From f9f02662ffb954b44193f57fe0596dc3c0d26608 Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Wed, 10 Sep 2025 22:24:20 +0800 Subject: [PATCH 01/10] only keep esp32 flag .go --- .../board_adafruit-esp32-feather-v2.go | 125 - emb/machine/board_ae_rp2040.go | 86 - emb/machine/board_arduino.go | 40 - emb/machine/board_arduino_leonardo.go | 39 - emb/machine/board_arduino_mega1280.go | 104 - emb/machine/board_arduino_mega2560.go | 165 -- emb/machine/board_arduino_mkr1000.go | 91 - emb/machine/board_arduino_mkrwifi1010.go | 124 - emb/machine/board_arduino_nano.go | 40 - emb/machine/board_arduino_nano33.go | 135 - emb/machine/board_arduino_zero.go | 102 - emb/machine/board_atmega328p.go | 42 - emb/machine/board_atmega328pb.go | 51 - emb/machine/board_atsamd21.go | 76 - emb/machine/board_atsame54-xpro.go | 293 -- emb/machine/board_badger2040-w.go | 95 - emb/machine/board_badger2040.go | 94 - emb/machine/board_bluemicro840.go | 80 - emb/machine/board_bluepill.go | 110 - emb/machine/board_btt_skr_pico.go | 121 - emb/machine/board_challenger_rp2040.go | 93 - emb/machine/board_circuitplay_bluefruit.go | 95 - emb/machine/board_circuitplay_express.go | 119 - emb/machine/board_clue_alpha.go | 125 - emb/machine/board_digispark.go | 19 - emb/machine/board_elecrow-rp2040-w5.go | 94 - emb/machine/board_elecrow-rp2350-w5.go | 94 - emb/machine/board_esp-c3-32s-kit.go | 40 - emb/machine/board_esp32-c3-devkit-rust-1.go | 81 - emb/machine/board_esp32-coreboard-v2.go | 88 - emb/machine/board_esp32c3-12f.go | 54 - emb/machine/board_esp32c3-supermini.go | 57 - emb/machine/board_fe310.go | 38 - emb/machine/board_feather-m0-express.go | 102 - emb/machine/board_feather-m0.go | 97 - emb/machine/board_feather-m4-can.go | 138 - emb/machine/board_feather-m4.go | 96 - emb/machine/board_feather-nrf52840-sense.go | 105 - emb/machine/board_feather-nrf52840.go | 105 - emb/machine/board_feather-stm32f405.go | 255 -- emb/machine/board_feather_rp2040.go | 82 - emb/machine/board_gemma-m0.go | 97 - emb/machine/board_gnse.go | 88 - emb/machine/board_gopher-badge.go | 90 - emb/machine/board_grandcentral-m4.go | 267 -- emb/machine/board_hifive1b.go | 61 - emb/machine/board_hifive1b_baremetal.go | 12 - emb/machine/board_hw-651.go | 77 - emb/machine/board_itsybitsy-m0.go | 110 - emb/machine/board_itsybitsy-m4.go | 94 - emb/machine/board_itsybitsy-nrf52840.go | 99 - emb/machine/board_k210.go | 354 --- emb/machine/board_kb2040.go | 84 - emb/machine/board_lgt92.go | 97 - emb/machine/board_lorae5.go | 97 - emb/machine/board_m5paper.go | 112 - emb/machine/board_m5stack.go | 124 - emb/machine/board_m5stack_core2.go | 115 - emb/machine/board_m5stamp_c3.go | 51 - emb/machine/board_m5stick_c.go | 117 - emb/machine/board_macropad-rp2040.go | 87 - emb/machine/board_maixbit.go | 74 - emb/machine/board_maixbit_baremetal.go | 15 - emb/machine/board_makerfabs-esp32c3spi35.go | 103 - emb/machine/board_matrixportal-m4.go | 200 -- emb/machine/board_mch2022.go | 28 - emb/machine/board_mdbt50qrx.go | 40 - emb/machine/board_metro-m4-airlift.go | 136 - emb/machine/board_microbit-v2.go | 119 - emb/machine/board_microbit.go | 78 - emb/machine/board_mksnanov3.go | 142 - emb/machine/board_nano-33-ble.go | 128 - emb/machine/board_nano-rp2040.go | 126 - emb/machine/board_nicenano.go | 79 - emb/machine/board_nodemcu.go | 35 - emb/machine/board_nrf51.go | 43 - emb/machine/board_nrf52840-mdk-usb-dongle.go | 48 - emb/machine/board_nrf52840-mdk.go | 43 - emb/machine/board_nrf52840.go | 55 - emb/machine/board_nrf52840_generic.go | 25 - emb/machine/board_nucleof103rb.go | 55 - emb/machine/board_nucleof722ze.go | 68 - emb/machine/board_nucleol031k6.go | 98 - emb/machine/board_nucleol432kc.go | 100 - emb/machine/board_nucleol476rg.go | 105 - emb/machine/board_nucleol552ze.go | 60 - emb/machine/board_nucleowl55jc.go | 96 - emb/machine/board_p1am-100.go | 140 - emb/machine/board_particle_argon.go | 106 - emb/machine/board_particle_boron.go | 109 - emb/machine/board_particle_xenon.go | 95 - emb/machine/board_pca10031.go | 41 - emb/machine/board_pca10040.go | 55 - emb/machine/board_pca10056.go | 65 - emb/machine/board_pca10059.go | 59 - emb/machine/board_pga2350.go | 98 - emb/machine/board_pico.go | 88 - emb/machine/board_pico2.go | 88 - emb/machine/board_pico_plus2.go | 93 - emb/machine/board_pinetime.go | 60 - emb/machine/board_pybadge.go | 162 -- emb/machine/board_pygamer.go | 133 - emb/machine/board_pyportal.go | 165 -- emb/machine/board_qtpy.go | 102 - emb/machine/board_qtpy_esp32c3.go | 60 - emb/machine/board_qtpy_rp2040.go | 93 - emb/machine/board_rak4631.go | 86 - emb/machine/board_reelboard.go | 74 - emb/machine/board_stm32f469disco.go | 79 - emb/machine/board_stm32f4disco.go | 106 - emb/machine/board_swan.go | 62 - emb/machine/board_teensy36.go | 103 - emb/machine/board_teensy40.go | 390 --- emb/machine/board_teensy41.go | 319 --- emb/machine/board_thingplus_rp2040.go | 103 - emb/machine/board_thumby.go | 76 - emb/machine/board_tiny2350.go | 82 - emb/machine/board_trinket.go | 88 - emb/machine/board_trinkey_qt2040.go | 62 - emb/machine/board_tufty2040.go | 85 - emb/machine/board_waveshare-rp2040-zero.go | 104 - emb/machine/board_waveshare_rp2040_tiny.go | 121 - emb/machine/board_wioterminal.go | 432 --- emb/machine/board_x9pro.go | 30 - emb/machine/board_xiao-ble.go | 111 - emb/machine/board_xiao-esp32c3.go | 53 - emb/machine/board_xiao-rp2040.go | 90 - emb/machine/board_xiao.go | 103 - emb/machine/buffer_atmega.go | 5 - emb/machine/buffer_generic.go | 5 - emb/machine/deviceid.go | 17 - emb/machine/flash.go | 77 - emb/machine/i2s.go | 80 - emb/machine/machine_atmega.go | 340 --- emb/machine/machine_atmega1280.go | 937 ------- emb/machine/machine_atmega1284p.go | 81 - emb/machine/machine_atmega2560.go | 141 - emb/machine/machine_atmega328.go | 548 ---- emb/machine/machine_atmega328p.go | 60 - emb/machine/machine_atmega328pb.go | 119 - emb/machine/machine_atmega32u4.go | 76 - emb/machine/machine_atsam.go | 31 - emb/machine/machine_atsamd21.go | 2090 --------------- emb/machine/machine_atsamd21_simulator.go | 45 - emb/machine/machine_atsamd21_usb.go | 664 ----- emb/machine/machine_atsamd21e18.go | 359 --- emb/machine/machine_atsamd21g18.go | 606 ----- emb/machine/machine_atsamd51.go | 2358 ----------------- emb/machine/machine_atsamd51_usb.go | 495 ---- emb/machine/machine_atsamd51g19.go | 98 - emb/machine/machine_atsamd51j19.go | 110 - emb/machine/machine_atsamd51j20.go | 110 - emb/machine/machine_atsamd51p19.go | 124 - emb/machine/machine_atsamd51p20.go | 124 - emb/machine/machine_atsame51j19.go | 110 - emb/machine/machine_atsame54p20.go | 124 - emb/machine/machine_atsame5x_can.go | 478 ---- emb/machine/machine_attiny1616.go | 52 - emb/machine/machine_attiny85.go | 23 - emb/machine/machine_avr.go | 150 -- emb/machine/machine_avrtiny.go | 62 - emb/machine/machine_cortexm.go | 10 - emb/machine/machine_fe310.go | 370 --- emb/machine/machine_gameboyadvance.go | 64 - emb/machine/machine_generic_peripherals.go | 14 - emb/machine/machine_k210.go | 661 ----- emb/machine/machine_mimxrt1062.go | 1064 -------- emb/machine/machine_mimxrt1062_i2c.go | 642 ----- emb/machine/machine_mimxrt1062_spi.go | 254 -- emb/machine/machine_mimxrt1062_uart.go | 303 --- emb/machine/machine_nrf.go | 449 ---- emb/machine/machine_nrf51.go | 278 -- emb/machine/machine_nrf52.go | 71 - emb/machine/machine_nrf52833.go | 92 - emb/machine/machine_nrf52840.go | 110 - .../machine_nrf52840_enter_bootloader.go | 38 - emb/machine/machine_nrf52840_lfxtal_false.go | 5 - emb/machine/machine_nrf52840_lfxtal_true.go | 5 - emb/machine/machine_nrf52840_simulator.go | 60 - emb/machine/machine_nrf52840_usb.go | 381 --- .../machine_nrf52840_usb_reset_bossa.go | 9 - .../machine_nrf52840_usb_reset_none.go | 8 - emb/machine/machine_nrf52840_usb_reset_uf2.go | 9 - emb/machine/machine_nrf528xx.go | 259 -- emb/machine/machine_nrf52xxx.go | 546 ---- emb/machine/machine_nrf5x.go | 126 - emb/machine/machine_nrf_bare.go | 9 - emb/machine/machine_nrf_sd.go | 59 - emb/machine/machine_nxpmk66f18.go | 291 -- emb/machine/machine_nxpmk66f18_uart.go | 309 --- emb/machine/machine_rp2.go | 137 - emb/machine/machine_rp2040_rom.go | 254 -- emb/machine/machine_rp2040_rtc.go | 240 -- emb/machine/machine_rp2040_simulator.go | 96 - emb/machine/machine_rp2040_usb.go | 148 -- ...e_rp2040_usb_fix_usb_device_enumeration.go | 120 - emb/machine/machine_rp2350_rom.go | 560 ---- emb/machine/machine_rp2350_usb.go | 151 -- emb/machine/machine_rp2_2040.go | 223 -- emb/machine/machine_rp2_2350.go | 224 -- emb/machine/machine_rp2_2350a.go | 14 - emb/machine/machine_rp2_2350b.go | 48 - emb/machine/machine_rp2_adc.go | 114 - emb/machine/machine_rp2_clocks.go | 236 -- emb/machine/machine_rp2_flash.go | 111 - emb/machine/machine_rp2_gpio.go | 282 -- emb/machine/machine_rp2_i2c.go | 639 ----- emb/machine/machine_rp2_pins.go | 37 - emb/machine/machine_rp2_pll.go | 279 -- emb/machine/machine_rp2_pwm.go | 420 --- emb/machine/machine_rp2_resets.go | 31 - emb/machine/machine_rp2_rng.go | 41 - emb/machine/machine_rp2_spi.go | 404 --- emb/machine/machine_rp2_sync.go | 39 - emb/machine/machine_rp2_timer.go | 103 - emb/machine/machine_rp2_uart.go | 159 -- emb/machine/machine_rp2_usb.go | 304 --- emb/machine/machine_rp2_watchdog.go | 62 - emb/machine/machine_rp2_xosc.go | 47 - emb/machine/machine_stm32.go | 104 - emb/machine/machine_stm32_adc_f1.go | 90 - emb/machine/machine_stm32_adc_f4.go | 114 - emb/machine/machine_stm32_exti_afio.go | 27 - emb/machine/machine_stm32_exti_exti.go | 26 - emb/machine/machine_stm32_exti_syscfg.go | 27 - .../machine_stm32_exti_syscfg_noenable.go | 26 - emb/machine/machine_stm32_flash.go | 115 - emb/machine/machine_stm32_gpio_reva.go | 92 - emb/machine/machine_stm32_gpio_revb.go | 79 - emb/machine/machine_stm32_gpio_revb_mp.go | 86 - emb/machine/machine_stm32_i2c_reva.go | 436 --- emb/machine/machine_stm32_i2c_revb.go | 378 --- emb/machine/machine_stm32_iwdg.go | 66 - emb/machine/machine_stm32_moder_gpio.go | 164 -- emb/machine/machine_stm32_rng.go | 35 - emb/machine/machine_stm32_spi.go | 147 - emb/machine/machine_stm32_tim.go | 340 --- emb/machine/machine_stm32_tim_moder.go | 10 - emb/machine/machine_stm32_uart.go | 85 - emb/machine/machine_stm32f103.go | 739 ------ emb/machine/machine_stm32f4.go | 936 ------- emb/machine/machine_stm32f40x.go | 13 - emb/machine/machine_stm32f469.go | 13 - emb/machine/machine_stm32f7.go | 725 ----- emb/machine/machine_stm32f7x2.go | 70 - emb/machine/machine_stm32l0.go | 317 --- emb/machine/machine_stm32l0x1.go | 197 -- emb/machine/machine_stm32l0x2.go | 259 -- emb/machine/machine_stm32l4.go | 650 ----- emb/machine/machine_stm32l4x2.go | 36 - emb/machine/machine_stm32l4x5.go | 36 - emb/machine/machine_stm32l4x6.go | 36 - emb/machine/machine_stm32l5.go | 559 ---- emb/machine/machine_stm32l5x2.go | 68 - emb/machine/machine_stm32wlx.go | 553 ---- emb/machine/machine_tkey.go | 234 -- emb/machine/machine_tkey_rom.go | 59 - emb/machine/spi_tx.go | 61 - emb/machine/usb.go | 338 --- emb/machine/virt.go | 189 -- emb/machine/watchdog.go | 34 - 261 files changed, 44180 deletions(-) delete mode 100644 emb/machine/board_adafruit-esp32-feather-v2.go delete mode 100644 emb/machine/board_ae_rp2040.go delete mode 100644 emb/machine/board_arduino.go delete mode 100644 emb/machine/board_arduino_leonardo.go delete mode 100644 emb/machine/board_arduino_mega1280.go delete mode 100644 emb/machine/board_arduino_mega2560.go delete mode 100644 emb/machine/board_arduino_mkr1000.go delete mode 100644 emb/machine/board_arduino_mkrwifi1010.go delete mode 100644 emb/machine/board_arduino_nano.go delete mode 100644 emb/machine/board_arduino_nano33.go delete mode 100644 emb/machine/board_arduino_zero.go delete mode 100644 emb/machine/board_atmega328p.go delete mode 100644 emb/machine/board_atmega328pb.go delete mode 100644 emb/machine/board_atsamd21.go delete mode 100644 emb/machine/board_atsame54-xpro.go delete mode 100644 emb/machine/board_badger2040-w.go delete mode 100644 emb/machine/board_badger2040.go delete mode 100644 emb/machine/board_bluemicro840.go delete mode 100644 emb/machine/board_bluepill.go delete mode 100644 emb/machine/board_btt_skr_pico.go delete mode 100644 emb/machine/board_challenger_rp2040.go delete mode 100644 emb/machine/board_circuitplay_bluefruit.go delete mode 100644 emb/machine/board_circuitplay_express.go delete mode 100644 emb/machine/board_clue_alpha.go delete mode 100644 emb/machine/board_digispark.go delete mode 100644 emb/machine/board_elecrow-rp2040-w5.go delete mode 100644 emb/machine/board_elecrow-rp2350-w5.go delete mode 100644 emb/machine/board_esp-c3-32s-kit.go delete mode 100644 emb/machine/board_esp32-c3-devkit-rust-1.go delete mode 100644 emb/machine/board_esp32-coreboard-v2.go delete mode 100644 emb/machine/board_esp32c3-12f.go delete mode 100644 emb/machine/board_esp32c3-supermini.go delete mode 100644 emb/machine/board_fe310.go delete mode 100644 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emb/machine/board_nano-33-ble.go delete mode 100644 emb/machine/board_nano-rp2040.go delete mode 100644 emb/machine/board_nicenano.go delete mode 100644 emb/machine/board_nodemcu.go delete mode 100644 emb/machine/board_nrf51.go delete mode 100644 emb/machine/board_nrf52840-mdk-usb-dongle.go delete mode 100644 emb/machine/board_nrf52840-mdk.go delete mode 100644 emb/machine/board_nrf52840.go delete mode 100644 emb/machine/board_nrf52840_generic.go delete mode 100644 emb/machine/board_nucleof103rb.go delete mode 100644 emb/machine/board_nucleof722ze.go delete mode 100644 emb/machine/board_nucleol031k6.go delete mode 100644 emb/machine/board_nucleol432kc.go delete mode 100644 emb/machine/board_nucleol476rg.go delete mode 100644 emb/machine/board_nucleol552ze.go delete mode 100644 emb/machine/board_nucleowl55jc.go delete mode 100644 emb/machine/board_p1am-100.go delete mode 100644 emb/machine/board_particle_argon.go delete mode 100644 emb/machine/board_particle_boron.go delete mode 100644 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a/emb/machine/board_adafruit-esp32-feather-v2.go b/emb/machine/board_adafruit-esp32-feather-v2.go deleted file mode 100644 index f971dca..0000000 --- a/emb/machine/board_adafruit-esp32-feather-v2.go +++ /dev/null @@ -1,125 +0,0 @@ -//go:build adafruit_esp32_feather_v2 - -package machine - -const GPIO20 Pin = 20 - -const ( - IO0 = GPIO0 - IO2 = GPIO2 - IO4 = GPIO4 - IO5 = GPIO5 - IO7 = GPIO7 - IO8 = GPIO8 - IO12 = GPIO12 - IO13 = GPIO13 - IO14 = GPIO14 - IO15 = GPIO15 - IO19 = GPIO19 - IO20 = GPIO20 - IO21 = GPIO21 - IO22 = GPIO22 - IO25 = GPIO25 - IO26 = GPIO26 - IO27 = GPIO27 - IO32 = GPIO32 - IO33 = GPIO33 - IO34 = GPIO34 - IO35 = GPIO35 - IO36 = GPIO36 - IO37 = GPIO37 - IO38 = GPIO38 - IO39 = GPIO39 -) - -// Digital pins -const ( - D12 = IO12 - D13 = IO13 - D14 = IO14 - D15 = IO15 - D27 = IO27 - D32 = IO32 - D33 = IO33 - D37 = IO37 -) - -// Analog pins -const ( - A0 = IO26 - A1 = IO25 - A2 = IO34 - A3 = IO39 - A4 = IO36 - A5 = IO4 -) - -// Built-in LEDs and Button -const ( - WS2812 = IO0 - NEOPIXEL = WS2812 - NEOPIXEL_I2C_POWER = IO2 - LED = IO13 - BUTTON = IO38 -) - -// SPI pins -const ( - SPI_SCK_PIN = IO5 - SPI_MOSI_PIN = IO19 - SPI_MISO_PIN = IO21 - - SPI_SDO_PIN = SPI_MOSI_PIN - SPI_SDI_PIN = SPI_MISO_PIN - - // Silk labels - SCK = SPI_SCK_PIN - MO = SPI_MOSI_PIN - MI = SPI_MISO_PIN -) - -// I2C pins -const ( - I2C_SCL_PIN = IO20 - I2C_SDA_PIN = IO22 - - // Silk labels - SCL = I2C_SCL_PIN - SDA = I2C_SDA_PIN -) - -// ADC pins -const ( - ADC1_0 = IO36 - ADC1_1 = IO37 - ADC1_2 = IO38 - ADC1_3 = IO39 - ADC1_4 = IO32 - ADC1_5 = IO33 - ADC1_6 = IO34 - ADC1_7 = IO35 - - ADC2_0 = IO4 - ADC2_1 = IO0 - ADC2_2 = IO2 - ADC2_3 = IO15 - ADC2_4 = IO13 - ADC2_5 = IO12 - ADC2_6 = IO14 - ADC2_7 = IO27 - ADC2_8 = IO25 - ADC2_9 = IO26 -) - -// UART pins -const ( - UART_TX_PIN = IO19 - UART_RX_PIN = IO22 - - UART2_TX_PIN = IO8 - UART2_RX_PIN = IO7 - - // Silk labels - RX = UART2_RX_PIN - TX = UART2_TX_PIN -) diff --git a/emb/machine/board_ae_rp2040.go b/emb/machine/board_ae_rp2040.go deleted file mode 100644 index 716cf72..0000000 --- a/emb/machine/board_ae_rp2040.go +++ /dev/null @@ -1,86 +0,0 @@ -//go:build ae_rp2040 - -package machine - -// GPIO pins -const ( - GP0 Pin = GPIO0 - GP1 Pin = GPIO1 - GP2 Pin = GPIO2 - GP3 Pin = GPIO3 - GP4 Pin = GPIO4 - GP5 Pin = GPIO5 - GP6 Pin = GPIO6 - GP7 Pin = GPIO7 - GP8 Pin = GPIO8 - GP9 Pin = GPIO9 - GP10 Pin = GPIO10 - GP11 Pin = GPIO11 - GP12 Pin = GPIO12 - GP13 Pin = GPIO13 - GP14 Pin = GPIO14 - GP15 Pin = GPIO15 - GP16 Pin = GPIO16 - GP17 Pin = GPIO17 - GP18 Pin = GPIO18 - GP19 Pin = GPIO19 - GP20 Pin = GPIO20 - GP21 Pin = GPIO21 - GP22 Pin = GPIO22 - GP26 Pin = GPIO26 - GP27 Pin = GPIO27 - GP28 Pin = GPIO28 - GP29 Pin = GPIO29 - - // Onboard crystal oscillator frequency, in MHz. - xoscFreq = 12 // MHz -) - -// I2C Default pins on Raspberry Pico. -const ( - I2C0_SDA_PIN = GP4 - I2C0_SCL_PIN = GP5 - - I2C1_SDA_PIN = GP2 - I2C1_SCL_PIN = GP3 -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO18 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO19 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO16 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO10 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO11 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO12 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO8 - UART1_RX_PIN = GPIO9 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "AE-RP2040" - usb_STRING_MANUFACTURER = "AKIZUKI DENSHI" -) - -var ( - usb_VID uint16 = 0x2E8A - usb_PID uint16 = 0x000A -) diff --git a/emb/machine/board_arduino.go b/emb/machine/board_arduino.go deleted file mode 100644 index a66889a..0000000 --- a/emb/machine/board_arduino.go +++ /dev/null @@ -1,40 +0,0 @@ -//go:build arduino - -package machine - -// Digital pins, marked as plain numbers on the board. -const ( - D0 = PD0 // RX - D1 = PD1 // TX - D2 = PD2 - D3 = PD3 - D4 = PD4 - D5 = PD5 - D6 = PD6 - D7 = PD7 - D8 = PB0 - D9 = PB1 - D10 = PB2 - D11 = PB3 - D12 = PB4 - D13 = PB5 -) - -// LED on the Arduino -const LED Pin = D13 - -// ADC on the Arduino -const ( - ADC0 Pin = PC0 - ADC1 Pin = PC1 - ADC2 Pin = PC2 - ADC3 Pin = PC3 - ADC4 Pin = PC4 // Used by TWI for SDA - ADC5 Pin = PC5 // Used by TWI for SCL -) - -// UART pins -const ( - UART_TX_PIN Pin = PD1 - UART_RX_PIN Pin = PD0 -) diff --git a/emb/machine/board_arduino_leonardo.go b/emb/machine/board_arduino_leonardo.go deleted file mode 100644 index 01f9570..0000000 --- a/emb/machine/board_arduino_leonardo.go +++ /dev/null @@ -1,39 +0,0 @@ -//go:build arduino_leonardo - -package machine - -// Return the current CPU frequency in hertz. -func CPUFrequency() uint32 { - return 16000000 -} - -// Digital pins, marked as plain numbers on the board. -const ( - D0 = PD2 // RX - D1 = PD3 // TX - D2 = PD1 - D3 = PD0 - D4 = PD4 - D5 = PC6 - D6 = PD7 - D7 = PE6 - D8 = PB4 - D9 = PB5 - D10 = PB6 - D11 = PB7 - D12 = PD6 - D13 = PC7 -) - -// LED on the Arduino -const LED Pin = D13 - -// ADC on the Arduino -const ( - ADC0 Pin = PF7 - ADC1 Pin = PF6 - ADC2 Pin = PF5 - ADC3 Pin = PF4 - ADC4 Pin = PF1 - ADC5 Pin = PF0 -) diff --git a/emb/machine/board_arduino_mega1280.go b/emb/machine/board_arduino_mega1280.go deleted file mode 100644 index 7bf6090..0000000 --- a/emb/machine/board_arduino_mega1280.go +++ /dev/null @@ -1,104 +0,0 @@ -//go:build arduino_mega1280 - -package machine - -// Return the current CPU frequency in hertz. -func CPUFrequency() uint32 { - return 16000000 -} - -const ( - A0 Pin = PF0 - A1 Pin = PF1 - A2 Pin = PF2 - A3 Pin = PF3 - A4 Pin = PF4 - A5 Pin = PF5 - A6 Pin = PF6 - A7 Pin = PF7 - A8 Pin = PK0 - A9 Pin = PK1 - A10 Pin = PK2 - A11 Pin = PK3 - A12 Pin = PK4 - A13 Pin = PK5 - A14 Pin = PK6 - A15 Pin = PK7 - - // Analog Input - ADC0 Pin = PF0 - ADC1 Pin = PF1 - ADC2 Pin = PF2 - ADC3 Pin = PF3 - ADC4 Pin = PF4 - ADC5 Pin = PF5 - ADC6 Pin = PF6 - ADC7 Pin = PF7 - ADC8 Pin = PK0 - ADC9 Pin = PK1 - ADC10 Pin = PK2 - ADC11 Pin = PK3 - ADC12 Pin = PK4 - ADC13 Pin = PK5 - ADC14 Pin = PK6 - ADC15 Pin = PK7 - - // Digital pins - D0 Pin = PE0 - D1 Pin = PE1 - D2 Pin = PE4 - D3 Pin = PE5 - D4 Pin = PG5 - D5 Pin = PE3 - D6 Pin = PH3 - D7 Pin = PH4 - D8 Pin = PH5 - D9 Pin = PH6 - D10 Pin = PB4 - D11 Pin = PB5 - D12 Pin = PB6 - D13 Pin = PB7 - D14 Pin = PJ1 - D15 Pin = PJ0 - D16 Pin = PH1 - D17 Pin = PH0 - D18 Pin = PD3 - D19 Pin = PD2 - D20 Pin = PD1 - D21 Pin = PD0 - D22 Pin = PA0 - D23 Pin = PA1 - D24 Pin = PA2 - D25 Pin = PA3 - D26 Pin = PA4 - D27 Pin = PA5 - D28 Pin = PA6 - D29 Pin = PA7 - D30 Pin = PC7 - D31 Pin = PC6 - D32 Pin = PC5 - D33 Pin = PC4 - D34 Pin = PC3 - D35 Pin = PC2 - D36 Pin = PC1 - D37 Pin = PC0 - D38 Pin = PD7 - D39 Pin = PG2 - D40 Pin = PG1 - D41 Pin = PG0 - D42 Pin = PL7 - D43 Pin = PL6 - D44 Pin = PL5 - D45 Pin = PL4 - D46 Pin = PL3 - D47 Pin = PL2 - D48 Pin = PL1 - D49 Pin = PL0 - D50 Pin = PB3 - D51 Pin = PB2 - D52 Pin = PB1 - D53 Pin = PB0 - - AREF Pin = NoPin - LED Pin = PB7 -) diff --git a/emb/machine/board_arduino_mega2560.go b/emb/machine/board_arduino_mega2560.go deleted file mode 100644 index 2e4aefd..0000000 --- a/emb/machine/board_arduino_mega2560.go +++ /dev/null @@ -1,165 +0,0 @@ -//go:build arduino_mega2560 - -package machine - -import ( - "device/avr" - "runtime/interrupt" -) - -// Return the current CPU frequency in hertz. -func CPUFrequency() uint32 { - return 16000000 -} - -const ( - A0 Pin = PF0 - A1 Pin = PF1 - A2 Pin = PF2 - A3 Pin = PF3 - A4 Pin = PF4 - A5 Pin = PF5 - A6 Pin = PF6 - A7 Pin = PF7 - A8 Pin = PK0 - A9 Pin = PK1 - A10 Pin = PK2 - A11 Pin = PK3 - A12 Pin = PK4 - A13 Pin = PK5 - A14 Pin = PK6 - A15 Pin = PK7 - - // Analog Input - ADC0 Pin = PF0 - ADC1 Pin = PF1 - ADC2 Pin = PF2 - ADC3 Pin = PF3 - ADC4 Pin = PF4 - ADC5 Pin = PF5 - ADC6 Pin = PF6 - ADC7 Pin = PF7 - ADC8 Pin = PK0 - ADC9 Pin = PK1 - ADC10 Pin = PK2 - ADC11 Pin = PK3 - ADC12 Pin = PK4 - ADC13 Pin = PK5 - ADC14 Pin = PK6 - ADC15 Pin = PK7 - - // Digital pins - D0 Pin = PE0 - D1 Pin = PE1 - D2 Pin = PE4 - D3 Pin = PE5 - D4 Pin = PG5 - D5 Pin = PE3 - D6 Pin = PH3 - D7 Pin = PH4 - D8 Pin = PH5 - D9 Pin = PH6 - D10 Pin = PB4 - D11 Pin = PB5 - D12 Pin = PB6 - D13 Pin = PB7 - D14 Pin = PJ1 // TX3 - D15 Pin = PJ0 // RX3 - D16 Pin = PH1 // TX2 - D17 Pin = PH0 // RX2 - D18 Pin = PD3 // TX1 - D19 Pin = PD2 // RX1 - D20 Pin = PD1 - D21 Pin = PD0 - D22 Pin = PA0 - D23 Pin = PA1 - D24 Pin = PA2 - D25 Pin = PA3 - D26 Pin = PA4 - D27 Pin = PA5 - D28 Pin = PA6 - D29 Pin = PA7 - D30 Pin = PC7 - D31 Pin = PC6 - D32 Pin = PC5 - D33 Pin = PC4 - D34 Pin = PC3 - D35 Pin = PC2 - D36 Pin = PC1 - D37 Pin = PC0 - D38 Pin = PD7 - D39 Pin = PG2 - D40 Pin = PG1 - D41 Pin = PG0 - D42 Pin = PL7 - D43 Pin = PL6 - D44 Pin = PL5 - D45 Pin = PL4 - D46 Pin = PL3 - D47 Pin = PL2 - D48 Pin = PL1 - D49 Pin = PL0 - D50 Pin = PB3 - D51 Pin = PB2 - D52 Pin = PB1 - D53 Pin = PB0 - - AREF Pin = NoPin - LED Pin = PB7 -) - -// UART pins -const ( - UART_TX_PIN Pin = UART0_TX_PIN - UART_RX_PIN Pin = UART0_RX_PIN - UART0_TX_PIN Pin = D1 - UART0_RX_PIN Pin = D0 - UART1_TX_PIN Pin = D18 - UART1_RX_PIN Pin = D19 - UART2_TX_PIN Pin = D16 - UART2_RX_PIN Pin = D17 - UART3_TX_PIN Pin = D14 - UART3_RX_PIN Pin = D15 -) - -var ( - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - - dataReg: avr.UDR1, - baudRegH: avr.UBRR1H, - baudRegL: avr.UBRR1L, - statusRegA: avr.UCSR1A, - statusRegB: avr.UCSR1B, - statusRegC: avr.UCSR1C, - } - UART2 = &_UART2 - _UART2 = UART{ - Buffer: NewRingBuffer(), - - dataReg: avr.UDR2, - baudRegH: avr.UBRR2H, - baudRegL: avr.UBRR2L, - statusRegA: avr.UCSR2A, - statusRegB: avr.UCSR2B, - statusRegC: avr.UCSR2C, - } - UART3 = &_UART3 - _UART3 = UART{ - Buffer: NewRingBuffer(), - - dataReg: avr.UDR3, - baudRegH: avr.UBRR3H, - baudRegL: avr.UBRR3L, - statusRegA: avr.UCSR3A, - statusRegB: avr.UCSR3B, - statusRegC: avr.UCSR3C, - } -) - -func init() { - interrupt.New(irq_USART1_RX, _UART1.handleInterrupt) - interrupt.New(irq_USART2_RX, _UART2.handleInterrupt) - interrupt.New(irq_USART3_RX, _UART3.handleInterrupt) -} diff --git a/emb/machine/board_arduino_mkr1000.go b/emb/machine/board_arduino_mkr1000.go deleted file mode 100644 index f513012..0000000 --- a/emb/machine/board_arduino_mkr1000.go +++ /dev/null @@ -1,91 +0,0 @@ -//go:build arduino_mkr1000 - -// This contains the pin mappings for the Arduino MKR1000 board. -// -// For more information, see: https://store.arduino.cc/usa/arduino-mkr1000-with-headers-mounted -package machine - -// used to reset into bootloader -const resetMagicValue = 0x07738135 - -// GPIO Pins -const ( - D0 Pin = PA22 // PWM available - D1 Pin = PA23 // PWM available - D2 Pin = PA10 // PWM available - D3 Pin = PA11 // PWM available - D4 Pin = PB10 // PWM available - D5 Pin = PB11 // PWM available - - D6 Pin = PA20 // PWM available - D7 Pin = PA21 // PWM available - D8 Pin = PA16 // PWM available - D9 Pin = PA17 - D10 Pin = PA19 // PWM available - D11 Pin = PA08 // SDA - D12 Pin = PA09 // PWM available, SCL - D13 Pin = PB23 // RX - D14 Pin = PB22 // TX - - RX0 Pin = PB23 // UART2 RX - TX1 Pin = PB22 // UART2 TX -) - -// Analog pins -const ( - A0 Pin = PA02 // ADC0/AIN[0] - A1 Pin = PB02 // AIN[10] - A2 Pin = PB03 // AIN[11] - A3 Pin = PA04 // AIN[04] - A4 Pin = PA05 // AIN[05] - A5 Pin = PA06 // AIN[06] - A6 Pin = PA07 // AIN[07] -) - -const ( - LED = D6 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN Pin = PA24 - USBCDC_DP_PIN Pin = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN Pin = PB22 - UART_RX_PIN Pin = PB23 -) - -// I2C pins -const ( - SDA_PIN Pin = D11 // SDA - SCL_PIN Pin = D12 // SCL -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = D9 // SCK: S1 - SPI0_SDO_PIN Pin = D8 // SDO: S1 - SPI0_SDI_PIN Pin = D10 // SDI: S1 -) - -// I2S pins -const ( - I2S_SCK_PIN Pin = PA10 - I2S_SDO_PIN Pin = PA07 - I2S_SDI_PIN = NoPin - I2S_WS_PIN = NoPin // TODO: figure out what this is on Arduino MKR1000 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Arduino MKR1000" - usb_STRING_MANUFACTURER = "Arduino" -) - -var ( - usb_VID uint16 = 0x2341 - usb_PID uint16 = 0x804e -) diff --git a/emb/machine/board_arduino_mkrwifi1010.go b/emb/machine/board_arduino_mkrwifi1010.go deleted file mode 100644 index c68da9b..0000000 --- a/emb/machine/board_arduino_mkrwifi1010.go +++ /dev/null @@ -1,124 +0,0 @@ -//go:build arduino_mkrwifi1010 - -// This contains the pin mappings for the Arduino MKR WiFi 1010 board. -// -// For more information, see: https://store.arduino.cc/usa/mkr-wifi-1010 -package machine - -// used to reset into bootloader -const resetMagicValue = 0x07738135 - -// GPIO Pins -const ( - D0 Pin = PA22 // PWM available - D1 Pin = PA23 // PWM available - D2 Pin = PA10 // PWM available - D3 Pin = PA11 // PWM available - D4 Pin = PB10 // PWM available - D5 Pin = PB11 // PWM available - - D6 Pin = PA20 // PWM available - D7 Pin = PA21 // PWM available - D8 Pin = PA16 // PWM available - D9 Pin = PA17 - D10 Pin = PA19 // PWM available - D11 Pin = PA08 // SDA - D12 Pin = PA09 // PWM available, SCL - D13 Pin = PB23 // RX - D14 Pin = PB22 // TX - - RX0 Pin = PB23 // UART1 RX - TX1 Pin = PB22 // UART1 TX -) - -// Analog pins -const ( - A0 Pin = PA02 // ADC0/AIN[0] - A1 Pin = PB02 // AIN[10] - A2 Pin = PB03 // AIN[11] - A3 Pin = PA04 // AIN[04] - A4 Pin = PA05 // AIN[05] - A5 Pin = PA06 // AIN[06] - A6 Pin = PA07 // AIN[07] -) - -const ( - LED = D6 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN Pin = PA24 - USBCDC_DP_PIN Pin = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN Pin = PB22 - UART_RX_PIN Pin = PB23 -) - -// I2C pins -const ( - SDA_PIN Pin = D11 // SDA - SCL_PIN Pin = D12 // SCL -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = D9 // SCK: S1 - SPI0_SDO_PIN Pin = D8 // SDO: S1 - SPI0_SDI_PIN Pin = D10 // SDI: S1 -) - -// I2S pins -const ( - I2S_SCK_PIN Pin = PA10 - I2S_SDO_PIN Pin = PA07 - I2S_SDI_PIN = NoPin - I2S_WS_PIN = NoPin // TODO: figure out what this is on Arduino MKR WiFi 1010. -) - -// NINA-W102 Pins -const ( - NINA_SDO Pin = PA12 - NINA_SDI Pin = PA13 - NINA_CS Pin = PA14 - NINA_SCK Pin = PA15 - NINA_GPIO0 Pin = PA27 - NINA_RESETN Pin = PB08 - NINA_ACK Pin = PA28 - NINA_TX Pin = PA22 - NINA_RX Pin = PA23 -) - -// UART on the Arduino MKR WiFi 1010. -var UART1 = &sercomUSART5 - -// I2C on the Arduino MKR WiFi 1010. -var ( - I2C0 = sercomI2CM2 -) - -// SPI on the Arduino MKR WiFi 1010. -var ( - SPI0 = sercomSPIM1 - - SPI1 = sercomSPIM4 - NINA_SPI = SPI1 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Arduino MKR WiFi 1010" - usb_STRING_MANUFACTURER = "Arduino" -) - -var ( - usb_VID uint16 = 0x2341 - usb_PID uint16 = 0x8054 -) - -var ( - DefaultUART = UART1 -) diff --git a/emb/machine/board_arduino_nano.go b/emb/machine/board_arduino_nano.go deleted file mode 100644 index c677219..0000000 --- a/emb/machine/board_arduino_nano.go +++ /dev/null @@ -1,40 +0,0 @@ -//go:build arduino_nano - -package machine - -// Digital pins. -const ( - D0 = PD0 // RX0 - D1 = PD1 // TX1 - D2 = PD2 - D3 = PD3 - D4 = PD4 - D5 = PD5 - D6 = PD6 - D7 = PD7 - D8 = PB0 - D9 = PB1 - D10 = PB2 - D11 = PB3 - D12 = PB4 - D13 = PB5 -) - -// LED on the Arduino -const LED Pin = D13 - -// ADC on the Arduino -const ( - ADC0 Pin = PC0 - ADC1 Pin = PC1 - ADC2 Pin = PC2 - ADC3 Pin = PC3 - ADC4 Pin = PC4 // Used by TWI for SDA - ADC5 Pin = PC5 // Used by TWI for SCL -) - -// UART pins -const ( - UART_TX_PIN Pin = PD1 - UART_RX_PIN Pin = PD0 -) diff --git a/emb/machine/board_arduino_nano33.go b/emb/machine/board_arduino_nano33.go deleted file mode 100644 index 9232d38..0000000 --- a/emb/machine/board_arduino_nano33.go +++ /dev/null @@ -1,135 +0,0 @@ -//go:build arduino_nano33 - -// This contains the pin mappings for the Arduino Nano33 IoT board. -// -// For more information, see: https://store.arduino.cc/nano-33-iot -package machine - -// used to reset into bootloader -const resetMagicValue = 0x07738135 - -// GPIO Pins -const ( - RX0 Pin = PB23 // UART2 RX - TX1 Pin = PB22 // UART2 TX - - D2 Pin = PB10 // PWM available - D3 Pin = PB11 // PWM available - D4 Pin = PA07 - D5 Pin = PA05 // PWM available - D6 Pin = PA04 // PWM available - D7 Pin = PA06 - - D8 Pin = PA18 - D9 Pin = PA20 // PWM available - D10 Pin = PA21 // PWM available - D11 Pin = PA16 // PWM available - D12 Pin = PA19 // PWM available - - D13 Pin = PA17 -) - -// Analog pins -const ( - A0 Pin = PA02 // ADC/AIN[0] - A1 Pin = PB02 // ADC/AIN[10] - A2 Pin = PA11 // ADC/AIN[19] - A3 Pin = PA10 // ADC/AIN[18], - A4 Pin = PB08 // ADC/AIN[2], SCL: SERCOM2/PAD[1] - A5 Pin = PB09 // ADC/AIN[3], SDA: SERCOM2/PAD[1] - A6 Pin = PA09 // ADC/AIN[17] - A7 Pin = PB03 // ADC/AIN[11] -) - -const ( - LED = D13 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN Pin = PA24 - USBCDC_DP_PIN Pin = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN Pin = PA22 - UART_RX_PIN Pin = PA23 -) - -// UART1 on the Arduino Nano 33 connects to the onboard NINA-W102 WiFi chip. -var UART1 = &sercomUSART3 - -// UART2 on the Arduino Nano 33 connects to the normal TX/RX pins. -var UART2 = &sercomUSART5 - -// UART_NINA on the Arduino Nano 33 connects to the NINA HCI. -var UART_NINA = &sercomUSART2 - -// I2C pins -const ( - SDA_PIN Pin = A4 // SDA: SERCOM4/PAD[1] - SCL_PIN Pin = A5 // SCL: SERCOM4/PAD[1] -) - -// I2C on the Arduino Nano 33. -var ( - I2C0 = sercomI2CM4 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = D13 // SCK: SERCOM1/PAD[1] - SPI0_SDO_PIN Pin = D11 // SDO: SERCOM1/PAD[0] - SPI0_SDI_PIN Pin = D12 // SDI: SERCOM1/PAD[3] -) - -// SPI on the Arduino Nano 33. -var SPI0 = sercomSPIM1 - -// SPI1 is connected to the NINA-W102 chip on the Arduino Nano 33. -var ( - SPI1 = sercomSPIM2 - NINA_SPI = SPI1 -) - -// NINA-W102 Pins -const ( - NINA_SDO Pin = PA12 - NINA_SDI Pin = PA13 - NINA_CS Pin = PA14 - NINA_SCK Pin = PA15 - NINA_GPIO0 Pin = PA27 - NINA_RESETN Pin = PA08 - NINA_ACK Pin = PA28 - NINA_TX Pin = PA12 - NINA_RX Pin = PA13 - NINA_RTS Pin = PA14 - NINA_CTS Pin = PA15 -) - -// NINA-W102 settings -const ( - NINA_BAUDRATE = 912600 - NINA_RESET_INVERTED = true - NINA_SOFT_FLOWCONTROL = false -) - -// I2S pins -const ( - I2S_SCK_PIN Pin = PA10 - I2S_SDO_PIN Pin = PA08 - I2S_SDI_PIN = NoPin - I2S_WS_PIN = NoPin // TODO: figure out what this is on Arduino Nano 33. -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Arduino NANO 33 IoT" - usb_STRING_MANUFACTURER = "Arduino" -) - -var ( - usb_VID uint16 = 0x2341 - usb_PID uint16 = 0x8057 -) diff --git a/emb/machine/board_arduino_zero.go b/emb/machine/board_arduino_zero.go deleted file mode 100644 index 758fcb1..0000000 --- a/emb/machine/board_arduino_zero.go +++ /dev/null @@ -1,102 +0,0 @@ -//go:build sam && atsamd21 && arduino_zero - -package machine - -// used to reset into bootloader -const resetMagicValue = 0x07738135 - -// GPIO Pins - Digital Low -const ( - D0 = PA11 // RX - D1 = PA10 // TX - D2 = PA14 - D3 = PA09 // PWM available - D4 = PA08 // PWM available - D5 = PA15 // PWM available - D6 = PA20 // PWM available - D7 = PA21 -) - -// GPIO Pins - Digital High -const ( - D8 = PA06 // PWM available - D9 = PA07 // PWM available - D10 = PA18 // PWM available - D11 = PA16 // PWM available - D12 = PA19 // PWM available - D13 = PA17 // PWM available -) - -// ADC pins -const ( - AREF Pin = PA03 - ADC0 Pin = PA02 - ADC1 Pin = PB08 - ADC2 Pin = PB09 - ADC3 Pin = PA04 - ADC4 Pin = PA05 - ADC5 Pin = PB02 -) - -// LEDs on the Arduino Zero -const ( - LED = LED1 - LED1 Pin = D13 - LED2 Pin = PA27 // TX LED - LED3 Pin = PB03 // RX LED -) - -// SPI pins - EDBG connected -const ( - SPI0_SDO_PIN Pin = PA16 // MOSI: SERCOM1/PAD[0] - SPI0_SDI_PIN Pin = PA19 // MISO: SERCOM1/PAD[2] - SPI0_SCK_PIN Pin = PA17 // SCK: SERCOM1/PAD[3] -) - -// SPI pins (Legacy ICSP) -const ( - SPI1_SDO_PIN Pin = PB10 // MOSI: SERCOM4/PAD[2] - Pin 4 - SPI1_SDI_PIN Pin = PA12 // MISO: SERCOM4/PAD[0] - Pin 1 - SPI1_SCK_PIN Pin = PB11 // SCK: SERCOM4/PAD[3] - Pin 3 -) - -// I2C pins - EDBG connected -const ( - SDA_PIN Pin = PA22 // SDA: SERCOM3/PAD[0] - Pin 20 - SCL_PIN Pin = PA23 // SCL: SERCOM3/PAD[1] - Pin 21 -) - -// I2S pins - might not be exposed -const ( - I2S_SCK_PIN Pin = PA10 - I2S_SDO_PIN Pin = PA07 - I2S_SDI_PIN = NoPin - I2S_WS_PIN Pin = PA11 -) - -// UART0 pins - EDBG connected -const ( - UART_RX_PIN Pin = D0 - UART_TX_PIN Pin = D1 -) - -// 'native' USB port pins -const ( - USBCDC_DM_PIN Pin = PA24 - USBCDC_DP_PIN Pin = PA25 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Arduino Zero" - usb_STRING_MANUFACTURER = "Arduino LLC" - - usb_VID uint16 = 0x2341 - usb_PID uint16 = 0x804d -) - -// 32.768 KHz Crystal -const ( - XIN32 Pin = PA00 - XOUT32 Pin = PA01 -) diff --git a/emb/machine/board_atmega328p.go b/emb/machine/board_atmega328p.go deleted file mode 100644 index 234bf31..0000000 --- a/emb/machine/board_atmega328p.go +++ /dev/null @@ -1,42 +0,0 @@ -//go:build (avr && atmega328p) || arduino || arduino_nano - -package machine - -// Return the current CPU frequency in hertz. -func CPUFrequency() uint32 { - return 16000000 -} - -const ( - // Note: start at port B because there is no port A. - portB Pin = iota * 8 - portC - portD -) - -const ( - PB0 = portB + 0 - PB1 = portB + 1 // peripherals: Timer1 channel A - PB2 = portB + 2 // peripherals: Timer1 channel B - PB3 = portB + 3 // peripherals: Timer2 channel A - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 // peripherals: Timer2 channel B - PD4 = portD + 4 - PD5 = portD + 5 // peripherals: Timer0 channel B - PD6 = portD + 6 // peripherals: Timer0 channel A - PD7 = portD + 7 -) diff --git a/emb/machine/board_atmega328pb.go b/emb/machine/board_atmega328pb.go deleted file mode 100644 index e3e45f0..0000000 --- a/emb/machine/board_atmega328pb.go +++ /dev/null @@ -1,51 +0,0 @@ -//go:build avr && atmega328pb - -package machine - -// Return the current CPU frequency in hertz. -func CPUFrequency() uint32 { - return 16000000 -} - -const ( - // Note: start at port B because there is no port A. - portB Pin = iota * 8 - portC - portD - portE -) - -const ( - PB0 = portB + 0 - PB1 = portB + 1 // peripherals: Timer1 channel A - PB2 = portB + 2 // peripherals: Timer1 channel B - PB3 = portB + 3 // peripherals: Timer2 channel A - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 // peripherals: Timer2 channel B - PD4 = portD + 4 - PD5 = portD + 5 // peripherals: Timer0 channel B - PD6 = portD + 6 // peripherals: Timer0 channel A - PD7 = portD + 7 - PE0 = portE + 0 - PE1 = portE + 1 - PE2 = portE + 2 - PE3 = portE + 3 - PE4 = portE + 4 - PE5 = portE + 5 - PE6 = portE + 6 - PE7 = portE + 7 -) diff --git a/emb/machine/board_atsamd21.go b/emb/machine/board_atsamd21.go deleted file mode 100644 index 8782249..0000000 --- a/emb/machine/board_atsamd21.go +++ /dev/null @@ -1,76 +0,0 @@ -//go:build (sam && atsamd21) || arduino_nano33 || circuitplay_express - -package machine - -// Return the current CPU frequency in hertz. -func CPUFrequency() uint32 { - return 48000000 -} - -// Hardware pins -const ( - PA00 Pin = 0 // peripherals: TCC2 channel 0 - PA01 Pin = 1 // peripherals: TCC2 channel 1 - PA02 Pin = 2 - PA03 Pin = 3 - PA04 Pin = 4 // peripherals: TCC0 channel 0 - PA05 Pin = 5 // peripherals: TCC0 channel 1 - PA06 Pin = 6 // peripherals: TCC1 channel 0 - PA07 Pin = 7 // peripherals: TCC1 channel 1 - PA08 Pin = 8 // peripherals: TCC0 channel 0, TCC1 channel 2 - PA09 Pin = 9 // peripherals: TCC0 channel 1, TCC1 channel 3 - PA10 Pin = 10 // peripherals: TCC1 channel 0, TCC0 channel 2 - PA11 Pin = 11 // peripherals: TCC1 channel 1, TCC0 channel 3 - PA12 Pin = 12 // peripherals: TCC2 channel 0, TCC0 channel 2 - PA13 Pin = 13 // peripherals: TCC2 channel 1, TCC0 channel 3 - PA14 Pin = 14 // peripherals: TCC0 channel 0 - PA15 Pin = 15 // peripherals: TCC0 channel 1 - PA16 Pin = 16 // peripherals: TCC2 channel 0, TCC0 channel 2 - PA17 Pin = 17 // peripherals: TCC2 channel 1, TCC0 channel 3 - PA18 Pin = 18 // peripherals: TCC0 channel 2 - PA19 Pin = 19 // peripherals: TCC0 channel 3 - PA20 Pin = 20 // peripherals: TCC0 channel 2 - PA21 Pin = 21 // peripherals: TCC0 channel 3 - PA22 Pin = 22 // peripherals: TCC0 channel 0 - PA23 Pin = 23 // peripherals: TCC0 channel 1 - PA24 Pin = 24 // peripherals: TCC1 channel 2 - PA25 Pin = 25 // peripherals: TCC1 channel 3 - PA26 Pin = 26 - PA27 Pin = 27 - PA28 Pin = 28 - PA29 Pin = 29 - PA30 Pin = 30 // peripherals: TCC1 channel 0 - PA31 Pin = 31 // peripherals: TCC1 channel 1 - PB00 Pin = 32 - PB01 Pin = 33 - PB02 Pin = 34 - PB03 Pin = 35 - PB04 Pin = 36 - PB05 Pin = 37 - PB06 Pin = 38 - PB07 Pin = 39 - PB08 Pin = 40 - PB09 Pin = 41 - PB10 Pin = 42 // peripherals: TCC0 channel 0 - PB11 Pin = 43 // peripherals: TCC0 channel 1 - PB12 Pin = 44 // peripherals: TCC0 channel 2 - PB13 Pin = 45 // peripherals: TCC0 channel 3 - PB14 Pin = 46 - PB15 Pin = 47 - PB16 Pin = 48 // peripherals: TCC0 channel 0 - PB17 Pin = 49 // peripherals: TCC0 channel 1 - PB18 Pin = 50 - PB19 Pin = 51 - PB20 Pin = 52 - PB21 Pin = 53 - PB22 Pin = 54 - PB23 Pin = 55 - PB24 Pin = 56 - PB25 Pin = 57 - PB26 Pin = 58 - PB27 Pin = 59 - PB28 Pin = 60 - PB29 Pin = 61 - PB30 Pin = 62 // peripherals: TCC0 channel 0, TCC1 channel 2 - PB31 Pin = 63 // peripherals: TCC0 channel 1, TCC1 channel 3 -) diff --git a/emb/machine/board_atsame54-xpro.go b/emb/machine/board_atsame54-xpro.go deleted file mode 100644 index ae1086d..0000000 --- a/emb/machine/board_atsame54-xpro.go +++ /dev/null @@ -1,293 +0,0 @@ -//go:build atsame54_xpro - -package machine - -import ( - "device/sam" -) - -// Definition for compatibility, but not used -const resetMagicValue = 0x00000000 - -const ( - LED = PC18 - BUTTON = PB31 -) - -const ( - // https://ww1.microchip.com/downloads/en/DeviceDoc/70005321A.pdf - - // Extension Header EXT1 - EXT1_PIN3_ADC_P = PB04 - EXT1_PIN4_ADC_N = PB05 - EXT1_PIN5_GPIO1 = PA06 - EXT1_PIN6_GPIO2 = PA07 - EXT1_PIN7_PWM_P = PB08 - EXT1_PIN8_PWM_N = PB09 - EXT1_PIN9_IRQ = PB07 - EXT1_PIN9_GPIO = PB07 - EXT1_PIN10_SPI_SS_B = PA27 - EXT1_PIN10_GPIO = PA27 - EXT1_PIN11_TWI_SDA = PA22 - EXT1_PIN12_TWI_SCL = PA23 - EXT1_PIN13_UART_RX = PA05 - EXT1_PIN14_UART_TX = PA04 - EXT1_PIN15_SPI_SS_A = PB28 - EXT1_PIN16_SPI_SDO = PB27 - EXT1_PIN17_SPI_SDI = PB29 - EXT1_PIN18_SPI_SCK = PB26 - - // Extension Header EXT2 - EXT2_PIN3_ADC_P = PB00 - EXT2_PIN4_ADC_N = PA03 - EXT2_PIN5_GPIO1 = PB01 - EXT2_PIN6_GPIO2 = PB06 - EXT2_PIN7_PWM_P = PB14 - EXT2_PIN8_PWM_N = PB15 - EXT2_PIN9_IRQ = PD00 - EXT2_PIN9_GPIO = PD00 - EXT2_PIN10_SPI_SS_B = PB02 - EXT2_PIN10_GPIO = PB02 - EXT2_PIN11_TWI_SDA = PD08 - EXT2_PIN12_TWI_SCL = PD09 - EXT2_PIN13_UART_RX = PB17 - EXT2_PIN14_UART_TX = PB16 - EXT2_PIN15_SPI_SS_A = PC06 - EXT2_PIN16_SPI_SDO = PC04 - EXT2_PIN17_SPI_SDI = PC07 - EXT2_PIN18_SPI_SCK = PC05 - - // Extension Header EXT3 - EXT3_PIN3_ADC_P = PC02 - EXT3_PIN4_ADC_N = PC03 - EXT3_PIN5_GPIO1 = PC01 - EXT3_PIN6_GPIO2 = PC10 - EXT3_PIN7_PWM_P = PD10 - EXT3_PIN8_PWM_N = PD11 - EXT3_PIN9_IRQ = PC30 - EXT3_PIN9_GPIO = PC30 - EXT3_PIN10_SPI_SS_B = PC31 - EXT3_PIN10_GPIO = PC31 - EXT3_PIN11_TWI_SDA = PD08 - EXT3_PIN12_TWI_SCL = PD09 - EXT3_PIN13_UART_RX = PC23 - EXT3_PIN14_UART_TX = PC22 - EXT3_PIN15_SPI_SS_A = PC14 - EXT3_PIN16_SPI_SDO = PC04 - EXT3_PIN17_SPI_SDI = PC07 - EXT3_PIN18_SPI_SCK = PC05 - - // SD_CARD - SD_CARD_MCDA0 = PB18 - SD_CARD_MCDA1 = PB19 - SD_CARD_MCDA2 = PB20 - SD_CARD_MCDA3 = PB21 - SD_CARD_MCCK = PA21 - SD_CARD_MCCDA = PA20 - SD_CARD_DETECT = PD20 - SD_CARD_PROTECT = PD21 - - // I2C - I2C_SDA = PD08 - I2C_SCL = PD09 - - // CAN - CAN0_TX = PA22 - CAN0_RX = PA23 - - CAN1_STANDBY = PC13 - CAN1_TX = PB12 - CAN1_RX = PB13 - - CAN_STANDBY = CAN1_STANDBY - CAN_TX = CAN1_TX - CAN_RX = CAN1_RX - - // PDEC - PDEC_PHASE_A = PC16 - PDEC_PHASE_B = PC17 - PDEC_INDEX = PC18 - - // PCC - PCC_I2C_SDA = PD08 - PCC_I2C_SCL = PD09 - PCC_VSYNC_DEN1 = PA12 - PCC_HSYNC_DEN2 = PA13 - PCC_CLK = PA14 - PCC_XCLK = PA15 - PCC_DATA00 = PA16 - PCC_DATA01 = PA17 - PCC_DATA02 = PA18 - PCC_DATA03 = PA19 - PCC_DATA04 = PA20 - PCC_DATA05 = PA21 - PCC_DATA06 = PA22 - PCC_DATA07 = PA23 - PCC_DATA08 = PB14 - PCC_DATA09 = PB15 - PCC_RESET = PC12 - PCC_PWDN = PC11 - - // Ethernet - ETHERNET_TXCK = PA14 - ETHERNET_TXEN = PA17 - ETHERNET_TX0 = PA18 - ETHERNET_TX1 = PA19 - ETHERNET_RXER = PA15 - ETHERNET_RX0 = PA13 - ETHERNET_RX1 = PA12 - ETHERNET_RXDV = PC20 - ETHERNET_MDIO = PC12 - ETHERNET_MDC = PC11 - ETHERNET_INT = PD12 - ETHERNET_RESET = PC21 - - PIN_QT_BUTTON = PA16 - PIN_BTN0 = PB31 - PIN_ETH_LED = PC15 - PIN_LED0 = PC18 - PIN_ADC_DAC = PA02 - PIN_VBUS_DETECT = PC00 - PIN_USB_ID = PC19 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART pins -const ( - // Extension Header EXT1 - UART_TX_PIN = PA04 // TX : SERCOM0/PAD[0] - UART_RX_PIN = PA05 // RX : SERCOM0/PAD[1] - - // Extension Header EXT2 - UART2_TX_PIN = PB16 // TX : SERCOM5/PAD[0] - UART2_RX_PIN = PB17 // RX : SERCOM5/PAD[1] - - // Extension Header EXT3 - UART3_TX_PIN = PC22 // TX : SERCOM1/PAD[0] - UART3_RX_PIN = PC23 // RX : SERCOM1/PAD[1] - - // Virtual COM Port - UART4_TX_PIN = PB25 // TX : SERCOM2/PAD[0] - UART4_RX_PIN = PB24 // RX : SERCOM2/PAD[1] -) - -// I2C pins -const ( - // Extension Header EXT1 - SDA0_PIN = PA22 // SDA: SERCOM3/PAD[0] - SCL0_PIN = PA23 // SCL: SERCOM3/PAD[1] - - // Extension Header EXT2 - SDA1_PIN = PD08 // SDA: SERCOM7/PAD[0] - SCL1_PIN = PD09 // SCL: SERCOM7/PAD[1] - - // Extension Header EXT3 - SDA2_PIN = PD08 // SDA: SERCOM7/PAD[0] - SCL2_PIN = PD09 // SCL: SERCOM7/PAD[1] - - // Data Gateway Interface - SDA_DGI_PIN = PD08 // SDA: SERCOM7/PAD[0] - SCL_DGI_PIN = PD09 // SCL: SERCOM7/PAD[1] - - SDA_PIN = SDA0_PIN - SCL_PIN = SCL0_PIN -) - -// SPI pins -const ( - // Extension Header EXT1 - SPI0_SCK_PIN = PB26 // SCK: SERCOM4/PAD[1] - SPI0_SDO_PIN = PB27 // SDO: SERCOM4/PAD[0] - SPI0_SDI_PIN = PB29 // SDI: SERCOM4/PAD[3] - SPI0_SS_PIN = PB28 // SS : SERCOM4/PAD[2] - - // Extension Header EXT2 - SPI1_SCK_PIN = PC05 // SCK: SERCOM6/PAD[1] - SPI1_SDO_PIN = PC04 // SDO: SERCOM6/PAD[0] - SPI1_SDI_PIN = PC07 // SDI: SERCOM6/PAD[3] - SPI1_SS_PIN = PC06 // SS : SERCOM6/PAD[2] - - // Extension Header EXT3 - SPI2_SCK_PIN = PC05 // SCK: SERCOM6/PAD[1] - SPI2_SDO_PIN = PC04 // SDO: SERCOM6/PAD[0] - SPI2_SDI_PIN = PC07 // SDI: SERCOM6/PAD[3] - SPI2_SS_PIN = PC14 // SS : GPIO - - // Data Gateway Interface - SPI_DGI_SCK_PIN = PC05 // SCK: SERCOM6/PAD[1] - SPI_DGI_SDO_PIN = PC04 // SDO: SERCOM6/PAD[0] - SPI_DGI_SDI_PIN = PC07 // SDI: SERCOM6/PAD[3] - SPI_DGI_SS_PIN = PD01 // SS : GPIO -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "SAM E54 Xplained Pro" - usb_STRING_MANUFACTURER = "Atmel" -) - -var ( - usb_VID uint16 = 0x03EB - usb_PID uint16 = 0x2404 -) - -// UART on the SAM E54 Xplained Pro -var ( - // Extension Header EXT1 - UART1 = &sercomUSART0 - - // Extension Header EXT2 - UART2 = &sercomUSART5 - - // Extension Header EXT3 - UART3 = &sercomUSART1 - - // EDBG Virtual COM Port - UART4 = &sercomUSART2 -) - -// I2C on the SAM E54 Xplained Pro -var ( - // Extension Header EXT1 - I2C0 = sercomI2CM3 - - // Extension Header EXT2 - I2C1 = sercomI2CM7 - - // Extension Header EXT3 - I2C2 = sercomI2CM7 - - // Data Gateway Interface - I2C3 = sercomI2CM7 -) - -// SPI on the SAM E54 Xplained Pro -var ( - // Extension Header EXT1 - SPI0 = sercomSPIM4 - - // Extension Header EXT2 - SPI1 = sercomSPIM6 - - // Extension Header EXT3 - SPI2 = sercomSPIM6 - - // Data Gateway Interface - SPI3 = sercomSPIM6 -) - -// CAN on the SAM E54 Xplained Pro -var ( - CAN0 = CAN{ - Bus: sam.CAN0, - } - - CAN1 = CAN{ - Bus: sam.CAN1, - } -) diff --git a/emb/machine/board_badger2040-w.go b/emb/machine/board_badger2040-w.go deleted file mode 100644 index d098265..0000000 --- a/emb/machine/board_badger2040-w.go +++ /dev/null @@ -1,95 +0,0 @@ -//go:build badger2040_w - -// This contains the pin mappings for the Badger 2040 W board. -// -// For more information, see: https://shop.pimoroni.com/products/badger-2040-w -// Also -// - Badger 2040 W schematic: https://cdn.shopify.com/s/files/1/0174/1800/files/badger_w_schematic.pdf?v=1675859004 -package machine - -const ( - LED Pin = GPIO22 - - BUTTON_A Pin = GPIO12 - BUTTON_B Pin = GPIO13 - BUTTON_C Pin = GPIO14 - BUTTON_UP Pin = GPIO15 - BUTTON_DOWN Pin = GPIO11 - BUTTON_USER Pin = NoPin // Not available on Badger 2040 W - - EPD_BUSY_PIN Pin = GPIO26 - EPD_RESET_PIN Pin = GPIO21 - EPD_DC_PIN Pin = GPIO20 - EPD_CS_PIN Pin = GPIO17 - EPD_SCK_PIN Pin = GPIO18 - EPD_SDO_PIN Pin = GPIO19 - - VBUS_DETECT Pin = GPIO24 - VREF_POWER Pin = GPIO27 - VREF_1V24 Pin = GPIO28 - VBAT_SENSE Pin = GPIO29 - ENABLE_3V3 Pin = GPIO10 - - BATTERY = VBAT_SENSE - RTC_ALARM = GPIO8 -) - -// I2C pins -const ( - I2C0_SDA_PIN Pin = GPIO4 - I2C0_SCL_PIN Pin = GPIO5 - - I2C1_SDA_PIN Pin = NoPin - I2C1_SCL_PIN Pin = NoPin -) - -// SPI pins. -const ( - SPI0_SCK_PIN Pin = GPIO18 - SPI0_SDO_PIN Pin = GPIO19 - SPI0_SDI_PIN Pin = GPIO16 - - SPI1_SCK_PIN Pin = NoPin - SPI1_SDO_PIN Pin = NoPin - SPI1_SDI_PIN Pin = NoPin -) - -// QSPI pins¿? -const ( -/* - TODO - -SPI0_SD0_PIN Pin = QSPI_SD0 -SPI0_SD1_PIN Pin = QSPI_SD1 -SPI0_SD2_PIN Pin = QSPI_SD2 -SPI0_SD3_PIN Pin = QSPI_SD3 -SPI0_SCK_PIN Pin = QSPI_SCLKGPIO6 -SPI0_CS_PIN Pin = QSPI_CS -*/ -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Badger 2040 W" - usb_STRING_MANUFACTURER = "Pimoroni" -) - -var ( - usb_VID uint16 = 0x2e8a - usb_PID uint16 = 0x0003 -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 diff --git a/emb/machine/board_badger2040.go b/emb/machine/board_badger2040.go deleted file mode 100644 index 73f802a..0000000 --- a/emb/machine/board_badger2040.go +++ /dev/null @@ -1,94 +0,0 @@ -//go:build badger2040 - -// This contains the pin mappings for the Badger 2040 board. -// -// For more information, see: https://shop.pimoroni.com/products/badger-2040 -// Also -// - Badger 2040 schematic: https://cdn.shopify.com/s/files/1/0174/1800/files/badger_2040_schematic.pdf?v=1645702148 -package machine - -const ( - LED Pin = GPIO25 - - BUTTON_A Pin = GPIO12 - BUTTON_B Pin = GPIO13 - BUTTON_C Pin = GPIO14 - BUTTON_UP Pin = GPIO15 - BUTTON_DOWN Pin = GPIO11 - BUTTON_USER Pin = GPIO23 - - EPD_BUSY_PIN Pin = GPIO26 - EPD_RESET_PIN Pin = GPIO21 - EPD_DC_PIN Pin = GPIO20 - EPD_CS_PIN Pin = GPIO17 - EPD_SCK_PIN Pin = GPIO18 - EPD_SDO_PIN Pin = GPIO19 - - VBUS_DETECT Pin = GPIO24 - VREF_POWER Pin = GPIO27 - VREF_1V24 Pin = GPIO28 - VBAT_SENSE Pin = GPIO29 - ENABLE_3V3 Pin = GPIO10 - - BATTERY = VBAT_SENSE -) - -// I2C pins -const ( - I2C0_SDA_PIN Pin = GPIO4 - I2C0_SCL_PIN Pin = GPIO5 - - I2C1_SDA_PIN Pin = NoPin - I2C1_SCL_PIN Pin = NoPin -) - -// SPI pins. -const ( - SPI0_SCK_PIN Pin = GPIO18 - SPI0_SDO_PIN Pin = GPIO19 - SPI0_SDI_PIN Pin = GPIO16 - - SPI1_SCK_PIN Pin = NoPin - SPI1_SDO_PIN Pin = NoPin - SPI1_SDI_PIN Pin = NoPin -) - -// QSPI pins¿? -const ( -/* - TODO - -SPI0_SD0_PIN Pin = QSPI_SD0 -SPI0_SD1_PIN Pin = QSPI_SD1 -SPI0_SD2_PIN Pin = QSPI_SD2 -SPI0_SD3_PIN Pin = QSPI_SD3 -SPI0_SCK_PIN Pin = QSPI_SCLKGPIO6 -SPI0_CS_PIN Pin = QSPI_CS -*/ -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Badger 2040" - usb_STRING_MANUFACTURER = "Pimoroni" -) - -var ( - usb_VID uint16 = 0x2e8a - usb_PID uint16 = 0x0003 -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 diff --git a/emb/machine/board_bluemicro840.go b/emb/machine/board_bluemicro840.go deleted file mode 100644 index acca709..0000000 --- a/emb/machine/board_bluemicro840.go +++ /dev/null @@ -1,80 +0,0 @@ -//go:build bluemicro840 - -package machine - -const HasLowFrequencyCrystal = true - -// GPIO Pins -const ( - D006 = P0_06 - D008 = P0_08 - D015 = P0_15 - D017 = P0_17 - D020 = P0_20 - D013 = P0_13 - D024 = P0_24 - D009 = P0_09 - D010 = P0_10 - D106 = P1_06 - - D031 = P0_31 // AIN7; P0.31 (AIN7) is used to read the voltage of the battery via ADC. It can’t be used for any other function. - D012 = P0_12 // VCC 3.3V; P0.12 on VCC shuts off the power to VCC when you set it to high; This saves on battery immensely for LEDs of all kinds that eat power even when off - - D030 = P0_30 - D026 = P0_26 - D029 = P0_29 - D002 = P0_02 - D113 = P1_13 - D003 = P0_03 - D028 = P0_28 - D111 = P1_11 -) - -// Analog Pins -const ( - AIN0 = P0_02 - AIN1 = P0_03 - AIN2 = P0_04 // Not Connected - AIN3 = P0_05 // Not Connected - AIN4 = P0_28 - AIN5 = P0_29 - AIN6 = P0_30 - AIN7 = P0_31 // Battery -) - -const ( - LED1 Pin = P1_04 // Red LED - LED2 Pin = P1_10 // Blue LED - LED Pin = LED1 -) - -// UART0 pins (logical UART1) - Maps to same location as Pro Micro -const ( - UART_RX_PIN = P0_08 - UART_TX_PIN = P0_06 -) - -// I2C pins -const ( - SDA_PIN = P0_15 // I2C0 external - SCL_PIN = P0_17 // I2C0 external -) - -// SPI pins -const ( - SPI0_SCK_PIN = P1_13 // SCK - SPI0_SDI_PIN = P0_03 // SDI - SPI0_SDO_PIN = P0_28 // SDO - -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "bluemicro840" - usb_STRING_MANUFACTURER = "BlueMicro" -) - -var ( - usb_VID uint16 = 0x1d50 - usb_PID uint16 = 0x6161 -) diff --git a/emb/machine/board_bluepill.go b/emb/machine/board_bluepill.go deleted file mode 100644 index 83f527d..0000000 --- a/emb/machine/board_bluepill.go +++ /dev/null @@ -1,110 +0,0 @@ -//go:build bluepill - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -// Pins printed on the silkscreen -const ( - C13 = PC13 - C14 = PC14 - C15 = PC15 - A0 = PA0 - A1 = PA1 - A2 = PA2 - A3 = PA3 - A4 = PA4 - A5 = PA5 - A6 = PA6 - A7 = PA7 - B0 = PB0 - B1 = PB1 - B10 = PB10 - B11 = PB11 - B12 = PB12 - B13 = PB13 - B14 = PB14 - B15 = PB15 - A8 = PA8 - A9 = PA9 - A10 = PA10 - A11 = PA11 - A12 = PA12 - A13 = PA13 - A14 = PA14 - A15 = PA15 - B3 = PB3 - B4 = PB4 - B5 = PB5 - B6 = PB6 - B7 = PB7 - B8 = PB8 - B9 = PB9 -) - -// Analog Pins -const ( - ADC0 = PA0 - ADC1 = PA1 - ADC2 = PA2 - ADC3 = PA3 - ADC4 = PA4 - ADC5 = PA5 - ADC6 = PA6 - ADC7 = PA7 - ADC8 = PB0 - ADC9 = PB1 -) - -const ( - // This board does not have a user button, so - // use first GPIO pin by default - BUTTON = PA0 - - LED = PC13 -) - -var DefaultUART = UART1 - -// UART pins -const ( - UART_TX_PIN = PA9 - UART_RX_PIN = PA10 - UART_ALT_TX_PIN = PB6 - UART_ALT_RX_PIN = PB7 -) - -var ( - // USART1 is the first hardware serial port on the STM32. - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART1, - } - UART2 = &_UART2 - _UART2 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART2, - } -) - -func init() { - UART1.Interrupt = interrupt.New(stm32.IRQ_USART1, _UART1.handleInterrupt) - UART2.Interrupt = interrupt.New(stm32.IRQ_USART2, _UART2.handleInterrupt) -} - -// SPI pins -const ( - SPI0_SCK_PIN = PA5 - SPI0_SDO_PIN = PA7 - SPI0_SDI_PIN = PA6 -) - -// I2C pins -const ( - I2C0_SDA_PIN = PB7 - I2C0_SCL_PIN = PB6 -) diff --git a/emb/machine/board_btt_skr_pico.go b/emb/machine/board_btt_skr_pico.go deleted file mode 100644 index 6036ad9..0000000 --- a/emb/machine/board_btt_skr_pico.go +++ /dev/null @@ -1,121 +0,0 @@ -//go:build btt_skr_pico - -// This contains the pin mappings for the BigTreeTech SKR Pico. -// -// Purchase link: https://biqu.equipment/products/btt-skr-pico-v1-0 -// Board schematic: https://github.com/bigtreetech/SKR-Pico/blob/master/Hardware/BTT%20SKR%20Pico%20V1.0-SCH.pdf -// Pin diagram: https://github.com/bigtreetech/SKR-Pico/blob/master/Hardware/BTT%20SKR%20Pico%20V1.0-PIN.pdf - -package machine - -// TMC stepper driver motor direction. -// X/Y/Z/E refers to motors for X/Y/Z and the extruder. -const ( - X_DIR = GPIO10 - Y_DIR = GPIO5 - Z_DIR = GPIO28 - E_DIR = GPIO13 -) - -// TMC stepper driver motor step -const ( - X_STEP = GPIO11 - Y_STEP = GPIO6 - Z_STEP = GPIO19 - E_STEP = GPIO14 -) - -// TMC stepper driver enable -const ( - X_ENABLE = GPIO12 - Y_ENABLE = GPIO7 - Z_ENABLE = GPIO2 - E_ENABLE = GPIO15 -) - -// TMC stepper driver UART -const ( - TMC_UART_TX = UART1_TX_PIN - TMC_UART_RX = UART1_RX_PIN -) - -// Endstops -const ( - X_ENDSTOP = GPIO4 - Y_ENDSTOP = GPIO3 - Z_ENDSTOP = GPIO25 - E_ENDSTOP = GPIO16 -) - -// Fan PWM -const ( - FAN1_PWM = GPIO17 - FAN2_PWM = GPIO18 - FAN3_PWM = GPIO20 -) - -// Heater PWM -const ( - HEATER_BED_PWM = GPIO21 - HEATER_EXTRUDER_PWM = GPIO23 -) - -// Thermistors -const ( - THERM_BED = GPIO26 // Bed heater - THERM_EXTRUDER = GPIO27 // Toolhead heater -) - -// Misc -const ( - RGB = GPIO24 // Neopixel - SERVO = GPIO29 // Servo - PROBE = GPIO22 // Probe -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// I2C. We don't have this available -const ( - I2C0_SDA_PIN = NoPin - I2C0_SCL_PIN = NoPin - - I2C1_SDA_PIN = NoPin - I2C1_SCL_PIN = NoPin -) - -// SPI. We don't have this available -const ( - SPI0_SCK_PIN = NoPin - SPI0_SDO_PIN = NoPin - SPI0_SDI_PIN = NoPin - SPI1_SCK_PIN = NoPin - SPI1_SDO_PIN = NoPin - SPI1_SDI_PIN = NoPin -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "SKR Pico" - usb_STRING_MANUFACTURER = "BigTreeTech" -) - -var ( - usb_VID uint16 = 0x2e8a - usb_PID uint16 = 0x0003 -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO8 - UART1_RX_PIN = GPIO9 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 diff --git a/emb/machine/board_challenger_rp2040.go b/emb/machine/board_challenger_rp2040.go deleted file mode 100644 index 9a85aa0..0000000 --- a/emb/machine/board_challenger_rp2040.go +++ /dev/null @@ -1,93 +0,0 @@ -//go:build challenger_rp2040 - -package machine - -const ( - LED = GPIO24 - - // Onboard crystal oscillator frequency, in MHz. - xoscFreq = 12 // MHz -) - -// GPIO Pins -const ( - D5 = GPIO2 - D6 = GPIO3 - D9 = GPIO4 - D10 = GPIO5 - D11 = GPIO6 - D12 = GPIO7 - D13 = GPIO8 -) - -// Analog pins -const ( - A0 = ADC0 - A1 = ADC1 - A2 = ADC2 - A3 = ADC3 -) - -// I2C Pins. -const ( - I2C0_SDA_PIN = GPIO24 - I2C0_SCL_PIN = GPIO25 - - I2C1_SDA_PIN = GPIO2 - I2C1_SCL_PIN = GPIO3 - - SDA_PIN = I2C1_SDA_PIN - SCL_PIN = I2C1_SCL_PIN -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO22 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO23 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO20 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO10 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO11 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO12 // Rx -) - -// LoRa default pins -const ( - LORA_CS = GPIO9 - LORA_SCK = GPIO10 - LORA_SDO = GPIO11 - LORA_SDI = GPIO12 - LORA_RESET = GPIO13 - LORA_DIO0 = GPIO14 - LORA_DIO1 = GPIO15 - LORA_DIO2 = GPIO18 -) - -// UART pins -const ( - UART0_TX_PIN = GPIO16 - UART0_RX_PIN = GPIO17 - UART1_TX_PIN = GPIO4 - UART1_RX_PIN = GPIO5 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Challenger 2040 LoRa" - usb_STRING_MANUFACTURER = "iLabs" -) - -var ( - usb_VID uint16 = 0x2e8a - usb_PID uint16 = 0x1023 -) diff --git a/emb/machine/board_circuitplay_bluefruit.go b/emb/machine/board_circuitplay_bluefruit.go deleted file mode 100644 index a133003..0000000 --- a/emb/machine/board_circuitplay_bluefruit.go +++ /dev/null @@ -1,95 +0,0 @@ -//go:build circuitplay_bluefruit - -package machine - -const HasLowFrequencyCrystal = false - -// GPIO Pins -const ( - D0 = P0_30 - D1 = P0_14 - D2 = P0_05 - D3 = P0_04 - D4 = P1_02 - D5 = P1_15 - D6 = P0_02 - D7 = P1_06 - D8 = P0_13 - D9 = P0_29 - D10 = P0_03 - D11 = P1_04 - D12 = P0_26 - D13 = P1_14 -) - -// Analog Pins -const ( - A1 = P0_02 - A2 = P0_29 - A3 = P0_03 - A4 = P0_04 - A5 = P0_05 - A6 = P0_30 - A7 = P0_14 - A8 = P0_28 - A9 = P0_31 -) - -const ( - LED = D13 - NEOPIXELS = D8 - WS2812 = D8 - - BUTTONA = D4 - BUTTONB = D5 - SLIDER = D7 // built-in slide switch - - BUTTON = BUTTONA - BUTTON1 = BUTTONB - - LIGHTSENSOR = A8 - TEMPSENSOR = A9 -) - -// UART0 pins (logical UART1) -const ( - UART_TX_PIN = P0_14 // PORTB - UART_RX_PIN = P0_30 // PORTB -) - -// I2C pins -const ( - SDA_PIN = P0_05 // I2C0 external - SCL_PIN = P0_04 // I2C0 external - - SDA1_PIN = P1_10 // I2C1 internal - SCL1_PIN = P1_12 // I2C1 internal -) - -// SPI pins (internal flash) -const ( - SPI0_SCK_PIN = P0_19 // SCK - SPI0_SDO_PIN = P0_21 // SDO - SPI0_SDI_PIN = P0_23 // SDI -) - -// PDM pins -const ( - PDM_CLK_PIN = P0_17 // CLK - PDM_DIN_PIN = P0_16 // DIN -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit Circuit Playground Bluefruit" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8045 -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_circuitplay_express.go b/emb/machine/board_circuitplay_express.go deleted file mode 100644 index ce1f29c..0000000 --- a/emb/machine/board_circuitplay_express.go +++ /dev/null @@ -1,119 +0,0 @@ -//go:build circuitplay_express - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PB09 - D1 = PB08 - D2 = PB02 - D3 = PB03 - D4 = PA28 - D5 = PA14 - D6 = PA05 - D7 = PA15 - D8 = PB23 - D9 = PA06 - D10 = PA07 - D11 = NoPin // does not seem to exist - D12 = PA02 - D13 = PA17 // PWM available -) - -// Analog Pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PA05 // PWM available, also ADC/AIN[5] - A2 = PA06 // PWM available, also ADC/AIN[6] - A3 = PA07 // PWM available, also ADC/AIN[7] - A4 = PB03 // PORTB - A5 = PB02 // PORTB - A6 = PB09 // PORTB - A7 = PB08 // PORTB - A8 = PA11 // ADC/AIN[19] - A9 = PA09 // ADC/AIN[17] - A10 = PA04 -) - -const ( - LED = D13 - NEOPIXELS = D8 - WS2812 = D8 - - BUTTONA = D4 - BUTTONB = D5 - SLIDER = D7 // built-in slide switch - - BUTTON = BUTTONA - BUTTON1 = BUTTONB - - LIGHTSENSOR = A8 - TEMPSENSOR = A9 - PROXIMITY = A10 -) - -// USBCDC pins (logical UART0) -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART0 pins (logical UART1) -const ( - UART_TX_PIN = PB08 // PORTB - UART_RX_PIN = PB09 // PORTB -) - -// UART1 on the Circuit Playground Express. -var ( - UART1 = &sercomUSART4 - - DefaultUART = UART1 -) - -// I2C pins -const ( - SDA_PIN = PB02 // I2C0 external - SCL_PIN = PB03 // I2C0 external - - SDA1_PIN = PA00 // I2C1 internal - SCL1_PIN = PA01 // I2C1 internal -) - -// I2C on the Circuit Playground Express. -var ( - I2C0 = sercomI2CM5 // external device - I2C1 = sercomI2CM1 // internal device -) - -// SPI pins (internal flash) -const ( - SPI0_SCK_PIN = PA21 // SCK: SERCOM3/PAD[3] - SPI0_SDO_PIN = PA20 // SDO: SERCOM3/PAD[2] - SPI0_SDI_PIN = PA16 // SDI: SERCOM3/PAD[0] -) - -// SPI on the Circuit Playground Express. -var SPI0 = sercomSPIM3 - -// I2S pins -const ( - I2S_SCK_PIN = PA10 - I2S_SDO_PIN = PA08 - I2S_SDI_PIN = NoPin - I2S_WS_PIN = NoPin // no WS, instead uses SCK to sync -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit Circuit Playground Express" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8018 -) diff --git a/emb/machine/board_clue_alpha.go b/emb/machine/board_clue_alpha.go deleted file mode 100644 index 8d16f4e..0000000 --- a/emb/machine/board_clue_alpha.go +++ /dev/null @@ -1,125 +0,0 @@ -//go:build clue_alpha - -package machine - -const HasLowFrequencyCrystal = false - -// GPIO Pins -const ( - D0 = P0_04 - D1 = P0_05 - D2 = P0_03 - D3 = P0_28 - D4 = P0_02 - D5 = P1_02 - D6 = P1_09 - D7 = P0_07 - D8 = P1_07 - D9 = P0_27 - D10 = P0_30 - D11 = P1_10 - D12 = P0_31 - D13 = P0_08 - D14 = P0_06 - D15 = P0_26 - D16 = P0_29 - D17 = P1_01 - D18 = P0_16 - D19 = P0_25 - D20 = P0_24 - D29 = P0_14 - D30 = P0_15 - D31 = P0_12 - D32 = P0_13 - D33 = P1_03 - D34 = P1_05 - D35 = P0_00 - D36 = P0_01 - D37 = P0_19 - D38 = P0_20 - D39 = P0_17 - D40 = P0_22 - D41 = P0_23 - D42 = P0_21 - D43 = P0_10 - D44 = P0_09 - D45 = P1_06 - D46 = P1_00 -) - -// Analog Pins -const ( - A0 = D12 - A1 = D16 - A2 = D0 - A3 = D1 - A4 = D2 - A5 = D3 - A6 = D4 - A7 = D10 -) - -const ( - LED = D17 - LED1 = LED - LED2 = D43 - NEOPIXEL = D18 - WS2812 = D18 - - BUTTON_LEFT = D5 - BUTTON_RIGHT = D11 - - // 240x240 ST7789 display is connected to these pins (use RowOffset = 80) - TFT_SCK = D29 - TFT_SDO = D30 - TFT_CS = D31 - TFT_DC = D32 - TFT_RESET = D33 - TFT_LITE = D34 - - PDM_DAT = D35 - PDM_CLK = D36 - - QSPI_SCK = D37 - QSPI_CS = D38 - QSPI_DATA0 = D39 - QSPI_DATA1 = D40 - QSPI_DATA2 = D41 - QSPI_DATA3 = D42 - - SPEAKER = D46 -) - -// UART0 pins (logical UART1) -const ( - UART_RX_PIN = D0 - UART_TX_PIN = D1 -) - -// I2C pins -const ( - SDA_PIN = D20 // I2C0 external - SCL_PIN = D19 // I2C0 external -) - -// SPI pins -const ( - SPI0_SCK_PIN = D13 // SCK - SPI0_SDO_PIN = D15 // SDO - SPI0_SDI_PIN = D14 // SDI -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit CLUE" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8072 -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_digispark.go b/emb/machine/board_digispark.go deleted file mode 100644 index f380aae..0000000 --- a/emb/machine/board_digispark.go +++ /dev/null @@ -1,19 +0,0 @@ -//go:build digispark - -package machine - -// Return the current CPU frequency in hertz. -func CPUFrequency() uint32 { - return 16000000 -} - -const ( - P0 Pin = PB0 - P1 Pin = PB1 - P2 Pin = PB2 - P3 Pin = PB3 - P4 Pin = PB4 - P5 Pin = PB5 - - LED = P1 -) diff --git a/emb/machine/board_elecrow-rp2040-w5.go b/emb/machine/board_elecrow-rp2040-w5.go deleted file mode 100644 index 1ea0181..0000000 --- a/emb/machine/board_elecrow-rp2040-w5.go +++ /dev/null @@ -1,94 +0,0 @@ -//go:build elecrow_rp2040 - -// This file contains the pin mappings for the Elecrow Pico rp2040 W5 boards. -// -// Elecrow Pico rp2040 W5 is a microcontroller using the Raspberry Pi RP2040 -// chip and rtl8720d Wifi chip. -// -// - https://www.elecrow.com/wiki/PICO_W5_RP2040_Dev_Board.html -package machine - -// GPIO pins -const ( - GP0 Pin = GPIO0 - GP1 Pin = GPIO1 - GP2 Pin = GPIO2 - GP3 Pin = GPIO3 - GP4 Pin = GPIO4 - GP5 Pin = GPIO5 - GP6 Pin = GPIO6 - GP7 Pin = GPIO7 - GP8 Pin = GPIO8 - GP9 Pin = GPIO9 - GP10 Pin = GPIO10 - GP11 Pin = GPIO11 - GP12 Pin = GPIO12 - GP13 Pin = GPIO13 - GP14 Pin = GPIO14 - GP15 Pin = GPIO15 - GP16 Pin = GPIO16 - GP17 Pin = GPIO17 - GP18 Pin = GPIO18 - GP19 Pin = GPIO19 - GP20 Pin = GPIO20 - GP21 Pin = GPIO21 - GP22 Pin = GPIO22 - GP26 Pin = GPIO26 - GP27 Pin = GPIO27 - GP28 Pin = GPIO28 - - // Onboard LED - LED Pin = GPIO25 - - // Onboard crystal oscillator frequency, in MHz. - xoscFreq = 12 // MHz -) - -// I2C Default pins on Raspberry Pico. -const ( - I2C0_SDA_PIN = GP4 - I2C0_SCL_PIN = GP5 - - I2C1_SDA_PIN = GP2 - I2C1_SCL_PIN = GP3 -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO18 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO19 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO16 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO10 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO11 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO12 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO4 // Wired to rtl8720d UART1_Tx - UART1_RX_PIN = GPIO5 // Wired to rtl8720n UART1_Rx - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Pico" - usb_STRING_MANUFACTURER = "Raspberry Pi" -) - -var ( - usb_VID uint16 = 0x2E8A - usb_PID uint16 = 0x000A -) diff --git a/emb/machine/board_elecrow-rp2350-w5.go b/emb/machine/board_elecrow-rp2350-w5.go deleted file mode 100644 index 80a8436..0000000 --- a/emb/machine/board_elecrow-rp2350-w5.go +++ /dev/null @@ -1,94 +0,0 @@ -//go:build elecrow_rp2350 - -// This file contains the pin mappings for the Elecrow Pico rp2350 W5 boards. -// -// Elecrow Pico rp2350 W5 is a microcontroller using the Raspberry Pi RP2350 -// chip and rtl8720d Wifi chip. -// -// - https://www.elecrow.com/pico-w5-microcontroller-development-boards-rp2350-microcontroller-board.html -package machine - -// GPIO pins -const ( - GP0 Pin = GPIO0 - GP1 Pin = GPIO1 - GP2 Pin = GPIO2 - GP3 Pin = GPIO3 - GP4 Pin = GPIO4 - GP5 Pin = GPIO5 - GP6 Pin = GPIO6 - GP7 Pin = GPIO7 - GP8 Pin = GPIO8 - GP9 Pin = GPIO9 - GP10 Pin = GPIO10 - GP11 Pin = GPIO11 - GP12 Pin = GPIO12 - GP13 Pin = GPIO13 - GP14 Pin = GPIO14 - GP15 Pin = GPIO15 - GP16 Pin = GPIO16 - GP17 Pin = GPIO17 - GP18 Pin = GPIO18 - GP19 Pin = GPIO19 - GP20 Pin = GPIO20 - GP21 Pin = GPIO21 - GP22 Pin = GPIO22 - GP26 Pin = GPIO26 - GP27 Pin = GPIO27 - GP28 Pin = GPIO28 - - // Onboard LED - LED Pin = GPIO25 - - // Onboard crystal oscillator frequency, in MHz. - xoscFreq = 12 // MHz -) - -// I2C Default pins on Raspberry Pico. -const ( - I2C0_SDA_PIN = GP4 - I2C0_SCL_PIN = GP5 - - I2C1_SDA_PIN = GP2 - I2C1_SCL_PIN = GP3 -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO18 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO19 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO16 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO10 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO11 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO12 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO4 // Wired to rtl8720d UART1_Tx - UART1_RX_PIN = GPIO5 // Wired to rtl8720n UART1_Rx - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Pico2" - usb_STRING_MANUFACTURER = "Raspberry Pi" -) - -var ( - usb_VID uint16 = 0x2E8A - usb_PID uint16 = 0x000F -) diff --git a/emb/machine/board_esp-c3-32s-kit.go b/emb/machine/board_esp-c3-32s-kit.go deleted file mode 100644 index 09385aa..0000000 --- a/emb/machine/board_esp-c3-32s-kit.go +++ /dev/null @@ -1,40 +0,0 @@ -//go:build esp_c3_32s_kit - -package machine - -// See: -// * https://www.waveshare.com/w/upload/8/8f/Esp32-c3s_specification.pdf -// * https://www.waveshare.com/w/upload/4/46/Nodemcu-esp-c3-32s-kit-schematics.pdf - -// Digital Pins -const ( - IO0 = GPIO0 - IO1 = GPIO1 - IO2 = GPIO2 - IO3 = GPIO3 - IO4 = GPIO4 - IO5 = GPIO5 - IO6 = GPIO6 - IO7 = GPIO7 - IO8 = GPIO8 - IO9 = GPIO9 - IO18 = GPIO18 - IO19 = GPIO19 -) - -const ( - LED_RED = IO3 - LED_GREEN = IO4 - LED_BLUE = IO5 - - LED = LED_RED - - LED1 = LED_RED - LED2 = LED_GREEN -) - -// I2C pins -const ( - SDA_PIN = NoPin - SCL_PIN = NoPin -) diff --git a/emb/machine/board_esp32-c3-devkit-rust-1.go b/emb/machine/board_esp32-c3-devkit-rust-1.go deleted file mode 100644 index 8e47269..0000000 --- a/emb/machine/board_esp32-c3-devkit-rust-1.go +++ /dev/null @@ -1,81 +0,0 @@ -//go:build esp32_c3_devkit_rust_1 - -// This file contains the pin mappings for the Espressif ESP32-C3 Development Board for Rust. -// -// The Espressif ESP32-C3-DevKit-RUST-1 development board is powered -// by the Espressif ESP32-C3 SoC featuring an open-source RISC-V architecture. -// -// Specifications: -// SoC: ESP32-C3-MINI-1, 4MB Flash, RISCV-32bit, 160MHz, 400KB SRAM -// Wireless: WiFi & Bluetooth 5.0 (BLE) -// ICM-42670-P 6-Axis IMU (I2C Addr 0x68) -// SHTC3 Humidity and Temperature Sensor (I2C Addr 0x70) -// WS2812B LED - -// GitHub: https://github.com/esp-rs/esp-rust-board -// Schematic: https://github.com/esp-rs/esp-rust-board/blob/master/hardware/esp-rust-board/schematic/esp-rust-board.pdf -// Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf - -package machine - -// Digital pins -const ( - // Pin // Function - // ----- // --------------- - D0 = GPIO0 // - D1 = GPIO1 // - D2 = GPIO2 // WS2812 - D3 = GPIO3 // - D4 = GPIO4 // MTMS - D5 = GPIO5 // MTDI - D6 = GPIO6 // MTCK - D7 = GPIO7 // Red LED / MTDO - D8 = GPIO8 // I2C SCL - D9 = GPIO9 // Boot Button - D10 = GPIO10 // I2C SDA - D18 = GPIO18 // USB DM - D19 = GPIO19 // USB DP - D20 = GPIO20 // UART RX - D21 = GPIO21 // UART TX -) - -// Analog pins -const ( - A0 = GPIO0 - A1 = GPIO1 - A2 = GPIO2 - A3 = GPIO3 - A4 = GPIO4 - A5 = GPIO5 -) - -// Button pin -const ( - BUTTON = BUTTON_BOOT - BUTTON_BOOT = D9 -) - -// LED pins -const ( - LED = LED_BUILTIN - WS2812 = D2 - LED_BUILTIN = D7 -) - -// I2C pins -const ( - SCL_PIN = D8 - SDA_PIN = D10 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = D18 - USBCDC_DP_PIN = D19 -) - -// UART pins -const ( - UART_RX_PIN = D20 - UART_TX_PIN = D21 -) diff --git a/emb/machine/board_esp32-coreboard-v2.go b/emb/machine/board_esp32-coreboard-v2.go deleted file mode 100644 index 044d906..0000000 --- a/emb/machine/board_esp32-coreboard-v2.go +++ /dev/null @@ -1,88 +0,0 @@ -//go:build esp32_coreboard_v2 - -package machine - -const ( - CLK = GPIO6 - CMD = GPIO11 - IO0 = GPIO0 - IO1 = GPIO1 - IO2 = GPIO2 - IO3 = GPIO3 - IO4 = GPIO4 - IO5 = GPIO5 - IO9 = GPIO9 - IO10 = GPIO10 - IO16 = GPIO16 - IO17 = GPIO17 - IO18 = GPIO18 - IO19 = GPIO19 - IO21 = GPIO21 - IO22 = GPIO22 - IO23 = GPIO23 - IO25 = GPIO25 - IO26 = GPIO26 - IO27 = GPIO27 - IO32 = GPIO32 - IO33 = GPIO33 - IO34 = GPIO34 - IO35 = GPIO35 - IO36 = GPIO36 - IO39 = GPIO39 - RXD = GPIO3 - SD0 = GPIO7 - SD1 = GPIO8 - SD2 = GPIO9 - SD3 = GPIO10 - SVN = GPIO39 - SVP = GPIO36 - TCK = GPIO13 - TD0 = GPIO15 - TDI = GPIO12 - TMS = GPIO14 - TXD = GPIO1 -) - -// Built-in LED on some ESP32 boards. -const LED = IO2 - -// SPI pins -const ( - SPI0_SCK_PIN = IO18 - SPI0_SDO_PIN = IO23 - SPI0_SDI_PIN = IO19 - SPI0_CS0_PIN = IO5 -) - -// I2C pins -const ( - SDA_PIN = IO21 - SCL_PIN = IO22 -) - -// ADC pins -const ( - ADC0 Pin = IO34 - ADC1 Pin = IO35 - ADC2 Pin = IO36 - ADC3 Pin = IO39 -) - -// UART0 pins -const ( - UART_TX_PIN = IO1 - UART_RX_PIN = IO3 -) - -// UART1 pins -const ( - UART1_TX_PIN = IO9 - UART1_RX_PIN = IO10 -) - -// PWM pins -const ( - PWM0_PIN Pin = IO2 - PWM1_PIN Pin = IO0 - PWM2_PIN Pin = IO4 -) diff --git a/emb/machine/board_esp32c3-12f.go b/emb/machine/board_esp32c3-12f.go deleted file mode 100644 index f023bb9..0000000 --- a/emb/machine/board_esp32c3-12f.go +++ /dev/null @@ -1,54 +0,0 @@ -//go:build esp32c312f - -package machine - -// Built-in RGB LED -const ( - LED_RED = IO3 - LED_GREEN = IO4 - LED_BLUE = IO5 - LED = LED_RED -) - -const ( - IO0 = GPIO0 - IO1 = GPIO1 - IO2 = GPIO2 - IO3 = GPIO3 - IO4 = GPIO4 - IO5 = GPIO5 - IO6 = GPIO6 - IO7 = GPIO7 - IO8 = GPIO8 - IO9 = GPIO9 - IO10 = GPIO10 - IO18 = GPIO18 - IO19 = GPIO19 - RXD = GPIO20 - TXD = GPIO21 -) - -// ADC pins -const ( - ADC0 Pin = ADC1_0 - ADC1 Pin = ADC2_0 - - ADC1_0 Pin = IO0 - ADC1_1 Pin = IO1 - ADC1_2 Pin = IO2 - ADC1_3 Pin = IO3 - ADC1_4 Pin = IO4 - ADC2_0 Pin = IO5 -) - -// UART0 pins -const ( - UART_TX_PIN = TXD - UART_RX_PIN = RXD -) - -// I2C pins -const ( - SCL_PIN = NoPin - SDA_PIN = NoPin -) diff --git a/emb/machine/board_esp32c3-supermini.go b/emb/machine/board_esp32c3-supermini.go deleted file mode 100644 index c180ff0..0000000 --- a/emb/machine/board_esp32c3-supermini.go +++ /dev/null @@ -1,57 +0,0 @@ -//go:build esp32c3_supermini - -// This file contains the pin mappings for the ESP32 supermini boards. -// -// - https://web.archive.org/web/20240805232453/https://dl.artronshop.co.th/ESP32-C3%20SuperMini%20datasheet.pdf - -package machine - -// Digital Pins -const ( - IO0 = GPIO0 - IO1 = GPIO1 - IO2 = GPIO2 - IO3 = GPIO3 - IO4 = GPIO4 - IO5 = GPIO5 - IO6 = GPIO6 - IO7 = GPIO7 - IO8 = GPIO8 - IO9 = GPIO9 - IO10 = GPIO10 - IO20 = GPIO20 - IO21 = GPIO21 -) - -// Built-in LED -const LED = GPIO8 - -// Analog pins -const ( - A0 = GPIO0 - A1 = GPIO1 - A2 = GPIO2 - A3 = GPIO3 - A4 = GPIO4 - A5 = GPIO5 -) - -// UART pins -const ( - UART_RX_PIN = GPIO20 - UART_TX_PIN = GPIO21 -) - -// I2C pins -const ( - SDA_PIN = GPIO8 - SCL_PIN = GPIO9 -) - -// SPI pins -const ( - SPI_MISO_PIN = GPIO5 - SPI_MOSI_PIN = GPIO6 - SPI_SS_PIN = GPIO7 - SPI_SCK_PIN = GPIO4 -) diff --git a/emb/machine/board_fe310.go b/emb/machine/board_fe310.go deleted file mode 100644 index 8881015..0000000 --- a/emb/machine/board_fe310.go +++ /dev/null @@ -1,38 +0,0 @@ -//go:build hifive1b - -package machine - -const ( - P00 Pin = 0 - P01 Pin = 1 - P02 Pin = 2 - P03 Pin = 3 - P04 Pin = 4 - P05 Pin = 5 - P06 Pin = 6 - P07 Pin = 7 - P08 Pin = 8 - P09 Pin = 9 - P10 Pin = 10 - P11 Pin = 11 - P12 Pin = 12 - P13 Pin = 13 - P14 Pin = 14 - P15 Pin = 15 - P16 Pin = 16 - P17 Pin = 17 - P18 Pin = 18 - P19 Pin = 19 - P20 Pin = 20 - P21 Pin = 21 - P22 Pin = 22 - P23 Pin = 23 - P24 Pin = 24 - P25 Pin = 25 - P26 Pin = 26 - P27 Pin = 27 - P28 Pin = 28 - P29 Pin = 29 - P30 Pin = 30 - P31 Pin = 31 -) diff --git a/emb/machine/board_feather-m0-express.go b/emb/machine/board_feather-m0-express.go deleted file mode 100644 index 226369f..0000000 --- a/emb/machine/board_feather-m0-express.go +++ /dev/null @@ -1,102 +0,0 @@ -//go:build sam && atsamd21 && feather_m0_express - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PA11 // UART0 RX - D1 = PA10 // UART0 TX - D2 = NoPin // does not seem to exist - D3 = NoPin // does not seem to exist - D4 = NoPin // does not seem to exist - D5 = PA15 - D6 = PA20 - D7 = NoPin // does not seem to exist - D8 = PA06 // NEOPIXEL - D9 = PA07 - D10 = PA18 - D11 = PA16 - D12 = PA19 - D13 = PA17 -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PB08 // ADC/AIN[2] - A2 = PB09 // ADC/AIN[3] - A3 = PA04 // ADC/AIN[4] - A4 = PA05 // ADC/AIN[5] - A5 = PB02 // ADC/AIN[10] -) - -const ( - LED = D13 - NEOPIXEL = D8 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN = D1 - UART_RX_PIN = D0 - - UART1_TX_PIN = D10 - UART1_RX_PIN = D12 -) - -// UART0 on the Feather M0 Express. -var UART0 = &sercomUSART0 -var UART1 = &sercomUSART1 - -// I2C pins -const ( - SDA_PIN = PA22 // SDA: SERCOM3/PAD[0] - SCL_PIN = PA23 // SCL: SERCOM3/PAD[1] -) - -// I2C on the Feather M0 Express. -var ( - I2C0 = sercomI2CM3 -) - -// SPI pins -const ( - SPI0_SCK_PIN = PB11 // SCK: SERCOM4/PAD[3] - SPI0_SDO_PIN = PB10 // SDO: SERCOM4/PAD[2] - SPI0_SDI_PIN = PA12 // SDI: SERCOM4/PAD[0] -) - -// SPI on the Feather M0. -var SPI0 = sercomSPIM4 - -// I2S pins -const ( - I2S_SCK_PIN = PA10 - I2S_SDO_PIN = PA07 - I2S_SDI_PIN = NoPin - I2S_WS_PIN = NoPin // TODO: figure out what this is on Feather M0 Express. -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit Feather M0 Express" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x801B -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_feather-m0.go b/emb/machine/board_feather-m0.go deleted file mode 100644 index f38d8ec..0000000 --- a/emb/machine/board_feather-m0.go +++ /dev/null @@ -1,97 +0,0 @@ -//go:build sam && atsamd21 && feather_m0 - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PA11 // UART0 RX - D1 = PA10 // UART0 TX - D2 = NoPin // does not seem to exist - D3 = PA09 - D4 = PA08 - D5 = PA15 // PWM available - D6 = PA20 // PWM available - D7 = NoPin // does not seem to exist - D8 = PA06 - D9 = PA07 // PWM available - D10 = PA18 // can be used for PWM or UART1 TX - D11 = PA16 // can be used for PWM or UART1 RX - D12 = PA19 // PWM available - D13 = PA17 // PWM available -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PB08 // ADC/AIN[2] - A2 = PB09 // ADC/AIN[3] - A3 = PA04 // ADC/AIN[4] - A4 = PA05 // ADC/AIN[5] - A5 = PB02 // ADC/AIN[10] -) - -const ( - LED = D13 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN = D10 - UART_RX_PIN = D11 -) - -// UART1 on the Feather M0. -var UART1 = &sercomUSART1 - -// I2C pins -const ( - SDA_PIN = PA22 // SDA: SERCOM3/PAD[0] - SCL_PIN = PA23 // SCL: SERCOM3/PAD[1] -) - -// I2C on the Feather M0. -var ( - I2C0 = sercomI2CM3 -) - -// SPI pins -const ( - SPI0_SCK_PIN = PB11 // SCK: SERCOM4/PAD[3] - SPI0_SDO_PIN = PB10 // SDO: SERCOM4/PAD[2] - SPI0_SDI_PIN = PA12 // SDI: SERCOM4/PAD[0] -) - -// SPI on the Feather M0. -var SPI0 = sercomSPIM4 - -// I2S pins -const ( - I2S_SCK_PIN = PA10 - I2S_SDO_PIN = PA08 - I2S_SDI_PIN = NoPin - I2S_WS_PIN = NoPin // TODO: figure out what this is on Feather M0. -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit Feather M0 Express" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x801B -) - -var ( - DefaultUART = UART1 -) diff --git a/emb/machine/board_feather-m4-can.go b/emb/machine/board_feather-m4-can.go deleted file mode 100644 index 6a39506..0000000 --- a/emb/machine/board_feather-m4-can.go +++ /dev/null @@ -1,138 +0,0 @@ -//go:build feather_m4_can - -package machine - -import ( - "device/sam" -) - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PB17 // UART0 RX/PWM available - D1 = PB16 // UART0 TX/PWM available - D4 = PA14 // PWM available - D5 = PA16 // PWM available - D6 = PA18 // PWM available - D7 = PB03 // neopixel power - D8 = PB02 // built-in neopixel - D9 = PA19 // PWM available - D10 = PA20 // can be used for PWM or UART1 TX - D11 = PA21 // can be used for PWM or UART1 RX - D12 = PA22 // PWM available - D13 = PA23 // PWM available - D21 = PA13 // PWM available - D22 = PA12 // PWM available - D23 = PB22 // PWM available - D24 = PB23 // PWM available - D25 = PA17 // PWM available -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PA05 // ADC/AIN[2] - A2 = PB08 // ADC/AIN[3] - A3 = PB09 // ADC/AIN[4] - A4 = PA04 // ADC/AIN[5] - A5 = PA06 // ADC/AIN[10] -) - -const ( - LED = D13 - NEOPIXELS = D8 - WS2812 = D8 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -const ( - UART_TX_PIN = D1 - UART_RX_PIN = D0 -) - -const ( - UART2_TX_PIN = A4 - UART2_RX_PIN = A5 -) - -// I2C pins -const ( - SDA_PIN = D22 // SDA: SERCOM2/PAD[0] - SCL_PIN = D21 // SCL: SERCOM2/PAD[1] -) - -// SPI pins -const ( - SPI0_SCK_PIN = D25 // SCK: SERCOM1/PAD[1] - SPI0_SDO_PIN = D24 // SDO: SERCOM1/PAD[3] - SPI0_SDI_PIN = D23 // SDI: SERCOM1/PAD[2] -) - -// CAN pins -const ( - CAN0_TX = PA22 - CAN0_RX = PA23 - - CAN1_STANDBY = PB12 - CAN1_TX = PB14 - CAN1_RX = PB15 - BOOST_EN = PB13 // power control of CAN1's TCAN1051HGV (H: enable) - - CAN_STANDBY = CAN1_STANDBY - CAN_S = CAN1_STANDBY - CAN_TX = CAN1_TX - CAN_RX = CAN1_RX -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit Feather M4 CAN" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x80CD -) - -var ( - UART1 = &sercomUSART5 - - UART2 = &sercomUSART0 -) - -func init() { - // turn on neopixel - D7.Configure(PinConfig{Mode: PinOutput}) - D7.High() -} - -// I2C on the Feather M4 CAN. -var ( - I2C0 = sercomI2CM2 -) - -// SPI on the Feather M4 CAN. -var SPI0 = sercomSPIM1 - -// CAN on the Feather M4 CAN. -var ( - CAN0 = CAN{ - Bus: sam.CAN0, - } - - CAN1 = CAN{ - Bus: sam.CAN1, - } -) - -var ( - DefaultUART = UART1 -) diff --git a/emb/machine/board_feather-m4.go b/emb/machine/board_feather-m4.go deleted file mode 100644 index fb88fb9..0000000 --- a/emb/machine/board_feather-m4.go +++ /dev/null @@ -1,96 +0,0 @@ -//go:build feather_m4 - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PB17 // UART0 RX/PWM available - D1 = PB16 // UART0 TX/PWM available - D4 = PA14 // PWM available - D5 = PA16 // PWM available - D6 = PA18 // PWM available - D8 = PB03 // built-in neopixel - D9 = PA19 // PWM available - D10 = PA20 // can be used for PWM or UART1 TX - D11 = PA21 // can be used for PWM or UART1 RX - D12 = PA22 // PWM available - D13 = PA23 // PWM available - D21 = PA13 // PWM available - D22 = PA12 // PWM available - D23 = PB22 // PWM available - D24 = PB23 // PWM available - D25 = PA17 // PWM available -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PA05 // ADC/AIN[2] - A2 = PB08 // ADC/AIN[3] - A3 = PB09 // ADC/AIN[4] - A4 = PA04 // ADC/AIN[5] - A5 = PA06 // ADC/AIN[10] -) - -const ( - LED = D13 - WS2812 = D8 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -const ( - UART_TX_PIN = D1 - UART_RX_PIN = D0 -) - -const ( - UART2_TX_PIN = A4 - UART2_RX_PIN = A5 -) - -var ( - UART1 = &sercomUSART5 - UART2 = &sercomUSART0 - - DefaultUART = UART1 -) - -// I2C pins -const ( - SDA_PIN = D22 // SDA: SERCOM2/PAD[0] - SCL_PIN = D21 // SCL: SERCOM2/PAD[1] -) - -// I2C on the Feather M4. -var ( - I2C0 = sercomI2CM2 -) - -// SPI pins -const ( - SPI0_SCK_PIN = D25 // SCK: SERCOM1/PAD[1] - SPI0_SDO_PIN = D24 // SDO: SERCOM1/PAD[3] - SPI0_SDI_PIN = D23 // SDI: SERCOM1/PAD[2] -) - -// SPI on the Feather M4. -var SPI0 = sercomSPIM1 - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit Feather M4" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8022 -) diff --git a/emb/machine/board_feather-nrf52840-sense.go b/emb/machine/board_feather-nrf52840-sense.go deleted file mode 100644 index ab1c3fb..0000000 --- a/emb/machine/board_feather-nrf52840-sense.go +++ /dev/null @@ -1,105 +0,0 @@ -//go:build feather_nrf52840_sense - -package machine - -const HasLowFrequencyCrystal = false - -// GPIO Pins -const ( - D0 = P0_25 // UART TX - D1 = P0_24 // UART RX - D2 = P0_10 // NFC2 - D3 = P1_11 - D4 = P1_10 // LED2 - D5 = P1_08 - D6 = P0_07 - D7 = P1_02 // Button - D8 = P0_16 // NeoPixel - D9 = P0_26 - D10 = P0_27 - D11 = P0_06 - D12 = P0_08 - D13 = P1_09 // LED1 - D14 = P0_04 // A0 - D15 = P0_05 // A1 - D16 = P0_30 // A2 - D17 = P0_28 // A3 - D18 = P0_02 // A4 - D19 = P0_03 // A5 - D20 = P0_29 // Battery - D21 = P0_31 // AREF - D22 = P0_12 // I2C SDA - D23 = P0_11 // I2C SCL - D24 = P0_15 // SPI MISO - D25 = P0_13 // SPI MOSI - D26 = P0_14 // SPI SCK - D27 = P0_19 // QSPI CLK - D28 = P0_20 // QSPI CS - D29 = P0_17 // QSPI Data 0 - D30 = P0_22 // QSPI Data 1 - D31 = P0_23 // QSPI Data 2 - D32 = P0_21 // QSPI Data 3 - D33 = P0_09 // NFC1 (test point on bottom of board) -) - -// Analog Pins -const ( - A0 = D14 - A1 = D15 - A2 = D16 - A3 = D17 - A4 = D18 - A5 = D19 - A6 = D20 // Battery - A7 = D21 // ARef -) - -const ( - LED = D13 - LED1 = LED - LED2 = D4 - NEOPIXEL = D8 - WS2812 = D8 - BUTTON = D7 - - QSPI_SCK = D27 - QSPI_CS = D28 - QSPI_DATA0 = D29 - QSPI_DATA1 = D30 - QSPI_DATA2 = D31 - QSPI_DATA3 = D32 -) - -// UART0 pins (logical UART1) -const ( - UART_RX_PIN = D1 - UART_TX_PIN = D0 -) - -// I2C pins -const ( - SDA_PIN = D22 // I2C0 external - SCL_PIN = D23 // I2C0 external -) - -// SPI pins -const ( - SPI0_SCK_PIN = D26 // SCK - SPI0_SDO_PIN = D25 // SDO - SPI0_SDI_PIN = D24 // SDI -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Feather nRF52840 Express" - usb_STRING_MANUFACTURER = "Adafruit Industries LLC" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8088 -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_feather-nrf52840.go b/emb/machine/board_feather-nrf52840.go deleted file mode 100644 index 02fd053..0000000 --- a/emb/machine/board_feather-nrf52840.go +++ /dev/null @@ -1,105 +0,0 @@ -//go:build feather_nrf52840 - -package machine - -const HasLowFrequencyCrystal = true - -// GPIO Pins -const ( - D0 = P0_25 // UART TX - D1 = P0_24 // UART RX - D2 = P0_10 // NFC2 - D3 = P1_15 // LED1 - D4 = P1_10 // LED2 - D5 = P1_08 - D6 = P0_07 - D7 = P1_02 // Button - D8 = P0_16 // NeoPixel - D9 = P0_26 - D10 = P0_27 - D11 = P0_06 - D12 = P0_08 - D13 = P1_09 - D14 = P0_04 // A0 - D15 = P0_05 // A1 - D16 = P0_30 // A2 - D17 = P0_28 // A3 - D18 = P0_02 // A4 - D19 = P0_03 // A5 - D20 = P0_29 // Battery - D21 = P0_31 // AREF - D22 = P0_12 // I2C SDA - D23 = P0_11 // I2C SCL - D24 = P0_15 // SPI MISO - D25 = P0_13 // SPI MOSI - D26 = P0_14 // SPI SCK - D27 = P0_19 // QSPI CLK - D28 = P0_20 // QSPI CS - D29 = P0_17 // QSPI Data 0 - D30 = P0_22 // QSPI Data 1 - D31 = P0_23 // QSPI Data 2 - D32 = P0_21 // QSPI Data 3 - D33 = P0_09 // NFC1 (test point on bottom of board) -) - -// Analog Pins -const ( - A0 = D14 - A1 = D15 - A2 = D16 - A3 = D17 - A4 = D18 - A5 = D19 - A6 = D20 // Battery - A7 = D21 // ARef -) - -const ( - LED = D3 - LED1 = LED - LED2 = D4 - NEOPIXEL = D8 - WS2812 = D8 - BUTTON = D7 - - QSPI_SCK = D27 - QSPI_CS = D28 - QSPI_DATA0 = D29 - QSPI_DATA1 = D30 - QSPI_DATA2 = D31 - QSPI_DATA3 = D32 -) - -// UART0 pins (logical UART1) -const ( - UART_RX_PIN = D1 - UART_TX_PIN = D0 -) - -// I2C pins -const ( - SDA_PIN = D22 // I2C0 external - SCL_PIN = D23 // I2C0 external -) - -// SPI pins -const ( - SPI0_SCK_PIN = D26 // SCK - SPI0_SDO_PIN = D25 // SDO - SPI0_SDI_PIN = D24 // SDI -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Feather nRF52840 Express" - usb_STRING_MANUFACTURER = "Adafruit Industries LLC" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x802A -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_feather-stm32f405.go b/emb/machine/board_feather-stm32f405.go deleted file mode 100644 index 4a184ba..0000000 --- a/emb/machine/board_feather-stm32f405.go +++ /dev/null @@ -1,255 +0,0 @@ -//go:build feather_stm32f405 - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - NUM_DIGITAL_IO_PINS = 39 - NUM_ANALOG_IO_PINS = 7 -) - -// Digital pins -const ( - // Arduino pin = MCU port pin // primary functions (alternate functions) - D0 = PB11 // USART3 RX, PWM TIM2_CH4 (I2C2 SDA) - D1 = PB10 // USART3 TX, PWM TIM2_CH3 (I2C2 SCL, I2S2 BCK) - D2 = PB3 // GPIO, SPI3 FLASH SCK - D3 = PB4 // GPIO, SPI3 FLASH MISO - D4 = PB5 // GPIO, SPI3 FLASH MOSI - D5 = PC7 // GPIO, PWM TIM3_CH2 (USART6 RX, I2S3 MCK) - D6 = PC6 // GPIO, PWM TIM3_CH1 (USART6 TX, I2S2 MCK) - D7 = PA15 // GPIO, SPI3 FLASH CS - D8 = PC0 // GPIO, Neopixel - D9 = PB8 // GPIO, PWM TIM4_CH3 (CAN1 RX, I2C1 SCL) - D10 = PB9 // GPIO, PWM TIM4_CH4 (CAN1 TX, I2C1 SDA, I2S2 WSL) - D11 = PC3 // GPIO (I2S2 SD, SPI2 MOSI) - D12 = PC2 // GPIO (I2S2ext SD, SPI2 MISO) - D13 = PC1 // GPIO, Builtin LED - D14 = PB7 // I2C1 SDA, PWM TIM4_CH2 (USART1 RX) - D15 = PB6 // I2C1 SCL, PWM TIM4_CH1 (USART1 TX, CAN2 TX) - D16 = PA4 // A0 (DAC OUT1) - D17 = PA5 // A1 (DAC OUT2, SPI1 SCK) - D18 = PA6 // A2, PWM TIM3_CH1 (SPI1 MISO) - D19 = PA7 // A3, PWM TIM3_CH2 (SPI1 MOSI) - D20 = PC4 // A4 - D21 = PC5 // A5 - D22 = PA3 // A6 - D23 = PB13 // SPI2 SCK, PWM TIM1_CH1N (I2S2 BCK, CAN2 TX) - D24 = PB14 // SPI2 MISO, PWM TIM1_CH2N (I2S2ext SD) - D25 = PB15 // SPI2 MOSI, PWM TIM1_CH3N (I2S2 SD) - D26 = PC8 // SDIO - D27 = PC9 // SDIO - D28 = PC10 // SDIO - D29 = PC11 // SDIO - D30 = PC12 // SDIO - D31 = PD2 // SDIO - D32 = PB12 // SD Detect - D33 = PC14 // OSC32 - D34 = PC15 // OSC32 - D35 = PA11 // USB D+ - D36 = PA12 // USB D- - D37 = PA13 // SWDIO - D38 = PA14 // SWCLK -) - -// Analog pins -const ( - A0 = D16 // ADC12 IN4 - A1 = D17 // ADC12 IN5 - A2 = D18 // ADC12 IN6 - A3 = D19 // ADC12 IN7 - A4 = D20 // ADC12 IN14 - A5 = D21 // ADC12 IN15 - A6 = D22 // VBAT -) - -func init() { - initLED() - initUART() - initSPI() - initI2C() -} - -// -- LEDs --------------------------------------------------------------------- - -const ( - NUM_BOARD_LED = 1 - NUM_BOARD_NEOPIXEL = 1 - - LED_RED = D13 - LED_NEOPIXEL = D8 - LED_BUILTIN = LED_RED - LED = LED_BUILTIN - WS2812 = D8 -) - -func initLED() {} - -// -- UART --------------------------------------------------------------------- - -const ( - // #===========#==========#==============#============#=======#=======# - // | Interface | Hardware | Bus(Freq) | RX/TX Pins | AltFn | Alias | - // #===========#==========#==============#============#=======#=======# - // | UART1 | USART3 | APB1(42 MHz) | D0/D1 | 7 | ~ | - // | UART2 | USART6 | APB2(84 MHz) | D5/D6 | 8 | ~ | - // | UART3 | USART1 | APB2(84 MHz) | D14/D15 | 7 | ~ | - // | --------- | -------- | ------------ | ---------- | ----- | ----- | - // | UART0 | USART3 | APB1(42 MHz) | D0/D1 | 7 | UART1 | - // #===========#==========#==============#============#=======#=======# - NUM_UART_INTERFACES = 3 - - UART1_RX_PIN = D0 // UART1 = hardware: USART3 - UART1_TX_PIN = D1 // - - UART2_RX_PIN = D5 // UART2 = hardware: USART6 - UART2_TX_PIN = D6 // - - UART3_RX_PIN = D14 // UART3 = hardware: USART1 - UART3_TX_PIN = D15 // - - UART0_RX_PIN = UART1_RX_PIN // UART0 = alias: UART1 - UART0_TX_PIN = UART1_TX_PIN // - - UART_RX_PIN = UART0_RX_PIN // default/primary UART pins - UART_TX_PIN = UART0_TX_PIN // -) - -var ( - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART3, - TxAltFuncSelector: AF7_USART1_2_3, - RxAltFuncSelector: AF7_USART1_2_3, - } - UART2 = &_UART2 - _UART2 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART6, - TxAltFuncSelector: AF8_USART4_5_6, - RxAltFuncSelector: AF8_USART4_5_6, - } - UART3 = &_UART3 - _UART3 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART1, - TxAltFuncSelector: AF7_USART1_2_3, - RxAltFuncSelector: AF7_USART1_2_3, - } - DefaultUART = UART1 -) - -func initUART() { - UART1.Interrupt = interrupt.New(stm32.IRQ_USART3, _UART1.handleInterrupt) - UART2.Interrupt = interrupt.New(stm32.IRQ_USART6, _UART2.handleInterrupt) - UART3.Interrupt = interrupt.New(stm32.IRQ_USART1, _UART3.handleInterrupt) -} - -// -- SPI ---------------------------------------------------------------------- - -const ( - // #===========#==========#==============#==================#=======#=======# - // | Interface | Hardware | Bus(Freq) | SCK/SDI/SDO Pins | AltFn | Alias | - // #===========#==========#==============#==================#=======#=======# - // | SPI1 | SPI2 | APB1(42 MHz) | D23/D24/D25 | 5 | ~ | - // | SPI2 | SPI3 | APB1(42 MHz) | D2/D3/D4 | 6 | ~ | - // | SPI3 | SPI1 | APB2(84 MHz) | D17/D18/D19 | 5 | ~ | - // | --------- | -------- | ------------ | ---------------- | ----- | ----- | - // | SPI0 | SPI2 | APB1(42 MHz) | D23/D24/D25 | 5 | SPI1 | - // #===========#==========#==============#==================#=======#=======# - NUM_SPI_INTERFACES = 3 - - SPI1_SCK_PIN = D23 // - SPI1_SDI_PIN = D24 // SPI1 = hardware: SPI2 - SPI1_SDO_PIN = D25 // - - SPI2_SCK_PIN = D2 // - SPI2_SDI_PIN = D3 // SPI2 = hardware: SPI3 - SPI2_SDO_PIN = D4 // - - SPI3_SCK_PIN = D17 // - SPI3_SDI_PIN = D18 // SPI3 = hardware: SPI1 - SPI3_SDO_PIN = D19 // - - SPI0_SCK_PIN = SPI1_SCK_PIN // - SPI0_SDI_PIN = SPI1_SDI_PIN // SPI0 = alias: SPI1 - SPI0_SDO_PIN = SPI1_SDO_PIN // - - SPI_SCK_PIN = SPI0_SCK_PIN // - SPI_SDI_PIN = SPI0_SDI_PIN // default/primary SPI pins - SPI_SDO_PIN = SPI0_SDO_PIN // -) - -var ( - SPI1 = &SPI{ - Bus: stm32.SPI2, - AltFuncSelector: AF5_SPI1_SPI2, - } - SPI2 = &SPI{ - Bus: stm32.SPI3, - AltFuncSelector: AF6_SPI3, - } - SPI3 = &SPI{ - Bus: stm32.SPI1, - AltFuncSelector: AF5_SPI1_SPI2, - } - SPI0 = SPI1 -) - -func initSPI() {} - -// -- I2C ---------------------------------------------------------------------- - -const ( - // #===========#==========#==============#==============#=======#=======# - // | Interface | Hardware | Bus(Freq) | SDA/SCL Pins | AltFn | Alias | - // #===========#==========#==============#==============#=======#=======# - // | I2C1 | I2C1 | APB1(42 MHz) | D14/D15 | 4 | ~ | - // | I2C2 | I2C2 | APB1(42 MHz) | D0/D1 | 4 | ~ | - // | I2C3 | I2C1 | APB1(42 MHz) | D9/D10 | 4 | ~ | - // | --------- | -------- | ------------ | ------------ | ----- | ----- | - // | I2C0 | I2C1 | APB1(42 MHz) | D14/D15 | 4 | I2C1 | - // #===========#==========#==============#==============#=======#=======# - NUM_I2C_INTERFACES = 3 - - I2C1_SDA_PIN = D14 // I2C1 = hardware: I2C1 - I2C1_SCL_PIN = D15 // - - I2C2_SDA_PIN = D0 // I2C2 = hardware: I2C2 - I2C2_SCL_PIN = D1 // - - I2C3_SDA_PIN = D9 // I2C3 = hardware: I2C1 - I2C3_SCL_PIN = D10 // (interface duplicated on second pair of pins) - - I2C0_SDA_PIN = I2C1_SDA_PIN // I2C0 = alias: I2C1 - I2C0_SCL_PIN = I2C1_SCL_PIN // - - I2C_SDA_PIN = I2C0_SDA_PIN // default/primary I2C pins - I2C_SCL_PIN = I2C0_SCL_PIN // - - SDA_PIN = I2C0_SDA_PIN - SCL_PIN = I2C0_SCL_PIN -) - -var ( - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: AF4_I2C1_2_3, - } - I2C2 = &I2C{ - Bus: stm32.I2C2, - AltFuncSelector: AF4_I2C1_2_3, - } - I2C3 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: AF4_I2C1_2_3, - } - I2C0 = I2C1 -) - -func initI2C() {} diff --git a/emb/machine/board_feather_rp2040.go b/emb/machine/board_feather_rp2040.go deleted file mode 100644 index 44091e5..0000000 --- a/emb/machine/board_feather_rp2040.go +++ /dev/null @@ -1,82 +0,0 @@ -//go:build feather_rp2040 - -package machine - -// Onboard crystal oscillator frequency, in MHz. -const xoscFreq = 12 // MHz - -// GPIO Pins -const ( - D4 = GPIO6 - D5 = GPIO7 - D6 = GPIO8 - D9 = GPIO9 - D10 = GPIO10 - D11 = GPIO11 - D12 = GPIO12 - D13 = GPIO13 - D24 = GPIO24 - D25 = GPIO25 -) - -// Analog pins -const ( - A0 = GPIO26 - A1 = GPIO27 - A2 = GPIO28 - A3 = GPIO29 -) - -const LED = GPIO13 - -// I2C Pins. -const ( - I2C0_SDA_PIN = GPIO24 - I2C0_SCL_PIN = GPIO25 - - I2C1_SDA_PIN = GPIO2 - I2C1_SCL_PIN = GPIO3 - - SDA_PIN = I2C1_SDA_PIN - SCL_PIN = I2C1_SCL_PIN -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO18 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO19 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO20 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO10 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO11 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO12 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO8 - UART1_RX_PIN = GPIO9 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Feather RP2040" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x80F1 -) diff --git a/emb/machine/board_gemma-m0.go b/emb/machine/board_gemma-m0.go deleted file mode 100644 index af1caaa..0000000 --- a/emb/machine/board_gemma-m0.go +++ /dev/null @@ -1,97 +0,0 @@ -//go:build sam && atsamd21 && gemma_m0 - -package machine - -// Used to reset into bootloader. -const resetMagicValue = 0xf01669ef - -// GPIO Pins. -const ( - D0 = PA04 // SERCOM0/PAD[0] - D1 = PA02 - D2 = PA05 // SERCOM0/PAD[1] - D3 = PA00 // DotStar LED: SERCOM1/PAD[0]: APA102/MOSI - D4 = PA01 // DotStar LED: SERCOM1/PAD[1]: APA102/SCK - D11 = PA30 // Flash Access: SERCOM1/PAD[2] - D12 = PA31 // Flash Access: SERCOM1/PAD[3] - D13 = PA23 // LED: SERCOM3/PAD[1] SERCOM5/PAD[1] -) - -// Analog pins. -const ( - A0 = D1 - A1 = D2 - A2 = D0 -) - -const ( - LED = PA23 -) - -// USBCDC pins. -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART0 pins. -const ( - UART_TX_PIN = PA04 // TX: SERCOM0/PAD[0] - UART_RX_PIN = PA05 // RX: SERCOM0/PAD[1] -) - -// UART0s on the Gemma M0. -var UART0 = &sercomUSART0 - -// SPI pins. -const ( - SPI0_SCK_PIN = PA05 // SCK: SERCOM0/PAD[1] - SPI0_SDO_PIN = PA04 // MOSI: SERCOM0/PAD[0] - SPI0_SDI_PIN = NoPin - SPI0_CS_PIN = NoPin -) - -// SPI on the Gemma M0. -var SPI0 = sercomSPIM0 - -// SPI pins for DotStar LED (using APA102 software SPI) and Flash. -const ( - SPI1_SCK_PIN = PA01 // SCK: SERCOM1/PAD[0] - SPI1_SDO_PIN = PA00 // MOSI: SERCOM1/PAD[1] - SPI1_SDI_PIN = PA31 // MISO: SERCOM1/PAD[3] - SPI1_CS_PIN = PA30 // CS: SERCOM1/PAD[2] -) - -// I2C pins. -const ( - SDA_PIN = PA04 // SDA: SERCOM0/PAD[0] - SCL_PIN = PA05 // SCL: SERCOM0/PAD[1] -) - -// I2C on the Gemma M0. -var ( - I2C0 = sercomI2CM0 -) - -// I2S (not connected, needed for atsamd21). -const ( - I2S_SCK_PIN = NoPin - I2S_SDO_PIN = NoPin - I2S_SDI_PIN = NoPin - I2S_WS_PIN = NoPin -) - -// USB CDC identifiers. -const ( - usb_STRING_PRODUCT = "Adafruit Gemma M0" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x801E -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_gnse.go b/emb/machine/board_gnse.go deleted file mode 100644 index 8e78b43..0000000 --- a/emb/machine/board_gnse.go +++ /dev/null @@ -1,88 +0,0 @@ -//go:build gnse - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - LED_RED = PB5 - LED_GREEN = PB6 - LED_BLUE = PB7 - LED1 = LED_RED // Red - LED2 = LED_GREEN // Green - LED3 = LED_BLUE // Blue - LED = LED_GREEN // Default - - BUTTON = PB3 - BUZZER = PA15 - VBATT_ADC = PB2 - SENSOR_EN = PB12 - FLASH_EN = PC13 - - // SPI0 - SPI0_NSS_PIN = PA4 - SPI0_SCK_PIN = PA5 - SPI0_SDO_PIN = PA6 - SPI0_SDI_PIN = PA7 - - //MCU USART2 - UART2_RX_PIN = PA3 - UART2_TX_PIN = PA2 - - // DEFAULT USART - UART_RX_PIN = UART2_RX_PIN - UART_TX_PIN = UART2_TX_PIN - - // I2C1 pins - // I2C1 is connected to Flash, Accelerometer, Env. Sensor, Crypto Element) - I2C1_SCL_PIN = PA9 - I2C1_SDA_PIN = PA10 - I2C1_ALT_FUNC = 4 - - // I2C2 pins - // I2C2 is expansion J10 QWIIC Connector - I2C2_SCL_PIN = PA12 - I2C2_SDA_PIN = PA11 - I2C2_ALT_FUNC = 4 - - // I2C0 alias for I2C1 - I2C0_SDA_PIN = I2C1_SDA_PIN - I2C0_SCL_PIN = I2C1_SCL_PIN -) - -var ( - // STM32 UART2 is connected to the embedded STLINKV3 Virtual Com Port - UART0 = &_UART0 - _UART0 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART2, - TxAltFuncSelector: 7, - RxAltFuncSelector: 7, - } - - DefaultUART = UART0 - - // I2C Busses - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: I2C1_ALT_FUNC, - } - I2C2 = &I2C{ - Bus: stm32.I2C2, - AltFuncSelector: I2C2_ALT_FUNC, - } - I2C0 = I2C1 - - // SPI - SPI3 = &SPI{ - Bus: stm32.SPI3, - } -) - -func init() { - // Enable UARTs Interrupts - UART0.Interrupt = interrupt.New(stm32.IRQ_USART2, _UART0.handleInterrupt) -} diff --git a/emb/machine/board_gopher-badge.go b/emb/machine/board_gopher-badge.go deleted file mode 100644 index 7af2711..0000000 --- a/emb/machine/board_gopher-badge.go +++ /dev/null @@ -1,90 +0,0 @@ -//go:build gopher_badge - -// This contains the pin mappings for the Gopher Badge. -// -// For more information, see: https://gopherbadge.com/ -package machine - -const ( - /*ADC0 Pin = GPIO26 - ADC1 Pin = GPIO27 - ADC2 Pin = GPIO28 - GPIO4 Pin = GPIO4 - GPIO5 Pin = GPIO5 - GPIO6 Pin = GPIO6 - GPIO7 Pin = GPIO7 - GPIO8 Pin = GPIO8 - GPIO9 Pin = GPIO9*/ - - PENIRQ Pin = GPIO13 - - LED Pin = GPIO2 - NEOPIXELS Pin = GPIO15 - WS2812 Pin = GPIO15 - - BUTTON_A Pin = GPIO10 - BUTTON_B Pin = GPIO11 - BUTTON_LEFT Pin = GPIO25 - BUTTON_UP Pin = GPIO24 - BUTTON_RIGHT Pin = GPIO22 - BUTTON_DOWN Pin = GPIO23 - - TFT_RST Pin = GPIO21 - TFT_SDI Pin = GPIO19 - TFT_SDO Pin = GPIO16 - TFT_CS Pin = GPIO17 - TFT_SCL Pin = GPIO18 - TFT_WRX Pin = GPIO20 - TFT_BACKLIGHT Pin = GPIO12 - - SPEAKER Pin = GPIO14 - SPEAKER_ENABLE Pin = GPIO3 -) - -// I2C pins -const ( - I2C0_SDA_PIN Pin = GPIO0 - I2C0_SCL_PIN Pin = GPIO1 - - I2C1_SDA_PIN Pin = NoPin - I2C1_SCL_PIN Pin = NoPin -) - -// SPI pins. -const ( - SPI0_SCK_PIN Pin = GPIO18 - SPI0_SDO_PIN Pin = GPIO19 - SPI0_SDI_PIN Pin = GPIO16 - - SPI1_SCK_PIN Pin = NoPin - SPI1_SDO_PIN Pin = NoPin - SPI1_SDI_PIN Pin = NoPin -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Gopher Badge" - usb_STRING_MANUFACTURER = "TinyGo" -) - -var ( - usb_VID uint16 = 0x2e8a - usb_PID uint16 = 0x0003 -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO4 - UART1_RX_PIN = GPIO5 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART1 diff --git a/emb/machine/board_grandcentral-m4.go b/emb/machine/board_grandcentral-m4.go deleted file mode 100644 index 61ef6a8..0000000 --- a/emb/machine/board_grandcentral-m4.go +++ /dev/null @@ -1,267 +0,0 @@ -//go:build grandcentral_m4 - -package machine - -// Digital pins -const ( - // = Pin Alt. Function SERCOM PWM Timer Interrupt - // ------ -------------------- -------- ----------- ----------- - D0 = PB25 // UART1 RX 0[1] EXTI9 - D1 = PB24 // UART1 TX 0[0] EXTI8 - D2 = PC18 // TCC0[2] EXTI2 - D3 = PC19 // TCC0[3] EXTI3 - D4 = PC20 // TCC0[4] EXTI4 - D5 = PC21 // TCC0[5] EXTI5 - D6 = PD20 // TCC1[0] EXTI10 - D7 = PD21 // TCC1[1] EXTI11 - D8 = PB18 // TCC1[0] EXTI2 - D9 = PB02 // TC6[0] EXTI3 - D10 = PB22 // TC7[0] EXTI6 - D11 = PB23 // EXTI7 - D12 = PB00 // TC7[0] EXTI0 - D13 = PB01 // On-board LED TC7[1] EXTI1 - D14 = PB16 // UART4 TX, I2S0 SCK 5[0] TC6[0] EXTI0 - D15 = PB17 // UART4 RX, I2S0 MCK 5[1] EXTI1 - D16 = PC22 // UART3 TX 1[0] EXTI6 - D17 = PC23 // UART3 RX 1[1] EXTI6 - D18 = PB12 // UART2 TX 4[0] TCC3[0] EXTI12 - D19 = PB13 // UART2 RX 4[1] TCC3[1] EXTI13 - D20 = PB20 // I2C0 SDA 3[0] EXTI4 - D21 = PB21 // I2C0 SCL 3[1] EXTI5 - D22 = PD12 // EXTI7 - D23 = PA15 // TCC2[1] EXTI15 - D24 = PC17 // I2C1 SCL 6[1] TCC0[1] EXTI1 - D25 = PC16 // I2C1 SDA 6[0] TCC0[0] EXTI0 - D26 = PA12 // PCC DEN1 TC2[0] EXTI12 - D27 = PA13 // PCC DEN2 TC2[1] EXTI13 - D28 = PA14 // PCC CLK TCC2[0] EXTI14 - D29 = PB19 // PCC XCLK EXTI3 - D30 = PA23 // PCC D7 TC4[1] EXTI7 - D31 = PA22 // PCC D6, I2S0 SDI TC4[0] EXTI6 - D32 = PA21 // PCC D5, I2S0 SDO EXTI5 - D33 = PA20 // PCC D4, I2S0 FS EXTI4 - D34 = PA19 // PCC D3 TC3[1] EXTI3 - D35 = PA18 // PCC D2 TC3[0] EXTI2 - D36 = PA17 // PCC D1 EXTI1 - D37 = PA16 // PCC D0 EXTI0 - D38 = PB15 // PCC D9 TCC4[1] EXTI15 - D39 = PB14 // PCC D8 TCC4[0] EXTI14 - D40 = PC13 // PCC D11 EXTI13 - D41 = PC12 // PCC D10 EXTI12 - D42 = PC15 // PCC D13 EXTI15 - D43 = PC14 // PCC D12 EXTI14 - D44 = PC11 // EXTI11 - D45 = PC10 // EXTI10 - D46 = PC06 // EXTI6 - D47 = PC07 // EXTI5 - D48 = PC04 // EXTI4 - D49 = PC05 // EXTI5 - D50 = PD11 // SPI0 SDI 7[3] EXTI11 - D51 = PD08 // SPI0 SDO 7[0] EXTI8 - D52 = PD09 // SPI0 SCK 7[1] EXTI9 - D53 = PD10 // SPI0 CS EXTI10 - D54 = PB05 // ADC1 (A8) EXTI5 - D55 = PB06 // ADC1 (A9) EXTI6 - D56 = PB07 // ADC1 (A10) EXTI7 - D57 = PB08 // ADC1 (A11) EXTI8 - D58 = PB09 // ADC1 (A12) EXTI9 - D59 = PA04 // ADC0 (A13) TC0[0] EXTI4 - D60 = PA06 // ADC0 (A14) TC1[0] EXTI6 - D61 = PA07 // ADC0 (A15) TC1[1] EXTI7 - D62 = PB20 // I2C0 SDA 3[0] TCC1[2] EXTI4 - D63 = PB21 // I2C0 SCL 3[1] TCC1[3] EXTI5 - D64 = PD11 // SPI0 SDI 7[3] EXTI6 - D65 = PD08 // SPI0 SDO 7[0] EXTI3 - D66 = PD09 // SPI0 SCK 7[1] EXTI4 - D67 = PA02 // ADC0 (A0), DAC0 EXTI2 - D68 = PA05 // ADC0 (A1), DAC1 EXTI5 - D69 = PB03 // ADC0 (A2) TC6[1] EXTI3 - D70 = PC00 // ADC1 (A3) EXTI0 - D71 = PC01 // ADC1 (A4) EXTI1 - D72 = PC02 // ADC1 (A5) EXTI2 - D73 = PC03 // ADC1 (A6) EXTI3 - D74 = PB04 // ADC1 (A7) EXTI4 - D75 = PC31 // UART RX LED - D76 = PC30 // UART TX LED - D77 = PA27 // USB HOST EN - D78 = PA24 // USB DM EXTI8 - D79 = PA25 // USB DP EXTI9 - D80 = PB29 // SD/SPI1 SDI 2[3] - D81 = PB27 // SD/SPI1 SCK 2[1] - D82 = PB26 // SD/SPI1 SDO 2[0] - D83 = PB28 // SD/SPI1 CS - D84 = PA03 // AREF EXTI3 - D85 = PA02 // DAC0 EXTI2 - D86 = PA05 // DAC1 EXTI5 - D87 = PB01 // On-board LED (D13) TC7[1] EXTI1 - D88 = PC24 // On-board NeoPixel - D89 = PB10 // QSPI SCK EXTI10 - D90 = PB11 // QSPI CS EXTI11 - D91 = PA08 // QSPI ID0 EXTI(NMI) - D92 = PA09 // QSPI ID1 EXTI9 - D93 = PA10 // QSPI ID2 EXTI10 - D94 = PA11 // QSPI ID3 EXTI11 - D95 = PB31 // SD Detect EXTI15 - D96 = PB30 // SWO EXTI14 -) - -// Analog pins -const ( - A0 = D67 // (PA02) ADC0 ch. 0, - A1 = D68 // (PA05) ADC0 ch. 5, - A2 = D69 // (PB03) ADC0 ch. 15 - A3 = D70 // (PC00) ADC1 ch. 10 - A4 = D71 // (PC01) ADC1 ch. 11 - A5 = D72 // (PC02) ADC1 ch. 4 - A6 = D73 // (PC03) ADC1 ch. 5 - A7 = D74 // (PB04) ADC1 ch. 6 - A8 = D54 // (PB05) ADC1 ch. 7 - A9 = D55 // (PB06) ADC1 ch. 8 - A10 = D56 // (PB07) ADC1 ch. 9 - A11 = D57 // (PB08) ADC1 ch. 0 - A12 = D58 // (PB09) ADC1 ch. 1 - A13 = D59 // (PA04) ADC0 ch. 4 - A14 = D60 // (PA06) ADC0 ch. 6 - A15 = D61 // (PA07) ADC0 ch. 7 - - AREF = D84 // (PA03) -) - -// LED pins -const ( - LED_PIN = D13 // (PB01), also on D87 - UART_RX_LED_PIN = D75 // (PC31) - UART_TX_LED_PIN = D76 // (PC30) - NEOPIXEL_PIN = D88 // (PC24) - - // aliases used by examples and drivers - LED = LED_PIN - LED_RX = UART_RX_LED_PIN - LED_TX = UART_TX_LED_PIN - NEOPIXEL = NEOPIXEL_PIN - WS2812 = NEOPIXEL_PIN -) - -// UART pins -const ( - UART1_RX_PIN = D0 // (PB25) - UART1_TX_PIN = D1 // (PB24) - - UART2_RX_PIN = D19 // (PB13) - UART2_TX_PIN = D18 // (PB12) - - UART3_RX_PIN = D17 // (PC23) - UART3_TX_PIN = D16 // (PC22) - - UART4_RX_PIN = D15 // (PB17) - UART4_TX_PIN = D14 // (PB16) - - UART_RX_PIN = UART1_RX_PIN // default pins - UART_TX_PIN = UART1_TX_PIN // -) - -// UART on the Grand Central M4 -var ( - UART1 = &sercomUSART0 - UART2 = &sercomUSART4 - UART3 = &sercomUSART1 - UART4 = &sercomUSART5 - - DefaultUART = UART1 -) - -// SPI pins -const ( - SPI0_SCK_PIN = D66 // (PD09), also on D52 - SPI0_SDO_PIN = D65 // (PD08), also on D51 - SPI0_SDI_PIN = D64 // (PD11), also on D50 - SPI0_CS_PIN = D53 // (PD10) - - SPI1_SCK_PIN = D81 // (PB27) - SPI1_SDO_PIN = D82 // (PB26) - SPI1_SDI_PIN = D80 // (PB29) - - SPI_SCK_PIN = SPI0_SCK_PIN // default pins - SPI_SDO_PIN = SPI0_SDO_PIN // - SPI_SDI_PIN = SPI0_SDI_PIN // - SPI_CS_PIN = SPI0_CS_PIN // -) - -// SPI on the Grand Central M4 -var ( - SPI0 = sercomSPIM7 - SPI1 = sercomSPIM2 // SD card -) - -// I2C pins -const ( - I2C0_SDA_PIN = D62 // (PB20), also on D20 - I2C0_SCL_PIN = D63 // (PB21), also on D21 - - I2C1_SDA_PIN = D25 // (PC16) - I2C1_SCL_PIN = D24 // (PC17) - - I2C_SDA_PIN = I2C0_SDA_PIN // default pins - I2C_SCL_PIN = I2C0_SCL_PIN // - - SDA_PIN = I2C_SDA_PIN // unconventional pin names - SCL_PIN = I2C_SCL_PIN // (required by machine_atsamd51.go) -) - -// I2C on the Grand Central M4 -var ( - I2C0 = sercomI2CM3 - I2C1 = sercomI2CM6 -) - -// I2S pins -const ( - I2S0_SCK_PIN = D14 // (PB16) - I2S0_MCK_PIN = D15 // (PB17) - I2S0_FS_PIN = D33 // (PA20) - I2S0_SDO_PIN = D32 // (PA21) - I2S0_SDI_PIN = D31 // (PA22) - - I2S_SCK_PIN = I2S0_SCK_PIN // default pins - I2S_WS_PIN = I2S0_FS_PIN // - I2S_SDO_PIN = I2S0_SDO_PIN - I2S_SDI_PIN = NoPin -) - -// SD card pins -const ( - SD0_SCK_PIN = D81 // (PB27) - SD0_SDO_PIN = D82 // (PB26) - SD0_SDI_PIN = D80 // (PB29) - SD0_CS_PIN = D83 // (PB28) - SD0_DET_PIN = D95 // (PB31) - - SDCARD_SCK_PIN = SD0_SCK_PIN // default pins - SDCARD_SDO_PIN = SD0_SDO_PIN // - SDCARD_SDI_PIN = SD0_SDI_PIN // - SDCARD_CS_PIN = SD0_CS_PIN // - SDCARD_DET_PIN = SD0_DET_PIN // -) - -// Other peripheral constants -const ( - resetMagicValue = 0xF01669EF // Used to reset into bootloader -) - -// USB CDC pins -const ( - USBCDC_HOSTEN_PIN = D77 // (PA27) host enable - USBCDC_DM_PIN = D78 // (PA24) D- - USBCDC_DP_PIN = D79 // (PA25) D+ -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit Grand Central M4" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8031 -) diff --git a/emb/machine/board_hifive1b.go b/emb/machine/board_hifive1b.go deleted file mode 100644 index a38b6c0..0000000 --- a/emb/machine/board_hifive1b.go +++ /dev/null @@ -1,61 +0,0 @@ -//go:build hifive1b - -package machine - -const ( - D0 = P16 - D1 = P17 - D2 = P18 - D3 = P19 // Green LED/PWM (PWM1_PWM1) - D4 = P20 // PWM (PWM1_PWM0) - D5 = P21 // Blue LED/PWM (PWM1_PWM2) - D6 = P22 // Red LED/PWM (PWM1_PWM3) - D7 = P16 - D8 = NoPin // PWM? - D9 = P01 - D10 = P02 // SPI1_CS0 - D11 = P03 // SPI1_DQ0 - D12 = P04 // SPI1_DQ1 - D13 = P05 // SPI1_SCK - D14 = NoPin // not connected - D15 = P09 // does not seem to work? - D16 = P10 // PWM (PWM2_PWM0) - D17 = P11 // PWM (PWM2_PWM1) - D18 = P12 // SDA (I2C0_SDA)/PWM (PWM2_PWM2) - D19 = P13 // SDL (I2C0_SCL)/PWM (PWM2_PWM3) -) - -const ( - LED = LED1 - LED1 = LED_RED - LED2 = LED_GREEN - LED3 = LED_BLUE - LED_RED = P22 - LED_GREEN = P19 - LED_BLUE = P21 -) - -var DefaultUART = UART0 - -const ( - // TODO: figure out the pin numbers for these. - UART_TX_PIN = D1 - UART_RX_PIN = D0 -) - -// SPI pins -const ( - SPI0_SCK_PIN = NoPin - SPI0_SDO_PIN = NoPin - SPI0_SDI_PIN = NoPin - - SPI1_SCK_PIN = D13 - SPI1_SDO_PIN = D11 - SPI1_SDI_PIN = D12 -) - -// I2C pins -const ( - I2C0_SDA_PIN = D18 - I2C0_SCL_PIN = D19 -) diff --git a/emb/machine/board_hifive1b_baremetal.go b/emb/machine/board_hifive1b_baremetal.go deleted file mode 100644 index f621d3b..0000000 --- a/emb/machine/board_hifive1b_baremetal.go +++ /dev/null @@ -1,12 +0,0 @@ -//go:build fe310 && hifive1b - -package machine - -import "device/sifive" - -// SPI on the HiFive1. -var ( - SPI1 = &SPI{ - Bus: sifive.QSPI1, - } -) diff --git a/emb/machine/board_hw-651.go b/emb/machine/board_hw-651.go deleted file mode 100644 index 5473150..0000000 --- a/emb/machine/board_hw-651.go +++ /dev/null @@ -1,77 +0,0 @@ -//go:build hw_651 - -package machine - -// No-name brand board based on the nRF51822 chip with low frequency crystal on board. -// Pinout (reverse engineered from the board) can be found here: -// https://aviatorahmet.blogspot.com/2020/12/pinout-of-nrf51822-board.html -// https://cr0wg4n.medium.com/pinout-nrf51822-board-hw-651-78da2eda8894 - -const HasLowFrequencyCrystal = true - -var DefaultUART = UART0 - -// GPIO pins on header J1 -const ( - J1_01 = P0_21 - J1_03 = P0_23 - J1_04 = P0_22 - J1_05 = P0_25 - J1_06 = P0_24 - J1_09 = P0_29 - J1_10 = P0_28 - J1_11 = P0_30 - J1_13 = P0_00 - J1_15 = P0_02 - J1_17 = P0_04 - J1_16 = P0_01 - J1_18 = P0_03 -) - -// GPIO pins on header J2 -const ( - J2_01 = P0_20 - J2_03 = P0_18 - J2_04 = P0_19 - J2_07 = P0_16 - J2_08 = P0_15 - J2_09 = P0_14 - J2_10 = P0_13 - J2_11 = P0_12 - J2_12 = P0_11 - J2_13 = P0_10 - J2_14 = P0_09 - J2_15 = P0_08 - J2_16 = P0_07 - J2_17 = P0_06 - J2_18 = P0_05 -) - -// UART pins -const ( - UART_TX_PIN = P0_24 // J1_06 on the board - UART_RX_PIN = P0_25 // J1_05 on the board -) - -// ADC pins -const ( - ADC0 = P0_03 // J1_18 on the board - ADC1 = P0_02 // J1_15 on the board - ADC2 = P0_01 // J1_16 on the board - ADC3 = P0_04 // J1_17 on the board - ADC4 = P0_05 // J2_18 on the board - ADC5 = P0_06 // J2_17 on the board -) - -// I2C pins -const ( - SDA_PIN = P0_30 // J1_11 on the board - SCL_PIN = P0_00 // J1_13 on the board -) - -// SPI pins -const ( - SPI0_SCK_PIN = P0_23 // J1_03 on the board - SPI0_SDO_PIN = P0_21 // J1_01 on the board - SPI0_SDI_PIN = P0_22 // J1_04 on the board -) diff --git a/emb/machine/board_itsybitsy-m0.go b/emb/machine/board_itsybitsy-m0.go deleted file mode 100644 index 0cc6cad..0000000 --- a/emb/machine/board_itsybitsy-m0.go +++ /dev/null @@ -1,110 +0,0 @@ -//go:build sam && atsamd21 && itsybitsy_m0 - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PA11 // UART0 RX - D1 = PA10 // UART0 TX - D2 = PA14 - D3 = PA09 // PWM available - D4 = PA08 // PWM available - D5 = PA15 // PWM available - D6 = PA20 // PWM available - D7 = PA21 // PWM available - D8 = PA06 // PWM available - D9 = PA07 // PWM available - D10 = PA18 // can be used for PWM or UART1 TX - D11 = PA16 // can be used for PWM or UART1 RX - D12 = PA19 // PWM available - D13 = PA17 // PWM available -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PB08 // ADC/AIN[2] - A2 = PB09 // ADC/AIN[3] - A3 = PA04 // ADC/AIN[4] - A4 = PA05 // ADC/AIN[5] - A5 = PB02 // ADC/AIN[10] -) - -const ( - LED = D13 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN = D10 - UART_RX_PIN = D11 -) - -// UART1 on the ItsyBitsy M0. -var ( - UART1 = &sercomUSART1 -) - -// I2C pins -const ( - SDA_PIN = PA22 // SDA: SERCOM3/PAD[0] - SCL_PIN = PA23 // SCL: SERCOM3/PAD[1] -) - -// I2C on the ItsyBitsy M0. -var ( - I2C0 = sercomI2CM3 -) - -// SPI pins -const ( - SPI0_SCK_PIN = PB11 // SCK: SERCOM4/PAD[3] - SPI0_SDO_PIN = PB10 // SDO: SERCOM4/PAD[2] - SPI0_SDI_PIN = PA12 // SDI: SERCOM4/PAD[0] -) - -// SPI on the ItsyBitsy M0. -var SPI0 = sercomSPIM4 - -// "Internal" SPI pins; SPI flash is attached to these on ItsyBitsy M0 -const ( - SPI1_CS_PIN = PA27 - SPI1_SCK_PIN = PB23 - SPI1_SDO_PIN = PB22 - SPI1_SDI_PIN = PB03 -) - -// "Internal" SPI on Sercom 5 -var SPI1 = sercomSPIM5 - -// I2S pins -const ( - I2S_SCK_PIN = PA10 - I2S_SDO_PIN = PA08 - I2S_SDI_PIN = NoPin - I2S_WS_PIN = NoPin // TODO: figure out what this is on ItsyBitsy M0. -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit ItsyBitsy M0 Express" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x800F -) - -var ( - DefaultUART = UART1 -) diff --git a/emb/machine/board_itsybitsy-m4.go b/emb/machine/board_itsybitsy-m4.go deleted file mode 100644 index 687538e..0000000 --- a/emb/machine/board_itsybitsy-m4.go +++ /dev/null @@ -1,94 +0,0 @@ -//go:build itsybitsy_m4 - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PA16 // UART0 RX/PWM available - D1 = PA17 // UART0 TX/PWM available - D2 = PA07 - D3 = PB22 - D4 = PA14 // PWM available - D5 = PA15 // PWM available - D6 = PB02 // dotStar clock - D7 = PA18 // PWM available - D8 = PB03 // dotStar data - D9 = PA19 // PWM available - D10 = PA20 // can be used for PWM or UART1 TX - D11 = PA21 // can be used for PWM or UART1 RX - D12 = PA23 // PWM available - D13 = PA22 // PWM available -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PA05 // ADC/AIN[2] - A2 = PB08 // ADC/AIN[3] - A3 = PB09 // ADC/AIN[4] - A4 = PA04 // ADC/AIN[5] - A5 = PA06 // ADC/AIN[10] -) - -const ( - LED = D13 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN = D1 - UART_RX_PIN = D0 -) - -const ( - UART2_TX_PIN = A4 - UART2_RX_PIN = D2 -) - -var ( - UART1 = &sercomUSART3 - UART2 = &sercomUSART0 - - DefaultUART = UART1 -) - -// I2C pins -const ( - SDA_PIN = PA12 // SDA: SERCOM2/PAD[0] - SCL_PIN = PA13 // SCL: SERCOM2/PAD[1] -) - -// I2C on the ItsyBitsy M4. -var ( - I2C0 = sercomI2CM2 -) - -// SPI pins -const ( - SPI0_SCK_PIN = PA01 // SCK: SERCOM1/PAD[1] - SPI0_SDO_PIN = PA00 // SDO: SERCOM1/PAD[0] - SPI0_SDI_PIN = PB23 // SDI: SERCOM1/PAD[3] -) - -// SPI on the ItsyBitsy M4. -var SPI0 = sercomSPIM1 - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit ItsyBitsy M4" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x802B -) diff --git a/emb/machine/board_itsybitsy-nrf52840.go b/emb/machine/board_itsybitsy-nrf52840.go deleted file mode 100644 index 0e5818f..0000000 --- a/emb/machine/board_itsybitsy-nrf52840.go +++ /dev/null @@ -1,99 +0,0 @@ -//go:build itsybitsy_nrf52840 - -package machine - -const HasLowFrequencyCrystal = true - -// GPIO Pins -const ( - D0 = P0_25 // UART TX - D1 = P0_24 // UART RX - D2 = P1_02 - D3 = P0_06 // LED1 - D4 = P0_29 // Button - D5 = P0_27 - D6 = P1_09 // DotStar Clock - D7 = P1_08 - D8 = P0_08 // DotStar Data - D9 = P0_07 - D10 = P0_05 - D11 = P0_26 - D12 = P0_11 - D13 = P0_12 - D14 = P0_04 // A0 - D15 = P0_30 // A1 - D16 = P0_28 // A2 - D17 = P0_31 // A3 - D18 = P0_02 // A4 - D19 = P0_03 // A5 - D20 = P0_05 // A6 - D21 = P0_16 // I2C SDA - D22 = P0_14 // I2C SCL - D23 = P0_20 // SPI SDI - D24 = P0_15 // SPI SDO - D25 = P0_13 // SPI SCK - D26 = P0_19 // QSPI SCK - D27 = P0_23 // QSPI CS - D28 = P0_21 // QSPI Data 0 - D29 = P0_22 // QSPI Data 1 - D30 = P1_00 // QSPI Data 2 - D31 = P0_17 // QSPI Data 3 -) - -// Analog Pins -const ( - A0 = D14 - A1 = D15 - A2 = D16 - A3 = D17 - A4 = D18 - A5 = D19 - A6 = D20 -) - -const ( - LED = D3 - LED1 = LED - BUTTON = D4 - - QSPI_SCK = D26 - QSPI_CS = D27 - QSPI_DATA0 = D28 - QSPI_DATA1 = D29 - QSPI_DATA2 = D30 - QSPI_DATA3 = D31 -) - -// UART0 pins (logical UART1) -const ( - UART_RX_PIN = D0 - UART_TX_PIN = D1 -) - -// I2C pins -const ( - SDA_PIN = D21 // I2C0 external - SCL_PIN = D22 // I2C0 external -) - -// SPI pins -const ( - SPI0_SCK_PIN = D25 - SPI0_SDO_PIN = D24 - SPI0_SDI_PIN = D23 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit ItsyBitsy nRF52840 Express" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8051 -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_k210.go b/emb/machine/board_k210.go deleted file mode 100644 index 862be25..0000000 --- a/emb/machine/board_k210.go +++ /dev/null @@ -1,354 +0,0 @@ -//go:build maixbit - -// Chip datasheet: https://s3.cn-north-1.amazonaws.com.cn/dl.kendryte.com/documents/kendryte_datasheet_20181011163248_en.pdf - -package machine - -// K210 IO pins. -const ( - P00 Pin = 0 - P01 Pin = 1 - P02 Pin = 2 - P03 Pin = 3 - P04 Pin = 4 - P05 Pin = 5 - P06 Pin = 6 - P07 Pin = 7 - P08 Pin = 8 - P09 Pin = 9 - P10 Pin = 10 - P11 Pin = 11 - P12 Pin = 12 - P13 Pin = 13 - P14 Pin = 14 - P15 Pin = 15 - P16 Pin = 16 - P17 Pin = 17 - P18 Pin = 18 - P19 Pin = 19 - P20 Pin = 20 - P21 Pin = 21 - P22 Pin = 22 - P23 Pin = 23 - P24 Pin = 24 - P25 Pin = 25 - P26 Pin = 26 - P27 Pin = 27 - P28 Pin = 28 - P29 Pin = 29 - P30 Pin = 30 - P31 Pin = 31 - P32 Pin = 32 - P33 Pin = 33 - P34 Pin = 34 - P35 Pin = 35 - P36 Pin = 36 - P37 Pin = 37 - P38 Pin = 38 - P39 Pin = 39 - P40 Pin = 40 - P41 Pin = 41 - P42 Pin = 42 - P43 Pin = 43 - P44 Pin = 44 - P45 Pin = 45 - P46 Pin = 46 - P47 Pin = 47 -) - -type FPIOAFunction uint8 - -// Every pin on the Kendryte K210 is assigned to an FPIOA function. -// Each pin can be configured with every function below. -const ( - FUNC_JTAG_TCLK FPIOAFunction = 0 // JTAG Test Clock - FUNC_JTAG_TDI FPIOAFunction = 1 // JTAG Test Data In - FUNC_JTAG_TMS FPIOAFunction = 2 // JTAG Test Mode Select - FUNC_JTAG_TDO FPIOAFunction = 3 // JTAG Test Data Out - FUNC_SPI0_D0 FPIOAFunction = 4 // SPI0 Data 0 - FUNC_SPI0_D1 FPIOAFunction = 5 // SPI0 Data 1 - FUNC_SPI0_D2 FPIOAFunction = 6 // SPI0 Data 2 - FUNC_SPI0_D3 FPIOAFunction = 7 // SPI0 Data 3 - FUNC_SPI0_D4 FPIOAFunction = 8 // SPI0 Data 4 - FUNC_SPI0_D5 FPIOAFunction = 9 // SPI0 Data 5 - FUNC_SPI0_D6 FPIOAFunction = 10 // SPI0 Data 6 - FUNC_SPI0_D7 FPIOAFunction = 11 // SPI0 Data 7 - FUNC_SPI0_SS0 FPIOAFunction = 12 // SPI0 Chip Select 0 - FUNC_SPI0_SS1 FPIOAFunction = 13 // SPI0 Chip Select 1 - FUNC_SPI0_SS2 FPIOAFunction = 14 // SPI0 Chip Select 2 - FUNC_SPI0_SS3 FPIOAFunction = 15 // SPI0 Chip Select 3 - FUNC_SPI0_ARB FPIOAFunction = 16 // SPI0 Arbitration - FUNC_SPI0_SCLK FPIOAFunction = 17 // SPI0 Serial Clock - FUNC_UARTHS_RX FPIOAFunction = 18 // UART High speed Receiver - FUNC_UARTHS_TX FPIOAFunction = 19 // UART High speed Transmitter - FUNC_RESV6 FPIOAFunction = 20 // Reserved function - FUNC_RESV7 FPIOAFunction = 21 // Reserved function - FUNC_CLK_SPI1 FPIOAFunction = 22 // Clock SPI1 - FUNC_CLK_I2C1 FPIOAFunction = 23 // Clock I2C1 - FUNC_GPIOHS0 FPIOAFunction = 24 // GPIO High speed 0 - FUNC_GPIOHS1 FPIOAFunction = 25 // GPIO High speed 1 - FUNC_GPIOHS2 FPIOAFunction = 26 // GPIO High speed 2 - FUNC_GPIOHS3 FPIOAFunction = 27 // GPIO High speed 3 - FUNC_GPIOHS4 FPIOAFunction = 28 // GPIO High speed 4 - FUNC_GPIOHS5 FPIOAFunction = 29 // GPIO High speed 5 - FUNC_GPIOHS6 FPIOAFunction = 30 // GPIO High speed 6 - FUNC_GPIOHS7 FPIOAFunction = 31 // GPIO High speed 7 - FUNC_GPIOHS8 FPIOAFunction = 32 // GPIO High speed 8 - FUNC_GPIOHS9 FPIOAFunction = 33 // GPIO High speed 9 - FUNC_GPIOHS10 FPIOAFunction = 34 // GPIO High speed 10 - FUNC_GPIOHS11 FPIOAFunction = 35 // GPIO High speed 11 - FUNC_GPIOHS12 FPIOAFunction = 36 // GPIO High speed 12 - FUNC_GPIOHS13 FPIOAFunction = 37 // GPIO High speed 13 - FUNC_GPIOHS14 FPIOAFunction = 38 // GPIO High speed 14 - FUNC_GPIOHS15 FPIOAFunction = 39 // GPIO High speed 15 - FUNC_GPIOHS16 FPIOAFunction = 40 // GPIO High speed 16 - FUNC_GPIOHS17 FPIOAFunction = 41 // GPIO High speed 17 - FUNC_GPIOHS18 FPIOAFunction = 42 // GPIO High speed 18 - FUNC_GPIOHS19 FPIOAFunction = 43 // GPIO High speed 19 - FUNC_GPIOHS20 FPIOAFunction = 44 // GPIO High speed 20 - FUNC_GPIOHS21 FPIOAFunction = 45 // GPIO High speed 21 - FUNC_GPIOHS22 FPIOAFunction = 46 // GPIO High speed 22 - FUNC_GPIOHS23 FPIOAFunction = 47 // GPIO High speed 23 - FUNC_GPIOHS24 FPIOAFunction = 48 // GPIO High speed 24 - FUNC_GPIOHS25 FPIOAFunction = 49 // GPIO High speed 25 - FUNC_GPIOHS26 FPIOAFunction = 50 // GPIO High speed 26 - FUNC_GPIOHS27 FPIOAFunction = 51 // GPIO High speed 27 - FUNC_GPIOHS28 FPIOAFunction = 52 // GPIO High speed 28 - FUNC_GPIOHS29 FPIOAFunction = 53 // GPIO High speed 29 - FUNC_GPIOHS30 FPIOAFunction = 54 // GPIO High speed 30 - FUNC_GPIOHS31 FPIOAFunction = 55 // GPIO High speed 31 - FUNC_GPIO0 FPIOAFunction = 56 // GPIO pin 0 - FUNC_GPIO1 FPIOAFunction = 57 // GPIO pin 1 - FUNC_GPIO2 FPIOAFunction = 58 // GPIO pin 2 - FUNC_GPIO3 FPIOAFunction = 59 // GPIO pin 3 - FUNC_GPIO4 FPIOAFunction = 60 // GPIO pin 4 - FUNC_GPIO5 FPIOAFunction = 61 // GPIO pin 5 - FUNC_GPIO6 FPIOAFunction = 62 // GPIO pin 6 - FUNC_GPIO7 FPIOAFunction = 63 // GPIO pin 7 - FUNC_UART1_RX FPIOAFunction = 64 // UART1 Receiver - FUNC_UART1_TX FPIOAFunction = 65 // UART1 Transmitter - FUNC_UART2_RX FPIOAFunction = 66 // UART2 Receiver - FUNC_UART2_TX FPIOAFunction = 67 // UART2 Transmitter - FUNC_UART3_RX FPIOAFunction = 68 // UART3 Receiver - FUNC_UART3_TX FPIOAFunction = 69 // UART3 Transmitter - FUNC_SPI1_D0 FPIOAFunction = 70 // SPI1 Data 0 - FUNC_SPI1_D1 FPIOAFunction = 71 // SPI1 Data 1 - FUNC_SPI1_D2 FPIOAFunction = 72 // SPI1 Data 2 - FUNC_SPI1_D3 FPIOAFunction = 73 // SPI1 Data 3 - FUNC_SPI1_D4 FPIOAFunction = 74 // SPI1 Data 4 - FUNC_SPI1_D5 FPIOAFunction = 75 // SPI1 Data 5 - FUNC_SPI1_D6 FPIOAFunction = 76 // SPI1 Data 6 - FUNC_SPI1_D7 FPIOAFunction = 77 // SPI1 Data 7 - FUNC_SPI1_SS0 FPIOAFunction = 78 // SPI1 Chip Select 0 - FUNC_SPI1_SS1 FPIOAFunction = 79 // SPI1 Chip Select 1 - FUNC_SPI1_SS2 FPIOAFunction = 80 // SPI1 Chip Select 2 - FUNC_SPI1_SS3 FPIOAFunction = 81 // SPI1 Chip Select 3 - FUNC_SPI1_ARB FPIOAFunction = 82 // SPI1 Arbitration - FUNC_SPI1_SCLK FPIOAFunction = 83 // SPI1 Serial Clock - FUNC_SPI_PERIPHERAL_D0 FPIOAFunction = 84 // SPI Peripheral Data 0 - FUNC_SPI_PERIPHERAL_SS FPIOAFunction = 85 // SPI Peripheral Select - FUNC_SPI_PERIPHERAL_SCLK FPIOAFunction = 86 // SPI Peripheral Serial Clock - FUNC_I2S0_MCLK FPIOAFunction = 87 // I2S0 Main Clock - FUNC_I2S0_SCLK FPIOAFunction = 88 // I2S0 Serial Clock(BCLK) - FUNC_I2S0_WS FPIOAFunction = 89 // I2S0 Word Select(LRCLK) - FUNC_I2S0_IN_D0 FPIOAFunction = 90 // I2S0 Serial Data Input 0 - FUNC_I2S0_IN_D1 FPIOAFunction = 91 // I2S0 Serial Data Input 1 - FUNC_I2S0_IN_D2 FPIOAFunction = 92 // I2S0 Serial Data Input 2 - FUNC_I2S0_IN_D3 FPIOAFunction = 93 // I2S0 Serial Data Input 3 - FUNC_I2S0_OUT_D0 FPIOAFunction = 94 // I2S0 Serial Data Output 0 - FUNC_I2S0_OUT_D1 FPIOAFunction = 95 // I2S0 Serial Data Output 1 - FUNC_I2S0_OUT_D2 FPIOAFunction = 96 // I2S0 Serial Data Output 2 - FUNC_I2S0_OUT_D3 FPIOAFunction = 97 // I2S0 Serial Data Output 3 - FUNC_I2S1_MCLK FPIOAFunction = 98 // I2S1 Main Clock - FUNC_I2S1_SCLK FPIOAFunction = 99 // I2S1 Serial Clock(BCLK) - FUNC_I2S1_WS FPIOAFunction = 100 // I2S1 Word Select(LRCLK) - FUNC_I2S1_IN_D0 FPIOAFunction = 101 // I2S1 Serial Data Input 0 - FUNC_I2S1_IN_D1 FPIOAFunction = 102 // I2S1 Serial Data Input 1 - FUNC_I2S1_IN_D2 FPIOAFunction = 103 // I2S1 Serial Data Input 2 - FUNC_I2S1_IN_D3 FPIOAFunction = 104 // I2S1 Serial Data Input 3 - FUNC_I2S1_OUT_D0 FPIOAFunction = 105 // I2S1 Serial Data Output 0 - FUNC_I2S1_OUT_D1 FPIOAFunction = 106 // I2S1 Serial Data Output 1 - FUNC_I2S1_OUT_D2 FPIOAFunction = 107 // I2S1 Serial Data Output 2 - FUNC_I2S1_OUT_D3 FPIOAFunction = 108 // I2S1 Serial Data Output 3 - FUNC_I2S2_MCLK FPIOAFunction = 109 // I2S2 Main Clock - FUNC_I2S2_SCLK FPIOAFunction = 110 // I2S2 Serial Clock(BCLK) - FUNC_I2S2_WS FPIOAFunction = 111 // I2S2 Word Select(LRCLK) - FUNC_I2S2_IN_D0 FPIOAFunction = 112 // I2S2 Serial Data Input 0 - FUNC_I2S2_IN_D1 FPIOAFunction = 113 // I2S2 Serial Data Input 1 - FUNC_I2S2_IN_D2 FPIOAFunction = 114 // I2S2 Serial Data Input 2 - FUNC_I2S2_IN_D3 FPIOAFunction = 115 // I2S2 Serial Data Input 3 - FUNC_I2S2_OUT_D0 FPIOAFunction = 116 // I2S2 Serial Data Output 0 - FUNC_I2S2_OUT_D1 FPIOAFunction = 117 // I2S2 Serial Data Output 1 - FUNC_I2S2_OUT_D2 FPIOAFunction = 118 // I2S2 Serial Data Output 2 - FUNC_I2S2_OUT_D3 FPIOAFunction = 119 // I2S2 Serial Data Output 3 - FUNC_RESV0 FPIOAFunction = 120 // Reserved function - FUNC_RESV1 FPIOAFunction = 121 // Reserved function - FUNC_RESV2 FPIOAFunction = 122 // Reserved function - FUNC_RESV3 FPIOAFunction = 123 // Reserved function - FUNC_RESV4 FPIOAFunction = 124 // Reserved function - FUNC_RESV5 FPIOAFunction = 125 // Reserved function - FUNC_I2C0_SCLK FPIOAFunction = 126 // I2C0 Serial Clock - FUNC_I2C0_SDA FPIOAFunction = 127 // I2C0 Serial Data - FUNC_I2C1_SCLK FPIOAFunction = 128 // I2C1 Serial Clock - FUNC_I2C1_SDA FPIOAFunction = 129 // I2C1 Serial Data - FUNC_I2C2_SCLK FPIOAFunction = 130 // I2C2 Serial Clock - FUNC_I2C2_SDA FPIOAFunction = 131 // I2C2 Serial Data - FUNC_CMOS_XCLK FPIOAFunction = 132 // DVP System Clock - FUNC_CMOS_RST FPIOAFunction = 133 // DVP System Reset - FUNC_CMOS_PWDN FPIOAFunction = 134 // DVP Power Down Mode - FUNC_CMOS_VSYNC FPIOAFunction = 135 // DVP Vertical Sync - FUNC_CMOS_HREF FPIOAFunction = 136 // DVP Horizontal Reference output - FUNC_CMOS_PCLK FPIOAFunction = 137 // Pixel Clock - FUNC_CMOS_D0 FPIOAFunction = 138 // Data Bit 0 - FUNC_CMOS_D1 FPIOAFunction = 139 // Data Bit 1 - FUNC_CMOS_D2 FPIOAFunction = 140 // Data Bit 2 - FUNC_CMOS_D3 FPIOAFunction = 141 // Data Bit 3 - FUNC_CMOS_D4 FPIOAFunction = 142 // Data Bit 4 - FUNC_CMOS_D5 FPIOAFunction = 143 // Data Bit 5 - FUNC_CMOS_D6 FPIOAFunction = 144 // Data Bit 6 - FUNC_CMOS_D7 FPIOAFunction = 145 // Data Bit 7 - FUNC_SCCB_SCLK FPIOAFunction = 146 // SCCB Serial Clock - FUNC_SCCB_SDA FPIOAFunction = 147 // SCCB Serial Data - FUNC_UART1_CTS FPIOAFunction = 148 // UART1 Clear To Send - FUNC_UART1_DSR FPIOAFunction = 149 // UART1 Data Set Ready - FUNC_UART1_DCD FPIOAFunction = 150 // UART1 Data Carrier Detect - FUNC_UART1_RI FPIOAFunction = 151 // UART1 Ring Indicator - FUNC_UART1_SIR_IN FPIOAFunction = 152 // UART1 Serial Infrared Input - FUNC_UART1_DTR FPIOAFunction = 153 // UART1 Data Terminal Ready - FUNC_UART1_RTS FPIOAFunction = 154 // UART1 Request To Send - FUNC_UART1_OUT2 FPIOAFunction = 155 // UART1 User-designated Output 2 - FUNC_UART1_OUT1 FPIOAFunction = 156 // UART1 User-designated Output 1 - FUNC_UART1_SIR_OUT FPIOAFunction = 157 // UART1 Serial Infrared Output - FUNC_UART1_BAUD FPIOAFunction = 158 // UART1 Transmit Clock Output - FUNC_UART1_RE FPIOAFunction = 159 // UART1 Receiver Output Enable - FUNC_UART1_DE FPIOAFunction = 160 // UART1 Driver Output Enable - FUNC_UART1_RS485_EN FPIOAFunction = 161 // UART1 RS485 Enable - FUNC_UART2_CTS FPIOAFunction = 162 // UART2 Clear To Send - FUNC_UART2_DSR FPIOAFunction = 163 // UART2 Data Set Ready - FUNC_UART2_DCD FPIOAFunction = 164 // UART2 Data Carrier Detect - FUNC_UART2_RI FPIOAFunction = 165 // UART2 Ring Indicator - FUNC_UART2_SIR_IN FPIOAFunction = 166 // UART2 Serial Infrared Input - FUNC_UART2_DTR FPIOAFunction = 167 // UART2 Data Terminal Ready - FUNC_UART2_RTS FPIOAFunction = 168 // UART2 Request To Send - FUNC_UART2_OUT2 FPIOAFunction = 169 // UART2 User-designated Output 2 - FUNC_UART2_OUT1 FPIOAFunction = 170 // UART2 User-designated Output 1 - FUNC_UART2_SIR_OUT FPIOAFunction = 171 // UART2 Serial Infrared Output - FUNC_UART2_BAUD FPIOAFunction = 172 // UART2 Transmit Clock Output - FUNC_UART2_RE FPIOAFunction = 173 // UART2 Receiver Output Enable - FUNC_UART2_DE FPIOAFunction = 174 // UART2 Driver Output Enable - FUNC_UART2_RS485_EN FPIOAFunction = 175 // UART2 RS485 Enable - FUNC_UART3_CTS FPIOAFunction = 176 // UART3 Clear To Send - FUNC_UART3_DSR FPIOAFunction = 177 // UART3 Data Set Ready - FUNC_UART3_DCD FPIOAFunction = 178 // UART3 Data Carrier Detect - FUNC_UART3_RI FPIOAFunction = 179 // UART3 Ring Indicator - FUNC_UART3_SIR_IN FPIOAFunction = 180 // UART3 Serial Infrared Input - FUNC_UART3_DTR FPIOAFunction = 181 // UART3 Data Terminal Ready - FUNC_UART3_RTS FPIOAFunction = 182 // UART3 Request To Send - FUNC_UART3_OUT2 FPIOAFunction = 183 // UART3 User-designated Output 2 - FUNC_UART3_OUT1 FPIOAFunction = 184 // UART3 User-designated Output 1 - FUNC_UART3_SIR_OUT FPIOAFunction = 185 // UART3 Serial Infrared Output - FUNC_UART3_BAUD FPIOAFunction = 186 // UART3 Transmit Clock Output - FUNC_UART3_RE FPIOAFunction = 187 // UART3 Receiver Output Enable - FUNC_UART3_DE FPIOAFunction = 188 // UART3 Driver Output Enable - FUNC_UART3_RS485_EN FPIOAFunction = 189 // UART3 RS485 Enable - FUNC_TIMER0_TOGGLE1 FPIOAFunction = 190 // TIMER0 Toggle Output 1 - FUNC_TIMER0_TOGGLE2 FPIOAFunction = 191 // TIMER0 Toggle Output 2 - FUNC_TIMER0_TOGGLE3 FPIOAFunction = 192 // TIMER0 Toggle Output 3 - FUNC_TIMER0_TOGGLE4 FPIOAFunction = 193 // TIMER0 Toggle Output 4 - FUNC_TIMER1_TOGGLE1 FPIOAFunction = 194 // TIMER1 Toggle Output 1 - FUNC_TIMER1_TOGGLE2 FPIOAFunction = 195 // TIMER1 Toggle Output 2 - FUNC_TIMER1_TOGGLE3 FPIOAFunction = 196 // TIMER1 Toggle Output 3 - FUNC_TIMER1_TOGGLE4 FPIOAFunction = 197 // TIMER1 Toggle Output 4 - FUNC_TIMER2_TOGGLE1 FPIOAFunction = 198 // TIMER2 Toggle Output 1 - FUNC_TIMER2_TOGGLE2 FPIOAFunction = 199 // TIMER2 Toggle Output 2 - FUNC_TIMER2_TOGGLE3 FPIOAFunction = 200 // TIMER2 Toggle Output 3 - FUNC_TIMER2_TOGGLE4 FPIOAFunction = 201 // TIMER2 Toggle Output 4 - FUNC_CLK_SPI2 FPIOAFunction = 202 // Clock SPI2 - FUNC_CLK_I2C2 FPIOAFunction = 203 // Clock I2C2 - FUNC_INTERNAL0 FPIOAFunction = 204 // Internal function signal 0 - FUNC_INTERNAL1 FPIOAFunction = 205 // Internal function signal 1 - FUNC_INTERNAL2 FPIOAFunction = 206 // Internal function signal 2 - FUNC_INTERNAL3 FPIOAFunction = 207 // Internal function signal 3 - FUNC_INTERNAL4 FPIOAFunction = 208 // Internal function signal 4 - FUNC_INTERNAL5 FPIOAFunction = 209 // Internal function signal 5 - FUNC_INTERNAL6 FPIOAFunction = 210 // Internal function signal 6 - FUNC_INTERNAL7 FPIOAFunction = 211 // Internal function signal 7 - FUNC_INTERNAL8 FPIOAFunction = 212 // Internal function signal 8 - FUNC_INTERNAL9 FPIOAFunction = 213 // Internal function signal 9 - FUNC_INTERNAL10 FPIOAFunction = 214 // Internal function signal 10 - FUNC_INTERNAL11 FPIOAFunction = 215 // Internal function signal 11 - FUNC_INTERNAL12 FPIOAFunction = 216 // Internal function signal 12 - FUNC_INTERNAL13 FPIOAFunction = 217 // Internal function signal 13 - FUNC_INTERNAL14 FPIOAFunction = 218 // Internal function signal 14 - FUNC_INTERNAL15 FPIOAFunction = 219 // Internal function signal 15 - FUNC_INTERNAL16 FPIOAFunction = 220 // Internal function signal 16 - FUNC_INTERNAL17 FPIOAFunction = 221 // Internal function signal 17 - FUNC_CONSTANT FPIOAFunction = 222 // Constant function - FUNC_INTERNAL18 FPIOAFunction = 223 // Internal function signal 18 - FUNC_DEBUG0 FPIOAFunction = 224 // Debug function 0 - FUNC_DEBUG1 FPIOAFunction = 225 // Debug function 1 - FUNC_DEBUG2 FPIOAFunction = 226 // Debug function 2 - FUNC_DEBUG3 FPIOAFunction = 227 // Debug function 3 - FUNC_DEBUG4 FPIOAFunction = 228 // Debug function 4 - FUNC_DEBUG5 FPIOAFunction = 229 // Debug function 5 - FUNC_DEBUG6 FPIOAFunction = 230 // Debug function 6 - FUNC_DEBUG7 FPIOAFunction = 231 // Debug function 7 - FUNC_DEBUG8 FPIOAFunction = 232 // Debug function 8 - FUNC_DEBUG9 FPIOAFunction = 233 // Debug function 9 - FUNC_DEBUG10 FPIOAFunction = 234 // Debug function 10 - FUNC_DEBUG11 FPIOAFunction = 235 // Debug function 11 - FUNC_DEBUG12 FPIOAFunction = 236 // Debug function 12 - FUNC_DEBUG13 FPIOAFunction = 237 // Debug function 13 - FUNC_DEBUG14 FPIOAFunction = 238 // Debug function 14 - FUNC_DEBUG15 FPIOAFunction = 239 // Debug function 15 - FUNC_DEBUG16 FPIOAFunction = 240 // Debug function 16 - FUNC_DEBUG17 FPIOAFunction = 241 // Debug function 17 - FUNC_DEBUG18 FPIOAFunction = 242 // Debug function 18 - FUNC_DEBUG19 FPIOAFunction = 243 // Debug function 19 - FUNC_DEBUG20 FPIOAFunction = 244 // Debug function 20 - FUNC_DEBUG21 FPIOAFunction = 245 // Debug function 21 - FUNC_DEBUG22 FPIOAFunction = 246 // Debug function 22 - FUNC_DEBUG23 FPIOAFunction = 247 // Debug function 23 - FUNC_DEBUG24 FPIOAFunction = 248 // Debug function 24 - FUNC_DEBUG25 FPIOAFunction = 249 // Debug function 25 - FUNC_DEBUG26 FPIOAFunction = 250 // Debug function 26 - FUNC_DEBUG27 FPIOAFunction = 251 // Debug function 27 - FUNC_DEBUG28 FPIOAFunction = 252 // Debug function 28 - FUNC_DEBUG29 FPIOAFunction = 253 // Debug function 29 - FUNC_DEBUG30 FPIOAFunction = 254 // Debug function 30 - FUNC_DEBUG31 FPIOAFunction = 255 // Debug function 31 -) - -// These are the default FPIOA values for each function. -// (source: https://github.com/kendryte/kendryte-standalone-sdk/blob/develop/lib/drivers/fpioa.c#L69) -var fpioaFuncDefaults [256]uint32 = [256]uint32{ - 0x00900000, 0x00900001, 0x00900002, 0x00001f03, 0x00b03f04, 0x00b03f05, 0x00b03f06, 0x00b03f07, 0x00b03f08, - 0x00b03f09, 0x00b03f0a, 0x00b03f0b, 0x00001f0c, 0x00001f0d, 0x00001f0e, 0x00001f0f, 0x03900010, 0x00001f11, - 0x00900012, 0x00001f13, 0x00900014, 0x00900015, 0x00001f16, 0x00001f17, 0x00901f18, 0x00901f19, 0x00901f1a, - 0x00901f1b, 0x00901f1c, 0x00901f1d, 0x00901f1e, 0x00901f1f, 0x00901f20, 0x00901f21, 0x00901f22, 0x00901f23, - 0x00901f24, 0x00901f25, 0x00901f26, 0x00901f27, 0x00901f28, 0x00901f29, 0x00901f2a, 0x00901f2b, 0x00901f2c, - 0x00901f2d, 0x00901f2e, 0x00901f2f, 0x00901f30, 0x00901f31, 0x00901f32, 0x00901f33, 0x00901f34, 0x00901f35, - 0x00901f36, 0x00901f37, 0x00901f38, 0x00901f39, 0x00901f3a, 0x00901f3b, 0x00901f3c, 0x00901f3d, 0x00901f3e, - 0x00901f3f, 0x00900040, 0x00001f41, 0x00900042, 0x00001f43, 0x00900044, 0x00001f45, 0x00b03f46, 0x00b03f47, - 0x00b03f48, 0x00b03f49, 0x00b03f4a, 0x00b03f4b, 0x00b03f4c, 0x00b03f4d, 0x00001f4e, 0x00001f4f, 0x00001f50, - 0x00001f51, 0x03900052, 0x00001f53, 0x00b03f54, 0x00900055, 0x00900056, 0x00001f57, 0x00001f58, 0x00001f59, - 0x0090005a, 0x0090005b, 0x0090005c, 0x0090005d, 0x00001f5e, 0x00001f5f, 0x00001f60, 0x00001f61, 0x00001f62, - 0x00001f63, 0x00001f64, 0x00900065, 0x00900066, 0x00900067, 0x00900068, 0x00001f69, 0x00001f6a, 0x00001f6b, - 0x00001f6c, 0x00001f6d, 0x00001f6e, 0x00001f6f, 0x00900070, 0x00900071, 0x00900072, 0x00900073, 0x00001f74, - 0x00001f75, 0x00001f76, 0x00001f77, 0x00000078, 0x00000079, 0x0000007a, 0x0000007b, 0x0000007c, 0x0000007d, - 0x0099107e, 0x0099107f, 0x00991080, 0x00991081, 0x00991082, 0x00991083, 0x00001f84, 0x00001f85, 0x00001f86, - 0x00900087, 0x00900088, 0x00900089, 0x0090008a, 0x0090008b, 0x0090008c, 0x0090008d, 0x0090008e, 0x0090008f, - 0x00900090, 0x00900091, 0x00993092, 0x00993093, 0x00900094, 0x00900095, 0x00900096, 0x00900097, 0x00900098, - 0x00001f99, 0x00001f9a, 0x00001f9b, 0x00001f9c, 0x00001f9d, 0x00001f9e, 0x00001f9f, 0x00001fa0, 0x00001fa1, - 0x009000a2, 0x009000a3, 0x009000a4, 0x009000a5, 0x009000a6, 0x00001fa7, 0x00001fa8, 0x00001fa9, 0x00001faa, - 0x00001fab, 0x00001fac, 0x00001fad, 0x00001fae, 0x00001faf, 0x009000b0, 0x009000b1, 0x009000b2, 0x009000b3, - 0x009000b4, 0x00001fb5, 0x00001fb6, 0x00001fb7, 0x00001fb8, 0x00001fb9, 0x00001fba, 0x00001fbb, 0x00001fbc, - 0x00001fbd, 0x00001fbe, 0x00001fbf, 0x00001fc0, 0x00001fc1, 0x00001fc2, 0x00001fc3, 0x00001fc4, 0x00001fc5, - 0x00001fc6, 0x00001fc7, 0x00001fc8, 0x00001fc9, 0x00001fca, 0x00001fcb, 0x00001fcc, 0x00001fcd, 0x00001fce, - 0x00001fcf, 0x00001fd0, 0x00001fd1, 0x00001fd2, 0x00001fd3, 0x00001fd4, 0x009000d5, 0x009000d6, 0x009000d7, - 0x009000d8, 0x009100d9, 0x00991fda, 0x009000db, 0x009000dc, 0x009000dd, 0x000000de, 0x009000df, 0x00001fe0, - 0x00001fe1, 0x00001fe2, 0x00001fe3, 0x00001fe4, 0x00001fe5, 0x00001fe6, 0x00001fe7, 0x00001fe8, 0x00001fe9, - 0x00001fea, 0x00001feb, 0x00001fec, 0x00001fed, 0x00001fee, 0x00001fef, 0x00001ff0, 0x00001ff1, 0x00001ff2, - 0x00001ff3, 0x00001ff4, 0x00001ff5, 0x00001ff6, 0x00001ff7, 0x00001ff8, 0x00001ff9, 0x00001ffa, 0x00001ffb, - 0x00001ffc, 0x00001ffd, 0x00001ffe, 0x00001fff, -} diff --git a/emb/machine/board_kb2040.go b/emb/machine/board_kb2040.go deleted file mode 100644 index 1a6f353..0000000 --- a/emb/machine/board_kb2040.go +++ /dev/null @@ -1,84 +0,0 @@ -//go:build kb2040 - -package machine - -// Onboard crystal oscillator frequency, in MHz. -const xoscFreq = 12 // MHz - -// GPIO Pins -const ( - D0 = GPIO0 - D1 = GPIO1 - D2 = GPIO2 - D3 = GPIO3 - D4 = GPIO4 - D5 = GPIO5 - D6 = GPIO6 - D7 = GPIO7 - D8 = GPIO8 - D9 = GPIO9 - D10 = GPIO10 -) - -// Analog pins -const ( - A0 = GPIO26 - A1 = GPIO27 - A2 = GPIO28 - A3 = GPIO29 -) - -// Note: there is no user-controllable LED on the KB2040 board -// const LED = notConnected - -// I2C Pins. -const ( - I2C0_SDA_PIN = GPIO12 - I2C0_SCL_PIN = GPIO13 - - I2C1_SDA_PIN = GPIO2 - I2C1_SCL_PIN = GPIO3 - - SDA_PIN = I2C0_SDA_PIN - SCL_PIN = I2C0_SCL_PIN -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO18 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO19 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO20 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO26 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO27 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO28 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO8 - UART1_RX_PIN = GPIO9 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "KB2040" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8106 -) diff --git a/emb/machine/board_lgt92.go b/emb/machine/board_lgt92.go deleted file mode 100644 index 71b0508..0000000 --- a/emb/machine/board_lgt92.go +++ /dev/null @@ -1,97 +0,0 @@ -//go:build lgt92 - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - LED1 = PA12 - LED2 = PA8 - LED3 = PA11 - - LED_RED = LED1 - LED_BLUE = LED2 - LED_GREEN = LED3 - - // Default led - LED = LED1 - - BUTTON = PB14 - - // LG GPS module - GPS_STANDBY_PIN = PB3 - GPS_RESET_PIN = PB4 - GPS_POWER_PIN = PB5 - - MEMS_ACCEL_CS = PE3 - MEMS_ACCEL_INT1 = PE0 - MEMS_ACCEL_INT2 = PE1 - - // SPI - SPI1_SCK_PIN = PA5 - SPI1_SDI_PIN = PA6 - SPI1_SDO_PIN = PA7 - SPI0_SCK_PIN = SPI1_SCK_PIN - SPI0_SDI_PIN = SPI1_SDI_PIN - SPI0_SDO_PIN = SPI1_SDO_PIN - - // LORA RFM95 Radio - RFM95_DIO0_PIN = PC13 - - // TinyGo UART is MCU LPUSART1 - UART_RX_PIN = PA13 - UART_TX_PIN = PA14 - - // TinyGo UART1 is MCU USART1 - UART1_RX_PIN = PB6 - UART1_TX_PIN = PB7 - - // MPU9250 Nine-Axis (Gyro + Accelerometer + Compass) - I2C0_SCL_PIN = PA9 - I2C0_SDA_PIN = PA10 -) - -var DefaultUART = UART0 - -var ( - - // Console UART (LPUSART1) - UART0 = &_UART0 - _UART0 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.LPUART1, - TxAltFuncSelector: 6, - RxAltFuncSelector: 6, - } - - // Gps UART - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART1, - TxAltFuncSelector: 0, - RxAltFuncSelector: 0, - } - - // MPU9250 Nine-Axis (Gyro + Accelerometer + Compass) - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: 6, - } - I2C0 = I2C1 - - // SPI - SPI0 = &SPI{ - Bus: stm32.SPI1, - } - SPI1 = SPI0 -) - -func init() { - // Enable UARTs Interrupts - UART0.Interrupt = interrupt.New(stm32.IRQ_AES_RNG_LPUART1, _UART0.handleInterrupt) - UART1.Interrupt = interrupt.New(stm32.IRQ_USART1, _UART1.handleInterrupt) -} diff --git a/emb/machine/board_lorae5.go b/emb/machine/board_lorae5.go deleted file mode 100644 index 18b5d8e..0000000 --- a/emb/machine/board_lorae5.go +++ /dev/null @@ -1,97 +0,0 @@ -//go:build lorae5 - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - // We assume a LED is connected on PB5 - LED = PB5 // Default LED - - // Set the POWER_EN3V3 pin to high to turn - // on the 3.3V power for all peripherals - POWER_EN3V3 = PA9 - - // Set the POWER_EN5V pin to high to turn - // on the 5V bus power for all peripherals - POWER_EN5V = PB10 -) - -// SubGhz (SPI3) -const ( - SPI0_NSS_PIN = PA4 - SPI0_SCK_PIN = PA5 - SPI0_SDO_PIN = PA6 - SPI0_SDI_PIN = PA7 -) - -// UARTS -const ( - // MCU USART1 - UART1_TX_PIN = PB6 - UART1_RX_PIN = PB7 - - // MCU USART2 - UART2_TX_PIN = PA2 - UART2_RX_PIN = PA3 - - // DEFAULT USART - UART_TX_PIN = UART1_TX_PIN - UART_RX_PIN = UART1_RX_PIN - - // I2C2 pins - I2C2_SCL_PIN = PB15 - I2C2_SDA_PIN = PA15 - I2C2_ALT_FUNC = 4 - - // I2C0 alias for I2C2 - I2C0_SDA_PIN = I2C2_SDA_PIN - I2C0_SCL_PIN = I2C2_SCL_PIN -) - -var ( - // Console UART - UART0 = &_UART0 - _UART0 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART1, - TxAltFuncSelector: AF7_USART1_2, - RxAltFuncSelector: AF7_USART1_2, - } - DefaultUART = UART0 - - // Since we treat UART1 as zero, let's also call it by the real name - UART1 = UART0 - - // UART2 - UART2 = &_UART2 - _UART2 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART2, - TxAltFuncSelector: AF7_USART1_2, - RxAltFuncSelector: AF7_USART1_2, - } - - // I2C Busses - I2C2 = &I2C{ - Bus: stm32.I2C2, - AltFuncSelector: I2C2_ALT_FUNC, - } - - // Set "default" I2C bus to I2C2 - I2C0 = I2C2 - - // SPI - SPI3 = &SPI{ - Bus: stm32.SPI3, - } -) - -func init() { - // Enable UARTs Interrupts - UART0.Interrupt = interrupt.New(stm32.IRQ_USART1, _UART0.handleInterrupt) - UART2.Interrupt = interrupt.New(stm32.IRQ_USART2, _UART2.handleInterrupt) -} diff --git a/emb/machine/board_m5paper.go b/emb/machine/board_m5paper.go deleted file mode 100644 index 7c20f4d..0000000 --- a/emb/machine/board_m5paper.go +++ /dev/null @@ -1,112 +0,0 @@ -//go:build m5paper - -package machine - -const ( - IO0 = GPIO0 - IO1 = GPIO1 - IO2 = GPIO2 - IO3 = GPIO3 - IO4 = GPIO4 - IO5 = GPIO5 - IO6 = GPIO6 - IO7 = GPIO7 - IO8 = GPIO8 - IO9 = GPIO9 - IO10 = GPIO10 - IO11 = GPIO11 - IO12 = GPIO12 - IO13 = GPIO13 - IO14 = GPIO14 - IO15 = GPIO15 - IO16 = GPIO16 - IO17 = GPIO17 - IO18 = GPIO18 - IO19 = GPIO19 - IO21 = GPIO21 - IO22 = GPIO22 - IO23 = GPIO23 - IO25 = GPIO25 - IO26 = GPIO26 - IO27 = GPIO27 - IO32 = GPIO32 - IO33 = GPIO33 - IO34 = GPIO34 - IO35 = GPIO35 - IO36 = GPIO36 - IO37 = GPIO37 - IO38 = GPIO38 - IO39 = GPIO39 -) - -const ( - POWER_PIN = IO2 - EXT_POWER_PIN = IO5 - EPD_POWER_PIN = IO23 - - // Buttons - BUTTON_RIGHT = IO39 - BUTTON_PUSH = IO38 - BUTTON_LEFT = IO37 - BUTTON = BUTTON_PUSH - - // Touch Screen Interrupt - TOUCH_INT = IO36 -) - -// SPI pins -const ( - SPI0_SCK_PIN = IO14 - SPI0_SDO_PIN = IO12 - SPI0_SDI_PIN = IO13 - - // EPD (IT8951) - EPD_SCK_PIN = SPI0_SCK_PIN - EPD_SDO_PIN = SPI0_SDO_PIN - EPD_SDI_PIN = SPI0_SDI_PIN - EPD_CS_PIN = IO15 - EPD_BUSY_PIN = IO27 - - // SD CARD - SDCARD_SCK_PIN = SPI0_SCK_PIN - SDCARD_SDO_PIN = SPI0_SDO_PIN - SDCARD_SDI_PIN = SPI0_SDI_PIN - SDCARD_CS_PIN = IO4 -) - -// I2C pins -const ( - SDA0_PIN = IO21 - SCL0_PIN = IO22 - - SDA_PIN = SDA0_PIN - SCL_PIN = SCL0_PIN - - I2C_TEMP_ADDR = 0x44 // temperature sensor (SHT30) - I2C_CLOCK_ADDR = 0x51 // real time clock (BM8563) - I2C_TOUCH_ADDR = 0x5D // touch screen controller (GT911) -) - -// ADC pins -const ( - ADC1 Pin = IO35 - ADC2 Pin = IO36 - - BATTERY_ADC_PIN = ADC1 -) - -// DAC pins -const ( - DAC1 Pin = IO25 - DAC2 Pin = IO26 -) - -// UART pins -const ( - // UART0 (CP2104) - UART0_TX_PIN = IO1 - UART0_RX_PIN = IO3 - - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) diff --git a/emb/machine/board_m5stack.go b/emb/machine/board_m5stack.go deleted file mode 100644 index 33c890a..0000000 --- a/emb/machine/board_m5stack.go +++ /dev/null @@ -1,124 +0,0 @@ -//go:build m5stack - -package machine - -const ( - // GND | ADC G35 - // GND | ADC G36 - // GND | RST EN - // G23 MOSI | DAC/SPK G25 - // G19 MISO | DAC G26 - // G18 SCK | 3.3V - // G3 RXD1 | TXD1 G1 - // G16 RXD2 | TXD2 G17 - // G21 SDA | DCL G22 - // G2 GPIO | GPIO G5 - // G12 IIS_SK | IIS_WS G13 - // G15 IIS_OUT | IIS_MK G0 - // HPWR | IIS_IN G34 - // HPWR | 5V - // HPWR | BATTERY - - IO0 = GPIO0 - IO1 = GPIO1 - IO2 = GPIO2 - IO3 = GPIO3 - IO4 = GPIO4 - IO5 = GPIO5 - IO6 = GPIO6 - IO7 = GPIO7 - IO8 = GPIO8 - IO9 = GPIO9 - IO10 = GPIO10 - IO11 = GPIO11 - IO12 = GPIO12 - IO13 = GPIO13 - IO14 = GPIO14 - IO15 = GPIO15 - IO16 = GPIO16 - IO17 = GPIO17 - IO18 = GPIO18 - IO19 = GPIO19 - IO21 = GPIO21 - IO22 = GPIO22 - IO23 = GPIO23 - IO25 = GPIO25 - IO26 = GPIO26 - IO27 = GPIO27 - IO32 = GPIO32 - IO33 = GPIO33 - IO34 = GPIO34 - IO35 = GPIO35 - IO36 = GPIO36 - IO37 = GPIO37 - IO38 = GPIO38 - IO39 = GPIO39 -) - -const ( - // Buttons - BUTTON_A = IO39 - BUTTON_B = IO38 - BUTTON_C = IO37 - BUTTON = BUTTON_A - - // Speaker - SPEAKER_PIN = IO25 -) - -// SPI pins -const ( - SPI0_SCK_PIN = IO18 - SPI0_SDO_PIN = IO23 - SPI0_SDI_PIN = IO19 - SPI0_CS0_PIN = IO14 - - // LCD (ILI9342C) - LCD_SCK_PIN = SPI0_SCK_PIN - LCD_SDO_PIN = SPI0_SDO_PIN - LCD_SDI_PIN = SPI0_SDI_PIN // NoPin ? - LCD_SS_PIN = SPI0_CS0_PIN - LCD_DC_PIN = IO27 - LCD_RST_PIN = IO33 - LCD_BL_PIN = IO32 - - // SD CARD - SDCARD_SCK_PIN = SPI0_SCK_PIN - SDCARD_SDO_PIN = SPI0_SDO_PIN - SDCARD_SDI_PIN = SPI0_SDI_PIN - SDCARD_SS_PIN = IO4 -) - -// I2C pins -const ( - SDA0_PIN = IO21 - SCL0_PIN = IO22 - - SDA_PIN = SDA0_PIN - SCL_PIN = SCL0_PIN -) - -// ADC pins -const ( - ADC1 Pin = IO35 - ADC2 Pin = IO36 -) - -// DAC pins -const ( - DAC1 Pin = IO25 - DAC2 Pin = IO26 -) - -// UART pins -const ( - // UART0 (CP2104) - UART0_TX_PIN = IO1 - UART0_RX_PIN = IO3 - - UART1_TX_PIN = IO17 - UART1_RX_PIN = IO16 - - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) diff --git a/emb/machine/board_m5stack_core2.go b/emb/machine/board_m5stack_core2.go deleted file mode 100644 index 773a069..0000000 --- a/emb/machine/board_m5stack_core2.go +++ /dev/null @@ -1,115 +0,0 @@ -//go:build m5stack_core2 - -package machine - -const ( - // GND | ADC G35 - // GND | ADC G36 - // GND | RST EN - // G23 MOSI | DAC G25 - // G38 MISO | DAC G26 - // G18 SCK | 3.3V - // G3 RXD0 | TXD0 G1 - // G13 RXD2 | TXD2 G14 - // G21 intSDA | intSC G22 - // G32 PA_SDA | PA_SCL G33 - // G27 GPIO | GPIO G19 - // G2 I2S_DOUT | I2S_LRCKC G0 - // N/C | PDM_DAT G34 - // N/C | 5V - // N/C | BAT - - IO0 = GPIO0 - IO1 = GPIO1 // U0TXD - IO2 = GPIO2 - IO3 = GPIO3 // U0RXD - IO4 = GPIO4 - IO5 = GPIO5 - IO6 = GPIO6 // SD_CLK - IO7 = GPIO7 // SD_DATA0 - IO8 = GPIO8 // SD_DATA1 - IO9 = GPIO9 // SD_DATA2 - IO10 = GPIO10 // SD_DATA3 - IO11 = GPIO11 // SD_CMD - IO12 = GPIO12 - IO13 = GPIO13 // U0RXD - IO14 = GPIO14 // U1TXD - IO15 = GPIO15 - IO16 = GPIO16 - IO17 = GPIO17 - IO18 = GPIO18 // SPI0_SCK - IO19 = GPIO19 - IO21 = GPIO21 // SDA0 - IO22 = GPIO22 // SCL0 - IO23 = GPIO23 // SPI0_SDO - IO25 = GPIO25 - IO26 = GPIO26 - IO27 = GPIO27 - IO32 = GPIO32 // SDA1 - IO33 = GPIO33 // SCL1 - IO34 = GPIO34 - IO35 = GPIO35 // ADC1 - IO36 = GPIO36 // ADC2 - IO38 = GPIO38 // SPI0_SDI - IO39 = GPIO39 -) - -// SPI pins -const ( - SPI0_SCK_PIN = IO18 - SPI0_SDO_PIN = IO23 - SPI0_SDI_PIN = IO38 - SPI0_CS0_PIN = IO5 - - // LCD (ILI9342C) - LCD_SCK_PIN = SPI0_SCK_PIN - LCD_SDO_PIN = SPI0_SDO_PIN - LCD_SDI_PIN = SPI0_SDI_PIN - LCD_SS_PIN = SPI0_CS0_PIN - LCD_DC_PIN = IO15 - - // SD CARD - SDCARD_SCK_PIN = SPI0_SCK_PIN - SDCARD_SDO_PIN = SPI0_SDO_PIN - SDCARD_SDI_PIN = SPI0_SDI_PIN - SDCARD_SS_PIN = IO4 -) - -// I2C pins -const ( - // Internal I2C (AXP192 / FT6336U / BM8563 / MPU6886) - SDA0_PIN = IO21 - SCL0_PIN = IO22 - - // External I2C (PORT A) - SDA1_PIN = IO32 - SCL1_PIN = IO33 - - SDA_PIN = SDA1_PIN - SCL_PIN = SCL1_PIN -) - -// ADC pins -const ( - ADC1 Pin = IO35 - ADC2 Pin = IO36 -) - -// DAC pins -const ( - DAC1 Pin = IO25 - DAC2 Pin = IO26 -) - -// UART pins -const ( - // UART0 (CP2104) - UART0_TX_PIN = IO1 - UART0_RX_PIN = IO3 - - UART1_TX_PIN = IO14 - UART1_RX_PIN = IO13 - - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) diff --git a/emb/machine/board_m5stamp_c3.go b/emb/machine/board_m5stamp_c3.go deleted file mode 100644 index a77e544..0000000 --- a/emb/machine/board_m5stamp_c3.go +++ /dev/null @@ -1,51 +0,0 @@ -//go:build m5stamp_c3 - -package machine - -const ( - IO0 = GPIO0 - IO1 = GPIO1 - IO2 = GPIO2 - IO3 = GPIO3 - IO4 = GPIO4 - IO5 = GPIO5 - IO6 = GPIO6 - IO7 = GPIO7 - IO8 = GPIO8 - IO9 = GPIO9 - IO10 = GPIO10 - IO11 = GPIO11 - IO12 = GPIO12 - IO13 = GPIO13 - IO14 = GPIO14 - IO15 = GPIO15 - IO16 = GPIO16 - IO17 = GPIO17 - IO18 = GPIO18 - IO19 = GPIO19 - IO20 = GPIO20 - IO21 = GPIO21 - - XTAL_32K_P = IO0 - XTAL_32K_N = IO1 - MTMS = IO4 - MTDI = IO5 - MTCK = IO6 - MTDO = IO7 - VDD_SPI = IO11 - SPIHD = IO12 - SPISP = IO13 - SPICS0 = IO14 - SPICLK = IO15 - SPID = IO16 - SPIQ = IO17 - U0RXD = IO20 - U0TXD = IO21 - - UART_TX_PIN = U0TXD - UART_RX_PIN = U0RXD -) - -const ( - WS2812 = IO2 -) diff --git a/emb/machine/board_m5stick_c.go b/emb/machine/board_m5stick_c.go deleted file mode 100644 index 2eeb522..0000000 --- a/emb/machine/board_m5stick_c.go +++ /dev/null @@ -1,117 +0,0 @@ -//go:build m5stick_c - -// This file contains the pin mapping for the M5STACK M5Stick-C device. -// doc: https://docs.m5stack.com/en/core/m5stickc - -package machine - -const ( - // HAT | HY2.0-4P - // | - // GND | GND - // 5V OUT | VOUT - // G26 | G32 SDA - // G36 | G33 SCL - // G0 | - // BAT | - // 3V3 | - // 5V IN | - - IO0 = GPIO0 // CLK - IO1 = GPIO1 // U0TXD - IO2 = GPIO2 - IO3 = GPIO3 // U0RXD - IO4 = GPIO4 - IO5 = GPIO5 // TFT_CS LCD_SS SPI0_SS - IO6 = GPIO6 - IO7 = GPIO7 - IO8 = GPIO8 - IO9 = GPIO9 // IR - IO10 = GPIO10 // LED - IO11 = GPIO11 - IO12 = GPIO12 - IO13 = GPIO13 // TFT_CLK LCD_SCK SPI0_SCK - IO14 = GPIO14 - IO15 = GPIO15 // TFT_MOSI LCD_MOSI SPI0_MOSI - IO16 = GPIO16 - IO17 = GPIO17 - IO18 = GPIO18 // TFT_RST LCD_RST - IO19 = GPIO19 - IO21 = GPIO21 // SDA0 - IO22 = GPIO22 // SCL0 - IO23 = GPIO23 // TFT_DC LCD_DC - IO25 = GPIO25 // - DAC1 - IO26 = GPIO26 // HAT DAC2 - IO27 = GPIO27 - IO32 = GPIO32 // SDA1 / PIN 32 / RXD2 - IO33 = GPIO33 // SCL1 / PIN 33 / TXD2 - IO34 = GPIO34 // MIC_DATA - IO35 = GPIO35 // IRQ0 ADC1 - IO36 = GPIO36 // HAT ADC2 LCD_MISO SPI0_MISO - IO37 = GPIO37 // BUTTON_A, BUTTON_HOME, BUTTON - IO38 = GPIO38 - IO39 = GPIO39 // BUTTON_B, BUTTON_RST -) - -const ( - // Buttons - BUTTON_A = IO37 - BUTTON_B = IO39 - BUTTON_HOME = BUTTON_A - BUTTON_RST = BUTTON_B - BUTTON = BUTTON_A - - // LED - IR = IO9 - LED = IO10 -) - -// SPI pins -const ( - SPI0_SCK_PIN = IO13 - SPI0_SDO_PIN = IO15 - SPI0_CS0_PIN = IO5 - - // LCD () - LCD_SCK_PIN = SPI0_SCK_PIN - LCD_SDO_PIN = SPI0_SDO_PIN - LCD_SS_PIN = SPI0_CS0_PIN - LCD_DC_PIN = IO23 - LCD_RST_PIN = IO18 -) - -// I2C pins -const ( - // Internal I2C (AXP192 / BM8563 / MPU6886) - SDA0_PIN = IO21 - SCL0_PIN = IO22 - - // External I2C (GROOVE PORT) - SDA1_PIN = IO32 - SCL1_PIN = IO33 - - SDA_PIN = SDA1_PIN - SCL_PIN = SCL1_PIN -) - -// ADC pins -const ( - ADC1 Pin = IO35 - ADC2 Pin = IO36 -) - -// DAC pins -const ( - DAC1 Pin = IO25 - DAC2 Pin = IO26 -) - -// UART pins -const ( - // UART0 (CP2104) - UART0_TX_PIN = IO1 - UART0_RX_PIN = IO3 - - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) diff --git a/emb/machine/board_macropad-rp2040.go b/emb/machine/board_macropad-rp2040.go deleted file mode 100644 index 78bd2b7..0000000 --- a/emb/machine/board_macropad-rp2040.go +++ /dev/null @@ -1,87 +0,0 @@ -//go:build macropad_rp2040 - -package machine - -const ( - NeopixelCount = 12 - - // Onboard crystal oscillator frequency, in MHz. - xoscFreq = 12 // MHz -) - -const ( - SWITCH = GPIO0 - BUTTON = GPIO0 - - KEY1 = GPIO1 - KEY2 = GPIO2 - KEY3 = GPIO3 - KEY4 = GPIO4 - KEY5 = GPIO5 - KEY6 = GPIO6 - KEY7 = GPIO7 - KEY8 = GPIO8 - KEY9 = GPIO9 - KEY10 = GPIO10 - KEY11 = GPIO11 - KEY12 = GPIO12 - - LED = GPIO13 - - SPEAKER_ENABLE = GPIO14 - SPEAKER = GPIO16 - - ROT_A = GPIO18 - ROT_B = GPIO17 - - OLED_CS = GPIO22 - OLED_RST = GPIO23 - OLED_DC = GPIO24 - - NEOPIXEL = GPIO19 - WS2812 = NEOPIXEL -) - -// I2C Default pins on Raspberry Pico. -const ( - I2C0_SDA_PIN = GPIO20 - I2C0_SCL_PIN = GPIO21 - - I2C1_SDA_PIN = NoPin // not pinned out - I2C1_SCL_PIN = NoPin // not pinned out -) - -// SPI default pins -const ( - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO26 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO27 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO28 // Rx - - SPI0_SCK_PIN = NoPin // not pinned out - SPI0_SDO_PIN = NoPin // not pinned out - SPI0_SDI_PIN = NoPin // not pinned out -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "MacroPad RP2040" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8107 -) diff --git a/emb/machine/board_maixbit.go b/emb/machine/board_maixbit.go deleted file mode 100644 index 359a9b8..0000000 --- a/emb/machine/board_maixbit.go +++ /dev/null @@ -1,74 +0,0 @@ -//go:build maixbit - -package machine - -// Pins on the MAix Bit. -const ( - D0 = P00 // JTAG_TCLK - D1 = P01 // JTAG_TDI - D2 = P02 // JTAG_TMS - D3 = P03 // JTAG_TDO - D4 = P04 // UARTHS_RX - D5 = P05 // UARTHS_TX - D6 = P06 // RESV0 - D7 = P07 // RESV0 - D8 = P08 // GPIO1 - D9 = P09 // GPIO2 - D10 = P10 // GPIO3 - D11 = P11 // GPIO4 - D12 = P12 // GPIO5 - D13 = P13 // GPIO6 - D14 = P14 // GPIO7 - D15 = P15 // GPIO8 - D16 = P16 // GPIOHS0 - D17 = P17 // GPIOHS1 - D18 = P18 // GPIOHS2 - D19 = P19 // GPIOHS3 - D20 = P20 // GPIOHS4 - D21 = P21 // GPIOHS5 - D22 = P22 // GPIOHS6 - D23 = P23 // GPIOHS7 - D24 = P24 // GPIOHS8 - D25 = P25 // GPIOHS9 - D26 = P26 // GPIOHS10 / SPI0_SDI - D27 = P27 // GPIOHS11 / SPI0_SCLK - D28 = P28 // GPIOHS12 / SPI0_SDO - D29 = P29 // GPIOHS13 - D30 = P30 // GPIOHS14 - D31 = P31 // GPIOHS15 - D32 = P32 // GPIOHS16 - D33 = P33 // GPIOHS17 - D34 = P34 // GPIOHS18 - D35 = P35 // GPIOHS19 -) - -const ( - LED = LED1 - LED1 = LED_RED - LED2 = LED_GREEN - LED3 = LED_BLUE - LED_RED = D13 - LED_GREEN = D12 - LED_BLUE = D14 -) - -var DefaultUART = UART0 - -// Default pins for UARTHS. -const ( - UART_TX_PIN = D5 - UART_RX_PIN = D4 -) - -// SPI pins. -const ( - SPI0_SCK_PIN = D27 - SPI0_SDO_PIN = D28 - SPI0_SDI_PIN = D26 -) - -// I2C pins. -const ( - I2C0_SDA_PIN = D34 - I2C0_SCL_PIN = D35 -) diff --git a/emb/machine/board_maixbit_baremetal.go b/emb/machine/board_maixbit_baremetal.go deleted file mode 100644 index f5a7e8d..0000000 --- a/emb/machine/board_maixbit_baremetal.go +++ /dev/null @@ -1,15 +0,0 @@ -//go:build k210 && maixbit - -package machine - -import "device/kendryte" - -// SPI on the MAix Bit. -var ( - SPI0 = &SPI{ - Bus: kendryte.SPI0, - } - SPI1 = &SPI{ - Bus: kendryte.SPI1, - } -) diff --git a/emb/machine/board_makerfabs-esp32c3spi35.go b/emb/machine/board_makerfabs-esp32c3spi35.go deleted file mode 100644 index 6e4e6f4..0000000 --- a/emb/machine/board_makerfabs-esp32c3spi35.go +++ /dev/null @@ -1,103 +0,0 @@ -//go:build makerfabs_esp32c3spi35 - -// This file contains the pin mappings for the Makerfabs ESP32C3SPI35 board. -// -// The Makerfabs ESP32C3SPI35 is an LCD Touchscreen development board powered -// by the Espressif ESP32-C3 SoC featuring an open-source RISC-V architecture. -// -// Specifications: -// SoC: ESP32-C3-MINI-1-N4, 4MB Flash, RISCV-32bit, 160MHz, 400KB SRAM -// Wireless: WiFi & Bluetooth 5.0 (BLE) -// LCD: 3.5inch TFT LCD (480x320) -// LCD Driver: ILI9488 SPI -// Touch Panel: Capacitive -// Touch Panel Driver: FT6236 -// MicroSD Card Slot -// Mabee Interface -// Dual USB Type-C (one for USB-to-UART and one for native USB) -// -// Website: https://www.makerfabs.com/ep32-c3-risc-v-spi-tft-touch.html -// Wiki: https://wiki.makerfabs.com/ESP32_C3_SPI_3.5_TFT_with_Touch.html -// GitHub: https://github.com/Makerfabs/Makerfabs-ESP32-C3-SPI-TFT-with-Touch -// Schematic: https://github.com/Makerfabs/Makerfabs-ESP32-C3-SPI-TFT-with-Touch/raw/main/Hardware/ESP32-C3%20TFT%20Touch%20v1.1(3.5''%20ili9488).PDF -// Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf - -package machine - -// Digital pins -const ( - // Pin // Function - // ----- // --------------------- - D0 = GPIO0 // Touchscreen CS - D1 = GPIO1 // MicroSD CS - D2 = GPIO2 // I2C SDA - D3 = GPIO3 // I2C SCL - D4 = GPIO4 // SPI CS - D5 = GPIO5 // SPI SCK - D6 = GPIO6 // SPI SDO - D7 = GPIO7 // SPI SDI - D8 = GPIO8 // Touchscreen Backlight - D9 = GPIO9 // Boot Button - D10 = GPIO10 // TFT D/C - D18 = GPIO18 // USB DM - D19 = GPIO19 // USB DP - D20 = GPIO20 // UART RX - D21 = GPIO21 // UART TX -) - -// Button pin -const ( - BUTTON = BUTTON_BOOT - BUTTON_BOOT = D9 -) - -// TFT pins -const ( - TFT_BL_PIN = D8 - TFT_CS_PIN = SPI_CS_PIN - TFT_DC_PIN = D10 - TFT_SCK_PIN = SPI_SCK_PIN - TFT_SDI_PIN = SPI_SDI_PIN - TFT_SDO_PIN = SPI_SDO_PIN -) - -// Touchscreen pins -const ( - TS_CS_PIN = D0 - TS_SDA_PIN = SDA_PIN - TS_SCL_PIN = SCL_PIN -) - -// MicroSD pins -const ( - SD_CS_PIN = D1 - SD_SCK_PIN = SPI_SCK_PIN - SD_SDI_PIN = SPI_SDI_PIN - SD_SDO_PIN = SPI_SDO_PIN -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = D18 - USBCDC_DP_PIN = D19 -) - -// UART pins -const ( - UART_RX_PIN = D20 - UART_TX_PIN = D21 -) - -// I2C pins -const ( - SDA_PIN = D2 - SCL_PIN = D3 -) - -// SPI pins -const ( - SPI_CS_PIN = D4 - SPI_SCK_PIN = D5 - SPI_SDI_PIN = D7 - SPI_SDO_PIN = D6 -) diff --git a/emb/machine/board_matrixportal-m4.go b/emb/machine/board_matrixportal-m4.go deleted file mode 100644 index b99fcb2..0000000 --- a/emb/machine/board_matrixportal-m4.go +++ /dev/null @@ -1,200 +0,0 @@ -//go:build matrixportal_m4 - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xF01669EF - -// Digital pins -const ( - // Pin // Function SERCOM PWM Interrupt - // ---- // ---------------- ------ --- --------- - D0 = PA01 // UART RX 1[1] PWM EXTI1 - D1 = PA00 // UART TX 1[0] PWM EXTI0 - D2 = PB22 // Button "Up" EXTI6 - D3 = PB23 // Button "Down" EXTI7 - D4 = PA23 // NeoPixel EXTI7 - D5 = PB31 // I2C SDA 5[1] EXTI15 - D6 = PB30 // I2C SCL 5[0] EXTI14 - D7 = PB00 // HUB75 R1 EXTI0 - D8 = PB01 // HUB75 G1 EXTI1 - D9 = PB02 // HUB75 B1 EXTI2 - D10 = PB03 // HUB75 R2 EXTI3 - D11 = PB04 // HUB75 G2 EXTI4 - D12 = PB05 // HUB75 B2 EXTI5 - D13 = PA14 // LED PWM EXTI14 - D14 = PB06 // HUB75 CLK EXTI6 - D15 = PB14 // HUB75 LAT EXTI14 - D16 = PB12 // HUB75 OE EXTI12 - D17 = PB07 // HUB75 ADDR A EXTI7 - D18 = PB08 // HUB75 ADDR B EXTI8 - D19 = PB09 // HUB75 ADDR C EXTI9 - D20 = PB15 // HUB75 ADDR D EXTI15 - D21 = PB13 // HUB75 ADDR E EXTI13 - D22 = PA02 // ADC (A0) EXTI2 - D23 = PA05 // ADC (A1) EXTI5 - D24 = PA04 // ADC (A2) PWM EXTI4 - D25 = PA06 // ADC (A3) PWM EXTI6 - D26 = PA07 // ADC (A4) EXTI7 - D27 = PA12 // ESP32 UART RX 4[1] PWM EXTI12 - D28 = PA13 // ESP32 UART TX 4[0] PWM EXTI13 - D29 = PA20 // ESP32 GPIO0 PWM EXTI4 - D30 = PA21 // ESP32 Reset PWM EXTI5 - D31 = PA22 // ESP32 Busy PWM EXTI6 - D32 = PA18 // ESP32 RTS PWM EXTI2 - D33 = PB17 // ESP32 SPI CS PWM EXTI1 - D34 = PA16 // ESP32 SPI SCK 3[1] PWM EXTI0 - D35 = PA17 // ESP32 SPI SDI 3[0] PWM EXTI1 - D36 = PA19 // ESP32 SPI SDO 1[3] PWM EXTI3 - D37 = NoPin // USB Host enable - D38 = PA24 // USB DM - D39 = PA25 // USB DP - D40 = PA03 // DAC/VREFP - D41 = PB10 // Flash QSPI SCK - D42 = PB11 // Flash QSPI CS - D43 = PA08 // Flash QSPI I00 - D44 = PA09 // Flash QSPI IO1 - D45 = PA10 // Flash QSPI IO2 - D46 = PA11 // Flash QSPI IO3 - D47 = PA27 // LIS3DH IRQ EXTI11 - D48 = PA05 // SPI SCK 0[1] EXTI5 - D49 = PA04 // SPI SDO 0[0] PWM EXTI4 - D50 = PA07 // SPI SDI 0[3] EXTI7 -) - -// Analog pins -const ( - A0 = PA02 // ADC Channel 0 - A1 = PA05 // ADC Channel 5 - A2 = PA04 // ADC Channel 4 - A3 = PA06 // ADC Channel 6 - A4 = PA07 // ADC Channel 7 -) - -// LED pins -const ( - LED = D13 - NEOPIXEL = D4 - WS2812 = D4 -) - -// Button pins -const ( - BUTTON_UP = D2 - BUTTON_DOWN = D3 -) - -// UART pins -const ( - UART1_RX_PIN = D0 // SERCOM1[1] - UART1_TX_PIN = D1 // SERCOM1[0] - - UART2_RX_PIN = D27 // SERCOM4[1] (ESP32 RX) - UART2_TX_PIN = D28 // SERCOM4[0] (ESP32 TX) - - UART_RX_PIN = UART1_RX_PIN - UART_TX_PIN = UART1_TX_PIN -) - -// UART on the MatrixPortal M4 -var ( - UART1 = &sercomUSART1 - UART2 = &sercomUSART4 - - DefaultUART = UART1 -) - -// SPI pins -const ( - SPI0_SCK_PIN = D34 // SERCOM3[1] (ESP32 SCK) - SPI0_SDO_PIN = D36 // SERCOM1[3] (ESP32 SDO) - SPI0_SDI_PIN = D35 // SERCOM3[0] (ESP32 SDI) - - SPI1_SCK_PIN = D48 // SERCOM0[1] - SPI1_SDO_PIN = D49 // SERCOM0[0] - SPI1_SDI_PIN = D50 // SERCOM0[3] - - SPI_SCK_PIN = SPI0_SCK_PIN - SPI_SDO_PIN = SPI0_SDO_PIN - SPI_SDI_PIN = SPI0_SDI_PIN -) - -// I2C pins -const ( - I2C0_SDA_PIN = D5 // SERCOM5[1] - I2C0_SCL_PIN = D6 // SERCOM5[0] - - I2C_SDA_PIN = I2C0_SDA_PIN - I2C_SCL_PIN = I2C0_SCL_PIN - - SDA_PIN = I2C_SDA_PIN // awkward naming required by machine_atsamd51.go - SCL_PIN = I2C_SCL_PIN // -) - -// I2C on the MatrixPortal M4 -var ( - I2C0 = sercomI2CM5 -) - -// ESP32 pins -const ( - NINA_ACK = D31 - NINA_GPIO0 = D29 - NINA_RESETN = D30 - - NINA_RX = UART2_RX_PIN - NINA_TX = UART2_TX_PIN - NINA_RTS = D32 - - NINA_CS = D33 - NINA_SDO = SPI0_SDO_PIN - NINA_SDI = SPI0_SDI_PIN - NINA_SCK = SPI0_SCK_PIN -) - -// SPI on the MatrixPortal M4 -var ( - SPI0 = sercomSPIM3 // BUG: SDO on SERCOM1! - NINA_SPI = SPI0 - - SPI1 = sercomSPIM0 -) - -// HUB75 pins -const ( - HUB75_R1 = D7 - HUB75_G1 = D8 - HUB75_B1 = D9 - HUB75_R2 = D10 - HUB75_G2 = D11 - HUB75_B2 = D12 - - HUB75_CLK = D14 - HUB75_LAT = D15 - HUB75_OE = D16 - HUB75_ADDR_A = D17 - HUB75_ADDR_B = D18 - HUB75_ADDR_C = D19 - HUB75_ADDR_D = D20 - HUB75_ADDR_E = D21 -) - -// USB CDC pins (UART0) -const ( - USBCDC_DM_PIN = D38 - USBCDC_DP_PIN = D39 - - UART0_RX_PIN = USBCDC_DM_PIN - UART0_TX_PIN = USBCDC_DP_PIN -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Matrix Portal M4" - usb_STRING_MANUFACTURER = "Adafruit Industries" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x80C9 -) diff --git a/emb/machine/board_mch2022.go b/emb/machine/board_mch2022.go deleted file mode 100644 index bc6b600..0000000 --- a/emb/machine/board_mch2022.go +++ /dev/null @@ -1,28 +0,0 @@ -//go:build mch2022 - -package machine - -// See: https://badge.team/docs/badges/mch2022/pinout/ - -const ( - UART_TX_PIN Pin = 1 - UART_RX_PIN Pin = 3 - - WS2812 Pin = 5 - - PowerOn Pin = 19 // Set high to enable power to LEDs and SD card - - // I2C pins - SDA_PIN Pin = 22 - SCL_PIN Pin = 21 - - // SPI and related pins (ICE40 and LCD). - LCD_RESET Pin = 25 - LCD_MODE Pin = 26 - LCD_DC Pin = 33 - SPI0_SCK_PIN Pin = 18 - SPI0_SDO_PIN Pin = 23 - SPI0_SDI_PIN Pin = 35 // connected to ICE40 - SPI0_CS_ICE40_PIN Pin = 27 - SPI0_CS_LCD_PIN Pin = 32 -) diff --git a/emb/machine/board_mdbt50qrx.go b/emb/machine/board_mdbt50qrx.go deleted file mode 100644 index b93bee7..0000000 --- a/emb/machine/board_mdbt50qrx.go +++ /dev/null @@ -1,40 +0,0 @@ -//go:build mdbt50qrx - -package machine - -const HasLowFrequencyCrystal = false - -// GPIO Pins -const ( - D0 = P1_13 // LED1 - D1 = P1_11 // LED2 (not populated by default) - D2 = P0_15 // Button -) - -const ( - LED = D0 -) - -// MDBT50Q-RX dongle does not have pins broken out for the peripherals below, -// however the machine_nrf*.go implementations of I2C/SPI/etc expect the pin -// constants to be defined, so we are defining them all as NoPin -const ( - UART_TX_PIN = NoPin - UART_RX_PIN = NoPin - SDA_PIN = NoPin - SCL_PIN = NoPin - SPI0_SCK_PIN = NoPin - SPI0_SDO_PIN = NoPin - SPI0_SDI_PIN = NoPin -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Raytac MDBT50Q - RX" - usb_STRING_MANUFACTURER = "Raytac Corporation" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x810B -) diff --git a/emb/machine/board_metro-m4-airlift.go b/emb/machine/board_metro-m4-airlift.go deleted file mode 100644 index 0fd4291..0000000 --- a/emb/machine/board_metro-m4-airlift.go +++ /dev/null @@ -1,136 +0,0 @@ -//go:build metro_m4_airlift - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PA23 // UART0 RX/PWM available - D1 = PA22 // UART0 TX/PWM available - D2 = PB17 // PWM available - D3 = PB16 // PWM available - D4 = PB13 // PWM available - D5 = PB14 // PWM available - D6 = PB15 // PWM available - D7 = PB12 // PWM available - - D8 = PA21 // PWM available - D9 = PA20 // PWM available - D10 = PA18 // can be used for PWM or UART1 TX - D11 = PA19 // can be used for PWM or UART1 RX - D12 = PA17 // PWM available - D13 = PA16 // PWM available - - D40 = PB22 // built-in neopixel -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PA05 // ADC/AIN[2] - A2 = PB06 // ADC/AIN[3] - A3 = PB00 // ADC/AIN[4] // NOTE: different between "airlift" and non-airlift versions - A4 = PB08 // ADC/AIN[5] - A5 = PB09 // ADC/AIN[10] -) - -const ( - LED = D13 - WS2812 = D40 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -const ( - UART_TX_PIN = D1 - UART_RX_PIN = D0 -) - -const ( - UART2_TX_PIN = PA04 - UART2_RX_PIN = PA07 -) - -var ( - UART1 = &sercomUSART3 - UART2 = &sercomUSART0 - - DefaultUART = UART1 - - UART_NINA = UART2 -) - -// NINA-W102 settings -const ( - NINA_BAUDRATE = 115200 - NINA_RESET_INVERTED = true - NINA_SOFT_FLOWCONTROL = true -) - -const ( - NINA_CS = PA15 - NINA_ACK = PB04 - NINA_GPIO0 = PB01 - NINA_RESETN = PB05 - - // pins used for the ESP32 connection do not allow hardware - // flow control, which is required. have to emulate with software. - NINA_TX = PA04 - NINA_RX = PA07 - NINA_CTS = NINA_ACK - NINA_RTS = NINA_GPIO0 -) - -// I2C pins -const ( - SDA_PIN = PB02 // SDA: SERCOM5/PAD[0] - SCL_PIN = PB03 // SCL: SERCOM5/PAD[1] -) - -// I2C on the Metro M4. -var ( - I2C0 = sercomI2CM5 -) - -// SPI pins -const ( - SPI0_SCK_PIN = PA13 // SCK: SERCOM2/PAD[1] - SPI0_SDO_PIN = PA12 // SDO: SERCOM2/PAD[0] - SPI0_SDI_PIN = PA14 // SDI: SERCOM2/PAD[2] - - NINA_SDO = SPI0_SDO_PIN - NINA_SDI = SPI0_SDI_PIN - NINA_SCK = SPI0_SCK_PIN -) - -const ( - SPI1_SCK_PIN = D12 // SDI: SERCOM1/PAD[1] - SPI1_SDO_PIN = D11 // SDO: SERCOM1/PAD[3] - SPI1_SDI_PIN = D13 // SCK: SERCOM1/PAD[0] -) - -// SPI on the Metro M4. -var ( - SPI0 = sercomSPIM2 - NINA_SPI = SPI0 -) - -// SPI1 on the Metro M4 on pins 11,12,13 -var SPI1 = sercomSPIM1 - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit Metro M4 Airlift Lite" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8037 -) diff --git a/emb/machine/board_microbit-v2.go b/emb/machine/board_microbit-v2.go deleted file mode 100644 index 26cfb51..0000000 --- a/emb/machine/board_microbit-v2.go +++ /dev/null @@ -1,119 +0,0 @@ -//go:build microbit_v2 - -package machine - -// The micro:bit does not have a 32kHz crystal on board. -const HasLowFrequencyCrystal = false - -// Buttons on the micro:bit v2 (A and B) -const ( - BUTTON Pin = BUTTONA - BUTTONA Pin = P5 - BUTTONB Pin = P11 -) - -var DefaultUART = UART0 - -// UART pins -const ( - UART_TX_PIN Pin = P34 - UART_RX_PIN Pin = P33 -) - -// ADC pins -const ( - ADC0 Pin = P0 - ADC1 Pin = P1 - ADC2 Pin = P2 -) - -// I2C0 (internal) pins -const ( - SDA_PIN Pin = SDA0_PIN - SCL_PIN Pin = SCL0_PIN - SDA0_PIN Pin = P30 - SCL0_PIN Pin = P31 -) - -// I2C1 (external) pins -const ( - SDA1_PIN Pin = P20 - SCL1_PIN Pin = P19 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = P13 - SPI0_SDO_PIN Pin = P15 - SPI0_SDI_PIN Pin = P14 -) - -// GPIO/Analog pins -const ( - P0 Pin = 2 - P1 Pin = 3 - P2 Pin = 4 - P3 Pin = 31 - P4 Pin = 28 - P5 Pin = 14 - P6 Pin = 37 - P7 Pin = 11 - P8 Pin = 10 - P9 Pin = 9 - P10 Pin = 30 - P11 Pin = 23 - P12 Pin = 12 - P13 Pin = 17 - P14 Pin = 1 - P15 Pin = 13 - P16 Pin = 34 - P19 Pin = 26 - P20 Pin = 32 - P21 Pin = 21 - P22 Pin = 22 - P23 Pin = 15 - P24 Pin = 24 - P25 Pin = 19 - P26 Pin = 36 - P27 Pin = 0 - P28 Pin = 20 - P29 Pin = 5 - P30 Pin = 16 - P31 Pin = 8 - P32 Pin = 25 - P33 Pin = 40 - P34 Pin = 6 -) - -// LED matrix pins -const ( - LED_COL_1 Pin = P0_28 - LED_COL_2 Pin = P0_11 - LED_COL_3 Pin = P0_31 - LED_COL_4 Pin = P1_05 - LED_COL_5 Pin = P0_30 - LED_ROW_1 Pin = P0_21 - LED_ROW_2 Pin = P0_22 - LED_ROW_3 Pin = P0_15 - LED_ROW_4 Pin = P0_24 - LED_ROW_5 Pin = P0_19 -) - -// Peripherals -const ( - BUZZER = P27 - CAP_TOUCH = P26 - MIC = P29 - MIC_LED = P28 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "BBC micro:bit V2" - usb_STRING_MANUFACTURER = "BBC" -) - -var ( - usb_VID uint16 = 0x0d28 - usb_PID uint16 = 0x0204 -) diff --git a/emb/machine/board_microbit.go b/emb/machine/board_microbit.go deleted file mode 100644 index 719bd1d..0000000 --- a/emb/machine/board_microbit.go +++ /dev/null @@ -1,78 +0,0 @@ -//go:build microbit - -package machine - -// The micro:bit does not have a 32kHz crystal on board. -const HasLowFrequencyCrystal = false - -var DefaultUART = UART0 - -// GPIO/Analog pins -const ( - P0 = P0_03 - P1 = P0_02 - P2 = P0_01 - P3 = P0_04 - P4 = P0_05 - P5 = P0_17 - P6 = P0_12 - P7 = P0_11 - P8 = P0_18 - P9 = P0_10 - P10 = P0_06 - P11 = P0_26 - P12 = P0_20 - P13 = P0_23 - P14 = P0_22 - P15 = P0_21 - P16 = P0_16 -) - -// Buttons on the micro:bit (A and B) -const ( - BUTTONA = P0_17 - BUTTONB = P0_26 - BUTTON = BUTTONA -) - -// UART pins -const ( - UART_TX_PIN = P0_24 - UART_RX_PIN = P0_25 -) - -// ADC pins -const ( - ADC0 = P0_03 // P0 on the board - ADC1 = P0_02 // P1 on the board - ADC2 = P0_01 // P2 on the board -) - -// I2C pins -const ( - SDA_PIN = P0_30 // P20 on the board - SCL_PIN = P0_00 // P19 on the board -) - -// SPI pins -const ( - SPI0_SCK_PIN = P0_23 // P13 on the board - SPI0_SDO_PIN = P0_21 // P15 on the board - SPI0_SDI_PIN = P0_22 // P14 on the board -) - -// LED matrix pins -const ( - LED_COL_1 = P0_04 - LED_COL_2 = P0_05 - LED_COL_3 = P0_06 - LED_COL_4 = P0_07 - LED_COL_5 = P0_08 - LED_COL_6 = P0_09 - LED_COL_7 = P0_10 - LED_COL_8 = P0_11 - LED_COL_9 = P0_12 - LED_ROW_1 = P0_13 - LED_ROW_2 = P0_14 - LED_ROW_3 = P0_15 -) diff --git a/emb/machine/board_mksnanov3.go b/emb/machine/board_mksnanov3.go deleted file mode 100644 index 35fef68..0000000 --- a/emb/machine/board_mksnanov3.go +++ /dev/null @@ -1,142 +0,0 @@ -//go:build mksnanov3 - -// The MKS Robin Nano V3.X board. -// Documented at https://github.com/makerbase-mks/MKS-Robin-Nano-V3.X. - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -// LED is also wired to the SD card card detect (CD) pin. -const LED = PD12 - -// UART pins -const ( - UART_TX_PIN = PB10 - UART_RX_PIN = PB11 -) - -// EXP1 and EXP2 expansion ports for connecting -// the MKS TS35 V2.0 expansion board. -const ( - BEEPER = EXP1_1 - - // LCD pins. - LCD_DC = EXP1_8 - LCD_CS = EXP1_7 - LCD_RS = EXP1_4 - LCD_BACKLIGHT = EXP1_3 - - // Touch pins. Note that some pins are shared with the - // LCD SPI1 interface. - TOUCH_CLK = EXP2_2 - TOUCH_CS = EXP1_5 - TOUCH_DIN = EXP2_6 - TOUCH_DOUT = EXP2_1 - TOUCH_IRQ = EXP1_6 - - BUTTON = BUTTON_JOG - BUTTON_JOG = EXP1_2 - BUTTON_JOG_CCW = EXP2_3 - BUTTON_JOG_CW = EXP2_5 - - EXP1_1 = PC5 - EXP1_2 = PE13 - EXP1_3 = PD13 - EXP1_4 = PC6 - EXP1_5 = PE14 - EXP1_6 = PE15 - EXP1_7 = PD11 - EXP1_8 = PD10 - - EXP2_1 = PA6 - EXP2_2 = PA5 - EXP2_3 = PE8 - EXP2_4 = PE10 - EXP2_5 = PE11 - EXP2_6 = PA7 - EXP2_7 = PE12 -) - -var ( - UART3 = &_UART3 - _UART3 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART3, - TxAltFuncSelector: AF7_USART1_2_3, - RxAltFuncSelector: AF7_USART1_2_3, - } - DefaultUART = UART3 -) - -// set up RX IRQ handler. Follow similar pattern for other UARTx instances -func init() { - UART3.Interrupt = interrupt.New(stm32.IRQ_USART3, _UART3.handleInterrupt) -} - -// SPI pins -const ( - SPI1_SCK_PIN = EXP2_2 - SPI1_SDI_PIN = EXP2_1 - SPI1_SDO_PIN = EXP2_6 - SPI0_SCK_PIN = SPI1_SCK_PIN - SPI0_SDI_PIN = SPI1_SDI_PIN - SPI0_SDO_PIN = SPI1_SDO_PIN -) - -// Since the first interface is named SPI1, both SPI0 and SPI1 refer to SPI1. -var ( - SPI0 = &SPI{ - Bus: stm32.SPI1, - AltFuncSelector: AF5_SPI1_SPI2, - } - SPI1 = SPI0 -) - -const ( - I2C0_SCL_PIN = PB6 - I2C0_SDA_PIN = PB7 -) - -var ( - I2C0 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: AF4_I2C1_2_3, - } -) - -// Motor control pins. -const ( - X_ENABLE = PE4 - X_STEP = PE3 - X_DIR = PE2 - X_DIAG = PA15 - X_UART = PD5 - - Y_ENABLE = PE1 - Y_STEP = PE0 - Y_DIR = PB9 - Y_DIAG = PD2 - Y_UART = PD7 - - Z_ENABLE = PB8 - Z_STEP = PB5 - Z_DIR = PB4 - Z_DIAG = PC8 - Z_UART = PD4 - - E0_ENABLE = PB3 - E0_STEP = PD6 - E0_DIR = PD3 - E0_DIAG = PC4 - E0_UART = PD9 - - E1_ENABLE = PA3 - E1_STEP = PD15 - E1_DIR = PA1 - E1_DIAG = PE7 - E1_UART = PD8 -) diff --git a/emb/machine/board_nano-33-ble.go b/emb/machine/board_nano-33-ble.go deleted file mode 100644 index 758d543..0000000 --- a/emb/machine/board_nano-33-ble.go +++ /dev/null @@ -1,128 +0,0 @@ -//go:build nano_33_ble - -// This contains the pin mappings for the Arduino Nano 33 BLE [Sense] boards. -// - https://store.arduino.cc/arduino-nano-33-ble -// - https://store.arduino.cc/arduino-nano-33-ble-sense -// -// ---------------------------------------------------------------------------- -// Flashing -// -// Special version of bossac is required. -// This executable can be obtained two ways: -// 1. In Arduino IDE, install support for the board ("Arduino Mbed OS Nano Boards") -// Search for "tools/bossac/1.9.1-arduino2/bossac" in Arduino IDEs directory -// 2. Download https://downloads.arduino.cc/packages/package_index.json -// Search for "bossac-1.9.1-arduino2" in that file -// Download tarball for your OS and unpack it -// -// Once you have the executable, make it accessible in your PATH as "bossac_arduino2". -// -// It is possible to replace original bossac with this new one (this only adds support for nrf chip). -// In that case make "bossac_arduino2" symlink on it, for the board target to be able to find it. -// -// ---------------------------------------------------------------------------- -// Bluetooth -// -// SoftDevice (s140v7) must be flashed first to enable use of bluetooth on this board. -// See https://github.com/tinygo-org/bluetooth -// -// SoftDevice overwrites original bootloader and flashing method described above is not available anymore. -// Instead, please use debug probe and flash your code with "nano-33-ble-s140v7" target. -package machine - -const HasLowFrequencyCrystal = true - -// Digital Pins -const ( - D2 Pin = P1_11 - D3 Pin = P1_12 - D4 Pin = P1_15 - D5 Pin = P1_13 - D6 Pin = P1_14 - D7 Pin = P0_23 - D8 Pin = P0_21 - D9 Pin = P0_27 - D10 Pin = P1_02 - D11 Pin = P1_01 - D12 Pin = P1_08 - D13 Pin = P0_13 -) - -// Analog pins -const ( - A0 Pin = P0_04 - A1 Pin = P0_05 - A2 Pin = P0_30 - A3 Pin = P0_29 - A4 Pin = P0_31 - A5 Pin = P0_02 - A6 Pin = P0_28 - A7 Pin = P0_03 -) - -// Onboard LEDs -const ( - LED = LED_BUILTIN - LED1 = LED_RED - LED2 = LED_GREEN - LED3 = LED_BLUE - LED_BUILTIN = P0_13 - LED_RED = P0_24 - LED_GREEN = P0_16 - LED_BLUE = P0_06 - LED_PWR = P1_09 -) - -// UART0 pins -const ( - UART_RX_PIN = P1_10 - UART_TX_PIN = P1_03 -) - -// I2C pins -const ( - // Defaults to internal - SDA_PIN = SDA1_PIN - SCL_PIN = SCL1_PIN - - // I2C0 (external) pins - SDA0_PIN = P0_31 - SCL0_PIN = P0_02 - - // I2C1 (internal) pins - SDA1_PIN = P0_14 - SCL1_PIN = P0_15 - - I2C_PULLUP = P1_00 // Set high for I2C to work -) - -// SPI pins -const ( - SPI0_SCK_PIN = P0_13 - SPI0_SDO_PIN = P1_01 - SPI0_SDI_PIN = P1_08 -) - -// Peripherals -const ( - APDS_INT = P0_19 // Proximity (APDS9960) interrupt pin - - LSM_PWR = P0_22 // IMU (LSM9DS1) power - LPS_PWR = P0_22 // Pressure (LPS22HB) power - HTS_PWR = P0_22 // Humidity (HTS221) power - - MIC_PWR = P0_17 // Microphone (MP34DT06JTR) power - MIC_CLK = P0_26 - MIC_DIN = P0_25 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Nano 33 BLE" - usb_STRING_MANUFACTURER = "Arduino" -) - -var ( - usb_VID uint16 = 0x2341 - usb_PID uint16 = 0x805a -) diff --git a/emb/machine/board_nano-rp2040.go b/emb/machine/board_nano-rp2040.go deleted file mode 100644 index 8155523..0000000 --- a/emb/machine/board_nano-rp2040.go +++ /dev/null @@ -1,126 +0,0 @@ -//go:build nano_rp2040 - -// This contains the pin mappings for the Arduino Nano RP2040 Connect board. -// -// Sometimes the board is not detected even when the board is connected to your computer. -// To solve this, place a jumper wire between the REC and GND pins, then connect the board to your computer. -// -// For more information, see: https://store.arduino.cc/nano-rp2040-connect -// Also -// - Datasheets: https://docs.arduino.cc/hardware/nano-rp2040-connect -// - Nano RP2040 Connect technical reference: https://docs.arduino.cc/tutorials/nano-rp2040-connect/rp2040-01-technical-reference -package machine - -// Digital Pins -const ( - D2 Pin = GPIO25 - D3 Pin = GPIO15 - D4 Pin = GPIO16 - D5 Pin = GPIO17 - D6 Pin = GPIO18 - D7 Pin = GPIO19 - D8 Pin = GPIO20 - D9 Pin = GPIO21 - D10 Pin = GPIO5 - D11 Pin = GPIO7 - D12 Pin = GPIO4 - D13 Pin = GPIO6 - D14 Pin = GPIO26 - D15 Pin = GPIO27 - D16 Pin = GPIO28 - D17 Pin = GPIO29 - D18 Pin = GPIO12 - D19 Pin = GPIO13 -) - -// Analog pins -const ( - A0 Pin = ADC0 - A1 Pin = ADC1 - A2 Pin = ADC2 - A3 Pin = ADC3 -) - -// Onboard LED -const ( - LED = GPIO6 -) - -// I2C pins -const ( - I2C0_SDA_PIN Pin = GPIO12 - I2C0_SCL_PIN Pin = GPIO13 - - I2C1_SDA_PIN Pin = GPIO18 - I2C1_SCL_PIN Pin = GPIO19 -) - -// SPI pins. SPI1 not available on Nano RP2040 Connect. -const ( - SPI0_SCK_PIN Pin = GPIO6 - SPI0_SDO_PIN Pin = GPIO7 - SPI0_SDI_PIN Pin = GPIO4 - - // GPIO22 does not have SPI functionality so we set it to avoid interfering with NINA. - SPI1_SCK_PIN Pin = GPIO22 - SPI1_SDO_PIN Pin = GPIO22 - SPI1_SDI_PIN Pin = GPIO22 -) - -var ( - NINA_SPI = SPI1 -) - -// NINA-W102 Pins -const ( - NINA_SCK Pin = GPIO14 - NINA_SDO Pin = GPIO11 - NINA_SDI Pin = GPIO8 - - NINA_CS Pin = GPIO9 - NINA_ACK Pin = GPIO10 - NINA_GPIO0 Pin = GPIO2 - NINA_RESETN Pin = GPIO3 - - NINA_TX Pin = GPIO8 - NINA_RX Pin = GPIO9 - NINA_CTS Pin = GPIO10 - NINA_RTS Pin = GPIO11 -) - -// NINA-W102 settings -const ( - NINA_BAUDRATE = 115200 - NINA_RESET_INVERTED = true - NINA_SOFT_FLOWCONTROL = false -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// USB CDC identifiers -// https://github.com/arduino/ArduinoCore-mbed/blob/master/variants/NANO_RP2040_CONNECT/pins_arduino.h -const ( - usb_STRING_PRODUCT = "Nano RP2040 Connect" - usb_STRING_MANUFACTURER = "Arduino" -) - -var ( - usb_VID uint16 = 0x2341 - usb_PID uint16 = 0x005e -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -// UART_NINA on the Arduino Nano RP2040 connects to the NINA HCI. -var UART_NINA = UART1 - -var DefaultUART = UART0 diff --git a/emb/machine/board_nicenano.go b/emb/machine/board_nicenano.go deleted file mode 100644 index 254e780..0000000 --- a/emb/machine/board_nicenano.go +++ /dev/null @@ -1,79 +0,0 @@ -//go:build nicenano - -package machine - -const HasLowFrequencyCrystal = true - -// GPIO Pins -const ( - D006 = P0_06 - D008 = P0_08 - D017 = P0_17 - D020 = P0_20 - D022 = P0_22 - D024 = P0_24 - D100 = P1_00 - D011 = P0_11 - D104 = P1_04 - D106 = P1_06 - - D004 = P0_04 // AIN2; P0.04 (AIN2) is used to read the voltage of the battery via ADC. It can’t be used for any other function. - D013 = P0_13 // VCC 3.3V; P0.13 on VCC shuts off the power to VCC when you set it to high; This saves on battery immensely for LEDs of all kinds that eat power even when off - D115 = P1_15 - D113 = P1_13 - D031 = P0_31 // AIN7 - D029 = P0_29 // AIN5 - D002 = P0_02 // AIN0 - - D111 = P1_11 - D010 = P0_10 // NFC2 - D009 = P0_09 // NFC1 - - D026 = P0_26 - D012 = P0_12 - D101 = P1_01 - D102 = P1_02 - D107 = P1_07 -) - -// Analog Pins -const ( - AIN2 = P0_04 // Battery - AIN7 = P0_31 - AIN5 = P0_29 - AIN0 = P0_02 -) - -const ( - LED = P0_15 -) - -// UART0 pins (logical UART1) -const ( - UART_RX_PIN = P0_06 - UART_TX_PIN = P0_08 -) - -// I2C pins -const ( - SDA_PIN = P0_17 // I2C0 external - SCL_PIN = P0_20 // I2C0 external -) - -// SPI pins -const ( - SPI0_SCK_PIN = P0_22 // SCK - SPI0_SDO_PIN = P0_24 // SDO - SPI0_SDI_PIN = P1_00 // SDI -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "nice!nano" - usb_STRING_MANUFACTURER = "Nice Keyboards" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x0029 -) diff --git a/emb/machine/board_nodemcu.go b/emb/machine/board_nodemcu.go deleted file mode 100644 index 5157c82..0000000 --- a/emb/machine/board_nodemcu.go +++ /dev/null @@ -1,35 +0,0 @@ -//go:build nodemcu - -// Pinout for the NodeMCU dev kit. - -package machine - -// GPIO pins on the NodeMCU board. -const ( - D0 = GPIO16 - D1 = GPIO5 - D2 = GPIO4 - D3 = GPIO0 - D4 = GPIO2 - D5 = GPIO14 - D6 = GPIO12 - D7 = GPIO13 - D8 = GPIO15 -) - -// Onboard blue LED (on the AI-Thinker module). -const LED = D4 - -// SPI pins -const ( - SPI0_SCK_PIN = D5 - SPI0_SDO_PIN = D7 - SPI0_SDI_PIN = D6 - SPI0_CS0_PIN = D8 -) - -// I2C pins -const ( - SDA_PIN = D2 - SCL_PIN = D1 -) diff --git a/emb/machine/board_nrf51.go b/emb/machine/board_nrf51.go deleted file mode 100644 index 74e2581..0000000 --- a/emb/machine/board_nrf51.go +++ /dev/null @@ -1,43 +0,0 @@ -//go:build nrf51 || microbit - -package machine - -func CPUFrequency() uint32 { - return 16000000 -} - -// Hardware pins -const ( - P0_00 Pin = 0 - P0_01 Pin = 1 - P0_02 Pin = 2 - P0_03 Pin = 3 - P0_04 Pin = 4 - P0_05 Pin = 5 - P0_06 Pin = 6 - P0_07 Pin = 7 - P0_08 Pin = 8 - P0_09 Pin = 9 - P0_10 Pin = 10 - P0_11 Pin = 11 - P0_12 Pin = 12 - P0_13 Pin = 13 - P0_14 Pin = 14 - P0_15 Pin = 15 - P0_16 Pin = 16 - P0_17 Pin = 17 - P0_18 Pin = 18 - P0_19 Pin = 19 - P0_20 Pin = 20 - P0_21 Pin = 21 - P0_22 Pin = 22 - P0_23 Pin = 23 - P0_24 Pin = 24 - P0_25 Pin = 25 - P0_26 Pin = 26 - P0_27 Pin = 27 - P0_28 Pin = 28 - P0_29 Pin = 29 - P0_30 Pin = 30 - P0_31 Pin = 31 -) diff --git a/emb/machine/board_nrf52840-mdk-usb-dongle.go b/emb/machine/board_nrf52840-mdk-usb-dongle.go deleted file mode 100644 index c30555c..0000000 --- a/emb/machine/board_nrf52840-mdk-usb-dongle.go +++ /dev/null @@ -1,48 +0,0 @@ -//go:build nrf52840_mdk_usb_dongle - -package machine - -const HasLowFrequencyCrystal = true - -// LEDs on the nrf52840-mdk-usb-dongle -const ( - LED Pin = LED_GREEN - LED_GREEN Pin = 22 - LED_RED Pin = 23 - LED_BLUE Pin = 24 -) - -// RESET/USR button, depending on value of PSELRESET UICR register -const ( - BUTTON Pin = 18 -) - -// UART pins -const ( - UART_TX_PIN Pin = NoPin - UART_RX_PIN Pin = NoPin -) - -// I2C pins (unused) -const ( - SDA_PIN = NoPin - SCL_PIN = NoPin -) - -// SPI pins (unused) -const ( - SPI0_SCK_PIN = NoPin - SPI0_SDO_PIN = NoPin - SPI0_SDI_PIN = NoPin -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Makerdiary nRF52840 MDK USB Dongle" - usb_STRING_MANUFACTURER = "Nordic Semiconductor ASA" -) - -var ( - usb_VID uint16 = 0x1915 - usb_PID uint16 = 0xCAFE -) diff --git a/emb/machine/board_nrf52840-mdk.go b/emb/machine/board_nrf52840-mdk.go deleted file mode 100644 index 20edde9..0000000 --- a/emb/machine/board_nrf52840-mdk.go +++ /dev/null @@ -1,43 +0,0 @@ -//go:build nrf52840_mdk - -package machine - -const HasLowFrequencyCrystal = true - -// LEDs on the nrf52840-mdk (nRF52840 dev board) -const ( - LED_GREEN Pin = 22 - LED_RED Pin = 23 - LED_BLUE Pin = 24 - LED Pin = LED_GREEN -) - -// UART pins -const ( - UART_TX_PIN Pin = 20 - UART_RX_PIN Pin = 19 -) - -// I2C pins (unused) -const ( - SDA_PIN = NoPin - SCL_PIN = NoPin -) - -// SPI pins (unused) -const ( - SPI0_SCK_PIN = NoPin - SPI0_SDO_PIN = NoPin - SPI0_SDI_PIN = NoPin -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Makerdiary nRF52840 MDK" - usb_STRING_MANUFACTURER = "Nordic Semiconductor ASA" -) - -var ( - usb_VID uint16 = 0x1915 - usb_PID uint16 = 0xCAFE -) diff --git a/emb/machine/board_nrf52840.go b/emb/machine/board_nrf52840.go deleted file mode 100644 index e7f1f89..0000000 --- a/emb/machine/board_nrf52840.go +++ /dev/null @@ -1,55 +0,0 @@ -//go:build nrf52840 || circuitplay_bluefruit || reelboard || clue || itsybitsy_nrf52840 - -package machine - -// Hardware pins -const ( - P0_00 Pin = 0 - P0_01 Pin = 1 - P0_02 Pin = 2 - P0_03 Pin = 3 - P0_04 Pin = 4 - P0_05 Pin = 5 - P0_06 Pin = 6 - P0_07 Pin = 7 - P0_08 Pin = 8 - P0_09 Pin = 9 - P0_10 Pin = 10 - P0_11 Pin = 11 - P0_12 Pin = 12 - P0_13 Pin = 13 - P0_14 Pin = 14 - P0_15 Pin = 15 - P0_16 Pin = 16 - P0_17 Pin = 17 - P0_18 Pin = 18 - P0_19 Pin = 19 - P0_20 Pin = 20 - P0_21 Pin = 21 - P0_22 Pin = 22 - P0_23 Pin = 23 - P0_24 Pin = 24 - P0_25 Pin = 25 - P0_26 Pin = 26 - P0_27 Pin = 27 - P0_28 Pin = 28 - P0_29 Pin = 29 - P0_30 Pin = 30 - P0_31 Pin = 31 - P1_00 Pin = 32 - P1_01 Pin = 33 - P1_02 Pin = 34 - P1_03 Pin = 35 - P1_04 Pin = 36 - P1_05 Pin = 37 - P1_06 Pin = 38 - P1_07 Pin = 39 - P1_08 Pin = 40 - P1_09 Pin = 41 - P1_10 Pin = 42 - P1_11 Pin = 43 - P1_12 Pin = 44 - P1_13 Pin = 45 - P1_14 Pin = 46 - P1_15 Pin = 47 -) diff --git a/emb/machine/board_nrf52840_generic.go b/emb/machine/board_nrf52840_generic.go deleted file mode 100644 index 1cf30e2..0000000 --- a/emb/machine/board_nrf52840_generic.go +++ /dev/null @@ -1,25 +0,0 @@ -//go:build nrf52840 && nrf52840_generic - -package machine - -var ( - LED = NoPin - SDA_PIN = NoPin - SCL_PIN = NoPin - UART_TX_PIN = NoPin - UART_RX_PIN = NoPin - SPI0_SCK_PIN = NoPin - SPI0_SDO_PIN = NoPin - SPI0_SDI_PIN = NoPin - - // https://pid.codes/org/TinyGo/ - usb_VID uint16 = 0x1209 - usb_PID uint16 = 0x9090 - - usb_STRING_MANUFACTURER = "TinyGo" - usb_STRING_PRODUCT = "nRF52840 Generic board" -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_nucleof103rb.go b/emb/machine/board_nucleof103rb.go deleted file mode 100644 index af7a99e..0000000 --- a/emb/machine/board_nucleof103rb.go +++ /dev/null @@ -1,55 +0,0 @@ -//go:build nucleof103rb - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - LED = LED_BUILTIN - LED_BUILTIN = LED_GREEN - LED_GREEN = PA5 -) - -const ( - BUTTON = BUTTON_USER - BUTTON_USER = PC13 -) - -// UART pins -const ( - UART_TX_PIN = PA2 - UART_RX_PIN = PA3 - UART_ALT_TX_PIN = PD5 - UART_ALT_RX_PIN = PD6 -) - -var ( - // USART2 is the hardware serial port connected to the onboard ST-LINK - // debugger to be exposed as virtual COM port over USB on Nucleo boards. - UART2 = &_UART2 - _UART2 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART2, - } - DefaultUART = UART2 -) - -func init() { - UART2.Interrupt = interrupt.New(stm32.IRQ_USART2, _UART2.handleInterrupt) -} - -// SPI pins -const ( - SPI0_SCK_PIN = PA5 - SPI0_SDI_PIN = PA6 - SPI0_SDO_PIN = PA7 -) - -// I2C pins -const ( - I2C0_SCL_PIN = PB6 - I2C0_SDA_PIN = PB7 -) diff --git a/emb/machine/board_nucleof722ze.go b/emb/machine/board_nucleof722ze.go deleted file mode 100644 index c9a0b01..0000000 --- a/emb/machine/board_nucleof722ze.go +++ /dev/null @@ -1,68 +0,0 @@ -//go:build nucleof722ze - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - LED = LED_BUILTIN - LED_BUILTIN = LED_GREEN - LED_GREEN = PB0 - LED_BLUE = PB7 - LED_RED = PB14 -) - -const ( - BUTTON = BUTTON_USER - BUTTON_USER = PC13 -) - -// UART pins -const ( - // PD8 and PD9 are connected to the ST-Link Virtual Com Port (VCP) - UART_TX_PIN = PD8 - UART_RX_PIN = PD9 - UART_ALT_FN = 7 // GPIO_AF7_UART3 -) - -var ( - // USART3 is the hardware serial port connected to the onboard ST-LINK - // debugger to be exposed as virtual COM port over USB on Nucleo boards. - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART3, - TxAltFuncSelector: UART_ALT_FN, - RxAltFuncSelector: UART_ALT_FN, - } - DefaultUART = UART1 -) - -func init() { - UART1.Interrupt = interrupt.New(stm32.IRQ_USART3, _UART1.handleInterrupt) -} - -// SPI pins -const ( - SPI0_SCK_PIN = PA5 - SPI0_SDI_PIN = PA6 - SPI0_SDO_PIN = PA7 -) - -// I2C pins -const ( - I2C0_SCL_PIN = PB8 - I2C0_SDA_PIN = PB9 -) - -var ( - // I2C1 is documented, alias to I2C0 as well - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: 4, - } - I2C0 = I2C1 -) diff --git a/emb/machine/board_nucleol031k6.go b/emb/machine/board_nucleol031k6.go deleted file mode 100644 index aea92d8..0000000 --- a/emb/machine/board_nucleol031k6.go +++ /dev/null @@ -1,98 +0,0 @@ -//go:build nucleol031k6 - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - // Arduino Pins - A0 = PA0 // ADC_IN0 - A1 = PA1 // ADC_IN1 - A2 = PA3 // ADC_IN3 - A3 = PA4 // ADC_IN4 - A4 = PA5 // ADC_IN5 || I2C1_SDA - A5 = PA6 // ADC_IN6 || I2C1_SCL - A6 = PA7 // ADC_IN7 - A7 = PA2 // ADC_IN2 - - D0 = PA10 // USART1_TX - D1 = PA9 // USART1_RX - D2 = PA12 - D3 = PB0 // TIM2_CH3 - D4 = PB7 - D5 = PB6 // TIM16_CH1N - D6 = PB1 // TIM14_CH1 - D9 = PA8 // TIM1_CH1 - D10 = PA11 // SPI_CS || TIM1_CH4 - D11 = PB5 // SPI1_MOSI || TIM3_CH2 - D12 = PB4 // SPI1_MISO - D13 = PB3 // SPI1_SCK -) - -const ( - LED = LED_BUILTIN - LED_BUILTIN = LED_GREEN - LED_GREEN = PB3 -) - -const ( - // This board does not have a user button, so - // use first GPIO pin by default - BUTTON = PA0 -) - -const ( - // UART pins - // PA2 and PA15 are connected to the ST-Link Virtual Com Port (VCP) - UART_TX_PIN = PA2 - UART_RX_PIN = PA15 - - // SPI - SPI1_SCK_PIN = PB3 - SPI1_SDI_PIN = PB5 - SPI1_SDO_PIN = PB4 - SPI0_SCK_PIN = SPI1_SCK_PIN - SPI0_SDI_PIN = SPI1_SDI_PIN - SPI0_SDO_PIN = SPI1_SDO_PIN - - // I2C pins - // PB6 and PB7 are mapped to CN4 pin 7 and CN4 pin 8 respectively with the - // default solder bridge settings - I2C0_SCL_PIN = PB7 - I2C0_SDA_PIN = PB6 - I2C0_ALT_FUNC = 1 -) - -var ( - // USART2 is the hardware serial port connected to the onboard ST-LINK - // debugger to be exposed as virtual COM port over USB on Nucleo boards. - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART2, - TxAltFuncSelector: 4, - RxAltFuncSelector: 4, - } - DefaultUART = UART1 - - // I2C1 is documented, alias to I2C0 as well - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: 1, - } - I2C0 = I2C1 - - // SPI - SPI0 = &SPI{ - Bus: stm32.SPI1, - AltFuncSelector: 0, - } - SPI1 = SPI0 -) - -func init() { - UART1.Interrupt = interrupt.New(stm32.IRQ_USART2, _UART1.handleInterrupt) -} diff --git a/emb/machine/board_nucleol432kc.go b/emb/machine/board_nucleol432kc.go deleted file mode 100644 index 3d09b6c..0000000 --- a/emb/machine/board_nucleol432kc.go +++ /dev/null @@ -1,100 +0,0 @@ -//go:build nucleol432kc - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - // Arduino Pins - A0 = PA0 - A1 = PA1 - A2 = PA3 - A3 = PA4 - A4 = PA5 - A5 = PA6 - A6 = PA7 - A7 = PA2 - - D0 = PA10 - D1 = PA9 - D2 = PA12 - D3 = PB0 - D4 = PB7 - D5 = PB6 - D6 = PB1 - D7 = PC14 - D8 = PC15 - D9 = PA8 - D10 = PA11 - D11 = PB5 - D12 = PB4 - D13 = PB3 -) - -const ( - LED = LED_BUILTIN - LED_BUILTIN = LED_GREEN - LED_GREEN = PB3 -) - -const ( - // This board does not have a user button, so - // use first GPIO pin by default - BUTTON = PA0 -) - -const ( - // UART pins - // PA2 and PA15 are connected to the ST-Link Virtual Com Port (VCP) - UART_TX_PIN = PA2 - UART_RX_PIN = PA15 - - // I2C pins - // With default solder bridge settings: - // PB6 / Arduino D5 / CN3 Pin 8 is SCL - // PB7 / Arduino D4 / CN3 Pin 7 is SDA - I2C0_SCL_PIN = PB6 - I2C0_SDA_PIN = PB7 - - // SPI pins - SPI1_SCK_PIN = PB3 - SPI1_SDI_PIN = PB5 - SPI1_SDO_PIN = PB4 - SPI0_SCK_PIN = SPI1_SCK_PIN - SPI0_SDI_PIN = SPI1_SDI_PIN - SPI0_SDO_PIN = SPI1_SDO_PIN -) - -var ( - // USART2 is the hardware serial port connected to the onboard ST-LINK - // debugger to be exposed as virtual COM port over USB on Nucleo boards. - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART2, - TxAltFuncSelector: 7, - RxAltFuncSelector: 3, - } - DefaultUART = UART1 - - // I2C1 is documented, alias to I2C0 as well - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: 4, - } - I2C0 = I2C1 - - // SPI1 is documented, alias to SPI0 as well - SPI1 = &SPI{ - Bus: stm32.SPI1, - AltFuncSelector: 5, - } - SPI0 = SPI1 -) - -func init() { - UART1.Interrupt = interrupt.New(stm32.IRQ_USART2, _UART1.handleInterrupt) -} diff --git a/emb/machine/board_nucleol476rg.go b/emb/machine/board_nucleol476rg.go deleted file mode 100644 index 0a173af..0000000 --- a/emb/machine/board_nucleol476rg.go +++ /dev/null @@ -1,105 +0,0 @@ -//go:build nucleol476rg - -// Schematic: https://www.st.com/resource/en/user_manual/um1724-stm32-nucleo64-boards-mb1136-stmicroelectronics.pdf -// Datasheet: https://www.st.com/resource/en/datasheet/stm32l476je.pdf - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - // Arduino Pins - A0 = PA0 - A1 = PA1 - A2 = PA4 - A3 = PB0 - A4 = PC1 - A5 = PC0 - - D0 = PA3 - D1 = PA2 - D2 = PA10 - D3 = PB3 - D4 = PB5 - D5 = PB4 - D6 = PB10 - D7 = PA8 - D8 = PA9 - D9 = PC7 - D10 = PB6 - D11 = PA7 - D12 = PA6 - D13 = PA5 - D14 = PB9 - D15 = PB8 -) - -// User LD2: the green LED is a user LED connected to ARDUINO® signal D13 corresponding -// to STM32 I/O PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. -const ( - LED = LED_BUILTIN - LED_BUILTIN = LED_GREEN - LED_GREEN = PA5 -) - -const ( - // This board does not have a user button, so - // use first GPIO pin by default - BUTTON = PA0 -) - -const ( - // UART pins - // PA2 and PA3 are connected to the ST-Link Virtual Com Port (VCP) - UART_TX_PIN = PA2 - UART_RX_PIN = PA3 - - // I2C pins - // With default solder bridge settings: - // PB8 / Arduino D5 / CN3 Pin 8 is SCL - // PB7 / Arduino D4 / CN3 Pin 7 is SDA - I2C0_SCL_PIN = PB8 - I2C0_SDA_PIN = PB9 - - // SPI pins - SPI1_SCK_PIN = PA5 - SPI1_SDI_PIN = PA6 - SPI1_SDO_PIN = PA7 - SPI0_SCK_PIN = SPI1_SCK_PIN - SPI0_SDI_PIN = SPI1_SDI_PIN - SPI0_SDO_PIN = SPI1_SDO_PIN -) - -var ( - // USART2 is the hardware serial port connected to the onboard ST-LINK - // debugger to be exposed as virtual COM port over USB on Nucleo boards. - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART2, - TxAltFuncSelector: AF7_USART1_2_3, - RxAltFuncSelector: AF7_USART1_2_3, - } - DefaultUART = UART1 - - // I2C1 is documented, alias to I2C0 as well - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: AF4_I2C1_2_3, - } - I2C0 = I2C1 - - // SPI1 is documented, alias to SPI0 as well - SPI1 = &SPI{ - Bus: stm32.SPI1, - AltFuncSelector: AF5_SPI1_2, - } - SPI0 = SPI1 -) - -func init() { - UART1.Interrupt = interrupt.New(stm32.IRQ_USART2, _UART1.handleInterrupt) -} diff --git a/emb/machine/board_nucleol552ze.go b/emb/machine/board_nucleol552ze.go deleted file mode 100644 index 6a13d9f..0000000 --- a/emb/machine/board_nucleol552ze.go +++ /dev/null @@ -1,60 +0,0 @@ -//go:build nucleol552ze - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - LED_GREEN = PC7 - LED_BLUE = PB7 - LED_RED = PA9 - LED_BUILTIN = LED_GREEN - LED = LED_BUILTIN -) - -const ( - BUTTON = BUTTON_USER - BUTTON_USER = PC13 -) - -// UART pins -const ( - // PG7 and PG8 are connected to the ST-Link Virtual Com Port (VCP) - UART_TX_PIN = PG7 - UART_RX_PIN = PG8 - UART_ALT_FN = 8 // GPIO_AF8_LPUART1 -) - -var ( - // LPUART1 is the hardware serial port connected to the onboard ST-LINK - // debugger to be exposed as virtual COM port over USB on Nucleo boards. - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.LPUART1, - TxAltFuncSelector: UART_ALT_FN, - RxAltFuncSelector: UART_ALT_FN, - } - DefaultUART = UART1 -) - -const ( - I2C0_SCL_PIN = PB8 - I2C0_SDA_PIN = PB9 -) - -var ( - // I2C1 is documented, alias to I2C0 as well - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: 4, - } - I2C0 = I2C1 -) - -func init() { - UART1.Interrupt = interrupt.New(stm32.IRQ_LPUART1, _UART1.handleInterrupt) -} diff --git a/emb/machine/board_nucleowl55jc.go b/emb/machine/board_nucleowl55jc.go deleted file mode 100644 index a8e88dd..0000000 --- a/emb/machine/board_nucleowl55jc.go +++ /dev/null @@ -1,96 +0,0 @@ -//go:build nucleowl55jc - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - LED_BLUE = PB15 - LED_GREEN = PB9 - LED_RED = PB11 - LED = LED_RED - - BTN1 = PA0 - BTN2 = PA1 - BTN3 = PC6 - BUTTON = BTN1 - - // SubGhz (SPI3) - SPI0_NSS_PIN = PA4 - SPI0_SCK_PIN = PA5 - SPI0_SDO_PIN = PA6 - SPI0_SDI_PIN = PA7 - - //MCU USART1 - UART1_TX_PIN = PB6 - UART1_RX_PIN = PB7 - - //MCU USART2 - UART2_RX_PIN = PA3 - UART2_TX_PIN = PA2 - - // DEFAULT USART - UART_RX_PIN = UART2_RX_PIN - UART_TX_PIN = UART2_TX_PIN - - // I2C1 pins - I2C1_SCL_PIN = PA9 - I2C1_SDA_PIN = PA10 - I2C1_ALT_FUNC = 4 - - // I2C2 pins - I2C2_SCL_PIN = PA12 - I2C2_SDA_PIN = PA11 - I2C2_ALT_FUNC = 4 - - // I2C0 alias for I2C1 - I2C0_SDA_PIN = I2C1_SDA_PIN - I2C0_SCL_PIN = I2C1_SCL_PIN -) - -var ( - // STM32 UART2 is connected to the embedded STLINKV3 Virtual Com Port - UART0 = &_UART0 - _UART0 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART2, - TxAltFuncSelector: 7, - RxAltFuncSelector: 7, - } - - // UART1 is free - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART1, - TxAltFuncSelector: 7, - RxAltFuncSelector: 7, - } - - DefaultUART = UART0 - - // I2C Busses - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: I2C1_ALT_FUNC, - } - I2C2 = &I2C{ - Bus: stm32.I2C2, - AltFuncSelector: I2C2_ALT_FUNC, - } - I2C0 = I2C1 - - // SPI - SPI3 = &SPI{ - Bus: stm32.SPI3, - } -) - -func init() { - // Enable UARTs Interrupts - UART0.Interrupt = interrupt.New(stm32.IRQ_USART2, _UART0.handleInterrupt) - UART1.Interrupt = interrupt.New(stm32.IRQ_USART1, _UART1.handleInterrupt) -} diff --git a/emb/machine/board_p1am-100.go b/emb/machine/board_p1am-100.go deleted file mode 100644 index f2a7d13..0000000 --- a/emb/machine/board_p1am-100.go +++ /dev/null @@ -1,140 +0,0 @@ -//go:build p1am_100 - -// This contains the pin mappings for the ProductivityOpen P1AM-100 board. -// -// For more information, see: https://facts-engineering.github.io/ -package machine - -// used to reset into bootloader -const resetMagicValue = 0x07738135 - -// Note: On the P1AM-100, pins D8, D9, D10, A3, and A4 are used for -// communication with the base controller. - -// GPIO Pins -const ( - D0 Pin = PA22 // PWM available - D1 Pin = PA23 // PWM available - D2 Pin = PA10 // PWM available - D3 Pin = PA11 // PWM available - D4 Pin = PB10 // PWM available - D5 Pin = PB11 // PWM available - D6 Pin = PA20 // PWM available - D7 Pin = PA21 // PWM available - - D8 Pin = PA16 // PWM available - D9 Pin = PA17 - D10 Pin = PA19 // PWM available - D11 Pin = PA08 - D12 Pin = PA09 - D13 Pin = PB23 - D14 Pin = PB22 - - // Remaining pins are shared with analog pins - D15 Pin = PA02 - - D16 Pin = PB02 - D17 Pin = PB03 - D18 Pin = PA04 // PWM available - D19 Pin = PA05 // PWM available - D20 Pin = PA06 - D21 Pin = PA07 -) - -// Analog pins -const ( - A0 Pin = PA02 // ADC/AIN[0] - A1 Pin = PB02 // ADC/AIN[10] - A2 Pin = PB03 // ADC/AIN[11] - A3 Pin = PA04 // ADC/AIN[4] - A4 Pin = PA05 // ADC/AIN[5] - A5 Pin = PA06 // ADC/AIN[6] - A6 Pin = PA07 // ADC/AIN[7] -) - -const ( - SWITCH Pin = PA28 - LED Pin = PB08 - ADC_BATTERY Pin = PB09 // ADC/AIN[3] -) - -// P1AM Base Controller -const ( - BASE_SLAVE_SELECT_PIN Pin = A3 - BASE_SLAVE_ACK_PIN Pin = A4 - BASE_ENABLE_PIN Pin = PB09 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN Pin = PA24 - USBCDC_DP_PIN Pin = PA25 - USBCDC_HOST_ENABLE_PIN Pin = PA18 -) - -// UART1 pins -const ( - UART_RX_PIN Pin = PB23 // RX: SERCOM5/PAD[3] - UART_TX_PIN Pin = PB22 // TX: SERCOM5/PAD[2] -) - -// UART1 on the P1AM-100 connects to the normal TX/RX pins. -var UART1 = &sercomUSART5 - -// I2C pins -const ( - SDA_PIN Pin = PA08 // SDA: SERCOM0/PAD[0] - SCL_PIN Pin = PA09 // SCL: SERCOM0/PAD[1] -) - -// I2C on the P1AM-100. -var ( - I2C0 = sercomI2CM0 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = D9 // SCK: SERCOM1/PAD[1] - SPI0_SDO_PIN Pin = D8 // SDO: SERCOM1/PAD[0] - SPI0_SDI_PIN Pin = D10 // SDI: SERCOM1/PAD[3] -) - -// SD card pins -const ( - SDCARD_SDI_PIN Pin = PA15 // SDI: SERCOM2/PAD[3] - SDCARD_SDO_PIN Pin = PA12 // SDO: SERCOM2/PAD[0] - SDCARD_SCK_PIN Pin = PA13 // SCK: SERCOM2/PAD[1] - SDCARD_SS_PIN Pin = PA14 // SS: as GPIO - SDCARD_CD_PIN Pin = PA27 -) - -// SPI on the P1AM-100 is used for Base Controller. -var ( - SPI0 = sercomSPIM1 - BASE_CONTROLLER_SPI = SPI0 -) - -// SPI1 is connected to the SD card slot on the P1AM-100 -var ( - SPI1 = sercomSPIM2 - SDCARD_SPI = SPI1 -) - -// I2S pins -const ( - I2S_SCK_PIN Pin = D2 - I2S_SDO_PIN Pin = A6 - I2S_SDI_PIN = NoPin - I2S_WS_PIN = D3 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "P1AM-100" - usb_STRING_MANUFACTURER = "Facts Engineering" -) - -var ( - usb_VID uint16 = 0x1354 - usb_PID uint16 = 0x4000 -) diff --git a/emb/machine/board_particle_argon.go b/emb/machine/board_particle_argon.go deleted file mode 100644 index efd8613..0000000 --- a/emb/machine/board_particle_argon.go +++ /dev/null @@ -1,106 +0,0 @@ -//go:build particle_argon - -package machine - -const HasLowFrequencyCrystal = true - -// More info: https://docs.particle.io/datasheets/wi-fi/argon-datasheet/ -// Board diagram: https://docs.particle.io/assets/images/argon/argon-block-diagram.png - -// GPIOs -const ( - A0 Pin = 3 - A1 Pin = 4 - A2 Pin = 28 - A3 Pin = 29 - A4 Pin = 30 - A5 Pin = 31 - D0 Pin = 26 // Also SDA - D1 Pin = 27 // Also SCL - D2 Pin = 33 - D3 Pin = 34 - D4 Pin = 40 - D5 Pin = 42 - D6 Pin = 43 - D7 Pin = 44 // Also LED - D8 Pin = 35 - D9 Pin = 6 // Also TX - D10 Pin = 8 // Also RX - D11 Pin = 46 // Also SDI - D12 Pin = 45 // Also SDO - D13 Pin = 47 // Also SCK -) - -// LEDs -const ( - LED Pin = 44 - LED_GREEN Pin = 14 - LED_RED Pin = 13 - LED_BLUE Pin = 15 -) - -// UART -var ( - DefaultUART = UART0 -) - -const ( - UART_TX_PIN Pin = 6 - UART_RX_PIN Pin = 8 -) - -// I2C pins -const ( - SDA_PIN Pin = 26 - SCL_PIN Pin = 27 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = 47 - SPI0_SDO_PIN Pin = 45 - SPI0_SDI_PIN Pin = 46 -) - -// Internal 4MB SPI Flash -const ( - SPI1_SCK_PIN Pin = 19 - SPI1_SDO_PIN Pin = 20 - SPI1_SDI_PIN Pin = 21 - SPI1_CS_PIN Pin = 17 - SPI1_WP_PIN Pin = 22 - SPI1_HOLD_PIN Pin = 23 -) - -// ESP32 coprocessor -const ( - ESP32_TXD_PIN Pin = 36 - ESP32_RXD_PIN Pin = 37 - ESP32_CTS_PIN Pin = 39 - ESP32_RTS_PIN Pin = 38 - ESP32_BOOT_MODE_PIN Pin = 16 - ESP32_WIFI_EN_PIN Pin = 24 - ESP32_HOST_WK_PIN Pin = 7 -) - -// Other peripherals -const ( - MODE_BUTTON_PIN Pin = 11 - CHARGE_STATUS_PIN Pin = 41 - LIPO_VOLTAGE_PIN Pin = 5 - PCB_ANTENNA_PIN Pin = 2 - EXTERNAL_UFL_PIN Pin = 25 - NFC1_PIN Pin = 9 - NFC2_PIN Pin = 10 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Argon" - usb_STRING_MANUFACTURER = "Particle" -) - -var ( - usb_VID uint16 = 0x2B04 - usb_PID uint16 = 0xD00C -) diff --git a/emb/machine/board_particle_boron.go b/emb/machine/board_particle_boron.go deleted file mode 100644 index f986060..0000000 --- a/emb/machine/board_particle_boron.go +++ /dev/null @@ -1,109 +0,0 @@ -//go:build particle_boron - -package machine - -const HasLowFrequencyCrystal = true - -// More info: https://docs.particle.io/datasheets/cellular/boron-datasheet/ -// Board diagram: https://docs.particle.io/assets/images/boron/boron-block-diagram.png - -// GPIOs -const ( - A0 Pin = 3 - A1 Pin = 4 - A2 Pin = 28 - A3 Pin = 29 - A4 Pin = 30 - A5 Pin = 31 - D0 Pin = 26 // Also SDA - D1 Pin = 27 // Also SCL - D2 Pin = 33 - D3 Pin = 34 - D4 Pin = 40 - D5 Pin = 42 - D6 Pin = 43 - D7 Pin = 44 // Also LED - D8 Pin = 35 - D9 Pin = 6 // Also TX - D10 Pin = 8 // Also RX - D11 Pin = 46 // Also SDI - D12 Pin = 45 // Also SDO - D13 Pin = 47 // Also SCK -) - -// LEDs -const ( - LED Pin = 44 - LED_GREEN Pin = 14 - LED_RED Pin = 13 - LED_BLUE Pin = 15 -) - -// UART -var ( - DefaultUART = UART0 -) - -const ( - UART_TX_PIN Pin = 6 - UART_RX_PIN Pin = 8 -) - -// I2C pins -const ( - SDA_PIN Pin = 26 - SCL_PIN Pin = 27 - - // Internal I2C with MAX17043 (Fuel gauge) and BQ24195 (Power management) chips on it - SDA1_PIN Pin = 24 - SCL1_PIN Pin = 41 - INT1_PIN Pin = 5 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = 47 - SPI0_SDO_PIN Pin = 45 - SPI0_SDI_PIN Pin = 46 -) - -// Internal 4MB SPI Flash -const ( - SPI1_SCK_PIN Pin = 19 - SPI1_SDO_PIN Pin = 20 - SPI1_SDI_PIN Pin = 21 - SPI1_CS_PIN Pin = 17 - SPI1_WP_PIN Pin = 22 - SPI1_HOLD_PIN Pin = 23 -) - -// u-blox SARA coprocessor -const ( - SARA_TXD_PIN Pin = 37 - SARA_RXD_PIN Pin = 36 - SARA_CTS_PIN Pin = 38 - SARA_RTS_PIN Pin = 39 - SARA_RESET_PIN Pin = 12 - SARA_POWER_ON_PIN Pin = 16 - SARA_BUFF_EN_PIN Pin = 25 - SARA_VINT_PIN Pin = 2 -) - -// Other peripherals -const ( - MODE_BUTTON_PIN Pin = 11 - ANTENNA_SEL_PIN Pin = 7 // Low: chip antenna, High: External uFL - NFC1_PIN Pin = 9 - NFC2_PIN Pin = 10 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Boron" - usb_STRING_MANUFACTURER = "Particle" -) - -var ( - usb_VID uint16 = 0x2B04 - usb_PID uint16 = 0xD00D -) diff --git a/emb/machine/board_particle_xenon.go b/emb/machine/board_particle_xenon.go deleted file mode 100644 index 52c2b18..0000000 --- a/emb/machine/board_particle_xenon.go +++ /dev/null @@ -1,95 +0,0 @@ -//go:build particle_xenon - -package machine - -const HasLowFrequencyCrystal = true - -// More info: https://docs.particle.io/datasheets/discontinued/xenon-datasheet/ -// Board diagram: https://docs.particle.io/assets/images/xenon/xenon-block-diagram.png - -// GPIOs -const ( - A0 Pin = 3 - A1 Pin = 4 - A2 Pin = 28 - A3 Pin = 29 - A4 Pin = 30 - A5 Pin = 31 - D0 Pin = 26 // Also SDA - D1 Pin = 27 // Also SCL - D2 Pin = 33 - D3 Pin = 34 - D4 Pin = 40 - D5 Pin = 42 - D6 Pin = 43 - D7 Pin = 44 // Also LED - D8 Pin = 35 - D9 Pin = 6 // Also TX - D10 Pin = 8 // Also RX - D11 Pin = 46 // Also SDI - D12 Pin = 45 // Also SDO - D13 Pin = 47 // Also SCK -) - -// LEDs -const ( - LED Pin = 44 - LED_GREEN Pin = 14 - LED_RED Pin = 13 - LED_BLUE Pin = 15 -) - -// UART -var ( - DefaultUART = UART0 -) - -const ( - UART_TX_PIN Pin = 6 - UART_RX_PIN Pin = 8 -) - -// I2C pins -const ( - SDA_PIN Pin = 26 - SCL_PIN Pin = 27 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = 47 - SPI0_SDO_PIN Pin = 45 - SPI0_SDI_PIN Pin = 46 -) - -// Internal 4MB SPI Flash -const ( - SPI1_SCK_PIN Pin = 19 - SPI1_SDO_PIN Pin = 20 - SPI1_SDI_PIN Pin = 21 - SPI1_CS_PIN Pin = 17 - SPI1_WP_PIN Pin = 22 - SPI1_HOLD_PIN Pin = 23 -) - -// Other peripherals -const ( - MODE_BUTTON_PIN Pin = 11 - CHARGE_STATUS_PIN Pin = 41 - LIPO_VOLTAGE_PIN Pin = 5 - PCB_ANTENNA_PIN Pin = 24 - EXTERNAL_UFL_PIN Pin = 25 - NFC1_PIN Pin = 9 - NFC2_PIN Pin = 10 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Xenon" - usb_STRING_MANUFACTURER = "Particle" -) - -var ( - usb_VID uint16 = 0x2B04 - usb_PID uint16 = 0xD00E -) diff --git a/emb/machine/board_pca10031.go b/emb/machine/board_pca10031.go deleted file mode 100644 index 3d8f34f..0000000 --- a/emb/machine/board_pca10031.go +++ /dev/null @@ -1,41 +0,0 @@ -//go:build pca10031 - -// pca10031 is a nrf51 based dongle, intended for use in wireless applications. -// -// https://infocenter.nordicsemi.com/pdf/nRF51_Dongle_UG_v1.0.pdf -package machine - -// The pca10031 has a 32kHz crystal on board. -const HasLowFrequencyCrystal = true - -// LED on the pca10031 -const ( - LED1 = LED_RED - LED2 = LED_GREEN - LED3 = LED_BLUE - LED_RED = P0_21 - LED_GREEN = P0_22 - LED_BLUE = P0_23 - LED = LED_RED -) - -var DefaultUART = UART0 - -// UART pins -const ( - UART_TX_PIN = P0_09 - UART_RX_PIN = P0_11 -) - -// I2C pins (disabled) -const ( - SDA_PIN = NoPin - SCL_PIN = NoPin -) - -// SPI pins (unused) -const ( - SPI0_SCK_PIN = NoPin - SPI0_SDO_PIN = NoPin - SPI0_SDI_PIN = NoPin -) diff --git a/emb/machine/board_pca10040.go b/emb/machine/board_pca10040.go deleted file mode 100644 index a9be6ad..0000000 --- a/emb/machine/board_pca10040.go +++ /dev/null @@ -1,55 +0,0 @@ -//go:build pca10040 - -package machine - -// The PCA10040 has a low-frequency (32kHz) crystal oscillator on board. -const HasLowFrequencyCrystal = true - -// LEDs on the PCA10040 (nRF52832 dev board) -const ( - LED1 Pin = 17 - LED2 Pin = 18 - LED3 Pin = 19 - LED4 Pin = 20 - LED Pin = LED1 -) - -// Buttons on the PCA10040 (nRF52832 dev board) -const ( - BUTTON1 Pin = 13 - BUTTON2 Pin = 14 - BUTTON3 Pin = 15 - BUTTON4 Pin = 16 - BUTTON Pin = BUTTON1 -) - -var DefaultUART = UART0 - -// UART pins for NRF52840-DK -const ( - UART_TX_PIN Pin = 6 - UART_RX_PIN Pin = 8 -) - -// ADC pins -const ( - ADC0 Pin = 3 - ADC1 Pin = 4 - ADC2 Pin = 28 - ADC3 Pin = 29 - ADC4 Pin = 30 - ADC5 Pin = 31 -) - -// I2C pins -const ( - SDA_PIN Pin = 26 - SCL_PIN Pin = 27 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = 25 - SPI0_SDO_PIN Pin = 23 - SPI0_SDI_PIN Pin = 24 -) diff --git a/emb/machine/board_pca10056.go b/emb/machine/board_pca10056.go deleted file mode 100644 index 44a2d53..0000000 --- a/emb/machine/board_pca10056.go +++ /dev/null @@ -1,65 +0,0 @@ -//go:build pca10056 - -package machine - -const HasLowFrequencyCrystal = true - -// LEDs on the pca10056 -const ( - LED1 Pin = 13 - LED2 Pin = 14 - LED3 Pin = 15 - LED4 Pin = 16 - LED Pin = LED1 -) - -// Buttons on the pca10056 -const ( - BUTTON1 Pin = 11 - BUTTON2 Pin = 12 - BUTTON3 Pin = 24 - BUTTON4 Pin = 25 - BUTTON Pin = BUTTON1 -) - -var DefaultUART = UART0 - -// UART pins -const ( - UART_TX_PIN Pin = 6 - UART_RX_PIN Pin = 8 -) - -// ADC pins -const ( - ADC0 Pin = 3 - ADC1 Pin = 4 - ADC2 Pin = 28 - ADC3 Pin = 29 - ADC4 Pin = 30 - ADC5 Pin = 31 -) - -// I2C pins -const ( - SDA_PIN Pin = 26 // P0.26 - SCL_PIN Pin = 27 // P0.27 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = 47 // P1.15 - SPI0_SDO_PIN Pin = 45 // P1.13 - SPI0_SDI_PIN Pin = 46 // P1.14 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Nordic nRF52840DK (PCA10056)" - usb_STRING_MANUFACTURER = "Nordic Semiconductor" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8029 -) diff --git a/emb/machine/board_pca10059.go b/emb/machine/board_pca10059.go deleted file mode 100644 index bd11503..0000000 --- a/emb/machine/board_pca10059.go +++ /dev/null @@ -1,59 +0,0 @@ -//go:build pca10059 - -package machine - -// The PCA10040 has a low-frequency (32kHz) crystal oscillator on board. -const HasLowFrequencyCrystal = true - -// LEDs on the PCA10059 (nRF52840 dongle) -const ( - LED1 Pin = 6 - LED2 Pin = 8 - LED3 Pin = (1 << 5) | 9 - LED4 Pin = 12 - LED Pin = LED1 -) - -// Buttons on the PCA10059 (nRF52840 dongle) -const ( - BUTTON1 Pin = (1 << 5) | 6 - BUTTON Pin = BUTTON1 -) - -// ADC pins -const ( - ADC1 Pin = 2 - ADC2 Pin = 4 - ADC3 Pin = 29 - ADC4 Pin = 31 -) - -// UART pins -const ( - UART_TX_PIN Pin = NoPin - UART_RX_PIN Pin = NoPin -) - -// I2C pins (unused) -const ( - SDA_PIN = NoPin - SCL_PIN = NoPin -) - -// SPI pins (unused) -const ( - SPI0_SCK_PIN = NoPin - SPI0_SDO_PIN = NoPin - SPI0_SDI_PIN = NoPin -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "nRF52840 Dongle" - usb_STRING_MANUFACTURER = "Nordic Semiconductor ASA" -) - -var ( - usb_VID uint16 = 0x1915 - usb_PID uint16 = 0xCAFE -) diff --git a/emb/machine/board_pga2350.go b/emb/machine/board_pga2350.go deleted file mode 100644 index 710f14d..0000000 --- a/emb/machine/board_pga2350.go +++ /dev/null @@ -1,98 +0,0 @@ -//go:build pga2350 - -package machine - -// PGA2350 pin definitions. -const ( - GP0 = GPIO0 - GP1 = GPIO1 - GP2 = GPIO2 - GP3 = GPIO3 - GP4 = GPIO4 - GP5 = GPIO5 - GP6 = GPIO6 - GP7 = GPIO7 - GP8 = GPIO8 - GP9 = GPIO9 - GP10 = GPIO10 - GP11 = GPIO11 - GP12 = GPIO12 - GP13 = GPIO13 - GP14 = GPIO14 - GP15 = GPIO15 - GP16 = GPIO16 - GP17 = GPIO17 - GP18 = GPIO18 - GP19 = GPIO19 - GP20 = GPIO20 - GP21 = GPIO21 - GP22 = GPIO22 - GP26 = GPIO26 - GP27 = GPIO27 - GP28 = GPIO28 - GP29 = GPIO29 - GP30 = GPIO30 // peripherals: PWM7 channel A - GP31 = GPIO31 // peripherals: PWM7 channel B - GP32 = GPIO32 // peripherals: PWM8 channel A - GP33 = GPIO33 // peripherals: PWM8 channel B - GP34 = GPIO34 // peripherals: PWM9 channel A - GP35 = GPIO35 // peripherals: PWM9 channel B - GP36 = GPIO36 // peripherals: PWM10 channel A - GP37 = GPIO37 // peripherals: PWM10 channel B - GP38 = GPIO38 // peripherals: PWM11 channel A - GP39 = GPIO39 // peripherals: PWM11 channel B - GP40 = GPIO40 // peripherals: PWM8 channel A - GP41 = GPIO41 // peripherals: PWM8 channel B - GP42 = GPIO42 // peripherals: PWM9 channel A - GP43 = GPIO43 // peripherals: PWM9 channel B - GP44 = GPIO44 // peripherals: PWM10 channel A - GP45 = GPIO45 // peripherals: PWM10 channel B - GP46 = GPIO46 // peripherals: PWM11 channel A - GP47 = GPIO47 // peripherals: PWM11 channel B - -) - -var DefaultUART = UART0 - -// Peripheral defaults. -const ( - xoscFreq = 12 // MHz - - I2C0_SDA_PIN = GP4 - I2C0_SCL_PIN = GP5 - - I2C1_SDA_PIN = GP2 - I2C1_SCL_PIN = GP3 - - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO18 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO19 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO16 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO10 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO11 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO12 // Rx - - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO8 - UART1_RX_PIN = GPIO9 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -// USB identifiers -const ( - usb_STRING_PRODUCT = "PGA2350" - usb_STRING_MANUFACTURER = "Pimoroni" -) - -var ( - usb_VID uint16 = 0x2E8A - usb_PID uint16 = 0x000A -) diff --git a/emb/machine/board_pico.go b/emb/machine/board_pico.go deleted file mode 100644 index efbd6ef..0000000 --- a/emb/machine/board_pico.go +++ /dev/null @@ -1,88 +0,0 @@ -//go:build pico - -package machine - -// GPIO pins -const ( - GP0 Pin = GPIO0 - GP1 Pin = GPIO1 - GP2 Pin = GPIO2 - GP3 Pin = GPIO3 - GP4 Pin = GPIO4 - GP5 Pin = GPIO5 - GP6 Pin = GPIO6 - GP7 Pin = GPIO7 - GP8 Pin = GPIO8 - GP9 Pin = GPIO9 - GP10 Pin = GPIO10 - GP11 Pin = GPIO11 - GP12 Pin = GPIO12 - GP13 Pin = GPIO13 - GP14 Pin = GPIO14 - GP15 Pin = GPIO15 - GP16 Pin = GPIO16 - GP17 Pin = GPIO17 - GP18 Pin = GPIO18 - GP19 Pin = GPIO19 - GP20 Pin = GPIO20 - GP21 Pin = GPIO21 - GP22 Pin = GPIO22 - GP26 Pin = GPIO26 - GP27 Pin = GPIO27 - GP28 Pin = GPIO28 - - // Onboard LED - LED Pin = GPIO25 - - // Onboard crystal oscillator frequency, in MHz. - xoscFreq = 12 // MHz -) - -// I2C Default pins on Raspberry Pico. -const ( - I2C0_SDA_PIN = GP4 - I2C0_SCL_PIN = GP5 - - I2C1_SDA_PIN = GP2 - I2C1_SCL_PIN = GP3 -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO18 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO19 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO16 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO10 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO11 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO12 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO8 - UART1_RX_PIN = GPIO9 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Pico" - usb_STRING_MANUFACTURER = "Raspberry Pi" -) - -var ( - usb_VID uint16 = 0x2E8A - usb_PID uint16 = 0x000A -) diff --git a/emb/machine/board_pico2.go b/emb/machine/board_pico2.go deleted file mode 100644 index 327c542..0000000 --- a/emb/machine/board_pico2.go +++ /dev/null @@ -1,88 +0,0 @@ -//go:build pico2 - -package machine - -// GPIO pins -const ( - GP0 Pin = GPIO0 - GP1 Pin = GPIO1 - GP2 Pin = GPIO2 - GP3 Pin = GPIO3 - GP4 Pin = GPIO4 - GP5 Pin = GPIO5 - GP6 Pin = GPIO6 - GP7 Pin = GPIO7 - GP8 Pin = GPIO8 - GP9 Pin = GPIO9 - GP10 Pin = GPIO10 - GP11 Pin = GPIO11 - GP12 Pin = GPIO12 - GP13 Pin = GPIO13 - GP14 Pin = GPIO14 - GP15 Pin = GPIO15 - GP16 Pin = GPIO16 - GP17 Pin = GPIO17 - GP18 Pin = GPIO18 - GP19 Pin = GPIO19 - GP20 Pin = GPIO20 - GP21 Pin = GPIO21 - GP22 Pin = GPIO22 - GP26 Pin = GPIO26 - GP27 Pin = GPIO27 - GP28 Pin = GPIO28 - - // Onboard LED - LED Pin = GPIO25 - - // Onboard crystal oscillator frequency, in MHz. - xoscFreq = 12 // MHz -) - -// I2C Default pins on Raspberry Pico. -const ( - I2C0_SDA_PIN = GP4 - I2C0_SCL_PIN = GP5 - - I2C1_SDA_PIN = GP2 - I2C1_SCL_PIN = GP3 -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO18 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO19 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO16 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO10 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO11 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO12 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO8 - UART1_RX_PIN = GPIO9 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Pico2" - usb_STRING_MANUFACTURER = "Raspberry Pi" -) - -var ( - usb_VID uint16 = 0x2E8A - usb_PID uint16 = 0x000A -) diff --git a/emb/machine/board_pico_plus2.go b/emb/machine/board_pico_plus2.go deleted file mode 100644 index c21c9ea..0000000 --- a/emb/machine/board_pico_plus2.go +++ /dev/null @@ -1,93 +0,0 @@ -//go:build pico_plus2 - -package machine - -// GPIO pins -const ( - GP0 Pin = GPIO0 - GP1 Pin = GPIO1 - GP2 Pin = GPIO2 - GP3 Pin = GPIO3 - GP4 Pin = GPIO4 - GP5 Pin = GPIO5 - GP6 Pin = GPIO6 - GP7 Pin = GPIO7 - GP8 Pin = GPIO8 - GP9 Pin = GPIO9 - GP10 Pin = GPIO10 - GP11 Pin = GPIO11 - GP12 Pin = GPIO12 - GP13 Pin = GPIO13 - GP14 Pin = GPIO14 - GP15 Pin = GPIO15 - GP16 Pin = GPIO16 - GP17 Pin = GPIO17 - GP18 Pin = GPIO18 - GP19 Pin = GPIO19 - GP20 Pin = GPIO20 - GP21 Pin = GPIO21 - GP22 Pin = GPIO22 - GP26 Pin = GPIO26 - GP27 Pin = GPIO27 - GP28 Pin = GPIO28 - GP32 Pin = GPIO32 - GP33 Pin = GPIO33 - GP34 Pin = GPIO34 - GP35 Pin = GPIO35 - GP36 Pin = GPIO36 - - // Onboard LED - LED Pin = GPIO25 - - // Onboard crystal oscillator frequency, in MHz. - xoscFreq = 12 // MHz -) - -// I2C Default pins on Raspberry Pico. -const ( - I2C0_SDA_PIN = GP4 - I2C0_SCL_PIN = GP5 - - I2C1_SDA_PIN = GP2 - I2C1_SCL_PIN = GP3 -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO18 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO19 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO16 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO10 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO11 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO12 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO8 - UART1_RX_PIN = GPIO9 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Pico Plus2" - usb_STRING_MANUFACTURER = "Pimoroni" -) - -var ( - usb_VID uint16 = 0x2E8A - usb_PID uint16 = 0x000F -) diff --git a/emb/machine/board_pinetime.go b/emb/machine/board_pinetime.go deleted file mode 100644 index f7a137b..0000000 --- a/emb/machine/board_pinetime.go +++ /dev/null @@ -1,60 +0,0 @@ -//go:build pinetime - -package machine - -// Board pins for the PineTime. -// Details: https://wiki.pine64.org/index.php/PineTime - -// The PineTime has a low-frequency (32kHz) crystal oscillator on board. -const HasLowFrequencyCrystal = true - -// LEDs simply expose the three brightness level LEDs on the PineTime. They can -// be useful for simple "hello world" style programs. -const ( - LED1 = LCD_BACKLIGHT_HIGH - LED2 = LCD_BACKLIGHT_MID - LED3 = LCD_BACKLIGHT_LOW - LED = LED1 -) - -// The PineTime doesn't have a UART output. -// Additionally, leaving the UART on results in a pretty big current drain. -const ( - UART_TX_PIN Pin = NoPin - UART_RX_PIN Pin = NoPin -) - -// SPI pins for the PineTime. -const ( - SPI0_SCK_PIN Pin = 2 - SPI0_SDO_PIN Pin = 3 - SPI0_SDI_PIN Pin = 4 -) - -// I2C pins for the PineTime. -const ( - SDA_PIN Pin = 6 - SCL_PIN Pin = 7 -) - -// Button pins. For some reason, there are two pins for the button. -const ( - BUTTON_IN Pin = 13 - BUTTON_OUT Pin = 15 -) - -// Pin for the vibrator. -const VIBRATOR_PIN Pin = 16 - -// LCD pins, using the naming convention of the official docs: -// http://files.pine64.org/doc/PineTime/PineTime%20Port%20Assignment%20rev1.0.pdf -const ( - LCD_SCK = SPI0_SCK_PIN - LCD_SDI = SPI0_SDO_PIN - LCD_RS Pin = 18 - LCD_CS Pin = 25 - LCD_RESET Pin = 26 - LCD_BACKLIGHT_LOW Pin = 14 - LCD_BACKLIGHT_MID Pin = 22 - LCD_BACKLIGHT_HIGH Pin = 23 -) diff --git a/emb/machine/board_pybadge.go b/emb/machine/board_pybadge.go deleted file mode 100644 index 30d44d1..0000000 --- a/emb/machine/board_pybadge.go +++ /dev/null @@ -1,162 +0,0 @@ -//go:build pybadge - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PB17 // UART0 RX/PWM available - D1 = PB16 // UART0 TX/PWM available - D2 = PB03 - D3 = PB02 - D4 = PA14 // PWM available - D5 = PA16 // PWM available - D6 = PA18 // PWM available - D7 = PB14 - D8 = PA15 // built-in neopixel - D9 = PA19 // PWM available - D10 = PA20 // can be used for PWM or UART1 TX - D11 = PA21 // can be used for PWM or UART1 RX - D12 = PA22 // PWM available - D13 = PA23 // PWM available -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PA05 // ADC/AIN[2] - A2 = PB08 // ADC/AIN[3] - A3 = PB09 // ADC/AIN[4] - A4 = PA04 // ADC/AIN[5] - A5 = PA06 // ADC/AIN[6] - A6 = PB01 // ADC/AIN[12]/VMEAS - A7 = PB04 // ADC/AIN[6]/LIGHT - A8 = D2 // ADC/AIN[14] - A9 = D3 // ADC/AIN[15] -) - -const ( - LED = D13 - NEOPIXELS = D8 - WS2812 = D8 - - LIGHTSENSOR = A7 - - BUTTON_LATCH = PB00 - BUTTON_OUT = PB30 - BUTTON_CLK = PB31 - - TFT_DC = PB05 - TFT_CS = PB07 - TFT_RST = PA00 - TFT_LITE = PA01 - - SPEAKER_ENABLE = PA27 -) - -const ( - BUTTON_LEFT_MASK = 1 - BUTTON_UP_MASK = 2 - BUTTON_DOWN_MASK = 4 - BUTTON_RIGHT_MASK = 8 - BUTTON_SELECT_MASK = 16 - BUTTON_START_MASK = 32 - BUTTON_A_MASK = 64 - BUTTON_B_MASK = 128 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN = D1 - UART_RX_PIN = D0 -) - -const ( - UART2_TX_PIN = A4 - UART2_RX_PIN = A5 -) - -var ( - UART1 = &sercomUSART5 - UART2 = &sercomUSART0 - - DefaultUART = UART1 -) - -// I2C pins -const ( - SDA_PIN = PA12 // SDA: SERCOM2/PAD[0] - SCL_PIN = PA13 // SCL: SERCOM2/PAD[1] -) - -// I2C on the ItsyBitsy M4. -var I2C0 = sercomI2CM2 - -// SPI pins -const ( - SPI0_SCK_PIN = PA17 // SCK: SERCOM1/PAD[1] - SPI0_SDO_PIN = PB23 // SDO: SERCOM1/PAD[3] - SPI0_SDI_PIN = PB22 // SDI: SERCOM1/PAD[2] -) - -// TFT SPI pins -const ( - SPI1_SCK_PIN = PB13 // SCK: SERCOM4/PAD[1] - SPI1_SDO_PIN = PB15 // SDO: SERCOM4/PAD[3] - SPI1_SDI_PIN = NoPin -) - -// SPI on the PyBadge. -var SPI0 = sercomSPIM1 - -// TFT SPI on the PyBadge. -var SPI1 = sercomSPIM4 - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit pyBadge M4" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8033 -) - -// NINA-W102 settings when using AirLift WiFi FeatherWing -const ( - NINA_BAUDRATE = 115200 - NINA_RESET_INVERTED = true - NINA_SOFT_FLOWCONTROL = true -) - -const ( - NINA_CS = D13 - NINA_ACK = D11 - NINA_GPIO0 = D10 - NINA_RESETN = D12 - - // pins used for the ESP32 connection do not allow hardware - // flow control, which is required. have to emulate with software. - NINA_TX = UART_TX_PIN - NINA_RX = UART_RX_PIN - NINA_CTS = NINA_ACK - NINA_RTS = NINA_GPIO0 - - NINA_SDO = SPI0_SDO_PIN - NINA_SDI = SPI0_SDI_PIN - NINA_SCK = SPI0_SCK_PIN -) - -var ( - NINA_SPI = SPI0 - UART_NINA = UART1 -) diff --git a/emb/machine/board_pygamer.go b/emb/machine/board_pygamer.go deleted file mode 100644 index 84a7464..0000000 --- a/emb/machine/board_pygamer.go +++ /dev/null @@ -1,133 +0,0 @@ -//go:build sam && atsamd51 && pygamer - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PB17 // UART0 RX/PWM available - D1 = PB16 // UART0 TX/PWM available - D2 = PB03 - D3 = PB02 - D4 = PA14 // PWM available - D5 = PA16 // PWM available - D6 = PA18 // PWM available - D7 = PB14 // CS for microSD card slot - D8 = PA15 // built-in neopixel - D9 = PA19 // PWM available - D10 = PA20 // can be used for PWM or UART1 TX - D11 = PA21 // can be used for PWM or UART1 RX - D12 = PA22 // PWM available - D13 = PA23 // PWM available -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PA05 // ADC/AIN[2] - A2 = PB08 // ADC/AIN[3] - A3 = PB09 // ADC/AIN[4] - A4 = PA04 // ADC/AIN[5] - A5 = PA06 // ADC/AIN[6] - A6 = PB01 // ADC/AIN[12]/VMEAS - A7 = PB04 // ADC/AIN[6]/LIGHT - A8 = D2 // ADC/AIN[14] - A9 = D3 // ADC/AIN[15] -) - -const ( - LED = D13 - NEOPIXELS = D8 - WS2812 = D8 - - SD_CS = D7 - - LIGHTSENSOR = A7 - - BUTTON_LATCH = PB00 - BUTTON_OUT = PB30 - BUTTON_CLK = PB31 - - JOYY = PB06 - JOYX = PB07 - - TFT_DC = PB05 - TFT_CS = PB12 - TFT_RST = PA00 - TFT_LITE = PA01 - - SPEAKER_ENABLE = PA27 -) - -const ( - BUTTON_SELECT_MASK = 16 - BUTTON_START_MASK = 32 - BUTTON_A_MASK = 64 - BUTTON_B_MASK = 128 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN = D1 - UART_RX_PIN = D0 -) - -// UART1 var is on SERCOM3, defined in atsamd51.go - -// UART2 pins -const ( - UART2_TX_PIN = A4 - UART2_RX_PIN = A5 -) - -// UART2 var is on SERCOM0, defined in atsamd51.go - -// I2C pins -const ( - SDA_PIN = PA12 // SDA: SERCOM2/PAD[0] - SCL_PIN = PA13 // SCL: SERCOM2/PAD[1] -) - -// I2C on the PyGamer. -var ( - I2C0 = sercomI2CM2 -) - -// SPI pins -const ( - SPI0_SCK_PIN = PA17 // SCK: SERCOM1/PAD[1] - SPI0_SDO_PIN = PB23 // SDO: SERCOM1/PAD[3] - SPI0_SDI_PIN = PB22 // SDI: SERCOM1/PAD[2] -) - -// SPI on the PyGamer. -var SPI0 = sercomSPIM1 - -// TFT SPI pins -const ( - SPI1_SCK_PIN = PB13 // SCK: SERCOM4/PAD[1] - SPI1_SDO_PIN = PB15 // SDO: SERCOM4/PAD[3] - SPI1_SDI_PIN = NoPin -) - -// TFT SPI on the PyGamer. -var SPI1 = sercomSPIM4 - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit pyGamer M4" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8033 -) diff --git a/emb/machine/board_pyportal.go b/emb/machine/board_pyportal.go deleted file mode 100644 index 98ef01d..0000000 --- a/emb/machine/board_pyportal.go +++ /dev/null @@ -1,165 +0,0 @@ -//go:build pyportal - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PB13 // NINA_RX - D1 = PB12 // NINA_TX - D2 = PB22 // built-in neopixel - D3 = PA04 // PWM available - D4 = PA05 // PWM available - D5 = PB16 // NINA_ACK - D6 = PB15 // NINA_GPIO0 - D7 = PB17 // NINA_RESETN - D8 = PB14 // NINA_CS - D9 = PB04 // TFT_RD - D10 = PB05 // TFT_DC - D11 = PB06 // TFT_CS - D12 = PB07 // TFT_TE - D13 = PB23 // built-in LED - D24 = PA00 // TFT_RESET - D25 = PB31 // TFT_BACKLIGHT - D26 = PB09 // TFT_WR - D27 = PB02 // SDA - D28 = PB03 // SCL - D29 = PA12 // SDO - D30 = PA13 // SCK - D31 = PA14 // SDI - D32 = PB30 // SD_CS - D33 = PA01 // SD_CARD_DETECT - D34 = PA16 // LCD_DATA0 - D35 = PA17 // LCD_DATA1 - D36 = PA18 // LCD_DATA2 - D37 = PA19 // LCD_DATA3 - D38 = PA20 // LCD_DATA4 - D39 = PA21 // LCD_DATA5 - D40 = PA22 // LCD_DATA6 - D41 = PA23 // LCD_DATA7 - D42 = PB10 // QSPI - D43 = PB11 // QSPI - D44 = PA08 // QSPI - D45 = PA09 // QSPI - D46 = PA10 // QSPI - D47 = PA11 // QSPI - D50 = PA02 // speaker amplifier shutdown - D51 = PA15 // NINA_RTS - - NINA_CS = D8 - NINA_ACK = D5 - NINA_GPIO0 = D6 - NINA_RESETN = D7 - - // pins used for the ESP32 connection do not allow hardware - // flow control, which is required. have to emulate with software. - NINA_TX = D1 - NINA_RX = D0 - NINA_CTS = NINA_ACK - NINA_RTS = NINA_GPIO0 - - LCD_DATA0 = D34 - - TFT_RD = D9 - TFT_DC = D10 - TFT_CS = D11 - TFT_TE = D12 - TFT_RESET = D24 - TFT_BACKLIGHT = D25 - TFT_WR = D26 - - NEOPIXEL = D2 - WS2812 = D2 - SPK_SD = D50 -) - -// Analog pins -const ( - A0 = PA02 // ADC0/AIN[0] - A1 = D3 // ADC0/AIN[4] - A2 = PA07 // ADC0/AIN[7] - A3 = D4 // ADC0/AIN[5] - A4 = PB00 // ADC0/AIN[12] - A5 = PB01 // ADC0/AIN[13] - A6 = PA06 // ADC0/AIN[6] - A7 = PB08 // ADC1/AIN[0] - - AUDIO_OUT = A0 - LIGHT = A2 - TOUCH_YD = A4 - TOUCH_XL = A5 - TOUCH_YU = A6 - TOUCH_XR = A7 -) - -const ( - LED = D13 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 aka NINA_TX/NINA_RX -const ( - UART_TX_PIN = D1 - UART_RX_PIN = D0 -) - -var ( - UART1 = &sercomUSART4 - - DefaultUART = UART1 - - UART_NINA = UART1 -) - -// NINA-W102 settings -const ( - NINA_BAUDRATE = 115200 - NINA_RESET_INVERTED = true - NINA_SOFT_FLOWCONTROL = true -) - -// I2C pins -const ( - SDA_PIN = PB02 // SDA: SERCOM2/PAD[0] - SCL_PIN = PB03 // SCL: SERCOM2/PAD[1] -) - -// I2C on the PyPortal. -var ( - I2C0 = sercomI2CM5 -) - -// SPI pins -const ( - SPI0_SCK_PIN = PA13 // SCK: SERCOM1/PAD[1] - SPI0_SDO_PIN = PA12 // SDO: SERCOM1/PAD[3] - SPI0_SDI_PIN = PA14 // SDI: SERCOM1/PAD[2] - - NINA_SDO = SPI0_SDO_PIN - NINA_SDI = SPI0_SDI_PIN - NINA_SCK = SPI0_SCK_PIN -) - -// SPI on the PyPortal. -var ( - SPI0 = sercomSPIM2 - NINA_SPI = SPI0 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit PyPortal M4" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x8035 -) diff --git a/emb/machine/board_qtpy.go b/emb/machine/board_qtpy.go deleted file mode 100644 index e8a93e3..0000000 --- a/emb/machine/board_qtpy.go +++ /dev/null @@ -1,102 +0,0 @@ -//go:build sam && atsamd21 && qtpy - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PA02 // PWM available - D1 = PA03 - D2 = PA04 // PWM available - D3 = PA05 // PWM available - D4 = PA16 // PWM available - D5 = PA17 // PWM available - D6 = PA06 - D7 = PA07 - D8 = PA11 - D9 = PA09 - D10 = PA10 - D11 = PA18 - D12 = PA15 - D13 = PA27 - D14 = PA23 - D15 = PA19 - D16 = PA22 - D17 = PA08 -) - -// Analog pins -const ( - A0 = D0 - A1 = D1 - A2 = D2 - A3 = D3 - A4 = D4 -) - -const ( - NEOPIXELS = D11 - WS2812 = D11 - NEOPIXELS_POWER = D12 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN = D6 - UART_RX_PIN = D7 -) - -// UART1 on the QT Py M0. -var UART1 = &sercomUSART0 - -// SPI pins -const ( - SPI0_SCK_PIN = D8 - SPI0_SDO_PIN = D10 - SPI0_SDI_PIN = D9 -) - -// SPI on the QT Py M0. -var SPI0 = sercomSPIM0 - -// I2C pins -const ( - SDA_PIN = D4 // SDA - SCL_PIN = D5 // SCL -) - -// I2C on the QT Py M0. -var ( - I2C0 = sercomI2CM1 -) - -// I2S pins -const ( - I2S_SCK_PIN = PA10 - I2S_SDO_PIN = PA08 - I2S_SDI_PIN = NoPin // TODO: figure out what this is on QT Py M0. - I2S_WS_PIN = NoPin // TODO: figure out what this is on QT Py M0. -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit QTPy M0" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x80CB -) - -var ( - DefaultUART = UART1 -) diff --git a/emb/machine/board_qtpy_esp32c3.go b/emb/machine/board_qtpy_esp32c3.go deleted file mode 100644 index a2e3f48..0000000 --- a/emb/machine/board_qtpy_esp32c3.go +++ /dev/null @@ -1,60 +0,0 @@ -//go:build qtpy_esp32c3 - -// This file contains the pin mappings for the Adafruit QtPy ESP32C3 boards. -// -// https://learn.adafruit.com/adafruit-qt-py-esp32-c3-wifi-dev-board/pinouts -package machine - -// Digital Pins -const ( - D0 = GPIO4 - D1 = GPIO3 - D2 = GPIO1 - D3 = GPIO0 -) - -// Analog pins (ADC1) -const ( - A0 = GPIO4 - A1 = GPIO3 - A2 = GPIO1 - A3 = GPIO0 -) - -// UART pins -const ( - RX_PIN = GPIO20 - TX_PIN = GPIO21 - - UART_RX_PIN = RX_PIN - UART_TX_PIN = TX_PIN -) - -// I2C pins -const ( - SDA_PIN = GPIO5 - SCL_PIN = GPIO6 - - I2C0_SDA_PIN = SDA_PIN - I2C0_SCL_PIN = SCL_PIN -) - -// SPI pins -const ( - SCK_PIN = GPIO10 - MI_PIN = GPIO8 - MO_PIN = GPIO7 - - SPI_SCK_PIN = SCK_PIN - SPI_SDI_PIN = MI_PIN - SPI_SDO_PIN = MO_PIN -) - -const ( - NEOPIXEL = GPIO2 - WS2812 = GPIO2 - - // also used for boot button. - // set it to be an input-with-pullup - BUTTON = GPIO9 -) diff --git a/emb/machine/board_qtpy_rp2040.go b/emb/machine/board_qtpy_rp2040.go deleted file mode 100644 index 3eabf0c..0000000 --- a/emb/machine/board_qtpy_rp2040.go +++ /dev/null @@ -1,93 +0,0 @@ -//go:build qtpy_rp2040 - -package machine - -// Onboard crystal oscillator frequency, in MHz. -const xoscFreq = 12 // MHz - -// GPIO Pins -const ( - SDA = GPIO24 - SCL = GPIO25 - TX = GPIO20 - MO = GPIO3 - MOSI = GPIO3 - MI = GPIO4 - MISO = GPIO4 - SCK = GPIO6 - RX = GPIO5 - - QT_SCL1 = GPIO23 - QT_SDA1 = GPIO22 -) - -// Analog pins -const ( - A0 = GPIO29 - A1 = GPIO28 - A2 = GPIO27 - A3 = GPIO26 -) - -const ( - NEOPIXEL = GPIO12 - WS2812 = GPIO12 - NEOPIXEL_POWER = GPIO11 -) - -// I2C Pins. -const ( - I2C0_SDA_PIN = GPIO24 - I2C0_SCL_PIN = GPIO25 - - I2C1_SDA_PIN = GPIO26 - I2C1_SCL_PIN = GPIO27 - - I2C1_QT_SDA_PIN = GPIO22 - I2C1_QT_SCL_PIN = GPIO23 - - SDA_PIN = GPIO24 - SCL_PIN = GPIO25 -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO6 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO3 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO4 // Rx - SPI0_CS = GPIO5 - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO26 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO27 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO24 // Rx - SPI1_CS = GPIO25 -) - -// UART pins -const ( - UART0_TX_PIN = GPIO28 - UART0_RX_PIN = GPIO29 - UART1_TX_PIN = GPIO20 - UART1_RX_PIN = GPIO5 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "QT Py RP2040" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x80F7 -) diff --git a/emb/machine/board_rak4631.go b/emb/machine/board_rak4631.go deleted file mode 100644 index c59f371..0000000 --- a/emb/machine/board_rak4631.go +++ /dev/null @@ -1,86 +0,0 @@ -//go:build rak4631 - -package machine - -const HasLowFrequencyCrystal = true - -// Digital Pins -const ( - D0 Pin = P0_28 - D1 Pin = P0_02 -) - -// Analog pins -const ( - A0 Pin = P0_17 - A1 Pin = P1_02 - A2 Pin = P0_21 -) - -// Onboard LEDs -const ( - LED = LED2 - LED1 = P1_03 - LED2 = P1_04 -) - -// UART pins -const ( - // Default to UART1 - UART_RX_PIN = UART0_RX_PIN - UART_TX_PIN = UART0_TX_PIN - - // UART1 - UART0_RX_PIN = P0_19 - UART0_TX_PIN = P0_20 - - // UART2 - UART1_RX_PIN = P0_15 - UART1_TX_PIN = P0_16 -) - -// I2C pins -const ( - SDA_PIN = SDA1_PIN - SCL_PIN = SCL1_PIN - - SDA1_PIN = P0_13 - SCL1_PIN = P0_14 - - SDA2_PIN = P0_24 - SCL2_PIN = P0_25 -) - -// SPI pins -const ( - SPI0_SCK_PIN = P0_03 - SPI0_SDO_PIN = P0_29 - SPI0_SDI_PIN = P0_30 -) - -// Peripherals -const ( - LORA_NSS = P1_10 - LORA_SCK = P1_11 - LORA_MOSI = P1_12 - LORA_MISO = P1_13 - LORA_BUSY = P1_14 - LORA_DIO1 = P1_15 - LORA_NRESET = P1_06 - LORA_POWER = P1_05 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "WisCore RAK4631 Board" - usb_STRING_MANUFACTURER = "RAKwireless" -) - -var ( - usb_VID uint16 = 0x239a - usb_PID uint16 = 0x8029 -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_reelboard.go b/emb/machine/board_reelboard.go deleted file mode 100644 index 3c84070..0000000 --- a/emb/machine/board_reelboard.go +++ /dev/null @@ -1,74 +0,0 @@ -//go:build reelboard - -package machine - -const HasLowFrequencyCrystal = true - -// Pins on the reel board -const ( - LED_RED Pin = 11 - LED_GREEN Pin = 12 - LED_BLUE Pin = 41 - LED_YELLOW Pin = 13 - LED1 Pin = LED_YELLOW - LED2 Pin = LED_RED - LED3 Pin = LED_GREEN - LED4 Pin = LED_BLUE - LED Pin = LED1 - EPD_BUSY_PIN Pin = 14 - EPD_RESET_PIN Pin = 15 - EPD_DC_PIN Pin = 16 - EPD_CS_PIN Pin = 17 - EPD_SCK_PIN Pin = 19 - EPD_SDO_PIN Pin = 20 - POWER_SUPPLY_PIN Pin = 32 -) - -// User "a" button on the reel board -const ( - BUTTON Pin = 7 -) - -var DefaultUART = UART0 - -// UART pins -const ( - UART_TX_PIN Pin = 6 - UART_RX_PIN Pin = 8 -) - -// I2C pins -const ( - SDA_PIN Pin = 26 - SCL_PIN Pin = 27 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = 47 - SPI0_SDO_PIN Pin = 45 - SPI0_SDI_PIN Pin = 46 -) - -// PowerSupplyActive enables the supply voltages for nRF52840 and peripherals (true) or only for nRF52840 (false) -// This controls the TPS610981 boost converter. You must turn the power supply active in order to use the EPD and -// other onboard peripherals. -func PowerSupplyActive(active bool) { - POWER_SUPPLY_PIN.Configure(PinConfig{Mode: PinOutput}) - if active { - POWER_SUPPLY_PIN.High() - } else { - POWER_SUPPLY_PIN.Low() - } -} - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "PHYTEC reelboard" - usb_STRING_MANUFACTURER = "PHYTEC" -) - -var ( - usb_VID uint16 = 0x2FE3 - usb_PID uint16 = 0x100 -) diff --git a/emb/machine/board_stm32f469disco.go b/emb/machine/board_stm32f469disco.go deleted file mode 100644 index 8fb5cde..0000000 --- a/emb/machine/board_stm32f469disco.go +++ /dev/null @@ -1,79 +0,0 @@ -//go:build stm32f469disco - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - LED = LED_BUILTIN - LED1 = LED_GREEN - LED2 = LED_ORANGE - LED3 = LED_RED - LED4 = LED_BLUE - LED_BUILTIN = LED_GREEN - LED_GREEN = PG6 - LED_ORANGE = PD4 - LED_RED = PD5 - LED_BLUE = PK3 -) - -const ( - BUTTON = PA0 -) - -// UART pins -const ( - UART_TX_PIN = PB10 - UART_RX_PIN = PB11 -) - -var ( - UART3 = &_UART3 - _UART3 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART3, - TxAltFuncSelector: AF7_USART1_2_3, - RxAltFuncSelector: AF7_USART1_2_3, - } - DefaultUART = UART3 -) - -// set up RX IRQ handler. Follow similar pattern for other UARTx instances -func init() { - UART3.Interrupt = interrupt.New(stm32.IRQ_USART3, _UART3.handleInterrupt) -} - -// SPI pins -const ( - SPI1_SCK_PIN = PA5 - SPI1_SDI_PIN = PA6 - SPI1_SDO_PIN = PA7 - SPI0_SCK_PIN = SPI1_SCK_PIN - SPI0_SDI_PIN = SPI1_SDI_PIN - SPI0_SDO_PIN = SPI1_SDO_PIN -) - -// Since the first interface is named SPI1, both SPI0 and SPI1 refer to SPI1. -// TODO: implement SPI2 and SPI3. -var ( - SPI0 = &SPI{ - Bus: stm32.SPI1, - AltFuncSelector: AF5_SPI1_SPI2, - } - SPI1 = SPI0 -) - -const ( - I2C0_SCL_PIN = PB6 - I2C0_SDA_PIN = PB9 -) - -var ( - I2C0 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: AF4_I2C1_2_3, - } -) diff --git a/emb/machine/board_stm32f4disco.go b/emb/machine/board_stm32f4disco.go deleted file mode 100644 index d048fca..0000000 --- a/emb/machine/board_stm32f4disco.go +++ /dev/null @@ -1,106 +0,0 @@ -//go:build stm32f4disco - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - LED1 = LED_GREEN - LED2 = LED_ORANGE - LED3 = LED_RED - LED4 = LED_BLUE - LED_GREEN = PD12 - LED_ORANGE = PD13 - LED_RED = PD14 - LED_BLUE = PD15 - LED = LED_BUILTIN - LED_BUILTIN = LED_GREEN -) - -const ( - BUTTON = PA0 -) - -// Analog Pins -const ( - ADC0 = PA0 - ADC1 = PA1 - ADC2 = PA2 - ADC3 = PA3 - ADC4 = PA4 - ADC5 = PA5 - ADC6 = PA6 - ADC7 = PA7 - ADC8 = PB0 - ADC9 = PB1 - ADC10 = PC0 - ADC11 = PC1 - ADC12 = PC2 - ADC13 = PC3 - ADC14 = PC4 - ADC15 = PC5 -) - -// UART pins -const ( - UART_TX_PIN = PA2 - UART_RX_PIN = PA3 -) - -var ( - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART2, - TxAltFuncSelector: AF7_USART1_2_3, - RxAltFuncSelector: AF7_USART1_2_3, - } - DefaultUART = UART1 -) - -// set up RX IRQ handler. Follow similar pattern for other UARTx instances -func init() { - UART1.Interrupt = interrupt.New(stm32.IRQ_USART2, _UART1.handleInterrupt) -} - -// SPI pins -const ( - SPI1_SCK_PIN = PA5 - SPI1_SDI_PIN = PA6 - SPI1_SDO_PIN = PA7 - SPI0_SCK_PIN = SPI1_SCK_PIN - SPI0_SDI_PIN = SPI1_SDI_PIN - SPI0_SDO_PIN = SPI1_SDO_PIN -) - -// MEMs accelerometer -const ( - MEMS_ACCEL_CS = PE3 - MEMS_ACCEL_INT1 = PE0 - MEMS_ACCEL_INT2 = PE1 -) - -// Since the first interface is named SPI1, both SPI0 and SPI1 refer to SPI1. -// TODO: implement SPI2 and SPI3. -var ( - SPI0 = &SPI{ - Bus: stm32.SPI1, - AltFuncSelector: AF5_SPI1_SPI2, - } - SPI1 = SPI0 -) - -const ( - I2C0_SCL_PIN = PB6 - I2C0_SDA_PIN = PB9 -) - -var ( - I2C0 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: AF4_I2C1_2_3, - } -) diff --git a/emb/machine/board_swan.go b/emb/machine/board_swan.go deleted file mode 100644 index 7502dd6..0000000 --- a/emb/machine/board_swan.go +++ /dev/null @@ -1,62 +0,0 @@ -//go:build swan - -package machine - -import ( - "device/stm32" - "runtime/interrupt" -) - -const ( - // LED on the SWAN - LED = PE2 - - // UART pins - // PA9 and PA10 are connected to the SWAN Tx/Rx - UART_TX_PIN = PA9 - UART_RX_PIN = PA10 - - // I2C pins - // PB6 is SCL - // PB7 is SDA - I2C0_SCL_PIN = PB6 - I2C0_SDA_PIN = PB7 - - // SPI pins - SPI1_SCK_PIN = PD1 - SPI1_SDI_PIN = PB14 - SPI1_SDO_PIN = PB15 - SPI0_SCK_PIN = SPI1_SCK_PIN - SPI0_SDI_PIN = SPI1_SDI_PIN - SPI0_SDO_PIN = SPI1_SDO_PIN -) - -var ( - // USART1 is connected to the TX/RX pins - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: stm32.USART1, - TxAltFuncSelector: 7, - RxAltFuncSelector: 7, - } - DefaultUART = UART1 - - // I2C1 is documented, alias to I2C0 as well - I2C1 = &I2C{ - Bus: stm32.I2C1, - AltFuncSelector: 4, - } - I2C0 = I2C1 - - // SPI1 is documented, alias to SPI0 as well - SPI1 = &SPI{ - Bus: stm32.SPI2, - AltFuncSelector: 5, - } - SPI0 = SPI1 -) - -func init() { - UART1.Interrupt = interrupt.New(stm32.IRQ_USART1, _UART1.handleInterrupt) -} diff --git a/emb/machine/board_teensy36.go b/emb/machine/board_teensy36.go deleted file mode 100644 index 4859154..0000000 --- a/emb/machine/board_teensy36.go +++ /dev/null @@ -1,103 +0,0 @@ -//go:build nxp && mk66f18 && teensy36 - -package machine - -// CPUFrequency returns the frequency of the ARM core clock (180MHz) -func CPUFrequency() uint32 { return 180000000 } - -// ClockFrequency returns the frequency of the external oscillator (16MHz) -func ClockFrequency() uint32 { return 16000000 } - -// digital IO -const ( - D00 = PB16 - D01 = PB17 - D02 = PD00 - D03 = PA12 - D04 = PA13 - D05 = PD07 - D06 = PD04 - D07 = PD02 - D08 = PD03 - D09 = PC03 - D10 = PC04 - D11 = PC06 - D12 = PC07 - D13 = PC05 - D14 = PD01 - D15 = PC00 - D16 = PB00 - D17 = PB01 - D18 = PB03 - D19 = PB02 - D20 = PD05 - D21 = PD06 - D22 = PC01 - D23 = PC02 - D24 = PE26 - D25 = PA05 - D26 = PA14 - D27 = PA15 - D28 = PA16 - D29 = PB18 - D30 = PB19 - D31 = PB10 - D32 = PB11 - D33 = PE24 - D34 = PE25 - D35 = PC08 - D36 = PC09 - D37 = PC10 - D38 = PC11 - D39 = PA17 - D40 = PA28 - D41 = PA29 - D42 = PA26 - D43 = PB20 - D44 = PB22 - D45 = PB23 - D46 = PB21 - D47 = PD08 - D48 = PD09 - D49 = PB04 - D50 = PB05 - D51 = PD14 - D52 = PD13 - D53 = PD12 - D54 = PD15 - D55 = PD11 - D56 = PE10 - D57 = PE11 - D58 = PE00 - D59 = PE01 - D60 = PE02 - D61 = PE03 - D62 = PE04 - D63 = PE05 -) - -// LED on the Teensy -const LED = PC05 - -var ( - TeensyUART1 = UART0 - TeensyUART2 = UART1 - TeensyUART3 = UART2 - TeensyUART4 = UART3 - TeensyUART5 = UART4 -) - -var DefaultUART = UART0 - -const ( - defaultUART0RX = D00 - defaultUART0TX = D01 - defaultUART1RX = D09 - defaultUART1TX = D10 - defaultUART2RX = D07 - defaultUART2TX = D08 - defaultUART3RX = D31 - defaultUART3TX = D32 - defaultUART4RX = D34 - defaultUART4TX = D33 -) diff --git a/emb/machine/board_teensy40.go b/emb/machine/board_teensy40.go deleted file mode 100644 index 22529a8..0000000 --- a/emb/machine/board_teensy40.go +++ /dev/null @@ -1,390 +0,0 @@ -//go:build teensy40 - -package machine - -import ( - "device/nxp" - "runtime/interrupt" -) - -// Digital pins -const ( - // = Pin // [Pad]: Alt Func 0 Alt Func 1 Alt Func 2 Alt Func 3 Alt Func 4 Alt Func 5 Alt Func 6 Alt Func 7 Alt Func 8 Alt Func 9 - // = ---- ----------- --------------- --------------- --------------- -------------- -------------------- ---------- -------------------- --------------------- --------------------- ---------------- - D0 = PA3 // [AD_B0_03]: FLEXCAN2_RX XBAR1_INOUT17 LPUART6_RX USB_OTG1_OC FLEXPWM1_PWMX01 GPIO1_IO03 REF_CLK_24M LPSPI3_PCS0 ~ ~ - D1 = PA2 // [AD_B0_02]: FLEXCAN2_TX XBAR1_INOUT16 LPUART6_TX USB_OTG1_PWR FLEXPWM1_PWMX00 GPIO1_IO02 LPI2C1_HREQ LPSPI3_SDI ~ ~ - D2 = PD4 // [EMC_04]: SEMC_DATA04 FLEXPWM4_PWMA02 SAI2_TX_DATA XBAR1_INOUT06 FLEXIO1_FLEXIO04 GPIO4_IO04 ~ ~ ~ ~ - D3 = PD5 // [EMC_05]: SEMC_DATA05 FLEXPWM4_PWMB02 SAI2_TX_SYNC XBAR1_INOUT07 FLEXIO1_FLEXIO05 GPIO4_IO05 ~ ~ ~ ~ - D4 = PD6 // [EMC_06]: SEMC_DATA06 FLEXPWM2_PWMA00 SAI2_TX_BCLK XBAR1_INOUT08 FLEXIO1_FLEXIO06 GPIO4_IO06 ~ ~ ~ ~ - D5 = PD8 // [EMC_08]: SEMC_DM00 FLEXPWM2_PWMA01 SAI2_RX_DATA XBAR1_INOUT17 FLEXIO1_FLEXIO08 GPIO4_IO08 ~ ~ ~ ~ - D6 = PB10 // [B0_10]: LCD_DATA06 QTIMER4_TIMER1 FLEXPWM2_PWMA02 SAI1_TX_DATA03 FLEXIO2_FLEXIO10 GPIO2_IO10 SRC_BOOT_CFG06 ENET2_CRS ~ ~ - D7 = PB17 // [B1_01]: LCD_DATA13 XBAR1_INOUT15 LPUART4_RX SAI1_TX_DATA00 FLEXIO2_FLEXIO17 GPIO2_IO17 FLEXPWM1_PWMB03 ENET2_RDATA00 FLEXIO3_FLEXIO17 ~ - D8 = PB16 // [B1_00]: LCD_DATA12 XBAR1_INOUT14 LPUART4_TX SAI1_RX_DATA00 FLEXIO2_FLEXIO16 GPIO2_IO16 FLEXPWM1_PWMA03 ENET2_RX_ER FLEXIO3_FLEXIO16 ~ - D9 = PB11 // [B0_11]: LCD_DATA07 QTIMER4_TIMER2 FLEXPWM2_PWMB02 SAI1_TX_DATA02 FLEXIO2_FLEXIO11 GPIO2_IO11 SRC_BOOT_CFG07 ENET2_COL ~ ~ - D10 = PB0 // [B0_00]: LCD_CLK QTIMER1_TIMER0 MQS_RIGHT LPSPI4_PCS0 FLEXIO2_FLEXIO00 GPIO2_IO00 SEMC_CSX01 ENET2_MDC ~ ~ - D11 = PB2 // [B0_02]: LCD_HSYNC QTIMER1_TIMER2 FLEXCAN1_TX LPSPI4_SDO FLEXIO2_FLEXIO02 GPIO2_IO02 SEMC_CSX03 ENET2_1588_EVENT0_OUT ~ ~ - D12 = PB1 // [B0_01]: LCD_ENABLE QTIMER1_TIMER1 MQS_LEFT LPSPI4_SDI FLEXIO2_FLEXIO01 GPIO2_IO01 SEMC_CSX02 ENET2_MDIO ~ ~ - D13 = PB3 // [B0_03]: LCD_VSYNC QTIMER2_TIMER0 FLEXCAN1_RX LPSPI4_SCK FLEXIO2_FLEXIO03 GPIO2_IO03 WDOG2_RESET_B_DEB ENET2_1588_EVENT0_IN ~ ~ - D14 = PA18 // [AD_B1_02]: USB_OTG1_ID QTIMER3_TIMER2 LPUART2_TX SPDIF_OUT ENET_1588_EVENT2_OUT GPIO1_IO18 USDHC1_CD_B KPP_ROW06 GPT2_CLK FLEXIO3_FLEXIO02 - D15 = PA19 // [AD_B1_03]: USB_OTG1_OC QTIMER3_TIMER3 LPUART2_RX SPDIF_IN ENET_1588_EVENT2_IN GPIO1_IO19 USDHC2_CD_B KPP_COL06 GPT2_CAPTURE1 FLEXIO3_FLEXIO03 - D16 = PA23 // [AD_B1_07]: FLEXSPIB_DATA00 LPI2C3_SCL LPUART3_RX SPDIF_EXT_CLK CSI_HSYNC GPIO1_IO23 USDHC2_DATA3 KPP_COL04 GPT2_COMPARE3 FLEXIO3_FLEXIO07 - D17 = PA22 // [AD_B1_06]: FLEXSPIB_DATA01 LPI2C3_SDA LPUART3_TX SPDIF_LOCK CSI_VSYNC GPIO1_IO22 USDHC2_DATA2 KPP_ROW04 GPT2_COMPARE2 FLEXIO3_FLEXIO06 - D18 = PA17 // [AD_B1_01]: USB_OTG1_PWR QTIMER3_TIMER1 LPUART2_RTS_B LPI2C1_SDA CCM_PMIC_READY GPIO1_IO17 USDHC1_VSELECT KPP_COL07 ENET2_1588_EVENT0_IN FLEXIO3_FLEXIO01 - D19 = PA16 // [AD_B1_00]: USB_OTG2_ID QTIMER3_TIMER0 LPUART2_CTS_B LPI2C1_SCL WDOG1_B GPIO1_IO16 USDHC1_WP KPP_ROW07 ENET2_1588_EVENT0_OUT FLEXIO3_FLEXIO00 - D20 = PA26 // [AD_B1_10]: FLEXSPIA_DATA03 WDOG1_B LPUART8_TX SAI1_RX_SYNC CSI_DATA07 GPIO1_IO26 USDHC2_WP KPP_ROW02 ENET2_1588_EVENT1_OUT FLEXIO3_FLEXIO10 - D21 = PA27 // [AD_B1_11]: FLEXSPIA_DATA02 EWM_OUT_B LPUART8_RX SAI1_RX_BCLK CSI_DATA06 GPIO1_IO27 USDHC2_RESET_B KPP_COL02 ENET2_1588_EVENT1_IN FLEXIO3_FLEXIO11 - D22 = PA24 // [AD_B1_08]: FLEXSPIA_SS1_B FLEXPWM4_PWMA00 FLEXCAN1_TX CCM_PMIC_READY CSI_DATA09 GPIO1_IO24 USDHC2_CMD KPP_ROW03 FLEXIO3_FLEXIO08 ~ - D23 = PA25 // [AD_B1_09]: FLEXSPIA_DQS FLEXPWM4_PWMA01 FLEXCAN1_RX SAI1_MCLK CSI_DATA08 GPIO1_IO25 USDHC2_CLK KPP_COL03 FLEXIO3_FLEXIO09 ~ - D24 = PA12 // [AD_B0_12]: LPI2C4_SCL CCM_PMIC_READY LPUART1_TX WDOG2_WDOG_B FLEXPWM1_PWMX02 GPIO1_IO12 ENET_1588_EVENT1_OUT NMI_GLUE_NMI ~ ~ - D25 = PA13 // [AD_B0_13]: LPI2C4_SDA GPT1_CLK LPUART1_RX EWM_OUT_B FLEXPWM1_PWMX03 GPIO1_IO13 ENET_1588_EVENT1_IN REF_CLK_24M ~ ~ - D26 = PA30 // [AD_B1_14]: FLEXSPIA_SCLK ACMP_OUT02 LPSPI3_SDO SAI1_TX_BCLK CSI_DATA03 GPIO1_IO30 USDHC2_DATA6 KPP_ROW00 ENET2_1588_EVENT3_OUT FLEXIO3_FLEXIO14 - D27 = PA31 // [AD_B1_15]: FLEXSPIA_SS0_B ACMP_OUT03 LPSPI3_SCK SAI1_TX_SYNC CSI_DATA02 GPIO1_IO31 USDHC2_DATA7 KPP_COL00 ENET2_1588_EVENT3_IN FLEXIO3_FLEXIO15 - D28 = PC18 // [EMC_32]: SEMC_DATA10 FLEXPWM3_PWMB01 LPUART7_RX CCM_PMIC_RDY CSI_DATA21 GPIO3_IO18 ENET2_TX_EN ~ ~ ~ - D29 = PD31 // [EMC_31]: SEMC_DATA09 FLEXPWM3_PWMA01 LPUART7_TX LPSPI1_PCS1 CSI_DATA22 GPIO4_IO31 ENET2_TDATA01 ~ ~ ~ - D30 = PC23 // [EMC_37]: SEMC_DATA15 XBAR1_IN23 GPT1_COMPARE3 SAI3_MCLK CSI_DATA16 GPIO3_IO23 USDHC2_WP ENET2_RX_EN FLEXCAN3_RX ~ - D31 = PC22 // [EMC_36]: SEMC_DATA14 XBAR1_IN22 GPT1_COMPARE2 SAI3_TX_DATA CSI_DATA17 GPIO3_IO22 USDHC1_WP ENET2_RDATA01 FLEXCAN3_TX ~ - D32 = PB12 // [B0_12]: LCD_DATA08 XBAR1_INOUT10 ARM_TRACE_CLK SAI1_TX_DATA01 FLEXIO2_FLEXIO12 GPIO2_IO12 SRC_BOOT_CFG08 ENET2_TDATA00 ~ ~ - D33 = PD7 // [EMC_07]: SEMC_DATA07 FLEXPWM2_PWMB00 SAI2_MCLK XBAR1_INOUT09 FLEXIO1_FLEXIO07 GPIO4_IO07 ~ ~ ~ ~ - D34 = PC15 // [SD_B0_03]: USDHC1_DATA1 FLEXPWM1_PWMB01 LPUART8_RTS_B XBAR1_INOUT07 LPSPI1_SDI GPIO3_IO15 ENET2_RDATA00 SEMC_CLK6 ~ ~ - D35 = PC14 // [SD_B0_02]: USDHC1_DATA0 FLEXPWM1_PWMA01 LPUART8_CTS_B XBAR1_INOUT06 LPSPI1_SDO GPIO3_IO14 ENET2_RX_ER SEMC_CLK5 ~ ~ - D36 = PC13 // [SD_B0_01]: USDHC1_CLK FLEXPWM1_PWMB00 LPI2C3_SDA XBAR1_INOUT05 LPSPI1_PCS0 GPIO3_IO13 FLEXSPIB_SS1_B ENET2_TX_CLK ENET2_REF_CLK2 ~ - D37 = PC12 // [SD_B0_00]: USDHC1_CMD FLEXPWM1_PWMA00 LPI2C3_SCL XBAR1_INOUT04 LPSPI1_SCK GPIO3_IO12 FLEXSPIA_SS1_B ENET2_TX_EN SEMC_DQS4 ~ - D38 = PC17 // [SD_B0_05]: USDHC1_DATA3 FLEXPWM1_PWMB02 LPUART8_RX XBAR1_INOUT09 FLEXSPIB_DQS GPIO3_IO17 CCM_CLKO2 ENET2_RX_EN ~ ~ - D39 = PC16 // [SD_B0_04]: USDHC1_DATA2 FLEXPWM1_PWMA02 LPUART8_TX XBAR1_INOUT08 FLEXSPIB_SS0_B GPIO3_IO16 CCM_CLKO1 ENET2_RDATA01 ~ ~ -) - -// Analog pins -const ( - // = Pin // Dig | [Pad] {ADC1/ADC2} - A0 = PA18 // D14 | [AD_B1_02] { 7 / 7 } - A1 = PA19 // D15 | [AD_B1_03] { 8 / 8 } - A2 = PA23 // D16 | [AD_B1_07] { 12 / 12 } - A3 = PA22 // D17 | [AD_B1_06] { 11 / 11 } - A4 = PA17 // D18 | [AD_B1_01] { 6 / 6 } - A5 = PA16 // D19 | [AD_B1_00] { 5 / 5 } - A6 = PA26 // D20 | [AD_B1_10] { 15 / 15 } - A7 = PA27 // D21 | [AD_B1_11] { 0 / 0 } - A8 = PA24 // D22 | [AD_B1_08] { 13 / 13 } - A9 = PA25 // D23 | [AD_B1_09] { 14 / 14 } - A10 = PA12 // D24 | [AD_B0_12] { 1 / - } - A11 = PA13 // D25 | [AD_B0_13] { 2 / - } - A12 = PA30 // D26 | [AD_B1_14] { - / 3 } - A13 = PA31 // D27 | [AD_B1_15] { - / 4 } -) - -// Default peripheral pins -const ( - LED = D13 - - UART_RX_PIN = UART1_RX_PIN // D0 - UART_TX_PIN = UART1_TX_PIN // D1 - - SPI_SDI_PIN = SPI1_SDI_PIN // D12 - SPI_SDO_PIN = SPI1_SDO_PIN // D11 - SPI_SCK_PIN = SPI1_SCK_PIN // D13 - SPI_CS_PIN = SPI1_CS_PIN // D10 - - I2C_SDA_PIN = I2C1_SDA_PIN // D18/A4 - I2C_SCL_PIN = I2C1_SCL_PIN // D19/A5 -) - -// Default peripherals -var ( - DefaultUART = UART1 -) - -func init() { - // register any interrupt handlers for this board's peripherals - _UART1.Interrupt = interrupt.New(nxp.IRQ_LPUART6, _UART1.handleInterrupt) - _UART2.Interrupt = interrupt.New(nxp.IRQ_LPUART4, _UART2.handleInterrupt) - _UART3.Interrupt = interrupt.New(nxp.IRQ_LPUART2, _UART3.handleInterrupt) - _UART4.Interrupt = interrupt.New(nxp.IRQ_LPUART3, _UART4.handleInterrupt) - _UART5.Interrupt = interrupt.New(nxp.IRQ_LPUART8, _UART5.handleInterrupt) - _UART6.Interrupt = interrupt.New(nxp.IRQ_LPUART1, _UART6.handleInterrupt) - _UART7.Interrupt = interrupt.New(nxp.IRQ_LPUART7, _UART7.handleInterrupt) -} - -// #=====================================================# -// | UART | -// #===========#===========#=============#===============# -// | Interface | Hardware | Clock(Freq) | RX/TX : Alt | -// #===========#===========#=============#=========-=====# -// | UART1 | LPUART6 | OSC(24 MHz) | D0/D1 : 2/2 | -// | UART2 | LPUART4 | OSC(24 MHz) | D7/D8 : 2/2 | -// | UART3 | LPUART2 | OSC(24 MHz) | D15/D14 : 2/2 | -// | UART4 | LPUART3 | OSC(24 MHz) | D16/D17 : 2/2 | -// | UART5 | LPUART8 | OSC(24 MHz) | D21/D20 : 2/2 | -// | UART6 | LPUART1 | OSC(24 MHz) | D25/D24 : 2/2 | -// | UART7 | LPUART7 | OSC(24 MHz) | D28/D29 : 2/2 | -// #===========#===========#=============#=========-=====# -const ( - UART1_RX_PIN = D0 - UART1_TX_PIN = D1 - - UART2_RX_PIN = D7 - UART2_TX_PIN = D8 - - UART3_RX_PIN = D15 - UART3_TX_PIN = D14 - - UART4_RX_PIN = D16 - UART4_TX_PIN = D17 - - UART5_RX_PIN = D21 - UART5_TX_PIN = D20 - - UART6_RX_PIN = D25 - UART6_TX_PIN = D24 - - UART7_RX_PIN = D28 - UART7_TX_PIN = D29 -) - -var ( - UART1 = &_UART1 - _UART1 = UART{ - Bus: nxp.LPUART6, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D0 (PA3 [AD_B0_03]) - mux: nxp.IOMUXC_LPUART6_RX_SELECT_INPUT_DAISY_GPIO_AD_B0_03_ALT2, - sel: &nxp.IOMUXC.LPUART6_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D1 (PA2 [AD_B0_02]) - mux: nxp.IOMUXC_LPUART6_TX_SELECT_INPUT_DAISY_GPIO_AD_B0_02_ALT2, - sel: &nxp.IOMUXC.LPUART6_TX_SELECT_INPUT, - }, - } - UART2 = &_UART2 - _UART2 = UART{ - Bus: nxp.LPUART4, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D7 (PB17 [B1_01]) - mux: nxp.IOMUXC_LPUART4_RX_SELECT_INPUT_DAISY_GPIO_B1_01_ALT2, - sel: &nxp.IOMUXC.LPUART4_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D8 (PB16 [B1_00]) - mux: nxp.IOMUXC_LPUART4_TX_SELECT_INPUT_DAISY_GPIO_B1_00_ALT2, - sel: &nxp.IOMUXC.LPUART4_TX_SELECT_INPUT, - }, - } - UART3 = &_UART3 - _UART3 = UART{ - Bus: nxp.LPUART2, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D15 (PA19 [AD_B1_03]) - mux: nxp.IOMUXC_LPUART2_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_03_ALT2, - sel: &nxp.IOMUXC.LPUART2_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D14 (PA18 [AD_B1_02]) - mux: nxp.IOMUXC_LPUART2_TX_SELECT_INPUT_DAISY_GPIO_AD_B1_02_ALT2, - sel: &nxp.IOMUXC.LPUART2_TX_SELECT_INPUT, - }, - } - UART4 = &_UART4 - _UART4 = UART{ - Bus: nxp.LPUART3, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D16 (PA23 [AD_B1_07]) - mux: nxp.IOMUXC_LPUART3_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_07_ALT2, - sel: &nxp.IOMUXC.LPUART3_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D17 (PA22 [AD_B1_06]) - mux: nxp.IOMUXC_LPUART3_TX_SELECT_INPUT_DAISY_GPIO_AD_B1_06_ALT2, - sel: &nxp.IOMUXC.LPUART3_TX_SELECT_INPUT, - }, - } - UART5 = &_UART5 - _UART5 = UART{ - Bus: nxp.LPUART8, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D21 (PA27 [AD_B1_11]) - mux: nxp.IOMUXC_LPUART8_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_11_ALT2, - sel: &nxp.IOMUXC.LPUART8_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D20 (PA26 [AD_B1_10]) - mux: nxp.IOMUXC_LPUART8_TX_SELECT_INPUT_DAISY_GPIO_AD_B1_10_ALT2, - sel: &nxp.IOMUXC.LPUART8_TX_SELECT_INPUT, - }, - } - UART6 = &_UART6 - _UART6 = UART{ - Bus: nxp.LPUART1, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - // LPUART1 not connected via IOMUXC - // RX: D24 (PA12 [AD_B0_12]) - // TX: D25 (PA13 [AD_B0_13]) - } - UART7 = &_UART7 - _UART7 = UART{ - Bus: nxp.LPUART7, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D28 (PC18 [EMC_32]) - mux: nxp.IOMUXC_LPUART7_RX_SELECT_INPUT_DAISY_GPIO_EMC_32_ALT2, - sel: &nxp.IOMUXC.LPUART7_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D29 (PD31 [EMC_31]) - mux: nxp.IOMUXC_LPUART7_TX_SELECT_INPUT_DAISY_GPIO_EMC_31_ALT2, - sel: &nxp.IOMUXC.LPUART7_TX_SELECT_INPUT, - }, - } -) - -// #==================================================================# -// | SPI | -// #===========#==========#===============#===========================# -// | Interface | Hardware | Clock(Freq) | SDI/SDO/SCK/CS : Alt | -// #===========#==========#===============#=================-=========# -// | SPI1 | LPSPI4 | PLL2(132 MHz) | D12/D11/D13/D10 : 3/3/3/3 | -// | SPI2 | LPSPI3 | PLL2(132 MHz) | D1/D26/D27/D0 : 7/2/2/7 | -// | SPI3 | LPSPI1 | PLL2(132 MHz) | D34/D35/D37/D36 : 4/4/4/4 | -// #===========#==========#===============#=================-=========# -const ( - SPI1_SDI_PIN = D12 - SPI1_SDO_PIN = D11 - SPI1_SCK_PIN = D13 - SPI1_CS_PIN = D10 - - SPI2_SDI_PIN = D1 - SPI2_SDO_PIN = D26 - SPI2_SCK_PIN = D27 - SPI2_CS_PIN = D0 - - SPI3_SDI_PIN = D34 - SPI3_SDO_PIN = D35 - SPI3_SCK_PIN = D37 - SPI3_CS_PIN = D36 -) - -var ( - SPI0 = SPI1 // SPI0 is an alias of SPI1 (LPSPI4) - SPI1 = &SPI{ - Bus: nxp.LPSPI4, - muxSDI: muxSelect{ // D12 (PB1 [B0_01]) - mux: nxp.IOMUXC_LPSPI4_SDI_SELECT_INPUT_DAISY_GPIO_B0_01_ALT3, - sel: &nxp.IOMUXC.LPSPI4_SDI_SELECT_INPUT, - }, - muxSDO: muxSelect{ // D11 (PB2 [B0_02]) - mux: nxp.IOMUXC_LPSPI4_SDO_SELECT_INPUT_DAISY_GPIO_B0_02_ALT3, - sel: &nxp.IOMUXC.LPSPI4_SDO_SELECT_INPUT, - }, - muxSCK: muxSelect{ // D13 (PB3 [B0_03]) - mux: nxp.IOMUXC_LPSPI4_SCK_SELECT_INPUT_DAISY_GPIO_B0_03_ALT3, - sel: &nxp.IOMUXC.LPSPI4_SCK_SELECT_INPUT, - }, - muxCS: muxSelect{ // D10 (PB0 [B0_00]) - mux: nxp.IOMUXC_LPSPI4_PCS0_SELECT_INPUT_DAISY_GPIO_B0_00_ALT3, - sel: &nxp.IOMUXC.LPSPI4_PCS0_SELECT_INPUT, - }, - } - SPI2 = &SPI{ - Bus: nxp.LPSPI3, - muxSDI: muxSelect{ // D1 (PA2 [AD_B0_02]) - mux: nxp.IOMUXC_LPSPI3_SDI_SELECT_INPUT_DAISY_GPIO_AD_B0_02_ALT7, - sel: &nxp.IOMUXC.LPSPI3_SDI_SELECT_INPUT, - }, - muxSDO: muxSelect{ // D26 (PA30 [AD_B1_14]) - mux: nxp.IOMUXC_LPSPI3_SDO_SELECT_INPUT_DAISY_GPIO_AD_B1_14_ALT2, - sel: &nxp.IOMUXC.LPSPI3_SDO_SELECT_INPUT, - }, - muxSCK: muxSelect{ // D27 (PA31 [AD_B1_15]) - mux: nxp.IOMUXC_LPSPI3_SCK_SELECT_INPUT_DAISY_GPIO_AD_B1_15, - sel: &nxp.IOMUXC.LPSPI3_SCK_SELECT_INPUT, - }, - muxCS: muxSelect{ // D0 (PA3 [AD_B0_03]) - mux: nxp.IOMUXC_LPSPI3_PCS0_SELECT_INPUT_DAISY_GPIO_AD_B0_03_ALT7, - sel: &nxp.IOMUXC.LPSPI3_PCS0_SELECT_INPUT, - }, - } - SPI3 = &SPI{ - Bus: nxp.LPSPI1, - muxSDI: muxSelect{ // D34 (PC15 [SD_B0_03]) - mux: nxp.IOMUXC_LPSPI1_SDI_SELECT_INPUT_DAISY_GPIO_SD_B0_03_ALT4, - sel: &nxp.IOMUXC.LPSPI1_SDI_SELECT_INPUT, - }, - muxSDO: muxSelect{ // D35 (PC14 [SD_B0_02]) - mux: nxp.IOMUXC_LPSPI1_SDO_SELECT_INPUT_DAISY_GPIO_SD_B0_02_ALT4, - sel: &nxp.IOMUXC.LPSPI1_SDO_SELECT_INPUT, - }, - muxSCK: muxSelect{ // D37 (PC12 [SD_B0_00]) - mux: nxp.IOMUXC_LPSPI1_SCK_SELECT_INPUT_DAISY_GPIO_SD_B0_00_ALT4, - sel: &nxp.IOMUXC.LPSPI1_SCK_SELECT_INPUT, - }, - muxCS: muxSelect{ // D36 (PC13 [SD_B0_01]) - mux: nxp.IOMUXC_LPSPI1_PCS0_SELECT_INPUT_DAISY_GPIO_SD_B0_01_ALT4, - sel: &nxp.IOMUXC.LPSPI1_PCS0_SELECT_INPUT, - }, - } -) - -// #====================================================# -// | I2C | -// #===========#==========#=============#===============# -// | Interface | Hardware | Clock(Freq) | SDA/SCL : Alt | -// #===========#==========#=============#=========-=====# -// | I2C1 | LPI2C1 | OSC(24 MHz) | D18/D19 : 3/3 | -// | I2C2 | LPI2C3 | OSC(24 MHz) | D17/D16 : 1/1 | -// | I2C3 | LPI2C4 | OSC(24 MHz) | D25/D24 : 0/0 | -// #===========#==========#=============#=========-=====# -const ( - I2C1_SDA_PIN = D18 - I2C1_SCL_PIN = D19 - - I2C2_SDA_PIN = D17 - I2C2_SCL_PIN = D16 - - I2C3_SDA_PIN = D25 - I2C3_SCL_PIN = D24 -) - -var ( - I2C0 = I2C1 // I2C0 is an alias for I2C1 (LPI2C1) - I2C1 = &_I2C1 - _I2C1 = I2C{ - Bus: nxp.LPI2C1, - sda: I2C1_SDA_PIN, // D18 (PA17 [AD_B1_01]) - scl: I2C1_SCL_PIN, // D19 (PA16 [AD_B1_00]) - muxSDA: muxSelect{ - mux: nxp.IOMUXC_LPI2C1_SDA_SELECT_INPUT_DAISY_GPIO_AD_B1_01_ALT3, - sel: &nxp.IOMUXC.LPI2C1_SDA_SELECT_INPUT, - }, - muxSCL: muxSelect{ - mux: nxp.IOMUXC_LPI2C1_SCL_SELECT_INPUT_DAISY_GPIO_AD_B1_00_ALT3, - sel: &nxp.IOMUXC.LPI2C1_SCL_SELECT_INPUT, - }, - } - I2C2 = &_I2C2 - _I2C2 = I2C{ - Bus: nxp.LPI2C3, - sda: I2C2_SDA_PIN, // D17 (PA22 [AD_B1_06]) - scl: I2C2_SCL_PIN, // D16 (PA23 [AD_B1_07]) - muxSDA: muxSelect{ - mux: nxp.IOMUXC_LPI2C3_SDA_SELECT_INPUT_DAISY_GPIO_AD_B1_06_ALT1, - sel: &nxp.IOMUXC.LPI2C3_SDA_SELECT_INPUT, - }, - muxSCL: muxSelect{ - mux: nxp.IOMUXC_LPI2C3_SCL_SELECT_INPUT_DAISY_GPIO_AD_B1_07_ALT1, - sel: &nxp.IOMUXC.LPI2C3_SCL_SELECT_INPUT, - }, - } - I2C3 = &_I2C3 - _I2C3 = I2C{ - Bus: nxp.LPI2C4, - sda: I2C3_SDA_PIN, // D25 (PA13 [AD_B0_13]) - scl: I2C3_SCL_PIN, // D24 (PA12 [AD_B0_12]) - muxSDA: muxSelect{ - mux: nxp.IOMUXC_LPI2C4_SDA_SELECT_INPUT_DAISY_GPIO_AD_B0_13_ALT0, - sel: &nxp.IOMUXC.LPI2C4_SDA_SELECT_INPUT, - }, - muxSCL: muxSelect{ - mux: nxp.IOMUXC_LPI2C4_SCL_SELECT_INPUT_DAISY_GPIO_AD_B0_12_ALT0, - sel: &nxp.IOMUXC.LPI2C4_SCL_SELECT_INPUT, - }, - } -) diff --git a/emb/machine/board_teensy41.go b/emb/machine/board_teensy41.go deleted file mode 100644 index 436c1b9..0000000 --- a/emb/machine/board_teensy41.go +++ /dev/null @@ -1,319 +0,0 @@ -//go:build teensy41 - -package machine - -import ( - "device/nxp" - "runtime/interrupt" -) - -// Digital pins -const ( - // = Pin // [Pad]: Alt Func 0 Alt Func 1 Alt Func 2 Alt Func 3 Alt Func 4 Alt Func 5 Alt Func 6 Alt Func 7 Alt Func 8 Alt Func 9 - // = ---- ----------- --------------- --------------- --------------- -------------- -------------------- ---------- -------------------- --------------------- --------------------- ---------------- - D0 = PA3 // [AD_B0_03]: FLEXCAN2_RX XBAR1_INOUT17 LPUART6_RX USB_OTG1_OC FLEXPWM1_PWMX01 GPIO1_IO03 REF_CLK_24M LPSPI3_PCS0 ~ ~ - D1 = PA2 // [AD_B0_02]: FLEXCAN2_TX XBAR1_INOUT16 LPUART6_TX USB_OTG1_PWR FLEXPWM1_PWMX00 GPIO1_IO02 LPI2C1_HREQ LPSPI3_SDI ~ ~ - D2 = PD4 // [EMC_04]: SEMC_DATA04 FLEXPWM4_PWMA02 SAI2_TX_DATA XBAR1_INOUT06 FLEXIO1_FLEXIO04 GPIO4_IO04 ~ ~ ~ ~ - D3 = PD5 // [EMC_05]: SEMC_DATA05 FLEXPWM4_PWMB02 SAI2_TX_SYNC XBAR1_INOUT07 FLEXIO1_FLEXIO05 GPIO4_IO05 ~ ~ ~ ~ - D4 = PD6 // [EMC_06]: SEMC_DATA06 FLEXPWM2_PWMA00 SAI2_TX_BCLK XBAR1_INOUT08 FLEXIO1_FLEXIO06 GPIO4_IO06 ~ ~ ~ ~ - D5 = PD8 // [EMC_08]: SEMC_DM00 FLEXPWM2_PWMA01 SAI2_RX_DATA XBAR1_INOUT17 FLEXIO1_FLEXIO08 GPIO4_IO08 ~ ~ ~ ~ - D6 = PB10 // [B0_10]: LCD_DATA06 QTIMER4_TIMER1 FLEXPWM2_PWMA02 SAI1_TX_DATA03 FLEXIO2_FLEXIO10 GPIO2_IO10 SRC_BOOT_CFG06 ENET2_CRS ~ ~ - D7 = PB17 // [B1_01]: LCD_DATA13 XBAR1_INOUT15 LPUART4_RX SAI1_TX_DATA00 FLEXIO2_FLEXIO17 GPIO2_IO17 FLEXPWM1_PWMB03 ENET2_RDATA00 FLEXIO3_FLEXIO17 ~ - D8 = PB16 // [B1_00]: LCD_DATA12 XBAR1_INOUT14 LPUART4_TX SAI1_RX_DATA00 FLEXIO2_FLEXIO16 GPIO2_IO16 FLEXPWM1_PWMA03 ENET2_RX_ER FLEXIO3_FLEXIO16 ~ - D9 = PB11 // [B0_11]: LCD_DATA07 QTIMER4_TIMER2 FLEXPWM2_PWMB02 SAI1_TX_DATA02 FLEXIO2_FLEXIO11 GPIO2_IO11 SRC_BOOT_CFG07 ENET2_COL ~ ~ - D10 = PB0 // [B0_00]: LCD_CLK QTIMER1_TIMER0 MQS_RIGHT LPSPI4_PCS0 FLEXIO2_FLEXIO00 GPIO2_IO00 SEMC_CSX01 ENET2_MDC ~ ~ - D11 = PB2 // [B0_02]: LCD_HSYNC QTIMER1_TIMER2 FLEXCAN1_TX LPSPI4_SDO FLEXIO2_FLEXIO02 GPIO2_IO02 SEMC_CSX03 ENET2_1588_EVENT0_OUT ~ ~ - D12 = PB1 // [B0_01]: LCD_ENABLE QTIMER1_TIMER1 MQS_LEFT LPSPI4_SDI FLEXIO2_FLEXIO01 GPIO2_IO01 SEMC_CSX02 ENET2_MDIO ~ ~ - D13 = PB3 // [B0_03]: LCD_VSYNC QTIMER2_TIMER0 FLEXCAN1_RX LPSPI4_SCK FLEXIO2_FLEXIO03 GPIO2_IO03 WDOG2_RESET_B_DEB ENET2_1588_EVENT0_IN ~ ~ - D14 = PA18 // [AD_B1_02]: USB_OTG1_ID QTIMER3_TIMER2 LPUART2_TX SPDIF_OUT ENET_1588_EVENT2_OUT GPIO1_IO18 USDHC1_CD_B KPP_ROW06 GPT2_CLK FLEXIO3_FLEXIO02 - D15 = PA19 // [AD_B1_03]: USB_OTG1_OC QTIMER3_TIMER3 LPUART2_RX SPDIF_IN ENET_1588_EVENT2_IN GPIO1_IO19 USDHC2_CD_B KPP_COL06 GPT2_CAPTURE1 FLEXIO3_FLEXIO03 - D16 = PA23 // [AD_B1_07]: FLEXSPIB_DATA00 LPI2C3_SCL LPUART3_RX SPDIF_EXT_CLK CSI_HSYNC GPIO1_IO23 USDHC2_DATA3 KPP_COL04 GPT2_COMPARE3 FLEXIO3_FLEXIO07 - D17 = PA22 // [AD_B1_06]: FLEXSPIB_DATA01 LPI2C3_SDA LPUART3_TX SPDIF_LOCK CSI_VSYNC GPIO1_IO22 USDHC2_DATA2 KPP_ROW04 GPT2_COMPARE2 FLEXIO3_FLEXIO06 - D18 = PA17 // [AD_B1_01]: USB_OTG1_PWR QTIMER3_TIMER1 LPUART2_RTS_B LPI2C1_SDA CCM_PMIC_READY GPIO1_IO17 USDHC1_VSELECT KPP_COL07 ENET2_1588_EVENT0_IN FLEXIO3_FLEXIO01 - D19 = PA16 // [AD_B1_00]: USB_OTG2_ID QTIMER3_TIMER0 LPUART2_CTS_B LPI2C1_SCL WDOG1_B GPIO1_IO16 USDHC1_WP KPP_ROW07 ENET2_1588_EVENT0_OUT FLEXIO3_FLEXIO00 - D20 = PA26 // [AD_B1_10]: FLEXSPIA_DATA03 WDOG1_B LPUART8_TX SAI1_RX_SYNC CSI_DATA07 GPIO1_IO26 USDHC2_WP KPP_ROW02 ENET2_1588_EVENT1_OUT FLEXIO3_FLEXIO10 - D21 = PA27 // [AD_B1_11]: FLEXSPIA_DATA02 EWM_OUT_B LPUART8_RX SAI1_RX_BCLK CSI_DATA06 GPIO1_IO27 USDHC2_RESET_B KPP_COL02 ENET2_1588_EVENT1_IN FLEXIO3_FLEXIO11 - D22 = PA24 // [AD_B1_08]: FLEXSPIA_SS1_B FLEXPWM4_PWMA00 FLEXCAN1_TX CCM_PMIC_READY CSI_DATA09 GPIO1_IO24 USDHC2_CMD KPP_ROW03 FLEXIO3_FLEXIO08 ~ - D23 = PA25 // [AD_B1_09]: FLEXSPIA_DQS FLEXPWM4_PWMA01 FLEXCAN1_RX SAI1_MCLK CSI_DATA08 GPIO1_IO25 USDHC2_CLK KPP_COL03 FLEXIO3_FLEXIO09 ~ - D24 = PA12 // [AD_B0_12]: LPI2C4_SCL CCM_PMIC_READY LPUART1_TX WDOG2_WDOG_B FLEXPWM1_PWMX02 GPIO1_IO12 ENET_1588_EVENT1_OUT NMI_GLUE_NMI ~ ~ - D25 = PA13 // [AD_B0_13]: LPI2C4_SDA GPT1_CLK LPUART1_RX EWM_OUT_B FLEXPWM1_PWMX03 GPIO1_IO13 ENET_1588_EVENT1_IN REF_CLK_24M ~ ~ - D26 = PA30 // [AD_B1_14]: FLEXSPIA_SCLK ACMP_OUT02 LPSPI3_SDO SAI1_TX_BCLK CSI_DATA03 GPIO1_IO30 USDHC2_DATA6 KPP_ROW00 ENET2_1588_EVENT3_OUT FLEXIO3_FLEXIO14 - D27 = PA31 // [AD_B1_15]: FLEXSPIA_SS0_B ACMP_OUT03 LPSPI3_SCK SAI1_TX_SYNC CSI_DATA02 GPIO1_IO31 USDHC2_DATA7 KPP_COL00 ENET2_1588_EVENT3_IN FLEXIO3_FLEXIO15 - D28 = PC18 // [EMC_32]: SEMC_DATA10 FLEXPWM3_PWMB01 LPUART7_RX CCM_PMIC_RDY CSI_DATA21 GPIO3_IO18 ENET2_TX_EN ~ ~ ~ - D29 = PD31 // [EMC_31]: SEMC_DATA09 FLEXPWM3_PWMA01 LPUART7_TX LPSPI1_PCS1 CSI_DATA22 GPIO4_IO31 ENET2_TDATA01 ~ ~ ~ - D30 = PC23 // [EMC_37]: SEMC_DATA15 XBAR1_IN23 GPT1_COMPARE3 SAI3_MCLK CSI_DATA16 GPIO3_IO23 USDHC2_WP ENET2_RX_EN FLEXCAN3_RX ~ - D31 = PC22 // [EMC_36]: SEMC_DATA14 XBAR1_IN22 GPT1_COMPARE2 SAI3_TX_DATA CSI_DATA17 GPIO3_IO22 USDHC1_WP ENET2_RDATA01 FLEXCAN3_TX ~ - D32 = PB12 // [B0_12]: LCD_DATA08 XBAR1_INOUT10 ARM_TRACE_CLK SAI1_TX_DATA01 FLEXIO2_FLEXIO12 GPIO2_IO12 SRC_BOOT_CFG08 ENET2_TDATA00 ~ ~ - D33 = PD7 // [EMC_07]: SEMC_DATA07 FLEXPWM2_PWMB00 SAI2_MCLK XBAR1_INOUT09 FLEXIO1_FLEXIO07 GPIO4_IO07 ~ ~ ~ ~ - D34 = PB29 // [B1_13]: WDOG1_B LPUART5_RX CSI_VSYNC ENET_1588_EVENT0_OUT FLEXIO2_FLEXIO29 GPIO2_IO29 USDHC1_WP SEMC_DQS4 FLEXIO3_FLEXIO29 ~ - D35 = PB28 // [B1_12]: LPUART5_TX CSI_PIXCLK ENET_1588_EVENT0_IN FLEXIO2_FLEXIO28 GPIO2_IO28 USDHC1_CD_B FLEXIO3_FLEXIO28 ~ ~ ~ - D36 = PB18 // [B1_02]: LCD_DATA14 XBAR1_INOUT16 LPSPI4_PCS2 SAI1_TX_BCLK FLEXIO2_FLEXIO18 GPIO2_IO18 FLEXPWM2_PWMA03 ENET2_RDATA01 FLEXIO3_FLEXIO18 ~ - D37 = PB19 // [B1_03]: LCD_DATA15 XBAR1_INOUT17 LPSPI4_PCS1 SAI1_TX_SYNC FLEXIO2_FLEXIO19 GPIO2_IO19 FLEXPWM2_PWMB03 ENET2_RX_EN FLEXIO3_FLEXIO19 ~ - D38 = PA28 // [AD_B1_12]: FLEXSPIA_DATA01 ACMP_OUT00 LPSPI3_PCS0 SAI1_RX_DATA00 CSI_DATA05 GPIO1_IO28 USDHC2_DATA4 KPP_ROW01 ENET2_1588_EVENT2_OUT FLEXIO3_FLEXIO12 - D39 = PA29 // [AD_B1_13]: FLEXSPIA_DATA00 ACMP_OUT01 LPSPI3_SDI SAI1_TX_DATA00 CSI_DATA04 GPIO1_IO29 USDHC2_DATA5 KPP_COL01 ENET2_1588_EVENT2_IN FLEXIO3_FLEXIO13 - D40 = PA20 // [AD_B1_04]: FLEXSPIB_DATA03 ENET_MDC LPUART3_CTS_B SPDIF_SR_CLK CSI_PIXCLK GPIO1_IO20 USDHC2_DATA0 KPP_ROW05 GPT2_CAPTURE2 FLEXIO3_FLEXIO04 - D41 = PA21 // [AD_B1_05]: FLEXSPIB_DATA02 ENET_MDIO LPUART3_RTS_B SPDIF_OUT CSI_MCLK GPIO1_IO21 USDHC2_DATA1 KPP_COL05 GPT2_COMPARE1 FLEXIO3_FLEXIO05 - D42 = PC15 // [SD_B0_03]: USDHC1_DATA1 FLEXPWM1_PWMB01 LPUART8_RTS_B XBAR1_INOUT07 LPSPI1_SDI GPIO3_IO15 ENET2_RDATA00 SEMC_CLK6 ~ ~ - D43 = PC14 // [SD_B0_02]: USDHC1_DATA0 FLEXPWM1_PWMA01 LPUART8_CTS_B XBAR1_INOUT06 LPSPI1_SDO GPIO3_IO14 ENET2_RX_ER SEMC_CLK5 ~ ~ - D44 = PC13 // [SD_B0_01]: USDHC1_CLK FLEXPWM1_PWMB00 LPI2C3_SDA XBAR1_INOUT05 LPSPI1_PCS0 GPIO3_IO13 FLEXSPIB_SS1_B ENET2_TX_CLK ENET2_REF_CLK2 ~ - D45 = PC12 // [SD_B0_00]: USDHC1_CMD FLEXPWM1_PWMA00 LPI2C3_SCL XBAR1_INOUT04 LPSPI1_SCK GPIO3_IO12 FLEXSPIA_SS1_B ENET2_TX_EN SEMC_DQS4 ~ - D46 = PC17 // [SD_B0_05]: USDHC1_DATA3 FLEXPWM1_PWMB02 LPUART8_RX XBAR1_INOUT09 FLEXSPIB_DQS GPIO3_IO17 CCM_CLKO2 ENET2_RX_EN ~ ~ - D47 = PC16 // [SD_B0_04]: USDHC1_DATA2 FLEXPWM1_PWMA02 LPUART8_TX XBAR1_INOUT08 FLEXSPIB_SS0_B GPIO3_IO16 CCM_CLKO1 ENET2_RDATA01 ~ ~ - D48 = PD24 // [EMC_24]: SEMC_CAS FLEXPWM1_PWMB00 LPUART5_RX ENET_TX_EN GPT1_CAPTURE1 GPIO4_IO24 FLEXSPI2_A_SS0_B ~ ~ ~ - D49 = PD27 // [EMC_27]: SEMC_CKE FLEXPWM1_PWMA02 LPUART5_RTS_B LPSPI1_SCK FLEXIO1_FLEXIO13 GPIO4_IO27 FLEXSPI2_A_DATA01 ~ ~ ~ - D50 = PD28 // [EMC_28]: SEMC_WE FLEXPWM1_PWMB02 LPUART5_CTS_B LPSPI1_SDO FLEXIO1_FLEXIO14 GPIO4_IO28 FLEXSPI2_A_DATA02 ~ ~ ~ - D51 = PD22 // [EMC_22]: SEMC_BA1 FLEXPWM3_PWMB03 LPI2C3_SCL ENET_TDATA00 QTIMER2_TIMER3 GPIO4_IO22 FLEXSPI2_A_SS1_B ~ ~ ~ - D52 = PD26 // [EMC_26]: SEMC_CLK FLEXPWM1_PWMB01 LPUART6_RX ENET_RX_ER FLEXIO1_FLEXIO12 GPIO4_IO26 FLEXSPI2_A_DATA00 ~ ~ ~ - D53 = PD25 // [EMC_25]: SEMC_RAS FLEXPWM1_PWMA01 LPUART6_TX ENET_TX_CLK ENET_REF_CLK GPIO4_IO25 FLEXSPI2_A_SCLK ~ ~ ~ - D54 = PD29 // [EMC_29]: SEMC_CS0 FLEXPWM3_PWMA00 LPUART6_RTS_B LPSPI1_SDI FLEXIO1_FLEXIO15 GPIO4_IO29 FLEXSPI2_A_DATA03 ~ ~ ~ -) - -// Analog pins -const ( - // = Pin // Dig | [Pad] {ADC1/ADC2} - A0 = PA18 // D14 | [AD_B1_02] { 7 / 7 } - A1 = PA19 // D15 | [AD_B1_03] { 8 / 8 } - A2 = PA23 // D16 | [AD_B1_07] { 12 / 12 } - A3 = PA22 // D17 | [AD_B1_06] { 11 / 11 } - A4 = PA17 // D18 | [AD_B1_01] { 6 / 6 } - A5 = PA16 // D19 | [AD_B1_00] { 5 / 5 } - A6 = PA26 // D20 | [AD_B1_10] { 15 / 15 } - A7 = PA27 // D21 | [AD_B1_11] { 0 / 0 } - A8 = PA24 // D22 | [AD_B1_08] { 13 / 13 } - A9 = PA25 // D23 | [AD_B1_09] { 14 / 14 } - A10 = PA12 // D24 | [AD_B0_12] { 1 / - } - A11 = PA13 // D25 | [AD_B0_13] { 2 / - } - A12 = PA30 // D26 | [AD_B1_14] { - / 3 } - A13 = PA31 // D27 | [AD_B1_15] { - / 4 } - A14 = PA28 // D38 | [AD_B1_12] { ? / ? } // FIXME - A15 = PA29 // D39 | [AD_B1_13] { ? / ? } // FIXME - A16 = PA20 // D40 | [AD_B1_04] { ? / ? } // FIXME - A17 = PA21 // D41 | [AD_B1_05] { ? / ? } // FIXME -) - -// Default peripheral pins -const ( - LED = D13 - - UART_RX_PIN = UART1_RX_PIN // D0 - UART_TX_PIN = UART1_TX_PIN // D1 - - SPI_SDI_PIN = SPI1_SDI_PIN // D12 - SPI_SDO_PIN = SPI1_SDO_PIN // D11 - SPI_SCK_PIN = SPI1_SCK_PIN // D13 - SPI_CS_PIN = SPI1_CS_PIN // D10 - - I2C_SDA_PIN = I2C1_SDA_PIN // D18/A4 - I2C_SCL_PIN = I2C1_SCL_PIN // D19/A5 -) - -// Default peripherals -var ( - DefaultUART = UART1 -) - -func init() { - // register any interrupt handlers for this board's peripherals - _UART1.Interrupt = interrupt.New(nxp.IRQ_LPUART6, _UART1.handleInterrupt) - _UART2.Interrupt = interrupt.New(nxp.IRQ_LPUART4, _UART2.handleInterrupt) - _UART3.Interrupt = interrupt.New(nxp.IRQ_LPUART2, _UART3.handleInterrupt) - _UART4.Interrupt = interrupt.New(nxp.IRQ_LPUART3, _UART4.handleInterrupt) - _UART5.Interrupt = interrupt.New(nxp.IRQ_LPUART8, _UART5.handleInterrupt) - _UART6.Interrupt = interrupt.New(nxp.IRQ_LPUART1, _UART6.handleInterrupt) - _UART7.Interrupt = interrupt.New(nxp.IRQ_LPUART7, _UART7.handleInterrupt) - _UART8.Interrupt = interrupt.New(nxp.IRQ_LPUART5, _UART8.handleInterrupt) -} - -// #=====================================================# -// | UART | -// #===========#===========#=============#===============# -// | Interface | Hardware | Clock(Freq) | RX/TX : Alt | -// #===========#===========#=============#=========-=====# -// | UART1 | LPUART6 | OSC(24 MHz) | D0/D1 : 2/2 | -// | UART2 | LPUART4 | OSC(24 MHz) | D7/D8 : 2/2 | -// | UART3 | LPUART2 | OSC(24 MHz) | D15/D14 : 2/2 | -// | UART4 | LPUART3 | OSC(24 MHz) | D16/D17 : 2/2 | -// | UART5 | LPUART8 | OSC(24 MHz) | D21/D20 : 2/2 | -// | UART6 | LPUART1 | OSC(24 MHz) | D25/D24 : 2/2 | -// | UART7 | LPUART7 | OSC(24 MHz) | D28/D29 : 2/2 | -// | UART8 | LPUART5 | OSC(24 MHz) | D34/D35 : 1/1 | -// #===========#===========#=============#=========-=====# -const ( - UART1_RX_PIN = D0 - UART1_TX_PIN = D1 - - UART2_RX_PIN = D7 - UART2_TX_PIN = D8 - - UART3_RX_PIN = D15 - UART3_TX_PIN = D14 - - UART4_RX_PIN = D16 - UART4_TX_PIN = D17 - - UART5_RX_PIN = D21 - UART5_TX_PIN = D20 - - UART6_RX_PIN = D25 - UART6_TX_PIN = D24 - - UART7_RX_PIN = D28 - UART7_TX_PIN = D29 - - UART8_RX_PIN = D34 - UART8_TX_PIN = D35 -) - -var ( - UART1 = &_UART1 - _UART1 = UART{ - Bus: nxp.LPUART6, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D0 (PA3 [AD_B0_03]) - mux: nxp.IOMUXC_LPUART6_RX_SELECT_INPUT_DAISY_GPIO_AD_B0_03_ALT2, - sel: &nxp.IOMUXC.LPUART6_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D1 (PA2 [AD_B0_02]) - mux: nxp.IOMUXC_LPUART6_TX_SELECT_INPUT_DAISY_GPIO_AD_B0_02_ALT2, - sel: &nxp.IOMUXC.LPUART6_TX_SELECT_INPUT, - }, - } - UART2 = &_UART2 - _UART2 = UART{ - Bus: nxp.LPUART4, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D7 (PB17 [B1_01]) - mux: nxp.IOMUXC_LPUART4_RX_SELECT_INPUT_DAISY_GPIO_B1_01_ALT2, - sel: &nxp.IOMUXC.LPUART4_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D8 (PB16 [B1_00]) - mux: nxp.IOMUXC_LPUART4_TX_SELECT_INPUT_DAISY_GPIO_B1_00_ALT2, - sel: &nxp.IOMUXC.LPUART4_TX_SELECT_INPUT, - }, - } - UART3 = &_UART3 - _UART3 = UART{ - Bus: nxp.LPUART2, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D15 (PA19 [AD_B1_03]) - mux: nxp.IOMUXC_LPUART2_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_03_ALT2, - sel: &nxp.IOMUXC.LPUART2_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D14 (PA18 [AD_B1_02]) - mux: nxp.IOMUXC_LPUART2_TX_SELECT_INPUT_DAISY_GPIO_AD_B1_02_ALT2, - sel: &nxp.IOMUXC.LPUART2_TX_SELECT_INPUT, - }, - } - UART4 = &_UART4 - _UART4 = UART{ - Bus: nxp.LPUART3, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D16 (PA23 [AD_B1_07]) - mux: nxp.IOMUXC_LPUART3_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_07_ALT2, - sel: &nxp.IOMUXC.LPUART3_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D17 (PA22 [AD_B1_06]) - mux: nxp.IOMUXC_LPUART3_TX_SELECT_INPUT_DAISY_GPIO_AD_B1_06_ALT2, - sel: &nxp.IOMUXC.LPUART3_TX_SELECT_INPUT, - }, - } - UART5 = &_UART5 - _UART5 = UART{ - Bus: nxp.LPUART8, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D21 (PA27 [AD_B1_11]) - mux: nxp.IOMUXC_LPUART8_RX_SELECT_INPUT_DAISY_GPIO_AD_B1_11_ALT2, - sel: &nxp.IOMUXC.LPUART8_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D20 (PA26 [AD_B1_10]) - mux: nxp.IOMUXC_LPUART8_TX_SELECT_INPUT_DAISY_GPIO_AD_B1_10_ALT2, - sel: &nxp.IOMUXC.LPUART8_TX_SELECT_INPUT, - }, - } - UART6 = &_UART6 - _UART6 = UART{ - Bus: nxp.LPUART1, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - // LPUART1 not connected via IOMUXC - // RX: D24 (PA12 [AD_B0_12]) - // TX: D25 (PA13 [AD_B0_13]) - } - UART7 = &_UART7 - _UART7 = UART{ - Bus: nxp.LPUART7, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D28 (PC18 [EMC_32]) - mux: nxp.IOMUXC_LPUART7_RX_SELECT_INPUT_DAISY_GPIO_EMC_32_ALT2, - sel: &nxp.IOMUXC.LPUART7_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D29 (PD31 [EMC_31]) - mux: nxp.IOMUXC_LPUART7_TX_SELECT_INPUT_DAISY_GPIO_EMC_31_ALT2, - sel: &nxp.IOMUXC.LPUART7_TX_SELECT_INPUT, - }, - } - UART8 = &_UART8 - _UART8 = UART{ - Bus: nxp.LPUART5, - Buffer: NewRingBuffer(), - txBuffer: NewRingBuffer(), - muxRX: muxSelect{ // D34 (PB29 [B1_13]) - mux: nxp.IOMUXC_LPUART5_RX_SELECT_INPUT_DAISY_GPIO_B1_13_ALT1, - sel: &nxp.IOMUXC.LPUART5_RX_SELECT_INPUT, - }, - muxTX: muxSelect{ // D35 (PB28 [B1_12]) - mux: nxp.IOMUXC_LPUART5_TX_SELECT_INPUT_DAISY_GPIO_B1_12_ALT1, - sel: &nxp.IOMUXC.LPUART5_TX_SELECT_INPUT, - }, - } -) - -// #===========#==========#===============#===========================# -// | Interface | Hardware | Clock(Freq) | SDI/SDO/SCK/CS : Alt | -// #===========#==========#===============#=================-=========# -// | SPI1 | LPSPI4 | PLL2(132 MHz) | D12/D11/D13/D10 : 3/3/3/3 | -// | SPI2 | LPSPI3 | PLL2(132 MHz) | D1/D26/D27/D0 : 7/2/2/7 | -// | SPI3 | LPSPI1 | PLL2(132 MHz) | D34/D35/D37/D36 : 4/4/4/4 | -// #===========#==========#===============#=================-=========# -const ( - SPI1_SDI_PIN = D12 - SPI1_SDO_PIN = D11 - SPI1_SCK_PIN = D13 - SPI1_CS_PIN = D10 - - SPI2_SDI_PIN = D1 - SPI2_SDO_PIN = D26 - SPI2_SCK_PIN = D27 - SPI2_CS_PIN = D0 - - SPI3_SDI_PIN = D34 - SPI3_SDO_PIN = D35 - SPI3_SCK_PIN = D37 - SPI3_CS_PIN = D36 -) - -// #====================================================# -// | I2C | -// #===========#==========#=============#===============# -// | Interface | Hardware | Clock(Freq) | SDA/SCL : Alt | -// #===========#==========#=============#=========-=====# -// | I2C1 | LPI2C1 | OSC(24 MHz) | D18/D19 : 3/3 | -// | I2C2 | LPI2C3 | OSC(24 MHz) | D17/D16 : 1/1 | -// | I2C3 | LPI2C4 | OSC(24 MHz) | D25/D24 : 0/0 | -// #===========#==========#=============#=========-=====# -const ( - I2C1_SDA_PIN = D18 - I2C1_SCL_PIN = D19 - - I2C2_SDA_PIN = D17 - I2C2_SCL_PIN = D16 - - I2C3_SDA_PIN = D25 - I2C3_SCL_PIN = D24 -) diff --git a/emb/machine/board_thingplus_rp2040.go b/emb/machine/board_thingplus_rp2040.go deleted file mode 100644 index 48292d2..0000000 --- a/emb/machine/board_thingplus_rp2040.go +++ /dev/null @@ -1,103 +0,0 @@ -//go:build thingplus_rp2040 - -package machine - -// Onboard crystal oscillator frequency, in MHz. -const xoscFreq = 12 // MHz - -// GPIO Pins -const ( - GP0 Pin = GPIO0 // TX - GP1 Pin = GPIO1 // RX - GP2 Pin = GPIO2 // SCK - GP3 Pin = GPIO3 // COPI - GP4 Pin = GPIO4 // CIPO - - GP6 Pin = GPIO6 // SDA - GP7 Pin = GPIO7 // SCL (connected to GPIO23 as well) - GP8 Pin = GPIO8 // WS2812 RGB LED - GP9 Pin = GPIO9 // muSDcard DATA3 / CS - GP10 Pin = GPIO10 // muSDcard DATA2 - GP11 Pin = GPIO11 // muSDcard DATA1 - GP12 Pin = GPIO12 // muSDcard DATA0 / CIPO - - GP14 Pin = GPIO14 // muSDcard CLK /SCLK - GP15 Pin = GPIO15 // muSDcard CMD / COPI - GP16 Pin = GPIO16 // 16 - GP17 Pin = GPIO17 // 17 - GP18 Pin = GPIO18 // 18 - GP19 Pin = GPIO19 // 19 - GP20 Pin = GPIO20 // 20 - GP21 Pin = GPIO21 // 21 - GP22 Pin = GPIO22 // 22 - GP23 Pin = GPIO23 // Connected to GPIO7 - GP25 Pin = GPIO25 // Status blue LED - GP26 Pin = GPIO26 // ADC0 - GP27 Pin = GPIO27 // ADC1 - GP28 Pin = GPIO28 // ADC2 - GP29 Pin = GPIO29 // ADC3 -) - -// Analog pins -const ( - A0 = GPIO26 - A1 = GPIO27 - A2 = GPIO28 - A3 = GPIO29 -) - -// Onboard LEDs -const ( - LED = GPIO25 - WS2812 = GPIO8 -) - -// I2C Pins. -const ( - I2C0_SCL_PIN = GPIO6 // N/A - I2C0_SDA_PIN = GPIO7 // N/A - - I2C1_SDA_PIN = GPIO6 - I2C1_SCL_PIN = GPIO7 - - SDA_PIN = I2C1_SDA_PIN - SCL_PIN = I2C1_SCL_PIN -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO2 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO3 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO4 // Rx - - // Default Serial Clock Bus 1 for SPI communications to muSDcard - SPI1_SCK_PIN = GPIO14 - // Default Serial Out Bus 1 for SPI communications to muSDcard - SPI1_SDO_PIN = GPIO15 // Tx - // Default Serial In Bus 1 for SPI communications to muSDcard - SPI1_SDI_PIN = GPIO12 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Thing Plus RP2040" - usb_STRING_MANUFACTURER = "SparkFun" -) - -var ( - usb_VID uint16 = 0x1B4F - usb_PID uint16 = 0x0026 -) diff --git a/emb/machine/board_thumby.go b/emb/machine/board_thumby.go deleted file mode 100644 index f89a8b7..0000000 --- a/emb/machine/board_thumby.go +++ /dev/null @@ -1,76 +0,0 @@ -//go:build thumby - -// This contains the pin mappings for the Thumby. -// -// https://thumby.us/ -package machine - -const ( - THUMBY_SCK_PIN = I2C1_SDA_PIN - THUMBY_SDA_PIN = I2C1_SCL_PIN - - THUMBY_CS_PIN = GPIO16 - THUMBY_DC_PIN = GPIO17 - THUMBY_RESET_PIN = GPIO20 - - THUMBY_LINK_TX_PIN = UART0_TX_PIN - THUMBY_LINK_RX_PIN = UART0_RX_PIN - THUMBY_LINK_PU_PIN = GPIO2 - - THUMBY_BTN_LDPAD_PIN = GPIO3 - THUMBY_BTN_RDPAD_PIN = GPIO5 - THUMBY_BTN_UDPAD_PIN = GPIO4 - THUMBY_BTN_DDPAD_PIN = GPIO6 - THUMBY_BTN_B_PIN = GPIO24 - THUMBY_BTN_A_PIN = GPIO27 - - THUMBY_AUDIO_PIN = GPIO28 - - THUMBY_SCREEN_RESET_PIN = GPIO20 -) - -// I2C pins -const ( - I2C0_SDA_PIN Pin = NoPin - I2C0_SCL_PIN Pin = NoPin - - I2C1_SDA_PIN Pin = GPIO18 - I2C1_SCL_PIN Pin = GPIO19 -) - -// SPI pins -const ( - SPI0_SCK_PIN = GPIO18 - SPI0_SDO_PIN = GPIO19 - SPI0_SDI_PIN = GPIO16 - - SPI1_SCK_PIN = NoPin - SPI1_SDO_PIN = NoPin - SPI1_SDI_PIN = NoPin -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Thumby" - usb_STRING_MANUFACTURER = "TinyCircuits" -) - -var ( - usb_VID uint16 = 0x2E8A - usb_PID uint16 = 0x0005 -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 diff --git a/emb/machine/board_tiny2350.go b/emb/machine/board_tiny2350.go deleted file mode 100644 index f04fa06..0000000 --- a/emb/machine/board_tiny2350.go +++ /dev/null @@ -1,82 +0,0 @@ -//go:build tiny2350 - -package machine - -// GPIO pins -const ( - GP0 Pin = GPIO0 - GP1 Pin = GPIO1 - GP2 Pin = GPIO2 - GP3 Pin = GPIO3 - GP4 Pin = GPIO4 - GP5 Pin = GPIO5 - GP6 Pin = GPIO6 - GP7 Pin = GPIO7 - GP12 Pin = GPIO12 - GP13 Pin = GPIO13 - GP18 Pin = GPIO18 - GP19 Pin = GPIO19 - GP20 Pin = GPIO20 - GP26 Pin = GPIO26 - GP27 Pin = GPIO27 - GP28 Pin = GPIO28 - GP29 Pin = GPIO29 - - // Onboard LED - LED_RED Pin = GPIO18 - LED_GREEN Pin = GPIO19 - LED_BLUE Pin = GPIO20 - LED = LED_RED - - // Onboard crystal oscillator frequency, in MHz. - xoscFreq = 12 // MHz -) - -// I2C Default pins on Tiny2350. -const ( - I2C0_SDA_PIN = GP12 - I2C0_SCL_PIN = GP13 - - I2C1_SDA_PIN = GP2 - I2C1_SCL_PIN = GP3 -) - -// SPI default pins -const ( - // Default Serial Clock Bus 0 for SPI communications - SPI0_SCK_PIN = GPIO6 - // Default Serial Out Bus 0 for SPI communications - SPI0_SDO_PIN = GPIO7 // Tx - // Default Serial In Bus 0 for SPI communications - SPI0_SDI_PIN = GPIO4 // Rx - - // Default Serial Clock Bus 1 for SPI communications - SPI1_SCK_PIN = GPIO26 - // Default Serial Out Bus 1 for SPI communications - SPI1_SDO_PIN = GPIO27 // Tx - // Default Serial In Bus 1 for SPI communications - SPI1_SDI_PIN = GPIO28 // Rx -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART1_TX_PIN = GPIO4 - UART1_RX_PIN = GPIO5 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Tiny2350" - usb_STRING_MANUFACTURER = "Pimoroni" -) - -var ( - usb_VID uint16 = 0x2E8A - usb_PID uint16 = 0x000F -) diff --git a/emb/machine/board_trinket.go b/emb/machine/board_trinket.go deleted file mode 100644 index 089eadb..0000000 --- a/emb/machine/board_trinket.go +++ /dev/null @@ -1,88 +0,0 @@ -//go:build sam && atsamd21 && trinket_m0 - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PA08 // PWM available - D1 = PA02 - D2 = PA09 // PWM available - D3 = PA07 // PWM available / UART0 RX - D4 = PA06 // PWM available / UART0 TX - D13 = PA10 // LED -) - -// Analog pins -const ( - A0 = D1 - A1 = D2 - A2 = D0 - A3 = D3 - A4 = D4 -) - -const ( - LED = D13 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN = D4 - UART_RX_PIN = D3 -) - -// UART1 on the Trinket M0. -var UART1 = &sercomUSART0 - -// SPI pins -const ( - SPI0_SCK_PIN = D3 - SPI0_SDO_PIN = D4 - SPI0_SDI_PIN = D2 -) - -// SPI on the Trinket M0. -var SPI0 = sercomSPIM0 - -// I2C pins -const ( - SDA_PIN = D0 // SDA - SCL_PIN = D2 // SCL -) - -// I2C on the Trinket M0. -var ( - I2C0 = sercomI2CM2 -) - -// I2S pins -const ( - I2S_SCK_PIN = PA10 - I2S_SDO_PIN = PA08 - I2S_SDI_PIN = NoPin // TODO: figure out what this is on Trinket M0. - I2S_WS_PIN = NoPin // TODO: figure out what this is on Trinket M0. -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Adafruit Trinket M0" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239A - usb_PID uint16 = 0x801E -) - -var ( - DefaultUART = UART1 -) diff --git a/emb/machine/board_trinkey_qt2040.go b/emb/machine/board_trinkey_qt2040.go deleted file mode 100644 index 1a49c6d..0000000 --- a/emb/machine/board_trinkey_qt2040.go +++ /dev/null @@ -1,62 +0,0 @@ -//go:build trinkey_qt2040 - -// This file contains the pin mappings for the Adafruit Trinkey QT2040 board. -// -// The Trinkey QT2040 is a small development board based on the RP2040 which -// plugs into a USB A port. The board has a minimal pinout: an integrated -// NeoPixel LED and a STEMMA QT I2C port. -// -// - Product: https://www.adafruit.com/product/5056 -// - Overview: https://learn.adafruit.com/adafruit-trinkey-qt2040 -// - Pinouts: https://learn.adafruit.com/adafruit-trinkey-qt2040/pinouts -// - Datasheets: https://learn.adafruit.com/adafruit-trinkey-qt2040/downloads - -package machine - -// Onboard crystal oscillator frequency, in MHz -const xoscFreq = 12 // MHz - -// Onboard LEDs -const ( - NEOPIXEL = GPIO27 - WS2812 = NEOPIXEL -) - -// I2C pins -const ( - I2C0_SDA_PIN = GPIO16 - I2C0_SCL_PIN = GPIO17 - - I2C1_SDA_PIN = NoPin - I2C1_SCL_PIN = NoPin -) - -// SPI pins -const ( - SPI0_SCK_PIN = NoPin - SPI0_SDO_PIN = NoPin - SPI0_SDI_PIN = NoPin - - SPI1_SCK_PIN = NoPin - SPI1_SDO_PIN = NoPin - SPI1_SDI_PIN = NoPin -) - -// UART pins -const ( - UART0_TX_PIN = NoPin - UART0_RX_PIN = NoPin - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -// USB identifiers -const ( - usb_STRING_PRODUCT = "Trinkey QT2040" - usb_STRING_MANUFACTURER = "Adafruit" -) - -var ( - usb_VID uint16 = 0x239a - usb_PID uint16 = 0x8109 -) diff --git a/emb/machine/board_tufty2040.go b/emb/machine/board_tufty2040.go deleted file mode 100644 index 57d244f..0000000 --- a/emb/machine/board_tufty2040.go +++ /dev/null @@ -1,85 +0,0 @@ -//go:build tufty2040 - -// This contains the pin mappings for the Badger 2040 Connect board. -// -// For more information, see: https://shop.pimoroni.com/products/tufty-2040 -// Also -// - Tufty 2040 schematic: https://cdn.shopify.com/s/files/1/0174/1800/files/tufty_schematic.pdf?v=1655385675 -package machine - -const ( - LED Pin = GPIO25 - - BUTTON_A Pin = GPIO7 - BUTTON_B Pin = GPIO8 - BUTTON_C Pin = GPIO9 - BUTTON_UP Pin = GPIO22 - BUTTON_DOWN Pin = GPIO6 - BUTTON_USER Pin = GPIO23 - - LCD_BACKLIGHT Pin = GPIO2 - LCD_CS Pin = GPIO10 - LCD_DC Pin = GPIO11 - LCD_WR Pin = GPIO12 - LCD_RD Pin = GPIO13 - LCD_DB0 Pin = GPIO14 - LCD_DB1 Pin = GPIO15 - LCD_DB2 Pin = GPIO16 - LCD_DB3 Pin = GPIO17 - LCD_DB4 Pin = GPIO18 - LCD_DB5 Pin = GPIO19 - LCD_DB6 Pin = GPIO20 - LCD_DB7 Pin = GPIO21 - - VBUS_DETECT Pin = GPIO24 - BATTERY Pin = GPIO29 - USER_LED Pin = GPIO25 - LIGHT_SENSE Pin = GPIO26 - SENSOR_POWER Pin = GPIO27 -) - -// I2C pins -const ( - I2C0_SDA_PIN Pin = GPIO4 - I2C0_SCL_PIN Pin = GPIO5 - - I2C1_SDA_PIN Pin = NoPin - I2C1_SCL_PIN Pin = NoPin -) - -// SPI pins. -const ( - SPI0_SCK_PIN Pin = NoPin - SPI0_SDO_PIN Pin = NoPin - SPI0_SDI_PIN Pin = NoPin - - SPI1_SCK_PIN Pin = NoPin - SPI1_SDO_PIN Pin = NoPin - SPI1_SDI_PIN Pin = NoPin -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Tufty 2040" - usb_STRING_MANUFACTURER = "Pimoroni" -) - -var ( - usb_VID uint16 = 0x2e8a - usb_PID uint16 = 0x1002 -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 diff --git a/emb/machine/board_waveshare-rp2040-zero.go b/emb/machine/board_waveshare-rp2040-zero.go deleted file mode 100644 index 00ddc53..0000000 --- a/emb/machine/board_waveshare-rp2040-zero.go +++ /dev/null @@ -1,104 +0,0 @@ -//go:build waveshare_rp2040_zero - -// This file contains the pin mappings for the Waveshare RP2040-Zero boards. -// -// Waveshare RP2040-Zero is a microcontroller using the Raspberry Pi RP2040 chip. -// -// - https://www.waveshare.com/wiki/RP2040-Zero -package machine - -// Digital Pins -const ( - D0 Pin = GPIO0 - D1 Pin = GPIO1 - D2 Pin = GPIO2 - D3 Pin = GPIO3 - D4 Pin = GPIO4 - D5 Pin = GPIO5 - D6 Pin = GPIO6 - D7 Pin = GPIO7 - D8 Pin = GPIO8 - D9 Pin = GPIO9 - D10 Pin = GPIO10 - D11 Pin = GPIO11 - D12 Pin = GPIO12 - D13 Pin = GPIO13 - D14 Pin = GPIO14 - D15 Pin = GPIO15 - D16 Pin = GPIO16 - D17 Pin = GPIO17 - D18 Pin = GPIO18 - D19 Pin = GPIO19 - D20 Pin = GPIO20 - D21 Pin = GPIO21 - D22 Pin = GPIO22 - D23 Pin = GPIO23 - D24 Pin = GPIO24 - D25 Pin = GPIO25 - D26 Pin = GPIO26 - D27 Pin = GPIO27 - D28 Pin = GPIO28 - D29 Pin = GPIO29 -) - -// Analog pins -const ( - A0 Pin = D26 - A1 Pin = D27 - A2 Pin = D28 - A3 Pin = D29 -) - -// Onboard LEDs -const ( - NEOPIXEL = GPIO16 - WS2812 = GPIO16 -) - -// I2C pins -const ( - I2C0_SDA_PIN Pin = D0 - I2C0_SCL_PIN Pin = D1 - - I2C1_SDA_PIN Pin = D2 - I2C1_SCL_PIN Pin = D3 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = D6 - SPI0_SDO_PIN Pin = D3 - SPI0_SDI_PIN Pin = D4 - - SPI1_SCK_PIN Pin = D10 - SPI1_SDO_PIN Pin = D11 - SPI1_SDI_PIN Pin = D12 -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN - UART1_TX_PIN = GPIO8 - UART1_RX_PIN = GPIO9 -) - -var DefaultUART = UART0 - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "RP2040-Zero" - usb_STRING_MANUFACTURER = "Waveshare" -) - -var ( - usb_VID uint16 = 0x2e8a - usb_PID uint16 = 0x0003 -) diff --git a/emb/machine/board_waveshare_rp2040_tiny.go b/emb/machine/board_waveshare_rp2040_tiny.go deleted file mode 100644 index a3ef354..0000000 --- a/emb/machine/board_waveshare_rp2040_tiny.go +++ /dev/null @@ -1,121 +0,0 @@ -//go:build waveshare_rp2040_tiny - -// This file contains the pin mappings for the Waveshare RP2040-Tiny boards. -// -// Waveshare RP2040-Tiny is a microcontroller using the Raspberry Pi RP2040 chip. -// -// - https://www.waveshare.com/wiki/RP2040-Tiny -package machine - -// Digital Pins -const ( - GP0 Pin = GPIO0 - GP1 Pin = GPIO1 - GP2 Pin = GPIO2 - GP3 Pin = GPIO3 - GP4 Pin = GPIO4 - GP5 Pin = GPIO5 - GP6 Pin = GPIO6 - GP7 Pin = GPIO7 - GP8 Pin = GPIO8 - GP9 Pin = GPIO9 - GP10 Pin = GPIO10 - GP11 Pin = GPIO11 - GP12 Pin = GPIO12 - GP13 Pin = GPIO13 - GP14 Pin = GPIO14 - GP15 Pin = GPIO15 - GP16 Pin = GPIO16 - GP17 Pin = NoPin - GP18 Pin = NoPin - GP19 Pin = NoPin - GP20 Pin = NoPin - GP21 Pin = NoPin - GP22 Pin = NoPin - GP23 Pin = NoPin - GP24 Pin = GPIO24 - GP25 Pin = GPIO25 - GP26 Pin = GPIO26 - GP27 Pin = GPIO27 - GP28 Pin = GPIO28 - GP29 Pin = GPIO29 -) - -// Analog pins -const ( - A0 Pin = GP26 - A1 Pin = GP27 - A2 Pin = GP28 - A3 Pin = GP29 -) - -// Onboard LEDs -const ( - LED = GP16 - WS2812 = GP16 -) - -// I2C pins -const ( - I2C0_SDA_PIN Pin = GP0 - I2C0_SCL_PIN Pin = GP1 - I2C1_SDA_PIN Pin = GP2 - I2C1_SCL_PIN Pin = GP3 - - // default I2C0 - I2C_SDA_PIN Pin = I2C0_SDA_PIN - I2C_SCL_PIN Pin = I2C0_SCL_PIN -) - -// SPI pins -const ( - SPI0_RX_PIN Pin = GP0 - SPI0_CSN_PIN Pin = GP1 - SPI0_SCK_PIN Pin = GP2 - SPI0_TX_PIN Pin = GP3 - SPI0_SDO_PIN Pin = SPI0_TX_PIN - SPI0_SDI_PIN Pin = SPI0_RX_PIN - - SPI1_RX_PIN Pin = GP8 - SPI1_CSN_PIN Pin = GP9 - SPI1_SCK_PIN Pin = GP10 - SPI1_TX_PIN Pin = GP11 - SPI1_SDO_PIN Pin = SPI1_TX_PIN - SPI1_SDI_PIN Pin = SPI1_RX_PIN - - // default SPI0 - SPI_RX_PIN Pin = SPI0_RX_PIN - SPI_CSN_PIN Pin = SPI0_CSN_PIN - SPI_SCK_PIN Pin = SPI0_SCK_PIN - SPI_TX_PIN Pin = SPI0_TX_PIN - SPI_SDO_PIN Pin = SPI0_TX_PIN - SPI_SDI_PIN Pin = SPI0_RX_PIN -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// UART pins -const ( - UART0_TX_PIN = GP0 - UART0_RX_PIN = GP1 - UART1_TX_PIN = GP8 - UART1_RX_PIN = GP9 - - // default UART0 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "RP2040-Tiny" - usb_STRING_MANUFACTURER = "Waveshare" -) - -var ( - usb_VID uint16 = 0x2e8a - usb_PID uint16 = 0x0003 -) diff --git a/emb/machine/board_wioterminal.go b/emb/machine/board_wioterminal.go deleted file mode 100644 index 6997120..0000000 --- a/emb/machine/board_wioterminal.go +++ /dev/null @@ -1,432 +0,0 @@ -//go:build wioterminal - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -const ( - ADC0 = A0 - ADC1 = A1 - ADC2 = A2 - ADC3 = A3 - ADC4 = A4 - ADC5 = A5 - ADC6 = A6 - ADC7 = A7 - ADC8 = A8 - - LED = PIN_LED - BUTTON = BUTTON_1 -) - -const ( - // https://github.com/Seeed-Studio/ArduinoCore-samd/blob/master/variants/wio_terminal/variant.h - - // LEDs - PIN_LED_13 = PA15 - PIN_LED_RXL = PA15 - PIN_LED_TXL = PA15 - PIN_LED = PIN_LED_13 - PIN_LED2 = PIN_LED_RXL - PIN_LED3 = PIN_LED_TXL - LED_BUILTIN = PIN_LED_13 - PIN_NEOPIXEL = PA15 - - //Digital PINs - D0 = PB08 - D1 = PB09 - D2 = PA07 - D3 = PB04 - D4 = PB05 - D5 = PB06 - D6 = PA04 - D7 = PB07 - D8 = PA06 - - //Analog PINs - A0 = PB08 // ADC/AIN[0] - A1 = PB09 // ADC/AIN[2] - A2 = PA07 // ADC/AIN[3] - A3 = PB04 // ADC/AIN[4] - A4 = PB05 // ADC/AIN[5] - A5 = PB06 // ADC/AIN[10] - A6 = PA04 // ADC/AIN[10] - A7 = PB07 // ADC/AIN[10] - A8 = PA06 // ADC/AIN[10] - - // 3.3V || 5V - // BCM2 || 5V - // BCM3 || GND - // BCM4 || BCM14 - // GND || BCM15 - // BCM17 || BCM18 - // BCM27 || GND - // BCM22 || BCM23 - // GND || BCM24 - // BCM10 || GND - // BCM9 || BCM25 - // BCM11 || BCM8 - // GND || BCM7 - // BCM0 || BCM1 - // BCM5 || GND - // BCM6 || BCM12 - // BCM13 || GND - // BCM19 || BCM16 - // BCM26 || BCM20 - // GND || BCM21 - - //PIN DEFINE FOR RPI - BCM0 = PA13 // I2C Wire1 - BCM1 = PA12 // I2C Wire1 - BCM2 = PA17 // I2C Wire2 - BCM3 = PA16 // I2C Wire2 - BCM4 = PB14 // GCLK - BCM5 = PB12 // GCLK - BCM6 = PB13 // GCLK - BCM7 = PA05 // DAC1 - BCM8 = PB01 // SPI SS - BCM9 = PB00 // SPI SDI - BCM10 = PB02 // SPI SDO - BCM11 = PB03 // SPI SCK - BCM12 = PB06 - BCM13 = PA04 - BCM14 = PB27 // UART Serial1 - BCM15 = PB26 // UART Serial1 - BCM16 = PB07 - BCM17 = PA02 // DAC0 - BCM18 = PB28 // FPC Digital & AD pins - BCM19 = PA20 // WIO_IR - BCM20 = PA21 // I2S SDO - BCM21 = PA22 // I2S SDI - BCM22 = PB09 - BCM23 = PA07 - BCM24 = PB04 - BCM25 = PB05 - BCM26 = PA06 - BCM27 = PB08 - - // FPC NEW DEFINE - FPC1 = PB28 // FPC Digital & AD pins - FPC2 = PB17 - FPC3 = PB29 - FPC4 = PA14 - FPC5 = PC01 - FPC6 = PC02 - FPC7 = PC03 - FPC8 = PC04 - FPC9 = PC31 - FPC10 = PD00 - - // RPI Analog RPIs - RPI_A0 = PB08 - RPI_A1 = PB09 - RPI_A2 = PA07 - RPI_A3 = PB04 - RPI_A4 = PB05 - RPI_A5 = PB06 - RPI_A6 = PA04 - RPI_A7 = PB07 - RPI_A8 = PA06 - - PIN_DAC0 = PA02 - PIN_DAC1 = PA05 - - // FPO Analog RPIs - //FPC_A7 = FPC_D7 - //FPC_A8 = FPC_D8 - //FPC_A9 = FPC_D9 - //FPC_A11 = FPC_D11 - //FPC_A12 = FPC_D12 - //FPC_A13 = FPC_D13 - - // USB - PIN_USB_DM = PA24 - PIN_USB_DP = PA25 - PIN_USB_HOST_ENABLE = PA27 - - // BUTTON - BUTTON_1 = PC26 - BUTTON_2 = PC27 - BUTTON_3 = PC28 - WIO_KEY_A = PC26 - WIO_KEY_B = PC27 - WIO_KEY_C = PC28 - - // SWITCH - SWITCH_X = PD20 - SWITCH_Y = PD12 - SWITCH_Z = PD09 - SWITCH_B = PD08 - SWITCH_U = PD10 - - WIO_5S_UP = PD20 - WIO_5S_LEFT = PD12 - WIO_5S_RIGHT = PD09 - WIO_5S_DOWN = PD08 - WIO_5S_PRESS = PD10 - - // IRQ0 : RTL8720D - IRQ0 = PC20 - - // BUZZER_CTR - BUZZER_CTR = PD11 - WIO_BUZZER = PD11 - - // MIC_INPUT - MIC_INPUT = PC30 - WIO_MIC = PC30 - - // GCLK - GCLK0 = PB14 - GCLK1 = PB12 - GCLK2 = PB13 - - // Serial interfaces - // Serial1 - PIN_SERIAL1_RX = PB27 - PIN_SERIAL1_TX = PB26 - - // Serial2 : RTL8720D - PIN_SERIAL2_RX = PC23 - PIN_SERIAL2_TX = PC22 - - // Wire Interfaces - // I2C Wire2 - // I2C1 - PIN_WIRE_SDA = PA17 - PIN_WIRE_SCL = PA16 - SDA = PIN_WIRE_SDA - SCL = PIN_WIRE_SCL - - // I2C Wire1 - // I2C0 : LIS3DHTR and ATECC608 - PIN_WIRE1_SDA = PA13 - PIN_WIRE1_SCL = PA12 - - SDA1 = PIN_WIRE1_SDA - SCL1 = PIN_WIRE1_SCL - - PIN_GYROSCOPE_WIRE_SDA = PIN_WIRE1_SDA - PIN_GYROSCOPE_WIRE_SCL = PIN_WIRE1_SCL - GYROSCOPE_INT1 = PC21 - - WIO_LIS3DH_SDA = PIN_WIRE1_SDA - WIO_LIS3DH_SCL = PIN_WIRE1_SCL - WIO_LIS3DH_INT = PC21 - - // SPI - PIN_SPI_SDI = PB00 - PIN_SPI_SDO = PB02 - PIN_SPI_SCK = PB03 - PIN_SPI_SS = PB01 - - SS = PIN_SPI_SS - SDO = PIN_SPI_SDO - SDI = PIN_SPI_SDI - SCK = PIN_SPI_SCK - - // SPI1 RTL8720D_SPI - PIN_SPI1_SDI = PC24 - PIN_SPI1_SDO = PB24 - PIN_SPI1_SCK = PB25 - PIN_SPI1_SS = PC25 - - SS1 = PIN_SPI1_SS - SDO1 = PIN_SPI1_SDO - SDI1 = PIN_SPI1_SDI - SCK1 = PIN_SPI1_SCK - - // SPI2 SD_SPI - PIN_SPI2_SDI = PC18 - PIN_SPI2_SDO = PC16 - PIN_SPI2_SCK = PC17 - PIN_SPI2_SS = PC19 - - SS2 = PIN_SPI2_SS - SDO2 = PIN_SPI2_SDO - SDI2 = PIN_SPI2_SDI - SCK2 = PIN_SPI2_SCK - - // SPI3 LCD_SPI - PIN_SPI3_SDI = PB18 - PIN_SPI3_SDO = PB19 - PIN_SPI3_SCK = PB20 - PIN_SPI3_SS = PB21 - - SS3 = PIN_SPI3_SS - SDO3 = PIN_SPI3_SDO - SDI3 = PIN_SPI3_SDI - SCK3 = PIN_SPI3_SCK - - // Needed for SD library - SDCARD_SDI_PIN = PIN_SPI2_SDI - SDCARD_SDO_PIN = PIN_SPI2_SDO - SDCARD_SCK_PIN = PIN_SPI2_SCK - SDCARD_SS_PIN = PIN_SPI2_SS - SDCARD_DET_PIN = PD21 - - LCD_SDI_PIN = PIN_SPI3_SDI - LCD_SDO_PIN = PIN_SPI3_SDO - LCD_SCK_PIN = PIN_SPI3_SCK - LCD_SS_PIN = PIN_SPI3_SS - LCD_DC = PC06 - LCD_RESET = PC07 - LCD_BACKLIGHT = PC05 - - // 4 WIRE LCD TOUCH - LCD_XL = PC10 - LCD_YU = PC11 - LCD_XR = PC12 - LCD_YD = PC13 - - // Needed for RTL8720D - RTL8720D_SDI_PIN = PIN_SPI1_SDI - RTL8720D_SDO_PIN = PIN_SPI1_SDO - RTL8720D_SCK_PIN = PIN_SPI1_SCK - RTL8720D_SS_PIN = PIN_SPI1_SS - - //QSPI Pins - PIN_QSPI_IO0 = PA08 - PIN_QSPI_IO1 = PA09 - PIN_QSPI_IO2 = PA10 - PIN_QSPI_IO3 = PA11 - PIN_QSPI_SCK = PB10 - PIN_QSPI_CS = PB11 - - // I2S Interfaces - PIN_I2S_FS = PA20 - PIN_I2S_SCK = PB16 - PIN_I2S_SDO = PA22 - PIN_I2S_SDI = PA21 - - I2S_LRCLK = PA20 - I2S_BLCK = PB16 - I2S_SDOUT = PA22 - I2S_SDIN = PA21 - - // RTL8720D Interfaces - RTL8720D_CHIP_PU = PA18 - RTL8720D_GPIO0 = PA19 // SYNC - - // SWD - SWDCLK = PA30 - SWDIO = PA31 - SWO = PB30 - - // light sensor - WIO_LIGHT = PD01 - - // ir sensor - WIO_IR = PB31 - - // OUTPUT_CTR - OUTPUT_CTR_5V = PC14 - OUTPUT_CTR_3V3 = PC15 -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PIN_USB_DM - USBCDC_DP_PIN = PIN_USB_DP -) - -// UART1 pins -const ( - UART_TX_PIN = PIN_SERIAL1_TX - UART_RX_PIN = PIN_SERIAL1_RX -) - -// UART2 pins RTL8720D -const ( - UART2_TX_PIN = PIN_SERIAL2_TX - UART2_RX_PIN = PIN_SERIAL2_RX -) - -var ( - DefaultUART = UART1 - - UART1 = &sercomUSART2 - - // RTL8720D (tx: PC22, rx: PC23) - UART2 = &sercomUSART1 - - // RTL8720D (tx: PB24, rx: PC24) - UART3 = &sercomUSART0 - - // Right-hand grove port (tx: D0, rx: D1) - UART4 = &sercomUSART4 -) - -// I2C pins -const ( - SDA1_PIN = PA17 // SDA: SERCOM3/PAD[0] - SCL1_PIN = PA16 // SCL: SERCOM3/PAD[1] - - SDA0_PIN = PA13 // SDA: SERCOM4/PAD[0] - SCL0_PIN = PA12 // SCL: SERCOM4/PAD[1] - - SDA_PIN = SDA1_PIN - SCL_PIN = SCL1_PIN -) - -// I2C on the Wio Terminal -var ( - I2C0 = sercomI2CM4 - I2C1 = sercomI2CM3 -) - -// I2S pins -const ( - I2S_SCK_PIN = BCM18 - I2S_SDO_PIN = BCM21 - I2S_SDI_PIN = BCM20 - I2S_WS_PIN = BCM19 -) - -// SPI pins -const ( - SPI0_SCK_PIN = SCK // SCK: SERCOM5/PAD[1] - SPI0_SDO_PIN = SDO // SDO: SERCOM5/PAD[0] - SPI0_SDI_PIN = SDI // SDI: SERCOM5/PAD[2] - - // RTL8720D - SPI1_SCK_PIN = SCK1 // SCK: SERCOM0/PAD[1] - SPI1_SDO_PIN = SDO1 // SDO: SERCOM0/PAD[0] - SPI1_SDI_PIN = SDI1 // SDI: SERCOM0/PAD[2] - - // SD - SPI2_SCK_PIN = SCK2 // SCK: SERCOM6/PAD[1] - SPI2_SDO_PIN = SDO2 // SDO: SERCOM6/PAD[0] - SPI2_SDI_PIN = SDI2 // SDI: SERCOM6/PAD[2] - - // LCD - SPI3_SCK_PIN = SCK3 // SCK: SERCOM7/PAD[1] - SPI3_SDO_PIN = SDO3 // SDO: SERCOM7/PAD[3] - SPI3_SDI_PIN = SDI3 // SDI: SERCOM7/PAD[2] -) - -// SPI on the Wio Terminal -var ( - SPI0 = sercomSPIM5 - - // RTL8720D - SPI1 = sercomSPIM0 - - // SD - SPI2 = sercomSPIM6 - - // LCD - SPI3 = sercomSPIM7 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Seeed Wio Terminal" - usb_STRING_MANUFACTURER = "Seeed" -) - -var ( - usb_VID uint16 = 0x2886 - usb_PID uint16 = 0x802D -) diff --git a/emb/machine/board_x9pro.go b/emb/machine/board_x9pro.go deleted file mode 100644 index 88468e9..0000000 --- a/emb/machine/board_x9pro.go +++ /dev/null @@ -1,30 +0,0 @@ -//go:build x9pro - -package machine - -// https://hackaday.io/project/144350-hacking-wearables-for-mental-health-and-more/details -const ( - LED Pin = 4 // HR LED pin - UART_TX_PIN Pin = NoPin - UART_RX_PIN Pin = NoPin - SCL_PIN Pin = NoPin - SDA_PIN Pin = NoPin - SPI0_SCK_PIN Pin = 18 - SPI0_SDI_PIN Pin = 19 - SPI0_SDO_PIN Pin = 20 -) - -// LCD pins. -const ( - OLED_CS Pin = 15 // chip select - OLED_RES Pin = 14 // reset pin - OLED_DC Pin = 13 // data/command - OLED_SCK Pin = 12 // SPI clock - OLED_SDO Pin = 11 // SPI SDO (chip-out, peripheral-in) - OLED_LED_POW Pin = 16 - OLED_IC_POW Pin = 17 -) - -const HasLowFrequencyCrystal = true - -var DefaultUART = UART0 diff --git a/emb/machine/board_xiao-ble.go b/emb/machine/board_xiao-ble.go deleted file mode 100644 index b4168d8..0000000 --- a/emb/machine/board_xiao-ble.go +++ /dev/null @@ -1,111 +0,0 @@ -//go:build xiao_ble - -// This file contains the pin mappings for the Seeed XIAO BLE nRF52840 [Sense] boards. -// -// Seeed XIAO BLE is an ultra-small size, ultra-low power Bluetooth development board based on the Nordic nRF52840. -// It features an onboard Bluetooth antenna, onboard battery charging chip, and 21*17.5mm thumb size, which makes it ideal for IoT projects. -// -// Seeed XIAO BLE nRF52840 Sense is a tiny Bluetooth LE development board designed for IoT and AI applications. -// It features an onboard antenna, 6 Dof IMU, microphone, all of which make it an ideal board to run AI using TinyML and TensorFlow Lite. -// -// SoftDevice (s140v7) is pre-flashed on this board already. -// See https://github.com/tinygo-org/bluetooth -// -// - https://www.seeedstudio.com/Seeed-XIAO-BLE-nRF52840-p-5201.html -// - https://www.seeedstudio.com/Seeed-XIAO-BLE-Sense-nRF52840-p-5253.html -// -// - https://wiki.seeedstudio.com/XIAO_BLE/ -// - https://github.com/Seeed-Studio/ArduinoCore-mbed/tree/master/variants/SEEED_XIAO_NRF52840_SENSE -package machine - -const HasLowFrequencyCrystal = true - -// Digital Pins -const ( - D0 Pin = P0_02 - D1 Pin = P0_03 - D2 Pin = P0_28 - D3 Pin = P0_29 - D4 Pin = P0_04 - D5 Pin = P0_05 - D6 Pin = P1_11 - D7 Pin = P1_12 - D8 Pin = P1_13 - D9 Pin = P1_14 - D10 Pin = P1_15 -) - -// Analog pins -const ( - A0 Pin = P0_02 - A1 Pin = P0_03 - A2 Pin = P0_28 - A3 Pin = P0_29 - A4 Pin = P0_04 - A5 Pin = P0_05 -) - -// Onboard LEDs -const ( - LED = LED_CHG - LED1 = LED_RED - LED2 = LED_GREEN - LED3 = LED_BLUE - LED_CHG = P0_17 - LED_RED = P0_26 - LED_GREEN = P0_30 - LED_BLUE = P0_06 -) - -// UART0 pins -const ( - UART_RX_PIN = P1_12 - UART_TX_PIN = P1_11 -) - -// I2C pins -const ( - // Defaults to internal - SDA_PIN = SDA1_PIN - SCL_PIN = SCL1_PIN - - // I2C0 (external) pins - SDA0_PIN = P0_04 - SCL0_PIN = P0_05 - - // I2C1 (internal) pins - SDA1_PIN = P0_07 - SCL1_PIN = P0_27 -) - -// SPI pins -const ( - SPI0_SCK_PIN = P1_13 - SPI0_SDO_PIN = P1_14 - SPI0_SDI_PIN = P1_15 -) - -// Peripherals -const ( - LSM_PWR = P1_08 // IMU (LSM6DS3TR) power - LSM_INT = P0_11 // IMU (LSM6DS3TR) interrupt - - MIC_PWR = P1_10 // Microphone (MSM261D3526H1CPM) power - MIC_CLK = P1_00 - MIC_DIN = P0_16 -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "XIAO nRF52840 Sense" - usb_STRING_MANUFACTURER = "Seeed" -) - -var ( - usb_VID uint16 = 0x2886 - usb_PID uint16 = 0x8045 -) - -var ( - DefaultUART = UART0 -) diff --git a/emb/machine/board_xiao-esp32c3.go b/emb/machine/board_xiao-esp32c3.go deleted file mode 100644 index 5a2cf2e..0000000 --- a/emb/machine/board_xiao-esp32c3.go +++ /dev/null @@ -1,53 +0,0 @@ -//go:build xiao_esp32c3 - -// This file contains the pin mappings for the Seeed XIAO ESP32C3 boards. -// -// Seeed Studio XIAO ESP32C3 is an IoT mini development board based on -// the Espressif ESP32-C3 WiFi/Bluetooth dual-mode chip. -// -// - https://www.seeedstudio.com/Seeed-XIAO-ESP32C3-p-5431.html -// - https://wiki.seeedstudio.com/XIAO_ESP32C3_Getting_Started/ - -package machine - -// Digital Pins -const ( - D0 = GPIO2 - D1 = GPIO3 - D2 = GPIO4 - D3 = GPIO5 - D4 = GPIO6 - D5 = GPIO7 - D6 = GPIO21 - D7 = GPIO20 - D8 = GPIO8 - D9 = GPIO9 - D10 = GPIO10 -) - -// Analog pins -const ( - A0 = GPIO2 - A1 = GPIO3 - A2 = GPIO4 - A3 = GPIO5 -) - -// UART pins -const ( - UART_RX_PIN = GPIO20 - UART_TX_PIN = GPIO21 -) - -// I2C pins -const ( - SDA_PIN = GPIO6 - SCL_PIN = GPIO7 -) - -// SPI pins -const ( - SPI_SCK_PIN = GPIO8 - SPI_SDI_PIN = GPIO9 - SPI_SDO_PIN = GPIO10 -) diff --git a/emb/machine/board_xiao-rp2040.go b/emb/machine/board_xiao-rp2040.go deleted file mode 100644 index b010314..0000000 --- a/emb/machine/board_xiao-rp2040.go +++ /dev/null @@ -1,90 +0,0 @@ -//go:build xiao_rp2040 - -// This file contains the pin mappings for the Seeed XIAO RP2040 boards. -// -// XIAO RP2040 is a microcontroller using the Raspberry Pi RP2040 chip. -// -// - https://wiki.seeedstudio.com/XIAO-RP2040/ -package machine - -// Digital Pins -const ( - D0 Pin = GPIO26 - D1 Pin = GPIO27 - D2 Pin = GPIO28 - D3 Pin = GPIO29 - D4 Pin = GPIO6 - D5 Pin = GPIO7 - D6 Pin = GPIO0 - D7 Pin = GPIO1 - D8 Pin = GPIO2 - D9 Pin = GPIO4 - D10 Pin = GPIO3 -) - -// Analog pins -const ( - A0 Pin = D0 - A1 Pin = D1 - A2 Pin = D2 - A3 Pin = D3 -) - -// Onboard LEDs -const ( - NEOPIXEL = GPIO12 - WS2812 = GPIO12 - NEO_PWR = GPIO11 - NEOPIXEL_POWER = GPIO11 - - LED = GPIO17 - LED_RED = GPIO17 - LED_GREEN = GPIO16 - LED_BLUE = GPIO25 -) - -// I2C pins -const ( - I2C0_SDA_PIN Pin = D2 - I2C0_SCL_PIN Pin = D3 - - I2C1_SDA_PIN Pin = D4 - I2C1_SCL_PIN Pin = D5 -) - -// SPI pins -const ( - SPI0_SCK_PIN Pin = D8 - SPI0_SDO_PIN Pin = D10 - SPI0_SDI_PIN Pin = D9 - - SPI1_SCK_PIN Pin = NoPin - SPI1_SDO_PIN Pin = NoPin - SPI1_SDI_PIN Pin = NoPin -) - -// Onboard crystal oscillator frequency, in MHz. -const ( - xoscFreq = 12 // MHz -) - -// UART pins -const ( - UART0_TX_PIN = GPIO0 - UART0_RX_PIN = GPIO1 - UART_TX_PIN = UART0_TX_PIN - UART_RX_PIN = UART0_RX_PIN -) - -var DefaultUART = UART0 - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "XIAO RP2040" - usb_STRING_MANUFACTURER = "Seeed" -) - -var ( - usb_VID uint16 = 0x2e8a - usb_PID uint16 = 0x000a -) diff --git a/emb/machine/board_xiao.go b/emb/machine/board_xiao.go deleted file mode 100644 index 5bbb34d..0000000 --- a/emb/machine/board_xiao.go +++ /dev/null @@ -1,103 +0,0 @@ -//go:build sam && atsamd21 && xiao - -package machine - -// used to reset into bootloader -const resetMagicValue = 0xf01669ef - -// GPIO Pins -const ( - D0 = PA02 // can be used for PWM or DAC - D1 = PA04 // PWM available - D2 = PA10 // PWM available - D3 = PA11 // PWM available - D4 = PA08 // can be used for PWM or I2C SDA - D5 = PA09 // can be used for PWM or I2C SCL - D6 = PB08 // can be used for PWM or UART1 TX - D7 = PB09 // can be used for PWM or UART1 RX - D8 = PA07 // can be used for PWM or SPI SCK - D9 = PA05 // can be used for PWM or SPI SDI - D10 = PA06 // can be used for PWM or SPI SDO -) - -// Analog pins -const ( - A0 = PA02 // ADC/AIN[0] - A1 = PA04 // ADC/AIN[4] - A2 = PA10 // ADC/AIN[18] - A3 = PA11 // ADC/AIN[19] - A4 = PA08 // ADC/AIN[16] - A5 = PA09 // ADC/AIN[17] - A6 = PB08 // ADC/AIN[2] - A7 = PB09 // ADC/AIN[3] - A8 = PA07 // ADC/AIN[7] - A9 = PA05 // ADC/AIN[6] - A10 = PA06 // ADC/AIN[5] -) - -const ( - LED = PA17 - LED_RXL = PA18 - LED_TXL = PA19 - LED2 = LED_RXL - LED3 = LED_TXL -) - -// USBCDC pins -const ( - USBCDC_DM_PIN = PA24 - USBCDC_DP_PIN = PA25 -) - -// UART1 pins -const ( - UART_TX_PIN = D6 - UART_RX_PIN = D7 -) - -// UART1 on the Xiao -var UART1 = &sercomUSART4 - -// I2C pins -const ( - SDA_PIN = PA08 // SDA: SERCOM2/PAD[0] - SCL_PIN = PA09 // SCL: SERCOM2/PAD[1] -) - -// I2C on the Xiao -var ( - I2C0 = sercomI2CM2 -) - -// SPI pins -const ( - SPI0_SCK_PIN = PA07 // SCK: SERCOM0/PAD[3] - SPI0_SDO_PIN = PA06 // SDO: SERCOM0/PAD[2] - SPI0_SDI_PIN = PA05 // SDI: SERCOM0/PAD[1] -) - -// SPI on the Xiao -var SPI0 = sercomSPIM0 - -// I2S pins -const ( - I2S_SCK_PIN = PA10 - I2S_SDO_PIN = PA08 - I2S_SDI_PIN = NoPin // TODO: figure out what this is on Xiao - I2S_WS_PIN = NoPin // TODO: figure out what this is on Xiao -) - -// USB CDC identifiers -const ( - usb_STRING_PRODUCT = "Seeed XIAO M0" - usb_STRING_MANUFACTURER = "Seeed" -) - -var ( - usb_VID uint16 = 0x2886 - usb_PID uint16 = 0x802F -) - -var ( - DefaultUART = UART1 -) diff --git a/emb/machine/buffer_atmega.go b/emb/machine/buffer_atmega.go deleted file mode 100644 index a321eae..0000000 --- a/emb/machine/buffer_atmega.go +++ /dev/null @@ -1,5 +0,0 @@ -//go:build atmega - -package machine - -const bufferSize = 32 diff --git a/emb/machine/buffer_generic.go b/emb/machine/buffer_generic.go deleted file mode 100644 index 0d82b44..0000000 --- a/emb/machine/buffer_generic.go +++ /dev/null @@ -1,5 +0,0 @@ -//go:build !atmega - -package machine - -const bufferSize = 128 diff --git a/emb/machine/deviceid.go b/emb/machine/deviceid.go deleted file mode 100644 index cb2e1d0..0000000 --- a/emb/machine/deviceid.go +++ /dev/null @@ -1,17 +0,0 @@ -//go:build rp2040 || nrf || sam - -package machine - -// DeviceID returns an identifier that is unique within -// a particular chipset. -// -// The identity is one burnt into the MCU itself, or the -// flash chip at time of manufacture. -// -// It's possible that two different vendors may allocate -// the same DeviceID, so callers should take this into -// account if needing to generate a globally unique id. -// -// The length of the hardware ID is vendor-specific, but -// 8 bytes (64 bits) and 16 bytes (128 bits) are common. -var _ = (func() []byte)(DeviceID) diff --git a/emb/machine/flash.go b/emb/machine/flash.go deleted file mode 100644 index c89c091..0000000 --- a/emb/machine/flash.go +++ /dev/null @@ -1,77 +0,0 @@ -//go:build nrf || nrf51 || nrf52 || nrf528xx || stm32f4 || stm32l4 || stm32wlx || atsamd21 || atsamd51 || atsame5x || rp2040 || rp2350 - -package machine - -import ( - "errors" - "io" - "unsafe" -) - -//go:extern __flash_data_start -var flashDataStart [0]byte - -//go:extern __flash_data_end -var flashDataEnd [0]byte - -// Return the start of the writable flash area, aligned on a page boundary. This -// is usually just after the program and static data. -func FlashDataStart() uintptr { - pagesize := uintptr(eraseBlockSize()) - return (uintptr(unsafe.Pointer(&flashDataStart)) + pagesize - 1) &^ (pagesize - 1) -} - -// Return the end of the writable flash area. Usually this is the address one -// past the end of the on-chip flash. -func FlashDataEnd() uintptr { - return uintptr(unsafe.Pointer(&flashDataEnd)) -} - -var ( - errFlashCannotErasePage = errors.New("cannot erase flash page") - errFlashInvalidWriteLength = errors.New("write flash data must align to correct number of bits") - errFlashNotAllowedWriteData = errors.New("not allowed to write flash data") - errFlashCannotWriteData = errors.New("cannot write flash data") - errFlashCannotReadPastEOF = errors.New("cannot read beyond end of flash data") - errFlashCannotWritePastEOF = errors.New("cannot write beyond end of flash data") - errFlashCannotErasePastEOF = errors.New("cannot erase beyond end of flash data") -) - -// BlockDevice is the raw device that is meant to store flash data. -type BlockDevice interface { - // ReadAt reads the given number of bytes from the block device. - io.ReaderAt - - // WriteAt writes the given number of bytes to the block device. - io.WriterAt - - // Size returns the number of bytes in this block device. - Size() int64 - - // WriteBlockSize returns the block size in which data can be written to - // memory. It can be used by a client to optimize writes, non-aligned writes - // should always work correctly. - WriteBlockSize() int64 - - // EraseBlockSize returns the smallest erasable area on this particular chip - // in bytes. This is used for the block size in EraseBlocks. - // It must be a power of two, and may be as small as 1. A typical size is 4096. - EraseBlockSize() int64 - - // EraseBlocks erases the given number of blocks. An implementation may - // transparently coalesce ranges of blocks into larger bundles if the chip - // supports this. The start and len parameters are in block numbers, use - // EraseBlockSize to map addresses to blocks. - EraseBlocks(start, len int64) error -} - -// pad data if needed so it is long enough for correct byte alignment on writes. -func flashPad(p []byte, writeBlockSize int) []byte { - overflow := len(p) % writeBlockSize - if overflow != 0 { - for i := 0; i < writeBlockSize-overflow; i++ { - p = append(p, 0xff) - } - } - return p -} diff --git a/emb/machine/i2s.go b/emb/machine/i2s.go deleted file mode 100644 index 13dc80f..0000000 --- a/emb/machine/i2s.go +++ /dev/null @@ -1,80 +0,0 @@ -//go:build sam && atsamd21 - -// This is the definition for I2S bus functions. -// Actual implementations if available for any given hardware -// are to be found in its the board definition. -// -// For more info about I2S, see: https://en.wikipedia.org/wiki/I%C2%B2S -// - -package machine - -import "errors" - -// If you are getting a compile error on this line please check to see you've -// correctly implemented the methods on the I2S type. They must match -// the interface method signatures type to type perfectly. -// If not implementing the I2S type please remove your target from the build tags -// at the top of this file. -var _ interface { - SetSampleFrequency(freq uint32) error - ReadMono(b []uint16) (int, error) - ReadStereo(b []uint32) (int, error) - WriteMono(b []uint16) (int, error) - WriteStereo(b []uint32) (int, error) - Enable(enabled bool) -} = (*I2S)(nil) - -type I2SMode uint8 -type I2SStandard uint8 -type I2SClockSource uint8 -type I2SDataFormat uint8 - -const ( - I2SModeSource I2SMode = iota - I2SModeReceiver - I2SModePDM - I2SModeSourceReceiver -) - -const ( - I2StandardPhilips I2SStandard = iota - I2SStandardMSB - I2SStandardLSB -) - -const ( - I2SClockSourceInternal I2SClockSource = iota - I2SClockSourceExternal -) - -const ( - I2SDataFormatDefault I2SDataFormat = 0 - I2SDataFormat8bit = 8 - I2SDataFormat16bit = 16 - I2SDataFormat24bit = 24 - I2SDataFormat32bit = 32 -) - -var ( - ErrInvalidSampleFrequency = errors.New("i2s: invalid sample frequency") -) - -// All fields are optional and may not be required or used on a particular platform. -type I2SConfig struct { - // clock - SCK Pin - // word select - WS Pin - // data out - SDO Pin - // data in - SDI Pin - Mode I2SMode - Standard I2SStandard - ClockSource I2SClockSource - DataFormat I2SDataFormat - AudioFrequency uint32 - MainClockOutput bool - Stereo bool -} diff --git a/emb/machine/machine_atmega.go b/emb/machine/machine_atmega.go deleted file mode 100644 index 7a59e5e..0000000 --- a/emb/machine/machine_atmega.go +++ /dev/null @@ -1,340 +0,0 @@ -//go:build avr && atmega - -package machine - -import ( - "device/avr" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -// I2C on AVR. -type I2C struct { - srReg *volatile.Register8 - brReg *volatile.Register8 - crReg *volatile.Register8 - drReg *volatile.Register8 - - srPS0 byte - srPS1 byte - crEN byte - crINT byte - crSTO byte - crEA byte - crSTA byte -} - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 -} - -// Configure is intended to setup the I2C interface. -func (i2c *I2C) Configure(config I2CConfig) error { - // Default I2C bus speed is 100 kHz. - if config.Frequency == 0 { - config.Frequency = 100 * KHz - } - - // Activate internal pullups for twi. - avr.PORTC.SetBits((avr.DIDR0_ADC4D | avr.DIDR0_ADC5D)) - - return i2c.SetBaudRate(config.Frequency) -} - -// SetBaudRate sets the communication speed for I2C. -func (i2c *I2C) SetBaudRate(br uint32) error { - // Initialize twi prescaler and bit rate. - i2c.srReg.SetBits((i2c.srPS0 | i2c.srPS1)) - - // twi bit rate formula from atmega128 manual pg. 204: - // SCL Frequency = CPU Clock Frequency / (16 + (2 * TWBR)) - // NOTE: TWBR should be 10 or higher for controller mode. - // It is 72 for a 16mhz board with 100kHz TWI - i2c.brReg.Set(uint8(((CPUFrequency() / br) - 16) / 2)) - - // Enable twi module. - i2c.crReg.Set(i2c.crEN) - - return nil -} - -// Tx does a single I2C transaction at the specified address. -// It clocks out the given address, writes the bytes in w, reads back len(r) -// bytes and stores them in r, and generates a stop condition on the bus. -func (i2c *I2C) Tx(addr uint16, w, r []byte) error { - if len(w) != 0 { - i2c.start(uint8(addr), true) // start transmission for writing - for _, b := range w { - i2c.writeByte(b) - } - } - if len(r) != 0 { - i2c.start(uint8(addr), false) // re-start transmission for reading - for i := range r { // read each char - r[i] = i2c.readByte() - } - } - if len(w) != 0 || len(r) != 0 { - // Stop the transmission after it has been started. - i2c.stop() - } - return nil -} - -// start starts an I2C communication session. -func (i2c *I2C) start(address uint8, write bool) { - // Clear TWI interrupt flag, put start condition on SDA, and enable TWI. - i2c.crReg.Set((i2c.crINT | i2c.crSTA | i2c.crEN)) - - // Wait till start condition is transmitted. - for !i2c.crReg.HasBits(i2c.crINT) { - } - - // Write 7-bit shifted peripheral address. - address <<= 1 - if !write { - address |= 1 // set read flag - } - i2c.writeByte(address) -} - -// stop ends an I2C communication session. -func (i2c *I2C) stop() { - // Send stop condition. - i2c.crReg.Set(i2c.crEN | i2c.crINT | i2c.crSTO) - - // Wait for stop condition to be executed on bus. - for !i2c.crReg.HasBits(i2c.crSTO) { - } -} - -// writeByte writes a single byte to the I2C bus. -func (i2c *I2C) writeByte(data byte) error { - // Write data to register. - i2c.drReg.Set(data) - - // Clear TWI interrupt flag and enable TWI. - i2c.crReg.Set(i2c.crEN | i2c.crINT) - - // Wait till data is transmitted. - for !i2c.crReg.HasBits(i2c.crINT) { - } - return nil -} - -// readByte reads a single byte from the I2C bus. -func (i2c *I2C) readByte() byte { - // Clear TWI interrupt flag and enable TWI. - i2c.crReg.Set(i2c.crEN | i2c.crINT | i2c.crEA) - - // Wait till read request is transmitted. - for !i2c.crReg.HasBits(i2c.crINT) { - } - - return byte(i2c.drReg.Get()) -} - -// Always use UART0 as the serial output. -var DefaultUART = UART0 - -// UART -var ( - // UART0 is the hardware serial port on the AVR. - UART0 = &_UART0 - _UART0 = UART{ - Buffer: NewRingBuffer(), - - dataReg: avr.UDR0, - baudRegH: avr.UBRR0H, - baudRegL: avr.UBRR0L, - statusRegA: avr.UCSR0A, - statusRegB: avr.UCSR0B, - statusRegC: avr.UCSR0C, - } -) - -func init() { - // Register the UART interrupt. - interrupt.New(irq_USART0_RX, _UART0.handleInterrupt) -} - -// UART on the AVR. -type UART struct { - Buffer *RingBuffer - - dataReg *volatile.Register8 - baudRegH *volatile.Register8 - baudRegL *volatile.Register8 - - statusRegA *volatile.Register8 - statusRegB *volatile.Register8 - statusRegC *volatile.Register8 -} - -// Configure the UART on the AVR. Defaults to 9600 baud on Arduino. -func (uart *UART) Configure(config UARTConfig) { - if config.BaudRate == 0 { - config.BaudRate = 9600 - } - - // Prescale formula for u2x mode from AVR MiniCore source code. - // Same as formula from specification but taking into account rounding error. - ps := (CPUFrequency()/4/config.BaudRate - 1) / 2 - uart.statusRegA.SetBits(avr.UCSR0A_U2X0) - - // Hardcoded exception for 57600 for compatibility with older bootloaders. - // Also, prescale cannot be > 4095, so switch back to non-u2x mode if the baud rate is too low. - if (CPUFrequency() == 16000000 && config.BaudRate == 57600) || ps > 0xfff { - ps = (CPUFrequency()/8/config.BaudRate - 1) / 2 - uart.statusRegA.ClearBits(avr.UCSR0A_U2X0) - } - - uart.baudRegH.Set(uint8(ps >> 8)) - uart.baudRegL.Set(uint8(ps & 0xff)) - - // enable RX, TX and RX interrupt - uart.statusRegB.Set(avr.UCSR0B_RXEN0 | avr.UCSR0B_TXEN0 | avr.UCSR0B_RXCIE0) - - // 8-bits data - uart.statusRegC.Set(avr.UCSR0C_UCSZ01 | avr.UCSR0C_UCSZ00) -} - -func (uart *UART) handleInterrupt(intr interrupt.Interrupt) { - // Read register to clear it. - data := uart.dataReg.Get() - - // Ensure no error. - if !uart.statusRegA.HasBits(avr.UCSR0A_FE0 | avr.UCSR0A_DOR0 | avr.UCSR0A_UPE0) { - // Put data from UDR register into buffer. - uart.Receive(byte(data)) - } -} - -// WriteByte writes a byte of data to the UART. -func (uart *UART) writeByte(c byte) error { - // Wait until UART buffer is not busy. - for !uart.statusRegA.HasBits(avr.UCSR0A_UDRE0) { - } - uart.dataReg.Set(c) // send char - return nil -} - -func (uart *UART) flush() {} - -// SPIConfig is used to store config info for SPI. -type SPIConfig struct { - Frequency uint32 - LSBFirst bool - Mode uint8 -} - -// SPI is for the Serial Peripheral Interface -// Data is taken from http://ww1.microchip.com/downloads/en/DeviceDoc/ATmega48A-PA-88A-PA-168A-PA-328-P-DS-DS40002061A.pdf page 169 and following -type SPI struct { - // The registers for the SPIx port set by the chip - spcr *volatile.Register8 - spdr *volatile.Register8 - spsr *volatile.Register8 - - spcrR0 byte - spcrR1 byte - spcrCPHA byte - spcrCPOL byte - spcrDORD byte - spcrSPE byte - spcrMSTR byte - - spsrI2X byte - spsrSPIF byte - - // The io pins for the SPIx port set by the chip - sck Pin - sdi Pin - sdo Pin - cs Pin -} - -// Configure is intended to setup the SPI interface. -func (s *SPI) Configure(config SPIConfig) error { - - // This is only here to help catch a bug with the configuration - // where a machine missed a value. - if s.spcr == (*volatile.Register8)(unsafe.Pointer(uintptr(0))) || - s.spsr == (*volatile.Register8)(unsafe.Pointer(uintptr(0))) || - s.spdr == (*volatile.Register8)(unsafe.Pointer(uintptr(0))) || - s.sck == 0 || s.sdi == 0 || s.sdo == 0 || s.cs == 0 { - return errSPIInvalidMachineConfig - } - - // Make the defaults meaningful - if config.Frequency == 0 { - config.Frequency = 4000000 - } - - // Default all port configuration bits to 0 for simplicity - s.spcr.Set(0) - s.spsr.Set(0) - - // Setup pins output configuration - s.sck.Configure(PinConfig{Mode: PinOutput}) - s.sdi.Configure(PinConfig{Mode: PinInput}) - s.sdo.Configure(PinConfig{Mode: PinOutput}) - - // Prevent CS glitches if the pin is enabled Low (0, default) - s.cs.High() - // If the CS pin is not configured as output the SPI port operates in - // slave mode. - s.cs.Configure(PinConfig{Mode: PinOutput}) - - frequencyDivider := CPUFrequency() / config.Frequency - - switch { - case frequencyDivider >= 128: - s.spcr.SetBits(s.spcrR0 | s.spcrR1) - case frequencyDivider >= 64: - s.spcr.SetBits(s.spcrR1) - case frequencyDivider >= 32: - s.spcr.SetBits(s.spcrR1) - s.spsr.SetBits(s.spsrI2X) - case frequencyDivider >= 16: - s.spcr.SetBits(s.spcrR0) - case frequencyDivider >= 8: - s.spcr.SetBits(s.spcrR0) - s.spsr.SetBits(s.spsrI2X) - case frequencyDivider >= 4: - // The clock is already set to all 0's. - default: // defaults to fastest which is /2 - s.spsr.SetBits(s.spsrI2X) - } - - switch config.Mode { - case Mode1: - s.spcr.SetBits(s.spcrCPHA) - case Mode2: - s.spcr.SetBits(s.spcrCPHA) - case Mode3: - s.spcr.SetBits(s.spcrCPHA | s.spcrCPOL) - default: // default is mode 0 - } - - if config.LSBFirst { - s.spcr.SetBits(s.spcrDORD) - } - - // enable SPI, set controller, set clock rate - s.spcr.SetBits(s.spcrSPE | s.spcrMSTR) - - return nil -} - -// Transfer writes the byte into the register and returns the read content -func (s *SPI) Transfer(b byte) (byte, error) { - s.spdr.Set(uint8(b)) - - for !s.spsr.HasBits(s.spsrSPIF) { - } - - return byte(s.spdr.Get()), nil -} diff --git a/emb/machine/machine_atmega1280.go b/emb/machine/machine_atmega1280.go deleted file mode 100644 index ad33dcf..0000000 --- a/emb/machine/machine_atmega1280.go +++ /dev/null @@ -1,937 +0,0 @@ -//go:build avr && atmega1280 - -package machine - -import ( - "device/avr" - "runtime/interrupt" - "runtime/volatile" -) - -const irq_USART0_RX = avr.IRQ_USART0_RX - -const ( - portA Pin = iota * 8 - portB - portC - portD - portE - portF - portG - portH - portJ - portK - portL -) - -const ( - PA0 = portA + 0 - PA1 = portA + 1 - PA2 = portA + 2 - PA3 = portA + 3 - PA4 = portA + 4 - PA5 = portA + 5 - PA6 = portA + 6 - PA7 = portA + 7 - PB0 = portB + 0 - PB1 = portB + 1 - PB2 = portB + 2 - PB3 = portB + 3 - PB4 = portB + 4 // peripherals: Timer2 channel A - PB5 = portB + 5 // peripherals: Timer1 channel A - PB6 = portB + 6 // peripherals: Timer1 channel B - PB7 = portB + 7 // peripherals: Timer0 channel A - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 - PD7 = portD + 7 - PE0 = portE + 0 - PE1 = portE + 1 - PE3 = portE + 3 // peripherals: Timer3 channel A - PE4 = portE + 4 // peripherals: Timer3 channel B - PE5 = portE + 5 // peripherals: Timer3 channel C - PE6 = portE + 6 - PF0 = portF + 0 - PF1 = portF + 1 - PF2 = portF + 2 - PF3 = portF + 3 - PF4 = portF + 4 - PF5 = portF + 5 - PF6 = portF + 6 - PF7 = portF + 7 - PG0 = portG + 0 - PG1 = portG + 1 - PG2 = portG + 2 - PG5 = portG + 5 // peripherals: Timer0 channel B - PH0 = portH + 0 - PH1 = portH + 1 - PH3 = portH + 3 // peripherals: Timer4 channel A - PH4 = portH + 4 // peripherals: Timer4 channel B - PH5 = portH + 5 // peripherals: Timer4 channel C - PH6 = portH + 6 // peripherals: Timer0 channel B - PJ0 = portJ + 0 - PJ1 = portJ + 1 - PK0 = portK + 0 - PK1 = portK + 1 - PK2 = portK + 2 - PK3 = portK + 3 - PK4 = portK + 4 - PK5 = portK + 5 - PK6 = portK + 6 - PK7 = portK + 7 - PL0 = portL + 0 - PL1 = portL + 1 - PL2 = portL + 2 - PL3 = portL + 3 // peripherals: Timer5 channel A - PL4 = portL + 4 // peripherals: Timer5 channel B - PL5 = portL + 5 // peripherals: Timer5 channel C - PL6 = portL + 6 - PL7 = portL + 7 -) - -// getPortMask returns the PORTx register and mask for the pin. -func (p Pin) getPortMask() (*volatile.Register8, uint8) { - switch { - case p >= PA0 && p <= PA7: - return avr.PORTA, 1 << uint8(p-portA) - case p >= PB0 && p <= PB7: - return avr.PORTB, 1 << uint8(p-portB) - case p >= PC0 && p <= PC7: - return avr.PORTC, 1 << uint8(p-portC) - case p >= PD0 && p <= PD7: - return avr.PORTD, 1 << uint8(p-portD) - case p >= PE0 && p <= PE6: - return avr.PORTE, 1 << uint8(p-portE) - case p >= PF0 && p <= PF7: - return avr.PORTF, 1 << uint8(p-portF) - case p >= PG0 && p <= PG5: - return avr.PORTG, 1 << uint8(p-portG) - case p >= PH0 && p <= PH6: - return avr.PORTH, 1 << uint8(p-portH) - case p >= PJ0 && p <= PJ1: - return avr.PORTJ, 1 << uint8(p-portJ) - case p >= PK0 && p <= PK7: - return avr.PORTK, 1 << uint8(p-portK) - case p >= PL0 && p <= PL7: - return avr.PORTL, 1 << uint8(p-portL) - default: - return avr.PORTA, 255 - } -} - -// PWM is one PWM peripheral, which consists of a counter and two output -// channels (that can be connected to two fixed pins). You can set the frequency -// using SetPeriod, but only for all the channels in this PWM peripheral at -// once. -type PWM struct { - num uint8 -} - -var ( - Timer0 = PWM{0} // 8 bit timer for PB7 and PG5 - Timer1 = PWM{1} // 16 bit timer for PB5 and PB6 - Timer2 = PWM{2} // 8 bit timer for PB4 and PH6 - Timer3 = PWM{3} // 16 bit timer for PE3, PE4 and PE5 - Timer4 = PWM{4} // 16 bit timer for PH3, PH4 and PH5 - Timer5 = PWM{5} // 16 bit timer for PL3, PL4 and PL5 -) - -// Configure enables and configures this PWM. -// -// For the two 8 bit timers, there is only a limited number of periods -// available, namely the CPU frequency divided by 256 and again divided by 1, 8, -// 64, 256, or 1024. For a MCU running at 16MHz, this would be a period of 16µs, -// 128µs, 1024µs, 4096µs, or 16384µs. -func (pwm PWM) Configure(config PWMConfig) error { - - switch pwm.num { - case 0, 2: // 8-bit timers (Timer/counter 0 and Timer/counter 2) - // Calculate the timer prescaler. - // While we could configure a flexible top, that would sacrifice one of - // the PWM output compare registers and thus a PWM channel. I've chosen - // to instead limit this timer to a fixed number of frequencies. - var prescaler uint8 - switch config.Period { - case 0, (uint64(1e9) * 256 * 1) / uint64(CPUFrequency()): - prescaler = 1 - case (uint64(1e9) * 256 * 8) / uint64(CPUFrequency()): - prescaler = 2 - case (uint64(1e9) * 256 * 64) / uint64(CPUFrequency()): - prescaler = 3 - case (uint64(1e9) * 256 * 256) / uint64(CPUFrequency()): - prescaler = 4 - case (uint64(1e9) * 256 * 1024) / uint64(CPUFrequency()): - prescaler = 5 - default: - return ErrPWMPeriodTooLong - } - - if pwm.num == 0 { - avr.TCCR0B.Set(prescaler) - // Set the PWM mode to fast PWM (mode = 3). - avr.TCCR0A.Set(avr.TCCR0A_WGM00 | avr.TCCR0A_WGM01) - // monotonic timer is using the same time as PWM:0 - // we must adjust internal settings of monotonic timer when PWM:0 settings changed - adjustMonotonicTimer() - } else { - avr.TCCR2B.Set(prescaler) - // Set the PWM mode to fast PWM (mode = 3). - avr.TCCR2A.Set(avr.TCCR2A_WGM20 | avr.TCCR2A_WGM21) - } - case 1, 3, 4, 5: - // The top value is the number of PWM ticks a PWM period takes. It is - // initially picked assuming an unlimited counter top and no PWM - // prescaler. - var top uint64 - if config.Period == 0 { - // Use a top appropriate for LEDs. Picking a relatively low period - // here (0xff) for consistency with the other timers. - top = 0xff - } else { - // The formula below calculates the following formula, optimized: - // top = period * (CPUFrequency() / 1e9) - // By dividing the CPU frequency first (an operation that is easily - // optimized away) the period has less chance of overflowing. - top = config.Period * (uint64(CPUFrequency()) / 1000000) / 1000 - } - - // The ideal PWM period may be larger than would fit in the PWM counter, - // which is 16 bits (see maxTop). Therefore, try to make the PWM clock - // speed lower with a prescaler to make the top value fit the maximum - // top value. - - const maxTop = 0x10000 - var prescalingTop uint8 - switch { - case top <= maxTop: - prescalingTop = 3<<3 | 1 // no prescaling - case top/8 <= maxTop: - prescalingTop = 3<<3 | 2 // divide by 8 - top /= 8 - case top/64 <= maxTop: - prescalingTop = 3<<3 | 3 // divide by 64 - top /= 64 - case top/256 <= maxTop: - prescalingTop = 3<<3 | 4 // divide by 256 - top /= 256 - case top/1024 <= maxTop: - prescalingTop = 3<<3 | 5 // divide by 1024 - top /= 1024 - default: - return ErrPWMPeriodTooLong - } - - // A top of 0x10000 is at 100% duty cycle. Subtract one because the - // counter counts from 0, not 1 (avoiding an off-by-one). - top -= 1 - - switch pwm.num { - case 1: - avr.TCCR1A.Set(avr.TCCR1A_WGM11) - avr.TCCR1B.Set(prescalingTop) - avr.ICR1H.Set(uint8(top >> 8)) - avr.ICR1L.Set(uint8(top)) - case 3: - avr.TCCR3A.Set(avr.TCCR3A_WGM31) - avr.TCCR3B.Set(prescalingTop) - avr.ICR3H.Set(uint8(top >> 8)) - avr.ICR3L.Set(uint8(top)) - case 4: - avr.TCCR4A.Set(avr.TCCR4A_WGM41) - avr.TCCR4B.Set(prescalingTop) - avr.ICR4H.Set(uint8(top >> 8)) - avr.ICR4L.Set(uint8(top)) - case 5: - avr.TCCR5A.Set(avr.TCCR5A_WGM51) - avr.TCCR5B.Set(prescalingTop) - avr.ICR5H.Set(uint8(top >> 8)) - avr.ICR5L.Set(uint8(top)) - } - } - return nil -} - -// SetPeriod updates the period of this PWM peripheral. -// To set a particular frequency, use the following formula: -// -// period = 1e9 / frequency -// -// If you use a period of 0, a period that works well for LEDs will be picked. -// -// SetPeriod will not change the prescaler, but also won't change the current -// value in any of the channels. This means that you may need to update the -// value for the particular channel. -// -// Note that you cannot pick any arbitrary period after the PWM peripheral has -// been configured. If you want to switch between frequencies, pick the lowest -// frequency (longest period) once when calling Configure and adjust the -// frequency here as needed. -func (pwm PWM) SetPeriod(period uint64) error { - if pwm.num == 0 || pwm.num == 2 { - return ErrPWMPeriodTooLong // TODO better error message - } - - // The top value is the number of PWM ticks a PWM period takes. It is - // initially picked assuming an unlimited counter top and no PWM - // prescaler. - var top uint64 - if period == 0 { - // Use a top appropriate for LEDs. Picking a relatively low period - // here (0xff) for consistency with the other timers. - top = 0xff - } else { - // The formula below calculates the following formula, optimized: - // top = period * (CPUFrequency() / 1e9) - // By dividing the CPU frequency first (an operation that is easily - // optimized away) the period has less chance of overflowing. - top = period * (uint64(CPUFrequency()) / 1000000) / 1000 - } - - var prescaler uint8 - - switch pwm.num { - case 1: - prescaler = avr.TCCR1B.Get() & 0x7 - case 3: - prescaler = avr.TCCR3B.Get() & 0x7 - case 4: - prescaler = avr.TCCR4B.Get() & 0x7 - case 5: - prescaler = avr.TCCR5B.Get() & 0x7 - } - - switch prescaler { - case 1: - top /= 1 - case 2: - top /= 8 - case 3: - top /= 64 - case 4: - top /= 256 - case 5: - top /= 1024 - } - - // A top of 0x10000 is at 100% duty cycle. Subtract one because the counter - // counts from 0, not 1 (avoiding an off-by-one). - top -= 1 - - if top > 0xffff { - return ErrPWMPeriodTooLong - } - - switch pwm.num { - case 1: - // Warning: this change is not atomic! - avr.ICR1H.Set(uint8(top >> 8)) - avr.ICR1L.Set(uint8(top)) - - // ... and because of that, set the counter back to zero to avoid most of - // the effects of this non-atomicity. - avr.TCNT1H.Set(0) - avr.TCNT1L.Set(0) - case 3: - // Warning: this change is not atomic! - avr.ICR3H.Set(uint8(top >> 8)) - avr.ICR3L.Set(uint8(top)) - - // ... and because of that, set the counter back to zero to avoid most of - // the effects of this non-atomicity. - avr.TCNT3H.Set(0) - avr.TCNT3L.Set(0) - case 4: - // Warning: this change is not atomic! - avr.ICR4H.Set(uint8(top >> 8)) - avr.ICR4L.Set(uint8(top)) - - // ... and because of that, set the counter back to zero to avoid most of - // the effects of this non-atomicity. - avr.TCNT4H.Set(0) - avr.TCNT4L.Set(0) - case 5: - // Warning: this change is not atomic! - avr.ICR5H.Set(uint8(top >> 8)) - avr.ICR5L.Set(uint8(top)) - - // ... and because of that, set the counter back to zero to avoid most of - // the effects of this non-atomicity. - avr.TCNT5H.Set(0) - avr.TCNT5L.Set(0) - } - - return nil -} - -// Top returns the current counter top, for use in duty cycle calculation. It -// will only change with a call to Configure or SetPeriod, otherwise it is -// constant. -// -// The value returned here is hardware dependent. In general, it's best to treat -// it as an opaque value that can be divided by some number and passed to Set -// (see Set documentation for more information). -func (pwm PWM) Top() uint32 { - switch pwm.num { - case 1: - // Timer 1 has a configurable top value. - low := avr.ICR1L.Get() - high := avr.ICR1H.Get() - return uint32(high)<<8 | uint32(low) + 1 - case 3: - // Timer 3 has a configurable top value. - low := avr.ICR3L.Get() - high := avr.ICR3H.Get() - return uint32(high)<<8 | uint32(low) + 1 - case 4: - // Timer 4 has a configurable top value. - low := avr.ICR4L.Get() - high := avr.ICR4H.Get() - return uint32(high)<<8 | uint32(low) + 1 - case 5: - // Timer 5 has a configurable top value. - low := avr.ICR5L.Get() - high := avr.ICR5H.Get() - return uint32(high)<<8 | uint32(low) + 1 - } - - // Other timers go from 0 to 0xff (0x100 or 256 in total). - return 256 -} - -// Counter returns the current counter value of the timer in this PWM -// peripheral. It may be useful for debugging. -func (pwm PWM) Counter() uint32 { - switch pwm.num { - case 0: - return uint32(avr.TCNT0.Get()) - case 1: - mask := interrupt.Disable() - low := avr.TCNT1L.Get() - high := avr.TCNT1H.Get() - interrupt.Restore(mask) - return uint32(high)<<8 | uint32(low) - case 2: - return uint32(avr.TCNT2.Get()) - case 3: - mask := interrupt.Disable() - low := avr.TCNT3L.Get() - high := avr.TCNT3H.Get() - interrupt.Restore(mask) - return uint32(high)<<8 | uint32(low) - case 4: - mask := interrupt.Disable() - low := avr.TCNT4L.Get() - high := avr.TCNT4H.Get() - interrupt.Restore(mask) - return uint32(high)<<8 | uint32(low) - case 5: - mask := interrupt.Disable() - low := avr.TCNT5L.Get() - high := avr.TCNT5H.Get() - interrupt.Restore(mask) - return uint32(high)<<8 | uint32(low) - } - - // Unknown PWM. - return 0 -} - -// Period returns the used PWM period in nanoseconds. It might deviate slightly -// from the configured period due to rounding. -func (pwm PWM) Period() uint64 { - var prescaler uint8 - switch pwm.num { - case 0: - prescaler = avr.TCCR0B.Get() & 0x7 - case 1: - prescaler = avr.TCCR1B.Get() & 0x7 - case 2: - prescaler = avr.TCCR2B.Get() & 0x7 - case 3: - prescaler = avr.TCCR3B.Get() & 0x7 - case 4: - prescaler = avr.TCCR4B.Get() & 0x7 - case 5: - prescaler = avr.TCCR5B.Get() & 0x7 - } - top := uint64(pwm.Top()) - switch prescaler { - case 1: // prescaler 1 - return 1 * top * 1000 / uint64(CPUFrequency()/1e6) - case 2: // prescaler 8 - return 8 * top * 1000 / uint64(CPUFrequency()/1e6) - case 3: // prescaler 64 - return 64 * top * 1000 / uint64(CPUFrequency()/1e6) - case 4: // prescaler 256 - return 256 * top * 1000 / uint64(CPUFrequency()/1e6) - case 5: // prescaler 1024 - return 1024 * top * 1000 / uint64(CPUFrequency()/1e6) - default: // unknown clock source - return 0 - } -} - -// Channel returns a PWM channel for the given pin. -func (pwm PWM) Channel(pin Pin) (uint8, error) { - pin.Configure(PinConfig{Mode: PinOutput}) - pin.Low() - switch pwm.num { - case 0: - switch pin { - case PB7: // channel A - avr.TCCR0A.SetBits(avr.TCCR0A_COM0A1) - return 0, nil - case PG5: // channel B - avr.TCCR0A.SetBits(avr.TCCR0A_COM0B1) - return 1, nil - } - case 1: - switch pin { - case PB5: // channel A - avr.TCCR1A.SetBits(avr.TCCR1A_COM1A1) - return 0, nil - case PB6: // channel B - avr.TCCR1A.SetBits(avr.TCCR1A_COM1B1) - return 1, nil - } - case 2: - switch pin { - case PB4: // channel A - avr.TCCR2A.SetBits(avr.TCCR2A_COM2A1) - return 0, nil - case PH6: // channel B - avr.TCCR2A.SetBits(avr.TCCR2A_COM2B1) - return 1, nil - } - case 3: - switch pin { - case PE3: // channel A - avr.TCCR3A.SetBits(avr.TCCR3A_COM3A1) - return 0, nil - case PE4: //channel B - avr.TCCR3A.SetBits(avr.TCCR3A_COM3B1) - return 1, nil - case PE5: //channel C - avr.TCCR3A.SetBits(avr.TCCR3A_COM3C1) - return 2, nil - } - case 4: - switch pin { - case PH3: // channel A - avr.TCCR4A.SetBits(avr.TCCR4A_COM4A1) - return 0, nil - case PH4: //channel B - avr.TCCR4A.SetBits(avr.TCCR4A_COM4B1) - return 1, nil - case PH5: //channel C - avr.TCCR4A.SetBits(avr.TCCR4A_COM4C1) - return 2, nil - } - case 5: - switch pin { - case PL3: // channel A - avr.TCCR5A.SetBits(avr.TCCR5A_COM5A1) - return 0, nil - case PL4: //channel B - avr.TCCR5A.SetBits(avr.TCCR5A_COM5B1) - return 1, nil - case PL5: //channel C - avr.TCCR5A.SetBits(avr.TCCR5A_COM5C1) - return 2, nil - } - } - return 0, ErrInvalidOutputPin -} - -// SetInverting sets whether to invert the output of this channel. -// Without inverting, a 25% duty cycle would mean the output is high for 25% of -// the time and low for the rest. Inverting flips the output as if a NOT gate -// was placed at the output, meaning that the output would be 25% low and 75% -// high with a duty cycle of 25%. -// -// Note: the invert state may not be applied on the AVR until the next call to -// ch.Set(). -func (pwm PWM) SetInverting(channel uint8, inverting bool) { - switch pwm.num { - case 0: - switch channel { - case 0: // channel A, PB7 - if inverting { - avr.PORTB.SetBits(1 << 7) // PB7 high - avr.TCCR0A.SetBits(avr.TCCR0A_COM0A0) - } else { - avr.PORTB.ClearBits(1 << 7) // PB7 low - avr.TCCR0A.ClearBits(avr.TCCR0A_COM0A0) - } - case 1: // channel B, PG5 - if inverting { - avr.PORTG.SetBits(1 << 5) // PG5 high - avr.TCCR0A.SetBits(avr.TCCR0A_COM0B0) - } else { - avr.PORTG.ClearBits(1 << 5) // PG5 low - avr.TCCR0A.ClearBits(avr.TCCR0A_COM0B0) - } - } - case 1: - // Note: the COM1A0/COM1B0 bit is not set with the configuration below. - // It will be set the following call to Set(), however. - switch channel { - case 0: // channel A, PB5 - if inverting { - avr.PORTB.SetBits(1 << 5) // PB5 high - } else { - avr.PORTB.ClearBits(1 << 5) // PB5 low - } - case 1: // channel B, PB6 - if inverting { - avr.PORTB.SetBits(1 << 6) // PB6 high - } else { - avr.PORTB.ClearBits(1 << 6) // PB6 low - } - } - case 2: - switch channel { - case 0: // channel A, PB4 - if inverting { - avr.PORTB.SetBits(1 << 4) // PB4 high - avr.TCCR2A.SetBits(avr.TCCR2A_COM2A0) - } else { - avr.PORTB.ClearBits(1 << 4) // PB4 low - avr.TCCR2A.ClearBits(avr.TCCR2A_COM2A0) - } - case 1: // channel B, PH6 - if inverting { - avr.PORTH.SetBits(1 << 6) // PH6 high - avr.TCCR2A.SetBits(avr.TCCR2A_COM2B0) - } else { - avr.PORTH.ClearBits(1 << 6) // PH6 low - avr.TCCR2A.ClearBits(avr.TCCR2A_COM2B0) - } - } - case 3: - // Note: the COM3A0/COM3B0 bit is not set with the configuration below. - // It will be set the following call to Set(), however. - switch channel { - case 0: // channel A, PE3 - if inverting { - avr.PORTE.SetBits(1 << 3) // PE3 high - } else { - avr.PORTE.ClearBits(1 << 3) // PE3 low - } - case 1: // channel B, PE4 - if inverting { - avr.PORTE.SetBits(1 << 4) // PE4 high - } else { - avr.PORTE.ClearBits(1 << 4) // PE4 low - } - case 2: // channel C, PE5 - if inverting { - avr.PORTE.SetBits(1 << 5) // PE4 high - } else { - avr.PORTE.ClearBits(1 << 5) // PE4 low - } - } - case 4: - // Note: the COM3A0/COM3B0 bit is not set with the configuration below. - // It will be set the following call to Set(), however. - switch channel { - case 0: // channel A, PH3 - if inverting { - avr.PORTH.SetBits(1 << 3) // PH3 high - } else { - avr.PORTH.ClearBits(1 << 3) // PH3 low - } - case 1: // channel B, PH4 - if inverting { - avr.PORTH.SetBits(1 << 4) // PH4 high - } else { - avr.PORTH.ClearBits(1 << 4) // PH4 low - } - case 2: // channel C, PH5 - if inverting { - avr.PORTH.SetBits(1 << 5) // PH4 high - } else { - avr.PORTH.ClearBits(1 << 5) // PH4 low - } - } - case 5: - // Note: the COM3A0/COM3B0 bit is not set with the configuration below. - // It will be set the following call to Set(), however. - switch channel { - case 0: // channel A, PL3 - if inverting { - avr.PORTL.SetBits(1 << 3) // PL3 high - } else { - avr.PORTL.ClearBits(1 << 3) // PL3 low - } - case 1: // channel B, PL4 - if inverting { - avr.PORTL.SetBits(1 << 4) // PL4 high - } else { - avr.PORTL.ClearBits(1 << 4) // PL4 low - } - case 2: // channel C, PH5 - if inverting { - avr.PORTL.SetBits(1 << 5) // PL4 high - } else { - avr.PORTL.ClearBits(1 << 5) // PL4 low - } - } - } -} - -// Set updates the channel value. This is used to control the channel duty -// cycle, in other words the fraction of time the channel output is high (or low -// when inverted). For example, to set it to a 25% duty cycle, use: -// -// pwm.Set(channel, pwm.Top() / 4) -// -// pwm.Set(channel, 0) will set the output to low and pwm.Set(channel, -// pwm.Top()) will set the output to high, assuming the output isn't inverted. -func (pwm PWM) Set(channel uint8, value uint32) { - switch pwm.num { - case 0: - value := uint16(value) - switch channel { - case 0: // channel A - if value == 0 { - avr.TCCR0A.ClearBits(avr.TCCR0A_COM0A1) - } else { - avr.OCR0A.Set(uint8(value - 1)) - avr.TCCR0A.SetBits(avr.TCCR0A_COM0A1) - } - case 1: // channel B - if value == 0 { - avr.TCCR0A.ClearBits(avr.TCCR0A_COM0B1) - } else { - avr.OCR0B.Set(uint8(value) - 1) - avr.TCCR0A.SetBits(avr.TCCR0A_COM0B1) - } - } - // monotonic timer is using the same time as PWM:0 - // we must adjust internal settings of monotonic timer when PWM:0 settings changed - adjustMonotonicTimer() - case 1: - mask := interrupt.Disable() - switch channel { - case 0: // channel A, PB5 - if value == 0 { - avr.TCCR1A.ClearBits(avr.TCCR1A_COM1A1 | avr.TCCR1A_COM1A0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR1AH.Set(uint8(value >> 8)) - avr.OCR1AL.Set(uint8(value)) - if avr.PORTB.HasBits(1 << 5) { // is PB1 high? - // Yes, set the inverting bit. - avr.TCCR1A.SetBits(avr.TCCR1A_COM1A1 | avr.TCCR1A_COM1A0) - } else { - // No, output is non-inverting. - avr.TCCR1A.SetBits(avr.TCCR1A_COM1A1) - } - } - case 1: // channel B, PB6 - if value == 0 { - avr.TCCR1A.ClearBits(avr.TCCR1A_COM1B1 | avr.TCCR1A_COM1B0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR1BH.Set(uint8(value >> 8)) - avr.OCR1BL.Set(uint8(value)) - if avr.PORTB.HasBits(1 << 6) { // is PB6 high? - // Yes, set the inverting bit. - avr.TCCR1A.SetBits(avr.TCCR1A_COM1B1 | avr.TCCR1A_COM1B0) - } else { - // No, output is non-inverting. - avr.TCCR1A.SetBits(avr.TCCR1A_COM1B1) - } - } - } - interrupt.Restore(mask) - case 2: - value := uint16(value) - switch channel { - case 0: // channel A - if value == 0 { - avr.TCCR2A.ClearBits(avr.TCCR2A_COM2A1) - } else { - avr.OCR2A.Set(uint8(value - 1)) - avr.TCCR2A.SetBits(avr.TCCR2A_COM2A1) - } - case 1: // channel B - if value == 0 { - avr.TCCR2A.ClearBits(avr.TCCR2A_COM2B1) - } else { - avr.OCR2B.Set(uint8(value - 1)) - avr.TCCR2A.SetBits(avr.TCCR2A_COM2B1) - } - } - case 3: - mask := interrupt.Disable() - switch channel { - case 0: // channel A, PE3 - if value == 0 { - avr.TCCR3A.ClearBits(avr.TCCR3A_COM3A1 | avr.TCCR3A_COM3A0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR3AH.Set(uint8(value >> 8)) - avr.OCR3AL.Set(uint8(value)) - if avr.PORTE.HasBits(1 << 3) { // is PE3 high? - // Yes, set the inverting bit. - avr.TCCR3A.SetBits(avr.TCCR3A_COM3A1 | avr.TCCR3A_COM3A0) - } else { - // No, output is non-inverting. - avr.TCCR3A.SetBits(avr.TCCR3A_COM3A1) - } - } - case 1: // channel B, PE4 - if value == 0 { - avr.TCCR3A.ClearBits(avr.TCCR3A_COM3B1 | avr.TCCR3A_COM3B0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR3BH.Set(uint8(value >> 8)) - avr.OCR3BL.Set(uint8(value)) - if avr.PORTE.HasBits(1 << 4) { // is PE4 high? - // Yes, set the inverting bit. - avr.TCCR3A.SetBits(avr.TCCR3A_COM3B1 | avr.TCCR3A_COM3B0) - } else { - // No, output is non-inverting. - avr.TCCR3A.SetBits(avr.TCCR3A_COM3B1) - } - } - case 2: // channel C, PE5 - if value == 0 { - avr.TCCR3A.ClearBits(avr.TCCR3A_COM3C1 | avr.TCCR3A_COM3C0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR3CH.Set(uint8(value >> 8)) - avr.OCR3CL.Set(uint8(value)) - if avr.PORTE.HasBits(1 << 5) { // is PE5 high? - // Yes, set the inverting bit. - avr.TCCR3A.SetBits(avr.TCCR3A_COM3C1 | avr.TCCR3A_COM3C0) - } else { - // No, output is non-inverting. - avr.TCCR3A.SetBits(avr.TCCR3A_COM3C1) - } - } - } - interrupt.Restore(mask) - case 4: - mask := interrupt.Disable() - switch channel { - case 0: // channel A, PH3 - if value == 0 { - avr.TCCR4A.ClearBits(avr.TCCR4A_COM4A1 | avr.TCCR4A_COM4A0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR4AH.Set(uint8(value >> 8)) - avr.OCR4AL.Set(uint8(value)) - if avr.PORTH.HasBits(1 << 3) { // is PH3 high? - // Yes, set the inverting bit. - avr.TCCR4A.SetBits(avr.TCCR4A_COM4A1 | avr.TCCR4A_COM4A0) - } else { - // No, output is non-inverting. - avr.TCCR4A.SetBits(avr.TCCR4A_COM4A1) - } - } - case 1: // channel B, PH4 - if value == 0 { - avr.TCCR4A.ClearBits(avr.TCCR4A_COM4B1 | avr.TCCR4A_COM4B0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR4BH.Set(uint8(value >> 8)) - avr.OCR4BL.Set(uint8(value)) - if avr.PORTH.HasBits(1 << 4) { // is PH4 high? - // Yes, set the inverting bit. - avr.TCCR4A.SetBits(avr.TCCR4A_COM4B1 | avr.TCCR4A_COM4B0) - } else { - // No, output is non-inverting. - avr.TCCR4A.SetBits(avr.TCCR4A_COM4B1) - } - } - case 2: // channel C, PH5 - if value == 0 { - avr.TCCR4A.ClearBits(avr.TCCR4A_COM4C1 | avr.TCCR4A_COM4C0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR4CH.Set(uint8(value >> 8)) - avr.OCR4CL.Set(uint8(value)) - if avr.PORTH.HasBits(1 << 5) { // is PH5 high? - // Yes, set the inverting bit. - avr.TCCR4A.SetBits(avr.TCCR4A_COM4C1 | avr.TCCR4A_COM4C0) - } else { - // No, output is non-inverting. - avr.TCCR4A.SetBits(avr.TCCR4A_COM4C1) - } - } - } - interrupt.Restore(mask) - case 5: - mask := interrupt.Disable() - switch channel { - case 0: // channel A, PL3 - if value == 0 { - avr.TCCR5A.ClearBits(avr.TCCR5A_COM5A1 | avr.TCCR5A_COM5A0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR5AH.Set(uint8(value >> 8)) - avr.OCR5AL.Set(uint8(value)) - if avr.PORTL.HasBits(1 << 3) { // is PL3 high? - // Yes, set the inverting bit. - avr.TCCR5A.SetBits(avr.TCCR5A_COM5A1 | avr.TCCR5A_COM5A0) - } else { - // No, output is non-inverting. - avr.TCCR5A.SetBits(avr.TCCR5A_COM5A1) - } - } - case 1: // channel B, PL4 - if value == 0 { - avr.TCCR5A.ClearBits(avr.TCCR5A_COM5B1 | avr.TCCR5A_COM5B0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR5BH.Set(uint8(value >> 8)) - avr.OCR5BL.Set(uint8(value)) - if avr.PORTL.HasBits(1 << 4) { // is PL4 high? - // Yes, set the inverting bit. - avr.TCCR5A.SetBits(avr.TCCR5A_COM5B1 | avr.TCCR5A_COM5B0) - } else { - // No, output is non-inverting. - avr.TCCR5A.SetBits(avr.TCCR5A_COM5B1) - } - } - case 2: // channel C, PL5 - if value == 0 { - avr.TCCR5A.ClearBits(avr.TCCR5A_COM5C1 | avr.TCCR5A_COM5C0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR5CH.Set(uint8(value >> 8)) - avr.OCR5CL.Set(uint8(value)) - if avr.PORTL.HasBits(1 << 5) { // is PL5 high? - // Yes, set the inverting bit. - avr.TCCR5A.SetBits(avr.TCCR5A_COM5C1 | avr.TCCR5A_COM5C0) - } else { - // No, output is non-inverting. - avr.TCCR5A.SetBits(avr.TCCR5A_COM5C1) - } - } - } - interrupt.Restore(mask) - } -} - -// SPI configuration -var SPI0 = &SPI{ - spcr: avr.SPCR, - spdr: avr.SPDR, - spsr: avr.SPSR, - sck: PB1, - sdo: PB2, - sdi: PB3, - cs: PB0} diff --git a/emb/machine/machine_atmega1284p.go b/emb/machine/machine_atmega1284p.go deleted file mode 100644 index db8fd65..0000000 --- a/emb/machine/machine_atmega1284p.go +++ /dev/null @@ -1,81 +0,0 @@ -//go:build avr && atmega1284p - -package machine - -import ( - "device/avr" - "runtime/volatile" -) - -const irq_USART0_RX = avr.IRQ_USART0_RX - -// Return the current CPU frequency in hertz. -func CPUFrequency() uint32 { - return 20000000 -} - -const ( - portA Pin = iota * 8 - portB - portC - portD -) - -const ( - PA0 = portA + 0 - PA1 = portA + 1 - PA2 = portA + 2 - PA3 = portA + 3 - PA4 = portA + 4 - PA5 = portA + 5 - PA6 = portA + 6 - PA7 = portA + 7 - PB0 = portB + 0 - PB1 = portB + 1 - PB2 = portB + 2 - PB3 = portB + 3 - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 - PD4 = portD + 4 - PD5 = portD + 5 - PD6 = portD + 6 - PD7 = portD + 7 -) - -// getPortMask returns the PORTx register and mask for the pin. -func (p Pin) getPortMask() (*volatile.Register8, uint8) { - switch { - case p >= PA0 && p <= PA7: - return avr.PORTA, 1 << uint8(p-portA) - case p >= PB0 && p <= PB7: - return avr.PORTB, 1 << uint8(p-portB) - case p >= PC0 && p <= PC7: - return avr.PORTC, 1 << uint8(p-portC) - default: - return avr.PORTD, 1 << uint8(p-portD) - } -} - -// SPI configuration -var SPI0 = &SPI{ - spcr: avr.SPCR, - spsr: avr.SPSR, - spdr: avr.SPDR, - sck: PB7, - sdo: PB5, - sdi: PB6, - cs: PB4} diff --git a/emb/machine/machine_atmega2560.go b/emb/machine/machine_atmega2560.go deleted file mode 100644 index ede862a..0000000 --- a/emb/machine/machine_atmega2560.go +++ /dev/null @@ -1,141 +0,0 @@ -//go:build avr && atmega2560 - -package machine - -import ( - "device/avr" - "runtime/volatile" -) - -const irq_USART0_RX = avr.IRQ_USART0_RX -const irq_USART1_RX = avr.IRQ_USART1_RX -const irq_USART2_RX = avr.IRQ_USART2_RX -const irq_USART3_RX = avr.IRQ_USART3_RX - -const ( - portA Pin = iota * 8 - portB - portC - portD - portE - portF - portG - portH - portJ - portK - portL -) - -const ( - PA0 = portA + 0 - PA1 = portA + 1 - PA2 = portA + 2 - PA3 = portA + 3 - PA4 = portA + 4 - PA5 = portA + 5 - PA6 = portA + 6 - PA7 = portA + 7 - PB0 = portB + 0 - PB1 = portB + 1 - PB2 = portB + 2 - PB3 = portB + 3 - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 - PD7 = portD + 7 - PE0 = portE + 0 - PE1 = portE + 1 - PE3 = portE + 3 - PE4 = portE + 4 - PE5 = portE + 5 - PE6 = portE + 6 - PF0 = portF + 0 - PF1 = portF + 1 - PF2 = portF + 2 - PF3 = portF + 3 - PF4 = portF + 4 - PF5 = portF + 5 - PF6 = portF + 6 - PF7 = portF + 7 - PG0 = portG + 0 - PG1 = portG + 1 - PG2 = portG + 2 - PG5 = portG + 5 - PH0 = portH + 0 - PH1 = portH + 1 - PH3 = portH + 3 - PH4 = portH + 4 - PH5 = portH + 5 - PH6 = portH + 6 - PJ0 = portJ + 0 - PJ1 = portJ + 1 - PK0 = portK + 0 - PK1 = portK + 1 - PK2 = portK + 2 - PK3 = portK + 3 - PK4 = portK + 4 - PK5 = portK + 5 - PK6 = portK + 6 - PK7 = portK + 7 - PL0 = portL + 0 - PL1 = portL + 1 - PL2 = portL + 2 - PL3 = portL + 3 - PL4 = portL + 4 - PL5 = portL + 5 - PL6 = portL + 6 - PL7 = portL + 7 -) - -// getPortMask returns the PORTx register and mask for the pin. -func (p Pin) getPortMask() (*volatile.Register8, uint8) { - switch { - case p >= PA0 && p <= PA7: - return avr.PORTA, 1 << uint8(p-portA) - case p >= PB0 && p <= PB7: - return avr.PORTB, 1 << uint8(p-portB) - case p >= PC0 && p <= PC7: - return avr.PORTC, 1 << uint8(p-portC) - case p >= PD0 && p <= PD7: - return avr.PORTD, 1 << uint8(p-portD) - case p >= PE0 && p <= PE6: - return avr.PORTE, 1 << uint8(p-portE) - case p >= PF0 && p <= PF7: - return avr.PORTF, 1 << uint8(p-portF) - case p >= PG0 && p <= PG5: - return avr.PORTG, 1 << uint8(p-portG) - case p >= PH0 && p <= PH6: - return avr.PORTH, 1 << uint8(p-portH) - case p >= PJ0 && p <= PJ1: - return avr.PORTJ, 1 << uint8(p-portJ) - case p >= PK0 && p <= PK7: - return avr.PORTK, 1 << uint8(p-portK) - case p >= PL0 && p <= PL7: - return avr.PORTL, 1 << uint8(p-portL) - default: - return avr.PORTA, 255 - } -} - -// SPI configuration -var SPI0 = &SPI{ - spcr: avr.SPCR, - spdr: avr.SPDR, - spsr: avr.SPSR, - sck: PB1, - sdo: PB2, - sdi: PB3, - cs: PB0} diff --git a/emb/machine/machine_atmega328.go b/emb/machine/machine_atmega328.go deleted file mode 100644 index c354ccb..0000000 --- a/emb/machine/machine_atmega328.go +++ /dev/null @@ -1,548 +0,0 @@ -//go:build avr && (atmega328p || atmega328pb) - -package machine - -import ( - "device/avr" - "runtime/interrupt" - "runtime/volatile" -) - -// PWM is one PWM peripheral, which consists of a counter and two output -// channels (that can be connected to two fixed pins). You can set the frequency -// using SetPeriod, but only for all the channels in this PWM peripheral at -// once. -type PWM struct { - num uint8 -} - -var ( - Timer0 = PWM{0} // 8 bit timer for PD5 and PD6 - Timer1 = PWM{1} // 16 bit timer for PB1 and PB2 - Timer2 = PWM{2} // 8 bit timer for PB3 and PD3 -) - -// Configure enables and configures this PWM. -// -// For the two 8 bit timers, there is only a limited number of periods -// available, namely the CPU frequency divided by 256 and again divided by 1, 8, -// 64, 256, or 1024. For a MCU running at 16MHz, this would be a period of 16µs, -// 128µs, 1024µs, 4096µs, or 16384µs. -func (pwm PWM) Configure(config PWMConfig) error { - switch pwm.num { - case 0, 2: // 8-bit timers (Timer/counter 0 and Timer/counter 2) - // Calculate the timer prescaler. - // While we could configure a flexible top, that would sacrifice one of - // the PWM output compare registers and thus a PWM channel. I've chosen - // to instead limit this timer to a fixed number of frequencies. - var prescaler uint8 - switch config.Period { - case 0, (uint64(1e9) * 256 * 1) / uint64(CPUFrequency()): - prescaler = 1 - case (uint64(1e9) * 256 * 8) / uint64(CPUFrequency()): - prescaler = 2 - case (uint64(1e9) * 256 * 64) / uint64(CPUFrequency()): - prescaler = 3 - case (uint64(1e9) * 256 * 256) / uint64(CPUFrequency()): - prescaler = 4 - case (uint64(1e9) * 256 * 1024) / uint64(CPUFrequency()): - prescaler = 5 - default: - return ErrPWMPeriodTooLong - } - - if pwm.num == 0 { - avr.TCCR0B.Set(prescaler) - // Set the PWM mode to fast PWM (mode = 3). - avr.TCCR0A.Set(avr.TCCR0A_WGM00 | avr.TCCR0A_WGM01) - // monotonic timer is using the same time as PWM:0 - // we must adjust internal settings of monotonic timer when PWM:0 settings changed - adjustMonotonicTimer() - } else { - avr.TCCR2B.Set(prescaler) - // Set the PWM mode to fast PWM (mode = 3). - avr.TCCR2A.Set(avr.TCCR2A_WGM20 | avr.TCCR2A_WGM21) - } - case 1: // Timer/counter 1 - // The top value is the number of PWM ticks a PWM period takes. It is - // initially picked assuming an unlimited counter top and no PWM - // prescaler. - var top uint64 - if config.Period == 0 { - // Use a top appropriate for LEDs. Picking a relatively low period - // here (0xff) for consistency with the other timers. - top = 0xff - } else { - // The formula below calculates the following formula, optimized: - // top = period * (CPUFrequency() / 1e9) - // By dividing the CPU frequency first (an operation that is easily - // optimized away) the period has less chance of overflowing. - top = config.Period * (uint64(CPUFrequency()) / 1000000) / 1000 - } - - avr.TCCR1A.Set(avr.TCCR1A_WGM11) - - // The ideal PWM period may be larger than would fit in the PWM counter, - // which is 16 bits (see maxTop). Therefore, try to make the PWM clock - // speed lower with a prescaler to make the top value fit the maximum - // top value. - const maxTop = 0x10000 - switch { - case top <= maxTop: - avr.TCCR1B.Set(3<<3 | 1) // no prescaling - case top/8 <= maxTop: - avr.TCCR1B.Set(3<<3 | 2) // divide by 8 - top /= 8 - case top/64 <= maxTop: - avr.TCCR1B.Set(3<<3 | 3) // divide by 64 - top /= 64 - case top/256 <= maxTop: - avr.TCCR1B.Set(3<<3 | 4) // divide by 256 - top /= 256 - case top/1024 <= maxTop: - avr.TCCR1B.Set(3<<3 | 5) // divide by 1024 - top /= 1024 - default: - return ErrPWMPeriodTooLong - } - - // A top of 0x10000 is at 100% duty cycle. Subtract one because the - // counter counts from 0, not 1 (avoiding an off-by-one). - top -= 1 - - avr.ICR1H.Set(uint8(top >> 8)) - avr.ICR1L.Set(uint8(top)) - } - return nil -} - -// SetPeriod updates the period of this PWM peripheral. -// To set a particular frequency, use the following formula: -// -// period = 1e9 / frequency -// -// If you use a period of 0, a period that works well for LEDs will be picked. -// -// SetPeriod will not change the prescaler, but also won't change the current -// value in any of the channels. This means that you may need to update the -// value for the particular channel. -// -// Note that you cannot pick any arbitrary period after the PWM peripheral has -// been configured. If you want to switch between frequencies, pick the lowest -// frequency (longest period) once when calling Configure and adjust the -// frequency here as needed. -func (pwm PWM) SetPeriod(period uint64) error { - if pwm.num != 1 { - return ErrPWMPeriodTooLong // TODO better error message - } - - // The top value is the number of PWM ticks a PWM period takes. It is - // initially picked assuming an unlimited counter top and no PWM - // prescaler. - var top uint64 - if period == 0 { - // Use a top appropriate for LEDs. Picking a relatively low period - // here (0xff) for consistency with the other timers. - top = 0xff - } else { - // The formula below calculates the following formula, optimized: - // top = period * (CPUFrequency() / 1e9) - // By dividing the CPU frequency first (an operation that is easily - // optimized away) the period has less chance of overflowing. - top = period * (uint64(CPUFrequency()) / 1000000) / 1000 - } - - prescaler := avr.TCCR1B.Get() & 0x7 - switch prescaler { - case 1: - top /= 1 - case 2: - top /= 8 - case 3: - top /= 64 - case 4: - top /= 256 - case 5: - top /= 1024 - } - - // A top of 0x10000 is at 100% duty cycle. Subtract one because the counter - // counts from 0, not 1 (avoiding an off-by-one). - top -= 1 - - if top > 0xffff { - return ErrPWMPeriodTooLong - } - - // Warning: this change is not atomic! - avr.ICR1H.Set(uint8(top >> 8)) - avr.ICR1L.Set(uint8(top)) - - // ... and because of that, set the counter back to zero to avoid most of - // the effects of this non-atomicity. - avr.TCNT1H.Set(0) - avr.TCNT1L.Set(0) - - return nil -} - -// Top returns the current counter top, for use in duty cycle calculation. It -// will only change with a call to Configure or SetPeriod, otherwise it is -// constant. -// -// The value returned here is hardware dependent. In general, it's best to treat -// it as an opaque value that can be divided by some number and passed to Set -// (see Set documentation for more information). -func (pwm PWM) Top() uint32 { - if pwm.num == 1 { - // Timer 1 has a configurable top value. - low := avr.ICR1L.Get() - high := avr.ICR1H.Get() - return uint32(high)<<8 | uint32(low) + 1 - } - // Other timers go from 0 to 0xff (0x100 or 256 in total). - return 256 -} - -// Counter returns the current counter value of the timer in this PWM -// peripheral. It may be useful for debugging. -func (pwm PWM) Counter() uint32 { - switch pwm.num { - case 0: - return uint32(avr.TCNT0.Get()) - case 1: - mask := interrupt.Disable() - low := avr.TCNT1L.Get() - high := avr.TCNT1H.Get() - interrupt.Restore(mask) - return uint32(high)<<8 | uint32(low) - case 2: - return uint32(avr.TCNT2.Get()) - } - // Unknown PWM. - return 0 -} - -// Period returns the used PWM period in nanoseconds. It might deviate slightly -// from the configured period due to rounding. -func (pwm PWM) Period() uint64 { - var prescaler uint8 - switch pwm.num { - case 0: - prescaler = avr.TCCR0B.Get() & 0x7 - case 1: - prescaler = avr.TCCR1B.Get() & 0x7 - case 2: - prescaler = avr.TCCR2B.Get() & 0x7 - } - top := uint64(pwm.Top()) - switch prescaler { - case 1: // prescaler 1 - return 1 * top * 1000 / uint64(CPUFrequency()/1e6) - case 2: // prescaler 8 - return 8 * top * 1000 / uint64(CPUFrequency()/1e6) - case 3: // prescaler 64 - return 64 * top * 1000 / uint64(CPUFrequency()/1e6) - case 4: // prescaler 256 - return 256 * top * 1000 / uint64(CPUFrequency()/1e6) - case 5: // prescaler 1024 - return 1024 * top * 1000 / uint64(CPUFrequency()/1e6) - default: // unknown clock source - return 0 - } -} - -// Channel returns a PWM channel for the given pin. -func (pwm PWM) Channel(pin Pin) (uint8, error) { - pin.Configure(PinConfig{Mode: PinOutput}) - pin.Low() - switch pwm.num { - case 0: - switch pin { - case PD6: // channel A - avr.TCCR0A.SetBits(avr.TCCR0A_COM0A1) - return 0, nil - case PD5: // channel B - avr.TCCR0A.SetBits(avr.TCCR0A_COM0B1) - return 1, nil - } - case 1: - switch pin { - case PB1: // channel A - avr.TCCR1A.SetBits(avr.TCCR1A_COM1A1) - return 0, nil - case PB2: // channel B - avr.TCCR1A.SetBits(avr.TCCR1A_COM1B1) - return 1, nil - } - case 2: - switch pin { - case PB3: // channel A - avr.TCCR2A.SetBits(avr.TCCR2A_COM2A1) - return 0, nil - case PD3: // channel B - avr.TCCR2A.SetBits(avr.TCCR2A_COM2B1) - return 1, nil - } - } - return 0, ErrInvalidOutputPin -} - -// SetInverting sets whether to invert the output of this channel. -// Without inverting, a 25% duty cycle would mean the output is high for 25% of -// the time and low for the rest. Inverting flips the output as if a NOT gate -// was placed at the output, meaning that the output would be 25% low and 75% -// high with a duty cycle of 25%. -// -// Note: the invert state may not be applied on the AVR until the next call to -// ch.Set(). -func (pwm PWM) SetInverting(channel uint8, inverting bool) { - switch pwm.num { - case 0: - switch channel { - case 0: // channel A - if inverting { - avr.PORTB.SetBits(1 << 6) // PB6 high - avr.TCCR0A.SetBits(avr.TCCR0A_COM0A0) - } else { - avr.PORTB.ClearBits(1 << 6) // PB6 low - avr.TCCR0A.ClearBits(avr.TCCR0A_COM0A0) - } - case 1: // channel B - if inverting { - avr.PORTB.SetBits(1 << 5) // PB5 high - avr.TCCR0A.SetBits(avr.TCCR0A_COM0B0) - } else { - avr.PORTB.ClearBits(1 << 5) // PB5 low - avr.TCCR0A.ClearBits(avr.TCCR0A_COM0B0) - } - } - case 1: - // Note: the COM1A0/COM1B0 bit is not set with the configuration below. - // It will be set the following call to Set(), however. - switch channel { - case 0: // channel A, PB1 - if inverting { - avr.PORTB.SetBits(1 << 1) // PB1 high - } else { - avr.PORTB.ClearBits(1 << 1) // PB1 low - } - case 1: // channel B, PB2 - if inverting { - avr.PORTB.SetBits(1 << 2) // PB2 high - } else { - avr.PORTB.ClearBits(1 << 2) // PB2 low - } - } - case 2: - switch channel { - case 0: // channel A - if inverting { - avr.PORTB.SetBits(1 << 3) // PB3 high - avr.TCCR2A.SetBits(avr.TCCR2A_COM2A0) - } else { - avr.PORTB.ClearBits(1 << 3) // PB3 low - avr.TCCR2A.ClearBits(avr.TCCR2A_COM2A0) - } - case 1: // channel B - if inverting { - avr.PORTD.SetBits(1 << 3) // PD3 high - avr.TCCR2A.SetBits(avr.TCCR2A_COM2B0) - } else { - avr.PORTD.ClearBits(1 << 3) // PD3 low - avr.TCCR2A.ClearBits(avr.TCCR2A_COM2B0) - } - } - } -} - -// Set updates the channel value. This is used to control the channel duty -// cycle, in other words the fraction of time the channel output is high (or low -// when inverted). For example, to set it to a 25% duty cycle, use: -// -// pwm.Set(channel, pwm.Top() / 4) -// -// pwm.Set(channel, 0) will set the output to low and pwm.Set(channel, -// pwm.Top()) will set the output to high, assuming the output isn't inverted. -func (pwm PWM) Set(channel uint8, value uint32) { - switch pwm.num { - case 0: - value := uint16(value) - switch channel { - case 0: // channel A - if value == 0 { - avr.TCCR0A.ClearBits(avr.TCCR0A_COM0A1) - } else { - avr.OCR0A.Set(uint8(value - 1)) - avr.TCCR0A.SetBits(avr.TCCR0A_COM0A1) - } - case 1: // channel B - if value == 0 { - avr.TCCR0A.ClearBits(avr.TCCR0A_COM0B1) - } else { - avr.OCR0B.Set(uint8(value) - 1) - avr.TCCR0A.SetBits(avr.TCCR0A_COM0B1) - } - } - // monotonic timer is using the same time as PWM:0 - // we must adjust internal settings of monotonic timer when PWM:0 settings changed - adjustMonotonicTimer() - case 1: - mask := interrupt.Disable() - switch channel { - case 0: // channel A, PB1 - if value == 0 { - avr.TCCR1A.ClearBits(avr.TCCR1A_COM1A1 | avr.TCCR1A_COM1A0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR1AH.Set(uint8(value >> 8)) - avr.OCR1AL.Set(uint8(value)) - if avr.PORTB.HasBits(1 << 1) { // is PB1 high? - // Yes, set the inverting bit. - avr.TCCR1A.SetBits(avr.TCCR1A_COM1A1 | avr.TCCR1A_COM1A0) - } else { - // No, output is non-inverting. - avr.TCCR1A.SetBits(avr.TCCR1A_COM1A1) - } - } - case 1: // channel B, PB2 - if value == 0 { - avr.TCCR1A.ClearBits(avr.TCCR1A_COM1B1 | avr.TCCR1A_COM1B0) - } else { - value := uint16(value) - 1 // yes, this is safe (it relies on underflow) - avr.OCR1BH.Set(uint8(value >> 8)) - avr.OCR1BL.Set(uint8(value)) - if avr.PORTB.HasBits(1 << 2) { // is PB2 high? - // Yes, set the inverting bit. - avr.TCCR1A.SetBits(avr.TCCR1A_COM1B1 | avr.TCCR1A_COM1B0) - } else { - // No, output is non-inverting. - avr.TCCR1A.SetBits(avr.TCCR1A_COM1B1) - } - } - } - interrupt.Restore(mask) - case 2: - value := uint16(value) - switch channel { - case 0: // channel A - if value == 0 { - avr.TCCR2A.ClearBits(avr.TCCR2A_COM2A1) - } else { - avr.OCR2A.Set(uint8(value - 1)) - avr.TCCR2A.SetBits(avr.TCCR2A_COM2A1) - } - case 1: // channel B - if value == 0 { - avr.TCCR2A.ClearBits(avr.TCCR2A_COM2B1) - } else { - avr.OCR2B.Set(uint8(value - 1)) - avr.TCCR2A.SetBits(avr.TCCR2A_COM2B1) - } - } - } -} - -// Pin Change Interrupts -type PinChange uint8 - -const ( - PinRising PinChange = 1 << iota - PinFalling - PinToggle = PinRising | PinFalling -) - -func (pin Pin) SetInterrupt(pinChange PinChange, callback func(Pin)) (err error) { - - switch { - case pin >= PB0 && pin <= PB7: - // PCMSK0 - PCINT0-7 - pinStates[0] = avr.PINB.Get() - pinIndex := pin - PB0 - if pinChange&PinRising > 0 { - pinCallbacks[0][pinIndex][0] = callback - } - if pinChange&PinFalling > 0 { - pinCallbacks[0][pinIndex][1] = callback - } - if callback != nil { - avr.PCMSK0.SetBits(1 << pinIndex) - } else { - avr.PCMSK0.ClearBits(1 << pinIndex) - } - avr.PCICR.SetBits(avr.PCICR_PCIE0) - interrupt.New(avr.IRQ_PCINT0, handlePCINT0Interrupts) - case pin >= PC0 && pin <= PC7: - // PCMSK1 - PCINT8-14 - pinStates[1] = avr.PINC.Get() - pinIndex := pin - PC0 - if pinChange&PinRising > 0 { - pinCallbacks[1][pinIndex][0] = callback - } - if pinChange&PinFalling > 0 { - pinCallbacks[1][pinIndex][1] = callback - } - if callback != nil { - avr.PCMSK1.SetBits(1 << pinIndex) - } else { - avr.PCMSK1.ClearBits(1 << pinIndex) - } - avr.PCICR.SetBits(avr.PCICR_PCIE1) - interrupt.New(avr.IRQ_PCINT1, handlePCINT1Interrupts) - case pin >= PD0 && pin <= PD7: - // PCMSK2 - PCINT16-23 - pinStates[2] = avr.PIND.Get() - pinIndex := pin - PD0 - if pinChange&PinRising > 0 { - pinCallbacks[2][pinIndex][0] = callback - } - if pinChange&PinFalling > 0 { - pinCallbacks[2][pinIndex][1] = callback - } - if callback != nil { - avr.PCMSK2.SetBits(1 << pinIndex) - } else { - avr.PCMSK2.ClearBits(1 << pinIndex) - } - avr.PCICR.SetBits(avr.PCICR_PCIE2) - interrupt.New(avr.IRQ_PCINT2, handlePCINT2Interrupts) - default: - return ErrInvalidInputPin - } - - return nil -} - -var pinCallbacks [3][8][2]func(Pin) -var pinStates [3]uint8 - -func handlePCINTInterrupts(intr uint8, port *volatile.Register8) { - current := port.Get() - change := pinStates[intr] ^ current - pinStates[intr] = current - for i := uint8(0); i < 8; i++ { - if (change>>i)&0x01 != 0x01 { - continue - } - pin := Pin(intr*8 + i) - value := pin.Get() - if value && pinCallbacks[intr][i][0] != nil { - pinCallbacks[intr][i][0](pin) - } - if !value && pinCallbacks[intr][i][1] != nil { - pinCallbacks[intr][i][1](pin) - } - } -} - -func handlePCINT0Interrupts(intr interrupt.Interrupt) { - handlePCINTInterrupts(0, avr.PINB) -} - -func handlePCINT1Interrupts(intr interrupt.Interrupt) { - handlePCINTInterrupts(1, avr.PINC) -} - -func handlePCINT2Interrupts(intr interrupt.Interrupt) { - handlePCINTInterrupts(2, avr.PIND) -} diff --git a/emb/machine/machine_atmega328p.go b/emb/machine/machine_atmega328p.go deleted file mode 100644 index 5bacfb8..0000000 --- a/emb/machine/machine_atmega328p.go +++ /dev/null @@ -1,60 +0,0 @@ -//go:build avr && atmega328p - -package machine - -import ( - "device/avr" - "runtime/volatile" -) - -const irq_USART0_RX = avr.IRQ_USART_RX - -// I2C0 is the only I2C interface on most AVRs. -var I2C0 = &I2C{ - srReg: avr.TWSR, - brReg: avr.TWBR, - crReg: avr.TWCR, - drReg: avr.TWDR, - srPS0: avr.TWSR_TWPS0, - srPS1: avr.TWSR_TWPS1, - crEN: avr.TWCR_TWEN, - crINT: avr.TWCR_TWINT, - crSTO: avr.TWCR_TWSTO, - crEA: avr.TWCR_TWEA, - crSTA: avr.TWCR_TWSTA, -} - -// SPI configuration -var SPI0 = &SPI{ - spcr: avr.SPCR, - spdr: avr.SPDR, - spsr: avr.SPSR, - - spcrR0: avr.SPCR_SPR0, - spcrR1: avr.SPCR_SPR1, - spcrCPHA: avr.SPCR_CPHA, - spcrCPOL: avr.SPCR_CPOL, - spcrDORD: avr.SPCR_DORD, - spcrSPE: avr.SPCR_SPE, - spcrMSTR: avr.SPCR_MSTR, - - spsrI2X: avr.SPSR_SPI2X, - spsrSPIF: avr.SPSR_SPIF, - - sck: PB5, - sdo: PB3, - sdi: PB4, - cs: PB2, -} - -// getPortMask returns the PORTx register and mask for the pin. -func (p Pin) getPortMask() (*volatile.Register8, uint8) { - switch { - case p >= PB0 && p <= PB7: // port B - return avr.PORTB, 1 << uint8(p-portB) - case p >= PC0 && p <= PC7: // port C - return avr.PORTC, 1 << uint8(p-portC) - default: // port D - return avr.PORTD, 1 << uint8(p-portD) - } -} diff --git a/emb/machine/machine_atmega328pb.go b/emb/machine/machine_atmega328pb.go deleted file mode 100644 index 935c581..0000000 --- a/emb/machine/machine_atmega328pb.go +++ /dev/null @@ -1,119 +0,0 @@ -//go:build avr && atmega328pb - -package machine - -import ( - "device/avr" - "runtime/interrupt" - "runtime/volatile" -) - -const irq_USART0_RX = avr.IRQ_USART0_RX -const irq_USART1_RX = avr.IRQ_USART1_RX - -var ( - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - - dataReg: avr.UDR1, - baudRegH: avr.UBRR1H, - baudRegL: avr.UBRR1L, - statusRegA: avr.UCSR1A, - statusRegB: avr.UCSR1B, - statusRegC: avr.UCSR1C, - } -) - -func init() { - // Register the UART interrupt. - interrupt.New(irq_USART1_RX, _UART1.handleInterrupt) -} - -// I2C0 is the only I2C interface on most AVRs. -var I2C0 = &I2C{ - srReg: avr.TWSR0, - brReg: avr.TWBR0, - crReg: avr.TWCR0, - drReg: avr.TWDR0, - srPS0: avr.TWSR0_TWPS0, - srPS1: avr.TWSR0_TWPS1, - crEN: avr.TWCR0_TWEN, - crINT: avr.TWCR0_TWINT, - crSTO: avr.TWCR0_TWSTO, - crEA: avr.TWCR0_TWEA, - crSTA: avr.TWCR0_TWSTA, -} - -var I2C1 = &I2C{ - srReg: avr.TWSR1, - brReg: avr.TWBR1, - crReg: avr.TWCR1, - drReg: avr.TWDR1, - srPS0: avr.TWSR1_TWPS10, - srPS1: avr.TWSR1_TWPS11, - crEN: avr.TWCR1_TWEN1, - crINT: avr.TWCR1_TWINT1, - crSTO: avr.TWCR1_TWSTO1, - crEA: avr.TWCR1_TWEA1, - crSTA: avr.TWCR1_TWSTA1, -} - -// SPI configuration -var SPI0 = &SPI{ - spcr: avr.SPCR0, - spdr: avr.SPDR0, - spsr: avr.SPSR0, - - spcrR0: avr.SPCR0_SPR0, - spcrR1: avr.SPCR0_SPR1, - spcrCPHA: avr.SPCR0_CPHA, - spcrCPOL: avr.SPCR0_CPOL, - spcrDORD: avr.SPCR0_DORD, - spcrSPE: avr.SPCR0_SPE, - spcrMSTR: avr.SPCR0_MSTR, - - spsrI2X: avr.SPSR0_SPI2X, - spsrSPIF: avr.SPSR0_SPIF, - - sck: PB5, - sdo: PB3, - sdi: PB4, - cs: PB2, -} - -var SPI1 = &SPI{ - spcr: avr.SPCR1, - spdr: avr.SPDR1, - spsr: avr.SPSR1, - - spcrR0: avr.SPCR1_SPR10, - spcrR1: avr.SPCR1_SPR11, - spcrCPHA: avr.SPCR1_CPHA1, - spcrCPOL: avr.SPCR1_CPOL1, - spcrDORD: avr.SPCR1_DORD1, - spcrSPE: avr.SPCR1_SPE1, - spcrMSTR: avr.SPCR1_MSTR1, - - spsrI2X: avr.SPSR1_SPI2X1, - spsrSPIF: avr.SPSR1_SPIF1, - - sck: PC1, - sdo: PE3, - sdi: PC0, - cs: PE2, -} - -// getPortMask returns the PORTx register and mask for the pin. -func (p Pin) getPortMask() (*volatile.Register8, uint8) { - switch { - case p >= PB0 && p <= PB7: // port B - return avr.PORTB, 1 << uint8(p-portB) - case p >= PC0 && p <= PC7: // port C - return avr.PORTC, 1 << uint8(p-portC) - case p >= PD0 && p <= PD7: // port D - return avr.PORTD, 1 << uint8(p-portD) - default: // port E - return avr.PORTE, 1 << uint8(p-portE) - } -} diff --git a/emb/machine/machine_atmega32u4.go b/emb/machine/machine_atmega32u4.go deleted file mode 100644 index 8b3faab..0000000 --- a/emb/machine/machine_atmega32u4.go +++ /dev/null @@ -1,76 +0,0 @@ -//go:build avr && atmega32u4 - -package machine - -import ( - "device/avr" - "runtime/volatile" -) - -const ( - // Note: start at port B because there is no port A. - portB Pin = iota * 8 - portC - portD - portE - portF -) - -const ( - PB0 = portB + 0 - PB1 = portB + 1 // peripherals: Timer1 channel A - PB2 = portB + 2 // peripherals: Timer1 channel B - PB3 = portB + 3 // peripherals: Timer2 channel A - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 - PD4 = portD + 4 - PD5 = portD + 5 - PD6 = portD + 6 - PD7 = portD + 7 - PE0 = portE + 0 - PE1 = portE + 1 - PE2 = portE + 2 - PE3 = portE + 3 - PE4 = portE + 4 - PE5 = portE + 5 - PE6 = portE + 6 - PE7 = portE + 7 - PF0 = portF + 0 - PF1 = portF + 1 - PF2 = portF + 2 - PF3 = portF + 3 - PF4 = portF + 4 - PF5 = portF + 5 - PF6 = portF + 6 - PF7 = portF + 7 -) - -// getPortMask returns the PORTx register and mask for the pin. -func (p Pin) getPortMask() (*volatile.Register8, uint8) { - switch { - case p >= PB0 && p <= PB7: // port B - return avr.PORTB, 1 << uint8(p-portB) - case p >= PC0 && p <= PC7: // port C - return avr.PORTC, 1 << uint8(p-portC) - case p >= PD0 && p <= PD7: // port D - return avr.PORTD, 1 << uint8(p-portD) - case p >= PE0 && p <= PE7: // port E - return avr.PORTE, 1 << uint8(p-portE) - default: // port F - return avr.PORTF, 1 << uint8(p-portF) - } -} diff --git a/emb/machine/machine_atsam.go b/emb/machine/machine_atsam.go deleted file mode 100644 index ad2f073..0000000 --- a/emb/machine/machine_atsam.go +++ /dev/null @@ -1,31 +0,0 @@ -//go:build sam - -package machine - -import ( - "runtime/volatile" - "unsafe" -) - -var deviceID [16]byte - -// DeviceID returns an identifier that is unique within -// a particular chipset. -// -// The identity is one burnt into the MCU itself, or the -// flash chip at time of manufacture. -// -// It's possible that two different vendors may allocate -// the same DeviceID, so callers should take this into -// account if needing to generate a globally unique id. -// -// The length of the hardware ID is vendor-specific, but -// 8 bytes (64 bits) and 16 bytes (128 bits) are common. -func DeviceID() []byte { - for i := 0; i < len(deviceID); i++ { - word := (*volatile.Register32)(unsafe.Pointer(deviceIDAddr[i/4])).Get() - deviceID[i] = byte(word >> ((i % 4) * 8)) - } - - return deviceID[:] -} diff --git a/emb/machine/machine_atsamd21.go b/emb/machine/machine_atsamd21.go deleted file mode 100644 index b46dcef..0000000 --- a/emb/machine/machine_atsamd21.go +++ /dev/null @@ -1,2090 +0,0 @@ -//go:build sam && atsamd21 - -// Peripheral abstraction layer for the atsamd21. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD21-Family-DataSheet-DS40001882D.pdf -package machine - -import ( - "device/arm" - "device/sam" - "errors" - "internal/binary" - "runtime/interrupt" - "unsafe" -) - -const deviceName = sam.Device - -// DS40001882F, Section 10.3.3: Serial Number -var deviceIDAddr = []uintptr{0x0080A00C, 0x0080A040, 0x0080A044, 0x0080A048} - -const ( - PinAnalog PinMode = 1 - PinSERCOM PinMode = 2 - PinSERCOMAlt PinMode = 3 - PinTimer PinMode = 4 - PinTimerAlt PinMode = 5 - PinCom PinMode = 6 - //PinAC_CLK PinMode = 7 - PinDigital PinMode = 8 - PinInput PinMode = 9 - PinInputPullup PinMode = 10 - PinOutput PinMode = 11 - PinTCC PinMode = PinTimer - PinTCCAlt PinMode = PinTimerAlt - PinInputPulldown PinMode = 12 -) - -type PinChange uint8 - -// Pin change interrupt constants for SetInterrupt. -const ( - PinRising PinChange = sam.EIC_CONFIG_SENSE0_RISE - PinFalling PinChange = sam.EIC_CONFIG_SENSE0_FALL - PinToggle PinChange = sam.EIC_CONFIG_SENSE0_BOTH -) - -// Callbacks to be called for pins configured with SetInterrupt. Unfortunately, -// we also need to keep track of which interrupt channel is used by which pin, -// as the only alternative would be iterating through all pins. -// -// We're using the magic constant 16 here because the SAM D21 has 16 interrupt -// channels configurable for pins. -var ( - interruptPins [16]Pin // warning: the value is invalid when pinCallbacks[i] is not set! - pinCallbacks [16]func(Pin) -) - -const ( - pinPadMapSERCOM0Pad0 byte = (0x10 << 1) | 0x00 - pinPadMapSERCOM1Pad0 byte = (0x20 << 1) | 0x00 - pinPadMapSERCOM2Pad0 byte = (0x30 << 1) | 0x00 - pinPadMapSERCOM3Pad0 byte = (0x40 << 1) | 0x00 - pinPadMapSERCOM4Pad0 byte = (0x50 << 1) | 0x00 - pinPadMapSERCOM5Pad0 byte = (0x60 << 1) | 0x00 - pinPadMapSERCOM0Pad2 byte = (0x10 << 1) | 0x10 - pinPadMapSERCOM1Pad2 byte = (0x20 << 1) | 0x10 - pinPadMapSERCOM2Pad2 byte = (0x30 << 1) | 0x10 - pinPadMapSERCOM3Pad2 byte = (0x40 << 1) | 0x10 - pinPadMapSERCOM4Pad2 byte = (0x50 << 1) | 0x10 - pinPadMapSERCOM5Pad2 byte = (0x60 << 1) | 0x10 - - pinPadMapSERCOM0AltPad0 byte = (0x01 << 1) | 0x00 - pinPadMapSERCOM1AltPad0 byte = (0x02 << 1) | 0x00 - pinPadMapSERCOM2AltPad0 byte = (0x03 << 1) | 0x00 - pinPadMapSERCOM3AltPad0 byte = (0x04 << 1) | 0x00 - pinPadMapSERCOM4AltPad0 byte = (0x05 << 1) | 0x00 - pinPadMapSERCOM5AltPad0 byte = (0x06 << 1) | 0x00 - pinPadMapSERCOM0AltPad2 byte = (0x01 << 1) | 0x01 - pinPadMapSERCOM1AltPad2 byte = (0x02 << 1) | 0x01 - pinPadMapSERCOM2AltPad2 byte = (0x03 << 1) | 0x01 - pinPadMapSERCOM3AltPad2 byte = (0x04 << 1) | 0x01 - pinPadMapSERCOM4AltPad2 byte = (0x05 << 1) | 0x01 - pinPadMapSERCOM5AltPad2 byte = (0x06 << 1) | 0x01 -) - -// pinPadMapping lists which pins have which SERCOMs attached to them. -// The encoding is rather dense, with each byte encoding two pins and both -// SERCOM and SERCOM-ALT. -// -// Observations: -// - There are six SERCOMs. Those SERCOM numbers can be encoded in 3 bits. -// - Even pad numbers are always on even pins, and odd pad numbers are always on -// odd pins. -// - Pin pads come in pairs. If PA00 has pad 0, then PA01 has pad 1. -// -// With this information, we can encode SERCOM pin/pad numbers much more -// efficiently. First of all, due to pads coming in pairs, we can ignore half -// the pins: the information for an odd pin can be calculated easily from the -// preceding even pin. And second, if odd pads are always on odd pins and even -// pads on even pins, we can drop a single bit from the pad number. -// -// Each byte below is split in two nibbles. The 4 high bits are for SERCOM and -// the 4 low bits are for SERCOM-ALT. Of each nibble, the 3 high bits encode the -// SERCOM + 1 while the low bit encodes whether this is PAD0 or PAD2 (0 means -// PAD0, 1 means PAD2). It encodes SERCOM + 1 instead of just the SERCOM number, -// to make it easy to check whether a nibble is set at all. -var pinPadMapping = [32]byte{ - // page 21 - PA00 / 2: 0 | pinPadMapSERCOM1AltPad0, - PB08 / 2: 0 | pinPadMapSERCOM4AltPad0, - PA04 / 2: 0 | pinPadMapSERCOM0AltPad0, - PA06 / 2: 0 | pinPadMapSERCOM0AltPad2, - PA08 / 2: pinPadMapSERCOM0Pad0 | pinPadMapSERCOM2AltPad0, - PA10 / 2: pinPadMapSERCOM0Pad2 | pinPadMapSERCOM2AltPad2, - - // page 22 - PB10 / 2: 0 | pinPadMapSERCOM4AltPad2, - PB12 / 2: pinPadMapSERCOM4Pad0 | 0, - PB14 / 2: pinPadMapSERCOM4Pad2 | 0, - PA12 / 2: pinPadMapSERCOM2Pad0 | pinPadMapSERCOM4AltPad0, - PA14 / 2: pinPadMapSERCOM2Pad2 | pinPadMapSERCOM4AltPad2, - PA16 / 2: pinPadMapSERCOM1Pad0 | pinPadMapSERCOM3AltPad0, - PA18 / 2: pinPadMapSERCOM1Pad2 | pinPadMapSERCOM3AltPad2, - PB16 / 2: pinPadMapSERCOM5Pad0 | 0, - PA20 / 2: pinPadMapSERCOM5Pad2 | pinPadMapSERCOM3AltPad2, - PA22 / 2: pinPadMapSERCOM3Pad0 | pinPadMapSERCOM5AltPad0, - PA24 / 2: pinPadMapSERCOM3Pad2 | pinPadMapSERCOM5AltPad2, - - // page 23 - PB22 / 2: 0 | pinPadMapSERCOM5AltPad2, - PA30 / 2: 0 | pinPadMapSERCOM1AltPad2, - PB30 / 2: 0 | pinPadMapSERCOM5AltPad0, - PB00 / 2: 0 | pinPadMapSERCOM5AltPad2, - PB02 / 2: 0 | pinPadMapSERCOM5AltPad0, -} - -// findPinPadMapping looks up the pad number and the pinmode for a given pin, -// given a SERCOM number. The result can either be SERCOM, SERCOM-ALT, or "not -// found" (indicated by returning ok=false). The pad number is returned to -// calculate the DOPO/DIPO bitfields of the various serial peripherals. -func findPinPadMapping(sercom uint8, pin Pin) (pinMode PinMode, pad uint32, ok bool) { - if int(pin)/2 >= len(pinPadMapping) { - // This is probably NoPin, for which no mapping is available. - return - } - - nibbles := pinPadMapping[pin/2] - upper := nibbles >> 4 - lower := nibbles & 0xf - - if upper != 0 { - // SERCOM - if (upper>>1)-1 == sercom { - pinMode = PinSERCOM - pad |= uint32((upper & 1) << 1) - ok = true - } - } - if lower != 0 { - // SERCOM-ALT - if (lower>>1)-1 == sercom { - pinMode = PinSERCOMAlt - pad |= uint32((lower & 1) << 1) - ok = true - } - } - - if ok { - // The lower bit of the pad is the same as the lower bit of the pin number. - pad |= uint32(pin & 1) - } - return -} - -// SetInterrupt sets an interrupt to be executed when a particular pin changes -// state. The pin should already be configured as an input, including a pull up -// or down if no external pull is provided. -// -// This call will replace a previously set callback on this pin. You can pass a -// nil func to unset the pin change interrupt. If you do so, the change -// parameter is ignored and can be set to any value (such as 0). -func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error { - // Most pins follow a common pattern where the EXTINT value is the pin - // number modulo 16. However, there are a few exceptions, as you can see - // below. - extint := uint8(0) - switch p { - case PA08: - // Connected to NMI. This is not currently supported. - return ErrInvalidInputPin - case PA24: - extint = 12 - case PA25: - extint = 13 - case PA27: - extint = 15 - case PA28: - extint = 8 - case PA30: - extint = 10 - case PA31: - extint = 11 - default: - // All other pins follow a normal pattern. - extint = uint8(p) % 16 - } - - if callback == nil { - // Disable this pin interrupt (if it was enabled). - sam.EIC.INTENCLR.Set(1 << extint) - if pinCallbacks[extint] != nil { - pinCallbacks[extint] = nil - } - return nil - } - - if pinCallbacks[extint] != nil { - // The pin was already configured. - // To properly re-configure a pin, unset it first and set a new - // configuration. - return ErrNoPinChangeChannel - } - pinCallbacks[extint] = callback - interruptPins[extint] = p - - if sam.EIC.CTRL.Get() == 0 { - // EIC peripheral has not yet been initialized. Initialize it now. - - // The EIC needs two clocks: CLK_EIC_APB and GCLK_EIC. CLK_EIC_APB is - // enabled by default, so doesn't have to be re-enabled. The other is - // required for detecting edges and must be enabled manually. - sam.GCLK.CLKCTRL.Set(sam.GCLK_CLKCTRL_ID_EIC<= 8 { - addr = &sam.EIC.CONFIG1 - } - pos := (extint % 8) * 4 // bit position in register - addr.ReplaceBits(uint32(change), 0xf, pos) - - // Enable external interrupt for this pin. - sam.EIC.INTENSET.Set(1 << extint) - - // Set the PMUXEN flag, while keeping the INEN and PULLEN flags (if they - // were set before). This avoids clearing the pin pull mode while - // configuring the pin interrupt. - p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | (p.getPinCfg() & (sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN))) - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - p.setPMux(val | (sam.PORT_PMUX0_PMUXO_A << sam.PORT_PMUX0_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk - p.setPMux(val | (sam.PORT_PMUX0_PMUXE_A << sam.PORT_PMUX0_PMUXE_Pos)) - } - - interrupt.New(sam.IRQ_EIC, func(interrupt.Interrupt) { - flags := sam.EIC.INTFLAG.Get() - sam.EIC.INTFLAG.Set(flags) // clear interrupt - for i := uint(0); i < 16; i++ { // there are 16 channels - if flags&(1<>3) & uint16(0x7) - - // ADC Linearity bits 4:0 - linearity0Fuse := *(*uint32)(unsafe.Pointer(uintptr(0x00806020))) - linearity := uint16(linearity0Fuse>>27) & uint16(0x1f) - - // ADC Linearity bits 7:5 - linearity1Fuse := *(*uint32)(unsafe.Pointer(uintptr(0x00806020) + 4)) - linearity |= uint16(linearity1Fuse) & uint16(0x7) << 5 - - // set calibration - sam.ADC.CALIB.Set((bias << 8) | linearity) -} - -// Configure configures a ADC pin to be able to be used to read data. -func (a ADC) Configure(config ADCConfig) { - - // Wait for synchronization - waitADCSync() - - var resolution uint32 - switch config.Resolution { - case 8: - resolution = sam.ADC_CTRLB_RESSEL_8BIT - case 10: - resolution = sam.ADC_CTRLB_RESSEL_10BIT - case 12: - resolution = sam.ADC_CTRLB_RESSEL_12BIT - case 16: - resolution = sam.ADC_CTRLB_RESSEL_16BIT - default: - resolution = sam.ADC_CTRLB_RESSEL_12BIT - } - // Divide Clock by 32 with 12 bits resolution as default - sam.ADC.CTRLB.Set((sam.ADC_CTRLB_PRESCALER_DIV32 << sam.ADC_CTRLB_PRESCALER_Pos) | - uint16(resolution<> sam.ADC_CTRLB_RESSEL_Pos { - case sam.ADC_CTRLB_RESSEL_8BIT: - val = val << 8 - case sam.ADC_CTRLB_RESSEL_10BIT: - val = val << 6 - case sam.ADC_CTRLB_RESSEL_16BIT: - val = val << 4 - case sam.ADC_CTRLB_RESSEL_12BIT: - val = val << 4 - } - return val -} - -func (a ADC) getADCChannel() uint8 { - switch a.Pin { - case PA02: - return 0 - case PA03: - return 1 - case PB04: - return 12 - case PB05: - return 13 - case PB06: - return 14 - case PB07: - return 15 - case PB08: - return 2 - case PB09: - return 3 - case PA04: - return 4 - case PA05: - return 5 - case PA06: - return 6 - case PA07: - return 7 - case PA08: - return 16 - case PA09: - return 17 - case PA10: - return 18 - case PA11: - return 19 - case PB00: - return 8 - case PB01: - return 9 - case PB02: - return 10 - case PB03: - return 11 - default: - return 0 - } -} - -func waitADCSync() { - for sam.ADC.STATUS.HasBits(sam.ADC_STATUS_SYNCBUSY) { - } -} - -// UART on the SAMD21. -type UART struct { - Buffer *RingBuffer - Bus *sam.SERCOM_USART_Type - SERCOM uint8 - Interrupt interrupt.Interrupt -} - -const ( - sampleRate16X = 16 - lsbFirst = 1 -) - -// Configure the UART. -func (uart *UART) Configure(config UARTConfig) error { - // Default baud rate to 115200. - if config.BaudRate == 0 { - config.BaudRate = 115200 - } - - // Use default pins if pins are not set. - if config.TX == 0 && config.RX == 0 { - // use default pins - config.TX = UART_TX_PIN - config.RX = UART_RX_PIN - } - - // Determine transmit pinout. - txPinMode, txPad, ok := findPinPadMapping(uart.SERCOM, config.TX) - if !ok { - return ErrInvalidOutputPin - } - var txPadOut uint32 - // See table 25-9 of the datasheet (page 459) for how pads are mapped to - // pinout values. - switch txPad { - case 0: - txPadOut = 0 - case 2: - txPadOut = 1 - default: - // this should be a flow control (RTS/CTS) pin - return ErrInvalidOutputPin - } - - // Determine receive pinout. - rxPinMode, rxPad, ok := findPinPadMapping(uart.SERCOM, config.RX) - if !ok { - return ErrInvalidInputPin - } - // As you can see in table 25-8 on page 459 of the datasheet, input pins - // are mapped directly. - rxPadOut := rxPad - - // configure pins - config.TX.Configure(PinConfig{Mode: txPinMode}) - config.RX.Configure(PinConfig{Mode: rxPinMode}) - - // configure RTS/CTS pins if provided - if config.RTS != 0 && config.CTS != 0 { - rtsPinMode, _, ok := findPinPadMapping(uart.SERCOM, config.RTS) - if !ok { - return ErrInvalidOutputPin - } - - ctsPinMode, _, ok := findPinPadMapping(uart.SERCOM, config.CTS) - if !ok { - return ErrInvalidInputPin - } - - // See table 25-9 of the datasheet (page 459) for how pads are mapped to - // pinout values. - if txPadOut == 1 { - return ErrInvalidOutputPin - } - txPadOut = 2 - - config.RTS.Configure(PinConfig{Mode: rtsPinMode}) - config.CTS.Configure(PinConfig{Mode: ctsPinMode}) - } - - // reset SERCOM0 - uart.Bus.CTRLA.SetBits(sam.SERCOM_USART_CTRLA_SWRST) - for uart.Bus.CTRLA.HasBits(sam.SERCOM_USART_CTRLA_SWRST) || - uart.Bus.SYNCBUSY.HasBits(sam.SERCOM_USART_SYNCBUSY_SWRST) { - } - - // set UART mode/sample rate - // SERCOM_USART_CTRLA_MODE(mode) | - // SERCOM_USART_CTRLA_SAMPR(sampleRate); - uart.Bus.CTRLA.Set((sam.SERCOM_USART_CTRLA_MODE_USART_INT_CLK << sam.SERCOM_USART_CTRLA_MODE_Pos) | - (1 << sam.SERCOM_USART_CTRLA_SAMPR_Pos)) // sample rate of 16x - - // Set baud rate - uart.SetBaudRate(config.BaudRate) - - // setup UART frame - // SERCOM_USART_CTRLA_FORM( (parityMode == SERCOM_NO_PARITY ? 0 : 1) ) | - // dataOrder << SERCOM_USART_CTRLA_DORD_Pos; - uart.Bus.CTRLA.SetBits((0 << sam.SERCOM_USART_CTRLA_FORM_Pos) | // no parity - (lsbFirst << sam.SERCOM_USART_CTRLA_DORD_Pos)) // data order - - // set UART stop bits/parity - // SERCOM_USART_CTRLB_CHSIZE(charSize) | - // nbStopBits << SERCOM_USART_CTRLB_SBMODE_Pos | - // (parityMode == SERCOM_NO_PARITY ? 0 : parityMode) << SERCOM_USART_CTRLB_PMODE_Pos; //If no parity use default value - uart.Bus.CTRLB.SetBits((0 << sam.SERCOM_USART_CTRLB_CHSIZE_Pos) | // 8 bits is 0 - (0 << sam.SERCOM_USART_CTRLB_SBMODE_Pos) | // 1 stop bit is zero - (0 << sam.SERCOM_USART_CTRLB_PMODE_Pos)) // no parity - - // set UART pads. This is not same as pins... - // SERCOM_USART_CTRLA_TXPO(txPad) | - // SERCOM_USART_CTRLA_RXPO(rxPad); - uart.Bus.CTRLA.SetBits((txPadOut << sam.SERCOM_USART_CTRLA_TXPO_Pos) | - (rxPadOut << sam.SERCOM_USART_CTRLA_RXPO_Pos)) - - // Enable Transceiver and Receiver - //sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN ; - uart.Bus.CTRLB.SetBits(sam.SERCOM_USART_CTRLB_TXEN | sam.SERCOM_USART_CTRLB_RXEN) - - // Enable USART1 port. - // sercom->USART.CTRLA.bit.ENABLE = 0x1u; - uart.Bus.CTRLA.SetBits(sam.SERCOM_USART_CTRLA_ENABLE) - for uart.Bus.SYNCBUSY.HasBits(sam.SERCOM_USART_SYNCBUSY_ENABLE) { - } - - // setup interrupt on receive - uart.Bus.INTENSET.Set(sam.SERCOM_USART_INTENSET_RXC) - - // Enable RX IRQ. - uart.Interrupt.Enable() - - return nil -} - -// SetBaudRate sets the communication speed for the UART. -func (uart *UART) SetBaudRate(br uint32) { - // Asynchronous fractional mode (Table 24-2 in datasheet) - // BAUD = fref / (sampleRateValue * fbaud) - // (multiply by 8, to calculate fractional piece) - // uint32_t baudTimes8 = (SystemCoreClock * 8) / (16 * baudrate); - baud := (CPUFrequency() * 8) / (sampleRate16X * br) - - // sercom->USART.BAUD.FRAC.FP = (baudTimes8 % 8); - // sercom->USART.BAUD.FRAC.BAUD = (baudTimes8 / 8); - uart.Bus.BAUD.Set(uint16(((baud % 8) << sam.SERCOM_USART_BAUD_FRAC_MODE_FP_Pos) | - ((baud / 8) << sam.SERCOM_USART_BAUD_FRAC_MODE_BAUD_Pos))) -} - -// WriteByte writes a byte of data to the UART. -func (uart *UART) writeByte(c byte) error { - // wait until ready to receive - for !uart.Bus.INTFLAG.HasBits(sam.SERCOM_USART_INTFLAG_DRE) { - } - uart.Bus.DATA.Set(uint16(c)) - return nil -} - -func (uart *UART) flush() {} - -// handleInterrupt should be called from the appropriate interrupt handler for -// this UART instance. -func (uart *UART) handleInterrupt(interrupt.Interrupt) { - // should reset IRQ - uart.Receive(byte((uart.Bus.DATA.Get() & 0xFF))) - uart.Bus.INTFLAG.SetBits(sam.SERCOM_USART_INTFLAG_RXC) -} - -// I2C on the SAMD21. -type I2C struct { - Bus *sam.SERCOM_I2CM_Type - SERCOM uint8 -} - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 - SCL Pin - SDA Pin -} - -const ( - // Default rise time in nanoseconds, based on 4.7K ohm pull up resistors - riseTimeNanoseconds = 125 - - // wire bus states - wireUnknownState = 0 - wireIdleState = 1 - wireOwnerState = 2 - wireBusyState = 3 - - // wire commands - wireCmdNoAction = 0 - wireCmdRepeatStart = 1 - wireCmdRead = 2 - wireCmdStop = 3 -) - -const i2cTimeout = 1000 - -// Configure is intended to setup the I2C interface. -func (i2c *I2C) Configure(config I2CConfig) error { - // Default I2C bus speed is 100 kHz. - if config.Frequency == 0 { - config.Frequency = 100 * KHz - } - if config.SDA == 0 && config.SCL == 0 { - config.SDA = SDA_PIN - config.SCL = SCL_PIN - } - - sclPinMode, sclPad, ok := findPinPadMapping(i2c.SERCOM, config.SCL) - if !ok || sclPad != 1 { - // SCL must be on pad 1, according to section 27.5 of the datasheet. - // Note: this is not an exhaustive test for I2C support on the pin: not - // all pins support I2C. - return ErrInvalidClockPin - } - sdaPinMode, sdaPad, ok := findPinPadMapping(i2c.SERCOM, config.SDA) - if !ok || sdaPad != 0 { - // SDA must be on pad 0, according to section 27.5 of the datasheet. - // Note: this is not an exhaustive test for I2C support on the pin: not - // all pins support I2C. - return ErrInvalidDataPin - } - - // reset SERCOM - i2c.Bus.CTRLA.SetBits(sam.SERCOM_I2CM_CTRLA_SWRST) - for i2c.Bus.CTRLA.HasBits(sam.SERCOM_I2CM_CTRLA_SWRST) || - i2c.Bus.SYNCBUSY.HasBits(sam.SERCOM_I2CM_SYNCBUSY_SWRST) { - } - - // Set i2c controller mode - //SERCOM_I2CM_CTRLA_MODE( I2C_MASTER_OPERATION ) - i2c.Bus.CTRLA.Set(sam.SERCOM_I2CM_CTRLA_MODE_I2C_MASTER << sam.SERCOM_I2CM_CTRLA_MODE_Pos) // | - - i2c.SetBaudRate(config.Frequency) - - // Enable I2CM port. - // sercom->USART.CTRLA.bit.ENABLE = 0x1u; - i2c.Bus.CTRLA.SetBits(sam.SERCOM_I2CM_CTRLA_ENABLE) - for i2c.Bus.SYNCBUSY.HasBits(sam.SERCOM_I2CM_SYNCBUSY_ENABLE) { - } - - // set bus idle mode - i2c.Bus.STATUS.SetBits(wireIdleState << sam.SERCOM_I2CM_STATUS_BUSSTATE_Pos) - for i2c.Bus.SYNCBUSY.HasBits(sam.SERCOM_I2CM_SYNCBUSY_SYSOP) { - } - - // enable pins - config.SDA.Configure(PinConfig{Mode: sdaPinMode}) - config.SCL.Configure(PinConfig{Mode: sclPinMode}) - - return nil -} - -// SetBaudRate sets the communication speed for I2C. -func (i2c *I2C) SetBaudRate(br uint32) error { - // Synchronous arithmetic baudrate, via Arduino SAMD implementation: - // SystemCoreClock / ( 2 * baudrate) - 5 - (((SystemCoreClock / 1000000) * WIRE_RISE_TIME_NANOSECONDS) / (2 * 1000)); - baud := CPUFrequency()/(2*br) - 5 - (((CPUFrequency() / 1000000) * riseTimeNanoseconds) / (2 * 1000)) - i2c.Bus.BAUD.Set(baud) - return nil -} - -// Tx does a single I2C transaction at the specified address. -// It clocks out the given address, writes the bytes in w, reads back len(r) -// bytes and stores them in r, and generates a stop condition on the bus. -func (i2c *I2C) Tx(addr uint16, w, r []byte) error { - var err error - if len(w) != 0 { - // send start/address for write - i2c.sendAddress(addr, true) - - // wait until transmission complete - timeout := i2cTimeout - for !i2c.Bus.INTFLAG.HasBits(sam.SERCOM_I2CM_INTFLAG_MB) { - timeout-- - if timeout == 0 { - return errI2CWriteTimeout - } - } - - // ACK received (0: ACK, 1: NACK) - if i2c.Bus.STATUS.HasBits(sam.SERCOM_I2CM_STATUS_RXNACK) { - return errI2CAckExpected - } - - // write data - for _, b := range w { - err = i2c.WriteByte(b) - if err != nil { - return err - } - } - - err = i2c.signalStop() - if err != nil { - return err - } - } - if len(r) != 0 { - // send start/address for read - i2c.sendAddress(addr, false) - - // wait transmission complete - for !i2c.Bus.INTFLAG.HasBits(sam.SERCOM_I2CM_INTFLAG_SB) { - // If the peripheral NACKS the address, the MB bit will be set. - // In that case, send a stop condition and return error. - if i2c.Bus.INTFLAG.HasBits(sam.SERCOM_I2CM_INTFLAG_MB) { - i2c.Bus.CTRLB.SetBits(wireCmdStop << sam.SERCOM_I2CM_CTRLB_CMD_Pos) // Stop condition - return errI2CAckExpected - } - } - - // ACK received (0: ACK, 1: NACK) - if i2c.Bus.STATUS.HasBits(sam.SERCOM_I2CM_STATUS_RXNACK) { - return errI2CAckExpected - } - - // read first byte - r[0] = i2c.readByte() - for i := 1; i < len(r); i++ { - // Send an ACK - i2c.Bus.CTRLB.ClearBits(sam.SERCOM_I2CM_CTRLB_ACKACT) - - i2c.signalRead() - - // Read data and send the ACK - r[i] = i2c.readByte() - } - - // Send NACK to end transmission - i2c.Bus.CTRLB.SetBits(sam.SERCOM_I2CM_CTRLB_ACKACT) - - err = i2c.signalStop() - if err != nil { - return err - } - } - - return nil -} - -// WriteByte writes a single byte to the I2C bus. -func (i2c *I2C) WriteByte(data byte) error { - // Send data byte - i2c.Bus.DATA.Set(data) - - // wait until transmission successful - timeout := i2cTimeout - for !i2c.Bus.INTFLAG.HasBits(sam.SERCOM_I2CM_INTFLAG_MB) { - // check for bus error - if sam.SERCOM3_I2CM.STATUS.HasBits(sam.SERCOM_I2CM_STATUS_BUSERR) { - return errI2CBusError - } - timeout-- - if timeout == 0 { - return errI2CWriteTimeout - } - } - - if i2c.Bus.STATUS.HasBits(sam.SERCOM_I2CM_STATUS_RXNACK) { - return errI2CAckExpected - } - - return nil -} - -// sendAddress sends the address and start signal -func (i2c *I2C) sendAddress(address uint16, write bool) error { - data := (address << 1) - if !write { - data |= 1 // set read flag - } - - // wait until bus ready - timeout := i2cTimeout - for !i2c.Bus.STATUS.HasBits(wireIdleState< 0 { - baudRate-- - } - spi.Bus.BAUD.Set(uint8(baudRate)) - - // Enable SPI port. - spi.Bus.CTRLA.SetBits(sam.SERCOM_SPI_CTRLA_ENABLE) - for spi.Bus.SYNCBUSY.HasBits(sam.SERCOM_SPI_SYNCBUSY_ENABLE) { - } - - return nil -} - -// Transfer writes/reads a single byte using the SPI interface. -func (spi *SPI) Transfer(w byte) (byte, error) { - // write data - spi.Bus.DATA.Set(uint32(w)) - - // wait for receive - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_RXC) { - } - - // return data - return byte(spi.Bus.DATA.Get()), nil -} - -// Tx handles read/write operation for SPI interface. Since SPI is a synchronous write/read -// interface, there must always be the same number of bytes written as bytes read. -// The Tx method knows about this, and offers a few different ways of calling it. -// -// This form sends the bytes in tx buffer, putting the resulting bytes read into the rx buffer. -// Note that the tx and rx buffers must be the same size: -// -// spi.Tx(tx, rx) -// -// This form sends the tx buffer, ignoring the result. Useful for sending "commands" that return zeros -// until all the bytes in the command packet have been received: -// -// spi.Tx(tx, nil) -// -// This form sends zeros, putting the result into the rx buffer. Good for reading a "result packet": -// -// spi.Tx(nil, rx) -func (spi *SPI) Tx(w, r []byte) error { - switch { - case w == nil: - // read only, so write zero and read a result. - spi.rx(r) - case r == nil: - // write only - spi.tx(w) - - default: - // write/read - if len(w) != len(r) { - return ErrTxInvalidSliceSize - } - - spi.txrx(w, r) - } - - return nil -} - -func (spi *SPI) tx(tx []byte) { - for i := 0; i < len(tx); i++ { - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_DRE) { - } - spi.Bus.DATA.Set(uint32(tx[i])) - } - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_TXC) { - } - - // read to clear RXC register - for spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_RXC) { - spi.Bus.DATA.Get() - } -} - -func (spi *SPI) rx(rx []byte) { - spi.Bus.DATA.Set(0) - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_DRE) { - } - - for i := 1; i < len(rx); i++ { - spi.Bus.DATA.Set(0) - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_RXC) { - } - rx[i-1] = byte(spi.Bus.DATA.Get()) - } - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_RXC) { - } - rx[len(rx)-1] = byte(spi.Bus.DATA.Get()) -} - -func (spi *SPI) txrx(tx, rx []byte) { - spi.Bus.DATA.Set(uint32(tx[0])) - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_DRE) { - } - - for i := 1; i < len(rx); i++ { - spi.Bus.DATA.Set(uint32(tx[i])) - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_RXC) { - } - rx[i-1] = byte(spi.Bus.DATA.Get()) - } - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPI_INTFLAG_RXC) { - } - rx[len(rx)-1] = byte(spi.Bus.DATA.Get()) -} - -// TCC is one timer/counter peripheral, which consists of a counter and multiple -// output channels (that can be connected to actual pins). You can set the -// frequency using SetPeriod, but only for all the channels in this TCC -// peripheral at once. -type TCC sam.TCC_Type - -// The SAM D21 has three TCC peripherals, which have PWM as one feature. -var ( - TCC0 = (*TCC)(sam.TCC0) - TCC1 = (*TCC)(sam.TCC1) - TCC2 = (*TCC)(sam.TCC2) -) - -//go:inline -func (tcc *TCC) timer() *sam.TCC_Type { - return (*sam.TCC_Type)(tcc) -} - -// Configure enables and configures this TCC. -func (tcc *TCC) Configure(config PWMConfig) error { - // Enable the clock source for this timer. - switch tcc.timer() { - case sam.TCC0: - sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_TCC0_) - // Use GCLK0 for TCC0/TCC1 - sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_TCC0_TCC1 << sam.GCLK_CLKCTRL_ID_Pos) | - (sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) | - sam.GCLK_CLKCTRL_CLKEN) - for sam.GCLK.STATUS.HasBits(sam.GCLK_STATUS_SYNCBUSY) { - } - case sam.TCC1: - sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_TCC1_) - // Use GCLK0 for TCC0/TCC1 - sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_TCC0_TCC1 << sam.GCLK_CLKCTRL_ID_Pos) | - (sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) | - sam.GCLK_CLKCTRL_CLKEN) - for sam.GCLK.STATUS.HasBits(sam.GCLK_STATUS_SYNCBUSY) { - } - case sam.TCC2: - sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_TCC2_) - // Use GCLK0 for TCC2/TC3 - sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_TCC2_TC3 << sam.GCLK_CLKCTRL_ID_Pos) | - (sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) | - sam.GCLK_CLKCTRL_CLKEN) - for sam.GCLK.STATUS.HasBits(sam.GCLK_STATUS_SYNCBUSY) { - } - } - - // Disable timer (if it was enabled). This is necessary because - // tcc.setPeriod may want to change the prescaler bits in CTRLA, which is - // only allowed when the TCC is disabled. - tcc.timer().CTRLA.ClearBits(sam.TCC_CTRLA_ENABLE) - - // Use "Normal PWM" (single-slope PWM) - tcc.timer().WAVE.Set(sam.TCC_WAVE_WAVEGEN_NPWM) - - // Wait for synchronization of all changed registers. - for tcc.timer().SYNCBUSY.Get() != 0 { - } - - // Set the period and prescaler. - err := tcc.setPeriod(config.Period, true) - - // Enable the timer. - tcc.timer().CTRLA.SetBits(sam.TCC_CTRLA_ENABLE) - - // Wait for synchronization of all changed registers. - for tcc.timer().SYNCBUSY.Get() != 0 { - } - - // Return any error that might have occurred in the tcc.setPeriod call. - return err -} - -// SetPeriod updates the period of this TCC peripheral. -// To set a particular frequency, use the following formula: -// -// period = 1e9 / frequency -// -// If you use a period of 0, a period that works well for LEDs will be picked. -// -// SetPeriod will not change the prescaler, but also won't change the current -// value in any of the channels. This means that you may need to update the -// value for the particular channel. -// -// Note that you cannot pick any arbitrary period after the TCC peripheral has -// been configured. If you want to switch between frequencies, pick the lowest -// frequency (longest period) once when calling Configure and adjust the -// frequency here as needed. -func (tcc *TCC) SetPeriod(period uint64) error { - err := tcc.setPeriod(period, false) - if err == nil { - if tcc.Counter() >= tcc.Top() { - // When setting the timer to a shorter period, there is a chance - // that it passes the counter value and thus goes all the way to MAX - // before wrapping back to zero. - // To avoid this, reset the counter back to 0. - tcc.timer().COUNT.Set(0) - } - } - return err -} - -// setPeriod sets the period of this TCC, possibly updating the prescaler as -// well. The prescaler can only modified when the TCC is disabled, that is, in -// the Configure function. -func (tcc *TCC) setPeriod(period uint64, updatePrescaler bool) error { - var top uint64 - if period == 0 { - // Make sure the TOP value is at 0xffff (enough for a 16-bit timer). - top = 0xffff - } else { - // The formula below calculates the following formula, optimized: - // period * (48e6 / 1e9) - // This assumes that the chip is running at the (default) 48MHz speed. - top = period * 6 / 125 - } - - maxTop := uint64(0xffffff) - if tcc.timer() == sam.TCC2 { - // TCC2 is a 16-bit timer, not a 24-bit timer. - maxTop = 0xffff - } - - if updatePrescaler { - // This function was called during Configure(), with the timer disabled. - // Note that updating the prescaler can only happen while the peripheral - // is disabled. - var prescaler uint32 - switch { - case top <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV1 - case top/2 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV2 - top = top / 2 - case top/4 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV4 - top = top / 4 - case top/8 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV8 - top = top / 8 - case top/16 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV16 - top = top / 16 - case top/64 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV64 - top = top / 64 - case top/256 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV256 - top = top / 256 - case top/1024 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV1024 - top = top / 1024 - default: - return ErrPWMPeriodTooLong - } - tcc.timer().CTRLA.Set((tcc.timer().CTRLA.Get() &^ sam.TCC_CTRLA_PRESCALER_Msk) | (prescaler << sam.TCC_CTRLA_PRESCALER_Pos)) - } else { - // Do not update the prescaler, but use the already-configured - // prescaler. This is the normal SetPeriod case, where the prescaler - // must not be changed. - prescaler := (tcc.timer().CTRLA.Get() & sam.TCC_CTRLA_PRESCALER_Msk) >> sam.TCC_CTRLA_PRESCALER_Pos - switch prescaler { - case sam.TCC_CTRLA_PRESCALER_DIV1: - top /= 1 // no-op - case sam.TCC_CTRLA_PRESCALER_DIV2: - top /= 2 - case sam.TCC_CTRLA_PRESCALER_DIV4: - top /= 4 - case sam.TCC_CTRLA_PRESCALER_DIV8: - top /= 8 - case sam.TCC_CTRLA_PRESCALER_DIV16: - top /= 16 - case sam.TCC_CTRLA_PRESCALER_DIV64: - top /= 64 - case sam.TCC_CTRLA_PRESCALER_DIV256: - top /= 256 - case sam.TCC_CTRLA_PRESCALER_DIV1024: - top /= 1024 - default: - // unreachable - } - if top > maxTop { - return ErrPWMPeriodTooLong - } - } - - // Set the period (the counter top). - tcc.timer().PER.Set(uint32(top) - 1) - - // Wait for synchronization of CTRLA.PRESCALER and PER registers. - for tcc.timer().SYNCBUSY.Get() != 0 { - } - - return nil -} - -// Top returns the current counter top, for use in duty cycle calculation. It -// will only change with a call to Configure or SetPeriod, otherwise it is -// constant. -// -// The value returned here is hardware dependent. In general, it's best to treat -// it as an opaque value that can be divided by some number and passed to Set -// (see Set documentation for more information). -func (tcc *TCC) Top() uint32 { - return tcc.timer().PER.Get() + 1 -} - -// Counter returns the current counter value of the timer in this TCC -// peripheral. It may be useful for debugging. -func (tcc *TCC) Counter() uint32 { - tcc.timer().CTRLBSET.Set(sam.TCC_CTRLBSET_CMD_READSYNC << sam.TCC_CTRLBSET_CMD_Pos) - for tcc.timer().SYNCBUSY.Get() != 0 { - } - return tcc.timer().COUNT.Get() -} - -// Some constants to make pinTimerMapping below easier to read. -const ( - pinTCC0 = 1 - pinTCC1 = 2 - pinTCC2 = 3 - pinTimerCh0 = 0 << 3 - pinTimerCh2 = 1 << 3 - pinTCC0Ch0 = pinTCC0 | pinTimerCh0 - pinTCC0Ch2 = pinTCC0 | pinTimerCh2 - pinTCC1Ch0 = pinTCC1 | pinTimerCh0 - pinTCC1Ch2 = pinTCC1 | pinTimerCh2 - pinTCC2Ch0 = pinTCC2 | pinTimerCh0 -) - -// Mapping from pin number to TCC peripheral and channel using a special -// encoding. Note that only TCC0-TCC2 are included, not TC3 and up. -// Every byte is split in two nibbles where the low nibble describes PinTCC and -// the high nibble describes PinTCCAlt. Within a nibble, there is one bit that -// indicates Ch0/Ch1 or Ch2/Ch3, and three other bits that contain the TCC -// peripheral number plus one (to distinguish between TCC0Ch0 and 0). -// -// The encoding can be so compact because all pins are configured in pairs, so -// if you know PA00 you can infer the configuration of PA01. And only channel 0 -// or 2 need to be included (taking up just one bit), because channel 0 and 2 -// are only ever used on odd pins and channel 1 and 3 on even pins, again using -// the pin pair pattern to reduce the amount of information needed to be stored. -// -// Datasheet: https://cdn.sparkfun.com/datasheets/Dev/Arduino/Boards/Atmel-42181-SAM-D21_Datasheet.pdf -var pinTimerMapping = [...]uint8{ - // page 21 - PA00 / 2: pinTCC2Ch0 | 0, - PA04 / 2: pinTCC0Ch0 | 0, - PA06 / 2: pinTCC1Ch0 | 0, - PA08 / 2: pinTCC0Ch0 | pinTCC1Ch2<<4, - PA10 / 2: pinTCC1Ch0 | pinTCC0Ch2<<4, - // page 22 - PB10 / 2: 0 | pinTCC0Ch0<<4, - PB12 / 2: 0 | pinTCC0Ch2<<4, - PA12 / 2: pinTCC2Ch0 | pinTCC0Ch2<<4, - PA14 / 2: 0 | pinTCC0Ch0<<4, - PA16 / 2: pinTCC2Ch0 | pinTCC0Ch2<<4, - PA18 / 2: 0 | pinTCC0Ch2<<4, - PB16 / 2: 0 | pinTCC0Ch0<<4, - PA20 / 2: 0 | pinTCC0Ch2<<4, - PA22 / 2: 0 | pinTCC0Ch0<<4, - PA24 / 2: 0 | pinTCC1Ch2<<4, - // page 23 - PA30 / 2: 0 | pinTCC1Ch0<<4, - PB30 / 2: pinTCC0Ch0 | pinTCC1Ch2<<4, -} - -// findPinTimerMapping returns the pin mode (PinTCC or PinTCCAlt) and the channel -// number for a given timer and pin. A zero PinMode is returned if no mapping -// could be found. -func findPinTimerMapping(timer uint8, pin Pin) (PinMode, uint8) { - mapping := pinTimerMapping[pin/2] - // evenChannel below indicates the channel 0 or 2, for the even part of the - // pin pair. The next pin will also have the next channel (1 or 3). - if mapping&0x07 == timer+1 { - // PWM output is on peripheral function E. - evenChannel := ((mapping >> 3) & 1) * 2 - return PinTCC, evenChannel + uint8(pin&1) - } - if (mapping&0x70)>>4 == timer+1 { - // PWM output is on peripheral function F. - evenChannel := ((mapping >> 7) & 1) * 2 - return PinTCCAlt, evenChannel + uint8(pin&1) - } - return 0, 0 -} - -// Channel returns a PWM channel for the given pin. Note that one channel may be -// shared between multiple pins, and so will have the same duty cycle. If this -// is not desirable, look for a different TCC peripheral or consider using a -// different pin. -func (tcc *TCC) Channel(pin Pin) (uint8, error) { - var pinMode PinMode - var channel uint8 - switch tcc.timer() { - case sam.TCC0: - pinMode, channel = findPinTimerMapping(0, pin) - case sam.TCC1: - pinMode, channel = findPinTimerMapping(1, pin) - case sam.TCC2: - pinMode, channel = findPinTimerMapping(2, pin) - } - - if pinMode == 0 { - // No pin could be found. - return 0, ErrInvalidOutputPin - } - - // Enable the port multiplexer for pin - pin.setPinCfg(sam.PORT_PINCFG0_PMUXEN) - - if pin&1 > 0 { - // odd pin, so save the even pins - val := pin.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - pin.setPMux(val | uint8(pinMode<> 6) - syncDAC() - return nil -} - -func syncDAC() { - for sam.DAC.STATUS.HasBits(sam.DAC_STATUS_SYNCBUSY) { - } -} - -// Flash related code -const memoryStart = 0x0 - -// compile-time check for ensuring we fulfill BlockDevice interface -var _ BlockDevice = flashBlockDevice{} - -var Flash flashBlockDevice - -type flashBlockDevice struct { - initComplete bool -} - -// ReadAt reads the given number of bytes from the block device. -func (f flashBlockDevice) ReadAt(p []byte, off int64) (n int, err error) { - if FlashDataStart()+uintptr(off)+uintptr(len(p)) > FlashDataEnd() { - return 0, errFlashCannotReadPastEOF - } - - f.ensureInitComplete() - - waitWhileFlashBusy() - - data := unsafe.Slice((*byte)(unsafe.Add(unsafe.Pointer(FlashDataStart()), uintptr(off))), len(p)) - copy(p, data) - - return len(p), nil -} - -// WriteAt writes the given number of bytes to the block device. -// Data is written to the page buffer in 4-byte chunks, then saved to flash memory. -// See Atmel-42181G–SAM-D21_Datasheet–09/2015 page 359. -// If the length of p is not long enough it will be padded with 0xFF bytes. -// This method assumes that the destination is already erased. -func (f flashBlockDevice) WriteAt(p []byte, off int64) (n int, err error) { - if FlashDataStart()+uintptr(off)+uintptr(len(p)) > FlashDataEnd() { - return 0, errFlashCannotWritePastEOF - } - - f.ensureInitComplete() - - address := FlashDataStart() + uintptr(off) - padded := flashPad(p, int(f.WriteBlockSize())) - - waitWhileFlashBusy() - - for j := 0; j < len(padded); j += int(f.WriteBlockSize()) { - // page buffer is 64 bytes long, but only 4 bytes can be written at once - for k := 0; k < int(f.WriteBlockSize()); k += 4 { - *(*uint32)(unsafe.Pointer(address + uintptr(k))) = binary.LittleEndian.Uint32(padded[j+k : j+k+4]) - } - - sam.NVMCTRL.SetADDR(uint32(address >> 1)) - sam.NVMCTRL.CTRLA.Set(sam.NVMCTRL_CTRLA_CMD_WP | (sam.NVMCTRL_CTRLA_CMDEX_KEY << sam.NVMCTRL_CTRLA_CMDEX_Pos)) - - waitWhileFlashBusy() - - if err := checkFlashError(); err != nil { - return j, err - } - - address += uintptr(f.WriteBlockSize()) - } - - return len(padded), nil -} - -// Size returns the number of bytes in this block device. -func (f flashBlockDevice) Size() int64 { - return int64(FlashDataEnd() - FlashDataStart()) -} - -const writeBlockSize = 64 - -// WriteBlockSize returns the block size in which data can be written to -// memory. It can be used by a client to optimize writes, non-aligned writes -// should always work correctly. -func (f flashBlockDevice) WriteBlockSize() int64 { - return writeBlockSize -} - -const eraseBlockSizeValue = 256 - -func eraseBlockSize() int64 { - return eraseBlockSizeValue -} - -// EraseBlockSize returns the smallest erasable area on this particular chip -// in bytes. This is used for the block size in EraseBlocks. -func (f flashBlockDevice) EraseBlockSize() int64 { - return eraseBlockSize() -} - -// EraseBlocks erases the given number of blocks. An implementation may -// transparently coalesce ranges of blocks into larger bundles if the chip -// supports this. The start and len parameters are in block numbers, use -// EraseBlockSize to map addresses to blocks. -func (f flashBlockDevice) EraseBlocks(start, len int64) error { - f.ensureInitComplete() - - address := FlashDataStart() + uintptr(start*f.EraseBlockSize()) - waitWhileFlashBusy() - - for i := start; i < start+len; i++ { - sam.NVMCTRL.SetADDR(uint32(address >> 1)) - sam.NVMCTRL.CTRLA.Set(sam.NVMCTRL_CTRLA_CMD_ER | (sam.NVMCTRL_CTRLA_CMDEX_KEY << sam.NVMCTRL_CTRLA_CMDEX_Pos)) - - waitWhileFlashBusy() - - if err := checkFlashError(); err != nil { - return err - } - - address += uintptr(f.EraseBlockSize()) - } - - return nil -} - -func (f flashBlockDevice) ensureInitComplete() { - if f.initComplete { - return - } - - sam.NVMCTRL.SetCTRLB_READMODE(sam.NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY) - sam.NVMCTRL.SetCTRLB_SLEEPPRM(sam.NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS) - - waitWhileFlashBusy() - - f.initComplete = true -} - -func waitWhileFlashBusy() { - for sam.NVMCTRL.GetINTFLAG_READY() != sam.NVMCTRL_INTFLAG_READY { - } -} - -var ( - errFlashPROGE = errors.New("errFlashPROGE") - errFlashLOCKE = errors.New("errFlashLOCKE") - errFlashNVME = errors.New("errFlashNVME") -) - -func checkFlashError() error { - switch { - case sam.NVMCTRL.GetSTATUS_PROGE() != 0: - return errFlashPROGE - case sam.NVMCTRL.GetSTATUS_LOCKE() != 0: - return errFlashLOCKE - case sam.NVMCTRL.GetSTATUS_NVME() != 0: - return errFlashNVME - } - - return nil -} - -// Watchdog provides access to the hardware watchdog available -// in the SAMD21. -var Watchdog = &watchdogImpl{} - -const ( - // WatchdogMaxTimeout in milliseconds (16s) - WatchdogMaxTimeout = (16384 * 1000) / 1024 -) - -type watchdogImpl struct{} - -// Configure the watchdog. -// -// This method should not be called after the watchdog is started and on -// some platforms attempting to reconfigure after starting the watchdog -// is explicitly forbidden / will not work. -func (wd *watchdogImpl) Configure(config WatchdogConfig) error { - // Use OSCULP32K as source for Generic Clock Generator 8, divided by 32 to get 1.024kHz - sam.GCLK.GENDIV.Set(sam.GCLK_CLKCTRL_GEN_GCLK8 | (32 << sam.GCLK_GENDIV_DIV_Pos)) - sam.GCLK.GENCTRL.Set(sam.GCLK_CLKCTRL_GEN_GCLK8 | (sam.GCLK_GENCTRL_SRC_OSCULP32K << sam.GCLK_GENCTRL_SRC_Pos) | sam.GCLK_GENCTRL_GENEN) - waitForSync() - - // Use GCLK8 for watchdog - sam.GCLK.CLKCTRL.Set(sam.GCLK_CLKCTRL_ID_WDT | (sam.GCLK_CLKCTRL_GEN_GCLK8 << sam.GCLK_CLKCTRL_GEN_Pos) | sam.GCLK_CLKCTRL_CLKEN) - - // Power on the watchdog peripheral - sam.PM.APBAMASK.SetBits(sam.PM_APBAMASK_WDT_) - - // 1.024kHz clock - cycles := int((int64(config.TimeoutMillis) * 1024) / 1000) - - // period is expressed as a power-of-two, starting at 8 / 1024ths of a second - period := uint8(0) - cfgCycles := 8 - for cfgCycles < cycles { - period++ - cfgCycles <<= 1 - - if period >= 0xB { - break - } - } - - sam.WDT.CONFIG.Set(period << sam.WDT_CONFIG_PER_Pos) - - return nil -} - -// Starts the watchdog. -func (wd *watchdogImpl) Start() error { - sam.WDT.CTRL.SetBits(sam.WDT_CTRL_ENABLE) - return nil -} - -// Update the watchdog, indicating that `source` is healthy. -func (wd *watchdogImpl) Update() { - sam.WDT.CLEAR.Set(sam.WDT_CLEAR_CLEAR_KEY) -} diff --git a/emb/machine/machine_atsamd21_simulator.go b/emb/machine/machine_atsamd21_simulator.go deleted file mode 100644 index 2a22533..0000000 --- a/emb/machine/machine_atsamd21_simulator.go +++ /dev/null @@ -1,45 +0,0 @@ -//go:build !baremetal && (gemma_m0 || qtpy || trinket_m0 || arduino_mkr1000 || arduino_mkrwifi1010 || arduino_nano33 || arduino_zero || circuitplay_express || feather_m0_express || feather_m0 || itsybitsy_m0 || p1am_100 || xiao) - -// Simulated atsamd21 chips. - -package machine - -// The timer channels/pins match the hardware, and encode the same information -// as pinTimerMapping but in a more generic (less efficient) way. - -var TCC0 = &timerType{ - instance: 0, - frequency: 48e6, - bits: 24, - prescalers: []int{1, 2, 4, 8, 16, 64, 256, 1024}, - channelPins: [][]Pin{ - {PA04, PA08, PB10, PA14, PB16, PA22, PB30}, // channel 0 - {PA05, PA09, PB11, PA15, PB17, PA23, PB31}, // channel 1 - {PA10, PB12, PA12, PA16, PA18, PA20}, // channel 2 - {PA11, PB13, PA13, PA17, PA19, PA21}, // channel 3 - }, -} - -var TCC1 = &timerType{ - instance: 1, - frequency: 48e6, - bits: 24, - prescalers: []int{1, 2, 4, 8, 16, 64, 256, 1024}, - channelPins: [][]Pin{ - {PA06, PA10, PA30}, // channel 0 - {PA07, PA11, PA31}, // channel 1 - {PA08, PA24, PB30}, // channel 2 - {PA09, PA25, PB31}, // channel 3 - }, -} - -var TCC2 = &timerType{ - instance: 2, - frequency: 48e6, - bits: 16, - prescalers: []int{1, 2, 4, 8, 16, 64, 256, 1024}, - channelPins: [][]Pin{ - {PA00, PA12, PA16}, // channel 0 - {PA01, PA13, PA17}, // channel 1 - }, -} diff --git a/emb/machine/machine_atsamd21_usb.go b/emb/machine/machine_atsamd21_usb.go deleted file mode 100644 index 7b9d2e1..0000000 --- a/emb/machine/machine_atsamd21_usb.go +++ /dev/null @@ -1,664 +0,0 @@ -//go:build sam && atsamd21 - -package machine - -import ( - "device/sam" - "machine/usb" - "runtime/interrupt" - "unsafe" -) - -const ( - // these are SAMD21 specific. - usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos = 0 - usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask = 0x3FFF - - usb_DEVICE_PCKSIZE_SIZE_Pos = 28 - usb_DEVICE_PCKSIZE_SIZE_Mask = 0x7 - - usb_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos = 14 - usb_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Mask = 0x3FFF - - NumberOfUSBEndpoints = 8 -) - -var ( - endPoints = []uint32{ - usb.CONTROL_ENDPOINT: usb.ENDPOINT_TYPE_CONTROL, - usb.CDC_ENDPOINT_ACM: (usb.ENDPOINT_TYPE_INTERRUPT | usb.EndpointIn), - usb.CDC_ENDPOINT_OUT: (usb.ENDPOINT_TYPE_BULK | usb.EndpointOut), - usb.CDC_ENDPOINT_IN: (usb.ENDPOINT_TYPE_BULK | usb.EndpointIn), - usb.HID_ENDPOINT_IN: (usb.ENDPOINT_TYPE_DISABLE), // Interrupt In - usb.HID_ENDPOINT_OUT: (usb.ENDPOINT_TYPE_DISABLE), // Interrupt Out - usb.MIDI_ENDPOINT_IN: (usb.ENDPOINT_TYPE_DISABLE), // Bulk In - usb.MIDI_ENDPOINT_OUT: (usb.ENDPOINT_TYPE_DISABLE), // Bulk Out - } -) - -// Configure the USB peripheral. The config is here for compatibility with the UART interface. -func (dev *USBDevice) Configure(config UARTConfig) { - if dev.initcomplete { - return - } - - // reset USB interface - sam.USB_DEVICE.CTRLA.SetBits(sam.USB_DEVICE_CTRLA_SWRST) - for sam.USB_DEVICE.SYNCBUSY.HasBits(sam.USB_DEVICE_SYNCBUSY_SWRST) || - sam.USB_DEVICE.SYNCBUSY.HasBits(sam.USB_DEVICE_SYNCBUSY_ENABLE) { - } - - sam.USB_DEVICE.DESCADD.Set(uint32(uintptr(unsafe.Pointer(&usbEndpointDescriptors)))) - - // configure pins - USBCDC_DM_PIN.Configure(PinConfig{Mode: PinCom}) - USBCDC_DP_PIN.Configure(PinConfig{Mode: PinCom}) - - // performs pad calibration from store fuses - handlePadCalibration() - - // run in standby - sam.USB_DEVICE.CTRLA.SetBits(sam.USB_DEVICE_CTRLA_RUNSTDBY) - - // set full speed - sam.USB_DEVICE.CTRLB.SetBits(sam.USB_DEVICE_CTRLB_SPDCONF_FS << sam.USB_DEVICE_CTRLB_SPDCONF_Pos) - - // attach - sam.USB_DEVICE.CTRLB.ClearBits(sam.USB_DEVICE_CTRLB_DETACH) - - // enable interrupt for end of reset - sam.USB_DEVICE.INTENSET.SetBits(sam.USB_DEVICE_INTENSET_EORST) - - // enable interrupt for start of frame - sam.USB_DEVICE.INTENSET.SetBits(sam.USB_DEVICE_INTENSET_SOF) - - // enable USB - sam.USB_DEVICE.CTRLA.SetBits(sam.USB_DEVICE_CTRLA_ENABLE) - - // enable IRQ - interrupt.New(sam.IRQ_USB, handleUSBIRQ).Enable() - - dev.initcomplete = true -} - -func handlePadCalibration() { - // Load Pad Calibration data from non-volatile memory - // This requires registers that are not included in the SVD file. - // Modeled after defines from samd21g18a.h and nvmctrl.h: - // - // #define NVMCTRL_OTP4 0x00806020 - // - // #define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4) - // #define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */ - // #define USB_FUSES_TRANSN_Msk (0x1Fu << USB_FUSES_TRANSN_Pos) - // #define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))) - - // #define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4) - // #define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */ - // #define USB_FUSES_TRANSP_Msk (0x1Fu << USB_FUSES_TRANSP_Pos) - // #define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))) - - // #define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4) - // #define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */ - // #define USB_FUSES_TRIM_Msk (0x7u << USB_FUSES_TRIM_Pos) - // #define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))) - // - fuse := *(*uint32)(unsafe.Pointer(uintptr(0x00806020) + 4)) - calibTransN := uint16(fuse>>13) & uint16(0x1f) - calibTransP := uint16(fuse>>18) & uint16(0x1f) - calibTrim := uint16(fuse>>23) & uint16(0x7) - - if calibTransN == 0x1f { - calibTransN = 5 - } - sam.USB_DEVICE.PADCAL.SetBits(calibTransN << sam.USB_DEVICE_PADCAL_TRANSN_Pos) - - if calibTransP == 0x1f { - calibTransP = 29 - } - sam.USB_DEVICE.PADCAL.SetBits(calibTransP << sam.USB_DEVICE_PADCAL_TRANSP_Pos) - - if calibTrim == 0x7 { - calibTrim = 3 - } - sam.USB_DEVICE.PADCAL.SetBits(calibTrim << sam.USB_DEVICE_PADCAL_TRIM_Pos) -} - -func handleUSBIRQ(intr interrupt.Interrupt) { - // reset all interrupt flags - flags := sam.USB_DEVICE.INTFLAG.Get() - sam.USB_DEVICE.INTFLAG.Set(flags) - - // End of reset - if (flags & sam.USB_DEVICE_INTFLAG_EORST) > 0 { - // Configure control endpoint - initEndpoint(0, usb.ENDPOINT_TYPE_CONTROL) - - usbConfiguration = 0 - - // ack the End-Of-Reset interrupt - sam.USB_DEVICE.INTFLAG.Set(sam.USB_DEVICE_INTFLAG_EORST) - } - - // Start of frame - if (flags & sam.USB_DEVICE_INTFLAG_SOF) > 0 { - // if you want to blink LED showing traffic, this would be the place... - } - - // Endpoint 0 Setup interrupt - if getEPINTFLAG(0)&sam.USB_DEVICE_EPINTFLAG_RXSTP > 0 { - // ack setup received - setEPINTFLAG(0, sam.USB_DEVICE_EPINTFLAG_RXSTP) - - // parse setup - setup := usb.NewSetup(udd_ep_out_cache_buffer[0][:]) - - // Clear the Bank 0 ready flag on Control OUT - usbEndpointDescriptors[0].DeviceDescBank[0].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[0])))) - usbEndpointDescriptors[0].DeviceDescBank[0].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) - setEPSTATUSCLR(0, sam.USB_DEVICE_EPSTATUSCLR_BK0RDY) - - ok := false - if (setup.BmRequestType & usb.REQUEST_TYPE) == usb.REQUEST_STANDARD { - // Standard Requests - ok = handleStandardSetup(setup) - } else { - // Class Interface Requests - if setup.WIndex < uint16(len(usbSetupHandler)) && usbSetupHandler[setup.WIndex] != nil { - ok = usbSetupHandler[setup.WIndex](setup) - } - } - - if ok { - // set Bank1 ready - setEPSTATUSSET(0, sam.USB_DEVICE_EPSTATUSSET_BK1RDY) - } else { - // Stall endpoint - setEPSTATUSSET(0, sam.USB_DEVICE_EPINTFLAG_STALL1) - } - - if getEPINTFLAG(0)&sam.USB_DEVICE_EPINTFLAG_STALL1 > 0 { - // ack the stall - setEPINTFLAG(0, sam.USB_DEVICE_EPINTFLAG_STALL1) - - // clear stall request - setEPINTENCLR(0, sam.USB_DEVICE_EPINTENCLR_STALL1) - } - } - - // Now the actual transfer handlers, ignore endpoint number 0 (setup) - var i uint32 - for i = 1; i < uint32(len(endPoints)); i++ { - // Check if endpoint has a pending interrupt - epFlags := getEPINTFLAG(i) - setEPINTFLAG(i, epFlags) - if (epFlags & sam.USB_DEVICE_EPINTFLAG_TRCPT0) > 0 { - buf := handleEndpointRx(i) - if usbRxHandler[i] == nil || usbRxHandler[i](buf) { - AckUsbOutTransfer(i) - } - } else if (epFlags & sam.USB_DEVICE_EPINTFLAG_TRCPT1) > 0 { - if usbTxHandler[i] != nil { - usbTxHandler[i]() - } - } - } -} - -func initEndpoint(ep, config uint32) { - switch config { - case usb.ENDPOINT_TYPE_INTERRUPT | usb.EndpointIn: - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[1].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[1].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_in_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, ((usb.ENDPOINT_TYPE_INTERRUPT + 1) << sam.USB_DEVICE_EPCFG_EPTYPE1_Pos)) - - setEPINTENSET(ep, sam.USB_DEVICE_EPINTENSET_TRCPT1) - - case usb.ENDPOINT_TYPE_BULK | usb.EndpointOut: - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[0].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, ((usb.ENDPOINT_TYPE_BULK + 1) << sam.USB_DEVICE_EPCFG_EPTYPE0_Pos)) - - // receive interrupts when current transfer complete - setEPINTENSET(ep, sam.USB_DEVICE_EPINTENSET_TRCPT0) - - // set byte count to zero, we have not received anything yet - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) - - // ready for next transfer - setEPSTATUSCLR(ep, sam.USB_DEVICE_EPSTATUSCLR_BK0RDY) - - case usb.ENDPOINT_TYPE_INTERRUPT | usb.EndpointOut: - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[0].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, ((usb.ENDPOINT_TYPE_INTERRUPT + 1) << sam.USB_DEVICE_EPCFG_EPTYPE0_Pos)) - - // receive interrupts when current transfer complete - setEPINTENSET(ep, sam.USB_DEVICE_EPINTENSET_TRCPT0) - - // set byte count to zero, we have not received anything yet - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) - - // ready for next transfer - setEPSTATUSCLR(ep, sam.USB_DEVICE_EPSTATUSCLR_BK0RDY) - - case usb.ENDPOINT_TYPE_BULK | usb.EndpointIn: - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[1].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[1].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_in_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, ((usb.ENDPOINT_TYPE_BULK + 1) << sam.USB_DEVICE_EPCFG_EPTYPE1_Pos)) - - // NAK on endpoint IN, the bank is not yet filled in. - setEPSTATUSCLR(ep, sam.USB_DEVICE_EPSTATUSCLR_BK1RDY) - - setEPINTENSET(ep, sam.USB_DEVICE_EPINTENSET_TRCPT1) - - case usb.ENDPOINT_TYPE_CONTROL: - // Control OUT - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[0].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, getEPCFG(ep)|((usb.ENDPOINT_TYPE_CONTROL+1)<> - usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) & usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask) - - if bytesread != cdcLineInfoSize { - return b, ErrUSBBytesRead - } - - copy(b[:7], udd_ep_out_cache_buffer[0][:7]) - - return b, nil -} - -func handleEndpointRx(ep uint32) []byte { - // get data - count := int((usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.Get() >> - usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) & usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask) - - return udd_ep_out_cache_buffer[ep][:count] -} - -// AckUsbOutTransfer is called to acknowledge the completion of a USB OUT transfer. -func AckUsbOutTransfer(ep uint32) { - // set byte count to zero - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) - - // set multi packet size to 64 - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.SetBits(64 << usb_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) - - // set ready for next data - setEPSTATUSCLR(ep, sam.USB_DEVICE_EPSTATUSCLR_BK0RDY) - -} - -func SendZlp() { - usbEndpointDescriptors[0].DeviceDescBank[1].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) -} - -func epPacketSize(size uint16) uint32 { - switch size { - case 8: - return 0 - case 16: - return 1 - case 32: - return 2 - case 64: - return 3 - case 128: - return 4 - case 256: - return 5 - case 512: - return 6 - case 1023: - return 7 - default: - return 0 - } -} - -func getEPCFG(ep uint32) uint8 { - switch ep { - case 0: - return sam.USB_DEVICE.EPCFG0.Get() - case 1: - return sam.USB_DEVICE.EPCFG1.Get() - case 2: - return sam.USB_DEVICE.EPCFG2.Get() - case 3: - return sam.USB_DEVICE.EPCFG3.Get() - case 4: - return sam.USB_DEVICE.EPCFG4.Get() - case 5: - return sam.USB_DEVICE.EPCFG5.Get() - case 6: - return sam.USB_DEVICE.EPCFG6.Get() - case 7: - return sam.USB_DEVICE.EPCFG7.Get() - default: - return 0 - } -} - -func setEPCFG(ep uint32, val uint8) { - switch ep { - case 0: - sam.USB_DEVICE.EPCFG0.Set(val) - case 1: - sam.USB_DEVICE.EPCFG1.Set(val) - case 2: - sam.USB_DEVICE.EPCFG2.Set(val) - case 3: - sam.USB_DEVICE.EPCFG3.Set(val) - case 4: - sam.USB_DEVICE.EPCFG4.Set(val) - case 5: - sam.USB_DEVICE.EPCFG5.Set(val) - case 6: - sam.USB_DEVICE.EPCFG6.Set(val) - case 7: - sam.USB_DEVICE.EPCFG7.Set(val) - default: - return - } -} - -func setEPSTATUSCLR(ep uint32, val uint8) { - switch ep { - case 0: - sam.USB_DEVICE.EPSTATUSCLR0.Set(val) - case 1: - sam.USB_DEVICE.EPSTATUSCLR1.Set(val) - case 2: - sam.USB_DEVICE.EPSTATUSCLR2.Set(val) - case 3: - sam.USB_DEVICE.EPSTATUSCLR3.Set(val) - case 4: - sam.USB_DEVICE.EPSTATUSCLR4.Set(val) - case 5: - sam.USB_DEVICE.EPSTATUSCLR5.Set(val) - case 6: - sam.USB_DEVICE.EPSTATUSCLR6.Set(val) - case 7: - sam.USB_DEVICE.EPSTATUSCLR7.Set(val) - default: - return - } -} - -func setEPSTATUSSET(ep uint32, val uint8) { - switch ep { - case 0: - sam.USB_DEVICE.EPSTATUSSET0.Set(val) - case 1: - sam.USB_DEVICE.EPSTATUSSET1.Set(val) - case 2: - sam.USB_DEVICE.EPSTATUSSET2.Set(val) - case 3: - sam.USB_DEVICE.EPSTATUSSET3.Set(val) - case 4: - sam.USB_DEVICE.EPSTATUSSET4.Set(val) - case 5: - sam.USB_DEVICE.EPSTATUSSET5.Set(val) - case 6: - sam.USB_DEVICE.EPSTATUSSET6.Set(val) - case 7: - sam.USB_DEVICE.EPSTATUSSET7.Set(val) - default: - return - } -} - -func getEPSTATUS(ep uint32) uint8 { - switch ep { - case 0: - return sam.USB_DEVICE.EPSTATUS0.Get() - case 1: - return sam.USB_DEVICE.EPSTATUS1.Get() - case 2: - return sam.USB_DEVICE.EPSTATUS2.Get() - case 3: - return sam.USB_DEVICE.EPSTATUS3.Get() - case 4: - return sam.USB_DEVICE.EPSTATUS4.Get() - case 5: - return sam.USB_DEVICE.EPSTATUS5.Get() - case 6: - return sam.USB_DEVICE.EPSTATUS6.Get() - case 7: - return sam.USB_DEVICE.EPSTATUS7.Get() - default: - return 0 - } -} - -func getEPINTFLAG(ep uint32) uint8 { - switch ep { - case 0: - return sam.USB_DEVICE.EPINTFLAG0.Get() - case 1: - return sam.USB_DEVICE.EPINTFLAG1.Get() - case 2: - return sam.USB_DEVICE.EPINTFLAG2.Get() - case 3: - return sam.USB_DEVICE.EPINTFLAG3.Get() - case 4: - return sam.USB_DEVICE.EPINTFLAG4.Get() - case 5: - return sam.USB_DEVICE.EPINTFLAG5.Get() - case 6: - return sam.USB_DEVICE.EPINTFLAG6.Get() - case 7: - return sam.USB_DEVICE.EPINTFLAG7.Get() - default: - return 0 - } -} - -func setEPINTFLAG(ep uint32, val uint8) { - switch ep { - case 0: - sam.USB_DEVICE.EPINTFLAG0.Set(val) - case 1: - sam.USB_DEVICE.EPINTFLAG1.Set(val) - case 2: - sam.USB_DEVICE.EPINTFLAG2.Set(val) - case 3: - sam.USB_DEVICE.EPINTFLAG3.Set(val) - case 4: - sam.USB_DEVICE.EPINTFLAG4.Set(val) - case 5: - sam.USB_DEVICE.EPINTFLAG5.Set(val) - case 6: - sam.USB_DEVICE.EPINTFLAG6.Set(val) - case 7: - sam.USB_DEVICE.EPINTFLAG7.Set(val) - default: - return - } -} - -func setEPINTENCLR(ep uint32, val uint8) { - switch ep { - case 0: - sam.USB_DEVICE.EPINTENCLR0.Set(val) - case 1: - sam.USB_DEVICE.EPINTENCLR1.Set(val) - case 2: - sam.USB_DEVICE.EPINTENCLR2.Set(val) - case 3: - sam.USB_DEVICE.EPINTENCLR3.Set(val) - case 4: - sam.USB_DEVICE.EPINTENCLR4.Set(val) - case 5: - sam.USB_DEVICE.EPINTENCLR5.Set(val) - case 6: - sam.USB_DEVICE.EPINTENCLR6.Set(val) - case 7: - sam.USB_DEVICE.EPINTENCLR7.Set(val) - default: - return - } -} - -func setEPINTENSET(ep uint32, val uint8) { - switch ep { - case 0: - sam.USB_DEVICE.EPINTENSET0.Set(val) - case 1: - sam.USB_DEVICE.EPINTENSET1.Set(val) - case 2: - sam.USB_DEVICE.EPINTENSET2.Set(val) - case 3: - sam.USB_DEVICE.EPINTENSET3.Set(val) - case 4: - sam.USB_DEVICE.EPINTENSET4.Set(val) - case 5: - sam.USB_DEVICE.EPINTENSET5.Set(val) - case 6: - sam.USB_DEVICE.EPINTENSET6.Set(val) - case 7: - sam.USB_DEVICE.EPINTENSET7.Set(val) - default: - return - } -} diff --git a/emb/machine/machine_atsamd21e18.go b/emb/machine/machine_atsamd21e18.go deleted file mode 100644 index 85d6853..0000000 --- a/emb/machine/machine_atsamd21e18.go +++ /dev/null @@ -1,359 +0,0 @@ -//go:build sam && atsamd21 && atsamd21e18 - -// Peripheral abstraction layer for the atsamd21. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD21-Family-DataSheet-DS40001882D.pdf -package machine - -import ( - "device/sam" - "runtime/interrupt" -) - -var ( - sercomUSART0 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM0_USART, SERCOM: 0} - sercomUSART1 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM1_USART, SERCOM: 1} - sercomUSART2 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM2_USART, SERCOM: 2} - sercomUSART3 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM3_USART, SERCOM: 3} - - sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0} - sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1} - sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2} - sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3} - - sercomSPIM0 = &SPI{Bus: sam.SERCOM0_SPI, SERCOM: 0} - sercomSPIM1 = &SPI{Bus: sam.SERCOM1_SPI, SERCOM: 1} - sercomSPIM2 = &SPI{Bus: sam.SERCOM2_SPI, SERCOM: 2} - sercomSPIM3 = &SPI{Bus: sam.SERCOM3_SPI, SERCOM: 3} -) - -func init() { - sercomUSART0.Interrupt = interrupt.New(sam.IRQ_SERCOM0, sercomUSART0.handleInterrupt) - sercomUSART1.Interrupt = interrupt.New(sam.IRQ_SERCOM1, sercomUSART1.handleInterrupt) - sercomUSART2.Interrupt = interrupt.New(sam.IRQ_SERCOM2, sercomUSART2.handleInterrupt) - sercomUSART3.Interrupt = interrupt.New(sam.IRQ_SERCOM3, sercomUSART3.handleInterrupt) -} - -// Return the register and mask to enable a given GPIO pin. This can be used to -// implement bit-banged drivers. -func (p Pin) PortMaskSet() (*uint32, uint32) { - return &sam.PORT.OUTSET0.Reg, 1 << uint8(p) -} - -// Return the register and mask to disable a given port. This can be used to -// implement bit-banged drivers. -func (p Pin) PortMaskClear() (*uint32, uint32) { - return &sam.PORT.OUTCLR0.Reg, 1 << uint8(p) -} - -// Set the pin to high or low. -// Warning: only use this on an output pin! -func (p Pin) Set(high bool) { - if high { - sam.PORT.OUTSET0.Set(1 << uint8(p)) - } else { - sam.PORT.OUTCLR0.Set(1 << uint8(p)) - } -} - -// Get returns the current value of a GPIO pin when configured as an input or as -// an output. -func (p Pin) Get() bool { - return (sam.PORT.IN0.Get()>>uint8(p))&1 > 0 -} - -// Configure this pin with the given configuration. -func (p Pin) Configure(config PinConfig) { - switch config.Mode { - case PinOutput: - sam.PORT.DIRSET0.Set(1 << uint8(p)) - // output is also set to input enable so pin can read back its own value - p.setPinCfg(sam.PORT_PINCFG0_INEN) - - case PinInput: - sam.PORT.DIRCLR0.Set(1 << uint8(p)) - p.setPinCfg(sam.PORT_PINCFG0_INEN) - - case PinInputPulldown: - sam.PORT.DIRCLR0.Set(1 << uint8(p)) - sam.PORT.OUTCLR0.Set(1 << uint8(p)) - p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN) - - case PinInputPullup: - sam.PORT.DIRCLR0.Set(1 << uint8(p)) - sam.PORT.OUTSET0.Set(1 << uint8(p)) - p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN) - - case PinSERCOM: - if uint8(p)&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_PMUX0_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk - p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_PMUX0_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | sam.PORT_PINCFG0_DRVSTR | sam.PORT_PINCFG0_INEN) - - case PinSERCOMAlt: - if uint8(p)&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_PMUX0_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk - p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_PMUX0_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | sam.PORT_PINCFG0_DRVSTR) - - case PinCom: - if uint8(p)&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - p.setPMux(val | (uint8(PinCom) << sam.PORT_PMUX0_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk - p.setPMux(val | (uint8(PinCom) << sam.PORT_PMUX0_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_PINCFG0_PMUXEN) - case PinAnalog: - if uint8(p)&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - p.setPMux(val | (uint8(PinAnalog) << sam.PORT_PMUX0_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk - p.setPMux(val | (uint8(PinAnalog) << sam.PORT_PMUX0_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | sam.PORT_PINCFG0_DRVSTR) - } -} - -// getPMux returns the value for the correct PMUX register for this pin. -func (p Pin) getPMux() uint8 { - switch p >> 1 { - case 0: - return sam.PORT.PMUX0_0.Get() - case 1: - return sam.PORT.PMUX0_1.Get() - case 2: - return sam.PORT.PMUX0_2.Get() - case 3: - return sam.PORT.PMUX0_3.Get() - case 4: - return sam.PORT.PMUX0_4.Get() - case 5: - return sam.PORT.PMUX0_5.Get() - case 6: - return sam.PORT.PMUX0_6.Get() - case 7: - return sam.PORT.PMUX0_7.Get() - case 8: - return sam.PORT.PMUX0_8.Get() - case 9: - return sam.PORT.PMUX0_9.Get() - case 10: - return sam.PORT.PMUX0_10.Get() - case 11: - return sam.PORT.PMUX0_11.Get() - case 12: - return sam.PORT.PMUX0_12.Get() - case 13: - return sam.PORT.PMUX0_13.Get() - case 14: - return sam.PORT.PMUX0_14.Get() - case 15: - return sam.PORT.PMUX0_15.Get() - default: - return 0 - } -} - -// setPMux sets the value for the correct PMUX register for this pin. -func (p Pin) setPMux(val uint8) { - switch p >> 1 { - case 0: - sam.PORT.PMUX0_0.Set(val) - case 1: - sam.PORT.PMUX0_1.Set(val) - case 2: - sam.PORT.PMUX0_2.Set(val) - case 3: - sam.PORT.PMUX0_3.Set(val) - case 4: - sam.PORT.PMUX0_4.Set(val) - case 5: - sam.PORT.PMUX0_5.Set(val) - case 6: - sam.PORT.PMUX0_6.Set(val) - case 7: - sam.PORT.PMUX0_7.Set(val) - case 8: - sam.PORT.PMUX0_8.Set(val) - case 9: - sam.PORT.PMUX0_9.Set(val) - case 10: - sam.PORT.PMUX0_10.Set(val) - case 11: - sam.PORT.PMUX0_11.Set(val) - case 12: - sam.PORT.PMUX0_12.Set(val) - case 13: - sam.PORT.PMUX0_13.Set(val) - case 14: - sam.PORT.PMUX0_14.Set(val) - case 15: - sam.PORT.PMUX0_15.Set(val) - } -} - -// getPinCfg returns the value for the correct PINCFG register for this pin. -func (p Pin) getPinCfg() uint8 { - switch p { - case 0: - return sam.PORT.PINCFG0_0.Get() - case 1: - return sam.PORT.PINCFG0_1.Get() - case 2: - return sam.PORT.PINCFG0_2.Get() - case 3: - return sam.PORT.PINCFG0_3.Get() - case 4: - return sam.PORT.PINCFG0_4.Get() - case 5: - return sam.PORT.PINCFG0_5.Get() - case 6: - return sam.PORT.PINCFG0_6.Get() - case 7: - return sam.PORT.PINCFG0_7.Get() - case 8: - return sam.PORT.PINCFG0_8.Get() - case 9: - return sam.PORT.PINCFG0_9.Get() - case 10: - return sam.PORT.PINCFG0_10.Get() - case 11: - return sam.PORT.PINCFG0_11.Get() - case 12: - return sam.PORT.PINCFG0_12.Get() - case 13: - return sam.PORT.PINCFG0_13.Get() - case 14: - return sam.PORT.PINCFG0_14.Get() - case 15: - return sam.PORT.PINCFG0_15.Get() - case 16: - return sam.PORT.PINCFG0_16.Get() - case 17: - return sam.PORT.PINCFG0_17.Get() - case 18: - return sam.PORT.PINCFG0_18.Get() - case 19: - return sam.PORT.PINCFG0_19.Get() - case 20: - return sam.PORT.PINCFG0_20.Get() - case 21: - return sam.PORT.PINCFG0_21.Get() - case 22: - return sam.PORT.PINCFG0_22.Get() - case 23: - return sam.PORT.PINCFG0_23.Get() - case 24: - return sam.PORT.PINCFG0_24.Get() - case 25: - return sam.PORT.PINCFG0_25.Get() - case 26: - return sam.PORT.PINCFG0_26.Get() - case 27: - return sam.PORT.PINCFG0_27.Get() - case 28: - return sam.PORT.PINCFG0_28.Get() - case 29: - return sam.PORT.PINCFG0_29.Get() - case 30: - return sam.PORT.PINCFG0_30.Get() - case 31: - return sam.PORT.PINCFG0_31.Get() - default: - return 0 - } -} - -// setPinCfg sets the value for the correct PINCFG register for this pin. -func (p Pin) setPinCfg(val uint8) { - switch p { - case 0: - sam.PORT.PINCFG0_0.Set(val) - case 1: - sam.PORT.PINCFG0_1.Set(val) - case 2: - sam.PORT.PINCFG0_2.Set(val) - case 3: - sam.PORT.PINCFG0_3.Set(val) - case 4: - sam.PORT.PINCFG0_4.Set(val) - case 5: - sam.PORT.PINCFG0_5.Set(val) - case 6: - sam.PORT.PINCFG0_6.Set(val) - case 7: - sam.PORT.PINCFG0_7.Set(val) - case 8: - sam.PORT.PINCFG0_8.Set(val) - case 9: - sam.PORT.PINCFG0_9.Set(val) - case 10: - sam.PORT.PINCFG0_10.Set(val) - case 11: - sam.PORT.PINCFG0_11.Set(val) - case 12: - sam.PORT.PINCFG0_12.Set(val) - case 13: - sam.PORT.PINCFG0_13.Set(val) - case 14: - sam.PORT.PINCFG0_14.Set(val) - case 15: - sam.PORT.PINCFG0_15.Set(val) - case 16: - sam.PORT.PINCFG0_16.Set(val) - case 17: - sam.PORT.PINCFG0_17.Set(val) - case 18: - sam.PORT.PINCFG0_18.Set(val) - case 19: - sam.PORT.PINCFG0_19.Set(val) - case 20: - sam.PORT.PINCFG0_20.Set(val) - case 21: - sam.PORT.PINCFG0_21.Set(val) - case 22: - sam.PORT.PINCFG0_22.Set(val) - case 23: - sam.PORT.PINCFG0_23.Set(val) - case 24: - sam.PORT.PINCFG0_24.Set(val) - case 25: - sam.PORT.PINCFG0_25.Set(val) - case 26: - sam.PORT.PINCFG0_26.Set(val) - case 27: - sam.PORT.PINCFG0_27.Set(val) - case 28: - sam.PORT.PINCFG0_28.Set(val) - case 29: - sam.PORT.PINCFG0_29.Set(val) - case 30: - sam.PORT.PINCFG0_30.Set(val) - case 31: - sam.PORT.PINCFG0_31.Set(val) - } -} diff --git a/emb/machine/machine_atsamd21g18.go b/emb/machine/machine_atsamd21g18.go deleted file mode 100644 index 9e845cf..0000000 --- a/emb/machine/machine_atsamd21g18.go +++ /dev/null @@ -1,606 +0,0 @@ -//go:build sam && atsamd21 && atsamd21g18 - -// Peripheral abstraction layer for the atsamd21. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD21-Family-DataSheet-DS40001882D.pdf -package machine - -import ( - "device/sam" - "runtime/interrupt" -) - -var ( - sercomUSART0 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM0_USART, SERCOM: 0} - sercomUSART1 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM1_USART, SERCOM: 1} - sercomUSART2 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM2_USART, SERCOM: 2} - sercomUSART3 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM3_USART, SERCOM: 3} - sercomUSART4 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM4_USART, SERCOM: 4} - sercomUSART5 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM5_USART, SERCOM: 5} - - sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0} - sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1} - sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2} - sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3} - sercomI2CM4 = &I2C{Bus: sam.SERCOM4_I2CM, SERCOM: 4} - sercomI2CM5 = &I2C{Bus: sam.SERCOM5_I2CM, SERCOM: 5} - - sercomSPIM0 = &SPI{Bus: sam.SERCOM0_SPI, SERCOM: 0} - sercomSPIM1 = &SPI{Bus: sam.SERCOM1_SPI, SERCOM: 1} - sercomSPIM2 = &SPI{Bus: sam.SERCOM2_SPI, SERCOM: 2} - sercomSPIM3 = &SPI{Bus: sam.SERCOM3_SPI, SERCOM: 3} - sercomSPIM4 = &SPI{Bus: sam.SERCOM4_SPI, SERCOM: 4} - sercomSPIM5 = &SPI{Bus: sam.SERCOM5_SPI, SERCOM: 5} -) - -func init() { - sercomUSART0.Interrupt = interrupt.New(sam.IRQ_SERCOM0, sercomUSART0.handleInterrupt) - sercomUSART1.Interrupt = interrupt.New(sam.IRQ_SERCOM1, sercomUSART1.handleInterrupt) - sercomUSART2.Interrupt = interrupt.New(sam.IRQ_SERCOM2, sercomUSART2.handleInterrupt) - sercomUSART3.Interrupt = interrupt.New(sam.IRQ_SERCOM3, sercomUSART3.handleInterrupt) - sercomUSART4.Interrupt = interrupt.New(sam.IRQ_SERCOM4, sercomUSART4.handleInterrupt) - sercomUSART5.Interrupt = interrupt.New(sam.IRQ_SERCOM5, sercomUSART5.handleInterrupt) -} - -// Return the register and mask to enable a given GPIO pin. This can be used to -// implement bit-banged drivers. -func (p Pin) PortMaskSet() (*uint32, uint32) { - // Note: using PORT_IOBUS for faster pin accesses. - // The regular PORT registers appear to take around 4 clock cycles to store, - // which is longer than the ws2812 driver expects. The IOBUS is is fast - // enough to avoid this issue. - if p < 32 { - return &sam.PORT_IOBUS.OUTSET0.Reg, 1 << uint8(p) - } else { - return &sam.PORT_IOBUS.OUTSET1.Reg, 1 << uint8(p-32) - } -} - -// Return the register and mask to disable a given port. This can be used to -// implement bit-banged drivers. -func (p Pin) PortMaskClear() (*uint32, uint32) { - if p < 32 { - return &sam.PORT_IOBUS.OUTCLR0.Reg, 1 << uint8(p) - } else { - return &sam.PORT_IOBUS.OUTCLR1.Reg, 1 << uint8(p-32) - } -} - -// Set the pin to high or low. -// Warning: only use this on an output pin! -func (p Pin) Set(high bool) { - if p < 32 { - if high { - sam.PORT.OUTSET0.Set(1 << uint8(p)) - } else { - sam.PORT.OUTCLR0.Set(1 << uint8(p)) - } - } else { - if high { - sam.PORT.OUTSET1.Set(1 << uint8(p-32)) - } else { - sam.PORT.OUTCLR1.Set(1 << uint8(p-32)) - } - } -} - -// Get returns the current value of a GPIO pin when configured as an input or as -// an output. -func (p Pin) Get() bool { - if p < 32 { - return (sam.PORT.IN0.Get()>>uint8(p))&1 > 0 - } else { - return (sam.PORT.IN1.Get()>>uint8(p-32))&1 > 0 - } -} - -// Configure this pin with the given configuration. -func (p Pin) Configure(config PinConfig) { - switch config.Mode { - case PinOutput: - if p < 32 { - sam.PORT.DIRSET0.Set(1 << uint8(p)) - // output is also set to input enable so pin can read back its own value - p.setPinCfg(sam.PORT_PINCFG0_INEN) - } else { - sam.PORT.DIRSET1.Set(1 << uint8(p-32)) - // output is also set to input enable so pin can read back its own value - p.setPinCfg(sam.PORT_PINCFG0_INEN) - } - - case PinInput: - if p < 32 { - sam.PORT.DIRCLR0.Set(1 << uint8(p)) - p.setPinCfg(sam.PORT_PINCFG0_INEN) - } else { - sam.PORT.DIRCLR1.Set(1 << uint8(p-32)) - p.setPinCfg(sam.PORT_PINCFG0_INEN) - } - - case PinInputPulldown: - if p < 32 { - sam.PORT.DIRCLR0.Set(1 << uint8(p)) - sam.PORT.OUTCLR0.Set(1 << uint8(p)) - p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN) - } else { - sam.PORT.DIRCLR1.Set(1 << uint8(p-32)) - sam.PORT.OUTCLR1.Set(1 << uint8(p-32)) - p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN) - } - - case PinInputPullup: - if p < 32 { - sam.PORT.DIRCLR0.Set(1 << uint8(p)) - sam.PORT.OUTSET0.Set(1 << uint8(p)) - p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN) - } else { - sam.PORT.DIRCLR1.Set(1 << uint8(p-32)) - sam.PORT.OUTSET1.Set(1 << uint8(p-32)) - p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN) - } - - case PinSERCOM: - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_PMUX0_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk - p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_PMUX0_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | sam.PORT_PINCFG0_DRVSTR | sam.PORT_PINCFG0_INEN) - - case PinSERCOMAlt: - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_PMUX0_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk - p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_PMUX0_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | sam.PORT_PINCFG0_DRVSTR) - - case PinCom: - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - p.setPMux(val | (uint8(PinCom) << sam.PORT_PMUX0_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk - p.setPMux(val | (uint8(PinCom) << sam.PORT_PMUX0_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_PINCFG0_PMUXEN) - case PinAnalog: - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk - p.setPMux(val | (uint8(PinAnalog) << sam.PORT_PMUX0_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk - p.setPMux(val | (uint8(PinAnalog) << sam.PORT_PMUX0_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | sam.PORT_PINCFG0_DRVSTR) - } -} - -// getPMux returns the value for the correct PMUX register for this pin. -func (p Pin) getPMux() uint8 { - switch uint8(p) >> 1 { - case 0: - return sam.PORT.PMUX0_0.Get() - case 1: - return sam.PORT.PMUX0_1.Get() - case 2: - return sam.PORT.PMUX0_2.Get() - case 3: - return sam.PORT.PMUX0_3.Get() - case 4: - return sam.PORT.PMUX0_4.Get() - case 5: - return sam.PORT.PMUX0_5.Get() - case 6: - return sam.PORT.PMUX0_6.Get() - case 7: - return sam.PORT.PMUX0_7.Get() - case 8: - return sam.PORT.PMUX0_8.Get() - case 9: - return sam.PORT.PMUX0_9.Get() - case 10: - return sam.PORT.PMUX0_10.Get() - case 11: - return sam.PORT.PMUX0_11.Get() - case 12: - return sam.PORT.PMUX0_12.Get() - case 13: - return sam.PORT.PMUX0_13.Get() - case 14: - return sam.PORT.PMUX0_14.Get() - case 15: - return sam.PORT.PMUX0_15.Get() - case 16: - return uint8(sam.PORT.PMUX1_0.Get()>>0) & 0xff - case 17: - return uint8(sam.PORT.PMUX1_0.Get()>>8) & 0xff - case 18: - return uint8(sam.PORT.PMUX1_0.Get()>>16) & 0xff - case 19: - return uint8(sam.PORT.PMUX1_0.Get()>>24) & 0xff - case 20: - return uint8(sam.PORT.PMUX1_4.Get()>>0) & 0xff - case 21: - return uint8(sam.PORT.PMUX1_4.Get()>>8) & 0xff - case 22: - return uint8(sam.PORT.PMUX1_4.Get()>>16) & 0xff - case 23: - return uint8(sam.PORT.PMUX1_4.Get()>>24) & 0xff - case 24: - return uint8(sam.PORT.PMUX1_8.Get()>>0) & 0xff - case 25: - return uint8(sam.PORT.PMUX1_8.Get()>>8) & 0xff - case 26: - return uint8(sam.PORT.PMUX1_8.Get()>>16) & 0xff - case 27: - return uint8(sam.PORT.PMUX1_8.Get()>>24) & 0xff - case 28: - return uint8(sam.PORT.PMUX1_12.Get()>>0) & 0xff - case 29: - return uint8(sam.PORT.PMUX1_12.Get()>>8) & 0xff - case 30: - return uint8(sam.PORT.PMUX1_12.Get()>>16) & 0xff - case 31: - return uint8(sam.PORT.PMUX1_12.Get()>>24) & 0xff - default: - return 0 - } -} - -// setPMux sets the value for the correct PMUX register for this pin. -func (p Pin) setPMux(val uint8) { - switch uint8(p) >> 1 { - case 0: - sam.PORT.PMUX0_0.Set(val) - case 1: - sam.PORT.PMUX0_1.Set(val) - case 2: - sam.PORT.PMUX0_2.Set(val) - case 3: - sam.PORT.PMUX0_3.Set(val) - case 4: - sam.PORT.PMUX0_4.Set(val) - case 5: - sam.PORT.PMUX0_5.Set(val) - case 6: - sam.PORT.PMUX0_6.Set(val) - case 7: - sam.PORT.PMUX0_7.Set(val) - case 8: - sam.PORT.PMUX0_8.Set(val) - case 9: - sam.PORT.PMUX0_9.Set(val) - case 10: - sam.PORT.PMUX0_10.Set(val) - case 11: - sam.PORT.PMUX0_11.Set(val) - case 12: - sam.PORT.PMUX0_12.Set(val) - case 13: - sam.PORT.PMUX0_13.Set(val) - case 14: - sam.PORT.PMUX0_14.Set(val) - case 15: - sam.PORT.PMUX0_15.Set(val) - case 16: - sam.PORT.PMUX1_0.ReplaceBits(uint32(val), 0xff, 0) - case 17: - sam.PORT.PMUX1_0.ReplaceBits(uint32(val), 0xff, 8) - case 18: - sam.PORT.PMUX1_0.ReplaceBits(uint32(val), 0xff, 16) - case 19: - sam.PORT.PMUX1_0.ReplaceBits(uint32(val), 0xff, 24) - case 20: - sam.PORT.PMUX1_4.ReplaceBits(uint32(val), 0xff, 0) - case 21: - sam.PORT.PMUX1_4.ReplaceBits(uint32(val), 0xff, 8) - case 22: - sam.PORT.PMUX1_4.ReplaceBits(uint32(val), 0xff, 16) - case 23: - sam.PORT.PMUX1_4.ReplaceBits(uint32(val), 0xff, 24) - case 24: - sam.PORT.PMUX1_8.ReplaceBits(uint32(val), 0xff, 0) - case 25: - sam.PORT.PMUX1_8.ReplaceBits(uint32(val), 0xff, 8) - case 26: - sam.PORT.PMUX1_8.ReplaceBits(uint32(val), 0xff, 16) - case 27: - sam.PORT.PMUX1_8.ReplaceBits(uint32(val), 0xff, 24) - case 28: - sam.PORT.PMUX1_12.ReplaceBits(uint32(val), 0xff, 0) - case 29: - sam.PORT.PMUX1_12.ReplaceBits(uint32(val), 0xff, 8) - case 30: - sam.PORT.PMUX1_12.ReplaceBits(uint32(val), 0xff, 16) - case 31: - sam.PORT.PMUX1_12.ReplaceBits(uint32(val), 0xff, 24) - } -} - -// getPinCfg returns the value for the correct PINCFG register for this pin. -func (p Pin) getPinCfg() uint8 { - switch p { - case 0: - return sam.PORT.PINCFG0_0.Get() - case 1: - return sam.PORT.PINCFG0_1.Get() - case 2: - return sam.PORT.PINCFG0_2.Get() - case 3: - return sam.PORT.PINCFG0_3.Get() - case 4: - return sam.PORT.PINCFG0_4.Get() - case 5: - return sam.PORT.PINCFG0_5.Get() - case 6: - return sam.PORT.PINCFG0_6.Get() - case 7: - return sam.PORT.PINCFG0_7.Get() - case 8: - return sam.PORT.PINCFG0_8.Get() - case 9: - return sam.PORT.PINCFG0_9.Get() - case 10: - return sam.PORT.PINCFG0_10.Get() - case 11: - return sam.PORT.PINCFG0_11.Get() - case 12: - return sam.PORT.PINCFG0_12.Get() - case 13: - return sam.PORT.PINCFG0_13.Get() - case 14: - return sam.PORT.PINCFG0_14.Get() - case 15: - return sam.PORT.PINCFG0_15.Get() - case 16: - return sam.PORT.PINCFG0_16.Get() - case 17: - return sam.PORT.PINCFG0_17.Get() - case 18: - return sam.PORT.PINCFG0_18.Get() - case 19: - return sam.PORT.PINCFG0_19.Get() - case 20: - return sam.PORT.PINCFG0_20.Get() - case 21: - return sam.PORT.PINCFG0_21.Get() - case 22: - return sam.PORT.PINCFG0_22.Get() - case 23: - return sam.PORT.PINCFG0_23.Get() - case 24: - return sam.PORT.PINCFG0_24.Get() - case 25: - return sam.PORT.PINCFG0_25.Get() - case 26: - return sam.PORT.PINCFG0_26.Get() - case 27: - return sam.PORT.PINCFG0_27.Get() - case 28: - return sam.PORT.PINCFG0_28.Get() - case 29: - return sam.PORT.PINCFG0_29.Get() - case 30: - return sam.PORT.PINCFG0_30.Get() - case 31: - return sam.PORT.PINCFG0_31.Get() - case 32: // PB00 - return uint8(sam.PORT.PINCFG1_0.Get()>>0) & 0xff - case 33: // PB01 - return uint8(sam.PORT.PINCFG1_0.Get()>>8) & 0xff - case 34: // PB02 - return uint8(sam.PORT.PINCFG1_0.Get()>>16) & 0xff - case 35: // PB03 - return uint8(sam.PORT.PINCFG1_0.Get()>>24) & 0xff - case 36: // PB04 - return uint8(sam.PORT.PINCFG1_4.Get()>>0) & 0xff - case 37: // PB05 - return uint8(sam.PORT.PINCFG1_4.Get()>>8) & 0xff - case 38: // PB06 - return uint8(sam.PORT.PINCFG1_4.Get()>>16) & 0xff - case 39: // PB07 - return uint8(sam.PORT.PINCFG1_4.Get()>>24) & 0xff - case 40: // PB08 - return uint8(sam.PORT.PINCFG1_8.Get()>>0) & 0xff - case 41: // PB09 - return uint8(sam.PORT.PINCFG1_8.Get()>>8) & 0xff - case 42: // PB10 - return uint8(sam.PORT.PINCFG1_8.Get()>>16) & 0xff - case 43: // PB11 - return uint8(sam.PORT.PINCFG1_8.Get()>>24) & 0xff - case 44: // PB12 - return uint8(sam.PORT.PINCFG1_12.Get()>>0) & 0xff - case 45: // PB13 - return uint8(sam.PORT.PINCFG1_12.Get()>>8) & 0xff - case 46: // PB14 - return uint8(sam.PORT.PINCFG1_12.Get()>>16) & 0xff - case 47: // PB15 - return uint8(sam.PORT.PINCFG1_12.Get()>>24) & 0xff - case 48: // PB16 - return uint8(sam.PORT.PINCFG1_16.Get()>>0) & 0xff - case 49: // PB17 - return uint8(sam.PORT.PINCFG1_16.Get()>>8) & 0xff - case 50: // PB18 - return uint8(sam.PORT.PINCFG1_16.Get()>>16) & 0xff - case 51: // PB19 - return uint8(sam.PORT.PINCFG1_16.Get()>>24) & 0xff - case 52: // PB20 - return uint8(sam.PORT.PINCFG1_20.Get()>>0) & 0xff - case 53: // PB21 - return uint8(sam.PORT.PINCFG1_20.Get()>>8) & 0xff - case 54: // PB22 - return uint8(sam.PORT.PINCFG1_20.Get()>>16) & 0xff - case 55: // PB23 - return uint8(sam.PORT.PINCFG1_20.Get()>>24) & 0xff - case 56: // PB24 - return uint8(sam.PORT.PINCFG1_24.Get()>>0) & 0xff - case 57: // PB25 - return uint8(sam.PORT.PINCFG1_24.Get()>>8) & 0xff - case 58: // PB26 - return uint8(sam.PORT.PINCFG1_24.Get()>>16) & 0xff - case 59: // PB27 - return uint8(sam.PORT.PINCFG1_24.Get()>>24) & 0xff - case 60: // PB28 - return uint8(sam.PORT.PINCFG1_28.Get()>>0) & 0xff - case 61: // PB29 - return uint8(sam.PORT.PINCFG1_28.Get()>>8) & 0xff - case 62: // PB30 - return uint8(sam.PORT.PINCFG1_28.Get()>>16) & 0xff - case 63: // PB31 - return uint8(sam.PORT.PINCFG1_28.Get()>>24) & 0xff - default: - return 0 - } -} - -// setPinCfg sets the value for the correct PINCFG register for this pin. -func (p Pin) setPinCfg(val uint8) { - switch p { - case 0: - sam.PORT.PINCFG0_0.Set(val) - case 1: - sam.PORT.PINCFG0_1.Set(val) - case 2: - sam.PORT.PINCFG0_2.Set(val) - case 3: - sam.PORT.PINCFG0_3.Set(val) - case 4: - sam.PORT.PINCFG0_4.Set(val) - case 5: - sam.PORT.PINCFG0_5.Set(val) - case 6: - sam.PORT.PINCFG0_6.Set(val) - case 7: - sam.PORT.PINCFG0_7.Set(val) - case 8: - sam.PORT.PINCFG0_8.Set(val) - case 9: - sam.PORT.PINCFG0_9.Set(val) - case 10: - sam.PORT.PINCFG0_10.Set(val) - case 11: - sam.PORT.PINCFG0_11.Set(val) - case 12: - sam.PORT.PINCFG0_12.Set(val) - case 13: - sam.PORT.PINCFG0_13.Set(val) - case 14: - sam.PORT.PINCFG0_14.Set(val) - case 15: - sam.PORT.PINCFG0_15.Set(val) - case 16: - sam.PORT.PINCFG0_16.Set(val) - case 17: - sam.PORT.PINCFG0_17.Set(val) - case 18: - sam.PORT.PINCFG0_18.Set(val) - case 19: - sam.PORT.PINCFG0_19.Set(val) - case 20: - sam.PORT.PINCFG0_20.Set(val) - case 21: - sam.PORT.PINCFG0_21.Set(val) - case 22: - sam.PORT.PINCFG0_22.Set(val) - case 23: - sam.PORT.PINCFG0_23.Set(val) - case 24: - sam.PORT.PINCFG0_24.Set(val) - case 25: - sam.PORT.PINCFG0_25.Set(val) - case 26: - sam.PORT.PINCFG0_26.Set(val) - case 27: - sam.PORT.PINCFG0_27.Set(val) - case 28: - sam.PORT.PINCFG0_28.Set(val) - case 29: - sam.PORT.PINCFG0_29.Set(val) - case 30: - sam.PORT.PINCFG0_30.Set(val) - case 31: - sam.PORT.PINCFG0_31.Set(val) - case 32: // PB00 - sam.PORT.PINCFG1_0.ReplaceBits(uint32(val), 0xff, 0) - case 33: // PB01 - sam.PORT.PINCFG1_0.ReplaceBits(uint32(val), 0xff, 8) - case 34: // PB02 - sam.PORT.PINCFG1_0.ReplaceBits(uint32(val), 0xff, 16) - case 35: // PB03 - sam.PORT.PINCFG1_0.ReplaceBits(uint32(val), 0xff, 24) - case 36: // PB04 - sam.PORT.PINCFG1_4.ReplaceBits(uint32(val), 0xff, 0) - case 37: // PB05 - sam.PORT.PINCFG1_4.ReplaceBits(uint32(val), 0xff, 8) - case 38: // PB06 - sam.PORT.PINCFG1_4.ReplaceBits(uint32(val), 0xff, 16) - case 39: // PB07 - sam.PORT.PINCFG1_4.ReplaceBits(uint32(val), 0xff, 24) - case 40: // PB08 - sam.PORT.PINCFG1_8.ReplaceBits(uint32(val), 0xff, 0) - case 41: // PB09 - sam.PORT.PINCFG1_8.ReplaceBits(uint32(val), 0xff, 8) - case 42: // PB10 - sam.PORT.PINCFG1_8.ReplaceBits(uint32(val), 0xff, 16) - case 43: // PB11 - sam.PORT.PINCFG1_8.ReplaceBits(uint32(val), 0xff, 24) - case 44: // PB12 - sam.PORT.PINCFG1_12.ReplaceBits(uint32(val), 0xff, 0) - case 45: // PB13 - sam.PORT.PINCFG1_12.ReplaceBits(uint32(val), 0xff, 8) - case 46: // PB14 - sam.PORT.PINCFG1_12.ReplaceBits(uint32(val), 0xff, 16) - case 47: // PB15 - sam.PORT.PINCFG1_12.ReplaceBits(uint32(val), 0xff, 24) - case 48: // PB16 - sam.PORT.PINCFG1_16.ReplaceBits(uint32(val), 0xff, 0) - case 49: // PB17 - sam.PORT.PINCFG1_16.ReplaceBits(uint32(val), 0xff, 8) - case 50: // PB18 - sam.PORT.PINCFG1_16.ReplaceBits(uint32(val), 0xff, 16) - case 51: // PB19 - sam.PORT.PINCFG1_16.ReplaceBits(uint32(val), 0xff, 24) - case 52: // PB20 - sam.PORT.PINCFG1_20.ReplaceBits(uint32(val), 0xff, 0) - case 53: // PB21 - sam.PORT.PINCFG1_20.ReplaceBits(uint32(val), 0xff, 8) - case 54: // PB22 - sam.PORT.PINCFG1_20.ReplaceBits(uint32(val), 0xff, 16) - case 55: // PB23 - sam.PORT.PINCFG1_20.ReplaceBits(uint32(val), 0xff, 24) - case 56: // PB24 - sam.PORT.PINCFG1_24.ReplaceBits(uint32(val), 0xff, 0) - case 57: // PB25 - sam.PORT.PINCFG1_24.ReplaceBits(uint32(val), 0xff, 8) - case 58: // PB26 - sam.PORT.PINCFG1_24.ReplaceBits(uint32(val), 0xff, 16) - case 59: // PB27 - sam.PORT.PINCFG1_24.ReplaceBits(uint32(val), 0xff, 24) - case 60: // PB28 - sam.PORT.PINCFG1_28.ReplaceBits(uint32(val), 0xff, 0) - case 61: // PB29 - sam.PORT.PINCFG1_28.ReplaceBits(uint32(val), 0xff, 8) - case 62: // PB30 - sam.PORT.PINCFG1_28.ReplaceBits(uint32(val), 0xff, 16) - case 63: // PB31 - sam.PORT.PINCFG1_28.ReplaceBits(uint32(val), 0xff, 24) - } -} diff --git a/emb/machine/machine_atsamd51.go b/emb/machine/machine_atsamd51.go deleted file mode 100644 index 576f454..0000000 --- a/emb/machine/machine_atsamd51.go +++ /dev/null @@ -1,2358 +0,0 @@ -//go:build (sam && atsamd51) || (sam && atsame5x) - -// Peripheral abstraction layer for the atsamd51. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf -package machine - -import ( - "device/arm" - "device/sam" - "errors" - "internal/binary" - "runtime/interrupt" - "unsafe" -) - -const deviceName = sam.Device - -// DS60001507, Section 9.6: Serial Number -var deviceIDAddr = []uintptr{0x008061FC, 0x00806010, 0x00806014, 0x00806018} - -func CPUFrequency() uint32 { - return 120000000 -} - -const ( - PinAnalog PinMode = 1 - PinSERCOM PinMode = 2 - PinSERCOMAlt PinMode = 3 - PinTimer PinMode = 4 - PinTimerAlt PinMode = 5 - PinTCCPDEC PinMode = 6 - PinCom PinMode = 7 - PinSDHC PinMode = 8 - PinI2S PinMode = 9 - PinPCC PinMode = 10 - PinGMAC PinMode = 11 - PinACCLK PinMode = 12 - PinCCL PinMode = 13 - PinDigital PinMode = 14 - PinInput PinMode = 15 - PinInputPullup PinMode = 16 - PinOutput PinMode = 17 - PinTCCE PinMode = PinTimer - PinTCCF PinMode = PinTimerAlt - PinTCCG PinMode = PinTCCPDEC - PinInputPulldown PinMode = 18 - PinCAN PinMode = 19 - PinCAN0 PinMode = PinSDHC - PinCAN1 PinMode = PinCom -) - -type PinChange uint8 - -// Pin change interrupt constants for SetInterrupt. -const ( - PinRising PinChange = sam.EIC_CONFIG_SENSE0_RISE - PinFalling PinChange = sam.EIC_CONFIG_SENSE0_FALL - PinToggle PinChange = sam.EIC_CONFIG_SENSE0_BOTH -) - -// Callbacks to be called for pins configured with SetInterrupt. Unfortunately, -// we also need to keep track of which interrupt channel is used by which pin, -// as the only alternative would be iterating through all pins. -// -// We're using the magic constant 16 here because the SAM D21 has 16 interrupt -// channels configurable for pins. -var ( - interruptPins [16]Pin // warning: the value is invalid when pinCallbacks[i] is not set! - pinCallbacks [16]func(Pin) -) - -// Hardware pins -const ( - PA00 Pin = 0 - PA01 Pin = 1 - PA02 Pin = 2 - PA03 Pin = 3 - PA04 Pin = 4 - PA05 Pin = 5 - PA06 Pin = 6 - PA07 Pin = 7 - PA08 Pin = 8 // peripherals: TCC0 channel 0, TCC1 channel 4 - PA09 Pin = 9 // peripherals: TCC0 channel 1, TCC1 channel 5 - PA10 Pin = 10 // peripherals: TCC0 channel 2, TCC1 channel 6 - PA11 Pin = 11 // peripherals: TCC0 channel 3, TCC1 channel 7 - PA12 Pin = 12 // peripherals: TCC0 channel 6, TCC1 channel 2 - PA13 Pin = 13 // peripherals: TCC0 channel 7, TCC1 channel 3 - PA14 Pin = 14 // peripherals: TCC2 channel 0, TCC1 channel 2 - PA15 Pin = 15 // peripherals: TCC2 channel 1, TCC1 channel 3 - PA16 Pin = 16 // peripherals: TCC1 channel 0, TCC0 channel 4 - PA17 Pin = 17 // peripherals: TCC1 channel 1, TCC0 channel 5 - PA18 Pin = 18 // peripherals: TCC1 channel 2, TCC0 channel 6 - PA19 Pin = 19 // peripherals: TCC1 channel 3, TCC0 channel 7 - PA20 Pin = 20 // peripherals: TCC1 channel 4, TCC0 channel 0 - PA21 Pin = 21 // peripherals: TCC1 channel 5, TCC0 channel 1 - PA22 Pin = 22 // peripherals: TCC1 channel 6, TCC0 channel 2 - PA23 Pin = 23 // peripherals: TCC1 channel 7, TCC0 channel 3 - PA24 Pin = 24 // peripherals: TCC2 channel 2 - PA25 Pin = 25 // peripherals: TCC2 channel 3 - PA26 Pin = 26 - PA27 Pin = 27 - PA28 Pin = 28 - PA29 Pin = 29 - PA30 Pin = 30 // peripherals: TCC2 channel 0 - PA31 Pin = 31 // peripherals: TCC2 channel 1 - PB00 Pin = 32 - PB01 Pin = 33 - PB02 Pin = 34 // peripherals: TCC2 channel 2 - PB03 Pin = 35 // peripherals: TCC2 channel 3 - PB04 Pin = 36 - PB05 Pin = 37 - PB06 Pin = 38 - PB07 Pin = 39 - PB08 Pin = 40 - PB09 Pin = 41 - PB10 Pin = 42 // peripherals: TCC0 channel 4, TCC1 channel 0 - PB11 Pin = 43 // peripherals: TCC0 channel 5, TCC1 channel 1 - PB12 Pin = 44 // peripherals: TCC3 channel 0, TCC0 channel 0 - PB13 Pin = 45 // peripherals: TCC3 channel 1, TCC0 channel 1 - PB14 Pin = 46 // peripherals: TCC4 channel 0, TCC0 channel 2 - PB15 Pin = 47 // peripherals: TCC4 channel 1, TCC0 channel 3 - PB16 Pin = 48 // peripherals: TCC3 channel 0, TCC0 channel 4 - PB17 Pin = 49 // peripherals: TCC3 channel 1, TCC0 channel 5 - PB18 Pin = 50 // peripherals: TCC1 channel 0 - PB19 Pin = 51 // peripherals: TCC1 channel 1 - PB20 Pin = 52 // peripherals: TCC1 channel 2 - PB21 Pin = 53 // peripherals: TCC1 channel 3 - PB22 Pin = 54 - PB23 Pin = 55 - PB24 Pin = 56 - PB25 Pin = 57 - PB26 Pin = 58 // peripherals: TCC1 channel 2 - PB27 Pin = 59 // peripherals: TCC1 channel 3 - PB28 Pin = 60 // peripherals: TCC1 channel 4 - PB29 Pin = 61 // peripherals: TCC1 channel 5 - PB30 Pin = 62 // peripherals: TCC4 channel 0, TCC0 channel 6 - PB31 Pin = 63 // peripherals: TCC4 channel 1, TCC0 channel 7 - PC00 Pin = 64 - PC01 Pin = 65 - PC02 Pin = 66 - PC03 Pin = 67 - PC04 Pin = 68 // peripherals: TCC0 channel 0 - PC05 Pin = 69 // peripherals: TCC0 channel 1 - PC06 Pin = 70 - PC07 Pin = 71 - PC08 Pin = 72 - PC09 Pin = 73 - PC10 Pin = 74 // peripherals: TCC0 channel 0, TCC1 channel 4 - PC11 Pin = 75 // peripherals: TCC0 channel 1, TCC1 channel 5 - PC12 Pin = 76 // peripherals: TCC0 channel 2, TCC1 channel 6 - PC13 Pin = 77 // peripherals: TCC0 channel 3, TCC1 channel 7 - PC14 Pin = 78 // peripherals: TCC0 channel 4, TCC1 channel 0 - PC15 Pin = 79 // peripherals: TCC0 channel 5, TCC1 channel 1 - PC16 Pin = 80 // peripherals: TCC0 channel 0 - PC17 Pin = 81 // peripherals: TCC0 channel 1 - PC18 Pin = 82 // peripherals: TCC0 channel 2 - PC19 Pin = 83 // peripherals: TCC0 channel 3 - PC20 Pin = 84 // peripherals: TCC0 channel 4 - PC21 Pin = 85 // peripherals: TCC0 channel 5 - PC22 Pin = 86 // peripherals: TCC0 channel 6 - PC23 Pin = 87 // peripherals: TCC0 channel 7 - PC24 Pin = 88 - PC25 Pin = 89 - PC26 Pin = 90 - PC27 Pin = 91 - PC28 Pin = 92 - PC29 Pin = 93 - PC30 Pin = 94 - PC31 Pin = 95 - PD00 Pin = 96 - PD01 Pin = 97 - PD02 Pin = 98 - PD03 Pin = 99 - PD04 Pin = 100 - PD05 Pin = 101 - PD06 Pin = 102 - PD07 Pin = 103 - PD08 Pin = 104 // peripherals: TCC0 channel 1 - PD09 Pin = 105 // peripherals: TCC0 channel 2 - PD10 Pin = 106 // peripherals: TCC0 channel 3 - PD11 Pin = 107 // peripherals: TCC0 channel 4 - PD12 Pin = 108 // peripherals: TCC0 channel 5 - PD13 Pin = 109 // peripherals: TCC0 channel 6 - PD14 Pin = 110 - PD15 Pin = 111 - PD16 Pin = 112 - PD17 Pin = 113 - PD18 Pin = 114 - PD19 Pin = 115 - PD20 Pin = 116 // peripherals: TCC1 channel 0 - PD21 Pin = 117 // peripherals: TCC1 channel 1 - PD22 Pin = 118 - PD23 Pin = 119 - PD24 Pin = 120 - PD25 Pin = 121 - PD26 Pin = 122 - PD27 Pin = 123 - PD28 Pin = 124 - PD29 Pin = 125 - PD30 Pin = 126 - PD31 Pin = 127 -) - -const ( - pinPadMapSERCOM0Pad0 uint16 = 0x1000 - pinPadMapSERCOM1Pad0 uint16 = 0x2000 - pinPadMapSERCOM2Pad0 uint16 = 0x3000 - pinPadMapSERCOM3Pad0 uint16 = 0x4000 - pinPadMapSERCOM4Pad0 uint16 = 0x5000 - pinPadMapSERCOM5Pad0 uint16 = 0x6000 - pinPadMapSERCOM6Pad0 uint16 = 0x7000 - pinPadMapSERCOM7Pad0 uint16 = 0x8000 - pinPadMapSERCOM0Pad2 uint16 = 0x1200 - pinPadMapSERCOM1Pad2 uint16 = 0x2200 - pinPadMapSERCOM2Pad2 uint16 = 0x3200 - pinPadMapSERCOM3Pad2 uint16 = 0x4200 - pinPadMapSERCOM4Pad2 uint16 = 0x5200 - pinPadMapSERCOM5Pad2 uint16 = 0x6200 - pinPadMapSERCOM6Pad2 uint16 = 0x7200 - pinPadMapSERCOM7Pad2 uint16 = 0x8200 - - pinPadMapSERCOM0AltPad0 uint16 = 0x0010 - pinPadMapSERCOM1AltPad0 uint16 = 0x0020 - pinPadMapSERCOM2AltPad0 uint16 = 0x0030 - pinPadMapSERCOM3AltPad0 uint16 = 0x0040 - pinPadMapSERCOM4AltPad0 uint16 = 0x0050 - pinPadMapSERCOM5AltPad0 uint16 = 0x0060 - pinPadMapSERCOM6AltPad0 uint16 = 0x0070 - pinPadMapSERCOM7AltPad0 uint16 = 0x0080 - pinPadMapSERCOM0AltPad1 uint16 = 0x0011 - pinPadMapSERCOM1AltPad1 uint16 = 0x0021 - pinPadMapSERCOM2AltPad1 uint16 = 0x0031 - pinPadMapSERCOM3AltPad1 uint16 = 0x0041 - pinPadMapSERCOM4AltPad1 uint16 = 0x0051 - pinPadMapSERCOM5AltPad1 uint16 = 0x0061 - pinPadMapSERCOM6AltPad1 uint16 = 0x0071 - pinPadMapSERCOM7AltPad1 uint16 = 0x0081 - pinPadMapSERCOM0AltPad2 uint16 = 0x0012 - pinPadMapSERCOM1AltPad2 uint16 = 0x0022 - pinPadMapSERCOM2AltPad2 uint16 = 0x0032 - pinPadMapSERCOM3AltPad2 uint16 = 0x0042 - pinPadMapSERCOM4AltPad2 uint16 = 0x0052 - pinPadMapSERCOM5AltPad2 uint16 = 0x0062 - pinPadMapSERCOM6AltPad2 uint16 = 0x0072 - pinPadMapSERCOM7AltPad2 uint16 = 0x0082 -) - -// pinPadMapping lists which pins have which SERCOMs attached to them. -// The encoding is rather dense, with each uint16 encoding two pins and both -// SERCOM and SERCOM-ALT. -// -// Observations: -// - There are eight SERCOMs. Those SERCOM numbers can be encoded in 4 bits. -// - Even pad numbers are usually on even pins, and odd pad numbers are usually -// on odd pins. The exception is SERCOM-ALT, which sometimes swaps pad 0 and 1. -// With that, there is still an invariant that the pad number for an odd pin is -// the pad number for the corresponding even pin with the low bit toggled. -// - Pin pads come in pairs. If PA00 has pad 0, then PA01 has pad 1. -// -// With this information, we can encode SERCOM pin/pad numbers much more -// efficiently. Due to pads coming in pairs, we can ignore half the pins: the -// information for an odd pin can be calculated easily from the preceding even -// pin. -// -// Each word below is split in two bytes. The 8 high bytes are for SERCOM and -// the 8 low bits are for SERCOM-ALT. Of each byte, the 4 high bits encode the -// SERCOM + 1 while the two low bits encodes the pad number (the pad number for -// the odd pin can be trivially calculated by toggling the low bit of the pad -// number). It encodes SERCOM + 1 instead of just the SERCOM number, to make it -// easy to check whether a nibble is set at all. -// -// Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/60001507E.pdf -var pinPadMapping = [64]uint16{ - // page 32 - PA00 / 2: 0 | pinPadMapSERCOM1AltPad0, - - // page 33 - PB08 / 2: 0 | pinPadMapSERCOM4AltPad0, - PA04 / 2: 0 | pinPadMapSERCOM0AltPad0, - PA06 / 2: 0 | pinPadMapSERCOM0AltPad2, - PC04 / 2: pinPadMapSERCOM6Pad0 | 0, - PC06 / 2: pinPadMapSERCOM6Pad2 | 0, - PA08 / 2: pinPadMapSERCOM0Pad0 | pinPadMapSERCOM2AltPad1, - PA10 / 2: pinPadMapSERCOM0Pad2 | pinPadMapSERCOM2AltPad2, - PB10 / 2: 0 | pinPadMapSERCOM4AltPad2, - PB12 / 2: pinPadMapSERCOM4Pad0 | 0, - PB14 / 2: pinPadMapSERCOM4Pad2 | 0, - PD08 / 2: pinPadMapSERCOM7Pad0 | pinPadMapSERCOM6AltPad1, - PD10 / 2: pinPadMapSERCOM7Pad2 | pinPadMapSERCOM6AltPad2, - PC10 / 2: pinPadMapSERCOM6Pad2 | pinPadMapSERCOM7AltPad2, - - // page 34 - PC12 / 2: pinPadMapSERCOM7Pad0 | pinPadMapSERCOM6AltPad1, - PC14 / 2: pinPadMapSERCOM7Pad2 | pinPadMapSERCOM6AltPad2, - PA12 / 2: pinPadMapSERCOM2Pad0 | pinPadMapSERCOM4AltPad1, - PA14 / 2: pinPadMapSERCOM2Pad2 | pinPadMapSERCOM4AltPad2, - PA16 / 2: pinPadMapSERCOM1Pad0 | pinPadMapSERCOM3AltPad1, - PA18 / 2: pinPadMapSERCOM1Pad2 | pinPadMapSERCOM3AltPad2, - PC16 / 2: pinPadMapSERCOM6Pad0 | pinPadMapSERCOM0AltPad1, - PC18 / 2: pinPadMapSERCOM6Pad2 | pinPadMapSERCOM0AltPad2, - PC22 / 2: pinPadMapSERCOM1Pad0 | pinPadMapSERCOM3AltPad1, - PD20 / 2: pinPadMapSERCOM1Pad2 | pinPadMapSERCOM3AltPad2, - PB16 / 2: pinPadMapSERCOM5Pad0 | 0, - PB18 / 2: pinPadMapSERCOM5Pad2 | pinPadMapSERCOM7AltPad2, - - // page 35 - PB20 / 2: pinPadMapSERCOM3Pad0 | pinPadMapSERCOM7AltPad1, - PA20 / 2: pinPadMapSERCOM5Pad2 | pinPadMapSERCOM3AltPad2, - PA22 / 2: pinPadMapSERCOM3Pad0 | pinPadMapSERCOM5AltPad1, - PA24 / 2: pinPadMapSERCOM3Pad2 | pinPadMapSERCOM5AltPad2, - PB22 / 2: pinPadMapSERCOM1Pad2 | pinPadMapSERCOM5AltPad2, - PB24 / 2: pinPadMapSERCOM0Pad0 | pinPadMapSERCOM2AltPad1, - PB26 / 2: pinPadMapSERCOM2Pad0 | pinPadMapSERCOM4AltPad1, - PB28 / 2: pinPadMapSERCOM2Pad2 | pinPadMapSERCOM4AltPad2, - PC24 / 2: pinPadMapSERCOM0Pad2 | pinPadMapSERCOM2AltPad2, - //PC26 / 2: pinPadMapSERCOM1Pad1 | 0, // note: PC26 doesn't support SERCOM, but PC27 does - //PC28 / 2: pinPadMapSERCOM1Pad1 | 0, // note: PC29 doesn't exist in the datasheet? - PA30 / 2: 0 | pinPadMapSERCOM1AltPad2, - - // page 36 - PB30 / 2: 0 | pinPadMapSERCOM5AltPad1, - PB00 / 2: 0 | pinPadMapSERCOM5AltPad2, - PB02 / 2: 0 | pinPadMapSERCOM5AltPad0, -} - -// findPinPadMapping looks up the pad number and the pinmode for a given pin and -// SERCOM number. The result can either be SERCOM, SERCOM-ALT, or "not found" -// (indicated by returning ok=false). The pad number is returned to calculate -// the DOPO/DIPO bitfields of the various serial peripherals. -func findPinPadMapping(sercom uint8, pin Pin) (pinMode PinMode, pad uint32, ok bool) { - if int(pin)/2 >= len(pinPadMapping) { - // This is probably NoPin, for which no mapping is available. - return - } - - bytes := pinPadMapping[pin/2] - upper := byte(bytes >> 8) - lower := byte(bytes & 0xff) - - if upper != 0 { - // SERCOM - if (upper>>4)-1 == sercom { - pinMode = PinSERCOM - pad |= uint32(upper % 4) - ok = true - } - } - if lower != 0 { - // SERCOM-ALT - if (lower>>4)-1 == sercom { - pinMode = PinSERCOMAlt - pad |= uint32(lower % 4) - ok = true - } - } - - if ok { - // If the pin is uneven, toggle the lowest bit of the pad number. - if pin&1 != 0 { - pad ^= 1 - } - } - return -} - -// SetInterrupt sets an interrupt to be executed when a particular pin changes -// state. The pin should already be configured as an input, including a pull up -// or down if no external pull is provided. -// -// This call will replace a previously set callback on this pin. You can pass a -// nil func to unset the pin change interrupt. If you do so, the change -// parameter is ignored and can be set to any value (such as 0). -func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error { - // Most pins follow a common pattern where the EXTINT value is the pin - // number modulo 16. However, there are a few exceptions, as you can see - // below. - extint := uint8(0) - - switch p { - case PA08: - // Connected to NMI. This is not currently supported. - return ErrInvalidInputPin - case PB26: - extint = 12 - case PB27: - extint = 13 - case PB28: - extint = 14 - case PB29: - extint = 15 - case PC07: - extint = 9 - case PD08: - extint = 3 - case PD09: - extint = 4 - case PD10: - extint = 5 - case PD11: - extint = 6 - case PD12: - extint = 7 - case PD20: - extint = 10 - case PD21: - extint = 11 - default: - // All other pins follow a normal pattern. - extint = uint8(p) % 16 - } - - if callback == nil { - // Disable this pin interrupt (if it was enabled). - sam.EIC.INTENCLR.Set(1 << extint) - if pinCallbacks[extint] != nil { - pinCallbacks[extint] = nil - } - return nil - } - - if pinCallbacks[extint] != nil { - // The pin was already configured. - // To properly re-configure a pin, unset it first and set a new - // configuration. - return ErrNoPinChangeChannel - } - pinCallbacks[extint] = callback - interruptPins[extint] = p - - if !sam.EIC.CTRLA.HasBits(sam.EIC_CTRLA_ENABLE) { - // EIC peripheral has not yet been initialized. Initialize it now. - - // The EIC needs two clocks: CLK_EIC_APB and GCLK_EIC. CLK_EIC_APB is - // enabled by default, so doesn't have to be re-enabled. The other is - // required for detecting edges and must be enabled manually. - sam.GCLK.PCHCTRL[4].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - - // should not be necessary (CLKCTRL is not synchronized) - for sam.GCLK.SYNCBUSY.HasBits(sam.GCLK_SYNCBUSY_GENCTRL_GCLK0 << sam.GCLK_SYNCBUSY_GENCTRL_Pos) { - } - } - - // CONFIG register is enable-protected, so disable EIC. - sam.EIC.CTRLA.ClearBits(sam.EIC_CTRLA_ENABLE) - - // Configure this pin. Set the 4 bits of the EIC.CONFIGx register to the - // sense value (filter bit set to 0, sense bits set to the change value). - addr := &sam.EIC.CONFIG[0] - if extint >= 8 { - addr = &sam.EIC.CONFIG[1] - } - pos := (extint % 8) * 4 // bit position in register - addr.ReplaceBits(uint32(change), 0xf, pos) - - // Enable external interrupt for this pin. - sam.EIC.INTENSET.Set(1 << extint) - - sam.EIC.CTRLA.Set(sam.EIC_CTRLA_ENABLE) - for sam.EIC.SYNCBUSY.HasBits(sam.EIC_SYNCBUSY_ENABLE) { - } - - // Set the PMUXEN flag, while keeping the INEN and PULLEN flags (if they - // were set before). This avoids clearing the pin pull mode while - // configuring the pin interrupt. - p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | (p.getPinCfg() & (sam.PORT_GROUP_PINCFG_INEN | sam.PORT_GROUP_PINCFG_PULLEN))) - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk - p.setPMux(val | (0 << sam.PORT_GROUP_PMUX_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk - p.setPMux(val | (0 << sam.PORT_GROUP_PMUX_PMUXE_Pos)) - } - - handleEICInterrupt := func(interrupt.Interrupt) { - flags := sam.EIC.INTFLAG.Get() - sam.EIC.INTFLAG.Set(flags) // clear interrupt - for i := uint(0); i < 16; i++ { // there are 16 channels - if flags&(1<>pin_in_group)&1 > 0 -} - -// Toggle switches an output pin from low to high or from high to low. -// Warning: only use this on an output pin! -func (p Pin) Toggle() { - group, pin_in_group := p.getPinGrouping() - sam.PORT.GROUP[group].OUTTGL.Set(1 << pin_in_group) -} - -// Configure this pin with the given configuration. -func (p Pin) Configure(config PinConfig) { - group, pin_in_group := p.getPinGrouping() - switch config.Mode { - case PinOutput: - sam.PORT.GROUP[group].DIRSET.Set(1 << pin_in_group) - // output is also set to input enable so pin can read back its own value - p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN) - - case PinInput: - sam.PORT.GROUP[group].DIRCLR.Set(1 << pin_in_group) - p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN) - - case PinInputPulldown: - sam.PORT.GROUP[group].DIRCLR.Set(1 << pin_in_group) - sam.PORT.GROUP[group].OUTCLR.Set(1 << pin_in_group) - p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN | sam.PORT_GROUP_PINCFG_PULLEN) - - case PinInputPullup: - sam.PORT.GROUP[group].DIRCLR.Set(1 << pin_in_group) - sam.PORT.GROUP[group].OUTSET.Set(1 << pin_in_group) - p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN | sam.PORT_GROUP_PINCFG_PULLEN) - - case PinSERCOM: - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk - p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_GROUP_PMUX_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk - p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_GROUP_PMUX_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | sam.PORT_GROUP_PINCFG_DRVSTR | sam.PORT_GROUP_PINCFG_INEN) - - case PinSERCOMAlt: - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk - p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_GROUP_PMUX_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk - p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_GROUP_PMUX_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | sam.PORT_GROUP_PINCFG_DRVSTR) - - case PinCom: - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk - p.setPMux(val | (uint8(PinCom) << sam.PORT_GROUP_PMUX_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk - p.setPMux(val | (uint8(PinCom) << sam.PORT_GROUP_PMUX_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN) - case PinAnalog: - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk - p.setPMux(val | (uint8(PinAnalog) << sam.PORT_GROUP_PMUX_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk - p.setPMux(val | (uint8(PinAnalog) << sam.PORT_GROUP_PMUX_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | sam.PORT_GROUP_PINCFG_DRVSTR) - case PinSDHC: - if p&1 > 0 { - // odd pin, so save the even pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk - p.setPMux(val | (uint8(PinSDHC) << sam.PORT_GROUP_PMUX_PMUXO_Pos)) - } else { - // even pin, so save the odd pins - val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk - p.setPMux(val | (uint8(PinSDHC) << sam.PORT_GROUP_PMUX_PMUXE_Pos)) - } - // enable port config - p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN) - } -} - -// getPMux returns the value for the correct PMUX register for this pin. -func (p Pin) getPMux() uint8 { - group, pin_in_group := p.getPinGrouping() - return sam.PORT.GROUP[group].PMUX[pin_in_group>>1].Get() -} - -// setPMux sets the value for the correct PMUX register for this pin. -func (p Pin) setPMux(val uint8) { - group, pin_in_group := p.getPinGrouping() - sam.PORT.GROUP[group].PMUX[pin_in_group>>1].Set(val) -} - -// getPinCfg returns the value for the correct PINCFG register for this pin. -func (p Pin) getPinCfg() uint8 { - group, pin_in_group := p.getPinGrouping() - return sam.PORT.GROUP[group].PINCFG[pin_in_group].Get() -} - -// setPinCfg sets the value for the correct PINCFG register for this pin. -func (p Pin) setPinCfg(val uint8) { - group, pin_in_group := p.getPinGrouping() - sam.PORT.GROUP[group].PINCFG[pin_in_group].Set(val) -} - -// getPinGrouping calculates the gpio group and pin id from the pin number. -// Pins are split into groups of 32, and each group has its own set of -// control registers. -func (p Pin) getPinGrouping() (uint8, uint8) { - group := uint8(p) >> 5 - pin_in_group := uint8(p) & 0x1f - return group, pin_in_group -} - -// InitADC initializes the ADC. -func InitADC() { - // ADC Bias Calibration - // NVMCTRL_SW0 0x00800080 - // #define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0 - // #define ADC0_FUSES_BIASCOMP_Pos 2 /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */ - // #define ADC0_FUSES_BIASCOMP_Msk (_Ul(0x7) << ADC0_FUSES_BIASCOMP_Pos) - // #define ADC0_FUSES_BIASCOMP(value) (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos)) - - // #define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0 - // #define ADC0_FUSES_BIASR2R_Pos 8 /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */ - // #define ADC0_FUSES_BIASR2R_Msk (_Ul(0x7) << ADC0_FUSES_BIASR2R_Pos) - // #define ADC0_FUSES_BIASR2R(value) (ADC0_FUSES_BIASR2R_Msk & ((value) << ADC0_FUSES_BIASR2R_Pos)) - - // #define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0 - // #define ADC0_FUSES_BIASREFBUF_Pos 5 /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */ - // #define ADC0_FUSES_BIASREFBUF_Msk (_Ul(0x7) << ADC0_FUSES_BIASREFBUF_Pos) - // #define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos)) - - // #define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0 - // #define ADC1_FUSES_BIASCOMP_Pos 16 /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */ - // #define ADC1_FUSES_BIASCOMP_Msk (_Ul(0x7) << ADC1_FUSES_BIASCOMP_Pos) - // #define ADC1_FUSES_BIASCOMP(value) (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos)) - - // #define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0 - // #define ADC1_FUSES_BIASR2R_Pos 22 /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */ - // #define ADC1_FUSES_BIASR2R_Msk (_Ul(0x7) << ADC1_FUSES_BIASR2R_Pos) - // #define ADC1_FUSES_BIASR2R(value) (ADC1_FUSES_BIASR2R_Msk & ((value) << ADC1_FUSES_BIASR2R_Pos)) - - // #define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0 - // #define ADC1_FUSES_BIASREFBUF_Pos 19 /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */ - // #define ADC1_FUSES_BIASREFBUF_Msk (_Ul(0x7) << ADC1_FUSES_BIASREFBUF_Pos) - // #define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos)) - - adcFuse := *(*uint32)(unsafe.Pointer(uintptr(0x00800080))) - - // uint32_t biascomp = (*((uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos; - biascomp := (adcFuse & uint32(0x7<<2)) //>> 2 - - // uint32_t biasr2r = (*((uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos; - biasr2r := (adcFuse & uint32(0x7<<8)) //>> 8 - - // uint32_t biasref = (*((uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR) & ADC0_FUSES_BIASREFBUF_Msk) >> ADC0_FUSES_BIASREFBUF_Pos; - biasref := (adcFuse & uint32(0x7<<5)) //>> 5 - - // calibrate ADC0 - sam.ADC0.CALIB.Set(uint16(biascomp | biasr2r | biasref)) - - // biascomp = (*((uint32_t *)ADC1_FUSES_BIASCOMP_ADDR) & ADC1_FUSES_BIASCOMP_Msk) >> ADC1_FUSES_BIASCOMP_Pos; - biascomp = (adcFuse & uint32(0x7<<16)) //>> 16 - - // biasr2r = (*((uint32_t *)ADC1_FUSES_BIASR2R_ADDR) & ADC1_FUSES_BIASR2R_Msk) >> ADC1_FUSES_BIASR2R_Pos; - biasr2r = (adcFuse & uint32(0x7<<22)) //>> 22 - - // biasref = (*((uint32_t *)ADC1_FUSES_BIASREFBUF_ADDR) & ADC1_FUSES_BIASREFBUF_Msk) >> ADC1_FUSES_BIASREFBUF_Pos; - biasref = (adcFuse & uint32(0x7<<19)) //>> 19 - - // calibrate ADC1 - sam.ADC1.CALIB.Set(uint16((biascomp | biasr2r | biasref) >> 16)) -} - -// Configure configures a ADCPin to be able to be used to read data. -func (a ADC) Configure(config ADCConfig) { - - for _, adc := range []*sam.ADC_Type{sam.ADC0, sam.ADC1} { - - for adc.SYNCBUSY.HasBits(sam.ADC_SYNCBUSY_CTRLB) { - } // wait for sync - - // Averaging (see datasheet table in AVGCTRL register description) - var resolution uint32 = sam.ADC_CTRLB_RESSEL_16BIT - var samples uint32 - switch config.Samples { - case 2: - samples = sam.ADC_AVGCTRL_SAMPLENUM_2 - case 4: - samples = sam.ADC_AVGCTRL_SAMPLENUM_4 - case 8: - samples = sam.ADC_AVGCTRL_SAMPLENUM_8 - case 16: - samples = sam.ADC_AVGCTRL_SAMPLENUM_16 - case 32: - samples = sam.ADC_AVGCTRL_SAMPLENUM_32 - case 64: - samples = sam.ADC_AVGCTRL_SAMPLENUM_64 - case 128: - samples = sam.ADC_AVGCTRL_SAMPLENUM_128 - case 256: - samples = sam.ADC_AVGCTRL_SAMPLENUM_256 - case 512: - samples = sam.ADC_AVGCTRL_SAMPLENUM_512 - case 1024: - samples = sam.ADC_AVGCTRL_SAMPLENUM_1024 - default: // 1 sample only (no oversampling nor averaging), adjusting result by 0 - // Resolutions less than 16 bits only make sense when sampling only - // once. Resulting ADC values become erratic when using both - // multi-sampling and less than 16 bits of resolution. - samples = sam.ADC_AVGCTRL_SAMPLENUM_1 - switch config.Resolution { - case 8: - resolution = sam.ADC_CTRLB_RESSEL_8BIT - case 10: - resolution = sam.ADC_CTRLB_RESSEL_10BIT - case 12: - resolution = sam.ADC_CTRLB_RESSEL_12BIT - case 16: - resolution = sam.ADC_CTRLB_RESSEL_16BIT - default: - resolution = sam.ADC_CTRLB_RESSEL_12BIT - } - } - - adc.AVGCTRL.Set(uint8(samples<> sam.ADC_CTRLB_RESSEL_Pos { - case sam.ADC_CTRLB_RESSEL_8BIT: - val = val << 8 - case sam.ADC_CTRLB_RESSEL_10BIT: - val = val << 6 - case sam.ADC_CTRLB_RESSEL_12BIT: - val = val << 4 - case sam.ADC_CTRLB_RESSEL_16BIT: - // Adjust for multiple samples. This is only configured when the - // resolution is 16 bits. - switch (bus.AVGCTRL.Get() & sam.ADC_AVGCTRL_SAMPLENUM_Msk) >> sam.ADC_AVGCTRL_SAMPLENUM_Pos { - case sam.ADC_AVGCTRL_SAMPLENUM_1: - val <<= 4 - case sam.ADC_AVGCTRL_SAMPLENUM_2: - val <<= 3 - case sam.ADC_AVGCTRL_SAMPLENUM_4: - val <<= 2 - case sam.ADC_AVGCTRL_SAMPLENUM_8: - val <<= 1 - default: - // These values are all shifted by the hardware so they fit exactly - // in a 16-bit integer, so they don't need to be shifted here. - } - } - return val -} - -func (a ADC) getADCBus() *sam.ADC_Type { - if (a.Pin >= PB04 && a.Pin <= PB07) || (a.Pin >= PC00) { - return sam.ADC1 - } - return sam.ADC0 -} - -func (a ADC) getADCChannel() uint8 { - switch a.Pin { - case PA02: - return 0 - case PB08: - return 2 - case PB09: - return 3 - case PA04: - return 4 - case PA05: - return 5 - case PA06: - return 6 - case PA07: - return 7 - case PB00: - return 12 - case PB01: - return 13 - case PB02: - return 14 - case PB03: - return 15 - case PA09: - return 17 - case PA11: - return 19 - - case PB04: - return 6 - case PB05: - return 7 - case PB06: - return 8 - case PB07: - return 9 - - case PC00: - return 10 - case PC01: - return 11 - case PC02: - return 4 - case PC03: - return 5 - case PC30: - return 12 - case PC31: - return 13 - - case PD00: - return 14 - case PD01: - return 15 - default: - panic("Invalid ADC pin") - } -} - -// UART on the SAMD51. -type UART struct { - Buffer *RingBuffer - Bus *sam.SERCOM_USART_INT_Type - SERCOM uint8 - Interrupt interrupt.Interrupt // RXC interrupt -} - -var ( - sercomUSART0 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM0_USART_INT, SERCOM: 0} - sercomUSART1 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM1_USART_INT, SERCOM: 1} - sercomUSART2 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM2_USART_INT, SERCOM: 2} - sercomUSART3 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM3_USART_INT, SERCOM: 3} - sercomUSART4 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM4_USART_INT, SERCOM: 4} - sercomUSART5 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM5_USART_INT, SERCOM: 5} -) - -func init() { - sercomUSART0.Interrupt = interrupt.New(sam.IRQ_SERCOM0_2, sercomUSART0.handleInterrupt) - sercomUSART1.Interrupt = interrupt.New(sam.IRQ_SERCOM1_2, sercomUSART1.handleInterrupt) - sercomUSART2.Interrupt = interrupt.New(sam.IRQ_SERCOM2_2, sercomUSART2.handleInterrupt) - sercomUSART3.Interrupt = interrupt.New(sam.IRQ_SERCOM3_2, sercomUSART3.handleInterrupt) - sercomUSART4.Interrupt = interrupt.New(sam.IRQ_SERCOM4_2, sercomUSART4.handleInterrupt) - sercomUSART5.Interrupt = interrupt.New(sam.IRQ_SERCOM5_2, sercomUSART5.handleInterrupt) -} - -const ( - sampleRate16X = 16 - lsbFirst = 1 -) - -// Configure the UART. -func (uart *UART) Configure(config UARTConfig) error { - // Default baud rate to 115200. - if config.BaudRate == 0 { - config.BaudRate = 115200 - } - - // determine pins - if config.TX == 0 && config.RX == 0 { - // use default pins - config.TX = UART_TX_PIN - config.RX = UART_RX_PIN - } - - // Determine transmit pinout. - txPinMode, txPad, ok := findPinPadMapping(uart.SERCOM, config.TX) - if !ok { - return ErrInvalidOutputPin - } - var txPadOut uint32 - // See CTRLA.RXPO bits of the SERCOM USART peripheral (page 945-946) for how - // pads are mapped to pinout values. - switch txPad { - case 0: - txPadOut = 0 - default: - // should be flow control (RTS/CTS) pin - return ErrInvalidOutputPin - } - - // Determine receive pinout. - rxPinMode, rxPad, ok := findPinPadMapping(uart.SERCOM, config.RX) - if !ok { - return ErrInvalidInputPin - } - // As you can see in the CTRLA.RXPO bits of the SERCOM USART peripheral - // (page 945), input pins are mapped directly. - rxPadOut := rxPad - - // configure pins - config.TX.Configure(PinConfig{Mode: txPinMode}) - config.RX.Configure(PinConfig{Mode: rxPinMode}) - - // configure RTS/CTS pins if provided - if config.RTS != 0 && config.CTS != 0 { - rtsPinMode, _, ok := findPinPadMapping(uart.SERCOM, config.RTS) - if !ok { - return ErrInvalidOutputPin - } - - ctsPinMode, _, ok := findPinPadMapping(uart.SERCOM, config.CTS) - if !ok { - return ErrInvalidInputPin - } - - // See CTRLA.RXPO bits of the SERCOM USART peripheral (page 945-946) for how - // pads are mapped to pinout values. - txPadOut = 2 - - config.RTS.Configure(PinConfig{Mode: rtsPinMode}) - config.CTS.Configure(PinConfig{Mode: ctsPinMode}) - } - - // reset SERCOM - uart.Bus.CTRLA.SetBits(sam.SERCOM_USART_INT_CTRLA_SWRST) - for uart.Bus.CTRLA.HasBits(sam.SERCOM_USART_INT_CTRLA_SWRST) || - uart.Bus.SYNCBUSY.HasBits(sam.SERCOM_USART_INT_SYNCBUSY_SWRST) { - } - - // set UART mode/sample rate - // SERCOM_USART_CTRLA_MODE(mode) | - // SERCOM_USART_CTRLA_SAMPR(sampleRate); - // sam.SERCOM_USART_CTRLA_MODE_USART_INT_CLK = 1? - uart.Bus.CTRLA.Set((1 << sam.SERCOM_USART_INT_CTRLA_MODE_Pos) | - (1 << sam.SERCOM_USART_INT_CTRLA_SAMPR_Pos)) // sample rate of 16x - - // set clock - setSERCOMClockGenerator(uart.SERCOM, sam.GCLK_PCHCTRL_GEN_GCLK1) - - // Set baud rate - uart.SetBaudRate(config.BaudRate) - - // setup UART frame - // SERCOM_USART_CTRLA_FORM( (parityMode == SERCOM_NO_PARITY ? 0 : 1) ) | - // dataOrder << SERCOM_USART_CTRLA_DORD_Pos; - uart.Bus.CTRLA.SetBits((0 << sam.SERCOM_USART_INT_CTRLA_FORM_Pos) | // no parity - (lsbFirst << sam.SERCOM_USART_INT_CTRLA_DORD_Pos)) // data order - - // set UART stop bits/parity - // SERCOM_USART_CTRLB_CHSIZE(charSize) | - // nbStopBits << SERCOM_USART_CTRLB_SBMODE_Pos | - // (parityMode == SERCOM_NO_PARITY ? 0 : parityMode) << SERCOM_USART_CTRLB_PMODE_Pos; //If no parity use default value - uart.Bus.CTRLB.SetBits((0 << sam.SERCOM_USART_INT_CTRLB_CHSIZE_Pos) | // 8 bits is 0 - (0 << sam.SERCOM_USART_INT_CTRLB_SBMODE_Pos) | // 1 stop bit is zero - (0 << sam.SERCOM_USART_INT_CTRLB_PMODE_Pos)) // no parity - - // set UART pads. This is not same as pins... - // SERCOM_USART_CTRLA_TXPO(txPad) | - // SERCOM_USART_CTRLA_RXPO(rxPad); - uart.Bus.CTRLA.SetBits((txPadOut << sam.SERCOM_USART_INT_CTRLA_TXPO_Pos) | - (rxPadOut << sam.SERCOM_USART_INT_CTRLA_RXPO_Pos)) - - // Enable Transceiver and Receiver - //sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN ; - uart.Bus.CTRLB.SetBits(sam.SERCOM_USART_INT_CTRLB_TXEN | sam.SERCOM_USART_INT_CTRLB_RXEN) - - // Enable USART1 port. - // sercom->USART.CTRLA.bit.ENABLE = 0x1u; - uart.Bus.CTRLA.SetBits(sam.SERCOM_USART_INT_CTRLA_ENABLE) - for uart.Bus.SYNCBUSY.HasBits(sam.SERCOM_USART_INT_SYNCBUSY_ENABLE) { - } - - // setup interrupt on receive - uart.Bus.INTENSET.Set(sam.SERCOM_USART_INT_INTENSET_RXC) - - // Enable RX IRQ. - // This is a small note at the bottom of the NVIC section of the datasheet: - // > The integer number specified in the source refers to the respective bit - // > position in the INTFLAG register of respective peripheral. - // Therefore, if we only need to listen to the RXC interrupt source (in bit - // position 2), we only need interrupt source 2 for this SERCOM device. - uart.Interrupt.Enable() - - return nil -} - -// SetBaudRate sets the communication speed for the UART. -func (uart *UART) SetBaudRate(br uint32) { - // Asynchronous fractional mode (Table 24-2 in datasheet) - // BAUD = fref / (sampleRateValue * fbaud) - // (multiply by 8, to calculate fractional piece) - // uint32_t baudTimes8 = (SystemCoreClock * 8) / (16 * baudrate); - baud := (SERCOM_FREQ_REF * 8) / (sampleRate16X * br) - - // sercom->USART.BAUD.FRAC.FP = (baudTimes8 % 8); - // sercom->USART.BAUD.FRAC.BAUD = (baudTimes8 / 8); - uart.Bus.BAUD.Set(uint16(((baud % 8) << sam.SERCOM_USART_INT_BAUD_FRAC_MODE_FP_Pos) | - ((baud / 8) << sam.SERCOM_USART_INT_BAUD_FRAC_MODE_BAUD_Pos))) -} - -// WriteByte writes a byte of data to the UART. -func (uart *UART) writeByte(c byte) error { - // wait until ready to receive - for !uart.Bus.INTFLAG.HasBits(sam.SERCOM_USART_INT_INTFLAG_DRE) { - } - uart.Bus.DATA.Set(uint32(c)) - return nil -} - -func (uart *UART) flush() {} - -func (uart *UART) handleInterrupt(interrupt.Interrupt) { - // should reset IRQ - uart.Receive(byte((uart.Bus.DATA.Get() & 0xFF))) - uart.Bus.INTFLAG.SetBits(sam.SERCOM_USART_INT_INTFLAG_RXC) -} - -// I2C on the SAMD51. -type I2C struct { - Bus *sam.SERCOM_I2CM_Type - SERCOM uint8 -} - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 - SCL Pin - SDA Pin -} - -const ( - // SERCOM_FREQ_REF is always reference frequency on SAMD51 regardless of CPU speed. - SERCOM_FREQ_REF = 48000000 - SERCOM_FREQ_REF_GCLK0 = 120000000 - - // Default rise time in nanoseconds, based on 4.7K ohm pull up resistors - riseTimeNanoseconds = 125 - - // wire bus states - wireUnknownState = 0 - wireIdleState = 1 - wireOwnerState = 2 - wireBusyState = 3 - - // wire commands - wireCmdNoAction = 0 - wireCmdRepeatStart = 1 - wireCmdRead = 2 - wireCmdStop = 3 -) - -const i2cTimeout = 28000 // about 210us - -// Configure is intended to setup the I2C interface. -func (i2c *I2C) Configure(config I2CConfig) error { - // Default I2C bus speed is 100 kHz. - if config.Frequency == 0 { - config.Frequency = 100 * KHz - } - - // Use default I2C pins if not set. - if config.SDA == 0 && config.SCL == 0 { - config.SDA = SDA_PIN - config.SCL = SCL_PIN - } - - sclPinMode, sclPad, ok := findPinPadMapping(i2c.SERCOM, config.SCL) - if !ok || sclPad != 1 { - // SCL must be on pad 1, according to section 36.4 of the datasheet. - // Note: this is not an exhaustive test for I2C support on the pin: not - // all pins support I2C. - return ErrInvalidClockPin - } - sdaPinMode, sdaPad, ok := findPinPadMapping(i2c.SERCOM, config.SDA) - if !ok || sdaPad != 0 { - // SDA must be on pad 0, according to section 36.4 of the datasheet. - // Note: this is not an exhaustive test for I2C support on the pin: not - // all pins support I2C. - return ErrInvalidDataPin - } - - // reset SERCOM - i2c.Bus.CTRLA.SetBits(sam.SERCOM_I2CM_CTRLA_SWRST) - for i2c.Bus.CTRLA.HasBits(sam.SERCOM_I2CM_CTRLA_SWRST) || - i2c.Bus.SYNCBUSY.HasBits(sam.SERCOM_I2CM_SYNCBUSY_SWRST) { - } - - // set clock - setSERCOMClockGenerator(i2c.SERCOM, sam.GCLK_PCHCTRL_GEN_GCLK1) - - // Set i2c controller mode - //SERCOM_I2CM_CTRLA_MODE( I2C_MASTER_OPERATION ) - // sam.SERCOM_I2CM_CTRLA_MODE_I2C_MASTER = 5? - i2c.Bus.CTRLA.Set(5 << sam.SERCOM_I2CM_CTRLA_MODE_Pos) // | - - i2c.SetBaudRate(config.Frequency) - - // Enable I2CM port. - // sercom->USART.CTRLA.bit.ENABLE = 0x1u; - i2c.Bus.CTRLA.SetBits(sam.SERCOM_I2CM_CTRLA_ENABLE) - for i2c.Bus.SYNCBUSY.HasBits(sam.SERCOM_I2CM_SYNCBUSY_ENABLE) { - } - - // set bus idle mode - i2c.Bus.STATUS.SetBits(wireIdleState << sam.SERCOM_I2CM_STATUS_BUSSTATE_Pos) - for i2c.Bus.SYNCBUSY.HasBits(sam.SERCOM_I2CM_SYNCBUSY_SYSOP) { - } - - // enable pins - config.SDA.Configure(PinConfig{Mode: sdaPinMode}) - config.SCL.Configure(PinConfig{Mode: sclPinMode}) - - return nil -} - -// SetBaudRate sets the communication speed for I2C. -func (i2c *I2C) SetBaudRate(br uint32) error { - // Synchronous arithmetic baudrate, via Adafruit SAMD51 implementation: - // sercom->I2CM.BAUD.bit.BAUD = SERCOM_FREQ_REF / ( 2 * baudrate) - 1 ; - baud := SERCOM_FREQ_REF/(2*br) - 1 - i2c.Bus.BAUD.Set(baud) - return nil -} - -// Tx does a single I2C transaction at the specified address. -// It clocks out the given address, writes the bytes in w, reads back len(r) -// bytes and stores them in r, and generates a stop condition on the bus. -func (i2c *I2C) Tx(addr uint16, w, r []byte) error { - var err error - if len(w) != 0 { - // send start/address for write - i2c.sendAddress(addr, true) - - // wait until transmission complete - timeout := i2cTimeout - for !i2c.Bus.INTFLAG.HasBits(sam.SERCOM_I2CM_INTFLAG_MB) { - timeout-- - if timeout == 0 { - return errI2CWriteTimeout - } - } - - // ACK received (0: ACK, 1: NACK) - if i2c.Bus.STATUS.HasBits(sam.SERCOM_I2CM_STATUS_RXNACK) { - return errI2CAckExpected - } - - // write data - for _, b := range w { - err = i2c.WriteByte(b) - if err != nil { - return err - } - } - - err = i2c.signalStop() - if err != nil { - return err - } - } - if len(r) != 0 { - // send start/address for read - i2c.sendAddress(addr, false) - - // wait transmission complete - for !i2c.Bus.INTFLAG.HasBits(sam.SERCOM_I2CM_INTFLAG_SB) { - // If the peripheral NACKS the address, the MB bit will be set. - // In that case, send a stop condition and return error. - if i2c.Bus.INTFLAG.HasBits(sam.SERCOM_I2CM_INTFLAG_MB) { - i2c.Bus.CTRLB.SetBits(wireCmdStop << sam.SERCOM_I2CM_CTRLB_CMD_Pos) // Stop condition - return errI2CAckExpected - } - } - - // ACK received (0: ACK, 1: NACK) - if i2c.Bus.STATUS.HasBits(sam.SERCOM_I2CM_STATUS_RXNACK) { - return errI2CAckExpected - } - - // read first byte - r[0] = i2c.readByte() - for i := 1; i < len(r); i++ { - // Send an ACK - i2c.Bus.CTRLB.ClearBits(sam.SERCOM_I2CM_CTRLB_ACKACT) - - i2c.signalRead() - - // Read data and send the ACK - r[i] = i2c.readByte() - } - - // Send NACK to end transmission - i2c.Bus.CTRLB.SetBits(sam.SERCOM_I2CM_CTRLB_ACKACT) - - err = i2c.signalStop() - if err != nil { - return err - } - } - - return nil -} - -// WriteByte writes a single byte to the I2C bus. -func (i2c *I2C) WriteByte(data byte) error { - // Send data byte - i2c.Bus.DATA.Set(data) - - // wait until transmission successful - timeout := i2cTimeout - for !i2c.Bus.INTFLAG.HasBits(sam.SERCOM_I2CM_INTFLAG_MB) { - // check for bus error - if i2c.Bus.STATUS.HasBits(sam.SERCOM_I2CM_STATUS_BUSERR) { - return errI2CBusError - } - timeout-- - if timeout == 0 { - return errI2CWriteTimeout - } - } - - if i2c.Bus.STATUS.HasBits(sam.SERCOM_I2CM_STATUS_RXNACK) { - return errI2CAckExpected - } - - return nil -} - -// sendAddress sends the address and start signal -func (i2c *I2C) sendAddress(address uint16, write bool) error { - data := (address << 1) - if !write { - data |= 1 // set read flag - } - - // wait until bus ready - timeout := i2cTimeout - for !i2c.Bus.STATUS.HasBits(wireIdleState< freqGCLK1 && uint32(uint8(baudRateGCLK0-1))+1 == baudRateGCLK0 { - // Pick this 120MHz clock if it results in a better frequency after - // division, and the baudRate value fits in the BAUD register. - setSERCOMClockGenerator(spi.SERCOM, sam.GCLK_PCHCTRL_GEN_GCLK0) - spi.Bus.BAUD.Set(uint8(baudRateGCLK0 - 1)) - } else { - // Use the 48MHz clock in other cases. - setSERCOMClockGenerator(spi.SERCOM, sam.GCLK_PCHCTRL_GEN_GCLK1) - spi.Bus.BAUD.Set(uint8(baudRateGCLK1 - 1)) - } - - // Enable SPI port. - spi.Bus.CTRLA.SetBits(sam.SERCOM_SPIM_CTRLA_ENABLE) - for spi.Bus.SYNCBUSY.HasBits(sam.SERCOM_SPIM_SYNCBUSY_ENABLE) { - } - - return nil -} - -// Transfer writes/reads a single byte using the SPI interface. -func (spi *SPI) Transfer(w byte) (byte, error) { - // write data - spi.Bus.DATA.Set(uint32(w)) - - // wait for receive - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_RXC) { - } - - // return data - return byte(spi.Bus.DATA.Get()), nil -} - -// Tx handles read/write operation for SPI interface. Since SPI is a synchronous write/read -// interface, there must always be the same number of bytes written as bytes read. -// The Tx method knows about this, and offers a few different ways of calling it. -// -// This form sends the bytes in tx buffer, putting the resulting bytes read into the rx buffer. -// Note that the tx and rx buffers must be the same size: -// -// spi.Tx(tx, rx) -// -// This form sends the tx buffer, ignoring the result. Useful for sending "commands" that return zeros -// until all the bytes in the command packet have been received: -// -// spi.Tx(tx, nil) -// -// This form sends zeros, putting the result into the rx buffer. Good for reading a "result packet": -// -// spi.Tx(nil, rx) -func (spi *SPI) Tx(w, r []byte) error { - switch { - case w == nil: - // read only, so write zero and read a result. - spi.rx(r) - case r == nil: - // write only - spi.tx(w) - - default: - // write/read - if len(w) != len(r) { - return ErrTxInvalidSliceSize - } - - spi.txrx(w, r) - } - - return nil -} - -func (spi *SPI) tx(tx []byte) { - for i := 0; i < len(tx); i++ { - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_DRE) { - } - spi.Bus.DATA.Set(uint32(tx[i])) - } - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_TXC) { - } - - // read to clear RXC register - for spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_RXC) { - spi.Bus.DATA.Get() - } -} - -func (spi *SPI) rx(rx []byte) { - spi.Bus.DATA.Set(0) - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_DRE) { - } - - for i := 1; i < len(rx); i++ { - spi.Bus.DATA.Set(0) - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_RXC) { - } - rx[i-1] = byte(spi.Bus.DATA.Get()) - } - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_RXC) { - } - rx[len(rx)-1] = byte(spi.Bus.DATA.Get()) -} - -func (spi *SPI) txrx(tx, rx []byte) { - spi.Bus.DATA.Set(uint32(tx[0])) - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_DRE) { - } - - for i := 1; i < len(rx); i++ { - spi.Bus.DATA.Set(uint32(tx[i])) - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_RXC) { - } - rx[i-1] = byte(spi.Bus.DATA.Get()) - } - for !spi.Bus.INTFLAG.HasBits(sam.SERCOM_SPIM_INTFLAG_RXC) { - } - rx[len(rx)-1] = byte(spi.Bus.DATA.Get()) -} - -// The QSPI peripheral on ATSAMD51 is only available on the following pins -const ( - QSPI_SCK = PB10 - QSPI_CS = PB11 - QSPI_DATA0 = PA08 - QSPI_DATA1 = PA09 - QSPI_DATA2 = PA10 - QSPI_DATA3 = PA11 -) - -// TCC is one timer peripheral, which consists of a counter and multiple output -// channels (that can be connected to actual pins). You can set the frequency -// using SetPeriod, but only for all the channels in this timer peripheral at -// once. -type TCC sam.TCC_Type - -//go:inline -func (tcc *TCC) timer() *sam.TCC_Type { - return (*sam.TCC_Type)(tcc) -} - -// Configure enables and configures this TCC. -func (tcc *TCC) Configure(config PWMConfig) error { - // Enable the TCC clock to be able to use the TCC. - tcc.configureClock() - - // Disable timer (if it was enabled). This is necessary because - // tcc.setPeriod may want to change the prescaler bits in CTRLA, which is - // only allowed when the TCC is disabled. - tcc.timer().CTRLA.ClearBits(sam.TCC_CTRLA_ENABLE) - - // Use "Normal PWM" (single-slope PWM) - tcc.timer().WAVE.Set(sam.TCC_WAVE_WAVEGEN_NPWM) - - // Wait for synchronization of all changed registers. - for tcc.timer().SYNCBUSY.Get() != 0 { - } - - // Set the period and prescaler. - err := tcc.setPeriod(config.Period, true) - - // Enable the timer. - tcc.timer().CTRLA.SetBits(sam.TCC_CTRLA_ENABLE) - - // Wait for synchronization of all changed registers. - for tcc.timer().SYNCBUSY.Get() != 0 { - } - - // Return any error that might have occurred in the tcc.setPeriod call. - return err -} - -// SetPeriod updates the period of this TCC peripheral. -// To set a particular frequency, use the following formula: -// -// period = 1e9 / frequency -// -// If you use a period of 0, a period that works well for LEDs will be picked. -// -// SetPeriod will not change the prescaler, but also won't change the current -// value in any of the channels. This means that you may need to update the -// value for the particular channel. -// -// Note that you cannot pick any arbitrary period after the TCC peripheral has -// been configured. If you want to switch between frequencies, pick the lowest -// frequency (longest period) once when calling Configure and adjust the -// frequency here as needed. -func (tcc *TCC) SetPeriod(period uint64) error { - return tcc.setPeriod(period, false) -} - -// setPeriod sets the period of this TCC, possibly updating the prescaler as -// well. The prescaler can only modified when the TCC is disabled, that is, in -// the Configure function. -func (tcc *TCC) setPeriod(period uint64, updatePrescaler bool) error { - var top uint64 - if period == 0 { - // Make sure the TOP value is at 0xffff (enough for a 16-bit timer). - top = 0xffff - } else { - // The formula below calculates the following formula, optimized: - // period * (120e6 / 1e9) - // This assumes that the chip is running from generic clock generator 0 - // at 120MHz. - top = period * 3 / 25 - } - - maxTop := uint64(0xffff) - if tcc.timer() == sam.TCC0 || tcc.timer() == sam.TCC1 { - // Only TCC0 and TCC1 are 24-bit timers, the rest are 16-bit. - maxTop = 0xffffff - } - - if updatePrescaler { - // This function was called during Configure(), with the timer disabled. - // Note that updating the prescaler can only happen while the peripheral - // is disabled. - var prescaler uint32 - switch { - case top <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV1 - case top/2 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV2 - top = top / 2 - case top/4 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV4 - top = top / 4 - case top/8 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV8 - top = top / 8 - case top/16 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV16 - top = top / 16 - case top/64 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV64 - top = top / 64 - case top/256 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV256 - top = top / 256 - case top/1024 <= maxTop: - prescaler = sam.TCC_CTRLA_PRESCALER_DIV1024 - top = top / 1024 - default: - return ErrPWMPeriodTooLong - } - tcc.timer().CTRLA.Set((tcc.timer().CTRLA.Get() &^ sam.TCC_CTRLA_PRESCALER_Msk) | (prescaler << sam.TCC_CTRLA_PRESCALER_Pos)) - } else { - // Do not update the prescaler, but use the already-configured - // prescaler. This is the normal SetPeriod case, where the prescaler - // must not be changed. - prescaler := (tcc.timer().CTRLA.Get() & sam.TCC_CTRLA_PRESCALER_Msk) >> sam.TCC_CTRLA_PRESCALER_Pos - switch prescaler { - case sam.TCC_CTRLA_PRESCALER_DIV1: - top /= 1 // no-op - case sam.TCC_CTRLA_PRESCALER_DIV2: - top /= 2 - case sam.TCC_CTRLA_PRESCALER_DIV4: - top /= 4 - case sam.TCC_CTRLA_PRESCALER_DIV8: - top /= 8 - case sam.TCC_CTRLA_PRESCALER_DIV16: - top /= 16 - case sam.TCC_CTRLA_PRESCALER_DIV64: - top /= 64 - case sam.TCC_CTRLA_PRESCALER_DIV256: - top /= 256 - case sam.TCC_CTRLA_PRESCALER_DIV1024: - top /= 1024 - default: - // unreachable - } - if top > maxTop { - return ErrPWMPeriodTooLong - } - } - - // Set the period (the counter top). - tcc.timer().PER.Set(uint32(top) - 1) - - // Wait for synchronization of CTRLA.PRESCALER and PER registers. - for tcc.timer().SYNCBUSY.Get() != 0 { - } - - return nil -} - -// Top returns the current counter top, for use in duty cycle calculation. It -// will only change with a call to Configure or SetPeriod, otherwise it is -// constant. -// -// The value returned here is hardware dependent. In general, it's best to treat -// it as an opaque value that can be divided by some number and passed to -// tcc.Set (see tcc.Set for more information). -func (tcc *TCC) Top() uint32 { - return tcc.timer().PER.Get() + 1 -} - -// Counter returns the current counter value of the timer in this TCC -// peripheral. It may be useful for debugging. -func (tcc *TCC) Counter() uint32 { - tcc.timer().CTRLBSET.Set(sam.TCC_CTRLBSET_CMD_READSYNC << sam.TCC_CTRLBSET_CMD_Pos) - for tcc.timer().SYNCBUSY.Get() != 0 { - } - return tcc.timer().COUNT.Get() -} - -// Constants that encode a TCC number and WO number together in a single byte. -const ( - pinTCC0 = 1 << 4 // keep the value 0 usable as "no value" - pinTCC1 = 2 << 4 - pinTCC2 = 3 << 4 - pinTCC3 = 4 << 4 - pinTCC4 = 5 << 4 - pinTCC0_0 = pinTCC0 | 0 - pinTCC0_1 = pinTCC0 | 1 - pinTCC0_2 = pinTCC0 | 2 - pinTCC0_3 = pinTCC0 | 3 - pinTCC0_4 = pinTCC0 | 4 - pinTCC0_5 = pinTCC0 | 5 - pinTCC0_6 = pinTCC0 | 6 - pinTCC1_0 = pinTCC1 | 0 - pinTCC1_2 = pinTCC1 | 2 - pinTCC1_4 = pinTCC1 | 4 - pinTCC1_6 = pinTCC1 | 6 - pinTCC2_0 = pinTCC2 | 0 - pinTCC2_2 = pinTCC2 | 2 - pinTCC3_0 = pinTCC3 | 0 - pinTCC4_0 = pinTCC4 | 0 -) - -// This is a copy of columns F and G (the TCC columns) of table 6-1 in the -// datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/60001507E.pdf -// For example, "TCC0/WO[2]" is converted to pinTCC0_2. -// Only the even pin numbers are stored here. The odd pin numbers are left out, -// because their PWM output can be determined from the even number: just add one -// to the wave output (WO) number. -var pinTimerMapping = [...]struct{ F, G uint8 }{ - // page 33 - PC04 / 2: {pinTCC0_0, 0}, - PA08 / 2: {pinTCC0_0, pinTCC1_4}, - PA10 / 2: {pinTCC0_2, pinTCC1_6}, - PB10 / 2: {pinTCC0_4, pinTCC1_0}, - PB12 / 2: {pinTCC3_0, pinTCC0_0}, - PB14 / 2: {pinTCC4_0, pinTCC0_2}, - PD08 / 2: {pinTCC0_1, 0}, - PD10 / 2: {pinTCC0_3, 0}, - PD12 / 2: {pinTCC0_5, 0}, - PC10 / 2: {pinTCC0_0, pinTCC1_4}, - // page 34 - PC12 / 2: {pinTCC0_2, pinTCC1_6}, - PC14 / 2: {pinTCC0_4, pinTCC1_0}, - PA12 / 2: {pinTCC0_6, pinTCC1_2}, - PA14 / 2: {pinTCC2_0, pinTCC1_2}, - PA16 / 2: {pinTCC1_0, pinTCC0_4}, - PA18 / 2: {pinTCC1_2, pinTCC0_6}, - PC16 / 2: {pinTCC0_0, 0}, - PC18 / 2: {pinTCC0_2, 0}, - PC20 / 2: {pinTCC0_4, 0}, - PC22 / 2: {pinTCC0_6, 0}, - PD20 / 2: {pinTCC1_0, 0}, - PB16 / 2: {pinTCC3_0, pinTCC0_4}, - PB18 / 2: {pinTCC1_0, 0}, - // page 35 - PB20 / 2: {pinTCC1_2, 0}, - PA20 / 2: {pinTCC1_4, pinTCC0_0}, - PA22 / 2: {pinTCC1_6, pinTCC0_2}, - PA24 / 2: {pinTCC2_2, 0}, - PB26 / 2: {pinTCC1_2, 0}, - PB28 / 2: {pinTCC1_4, 0}, - PA30 / 2: {pinTCC2_0, 0}, - // page 36 - PB30 / 2: {pinTCC4_0, pinTCC0_6}, - PB02 / 2: {pinTCC2_2, 0}, -} - -// findPinTimerMapping returns the pin mode (PinTCCF or PinTCCG) and the channel -// number for a given timer and pin. A zero PinMode is returned if no mapping -// could be found. -func findPinTimerMapping(timer uint8, pin Pin) (PinMode, uint8) { - if int(pin/2) >= len(pinTimerMapping) { - return 0, 0 // invalid pin number - } - - mapping := pinTimerMapping[pin/2] - - // Check for column F in the datasheet. - if mapping.F>>4-1 == timer { - return PinTCCF, mapping.F&0x0f + uint8(pin)&1 - } - - // Check for column G in the datasheet. - if mapping.G>>4-1 == timer { - return PinTCCG, mapping.G&0x0f + uint8(pin)&1 - } - - // Nothing found. - return 0, 0 -} - -// Channel returns a PWM channel for the given pin. Note that one channel may be -// shared between multiple pins, and so will have the same duty cycle. If this -// is not desirable, look for a different TCC or consider using a different pin. -func (tcc *TCC) Channel(pin Pin) (uint8, error) { - pinMode, woOutput := findPinTimerMapping(tcc.timerNum(), pin) - - if pinMode == 0 { - // No pin could be found. - return 0, ErrInvalidOutputPin - } - - // Convert from waveform output to channel, assuming WEXCTRL.OTMX equals 0. - // See table 49-4 "Output Matrix Channel Pin Routing Configuration" on page - // 1829 of the datasheet. - // The number of channels varies by TCC instance, hence the need to switch - // over them. For TCC2-4 the number of channels is equal to the number of - // waveform outputs, so the WO number maps directly to the channel number. - // For TCC0 and TCC1 this is not the case so they will need some special - // handling. - channel := woOutput - switch tcc.timer() { - case sam.TCC0: - channel = woOutput % 6 - case sam.TCC1: - channel = woOutput % 4 - } - - // Enable the port multiplexer for pin - pin.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN) - - // Connect timer/mux to pin. - if pin&1 > 0 { - // odd pin, so save the even pins - val := pin.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk - pin.setPMux(val | uint8(pinMode<> 4) - dac.syncDAC() - return nil -} - -func (dac DAC) syncDAC() { - switch dac.Channel { - case 0: - for !sam.DAC.STATUS.HasBits(sam.DAC_STATUS_EOC0) { - } - for sam.DAC.SYNCBUSY.HasBits(sam.DAC_SYNCBUSY_DATA0) { - } - default: - for !sam.DAC.STATUS.HasBits(sam.DAC_STATUS_EOC1) { - } - for sam.DAC.SYNCBUSY.HasBits(sam.DAC_SYNCBUSY_DATA1) { - } - } -} - -// GetRNG returns 32 bits of cryptographically secure random data -func GetRNG() (uint32, error) { - if !sam.MCLK.APBCMASK.HasBits(sam.MCLK_APBCMASK_TRNG_) { - // Turn on clock for TRNG - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TRNG_) - - // enable - sam.TRNG.CTRLA.Set(sam.TRNG_CTRLA_ENABLE) - } - for !sam.TRNG.INTFLAG.HasBits(sam.TRNG_INTFLAG_DATARDY) { - } - ret := sam.TRNG.DATA.Get() - return ret, nil -} - -// Flash related code -const memoryStart = 0x0 - -// compile-time check for ensuring we fulfill BlockDevice interface -var _ BlockDevice = flashBlockDevice{} - -var Flash flashBlockDevice - -type flashBlockDevice struct { - initComplete bool -} - -// ReadAt reads the given number of bytes from the block device. -func (f flashBlockDevice) ReadAt(p []byte, off int64) (n int, err error) { - if FlashDataStart()+uintptr(off)+uintptr(len(p)) > FlashDataEnd() { - return 0, errFlashCannotReadPastEOF - } - - waitWhileFlashBusy() - - data := unsafe.Slice((*byte)(unsafe.Add(unsafe.Pointer(FlashDataStart()), uintptr(off))), len(p)) - copy(p, data) - - return len(p), nil -} - -// WriteAt writes the given number of bytes to the block device. -// Data is written to the page buffer in 4-byte chunks, then saved to flash memory. -// See SAM-D5x-E5x-Family-Data-Sheet-DS60001507.pdf page 591-592. -// If the length of p is not long enough it will be padded with 0xFF bytes. -// This method assumes that the destination is already erased. -func (f flashBlockDevice) WriteAt(p []byte, off int64) (n int, err error) { - if FlashDataStart()+uintptr(off)+uintptr(len(p)) > FlashDataEnd() { - return 0, errFlashCannotWritePastEOF - } - - address := FlashDataStart() + uintptr(off) - padded := flashPad(p, int(f.WriteBlockSize())) - - settings := disableFlashCache() - defer restoreFlashCache(settings) - - waitWhileFlashBusy() - - sam.NVMCTRL.CTRLB.Set(sam.NVMCTRL_CTRLB_CMD_PBC | (sam.NVMCTRL_CTRLB_CMDEX_KEY << sam.NVMCTRL_CTRLB_CMDEX_Pos)) - - waitWhileFlashBusy() - - for j := 0; j < len(padded); j += int(f.WriteBlockSize()) { - // page buffer is 512 bytes long, but only 4 bytes can be written at once - for k := 0; k < int(f.WriteBlockSize()); k += 4 { - *(*uint32)(unsafe.Pointer(address + uintptr(k))) = binary.LittleEndian.Uint32(padded[j+k : j+k+4]) - } - - sam.NVMCTRL.SetADDR(uint32(address)) - sam.NVMCTRL.CTRLB.Set(sam.NVMCTRL_CTRLB_CMD_WP | (sam.NVMCTRL_CTRLB_CMDEX_KEY << sam.NVMCTRL_CTRLB_CMDEX_Pos)) - - waitWhileFlashBusy() - - if err := checkFlashError(); err != nil { - return j, err - } - - address += uintptr(f.WriteBlockSize()) - } - - return len(padded), nil -} - -// Size returns the number of bytes in this block device. -func (f flashBlockDevice) Size() int64 { - return int64(FlashDataEnd() - FlashDataStart()) -} - -const writeBlockSize = 512 - -// WriteBlockSize returns the block size in which data can be written to -// memory. It can be used by a client to optimize writes, non-aligned writes -// should always work correctly. -func (f flashBlockDevice) WriteBlockSize() int64 { - return writeBlockSize -} - -const eraseBlockSizeValue = 8192 - -func eraseBlockSize() int64 { - return eraseBlockSizeValue -} - -// EraseBlockSize returns the smallest erasable area on this particular chip -// in bytes. This is used for the block size in EraseBlocks. -func (f flashBlockDevice) EraseBlockSize() int64 { - return eraseBlockSize() -} - -// EraseBlocks erases the given number of blocks. An implementation may -// transparently coalesce ranges of blocks into larger bundles if the chip -// supports this. The start and len parameters are in block numbers, use -// EraseBlockSize to map addresses to blocks. -func (f flashBlockDevice) EraseBlocks(start, len int64) error { - address := FlashDataStart() + uintptr(start*f.EraseBlockSize()) - - settings := disableFlashCache() - defer restoreFlashCache(settings) - - waitWhileFlashBusy() - - for i := start; i < start+len; i++ { - sam.NVMCTRL.SetADDR(uint32(address)) - sam.NVMCTRL.CTRLB.Set(sam.NVMCTRL_CTRLB_CMD_EB | (sam.NVMCTRL_CTRLB_CMDEX_KEY << sam.NVMCTRL_CTRLB_CMDEX_Pos)) - - waitWhileFlashBusy() - - if err := checkFlashError(); err != nil { - return err - } - - address += uintptr(f.EraseBlockSize()) - } - - return nil -} - -func disableFlashCache() uint16 { - settings := sam.NVMCTRL.CTRLA.Get() - - // disable caches - sam.NVMCTRL.SetCTRLA_CACHEDIS0(1) - sam.NVMCTRL.SetCTRLA_CACHEDIS1(1) - - waitWhileFlashBusy() - - return settings -} - -func restoreFlashCache(settings uint16) { - sam.NVMCTRL.CTRLA.Set(settings) - waitWhileFlashBusy() -} - -func waitWhileFlashBusy() { - for sam.NVMCTRL.GetSTATUS_READY() != sam.NVMCTRL_STATUS_READY { - } -} - -var ( - errFlashADDRE = errors.New("errFlashADDRE") - errFlashPROGE = errors.New("errFlashPROGE") - errFlashLOCKE = errors.New("errFlashLOCKE") - errFlashECCSE = errors.New("errFlashECCSE") - errFlashNVME = errors.New("errFlashNVME") - errFlashSEESOVF = errors.New("errFlashSEESOVF") -) - -func checkFlashError() error { - switch { - case sam.NVMCTRL.GetINTENSET_ADDRE() != 0: - return errFlashADDRE - case sam.NVMCTRL.GetINTENSET_PROGE() != 0: - return errFlashPROGE - case sam.NVMCTRL.GetINTENSET_LOCKE() != 0: - return errFlashLOCKE - case sam.NVMCTRL.GetINTENSET_ECCSE() != 0: - return errFlashECCSE - case sam.NVMCTRL.GetINTENSET_NVME() != 0: - return errFlashNVME - case sam.NVMCTRL.GetINTENSET_SEESOVF() != 0: - return errFlashSEESOVF - } - - return nil -} - -// Watchdog provides access to the hardware watchdog available -// in the SAMD51. -var Watchdog = &watchdogImpl{} - -const ( - // WatchdogMaxTimeout in milliseconds (16s) - WatchdogMaxTimeout = (16384 * 1000) / 1024 // CYC16384/1024kHz -) - -type watchdogImpl struct{} - -// Configure the watchdog. -// -// This method should not be called after the watchdog is started and on -// some platforms attempting to reconfigure after starting the watchdog -// is explicitly forbidden / will not work. -func (wd *watchdogImpl) Configure(config WatchdogConfig) error { - // 1.024kHz clock - cycles := int((int64(config.TimeoutMillis) * 1024) / 1000) - - // period is expressed as a power-of-two, starting at 8 / 1024ths of a second - period := uint8(0) - cfgCycles := 8 - for cfgCycles < cycles { - period++ - cfgCycles <<= 1 - - if period >= 0xB { - break - } - } - - sam.WDT.CONFIG.Set(period << sam.WDT_CONFIG_PER_Pos) - - return nil -} - -// Starts the watchdog. -func (wd *watchdogImpl) Start() error { - sam.WDT.CTRLA.SetBits(sam.WDT_CTRLA_ENABLE) - return nil -} - -// Update the watchdog, indicating that `source` is healthy. -func (wd *watchdogImpl) Update() { - sam.WDT.CLEAR.Set(sam.WDT_CLEAR_CLEAR_KEY) -} diff --git a/emb/machine/machine_atsamd51_usb.go b/emb/machine/machine_atsamd51_usb.go deleted file mode 100644 index a95089f..0000000 --- a/emb/machine/machine_atsamd51_usb.go +++ /dev/null @@ -1,495 +0,0 @@ -//go:build (sam && atsamd51) || (sam && atsame5x) - -package machine - -import ( - "device/sam" - "machine/usb" - "runtime/interrupt" - "unsafe" -) - -const ( - // these are SAMD51 specific. - usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos = 0 - usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask = 0x3FFF - - usb_DEVICE_PCKSIZE_SIZE_Pos = 28 - usb_DEVICE_PCKSIZE_SIZE_Mask = 0x7 - - usb_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos = 14 - usb_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Mask = 0x3FFF - - NumberOfUSBEndpoints = 8 -) - -var ( - endPoints = []uint32{ - usb.CONTROL_ENDPOINT: usb.ENDPOINT_TYPE_CONTROL, - usb.CDC_ENDPOINT_ACM: (usb.ENDPOINT_TYPE_INTERRUPT | usb.EndpointIn), - usb.CDC_ENDPOINT_OUT: (usb.ENDPOINT_TYPE_BULK | usb.EndpointOut), - usb.CDC_ENDPOINT_IN: (usb.ENDPOINT_TYPE_BULK | usb.EndpointIn), - usb.HID_ENDPOINT_IN: (usb.ENDPOINT_TYPE_DISABLE), // Interrupt In - usb.HID_ENDPOINT_OUT: (usb.ENDPOINT_TYPE_DISABLE), // Interrupt Out - usb.MIDI_ENDPOINT_IN: (usb.ENDPOINT_TYPE_DISABLE), // Bulk In - usb.MIDI_ENDPOINT_OUT: (usb.ENDPOINT_TYPE_DISABLE), // Bulk Out - } -) - -// Configure the USB peripheral. The config is here for compatibility with the UART interface. -func (dev *USBDevice) Configure(config UARTConfig) { - if dev.initcomplete { - return - } - - // reset USB interface - sam.USB_DEVICE.CTRLA.SetBits(sam.USB_DEVICE_CTRLA_SWRST) - for sam.USB_DEVICE.SYNCBUSY.HasBits(sam.USB_DEVICE_SYNCBUSY_SWRST) || - sam.USB_DEVICE.SYNCBUSY.HasBits(sam.USB_DEVICE_SYNCBUSY_ENABLE) { - } - - sam.USB_DEVICE.DESCADD.Set(uint32(uintptr(unsafe.Pointer(&usbEndpointDescriptors)))) - - // configure pins - USBCDC_DM_PIN.Configure(PinConfig{Mode: PinCom}) - USBCDC_DP_PIN.Configure(PinConfig{Mode: PinCom}) - - // performs pad calibration from store fuses - handlePadCalibration() - - // run in standby - sam.USB_DEVICE.CTRLA.SetBits(sam.USB_DEVICE_CTRLA_RUNSTDBY) - - // set full speed - sam.USB_DEVICE.CTRLB.SetBits(sam.USB_DEVICE_CTRLB_SPDCONF_FS << sam.USB_DEVICE_CTRLB_SPDCONF_Pos) - - // attach - sam.USB_DEVICE.CTRLB.ClearBits(sam.USB_DEVICE_CTRLB_DETACH) - - // enable interrupt for end of reset - sam.USB_DEVICE.INTENSET.SetBits(sam.USB_DEVICE_INTENSET_EORST) - - // enable interrupt for start of frame - sam.USB_DEVICE.INTENSET.SetBits(sam.USB_DEVICE_INTENSET_SOF) - - // enable USB - sam.USB_DEVICE.CTRLA.SetBits(sam.USB_DEVICE_CTRLA_ENABLE) - - // enable IRQ - interrupt.New(sam.IRQ_USB_OTHER, handleUSBIRQ).Enable() - interrupt.New(sam.IRQ_USB_SOF_HSOF, handleUSBIRQ).Enable() - interrupt.New(sam.IRQ_USB_TRCPT0, handleUSBIRQ).Enable() - interrupt.New(sam.IRQ_USB_TRCPT1, handleUSBIRQ).Enable() - - dev.initcomplete = true -} - -func handlePadCalibration() { - // Load Pad Calibration data from non-volatile memory - // This requires registers that are not included in the SVD file. - // Modeled after defines from samd21g18a.h and nvmctrl.h: - // - // #define NVMCTRL_OTP4 0x00806020 - // - // #define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4) - // #define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */ - // #define USB_FUSES_TRANSN_Msk (0x1Fu << USB_FUSES_TRANSN_Pos) - // #define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))) - - // #define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4) - // #define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */ - // #define USB_FUSES_TRANSP_Msk (0x1Fu << USB_FUSES_TRANSP_Pos) - // #define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))) - - // #define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4) - // #define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */ - // #define USB_FUSES_TRIM_Msk (0x7u << USB_FUSES_TRIM_Pos) - // #define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))) - // - fuse := *(*uint32)(unsafe.Pointer(uintptr(0x00806020) + 4)) - calibTransN := uint16(fuse>>13) & uint16(0x1f) - calibTransP := uint16(fuse>>18) & uint16(0x1f) - calibTrim := uint16(fuse>>23) & uint16(0x7) - - if calibTransN == 0x1f { - calibTransN = 5 - } - sam.USB_DEVICE.PADCAL.SetBits(calibTransN << sam.USB_DEVICE_PADCAL_TRANSN_Pos) - - if calibTransP == 0x1f { - calibTransP = 29 - } - sam.USB_DEVICE.PADCAL.SetBits(calibTransP << sam.USB_DEVICE_PADCAL_TRANSP_Pos) - - if calibTrim == 0x7 { - calibTrim = 3 - } - sam.USB_DEVICE.PADCAL.SetBits(calibTrim << sam.USB_DEVICE_PADCAL_TRIM_Pos) -} - -func handleUSBIRQ(intr interrupt.Interrupt) { - // reset all interrupt flags - flags := sam.USB_DEVICE.INTFLAG.Get() - sam.USB_DEVICE.INTFLAG.Set(flags) - - // End of reset - if (flags & sam.USB_DEVICE_INTFLAG_EORST) > 0 { - // Configure control endpoint - initEndpoint(0, usb.ENDPOINT_TYPE_CONTROL) - - usbConfiguration = 0 - - // ack the End-Of-Reset interrupt - sam.USB_DEVICE.INTFLAG.Set(sam.USB_DEVICE_INTFLAG_EORST) - } - - // Start of frame - if (flags & sam.USB_DEVICE_INTFLAG_SOF) > 0 { - // if you want to blink LED showing traffic, this would be the place... - } - - // Endpoint 0 Setup interrupt - if getEPINTFLAG(0)&sam.USB_DEVICE_ENDPOINT_EPINTFLAG_RXSTP > 0 { - // ack setup received - setEPINTFLAG(0, sam.USB_DEVICE_ENDPOINT_EPINTFLAG_RXSTP) - - // parse setup - setup := usb.NewSetup(udd_ep_out_cache_buffer[0][:]) - - // Clear the Bank 0 ready flag on Control OUT - usbEndpointDescriptors[0].DeviceDescBank[0].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[0])))) - usbEndpointDescriptors[0].DeviceDescBank[0].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) - setEPSTATUSCLR(0, sam.USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY) - - ok := false - if (setup.BmRequestType & usb.REQUEST_TYPE) == usb.REQUEST_STANDARD { - // Standard Requests - ok = handleStandardSetup(setup) - } else { - // Class Interface Requests - if setup.WIndex < uint16(len(usbSetupHandler)) && usbSetupHandler[setup.WIndex] != nil { - ok = usbSetupHandler[setup.WIndex](setup) - } - } - - if ok { - // set Bank1 ready - setEPSTATUSSET(0, sam.USB_DEVICE_ENDPOINT_EPSTATUSSET_BK1RDY) - } else { - // Stall endpoint - setEPSTATUSSET(0, sam.USB_DEVICE_ENDPOINT_EPINTFLAG_STALL1) - } - - if getEPINTFLAG(0)&sam.USB_DEVICE_ENDPOINT_EPINTFLAG_STALL1 > 0 { - // ack the stall - setEPINTFLAG(0, sam.USB_DEVICE_ENDPOINT_EPINTFLAG_STALL1) - - // clear stall request - setEPINTENCLR(0, sam.USB_DEVICE_ENDPOINT_EPINTENCLR_STALL1) - } - } - - // Now the actual transfer handlers, ignore endpoint number 0 (setup) - var i uint32 - for i = 1; i < uint32(len(endPoints)); i++ { - // Check if endpoint has a pending interrupt - epFlags := getEPINTFLAG(i) - setEPINTFLAG(i, epFlags) - if (epFlags & sam.USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT0) > 0 { - buf := handleEndpointRx(i) - if usbRxHandler[i] == nil || usbRxHandler[i](buf) { - AckUsbOutTransfer(i) - } - } else if (epFlags & sam.USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT1) > 0 { - if usbTxHandler[i] != nil { - usbTxHandler[i]() - } - } - } -} - -func initEndpoint(ep, config uint32) { - switch config { - case usb.ENDPOINT_TYPE_INTERRUPT | usb.EndpointIn: - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[1].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[1].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_in_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, ((usb.ENDPOINT_TYPE_INTERRUPT + 1) << sam.USB_DEVICE_ENDPOINT_EPCFG_EPTYPE1_Pos)) - - setEPINTENSET(ep, sam.USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT1) - - case usb.ENDPOINT_TYPE_BULK | usb.EndpointOut: - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[0].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, ((usb.ENDPOINT_TYPE_BULK + 1) << sam.USB_DEVICE_ENDPOINT_EPCFG_EPTYPE0_Pos)) - - // receive interrupts when current transfer complete - setEPINTENSET(ep, sam.USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT0) - - // set byte count to zero, we have not received anything yet - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) - - // ready for next transfer - setEPSTATUSCLR(ep, sam.USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY) - - case usb.ENDPOINT_TYPE_INTERRUPT | usb.EndpointOut: - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[0].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, ((usb.ENDPOINT_TYPE_INTERRUPT + 1) << sam.USB_DEVICE_ENDPOINT_EPCFG_EPTYPE0_Pos)) - - // receive interrupts when current transfer complete - setEPINTENSET(ep, sam.USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT0) - - // set byte count to zero, we have not received anything yet - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) - - // ready for next transfer - setEPSTATUSCLR(ep, sam.USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY) - - case usb.ENDPOINT_TYPE_BULK | usb.EndpointIn: - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[1].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[1].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_in_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, ((usb.ENDPOINT_TYPE_BULK + 1) << sam.USB_DEVICE_ENDPOINT_EPCFG_EPTYPE1_Pos)) - - // NAK on endpoint IN, the bank is not yet filled in. - setEPSTATUSCLR(ep, sam.USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK1RDY) - - setEPINTENSET(ep, sam.USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT1) - - case usb.ENDPOINT_TYPE_CONTROL: - // Control OUT - // set packet size - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.SetBits(epPacketSize(64) << usb_DEVICE_PCKSIZE_SIZE_Pos) - - // set data buffer address - usbEndpointDescriptors[ep].DeviceDescBank[0].ADDR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[ep])))) - - // set endpoint type - setEPCFG(ep, getEPCFG(ep)|((usb.ENDPOINT_TYPE_CONTROL+1)<> - usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) & usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask) - - if bytesread != cdcLineInfoSize { - return b, ErrUSBBytesRead - } - - copy(b[:7], udd_ep_out_cache_buffer[0][:7]) - - return b, nil -} - -func handleEndpointRx(ep uint32) []byte { - // get data - count := int((usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.Get() >> - usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) & usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask) - - return udd_ep_out_cache_buffer[ep][:count] -} - -// AckUsbOutTransfer is called to acknowledge the completion of a USB OUT transfer. -func AckUsbOutTransfer(ep uint32) { - // set byte count to zero - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) - - // set multi packet size to 64 - usbEndpointDescriptors[ep].DeviceDescBank[0].PCKSIZE.SetBits(64 << usb_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) - - // set ready for next data - setEPSTATUSCLR(ep, sam.USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY) -} - -func SendZlp() { - usbEndpointDescriptors[0].DeviceDescBank[1].PCKSIZE.ClearBits(usb_DEVICE_PCKSIZE_BYTE_COUNT_Mask << usb_DEVICE_PCKSIZE_BYTE_COUNT_Pos) -} - -func epPacketSize(size uint16) uint32 { - switch size { - case 8: - return 0 - case 16: - return 1 - case 32: - return 2 - case 64: - return 3 - case 128: - return 4 - case 256: - return 5 - case 512: - return 6 - case 1023: - return 7 - default: - return 0 - } -} - -func getEPCFG(ep uint32) uint8 { - return sam.USB_DEVICE.DEVICE_ENDPOINT[ep].EPCFG.Get() -} - -func setEPCFG(ep uint32, val uint8) { - sam.USB_DEVICE.DEVICE_ENDPOINT[ep].EPCFG.Set(val) -} - -func setEPSTATUSCLR(ep uint32, val uint8) { - sam.USB_DEVICE.DEVICE_ENDPOINT[ep].EPSTATUSCLR.Set(val) -} - -func setEPSTATUSSET(ep uint32, val uint8) { - sam.USB_DEVICE.DEVICE_ENDPOINT[ep].EPSTATUSSET.Set(val) -} - -func getEPSTATUS(ep uint32) uint8 { - return sam.USB_DEVICE.DEVICE_ENDPOINT[ep].EPSTATUS.Get() -} - -func getEPINTFLAG(ep uint32) uint8 { - return sam.USB_DEVICE.DEVICE_ENDPOINT[ep].EPINTFLAG.Get() -} - -func setEPINTFLAG(ep uint32, val uint8) { - sam.USB_DEVICE.DEVICE_ENDPOINT[ep].EPINTFLAG.Set(val) -} - -func setEPINTENCLR(ep uint32, val uint8) { - sam.USB_DEVICE.DEVICE_ENDPOINT[ep].EPINTENCLR.Set(val) -} - -func setEPINTENSET(ep uint32, val uint8) { - sam.USB_DEVICE.DEVICE_ENDPOINT[ep].EPINTENSET.Set(val) -} diff --git a/emb/machine/machine_atsamd51g19.go b/emb/machine/machine_atsamd51g19.go deleted file mode 100644 index f223f6e..0000000 --- a/emb/machine/machine_atsamd51g19.go +++ /dev/null @@ -1,98 +0,0 @@ -//go:build sam && atsamd51 && atsamd51g19 - -// Peripheral abstraction layer for the atsamd51. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf -package machine - -import "device/sam" - -const HSRAM_SIZE = 0x00030000 - -var ( - sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0} - sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1} - sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2} - sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3} - sercomI2CM4 = &I2C{Bus: sam.SERCOM4_I2CM, SERCOM: 4} - sercomI2CM5 = &I2C{Bus: sam.SERCOM5_I2CM, SERCOM: 5} - - sercomSPIM0 = &SPI{Bus: sam.SERCOM0_SPIM, SERCOM: 0} - sercomSPIM1 = &SPI{Bus: sam.SERCOM1_SPIM, SERCOM: 1} - sercomSPIM2 = &SPI{Bus: sam.SERCOM2_SPIM, SERCOM: 2} - sercomSPIM3 = &SPI{Bus: sam.SERCOM3_SPIM, SERCOM: 3} - sercomSPIM4 = &SPI{Bus: sam.SERCOM4_SPIM, SERCOM: 4} - sercomSPIM5 = &SPI{Bus: sam.SERCOM5_SPIM, SERCOM: 5} -) - -// setSERCOMClockGenerator sets the GCLK for sercom -func setSERCOMClockGenerator(sercom uint8, gclk uint32) { - switch sercom { - case 0: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 1: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 2: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 3: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 4: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 5: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - } -} - -// This chip has three TCC peripherals, which have PWM as one feature. -var ( - TCC0 = (*TCC)(sam.TCC0) - TCC1 = (*TCC)(sam.TCC1) - TCC2 = (*TCC)(sam.TCC2) -) - -func (tcc *TCC) configureClock() { - // Turn on timer clocks used for TCC and use generic clock generator 0. - switch tcc.timer() { - case sam.TCC0: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC1: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC2: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC2].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - } -} - -func (tcc *TCC) timerNum() uint8 { - switch tcc.timer() { - case sam.TCC0: - return 0 - case sam.TCC1: - return 1 - case sam.TCC2: - return 2 - default: - return 0x0f // should not happen - } -} diff --git a/emb/machine/machine_atsamd51j19.go b/emb/machine/machine_atsamd51j19.go deleted file mode 100644 index 640e1ef..0000000 --- a/emb/machine/machine_atsamd51j19.go +++ /dev/null @@ -1,110 +0,0 @@ -//go:build sam && atsamd51 && atsamd51j19 - -// Peripheral abstraction layer for the atsamd51. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf -package machine - -import "device/sam" - -const HSRAM_SIZE = 0x00030000 - -var ( - sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0} - sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1} - sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2} - sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3} - sercomI2CM4 = &I2C{Bus: sam.SERCOM4_I2CM, SERCOM: 4} - sercomI2CM5 = &I2C{Bus: sam.SERCOM5_I2CM, SERCOM: 5} - - sercomSPIM0 = &SPI{Bus: sam.SERCOM0_SPIM, SERCOM: 0} - sercomSPIM1 = &SPI{Bus: sam.SERCOM1_SPIM, SERCOM: 1} - sercomSPIM2 = &SPI{Bus: sam.SERCOM2_SPIM, SERCOM: 2} - sercomSPIM3 = &SPI{Bus: sam.SERCOM3_SPIM, SERCOM: 3} - sercomSPIM4 = &SPI{Bus: sam.SERCOM4_SPIM, SERCOM: 4} - sercomSPIM5 = &SPI{Bus: sam.SERCOM5_SPIM, SERCOM: 5} -) - -// setSERCOMClockGenerator sets the GCLK for sercom -func setSERCOMClockGenerator(sercom uint8, gclk uint32) { - switch sercom { - case 0: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 1: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 2: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 3: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 4: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 5: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - } -} - -// This chip has five TCC peripherals, which have PWM as one feature. -var ( - TCC0 = (*TCC)(sam.TCC0) - TCC1 = (*TCC)(sam.TCC1) - TCC2 = (*TCC)(sam.TCC2) - TCC3 = (*TCC)(sam.TCC3) - TCC4 = (*TCC)(sam.TCC4) -) - -func (tcc *TCC) configureClock() { - // Turn on timer clocks used for the TCC and use generic clock generator 0. - switch tcc.timer() { - case sam.TCC0: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC1: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC2: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC2].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC3: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC3].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC4: - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_TCC4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC4].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - } -} - -func (tcc *TCC) timerNum() uint8 { - switch tcc.timer() { - case sam.TCC0: - return 0 - case sam.TCC1: - return 1 - case sam.TCC2: - return 2 - case sam.TCC3: - return 3 - case sam.TCC4: - return 4 - default: - return 0x0f // should not happen - } -} diff --git a/emb/machine/machine_atsamd51j20.go b/emb/machine/machine_atsamd51j20.go deleted file mode 100644 index d582278..0000000 --- a/emb/machine/machine_atsamd51j20.go +++ /dev/null @@ -1,110 +0,0 @@ -//go:build sam && atsamd51 && atsamd51j20 - -// Peripheral abstraction layer for the atsamd51. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf -package machine - -import "device/sam" - -const HSRAM_SIZE = 0x00040000 - -var ( - sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0} - sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1} - sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2} - sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3} - sercomI2CM4 = &I2C{Bus: sam.SERCOM4_I2CM, SERCOM: 4} - sercomI2CM5 = &I2C{Bus: sam.SERCOM5_I2CM, SERCOM: 5} - - sercomSPIM0 = &SPI{Bus: sam.SERCOM0_SPIM, SERCOM: 0} - sercomSPIM1 = &SPI{Bus: sam.SERCOM1_SPIM, SERCOM: 1} - sercomSPIM2 = &SPI{Bus: sam.SERCOM2_SPIM, SERCOM: 2} - sercomSPIM3 = &SPI{Bus: sam.SERCOM3_SPIM, SERCOM: 3} - sercomSPIM4 = &SPI{Bus: sam.SERCOM4_SPIM, SERCOM: 4} - sercomSPIM5 = &SPI{Bus: sam.SERCOM5_SPIM, SERCOM: 5} -) - -// setSERCOMClockGenerator sets the GCLK for sercom -func setSERCOMClockGenerator(sercom uint8, gclk uint32) { - switch sercom { - case 0: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 1: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 2: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 3: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 4: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 5: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - } -} - -// This chip has five TCC peripherals, which have PWM as one feature. -var ( - TCC0 = (*TCC)(sam.TCC0) - TCC1 = (*TCC)(sam.TCC1) - TCC2 = (*TCC)(sam.TCC2) - TCC3 = (*TCC)(sam.TCC3) - TCC4 = (*TCC)(sam.TCC4) -) - -func (tcc *TCC) configureClock() { - // Turn on timer clocks used for TCC and use generic clock generator 0. - switch tcc.timer() { - case sam.TCC0: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC1: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC2: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC2].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC3: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC3].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC4: - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_TCC4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC4].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - } -} - -func (tcc *TCC) timerNum() uint8 { - switch tcc.timer() { - case sam.TCC0: - return 0 - case sam.TCC1: - return 1 - case sam.TCC2: - return 2 - case sam.TCC3: - return 3 - case sam.TCC4: - return 4 - default: - return 0x0f // should not happen - } -} diff --git a/emb/machine/machine_atsamd51p19.go b/emb/machine/machine_atsamd51p19.go deleted file mode 100644 index bcd66a9..0000000 --- a/emb/machine/machine_atsamd51p19.go +++ /dev/null @@ -1,124 +0,0 @@ -//go:build sam && atsamd51 && atsamd51p19 - -// Peripheral abstraction layer for the atsamd51. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf -package machine - -import "device/sam" - -const HSRAM_SIZE = 0x00030000 - -var ( - sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0} - sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1} - sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2} - sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3} - sercomI2CM4 = &I2C{Bus: sam.SERCOM4_I2CM, SERCOM: 4} - sercomI2CM5 = &I2C{Bus: sam.SERCOM5_I2CM, SERCOM: 5} - sercomI2CM6 = &I2C{Bus: sam.SERCOM6_I2CM, SERCOM: 6} - sercomI2CM7 = &I2C{Bus: sam.SERCOM7_I2CM, SERCOM: 7} - - sercomSPIM0 = &SPI{Bus: sam.SERCOM0_SPIM, SERCOM: 0} - sercomSPIM1 = &SPI{Bus: sam.SERCOM1_SPIM, SERCOM: 1} - sercomSPIM2 = &SPI{Bus: sam.SERCOM2_SPIM, SERCOM: 2} - sercomSPIM3 = &SPI{Bus: sam.SERCOM3_SPIM, SERCOM: 3} - sercomSPIM4 = &SPI{Bus: sam.SERCOM4_SPIM, SERCOM: 4} - sercomSPIM5 = &SPI{Bus: sam.SERCOM5_SPIM, SERCOM: 5} - sercomSPIM6 = &SPI{Bus: sam.SERCOM6_SPIM, SERCOM: 6} - sercomSPIM7 = &SPI{Bus: sam.SERCOM7_SPIM, SERCOM: 7} -) - -// setSERCOMClockGenerator sets the GCLK for sercom -func setSERCOMClockGenerator(sercom uint8, gclk uint32) { - switch sercom { - case 0: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 1: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 2: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 3: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 4: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 5: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 6: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM6_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM6_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM6_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 7: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM7_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM7_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM7_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - } -} - -// This chip has five TCC peripherals, which have PWM as one feature. -var ( - TCC0 = (*TCC)(sam.TCC0) - TCC1 = (*TCC)(sam.TCC1) - TCC2 = (*TCC)(sam.TCC2) - TCC3 = (*TCC)(sam.TCC3) - TCC4 = (*TCC)(sam.TCC4) -) - -func (tcc *TCC) configureClock() { - // Turn on timer clocks used for TCC and use generic clock generator 0. - switch tcc.timer() { - case sam.TCC0: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC1: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC2: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC2].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC3: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC3].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC4: - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_TCC4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC4].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - } -} - -func (tcc *TCC) timerNum() uint8 { - switch tcc.timer() { - case sam.TCC0: - return 0 - case sam.TCC1: - return 1 - case sam.TCC2: - return 2 - case sam.TCC3: - return 3 - case sam.TCC4: - return 4 - default: - return 0x0f // should not happen - } -} diff --git a/emb/machine/machine_atsamd51p20.go b/emb/machine/machine_atsamd51p20.go deleted file mode 100644 index 40e435f..0000000 --- a/emb/machine/machine_atsamd51p20.go +++ /dev/null @@ -1,124 +0,0 @@ -//go:build sam && atsamd51 && atsamd51p20 - -// Peripheral abstraction layer for the atsamd51. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf -package machine - -import "device/sam" - -const HSRAM_SIZE = 0x00040000 - -var ( - sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0} - sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1} - sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2} - sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3} - sercomI2CM4 = &I2C{Bus: sam.SERCOM4_I2CM, SERCOM: 4} - sercomI2CM5 = &I2C{Bus: sam.SERCOM5_I2CM, SERCOM: 5} - sercomI2CM6 = &I2C{Bus: sam.SERCOM6_I2CM, SERCOM: 6} - sercomI2CM7 = &I2C{Bus: sam.SERCOM7_I2CM, SERCOM: 7} - - sercomSPIM0 = &SPI{Bus: sam.SERCOM0_SPIM, SERCOM: 0} - sercomSPIM1 = &SPI{Bus: sam.SERCOM1_SPIM, SERCOM: 1} - sercomSPIM2 = &SPI{Bus: sam.SERCOM2_SPIM, SERCOM: 2} - sercomSPIM3 = &SPI{Bus: sam.SERCOM3_SPIM, SERCOM: 3} - sercomSPIM4 = &SPI{Bus: sam.SERCOM4_SPIM, SERCOM: 4} - sercomSPIM5 = &SPI{Bus: sam.SERCOM5_SPIM, SERCOM: 5} - sercomSPIM6 = &SPI{Bus: sam.SERCOM6_SPIM, SERCOM: 6} - sercomSPIM7 = &SPI{Bus: sam.SERCOM7_SPIM, SERCOM: 7} -) - -// setSERCOMClockGenerator sets the GCLK for sercom -func setSERCOMClockGenerator(sercom uint8, gclk uint32) { - switch sercom { - case 0: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 1: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 2: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 3: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 4: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 5: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 6: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM6_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM6_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM6_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 7: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM7_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM7_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM7_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - } -} - -// This chip has five TCC peripherals, which have PWM as one feature. -var ( - TCC0 = (*TCC)(sam.TCC0) - TCC1 = (*TCC)(sam.TCC1) - TCC2 = (*TCC)(sam.TCC2) - TCC3 = (*TCC)(sam.TCC3) - TCC4 = (*TCC)(sam.TCC4) -) - -func (tcc *TCC) configureClock() { - // Turn on timer clocks used for TCC and use generic clock generator 0. - switch tcc.timer() { - case sam.TCC0: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC1: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC2: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC2].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC3: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC3].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC4: - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_TCC4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC4].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - } -} - -func (tcc *TCC) timerNum() uint8 { - switch tcc.timer() { - case sam.TCC0: - return 0 - case sam.TCC1: - return 1 - case sam.TCC2: - return 2 - case sam.TCC3: - return 3 - case sam.TCC4: - return 4 - default: - return 0x0f // should not happen - } -} diff --git a/emb/machine/machine_atsame51j19.go b/emb/machine/machine_atsame51j19.go deleted file mode 100644 index 29ea411..0000000 --- a/emb/machine/machine_atsame51j19.go +++ /dev/null @@ -1,110 +0,0 @@ -//go:build sam && atsame51 && atsame51j19 - -// Peripheral abstraction layer for the atsame51. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf -package machine - -import "device/sam" - -const HSRAM_SIZE = 0x00030000 - -var ( - sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0} - sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1} - sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2} - sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3} - sercomI2CM4 = &I2C{Bus: sam.SERCOM4_I2CM, SERCOM: 4} - sercomI2CM5 = &I2C{Bus: sam.SERCOM5_I2CM, SERCOM: 5} - - sercomSPIM0 = &SPI{Bus: sam.SERCOM0_SPIM, SERCOM: 0} - sercomSPIM1 = &SPI{Bus: sam.SERCOM1_SPIM, SERCOM: 1} - sercomSPIM2 = &SPI{Bus: sam.SERCOM2_SPIM, SERCOM: 2} - sercomSPIM3 = &SPI{Bus: sam.SERCOM3_SPIM, SERCOM: 3} - sercomSPIM4 = &SPI{Bus: sam.SERCOM4_SPIM, SERCOM: 4} - sercomSPIM5 = &SPI{Bus: sam.SERCOM5_SPIM, SERCOM: 5} -) - -// setSERCOMClockGenerator sets the GCLK for sercom -func setSERCOMClockGenerator(sercom uint8, gclk uint32) { - switch sercom { - case 0: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 1: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 2: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 3: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 4: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 5: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - } -} - -// This chip has five TCC peripherals, which have PWM as one feature. -var ( - TCC0 = (*TCC)(sam.TCC0) - TCC1 = (*TCC)(sam.TCC1) - TCC2 = (*TCC)(sam.TCC2) - TCC3 = (*TCC)(sam.TCC3) - TCC4 = (*TCC)(sam.TCC4) -) - -func (tcc *TCC) configureClock() { - // Turn on timer clocks used for the TCC and use generic clock generator 0. - switch tcc.timer() { - case sam.TCC0: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC1: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC2: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC2].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC3: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC3].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC4: - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_TCC4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC4].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - } -} - -func (tcc *TCC) timerNum() uint8 { - switch tcc.timer() { - case sam.TCC0: - return 0 - case sam.TCC1: - return 1 - case sam.TCC2: - return 2 - case sam.TCC3: - return 3 - case sam.TCC4: - return 4 - default: - return 0x0f // should not happen - } -} diff --git a/emb/machine/machine_atsame54p20.go b/emb/machine/machine_atsame54p20.go deleted file mode 100644 index d7cc31f..0000000 --- a/emb/machine/machine_atsame54p20.go +++ /dev/null @@ -1,124 +0,0 @@ -//go:build sam && atsame5x && atsame54p20 - -// Peripheral abstraction layer for the atsame54. -// -// Datasheet: -// http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf -package machine - -import "device/sam" - -const HSRAM_SIZE = 0x00040000 - -var ( - sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0} - sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1} - sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2} - sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3} - sercomI2CM4 = &I2C{Bus: sam.SERCOM4_I2CM, SERCOM: 4} - sercomI2CM5 = &I2C{Bus: sam.SERCOM5_I2CM, SERCOM: 5} - sercomI2CM6 = &I2C{Bus: sam.SERCOM6_I2CM, SERCOM: 6} - sercomI2CM7 = &I2C{Bus: sam.SERCOM7_I2CM, SERCOM: 7} - - sercomSPIM0 = &SPI{Bus: sam.SERCOM0_SPIM, SERCOM: 0} - sercomSPIM1 = &SPI{Bus: sam.SERCOM1_SPIM, SERCOM: 1} - sercomSPIM2 = &SPI{Bus: sam.SERCOM2_SPIM, SERCOM: 2} - sercomSPIM3 = &SPI{Bus: sam.SERCOM3_SPIM, SERCOM: 3} - sercomSPIM4 = &SPI{Bus: sam.SERCOM4_SPIM, SERCOM: 4} - sercomSPIM5 = &SPI{Bus: sam.SERCOM5_SPIM, SERCOM: 5} - sercomSPIM6 = &SPI{Bus: sam.SERCOM6_SPIM, SERCOM: 6} - sercomSPIM7 = &SPI{Bus: sam.SERCOM7_SPIM, SERCOM: 7} -) - -// setSERCOMClockGenerator sets the GCLK for sercom -func setSERCOMClockGenerator(sercom uint8, gclk uint32) { - switch sercom { - case 0: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 1: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 2: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 3: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 4: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 5: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 6: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM6_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM6_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM6_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - case 7: - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM7_CORE].ClearBits(sam.GCLK_PCHCTRL_CHEN) - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM7_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM7_CORE].Set((gclk << sam.GCLK_PCHCTRL_GEN_Pos) | - sam.GCLK_PCHCTRL_CHEN) - } -} - -// This chip has five TCC peripherals, which have PWM as one feature. -var ( - TCC0 = (*TCC)(sam.TCC0) - TCC1 = (*TCC)(sam.TCC1) - TCC2 = (*TCC)(sam.TCC2) - TCC3 = (*TCC)(sam.TCC3) - TCC4 = (*TCC)(sam.TCC4) -) - -func (tcc *TCC) configureClock() { - // Turn on timer clocks used for TCC and use generic clock generator 0. - switch tcc.timer() { - case sam.TCC0: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC0_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC1: - sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC1_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC2: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC2_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC2].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC3: - sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC3_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC3].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - case sam.TCC4: - sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_TCC4_) - sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC4].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN) - } -} - -func (tcc *TCC) timerNum() uint8 { - switch tcc.timer() { - case sam.TCC0: - return 0 - case sam.TCC1: - return 1 - case sam.TCC2: - return 2 - case sam.TCC3: - return 3 - case sam.TCC4: - return 4 - default: - return 0x0f // should not happen - } -} diff --git a/emb/machine/machine_atsame5x_can.go b/emb/machine/machine_atsame5x_can.go deleted file mode 100644 index bf38cd8..0000000 --- a/emb/machine/machine_atsame5x_can.go +++ /dev/null @@ -1,478 +0,0 @@ -//go:build (sam && atsame51) || (sam && atsame54) - -package machine - -import ( - "device/sam" - "errors" - "runtime/interrupt" - "unsafe" -) - -const ( - CANRxFifoSize = 16 - CANTxFifoSize = 16 - CANEvFifoSize = 16 -) - -// Message RAM can only be located in the first 64 KB area of the system RAM. -// TODO: when the go:section pragma is merged, add the section configuration - -//go:align 4 -var CANRxFifo [2][(8 + 64) * CANRxFifoSize]byte - -//go:align 4 -var CANTxFifo [2][(8 + 64) * CANTxFifoSize]byte - -//go:align 4 -var CANEvFifo [2][(8) * CANEvFifoSize]byte - -type CAN struct { - Bus *sam.CAN_Type -} - -type CANTransferRate uint32 - -// CAN transfer rates for CANConfig -const ( - CANTransferRate125kbps CANTransferRate = 125000 - CANTransferRate250kbps CANTransferRate = 250000 - CANTransferRate500kbps CANTransferRate = 500000 - CANTransferRate1000kbps CANTransferRate = 1000000 - CANTransferRate2000kbps CANTransferRate = 2000000 - CANTransferRate4000kbps CANTransferRate = 4000000 -) - -// CANConfig holds CAN configuration parameters. Tx and Rx need to be -// specified with some pins. When the Standby Pin is specified, configure it -// as an output pin and output Low in Configure(). If this operation is not -// necessary, specify NoPin. -type CANConfig struct { - TransferRate CANTransferRate - TransferRateFD CANTransferRate - Tx Pin - Rx Pin - Standby Pin -} - -var ( - errCANInvalidTransferRate = errors.New("CAN: invalid TransferRate") - errCANInvalidTransferRateFD = errors.New("CAN: invalid TransferRateFD") -) - -// Configure this CAN peripheral with the given configuration. -func (can *CAN) Configure(config CANConfig) error { - if config.Standby != NoPin { - config.Standby.Configure(PinConfig{Mode: PinOutput}) - config.Standby.Low() - } - - mode := PinCAN0 - if can.instance() == 1 { - mode = PinCAN1 - } - - config.Rx.Configure(PinConfig{Mode: mode}) - config.Tx.Configure(PinConfig{Mode: mode}) - - can.Bus.CCCR.SetBits(sam.CAN_CCCR_INIT) - for !can.Bus.CCCR.HasBits(sam.CAN_CCCR_INIT) { - } - - can.Bus.CCCR.SetBits(sam.CAN_CCCR_CCE) - - can.Bus.CCCR.SetBits(sam.CAN_CCCR_BRSE | sam.CAN_CCCR_FDOE) - can.Bus.MRCFG.Set(sam.CAN_MRCFG_QOS_MEDIUM) - // base clock == 48 MHz - if config.TransferRate == 0 { - config.TransferRate = CANTransferRate500kbps - } - brp := uint32(6) - switch config.TransferRate { - case CANTransferRate125kbps: - brp = 32 - case CANTransferRate250kbps: - brp = 16 - case CANTransferRate500kbps: - brp = 8 - case CANTransferRate1000kbps: - brp = 4 - default: - return errCANInvalidTransferRate - } - can.Bus.NBTP.Set(8<> sam.CAN_TXFQS_TFQPI_Pos - - f := CANTxFifo[can.instance()][putIndex*(8+64) : (putIndex+1)*(8+64)] - id := e.ID - if !e.XTD { - // standard identifier is stored into ID[28:18] - id <<= 18 - } - - f[3] = byte(id>>24) & 0x1F - if e.ESI { - f[3] |= 0x80 - } - if e.XTD { - f[3] |= 0x40 - } - if e.RTR { - f[3] |= 0x20 - } - f[2] = byte(id >> 16) - f[1] = byte(id >> 8) - f[0] = byte(id) - f[7] = e.MM - f[6] = e.DLC - if e.EFC { - f[6] |= 0x80 - } - if e.FDF { - f[6] |= 0x20 - } - if e.BRS { - f[6] |= 0x10 - } - f[5] = 0x00 // reserved - f[4] = 0x00 // reserved - - length := CANDlcToLength(e.DLC, e.FDF) - for i := byte(0); i < length; i++ { - f[8+i] = e.DB[i] - } - - can.Bus.TXBAR.SetBits(1 << putIndex) -} - -// The Tx transmits CAN frames. It is easier to use than TxRaw, but not as -// flexible. -func (can *CAN) Tx(id uint32, data []byte, isFD, isExtendedID bool) { - length := byte(len(data)) - dlc := CANLengthToDlc(length, true) - - e := CANTxBufferElement{ - ESI: false, - XTD: isExtendedID, - RTR: false, - ID: id, - MM: 0x00, - EFC: true, - FDF: isFD, - BRS: isFD, - DLC: dlc, - } - - if !isFD { - if length > 8 { - length = 8 - } - } - for i := byte(0); i < length; i++ { - e.DB[i] = data[i] - } - - can.TxRaw(&e) -} - -// RxFifoSize returns the number of CAN Frames currently stored in the RXFifo. -func (can *CAN) RxFifoSize() int { - sz := (can.Bus.RXF0S.Get() & sam.CAN_RXF0S_F0FL_Msk) >> sam.CAN_RXF0S_F0FL_Pos - return int(sz) -} - -// RxFifoIsFull returns whether RxFifo is full or not. -func (can *CAN) RxFifoIsFull() bool { - sz := (can.Bus.RXF0S.Get() & sam.CAN_RXF0S_F0FL_Msk) >> sam.CAN_RXF0S_F0FL_Pos - return sz == CANRxFifoSize -} - -// RxFifoIsEmpty returns whether RxFifo is empty or not. -func (can *CAN) RxFifoIsEmpty() bool { - sz := (can.Bus.RXF0S.Get() & sam.CAN_RXF0S_F0FL_Msk) >> sam.CAN_RXF0S_F0FL_Pos - return sz == 0 -} - -// RxRaw copies the received CAN frame to CANRxBufferElement. -func (can *CAN) RxRaw(e *CANRxBufferElement) { - idx := (can.Bus.RXF0S.Get() & sam.CAN_RXF0S_F0GI_Msk) >> sam.CAN_RXF0S_F0GI_Pos - f := CANRxFifo[can.instance()][idx*(8+64):] - - e.ESI = false - if (f[3] & 0x80) != 0x00 { - e.ESI = true - } - - e.XTD = false - if (f[3] & 0x40) != 0x00 { - e.XTD = true - } - - e.RTR = false - if (f[3] & 0x20) != 0x00 { - e.RTR = true - } - - id := ((uint32(f[3]) << 24) + (uint32(f[2]) << 16) + (uint32(f[1]) << 8) + uint32(f[0])) & 0x1FFFFFFF - if !e.XTD { - id >>= 18 - id &= 0x000007FF - } - e.ID = id - - e.ANMF = false - if (f[7] & 0x80) != 0x00 { - e.ANMF = true - } - - e.FIDX = f[7] & 0x7F - - e.FDF = false - if (f[6] & 0x20) != 0x00 { - e.FDF = true - } - - e.BRS = false - if (f[6] & 0x10) != 0x00 { - e.BRS = true - } - - e.DLC = f[6] & 0x0F - - e.RXTS = (uint16(f[5]) << 8) + uint16(f[4]) - - for i := byte(0); i < CANDlcToLength(e.DLC, e.FDF); i++ { - e.DB[i] = f[i+8] - } - - can.Bus.RXF0A.ReplaceBits(idx, sam.CAN_RXF0A_F0AI_Msk, sam.CAN_RXF0A_F0AI_Pos) -} - -// Rx receives a CAN frame. It is easier to use than RxRaw, but not as -// flexible. -func (can *CAN) Rx() (id uint32, dlc byte, data []byte, isFd, isExtendedID bool) { - e := CANRxBufferElement{} - can.RxRaw(&e) - length := CANDlcToLength(e.DLC, e.FDF) - return e.ID, length, e.DB[:length], e.FDF, e.XTD -} - -func (can *CAN) instance() byte { - if can.Bus == sam.CAN0 { - return 0 - } else { - return 1 - } -} - -// CANTxBufferElement is a struct that corresponds to the same5x' Tx Buffer -// Element. -type CANTxBufferElement struct { - ESI bool - XTD bool - RTR bool - ID uint32 - MM uint8 - EFC bool - FDF bool - BRS bool - DLC uint8 - DB [64]uint8 -} - -// CANRxBufferElement is a struct that corresponds to the same5x Rx Buffer and -// FIFO Element. -type CANRxBufferElement struct { - ESI bool - XTD bool - RTR bool - ID uint32 - ANMF bool - FIDX uint8 - FDF bool - BRS bool - DLC uint8 - RXTS uint16 - DB [64]uint8 -} - -// Data returns the received data as a slice of the size according to dlc. -func (e CANRxBufferElement) Data() []byte { - return e.DB[:CANDlcToLength(e.DLC, e.FDF)] -} - -// Length returns its actual length. -func (e CANRxBufferElement) Length() byte { - return CANDlcToLength(e.DLC, e.FDF) -} - -// CANDlcToLength() converts a DLC value to its actual length. -func CANDlcToLength(dlc byte, isFD bool) byte { - length := dlc - if dlc == 0x09 { - length = 12 - } else if dlc == 0x0A { - length = 16 - } else if dlc == 0x0B { - length = 20 - } else if dlc == 0x0C { - length = 24 - } else if dlc == 0x0D { - length = 32 - } else if dlc == 0x0E { - length = 48 - } else if dlc == 0x0F { - length = 64 - } - return length - -} - -// CANLengthToDlc() converts its actual length to a DLC value. -func CANLengthToDlc(length byte, isFD bool) byte { - dlc := length - if length <= 0x08 { - } else if length <= 12 { - dlc = 0x09 - } else if length <= 16 { - dlc = 0x0A - } else if length <= 20 { - dlc = 0x0B - } else if length <= 24 { - dlc = 0x0C - } else if length <= 32 { - dlc = 0x0D - } else if length <= 48 { - dlc = 0x0E - } else if length <= 64 { - dlc = 0x0F - } - return dlc -} diff --git a/emb/machine/machine_attiny1616.go b/emb/machine/machine_attiny1616.go deleted file mode 100644 index 55007ab..0000000 --- a/emb/machine/machine_attiny1616.go +++ /dev/null @@ -1,52 +0,0 @@ -//go:build attiny1616 - -package machine - -import ( - "device/avr" -) - -const ( - portA Pin = iota * 8 - portB - portC -) - -const ( - PA0 = portA + 0 - PA1 = portA + 1 - PA2 = portA + 2 - PA3 = portA + 3 - PA4 = portA + 4 - PA5 = portA + 5 - PA6 = portA + 6 - PA7 = portA + 7 - PB0 = portB + 0 - PB1 = portB + 1 - PB2 = portB + 2 - PB3 = portB + 3 - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 -) - -// getPortMask returns the PORT peripheral and mask for the pin. -func (p Pin) getPortMask() (*avr.PORT_Type, uint8) { - switch { - case p >= PA0 && p <= PA7: // port A - return avr.PORTA, 1 << uint8(p-portA) - case p >= PB0 && p <= PB7: // port B - return avr.PORTB, 1 << uint8(p-portB) - default: // port C - return avr.PORTC, 1 << uint8(p-portC) - } -} diff --git a/emb/machine/machine_attiny85.go b/emb/machine/machine_attiny85.go deleted file mode 100644 index 33424c6..0000000 --- a/emb/machine/machine_attiny85.go +++ /dev/null @@ -1,23 +0,0 @@ -//go:build attiny85 - -package machine - -import ( - "device/avr" - "runtime/volatile" -) - -const ( - PB0 Pin = iota - PB1 - PB2 - PB3 - PB4 - PB5 -) - -// getPortMask returns the PORTx register and mask for the pin. -func (p Pin) getPortMask() (*volatile.Register8, uint8) { - // Very simple for the attiny85, which only has a single port. - return avr.PORTB, 1 << uint8(p) -} diff --git a/emb/machine/machine_avr.go b/emb/machine/machine_avr.go deleted file mode 100644 index 75252c3..0000000 --- a/emb/machine/machine_avr.go +++ /dev/null @@ -1,150 +0,0 @@ -//go:build avr && !avrtiny - -package machine - -import ( - "device/avr" - "runtime/volatile" - "unsafe" -) - -const deviceName = avr.DEVICE - -const ( - PinInput PinMode = iota - PinInputPullup - PinOutput -) - -// In all the AVRs I've looked at, the PIN/DDR/PORT registers followed a regular -// pattern: PINx, DDRx, PORTx in this order without registers in between. -// Therefore, if you know any of them, you can calculate the other two. -// -// For now, I've chosen to let the PORTx register be the one that is returned -// for each specific chip and to calculate the others from that one. Setting an -// output port (done using PORTx) is likely the most common operation and the -// one that is the most time critical. For others, the PINx and DDRx register -// can trivially be calculated using a subtraction. - -// Configure sets the pin to input or output. -func (p Pin) Configure(config PinConfig) { - port, mask := p.getPortMask() - // The DDRx register can be found by subtracting one from the PORTx - // register, as this appears to be the case for many (most? all?) AVR chips. - ddr := (*volatile.Register8)(unsafe.Pointer(uintptr(unsafe.Pointer(port)) - 1)) - if config.Mode == PinOutput { - // set output bit - ddr.SetBits(mask) - - // Note: if the pin was PinInputPullup before, it'll now be high. - // Otherwise it will be low. - } else { - // configure input: clear output bit - ddr.ClearBits(mask) - - if config.Mode == PinInput { - // No pullup (floating). - // The transition may be one of the following: - // output high -> input pullup -> input (safe: output high and input pullup are similar) - // output low -> input -> input (safe: no extra transition) - port.ClearBits(mask) - } else { - // Pullup. - // The transition may be one of the following: - // output high -> input pullup -> input pullup (safe: no extra transition) - // output low -> input -> input pullup (possibly problematic) - // For the last transition (output low -> input -> input pullup), - // the transition may be problematic in some cases because there is - // an intermediate floating state (which may cause irratic - // interrupts, for example). If this is a problem, the application - // should set the pin high before configuring it as PinInputPullup. - // We can't do that here because setting it to high as an - // intermediate state may have other problems. - port.SetBits(mask) - } - } -} - -// Get returns the current value of a GPIO pin when the pin is configured as an -// input or as an output. -func (p Pin) Get() bool { - port, mask := p.getPortMask() - // As noted above, the PINx register is always two registers below the PORTx - // register, so we can find it simply by subtracting two from the PORTx - // register address. - pin := (*volatile.Register8)(unsafe.Pointer(uintptr(unsafe.Pointer(port)) - 2)) // PINA, PINB, etc - return (pin.Get() & mask) > 0 -} - -// Set changes the value of the GPIO pin. The pin must be configured as output. -func (p Pin) Set(value bool) { - if value { // set bits - port, mask := p.PortMaskSet() - port.Set(mask) - } else { // clear bits - port, mask := p.PortMaskClear() - port.Set(mask) - } -} - -// Return the register and mask to enable a given GPIO pin. This can be used to -// implement bit-banged drivers. -// -// Warning: there are no separate pin set/clear registers on the AVR. The -// returned mask is only valid as long as no other pin in the same port has been -// changed. -func (p Pin) PortMaskSet() (*volatile.Register8, uint8) { - port, mask := p.getPortMask() - return port, port.Get() | mask -} - -// Return the register and mask to disable a given port. This can be used to -// implement bit-banged drivers. -// -// Warning: there are no separate pin set/clear registers on the AVR. The -// returned mask is only valid as long as no other pin in the same port has been -// changed. -func (p Pin) PortMaskClear() (*volatile.Register8, uint8) { - port, mask := p.getPortMask() - return port, port.Get() &^ mask -} - -// InitADC initializes the registers needed for ADC. -func InitADC() { - // set a2d prescaler so we are inside the desired 50-200 KHz range at 16MHz. - avr.ADCSRA.SetBits(avr.ADCSRA_ADPS2 | avr.ADCSRA_ADPS1 | avr.ADCSRA_ADPS0) - - // enable a2d conversions - avr.ADCSRA.SetBits(avr.ADCSRA_ADEN) -} - -// Configure configures a ADCPin to be able to be used to read data. -func (a ADC) Configure(ADCConfig) { - return // no pin specific setup on AVR machine. -} - -// Get returns the current value of a ADC pin, in the range 0..0xffff. The AVR -// has an ADC of 10 bits precision so the lower 6 bits will be zero. -func (a ADC) Get() uint16 { - // set the analog reference (high two bits of ADMUX) and select the - // channel (low 4 bits), masked to only turn on one ADC at a time. - // set the ADLAR bit (left-adjusted result) to get a value scaled to 16 - // bits. This has the same effect as shifting the return value left by 6 - // bits. - avr.ADMUX.Set(avr.ADMUX_REFS0 | avr.ADMUX_ADLAR | (uint8(a.Pin) & 0x07)) - - // start the conversion - avr.ADCSRA.SetBits(avr.ADCSRA_ADSC) - - // ADSC is cleared when the conversion finishes - for ok := true; ok; ok = avr.ADCSRA.HasBits(avr.ADCSRA_ADSC) { - } - - return uint16(avr.ADCL.Get()) | uint16(avr.ADCH.Get())<<8 -} - -// linked from runtime.adjustMonotonicTimer -func adjustMonotonicTimer() - -// linked from runtime.initMonotonicTimer -func initMonotonicTimer() diff --git a/emb/machine/machine_avrtiny.go b/emb/machine/machine_avrtiny.go deleted file mode 100644 index 78168f4..0000000 --- a/emb/machine/machine_avrtiny.go +++ /dev/null @@ -1,62 +0,0 @@ -//go:build avrtiny - -package machine - -import ( - "device/avr" - "runtime/volatile" - "unsafe" -) - -const deviceName = avr.DEVICE - -const ( - PinInput PinMode = iota - PinInputPullup - PinOutput -) - -// Configure sets the pin to input or output. -func (p Pin) Configure(config PinConfig) { - port, mask := p.getPortMask() - - if config.Mode == PinOutput { - // set output bit - port.DIRSET.Set(mask) - - // Note: the output state (high or low) is as it was before. - } else { - // Configure the pin as an input. - // First set up the configuration that will be used when it is an input. - pinctrl := uint8(0) - if config.Mode == PinInputPullup { - pinctrl |= avr.PORT_PIN0CTRL_PULLUPEN - } - // Find the PINxCTRL register for this pin. - ctrlAddress := (*volatile.Register8)(unsafe.Add(unsafe.Pointer(&port.PIN0CTRL), p%8)) - ctrlAddress.Set(pinctrl) - - // Configure the pin as input (if it wasn't an input pin before). - port.DIRCLR.Set(mask) - } -} - -// Get returns the current value of a GPIO pin when the pin is configured as an -// input or as an output. -func (p Pin) Get() bool { - port, mask := p.getPortMask() - // As noted above, the PINx register is always two registers below the PORTx - // register, so we can find it simply by subtracting two from the PORTx - // register address. - return (port.IN.Get() & mask) > 0 -} - -// Set changes the value of the GPIO pin. The pin must be configured as output. -func (p Pin) Set(high bool) { - port, mask := p.getPortMask() - if high { - port.OUTSET.Set(mask) - } else { - port.OUTCLR.Set(mask) - } -} diff --git a/emb/machine/machine_cortexm.go b/emb/machine/machine_cortexm.go deleted file mode 100644 index 0f8f264..0000000 --- a/emb/machine/machine_cortexm.go +++ /dev/null @@ -1,10 +0,0 @@ -//go:build cortexm - -package machine - -import "device/arm" - -// CPUReset performs a hard system reset. -func CPUReset() { - arm.SystemReset() -} diff --git a/emb/machine/machine_fe310.go b/emb/machine/machine_fe310.go deleted file mode 100644 index 2f716d6..0000000 --- a/emb/machine/machine_fe310.go +++ /dev/null @@ -1,370 +0,0 @@ -//go:build fe310 - -package machine - -import ( - "device/sifive" - "runtime/interrupt" - "unsafe" -) - -const deviceName = sifive.Device - -func CPUFrequency() uint32 { - return 320000000 // 320MHz -} - -const ( - PinInput PinMode = iota - PinOutput - PinPWM - PinSPI - PinI2C = PinSPI -) - -// Configure this pin with the given configuration. -func (p Pin) Configure(config PinConfig) { - sifive.GPIO0.INPUT_EN.SetBits(1 << uint8(p)) - switch config.Mode { - case PinInput: - sifive.GPIO0.OUTPUT_EN.ClearBits(1 << uint8(p)) - case PinOutput: - sifive.GPIO0.OUTPUT_EN.SetBits(1 << uint8(p)) - case PinPWM: - sifive.GPIO0.IOF_EN.SetBits(1 << uint8(p)) - sifive.GPIO0.IOF_SEL.SetBits(1 << uint8(p)) - case PinSPI: - sifive.GPIO0.IOF_EN.SetBits(1 << uint8(p)) - sifive.GPIO0.IOF_SEL.ClearBits(1 << uint8(p)) - } -} - -// Set the pin to high or low. -func (p Pin) Set(high bool) { - if high { - sifive.GPIO0.PORT.SetBits(1 << uint8(p)) - } else { - sifive.GPIO0.PORT.ClearBits(1 << uint8(p)) - } -} - -// Get returns the current value of a GPIO pin when the pin is configured as an -// input or as an output. -func (p Pin) Get() bool { - val := sifive.GPIO0.VALUE.Get() & (1 << uint8(p)) - return (val > 0) -} - -// Return the register and mask to enable a given GPIO pin. This can be used to -// implement bit-banged drivers. -// -// Warning: only use this on an output pin! -func (p Pin) PortMaskSet() (*uint32, uint32) { - return (*uint32)(unsafe.Pointer(&sifive.GPIO0.PORT)), sifive.GPIO0.PORT.Get() | (1 << uint8(p)) -} - -// Return the register and mask to disable a given GPIO pin. This can be used to -// implement bit-banged drivers. -// -// Warning: only use this on an output pin! -func (p Pin) PortMaskClear() (*uint32, uint32) { - return (*uint32)(unsafe.Pointer(&sifive.GPIO0.PORT)), sifive.GPIO0.PORT.Get() &^ (1 << uint8(p)) -} - -type UART struct { - Bus *sifive.UART_Type - Buffer *RingBuffer -} - -var ( - UART0 = &_UART0 - _UART0 = UART{Bus: sifive.UART0, Buffer: NewRingBuffer()} -) - -func (uart *UART) Configure(config UARTConfig) { - if config.BaudRate == 0 { - config.BaudRate = 115200 - } - // The divisor is: - // fbaud = fin / (div + 1) - // Restating to get the divisor: - // div = fin / fbaud - 1 - // But we're using integers, so we should take care of rounding: - // div = (fin + fbaud/2) / fbaud - 1 - divisor := (CPUFrequency()+config.BaudRate/2)/config.BaudRate - 1 - sifive.UART0.DIV.Set(divisor) - sifive.UART0.TXCTRL.Set(sifive.UART_TXCTRL_ENABLE) - sifive.UART0.RXCTRL.Set(sifive.UART_RXCTRL_ENABLE) - sifive.UART0.IE.Set(sifive.UART_IE_RXWM) // enable the receive interrupt (only) - intr := interrupt.New(sifive.IRQ_UART0, _UART0.handleInterrupt) - intr.SetPriority(5) - intr.Enable() -} - -func (uart *UART) handleInterrupt(interrupt.Interrupt) { - rxdata := uart.Bus.RXDATA.Get() - c := byte(rxdata) - if uint32(c) != rxdata { - // The rxdata has other bits set than just the low 8 bits. This probably - // means that the 'empty' flag is set, which indicates there is no data - // to be read and the byte is garbage. Ignore this byte. - return - } - uart.Receive(c) -} - -func (uart *UART) writeByte(c byte) error { - for sifive.UART0.TXDATA.Get()&sifive.UART_TXDATA_FULL != 0 { - } - - sifive.UART0.TXDATA.Set(uint32(c)) - return nil -} - -func (uart *UART) flush() {} - -// SPI on the FE310. The normal SPI0 is actually a quad-SPI meant for flash, so it is best -// to use SPI1 or SPI2 port for most applications. -type SPI struct { - Bus *sifive.QSPI_Type -} - -// SPIConfig is used to store config info for SPI. -type SPIConfig struct { - Frequency uint32 - SCK Pin - SDO Pin - SDI Pin - LSBFirst bool - Mode uint8 -} - -// Configure is intended to setup the SPI interface. -func (spi *SPI) Configure(config SPIConfig) error { - // Use default pins if not set. - if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 { - config.SCK = SPI0_SCK_PIN - config.SDO = SPI0_SDO_PIN - config.SDI = SPI0_SDI_PIN - } - - // enable pins for SPI - config.SCK.Configure(PinConfig{Mode: PinSPI}) - config.SDO.Configure(PinConfig{Mode: PinSPI}) - config.SDI.Configure(PinConfig{Mode: PinSPI}) - - // set default frequency - if config.Frequency == 0 { - config.Frequency = 4000000 // 4MHz - } - - // div = (SPI_CFG(dev)->f_sys / (2 * frequency)) - 1; - div := CPUFrequency()/(2*config.Frequency) - 1 - spi.Bus.DIV.Set(div) - - // set mode - switch config.Mode { - case 0: - spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_PHASE) - spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_POLARITY) - case 1: - spi.Bus.MODE.SetBits(sifive.QSPI_MODE_PHASE) - spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_POLARITY) - case 2: - spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_PHASE) - spi.Bus.MODE.SetBits(sifive.QSPI_MODE_POLARITY) - case 3: - spi.Bus.MODE.SetBits(sifive.QSPI_MODE_PHASE | sifive.QSPI_MODE_POLARITY) - default: // to mode 0 - spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_PHASE) - spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_POLARITY) - } - - // frame length - spi.Bus.FMT.SetBits(8 << sifive.QSPI_FMT_LENGTH_Pos) - - // Set single line operation, by clearing all bits - spi.Bus.FMT.ClearBits(sifive.QSPI_FMT_PROTOCOL_Msk) - - // set bit transfer order - if config.LSBFirst { - spi.Bus.FMT.SetBits(sifive.QSPI_FMT_ENDIAN) - } else { - spi.Bus.FMT.ClearBits(sifive.QSPI_FMT_ENDIAN) - } - - return nil -} - -// Transfer writes/reads a single byte using the SPI interface. -func (spi *SPI) Transfer(w byte) (byte, error) { - // wait for tx ready - for spi.Bus.TXDATA.HasBits(sifive.QSPI_TXDATA_FULL) { - } - - // write data - spi.Bus.TXDATA.Set(uint32(w)) - - // wait until receive has data - data := spi.Bus.RXDATA.Get() - for data&sifive.QSPI_RXDATA_EMPTY > 0 { - data = spi.Bus.RXDATA.Get() - } - - // return data - return byte(data), nil -} - -// I2C on the FE310-G002. -type I2C struct { - Bus sifive.I2C_Type -} - -var ( - I2C0 = (*I2C)(unsafe.Pointer(sifive.I2C0)) -) - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 - SCL Pin - SDA Pin -} - -var i2cClockFrequency uint32 = 32000000 - -// Configure is intended to setup the I2C interface. -func (i2c *I2C) Configure(config I2CConfig) error { - if config.Frequency == 0 { - config.Frequency = 100 * KHz - } - - if config.SDA == 0 && config.SCL == 0 { - config.SDA = I2C0_SDA_PIN - config.SCL = I2C0_SCL_PIN - } - - i2c.SetBaudRate(config.Frequency) - - config.SDA.Configure(PinConfig{Mode: PinI2C}) - config.SCL.Configure(PinConfig{Mode: PinI2C}) - - return nil -} - -// SetBaudRate sets the communication speed for I2C. -func (i2c *I2C) SetBaudRate(br uint32) error { - var prescaler = i2cClockFrequency/(5*br) - 1 - - // disable controller before setting the prescale registers - i2c.Bus.CTR.ClearBits(sifive.I2C_CTR_EN) - - // set prescaler registers - i2c.Bus.PRER_LO.Set(uint32(prescaler & 0xff)) - i2c.Bus.PRER_HI.Set(uint32((prescaler >> 8) & 0xff)) - - // enable controller - i2c.Bus.CTR.SetBits(sifive.I2C_CTR_EN) - - return nil -} - -// Tx does a single I2C transaction at the specified address. -// It clocks out the given address, writes the bytes in w, reads back len(r) -// bytes and stores them in r, and generates a stop condition on the bus. -func (i2c *I2C) Tx(addr uint16, w, r []byte) error { - var err error - if len(w) != 0 { - // send start/address for write - i2c.sendAddress(addr, true) - - // ACK received (0: ACK, 1: NACK) - if i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_RX_ACK) { - return errI2CAckExpected - } - - // write data - for _, b := range w { - err = i2c.writeByte(b) - if err != nil { - return err - } - } - } - if len(r) != 0 { - // send start/address for read - i2c.sendAddress(addr, false) - - // ACK received (0: ACK, 1: NACK) - if i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_RX_ACK) { - return errI2CAckExpected - } - - // read first byte - r[0] = i2c.readByte() - for i := 1; i < len(r); i++ { - // send an ACK - i2c.Bus.CR_SR.Set(^uint32(sifive.I2C_CR_ACK)) - - // read data and send the ACK - r[i] = i2c.readByte() - } - - // send NACK to end transmission - i2c.Bus.CR_SR.Set(sifive.I2C_CR_ACK) - } - - // generate stop condition - i2c.Bus.CR_SR.Set(sifive.I2C_CR_STO) - return nil -} - -// Writes a single byte to the I2C bus. -func (i2c *I2C) writeByte(data byte) error { - // Send data byte - i2c.Bus.TXR_RXR.Set(uint32(data)) - - i2c.Bus.CR_SR.Set(sifive.I2C_CR_WR) - - // wait until transmission complete - for i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_TIP) { - } - - // ACK received (0: ACK, 1: NACK) - if i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_RX_ACK) { - return errI2CAckExpected - } - - return nil -} - -// Reads a single byte from the I2C bus. -func (i2c *I2C) readByte() byte { - i2c.Bus.CR_SR.Set(sifive.I2C_CR_RD) - - // wait until transmission complete - for i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_TIP) { - } - - return byte(i2c.Bus.TXR_RXR.Get()) -} - -// Sends the address and start signal. -func (i2c *I2C) sendAddress(address uint16, write bool) error { - data := (address << 1) - if !write { - data |= 1 // set read flag in transmit register - } - - // write address to transmit register - i2c.Bus.TXR_RXR.Set(uint32(data)) - - // generate start condition - i2c.Bus.CR_SR.Set((sifive.I2C_CR_STA | sifive.I2C_CR_WR)) - - // wait until transmission complete - for i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_TIP) { - } - - return nil -} diff --git a/emb/machine/machine_gameboyadvance.go b/emb/machine/machine_gameboyadvance.go deleted file mode 100644 index a5c0c06..0000000 --- a/emb/machine/machine_gameboyadvance.go +++ /dev/null @@ -1,64 +0,0 @@ -//go:build gameboyadvance - -package machine - -import ( - "device/gba" - - "image/color" - "runtime/volatile" - "unsafe" -) - -// Not sure what name to pick here. Not using ARM7TDMI because that's the CPU -// name, not the device name. -const deviceName = "GBA" - -// Interrupt numbers as used on the GameBoy Advance. Register them with -// runtime/interrupt.New. -const ( - IRQ_VBLANK = gba.IRQ_VBLANK - IRQ_HBLANK = gba.IRQ_HBLANK - IRQ_VCOUNT = gba.IRQ_VCOUNT - IRQ_TIMER0 = gba.IRQ_TIMER0 - IRQ_TIMER1 = gba.IRQ_TIMER1 - IRQ_TIMER2 = gba.IRQ_TIMER2 - IRQ_TIMER3 = gba.IRQ_TIMER3 - IRQ_COM = gba.IRQ_COM - IRQ_DMA0 = gba.IRQ_DMA0 - IRQ_DMA1 = gba.IRQ_DMA1 - IRQ_DMA2 = gba.IRQ_DMA2 - IRQ_DMA3 = gba.IRQ_DMA3 - IRQ_KEYPAD = gba.IRQ_KEYPAD - IRQ_GAMEPAK = gba.IRQ_GAMEPAK -) - -// Set has not been implemented. -func (p Pin) Set(value bool) { - // do nothing -} - -var Display = DisplayMode3{(*[160][240]volatile.Register16)(unsafe.Pointer(uintptr(gba.MEM_VRAM)))} - -type DisplayMode3 struct { - port *[160][240]volatile.Register16 -} - -func (d *DisplayMode3) Configure() { - // Use video mode 3 (in BG2, a 16bpp bitmap in VRAM) and Enable BG2 - gba.DISP.DISPCNT.Set(gba.DISPCNT_BGMODE_3<> 3) | ((uint16(c.G) >> 3) << 5) | ((uint16(c.B) >> 3) << 10)) -} - -func (d *DisplayMode3) Display() error { - // Nothing to do here. - return nil -} diff --git a/emb/machine/machine_generic_peripherals.go b/emb/machine/machine_generic_peripherals.go deleted file mode 100644 index 6c95c20..0000000 --- a/emb/machine/machine_generic_peripherals.go +++ /dev/null @@ -1,14 +0,0 @@ -//go:build !baremetal && !arduino_mkr1000 && !arduino_mkrwifi1010 && !arduino_nano33 && !arduino_zero && !circuitplay_express && !feather_m0 && !feather_m4 && !grandcentral_m4 && !itsybitsy_m0 && !itsybitsy_m4 && !matrixportal_m4 && !metro_m4_airlift && !p1am_100 && !pybadge && !pygamer && !pyportal && !qtpy && !trinket_m0 && !wioterminal && !xiao - -package machine - -// These peripherals are defined separately so that they can be excluded on -// boards that define their peripherals in the board file (e.g. board_qtpy.go). - -var ( - UART0 = hardwareUART0 - UART1 = hardwareUART1 - SPI0 = &SPI{0} - SPI1 = &SPI{1} - I2C0 = &I2C{0} -) diff --git a/emb/machine/machine_k210.go b/emb/machine/machine_k210.go deleted file mode 100644 index d83576a..0000000 --- a/emb/machine/machine_k210.go +++ /dev/null @@ -1,661 +0,0 @@ -//go:build k210 - -package machine - -import ( - "device/kendryte" - "device/riscv" - "errors" - "runtime/interrupt" - "unsafe" -) - -const deviceName = kendryte.Device - -func CPUFrequency() uint32 { - return 390000000 -} - -type fpioaPullMode uint8 -type PinChange uint8 - -// Pin modes. -const ( - PinInput PinMode = iota - PinInputPullup - PinInputPulldown - PinOutput -) - -// Deprecated: use PinInputPullup and PinInputPulldown instead. -const ( - PinInputPullUp = PinInputPullup - PinInputPullDown = PinInputPulldown -) - -// FPIOA internal pull resistors. -const ( - fpioaPullNone fpioaPullMode = iota - fpioaPullDown - fpioaPullUp -) - -// GPIOHS pin interrupt events. -const ( - PinRising PinChange = 1 << iota - PinFalling - PinToggle = PinRising | PinFalling -) - -var ( - errUnsupportedSPIController = errors.New("SPI controller not supported. Use SPI0 or SPI1.") - errI2CTxAbort = errors.New("I2C transmission has been aborted.") -) - -func (p Pin) setFPIOAIOPull(pull fpioaPullMode) { - switch pull { - case fpioaPullNone: - kendryte.FPIOA.IO[uint8(p)].ClearBits(kendryte.FPIOA_IO_PU & kendryte.FPIOA_IO_PD) - case fpioaPullUp: - kendryte.FPIOA.IO[uint8(p)].SetBits(kendryte.FPIOA_IO_PU) - kendryte.FPIOA.IO[uint8(p)].ClearBits(kendryte.FPIOA_IO_PD) - case fpioaPullDown: - kendryte.FPIOA.IO[uint8(p)].ClearBits(kendryte.FPIOA_IO_PU) - kendryte.FPIOA.IO[uint8(p)].SetBits(kendryte.FPIOA_IO_PD) - } -} - -// SetFPIOAFunction is used to configure the pin for one of the FPIOA functions. -// Each pin on the Kendryte K210 can be configured with any of the available FPIOA functions. -func (p Pin) SetFPIOAFunction(f FPIOAFunction) { - kendryte.FPIOA.IO[uint8(p)].Set(fpioaFuncDefaults[uint8(f)]) -} - -// FPIOAFunction returns the current FPIOA function of the pin. -func (p Pin) FPIOAFunction() FPIOAFunction { - return FPIOAFunction((kendryte.FPIOA.IO[uint8(p)].Get() & kendryte.FPIOA_IO_CH_SEL_Msk)) -} - -// Configure this pin with the given configuration. -// The pin must already be set as GPIO or GPIOHS pin. -func (p Pin) Configure(config PinConfig) { - var input bool - - // Check if the current pin's FPIOA function is either GPIO or GPIOHS. - f := p.FPIOAFunction() - if f < FUNC_GPIOHS0 || f > FUNC_GPIO7 { - return // The pin is not configured as GPIO or GPIOHS. - } - - // Configure pin. - kendryte.FPIOA.IO[uint8(p)].SetBits(kendryte.FPIOA_IO_OE_EN | kendryte.FPIOA_IO_IE_EN | kendryte.FPIOA_IO_ST | kendryte.FPIOA_IO_DS_Msk) - - switch config.Mode { - case PinInput: - p.setFPIOAIOPull(fpioaPullNone) - input = true - case PinInputPullup: - p.setFPIOAIOPull(fpioaPullUp) - input = true - case PinInputPulldown: - p.setFPIOAIOPull(fpioaPullDown) - input = true - case PinOutput: - p.setFPIOAIOPull(fpioaPullNone) - input = false - } - - if f >= FUNC_GPIO0 && f <= FUNC_GPIO7 { - // Converts the IO pin number in the effective GPIO number (based on the FPIOA function). - gpioPin := uint8(f - FUNC_GPIO0) - - if input { - kendryte.GPIO.DIRECTION.ClearBits(1 << gpioPin) - } else { - kendryte.GPIO.DIRECTION.SetBits(1 << gpioPin) - } - } else if f >= FUNC_GPIOHS0 && f <= FUNC_GPIOHS31 { - // Converts the IO pin number in the effective GPIOHS number (based on the FPIOA function). - gpioPin := uint8(f - FUNC_GPIOHS0) - - if input { - kendryte.GPIOHS.INPUT_EN.SetBits(1 << gpioPin) - kendryte.GPIOHS.OUTPUT_EN.ClearBits(1 << gpioPin) - } else { - kendryte.GPIOHS.OUTPUT_EN.SetBits(1 << gpioPin) - kendryte.GPIOHS.INPUT_EN.ClearBits(1 << gpioPin) - } - } -} - -// Set the pin to high or low. -func (p Pin) Set(high bool) { - - // Check if the current pin's FPIOA function is either GPIO or GPIOHS. - f := p.FPIOAFunction() - if f < FUNC_GPIOHS0 || f > FUNC_GPIO7 { - return // The pin is not configured as GPIO or GPIOHS. - } - - if f >= FUNC_GPIO0 && f <= FUNC_GPIO7 { - gpioPin := uint8(f - FUNC_GPIO0) - - if high { - kendryte.GPIO.DATA_OUTPUT.SetBits(1 << gpioPin) - } else { - kendryte.GPIO.DATA_OUTPUT.ClearBits(1 << gpioPin) - } - } else if f >= FUNC_GPIOHS0 && f <= FUNC_GPIOHS31 { - gpioPin := uint8(f - FUNC_GPIOHS0) - - if high { - kendryte.GPIOHS.OUTPUT_VAL.SetBits(1 << gpioPin) - } else { - kendryte.GPIOHS.OUTPUT_VAL.ClearBits(1 << gpioPin) - } - } -} - -// Get returns the current value of a GPIO pin. -func (p Pin) Get() bool { - - // Check if the current pin's FPIOA function is either GPIO or GPIOHS. - f := p.FPIOAFunction() - if f < FUNC_GPIOHS0 || f > FUNC_GPIO7 { - return false // The pin is not configured as GPIO or GPIOHS. - } - - var val uint32 - if f >= FUNC_GPIO0 && f <= FUNC_GPIO7 { - gpioPin := uint8(f - FUNC_GPIO0) - val = kendryte.GPIO.DATA_INPUT.Get() & (1 << gpioPin) - } else if f >= FUNC_GPIOHS0 && f <= FUNC_GPIOHS31 { - gpioPin := uint8(f - FUNC_GPIOHS0) - val = kendryte.GPIOHS.INPUT_VAL.Get() & (1 << gpioPin) - } - return (val > 0) -} - -// Callbacks to be called for GPIOHS pins configured with SetInterrupt. -var pinCallbacks [32]func(Pin) - -// SetInterrupt sets an interrupt to be executed when a particular pin changes -// state. The pin should already be configured as an input, including a pull up -// or down if no external pull is provided. -// -// You can pass a nil func to unset the pin change interrupt. If you do so, -// the change parameter is ignored and can be set to any value (such as 0). -// If the pin is already configured with a callback, you must first unset -// this pins interrupt before you can set a new callback. -func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error { - - // Check if the pin is a GPIOHS pin. - f := p.FPIOAFunction() - if f < FUNC_GPIOHS0 || f > FUNC_GPIOHS31 { - return ErrInvalidDataPin - } - - gpioPin := uint8(f - FUNC_GPIOHS0) - - // Clear all interrupts. - kendryte.GPIOHS.RISE_IE.ClearBits(1 << gpioPin) - kendryte.GPIOHS.FALL_IE.ClearBits(1 << gpioPin) - kendryte.GPIOHS.HIGH_IE.ClearBits(1 << gpioPin) - kendryte.GPIOHS.LOW_IE.ClearBits(1 << gpioPin) - - // Clear all the pending bits for this pin. - kendryte.GPIOHS.RISE_IP.SetBits(1 << gpioPin) - kendryte.GPIOHS.FALL_IP.SetBits(1 << gpioPin) - kendryte.GPIOHS.HIGH_IP.SetBits(1 << gpioPin) - kendryte.GPIOHS.LOW_IP.SetBits(1 << gpioPin) - - if callback == nil { - if pinCallbacks[gpioPin] != nil { - pinCallbacks[gpioPin] = nil - } - return nil - } - - if pinCallbacks[gpioPin] != nil { - // The pin was already configured. - // To properly re-configure a pin, unset it first and set a new - // configuration. - return ErrNoPinChangeChannel - } - - pinCallbacks[gpioPin] = callback - - // Enable interrupts. - if change&PinRising != 0 { - kendryte.GPIOHS.RISE_IE.SetBits(1 << gpioPin) - } - if change&PinFalling != 0 { - kendryte.GPIOHS.FALL_IE.SetBits(1 << gpioPin) - } - - handleInterrupt := func(inter interrupt.Interrupt) { - - pin := uint8(inter.GetNumber() - kendryte.IRQ_GPIOHS0) - - if kendryte.GPIOHS.RISE_IE.HasBits(1 << pin) { - kendryte.GPIOHS.RISE_IE.ClearBits(1 << pin) - // Acknowledge interrupt atomically. - riscv.AsmFull( - "amoor.w {}, {mask}, ({reg})", - map[string]interface{}{ - "mask": uint32(1 << pin), - "reg": uintptr(unsafe.Pointer(&kendryte.GPIOHS.RISE_IP.Reg)), - }) - kendryte.GPIOHS.RISE_IE.SetBits(1 << pin) - } - - if kendryte.GPIOHS.FALL_IE.HasBits(1 << pin) { - kendryte.GPIOHS.FALL_IE.ClearBits(1 << pin) - // Acknowledge interrupt atomically. - riscv.AsmFull( - "amoor.w {}, {mask}, ({reg})", - map[string]interface{}{ - "mask": uint32(1 << pin), - "reg": uintptr(unsafe.Pointer(&kendryte.GPIOHS.FALL_IP.Reg)), - }) - kendryte.GPIOHS.FALL_IE.SetBits(1 << pin) - } - - pinCallbacks[pin](Pin(pin)) - } - - var ir interrupt.Interrupt - - switch f { - case FUNC_GPIOHS0: - ir = interrupt.New(kendryte.IRQ_GPIOHS0, handleInterrupt) - case FUNC_GPIOHS1: - ir = interrupt.New(kendryte.IRQ_GPIOHS1, handleInterrupt) - case FUNC_GPIOHS2: - ir = interrupt.New(kendryte.IRQ_GPIOHS2, handleInterrupt) - case FUNC_GPIOHS3: - ir = interrupt.New(kendryte.IRQ_GPIOHS3, handleInterrupt) - case FUNC_GPIOHS4: - ir = interrupt.New(kendryte.IRQ_GPIOHS4, handleInterrupt) - case FUNC_GPIOHS5: - ir = interrupt.New(kendryte.IRQ_GPIOHS5, handleInterrupt) - case FUNC_GPIOHS6: - ir = interrupt.New(kendryte.IRQ_GPIOHS6, handleInterrupt) - case FUNC_GPIOHS7: - ir = interrupt.New(kendryte.IRQ_GPIOHS7, handleInterrupt) - case FUNC_GPIOHS8: - ir = interrupt.New(kendryte.IRQ_GPIOHS8, handleInterrupt) - case FUNC_GPIOHS9: - ir = interrupt.New(kendryte.IRQ_GPIOHS9, handleInterrupt) - case FUNC_GPIOHS10: - ir = interrupt.New(kendryte.IRQ_GPIOHS10, handleInterrupt) - case FUNC_GPIOHS11: - ir = interrupt.New(kendryte.IRQ_GPIOHS11, handleInterrupt) - case FUNC_GPIOHS12: - ir = interrupt.New(kendryte.IRQ_GPIOHS12, handleInterrupt) - case FUNC_GPIOHS13: - ir = interrupt.New(kendryte.IRQ_GPIOHS13, handleInterrupt) - case FUNC_GPIOHS14: - ir = interrupt.New(kendryte.IRQ_GPIOHS14, handleInterrupt) - case FUNC_GPIOHS15: - ir = interrupt.New(kendryte.IRQ_GPIOHS15, handleInterrupt) - case FUNC_GPIOHS16: - ir = interrupt.New(kendryte.IRQ_GPIOHS16, handleInterrupt) - case FUNC_GPIOHS17: - ir = interrupt.New(kendryte.IRQ_GPIOHS17, handleInterrupt) - case FUNC_GPIOHS18: - ir = interrupt.New(kendryte.IRQ_GPIOHS18, handleInterrupt) - case FUNC_GPIOHS19: - ir = interrupt.New(kendryte.IRQ_GPIOHS19, handleInterrupt) - case FUNC_GPIOHS20: - ir = interrupt.New(kendryte.IRQ_GPIOHS20, handleInterrupt) - case FUNC_GPIOHS21: - ir = interrupt.New(kendryte.IRQ_GPIOHS21, handleInterrupt) - case FUNC_GPIOHS22: - ir = interrupt.New(kendryte.IRQ_GPIOHS22, handleInterrupt) - case FUNC_GPIOHS23: - ir = interrupt.New(kendryte.IRQ_GPIOHS23, handleInterrupt) - case FUNC_GPIOHS24: - ir = interrupt.New(kendryte.IRQ_GPIOHS24, handleInterrupt) - case FUNC_GPIOHS25: - ir = interrupt.New(kendryte.IRQ_GPIOHS25, handleInterrupt) - case FUNC_GPIOHS26: - ir = interrupt.New(kendryte.IRQ_GPIOHS26, handleInterrupt) - case FUNC_GPIOHS27: - ir = interrupt.New(kendryte.IRQ_GPIOHS27, handleInterrupt) - case FUNC_GPIOHS28: - ir = interrupt.New(kendryte.IRQ_GPIOHS28, handleInterrupt) - case FUNC_GPIOHS29: - ir = interrupt.New(kendryte.IRQ_GPIOHS29, handleInterrupt) - case FUNC_GPIOHS30: - ir = interrupt.New(kendryte.IRQ_GPIOHS30, handleInterrupt) - case FUNC_GPIOHS31: - ir = interrupt.New(kendryte.IRQ_GPIOHS31, handleInterrupt) - } - - ir.SetPriority(5) - ir.Enable() - - return nil - -} - -type UART struct { - Bus *kendryte.UARTHS_Type - Buffer *RingBuffer -} - -var ( - UART0 = &_UART0 - _UART0 = UART{Bus: kendryte.UARTHS, Buffer: NewRingBuffer()} -) - -func (uart *UART) Configure(config UARTConfig) { - - // Use default baudrate if not set. - if config.BaudRate == 0 { - config.BaudRate = 115200 - } - - // Use default pins if not set. - if config.TX == 0 && config.RX == 0 { - config.TX = UART_TX_PIN - config.RX = UART_RX_PIN - } - - config.TX.SetFPIOAFunction(FUNC_UARTHS_TX) - config.RX.SetFPIOAFunction(FUNC_UARTHS_RX) - - div := CPUFrequency()/config.BaudRate - 1 - - uart.Bus.DIV.Set(div) - uart.Bus.TXCTRL.Set(kendryte.UARTHS_TXCTRL_TXEN) - uart.Bus.RXCTRL.Set(kendryte.UARTHS_RXCTRL_RXEN) - - // Enable interrupts on receive. - uart.Bus.IE.Set(kendryte.UARTHS_IE_RXWM) - - intr := interrupt.New(kendryte.IRQ_UARTHS, _UART0.handleInterrupt) - intr.SetPriority(5) - intr.Enable() -} - -func (uart *UART) handleInterrupt(interrupt.Interrupt) { - rxdata := uart.Bus.RXDATA.Get() - c := byte(rxdata) - if uint32(c) != rxdata { - // The rxdata has other bits set than just the low 8 bits. This probably - // means that the 'empty' flag is set, which indicates there is no data - // to be read and the byte is garbage. Ignore this byte. - return - } - uart.Receive(c) -} - -func (uart *UART) writeByte(c byte) error { - for uart.Bus.TXDATA.Get()&kendryte.UARTHS_TXDATA_FULL != 0 { - } - - uart.Bus.TXDATA.Set(uint32(c)) - return nil -} - -func (uart *UART) flush() {} - -type SPI struct { - Bus *kendryte.SPI_Type -} - -// SPIConfig is used to store config info for SPI. -type SPIConfig struct { - Frequency uint32 - SCK Pin - SDO Pin - SDI Pin - LSBFirst bool - Mode uint8 -} - -// Configure is intended to setup the SPI interface. -// Only SPI controller 0 and 1 can be used because SPI2 is a special -// peripheral-mode controller and SPI3 is used for flashing. -func (spi *SPI) Configure(config SPIConfig) error { - // Use default pins if not set. - if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 { - config.SCK = SPI0_SCK_PIN - config.SDO = SPI0_SDO_PIN - config.SDI = SPI0_SDI_PIN - } - - // Enable APB2 clock. - kendryte.SYSCTL.CLK_EN_CENT.SetBits(kendryte.SYSCTL_CLK_EN_CENT_APB2_CLK_EN) - - switch spi.Bus { - case kendryte.SPI0: - // Initialize SPI clock. - kendryte.SYSCTL.CLK_EN_PERI.SetBits(kendryte.SYSCTL_CLK_EN_PERI_SPI0_CLK_EN) - kendryte.SYSCTL.CLK_TH1.ClearBits(kendryte.SYSCTL_CLK_TH1_SPI0_CLK_Msk) - - // Initialize pins. - config.SCK.SetFPIOAFunction(FUNC_SPI0_SCLK) - config.SDO.SetFPIOAFunction(FUNC_SPI0_D0) - config.SDI.SetFPIOAFunction(FUNC_SPI0_D1) - case kendryte.SPI1: - // Initialize SPI clock. - kendryte.SYSCTL.CLK_EN_PERI.SetBits(kendryte.SYSCTL_CLK_EN_PERI_SPI1_CLK_EN) - kendryte.SYSCTL.CLK_TH1.ClearBits(kendryte.SYSCTL_CLK_TH1_SPI1_CLK_Msk) - - // Initialize pins. - config.SCK.SetFPIOAFunction(FUNC_SPI1_SCLK) - config.SDO.SetFPIOAFunction(FUNC_SPI1_D0) - config.SDI.SetFPIOAFunction(FUNC_SPI1_D1) - default: - return errUnsupportedSPIController - } - - // Set default frequency. - if config.Frequency == 0 { - config.Frequency = 4000000 // 4MHz - } - - baudr := CPUFrequency() / config.Frequency - spi.Bus.BAUDR.Set(baudr) - - // Configure SPI mode 0, standard frame format, 8-bit data, little-endian. - spi.Bus.IMR.Set(0) - spi.Bus.DMACR.Set(0) - spi.Bus.DMATDLR.Set(0x10) - spi.Bus.DMARDLR.Set(0) - spi.Bus.SER.Set(0) - spi.Bus.SSIENR.Set(0) - spi.Bus.CTRLR0.Set((7 << 16)) - spi.Bus.SPI_CTRLR0.Set(0) - spi.Bus.ENDIAN.Set(0) - - return nil -} - -// Transfer writes/reads a single byte using the SPI interface. -func (spi *SPI) Transfer(w byte) (byte, error) { - spi.Bus.SSIENR.Set(0) - - // Set transfer-receive mode. - spi.Bus.CTRLR0.ClearBits(0x3 << 8) - - // Enable/disable SPI. - spi.Bus.SSIENR.Set(1) - defer spi.Bus.SSIENR.Set(0) - - // Enable/disable device. - spi.Bus.SER.Set(0x1) - defer spi.Bus.SER.Set(0) - - spi.Bus.DR0.Set(uint32(w)) - - // Wait for transfer. - for spi.Bus.SR.Get()&0x05 != 0x04 { - } - - // Wait for data. - for spi.Bus.RXFLR.Get() == 0 { - } - - return byte(spi.Bus.DR0.Get()), nil -} - -// I2C on the K210. -type I2C struct { - Bus kendryte.I2C_Type -} - -var ( - I2C0 = (*I2C)(unsafe.Pointer(kendryte.I2C0)) - I2C1 = (*I2C)(unsafe.Pointer(kendryte.I2C1)) - I2C2 = (*I2C)(unsafe.Pointer(kendryte.I2C2)) -) - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 - SCL Pin - SDA Pin -} - -// Configure is intended to setup the I2C interface. -func (i2c *I2C) Configure(config I2CConfig) error { - - if config.Frequency == 0 { - config.Frequency = 100 * KHz - } - - if config.SDA == 0 && config.SCL == 0 { - config.SDA = I2C0_SDA_PIN - config.SCL = I2C0_SCL_PIN - } - - // Enable APB0 clock. - kendryte.SYSCTL.CLK_EN_CENT.SetBits(kendryte.SYSCTL_CLK_EN_CENT_APB0_CLK_EN) - - switch &i2c.Bus { - case kendryte.I2C0: - // Initialize I2C0 clock. - kendryte.SYSCTL.CLK_EN_PERI.SetBits(kendryte.SYSCTL_CLK_EN_PERI_I2C0_CLK_EN) - kendryte.SYSCTL.CLK_TH5.ReplaceBits(0x03, kendryte.SYSCTL_CLK_TH5_I2C0_CLK_Msk, kendryte.SYSCTL_CLK_TH5_I2C0_CLK_Pos) - - // Initialize pins. - config.SDA.SetFPIOAFunction(FUNC_I2C0_SDA) - config.SCL.SetFPIOAFunction(FUNC_I2C0_SCLK) - case kendryte.I2C1: - // Initialize I2C1 clock. - kendryte.SYSCTL.CLK_EN_PERI.SetBits(kendryte.SYSCTL_CLK_EN_PERI_I2C1_CLK_EN) - kendryte.SYSCTL.CLK_TH5.ReplaceBits(0x03, kendryte.SYSCTL_CLK_TH5_I2C1_CLK_Msk, kendryte.SYSCTL_CLK_TH5_I2C1_CLK_Pos) - - // Initialize pins. - config.SDA.SetFPIOAFunction(FUNC_I2C1_SDA) - config.SCL.SetFPIOAFunction(FUNC_I2C1_SCLK) - case kendryte.I2C2: - // Initialize I2C2 clock. - kendryte.SYSCTL.CLK_EN_PERI.SetBits(kendryte.SYSCTL_CLK_EN_PERI_I2C2_CLK_EN) - kendryte.SYSCTL.CLK_TH5.ReplaceBits(0x03, kendryte.SYSCTL_CLK_TH5_I2C2_CLK_Msk, kendryte.SYSCTL_CLK_TH5_I2C2_CLK_Pos) - - // Initialize pins. - config.SDA.SetFPIOAFunction(FUNC_I2C2_SDA) - config.SCL.SetFPIOAFunction(FUNC_I2C2_SCLK) - } - - i2c.SetBaudRate(config.Frequency) - - i2c.Bus.INTR_MASK.Set(0) - i2c.Bus.DMA_CR.Set(0x03) - i2c.Bus.DMA_RDLR.Set(0) - i2c.Bus.DMA_TDLR.Set(0x4) - - return nil -} - -// SetBaudRate sets the communication speed for I2C. -func (i2c *I2C) SetBaudRate(br uint32) error { - div := CPUFrequency() / br / 16 - - // Disable controller before setting the prescale register. - i2c.Bus.ENABLE.Set(0) - - i2c.Bus.CON.Set(0x63) - - // Set prescaler registers. - i2c.Bus.SS_SCL_HCNT.Set(uint32(div)) - i2c.Bus.SS_SCL_LCNT.Set(uint32(div)) - - return nil -} - -// Tx does a single I2C transaction at the specified address. -// It clocks out the given address, writes the bytes in w, reads back len(r) -// bytes and stores them in r, and generates a stop condition on the bus. -func (i2c *I2C) Tx(addr uint16, w, r []byte) error { - // Set peripheral address. - i2c.Bus.TAR.Set(uint32(addr)) - // Enable controller. - i2c.Bus.ENABLE.Set(1) - - if len(w) != 0 { - i2c.Bus.CLR_TX_ABRT.Set(i2c.Bus.CLR_TX_ABRT.Get()) - dataLen := uint32(len(w)) - di := 0 - - for dataLen != 0 { - fifoLen := 8 - i2c.Bus.TXFLR.Get() - if dataLen < fifoLen { - fifoLen = dataLen - } - - for i := uint32(0); i < fifoLen; i++ { - i2c.Bus.DATA_CMD.Set(uint32(w[di])) - di += 1 - } - if i2c.Bus.TX_ABRT_SOURCE.Get() != 0 { - return errI2CTxAbort - } - dataLen -= fifoLen - } - - // Wait for transmission to complete. - for i2c.Bus.STATUS.HasBits(kendryte.I2C_STATUS_ACTIVITY) || !i2c.Bus.STATUS.HasBits(kendryte.I2C_STATUS_TFE) { - } - - if i2c.Bus.TX_ABRT_SOURCE.Get() != 0 { - return errI2CTxAbort - } - } - if len(r) != 0 { - dataLen := uint32(len(r)) - cmdLen := uint32(len(r)) - di := 0 - - for dataLen != 0 || cmdLen != 0 { - fifoLen := i2c.Bus.RXFLR.Get() - if dataLen < fifoLen { - fifoLen = dataLen - } - for i := uint32(0); i < fifoLen; i++ { - r[di] = byte(i2c.Bus.DATA_CMD.Get()) - di += 1 - } - dataLen -= fifoLen - - fifoLen = 8 - i2c.Bus.TXFLR.Get() - if cmdLen < fifoLen { - fifoLen = cmdLen - } - for i := uint32(0); i < fifoLen; i++ { - i2c.Bus.DATA_CMD.Set(0x100) - } - if i2c.Bus.TX_ABRT_SOURCE.Get() != 0 { - return errI2CTxAbort - } - cmdLen -= fifoLen - } - } - - return nil -} diff --git a/emb/machine/machine_mimxrt1062.go b/emb/machine/machine_mimxrt1062.go deleted file mode 100644 index 74d01c7..0000000 --- a/emb/machine/machine_mimxrt1062.go +++ /dev/null @@ -1,1064 +0,0 @@ -//go:build mimxrt1062 - -package machine - -import ( - "device/nxp" - "math/bits" - "runtime/interrupt" - "runtime/volatile" -) - -// Peripheral abstraction layer for the MIMXRT1062 - -const deviceName = nxp.Device - -func CPUFrequency() uint32 { - return 600000000 -} - -const ( - // GPIO - PinInput PinMode = iota - PinInputPullup - PinInputPulldown - PinOutput - PinOutputOpenDrain - PinDisable - - // ADC - PinInputAnalog - - // UART - PinModeUARTTX - PinModeUARTRX - - // SPI - PinModeSPISDI - PinModeSPISDO - PinModeSPICLK - PinModeSPICS - - // I2C - PinModeI2CSDA - PinModeI2CSCL -) - -// Deprecated: use PinInputPullup and PinInputPulldown instead. -const ( - PinInputPullUp = PinInputPullup - PinInputPullDown = PinInputPulldown -) - -type PinChange uint8 - -const ( - PinRising PinChange = iota + 2 - PinFalling - PinToggle -) - -// pinJumpTable represents a function lookup table for all 128 GPIO pins. -// -// There are 4 GPIO ports (A-D) and 32 pins (0-31) on each port. The uint8 value -// of a Pin is used as table index. The number of pins with a defined (non-nil) -// function is recorded in the uint8 field numDefined. -type pinJumpTable struct { - lut [4 * 32]func(Pin) - numDefined uint8 -} - -// pinISR stores the interrupt callbacks for GPIO pins, and pinInterrupt holds -// an interrupt service routine that dispatches the interrupt callbacks. -var ( - pinISR pinJumpTable - pinInterrupt *interrupt.Interrupt -) - -// From the i.MXRT1062 Processor Reference Manual (Chapter 12 - GPIO): -// -// | High-speed GPIOs exist in this device: -// | - GPIO1-5 are standard-speed GPIOs that run off the IPG_CLK_ROOT, while -// | GPIO6-9 are high-speed GPIOs that run at the AHB_CLK_ROOT frequency. -// | See the table "System Clocks, Gating, and Override" in CCM chapter. -// | - Regular GPIO and high speed GPIO are paired (GPIO1 and GPIO6 share the -// | same pins, GPIO2 and GPIO7 share, etc). The IOMUXC_GPR_GPR26-29 -// | registers are used to determine if the regular or high-speed GPIO -// | module is used for the GPIO pins on a given port. -// -// Therefore, we do not even use GPIO1-5 and instead use their high-speed -// partner for all pins. This is configured at startup in the runtime package -// (func initPins() in `runtime_mimxrt1062.go`). -// We cannot declare 32 pins for all available ports (GPIO1-9) anyway, since Pin -// is only uint8, and 9*32=288 > 256, so something has to be sacrificed. - -const ( - portA Pin = iota * 32 // GPIO1(6) - portB // GPIO2(7) - portC // GPIO3(8) - portD // GPIO4(9) -) - -const ( - // [Pad]: Alt Func 0 Alt Func 1 Alt Func 2 Alt Func 3 Alt Func 4 Alt Func 5 Alt Func 6 Alt Func 7 Alt Func 8 Alt Func 9 - // ---------- --------------- --------------- ------------------- -------------------- -------------------- ----------- -------------------- -------------------- --------------------- ---------------- - PA0 = portA + 0 // [AD_B0_00]: FLEXPWM2_PWMA03 XBAR1_INOUT14 REF_CLK_32K USB_OTG2_ID LPI2C1_SCLS GPIO1_IO00 USDHC1_RESET_B LPSPI3_SCK ~ ~ - PA1 = portA + 1 // [AD_B0_01]: FLEXPWM2_PWMB03 XBAR1_INOUT15 REF_CLK_24M USB_OTG1_ID LPI2C1_SDAS GPIO1_IO01 EWM_OUT_B LPSPI3_SDO ~ ~ - PA2 = portA + 2 // [AD_B0_02]: FLEXCAN2_TX XBAR1_INOUT16 LPUART6_TX USB_OTG1_PWR FLEXPWM1_PWMX00 GPIO1_IO02 LPI2C1_HREQ LPSPI3_SDI ~ ~ - PA3 = portA + 3 // [AD_B0_03]: FLEXCAN2_RX XBAR1_INOUT17 LPUART6_RX USB_OTG1_OC FLEXPWM1_PWMX01 GPIO1_IO03 REF_CLK_24M LPSPI3_PCS0 ~ ~ - PA4 = portA + 4 // [AD_B0_04]: SRC_BOOT_MODE00 MQS_RIGHT ENET_TX_DATA03 SAI2_TX_SYNC CSI_DATA09 GPIO1_IO04 PIT_TRIGGER00 LPSPI3_PCS1 ~ ~ - PA5 = portA + 5 // [AD_B0_05]: SRC_BOOT_MODE01 MQS_LEFT ENET_TX_DATA02 SAI2_TX_BCLK CSI_DATA08 GPIO1_IO05 XBAR1_INOUT17 LPSPI3_PCS2 ~ ~ - PA6 = portA + 6 // [AD_B0_06]: JTAG_TMS GPT2_COMPARE1 ENET_RX_CLK SAI2_RX_BCLK CSI_DATA07 GPIO1_IO06 XBAR1_INOUT18 LPSPI3_PCS3 ~ ~ - PA7 = portA + 7 // [AD_B0_07]: JTAG_TCK GPT2_COMPARE2 ENET_TX_ER SAI2_RX_SYNC CSI_DATA06 GPIO1_IO07 XBAR1_INOUT19 ENET_1588_EVENT3_OUT ~ ~ - PA8 = portA + 8 // [AD_B0_08]: JTAG_MOD GPT2_COMPARE3 ENET_RX_DATA03 SAI2_RX_DATA CSI_DATA05 GPIO1_IO08 XBAR1_IN20 ENET_1588_EVENT3_IN ~ ~ - PA9 = portA + 9 // [AD_B0_09]: JTAG_TDI FLEXPWM2_PWMA03 ENET_RX_DATA02 SAI2_TX_DATA CSI_DATA04 GPIO1_IO09 XBAR1_IN21 GPT2_CLK SEMC_DQS4 ~ - PA10 = portA + 10 // [AD_B0_10]: JTAG_TDO FLEXPWM1_PWMA03 ENET_CRS SAI2_MCLK CSI_DATA03 GPIO1_IO10 XBAR1_IN22 ENET_1588_EVENT0_OUT FLEXCAN3_TX ARM_TRACE_SWO - PA11 = portA + 11 // [AD_B0_11]: JTAG_TRSTB FLEXPWM1_PWMB03 ENET_COL WDOG1_WDOG_B CSI_DATA02 GPIO1_IO11 XBAR1_IN23 ENET_1588_EVENT0_IN FLEXCAN3_RX SEMC_CLK6 - PA12 = portA + 12 // [AD_B0_12]: LPI2C4_SCL CCM_PMIC_READY LPUART1_TX WDOG2_WDOG_B FLEXPWM1_PWMX02 GPIO1_IO12 ENET_1588_EVENT1_OUT NMI_GLUE_NMI ~ ~ - PA13 = portA + 13 // [AD_B0_13]: LPI2C4_SDA GPT1_CLK LPUART1_RX EWM_OUT_B FLEXPWM1_PWMX03 GPIO1_IO13 ENET_1588_EVENT1_IN REF_CLK_24M ~ ~ - PA14 = portA + 14 // [AD_B0_14]: USB_OTG2_OC XBAR1_IN24 LPUART1_CTS_B ENET_1588_EVENT0_OUT CSI_VSYNC GPIO1_IO14 FLEXCAN2_TX FLEXCAN3_TX ~ ~ - PA15 = portA + 15 // [AD_B0_15]: USB_OTG2_PWR XBAR1_IN25 LPUART1_RTS_B ENET_1588_EVENT0_IN CSI_HSYNC GPIO1_IO15 FLEXCAN2_RX WDOG1_WDOG_RST_B_DEB FLEXCAN3_RX ~ - PA16 = portA + 16 // [AD_B1_00]: USB_OTG2_ID QTIMER3_TIMER0 LPUART2_CTS_B LPI2C1_SCL WDOG1_B GPIO1_IO16 USDHC1_WP KPP_ROW07 ENET2_1588_EVENT0_OUT FLEXIO3_FLEXIO00 - PA17 = portA + 17 // [AD_B1_01]: USB_OTG1_PWR QTIMER3_TIMER1 LPUART2_RTS_B LPI2C1_SDA CCM_PMIC_READY GPIO1_IO17 USDHC1_VSELECT KPP_COL07 ENET2_1588_EVENT0_IN FLEXIO3_FLEXIO01 - PA18 = portA + 18 // [AD_B1_02]: USB_OTG1_ID QTIMER3_TIMER2 LPUART2_TX SPDIF_OUT ENET_1588_EVENT2_OUT GPIO1_IO18 USDHC1_CD_B KPP_ROW06 GPT2_CLK FLEXIO3_FLEXIO02 - PA19 = portA + 19 // [AD_B1_03]: USB_OTG1_OC QTIMER3_TIMER3 LPUART2_RX SPDIF_IN ENET_1588_EVENT2_IN GPIO1_IO19 USDHC2_CD_B KPP_COL06 GPT2_CAPTURE1 FLEXIO3_FLEXIO03 - PA20 = portA + 20 // [AD_B1_04]: FLEXSPIB_DATA03 ENET_MDC LPUART3_CTS_B SPDIF_SR_CLK CSI_PIXCLK GPIO1_IO20 USDHC2_DATA0 KPP_ROW05 GPT2_CAPTURE2 FLEXIO3_FLEXIO04 - PA21 = portA + 21 // [AD_B1_05]: FLEXSPIB_DATA02 ENET_MDIO LPUART3_RTS_B SPDIF_OUT CSI_MCLK GPIO1_IO21 USDHC2_DATA1 KPP_COL05 GPT2_COMPARE1 FLEXIO3_FLEXIO05 - PA22 = portA + 22 // [AD_B1_06]: FLEXSPIB_DATA01 LPI2C3_SDA LPUART3_TX SPDIF_LOCK CSI_VSYNC GPIO1_IO22 USDHC2_DATA2 KPP_ROW04 GPT2_COMPARE2 FLEXIO3_FLEXIO06 - PA23 = portA + 23 // [AD_B1_07]: FLEXSPIB_DATA00 LPI2C3_SCL LPUART3_RX SPDIF_EXT_CLK CSI_HSYNC GPIO1_IO23 USDHC2_DATA3 KPP_COL04 GPT2_COMPARE3 FLEXIO3_FLEXIO07 - PA24 = portA + 24 // [AD_B1_08]: FLEXSPIA_SS1_B FLEXPWM4_PWMA00 FLEXCAN1_TX CCM_PMIC_READY CSI_DATA09 GPIO1_IO24 USDHC2_CMD KPP_ROW03 FLEXIO3_FLEXIO08 ~ - PA25 = portA + 25 // [AD_B1_09]: FLEXSPIA_DQS FLEXPWM4_PWMA01 FLEXCAN1_RX SAI1_MCLK CSI_DATA08 GPIO1_IO25 USDHC2_CLK KPP_COL03 FLEXIO3_FLEXIO09 ~ - PA26 = portA + 26 // [AD_B1_10]: FLEXSPIA_DATA03 WDOG1_B LPUART8_TX SAI1_RX_SYNC CSI_DATA07 GPIO1_IO26 USDHC2_WP KPP_ROW02 ENET2_1588_EVENT1_OUT FLEXIO3_FLEXIO10 - PA27 = portA + 27 // [AD_B1_11]: FLEXSPIA_DATA02 EWM_OUT_B LPUART8_RX SAI1_RX_BCLK CSI_DATA06 GPIO1_IO27 USDHC2_RESET_B KPP_COL02 ENET2_1588_EVENT1_IN FLEXIO3_FLEXIO11 - PA28 = portA + 28 // [AD_B1_12]: FLEXSPIA_DATA01 ACMP_OUT00 LPSPI3_PCS0 SAI1_RX_DATA00 CSI_DATA05 GPIO1_IO28 USDHC2_DATA4 KPP_ROW01 ENET2_1588_EVENT2_OUT FLEXIO3_FLEXIO12 - PA29 = portA + 29 // [AD_B1_13]: FLEXSPIA_DATA00 ACMP_OUT01 LPSPI3_SDI SAI1_TX_DATA00 CSI_DATA04 GPIO1_IO29 USDHC2_DATA5 KPP_COL01 ENET2_1588_EVENT2_IN FLEXIO3_FLEXIO13 - PA30 = portA + 30 // [AD_B1_14]: FLEXSPIA_SCLK ACMP_OUT02 LPSPI3_SDO SAI1_TX_BCLK CSI_DATA03 GPIO1_IO30 USDHC2_DATA6 KPP_ROW00 ENET2_1588_EVENT3_OUT FLEXIO3_FLEXIO14 - PA31 = portA + 31 // [AD_B1_15]: FLEXSPIA_SS0_B ACMP_OUT03 LPSPI3_SCK SAI1_TX_SYNC CSI_DATA02 GPIO1_IO31 USDHC2_DATA7 KPP_COL00 ENET2_1588_EVENT3_IN FLEXIO3_FLEXIO15 - - PB0 = portB + 0 // [B0_00]: LCD_CLK QTIMER1_TIMER0 MQS_RIGHT LPSPI4_PCS0 FLEXIO2_FLEXIO00 GPIO2_IO00 SEMC_CSX01 ENET2_MDC ~ ~ - PB1 = portB + 1 // [B0_01]: LCD_ENABLE QTIMER1_TIMER1 MQS_LEFT LPSPI4_SDI FLEXIO2_FLEXIO01 GPIO2_IO01 SEMC_CSX02 ENET2_MDIO ~ ~ - PB2 = portB + 2 // [B0_02]: LCD_HSYNC QTIMER1_TIMER2 FLEXCAN1_TX LPSPI4_SDO FLEXIO2_FLEXIO02 GPIO2_IO02 SEMC_CSX03 ENET2_1588_EVENT0_OUT ~ ~ - PB3 = portB + 3 // [B0_03]: LCD_VSYNC QTIMER2_TIMER0 FLEXCAN1_RX LPSPI4_SCK FLEXIO2_FLEXIO03 GPIO2_IO03 WDOG2_RESET_B_DEB ENET2_1588_EVENT0_IN ~ ~ - PB4 = portB + 4 // [B0_04]: LCD_DATA00 QTIMER2_TIMER1 LPI2C2_SCL ARM_TRACE0 FLEXIO2_FLEXIO04 GPIO2_IO04 SRC_BOOT_CFG00 ENET2_TDATA03 ~ ~ - PB5 = portB + 5 // [B0_05]: LCD_DATA01 QTIMER2_TIMER2 LPI2C2_SDA ARM_TRACE1 FLEXIO2_FLEXIO05 GPIO2_IO05 SRC_BOOT_CFG01 ENET2_TDATA02 ~ ~ - PB6 = portB + 6 // [B0_06]: LCD_DATA02 QTIMER3_TIMER0 FLEXPWM2_PWMA00 ARM_TRACE2 FLEXIO2_FLEXIO06 GPIO2_IO06 SRC_BOOT_CFG02 ENET2_RX_CLK ~ ~ - PB7 = portB + 7 // [B0_07]: LCD_DATA03 QTIMER3_TIMER1 FLEXPWM2_PWMB00 ARM_TRACE3 FLEXIO2_FLEXIO07 GPIO2_IO07 SRC_BOOT_CFG03 ENET2_TX_ER ~ ~ - PB8 = portB + 8 // [B0_08]: LCD_DATA04 QTIMER3_TIMER2 FLEXPWM2_PWMA01 LPUART3_TX FLEXIO2_FLEXIO08 GPIO2_IO08 SRC_BOOT_CFG04 ENET2_RDATA03 ~ ~ - PB9 = portB + 9 // [B0_09]: LCD_DATA05 QTIMER4_TIMER0 FLEXPWM2_PWMB01 LPUART3_RX FLEXIO2_FLEXIO09 GPIO2_IO09 SRC_BOOT_CFG05 ENET2_RDATA02 ~ ~ - PB10 = portB + 10 // [B0_10]: LCD_DATA06 QTIMER4_TIMER1 FLEXPWM2_PWMA02 SAI1_TX_DATA03 FLEXIO2_FLEXIO10 GPIO2_IO10 SRC_BOOT_CFG06 ENET2_CRS ~ ~ - PB11 = portB + 11 // [B0_11]: LCD_DATA07 QTIMER4_TIMER2 FLEXPWM2_PWMB02 SAI1_TX_DATA02 FLEXIO2_FLEXIO11 GPIO2_IO11 SRC_BOOT_CFG07 ENET2_COL ~ ~ - PB12 = portB + 12 // [B0_12]: LCD_DATA08 XBAR1_INOUT10 ARM_TRACE_CLK SAI1_TX_DATA01 FLEXIO2_FLEXIO12 GPIO2_IO12 SRC_BOOT_CFG08 ENET2_TDATA00 ~ ~ - PB13 = portB + 13 // [B0_13]: LCD_DATA09 XBAR1_INOUT11 ARM_TRACE_SWO SAI1_MCLK FLEXIO2_FLEXIO13 GPIO2_IO13 SRC_BOOT_CFG09 ENET2_TDATA01 ~ ~ - PB14 = portB + 14 // [B0_14]: LCD_DATA10 XBAR1_INOUT12 ARM_TXEV SAI1_RX_SYNC FLEXIO2_FLEXIO14 GPIO2_IO14 SRC_BOOT_CFG10 ENET2_TX_EN ~ ~ - PB15 = portB + 15 // [B0_15]: LCD_DATA11 XBAR1_INOUT13 ARM_RXEV SAI1_RX_BCLK FLEXIO2_FLEXIO15 GPIO2_IO15 SRC_BOOT_CFG11 ENET2_TX_CLK ENET2_REF_CLK2 ~ - PB16 = portB + 16 // [B1_00]: LCD_DATA12 XBAR1_INOUT14 LPUART4_TX SAI1_RX_DATA00 FLEXIO2_FLEXIO16 GPIO2_IO16 FLEXPWM1_PWMA03 ENET2_RX_ER FLEXIO3_FLEXIO16 ~ - PB17 = portB + 17 // [B1_01]: LCD_DATA13 XBAR1_INOUT15 LPUART4_RX SAI1_TX_DATA00 FLEXIO2_FLEXIO17 GPIO2_IO17 FLEXPWM1_PWMB03 ENET2_RDATA00 FLEXIO3_FLEXIO17 ~ - PB18 = portB + 18 // [B1_02]: LCD_DATA14 XBAR1_INOUT16 LPSPI4_PCS2 SAI1_TX_BCLK FLEXIO2_FLEXIO18 GPIO2_IO18 FLEXPWM2_PWMA03 ENET2_RDATA01 FLEXIO3_FLEXIO18 ~ - PB19 = portB + 19 // [B1_03]: LCD_DATA15 XBAR1_INOUT17 LPSPI4_PCS1 SAI1_TX_SYNC FLEXIO2_FLEXIO19 GPIO2_IO19 FLEXPWM2_PWMB03 ENET2_RX_EN FLEXIO3_FLEXIO19 ~ - PB20 = portB + 20 // [B1_04]: LCD_DATA16 LPSPI4_PCS0 CSI_DATA15 ENET_RX_DATA00 FLEXIO2_FLEXIO20 GPIO2_IO20 GPT1_CLK FLEXIO3_FLEXIO20 ~ ~ - PB21 = portB + 21 // [B1_05]: LCD_DATA17 LPSPI4_SDI CSI_DATA14 ENET_RX_DATA01 FLEXIO2_FLEXIO21 GPIO2_IO21 GPT1_CAPTURE1 FLEXIO3_FLEXIO21 ~ ~ - PB22 = portB + 22 // [B1_06]: LCD_DATA18 LPSPI4_SDO CSI_DATA13 ENET_RX_EN FLEXIO2_FLEXIO22 GPIO2_IO22 GPT1_CAPTURE2 FLEXIO3_FLEXIO22 ~ ~ - PB23 = portB + 23 // [B1_07]: LCD_DATA19 LPSPI4_SCK CSI_DATA12 ENET_TX_DATA00 FLEXIO2_FLEXIO23 GPIO2_IO23 GPT1_COMPARE1 FLEXIO3_FLEXIO23 ~ ~ - PB24 = portB + 24 // [B1_08]: LCD_DATA20 QTIMER1_TIMER3 CSI_DATA11 ENET_TX_DATA01 FLEXIO2_FLEXIO24 GPIO2_IO24 FLEXCAN2_TX GPT1_COMPARE2 FLEXIO3_FLEXIO24 ~ - PB25 = portB + 25 // [B1_09]: LCD_DATA21 QTIMER2_TIMER3 CSI_DATA10 ENET_TX_EN FLEXIO2_FLEXIO25 GPIO2_IO25 FLEXCAN2_RX GPT1_COMPARE3 FLEXIO3_FLEXIO25 ~ - PB26 = portB + 26 // [B1_10]: LCD_DATA22 QTIMER3_TIMER3 CSI_DATA00 ENET_TX_CLK FLEXIO2_FLEXIO26 GPIO2_IO26 ENET_REF_CLK FLEXIO3_FLEXIO26 ~ ~ - PB27 = portB + 27 // [B1_11]: LCD_DATA23 QTIMER4_TIMER3 CSI_DATA01 ENET_RX_ER FLEXIO2_FLEXIO27 GPIO2_IO27 LPSPI4_PCS3 FLEXIO3_FLEXIO27 ~ ~ - PB28 = portB + 28 // [B1_12]: LPUART5_TX CSI_PIXCLK ENET_1588_EVENT0_IN FLEXIO2_FLEXIO28 GPIO2_IO28 USDHC1_CD_B FLEXIO3_FLEXIO28 ~ ~ ~ - PB29 = portB + 29 // [B1_13]: WDOG1_B LPUART5_RX CSI_VSYNC ENET_1588_EVENT0_OUT FLEXIO2_FLEXIO29 GPIO2_IO29 USDHC1_WP SEMC_DQS4 FLEXIO3_FLEXIO29 ~ - PB30 = portB + 30 // [B1_14]: ENET_MDC FLEXPWM4_PWMA02 CSI_HSYNC XBAR1_IN02 FLEXIO2_FLEXIO30 GPIO2_IO30 USDHC1_VSELECT ENET2_TDATA00 FLEXIO3_FLEXIO30 ~ - PB31 = portB + 31 // [B1_15]: ENET_MDIO FLEXPWM4_PWMA03 CSI_MCLK XBAR1_IN03 FLEXIO2_FLEXIO31 GPIO2_IO31 USDHC1_RESET_B ENET2_TDATA01 FLEXIO3_FLEXIO31 ~ - - PC0 = portC + 0 // [SD_B1_00]: USDHC2_DATA3 FLEXSPIB_DATA03 FLEXPWM1_PWMA03 SAI1_TX_DATA03 LPUART4_TX GPIO3_IO00 SAI3_RX_DATA ~ ~ ~ - PC1 = portC + 1 // [SD_B1_01]: USDHC2_DATA2 FLEXSPIB_DATA02 FLEXPWM1_PWMB03 SAI1_TX_DATA02 LPUART4_RX GPIO3_IO01 SAI3_TX_DATA ~ ~ ~ - PC2 = portC + 2 // [SD_B1_02]: USDHC2_DATA1 FLEXSPIB_DATA01 FLEXPWM2_PWMA03 SAI1_TX_DATA01 FLEXCAN1_TX GPIO3_IO02 CCM_WAIT SAI3_TX_SYNC ~ ~ - PC3 = portC + 3 // [SD_B1_03]: USDHC2_DATA0 FLEXSPIB_DATA00 FLEXPWM2_PWMB03 SAI1_MCLK FLEXCAN1_RX GPIO3_IO03 CCM_PMIC_READY SAI3_TX_BCLK ~ ~ - PC4 = portC + 4 // [SD_B1_04]: USDHC2_CLK FLEXSPIB_SCLK LPI2C1_SCL SAI1_RX_SYNC FLEXSPIA_SS1_B GPIO3_IO04 CCM_STOP SAI3_MCLK ~ ~ - PC5 = portC + 5 // [SD_B1_05]: USDHC2_CMD FLEXSPIA_DQS LPI2C1_SDA SAI1_RX_BCLK FLEXSPIB_SS0_B GPIO3_IO05 SAI3_RX_SYNC ~ ~ ~ - PC6 = portC + 6 // [SD_B1_06]: USDHC2_RESET_B FLEXSPIA_SS0_B LPUART7_CTS_B SAI1_RX_DATA00 LPSPI2_PCS0 GPIO3_IO06 SAI3_RX_BCLK ~ ~ ~ - PC7 = portC + 7 // [SD_B1_07]: SEMC_CSX01 FLEXSPIA_SCLK LPUART7_RTS_B SAI1_TX_DATA00 LPSPI2_SCK GPIO3_IO07 ~ ~ ~ ~ - PC8 = portC + 8 // [SD_B1_08]: USDHC2_DATA4 FLEXSPIA_DATA00 LPUART7_TX SAI1_TX_BCLK LPSPI2_SD0 GPIO3_IO08 SEMC_CSX02 ~ ~ ~ - PC9 = portC + 9 // [SD_B1_09]: USDHC2_DATA5 FLEXSPIA_DATA01 LPUART7_RX SAI1_TX_SYNC LPSPI2_SDI GPIO3_IO09 ~ ~ ~ ~ - PC10 = portC + 10 // [SD_B1_10]: USDHC2_DATA6 FLEXSPIA_DATA02 LPUART2_RX LPI2C2_SDA LPSPI2_PCS2 GPIO3_IO10 ~ ~ ~ ~ - PC11 = portC + 11 // [SD_B1_11]: USDHC2_DATA7 FLEXSPIA_DATA03 LPUART2_TX LPI2C2_SCL LPSPI2_PCS3 GPIO3_IO11 ~ ~ ~ ~ - PC12 = portC + 12 // [SD_B0_00]: USDHC1_CMD FLEXPWM1_PWMA00 LPI2C3_SCL XBAR1_INOUT04 LPSPI1_SCK GPIO3_IO12 FLEXSPIA_SS1_B ENET2_TX_EN SEMC_DQS4 ~ - PC13 = portC + 13 // [SD_B0_01]: USDHC1_CLK FLEXPWM1_PWMB00 LPI2C3_SDA XBAR1_INOUT05 LPSPI1_PCS0 GPIO3_IO13 FLEXSPIB_SS1_B ENET2_TX_CLK ENET2_REF_CLK2 ~ - PC14 = portC + 14 // [SD_B0_02]: USDHC1_DATA0 FLEXPWM1_PWMA01 LPUART8_CTS_B XBAR1_INOUT06 LPSPI1_SDO GPIO3_IO14 ENET2_RX_ER SEMC_CLK5 ~ ~ - PC15 = portC + 15 // [SD_B0_03]: USDHC1_DATA1 FLEXPWM1_PWMB01 LPUART8_RTS_B XBAR1_INOUT07 LPSPI1_SDI GPIO3_IO15 ENET2_RDATA00 SEMC_CLK6 ~ ~ - PC16 = portC + 16 // [SD_B0_04]: USDHC1_DATA2 FLEXPWM1_PWMA02 LPUART8_TX XBAR1_INOUT08 FLEXSPIB_SS0_B GPIO3_IO16 CCM_CLKO1 ENET2_RDATA01 ~ ~ - PC17 = portC + 17 // [SD_B0_05]: USDHC1_DATA3 FLEXPWM1_PWMB02 LPUART8_RX XBAR1_INOUT09 FLEXSPIB_DQS GPIO3_IO17 CCM_CLKO2 ENET2_RX_EN ~ ~ - PC18 = portC + 18 // [EMC_32]: SEMC_DATA10 FLEXPWM3_PWMB01 LPUART7_RX CCM_PMIC_RDY CSI_DATA21 GPIO3_IO18 ENET2_TX_EN ~ ~ ~ - PC19 = portC + 19 // [EMC_33]: SEMC_DATA11 FLEXPWM3_PWMA02 USDHC1_RESET_B SAI3_RX_DATA CSI_DATA20 GPIO3_IO19 ENET2_TX_CLK ENET2_REF_CLK2 ~ ~ - PC20 = portC + 20 // [EMC_34]: SEMC_DATA12 FLEXPWM3_PWMB02 USDHC1_VSELECT SAI3_RX_SYNC CSI_DATA19 GPIO3_IO20 ENET2_RX_ER ~ ~ ~ - PC21 = portC + 21 // [EMC_35]: SEMC_DATA13 XBAR1_INOUT18 GPT1_COMPARE1 SAI3_RX_BCLK CSI_DATA18 GPIO3_IO21 USDHC1_CD_B ENET2_RDATA00 ~ ~ - PC22 = portC + 22 // [EMC_36]: SEMC_DATA14 XBAR1_IN22 GPT1_COMPARE2 SAI3_TX_DATA CSI_DATA17 GPIO3_IO22 USDHC1_WP ENET2_RDATA01 FLEXCAN3_TX ~ - PC23 = portC + 23 // [EMC_37]: SEMC_DATA15 XBAR1_IN23 GPT1_COMPARE3 SAI3_MCLK CSI_DATA16 GPIO3_IO23 USDHC2_WP ENET2_RX_EN FLEXCAN3_RX ~ - PC24 = portC + 24 // [EMC_38]: SEMC_DM01 FLEXPWM1_PWMA03 LPUART8_TX SAI3_TX_BCLK CSI_FIELD GPIO3_IO24 USDHC2_VSELECT ENET2_MDC ~ ~ - PC25 = portC + 25 // [EMC_39]: SEMC_DQS FLEXPWM1_PWMB03 LPUART8_RX SAI3_TX_SYNC WDOG1_WDOG_B GPIO3_IO25 USDHC2_CD_B ENET2_MDIO SEMC_DQS4 ~ - PC26 = portC + 26 // [EMC_40]: SEMC_RDY GPT2_CAPTURE2 LPSPI1_PCS2 USB_OTG2_OC ENET_MDC GPIO3_IO26 USDHC2_RESET_B SEMC_CLK5 ~ ~ - PC27 = portC + 27 // [EMC_41]: SEMC_CSX00 GPT2_CAPTURE1 LPSPI1_PCS3 USB_OTG2_PWR ENET_MDIO GPIO3_IO27 USDHC1_VSELECT ~ ~ ~ - _ = portC + 28 // - _ = portC + 29 // - _ = portC + 30 // - _ = portC + 31 // - - PD0 = portD + 0 // [EMC_00]: SEMC_DATA00 FLEXPWM4_PWMA00 LPSPI2_SCK XBAR1_XBAR_IN02 FLEXIO1_FLEXIO00 GPIO4_IO00 ~ ~ ~ ~ - PD1 = portD + 1 // [EMC_01]: SEMC_DATA01 FLEXPWM4_PWMB00 LPSPI2_PCS0 XBAR1_IN03 FLEXIO1_FLEXIO01 GPIO4_IO01 ~ ~ ~ ~ - PD2 = portD + 2 // [EMC_02]: SEMC_DATA02 FLEXPWM4_PWMA01 LPSPI2_SDO XBAR1_INOUT04 FLEXIO1_FLEXIO02 GPIO4_IO02 ~ ~ ~ ~ - PD3 = portD + 3 // [EMC_03]: SEMC_DATA03 FLEXPWM4_PWMB01 LPSPI2_SDI XBAR1_INOUT05 FLEXIO1_FLEXIO03 GPIO4_IO03 ~ ~ ~ ~ - PD4 = portD + 4 // [EMC_04]: SEMC_DATA04 FLEXPWM4_PWMA02 SAI2_TX_DATA XBAR1_INOUT06 FLEXIO1_FLEXIO04 GPIO4_IO04 ~ ~ ~ ~ - PD5 = portD + 5 // [EMC_05]: SEMC_DATA05 FLEXPWM4_PWMB02 SAI2_TX_SYNC XBAR1_INOUT07 FLEXIO1_FLEXIO05 GPIO4_IO05 ~ ~ ~ ~ - PD6 = portD + 6 // [EMC_06]: SEMC_DATA06 FLEXPWM2_PWMA00 SAI2_TX_BCLK XBAR1_INOUT08 FLEXIO1_FLEXIO06 GPIO4_IO06 ~ ~ ~ ~ - PD7 = portD + 7 // [EMC_07]: SEMC_DATA07 FLEXPWM2_PWMB00 SAI2_MCLK XBAR1_INOUT09 FLEXIO1_FLEXIO07 GPIO4_IO07 ~ ~ ~ ~ - PD8 = portD + 8 // [EMC_08]: SEMC_DM00 FLEXPWM2_PWMA01 SAI2_RX_DATA XBAR1_INOUT17 FLEXIO1_FLEXIO08 GPIO4_IO08 ~ ~ ~ ~ - PD9 = portD + 9 // [EMC_09]: SEMC_ADDR00 FLEXPWM2_PWMB01 SAI2_RX_SYNC FLEXCAN2_TX FLEXIO1_FLEXIO09 GPIO4_IO09 FLEXSPI2_B_SS1_B ~ ~ ~ - PD10 = portD + 10 // [EMC_10]: SEMC_ADDR01 FLEXPWM2_PWMA02 SAI2_RX_BCLK FLEXCAN2_RX FLEXIO1_FLEXIO10 GPIO4_IO10 FLEXSPI2_B_SS0_B ~ ~ ~ - PD11 = portD + 11 // [EMC_11]: SEMC_ADDR02 FLEXPWM2_PWMB02 LPI2C4_SDA USDHC2_RESET_B FLEXIO1_FLEXIO11 GPIO4_IO11 FLEXSPI2_B_DQS ~ ~ ~ - PD12 = portD + 12 // [EMC_12]: SEMC_ADDR03 XBAR1_IN24 LPI2C4_SCL USDHC1_WP FLEXPWM1_PWMA03 GPIO4_IO12 FLEXSPI2_B_SCLK ~ ~ ~ - PD13 = portD + 13 // [EMC_13]: SEMC_ADDR04 XBAR1_IN25 LPUART3_TX MQS_RIGHT FLEXPWM1_PWMB03 GPIO4_IO13 FLEXSPI2_B_DATA00 ~ ~ ~ - PD14 = portD + 14 // [EMC_14]: SEMC_ADDR05 XBAR1_INOUT19 LPUART3_RX MQS_LEFT LPSPI2_PCS1 GPIO4_IO14 FLEXSPI2_B_DATA01 ~ ~ ~ - PD15 = portD + 15 // [EMC_15]: SEMC_ADDR06 XBAR1_IN20 LPUART3_CTS_B SPDIF_OUT QTIMER3_TIMER0 GPIO4_IO15 FLEXSPI2_B_DATA02 ~ ~ ~ - PD16 = portD + 16 // [EMC_16]: SEMC_ADDR07 XBAR1_IN21 LPUART3_RTS_B SPDIF_IN QTIMER3_TIMER1 GPIO4_IO16 FLEXSPI2_B_DATA03 ~ ~ ~ - PD17 = portD + 17 // [EMC_17]: SEMC_ADDR08 FLEXPWM4_PWMA03 LPUART4_CTS_B FLEXCAN1_TX QTIMER3_TIMER2 GPIO4_IO17 ~ ~ ~ ~ - PD18 = portD + 18 // [EMC_18]: SEMC_ADDR09 FLEXPWM4_PWMB03 LPUART4_RTS_B FLEXCAN1_RX QTIMER3_TIMER3 GPIO4_IO18 SNVS_VIO_5_CTL ~ ~ ~ - PD19 = portD + 19 // [EMC_19]: SEMC_ADDR11 FLEXPWM2_PWMA03 LPUART4_TX ENET_RDATA01 QTIMER2_TIMER0 GPIO4_IO19 SNVS_VIO_5 ~ ~ ~ - PD20 = portD + 20 // [EMC_20]: SEMC_ADDR12 FLEXPWM2_PWMB03 LPUART4_RX ENET_RDATA00 QTIMER2_TIMER1 GPIO4_IO20 ~ ~ ~ ~ - PD21 = portD + 21 // [EMC_21]: SEMC_BA0 FLEXPWM3_PWMA03 LPI2C3_SDA ENET_TDATA01 QTIMER2_TIMER2 GPIO4_IO21 ~ ~ ~ ~ - PD22 = portD + 22 // [EMC_22]: SEMC_BA1 FLEXPWM3_PWMB03 LPI2C3_SCL ENET_TDATA00 QTIMER2_TIMER3 GPIO4_IO22 FLEXSPI2_A_SS1_B ~ ~ ~ - PD23 = portD + 23 // [EMC_23]: SEMC_ADDR10 FLEXPWM1_PWMA00 LPUART5_TX ENET_RX_EN GPT1_CAPTURE2 GPIO4_IO23 FLEXSPI2_A_DQS ~ ~ ~ - PD24 = portD + 24 // [EMC_24]: SEMC_CAS FLEXPWM1_PWMB00 LPUART5_RX ENET_TX_EN GPT1_CAPTURE1 GPIO4_IO24 FLEXSPI2_A_SS0_B ~ ~ ~ - PD25 = portD + 25 // [EMC_25]: SEMC_RAS FLEXPWM1_PWMA01 LPUART6_TX ENET_TX_CLK ENET_REF_CLK GPIO4_IO25 FLEXSPI2_A_SCLK ~ ~ ~ - PD26 = portD + 26 // [EMC_26]: SEMC_CLK FLEXPWM1_PWMB01 LPUART6_RX ENET_RX_ER FLEXIO1_FLEXIO12 GPIO4_IO26 FLEXSPI2_A_DATA00 ~ ~ ~ - PD27 = portD + 27 // [EMC_27]: SEMC_CKE FLEXPWM1_PWMA02 LPUART5_RTS_B LPSPI1_SCK FLEXIO1_FLEXIO13 GPIO4_IO27 FLEXSPI2_A_DATA01 ~ ~ ~ - PD28 = portD + 28 // [EMC_28]: SEMC_WE FLEXPWM1_PWMB02 LPUART5_CTS_B LPSPI1_SDO FLEXIO1_FLEXIO14 GPIO4_IO28 FLEXSPI2_A_DATA02 ~ ~ ~ - PD29 = portD + 29 // [EMC_29]: SEMC_CS0 FLEXPWM3_PWMA00 LPUART6_RTS_B LPSPI1_SDI FLEXIO1_FLEXIO15 GPIO4_IO29 FLEXSPI2_A_DATA03 ~ ~ ~ - PD30 = portD + 30 // [EMC_30]: SEMC_DATA08 FLEXPWM3_PWMB00 LPUART6_CTS_B LPSPI1_PCS0 CSI_DATA23 GPIO4_IO30 ENET2_TDATA00 ~ ~ ~ - PD31 = portD + 31 // [EMC_31]: SEMC_DATA09 FLEXPWM3_PWMA01 LPUART7_TX LPSPI1_PCS1 CSI_DATA22 GPIO4_IO31 ENET2_TDATA01 ~ ~ ~ -) - -func (p Pin) getPos() uint8 { return uint8(p % 32) } -func (p Pin) getMask() uint32 { return uint32(1) << p.getPos() } -func (p Pin) getPort() Pin { return Pin(p/32) * 32 } - -// Configure sets the GPIO pad and pin properties, and selects the appropriate -// alternate function, for a given Pin and PinConfig. -func (p Pin) Configure(config PinConfig) { - var ( - sre = uint32(0x01 << 0) - dse = func(n uint32) uint32 { return (n & 0x07) << 3 } - spd = func(n uint32) uint32 { return (n & 0x03) << 6 } - ode = uint32(0x01 << 11) - pke = uint32(0x01 << 12) - pue = uint32(0x01 << 13) - pup = func(n uint32) uint32 { return (n & 0x03) << 14 } - hys = uint32(0x01 << 16) - ) - - _, gpio := p.getGPIO() // use fast GPIO for all pins - pad, mux := p.getPad() - - // first configure the pad characteristics - switch config.Mode { - case PinInput: - gpio.GDIR.ClearBits(p.getMask()) - pad.Set(dse(7)) - - case PinInputPullup: - gpio.GDIR.ClearBits(p.getMask()) - pad.Set(dse(7) | pke | pue | pup(3) | hys) - - case PinInputPulldown: - gpio.GDIR.ClearBits(p.getMask()) - pad.Set(dse(7) | pke | pue | hys) - - case PinOutput: - gpio.GDIR.SetBits(p.getMask()) - pad.Set(dse(7)) - - case PinOutputOpenDrain: - gpio.GDIR.SetBits(p.getMask()) - pad.Set(dse(7) | ode) - - case PinDisable: - gpio.GDIR.ClearBits(p.getMask()) - pad.Set(dse(7) | hys) - - case PinInputAnalog: - gpio.GDIR.ClearBits(p.getMask()) - pad.Set(dse(7)) - - case PinModeUARTTX: - pad.Set(sre | dse(3) | spd(3)) - - case PinModeUARTRX: - pad.Set(dse(7) | pke | pue | pup(3) | hys) - - case PinModeSPISDI: - pad.Set(dse(7) | spd(2)) - - case PinModeSPISDO: - pad.Set(dse(7) | spd(2)) - - case PinModeSPICLK: - pad.Set(dse(7) | spd(2)) - - case PinModeSPICS: - pad.Set(dse(7)) - - case PinModeI2CSDA, PinModeI2CSCL: - pad.Set(ode | sre | dse(4) | spd(1) | pke | pue | pup(3)) - } - - // then configure the alternate function mux - mux.Set(p.getMuxMode(config)) -} - -// Get returns the current value of a GPIO pin. -func (p Pin) Get() bool { - _, gpio := p.getGPIO() // use fast GPIO for all pins - return gpio.PSR.HasBits(p.getMask()) -} - -// Set changes the value of the GPIO pin. The pin must be configured as output. -func (p Pin) Set(value bool) { - _, gpio := p.getGPIO() // use fast GPIO for all pins - if value { - gpio.DR_SET.Set(p.getMask()) - } else { - gpio.DR_CLEAR.Set(p.getMask()) - } -} - -// Toggle switches an output pin from low to high or from high to low. -func (p Pin) Toggle() { - _, gpio := p.getGPIO() // use fast GPIO for all pins - gpio.DR_TOGGLE.Set(p.getMask()) -} - -// dispatchInterrupt invokes the user-provided callback functions for external -// interrupts generated on the high-speed GPIO pins. -// -// Unfortunately, all four high-speed GPIO ports (A-D) are connected to just a -// single interrupt control line. Therefore, the interrupt status register (ISR) -// must be checked in all four GPIO ports on every interrupt. -func (jt *pinJumpTable) dispatchInterrupt(interrupt.Interrupt) { - handle := func(gpio *nxp.GPIO_Type, port Pin) { - if status := gpio.ISR.Get() & gpio.IMR.Get(); status != 0 { - gpio.ISR.Set(status) // clear interrupt - for status != 0 { - off := Pin(bits.TrailingZeros32(status)) // ctz - pin := Pin(port + off) - jt.lut[pin](pin) - status &^= 1 << off - } - } - } - if jt.numDefined > 0 { - handle(nxp.GPIO6, portA) - handle(nxp.GPIO7, portB) - handle(nxp.GPIO8, portC) - handle(nxp.GPIO9, portD) - } -} - -// set associates a function with a given Pin in the receiver lookup table. If -// the function is nil, the given Pin's associated function is removed. -func (jt *pinJumpTable) set(pin Pin, fn func(Pin)) { - if int(pin) < len(jt.lut) { - if nil != fn { - if nil == jt.lut[pin] { - jt.numDefined++ - } - jt.lut[pin] = fn - } else { - if nil != jt.lut[pin] { - jt.numDefined-- - } - jt.lut[pin] = nil - } - } -} - -// SetInterrupt sets an interrupt to be executed when a particular pin changes -// state. The pin should already be configured as an input, including a pull up -// or down if no external pull is provided. -// -// This call will replace a previously set callback on this pin. You can pass a -// nil func to unset the pin change interrupt. If you do so, the change -// parameter is ignored and can be set to any value (such as 0). -func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error { - _, gpio := p.getGPIO() // use fast GPIO for all pins - mask := p.getMask() - if nil != callback { - switch change { - case PinRising, PinFalling: - gpio.EDGE_SEL.ClearBits(mask) - var reg *volatile.Register32 - var pos uint8 - if pos = p.getPos(); pos < 16 { - reg = &gpio.ICR1 // ICR1 = pins 0-15 - } else { - reg = &gpio.ICR2 // ICR2 = pins 16-31 - pos -= 16 - } - reg.ReplaceBits(uint32(change), 0x3, pos*2) - case PinToggle: - gpio.EDGE_SEL.SetBits(mask) - } - pinISR.set(p, callback) // associate the callback with the pin - gpio.ISR.Set(mask) // clear any pending interrupt (W1C) - gpio.IMR.SetBits(mask) // enable external interrupt - } else { - pinISR.set(p, nil) // remove any associated callback from the pin - gpio.ISR.Set(mask) // clear any pending interrupt (W1C) - gpio.IMR.ClearBits(mask) // disable external interrupt - } - // enable or disable the interrupt based on number of defined callbacks - if pinISR.numDefined > 0 { - if nil == pinInterrupt { - // create the Interrupt if it is not yet defined - irq := interrupt.New(nxp.IRQ_GPIO6_7_8_9, pinISR.dispatchInterrupt) - pinInterrupt = &irq - pinInterrupt.Enable() - } - } else { - if nil != pinInterrupt { - // disable the interrupt if it is defined - pinInterrupt.Disable() - } - } - return nil -} - -// getGPIO returns both the normal (IPG_CLK_ROOT) and high-speed (AHB_CLK_ROOT) -// GPIO peripherals to which a given Pin is connected. -// -// Note that, currently, the device is configured to use high-speed GPIO for all -// pins (GPIO6-9), so the first return value should not be used (GPIO1-4). -// See the remarks and documentation reference in the comments preceding the -// const Pin definitions above. -func (p Pin) getGPIO() (norm *nxp.GPIO_Type, fast *nxp.GPIO_Type) { - switch p.getPort() { - case portA: - return nxp.GPIO1, nxp.GPIO6 - case portB: - return nxp.GPIO2, nxp.GPIO7 - case portC: - return nxp.GPIO3, nxp.GPIO8 - case portD: - return nxp.GPIO4, nxp.GPIO9 - default: - panic("machine: unknown port") - } -} - -// getPad returns both the pad and mux configuration registers for a given Pin. -func (p Pin) getPad() (pad *volatile.Register32, mux *volatile.Register32) { - switch p.getPort() { - case portA: - switch p.getPos() { - case 0: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_00, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_00 - case 1: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_01, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_01 - case 2: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_02, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_02 - case 3: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_03, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_03 - case 4: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_04, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_04 - case 5: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_05, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_05 - case 6: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_06, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_06 - case 7: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_07, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_07 - case 8: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_08, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_08 - case 9: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_09, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_09 - case 10: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_10, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_10 - case 11: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_11, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_11 - case 12: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_12, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_12 - case 13: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_13, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_13 - case 14: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_14, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_14 - case 15: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B0_15, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B0_15 - case 16: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_00, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_00 - case 17: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_01, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_01 - case 18: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_02, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_02 - case 19: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_03, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_03 - case 20: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_04, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_04 - case 21: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_05, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_05 - case 22: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_06, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_06 - case 23: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_07, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_07 - case 24: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_08, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_08 - case 25: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_09, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_09 - case 26: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_10, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_10 - case 27: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_11, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_11 - case 28: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_12, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_12 - case 29: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_13, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_13 - case 30: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_14, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_14 - case 31: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_B1_15, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_AD_B1_15 - } - case portB: - switch p.getPos() { - case 0: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_00, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_00 - case 1: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_01, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_01 - case 2: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_02, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_02 - case 3: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_03, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_03 - case 4: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_04, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_04 - case 5: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_05, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_05 - case 6: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_06, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_06 - case 7: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_07, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_07 - case 8: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_08, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_08 - case 9: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_09, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_09 - case 10: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_10, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_10 - case 11: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_11, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_11 - case 12: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_12, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_12 - case 13: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_13, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_13 - case 14: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_14, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_14 - case 15: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B0_15, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B0_15 - case 16: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_00, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_00 - case 17: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_01, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_01 - case 18: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_02, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_02 - case 19: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_03, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_03 - case 20: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_04, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_04 - case 21: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_05, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_05 - case 22: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_06, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_06 - case 23: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_07, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_07 - case 24: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_08, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_08 - case 25: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_09, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_09 - case 26: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_10, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_10 - case 27: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_11, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_11 - case 28: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_12, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_12 - case 29: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_13, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_13 - case 30: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_14, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_14 - case 31: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_B1_15, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_B1_15 - } - case portC: - switch p.getPos() { - case 0: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_00, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_00 - case 1: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_01, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_01 - case 2: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_02, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_02 - case 3: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_03, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_03 - case 4: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_04, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_04 - case 5: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_05, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_05 - case 6: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_06, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_06 - case 7: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_07, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_07 - case 8: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_08, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_08 - case 9: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_09, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_09 - case 10: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_10, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_10 - case 11: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B1_11, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B1_11 - case 12: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B0_00, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B0_00 - case 13: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B0_01, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B0_01 - case 14: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B0_02, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B0_02 - case 15: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B0_03, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B0_03 - case 16: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B0_04, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B0_04 - case 17: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_SD_B0_05, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_SD_B0_05 - case 18: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_32, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_32 - case 19: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_33, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_33 - case 20: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_34, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_34 - case 21: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_35, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_35 - case 22: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_36, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_36 - case 23: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_37, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_37 - case 24: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_38, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_38 - case 25: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_39, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_39 - case 26: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_40, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_40 - case 27: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_41, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_41 - case 28, 29, 30, 31: - } - case portD: - switch p.getPos() { - case 0: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_00, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_00 - case 1: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_01, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_01 - case 2: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_02, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_02 - case 3: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_03, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_03 - case 4: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_04, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_04 - case 5: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_05, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_05 - case 6: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_06, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_06 - case 7: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_07, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_07 - case 8: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_08, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_08 - case 9: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_09, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_09 - case 10: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_10, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_10 - case 11: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_11, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_11 - case 12: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_12, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_12 - case 13: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_13, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_13 - case 14: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_14, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_14 - case 15: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_15, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_15 - case 16: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_16, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_16 - case 17: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_17, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_17 - case 18: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_18, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_18 - case 19: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_19, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_19 - case 20: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_20, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_20 - case 21: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_21, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_21 - case 22: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_22, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_22 - case 23: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_23, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_23 - case 24: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_24, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_24 - case 25: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_25, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_25 - case 26: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_26, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_26 - case 27: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_27, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_27 - case 28: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_28, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_28 - case 29: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_29, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_29 - case 30: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_30, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_30 - case 31: - return &nxp.IOMUXC.SW_PAD_CTL_PAD_GPIO_EMC_31, &nxp.IOMUXC.SW_MUX_CTL_PAD_GPIO_EMC_31 - } - } - panic("machine: invalid pin") -} - -// muxSelect is yet another level of indirection required to connect pins in an -// alternate function state to a desired peripheral (since more than one pin can -// provide a given alternate function). -// -// Once a pin is configured with a given alternate function mode, the IOMUXC -// device must then be configured to select which alternate function pin to -// route to the desired peripheral. -// -// The reference manual refers to this functionality as a "Daisy Chain". The -// associated docs are found in the i.MX RT1060 Processor Reference Manual: -// "Chapter 11.3.3 Daisy chain - multi pads driving same module input pin" -type muxSelect struct { - mux uint8 // AF mux selection (NOT a Pin type) - sel *volatile.Register32 // AF selection register -} - -// connect configures the IOMUXC controller to route a given pin with alternate -// function to a desired peripheral (see godoc comments on type muxSelect). -func (s muxSelect) connect() { - s.sel.Set(uint32(s.mux)) -} - -// getMuxMode acts as a callback from the `(Pin).Configure(PinMode)` routine to -// determine the alternate function setting for a given Pin and PinConfig. -// This value is used in the IOMUXC device's SW_MUX_CTL_PAD_GPIO_* registers. -func (p Pin) getMuxMode(config PinConfig) uint32 { - const forcePath = true // TODO: should be input parameter? - switch config.Mode { - - // GPIO - case PinInput, PinInputPullup, PinInputPulldown, - PinOutput, PinOutputOpenDrain, PinDisable: - mode := uint32(0x5) // GPIO is always alternate function 5 - if forcePath { - mode |= 0x10 // SION bit - } - return mode - - // ADC - case PinInputAnalog: - mode := uint32(0x5) // use alternate function 5 (GPIO) - if forcePath { - mode |= 0x10 // SION bit - } - return mode - - // UART RX/TX - case PinModeUARTRX, PinModeUARTTX: - mode := uint32(0x2) // UART is usually alternate function 2 on Teensy 4.x - // Teensy 4.1 has a UART (LPUART5) with alternate function 1 - if p == PB28 || p == PB29 { - mode = 0x1 - } - return mode - - // SPI SDI - case PinModeSPISDI: - var mode uint32 - switch p { - case PC15: // LPSPI1 SDI on PC15 alternate function 4 - mode = uint32(0x4) - case PA2: // LPSPI3 SDI on PA2 alternate function 7 - mode = uint32(0x7) - case PB1: // LPSPI4 SDI on PB1 alternate function 3 - mode = uint32(0x3) - default: - panic("machine: invalid SPI SDI pin") - } - if forcePath { - mode |= 0x10 // SION bit - } - return mode - - // SPI SDO - case PinModeSPISDO: - var mode uint32 - switch p { - case PC14: // LPSPI1 SDO on PC14 alternate function 4 - mode = uint32(0x4) - case PA30: // LPSPI3 SDO on PA30 alternate function 2 - mode = uint32(0x2) - case PB2: // LPSPI4 SDO on PB2 alternate function 3 - mode = uint32(0x3) - default: - panic("machine: invalid SPI SDO pin") - } - if forcePath { - mode |= 0x10 // SION bit - } - return mode - - // SPI SCK - case PinModeSPICLK: - var mode uint32 - switch p { - case PC12: // LPSPI1 SCK on PC12 alternate function 4 - mode = uint32(0x4) - case PA31: // LPSPI3 SCK on PA31 alternate function 2 - mode = uint32(0x2) - case PB3: // LPSPI4 SCK on PB3 alternate function 3 - mode = uint32(0x3) - default: - panic("machine: invalid SPI CLK pin") - } - if forcePath { - mode |= 0x10 // SION bit - } - return mode - - // SPI CS - case PinModeSPICS: - var mode uint32 - switch p { - case PC13: // LPSPI1 CS on PC13 alternate function 4 - mode = uint32(0x4) - case PA3: // LPSPI3 CS on PA3 alternate function 7 - mode = uint32(0x7) - case PB0: // LPSPI4 CS on PB0 alternate function 3 - mode = uint32(0x3) - default: // use alternate function 5 (GPIO) if non-CS pin selected - mode = uint32(0x5) - } - if forcePath { - mode |= 0x10 // SION bit - } - return mode - - // I2C SDA - case PinModeI2CSDA: - var mode uint32 - switch p { - case PA13: // LPI2C4 SDA on PA13 alternate function 0 - mode = uint32(0) - case PA17: // LPI2C1 SDA on PA17 alternate function 3 - mode = uint32(3) - case PA22: // LPI2C3 SDA on PA22 alternate function 1 - mode = uint32(1) - default: - panic("machine: invalid I2C SDA pin") - } - if forcePath { - mode |= 0x10 // SION bit - } - return mode - - // I2C SCL - case PinModeI2CSCL: - var mode uint32 - switch p { - case PA12: // LPI2C4 SCL on PA12 alternate function 0 - mode = uint32(0) - case PA16: // LPI2C1 SCL on PA16 alternate function 3 - mode = uint32(3) - case PA23: // LPI2C3 SCL on PA23 alternate function 1 - mode = uint32(1) - default: - panic("machine: invalid I2C SCL pin") - } - if forcePath { - mode |= 0x10 // SION bit - } - return mode - - default: - panic("machine: invalid pin mode") - } -} - -// maximum ADC value for the currently configured resolution (used for scaling) -var adcMaximum uint32 - -// InitADC is not used by this machine. Use `(ADC).Configure()`. -func InitADC() {} - -// Configure initializes the receiver's ADC peripheral and pin for analog input. -func (a ADC) Configure(config ADCConfig) { - // if not specified, use defaults: 10-bit resolution, 4 samples/conversion - const ( - defaultResolution = uint32(10) - defaultSamples = uint32(4) - ) - - a.Pin.Configure(PinConfig{Mode: PinInputAnalog}) - - resolution, samples := config.Resolution, config.Samples - if 0 == resolution { - resolution = defaultResolution - } - if 0 == samples { - samples = defaultSamples - } - if resolution > 12 { - resolution = 12 // maximum resolution of 12 bits - } - adcMaximum = (uint32(1) << resolution) - 1 - - mode, average := a.mode(resolution, samples) - - nxp.ADC1.CFG.Set(mode | nxp.ADC_CFG_ADHSC) // configure ADC1 - nxp.ADC2.CFG.Set(mode | nxp.ADC_CFG_ADHSC) // configure ADC2 - - // begin calibration - nxp.ADC1.GC.Set(average | nxp.ADC_GC_CAL) - nxp.ADC2.GC.Set(average | nxp.ADC_GC_CAL) - - for a.isCalibrating() { - } // wait for calibration -} - -// Get performs a single ADC conversion, returning a 16-bit unsigned integer. -// The value returned will be scaled (uniformly distributed) if necessary so -// that it is always in the range [0..65535], regardless of the ADC's configured -// bit size (resolution). -func (a ADC) Get() uint16 { - if ch1, ch2, ok := a.Pin.getADCChannel(); ok { - for a.isCalibrating() { - } // wait for calibration - var val uint32 - if noADCChannel != ch1 { - nxp.ADC1.HC0.Set(uint32(ch1)) - for !nxp.ADC1.HS.HasBits(nxp.ADC_HS_COCO0) { - } - val = nxp.ADC1.R0.Get() & 0xFFFF - } else { - nxp.ADC2.HC0.Set(uint32(ch2)) - for !nxp.ADC2.HS.HasBits(nxp.ADC_HS_COCO0) { - } - val = nxp.ADC2.R0.Get() & 0xFFFF - } - // should never be zero, but just in case, use UINT16_MAX so that the scalar - // gets factored out of the conversion result, leaving the original reading - // to be returned unaltered/unscaled. - if adcMaximum == 0 { - adcMaximum = 0xFFFF - } - // scale up to a 16-bit value - return uint16((val * 0xFFFF) / adcMaximum) - } - return 0 -} - -// mode constructs bit masks for mode and average - used in ADC configuration -// registers - from a given ADC bit size (resolution) and sample count. -func (a ADC) mode(resolution, samples uint32) (mode, average uint32) { - - // use asynchronous clock (ADACK) (0 = IPG, 1 = IPG/2, or 3 = ADACK) - mode = (nxp.ADC_CFG_ADICLK_ADICLK_3 << nxp.ADC_CFG_ADICLK_Pos) & nxp.ADC_CFG_ADICLK_Msk - - // input clock DIV2 (0 = DIV1, 1 = DIV2, 2 = DIV4, or 3 = DIV8) - mode |= (nxp.ADC_CFG_ADIV_ADIV_1 << nxp.ADC_CFG_ADIV_Pos) & nxp.ADC_CFG_ADIV_Msk - - switch resolution { - case 8: // 8-bit conversion, sample period (ADC clocks) = 8 - mode |= (nxp.ADC_CFG_MODE_MODE_0 << nxp.ADC_CFG_MODE_Pos) & nxp.ADC_CFG_MODE_Msk - mode |= (nxp.ADC_CFG_ADSTS_ADSTS_3 << nxp.ADC_CFG_ADSTS_Pos) & nxp.ADC_CFG_ADSTS_Msk - - case 12: // 12-bit conversion, sample period (ADC clocks) = 24 - mode |= (nxp.ADC_CFG_MODE_MODE_2 << nxp.ADC_CFG_MODE_Pos) & nxp.ADC_CFG_MODE_Msk - mode |= (nxp.ADC_CFG_ADSTS_ADSTS_3 << nxp.ADC_CFG_ADSTS_Pos) & nxp.ADC_CFG_ADSTS_Msk - mode |= nxp.ADC_CFG_ADLSMP - - default: // 10-bit conversion, sample period (ADC clocks) = 20 - mode |= (nxp.ADC_CFG_MODE_MODE_1 << nxp.ADC_CFG_MODE_Pos) & nxp.ADC_CFG_MODE_Msk - mode |= (nxp.ADC_CFG_ADSTS_ADSTS_2 << nxp.ADC_CFG_ADSTS_Pos) & nxp.ADC_CFG_ADSTS_Msk - mode |= nxp.ADC_CFG_ADLSMP - } - - if samples >= 4 { - if samples >= 32 { - // 32 samples averaged - mode |= (nxp.ADC_CFG_AVGS_AVGS_3 << nxp.ADC_CFG_AVGS_Pos) & nxp.ADC_CFG_AVGS_Msk - } else if samples >= 16 { - // 16 samples averaged - mode |= (nxp.ADC_CFG_AVGS_AVGS_2 << nxp.ADC_CFG_AVGS_Pos) & nxp.ADC_CFG_AVGS_Msk - } else if samples >= 8 { - // 8 samples averaged - mode |= (nxp.ADC_CFG_AVGS_AVGS_1 << nxp.ADC_CFG_AVGS_Pos) & nxp.ADC_CFG_AVGS_Msk - } else { - // 4 samples averaged - mode |= (nxp.ADC_CFG_AVGS_AVGS_0 << nxp.ADC_CFG_AVGS_Pos) & nxp.ADC_CFG_AVGS_Msk - } - average = nxp.ADC_GC_AVGE - } - - return mode, average -} - -// isCalibrating returns true if and only if either one (or both) of ADC1 and -// ADC2 have their calibrating flags set. ADC reads must wait until these flags -// are clear before attempting a conversion. -func (a ADC) isCalibrating() bool { - return nxp.ADC1.GC.HasBits(nxp.ADC_GC_CAL) || nxp.ADC2.GC.HasBits(nxp.ADC_GC_CAL) -} - -const noADCChannel = uint8(0xFF) - -// getADCChannel returns the input channel for ADC1/ADC2 of the receiver Pin p. -func (p Pin) getADCChannel() (adc1, adc2 uint8, ok bool) { - switch p { - case PA12: // [AD_B0_12]: ADC1_IN1 ~ - return 1, noADCChannel, true - case PA13: // [AD_B0_13]: ADC1_IN2 ~ - return 2, noADCChannel, true - case PA14: // [AD_B0_14]: ADC1_IN3 ~ - return 3, noADCChannel, true - case PA15: // [AD_B0_15]: ADC1_IN4 ~ - return 4, noADCChannel, true - case PA16: // [AD_B1_00]: ADC1_IN5 ADC2_IN5 - return 5, 5, true - case PA17: // [AD_B1_01]: ADC1_IN6 ADC2_IN6 - return 6, 6, true - case PA18: // [AD_B1_02]: ADC1_IN7 ADC2_IN7 - return 7, 7, true - case PA19: // [AD_B1_03]: ADC1_IN8 ADC2_IN8 - return 8, 8, true - case PA20: // [AD_B1_04]: ADC1_IN9 ADC2_IN9 - return 9, 9, true - case PA21: // [AD_B1_05]: ADC1_IN10 ADC2_IN10 - return 10, 10, true - case PA22: // [AD_B1_06]: ADC1_IN11 ADC2_IN11 - return 11, 11, true - case PA23: // [AD_B1_07]: ADC1_IN12 ADC2_IN12 - return 12, 12, true - case PA24: // [AD_B1_08]: ADC1_IN13 ADC2_IN13 - return 13, 13, true - case PA25: // [AD_B1_09]: ADC1_IN14 ADC2_IN14 - return 14, 14, true - case PA26: // [AD_B1_10]: ADC1_IN15 ADC2_IN15 - return 15, 15, true - case PA27: // [AD_B1_11]: ADC1_IN0 ADC2_IN0 - return 16, 16, true - case PA28: // [AD_B1_12]: ~ ADC2_IN1 - return noADCChannel, 1, true - case PA29: // [AD_B1_13]: ~ ADC2_IN2 - return noADCChannel, 2, true - case PA30: // [AD_B1_14]: ~ ADC2_IN3 - return noADCChannel, 3, true - case PA31: // [AD_B1_15]: ~ ADC2_IN4 - return noADCChannel, 4, true - default: - return noADCChannel, noADCChannel, false - } -} diff --git a/emb/machine/machine_mimxrt1062_i2c.go b/emb/machine/machine_mimxrt1062_i2c.go deleted file mode 100644 index f3c4636..0000000 --- a/emb/machine/machine_mimxrt1062_i2c.go +++ /dev/null @@ -1,642 +0,0 @@ -//go:build mimxrt1062 - -package machine - -// I2C peripheral abstraction layer for the MIMXRT1062 - -import ( - "device/nxp" -) - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 - SDA Pin - SCL Pin -} - -type I2C struct { - Bus *nxp.LPI2C_Type - - // these pins are initialized by each global I2C variable declared in the - // board_teensy4x.go file according to the board manufacturer's default pin - // mapping. they can be overridden with the I2CConfig argument given to - // (*I2C) Configure(I2CConfig). - sda, scl Pin - - // these hold the input selector ("daisy chain") values that select which pins - // are connected to the LPI2C device, and should be defined where the I2C - // instance is declared (e.g., in the board definition). see the godoc - // comments on type muxSelect for more details. - muxSDA, muxSCL muxSelect -} - -type i2cDirection bool - -const ( - directionWrite i2cDirection = false - directionRead i2cDirection = true -) - -func (dir i2cDirection) shift(addr uint16) uint32 { - if addr <<= 1; dir == directionRead { - addr |= 1 - } - return uint32(addr) & 0xFF -} - -// I2C enumerated types -type ( - resultFlag uint32 - statusFlag uint32 - transferFlag uint32 - commandFlag uint32 - stateFlag uint32 -) - -const ( - // general purpose results - resultSuccess resultFlag = 0x0 // success - resultFail resultFlag = 0x1 // fail - resultReadOnly resultFlag = 0x2 // read only failure - resultOutOfRange resultFlag = 0x3 // out of range access - resultInvalidArgument resultFlag = 0x4 // invalid argument check - // I2C-specific results - resultBusy resultFlag = 0x0384 + 0x0 // the controller is already performing a transfer - resultIdle resultFlag = 0x0384 + 0x1 // the peripheral driver is idle - resultNak resultFlag = 0x0384 + 0x2 // the peripheral device sent a NAK in response to a byte - resultFifoError resultFlag = 0x0384 + 0x3 // FIFO under run or overrun - resultBitError resultFlag = 0x0384 + 0x4 // transferred bit was not seen on the bus - resultArbitrationLost resultFlag = 0x0384 + 0x5 // arbitration lost error - resultPinLowTimeout resultFlag = 0x0384 + 0x6 // SCL or SDA were held low longer than the timeout - resultNoTransferInProgress resultFlag = 0x0384 + 0x7 // attempt to abort a transfer when one is not in progress - resultDmaRequestFail resultFlag = 0x0384 + 0x8 // DMA request failed - resultTimeout resultFlag = 0x0384 + 0x9 // timeout polling status flags -) - -const ( - statusTxReady statusFlag = nxp.LPI2C_MSR_TDF // transmit data flag - statusRxReady statusFlag = nxp.LPI2C_MSR_RDF // receive data flag - statusEndOfPacket statusFlag = nxp.LPI2C_MSR_EPF // end Packet flag - statusStopDetect statusFlag = nxp.LPI2C_MSR_SDF // stop detect flag - statusNackDetect statusFlag = nxp.LPI2C_MSR_NDF // NACK detect flag - statusArbitrationLost statusFlag = nxp.LPI2C_MSR_ALF // arbitration lost flag - statusFifoErr statusFlag = nxp.LPI2C_MSR_FEF // FIFO error flag - statusPinLowTimeout statusFlag = nxp.LPI2C_MSR_PLTF // pin low timeout flag - statusI2CDataMatch statusFlag = nxp.LPI2C_MSR_DMF // data match flag - statusBusy statusFlag = nxp.LPI2C_MSR_MBF // busy flag - statusBusBusy statusFlag = nxp.LPI2C_MSR_BBF // bus busy flag - - // all flags which are cleared by the driver upon starting a transfer - statusClear statusFlag = statusEndOfPacket | statusStopDetect | statusNackDetect | - statusArbitrationLost | statusFifoErr | statusPinLowTimeout | statusI2CDataMatch - - // IRQ sources enabled by the non-blocking transactional API - statusIrq statusFlag = statusArbitrationLost | statusTxReady | statusRxReady | - statusStopDetect | statusNackDetect | statusPinLowTimeout | statusFifoErr - - // errors to check for - statusError statusFlag = statusNackDetect | statusArbitrationLost | statusFifoErr | - statusPinLowTimeout -) - -// LPI2C transfer modes -const ( - transferDefault transferFlag = 0x0 // transfer starts with a start signal, stops with a stop signal - transferNoStart transferFlag = 0x1 // don't send a start condition, address, and sub address - transferRepeatedStart transferFlag = 0x2 // send a repeated start condition - transferNoStop transferFlag = 0x4 // don't send a stop condition -) - -// LPI2C FIFO commands -const ( - commandTxData commandFlag = (0x0 << nxp.LPI2C_MTDR_CMD_Pos) & nxp.LPI2C_MTDR_CMD_Msk // transmit - commandRxData commandFlag = (0x1 << nxp.LPI2C_MTDR_CMD_Pos) & nxp.LPI2C_MTDR_CMD_Msk // receive - commandStop commandFlag = (0x2 << nxp.LPI2C_MTDR_CMD_Pos) & nxp.LPI2C_MTDR_CMD_Msk // generate STOP condition - commandStart commandFlag = (0x4 << nxp.LPI2C_MTDR_CMD_Pos) & nxp.LPI2C_MTDR_CMD_Msk // generate (REPEATED)START and transmit -) - -// LPI2C transactional states -const ( - stateIdle stateFlag = 0x0 - stateSendCommand stateFlag = 0x1 - stateIssueReadCommand stateFlag = 0x2 - stateTransferData stateFlag = 0x3 - stateStop stateFlag = 0x4 - stateWaitForCompletion stateFlag = 0x5 -) - -func (i2c *I2C) setPins(c I2CConfig) (sda, scl Pin) { - // if both given pins are defined, or either receiver pin is undefined. - if 0 != c.SDA && 0 != c.SCL || 0 == i2c.sda || 0 == i2c.scl { - // override the receiver's pins. - i2c.sda, i2c.scl = c.SDA, c.SCL - } - // return the selected pins. - return i2c.sda, i2c.scl -} - -// Configure is intended to setup an I2C interface for transmit/receive. -func (i2c *I2C) Configure(config I2CConfig) error { - // init pins - sda, scl := i2c.setPins(config) - - // configure the mux and pad control registers - sda.Configure(PinConfig{Mode: PinModeI2CSDA}) - scl.Configure(PinConfig{Mode: PinModeI2CSCL}) - - // configure the mux input selector - i2c.muxSDA.connect() - i2c.muxSCL.connect() - - freq := config.Frequency - if 0 == freq { - freq = 100 * KHz - } - - // reset clock and registers, and enable LPI2C module interface - i2c.reset(freq) - - return nil -} - -// SetBaudRate sets the communication speed for I2C. -func (i2c I2C) SetBaudRate(br uint32) error { - // TODO: implement - return errI2CNotImplemented -} - -func (i2c I2C) Tx(addr uint16, w, r []byte) error { - // perform transmit transfer - if nil != w { - // generate start condition on bus - if result := i2c.start(addr, directionWrite); resultSuccess != result { - return errI2CSignalStartTimeout - } - // ensure TX FIFO is empty - if result := i2c.waitForTxEmpty(); resultSuccess != result { - return errI2CBusReadyTimeout - } - // check if communication was successful - if status := statusFlag(i2c.Bus.MSR.Get()); 0 != (status & statusNackDetect) { - return errI2CAckExpected - } - // send transmit data - if result := i2c.controllerTransmit(w); resultSuccess != result { - return errI2CWriteTimeout - } - } - - // perform receive transfer - if nil != r { - // generate (repeated-)start condition on bus - if result := i2c.start(addr, directionRead); resultSuccess != result { - return errI2CSignalStartTimeout - } - // read received data - if result := i2c.controllerReceive(r); resultSuccess != result { - return errI2CReadTimeout - } - } - - // generate stop condition on bus - if result := i2c.stop(); resultSuccess != result { - return errI2CSignalStopTimeout - } - - return nil -} - -// WriteRegisterEx transmits first the register and then the data to the -// peripheral device. -// -// Many I2C-compatible devices are organized in terms of registers. This method -// is a shortcut to easily write to such registers. Also, it only works for -// devices with 7-bit addresses, which is the vast majority. -func (i2c I2C) WriteRegisterEx(address uint8, register uint8, data []byte) error { - option := transferOption{ - flags: transferDefault, // transfer options bit mask (0 = normal transfer) - peripheral: uint16(address), // 7-bit peripheral address - direction: directionWrite, // directionRead or directionWrite - subaddress: uint16(register), // peripheral sub-address (transferred MSB first) - subaddressSize: 1, // byte length of sub-address (maximum = 4 bytes) - } - if result := i2c.controllerTransferPoll(option, data); resultSuccess != result { - return errI2CWriteTimeout - } - return nil -} - -// ReadRegisterEx transmits the register, restarts the connection as a read -// operation, and reads the response. -// -// Many I2C-compatible devices are organized in terms of registers. This method -// is a shortcut to easily read such registers. Also, it only works for devices -// with 7-bit addresses, which is the vast majority. -func (i2c I2C) ReadRegisterEx(address uint8, register uint8, data []byte) error { - option := transferOption{ - flags: transferDefault, // transfer options bit mask (0 = normal transfer) - peripheral: uint16(address), // 7-bit peripheral address - direction: directionRead, // directionRead or directionWrite - subaddress: uint16(register), // peripheral sub-address (transferred MSB first) - subaddressSize: 1, // byte length of sub-address (maximum = 4 bytes) - } - if result := i2c.controllerTransferPoll(option, data); resultSuccess != result { - return errI2CWriteTimeout - } - return nil -} - -func (i2c *I2C) reset(freq uint32) { - // disable interface - i2c.Bus.MCR.ClearBits(nxp.LPI2C_MCR_MEN) - - // software reset all interface registers - i2c.Bus.MCR.Set(nxp.LPI2C_MCR_RST) - - // RST remains set until manually cleared! - i2c.Bus.MCR.ClearBits(nxp.LPI2C_MCR_RST) - - // disable host request - i2c.Bus.MCFGR0.Set(0) - - // enable ACK, use I2C 2-pin open drain mode - i2c.Bus.MCFGR1.Set(0) - - // set FIFO watermarks (RX=1, TX=1) - mfcr := (uint32(0x1) << nxp.LPI2C_MFCR_RXWATER_Pos) & nxp.LPI2C_MFCR_RXWATER_Msk - mfcr |= (uint32(0x1) << nxp.LPI2C_MFCR_TXWATER_Pos) & nxp.LPI2C_MFCR_TXWATER_Msk - i2c.Bus.MFCR.Set(mfcr) - - // configure clock using receiver frequency - i2c.setFrequency(freq) - - // clear reset, and enable the interface - i2c.Bus.MCR.Set(nxp.LPI2C_MCR_MEN) - - // wait for the I2C bus to idle - for i2c.Bus.MSR.Get()&nxp.LPI2C_MSR_BBF != 0 { - } -} - -func (i2c *I2C) setFrequency(freq uint32) { - var ( - bestPre uint32 = 0 - bestClkHi uint32 = 0 - bestError uint32 = 0xFFFFFFFF - ) - - // disable interface - wasEnabled := i2c.Bus.MCR.HasBits(nxp.LPI2C_MCR_MEN) - i2c.Bus.MCR.ClearBits(nxp.LPI2C_MCR_MEN) - - // baud rate = (24MHz/(2^pre))/(CLKLO+1 + CLKHI+1 + FLOOR((2+FILTSCL)/(2^pre))) - // assume: CLKLO=2*CLKHI, SETHOLD=CLKHI, DATAVD=CLKHI/2 - for pre := uint32(1); pre <= 128; pre *= 2 { - if bestError == 0 { - break - } - for clkHi := uint32(1); clkHi < 32; clkHi++ { - var absError, rate uint32 - if clkHi == 1 { - rate = (24 * MHz / pre) / (1 + 3 + 2 + 2/pre) - } else { - rate = (24 * MHz / pre) / (3*clkHi + 2 + 2/pre) - } - if freq > rate { - absError = freq - rate - } else { - absError = rate - freq - } - if absError < bestError { - bestPre = pre - bestClkHi = clkHi - bestError = absError - // if the error is 0, then we can stop searching because we won't find a - // better match - if absError == 0 { - break - } - } - } - } - - var ( - clklo = func(n uint32) uint32 { return (n << nxp.LPI2C_MCCR0_CLKLO_Pos) & nxp.LPI2C_MCCR0_CLKLO_Msk } - clkhi = func(n uint32) uint32 { return (n << nxp.LPI2C_MCCR0_CLKHI_Pos) & nxp.LPI2C_MCCR0_CLKHI_Msk } - datavd = func(n uint32) uint32 { return (n << nxp.LPI2C_MCCR0_DATAVD_Pos) & nxp.LPI2C_MCCR0_DATAVD_Msk } - sethold = func(n uint32) uint32 { return (n << nxp.LPI2C_MCCR0_SETHOLD_Pos) & nxp.LPI2C_MCCR0_SETHOLD_Msk } - ) - // StandardMode, FastMode, FastModePlus, and UltraFastMode - mccr0 := clkhi(bestClkHi) - if bestClkHi < 2 { - mccr0 |= (clklo(3) | sethold(2) | datavd(1)) - } else { - mccr0 |= clklo(2*bestClkHi) | sethold(bestClkHi) | datavd(bestClkHi/2) - } - i2c.Bus.MCCR0.Set(mccr0) - i2c.Bus.MCCR1.Set(i2c.Bus.MCCR0.Get()) - - for i := uint32(0); i < 8; i++ { - if bestPre == (1 << i) { - bestPre = i - break - } - } - preMask := (bestPre << nxp.LPI2C_MCFGR1_PRESCALE_Pos) & nxp.LPI2C_MCFGR1_PRESCALE_Msk - i2c.Bus.MCFGR1.Set((i2c.Bus.MCFGR1.Get() & ^uint32(nxp.LPI2C_MCFGR1_PRESCALE_Msk)) | preMask) - - var ( - filtsda = func(n uint32) uint32 { return (n << nxp.LPI2C_MCFGR2_FILTSDA_Pos) & nxp.LPI2C_MCFGR2_FILTSDA_Msk } - filtscl = func(n uint32) uint32 { return (n << nxp.LPI2C_MCFGR2_FILTSCL_Pos) & nxp.LPI2C_MCFGR2_FILTSCL_Msk } - busidle = func(n uint32) uint32 { return (n << nxp.LPI2C_MCFGR2_BUSIDLE_Pos) & nxp.LPI2C_MCFGR2_BUSIDLE_Msk } - pinlow = func(n uint32) uint32 { return (n << nxp.LPI2C_MCFGR3_PINLOW_Pos) & nxp.LPI2C_MCFGR3_PINLOW_Msk } - - mcfgr2, mcfgr3 uint32 - ) - const i2cClockStretchTimeout = 15000 // microseconds - if freq >= 5*MHz { - // I2C UltraFastMode 5 MHz - mcfgr2 = 0 // disable glitch filters and timeout for UltraFastMode - mcfgr3 = 0 // - } else if freq >= 1*MHz { - // I2C FastModePlus 1 MHz - mcfgr2 = filtsda(1) | filtscl(1) | busidle(2400) // 100us timeout - mcfgr3 = pinlow(i2cClockStretchTimeout*24/256 + 1) - } else if freq >= 400*KHz { - // I2C FastMode 400 kHz - mcfgr2 = filtsda(2) | filtscl(2) | busidle(3600) // 150us timeout - mcfgr3 = pinlow(i2cClockStretchTimeout*24/256 + 1) - } else { - // I2C StandardMode 100 kHz - mcfgr2 = filtsda(5) | filtscl(5) | busidle(3000) // 250us timeout - mcfgr3 = pinlow(i2cClockStretchTimeout*12/256 + 1) - } - i2c.Bus.MCFGR2.Set(mcfgr2) - i2c.Bus.MCFGR3.Set(mcfgr3) - - // restore controller mode if it was enabled when called - if wasEnabled { - i2c.Bus.MCR.SetBits(nxp.LPI2C_MCR_MEN) - } -} - -// checkStatus converts the status register to a resultFlag for return, and -// clears any errors if present. -func (i2c *I2C) checkStatus(status statusFlag) resultFlag { - result := resultSuccess - // check for error. these errors cause a stop to be sent automatically. - // we must clear the errors before a new transfer can start. - if status &= statusError; 0 != status { - // select the correct error code ordered by severity, bus issues first. - if 0 != (status & statusPinLowTimeout) { - result = resultPinLowTimeout - } else if 0 != (status & statusArbitrationLost) { - result = resultArbitrationLost - } else if 0 != (status & statusNackDetect) { - result = resultNak - } else if 0 != (status & statusFifoErr) { - result = resultFifoError - } - // clear the flags - i2c.Bus.MSR.Set(uint32(status)) - // reset fifos. these flags clear automatically. - i2c.Bus.MCR.SetBits(nxp.LPI2C_MCR_RRF | nxp.LPI2C_MCR_RTF) - } - return result -} - -func (i2c *I2C) getFIFOSize() (rx, tx uint32) { return 4, 4 } -func (i2c *I2C) getFIFOCount() (rx, tx uint32) { - mfsr := i2c.Bus.MFSR.Get() - return (mfsr & nxp.LPI2C_MFSR_RXCOUNT_Msk) >> nxp.LPI2C_MFSR_RXCOUNT_Pos, - (mfsr & nxp.LPI2C_MFSR_TXCOUNT_Msk) >> nxp.LPI2C_MFSR_TXCOUNT_Pos -} - -func (i2c *I2C) waitForTxReady() resultFlag { - result := resultSuccess - _, txSize := i2c.getFIFOSize() - for { - _, txCount := i2c.getFIFOCount() - status := statusFlag(i2c.Bus.MSR.Get()) - if result = i2c.checkStatus(status); resultSuccess != result { - break - } - if txSize-txCount > 0 { - break - } - } - return result -} - -func (i2c *I2C) waitForTxEmpty() resultFlag { - result := resultSuccess - for { - _, txCount := i2c.getFIFOCount() - status := statusFlag(i2c.Bus.MSR.Get()) - if result = i2c.checkStatus(status); resultSuccess != result { - break - } - if 0 == txCount { - break - } - } - return result -} - -// isBusBusy checks if the I2C bus is busy, returning true if it is busy and we -// are not the ones driving it, otherwise false. -func (i2c *I2C) isBusBusy() bool { - status := statusFlag(i2c.Bus.MSR.Get()) - return (0 != (status & statusBusBusy)) && (0 == (status & statusBusy)) -} - -// start sends a START signal and peripheral address on the I2C bus. -// -// This function is used to initiate a new controller mode transfer. First, the -// bus state is checked to ensure that another controller is not occupying the -// bus. Then a START signal is transmitted, followed by the 7-bit peripheral -// address. Note that this function does not actually wait until the START and -// address are successfully sent on the bus before returning. -func (i2c *I2C) start(address uint16, dir i2cDirection) resultFlag { - // return an error if the bus is already in use by another controller - if i2c.isBusBusy() { - return resultBusy - } - // clear all flags - i2c.Bus.MSR.Set(uint32(statusClear)) - // turn off auto-stop - i2c.Bus.MCFGR1.ClearBits(nxp.LPI2C_MCFGR1_AUTOSTOP) - // wait until there is room in the FIFO - if result := i2c.waitForTxReady(); resultSuccess != result { - return result - } - - // issue start command - i2c.Bus.MTDR.Set(uint32(commandStart) | dir.shift(address)) - return resultSuccess -} - -// stop sends a STOP signal on the I2C bus. -// -// This function does not return until the STOP signal is seen on the bus, or -// an error occurs. -func (i2c *I2C) stop() resultFlag { - const tryMax = 0 // keep waiting forever - // wait until there is room in the FIFO - result := i2c.waitForTxReady() - if resultSuccess != result { - return result - } - // send the STOP signal - i2c.Bus.MTDR.Set(uint32(commandStop)) - // wait for the stop detected flag to set, indicating the transfer has - // completed on the bus. also check for errors while waiting. - try := 0 - for resultSuccess == result && (0 == tryMax || try < tryMax) { - status := statusFlag(i2c.Bus.MSR.Get()) - result = i2c.checkStatus(status) - if (0 != (status & statusStopDetect)) && (0 != (status & statusTxReady)) { - i2c.Bus.MSR.Set(uint32(statusStopDetect)) - break - } - try++ - } - if 0 != tryMax && try >= tryMax { - return resultTimeout - } - return result -} - -// controllerReceive performs a polling receive transfer on the I2C bus. -func (i2c *I2C) controllerReceive(rxBuffer []byte) resultFlag { - const tryMax = 0 // keep trying forever - rxSize := len(rxBuffer) - if rxSize == 0 { - return resultSuccess - } - // wait until there is room in the FIFO - result := i2c.waitForTxReady() - if resultSuccess != result { - return result - } - sizeMask := (uint32(rxSize-1) << nxp.LPI2C_MTDR_DATA_Pos) & nxp.LPI2C_MTDR_DATA_Msk - i2c.Bus.MTDR.Set(uint32(commandRxData) | sizeMask) - - // receive data - for rxSize > 0 { - // read LPI2C receive FIFO register. the register includes a flag to - // indicate whether the FIFO is empty, so we can both get the data and check - // if we need to keep reading using a single register read. - var data uint32 - try := 0 - for 0 == tryMax || try < tryMax { - // check for errors on the bus - status := statusFlag(i2c.Bus.MSR.Get()) - result = i2c.checkStatus(status) - if resultSuccess != result { - return result - } - // read received data, break if FIFO was non-empty - data = i2c.Bus.MRDR.Get() - if 0 == (data & nxp.LPI2C_MRDR_RXEMPTY_Msk) { - break - } - try++ - } - // ensure we didn't timeout waiting for data - if 0 != tryMax && try >= tryMax { - return resultTimeout - } - // copy data to RX buffer - rxBuffer[len(rxBuffer)-rxSize] = byte(data & nxp.LPI2C_MRDR_DATA_Msk) - rxSize-- - } - return result -} - -// controllerTransmit performs a polling transmit transfer on the I2C bus. -func (i2c *I2C) controllerTransmit(txBuffer []byte) resultFlag { - txSize := len(txBuffer) - for txSize > 0 { - // wait until there is room in the FIFO - result := i2c.waitForTxReady() - if resultSuccess != result { - return result - } - // write byte into LPI2C data register - i2c.Bus.MTDR.Set(uint32(txBuffer[len(txBuffer)-txSize] & nxp.LPI2C_MTDR_DATA_Msk)) - txSize-- - } - return resultSuccess -} - -type transferOption struct { - flags transferFlag // transfer options bit mask (0 = normal transfer) - peripheral uint16 // 7-bit peripheral address - direction i2cDirection // directionRead or directionWrite - subaddress uint16 // peripheral sub-address (transferred MSB first) - subaddressSize uint16 // byte length of sub-address (maximum = 4 bytes) -} - -func (i2c *I2C) controllerTransferPoll(option transferOption, data []byte) resultFlag { - // return an error if the bus is already in use by another controller - if i2c.isBusBusy() { - return resultBusy - } - // clear all flags - i2c.Bus.MSR.Set(uint32(statusClear)) - // turn off auto-stop - i2c.Bus.MCFGR1.ClearBits(nxp.LPI2C_MCFGR1_AUTOSTOP) - - cmd := make([]uint16, 0, 7) - size := len(data) - - direction := option.direction - if option.subaddressSize > 0 { - direction = directionWrite - } - // peripheral address - if 0 == (option.flags & transferNoStart) { - addr := direction.shift(option.peripheral) - cmd = append(cmd, uint16(uint32(commandStart)|addr)) - } - // sub-address (MSB-first) - rem := option.subaddressSize - for rem > 0 { - rem-- - cmd = append(cmd, (option.subaddress>>(8*rem))&0xFF) - } - // need to send repeated start if switching directions to read - if (0 != size) && (directionRead == option.direction) { - if directionWrite == direction { - addr := directionRead.shift(option.peripheral) - cmd = append(cmd, uint16(uint32(commandStart)|addr)) - } - } - // send command buffer - result := resultSuccess - for _, c := range cmd { - // wait until there is room in the FIFO - if result = i2c.waitForTxReady(); resultSuccess != result { - return result - } - // write byte into LPI2C controller data register - i2c.Bus.MTDR.Set(uint32(c)) - } - // send data - if option.direction == directionWrite && size > 0 { - result = i2c.controllerTransmit(data) - } - // receive data - if option.direction == directionRead && size > 0 { - result = i2c.controllerReceive(data) - } - if resultSuccess != result { - return result - } - if 0 == (option.flags & transferNoStop) { - result = i2c.stop() - } - return result -} diff --git a/emb/machine/machine_mimxrt1062_spi.go b/emb/machine/machine_mimxrt1062_spi.go deleted file mode 100644 index d982eea..0000000 --- a/emb/machine/machine_mimxrt1062_spi.go +++ /dev/null @@ -1,254 +0,0 @@ -//go:build mimxrt1062 - -package machine - -// SPI peripheral abstraction layer for the MIMXRT1062 - -import ( - "device/nxp" - "errors" - "unsafe" -) - -// SPIConfig is used to store config info for SPI. -type SPIConfig struct { - Frequency uint32 - SDI Pin - SDO Pin - SCK Pin - CS Pin - LSBFirst bool - Mode uint8 -} - -func (c SPIConfig) getPins() (di, do, ck, cs Pin) { - if 0 == c.SDI && 0 == c.SDO && 0 == c.SCK && 0 == c.CS { - // default pins if none specified - return SPI_SDI_PIN, SPI_SDO_PIN, SPI_SCK_PIN, SPI_CS_PIN - } - return c.SDI, c.SDO, c.SCK, c.CS -} - -type SPI struct { - Bus *nxp.LPSPI_Type - - // these hold the input selector ("daisy chain") values that select which pins - // are connected to the LPSPI device, and should be defined where the SPI - // instance is declared (e.g., in the board definition). see the godoc - // comments on type muxSelect for more details. - muxSDI, muxSDO, muxSCK, muxCS muxSelect - - // these are copied from SPIConfig, during (*SPI).Configure(SPIConfig), and - // should be considered read-only for internal reference (i.e., modifying them - // will have no desirable effect). - sdi, sdo, sck, cs Pin - frequency uint32 - - // auxiliary state data used internally - configured bool -} - -const ( - statusTxDataRequest = nxp.LPSPI_SR_TDF // Transmit data flag - statusRxDataReady = nxp.LPSPI_SR_RDF // Receive data flag - statusWordComplete = nxp.LPSPI_SR_WCF // Word Complete flag - statusFrameComplete = nxp.LPSPI_SR_FCF // Frame Complete flag - statusTransferComplete = nxp.LPSPI_SR_TCF // Transfer Complete flag - statusTransmitError = nxp.LPSPI_SR_TEF // Transmit Error flag (FIFO underrun) - statusReceiveError = nxp.LPSPI_SR_REF // Receive Error flag (FIFO overrun) - statusDataMatch = nxp.LPSPI_SR_DMF // Data Match flag - statusModuleBusy = nxp.LPSPI_SR_MBF // Module Busy flag - statusAll = nxp.LPSPI_SR_TDF | nxp.LPSPI_SR_RDF | - nxp.LPSPI_SR_WCF | nxp.LPSPI_SR_FCF | nxp.LPSPI_SR_TCF | nxp.LPSPI_SR_TEF | - nxp.LPSPI_SR_REF | nxp.LPSPI_SR_DMF | nxp.LPSPI_SR_MBF -) - -var ( - errSPINotConfigured = errors.New("SPI interface is not yet configured") -) - -// Configure is intended to setup an SPI interface for transmit/receive. -func (spi *SPI) Configure(config SPIConfig) error { - - const defaultSpiFreq = 4000000 // 4 MHz - - // init pins - spi.sdi, spi.sdo, spi.sck, spi.cs = config.getPins() - - // configure the mux and pad control registers - spi.sdi.Configure(PinConfig{Mode: PinModeSPISDI}) - spi.sdo.Configure(PinConfig{Mode: PinModeSPISDO}) - spi.sck.Configure(PinConfig{Mode: PinModeSPICLK}) - spi.cs.Configure(PinConfig{Mode: PinModeSPICS}) - - // configure the mux input selector - spi.muxSDI.connect() - spi.muxSDO.connect() - spi.muxSCK.connect() - spi.muxCS.connect() - - // software reset of LPSPI state registers - spi.Bus.CR.SetBits(nxp.LPSPI_CR_RST) - // also reset FIFOs (not performed by software reset above) - spi.Bus.CR.SetBits(nxp.LPSPI_CR_RRF | nxp.LPSPI_CR_RTF) - spi.Bus.CR.Set(0) - - // set controller mode, and input data is sampled on delayed SCK edge - spi.Bus.CFGR1.Set(nxp.LPSPI_CFGR1_MASTER | nxp.LPSPI_CFGR1_SAMPLE) - - spi.frequency = config.Frequency - if 0 == spi.frequency { - spi.frequency = defaultSpiFreq - } - - // configure LPSPI clock divisor and CS assertion delays - div := spi.getClockDivisor(config.Frequency) - ccr := (div << nxp.LPSPI_CCR_SCKDIV_Pos) & nxp.LPSPI_CCR_SCKDIV_Msk - ccr |= ((div / 2) << nxp.LPSPI_CCR_DBT_Pos) & nxp.LPSPI_CCR_DBT_Msk - ccr |= ((div / 2) << nxp.LPSPI_CCR_PCSSCK_Pos) & nxp.LPSPI_CCR_PCSSCK_Msk - spi.Bus.CCR.Set(ccr) - - // 8-bit frame size (words) - tcr := uint32(7) - if config.LSBFirst { - tcr |= nxp.LPSPI_TCR_LSBF - } - // set polarity and phase - switch config.Mode { - case Mode1: - tcr |= nxp.LPSPI_TCR_CPHA - case Mode2: - tcr |= nxp.LPSPI_TCR_CPOL - case Mode3: - tcr |= nxp.LPSPI_TCR_CPOL - tcr |= nxp.LPSPI_TCR_CPHA - } - spi.Bus.TCR.Set(tcr) - - // clear FIFO water marks - spi.setWatermark(0, 0) - - // enable LPSPI module - spi.Bus.CR.Set(nxp.LPSPI_CR_MEN) - - spi.configured = true - - return nil -} - -// Transfer writes/reads a single byte using the SPI interface. -func (spi *SPI) Transfer(w byte) (byte, error) { - if !spi.configured { - return 0, errSPINotConfigured - } - - const readTryMax = 10000 - - for spi.Bus.SR.HasBits(statusModuleBusy) { - } // wait for SPI busy bit to clear - - _, txFIFOSize := spi.getFIFOSize() - - spi.flushFIFO(true, true) - spi.Bus.SR.Set(statusAll) // clear all status flags (W1C) - - // enable LPSPI module - spi.Bus.CR.Set(nxp.LPSPI_CR_MEN) - - // TODO: unnecessary since we just flushed the FIFO? - for { // wait for TX FIFO to not be full - if _, txFIFO := spi.getFIFOCount(); txFIFO < txFIFOSize { - break - } - } - - // write out byte to TX FIFO - spi.Bus.TDR.Set(uint32(w)) - - // try to read from RX FIFO if anything exists - didRead := false - data := byte(0) - for i := 0; !didRead && (i < readTryMax); i++ { - rxFIFO, _ := spi.getFIFOCount() - didRead = rxFIFO > 0 - if didRead { - data = byte(spi.Bus.RDR.Get()) - } - } - - // if nothing was read, then wait for transfer complete flag to decide when - // we are finished - if !didRead { - for !spi.Bus.SR.HasBits(nxp.LPSPI_SR_TCF) { - } // wait for all transfers complete flag to set - } - - return data, nil -} - -func (spi *SPI) isHardwareCSPin(pin Pin) bool { - switch unsafe.Pointer(spi.Bus) { - case unsafe.Pointer(nxp.LPSPI1): - return SPI1_CS_PIN == pin - case unsafe.Pointer(nxp.LPSPI2): - return SPI2_CS_PIN == pin - case unsafe.Pointer(nxp.LPSPI3): - return SPI3_CS_PIN == pin - } - return false -} - -func (spi *SPI) hasHardwareCSPin() bool { - return spi.isHardwareCSPin(spi.cs) -} - -// getClockDivisor finds the SPI prescalar that minimizes the error between -// requested frequency and possible frequencies available with the LPSPI clock. -// this routine is based on Teensyduino (libraries/SPI/SPI.cpp): -// -// void SPIClass::setClockDivider_noInline(uint32_t clk) -func (spi *SPI) getClockDivisor(freq uint32) uint32 { - const clock = 132000000 // LPSPI root clock frequency (PLL2) - d := uint32(clock) - if freq > 0 { - d /= freq - } - if d > 0 && clock/d > freq { - d++ - } - if d > 257 { - return 255 - } - if d > 2 { - return d - 2 - } - return 0 -} - -func (spi *SPI) getFIFOSize() (rx, tx uint32) { - param := spi.Bus.PARAM.Get() - return uint32(1) << ((param & nxp.LPSPI_PARAM_RXFIFO_Msk) >> nxp.LPSPI_PARAM_RXFIFO_Pos), - uint32(1) << ((param & nxp.LPSPI_PARAM_TXFIFO_Msk) >> nxp.LPSPI_PARAM_TXFIFO_Pos) -} - -func (spi *SPI) getFIFOCount() (rx, tx uint32) { - fsr := spi.Bus.FSR.Get() - return (fsr & nxp.LPSPI_FSR_RXCOUNT_Msk) >> nxp.LPSPI_FSR_RXCOUNT_Pos, - (fsr & nxp.LPSPI_FSR_TXCOUNT_Msk) >> nxp.LPSPI_FSR_TXCOUNT_Pos -} - -func (spi *SPI) flushFIFO(rx, tx bool) { - var flush uint32 - if rx { - flush |= nxp.LPSPI_CR_RRF - } - if tx { - flush |= nxp.LPSPI_CR_RTF - } - spi.Bus.CR.SetBits(flush) -} - -func (spi *SPI) setWatermark(rx, tx uint32) { - spi.Bus.FCR.Set(((rx << nxp.LPSPI_FCR_RXWATER_Pos) & nxp.LPSPI_FCR_RXWATER_Msk) | - ((tx << nxp.LPSPI_FCR_TXWATER_Pos) & nxp.LPSPI_FCR_TXWATER_Msk)) -} diff --git a/emb/machine/machine_mimxrt1062_uart.go b/emb/machine/machine_mimxrt1062_uart.go deleted file mode 100644 index 6265b85..0000000 --- a/emb/machine/machine_mimxrt1062_uart.go +++ /dev/null @@ -1,303 +0,0 @@ -//go:build mimxrt1062 - -package machine - -import ( - "device/nxp" - "runtime/interrupt" - "runtime/volatile" -) - -// UART peripheral abstraction layer for the MIMXRT1062 - -type UART struct { - Bus *nxp.LPUART_Type - Buffer *RingBuffer - Interrupt interrupt.Interrupt - - // txBuffer should be allocated globally (such as when UART is created) to - // prevent it being reclaimed or cleaned up prematurely. - txBuffer *RingBuffer - - // these hold the input selector ("daisy chain") values that select which pins - // are connected to the LPUART device, and should be defined where the UART - // instance is declared. see the godoc comments on type muxSelect for more - // details. - muxRX, muxTX muxSelect - - // these are copied from UARTConfig, during (*UART).Configure(UARTConfig), and - // should be considered read-only for internal reference (i.e., modifying them - // will have no desirable effect). - rx, tx Pin - baud uint32 - - // auxiliary state data used internally - configured bool - transmitting volatile.Register32 -} - -func (uart *UART) isTransmitting() bool { return uart.transmitting.Get() != 0 } -func (uart *UART) startTransmitting() { uart.transmitting.Set(1) } -func (uart *UART) stopTransmitting() { uart.transmitting.Set(0) } -func (uart *UART) resetTransmitting() { - uart.stopTransmitting() - uart.Bus.GLOBAL.SetBits(nxp.LPUART_GLOBAL_RST) - uart.Bus.GLOBAL.ClearBits(nxp.LPUART_GLOBAL_RST) -} - -// Configure initializes a UART with the given UARTConfig and other default -// settings. -func (uart *UART) Configure(config UARTConfig) { - - const defaultUartFreq = 115200 - - // use default baud rate if not specified - if config.BaudRate == 0 { - config.BaudRate = defaultUartFreq - } - - // use default UART pins if not specified - if config.RX == 0 && config.TX == 0 { - config.RX = UART_RX_PIN - config.TX = UART_TX_PIN - } - - uart.baud = config.BaudRate - uart.rx = config.RX - uart.tx = config.TX - - // configure the mux and pad control registers - uart.rx.Configure(PinConfig{Mode: PinModeUARTRX}) - uart.tx.Configure(PinConfig{Mode: PinModeUARTTX}) - - // configure the mux input selector - uart.muxRX.connect() - uart.muxTX.connect() - - // reset all internal logic and registers - uart.resetTransmitting() - - // disable until we have finished configuring registers - uart.Bus.CTRL.Set(0) - - // determine the baud rate and over-sample divisors - sbr, osr := uart.getBaudRateDivisor(uart.baud) - - // set the baud rate, over-sample configuration, stop bits - baudBits := (((osr - 1) << nxp.LPUART_BAUD_OSR_Pos) & nxp.LPUART_BAUD_OSR_Msk) | - ((sbr << nxp.LPUART_BAUD_SBR_Pos) & nxp.LPUART_BAUD_SBR_Msk) - if osr <= 8 { - // if OSR less than or equal to 8, we must enable sampling on both edges - baudBits |= nxp.LPUART_BAUD_BOTHEDGE - } - uart.Bus.BAUD.Set(baudBits) - uart.Bus.PINCFG.Set(0) // disable triggers - - // configure watermarks, flush and enable TX/RX FIFOs - rxSize, txSize := uart.getFIFOSize() - rxWater := rxSize >> 1 - if rxWater > uint32(nxp.LPUART_FIFO_RXFIFOSIZE_Msk>>nxp.LPUART_FIFO_RXFIFOSIZE_Pos) { - rxWater = uint32(nxp.LPUART_FIFO_RXFIFOSIZE_Msk >> nxp.LPUART_FIFO_RXFIFOSIZE_Pos) - } - txWater := txSize >> 1 - if txWater > uint32(nxp.LPUART_FIFO_TXFIFOSIZE_Msk>>nxp.LPUART_FIFO_TXFIFOSIZE_Pos) { - txWater = uint32(nxp.LPUART_FIFO_TXFIFOSIZE_Msk >> nxp.LPUART_FIFO_TXFIFOSIZE_Pos) - } - uart.Bus.WATER.Set( - ((rxWater << nxp.LPUART_WATER_RXWATER_Pos) & nxp.LPUART_WATER_RXWATER_Msk) | - ((txWater << nxp.LPUART_WATER_TXWATER_Pos) & nxp.LPUART_WATER_TXWATER_Msk)) - uart.Bus.FIFO.SetBits(nxp.LPUART_FIFO_RXFE | nxp.LPUART_FIFO_TXFE | - nxp.LPUART_FIFO_RXFLUSH | nxp.LPUART_FIFO_TXFLUSH) - - // for now we assume some configuration. in particular: - // Data bits -> 8-bit - // Parity bit -> None (parity bit generation disabled) - // Stop bits -> 1 stop bit - // MSB first -> false - // RX idle type -> idle count starts after start bit - // RX idle config -> 1 idle character - // RX RTS enabled -> false - // TX CTS enabled -> false - - // enable transmitter, receiver functions - uart.Bus.CTRL.Set(nxp.LPUART_CTRL_TE | nxp.LPUART_CTRL_RE | - // enable receiver, idle line interrupts - nxp.LPUART_CTRL_RIE | nxp.LPUART_CTRL_ILIE) - - // clear all status flags - uart.Bus.STAT.Set(uart.Bus.STAT.Get()) - - // enable RX interrupt - uart.Interrupt.SetPriority(0xC0) - uart.Interrupt.Enable() - - uart.configured = true -} - -// Disable disables the UART interface. -// -// If any buffered data has not yet been transmitted, Disable waits until -// transmission completes before disabling the interface. The receiver UART's -// interrupt is also disabled, and the RX/TX pins are reconfigured for GPIO -// input (pull-up). -func (uart *UART) Disable() { - - // first ensure the device is enabled - if uart.configured { - - // wait for any buffered data to send - uart.Sync() - - // stop trapping RX interrupts - uart.Interrupt.Disable() - - // reset all internal registers - uart.resetTransmitting() - - // disable RX/TX functions - uart.Bus.CTRL.ClearBits(nxp.LPUART_CTRL_TE | nxp.LPUART_CTRL_RE) - - // put pins back into GPIO mode - uart.rx.Configure(PinConfig{Mode: PinInputPullup}) - uart.tx.Configure(PinConfig{Mode: PinInputPullup}) - } - uart.configured = false -} - -// Sync blocks the calling goroutine until all data in the output buffer has -// been transmitted. -func (uart *UART) Sync() error { - for uart.isTransmitting() { - } - return nil -} - -// WriteByte writes a single byte of data to the UART interface. -func (uart *UART) writeByte(c byte) error { - uart.startTransmitting() - for !uart.txBuffer.Put(c) { - } - uart.Bus.CTRL.SetBits(nxp.LPUART_CTRL_TIE) - return nil -} - -func (uart *UART) flush() {} - -// getBaudRateDivisor finds the greatest over-sampling factor (4..32) and -// corresponding baud rate divisor (1..8191) that best partition a given baud -// rate into equal intervals. -// -// This is an integral (non-floating point) translation of the logic at the -// beginning of: -// -// void HardwareSerial::begin(uint32_t baud, uint16_t format) -// -// (from Teensyduino: cores/teensy4/HardwareSerial.cpp) -// -// We don't want to use floating point here in case it gets called from an ISR -// or very early during system init. -func (uart *UART) getBaudRateDivisor(baudRate uint32) (sbr uint32, osr uint32) { - const clock = 24000000 // UART is muxed to 24 MHz OSC - err := uint32(0xFFFFFFFF) - sbr, osr = 0, 0 - for o := uint32(4); o <= 32; o++ { - s := ((clock*10)/(baudRate*o) + 5) / 10 - if s == 0 { - s = 1 - } - b := clock / (s * o) - var e uint32 - if b > baudRate { - e = b - baudRate - } else { - e = baudRate - b - } - if e <= err { - err = e - osr = o - sbr = s - } - } - return sbr, osr -} - -func (uart *UART) getFIFOSize() (rx, tx uint32) { - fifo := uart.Bus.FIFO.Get() - rx = uint32(1) << ((fifo & nxp.LPUART_FIFO_RXFIFOSIZE_Msk) >> nxp.LPUART_FIFO_RXFIFOSIZE_Pos) - if rx > 1 { - rx <<= 1 - } - tx = uint32(1) << ((fifo & nxp.LPUART_FIFO_TXFIFOSIZE_Msk) >> nxp.LPUART_FIFO_TXFIFOSIZE_Pos) - if tx > 1 { - tx <<= 1 - } - return rx, tx -} - -func (uart *UART) getStatus() uint32 { - return uart.Bus.STAT.Get() | - ((uart.Bus.FIFO.Get() & uint32(nxp.LPUART_FIFO_TXEMPT_Msk|nxp.LPUART_FIFO_RXEMPT_Msk| - nxp.LPUART_FIFO_TXOF_Msk|nxp.LPUART_FIFO_RXUF_Msk)) >> 16) -} - -func (uart *UART) getEnabledInterrupts() uint32 { - return ((uart.Bus.BAUD.Get() & uint32(nxp.LPUART_BAUD_LBKDIE_Msk|nxp.LPUART_BAUD_RXEDGIE_Msk)) >> 8) | - ((uart.Bus.FIFO.Get() & uint32(nxp.LPUART_FIFO_TXOFE_Msk|nxp.LPUART_FIFO_RXUFE_Msk)) >> 8) | - (uart.Bus.CTRL.Get() & uint32(0xFF0C000)) -} - -func (uart *UART) disableInterrupts(mask uint32) { - uart.Bus.BAUD.ClearBits((mask << 8) & uint32(nxp.LPUART_BAUD_LBKDIE_Msk|nxp.LPUART_BAUD_RXEDGIE_Msk)) - uart.Bus.FIFO.Set((uart.Bus.FIFO.Get() & ^uint32(nxp.LPUART_FIFO_TXOF_Msk|nxp.LPUART_FIFO_RXUF_Msk)) & - ^uint32((mask<<8)&(nxp.LPUART_FIFO_TXOFE_Msk|nxp.LPUART_FIFO_RXUFE_Msk))) - mask &= uint32(0xFFFFFF00) - uart.Bus.CTRL.ClearBits(mask) -} - -func (uart *UART) handleInterrupt(interrupt.Interrupt) { - - stat := uart.getStatus() - inte := uart.getEnabledInterrupts() - - _, txSize := uart.getFIFOSize() - - // check for and clear overrun, otherwise RX will not work - if (stat & uint32(nxp.LPUART_STAT_OR)) != 0 { - uart.Bus.STAT.Set((uart.Bus.STAT.Get() & uint32(0x3FE00000)) | nxp.LPUART_STAT_OR) - } - - // idle or receive data register is full - if (stat & uint32(nxp.LPUART_STAT_RDRF|nxp.LPUART_STAT_IDLE)) != 0 { - count := (uart.Bus.WATER.Get() & uint32(nxp.LPUART_WATER_RXCOUNT_Msk)) >> nxp.LPUART_WATER_RXCOUNT_Pos - for ; count > 0; count-- { - // read up to 8 bits of data at a time - // TODO: 7, 9, and 10-bit support? - uart.Buffer.Put(uint8(uart.Bus.DATA.Get() & uint32(0xFF))) - } - // if it was an IDLE status, clear the flag - if (stat & uint32(nxp.LPUART_STAT_IDLE)) != 0 { - uart.Bus.STAT.SetBits(nxp.LPUART_STAT_IDLE) - } - // disable idle line interrupts - uart.disableInterrupts(nxp.LPUART_CTRL_RIE | nxp.LPUART_CTRL_ORIE) - } - - // check if we have data to write - if ((inte & nxp.LPUART_CTRL_TIE) != 0) && ((stat & nxp.LPUART_STAT_TDRE) != 0) { - for ((uart.Bus.WATER.Get() & uint32(nxp.LPUART_WATER_TXCOUNT_Msk)) >> nxp.LPUART_WATER_TXCOUNT_Pos) < txSize { - if b, ok := uart.txBuffer.Get(); ok { - uart.Bus.DATA.Set(uint32(b)) - } else { - break - } - } - if uart.Bus.STAT.HasBits(nxp.LPUART_STAT_TDRE) { - uart.Bus.CTRL.Set((uart.Bus.CTRL.Get() & ^uint32(nxp.LPUART_CTRL_TIE)) | nxp.LPUART_CTRL_TCIE) - } - } - - if ((inte & nxp.LPUART_CTRL_TCIE) != 0) && ((stat & nxp.LPUART_STAT_TC) != 0) { - uart.stopTransmitting() - uart.Bus.CTRL.ClearBits(nxp.LPUART_CTRL_TCIE) - } -} diff --git a/emb/machine/machine_nrf.go b/emb/machine/machine_nrf.go deleted file mode 100644 index d6d6349..0000000 --- a/emb/machine/machine_nrf.go +++ /dev/null @@ -1,449 +0,0 @@ -//go:build nrf - -package machine - -import ( - "device/nrf" - "internal/binary" - "runtime/interrupt" - "unsafe" -) - -const deviceName = nrf.Device - -var deviceID [8]byte - -// DeviceID returns an identifier that is unique within -// a particular chipset. -// -// The identity is one burnt into the MCU itself, or the -// flash chip at time of manufacture. -// -// It's possible that two different vendors may allocate -// the same DeviceID, so callers should take this into -// account if needing to generate a globally unique id. -// -// The length of the hardware ID is vendor-specific, but -// 8 bytes (64 bits) is common. -func DeviceID() []byte { - words := make([]uint32, 2) - words[0] = nrf.FICR.DEVICEID[0].Get() - words[1] = nrf.FICR.DEVICEID[1].Get() - - for i := 0; i < 8; i++ { - shift := (i % 4) * 8 - w := i / 4 - deviceID[i] = byte(words[w] >> shift) - } - - return deviceID[:] -} - -const ( - PinInput PinMode = (nrf.GPIO_PIN_CNF_DIR_Input << nrf.GPIO_PIN_CNF_DIR_Pos) | (nrf.GPIO_PIN_CNF_INPUT_Connect << nrf.GPIO_PIN_CNF_INPUT_Pos) - PinInputPullup PinMode = PinInput | (nrf.GPIO_PIN_CNF_PULL_Pullup << nrf.GPIO_PIN_CNF_PULL_Pos) - PinInputPulldown PinMode = PinInput | (nrf.GPIO_PIN_CNF_PULL_Pulldown << nrf.GPIO_PIN_CNF_PULL_Pos) - PinOutput PinMode = (nrf.GPIO_PIN_CNF_DIR_Output << nrf.GPIO_PIN_CNF_DIR_Pos) | (nrf.GPIO_PIN_CNF_INPUT_Connect << nrf.GPIO_PIN_CNF_INPUT_Pos) -) - -type PinChange uint8 - -// Pin change interrupt constants for SetInterrupt. -const ( - PinRising PinChange = nrf.GPIOTE_CONFIG_POLARITY_LoToHi - PinFalling PinChange = nrf.GPIOTE_CONFIG_POLARITY_HiToLo - PinToggle PinChange = nrf.GPIOTE_CONFIG_POLARITY_Toggle -) - -// Callbacks to be called for pins configured with SetInterrupt. -var pinCallbacks [len(nrf.GPIOTE.CONFIG)]func(Pin) - -// Configure this pin with the given configuration. -func (p Pin) Configure(config PinConfig) { - cfg := config.Mode | nrf.GPIO_PIN_CNF_DRIVE_S0S1 | nrf.GPIO_PIN_CNF_SENSE_Disabled - port, pin := p.getPortPin() - port.PIN_CNF[pin].Set(uint32(cfg)) -} - -// Set the pin to high or low. -// Warning: only use this on an output pin! -func (p Pin) Set(high bool) { - port, pin := p.getPortPin() - if high { - port.OUTSET.Set(1 << pin) - } else { - port.OUTCLR.Set(1 << pin) - } -} - -// Return the register and mask to enable a given GPIO pin. This can be used to -// implement bit-banged drivers. -func (p Pin) PortMaskSet() (*uint32, uint32) { - port, pin := p.getPortPin() - return &port.OUTSET.Reg, 1 << pin -} - -// Return the register and mask to disable a given port. This can be used to -// implement bit-banged drivers. -func (p Pin) PortMaskClear() (*uint32, uint32) { - port, pin := p.getPortPin() - return &port.OUTCLR.Reg, 1 << pin -} - -// Get returns the current value of a GPIO pin when the pin is configured as an -// input or as an output. -func (p Pin) Get() bool { - port, pin := p.getPortPin() - return (port.IN.Get()>>pin)&1 != 0 -} - -// SetInterrupt sets an interrupt to be executed when a particular pin changes -// state. The pin should already be configured as an input, including a pull up -// or down if no external pull is provided. -// -// This call will replace a previously set callback on this pin. You can pass a -// nil func to unset the pin change interrupt. If you do so, the change -// parameter is ignored and can be set to any value (such as 0). -func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error { - // Some variables to easily check whether a channel was already configured - // as an event channel for the given pin. - // This is not just an optimization, this is required: the datasheet says - // that configuring more than one channel for a given pin results in - // unpredictable behavior. - expectedConfigMask := uint32(nrf.GPIOTE_CONFIG_MODE_Msk | nrf.GPIOTE_CONFIG_PSEL_Msk) - expectedConfig := nrf.GPIOTE_CONFIG_MODE_Event<> nrf.GPIOTE_CONFIG_PSEL_Pos) - pinCallbacks[i](pin) - } - } - }).Enable() - - // Everything was configured correctly. - return nil -} - -// UART on the NRF. -type UART struct { - Buffer *RingBuffer -} - -// UART -var ( - // UART0 is the hardware UART on the NRF SoC. - _UART0 = UART{Buffer: NewRingBuffer()} - UART0 = &_UART0 -) - -// Configure the UART. -func (uart *UART) Configure(config UARTConfig) { - // Default baud rate to 115200. - if config.BaudRate == 0 { - config.BaudRate = 115200 - } - - uart.SetBaudRate(config.BaudRate) - - // Set TX and RX pins - if config.TX == 0 && config.RX == 0 { - // Use default pins - uart.setPins(UART_TX_PIN, UART_RX_PIN) - } else { - uart.setPins(config.TX, config.RX) - } - - nrf.UART0.ENABLE.Set(nrf.UART_ENABLE_ENABLE_Enabled) - nrf.UART0.TASKS_STARTTX.Set(1) - nrf.UART0.TASKS_STARTRX.Set(1) - nrf.UART0.INTENSET.Set(nrf.UART_INTENSET_RXDRDY_Msk) - - // Enable RX IRQ. - intr := interrupt.New(nrf.IRQ_UART0, _UART0.handleInterrupt) - intr.SetPriority(0xc0) // low priority - intr.Enable() -} - -// SetBaudRate sets the communication speed for the UART. -func (uart *UART) SetBaudRate(br uint32) { - // Magic: calculate 'baudrate' register from the input number. - // Every value listed in the datasheet will be converted to the - // correct register value, except for 192600. I suspect the value - // listed in the nrf52 datasheet (0x0EBED000) is incorrectly rounded - // and should be 0x0EBEE000, as the nrf51 datasheet lists the - // nonrounded value 0x0EBEDFA4. - // Some background: - // https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values/2046#2046 - rate := uint32((uint64(br/400)*uint64(400*0xffffffff/16000000) + 0x800) & 0xffffff000) - - nrf.UART0.BAUDRATE.Set(rate) -} - -// WriteByte writes a byte of data to the UART. -func (uart *UART) writeByte(c byte) error { - nrf.UART0.EVENTS_TXDRDY.Set(0) - nrf.UART0.TXD.Set(uint32(c)) - for nrf.UART0.EVENTS_TXDRDY.Get() == 0 { - } - return nil -} - -func (uart *UART) flush() {} - -func (uart *UART) handleInterrupt(interrupt.Interrupt) { - if nrf.UART0.EVENTS_RXDRDY.Get() != 0 { - uart.Receive(byte(nrf.UART0.RXD.Get())) - nrf.UART0.EVENTS_RXDRDY.Set(0x0) - } -} - -const i2cTimeout = 0xffff // this is around 29ms on a nrf52 - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 - SCL Pin - SDA Pin - Mode I2CMode -} - -// Configure is intended to setup the I2C interface. -func (i2c *I2C) Configure(config I2CConfig) error { - - i2c.disable() - - // Default I2C bus speed is 100 kHz. - if config.Frequency == 0 { - config.Frequency = 100 * KHz - } - // Default I2C pins if not set. - if config.SDA == 0 && config.SCL == 0 { - config.SDA = SDA_PIN - config.SCL = SCL_PIN - } - - // do config - sclPort, sclPin := config.SCL.getPortPin() - sclPort.PIN_CNF[sclPin].Set((nrf.GPIO_PIN_CNF_DIR_Input << nrf.GPIO_PIN_CNF_DIR_Pos) | - (nrf.GPIO_PIN_CNF_INPUT_Connect << nrf.GPIO_PIN_CNF_INPUT_Pos) | - (nrf.GPIO_PIN_CNF_PULL_Pullup << nrf.GPIO_PIN_CNF_PULL_Pos) | - (nrf.GPIO_PIN_CNF_DRIVE_S0D1 << nrf.GPIO_PIN_CNF_DRIVE_Pos) | - (nrf.GPIO_PIN_CNF_SENSE_Disabled << nrf.GPIO_PIN_CNF_SENSE_Pos)) - - sdaPort, sdaPin := config.SDA.getPortPin() - sdaPort.PIN_CNF[sdaPin].Set((nrf.GPIO_PIN_CNF_DIR_Input << nrf.GPIO_PIN_CNF_DIR_Pos) | - (nrf.GPIO_PIN_CNF_INPUT_Connect << nrf.GPIO_PIN_CNF_INPUT_Pos) | - (nrf.GPIO_PIN_CNF_PULL_Pullup << nrf.GPIO_PIN_CNF_PULL_Pos) | - (nrf.GPIO_PIN_CNF_DRIVE_S0D1 << nrf.GPIO_PIN_CNF_DRIVE_Pos) | - (nrf.GPIO_PIN_CNF_SENSE_Disabled << nrf.GPIO_PIN_CNF_SENSE_Pos)) - - i2c.setPins(config.SCL, config.SDA) - - i2c.mode = config.Mode - if i2c.mode == I2CModeController { - i2c.SetBaudRate(config.Frequency) - - i2c.enableAsController() - } else { - i2c.enableAsTarget() - } - - return nil -} - -// SetBaudRate sets the I2C frequency. It has the side effect of also -// enabling the I2C hardware if disabled beforehand. -// -//go:inline -func (i2c *I2C) SetBaudRate(br uint32) error { - switch { - case br >= 400*KHz: - i2c.Bus.SetFREQUENCY(nrf.TWI_FREQUENCY_FREQUENCY_K400) - case br >= 250*KHz: - i2c.Bus.SetFREQUENCY(nrf.TWI_FREQUENCY_FREQUENCY_K250) - default: - i2c.Bus.SetFREQUENCY(nrf.TWI_FREQUENCY_FREQUENCY_K100) - } - - return nil -} - -// signalStop sends a stop signal to the I2C peripheral and waits for confirmation. -func (i2c *I2C) signalStop() error { - tries := 0 - i2c.Bus.TASKS_STOP.Set(1) - for i2c.Bus.EVENTS_STOPPED.Get() == 0 { - tries++ - if tries >= i2cTimeout { - return errI2CSignalStopTimeout - } - } - i2c.Bus.EVENTS_STOPPED.Set(0) - return nil -} - -var rngStarted = false - -// getRNG returns 32 bits of non-deterministic random data based on internal thermal noise. -// According to Nordic's documentation, the random output is suitable for cryptographic purposes. -func getRNG() (ret uint32, err error) { - // There's no apparent way to check the status of the RNG peripheral's task, so simply start it - // to avoid deadlocking while waiting for output. - if !rngStarted { - nrf.RNG.TASKS_START.Set(1) - nrf.RNG.SetCONFIG_DERCEN(nrf.RNG_CONFIG_DERCEN_Enabled) - rngStarted = true - } - - // The RNG returns one byte at a time, so stack up four bytes into a single uint32 for return. - for i := 0; i < 4; i++ { - // Wait for data to be ready. - for nrf.RNG.EVENTS_VALRDY.Get() == 0 { - } - // Append random byte to output. - ret = (ret << 8) ^ nrf.RNG.GetVALUE() - // Unset the EVENTS_VALRDY register to avoid reading the same random output twice. - nrf.RNG.EVENTS_VALRDY.Set(0) - } - - return ret, nil -} - -// ReadTemperature reads the silicon die temperature of the chip. The return -// value is in milli-celsius. -func ReadTemperature() int32 { - nrf.TEMP.TASKS_START.Set(1) - for nrf.TEMP.EVENTS_DATARDY.Get() == 0 { - } - temp := int32(nrf.TEMP.TEMP.Get()) * 250 // the returned value is in units of 0.25°C - nrf.TEMP.EVENTS_DATARDY.Set(0) - return temp -} - -const memoryStart = 0x0 - -// compile-time check for ensuring we fulfill BlockDevice interface -var _ BlockDevice = flashBlockDevice{} - -var Flash flashBlockDevice - -type flashBlockDevice struct { -} - -// ReadAt reads the given number of bytes from the block device. -func (f flashBlockDevice) ReadAt(p []byte, off int64) (n int, err error) { - if FlashDataStart()+uintptr(off)+uintptr(len(p)) > FlashDataEnd() { - return 0, errFlashCannotReadPastEOF - } - - data := unsafe.Slice((*byte)(unsafe.Pointer(FlashDataStart()+uintptr(off))), len(p)) - copy(p, data) - - return len(p), nil -} - -// WriteAt writes the given number of bytes to the block device. -// Only double-word (64 bits) length data can be programmed. See rm0461 page 78. -// If the length of p is not long enough it will be padded with 0xFF bytes. -// This method assumes that the destination is already erased. -func (f flashBlockDevice) WriteAt(p []byte, off int64) (n int, err error) { - if FlashDataStart()+uintptr(off)+uintptr(len(p)) > FlashDataEnd() { - return 0, errFlashCannotWritePastEOF - } - - address := FlashDataStart() + uintptr(off) - padded := flashPad(p, int(f.WriteBlockSize())) - - waitWhileFlashBusy() - - nrf.NVMC.SetCONFIG_WEN(nrf.NVMC_CONFIG_WEN_Wen) - defer nrf.NVMC.SetCONFIG_WEN(nrf.NVMC_CONFIG_WEN_Ren) - - for j := 0; j < len(padded); j += int(f.WriteBlockSize()) { - // write word - *(*uint32)(unsafe.Pointer(address)) = binary.LittleEndian.Uint32(padded[j : j+int(f.WriteBlockSize())]) - address += uintptr(f.WriteBlockSize()) - waitWhileFlashBusy() - } - - return len(padded), nil -} - -// Size returns the number of bytes in this block device. -func (f flashBlockDevice) Size() int64 { - return int64(FlashDataEnd() - FlashDataStart()) -} - -const writeBlockSize = 4 - -// WriteBlockSize returns the block size in which data can be written to -// memory. It can be used by a client to optimize writes, non-aligned writes -// should always work correctly. -func (f flashBlockDevice) WriteBlockSize() int64 { - return writeBlockSize -} - -// EraseBlockSize returns the smallest erasable area on this particular chip -// in bytes. This is used for the block size in EraseBlocks. -// It must be a power of two, and may be as small as 1. A typical size is 4096. -func (f flashBlockDevice) EraseBlockSize() int64 { - return eraseBlockSize() -} - -// EraseBlocks erases the given number of blocks. An implementation may -// transparently coalesce ranges of blocks into larger bundles if the chip -// supports this. The start and len parameters are in block numbers, use -// EraseBlockSize to map addresses to blocks. -func (f flashBlockDevice) EraseBlocks(start, len int64) error { - address := FlashDataStart() + uintptr(start*f.EraseBlockSize()) - waitWhileFlashBusy() - - nrf.NVMC.SetCONFIG_WEN(nrf.NVMC_CONFIG_WEN_Een) - defer nrf.NVMC.SetCONFIG_WEN(nrf.NVMC_CONFIG_WEN_Ren) - - for i := start; i < start+len; i++ { - nrf.NVMC.ERASEPAGE.Set(uint32(address)) - waitWhileFlashBusy() - address += uintptr(f.EraseBlockSize()) - } - - return nil -} - -func waitWhileFlashBusy() { - for nrf.NVMC.GetREADY() != nrf.NVMC_READY_READY_Ready { - } -} diff --git a/emb/machine/machine_nrf51.go b/emb/machine/machine_nrf51.go deleted file mode 100644 index d627d63..0000000 --- a/emb/machine/machine_nrf51.go +++ /dev/null @@ -1,278 +0,0 @@ -//go:build nrf51 - -package machine - -import ( - "device/nrf" -) - -const eraseBlockSizeValue = 1024 - -func eraseBlockSize() int64 { - return eraseBlockSizeValue -} - -// Get peripheral and pin number for this GPIO pin. -func (p Pin) getPortPin() (*nrf.GPIO_Type, uint32) { - return nrf.GPIO, uint32(p) -} - -func (uart *UART) setPins(tx, rx Pin) { - nrf.UART0.PSELTXD.Set(uint32(tx)) - nrf.UART0.PSELRXD.Set(uint32(rx)) -} - -func (i2c *I2C) setPins(scl, sda Pin) { - i2c.Bus.PSELSCL.Set(uint32(scl)) - i2c.Bus.PSELSDA.Set(uint32(sda)) -} - -// SPI on the NRF. -type SPI struct { - Bus *nrf.SPI_Type -} - -// There are 2 SPI interfaces on the NRF51. -var ( - SPI0 = &SPI{Bus: nrf.SPI0} - SPI1 = &SPI{Bus: nrf.SPI1} -) - -// SPIConfig is used to store config info for SPI. -type SPIConfig struct { - Frequency uint32 - SCK Pin - SDO Pin - SDI Pin - LSBFirst bool - Mode uint8 -} - -// Configure is intended to setup the SPI interface. -func (spi *SPI) Configure(config SPIConfig) error { - // Disable bus to configure it - spi.Bus.ENABLE.Set(nrf.SPI_ENABLE_ENABLE_Disabled) - - // set frequency - var freq uint32 - - if config.Frequency == 0 { - config.Frequency = 4000000 // 4MHz - } - - switch { - case config.Frequency >= 8000000: - freq = nrf.SPI_FREQUENCY_FREQUENCY_M8 - case config.Frequency >= 4000000: - freq = nrf.SPI_FREQUENCY_FREQUENCY_M4 - case config.Frequency >= 2000000: - freq = nrf.SPI_FREQUENCY_FREQUENCY_M2 - case config.Frequency >= 1000000: - freq = nrf.SPI_FREQUENCY_FREQUENCY_M1 - case config.Frequency >= 500000: - freq = nrf.SPI_FREQUENCY_FREQUENCY_K500 - case config.Frequency >= 250000: - freq = nrf.SPI_FREQUENCY_FREQUENCY_K250 - default: // below 250kHz, default to the lowest speed available - freq = nrf.SPI_FREQUENCY_FREQUENCY_K125 - } - spi.Bus.FREQUENCY.Set(freq) - - var conf uint32 - - // set bit transfer order - if config.LSBFirst { - conf = (nrf.SPI_CONFIG_ORDER_LsbFirst << nrf.SPI_CONFIG_ORDER_Pos) - } - - // set mode - switch config.Mode { - case 0: - conf &^= (nrf.SPI_CONFIG_CPOL_ActiveHigh << nrf.SPI_CONFIG_CPOL_Pos) - conf &^= (nrf.SPI_CONFIG_CPHA_Leading << nrf.SPI_CONFIG_CPHA_Pos) - case 1: - conf &^= (nrf.SPI_CONFIG_CPOL_ActiveHigh << nrf.SPI_CONFIG_CPOL_Pos) - conf |= (nrf.SPI_CONFIG_CPHA_Trailing << nrf.SPI_CONFIG_CPHA_Pos) - case 2: - conf |= (nrf.SPI_CONFIG_CPOL_ActiveLow << nrf.SPI_CONFIG_CPOL_Pos) - conf &^= (nrf.SPI_CONFIG_CPHA_Leading << nrf.SPI_CONFIG_CPHA_Pos) - case 3: - conf |= (nrf.SPI_CONFIG_CPOL_ActiveLow << nrf.SPI_CONFIG_CPOL_Pos) - conf |= (nrf.SPI_CONFIG_CPHA_Trailing << nrf.SPI_CONFIG_CPHA_Pos) - default: // to mode - conf &^= (nrf.SPI_CONFIG_CPOL_ActiveHigh << nrf.SPI_CONFIG_CPOL_Pos) - conf &^= (nrf.SPI_CONFIG_CPHA_Leading << nrf.SPI_CONFIG_CPHA_Pos) - } - spi.Bus.CONFIG.Set(conf) - - // set pins - if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 { - config.SCK = SPI0_SCK_PIN - config.SDO = SPI0_SDO_PIN - config.SDI = SPI0_SDI_PIN - } - spi.Bus.PSELSCK.Set(uint32(config.SCK)) - spi.Bus.PSELMOSI.Set(uint32(config.SDO)) - spi.Bus.PSELMISO.Set(uint32(config.SDI)) - - // Re-enable bus now that it is configured. - spi.Bus.ENABLE.Set(nrf.SPI_ENABLE_ENABLE_Enabled) - - return nil -} - -// Transfer writes/reads a single byte using the SPI interface. -func (spi *SPI) Transfer(w byte) (byte, error) { - spi.Bus.TXD.Set(uint32(w)) - for spi.Bus.EVENTS_READY.Get() == 0 { - } - r := spi.Bus.RXD.Get() - spi.Bus.EVENTS_READY.Set(0) - - // TODO: handle SPI errors - return byte(r), nil -} - -// Tx handles read/write operation for SPI interface. Since SPI is a synchronous write/read -// interface, there must always be the same number of bytes written as bytes read. -// The Tx method knows about this, and offers a few different ways of calling it. -// -// This form sends the bytes in tx buffer, putting the resulting bytes read into the rx buffer. -// Note that the tx and rx buffers must be the same size: -// -// spi.Tx(tx, rx) -// -// This form sends the tx buffer, ignoring the result. Useful for sending "commands" that return zeros -// until all the bytes in the command packet have been received: -// -// spi.Tx(tx, nil) -// -// This form sends zeros, putting the result into the rx buffer. Good for reading a "result packet": -// -// spi.Tx(nil, rx) -func (spi *SPI) Tx(w, r []byte) error { - var err error - - switch { - case len(w) == 0: - // read only, so write zero and read a result. - for i := range r { - r[i], err = spi.Transfer(0) - if err != nil { - return err - } - } - case len(r) == 0: - // write only - spi.Bus.TXD.Set(uint32(w[0])) - w = w[1:] - for _, b := range w { - spi.Bus.TXD.Set(uint32(b)) - for spi.Bus.EVENTS_READY.Get() == 0 { - } - spi.Bus.EVENTS_READY.Set(0) - _ = spi.Bus.RXD.Get() - } - for spi.Bus.EVENTS_READY.Get() == 0 { - } - spi.Bus.EVENTS_READY.Set(0) - _ = spi.Bus.RXD.Get() - - default: - // write/read - if len(w) != len(r) { - return ErrTxInvalidSliceSize - } - - for i, b := range w { - r[i], err = spi.Transfer(b) - if err != nil { - return err - } - } - } - - return nil -} - -// InitADC initializes the registers needed for ADC. -func InitADC() { - return // no specific setup on nrf51 machine. -} - -// Configure configures an ADC pin to be able to read analog data. -func (a ADC) Configure(ADCConfig) { - return // no pin specific setup on nrf51 machine. -} - -// Get returns the current value of a ADC pin in the range 0..0xffff. -func (a ADC) Get() uint16 { - var value uint32 - - adcPin := a.getADCPin() - - // Enable ADC. - nrf.ADC.SetENABLE(nrf.ADC_ENABLE_ENABLE_Enabled) - - // Set pin to read. - nrf.ADC.SetCONFIG_PSEL(adcPin) - - // config ADC - nrf.ADC.SetCONFIG_RES(nrf.ADC_CONFIG_RES_10bit) - nrf.ADC.SetCONFIG_INPSEL(nrf.ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling) - nrf.ADC.SetCONFIG_REFSEL(nrf.ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling) - - // Start tasks. - nrf.ADC.TASKS_START.Set(1) - - // Wait until the sample task is done. - for nrf.ADC.EVENTS_END.Get() == 0 { - } - nrf.ADC.EVENTS_END.Set(0x00) - - value = nrf.ADC.GetRESULT() - - // Stop the ADC - nrf.ADC.TASKS_STOP.Set(1) - - // Disable ADC. - nrf.ADC.SetENABLE(nrf.ADC_ENABLE_ENABLE_Disabled) - - if value < 0 { - value = 0 - } - - // Return 16-bit result from 10-bit value. - return uint16(value << 6) -} - -func (a ADC) getADCPin() uint32 { - switch a.Pin { - case 1: - return nrf.ADC_CONFIG_PSEL_AnalogInput2 - - case 2: - return nrf.ADC_CONFIG_PSEL_AnalogInput3 - - case 3: - return nrf.ADC_CONFIG_PSEL_AnalogInput4 - - case 4: - return nrf.ADC_CONFIG_PSEL_AnalogInput5 - - case 5: - return nrf.ADC_CONFIG_PSEL_AnalogInput6 - - case 6: - return nrf.ADC_CONFIG_PSEL_AnalogInput7 - - case 26: - return nrf.ADC_CONFIG_PSEL_AnalogInput0 - - case 27: - return nrf.ADC_CONFIG_PSEL_AnalogInput1 - - default: - return 0 - } -} diff --git a/emb/machine/machine_nrf52.go b/emb/machine/machine_nrf52.go deleted file mode 100644 index 71c5343..0000000 --- a/emb/machine/machine_nrf52.go +++ /dev/null @@ -1,71 +0,0 @@ -//go:build nrf52 - -package machine - -import ( - "device/nrf" -) - -// Hardware pins -const ( - P0_00 Pin = 0 - P0_01 Pin = 1 - P0_02 Pin = 2 - P0_03 Pin = 3 - P0_04 Pin = 4 - P0_05 Pin = 5 - P0_06 Pin = 6 - P0_07 Pin = 7 - P0_08 Pin = 8 - P0_09 Pin = 9 - P0_10 Pin = 10 - P0_11 Pin = 11 - P0_12 Pin = 12 - P0_13 Pin = 13 - P0_14 Pin = 14 - P0_15 Pin = 15 - P0_16 Pin = 16 - P0_17 Pin = 17 - P0_18 Pin = 18 - P0_19 Pin = 19 - P0_20 Pin = 20 - P0_21 Pin = 21 - P0_22 Pin = 22 - P0_23 Pin = 23 - P0_24 Pin = 24 - P0_25 Pin = 25 - P0_26 Pin = 26 - P0_27 Pin = 27 - P0_28 Pin = 28 - P0_29 Pin = 29 - P0_30 Pin = 30 - P0_31 Pin = 31 -) - -// Get peripheral and pin number for this GPIO pin. -func (p Pin) getPortPin() (*nrf.GPIO_Type, uint32) { - return nrf.P0, uint32(p) -} - -func (uart *UART) setPins(tx, rx Pin) { - nrf.UART0.PSELTXD.Set(uint32(tx)) - nrf.UART0.PSELRXD.Set(uint32(rx)) -} - -func (i2c *I2C) setPins(scl, sda Pin) { - i2c.Bus.PSELSCL.Set(uint32(scl)) - i2c.Bus.PSELSDA.Set(uint32(sda)) -} - -// PWM -var ( - PWM0 = &PWM{PWM: nrf.PWM0} - PWM1 = &PWM{PWM: nrf.PWM1} - PWM2 = &PWM{PWM: nrf.PWM2} -) - -const eraseBlockSizeValue = 4096 - -func eraseBlockSize() int64 { - return eraseBlockSizeValue -} diff --git a/emb/machine/machine_nrf52833.go b/emb/machine/machine_nrf52833.go deleted file mode 100644 index 60558eb..0000000 --- a/emb/machine/machine_nrf52833.go +++ /dev/null @@ -1,92 +0,0 @@ -//go:build nrf52833 - -package machine - -import ( - "device/nrf" -) - -// Hardware pins -const ( - P0_00 Pin = 0 - P0_01 Pin = 1 - P0_02 Pin = 2 - P0_03 Pin = 3 - P0_04 Pin = 4 - P0_05 Pin = 5 - P0_06 Pin = 6 - P0_07 Pin = 7 - P0_08 Pin = 8 - P0_09 Pin = 9 - P0_10 Pin = 10 - P0_11 Pin = 11 - P0_12 Pin = 12 - P0_13 Pin = 13 - P0_14 Pin = 14 - P0_15 Pin = 15 - P0_16 Pin = 16 - P0_17 Pin = 17 - P0_18 Pin = 18 - P0_19 Pin = 19 - P0_20 Pin = 20 - P0_21 Pin = 21 - P0_22 Pin = 22 - P0_23 Pin = 23 - P0_24 Pin = 24 - P0_25 Pin = 25 - P0_26 Pin = 26 - P0_27 Pin = 27 - P0_28 Pin = 28 - P0_29 Pin = 29 - P0_30 Pin = 30 - P0_31 Pin = 31 - P1_00 Pin = 32 - P1_01 Pin = 33 - P1_02 Pin = 34 - P1_03 Pin = 35 - P1_04 Pin = 36 - P1_05 Pin = 37 - P1_06 Pin = 38 - P1_07 Pin = 39 - P1_08 Pin = 40 - P1_09 Pin = 41 - P1_10 Pin = 42 - P1_11 Pin = 43 - P1_12 Pin = 44 - P1_13 Pin = 45 - P1_14 Pin = 46 - P1_15 Pin = 47 -) - -// Get peripheral and pin number for this GPIO pin. -func (p Pin) getPortPin() (*nrf.GPIO_Type, uint32) { - if p >= 32 { - return nrf.P1, uint32(p - 32) - } else { - return nrf.P0, uint32(p) - } -} - -func (uart *UART) setPins(tx, rx Pin) { - nrf.UART0.PSEL.TXD.Set(uint32(tx)) - nrf.UART0.PSEL.RXD.Set(uint32(rx)) -} - -func (i2c *I2C) setPins(scl, sda Pin) { - i2c.Bus.PSEL.SCL.Set(uint32(scl)) - i2c.Bus.PSEL.SDA.Set(uint32(sda)) -} - -// PWM -var ( - PWM0 = &PWM{PWM: nrf.PWM0} - PWM1 = &PWM{PWM: nrf.PWM1} - PWM2 = &PWM{PWM: nrf.PWM2} - PWM3 = &PWM{PWM: nrf.PWM3} -) - -const eraseBlockSizeValue = 4096 - -func eraseBlockSize() int64 { - return eraseBlockSizeValue -} diff --git a/emb/machine/machine_nrf52840.go b/emb/machine/machine_nrf52840.go deleted file mode 100644 index 21a4367..0000000 --- a/emb/machine/machine_nrf52840.go +++ /dev/null @@ -1,110 +0,0 @@ -//go:build nrf52840 - -package machine - -import ( - "device/nrf" - "errors" - "unsafe" -) - -// Get peripheral and pin number for this GPIO pin. -func (p Pin) getPortPin() (*nrf.GPIO_Type, uint32) { - if p >= 32 { - return nrf.P1, uint32(p - 32) - } else { - return nrf.P0, uint32(p) - } -} - -func (uart *UART) setPins(tx, rx Pin) { - nrf.UART0.PSEL.TXD.Set(uint32(tx)) - nrf.UART0.PSEL.RXD.Set(uint32(rx)) -} - -func (i2c *I2C) setPins(scl, sda Pin) { - i2c.Bus.PSEL.SCL.Set(uint32(scl)) - i2c.Bus.PSEL.SDA.Set(uint32(sda)) -} - -// PWM -var ( - PWM0 = &PWM{PWM: nrf.PWM0} - PWM1 = &PWM{PWM: nrf.PWM1} - PWM2 = &PWM{PWM: nrf.PWM2} - PWM3 = &PWM{PWM: nrf.PWM3} -) - -// PDM represents a PDM device -type PDM struct { - device *nrf.PDM_Type - defaultBuffer int16 -} - -// Configure is intended to set up the PDM interface prior to use. -func (pdm *PDM) Configure(config PDMConfig) error { - if config.DIN == 0 { - return errors.New("No DIN pin provided in configuration") - } - - if config.CLK == 0 { - return errors.New("No CLK pin provided in configuration") - } - - config.DIN.Configure(PinConfig{Mode: PinInput}) - config.CLK.Configure(PinConfig{Mode: PinOutput}) - pdm.device = nrf.PDM - pdm.device.PSEL.DIN.Set(uint32(config.DIN)) - pdm.device.PSEL.CLK.Set(uint32(config.CLK)) - pdm.device.PDMCLKCTRL.Set(nrf.PDM_PDMCLKCTRL_FREQ_Default) - pdm.device.RATIO.Set(nrf.PDM_RATIO_RATIO_Ratio64) - pdm.device.GAINL.Set(nrf.PDM_GAINL_GAINL_DefaultGain) - pdm.device.GAINR.Set(nrf.PDM_GAINR_GAINR_DefaultGain) - pdm.device.ENABLE.Set(nrf.PDM_ENABLE_ENABLE_Enabled) - - if config.Stereo { - pdm.device.MODE.Set(nrf.PDM_MODE_OPERATION_Stereo | nrf.PDM_MODE_EDGE_LeftRising) - } else { - pdm.device.MODE.Set(nrf.PDM_MODE_OPERATION_Mono | nrf.PDM_MODE_EDGE_LeftRising) - } - - pdm.device.SAMPLE.SetPTR(uint32(uintptr(unsafe.Pointer(&pdm.defaultBuffer)))) - pdm.device.SAMPLE.SetMAXCNT_BUFFSIZE(1) - pdm.device.SetTASKS_START(1) - return nil -} - -// Read stores a set of samples in the given target buffer. -func (pdm *PDM) Read(buf []int16) (uint32, error) { - pdm.device.SAMPLE.SetPTR(uint32(uintptr(unsafe.Pointer(&buf[0])))) - pdm.device.SAMPLE.MAXCNT.Set(uint32(len(buf))) - pdm.device.EVENTS_STARTED.Set(0) - - // Step 1: wait for new sampling to start for target buffer - for !pdm.device.EVENTS_STARTED.HasBits(nrf.PDM_EVENTS_STARTED_EVENTS_STARTED) { - } - pdm.device.EVENTS_END.Set(0) - - // Step 2: swap out buffers for next recording so we don't continue to - // write to the target buffer - pdm.device.EVENTS_STARTED.Set(0) - pdm.device.SAMPLE.SetPTR(uint32(uintptr(unsafe.Pointer(&pdm.defaultBuffer)))) - pdm.device.SAMPLE.MAXCNT.Set(1) - - // Step 3: wait for original event to end - for pdm.device.EVENTS_END.HasBits(nrf.PDM_EVENTS_STOPPED_EVENTS_STOPPED) { - } - - // Step 4: wait for default buffer to start recording before proceeding - // otherwise we see the contents of target buffer change later - for !pdm.device.EVENTS_STARTED.HasBits(nrf.PDM_EVENTS_STARTED_EVENTS_STARTED) { - } - - return uint32(len(buf)), nil -} - -const eraseBlockSizeValue = 4096 - -func eraseBlockSize() int64 { - return eraseBlockSizeValue -} diff --git a/emb/machine/machine_nrf52840_enter_bootloader.go b/emb/machine/machine_nrf52840_enter_bootloader.go deleted file mode 100644 index d24152a..0000000 --- a/emb/machine/machine_nrf52840_enter_bootloader.go +++ /dev/null @@ -1,38 +0,0 @@ -//go:build nrf52840 - -package machine - -import ( - "device/arm" - "device/nrf" -) - -const ( - dfuMagicSerialOnlyReset = 0x4e - dfuMagicUF2Reset = 0x57 - dfuMagicOTAReset = 0xA8 -) - -// EnterSerialBootloader resets the chip into the serial bootloader. After -// reset, it can be flashed using serial/nrfutil. -func EnterSerialBootloader() { - arm.DisableInterrupts() - nrf.POWER.GPREGRET.Set(dfuMagicSerialOnlyReset) - arm.SystemReset() -} - -// EnterUF2Bootloader resets the chip into the UF2 bootloader. After reset, it -// can be flashed via nrfutil or by copying a UF2 file to the mass storage device -func EnterUF2Bootloader() { - arm.DisableInterrupts() - nrf.POWER.GPREGRET.Set(dfuMagicUF2Reset) - arm.SystemReset() -} - -// EnterOTABootloader resets the chip into the bootloader so that it can be -// flashed via an OTA update -func EnterOTABootloader() { - arm.DisableInterrupts() - nrf.POWER.GPREGRET.Set(dfuMagicOTAReset) - arm.SystemReset() -} diff --git a/emb/machine/machine_nrf52840_lfxtal_false.go b/emb/machine/machine_nrf52840_lfxtal_false.go deleted file mode 100644 index ba38a32..0000000 --- a/emb/machine/machine_nrf52840_lfxtal_false.go +++ /dev/null @@ -1,5 +0,0 @@ -//go:build nrf52840 && nrf52840_lfxtal_false - -package machine - -const HasLowFrequencyCrystal = false diff --git a/emb/machine/machine_nrf52840_lfxtal_true.go b/emb/machine/machine_nrf52840_lfxtal_true.go deleted file mode 100644 index 4bef553..0000000 --- a/emb/machine/machine_nrf52840_lfxtal_true.go +++ /dev/null @@ -1,5 +0,0 @@ -//go:build nrf52840 && ((nrf52840_generic && !nrf52840_lfxtal_false) || nrf52840_lfxtal_true) - -package machine - -const HasLowFrequencyCrystal = true diff --git a/emb/machine/machine_nrf52840_simulator.go b/emb/machine/machine_nrf52840_simulator.go deleted file mode 100644 index f04f05c..0000000 --- a/emb/machine/machine_nrf52840_simulator.go +++ /dev/null @@ -1,60 +0,0 @@ -//go:build !baremetal && (bluemicro840 || circuitplay_bluefruit || clue_alpha || feather_nrf52840_sense || feather_nrf52840 || itsybitsy_nrf52840 || mdbt50qrx || nano_33_ble || nicenano || nrf52840_mdk || particle_3rd_gen || pca10056 || pca10059 || rak4631 || reelboard || xiao_ble) - -// Simulator support for nrf52840 based boards. - -package machine - -// Channel values below are nil, so that they get filled in on the first use. -// This is the same as what happens on baremetal. - -var PWM0 = &timerType{ - instance: 0, - frequency: 16e6, - bits: 15, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128}, - channelPins: [][]Pin{ - nil, // channel 0 - nil, // channel 1 - nil, // channel 2 - nil, // channel 3 - }, -} - -var PWM1 = &timerType{ - instance: 1, - frequency: 16e6, - bits: 15, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128}, - channelPins: [][]Pin{ - nil, // channel 0 - nil, // channel 1 - nil, // channel 2 - nil, // channel 3 - }, -} - -var PWM2 = &timerType{ - instance: 2, - frequency: 16e6, - bits: 15, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128}, - channelPins: [][]Pin{ - nil, // channel 0 - nil, // channel 1 - nil, // channel 2 - nil, // channel 3 - }, -} - -var PWM3 = &timerType{ - instance: 3, - frequency: 16e6, - bits: 15, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128}, - channelPins: [][]Pin{ - nil, // channel 0 - nil, // channel 1 - nil, // channel 2 - nil, // channel 3 - }, -} diff --git a/emb/machine/machine_nrf52840_usb.go b/emb/machine/machine_nrf52840_usb.go deleted file mode 100644 index 1fa4694..0000000 --- a/emb/machine/machine_nrf52840_usb.go +++ /dev/null @@ -1,381 +0,0 @@ -//go:build nrf52840 - -package machine - -import ( - "device/arm" - "device/nrf" - "machine/usb" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -const NumberOfUSBEndpoints = 8 - -var ( - sendOnEP0DATADONE struct { - ptr *byte - count int - offset int - } - epinen uint32 - epouten uint32 - easyDMABusy volatile.Register8 - - endPoints = []uint32{ - usb.CONTROL_ENDPOINT: usb.ENDPOINT_TYPE_CONTROL, - usb.CDC_ENDPOINT_ACM: (usb.ENDPOINT_TYPE_INTERRUPT | usb.EndpointIn), - usb.CDC_ENDPOINT_OUT: (usb.ENDPOINT_TYPE_BULK | usb.EndpointOut), - usb.CDC_ENDPOINT_IN: (usb.ENDPOINT_TYPE_BULK | usb.EndpointIn), - usb.HID_ENDPOINT_IN: (usb.ENDPOINT_TYPE_DISABLE), // Interrupt In - usb.HID_ENDPOINT_OUT: (usb.ENDPOINT_TYPE_DISABLE), // Interrupt Out - usb.MIDI_ENDPOINT_IN: (usb.ENDPOINT_TYPE_DISABLE), // Bulk In - usb.MIDI_ENDPOINT_OUT: (usb.ENDPOINT_TYPE_DISABLE), // Bulk Out - } -) - -// enterCriticalSection is used to protect access to easyDMA - only one thing -// can be done with it at a time -func enterCriticalSection() { - waitForEasyDMA() - easyDMABusy.SetBits(1) -} - -func waitForEasyDMA() { - for easyDMABusy.HasBits(1) { - arm.Asm("wfi") - } -} - -func exitCriticalSection() { - easyDMABusy.ClearBits(1) -} - -// Configure the USB peripheral. The config is here for compatibility with the UART interface. -func (dev *USBDevice) Configure(config UARTConfig) { - if dev.initcomplete { - return - } - - state := interrupt.Disable() - defer interrupt.Restore(state) - - nrf.USBD.USBPULLUP.Set(0) - - // Enable IRQ. Make sure this is higher than the SWI2 interrupt handler so - // that it is possible to print to the console from a BLE interrupt. You - // shouldn't generally do that but it is useful for debugging and panic - // logging. - intr := interrupt.New(nrf.IRQ_USBD, handleUSBIRQ) - intr.SetPriority(0x40) // interrupt priority 2 (lower number means more important) - intr.Enable() - - // enable interrupt for end of reset and start of frame - nrf.USBD.INTEN.Set(nrf.USBD_INTENSET_USBEVENT) - - // errata 187 - // https://infocenter.nordicsemi.com/topic/errata_nRF52840_EngB/ERR/nRF52840/EngineeringB/latest/anomaly_840_187.html - (*volatile.Register32)(unsafe.Pointer(uintptr(0x4006EC00))).Set(0x00009375) - (*volatile.Register32)(unsafe.Pointer(uintptr(0x4006ED14))).Set(0x00000003) - (*volatile.Register32)(unsafe.Pointer(uintptr(0x4006EC00))).Set(0x00009375) - - // enable USB - nrf.USBD.ENABLE.Set(1) - - timeout := 300000 - for !nrf.USBD.EVENTCAUSE.HasBits(nrf.USBD_EVENTCAUSE_READY) { - timeout-- - if timeout == 0 { - return - } - } - nrf.USBD.EVENTCAUSE.ClearBits(nrf.USBD_EVENTCAUSE_READY) - - // errata 187 - (*volatile.Register32)(unsafe.Pointer(uintptr(0x4006EC00))).Set(0x00009375) - (*volatile.Register32)(unsafe.Pointer(uintptr(0x4006ED14))).Set(0x00000000) - (*volatile.Register32)(unsafe.Pointer(uintptr(0x4006EC00))).Set(0x00009375) - - dev.initcomplete = true -} - -func handleUSBIRQ(interrupt.Interrupt) { - if nrf.USBD.EVENTS_SOF.Get() == 1 { - nrf.USBD.EVENTS_SOF.Set(0) - - // if you want to blink LED showing traffic, this would be the place... - } - - // USBD ready event - if nrf.USBD.EVENTS_USBEVENT.Get() == 1 { - nrf.USBD.EVENTS_USBEVENT.Set(0) - if (nrf.USBD.EVENTCAUSE.Get() & nrf.USBD_EVENTCAUSE_READY) > 0 { - - // Configure control endpoint - initEndpoint(0, usb.ENDPOINT_TYPE_CONTROL) - nrf.USBD.USBPULLUP.Set(1) - - usbConfiguration = 0 - } - nrf.USBD.EVENTCAUSE.Set(0) - } - - if nrf.USBD.EVENTS_EP0DATADONE.Get() == 1 { - // done sending packet - either need to send another or enter status stage - nrf.USBD.EVENTS_EP0DATADONE.Set(0) - if sendOnEP0DATADONE.ptr != nil { - // previous data was too big for one packet, so send a second - ptr := sendOnEP0DATADONE.ptr - count := sendOnEP0DATADONE.count - if count > usb.EndpointPacketSize { - sendOnEP0DATADONE.offset += usb.EndpointPacketSize - sendOnEP0DATADONE.ptr = &udd_ep_control_cache_buffer[sendOnEP0DATADONE.offset] - count = usb.EndpointPacketSize - } - sendOnEP0DATADONE.count -= count - sendViaEPIn( - 0, - ptr, - count, - ) - - // clear, so we know we're done - if sendOnEP0DATADONE.count == 0 { - sendOnEP0DATADONE.ptr = nil - sendOnEP0DATADONE.offset = 0 - } - } else { - // no more data, so set status stage - SendZlp() // nrf.USBD.TASKS_EP0STATUS.Set(1) - } - return - } - - // Endpoint 0 Setup interrupt - if nrf.USBD.EVENTS_EP0SETUP.Get() == 1 { - // ack setup received - nrf.USBD.EVENTS_EP0SETUP.Set(0) - - // parse setup - setup := parseUSBSetupRegisters() - - ok := false - if (setup.BmRequestType & usb.REQUEST_TYPE) == usb.REQUEST_STANDARD { - // Standard Requests - ok = handleStandardSetup(setup) - } else { - // Class Interface Requests - if setup.WIndex < uint16(len(usbSetupHandler)) && usbSetupHandler[setup.WIndex] != nil { - ok = usbSetupHandler[setup.WIndex](setup) - } - } - - if !ok { - // Stall endpoint - nrf.USBD.TASKS_EP0STALL.Set(1) - } - } - - // Now the actual transfer handlers, ignore endpoint number 0 (setup) - if nrf.USBD.EVENTS_EPDATA.Get() > 0 { - nrf.USBD.EVENTS_EPDATA.Set(0) - epDataStatus := nrf.USBD.EPDATASTATUS.Get() - nrf.USBD.EPDATASTATUS.Set(epDataStatus) - var i uint32 - for i = 1; i < uint32(len(endPoints)); i++ { - // Check if endpoint has a pending interrupt - inDataDone := epDataStatus&(nrf.USBD_EPDATASTATUS_EPIN1<<(i-1)) > 0 - outDataDone := epDataStatus&(nrf.USBD_EPDATASTATUS_EPOUT1<<(i-1)) > 0 - if inDataDone { - if usbTxHandler[i] != nil { - usbTxHandler[i]() - } - } else if outDataDone { - enterCriticalSection() - nrf.USBD.EPOUT[i].PTR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[i])))) - count := nrf.USBD.SIZE.EPOUT[i].Get() - nrf.USBD.EPOUT[i].MAXCNT.Set(count) - nrf.USBD.TASKS_STARTEPOUT[i].Set(1) - } - } - } - - // ENDEPOUT[n] events - for i := 0; i < len(endPoints); i++ { - if nrf.USBD.EVENTS_ENDEPOUT[i].Get() > 0 { - nrf.USBD.EVENTS_ENDEPOUT[i].Set(0) - buf := handleEndpointRx(uint32(i)) - if usbRxHandler[i] == nil || usbRxHandler[i](buf) { - AckUsbOutTransfer(uint32(i)) - } - exitCriticalSection() - } - } -} - -func parseUSBSetupRegisters() usb.Setup { - return usb.Setup{ - BmRequestType: uint8(nrf.USBD.BMREQUESTTYPE.Get()), - BRequest: uint8(nrf.USBD.BREQUEST.Get()), - WValueL: uint8(nrf.USBD.WVALUEL.Get()), - WValueH: uint8(nrf.USBD.WVALUEH.Get()), - WIndex: uint16((nrf.USBD.WINDEXH.Get() << 8) | nrf.USBD.WINDEXL.Get()), - WLength: uint16(((nrf.USBD.WLENGTHH.Get() & 0xff) << 8) | (nrf.USBD.WLENGTHL.Get() & 0xff)), - } -} - -func initEndpoint(ep, config uint32) { - switch config { - case usb.ENDPOINT_TYPE_INTERRUPT | usb.EndpointIn: - enableEPIn(ep) - - case usb.ENDPOINT_TYPE_BULK | usb.EndpointOut: - nrf.USBD.INTENSET.Set(nrf.USBD_INTENSET_ENDEPOUT0 << ep) - nrf.USBD.SIZE.EPOUT[ep].Set(0) - enableEPOut(ep) - - case usb.ENDPOINT_TYPE_INTERRUPT | usb.EndpointOut: - nrf.USBD.INTENSET.Set(nrf.USBD_INTENSET_ENDEPOUT0 << ep) - nrf.USBD.SIZE.EPOUT[ep].Set(0) - enableEPOut(ep) - - case usb.ENDPOINT_TYPE_BULK | usb.EndpointIn: - enableEPIn(ep) - - case usb.ENDPOINT_TYPE_CONTROL: - enableEPIn(0) - enableEPOut(0) - nrf.USBD.INTENSET.Set(nrf.USBD_INTENSET_ENDEPOUT0 | - nrf.USBD_INTENSET_EP0SETUP | - nrf.USBD_INTENSET_EPDATA | - nrf.USBD_INTENSET_EP0DATADONE) - SendZlp() // nrf.USBD.TASKS_EP0STATUS.Set(1) - } -} - -// SendUSBInPacket sends a packet for USBHID (interrupt in / bulk in). -func SendUSBInPacket(ep uint32, data []byte) bool { - sendUSBPacket(ep, data, 0) - - // clear transfer complete flag - nrf.USBD.INTENCLR.Set(nrf.USBD_INTENCLR_ENDEPOUT0 << 4) - - return true -} - -// Prevent file size increases: https://github.com/tinygo-org/tinygo/pull/998 -// -//go:noinline -func sendUSBPacket(ep uint32, data []byte, maxsize uint16) { - count := len(data) - if 0 < int(maxsize) && int(maxsize) < count { - count = int(maxsize) - } - - if ep == 0 { - copy(udd_ep_control_cache_buffer[:], data[:count]) - if count > usb.EndpointPacketSize { - sendOnEP0DATADONE.offset = usb.EndpointPacketSize - sendOnEP0DATADONE.ptr = &udd_ep_control_cache_buffer[sendOnEP0DATADONE.offset] - sendOnEP0DATADONE.count = count - usb.EndpointPacketSize - count = usb.EndpointPacketSize - } - sendViaEPIn( - ep, - &udd_ep_control_cache_buffer[0], - count, - ) - } else { - copy(udd_ep_in_cache_buffer[ep][:], data[:count]) - sendViaEPIn( - ep, - &udd_ep_in_cache_buffer[ep][0], - count, - ) - } -} - -func handleEndpointRx(ep uint32) []byte { - // get data - count := int(nrf.USBD.EPOUT[ep].AMOUNT.Get()) - - return udd_ep_out_cache_buffer[ep][:count] -} - -// AckUsbOutTransfer is called to acknowledge the completion of a USB OUT transfer. -func AckUsbOutTransfer(ep uint32) { - // set ready for next data - nrf.USBD.SIZE.EPOUT[ep].Set(0) -} - -func SendZlp() { - nrf.USBD.TASKS_EP0STATUS.Set(1) -} - -func sendViaEPIn(ep uint32, ptr *byte, count int) { - nrf.USBD.EPIN[ep].PTR.Set( - uint32(uintptr(unsafe.Pointer(ptr))), - ) - nrf.USBD.EPIN[ep].MAXCNT.Set(uint32(count)) - nrf.USBD.TASKS_STARTEPIN[ep].Set(1) -} - -func enableEPOut(ep uint32) { - epouten = epouten | (nrf.USBD_EPOUTEN_OUT0 << ep) - nrf.USBD.EPOUTEN.Set(epouten) -} - -func enableEPIn(ep uint32) { - epinen = epinen | (nrf.USBD_EPINEN_IN0 << ep) - nrf.USBD.EPINEN.Set(epinen) -} - -func handleUSBSetAddress(setup usb.Setup) bool { - // nrf USBD handles this - return true -} - -func ReceiveUSBControlPacket() ([cdcLineInfoSize]byte, error) { - var b [cdcLineInfoSize]byte - - nrf.USBD.TASKS_EP0RCVOUT.Set(1) - - nrf.USBD.EPOUT[0].PTR.Set(uint32(uintptr(unsafe.Pointer(&udd_ep_out_cache_buffer[0])))) - nrf.USBD.EPOUT[0].MAXCNT.Set(64) - - timeout := 300000 - count := 0 - for { - if nrf.USBD.EVENTS_EP0DATADONE.Get() == 1 { - nrf.USBD.EVENTS_EP0DATADONE.Set(0) - count = int(nrf.USBD.SIZE.EPOUT[0].Get()) - nrf.USBD.TASKS_STARTEPOUT[0].Set(1) - break - } - timeout-- - if timeout == 0 { - return b, ErrUSBReadTimeout - } - } - - timeout = 300000 - for { - if nrf.USBD.EVENTS_ENDEPOUT[0].Get() == 1 { - nrf.USBD.EVENTS_ENDEPOUT[0].Set(0) - break - } - - timeout-- - if timeout == 0 { - return b, ErrUSBReadTimeout - } - } - - nrf.USBD.TASKS_EP0STATUS.Set(1) - nrf.USBD.TASKS_EP0RCVOUT.Set(0) - - copy(b[:7], udd_ep_out_cache_buffer[0][:count]) - - return b, nil -} diff --git a/emb/machine/machine_nrf52840_usb_reset_bossa.go b/emb/machine/machine_nrf52840_usb_reset_bossa.go deleted file mode 100644 index b790eb7..0000000 --- a/emb/machine/machine_nrf52840_usb_reset_bossa.go +++ /dev/null @@ -1,9 +0,0 @@ -//go:build nrf52840 && nrf52840_reset_bossa - -package machine - -// EnterBootloader resets the chip into the serial bootloader. After -// reset, it can be flashed using serial/nrfutil. -func EnterBootloader() { - EnterSerialBootloader() -} diff --git a/emb/machine/machine_nrf52840_usb_reset_none.go b/emb/machine/machine_nrf52840_usb_reset_none.go deleted file mode 100644 index e3900e4..0000000 --- a/emb/machine/machine_nrf52840_usb_reset_none.go +++ /dev/null @@ -1,8 +0,0 @@ -//go:build nrf52840 && !nrf52840_reset_uf2 && !nrf52840_reset_bossa - -package machine - -// EnterBootloader resets the chip into the serial bootloader. -func EnterBootloader() { - // skip -} diff --git a/emb/machine/machine_nrf52840_usb_reset_uf2.go b/emb/machine/machine_nrf52840_usb_reset_uf2.go deleted file mode 100644 index 6573ebb..0000000 --- a/emb/machine/machine_nrf52840_usb_reset_uf2.go +++ /dev/null @@ -1,9 +0,0 @@ -//go:build nrf52840 && nrf52840_reset_uf2 - -package machine - -// EnterBootloader resets the chip into the UF2 bootloader. After reset, it -// can be flashed via nrfutil or by copying a UF2 file to the mass storage device -func EnterBootloader() { - EnterUF2Bootloader() -} diff --git a/emb/machine/machine_nrf528xx.go b/emb/machine/machine_nrf528xx.go deleted file mode 100644 index f8937ae..0000000 --- a/emb/machine/machine_nrf528xx.go +++ /dev/null @@ -1,259 +0,0 @@ -//go:build nrf52840 || nrf52833 - -package machine - -import ( - "device/nrf" - "unsafe" -) - -// I2C on the NRF528xx. -type I2C struct { - Bus *nrf.TWIM_Type // Called Bus to align with Bus field in nrf51 - BusT *nrf.TWIS_Type - mode I2CMode -} - -// There are 2 I2C interfaces on the NRF. -var ( - I2C0 = &I2C{Bus: nrf.TWIM0, BusT: nrf.TWIS0} - I2C1 = &I2C{Bus: nrf.TWIM1, BusT: nrf.TWIS1} -) - -func (i2c *I2C) enableAsController() { - i2c.Bus.ENABLE.Set(nrf.TWIM_ENABLE_ENABLE_Enabled) -} - -func (i2c *I2C) enableAsTarget() { - i2c.BusT.ENABLE.Set(nrf.TWIS_ENABLE_ENABLE_Enabled) -} - -func (i2c *I2C) disable() { - i2c.Bus.ENABLE.Set(0) -} - -// Tx does a single I2C transaction at the specified address (when in controller mode). -// -// It clocks out the given address, writes the bytes in w, reads back len(r) -// bytes and stores them in r, and generates a stop condition on the bus. -func (i2c *I2C) Tx(addr uint16, w, r []byte) (err error) { - i2c.Bus.ADDRESS.Set(uint32(addr)) - - i2c.Bus.EVENTS_STOPPED.Set(0) - i2c.Bus.EVENTS_ERROR.Set(0) - i2c.Bus.EVENTS_RXSTARTED.Set(0) - i2c.Bus.EVENTS_TXSTARTED.Set(0) - i2c.Bus.EVENTS_LASTRX.Set(0) - i2c.Bus.EVENTS_LASTTX.Set(0) - i2c.Bus.EVENTS_SUSPENDED.Set(0) - - // Configure for a single shot to perform both write and read (as applicable) - if len(w) != 0 { - i2c.Bus.TXD.PTR.Set(uint32(uintptr(unsafe.Pointer(&w[0])))) - i2c.Bus.TXD.MAXCNT.Set(uint32(len(w))) - - // If no read, immediately signal stop after TX - if len(r) == 0 { - i2c.Bus.SHORTS.Set(nrf.TWIM_SHORTS_LASTTX_STOP) - } - } - if len(r) != 0 { - i2c.Bus.RXD.PTR.Set(uint32(uintptr(unsafe.Pointer(&r[0])))) - i2c.Bus.RXD.MAXCNT.Set(uint32(len(r))) - - // Auto-start Rx after Tx and Stop after Rx - i2c.Bus.SHORTS.Set(nrf.TWIM_SHORTS_LASTTX_STARTRX | nrf.TWIM_SHORTS_LASTRX_STOP) - } - - // Fire the transaction - i2c.Bus.TASKS_RESUME.Set(1) - if len(w) != 0 { - i2c.Bus.TASKS_STARTTX.Set(1) - } else if len(r) != 0 { - i2c.Bus.TASKS_STARTRX.Set(1) - } - - // Wait until transaction stopped to ensure buffers fully processed - for i2c.Bus.EVENTS_STOPPED.Get() == 0 { - // Allow scheduler to run - gosched() - - // Handle errors by ensuring STOP sent on bus - if i2c.Bus.EVENTS_ERROR.Get() != 0 { - if i2c.Bus.EVENTS_STOPPED.Get() == 0 { - // STOP cannot be sent during SUSPEND - i2c.Bus.TASKS_RESUME.Set(1) - i2c.Bus.TASKS_STOP.Set(1) - } - err = twiCError(i2c.Bus.ERRORSRC.Get()) - } - } - - return -} - -// Listen starts listening for I2C requests sent to specified address -// -// addr is the address to listen to -func (i2c *I2C) Listen(addr uint8) error { - i2c.BusT.ADDRESS[0].Set(uint32(addr)) - i2c.BusT.CONFIG.Set(nrf.TWIS_CONFIG_ADDRESS0_Enabled) - - i2c.BusT.EVENTS_STOPPED.Set(0) - i2c.BusT.EVENTS_ERROR.Set(0) - i2c.BusT.EVENTS_RXSTARTED.Set(0) - i2c.BusT.EVENTS_TXSTARTED.Set(0) - i2c.BusT.EVENTS_WRITE.Set(0) - i2c.BusT.EVENTS_READ.Set(0) - - return nil -} - -// WaitForEvent blocks the current go-routine until an I2C event is received (when in Target mode). -// -// The passed buffer will be populated for receive events, with the number of bytes -// received returned in count. For other event types, buf is not modified and a count -// of zero is returned. -// -// For request events, the caller MUST call `Reply` to avoid hanging the i2c bus indefinitely. -func (i2c *I2C) WaitForEvent(buf []byte) (evt I2CTargetEvent, count int, err error) { - i2c.BusT.RXD.PTR.Set(uint32(uintptr(unsafe.Pointer(&buf[0])))) - i2c.BusT.RXD.MAXCNT.Set(uint32(len(buf))) - - i2c.BusT.TASKS_PREPARERX.Set(nrf.TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger) - - i2c.Bus.TASKS_RESUME.Set(1) - - for i2c.BusT.EVENTS_STOPPED.Get() == 0 && - i2c.BusT.EVENTS_READ.Get() == 0 { - gosched() - - if i2c.BusT.EVENTS_ERROR.Get() != 0 { - i2c.BusT.EVENTS_ERROR.Set(0) - return I2CReceive, 0, twisError(i2c.BusT.ERRORSRC.Get()) - } - } - - count = 0 - evt = I2CFinish - err = nil - - if i2c.BusT.EVENTS_WRITE.Get() != 0 { - i2c.BusT.EVENTS_WRITE.Set(0) - - // Data was sent to this target. We've waited for - // READ or STOPPED event, so transmission should be - // complete. - count = int(i2c.BusT.RXD.AMOUNT.Get()) - evt = I2CReceive - } else if i2c.BusT.EVENTS_READ.Get() != 0 { - i2c.BusT.EVENTS_READ.Set(0) - - // Data is requested from this target, hw will stretch - // the controller's clock until there is a reply to - // send - evt = I2CRequest - } else if i2c.BusT.EVENTS_STOPPED.Get() != 0 { - i2c.BusT.EVENTS_STOPPED.Set(0) - evt = I2CFinish - } - - return -} - -// Reply supplies the response data the controller. -func (i2c *I2C) Reply(buf []byte) error { - i2c.BusT.TXD.PTR.Set(uint32(uintptr(unsafe.Pointer(&buf[0])))) - i2c.BusT.TXD.MAXCNT.Set(uint32(len(buf))) - - i2c.BusT.EVENTS_STOPPED.Set(0) - - // Trigger Tx - i2c.BusT.TASKS_PREPARETX.Set(nrf.TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger) - - // Block, waiting for Tx to complete - for i2c.BusT.EVENTS_STOPPED.Get() == 0 { - gosched() - - if i2c.BusT.EVENTS_ERROR.Get() != 0 { - return twisError(i2c.BusT.ERRORSRC.Get()) - } - } - - i2c.BusT.EVENTS_STOPPED.Set(0) - - return nil -} - -// twiCError converts an I2C controller error to Go -func twiCError(val uint32) error { - if val == 0 { - return nil - } else if val&nrf.TWIM_ERRORSRC_OVERRUN_Msk == nrf.TWIM_ERRORSRC_OVERRUN { - return errI2CBusError - } else if val&nrf.TWIM_ERRORSRC_ANACK_Msk == nrf.TWIM_ERRORSRC_ANACK { - return errI2CAckExpected - } else if val&nrf.TWIM_ERRORSRC_DNACK_Msk == nrf.TWIM_ERRORSRC_DNACK { - return errI2CAckExpected - } - - return errI2CBusError -} - -// twisError converts an I2C target error to Go -func twisError(val uint32) error { - if val == 0 { - return nil - } else if val&nrf.TWIS_ERRORSRC_OVERFLOW_Msk == nrf.TWIS_ERRORSRC_OVERFLOW { - return errI2COverflow - } else if val&nrf.TWIS_ERRORSRC_DNACK_Msk == nrf.TWIS_ERRORSRC_DNACK { - return errI2CAckExpected - } else if val&nrf.TWIS_ERRORSRC_OVERREAD_Msk == nrf.TWIS_ERRORSRC_OVERREAD { - return errI2COverread - } - - return errI2CBusError -} - -var ( - Watchdog = &watchdogImpl{} -) - -const ( - // WatchdogMaxTimeout in milliseconds (approx 36h) - WatchdogMaxTimeout = (0xffffffff * 1000) / 32768 -) - -type watchdogImpl struct { -} - -// Configure the watchdog. -// -// This method should not be called after the watchdog is started and on -// some platforms attempting to reconfigure after starting the watchdog -// is explicitly forbidden / will not work. -func (wd *watchdogImpl) Configure(config WatchdogConfig) error { - // 32.768kHz counter - crv := int32((int64(config.TimeoutMillis) * 32768) / 1000) - nrf.WDT.CRV.Set(uint32(crv)) - - // One source - nrf.WDT.RREN.Set(0x1) - - // Run during sleep - nrf.WDT.CONFIG.Set(nrf.WDT_CONFIG_SLEEP_Run) - - return nil -} - -// Starts the watchdog. -func (wd *watchdogImpl) Start() error { - nrf.WDT.TASKS_START.Set(nrf.WDT_TASKS_START_TASKS_START) - return nil -} - -// Update the watchdog, indicating that `source` is healthy. -func (wd *watchdogImpl) Update() { - // 0x6E524635 = magic value from datasheet - nrf.WDT.RR[0].Set(0x6E524635) -} diff --git a/emb/machine/machine_nrf52xxx.go b/emb/machine/machine_nrf52xxx.go deleted file mode 100644 index a582a7a..0000000 --- a/emb/machine/machine_nrf52xxx.go +++ /dev/null @@ -1,546 +0,0 @@ -//go:build nrf52 || nrf52840 || nrf52833 - -package machine - -import ( - "device/nrf" - "runtime/volatile" - "unsafe" -) - -func CPUFrequency() uint32 { - return 64000000 -} - -// InitADC initializes the registers needed for ADC. -func InitADC() { - // Enable ADC. - // The ADC does not consume a noticeable amount of current by being enabled. - nrf.SAADC.ENABLE.Set(nrf.SAADC_ENABLE_ENABLE_Enabled << nrf.SAADC_ENABLE_ENABLE_Pos) -} - -// Configure configures an ADC pin to be able to read analog data. -// Reference voltage can be 150, 300, 600, 1200, 1800, 2400, 3000(default), 3600 mV -// Resolution can be 8, 10, 12(default), 14 bits -// SampleTime will be ceiled to 3(default), 5, 10, 15, 20 or 40(max) µS respectively -// Samples can be 1(default), 2, 4, 8, 16, 32, 64, 128, 256 samples -func (a *ADC) Configure(config ADCConfig) { - var configVal uint32 = nrf.SAADC_CH_CONFIG_RESP_Bypass<= 8000000: - freq = nrf.SPIM_FREQUENCY_FREQUENCY_M8 - case config.Frequency >= 4000000: - freq = nrf.SPIM_FREQUENCY_FREQUENCY_M4 - case config.Frequency >= 2000000: - freq = nrf.SPIM_FREQUENCY_FREQUENCY_M2 - case config.Frequency >= 1000000: - freq = nrf.SPIM_FREQUENCY_FREQUENCY_M1 - case config.Frequency >= 500000: - freq = nrf.SPIM_FREQUENCY_FREQUENCY_K500 - case config.Frequency >= 250000: - freq = nrf.SPIM_FREQUENCY_FREQUENCY_K250 - default: // below 250kHz, default to the lowest speed available - freq = nrf.SPIM_FREQUENCY_FREQUENCY_K125 - } - spi.Bus.FREQUENCY.Set(freq) - - var conf uint32 - - // set bit transfer order - if config.LSBFirst { - conf = (nrf.SPIM_CONFIG_ORDER_LsbFirst << nrf.SPIM_CONFIG_ORDER_Pos) - } - - // set mode - switch config.Mode { - case 0: - conf &^= (nrf.SPIM_CONFIG_CPOL_ActiveHigh << nrf.SPIM_CONFIG_CPOL_Pos) - conf &^= (nrf.SPIM_CONFIG_CPHA_Leading << nrf.SPIM_CONFIG_CPHA_Pos) - case 1: - conf &^= (nrf.SPIM_CONFIG_CPOL_ActiveHigh << nrf.SPIM_CONFIG_CPOL_Pos) - conf |= (nrf.SPIM_CONFIG_CPHA_Trailing << nrf.SPIM_CONFIG_CPHA_Pos) - case 2: - conf |= (nrf.SPIM_CONFIG_CPOL_ActiveLow << nrf.SPIM_CONFIG_CPOL_Pos) - conf &^= (nrf.SPIM_CONFIG_CPHA_Leading << nrf.SPIM_CONFIG_CPHA_Pos) - case 3: - conf |= (nrf.SPIM_CONFIG_CPOL_ActiveLow << nrf.SPIM_CONFIG_CPOL_Pos) - conf |= (nrf.SPIM_CONFIG_CPHA_Trailing << nrf.SPIM_CONFIG_CPHA_Pos) - default: // to mode - conf &^= (nrf.SPIM_CONFIG_CPOL_ActiveHigh << nrf.SPIM_CONFIG_CPOL_Pos) - conf &^= (nrf.SPIM_CONFIG_CPHA_Leading << nrf.SPIM_CONFIG_CPHA_Pos) - } - spi.Bus.CONFIG.Set(conf) - - // set pins - if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 { - config.SCK = SPI0_SCK_PIN - config.SDO = SPI0_SDO_PIN - config.SDI = SPI0_SDI_PIN - } - spi.Bus.PSEL.SCK.Set(uint32(config.SCK)) - spi.Bus.PSEL.MOSI.Set(uint32(config.SDO)) - spi.Bus.PSEL.MISO.Set(uint32(config.SDI)) - - // Re-enable bus now that it is configured. - spi.Bus.ENABLE.Set(nrf.SPIM_ENABLE_ENABLE_Enabled) - - return nil -} - -// Transfer writes/reads a single byte using the SPI interface. -func (spi *SPI) Transfer(w byte) (byte, error) { - buf := spi.buf[:] - buf[0] = w - err := spi.Tx(buf[:], buf[:]) - return buf[0], err -} - -// Tx handles read/write operation for SPI interface. Since SPI is a synchronous -// write/read interface, there must always be the same number of bytes written -// as bytes read. Therefore, if the number of bytes don't match it will be -// padded until they fit: if len(w) > len(r) the extra bytes received will be -// dropped and if len(w) < len(r) extra 0 bytes will be sent. -func (spi *SPI) Tx(w, r []byte) error { - // Unfortunately the hardware (on the nrf52832) only supports up to 255 - // bytes in the buffers, so if either w or r is longer than that the - // transfer needs to be broken up in pieces. - // The nrf52840 supports far larger buffers however, which isn't yet - // supported. - for len(r) != 0 || len(w) != 0 { - // Prepare the SPI transfer: set the DMA pointers and lengths. - // read buffer - nr := uint32(len(r)) - if nr > 0 { - if nr > 255 { - nr = 255 - } - spi.Bus.RXD.PTR.Set(uint32(uintptr(unsafe.Pointer(&r[0])))) - r = r[nr:] - } - spi.Bus.RXD.MAXCNT.Set(nr) - - // write buffer - nw := uint32(len(w)) - if nw > 0 { - if nw > 255 { - nw = 255 - } - spi.Bus.TXD.PTR.Set(uint32(uintptr(unsafe.Pointer(&w[0])))) - w = w[nw:] - } - spi.Bus.TXD.MAXCNT.Set(nw) - - // Do the transfer. - // Note: this can be improved by not waiting until the transfer is - // finished if the transfer is send-only (a common case). - spi.Bus.TASKS_START.Set(1) - for spi.Bus.EVENTS_END.Get() == 0 { - } - spi.Bus.EVENTS_END.Set(0) - } - - return nil -} - -// PWM is one PWM peripheral, which consists of a counter and multiple output -// channels (that can be connected to actual pins). You can set the frequency -// using SetPeriod, but only for all the channels in this PWM peripheral at -// once. -type PWM struct { - PWM *nrf.PWM_Type - - channelValues [4]volatile.Register16 -} - -// Configure enables and configures this PWM. -// On the nRF52 series, the maximum period is around 0.26s. -func (pwm *PWM) Configure(config PWMConfig) error { - // Enable the peripheral. - pwm.PWM.ENABLE.Set(nrf.PWM_ENABLE_ENABLE_Enabled << nrf.PWM_ENABLE_ENABLE_Pos) - - // Use up counting only. TODO: allow configuring as up-and-down. - pwm.PWM.MODE.Set(nrf.PWM_MODE_UPDOWN_Up << nrf.PWM_MODE_UPDOWN_Pos) - - // Indicate there are four channels that each have a different value. - pwm.PWM.DECODER.Set(nrf.PWM_DECODER_LOAD_Individual< maxTop { - return ErrPWMPeriodTooLong - } - } - pwm.PWM.COUNTERTOP.Set(uint32(top)) - - // Apparently this is needed to apply the new COUNTERTOP. - pwm.PWM.TASKS_SEQSTART[0].Set(1) - - return nil -} - -// Top returns the current counter top, for use in duty cycle calculation. It -// will only change with a call to Configure or SetPeriod, otherwise it is -// constant. -// -// The value returned here is hardware dependent. In general, it's best to treat -// it as an opaque value that can be divided by some number and passed to -// pwm.Set (see pwm.Set for more information). -func (pwm *PWM) Top() uint32 { - return pwm.PWM.COUNTERTOP.Get() -} - -// Channel returns a PWM channel for the given pin. -func (pwm *PWM) Channel(pin Pin) (uint8, error) { - config := uint32(pin) - for ch := uint8(0); ch < 4; ch++ { - channelConfig := pwm.PWM.PSEL.OUT[ch].Get() - if channelConfig == 0xffffffff { - // Unused channel. Configure it. - pwm.PWM.PSEL.OUT[ch].Set(config) - // Configure the pin (required by the reference manual). - pin.Configure(PinConfig{Mode: PinOutput}) - // Set channel to zero and non-inverting. - pwm.channelValues[ch].Set(0x8000) - return ch, nil - } else if channelConfig == config { - // This channel is already configured for this pin. - return ch, nil - } - } - - // All four pins are already in use with other pins. - return 0, ErrInvalidOutputPin -} - -// SetInverting sets whether to invert the output of this channel. -// Without inverting, a 25% duty cycle would mean the output is high for 25% of -// the time and low for the rest. Inverting flips the output as if a NOT gate -// was placed at the output, meaning that the output would be 25% low and 75% -// high with a duty cycle of 25%. -func (pwm *PWM) SetInverting(channel uint8, inverting bool) { - ptr := &pwm.channelValues[channel] - if inverting { - ptr.Set(ptr.Get() &^ 0x8000) - } else { - ptr.Set(ptr.Get() | 0x8000) - } -} - -// Set updates the channel value. This is used to control the channel duty -// cycle. For example, to set it to a 25% duty cycle, use: -// -// ch.Set(ch.Top() / 4) -// -// ch.Set(0) will set the output to low and ch.Set(ch.Top()) will set the output -// to high, assuming the output isn't inverted. -func (pwm *PWM) Set(channel uint8, value uint32) { - // Update the channel value while retaining the polarity bit. - ptr := &pwm.channelValues[channel] - ptr.Set(ptr.Get()&0x8000 | uint16(value)&0x7fff) - - // Start the PWM, if it isn't already running. - pwm.PWM.TASKS_SEQSTART[0].Set(1) -} diff --git a/emb/machine/machine_nrf5x.go b/emb/machine/machine_nrf5x.go deleted file mode 100644 index 4c73103..0000000 --- a/emb/machine/machine_nrf5x.go +++ /dev/null @@ -1,126 +0,0 @@ -//go:build nrf51 || nrf52 - -package machine - -import "device/nrf" - -// I2C on the NRF51 and NRF52. -type I2C struct { - Bus *nrf.TWI_Type - mode I2CMode -} - -// There are 2 I2C interfaces on the NRF. -var ( - I2C0 = &I2C{Bus: nrf.TWI0} - I2C1 = &I2C{Bus: nrf.TWI1} -) - -func (i2c *I2C) enableAsController() { - i2c.Bus.ENABLE.Set(nrf.TWI_ENABLE_ENABLE_Enabled) -} - -func (i2c *I2C) enableAsTarget() { - // Not supported on this hardware -} - -func (i2c *I2C) disable() { - i2c.Bus.ENABLE.Set(0) -} - -// Tx does a single I2C transaction at the specified address. -// It clocks out the given address, writes the bytes in w, reads back len(r) -// bytes and stores them in r, and generates a stop condition on the bus. -func (i2c *I2C) Tx(addr uint16, w, r []byte) (err error) { - - // Tricky stop condition. - // After reads, the stop condition is generated implicitly with a shortcut. - // After writes not followed by reads and in the case of errors, stop must be generated explicitly. - - i2c.Bus.ADDRESS.Set(uint32(addr)) - - if len(w) != 0 { - i2c.Bus.TASKS_STARTTX.Set(1) // start transmission for writing - for _, b := range w { - if err = i2c.writeByte(b); err != nil { - i2c.signalStop() - return - } - } - } - - if len(r) != 0 { - // To trigger suspend task when a byte is received - i2c.Bus.SHORTS.Set(nrf.TWI_SHORTS_BB_SUSPEND) - i2c.Bus.TASKS_STARTRX.Set(1) // re-start transmission for reading - for i := range r { // read each char - if i+1 == len(r) { - // To trigger stop task when last byte is received, set before resume task. - i2c.Bus.SHORTS.Set(nrf.TWI_SHORTS_BB_STOP) - } - if i > 0 { - i2c.Bus.TASKS_RESUME.Set(1) // re-start transmission for reading - } - if r[i], err = i2c.readByte(); err != nil { - i2c.Bus.SHORTS.Set(nrf.TWI_SHORTS_BB_SUSPEND_Disabled) - i2c.signalStop() - return - } - } - i2c.Bus.SHORTS.Set(nrf.TWI_SHORTS_BB_SUSPEND_Disabled) - } - - if len(r) == 0 { - // Stop the I2C transaction after the write. - err = i2c.signalStop() - } else { - // The last byte read has already stopped the transaction, via - // TWI_SHORTS_BB_STOP. But we still need to wait until we receive the - // STOPPED event. - tries := 0 - for i2c.Bus.EVENTS_STOPPED.Get() == 0 { - tries++ - if tries >= i2cTimeout { - return errI2CSignalStopTimeout - } - } - i2c.Bus.EVENTS_STOPPED.Set(0) - } - - return -} - -// writeByte writes a single byte to the I2C bus and waits for confirmation. -func (i2c *I2C) writeByte(data byte) error { - tries := 0 - i2c.Bus.TXD.Set(uint32(data)) - for i2c.Bus.EVENTS_TXDSENT.Get() == 0 { - if e := i2c.Bus.EVENTS_ERROR.Get(); e != 0 { - i2c.Bus.EVENTS_ERROR.Set(0) - return errI2CBusError - } - tries++ - if tries >= i2cTimeout { - return errI2CWriteTimeout - } - } - i2c.Bus.EVENTS_TXDSENT.Set(0) - return nil -} - -// readByte reads a single byte from the I2C bus when it is ready. -func (i2c *I2C) readByte() (byte, error) { - tries := 0 - for i2c.Bus.EVENTS_RXDREADY.Get() == 0 { - if e := i2c.Bus.EVENTS_ERROR.Get(); e != 0 { - i2c.Bus.EVENTS_ERROR.Set(0) - return 0, errI2CBusError - } - tries++ - if tries >= i2cTimeout { - return 0, errI2CReadTimeout - } - } - i2c.Bus.EVENTS_RXDREADY.Set(0) - return byte(i2c.Bus.RXD.Get()), nil -} diff --git a/emb/machine/machine_nrf_bare.go b/emb/machine/machine_nrf_bare.go deleted file mode 100644 index b94886e..0000000 --- a/emb/machine/machine_nrf_bare.go +++ /dev/null @@ -1,9 +0,0 @@ -//go:build nrf && !softdevice - -package machine - -// GetRNG returns 32 bits of non-deterministic random data based on internal thermal noise. -// According to Nordic's documentation, the random output is suitable for cryptographic purposes. -func GetRNG() (ret uint32, err error) { - return getRNG() -} diff --git a/emb/machine/machine_nrf_sd.go b/emb/machine/machine_nrf_sd.go deleted file mode 100644 index b816e62..0000000 --- a/emb/machine/machine_nrf_sd.go +++ /dev/null @@ -1,59 +0,0 @@ -//go:build nrf && softdevice - -package machine - -import ( - "device/arm" - "device/nrf" - - "errors" -) - -// avoid a heap allocation in GetRNG. -var ( - softdeviceEnabled uint8 - bytesAvailable uint8 - buf [4]uint8 - - errNoSoftDeviceSupport = errors.New("rng: softdevice not supported on this device") - errNotEnoughRandomData = errors.New("rng: not enough random data available") -) - -// GetRNG returns 32 bits of non-deterministic random data based on internal thermal noise. -// According to Nordic's documentation, the random output is suitable for cryptographic purposes. -func GetRNG() (ret uint32, err error) { - // First check whether the SoftDevice is enabled. - // sd_rand_application_bytes_available_get cannot be called when the SoftDevice is not enabled. - arm.SVCall1(0x12, &softdeviceEnabled) // sd_softdevice_is_enabled - - if softdeviceEnabled == 0 { - return getRNG() - } - - // call into the SoftDevice to get random data bytes available - switch nrf.Device { - case "nrf51": - // sd_rand_application_bytes_available_get: SOC_SVC_BASE_NOT_AVAILABLE + 4 - arm.SVCall1(0x2B+4, &bytesAvailable) - case "nrf52", "nrf52840", "nrf52833": - // sd_rand_application_bytes_available_get: SOC_SVC_BASE_NOT_AVAILABLE + 4 - arm.SVCall1(0x2C+4, &bytesAvailable) - default: - return 0, errNoSoftDeviceSupport - } - - if bytesAvailable < 4 { - return 0, errNotEnoughRandomData - } - - switch nrf.Device { - case "nrf51": - // sd_rand_application_vector_get: SOC_SVC_BASE_NOT_AVAILABLE + 5 - arm.SVCall2(0x2B+5, &buf, 4) - case "nrf52", "nrf52840", "nrf52833": - // sd_rand_application_vector_get: SOC_SVC_BASE_NOT_AVAILABLE + 5 - arm.SVCall2(0x2C+5, &buf, 4) - } - - return uint32(buf[0]) | uint32(buf[1])<<8 | uint32(buf[2])<<16 | uint32(buf[3])<<24, nil -} diff --git a/emb/machine/machine_nxpmk66f18.go b/emb/machine/machine_nxpmk66f18.go deleted file mode 100644 index 5dd54d9..0000000 --- a/emb/machine/machine_nxpmk66f18.go +++ /dev/null @@ -1,291 +0,0 @@ -// Derivative work of Teensyduino Core Library -// http://www.pjrc.com/teensy/ -// Copyright (c) 2017 PJRC.COM, LLC. -// -// Permission is hereby granted, free of charge, to any person obtaining -// a copy of this software and associated documentation files (the -// "Software"), to deal in the Software without restriction, including -// without limitation the rights to use, copy, modify, merge, publish, -// distribute, sublicense, and/or sell copies of the Software, and to -// permit persons to whom the Software is furnished to do so, subject to -// the following conditions: -// -// 1. The above copyright notice and this permission notice shall be -// included in all copies or substantial portions of the Software. -// -// 2. If the Software is incorporated into a build system that allows -// selection among a list of target devices, then similar target -// devices manufactured by PJRC.COM must be included in the list of -// target devices and selectable in the same manner. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN -// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -// SOFTWARE. - -//go:build nxp && mk66f18 - -package machine - -import ( - "device/nxp" - "runtime/volatile" - "unsafe" -) - -const deviceName = nxp.Device - -const ( - PinInput PinMode = iota - PinInputPullup - PinInputPulldown - PinOutput - PinOutputOpenDrain - PinDisable -) - -// Deprecated: use PinInputPullup and PinInputPulldown instead. -const ( - PinInputPullUp = PinInputPullup - PinInputPullDown = PinInputPulldown -) - -const ( - PA00 Pin = iota - PA01 - PA02 - PA03 - PA04 - PA05 - PA06 - PA07 - PA08 - PA09 - PA10 - PA11 - PA12 - PA13 - PA14 - PA15 - PA16 - PA17 - PA18 - PA19 - PA20 - PA21 - PA22 - PA23 - PA24 - PA25 - PA26 - PA27 - PA28 - PA29 -) - -const ( - PB00 Pin = iota + 32 - PB01 - PB02 - PB03 - PB04 - PB05 - PB06 - PB07 - PB08 - PB09 - PB10 - PB11 - _ - _ - _ - _ - PB16 - PB17 - PB18 - PB19 - PB20 - PB21 - PB22 - PB23 -) - -const ( - PC00 Pin = iota + 64 - PC01 - PC02 - PC03 - PC04 - PC05 - PC06 - PC07 - PC08 - PC09 - PC10 - PC11 - PC12 - PC13 - PC14 - PC15 - PC16 - PC17 - PC18 - PC19 -) - -const ( - PD00 Pin = iota + 96 - PD01 - PD02 - PD03 - PD04 - PD05 - PD06 - PD07 - PD08 - PD09 - PD10 - PD11 - PD12 - PD13 - PD14 - PD15 -) - -const ( - PE00 Pin = iota + 128 - PE01 - PE02 - PE03 - PE04 - PE05 - PE06 - PE07 - PE08 - PE09 - PE10 - PE11 - PE12 - PE13 - PE14 - PE15 - PE16 - PE17 - PE18 - PE19 - PE20 - PE21 - PE22 - PE23 - PE24 - PE25 - PE26 - PE27 - PE28 -) - -//go:inline -func (p Pin) reg() (*nxp.GPIO_Type, *volatile.Register32, uint8) { - var gpio *nxp.GPIO_Type - var pcr *nxp.PORT_Type - - switch p / 32 { - case 0: - gpio, pcr = nxp.GPIOA, nxp.PORTA - case 1: - gpio, pcr = nxp.GPIOB, nxp.PORTB - case 2: - gpio, pcr = nxp.GPIOC, nxp.PORTC - case 3: - gpio, pcr = nxp.GPIOD, nxp.PORTD - case 5: - gpio, pcr = nxp.GPIOE, nxp.PORTE - default: - panic("invalid pin number") - } - - return gpio, &(*[32]volatile.Register32)(unsafe.Pointer(pcr))[p%32], uint8(p % 32) -} - -// Configure this pin with the given configuration. -func (p Pin) Configure(config PinConfig) { - gpio, pcr, pos := p.reg() - - switch config.Mode { - case PinOutput: - gpio.PDDR.SetBits(1 << pos) - pcr.Set((1 << nxp.PORT_PCR0_MUX_Pos) | nxp.PORT_PCR0_SRE | nxp.PORT_PCR0_DSE) - - case PinOutputOpenDrain: - gpio.PDDR.SetBits(1 << pos) - pcr.Set((1 << nxp.PORT_PCR0_MUX_Pos) | nxp.PORT_PCR0_SRE | nxp.PORT_PCR0_DSE | nxp.PORT_PCR0_ODE) - - case PinInput: - gpio.PDDR.ClearBits(1 << pos) - pcr.Set((1 << nxp.PORT_PCR0_MUX_Pos)) - - case PinInputPullup: - gpio.PDDR.ClearBits(1 << pos) - pcr.Set((1 << nxp.PORT_PCR0_MUX_Pos) | nxp.PORT_PCR0_PE | nxp.PORT_PCR0_PS) - - case PinInputPulldown: - gpio.PDDR.ClearBits(1 << pos) - pcr.Set((1 << nxp.PORT_PCR0_MUX_Pos) | nxp.PORT_PCR0_PE) - - case PinDisable: - gpio.PDDR.ClearBits(1 << pos) - pcr.Set((0 << nxp.PORT_PCR0_MUX_Pos)) - } -} - -// Set changes the value of the GPIO pin. The pin must be configured as output. -func (p Pin) Set(value bool) { - gpio, _, pos := p.reg() - if value { - gpio.PSOR.Set(1 << pos) - } else { - gpio.PCOR.Set(1 << pos) - } -} - -// Get returns the current value of a GPIO pin. -func (p Pin) Get() bool { - gpio, _, pos := p.reg() - return gpio.PDIR.HasBits(1 << pos) -} - -func (p Pin) Control() *volatile.Register32 { - _, pcr, _ := p.reg() - return pcr -} - -func (p Pin) Fast() FastPin { - gpio, _, pos := p.reg() - return FastPin{ - PDOR: gpio.PDOR.Bit(pos), - PSOR: gpio.PSOR.Bit(pos), - PCOR: gpio.PCOR.Bit(pos), - PTOR: gpio.PTOR.Bit(pos), - PDIR: gpio.PDIR.Bit(pos), - PDDR: gpio.PDDR.Bit(pos), - } -} - -type FastPin struct { - PDOR *volatile.BitRegister - PSOR *volatile.BitRegister - PCOR *volatile.BitRegister - PTOR *volatile.BitRegister - PDIR *volatile.BitRegister - PDDR *volatile.BitRegister -} - -func (p FastPin) Set() { p.PSOR.Set(true) } -func (p FastPin) Clear() { p.PCOR.Set(true) } -func (p FastPin) Toggle() { p.PTOR.Set(true) } -func (p FastPin) Write(v bool) { p.PDOR.Set(v) } -func (p FastPin) Read() bool { return p.PDIR.Get() } diff --git a/emb/machine/machine_nxpmk66f18_uart.go b/emb/machine/machine_nxpmk66f18_uart.go deleted file mode 100644 index a14d18f..0000000 --- a/emb/machine/machine_nxpmk66f18_uart.go +++ /dev/null @@ -1,309 +0,0 @@ -// Derivative work of Teensyduino Core Library -// http://www.pjrc.com/teensy/ -// Copyright (c) 2017 PJRC.COM, LLC. -// -// Permission is hereby granted, free of charge, to any person obtaining -// a copy of this software and associated documentation files (the -// "Software"), to deal in the Software without restriction, including -// without limitation the rights to use, copy, modify, merge, publish, -// distribute, sublicense, and/or sell copies of the Software, and to -// permit persons to whom the Software is furnished to do so, subject to -// the following conditions: -// -// 1. The above copyright notice and this permission notice shall be -// included in all copies or substantial portions of the Software. -// -// 2. If the Software is incorporated into a build system that allows -// selection among a list of target devices, then similar target -// devices manufactured by PJRC.COM must be included in the list of -// target devices and selectable in the same manner. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN -// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -// SOFTWARE. - -//go:build nxp && mk66f18 - -package machine - -import ( - "device/arm" - "device/nxp" - "errors" - "runtime/interrupt" - "runtime/volatile" - - _ "unsafe" // for go:linkname -) - -const ( - uartC2Enable = nxp.UART_C2_TE | nxp.UART_C2_RE | nxp.UART_C2_RIE | nxp.UART_C2_ILIE - uartC2TXActive = uartC2Enable | nxp.UART_C2_TIE - uartC2TXCompleting = uartC2Enable | nxp.UART_C2_TCIE - uartC2TXInactive = uartC2Enable - - uartIRQPriority = 64 - - // determined from UARTx_PFIFO - uartRXFIFODepth = 8 - uartTXFIFODepth = 8 -) - -var ( - ErrNotImplemented = errors.New("device has not been implemented") - ErrNotConfigured = errors.New("device has not been configured") -) - -// PutcharUART writes a byte to the UART synchronously, without using interrupts -// or calling the scheduler -func PutcharUART(u *UART, c byte) { - // ensure the UART has been configured - if !u.SCGC.HasBits(u.SCGCMask) { - u.configure(UARTConfig{}, false) - } - - for u.TCFIFO.Get() > 0 { - // busy wait - } - u.D.Set(c) - u.C2.Set(uartC2TXActive) -} - -// PollUART manually checks a UART status and calls the ISR. This should only be -// called by runtime.abort. -func PollUART(u *UART) { - if u.SCGC.HasBits(u.SCGCMask) { - u.handleStatusInterrupt(u.Interrupt) - } -} - -type UART struct { - *nxp.UART_Type - SCGC *volatile.Register32 - SCGCMask uint32 - - DefaultRX Pin - DefaultTX Pin - - // state - Buffer RingBuffer // RX Buffer - TXBuffer RingBuffer - Configured bool - Transmitting volatile.Register8 - Interrupt interrupt.Interrupt -} - -var ( - UART0 = &_UART0 - UART1 = &_UART1 - UART2 = &_UART2 - UART3 = &_UART3 - UART4 = &_UART4 - _UART0 = UART{UART_Type: nxp.UART0, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART0, DefaultRX: defaultUART0RX, DefaultTX: defaultUART0TX} - _UART1 = UART{UART_Type: nxp.UART1, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART1, DefaultRX: defaultUART1RX, DefaultTX: defaultUART1TX} - _UART2 = UART{UART_Type: nxp.UART2, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART2, DefaultRX: defaultUART2RX, DefaultTX: defaultUART2TX} - _UART3 = UART{UART_Type: nxp.UART3, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART3, DefaultRX: defaultUART3RX, DefaultTX: defaultUART3TX} - _UART4 = UART{UART_Type: nxp.UART4, SCGC: &nxp.SIM.SCGC1, SCGCMask: nxp.SIM_SCGC1_UART4, DefaultRX: defaultUART4RX, DefaultTX: defaultUART4TX} -) - -func init() { - UART0.Interrupt = interrupt.New(nxp.IRQ_UART0_RX_TX, _UART0.handleStatusInterrupt) - UART1.Interrupt = interrupt.New(nxp.IRQ_UART1_RX_TX, _UART1.handleStatusInterrupt) - UART2.Interrupt = interrupt.New(nxp.IRQ_UART2_RX_TX, _UART2.handleStatusInterrupt) - UART3.Interrupt = interrupt.New(nxp.IRQ_UART3_RX_TX, _UART3.handleStatusInterrupt) - UART4.Interrupt = interrupt.New(nxp.IRQ_UART4_RX_TX, _UART4.handleStatusInterrupt) -} - -// Configure the UART. -func (u *UART) Configure(config UARTConfig) { - u.configure(config, true) -} - -func (u *UART) configure(config UARTConfig, canSched bool) { - // from: serial_begin - - if !u.Configured { - u.Transmitting.Set(0) - - // turn on the clock - u.SCGC.Set(u.SCGCMask) - - // configure pins - u.DefaultRX.Control().Set(nxp.PORT_PCR0_PE | nxp.PORT_PCR0_PS | nxp.PORT_PCR0_PFE | (3 << nxp.PORT_PCR0_MUX_Pos)) - u.DefaultTX.Control().Set(nxp.PORT_PCR0_DSE | nxp.PORT_PCR0_SRE | (3 << nxp.PORT_PCR0_MUX_Pos)) - u.C1.Set(nxp.UART_C1_ILT) - } - - // default to 115200 baud - if config.BaudRate == 0 { - config.BaudRate = 115200 - } - - // copied from teensy core's BAUD2DIV macro - divisor := ((CPUFrequency() * 2) + (config.BaudRate >> 1)) / config.BaudRate - if divisor < 32 { - divisor = 32 - } - - if u.Configured { - // don't change baud rate mid transmit - if canSched { - u.Flush() - } else { - for u.Transmitting.Get() != 0 { - // busy wait flush - } - } - } - - // set the divisor - u.BDH.Set(uint8((divisor >> 13) & 0x1F)) - u.BDL.Set(uint8((divisor >> 5) & 0xFF)) - u.C4.Set(uint8(divisor & 0x1F)) - - if !u.Configured { - u.Configured = true - - u.C1.Set(nxp.UART_C1_ILT) - - // configure TX and RX watermark - u.TWFIFO.Set(2) // causes bit TDRE of S1 to set - u.RWFIFO.Set(4) // causes bit RDRF of S1 to set - - // enable FIFOs - u.PFIFO.Set(nxp.UART_PFIFO_TXFE | nxp.UART_PFIFO_RXFE) - - // setup interrupts - u.C2.Set(uartC2TXInactive) - u.Interrupt.SetPriority(uartIRQPriority) - u.Interrupt.Enable() - } -} - -func (u *UART) Disable() { - // from: serial_end - - // check if the device has been enabled already - if !u.SCGC.HasBits(u.SCGCMask) { - return - } - - u.Flush() - - u.Interrupt.Disable() - u.C2.Set(0) - - // reconfigure pin - u.DefaultRX.Configure(PinConfig{Mode: PinInputPullup}) - u.DefaultTX.Configure(PinConfig{Mode: PinInputPullup}) - - // clear flags - u.S1.Get() - u.D.Get() - u.Buffer.Clear() -} - -func (u *UART) Flush() { - for u.Transmitting.Get() != 0 { - gosched() - } -} - -func (u *UART) handleStatusInterrupt(interrupt.Interrupt) { - // from: uart0_status_isr - - // receive - if u.S1.HasBits(nxp.UART_S1_RDRF | nxp.UART_S1_IDLE) { - intrs := arm.DisableInterrupts() - avail := u.RCFIFO.Get() - if avail == 0 { - // The only way to clear the IDLE interrupt flag is - // to read the data register. But reading with no - // data causes a FIFO underrun, which causes the - // FIFO to return corrupted data. If anyone from - // Freescale reads this, what a poor design! There - // write should be a write-1-to-clear for IDLE. - u.D.Get() - // flushing the fifo recovers from the underrun, - // but there's a possible race condition where a - // new character could be received between reading - // RCFIFO == 0 and flushing the FIFO. To minimize - // the chance, interrupts are disabled so a higher - // priority interrupt (hopefully) doesn't delay. - // TODO: change this to disabling the IDLE interrupt - // which won't be simple, since we already manage - // which transmit interrupts are enabled. - u.CFIFO.Set(nxp.UART_CFIFO_RXFLUSH) - arm.EnableInterrupts(intrs) - - } else { - arm.EnableInterrupts(intrs) - - for { - u.Buffer.Put(u.D.Get()) - avail-- - if avail <= 0 { - break - } - } - } - } - - // transmit - if u.C2.HasBits(nxp.UART_C2_TIE) && u.S1.HasBits(nxp.UART_S1_TDRE) { - data := make([]byte, 0, uartTXFIFODepth) - avail := uartTXFIFODepth - u.TCFIFO.Get() - - // get avail bytes from ring buffer - for len(data) < int(avail) { - if b, ok := u.TXBuffer.Get(); ok { - data = append(data, b) - } else { - break - } - } - - // write data to FIFO - l := len(data) - for i, b := range data { - if i == l-1 { - // only clear TDRE on last write, per the manual - u.S1.Get() - } - u.D.Set(b) - } - - // if FIFO still has room, disable TIE, enable TCIE - if u.S1.HasBits(nxp.UART_S1_TDRE) { - u.C2.Set(uartC2TXCompleting) - } - } - - // transmit complete - if u.C2.HasBits(nxp.UART_C2_TCIE) && u.S1.HasBits(nxp.UART_S1_TC) { - u.Transmitting.Set(0) - u.C2.Set(uartC2TXInactive) - } -} - -// WriteByte writes a byte of data to the UART. -func (u *UART) writeByte(c byte) error { - if !u.Configured { - return ErrNotConfigured - } - - for !u.TXBuffer.Put(c) { - gosched() - } - - u.Transmitting.Set(1) - u.C2.Set(uartC2TXActive) - return nil -} - -func (uart *UART) flush() {} diff --git a/emb/machine/machine_rp2.go b/emb/machine/machine_rp2.go deleted file mode 100644 index 9afefa5..0000000 --- a/emb/machine/machine_rp2.go +++ /dev/null @@ -1,137 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -const deviceName = rp.Device - -const ( - // Number of spin locks available - // Note: On RP2350, most spinlocks are unusable due to Errata 2 - _NUMSPINLOCKS = 32 - _PICO_SPINLOCK_ID_IRQ = 9 - // is48Pin notes whether the chip is RP2040 with 32 pins or RP2350 with 48 pins. - is48Pin = _NUMBANK0_GPIOS == 48 -) - -// UART on the RP2040 -var ( - UART0 = &_UART0 - _UART0 = UART{ - Buffer: NewRingBuffer(), - Bus: rp.UART0, - } - - UART1 = &_UART1 - _UART1 = UART{ - Buffer: NewRingBuffer(), - Bus: rp.UART1, - } -) - -func init() { - UART0.Interrupt = interrupt.New(rp.IRQ_UART0_IRQ, _UART0.handleInterrupt) - UART1.Interrupt = interrupt.New(rp.IRQ_UART1_IRQ, _UART1.handleInterrupt) -} - -//go:linkname machineInit runtime.machineInit -func machineInit() { - // Reset all peripherals to put system into a known state, - // except for QSPI pads and the XIP IO bank, as this is fatal if running from flash - // and the PLLs, as this is fatal if clock muxing has not been reset on this boot - // and USB, syscfg, as this disturbs USB-to-SWD on core 1 - bits := ^uint32(initDontReset) - resetBlock(bits) - - // Remove reset from peripherals which are clocked only by clkSys and - // clkRef. Other peripherals stay in reset until we've configured clocks. - bits = ^uint32(initUnreset) - unresetBlockWait(bits) - - clocks.init() - - // Peripheral clocks should now all be running - unresetBlockWait(RESETS_RESET_Msk) -} - -//go:linkname ticks runtime.machineTicks -func ticks() uint64 { - return timer.timeElapsed() -} - -//go:linkname lightSleep runtime.machineLightSleep -func lightSleep(ticks uint64) { - timer.lightSleep(ticks) -} - -// CurrentCore returns the core number the call was made from. -func CurrentCore() int { - return int(rp.SIO.CPUID.Get()) -} - -// NumCores returns number of cores available on the device. -func NumCores() int { return 2 } - -// ChipVersion returns the version of the chip. 1 is returned for B0 and B1 -// chip. -func ChipVersion() uint8 { - const ( - SYSINFO_BASE = 0x40000000 - SYSINFO_CHIP_ID_OFFSET = 0x00000000 - SYSINFO_CHIP_ID_REVISION_BITS = 0xf0000000 - SYSINFO_CHIP_ID_REVISION_LSB = 28 - ) - - // First register of sysinfo is chip id - chipID := *(*uint32)(unsafe.Pointer(uintptr(SYSINFO_BASE + SYSINFO_CHIP_ID_OFFSET))) - // Version 1 == B0/B1 - version := (chipID & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB - return uint8(version) -} - -// Single DMA channel. See rp.DMA_Type. -type dmaChannel struct { - READ_ADDR volatile.Register32 - WRITE_ADDR volatile.Register32 - TRANS_COUNT volatile.Register32 - CTRL_TRIG volatile.Register32 - _ [12]volatile.Register32 // aliases -} - -// Static assignment of DMA channels to peripherals. -// Allocating them statically is good enough for now. If lots of peripherals use -// DMA, these might need to be assigned at runtime. -const ( - spi0DMAChannel = iota - spi1DMAChannel -) - -// DMA channels usable on the RP2040. -var dmaChannels = (*[12 + 4*rp2350ExtraReg]dmaChannel)(unsafe.Pointer(rp.DMA)) - -//go:inline -func boolToBit(a bool) uint32 { - if a { - return 1 - } - return 0 -} - -//go:inline -func u32max(a, b uint32) uint32 { - if a > b { - return a - } - return b -} - -//go:inline -func isReservedI2CAddr(addr uint8) bool { - return (addr&0x78) == 0 || (addr&0x78) == 0x78 -} diff --git a/emb/machine/machine_rp2040_rom.go b/emb/machine/machine_rp2040_rom.go deleted file mode 100644 index 5541e2a..0000000 --- a/emb/machine/machine_rp2040_rom.go +++ /dev/null @@ -1,254 +0,0 @@ -//go:build tinygo && rp2040 - -package machine - -import ( - "runtime/interrupt" - "unsafe" -) - -/* -// https://github.com/raspberrypi/pico-sdk -// src/rp2_common/pico_bootrom/include/pico/bootrom.h - -#define ROM_FUNC_POPCOUNT32 ROM_TABLE_CODE('P', '3') -#define ROM_FUNC_REVERSE32 ROM_TABLE_CODE('R', '3') -#define ROM_FUNC_CLZ32 ROM_TABLE_CODE('L', '3') -#define ROM_FUNC_CTZ32 ROM_TABLE_CODE('T', '3') -#define ROM_FUNC_MEMSET ROM_TABLE_CODE('M', 'S') -#define ROM_FUNC_MEMSET4 ROM_TABLE_CODE('S', '4') -#define ROM_FUNC_MEMCPY ROM_TABLE_CODE('M', 'C') -#define ROM_FUNC_MEMCPY44 ROM_TABLE_CODE('C', '4') -#define ROM_FUNC_RESET_USB_BOOT ROM_TABLE_CODE('U', 'B') -#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F') -#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X') -#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E') -#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P') -#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C') -#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X') - -#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) - -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned long uint32_t; -typedef unsigned long size_t; -typedef unsigned long uintptr_t; - -#define false 0 -#define true 1 -typedef int bool; - -#define ram_func __attribute__((section(".ramfuncs"),noinline)) - -typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code); -typedef void __attribute__((noreturn)) (*rom_reset_usb_boot_fn)(uint32_t, uint32_t); -typedef void (*flash_init_boot2_copyout_fn)(void); -typedef void (*flash_enable_xip_via_boot2_fn)(void); -typedef void (*flash_exit_xip_fn)(void); -typedef void (*flash_flush_cache_fn)(void); -typedef void (*flash_connect_internal_fn)(void); -typedef void (*flash_range_erase_fn)(uint32_t, size_t, uint32_t, uint16_t); -typedef void (*flash_range_program_fn)(uint32_t, const uint8_t*, size_t); - -static inline __attribute__((always_inline)) void __compiler_memory_barrier(void) { - __asm__ volatile ("" : : : "memory"); -} - -#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)(uintptr_t)(rom_address)) - -void *rom_func_lookup(uint32_t code) { - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18); - uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14); - return rom_table_lookup(func_table, code); -} - -void reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask) { - rom_reset_usb_boot_fn func = (rom_reset_usb_boot_fn) rom_func_lookup(ROM_FUNC_RESET_USB_BOOT); - func(usb_activity_gpio_pin_mask, disable_interface_mask); -} - -#define FLASH_BLOCK_ERASE_CMD 0xd8 - -#define FLASH_PAGE_SIZE (1u << 8) -#define FLASH_SECTOR_SIZE (1u << 12) -#define FLASH_BLOCK_SIZE (1u << 16) - -#define BOOT2_SIZE_WORDS 64 -#define XIP_BASE 0x10000000 - -static uint32_t boot2_copyout[BOOT2_SIZE_WORDS]; -static bool boot2_copyout_valid = false; - -static ram_func void flash_init_boot2_copyout() { - if (boot2_copyout_valid) - return; - for (int i = 0; i < BOOT2_SIZE_WORDS; ++i) - boot2_copyout[i] = ((uint32_t *)XIP_BASE)[i]; - __compiler_memory_barrier(); - boot2_copyout_valid = true; -} - -static ram_func void flash_enable_xip_via_boot2() { - ((void (*)(void))boot2_copyout+1)(); -} - -#define IO_QSPI_BASE 0x40018000 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB 8 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH 0x3 - -#define XIP_SSI_BASE 0x18000000 -#define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE) -#define SSI_SR_OFFSET 0x00000028 -#define SSI_DR0_OFFSET 0x00000060 -#define SSI_SR_TFNF_BITS 0x00000002 -#define SSI_SR_RFNE_BITS 0x00000008 - -void ram_func flash_cs_force(bool high) { - uint32_t field_val = high ? - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH : - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW; - - // &ioqspi_hw->io[1].ctrl - uint32_t *addr = (uint32_t*)(IO_QSPI_BASE + (1 * 8) + 4); - - *addr = ((*addr) & !IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS) - | (field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB); - -} - -// See https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_flash/flash.c#L86 -void ram_func flash_range_write(uint32_t offset, const uint8_t *data, size_t count) -{ - flash_range_program_fn flash_range_program_func = (flash_range_program_fn) rom_func_lookup(ROM_FUNC_FLASH_RANGE_PROGRAM); - flash_connect_internal_fn flash_connect_internal_func = (flash_connect_internal_fn) rom_func_lookup(ROM_FUNC_CONNECT_INTERNAL_FLASH); - flash_exit_xip_fn flash_exit_xip_func = (flash_exit_xip_fn) rom_func_lookup(ROM_FUNC_FLASH_EXIT_XIP); - flash_flush_cache_fn flash_flush_cache_func = (flash_flush_cache_fn) rom_func_lookup(ROM_FUNC_FLASH_FLUSH_CACHE); - - flash_init_boot2_copyout(); - - __compiler_memory_barrier(); - - flash_connect_internal_func(); - flash_exit_xip_func(); - - flash_range_program_func(offset, data, count); - flash_flush_cache_func(); - flash_enable_xip_via_boot2(); -} - -void ram_func flash_erase_blocks(uint32_t offset, size_t count) -{ - flash_range_erase_fn flash_range_erase_func = (flash_range_erase_fn) rom_func_lookup(ROM_FUNC_FLASH_RANGE_ERASE); - flash_connect_internal_fn flash_connect_internal_func = (flash_connect_internal_fn) rom_func_lookup(ROM_FUNC_CONNECT_INTERNAL_FLASH); - flash_exit_xip_fn flash_exit_xip_func = (flash_exit_xip_fn) rom_func_lookup(ROM_FUNC_FLASH_EXIT_XIP); - flash_flush_cache_fn flash_flush_cache_func = (flash_flush_cache_fn) rom_func_lookup(ROM_FUNC_FLASH_FLUSH_CACHE); - - flash_init_boot2_copyout(); - - __compiler_memory_barrier(); - - flash_connect_internal_func(); - flash_exit_xip_func(); - - flash_range_erase_func(offset, count, FLASH_BLOCK_SIZE, FLASH_BLOCK_ERASE_CMD); - flash_flush_cache_func(); - flash_enable_xip_via_boot2(); -} - -void ram_func flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) { - flash_connect_internal_fn flash_connect_internal_func = (flash_connect_internal_fn) rom_func_lookup(ROM_FUNC_CONNECT_INTERNAL_FLASH); - flash_exit_xip_fn flash_exit_xip_func = (flash_exit_xip_fn) rom_func_lookup(ROM_FUNC_FLASH_EXIT_XIP); - flash_flush_cache_fn flash_flush_cache_func = (flash_flush_cache_fn) rom_func_lookup(ROM_FUNC_FLASH_FLUSH_CACHE); - - flash_init_boot2_copyout(); - - __compiler_memory_barrier(); - - flash_connect_internal_func(); - flash_exit_xip_func(); - - flash_cs_force(0); - size_t tx_remaining = count; - size_t rx_remaining = count; - // We may be interrupted -- don't want FIFO to overflow if we're distracted. - const size_t max_in_flight = 16 - 2; - while (tx_remaining || rx_remaining) { - uint32_t flags = *(uint32_t*)(XIP_SSI_BASE + SSI_SR_OFFSET); - bool can_put = !!(flags & SSI_SR_TFNF_BITS); - bool can_get = !!(flags & SSI_SR_RFNE_BITS); - if (can_put && tx_remaining && rx_remaining - tx_remaining < max_in_flight) { - *(uint32_t*)(XIP_SSI_BASE + SSI_DR0_OFFSET) = *txbuf++; - --tx_remaining; - } - if (can_get && rx_remaining) { - *rxbuf++ = (uint8_t)*(uint32_t*)(XIP_SSI_BASE + SSI_DR0_OFFSET); - --rx_remaining; - } - } - flash_cs_force(1); - - flash_flush_cache_func(); - flash_enable_xip_via_boot2(); -} - -*/ -import "C" - -func enterBootloader() { - C.reset_usb_boot(0, 0) -} - -func doFlashCommand(tx []byte, rx []byte) error { - if len(tx) != len(rx) { - return errFlashInvalidWriteLength - } - - C.flash_do_cmd( - (*C.uint8_t)(unsafe.Pointer(&tx[0])), - (*C.uint8_t)(unsafe.Pointer(&rx[0])), - C.ulong(len(tx))) - - return nil -} - -// Flash related code -const memoryStart = C.XIP_BASE // memory start for purpose of erase - -func (f flashBlockDevice) writeAt(p []byte, off int64) (n int, err error) { - if writeAddress(off)+uintptr(C.XIP_BASE) > FlashDataEnd() { - return 0, errFlashCannotWritePastEOF - } - - state := interrupt.Disable() - defer interrupt.Restore(state) - - // rp2040 writes to offset, not actual address - // e.g. real address 0x10003000 is written to at - // 0x00003000 - address := writeAddress(off) - padded := flashPad(p, int(f.WriteBlockSize())) - - C.flash_range_write(C.uint32_t(address), - (*C.uint8_t)(unsafe.Pointer(&padded[0])), - C.ulong(len(padded))) - - return len(padded), nil -} - -func (f flashBlockDevice) eraseBlocks(start, length int64) error { - address := writeAddress(start * f.EraseBlockSize()) - if address+uintptr(C.XIP_BASE) > FlashDataEnd() { - return errFlashCannotErasePastEOF - } - - state := interrupt.Disable() - defer interrupt.Restore(state) - - C.flash_erase_blocks(C.uint32_t(address), C.ulong(length*f.EraseBlockSize())) - - return nil -} diff --git a/emb/machine/machine_rp2040_rtc.go b/emb/machine/machine_rp2040_rtc.go deleted file mode 100644 index 192e187..0000000 --- a/emb/machine/machine_rp2040_rtc.go +++ /dev/null @@ -1,240 +0,0 @@ -//go:build rp2040 - -// Implementation based on code located here: -// https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_rtc/rtc.c - -package machine - -import ( - "device/rp" - "errors" - "runtime/interrupt" - "unsafe" -) - -type rtcType rp.RTC_Type - -type rtcTime struct { - Year int16 - Month int8 - Day int8 - Dotw int8 - Hour int8 - Min int8 - Sec int8 -} - -var RTC = (*rtcType)(unsafe.Pointer(rp.RTC)) - -const ( - second = 1 - minute = 60 * second - hour = 60 * minute - day = 24 * hour -) - -var ( - rtcAlarmRepeats bool - rtcCallback func() - rtcEpoch = rtcTime{ - Year: 1970, Month: 1, Day: 1, Dotw: 4, Hour: 0, Min: 0, Sec: 0, - } -) - -var ( - ErrRtcDelayTooSmall = errors.New("RTC interrupt deplay is too small, shall be at least 1 second") - ErrRtcDelayTooLarge = errors.New("RTC interrupt deplay is too large, shall be no more than 1 day") -) - -// SetInterrupt configures delayed and optionally recurring interrupt by real time clock. -// -// Delay is specified in whole seconds, allowed range depends on platform. -// Zero delay disables previously configured interrupt, if any. -// -// RP2040 implementation allows delay to be up to 1 day, otherwise a respective error is emitted. -func (rtc *rtcType) SetInterrupt(delay uint32, repeat bool, callback func()) error { - - // Verify delay range - if delay > day { - return ErrRtcDelayTooLarge - } - - // De-configure delayed interrupt if delay is zero - if delay == 0 { - rtc.disableInterruptMatch() - return nil - } - - // Configure delayed interrupt - rtc.setDivider() - - rtcAlarmRepeats = repeat - rtcCallback = callback - - err := rtc.setTime(rtcEpoch) - if err != nil { - return err - } - rtc.setAlarm(toAlarmTime(delay), callback) - - return nil -} - -func toAlarmTime(delay uint32) rtcTime { - result := rtcEpoch - remainder := delay + 1 // needed "+1", otherwise alarm fires one second too early - if remainder >= hour { - result.Hour = int8(remainder / hour) - remainder %= hour - } - if remainder >= minute { - result.Min = int8(remainder / minute) - remainder %= minute - } - result.Sec = int8(remainder) - return result -} - -func (rtc *rtcType) setDivider() { - // Get clk_rtc freq and make sure it is running - rtcFreq := configuredFreq[clkRTC] - if rtcFreq == 0 { - panic("can not set RTC divider, clock is not running") - } - - // Take rtc out of reset now that we know clk_rtc is running - resetBlock(rp.RESETS_RESET_RTC) - unresetBlockWait(rp.RESETS_RESET_RTC) - - // Set up the 1 second divider. - // If rtc_freq is 400 then clkdiv_m1 should be 399 - rtcFreq -= 1 - - // Check the freq is not too big to divide - if rtcFreq > rp.RTC_CLKDIV_M1_CLKDIV_M1_Msk { - panic("can not set RTC divider, clock frequency is too big to divide") - } - - // Write divide value - rtc.CLKDIV_M1.Set(rtcFreq) -} - -// setTime configures RTC with supplied time, initialises and activates it. -func (rtc *rtcType) setTime(t rtcTime) error { - - // Disable RTC and wait while it is still running - rtc.CTRL.Set(0) - for rtc.isActive() { - } - - rtc.SETUP_0.Set((uint32(t.Year) << rp.RTC_SETUP_0_YEAR_Pos) | - (uint32(t.Month) << rp.RTC_SETUP_0_MONTH_Pos) | - (uint32(t.Day) << rp.RTC_SETUP_0_DAY_Pos)) - - rtc.SETUP_1.Set((uint32(t.Dotw) << rp.RTC_SETUP_1_DOTW_Pos) | - (uint32(t.Hour) << rp.RTC_SETUP_1_HOUR_Pos) | - (uint32(t.Min) << rp.RTC_SETUP_1_MIN_Pos) | - (uint32(t.Sec) << rp.RTC_SETUP_1_SEC_Pos)) - - // Load setup values into RTC clock domain - rtc.CTRL.SetBits(rp.RTC_CTRL_LOAD) - - // Enable RTC and wait for it to be running - rtc.CTRL.SetBits(rp.RTC_CTRL_RTC_ENABLE) - for !rtc.isActive() { - } - - return nil -} - -func (rtc *rtcType) isActive() bool { - return rtc.CTRL.HasBits(rp.RTC_CTRL_RTC_ACTIVE) -} - -// setAlarm configures alarm in RTC and arms it. -// The callback is executed in the context of an interrupt handler, -// so regular restructions for this sort of code apply: no blocking, no memory allocation, etc. -func (rtc *rtcType) setAlarm(t rtcTime, callback func()) { - - rtc.disableInterruptMatch() - - // Clear all match enable bits - rtc.IRQ_SETUP_0.ClearBits(rp.RTC_IRQ_SETUP_0_YEAR_ENA | rp.RTC_IRQ_SETUP_0_MONTH_ENA | rp.RTC_IRQ_SETUP_0_DAY_ENA) - rtc.IRQ_SETUP_1.ClearBits(rp.RTC_IRQ_SETUP_1_DOTW_ENA | rp.RTC_IRQ_SETUP_1_HOUR_ENA | rp.RTC_IRQ_SETUP_1_MIN_ENA | rp.RTC_IRQ_SETUP_1_SEC_ENA) - - // Only add to setup if it isn't -1 and set the match enable bits for things we care about - if t.Year >= 0 { - rtc.IRQ_SETUP_0.SetBits(uint32(t.Year) << rp.RTC_SETUP_0_YEAR_Pos) - rtc.IRQ_SETUP_0.SetBits(rp.RTC_IRQ_SETUP_0_YEAR_ENA) - } - - if t.Month >= 0 { - rtc.IRQ_SETUP_0.SetBits(uint32(t.Month) << rp.RTC_SETUP_0_MONTH_Pos) - rtc.IRQ_SETUP_0.SetBits(rp.RTC_IRQ_SETUP_0_MONTH_ENA) - } - - if t.Day >= 0 { - rtc.IRQ_SETUP_0.SetBits(uint32(t.Day) << rp.RTC_SETUP_0_DAY_Pos) - rtc.IRQ_SETUP_0.SetBits(rp.RTC_IRQ_SETUP_0_DAY_ENA) - } - - if t.Dotw >= 0 { - rtc.IRQ_SETUP_1.SetBits(uint32(t.Dotw) << rp.RTC_SETUP_1_DOTW_Pos) - rtc.IRQ_SETUP_1.SetBits(rp.RTC_IRQ_SETUP_1_DOTW_ENA) - } - - if t.Hour >= 0 { - rtc.IRQ_SETUP_1.SetBits(uint32(t.Hour) << rp.RTC_SETUP_1_HOUR_Pos) - rtc.IRQ_SETUP_1.SetBits(rp.RTC_IRQ_SETUP_1_HOUR_ENA) - } - - if t.Min >= 0 { - rtc.IRQ_SETUP_1.SetBits(uint32(t.Min) << rp.RTC_SETUP_1_MIN_Pos) - rtc.IRQ_SETUP_1.SetBits(rp.RTC_IRQ_SETUP_1_MIN_ENA) - } - - if t.Sec >= 0 { - rtc.IRQ_SETUP_1.SetBits(uint32(t.Sec) << rp.RTC_SETUP_1_SEC_Pos) - rtc.IRQ_SETUP_1.SetBits(rp.RTC_IRQ_SETUP_1_SEC_ENA) - } - - // Enable the IRQ at the proc - interrupt.New(rp.IRQ_RTC_IRQ, rtcHandleInterrupt).Enable() - - // Enable the IRQ at the peri - rtc.INTE.Set(rp.RTC_INTE_RTC) - - rtc.enableInterruptMatch() -} - -func (rtc *rtcType) enableInterruptMatch() { - // Set matching and wait for it to be enabled - rtc.IRQ_SETUP_0.SetBits(rp.RTC_IRQ_SETUP_0_MATCH_ENA) - for !rtc.IRQ_SETUP_0.HasBits(rp.RTC_IRQ_SETUP_0_MATCH_ACTIVE) { - } -} - -func (rtc *rtcType) disableInterruptMatch() { - // Disable matching and wait for it to stop being active - rtc.IRQ_SETUP_0.ClearBits(rp.RTC_IRQ_SETUP_0_MATCH_ENA) - for rtc.IRQ_SETUP_0.HasBits(rp.RTC_IRQ_SETUP_0_MATCH_ACTIVE) { - } -} - -func rtcHandleInterrupt(itr interrupt.Interrupt) { - // Always disable the alarm to clear the current IRQ. - // Even if it is a repeatable alarm, we don't want it to keep firing. - // If it matches on a second it can keep firing for that second. - RTC.disableInterruptMatch() - - // Call user callback function - if rtcCallback != nil { - rtcCallback() - } - - if rtcAlarmRepeats { - // If it is a repeatable alarm, reset time and re-enable the alarm. - RTC.setTime(rtcEpoch) - RTC.enableInterruptMatch() - } -} diff --git a/emb/machine/machine_rp2040_simulator.go b/emb/machine/machine_rp2040_simulator.go deleted file mode 100644 index 6c1d106..0000000 --- a/emb/machine/machine_rp2040_simulator.go +++ /dev/null @@ -1,96 +0,0 @@ -//go:build !baremetal && (ae_rp2040 || badger2040_w || badger2040 || challenger_rp2040 || elecrow_rp2040 || feather_rp2040 || gopher_badge || kb2040 || macropad_rp2040 || nano_rp2040 || pico || qtpy_rp2040 || thingplus_rp2040 || thumby || trinkey_qt2040 || tufty2040 || waveshare_rp2040_tiny || waveshare_rp2040_zero || xiao_rp2040) - -// Simulator support for the RP2040. -// -// This is *only* for the RP2040. RP2350 is a different chip with slightly -// different characteristics. - -package machine - -var PWM0 = &timerType{ - instance: 0, - frequency: 200e6, - bits: 16, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128, 256}, // actually a continuing range, TODO - channelPins: [][]Pin{ - {GPIO0, GPIO16}, // channel A (0) - {GPIO1, GPIO17}, // channel B (1) - }, -} - -var PWM1 = &timerType{ - instance: 0, - frequency: 200e6, - bits: 16, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128, 256}, - channelPins: [][]Pin{ - {GPIO2, GPIO18}, // channel A (0) - {GPIO3, GPIO19}, // channel B (1) - }, -} - -var PWM2 = &timerType{ - instance: 0, - frequency: 200e6, - bits: 16, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128, 256}, - channelPins: [][]Pin{ - {GPIO4, GPIO20}, // channel A (0) - {GPIO5, GPIO21}, // channel B (1) - }, -} - -var PWM3 = &timerType{ - instance: 0, - frequency: 200e6, - bits: 16, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128, 256}, - channelPins: [][]Pin{ - {GPIO6, GPIO22}, // channel A (0) - {GPIO7, GPIO23}, // channel B (1) - }, -} - -var PWM4 = &timerType{ - instance: 0, - frequency: 200e6, - bits: 16, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128, 256}, - channelPins: [][]Pin{ - {GPIO8, GPIO24}, // channel A (0) - {GPIO9, GPIO25}, // channel B (1) - }, -} - -var PWM5 = &timerType{ - instance: 0, - frequency: 200e6, - bits: 16, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128, 256}, - channelPins: [][]Pin{ - {GPIO10, GPIO26}, // channel A (0) - {GPIO11, GPIO27}, // channel B (1) - }, -} - -var PWM6 = &timerType{ - instance: 0, - frequency: 200e6, - bits: 16, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128, 256}, - channelPins: [][]Pin{ - {GPIO12, GPIO28}, // channel A (0) - {GPIO13, GPIO29}, // channel B (1) - }, -} - -var PWM7 = &timerType{ - instance: 0, - frequency: 200e6, - bits: 16, - prescalers: []int{1, 2, 4, 8, 16, 32, 64, 128, 256}, - channelPins: [][]Pin{ - {GPIO14}, // channel A (0) - {GPIO15}, // channel B (1) - }, -} diff --git a/emb/machine/machine_rp2040_usb.go b/emb/machine/machine_rp2040_usb.go deleted file mode 100644 index 087e3bf..0000000 --- a/emb/machine/machine_rp2040_usb.go +++ /dev/null @@ -1,148 +0,0 @@ -//go:build rp2040 - -package machine - -import ( - "device/rp" - "machine/usb" - "runtime/interrupt" -) - -// Configure the USB peripheral. The config is here for compatibility with the UART interface. -func (dev *USBDevice) Configure(config UARTConfig) { - // Reset usb controller - resetBlock(rp.RESETS_RESET_USBCTRL) - unresetBlockWait(rp.RESETS_RESET_USBCTRL) - - // Clear any previous state in dpram just in case - _usbDPSRAM.clear() - - // Enable USB interrupt at processor - rp.USBCTRL_REGS.INTE.Set(0) - intr := interrupt.New(rp.IRQ_USBCTRL_IRQ, handleUSBIRQ) - intr.SetPriority(0x00) - intr.Enable() - irqSet(rp.IRQ_USBCTRL_IRQ, true) - - // Mux the controller to the onboard usb phy - rp.USBCTRL_REGS.USB_MUXING.Set(rp.USBCTRL_REGS_USB_MUXING_TO_PHY | rp.USBCTRL_REGS_USB_MUXING_SOFTCON) - - // Force VBUS detect so the device thinks it is plugged into a host - rp.USBCTRL_REGS.USB_PWR.Set(rp.USBCTRL_REGS_USB_PWR_VBUS_DETECT | rp.USBCTRL_REGS_USB_PWR_VBUS_DETECT_OVERRIDE_EN) - - // Enable the USB controller in device mode. - rp.USBCTRL_REGS.MAIN_CTRL.Set(rp.USBCTRL_REGS_MAIN_CTRL_CONTROLLER_EN) - - // Enable an interrupt per EP0 transaction - rp.USBCTRL_REGS.SIE_CTRL.Set(rp.USBCTRL_REGS_SIE_CTRL_EP0_INT_1BUF) - - // Enable interrupts for when a buffer is done, when the bus is reset, - // and when a setup packet is received - rp.USBCTRL_REGS.INTE.Set(rp.USBCTRL_REGS_INTE_BUFF_STATUS | - rp.USBCTRL_REGS_INTE_BUS_RESET | - rp.USBCTRL_REGS_INTE_SETUP_REQ) - - // Present full speed device by enabling pull up on DP - rp.USBCTRL_REGS.SIE_CTRL.SetBits(rp.USBCTRL_REGS_SIE_CTRL_PULLUP_EN) -} - -func handleUSBIRQ(intr interrupt.Interrupt) { - status := rp.USBCTRL_REGS.INTS.Get() - - // Setup packet received - if (status & rp.USBCTRL_REGS_INTS_SETUP_REQ) > 0 { - rp.USBCTRL_REGS.SIE_STATUS.Set(rp.USBCTRL_REGS_SIE_STATUS_SETUP_REC) - setup := usb.NewSetup(_usbDPSRAM.setupBytes()) - - ok := false - if (setup.BmRequestType & usb.REQUEST_TYPE) == usb.REQUEST_STANDARD { - // Standard Requests - ok = handleStandardSetup(setup) - } else { - // Class Interface Requests - if setup.WIndex < uint16(len(usbSetupHandler)) && usbSetupHandler[setup.WIndex] != nil { - ok = usbSetupHandler[setup.WIndex](setup) - } - } - - if !ok { - // Stall endpoint? - USBDev.SetStallEPIn(0) - } - - } - - // Buffer status, one or more buffers have completed - if (status & rp.USBCTRL_REGS_INTS_BUFF_STATUS) > 0 { - if sendOnEP0DATADONE.offset > 0 { - ep := uint32(0) - data := sendOnEP0DATADONE.data - count := len(data) - sendOnEP0DATADONE.offset - if ep == 0 && count > usb.EndpointPacketSize { - count = usb.EndpointPacketSize - } - - sendViaEPIn(ep, data[sendOnEP0DATADONE.offset:], count) - sendOnEP0DATADONE.offset += count - if sendOnEP0DATADONE.offset == len(data) { - sendOnEP0DATADONE.offset = 0 - } - } - - s2 := rp.USBCTRL_REGS.BUFF_STATUS.Get() - - // OUT (PC -> rp2040) - for i := 0; i < 16; i++ { - if s2&(1<<(i*2+1)) > 0 { - buf := handleEndpointRx(uint32(i)) - if usbRxHandler[i] == nil || usbRxHandler[i](buf) { - AckUsbOutTransfer(uint32(i)) - } - } - } - - // IN (rp2040 -> PC) - for i := 0; i < 16; i++ { - if s2&(1<<(i*2)) > 0 { - if usbTxHandler[i] != nil { - usbTxHandler[i]() - } - } - } - - rp.USBCTRL_REGS.BUFF_STATUS.Set(s2) - } - - // Bus is reset - if (status & rp.USBCTRL_REGS_INTS_BUS_RESET) > 0 { - rp.USBCTRL_REGS.SIE_STATUS.Set(rp.USBCTRL_REGS_SIE_STATUS_BUS_RESET) - fixRP2040UsbDeviceEnumeration() - - rp.USBCTRL_REGS.ADDR_ENDP.Set(0) - initEndpoint(0, usb.ENDPOINT_TYPE_CONTROL) - } -} - -func handleUSBSetAddress(setup usb.Setup) bool { - // Using 570μs timeout which is exactly the same as SAMD21. - const ackTimeout = 570 - - rp.USBCTRL_REGS.SIE_STATUS.Set(rp.USBCTRL_REGS_SIE_STATUS_ACK_REC) - sendUSBPacket(0, []byte{}, 0) - - // Wait for transfer to complete with a timeout. - t := timer.timeElapsed() - for (rp.USBCTRL_REGS.SIE_STATUS.Get() & rp.USBCTRL_REGS_SIE_STATUS_ACK_REC) == 0 { - if dt := timer.timeElapsed() - t; dt >= ackTimeout { - return false - } - } - - // Set the device address to that requested by host. - rp.USBCTRL_REGS.ADDR_ENDP.Set(uint32(setup.WValueL) & rp.USBCTRL_REGS_ADDR_ENDP_ADDRESS_Msk) - return true -} - -func armEPZeroStall() { - rp.USBCTRL_REGS.EP_STALL_ARM.Set(rp.USBCTRL_REGS_EP_STALL_ARM_EP0_IN) -} diff --git a/emb/machine/machine_rp2040_usb_fix_usb_device_enumeration.go b/emb/machine/machine_rp2040_usb_fix_usb_device_enumeration.go deleted file mode 100644 index f027f94..0000000 --- a/emb/machine/machine_rp2040_usb_fix_usb_device_enumeration.go +++ /dev/null @@ -1,120 +0,0 @@ -//go:build rp2040 - -package machine - -import ( - "device/arm" - "device/rp" -) - -// https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c -// According to errata RP2040-E5: -// "It is safe (and inexpensive) to enable the software workaround even when using versions of RP2040 -// which include the fix in hardware." -// So let us always use the software fix. -func fixRP2040UsbDeviceEnumeration() { - // After coming out of reset, the hardware expects 800us of LS_J (linestate J) time - // before it will move to the connected state. However on a hub that broadcasts packets - // for other devices this isn't the case. The plan here is to wait for the end of the bus - // reset, force an LS_J for 1ms and then switch control back to the USB phy. Unfortunately - // this requires us to use GPIO15 as there is no other way to force the input path. - // We only need to force DP as DM can be left at zero. It will be gated off by GPIO - // logic if it isn't func selected. - - // Wait SE0 phase will call force ls_j phase which will call finish phase - hw_enumeration_fix_wait_se0() -} - -func hw_enumeration_fix_wait_se0() { - // Wait for SE0 to end (i.e. the host to stop resetting). This reset can last quite long. - // 10-15ms so we are going to set a timer callback. - - // if timer pool disabled, or no timer available, have to busy wait. - hw_enumeration_fix_busy_wait_se0() -} - -const ( - LS_SE0 = 0b00 - LS_J = 0b01 - LS_K = 0b10 - LS_SE1 = 0b11 -) - -const ( - dp = 15 -) - -var ( - gpioCtrlPrev uint32 - padCtrlPrev uint32 -) - -func hw_enumeration_fix_busy_wait_se0() { - for ((rp.USBCTRL_REGS.SIE_STATUS.Get() & rp.USBCTRL_REGS_SIE_STATUS_LINE_STATE_Msk) >> rp.USBCTRL_REGS_SIE_STATUS_LINE_STATE_Pos) == LS_SE0 { - } - - // Now force LS_J (next stage of fix) - hw_enumeration_fix_force_ls_j() -} - -func hw_enumeration_fix_force_ls_j() { - // DM must be 0 for this to work. This is true if it is selected - // to any other function. fn 8 on this pin is only for debug so shouldn't - // be selected - - // Before changing any pin state, take a copy of the current gpio control register - gpioCtrlPrev = ioBank0.io[dp].ctrl.Get() - // Also take a copy of the pads register - padCtrlPrev = padsBank0.io[dp].Get() - - // Enable bus keep and force pin to tristate, so USB DP muxing doesn't affect - // pin state - padsBank0.io[dp].SetBits(rp.PADS_BANK0_GPIO0_PUE | rp.PADS_BANK0_GPIO0_PDE) - ioBank0.io[dp].ctrl.ReplaceBits(rp.IO_BANK0_GPIO0_CTRL_OEOVER_DISABLE, rp.IO_BANK0_GPIO0_CTRL_OEOVER_Msk>>rp.IO_BANK0_GPIO0_CTRL_OEOVER_Pos, rp.IO_BANK0_GPIO0_CTRL_OEOVER_Pos) - - // Select function 8 (USB debug muxing) without disturbing other controls - ioBank0.io[dp].ctrl.ReplaceBits(8, rp.IO_BANK0_GPIO0_CTRL_FUNCSEL_Msk>>rp.IO_BANK0_GPIO0_CTRL_FUNCSEL_Pos, rp.IO_BANK0_GPIO0_CTRL_FUNCSEL_Pos) - - // J state is a differential 1 for a full speed device so - // DP = 1 and DM = 0. Don't actually need to set DM low as it - // is already gated assuming it isn't funcseld. - ioBank0.io[dp].ctrl.ReplaceBits(rp.IO_BANK0_GPIO1_CTRL_INOVER_HIGH, rp.IO_BANK0_GPIO1_CTRL_INOVER_Msk>>rp.IO_BANK0_GPIO1_CTRL_INOVER_Pos, rp.IO_BANK0_GPIO1_CTRL_INOVER_Pos) - - // Force PHY pull up to stay before switching away from the phy - rp.USBCTRL_REGS.USBPHY_DIRECT.SetBits(rp.USBCTRL_REGS_USBPHY_DIRECT_DP_PULLUP_EN) - rp.USBCTRL_REGS.USBPHY_DIRECT_OVERRIDE.SetBits(rp.USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN) - - // Switch to GPIO phy with LS_J forced - rp.USBCTRL_REGS.USB_MUXING.Set(rp.USBCTRL_REGS_USB_MUXING_TO_DIGITAL_PAD | rp.USBCTRL_REGS_USB_MUXING_SOFTCON) - - // LS_J is now forced but while loop to wait ~800us here just to check - waitCycles(25000) - - // if timer pool disabled, or no timer available, have to busy wait. - hw_enumeration_fix_finish() - -} - -func hw_enumeration_fix_finish() { - // Should think we are connected now - for (rp.USBCTRL_REGS.SIE_STATUS.Get() & rp.USBCTRL_REGS_SIE_STATUS_CONNECTED) != rp.USBCTRL_REGS_SIE_STATUS_CONNECTED { - } - - // Switch back to USB phy - rp.USBCTRL_REGS.USB_MUXING.Set(rp.USBCTRL_REGS_USB_MUXING_TO_PHY | rp.USBCTRL_REGS_USB_MUXING_SOFTCON) - - // Get rid of DP pullup override - rp.USBCTRL_REGS.USBPHY_DIRECT_OVERRIDE.ClearBits(rp.USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN) - - // Finally, restore the gpio ctrl value back to GPIO15 - ioBank0.io[dp].ctrl.Set(gpioCtrlPrev) - // Restore the pad ctrl value - padsBank0.io[dp].Set(padCtrlPrev) -} - -func waitCycles(n int) { - for n > 0 { - arm.Asm("nop") - n-- - } -} diff --git a/emb/machine/machine_rp2350_rom.go b/emb/machine/machine_rp2350_rom.go deleted file mode 100644 index 665464a..0000000 --- a/emb/machine/machine_rp2350_rom.go +++ /dev/null @@ -1,560 +0,0 @@ -//go:build tinygo && rp2350 - -package machine - -import ( - "runtime/interrupt" - "unsafe" -) - -/* -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned long uint32_t; -typedef unsigned long size_t; -typedef unsigned long uintptr_t; -typedef long int intptr_t; - -typedef const volatile uint16_t io_ro_16; -typedef const volatile uint32_t io_ro_32; -typedef volatile uint16_t io_rw_16; -typedef volatile uint32_t io_rw_32; -typedef volatile uint32_t io_wo_32; - -#define false 0 -#define true 1 -typedef int bool; - -#define ram_func __attribute__((section(".ramfuncs"),noinline)) - -typedef void (*flash_exit_xip_fn)(void); -typedef void (*flash_flush_cache_fn)(void); -typedef void (*flash_connect_internal_fn)(void); -typedef void (*flash_range_erase_fn)(uint32_t, size_t, uint32_t, uint16_t); -typedef void (*flash_range_program_fn)(uint32_t, const uint8_t*, size_t); -static inline __attribute__((always_inline)) void __compiler_memory_barrier(void) { - __asm__ volatile ("" : : : "memory"); -} - -// https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf -// 13.9. Predefined OTP Data Locations -// OTP_DATA: FLASH_DEVINFO Register - -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_BITS 0x0F00 -#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_LSB 8 -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_BITS 0xF000 -#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_LSB 12 - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2350/hardware_regs/include/hardware/regs/addressmap.h - -#define REG_ALIAS_RW_BITS (0x0 << 12) -#define REG_ALIAS_XOR_BITS (0x1 << 12) -#define REG_ALIAS_SET_BITS (0x2 << 12) -#define REG_ALIAS_CLR_BITS (0x3 << 12) - -#define XIP_BASE 0x10000000 -#define XIP_QMI_BASE 0x400d0000 -#define IO_QSPI_BASE 0x40030000 -#define BOOTRAM_BASE 0x400e0000 - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2_common/hardware_base/include/hardware/address_mapped.h - -#define hw_alias_check_addr(addr) ((uintptr_t)(addr)) -#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS + hw_alias_check_addr(addr))) -#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS + hw_alias_check_addr(addr))) -#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS + hw_alias_check_addr(addr))) - -__attribute__((always_inline)) -static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { - *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask; -} - -__attribute__((always_inline)) -static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { - *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask; -} - -__attribute__((always_inline)) -static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { - *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask; -} - -__attribute__((always_inline)) -static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) { - hw_xor_bits(addr, (*addr ^ values) & write_mask); -} - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2_common/pico_platform_compiler/include/pico/platform/compiler.h - -#define pico_default_asm_volatile(...) __asm volatile (".syntax unified\n" __VA_ARGS__) - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2350/pico_platform/include/pico/platform.h - -static bool pico_processor_state_is_nonsecure(void) { -// // todo add a define to disable NS checking at all? -// // IDAU-Exempt addresses return S=1 when tested in the Secure state, -// // whereas executing a tt in the NonSecure state will always return S=0. -// uint32_t tt; -// pico_default_asm_volatile ( -// "movs %0, #0\n" -// "tt %0, %0\n" -// : "=r" (tt) : : "cc" -// ); -// return !(tt & (1u << 22)); - - return false; -} - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2_common/pico_bootrom/include/pico/bootrom_constants.h - -// RP2040 & RP2350 -#define ROM_DATA_SOFTWARE_GIT_REVISION ROM_TABLE_CODE('G', 'R') -#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X') -#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X') -#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C') -#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F') -#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E') -#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P') - -// RP2350 only -#define ROM_FUNC_PICK_AB_PARTITION ROM_TABLE_CODE('A', 'B') -#define ROM_FUNC_CHAIN_IMAGE ROM_TABLE_CODE('C', 'I') -#define ROM_FUNC_EXPLICIT_BUY ROM_TABLE_CODE('E', 'B') -#define ROM_FUNC_FLASH_RUNTIME_TO_STORAGE_ADDR ROM_TABLE_CODE('F', 'A') -#define ROM_DATA_FLASH_DEVINFO16_PTR ROM_TABLE_CODE('F', 'D') -#define ROM_FUNC_FLASH_OP ROM_TABLE_CODE('F', 'O') -#define ROM_FUNC_GET_B_PARTITION ROM_TABLE_CODE('G', 'B') -#define ROM_FUNC_GET_PARTITION_TABLE_INFO ROM_TABLE_CODE('G', 'P') -#define ROM_FUNC_GET_SYS_INFO ROM_TABLE_CODE('G', 'S') -#define ROM_FUNC_GET_UF2_TARGET_PARTITION ROM_TABLE_CODE('G', 'U') -#define ROM_FUNC_LOAD_PARTITION_TABLE ROM_TABLE_CODE('L', 'P') -#define ROM_FUNC_OTP_ACCESS ROM_TABLE_CODE('O', 'A') -#define ROM_DATA_PARTITION_TABLE_PTR ROM_TABLE_CODE('P', 'T') -#define ROM_FUNC_FLASH_RESET_ADDRESS_TRANS ROM_TABLE_CODE('R', 'A') -#define ROM_FUNC_REBOOT ROM_TABLE_CODE('R', 'B') -#define ROM_FUNC_SET_ROM_CALLBACK ROM_TABLE_CODE('R', 'C') -#define ROM_FUNC_SECURE_CALL ROM_TABLE_CODE('S', 'C') -#define ROM_FUNC_SET_NS_API_PERMISSION ROM_TABLE_CODE('S', 'P') -#define ROM_FUNC_BOOTROM_STATE_RESET ROM_TABLE_CODE('S', 'R') -#define ROM_FUNC_SET_BOOTROM_STACK ROM_TABLE_CODE('S', 'S') -#define ROM_DATA_SAVED_XIP_SETUP_FUNC_PTR ROM_TABLE_CODE('X', 'F') -#define ROM_FUNC_FLASH_SELECT_XIP_READ_MODE ROM_TABLE_CODE('X', 'M') -#define ROM_FUNC_VALIDATE_NS_BUFFER ROM_TABLE_CODE('V', 'B') - -#define BOOTSEL_FLAG_GPIO_PIN_SPECIFIED 0x20 - -#define BOOTROM_FUNC_TABLE_OFFSET 0x14 - -// todo remove this (or #ifdef it for A1/A2) -#define BOOTROM_IS_A2() ((*(volatile uint8_t *)0x13) == 2) -#define BOOTROM_WELL_KNOWN_PTR_SIZE (BOOTROM_IS_A2() ? 2 : 4) - -#define BOOTROM_VTABLE_OFFSET 0x00 -#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_FUNC_TABLE_OFFSET + BOOTROM_WELL_KNOWN_PTR_SIZE) - - -// https://github.com/raspberrypi/pico-sdk -// src/common/boot_picoboot_headers/include/boot/picoboot_constants.h - -// values 0-7 are secure/non-secure -#define REBOOT2_FLAG_REBOOT_TYPE_NORMAL 0x0 // param0 = diagnostic partition -#define REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL 0x2 // param0 = bootsel_flags, param1 = gpio_config -#define REBOOT2_FLAG_REBOOT_TYPE_RAM_IMAGE 0x3 // param0 = image_base, param1 = image_end -#define REBOOT2_FLAG_REBOOT_TYPE_FLASH_UPDATE 0x4 // param0 = update_base - -#define REBOOT2_FLAG_NO_RETURN_ON_SUCCESS 0x100 - -#define RT_FLAG_FUNC_ARM_SEC 0x0004 -#define RT_FLAG_FUNC_ARM_NONSEC 0x0010 -#define RT_FLAG_DATA 0x0040 - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2_common/pico_bootrom/include/pico/bootrom.h - -#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) - -typedef void *(*rom_table_lookup_fn)(uint32_t code, uint32_t mask); - -__attribute__((always_inline)) -static void *rom_func_lookup_inline(uint32_t code) { - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_OFFSET); - if (pico_processor_state_is_nonsecure()) { - return rom_table_lookup(code, RT_FLAG_FUNC_ARM_NONSEC); - } else { - return rom_table_lookup(code, RT_FLAG_FUNC_ARM_SEC); - } -} - -__attribute__((always_inline)) -static void *rom_data_lookup_inline(uint32_t code) { - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_OFFSET); - return rom_table_lookup(code, RT_FLAG_DATA); -} - -typedef int (*rom_reboot_fn)(uint32_t flags, uint32_t delay_ms, uint32_t p0, uint32_t p1); - -__attribute__((always_inline)) -int rom_reboot(uint32_t flags, uint32_t delay_ms, uint32_t p0, uint32_t p1) { - rom_reboot_fn func = (rom_reboot_fn) rom_func_lookup_inline(ROM_FUNC_REBOOT); - return func(flags, delay_ms, p0, p1); -} - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2_common/pico_bootrom/bootrom.c - -void reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask) { - uint32_t flags = disable_interface_mask; - if (usb_activity_gpio_pin_mask) { - flags |= BOOTSEL_FLAG_GPIO_PIN_SPECIFIED; - // the parameter is actually the gpio number, but we only care if BOOTSEL_FLAG_GPIO_PIN_SPECIFIED - usb_activity_gpio_pin_mask = (uint32_t)__builtin_ctz(usb_activity_gpio_pin_mask); - } - rom_reboot(REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL | REBOOT2_FLAG_NO_RETURN_ON_SUCCESS, 10, flags, usb_activity_gpio_pin_mask); - __builtin_unreachable(); -} - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2350/hardware_regs/include/hardware/regs/qmi.h - -#define QMI_DIRECT_CSR_EN_BITS 0x00000001 -#define QMI_DIRECT_CSR_RXEMPTY_BITS 0x00010000 -#define QMI_DIRECT_CSR_TXFULL_BITS 0x00000400 -#define QMI_M1_WFMT_RESET 0x00001000 -#define QMI_M1_WCMD_RESET 0x0000a002 - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2350/hardware_regs/include/hardware/regs/io_qspi.h - -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB 12 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH 0x3 - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2350/hardware_structs/include/hardware/structs/io_qspi.h - -typedef struct { - io_rw_32 inte; // IO_QSPI_PROC0_INTE - io_rw_32 intf; // IO_QSPI_PROC0_INTF - io_ro_32 ints; // IO_QSPI_PROC0_INTS -} io_qspi_irq_ctrl_hw_t; - -typedef struct { - io_ro_32 status; // IO_QSPI_GPIO_QSPI_SCLK_STATUS - io_rw_32 ctrl; // IO_QSPI_GPIO_QSPI_SCLK_CTRL -} io_qspi_status_ctrl_hw_t; - -typedef struct { - io_ro_32 usbphy_dp_status; // IO_QSPI_USBPHY_DP_STATUS - io_rw_32 usbphy_dp_ctrl; // IO_QSPI_USBPHY_DP_CTRL - io_ro_32 usbphy_dm_status; // IO_QSPI_USBPHY_DM_STATUS - io_rw_32 usbphy_dm_ctrl; // IO_QSPI_USBPHY_DM_CTRL - io_qspi_status_ctrl_hw_t io[6]; - uint32_t _pad0[112]; - io_ro_32 irqsummary_proc0_secure; // IO_QSPI_IRQSUMMARY_PROC0_SECURE - io_ro_32 irqsummary_proc0_nonsecure; // IO_QSPI_IRQSUMMARY_PROC0_NONSECURE - io_ro_32 irqsummary_proc1_secure; // IO_QSPI_IRQSUMMARY_PROC1_SECURE - io_ro_32 irqsummary_proc1_nonsecure; // IO_QSPI_IRQSUMMARY_PROC1_NONSECURE - io_ro_32 irqsummary_dormant_wake_secure; // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE - io_ro_32 irqsummary_dormant_wake_nonsecure; // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE - io_rw_32 intr; // IO_QSPI_INTR - - union { - struct { - io_qspi_irq_ctrl_hw_t proc0_irq_ctrl; - io_qspi_irq_ctrl_hw_t proc1_irq_ctrl; - io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl; - }; - io_qspi_irq_ctrl_hw_t irq_ctrl[3]; - }; -} io_qspi_hw_t; - -#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE) - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2350/hardware_structs/include/hardware/structs/qmi.h - -typedef struct { - io_rw_32 timing; // QMI_M0_TIMING - io_rw_32 rfmt; // QMI_M0_RFMT - io_rw_32 rcmd; // QMI_M0_RCMD - io_rw_32 wfmt; // QMI_M0_WFMT - io_rw_32 wcmd; // QMI_M0_WCMD -} qmi_mem_hw_t; - -typedef struct { - io_rw_32 direct_csr; // QMI_DIRECT_CSR - io_wo_32 direct_tx; // QMI_DIRECT_TX - io_ro_32 direct_rx; // QMI_DIRECT_RX - qmi_mem_hw_t m[2]; - io_rw_32 atrans[8]; // QMI_ATRANS0 -} qmi_hw_t; - -#define qmi_hw ((qmi_hw_t *)XIP_QMI_BASE) - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2_common/hardware_xip_cache/include/hardware/xip_cache.h - -// Noop unless using XIP Cache-as-SRAM -// Non-noop version in src/rp2_common/hardware_xip_cache/xip_cache.c -static inline void xip_cache_clean_all(void) {} - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2_common/hardware_flash/include/hardware/flash.h - -#define FLASH_PAGE_SIZE (1u << 8) -#define FLASH_SECTOR_SIZE (1u << 12) -#define FLASH_BLOCK_SIZE (1u << 16) - - -// https://github.com/raspberrypi/pico-sdk -// src/rp2_common/hardware_flash/flash.c - -#define BOOT2_SIZE_WORDS 64 -#define FLASH_BLOCK_ERASE_CMD 0xd8 - -static uint32_t boot2_copyout[BOOT2_SIZE_WORDS]; -static bool boot2_copyout_valid = false; - -static ram_func void flash_init_boot2_copyout(void) { - if (boot2_copyout_valid) - return; - for (int i = 0; i < BOOT2_SIZE_WORDS; ++i) - boot2_copyout[i] = ((uint32_t *)BOOTRAM_BASE)[i]; - __compiler_memory_barrier(); - boot2_copyout_valid = true; -} - -static ram_func void flash_enable_xip_via_boot2(void) { - ((void (*)(void))((intptr_t)boot2_copyout+1))(); -} - -// This is a static symbol because the layout of FLASH_DEVINFO is liable to change from device to -// device, so fields must have getters/setters. -static io_rw_16 * ram_func flash_devinfo_ptr(void) { - // Note the lookup returns a pointer to a 32-bit pointer literal in the ROM - io_rw_16 **p = (io_rw_16 **) rom_data_lookup_inline(ROM_DATA_FLASH_DEVINFO16_PTR); - return *p; -} - -// This is a RAM function because may be called during flash programming to enable save/restore of -// QMI window 1 registers on RP2350: -uint8_t ram_func flash_devinfo_get_cs_size(uint8_t cs) { - io_ro_16 *devinfo = (io_ro_16 *) flash_devinfo_ptr(); - if (cs == 0u) { - return (uint8_t) ( - (*devinfo & OTP_DATA_FLASH_DEVINFO_CS0_SIZE_BITS) >> OTP_DATA_FLASH_DEVINFO_CS0_SIZE_LSB - ); - } else { - return (uint8_t) ( - (*devinfo & OTP_DATA_FLASH_DEVINFO_CS1_SIZE_BITS) >> OTP_DATA_FLASH_DEVINFO_CS1_SIZE_LSB - ); - } -} - -// This is specifically for saving/restoring the registers modified by RP2350 -// flash_exit_xip() ROM func, not the entirety of the QMI window state. -typedef struct flash_rp2350_qmi_save_state { - uint32_t timing; - uint32_t rcmd; - uint32_t rfmt; -} flash_rp2350_qmi_save_state_t; - -static ram_func void flash_rp2350_save_qmi_cs1(flash_rp2350_qmi_save_state_t *state) { - state->timing = qmi_hw->m[1].timing; - state->rcmd = qmi_hw->m[1].rcmd; - state->rfmt = qmi_hw->m[1].rfmt; -} - -static ram_func void flash_rp2350_restore_qmi_cs1(const flash_rp2350_qmi_save_state_t *state) { - if (flash_devinfo_get_cs_size(1) == 0) { - // Case 1: The RP2350 ROM sets QMI to a clean (03h read) configuration - // during flash_exit_xip(), even though when CS1 is not enabled via - // FLASH_DEVINFO it does not issue an XIP exit sequence to CS1. In - // this case, restore the original register config for CS1 as it is - // still the correct config. - qmi_hw->m[1].timing = state->timing; - qmi_hw->m[1].rcmd = state->rcmd; - qmi_hw->m[1].rfmt = state->rfmt; - } else { - // Case 2: If RAM is attached to CS1, and the ROM has issued an XIP - // exit sequence to it, then the ROM re-initialisation of the QMI - // registers has actually not gone far enough. The old XIP write mode - // is no longer valid when the QSPI RAM is returned to a serial - // command state. Restore the default 02h serial write command config. - qmi_hw->m[1].wfmt = QMI_M1_WFMT_RESET; - qmi_hw->m[1].wcmd = QMI_M1_WCMD_RESET; - } -} - -void ram_func flash_cs_force(bool high) { - uint32_t field_val = high ? - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH : - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW; - hw_write_masked(&io_qspi_hw->io[1].ctrl, - field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB, - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS - ); -} - -// Adapted from flash_range_program() -void ram_func flash_range_write(uint32_t offset, const uint8_t *data, size_t count) { - flash_connect_internal_fn flash_connect_internal_func = (flash_connect_internal_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); - flash_exit_xip_fn flash_exit_xip_func = (flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); - flash_range_program_fn flash_range_program_func = (flash_range_program_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM); - flash_flush_cache_fn flash_flush_cache_func = (flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); - flash_init_boot2_copyout(); - xip_cache_clean_all(); - flash_rp2350_qmi_save_state_t qmi_save; - flash_rp2350_save_qmi_cs1(&qmi_save); - - __compiler_memory_barrier(); - - flash_connect_internal_func(); - flash_exit_xip_func(); - flash_range_program_func(offset, data, count); - flash_flush_cache_func(); // Note this is needed to remove CSn IO force as well as cache flushing - flash_enable_xip_via_boot2(); - flash_rp2350_restore_qmi_cs1(&qmi_save); -} - -// Adapted from flash_range_erase() -void ram_func flash_erase_blocks(uint32_t offset, size_t count) { - flash_connect_internal_fn flash_connect_internal_func = (flash_connect_internal_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); - flash_exit_xip_fn flash_exit_xip_func = (flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); - flash_range_erase_fn flash_range_erase_func = (flash_range_erase_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE); - flash_flush_cache_fn flash_flush_cache_func = (flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); - flash_init_boot2_copyout(); - // Commit any pending writes to external RAM, to avoid losing them in the subsequent flush: - xip_cache_clean_all(); - flash_rp2350_qmi_save_state_t qmi_save; - flash_rp2350_save_qmi_cs1(&qmi_save); - - // No flash accesses after this point - __compiler_memory_barrier(); - - flash_connect_internal_func(); - flash_exit_xip_func(); - flash_range_erase_func(offset, count, FLASH_BLOCK_SIZE, FLASH_BLOCK_ERASE_CMD); - flash_flush_cache_func(); // Note this is needed to remove CSn IO force as well as cache flushing - flash_enable_xip_via_boot2(); - flash_rp2350_restore_qmi_cs1(&qmi_save); -} - -void ram_func flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) { - flash_connect_internal_fn flash_connect_internal_func = (flash_connect_internal_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); - flash_exit_xip_fn flash_exit_xip_func = (flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); - flash_flush_cache_fn flash_flush_cache_func = (flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); - flash_init_boot2_copyout(); - xip_cache_clean_all(); - - flash_rp2350_qmi_save_state_t qmi_save; - flash_rp2350_save_qmi_cs1(&qmi_save); - - __compiler_memory_barrier(); - flash_connect_internal_func(); - flash_exit_xip_func(); - - flash_cs_force(0); - size_t tx_remaining = count; - size_t rx_remaining = count; - - // QMI version -- no need to bound FIFO contents as QMI stalls on full DIRECT_RX. - hw_set_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS); - while (tx_remaining || rx_remaining) { - uint32_t flags = qmi_hw->direct_csr; - bool can_put = !(flags & QMI_DIRECT_CSR_TXFULL_BITS); - bool can_get = !(flags & QMI_DIRECT_CSR_RXEMPTY_BITS); - if (can_put && tx_remaining) { - qmi_hw->direct_tx = *txbuf++; - --tx_remaining; - } - if (can_get && rx_remaining) { - *rxbuf++ = (uint8_t)qmi_hw->direct_rx; - --rx_remaining; - } - } - hw_clear_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS); - - flash_cs_force(1); - - flash_flush_cache_func(); - flash_enable_xip_via_boot2(); - flash_rp2350_restore_qmi_cs1(&qmi_save); -} - -*/ -import "C" - -func enterBootloader() { - C.reset_usb_boot(0, 0) -} - -func doFlashCommand(tx []byte, rx []byte) error { - if len(tx) != len(rx) { - return errFlashInvalidWriteLength - } - - C.flash_do_cmd( - (*C.uint8_t)(unsafe.Pointer(&tx[0])), - (*C.uint8_t)(unsafe.Pointer(&rx[0])), - C.ulong(len(tx))) - - return nil -} - -// Flash related code -const memoryStart = C.XIP_BASE // memory start for purpose of erase - -func (f flashBlockDevice) writeAt(p []byte, off int64) (n int, err error) { - if writeAddress(off)+uintptr(C.XIP_BASE) > FlashDataEnd() { - return 0, errFlashCannotWritePastEOF - } - - state := interrupt.Disable() - defer interrupt.Restore(state) - - // rp2350 writes to offset, not actual address - // e.g. real address 0x10003000 is written to at - // 0x00003000 - address := writeAddress(off) - padded := flashPad(p, int(f.WriteBlockSize())) - - C.flash_range_write(C.uint32_t(address), - (*C.uint8_t)(unsafe.Pointer(&padded[0])), - C.ulong(len(padded))) - - return len(padded), nil -} - -func (f flashBlockDevice) eraseBlocks(start, length int64) error { - address := writeAddress(start * f.EraseBlockSize()) - if address+uintptr(C.XIP_BASE) > FlashDataEnd() { - return errFlashCannotErasePastEOF - } - - state := interrupt.Disable() - defer interrupt.Restore(state) - - C.flash_erase_blocks(C.uint32_t(address), C.ulong(length*f.EraseBlockSize())) - - return nil -} diff --git a/emb/machine/machine_rp2350_usb.go b/emb/machine/machine_rp2350_usb.go deleted file mode 100644 index ca09262..0000000 --- a/emb/machine/machine_rp2350_usb.go +++ /dev/null @@ -1,151 +0,0 @@ -//go:build rp2350 - -package machine - -import ( - "device/rp" - "machine/usb" - "runtime/interrupt" -) - -// Configure the USB peripheral. The config is here for compatibility with the UART interface. -func (dev *USBDevice) Configure(config UARTConfig) { - // Reset usb controller - resetBlock(rp.RESETS_RESET_USBCTRL) - unresetBlockWait(rp.RESETS_RESET_USBCTRL) - - // Clear any previous state in dpram just in case - _usbDPSRAM.clear() - - // Enable USB interrupt at processor - rp.USB.INTE.Set(0) - intr := interrupt.New(rp.IRQ_USBCTRL_IRQ, handleUSBIRQ) - intr.SetPriority(0x00) - intr.Enable() - irqSet(rp.IRQ_USBCTRL_IRQ, true) - - // Mux the controller to the onboard usb phy - rp.USB.USB_MUXING.Set(rp.USB_USB_MUXING_TO_PHY | rp.USB_USB_MUXING_SOFTCON) - - // Force VBUS detect so the device thinks it is plugged into a host - rp.USB.USB_PWR.Set(rp.USB_USB_PWR_VBUS_DETECT | rp.USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN) - - // Enable the USB controller in device mode. - rp.USB.MAIN_CTRL.Set(rp.USB_MAIN_CTRL_CONTROLLER_EN) - - // Enable an interrupt per EP0 transaction - rp.USB.SIE_CTRL.Set(rp.USB_SIE_CTRL_EP0_INT_1BUF) - - // Enable interrupts for when a buffer is done, when the bus is reset, - // and when a setup packet is received - rp.USB.INTE.Set(rp.USB_INTE_BUFF_STATUS | - rp.USB_INTE_BUS_RESET | - rp.USB_INTE_SETUP_REQ) - - // Present full speed device by enabling pull up on DP - rp.USB.SIE_CTRL.SetBits(rp.USB_SIE_CTRL_PULLUP_EN) - - // 12.7.2 Disable phy isolation - rp.USB.SetMAIN_CTRL_PHY_ISO(0x0) -} - -func handleUSBIRQ(intr interrupt.Interrupt) { - status := rp.USB.INTS.Get() - - // Setup packet received - if (status & rp.USB_INTS_SETUP_REQ) > 0 { - rp.USB.SIE_STATUS.Set(rp.USB_SIE_STATUS_SETUP_REC) - setup := usb.NewSetup(_usbDPSRAM.setupBytes()) - - ok := false - if (setup.BmRequestType & usb.REQUEST_TYPE) == usb.REQUEST_STANDARD { - // Standard Requests - ok = handleStandardSetup(setup) - } else { - // Class Interface Requests - if setup.WIndex < uint16(len(usbSetupHandler)) && usbSetupHandler[setup.WIndex] != nil { - ok = usbSetupHandler[setup.WIndex](setup) - } - } - - if !ok { - // Stall endpoint? - USBDev.SetStallEPIn(0) - } - - } - - // Buffer status, one or more buffers have completed - if (status & rp.USB_INTS_BUFF_STATUS) > 0 { - if sendOnEP0DATADONE.offset > 0 { - ep := uint32(0) - data := sendOnEP0DATADONE.data - count := len(data) - sendOnEP0DATADONE.offset - if ep == 0 && count > usb.EndpointPacketSize { - count = usb.EndpointPacketSize - } - - sendViaEPIn(ep, data[sendOnEP0DATADONE.offset:], count) - sendOnEP0DATADONE.offset += count - if sendOnEP0DATADONE.offset == len(data) { - sendOnEP0DATADONE.offset = 0 - } - } - - s2 := rp.USB.BUFF_STATUS.Get() - - // OUT (PC -> rp2350) - for i := 0; i < 16; i++ { - if s2&(1<<(i*2+1)) > 0 { - buf := handleEndpointRx(uint32(i)) - if usbRxHandler[i] == nil || usbRxHandler[i](buf) { - AckUsbOutTransfer(uint32(i)) - } - } - } - - // IN (rp2350 -> PC) - for i := 0; i < 16; i++ { - if s2&(1<<(i*2)) > 0 { - if usbTxHandler[i] != nil { - usbTxHandler[i]() - } - } - } - - rp.USB.BUFF_STATUS.Set(s2) - } - - // Bus is reset - if (status & rp.USB_INTS_BUS_RESET) > 0 { - rp.USB.SIE_STATUS.Set(rp.USB_SIE_STATUS_BUS_RESET) - //fixRP2040UsbDeviceEnumeration() - - rp.USB.ADDR_ENDP.Set(0) - initEndpoint(0, usb.ENDPOINT_TYPE_CONTROL) - } -} - -func handleUSBSetAddress(setup usb.Setup) bool { - // Using 570μs timeout which is exactly the same as SAMD21. - const ackTimeout = 570 - - rp.USB.SIE_STATUS.Set(rp.USB_SIE_STATUS_ACK_REC) - sendUSBPacket(0, []byte{}, 0) - - // Wait for transfer to complete with a timeout. - t := timer.timeElapsed() - for (rp.USB.SIE_STATUS.Get() & rp.USB_SIE_STATUS_ACK_REC) == 0 { - if dt := timer.timeElapsed() - t; dt >= ackTimeout { - return false - } - } - - // Set the device address to that requested by host. - rp.USB.ADDR_ENDP.Set(uint32(setup.WValueL) & rp.USB_ADDR_ENDP_ADDRESS_Msk) - return true -} - -func armEPZeroStall() { - rp.USB.EP_STALL_ARM.Set(rp.USB_EP_STALL_ARM_EP0_IN) -} diff --git a/emb/machine/machine_rp2_2040.go b/emb/machine/machine_rp2_2040.go deleted file mode 100644 index 9cdb3a0..0000000 --- a/emb/machine/machine_rp2_2040.go +++ /dev/null @@ -1,223 +0,0 @@ -//go:build rp2040 - -package machine - -import ( - "device/rp" - "runtime/volatile" - "unsafe" -) - -const ( - cpuFreq = 200 * MHz - _NUMBANK0_GPIOS = 30 - _NUMBANK0_IRQS = 4 - _NUMIRQ = 32 - rp2350ExtraReg = 0 - RESETS_RESET_Msk = 0x01ffffff - initUnreset = rp.RESETS_RESET_ADC | - rp.RESETS_RESET_RTC | - rp.RESETS_RESET_SPI0 | - rp.RESETS_RESET_SPI1 | - rp.RESETS_RESET_UART0 | - rp.RESETS_RESET_UART1 | - rp.RESETS_RESET_USBCTRL - initDontReset = rp.RESETS_RESET_IO_QSPI | - rp.RESETS_RESET_PADS_QSPI | - rp.RESETS_RESET_PLL_USB | - rp.RESETS_RESET_USBCTRL | - rp.RESETS_RESET_SYSCFG | - rp.RESETS_RESET_PLL_SYS - padEnableMask = rp.PADS_BANK0_GPIO0_IE_Msk | - rp.PADS_BANK0_GPIO0_OD_Msk -) - -const ( - PinOutput PinMode = iota - PinInput - PinInputPulldown - PinInputPullup - PinAnalog - PinUART - PinPWM - PinI2C - PinSPI - PinPIO0 - PinPIO1 -) - -// Analog pins on RP2040. -const ( - ADC0 Pin = GPIO26 - ADC1 Pin = GPIO27 - ADC2 Pin = GPIO28 - ADC3 Pin = GPIO29 - - thermADC = 30 -) - -const ( - clkGPOUT0 clockIndex = iota // GPIO Muxing 0 - clkGPOUT1 // GPIO Muxing 1 - clkGPOUT2 // GPIO Muxing 2 - clkGPOUT3 // GPIO Muxing 3 - clkRef // Watchdog and timers reference clock - clkSys // Processors, bus fabric, memory, memory mapped registers - clkPeri // Peripheral clock for UART and SPI - clkUSB // USB clock - clkADC // ADC clock - clkRTC // Real time clock - numClocks -) - -func calcClockDiv(srcFreq, freq uint32) uint32 { - // Div register is 24.8 int.frac divider so multiply by 2^8 (left shift by 8) - return uint32((uint64(srcFreq) << 8) / uint64(freq)) -} - -type clocksType struct { - clk [numClocks]clockType - resus struct { - ctrl volatile.Register32 - status volatile.Register32 - } - fc0 fc - wakeEN0 volatile.Register32 - wakeEN1 volatile.Register32 - sleepEN0 volatile.Register32 - sleepEN1 volatile.Register32 - enabled0 volatile.Register32 - enabled1 volatile.Register32 - intR volatile.Register32 - intE volatile.Register32 - intF volatile.Register32 - intS volatile.Register32 -} - -// GPIO function selectors -const ( - fnJTAG pinFunc = 0 - fnSPI pinFunc = 1 // Connect one of the internal PL022 SPI peripherals to GPIO - fnUART pinFunc = 2 - fnI2C pinFunc = 3 - // Connect a PWM slice to GPIO. There are eight PWM slices, - // each with two outputchannels (A/B). The B pin can also be used as an input, - // for frequency and duty cyclemeasurement - fnPWM pinFunc = 4 - // Software control of GPIO, from the single-cycle IO (SIO) block. - // The SIO function (F5)must be selected for the processors to drive a GPIO, - // but the input is always connected,so software can check the state of GPIOs at any time. - fnSIO pinFunc = 5 - // Connect one of the programmable IO blocks (PIO) to GPIO. PIO can implement a widevariety of interfaces, - // and has its own internal pin mapping hardware, allowing flexibleplacement of digital interfaces on bank 0 GPIOs. - // The PIO function (F6, F7) must beselected for PIO to drive a GPIO, but the input is always connected, - // so the PIOs canalways see the state of all pins. - fnPIO0, fnPIO1 pinFunc = 6, 7 - // General purpose clock inputs/outputs. Can be routed to a number of internal clock domains onRP2040, - // e.g. Input: to provide a 1 Hz clock for the RTC, or can be connected to an internalfrequency counter. - // e.g. Output: optional integer divide - fnGPCK pinFunc = 8 - // USB power control signals to/from the internal USB controller - fnUSB pinFunc = 9 - fnNULL pinFunc = 0x1f - - fnXIP pinFunc = 0 -) - -// Configure configures the gpio pin as per mode. -func (p Pin) Configure(config PinConfig) { - if p == NoPin { - return - } - p.init() - mask := uint32(1) << p - switch config.Mode { - case PinOutput: - p.setFunc(fnSIO) - rp.SIO.GPIO_OE_SET.Set(mask) - case PinInput: - p.setFunc(fnSIO) - p.pulloff() - case PinInputPulldown: - p.setFunc(fnSIO) - p.pulldown() - case PinInputPullup: - p.setFunc(fnSIO) - p.pullup() - case PinAnalog: - p.setFunc(fnNULL) - p.pulloff() - case PinUART: - p.setFunc(fnUART) - case PinPWM: - p.setFunc(fnPWM) - case PinI2C: - // IO config according to 4.3.1.3 of rp2040 datasheet. - p.setFunc(fnI2C) - p.pullup() - p.setSchmitt(true) - p.setSlew(false) - case PinSPI: - p.setFunc(fnSPI) - case PinPIO0: - p.setFunc(fnPIO0) - case PinPIO1: - p.setFunc(fnPIO1) - } -} - -var ( - timer = (*timerType)(unsafe.Pointer(rp.TIMER)) -) - -// Enable or disable a specific interrupt on the executing core. -// num is the interrupt number which must be in [0,31]. -func irqSet(num uint32, enabled bool) { - if num >= _NUMIRQ { - return - } - irqSetMask(1<= 32 { - mask := uint32(1) << (p % 32) - rp.SIO.GPIO_HI_OE_SET.Set(mask) - } else { - mask := uint32(1) << p - rp.SIO.GPIO_OE_SET.Set(mask) - } - case PinInput: - p.setFunc(fnSIO) - p.pulloff() - case PinInputPulldown: - p.setFunc(fnSIO) - p.pulldown() - case PinInputPullup: - p.setFunc(fnSIO) - p.pullup() - case PinAnalog: - p.setFunc(fnNULL) - p.pulloff() - case PinUART: - p.setFunc(fnUART) - case PinPWM: - p.setFunc(fnPWM) - case PinI2C: - // IO config according to 4.3.1.3 of rp2040 datasheet. - p.setFunc(fnI2C) - p.pullup() - p.setSchmitt(true) - p.setSlew(false) - case PinSPI: - p.setFunc(fnSPI) - case PinPIO0: - p.setFunc(fnPIO0) - case PinPIO1: - p.setFunc(fnPIO1) - case PinPIO2: - p.setFunc(fnPIO2) - } -} - -var ( - timer = (*timerType)(unsafe.Pointer(rp.TIMER0)) -) - -// Enable or disable a specific interrupt on the executing core. -// num is the interrupt number which must be in [0,_NUMIRQ). -func irqSet(num uint32, enabled bool) { - if num >= _NUMIRQ { - return - } - - register_index := num / 32 - var mask uint32 = 1 << (num % 32) - - if enabled { - // Clear pending before enable - //(if IRQ is actually asserted, it will immediately re-pend) - if register_index == 0 { - rp.PPB.NVIC_ICPR0.Set(mask) - rp.PPB.NVIC_ISER0.Set(mask) - } else { - rp.PPB.NVIC_ICPR1.Set(mask) - rp.PPB.NVIC_ISER1.Set(mask) - } - } else { - if register_index == 0 { - rp.PPB.NVIC_ICER0.Set(mask) - } else { - rp.PPB.NVIC_ICER1.Set(mask) - } - } -} - -func (clks *clocksType) initRTC() {} // No RTC on RP2350. - -func (clks *clocksType) initTicks() { - rp.TICKS.SetTIMER0_CTRL_ENABLE(0) - rp.TICKS.SetTIMER0_CYCLES(12) - rp.TICKS.SetTIMER0_CTRL_ENABLE(1) -} - -// startTick starts the watchdog tick. -// On RP2040, the watchdog contained a tick generator used to generate a 1μs tick for the watchdog. This was also -// distributed to the system timer. On RP2350, the watchdog instead takes a tick input from the system-level ticks block. See Section 8.5. -func (wd *watchdogImpl) startTick(cycles uint32) { - rp.TICKS.WATCHDOG_CTRL.SetBits(1) -} - -func adjustCoreVoltage() bool { - return false -} diff --git a/emb/machine/machine_rp2_2350a.go b/emb/machine/machine_rp2_2350a.go deleted file mode 100644 index 09ec8a1..0000000 --- a/emb/machine/machine_rp2_2350a.go +++ /dev/null @@ -1,14 +0,0 @@ -//go:build rp2350 && !rp2350b - -package machine - -// Analog pins on RP2350a. -const ( - ADC0 Pin = GPIO26 - ADC1 Pin = GPIO27 - ADC2 Pin = GPIO28 - ADC3 Pin = GPIO29 - - // fifth ADC channel. - thermADC = 30 -) diff --git a/emb/machine/machine_rp2_2350b.go b/emb/machine/machine_rp2_2350b.go deleted file mode 100644 index bd5ceeb..0000000 --- a/emb/machine/machine_rp2_2350b.go +++ /dev/null @@ -1,48 +0,0 @@ -//go:build rp2350b - -package machine - -// RP2350B has additional pins. - -const ( - GPIO30 Pin = 30 // peripherals: PWM7 channel A - GPIO31 Pin = 31 // peripherals: PWM7 channel B - GPIO32 Pin = 32 // peripherals: PWM8 channel A - GPIO33 Pin = 33 // peripherals: PWM8 channel B - GPIO34 Pin = 34 // peripherals: PWM9 channel A - GPIO35 Pin = 35 // peripherals: PWM9 channel B - GPIO36 Pin = 36 // peripherals: PWM10 channel A - GPIO37 Pin = 37 // peripherals: PWM10 channel B - GPIO38 Pin = 38 // peripherals: PWM11 channel A - GPIO39 Pin = 39 // peripherals: PWM11 channel B - GPIO40 Pin = 40 // peripherals: PWM8 channel A - GPIO41 Pin = 41 // peripherals: PWM8 channel B - GPIO42 Pin = 42 // peripherals: PWM9 channel A - GPIO43 Pin = 43 // peripherals: PWM9 channel B - GPIO44 Pin = 44 // peripherals: PWM10 channel A - GPIO45 Pin = 45 // peripherals: PWM10 channel B - GPIO46 Pin = 46 // peripherals: PWM11 channel A - GPIO47 Pin = 47 // peripherals: PWM11 channel B -) - -// Analog pins on 2350b. -const ( - ADC0 Pin = GPIO40 - ADC1 Pin = GPIO41 - ADC2 Pin = GPIO42 - ADC3 Pin = GPIO43 - ADC4 Pin = GPIO44 - ADC5 Pin = GPIO45 - ADC6 Pin = GPIO46 - ADC7 Pin = GPIO47 - // Ninth ADC channel. - thermADC = 48 -) - -// Additional PWMs on the RP2350B. -var ( - PWM8 = getPWMGroup(8) - PWM9 = getPWMGroup(9) - PWM10 = getPWMGroup(10) - PWM11 = getPWMGroup(11) -) diff --git a/emb/machine/machine_rp2_adc.go b/emb/machine/machine_rp2_adc.go deleted file mode 100644 index fc9a826..0000000 --- a/emb/machine/machine_rp2_adc.go +++ /dev/null @@ -1,114 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "errors" - "sync" -) - -// ADCChannel is the ADC peripheral mux channel. 0-4. -type ADCChannel uint8 - -// Used to serialise ADC sampling -var adcLock sync.Mutex - -// ADC peripheral reference voltage (mV) -var adcAref uint32 - -// InitADC resets the ADC peripheral. -func InitADC() { - rp.RESETS.RESET.SetBits(rp.RESETS_RESET_ADC) - rp.RESETS.RESET.ClearBits(rp.RESETS_RESET_ADC) - for !rp.RESETS.RESET_DONE.HasBits(rp.RESETS_RESET_ADC) { - } - // enable ADC - rp.ADC.CS.Set(rp.ADC_CS_EN) - adcAref = 3300 - waitForReady() -} - -// Configure sets the ADC pin to analog input mode. -func (a ADC) Configure(config ADCConfig) error { - c, err := a.GetADCChannel() - if err != nil { - return err - } - return c.Configure(config) -} - -// Get returns a one-shot ADC sample reading. -func (a ADC) Get() uint16 { - if c, err := a.GetADCChannel(); err == nil { - return c.getOnce() - } - // Not an ADC pin! - return 0 -} - -// GetADCChannel returns the channel associated with the ADC pin. -func (a ADC) GetADCChannel() (c ADCChannel, err error) { - if a.Pin < ADC0 { - return 0, errors.New("no ADC channel for pin value") - } - return ADCChannel(a.Pin - ADC0), nil -} - -// Configure sets the channel's associated pin to analog input mode. -// The powered on temperature sensor increases ADC_AVDD current by approximately 40 μA. -func (c ADCChannel) Configure(config ADCConfig) error { - if config.Reference != 0 { - adcAref = config.Reference - } - p, err := c.Pin() - if err != nil { - return err - } - p.Configure(PinConfig{Mode: PinAnalog}) - return nil -} - -// getOnce returns a one-shot ADC sample reading from an ADC channel. -func (c ADCChannel) getOnce() uint16 { - // Make it safe to sample multiple ADC channels in separate go routines. - adcLock.Lock() - rp.ADC.CS.ReplaceBits(uint32(c), 0b111, rp.ADC_CS_AINSEL_Pos) - rp.ADC.CS.SetBits(rp.ADC_CS_START_ONCE) - - waitForReady() - adcLock.Unlock() - - // rp2040 is a 12-bit ADC, scale raw reading to 16-bits. - return uint16(rp.ADC.RESULT.Get()) << 4 -} - -// getVoltage does a one-shot sample and returns a millivolts reading. -// Integer portion is stored in the high 16 bits and fractional in the low 16 bits. -func (c ADCChannel) getVoltage() uint32 { - return (adcAref << 16) / (1 << 12) * uint32(c.getOnce()>>4) -} - -// ReadTemperature does a one-shot sample of the internal temperature sensor and returns a milli-celsius reading. -func ReadTemperature() (millicelsius int32) { - if rp.ADC.CS.Get()&rp.ADC_CS_EN == 0 { - InitADC() - } - thermChan, _ := ADC{Pin: thermADC}.GetADCChannel() - // Enable temperature sensor bias source - rp.ADC.CS.SetBits(rp.ADC_CS_TS_EN) - - // T = 27 - (ADC_voltage - 0.706)/0.001721 - return (27000<<16 - (int32(thermChan.getVoltage())-706<<16)*581) >> 16 -} - -// waitForReady spins waiting for the ADC peripheral to become ready. -func waitForReady() { - for !rp.ADC.CS.HasBits(rp.ADC_CS_READY) { - } -} - -// The Pin method returns the GPIO Pin associated with the ADC mux channel, if it has one. -func (c ADCChannel) Pin() (p Pin, err error) { - return Pin(c) + ADC0, nil -} diff --git a/emb/machine/machine_rp2_clocks.go b/emb/machine/machine_rp2_clocks.go deleted file mode 100644 index dafebbe..0000000 --- a/emb/machine/machine_rp2_clocks.go +++ /dev/null @@ -1,236 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/arm" - "device/rp" - "runtime/volatile" - "unsafe" -) - -func CPUFrequency() uint32 { - return cpuFreq -} - -// clockIndex identifies a hardware clock -type clockIndex uint8 - -type clockType struct { - ctrl volatile.Register32 - div volatile.Register32 - selected volatile.Register32 -} - -type fc struct { - refKHz volatile.Register32 - minKHz volatile.Register32 - maxKHz volatile.Register32 - delay volatile.Register32 - interval volatile.Register32 - src volatile.Register32 - status volatile.Register32 - result volatile.Register32 -} - -var clocks = (*clocksType)(unsafe.Pointer(rp.CLOCKS)) - -var configuredFreq [numClocks]uint32 - -type clock struct { - *clockType - cix clockIndex -} - -// The delay in seconds for core voltage adjustments to -// settle. Taken from the Pico SDK. -const _VREG_VOLTAGE_AUTO_ADJUST_DELAY = 1 / 1e3 - -// clock returns the clock identified by cix. -func (clks *clocksType) clock(cix clockIndex) clock { - return clock{ - &clks.clk[cix], - cix, - } -} - -// hasGlitchlessMux returns true if clock contains a glitchless multiplexer. -// -// Clock muxing consists of two components: -// -// A glitchless mux, which can be switched freely, but whose inputs must be -// free-running. -// -// An auxiliary (glitchy) mux, whose output glitches when switched, but has -// no constraints on its inputs. -// -// Not all clocks have both types of mux. -func (clk *clock) hasGlitchlessMux() bool { - return clk.cix == clkSys || clk.cix == clkRef -} - -// configure configures the clock by selecting the main clock source src -// and the auxiliary clock source auxsrc -// and finally setting the clock frequency to freq -// given the input clock source frequency srcFreq. -func (clk *clock) configure(src, auxsrc, srcFreq, freq uint32) { - if freq > srcFreq { - panic("clock frequency cannot be greater than source frequency") - } - - div := calcClockDiv(srcFreq, freq) - - // If increasing divisor, set divisor before source. Otherwise set source - // before divisor. This avoids a momentary overspeed when e.g. switching - // to a faster source and increasing divisor to compensate. - if div > clk.div.Get() { - clk.div.Set(div) - } - - // If switching a glitchless slice (ref or sys) to an aux source, switch - // away from aux *first* to avoid passing glitches when changing aux mux. - // Assume (!!!) glitchless source 0 is no faster than the aux source. - if clk.hasGlitchlessMux() && src == rp.CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX { - clk.ctrl.ClearBits(rp.CLOCKS_CLK_REF_CTRL_SRC_Msk) - for !clk.selected.HasBits(1) { - } - } else - // If no glitchless mux, cleanly stop the clock to avoid glitches - // propagating when changing aux mux. Note it would be a really bad idea - // to do this on one of the glitchless clocks (clkSys, clkRef). - { - // Disable clock. On clkRef and ClkSys this does nothing, - // all other clocks have the ENABLE bit in the same position. - clk.ctrl.ClearBits(rp.CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Msk) - if configuredFreq[clk.cix] > 0 { - // Delay for 3 cycles of the target clock, for ENABLE propagation. - // Note XOSC_COUNT is not helpful here because XOSC is not - // necessarily running, nor is timer... so, 3 cycles per loop: - delayCyc := configuredFreq[clkSys]/configuredFreq[clk.cix] + 1 - for delayCyc != 0 { - // This could be done more efficiently but TinyGo inline - // assembly is not yet capable enough to express that. In the - // meantime, this forces at least 3 cycles per loop. - delayCyc-- - arm.Asm("nop\nnop\nnop") - } - } - } - - // Set aux mux first, and then glitchless mux if this clock has one. - clk.ctrl.ReplaceBits(auxsrc< FlashDataEnd() { - return 0, errFlashCannotReadPastEOF - } - - data := unsafe.Slice((*byte)(unsafe.Pointer(readAddress(off))), len(p)) - copy(p, data) - - return len(p), nil -} - -// WriteAt writes the given number of bytes to the block device. -// Only word (32 bits) length data can be programmed. -// If the length of p is not long enough it will be padded with 0xFF bytes. -// This method assumes that the destination is already erased. -func (f flashBlockDevice) WriteAt(p []byte, off int64) (n int, err error) { - return f.writeAt(p, off) -} - -// Size returns the number of bytes in this block device. -func (f flashBlockDevice) Size() int64 { - return int64(FlashDataEnd() - FlashDataStart()) -} - -const writeBlockSize = 1 << 8 - -// WriteBlockSize returns the block size in which data can be written to -// memory. It can be used by a client to optimize writes, non-aligned writes -// should always work correctly. -func (f flashBlockDevice) WriteBlockSize() int64 { - return writeBlockSize -} - -const eraseBlockSizeValue = 1 << 12 - -func eraseBlockSize() int64 { - return eraseBlockSizeValue -} - -// EraseBlockSize returns the smallest erasable area on this particular chip -// in bytes. This is used for the block size in EraseBlocks. -func (f flashBlockDevice) EraseBlockSize() int64 { - return eraseBlockSize() -} - -// EraseBlocks erases the given number of blocks. An implementation may -// transparently coalesce ranges of blocks into larger bundles if the chip -// supports this. The start and len parameters are in block numbers, use -// EraseBlockSize to map addresses to blocks. -func (f flashBlockDevice) EraseBlocks(start, length int64) error { - return f.eraseBlocks(start, length) -} - -// return the correct address to be used for write -func writeAddress(off int64) uintptr { - return readAddress(off) - uintptr(memoryStart) -} - -// return the correct address to be used for reads -func readAddress(off int64) uintptr { - return FlashDataStart() + uintptr(off) -} diff --git a/emb/machine/machine_rp2_gpio.go b/emb/machine/machine_rp2_gpio.go deleted file mode 100644 index 25d7626..0000000 --- a/emb/machine/machine_rp2_gpio.go +++ /dev/null @@ -1,282 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -type ioType struct { - status volatile.Register32 - ctrl volatile.Register32 -} - -type irqCtrl struct { - intE [_NUMBANK0_IRQS]volatile.Register32 - intF [_NUMBANK0_IRQS]volatile.Register32 - intS [_NUMBANK0_IRQS]volatile.Register32 -} - -type irqSummary struct { - proc [2]struct { - secure [2]volatile.Register32 - nonsecure [2]volatile.Register32 - } - comaWake struct { - secure [2]volatile.Register32 - nonsecure [2]volatile.Register32 - } -} - -type ioBank0Type struct { - io [_NUMBANK0_GPIOS]ioType - _ [rp2350ExtraReg][128]byte - irqsum [rp2350ExtraReg]irqSummary - intR [_NUMBANK0_IRQS]volatile.Register32 - proc0IRQctrl irqCtrl - proc1IRQctrl irqCtrl - dormantWakeIRQctrl irqCtrl -} - -var ioBank0 = (*ioBank0Type)(unsafe.Pointer(rp.IO_BANK0)) - -type padsBank0Type struct { - voltageSelect volatile.Register32 - io [_NUMBANK0_GPIOS]volatile.Register32 -} - -var padsBank0 = (*padsBank0Type)(unsafe.Pointer(rp.PADS_BANK0)) - -// pinFunc represents a GPIO function. -// -// Each GPIO can have one function selected at a time. -// Likewise, each peripheral input (e.g. UART0 RX) should only be selected -// on one GPIO at a time. If the same peripheral input is connected to multiple GPIOs, -// the peripheral sees the logical OR of these GPIO inputs. -type pinFunc uint8 - -func (p Pin) PortMaskSet() (*uint32, uint32) { - return (*uint32)(unsafe.Pointer(&rp.SIO.GPIO_OUT_SET)), 1 << p -} - -// set drives the pin high -func (p Pin) set() { - if is48Pin && p >= 32 { - mask := uint32(1) << (p % 32) - rp.SIO.GPIO_HI_OUT_SET.Set(mask) - } else { - mask := uint32(1) << p - rp.SIO.GPIO_OUT_SET.Set(mask) - } -} - -func (p Pin) PortMaskClear() (*uint32, uint32) { - return (*uint32)(unsafe.Pointer(&rp.SIO.GPIO_OUT_CLR)), 1 << p -} - -// clr drives the pin low -func (p Pin) clr() { - if is48Pin && p >= 32 { - mask := uint32(1) << (p % 32) - rp.SIO.GPIO_HI_OUT_CLR.Set(mask) - } else { - mask := uint32(1) << p - rp.SIO.GPIO_OUT_CLR.Set(mask) - } -} - -// xor toggles the pin -func (p Pin) xor() { - if is48Pin && p >= 32 { - mask := uint32(1) << (p % 32) - rp.SIO.GPIO_HI_OUT_XOR.Set(mask) - } else { - mask := uint32(1) << p - rp.SIO.GPIO_OUT_XOR.Set(mask) - } -} - -// get returns the pin value -func (p Pin) get() bool { - if is48Pin && p >= 32 { - return rp.SIO.GPIO_HI_IN.HasBits(1 << (p % 32)) - } - return rp.SIO.GPIO_IN.HasBits(1 << p) -} - -func (p Pin) ioCtrl() *volatile.Register32 { - return &ioBank0.io[p].ctrl -} - -func (p Pin) padCtrl() *volatile.Register32 { - return &padsBank0.io[p] -} - -func (p Pin) pullup() { - p.padCtrl().SetBits(rp.PADS_BANK0_GPIO0_PUE) - p.padCtrl().ClearBits(rp.PADS_BANK0_GPIO0_PDE) -} - -func (p Pin) pulldown() { - p.padCtrl().SetBits(rp.PADS_BANK0_GPIO0_PDE) - p.padCtrl().ClearBits(rp.PADS_BANK0_GPIO0_PUE) -} - -func (p Pin) pulloff() { - p.padCtrl().ClearBits(rp.PADS_BANK0_GPIO0_PDE) - p.padCtrl().ClearBits(rp.PADS_BANK0_GPIO0_PUE) -} - -// setSlew sets pad slew rate control. -// true sets to fast. false sets to slow. -func (p Pin) setSlew(sr bool) { - p.padCtrl().ReplaceBits(boolToBit(sr)<= 32 { - mask := uint32(1) << (p % 32) - rp.SIO.GPIO_HI_OE_CLR.Set(mask) - } else { - mask := uint32(1) << p - rp.SIO.GPIO_OE_CLR.Set(mask) - } - p.clr() -} - -// Set drives the pin high if value is true else drives it low. -func (p Pin) Set(value bool) { - if p == NoPin { - return - } - if value { - p.set() - } else { - p.clr() - } -} - -// Get reads the pin value. -func (p Pin) Get() bool { - return p.get() -} - -// PinChange represents one or more trigger events that can happen on a given GPIO pin -// on the RP2040. ORed PinChanges are valid input to most IRQ functions. -type PinChange uint8 - -// Pin change interrupt constants for SetInterrupt. -const ( - // Edge falling - PinFalling PinChange = 4 << iota - // Edge rising - PinRising - - PinToggle = PinFalling | PinRising -) - -// Callbacks to be called for pins configured with SetInterrupt. -var ( - pinCallbacks [2][_NUMBANK0_GPIOS]func(Pin) - setInt [2][_NUMBANK0_GPIOS]bool -) - -// SetInterrupt sets an interrupt to be executed when a particular pin changes -// state. The pin should already be configured as an input, including a pull up -// or down if no external pull is provided. -// -// This call will replace a previously set callback on this pin. You can pass a -// nil func to unset the pin change interrupt. If you do so, the change -// parameter is ignored and can be set to any value (such as 0). -func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error { - if p == NoPin { - return nil - } - if p > 31 || p < 0 { - return ErrInvalidInputPin - } - core := CurrentCore() - if callback == nil { - // disable current interrupt - p.setInterrupt(change, false) - pinCallbacks[core][p] = nil - return nil - } - - if pinCallbacks[core][p] != nil { - // Callback already configured. Should disable callback by passing a nil callback first. - return ErrNoPinChangeChannel - } - p.setInterrupt(change, true) - pinCallbacks[core][p] = callback - - if setInt[core][p] { - // interrupt has already been set. Exit. - return nil - } - interrupt.New(rp.IRQ_IO_IRQ_BANK0, gpioHandleInterrupt).Enable() - irqSet(rp.IRQ_IO_IRQ_BANK0, true) - return nil -} - -// gpioHandleInterrupt finds the corresponding pin for the interrupt. -// C SDK equivalent of gpio_irq_handler -func gpioHandleInterrupt(intr interrupt.Interrupt) { - - core := CurrentCore() - var gpio Pin - for gpio = 0; gpio < _NUMBANK0_GPIOS; gpio++ { - var base *irqCtrl - switch core { - case 0: - base = &ioBank0.proc0IRQctrl - case 1: - base = &ioBank0.proc1IRQctrl - } - - statreg := base.intS[gpio>>3].Get() - change := getIntChange(gpio, statreg) - if change != 0 { - gpio.acknowledgeInterrupt(change) - callback := pinCallbacks[core][gpio] - if callback != nil { - callback(gpio) - } - } - } -} - -// events returns the bit representation of the pin change for the rp2040. -func (change PinChange) events() uint32 { - return uint32(change) -} - -// intBit is the bit storage form of a PinChange for a given Pin -// in the IO_BANK0 interrupt registers (page 269 RP2040 Datasheet). -func (p Pin) ioIntBit(change PinChange) uint32 { - return change.events() << (4 * (p % 8)) -} - -// Acquire interrupt data from a INT status register. -func getIntChange(p Pin, status uint32) PinChange { - return PinChange(status>>(4*(p%8))) & 0xf -} diff --git a/emb/machine/machine_rp2_i2c.go b/emb/machine/machine_rp2_i2c.go deleted file mode 100644 index 54a5e53..0000000 --- a/emb/machine/machine_rp2_i2c.go +++ /dev/null @@ -1,639 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "errors" - "internal/itoa" -) - -// I2C on the RP2040/RP2350 -var ( - I2C0 = &_I2C0 - _I2C0 = I2C{ - Bus: rp.I2C0, - } - I2C1 = &_I2C1 - _I2C1 = I2C{ - Bus: rp.I2C1, - } -) - -// The I2C target implementation is based on the C implementation from -// here: https://github.com/vmilea/pico_i2c_slave - -// Features: Taken from datasheet. -// Default controller mode, with target mode available (not simultaneously). -// Default target address of RP2040: 0x055 -// Supports 10-bit addressing in controller mode -// 16-element transmit buffer -// 16-element receive buffer -// Can be driven from DMA -// Can generate interrupts -// Fast mode plus max transfer speed (1000kb/s) - -// GPIO config -// Each controller must connect its clock SCL and data SDA to one pair of GPIOs. -// The I2C standard requires that drivers drivea signal low, or when not driven the signal will be pulled high. -// This applies to SCL and SDA. The GPIO pads should be configured for: -// Pull-up enabled -// Slew rate limited -// Schmitt trigger enabled -// Note: There should also be external pull-ups on the board as the internal pad pull-ups may not be strong enough to pull upexternal circuits. - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 - // SDA/SCL Serial Data and clock pins. Refer to datasheet to see - // which pins match the desired bus. - SDA, SCL Pin - Mode I2CMode -} - -type I2C struct { - Bus *rp.I2C0_Type - mode I2CMode - txInProgress bool -} - -var ( - errInvalidI2CBaudrate = errors.New("i2c: invalid baudrate") - errInvalidTgtAddr = errors.New("i2c: invalid target address: not in 0..0x80 or is reserved") - errI2CGeneric = errors.New("i2c: generic error") - errI2CDisable = errors.New("i2c: peripheral timeout in disable") - errInvalidI2CSDA = errors.New("i2c: invalid SDA pin") - errInvalidI2CSCL = errors.New("i2c: invalid SCL pin") - errI2CAlreadyListening = errors.New("i2c: already listening") - errI2CWrongMode = errors.New("i2c: wrong mode") - errI2CUnderflow = errors.New("i2c: underflow") -) - -// Tx performs a write and then a read transfer placing the result in -// in r. -// -// Passing a nil value for w or r skips the transfer corresponding to write -// or read, respectively. -// -// i2c.Tx(addr, nil, r) -// -// Performs only a read transfer. -// -// i2c.Tx(addr, w, nil) -// -// Performs only a write transfer. -func (i2c *I2C) Tx(addr uint16, w, r []byte) error { - if i2c.mode != I2CModeController { - return errI2CWrongMode - } - return i2c.tx(uint8(addr), w, r) -} - -// Listen starts listening for I2C requests sent to specified address -// -// addr is the address to listen to -func (i2c *I2C) Listen(addr uint16) error { - if i2c.mode != I2CModeTarget { - return errI2CWrongMode - } - - return i2c.listen(uint8(addr)) -} - -// Configure initializes i2c peripheral and configures I2C config's pins passed. -// Here's a list of valid SDA and SCL GPIO pins on bus I2C0 of the rp2040: -// -// SDA: 0, 4, 8, 12, 16, 20 -// SCL: 1, 5, 9, 13, 17, 21 -// -// Same as above for I2C1 bus: -// -// SDA: 2, 6, 10, 14, 18, 26 -// SCL: 3, 7, 11, 15, 19, 27 -func (i2c *I2C) Configure(config I2CConfig) error { - const defaultBaud uint32 = 100_000 // 100kHz standard mode - if config.SCL == 0 && config.SDA == 0 { - // If config pins are zero valued or clock pin is invalid then we set default values. - switch i2c.Bus { - case rp.I2C0: - config.SCL = I2C0_SCL_PIN - config.SDA = I2C0_SDA_PIN - case rp.I2C1: - config.SCL = I2C1_SCL_PIN - config.SDA = I2C1_SDA_PIN - } - } - var okSCL, okSDA bool - switch i2c.Bus { - case rp.I2C0: - okSCL = (config.SCL+3)%4 == 0 - okSDA = (config.SDA+4)%4 == 0 - case rp.I2C1: - okSCL = (config.SCL+1)%4 == 0 - okSDA = (config.SDA+2)%4 == 0 - } - - switch { - case !okSCL: - return errInvalidI2CSCL - case !okSDA: - return errInvalidI2CSDA - } - - if config.Frequency == 0 { - config.Frequency = defaultBaud - } - config.SDA.Configure(PinConfig{PinI2C}) - config.SCL.Configure(PinConfig{PinI2C}) - return i2c.init(config) -} - -// SetBaudRate sets the I2C frequency. It has the side effect of also -// enabling the I2C hardware if disabled beforehand. -// -//go:inline -func (i2c *I2C) SetBaudRate(br uint32) error { - - if br == 0 { - return errInvalidI2CBaudrate - } - - // I2C is synchronous design that runs from clk_sys - freqin := CPUFrequency() - - // TODO there are some subtleties to I2C timing which we are completely ignoring here - period := (freqin + br/2) / br - lcnt := period * 3 / 5 // oof this one hurts - hcnt := period - lcnt - // Check for out-of-range divisors: - if hcnt > rp.I2C0_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_Msk || hcnt < 8 || lcnt > rp.I2C0_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Msk || lcnt < 8 { - return errInvalidI2CBaudrate - } - - // Per I2C-bus specification a device in standard or fast mode must - // internally provide a hold time of at least 300ns for the SDA signal to - // bridge the undefined region of the falling edge of SCL. A smaller hold - // time of 120ns is used for fast mode plus. - - // sda_tx_hold_count = freq_in [cycles/s] * 300ns * (1s / 1e9ns) - // Reduce 300/1e9 to 3/1e7 to avoid numbers that don't fit in uint. - // Add 1 to avoid division truncation. - sdaTxHoldCnt := ((freqin * 3) / 10000000) + 1 - if br >= 1_000_000 { - // sda_tx_hold_count = freq_in [cycles/s] * 120ns * (1s / 1e9ns) - // Reduce 120/1e9 to 3/25e6 to avoid numbers that don't fit in uint. - // Add 1 to avoid division truncation. - sdaTxHoldCnt = ((freqin * 3) / 25000000) + 1 - } - - if sdaTxHoldCnt > lcnt-2 { - return errInvalidI2CBaudrate - } - err := i2c.disable() - if err != nil { - return err - } - // Always use "fast" mode (<= 400 kHz, works fine for standard mode too) - - i2c.Bus.IC_CON.ReplaceBits(rp.I2C0_IC_CON_SPEED_FAST< deadline { - return errI2CDisable - } - } - return nil -} - -//go:inline -func (i2c *I2C) init(config I2CConfig) error { - i2c.reset() - if err := i2c.disable(); err != nil { - return err - } - - i2c.mode = config.Mode - - // Configure as fast-mode with RepStart support, 7-bit addresses - mode := uint32(rp.I2C0_IC_CON_SPEED_FAST<= 0x80 || isReservedI2CAddr(addr) { - return errInvalidTgtAddr - } - txlen := len(tx) - rxlen := len(rx) - // Quick return if possible. - if txlen == 0 && rxlen == 0 { - return nil - } - - err = i2c.disable() - if err != nil { - return err - } - i2c.Bus.IC_TAR.Set(uint32(addr)) - i2c.enable() - abort := false - var abortReason i2cAbortError - txStop := rxlen == 0 - for txCtr := 0; txCtr < txlen; txCtr++ { - if abort { - break - } - first := txCtr == 0 - last := txCtr == txlen-1 && rxlen == 0 - i2c.Bus.IC_DATA_CMD.Set( - (boolToBit(first) << rp.I2C0_IC_DATA_CMD_RESTART_Pos) | - (boolToBit(last && txStop) << rp.I2C0_IC_DATA_CMD_STOP_Pos) | - uint32(tx[txCtr])) - - // Wait until the transmission of the address/data from the internal - // shift register has completed. For this to function correctly, the - // TX_EMPTY_CTRL flag in IC_CON must be set. The TX_EMPTY_CTRL flag - // was set in i2c_init. - - // IC_RAW_INTR_STAT_TX_EMPTY: This bit is set to 1 when the transmit buffer is at or below - // the threshold value set in the IC_TX_TL register and the - // transmission of the address/data from the internal shift - // register for the most recently popped command is - // completed. It is automatically cleared by hardware when - // the buffer level goes above the threshold. When - // IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held - // in reset. There the TX FIFO looks like it has no data within - // it, so this bit is set to 1, provided there is activity in the - // controller or target state machines. When there is no longer - // any activity, then with ic_en=0, this bit is set to 0. - for !i2c.interrupted(rp.I2C0_IC_RAW_INTR_STAT_TX_EMPTY) { - if ticks() > deadline { - return errI2CWriteTimeout // If there was a timeout, don't attempt to do anything else. - } - - before := ticks() - gosched() - deadline += ticks() - before - } - - abortReason = i2c.getAbortReason() - if abortReason != 0 { - i2c.clearAbortReason() - abort = true - } - if abort || last { - // If the transaction was aborted or if it completed - // successfully wait until the STOP condition has occurred. - - // TODO Could there be an abort while waiting for the STOP - // condition here? If so, additional code would be needed here - // to take care of the abort. - for !i2c.interrupted(rp.I2C0_IC_RAW_INTR_STAT_STOP_DET) { - if ticks() > deadline { - if abort { - return abortReason - } - return errI2CWriteTimeout - } - - before := ticks() - gosched() - deadline += ticks() - before - } - i2c.Bus.IC_CLR_STOP_DET.Get() - } - } - - // Midway check for abort. Related issue https://github.com/tinygo-org/tinygo/issues/3671. - // The root cause for an abort after writing registers was "tx data no ack" (abort code=8). - // If the abort code was not registered then the whole peripheral would remain in disabled state forever. - abortReason = i2c.getAbortReason() - if abortReason != 0 { - i2c.clearAbortReason() - abort = true - } - - rxStart := txlen == 0 - if rxlen > 0 && !abort { - for rxCtr := 0; rxCtr < rxlen; rxCtr++ { - first := rxCtr == 0 - last := rxCtr == rxlen-1 - for i2c.writeAvailable() == 0 { - before := ticks() - gosched() - deadline += ticks() - before - } - i2c.Bus.IC_DATA_CMD.Set( - boolToBit(first && rxStart)< 1 for read - - for !abort && i2c.readAvailable() == 0 { - abortReason = i2c.getAbortReason() - if abortReason != 0 { - i2c.clearAbortReason() - abort = true - } - if ticks() > deadline { - return errI2CReadTimeout // If there was a timeout, don't attempt to do anything else. - } - - before := ticks() - gosched() - deadline += ticks() - before - } - if abort { - break - } - rx[rxCtr] = uint8(i2c.Bus.IC_DATA_CMD.Get()) - } - } - // From Pico SDK: A lot of things could have just happened due to the ingenious and - // creative design of I2C. Try to figure things out. - if abort { - switch { - case abortReason == 0 || abortReason&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK != 0: - // No reported errors - seems to happen if there is nothing connected to the bus. - // Address byte not acknowledged - err = errI2CGeneric - case abortReason&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK != 0: - // Address acknowledged, some data not acknowledged - fallthrough - default: - err = abortReason - } - } - return err -} - -// listen sets up for async handling of requests on the I2C bus. -func (i2c *I2C) listen(addr uint8) error { - if addr >= 0x80 || isReservedI2CAddr(addr) { - return errInvalidTgtAddr - } - - err := i2c.disable() - if err != nil { - return err - } - - i2c.Bus.IC_SAR.Set(uint32(addr)) - - i2c.enable() - - return nil -} - -func (i2c *I2C) WaitForEvent(buf []byte) (evt I2CTargetEvent, count int, err error) { - rxPtr := 0 - for { - stat := i2c.Bus.IC_RAW_INTR_STAT.Get() - - if stat&rp.I2C0_IC_INTR_MASK_M_RX_FULL != 0 { - b := uint8(i2c.Bus.IC_DATA_CMD.Get()) - if rxPtr < len(buf) { - buf[rxPtr] = b - rxPtr++ - } - } - - // Stop - if stat&rp.I2C0_IC_INTR_MASK_M_STOP_DET != 0 { - if rxPtr > 0 { - return I2CReceive, rxPtr, nil - } - - i2c.Bus.IC_CLR_STOP_DET.Get() // clear - return I2CFinish, 0, nil - } - - // Start or restart - ignore start, return on restart - if stat&rp.I2C0_IC_INTR_MASK_M_START_DET != 0 { - i2c.Bus.IC_CLR_START_DET.Get() // clear restart - - // Restart - if rxPtr > 0 { - return I2CReceive, rxPtr, nil - } - } - - // Read request - leave flag set until we start to reply. - if stat&rp.I2C0_IC_INTR_MASK_M_RD_REQ != 0 { - return I2CRequest, 0, nil - } - - gosched() - } -} - -func (i2c *I2C) Reply(buf []byte) error { - txPtr := 0 - - stat := i2c.Bus.IC_RAW_INTR_STAT.Get() - - if stat&rp.I2C0_IC_INTR_MASK_M_RD_REQ == 0 { - return errI2CWrongMode - } - i2c.Bus.IC_CLR_RD_REQ.Get() // clear restart - - // Clear any dangling TX abort - if stat&rp.I2C0_IC_INTR_MASK_M_TX_ABRT != 0 { - i2c.Bus.IC_CLR_TX_ABRT.Get() - } - - for txPtr < len(buf) { - if i2c.Bus.GetIC_RAW_INTR_STAT_TX_EMPTY() != 0 { - i2c.Bus.SetIC_DATA_CMD_DAT(uint32(buf[txPtr])) - txPtr++ - // The DW_apb_i2c flushes/resets/empties the - // TX_FIFO and RX_FIFO whenever there is a transmit abort - // caused by any of the events tracked by the - // IC_TX_ABRT_SOURCE register. - // In other words, it's safe to block until TX FIFO is - // EMPTY--it will empty from being transmitted or on error. - for i2c.Bus.GetIC_RAW_INTR_STAT_TX_EMPTY() == 0 { - } - } - - // This Tx abort is a normal case - we're sending more - // data than controller wants to receive - if i2c.Bus.GetIC_RAW_INTR_STAT_TX_ABRT() != 0 { - i2c.Bus.GetIC_CLR_TX_ABRT_CLR_TX_ABRT() - return nil - } - - gosched() - } - - return nil -} - -// writeAvailable determines non-blocking write space available -// -//go:inline -func (i2c *I2C) writeAvailable() uint32 { - return rp.I2C0_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_Pos - i2c.Bus.IC_TXFLR.Get() -} - -// readAvailable determines number of bytes received -// -//go:inline -func (i2c *I2C) readAvailable() uint32 { - return i2c.Bus.IC_RXFLR.Get() -} - -// Equivalent to IC_CLR_TX_ABRT.Get() (side effect clears ABORT_REASON) -// -//go:inline -func (i2c *I2C) clearAbortReason() { - // Note clearing the abort flag also clears the reason, and - // this instance of flag is clear-on-read! Note also the - // IC_CLR_TX_ABRT register always reads as 0. - i2c.Bus.IC_CLR_TX_ABRT.Get() -} - -// getAbortReason reads IC_TX_ABRT_SOURCE register. -// -//go:inline -func (i2c *I2C) getAbortReason() i2cAbortError { - return i2cAbortError(i2c.Bus.IC_TX_ABRT_SOURCE.Get()) -} - -// returns true if RAW_INTR_STAT bits in mask are all set. performs: -// -// RAW_INTR_STAT & mask == mask -// -//go:inline -func (i2c *I2C) interrupted(mask uint32) bool { - reg := i2c.Bus.IC_RAW_INTR_STAT.Get() - return reg&mask == mask -} - -type i2cAbortError uint32 - -func (b i2cAbortError) Error() string { - return "i2c abort, reason " + itoa.Uitoa(uint(b)) -} - -func (b i2cAbortError) Reasons() (reasons []string) { - if b == 0 { - return nil - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK != 0 { - reasons = append(reasons, "7-bit address no ack") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK != 0 { - reasons = append(reasons, "10-bit address first byte no ack") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK != 0 { - reasons = append(reasons, "10-bit address second byte no ack") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK != 0 { - reasons = append(reasons, "tx data no ack") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK != 0 { - reasons = append(reasons, "general call no ack") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ != 0 { - reasons = append(reasons, "general call read") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET != 0 { - reasons = append(reasons, "high speed ack detect") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET != 0 { - reasons = append(reasons, "start byte ack detect") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT != 0 { - reasons = append(reasons, "high speed no restart") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT != 0 { - reasons = append(reasons, "start byte no restart") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT != 0 { - reasons = append(reasons, "10-bit read no restart") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS != 0 { - reasons = append(reasons, "master disabled") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ARB_LOST != 0 { - reasons = append(reasons, "arbitration lost") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO != 0 { - reasons = append(reasons, "slave flush tx fifo") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST != 0 { - reasons = append(reasons, "slave arbitration lost") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX != 0 { - reasons = append(reasons, "slave read while inactive") - } - if b&rp.I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT != 0 { - reasons = append(reasons, "user abort") - } - return reasons -} diff --git a/emb/machine/machine_rp2_pins.go b/emb/machine/machine_rp2_pins.go deleted file mode 100644 index 36e9bd6..0000000 --- a/emb/machine/machine_rp2_pins.go +++ /dev/null @@ -1,37 +0,0 @@ -//go:build rp2040 || rp2350 || gopher_badge || pico - -package machine - -const ( - // GPIO pins - GPIO0 Pin = 0 // peripherals: PWM0 channel A - GPIO1 Pin = 1 // peripherals: PWM0 channel B - GPIO2 Pin = 2 // peripherals: PWM1 channel A - GPIO3 Pin = 3 // peripherals: PWM1 channel B - GPIO4 Pin = 4 // peripherals: PWM2 channel A - GPIO5 Pin = 5 // peripherals: PWM2 channel B - GPIO6 Pin = 6 // peripherals: PWM3 channel A - GPIO7 Pin = 7 // peripherals: PWM3 channel B - GPIO8 Pin = 8 // peripherals: PWM4 channel A - GPIO9 Pin = 9 // peripherals: PWM4 channel B - GPIO10 Pin = 10 // peripherals: PWM5 channel A - GPIO11 Pin = 11 // peripherals: PWM5 channel B - GPIO12 Pin = 12 // peripherals: PWM6 channel A - GPIO13 Pin = 13 // peripherals: PWM6 channel B - GPIO14 Pin = 14 // peripherals: PWM7 channel A - GPIO15 Pin = 15 // peripherals: PWM7 channel B - GPIO16 Pin = 16 // peripherals: PWM0 channel A - GPIO17 Pin = 17 // peripherals: PWM0 channel B - GPIO18 Pin = 18 // peripherals: PWM1 channel A - GPIO19 Pin = 19 // peripherals: PWM1 channel B - GPIO20 Pin = 20 // peripherals: PWM2 channel A - GPIO21 Pin = 21 // peripherals: PWM2 channel B - GPIO22 Pin = 22 // peripherals: PWM3 channel A - GPIO23 Pin = 23 // peripherals: PWM3 channel B - GPIO24 Pin = 24 // peripherals: PWM4 channel A - GPIO25 Pin = 25 // peripherals: PWM4 channel B - GPIO26 Pin = 26 // peripherals: PWM5 channel A - GPIO27 Pin = 27 // peripherals: PWM5 channel B - GPIO28 Pin = 28 // peripherals: PWM6 channel A - GPIO29 Pin = 29 // peripherals: PWM6 channel B -) diff --git a/emb/machine/machine_rp2_pll.go b/emb/machine/machine_rp2_pll.go deleted file mode 100644 index d576084..0000000 --- a/emb/machine/machine_rp2_pll.go +++ /dev/null @@ -1,279 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "errors" - "math" - "math/bits" - "runtime/volatile" - "unsafe" -) - -type pll struct { - cs volatile.Register32 - pwr volatile.Register32 - fbDivInt volatile.Register32 - prim volatile.Register32 -} - -var ( - pllSys = (*pll)(unsafe.Pointer(rp.PLL_SYS)) - pllUSB = (*pll)(unsafe.Pointer(rp.PLL_USB)) -) - -// init initializes pll (Sys or USB) given the following parameters. -// -// Input clock divider, refdiv. -// -// Requested output frequency from the VCO (voltage controlled oscillator), vcoFreq. -// -// Post Divider 1, postDiv1 with range 1-7 and be >= postDiv2. -// -// Post Divider 2, postDiv2 with range 1-7. -func (pll *pll) init(refdiv, fbdiv, postDiv1, postDiv2 uint32) { - refFreq := xoscFreq / refdiv - - // What are we multiplying the reference clock by to get the vco freq - // (The regs are called div, because you divide the vco output and compare it to the refclk) - - // Check fbdiv range - if !(fbdiv >= 16 && fbdiv <= 320) { - panic("fbdiv should be in the range [16,320]") - } - - // Check divider ranges - if !((postDiv1 >= 1 && postDiv1 <= 7) && (postDiv2 >= 1 && postDiv2 <= 7)) { - panic("postdiv1, postdiv1 should be in the range [1,7]") - } - - // postDiv1 should be >= postDiv2 - // from appnote page 11 - // postdiv1 is designed to operate with a higher input frequency - // than postdiv2 - if postDiv1 < postDiv2 { - panic("postdiv1 should be greater than or equal to postdiv2") - } - - // Check that reference frequency is no greater than vcoFreq / 16 - vcoFreq := calcVCO(xoscFreq, fbdiv, refdiv) - if refFreq > vcoFreq/16 { - panic("reference frequency should not be greater than vco frequency divided by 16") - } - - // div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10 - pdiv := uint32(postDiv1)< maxVCO { - break - } - calcPD12 := vco / targetFreq - if calcPD12 < 1 { - calcPD12 = 1 - } else if calcPD12 > 49 { - calcPD12 = 49 - } - iters++ - pd1 = pdTable[calcPD12].hivco[0] - pd2 = pdTable[calcPD12].hivco[1] - fout, err := pllFreqOutPostdiv(xoscRef, fbdiv, MHz, refdiv, pd1, pd2) - found := false - margin := abs(int64(fout) - int64(targetFreq)) - if err == nil && margin <= bestMargin { - found = true - bestFreq = fout - bestFbdiv = fbdiv - bestpd1 = pd1 - bestpd2 = pd2 - bestRefdiv = refdiv - bestMargin = margin - } - pd1 = pdTable[calcPD12].lovco[0] - pd2 = pdTable[calcPD12].lovco[1] - fout, err = pllFreqOutPostdiv(xoscRef, fbdiv, MHz, refdiv, pd1, pd2) - margin = abs(int64(fout) - int64(targetFreq)) - if err == nil && margin <= bestMargin { - found = true - bestFreq = fout - bestFbdiv = fbdiv - bestpd1 = pd1 - bestpd2 = pd2 - bestRefdiv = refdiv - bestMargin = margin - } - if found && ps.LowerVCO { - break - } - } - } - if bestFreq == 0 { - return fbdiv, refdiv, pd1, pd2, errors.New("no best frequency found") - } - return bestFbdiv, bestRefdiv, bestpd1, bestpd2, nil -} - -func abs(a int64) int64 { - if a == math.MinInt64 { - return math.MaxInt64 - } else if a < 0 { - return -a - } - return a -} - -func pllFreqOutPostdiv(xosc, fbdiv, MHz uint64, refdiv, postdiv1, postdiv2 uint8) (foutpostdiv uint64, err error) { - // testing grounds. - const ( - mhz = 1 - cfref = 12 * mhz // given by crystal oscillator selection. - crefd = 1 - cfbdiv = 100 - cvco = cfref * cfbdiv / crefd - cpd1 = 6 - cpd2 = 2 - foutpd = (cfref / crefd) * cfbdiv / (cpd1 * cpd2) - ) - refFreq := xosc / uint64(refdiv) - overflow, vco := bits.Mul64(xosc, fbdiv) - vco /= uint64(refdiv) - foutpostdiv = vco / uint64(postdiv1*postdiv2) - switch { - case refdiv < 1 || refdiv > 63: - err = errors.New("reference divider out of range") - case fbdiv < 16 || fbdiv > 320: - err = errors.New("feedback divider out of range") - case postdiv1 < 1 || postdiv1 > 7: - err = errors.New("postdiv1 out of range") - case postdiv2 < 1 || postdiv2 > 7: - err = errors.New("postdiv2 out of range") - case postdiv1 < postdiv2: - err = errors.New("user error: use higher value for postdiv1 for lower power consumption") - case vco < 750*MHz || vco > 1600*MHz: - err = errors.New("VCO out of range") - case refFreq < 5*MHz: - err = errors.New("minimum reference frequency breach") - case refFreq > vco/16: - err = errors.New("maximum reference frequency breach") - case vco > 1200*MHz && vco < 1600*MHz && xosc < 75*MHz && refdiv != 1: - err = errors.New("refdiv should be 1 for given VCO and reference frequency") - case overflow != 0: - err = errVCOOverflow - } - if err != nil { - return 0, err - } - return foutpostdiv, nil -} - -func calcVCO(xoscFreq, fbdiv, refdiv uint32) uint32 { - const maxXoscMHz = math.MaxUint32 / 320 / MHz // 13MHz maximum xosc apparently. - if fbdiv > 320 || xoscFreq > math.MaxUint32/320 { - panic("invalid VCO calculation args") - } - return xoscFreq * fbdiv / refdiv -} - -var pdTable = [50]struct { - hivco [2]uint8 - lovco [2]uint8 -}{} - -func genTable() { - if pdTable[1].hivco[1] != 0 { - return // Already generated. - } - for product := 1; product < len(pdTable); product++ { - bestProdhi := 255 - bestProdlo := 255 - for pd1 := 7; pd1 > 0; pd1-- { - for pd2 := pd1; pd2 > 0; pd2-- { - gotprod := pd1 * pd2 - if abs(int64(gotprod-product)) < abs(int64(bestProdlo-product)) { - bestProdlo = gotprod - pdTable[product].lovco[0] = uint8(pd1) - pdTable[product].lovco[1] = uint8(pd2) - } - } - } - for pd1 := 1; pd1 < 8; pd1++ { - for pd2 := 1; pd2 <= pd1; pd2++ { - gotprod := pd1 * pd2 - if abs(int64(gotprod-product)) < abs(int64(bestProdhi-product)) { - bestProdhi = gotprod - pdTable[product].hivco[0] = uint8(pd1) - pdTable[product].hivco[1] = uint8(pd2) - } - } - } - } -} diff --git a/emb/machine/machine_rp2_pwm.go b/emb/machine/machine_rp2_pwm.go deleted file mode 100644 index 772811e..0000000 --- a/emb/machine/machine_rp2_pwm.go +++ /dev/null @@ -1,420 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "errors" - "math" - "runtime/volatile" - "unsafe" -) - -var ( - ErrBadPeriod = errors.New("period outside valid range 8ns..268ms") -) - -const ( - maxPWMPins = _NUMBANK0_GPIOS - 1 -) - -// pwmGroup is one PWM peripheral, which consists of a counter and two output -// channels. You can set the frequency using SetPeriod, -// but only for all the channels in this PWM peripheral at once. -// -// div: integer value to reduce counting rate by. Must be greater than or equal to 1. -// -// cc: counter compare level. Contains 2 channel levels. The 16 LSBs are Channel A's level (Duty Cycle) -// and the 16 MSBs are Channel B's level. -// -// top: Wrap. Highest number counter will reach before wrapping over. usually 0xffff. -// -// csr: Clock mode. PWM_CH0_CSR_DIVMODE_xxx registers have 4 possible modes, of which Free-running is used. -// csr contains output polarity bit at PWM_CH0_CSR_x_INV where x is the channel. -// csr contains phase correction bit at PWM_CH0_CSR_PH_CORRECT_Msk. -// csr contains PWM enable bit at PWM_CH0_CSR_EN. If not enabled PWM will not be active. -// -// ctr: PWM counter value. -type pwmGroup struct { - CSR volatile.Register32 - DIV volatile.Register32 - CTR volatile.Register32 - CC volatile.Register32 - TOP volatile.Register32 -} - -// Equivalent of -// -// var pwmSlice []pwmGroup = (*[8]pwmGroup)(unsafe.Pointer(rp.PWM))[:] -// return &pwmSlice[index] -// -// 0x14 is the size of a pwmGroup. -func getPWMGroup(index uintptr) *pwmGroup { - return (*pwmGroup)(unsafe.Add(unsafe.Pointer(rp.PWM), 0x14*index)) -} - -// Hardware Pulse Width Modulation (PWM) API -// PWM peripherals available on RP2040. Each peripheral has 2 pins available for -// a total of 16 available PWM outputs. Some pins may not be available on some boards. -// -// The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or -// measure the frequency or duty cycle of an input signal. This gives a total of up to 16 controllable -// PWM outputs. All 30 GPIOs can be driven by the PWM block -// -// The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a -// toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of -// time spent at the high signal level is known as the duty cycle of the signal. -// -// The default behaviour of a PWM slice is to count upward until the wrap value (\ref pwm_config_set_wrap) is reached, and then -// immediately wrap to 0. PWM slices also offer a phase-correct mode, where the counter starts to count downward after -// reaching TOP, until it reaches 0 again. -var ( - PWM0 = getPWMGroup(0) - PWM1 = getPWMGroup(1) - PWM2 = getPWMGroup(2) - PWM3 = getPWMGroup(3) - PWM4 = getPWMGroup(4) - PWM5 = getPWMGroup(5) - PWM6 = getPWMGroup(6) - PWM7 = getPWMGroup(7) -) - -// Configure enables and configures this PWM. -func (pwm *pwmGroup) Configure(config PWMConfig) error { - return pwm.init(config, true) -} - -// Channel returns a PWM channel for the given pin. If pin does -// not belong to PWM peripheral ErrInvalidOutputPin error is returned. -// It also configures pin as PWM output. -func (pwm *pwmGroup) Channel(pin Pin) (channel uint8, err error) { - if pin > maxPWMPins || pwmGPIOToSlice(pin) != pwm.peripheral() { - return 3, ErrInvalidOutputPin - } - pin.Configure(PinConfig{PinPWM}) - return pwmGPIOToChannel(pin), nil -} - -// Peripheral returns the RP2040 PWM peripheral which ranges from 0 to 7. Each -// PWM peripheral has 2 channels, A and B which correspond to 0 and 1 in the program. -// This number corresponds to the package's PWM0 throughout PWM7 handles -func PWMPeripheral(pin Pin) (sliceNum uint8, err error) { - if pin > maxPWMPins { - return 0, ErrInvalidOutputPin - } - return pwmGPIOToSlice(pin), nil -} - -// returns the number of the pwm peripheral (0-7) -func (pwm *pwmGroup) peripheral() uint8 { - return uint8((uintptr(unsafe.Pointer(pwm)) - uintptr(unsafe.Pointer(rp.PWM))) / 0x14) -} - -// SetPeriod updates the period of this PWM peripheral in nanoseconds. -// To set a particular frequency, use the following formula: -// -// period = 1e9 / frequency -// -// Where frequency is in hertz. If you use a period of 0, a period -// that works well for LEDs will be picked. -// -// SetPeriod will try not to modify TOP if possible to reach the target period. -// If the period is unattainable with current TOP SetPeriod will modify TOP -// by the bare minimum to reach the target period. It will also enable phase -// correct to reach periods above 130ms. -func (p *pwmGroup) SetPeriod(period uint64) error { - if period == 0 { - period = 1e5 - } - return p.setPeriod(period) -} - -// Top returns the current counter top, for use in duty cycle calculation. -// -// The value returned here is hardware dependent. In general, it's best to treat -// it as an opaque value that can be divided by some number and passed to Set -// (see Set documentation for more information). -func (p *pwmGroup) Top() uint32 { - return p.getWrap() -} - -// Counter returns the current counter value of the timer in this PWM -// peripheral. It may be useful for debugging. -func (p *pwmGroup) Counter() uint32 { - return (p.CTR.Get() & rp.PWM_CH0_CTR_CH0_CTR_Msk) >> rp.PWM_CH0_CTR_CH0_CTR_Pos -} - -// Period returns the used PWM period in nanoseconds. -func (p *pwmGroup) Period() uint64 { - // Lines below can overflow if operations done without care. - // maxInt=255, maxFrac=15, maxTop=65536, maxPHC=1 => maxProduct= (16*255+15) * (65536*2*1e9) = 5.3673e17 < MaxUint64=1.8e19 (close call.) - const compileTimeCheckPeriod uint64 = (255*16 + 15) * (65535 + 1) * 2 * 1e9 - freq := uint64(CPUFrequency()) - top := p.getWrap() - phc := p.getPhaseCorrect() - Int, frac := p.getClockDiv() - return (16*uint64(Int) + uint64(frac)) * uint64((top+1)*(phc+1)*1e9) / (16 * freq) // cycles = (TOP+1) * (CSRPHCorrect + 1) * (DIV_INT + DIV_FRAC/16) -} - -// SetInverting sets whether to invert the output of this channel. -// Without inverting, a 25% duty cycle would mean the output is high for 25% of -// the time and low for the rest. Inverting flips the output as if a NOT gate -// was placed at the output, meaning that the output would be 25% low and 75% -// high with a duty cycle of 25%. -func (p *pwmGroup) SetInverting(channel uint8, inverting bool) { - channel &= 1 - p.setInverting(channel, inverting) -} - -// Set updates the channel value. This is used to control the channel duty -// cycle, in other words the fraction of time the channel output is high (or low -// when inverted). For example, to set it to a 25% duty cycle, use: -// -// pwm.Set(channel, pwm.Top() / 4) -// -// pwm.Set(channel, 0) will set the output to low and pwm.Set(channel, -// pwm.Top()) will set the output to high, assuming the output isn't inverted. -func (p *pwmGroup) Set(channel uint8, value uint32) { - val := uint16(value) - channel &= 1 - p.setChanLevel(channel, val) -} - -// Get current level (last set by Set). Default value on initialization is 0. -func (p *pwmGroup) Get(channel uint8) (value uint32) { - channel &= 1 - return uint32(p.getChanLevel(channel)) -} - -// SetTop sets TOP control register. Max value is 16bit (0xffff). -func (p *pwmGroup) SetTop(top uint32) { - p.setWrap(uint16(top)) -} - -// SetCounter sets counter control register. Max value is 16bit (0xffff). -// Useful for synchronising two different PWM peripherals. -func (p *pwmGroup) SetCounter(ctr uint32) { - p.CTR.Set(ctr) -} - -// Enable enables or disables PWM peripheral channels. -func (p *pwmGroup) Enable(enable bool) { - p.enable(enable) -} - -// IsEnabled returns true if peripheral is enabled. -func (p *pwmGroup) IsEnabled() (enabled bool) { - return (p.CSR.Get()&rp.PWM_CH0_CSR_EN_Msk)>>rp.PWM_CH0_CSR_EN_Pos != 0 -} - -// Initialise a PWM with settings from a configuration object. -// If start is true then PWM starts on initialization. -func (pwm *pwmGroup) init(config PWMConfig, start bool) error { - // Not enable Phase correction - pwm.setPhaseCorrect(false) - - // Clock mode set by default to Free running - pwm.setDivMode(rp.PWM_CH0_CSR_DIVMODE_DIV) - - // Set Output polarity (false/false) - pwm.setInverting(0, false) - pwm.setInverting(1, false) - - // Set wrap. The highest value the counter will reach before returning to zero, also known as TOP. - pwm.setWrap(0xffff) - // period is set after TOP (Wrap). - err := pwm.SetPeriod(config.Period) - if err != nil { - return err - } - // period already set beforea - // Reset counter and compare (pwm level set to zero) - pwm.CTR.ReplaceBits(0, rp.PWM_CH0_CTR_CH0_CTR_Msk, 0) // PWM_CH0_CTR_RESET - pwm.CC.Set(0) // PWM_CH0_CC_RESET - - pwm.enable(start) - return nil -} - -func (pwm *pwmGroup) setPhaseCorrect(correct bool) { - pwm.CSR.ReplaceBits(boolToBit(correct)< maxPeriod || period < 8 { - return ErrBadPeriod - } - if period > maxPeriod/2 { - pwm.setPhaseCorrect(true) // Must enable Phase correct to reach large periods. - } - - // clearing above expression: - // DIV_INT + DIV_FRAC/16 = cycles / ( (TOP+1) * (CSRPHCorrect+1) ) // DIV_FRAC/16 is always 0 in this equation - // where cycles must be converted to time: - // target_period = cycles * period_per_cycle ==> cycles = target_period/period_per_cycle - var ( - freq = uint64(CPUFrequency()) - phc = uint64(pwm.getPhaseCorrect()) - rhs = 16 * period * freq / ((1 + phc) * 1e9 * (1 + topStart)) // right-hand-side of equation, scaled so frac is not divided - whole = rhs / 16 - frac = rhs % 16 - ) - switch { - case whole > 0xff: - whole = 0xff - case whole == 0: - // whole calculation underflowed so setting to minimum - // permissible value in DIV_INT register. - whole = 1 - frac = 0 - } - - // Step 2 is acquiring a better top value. Clearing the equation: - // TOP = cycles / ( (DIVINT+DIVFRAC/16) * (CSRPHCorrect+1) ) - 1 - top := 16*period*freq/((1+phc)*1e9*(16*whole+frac)) - 1 - if top > maxTop { - top = maxTop - } - pwm.SetTop(uint32(top)) - pwm.setClockDiv(uint8(whole), uint8(frac)) - return nil -} - -// Int is integer value to reduce counting rate by. Must be greater than or equal to 1. DIV_INT is bits 4:11 (8 bits). -// frac's (DIV_FRAC) default value on reset is 0. Max value for frac is 15 (4 bits). This is known as a fixed-point -// fractional number. -// -// cycles = (TOP+1) * (CSRPHCorrect + 1) * (DIV_INT + DIV_FRAC/16) -func (pwm *pwmGroup) setClockDiv(Int, frac uint8) { - pwm.DIV.ReplaceBits((uint32(frac)<> pos) - return level -} - -func (pwm *pwmGroup) getWrap() (top uint32) { - return (pwm.TOP.Get() & rp.PWM_CH0_TOP_CH0_TOP_Msk) >> rp.PWM_CH0_TOP_CH0_TOP_Pos -} - -func (pwm *pwmGroup) getPhaseCorrect() (phCorrect uint32) { - return (pwm.CSR.Get() & rp.PWM_CH0_CSR_PH_CORRECT_Msk) >> rp.PWM_CH0_CSR_PH_CORRECT_Pos -} - -func (pwm *pwmGroup) getClockDiv() (Int, frac uint8) { - div := pwm.DIV.Get() - return uint8((div & rp.PWM_CH0_DIV_INT_Msk) >> rp.PWM_CH0_DIV_INT_Pos), uint8((div & rp.PWM_CH0_DIV_FRAC_Msk) >> rp.PWM_CH0_DIV_FRAC_Pos) -} - -// pwmGPIOToSlice Determine the PWM channel that is attached to the specified GPIO. -// gpio must be less than 30. Returns the PWM slice number that controls the specified GPIO. -func pwmGPIOToSlice(gpio Pin) (slicenum uint8) { - if is48Pin && gpio >= 32 { - return uint8(8 + ((gpio-32)/2)%4) - } - return (uint8(gpio) >> 1) & 7 -} - -// Determine the PWM channel that is attached to the specified GPIO. -// Each slice 0 to 7 has two channels, A and B. -func pwmGPIOToChannel(gpio Pin) (channel uint8) { - return uint8(gpio) & 1 -} diff --git a/emb/machine/machine_rp2_resets.go b/emb/machine/machine_rp2_resets.go deleted file mode 100644 index 245436c..0000000 --- a/emb/machine/machine_rp2_resets.go +++ /dev/null @@ -1,31 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "unsafe" -) - -var resets = (*rp.RESETS_Type)(unsafe.Pointer(rp.RESETS)) - -// resetBlock resets hardware blocks specified -// by the bit pattern in bits. -func resetBlock(bits uint32) { - resets.RESET.SetBits(bits) -} - -// unresetBlock brings hardware blocks specified by the -// bit pattern in bits out of reset. -func unresetBlock(bits uint32) { - resets.RESET.ClearBits(bits) -} - -// unresetBlockWait brings specified hardware blocks -// specified by the bit pattern in bits -// out of reset and wait for completion. -func unresetBlockWait(bits uint32) { - unresetBlock(bits) - for !resets.RESET_DONE.HasBits(bits) { - } -} diff --git a/emb/machine/machine_rp2_rng.go b/emb/machine/machine_rp2_rng.go deleted file mode 100644 index e619f05..0000000 --- a/emb/machine/machine_rp2_rng.go +++ /dev/null @@ -1,41 +0,0 @@ -//go:build rp2040 || rp2350 - -// Implementation based on code located here: -// https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/pico_lwip/random.c - -package machine - -import ( - "device/rp" -) - -const numberOfCycles = 32 - -// GetRNG returns 32 bits of semi-random data based on ring oscillator. -// -// Unlike some other implementations of GetRNG, these random numbers are not -// cryptographically secure and must not be used for cryptographic operations -// (nonces, etc). -func GetRNG() (uint32, error) { - var val uint32 - for i := 0; i < 4; i++ { - val = (val << 8) | uint32(roscRandByte()) - } - return val, nil -} - -var randomByte uint8 - -func roscRandByte() uint8 { - var poly uint8 - for i := 0; i < numberOfCycles; i++ { - if randomByte&0x80 != 0 { - poly = 0x35 - } else { - poly = 0 - } - randomByte = ((randomByte << 1) | uint8(rp.ROSC.GetRANDOMBIT()) ^ poly) - // TODO: delay a little because the random bit is a little slow - } - return randomByte -} diff --git a/emb/machine/machine_rp2_spi.go b/emb/machine/machine_rp2_spi.go deleted file mode 100644 index d9cfc11..0000000 --- a/emb/machine/machine_rp2_spi.go +++ /dev/null @@ -1,404 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "errors" - "unsafe" -) - -// SPI on the RP2040 -var ( - SPI0 = &SPI{ - Bus: rp.SPI0, - } - SPI1 = &SPI{ - Bus: rp.SPI1, - } -) - -// SPIConfig is used to store config info for SPI. -type SPIConfig struct { - Frequency uint32 - // LSB not supported on rp2040. - LSBFirst bool - // Mode's two most LSB are CPOL and CPHA. i.e. Mode==2 (0b10) is CPOL=1, CPHA=0 - Mode uint8 - // Serial clock pin - SCK Pin - // TX or Serial Data Out (MOSI if rp2040 is master) - SDO Pin - // RX or Serial Data In (MISO if rp2040 is master) - SDI Pin -} - -var ( - ErrLSBNotSupported = errors.New("SPI LSB unsupported on PL022") - ErrSPITimeout = errors.New("SPI timeout") - ErrSPIBaud = errors.New("SPI baud too low or above 66.5Mhz") - errSPIInvalidSDI = errors.New("invalid SPI SDI pin") - errSPIInvalidSDO = errors.New("invalid SPI SDO pin") - errSPIInvalidSCK = errors.New("invalid SPI SCK pin") -) - -type SPI struct { - Bus *rp.SPI0_Type -} - -// Tx handles read/write operation for SPI interface. Since SPI is a synchronous write/read -// interface, there must always be the same number of bytes written as bytes read. -// The Tx method knows about this, and offers a few different ways of calling it. -// -// This form sends the bytes in tx buffer, putting the resulting bytes read into the rx buffer. -// Note that the tx and rx buffers must be the same size: -// -// spi.Tx(tx, rx) -// -// This form sends the tx buffer, ignoring the result. Useful for sending "commands" that return zeros -// until all the bytes in the command packet have been received: -// -// spi.Tx(tx, nil) -// -// This form sends zeros, putting the result into the rx buffer. Good for reading a "result packet": -// -// spi.Tx(nil, rx) -// -// Remark: This implementation (RP2040) allows reading into buffer with a custom repeated -// value on tx. -// -// spi.Tx([]byte{0xff}, rx) // may cause unwanted heap allocations. -// -// This form sends 0xff and puts the result into rx buffer. Useful for reading from SD cards -// which require 0xff input on SI. -func (spi *SPI) Tx(w, r []byte) (err error) { - switch { - case w == nil: - // read only, so write zero and read a result. - err = spi.rx(r, 0) - case r == nil: - // write only - err = spi.tx(w) - case len(w) == 1 && len(r) > 1: - // Read with custom repeated value. - err = spi.rx(r, w[0]) - default: - // write/read - err = spi.txrx(w, r) - } - return err -} - -// Write a single byte and read a single byte from TX/RX FIFO. -func (spi *SPI) Transfer(w byte) (byte, error) { - for !spi.isWritable() { - } - - spi.Bus.SSPDR.Set(uint32(w)) - - for !spi.isReadable() { - } - return uint8(spi.Bus.SSPDR.Get()), nil -} - -func (spi *SPI) SetBaudRate(br uint32) error { - const maxBaud uint32 = 66.5 * MHz // max output frequency is 66.5MHz on rp2040. see Note page 527. - // Find smallest prescale value which puts output frequency in range of - // post-divide. Prescale is an even number from 2 to 254 inclusive. - var prescale, postdiv uint32 - freq := CPUFrequency() - for prescale = 2; prescale < 255; prescale += 2 { - if freq < (prescale+2)*256*br { - break - } - } - if prescale > 254 || br > maxBaud { - return ErrSPIBaud - } - // Find largest post-divide which makes output <= baudrate. Post-divide is - // an integer in the range 1 to 256 inclusive. - for postdiv = 256; postdiv > 1; postdiv-- { - if freq/(prescale*(postdiv-1)) > br { - break - } - } - spi.Bus.SSPCPSR.Set(prescale) - spi.Bus.SSPCR0.ReplaceBits((postdiv-1)<> rp.SPI0_SSPCR0_SCR_Pos) + 1 - return freqin / (prescale * postdiv) -} - -// Configure is intended to setup/initialize the SPI interface. -// Default baudrate of 4MHz is used if Frequency == 0. Default -// word length (data bits) is 8. -// Below is a list of GPIO pins corresponding to SPI0 bus on the rp2040: -// -// SI : 0, 4, 17 a.k.a RX and MISO (if rp2040 is master) -// SO : 3, 7, 19 a.k.a TX and MOSI (if rp2040 is master) -// SCK: 2, 6, 18 -// -// SPI1 bus GPIO pins: -// -// SI : 8, 12 -// SO : 11, 15 -// SCK: 10, 14 -// -// No pin configuration is needed of SCK, SDO and SDI needed after calling Configure. -func (spi *SPI) Configure(config SPIConfig) error { - const defaultBaud uint32 = 4 * MHz - if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 { - // set default pins if config zero valued or invalid clock pin supplied. - switch spi.Bus { - case rp.SPI0: - config.SCK = SPI0_SCK_PIN - config.SDO = SPI0_SDO_PIN - config.SDI = SPI0_SDI_PIN - case rp.SPI1: - config.SCK = SPI1_SCK_PIN - config.SDO = SPI1_SDO_PIN - config.SDI = SPI1_SDI_PIN - } - } - var okSDI, okSDO, okSCK bool - switch spi.Bus { - case rp.SPI0: - okSDI = config.SDI == 0 || config.SDI == 4 || config.SDI == 16 || config.SDI == 20 - okSDO = config.SDO == 3 || config.SDO == 7 || config.SDO == 19 || config.SDO == 23 - okSCK = config.SCK == 2 || config.SCK == 6 || config.SCK == 18 || config.SCK == 22 - case rp.SPI1: - okSDI = config.SDI == 8 || config.SDI == 12 || config.SDI == 24 || config.SDI == 28 - okSDO = config.SDO == 11 || config.SDO == 15 || config.SDO == 27 - okSCK = config.SCK == 10 || config.SCK == 14 || config.SCK == 26 - } - - switch { - case !okSDI: - return errSPIInvalidSDI - case !okSDO: - return errSPIInvalidSDO - case !okSCK: - return errSPIInvalidSCK - } - - if config.Frequency == 0 { - config.Frequency = defaultBaud - } - // SPI pin configuration - config.SCK.setFunc(fnSPI) - config.SDO.setFunc(fnSPI) - config.SDI.setFunc(fnSPI) - - return spi.initSPI(config) -} - -func (spi *SPI) initSPI(config SPIConfig) (err error) { - spi.reset() - // LSB-first not supported on PL022: - if config.LSBFirst { - return ErrLSBNotSupported - } - err = spi.SetBaudRate(config.Frequency) - // Set SPI Format (CPHA and CPOL) and frame format (default is Motorola) - spi.setFormat(config.Mode) - - // Always enable DREQ signals -- harmless if DMA is not listening - spi.Bus.SSPDMACR.SetBits(rp.SPI0_SSPDMACR_TXDMAE | rp.SPI0_SSPDMACR_RXDMAE) - // Finally enable the SPI - spi.Bus.SSPCR1.SetBits(rp.SPI0_SSPCR1_SSE) - return err -} - -//go:inline -func (spi *SPI) setFormat(mode uint8) { - cpha := uint32(mode) & 1 - cpol := uint32(mode>>1) & 1 - spi.Bus.SSPCR0.ReplaceBits( - (cpha<>3].Set(p.ioIntBit(change)) -} - -// Basic interrupt setting via ioBANK0 for GPIO interrupts. -func (p Pin) setInterrupt(change PinChange, enabled bool) { - // Separate mask/force/status per-core, so check which core called, and - // set the relevant IRQ controls. - switch CurrentCore() { - case 0: - p.ctrlSetInterrupt(change, enabled, &ioBank0.proc0IRQctrl) - case 1: - p.ctrlSetInterrupt(change, enabled, &ioBank0.proc1IRQctrl) - } -} - -// ctrlSetInterrupt acknowledges any pending interrupt and enables or disables -// the interrupt for a given IRQ control bank (IOBANK, DormantIRQ, QSPI). -// -// pico-sdk calls this the _gpio_set_irq_enabled, not to be confused with -// gpio_set_irq_enabled (no leading underscore). -func (p Pin) ctrlSetInterrupt(change PinChange, enabled bool, base *irqCtrl) { - p.acknowledgeInterrupt(change) - enReg := &base.intE[p>>3] - if enabled { - enReg.SetBits(p.ioIntBit(change)) - } else { - enReg.ClearBits(p.ioIntBit(change)) - } -} diff --git a/emb/machine/machine_rp2_timer.go b/emb/machine/machine_rp2_timer.go deleted file mode 100644 index a78ed70..0000000 --- a/emb/machine/machine_rp2_timer.go +++ /dev/null @@ -1,103 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/arm" - "runtime/interrupt" - "runtime/volatile" -) - -const numTimers = 4 - -// Alarm0 is reserved for sleeping by tinygo runtime code for RP2040. -// Alarm0 is also IRQ0 -const sleepAlarm = 0 -const sleepAlarmIRQ = 0 - -// The minimum sleep duration in μs (ticks) -const minSleep = 10 - -type timerType struct { - timeHW volatile.Register32 - timeLW volatile.Register32 - timeHR volatile.Register32 - timeLR volatile.Register32 - alarm [numTimers]volatile.Register32 - armed volatile.Register32 - timeRawH volatile.Register32 - timeRawL volatile.Register32 - dbgPause volatile.Register32 - pause volatile.Register32 - locked [rp2350ExtraReg]volatile.Register32 - source [rp2350ExtraReg]volatile.Register32 - intR volatile.Register32 - intE volatile.Register32 - intF volatile.Register32 - intS volatile.Register32 -} - -// TimeElapsed returns time elapsed since power up, in microseconds. -func (tmr *timerType) timeElapsed() (us uint64) { - // Need to make sure that the upper 32 bits of the timer - // don't change, so read that first - hi := tmr.timeRawH.Get() - var lo, nextHi uint32 - for { - // Read the lower 32 bits - lo = tmr.timeRawL.Get() - // Now read the upper 32 bits again and - // check that it hasn't incremented. If it has, loop around - // and read the lower 32 bits again to get an accurate value - nextHi = tmr.timeRawH.Get() - if hi == nextHi { - break - } - hi = nextHi - } - return uint64(hi)<<32 | uint64(lo) -} - -// lightSleep will put the processor into a sleep state a short period -// (up to approx 72mins per RP2040 datasheet, 4.6.3. Alarms). -// -// This function is a 'light' sleep and will return early if another -// interrupt or event triggers. This is intentional since the -// primary use-case is for use by the TinyGo scheduler which will -// re-sleep if needed. -func (tmr *timerType) lightSleep(us uint64) { - // minSleep is a way to avoid race conditions for short - // sleeps by ensuring there is enough time to setup the - // alarm before sleeping. For very short sleeps, this - // effectively becomes a 'busy loop'. - if us < minSleep { - return - } - - // Interrupt handler is essentially a no-op, we're just relying - // on the side-effect of waking the CPU from "wfe" - intr := interrupt.New(sleepAlarmIRQ, func(interrupt.Interrupt) { - // Clear the IRQ - timer.intR.Set(1 << sleepAlarm) - }) - - // Reset interrupt flag - tmr.intR.Set(1 << sleepAlarm) - - // Enable interrupt - tmr.intE.SetBits(1 << sleepAlarm) - intr.Enable() - - // Only the low 32 bits of time can be used for alarms - target := uint64(tmr.timeRawL.Get()) + us - tmr.alarm[sleepAlarm].Set(uint32(target)) - - // Wait for sleep (or any other) interrupt - arm.Asm("wfe") - - // Disarm timer - tmr.armed.Set(1 << sleepAlarm) - - // Disable interrupt - intr.Disable() -} diff --git a/emb/machine/machine_rp2_uart.go b/emb/machine/machine_rp2_uart.go deleted file mode 100644 index 03ebb9d..0000000 --- a/emb/machine/machine_rp2_uart.go +++ /dev/null @@ -1,159 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "runtime/interrupt" -) - -// UART on the RP2040. -type UART struct { - Buffer *RingBuffer - Bus *rp.UART0_Type - Interrupt interrupt.Interrupt -} - -// Configure the UART. -func (uart *UART) Configure(config UARTConfig) error { - initUART(uart) - - // Default baud rate to 115200. - if config.BaudRate == 0 { - config.BaudRate = 115200 - } - - // Use default pins if pins are not set. - if config.TX == 0 && config.RX == 0 { - // use default pins - config.TX = UART_TX_PIN - config.RX = UART_RX_PIN - } - - uart.SetBaudRate(config.BaudRate) - - // default to 8-1-N - uart.SetFormat(8, 1, ParityNone) - - // Enable the UART, both TX and RX - settings := uint32(rp.UART0_UARTCR_UARTEN | - rp.UART0_UARTCR_RXE | - rp.UART0_UARTCR_TXE) - const bits = rp.UART0_UARTCR_UARTEN | rp.UART0_UARTCR_TXE - if config.RTS != 0 { - settings |= rp.UART0_UARTCR_RTSEN - } - if config.CTS != 0 { - settings |= rp.UART0_UARTCR_CTSEN - } - - uart.Bus.UARTCR.SetBits(settings) - - // set GPIO mux to UART for the pins - if config.TX != NoPin { - config.TX.Configure(PinConfig{Mode: PinUART}) - } - if config.RX != NoPin { - config.RX.Configure(PinConfig{Mode: PinUART}) - } - if config.RTS != 0 { - config.RTS.Configure(PinConfig{Mode: PinOutput}) - } - if config.CTS != 0 { - config.CTS.Configure(PinConfig{Mode: PinInput}) - } - - // Enable RX IRQ. - uart.Interrupt.SetPriority(0x80) - uart.Interrupt.Enable() - - // Setup interrupt on receive. - uart.Bus.UARTIMSC.Set(rp.UART0_UARTIMSC_RXIM) - - return nil -} - -// SetBaudRate sets the baudrate to be used for the UART. -func (uart *UART) SetBaudRate(br uint32) { - div := 8 * CPUFrequency() / br - - ibrd := div >> 7 - var fbrd uint32 - - switch { - case ibrd == 0: - ibrd = 1 - fbrd = 0 - case ibrd >= 65535: - ibrd = 65535 - fbrd = 0 - default: - fbrd = ((div & 0x7f) + 1) / 2 - } - - // set PL011 baud divisor registers - uart.Bus.UARTIBRD.Set(ibrd) - uart.Bus.UARTFBRD.Set(fbrd) - - // PL011 needs a (dummy) line control register write. - // See https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_uart/uart.c#L93-L95 - uart.Bus.UARTLCR_H.SetBits(0) -} - -// WriteByte writes a byte of data to the UART. -func (uart *UART) writeByte(c byte) error { - // wait until buffer is not full - for uart.Bus.UARTFR.HasBits(rp.UART0_UARTFR_TXFF) { - gosched() - } - - // write data - uart.Bus.UARTDR.Set(uint32(c)) - return nil -} - -func (uart *UART) flush() { - for uart.Bus.UARTFR.HasBits(rp.UART0_UARTFR_BUSY) { - gosched() - } -} - -// SetFormat for number of data bits, stop bits, and parity for the UART. -func (uart *UART) SetFormat(databits, stopbits uint8, parity UARTParity) error { - var pen, pev uint8 - if parity != ParityNone { - pen = rp.UART0_UARTLCR_H_PEN - } - if parity == ParityEven { - pev = rp.UART0_UARTLCR_H_EPS - } - uart.Bus.UARTLCR_H.SetBits(uint32((databits-5)< usb.EndpointPacketSize { - count = usb.EndpointPacketSize - - sendOnEP0DATADONE.offset = count - sendOnEP0DATADONE.data = data - } else { - sendOnEP0DATADONE.offset = 0 - } - epXdata0[ep] = true - } - - sendViaEPIn(ep, data, count) -} - -func ReceiveUSBControlPacket() ([cdcLineInfoSize]byte, error) { - var b [cdcLineInfoSize]byte - ep := 0 - - for !_usbDPSRAM.EPxBufferControl[ep].Out.HasBits(usbBuf0CtrlFull) { - // TODO: timeout - } - - ctrl := _usbDPSRAM.EPxBufferControl[ep].Out.Get() - _usbDPSRAM.EPxBufferControl[ep].Out.Set(usbBufferLen & usbBuf0CtrlLenMask) - sz := ctrl & usbBuf0CtrlLenMask - - copy(b[:], _usbDPSRAM.EPxBuffer[ep].Buffer0[:sz]) - - _usbDPSRAM.EPxBufferControl[ep].Out.SetBits(usbBuf0CtrlData1Pid) - _usbDPSRAM.EPxBufferControl[ep].Out.SetBits(usbBuf0CtrlAvail) - - return b, nil -} - -func handleEndpointRx(ep uint32) []byte { - ctrl := _usbDPSRAM.EPxBufferControl[ep].Out.Get() - _usbDPSRAM.EPxBufferControl[ep].Out.Set(usbBufferLen & usbBuf0CtrlLenMask) - sz := ctrl & usbBuf0CtrlLenMask - - return _usbDPSRAM.EPxBuffer[ep].Buffer0[:sz] -} - -// AckUsbOutTransfer is called to acknowledge the completion of a USB OUT transfer. -func AckUsbOutTransfer(ep uint32) { - ep = ep & 0x7F - setEPDataPID(ep, !epXdata0[ep]) -} - -// Set the USB endpoint Packet ID to DATA0 or DATA1. -func setEPDataPID(ep uint32, dataOne bool) { - epXdata0[ep] = dataOne - if epXdata0[ep] || ep == 0 { - _usbDPSRAM.EPxBufferControl[ep].Out.SetBits(usbBuf0CtrlData1Pid) - } - - _usbDPSRAM.EPxBufferControl[ep].Out.SetBits(usbBuf0CtrlAvail) -} - -func SendZlp() { - sendUSBPacket(0, []byte{}, 0) -} - -func sendViaEPIn(ep uint32, data []byte, count int) { - // Prepare buffer control register value - val := uint32(count) | usbBuf0CtrlAvail - - // DATA0 or DATA1 - epXdata0[ep&0x7F] = !epXdata0[ep&0x7F] - if !epXdata0[ep&0x7F] { - val |= usbBuf0CtrlData1Pid - } - - // Mark as full - val |= usbBuf0CtrlFull - - copy(_usbDPSRAM.EPxBuffer[ep&0x7F].Buffer0[:], data[:count]) - _usbDPSRAM.EPxBufferControl[ep&0x7F].In.Set(val) -} - -// Set ENDPOINT_HALT/stall status on a USB IN endpoint. -func (dev *USBDevice) SetStallEPIn(ep uint32) { - ep = ep & 0x7F - // Prepare buffer control register value - if ep == 0 { - armEPZeroStall() - } - val := uint32(usbBuf0CtrlFull) - _usbDPSRAM.EPxBufferControl[ep].In.Set(val) - val |= uint32(usbBuf0CtrlStall) - _usbDPSRAM.EPxBufferControl[ep].In.Set(val) -} - -// Set ENDPOINT_HALT/stall status on a USB OUT endpoint. -func (dev *USBDevice) SetStallEPOut(ep uint32) { - ep = ep & 0x7F - if ep == 0 { - panic("SetStallEPOut: EP0 OUT not valid") - } - val := uint32(usbBuf0CtrlStall) - _usbDPSRAM.EPxBufferControl[ep].Out.Set(val) -} - -// Clear the ENDPOINT_HALT/stall on a USB IN endpoint. -func (dev *USBDevice) ClearStallEPIn(ep uint32) { - ep = ep & 0x7F - val := uint32(usbBuf0CtrlStall) - _usbDPSRAM.EPxBufferControl[ep].In.ClearBits(val) - if epXPIDReset[ep] { - // Reset the PID to DATA0 - setEPDataPID(ep, false) - } -} - -// Clear the ENDPOINT_HALT/stall on a USB OUT endpoint. -func (dev *USBDevice) ClearStallEPOut(ep uint32) { - ep = ep & 0x7F - val := uint32(usbBuf0CtrlStall) - _usbDPSRAM.EPxBufferControl[ep].Out.ClearBits(val) - if epXPIDReset[ep] { - // Reset the PID to DATA0 - setEPDataPID(ep, false) - } -} - -type usbDPSRAM struct { - // Note that EPxControl[0] is not EP0Control but 8-byte setup data. - EPxControl [16]usbEndpointControlRegister - - EPxBufferControl [16]usbBufferControlRegister - - EPxBuffer [16]usbBuffer -} - -type usbEndpointControlRegister struct { - In volatile.Register32 - Out volatile.Register32 -} -type usbBufferControlRegister struct { - In volatile.Register32 - Out volatile.Register32 -} - -type usbBuffer struct { - Buffer0 [usbBufferLen]byte - Buffer1 [usbBufferLen]byte -} - -var ( - _usbDPSRAM = (*usbDPSRAM)(unsafe.Pointer(uintptr(0x50100000))) - epXdata0 [16]bool - epXPIDReset [16]bool - setupBytes [8]byte -) - -func (d *usbDPSRAM) setupBytes() []byte { - - data := d.EPxControl[usb.CONTROL_ENDPOINT].In.Get() - setupBytes[0] = byte(data) - setupBytes[1] = byte(data >> 8) - setupBytes[2] = byte(data >> 16) - setupBytes[3] = byte(data >> 24) - - data = d.EPxControl[usb.CONTROL_ENDPOINT].Out.Get() - setupBytes[4] = byte(data) - setupBytes[5] = byte(data >> 8) - setupBytes[6] = byte(data >> 16) - setupBytes[7] = byte(data >> 24) - - return setupBytes[:] -} - -func (d *usbDPSRAM) clear() { - for i := 0; i < len(d.EPxControl); i++ { - d.EPxControl[i].In.Set(0) - d.EPxControl[i].Out.Set(0) - d.EPxBufferControl[i].In.Set(0) - d.EPxBufferControl[i].Out.Set(0) - } -} - -const ( - // DPRAM : Endpoint control register - usbEpControlEnable = 0x80000000 - usbEpControlDoubleBuffered = 0x40000000 - usbEpControlInterruptPerBuff = 0x20000000 - usbEpControlInterruptPerDoubleBuff = 0x10000000 - usbEpControlEndpointType = 0x0c000000 - usbEpControlInterruptOnStall = 0x00020000 - usbEpControlInterruptOnNak = 0x00010000 - usbEpControlBufferAddress = 0x0000ffff - - usbEpControlEndpointTypeControl = 0x00000000 - usbEpControlEndpointTypeISO = 0x04000000 - usbEpControlEndpointTypeBulk = 0x08000000 - usbEpControlEndpointTypeInterrupt = 0x0c000000 - - // Endpoint buffer control bits - usbBuf1CtrlFull = 0x80000000 - usbBuf1CtrlLast = 0x40000000 - usbBuf1CtrlData0Pid = 0x20000000 - usbBuf1CtrlData1Pid = 0x00000000 - usbBuf1CtrlSel = 0x10000000 - usbBuf1CtrlStall = 0x08000000 - usbBuf1CtrlAvail = 0x04000000 - usbBuf1CtrlLenMask = 0x03FF0000 - usbBuf0CtrlFull = 0x00008000 - usbBuf0CtrlLast = 0x00004000 - usbBuf0CtrlData0Pid = 0x00000000 - usbBuf0CtrlData1Pid = 0x00002000 - usbBuf0CtrlSel = 0x00001000 - usbBuf0CtrlStall = 0x00000800 - usbBuf0CtrlAvail = 0x00000400 - usbBuf0CtrlLenMask = 0x000003FF - - usbBufferLen = 64 -) diff --git a/emb/machine/machine_rp2_watchdog.go b/emb/machine/machine_rp2_watchdog.go deleted file mode 100644 index f776c5c..0000000 --- a/emb/machine/machine_rp2_watchdog.go +++ /dev/null @@ -1,62 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" -) - -// Watchdog provides access to the hardware watchdog available -// in the RP2040. -var Watchdog = &watchdogImpl{} - -const ( - // WatchdogMaxTimeout in milliseconds (approx 8.3s). - // - // Nominal 1us per watchdog tick, 24-bit counter, - // but due to errata two ticks consumed per 1us. - // See: Errata RP2040-E1 - WatchdogMaxTimeout = (rp.WATCHDOG_LOAD_LOAD_Msk / 1000) / 2 -) - -type watchdogImpl struct { - // The value to reset the counter to on each Update - loadValue uint32 -} - -// Configure the watchdog. -// -// This method should not be called after the watchdog is started and on -// some platforms attempting to reconfigure after starting the watchdog -// is explicitly forbidden / will not work. -func (wd *watchdogImpl) Configure(config WatchdogConfig) error { - // x2 due to errata RP2040-E1 - wd.loadValue = config.TimeoutMillis * 1000 * 2 - if wd.loadValue > rp.WATCHDOG_LOAD_LOAD_Msk { - wd.loadValue = rp.WATCHDOG_LOAD_LOAD_Msk - } - - rp.WATCHDOG.CTRL.ClearBits(rp.WATCHDOG_CTRL_ENABLE) - - // Reset everything apart from ROSC and XOSC - rp.PSM.WDSEL.Set(0x0001ffff &^ (rp.PSM_WDSEL_ROSC | rp.PSM_WDSEL_XOSC)) - - // Pause watchdog during debug - rp.WATCHDOG.CTRL.SetBits(rp.WATCHDOG_CTRL_PAUSE_DBG0 | rp.WATCHDOG_CTRL_PAUSE_DBG1 | rp.WATCHDOG_CTRL_PAUSE_JTAG) - - // Load initial counter - rp.WATCHDOG.LOAD.Set(wd.loadValue) - - return nil -} - -// Starts the watchdog. -func (wd *watchdogImpl) Start() error { - rp.WATCHDOG.CTRL.SetBits(rp.WATCHDOG_CTRL_ENABLE) - return nil -} - -// Update the watchdog, indicating that the app is healthy. -func (wd *watchdogImpl) Update() { - rp.WATCHDOG.LOAD.Set(wd.loadValue) -} diff --git a/emb/machine/machine_rp2_xosc.go b/emb/machine/machine_rp2_xosc.go deleted file mode 100644 index c9ce583..0000000 --- a/emb/machine/machine_rp2_xosc.go +++ /dev/null @@ -1,47 +0,0 @@ -//go:build rp2040 || rp2350 - -package machine - -import ( - "device/rp" - "runtime/volatile" - "unsafe" -) - -// On some boards, the XOSC can take longer than usual to stabilize. On such -// boards, this is needed to avoid a hard fault on boot/reset. Refer to -// PICO_XOSC_STARTUP_DELAY_MULTIPLIER in the Pico SDK for additional details. -const XOSC_STARTUP_DELAY_MULTIPLIER = 64 - -type xoscType struct { - ctrl volatile.Register32 - status volatile.Register32 - dormant volatile.Register32 - startup volatile.Register32 - reserved [3 - 3*rp2350ExtraReg]volatile.Register32 - count volatile.Register32 -} - -var xosc = (*xoscType)(unsafe.Pointer(rp.XOSC)) - -// init initializes the crystal oscillator system. -// -// This function will block until the crystal oscillator has stabilised. -func (osc *xoscType) init() { - // Assumes 1-15 MHz input - if xoscFreq > 15 { - panic("xosc frequency cannot be greater than 15MHz") - } - osc.ctrl.Set(rp.XOSC_CTRL_FREQ_RANGE_1_15MHZ) - - // Set xosc startup delay - delay := (((xoscFreq * MHz) / 1000) + 128) / 256 * XOSC_STARTUP_DELAY_MULTIPLIER - osc.startup.Set(uint32(delay)) - - // Set the enable bit now that we have set freq range and startup delay - osc.ctrl.SetBits(rp.XOSC_CTRL_ENABLE_ENABLE << rp.XOSC_CTRL_ENABLE_Pos) - - // Wait for xosc to be stable - for !osc.status.HasBits(rp.XOSC_STATUS_STABLE) { - } -} diff --git a/emb/machine/machine_stm32.go b/emb/machine/machine_stm32.go deleted file mode 100644 index 1edaa2c..0000000 --- a/emb/machine/machine_stm32.go +++ /dev/null @@ -1,104 +0,0 @@ -//go:build stm32 - -package machine - -import ( - "device/stm32" - - "runtime/volatile" - "unsafe" -) - -const deviceName = stm32.Device - -// Peripheral abstraction layer for the stm32. - -const ( - portA Pin = iota * 16 - portB - portC - portD - portE - portF - portG - portH - portI - portJ - portK -) - -// Peripheral operations sequence: -// 1. Enable the clock to the alternate function. -// 2. Enable clock to corresponding GPIO -// 3. Attach the alternate function. -// 4. Configure the input-output port and pins (of the corresponding GPIOx) to match the AF . -// 5. If desired enable the nested vector interrupt control to generate interrupts. -// 6. Program the AF/peripheral for the required configuration (eg baud rate for a USART) . - -// Given that the stm32 family has the AF and GPIO on different registers based on the chip, -// use the main function here for configuring, and use hooks in the more specific chip -// definition files -// Also, the stm32f1xx series handles things differently from the stm32f0/2/3/4 - -// ---------- General pin operations ---------- -type PinChange uint8 - -const ( - PinRising PinChange = 1 << iota - PinFalling - PinToggle = PinRising | PinFalling -) - -// Set the pin to high or low. -// Warning: only use this on an output pin! -func (p Pin) Set(high bool) { - port := p.getPort() - pin := uint8(p) % 16 - if high { - port.BSRR.Set(1 << pin) - } else { - port.BSRR.Set(1 << (pin + 16)) - } -} - -// Get returns the current value of a GPIO pin when the pin is configured as an -// input or as an output. -func (p Pin) Get() bool { - port := p.getPort() - pin := uint8(p) % 16 - val := port.IDR.Get() & (1 << pin) - return (val > 0) -} - -// PortMaskSet returns the register and mask to enable a given GPIO pin. This -// can be used to implement bit-banged drivers. -func (p Pin) PortMaskSet() (*uint32, uint32) { - port := p.getPort() - pin := uint8(p) % 16 - return &port.BSRR.Reg, 1 << pin -} - -// PortMaskClear returns the register and mask to disable a given port. This can -// be used to implement bit-banged drivers. -func (p Pin) PortMaskClear() (*uint32, uint32) { - port := p.getPort() - pin := uint8(p) % 16 - return &port.BSRR.Reg, 1 << (pin + 16) -} - -var deviceID [12]byte - -// DeviceID returns an identifier that is unique within -// a particular chipset. -// -// The identity is one burnt into the MCU itself. -// -// The length of the device ID for STM32 is 12 bytes (96 bits). -func DeviceID() []byte { - for i := 0; i < len(deviceID); i++ { - word := (*volatile.Register32)(unsafe.Pointer(deviceIDAddr[i/4])).Get() - deviceID[i] = byte(word >> ((i % 4) * 8)) - } - - return deviceID[:] -} diff --git a/emb/machine/machine_stm32_adc_f1.go b/emb/machine/machine_stm32_adc_f1.go deleted file mode 100644 index 7076bdd..0000000 --- a/emb/machine/machine_stm32_adc_f1.go +++ /dev/null @@ -1,90 +0,0 @@ -//go:build stm32f103 - -package machine - -import ( - "device/stm32" - "unsafe" -) - -const ( - Cycles_1_5 = 0x0 - Cycles_7_5 = 0x1 - Cycles_13_5 = 0x2 - Cycles_28_5 = 0x3 - Cycles_41_5 = 0x4 - Cycles_55_5 = 0x5 - Cycles_71_5 = 0x6 - Cycles_239_5 = 0x7 -) - -// InitADC initializes the registers needed for ADC1. -func InitADC() { - // Enable ADC clock - enableAltFuncClock(unsafe.Pointer(stm32.ADC1)) - - // enable - stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_ADON | stm32.ADC_CR2_ALIGN) - - return -} - -// Configure configures an ADC pin to be able to read analog data. -func (a ADC) Configure(ADCConfig) { - a.Pin.Configure(PinConfig{Mode: PinInputModeAnalog}) - - // set sample time - ch := a.getChannel() - if ch > 9 { - stm32.ADC1.SMPR1.SetBits(Cycles_28_5 << (ch - 10) * stm32.ADC_SMPR1_SMP11_Pos) - } else { - stm32.ADC1.SMPR2.SetBits(Cycles_28_5 << (ch * stm32.ADC_SMPR2_SMP1_Pos)) - } - - return -} - -// Get returns the current value of a ADC pin in the range 0..0xffff. -// TODO: DMA based implementation. -func (a ADC) Get() uint16 { - // set rank - ch := uint32(a.getChannel()) - stm32.ADC1.SetSQR3_SQ1(ch) - - // start conversion - stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_ADON) - - // wait for conversion to complete - for !stm32.ADC1.SR.HasBits(stm32.ADC_SR_EOC) { - } - - // read result as 16 bit value - return uint16(stm32.ADC1.DR.Get()) -} - -func (a ADC) getChannel() uint8 { - switch a.Pin { - case PA0: - return 0 - case PA1: - return 1 - case PA2: - return 2 - case PA3: - return 3 - case PA4: - return 4 - case PA5: - return 5 - case PA6: - return 6 - case PA7: - return 7 - case PB0: - return 8 - case PB1: - return 9 - } - - return 0 -} diff --git a/emb/machine/machine_stm32_adc_f4.go b/emb/machine/machine_stm32_adc_f4.go deleted file mode 100644 index df4984c..0000000 --- a/emb/machine/machine_stm32_adc_f4.go +++ /dev/null @@ -1,114 +0,0 @@ -//go:build stm32f4 - -package machine - -import ( - "device/stm32" - "unsafe" -) - -// InitADC initializes the registers needed for ADC1. -func InitADC() { - // Enable ADC clock - enableAltFuncClock(unsafe.Pointer(stm32.ADC1)) - - // stop scan, and clear scan resolution - stm32.ADC1.CR1.ClearBits(stm32.ADC_CR1_SCAN | stm32.ADC_CR1_RES_Msk) - - // set conversion mode and resolution - stm32.ADC1.CR1.SetBits(stm32.ADC_CR1_RES_TwelveBit) - - // clear CONT, ALIGN, EXTEN and EXTSEL bits from CR2 - stm32.ADC1.CR2.ClearBits(stm32.ADC_CR2_CONT | stm32.ADC_CR2_ALIGN | stm32.ADC_CR2_EXTEN_Msk | stm32.ADC_CR2_EXTSEL_Msk) - - // set CONT, ALIGN, EXTEN and EXTSEL bits from CR2 - stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_CONT_Single | stm32.ADC_CR2_ALIGN_Right) - - stm32.ADC1.SQR1.ClearBits(stm32.ADC_SQR1_L_Msk) - stm32.ADC1.SQR1.SetBits(2 << stm32.ADC_SQR1_L_Pos) // 2 means 3 conversions - - // enable - stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_ADON) - - return -} - -// Configure configures an ADC pin to be able to read analog data. -func (a ADC) Configure(ADCConfig) { - a.Pin.ConfigureAltFunc(PinConfig{Mode: PinInputAnalog}, 0) - - // set sample time - ch := a.getChannel() - if ch > 9 { - stm32.ADC1.SMPR1.SetBits(stm32.ADC_SMPR1_SMP11_Cycles84 << (ch - 10) * stm32.ADC_SMPR1_SMP11_Pos) - } else { - stm32.ADC1.SMPR2.SetBits(stm32.ADC_SMPR2_SMP1_Cycles84 << (ch * stm32.ADC_SMPR2_SMP1_Pos)) - } - - return -} - -// Get returns the current value of a ADC pin in the range 0..0xffff. -// TODO: DMA based implementation. -func (a ADC) Get() uint16 { - // set rank - ch := uint32(a.getChannel()) - stm32.ADC1.SQR3.SetBits(ch) - - // start conversion - stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_SWSTART) - - // wait for conversion to complete - for !stm32.ADC1.SR.HasBits(stm32.ADC_SR_EOC) { - } - - // read 12-bit result as 16 bit value - result := uint16(stm32.ADC1.DR.Get()) << 4 - - // clear flag - stm32.ADC1.SR.ClearBits(stm32.ADC_SR_EOC) - - // clear rank - stm32.ADC1.SQR3.ClearBits(ch) - - return result -} - -func (a ADC) getChannel() uint8 { - switch a.Pin { - case PA0: - return 0 - case PA1: - return 1 - case PA2: - return 2 - case PA3: - return 3 - case PA4: - return 4 - case PA5: - return 5 - case PA6: - return 6 - case PA7: - return 7 - case PB0: - return 8 - case PB1: - return 9 - case PC0: - return 10 - case PC1: - return 11 - case PC2: - return 12 - case PC3: - return 13 - case PC4: - return 14 - case PC5: - return 15 - } - - return 0 -} diff --git a/emb/machine/machine_stm32_exti_afio.go b/emb/machine/machine_stm32_exti_afio.go deleted file mode 100644 index 89a9506..0000000 --- a/emb/machine/machine_stm32_exti_afio.go +++ /dev/null @@ -1,27 +0,0 @@ -//go:build stm32f1 - -package machine - -import ( - "device/stm32" - "runtime/volatile" -) - -func getEXTIConfigRegister(pin uint8) *volatile.Register32 { - switch (pin & 0xf) / 4 { - case 0: - return &stm32.AFIO.EXTICR1 - case 1: - return &stm32.AFIO.EXTICR2 - case 2: - return &stm32.AFIO.EXTICR3 - case 3: - return &stm32.AFIO.EXTICR4 - } - return nil -} - -func enableEXTIConfigRegisters() { - // Enable AFIO - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_AFIOEN) -} diff --git a/emb/machine/machine_stm32_exti_exti.go b/emb/machine/machine_stm32_exti_exti.go deleted file mode 100644 index 874a043..0000000 --- a/emb/machine/machine_stm32_exti_exti.go +++ /dev/null @@ -1,26 +0,0 @@ -//go:build stm32l5 - -package machine - -import ( - "device/stm32" - "runtime/volatile" -) - -func getEXTIConfigRegister(pin uint8) *volatile.Register32 { - switch (pin & 0xf) / 4 { - case 0: - return &stm32.EXTI.EXTICR1 - case 1: - return &stm32.EXTI.EXTICR2 - case 2: - return &stm32.EXTI.EXTICR3 - case 3: - return &stm32.EXTI.EXTICR4 - } - return nil -} - -func enableEXTIConfigRegisters() { - // No-op -} diff --git a/emb/machine/machine_stm32_exti_syscfg.go b/emb/machine/machine_stm32_exti_syscfg.go deleted file mode 100644 index f7c91f8..0000000 --- a/emb/machine/machine_stm32_exti_syscfg.go +++ /dev/null @@ -1,27 +0,0 @@ -//go:build stm32 && !stm32f1 && !stm32l5 && !stm32wlx - -package machine - -import ( - "device/stm32" - "runtime/volatile" -) - -func getEXTIConfigRegister(pin uint8) *volatile.Register32 { - switch (pin & 0xf) / 4 { - case 0: - return &stm32.SYSCFG.EXTICR1 - case 1: - return &stm32.SYSCFG.EXTICR2 - case 2: - return &stm32.SYSCFG.EXTICR3 - case 3: - return &stm32.SYSCFG.EXTICR4 - } - return nil -} - -func enableEXTIConfigRegisters() { - // Enable SYSCFG - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) -} diff --git a/emb/machine/machine_stm32_exti_syscfg_noenable.go b/emb/machine/machine_stm32_exti_syscfg_noenable.go deleted file mode 100644 index 85f47fa..0000000 --- a/emb/machine/machine_stm32_exti_syscfg_noenable.go +++ /dev/null @@ -1,26 +0,0 @@ -//go:build stm32wlx - -package machine - -import ( - "device/stm32" - "runtime/volatile" -) - -func getEXTIConfigRegister(pin uint8) *volatile.Register32 { - switch (pin & 0xf) / 4 { - case 0: - return &stm32.SYSCFG.EXTICR1 - case 1: - return &stm32.SYSCFG.EXTICR2 - case 2: - return &stm32.SYSCFG.EXTICR3 - case 3: - return &stm32.SYSCFG.EXTICR4 - } - return nil -} - -func enableEXTIConfigRegisters() { - // No registers to enable -} diff --git a/emb/machine/machine_stm32_flash.go b/emb/machine/machine_stm32_flash.go deleted file mode 100644 index 280dc89..0000000 --- a/emb/machine/machine_stm32_flash.go +++ /dev/null @@ -1,115 +0,0 @@ -//go:build stm32f4 || stm32l4 || stm32wlx - -package machine - -import ( - "device/stm32" - - "unsafe" -) - -// compile-time check for ensuring we fulfill BlockDevice interface -var _ BlockDevice = flashBlockDevice{} - -var Flash flashBlockDevice - -type flashBlockDevice struct { -} - -// ReadAt reads the given number of bytes from the block device. -func (f flashBlockDevice) ReadAt(p []byte, off int64) (n int, err error) { - if FlashDataStart()+uintptr(off)+uintptr(len(p)) > FlashDataEnd() { - return 0, errFlashCannotReadPastEOF - } - - data := unsafe.Slice((*byte)(unsafe.Pointer(FlashDataStart()+uintptr(off))), len(p)) - copy(p, data) - - return len(p), nil -} - -// WriteAt writes the given number of bytes to the block device. -// Only double-word (64 bits) length data can be programmed. See rm0461 page 78. -// If the length of p is not long enough it will be padded with 0xFF bytes. -// This method assumes that the destination is already erased. -func (f flashBlockDevice) WriteAt(p []byte, off int64) (n int, err error) { - if FlashDataStart()+uintptr(off)+uintptr(len(p)) > FlashDataEnd() { - return 0, errFlashCannotWritePastEOF - } - - unlockFlash() - defer lockFlash() - - p = flashPad(p, int(f.WriteBlockSize())) - return writeFlashData(FlashDataStart()+uintptr(off), p) -} - -// Size returns the number of bytes in this block device. -func (f flashBlockDevice) Size() int64 { - return int64(FlashDataEnd() - FlashDataStart()) -} - -// WriteBlockSize returns the block size in which data can be written to -// memory. It can be used by a client to optimize writes, non-aligned writes -// should always work correctly. -func (f flashBlockDevice) WriteBlockSize() int64 { - return writeBlockSize -} - -func eraseBlockSize() int64 { - return eraseBlockSizeValue -} - -// EraseBlockSize returns the smallest erasable area on this particular chip -// in bytes. This is used for the block size in EraseBlocks. -// It must be a power of two, and may be as small as 1. A typical size is 4096. -// TODO: correctly handle processors that have differently sized blocks -// in different areas of memory like the STM32F40x and STM32F1x. -func (f flashBlockDevice) EraseBlockSize() int64 { - return eraseBlockSize() -} - -// EraseBlocks erases the given number of blocks. An implementation may -// transparently coalesce ranges of blocks into larger bundles if the chip -// supports this. The start and len parameters are in block numbers, use -// EraseBlockSize to map addresses to blocks. -// Note that block 0 should map to the address of FlashDataStart(). -func (f flashBlockDevice) EraseBlocks(start, len int64) error { - var address uintptr = uintptr(start*f.EraseBlockSize()) + FlashDataStart() - blk := int64(address-uintptr(memoryStart)) / f.EraseBlockSize() - - unlockFlash() - defer lockFlash() - - for i := blk; i < blk+len; i++ { - if err := eraseBlock(uint32(i)); err != nil { - return err - } - } - - return nil -} - -const memoryStart = 0x08000000 - -func unlockFlash() { - // keys as described rm0461 page 76 - var fkey1 uint32 = 0x45670123 - var fkey2 uint32 = 0xCDEF89AB - - // Wait for the flash memory not to be busy - for stm32.FLASH.GetSR_BSY() != 0 { - } - - // Check if the controller is unlocked already - if stm32.FLASH.GetCR_LOCK() != 0 { - // Write the first key - stm32.FLASH.SetKEYR(fkey1) - // Write the second key - stm32.FLASH.SetKEYR(fkey2) - } -} - -func lockFlash() { - stm32.FLASH.SetCR_LOCK(1) -} diff --git a/emb/machine/machine_stm32_gpio_reva.go b/emb/machine/machine_stm32_gpio_reva.go deleted file mode 100644 index 2fb5a03..0000000 --- a/emb/machine/machine_stm32_gpio_reva.go +++ /dev/null @@ -1,92 +0,0 @@ -//go:build stm32 && !stm32l4 && !stm32l5 && !stm32wlx - -package machine - -import ( - "device/stm32" -) - -// This variant of the GPIO input interrupt logic is for -// chips with a smaller number of interrupt channels -// (that fits in a single register). - -// -// STM32 allows one interrupt source per pin number, with -// the same pin number in different ports sharing a single -// interrupt source (so PA0, PB0, PC0 all share). Only a -// single physical pin can be connected to each interrupt -// line. -// -// To call interrupt callbacks, we record here for each -// pin number the callback and the actual associated pin. -// - -// Callbacks for pin interrupt events -var pinCallbacks [16]func(Pin) - -// The pin currently associated with interrupt callback -// for a given slot. -var interruptPins [16]Pin - -// SetInterrupt sets an interrupt to be executed when a particular pin changes -// state. The pin should already be configured as an input, including a pull up -// or down if no external pull is provided. -// -// This call will replace a previously set callback on this pin. You can pass a -// nil func to unset the pin change interrupt. If you do so, the change -// parameter is ignored and can be set to any value (such as 0). -func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error { - port := uint32(uint8(p) / 16) - pin := uint8(p) % 16 - - enableEXTIConfigRegisters() - - if callback == nil { - stm32.EXTI.IMR.ClearBits(1 << pin) - pinCallbacks[pin] = nil - return nil - } - - if pinCallbacks[pin] != nil { - // The pin was already configured. - // To properly re-configure a pin, unset it first and set a new - // configuration. - return ErrNoPinChangeChannel - } - - // Set the callback now (before the interrupt is enabled) to avoid - // possible race condition - pinCallbacks[pin] = callback - interruptPins[pin] = p - - crReg := getEXTIConfigRegister(pin) - shift := (pin & 0x3) * 4 - crReg.ReplaceBits(port, 0xf, shift) - - if (change & PinRising) != 0 { - stm32.EXTI.RTSR.SetBits(1 << pin) - } - if (change & PinFalling) != 0 { - stm32.EXTI.FTSR.SetBits(1 << pin) - } - stm32.EXTI.IMR.SetBits(1 << pin) - - intr := p.registerInterrupt() - intr.SetPriority(0) - intr.Enable() - - return nil -} - -func handlePinInterrupt(pin uint8) { - if stm32.EXTI.PR.HasBits(1 << pin) { - // Writing 1 to the pending register clears the - // pending flag for that bit - stm32.EXTI.PR.Set(1 << pin) - - callback := pinCallbacks[pin] - if callback != nil { - callback(interruptPins[pin]) - } - } -} diff --git a/emb/machine/machine_stm32_gpio_revb.go b/emb/machine/machine_stm32_gpio_revb.go deleted file mode 100644 index 49094c7..0000000 --- a/emb/machine/machine_stm32_gpio_revb.go +++ /dev/null @@ -1,79 +0,0 @@ -//go:build stm32l4 || stm32l5 - -package machine - -import ( - "device/stm32" -) - -// This variant of the GPIO input interrupt logic is for -// chips with a larger number of interrupt channels (more -// than fits in a single register). - -// -// STM32 allows one interrupt source per pin number, with -// the same pin number in different ports sharing a single -// interrupt source (so PA0, PB0, PC0 all share). Only a -// single physical pin can be connected to each interrupt -// line. -// -// To call interrupt callbacks, we record here for each -// pin number the callback and the actual associated pin. -// - -// Callbacks for pin interrupt events -var pinCallbacks [16]func(Pin) - -// The pin currently associated with interrupt callback -// for a given slot. -var interruptPins [16]Pin - -// SetInterrupt sets an interrupt to be executed when a particular pin changes -// state. The pin should already be configured as an input, including a pull up -// or down if no external pull is provided. -// -// This call will replace a previously set callback on this pin. You can pass a -// nil func to unset the pin change interrupt. If you do so, the change -// parameter is ignored and can be set to any value (such as 0). -func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error { - port := uint32(uint8(p) / 16) - pin := uint8(p) % 16 - - enableEXTIConfigRegisters() - - if callback == nil { - stm32.EXTI.IMR1.ClearBits(1 << pin) - pinCallbacks[pin] = nil - return nil - } - - if pinCallbacks[pin] != nil { - // The pin was already configured. - // To properly re-configure a pin, unset it first and set a new - // configuration. - return ErrNoPinChangeChannel - } - - // Set the callback now (before the interrupt is enabled) to avoid - // possible race condition - pinCallbacks[pin] = callback - interruptPins[pin] = p - - crReg := getEXTIConfigRegister(pin) - shift := (pin & 0x3) * 4 - crReg.ReplaceBits(port, 0xf, shift) - - if (change & PinRising) != 0 { - stm32.EXTI.RTSR1.SetBits(1 << pin) - } - if (change & PinFalling) != 0 { - stm32.EXTI.FTSR1.SetBits(1 << pin) - } - stm32.EXTI.IMR1.SetBits(1 << pin) - - intr := p.registerInterrupt() - intr.SetPriority(0) - intr.Enable() - - return nil -} diff --git a/emb/machine/machine_stm32_gpio_revb_mp.go b/emb/machine/machine_stm32_gpio_revb_mp.go deleted file mode 100644 index 2124b16..0000000 --- a/emb/machine/machine_stm32_gpio_revb_mp.go +++ /dev/null @@ -1,86 +0,0 @@ -//go:build stm32wlx - -package machine - -import ( - "device/stm32" -) - -// -// This variant of the GPIO input interrupt logic is for -// multi-core chips with a larger number of interrupt -// channels (more than fits in a single register). -// -// This logic is currently used by the single-core stm32wle5 -// due to a patch in stm32-rs project that has renamed the -// registers to match the dual-core names. This renaming is -// being discussed and may change in future. -// - -// -// STM32 allows one interrupt source per pin number, with -// the same pin number in different ports sharing a single -// interrupt source (so PA0, PB0, PC0 all share). Only a -// single physical pin can be connected to each interrupt -// line. -// -// To call interrupt callbacks, we record here for each -// pin number the callback and the actual associated pin. -// - -// Callbacks for pin interrupt events -var pinCallbacks [16]func(Pin) - -// The pin currently associated with interrupt callback -// for a given slot. -var interruptPins [16]Pin - -// SetInterrupt sets an interrupt to be executed when a particular pin changes -// state. The pin should already be configured as an input, including a pull up -// or down if no external pull is provided. -// -// This call will replace a previously set callback on this pin. You can pass a -// nil func to unset the pin change interrupt. If you do so, the change -// parameter is ignored and can be set to any value (such as 0). -func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error { - port := uint32(uint8(p) / 16) - pin := uint8(p) % 16 - - enableEXTIConfigRegisters() - - if callback == nil { - stm32.EXTI.C1IMR1.ClearBits(1 << pin) - pinCallbacks[pin] = nil - return nil - } - - if pinCallbacks[pin] != nil { - // The pin was already configured. - // To properly re-configure a pin, unset it first and set a new - // configuration. - return ErrNoPinChangeChannel - } - - // Set the callback now (before the interrupt is enabled) to avoid - // possible race condition - pinCallbacks[pin] = callback - interruptPins[pin] = p - - crReg := getEXTIConfigRegister(pin) - shift := (pin & 0x3) * 4 - crReg.ReplaceBits(port, 0xf, shift) - - if (change & PinRising) != 0 { - stm32.EXTI.RTSR1.SetBits(1 << pin) - } - if (change & PinFalling) != 0 { - stm32.EXTI.FTSR1.SetBits(1 << pin) - } - stm32.EXTI.C1IMR1.SetBits(1 << pin) - - intr := p.registerInterrupt() - intr.SetPriority(0) - intr.Enable() - - return nil -} diff --git a/emb/machine/machine_stm32_i2c_reva.go b/emb/machine/machine_stm32_i2c_reva.go deleted file mode 100644 index 1e4fd28..0000000 --- a/emb/machine/machine_stm32_i2c_reva.go +++ /dev/null @@ -1,436 +0,0 @@ -//go:build stm32f4 || stm32f1 - -package machine - -// I2C implementation for 'older' STM32 MCUs, including the F1 and F4 series -// of MCUs. - -import ( - "device/stm32" - "unsafe" -) - -const ( - flagOVR = 0x00010800 - flagAF = 0x00010400 - flagARLO = 0x00010200 - flagBERR = 0x00010100 - flagTXE = 0x00010080 - flagRXNE = 0x00010040 - flagSTOPF = 0x00010010 - flagADD10 = 0x00010008 - flagBTF = 0x00010004 - flagADDR = 0x00010002 - flagSB = 0x00010001 - flagDUALF = 0x00100080 - flagGENCALL = 0x00100010 - flagTRA = 0x00100004 - flagBUSY = 0x00100002 - flagMSL = 0x00100001 -) - -func (i2c *I2C) hasFlag(flag uint32) bool { - const mask = 0x0000FFFF - if uint8(flag>>16) == 1 { - return i2c.Bus.SR1.HasBits(flag & mask) - } else { - return i2c.Bus.SR2.HasBits(flag & mask) - } -} - -func (i2c *I2C) clearFlag(flag uint32) { - const mask = 0x0000FFFF - i2c.Bus.SR1.Set(^(flag & mask)) -} - -// clearFlagADDR reads both status registers to clear any pending ADDR flags. -func (i2c *I2C) clearFlagADDR() { - i2c.Bus.SR1.Get() - i2c.Bus.SR2.Get() -} - -func (i2c *I2C) waitForFlag(flag uint32, set bool) bool { - const tryMax = 10000 - hasFlag := false - for i := 0; !hasFlag && i < tryMax; i++ { - hasFlag = i2c.hasFlag(flag) == set - } - return hasFlag -} - -func (i2c *I2C) waitForFlagOrError(flag uint32, set bool) bool { - const tryMax = 10000 - hasFlag := false - for i := 0; !hasFlag && i < tryMax; i++ { - if hasFlag = i2c.hasFlag(flag) == set; !hasFlag { - // check for ACK failure - if i2c.hasFlag(flagAF) { - // generate stop condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_STOP) - // clear pending flags - i2c.clearFlag(flagAF) - return false - } else if i2c.hasFlag(flagSTOPF) { - // clear stop flag - i2c.clearFlag(flagSTOPF) - return false - } - } - } - return hasFlag -} - -type transferOption uint32 - -const ( - frameFirst = 0x00000001 - frameFirstAndNext = 0x00000002 - frameNext = 0x00000004 - frameFirstAndLast = 0x00000008 - frameLastNoStop = 0x00000010 - frameLast = 0x00000020 - frameNoOption = 0xFFFF0000 -) - -// I2C fast mode (Fm) duty cycle -const ( - DutyCycle2 = 0 - DutyCycle16x9 = 1 -) - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 - SCL Pin - SDA Pin - DutyCycle uint8 -} - -// Configure is intended to setup the STM32 I2C interface. -func (i2c *I2C) Configure(config I2CConfig) error { - - // The following is the required sequence in controller mode. - // 1. Program the peripheral input clock in I2C_CR2 Register in order to - // generate correct timings - // 2. Configure the clock control registers - // 3. Configure the rise time register - // 4. Program the I2C_CR1 register to enable the peripheral - // 5. Set the START bit in the I2C_CR1 register to generate a Start condition - - // disable I2C interface before any configuration changes - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_PE) - - // reset I2C bus - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_SWRST) - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_SWRST) - - // enable clock for I2C - enableAltFuncClock(unsafe.Pointer(i2c.Bus)) - - // init pins - if config.SCL == 0 && config.SDA == 0 { - config.SCL = I2C0_SCL_PIN - config.SDA = I2C0_SDA_PIN - } - i2c.configurePins(config) - - // default to 100 kHz (Sm, standard mode) if no frequency is set - if config.Frequency == 0 { - config.Frequency = 100 * KHz - } - - // configure I2C input clock - i2c.Bus.CR2.SetBits(i2c.getFreqRange(config)) - - // configure rise time - i2c.Bus.TRISE.Set(i2c.getRiseTime(config)) - - // configure clock control - i2c.Bus.CCR.Set(i2c.getSpeed(config)) - - // disable GeneralCall and NoStretch modes - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_ENGC | stm32.I2C_CR1_NOSTRETCH) - - // enable I2C interface - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_PE) - - return nil -} - -// SetBaudRate sets the communication speed for I2C. -func (i2c *I2C) SetBaudRate(br uint32) error { - // TODO: implement - return errI2CNotImplemented -} - -func (i2c *I2C) Tx(addr uint16, w, r []byte) error { - - if err := i2c.controllerTransmit(addr, w); nil != err { - return err - } - - if len(r) > 0 { - if err := i2c.controllerReceive(addr, r); nil != err { - return err - } - } - - return nil -} - -func (i2c *I2C) controllerTransmit(addr uint16, w []byte) error { - - if !i2c.waitForFlag(flagBUSY, false) { - return errI2CBusReadyTimeout - } - - // disable POS - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_POS) - - pos := 0 - rem := len(w) - - // send peripheral address - if err := i2c.controllerRequestWrite(addr, frameNoOption); nil != err { - return err - } - - // clear ADDR flag - i2c.clearFlagADDR() - - for rem > 0 { - // wait for TXE flag set - if !i2c.waitForFlagOrError(flagTXE, true) { - return errI2CAckExpected - } - - // write data to DR - i2c.Bus.DR.Set(uint32(w[pos])) - // update counters - pos++ - rem-- - - if i2c.hasFlag(flagBTF) && rem != 0 { - // write data to DR - i2c.Bus.DR.Set(uint32(w[pos])) - // update counters - pos++ - rem-- - } - - // wait for transfer finished flag BTF set - if !i2c.waitForFlagOrError(flagBTF, true) { - return errI2CWriteTimeout - } - } - - // generate stop condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_STOP) - - return nil -} - -func (i2c *I2C) controllerRequestWrite(addr uint16, option transferOption) error { - - if frameFirstAndLast == option || frameFirst == option || frameNoOption == option { - // generate start condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_START) - } else if false /* (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) */ { - // generate restart condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_START) - } - - // ensure start bit is set - if !i2c.waitForFlag(flagSB, true) { - return errI2CSignalStartTimeout - } - - // send peripheral address - i2c.Bus.DR.Set(uint32(addr) << 1) - - // wait for address ACK from peripheral - if !i2c.waitForFlagOrError(flagADDR, true) { - return errI2CSignalStartTimeout - } - - return nil -} - -func (i2c *I2C) controllerReceive(addr uint16, r []byte) error { - - if !i2c.waitForFlag(flagBUSY, false) { - return errI2CBusReadyTimeout - } - - // disable POS - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_POS) - - pos := 0 - rem := len(r) - - // send peripheral address - if err := i2c.controllerRequestRead(addr, frameNoOption); nil != err { - return err - } - - switch rem { - case 0: - // clear ADDR flag - i2c.clearFlagADDR() - // generate stop condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_STOP) - - case 1: - // disable ACK - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_ACK) - // clear ADDR flag - i2c.clearFlagADDR() - // generate stop condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_STOP) - - case 2: - // disable ACK - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_ACK) - // enable POS - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_POS) - // clear ADDR flag - i2c.clearFlagADDR() - - default: - // enable ACK - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_ACK) - // clear ADDR flag - i2c.clearFlagADDR() - } - - for rem > 0 { - switch rem { - case 1: - // wait until RXNE flag is set - if !i2c.waitForFlagOrError(flagRXNE, true) { - return errI2CReadTimeout - } - - // read data from DR - r[pos] = byte(i2c.Bus.DR.Get()) - - // update counters - pos++ - rem-- - - case 2: - // wait until transfer finished flag BTF is set - if !i2c.waitForFlag(flagBTF, true) { - return errI2CReadTimeout - } - - // generate stop condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_STOP) - - // read data from DR - r[pos] = byte(i2c.Bus.DR.Get()) - - // update counters - pos++ - rem-- - - // read data from DR - r[pos] = byte(i2c.Bus.DR.Get()) - - // update counters - pos++ - rem-- - - case 3: - // wait until transfer finished flag BTF is set - if !i2c.waitForFlag(flagBTF, true) { - return errI2CReadTimeout - } - - // disable ACK - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_ACK) - - // read data from DR - r[pos] = byte(i2c.Bus.DR.Get()) - - // update counters - pos++ - rem-- - - // wait until transfer finished flag BTF is set - if !i2c.waitForFlag(flagBTF, true) { - return errI2CReadTimeout - } - - // generate stop condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_STOP) - - // read data from DR - r[pos] = byte(i2c.Bus.DR.Get()) - - // update counters - pos++ - rem-- - - // read data from DR - r[pos] = byte(i2c.Bus.DR.Get()) - - // update counters - pos++ - rem-- - - default: - // wait until RXNE flag is set - if !i2c.waitForFlagOrError(flagRXNE, true) { - return errI2CReadTimeout - } - - // read data from DR - r[pos] = byte(i2c.Bus.DR.Get()) - - // update counters - pos++ - rem-- - - if i2c.hasFlag(flagBTF) { - // read data from DR - r[pos] = byte(i2c.Bus.DR.Get()) - - // update counters - pos++ - rem-- - } - } - } - - return nil -} - -func (i2c *I2C) controllerRequestRead(addr uint16, option transferOption) error { - - // enable ACK - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_ACK) - - if frameFirstAndLast == option || frameFirst == option || frameNoOption == option { - // generate start condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_START) - } else if false /* (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) */ { - // generate restart condition - i2c.Bus.CR1.SetBits(stm32.I2C_CR1_START) - } - - // ensure start bit is set - if !i2c.waitForFlag(flagSB, true) { - return errI2CSignalStartTimeout - } - - // send peripheral address - i2c.Bus.DR.Set(uint32(addr)<<1 | 1) - - // wait for address ACK from peripheral - if !i2c.waitForFlagOrError(flagADDR, true) { - return errI2CSignalStartTimeout - } - - return nil -} diff --git a/emb/machine/machine_stm32_i2c_revb.go b/emb/machine/machine_stm32_i2c_revb.go deleted file mode 100644 index 006661f..0000000 --- a/emb/machine/machine_stm32_i2c_revb.go +++ /dev/null @@ -1,378 +0,0 @@ -//go:build stm32l5 || stm32f7 || stm32l4 || stm32l0 || stm32wlx - -package machine - -import ( - "device/stm32" - "unsafe" -) - -//go:linkname ticks runtime.ticks -func ticks() int64 - -// I2C implementation for 'newer' STM32 MCUs, including the F7, L5 and L4 -// series of MCUs. -// -// Currently, only 100KHz mode is supported - -const ( - flagBUSY = stm32.I2C_ISR_BUSY - flagTCR = stm32.I2C_ISR_TCR - flagRXNE = stm32.I2C_ISR_RXNE - flagSTOPF = stm32.I2C_ISR_STOPF - flagAF = stm32.I2C_ISR_NACKF - flagTXIS = stm32.I2C_ISR_TXIS - flagTXE = stm32.I2C_ISR_TXE -) - -const ( - MAX_NBYTE_SIZE = 255 - - // 100ms delay = 100e6ns / 16ns - // In runtime_stm32_timers.go, tick is fixed at 16ns per tick - TIMEOUT_TICKS = 100e6 / 16 - - I2C_NO_STARTSTOP = 0x0 - I2C_GENERATE_START_WRITE = 0x80000000 | stm32.I2C_CR2_START - I2C_GENERATE_START_READ = 0x80000000 | stm32.I2C_CR2_START | stm32.I2C_CR2_RD_WRN - I2C_GENERATE_STOP = 0x80000000 | stm32.I2C_CR2_STOP -) - -type I2C struct { - Bus *stm32.I2C_Type - AltFuncSelector uint8 -} - -// I2CConfig is used to store config info for I2C. -type I2CConfig struct { - Frequency uint32 - SCL Pin - SDA Pin -} - -func (i2c *I2C) Configure(config I2CConfig) error { - // Frequency range - switch config.Frequency { - case 0: - config.Frequency = 100 * KHz - case 10 * KHz, 100 * KHz, 400 * KHz, 500 * KHz: - default: - return errI2CNotImplemented - } - - // disable I2C interface before any configuration changes - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_PE) - - // enable clock for I2C - enableAltFuncClock(unsafe.Pointer(i2c.Bus)) - - // init pins - if config.SCL == 0 && config.SDA == 0 { - config.SCL = I2C0_SCL_PIN - config.SDA = I2C0_SDA_PIN - } - i2c.configurePins(config) - - i2c.Bus.TIMINGR.Set(i2c.getFreqRange(config.Frequency)) - - // Disable Own Address1 before set the Own Address1 configuration - i2c.Bus.OAR1.ClearBits(stm32.I2C_OAR1_OA1EN) - - // 7 bit addressing, no self address - i2c.Bus.OAR1.Set(stm32.I2C_OAR1_OA1EN) - - // Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process - i2c.Bus.CR2.Set(stm32.I2C_CR2_AUTOEND | stm32.I2C_CR2_NACK) - - // Disable Own Address2 / Dual Addressing - i2c.Bus.OAR2.Set(0) - - // Disable Generalcall and NoStretch, Enable peripheral - i2c.Bus.CR1.Set(stm32.I2C_CR1_PE) - - return nil -} - -// SetBaudRate sets the communication speed for I2C. -func (i2c *I2C) SetBaudRate(br uint32) error { - switch br { - case 10 * KHz, 100 * KHz, 400 * KHz, 500 * KHz: - default: - return errI2CNotImplemented - } - - // disable I2C interface before any configuration changes - i2c.Bus.CR1.ClearBits(stm32.I2C_CR1_PE) - - i2c.Bus.TIMINGR.Set(i2c.getFreqRange(br)) - - // Disable Generalcall and NoStretch, Enable peripheral - i2c.Bus.CR1.Set(stm32.I2C_CR1_PE) - - return nil -} - -func (i2c *I2C) Tx(addr uint16, w, r []byte) error { - if len(w) > 0 { - if err := i2c.controllerTransmit(addr, w); nil != err { - return err - } - } - - if len(r) > 0 { - if err := i2c.controllerReceive(addr, r); nil != err { - return err - } - } - - return nil -} - -func (i2c *I2C) configurePins(config I2CConfig) { - config.SCL.ConfigureAltFunc(PinConfig{Mode: PinModeI2CSCL}, i2c.AltFuncSelector) - config.SDA.ConfigureAltFunc(PinConfig{Mode: PinModeI2CSDA}, i2c.AltFuncSelector) -} - -func (i2c *I2C) controllerTransmit(addr uint16, w []byte) error { - start := ticks() - - if !i2c.waitOnFlagUntilTimeout(flagBUSY, false, start) { - return errI2CBusReadyTimeout - } - - pos := 0 - xferCount := len(w) - xferSize := uint8(xferCount) - if xferCount > MAX_NBYTE_SIZE { - // Large write, indicate reload - xferSize = MAX_NBYTE_SIZE - i2c.transferConfig(addr, xferSize, stm32.I2C_CR2_RELOAD, I2C_GENERATE_START_WRITE) - } else { - // Small write, auto-end - i2c.transferConfig(addr, xferSize, stm32.I2C_CR2_AUTOEND, I2C_GENERATE_START_WRITE) - } - - for xferCount > 0 { - if !i2c.waitOnTXISFlagUntilTimeout(start) { - return errI2CWriteTimeout - } - - i2c.Bus.TXDR.Set(uint32(w[pos])) - pos++ - xferCount-- - xferSize-- - - // If we've written the last byte of this chunk - if xferCount != 0 && xferSize == 0 { - // Wait for Transfer Complete Reload to be flagged - if !i2c.waitOnFlagUntilTimeout(flagTCR, true, start) { - return errI2CWriteTimeout - } - - if xferCount > MAX_NBYTE_SIZE { - // Large write remaining, indicate reload - xferSize = MAX_NBYTE_SIZE - i2c.transferConfig(addr, xferSize, stm32.I2C_CR2_RELOAD, I2C_NO_STARTSTOP) - } else { - // Small write, auto-end - xferSize = uint8(xferCount) - i2c.transferConfig(addr, xferSize, stm32.I2C_CR2_AUTOEND, I2C_NO_STARTSTOP) - } - } - } - - if !i2c.waitOnStopFlagUntilTimeout(start) { - return errI2CWriteTimeout - } - - i2c.clearFlag(stm32.I2C_ISR_STOPF) - - i2c.resetCR2() - - return nil -} - -func (i2c *I2C) controllerReceive(addr uint16, r []byte) error { - start := ticks() - - if !i2c.waitOnFlagUntilTimeout(flagBUSY, false, start) { - return errI2CBusReadyTimeout - } - - pos := 0 - xferCount := len(r) - xferSize := uint8(xferCount) - if xferCount > MAX_NBYTE_SIZE { - // Large read, indicate reload - xferSize = MAX_NBYTE_SIZE - i2c.transferConfig(addr, xferSize, stm32.I2C_CR2_RELOAD, I2C_GENERATE_START_READ) - } else { - // Small read, auto-end - i2c.transferConfig(addr, xferSize, stm32.I2C_CR2_AUTOEND, I2C_GENERATE_START_READ) - } - - for xferCount > 0 { - if !i2c.waitOnRXNEFlagUntilTimeout(start) { - return errI2CWriteTimeout - } - - r[pos] = uint8(i2c.Bus.RXDR.Get()) - pos++ - xferCount-- - xferSize-- - - // If we've read the last byte of this chunk - if xferCount != 0 && xferSize == 0 { - // Wait for Transfer Complete Reload to be flagged - if !i2c.waitOnFlagUntilTimeout(flagTCR, true, start) { - return errI2CWriteTimeout - } - - if xferCount > MAX_NBYTE_SIZE { - // Large read remaining, indicate reload - xferSize = MAX_NBYTE_SIZE - i2c.transferConfig(addr, xferSize, stm32.I2C_CR2_RELOAD, I2C_NO_STARTSTOP) - } else { - // Small read, auto-end - xferSize = uint8(xferCount) - i2c.transferConfig(addr, xferSize, stm32.I2C_CR2_AUTOEND, I2C_NO_STARTSTOP) - } - } - } - - if !i2c.waitOnStopFlagUntilTimeout(start) { - return errI2CWriteTimeout - } - - i2c.clearFlag(stm32.I2C_ISR_STOPF) - - i2c.resetCR2() - - return nil -} - -func (i2c *I2C) waitOnFlagUntilTimeout(flag uint32, set bool, startTicks int64) bool { - for i2c.hasFlag(flag) != set { - if (ticks() - startTicks) > TIMEOUT_TICKS { - return false - } - } - return true -} - -func (i2c *I2C) waitOnRXNEFlagUntilTimeout(startTicks int64) bool { - for !i2c.hasFlag(flagRXNE) { - if i2c.isAcknowledgeFailed(startTicks) { - return false - } - - if i2c.hasFlag(flagSTOPF) { - i2c.clearFlag(flagSTOPF) - i2c.resetCR2() - return false - } - - if (ticks() - startTicks) > TIMEOUT_TICKS { - return false - } - } - - return true -} - -func (i2c *I2C) waitOnTXISFlagUntilTimeout(startTicks int64) bool { - for !i2c.hasFlag(flagTXIS) { - if i2c.isAcknowledgeFailed(startTicks) { - return false - } - - if (ticks() - startTicks) > TIMEOUT_TICKS { - return false - } - } - - return true -} - -func (i2c *I2C) waitOnStopFlagUntilTimeout(startTicks int64) bool { - for !i2c.hasFlag(flagSTOPF) { - if i2c.isAcknowledgeFailed(startTicks) { - return false - } - - if (ticks() - startTicks) > TIMEOUT_TICKS { - return false - } - } - - return true -} - -func (i2c *I2C) isAcknowledgeFailed(startTicks int64) bool { - if i2c.hasFlag(flagAF) { - // Wait until STOP Flag is reset - // AutoEnd should be initiate after AF - for !i2c.hasFlag(flagSTOPF) { - if (ticks() - startTicks) > TIMEOUT_TICKS { - return true - } - } - - i2c.clearFlag(flagAF) - i2c.clearFlag(flagSTOPF) - i2c.flushTXDR() - i2c.resetCR2() - - return true - } - - return false -} - -func (i2c *I2C) flushTXDR() { - // If a pending TXIS flag is set, write a dummy data in TXDR to clear it - if i2c.hasFlag(flagTXIS) { - i2c.Bus.TXDR.Set(0) - } - - // Flush TX register if not empty - if !i2c.hasFlag(flagTXE) { - i2c.clearFlag(flagTXE) - } -} - -func (i2c *I2C) resetCR2() { - i2c.Bus.CR2.ClearBits(stm32.I2C_CR2_SADD_Msk | - stm32.I2C_CR2_HEAD10R_Msk | - stm32.I2C_CR2_NBYTES_Msk | - stm32.I2C_CR2_RELOAD_Msk | - stm32.I2C_CR2_RD_WRN_Msk) -} - -func (i2c *I2C) transferConfig(addr uint16, size uint8, mode uint32, request uint32) { - mask := uint32(stm32.I2C_CR2_SADD_Msk | - stm32.I2C_CR2_NBYTES_Msk | - stm32.I2C_CR2_RELOAD_Msk | - stm32.I2C_CR2_AUTOEND_Msk | - (stm32.I2C_CR2_RD_WRN & uint32(request>>(31-stm32.I2C_CR2_RD_WRN_Pos))) | - stm32.I2C_CR2_START_Msk | - stm32.I2C_CR2_STOP_Msk) - - value := (uint32(addr<<1) & stm32.I2C_CR2_SADD_Msk) | - ((uint32(size) << stm32.I2C_CR2_NBYTES_Pos) & stm32.I2C_CR2_NBYTES_Msk) | - mode | request - - i2c.Bus.CR2.ReplaceBits(value, mask, 0) -} - -func (i2c *I2C) hasFlag(flag uint32) bool { - return i2c.Bus.ISR.HasBits(flag) -} - -func (i2c *I2C) clearFlag(flag uint32) { - if flag == stm32.I2C_ISR_TXE { - i2c.Bus.ISR.SetBits(flag) - } else { - i2c.Bus.ICR.SetBits(flag) - } -} diff --git a/emb/machine/machine_stm32_iwdg.go b/emb/machine/machine_stm32_iwdg.go deleted file mode 100644 index 1139d54..0000000 --- a/emb/machine/machine_stm32_iwdg.go +++ /dev/null @@ -1,66 +0,0 @@ -//go:build stm32 - -package machine - -import "device/stm32" - -var ( - Watchdog = &watchdogImpl{} -) - -const ( - // WatchdogMaxTimeout in milliseconds (32.768s) - // - // Timeout is based on 12-bit counter with /256 divider on - // 32.768kHz clock. See 21.3.3 of RM0090 for table. - WatchdogMaxTimeout = ((0xfff + 1) * 256 * 1024) / 32768 -) - -const ( - // Enable access to PR, RLR and WINR registers (0x5555) - iwdgKeyEnable = 0x5555 - // Reset the watchdog value (0xAAAA) - iwdgKeyReset = 0xaaaa - // Start the watchdog (0xCCCC) - iwdgKeyStart = 0xcccc - // Divide by 256 - iwdgDiv256 = 6 -) - -type watchdogImpl struct { -} - -// Configure the watchdog. -// -// This method should not be called after the watchdog is started and on -// some platforms attempting to reconfigure after starting the watchdog -// is explicitly forbidden / will not work. -func (wd *watchdogImpl) Configure(config WatchdogConfig) error { - - // Enable configuration of IWDG - stm32.IWDG.KR.Set(iwdgKeyEnable) - - // Unconditionally divide by /256 since we don't really need accuracy - // less than 8ms - stm32.IWDG.PR.Set(iwdgDiv256) - - timeout := config.TimeoutMillis - if timeout > WatchdogMaxTimeout { - timeout = WatchdogMaxTimeout - } - - // Set reload value based on /256 divider - stm32.IWDG.RLR.Set(((config.TimeoutMillis*32768 + (256 * 1024) - 1) / (256 * 1024)) - 1) - return nil -} - -// Starts the watchdog. -func (wd *watchdogImpl) Start() error { - stm32.IWDG.KR.Set(iwdgKeyStart) - return nil -} - -// Update the watchdog, indicating that `source` is healthy. -func (wd *watchdogImpl) Update() { - stm32.IWDG.KR.Set(iwdgKeyReset) -} diff --git a/emb/machine/machine_stm32_moder_gpio.go b/emb/machine/machine_stm32_moder_gpio.go deleted file mode 100644 index b8585c2..0000000 --- a/emb/machine/machine_stm32_moder_gpio.go +++ /dev/null @@ -1,164 +0,0 @@ -//go:build stm32 && !stm32f103 - -package machine - -import ( - "device/stm32" -) - -// GPIO for the stm32 families except the stm32f1xx which uses a simpler but -// less flexible mechanism. Extend the go:build directive above to exclude other -// models in the stm32f1xx series as necessary - -const ( - // Mode Flag - PinOutput PinMode = 0 - PinInput PinMode = PinInputFloating - PinInputFloating PinMode = 1 - PinInputPulldown PinMode = 2 - PinInputPullup PinMode = 3 - - // for UART - PinModeUARTTX PinMode = 4 - PinModeUARTRX PinMode = 5 - - // for I2C - PinModeI2CSCL PinMode = 6 - PinModeI2CSDA PinMode = 7 - - // for SPI - PinModeSPICLK PinMode = 8 - PinModeSPISDO PinMode = 9 - PinModeSPISDI PinMode = 10 - - // for analog/ADC - PinInputAnalog PinMode = 11 - - // for PWM - PinModePWMOutput PinMode = 12 -) - -// Define several bitfields that have different names across chip families but -// essentially have the same meaning. -const ( - // MODER bitfields. - gpioModeInput = 0 - gpioModeOutput = 1 - gpioModeAlternate = 2 - gpioModeAnalog = 3 - gpioModeMask = 0x3 - - // PUPDR bitfields. - gpioPullFloating = 0 - gpioPullUp = 1 - gpioPullDown = 2 - gpioPullMask = 0x3 - - // OSPEED bitfields. - gpioOutputSpeedVeryHigh = 3 - gpioOutputSpeedHigh = 2 - gpioOutputSpeedMedium = 1 - gpioOutputSpeedLow = 0 - gpioOutputSpeedMask = 0x3 -) - -// Configure this pin with the given configuration -func (p Pin) Configure(config PinConfig) { - // Use the default system alternate function; this - // will only be used if you try to call this with - // one of the peripheral modes instead of vanilla GPIO. - p.ConfigureAltFunc(config, 0) -} - -// Configure this pin with the given configuration including alternate -// -// function mapping if necessary. -func (p Pin) ConfigureAltFunc(config PinConfig, altFunc uint8) { - // Configure the GPIO pin. - p.enableClock() - port := p.getPort() - pos := (uint8(p) % 16) * 2 // assume each field is two bits in size (with mask 0x3) - - switch config.Mode { - - // GPIO - case PinInputFloating: - port.MODER.ReplaceBits(gpioModeInput, gpioModeMask, pos) - port.PUPDR.ReplaceBits(gpioPullFloating, gpioPullMask, pos) - case PinInputPulldown: - port.MODER.ReplaceBits(gpioModeInput, gpioModeMask, pos) - port.PUPDR.ReplaceBits(gpioPullDown, gpioPullMask, pos) - case PinInputPullup: - port.MODER.ReplaceBits(gpioModeInput, gpioModeMask, pos) - port.PUPDR.ReplaceBits(gpioPullUp, gpioPullMask, pos) - case PinOutput: - port.MODER.ReplaceBits(gpioModeOutput, gpioModeMask, pos) - port.OSPEEDR.ReplaceBits(gpioOutputSpeedHigh, gpioOutputSpeedMask, pos) - - // UART - case PinModeUARTTX: - port.MODER.ReplaceBits(gpioModeAlternate, gpioModeMask, pos) - port.OSPEEDR.ReplaceBits(gpioOutputSpeedHigh, gpioOutputSpeedMask, pos) - port.PUPDR.ReplaceBits(gpioPullUp, gpioPullMask, pos) - p.SetAltFunc(altFunc) - case PinModeUARTRX: - port.MODER.ReplaceBits(gpioModeAlternate, gpioModeMask, pos) - port.PUPDR.ReplaceBits(gpioPullFloating, gpioPullMask, pos) - p.SetAltFunc(altFunc) - - // I2C - case PinModeI2CSCL: - port.MODER.ReplaceBits(gpioModeAlternate, gpioModeMask, pos) - port.OTYPER.ReplaceBits(stm32.GPIO_OTYPER_OT0_OpenDrain, stm32.GPIO_OTYPER_OT0_Msk, pos/2) - port.OSPEEDR.ReplaceBits(gpioOutputSpeedLow, gpioOutputSpeedMask, pos) - port.PUPDR.ReplaceBits(gpioPullUp, gpioPullMask, pos) - p.SetAltFunc(altFunc) - case PinModeI2CSDA: - port.MODER.ReplaceBits(gpioModeAlternate, gpioModeMask, pos) - port.OTYPER.ReplaceBits(stm32.GPIO_OTYPER_OT0_OpenDrain, stm32.GPIO_OTYPER_OT0_Msk, pos/2) - port.OSPEEDR.ReplaceBits(gpioOutputSpeedLow, gpioOutputSpeedMask, pos) - port.PUPDR.ReplaceBits(gpioPullUp, gpioPullMask, pos) - p.SetAltFunc(altFunc) - - // SPI - case PinModeSPICLK: - port.MODER.ReplaceBits(gpioModeAlternate, gpioModeMask, pos) - port.OSPEEDR.ReplaceBits(gpioOutputSpeedHigh, gpioOutputSpeedMask, pos) - port.PUPDR.ReplaceBits(gpioPullFloating, gpioPullMask, pos) - p.SetAltFunc(altFunc) - case PinModeSPISDO: - port.MODER.ReplaceBits(gpioModeAlternate, gpioModeMask, pos) - port.OSPEEDR.ReplaceBits(gpioOutputSpeedLow, gpioOutputSpeedMask, pos) - port.PUPDR.ReplaceBits(gpioPullFloating, gpioPullMask, pos) - p.SetAltFunc(altFunc) - case PinModeSPISDI: - port.MODER.ReplaceBits(gpioModeAlternate, gpioModeMask, pos) - port.OSPEEDR.ReplaceBits(gpioOutputSpeedLow, gpioOutputSpeedMask, pos) - port.PUPDR.ReplaceBits(gpioPullFloating, gpioPullMask, pos) - p.SetAltFunc(altFunc) - - // PWM - case PinModePWMOutput: - port.MODER.ReplaceBits(gpioModeAlternate, gpioModeMask, pos) - port.OSPEEDR.ReplaceBits(gpioOutputSpeedHigh, gpioOutputSpeedMask, pos) - port.PUPDR.ReplaceBits(gpioPullFloating, gpioPullMask, pos) - p.SetAltFunc(altFunc) - - // ADC - case PinInputAnalog: - port.MODER.ReplaceBits(gpioModeAnalog, gpioModeMask, pos) - port.PUPDR.ReplaceBits(gpioPullFloating, gpioPullMask, pos) - } -} - -// SetAltFunc maps the given alternative function to the I/O pin -func (p Pin) SetAltFunc(af uint8) { - port := p.getPort() - pin := uint8(p) % 16 - pos := (pin % 8) * 4 - if pin < 8 { - port.AFRL.ReplaceBits(uint32(af), 0xf, pos) - } else { - port.AFRH.ReplaceBits(uint32(af), 0xf, pos) - } -} diff --git a/emb/machine/machine_stm32_rng.go b/emb/machine/machine_stm32_rng.go deleted file mode 100644 index 5eaff96..0000000 --- a/emb/machine/machine_stm32_rng.go +++ /dev/null @@ -1,35 +0,0 @@ -//go:build stm32 && !(stm32f103 || stm32l0x1) - -package machine - -import "device/stm32" - -var rngInitDone = false - -const RNG_MAX_READ_RETRIES = 1000 - -// GetRNG returns 32 bits of cryptographically secure random data -func GetRNG() (uint32, error) { - if !rngInitDone { - initRNG() - rngInitDone = true - } - - if stm32.RNG.SR.HasBits(stm32.RNG_SR_CECS) { - return 0, ErrClockRNG - } - if stm32.RNG.SR.HasBits(stm32.RNG_SR_SECS) { - return 0, ErrSeedRNG - } - - cnt := RNG_MAX_READ_RETRIES - for !stm32.RNG.SR.HasBits(stm32.RNG_SR_DRDY) { - cnt-- - if cnt == 0 { - return 0, ErrTimeoutRNG - } - } - - ret := stm32.RNG.DR.Get() - return ret, nil -} diff --git a/emb/machine/machine_stm32_spi.go b/emb/machine/machine_stm32_spi.go deleted file mode 100644 index 3c6e0b6..0000000 --- a/emb/machine/machine_stm32_spi.go +++ /dev/null @@ -1,147 +0,0 @@ -//go:build stm32 && !stm32f7x2 && !stm32l5x2 - -package machine - -// Peripheral abstraction layer for SPI on the stm32 family - -import ( - "device/stm32" - "runtime/volatile" - "unsafe" -) - -// SPIConfig is used to store config info for SPI. -type SPIConfig struct { - Frequency uint32 - SCK Pin - SDO Pin - SDI Pin - LSBFirst bool - Mode uint8 -} - -// Configure is intended to setup the STM32 SPI1 interface. -func (spi *SPI) Configure(config SPIConfig) error { - - // -- CONFIGURING THE SPI IN MASTER MODE -- - // - // 1. Select the BR[2:0] bits to define the serial clock baud rate (see - // SPI_CR1 register). - // 2. Select the CPOL and CPHA bits to define one of the four relationships - // between the data transfer and the serial clock (see Figure 248). This - // step is not required when the TI mode is selected. - // 3. Set the DFF bit to define 8- or 16-bit data frame format - // 4. Configure the LSBFIRST bit in the SPI_CR1 register to define the frame - // format. This step is not required when the TI mode is selected. - // 5. If the NSS pin is required in input mode, in hardware mode, connect the - // NSS pin to a high-level signal during the complete byte transmit - // sequence. In NSS software mode, set the SSM and SSI bits in the SPI_CR1 - // register. If the NSS pin is required in output mode, the SSOE bit only - // should be set. This step is not required when the TI mode is selected. - // 6. Set the FRF bit in SPI_CR2 to select the TI protocol for serial - // communications. - // 7. The MSTR and SPE bits must be set (they remain set only if the NSS pin - // is connected to a high-level signal). - - // disable SPI interface before any configuration changes - spi.Bus.CR1.ClearBits(stm32.SPI_CR1_SPE) - - // enable clock for SPI - enableAltFuncClock(unsafe.Pointer(spi.Bus)) - - // init pins - if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 { - config.SCK = SPI0_SCK_PIN - config.SDO = SPI0_SDO_PIN - config.SDI = SPI0_SDI_PIN - } - spi.configurePins(config) - - // Get SPI baud rate based on the bus speed it's attached to - var conf uint32 = spi.getBaudRate(config) - - // set bit transfer order - if config.LSBFirst { - conf |= stm32.SPI_CR1_LSBFIRST - } - - // set polarity and phase on the SPI interface - switch config.Mode { - case Mode1: - conf |= stm32.SPI_CR1_CPHA - case Mode2: - conf |= stm32.SPI_CR1_CPOL - case Mode3: - conf |= stm32.SPI_CR1_CPOL - conf |= stm32.SPI_CR1_CPHA - } - - // configure as SPI master - conf |= stm32.SPI_CR1_MSTR | stm32.SPI_CR1_SSI - - // enable the SPI interface - conf |= stm32.SPI_CR1_SPE - - // use software CS (GPIO) by default - conf |= stm32.SPI_CR1_SSM - - // now set the configuration - spi.Bus.CR1.Set(conf) - - // Series-specific configuration to set 8-bit transfer mode - spi.config8Bits() - - // enable SPI - spi.Bus.CR1.SetBits(stm32.SPI_CR1_SPE) - - return nil -} - -// Transfer writes/reads a single byte using the SPI interface. -func (spi *SPI) Transfer(w byte) (byte, error) { - - // 1. Enable the SPI by setting the SPE bit to 1. - // 2. Write the first data item to be transmitted into the SPI_DR register - // (this clears the TXE flag). - // 3. Wait until TXE=1 and write the second data item to be transmitted. Then - // wait until RXNE=1 and read the SPI_DR to get the first received data - // item (this clears the RXNE bit). Repeat this operation for each data - // item to be transmitted/received until the n–1 received data. - // 4. Wait until RXNE=1 and read the last received data. - // 5. Wait until TXE=1 and then wait until BSY=0 before disabling the SPI. - - // put output word (8-bit) in data register (DR), which is parallel-loaded - // into shift register, and shifted out on MOSI. Some series have 16-bit - // register but writes must be strictly 8-bit to output a byte. Writing - // 16-bits indicates a packed transfer (2 bytes). - (*volatile.Register8)(unsafe.Pointer(&spi.Bus.DR.Reg)).Set(w) - - // wait for SPI bus receive buffer not empty bit (RXNE) to be set. - // warning: blocks forever until this condition is met. - for !spi.Bus.SR.HasBits(stm32.SPI_SR_RXNE) { - } - - // copy input word (8-bit) in data register (DR), which was shifted in on MISO - // and parallel-loaded into register. - data := byte(spi.Bus.DR.Get()) - - // wait for SPI bus transmit buffer empty bit (TXE) to be set. - // warning: blocks forever until this condition is met. - for !spi.Bus.SR.HasBits(stm32.SPI_SR_TXE) { - } - - // wait for SPI bus busy bit (BSY) to be clear to indicate synchronous - // transfer complete. this will effectively prevent this Transfer() function - // from being capable of maintaining high-bandwidth communication throughput, - // but it will help guarantee stability on the bus. - for spi.Bus.SR.HasBits(stm32.SPI_SR_BSY) { - } - - // clear the overrun flag (only in full-duplex mode) - if !spi.Bus.CR1.HasBits(stm32.SPI_CR1_RXONLY | stm32.SPI_CR1_BIDIMODE | stm32.SPI_CR1_BIDIOE) { - spi.Bus.SR.Get() - } - - // Return received data from SPI data register - return data, nil -} diff --git a/emb/machine/machine_stm32_tim.go b/emb/machine/machine_stm32_tim.go deleted file mode 100644 index 4898ed9..0000000 --- a/emb/machine/machine_stm32_tim.go +++ /dev/null @@ -1,340 +0,0 @@ -//go:build stm32 - -package machine - -// The type alias `arrtype` should be defined to either uint32 or uint16 -// depending on the size of that register in the MCU's TIM_Type structure. - -import ( - "device/stm32" - "runtime/interrupt" - "runtime/volatile" -) - -const PWM_MODE1 = 0x6 - -type TimerCallback func() -type ChannelCallback func(channel uint8) - -type PinFunction struct { - Pin Pin - AltFunc uint8 -} - -type TimerChannel struct { - Pins []PinFunction -} - -type TIM struct { - EnableRegister *volatile.Register32 - EnableFlag uint32 - Device *stm32.TIM_Type - Channels [4]TimerChannel - UpInterrupt interrupt.Interrupt - OCInterrupt interrupt.Interrupt - - wraparoundCallback TimerCallback - channelCallbacks [4]ChannelCallback - - busFreq uint64 -} - -// Configure enables and configures this PWM. -func (t *TIM) Configure(config PWMConfig) error { - // Enable device - t.EnableRegister.SetBits(t.EnableFlag) - - err := t.setPeriod(config.Period, true) - if err != nil { - return err - } - - // Auto-repeat - t.Device.EGR.SetBits(stm32.TIM_EGR_UG) - - // Enable the timer - t.Device.CR1.SetBits(stm32.TIM_CR1_CEN | stm32.TIM_CR1_ARPE) - - return nil -} - -func (t *TIM) Count() uint32 { - return uint32(t.Device.CNT.Get()) -} - -// SetWraparoundInterrupt configures a callback to be called each -// time the timer 'wraps-around'. -// -// For example, if `Configure(PWMConfig{Period:1000000})` is used, -// to set the timer period to 1ms, this callback will be called every -// 1ms. -func (t *TIM) SetWraparoundInterrupt(callback TimerCallback) error { - // Disable this interrupt to prevent race conditions - //t.UpInterrupt.Disable() - - // Ensure the interrupt handler for Update events is registered - t.UpInterrupt = t.registerUPInterrupt() - - // Clear update flag - t.Device.SR.ClearBits(stm32.TIM_SR_UIF) - - t.wraparoundCallback = callback - t.UpInterrupt.SetPriority(0xc1) - t.UpInterrupt.Enable() - - // Enable the hardware interrupt - t.Device.DIER.SetBits(stm32.TIM_DIER_UIE) - - return nil -} - -// Sets a callback to be called when a channel reaches it's set-point. -// -// For example, if `t.Set(ch, t.Top() / 4)` is used then the callback will -// be called every quarter-period of the timer's base Period. -func (t *TIM) SetMatchInterrupt(channel uint8, callback ChannelCallback) error { - t.channelCallbacks[channel] = callback - - // Ensure the interrupt handler for Output Compare events is registered - t.OCInterrupt = t.registerOCInterrupt() - - // Clear the interrupt flag - t.Device.SR.ClearBits(stm32.TIM_SR_CC1IF << channel) - - // Enable the interrupt - t.OCInterrupt.SetPriority(0xc1) - t.OCInterrupt.Enable() - - // Enable the hardware interrupt - t.Device.DIER.SetBits(stm32.TIM_DIER_CC1IE << channel) - - return nil -} - -// SetPeriod updates the period of this PWM peripheral. -// To set a particular frequency, use the following formula: -// -// period = 1e9 / frequency -// -// If you use a period of 0, a period that works well for LEDs will be picked. -// -// SetPeriod will not change the prescaler, but also won't change the current -// value in any of the channels. This means that you may need to update the -// value for the particular channel. -// -// Note that you cannot pick any arbitrary period after the PWM peripheral has -// been configured. If you want to switch between frequencies, pick the lowest -// frequency (longest period) once when calling Configure and adjust the -// frequency here as needed. -func (t *TIM) SetPeriod(period uint64) error { - return t.setPeriod(period, false) -} - -func (t *TIM) setPeriod(period uint64, updatePrescaler bool) error { - var top uint64 - if period == 0 { - top = ARR_MAX - } else { - top = (period / 1000) * (t.busFreq / 1000) / 1000 - } - - var psc uint64 - if updatePrescaler { - if top > ARR_MAX*PSC_MAX { - return ErrPWMPeriodTooLong - } - - // Select the minimum PSC that scales the ARR value into - // range to maintain precision in ARR for changing frequencies - // later - psc = ceil(top, ARR_MAX) - top = top / psc - - t.Device.PSC.Set(uint32(psc - 1)) - } else { - psc = uint64(t.Device.PSC.Get()) + 1 - top = top / psc - - if top > ARR_MAX { - return ErrPWMPeriodTooLong - } - } - - t.Device.ARR.Set(arrtype(top - 1)) - return nil -} - -// Top returns the current counter top, for use in duty cycle calculation. It -// will only change with a call to Configure or SetPeriod, otherwise it is -// constant. -// -// The value returned here is hardware dependent. In general, it's best to treat -// it as an opaque value that can be divided by some number and passed to -// pwm.Set (see pwm.Set for more information). -func (t *TIM) Top() uint32 { - return uint32(t.Device.ARR.Get()) + 1 -} - -// Channel returns a PWM channel for the given pin. -func (t *TIM) Channel(pin Pin) (uint8, error) { - - for chi, ch := range t.Channels { - for _, p := range ch.Pins { - if p.Pin == pin { - t.configurePin(uint8(chi), p) - //p.Pin.ConfigureAltFunc(PinConfig{Mode: PinModePWMOutput}, p.AltFunc) - return uint8(chi), nil - } - } - } - - return 0, ErrInvalidOutputPin -} - -// Set updates the channel value. This is used to control the channel duty -// cycle. For example, to set it to a 25% duty cycle, use: -// -// t.Set(ch, t.Top() / 4) -// -// ch.Set(0) will set the output to low and ch.Set(ch.Top()) will set the output -// to high, assuming the output isn't inverted. -func (t *TIM) Set(channel uint8, value uint32) { - t.enableMainOutput() - - ccr := t.channelCCR(channel) - ccmr, offset := t.channelCCMR(channel) - - // Disable interrupts whilst programming to prevent spurious OC interrupts - mask := interrupt.Disable() - - // Set the PWM to Mode 1 (active below set value, inactive above) - // Preload is disabled so we can change OC value within one update period. - var ccmrVal uint32 - ccmrVal |= PWM_MODE1 << stm32.TIM_CCMR1_Output_OC1M_Pos - ccmr.ReplaceBits(ccmrVal, 0xFF, offset) - - // Set the compare value - ccr.Set(arrtype(value)) - - // Enable the channel (if not already) - t.Device.CCER.ReplaceBits(stm32.TIM_CCER_CC1E, 0xD, channel*4) - - // Force update - t.Device.EGR.SetBits(stm32.TIM_EGR_CC1G << channel) - - // Reset Interrupt Flag - t.Device.SR.ClearBits(stm32.TIM_SR_CC1IF << channel) - - // Restore interrupts - interrupt.Restore(mask) -} - -// Unset disables a channel, including any configured interrupts. -func (t *TIM) Unset(channel uint8) { - // Disable interrupts whilst programming to prevent spurious OC interrupts - mask := interrupt.Disable() - - // Disable the channel - t.Device.CCER.ReplaceBits(0, 0xD, channel*4) - - // Reset to zero value - ccr := t.channelCCR(channel) - ccr.Set(0) - - // Disable the hardware interrupt - t.Device.DIER.ClearBits(stm32.TIM_DIER_CC1IE << channel) - - // Clear the interrupt flag - t.Device.SR.ClearBits(stm32.TIM_SR_CC1IF << channel) - - // Restore interrupts - interrupt.Restore(mask) -} - -// SetInverting sets whether to invert the output of this channel. -// Without inverting, a 25% duty cycle would mean the output is high for 25% of -// the time and low for the rest. Inverting flips the output as if a NOT gate -// was placed at the output, meaning that the output would be 25% low and 75% -// high with a duty cycle of 25%. -func (t *TIM) SetInverting(channel uint8, inverting bool) { - // Enable the channel (if not already) - - var val = uint32(0) - if inverting { - val |= stm32.TIM_CCER_CC1P - } - - t.Device.CCER.ReplaceBits(val, stm32.TIM_CCER_CC1P_Msk, channel*4) -} - -func (t *TIM) handleUPInterrupt(interrupt.Interrupt) { - if t.Device.SR.HasBits(stm32.TIM_SR_UIF) { - // clear the update flag - t.Device.SR.ClearBits(stm32.TIM_SR_UIF) - - if t.wraparoundCallback != nil { - t.wraparoundCallback() - } - } -} - -func (t *TIM) handleOCInterrupt(interrupt.Interrupt) { - if t.Device.SR.HasBits(stm32.TIM_SR_CC1IF) { - if t.channelCallbacks[0] != nil { - t.channelCallbacks[0](0) - } - } - if t.Device.SR.HasBits(stm32.TIM_SR_CC2IF) { - if t.channelCallbacks[1] != nil { - t.channelCallbacks[1](1) - } - } - if t.Device.SR.HasBits(stm32.TIM_SR_CC3IF) { - if t.channelCallbacks[2] != nil { - t.channelCallbacks[2](2) - } - } - if t.Device.SR.HasBits(stm32.TIM_SR_CC4IF) { - if t.channelCallbacks[3] != nil { - t.channelCallbacks[3](3) - } - } - - // Reset interrupt flags - t.Device.SR.ClearBits(stm32.TIM_SR_CC1IF | stm32.TIM_SR_CC2IF | stm32.TIM_SR_CC3IF | stm32.TIM_SR_CC4IF) -} - -func (t *TIM) channelCCR(channel uint8) *arrRegType { - switch channel { - case 0: - return &t.Device.CCR1 - case 1: - return &t.Device.CCR2 - case 2: - return &t.Device.CCR3 - case 3: - return &t.Device.CCR4 - } - - return nil -} - -func (t *TIM) channelCCMR(channel uint8) (reg *volatile.Register32, offset uint8) { - switch channel { - case 0: - return &t.Device.CCMR1_Output, 0 - case 1: - return &t.Device.CCMR1_Output, 8 - case 2: - return &t.Device.CCMR2_Output, 0 - case 3: - return &t.Device.CCMR2_Output, 8 - } - - return nil, 0 -} - -//go:inline -func ceil(num uint64, denom uint64) uint64 { - return (num + denom - 1) / denom -} diff --git a/emb/machine/machine_stm32_tim_moder.go b/emb/machine/machine_stm32_tim_moder.go deleted file mode 100644 index 5cb360d..0000000 --- a/emb/machine/machine_stm32_tim_moder.go +++ /dev/null @@ -1,10 +0,0 @@ -//go:build stm32 && !stm32f1 - -package machine - -// Configuration of a GPIO pin for PWM output for STM32 MCUs with MODER -// register (most MCUs except STM32F1 series). - -func (t *TIM) configurePin(channel uint8, pf PinFunction) { - pf.Pin.ConfigureAltFunc(PinConfig{Mode: PinModePWMOutput}, pf.AltFunc) -} diff --git a/emb/machine/machine_stm32_uart.go b/emb/machine/machine_stm32_uart.go deleted file mode 100644 index 6e8806c..0000000 --- a/emb/machine/machine_stm32_uart.go +++ /dev/null @@ -1,85 +0,0 @@ -//go:build stm32 - -package machine - -// Peripheral abstraction layer for UARTs on the stm32 family. - -import ( - "device/stm32" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -// UART representation -type UART struct { - Buffer *RingBuffer - Bus *stm32.USART_Type - Interrupt interrupt.Interrupt - TxAltFuncSelector uint8 - RxAltFuncSelector uint8 - - // Registers specific to the chip - rxReg *volatile.Register32 - txReg *volatile.Register32 - statusReg *volatile.Register32 - txEmptyFlag uint32 -} - -// Configure the UART. -func (uart *UART) Configure(config UARTConfig) { - // Default baud rate to 115200. - if config.BaudRate == 0 { - config.BaudRate = 115200 - } - - // Set the GPIO pins to defaults if they're not set - if config.TX == 0 && config.RX == 0 { - config.TX = UART_TX_PIN - config.RX = UART_RX_PIN - } - - // STM32 families have different, but compatible, registers for - // basic UART functions. For each family populate the registers - // into `uart`. - uart.setRegisters() - - // Enable USART clock - enableAltFuncClock(unsafe.Pointer(uart.Bus)) - - uart.configurePins(config) - - // Set baud rate - uart.SetBaudRate(config.BaudRate) - - // Enable USART port, tx, rx and rx interrupts - uart.Bus.CR1.Set(stm32.USART_CR1_TE | stm32.USART_CR1_RE | stm32.USART_CR1_RXNEIE | stm32.USART_CR1_UE) - - // Enable RX IRQ - uart.Interrupt.SetPriority(0xc0) - uart.Interrupt.Enable() -} - -// handleInterrupt should be called from the appropriate interrupt handler for -// this UART instance. -func (uart *UART) handleInterrupt(interrupt.Interrupt) { - uart.Receive(byte((uart.rxReg.Get() & 0xFF))) -} - -// SetBaudRate sets the communication speed for the UART. Defer to chip-specific -// routines for calculation -func (uart *UART) SetBaudRate(br uint32) { - divider := uart.getBaudRateDivisor(br) - uart.Bus.BRR.Set(divider) -} - -// WriteByte writes a byte of data to the UART. -func (uart *UART) writeByte(c byte) error { - uart.txReg.Set(uint32(c)) - - for !uart.statusReg.HasBits(uart.txEmptyFlag) { - } - return nil -} - -func (uart *UART) flush() {} diff --git a/emb/machine/machine_stm32f103.go b/emb/machine/machine_stm32f103.go deleted file mode 100644 index 9e7bb34..0000000 --- a/emb/machine/machine_stm32f103.go +++ /dev/null @@ -1,739 +0,0 @@ -//go:build stm32 && stm32f103 - -package machine - -// Peripheral abstraction layer for the stm32. - -import ( - "device/stm32" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -func CPUFrequency() uint32 { - return 72000000 -} - -var deviceIDAddr = []uintptr{0x1FFFF7E8, 0x1FFFF7EC, 0x1FFFF7F0} - -// Internal use: configured speed of the APB1 and APB2 timers, this should be kept -// in sync with any changes to runtime package which configures the oscillators -// and clock frequencies -const APB1_TIM_FREQ = 72e6 // 72MHz -const APB2_TIM_FREQ = 72e6 // 72MHz - -const ( - PinInput PinMode = 0 // Input mode - PinOutput10MHz PinMode = 1 // Output mode, max speed 10MHz - PinOutput2MHz PinMode = 2 // Output mode, max speed 2MHz - PinOutput50MHz PinMode = 3 // Output mode, max speed 50MHz - PinOutput PinMode = PinOutput2MHz - - PinInputModeAnalog PinMode = 0 // Input analog mode - PinInputModeFloating PinMode = 4 // Input floating mode - PinInputModePullUpDown PinMode = 8 // Input pull up/down mode - PinInputModeReserved PinMode = 12 // Input mode (reserved) - - PinOutputModeGPPushPull PinMode = 0 // Output mode general purpose push/pull - PinOutputModeGPOpenDrain PinMode = 4 // Output mode general purpose open drain - PinOutputModeAltPushPull PinMode = 8 // Output mode alt. purpose push/pull - PinOutputModeAltOpenDrain PinMode = 12 // Output mode alt. purpose open drain - - // Pull-up vs Pull down is not part of the CNF0 / CNF1 bits, but is - // controlled by PxODR. Encoded using the 'spare' bit 5. - PinInputPulldown PinMode = PinInputModePullUpDown - PinInputPullup PinMode = PinInputModePullUpDown | 0x10 -) - -// Pin constants for all stm32f103 package sizes -const ( - PA0 = portA + 0 - PA1 = portA + 1 - PA2 = portA + 2 - PA3 = portA + 3 - PA4 = portA + 4 - PA5 = portA + 5 - PA6 = portA + 6 - PA7 = portA + 7 - PA8 = portA + 8 - PA9 = portA + 9 - PA10 = portA + 10 - PA11 = portA + 11 - PA12 = portA + 12 - PA13 = portA + 13 - PA14 = portA + 14 - PA15 = portA + 15 - - PB0 = portB + 0 - PB1 = portB + 1 - PB2 = portB + 2 - PB3 = portB + 3 - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PB8 = portB + 8 - PB9 = portB + 9 - PB10 = portB + 10 - PB11 = portB + 11 - PB12 = portB + 12 - PB13 = portB + 13 - PB14 = portB + 14 - PB15 = portB + 15 - - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PC8 = portC + 8 - PC9 = portC + 9 - PC10 = portC + 10 - PC11 = portC + 11 - PC12 = portC + 12 - PC13 = portC + 13 - PC14 = portC + 14 - PC15 = portC + 15 - - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 - PD4 = portD + 4 - PD5 = portD + 5 - PD6 = portD + 6 - PD7 = portD + 7 - PD8 = portD + 8 - PD9 = portD + 9 - PD10 = portD + 10 - PD11 = portD + 11 - PD12 = portD + 12 - PD13 = portD + 13 - PD14 = portD + 14 - PD15 = portD + 15 - - PE0 = portE + 0 - PE1 = portE + 1 - PE2 = portE + 2 - PE3 = portE + 3 - PE4 = portE + 4 - PE5 = portE + 5 - PE6 = portE + 6 - PE7 = portE + 7 - PE8 = portE + 8 - PE9 = portE + 9 - PE10 = portE + 10 - PE11 = portE + 11 - PE12 = portE + 12 - PE13 = portE + 13 - PE14 = portE + 14 - PE15 = portE + 15 - - PF0 = portF + 0 - PF1 = portF + 1 - PF2 = portF + 2 - PF3 = portF + 3 - PF4 = portF + 4 - PF5 = portF + 5 - PF6 = portF + 6 - PF7 = portF + 7 - PF8 = portF + 8 - PF9 = portF + 9 - PF10 = portF + 10 - PF11 = portF + 11 - PF12 = portF + 12 - PF13 = portF + 13 - PF14 = portF + 14 - PF15 = portF + 15 -) - -// Configure this pin with the given I/O settings. -// stm32f1xx uses different technique for setting the GPIO pins than the stm32f407 -func (p Pin) Configure(config PinConfig) { - // Configure the GPIO pin. - p.enableClock() - port := p.getPort() - pin := uint8(p) % 16 - pos := (pin % 8) * 4 - if pin < 8 { - port.CRL.ReplaceBits(uint32(config.Mode), 0xf, pos) - } else { - port.CRH.ReplaceBits(uint32(config.Mode), 0xf, pos) - } - - // If configured for input pull-up or pull-down, set ODR - // for desired pull-up or pull-down. - if (config.Mode & 0xf) == PinInputModePullUpDown { - var pullup uint32 - if config.Mode == PinInputPullup { - pullup = 1 - } - port.ODR.ReplaceBits(pullup, 0x1, pin) - } -} - -func (p Pin) getPort() *stm32.GPIO_Type { - switch p / 16 { - case 0: - return stm32.GPIOA - case 1: - return stm32.GPIOB - case 2: - return stm32.GPIOC - case 3: - return stm32.GPIOD - case 4: - return stm32.GPIOE - case 5: - return stm32.GPIOF - case 6: - return stm32.GPIOG - default: - panic("machine: unknown port") - } -} - -// enableClock enables the clock for this desired GPIO port. -func (p Pin) enableClock() { - switch p / 16 { - case 0: - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_IOPAEN) - case 1: - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_IOPBEN) - case 2: - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_IOPCEN) - case 3: - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_IOPDEN) - case 4: - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_IOPEEN) - case 5: - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_IOPFEN) - case 6: - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_IOPGEN) - default: - panic("machine: unknown port") - } -} - -// Enable peripheral clock. Expand to include all the desired peripherals -func enableAltFuncClock(bus unsafe.Pointer) { - switch bus { - case unsafe.Pointer(stm32.USART1): - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) - case unsafe.Pointer(stm32.USART2): - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN) - case unsafe.Pointer(stm32.I2C1): - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN) - case unsafe.Pointer(stm32.SPI1): - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) - case unsafe.Pointer(stm32.ADC1): - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC1EN) - default: - panic("machine: unknown peripheral") - } -} - -func (p Pin) registerInterrupt() interrupt.Interrupt { - pin := uint8(p) % 16 - - switch pin { - case 0: - return interrupt.New(stm32.IRQ_EXTI0, func(interrupt.Interrupt) { handlePinInterrupt(0) }) - case 1: - return interrupt.New(stm32.IRQ_EXTI1, func(interrupt.Interrupt) { handlePinInterrupt(1) }) - case 2: - return interrupt.New(stm32.IRQ_EXTI2, func(interrupt.Interrupt) { handlePinInterrupt(2) }) - case 3: - return interrupt.New(stm32.IRQ_EXTI3, func(interrupt.Interrupt) { handlePinInterrupt(3) }) - case 4: - return interrupt.New(stm32.IRQ_EXTI4, func(interrupt.Interrupt) { handlePinInterrupt(4) }) - case 5: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(5) }) - case 6: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(6) }) - case 7: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(7) }) - case 8: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(8) }) - case 9: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(9) }) - case 10: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(10) }) - case 11: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(11) }) - case 12: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(12) }) - case 13: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(13) }) - case 14: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(14) }) - case 15: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(15) }) - } - - return interrupt.Interrupt{} -} - -//---------- UART related code - -// Configure the TX and RX pins -func (uart *UART) configurePins(config UARTConfig) { - - // pins - switch config.TX { - case UART_ALT_TX_PIN: - // use alternate TX/RX pins via AFIO mapping - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_AFIOEN) - if uart.Bus == stm32.USART1 { - stm32.AFIO.MAPR.SetBits(stm32.AFIO_MAPR_USART1_REMAP) - } else if uart.Bus == stm32.USART2 { - stm32.AFIO.MAPR.SetBits(stm32.AFIO_MAPR_USART2_REMAP) - } - default: - // use standard TX/RX pins PA9 and PA10 - } - config.TX.Configure(PinConfig{Mode: PinOutput50MHz + PinOutputModeAltPushPull}) - config.RX.Configure(PinConfig{Mode: PinInputModeFloating}) -} - -// Determine the divisor for USARTs to get the given baudrate -func (uart *UART) getBaudRateDivisor(br uint32) uint32 { - - // Note: PCLK2 (from APB2) used for USART1 and PCLK1 for USART2, 3, 4, 5 - var divider uint32 - if uart.Bus == stm32.USART1 { - // first divide by PCLK2 prescaler (div 1) and then desired baudrate - divider = CPUFrequency() / br - } else { - // first divide by PCLK1 prescaler (div 2) and then desired baudrate - divider = CPUFrequency() / 2 / br - } - return divider -} - -// Register names vary by ST processor, these are for STM F103xx -func (uart *UART) setRegisters() { - uart.rxReg = &uart.Bus.DR - uart.txReg = &uart.Bus.DR - uart.statusReg = &uart.Bus.SR - uart.txEmptyFlag = stm32.USART_SR_TXE -} - -//---------- SPI related types and code - -type SPI struct { - Bus *stm32.SPI_Type -} - -// There are 3 SPI interfaces on the STM32F103xx. -// Since the first interface is named SPI1, both SPI0 and SPI1 refer to SPI1. -// TODO: implement SPI2 and SPI3. -var ( - SPI1 = &SPI{Bus: stm32.SPI1} - SPI0 = SPI1 -) - -func (spi *SPI) config8Bits() { - // no-op on this series -} - -// Set baud rate for SPI -func (spi *SPI) getBaudRate(config SPIConfig) uint32 { - var conf uint32 - - // set frequency dependent on PCLK2 prescaler (div 1) - switch { - case config.Frequency < 125000: - // Note: impossible to achieve lower frequency with current PCLK2! - conf |= stm32.SPI_CR1_BR_Div256 - case config.Frequency < 250000: - conf |= stm32.SPI_CR1_BR_Div256 - case config.Frequency < 500000: - conf |= stm32.SPI_CR1_BR_Div128 - case config.Frequency < 1000000: - conf |= stm32.SPI_CR1_BR_Div64 - case config.Frequency < 2000000: - conf |= stm32.SPI_CR1_BR_Div32 - case config.Frequency < 4000000: - conf |= stm32.SPI_CR1_BR_Div16 - default: - // When its bigger than Div16, just round to the maximum frequency. - conf |= stm32.SPI_CR1_BR_Div8 - } - return conf << stm32.SPI_CR1_BR_Pos -} - -// Configure SPI pins for input output and clock -func (spi *SPI) configurePins(config SPIConfig) { - config.SCK.Configure(PinConfig{Mode: PinOutput50MHz + PinOutputModeAltPushPull}) - config.SDO.Configure(PinConfig{Mode: PinOutput50MHz + PinOutputModeAltPushPull}) - config.SDI.Configure(PinConfig{Mode: PinInputModeFloating}) -} - -//---------- I2C related types and code - -// There are 2 I2C interfaces on the STM32F103xx. -// Since the first interface is named I2C1, both I2C0 and I2C1 refer to I2C1. -// TODO: implement I2C2. - -type I2C struct { - Bus *stm32.I2C_Type -} - -var ( - I2C1 = &I2C{Bus: stm32.I2C1} - I2C0 = I2C1 -) - -func (i2c *I2C) configurePins(config I2CConfig) { - if config.SDA == PB9 { - // use alternate I2C1 pins PB8/PB9 via AFIO mapping - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_AFIOEN) - stm32.AFIO.MAPR.SetBits(stm32.AFIO_MAPR_I2C1_REMAP) - } - - config.SDA.Configure(PinConfig{Mode: PinOutput50MHz + PinOutputModeAltOpenDrain}) - config.SCL.Configure(PinConfig{Mode: PinOutput50MHz + PinOutputModeAltOpenDrain}) -} - -func (i2c *I2C) getFreqRange(config I2CConfig) uint32 { - // pclk1 clock speed is main frequency divided by PCLK1 prescaler (div 2) - pclk1 := CPUFrequency() / 2 - - // set frequency range to PCLK1 clock speed in MHz - // aka setting the value 36 means to use 36 MHz clock - return pclk1 / 1000000 -} - -func (i2c *I2C) getRiseTime(config I2CConfig) uint32 { - // These bits must be programmed with the maximum SCL rise time given in the - // I2C bus specification, incremented by 1. - // For instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns. - // If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 - // and PCLK1 = 125 ns, therefore the TRISE[5:0] bits must be programmed with - // 09h (1000 ns / 125 ns = 8 + 1) - freqRange := i2c.getFreqRange(config) - if config.Frequency > 100000 { - // fast mode (Fm) adjustment - freqRange *= 300 - freqRange /= 1000 - } - return (freqRange + 1) << stm32.I2C_TRISE_TRISE_Pos -} - -func (i2c *I2C) getSpeed(config I2CConfig) uint32 { - ccr := func(pclk uint32, freq uint32, coeff uint32) uint32 { - return (((pclk - 1) / (freq * coeff)) + 1) & stm32.I2C_CCR_CCR_Msk - } - sm := func(pclk uint32, freq uint32) uint32 { // standard mode (Sm) - if s := ccr(pclk, freq, 2); s < 4 { - return 4 - } else { - return s - } - } - fm := func(pclk uint32, freq uint32, duty uint8) uint32 { // fast mode (Fm) - if duty == DutyCycle2 { - return ccr(pclk, freq, 3) - } else { - return ccr(pclk, freq, 25) | stm32.I2C_CCR_DUTY - } - } - clock := CPUFrequency() / 2 - if config.Frequency <= 100000 { - return sm(clock, config.Frequency) - } else { - s := fm(clock, config.Frequency, config.DutyCycle) - if (s & stm32.I2C_CCR_CCR_Msk) == 0 { - return 1 - } else { - return s | stm32.I2C_CCR_F_S - } - } -} - -//---------- Timer related code - -// For Pin Mappings see RM0008, pg 179 -// https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf -// -// Note: for STM32F1 series the pin mapping is done 'per timer' not per channel, -// not all channels on a timer have the same degrees of flexibility, and some -// combinations are only available on some packages - so care is needed at app -// level to ensure valid combinations of pins are used. -// - -var ( - TIM1 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM1EN, - Device: stm32.TIM1, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PE9, 0b11}, {PA8, 0b00}}}, - TimerChannel{Pins: []PinFunction{{PE11, 0b11}, {PA9, 0b00}}}, - TimerChannel{Pins: []PinFunction{{PE13, 0b11}, {PA10, 0b00}}}, - TimerChannel{Pins: []PinFunction{{PE14, 0b11}, {PA11, 0b00}}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM2 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM2EN, - Device: stm32.TIM2, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA0, 0b00}, {PA15, 0b01}}}, - TimerChannel{Pins: []PinFunction{{PA1, 0b00}, {PB3, 0b01}}}, - TimerChannel{Pins: []PinFunction{{PA2, 0b00}, {PB10, 0b10}}}, - TimerChannel{Pins: []PinFunction{{PA3, 0b00}, {PB11, 0b10}}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM3 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM3EN, - Device: stm32.TIM3, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA6, 0b00}, {PC6, 0b11}, {PB4, 0b10}}}, - TimerChannel{Pins: []PinFunction{{PA7, 0b00}, {PC7, 0b11}, {PB5, 0b10}}}, - TimerChannel{Pins: []PinFunction{{PB0, 0b00}, {PC8, 0b11}}}, - TimerChannel{Pins: []PinFunction{{PB1, 0b00}, {PC9, 0b11}}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM4 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM4EN, - Device: stm32.TIM4, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PD12, 0b1}, {PB6, 0}}}, - TimerChannel{Pins: []PinFunction{{PD13, 0b1}, {PB7, 0}}}, - TimerChannel{Pins: []PinFunction{{PD14, 0b1}, {PB8, 0}}}, - TimerChannel{Pins: []PinFunction{{PD15, 0b1}, {PB9, 0}}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM5 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM5EN, - Device: stm32.TIM5, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{{PA3, 0b0}}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM6 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM6EN, - Device: stm32.TIM6, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM7 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM7EN, - Device: stm32.TIM7, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM8 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM8EN, - Device: stm32.TIM8, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM9 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM9EN, - Device: stm32.TIM9, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA2, 0b0}, {PE5, 0b1}}}, - TimerChannel{Pins: []PinFunction{{PA3, 0b0}, {PE6, 0b1}}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM10 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM10EN, - Device: stm32.TIM10, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PB8, 0b0}, {PF6, 0b1}}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM11 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM11EN, - Device: stm32.TIM11, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PB9, 0b0}, {PF7, 0b1}}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM12 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM12EN, - Device: stm32.TIM12, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{}}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM13 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM13EN, - Device: stm32.TIM13, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA6, 0b0}, {PF8, 0b1}}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM14 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM14EN, - Device: stm32.TIM14, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA7, 0b0}, {PF9, 0b1}}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } -) - -func (t *TIM) registerUPInterrupt() interrupt.Interrupt { - switch t { - case &TIM1: - return interrupt.New(stm32.IRQ_TIM1_UP, TIM1.handleUPInterrupt) - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt) - case &TIM3: - return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt) - case &TIM4: - return interrupt.New(stm32.IRQ_TIM4, TIM4.handleUPInterrupt) - case &TIM5: - return interrupt.New(stm32.IRQ_TIM5, TIM5.handleUPInterrupt) - case &TIM6: - return interrupt.New(stm32.IRQ_TIM6, TIM6.handleUPInterrupt) - case &TIM7: - return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt) - case &TIM8: - return interrupt.New(stm32.IRQ_TIM8_UP, TIM8.handleUPInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) registerOCInterrupt() interrupt.Interrupt { - switch t { - case &TIM1: - return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleOCInterrupt) - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt) - case &TIM3: - return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt) - case &TIM4: - return interrupt.New(stm32.IRQ_TIM4, TIM4.handleOCInterrupt) - case &TIM5: - return interrupt.New(stm32.IRQ_TIM5, TIM5.handleOCInterrupt) - case &TIM6: - return interrupt.New(stm32.IRQ_TIM6, TIM6.handleOCInterrupt) - case &TIM7: - return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt) - case &TIM8: - return interrupt.New(stm32.IRQ_TIM8_CC, TIM8.handleOCInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) configurePin(channel uint8, pf PinFunction) { - remap := uint32(pf.AltFunc) - - switch t { - case &TIM1: - stm32.AFIO.MAPR.ReplaceBits(remap< clock { - freq = clock - } - - // calculate the exact clock divisor (freq=clock/div -> div=clock/freq). - // truncation is fine, since it produces a less-than-or-equal divisor, and - // thus a greater-than-or-equal frequency. - // divisors only come in consecutive powers of 2, so we can use log2 (or, - // equivalently, bits.Len - 1) to convert to respective enum value. - div := bits.Len32(clock/freq) - 1 - - // but DIV1 (2^0) is not permitted, as the least divisor is DIV2 (2^1), so - // subtract 1 from the log2 value, keeping a lower bound of 0 - if div < 0 { - div = 0 - } else if div > 0 { - div-- - } - - // finally, shift the enumerated value into position for SPI CR1 - return uint32(div) << stm32.SPI_CR1_BR_Pos -} - -// -- I2C ---------------------------------------------------------------------- - -type I2C struct { - Bus *stm32.I2C_Type - AltFuncSelector uint8 -} - -func (i2c *I2C) configurePins(config I2CConfig) { - config.SCL.ConfigureAltFunc(PinConfig{Mode: PinModeI2CSCL}, i2c.AltFuncSelector) - config.SDA.ConfigureAltFunc(PinConfig{Mode: PinModeI2CSDA}, i2c.AltFuncSelector) -} - -func (i2c *I2C) getFreqRange(config I2CConfig) uint32 { - // all I2C interfaces are on APB1 - clock := CPUFrequency() / 4 - // convert to MHz - clock /= 1000000 - // must be between 2 MHz (or 4 MHz for fast mode (Fm)) and 50 MHz, inclusive - var min, max uint32 = 2, 50 - if config.Frequency > 100000 { - min = 4 // fast mode (Fm) - } - if clock < min { - clock = min - } else if clock > max { - clock = max - } - return clock << stm32.I2C_CR2_FREQ_Pos -} - -func (i2c *I2C) getRiseTime(config I2CConfig) uint32 { - // These bits must be programmed with the maximum SCL rise time given in the - // I2C bus specification, incremented by 1. - // For instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns. - // If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 - // and PCLK1 = 125 ns, therefore the TRISE[5:0] bits must be programmed with - // 09h (1000 ns / 125 ns = 8 + 1) - freqRange := i2c.getFreqRange(config) - if config.Frequency > 100000 { - // fast mode (Fm) adjustment - freqRange *= 300 - freqRange /= 1000 - } - return (freqRange + 1) << stm32.I2C_TRISE_TRISE_Pos -} - -func (i2c *I2C) getSpeed(config I2CConfig) uint32 { - ccr := func(pclk uint32, freq uint32, coeff uint32) uint32 { - return (((pclk - 1) / (freq * coeff)) + 1) & stm32.I2C_CCR_CCR_Msk - } - sm := func(pclk uint32, freq uint32) uint32 { // standard mode (Sm) - if s := ccr(pclk, freq, 2); s < 4 { - return 4 - } else { - return s - } - } - fm := func(pclk uint32, freq uint32, duty uint8) uint32 { // fast mode (Fm) - if duty == DutyCycle2 { - return ccr(pclk, freq, 3) - } else { - return ccr(pclk, freq, 25) | stm32.I2C_CCR_DUTY - } - } - // all I2C interfaces are on APB1 - clock := CPUFrequency() / 4 - if config.Frequency <= 100000 { - return sm(clock, config.Frequency) - } else { - s := fm(clock, config.Frequency, config.DutyCycle) - if (s & stm32.I2C_CCR_CCR_Msk) == 0 { - return 1 - } else { - return s | stm32.I2C_CCR_F_S - } - } -} - -//---------- Flash related code - -// the block size actually depends on the sector. -// TODO: handle this correctly for sectors > 3 -const eraseBlockSizeValue = 16384 - -// see RM0090 page 75 -func sectorNumber(address uintptr) uint32 { - switch { - // 0x0800 0000 - 0x0800 3FFF - case address >= 0x08000000 && address <= 0x08003FFF: - return 0 - // 0x0800 4000 - 0x0800 7FFF - case address >= 0x08004000 && address <= 0x08007FFF: - return 1 - // 0x0800 8000 - 0x0800 BFFF - case address >= 0x08008000 && address <= 0x0800BFFF: - return 2 - // 0x0800 C000 - 0x0800 FFFF - case address >= 0x0800C000 && address <= 0x0800FFFF: - return 3 - // 0x0801 0000 - 0x0801 FFFF - case address >= 0x08010000 && address <= 0x0801FFFF: - return 4 - // 0x0802 0000 - 0x0803 FFFF - case address >= 0x08020000 && address <= 0x0803FFFF: - return 5 - // 0x0804 0000 - 0x0805 FFFF - case address >= 0x08040000 && address <= 0x0805FFFF: - return 6 - case address >= 0x08060000 && address <= 0x0807FFFF: - return 7 - case address >= 0x08080000 && address <= 0x0809FFFF: - return 8 - case address >= 0x080A0000 && address <= 0x080BFFFF: - return 9 - case address >= 0x080C0000 && address <= 0x080DFFFF: - return 10 - case address >= 0x080E0000 && address <= 0x080FFFFF: - return 11 - default: - return 0 - } -} - -// calculate sector number from address -// var sector uint32 = sectorNumber(address) - -// see RM0090 page 85 -// eraseBlock at the passed in block number -func eraseBlock(block uint32) error { - waitUntilFlashDone() - - // clear any previous errors - stm32.FLASH.SR.SetBits(0xF0) - - // set SER bit - stm32.FLASH.SetCR_SER(1) - defer stm32.FLASH.SetCR_SER(0) - - // set the block (aka sector) to be erased - stm32.FLASH.SetCR_SNB(block) - defer stm32.FLASH.SetCR_SNB(0) - - // start the page erase - stm32.FLASH.SetCR_STRT(1) - - waitUntilFlashDone() - - if err := checkError(); err != nil { - return err - } - - return nil -} - -const writeBlockSize = 2 - -// see RM0090 page 86 -// must write data in word-length -func writeFlashData(address uintptr, data []byte) (int, error) { - if len(data)%writeBlockSize != 0 { - return 0, errFlashInvalidWriteLength - } - - waitUntilFlashDone() - - // clear any previous errors - stm32.FLASH.SR.SetBits(0xF0) - - // set parallelism to x32 - stm32.FLASH.SetCR_PSIZE(2) - - for i := 0; i < len(data); i += writeBlockSize { - // start write operation - stm32.FLASH.SetCR_PG(1) - - *(*uint16)(unsafe.Pointer(address)) = binary.LittleEndian.Uint16(data[i : i+writeBlockSize]) - - waitUntilFlashDone() - - if err := checkError(); err != nil { - return i, err - } - - // end write operation - stm32.FLASH.SetCR_PG(0) - } - - return len(data), nil -} - -func waitUntilFlashDone() { - for stm32.FLASH.GetSR_BSY() != 0 { - } -} - -var ( - errFlashPGS = errors.New("errFlashPGS") - errFlashPGP = errors.New("errFlashPGP") - errFlashPGA = errors.New("errFlashPGA") - errFlashWRP = errors.New("errFlashWRP") -) - -func checkError() error { - switch { - case stm32.FLASH.GetSR_PGSERR() != 0: - return errFlashPGS - case stm32.FLASH.GetSR_PGPERR() != 0: - return errFlashPGP - case stm32.FLASH.GetSR_PGAERR() != 0: - return errFlashPGA - case stm32.FLASH.GetSR_WRPERR() != 0: - return errFlashWRP - } - - return nil -} diff --git a/emb/machine/machine_stm32f40x.go b/emb/machine/machine_stm32f40x.go deleted file mode 100644 index 953c7fa..0000000 --- a/emb/machine/machine_stm32f40x.go +++ /dev/null @@ -1,13 +0,0 @@ -//go:build stm32f4 && (stm32f405 || stm32f407) - -package machine - -func CPUFrequency() uint32 { - return 168000000 -} - -// Internal use: configured speed of the APB1 and APB2 timers, this should be kept -// in sync with any changes to runtime package which configures the oscillators -// and clock frequencies -const APB1_TIM_FREQ = 42000000 * 2 -const APB2_TIM_FREQ = 84000000 * 2 diff --git a/emb/machine/machine_stm32f469.go b/emb/machine/machine_stm32f469.go deleted file mode 100644 index dfda91f..0000000 --- a/emb/machine/machine_stm32f469.go +++ /dev/null @@ -1,13 +0,0 @@ -//go:build stm32f4 && stm32f469 - -package machine - -func CPUFrequency() uint32 { - return 180000000 -} - -// Internal use: configured speed of the APB1 and APB2 timers, this should be kept -// in sync with any changes to runtime package which configures the oscillators -// and clock frequencies -const APB1_TIM_FREQ = 45000000 * 2 -const APB2_TIM_FREQ = 90000000 * 2 diff --git a/emb/machine/machine_stm32f7.go b/emb/machine/machine_stm32f7.go deleted file mode 100644 index 11eff11..0000000 --- a/emb/machine/machine_stm32f7.go +++ /dev/null @@ -1,725 +0,0 @@ -//go:build stm32f7 - -package machine - -// Peripheral abstraction layer for the stm32f4 - -import ( - "device/stm32" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -var deviceIDAddr = []uintptr{0x1FF0F420, 0x1FF0F424, 0x1FF0F428} - -// Alternative peripheral pin functions -const ( - AF0_SYSTEM = 0 - AF1_TIM1_2 = 1 - AF2_TIM3_4_5 = 2 - AF3_TIM8_9_10_11_LPTIM1 = 3 - AF4_I2C1_2_3_USART1 = 4 - AF5_SPI1_2_3_4_5_I2S1_2_3 = 5 - AF6_SPI2_3_I2S2_3_SAI1_UART4 = 6 - AF7_SPI2_3_I2S2_3_USART1_2_3_UART5 = 7 - AF8_SAI2_USART6_UART4_5_7_8_OTG1_FS = 8 - AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS = 9 - AF10_SAI2_QUADSPI_SDMMC2_OTG2_HS_OTG1_FS = 10 - AF11_SDMMC2 = 11 - AF12_UART7_FMC_SDMMC1_OTG2_FS = 12 - AF15_EVENTOUT = 15 -) - -const ( - PA0 = portA + 0 - PA1 = portA + 1 - PA2 = portA + 2 - PA3 = portA + 3 - PA4 = portA + 4 - PA5 = portA + 5 - PA6 = portA + 6 - PA7 = portA + 7 - PA8 = portA + 8 - PA9 = portA + 9 - PA10 = portA + 10 - PA11 = portA + 11 - PA12 = portA + 12 - PA13 = portA + 13 - PA14 = portA + 14 - PA15 = portA + 15 - - PB0 = portB + 0 - PB1 = portB + 1 - PB2 = portB + 2 - PB3 = portB + 3 - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PB8 = portB + 8 - PB9 = portB + 9 - PB10 = portB + 10 - PB11 = portB + 11 - PB12 = portB + 12 - PB13 = portB + 13 - PB14 = portB + 14 - PB15 = portB + 15 - - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PC8 = portC + 8 - PC9 = portC + 9 - PC10 = portC + 10 - PC11 = portC + 11 - PC12 = portC + 12 - PC13 = portC + 13 - PC14 = portC + 14 - PC15 = portC + 15 - - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 - PD4 = portD + 4 - PD5 = portD + 5 - PD6 = portD + 6 - PD7 = portD + 7 - PD8 = portD + 8 - PD9 = portD + 9 - PD10 = portD + 10 - PD11 = portD + 11 - PD12 = portD + 12 - PD13 = portD + 13 - PD14 = portD + 14 - PD15 = portD + 15 - - PE0 = portE + 0 - PE1 = portE + 1 - PE2 = portE + 2 - PE3 = portE + 3 - PE4 = portE + 4 - PE5 = portE + 5 - PE6 = portE + 6 - PE7 = portE + 7 - PE8 = portE + 8 - PE9 = portE + 9 - PE10 = portE + 10 - PE11 = portE + 11 - PE12 = portE + 12 - PE13 = portE + 13 - PE14 = portE + 14 - PE15 = portE + 15 - - PF0 = portF + 0 - PF1 = portF + 1 - PF2 = portF + 2 - PF3 = portF + 3 - PF4 = portF + 4 - PF5 = portF + 5 - PF6 = portF + 6 - PF7 = portF + 7 - PF8 = portF + 8 - PF9 = portF + 9 - PF10 = portF + 10 - PF11 = portF + 11 - PF12 = portF + 12 - PF13 = portF + 13 - PF14 = portF + 14 - PF15 = portF + 15 - - PG0 = portG + 0 - PG1 = portG + 1 - PG2 = portG + 2 - PG3 = portG + 3 - PG4 = portG + 4 - PG5 = portG + 5 - PG6 = portG + 6 - PG7 = portG + 7 - PG8 = portG + 8 - PG9 = portG + 9 - PG10 = portG + 10 - PG11 = portG + 11 - PG12 = portG + 12 - PG13 = portG + 13 - PG14 = portG + 14 - PG15 = portG + 15 - - PH0 = portH + 0 - PH1 = portH + 1 - PH2 = portH + 2 - PH3 = portH + 3 - PH4 = portH + 4 - PH5 = portH + 5 - PH6 = portH + 6 - PH7 = portH + 7 - PH8 = portH + 8 - PH9 = portH + 9 - PH10 = portH + 10 - PH11 = portH + 11 - PH12 = portH + 12 - PH13 = portH + 13 - PH14 = portH + 14 - PH15 = portH + 15 - - PI0 = portI + 0 - PI1 = portI + 1 - PI2 = portI + 2 - PI3 = portI + 3 - PI4 = portI + 4 - PI5 = portI + 5 - PI6 = portI + 6 - PI7 = portI + 7 - PI8 = portI + 8 - PI9 = portI + 9 - PI10 = portI + 10 - PI11 = portI + 11 - PI12 = portI + 12 - PI13 = portI + 13 - PI14 = portI + 14 - PI15 = portI + 15 -) - -func (p Pin) getPort() *stm32.GPIO_Type { - switch p / 16 { - case 0: - return stm32.GPIOA - case 1: - return stm32.GPIOB - case 2: - return stm32.GPIOC - case 3: - return stm32.GPIOD - case 4: - return stm32.GPIOE - case 5: - return stm32.GPIOF - case 6: - return stm32.GPIOG - case 7: - return stm32.GPIOH - case 8: - return stm32.GPIOI - default: - panic("machine: unknown port") - } -} - -// enableClock enables the clock for this desired GPIO port. -func (p Pin) enableClock() { - switch p / 16 { - case 0: - stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOAEN) - case 1: - stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOBEN) - case 2: - stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOCEN) - case 3: - stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIODEN) - case 4: - stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOEEN) - case 5: - stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOFEN) - case 6: - stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOGEN) - case 7: - stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOHEN) - case 8: - stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOIEN) - default: - panic("machine: unknown port") - } -} - -// Enable peripheral clock -func enableAltFuncClock(bus unsafe.Pointer) { - switch bus { - case unsafe.Pointer(stm32.DAC): // DAC interface clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_DACEN) - case unsafe.Pointer(stm32.PWR): // Power interface clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN) - case unsafe.Pointer(stm32.CAN1): // CAN 1 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_CAN1EN) - case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN) - case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN) - case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN) - case unsafe.Pointer(stm32.UART5): // UART5 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART5EN) - case unsafe.Pointer(stm32.UART4): // UART4 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART4EN) - case unsafe.Pointer(stm32.USART3): // USART3 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART3EN) - case unsafe.Pointer(stm32.USART2): // USART2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN) - case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI3EN) - case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN) - case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN) - case unsafe.Pointer(stm32.TIM14): // TIM14 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM14EN) - case unsafe.Pointer(stm32.TIM13): // TIM13 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM13EN) - case unsafe.Pointer(stm32.TIM12): // TIM12 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM12EN) - case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN) - case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN) - case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM5EN) - case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM4EN) - case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN) - case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN) - case unsafe.Pointer(stm32.TIM11): // TIM11 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM11EN) - case unsafe.Pointer(stm32.TIM10): // TIM10 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM10EN) - case unsafe.Pointer(stm32.TIM9): // TIM9 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM9EN) - case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) - case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) - case unsafe.Pointer(stm32.ADC3): // ADC3 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC3EN) - case unsafe.Pointer(stm32.ADC2): // ADC2 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC2EN) - case unsafe.Pointer(stm32.ADC1): // ADC1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC1EN) - case unsafe.Pointer(stm32.USART6): // USART6 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART6EN) - case unsafe.Pointer(stm32.USART1): // USART1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) - case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN) - case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN) - } -} - -func (p Pin) registerInterrupt() interrupt.Interrupt { - pin := uint8(p) % 16 - - switch pin { - case 0: - return interrupt.New(stm32.IRQ_EXTI0, func(interrupt.Interrupt) { handlePinInterrupt(0) }) - case 1: - return interrupt.New(stm32.IRQ_EXTI1, func(interrupt.Interrupt) { handlePinInterrupt(1) }) - case 2: - return interrupt.New(stm32.IRQ_EXTI2, func(interrupt.Interrupt) { handlePinInterrupt(2) }) - case 3: - return interrupt.New(stm32.IRQ_EXTI3, func(interrupt.Interrupt) { handlePinInterrupt(3) }) - case 4: - return interrupt.New(stm32.IRQ_EXTI4, func(interrupt.Interrupt) { handlePinInterrupt(4) }) - case 5: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(5) }) - case 6: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(6) }) - case 7: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(7) }) - case 8: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(8) }) - case 9: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(9) }) - case 10: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(10) }) - case 11: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(11) }) - case 12: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(12) }) - case 13: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(13) }) - case 14: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(14) }) - case 15: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(15) }) - } - - return interrupt.Interrupt{} -} - -//---------- Timer related code - -var ( - TIM1 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM1EN, - Device: stm32.TIM1, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA8, AF1_TIM1_2}, - {PE9, AF1_TIM1_2}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA9, AF1_TIM1_2}, - {PE11, AF1_TIM1_2}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA10, AF1_TIM1_2}, - {PE13, AF1_TIM1_2}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA11, AF1_TIM1_2}, - {PE14, AF1_TIM1_2}, - }}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM2 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM2EN, - Device: stm32.TIM2, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA0, AF1_TIM1_2}, - {PA5, AF1_TIM1_2}, - {PA15, AF1_TIM1_2}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA1, AF1_TIM1_2}, - {PB3, AF1_TIM1_2}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA2, AF1_TIM1_2}, - {PB10, AF1_TIM1_2}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA3, AF1_TIM1_2}, - {PB11, AF1_TIM1_2}, - }}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM3 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM3EN, - Device: stm32.TIM3, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA6, AF2_TIM3_4_5}, - {PB4, AF2_TIM3_4_5}, - {PC6, AF2_TIM3_4_5}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA7, AF2_TIM3_4_5}, - {PB5, AF2_TIM3_4_5}, - {PC7, AF2_TIM3_4_5}, - }}, - TimerChannel{Pins: []PinFunction{ - {PB0, AF2_TIM3_4_5}, - {PC8, AF2_TIM3_4_5}, - }}, - TimerChannel{Pins: []PinFunction{ - {PB1, AF2_TIM3_4_5}, - {PC9, AF2_TIM3_4_5}, - }}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM4 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM4EN, - Device: stm32.TIM4, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PB6, AF2_TIM3_4_5}, - {PD12, AF2_TIM3_4_5}, - }}, - TimerChannel{Pins: []PinFunction{ - {PB7, AF2_TIM3_4_5}, - {PD13, AF2_TIM3_4_5}, - }}, - TimerChannel{Pins: []PinFunction{ - {PB8, AF2_TIM3_4_5}, - {PD14, AF2_TIM3_4_5}, - }}, - TimerChannel{Pins: []PinFunction{ - {PB9, AF2_TIM3_4_5}, - {PD15, AF2_TIM3_4_5}, - }}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM5 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM5EN, - Device: stm32.TIM5, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA0, AF2_TIM3_4_5}, - {PH10, AF2_TIM3_4_5}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA1, AF2_TIM3_4_5}, - {PH11, AF2_TIM3_4_5}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA2, AF2_TIM3_4_5}, - {PH12, AF2_TIM3_4_5}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA3, AF2_TIM3_4_5}, - {PI0, AF2_TIM3_4_5}, - }}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM6 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM6EN, - Device: stm32.TIM6, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM7 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM7EN, - Device: stm32.TIM7, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM8 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM8EN, - Device: stm32.TIM8, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PC6, AF3_TIM8_9_10_11_LPTIM1}, - {PI5, AF3_TIM8_9_10_11_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PC7, AF3_TIM8_9_10_11_LPTIM1}, - {PI6, AF3_TIM8_9_10_11_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PC8, AF3_TIM8_9_10_11_LPTIM1}, - {PI7, AF3_TIM8_9_10_11_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PC9, AF3_TIM8_9_10_11_LPTIM1}, - {PI2, AF3_TIM8_9_10_11_LPTIM1}, - }}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM9 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM9EN, - Device: stm32.TIM9, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA2, AF3_TIM8_9_10_11_LPTIM1}, - {PE5, AF3_TIM8_9_10_11_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA3, AF3_TIM8_9_10_11_LPTIM1}, - {PE6, AF3_TIM8_9_10_11_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM10 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM10EN, - Device: stm32.TIM10, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PB8, AF3_TIM8_9_10_11_LPTIM1}, - {PF6, AF3_TIM8_9_10_11_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM11 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM11EN, - Device: stm32.TIM11, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PB9, AF3_TIM8_9_10_11_LPTIM1}, - {PF7, AF3_TIM8_9_10_11_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM12 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM12EN, - Device: stm32.TIM12, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PB14, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, - {PH6, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, - }}, - TimerChannel{Pins: []PinFunction{ - {PB15, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, - {PH9, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM13 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM13EN, - Device: stm32.TIM13, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA6, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, - {PF8, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM14 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM14EN, - Device: stm32.TIM14, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA7, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, - {PF9, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } -) - -func (t *TIM) registerUPInterrupt() interrupt.Interrupt { - switch t { - case &TIM1: - return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM1.handleUPInterrupt) - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt) - case &TIM3: - return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt) - case &TIM4: - return interrupt.New(stm32.IRQ_TIM4, TIM4.handleUPInterrupt) - case &TIM5: - return interrupt.New(stm32.IRQ_TIM5, TIM5.handleUPInterrupt) - case &TIM6: - return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt) - case &TIM7: - return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt) - case &TIM8: - return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM8.handleUPInterrupt) - case &TIM9: - return interrupt.New(stm32.IRQ_TIM1_BRK_TIM9, TIM9.handleUPInterrupt) - case &TIM10: - return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM10.handleUPInterrupt) - case &TIM11: - return interrupt.New(stm32.IRQ_TIM1_TRG_COM_TIM11, TIM11.handleUPInterrupt) - case &TIM12: - return interrupt.New(stm32.IRQ_TIM8_BRK_TIM12, TIM12.handleUPInterrupt) - case &TIM13: - return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM13.handleUPInterrupt) - case &TIM14: - return interrupt.New(stm32.IRQ_TIM8_TRG_COM_TIM14, TIM14.handleUPInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) registerOCInterrupt() interrupt.Interrupt { - switch t { - case &TIM1: - return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleUPInterrupt) - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt) - case &TIM3: - return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt) - case &TIM4: - return interrupt.New(stm32.IRQ_TIM4, TIM4.handleOCInterrupt) - case &TIM5: - return interrupt.New(stm32.IRQ_TIM5, TIM5.handleOCInterrupt) - case &TIM6: - return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt) - case &TIM7: - return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt) - case &TIM8: - return interrupt.New(stm32.IRQ_TIM8_CC, TIM8.handleOCInterrupt) - case &TIM9: - return interrupt.New(stm32.IRQ_TIM1_BRK_TIM9, TIM9.handleOCInterrupt) - case &TIM10: - return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM10.handleOCInterrupt) - case &TIM11: - return interrupt.New(stm32.IRQ_TIM1_TRG_COM_TIM11, TIM11.handleOCInterrupt) - case &TIM12: - return interrupt.New(stm32.IRQ_TIM8_BRK_TIM12, TIM12.handleOCInterrupt) - case &TIM13: - return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM13.handleOCInterrupt) - case &TIM14: - return interrupt.New(stm32.IRQ_TIM8_TRG_COM_TIM14, TIM14.handleOCInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) enableMainOutput() { - t.Device.BDTR.SetBits(stm32.TIM_BDTR_MOE) -} - -type arrtype = uint32 -type arrRegType = volatile.Register32 - -const ( - ARR_MAX = 0x10000 - PSC_MAX = 0x10000 -) - -func initRNG() { - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_RNGEN) - stm32.RNG.CR.SetBits(stm32.RNG_CR_RNGEN) -} diff --git a/emb/machine/machine_stm32f7x2.go b/emb/machine/machine_stm32f7x2.go deleted file mode 100644 index 7da4070..0000000 --- a/emb/machine/machine_stm32f7x2.go +++ /dev/null @@ -1,70 +0,0 @@ -//go:build stm32f7x2 - -package machine - -// Peripheral abstraction layer for the stm32f407 - -import ( - "device/stm32" -) - -func CPUFrequency() uint32 { - return 216000000 -} - -// Internal use: configured speed of the APB1 and APB2 timers, this should be kept -// in sync with any changes to runtime package which configures the oscillators -// and clock frequencies -const APB1_TIM_FREQ = 54e6 // 54MHz -const APB2_TIM_FREQ = 216e6 // 216MHz - -//---------- UART related code - -// Configure the UART. -func (uart *UART) configurePins(config UARTConfig) { - // enable the alternate functions on the TX and RX pins - config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.TxAltFuncSelector) - config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.RxAltFuncSelector) -} - -// UART baudrate calc based on the bus and clockspeed -// NOTE: keep this in sync with the runtime/runtime_stm32f7x2.go clock init code -func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 { - var clock uint32 - switch uart.Bus { - case stm32.USART1, stm32.USART6: - clock = CPUFrequency() / 2 // APB2 Frequency - case stm32.USART2, stm32.USART3, stm32.UART4, stm32.UART5: - clock = CPUFrequency() / 8 // APB1 Frequency - } - return clock / baudRate -} - -// Register names vary by ST processor, these are for STM F7x2 -func (uart *UART) setRegisters() { - uart.rxReg = &uart.Bus.RDR - uart.txReg = &uart.Bus.TDR - uart.statusReg = &uart.Bus.ISR - uart.txEmptyFlag = stm32.USART_ISR_TXE -} - -//---------- I2C related code - -// Gets the value for TIMINGR register -func (i2c *I2C) getFreqRange(br uint32) uint32 { - // This is a 'magic' value calculated by STM32CubeMX - // for 27MHz PCLK1 (216MHz CPU Freq / 8). - // TODO: Do calculations based on PCLK1 - switch br { - case 10 * KHz: - return 0x5010C0FF - case 100 * KHz: - return 0x00606A9B - case 400 * KHz: - return 0x00201625 - case 500 * KHz: - return 0x00100429 - default: - return 0 - } -} diff --git a/emb/machine/machine_stm32l0.go b/emb/machine/machine_stm32l0.go deleted file mode 100644 index 1ecd958..0000000 --- a/emb/machine/machine_stm32l0.go +++ /dev/null @@ -1,317 +0,0 @@ -//go:build stm32l0 - -package machine - -// Peripheral abstraction layer for the stm32l0 - -import ( - "device/stm32" - "runtime/interrupt" -) - -func CPUFrequency() uint32 { - return 32000000 -} - -var deviceIDAddr = []uintptr{0x1FF80050, 0x1FF80054, 0x1FF80058} - -// Internal use: configured speed of the APB1 and APB2 timers, this should be kept -// in sync with any changes to runtime package which configures the oscillators -// and clock frequencies -const APB1_TIM_FREQ = 32e6 // 32MHz -const APB2_TIM_FREQ = 32e6 // 32MHz - -const ( - PA0 = portA + 0 - PA1 = portA + 1 - PA2 = portA + 2 - PA3 = portA + 3 - PA4 = portA + 4 - PA5 = portA + 5 - PA6 = portA + 6 - PA7 = portA + 7 - PA8 = portA + 8 - PA9 = portA + 9 - PA10 = portA + 10 - PA11 = portA + 11 - PA12 = portA + 12 - PA13 = portA + 13 - PA14 = portA + 14 - PA15 = portA + 15 - - PB0 = portB + 0 - PB1 = portB + 1 - PB2 = portB + 2 - PB3 = portB + 3 - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PB8 = portB + 8 - PB9 = portB + 9 - PB10 = portB + 10 - PB11 = portB + 11 - PB12 = portB + 12 - PB13 = portB + 13 - PB14 = portB + 14 - PB15 = portB + 15 - - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PC8 = portC + 8 - PC9 = portC + 9 - PC10 = portC + 10 - PC11 = portC + 11 - PC12 = portC + 12 - PC13 = portC + 13 - PC14 = portC + 14 - PC15 = portC + 15 - - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 - PD4 = portD + 4 - PD5 = portD + 5 - PD6 = portD + 6 - PD7 = portD + 7 - PD8 = portD + 8 - PD9 = portD + 9 - PD10 = portD + 10 - PD11 = portD + 11 - PD12 = portD + 12 - PD13 = portD + 13 - PD14 = portD + 14 - PD15 = portD + 15 - - PE0 = portE + 0 - PE1 = portE + 1 - PE2 = portE + 2 - PE3 = portE + 3 - PE4 = portE + 4 - PE5 = portE + 5 - PE6 = portE + 6 - PE7 = portE + 7 - PE8 = portE + 8 - PE9 = portE + 9 - PE10 = portE + 10 - PE11 = portE + 11 - PE12 = portE + 12 - PE13 = portE + 13 - PE14 = portE + 14 - PE15 = portE + 15 - - PH0 = portH + 0 - PH1 = portH + 1 -) - -func (p Pin) getPort() *stm32.GPIO_Type { - switch p / 16 { - case 0: - return stm32.GPIOA - case 1: - return stm32.GPIOB - case 2: - return stm32.GPIOC - case 3: - return stm32.GPIOD - case 4: - return stm32.GPIOE - case 7: - return stm32.GPIOH - default: - panic("machine: unknown port") - } -} - -// enableClock enables the clock for this desired GPIO port. -func (p Pin) enableClock() { - switch p / 16 { - case 0: - stm32.RCC.IOPENR.SetBits(stm32.RCC_IOPENR_IOPAEN) - case 1: - stm32.RCC.IOPENR.SetBits(stm32.RCC_IOPENR_IOPBEN) - case 2: - stm32.RCC.IOPENR.SetBits(stm32.RCC_IOPENR_IOPCEN) - case 3: - stm32.RCC.IOPENR.SetBits(stm32.RCC_IOPENR_IOPDEN) - case 4: - stm32.RCC.IOPENR.SetBits(stm32.RCC_IOPENR_IOPEEN) - case 7: - stm32.RCC.IOPENR.SetBits(stm32.RCC_IOPENR_IOPHEN) - default: - panic("machine: unknown port") - } -} - -func (p Pin) registerInterrupt() interrupt.Interrupt { - pin := uint8(p) % 16 - - switch pin { - case 0: - return interrupt.New(stm32.IRQ_EXTI0_1, func(interrupt.Interrupt) { handlePinInterrupt(0) }) - case 1: - return interrupt.New(stm32.IRQ_EXTI0_1, func(interrupt.Interrupt) { handlePinInterrupt(1) }) - case 2: - return interrupt.New(stm32.IRQ_EXTI2_3, func(interrupt.Interrupt) { handlePinInterrupt(2) }) - case 3: - return interrupt.New(stm32.IRQ_EXTI2_3, func(interrupt.Interrupt) { handlePinInterrupt(3) }) - case 4: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(4) }) - case 5: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(5) }) - case 6: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(6) }) - case 7: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(7) }) - case 8: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(8) }) - case 9: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(9) }) - case 10: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(10) }) - case 11: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(11) }) - case 12: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(12) }) - case 13: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(13) }) - case 14: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(14) }) - case 15: - return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(15) }) - } - - return interrupt.Interrupt{} -} - -//---------- UART related types and code - -// Configure the UART. -func (uart *UART) configurePins(config UARTConfig) { - // enable the alternate functions on the TX and RX pins - config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.TxAltFuncSelector) - config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.RxAltFuncSelector) -} - -// UART baudrate calc based on the bus and clockspeed -func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 { - var clock, rate uint32 - switch uart.Bus { - case stm32.LPUART1: - clock = CPUFrequency() / 2 // APB1 Frequency - rate = uint32((256 * clock) / baudRate) - case stm32.USART1: - clock = CPUFrequency() / 2 // APB2 Frequency - rate = uint32(clock / baudRate) - case stm32.USART2: - clock = CPUFrequency() / 2 // APB1 Frequency - rate = uint32(clock / baudRate) - } - - return rate -} - -// Register names vary by ST processor, these are for STM L0 family -func (uart *UART) setRegisters() { - uart.rxReg = &uart.Bus.RDR - uart.txReg = &uart.Bus.TDR - uart.statusReg = &uart.Bus.ISR - uart.txEmptyFlag = stm32.USART_ISR_TXE -} - -//---------- SPI related types and code - -// SPI on the STM32Fxxx using MODER / alternate function pins -type SPI struct { - Bus *stm32.SPI_Type - AltFuncSelector uint8 -} - -func (spi *SPI) config8Bits() { - // no-op on this series -} - -// Set baud rate for SPI -func (spi *SPI) getBaudRate(config SPIConfig) uint32 { - var conf uint32 - - localFrequency := config.Frequency - - // Default - if config.Frequency == 0 { - config.Frequency = 4e6 - } - - if spi.Bus != stm32.SPI1 { - // Assume it's SPI2 or SPI3 on APB1 at 1/2 the clock frequency of APB2, so - // we want to pretend to request 2x the baudrate asked for - localFrequency = localFrequency * 2 - } - - // set frequency dependent on PCLK prescaler. Since these are rather weird - // speeds due to the CPU frequency, pick a range up to that frequency for - // clients to use more human-understandable numbers, e.g. nearest 100KHz - - // These are based on APB2 clock frequency (84MHz on the discovery board) - // TODO: also include the MCU/APB clock setting in the equation - switch { - case localFrequency < 328125: - conf = stm32.SPI_CR1_BR_Div256 - case localFrequency < 656250: - conf = stm32.SPI_CR1_BR_Div128 - case localFrequency < 1312500: - conf = stm32.SPI_CR1_BR_Div64 - case localFrequency < 2625000: - conf = stm32.SPI_CR1_BR_Div32 - case localFrequency < 5250000: - conf = stm32.SPI_CR1_BR_Div16 - case localFrequency < 10500000: - conf = stm32.SPI_CR1_BR_Div8 - // NOTE: many SPI components won't operate reliably (or at all) above 10MHz - // Check the datasheet of the part - case localFrequency < 21000000: - conf = stm32.SPI_CR1_BR_Div4 - case localFrequency < 42000000: - conf = stm32.SPI_CR1_BR_Div2 - default: - // None of the specific baudrates were selected; choose the lowest speed - conf = stm32.SPI_CR1_BR_Div256 - } - - return conf << stm32.SPI_CR1_BR_Pos -} - -// Configure SPI pins for input output and clock -func (spi *SPI) configurePins(config SPIConfig) { - config.SCK.ConfigureAltFunc(PinConfig{Mode: PinModeSPICLK}, spi.AltFuncSelector) - config.SDO.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDO}, spi.AltFuncSelector) - config.SDI.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDI}, spi.AltFuncSelector) -} - -//---------- I2C related types and code - -// Gets the value for TIMINGR register -func (i2c I2C) getFreqRange(br uint32) uint32 { - // This is a 'magic' value calculated by STM32CubeMX - // for 16MHz PCLK1. - // TODO: Do calculations based on PCLK1 - switch br { - case 10 * KHz: - return 0x40003EFF - case 100 * KHz: - return 0x00303D5B - case 400 * KHz: - return 0x0010061A - case 500 * KHz: - return 0x00000117 - default: - return 0 - } -} diff --git a/emb/machine/machine_stm32l0x1.go b/emb/machine/machine_stm32l0x1.go deleted file mode 100644 index f0d23ca..0000000 --- a/emb/machine/machine_stm32l0x1.go +++ /dev/null @@ -1,197 +0,0 @@ -//go:build stm32l0x1 - -package machine - -// Peripheral abstraction layer for the stm32l0 - -import ( - "device/stm32" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -const ( - AF0_SYSTEM_SPI1_USART2_LPTIM_TIM21 = 0 - AF1_SPI1_I2C1_LPTIM = 1 - AF2_LPTIM_TIM2 = 2 - AF3_I2C1 = 3 - AF4_I2C1_USART2_LPUART1_TIM22 = 4 - AF5_TIM2_21_22 = 5 - AF6_LPUART1 = 6 - AF7_COMP1_2 = 7 -) - -// Enable peripheral clock -func enableAltFuncClock(bus unsafe.Pointer) { - switch bus { - case unsafe.Pointer(stm32.PWR): // Power interface clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN) - case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN) - case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN) - case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN) - case unsafe.Pointer(stm32.USART5): // UART5 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART5EN) - case unsafe.Pointer(stm32.USART4): // UART4 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART4EN) - case unsafe.Pointer(stm32.USART2): // USART2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN) - case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN) - case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_LPUART1EN) - case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN) - case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN) - case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN) - case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN) - case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN) - case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) - case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) - case unsafe.Pointer(stm32.ADC): // ADC clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADCEN) - case unsafe.Pointer(stm32.USART1): // USART1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) - } -} - -//---------- Timer related code - -var ( - TIM2 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM2EN, - Device: stm32.TIM2, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA0, AF2_LPTIM_TIM2}, {PA5, AF5_TIM2_21_22}, {PA8, AF5_TIM2_21_22}, {PA15, AF5_TIM2_21_22}}}, - TimerChannel{Pins: []PinFunction{{PA1, AF2_LPTIM_TIM2}, {PB3, AF2_LPTIM_TIM2}}}, - TimerChannel{Pins: []PinFunction{{PA2, AF2_LPTIM_TIM2}, {PB0, AF5_TIM2_21_22}, {PB10, AF2_LPTIM_TIM2}}}, - TimerChannel{Pins: []PinFunction{{PA3, AF2_LPTIM_TIM2}, {PB1, AF5_TIM2_21_22}, {PB11, AF2_LPTIM_TIM2}}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM3 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM3EN, - Device: stm32.TIM3, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM6 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM6EN, - Device: stm32.TIM6, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM7 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM7EN, - Device: stm32.TIM7, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM21 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM21EN, - Device: stm32.TIM21, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM22 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM22EN, - Device: stm32.TIM2, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } -) - -func (t *TIM) registerUPInterrupt() interrupt.Interrupt { - switch t { - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt) - case &TIM3: - return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt) - case &TIM6: - return interrupt.New(stm32.IRQ_TIM6, TIM6.handleUPInterrupt) - case &TIM7: - return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt) - case &TIM21: - return interrupt.New(stm32.IRQ_TIM21, TIM21.handleUPInterrupt) - case &TIM22: - return interrupt.New(stm32.IRQ_TIM22, TIM22.handleUPInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) registerOCInterrupt() interrupt.Interrupt { - switch t { - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt) - case &TIM3: - return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt) - case &TIM6: - return interrupt.New(stm32.IRQ_TIM6, TIM6.handleOCInterrupt) - case &TIM7: - return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt) - case &TIM21: - return interrupt.New(stm32.IRQ_TIM21, TIM21.handleOCInterrupt) - case &TIM22: - return interrupt.New(stm32.IRQ_TIM22, TIM22.handleOCInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) enableMainOutput() { - // nothing to do - no BDTR register -} - -type arrtype = uint16 -type arrRegType = volatile.Register16 - -const ( - ARR_MAX = 0x10000 - PSC_MAX = 0x10000 -) diff --git a/emb/machine/machine_stm32l0x2.go b/emb/machine/machine_stm32l0x2.go deleted file mode 100644 index 2a74792..0000000 --- a/emb/machine/machine_stm32l0x2.go +++ /dev/null @@ -1,259 +0,0 @@ -//go:build stm32l0x2 - -package machine - -// Peripheral abstraction layer for the stm32l0 - -import ( - "device/stm32" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -const ( - AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22 = 0 - AF1_SPI1_2_I2S2_I2C1_TIM2_21 = 1 - AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3 = 2 - AF3_I2C1_TSC = 3 - AF4_I2C1_USART1_2_LPUART1_TIM3_22 = 4 - AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22 = 5 - AF6_I2C1_2_LPUART1_USART4_5_TIM21 = 6 - AF7_I2C3_LPUART1_COMP1_2_TIM3 = 7 -) - -// Enable peripheral clock -func enableAltFuncClock(bus unsafe.Pointer) { - switch bus { - case unsafe.Pointer(stm32.DAC): // DAC interface clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_DACEN) - case unsafe.Pointer(stm32.PWR): // Power interface clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN) - case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN) - case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN) - case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN) - case unsafe.Pointer(stm32.USART5): // UART5 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART5EN) - case unsafe.Pointer(stm32.USART4): // UART4 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART4EN) - case unsafe.Pointer(stm32.USART2): // USART2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN) - case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN) - case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_LPUART1EN) - case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN) - case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN) - case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN) - case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN) - case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable - stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN) - case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) - case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) - case unsafe.Pointer(stm32.ADC): // ADC clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADCEN) - case unsafe.Pointer(stm32.USART1): // USART1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) - } -} - -//---------- Timer related code - -var ( - TIM2 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM2EN, - Device: stm32.TIM2, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA0, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PA5, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22}, - {PA15, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22}, - {PE9, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA1, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PB3, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PE10, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA2, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PB10, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PE11, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA3, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PB11, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PE12, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - }}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM3 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM3EN, - Device: stm32.TIM3, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA6, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PB4, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PC6, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PE3, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA7, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PB5, AF4_I2C1_USART1_2_LPUART1_TIM3_22}, - {PC7, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PE4, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - }}, - TimerChannel{Pins: []PinFunction{ - {PB0, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PC8, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PE5, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - }}, - TimerChannel{Pins: []PinFunction{ - {PB1, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PC9, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - {PE6, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3}, - }}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM6 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM6EN, - Device: stm32.TIM6, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM7 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR, - EnableFlag: stm32.RCC_APB1ENR_TIM7EN, - Device: stm32.TIM7, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM21 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM21EN, - Device: stm32.TIM21, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA2, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - {PB13, AF6_I2C1_2_LPUART1_USART4_5_TIM21}, - {PD0, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - {PE5, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA3, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - {PB14, AF6_I2C1_2_LPUART1_USART4_5_TIM21}, - {PD7, AF1_SPI1_2_I2S2_I2C1_TIM2_21}, - {PE6, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM22 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM22EN, - Device: stm32.TIM2, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA6, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22}, - {PB4, AF4_I2C1_USART1_2_LPUART1_TIM3_22}, - {PC6, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - {PE3, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA7, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22}, - {PB5, AF4_I2C1_USART1_2_LPUART1_TIM3_22}, - {PC7, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - {PE4, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } -) - -func (t *TIM) registerUPInterrupt() interrupt.Interrupt { - switch t { - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt) - case &TIM3: - return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt) - case &TIM6: - return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt) - case &TIM7: - return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt) - case &TIM21: - return interrupt.New(stm32.IRQ_TIM21, TIM21.handleUPInterrupt) - case &TIM22: - return interrupt.New(stm32.IRQ_TIM22, TIM22.handleUPInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) registerOCInterrupt() interrupt.Interrupt { - switch t { - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt) - case &TIM3: - return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt) - case &TIM6: - return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt) - case &TIM7: - return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt) - case &TIM21: - return interrupt.New(stm32.IRQ_TIM21, TIM21.handleOCInterrupt) - case &TIM22: - return interrupt.New(stm32.IRQ_TIM22, TIM22.handleOCInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) enableMainOutput() { - // nothing to do - no BDTR register -} - -type arrtype = uint16 -type arrRegType = volatile.Register16 - -const ( - ARR_MAX = 0x10000 - PSC_MAX = 0x10000 -) - -func initRNG() { - stm32.RCC.AHBENR.SetBits(stm32.RCC_AHBENR_RNGEN) - stm32.RNG.CR.SetBits(stm32.RNG_CR_RNGEN) -} diff --git a/emb/machine/machine_stm32l4.go b/emb/machine/machine_stm32l4.go deleted file mode 100644 index b5babc0..0000000 --- a/emb/machine/machine_stm32l4.go +++ /dev/null @@ -1,650 +0,0 @@ -//go:build stm32l4 - -package machine - -import ( - "device/stm32" - "errors" - "internal/binary" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -// Peripheral abstraction layer for the stm32l4 - -var deviceIDAddr = []uintptr{0x1FFF7590, 0x1FFF7594, 0x1FFF7598} - -const ( - AF0_SYSTEM = 0 - AF1_TIM1_2_LPTIM1 = 1 - AF2_TIM1_2 = 2 - AF3_USART2 = 3 - AF4_I2C1_2_3 = 4 - AF5_SPI1_2 = 5 - AF6_SPI3 = 6 - AF7_USART1_2_3 = 7 - AF8_LPUART1 = 8 - AF9_CAN1_TSC = 9 - AF10_USB_QUADSPI = 10 - AF12_COMP1_2_SWPMI1 = 12 - AF13_SAI1 = 13 - AF14_TIM2_15_16_LPTIM2 = 14 - AF15_EVENTOUT = 15 -) - -const ( - PA0 = portA + 0 - PA1 = portA + 1 - PA2 = portA + 2 - PA3 = portA + 3 - PA4 = portA + 4 - PA5 = portA + 5 - PA6 = portA + 6 - PA7 = portA + 7 - PA8 = portA + 8 - PA9 = portA + 9 - PA10 = portA + 10 - PA11 = portA + 11 - PA12 = portA + 12 - PA13 = portA + 13 - PA14 = portA + 14 - PA15 = portA + 15 - - PB0 = portB + 0 - PB1 = portB + 1 - PB2 = portB + 2 - PB3 = portB + 3 - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PB8 = portB + 8 - PB9 = portB + 9 - PB10 = portB + 10 - PB11 = portB + 11 - PB12 = portB + 12 - PB13 = portB + 13 - PB14 = portB + 14 - PB15 = portB + 15 - - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PC8 = portC + 8 - PC9 = portC + 9 - PC10 = portC + 10 - PC11 = portC + 11 - PC12 = portC + 12 - PC13 = portC + 13 - PC14 = portC + 14 - PC15 = portC + 15 - - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 - PD4 = portD + 4 - PD5 = portD + 5 - PD6 = portD + 6 - PD7 = portD + 7 - PD8 = portD + 8 - PD9 = portD + 9 - PD10 = portD + 10 - PD11 = portD + 11 - PD12 = portD + 12 - PD13 = portD + 13 - PD14 = portD + 14 - PD15 = portD + 15 - - PE0 = portE + 0 - PE1 = portE + 1 - PE2 = portE + 2 - PE3 = portE + 3 - PE4 = portE + 4 - PE5 = portE + 5 - PE6 = portE + 6 - PE7 = portE + 7 - PE8 = portE + 8 - PE9 = portE + 9 - PE10 = portE + 10 - PE11 = portE + 11 - PE12 = portE + 12 - PE13 = portE + 13 - PE14 = portE + 14 - PE15 = portE + 15 -) - -// IRQs are defined here as they vary in the SVDs, but do have consistent mapping -// to Timer Interrupts. -const ( - irq_TIM1_BRK_TIM15 = 24 - irq_TIM1_UP_TIM16 = 25 - irq_TIM1_TRG_COM_TIM17 = 26 - irq_TIM1_CC = 27 - irq_TIM2 = 28 - irq_TIM3 = 29 - irq_TIM4 = 30 - irq_TIM5 = 50 - irq_TIM6 = 54 - irq_TIM7 = 55 - irq_TIM8_BRK = 43 - irq_TIM8_UP = 44 - irq_TIM8_TRG_COM = 45 - irq_TIM8_CC = 46 -) - -func (p Pin) getPort() *stm32.GPIO_Type { - switch p / 16 { - case 0: - return stm32.GPIOA - case 1: - return stm32.GPIOB - case 2: - return stm32.GPIOC - case 3: - return stm32.GPIOD - case 4: - return stm32.GPIOE - default: - panic("machine: unknown port") - } -} - -// enableClock enables the clock for this desired GPIO port. -func (p Pin) enableClock() { - switch p / 16 { - case 0: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOAEN) - case 1: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOBEN) - case 2: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOCEN) - case 3: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIODEN) - case 4: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOEEN) - default: - panic("machine: unknown port") - } -} - -// Enable peripheral clock -func enableAltFuncClock(bus unsafe.Pointer) { - switch bus { - case unsafe.Pointer(stm32.PWR): // Power interface clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN) - case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C3EN) - case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C2EN) - case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C1EN) - case unsafe.Pointer(stm32.UART4): // UART4 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART4EN) - case unsafe.Pointer(stm32.USART3): // USART3 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART3EN) - case unsafe.Pointer(stm32.USART2): // USART2 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART2EN) - case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI3EN) - case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI2EN) - case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_WWDGEN) - case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM7EN) - case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM6EN) - case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM3EN) - case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM2EN) - case unsafe.Pointer(stm32.LPTIM2): // LPTIM2 clock enable - stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM2EN) - case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable - stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPUART1EN) - case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN) - case unsafe.Pointer(stm32.TIM15): // TIM15 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN) - case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) - case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) - case unsafe.Pointer(stm32.USART1): // USART1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) - case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN) - } -} - -func handlePinInterrupt(pin uint8) { - if stm32.EXTI.PR1.HasBits(1 << pin) { - // Writing 1 to the pending register clears the - // pending flag for that bit - stm32.EXTI.PR1.Set(1 << pin) - - callback := pinCallbacks[pin] - if callback != nil { - callback(interruptPins[pin]) - } - } -} - -func (p Pin) registerInterrupt() interrupt.Interrupt { - pin := uint8(p) % 16 - - switch pin { - case 0: - return interrupt.New(stm32.IRQ_EXTI0, func(interrupt.Interrupt) { handlePinInterrupt(0) }) - case 1: - return interrupt.New(stm32.IRQ_EXTI1, func(interrupt.Interrupt) { handlePinInterrupt(1) }) - case 2: - return interrupt.New(stm32.IRQ_EXTI2, func(interrupt.Interrupt) { handlePinInterrupt(2) }) - case 3: - return interrupt.New(stm32.IRQ_EXTI3, func(interrupt.Interrupt) { handlePinInterrupt(3) }) - case 4: - return interrupt.New(stm32.IRQ_EXTI4, func(interrupt.Interrupt) { handlePinInterrupt(4) }) - case 5: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(5) }) - case 6: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(6) }) - case 7: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(7) }) - case 8: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(8) }) - case 9: - return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(9) }) - case 10: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(10) }) - case 11: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(11) }) - case 12: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(12) }) - case 13: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(13) }) - case 14: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(14) }) - case 15: - return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(15) }) - } - - return interrupt.Interrupt{} -} - -//---------- UART related code - -// Configure the UART. -func (uart *UART) configurePins(config UARTConfig) { - // enable the alternate functions on the TX and RX pins - config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.TxAltFuncSelector) - config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.RxAltFuncSelector) -} - -// UART baudrate calc based on the bus and clockspeed -// NOTE: keep this in sync with the runtime/runtime_stm32l5x2.go clock init code -func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 { - return (CPUFrequency() / baudRate) -} - -// Register names vary by ST processor, these are for STM L5 -func (uart *UART) setRegisters() { - uart.rxReg = &uart.Bus.RDR - uart.txReg = &uart.Bus.TDR - uart.statusReg = &uart.Bus.ISR - uart.txEmptyFlag = stm32.USART_ISR_TXE -} - -//---------- SPI related types and code - -// SPI on the STM32Fxxx using MODER / alternate function pins -type SPI struct { - Bus *stm32.SPI_Type - AltFuncSelector uint8 -} - -func (spi *SPI) config8Bits() { - // Set rx threshold to 8-bits, so RXNE flag is set for 1 byte - // (common STM32 SPI implementation does 8-bit transfers only) - spi.Bus.CR2.SetBits(stm32.SPI_CR2_FRXTH) -} - -// Set baud rate for SPI -func (spi *SPI) getBaudRate(config SPIConfig) uint32 { - var conf uint32 - - // Default - if config.Frequency == 0 { - config.Frequency = 4e6 - } - - localFrequency := config.Frequency - - // set frequency dependent on PCLK prescaler. Since these are rather weird - // speeds due to the CPU frequency, pick a range up to that frequency for - // clients to use more human-understandable numbers, e.g. nearest 100KHz - - // These are based on 80MHz peripheral clock frequency - switch { - case localFrequency < 312500: - conf = stm32.SPI_CR1_BR_Div256 - case localFrequency < 625000: - conf = stm32.SPI_CR1_BR_Div128 - case localFrequency < 1250000: - conf = stm32.SPI_CR1_BR_Div64 - case localFrequency < 2500000: - conf = stm32.SPI_CR1_BR_Div32 - case localFrequency < 5000000: - conf = stm32.SPI_CR1_BR_Div16 - case localFrequency < 10000000: - conf = stm32.SPI_CR1_BR_Div8 - // NOTE: many SPI components won't operate reliably (or at all) above 10MHz - // Check the datasheet of the part - case localFrequency < 20000000: - conf = stm32.SPI_CR1_BR_Div4 - case localFrequency < 40000000: - conf = stm32.SPI_CR1_BR_Div2 - default: - // None of the specific baudrates were selected; choose the lowest speed - conf = stm32.SPI_CR1_BR_Div256 - } - - return conf << stm32.SPI_CR1_BR_Pos -} - -// Configure SPI pins for input output and clock -func (spi *SPI) configurePins(config SPIConfig) { - config.SCK.ConfigureAltFunc(PinConfig{Mode: PinModeSPICLK}, spi.AltFuncSelector) - config.SDO.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDO}, spi.AltFuncSelector) - config.SDI.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDI}, spi.AltFuncSelector) -} - -//---------- Timer related code - -var ( - TIM1 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM1EN, - Device: stm32.TIM1, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA8, AF1_TIM1_2_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA9, AF1_TIM1_2_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA10, AF1_TIM1_2_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA11, AF1_TIM1_2_LPTIM1}, - }}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM2 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR1, - EnableFlag: stm32.RCC_APB1ENR1_TIM2EN, - Device: stm32.TIM2, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA0, AF1_TIM1_2_LPTIM1}, - {PA5, AF1_TIM1_2_LPTIM1}, - {PA15, AF1_TIM1_2_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA1, AF1_TIM1_2_LPTIM1}, - {PB3, AF1_TIM1_2_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA2, AF1_TIM1_2_LPTIM1}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA3, AF1_TIM1_2_LPTIM1}, - }}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM3 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR1, - EnableFlag: stm32.RCC_APB1ENR1_TIM3EN, - Device: stm32.TIM3, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM6 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR1, - EnableFlag: stm32.RCC_APB1ENR1_TIM6EN, - Device: stm32.TIM6, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM7 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR1, - EnableFlag: stm32.RCC_APB1ENR1_TIM7EN, - Device: stm32.TIM7, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB1_TIM_FREQ, - } - - TIM15 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM15EN, - Device: stm32.TIM15, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA2, AF14_TIM2_15_16_LPTIM2}, - }}, - TimerChannel{Pins: []PinFunction{ - {PA3, AF14_TIM2_15_16_LPTIM2}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - - TIM16 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM16EN, - Device: stm32.TIM16, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{ - {PA6, AF14_TIM2_15_16_LPTIM2}, - }}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } -) - -func (t *TIM) registerUPInterrupt() interrupt.Interrupt { - switch t { - case &TIM1: - return interrupt.New(irq_TIM1_UP_TIM16, TIM1.handleUPInterrupt) - case &TIM2: - return interrupt.New(irq_TIM2, TIM2.handleUPInterrupt) - case &TIM3: - return interrupt.New(irq_TIM3, TIM3.handleUPInterrupt) - case &TIM6: - return interrupt.New(irq_TIM6, TIM6.handleUPInterrupt) - case &TIM7: - return interrupt.New(irq_TIM7, TIM7.handleUPInterrupt) - case &TIM15: - return interrupt.New(irq_TIM1_BRK_TIM15, TIM15.handleUPInterrupt) - case &TIM16: - return interrupt.New(irq_TIM1_UP_TIM16, TIM16.handleUPInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) registerOCInterrupt() interrupt.Interrupt { - switch t { - case &TIM1: - return interrupt.New(irq_TIM1_CC, TIM1.handleUPInterrupt) - case &TIM2: - return interrupt.New(irq_TIM2, TIM2.handleOCInterrupt) - case &TIM3: - return interrupt.New(irq_TIM3, TIM3.handleOCInterrupt) - case &TIM6: - return interrupt.New(irq_TIM6, TIM6.handleOCInterrupt) - case &TIM7: - return interrupt.New(irq_TIM7, TIM7.handleOCInterrupt) - case &TIM15: - return interrupt.New(irq_TIM1_BRK_TIM15, TIM15.handleOCInterrupt) - case &TIM16: - return interrupt.New(irq_TIM1_UP_TIM16, TIM16.handleOCInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) enableMainOutput() { - // nothing to do - no BDTR register -} - -type arrtype = uint32 -type arrRegType = volatile.Register32 - -const ( - ARR_MAX = 0x10000 - PSC_MAX = 0x10000 -) - -func initRNG() { - stm32.RCC.CRRCR.SetBits(stm32.RCC_CRRCR_HSI48ON) - for !stm32.RCC.CRRCR.HasBits(stm32.RCC_CRRCR_HSI48RDY) { - } - - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_RNGEN) - stm32.RNG.CR.SetBits(stm32.RNG_CR_RNGEN) -} - -//---------- Flash related code - -const eraseBlockSizeValue = 2048 - -// see RM0394 page 83 -// eraseBlock of the passed in block number -func eraseBlock(block uint32) error { - waitUntilFlashDone() - - // clear any previous errors - stm32.FLASH.SR.SetBits(0x3FA) - - // page erase operation - stm32.FLASH.SetCR_PER(1) - defer stm32.FLASH.SetCR_PER(0) - - // set the page to be erased - stm32.FLASH.SetCR_PNB(block) - - // start the page erase - stm32.FLASH.SetCR_START(1) - - waitUntilFlashDone() - - if err := checkError(); err != nil { - return err - } - - return nil -} - -const writeBlockSize = 8 - -// see RM0394 page 84 -// It is only possible to program double word (2 x 32-bit data). -func writeFlashData(address uintptr, data []byte) (int, error) { - if len(data)%writeBlockSize != 0 { - return 0, errFlashInvalidWriteLength - } - - waitUntilFlashDone() - - // clear any previous errors - stm32.FLASH.SR.SetBits(0x3FA) - - for j := 0; j < len(data); j += writeBlockSize { - // start page write operation - stm32.FLASH.SetCR_PG(1) - - // write second word using double-word high order word - *(*uint32)(unsafe.Pointer(address)) = binary.LittleEndian.Uint32(data[j : j+writeBlockSize/2]) - - address += writeBlockSize / 2 - - // write first word using double-word low order word - *(*uint32)(unsafe.Pointer(address)) = binary.LittleEndian.Uint32(data[j+writeBlockSize/2 : j+writeBlockSize]) - - waitUntilFlashDone() - - if err := checkError(); err != nil { - return j, err - } - - // end flash write - stm32.FLASH.SetCR_PG(0) - address += writeBlockSize / 2 - } - - return len(data), nil -} - -func waitUntilFlashDone() { - for stm32.FLASH.GetSR_BSY() != 0 { - } -} - -var ( - errFlashPGS = errors.New("errFlashPGS") - errFlashSIZE = errors.New("errFlashSIZE") - errFlashPGA = errors.New("errFlashPGA") - errFlashWRP = errors.New("errFlashWRP") - errFlashPROG = errors.New("errFlashPROG") -) - -func checkError() error { - switch { - case stm32.FLASH.GetSR_PGSERR() != 0: - return errFlashPGS - case stm32.FLASH.GetSR_SIZERR() != 0: - return errFlashSIZE - case stm32.FLASH.GetSR_PGAERR() != 0: - return errFlashPGA - case stm32.FLASH.GetSR_WRPERR() != 0: - return errFlashWRP - case stm32.FLASH.GetSR_PROGERR() != 0: - return errFlashPROG - } - - return nil -} diff --git a/emb/machine/machine_stm32l4x2.go b/emb/machine/machine_stm32l4x2.go deleted file mode 100644 index 142a8f5..0000000 --- a/emb/machine/machine_stm32l4x2.go +++ /dev/null @@ -1,36 +0,0 @@ -//go:build stm32l4x2 - -package machine - -// Peripheral abstraction layer for the stm32l4x2 - -func CPUFrequency() uint32 { - return 80000000 -} - -// Internal use: configured speed of the APB1 and APB2 timers, this should be kept -// in sync with any changes to runtime package which configures the oscillators -// and clock frequencies -const APB1_TIM_FREQ = 80e6 // 80MHz -const APB2_TIM_FREQ = 80e6 // 80MHz - -//---------- I2C related code - -// Gets the value for TIMINGR register -func (i2c *I2C) getFreqRange(br uint32) uint32 { - // These are 'magic' values calculated by STM32CubeMX - // for 80MHz PCLK1. - // TODO: Do calculations based on PCLK1 - switch br { - case 10 * KHz: - return 0xF010F3FE - case 100 * KHz: - return 0x10909CEC - case 400 * KHz: - return 0x00702991 - case 500 * KHz: - return 0x00300E84 - default: - return 0 - } -} diff --git a/emb/machine/machine_stm32l4x5.go b/emb/machine/machine_stm32l4x5.go deleted file mode 100644 index c8c550c..0000000 --- a/emb/machine/machine_stm32l4x5.go +++ /dev/null @@ -1,36 +0,0 @@ -//go:build stm32l4x5 - -package machine - -// Peripheral abstraction layer for the stm32l4x5 - -func CPUFrequency() uint32 { - return 120e6 -} - -// Internal use: configured speed of the APB1 and APB2 timers, this should be kept -// in sync with any changes to runtime package which configures the oscillators -// and clock frequencies -const APB1_TIM_FREQ = 120e6 // 120MHz -const APB2_TIM_FREQ = 120e6 // 120MHz - -//---------- I2C related code - -// Gets the value for TIMINGR register -func (i2c *I2C) getFreqRange(br uint32) uint32 { - // This is a 'magic' value calculated by STM32CubeMX - // for 120MHz PCLK1. - // TODO: Do calculations based on PCLK1 - switch br { - case 10 * KHz: - return 0x0 // does this even work? zero is weird here. - case 100 * KHz: - return 0x307075B1 - case 400 * KHz: - return 0x00B03FDB - case 500 * KHz: - return 0x005017C7 - default: - return 0 - } -} diff --git a/emb/machine/machine_stm32l4x6.go b/emb/machine/machine_stm32l4x6.go deleted file mode 100644 index de878eb..0000000 --- a/emb/machine/machine_stm32l4x6.go +++ /dev/null @@ -1,36 +0,0 @@ -//go:build stm32l4x6 - -package machine - -// Peripheral abstraction layer for the stm32l4x6 - -func CPUFrequency() uint32 { - return 80e6 -} - -// Internal use: configured speed of the APB1 and APB2 timers, this should be kept -// in sync with any changes to runtime package which configures the oscillators -// and clock frequencies -const APB1_TIM_FREQ = 80e6 // 80MHz -const APB2_TIM_FREQ = 80e6 // 80MHz - -//---------- I2C related code - -// Gets the value for TIMINGR register -func (i2c *I2C) getFreqRange(br uint32) uint32 { - // This is a 'magic' value calculated by STM32CubeMX - // for 80MHz PCLK1. - // TODO: Do calculations based on PCLK1 - switch br { - case 10 * KHz: - return 0xF010F3FE - case 100 * KHz: - return 0x10909CEC - case 400 * KHz: - return 0x00702991 - case 500 * KHz: - return 0x00300E84 - default: - return 0 - } -} diff --git a/emb/machine/machine_stm32l5.go b/emb/machine/machine_stm32l5.go deleted file mode 100644 index faa583c..0000000 --- a/emb/machine/machine_stm32l5.go +++ /dev/null @@ -1,559 +0,0 @@ -//go:build stm32l5 - -package machine - -// Peripheral abstraction layer for the stm32l5 - -import ( - "device/stm32" - "runtime/interrupt" - "runtime/volatile" - "unsafe" -) - -var deviceIDAddr = []uintptr{0x0BFA0590, 0x0BFA0594, 0x0BFA0598} - -const ( - AF0_SYSTEM = 0 - AF1_TIM1_2_5_8_LPTIM1 = 1 - AF2_TIM1_2_3_4_5_LPTIM3 = 2 - AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1 = 3 - AF4_I2C1_2_3_4 = 4 - AF5_SPI1_2_3_I2C4_DFSDM1_OCTOSPI1 = 5 - AF6_SPI3_I2C3_DFSDM1_COMP1 = 6 - AF7_USART1_2_3 = 7 - AF8_UART4_5_LPUART1_SDMMC1 = 8 - AF9_FDCAN1_TSC = 9 - AF10_USB_OCTOSPI1 = 10 - AF11_UCPD1 = 11 - AF12_SDMMC1_COMP1_2_TIM1_8_FMC = 12 - AF13_SAI1_2_TIM8 = 13 - AF14_TIM2_8_15_16_17_LPTIM2 = 14 - AF15_EVENTOUT = 15 -) - -const ( - PA0 = portA + 0 - PA1 = portA + 1 - PA2 = portA + 2 - PA3 = portA + 3 - PA4 = portA + 4 - PA5 = portA + 5 - PA6 = portA + 6 - PA7 = portA + 7 - PA8 = portA + 8 - PA9 = portA + 9 - PA10 = portA + 10 - PA11 = portA + 11 - PA12 = portA + 12 - PA13 = portA + 13 - PA14 = portA + 14 - PA15 = portA + 15 - - PB0 = portB + 0 - PB1 = portB + 1 - PB2 = portB + 2 - PB3 = portB + 3 - PB4 = portB + 4 - PB5 = portB + 5 - PB6 = portB + 6 - PB7 = portB + 7 - PB8 = portB + 8 - PB9 = portB + 9 - PB10 = portB + 10 - PB11 = portB + 11 - PB12 = portB + 12 - PB13 = portB + 13 - PB14 = portB + 14 - PB15 = portB + 15 - - PC0 = portC + 0 - PC1 = portC + 1 - PC2 = portC + 2 - PC3 = portC + 3 - PC4 = portC + 4 - PC5 = portC + 5 - PC6 = portC + 6 - PC7 = portC + 7 - PC8 = portC + 8 - PC9 = portC + 9 - PC10 = portC + 10 - PC11 = portC + 11 - PC12 = portC + 12 - PC13 = portC + 13 - PC14 = portC + 14 - PC15 = portC + 15 - - PD0 = portD + 0 - PD1 = portD + 1 - PD2 = portD + 2 - PD3 = portD + 3 - PD4 = portD + 4 - PD5 = portD + 5 - PD6 = portD + 6 - PD7 = portD + 7 - PD8 = portD + 8 - PD9 = portD + 9 - PD10 = portD + 10 - PD11 = portD + 11 - PD12 = portD + 12 - PD13 = portD + 13 - PD14 = portD + 14 - PD15 = portD + 15 - - PE0 = portE + 0 - PE1 = portE + 1 - PE2 = portE + 2 - PE3 = portE + 3 - PE4 = portE + 4 - PE5 = portE + 5 - PE6 = portE + 6 - PE7 = portE + 7 - PE8 = portE + 8 - PE9 = portE + 9 - PE10 = portE + 10 - PE11 = portE + 11 - PE12 = portE + 12 - PE13 = portE + 13 - PE14 = portE + 14 - PE15 = portE + 15 - - PF0 = portF + 0 - PF1 = portF + 1 - PF2 = portF + 2 - PF3 = portF + 3 - PF4 = portF + 4 - PF5 = portF + 5 - PF6 = portF + 6 - PF7 = portF + 7 - PF8 = portF + 8 - PF9 = portF + 9 - PF10 = portF + 10 - PF11 = portF + 11 - PF12 = portF + 12 - PF13 = portF + 13 - PF14 = portF + 14 - PF15 = portF + 15 - - PG0 = portG + 0 - PG1 = portG + 1 - PG2 = portG + 2 - PG3 = portG + 3 - PG4 = portG + 4 - PG5 = portG + 5 - PG6 = portG + 6 - PG7 = portG + 7 - PG8 = portG + 8 - PG9 = portG + 9 - PG10 = portG + 10 - PG11 = portG + 11 - PG12 = portG + 12 - PG13 = portG + 13 - PG14 = portG + 14 - PG15 = portG + 15 - - PH0 = portH + 0 - PH1 = portH + 1 -) - -func (p Pin) getPort() *stm32.GPIO_Type { - switch p / 16 { - case 0: - return stm32.GPIOA - case 1: - return stm32.GPIOB - case 2: - return stm32.GPIOC - case 3: - return stm32.GPIOD - case 4: - return stm32.GPIOE - case 5: - return stm32.GPIOF - case 6: - return stm32.GPIOG - case 7: - return stm32.GPIOH - default: - panic("machine: unknown port") - } -} - -// enableClock enables the clock for this desired GPIO port. -func (p Pin) enableClock() { - switch p / 16 { - case 0: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOAEN) - case 1: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOBEN) - case 2: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOCEN) - case 3: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIODEN) - case 4: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOEEN) - case 5: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOFEN) - case 6: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOGEN) - case 7: - stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOHEN) - default: - panic("machine: unknown port") - } -} - -// Enable peripheral clock -func enableAltFuncClock(bus unsafe.Pointer) { - switch bus { - case unsafe.Pointer(stm32.DAC): // DAC interface clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_DAC1EN) - case unsafe.Pointer(stm32.PWR): // Power interface clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN) - case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C3EN) - case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C2EN) - case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C1EN) - case unsafe.Pointer(stm32.UART5): // UART5 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART5EN) - case unsafe.Pointer(stm32.UART4): // UART4 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART4EN) - case unsafe.Pointer(stm32.USART3): // USART3 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART3EN) - case unsafe.Pointer(stm32.USART2): // USART2 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART2EN) - case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SP3EN) - case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI2EN) - case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_WWDGEN) - case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM7EN) - case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM6EN) - case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM5EN) - case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM4EN) - case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM3EN) - case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable - stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM2EN) - case unsafe.Pointer(stm32.UCPD1): // UCPD1 clock enable - stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_UCPD1EN) - case unsafe.Pointer(stm32.FDCAN1): // FDCAN1 clock enable - stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_FDCAN1EN) - case unsafe.Pointer(stm32.LPTIM3): // LPTIM3 clock enable - stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM3EN) - case unsafe.Pointer(stm32.LPTIM2): // LPTIM2 clock enable - stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM2EN) - case unsafe.Pointer(stm32.I2C4): // I2C4 clock enable - stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_I2C4EN) - case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable - stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPUART1EN) - case unsafe.Pointer(stm32.TIM17): // TIM17 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM17EN) - case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN) - case unsafe.Pointer(stm32.TIM15): // TIM15 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN) - case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) - case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) - case unsafe.Pointer(stm32.USART1): // USART1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) - case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN) - case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable - stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN) - } -} - -func (p Pin) registerInterrupt() interrupt.Interrupt { - pin := uint8(p) % 16 - - switch pin { - case 0: - return interrupt.New(stm32.IRQ_EXTI0, func(interrupt.Interrupt) { handlePinInterrupt(0) }) - case 1: - return interrupt.New(stm32.IRQ_EXTI1, func(interrupt.Interrupt) { handlePinInterrupt(1) }) - case 2: - return interrupt.New(stm32.IRQ_EXTI2, func(interrupt.Interrupt) { handlePinInterrupt(2) }) - case 3: - return interrupt.New(stm32.IRQ_EXTI3, func(interrupt.Interrupt) { handlePinInterrupt(3) }) - case 4: - return interrupt.New(stm32.IRQ_EXTI4, func(interrupt.Interrupt) { handlePinInterrupt(4) }) - case 5: - return interrupt.New(stm32.IRQ_EXTI5, func(interrupt.Interrupt) { handlePinInterrupt(5) }) - case 6: - return interrupt.New(stm32.IRQ_EXTI6, func(interrupt.Interrupt) { handlePinInterrupt(6) }) - case 7: - return interrupt.New(stm32.IRQ_EXTI7, func(interrupt.Interrupt) { handlePinInterrupt(7) }) - case 8: - return interrupt.New(stm32.IRQ_EXTI8, func(interrupt.Interrupt) { handlePinInterrupt(8) }) - case 9: - return interrupt.New(stm32.IRQ_EXTI9, func(interrupt.Interrupt) { handlePinInterrupt(9) }) - case 10: - return interrupt.New(stm32.IRQ_EXTI10, func(interrupt.Interrupt) { handlePinInterrupt(10) }) - case 11: - return interrupt.New(stm32.IRQ_EXTI11, func(interrupt.Interrupt) { handlePinInterrupt(11) }) - case 12: - return interrupt.New(stm32.IRQ_EXTI12, func(interrupt.Interrupt) { handlePinInterrupt(12) }) - case 13: - return interrupt.New(stm32.IRQ_EXTI13, func(interrupt.Interrupt) { handlePinInterrupt(13) }) - case 14: - return interrupt.New(stm32.IRQ_EXTI14, func(interrupt.Interrupt) { handlePinInterrupt(14) }) - case 15: - return interrupt.New(stm32.IRQ_EXTI15, func(interrupt.Interrupt) { handlePinInterrupt(15) }) - } - - return interrupt.Interrupt{} -} - -func handlePinInterrupt(pin uint8) { - // The pin abstraction doesn't differentiate pull-up - // events from pull-down events, so combine them to - // a single call here. - - if stm32.EXTI.RPR1.HasBits(1< clock { - freq = clock - } - - // calculate the exact clock divisor (freq=clock/div -> div=clock/freq). - // truncation is fine, since it produces a less-than-or-equal divisor, and - // thus a greater-than-or-equal frequency. - // divisors only come in consecutive powers of 2, so we can use log2 (or, - // equivalently, bits.Len - 1) to convert to respective enum value. - div := bits.Len32(clock/freq) - 1 - - // but DIV1 (2^0) is not permitted, as the least divisor is DIV2 (2^1), so - // subtract 1 from the log2 value, keeping a lower bound of 0 - if div < 0 { - div = 0 - } else if div > 0 { - div-- - } - - // finally, shift the enumerated value into position for SPI CR1 - return uint32(div) << stm32.SPI_CR1_BR_Pos -} - -//---------- I2C related code - -// Gets the value for TIMINGR register -func (i2c *I2C) getFreqRange(br uint32) uint32 { - // This is a 'magic' value calculated by STM32CubeMX - // for 48Mhz PCLK1. - // TODO: Do calculations based on PCLK1 - switch br { - case 10 * KHz: - return 0x9010DEFF - case 100 * KHz: - return 0x20303E5D - case 400 * KHz: - return 0x2010091A - case 500 * KHz: - return 0x00201441 - default: - return 0 - } -} - -//---------- UART related code - -// Configure the UART. -func (uart UART) configurePins(config UARTConfig) { - // enable the alternate functions on the TX and RX pins - config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.TxAltFuncSelector) - config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.RxAltFuncSelector) -} - -// UART baudrate calc based on the bus and clockspeed -// NOTE: keep this in sync with the runtime/runtime_stm32wle5.go clock init code -func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 { - var br uint32 - uartClock := CPUFrequency() // No Prescaler configuration - br = uint32((uartClock + baudRate/2) / baudRate) - return (br) -} - -// Register names vary by ST processor, these are for STM L5 -func (uart *UART) setRegisters() { - uart.rxReg = &uart.Bus.RDR - uart.txReg = &uart.Bus.TDR - uart.statusReg = &uart.Bus.ISR - uart.txEmptyFlag = stm32.USART_ISR_TXFNF //(TXFNF == TXE == bit 7, but depends alternate RM0461/1094) -} - -//---------- Timer related code - -var ( - TIM1 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM1EN, - Device: stm32.TIM1, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA8, AF1_TIM1_2_LPTIM1}}}, - TimerChannel{Pins: []PinFunction{{PA9, AF1_TIM1_2_LPTIM1}}}, - TimerChannel{Pins: []PinFunction{{PA10, AF1_TIM1_2_LPTIM1}}}, - TimerChannel{Pins: []PinFunction{{PA11, AF1_TIM1_2_LPTIM1}}}, - }, - busFreq: APB2_TIM_FREQ, - } - TIM2 = TIM{ - EnableRegister: &stm32.RCC.APB1ENR1, - EnableFlag: stm32.RCC_APB1ENR1_TIM2EN, - Device: stm32.TIM2, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA0, AF1_TIM1_2_LPTIM1}, {PA5, AF1_TIM1_2_LPTIM1}, {PA15, AF1_TIM1_2_LPTIM1}}}, - TimerChannel{Pins: []PinFunction{{PA1, AF1_TIM1_2_LPTIM1}, {PB3, AF1_TIM1_2_LPTIM1}}}, - TimerChannel{Pins: []PinFunction{{PA2, AF1_TIM1_2_LPTIM1}, {PB10, AF1_TIM1_2_LPTIM1}}}, - TimerChannel{Pins: []PinFunction{{PA3, AF1_TIM1_2_LPTIM1}, {PB11, AF1_TIM1_2_LPTIM1}}}, - }, - busFreq: APB1_TIM_FREQ, - } - TIM16 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM16EN, - Device: stm32.TIM16, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA6, AF14_TIM2_16_17_LPTIM2}}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } - TIM17 = TIM{ - EnableRegister: &stm32.RCC.APB2ENR, - EnableFlag: stm32.RCC_APB2ENR_TIM17EN, - Device: stm32.TIM17, - Channels: [4]TimerChannel{ - TimerChannel{Pins: []PinFunction{{PA7, AF1_TIM1_2_LPTIM1}, {PB9, AF1_TIM1_2_LPTIM1}}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - TimerChannel{Pins: []PinFunction{}}, - }, - busFreq: APB2_TIM_FREQ, - } -) - -func (t *TIM) registerUPInterrupt() interrupt.Interrupt { - switch t { - case &TIM1: - return interrupt.New(stm32.IRQ_TIM1_UP, TIM1.handleUPInterrupt) - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt) - case &TIM16: - return interrupt.New(stm32.IRQ_TIM16, TIM16.handleUPInterrupt) - case &TIM17: - return interrupt.New(stm32.IRQ_TIM17, TIM17.handleUPInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) registerOCInterrupt() interrupt.Interrupt { - switch t { - case &TIM1: - return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleOCInterrupt) - case &TIM2: - return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt) - case &TIM16: - return interrupt.New(stm32.IRQ_TIM16, TIM16.handleOCInterrupt) - case &TIM17: - return interrupt.New(stm32.IRQ_TIM17, TIM17.handleOCInterrupt) - } - - return interrupt.Interrupt{} -} - -func (t *TIM) enableMainOutput() { - t.Device.BDTR.SetBits(stm32.TIM_BDTR_MOE) -} - -func initRNG() { - stm32.RCC.AHB3ENR.SetBits(stm32.RCC_AHB3ENR_RNGEN) - - // Enable RNG with config.A (See RM0453 22.6.2) - stm32.RNG.CR.Set(0x40F00D40) // RNG Config. A - stm32.RNG.HTCR.Set(0x17590ABC) // MAGIC NUMBER - stm32.RNG.HTCR.Set(0x0000AA74) // HTCR VALUE - stm32.RNG.CR.Set(0x00F00D4C) // CONFIG A + RNG_EN=1 + IE=1 -} - -//---------- - -type arrtype = uint32 -type arrRegType = volatile.Register32 - -const ( - ARR_MAX = 0x10000 - PSC_MAX = 0x10000 -) - -//---------- Flash related code - -const eraseBlockSizeValue = 2048 - -// eraseBlock of the passed in block number -func eraseBlock(block uint32) error { - waitUntilFlashDone() - - // check if operation is allowed. - if stm32.FLASH.GetSR_PESD() != 0 { - return errFlashCannotErasePage - } - - // clear any previous errors - stm32.FLASH.SR.SetBits(0x3FA) - - // page erase operation - stm32.FLASH.SetCR_PER(1) - defer stm32.FLASH.SetCR_PER(0) - - // set the address to the page to be written - stm32.FLASH.SetCR_PNB(block) - defer stm32.FLASH.SetCR_PNB(0) - - // start the page erase - stm32.FLASH.SetCR_STRT(1) - - waitUntilFlashDone() - - if err := checkError(); err != nil { - return err - } - - return nil -} - -const writeBlockSize = 8 - -func writeFlashData(address uintptr, data []byte) (int, error) { - if len(data)%writeBlockSize != 0 { - return 0, errFlashInvalidWriteLength - } - - waitUntilFlashDone() - - // check if operation is allowed - if stm32.FLASH.GetSR_PESD() != 0 { - return 0, errFlashNotAllowedWriteData - } - - // clear any previous errors - stm32.FLASH.SR.SetBits(0x3FA) - - for j := 0; j < len(data); j += writeBlockSize { - // start page write operation - stm32.FLASH.SetCR_PG(1) - - // write first word using double-word high order word - *(*uint32)(unsafe.Pointer(address)) = binary.LittleEndian.Uint32(data[j : j+writeBlockSize/2]) - - address += writeBlockSize / 2 - - // write second word using double-word low order word - *(*uint32)(unsafe.Pointer(address)) = binary.LittleEndian.Uint32(data[j+writeBlockSize/2 : j+writeBlockSize]) - - waitUntilFlashDone() - - if err := checkError(); err != nil { - return j, err - } - - // end flash write - stm32.FLASH.SetCR_PG(0) - address += writeBlockSize / 2 - } - - return len(data), nil -} - -func waitUntilFlashDone() { - for stm32.FLASH.GetSR_BSY() != 0 { - } - - for stm32.FLASH.GetSR_CFGBSY() != 0 { - } -} - -var ( - errFlashPGS = errors.New("errFlashPGS") - errFlashSIZE = errors.New("errFlashSIZE") - errFlashPGA = errors.New("errFlashPGA") - errFlashWRP = errors.New("errFlashWRP") - errFlashPROG = errors.New("errFlashPROG") -) - -func checkError() error { - switch { - case stm32.FLASH.GetSR_PGSERR() != 0: - return errFlashPGS - case stm32.FLASH.GetSR_SIZERR() != 0: - return errFlashSIZE - case stm32.FLASH.GetSR_PGAERR() != 0: - return errFlashPGA - case stm32.FLASH.GetSR_WRPERR() != 0: - return errFlashWRP - case stm32.FLASH.GetSR_PROGERR() != 0: - return errFlashPROG - } - - return nil -} diff --git a/emb/machine/machine_tkey.go b/emb/machine/machine_tkey.go deleted file mode 100644 index 78863d8..0000000 --- a/emb/machine/machine_tkey.go +++ /dev/null @@ -1,234 +0,0 @@ -//go:build tkey - -package machine - -import ( - "device/tkey" - "errors" - "strconv" -) - -const deviceName = "TKey" - -// GPIO pins modes are only here to match the Pin interface. -// The actual configuration is fixed in the hardware. -const ( - PinOutput PinMode = iota - PinInput - PinInputPullup - PinInputPulldown -) - -const ( - LED_BLUE = Pin(tkey.TK1_MMIO_TK1_LED_B_BIT) - LED_GREEN = Pin(tkey.TK1_MMIO_TK1_LED_G_BIT) - LED_RED = Pin(tkey.TK1_MMIO_TK1_LED_R_BIT) - - LED = LED_GREEN - - TKEY_TOUCH = Pin(3) // 3 is unused, but we need a value here to match the Pin interface. - BUTTON = TKEY_TOUCH - - GPIO1 = Pin(tkey.TK1_MMIO_TK1_GPIO1_BIT + 8) - GPIO2 = Pin(tkey.TK1_MMIO_TK1_GPIO2_BIT + 8) - GPIO3 = Pin(tkey.TK1_MMIO_TK1_GPIO3_BIT + 8) - GPIO4 = Pin(tkey.TK1_MMIO_TK1_GPIO4_BIT + 8) -) - -var touchConfig, gpio1Config, gpio2Config PinConfig - -// No config needed for TKey, just to match the Pin interface. -func (p Pin) Configure(config PinConfig) { - switch p { - case BUTTON: - touchConfig = config - - // Clear any pending touch events. - tkey.TOUCH.STATUS.Set(0) - case GPIO1: - gpio1Config = config - case GPIO2: - gpio2Config = config - } -} - -// Set pin to high or low. -func (p Pin) Set(high bool) { - switch p { - case LED_BLUE, LED_GREEN, LED_RED: - if high { - tkey.TK1.LED.SetBits(1 << uint(p)) - } else { - tkey.TK1.LED.ClearBits(1 << uint(p)) - } - case GPIO3, GPIO4: - if high { - tkey.TK1.GPIO.SetBits(1 << uint(p-8)) - } else { - tkey.TK1.GPIO.ClearBits(1 << uint(p-8)) - } - } -} - -// Get returns the current value of a pin. -func (p Pin) Get() bool { - pushed := false - mode := PinInput - - switch p { - case BUTTON: - mode = touchConfig.Mode - if tkey.TOUCH.STATUS.HasBits(1) { - tkey.TOUCH.STATUS.Set(0) - pushed = true - } - case GPIO1: - mode = gpio1Config.Mode - pushed = tkey.TK1.GPIO.HasBits(1 << uint(p-8)) - case GPIO2: - mode = gpio2Config.Mode - pushed = tkey.TK1.GPIO.HasBits(1 << uint(p-8)) - case GPIO3, GPIO4: - mode = PinOutput - pushed = tkey.TK1.GPIO.HasBits(1 << uint(p-8)) - case LED_BLUE, LED_GREEN, LED_RED: - mode = PinOutput - pushed = tkey.TK1.LED.HasBits(1 << uint(p)) - } - - switch mode { - case PinInputPullup: - return !pushed - case PinInput, PinInputPulldown, PinOutput: - return pushed - } - - return false -} - -type UART struct { - Bus *tkey.UART_Type -} - -var ( - DefaultUART = UART0 - UART0 = &_UART0 - _UART0 = UART{Bus: tkey.UART} -) - -// The TKey UART is fixed at 62500 baud, 8N1. -func (uart *UART) Configure(config UARTConfig) error { - if !(config.BaudRate == 62500 || config.BaudRate == 0) { - return errors.New("uart: only 62500 baud rate is supported") - } - - return nil -} - -// Write a slice of data bytes to the UART. -func (uart *UART) Write(data []byte) (n int, err error) { - for _, c := range data { - if err := uart.WriteByte(c); err != nil { - return n, err - } - } - return len(data), nil -} - -// WriteByte writes a byte of data to the UART. -func (uart *UART) WriteByte(c byte) error { - for uart.Bus.TX_STATUS.Get() == 0 { - } - - uart.Bus.TX_DATA.Set(uint32(c)) - - return nil -} - -// Buffered returns the number of bytes buffered in the UART. -func (uart *UART) Buffered() int { - return int(uart.Bus.RX_BYTES.Get()) -} - -// ReadByte reads a byte of data from the UART. -func (uart *UART) ReadByte() (byte, error) { - for uart.Bus.RX_STATUS.Get() == 0 { - } - - return byte(uart.Bus.RX_DATA.Get()), nil -} - -// DTR is not available on the TKey. -func (uart *UART) DTR() bool { - return false -} - -// RTS is not available on the TKey. -func (uart *UART) RTS() bool { - return false -} - -// GetRNG returns 32 bits of cryptographically secure random data -func GetRNG() (uint32, error) { - for tkey.TRNG.STATUS.Get() == 0 { - } - - return uint32(tkey.TRNG.ENTROPY.Get()), nil -} - -// DesignName returns the FPGA design name. -func DesignName() (string, string) { - n0 := tkey.TK1.NAME0.Get() - name0 := string([]byte{byte(n0 >> 24), byte(n0 >> 16), byte(n0 >> 8), byte(n0)}) - n1 := tkey.TK1.NAME1.Get() - name1 := string([]byte{byte(n1 >> 24), byte(n1 >> 16), byte(n1 >> 8), byte(n1)}) - - return name0, name1 -} - -// DesignVersion returns the FPGA design version. -func DesignVersion() string { - version := tkey.TK1.VERSION.Get() - - return strconv.Itoa(int(version)) -} - -// CDI returns 8 words of Compound Device Identifier (CDI) generated and written by the firmware when the application is loaded. -func CDI() []byte { - cdi := make([]byte, 32) - for i := 0; i < 8; i++ { - c := tkey.TK1.CDI_FIRST[i].Get() - cdi[i*4] = byte(c >> 24) - cdi[i*4+1] = byte(c >> 16) - cdi[i*4+2] = byte(c >> 8) - cdi[i*4+3] = byte(c) - } - return cdi -} - -// UDI returns 2 words of Unique Device Identifier (UDI). Only available in firmware mode. -func UDI() []byte { - udi := make([]byte, 8) - for i := 0; i < 2; i++ { - c := tkey.TK1.UDI_FIRST[i].Get() - udi[i*4] = byte(c >> 24) - udi[i*4+1] = byte(c >> 16) - udi[i*4+2] = byte(c >> 8) - udi[i*4+3] = byte(c) - } - return udi -} - -// UDS returns 8 words of Unique Device Secret. Part of the FPGA design, changed when provisioning a TKey. -// Only available in firmware mode. UDS is only readable once per power cycle. -func UDS() []byte { - uds := make([]byte, 32) - for i := 0; i < 8; i++ { - c := tkey.UDS.DATA[i].Get() - uds[i*4] = byte(c >> 24) - uds[i*4+1] = byte(c >> 16) - uds[i*4+2] = byte(c >> 8) - uds[i*4+3] = byte(c) - } - return uds -} diff --git a/emb/machine/machine_tkey_rom.go b/emb/machine/machine_tkey_rom.go deleted file mode 100644 index bc7162e..0000000 --- a/emb/machine/machine_tkey_rom.go +++ /dev/null @@ -1,59 +0,0 @@ -//go:build tkey - -package machine - -/* - #define TK1_MMIO_TK1_BLAKE2S 0xff000040 - - typedef unsigned char uint8_t; - typedef unsigned long uint32_t; - typedef unsigned long size_t; - - // blake2s state context - typedef struct { - uint8_t b[64]; // input buffer - uint32_t h[8]; // chained state - uint32_t t[2]; // total number of bytes - size_t c; // pointer for b[] - size_t outlen; // digest size - } blake2s_ctx; - - typedef int (*fw_blake2s_p)(void *out, unsigned long outlen, const void *key, - unsigned long keylen, const void *in, - unsigned long inlen, blake2s_ctx *ctx); - - int blake2s(void *out, unsigned long outlen, const void *key, unsigned long keylen, const void *in, unsigned long inlen) - { - fw_blake2s_p const fw_blake2s = - (fw_blake2s_p) * (volatile uint32_t *)TK1_MMIO_TK1_BLAKE2S; - blake2s_ctx ctx; - - return fw_blake2s(out, outlen, key, keylen, in, inlen, &ctx); - } -*/ -import "C" -import ( - "errors" - "unsafe" -) - -var ( - ErrBLAKE2sInvalid = errors.New("invalid params for call to BLAKE2s") - ErrBLAKE2sFailed = errors.New("call to BLAKE2s failed") -) - -func BLAKE2s(output []byte, key []byte, input []byte) error { - if len(output) == 0 || len(input) == 0 { - return ErrBLAKE2sInvalid - } - - op := unsafe.Pointer(&output[0]) - kp := unsafe.Pointer(&key[0]) - ip := unsafe.Pointer(&input[0]) - - if res := C.blake2s(op, C.size_t(len(output)), kp, C.size_t(len(key)), ip, C.size_t(len(input))); res != 0 { - return ErrBLAKE2sFailed - } - - return nil -} diff --git a/emb/machine/spi_tx.go b/emb/machine/spi_tx.go deleted file mode 100644 index 97385bb..0000000 --- a/emb/machine/spi_tx.go +++ /dev/null @@ -1,61 +0,0 @@ -//go:build atmega || fe310 || k210 || (nxp && !mk66f18) || (stm32 && !stm32f7x2 && !stm32l5x2) - -// This file implements the SPI Tx function for targets that don't have a custom -// (faster) implementation for it. - -package machine - -// Tx handles read/write operation for SPI interface. Since SPI is a synchronous write/read -// interface, there must always be the same number of bytes written as bytes read. -// The Tx method knows about this, and offers a few different ways of calling it. -// -// This form sends the bytes in tx buffer, putting the resulting bytes read into the rx buffer. -// Note that the tx and rx buffers must be the same size: -// -// spi.Tx(tx, rx) -// -// This form sends the tx buffer, ignoring the result. Useful for sending "commands" that return zeros -// until all the bytes in the command packet have been received: -// -// spi.Tx(tx, nil) -// -// This form sends zeros, putting the result into the rx buffer. Good for reading a "result packet": -// -// spi.Tx(nil, rx) -func (spi *SPI) Tx(w, r []byte) error { - var err error - - switch { - case w == nil: - // read only, so write zero and read a result. - for i := range r { - r[i], err = spi.Transfer(0) - if err != nil { - return err - } - } - case r == nil: - // write only - for _, b := range w { - _, err = spi.Transfer(b) - if err != nil { - return err - } - } - - default: - // write/read - if len(w) != len(r) { - return ErrTxInvalidSliceSize - } - - for i, b := range w { - r[i], err = spi.Transfer(b) - if err != nil { - return err - } - } - } - - return nil -} diff --git a/emb/machine/usb.go b/emb/machine/usb.go deleted file mode 100644 index 434ee0f..0000000 --- a/emb/machine/usb.go +++ /dev/null @@ -1,338 +0,0 @@ -//go:build sam || nrf52840 || rp2040 || rp2350 - -package machine - -import ( - "machine/usb" - "machine/usb/descriptor" - - "errors" -) - -type USBDevice struct { - initcomplete bool - InitEndpointComplete bool -} - -var ( - USBDev = &USBDevice{} - USBCDC Serialer -) - -type Serialer interface { - WriteByte(c byte) error - Write(data []byte) (n int, err error) - Configure(config UARTConfig) error - Buffered() int - ReadByte() (byte, error) - DTR() bool - RTS() bool -} - -var usbDescriptor descriptor.Descriptor - -func usbVendorID() uint16 { - if usb.VendorID != 0 { - return usb.VendorID - } - - return usb_VID -} - -func usbProductID() uint16 { - if usb.ProductID != 0 { - return usb.ProductID - } - - return usb_PID -} - -func usbManufacturer() string { - if usb.Manufacturer != "" { - return usb.Manufacturer - } - - return usb_STRING_MANUFACTURER -} - -func usbProduct() string { - if usb.Product != "" { - return usb.Product - } - - return usb_STRING_PRODUCT -} - -func usbSerial() string { - if usb.Serial != "" { - return usb.Serial - } - return "" -} - -// strToUTF16LEDescriptor converts a utf8 string into a string descriptor -// note: the following code only converts ascii characters to UTF16LE. In order -// to do a "proper" conversion, we would need to pull in the 'unicode/utf16' -// package, which at the time this was written added 512 bytes to the compiled -// binary. -func strToUTF16LEDescriptor(in string, out []byte) { - out[0] = byte(len(out)) - out[1] = descriptor.TypeString - for i, rune := range in { - out[(i<<1)+2] = byte(rune) - out[(i<<1)+3] = 0 - } - return -} - -const cdcLineInfoSize = 7 - -var ( - ErrUSBReadTimeout = errors.New("USB read timeout") - ErrUSBBytesRead = errors.New("USB invalid number of bytes read") - ErrUSBBytesWritten = errors.New("USB invalid number of bytes written") -) - -var ( - usbEndpointDescriptors [NumberOfUSBEndpoints]descriptor.Device - - isEndpointHalt = false - isRemoteWakeUpEnabled = false - - usbConfiguration uint8 - usbSetInterface uint8 -) - -//go:align 4 -var udd_ep_control_cache_buffer [256]uint8 - -//go:align 4 -var udd_ep_in_cache_buffer [NumberOfUSBEndpoints][64]uint8 - -//go:align 4 -var udd_ep_out_cache_buffer [NumberOfUSBEndpoints][64]uint8 - -// usb_trans_buffer max size is 255 since that is max size -// for a descriptor (bLength is 1 byte), and the biggest use -// for this buffer is to transmit string descriptors. If -// this buffer is used for new purposes in future the length -// must be revisited. -var usb_trans_buffer [255]uint8 - -var ( - usbTxHandler [NumberOfUSBEndpoints]func() - usbRxHandler [NumberOfUSBEndpoints]func([]byte) bool - usbSetupHandler [usb.NumberOfInterfaces]func(usb.Setup) bool - usbStallHandler [NumberOfUSBEndpoints]func(usb.Setup) bool -) - -// sendDescriptor creates and sends the various USB descriptor types that -// can be requested by the host. -func sendDescriptor(setup usb.Setup) { - switch setup.WValueH { - case descriptor.TypeConfiguration: - sendUSBPacket(0, usbDescriptor.Configuration, setup.WLength) - return - case descriptor.TypeDevice: - usbDescriptor.Configure(usbVendorID(), usbProductID()) - sendUSBPacket(0, usbDescriptor.Device, setup.WLength) - return - - case descriptor.TypeString: - switch setup.WValueL { - case 0: - usb_trans_buffer[0] = 0x04 - usb_trans_buffer[1] = 0x03 - usb_trans_buffer[2] = 0x09 - usb_trans_buffer[3] = 0x04 - sendUSBPacket(0, usb_trans_buffer[:4], setup.WLength) - - case usb.IPRODUCT: - b := usb_trans_buffer[:(len(usbProduct())<<1)+2] - strToUTF16LEDescriptor(usbProduct(), b) - sendUSBPacket(0, b, setup.WLength) - - case usb.IMANUFACTURER: - b := usb_trans_buffer[:(len(usbManufacturer())<<1)+2] - strToUTF16LEDescriptor(usbManufacturer(), b) - sendUSBPacket(0, b, setup.WLength) - - case usb.ISERIAL: - sz := len(usbSerial()) - if sz == 0 { - SendZlp() - } else { - b := usb_trans_buffer[:(sz<<1)+2] - strToUTF16LEDescriptor(usbSerial(), b) - sendUSBPacket(0, b, setup.WLength) - } - } - return - case descriptor.TypeHIDReport: - if h, ok := usbDescriptor.HID[setup.WIndex]; ok { - sendUSBPacket(0, h, setup.WLength) - return - } - case descriptor.TypeDeviceQualifier: - // skip - default: - } - - // do not know how to handle this message, so return zero - SendZlp() - return -} - -func handleStandardSetup(setup usb.Setup) bool { - switch setup.BRequest { - case usb.GET_STATUS: - usb_trans_buffer[0] = 0 - usb_trans_buffer[1] = 0 - - if setup.BmRequestType != 0 { // endpoint - if isEndpointHalt { - usb_trans_buffer[0] = 1 - } - } - - sendUSBPacket(0, usb_trans_buffer[:2], setup.WLength) - return true - - case usb.CLEAR_FEATURE: - if setup.WValueL == 1 { // DEVICEREMOTEWAKEUP - isRemoteWakeUpEnabled = false - } else if setup.WValueL == 0 { // ENDPOINTHALT - if idx := setup.WIndex & 0x7F; idx < NumberOfUSBEndpoints && usbStallHandler[idx] != nil { - // Host has requested to clear an endpoint stall. If the request is addressed to - // an endpoint with a configured StallHandler, forward the message on. - // The 0x7F mask is used to clear the direction bit from the endpoint number - return usbStallHandler[idx](setup) - } - isEndpointHalt = false - } - SendZlp() - return true - - case usb.SET_FEATURE: - if setup.WValueL == 1 { // DEVICEREMOTEWAKEUP - isRemoteWakeUpEnabled = true - } else if setup.WValueL == 0 { // ENDPOINTHALT - if idx := setup.WIndex & 0x7F; idx < NumberOfUSBEndpoints && usbStallHandler[idx] != nil { - // Host has requested to stall an endpoint. If the request is addressed to - // an endpoint with a configured StallHandler, forward the message on. - // The 0x7F mask is used to clear the direction bit from the endpoint number - return usbStallHandler[idx](setup) - } - isEndpointHalt = true - } - SendZlp() - return true - - case usb.SET_ADDRESS: - return handleUSBSetAddress(setup) - - case usb.GET_DESCRIPTOR: - sendDescriptor(setup) - return true - - case usb.SET_DESCRIPTOR: - return false - - case usb.GET_CONFIGURATION: - usb_trans_buffer[0] = usbConfiguration - sendUSBPacket(0, usb_trans_buffer[:1], setup.WLength) - return true - - case usb.SET_CONFIGURATION: - if setup.BmRequestType&usb.REQUEST_RECIPIENT == usb.REQUEST_DEVICE { - for i := 1; i < len(endPoints); i++ { - initEndpoint(uint32(i), endPoints[i]) - } - - usbConfiguration = setup.WValueL - USBDev.InitEndpointComplete = true - - SendZlp() - return true - } else { - return false - } - - case usb.GET_INTERFACE: - usb_trans_buffer[0] = usbSetInterface - sendUSBPacket(0, usb_trans_buffer[:1], setup.WLength) - return true - - case usb.SET_INTERFACE: - usbSetInterface = setup.WValueL - - SendZlp() - return true - - default: - return true - } -} - -func EnableCDC(txHandler func(), rxHandler func([]byte), setupHandler func(usb.Setup) bool) { - if len(usbDescriptor.Device) == 0 { - usbDescriptor = descriptor.CDC - } - // Initialization of endpoints is required even for non-CDC - ConfigureUSBEndpoint(usbDescriptor, - []usb.EndpointConfig{ - { - Index: usb.CDC_ENDPOINT_ACM, - IsIn: true, - Type: usb.ENDPOINT_TYPE_INTERRUPT, - }, - { - Index: usb.CDC_ENDPOINT_OUT, - IsIn: false, - Type: usb.ENDPOINT_TYPE_BULK, - RxHandler: rxHandler, - }, - { - Index: usb.CDC_ENDPOINT_IN, - IsIn: true, - Type: usb.ENDPOINT_TYPE_BULK, - TxHandler: txHandler, - }, - }, - []usb.SetupConfig{ - { - Index: usb.CDC_ACM_INTERFACE, - Handler: setupHandler, - }, - }) -} - -func ConfigureUSBEndpoint(desc descriptor.Descriptor, epSettings []usb.EndpointConfig, setup []usb.SetupConfig) { - usbDescriptor = desc - - for _, ep := range epSettings { - if ep.IsIn { - endPoints[ep.Index] = uint32(ep.Type | usb.EndpointIn) - if ep.TxHandler != nil { - usbTxHandler[ep.Index] = ep.TxHandler - } - } else { - endPoints[ep.Index] = uint32(ep.Type | usb.EndpointOut) - if ep.RxHandler != nil { - usbRxHandler[ep.Index] = func(b []byte) bool { - ep.RxHandler(b) - return true - } - } else if ep.DelayRxHandler != nil { - usbRxHandler[ep.Index] = ep.DelayRxHandler - } - } - if ep.StallHandler != nil { - usbStallHandler[ep.Index] = ep.StallHandler - } - } - - for _, s := range setup { - usbSetupHandler[s.Index] = s.Handler - } -} diff --git a/emb/machine/virt.go b/emb/machine/virt.go deleted file mode 100644 index 2b28ae6..0000000 --- a/emb/machine/virt.go +++ /dev/null @@ -1,189 +0,0 @@ -//go:build tinygo.riscv32 && virt - -// Machine implementation for VirtIO targets. -// At the moment only QEMU RISC-V is supported, but support for ARM for example -// should not be difficult to add with a change to virtioFindDevice. - -package machine - -import ( - "errors" - "runtime/volatile" - "sync" - "unsafe" -) - -const deviceName = "riscv-qemu" - -func (p Pin) Set(high bool) { - // no pins defined -} - -var rngLock sync.Mutex -var rngDevice *virtioDevice1 -var rngBuf volatile.Register32 - -var errNoRNG = errors.New("machine: no entropy source found") -var errNoRNGData = errors.New("machine: entropy source didn't return enough data") - -// GetRNG returns random numbers from a VirtIO entropy source. -// When running in QEMU, it requires adding the RNG device: -// -// -device virtio-rng-device -func GetRNG() (uint32, error) { - rngLock.Lock() - - // Initialize the device on first use. - if rngDevice == nil { - // Search for an available RNG. - rngDevice = virtioFindDevice(virtioDeviceEntropySource) - if rngDevice == nil { - rngLock.Unlock() - return 0, errNoRNG - } - - // Initialize the device. - rngDevice.status.Set(0) // reset device - rngDevice.status.Set(virtioDeviceStatusAcknowledge) - rngDevice.status.Set(virtioDeviceStatusAcknowledge | virtioDeviceStatusDriver) - rngDevice.hostFeaturesSel.Set(0) - rngDevice.status.Set(virtioDeviceStatusAcknowledge | virtioDeviceStatusDriver | virtioDeviceStatusDriverOk) - rngDevice.guestPageSize.Set(4096) - - // Configure queue, according to section 4.2.4 "Legacy interface". - // Note: we're skipping checks for queuePFM and queueNumMax. - rngDevice.queueSel.Set(0) // use queue 0 (the only queue) - rngDevice.queueNum.Set(1) // use a single buffer in the queue - rngDevice.queueAlign.Set(4096) // default alignment appears to be 4096 - rngDevice.queuePFN.Set(uint32(uintptr(unsafe.Pointer(&rngQueue))) / 4096) - - // Configure the only buffer in the queue (but don't increment - // rngQueue.available yet). - rngQueue.buffers[0].address = uint64(uintptr(unsafe.Pointer(&rngBuf))) - rngQueue.buffers[0].length = uint32(unsafe.Sizeof(rngBuf)) - rngQueue.buffers[0].flags = 2 // 2 means write-only buffer - } - - // Increment the available ring buffer. This doesn't actually change the - // buffer index (it's a ring with a single entry), but the number needs to - // be incremented otherwise the device won't recognize a new buffer. - index := rngQueue.available.index - rngQueue.available.index = index + 1 - rngDevice.queueNotify.Set(0) // notify the device of the 'new' (reused) buffer - for rngQueue.used.index.Get() != index+1 { - // Busy wait until the RNG buffer is filled. - // A better way would be to wait for an interrupt, but since this driver - // implementation is mostly used for testing it's good enough for now. - } - - // Check that we indeed got 4 bytes back. - if rngQueue.used.ring[0].length != 4 { - rngLock.Unlock() - return 0, errNoRNGData - } - - // Read the resulting random numbers. - result := rngBuf.Get() - - rngLock.Unlock() - - return result, nil -} - -// Implement a driver for the VirtIO entropy device. -// https://docs.oasis-open.org/virtio/virtio/v1.2/csd01/virtio-v1.2-csd01.html -// http://wiki.osdev.org/Virtio -// http://www.dumais.io/index.php?article=aca38a9a2b065b24dfa1dee728062a12 - -const ( - virtioDeviceStatusAcknowledge = 1 - virtioDeviceStatusDriver = 2 - virtioDeviceStatusDriverOk = 4 - virtioDeviceStatusFeaturesOk = 8 - virtioDeviceStatusFailed = 128 -) - -const ( - virtioDeviceReserved = iota - virtioDeviceNetworkCard - virtioDeviceBlockDevice - virtioDeviceConsole - virtioDeviceEntropySource - // there are more device types -) - -// VirtIO device version 1 -type virtioDevice1 struct { - magic volatile.Register32 // always 0x74726976 - version volatile.Register32 - deviceID volatile.Register32 - vendorID volatile.Register32 - hostFeatures volatile.Register32 - hostFeaturesSel volatile.Register32 - _ [2]uint32 - guestFeatures volatile.Register32 - guestFeaturesSel volatile.Register32 - guestPageSize volatile.Register32 - _ uint32 - queueSel volatile.Register32 - queueNumMax volatile.Register32 - queueNum volatile.Register32 - queueAlign volatile.Register32 - queuePFN volatile.Register32 - _ [3]uint32 - queueNotify volatile.Register32 - _ [3]uint32 - interruptStatus volatile.Register32 - interruptAck volatile.Register32 - _ [2]uint32 - status volatile.Register32 -} - -// VirtIO queue, with a single buffer. -type virtioQueue struct { - buffers [1]struct { - address uint64 - length uint32 - flags uint16 - next uint16 - } // 16 bytes - - available struct { - flags uint16 - index uint16 - ring [1]uint16 - eventIndex uint16 - } // 8 bytes - - _ [4096 - 16*1 - 8*1]byte // padding (to align on a 4096 byte boundary) - - used struct { - flags uint16 - index volatile.Register16 - ring [1]struct { - index uint32 - length uint32 - } - availEvent uint16 - } -} - -func virtioFindDevice(deviceID uint32) *virtioDevice1 { - // On RISC-V, QEMU defines 8 VirtIO devices starting at 0x10001000 and - // repeating every 0x1000 bytes. - // The memory map can be seen in the QEMU source code: - // https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c - for i := 0; i < 8; i++ { - dev := (*virtioDevice1)(unsafe.Pointer(uintptr(0x10001000 + i*0x1000))) - if dev.magic.Get() != 0x74726976 || dev.version.Get() != 1 || dev.deviceID.Get() != deviceID { - continue - } - return dev - } - return nil -} - -// A VirtIO queue needs to be page-aligned. -// -//go:align 4096 -var rngQueue virtioQueue diff --git a/emb/machine/watchdog.go b/emb/machine/watchdog.go deleted file mode 100644 index 7dbf676..0000000 --- a/emb/machine/watchdog.go +++ /dev/null @@ -1,34 +0,0 @@ -//go:build nrf52840 || nrf52833 || rp2040 || rp2350 || atsamd21 || atsamd51 || atsame5x || stm32 - -package machine - -// WatchdogConfig holds configuration for the watchdog timer. -type WatchdogConfig struct { - // The timeout (in milliseconds) before the watchdog fires. - // - // If the requested timeout exceeds `MaxTimeout` it will be rounded - // down. - TimeoutMillis uint32 -} - -// watchdog must be implemented by any platform supporting watchdog functionality -type watchdog interface { - // Configure the watchdog. - // - // This method should not be called after the watchdog is started and on - // some platforms attempting to reconfigure after starting the watchdog - // is explicitly forbidden / will not work. - Configure(config WatchdogConfig) error - - // Starts the watchdog. - Start() error - - // Update the watchdog, indicating that the app is healthy. - Update() -} - -// Ensure required public symbols var exists and meets interface spec -var _ = watchdog(Watchdog) - -// Ensure required public constants exist -const _ = WatchdogMaxTimeout From 1abd99a7f3e9187327f2e0e68e0e12ca54d289cd Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Wed, 10 Sep 2025 22:53:08 +0800 Subject: [PATCH 02/10] restore coreboard-v2 --- emb/machine/board_esp32-coreboard-v2.go | 88 +++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 emb/machine/board_esp32-coreboard-v2.go diff --git a/emb/machine/board_esp32-coreboard-v2.go b/emb/machine/board_esp32-coreboard-v2.go new file mode 100644 index 0000000..044d906 --- /dev/null +++ b/emb/machine/board_esp32-coreboard-v2.go @@ -0,0 +1,88 @@ +//go:build esp32_coreboard_v2 + +package machine + +const ( + CLK = GPIO6 + CMD = GPIO11 + IO0 = GPIO0 + IO1 = GPIO1 + IO2 = GPIO2 + IO3 = GPIO3 + IO4 = GPIO4 + IO5 = GPIO5 + IO9 = GPIO9 + IO10 = GPIO10 + IO16 = GPIO16 + IO17 = GPIO17 + IO18 = GPIO18 + IO19 = GPIO19 + IO21 = GPIO21 + IO22 = GPIO22 + IO23 = GPIO23 + IO25 = GPIO25 + IO26 = GPIO26 + IO27 = GPIO27 + IO32 = GPIO32 + IO33 = GPIO33 + IO34 = GPIO34 + IO35 = GPIO35 + IO36 = GPIO36 + IO39 = GPIO39 + RXD = GPIO3 + SD0 = GPIO7 + SD1 = GPIO8 + SD2 = GPIO9 + SD3 = GPIO10 + SVN = GPIO39 + SVP = GPIO36 + TCK = GPIO13 + TD0 = GPIO15 + TDI = GPIO12 + TMS = GPIO14 + TXD = GPIO1 +) + +// Built-in LED on some ESP32 boards. +const LED = IO2 + +// SPI pins +const ( + SPI0_SCK_PIN = IO18 + SPI0_SDO_PIN = IO23 + SPI0_SDI_PIN = IO19 + SPI0_CS0_PIN = IO5 +) + +// I2C pins +const ( + SDA_PIN = IO21 + SCL_PIN = IO22 +) + +// ADC pins +const ( + ADC0 Pin = IO34 + ADC1 Pin = IO35 + ADC2 Pin = IO36 + ADC3 Pin = IO39 +) + +// UART0 pins +const ( + UART_TX_PIN = IO1 + UART_RX_PIN = IO3 +) + +// UART1 pins +const ( + UART1_TX_PIN = IO9 + UART1_RX_PIN = IO10 +) + +// PWM pins +const ( + PWM0_PIN Pin = IO2 + PWM1_PIN Pin = IO0 + PWM2_PIN Pin = IO4 +) From d89c0635250b28bdf1530c39ff02f7fdb85107e6 Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Wed, 10 Sep 2025 23:03:52 +0800 Subject: [PATCH 03/10] device --- emb/device/arm/arm.go | 216 + emb/device/arm/cortexm.S | 37 + emb/device/arm/interrupts.c | 22 + emb/device/arm/scb.go | 440 + emb/device/arm/semihosting.go | 65 + emb/device/arm64/arm64.go | 36 + emb/device/asm.go | 21 + emb/device/esp/esp32.S | 57 + emb/device/esp/esp32.go | 80119 ++++++++++ emb/device/esp/esp32c2.go | 34249 +++++ emb/device/esp/esp32c3.S | 67 + emb/device/esp/esp32c3.go | 54203 +++++++ emb/device/esp/esp32c6.go | 103000 +++++++++++++ emb/device/esp/esp32c6lp.go | 9803 ++ emb/device/esp/esp32h2.go | 79652 ++++++++++ emb/device/esp/esp32p4.go | 203958 ++++++++++++++++++++++++++ emb/device/esp/esp32s2.go | 81478 ++++++++++ emb/device/esp/esp32s2ulp.go | 5212 + emb/device/esp/esp32s3.go | 113964 ++++++++++++++ emb/device/esp/esp32s3ulp.go | 6647 + emb/device/esp/esp8266.S | 6 + emb/device/esp/esp8266.go | 10874 ++ emb/device/riscv/csr.go | 335 + emb/device/riscv/handleinterrupt.S | 130 + emb/device/riscv/riscv.go | 38 + emb/device/riscv/start.S | 59 + 26 files changed, 784688 insertions(+) create mode 100644 emb/device/arm/arm.go create mode 100644 emb/device/arm/cortexm.S create mode 100644 emb/device/arm/interrupts.c create mode 100644 emb/device/arm/scb.go create mode 100644 emb/device/arm/semihosting.go create mode 100644 emb/device/arm64/arm64.go create mode 100644 emb/device/asm.go create mode 100644 emb/device/esp/esp32.S create mode 100644 emb/device/esp/esp32.go create mode 100644 emb/device/esp/esp32c2.go create mode 100644 emb/device/esp/esp32c3.S create mode 100644 emb/device/esp/esp32c3.go create mode 100644 emb/device/esp/esp32c6.go create mode 100644 emb/device/esp/esp32c6lp.go create mode 100644 emb/device/esp/esp32h2.go create mode 100644 emb/device/esp/esp32p4.go create mode 100644 emb/device/esp/esp32s2.go create mode 100644 emb/device/esp/esp32s2ulp.go create mode 100644 emb/device/esp/esp32s3.go create mode 100644 emb/device/esp/esp32s3ulp.go create mode 100644 emb/device/esp/esp8266.S create mode 100644 emb/device/esp/esp8266.go create mode 100644 emb/device/riscv/csr.go create mode 100644 emb/device/riscv/handleinterrupt.S create mode 100644 emb/device/riscv/riscv.go create mode 100644 emb/device/riscv/start.S diff --git a/emb/device/arm/arm.go b/emb/device/arm/arm.go new file mode 100644 index 0000000..1f26b7f --- /dev/null +++ b/emb/device/arm/arm.go @@ -0,0 +1,216 @@ +// CMSIS abstraction functions. +// +// Original copyright: +// +// Copyright (c) 2009 - 2015 ARM LIMITED +// +// All rights reserved. +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// - Neither the name of ARM nor the names of its contributors may be used +// to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +package arm + +import "C" +import ( + "errors" + "runtime/volatile" + "unsafe" +) + +var errCycleCountTooLarge = errors.New("requested cycle count is too large, overflows 24 bit counter") + +// Run the given assembly code. The code will be marked as having side effects, +// as it doesn't produce output and thus would normally be eliminated by the +// optimizer. +func Asm(asm string) + +// Run the given inline assembly. The code will be marked as having side +// effects, as it would otherwise be optimized away. The inline assembly string +// recognizes template values in the form {name}, like so: +// +// arm.AsmFull( +// "str {value}, {result}", +// map[string]interface{}{ +// "value": 1 +// "result": &dest, +// }) +// +// You can use {} in the asm string (which expands to a register) to set the +// return value. +func AsmFull(asm string, regs map[string]interface{}) uintptr + +// Run the following system call (SVCall) with 0 arguments. +func SVCall0(num uintptr) uintptr + +// Run the following system call (SVCall) with 1 argument. +func SVCall1(num uintptr, a1 interface{}) uintptr + +// Run the following system call (SVCall) with 2 arguments. +func SVCall2(num uintptr, a1, a2 interface{}) uintptr + +// Run the following system call (SVCall) with 3 arguments. +func SVCall3(num uintptr, a1, a2, a3 interface{}) uintptr + +// Run the following system call (SVCall) with 4 arguments. +func SVCall4(num uintptr, a1, a2, a3, a4 interface{}) uintptr + +const ( + SCS_BASE = 0xE000E000 + SYST_BASE = SCS_BASE + 0x0010 + NVIC_BASE = SCS_BASE + 0x0100 +) + +// Nested Vectored Interrupt Controller (NVIC). +// +// Source: +// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CIHIGCIF.html +type NVIC_Type struct { + ISER [8]volatile.Register32 // Interrupt Set-enable Registers + _ [24]uint32 + ICER [8]volatile.Register32 // Interrupt Clear-enable Registers + _ [24]uint32 + ISPR [8]volatile.Register32 // Interrupt Set-pending Registers + _ [24]uint32 + ICPR [8]volatile.Register32 // Interrupt Clear-pending Registers + _ [24]uint32 + IABR [8]volatile.Register32 // Interrupt Active Bit Registers + _ [56]uint32 + IPR [60]volatile.Register32 // Interrupt Priority Registers +} + +var NVIC = (*NVIC_Type)(unsafe.Pointer(uintptr(NVIC_BASE))) + +// System Timer (SYST) +// +// Source: https://static.docs.arm.com/ddi0403/e/DDI0403E_d_armv7m_arm.pdf B3.3 +type SYST_Type struct { + SYST_CSR volatile.Register32 + SYST_RVR volatile.Register32 + SYST_CVR volatile.Register32 + SYST_CALIB volatile.Register32 +} + +var SYST = (*SYST_Type)(unsafe.Pointer(uintptr(SYST_BASE))) + +// Bitfields for SYST: System Timer +const ( + // SYST.SYST_CSR: SysTick Control and Status Register + SYST_CSR_ENABLE_Pos = 0x0 // Position of ENABLE field. + SYST_CSR_ENABLE_Msk = 0x1 // Bit mask of ENABLE field. + SYST_CSR_ENABLE = 0x1 // Bit ENABLE. + SYST_CSR_TICKINT_Pos = 0x1 // Position of TICKINT field. + SYST_CSR_TICKINT_Msk = 0x2 // Bit mask of TICKINT field. + SYST_CSR_TICKINT = 0x2 // Bit TICKINT. + SYST_CSR_CLKSOURCE_Pos = 0x2 // Position of CLKSOURCE field. + SYST_CSR_CLKSOURCE_Msk = 0x4 // Bit mask of CLKSOURCE field. + SYST_CSR_CLKSOURCE = 0x4 // Bit CLKSOURCE. + SYST_CSR_COUNTFLAG_Pos = 0x10 // Position of COUNTFLAG field. + SYST_CSR_COUNTFLAG_Msk = 0x10000 // Bit mask of COUNTFLAG field. + SYST_CSR_COUNTFLAG = 0x10000 // Bit COUNTFLAG. + + // SYST.SYST_RVR: SysTick Reload Value Register + SYST_RVR_RELOAD_Pos = 0x0 // Position of RELOAD field. + SYST_RVR_RELOAD_Msk = 0xffffff // Bit mask of RELOAD field. + + // SYST.SYST_CVR: SysTick Current Value Register + SYST_CVR_CURRENT_Pos = 0x0 // Position of CURRENT field. + SYST_CVR_CURRENT_Msk = 0xffffff // Bit mask of CURRENT field. + + // SYST.SYST_CALIB: SysTick Calibration Value Register + SYST_CALIB_TENMS_Pos = 0x0 // Position of TENMS field. + SYST_CALIB_TENMS_Msk = 0xffffff // Bit mask of TENMS field. + SYST_CALIB_SKEW_Pos = 0x1e // Position of SKEW field. + SYST_CALIB_SKEW_Msk = 0x40000000 // Bit mask of SKEW field. + SYST_CALIB_SKEW = 0x40000000 // Bit SKEW. + SYST_CALIB_NOREF_Pos = 0x1f // Position of NOREF field. + SYST_CALIB_NOREF_Msk = 0x80000000 // Bit mask of NOREF field. + SYST_CALIB_NOREF = 0x80000000 // Bit NOREF. +) + +// ClearPendingIRQ clears the pending status of the interrupt. +func ClearPendingIRQ(irq uint32) { + NVIC.ICPR[irq>>5].Set(1 << (irq & 0x1F)) +} + +// Enable the given interrupt number. +func EnableIRQ(irq uint32) { + NVIC.ISER[irq>>5].Set(1 << (irq & 0x1F)) +} + +// Disable the given interrupt number. +func DisableIRQ(irq uint32) { + NVIC.ICER[irq>>5].Set(1 << (irq & 0x1F)) +} + +// Set the priority of the given interrupt number. +// Note that the priority is given as a 0-255 number, where some of the lower +// bits are not implemented by the hardware. For example, to set a low interrupt +// priority, use 0xc0, which is equivalent to using priority level 5 when the +// hardware has 8 priority levels. Also note that the priority level is inverted +// in ARM: a lower number means it is a more important interrupt and will +// interrupt ISRs with a higher interrupt priority. +func SetPriority(irq uint32, priority uint32) { + // Details: + // http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/Cihgjeed.html + regnum := irq / 4 + regpos := irq % 4 + mask := uint32(0xff) << (regpos * 8) // bits to clear + priority = priority << (regpos * 8) // bits to set + NVIC.IPR[regnum].Set((uint32(NVIC.IPR[regnum].Get()) &^ mask) | priority) +} + +// DisableInterrupts disables all interrupts, and returns the old interrupt +// state. +// +//export DisableInterrupts +func DisableInterrupts() uintptr + +// EnableInterrupts enables all interrupts again. The value passed in must be +// the mask returned by DisableInterrupts. +// +//export EnableInterrupts +func EnableInterrupts(mask uintptr) + +// Set up the system timer to generate periodic tick events. +// This will cause SysTick_Handler to fire once per tick. +// The cyclecount parameter is a counter value which can range from 0 to +// 0xffffff. A value of 0 disables the timer. +func SetupSystemTimer(cyclecount uint32) error { + // turn it off + SYST.SYST_CSR.ClearBits(SYST_CSR_TICKINT | SYST_CSR_ENABLE) + if cyclecount == 0 { + // leave the system timer turned off. + return nil + } + if cyclecount&SYST_RVR_RELOAD_Msk != cyclecount { + // The cycle refresh register is only 24 bits wide. The user-specified value will overflow. + return errCycleCountTooLarge + } + + // set refresh count + SYST.SYST_RVR.Set(cyclecount) + // set current counter value + SYST.SYST_CVR.Set(cyclecount) + // enable clock, enable SysTick interrupt when clock reaches 0, run it off of the processor clock + SYST.SYST_CSR.SetBits(SYST_CSR_TICKINT | SYST_CSR_ENABLE | SYST_CSR_CLKSOURCE) + return nil +} diff --git a/emb/device/arm/cortexm.S b/emb/device/arm/cortexm.S new file mode 100644 index 0000000..e9b15aa --- /dev/null +++ b/emb/device/arm/cortexm.S @@ -0,0 +1,37 @@ +.syntax unified +.cfi_sections .debug_frame + +.section .text.HardFault_Handler +.global HardFault_Handler +.type HardFault_Handler, %function +HardFault_Handler: + .cfi_startproc + // Put the old stack pointer in the first argument, for easy debugging. This + // is especially useful on Cortex-M0, which supports far fewer debug + // facilities. + mov r0, sp + + // Load the default stack pointer from address 0 so that we can call normal + // functions again that expect a working stack. However, it will corrupt the + // old stack so the function below must not attempt to recover from this + // fault. + movs r3, #0 + ldr r3, [r3] + mov sp, r3 + + // Continue handling this error in Go. + bl handleHardFault + .cfi_endproc +.size HardFault_Handler, .-HardFault_Handler + +// This is a convenience function for semihosting support. +// At some point, this should be replaced by inline assembly. +.section .text.SemihostingCall +.global SemihostingCall +.type SemihostingCall, %function +SemihostingCall: + .cfi_startproc + bkpt 0xab + bx lr + .cfi_endproc +.size SemihostingCall, .-SemihostingCall diff --git a/emb/device/arm/interrupts.c b/emb/device/arm/interrupts.c new file mode 100644 index 0000000..d94a313 --- /dev/null +++ b/emb/device/arm/interrupts.c @@ -0,0 +1,22 @@ +#include + +void EnableInterrupts(uintptr_t mask) { + asm volatile( + "msr PRIMASK, %0" + : + : "r"(mask) + : "memory" + ); +} + +uintptr_t DisableInterrupts() { + uintptr_t mask; + asm volatile( + "mrs %0, PRIMASK\n\t" + "cpsid i" + : "=r"(mask) + : + : "memory" + ); + return mask; +} \ No newline at end of file diff --git a/emb/device/arm/scb.go b/emb/device/arm/scb.go new file mode 100644 index 0000000..528b7cb --- /dev/null +++ b/emb/device/arm/scb.go @@ -0,0 +1,440 @@ +// Hand created file. DO NOT DELETE. +// Cortex-M System Control Block-related definitions. + +//go:build cortexm + +package arm + +import ( + "runtime/volatile" + "unsafe" +) + +const SCB_BASE = SCS_BASE + 0x0D00 + +// System Control Block (SCB) +// +// SCB_Type provides the definitions for the System Control Block Registers. +type SCB_Type struct { + CPUID volatile.Register32 // 0xD00: CPUID Base Register + ICSR volatile.Register32 // 0xD04: Interrupt Control and State Register + VTOR volatile.Register32 // 0xD08: Vector Table Offset Register + AIRCR volatile.Register32 // 0xD0C: Application Interrupt and Reset Control Register + SCR volatile.Register32 // 0xD10: System Control Register + CCR volatile.Register32 // 0xD14: Configuration and Control Register + SHPR1 volatile.Register32 // 0xD18: System Handler Priority Register 1 (Cortex-M3/M33/M4/M7 only) + SHPR2 volatile.Register32 // 0xD1C: System Handler Priority Register 2 + SHPR3 volatile.Register32 // 0xD20: System Handler Priority Register 3 + // the following are only applicable for Cortex-M3/M33/M4/M7 + SHCSR volatile.Register32 // 0xD24: System Handler Control and State Register + CFSR volatile.Register32 // 0xD28: Configurable Fault Status Register + HFSR volatile.Register32 // 0xD2C: HardFault Status Register + DFSR volatile.Register32 // 0xD30: Debug Fault Status Register + MMFAR volatile.Register32 // 0xD34: MemManage Fault Address Register + BFAR volatile.Register32 // 0xD38: BusFault Address Register + AFSR volatile.Register32 // 0xD3C: Auxiliary Fault Status Register + PFR [2]volatile.Register32 // 0xD40: Processor Feature Register + DFR volatile.Register32 // 0xD48: Debug Feature Register + ADR volatile.Register32 // 0xD4C: Auxiliary Feature Register + MMFR [4]volatile.Register32 // 0xD50: Memory Model Feature Register + ISAR [5]volatile.Register32 // 0xD60: Instruction Set Attributes Register + _ [5]uint32 // reserved + CPACR volatile.Register32 // 0xD88: Coprocessor Access Control Register + +} + +var SCB = (*SCB_Type)(unsafe.Pointer(uintptr(SCB_BASE))) + +// SystemReset performs a hard system reset. +func SystemReset() { + SCB.AIRCR.Set((0x5FA << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk) + for { + Asm("wfi") + } +} + +const ( + // CPUID: CPUID Base Register + SCB_CPUID_REVISION_Pos = 0x0 // Position of REVISION field. + SCB_CPUID_REVISION_Msk = 0xf // Bit mask of REVISION field. + SCB_CPUID_PARTNO_Pos = 0x4 // Position of PARTNO field. + SCB_CPUID_PARTNO_Msk = 0xfff0 // Bit mask of PARTNO field. + SCB_CPUID_ARCHITECTURE_Pos = 0x10 // Position of ARCHITECTURE field. + SCB_CPUID_ARCHITECTURE_Msk = 0xf0000 // Bit mask of ARCHITECTURE field. + SCB_CPUID_VARIANT_Pos = 0x14 // Position of VARIANT field. + SCB_CPUID_VARIANT_Msk = 0xf00000 // Bit mask of VARIANT field. + SCB_CPUID_IMPLEMENTER_Pos = 0x18 // Position of IMPLEMENTER field. + SCB_CPUID_IMPLEMENTER_Msk = 0xff000000 // Bit mask of IMPLEMENTER field. + + // ICSR: Interrupt Control and State Register + SCB_ICSR_VECTACTIVE_Pos = 0x0 // Position of VECTACTIVE field. + SCB_ICSR_VECTACTIVE_Msk = 0x1ff // Bit mask of VECTACTIVE field. + SCB_ICSR_RETTOBASE_Pos = 0xb // Position of RETTOBASE field. + SCB_ICSR_RETTOBASE_Msk = 0x800 // Bit mask of RETTOBASE field. + SCB_ICSR_RETTOBASE = 0x800 // Bit RETTOBASE. + SCB_ICSR_RETTOBASE_RETTOBASE_0 = 0x0 // there are preempted active exceptions to execute + SCB_ICSR_RETTOBASE_RETTOBASE_1 = 0x1 // there are no active exceptions, or the currently-executing exception is the only active exception + SCB_ICSR_VECTPENDING_Pos = 0xc // Position of VECTPENDING field. + SCB_ICSR_VECTPENDING_Msk = 0x1ff000 // Bit mask of VECTPENDING field. + SCB_ICSR_ISRPENDING_Pos = 0x16 // Position of ISRPENDING field. + SCB_ICSR_ISRPENDING_Msk = 0x400000 // Bit mask of ISRPENDING field. + SCB_ICSR_ISRPENDING = 0x400000 // Bit ISRPENDING. + SCB_ICSR_ISRPENDING_ISRPENDING_0 = 0x0 // No external interrupt pending. + SCB_ICSR_ISRPENDING_ISRPENDING_1 = 0x1 // External interrupt pending. + SCB_ICSR_PENDSTCLR_Pos = 0x19 // Position of PENDSTCLR field. + SCB_ICSR_PENDSTCLR_Msk = 0x2000000 // Bit mask of PENDSTCLR field. + SCB_ICSR_PENDSTCLR = 0x2000000 // Bit PENDSTCLR. + SCB_ICSR_PENDSTCLR_PENDSTCLR_0 = 0x0 // no effect + SCB_ICSR_PENDSTCLR_PENDSTCLR_1 = 0x1 // removes the pending state from the SysTick exception + SCB_ICSR_PENDSTSET_Pos = 0x1a // Position of PENDSTSET field. + SCB_ICSR_PENDSTSET_Msk = 0x4000000 // Bit mask of PENDSTSET field. + SCB_ICSR_PENDSTSET = 0x4000000 // Bit PENDSTSET. + SCB_ICSR_PENDSTSET_PENDSTSET_0 = 0x0 // write: no effect; read: SysTick exception is not pending + SCB_ICSR_PENDSTSET_PENDSTSET_1 = 0x1 // write: changes SysTick exception state to pending; read: SysTick exception is pending + SCB_ICSR_PENDSVCLR_Pos = 0x1b // Position of PENDSVCLR field. + SCB_ICSR_PENDSVCLR_Msk = 0x8000000 // Bit mask of PENDSVCLR field. + SCB_ICSR_PENDSVCLR = 0x8000000 // Bit PENDSVCLR. + SCB_ICSR_PENDSVCLR_PENDSVCLR_0 = 0x0 // no effect + SCB_ICSR_PENDSVCLR_PENDSVCLR_1 = 0x1 // removes the pending state from the PendSV exception + SCB_ICSR_PENDSVSET_Pos = 0x1c // Position of PENDSVSET field. + SCB_ICSR_PENDSVSET_Msk = 0x10000000 // Bit mask of PENDSVSET field. + SCB_ICSR_PENDSVSET = 0x10000000 // Bit PENDSVSET. + SCB_ICSR_PENDSVSET_PENDSVSET_0 = 0x0 // write: no effect; read: PendSV exception is not pending + SCB_ICSR_PENDSVSET_PENDSVSET_1 = 0x1 // write: changes PendSV exception state to pending; read: PendSV exception is pending + SCB_ICSR_NMIPENDSET_Pos = 0x1f // Position of NMIPENDSET field. + SCB_ICSR_NMIPENDSET_Msk = 0x80000000 // Bit mask of NMIPENDSET field. + SCB_ICSR_NMIPENDSET = 0x80000000 // Bit NMIPENDSET. + SCB_ICSR_NMIPENDSET_NMIPENDSET_0 = 0x0 // write: no effect; read: NMI exception is not pending + SCB_ICSR_NMIPENDSET_NMIPENDSET_1 = 0x1 // write: changes NMI exception state to pending; read: NMI exception is pending + + // VTOR: Vector Table Offset Register + SCB_VTOR_TBLOFF_Pos = 0x7 // Position of TBLOFF field. + SCB_VTOR_TBLOFF_Msk = 0xffffff80 // Bit mask of TBLOFF field. + + // AIRCR: Application Interrupt and Reset Control Register + SCB_AIRCR_VECTRESET_Pos = 0x0 // Position of VECTRESET field. + SCB_AIRCR_VECTRESET_Msk = 0x1 // Bit mask of VECTRESET field. + SCB_AIRCR_VECTRESET = 0x1 // Bit VECTRESET. + SCB_AIRCR_VECTRESET_VECTRESET_0 = 0x0 // No change + SCB_AIRCR_VECTRESET_VECTRESET_1 = 0x1 // Causes a local system reset + SCB_AIRCR_VECTCLRACTIVE_Pos = 0x1 // Position of VECTCLRACTIVE field. + SCB_AIRCR_VECTCLRACTIVE_Msk = 0x2 // Bit mask of VECTCLRACTIVE field. + SCB_AIRCR_VECTCLRACTIVE = 0x2 // Bit VECTCLRACTIVE. + SCB_AIRCR_VECTCLRACTIVE_VECTCLRACTIVE_0 = 0x0 // No change + SCB_AIRCR_VECTCLRACTIVE_VECTCLRACTIVE_1 = 0x1 // Clears all active state information for fixed and configurable exceptions + SCB_AIRCR_SYSRESETREQ_Pos = 0x2 // Position of SYSRESETREQ field. + SCB_AIRCR_SYSRESETREQ_Msk = 0x4 // Bit mask of SYSRESETREQ field. + SCB_AIRCR_SYSRESETREQ = 0x4 // Bit SYSRESETREQ. + SCB_AIRCR_SYSRESETREQ_SYSRESETREQ_0 = 0x0 // no system reset request + SCB_AIRCR_SYSRESETREQ_SYSRESETREQ_1 = 0x1 // asserts a signal to the outer system that requests a reset + SCB_AIRCR_PRIGROUP_Pos = 0x8 // Position of PRIGROUP field. + SCB_AIRCR_PRIGROUP_Msk = 0x700 // Bit mask of PRIGROUP field. + SCB_AIRCR_ENDIANNESS_Pos = 0xf // Position of ENDIANNESS field. + SCB_AIRCR_ENDIANNESS_Msk = 0x8000 // Bit mask of ENDIANNESS field. + SCB_AIRCR_ENDIANNESS = 0x8000 // Bit ENDIANNESS. + SCB_AIRCR_ENDIANNESS_ENDIANNESS_0 = 0x0 // Little-endian + SCB_AIRCR_ENDIANNESS_ENDIANNESS_1 = 0x1 // Big-endian + SCB_AIRCR_VECTKEY_Pos = 0x10 // Position of VECTKEY field. + SCB_AIRCR_VECTKEY_Msk = 0xffff0000 // Bit mask of VECTKEY field. + + // SCR: System Control Register + SCB_SCR_SLEEPONEXIT_Pos = 0x1 // Position of SLEEPONEXIT field. + SCB_SCR_SLEEPONEXIT_Msk = 0x2 // Bit mask of SLEEPONEXIT field. + SCB_SCR_SLEEPONEXIT = 0x2 // Bit SLEEPONEXIT. + SCB_SCR_SLEEPONEXIT_SLEEPONEXIT_0 = 0x0 // o not sleep when returning to Thread mode + SCB_SCR_SLEEPONEXIT_SLEEPONEXIT_1 = 0x1 // enter sleep, or deep sleep, on return from an ISR + SCB_SCR_SLEEPDEEP_Pos = 0x2 // Position of SLEEPDEEP field. + SCB_SCR_SLEEPDEEP_Msk = 0x4 // Bit mask of SLEEPDEEP field. + SCB_SCR_SLEEPDEEP = 0x4 // Bit SLEEPDEEP. + SCB_SCR_SLEEPDEEP_SLEEPDEEP_0 = 0x0 // sleep + SCB_SCR_SLEEPDEEP_SLEEPDEEP_1 = 0x1 // deep sleep + SCB_SCR_SEVONPEND_Pos = 0x4 // Position of SEVONPEND field. + SCB_SCR_SEVONPEND_Msk = 0x10 // Bit mask of SEVONPEND field. + SCB_SCR_SEVONPEND = 0x10 // Bit SEVONPEND. + SCB_SCR_SEVONPEND_SEVONPEND_0 = 0x0 // only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + SCB_SCR_SEVONPEND_SEVONPEND_1 = 0x1 // enabled events and all interrupts, including disabled interrupts, can wakeup the processor + + // CCR: Configuration and Control Register + SCB_CCR_NONBASETHRDENA_Pos = 0x0 // Position of NONBASETHRDENA field. + SCB_CCR_NONBASETHRDENA_Msk = 0x1 // Bit mask of NONBASETHRDENA field. + SCB_CCR_NONBASETHRDENA = 0x1 // Bit NONBASETHRDENA. + SCB_CCR_NONBASETHRDENA_NONBASETHRDENA_0 = 0x0 // processor can enter Thread mode only when no exception is active + SCB_CCR_NONBASETHRDENA_NONBASETHRDENA_1 = 0x1 // processor can enter Thread mode from any level under the control of an EXC_RETURN value + SCB_CCR_USERSETMPEND_Pos = 0x1 // Position of USERSETMPEND field. + SCB_CCR_USERSETMPEND_Msk = 0x2 // Bit mask of USERSETMPEND field. + SCB_CCR_USERSETMPEND = 0x2 // Bit USERSETMPEND. + SCB_CCR_USERSETMPEND_USERSETMPEND_0 = 0x0 // disable + SCB_CCR_USERSETMPEND_USERSETMPEND_1 = 0x1 // enable + SCB_CCR_UNALIGN_TRP_Pos = 0x3 // Position of UNALIGN_TRP field. + SCB_CCR_UNALIGN_TRP_Msk = 0x8 // Bit mask of UNALIGN_TRP field. + SCB_CCR_UNALIGN_TRP = 0x8 // Bit UNALIGN_TRP. + SCB_CCR_UNALIGN_TRP_UNALIGN_TRP_0 = 0x0 // do not trap unaligned halfword and word accesses + SCB_CCR_UNALIGN_TRP_UNALIGN_TRP_1 = 0x1 // trap unaligned halfword and word accesses + SCB_CCR_DIV_0_TRP_Pos = 0x4 // Position of DIV_0_TRP field. + SCB_CCR_DIV_0_TRP_Msk = 0x10 // Bit mask of DIV_0_TRP field. + SCB_CCR_DIV_0_TRP = 0x10 // Bit DIV_0_TRP. + SCB_CCR_DIV_0_TRP_DIV_0_TRP_0 = 0x0 // do not trap divide by 0 + SCB_CCR_DIV_0_TRP_DIV_0_TRP_1 = 0x1 // trap divide by 0 + SCB_CCR_BFHFNMIGN_Pos = 0x8 // Position of BFHFNMIGN field. + SCB_CCR_BFHFNMIGN_Msk = 0x100 // Bit mask of BFHFNMIGN field. + SCB_CCR_BFHFNMIGN = 0x100 // Bit BFHFNMIGN. + SCB_CCR_BFHFNMIGN_BFHFNMIGN_0 = 0x0 // data bus faults caused by load and store instructions cause a lock-up + SCB_CCR_BFHFNMIGN_BFHFNMIGN_1 = 0x1 // handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions + SCB_CCR_STKALIGN_Pos = 0x9 // Position of STKALIGN field. + SCB_CCR_STKALIGN_Msk = 0x200 // Bit mask of STKALIGN field. + SCB_CCR_STKALIGN = 0x200 // Bit STKALIGN. + SCB_CCR_STKALIGN_STKALIGN_0 = 0x0 // 4-byte aligned + SCB_CCR_STKALIGN_STKALIGN_1 = 0x1 // 8-byte aligned + SCB_CCR_DC_Pos = 0x10 // Position of DC field. + SCB_CCR_DC_Msk = 0x10000 // Bit mask of DC field. + SCB_CCR_DC = 0x10000 // Bit DC. + SCB_CCR_DC_DC_0 = 0x0 // L1 data cache disabled + SCB_CCR_DC_DC_1 = 0x1 // L1 data cache enabled + SCB_CCR_IC_Pos = 0x11 // Position of IC field. + SCB_CCR_IC_Msk = 0x20000 // Bit mask of IC field. + SCB_CCR_IC = 0x20000 // Bit IC. + SCB_CCR_IC_IC_0 = 0x0 // L1 instruction cache disabled + SCB_CCR_IC_IC_1 = 0x1 // L1 instruction cache enabled + SCB_CCR_BP_Pos = 0x12 // Position of BP field. + SCB_CCR_BP_Msk = 0x40000 // Bit mask of BP field. + SCB_CCR_BP = 0x40000 // Bit BP. + + // SHPR1: System Handler Priority Register 1 + SCB_SHPR1_PRI_4_Pos = 0x0 // Position of PRI_4 field. + SCB_SHPR1_PRI_4_Msk = 0xff // Bit mask of PRI_4 field. + SCB_SHPR1_PRI_5_Pos = 0x8 // Position of PRI_5 field. + SCB_SHPR1_PRI_5_Msk = 0xff00 // Bit mask of PRI_5 field. + SCB_SHPR1_PRI_6_Pos = 0x10 // Position of PRI_6 field. + SCB_SHPR1_PRI_6_Msk = 0xff0000 // Bit mask of PRI_6 field. + + // SHPR2: System Handler Priority Register 2 + SCB_SHPR2_PRI_11_Pos = 0x18 // Position of PRI_11 field. + SCB_SHPR2_PRI_11_Msk = 0xff000000 // Bit mask of PRI_11 field. + + // SHPR3: System Handler Priority Register 3 + SCB_SHPR3_PRI_14_Pos = 0x10 // Position of PRI_14 field. + SCB_SHPR3_PRI_14_Msk = 0xff0000 // Bit mask of PRI_14 field. + SCB_SHPR3_PRI_15_Pos = 0x18 // Position of PRI_15 field. + SCB_SHPR3_PRI_15_Msk = 0xff000000 // Bit mask of PRI_15 field. + + // SHCSR: System Handler Control and State Register + SCB_SHCSR_MEMFAULTACT_Pos = 0x0 // Position of MEMFAULTACT field. + SCB_SHCSR_MEMFAULTACT_Msk = 0x1 // Bit mask of MEMFAULTACT field. + SCB_SHCSR_MEMFAULTACT = 0x1 // Bit MEMFAULTACT. + SCB_SHCSR_MEMFAULTACT_MEMFAULTACT_0 = 0x0 // exception is not active + SCB_SHCSR_MEMFAULTACT_MEMFAULTACT_1 = 0x1 // exception is active + SCB_SHCSR_BUSFAULTACT_Pos = 0x1 // Position of BUSFAULTACT field. + SCB_SHCSR_BUSFAULTACT_Msk = 0x2 // Bit mask of BUSFAULTACT field. + SCB_SHCSR_BUSFAULTACT = 0x2 // Bit BUSFAULTACT. + SCB_SHCSR_BUSFAULTACT_BUSFAULTACT_0 = 0x0 // exception is not active + SCB_SHCSR_BUSFAULTACT_BUSFAULTACT_1 = 0x1 // exception is active + SCB_SHCSR_USGFAULTACT_Pos = 0x3 // Position of USGFAULTACT field. + SCB_SHCSR_USGFAULTACT_Msk = 0x8 // Bit mask of USGFAULTACT field. + SCB_SHCSR_USGFAULTACT = 0x8 // Bit USGFAULTACT. + SCB_SHCSR_USGFAULTACT_USGFAULTACT_0 = 0x0 // exception is not active + SCB_SHCSR_USGFAULTACT_USGFAULTACT_1 = 0x1 // exception is active + SCB_SHCSR_SVCALLACT_Pos = 0x7 // Position of SVCALLACT field. + SCB_SHCSR_SVCALLACT_Msk = 0x80 // Bit mask of SVCALLACT field. + SCB_SHCSR_SVCALLACT = 0x80 // Bit SVCALLACT. + SCB_SHCSR_SVCALLACT_SVCALLACT_0 = 0x0 // exception is not active + SCB_SHCSR_SVCALLACT_SVCALLACT_1 = 0x1 // exception is active + SCB_SHCSR_MONITORACT_Pos = 0x8 // Position of MONITORACT field. + SCB_SHCSR_MONITORACT_Msk = 0x100 // Bit mask of MONITORACT field. + SCB_SHCSR_MONITORACT = 0x100 // Bit MONITORACT. + SCB_SHCSR_MONITORACT_MONITORACT_0 = 0x0 // exception is not active + SCB_SHCSR_MONITORACT_MONITORACT_1 = 0x1 // exception is active + SCB_SHCSR_PENDSVACT_Pos = 0xa // Position of PENDSVACT field. + SCB_SHCSR_PENDSVACT_Msk = 0x400 // Bit mask of PENDSVACT field. + SCB_SHCSR_PENDSVACT = 0x400 // Bit PENDSVACT. + SCB_SHCSR_PENDSVACT_PENDSVACT_0 = 0x0 // exception is not active + SCB_SHCSR_PENDSVACT_PENDSVACT_1 = 0x1 // exception is active + SCB_SHCSR_SYSTICKACT_Pos = 0xb // Position of SYSTICKACT field. + SCB_SHCSR_SYSTICKACT_Msk = 0x800 // Bit mask of SYSTICKACT field. + SCB_SHCSR_SYSTICKACT = 0x800 // Bit SYSTICKACT. + SCB_SHCSR_SYSTICKACT_SYSTICKACT_0 = 0x0 // exception is not active + SCB_SHCSR_SYSTICKACT_SYSTICKACT_1 = 0x1 // exception is active + SCB_SHCSR_USGFAULTPENDED_Pos = 0xc // Position of USGFAULTPENDED field. + SCB_SHCSR_USGFAULTPENDED_Msk = 0x1000 // Bit mask of USGFAULTPENDED field. + SCB_SHCSR_USGFAULTPENDED = 0x1000 // Bit USGFAULTPENDED. + SCB_SHCSR_USGFAULTPENDED_USGFAULTPENDED_0 = 0x0 // exception is not pending + SCB_SHCSR_USGFAULTPENDED_USGFAULTPENDED_1 = 0x1 // exception is pending + SCB_SHCSR_MEMFAULTPENDED_Pos = 0xd // Position of MEMFAULTPENDED field. + SCB_SHCSR_MEMFAULTPENDED_Msk = 0x2000 // Bit mask of MEMFAULTPENDED field. + SCB_SHCSR_MEMFAULTPENDED = 0x2000 // Bit MEMFAULTPENDED. + SCB_SHCSR_MEMFAULTPENDED_MEMFAULTPENDED_0 = 0x0 // exception is not pending + SCB_SHCSR_MEMFAULTPENDED_MEMFAULTPENDED_1 = 0x1 // exception is pending + SCB_SHCSR_BUSFAULTPENDED_Pos = 0xe // Position of BUSFAULTPENDED field. + SCB_SHCSR_BUSFAULTPENDED_Msk = 0x4000 // Bit mask of BUSFAULTPENDED field. + SCB_SHCSR_BUSFAULTPENDED = 0x4000 // Bit BUSFAULTPENDED. + SCB_SHCSR_BUSFAULTPENDED_BUSFAULTPENDED_0 = 0x0 // exception is not pending + SCB_SHCSR_BUSFAULTPENDED_BUSFAULTPENDED_1 = 0x1 // exception is pending + SCB_SHCSR_SVCALLPENDED_Pos = 0xf // Position of SVCALLPENDED field. + SCB_SHCSR_SVCALLPENDED_Msk = 0x8000 // Bit mask of SVCALLPENDED field. + SCB_SHCSR_SVCALLPENDED = 0x8000 // Bit SVCALLPENDED. + SCB_SHCSR_SVCALLPENDED_SVCALLPENDED_0 = 0x0 // exception is not pending + SCB_SHCSR_SVCALLPENDED_SVCALLPENDED_1 = 0x1 // exception is pending + SCB_SHCSR_MEMFAULTENA_Pos = 0x10 // Position of MEMFAULTENA field. + SCB_SHCSR_MEMFAULTENA_Msk = 0x10000 // Bit mask of MEMFAULTENA field. + SCB_SHCSR_MEMFAULTENA = 0x10000 // Bit MEMFAULTENA. + SCB_SHCSR_MEMFAULTENA_MEMFAULTENA_0 = 0x0 // disable the exception + SCB_SHCSR_MEMFAULTENA_MEMFAULTENA_1 = 0x1 // enable the exception + SCB_SHCSR_BUSFAULTENA_Pos = 0x11 // Position of BUSFAULTENA field. + SCB_SHCSR_BUSFAULTENA_Msk = 0x20000 // Bit mask of BUSFAULTENA field. + SCB_SHCSR_BUSFAULTENA = 0x20000 // Bit BUSFAULTENA. + SCB_SHCSR_BUSFAULTENA_BUSFAULTENA_0 = 0x0 // disable the exception + SCB_SHCSR_BUSFAULTENA_BUSFAULTENA_1 = 0x1 // enable the exception + SCB_SHCSR_USGFAULTENA_Pos = 0x12 // Position of USGFAULTENA field. + SCB_SHCSR_USGFAULTENA_Msk = 0x40000 // Bit mask of USGFAULTENA field. + SCB_SHCSR_USGFAULTENA = 0x40000 // Bit USGFAULTENA. + SCB_SHCSR_USGFAULTENA_USGFAULTENA_0 = 0x0 // disable the exception + SCB_SHCSR_USGFAULTENA_USGFAULTENA_1 = 0x1 // enable the exception + + // CFSR: Configurable Fault Status Register + SCB_CFSR_IACCVIOL_Pos = 0x0 // Position of IACCVIOL field. + SCB_CFSR_IACCVIOL_Msk = 0x1 // Bit mask of IACCVIOL field. + SCB_CFSR_IACCVIOL = 0x1 // Bit IACCVIOL. + SCB_CFSR_IACCVIOL_IACCVIOL_0 = 0x0 // no instruction access violation fault + SCB_CFSR_IACCVIOL_IACCVIOL_1 = 0x1 // the processor attempted an instruction fetch from a location that does not permit execution + SCB_CFSR_DACCVIOL_Pos = 0x1 // Position of DACCVIOL field. + SCB_CFSR_DACCVIOL_Msk = 0x2 // Bit mask of DACCVIOL field. + SCB_CFSR_DACCVIOL = 0x2 // Bit DACCVIOL. + SCB_CFSR_DACCVIOL_DACCVIOL_0 = 0x0 // no data access violation fault + SCB_CFSR_DACCVIOL_DACCVIOL_1 = 0x1 // the processor attempted a load or store at a location that does not permit the operation + SCB_CFSR_MUNSTKERR_Pos = 0x3 // Position of MUNSTKERR field. + SCB_CFSR_MUNSTKERR_Msk = 0x8 // Bit mask of MUNSTKERR field. + SCB_CFSR_MUNSTKERR = 0x8 // Bit MUNSTKERR. + SCB_CFSR_MUNSTKERR_MUNSTKERR_0 = 0x0 // no unstacking fault + SCB_CFSR_MUNSTKERR_MUNSTKERR_1 = 0x1 // unstack for an exception return has caused one or more access violations + SCB_CFSR_MSTKERR_Pos = 0x4 // Position of MSTKERR field. + SCB_CFSR_MSTKERR_Msk = 0x10 // Bit mask of MSTKERR field. + SCB_CFSR_MSTKERR = 0x10 // Bit MSTKERR. + SCB_CFSR_MSTKERR_MSTKERR_0 = 0x0 // no stacking fault + SCB_CFSR_MSTKERR_MSTKERR_1 = 0x1 // stacking for an exception entry has caused one or more access violations + SCB_CFSR_MLSPERR_Pos = 0x5 // Position of MLSPERR field. + SCB_CFSR_MLSPERR_Msk = 0x20 // Bit mask of MLSPERR field. + SCB_CFSR_MLSPERR = 0x20 // Bit MLSPERR. + SCB_CFSR_MLSPERR_MLSPERR_0 = 0x0 // No MemManage fault occurred during floating-point lazy state preservation + SCB_CFSR_MLSPERR_MLSPERR_1 = 0x1 // A MemManage fault occurred during floating-point lazy state preservation + SCB_CFSR_MMARVALID_Pos = 0x7 // Position of MMARVALID field. + SCB_CFSR_MMARVALID_Msk = 0x80 // Bit mask of MMARVALID field. + SCB_CFSR_MMARVALID = 0x80 // Bit MMARVALID. + SCB_CFSR_MMARVALID_MMARVALID_0 = 0x0 // value in MMAR is not a valid fault address + SCB_CFSR_MMARVALID_MMARVALID_1 = 0x1 // MMAR holds a valid fault address + SCB_CFSR_IBUSERR_Pos = 0x8 // Position of IBUSERR field. + SCB_CFSR_IBUSERR_Msk = 0x100 // Bit mask of IBUSERR field. + SCB_CFSR_IBUSERR = 0x100 // Bit IBUSERR. + SCB_CFSR_IBUSERR_IBUSERR_0 = 0x0 // no instruction bus error + SCB_CFSR_IBUSERR_IBUSERR_1 = 0x1 // instruction bus error + SCB_CFSR_PRECISERR_Pos = 0x9 // Position of PRECISERR field. + SCB_CFSR_PRECISERR_Msk = 0x200 // Bit mask of PRECISERR field. + SCB_CFSR_PRECISERR = 0x200 // Bit PRECISERR. + SCB_CFSR_PRECISERR_PRECISERR_0 = 0x0 // no precise data bus error + SCB_CFSR_PRECISERR_PRECISERR_1 = 0x1 // a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault + SCB_CFSR_IMPRECISERR_Pos = 0xa // Position of IMPRECISERR field. + SCB_CFSR_IMPRECISERR_Msk = 0x400 // Bit mask of IMPRECISERR field. + SCB_CFSR_IMPRECISERR = 0x400 // Bit IMPRECISERR. + SCB_CFSR_IMPRECISERR_IMPRECISERR_0 = 0x0 // no imprecise data bus error + SCB_CFSR_IMPRECISERR_IMPRECISERR_1 = 0x1 // a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error + SCB_CFSR_UNSTKERR_Pos = 0xb // Position of UNSTKERR field. + SCB_CFSR_UNSTKERR_Msk = 0x800 // Bit mask of UNSTKERR field. + SCB_CFSR_UNSTKERR = 0x800 // Bit UNSTKERR. + SCB_CFSR_UNSTKERR_UNSTKERR_0 = 0x0 // no unstacking fault + SCB_CFSR_UNSTKERR_UNSTKERR_1 = 0x1 // unstack for an exception return has caused one or more BusFaults + SCB_CFSR_STKERR_Pos = 0xc // Position of STKERR field. + SCB_CFSR_STKERR_Msk = 0x1000 // Bit mask of STKERR field. + SCB_CFSR_STKERR = 0x1000 // Bit STKERR. + SCB_CFSR_STKERR_STKERR_0 = 0x0 // no stacking fault + SCB_CFSR_STKERR_STKERR_1 = 0x1 // stacking for an exception entry has caused one or more BusFaults + SCB_CFSR_LSPERR_Pos = 0xd // Position of LSPERR field. + SCB_CFSR_LSPERR_Msk = 0x2000 // Bit mask of LSPERR field. + SCB_CFSR_LSPERR = 0x2000 // Bit LSPERR. + SCB_CFSR_LSPERR_LSPERR_0 = 0x0 // No bus fault occurred during floating-point lazy state preservation + SCB_CFSR_LSPERR_LSPERR_1 = 0x1 // A bus fault occurred during floating-point lazy state preservation + SCB_CFSR_BFARVALID_Pos = 0xf // Position of BFARVALID field. + SCB_CFSR_BFARVALID_Msk = 0x8000 // Bit mask of BFARVALID field. + SCB_CFSR_BFARVALID = 0x8000 // Bit BFARVALID. + SCB_CFSR_BFARVALID_BFARVALID_0 = 0x0 // value in BFAR is not a valid fault address + SCB_CFSR_BFARVALID_BFARVALID_1 = 0x1 // BFAR holds a valid fault address + SCB_CFSR_UNDEFINSTR_Pos = 0x10 // Position of UNDEFINSTR field. + SCB_CFSR_UNDEFINSTR_Msk = 0x10000 // Bit mask of UNDEFINSTR field. + SCB_CFSR_UNDEFINSTR = 0x10000 // Bit UNDEFINSTR. + SCB_CFSR_UNDEFINSTR_UNDEFINSTR_0 = 0x0 // no undefined instruction UsageFault + SCB_CFSR_UNDEFINSTR_UNDEFINSTR_1 = 0x1 // the processor has attempted to execute an undefined instruction + SCB_CFSR_INVSTATE_Pos = 0x11 // Position of INVSTATE field. + SCB_CFSR_INVSTATE_Msk = 0x20000 // Bit mask of INVSTATE field. + SCB_CFSR_INVSTATE = 0x20000 // Bit INVSTATE. + SCB_CFSR_INVSTATE_INVSTATE_0 = 0x0 // no invalid state UsageFault + SCB_CFSR_INVSTATE_INVSTATE_1 = 0x1 // the processor has attempted to execute an instruction that makes illegal use of the EPSR + SCB_CFSR_INVPC_Pos = 0x12 // Position of INVPC field. + SCB_CFSR_INVPC_Msk = 0x40000 // Bit mask of INVPC field. + SCB_CFSR_INVPC = 0x40000 // Bit INVPC. + SCB_CFSR_INVPC_INVPC_0 = 0x0 // no invalid PC load UsageFault + SCB_CFSR_INVPC_INVPC_1 = 0x1 // the processor has attempted an illegal load of EXC_RETURN to the PC + SCB_CFSR_NOCP_Pos = 0x13 // Position of NOCP field. + SCB_CFSR_NOCP_Msk = 0x80000 // Bit mask of NOCP field. + SCB_CFSR_NOCP = 0x80000 // Bit NOCP. + SCB_CFSR_NOCP_NOCP_0 = 0x0 // no UsageFault caused by attempting to access a coprocessor + SCB_CFSR_NOCP_NOCP_1 = 0x1 // the processor has attempted to access a coprocessor + SCB_CFSR_UNALIGNED_Pos = 0x18 // Position of UNALIGNED field. + SCB_CFSR_UNALIGNED_Msk = 0x1000000 // Bit mask of UNALIGNED field. + SCB_CFSR_UNALIGNED = 0x1000000 // Bit UNALIGNED. + SCB_CFSR_UNALIGNED_UNALIGNED_0 = 0x0 // no unaligned access fault, or unaligned access trapping not enabled + SCB_CFSR_UNALIGNED_UNALIGNED_1 = 0x1 // the processor has made an unaligned memory access + SCB_CFSR_DIVBYZERO_Pos = 0x19 // Position of DIVBYZERO field. + SCB_CFSR_DIVBYZERO_Msk = 0x2000000 // Bit mask of DIVBYZERO field. + SCB_CFSR_DIVBYZERO = 0x2000000 // Bit DIVBYZERO. + SCB_CFSR_DIVBYZERO_DIVBYZERO_0 = 0x0 // no divide by zero fault, or divide by zero trapping not enabled + SCB_CFSR_DIVBYZERO_DIVBYZERO_1 = 0x1 // the processor has executed an SDIV or UDIV instruction with a divisor of 0 + + // HFSR: HardFault Status register + SCB_HFSR_VECTTBL_Pos = 0x1 // Position of VECTTBL field. + SCB_HFSR_VECTTBL_Msk = 0x2 // Bit mask of VECTTBL field. + SCB_HFSR_VECTTBL = 0x2 // Bit VECTTBL. + SCB_HFSR_VECTTBL_VECTTBL_0 = 0x0 // no BusFault on vector table read + SCB_HFSR_VECTTBL_VECTTBL_1 = 0x1 // BusFault on vector table read + SCB_HFSR_FORCED_Pos = 0x1e // Position of FORCED field. + SCB_HFSR_FORCED_Msk = 0x40000000 // Bit mask of FORCED field. + SCB_HFSR_FORCED = 0x40000000 // Bit FORCED. + SCB_HFSR_FORCED_FORCED_0 = 0x0 // no forced HardFault + SCB_HFSR_FORCED_FORCED_1 = 0x1 // forced HardFault + SCB_HFSR_DEBUGEVT_Pos = 0x1f // Position of DEBUGEVT field. + SCB_HFSR_DEBUGEVT_Msk = 0x80000000 // Bit mask of DEBUGEVT field. + SCB_HFSR_DEBUGEVT = 0x80000000 // Bit DEBUGEVT. + SCB_HFSR_DEBUGEVT_DEBUGEVT_0 = 0x0 // No Debug event has occurred. + SCB_HFSR_DEBUGEVT_DEBUGEVT_1 = 0x1 // Debug event has occurred. The Debug Fault Status Register has been updated. + + // DFSR: Debug Fault Status Register + SCB_DFSR_HALTED_Pos = 0x0 // Position of HALTED field. + SCB_DFSR_HALTED_Msk = 0x1 // Bit mask of HALTED field. + SCB_DFSR_HALTED = 0x1 // Bit HALTED. + SCB_DFSR_HALTED_HALTED_0 = 0x0 // No active halt request debug event + SCB_DFSR_HALTED_HALTED_1 = 0x1 // Halt request debug event active + SCB_DFSR_BKPT_Pos = 0x1 // Position of BKPT field. + SCB_DFSR_BKPT_Msk = 0x2 // Bit mask of BKPT field. + SCB_DFSR_BKPT = 0x2 // Bit BKPT. + SCB_DFSR_BKPT_BKPT_0 = 0x0 // No current breakpoint debug event + SCB_DFSR_BKPT_BKPT_1 = 0x1 // At least one current breakpoint debug event + SCB_DFSR_DWTTRAP_Pos = 0x2 // Position of DWTTRAP field. + SCB_DFSR_DWTTRAP_Msk = 0x4 // Bit mask of DWTTRAP field. + SCB_DFSR_DWTTRAP = 0x4 // Bit DWTTRAP. + SCB_DFSR_DWTTRAP_DWTTRAP_0 = 0x0 // No current debug events generated by the DWT + SCB_DFSR_DWTTRAP_DWTTRAP_1 = 0x1 // At least one current debug event generated by the DWT + SCB_DFSR_VCATCH_Pos = 0x3 // Position of VCATCH field. + SCB_DFSR_VCATCH_Msk = 0x8 // Bit mask of VCATCH field. + SCB_DFSR_VCATCH = 0x8 // Bit VCATCH. + SCB_DFSR_VCATCH_VCATCH_0 = 0x0 // No Vector catch triggered + SCB_DFSR_VCATCH_VCATCH_1 = 0x1 // Vector catch triggered + SCB_DFSR_EXTERNAL_Pos = 0x4 // Position of EXTERNAL field. + SCB_DFSR_EXTERNAL_Msk = 0x10 // Bit mask of EXTERNAL field. + SCB_DFSR_EXTERNAL = 0x10 // Bit EXTERNAL. + SCB_DFSR_EXTERNAL_EXTERNAL_0 = 0x0 // No external debug request debug event + SCB_DFSR_EXTERNAL_EXTERNAL_1 = 0x1 // External debug request debug event + + // MMFAR: MemManage Fault Address Register + SCB_MMFAR_ADDRESS_Pos = 0x0 // Position of ADDRESS field. + SCB_MMFAR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field. + + // BFAR: BusFault Address Register + SCB_BFAR_ADDRESS_Pos = 0x0 // Position of ADDRESS field. + SCB_BFAR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field. +) diff --git a/emb/device/arm/semihosting.go b/emb/device/arm/semihosting.go new file mode 100644 index 0000000..10b6497 --- /dev/null +++ b/emb/device/arm/semihosting.go @@ -0,0 +1,65 @@ +package arm + +// Semihosting commands. +// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html +const ( + // Regular semihosting calls + SemihostingClock = 0x10 + SemihostingClose = 0x02 + SemihostingElapsed = 0x30 + SemihostingErrno = 0x13 + SemihostingFileLen = 0x0C + SemihostingGetCmdline = 0x15 + SemihostingHeapInfo = 0x16 + SemihostingIsError = 0x08 + SemihostingIsTTY = 0x09 + SemihostingOpen = 0x01 + SemihostingRead = 0x06 + SemihostingReadByte = 0x07 + SemihostingRemove = 0x0E + SemihostingRename = 0x0F + SemihostingSeek = 0x0A + SemihostingSystem = 0x12 + SemihostingTickFreq = 0x31 + SemihostingTime = 0x11 + SemihostingTmpName = 0x0D + SemihostingWrite = 0x05 + SemihostingWrite0 = 0x04 + SemihostingWriteByte = 0x03 + + // Angel semihosting calls + SemihostingEnterSVC = 0x17 + SemihostingReportException = 0x18 +) + +// Special codes for the Angel Semihosting interface. +// https://www.keil.com/support/man/docs/armcc/armcc_pge1358787050566.htm +const ( + // Hardware vector reason codes + SemihostingBranchThroughZero = 0x20000 + SemihostingUndefinedInstr = 0x20001 + SemihostingSoftwareInterrupt = 0x20002 + SemihostingPrefetchAbort = 0x20003 + SemihostingDataAbort = 0x20004 + SemihostingAddressException = 0x20005 + SemihostingIRQ = 0x20006 + SemihostingFIQ = 0x20007 + + // Software reason codes + SemihostingBreakPoint = 0x20020 + SemihostingWatchPoint = 0x20021 + SemihostingStepComplete = 0x20022 + SemihostingRunTimeErrorUnknown = 0x20023 + SemihostingInternalError = 0x20024 + SemihostingUserInterruption = 0x20025 + SemihostingApplicationExit = 0x20026 + SemihostingStackOverflow = 0x20027 + SemihostingDivisionByZero = 0x20028 + SemihostingOSSpecific = 0x20029 +) + +// Call a semihosting function. +// TODO: implement it here using inline assembly. +// +//go:linkname SemihostingCall SemihostingCall +func SemihostingCall(num int, arg uintptr) int diff --git a/emb/device/arm64/arm64.go b/emb/device/arm64/arm64.go new file mode 100644 index 0000000..7e8cea6 --- /dev/null +++ b/emb/device/arm64/arm64.go @@ -0,0 +1,36 @@ +package arm64 + +// Run the given assembly code. The code will be marked as having side effects, +// as it doesn't produce output and thus would normally be eliminated by the +// optimizer. +func Asm(asm string) + +// Run the given inline assembly. The code will be marked as having side +// effects, as it would otherwise be optimized away. The inline assembly string +// recognizes template values in the form {name}, like so: +// +// arm.AsmFull( +// "str {value}, {result}", +// map[string]interface{}{ +// "value": 1 +// "result": &dest, +// }) +// +// You can use {} in the asm string (which expands to a register) to set the +// return value. +func AsmFull(asm string, regs map[string]interface{}) uintptr + +// Run the following system call (SVCall) with 0 arguments. +func SVCall0(num uintptr) uintptr + +// Run the following system call (SVCall) with 1 argument. +func SVCall1(num uintptr, a1 interface{}) uintptr + +// Run the following system call (SVCall) with 2 arguments. +func SVCall2(num uintptr, a1, a2 interface{}) uintptr + +// Run the following system call (SVCall) with 3 arguments. +func SVCall3(num uintptr, a1, a2, a3 interface{}) uintptr + +// Run the following system call (SVCall) with 4 arguments. +func SVCall4(num uintptr, a1, a2, a3, a4 interface{}) uintptr diff --git a/emb/device/asm.go b/emb/device/asm.go new file mode 100644 index 0000000..49ddbc3 --- /dev/null +++ b/emb/device/asm.go @@ -0,0 +1,21 @@ +package device + +// Run the given assembly code. The code will be marked as having side effects, +// as it doesn't produce output and thus would normally be eliminated by the +// optimizer. +func Asm(asm string) + +// Run the given inline assembly. The code will be marked as having side +// effects, as it would otherwise be optimized away. The inline assembly string +// recognizes template values in the form {name}, like so: +// +// arm.AsmFull( +// "str {value}, {result}", +// map[string]interface{}{ +// "value": 1 +// "result": &dest, +// }) +// +// You can use {} in the asm string (which expands to a register) to set the +// return value. +func AsmFull(asm string, regs map[string]interface{}) uintptr diff --git a/emb/device/esp/esp32.S b/emb/device/esp/esp32.S new file mode 100644 index 0000000..1179a2d --- /dev/null +++ b/emb/device/esp/esp32.S @@ -0,0 +1,57 @@ + +// The following definitions were copied from: +// esp-idf/components/xtensa/include/xtensa/corebits.h +#define PS_WOE_MASK 0x00040000 +#define PS_OWB_MASK 0x00000F00 +#define PS_CALLINC_MASK 0x00030000 +#define PS_WOE PS_WOE_MASK + +// Only calling it call_start_cpu0 for consistency with ESP-IDF. +.section .text.call_start_cpu0 +1: + .long _stack_top +.global call_start_cpu0 +call_start_cpu0: + // We need to set the stack pointer to a different value. This is somewhat + // complicated in the Xtensa architecture. The code below is a modified + // version of the following code: + // https://github.com/espressif/esp-idf/blob/c77c4ccf/components/xtensa/include/xt_instr_macros.h#L47 + + // Disable WOE. + rsr.ps a2 + movi a3, ~(PS_WOE_MASK) + and a2, a2, a3 + wsr.ps a2 + rsync + + // Set WINDOWSTART to 1 << WINDOWBASE. + rsr.windowbase a2 + ssl a2 + movi a2, 1 + sll a2, a2 + wsr.windowstart a2 + rsync + + // Load new stack pointer. + l32r sp, 1b + + // Re-enable WOE. + rsr.ps a2 + movi a3, PS_WOE + or a2, a2, a3 + wsr.ps a2 + rsync + + // Enable the FPU (coprocessor 0 so the lowest bit). + movi a2, 1 + wsr.cpenable a2 + rsync + + // Jump to the runtime start function written in Go. + call4 main + +.section .text.tinygo_scanCurrentStack +.global tinygo_scanCurrentStack +tinygo_scanCurrentStack: + // TODO: save callee saved registers on the stack + j tinygo_scanstack diff --git a/emb/device/esp/esp32.go b/emb/device/esp/esp32.go new file mode 100644 index 0000000..381c6cd --- /dev/null +++ b/emb/device/esp/esp32.go @@ -0,0 +1,80119 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32 + +/* +// 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth/Bluetooth LE +*/ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32" + CPU = "Xtensa LX6" + FPUPresent = true + NVICPrioBits = 0 +) + +// Interrupt numbers. +const ( + // DPORT Peripheral + IRQ_WIFI_MAC = 0 + + // DPORT Peripheral + IRQ_WIFI_NMI = 1 + + // DPORT Peripheral + IRQ_WIFI_BB = 2 + + // DPORT Peripheral + IRQ_BT_MAC = 3 + + // DPORT Peripheral + IRQ_BT_BB = 4 + + // DPORT Peripheral + IRQ_BT_BB_NMI = 5 + + // DPORT Peripheral + IRQ_RWBT = 6 + + // DPORT Peripheral + IRQ_RWBLE = 7 + + // DPORT Peripheral + IRQ_RWBT_NMI = 8 + + // DPORT Peripheral + IRQ_RWBLE_NMI = 9 + + // Universal Host Controller Interface 0 + IRQ_UHCI0 = 12 + + // Universal Host Controller Interface 1 + IRQ_UHCI1 = 13 + + // Timer Group 0 + IRQ_TG0_T0_LEVEL = 14 + + // Timer Group 0 + IRQ_TG0_T1_LEVEL = 15 + + // Timer Group 0 + IRQ_TG0_WDT_LEVEL = 16 + + // Timer Group 0 + IRQ_TG0_LACT_LEVEL = 17 + + // Timer Group 1 + IRQ_TG1_T0_LEVEL = 18 + + // Timer Group 1 + IRQ_TG1_T1_LEVEL = 19 + + // Timer Group 1 + IRQ_TG1_WDT_LEVEL = 20 + + // Timer Group 1 + IRQ_TG1_LACT_LEVEL = 21 + + // General Purpose Input/Output + IRQ_GPIO = 22 + + // General Purpose Input/Output + IRQ_GPIO_NMI = 23 + + // DPORT Peripheral + IRQ_FROM_CPU_INTR0 = 24 + + // DPORT Peripheral + IRQ_FROM_CPU_INTR1 = 25 + + // DPORT Peripheral + IRQ_FROM_CPU_INTR2 = 26 + + // DPORT Peripheral + IRQ_FROM_CPU_INTR3 = 27 + + // SPI (Serial Peripheral Interface) Controller 0 + IRQ_SPI0 = 28 + + // SPI (Serial Peripheral Interface) Controller 1 + IRQ_SPI1 = 29 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_SPI2 = 30 + + // SPI (Serial Peripheral Interface) Controller 3 + IRQ_SPI3 = 31 + + // I2S (Inter-IC Sound) Controller 0 + IRQ_I2S0 = 32 + + // I2S (Inter-IC Sound) Controller 1 + IRQ_I2S1 = 33 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + IRQ_UART0 = 34 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + IRQ_UART1 = 35 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + IRQ_UART2 = 36 + + // DPORT Peripheral + IRQ_SDIO_HOST = 37 + + // DPORT Peripheral + IRQ_ETH_MAC = 38 + + // Motor Control Pulse-Width Modulation 0 + IRQ_MCPWM0 = 39 + + // Motor Control Pulse-Width Modulation 0 + IRQ_MCPWM1 = 40 + + // Motor Control Pulse-Width Modulation 0 + IRQ_MCPWM2 = 41 + + // Motor Control Pulse-Width Modulation 0 + IRQ_MCPWM3 = 42 + + // LED Control PWM (Pulse Width Modulation) + IRQ_LEDC = 43 + + // eFuse Controller + IRQ_EFUSE = 44 + + // Two-Wire Automotive Interface + IRQ_TWAI0 = 45 + + // Real-Time Clock Control + IRQ_RTC_CORE = 46 + + // Remote Control + IRQ_RMT = 47 + + // Pulse Count Controller + IRQ_PCNT = 48 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_EXT0 = 49 + + // I2C (Inter-Integrated Circuit) Controller 1 + IRQ_I2C_EXT1 = 50 + + // RSA (Rivest Shamir Adleman) Accelerator + IRQ_RSA = 51 + + // SPI (Serial Peripheral Interface) Controller 1 + IRQ_SPI1_DMA = 52 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_SPI2_DMA = 53 + + // SPI (Serial Peripheral Interface) Controller 3 + IRQ_SPI3_DMA = 54 + + // DPORT Peripheral + IRQ_WDT = 55 + + // LED Control PWM (Pulse Width Modulation) + IRQ_TIMER1 = 56 + + // LED Control PWM (Pulse Width Modulation) + IRQ_TIMER2 = 57 + + // Timer Group 0 + IRQ_TG0_T0_EDGE = 58 + + // Timer Group 0 + IRQ_TG0_T1_EDGE = 59 + + // Timer Group 0 + IRQ_TG0_WDT_EDGE = 60 + + // Timer Group 0 + IRQ_TG0_LACT_EDGE = 61 + + // Timer Group 1 + IRQ_TG1_T0_EDGE = 62 + + // Timer Group 1 + IRQ_TG1_T1_EDGE = 63 + + // Timer Group 1 + IRQ_TG1_WDT_EDGE = 64 + + // Timer Group 1 + IRQ_TG1_LACT_EDGE = 65 + + // DPORT Peripheral + IRQ_MMU_IA = 66 + + // DPORT Peripheral + IRQ_MPU_IA = 67 + + // DPORT Peripheral + IRQ_CACHE_IA = 68 + + // Highest interrupt number on this device. + IRQ_max = 68 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_WIFI_MAC: + callHandlers(IRQ_WIFI_MAC) + case IRQ_WIFI_NMI: + callHandlers(IRQ_WIFI_NMI) + case IRQ_WIFI_BB: + callHandlers(IRQ_WIFI_BB) + case IRQ_BT_MAC: + callHandlers(IRQ_BT_MAC) + case IRQ_BT_BB: + callHandlers(IRQ_BT_BB) + case IRQ_BT_BB_NMI: + callHandlers(IRQ_BT_BB_NMI) + case IRQ_RWBT: + callHandlers(IRQ_RWBT) + case IRQ_RWBLE: + callHandlers(IRQ_RWBLE) + case IRQ_RWBT_NMI: + callHandlers(IRQ_RWBT_NMI) + case IRQ_RWBLE_NMI: + callHandlers(IRQ_RWBLE_NMI) + case IRQ_UHCI0: + callHandlers(IRQ_UHCI0) + case IRQ_UHCI1: + callHandlers(IRQ_UHCI1) + case IRQ_TG0_T0_LEVEL: + callHandlers(IRQ_TG0_T0_LEVEL) + case IRQ_TG0_T1_LEVEL: + callHandlers(IRQ_TG0_T1_LEVEL) + case IRQ_TG0_WDT_LEVEL: + callHandlers(IRQ_TG0_WDT_LEVEL) + case IRQ_TG0_LACT_LEVEL: + callHandlers(IRQ_TG0_LACT_LEVEL) + case IRQ_TG1_T0_LEVEL: + callHandlers(IRQ_TG1_T0_LEVEL) + case IRQ_TG1_T1_LEVEL: + callHandlers(IRQ_TG1_T1_LEVEL) + case IRQ_TG1_WDT_LEVEL: + callHandlers(IRQ_TG1_WDT_LEVEL) + case IRQ_TG1_LACT_LEVEL: + callHandlers(IRQ_TG1_LACT_LEVEL) + case IRQ_GPIO: + callHandlers(IRQ_GPIO) + case IRQ_GPIO_NMI: + callHandlers(IRQ_GPIO_NMI) + case IRQ_FROM_CPU_INTR0: + callHandlers(IRQ_FROM_CPU_INTR0) + case IRQ_FROM_CPU_INTR1: + callHandlers(IRQ_FROM_CPU_INTR1) + case IRQ_FROM_CPU_INTR2: + callHandlers(IRQ_FROM_CPU_INTR2) + case IRQ_FROM_CPU_INTR3: + callHandlers(IRQ_FROM_CPU_INTR3) + case IRQ_SPI0: + callHandlers(IRQ_SPI0) + case IRQ_SPI1: + callHandlers(IRQ_SPI1) + case IRQ_SPI2: + callHandlers(IRQ_SPI2) + case IRQ_SPI3: + callHandlers(IRQ_SPI3) + case IRQ_I2S0: + callHandlers(IRQ_I2S0) + case IRQ_I2S1: + callHandlers(IRQ_I2S1) + case IRQ_UART0: + callHandlers(IRQ_UART0) + case IRQ_UART1: + callHandlers(IRQ_UART1) + case IRQ_UART2: + callHandlers(IRQ_UART2) + case IRQ_SDIO_HOST: + callHandlers(IRQ_SDIO_HOST) + case IRQ_ETH_MAC: + callHandlers(IRQ_ETH_MAC) + case IRQ_MCPWM0: + callHandlers(IRQ_MCPWM0) + case IRQ_MCPWM1: + callHandlers(IRQ_MCPWM1) + case IRQ_MCPWM2: + callHandlers(IRQ_MCPWM2) + case IRQ_MCPWM3: + callHandlers(IRQ_MCPWM3) + case IRQ_LEDC: + callHandlers(IRQ_LEDC) + case IRQ_EFUSE: + callHandlers(IRQ_EFUSE) + case IRQ_TWAI0: + callHandlers(IRQ_TWAI0) + case IRQ_RTC_CORE: + callHandlers(IRQ_RTC_CORE) + case IRQ_RMT: + callHandlers(IRQ_RMT) + case IRQ_PCNT: + callHandlers(IRQ_PCNT) + case IRQ_I2C_EXT0: + callHandlers(IRQ_I2C_EXT0) + case IRQ_I2C_EXT1: + callHandlers(IRQ_I2C_EXT1) + case IRQ_RSA: + callHandlers(IRQ_RSA) + case IRQ_SPI1_DMA: + callHandlers(IRQ_SPI1_DMA) + case IRQ_SPI2_DMA: + callHandlers(IRQ_SPI2_DMA) + case IRQ_SPI3_DMA: + callHandlers(IRQ_SPI3_DMA) + case IRQ_WDT: + callHandlers(IRQ_WDT) + case IRQ_TIMER1: + callHandlers(IRQ_TIMER1) + case IRQ_TIMER2: + callHandlers(IRQ_TIMER2) + case IRQ_TG0_T0_EDGE: + callHandlers(IRQ_TG0_T0_EDGE) + case IRQ_TG0_T1_EDGE: + callHandlers(IRQ_TG0_T1_EDGE) + case IRQ_TG0_WDT_EDGE: + callHandlers(IRQ_TG0_WDT_EDGE) + case IRQ_TG0_LACT_EDGE: + callHandlers(IRQ_TG0_LACT_EDGE) + case IRQ_TG1_T0_EDGE: + callHandlers(IRQ_TG1_T0_EDGE) + case IRQ_TG1_T1_EDGE: + callHandlers(IRQ_TG1_T1_EDGE) + case IRQ_TG1_WDT_EDGE: + callHandlers(IRQ_TG1_WDT_EDGE) + case IRQ_TG1_LACT_EDGE: + callHandlers(IRQ_TG1_LACT_EDGE) + case IRQ_MMU_IA: + callHandlers(IRQ_MMU_IA) + case IRQ_MPU_IA: + callHandlers(IRQ_MPU_IA) + case IRQ_CACHE_IA: + callHandlers(IRQ_CACHE_IA) + } +} + +// Peripherals. +var ( + // AES (Advanced Encryption Standard) Accelerator + AES = (*AES_Type)(unsafe.Pointer(uintptr(0x3ff01000))) + + // APB (Advanced Peripheral Bus) Controller + APB_CTRL = (*APB_CTRL_Type)(unsafe.Pointer(uintptr(0x3ff66000))) + + // BB Peripheral + BB = (*BB_Type)(unsafe.Pointer(uintptr(0x3ff5d000))) + + // DPORT Peripheral + DPORT = (*DPORT_Type)(unsafe.Pointer(uintptr(0x3ff00000))) + + // eFuse Controller + EFUSE = (*EFUSE_Type)(unsafe.Pointer(uintptr(0x3ff5a000))) + + // Ethernet DMA configuration and control registers + EMAC_DMA = (*EMAC_DMA_Type)(unsafe.Pointer(uintptr(0x3ff69000))) + + // Ethernet Clock, PHY type, and SRAM configuration registers + EMAC_EXT = (*EMAC_EXT_Type)(unsafe.Pointer(uintptr(0x3ff69800))) + + // Ethernet MAC configuration and control registers + EMAC_MAC = (*EMAC_MAC_Type)(unsafe.Pointer(uintptr(0x3ff6a000))) + + // FLASH_ENCRYPTION Peripheral + FLASH_ENCRYPTION = (*FLASH_ENCRYPTION_Type)(unsafe.Pointer(uintptr(0x3ff46000))) + + // FRC_TIMER Peripheral + FRC_TIMER = (*FRC_Type)(unsafe.Pointer(uintptr(0x3ff47000))) + + // General Purpose Input/Output + GPIO = (*GPIO_Type)(unsafe.Pointer(uintptr(0x3ff44000))) + + // Sigma-Delta Modulation + GPIO_SD = (*GPIO_SIGMADELTA_Type)(unsafe.Pointer(uintptr(0x3ff44f00))) + + // HINF Peripheral + HINF = (*HINF_Type)(unsafe.Pointer(uintptr(0x3ff4b000))) + + // I2C (Inter-Integrated Circuit) Controller 0 + I2C0 = (*I2C_Type)(unsafe.Pointer(uintptr(0x3ff53000))) + + // I2S (Inter-IC Sound) Controller 0 + I2S0 = (*I2S_Type)(unsafe.Pointer(uintptr(0x3ff4f000))) + + // Input/Output Multiplexer + IO_MUX = (*IO_MUX_Type)(unsafe.Pointer(uintptr(0x3ff49000))) + + // LED Control PWM (Pulse Width Modulation) + LEDC = (*LEDC_Type)(unsafe.Pointer(uintptr(0x3ff59000))) + + // Motor Control Pulse-Width Modulation 0 + MCPWM0 = (*MCPWM_Type)(unsafe.Pointer(uintptr(0x3ff5e000))) + + // NRX Peripheral + NRX = (*NRX_Type)(unsafe.Pointer(uintptr(0x3ff5cc00))) + + // Pulse Count Controller + PCNT = (*PCNT_Type)(unsafe.Pointer(uintptr(0x3ff57000))) + + // Remote Control + RMT = (*RMT_Type)(unsafe.Pointer(uintptr(0x3ff56000))) + + // Hardware Random Number Generator + RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x60035000))) + + // RSA (Rivest Shamir Adleman) Accelerator + RSA = (*RSA_Type)(unsafe.Pointer(uintptr(0x3ff02000))) + + // Real-Time Clock Control + RTC_CNTL = (*RTC_CNTL_Type)(unsafe.Pointer(uintptr(0x3ff48000))) + + // Low-power Input/Output + RTC_IO = (*RTC_GPIO_Type)(unsafe.Pointer(uintptr(0x3ff48400))) + + // Low-power I2C (Inter-Integrated Circuit) Controller + RTC_I2C = (*RTC_I2C_Type)(unsafe.Pointer(uintptr(0x3ff48c00))) + + // SD/MMC Host Controller + SDHOST = (*SDHOST_Type)(unsafe.Pointer(uintptr(0x3ff68000))) + + // SENS Peripheral + SENS = (*SENS_Type)(unsafe.Pointer(uintptr(0x3ff48800))) + + // SHA (Secure Hash Algorithm) Accelerator + SHA = (*SHA_Type)(unsafe.Pointer(uintptr(0x3ff03000))) + + // SLC Peripheral + SLC = (*SLC_Type)(unsafe.Pointer(uintptr(0x3ff58000))) + + // SLCHOST Peripheral + SLCHOST = (*SLCHOST_Type)(unsafe.Pointer(uintptr(0x3ff55000))) + + // SPI (Serial Peripheral Interface) Controller 0 + SPI0 = (*SPI_Type)(unsafe.Pointer(uintptr(0x3ff43000))) + + // Timer Group 0 + TIMG0 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x3ff5f000))) + + // Two-Wire Automotive Interface + TWAI0 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x3ff6b000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART0 = (*UART_Type)(unsafe.Pointer(uintptr(0x3ff40000))) + + // Universal Host Controller Interface 0 + UHCI0 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x3ff54000))) + + // I2C (Inter-Integrated Circuit) Controller 1 + I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x3ff67000))) + + // I2S (Inter-IC Sound) Controller 1 + I2S1 = (*I2S_Type)(unsafe.Pointer(uintptr(0x3ff6d000))) + + // Motor Control Pulse-Width Modulation 1 + MCPWM1 = (*MCPWM_Type)(unsafe.Pointer(uintptr(0x3ff6c000))) + + // SPI (Serial Peripheral Interface) Controller 1 + SPI1 = (*SPI_Type)(unsafe.Pointer(uintptr(0x3ff42000))) + + // SPI (Serial Peripheral Interface) Controller 2 + SPI2 = (*SPI_Type)(unsafe.Pointer(uintptr(0x3ff64000))) + + // SPI (Serial Peripheral Interface) Controller 3 + SPI3 = (*SPI_Type)(unsafe.Pointer(uintptr(0x3ff65000))) + + // Timer Group 1 + TIMG1 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x3ff60000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + UART1 = (*UART_Type)(unsafe.Pointer(uintptr(0x3ff50000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + UART2 = (*UART_Type)(unsafe.Pointer(uintptr(0x3ff6e000))) + + // Universal Host Controller Interface 1 + UHCI1 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x3ff4c000))) +) + +// AES (Advanced Encryption Standard) Accelerator +type AES_Type struct { + START volatile.Register32 // 0x0 + IDLE volatile.Register32 // 0x4 + MODE volatile.Register32 // 0x8 + _ [4]byte + KEY_0 volatile.Register32 // 0x10 + KEY_1 volatile.Register32 // 0x14 + KEY_2 volatile.Register32 // 0x18 + KEY_3 volatile.Register32 // 0x1C + KEY_4 volatile.Register32 // 0x20 + KEY_5 volatile.Register32 // 0x24 + KEY_6 volatile.Register32 // 0x28 + KEY_7 volatile.Register32 // 0x2C + TEXT_0 volatile.Register32 // 0x30 + TEXT_1 volatile.Register32 // 0x34 + TEXT_2 volatile.Register32 // 0x38 + TEXT_3 volatile.Register32 // 0x3C + ENDIAN volatile.Register32 // 0x40 +} + +// AES.START +func (o *AES_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetSTART() uint32 { + return volatile.LoadUint32(&o.START.Reg) & 0x1 +} + +// AES.IDLE +func (o *AES_Type) SetIDLE(value uint32) { + volatile.StoreUint32(&o.IDLE.Reg, volatile.LoadUint32(&o.IDLE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetIDLE() uint32 { + return volatile.LoadUint32(&o.IDLE.Reg) & 0x1 +} + +// AES.MODE +func (o *AES_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0xff +} + +// AES.KEY_0 +func (o *AES_Type) SetKEY_0_KEY(value uint32) { + volatile.StoreUint32(&o.KEY_0.Reg, volatile.LoadUint32(&o.KEY_0.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetKEY_0_KEY() uint32 { + return volatile.LoadUint32(&o.KEY_0.Reg) & 0xff +} + +// AES.KEY_1 +func (o *AES_Type) SetKEY_1_KEY(value uint32) { + volatile.StoreUint32(&o.KEY_1.Reg, volatile.LoadUint32(&o.KEY_1.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetKEY_1_KEY() uint32 { + return volatile.LoadUint32(&o.KEY_1.Reg) & 0xff +} + +// AES.KEY_2 +func (o *AES_Type) SetKEY_2_KEY(value uint32) { + volatile.StoreUint32(&o.KEY_2.Reg, volatile.LoadUint32(&o.KEY_2.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetKEY_2_KEY() uint32 { + return volatile.LoadUint32(&o.KEY_2.Reg) & 0xff +} + +// AES.KEY_3 +func (o *AES_Type) SetKEY_3_KEY(value uint32) { + volatile.StoreUint32(&o.KEY_3.Reg, volatile.LoadUint32(&o.KEY_3.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetKEY_3_KEY() uint32 { + return volatile.LoadUint32(&o.KEY_3.Reg) & 0xff +} + +// AES.KEY_4 +func (o *AES_Type) SetKEY_4_KEY(value uint32) { + volatile.StoreUint32(&o.KEY_4.Reg, volatile.LoadUint32(&o.KEY_4.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetKEY_4_KEY() uint32 { + return volatile.LoadUint32(&o.KEY_4.Reg) & 0xff +} + +// AES.KEY_5 +func (o *AES_Type) SetKEY_5_KEY(value uint32) { + volatile.StoreUint32(&o.KEY_5.Reg, volatile.LoadUint32(&o.KEY_5.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetKEY_5_KEY() uint32 { + return volatile.LoadUint32(&o.KEY_5.Reg) & 0xff +} + +// AES.KEY_6 +func (o *AES_Type) SetKEY_6_KEY(value uint32) { + volatile.StoreUint32(&o.KEY_6.Reg, volatile.LoadUint32(&o.KEY_6.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetKEY_6_KEY() uint32 { + return volatile.LoadUint32(&o.KEY_6.Reg) & 0xff +} + +// AES.KEY_7 +func (o *AES_Type) SetKEY_7_KEY(value uint32) { + volatile.StoreUint32(&o.KEY_7.Reg, volatile.LoadUint32(&o.KEY_7.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetKEY_7_KEY() uint32 { + return volatile.LoadUint32(&o.KEY_7.Reg) & 0xff +} + +// AES.TEXT_0 +func (o *AES_Type) SetTEXT_0_TEXT(value uint32) { + volatile.StoreUint32(&o.TEXT_0.Reg, volatile.LoadUint32(&o.TEXT_0.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetTEXT_0_TEXT() uint32 { + return volatile.LoadUint32(&o.TEXT_0.Reg) & 0xff +} + +// AES.TEXT_1 +func (o *AES_Type) SetTEXT_1_TEXT(value uint32) { + volatile.StoreUint32(&o.TEXT_1.Reg, volatile.LoadUint32(&o.TEXT_1.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetTEXT_1_TEXT() uint32 { + return volatile.LoadUint32(&o.TEXT_1.Reg) & 0xff +} + +// AES.TEXT_2 +func (o *AES_Type) SetTEXT_2_TEXT(value uint32) { + volatile.StoreUint32(&o.TEXT_2.Reg, volatile.LoadUint32(&o.TEXT_2.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetTEXT_2_TEXT() uint32 { + return volatile.LoadUint32(&o.TEXT_2.Reg) & 0xff +} + +// AES.TEXT_3 +func (o *AES_Type) SetTEXT_3_TEXT(value uint32) { + volatile.StoreUint32(&o.TEXT_3.Reg, volatile.LoadUint32(&o.TEXT_3.Reg)&^(0xff)|value) +} +func (o *AES_Type) GetTEXT_3_TEXT() uint32 { + return volatile.LoadUint32(&o.TEXT_3.Reg) & 0xff +} + +// AES.ENDIAN +func (o *AES_Type) SetENDIAN(value uint32) { + volatile.StoreUint32(&o.ENDIAN.Reg, volatile.LoadUint32(&o.ENDIAN.Reg)&^(0x3)|value) +} +func (o *AES_Type) GetENDIAN() uint32 { + return volatile.LoadUint32(&o.ENDIAN.Reg) & 0x3 +} + +// APB (Advanced Peripheral Bus) Controller +type APB_CTRL_Type struct { + SYSCLK_CONF volatile.Register32 // 0x0 + XTAL_TICK_CONF volatile.Register32 // 0x4 + PLL_TICK_CONF volatile.Register32 // 0x8 + CK8M_TICK_CONF volatile.Register32 // 0xC + APB_SARADC_CTRL volatile.Register32 // 0x10 + APB_SARADC_CTRL2 volatile.Register32 // 0x14 + APB_SARADC_FSM volatile.Register32 // 0x18 + APB_SARADC_SAR1_PATT_TAB1 volatile.Register32 // 0x1C + APB_SARADC_SAR1_PATT_TAB2 volatile.Register32 // 0x20 + APB_SARADC_SAR1_PATT_TAB3 volatile.Register32 // 0x24 + APB_SARADC_SAR1_PATT_TAB4 volatile.Register32 // 0x28 + APB_SARADC_SAR2_PATT_TAB1 volatile.Register32 // 0x2C + APB_SARADC_SAR2_PATT_TAB2 volatile.Register32 // 0x30 + APB_SARADC_SAR2_PATT_TAB3 volatile.Register32 // 0x34 + APB_SARADC_SAR2_PATT_TAB4 volatile.Register32 // 0x38 + APLL_TICK_CONF volatile.Register32 // 0x3C + _ [60]byte + DATE volatile.Register32 // 0x7C +} + +// APB_CTRL.SYSCLK_CONF +func (o *APB_CTRL_Type) SetSYSCLK_CONF_PRE_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x3ff)|value) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_PRE_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x3ff +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_CLK_320M_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_CLK_320M_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x400) >> 10 +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x800)|value<<11) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x800) >> 11 +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_RST_TICK_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_RST_TICK_CNT() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x1000) >> 12 +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_QUICK_CLK_CHNG(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_QUICK_CLK_CHNG() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x2000) >> 13 +} + +// APB_CTRL.XTAL_TICK_CONF +func (o *APB_CTRL_Type) SetXTAL_TICK_CONF_XTAL_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.XTAL_TICK_CONF.Reg, volatile.LoadUint32(&o.XTAL_TICK_CONF.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetXTAL_TICK_CONF_XTAL_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.XTAL_TICK_CONF.Reg) & 0xff +} + +// APB_CTRL.PLL_TICK_CONF +func (o *APB_CTRL_Type) SetPLL_TICK_CONF_PLL_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.PLL_TICK_CONF.Reg, volatile.LoadUint32(&o.PLL_TICK_CONF.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetPLL_TICK_CONF_PLL_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.PLL_TICK_CONF.Reg) & 0xff +} + +// APB_CTRL.CK8M_TICK_CONF +func (o *APB_CTRL_Type) SetCK8M_TICK_CONF_CK8M_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.CK8M_TICK_CONF.Reg, volatile.LoadUint32(&o.CK8M_TICK_CONF.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetCK8M_TICK_CONF_CK8M_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.CK8M_TICK_CONF.Reg) & 0xff +} + +// APB_CTRL.APB_SARADC_CTRL +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_START_FORCE(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_START_FORCE() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_START(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_START() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_SAR2_MUX(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_SAR2_MUX() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x4) >> 2 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_WORK_MODE(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_WORK_MODE() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x18) >> 3 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_SAR_SEL(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_SAR_SEL() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x20) >> 5 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_SAR_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_SAR_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x40) >> 6 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_SAR_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x7f80)|value<<7) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_SAR_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x7f80) >> 7 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_SAR1_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x78000)|value<<15) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_SAR1_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x78000) >> 15 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_SAR2_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x780000)|value<<19) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_SAR2_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x780000) >> 19 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_SAR1_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_SAR1_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x800000) >> 23 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_SAR2_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_SAR2_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_DATA_SAR_SEL(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_DATA_SAR_SEL() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL_SARADC_DATA_TO_I2S(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL_SARADC_DATA_TO_I2S() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL.Reg) & 0x4000000) >> 26 +} + +// APB_CTRL.APB_SARADC_CTRL2 +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL2.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL2.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_CTRL2.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL2.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL2.Reg)&^(0x1fe)|value<<1) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL2.Reg) & 0x1fe) >> 1 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL2_SARADC_SAR1_INV(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL2.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL2_SARADC_SAR1_INV() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL2.Reg) & 0x200) >> 9 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_CTRL2_SARADC_SAR2_INV(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_CTRL2.Reg, volatile.LoadUint32(&o.APB_SARADC_CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_CTRL2_SARADC_SAR2_INV() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_CTRL2.Reg) & 0x400) >> 10 +} + +// APB_CTRL.APB_SARADC_FSM +func (o *APB_CTRL_Type) SetAPB_SARADC_FSM_SARADC_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_FSM.Reg, volatile.LoadUint32(&o.APB_SARADC_FSM.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_FSM_SARADC_RSTB_WAIT() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_FSM.Reg) & 0xff +} +func (o *APB_CTRL_Type) SetAPB_SARADC_FSM_SARADC_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_FSM.Reg, volatile.LoadUint32(&o.APB_SARADC_FSM.Reg)&^(0xff00)|value<<8) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_FSM_SARADC_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_FSM.Reg) & 0xff00) >> 8 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_FSM_SARADC_START_WAIT(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_FSM.Reg, volatile.LoadUint32(&o.APB_SARADC_FSM.Reg)&^(0xff0000)|value<<16) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_FSM_SARADC_START_WAIT() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_FSM.Reg) & 0xff0000) >> 16 +} +func (o *APB_CTRL_Type) SetAPB_SARADC_FSM_SARADC_SAMPLE_CYCLE(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_FSM.Reg, volatile.LoadUint32(&o.APB_SARADC_FSM.Reg)&^(0xff000000)|value<<24) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_FSM_SARADC_SAMPLE_CYCLE() uint32 { + return (volatile.LoadUint32(&o.APB_SARADC_FSM.Reg) & 0xff000000) >> 24 +} + +// APB_CTRL.APB_SARADC_SAR1_PATT_TAB1 +func (o *APB_CTRL_Type) SetAPB_SARADC_SAR1_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_SAR1_PATT_TAB1.Reg, value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_SAR1_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_SAR1_PATT_TAB1.Reg) +} + +// APB_CTRL.APB_SARADC_SAR1_PATT_TAB2 +func (o *APB_CTRL_Type) SetAPB_SARADC_SAR1_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_SAR1_PATT_TAB2.Reg, value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_SAR1_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_SAR1_PATT_TAB2.Reg) +} + +// APB_CTRL.APB_SARADC_SAR1_PATT_TAB3 +func (o *APB_CTRL_Type) SetAPB_SARADC_SAR1_PATT_TAB3(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_SAR1_PATT_TAB3.Reg, value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_SAR1_PATT_TAB3() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_SAR1_PATT_TAB3.Reg) +} + +// APB_CTRL.APB_SARADC_SAR1_PATT_TAB4 +func (o *APB_CTRL_Type) SetAPB_SARADC_SAR1_PATT_TAB4(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_SAR1_PATT_TAB4.Reg, value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_SAR1_PATT_TAB4() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_SAR1_PATT_TAB4.Reg) +} + +// APB_CTRL.APB_SARADC_SAR2_PATT_TAB1 +func (o *APB_CTRL_Type) SetAPB_SARADC_SAR2_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_SAR2_PATT_TAB1.Reg, value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_SAR2_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_SAR2_PATT_TAB1.Reg) +} + +// APB_CTRL.APB_SARADC_SAR2_PATT_TAB2 +func (o *APB_CTRL_Type) SetAPB_SARADC_SAR2_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_SAR2_PATT_TAB2.Reg, value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_SAR2_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_SAR2_PATT_TAB2.Reg) +} + +// APB_CTRL.APB_SARADC_SAR2_PATT_TAB3 +func (o *APB_CTRL_Type) SetAPB_SARADC_SAR2_PATT_TAB3(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_SAR2_PATT_TAB3.Reg, value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_SAR2_PATT_TAB3() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_SAR2_PATT_TAB3.Reg) +} + +// APB_CTRL.APB_SARADC_SAR2_PATT_TAB4 +func (o *APB_CTRL_Type) SetAPB_SARADC_SAR2_PATT_TAB4(value uint32) { + volatile.StoreUint32(&o.APB_SARADC_SAR2_PATT_TAB4.Reg, value) +} +func (o *APB_CTRL_Type) GetAPB_SARADC_SAR2_PATT_TAB4() uint32 { + return volatile.LoadUint32(&o.APB_SARADC_SAR2_PATT_TAB4.Reg) +} + +// APB_CTRL.APLL_TICK_CONF +func (o *APB_CTRL_Type) SetAPLL_TICK_CONF_APLL_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.APLL_TICK_CONF.Reg, volatile.LoadUint32(&o.APLL_TICK_CONF.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetAPLL_TICK_CONF_APLL_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.APLL_TICK_CONF.Reg) & 0xff +} + +// APB_CTRL.DATE +func (o *APB_CTRL_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *APB_CTRL_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// BB Peripheral +type BB_Type struct { + _ [84]byte + BBPD_CTRL volatile.Register32 // 0x54 +} + +// BB.BBPD_CTRL: Baseband control register +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x1)|value) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x1 +} +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x2) >> 1 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x4) >> 2 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x8) >> 3 +} + +// DPORT Peripheral +type DPORT_Type struct { + PRO_BOOT_REMAP_CTRL volatile.Register32 // 0x0 + APP_BOOT_REMAP_CTRL volatile.Register32 // 0x4 + ACCESS_CHECK volatile.Register32 // 0x8 + PRO_DPORT_APB_MASK0 volatile.Register32 // 0xC + PRO_DPORT_APB_MASK1 volatile.Register32 // 0x10 + APP_DPORT_APB_MASK0 volatile.Register32 // 0x14 + APP_DPORT_APB_MASK1 volatile.Register32 // 0x18 + PERI_CLK_EN volatile.Register32 // 0x1C + PERI_RST_EN volatile.Register32 // 0x20 + WIFI_BB_CFG volatile.Register32 // 0x24 + WIFI_BB_CFG_2 volatile.Register32 // 0x28 + APPCPU_CTRL_A volatile.Register32 // 0x2C + APPCPU_CTRL_B volatile.Register32 // 0x30 + APPCPU_CTRL_C volatile.Register32 // 0x34 + APPCPU_CTRL_D volatile.Register32 // 0x38 + CPU_PER_CONF volatile.Register32 // 0x3C + PRO_CACHE_CTRL volatile.Register32 // 0x40 + PRO_CACHE_CTRL1 volatile.Register32 // 0x44 + PRO_CACHE_LOCK_0_ADDR volatile.Register32 // 0x48 + PRO_CACHE_LOCK_1_ADDR volatile.Register32 // 0x4C + PRO_CACHE_LOCK_2_ADDR volatile.Register32 // 0x50 + PRO_CACHE_LOCK_3_ADDR volatile.Register32 // 0x54 + APP_CACHE_CTRL volatile.Register32 // 0x58 + APP_CACHE_CTRL1 volatile.Register32 // 0x5C + APP_CACHE_LOCK_0_ADDR volatile.Register32 // 0x60 + APP_CACHE_LOCK_1_ADDR volatile.Register32 // 0x64 + APP_CACHE_LOCK_2_ADDR volatile.Register32 // 0x68 + APP_CACHE_LOCK_3_ADDR volatile.Register32 // 0x6C + TRACEMEM_MUX_MODE volatile.Register32 // 0x70 + PRO_TRACEMEM_ENA volatile.Register32 // 0x74 + APP_TRACEMEM_ENA volatile.Register32 // 0x78 + CACHE_MUX_MODE volatile.Register32 // 0x7C + IMMU_PAGE_MODE volatile.Register32 // 0x80 + DMMU_PAGE_MODE volatile.Register32 // 0x84 + ROM_MPU_ENA volatile.Register32 // 0x88 + MEM_PD_MASK volatile.Register32 // 0x8C + ROM_PD_CTRL volatile.Register32 // 0x90 + ROM_FO_CTRL volatile.Register32 // 0x94 + SRAM_PD_CTRL_0 volatile.Register32 // 0x98 + SRAM_PD_CTRL_1 volatile.Register32 // 0x9C + SRAM_FO_CTRL_0 volatile.Register32 // 0xA0 + SRAM_FO_CTRL_1 volatile.Register32 // 0xA4 + IRAM_DRAM_AHB_SEL volatile.Register32 // 0xA8 + TAG_FO_CTRL volatile.Register32 // 0xAC + AHB_LITE_MASK volatile.Register32 // 0xB0 + AHB_MPU_TABLE_0 volatile.Register32 // 0xB4 + AHB_MPU_TABLE_1 volatile.Register32 // 0xB8 + HOST_INF_SEL volatile.Register32 // 0xBC + PERIP_CLK_EN volatile.Register32 // 0xC0 + PERIP_RST_EN volatile.Register32 // 0xC4 + SLAVE_SPI_CONFIG volatile.Register32 // 0xC8 + WIFI_CLK_EN volatile.Register32 // 0xCC + CORE_RST_EN volatile.Register32 // 0xD0 + BT_LPCK_DIV_INT volatile.Register32 // 0xD4 + BT_LPCK_DIV_FRAC volatile.Register32 // 0xD8 + CPU_INTR_FROM_CPU_0 volatile.Register32 // 0xDC + CPU_INTR_FROM_CPU_1 volatile.Register32 // 0xE0 + CPU_INTR_FROM_CPU_2 volatile.Register32 // 0xE4 + CPU_INTR_FROM_CPU_3 volatile.Register32 // 0xE8 + PRO_INTR_STATUS_0 volatile.Register32 // 0xEC + PRO_INTR_STATUS_1 volatile.Register32 // 0xF0 + PRO_INTR_STATUS_2 volatile.Register32 // 0xF4 + APP_INTR_STATUS_0 volatile.Register32 // 0xF8 + APP_INTR_STATUS_1 volatile.Register32 // 0xFC + APP_INTR_STATUS_2 volatile.Register32 // 0x100 + PRO_MAC_INTR_MAP volatile.Register32 // 0x104 + PRO_MAC_NMI_MAP volatile.Register32 // 0x108 + PRO_BB_INT_MAP volatile.Register32 // 0x10C + PRO_BT_MAC_INT_MAP volatile.Register32 // 0x110 + PRO_BT_BB_INT_MAP volatile.Register32 // 0x114 + PRO_BT_BB_NMI_MAP volatile.Register32 // 0x118 + PRO_RWBT_IRQ_MAP volatile.Register32 // 0x11C + PRO_RWBLE_IRQ_MAP volatile.Register32 // 0x120 + PRO_RWBT_NMI_MAP volatile.Register32 // 0x124 + PRO_RWBLE_NMI_MAP volatile.Register32 // 0x128 + PRO_SLC0_INTR_MAP volatile.Register32 // 0x12C + PRO_SLC1_INTR_MAP volatile.Register32 // 0x130 + PRO_UHCI0_INTR_MAP volatile.Register32 // 0x134 + PRO_UHCI1_INTR_MAP volatile.Register32 // 0x138 + PRO_TG_T0_LEVEL_INT_MAP volatile.Register32 // 0x13C + PRO_TG_T1_LEVEL_INT_MAP volatile.Register32 // 0x140 + PRO_TG_WDT_LEVEL_INT_MAP volatile.Register32 // 0x144 + PRO_TG_LACT_LEVEL_INT_MAP volatile.Register32 // 0x148 + PRO_TG1_T0_LEVEL_INT_MAP volatile.Register32 // 0x14C + PRO_TG1_T1_LEVEL_INT_MAP volatile.Register32 // 0x150 + PRO_TG1_WDT_LEVEL_INT_MAP volatile.Register32 // 0x154 + PRO_TG1_LACT_LEVEL_INT_MAP volatile.Register32 // 0x158 + PRO_GPIO_INTERRUPT_MAP volatile.Register32 // 0x15C + PRO_GPIO_INTERRUPT_NMI_MAP volatile.Register32 // 0x160 + PRO_CPU_INTR_FROM_CPU_0_MAP volatile.Register32 // 0x164 + PRO_CPU_INTR_FROM_CPU_1_MAP volatile.Register32 // 0x168 + PRO_CPU_INTR_FROM_CPU_2_MAP volatile.Register32 // 0x16C + PRO_CPU_INTR_FROM_CPU_3_MAP volatile.Register32 // 0x170 + PRO_SPI_INTR_0_MAP volatile.Register32 // 0x174 + PRO_SPI_INTR_1_MAP volatile.Register32 // 0x178 + PRO_SPI_INTR_2_MAP volatile.Register32 // 0x17C + PRO_SPI_INTR_3_MAP volatile.Register32 // 0x180 + PRO_I2S0_INT_MAP volatile.Register32 // 0x184 + PRO_I2S1_INT_MAP volatile.Register32 // 0x188 + PRO_UART_INTR_MAP volatile.Register32 // 0x18C + PRO_UART1_INTR_MAP volatile.Register32 // 0x190 + PRO_UART2_INTR_MAP volatile.Register32 // 0x194 + PRO_SDIO_HOST_INTERRUPT_MAP volatile.Register32 // 0x198 + PRO_EMAC_INT_MAP volatile.Register32 // 0x19C + PRO_PWM0_INTR_MAP volatile.Register32 // 0x1A0 + PRO_PWM1_INTR_MAP volatile.Register32 // 0x1A4 + PRO_PWM2_INTR_MAP volatile.Register32 // 0x1A8 + PRO_PWM3_INTR_MAP volatile.Register32 // 0x1AC + PRO_LEDC_INT_MAP volatile.Register32 // 0x1B0 + PRO_EFUSE_INT_MAP volatile.Register32 // 0x1B4 + PRO_CAN_INT_MAP volatile.Register32 // 0x1B8 + PRO_RTC_CORE_INTR_MAP volatile.Register32 // 0x1BC + PRO_RMT_INTR_MAP volatile.Register32 // 0x1C0 + PRO_PCNT_INTR_MAP volatile.Register32 // 0x1C4 + PRO_I2C_EXT0_INTR_MAP volatile.Register32 // 0x1C8 + PRO_I2C_EXT1_INTR_MAP volatile.Register32 // 0x1CC + PRO_RSA_INTR_MAP volatile.Register32 // 0x1D0 + PRO_SPI1_DMA_INT_MAP volatile.Register32 // 0x1D4 + PRO_SPI2_DMA_INT_MAP volatile.Register32 // 0x1D8 + PRO_SPI3_DMA_INT_MAP volatile.Register32 // 0x1DC + PRO_WDG_INT_MAP volatile.Register32 // 0x1E0 + PRO_TIMER_INT1_MAP volatile.Register32 // 0x1E4 + PRO_TIMER_INT2_MAP volatile.Register32 // 0x1E8 + PRO_TG_T0_EDGE_INT_MAP volatile.Register32 // 0x1EC + PRO_TG_T1_EDGE_INT_MAP volatile.Register32 // 0x1F0 + PRO_TG_WDT_EDGE_INT_MAP volatile.Register32 // 0x1F4 + PRO_TG_LACT_EDGE_INT_MAP volatile.Register32 // 0x1F8 + PRO_TG1_T0_EDGE_INT_MAP volatile.Register32 // 0x1FC + PRO_TG1_T1_EDGE_INT_MAP volatile.Register32 // 0x200 + PRO_TG1_WDT_EDGE_INT_MAP volatile.Register32 // 0x204 + PRO_TG1_LACT_EDGE_INT_MAP volatile.Register32 // 0x208 + PRO_MMU_IA_INT_MAP volatile.Register32 // 0x20C + PRO_MPU_IA_INT_MAP volatile.Register32 // 0x210 + PRO_CACHE_IA_INT_MAP volatile.Register32 // 0x214 + APP_MAC_INTR_MAP volatile.Register32 // 0x218 + APP_MAC_NMI_MAP volatile.Register32 // 0x21C + APP_BB_INT_MAP volatile.Register32 // 0x220 + APP_BT_MAC_INT_MAP volatile.Register32 // 0x224 + APP_BT_BB_INT_MAP volatile.Register32 // 0x228 + APP_BT_BB_NMI_MAP volatile.Register32 // 0x22C + APP_RWBT_IRQ_MAP volatile.Register32 // 0x230 + APP_RWBLE_IRQ_MAP volatile.Register32 // 0x234 + APP_RWBT_NMI_MAP volatile.Register32 // 0x238 + APP_RWBLE_NMI_MAP volatile.Register32 // 0x23C + APP_SLC0_INTR_MAP volatile.Register32 // 0x240 + APP_SLC1_INTR_MAP volatile.Register32 // 0x244 + APP_UHCI0_INTR_MAP volatile.Register32 // 0x248 + APP_UHCI1_INTR_MAP volatile.Register32 // 0x24C + APP_TG_T0_LEVEL_INT_MAP volatile.Register32 // 0x250 + APP_TG_T1_LEVEL_INT_MAP volatile.Register32 // 0x254 + APP_TG_WDT_LEVEL_INT_MAP volatile.Register32 // 0x258 + APP_TG_LACT_LEVEL_INT_MAP volatile.Register32 // 0x25C + APP_TG1_T0_LEVEL_INT_MAP volatile.Register32 // 0x260 + APP_TG1_T1_LEVEL_INT_MAP volatile.Register32 // 0x264 + APP_TG1_WDT_LEVEL_INT_MAP volatile.Register32 // 0x268 + APP_TG1_LACT_LEVEL_INT_MAP volatile.Register32 // 0x26C + APP_GPIO_INTERRUPT_MAP volatile.Register32 // 0x270 + APP_GPIO_INTERRUPT_NMI_MAP volatile.Register32 // 0x274 + APP_CPU_INTR_FROM_CPU_0_MAP volatile.Register32 // 0x278 + APP_CPU_INTR_FROM_CPU_1_MAP volatile.Register32 // 0x27C + APP_CPU_INTR_FROM_CPU_2_MAP volatile.Register32 // 0x280 + APP_CPU_INTR_FROM_CPU_3_MAP volatile.Register32 // 0x284 + APP_SPI_INTR_0_MAP volatile.Register32 // 0x288 + APP_SPI_INTR_1_MAP volatile.Register32 // 0x28C + APP_SPI_INTR_2_MAP volatile.Register32 // 0x290 + APP_SPI_INTR_3_MAP volatile.Register32 // 0x294 + APP_I2S0_INT_MAP volatile.Register32 // 0x298 + APP_I2S1_INT_MAP volatile.Register32 // 0x29C + APP_UART_INTR_MAP volatile.Register32 // 0x2A0 + APP_UART1_INTR_MAP volatile.Register32 // 0x2A4 + APP_UART2_INTR_MAP volatile.Register32 // 0x2A8 + APP_SDIO_HOST_INTERRUPT_MAP volatile.Register32 // 0x2AC + APP_EMAC_INT_MAP volatile.Register32 // 0x2B0 + APP_PWM0_INTR_MAP volatile.Register32 // 0x2B4 + APP_PWM1_INTR_MAP volatile.Register32 // 0x2B8 + APP_PWM2_INTR_MAP volatile.Register32 // 0x2BC + APP_PWM3_INTR_MAP volatile.Register32 // 0x2C0 + APP_LEDC_INT_MAP volatile.Register32 // 0x2C4 + APP_EFUSE_INT_MAP volatile.Register32 // 0x2C8 + APP_CAN_INT_MAP volatile.Register32 // 0x2CC + APP_RTC_CORE_INTR_MAP volatile.Register32 // 0x2D0 + APP_RMT_INTR_MAP volatile.Register32 // 0x2D4 + APP_PCNT_INTR_MAP volatile.Register32 // 0x2D8 + APP_I2C_EXT0_INTR_MAP volatile.Register32 // 0x2DC + APP_I2C_EXT1_INTR_MAP volatile.Register32 // 0x2E0 + APP_RSA_INTR_MAP volatile.Register32 // 0x2E4 + APP_SPI1_DMA_INT_MAP volatile.Register32 // 0x2E8 + APP_SPI2_DMA_INT_MAP volatile.Register32 // 0x2EC + APP_SPI3_DMA_INT_MAP volatile.Register32 // 0x2F0 + APP_WDG_INT_MAP volatile.Register32 // 0x2F4 + APP_TIMER_INT1_MAP volatile.Register32 // 0x2F8 + APP_TIMER_INT2_MAP volatile.Register32 // 0x2FC + APP_TG_T0_EDGE_INT_MAP volatile.Register32 // 0x300 + APP_TG_T1_EDGE_INT_MAP volatile.Register32 // 0x304 + APP_TG_WDT_EDGE_INT_MAP volatile.Register32 // 0x308 + APP_TG_LACT_EDGE_INT_MAP volatile.Register32 // 0x30C + APP_TG1_T0_EDGE_INT_MAP volatile.Register32 // 0x310 + APP_TG1_T1_EDGE_INT_MAP volatile.Register32 // 0x314 + APP_TG1_WDT_EDGE_INT_MAP volatile.Register32 // 0x318 + APP_TG1_LACT_EDGE_INT_MAP volatile.Register32 // 0x31C + APP_MMU_IA_INT_MAP volatile.Register32 // 0x320 + APP_MPU_IA_INT_MAP volatile.Register32 // 0x324 + APP_CACHE_IA_INT_MAP volatile.Register32 // 0x328 + AHBLITE_MPU_TABLE_UART volatile.Register32 // 0x32C + AHBLITE_MPU_TABLE_SPI1 volatile.Register32 // 0x330 + AHBLITE_MPU_TABLE_SPI0 volatile.Register32 // 0x334 + AHBLITE_MPU_TABLE_GPIO volatile.Register32 // 0x338 + AHBLITE_MPU_TABLE_FE2 volatile.Register32 // 0x33C + AHBLITE_MPU_TABLE_FE volatile.Register32 // 0x340 + AHBLITE_MPU_TABLE_TIMER volatile.Register32 // 0x344 + AHBLITE_MPU_TABLE_RTC volatile.Register32 // 0x348 + AHBLITE_MPU_TABLE_IO_MUX volatile.Register32 // 0x34C + AHBLITE_MPU_TABLE_WDG volatile.Register32 // 0x350 + AHBLITE_MPU_TABLE_HINF volatile.Register32 // 0x354 + AHBLITE_MPU_TABLE_UHCI1 volatile.Register32 // 0x358 + AHBLITE_MPU_TABLE_MISC volatile.Register32 // 0x35C + AHBLITE_MPU_TABLE_I2C volatile.Register32 // 0x360 + AHBLITE_MPU_TABLE_I2S0 volatile.Register32 // 0x364 + AHBLITE_MPU_TABLE_UART1 volatile.Register32 // 0x368 + AHBLITE_MPU_TABLE_BT volatile.Register32 // 0x36C + AHBLITE_MPU_TABLE_BT_BUFFER volatile.Register32 // 0x370 + AHBLITE_MPU_TABLE_I2C_EXT0 volatile.Register32 // 0x374 + AHBLITE_MPU_TABLE_UHCI0 volatile.Register32 // 0x378 + AHBLITE_MPU_TABLE_SLCHOST volatile.Register32 // 0x37C + AHBLITE_MPU_TABLE_RMT volatile.Register32 // 0x380 + AHBLITE_MPU_TABLE_PCNT volatile.Register32 // 0x384 + AHBLITE_MPU_TABLE_SLC volatile.Register32 // 0x388 + AHBLITE_MPU_TABLE_LEDC volatile.Register32 // 0x38C + AHBLITE_MPU_TABLE_EFUSE volatile.Register32 // 0x390 + AHBLITE_MPU_TABLE_SPI_ENCRYPT volatile.Register32 // 0x394 + AHBLITE_MPU_TABLE_BB volatile.Register32 // 0x398 + AHBLITE_MPU_TABLE_PWM0 volatile.Register32 // 0x39C + AHBLITE_MPU_TABLE_TIMERGROUP volatile.Register32 // 0x3A0 + AHBLITE_MPU_TABLE_TIMERGROUP1 volatile.Register32 // 0x3A4 + AHBLITE_MPU_TABLE_SPI2 volatile.Register32 // 0x3A8 + AHBLITE_MPU_TABLE_SPI3 volatile.Register32 // 0x3AC + AHBLITE_MPU_TABLE_APB_CTRL volatile.Register32 // 0x3B0 + AHBLITE_MPU_TABLE_I2C_EXT1 volatile.Register32 // 0x3B4 + AHBLITE_MPU_TABLE_SDIO_HOST volatile.Register32 // 0x3B8 + AHBLITE_MPU_TABLE_EMAC volatile.Register32 // 0x3BC + AHBLITE_MPU_TABLE_CAN volatile.Register32 // 0x3C0 + AHBLITE_MPU_TABLE_PWM1 volatile.Register32 // 0x3C4 + AHBLITE_MPU_TABLE_I2S1 volatile.Register32 // 0x3C8 + AHBLITE_MPU_TABLE_UART2 volatile.Register32 // 0x3CC + AHBLITE_MPU_TABLE_PWM2 volatile.Register32 // 0x3D0 + AHBLITE_MPU_TABLE_PWM3 volatile.Register32 // 0x3D4 + AHBLITE_MPU_TABLE_RWBT volatile.Register32 // 0x3D8 + AHBLITE_MPU_TABLE_BTMAC volatile.Register32 // 0x3DC + AHBLITE_MPU_TABLE_WIFIMAC volatile.Register32 // 0x3E0 + AHBLITE_MPU_TABLE_PWR volatile.Register32 // 0x3E4 + MEM_ACCESS_DBUG0 volatile.Register32 // 0x3E8 + MEM_ACCESS_DBUG1 volatile.Register32 // 0x3EC + PRO_DCACHE_DBUG0 volatile.Register32 // 0x3F0 + PRO_DCACHE_DBUG1 volatile.Register32 // 0x3F4 + PRO_DCACHE_DBUG2 volatile.Register32 // 0x3F8 + PRO_DCACHE_DBUG3 volatile.Register32 // 0x3FC + PRO_DCACHE_DBUG4 volatile.Register32 // 0x400 + PRO_DCACHE_DBUG5 volatile.Register32 // 0x404 + PRO_DCACHE_DBUG6 volatile.Register32 // 0x408 + PRO_DCACHE_DBUG7 volatile.Register32 // 0x40C + PRO_DCACHE_DBUG8 volatile.Register32 // 0x410 + PRO_DCACHE_DBUG9 volatile.Register32 // 0x414 + APP_DCACHE_DBUG0 volatile.Register32 // 0x418 + APP_DCACHE_DBUG1 volatile.Register32 // 0x41C + APP_DCACHE_DBUG2 volatile.Register32 // 0x420 + APP_DCACHE_DBUG3 volatile.Register32 // 0x424 + APP_DCACHE_DBUG4 volatile.Register32 // 0x428 + APP_DCACHE_DBUG5 volatile.Register32 // 0x42C + APP_DCACHE_DBUG6 volatile.Register32 // 0x430 + APP_DCACHE_DBUG7 volatile.Register32 // 0x434 + APP_DCACHE_DBUG8 volatile.Register32 // 0x438 + APP_DCACHE_DBUG9 volatile.Register32 // 0x43C + PRO_CPU_RECORD_CTRL volatile.Register32 // 0x440 + PRO_CPU_RECORD_STATUS volatile.Register32 // 0x444 + PRO_CPU_RECORD_PID volatile.Register32 // 0x448 + PRO_CPU_RECORD_PDEBUGINST volatile.Register32 // 0x44C + PRO_CPU_RECORD_PDEBUGSTATUS volatile.Register32 // 0x450 + PRO_CPU_RECORD_PDEBUGDATA volatile.Register32 // 0x454 + PRO_CPU_RECORD_PDEBUGPC volatile.Register32 // 0x458 + PRO_CPU_RECORD_PDEBUGLS0STAT volatile.Register32 // 0x45C + PRO_CPU_RECORD_PDEBUGLS0ADDR volatile.Register32 // 0x460 + PRO_CPU_RECORD_PDEBUGLS0DATA volatile.Register32 // 0x464 + APP_CPU_RECORD_CTRL volatile.Register32 // 0x468 + APP_CPU_RECORD_STATUS volatile.Register32 // 0x46C + APP_CPU_RECORD_PID volatile.Register32 // 0x470 + APP_CPU_RECORD_PDEBUGINST volatile.Register32 // 0x474 + APP_CPU_RECORD_PDEBUGSTATUS volatile.Register32 // 0x478 + APP_CPU_RECORD_PDEBUGDATA volatile.Register32 // 0x47C + APP_CPU_RECORD_PDEBUGPC volatile.Register32 // 0x480 + APP_CPU_RECORD_PDEBUGLS0STAT volatile.Register32 // 0x484 + APP_CPU_RECORD_PDEBUGLS0ADDR volatile.Register32 // 0x488 + APP_CPU_RECORD_PDEBUGLS0DATA volatile.Register32 // 0x48C + RSA_PD_CTRL volatile.Register32 // 0x490 + ROM_MPU_TABLE0 volatile.Register32 // 0x494 + ROM_MPU_TABLE1 volatile.Register32 // 0x498 + ROM_MPU_TABLE2 volatile.Register32 // 0x49C + ROM_MPU_TABLE3 volatile.Register32 // 0x4A0 + SHROM_MPU_TABLE0 volatile.Register32 // 0x4A4 + SHROM_MPU_TABLE1 volatile.Register32 // 0x4A8 + SHROM_MPU_TABLE2 volatile.Register32 // 0x4AC + SHROM_MPU_TABLE3 volatile.Register32 // 0x4B0 + SHROM_MPU_TABLE4 volatile.Register32 // 0x4B4 + SHROM_MPU_TABLE5 volatile.Register32 // 0x4B8 + SHROM_MPU_TABLE6 volatile.Register32 // 0x4BC + SHROM_MPU_TABLE7 volatile.Register32 // 0x4C0 + SHROM_MPU_TABLE8 volatile.Register32 // 0x4C4 + SHROM_MPU_TABLE9 volatile.Register32 // 0x4C8 + SHROM_MPU_TABLE10 volatile.Register32 // 0x4CC + SHROM_MPU_TABLE11 volatile.Register32 // 0x4D0 + SHROM_MPU_TABLE12 volatile.Register32 // 0x4D4 + SHROM_MPU_TABLE13 volatile.Register32 // 0x4D8 + SHROM_MPU_TABLE14 volatile.Register32 // 0x4DC + SHROM_MPU_TABLE15 volatile.Register32 // 0x4E0 + SHROM_MPU_TABLE16 volatile.Register32 // 0x4E4 + SHROM_MPU_TABLE17 volatile.Register32 // 0x4E8 + SHROM_MPU_TABLE18 volatile.Register32 // 0x4EC + SHROM_MPU_TABLE19 volatile.Register32 // 0x4F0 + SHROM_MPU_TABLE20 volatile.Register32 // 0x4F4 + SHROM_MPU_TABLE21 volatile.Register32 // 0x4F8 + SHROM_MPU_TABLE22 volatile.Register32 // 0x4FC + SHROM_MPU_TABLE23 volatile.Register32 // 0x500 + IMMU_TABLE0 volatile.Register32 // 0x504 + IMMU_TABLE1 volatile.Register32 // 0x508 + IMMU_TABLE2 volatile.Register32 // 0x50C + IMMU_TABLE3 volatile.Register32 // 0x510 + IMMU_TABLE4 volatile.Register32 // 0x514 + IMMU_TABLE5 volatile.Register32 // 0x518 + IMMU_TABLE6 volatile.Register32 // 0x51C + IMMU_TABLE7 volatile.Register32 // 0x520 + IMMU_TABLE8 volatile.Register32 // 0x524 + IMMU_TABLE9 volatile.Register32 // 0x528 + IMMU_TABLE10 volatile.Register32 // 0x52C + IMMU_TABLE11 volatile.Register32 // 0x530 + IMMU_TABLE12 volatile.Register32 // 0x534 + IMMU_TABLE13 volatile.Register32 // 0x538 + IMMU_TABLE14 volatile.Register32 // 0x53C + IMMU_TABLE15 volatile.Register32 // 0x540 + DMMU_TABLE0 volatile.Register32 // 0x544 + DMMU_TABLE1 volatile.Register32 // 0x548 + DMMU_TABLE2 volatile.Register32 // 0x54C + DMMU_TABLE3 volatile.Register32 // 0x550 + DMMU_TABLE4 volatile.Register32 // 0x554 + DMMU_TABLE5 volatile.Register32 // 0x558 + DMMU_TABLE6 volatile.Register32 // 0x55C + DMMU_TABLE7 volatile.Register32 // 0x560 + DMMU_TABLE8 volatile.Register32 // 0x564 + DMMU_TABLE9 volatile.Register32 // 0x568 + DMMU_TABLE10 volatile.Register32 // 0x56C + DMMU_TABLE11 volatile.Register32 // 0x570 + DMMU_TABLE12 volatile.Register32 // 0x574 + DMMU_TABLE13 volatile.Register32 // 0x578 + DMMU_TABLE14 volatile.Register32 // 0x57C + DMMU_TABLE15 volatile.Register32 // 0x580 + PRO_INTRUSION_CTRL volatile.Register32 // 0x584 + PRO_INTRUSION_STATUS volatile.Register32 // 0x588 + APP_INTRUSION_CTRL volatile.Register32 // 0x58C + APP_INTRUSION_STATUS volatile.Register32 // 0x590 + FRONT_END_MEM_PD volatile.Register32 // 0x594 + MMU_IA_INT_EN volatile.Register32 // 0x598 + MPU_IA_INT_EN volatile.Register32 // 0x59C + CACHE_IA_INT_EN volatile.Register32 // 0x5A0 + SECURE_BOOT_CTRL volatile.Register32 // 0x5A4 + SPI_DMA_CHAN_SEL volatile.Register32 // 0x5A8 + PRO_VECBASE_CTRL volatile.Register32 // 0x5AC + PRO_VECBASE_SET volatile.Register32 // 0x5B0 + APP_VECBASE_CTRL volatile.Register32 // 0x5B4 + APP_VECBASE_SET volatile.Register32 // 0x5B8 + _ [2624]byte + DATE volatile.Register32 // 0xFFC +} + +// DPORT.PRO_BOOT_REMAP_CTRL +func (o *DPORT_Type) SetPRO_BOOT_REMAP_CTRL_PRO_BOOT_REMAP(value uint32) { + volatile.StoreUint32(&o.PRO_BOOT_REMAP_CTRL.Reg, volatile.LoadUint32(&o.PRO_BOOT_REMAP_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_BOOT_REMAP_CTRL_PRO_BOOT_REMAP() uint32 { + return volatile.LoadUint32(&o.PRO_BOOT_REMAP_CTRL.Reg) & 0x1 +} + +// DPORT.APP_BOOT_REMAP_CTRL +func (o *DPORT_Type) SetAPP_BOOT_REMAP_CTRL_APP_BOOT_REMAP(value uint32) { + volatile.StoreUint32(&o.APP_BOOT_REMAP_CTRL.Reg, volatile.LoadUint32(&o.APP_BOOT_REMAP_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPP_BOOT_REMAP_CTRL_APP_BOOT_REMAP() uint32 { + return volatile.LoadUint32(&o.APP_BOOT_REMAP_CTRL.Reg) & 0x1 +} + +// DPORT.ACCESS_CHECK +func (o *DPORT_Type) SetACCESS_CHECK_PRO(value uint32) { + volatile.StoreUint32(&o.ACCESS_CHECK.Reg, volatile.LoadUint32(&o.ACCESS_CHECK.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetACCESS_CHECK_PRO() uint32 { + return volatile.LoadUint32(&o.ACCESS_CHECK.Reg) & 0x1 +} +func (o *DPORT_Type) SetACCESS_CHECK_APP(value uint32) { + volatile.StoreUint32(&o.ACCESS_CHECK.Reg, volatile.LoadUint32(&o.ACCESS_CHECK.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetACCESS_CHECK_APP() uint32 { + return (volatile.LoadUint32(&o.ACCESS_CHECK.Reg) & 0x100) >> 8 +} + +// DPORT.PRO_DPORT_APB_MASK0 +func (o *DPORT_Type) SetPRO_DPORT_APB_MASK0(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_APB_MASK0.Reg, value) +} +func (o *DPORT_Type) GetPRO_DPORT_APB_MASK0() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_APB_MASK0.Reg) +} + +// DPORT.PRO_DPORT_APB_MASK1 +func (o *DPORT_Type) SetPRO_DPORT_APB_MASK1(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_APB_MASK1.Reg, value) +} +func (o *DPORT_Type) GetPRO_DPORT_APB_MASK1() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_APB_MASK1.Reg) +} + +// DPORT.APP_DPORT_APB_MASK0 +func (o *DPORT_Type) SetAPP_DPORT_APB_MASK0(value uint32) { + volatile.StoreUint32(&o.APP_DPORT_APB_MASK0.Reg, value) +} +func (o *DPORT_Type) GetAPP_DPORT_APB_MASK0() uint32 { + return volatile.LoadUint32(&o.APP_DPORT_APB_MASK0.Reg) +} + +// DPORT.APP_DPORT_APB_MASK1 +func (o *DPORT_Type) SetAPP_DPORT_APB_MASK1(value uint32) { + volatile.StoreUint32(&o.APP_DPORT_APB_MASK1.Reg, value) +} +func (o *DPORT_Type) GetAPP_DPORT_APB_MASK1() uint32 { + return volatile.LoadUint32(&o.APP_DPORT_APB_MASK1.Reg) +} + +// DPORT.PERI_CLK_EN +func (o *DPORT_Type) SetPERI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_EN.Reg, value) +} +func (o *DPORT_Type) GetPERI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_EN.Reg) +} + +// DPORT.PERI_RST_EN +func (o *DPORT_Type) SetPERI_RST_EN(value uint32) { + volatile.StoreUint32(&o.PERI_RST_EN.Reg, value) +} +func (o *DPORT_Type) GetPERI_RST_EN() uint32 { + return volatile.LoadUint32(&o.PERI_RST_EN.Reg) +} + +// DPORT.WIFI_BB_CFG +func (o *DPORT_Type) SetWIFI_BB_CFG(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG.Reg, value) +} +func (o *DPORT_Type) GetWIFI_BB_CFG() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG.Reg) +} + +// DPORT.WIFI_BB_CFG_2 +func (o *DPORT_Type) SetWIFI_BB_CFG_2(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG_2.Reg, value) +} +func (o *DPORT_Type) GetWIFI_BB_CFG_2() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG_2.Reg) +} + +// DPORT.APPCPU_CTRL_A +func (o *DPORT_Type) SetAPPCPU_CTRL_A_APPCPU_RESETTING(value uint32) { + volatile.StoreUint32(&o.APPCPU_CTRL_A.Reg, volatile.LoadUint32(&o.APPCPU_CTRL_A.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPPCPU_CTRL_A_APPCPU_RESETTING() uint32 { + return volatile.LoadUint32(&o.APPCPU_CTRL_A.Reg) & 0x1 +} + +// DPORT.APPCPU_CTRL_B +func (o *DPORT_Type) SetAPPCPU_CTRL_B_APPCPU_CLKGATE_EN(value uint32) { + volatile.StoreUint32(&o.APPCPU_CTRL_B.Reg, volatile.LoadUint32(&o.APPCPU_CTRL_B.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPPCPU_CTRL_B_APPCPU_CLKGATE_EN() uint32 { + return volatile.LoadUint32(&o.APPCPU_CTRL_B.Reg) & 0x1 +} + +// DPORT.APPCPU_CTRL_C +func (o *DPORT_Type) SetAPPCPU_CTRL_C_APPCPU_RUNSTALL(value uint32) { + volatile.StoreUint32(&o.APPCPU_CTRL_C.Reg, volatile.LoadUint32(&o.APPCPU_CTRL_C.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPPCPU_CTRL_C_APPCPU_RUNSTALL() uint32 { + return volatile.LoadUint32(&o.APPCPU_CTRL_C.Reg) & 0x1 +} + +// DPORT.APPCPU_CTRL_D +func (o *DPORT_Type) SetAPPCPU_CTRL_D(value uint32) { + volatile.StoreUint32(&o.APPCPU_CTRL_D.Reg, value) +} +func (o *DPORT_Type) GetAPPCPU_CTRL_D() uint32 { + return volatile.LoadUint32(&o.APPCPU_CTRL_D.Reg) +} + +// DPORT.CPU_PER_CONF +func (o *DPORT_Type) SetCPU_PER_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetCPU_PER_CONF_CPUPERIOD_SEL() uint32 { + return volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x3 +} +func (o *DPORT_Type) SetCPU_PER_CONF_LOWSPEED_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetCPU_PER_CONF_LOWSPEED_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetCPU_PER_CONF_FAST_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetCPU_PER_CONF_FAST_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x8) >> 3 +} + +// DPORT.PRO_CACHE_CTRL +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_CACHE_MODE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_CACHE_MODE() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_CACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_CACHE_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_CACHE_FLUSH_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_CACHE_FLUSH_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_CACHE_FLUSH_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_CACHE_FLUSH_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x20) >> 5 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_CACHE_LOCK_0_EN(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_CACHE_LOCK_0_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x40) >> 6 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_CACHE_LOCK_1_EN(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_CACHE_LOCK_1_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x80) >> 7 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_CACHE_LOCK_2_EN(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_CACHE_LOCK_2_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_CACHE_LOCK_3_EN(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_CACHE_LOCK_3_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_SINGLE_IRAM_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_SINGLE_IRAM_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_DRAM_SPLIT(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_DRAM_SPLIT() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x800) >> 11 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_AHB_SPI_REQ(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_AHB_SPI_REQ() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_SLAVE_REQ(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_SLAVE_REQ() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x2000) >> 13 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_AHB_SPI_REQ(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_AHB_SPI_REQ() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x4000) >> 14 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_SLAVE_REQ(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_SLAVE_REQ() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x8000) >> 15 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL_PRO_DRAM_HL(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL_PRO_DRAM_HL() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL.Reg) & 0x10000) >> 16 +} + +// DPORT.PRO_CACHE_CTRL1 +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM0(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM0() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x1 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM1(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM1() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CACHE_MASK_IROM0(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CACHE_MASK_IROM0() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CACHE_MASK_DRAM1(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CACHE_MASK_DRAM1() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CACHE_MASK_DROM0(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CACHE_MASK_DROM0() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CACHE_MASK_OPSDRAM(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x20)|value<<5) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CACHE_MASK_OPSDRAM() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x20) >> 5 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CMMU_SRAM_PAGE_MODE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x1c0)|value<<6) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CMMU_SRAM_PAGE_MODE() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x1c0) >> 6 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CMMU_FLASH_PAGE_MODE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x600)|value<<9) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CMMU_FLASH_PAGE_MODE() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x600) >> 9 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CMMU_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x800)|value<<11) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CMMU_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x800) >> 11 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CMMU_PD(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CMMU_PD() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetPRO_CACHE_CTRL1_PRO_CACHE_MMU_IA_CLR(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetPRO_CACHE_CTRL1_PRO_CACHE_MMU_IA_CLR() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_CTRL1.Reg) & 0x2000) >> 13 +} + +// DPORT.PRO_CACHE_LOCK_0_ADDR +func (o *DPORT_Type) SetPRO_CACHE_LOCK_0_ADDR_PRE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_0_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_0_ADDR.Reg)&^(0x3fff)|value) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_0_ADDR_PRE() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_LOCK_0_ADDR.Reg) & 0x3fff +} +func (o *DPORT_Type) SetPRO_CACHE_LOCK_0_ADDR_MIN(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_0_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_0_ADDR.Reg)&^(0x3c000)|value<<14) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_0_ADDR_MIN() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_LOCK_0_ADDR.Reg) & 0x3c000) >> 14 +} +func (o *DPORT_Type) SetPRO_CACHE_LOCK_0_ADDR_MAX(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_0_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_0_ADDR.Reg)&^(0x3c0000)|value<<18) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_0_ADDR_MAX() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_LOCK_0_ADDR.Reg) & 0x3c0000) >> 18 +} + +// DPORT.PRO_CACHE_LOCK_1_ADDR +func (o *DPORT_Type) SetPRO_CACHE_LOCK_1_ADDR_PRE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_1_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_1_ADDR.Reg)&^(0x3fff)|value) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_1_ADDR_PRE() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_LOCK_1_ADDR.Reg) & 0x3fff +} +func (o *DPORT_Type) SetPRO_CACHE_LOCK_1_ADDR_MIN(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_1_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_1_ADDR.Reg)&^(0x3c000)|value<<14) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_1_ADDR_MIN() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_LOCK_1_ADDR.Reg) & 0x3c000) >> 14 +} +func (o *DPORT_Type) SetPRO_CACHE_LOCK_1_ADDR_MAX(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_1_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_1_ADDR.Reg)&^(0x3c0000)|value<<18) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_1_ADDR_MAX() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_LOCK_1_ADDR.Reg) & 0x3c0000) >> 18 +} + +// DPORT.PRO_CACHE_LOCK_2_ADDR +func (o *DPORT_Type) SetPRO_CACHE_LOCK_2_ADDR_PRE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_2_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_2_ADDR.Reg)&^(0x3fff)|value) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_2_ADDR_PRE() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_LOCK_2_ADDR.Reg) & 0x3fff +} +func (o *DPORT_Type) SetPRO_CACHE_LOCK_2_ADDR_MIN(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_2_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_2_ADDR.Reg)&^(0x3c000)|value<<14) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_2_ADDR_MIN() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_LOCK_2_ADDR.Reg) & 0x3c000) >> 14 +} +func (o *DPORT_Type) SetPRO_CACHE_LOCK_2_ADDR_MAX(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_2_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_2_ADDR.Reg)&^(0x3c0000)|value<<18) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_2_ADDR_MAX() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_LOCK_2_ADDR.Reg) & 0x3c0000) >> 18 +} + +// DPORT.PRO_CACHE_LOCK_3_ADDR +func (o *DPORT_Type) SetPRO_CACHE_LOCK_3_ADDR_PRE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_3_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_3_ADDR.Reg)&^(0x3fff)|value) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_3_ADDR_PRE() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_LOCK_3_ADDR.Reg) & 0x3fff +} +func (o *DPORT_Type) SetPRO_CACHE_LOCK_3_ADDR_MIN(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_3_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_3_ADDR.Reg)&^(0x3c000)|value<<14) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_3_ADDR_MIN() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_LOCK_3_ADDR.Reg) & 0x3c000) >> 14 +} +func (o *DPORT_Type) SetPRO_CACHE_LOCK_3_ADDR_MAX(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_LOCK_3_ADDR.Reg, volatile.LoadUint32(&o.PRO_CACHE_LOCK_3_ADDR.Reg)&^(0x3c0000)|value<<18) +} +func (o *DPORT_Type) GetPRO_CACHE_LOCK_3_ADDR_MAX() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_LOCK_3_ADDR.Reg) & 0x3c0000) >> 18 +} + +// DPORT.APP_CACHE_CTRL +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_CACHE_MODE(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_CACHE_MODE() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_CACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_CACHE_ENABLE() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_CACHE_FLUSH_ENA(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_CACHE_FLUSH_ENA() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_CACHE_FLUSH_DONE(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_CACHE_FLUSH_DONE() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x20) >> 5 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_CACHE_LOCK_0_EN(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_CACHE_LOCK_0_EN() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x40) >> 6 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_CACHE_LOCK_1_EN(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_CACHE_LOCK_1_EN() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x80) >> 7 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_CACHE_LOCK_2_EN(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_CACHE_LOCK_2_EN() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_CACHE_LOCK_3_EN(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_CACHE_LOCK_3_EN() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_SINGLE_IRAM_ENA(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_SINGLE_IRAM_ENA() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_DRAM_SPLIT(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_DRAM_SPLIT() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x800) >> 11 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_AHB_SPI_REQ(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_AHB_SPI_REQ() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_SLAVE_REQ(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_SLAVE_REQ() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x2000) >> 13 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL_APP_DRAM_HL(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL_APP_DRAM_HL() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL.Reg) & 0x4000) >> 14 +} + +// DPORT.APP_CACHE_CTRL1 +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CACHE_MASK_IRAM0(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CACHE_MASK_IRAM0() uint32 { + return volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x1 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CACHE_MASK_IRAM1(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CACHE_MASK_IRAM1() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CACHE_MASK_IROM0(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CACHE_MASK_IROM0() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CACHE_MASK_DRAM1(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CACHE_MASK_DRAM1() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CACHE_MASK_DROM0(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CACHE_MASK_DROM0() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CACHE_MASK_OPSDRAM(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x20)|value<<5) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CACHE_MASK_OPSDRAM() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x20) >> 5 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CMMU_SRAM_PAGE_MODE(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x1c0)|value<<6) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CMMU_SRAM_PAGE_MODE() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x1c0) >> 6 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CMMU_FLASH_PAGE_MODE(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x600)|value<<9) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CMMU_FLASH_PAGE_MODE() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x600) >> 9 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CMMU_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x800)|value<<11) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CMMU_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x800) >> 11 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CMMU_PD(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CMMU_PD() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetAPP_CACHE_CTRL1_APP_CACHE_MMU_IA_CLR(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_CTRL1.Reg, volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetAPP_CACHE_CTRL1_APP_CACHE_MMU_IA_CLR() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_CTRL1.Reg) & 0x2000) >> 13 +} + +// DPORT.APP_CACHE_LOCK_0_ADDR +func (o *DPORT_Type) SetAPP_CACHE_LOCK_0_ADDR_PRE(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_0_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_0_ADDR.Reg)&^(0x3fff)|value) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_0_ADDR_PRE() uint32 { + return volatile.LoadUint32(&o.APP_CACHE_LOCK_0_ADDR.Reg) & 0x3fff +} +func (o *DPORT_Type) SetAPP_CACHE_LOCK_0_ADDR_MIN(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_0_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_0_ADDR.Reg)&^(0x3c000)|value<<14) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_0_ADDR_MIN() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_LOCK_0_ADDR.Reg) & 0x3c000) >> 14 +} +func (o *DPORT_Type) SetAPP_CACHE_LOCK_0_ADDR_MAX(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_0_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_0_ADDR.Reg)&^(0x3c0000)|value<<18) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_0_ADDR_MAX() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_LOCK_0_ADDR.Reg) & 0x3c0000) >> 18 +} + +// DPORT.APP_CACHE_LOCK_1_ADDR +func (o *DPORT_Type) SetAPP_CACHE_LOCK_1_ADDR_PRE(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_1_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_1_ADDR.Reg)&^(0x3fff)|value) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_1_ADDR_PRE() uint32 { + return volatile.LoadUint32(&o.APP_CACHE_LOCK_1_ADDR.Reg) & 0x3fff +} +func (o *DPORT_Type) SetAPP_CACHE_LOCK_1_ADDR_MIN(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_1_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_1_ADDR.Reg)&^(0x3c000)|value<<14) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_1_ADDR_MIN() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_LOCK_1_ADDR.Reg) & 0x3c000) >> 14 +} +func (o *DPORT_Type) SetAPP_CACHE_LOCK_1_ADDR_MAX(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_1_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_1_ADDR.Reg)&^(0x3c0000)|value<<18) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_1_ADDR_MAX() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_LOCK_1_ADDR.Reg) & 0x3c0000) >> 18 +} + +// DPORT.APP_CACHE_LOCK_2_ADDR +func (o *DPORT_Type) SetAPP_CACHE_LOCK_2_ADDR_PRE(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_2_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_2_ADDR.Reg)&^(0x3fff)|value) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_2_ADDR_PRE() uint32 { + return volatile.LoadUint32(&o.APP_CACHE_LOCK_2_ADDR.Reg) & 0x3fff +} +func (o *DPORT_Type) SetAPP_CACHE_LOCK_2_ADDR_MIN(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_2_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_2_ADDR.Reg)&^(0x3c000)|value<<14) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_2_ADDR_MIN() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_LOCK_2_ADDR.Reg) & 0x3c000) >> 14 +} +func (o *DPORT_Type) SetAPP_CACHE_LOCK_2_ADDR_MAX(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_2_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_2_ADDR.Reg)&^(0x3c0000)|value<<18) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_2_ADDR_MAX() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_LOCK_2_ADDR.Reg) & 0x3c0000) >> 18 +} + +// DPORT.APP_CACHE_LOCK_3_ADDR +func (o *DPORT_Type) SetAPP_CACHE_LOCK_3_ADDR_PRE(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_3_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_3_ADDR.Reg)&^(0x3fff)|value) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_3_ADDR_PRE() uint32 { + return volatile.LoadUint32(&o.APP_CACHE_LOCK_3_ADDR.Reg) & 0x3fff +} +func (o *DPORT_Type) SetAPP_CACHE_LOCK_3_ADDR_MIN(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_3_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_3_ADDR.Reg)&^(0x3c000)|value<<14) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_3_ADDR_MIN() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_LOCK_3_ADDR.Reg) & 0x3c000) >> 14 +} +func (o *DPORT_Type) SetAPP_CACHE_LOCK_3_ADDR_MAX(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_LOCK_3_ADDR.Reg, volatile.LoadUint32(&o.APP_CACHE_LOCK_3_ADDR.Reg)&^(0x3c0000)|value<<18) +} +func (o *DPORT_Type) GetAPP_CACHE_LOCK_3_ADDR_MAX() uint32 { + return (volatile.LoadUint32(&o.APP_CACHE_LOCK_3_ADDR.Reg) & 0x3c0000) >> 18 +} + +// DPORT.TRACEMEM_MUX_MODE +func (o *DPORT_Type) SetTRACEMEM_MUX_MODE(value uint32) { + volatile.StoreUint32(&o.TRACEMEM_MUX_MODE.Reg, volatile.LoadUint32(&o.TRACEMEM_MUX_MODE.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetTRACEMEM_MUX_MODE() uint32 { + return volatile.LoadUint32(&o.TRACEMEM_MUX_MODE.Reg) & 0x3 +} + +// DPORT.PRO_TRACEMEM_ENA +func (o *DPORT_Type) SetPRO_TRACEMEM_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_TRACEMEM_ENA.Reg, volatile.LoadUint32(&o.PRO_TRACEMEM_ENA.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_TRACEMEM_ENA() uint32 { + return volatile.LoadUint32(&o.PRO_TRACEMEM_ENA.Reg) & 0x1 +} + +// DPORT.APP_TRACEMEM_ENA +func (o *DPORT_Type) SetAPP_TRACEMEM_ENA(value uint32) { + volatile.StoreUint32(&o.APP_TRACEMEM_ENA.Reg, volatile.LoadUint32(&o.APP_TRACEMEM_ENA.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPP_TRACEMEM_ENA() uint32 { + return volatile.LoadUint32(&o.APP_TRACEMEM_ENA.Reg) & 0x1 +} + +// DPORT.CACHE_MUX_MODE +func (o *DPORT_Type) SetCACHE_MUX_MODE(value uint32) { + volatile.StoreUint32(&o.CACHE_MUX_MODE.Reg, volatile.LoadUint32(&o.CACHE_MUX_MODE.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetCACHE_MUX_MODE() uint32 { + return volatile.LoadUint32(&o.CACHE_MUX_MODE.Reg) & 0x3 +} + +// DPORT.IMMU_PAGE_MODE +func (o *DPORT_Type) SetIMMU_PAGE_MODE_INTERNAL_SRAM_IMMU_ENA(value uint32) { + volatile.StoreUint32(&o.IMMU_PAGE_MODE.Reg, volatile.LoadUint32(&o.IMMU_PAGE_MODE.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetIMMU_PAGE_MODE_INTERNAL_SRAM_IMMU_ENA() uint32 { + return volatile.LoadUint32(&o.IMMU_PAGE_MODE.Reg) & 0x1 +} +func (o *DPORT_Type) SetIMMU_PAGE_MODE(value uint32) { + volatile.StoreUint32(&o.IMMU_PAGE_MODE.Reg, volatile.LoadUint32(&o.IMMU_PAGE_MODE.Reg)&^(0x6)|value<<1) +} +func (o *DPORT_Type) GetIMMU_PAGE_MODE() uint32 { + return (volatile.LoadUint32(&o.IMMU_PAGE_MODE.Reg) & 0x6) >> 1 +} + +// DPORT.DMMU_PAGE_MODE +func (o *DPORT_Type) SetDMMU_PAGE_MODE_INTERNAL_SRAM_DMMU_ENA(value uint32) { + volatile.StoreUint32(&o.DMMU_PAGE_MODE.Reg, volatile.LoadUint32(&o.DMMU_PAGE_MODE.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetDMMU_PAGE_MODE_INTERNAL_SRAM_DMMU_ENA() uint32 { + return volatile.LoadUint32(&o.DMMU_PAGE_MODE.Reg) & 0x1 +} +func (o *DPORT_Type) SetDMMU_PAGE_MODE(value uint32) { + volatile.StoreUint32(&o.DMMU_PAGE_MODE.Reg, volatile.LoadUint32(&o.DMMU_PAGE_MODE.Reg)&^(0x6)|value<<1) +} +func (o *DPORT_Type) GetDMMU_PAGE_MODE() uint32 { + return (volatile.LoadUint32(&o.DMMU_PAGE_MODE.Reg) & 0x6) >> 1 +} + +// DPORT.ROM_MPU_ENA +func (o *DPORT_Type) SetROM_MPU_ENA_SHARE_ROM_MPU_ENA(value uint32) { + volatile.StoreUint32(&o.ROM_MPU_ENA.Reg, volatile.LoadUint32(&o.ROM_MPU_ENA.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetROM_MPU_ENA_SHARE_ROM_MPU_ENA() uint32 { + return volatile.LoadUint32(&o.ROM_MPU_ENA.Reg) & 0x1 +} +func (o *DPORT_Type) SetROM_MPU_ENA_PRO_ROM_MPU_ENA(value uint32) { + volatile.StoreUint32(&o.ROM_MPU_ENA.Reg, volatile.LoadUint32(&o.ROM_MPU_ENA.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetROM_MPU_ENA_PRO_ROM_MPU_ENA() uint32 { + return (volatile.LoadUint32(&o.ROM_MPU_ENA.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetROM_MPU_ENA_APP_ROM_MPU_ENA(value uint32) { + volatile.StoreUint32(&o.ROM_MPU_ENA.Reg, volatile.LoadUint32(&o.ROM_MPU_ENA.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetROM_MPU_ENA_APP_ROM_MPU_ENA() uint32 { + return (volatile.LoadUint32(&o.ROM_MPU_ENA.Reg) & 0x4) >> 2 +} + +// DPORT.MEM_PD_MASK +func (o *DPORT_Type) SetMEM_PD_MASK_LSLP_MEM_PD_MASK(value uint32) { + volatile.StoreUint32(&o.MEM_PD_MASK.Reg, volatile.LoadUint32(&o.MEM_PD_MASK.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetMEM_PD_MASK_LSLP_MEM_PD_MASK() uint32 { + return volatile.LoadUint32(&o.MEM_PD_MASK.Reg) & 0x1 +} + +// DPORT.ROM_PD_CTRL +func (o *DPORT_Type) SetROM_PD_CTRL_PRO_ROM_PD(value uint32) { + volatile.StoreUint32(&o.ROM_PD_CTRL.Reg, volatile.LoadUint32(&o.ROM_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetROM_PD_CTRL_PRO_ROM_PD() uint32 { + return volatile.LoadUint32(&o.ROM_PD_CTRL.Reg) & 0x1 +} +func (o *DPORT_Type) SetROM_PD_CTRL_APP_ROM_PD(value uint32) { + volatile.StoreUint32(&o.ROM_PD_CTRL.Reg, volatile.LoadUint32(&o.ROM_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetROM_PD_CTRL_APP_ROM_PD() uint32 { + return (volatile.LoadUint32(&o.ROM_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetROM_PD_CTRL_SHARE_ROM_PD(value uint32) { + volatile.StoreUint32(&o.ROM_PD_CTRL.Reg, volatile.LoadUint32(&o.ROM_PD_CTRL.Reg)&^(0xfc)|value<<2) +} +func (o *DPORT_Type) GetROM_PD_CTRL_SHARE_ROM_PD() uint32 { + return (volatile.LoadUint32(&o.ROM_PD_CTRL.Reg) & 0xfc) >> 2 +} + +// DPORT.ROM_FO_CTRL +func (o *DPORT_Type) SetROM_FO_CTRL_PRO_ROM_FO(value uint32) { + volatile.StoreUint32(&o.ROM_FO_CTRL.Reg, volatile.LoadUint32(&o.ROM_FO_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetROM_FO_CTRL_PRO_ROM_FO() uint32 { + return volatile.LoadUint32(&o.ROM_FO_CTRL.Reg) & 0x1 +} +func (o *DPORT_Type) SetROM_FO_CTRL_APP_ROM_FO(value uint32) { + volatile.StoreUint32(&o.ROM_FO_CTRL.Reg, volatile.LoadUint32(&o.ROM_FO_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetROM_FO_CTRL_APP_ROM_FO() uint32 { + return (volatile.LoadUint32(&o.ROM_FO_CTRL.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetROM_FO_CTRL_SHARE_ROM_FO(value uint32) { + volatile.StoreUint32(&o.ROM_FO_CTRL.Reg, volatile.LoadUint32(&o.ROM_FO_CTRL.Reg)&^(0xfc)|value<<2) +} +func (o *DPORT_Type) GetROM_FO_CTRL_SHARE_ROM_FO() uint32 { + return (volatile.LoadUint32(&o.ROM_FO_CTRL.Reg) & 0xfc) >> 2 +} + +// DPORT.SRAM_PD_CTRL_0 +func (o *DPORT_Type) SetSRAM_PD_CTRL_0(value uint32) { + volatile.StoreUint32(&o.SRAM_PD_CTRL_0.Reg, value) +} +func (o *DPORT_Type) GetSRAM_PD_CTRL_0() uint32 { + return volatile.LoadUint32(&o.SRAM_PD_CTRL_0.Reg) +} + +// DPORT.SRAM_PD_CTRL_1 +func (o *DPORT_Type) SetSRAM_PD_CTRL_1_SRAM_PD_1(value uint32) { + volatile.StoreUint32(&o.SRAM_PD_CTRL_1.Reg, volatile.LoadUint32(&o.SRAM_PD_CTRL_1.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetSRAM_PD_CTRL_1_SRAM_PD_1() uint32 { + return volatile.LoadUint32(&o.SRAM_PD_CTRL_1.Reg) & 0x1 +} + +// DPORT.SRAM_FO_CTRL_0 +func (o *DPORT_Type) SetSRAM_FO_CTRL_0(value uint32) { + volatile.StoreUint32(&o.SRAM_FO_CTRL_0.Reg, value) +} +func (o *DPORT_Type) GetSRAM_FO_CTRL_0() uint32 { + return volatile.LoadUint32(&o.SRAM_FO_CTRL_0.Reg) +} + +// DPORT.SRAM_FO_CTRL_1 +func (o *DPORT_Type) SetSRAM_FO_CTRL_1_SRAM_FO_1(value uint32) { + volatile.StoreUint32(&o.SRAM_FO_CTRL_1.Reg, volatile.LoadUint32(&o.SRAM_FO_CTRL_1.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetSRAM_FO_CTRL_1_SRAM_FO_1() uint32 { + return volatile.LoadUint32(&o.SRAM_FO_CTRL_1.Reg) & 0x1 +} + +// DPORT.IRAM_DRAM_AHB_SEL +func (o *DPORT_Type) SetIRAM_DRAM_AHB_SEL_MASK_PRO_IRAM(value uint32) { + volatile.StoreUint32(&o.IRAM_DRAM_AHB_SEL.Reg, volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetIRAM_DRAM_AHB_SEL_MASK_PRO_IRAM() uint32 { + return volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg) & 0x1 +} +func (o *DPORT_Type) SetIRAM_DRAM_AHB_SEL_MASK_APP_IRAM(value uint32) { + volatile.StoreUint32(&o.IRAM_DRAM_AHB_SEL.Reg, volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetIRAM_DRAM_AHB_SEL_MASK_APP_IRAM() uint32 { + return (volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetIRAM_DRAM_AHB_SEL_MASK_PRO_DRAM(value uint32) { + volatile.StoreUint32(&o.IRAM_DRAM_AHB_SEL.Reg, volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetIRAM_DRAM_AHB_SEL_MASK_PRO_DRAM() uint32 { + return (volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetIRAM_DRAM_AHB_SEL_MASK_APP_DRAM(value uint32) { + volatile.StoreUint32(&o.IRAM_DRAM_AHB_SEL.Reg, volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetIRAM_DRAM_AHB_SEL_MASK_APP_DRAM() uint32 { + return (volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetIRAM_DRAM_AHB_SEL_MASK_AHB(value uint32) { + volatile.StoreUint32(&o.IRAM_DRAM_AHB_SEL.Reg, volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetIRAM_DRAM_AHB_SEL_MASK_AHB() uint32 { + return (volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetIRAM_DRAM_AHB_SEL_MAC_DUMP_MODE(value uint32) { + volatile.StoreUint32(&o.IRAM_DRAM_AHB_SEL.Reg, volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg)&^(0x60)|value<<5) +} +func (o *DPORT_Type) GetIRAM_DRAM_AHB_SEL_MAC_DUMP_MODE() uint32 { + return (volatile.LoadUint32(&o.IRAM_DRAM_AHB_SEL.Reg) & 0x60) >> 5 +} + +// DPORT.TAG_FO_CTRL +func (o *DPORT_Type) SetTAG_FO_CTRL_PRO_CACHE_TAG_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.TAG_FO_CTRL.Reg, volatile.LoadUint32(&o.TAG_FO_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetTAG_FO_CTRL_PRO_CACHE_TAG_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.TAG_FO_CTRL.Reg) & 0x1 +} +func (o *DPORT_Type) SetTAG_FO_CTRL_PRO_CACHE_TAG_PD(value uint32) { + volatile.StoreUint32(&o.TAG_FO_CTRL.Reg, volatile.LoadUint32(&o.TAG_FO_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetTAG_FO_CTRL_PRO_CACHE_TAG_PD() uint32 { + return (volatile.LoadUint32(&o.TAG_FO_CTRL.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetTAG_FO_CTRL_APP_CACHE_TAG_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.TAG_FO_CTRL.Reg, volatile.LoadUint32(&o.TAG_FO_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetTAG_FO_CTRL_APP_CACHE_TAG_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.TAG_FO_CTRL.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetTAG_FO_CTRL_APP_CACHE_TAG_PD(value uint32) { + volatile.StoreUint32(&o.TAG_FO_CTRL.Reg, volatile.LoadUint32(&o.TAG_FO_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetTAG_FO_CTRL_APP_CACHE_TAG_PD() uint32 { + return (volatile.LoadUint32(&o.TAG_FO_CTRL.Reg) & 0x200) >> 9 +} + +// DPORT.AHB_LITE_MASK +func (o *DPORT_Type) SetAHB_LITE_MASK_PRO(value uint32) { + volatile.StoreUint32(&o.AHB_LITE_MASK.Reg, volatile.LoadUint32(&o.AHB_LITE_MASK.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAHB_LITE_MASK_PRO() uint32 { + return volatile.LoadUint32(&o.AHB_LITE_MASK.Reg) & 0x1 +} +func (o *DPORT_Type) SetAHB_LITE_MASK_APP(value uint32) { + volatile.StoreUint32(&o.AHB_LITE_MASK.Reg, volatile.LoadUint32(&o.AHB_LITE_MASK.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetAHB_LITE_MASK_APP() uint32 { + return (volatile.LoadUint32(&o.AHB_LITE_MASK.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetAHB_LITE_MASK_SDIO(value uint32) { + volatile.StoreUint32(&o.AHB_LITE_MASK.Reg, volatile.LoadUint32(&o.AHB_LITE_MASK.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetAHB_LITE_MASK_SDIO() uint32 { + return (volatile.LoadUint32(&o.AHB_LITE_MASK.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetAHB_LITE_MASK_PRODPORT(value uint32) { + volatile.StoreUint32(&o.AHB_LITE_MASK.Reg, volatile.LoadUint32(&o.AHB_LITE_MASK.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetAHB_LITE_MASK_PRODPORT() uint32 { + return (volatile.LoadUint32(&o.AHB_LITE_MASK.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetAHB_LITE_MASK_APPDPORT(value uint32) { + volatile.StoreUint32(&o.AHB_LITE_MASK.Reg, volatile.LoadUint32(&o.AHB_LITE_MASK.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetAHB_LITE_MASK_APPDPORT() uint32 { + return (volatile.LoadUint32(&o.AHB_LITE_MASK.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetAHB_LITE_MASK_AHB_LITE_SDHOST_PID(value uint32) { + volatile.StoreUint32(&o.AHB_LITE_MASK.Reg, volatile.LoadUint32(&o.AHB_LITE_MASK.Reg)&^(0x3800)|value<<11) +} +func (o *DPORT_Type) GetAHB_LITE_MASK_AHB_LITE_SDHOST_PID() uint32 { + return (volatile.LoadUint32(&o.AHB_LITE_MASK.Reg) & 0x3800) >> 11 +} + +// DPORT.AHB_MPU_TABLE_0 +func (o *DPORT_Type) SetAHB_MPU_TABLE_0(value uint32) { + volatile.StoreUint32(&o.AHB_MPU_TABLE_0.Reg, value) +} +func (o *DPORT_Type) GetAHB_MPU_TABLE_0() uint32 { + return volatile.LoadUint32(&o.AHB_MPU_TABLE_0.Reg) +} + +// DPORT.AHB_MPU_TABLE_1 +func (o *DPORT_Type) SetAHB_MPU_TABLE_1_AHB_ACCESS_GRANT_1(value uint32) { + volatile.StoreUint32(&o.AHB_MPU_TABLE_1.Reg, volatile.LoadUint32(&o.AHB_MPU_TABLE_1.Reg)&^(0x1ff)|value) +} +func (o *DPORT_Type) GetAHB_MPU_TABLE_1_AHB_ACCESS_GRANT_1() uint32 { + return volatile.LoadUint32(&o.AHB_MPU_TABLE_1.Reg) & 0x1ff +} + +// DPORT.HOST_INF_SEL +func (o *DPORT_Type) SetHOST_INF_SEL_PERI_IO_SWAP(value uint32) { + volatile.StoreUint32(&o.HOST_INF_SEL.Reg, volatile.LoadUint32(&o.HOST_INF_SEL.Reg)&^(0xff)|value) +} +func (o *DPORT_Type) GetHOST_INF_SEL_PERI_IO_SWAP() uint32 { + return volatile.LoadUint32(&o.HOST_INF_SEL.Reg) & 0xff +} +func (o *DPORT_Type) SetHOST_INF_SEL_LINK_DEVICE_SEL(value uint32) { + volatile.StoreUint32(&o.HOST_INF_SEL.Reg, volatile.LoadUint32(&o.HOST_INF_SEL.Reg)&^(0xff00)|value<<8) +} +func (o *DPORT_Type) GetHOST_INF_SEL_LINK_DEVICE_SEL() uint32 { + return (volatile.LoadUint32(&o.HOST_INF_SEL.Reg) & 0xff00) >> 8 +} + +// DPORT.PERIP_CLK_EN +func (o *DPORT_Type) SetPERIP_CLK_EN_TIMERS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_TIMERS_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x1 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_SPI01_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_SPI01_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_UART_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_UART_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_WDG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_WDG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_I2S0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_I2S0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_UART1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x20)|value<<5) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_UART1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x20) >> 5 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_SPI2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x40)|value<<6) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_SPI2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x40) >> 6 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_I2C0_EXT0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x80)|value<<7) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_I2C0_EXT0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x80) >> 7 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_UHCI0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_UHCI0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_RMT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_RMT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_PCNT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_PCNT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_LEDC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x800)|value<<11) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_LEDC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x800) >> 11 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_UHCI1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_UHCI1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_TIMERGROUP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_TIMERGROUP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x2000) >> 13 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_EFUSE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x4000)|value<<14) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_EFUSE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x4000) >> 14 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_TIMERGROUP1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x8000)|value<<15) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_TIMERGROUP1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x8000) >> 15 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_SPI3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x10000)|value<<16) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_SPI3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x10000) >> 16 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_PWM0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x20000)|value<<17) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_PWM0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x20000) >> 17 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_I2C_EXT1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x40000)|value<<18) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_I2C_EXT1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x40000) >> 18 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_TWAI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x80000)|value<<19) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_TWAI_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x80000) >> 19 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_PWM1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x100000)|value<<20) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_PWM1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x100000) >> 20 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_I2S1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x200000)|value<<21) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_I2S1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x200000) >> 21 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_SPI_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x400000)|value<<22) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_SPI_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x400000) >> 22 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_UART2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x800000)|value<<23) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_UART2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x800000) >> 23 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_UART_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_UART_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x1000000) >> 24 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_PWM2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_PWM2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x2000000) >> 25 +} +func (o *DPORT_Type) SetPERIP_CLK_EN_PWM3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *DPORT_Type) GetPERIP_CLK_EN_PWM3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN.Reg) & 0x4000000) >> 26 +} + +// DPORT.PERIP_RST_EN +func (o *DPORT_Type) SetPERIP_RST_EN_TIMERS_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPERIP_RST_EN_TIMERS_RST() uint32 { + return volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x1 +} +func (o *DPORT_Type) SetPERIP_RST_EN_SPI01_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetPERIP_RST_EN_SPI01_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetPERIP_RST_EN_UART_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetPERIP_RST_EN_UART_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetPERIP_RST_EN_WDG_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetPERIP_RST_EN_WDG_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetPERIP_RST_EN_I2S0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetPERIP_RST_EN_I2S0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetPERIP_RST_EN_UART1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x20)|value<<5) +} +func (o *DPORT_Type) GetPERIP_RST_EN_UART1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x20) >> 5 +} +func (o *DPORT_Type) SetPERIP_RST_EN_SPI2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x40)|value<<6) +} +func (o *DPORT_Type) GetPERIP_RST_EN_SPI2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x40) >> 6 +} +func (o *DPORT_Type) SetPERIP_RST_EN_I2C0_EXT0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x80)|value<<7) +} +func (o *DPORT_Type) GetPERIP_RST_EN_I2C0_EXT0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x80) >> 7 +} +func (o *DPORT_Type) SetPERIP_RST_EN_UHCI0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetPERIP_RST_EN_UHCI0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetPERIP_RST_EN_RMT_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetPERIP_RST_EN_RMT_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetPERIP_RST_EN_PCNT_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetPERIP_RST_EN_PCNT_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetPERIP_RST_EN_LEDC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x800)|value<<11) +} +func (o *DPORT_Type) GetPERIP_RST_EN_LEDC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x800) >> 11 +} +func (o *DPORT_Type) SetPERIP_RST_EN_UHCI1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetPERIP_RST_EN_UHCI1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetPERIP_RST_EN_TIMERGROUP_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetPERIP_RST_EN_TIMERGROUP_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x2000) >> 13 +} +func (o *DPORT_Type) SetPERIP_RST_EN_EFUSE_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x4000)|value<<14) +} +func (o *DPORT_Type) GetPERIP_RST_EN_EFUSE_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x4000) >> 14 +} +func (o *DPORT_Type) SetPERIP_RST_EN_TIMERGROUP1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x8000)|value<<15) +} +func (o *DPORT_Type) GetPERIP_RST_EN_TIMERGROUP1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x8000) >> 15 +} +func (o *DPORT_Type) SetPERIP_RST_EN_SPI3_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x10000)|value<<16) +} +func (o *DPORT_Type) GetPERIP_RST_EN_SPI3_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x10000) >> 16 +} +func (o *DPORT_Type) SetPERIP_RST_EN_PWM0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x20000)|value<<17) +} +func (o *DPORT_Type) GetPERIP_RST_EN_PWM0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x20000) >> 17 +} +func (o *DPORT_Type) SetPERIP_RST_EN_I2C_EXT1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x40000)|value<<18) +} +func (o *DPORT_Type) GetPERIP_RST_EN_I2C_EXT1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x40000) >> 18 +} +func (o *DPORT_Type) SetPERIP_RST_EN_TWAI_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x80000)|value<<19) +} +func (o *DPORT_Type) GetPERIP_RST_EN_TWAI_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x80000) >> 19 +} +func (o *DPORT_Type) SetPERIP_RST_EN_PWM1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x100000)|value<<20) +} +func (o *DPORT_Type) GetPERIP_RST_EN_PWM1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x100000) >> 20 +} +func (o *DPORT_Type) SetPERIP_RST_EN_I2S1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x200000)|value<<21) +} +func (o *DPORT_Type) GetPERIP_RST_EN_I2S1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x200000) >> 21 +} +func (o *DPORT_Type) SetPERIP_RST_EN_SPI_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x400000)|value<<22) +} +func (o *DPORT_Type) GetPERIP_RST_EN_SPI_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x400000) >> 22 +} +func (o *DPORT_Type) SetPERIP_RST_EN_UART2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x800000)|value<<23) +} +func (o *DPORT_Type) GetPERIP_RST_EN_UART2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x800000) >> 23 +} +func (o *DPORT_Type) SetPERIP_RST_EN_UART_MEM_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *DPORT_Type) GetPERIP_RST_EN_UART_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x1000000) >> 24 +} +func (o *DPORT_Type) SetPERIP_RST_EN_PWM2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *DPORT_Type) GetPERIP_RST_EN_PWM2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x2000000) >> 25 +} +func (o *DPORT_Type) SetPERIP_RST_EN_PWM3_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN.Reg, volatile.LoadUint32(&o.PERIP_RST_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *DPORT_Type) GetPERIP_RST_EN_PWM3_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN.Reg) & 0x4000000) >> 26 +} + +// DPORT.SLAVE_SPI_CONFIG +func (o *DPORT_Type) SetSLAVE_SPI_CONFIG_SLAVE_SPI_MASK_PRO(value uint32) { + volatile.StoreUint32(&o.SLAVE_SPI_CONFIG.Reg, volatile.LoadUint32(&o.SLAVE_SPI_CONFIG.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetSLAVE_SPI_CONFIG_SLAVE_SPI_MASK_PRO() uint32 { + return volatile.LoadUint32(&o.SLAVE_SPI_CONFIG.Reg) & 0x1 +} +func (o *DPORT_Type) SetSLAVE_SPI_CONFIG_SLAVE_SPI_MASK_APP(value uint32) { + volatile.StoreUint32(&o.SLAVE_SPI_CONFIG.Reg, volatile.LoadUint32(&o.SLAVE_SPI_CONFIG.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetSLAVE_SPI_CONFIG_SLAVE_SPI_MASK_APP() uint32 { + return (volatile.LoadUint32(&o.SLAVE_SPI_CONFIG.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetSLAVE_SPI_CONFIG_SPI_ENCRYPT_ENABLE(value uint32) { + volatile.StoreUint32(&o.SLAVE_SPI_CONFIG.Reg, volatile.LoadUint32(&o.SLAVE_SPI_CONFIG.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetSLAVE_SPI_CONFIG_SPI_ENCRYPT_ENABLE() uint32 { + return (volatile.LoadUint32(&o.SLAVE_SPI_CONFIG.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetSLAVE_SPI_CONFIG_SPI_DECRYPT_ENABLE(value uint32) { + volatile.StoreUint32(&o.SLAVE_SPI_CONFIG.Reg, volatile.LoadUint32(&o.SLAVE_SPI_CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetSLAVE_SPI_CONFIG_SPI_DECRYPT_ENABLE() uint32 { + return (volatile.LoadUint32(&o.SLAVE_SPI_CONFIG.Reg) & 0x1000) >> 12 +} + +// DPORT.WIFI_CLK_EN +func (o *DPORT_Type) SetWIFI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_CLK_EN.Reg, value) +} +func (o *DPORT_Type) GetWIFI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_CLK_EN.Reg) +} +func (o *DPORT_Type) SetWIFI_CLK_EN_WIFI_CLK_WIFI_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_CLK_EN.Reg, volatile.LoadUint32(&o.WIFI_CLK_EN.Reg)&^(0x7)|value) +} +func (o *DPORT_Type) GetWIFI_CLK_EN_WIFI_CLK_WIFI_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_CLK_EN.Reg) & 0x7 +} +func (o *DPORT_Type) SetWIFI_CLK_EN_WIFI_CLK_WIFI_BT_COMMON(value uint32) { + volatile.StoreUint32(&o.WIFI_CLK_EN.Reg, volatile.LoadUint32(&o.WIFI_CLK_EN.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetWIFI_CLK_EN_WIFI_CLK_WIFI_BT_COMMON() uint32 { + return volatile.LoadUint32(&o.WIFI_CLK_EN.Reg) & 0x3f +} +func (o *DPORT_Type) SetWIFI_CLK_EN_WIFI_CLK_BT_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_CLK_EN.Reg, volatile.LoadUint32(&o.WIFI_CLK_EN.Reg)&^(0x3800)|value<<11) +} +func (o *DPORT_Type) GetWIFI_CLK_EN_WIFI_CLK_BT_EN() uint32 { + return (volatile.LoadUint32(&o.WIFI_CLK_EN.Reg) & 0x3800) >> 11 +} + +// DPORT.CORE_RST_EN +func (o *DPORT_Type) SetCORE_RST_EN_CORE_RST(value uint32) { + volatile.StoreUint32(&o.CORE_RST_EN.Reg, volatile.LoadUint32(&o.CORE_RST_EN.Reg)&^(0xff)|value) +} +func (o *DPORT_Type) GetCORE_RST_EN_CORE_RST() uint32 { + return volatile.LoadUint32(&o.CORE_RST_EN.Reg) & 0xff +} + +// DPORT.BT_LPCK_DIV_INT +func (o *DPORT_Type) SetBT_LPCK_DIV_INT_BT_LPCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_INT.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg)&^(0xfff)|value) +} +func (o *DPORT_Type) GetBT_LPCK_DIV_INT_BT_LPCK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg) & 0xfff +} +func (o *DPORT_Type) SetBT_LPCK_DIV_INT_BTEXTWAKEUP_REQ(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_INT.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetBT_LPCK_DIV_INT_BTEXTWAKEUP_REQ() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg) & 0x1000) >> 12 +} + +// DPORT.BT_LPCK_DIV_FRAC +func (o *DPORT_Type) SetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_B(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0xfff)|value) +} +func (o *DPORT_Type) GetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_B() uint32 { + return volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0xfff +} +func (o *DPORT_Type) SetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_A(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0xfff000)|value<<12) +} +func (o *DPORT_Type) GetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0xfff000) >> 12 +} +func (o *DPORT_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x1000000)|value<<24) +} +func (o *DPORT_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x1000000) >> 24 +} +func (o *DPORT_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x2000000)|value<<25) +} +func (o *DPORT_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x2000000) >> 25 +} +func (o *DPORT_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x4000000)|value<<26) +} +func (o *DPORT_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x4000000) >> 26 +} +func (o *DPORT_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x8000000)|value<<27) +} +func (o *DPORT_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x8000000) >> 27 +} + +// DPORT.CPU_INTR_FROM_CPU_0 +func (o *DPORT_Type) SetCPU_INTR_FROM_CPU_0(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetCPU_INTR_FROM_CPU_0() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg) & 0x1 +} + +// DPORT.CPU_INTR_FROM_CPU_1 +func (o *DPORT_Type) SetCPU_INTR_FROM_CPU_1(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetCPU_INTR_FROM_CPU_1() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg) & 0x1 +} + +// DPORT.CPU_INTR_FROM_CPU_2 +func (o *DPORT_Type) SetCPU_INTR_FROM_CPU_2(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetCPU_INTR_FROM_CPU_2() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg) & 0x1 +} + +// DPORT.CPU_INTR_FROM_CPU_3 +func (o *DPORT_Type) SetCPU_INTR_FROM_CPU_3(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetCPU_INTR_FROM_CPU_3() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg) & 0x1 +} + +// DPORT.PRO_INTR_STATUS_0 +func (o *DPORT_Type) SetPRO_INTR_STATUS_0(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_0.Reg, value) +} +func (o *DPORT_Type) GetPRO_INTR_STATUS_0() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_0.Reg) +} + +// DPORT.PRO_INTR_STATUS_1 +func (o *DPORT_Type) SetPRO_INTR_STATUS_1(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_1.Reg, value) +} +func (o *DPORT_Type) GetPRO_INTR_STATUS_1() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_1.Reg) +} + +// DPORT.PRO_INTR_STATUS_2 +func (o *DPORT_Type) SetPRO_INTR_STATUS_2(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_2.Reg, value) +} +func (o *DPORT_Type) GetPRO_INTR_STATUS_2() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_2.Reg) +} + +// DPORT.APP_INTR_STATUS_0 +func (o *DPORT_Type) SetAPP_INTR_STATUS_0(value uint32) { + volatile.StoreUint32(&o.APP_INTR_STATUS_0.Reg, value) +} +func (o *DPORT_Type) GetAPP_INTR_STATUS_0() uint32 { + return volatile.LoadUint32(&o.APP_INTR_STATUS_0.Reg) +} + +// DPORT.APP_INTR_STATUS_1 +func (o *DPORT_Type) SetAPP_INTR_STATUS_1(value uint32) { + volatile.StoreUint32(&o.APP_INTR_STATUS_1.Reg, value) +} +func (o *DPORT_Type) GetAPP_INTR_STATUS_1() uint32 { + return volatile.LoadUint32(&o.APP_INTR_STATUS_1.Reg) +} + +// DPORT.APP_INTR_STATUS_2 +func (o *DPORT_Type) SetAPP_INTR_STATUS_2(value uint32) { + volatile.StoreUint32(&o.APP_INTR_STATUS_2.Reg, value) +} +func (o *DPORT_Type) GetAPP_INTR_STATUS_2() uint32 { + return volatile.LoadUint32(&o.APP_INTR_STATUS_2.Reg) +} + +// DPORT.PRO_MAC_INTR_MAP +func (o *DPORT_Type) SetPRO_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_MAC_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_MAC_NMI_MAP +func (o *DPORT_Type) SetPRO_MAC_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_MAC_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_MAC_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_MAC_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_MAC_NMI_MAP.Reg) & 0x1f +} + +// DPORT.PRO_BB_INT_MAP +func (o *DPORT_Type) SetPRO_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_BB_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_BB_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_BT_MAC_INT_MAP +func (o *DPORT_Type) SetPRO_BT_MAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_BT_MAC_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_BT_MAC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_BT_MAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_BT_MAC_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_BT_BB_INT_MAP +func (o *DPORT_Type) SetPRO_BT_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_BT_BB_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_BT_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_BT_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_BT_BB_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_BT_BB_NMI_MAP +func (o *DPORT_Type) SetPRO_BT_BB_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_BT_BB_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_BT_BB_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_BT_BB_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_BT_BB_NMI_MAP.Reg) & 0x1f +} + +// DPORT.PRO_RWBT_IRQ_MAP +func (o *DPORT_Type) SetPRO_RWBT_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RWBT_IRQ_MAP.Reg, volatile.LoadUint32(&o.PRO_RWBT_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_RWBT_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RWBT_IRQ_MAP.Reg) & 0x1f +} + +// DPORT.PRO_RWBLE_IRQ_MAP +func (o *DPORT_Type) SetPRO_RWBLE_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RWBLE_IRQ_MAP.Reg, volatile.LoadUint32(&o.PRO_RWBLE_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_RWBLE_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RWBLE_IRQ_MAP.Reg) & 0x1f +} + +// DPORT.PRO_RWBT_NMI_MAP +func (o *DPORT_Type) SetPRO_RWBT_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RWBT_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_RWBT_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_RWBT_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RWBT_NMI_MAP.Reg) & 0x1f +} + +// DPORT.PRO_RWBLE_NMI_MAP +func (o *DPORT_Type) SetPRO_RWBLE_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RWBLE_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_RWBLE_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_RWBLE_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RWBLE_NMI_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SLC0_INTR_MAP +func (o *DPORT_Type) SetPRO_SLC0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SLC0_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_SLC0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SLC0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SLC0_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SLC1_INTR_MAP +func (o *DPORT_Type) SetPRO_SLC1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SLC1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_SLC1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SLC1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SLC1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_UHCI0_INTR_MAP +func (o *DPORT_Type) SetPRO_UHCI0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UHCI0_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UHCI0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_UHCI0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UHCI0_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_UHCI1_INTR_MAP +func (o *DPORT_Type) SetPRO_UHCI1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UHCI1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UHCI1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_UHCI1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UHCI1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG_T0_LEVEL_INT_MAP +func (o *DPORT_Type) SetPRO_TG_T0_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_T0_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_T0_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG_T0_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_T0_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG_T1_LEVEL_INT_MAP +func (o *DPORT_Type) SetPRO_TG_T1_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_T1_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_T1_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG_T1_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_T1_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG_WDT_LEVEL_INT_MAP +func (o *DPORT_Type) SetPRO_TG_WDT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_WDT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_WDT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG_WDT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_WDT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG_LACT_LEVEL_INT_MAP +func (o *DPORT_Type) SetPRO_TG_LACT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_LACT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_LACT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG_LACT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_LACT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG1_T0_LEVEL_INT_MAP +func (o *DPORT_Type) SetPRO_TG1_T0_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_T0_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_T0_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG1_T0_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_T0_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG1_T1_LEVEL_INT_MAP +func (o *DPORT_Type) SetPRO_TG1_T1_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_T1_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_T1_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG1_T1_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_T1_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG1_WDT_LEVEL_INT_MAP +func (o *DPORT_Type) SetPRO_TG1_WDT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_WDT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_WDT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG1_WDT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_WDT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG1_LACT_LEVEL_INT_MAP +func (o *DPORT_Type) SetPRO_TG1_LACT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_LACT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_LACT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG1_LACT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_LACT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_GPIO_INTERRUPT_MAP +func (o *DPORT_Type) SetPRO_GPIO_INTERRUPT_MAP_PRO_GPIO_INTERRUPT_PRO_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_GPIO_INTERRUPT_MAP.Reg, volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_GPIO_INTERRUPT_MAP_PRO_GPIO_INTERRUPT_PRO_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_GPIO_INTERRUPT_NMI_MAP +func (o *DPORT_Type) SetPRO_GPIO_INTERRUPT_NMI_MAP_PRO_GPIO_INTERRUPT_PRO_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_GPIO_INTERRUPT_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_GPIO_INTERRUPT_NMI_MAP_PRO_GPIO_INTERRUPT_PRO_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_NMI_MAP.Reg) & 0x1f +} + +// DPORT.PRO_CPU_INTR_FROM_CPU_0_MAP +func (o *DPORT_Type) SetPRO_CPU_INTR_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_INTR_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_0_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_CPU_INTR_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_0_MAP.Reg) & 0x1f +} + +// DPORT.PRO_CPU_INTR_FROM_CPU_1_MAP +func (o *DPORT_Type) SetPRO_CPU_INTR_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_INTR_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_1_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_CPU_INTR_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_1_MAP.Reg) & 0x1f +} + +// DPORT.PRO_CPU_INTR_FROM_CPU_2_MAP +func (o *DPORT_Type) SetPRO_CPU_INTR_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_INTR_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_2_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_CPU_INTR_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_2_MAP.Reg) & 0x1f +} + +// DPORT.PRO_CPU_INTR_FROM_CPU_3_MAP +func (o *DPORT_Type) SetPRO_CPU_INTR_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_INTR_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_3_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_CPU_INTR_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_3_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SPI_INTR_0_MAP +func (o *DPORT_Type) SetPRO_SPI_INTR_0_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI_INTR_0_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI_INTR_0_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SPI_INTR_0_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI_INTR_0_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SPI_INTR_1_MAP +func (o *DPORT_Type) SetPRO_SPI_INTR_1_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI_INTR_1_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI_INTR_1_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SPI_INTR_1_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI_INTR_1_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SPI_INTR_2_MAP +func (o *DPORT_Type) SetPRO_SPI_INTR_2_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI_INTR_2_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI_INTR_2_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SPI_INTR_2_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI_INTR_2_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SPI_INTR_3_MAP +func (o *DPORT_Type) SetPRO_SPI_INTR_3_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI_INTR_3_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI_INTR_3_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SPI_INTR_3_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI_INTR_3_MAP.Reg) & 0x1f +} + +// DPORT.PRO_I2S0_INT_MAP +func (o *DPORT_Type) SetPRO_I2S0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_I2S0_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_I2S0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_I2S0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_I2S0_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_I2S1_INT_MAP +func (o *DPORT_Type) SetPRO_I2S1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_I2S1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_I2S1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_I2S1_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_UART_INTR_MAP +func (o *DPORT_Type) SetPRO_UART_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UART_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UART_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_UART_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UART_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_UART1_INTR_MAP +func (o *DPORT_Type) SetPRO_UART1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UART1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UART1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_UART1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UART1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_UART2_INTR_MAP +func (o *DPORT_Type) SetPRO_UART2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UART2_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UART2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_UART2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UART2_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SDIO_HOST_INTERRUPT_MAP +func (o *DPORT_Type) SetPRO_SDIO_HOST_INTERRUPT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SDIO_HOST_INTERRUPT_MAP.Reg, volatile.LoadUint32(&o.PRO_SDIO_HOST_INTERRUPT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SDIO_HOST_INTERRUPT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SDIO_HOST_INTERRUPT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_EMAC_INT_MAP +func (o *DPORT_Type) SetPRO_EMAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_EMAC_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_EMAC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_EMAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_EMAC_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_PWM0_INTR_MAP +func (o *DPORT_Type) SetPRO_PWM0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PWM0_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PWM0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_PWM0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PWM0_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_PWM1_INTR_MAP +func (o *DPORT_Type) SetPRO_PWM1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PWM1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PWM1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_PWM1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PWM1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_PWM2_INTR_MAP +func (o *DPORT_Type) SetPRO_PWM2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PWM2_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PWM2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_PWM2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PWM2_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_PWM3_INTR_MAP +func (o *DPORT_Type) SetPRO_PWM3_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PWM3_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PWM3_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_PWM3_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PWM3_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_LEDC_INT_MAP +func (o *DPORT_Type) SetPRO_LEDC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_LEDC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_LEDC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_LEDC_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_EFUSE_INT_MAP +func (o *DPORT_Type) SetPRO_EFUSE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_EFUSE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_EFUSE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_EFUSE_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_CAN_INT_MAP +func (o *DPORT_Type) SetPRO_CAN_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CAN_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_CAN_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_CAN_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CAN_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_RTC_CORE_INTR_MAP +func (o *DPORT_Type) SetPRO_RTC_CORE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RTC_CORE_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_RTC_CORE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_RTC_CORE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RTC_CORE_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_RMT_INTR_MAP +func (o *DPORT_Type) SetPRO_RMT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RMT_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_RMT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_RMT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RMT_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_PCNT_INTR_MAP +func (o *DPORT_Type) SetPRO_PCNT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PCNT_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PCNT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_PCNT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PCNT_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_I2C_EXT0_INTR_MAP +func (o *DPORT_Type) SetPRO_I2C_EXT0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_I2C_EXT0_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_I2C_EXT0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_I2C_EXT0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_I2C_EXT0_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_I2C_EXT1_INTR_MAP +func (o *DPORT_Type) SetPRO_I2C_EXT1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_I2C_EXT1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_I2C_EXT1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_I2C_EXT1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_I2C_EXT1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_RSA_INTR_MAP +func (o *DPORT_Type) SetPRO_RSA_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RSA_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_RSA_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_RSA_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RSA_INTR_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SPI1_DMA_INT_MAP +func (o *DPORT_Type) SetPRO_SPI1_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI1_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI1_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SPI1_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI1_DMA_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SPI2_DMA_INT_MAP +func (o *DPORT_Type) SetPRO_SPI2_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI2_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI2_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SPI2_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI2_DMA_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_SPI3_DMA_INT_MAP +func (o *DPORT_Type) SetPRO_SPI3_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI3_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI3_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_SPI3_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI3_DMA_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_WDG_INT_MAP +func (o *DPORT_Type) SetPRO_WDG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_WDG_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_WDG_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_WDG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_WDG_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TIMER_INT1_MAP +func (o *DPORT_Type) SetPRO_TIMER_INT1_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TIMER_INT1_MAP.Reg, volatile.LoadUint32(&o.PRO_TIMER_INT1_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TIMER_INT1_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TIMER_INT1_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TIMER_INT2_MAP +func (o *DPORT_Type) SetPRO_TIMER_INT2_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TIMER_INT2_MAP.Reg, volatile.LoadUint32(&o.PRO_TIMER_INT2_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TIMER_INT2_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TIMER_INT2_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG_T0_EDGE_INT_MAP +func (o *DPORT_Type) SetPRO_TG_T0_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_T0_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_T0_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG_T0_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_T0_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG_T1_EDGE_INT_MAP +func (o *DPORT_Type) SetPRO_TG_T1_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_T1_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_T1_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG_T1_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_T1_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG_WDT_EDGE_INT_MAP +func (o *DPORT_Type) SetPRO_TG_WDT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_WDT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_WDT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG_WDT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_WDT_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG_LACT_EDGE_INT_MAP +func (o *DPORT_Type) SetPRO_TG_LACT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_LACT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_LACT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG_LACT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_LACT_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG1_T0_EDGE_INT_MAP +func (o *DPORT_Type) SetPRO_TG1_T0_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_T0_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_T0_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG1_T0_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_T0_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG1_T1_EDGE_INT_MAP +func (o *DPORT_Type) SetPRO_TG1_T1_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_T1_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_T1_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG1_T1_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_T1_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG1_WDT_EDGE_INT_MAP +func (o *DPORT_Type) SetPRO_TG1_WDT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_WDT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_WDT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG1_WDT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_WDT_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_TG1_LACT_EDGE_INT_MAP +func (o *DPORT_Type) SetPRO_TG1_LACT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_LACT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_LACT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_TG1_LACT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_LACT_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_MMU_IA_INT_MAP +func (o *DPORT_Type) SetPRO_MMU_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_MMU_IA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_MMU_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_MMU_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_MMU_IA_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_MPU_IA_INT_MAP +func (o *DPORT_Type) SetPRO_MPU_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_MPU_IA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_MPU_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_MPU_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_MPU_IA_INT_MAP.Reg) & 0x1f +} + +// DPORT.PRO_CACHE_IA_INT_MAP +func (o *DPORT_Type) SetPRO_CACHE_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_IA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_CACHE_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_CACHE_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_IA_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_MAC_INTR_MAP +func (o *DPORT_Type) SetAPP_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_MAC_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_MAC_NMI_MAP +func (o *DPORT_Type) SetAPP_MAC_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.APP_MAC_NMI_MAP.Reg, volatile.LoadUint32(&o.APP_MAC_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_MAC_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.APP_MAC_NMI_MAP.Reg) & 0x1f +} + +// DPORT.APP_BB_INT_MAP +func (o *DPORT_Type) SetAPP_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_BB_INT_MAP.Reg, volatile.LoadUint32(&o.APP_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_BB_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_BT_MAC_INT_MAP +func (o *DPORT_Type) SetAPP_BT_MAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_BT_MAC_INT_MAP.Reg, volatile.LoadUint32(&o.APP_BT_MAC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_BT_MAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_BT_MAC_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_BT_BB_INT_MAP +func (o *DPORT_Type) SetAPP_BT_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_BT_BB_INT_MAP.Reg, volatile.LoadUint32(&o.APP_BT_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_BT_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_BT_BB_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_BT_BB_NMI_MAP +func (o *DPORT_Type) SetAPP_BT_BB_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.APP_BT_BB_NMI_MAP.Reg, volatile.LoadUint32(&o.APP_BT_BB_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_BT_BB_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.APP_BT_BB_NMI_MAP.Reg) & 0x1f +} + +// DPORT.APP_RWBT_IRQ_MAP +func (o *DPORT_Type) SetAPP_RWBT_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.APP_RWBT_IRQ_MAP.Reg, volatile.LoadUint32(&o.APP_RWBT_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_RWBT_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.APP_RWBT_IRQ_MAP.Reg) & 0x1f +} + +// DPORT.APP_RWBLE_IRQ_MAP +func (o *DPORT_Type) SetAPP_RWBLE_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.APP_RWBLE_IRQ_MAP.Reg, volatile.LoadUint32(&o.APP_RWBLE_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_RWBLE_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.APP_RWBLE_IRQ_MAP.Reg) & 0x1f +} + +// DPORT.APP_RWBT_NMI_MAP +func (o *DPORT_Type) SetAPP_RWBT_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.APP_RWBT_NMI_MAP.Reg, volatile.LoadUint32(&o.APP_RWBT_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_RWBT_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.APP_RWBT_NMI_MAP.Reg) & 0x1f +} + +// DPORT.APP_RWBLE_NMI_MAP +func (o *DPORT_Type) SetAPP_RWBLE_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.APP_RWBLE_NMI_MAP.Reg, volatile.LoadUint32(&o.APP_RWBLE_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_RWBLE_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.APP_RWBLE_NMI_MAP.Reg) & 0x1f +} + +// DPORT.APP_SLC0_INTR_MAP +func (o *DPORT_Type) SetAPP_SLC0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SLC0_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_SLC0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SLC0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SLC0_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_SLC1_INTR_MAP +func (o *DPORT_Type) SetAPP_SLC1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SLC1_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_SLC1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SLC1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SLC1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_UHCI0_INTR_MAP +func (o *DPORT_Type) SetAPP_UHCI0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_UHCI0_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_UHCI0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_UHCI0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_UHCI0_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_UHCI1_INTR_MAP +func (o *DPORT_Type) SetAPP_UHCI1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_UHCI1_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_UHCI1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_UHCI1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_UHCI1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG_T0_LEVEL_INT_MAP +func (o *DPORT_Type) SetAPP_TG_T0_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG_T0_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG_T0_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG_T0_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG_T0_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG_T1_LEVEL_INT_MAP +func (o *DPORT_Type) SetAPP_TG_T1_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG_T1_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG_T1_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG_T1_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG_T1_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG_WDT_LEVEL_INT_MAP +func (o *DPORT_Type) SetAPP_TG_WDT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG_WDT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG_WDT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG_WDT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG_WDT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG_LACT_LEVEL_INT_MAP +func (o *DPORT_Type) SetAPP_TG_LACT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG_LACT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG_LACT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG_LACT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG_LACT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG1_T0_LEVEL_INT_MAP +func (o *DPORT_Type) SetAPP_TG1_T0_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG1_T0_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG1_T0_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG1_T0_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG1_T0_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG1_T1_LEVEL_INT_MAP +func (o *DPORT_Type) SetAPP_TG1_T1_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG1_T1_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG1_T1_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG1_T1_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG1_T1_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG1_WDT_LEVEL_INT_MAP +func (o *DPORT_Type) SetAPP_TG1_WDT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG1_WDT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG1_WDT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG1_WDT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG1_WDT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG1_LACT_LEVEL_INT_MAP +func (o *DPORT_Type) SetAPP_TG1_LACT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG1_LACT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG1_LACT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG1_LACT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG1_LACT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_GPIO_INTERRUPT_MAP +func (o *DPORT_Type) SetAPP_GPIO_INTERRUPT_MAP_APP_GPIO_INTERRUPT_APP_MAP(value uint32) { + volatile.StoreUint32(&o.APP_GPIO_INTERRUPT_MAP.Reg, volatile.LoadUint32(&o.APP_GPIO_INTERRUPT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_GPIO_INTERRUPT_MAP_APP_GPIO_INTERRUPT_APP_MAP() uint32 { + return volatile.LoadUint32(&o.APP_GPIO_INTERRUPT_MAP.Reg) & 0x1f +} + +// DPORT.APP_GPIO_INTERRUPT_NMI_MAP +func (o *DPORT_Type) SetAPP_GPIO_INTERRUPT_NMI_MAP_APP_GPIO_INTERRUPT_APP_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.APP_GPIO_INTERRUPT_NMI_MAP.Reg, volatile.LoadUint32(&o.APP_GPIO_INTERRUPT_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_GPIO_INTERRUPT_NMI_MAP_APP_GPIO_INTERRUPT_APP_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.APP_GPIO_INTERRUPT_NMI_MAP.Reg) & 0x1f +} + +// DPORT.APP_CPU_INTR_FROM_CPU_0_MAP +func (o *DPORT_Type) SetAPP_CPU_INTR_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.APP_CPU_INTR_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.APP_CPU_INTR_FROM_CPU_0_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_CPU_INTR_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.APP_CPU_INTR_FROM_CPU_0_MAP.Reg) & 0x1f +} + +// DPORT.APP_CPU_INTR_FROM_CPU_1_MAP +func (o *DPORT_Type) SetAPP_CPU_INTR_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.APP_CPU_INTR_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.APP_CPU_INTR_FROM_CPU_1_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_CPU_INTR_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.APP_CPU_INTR_FROM_CPU_1_MAP.Reg) & 0x1f +} + +// DPORT.APP_CPU_INTR_FROM_CPU_2_MAP +func (o *DPORT_Type) SetAPP_CPU_INTR_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.APP_CPU_INTR_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.APP_CPU_INTR_FROM_CPU_2_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_CPU_INTR_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.APP_CPU_INTR_FROM_CPU_2_MAP.Reg) & 0x1f +} + +// DPORT.APP_CPU_INTR_FROM_CPU_3_MAP +func (o *DPORT_Type) SetAPP_CPU_INTR_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.APP_CPU_INTR_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.APP_CPU_INTR_FROM_CPU_3_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_CPU_INTR_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.APP_CPU_INTR_FROM_CPU_3_MAP.Reg) & 0x1f +} + +// DPORT.APP_SPI_INTR_0_MAP +func (o *DPORT_Type) SetAPP_SPI_INTR_0_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SPI_INTR_0_MAP.Reg, volatile.LoadUint32(&o.APP_SPI_INTR_0_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SPI_INTR_0_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SPI_INTR_0_MAP.Reg) & 0x1f +} + +// DPORT.APP_SPI_INTR_1_MAP +func (o *DPORT_Type) SetAPP_SPI_INTR_1_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SPI_INTR_1_MAP.Reg, volatile.LoadUint32(&o.APP_SPI_INTR_1_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SPI_INTR_1_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SPI_INTR_1_MAP.Reg) & 0x1f +} + +// DPORT.APP_SPI_INTR_2_MAP +func (o *DPORT_Type) SetAPP_SPI_INTR_2_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SPI_INTR_2_MAP.Reg, volatile.LoadUint32(&o.APP_SPI_INTR_2_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SPI_INTR_2_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SPI_INTR_2_MAP.Reg) & 0x1f +} + +// DPORT.APP_SPI_INTR_3_MAP +func (o *DPORT_Type) SetAPP_SPI_INTR_3_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SPI_INTR_3_MAP.Reg, volatile.LoadUint32(&o.APP_SPI_INTR_3_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SPI_INTR_3_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SPI_INTR_3_MAP.Reg) & 0x1f +} + +// DPORT.APP_I2S0_INT_MAP +func (o *DPORT_Type) SetAPP_I2S0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_I2S0_INT_MAP.Reg, volatile.LoadUint32(&o.APP_I2S0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_I2S0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_I2S0_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_I2S1_INT_MAP +func (o *DPORT_Type) SetAPP_I2S1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.APP_I2S1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_I2S1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_I2S1_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_UART_INTR_MAP +func (o *DPORT_Type) SetAPP_UART_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_UART_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_UART_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_UART_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_UART_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_UART1_INTR_MAP +func (o *DPORT_Type) SetAPP_UART1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_UART1_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_UART1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_UART1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_UART1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_UART2_INTR_MAP +func (o *DPORT_Type) SetAPP_UART2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_UART2_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_UART2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_UART2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_UART2_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_SDIO_HOST_INTERRUPT_MAP +func (o *DPORT_Type) SetAPP_SDIO_HOST_INTERRUPT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SDIO_HOST_INTERRUPT_MAP.Reg, volatile.LoadUint32(&o.APP_SDIO_HOST_INTERRUPT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SDIO_HOST_INTERRUPT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SDIO_HOST_INTERRUPT_MAP.Reg) & 0x1f +} + +// DPORT.APP_EMAC_INT_MAP +func (o *DPORT_Type) SetAPP_EMAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_EMAC_INT_MAP.Reg, volatile.LoadUint32(&o.APP_EMAC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_EMAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_EMAC_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_PWM0_INTR_MAP +func (o *DPORT_Type) SetAPP_PWM0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_PWM0_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_PWM0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_PWM0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_PWM0_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_PWM1_INTR_MAP +func (o *DPORT_Type) SetAPP_PWM1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_PWM1_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_PWM1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_PWM1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_PWM1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_PWM2_INTR_MAP +func (o *DPORT_Type) SetAPP_PWM2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_PWM2_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_PWM2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_PWM2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_PWM2_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_PWM3_INTR_MAP +func (o *DPORT_Type) SetAPP_PWM3_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_PWM3_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_PWM3_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_PWM3_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_PWM3_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_LEDC_INT_MAP +func (o *DPORT_Type) SetAPP_LEDC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.APP_LEDC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_LEDC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_LEDC_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_EFUSE_INT_MAP +func (o *DPORT_Type) SetAPP_EFUSE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.APP_EFUSE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_EFUSE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_EFUSE_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_CAN_INT_MAP +func (o *DPORT_Type) SetAPP_CAN_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_CAN_INT_MAP.Reg, volatile.LoadUint32(&o.APP_CAN_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_CAN_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_CAN_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_RTC_CORE_INTR_MAP +func (o *DPORT_Type) SetAPP_RTC_CORE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_RTC_CORE_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_RTC_CORE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_RTC_CORE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_RTC_CORE_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_RMT_INTR_MAP +func (o *DPORT_Type) SetAPP_RMT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_RMT_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_RMT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_RMT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_RMT_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_PCNT_INTR_MAP +func (o *DPORT_Type) SetAPP_PCNT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_PCNT_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_PCNT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_PCNT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_PCNT_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_I2C_EXT0_INTR_MAP +func (o *DPORT_Type) SetAPP_I2C_EXT0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_I2C_EXT0_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_I2C_EXT0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_I2C_EXT0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_I2C_EXT0_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_I2C_EXT1_INTR_MAP +func (o *DPORT_Type) SetAPP_I2C_EXT1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_I2C_EXT1_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_I2C_EXT1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_I2C_EXT1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_I2C_EXT1_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_RSA_INTR_MAP +func (o *DPORT_Type) SetAPP_RSA_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_RSA_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_RSA_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_RSA_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_RSA_INTR_MAP.Reg) & 0x1f +} + +// DPORT.APP_SPI1_DMA_INT_MAP +func (o *DPORT_Type) SetAPP_SPI1_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SPI1_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.APP_SPI1_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SPI1_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SPI1_DMA_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_SPI2_DMA_INT_MAP +func (o *DPORT_Type) SetAPP_SPI2_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SPI2_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.APP_SPI2_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SPI2_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SPI2_DMA_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_SPI3_DMA_INT_MAP +func (o *DPORT_Type) SetAPP_SPI3_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_SPI3_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.APP_SPI3_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_SPI3_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_SPI3_DMA_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_WDG_INT_MAP +func (o *DPORT_Type) SetAPP_WDG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_WDG_INT_MAP.Reg, volatile.LoadUint32(&o.APP_WDG_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_WDG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_WDG_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TIMER_INT1_MAP +func (o *DPORT_Type) SetAPP_TIMER_INT1_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TIMER_INT1_MAP.Reg, volatile.LoadUint32(&o.APP_TIMER_INT1_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TIMER_INT1_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TIMER_INT1_MAP.Reg) & 0x1f +} + +// DPORT.APP_TIMER_INT2_MAP +func (o *DPORT_Type) SetAPP_TIMER_INT2_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TIMER_INT2_MAP.Reg, volatile.LoadUint32(&o.APP_TIMER_INT2_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TIMER_INT2_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TIMER_INT2_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG_T0_EDGE_INT_MAP +func (o *DPORT_Type) SetAPP_TG_T0_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG_T0_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG_T0_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG_T0_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG_T0_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG_T1_EDGE_INT_MAP +func (o *DPORT_Type) SetAPP_TG_T1_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG_T1_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG_T1_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG_T1_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG_T1_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG_WDT_EDGE_INT_MAP +func (o *DPORT_Type) SetAPP_TG_WDT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG_WDT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG_WDT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG_WDT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG_WDT_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG_LACT_EDGE_INT_MAP +func (o *DPORT_Type) SetAPP_TG_LACT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG_LACT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG_LACT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG_LACT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG_LACT_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG1_T0_EDGE_INT_MAP +func (o *DPORT_Type) SetAPP_TG1_T0_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG1_T0_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG1_T0_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG1_T0_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG1_T0_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG1_T1_EDGE_INT_MAP +func (o *DPORT_Type) SetAPP_TG1_T1_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG1_T1_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG1_T1_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG1_T1_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG1_T1_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG1_WDT_EDGE_INT_MAP +func (o *DPORT_Type) SetAPP_TG1_WDT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG1_WDT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG1_WDT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG1_WDT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG1_WDT_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_TG1_LACT_EDGE_INT_MAP +func (o *DPORT_Type) SetAPP_TG1_LACT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_TG1_LACT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.APP_TG1_LACT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_TG1_LACT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_TG1_LACT_EDGE_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_MMU_IA_INT_MAP +func (o *DPORT_Type) SetAPP_MMU_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_MMU_IA_INT_MAP.Reg, volatile.LoadUint32(&o.APP_MMU_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_MMU_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_MMU_IA_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_MPU_IA_INT_MAP +func (o *DPORT_Type) SetAPP_MPU_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_MPU_IA_INT_MAP.Reg, volatile.LoadUint32(&o.APP_MPU_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_MPU_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_MPU_IA_INT_MAP.Reg) & 0x1f +} + +// DPORT.APP_CACHE_IA_INT_MAP +func (o *DPORT_Type) SetAPP_CACHE_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APP_CACHE_IA_INT_MAP.Reg, volatile.LoadUint32(&o.APP_CACHE_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetAPP_CACHE_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APP_CACHE_IA_INT_MAP.Reg) & 0x1f +} + +// DPORT.AHBLITE_MPU_TABLE_UART +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_UART_UART_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_UART.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UART.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_UART_UART_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UART.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_SPI1 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_SPI1_SPI1_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_SPI1.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI1.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_SPI1_SPI1_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI1.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_SPI0 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_SPI0_SPI0_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_SPI0.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI0.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_SPI0_SPI0_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI0.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_GPIO +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_GPIO_GPIO_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_GPIO.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_GPIO.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_GPIO_GPIO_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_GPIO.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_FE2 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_FE2_FE2_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_FE2.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_FE2.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_FE2_FE2_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_FE2.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_FE +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_FE_FE_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_FE.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_FE.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_FE_FE_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_FE.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_TIMER +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_TIMER_TIMER_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_TIMER.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_TIMER.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_TIMER_TIMER_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_TIMER.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_RTC +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_RTC_RTC_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_RTC.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_RTC.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_RTC_RTC_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_RTC.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_IO_MUX +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_IO_MUX_IOMUX_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_IO_MUX.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_IO_MUX.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_IO_MUX_IOMUX_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_IO_MUX.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_WDG +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_WDG_WDG_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_WDG.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_WDG.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_WDG_WDG_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_WDG.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_HINF +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_HINF_HINF_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_HINF.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_HINF.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_HINF_HINF_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_HINF.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_UHCI1 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_UHCI1_UHCI1_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_UHCI1.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UHCI1.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_UHCI1_UHCI1_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UHCI1.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_MISC +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_MISC_MISC_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_MISC.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_MISC.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_MISC_MISC_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_MISC.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_I2C +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_I2C_I2C_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_I2C.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2C.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_I2C_I2C_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2C.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_I2S0 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_I2S0_I2S0_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_I2S0.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2S0.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_I2S0_I2S0_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2S0.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_UART1 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_UART1_UART1_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_UART1.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UART1.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_UART1_UART1_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UART1.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_BT +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_BT_BT_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_BT.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_BT.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_BT_BT_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_BT.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_BT_BUFFER +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_BT_BUFFER_BTBUFFER_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_BT_BUFFER.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_BT_BUFFER.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_BT_BUFFER_BTBUFFER_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_BT_BUFFER.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_I2C_EXT0 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_I2C_EXT0_I2CEXT0_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_I2C_EXT0.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2C_EXT0.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_I2C_EXT0_I2CEXT0_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2C_EXT0.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_UHCI0 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_UHCI0_UHCI0_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_UHCI0.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UHCI0.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_UHCI0_UHCI0_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UHCI0.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_SLCHOST +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_SLCHOST_SLCHOST_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_SLCHOST.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SLCHOST.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_SLCHOST_SLCHOST_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SLCHOST.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_RMT +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_RMT_RMT_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_RMT.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_RMT.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_RMT_RMT_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_RMT.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_PCNT +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_PCNT_PCNT_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_PCNT.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PCNT.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_PCNT_PCNT_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PCNT.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_SLC +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_SLC_SLC_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_SLC.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SLC.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_SLC_SLC_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SLC.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_LEDC +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_LEDC_LEDC_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_LEDC.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_LEDC.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_LEDC_LEDC_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_LEDC.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_EFUSE +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_EFUSE_EFUSE_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_EFUSE.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_EFUSE.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_EFUSE_EFUSE_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_EFUSE.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_SPI_ENCRYPT +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_SPI_ENCRYPT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_SPI_ENCRYPT.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI_ENCRYPT.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_SPI_ENCRYPT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI_ENCRYPT.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_BB +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_BB_BB_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_BB.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_BB.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_BB_BB_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_BB.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_PWM0 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_PWM0_PWM0_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_PWM0.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWM0.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_PWM0_PWM0_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWM0.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_TIMERGROUP +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_TIMERGROUP_TIMERGROUP_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_TIMERGROUP.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_TIMERGROUP.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_TIMERGROUP_TIMERGROUP_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_TIMERGROUP.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_TIMERGROUP1 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_TIMERGROUP1_TIMERGROUP1_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_TIMERGROUP1.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_TIMERGROUP1.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_TIMERGROUP1_TIMERGROUP1_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_TIMERGROUP1.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_SPI2 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_SPI2_SPI2_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_SPI2.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI2.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_SPI2_SPI2_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI2.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_SPI3 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_SPI3_SPI3_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_SPI3.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI3.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_SPI3_SPI3_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SPI3.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_APB_CTRL +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_APB_CTRL_APBCTRL_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_APB_CTRL.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_APB_CTRL.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_APB_CTRL_APBCTRL_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_APB_CTRL.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_I2C_EXT1 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_I2C_EXT1_I2CEXT1_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_I2C_EXT1.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2C_EXT1.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_I2C_EXT1_I2CEXT1_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2C_EXT1.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_SDIO_HOST +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_SDIO_HOST_SDIOHOST_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_SDIO_HOST.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SDIO_HOST.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_SDIO_HOST_SDIOHOST_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_SDIO_HOST.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_EMAC +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_EMAC_EMAC_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_EMAC.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_EMAC.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_EMAC_EMAC_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_EMAC.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_CAN +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_CAN_CAN_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_CAN.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_CAN.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_CAN_CAN_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_CAN.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_PWM1 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_PWM1_PWM1_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_PWM1.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWM1.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_PWM1_PWM1_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWM1.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_I2S1 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_I2S1_I2S1_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_I2S1.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2S1.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_I2S1_I2S1_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_I2S1.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_UART2 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_UART2_UART2_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_UART2.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UART2.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_UART2_UART2_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_UART2.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_PWM2 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_PWM2_PWM2_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_PWM2.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWM2.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_PWM2_PWM2_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWM2.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_PWM3 +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_PWM3_PWM3_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_PWM3.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWM3.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_PWM3_PWM3_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWM3.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_RWBT +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_RWBT_RWBT_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_RWBT.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_RWBT.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_RWBT_RWBT_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_RWBT.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_BTMAC +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_BTMAC_BTMAC_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_BTMAC.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_BTMAC.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_BTMAC_BTMAC_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_BTMAC.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_WIFIMAC +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_WIFIMAC_WIFIMAC_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_WIFIMAC.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_WIFIMAC.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_WIFIMAC_WIFIMAC_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_WIFIMAC.Reg) & 0x3f +} + +// DPORT.AHBLITE_MPU_TABLE_PWR +func (o *DPORT_Type) SetAHBLITE_MPU_TABLE_PWR_PWR_ACCESS_GRANT_CONFIG(value uint32) { + volatile.StoreUint32(&o.AHBLITE_MPU_TABLE_PWR.Reg, volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWR.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetAHBLITE_MPU_TABLE_PWR_PWR_ACCESS_GRANT_CONFIG() uint32 { + return volatile.LoadUint32(&o.AHBLITE_MPU_TABLE_PWR.Reg) & 0x3f +} + +// DPORT.MEM_ACCESS_DBUG0 +func (o *DPORT_Type) SetMEM_ACCESS_DBUG0_PRO_ROM_MPU_AD(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG0.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG0_PRO_ROM_MPU_AD() uint32 { + return volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg) & 0x1 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG0_PRO_ROM_IA(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG0.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG0_PRO_ROM_IA() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG0_APP_ROM_MPU_AD(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG0.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG0_APP_ROM_MPU_AD() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG0_APP_ROM_IA(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG0.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG0_APP_ROM_IA() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG0_SHARE_ROM_MPU_AD(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG0.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg)&^(0x30)|value<<4) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG0_SHARE_ROM_MPU_AD() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg) & 0x30) >> 4 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG0_SHARE_ROM_IA(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG0.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg)&^(0x3c0)|value<<6) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG0_SHARE_ROM_IA() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg) & 0x3c0) >> 6 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG0_INTERNAL_SRAM_MMU_AD(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG0.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg)&^(0x3c00)|value<<10) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG0_INTERNAL_SRAM_MMU_AD() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg) & 0x3c00) >> 10 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG0_INTERNAL_SRAM_IA(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG0.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg)&^(0x3ffc000)|value<<14) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG0_INTERNAL_SRAM_IA() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg) & 0x3ffc000) >> 14 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG0_INTERNAL_SRAM_MMU_MULTI_HIT(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG0.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg)&^(0x3c000000)|value<<26) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG0_INTERNAL_SRAM_MMU_MULTI_HIT() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG0.Reg) & 0x3c000000) >> 26 +} + +// DPORT.MEM_ACCESS_DBUG1 +func (o *DPORT_Type) SetMEM_ACCESS_DBUG1_INTERNAL_SRAM_MMU_MISS(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG1.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg)&^(0xf)|value) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG1_INTERNAL_SRAM_MMU_MISS() uint32 { + return volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg) & 0xf +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG1_ARB_IA(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG1.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg)&^(0x30)|value<<4) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG1_ARB_IA() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg) & 0x30) >> 4 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG1_PIDGEN_IA(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG1.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg)&^(0xc0)|value<<6) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG1_PIDGEN_IA() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg) & 0xc0) >> 6 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG1_AHB_ACCESS_DENY(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG1.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG1_AHB_ACCESS_DENY() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG1_AHBLITE_ACCESS_DENY(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG1.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG1_AHBLITE_ACCESS_DENY() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetMEM_ACCESS_DBUG1_AHBLITE_IA(value uint32) { + volatile.StoreUint32(&o.MEM_ACCESS_DBUG1.Reg, volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetMEM_ACCESS_DBUG1_AHBLITE_IA() uint32 { + return (volatile.LoadUint32(&o.MEM_ACCESS_DBUG1.Reg) & 0x400) >> 10 +} + +// DPORT.PRO_DCACHE_DBUG0 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG0_PRO_SLAVE_WDATA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG0_PRO_SLAVE_WDATA() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg) & 0x1 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG0_PRO_CACHE_MMU_IA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG0_PRO_CACHE_MMU_IA() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg) & 0x1 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG0_PRO_CACHE_IA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg)&^(0x7e)|value<<1) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG0_PRO_CACHE_IA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg) & 0x7e) >> 1 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG0_PRO_CACHE_STATE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg)&^(0x7ff80)|value<<7) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG0_PRO_CACHE_STATE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg) & 0x7ff80) >> 7 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG0_PRO_WR_BAK_TO_READ(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg)&^(0x80000)|value<<19) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG0_PRO_WR_BAK_TO_READ() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg) & 0x80000) >> 19 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG0_PRO_TX_END(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg)&^(0x100000)|value<<20) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG0_PRO_TX_END() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg) & 0x100000) >> 20 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG0_PRO_SLAVE_WR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg)&^(0x200000)|value<<21) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG0_PRO_SLAVE_WR() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg) & 0x200000) >> 21 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG0_PRO_SLAVE_WDATA_V(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg)&^(0x400000)|value<<22) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG0_PRO_SLAVE_WDATA_V() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg) & 0x400000) >> 22 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG0_PRO_RX_END(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg)&^(0x800000)|value<<23) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG0_PRO_RX_END() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG0.Reg) & 0x800000) >> 23 +} + +// DPORT.PRO_DCACHE_DBUG1 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG1(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG1.Reg, value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG1() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG1.Reg) +} + +// DPORT.PRO_DCACHE_DBUG2 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG2_PRO_CACHE_VADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG2.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG2.Reg)&^(0x7ffffff)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG2_PRO_CACHE_VADDR() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG2.Reg) & 0x7ffffff +} + +// DPORT.PRO_DCACHE_DBUG3 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG3_PRO_MMU_RDATA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg)&^(0x1ff)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG3_PRO_MMU_RDATA() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg) & 0x1ff +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg)&^(0x7e00)|value<<9) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg) & 0x7e00) >> 9 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DRAM1(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DRAM1() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IROM0(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg)&^(0x800)|value<<11) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IROM0() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg) & 0x800) >> 11 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM1(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM1() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM0(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM0() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg) & 0x2000) >> 13 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DROM0(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg)&^(0x4000)|value<<14) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DROM0() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg) & 0x4000) >> 14 +} +func (o *DPORT_Type) SetPRO_DCACHE_DBUG3_PRO_CACHE_IRAM0_PID_ERROR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg)&^(0x8000)|value<<15) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG3_PRO_CACHE_IRAM0_PID_ERROR() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_DBUG3.Reg) & 0x8000) >> 15 +} + +// DPORT.PRO_DCACHE_DBUG4 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG4_PRO_DRAM1ADDR0_IA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG4.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG4.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG4_PRO_DRAM1ADDR0_IA() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG4.Reg) & 0xfffff +} + +// DPORT.PRO_DCACHE_DBUG5 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG5_PRO_DROM0ADDR0_IA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG5.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG5.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG5_PRO_DROM0ADDR0_IA() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG5.Reg) & 0xfffff +} + +// DPORT.PRO_DCACHE_DBUG6 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG6_PRO_IRAM0ADDR_IA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG6.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG6.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG6_PRO_IRAM0ADDR_IA() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG6.Reg) & 0xfffff +} + +// DPORT.PRO_DCACHE_DBUG7 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG7_PRO_IRAM1ADDR_IA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG7.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG7.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG7_PRO_IRAM1ADDR_IA() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG7.Reg) & 0xfffff +} + +// DPORT.PRO_DCACHE_DBUG8 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG8_PRO_IROM0ADDR_IA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG8.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG8.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG8_PRO_IROM0ADDR_IA() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG8.Reg) & 0xfffff +} + +// DPORT.PRO_DCACHE_DBUG9 +func (o *DPORT_Type) SetPRO_DCACHE_DBUG9_PRO_OPSDRAMADDR_IA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_DBUG9.Reg, volatile.LoadUint32(&o.PRO_DCACHE_DBUG9.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetPRO_DCACHE_DBUG9_PRO_OPSDRAMADDR_IA() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_DBUG9.Reg) & 0xfffff +} + +// DPORT.APP_DCACHE_DBUG0 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG0_APP_SLAVE_WDATA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG0_APP_SLAVE_WDATA() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg) & 0x1 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG0_APP_CACHE_MMU_IA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG0_APP_CACHE_MMU_IA() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg) & 0x1 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG0_APP_CACHE_IA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg)&^(0x7e)|value<<1) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG0_APP_CACHE_IA() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg) & 0x7e) >> 1 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG0_APP_CACHE_STATE(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg)&^(0x7ff80)|value<<7) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG0_APP_CACHE_STATE() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg) & 0x7ff80) >> 7 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG0_APP_WR_BAK_TO_READ(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg)&^(0x80000)|value<<19) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG0_APP_WR_BAK_TO_READ() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg) & 0x80000) >> 19 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG0_APP_TX_END(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg)&^(0x100000)|value<<20) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG0_APP_TX_END() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg) & 0x100000) >> 20 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG0_APP_SLAVE_WR(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg)&^(0x200000)|value<<21) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG0_APP_SLAVE_WR() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg) & 0x200000) >> 21 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG0_APP_SLAVE_WDATA_V(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg)&^(0x400000)|value<<22) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG0_APP_SLAVE_WDATA_V() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg) & 0x400000) >> 22 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG0_APP_RX_END(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG0.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg)&^(0x800000)|value<<23) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG0_APP_RX_END() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG0.Reg) & 0x800000) >> 23 +} + +// DPORT.APP_DCACHE_DBUG1 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG1(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG1.Reg, value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG1() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG1.Reg) +} + +// DPORT.APP_DCACHE_DBUG2 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG2_APP_CACHE_VADDR(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG2.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG2.Reg)&^(0x7ffffff)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG2_APP_CACHE_VADDR() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG2.Reg) & 0x7ffffff +} + +// DPORT.APP_DCACHE_DBUG3 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG3_APP_MMU_RDATA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg)&^(0x1ff)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG3_APP_MMU_RDATA() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg) & 0x1ff +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg)&^(0x7e00)|value<<9) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg) & 0x7e00) >> 9 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_OPPOSITE(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_OPPOSITE() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DRAM1(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DRAM1() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IROM0(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg)&^(0x800)|value<<11) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IROM0() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg) & 0x800) >> 11 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM1(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM1() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM0(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM0() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg) & 0x2000) >> 13 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DROM0(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg)&^(0x4000)|value<<14) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DROM0() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg) & 0x4000) >> 14 +} +func (o *DPORT_Type) SetAPP_DCACHE_DBUG3_APP_CACHE_IRAM0_PID_ERROR(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG3.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg)&^(0x8000)|value<<15) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG3_APP_CACHE_IRAM0_PID_ERROR() uint32 { + return (volatile.LoadUint32(&o.APP_DCACHE_DBUG3.Reg) & 0x8000) >> 15 +} + +// DPORT.APP_DCACHE_DBUG4 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG4_APP_DRAM1ADDR0_IA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG4.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG4.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG4_APP_DRAM1ADDR0_IA() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG4.Reg) & 0xfffff +} + +// DPORT.APP_DCACHE_DBUG5 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG5_APP_DROM0ADDR0_IA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG5.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG5.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG5_APP_DROM0ADDR0_IA() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG5.Reg) & 0xfffff +} + +// DPORT.APP_DCACHE_DBUG6 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG6_APP_IRAM0ADDR_IA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG6.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG6.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG6_APP_IRAM0ADDR_IA() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG6.Reg) & 0xfffff +} + +// DPORT.APP_DCACHE_DBUG7 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG7_APP_IRAM1ADDR_IA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG7.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG7.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG7_APP_IRAM1ADDR_IA() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG7.Reg) & 0xfffff +} + +// DPORT.APP_DCACHE_DBUG8 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG8_APP_IROM0ADDR_IA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG8.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG8.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG8_APP_IROM0ADDR_IA() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG8.Reg) & 0xfffff +} + +// DPORT.APP_DCACHE_DBUG9 +func (o *DPORT_Type) SetAPP_DCACHE_DBUG9_APP_OPSDRAMADDR_IA(value uint32) { + volatile.StoreUint32(&o.APP_DCACHE_DBUG9.Reg, volatile.LoadUint32(&o.APP_DCACHE_DBUG9.Reg)&^(0xfffff)|value) +} +func (o *DPORT_Type) GetAPP_DCACHE_DBUG9_APP_OPSDRAMADDR_IA() uint32 { + return volatile.LoadUint32(&o.APP_DCACHE_DBUG9.Reg) & 0xfffff +} + +// DPORT.PRO_CPU_RECORD_CTRL +func (o *DPORT_Type) SetPRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_ENABLE(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_CTRL.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_ENABLE() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_CTRL.Reg) & 0x1 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_DISABLE(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_CTRL.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_CTRL.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_CTRL_PRO_CPU_PDEBUG_ENABLE(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_CTRL.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_CTRL_PRO_CPU_PDEBUG_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_CTRL.Reg) & 0x100) >> 8 +} + +// DPORT.PRO_CPU_RECORD_STATUS +func (o *DPORT_Type) SetPRO_CPU_RECORD_STATUS_PRO_CPU_RECORDING(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_STATUS.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_STATUS.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_STATUS_PRO_CPU_RECORDING() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_STATUS.Reg) & 0x1 +} + +// DPORT.PRO_CPU_RECORD_PID +func (o *DPORT_Type) SetPRO_CPU_RECORD_PID_RECORD_PRO_PID(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PID.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PID.Reg)&^(0x7)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PID_RECORD_PRO_PID() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PID.Reg) & 0x7 +} + +// DPORT.PRO_CPU_RECORD_PDEBUGINST +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGINST(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg, value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGINST() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg) +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_SZ(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg)&^(0xff)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_SZ() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg) & 0xff +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_ISRC(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg)&^(0x7000)|value<<12) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_ISRC() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg) & 0x7000) >> 12 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP_REP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg)&^(0x100000)|value<<20) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP_REP() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg) & 0x100000) >> 20 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg)&^(0x200000)|value<<21) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg) & 0x200000) >> 21 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_CINTL(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg)&^(0xf000000)|value<<24) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_CINTL() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGINST.Reg) & 0xf000000) >> 24 +} + +// DPORT.PRO_CPU_RECORD_PDEBUGSTATUS +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PRO_PDEBUGSTATUS(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGSTATUS.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGSTATUS.Reg)&^(0xff)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PRO_PDEBUGSTATUS() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGSTATUS.Reg) & 0xff +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PDEBUGSTATUS_BBCAUSE(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGSTATUS.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGSTATUS.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PDEBUGSTATUS_BBCAUSE() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGSTATUS.Reg) & 0x3f +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PDEBUGSTATUS_INSNTYPE(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGSTATUS.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGSTATUS.Reg)&^(0x3f)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PDEBUGSTATUS_INSNTYPE() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGSTATUS.Reg) & 0x3f +} + +// DPORT.PRO_CPU_RECORD_PDEBUGDATA +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_OTHER(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_OTHER() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x1 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_EXCVEC(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x1f)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_EXCVEC() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x1f +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_SR(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0xff)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_SR() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0xff +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RER(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RER() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x1 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFF(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFF() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WER(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WER() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFFCONFL(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFFCONFL() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_ER(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x3ffc)|value<<2) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_ER() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x3ffc) >> 2 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_DCM(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_DCM() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSU(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSU() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ICM(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x40)|value<<6) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ICM() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x40) >> 6 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IRAMBUSY(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x80)|value<<7) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IRAMBUSY() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x80) >> 7 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_LSU(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_LSU() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IPIF(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IPIF() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RSR(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RSR() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_TIE(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_TIE() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WSR(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WSR() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_RUN(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_RUN() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_XSR(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_XSR() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_STR(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x800)|value<<11) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_STR() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x800) >> 11 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPIFETCH(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPIFETCH() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_L32R(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_L32R() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x2000) >> 13 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSPROC(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x4000)|value<<14) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSPROC() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x4000) >> 14 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPLOAD(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x8000)|value<<15) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPLOAD() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x8000) >> 15 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_MEMW(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x10000)|value<<16) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_MEMW() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x10000) >> 16 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_EXCCAUSE(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x3f0000)|value<<16) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_EXCCAUSE() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x3f0000) >> 16 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BANKCONFL(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x10000)|value<<16) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BANKCONFL() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x10000) >> 16 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_HALT(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x20000)|value<<17) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_HALT() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x20000) >> 17 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERMUL(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x40000)|value<<18) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERMUL() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x40000) >> 18 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERDIV(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg)&^(0x80000)|value<<19) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERDIV() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGDATA.Reg) & 0x80000) >> 19 +} + +// DPORT.PRO_CPU_RECORD_PDEBUGPC +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGPC.Reg, value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGPC.Reg) +} + +// DPORT.PRO_CPU_RECORD_PDEBUGLS0STAT +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_TYPE(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0xf)|value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_TYPE() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0xf +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_SZ(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0xf0)|value<<4) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_SZ() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0xf0) >> 4 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DTLBM(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DTLBM() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0x100) >> 8 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCM(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0x200)|value<<9) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCM() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0x200) >> 9 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCH(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0x400)|value<<10) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCH() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0x400) >> 10 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_UC(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0x1000)|value<<12) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_UC() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0x1000) >> 12 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_WB(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0x2000)|value<<13) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_WB() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0x2000) >> 13 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_COH(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0x10000)|value<<16) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_COH() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0x10000) >> 16 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_STCOH(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0x60000)|value<<17) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_STCOH() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0x60000) >> 17 +} +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_TGT(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg, volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg)&^(0xf00000)|value<<20) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_TGT() uint32 { + return (volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0STAT.Reg) & 0xf00000) >> 20 +} + +// DPORT.PRO_CPU_RECORD_PDEBUGLS0ADDR +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0ADDR.Reg, value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0ADDR.Reg) +} + +// DPORT.PRO_CPU_RECORD_PDEBUGLS0DATA +func (o *DPORT_Type) SetPRO_CPU_RECORD_PDEBUGLS0DATA(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_RECORD_PDEBUGLS0DATA.Reg, value) +} +func (o *DPORT_Type) GetPRO_CPU_RECORD_PDEBUGLS0DATA() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_RECORD_PDEBUGLS0DATA.Reg) +} + +// DPORT.APP_CPU_RECORD_CTRL +func (o *DPORT_Type) SetAPP_CPU_RECORD_CTRL_APP_CPU_RECORD_ENABLE(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_CTRL.Reg, volatile.LoadUint32(&o.APP_CPU_RECORD_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_CTRL_APP_CPU_RECORD_ENABLE() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_CTRL.Reg) & 0x1 +} +func (o *DPORT_Type) SetAPP_CPU_RECORD_CTRL_APP_CPU_RECORD_DISABLE(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_CTRL.Reg, volatile.LoadUint32(&o.APP_CPU_RECORD_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_CTRL_APP_CPU_RECORD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.APP_CPU_RECORD_CTRL.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetAPP_CPU_RECORD_CTRL_APP_CPU_PDEBUG_ENABLE(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_CTRL.Reg, volatile.LoadUint32(&o.APP_CPU_RECORD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_CTRL_APP_CPU_PDEBUG_ENABLE() uint32 { + return (volatile.LoadUint32(&o.APP_CPU_RECORD_CTRL.Reg) & 0x100) >> 8 +} + +// DPORT.APP_CPU_RECORD_STATUS +func (o *DPORT_Type) SetAPP_CPU_RECORD_STATUS_APP_CPU_RECORDING(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_STATUS.Reg, volatile.LoadUint32(&o.APP_CPU_RECORD_STATUS.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_STATUS_APP_CPU_RECORDING() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_STATUS.Reg) & 0x1 +} + +// DPORT.APP_CPU_RECORD_PID +func (o *DPORT_Type) SetAPP_CPU_RECORD_PID_RECORD_APP_PID(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_PID.Reg, volatile.LoadUint32(&o.APP_CPU_RECORD_PID.Reg)&^(0x7)|value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_PID_RECORD_APP_PID() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_PID.Reg) & 0x7 +} + +// DPORT.APP_CPU_RECORD_PDEBUGINST +func (o *DPORT_Type) SetAPP_CPU_RECORD_PDEBUGINST(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_PDEBUGINST.Reg, value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_PDEBUGINST() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_PDEBUGINST.Reg) +} + +// DPORT.APP_CPU_RECORD_PDEBUGSTATUS +func (o *DPORT_Type) SetAPP_CPU_RECORD_PDEBUGSTATUS_RECORD_APP_PDEBUGSTATUS(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_PDEBUGSTATUS.Reg, volatile.LoadUint32(&o.APP_CPU_RECORD_PDEBUGSTATUS.Reg)&^(0xff)|value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_PDEBUGSTATUS_RECORD_APP_PDEBUGSTATUS() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_PDEBUGSTATUS.Reg) & 0xff +} + +// DPORT.APP_CPU_RECORD_PDEBUGDATA +func (o *DPORT_Type) SetAPP_CPU_RECORD_PDEBUGDATA(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_PDEBUGDATA.Reg, value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_PDEBUGDATA() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_PDEBUGDATA.Reg) +} + +// DPORT.APP_CPU_RECORD_PDEBUGPC +func (o *DPORT_Type) SetAPP_CPU_RECORD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_PDEBUGPC.Reg, value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_PDEBUGPC.Reg) +} + +// DPORT.APP_CPU_RECORD_PDEBUGLS0STAT +func (o *DPORT_Type) SetAPP_CPU_RECORD_PDEBUGLS0STAT(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_PDEBUGLS0STAT.Reg, value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_PDEBUGLS0STAT() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_PDEBUGLS0STAT.Reg) +} + +// DPORT.APP_CPU_RECORD_PDEBUGLS0ADDR +func (o *DPORT_Type) SetAPP_CPU_RECORD_PDEBUGLS0ADDR(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_PDEBUGLS0ADDR.Reg, value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_PDEBUGLS0ADDR() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_PDEBUGLS0ADDR.Reg) +} + +// DPORT.APP_CPU_RECORD_PDEBUGLS0DATA +func (o *DPORT_Type) SetAPP_CPU_RECORD_PDEBUGLS0DATA(value uint32) { + volatile.StoreUint32(&o.APP_CPU_RECORD_PDEBUGLS0DATA.Reg, value) +} +func (o *DPORT_Type) GetAPP_CPU_RECORD_PDEBUGLS0DATA() uint32 { + return volatile.LoadUint32(&o.APP_CPU_RECORD_PDEBUGLS0DATA.Reg) +} + +// DPORT.RSA_PD_CTRL +func (o *DPORT_Type) SetRSA_PD_CTRL_RSA_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetRSA_PD_CTRL_RSA_PD() uint32 { + return volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x1 +} + +// DPORT.ROM_MPU_TABLE0 +func (o *DPORT_Type) SetROM_MPU_TABLE0(value uint32) { + volatile.StoreUint32(&o.ROM_MPU_TABLE0.Reg, volatile.LoadUint32(&o.ROM_MPU_TABLE0.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetROM_MPU_TABLE0() uint32 { + return volatile.LoadUint32(&o.ROM_MPU_TABLE0.Reg) & 0x3 +} + +// DPORT.ROM_MPU_TABLE1 +func (o *DPORT_Type) SetROM_MPU_TABLE1(value uint32) { + volatile.StoreUint32(&o.ROM_MPU_TABLE1.Reg, volatile.LoadUint32(&o.ROM_MPU_TABLE1.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetROM_MPU_TABLE1() uint32 { + return volatile.LoadUint32(&o.ROM_MPU_TABLE1.Reg) & 0x3 +} + +// DPORT.ROM_MPU_TABLE2 +func (o *DPORT_Type) SetROM_MPU_TABLE2(value uint32) { + volatile.StoreUint32(&o.ROM_MPU_TABLE2.Reg, volatile.LoadUint32(&o.ROM_MPU_TABLE2.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetROM_MPU_TABLE2() uint32 { + return volatile.LoadUint32(&o.ROM_MPU_TABLE2.Reg) & 0x3 +} + +// DPORT.ROM_MPU_TABLE3 +func (o *DPORT_Type) SetROM_MPU_TABLE3(value uint32) { + volatile.StoreUint32(&o.ROM_MPU_TABLE3.Reg, volatile.LoadUint32(&o.ROM_MPU_TABLE3.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetROM_MPU_TABLE3() uint32 { + return volatile.LoadUint32(&o.ROM_MPU_TABLE3.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE0 +func (o *DPORT_Type) SetSHROM_MPU_TABLE0(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE0.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE0.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE0() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE0.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE1 +func (o *DPORT_Type) SetSHROM_MPU_TABLE1(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE1.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE1.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE1() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE1.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE2 +func (o *DPORT_Type) SetSHROM_MPU_TABLE2(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE2.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE2.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE2() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE2.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE3 +func (o *DPORT_Type) SetSHROM_MPU_TABLE3(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE3.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE3.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE3() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE3.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE4 +func (o *DPORT_Type) SetSHROM_MPU_TABLE4(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE4.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE4.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE4() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE4.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE5 +func (o *DPORT_Type) SetSHROM_MPU_TABLE5(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE5.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE5.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE5() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE5.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE6 +func (o *DPORT_Type) SetSHROM_MPU_TABLE6(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE6.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE6.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE6() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE6.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE7 +func (o *DPORT_Type) SetSHROM_MPU_TABLE7(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE7.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE7.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE7() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE7.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE8 +func (o *DPORT_Type) SetSHROM_MPU_TABLE8(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE8.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE8.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE8() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE8.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE9 +func (o *DPORT_Type) SetSHROM_MPU_TABLE9(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE9.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE9.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE9() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE9.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE10 +func (o *DPORT_Type) SetSHROM_MPU_TABLE10(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE10.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE10.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE10() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE10.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE11 +func (o *DPORT_Type) SetSHROM_MPU_TABLE11(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE11.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE11.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE11() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE11.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE12 +func (o *DPORT_Type) SetSHROM_MPU_TABLE12(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE12.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE12.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE12() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE12.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE13 +func (o *DPORT_Type) SetSHROM_MPU_TABLE13(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE13.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE13.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE13() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE13.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE14 +func (o *DPORT_Type) SetSHROM_MPU_TABLE14(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE14.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE14.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE14() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE14.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE15 +func (o *DPORT_Type) SetSHROM_MPU_TABLE15(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE15.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE15.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE15() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE15.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE16 +func (o *DPORT_Type) SetSHROM_MPU_TABLE16(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE16.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE16.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE16() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE16.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE17 +func (o *DPORT_Type) SetSHROM_MPU_TABLE17(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE17.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE17.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE17() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE17.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE18 +func (o *DPORT_Type) SetSHROM_MPU_TABLE18(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE18.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE18.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE18() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE18.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE19 +func (o *DPORT_Type) SetSHROM_MPU_TABLE19(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE19.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE19.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE19() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE19.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE20 +func (o *DPORT_Type) SetSHROM_MPU_TABLE20(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE20.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE20.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE20() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE20.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE21 +func (o *DPORT_Type) SetSHROM_MPU_TABLE21(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE21.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE21.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE21() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE21.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE22 +func (o *DPORT_Type) SetSHROM_MPU_TABLE22(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE22.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE22.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE22() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE22.Reg) & 0x3 +} + +// DPORT.SHROM_MPU_TABLE23 +func (o *DPORT_Type) SetSHROM_MPU_TABLE23(value uint32) { + volatile.StoreUint32(&o.SHROM_MPU_TABLE23.Reg, volatile.LoadUint32(&o.SHROM_MPU_TABLE23.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSHROM_MPU_TABLE23() uint32 { + return volatile.LoadUint32(&o.SHROM_MPU_TABLE23.Reg) & 0x3 +} + +// DPORT.IMMU_TABLE0 +func (o *DPORT_Type) SetIMMU_TABLE0(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE0.Reg, volatile.LoadUint32(&o.IMMU_TABLE0.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE0() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE0.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE1 +func (o *DPORT_Type) SetIMMU_TABLE1(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE1.Reg, volatile.LoadUint32(&o.IMMU_TABLE1.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE1() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE1.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE2 +func (o *DPORT_Type) SetIMMU_TABLE2(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE2.Reg, volatile.LoadUint32(&o.IMMU_TABLE2.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE2() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE2.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE3 +func (o *DPORT_Type) SetIMMU_TABLE3(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE3.Reg, volatile.LoadUint32(&o.IMMU_TABLE3.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE3() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE3.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE4 +func (o *DPORT_Type) SetIMMU_TABLE4(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE4.Reg, volatile.LoadUint32(&o.IMMU_TABLE4.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE4() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE4.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE5 +func (o *DPORT_Type) SetIMMU_TABLE5(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE5.Reg, volatile.LoadUint32(&o.IMMU_TABLE5.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE5() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE5.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE6 +func (o *DPORT_Type) SetIMMU_TABLE6(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE6.Reg, volatile.LoadUint32(&o.IMMU_TABLE6.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE6() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE6.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE7 +func (o *DPORT_Type) SetIMMU_TABLE7(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE7.Reg, volatile.LoadUint32(&o.IMMU_TABLE7.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE7() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE7.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE8 +func (o *DPORT_Type) SetIMMU_TABLE8(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE8.Reg, volatile.LoadUint32(&o.IMMU_TABLE8.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE8() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE8.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE9 +func (o *DPORT_Type) SetIMMU_TABLE9(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE9.Reg, volatile.LoadUint32(&o.IMMU_TABLE9.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE9() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE9.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE10 +func (o *DPORT_Type) SetIMMU_TABLE10(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE10.Reg, volatile.LoadUint32(&o.IMMU_TABLE10.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE10() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE10.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE11 +func (o *DPORT_Type) SetIMMU_TABLE11(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE11.Reg, volatile.LoadUint32(&o.IMMU_TABLE11.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE11() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE11.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE12 +func (o *DPORT_Type) SetIMMU_TABLE12(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE12.Reg, volatile.LoadUint32(&o.IMMU_TABLE12.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE12() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE12.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE13 +func (o *DPORT_Type) SetIMMU_TABLE13(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE13.Reg, volatile.LoadUint32(&o.IMMU_TABLE13.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE13() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE13.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE14 +func (o *DPORT_Type) SetIMMU_TABLE14(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE14.Reg, volatile.LoadUint32(&o.IMMU_TABLE14.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE14() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE14.Reg) & 0x7f +} + +// DPORT.IMMU_TABLE15 +func (o *DPORT_Type) SetIMMU_TABLE15(value uint32) { + volatile.StoreUint32(&o.IMMU_TABLE15.Reg, volatile.LoadUint32(&o.IMMU_TABLE15.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetIMMU_TABLE15() uint32 { + return volatile.LoadUint32(&o.IMMU_TABLE15.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE0 +func (o *DPORT_Type) SetDMMU_TABLE0(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE0.Reg, volatile.LoadUint32(&o.DMMU_TABLE0.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE0() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE0.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE1 +func (o *DPORT_Type) SetDMMU_TABLE1(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE1.Reg, volatile.LoadUint32(&o.DMMU_TABLE1.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE1() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE1.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE2 +func (o *DPORT_Type) SetDMMU_TABLE2(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE2.Reg, volatile.LoadUint32(&o.DMMU_TABLE2.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE2() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE2.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE3 +func (o *DPORT_Type) SetDMMU_TABLE3(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE3.Reg, volatile.LoadUint32(&o.DMMU_TABLE3.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE3() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE3.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE4 +func (o *DPORT_Type) SetDMMU_TABLE4(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE4.Reg, volatile.LoadUint32(&o.DMMU_TABLE4.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE4() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE4.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE5 +func (o *DPORT_Type) SetDMMU_TABLE5(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE5.Reg, volatile.LoadUint32(&o.DMMU_TABLE5.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE5() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE5.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE6 +func (o *DPORT_Type) SetDMMU_TABLE6(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE6.Reg, volatile.LoadUint32(&o.DMMU_TABLE6.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE6() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE6.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE7 +func (o *DPORT_Type) SetDMMU_TABLE7(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE7.Reg, volatile.LoadUint32(&o.DMMU_TABLE7.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE7() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE7.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE8 +func (o *DPORT_Type) SetDMMU_TABLE8(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE8.Reg, volatile.LoadUint32(&o.DMMU_TABLE8.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE8() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE8.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE9 +func (o *DPORT_Type) SetDMMU_TABLE9(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE9.Reg, volatile.LoadUint32(&o.DMMU_TABLE9.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE9() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE9.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE10 +func (o *DPORT_Type) SetDMMU_TABLE10(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE10.Reg, volatile.LoadUint32(&o.DMMU_TABLE10.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE10() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE10.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE11 +func (o *DPORT_Type) SetDMMU_TABLE11(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE11.Reg, volatile.LoadUint32(&o.DMMU_TABLE11.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE11() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE11.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE12 +func (o *DPORT_Type) SetDMMU_TABLE12(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE12.Reg, volatile.LoadUint32(&o.DMMU_TABLE12.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE12() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE12.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE13 +func (o *DPORT_Type) SetDMMU_TABLE13(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE13.Reg, volatile.LoadUint32(&o.DMMU_TABLE13.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE13() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE13.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE14 +func (o *DPORT_Type) SetDMMU_TABLE14(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE14.Reg, volatile.LoadUint32(&o.DMMU_TABLE14.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE14() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE14.Reg) & 0x7f +} + +// DPORT.DMMU_TABLE15 +func (o *DPORT_Type) SetDMMU_TABLE15(value uint32) { + volatile.StoreUint32(&o.DMMU_TABLE15.Reg, volatile.LoadUint32(&o.DMMU_TABLE15.Reg)&^(0x7f)|value) +} +func (o *DPORT_Type) GetDMMU_TABLE15() uint32 { + return volatile.LoadUint32(&o.DMMU_TABLE15.Reg) & 0x7f +} + +// DPORT.PRO_INTRUSION_CTRL +func (o *DPORT_Type) SetPRO_INTRUSION_CTRL_PRO_INTRUSION_RECORD_RESET_N(value uint32) { + volatile.StoreUint32(&o.PRO_INTRUSION_CTRL.Reg, volatile.LoadUint32(&o.PRO_INTRUSION_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetPRO_INTRUSION_CTRL_PRO_INTRUSION_RECORD_RESET_N() uint32 { + return volatile.LoadUint32(&o.PRO_INTRUSION_CTRL.Reg) & 0x1 +} + +// DPORT.PRO_INTRUSION_STATUS +func (o *DPORT_Type) SetPRO_INTRUSION_STATUS_PRO_INTRUSION_RECORD(value uint32) { + volatile.StoreUint32(&o.PRO_INTRUSION_STATUS.Reg, volatile.LoadUint32(&o.PRO_INTRUSION_STATUS.Reg)&^(0xf)|value) +} +func (o *DPORT_Type) GetPRO_INTRUSION_STATUS_PRO_INTRUSION_RECORD() uint32 { + return volatile.LoadUint32(&o.PRO_INTRUSION_STATUS.Reg) & 0xf +} + +// DPORT.APP_INTRUSION_CTRL +func (o *DPORT_Type) SetAPP_INTRUSION_CTRL_APP_INTRUSION_RECORD_RESET_N(value uint32) { + volatile.StoreUint32(&o.APP_INTRUSION_CTRL.Reg, volatile.LoadUint32(&o.APP_INTRUSION_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetAPP_INTRUSION_CTRL_APP_INTRUSION_RECORD_RESET_N() uint32 { + return volatile.LoadUint32(&o.APP_INTRUSION_CTRL.Reg) & 0x1 +} + +// DPORT.APP_INTRUSION_STATUS +func (o *DPORT_Type) SetAPP_INTRUSION_STATUS_APP_INTRUSION_RECORD(value uint32) { + volatile.StoreUint32(&o.APP_INTRUSION_STATUS.Reg, volatile.LoadUint32(&o.APP_INTRUSION_STATUS.Reg)&^(0xf)|value) +} +func (o *DPORT_Type) GetAPP_INTRUSION_STATUS_APP_INTRUSION_RECORD() uint32 { + return volatile.LoadUint32(&o.APP_INTRUSION_STATUS.Reg) & 0xf +} + +// DPORT.FRONT_END_MEM_PD +func (o *DPORT_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU() uint32 { + return volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x1 +} +func (o *DPORT_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x8) >> 3 +} + +// DPORT.MMU_IA_INT_EN +func (o *DPORT_Type) SetMMU_IA_INT_EN(value uint32) { + volatile.StoreUint32(&o.MMU_IA_INT_EN.Reg, volatile.LoadUint32(&o.MMU_IA_INT_EN.Reg)&^(0xffffff)|value) +} +func (o *DPORT_Type) GetMMU_IA_INT_EN() uint32 { + return volatile.LoadUint32(&o.MMU_IA_INT_EN.Reg) & 0xffffff +} + +// DPORT.MPU_IA_INT_EN +func (o *DPORT_Type) SetMPU_IA_INT_EN(value uint32) { + volatile.StoreUint32(&o.MPU_IA_INT_EN.Reg, volatile.LoadUint32(&o.MPU_IA_INT_EN.Reg)&^(0x1ffff)|value) +} +func (o *DPORT_Type) GetMPU_IA_INT_EN() uint32 { + return volatile.LoadUint32(&o.MPU_IA_INT_EN.Reg) & 0x1ffff +} + +// DPORT.CACHE_IA_INT_EN +func (o *DPORT_Type) SetCACHE_IA_INT_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0xfffffff)|value) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN() uint32 { + return volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0xfffffff +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_APP_DROM0(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_APP_DROM0() uint32 { + return volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x1 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM0(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM0() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x2) >> 1 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM1(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x4)|value<<2) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM1() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x4) >> 2 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_APP_IROM0(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x8)|value<<3) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_APP_IROM0() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x8) >> 3 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_APP_DRAM1(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x10)|value<<4) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_APP_DRAM1() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x10) >> 4 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_APP_OPPOSITE(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x20)|value<<5) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_APP_OPPOSITE() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x20) >> 5 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_DROM0(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x4000)|value<<14) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_DROM0() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x4000) >> 14 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM0(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x8000)|value<<15) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM0() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x8000) >> 15 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM1(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x10000)|value<<16) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM1() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x10000) >> 16 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_IROM0(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x20000)|value<<17) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_IROM0() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x20000) >> 17 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_DRAM1(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x40000)|value<<18) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_DRAM1() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x40000) >> 18 +} +func (o *DPORT_Type) SetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_OPPOSITE(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_EN.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg)&^(0x80000)|value<<19) +} +func (o *DPORT_Type) GetCACHE_IA_INT_EN_CACHE_IA_INT_PRO_OPPOSITE() uint32 { + return (volatile.LoadUint32(&o.CACHE_IA_INT_EN.Reg) & 0x80000) >> 19 +} + +// DPORT.SECURE_BOOT_CTRL +func (o *DPORT_Type) SetSECURE_BOOT_CTRL_SW_BOOTLOADER_SEL(value uint32) { + volatile.StoreUint32(&o.SECURE_BOOT_CTRL.Reg, volatile.LoadUint32(&o.SECURE_BOOT_CTRL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetSECURE_BOOT_CTRL_SW_BOOTLOADER_SEL() uint32 { + return volatile.LoadUint32(&o.SECURE_BOOT_CTRL.Reg) & 0x1 +} + +// DPORT.SPI_DMA_CHAN_SEL +func (o *DPORT_Type) SetSPI_DMA_CHAN_SEL_SPI1_DMA_CHAN_SEL(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CHAN_SEL.Reg, volatile.LoadUint32(&o.SPI_DMA_CHAN_SEL.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetSPI_DMA_CHAN_SEL_SPI1_DMA_CHAN_SEL() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_CHAN_SEL.Reg) & 0x3 +} +func (o *DPORT_Type) SetSPI_DMA_CHAN_SEL_SPI2_DMA_CHAN_SEL(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CHAN_SEL.Reg, volatile.LoadUint32(&o.SPI_DMA_CHAN_SEL.Reg)&^(0xc)|value<<2) +} +func (o *DPORT_Type) GetSPI_DMA_CHAN_SEL_SPI2_DMA_CHAN_SEL() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CHAN_SEL.Reg) & 0xc) >> 2 +} +func (o *DPORT_Type) SetSPI_DMA_CHAN_SEL_SPI3_DMA_CHAN_SEL(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CHAN_SEL.Reg, volatile.LoadUint32(&o.SPI_DMA_CHAN_SEL.Reg)&^(0x30)|value<<4) +} +func (o *DPORT_Type) GetSPI_DMA_CHAN_SEL_SPI3_DMA_CHAN_SEL() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CHAN_SEL.Reg) & 0x30) >> 4 +} + +// DPORT.PRO_VECBASE_CTRL +func (o *DPORT_Type) SetPRO_VECBASE_CTRL_PRO_OUT_VECBASE_SEL(value uint32) { + volatile.StoreUint32(&o.PRO_VECBASE_CTRL.Reg, volatile.LoadUint32(&o.PRO_VECBASE_CTRL.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetPRO_VECBASE_CTRL_PRO_OUT_VECBASE_SEL() uint32 { + return volatile.LoadUint32(&o.PRO_VECBASE_CTRL.Reg) & 0x3 +} + +// DPORT.PRO_VECBASE_SET +func (o *DPORT_Type) SetPRO_VECBASE_SET_PRO_OUT_VECBASE(value uint32) { + volatile.StoreUint32(&o.PRO_VECBASE_SET.Reg, volatile.LoadUint32(&o.PRO_VECBASE_SET.Reg)&^(0x3fffff)|value) +} +func (o *DPORT_Type) GetPRO_VECBASE_SET_PRO_OUT_VECBASE() uint32 { + return volatile.LoadUint32(&o.PRO_VECBASE_SET.Reg) & 0x3fffff +} + +// DPORT.APP_VECBASE_CTRL +func (o *DPORT_Type) SetAPP_VECBASE_CTRL_APP_OUT_VECBASE_SEL(value uint32) { + volatile.StoreUint32(&o.APP_VECBASE_CTRL.Reg, volatile.LoadUint32(&o.APP_VECBASE_CTRL.Reg)&^(0x3)|value) +} +func (o *DPORT_Type) GetAPP_VECBASE_CTRL_APP_OUT_VECBASE_SEL() uint32 { + return volatile.LoadUint32(&o.APP_VECBASE_CTRL.Reg) & 0x3 +} + +// DPORT.APP_VECBASE_SET +func (o *DPORT_Type) SetAPP_VECBASE_SET_APP_OUT_VECBASE(value uint32) { + volatile.StoreUint32(&o.APP_VECBASE_SET.Reg, volatile.LoadUint32(&o.APP_VECBASE_SET.Reg)&^(0x3fffff)|value) +} +func (o *DPORT_Type) GetAPP_VECBASE_SET_APP_OUT_VECBASE() uint32 { + return volatile.LoadUint32(&o.APP_VECBASE_SET.Reg) & 0x3fffff +} + +// DPORT.DATE +func (o *DPORT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *DPORT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// eFuse Controller +type EFUSE_Type struct { + BLK0_RDATA0 volatile.Register32 // 0x0 + BLK0_RDATA1 volatile.Register32 // 0x4 + BLK0_RDATA2 volatile.Register32 // 0x8 + BLK0_RDATA3 volatile.Register32 // 0xC + BLK0_RDATA4 volatile.Register32 // 0x10 + BLK0_RDATA5 volatile.Register32 // 0x14 + BLK0_RDATA6 volatile.Register32 // 0x18 + BLK0_WDATA0 volatile.Register32 // 0x1C + BLK0_WDATA1 volatile.Register32 // 0x20 + BLK0_WDATA2 volatile.Register32 // 0x24 + BLK0_WDATA3 volatile.Register32 // 0x28 + BLK0_WDATA4 volatile.Register32 // 0x2C + BLK0_WDATA5 volatile.Register32 // 0x30 + BLK0_WDATA6 volatile.Register32 // 0x34 + BLK1_RDATA0 volatile.Register32 // 0x38 + BLK1_RDATA1 volatile.Register32 // 0x3C + BLK1_RDATA2 volatile.Register32 // 0x40 + BLK1_RDATA3 volatile.Register32 // 0x44 + BLK1_RDATA4 volatile.Register32 // 0x48 + BLK1_RDATA5 volatile.Register32 // 0x4C + BLK1_RDATA6 volatile.Register32 // 0x50 + BLK1_RDATA7 volatile.Register32 // 0x54 + BLK2_RDATA0 volatile.Register32 // 0x58 + BLK2_RDATA1 volatile.Register32 // 0x5C + BLK2_RDATA2 volatile.Register32 // 0x60 + BLK2_RDATA3 volatile.Register32 // 0x64 + BLK2_RDATA4 volatile.Register32 // 0x68 + BLK2_RDATA5 volatile.Register32 // 0x6C + BLK2_RDATA6 volatile.Register32 // 0x70 + BLK2_RDATA7 volatile.Register32 // 0x74 + BLK3_RDATA0 volatile.Register32 // 0x78 + BLK3_RDATA1 volatile.Register32 // 0x7C + BLK3_RDATA2 volatile.Register32 // 0x80 + BLK3_RDATA3 volatile.Register32 // 0x84 + BLK3_RDATA4 volatile.Register32 // 0x88 + BLK3_RDATA5 volatile.Register32 // 0x8C + BLK3_RDATA6 volatile.Register32 // 0x90 + BLK3_RDATA7 volatile.Register32 // 0x94 + BLK1_WDATA0 volatile.Register32 // 0x98 + BLK1_WDATA1 volatile.Register32 // 0x9C + BLK1_WDATA2 volatile.Register32 // 0xA0 + BLK1_WDATA3 volatile.Register32 // 0xA4 + BLK1_WDATA4 volatile.Register32 // 0xA8 + BLK1_WDATA5 volatile.Register32 // 0xAC + BLK1_WDATA6 volatile.Register32 // 0xB0 + BLK1_WDATA7 volatile.Register32 // 0xB4 + BLK2_WDATA0 volatile.Register32 // 0xB8 + BLK2_WDATA1 volatile.Register32 // 0xBC + BLK2_WDATA2 volatile.Register32 // 0xC0 + BLK2_WDATA3 volatile.Register32 // 0xC4 + BLK2_WDATA4 volatile.Register32 // 0xC8 + BLK2_WDATA5 volatile.Register32 // 0xCC + BLK2_WDATA6 volatile.Register32 // 0xD0 + BLK2_WDATA7 volatile.Register32 // 0xD4 + BLK3_WDATA0 volatile.Register32 // 0xD8 + BLK3_WDATA1 volatile.Register32 // 0xDC + BLK3_WDATA2 volatile.Register32 // 0xE0 + BLK3_WDATA3 volatile.Register32 // 0xE4 + BLK3_WDATA4 volatile.Register32 // 0xE8 + BLK3_WDATA5 volatile.Register32 // 0xEC + BLK3_WDATA6 volatile.Register32 // 0xF0 + BLK3_WDATA7 volatile.Register32 // 0xF4 + CLK volatile.Register32 // 0xF8 + CONF volatile.Register32 // 0xFC + STATUS volatile.Register32 // 0x100 + CMD volatile.Register32 // 0x104 + INT_RAW volatile.Register32 // 0x108 + INT_ST volatile.Register32 // 0x10C + INT_ENA volatile.Register32 // 0x110 + INT_CLR volatile.Register32 // 0x114 + DAC_CONF volatile.Register32 // 0x118 + DEC_STATUS volatile.Register32 // 0x11C + _ [220]byte + DATE volatile.Register32 // 0x1FC +} + +// EFUSE.BLK0_RDATA0 +func (o *EFUSE_Type) SetBLK0_RDATA0_RD_EFUSE_WR_DIS(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA0.Reg, volatile.LoadUint32(&o.BLK0_RDATA0.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetBLK0_RDATA0_RD_EFUSE_WR_DIS() uint32 { + return volatile.LoadUint32(&o.BLK0_RDATA0.Reg) & 0xffff +} +func (o *EFUSE_Type) SetBLK0_RDATA0_RD_EFUSE_RD_DIS(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA0.Reg, volatile.LoadUint32(&o.BLK0_RDATA0.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetBLK0_RDATA0_RD_EFUSE_RD_DIS() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA0.Reg) & 0xf0000) >> 16 +} +func (o *EFUSE_Type) SetBLK0_RDATA0_RD_FLASH_CRYPT_CNT(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA0.Reg, volatile.LoadUint32(&o.BLK0_RDATA0.Reg)&^(0x7f00000)|value<<20) +} +func (o *EFUSE_Type) GetBLK0_RDATA0_RD_FLASH_CRYPT_CNT() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA0.Reg) & 0x7f00000) >> 20 +} +func (o *EFUSE_Type) SetBLK0_RDATA0_RD_UART_DOWNLOAD_DIS(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA0.Reg, volatile.LoadUint32(&o.BLK0_RDATA0.Reg)&^(0x8000000)|value<<27) +} +func (o *EFUSE_Type) GetBLK0_RDATA0_RD_UART_DOWNLOAD_DIS() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA0.Reg) & 0x8000000) >> 27 +} +func (o *EFUSE_Type) SetBLK0_RDATA0_RESERVED_0_28(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA0.Reg, volatile.LoadUint32(&o.BLK0_RDATA0.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetBLK0_RDATA0_RESERVED_0_28() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA0.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.BLK0_RDATA1 +func (o *EFUSE_Type) SetBLK0_RDATA1(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA1.Reg, value) +} +func (o *EFUSE_Type) GetBLK0_RDATA1() uint32 { + return volatile.LoadUint32(&o.BLK0_RDATA1.Reg) +} + +// EFUSE.BLK0_RDATA2 +func (o *EFUSE_Type) SetBLK0_RDATA2_RD_MAC_1(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA2.Reg, volatile.LoadUint32(&o.BLK0_RDATA2.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetBLK0_RDATA2_RD_MAC_1() uint32 { + return volatile.LoadUint32(&o.BLK0_RDATA2.Reg) & 0xffff +} +func (o *EFUSE_Type) SetBLK0_RDATA2_RD_MAC_CRC(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA2.Reg, volatile.LoadUint32(&o.BLK0_RDATA2.Reg)&^(0xff0000)|value<<16) +} +func (o *EFUSE_Type) GetBLK0_RDATA2_RD_MAC_CRC() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA2.Reg) & 0xff0000) >> 16 +} +func (o *EFUSE_Type) SetBLK0_RDATA2_RD_RESERVE_0_88(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA2.Reg, volatile.LoadUint32(&o.BLK0_RDATA2.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetBLK0_RDATA2_RD_RESERVE_0_88() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA2.Reg) & 0xff000000) >> 24 +} + +// EFUSE.BLK0_RDATA3 +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_DISABLE_APP_CPU(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_DISABLE_APP_CPU() uint32 { + return volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_DISABLE_BT(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_DISABLE_BT() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_CHIP_PACKAGE_4BIT(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_CHIP_PACKAGE_4BIT() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_DIS_CACHE(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_DIS_CACHE() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_SPI_PAD_CONFIG_HD(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0x1f0)|value<<4) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_SPI_PAD_CONFIG_HD() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0x1f0) >> 4 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_CHIP_PACKAGE(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0xe00)|value<<9) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_CHIP_PACKAGE() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0xe00) >> 9 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_CHIP_CPU_FREQ_LOW(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_CHIP_CPU_FREQ_LOW() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_CHIP_CPU_FREQ_RATED(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_CHIP_CPU_FREQ_RATED() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_BLK3_PART_RESERVE(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_BLK3_PART_RESERVE() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_CHIP_VER_REV1(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_CHIP_VER_REV1() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetBLK0_RDATA3_RD_RESERVE_0_112(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA3.Reg, volatile.LoadUint32(&o.BLK0_RDATA3.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetBLK0_RDATA3_RD_RESERVE_0_112() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA3.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.BLK0_RDATA4 +func (o *EFUSE_Type) SetBLK0_RDATA4_RD_CLK8M_FREQ(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA4.Reg, volatile.LoadUint32(&o.BLK0_RDATA4.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetBLK0_RDATA4_RD_CLK8M_FREQ() uint32 { + return volatile.LoadUint32(&o.BLK0_RDATA4.Reg) & 0xff +} +func (o *EFUSE_Type) SetBLK0_RDATA4_RD_ADC_VREF(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA4.Reg, volatile.LoadUint32(&o.BLK0_RDATA4.Reg)&^(0x1f00)|value<<8) +} +func (o *EFUSE_Type) GetBLK0_RDATA4_RD_ADC_VREF() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA4.Reg) & 0x1f00) >> 8 +} +func (o *EFUSE_Type) SetBLK0_RDATA4_RD_RESERVE_0_141(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA4.Reg, volatile.LoadUint32(&o.BLK0_RDATA4.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetBLK0_RDATA4_RD_RESERVE_0_141() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA4.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetBLK0_RDATA4_RD_XPD_SDIO(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA4.Reg, volatile.LoadUint32(&o.BLK0_RDATA4.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetBLK0_RDATA4_RD_XPD_SDIO() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA4.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetBLK0_RDATA4_RD_XPD_SDIO_TIEH(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA4.Reg, volatile.LoadUint32(&o.BLK0_RDATA4.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetBLK0_RDATA4_RD_XPD_SDIO_TIEH() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA4.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetBLK0_RDATA4_RD_XPD_SDIO_FORCE(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA4.Reg, volatile.LoadUint32(&o.BLK0_RDATA4.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetBLK0_RDATA4_RD_XPD_SDIO_FORCE() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA4.Reg) & 0x10000) >> 16 +} +func (o *EFUSE_Type) SetBLK0_RDATA4_RD_RESERVE_0_145(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA4.Reg, volatile.LoadUint32(&o.BLK0_RDATA4.Reg)&^(0xfffe0000)|value<<17) +} +func (o *EFUSE_Type) GetBLK0_RDATA4_RD_RESERVE_0_145() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA4.Reg) & 0xfffe0000) >> 17 +} + +// EFUSE.BLK0_RDATA5 +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_SPI_PAD_CONFIG_CLK(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0x1f)|value) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_SPI_PAD_CONFIG_CLK() uint32 { + return volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0x1f +} +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_SPI_PAD_CONFIG_Q(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0x3e0)|value<<5) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_SPI_PAD_CONFIG_Q() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0x3e0) >> 5 +} +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_SPI_PAD_CONFIG_D(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0x7c00)|value<<10) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_SPI_PAD_CONFIG_D() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0x7c00) >> 10 +} +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_SPI_PAD_CONFIG_CS0(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0xf8000)|value<<15) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_SPI_PAD_CONFIG_CS0() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0xf8000) >> 15 +} +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_CHIP_VER_REV2(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_CHIP_VER_REV2() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_RESERVE_0_181(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_RESERVE_0_181() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_VOL_LEVEL_HP_INV(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0xc00000)|value<<22) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_VOL_LEVEL_HP_INV() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0xc00000) >> 22 +} +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_WAFER_VERSION_MINOR(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0x3000000)|value<<24) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_WAFER_VERSION_MINOR() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0x3000000) >> 24 +} +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_RESERVE_0_186(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0xc000000)|value<<26) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_RESERVE_0_186() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0xc000000) >> 26 +} +func (o *EFUSE_Type) SetBLK0_RDATA5_RD_FLASH_CRYPT_CONFIG(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA5.Reg, volatile.LoadUint32(&o.BLK0_RDATA5.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetBLK0_RDATA5_RD_FLASH_CRYPT_CONFIG() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA5.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.BLK0_RDATA6 +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_CODING_SCHEME(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_CODING_SCHEME() uint32 { + return volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x3 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_CONSOLE_DEBUG_DISABLE(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_CONSOLE_DEBUG_DISABLE() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_DISABLE_SDIO_HOST(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_DISABLE_SDIO_HOST() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_ABS_DONE_0(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_ABS_DONE_0() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_ABS_DONE_1(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_ABS_DONE_1() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_JTAG_DISABLE(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_JTAG_DISABLE() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_DISABLE_DL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_DISABLE_DL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_DISABLE_DL_DECRYPT(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_DISABLE_DL_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_DISABLE_DL_CACHE(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_DISABLE_DL_CACHE() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_KEY_STATUS(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_KEY_STATUS() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetBLK0_RDATA6_RD_RESERVE_0_203(value uint32) { + volatile.StoreUint32(&o.BLK0_RDATA6.Reg, volatile.LoadUint32(&o.BLK0_RDATA6.Reg)&^(0xfffff800)|value<<11) +} +func (o *EFUSE_Type) GetBLK0_RDATA6_RD_RESERVE_0_203() uint32 { + return (volatile.LoadUint32(&o.BLK0_RDATA6.Reg) & 0xfffff800) >> 11 +} + +// EFUSE.BLK0_WDATA0 +func (o *EFUSE_Type) SetBLK0_WDATA0_WR_DIS(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA0.Reg, volatile.LoadUint32(&o.BLK0_WDATA0.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetBLK0_WDATA0_WR_DIS() uint32 { + return volatile.LoadUint32(&o.BLK0_WDATA0.Reg) & 0xffff +} +func (o *EFUSE_Type) SetBLK0_WDATA0_RD_DIS(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA0.Reg, volatile.LoadUint32(&o.BLK0_WDATA0.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetBLK0_WDATA0_RD_DIS() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA0.Reg) & 0xf0000) >> 16 +} +func (o *EFUSE_Type) SetBLK0_WDATA0_FLASH_CRYPT_CNT(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA0.Reg, volatile.LoadUint32(&o.BLK0_WDATA0.Reg)&^(0x7f00000)|value<<20) +} +func (o *EFUSE_Type) GetBLK0_WDATA0_FLASH_CRYPT_CNT() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA0.Reg) & 0x7f00000) >> 20 +} + +// EFUSE.BLK0_WDATA1 +func (o *EFUSE_Type) SetBLK0_WDATA1(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA1.Reg, value) +} +func (o *EFUSE_Type) GetBLK0_WDATA1() uint32 { + return volatile.LoadUint32(&o.BLK0_WDATA1.Reg) +} + +// EFUSE.BLK0_WDATA2 +func (o *EFUSE_Type) SetBLK0_WDATA2_WIFI_MAC_CRC_HIGH(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA2.Reg, volatile.LoadUint32(&o.BLK0_WDATA2.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetBLK0_WDATA2_WIFI_MAC_CRC_HIGH() uint32 { + return volatile.LoadUint32(&o.BLK0_WDATA2.Reg) & 0xffffff +} + +// EFUSE.BLK0_WDATA3 +func (o *EFUSE_Type) SetBLK0_WDATA3_DISABLE_APP_CPU(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_DISABLE_APP_CPU() uint32 { + return volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_DISABLE_BT(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_DISABLE_BT() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_CHIP_PACKAGE_4BIT(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_CHIP_PACKAGE_4BIT() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_DIS_CACHE(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_DIS_CACHE() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_SPI_PAD_CONFIG_HD(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0x1f0)|value<<4) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_SPI_PAD_CONFIG_HD() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0x1f0) >> 4 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_CHIP_PACKAGE(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0xe00)|value<<9) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_CHIP_PACKAGE() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0xe00) >> 9 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_CHIP_CPU_FREQ_LOW(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_CHIP_CPU_FREQ_LOW() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_CHIP_CPU_FREQ_RATED(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_CHIP_CPU_FREQ_RATED() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_BLK3_PART_RESERVE(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_BLK3_PART_RESERVE() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_CHIP_VER_REV1(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_CHIP_VER_REV1() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetBLK0_WDATA3_RESERVE_0_112(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA3.Reg, volatile.LoadUint32(&o.BLK0_WDATA3.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetBLK0_WDATA3_RESERVE_0_112() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA3.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.BLK0_WDATA4 +func (o *EFUSE_Type) SetBLK0_WDATA4_CLK8M_FREQ(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA4.Reg, volatile.LoadUint32(&o.BLK0_WDATA4.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetBLK0_WDATA4_CLK8M_FREQ() uint32 { + return volatile.LoadUint32(&o.BLK0_WDATA4.Reg) & 0xff +} +func (o *EFUSE_Type) SetBLK0_WDATA4_ADC_VREF(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA4.Reg, volatile.LoadUint32(&o.BLK0_WDATA4.Reg)&^(0x1f00)|value<<8) +} +func (o *EFUSE_Type) GetBLK0_WDATA4_ADC_VREF() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA4.Reg) & 0x1f00) >> 8 +} +func (o *EFUSE_Type) SetBLK0_WDATA4_RESERVE_0_141(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA4.Reg, volatile.LoadUint32(&o.BLK0_WDATA4.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetBLK0_WDATA4_RESERVE_0_141() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA4.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetBLK0_WDATA4_XPD_SDIO(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA4.Reg, volatile.LoadUint32(&o.BLK0_WDATA4.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetBLK0_WDATA4_XPD_SDIO() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA4.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetBLK0_WDATA4_XPD_SDIO_TIEH(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA4.Reg, volatile.LoadUint32(&o.BLK0_WDATA4.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetBLK0_WDATA4_XPD_SDIO_TIEH() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA4.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetBLK0_WDATA4_XPD_SDIO_FORCE(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA4.Reg, volatile.LoadUint32(&o.BLK0_WDATA4.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetBLK0_WDATA4_XPD_SDIO_FORCE() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA4.Reg) & 0x10000) >> 16 +} +func (o *EFUSE_Type) SetBLK0_WDATA4_RESERVE_0_145(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA4.Reg, volatile.LoadUint32(&o.BLK0_WDATA4.Reg)&^(0xfffe0000)|value<<17) +} +func (o *EFUSE_Type) GetBLK0_WDATA4_RESERVE_0_145() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA4.Reg) & 0xfffe0000) >> 17 +} + +// EFUSE.BLK0_WDATA5 +func (o *EFUSE_Type) SetBLK0_WDATA5_SPI_PAD_CONFIG_CLK(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0x1f)|value) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_SPI_PAD_CONFIG_CLK() uint32 { + return volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0x1f +} +func (o *EFUSE_Type) SetBLK0_WDATA5_SPI_PAD_CONFIG_Q(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0x3e0)|value<<5) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_SPI_PAD_CONFIG_Q() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0x3e0) >> 5 +} +func (o *EFUSE_Type) SetBLK0_WDATA5_SPI_PAD_CONFIG_D(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0x7c00)|value<<10) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_SPI_PAD_CONFIG_D() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0x7c00) >> 10 +} +func (o *EFUSE_Type) SetBLK0_WDATA5_SPI_PAD_CONFIG_CS0(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0xf8000)|value<<15) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_SPI_PAD_CONFIG_CS0() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0xf8000) >> 15 +} +func (o *EFUSE_Type) SetBLK0_WDATA5_CHIP_VER_REV2(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_CHIP_VER_REV2() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetBLK0_WDATA5_RESERVE_0_181(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_RESERVE_0_181() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetBLK0_WDATA5_VOL_LEVEL_HP_INV(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0xc00000)|value<<22) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_VOL_LEVEL_HP_INV() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0xc00000) >> 22 +} +func (o *EFUSE_Type) SetBLK0_WDATA5_WAFER_VERSION_MINOR(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0x3000000)|value<<24) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_WAFER_VERSION_MINOR() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0x3000000) >> 24 +} +func (o *EFUSE_Type) SetBLK0_WDATA5_RESERVE_0_186(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0xc000000)|value<<26) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_RESERVE_0_186() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0xc000000) >> 26 +} +func (o *EFUSE_Type) SetBLK0_WDATA5_FLASH_CRYPT_CONFIG(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA5.Reg, volatile.LoadUint32(&o.BLK0_WDATA5.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetBLK0_WDATA5_FLASH_CRYPT_CONFIG() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA5.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.BLK0_WDATA6 +func (o *EFUSE_Type) SetBLK0_WDATA6_CODING_SCHEME(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_CODING_SCHEME() uint32 { + return volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x3 +} +func (o *EFUSE_Type) SetBLK0_WDATA6_CONSOLE_DEBUG_DISABLE(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_CONSOLE_DEBUG_DISABLE() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetBLK0_WDATA6_DISABLE_SDIO_HOST(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_DISABLE_SDIO_HOST() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetBLK0_WDATA6_ABS_DONE_0(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_ABS_DONE_0() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetBLK0_WDATA6_ABS_DONE_1(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_ABS_DONE_1() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetBLK0_WDATA6_DISABLE_JTAG(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_DISABLE_JTAG() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetBLK0_WDATA6_DISABLE_DL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_DISABLE_DL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetBLK0_WDATA6_DISABLE_DL_DECRYPT(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_DISABLE_DL_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetBLK0_WDATA6_DISABLE_DL_CACHE(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_DISABLE_DL_CACHE() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetBLK0_WDATA6_KEY_STATUS(value uint32) { + volatile.StoreUint32(&o.BLK0_WDATA6.Reg, volatile.LoadUint32(&o.BLK0_WDATA6.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetBLK0_WDATA6_KEY_STATUS() uint32 { + return (volatile.LoadUint32(&o.BLK0_WDATA6.Reg) & 0x400) >> 10 +} + +// EFUSE.BLK1_RDATA0 +func (o *EFUSE_Type) SetBLK1_RDATA0(value uint32) { + volatile.StoreUint32(&o.BLK1_RDATA0.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_RDATA0() uint32 { + return volatile.LoadUint32(&o.BLK1_RDATA0.Reg) +} + +// EFUSE.BLK1_RDATA1 +func (o *EFUSE_Type) SetBLK1_RDATA1(value uint32) { + volatile.StoreUint32(&o.BLK1_RDATA1.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_RDATA1() uint32 { + return volatile.LoadUint32(&o.BLK1_RDATA1.Reg) +} + +// EFUSE.BLK1_RDATA2 +func (o *EFUSE_Type) SetBLK1_RDATA2(value uint32) { + volatile.StoreUint32(&o.BLK1_RDATA2.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_RDATA2() uint32 { + return volatile.LoadUint32(&o.BLK1_RDATA2.Reg) +} + +// EFUSE.BLK1_RDATA3 +func (o *EFUSE_Type) SetBLK1_RDATA3(value uint32) { + volatile.StoreUint32(&o.BLK1_RDATA3.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_RDATA3() uint32 { + return volatile.LoadUint32(&o.BLK1_RDATA3.Reg) +} + +// EFUSE.BLK1_RDATA4 +func (o *EFUSE_Type) SetBLK1_RDATA4(value uint32) { + volatile.StoreUint32(&o.BLK1_RDATA4.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_RDATA4() uint32 { + return volatile.LoadUint32(&o.BLK1_RDATA4.Reg) +} + +// EFUSE.BLK1_RDATA5 +func (o *EFUSE_Type) SetBLK1_RDATA5(value uint32) { + volatile.StoreUint32(&o.BLK1_RDATA5.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_RDATA5() uint32 { + return volatile.LoadUint32(&o.BLK1_RDATA5.Reg) +} + +// EFUSE.BLK1_RDATA6 +func (o *EFUSE_Type) SetBLK1_RDATA6(value uint32) { + volatile.StoreUint32(&o.BLK1_RDATA6.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_RDATA6() uint32 { + return volatile.LoadUint32(&o.BLK1_RDATA6.Reg) +} + +// EFUSE.BLK1_RDATA7 +func (o *EFUSE_Type) SetBLK1_RDATA7(value uint32) { + volatile.StoreUint32(&o.BLK1_RDATA7.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_RDATA7() uint32 { + return volatile.LoadUint32(&o.BLK1_RDATA7.Reg) +} + +// EFUSE.BLK2_RDATA0 +func (o *EFUSE_Type) SetBLK2_RDATA0(value uint32) { + volatile.StoreUint32(&o.BLK2_RDATA0.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_RDATA0() uint32 { + return volatile.LoadUint32(&o.BLK2_RDATA0.Reg) +} + +// EFUSE.BLK2_RDATA1 +func (o *EFUSE_Type) SetBLK2_RDATA1(value uint32) { + volatile.StoreUint32(&o.BLK2_RDATA1.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_RDATA1() uint32 { + return volatile.LoadUint32(&o.BLK2_RDATA1.Reg) +} + +// EFUSE.BLK2_RDATA2 +func (o *EFUSE_Type) SetBLK2_RDATA2(value uint32) { + volatile.StoreUint32(&o.BLK2_RDATA2.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_RDATA2() uint32 { + return volatile.LoadUint32(&o.BLK2_RDATA2.Reg) +} + +// EFUSE.BLK2_RDATA3 +func (o *EFUSE_Type) SetBLK2_RDATA3(value uint32) { + volatile.StoreUint32(&o.BLK2_RDATA3.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_RDATA3() uint32 { + return volatile.LoadUint32(&o.BLK2_RDATA3.Reg) +} + +// EFUSE.BLK2_RDATA4 +func (o *EFUSE_Type) SetBLK2_RDATA4(value uint32) { + volatile.StoreUint32(&o.BLK2_RDATA4.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_RDATA4() uint32 { + return volatile.LoadUint32(&o.BLK2_RDATA4.Reg) +} + +// EFUSE.BLK2_RDATA5 +func (o *EFUSE_Type) SetBLK2_RDATA5(value uint32) { + volatile.StoreUint32(&o.BLK2_RDATA5.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_RDATA5() uint32 { + return volatile.LoadUint32(&o.BLK2_RDATA5.Reg) +} + +// EFUSE.BLK2_RDATA6 +func (o *EFUSE_Type) SetBLK2_RDATA6(value uint32) { + volatile.StoreUint32(&o.BLK2_RDATA6.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_RDATA6() uint32 { + return volatile.LoadUint32(&o.BLK2_RDATA6.Reg) +} + +// EFUSE.BLK2_RDATA7 +func (o *EFUSE_Type) SetBLK2_RDATA7(value uint32) { + volatile.StoreUint32(&o.BLK2_RDATA7.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_RDATA7() uint32 { + return volatile.LoadUint32(&o.BLK2_RDATA7.Reg) +} + +// EFUSE.BLK3_RDATA0 +func (o *EFUSE_Type) SetBLK3_RDATA0_RD_CUSTOM_MAC_CRC(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA0.Reg, volatile.LoadUint32(&o.BLK3_RDATA0.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetBLK3_RDATA0_RD_CUSTOM_MAC_CRC() uint32 { + return volatile.LoadUint32(&o.BLK3_RDATA0.Reg) & 0xff +} +func (o *EFUSE_Type) SetBLK3_RDATA0_RD_CUSTOM_MAC(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA0.Reg, volatile.LoadUint32(&o.BLK3_RDATA0.Reg)&^(0xffffff00)|value<<8) +} +func (o *EFUSE_Type) GetBLK3_RDATA0_RD_CUSTOM_MAC() uint32 { + return (volatile.LoadUint32(&o.BLK3_RDATA0.Reg) & 0xffffff00) >> 8 +} + +// EFUSE.BLK3_RDATA1 +func (o *EFUSE_Type) SetBLK3_RDATA1_RD_CUSTOM_MAC_1(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA1.Reg, volatile.LoadUint32(&o.BLK3_RDATA1.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetBLK3_RDATA1_RD_CUSTOM_MAC_1() uint32 { + return volatile.LoadUint32(&o.BLK3_RDATA1.Reg) & 0xffffff +} +func (o *EFUSE_Type) SetBLK3_RDATA1_RESERVED_3_56(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA1.Reg, volatile.LoadUint32(&o.BLK3_RDATA1.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetBLK3_RDATA1_RESERVED_3_56() uint32 { + return (volatile.LoadUint32(&o.BLK3_RDATA1.Reg) & 0xff000000) >> 24 +} + +// EFUSE.BLK3_RDATA2 +func (o *EFUSE_Type) SetBLK3_RDATA2(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA2.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_RDATA2() uint32 { + return volatile.LoadUint32(&o.BLK3_RDATA2.Reg) +} + +// EFUSE.BLK3_RDATA3 +func (o *EFUSE_Type) SetBLK3_RDATA3_RD_ADC1_TP_LOW(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA3.Reg, volatile.LoadUint32(&o.BLK3_RDATA3.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetBLK3_RDATA3_RD_ADC1_TP_LOW() uint32 { + return volatile.LoadUint32(&o.BLK3_RDATA3.Reg) & 0x7f +} +func (o *EFUSE_Type) SetBLK3_RDATA3_RD_ADC1_TP_HIGH(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA3.Reg, volatile.LoadUint32(&o.BLK3_RDATA3.Reg)&^(0xff80)|value<<7) +} +func (o *EFUSE_Type) GetBLK3_RDATA3_RD_ADC1_TP_HIGH() uint32 { + return (volatile.LoadUint32(&o.BLK3_RDATA3.Reg) & 0xff80) >> 7 +} +func (o *EFUSE_Type) SetBLK3_RDATA3_RD_ADC2_TP_LOW(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA3.Reg, volatile.LoadUint32(&o.BLK3_RDATA3.Reg)&^(0x7f0000)|value<<16) +} +func (o *EFUSE_Type) GetBLK3_RDATA3_RD_ADC2_TP_LOW() uint32 { + return (volatile.LoadUint32(&o.BLK3_RDATA3.Reg) & 0x7f0000) >> 16 +} +func (o *EFUSE_Type) SetBLK3_RDATA3_RD_ADC2_TP_HIGH(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA3.Reg, volatile.LoadUint32(&o.BLK3_RDATA3.Reg)&^(0xff800000)|value<<23) +} +func (o *EFUSE_Type) GetBLK3_RDATA3_RD_ADC2_TP_HIGH() uint32 { + return (volatile.LoadUint32(&o.BLK3_RDATA3.Reg) & 0xff800000) >> 23 +} + +// EFUSE.BLK3_RDATA4 +func (o *EFUSE_Type) SetBLK3_RDATA4(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA4.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_RDATA4() uint32 { + return volatile.LoadUint32(&o.BLK3_RDATA4.Reg) +} + +// EFUSE.BLK3_RDATA5 +func (o *EFUSE_Type) SetBLK3_RDATA5_RESERVED_3_160(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA5.Reg, volatile.LoadUint32(&o.BLK3_RDATA5.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetBLK3_RDATA5_RESERVED_3_160() uint32 { + return volatile.LoadUint32(&o.BLK3_RDATA5.Reg) & 0xffffff +} +func (o *EFUSE_Type) SetBLK3_RDATA5_RD_MAC_VERSION(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA5.Reg, volatile.LoadUint32(&o.BLK3_RDATA5.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetBLK3_RDATA5_RD_MAC_VERSION() uint32 { + return (volatile.LoadUint32(&o.BLK3_RDATA5.Reg) & 0xff000000) >> 24 +} + +// EFUSE.BLK3_RDATA6 +func (o *EFUSE_Type) SetBLK3_RDATA6(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA6.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_RDATA6() uint32 { + return volatile.LoadUint32(&o.BLK3_RDATA6.Reg) +} + +// EFUSE.BLK3_RDATA7 +func (o *EFUSE_Type) SetBLK3_RDATA7(value uint32) { + volatile.StoreUint32(&o.BLK3_RDATA7.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_RDATA7() uint32 { + return volatile.LoadUint32(&o.BLK3_RDATA7.Reg) +} + +// EFUSE.BLK1_WDATA0 +func (o *EFUSE_Type) SetBLK1_WDATA0(value uint32) { + volatile.StoreUint32(&o.BLK1_WDATA0.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_WDATA0() uint32 { + return volatile.LoadUint32(&o.BLK1_WDATA0.Reg) +} + +// EFUSE.BLK1_WDATA1 +func (o *EFUSE_Type) SetBLK1_WDATA1(value uint32) { + volatile.StoreUint32(&o.BLK1_WDATA1.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_WDATA1() uint32 { + return volatile.LoadUint32(&o.BLK1_WDATA1.Reg) +} + +// EFUSE.BLK1_WDATA2 +func (o *EFUSE_Type) SetBLK1_WDATA2(value uint32) { + volatile.StoreUint32(&o.BLK1_WDATA2.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_WDATA2() uint32 { + return volatile.LoadUint32(&o.BLK1_WDATA2.Reg) +} + +// EFUSE.BLK1_WDATA3 +func (o *EFUSE_Type) SetBLK1_WDATA3(value uint32) { + volatile.StoreUint32(&o.BLK1_WDATA3.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_WDATA3() uint32 { + return volatile.LoadUint32(&o.BLK1_WDATA3.Reg) +} + +// EFUSE.BLK1_WDATA4 +func (o *EFUSE_Type) SetBLK1_WDATA4(value uint32) { + volatile.StoreUint32(&o.BLK1_WDATA4.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_WDATA4() uint32 { + return volatile.LoadUint32(&o.BLK1_WDATA4.Reg) +} + +// EFUSE.BLK1_WDATA5 +func (o *EFUSE_Type) SetBLK1_WDATA5(value uint32) { + volatile.StoreUint32(&o.BLK1_WDATA5.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_WDATA5() uint32 { + return volatile.LoadUint32(&o.BLK1_WDATA5.Reg) +} + +// EFUSE.BLK1_WDATA6 +func (o *EFUSE_Type) SetBLK1_WDATA6(value uint32) { + volatile.StoreUint32(&o.BLK1_WDATA6.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_WDATA6() uint32 { + return volatile.LoadUint32(&o.BLK1_WDATA6.Reg) +} + +// EFUSE.BLK1_WDATA7 +func (o *EFUSE_Type) SetBLK1_WDATA7(value uint32) { + volatile.StoreUint32(&o.BLK1_WDATA7.Reg, value) +} +func (o *EFUSE_Type) GetBLK1_WDATA7() uint32 { + return volatile.LoadUint32(&o.BLK1_WDATA7.Reg) +} + +// EFUSE.BLK2_WDATA0 +func (o *EFUSE_Type) SetBLK2_WDATA0(value uint32) { + volatile.StoreUint32(&o.BLK2_WDATA0.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_WDATA0() uint32 { + return volatile.LoadUint32(&o.BLK2_WDATA0.Reg) +} + +// EFUSE.BLK2_WDATA1 +func (o *EFUSE_Type) SetBLK2_WDATA1(value uint32) { + volatile.StoreUint32(&o.BLK2_WDATA1.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_WDATA1() uint32 { + return volatile.LoadUint32(&o.BLK2_WDATA1.Reg) +} + +// EFUSE.BLK2_WDATA2 +func (o *EFUSE_Type) SetBLK2_WDATA2(value uint32) { + volatile.StoreUint32(&o.BLK2_WDATA2.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_WDATA2() uint32 { + return volatile.LoadUint32(&o.BLK2_WDATA2.Reg) +} + +// EFUSE.BLK2_WDATA3 +func (o *EFUSE_Type) SetBLK2_WDATA3(value uint32) { + volatile.StoreUint32(&o.BLK2_WDATA3.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_WDATA3() uint32 { + return volatile.LoadUint32(&o.BLK2_WDATA3.Reg) +} + +// EFUSE.BLK2_WDATA4 +func (o *EFUSE_Type) SetBLK2_WDATA4(value uint32) { + volatile.StoreUint32(&o.BLK2_WDATA4.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_WDATA4() uint32 { + return volatile.LoadUint32(&o.BLK2_WDATA4.Reg) +} + +// EFUSE.BLK2_WDATA5 +func (o *EFUSE_Type) SetBLK2_WDATA5(value uint32) { + volatile.StoreUint32(&o.BLK2_WDATA5.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_WDATA5() uint32 { + return volatile.LoadUint32(&o.BLK2_WDATA5.Reg) +} + +// EFUSE.BLK2_WDATA6 +func (o *EFUSE_Type) SetBLK2_WDATA6(value uint32) { + volatile.StoreUint32(&o.BLK2_WDATA6.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_WDATA6() uint32 { + return volatile.LoadUint32(&o.BLK2_WDATA6.Reg) +} + +// EFUSE.BLK2_WDATA7 +func (o *EFUSE_Type) SetBLK2_WDATA7(value uint32) { + volatile.StoreUint32(&o.BLK2_WDATA7.Reg, value) +} +func (o *EFUSE_Type) GetBLK2_WDATA7() uint32 { + return volatile.LoadUint32(&o.BLK2_WDATA7.Reg) +} + +// EFUSE.BLK3_WDATA0 +func (o *EFUSE_Type) SetBLK3_WDATA0(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA0.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_WDATA0() uint32 { + return volatile.LoadUint32(&o.BLK3_WDATA0.Reg) +} + +// EFUSE.BLK3_WDATA1 +func (o *EFUSE_Type) SetBLK3_WDATA1(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA1.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_WDATA1() uint32 { + return volatile.LoadUint32(&o.BLK3_WDATA1.Reg) +} + +// EFUSE.BLK3_WDATA2 +func (o *EFUSE_Type) SetBLK3_WDATA2(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA2.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_WDATA2() uint32 { + return volatile.LoadUint32(&o.BLK3_WDATA2.Reg) +} + +// EFUSE.BLK3_WDATA3 +func (o *EFUSE_Type) SetBLK3_WDATA3_ADC1_TP_LOW(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA3.Reg, volatile.LoadUint32(&o.BLK3_WDATA3.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetBLK3_WDATA3_ADC1_TP_LOW() uint32 { + return volatile.LoadUint32(&o.BLK3_WDATA3.Reg) & 0x7f +} +func (o *EFUSE_Type) SetBLK3_WDATA3_ADC1_TP_HIGH(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA3.Reg, volatile.LoadUint32(&o.BLK3_WDATA3.Reg)&^(0xff80)|value<<7) +} +func (o *EFUSE_Type) GetBLK3_WDATA3_ADC1_TP_HIGH() uint32 { + return (volatile.LoadUint32(&o.BLK3_WDATA3.Reg) & 0xff80) >> 7 +} +func (o *EFUSE_Type) SetBLK3_WDATA3_ADC2_TP_LOW(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA3.Reg, volatile.LoadUint32(&o.BLK3_WDATA3.Reg)&^(0x7f0000)|value<<16) +} +func (o *EFUSE_Type) GetBLK3_WDATA3_ADC2_TP_LOW() uint32 { + return (volatile.LoadUint32(&o.BLK3_WDATA3.Reg) & 0x7f0000) >> 16 +} +func (o *EFUSE_Type) SetBLK3_WDATA3_ADC2_TP_HIGH(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA3.Reg, volatile.LoadUint32(&o.BLK3_WDATA3.Reg)&^(0xff800000)|value<<23) +} +func (o *EFUSE_Type) GetBLK3_WDATA3_ADC2_TP_HIGH() uint32 { + return (volatile.LoadUint32(&o.BLK3_WDATA3.Reg) & 0xff800000) >> 23 +} + +// EFUSE.BLK3_WDATA4 +func (o *EFUSE_Type) SetBLK3_WDATA4(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA4.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_WDATA4() uint32 { + return volatile.LoadUint32(&o.BLK3_WDATA4.Reg) +} + +// EFUSE.BLK3_WDATA5 +func (o *EFUSE_Type) SetBLK3_WDATA5(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA5.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_WDATA5() uint32 { + return volatile.LoadUint32(&o.BLK3_WDATA5.Reg) +} + +// EFUSE.BLK3_WDATA6 +func (o *EFUSE_Type) SetBLK3_WDATA6(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA6.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_WDATA6() uint32 { + return volatile.LoadUint32(&o.BLK3_WDATA6.Reg) +} + +// EFUSE.BLK3_WDATA7 +func (o *EFUSE_Type) SetBLK3_WDATA7(value uint32) { + volatile.StoreUint32(&o.BLK3_WDATA7.Reg, value) +} +func (o *EFUSE_Type) GetBLK3_WDATA7() uint32 { + return volatile.LoadUint32(&o.BLK3_WDATA7.Reg) +} + +// EFUSE.CLK +func (o *EFUSE_Type) SetCLK_SEL0(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetCLK_SEL0() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0xff +} +func (o *EFUSE_Type) SetCLK_SEL1(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0xff00)|value<<8) +} +func (o *EFUSE_Type) GetCLK_SEL1() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0xff00) >> 8 +} +func (o *EFUSE_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x10000) >> 16 +} + +// EFUSE.CONF +func (o *EFUSE_Type) SetCONF_OP_CODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetCONF_OP_CODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0xffff +} +func (o *EFUSE_Type) SetCONF_FORCE_NO_WR_RD_DIS(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetCONF_FORCE_NO_WR_RD_DIS() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000) >> 16 +} + +// EFUSE.STATUS +func (o *EFUSE_Type) SetSTATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, value) +} +func (o *EFUSE_Type) GetSTATUS() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) +} + +// EFUSE.CMD +func (o *EFUSE_Type) SetCMD_READ_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCMD_READ_CMD() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCMD_PGM_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCMD_PGM_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_RAW +func (o *EFUSE_Type) SetINT_RAW_READ_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_RAW_READ_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_RAW_PGM_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_RAW_PGM_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ST +func (o *EFUSE_Type) SetINT_ST_READ_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ST_READ_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ST_PGM_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ST_PGM_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ENA +func (o *EFUSE_Type) SetINT_ENA_READ_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ENA_READ_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ENA_PGM_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ENA_PGM_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_CLR +func (o *EFUSE_Type) SetINT_CLR_READ_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_CLR_READ_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_CLR_PGM_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_CLR_PGM_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// EFUSE.DAC_CONF +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.DAC_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_PAD_SEL(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_PAD_SEL() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x100) >> 8 +} + +// EFUSE.DEC_STATUS +func (o *EFUSE_Type) SetDEC_STATUS_DEC_WARNINGS(value uint32) { + volatile.StoreUint32(&o.DEC_STATUS.Reg, volatile.LoadUint32(&o.DEC_STATUS.Reg)&^(0xfff)|value) +} +func (o *EFUSE_Type) GetDEC_STATUS_DEC_WARNINGS() uint32 { + return volatile.LoadUint32(&o.DEC_STATUS.Reg) & 0xfff +} + +// EFUSE.DATE +func (o *EFUSE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *EFUSE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Ethernet DMA configuration and control registers +type EMAC_DMA_Type struct { + DMABUSMODE volatile.Register32 // 0x0 + DMATXPOLLDEMAND volatile.Register32 // 0x4 + DMARXPOLLDEMAND volatile.Register32 // 0x8 + DMARXBASEADDR volatile.Register32 // 0xC + DMATXBASEADDR volatile.Register32 // 0x10 + DMASTATUS volatile.Register32 // 0x14 + DMAOPERATION_MODE volatile.Register32 // 0x18 + DMAIN_EN volatile.Register32 // 0x1C + DMAMISSEDFR volatile.Register32 // 0x20 + DMARINTWDTIMER volatile.Register32 // 0x24 + _ [32]byte + DMATXCURRDESC volatile.Register32 // 0x48 + DMARXCURRDESC volatile.Register32 // 0x4C + DMATXCURRADDR_BUF volatile.Register32 // 0x50 + DMARXCURRADDR_BUF volatile.Register32 // 0x54 +} + +// EMAC_DMA.DMABUSMODE: Bus mode configuration +func (o *EMAC_DMA_Type) SetDMABUSMODE_SW_RST(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x1)|value) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_SW_RST() uint32 { + return volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x1 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_DMA_ARB_SCH(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_DMA_ARB_SCH() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x2) >> 1 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_DESC_SKIP_LEN(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x7c)|value<<2) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_DESC_SKIP_LEN() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x7c) >> 2 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_ALT_DESC_SIZE(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x80)|value<<7) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_ALT_DESC_SIZE() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x80) >> 7 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_PROG_BURST_LEN(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x3f00)|value<<8) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_PROG_BURST_LEN() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x3f00) >> 8 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_PRI_RATIO(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0xc000)|value<<14) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_PRI_RATIO() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0xc000) >> 14 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_FIXED_BURST(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x10000)|value<<16) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_FIXED_BURST() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x10000) >> 16 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_RX_DMA_PBL(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x7e0000)|value<<17) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_RX_DMA_PBL() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x7e0000) >> 17 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_USE_SEP_PBL(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x800000)|value<<23) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_USE_SEP_PBL() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x800000) >> 23 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_PBLX8_MODE(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x1000000)|value<<24) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_PBLX8_MODE() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x1000000) >> 24 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_DMAADDRALIBEA(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x2000000)|value<<25) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_DMAADDRALIBEA() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x2000000) >> 25 +} +func (o *EMAC_DMA_Type) SetDMABUSMODE_DMAMIXEDBURST(value uint32) { + volatile.StoreUint32(&o.DMABUSMODE.Reg, volatile.LoadUint32(&o.DMABUSMODE.Reg)&^(0x4000000)|value<<26) +} +func (o *EMAC_DMA_Type) GetDMABUSMODE_DMAMIXEDBURST() uint32 { + return (volatile.LoadUint32(&o.DMABUSMODE.Reg) & 0x4000000) >> 26 +} + +// EMAC_DMA.DMASTATUS: State of interrupts, errors and other events +func (o *EMAC_DMA_Type) SetDMASTATUS_TRANS_INT(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x1)|value) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_TRANS_INT() uint32 { + return volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x1 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_TRANS_PROC_STOP(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_TRANS_PROC_STOP() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x2) >> 1 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_TRANS_BUF_UNAVAIL(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x4)|value<<2) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_TRANS_BUF_UNAVAIL() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x4) >> 2 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_TRANS_JABBER_TO(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x8)|value<<3) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_TRANS_JABBER_TO() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x8) >> 3 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_RECV_OVFLOW(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x10)|value<<4) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_RECV_OVFLOW() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x10) >> 4 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_TRANS_UNDFLOW(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x20)|value<<5) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_TRANS_UNDFLOW() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x20) >> 5 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_RECV_INT(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x40)|value<<6) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_RECV_INT() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x40) >> 6 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_RECV_BUF_UNAVAIL(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x80)|value<<7) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_RECV_BUF_UNAVAIL() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x80) >> 7 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_RECV_PROC_STOP(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x100)|value<<8) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_RECV_PROC_STOP() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x100) >> 8 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_RECV_WDT_TO(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x200)|value<<9) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_RECV_WDT_TO() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x200) >> 9 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_EARLY_TRANS_INT(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x400)|value<<10) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_EARLY_TRANS_INT() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x400) >> 10 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_FATAL_BUS_ERR_INT(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x2000)|value<<13) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_FATAL_BUS_ERR_INT() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x2000) >> 13 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_EARLY_RECV_INT(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x4000)|value<<14) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_EARLY_RECV_INT() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x4000) >> 14 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_ABN_INT_SUMM(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x8000)|value<<15) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_ABN_INT_SUMM() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x8000) >> 15 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_NORM_INT_SUMM(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x10000)|value<<16) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_NORM_INT_SUMM() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x10000) >> 16 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_RECV_PROC_STATE(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0xe0000)|value<<17) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_RECV_PROC_STATE() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0xe0000) >> 17 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_TRANS_PROC_STATE(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x700000)|value<<20) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_TRANS_PROC_STATE() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x700000) >> 20 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_ERROR_BITS(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x3800000)|value<<23) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_ERROR_BITS() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x3800000) >> 23 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_PMT_INT(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_PMT_INT() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x10000000) >> 28 +} +func (o *EMAC_DMA_Type) SetDMASTATUS_TS_TRI_INT(value uint32) { + volatile.StoreUint32(&o.DMASTATUS.Reg, volatile.LoadUint32(&o.DMASTATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *EMAC_DMA_Type) GetDMASTATUS_TS_TRI_INT() uint32 { + return (volatile.LoadUint32(&o.DMASTATUS.Reg) & 0x20000000) >> 29 +} + +// EMAC_DMA.DMAOPERATION_MODE: Receive and Transmit operating modes and command +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_START_STOP_RX(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_START_STOP_RX() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x2) >> 1 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_OPT_SECOND_FRAME(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x4)|value<<2) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_OPT_SECOND_FRAME() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x4) >> 2 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_RX_THRESH_CTRL(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x18)|value<<3) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_RX_THRESH_CTRL() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x18) >> 3 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_DROP_GFRM(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x20)|value<<5) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_DROP_GFRM() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x20) >> 5 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_FWD_UNDER_GF(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x40)|value<<6) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_FWD_UNDER_GF() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x40) >> 6 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_FWD_ERR_FRAME(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x80)|value<<7) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_FWD_ERR_FRAME() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x80) >> 7 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_START_STOP_TRANSMISSION_COMMAND(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x2000)|value<<13) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_START_STOP_TRANSMISSION_COMMAND() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x2000) >> 13 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_TX_THRESH_CTRL(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x1c000)|value<<14) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_TX_THRESH_CTRL() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x1c000) >> 14 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_FLUSH_TX_FIFO(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x100000)|value<<20) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_FLUSH_TX_FIFO() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x100000) >> 20 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_TX_STR_FWD(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x200000)|value<<21) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_TX_STR_FWD() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x200000) >> 21 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_DIS_FLUSH_RECV_FRAMES(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x1000000)|value<<24) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_DIS_FLUSH_RECV_FRAMES() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x1000000) >> 24 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_RX_STORE_FORWARD(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x2000000)|value<<25) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_RX_STORE_FORWARD() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x2000000) >> 25 +} +func (o *EMAC_DMA_Type) SetDMAOPERATION_MODE_DIS_DROP_TCPIP_ERR_FRAM(value uint32) { + volatile.StoreUint32(&o.DMAOPERATION_MODE.Reg, volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg)&^(0x4000000)|value<<26) +} +func (o *EMAC_DMA_Type) GetDMAOPERATION_MODE_DIS_DROP_TCPIP_ERR_FRAM() uint32 { + return (volatile.LoadUint32(&o.DMAOPERATION_MODE.Reg) & 0x4000000) >> 26 +} + +// EMAC_DMA.DMAIN_EN +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_TIE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x1)|value) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_TIE() uint32 { + return volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x1 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_TSE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_TSE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x2) >> 1 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_TBUE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x4)|value<<2) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_TBUE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x4) >> 2 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_TJTE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x8)|value<<3) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_TJTE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x8) >> 3 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_OIE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x10)|value<<4) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_OIE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x10) >> 4 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_UIE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x20)|value<<5) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_UIE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x20) >> 5 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_RIE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x40)|value<<6) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_RIE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x40) >> 6 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_RBUE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x80)|value<<7) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_RBUE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x80) >> 7 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_RSE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x100)|value<<8) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_RSE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x100) >> 8 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_RWTE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x200)|value<<9) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_RWTE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x200) >> 9 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_ETIE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x400)|value<<10) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_ETIE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x400) >> 10 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_FBEE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x2000)|value<<13) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_FBEE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x2000) >> 13 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_ERIE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x4000)|value<<14) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_ERIE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x4000) >> 14 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_AISE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x8000)|value<<15) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_AISE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x8000) >> 15 +} +func (o *EMAC_DMA_Type) SetDMAIN_EN_DMAIN_NISE(value uint32) { + volatile.StoreUint32(&o.DMAIN_EN.Reg, volatile.LoadUint32(&o.DMAIN_EN.Reg)&^(0x10000)|value<<16) +} +func (o *EMAC_DMA_Type) GetDMAIN_EN_DMAIN_NISE() uint32 { + return (volatile.LoadUint32(&o.DMAIN_EN.Reg) & 0x10000) >> 16 +} + +// EMAC_DMA.DMAMISSEDFR: Missed Frame and Buffer Overflow Counter Register +func (o *EMAC_DMA_Type) SetDMAMISSEDFR_MISSED_FC(value uint32) { + volatile.StoreUint32(&o.DMAMISSEDFR.Reg, volatile.LoadUint32(&o.DMAMISSEDFR.Reg)&^(0xffff)|value) +} +func (o *EMAC_DMA_Type) GetDMAMISSEDFR_MISSED_FC() uint32 { + return volatile.LoadUint32(&o.DMAMISSEDFR.Reg) & 0xffff +} +func (o *EMAC_DMA_Type) SetDMAMISSEDFR_OVERFLOW_BMFC(value uint32) { + volatile.StoreUint32(&o.DMAMISSEDFR.Reg, volatile.LoadUint32(&o.DMAMISSEDFR.Reg)&^(0x10000)|value<<16) +} +func (o *EMAC_DMA_Type) GetDMAMISSEDFR_OVERFLOW_BMFC() uint32 { + return (volatile.LoadUint32(&o.DMAMISSEDFR.Reg) & 0x10000) >> 16 +} +func (o *EMAC_DMA_Type) SetDMAMISSEDFR_OVERFLOW_FC(value uint32) { + volatile.StoreUint32(&o.DMAMISSEDFR.Reg, volatile.LoadUint32(&o.DMAMISSEDFR.Reg)&^(0xffe0000)|value<<17) +} +func (o *EMAC_DMA_Type) GetDMAMISSEDFR_OVERFLOW_FC() uint32 { + return (volatile.LoadUint32(&o.DMAMISSEDFR.Reg) & 0xffe0000) >> 17 +} +func (o *EMAC_DMA_Type) SetDMAMISSEDFR_OVERFLOW_BFOC(value uint32) { + volatile.StoreUint32(&o.DMAMISSEDFR.Reg, volatile.LoadUint32(&o.DMAMISSEDFR.Reg)&^(0x10000000)|value<<28) +} +func (o *EMAC_DMA_Type) GetDMAMISSEDFR_OVERFLOW_BFOC() uint32 { + return (volatile.LoadUint32(&o.DMAMISSEDFR.Reg) & 0x10000000) >> 28 +} + +// EMAC_DMA.DMARINTWDTIMER: Watchdog timer count on receive +func (o *EMAC_DMA_Type) SetDMARINTWDTIMER_RIWTC(value uint32) { + volatile.StoreUint32(&o.DMARINTWDTIMER.Reg, volatile.LoadUint32(&o.DMARINTWDTIMER.Reg)&^(0xff)|value) +} +func (o *EMAC_DMA_Type) GetDMARINTWDTIMER_RIWTC() uint32 { + return volatile.LoadUint32(&o.DMARINTWDTIMER.Reg) & 0xff +} + +// Ethernet Clock, PHY type, and SRAM configuration registers +type EMAC_EXT_Type struct { + EX_CLKOUT_CONF volatile.Register32 // 0x0 + EX_OSCCLK_CONF volatile.Register32 // 0x4 + EX_CLK_CTRL volatile.Register32 // 0x8 + EX_PHYINF_CONF volatile.Register32 // 0xC + PD_SEL volatile.Register32 // 0x10 + _ [232]byte + EX_DATE volatile.Register32 // 0xFC +} + +// EMAC_EXT.EX_CLKOUT_CONF: RMII clock divider setting +func (o *EMAC_EXT_Type) SetEX_CLKOUT_CONF_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.EX_CLKOUT_CONF.Reg, volatile.LoadUint32(&o.EX_CLKOUT_CONF.Reg)&^(0xf)|value) +} +func (o *EMAC_EXT_Type) GetEX_CLKOUT_CONF_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.EX_CLKOUT_CONF.Reg) & 0xf +} +func (o *EMAC_EXT_Type) SetEX_CLKOUT_CONF_H_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.EX_CLKOUT_CONF.Reg, volatile.LoadUint32(&o.EX_CLKOUT_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *EMAC_EXT_Type) GetEX_CLKOUT_CONF_H_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.EX_CLKOUT_CONF.Reg) & 0xf0) >> 4 +} +func (o *EMAC_EXT_Type) SetEX_CLKOUT_CONF_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.EX_CLKOUT_CONF.Reg, volatile.LoadUint32(&o.EX_CLKOUT_CONF.Reg)&^(0x300)|value<<8) +} +func (o *EMAC_EXT_Type) GetEX_CLKOUT_CONF_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.EX_CLKOUT_CONF.Reg) & 0x300) >> 8 +} + +// EMAC_EXT.EX_OSCCLK_CONF: RMII clock half and whole divider settings +func (o *EMAC_EXT_Type) SetEX_OSCCLK_CONF_DIV_NUM_10M(value uint32) { + volatile.StoreUint32(&o.EX_OSCCLK_CONF.Reg, volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *EMAC_EXT_Type) GetEX_OSCCLK_CONF_DIV_NUM_10M() uint32 { + return volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg) & 0x3f +} +func (o *EMAC_EXT_Type) SetEX_OSCCLK_CONF_H_DIV_NUM_10M(value uint32) { + volatile.StoreUint32(&o.EX_OSCCLK_CONF.Reg, volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *EMAC_EXT_Type) GetEX_OSCCLK_CONF_H_DIV_NUM_10M() uint32 { + return (volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *EMAC_EXT_Type) SetEX_OSCCLK_CONF_DIV_NUM_100M(value uint32) { + volatile.StoreUint32(&o.EX_OSCCLK_CONF.Reg, volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg)&^(0x3f000)|value<<12) +} +func (o *EMAC_EXT_Type) GetEX_OSCCLK_CONF_DIV_NUM_100M() uint32 { + return (volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg) & 0x3f000) >> 12 +} +func (o *EMAC_EXT_Type) SetEX_OSCCLK_CONF_H_DIV_NUM_100M(value uint32) { + volatile.StoreUint32(&o.EX_OSCCLK_CONF.Reg, volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg)&^(0xfc0000)|value<<18) +} +func (o *EMAC_EXT_Type) GetEX_OSCCLK_CONF_H_DIV_NUM_100M() uint32 { + return (volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg) & 0xfc0000) >> 18 +} +func (o *EMAC_EXT_Type) SetEX_OSCCLK_CONF_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.EX_OSCCLK_CONF.Reg, volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *EMAC_EXT_Type) GetEX_OSCCLK_CONF_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.EX_OSCCLK_CONF.Reg) & 0x1000000) >> 24 +} + +// EMAC_EXT.EX_CLK_CTRL: Clock enable and external/internal clock selection +func (o *EMAC_EXT_Type) SetEX_CLK_CTRL_EXT_EN(value uint32) { + volatile.StoreUint32(&o.EX_CLK_CTRL.Reg, volatile.LoadUint32(&o.EX_CLK_CTRL.Reg)&^(0x1)|value) +} +func (o *EMAC_EXT_Type) GetEX_CLK_CTRL_EXT_EN() uint32 { + return volatile.LoadUint32(&o.EX_CLK_CTRL.Reg) & 0x1 +} +func (o *EMAC_EXT_Type) SetEX_CLK_CTRL_INT_EN(value uint32) { + volatile.StoreUint32(&o.EX_CLK_CTRL.Reg, volatile.LoadUint32(&o.EX_CLK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_EXT_Type) GetEX_CLK_CTRL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.EX_CLK_CTRL.Reg) & 0x2) >> 1 +} +func (o *EMAC_EXT_Type) SetEX_CLK_CTRL_RX_125_CLK_EN(value uint32) { + volatile.StoreUint32(&o.EX_CLK_CTRL.Reg, volatile.LoadUint32(&o.EX_CLK_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EMAC_EXT_Type) GetEX_CLK_CTRL_RX_125_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.EX_CLK_CTRL.Reg) & 0x4) >> 2 +} +func (o *EMAC_EXT_Type) SetEX_CLK_CTRL_MII_CLK_TX_EN(value uint32) { + volatile.StoreUint32(&o.EX_CLK_CTRL.Reg, volatile.LoadUint32(&o.EX_CLK_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EMAC_EXT_Type) GetEX_CLK_CTRL_MII_CLK_TX_EN() uint32 { + return (volatile.LoadUint32(&o.EX_CLK_CTRL.Reg) & 0x8) >> 3 +} +func (o *EMAC_EXT_Type) SetEX_CLK_CTRL_MII_CLK_RX_EN(value uint32) { + volatile.StoreUint32(&o.EX_CLK_CTRL.Reg, volatile.LoadUint32(&o.EX_CLK_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EMAC_EXT_Type) GetEX_CLK_CTRL_MII_CLK_RX_EN() uint32 { + return (volatile.LoadUint32(&o.EX_CLK_CTRL.Reg) & 0x10) >> 4 +} +func (o *EMAC_EXT_Type) SetEX_CLK_CTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.EX_CLK_CTRL.Reg, volatile.LoadUint32(&o.EX_CLK_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EMAC_EXT_Type) GetEX_CLK_CTRL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.EX_CLK_CTRL.Reg) & 0x20) >> 5 +} + +// EMAC_EXT.EX_PHYINF_CONF: Selection of MII/RMII phy +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_INT_REVMII_RX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0x1)|value) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_INT_REVMII_RX_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0x1 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_EXT_REVMII_RX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_EXT_REVMII_RX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0x2) >> 1 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_SBD_FLOWCTRL(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0x4)|value<<2) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_SBD_FLOWCTRL() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0x4) >> 2 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_CORE_PHY_ADDR(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0xf8)|value<<3) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_CORE_PHY_ADDR() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0xf8) >> 3 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_REVMII_PHY_ADDR(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0x1f00)|value<<8) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_REVMII_PHY_ADDR() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0x1f00) >> 8 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_PHY_INTF_SEL(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0xe000)|value<<13) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_PHY_INTF_SEL() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0xe000) >> 13 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_SS_MODE(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_SS_MODE() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0x10000) >> 16 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_SBD_CLK_GATING_EN(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_SBD_CLK_GATING_EN() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0x20000) >> 17 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_PMT_CTRL_EN(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_PMT_CTRL_EN() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0x40000) >> 18 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_SCR_SMI_DLY_RX_SYNC(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_SCR_SMI_DLY_RX_SYNC() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0x80000) >> 19 +} +func (o *EMAC_EXT_Type) SetEX_PHYINF_CONF_TX_ERR_OUT_EN(value uint32) { + volatile.StoreUint32(&o.EX_PHYINF_CONF.Reg, volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *EMAC_EXT_Type) GetEX_PHYINF_CONF_TX_ERR_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.EX_PHYINF_CONF.Reg) & 0x100000) >> 20 +} + +// EMAC_EXT.PD_SEL: Ethernet RAM power-down enable +func (o *EMAC_EXT_Type) SetPD_SEL_RAM_PD_EN(value uint32) { + volatile.StoreUint32(&o.PD_SEL.Reg, volatile.LoadUint32(&o.PD_SEL.Reg)&^(0x3)|value) +} +func (o *EMAC_EXT_Type) GetPD_SEL_RAM_PD_EN() uint32 { + return volatile.LoadUint32(&o.PD_SEL.Reg) & 0x3 +} + +// Ethernet MAC configuration and control registers +type EMAC_MAC_Type struct { + EMACCONFIG volatile.Register32 // 0x0 + EMACFF volatile.Register32 // 0x4 + _ [8]byte + EMACGMIIADDR volatile.Register32 // 0x10 + EMACMIIDATA volatile.Register32 // 0x14 + EMACFC volatile.Register32 // 0x18 + _ [8]byte + EMACDEBUG volatile.Register32 // 0x24 + PMT_RWUFFR volatile.Register32 // 0x28 + PMT_CSR volatile.Register32 // 0x2C + EMACLPI_CRS volatile.Register32 // 0x30 + EMACLPITIMERSCONTROL volatile.Register32 // 0x34 + EMACINTS volatile.Register32 // 0x38 + EMACINTMASK volatile.Register32 // 0x3C + EMACADDR0HIGH volatile.Register32 // 0x40 + EMACADDR0LOW volatile.Register32 // 0x44 + EMACADDR1HIGH volatile.Register32 // 0x48 + EMACADDR1LOW volatile.Register32 // 0x4C + EMACADDR2HIGH volatile.Register32 // 0x50 + EMACADDR2LOW volatile.Register32 // 0x54 + EMACADDR3HIGH volatile.Register32 // 0x58 + EMACADDR3LOW volatile.Register32 // 0x5C + EMACADDR4HIGH volatile.Register32 // 0x60 + EMACADDR4LOW volatile.Register32 // 0x64 + EMACADDR5HIGH volatile.Register32 // 0x68 + EMACADDR5LOW volatile.Register32 // 0x6C + EMACADDR6HIGH volatile.Register32 // 0x70 + EMACADDR6LOW volatile.Register32 // 0x74 + EMACADDR7HIGH volatile.Register32 // 0x78 + EMACADDR7LOW volatile.Register32 // 0x7C + _ [88]byte + EMACCSTATUS volatile.Register32 // 0xD8 + EMACWDOGTO volatile.Register32 // 0xDC +} + +// EMAC_MAC.EMACCONFIG: MAC configuration +func (o *EMAC_MAC_Type) SetEMACCONFIG_PLTF(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x3)|value) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_PLTF() uint32 { + return volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x3 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_RX(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x4)|value<<2) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_RX() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x4) >> 2 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_TX(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x8)|value<<3) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_TX() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x8) >> 3 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_DEFERRALCHECK(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x10)|value<<4) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_DEFERRALCHECK() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x10) >> 4 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_BACKOFFLIMIT(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x60)|value<<5) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_BACKOFFLIMIT() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x60) >> 5 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_PADCRCSTRIP(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x80)|value<<7) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_PADCRCSTRIP() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x80) >> 7 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_RETRY(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x200)|value<<9) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_RETRY() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x200) >> 9 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_RXIPCOFFLOAD(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x400)|value<<10) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_RXIPCOFFLOAD() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x400) >> 10 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_DUPLEX(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x800)|value<<11) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_DUPLEX() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x800) >> 11 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x1000) >> 12 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_RXOWN(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x2000)|value<<13) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_RXOWN() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x2000) >> 13 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_FESPEED(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x4000)|value<<14) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_FESPEED() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x4000) >> 14 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_MII(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x8000)|value<<15) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_MII() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x8000) >> 15 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_DISABLECRS(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x10000)|value<<16) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_DISABLECRS() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x10000) >> 16 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_INTERFRAMEGAP(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0xe0000)|value<<17) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_INTERFRAMEGAP() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0xe0000) >> 17 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_JUMBOFRAME(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x100000)|value<<20) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_JUMBOFRAME() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x100000) >> 20 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_JABBER(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x400000)|value<<22) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_JABBER() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x400000) >> 22 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_WATCHDOG(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x800000)|value<<23) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_WATCHDOG() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x800000) >> 23 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_ASS2KP(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x8000000)|value<<27) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_ASS2KP() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x8000000) >> 27 +} +func (o *EMAC_MAC_Type) SetEMACCONFIG_SAIRC(value uint32) { + volatile.StoreUint32(&o.EMACCONFIG.Reg, volatile.LoadUint32(&o.EMACCONFIG.Reg)&^(0x70000000)|value<<28) +} +func (o *EMAC_MAC_Type) GetEMACCONFIG_SAIRC() uint32 { + return (volatile.LoadUint32(&o.EMACCONFIG.Reg) & 0x70000000) >> 28 +} + +// EMAC_MAC.EMACFF: Frame filter settings +func (o *EMAC_MAC_Type) SetEMACFF_PMODE(value uint32) { + volatile.StoreUint32(&o.EMACFF.Reg, volatile.LoadUint32(&o.EMACFF.Reg)&^(0x1)|value) +} +func (o *EMAC_MAC_Type) GetEMACFF_PMODE() uint32 { + return volatile.LoadUint32(&o.EMACFF.Reg) & 0x1 +} +func (o *EMAC_MAC_Type) SetEMACFF_DAIF(value uint32) { + volatile.StoreUint32(&o.EMACFF.Reg, volatile.LoadUint32(&o.EMACFF.Reg)&^(0x8)|value<<3) +} +func (o *EMAC_MAC_Type) GetEMACFF_DAIF() uint32 { + return (volatile.LoadUint32(&o.EMACFF.Reg) & 0x8) >> 3 +} +func (o *EMAC_MAC_Type) SetEMACFF_PAM(value uint32) { + volatile.StoreUint32(&o.EMACFF.Reg, volatile.LoadUint32(&o.EMACFF.Reg)&^(0x10)|value<<4) +} +func (o *EMAC_MAC_Type) GetEMACFF_PAM() uint32 { + return (volatile.LoadUint32(&o.EMACFF.Reg) & 0x10) >> 4 +} +func (o *EMAC_MAC_Type) SetEMACFF_DBF(value uint32) { + volatile.StoreUint32(&o.EMACFF.Reg, volatile.LoadUint32(&o.EMACFF.Reg)&^(0x20)|value<<5) +} +func (o *EMAC_MAC_Type) GetEMACFF_DBF() uint32 { + return (volatile.LoadUint32(&o.EMACFF.Reg) & 0x20) >> 5 +} +func (o *EMAC_MAC_Type) SetEMACFF_PCF(value uint32) { + volatile.StoreUint32(&o.EMACFF.Reg, volatile.LoadUint32(&o.EMACFF.Reg)&^(0xc0)|value<<6) +} +func (o *EMAC_MAC_Type) GetEMACFF_PCF() uint32 { + return (volatile.LoadUint32(&o.EMACFF.Reg) & 0xc0) >> 6 +} +func (o *EMAC_MAC_Type) SetEMACFF_SAIF(value uint32) { + volatile.StoreUint32(&o.EMACFF.Reg, volatile.LoadUint32(&o.EMACFF.Reg)&^(0x100)|value<<8) +} +func (o *EMAC_MAC_Type) GetEMACFF_SAIF() uint32 { + return (volatile.LoadUint32(&o.EMACFF.Reg) & 0x100) >> 8 +} +func (o *EMAC_MAC_Type) SetEMACFF_SAFE(value uint32) { + volatile.StoreUint32(&o.EMACFF.Reg, volatile.LoadUint32(&o.EMACFF.Reg)&^(0x200)|value<<9) +} +func (o *EMAC_MAC_Type) GetEMACFF_SAFE() uint32 { + return (volatile.LoadUint32(&o.EMACFF.Reg) & 0x200) >> 9 +} +func (o *EMAC_MAC_Type) SetEMACFF_RECEIVE_ALL(value uint32) { + volatile.StoreUint32(&o.EMACFF.Reg, volatile.LoadUint32(&o.EMACFF.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetEMACFF_RECEIVE_ALL() uint32 { + return (volatile.LoadUint32(&o.EMACFF.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACGMIIADDR: PHY configuration access +func (o *EMAC_MAC_Type) SetEMACGMIIADDR_MIIBUSY(value uint32) { + volatile.StoreUint32(&o.EMACGMIIADDR.Reg, volatile.LoadUint32(&o.EMACGMIIADDR.Reg)&^(0x1)|value) +} +func (o *EMAC_MAC_Type) GetEMACGMIIADDR_MIIBUSY() uint32 { + return volatile.LoadUint32(&o.EMACGMIIADDR.Reg) & 0x1 +} +func (o *EMAC_MAC_Type) SetEMACGMIIADDR_MIIWRITE(value uint32) { + volatile.StoreUint32(&o.EMACGMIIADDR.Reg, volatile.LoadUint32(&o.EMACGMIIADDR.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_MAC_Type) GetEMACGMIIADDR_MIIWRITE() uint32 { + return (volatile.LoadUint32(&o.EMACGMIIADDR.Reg) & 0x2) >> 1 +} +func (o *EMAC_MAC_Type) SetEMACGMIIADDR_MIICSRCLK(value uint32) { + volatile.StoreUint32(&o.EMACGMIIADDR.Reg, volatile.LoadUint32(&o.EMACGMIIADDR.Reg)&^(0x3c)|value<<2) +} +func (o *EMAC_MAC_Type) GetEMACGMIIADDR_MIICSRCLK() uint32 { + return (volatile.LoadUint32(&o.EMACGMIIADDR.Reg) & 0x3c) >> 2 +} +func (o *EMAC_MAC_Type) SetEMACGMIIADDR_MIIREG(value uint32) { + volatile.StoreUint32(&o.EMACGMIIADDR.Reg, volatile.LoadUint32(&o.EMACGMIIADDR.Reg)&^(0x7c0)|value<<6) +} +func (o *EMAC_MAC_Type) GetEMACGMIIADDR_MIIREG() uint32 { + return (volatile.LoadUint32(&o.EMACGMIIADDR.Reg) & 0x7c0) >> 6 +} +func (o *EMAC_MAC_Type) SetEMACGMIIADDR_MIIDEV(value uint32) { + volatile.StoreUint32(&o.EMACGMIIADDR.Reg, volatile.LoadUint32(&o.EMACGMIIADDR.Reg)&^(0xf800)|value<<11) +} +func (o *EMAC_MAC_Type) GetEMACGMIIADDR_MIIDEV() uint32 { + return (volatile.LoadUint32(&o.EMACGMIIADDR.Reg) & 0xf800) >> 11 +} + +// EMAC_MAC.EMACMIIDATA: PHY data read write +func (o *EMAC_MAC_Type) SetEMACMIIDATA_MII_DATA(value uint32) { + volatile.StoreUint32(&o.EMACMIIDATA.Reg, volatile.LoadUint32(&o.EMACMIIDATA.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACMIIDATA_MII_DATA() uint32 { + return volatile.LoadUint32(&o.EMACMIIDATA.Reg) & 0xffff +} + +// EMAC_MAC.EMACFC: Frame flow control +func (o *EMAC_MAC_Type) SetEMACFC_FCBBA(value uint32) { + volatile.StoreUint32(&o.EMACFC.Reg, volatile.LoadUint32(&o.EMACFC.Reg)&^(0x1)|value) +} +func (o *EMAC_MAC_Type) GetEMACFC_FCBBA() uint32 { + return volatile.LoadUint32(&o.EMACFC.Reg) & 0x1 +} +func (o *EMAC_MAC_Type) SetEMACFC_TFCE(value uint32) { + volatile.StoreUint32(&o.EMACFC.Reg, volatile.LoadUint32(&o.EMACFC.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_MAC_Type) GetEMACFC_TFCE() uint32 { + return (volatile.LoadUint32(&o.EMACFC.Reg) & 0x2) >> 1 +} +func (o *EMAC_MAC_Type) SetEMACFC_RFCE(value uint32) { + volatile.StoreUint32(&o.EMACFC.Reg, volatile.LoadUint32(&o.EMACFC.Reg)&^(0x4)|value<<2) +} +func (o *EMAC_MAC_Type) GetEMACFC_RFCE() uint32 { + return (volatile.LoadUint32(&o.EMACFC.Reg) & 0x4) >> 2 +} +func (o *EMAC_MAC_Type) SetEMACFC_UPFD(value uint32) { + volatile.StoreUint32(&o.EMACFC.Reg, volatile.LoadUint32(&o.EMACFC.Reg)&^(0x8)|value<<3) +} +func (o *EMAC_MAC_Type) GetEMACFC_UPFD() uint32 { + return (volatile.LoadUint32(&o.EMACFC.Reg) & 0x8) >> 3 +} +func (o *EMAC_MAC_Type) SetEMACFC_PLT(value uint32) { + volatile.StoreUint32(&o.EMACFC.Reg, volatile.LoadUint32(&o.EMACFC.Reg)&^(0x30)|value<<4) +} +func (o *EMAC_MAC_Type) GetEMACFC_PLT() uint32 { + return (volatile.LoadUint32(&o.EMACFC.Reg) & 0x30) >> 4 +} +func (o *EMAC_MAC_Type) SetEMACFC_DZPQ(value uint32) { + volatile.StoreUint32(&o.EMACFC.Reg, volatile.LoadUint32(&o.EMACFC.Reg)&^(0x80)|value<<7) +} +func (o *EMAC_MAC_Type) GetEMACFC_DZPQ() uint32 { + return (volatile.LoadUint32(&o.EMACFC.Reg) & 0x80) >> 7 +} +func (o *EMAC_MAC_Type) SetEMACFC_PAUSE_TIME(value uint32) { + volatile.StoreUint32(&o.EMACFC.Reg, volatile.LoadUint32(&o.EMACFC.Reg)&^(0xffff0000)|value<<16) +} +func (o *EMAC_MAC_Type) GetEMACFC_PAUSE_TIME() uint32 { + return (volatile.LoadUint32(&o.EMACFC.Reg) & 0xffff0000) >> 16 +} + +// EMAC_MAC.EMACDEBUG: Status debugging bits +func (o *EMAC_MAC_Type) SetEMACDEBUG_MACRPES(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x1)|value) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MACRPES() uint32 { + return volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x1 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MACRFFCS(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x6)|value<<1) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MACRFFCS() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x6) >> 1 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MTLRFWCAS(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x10)|value<<4) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MTLRFWCAS() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x10) >> 4 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MTLRFRCS(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x60)|value<<5) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MTLRFRCS() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x60) >> 5 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MTLRFFLS(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x300)|value<<8) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MTLRFFLS() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x300) >> 8 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MACTPES(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x10000)|value<<16) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MACTPES() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x10000) >> 16 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MACTFCS(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x60000)|value<<17) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MACTFCS() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x60000) >> 17 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MACTP(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x80000)|value<<19) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MACTP() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x80000) >> 19 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MTLTFRCS(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x300000)|value<<20) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MTLTFRCS() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x300000) >> 20 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MTLTFWCS(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x400000)|value<<22) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MTLTFWCS() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x400000) >> 22 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MTLTFNES(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x1000000)|value<<24) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MTLTFNES() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x1000000) >> 24 +} +func (o *EMAC_MAC_Type) SetEMACDEBUG_MTLTSFFS(value uint32) { + volatile.StoreUint32(&o.EMACDEBUG.Reg, volatile.LoadUint32(&o.EMACDEBUG.Reg)&^(0x2000000)|value<<25) +} +func (o *EMAC_MAC_Type) GetEMACDEBUG_MTLTSFFS() uint32 { + return (volatile.LoadUint32(&o.EMACDEBUG.Reg) & 0x2000000) >> 25 +} + +// EMAC_MAC.PMT_CSR: PMT Control and Status +func (o *EMAC_MAC_Type) SetPMT_CSR_PWRDWN(value uint32) { + volatile.StoreUint32(&o.PMT_CSR.Reg, volatile.LoadUint32(&o.PMT_CSR.Reg)&^(0x1)|value) +} +func (o *EMAC_MAC_Type) GetPMT_CSR_PWRDWN() uint32 { + return volatile.LoadUint32(&o.PMT_CSR.Reg) & 0x1 +} +func (o *EMAC_MAC_Type) SetPMT_CSR_MGKPKTEN(value uint32) { + volatile.StoreUint32(&o.PMT_CSR.Reg, volatile.LoadUint32(&o.PMT_CSR.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_MAC_Type) GetPMT_CSR_MGKPKTEN() uint32 { + return (volatile.LoadUint32(&o.PMT_CSR.Reg) & 0x2) >> 1 +} +func (o *EMAC_MAC_Type) SetPMT_CSR_RWKPKTEN(value uint32) { + volatile.StoreUint32(&o.PMT_CSR.Reg, volatile.LoadUint32(&o.PMT_CSR.Reg)&^(0x4)|value<<2) +} +func (o *EMAC_MAC_Type) GetPMT_CSR_RWKPKTEN() uint32 { + return (volatile.LoadUint32(&o.PMT_CSR.Reg) & 0x4) >> 2 +} +func (o *EMAC_MAC_Type) SetPMT_CSR_MGKPRCVD(value uint32) { + volatile.StoreUint32(&o.PMT_CSR.Reg, volatile.LoadUint32(&o.PMT_CSR.Reg)&^(0x20)|value<<5) +} +func (o *EMAC_MAC_Type) GetPMT_CSR_MGKPRCVD() uint32 { + return (volatile.LoadUint32(&o.PMT_CSR.Reg) & 0x20) >> 5 +} +func (o *EMAC_MAC_Type) SetPMT_CSR_RWKPRCVD(value uint32) { + volatile.StoreUint32(&o.PMT_CSR.Reg, volatile.LoadUint32(&o.PMT_CSR.Reg)&^(0x40)|value<<6) +} +func (o *EMAC_MAC_Type) GetPMT_CSR_RWKPRCVD() uint32 { + return (volatile.LoadUint32(&o.PMT_CSR.Reg) & 0x40) >> 6 +} +func (o *EMAC_MAC_Type) SetPMT_CSR_GLBLUCAST(value uint32) { + volatile.StoreUint32(&o.PMT_CSR.Reg, volatile.LoadUint32(&o.PMT_CSR.Reg)&^(0x200)|value<<9) +} +func (o *EMAC_MAC_Type) GetPMT_CSR_GLBLUCAST() uint32 { + return (volatile.LoadUint32(&o.PMT_CSR.Reg) & 0x200) >> 9 +} +func (o *EMAC_MAC_Type) SetPMT_CSR_RWKPTR(value uint32) { + volatile.StoreUint32(&o.PMT_CSR.Reg, volatile.LoadUint32(&o.PMT_CSR.Reg)&^(0x1f000000)|value<<24) +} +func (o *EMAC_MAC_Type) GetPMT_CSR_RWKPTR() uint32 { + return (volatile.LoadUint32(&o.PMT_CSR.Reg) & 0x1f000000) >> 24 +} +func (o *EMAC_MAC_Type) SetPMT_CSR_RWKFILTRST(value uint32) { + volatile.StoreUint32(&o.PMT_CSR.Reg, volatile.LoadUint32(&o.PMT_CSR.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetPMT_CSR_RWKFILTRST() uint32 { + return (volatile.LoadUint32(&o.PMT_CSR.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACLPI_CRS: LPI Control and Status +func (o *EMAC_MAC_Type) SetEMACLPI_CRS_TLPIEN(value uint32) { + volatile.StoreUint32(&o.EMACLPI_CRS.Reg, volatile.LoadUint32(&o.EMACLPI_CRS.Reg)&^(0x1)|value) +} +func (o *EMAC_MAC_Type) GetEMACLPI_CRS_TLPIEN() uint32 { + return volatile.LoadUint32(&o.EMACLPI_CRS.Reg) & 0x1 +} +func (o *EMAC_MAC_Type) SetEMACLPI_CRS_TLPIEX(value uint32) { + volatile.StoreUint32(&o.EMACLPI_CRS.Reg, volatile.LoadUint32(&o.EMACLPI_CRS.Reg)&^(0x2)|value<<1) +} +func (o *EMAC_MAC_Type) GetEMACLPI_CRS_TLPIEX() uint32 { + return (volatile.LoadUint32(&o.EMACLPI_CRS.Reg) & 0x2) >> 1 +} +func (o *EMAC_MAC_Type) SetEMACLPI_CRS_RLPIEN(value uint32) { + volatile.StoreUint32(&o.EMACLPI_CRS.Reg, volatile.LoadUint32(&o.EMACLPI_CRS.Reg)&^(0x4)|value<<2) +} +func (o *EMAC_MAC_Type) GetEMACLPI_CRS_RLPIEN() uint32 { + return (volatile.LoadUint32(&o.EMACLPI_CRS.Reg) & 0x4) >> 2 +} +func (o *EMAC_MAC_Type) SetEMACLPI_CRS_RLPIEX(value uint32) { + volatile.StoreUint32(&o.EMACLPI_CRS.Reg, volatile.LoadUint32(&o.EMACLPI_CRS.Reg)&^(0x8)|value<<3) +} +func (o *EMAC_MAC_Type) GetEMACLPI_CRS_RLPIEX() uint32 { + return (volatile.LoadUint32(&o.EMACLPI_CRS.Reg) & 0x8) >> 3 +} +func (o *EMAC_MAC_Type) SetEMACLPI_CRS_TLPIST(value uint32) { + volatile.StoreUint32(&o.EMACLPI_CRS.Reg, volatile.LoadUint32(&o.EMACLPI_CRS.Reg)&^(0x100)|value<<8) +} +func (o *EMAC_MAC_Type) GetEMACLPI_CRS_TLPIST() uint32 { + return (volatile.LoadUint32(&o.EMACLPI_CRS.Reg) & 0x100) >> 8 +} +func (o *EMAC_MAC_Type) SetEMACLPI_CRS_RLPIST(value uint32) { + volatile.StoreUint32(&o.EMACLPI_CRS.Reg, volatile.LoadUint32(&o.EMACLPI_CRS.Reg)&^(0x200)|value<<9) +} +func (o *EMAC_MAC_Type) GetEMACLPI_CRS_RLPIST() uint32 { + return (volatile.LoadUint32(&o.EMACLPI_CRS.Reg) & 0x200) >> 9 +} +func (o *EMAC_MAC_Type) SetEMACLPI_CRS_LPIEN(value uint32) { + volatile.StoreUint32(&o.EMACLPI_CRS.Reg, volatile.LoadUint32(&o.EMACLPI_CRS.Reg)&^(0x10000)|value<<16) +} +func (o *EMAC_MAC_Type) GetEMACLPI_CRS_LPIEN() uint32 { + return (volatile.LoadUint32(&o.EMACLPI_CRS.Reg) & 0x10000) >> 16 +} +func (o *EMAC_MAC_Type) SetEMACLPI_CRS_PLS(value uint32) { + volatile.StoreUint32(&o.EMACLPI_CRS.Reg, volatile.LoadUint32(&o.EMACLPI_CRS.Reg)&^(0x20000)|value<<17) +} +func (o *EMAC_MAC_Type) GetEMACLPI_CRS_PLS() uint32 { + return (volatile.LoadUint32(&o.EMACLPI_CRS.Reg) & 0x20000) >> 17 +} +func (o *EMAC_MAC_Type) SetEMACLPI_CRS_LPITXA(value uint32) { + volatile.StoreUint32(&o.EMACLPI_CRS.Reg, volatile.LoadUint32(&o.EMACLPI_CRS.Reg)&^(0x80000)|value<<19) +} +func (o *EMAC_MAC_Type) GetEMACLPI_CRS_LPITXA() uint32 { + return (volatile.LoadUint32(&o.EMACLPI_CRS.Reg) & 0x80000) >> 19 +} + +// EMAC_MAC.EMACLPITIMERSCONTROL: LPI Timers Control +func (o *EMAC_MAC_Type) SetEMACLPITIMERSCONTROL_LPI_TW_TIMER(value uint32) { + volatile.StoreUint32(&o.EMACLPITIMERSCONTROL.Reg, volatile.LoadUint32(&o.EMACLPITIMERSCONTROL.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACLPITIMERSCONTROL_LPI_TW_TIMER() uint32 { + return volatile.LoadUint32(&o.EMACLPITIMERSCONTROL.Reg) & 0xffff +} +func (o *EMAC_MAC_Type) SetEMACLPITIMERSCONTROL_LPI_LS_TIMER(value uint32) { + volatile.StoreUint32(&o.EMACLPITIMERSCONTROL.Reg, volatile.LoadUint32(&o.EMACLPITIMERSCONTROL.Reg)&^(0x3ff0000)|value<<16) +} +func (o *EMAC_MAC_Type) GetEMACLPITIMERSCONTROL_LPI_LS_TIMER() uint32 { + return (volatile.LoadUint32(&o.EMACLPITIMERSCONTROL.Reg) & 0x3ff0000) >> 16 +} + +// EMAC_MAC.EMACINTS: Interrupt status +func (o *EMAC_MAC_Type) SetEMACINTS_PMTINTS(value uint32) { + volatile.StoreUint32(&o.EMACINTS.Reg, volatile.LoadUint32(&o.EMACINTS.Reg)&^(0x8)|value<<3) +} +func (o *EMAC_MAC_Type) GetEMACINTS_PMTINTS() uint32 { + return (volatile.LoadUint32(&o.EMACINTS.Reg) & 0x8) >> 3 +} +func (o *EMAC_MAC_Type) SetEMACINTS_LPIIS(value uint32) { + volatile.StoreUint32(&o.EMACINTS.Reg, volatile.LoadUint32(&o.EMACINTS.Reg)&^(0x400)|value<<10) +} +func (o *EMAC_MAC_Type) GetEMACINTS_LPIIS() uint32 { + return (volatile.LoadUint32(&o.EMACINTS.Reg) & 0x400) >> 10 +} + +// EMAC_MAC.EMACINTMASK: Interrupt mask +func (o *EMAC_MAC_Type) SetEMACINTMASK_PMTINTMASK(value uint32) { + volatile.StoreUint32(&o.EMACINTMASK.Reg, volatile.LoadUint32(&o.EMACINTMASK.Reg)&^(0x8)|value<<3) +} +func (o *EMAC_MAC_Type) GetEMACINTMASK_PMTINTMASK() uint32 { + return (volatile.LoadUint32(&o.EMACINTMASK.Reg) & 0x8) >> 3 +} +func (o *EMAC_MAC_Type) SetEMACINTMASK_LPIINTMASK(value uint32) { + volatile.StoreUint32(&o.EMACINTMASK.Reg, volatile.LoadUint32(&o.EMACINTMASK.Reg)&^(0x400)|value<<10) +} +func (o *EMAC_MAC_Type) GetEMACINTMASK_LPIINTMASK() uint32 { + return (volatile.LoadUint32(&o.EMACINTMASK.Reg) & 0x400) >> 10 +} + +// EMAC_MAC.EMACADDR0HIGH: Upper 16 bits of the first 6-byte MAC address +func (o *EMAC_MAC_Type) SetEMACADDR0HIGH_ADDRESS0_HI(value uint32) { + volatile.StoreUint32(&o.EMACADDR0HIGH.Reg, volatile.LoadUint32(&o.EMACADDR0HIGH.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACADDR0HIGH_ADDRESS0_HI() uint32 { + return volatile.LoadUint32(&o.EMACADDR0HIGH.Reg) & 0xffff +} +func (o *EMAC_MAC_Type) SetEMACADDR0HIGH_ADDRESS_ENABLE0(value uint32) { + volatile.StoreUint32(&o.EMACADDR0HIGH.Reg, volatile.LoadUint32(&o.EMACADDR0HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetEMACADDR0HIGH_ADDRESS_ENABLE0() uint32 { + return (volatile.LoadUint32(&o.EMACADDR0HIGH.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACADDR1HIGH: Upper 16 bits of the second 6-byte MAC address +func (o *EMAC_MAC_Type) SetEMACADDR1HIGH_MAC_ADDRESS1_HI(value uint32) { + volatile.StoreUint32(&o.EMACADDR1HIGH.Reg, volatile.LoadUint32(&o.EMACADDR1HIGH.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACADDR1HIGH_MAC_ADDRESS1_HI() uint32 { + return volatile.LoadUint32(&o.EMACADDR1HIGH.Reg) & 0xffff +} +func (o *EMAC_MAC_Type) SetEMACADDR1HIGH_MASK_BYTE_CONTROL(value uint32) { + volatile.StoreUint32(&o.EMACADDR1HIGH.Reg, volatile.LoadUint32(&o.EMACADDR1HIGH.Reg)&^(0x3f000000)|value<<24) +} +func (o *EMAC_MAC_Type) GetEMACADDR1HIGH_MASK_BYTE_CONTROL() uint32 { + return (volatile.LoadUint32(&o.EMACADDR1HIGH.Reg) & 0x3f000000) >> 24 +} +func (o *EMAC_MAC_Type) SetEMACADDR1HIGH_SOURCE_ADDRESS(value uint32) { + volatile.StoreUint32(&o.EMACADDR1HIGH.Reg, volatile.LoadUint32(&o.EMACADDR1HIGH.Reg)&^(0x40000000)|value<<30) +} +func (o *EMAC_MAC_Type) GetEMACADDR1HIGH_SOURCE_ADDRESS() uint32 { + return (volatile.LoadUint32(&o.EMACADDR1HIGH.Reg) & 0x40000000) >> 30 +} +func (o *EMAC_MAC_Type) SetEMACADDR1HIGH_ADDRESS_ENABLE1(value uint32) { + volatile.StoreUint32(&o.EMACADDR1HIGH.Reg, volatile.LoadUint32(&o.EMACADDR1HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetEMACADDR1HIGH_ADDRESS_ENABLE1() uint32 { + return (volatile.LoadUint32(&o.EMACADDR1HIGH.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACADDR2HIGH: Upper 16 bits of the third 6-byte MAC address +func (o *EMAC_MAC_Type) SetEMACADDR2HIGH_MAC_ADDRESS2_HI(value uint32) { + volatile.StoreUint32(&o.EMACADDR2HIGH.Reg, volatile.LoadUint32(&o.EMACADDR2HIGH.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACADDR2HIGH_MAC_ADDRESS2_HI() uint32 { + return volatile.LoadUint32(&o.EMACADDR2HIGH.Reg) & 0xffff +} +func (o *EMAC_MAC_Type) SetEMACADDR2HIGH_MASK_BYTE_CONTROL2(value uint32) { + volatile.StoreUint32(&o.EMACADDR2HIGH.Reg, volatile.LoadUint32(&o.EMACADDR2HIGH.Reg)&^(0x3f000000)|value<<24) +} +func (o *EMAC_MAC_Type) GetEMACADDR2HIGH_MASK_BYTE_CONTROL2() uint32 { + return (volatile.LoadUint32(&o.EMACADDR2HIGH.Reg) & 0x3f000000) >> 24 +} +func (o *EMAC_MAC_Type) SetEMACADDR2HIGH_SOURCE_ADDRESS2(value uint32) { + volatile.StoreUint32(&o.EMACADDR2HIGH.Reg, volatile.LoadUint32(&o.EMACADDR2HIGH.Reg)&^(0x40000000)|value<<30) +} +func (o *EMAC_MAC_Type) GetEMACADDR2HIGH_SOURCE_ADDRESS2() uint32 { + return (volatile.LoadUint32(&o.EMACADDR2HIGH.Reg) & 0x40000000) >> 30 +} +func (o *EMAC_MAC_Type) SetEMACADDR2HIGH_ADDRESS_ENABLE2(value uint32) { + volatile.StoreUint32(&o.EMACADDR2HIGH.Reg, volatile.LoadUint32(&o.EMACADDR2HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetEMACADDR2HIGH_ADDRESS_ENABLE2() uint32 { + return (volatile.LoadUint32(&o.EMACADDR2HIGH.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACADDR3HIGH: Upper 16 bits of the fourth 6-byte MAC address +func (o *EMAC_MAC_Type) SetEMACADDR3HIGH_MAC_ADDRESS3_HI(value uint32) { + volatile.StoreUint32(&o.EMACADDR3HIGH.Reg, volatile.LoadUint32(&o.EMACADDR3HIGH.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACADDR3HIGH_MAC_ADDRESS3_HI() uint32 { + return volatile.LoadUint32(&o.EMACADDR3HIGH.Reg) & 0xffff +} +func (o *EMAC_MAC_Type) SetEMACADDR3HIGH_MASK_BYTE_CONTROL3(value uint32) { + volatile.StoreUint32(&o.EMACADDR3HIGH.Reg, volatile.LoadUint32(&o.EMACADDR3HIGH.Reg)&^(0x3f000000)|value<<24) +} +func (o *EMAC_MAC_Type) GetEMACADDR3HIGH_MASK_BYTE_CONTROL3() uint32 { + return (volatile.LoadUint32(&o.EMACADDR3HIGH.Reg) & 0x3f000000) >> 24 +} +func (o *EMAC_MAC_Type) SetEMACADDR3HIGH_SOURCE_ADDRESS3(value uint32) { + volatile.StoreUint32(&o.EMACADDR3HIGH.Reg, volatile.LoadUint32(&o.EMACADDR3HIGH.Reg)&^(0x40000000)|value<<30) +} +func (o *EMAC_MAC_Type) GetEMACADDR3HIGH_SOURCE_ADDRESS3() uint32 { + return (volatile.LoadUint32(&o.EMACADDR3HIGH.Reg) & 0x40000000) >> 30 +} +func (o *EMAC_MAC_Type) SetEMACADDR3HIGH_ADDRESS_ENABLE3(value uint32) { + volatile.StoreUint32(&o.EMACADDR3HIGH.Reg, volatile.LoadUint32(&o.EMACADDR3HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetEMACADDR3HIGH_ADDRESS_ENABLE3() uint32 { + return (volatile.LoadUint32(&o.EMACADDR3HIGH.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACADDR4HIGH: Upper 16 bits of the fifth 6-byte MAC address +func (o *EMAC_MAC_Type) SetEMACADDR4HIGH_MAC_ADDRESS4_HI(value uint32) { + volatile.StoreUint32(&o.EMACADDR4HIGH.Reg, volatile.LoadUint32(&o.EMACADDR4HIGH.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACADDR4HIGH_MAC_ADDRESS4_HI() uint32 { + return volatile.LoadUint32(&o.EMACADDR4HIGH.Reg) & 0xffff +} +func (o *EMAC_MAC_Type) SetEMACADDR4HIGH_MASK_BYTE_CONTROL4(value uint32) { + volatile.StoreUint32(&o.EMACADDR4HIGH.Reg, volatile.LoadUint32(&o.EMACADDR4HIGH.Reg)&^(0x3f000000)|value<<24) +} +func (o *EMAC_MAC_Type) GetEMACADDR4HIGH_MASK_BYTE_CONTROL4() uint32 { + return (volatile.LoadUint32(&o.EMACADDR4HIGH.Reg) & 0x3f000000) >> 24 +} +func (o *EMAC_MAC_Type) SetEMACADDR4HIGH_SOURCE_ADDRESS4(value uint32) { + volatile.StoreUint32(&o.EMACADDR4HIGH.Reg, volatile.LoadUint32(&o.EMACADDR4HIGH.Reg)&^(0x40000000)|value<<30) +} +func (o *EMAC_MAC_Type) GetEMACADDR4HIGH_SOURCE_ADDRESS4() uint32 { + return (volatile.LoadUint32(&o.EMACADDR4HIGH.Reg) & 0x40000000) >> 30 +} +func (o *EMAC_MAC_Type) SetEMACADDR4HIGH_ADDRESS_ENABLE4(value uint32) { + volatile.StoreUint32(&o.EMACADDR4HIGH.Reg, volatile.LoadUint32(&o.EMACADDR4HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetEMACADDR4HIGH_ADDRESS_ENABLE4() uint32 { + return (volatile.LoadUint32(&o.EMACADDR4HIGH.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACADDR5HIGH: Upper 16 bits of the sixth 6-byte MAC address +func (o *EMAC_MAC_Type) SetEMACADDR5HIGH_MAC_ADDRESS5_HI(value uint32) { + volatile.StoreUint32(&o.EMACADDR5HIGH.Reg, volatile.LoadUint32(&o.EMACADDR5HIGH.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACADDR5HIGH_MAC_ADDRESS5_HI() uint32 { + return volatile.LoadUint32(&o.EMACADDR5HIGH.Reg) & 0xffff +} +func (o *EMAC_MAC_Type) SetEMACADDR5HIGH_MASK_BYTE_CONTROL5(value uint32) { + volatile.StoreUint32(&o.EMACADDR5HIGH.Reg, volatile.LoadUint32(&o.EMACADDR5HIGH.Reg)&^(0x3f000000)|value<<24) +} +func (o *EMAC_MAC_Type) GetEMACADDR5HIGH_MASK_BYTE_CONTROL5() uint32 { + return (volatile.LoadUint32(&o.EMACADDR5HIGH.Reg) & 0x3f000000) >> 24 +} +func (o *EMAC_MAC_Type) SetEMACADDR5HIGH_SOURCE_ADDRESS5(value uint32) { + volatile.StoreUint32(&o.EMACADDR5HIGH.Reg, volatile.LoadUint32(&o.EMACADDR5HIGH.Reg)&^(0x40000000)|value<<30) +} +func (o *EMAC_MAC_Type) GetEMACADDR5HIGH_SOURCE_ADDRESS5() uint32 { + return (volatile.LoadUint32(&o.EMACADDR5HIGH.Reg) & 0x40000000) >> 30 +} +func (o *EMAC_MAC_Type) SetEMACADDR5HIGH_ADDRESS_ENABLE5(value uint32) { + volatile.StoreUint32(&o.EMACADDR5HIGH.Reg, volatile.LoadUint32(&o.EMACADDR5HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetEMACADDR5HIGH_ADDRESS_ENABLE5() uint32 { + return (volatile.LoadUint32(&o.EMACADDR5HIGH.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACADDR6HIGH: Upper 16 bits of the seventh 6-byte MAC address +func (o *EMAC_MAC_Type) SetEMACADDR6HIGH_MAC_ADDRESS6_HI(value uint32) { + volatile.StoreUint32(&o.EMACADDR6HIGH.Reg, volatile.LoadUint32(&o.EMACADDR6HIGH.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACADDR6HIGH_MAC_ADDRESS6_HI() uint32 { + return volatile.LoadUint32(&o.EMACADDR6HIGH.Reg) & 0xffff +} +func (o *EMAC_MAC_Type) SetEMACADDR6HIGH_MASK_BYTE_CONTROL6(value uint32) { + volatile.StoreUint32(&o.EMACADDR6HIGH.Reg, volatile.LoadUint32(&o.EMACADDR6HIGH.Reg)&^(0x3f000000)|value<<24) +} +func (o *EMAC_MAC_Type) GetEMACADDR6HIGH_MASK_BYTE_CONTROL6() uint32 { + return (volatile.LoadUint32(&o.EMACADDR6HIGH.Reg) & 0x3f000000) >> 24 +} +func (o *EMAC_MAC_Type) SetEMACADDR6HIGH_SOURCE_ADDRESS6(value uint32) { + volatile.StoreUint32(&o.EMACADDR6HIGH.Reg, volatile.LoadUint32(&o.EMACADDR6HIGH.Reg)&^(0x40000000)|value<<30) +} +func (o *EMAC_MAC_Type) GetEMACADDR6HIGH_SOURCE_ADDRESS6() uint32 { + return (volatile.LoadUint32(&o.EMACADDR6HIGH.Reg) & 0x40000000) >> 30 +} +func (o *EMAC_MAC_Type) SetEMACADDR6HIGH_ADDRESS_ENABLE6(value uint32) { + volatile.StoreUint32(&o.EMACADDR6HIGH.Reg, volatile.LoadUint32(&o.EMACADDR6HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetEMACADDR6HIGH_ADDRESS_ENABLE6() uint32 { + return (volatile.LoadUint32(&o.EMACADDR6HIGH.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACADDR7HIGH: Upper 16 bits of the eighth 6-byte MAC address +func (o *EMAC_MAC_Type) SetEMACADDR7HIGH_MAC_ADDRESS7_HI(value uint32) { + volatile.StoreUint32(&o.EMACADDR7HIGH.Reg, volatile.LoadUint32(&o.EMACADDR7HIGH.Reg)&^(0xffff)|value) +} +func (o *EMAC_MAC_Type) GetEMACADDR7HIGH_MAC_ADDRESS7_HI() uint32 { + return volatile.LoadUint32(&o.EMACADDR7HIGH.Reg) & 0xffff +} +func (o *EMAC_MAC_Type) SetEMACADDR7HIGH_MASK_BYTE_CONTROL7(value uint32) { + volatile.StoreUint32(&o.EMACADDR7HIGH.Reg, volatile.LoadUint32(&o.EMACADDR7HIGH.Reg)&^(0x3f000000)|value<<24) +} +func (o *EMAC_MAC_Type) GetEMACADDR7HIGH_MASK_BYTE_CONTROL7() uint32 { + return (volatile.LoadUint32(&o.EMACADDR7HIGH.Reg) & 0x3f000000) >> 24 +} +func (o *EMAC_MAC_Type) SetEMACADDR7HIGH_SOURCE_ADDRESS7(value uint32) { + volatile.StoreUint32(&o.EMACADDR7HIGH.Reg, volatile.LoadUint32(&o.EMACADDR7HIGH.Reg)&^(0x40000000)|value<<30) +} +func (o *EMAC_MAC_Type) GetEMACADDR7HIGH_SOURCE_ADDRESS7() uint32 { + return (volatile.LoadUint32(&o.EMACADDR7HIGH.Reg) & 0x40000000) >> 30 +} +func (o *EMAC_MAC_Type) SetEMACADDR7HIGH_ADDRESS_ENABLE7(value uint32) { + volatile.StoreUint32(&o.EMACADDR7HIGH.Reg, volatile.LoadUint32(&o.EMACADDR7HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *EMAC_MAC_Type) GetEMACADDR7HIGH_ADDRESS_ENABLE7() uint32 { + return (volatile.LoadUint32(&o.EMACADDR7HIGH.Reg) & 0x80000000) >> 31 +} + +// EMAC_MAC.EMACCSTATUS: Link communication status +func (o *EMAC_MAC_Type) SetEMACCSTATUS_LINK_MODE(value uint32) { + volatile.StoreUint32(&o.EMACCSTATUS.Reg, volatile.LoadUint32(&o.EMACCSTATUS.Reg)&^(0x1)|value) +} +func (o *EMAC_MAC_Type) GetEMACCSTATUS_LINK_MODE() uint32 { + return volatile.LoadUint32(&o.EMACCSTATUS.Reg) & 0x1 +} +func (o *EMAC_MAC_Type) SetEMACCSTATUS_LINK_SPEED(value uint32) { + volatile.StoreUint32(&o.EMACCSTATUS.Reg, volatile.LoadUint32(&o.EMACCSTATUS.Reg)&^(0x6)|value<<1) +} +func (o *EMAC_MAC_Type) GetEMACCSTATUS_LINK_SPEED() uint32 { + return (volatile.LoadUint32(&o.EMACCSTATUS.Reg) & 0x6) >> 1 +} +func (o *EMAC_MAC_Type) SetEMACCSTATUS_JABBER_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.EMACCSTATUS.Reg, volatile.LoadUint32(&o.EMACCSTATUS.Reg)&^(0x10)|value<<4) +} +func (o *EMAC_MAC_Type) GetEMACCSTATUS_JABBER_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.EMACCSTATUS.Reg) & 0x10) >> 4 +} + +// EMAC_MAC.EMACWDOGTO: Watchdog timeout control +func (o *EMAC_MAC_Type) SetEMACWDOGTO_WDOGTO(value uint32) { + volatile.StoreUint32(&o.EMACWDOGTO.Reg, volatile.LoadUint32(&o.EMACWDOGTO.Reg)&^(0x3fff)|value) +} +func (o *EMAC_MAC_Type) GetEMACWDOGTO_WDOGTO() uint32 { + return volatile.LoadUint32(&o.EMACWDOGTO.Reg) & 0x3fff +} +func (o *EMAC_MAC_Type) SetEMACWDOGTO_PWDOGEN(value uint32) { + volatile.StoreUint32(&o.EMACWDOGTO.Reg, volatile.LoadUint32(&o.EMACWDOGTO.Reg)&^(0x10000)|value<<16) +} +func (o *EMAC_MAC_Type) GetEMACWDOGTO_PWDOGEN() uint32 { + return (volatile.LoadUint32(&o.EMACWDOGTO.Reg) & 0x10000) >> 16 +} + +// FLASH_ENCRYPTION Peripheral +type FLASH_ENCRYPTION_Type struct { + BUFFER_0 volatile.Register32 // 0x0 + BUFFER_1 volatile.Register32 // 0x4 + BUFFER_2 volatile.Register32 // 0x8 + BUFFER_3 volatile.Register32 // 0xC + BUFFER_4 volatile.Register32 // 0x10 + BUFFER_5 volatile.Register32 // 0x14 + BUFFER_6 volatile.Register32 // 0x18 + BUFFER_7 volatile.Register32 // 0x1C + START volatile.Register32 // 0x20 + ADDRESS volatile.Register32 // 0x24 + DONE volatile.Register32 // 0x28 +} + +// FLASH_ENCRYPTION.BUFFER_0 +func (o *FLASH_ENCRYPTION_Type) SetBUFFER_0_BUFFER(value uint32) { + volatile.StoreUint32(&o.BUFFER_0.Reg, volatile.LoadUint32(&o.BUFFER_0.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetBUFFER_0_BUFFER() uint32 { + return volatile.LoadUint32(&o.BUFFER_0.Reg) & 0xff +} + +// FLASH_ENCRYPTION.BUFFER_1 +func (o *FLASH_ENCRYPTION_Type) SetBUFFER_1_BUFFER(value uint32) { + volatile.StoreUint32(&o.BUFFER_1.Reg, volatile.LoadUint32(&o.BUFFER_1.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetBUFFER_1_BUFFER() uint32 { + return volatile.LoadUint32(&o.BUFFER_1.Reg) & 0xff +} + +// FLASH_ENCRYPTION.BUFFER_2 +func (o *FLASH_ENCRYPTION_Type) SetBUFFER_2_BUFFER(value uint32) { + volatile.StoreUint32(&o.BUFFER_2.Reg, volatile.LoadUint32(&o.BUFFER_2.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetBUFFER_2_BUFFER() uint32 { + return volatile.LoadUint32(&o.BUFFER_2.Reg) & 0xff +} + +// FLASH_ENCRYPTION.BUFFER_3 +func (o *FLASH_ENCRYPTION_Type) SetBUFFER_3_BUFFER(value uint32) { + volatile.StoreUint32(&o.BUFFER_3.Reg, volatile.LoadUint32(&o.BUFFER_3.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetBUFFER_3_BUFFER() uint32 { + return volatile.LoadUint32(&o.BUFFER_3.Reg) & 0xff +} + +// FLASH_ENCRYPTION.BUFFER_4 +func (o *FLASH_ENCRYPTION_Type) SetBUFFER_4_BUFFER(value uint32) { + volatile.StoreUint32(&o.BUFFER_4.Reg, volatile.LoadUint32(&o.BUFFER_4.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetBUFFER_4_BUFFER() uint32 { + return volatile.LoadUint32(&o.BUFFER_4.Reg) & 0xff +} + +// FLASH_ENCRYPTION.BUFFER_5 +func (o *FLASH_ENCRYPTION_Type) SetBUFFER_5_BUFFER(value uint32) { + volatile.StoreUint32(&o.BUFFER_5.Reg, volatile.LoadUint32(&o.BUFFER_5.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetBUFFER_5_BUFFER() uint32 { + return volatile.LoadUint32(&o.BUFFER_5.Reg) & 0xff +} + +// FLASH_ENCRYPTION.BUFFER_6 +func (o *FLASH_ENCRYPTION_Type) SetBUFFER_6_BUFFER(value uint32) { + volatile.StoreUint32(&o.BUFFER_6.Reg, volatile.LoadUint32(&o.BUFFER_6.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetBUFFER_6_BUFFER() uint32 { + return volatile.LoadUint32(&o.BUFFER_6.Reg) & 0xff +} + +// FLASH_ENCRYPTION.BUFFER_7 +func (o *FLASH_ENCRYPTION_Type) SetBUFFER_7_BUFFER(value uint32) { + volatile.StoreUint32(&o.BUFFER_7.Reg, volatile.LoadUint32(&o.BUFFER_7.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetBUFFER_7_BUFFER() uint32 { + return volatile.LoadUint32(&o.BUFFER_7.Reg) & 0xff +} + +// FLASH_ENCRYPTION.START +func (o *FLASH_ENCRYPTION_Type) SetSTART_FLASH_START(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetSTART_FLASH_START() uint32 { + return volatile.LoadUint32(&o.START.Reg) & 0xff +} + +// FLASH_ENCRYPTION.ADDRESS +func (o *FLASH_ENCRYPTION_Type) SetADDRESS(value uint32) { + volatile.StoreUint32(&o.ADDRESS.Reg, volatile.LoadUint32(&o.ADDRESS.Reg)&^(0xff)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetADDRESS() uint32 { + return volatile.LoadUint32(&o.ADDRESS.Reg) & 0xff +} + +// FLASH_ENCRYPTION.DONE +func (o *FLASH_ENCRYPTION_Type) SetDONE_FLASH_DONE(value uint32) { + volatile.StoreUint32(&o.DONE.Reg, volatile.LoadUint32(&o.DONE.Reg)&^(0x1)|value) +} +func (o *FLASH_ENCRYPTION_Type) GetDONE_FLASH_DONE() uint32 { + return volatile.LoadUint32(&o.DONE.Reg) & 0x1 +} + +// FRC_TIMER Peripheral +type FRC_Type struct { + TIMER_LOAD volatile.Register32 // 0x0 + TIMER_COUNT volatile.Register32 // 0x4 + TIMER_CTRL volatile.Register32 // 0x8 + TIMER_INT volatile.Register32 // 0xC + TIMER_ALARM volatile.Register32 // 0x10 +} + +// FRC.TIMER_LOAD +func (o *FRC_Type) SetTIMER_LOAD_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER_LOAD.Reg, volatile.LoadUint32(&o.TIMER_LOAD.Reg)&^(0xff)|value) +} +func (o *FRC_Type) GetTIMER_LOAD_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER_LOAD.Reg) & 0xff +} + +// FRC.TIMER_COUNT +func (o *FRC_Type) SetTIMER_COUNT(value uint32) { + volatile.StoreUint32(&o.TIMER_COUNT.Reg, volatile.LoadUint32(&o.TIMER_COUNT.Reg)&^(0xff)|value) +} +func (o *FRC_Type) GetTIMER_COUNT() uint32 { + return volatile.LoadUint32(&o.TIMER_COUNT.Reg) & 0xff +} + +// FRC.TIMER_CTRL +func (o *FRC_Type) SetTIMER_CTRL_TIMER_PRESCALER(value uint32) { + volatile.StoreUint32(&o.TIMER_CTRL.Reg, volatile.LoadUint32(&o.TIMER_CTRL.Reg)&^(0x1fe)|value<<1) +} +func (o *FRC_Type) GetTIMER_CTRL_TIMER_PRESCALER() uint32 { + return (volatile.LoadUint32(&o.TIMER_CTRL.Reg) & 0x1fe) >> 1 +} + +// FRC.TIMER_INT +func (o *FRC_Type) SetTIMER_INT_CLR(value uint32) { + volatile.StoreUint32(&o.TIMER_INT.Reg, volatile.LoadUint32(&o.TIMER_INT.Reg)&^(0x1)|value) +} +func (o *FRC_Type) GetTIMER_INT_CLR() uint32 { + return volatile.LoadUint32(&o.TIMER_INT.Reg) & 0x1 +} + +// FRC.TIMER_ALARM +func (o *FRC_Type) SetTIMER_ALARM(value uint32) { + volatile.StoreUint32(&o.TIMER_ALARM.Reg, volatile.LoadUint32(&o.TIMER_ALARM.Reg)&^(0xff)|value) +} +func (o *FRC_Type) GetTIMER_ALARM() uint32 { + return volatile.LoadUint32(&o.TIMER_ALARM.Reg) & 0xff +} + +// General Purpose Input/Output +type GPIO_Type struct { + BT_SELECT volatile.Register32 // 0x0 + OUT volatile.Register32 // 0x4 + OUT_W1TS volatile.Register32 // 0x8 + OUT_W1TC volatile.Register32 // 0xC + OUT1 volatile.Register32 // 0x10 + OUT1_W1TS volatile.Register32 // 0x14 + OUT1_W1TC volatile.Register32 // 0x18 + SDIO_SELECT volatile.Register32 // 0x1C + ENABLE volatile.Register32 // 0x20 + ENABLE_W1TS volatile.Register32 // 0x24 + ENABLE_W1TC volatile.Register32 // 0x28 + ENABLE1 volatile.Register32 // 0x2C + ENABLE1_W1TS volatile.Register32 // 0x30 + ENABLE1_W1TC volatile.Register32 // 0x34 + STRAP volatile.Register32 // 0x38 + IN volatile.Register32 // 0x3C + IN1 volatile.Register32 // 0x40 + STATUS volatile.Register32 // 0x44 + STATUS_W1TS volatile.Register32 // 0x48 + STATUS_W1TC volatile.Register32 // 0x4C + STATUS1 volatile.Register32 // 0x50 + STATUS1_W1TS volatile.Register32 // 0x54 + STATUS1_W1TC volatile.Register32 // 0x58 + _ [4]byte + ACPU_INT volatile.Register32 // 0x60 + ACPU_NMI_INT volatile.Register32 // 0x64 + PCPU_INT volatile.Register32 // 0x68 + PCPU_NMI_INT volatile.Register32 // 0x6C + CPUSDIO_INT volatile.Register32 // 0x70 + ACPU_INT1 volatile.Register32 // 0x74 + ACPU_NMI_INT1 volatile.Register32 // 0x78 + PCPU_INT1 volatile.Register32 // 0x7C + PCPU_NMI_INT1 volatile.Register32 // 0x80 + CPUSDIO_INT1 volatile.Register32 // 0x84 + PIN0 volatile.Register32 // 0x88 + PIN1 volatile.Register32 // 0x8C + PIN2 volatile.Register32 // 0x90 + PIN3 volatile.Register32 // 0x94 + PIN4 volatile.Register32 // 0x98 + PIN5 volatile.Register32 // 0x9C + PIN6 volatile.Register32 // 0xA0 + PIN7 volatile.Register32 // 0xA4 + PIN8 volatile.Register32 // 0xA8 + PIN9 volatile.Register32 // 0xAC + PIN10 volatile.Register32 // 0xB0 + PIN11 volatile.Register32 // 0xB4 + PIN12 volatile.Register32 // 0xB8 + PIN13 volatile.Register32 // 0xBC + PIN14 volatile.Register32 // 0xC0 + PIN15 volatile.Register32 // 0xC4 + PIN16 volatile.Register32 // 0xC8 + PIN17 volatile.Register32 // 0xCC + PIN18 volatile.Register32 // 0xD0 + PIN19 volatile.Register32 // 0xD4 + PIN20 volatile.Register32 // 0xD8 + PIN21 volatile.Register32 // 0xDC + PIN22 volatile.Register32 // 0xE0 + PIN23 volatile.Register32 // 0xE4 + PIN24 volatile.Register32 // 0xE8 + PIN25 volatile.Register32 // 0xEC + PIN26 volatile.Register32 // 0xF0 + PIN27 volatile.Register32 // 0xF4 + PIN28 volatile.Register32 // 0xF8 + PIN29 volatile.Register32 // 0xFC + PIN30 volatile.Register32 // 0x100 + PIN31 volatile.Register32 // 0x104 + PIN32 volatile.Register32 // 0x108 + PIN33 volatile.Register32 // 0x10C + PIN34 volatile.Register32 // 0x110 + PIN35 volatile.Register32 // 0x114 + PIN36 volatile.Register32 // 0x118 + PIN37 volatile.Register32 // 0x11C + PIN38 volatile.Register32 // 0x120 + PIN39 volatile.Register32 // 0x124 + CALI_CONF volatile.Register32 // 0x128 + CALI_DATA volatile.Register32 // 0x12C + FUNC0_IN_SEL_CFG volatile.Register32 // 0x130 + FUNC1_IN_SEL_CFG volatile.Register32 // 0x134 + FUNC2_IN_SEL_CFG volatile.Register32 // 0x138 + FUNC3_IN_SEL_CFG volatile.Register32 // 0x13C + FUNC4_IN_SEL_CFG volatile.Register32 // 0x140 + FUNC5_IN_SEL_CFG volatile.Register32 // 0x144 + FUNC6_IN_SEL_CFG volatile.Register32 // 0x148 + FUNC7_IN_SEL_CFG volatile.Register32 // 0x14C + FUNC8_IN_SEL_CFG volatile.Register32 // 0x150 + FUNC9_IN_SEL_CFG volatile.Register32 // 0x154 + FUNC10_IN_SEL_CFG volatile.Register32 // 0x158 + FUNC11_IN_SEL_CFG volatile.Register32 // 0x15C + FUNC12_IN_SEL_CFG volatile.Register32 // 0x160 + FUNC13_IN_SEL_CFG volatile.Register32 // 0x164 + FUNC14_IN_SEL_CFG volatile.Register32 // 0x168 + FUNC15_IN_SEL_CFG volatile.Register32 // 0x16C + FUNC16_IN_SEL_CFG volatile.Register32 // 0x170 + FUNC17_IN_SEL_CFG volatile.Register32 // 0x174 + FUNC18_IN_SEL_CFG volatile.Register32 // 0x178 + FUNC19_IN_SEL_CFG volatile.Register32 // 0x17C + FUNC20_IN_SEL_CFG volatile.Register32 // 0x180 + FUNC21_IN_SEL_CFG volatile.Register32 // 0x184 + FUNC22_IN_SEL_CFG volatile.Register32 // 0x188 + FUNC23_IN_SEL_CFG volatile.Register32 // 0x18C + FUNC24_IN_SEL_CFG volatile.Register32 // 0x190 + FUNC25_IN_SEL_CFG volatile.Register32 // 0x194 + FUNC26_IN_SEL_CFG volatile.Register32 // 0x198 + FUNC27_IN_SEL_CFG volatile.Register32 // 0x19C + FUNC28_IN_SEL_CFG volatile.Register32 // 0x1A0 + FUNC29_IN_SEL_CFG volatile.Register32 // 0x1A4 + FUNC30_IN_SEL_CFG volatile.Register32 // 0x1A8 + FUNC31_IN_SEL_CFG volatile.Register32 // 0x1AC + FUNC32_IN_SEL_CFG volatile.Register32 // 0x1B0 + FUNC33_IN_SEL_CFG volatile.Register32 // 0x1B4 + FUNC34_IN_SEL_CFG volatile.Register32 // 0x1B8 + FUNC35_IN_SEL_CFG volatile.Register32 // 0x1BC + FUNC36_IN_SEL_CFG volatile.Register32 // 0x1C0 + FUNC37_IN_SEL_CFG volatile.Register32 // 0x1C4 + FUNC38_IN_SEL_CFG volatile.Register32 // 0x1C8 + FUNC39_IN_SEL_CFG volatile.Register32 // 0x1CC + FUNC40_IN_SEL_CFG volatile.Register32 // 0x1D0 + FUNC41_IN_SEL_CFG volatile.Register32 // 0x1D4 + FUNC42_IN_SEL_CFG volatile.Register32 // 0x1D8 + FUNC43_IN_SEL_CFG volatile.Register32 // 0x1DC + FUNC44_IN_SEL_CFG volatile.Register32 // 0x1E0 + FUNC45_IN_SEL_CFG volatile.Register32 // 0x1E4 + FUNC46_IN_SEL_CFG volatile.Register32 // 0x1E8 + FUNC47_IN_SEL_CFG volatile.Register32 // 0x1EC + FUNC48_IN_SEL_CFG volatile.Register32 // 0x1F0 + FUNC49_IN_SEL_CFG volatile.Register32 // 0x1F4 + FUNC50_IN_SEL_CFG volatile.Register32 // 0x1F8 + FUNC51_IN_SEL_CFG volatile.Register32 // 0x1FC + FUNC52_IN_SEL_CFG volatile.Register32 // 0x200 + FUNC53_IN_SEL_CFG volatile.Register32 // 0x204 + FUNC54_IN_SEL_CFG volatile.Register32 // 0x208 + FUNC55_IN_SEL_CFG volatile.Register32 // 0x20C + FUNC56_IN_SEL_CFG volatile.Register32 // 0x210 + FUNC57_IN_SEL_CFG volatile.Register32 // 0x214 + FUNC58_IN_SEL_CFG volatile.Register32 // 0x218 + FUNC59_IN_SEL_CFG volatile.Register32 // 0x21C + FUNC60_IN_SEL_CFG volatile.Register32 // 0x220 + FUNC61_IN_SEL_CFG volatile.Register32 // 0x224 + FUNC62_IN_SEL_CFG volatile.Register32 // 0x228 + FUNC63_IN_SEL_CFG volatile.Register32 // 0x22C + FUNC64_IN_SEL_CFG volatile.Register32 // 0x230 + FUNC65_IN_SEL_CFG volatile.Register32 // 0x234 + FUNC66_IN_SEL_CFG volatile.Register32 // 0x238 + FUNC67_IN_SEL_CFG volatile.Register32 // 0x23C + FUNC68_IN_SEL_CFG volatile.Register32 // 0x240 + FUNC69_IN_SEL_CFG volatile.Register32 // 0x244 + FUNC70_IN_SEL_CFG volatile.Register32 // 0x248 + FUNC71_IN_SEL_CFG volatile.Register32 // 0x24C + FUNC72_IN_SEL_CFG volatile.Register32 // 0x250 + FUNC73_IN_SEL_CFG volatile.Register32 // 0x254 + FUNC74_IN_SEL_CFG volatile.Register32 // 0x258 + FUNC75_IN_SEL_CFG volatile.Register32 // 0x25C + FUNC76_IN_SEL_CFG volatile.Register32 // 0x260 + FUNC77_IN_SEL_CFG volatile.Register32 // 0x264 + FUNC78_IN_SEL_CFG volatile.Register32 // 0x268 + FUNC79_IN_SEL_CFG volatile.Register32 // 0x26C + FUNC80_IN_SEL_CFG volatile.Register32 // 0x270 + FUNC81_IN_SEL_CFG volatile.Register32 // 0x274 + FUNC82_IN_SEL_CFG volatile.Register32 // 0x278 + FUNC83_IN_SEL_CFG volatile.Register32 // 0x27C + FUNC84_IN_SEL_CFG volatile.Register32 // 0x280 + FUNC85_IN_SEL_CFG volatile.Register32 // 0x284 + FUNC86_IN_SEL_CFG volatile.Register32 // 0x288 + FUNC87_IN_SEL_CFG volatile.Register32 // 0x28C + FUNC88_IN_SEL_CFG volatile.Register32 // 0x290 + FUNC89_IN_SEL_CFG volatile.Register32 // 0x294 + FUNC90_IN_SEL_CFG volatile.Register32 // 0x298 + FUNC91_IN_SEL_CFG volatile.Register32 // 0x29C + FUNC92_IN_SEL_CFG volatile.Register32 // 0x2A0 + FUNC93_IN_SEL_CFG volatile.Register32 // 0x2A4 + FUNC94_IN_SEL_CFG volatile.Register32 // 0x2A8 + FUNC95_IN_SEL_CFG volatile.Register32 // 0x2AC + FUNC96_IN_SEL_CFG volatile.Register32 // 0x2B0 + FUNC97_IN_SEL_CFG volatile.Register32 // 0x2B4 + FUNC98_IN_SEL_CFG volatile.Register32 // 0x2B8 + FUNC99_IN_SEL_CFG volatile.Register32 // 0x2BC + FUNC100_IN_SEL_CFG volatile.Register32 // 0x2C0 + FUNC101_IN_SEL_CFG volatile.Register32 // 0x2C4 + FUNC102_IN_SEL_CFG volatile.Register32 // 0x2C8 + FUNC103_IN_SEL_CFG volatile.Register32 // 0x2CC + FUNC104_IN_SEL_CFG volatile.Register32 // 0x2D0 + FUNC105_IN_SEL_CFG volatile.Register32 // 0x2D4 + FUNC106_IN_SEL_CFG volatile.Register32 // 0x2D8 + FUNC107_IN_SEL_CFG volatile.Register32 // 0x2DC + FUNC108_IN_SEL_CFG volatile.Register32 // 0x2E0 + FUNC109_IN_SEL_CFG volatile.Register32 // 0x2E4 + FUNC110_IN_SEL_CFG volatile.Register32 // 0x2E8 + FUNC111_IN_SEL_CFG volatile.Register32 // 0x2EC + FUNC112_IN_SEL_CFG volatile.Register32 // 0x2F0 + FUNC113_IN_SEL_CFG volatile.Register32 // 0x2F4 + FUNC114_IN_SEL_CFG volatile.Register32 // 0x2F8 + FUNC115_IN_SEL_CFG volatile.Register32 // 0x2FC + FUNC116_IN_SEL_CFG volatile.Register32 // 0x300 + FUNC117_IN_SEL_CFG volatile.Register32 // 0x304 + FUNC118_IN_SEL_CFG volatile.Register32 // 0x308 + FUNC119_IN_SEL_CFG volatile.Register32 // 0x30C + FUNC120_IN_SEL_CFG volatile.Register32 // 0x310 + FUNC121_IN_SEL_CFG volatile.Register32 // 0x314 + FUNC122_IN_SEL_CFG volatile.Register32 // 0x318 + FUNC123_IN_SEL_CFG volatile.Register32 // 0x31C + FUNC124_IN_SEL_CFG volatile.Register32 // 0x320 + FUNC125_IN_SEL_CFG volatile.Register32 // 0x324 + FUNC126_IN_SEL_CFG volatile.Register32 // 0x328 + FUNC127_IN_SEL_CFG volatile.Register32 // 0x32C + FUNC128_IN_SEL_CFG volatile.Register32 // 0x330 + FUNC129_IN_SEL_CFG volatile.Register32 // 0x334 + FUNC130_IN_SEL_CFG volatile.Register32 // 0x338 + FUNC131_IN_SEL_CFG volatile.Register32 // 0x33C + FUNC132_IN_SEL_CFG volatile.Register32 // 0x340 + FUNC133_IN_SEL_CFG volatile.Register32 // 0x344 + FUNC134_IN_SEL_CFG volatile.Register32 // 0x348 + FUNC135_IN_SEL_CFG volatile.Register32 // 0x34C + FUNC136_IN_SEL_CFG volatile.Register32 // 0x350 + FUNC137_IN_SEL_CFG volatile.Register32 // 0x354 + FUNC138_IN_SEL_CFG volatile.Register32 // 0x358 + FUNC139_IN_SEL_CFG volatile.Register32 // 0x35C + FUNC140_IN_SEL_CFG volatile.Register32 // 0x360 + FUNC141_IN_SEL_CFG volatile.Register32 // 0x364 + FUNC142_IN_SEL_CFG volatile.Register32 // 0x368 + FUNC143_IN_SEL_CFG volatile.Register32 // 0x36C + FUNC144_IN_SEL_CFG volatile.Register32 // 0x370 + FUNC145_IN_SEL_CFG volatile.Register32 // 0x374 + FUNC146_IN_SEL_CFG volatile.Register32 // 0x378 + FUNC147_IN_SEL_CFG volatile.Register32 // 0x37C + FUNC148_IN_SEL_CFG volatile.Register32 // 0x380 + FUNC149_IN_SEL_CFG volatile.Register32 // 0x384 + FUNC150_IN_SEL_CFG volatile.Register32 // 0x388 + FUNC151_IN_SEL_CFG volatile.Register32 // 0x38C + FUNC152_IN_SEL_CFG volatile.Register32 // 0x390 + FUNC153_IN_SEL_CFG volatile.Register32 // 0x394 + FUNC154_IN_SEL_CFG volatile.Register32 // 0x398 + FUNC155_IN_SEL_CFG volatile.Register32 // 0x39C + FUNC156_IN_SEL_CFG volatile.Register32 // 0x3A0 + FUNC157_IN_SEL_CFG volatile.Register32 // 0x3A4 + FUNC158_IN_SEL_CFG volatile.Register32 // 0x3A8 + FUNC159_IN_SEL_CFG volatile.Register32 // 0x3AC + FUNC160_IN_SEL_CFG volatile.Register32 // 0x3B0 + FUNC161_IN_SEL_CFG volatile.Register32 // 0x3B4 + FUNC162_IN_SEL_CFG volatile.Register32 // 0x3B8 + FUNC163_IN_SEL_CFG volatile.Register32 // 0x3BC + FUNC164_IN_SEL_CFG volatile.Register32 // 0x3C0 + FUNC165_IN_SEL_CFG volatile.Register32 // 0x3C4 + FUNC166_IN_SEL_CFG volatile.Register32 // 0x3C8 + FUNC167_IN_SEL_CFG volatile.Register32 // 0x3CC + FUNC168_IN_SEL_CFG volatile.Register32 // 0x3D0 + FUNC169_IN_SEL_CFG volatile.Register32 // 0x3D4 + FUNC170_IN_SEL_CFG volatile.Register32 // 0x3D8 + FUNC171_IN_SEL_CFG volatile.Register32 // 0x3DC + FUNC172_IN_SEL_CFG volatile.Register32 // 0x3E0 + FUNC173_IN_SEL_CFG volatile.Register32 // 0x3E4 + FUNC174_IN_SEL_CFG volatile.Register32 // 0x3E8 + FUNC175_IN_SEL_CFG volatile.Register32 // 0x3EC + FUNC176_IN_SEL_CFG volatile.Register32 // 0x3F0 + FUNC177_IN_SEL_CFG volatile.Register32 // 0x3F4 + FUNC178_IN_SEL_CFG volatile.Register32 // 0x3F8 + FUNC179_IN_SEL_CFG volatile.Register32 // 0x3FC + FUNC180_IN_SEL_CFG volatile.Register32 // 0x400 + FUNC181_IN_SEL_CFG volatile.Register32 // 0x404 + FUNC182_IN_SEL_CFG volatile.Register32 // 0x408 + FUNC183_IN_SEL_CFG volatile.Register32 // 0x40C + FUNC184_IN_SEL_CFG volatile.Register32 // 0x410 + FUNC185_IN_SEL_CFG volatile.Register32 // 0x414 + FUNC186_IN_SEL_CFG volatile.Register32 // 0x418 + FUNC187_IN_SEL_CFG volatile.Register32 // 0x41C + FUNC188_IN_SEL_CFG volatile.Register32 // 0x420 + FUNC189_IN_SEL_CFG volatile.Register32 // 0x424 + FUNC190_IN_SEL_CFG volatile.Register32 // 0x428 + FUNC191_IN_SEL_CFG volatile.Register32 // 0x42C + FUNC192_IN_SEL_CFG volatile.Register32 // 0x430 + FUNC193_IN_SEL_CFG volatile.Register32 // 0x434 + FUNC194_IN_SEL_CFG volatile.Register32 // 0x438 + FUNC195_IN_SEL_CFG volatile.Register32 // 0x43C + FUNC196_IN_SEL_CFG volatile.Register32 // 0x440 + FUNC197_IN_SEL_CFG volatile.Register32 // 0x444 + FUNC198_IN_SEL_CFG volatile.Register32 // 0x448 + FUNC199_IN_SEL_CFG volatile.Register32 // 0x44C + FUNC200_IN_SEL_CFG volatile.Register32 // 0x450 + FUNC201_IN_SEL_CFG volatile.Register32 // 0x454 + FUNC202_IN_SEL_CFG volatile.Register32 // 0x458 + FUNC203_IN_SEL_CFG volatile.Register32 // 0x45C + FUNC204_IN_SEL_CFG volatile.Register32 // 0x460 + FUNC205_IN_SEL_CFG volatile.Register32 // 0x464 + FUNC206_IN_SEL_CFG volatile.Register32 // 0x468 + FUNC207_IN_SEL_CFG volatile.Register32 // 0x46C + FUNC208_IN_SEL_CFG volatile.Register32 // 0x470 + FUNC209_IN_SEL_CFG volatile.Register32 // 0x474 + FUNC210_IN_SEL_CFG volatile.Register32 // 0x478 + FUNC211_IN_SEL_CFG volatile.Register32 // 0x47C + FUNC212_IN_SEL_CFG volatile.Register32 // 0x480 + FUNC213_IN_SEL_CFG volatile.Register32 // 0x484 + FUNC214_IN_SEL_CFG volatile.Register32 // 0x488 + FUNC215_IN_SEL_CFG volatile.Register32 // 0x48C + FUNC216_IN_SEL_CFG volatile.Register32 // 0x490 + FUNC217_IN_SEL_CFG volatile.Register32 // 0x494 + FUNC218_IN_SEL_CFG volatile.Register32 // 0x498 + FUNC219_IN_SEL_CFG volatile.Register32 // 0x49C + FUNC220_IN_SEL_CFG volatile.Register32 // 0x4A0 + FUNC221_IN_SEL_CFG volatile.Register32 // 0x4A4 + FUNC222_IN_SEL_CFG volatile.Register32 // 0x4A8 + FUNC223_IN_SEL_CFG volatile.Register32 // 0x4AC + FUNC224_IN_SEL_CFG volatile.Register32 // 0x4B0 + FUNC225_IN_SEL_CFG volatile.Register32 // 0x4B4 + FUNC226_IN_SEL_CFG volatile.Register32 // 0x4B8 + FUNC227_IN_SEL_CFG volatile.Register32 // 0x4BC + FUNC228_IN_SEL_CFG volatile.Register32 // 0x4C0 + FUNC229_IN_SEL_CFG volatile.Register32 // 0x4C4 + FUNC230_IN_SEL_CFG volatile.Register32 // 0x4C8 + FUNC231_IN_SEL_CFG volatile.Register32 // 0x4CC + FUNC232_IN_SEL_CFG volatile.Register32 // 0x4D0 + FUNC233_IN_SEL_CFG volatile.Register32 // 0x4D4 + FUNC234_IN_SEL_CFG volatile.Register32 // 0x4D8 + FUNC235_IN_SEL_CFG volatile.Register32 // 0x4DC + FUNC236_IN_SEL_CFG volatile.Register32 // 0x4E0 + FUNC237_IN_SEL_CFG volatile.Register32 // 0x4E4 + FUNC238_IN_SEL_CFG volatile.Register32 // 0x4E8 + FUNC239_IN_SEL_CFG volatile.Register32 // 0x4EC + FUNC240_IN_SEL_CFG volatile.Register32 // 0x4F0 + FUNC241_IN_SEL_CFG volatile.Register32 // 0x4F4 + FUNC242_IN_SEL_CFG volatile.Register32 // 0x4F8 + FUNC243_IN_SEL_CFG volatile.Register32 // 0x4FC + FUNC244_IN_SEL_CFG volatile.Register32 // 0x500 + FUNC245_IN_SEL_CFG volatile.Register32 // 0x504 + FUNC246_IN_SEL_CFG volatile.Register32 // 0x508 + FUNC247_IN_SEL_CFG volatile.Register32 // 0x50C + FUNC248_IN_SEL_CFG volatile.Register32 // 0x510 + FUNC249_IN_SEL_CFG volatile.Register32 // 0x514 + FUNC250_IN_SEL_CFG volatile.Register32 // 0x518 + FUNC251_IN_SEL_CFG volatile.Register32 // 0x51C + FUNC252_IN_SEL_CFG volatile.Register32 // 0x520 + FUNC253_IN_SEL_CFG volatile.Register32 // 0x524 + FUNC254_IN_SEL_CFG volatile.Register32 // 0x528 + FUNC255_IN_SEL_CFG volatile.Register32 // 0x52C + FUNC0_OUT_SEL_CFG volatile.Register32 // 0x530 + FUNC1_OUT_SEL_CFG volatile.Register32 // 0x534 + FUNC2_OUT_SEL_CFG volatile.Register32 // 0x538 + FUNC3_OUT_SEL_CFG volatile.Register32 // 0x53C + FUNC4_OUT_SEL_CFG volatile.Register32 // 0x540 + FUNC5_OUT_SEL_CFG volatile.Register32 // 0x544 + FUNC6_OUT_SEL_CFG volatile.Register32 // 0x548 + FUNC7_OUT_SEL_CFG volatile.Register32 // 0x54C + FUNC8_OUT_SEL_CFG volatile.Register32 // 0x550 + FUNC9_OUT_SEL_CFG volatile.Register32 // 0x554 + FUNC10_OUT_SEL_CFG volatile.Register32 // 0x558 + FUNC11_OUT_SEL_CFG volatile.Register32 // 0x55C + FUNC12_OUT_SEL_CFG volatile.Register32 // 0x560 + FUNC13_OUT_SEL_CFG volatile.Register32 // 0x564 + FUNC14_OUT_SEL_CFG volatile.Register32 // 0x568 + FUNC15_OUT_SEL_CFG volatile.Register32 // 0x56C + FUNC16_OUT_SEL_CFG volatile.Register32 // 0x570 + FUNC17_OUT_SEL_CFG volatile.Register32 // 0x574 + FUNC18_OUT_SEL_CFG volatile.Register32 // 0x578 + FUNC19_OUT_SEL_CFG volatile.Register32 // 0x57C + FUNC20_OUT_SEL_CFG volatile.Register32 // 0x580 + FUNC21_OUT_SEL_CFG volatile.Register32 // 0x584 + FUNC22_OUT_SEL_CFG volatile.Register32 // 0x588 + FUNC23_OUT_SEL_CFG volatile.Register32 // 0x58C + FUNC24_OUT_SEL_CFG volatile.Register32 // 0x590 + FUNC25_OUT_SEL_CFG volatile.Register32 // 0x594 + FUNC26_OUT_SEL_CFG volatile.Register32 // 0x598 + FUNC27_OUT_SEL_CFG volatile.Register32 // 0x59C + FUNC28_OUT_SEL_CFG volatile.Register32 // 0x5A0 + FUNC29_OUT_SEL_CFG volatile.Register32 // 0x5A4 + FUNC30_OUT_SEL_CFG volatile.Register32 // 0x5A8 + FUNC31_OUT_SEL_CFG volatile.Register32 // 0x5AC + FUNC32_OUT_SEL_CFG volatile.Register32 // 0x5B0 + FUNC33_OUT_SEL_CFG volatile.Register32 // 0x5B4 + FUNC34_OUT_SEL_CFG volatile.Register32 // 0x5B8 + FUNC35_OUT_SEL_CFG volatile.Register32 // 0x5BC + FUNC36_OUT_SEL_CFG volatile.Register32 // 0x5C0 + FUNC37_OUT_SEL_CFG volatile.Register32 // 0x5C4 + FUNC38_OUT_SEL_CFG volatile.Register32 // 0x5C8 + FUNC39_OUT_SEL_CFG volatile.Register32 // 0x5CC +} + +// GPIO.BT_SELECT +func (o *GPIO_Type) SetBT_SELECT(value uint32) { + volatile.StoreUint32(&o.BT_SELECT.Reg, value) +} +func (o *GPIO_Type) GetBT_SELECT() uint32 { + return volatile.LoadUint32(&o.BT_SELECT.Reg) +} + +// GPIO.OUT +func (o *GPIO_Type) SetOUT(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, value) +} +func (o *GPIO_Type) GetOUT() uint32 { + return volatile.LoadUint32(&o.OUT.Reg) +} + +// GPIO.OUT_W1TS +func (o *GPIO_Type) SetOUT_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_W1TS.Reg) +} + +// GPIO.OUT_W1TC +func (o *GPIO_Type) SetOUT_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_W1TC.Reg) +} + +// GPIO.OUT1 +func (o *GPIO_Type) SetOUT1_DATA(value uint32) { + volatile.StoreUint32(&o.OUT1.Reg, volatile.LoadUint32(&o.OUT1.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetOUT1_DATA() uint32 { + return volatile.LoadUint32(&o.OUT1.Reg) & 0xff +} + +// GPIO.OUT1_W1TS +func (o *GPIO_Type) SetOUT1_W1TS_OUT1_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TS.Reg, volatile.LoadUint32(&o.OUT1_W1TS.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetOUT1_W1TS_OUT1_DATA_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TS.Reg) & 0xff +} + +// GPIO.OUT1_W1TC +func (o *GPIO_Type) SetOUT1_W1TC_OUT1_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TC.Reg, volatile.LoadUint32(&o.OUT1_W1TC.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetOUT1_W1TC_OUT1_DATA_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TC.Reg) & 0xff +} + +// GPIO.SDIO_SELECT +func (o *GPIO_Type) SetSDIO_SELECT_SDIO_SEL(value uint32) { + volatile.StoreUint32(&o.SDIO_SELECT.Reg, volatile.LoadUint32(&o.SDIO_SELECT.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSDIO_SELECT_SDIO_SEL() uint32 { + return volatile.LoadUint32(&o.SDIO_SELECT.Reg) & 0xff +} + +// GPIO.ENABLE +func (o *GPIO_Type) SetENABLE(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, value) +} +func (o *GPIO_Type) GetENABLE() uint32 { + return volatile.LoadUint32(&o.ENABLE.Reg) +} + +// GPIO.ENABLE_W1TS +func (o *GPIO_Type) SetENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) +} + +// GPIO.ENABLE_W1TC +func (o *GPIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) +} + +// GPIO.ENABLE1 +func (o *GPIO_Type) SetENABLE1_DATA(value uint32) { + volatile.StoreUint32(&o.ENABLE1.Reg, volatile.LoadUint32(&o.ENABLE1.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetENABLE1_DATA() uint32 { + return volatile.LoadUint32(&o.ENABLE1.Reg) & 0xff +} + +// GPIO.ENABLE1_W1TS +func (o *GPIO_Type) SetENABLE1_W1TS_ENABLE1_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TS.Reg, volatile.LoadUint32(&o.ENABLE1_W1TS.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TS_ENABLE1_DATA_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TS.Reg) & 0xff +} + +// GPIO.ENABLE1_W1TC +func (o *GPIO_Type) SetENABLE1_W1TC_ENABLE1_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TC.Reg, volatile.LoadUint32(&o.ENABLE1_W1TC.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TC_ENABLE1_DATA_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TC.Reg) & 0xff +} + +// GPIO.STRAP +func (o *GPIO_Type) SetSTRAP_STRAPPING(value uint32) { + volatile.StoreUint32(&o.STRAP.Reg, volatile.LoadUint32(&o.STRAP.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetSTRAP_STRAPPING() uint32 { + return volatile.LoadUint32(&o.STRAP.Reg) & 0xffff +} + +// GPIO.IN +func (o *GPIO_Type) SetIN(value uint32) { + volatile.StoreUint32(&o.IN.Reg, value) +} +func (o *GPIO_Type) GetIN() uint32 { + return volatile.LoadUint32(&o.IN.Reg) +} + +// GPIO.IN1 +func (o *GPIO_Type) SetIN1_DATA_NEXT(value uint32) { + volatile.StoreUint32(&o.IN1.Reg, volatile.LoadUint32(&o.IN1.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetIN1_DATA_NEXT() uint32 { + return volatile.LoadUint32(&o.IN1.Reg) & 0xff +} + +// GPIO.STATUS +func (o *GPIO_Type) SetSTATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) +} + +// GPIO.STATUS_W1TS +func (o *GPIO_Type) SetSTATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) +} + +// GPIO.STATUS_W1TC +func (o *GPIO_Type) SetSTATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) +} + +// GPIO.STATUS1 +func (o *GPIO_Type) SetSTATUS1_INT(value uint32) { + volatile.StoreUint32(&o.STATUS1.Reg, volatile.LoadUint32(&o.STATUS1.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSTATUS1_INT() uint32 { + return volatile.LoadUint32(&o.STATUS1.Reg) & 0xff +} + +// GPIO.STATUS1_W1TS +func (o *GPIO_Type) SetSTATUS1_W1TS_STATUS1_INT_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TS.Reg, volatile.LoadUint32(&o.STATUS1_W1TS.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TS_STATUS1_INT_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TS.Reg) & 0xff +} + +// GPIO.STATUS1_W1TC +func (o *GPIO_Type) SetSTATUS1_W1TC_STATUS1_INT_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TC.Reg, volatile.LoadUint32(&o.STATUS1_W1TC.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TC_STATUS1_INT_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TC.Reg) & 0xff +} + +// GPIO.ACPU_INT +func (o *GPIO_Type) SetACPU_INT(value uint32) { + volatile.StoreUint32(&o.ACPU_INT.Reg, value) +} +func (o *GPIO_Type) GetACPU_INT() uint32 { + return volatile.LoadUint32(&o.ACPU_INT.Reg) +} + +// GPIO.ACPU_NMI_INT +func (o *GPIO_Type) SetACPU_NMI_INT(value uint32) { + volatile.StoreUint32(&o.ACPU_NMI_INT.Reg, value) +} +func (o *GPIO_Type) GetACPU_NMI_INT() uint32 { + return volatile.LoadUint32(&o.ACPU_NMI_INT.Reg) +} + +// GPIO.PCPU_INT +func (o *GPIO_Type) SetPCPU_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_INT.Reg) +} + +// GPIO.PCPU_NMI_INT +func (o *GPIO_Type) SetPCPU_NMI_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT.Reg) +} + +// GPIO.CPUSDIO_INT +func (o *GPIO_Type) SetCPUSDIO_INT(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT.Reg, value) +} +func (o *GPIO_Type) GetCPUSDIO_INT() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT.Reg) +} + +// GPIO.ACPU_INT1 +func (o *GPIO_Type) SetACPU_INT1_APPCPU_INT_H(value uint32) { + volatile.StoreUint32(&o.ACPU_INT1.Reg, volatile.LoadUint32(&o.ACPU_INT1.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetACPU_INT1_APPCPU_INT_H() uint32 { + return volatile.LoadUint32(&o.ACPU_INT1.Reg) & 0xff +} + +// GPIO.ACPU_NMI_INT1 +func (o *GPIO_Type) SetACPU_NMI_INT1_APPCPU_NMI_INT_H(value uint32) { + volatile.StoreUint32(&o.ACPU_NMI_INT1.Reg, volatile.LoadUint32(&o.ACPU_NMI_INT1.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetACPU_NMI_INT1_APPCPU_NMI_INT_H() uint32 { + return volatile.LoadUint32(&o.ACPU_NMI_INT1.Reg) & 0xff +} + +// GPIO.PCPU_INT1 +func (o *GPIO_Type) SetPCPU_INT1_PROCPU_INT_H(value uint32) { + volatile.StoreUint32(&o.PCPU_INT1.Reg, volatile.LoadUint32(&o.PCPU_INT1.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetPCPU_INT1_PROCPU_INT_H() uint32 { + return volatile.LoadUint32(&o.PCPU_INT1.Reg) & 0xff +} + +// GPIO.PCPU_NMI_INT1 +func (o *GPIO_Type) SetPCPU_NMI_INT1_PROCPU_NMI_INT_H(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT1.Reg, volatile.LoadUint32(&o.PCPU_NMI_INT1.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT1_PROCPU_NMI_INT_H() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT1.Reg) & 0xff +} + +// GPIO.CPUSDIO_INT1 +func (o *GPIO_Type) SetCPUSDIO_INT1_SDIO_INT_H(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT1.Reg, volatile.LoadUint32(&o.CPUSDIO_INT1.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetCPUSDIO_INT1_SDIO_INT_H() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT1.Reg) & 0xff +} +func (o *GPIO_Type) SetCPUSDIO_INT1_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT1.Reg, volatile.LoadUint32(&o.CPUSDIO_INT1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetCPUSDIO_INT1_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.CPUSDIO_INT1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetCPUSDIO_INT1_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT1.Reg, volatile.LoadUint32(&o.CPUSDIO_INT1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetCPUSDIO_INT1_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.CPUSDIO_INT1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetCPUSDIO_INT1_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT1.Reg, volatile.LoadUint32(&o.CPUSDIO_INT1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetCPUSDIO_INT1_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CPUSDIO_INT1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetCPUSDIO_INT1_PIN_CONFIG(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT1.Reg, volatile.LoadUint32(&o.CPUSDIO_INT1.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetCPUSDIO_INT1_PIN_CONFIG() uint32 { + return (volatile.LoadUint32(&o.CPUSDIO_INT1.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetCPUSDIO_INT1_PIN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT1.Reg, volatile.LoadUint32(&o.CPUSDIO_INT1.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetCPUSDIO_INT1_PIN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CPUSDIO_INT1.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN0 +func (o *GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN0_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN0_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN1 +func (o *GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN1_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN1_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN2 +func (o *GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN2_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN2_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN3 +func (o *GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN3_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN3_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN4 +func (o *GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN4_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN4_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN5 +func (o *GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN5_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN5_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN6 +func (o *GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN6_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN6_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN7 +func (o *GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN7_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN7_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN8 +func (o *GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN8_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN8_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN9 +func (o *GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN9_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN9_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN10 +func (o *GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN10_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN10_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN10_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN10_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN11 +func (o *GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN11_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN11_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN11_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN11_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN12 +func (o *GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN12_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN12_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN12_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN12_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN13 +func (o *GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN13_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN13_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN13_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN13_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN14 +func (o *GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN14_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN14_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN14_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN14_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN15 +func (o *GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN15_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN15_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN15_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN15_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN16 +func (o *GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN16_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN16_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN16_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN16_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN17 +func (o *GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN17_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN17_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN17_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN17_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN18 +func (o *GPIO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN18_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN18_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN18_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN18_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN19 +func (o *GPIO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN19_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN19_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN19_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN19_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN20 +func (o *GPIO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN20_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN20_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN20_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN20_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN21 +func (o *GPIO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN21_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN21_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN21_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN21_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN22 +func (o *GPIO_Type) SetPIN22_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN22_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN22_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN22_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN22_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN22_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN22_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN22_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN22_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN22_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN23 +func (o *GPIO_Type) SetPIN23_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN23_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN23_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN23_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN23_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN23_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN23_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN23_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN23_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN23_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN24 +func (o *GPIO_Type) SetPIN24_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN24_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN24_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN24_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN24_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN24_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN24_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN24_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN24_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN24_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN25 +func (o *GPIO_Type) SetPIN25_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN25_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN25_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN25_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN25_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN25_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN25_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN25_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN25_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN25_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN26 +func (o *GPIO_Type) SetPIN26_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN26_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN26_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN26_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN26_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN26_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN26_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN26_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN26_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN26_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN27 +func (o *GPIO_Type) SetPIN27_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN27_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN27_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN27_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN27_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN27_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN27_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN27_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN27_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN27_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN28 +func (o *GPIO_Type) SetPIN28_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN28_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN28_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN28_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN28_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN28_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN28_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN28_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN28_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN28_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN29 +func (o *GPIO_Type) SetPIN29_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN29_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN29_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN29_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN29_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN29_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN29_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN29_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN29_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN29_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN30 +func (o *GPIO_Type) SetPIN30_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN30_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN30_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN30_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN30_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN30_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN30_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN30_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN30_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN30_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN31 +func (o *GPIO_Type) SetPIN31_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN31_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN31_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN31_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN31_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN31_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN31_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN31_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN31_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN31_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN32 +func (o *GPIO_Type) SetPIN32_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN32_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN32_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN32_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN32_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN32_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN32_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN32_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN32_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN32_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN33 +func (o *GPIO_Type) SetPIN33_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN33_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN33_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN33_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN33_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN33_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN33_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN33_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN33_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN33_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN34 +func (o *GPIO_Type) SetPIN34_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN34_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN34_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN34_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN34_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN34_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN34_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN34_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN34_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN34_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN35 +func (o *GPIO_Type) SetPIN35_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN35_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN35_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN35_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN35_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN35_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN35_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN35_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN35_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN35_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN36 +func (o *GPIO_Type) SetPIN36_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN36_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN36_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN36_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN36_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN36_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN36_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN36_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN36_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN36_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN37 +func (o *GPIO_Type) SetPIN37_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN37_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN37_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN37_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN37_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN37_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN37_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN37_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN37_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN37_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN38 +func (o *GPIO_Type) SetPIN38_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN38_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN38_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN38_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN38_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN38_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN38_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN38_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN38_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN38_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN39 +func (o *GPIO_Type) SetPIN39_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN39_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN39_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN39_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN39_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN39_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN39_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN39_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN39_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN39_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x3e000) >> 13 +} + +// GPIO.CALI_CONF +func (o *GPIO_Type) SetCALI_CONF_CALI_RTC_MAX(value uint32) { + volatile.StoreUint32(&o.CALI_CONF.Reg, volatile.LoadUint32(&o.CALI_CONF.Reg)&^(0x3ff)|value) +} +func (o *GPIO_Type) GetCALI_CONF_CALI_RTC_MAX() uint32 { + return volatile.LoadUint32(&o.CALI_CONF.Reg) & 0x3ff +} +func (o *GPIO_Type) SetCALI_CONF_CALI_START(value uint32) { + volatile.StoreUint32(&o.CALI_CONF.Reg, volatile.LoadUint32(&o.CALI_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIO_Type) GetCALI_CONF_CALI_START() uint32 { + return (volatile.LoadUint32(&o.CALI_CONF.Reg) & 0x80000000) >> 31 +} + +// GPIO.CALI_DATA +func (o *GPIO_Type) SetCALI_DATA_CALI_VALUE_SYNC2(value uint32) { + volatile.StoreUint32(&o.CALI_DATA.Reg, volatile.LoadUint32(&o.CALI_DATA.Reg)&^(0xfffff)|value) +} +func (o *GPIO_Type) GetCALI_DATA_CALI_VALUE_SYNC2() uint32 { + return volatile.LoadUint32(&o.CALI_DATA.Reg) & 0xfffff +} +func (o *GPIO_Type) SetCALI_DATA_CALI_RDY_REAL(value uint32) { + volatile.StoreUint32(&o.CALI_DATA.Reg, volatile.LoadUint32(&o.CALI_DATA.Reg)&^(0x40000000)|value<<30) +} +func (o *GPIO_Type) GetCALI_DATA_CALI_RDY_REAL() uint32 { + return (volatile.LoadUint32(&o.CALI_DATA.Reg) & 0x40000000) >> 30 +} +func (o *GPIO_Type) SetCALI_DATA_CALI_RDY_SYNC2(value uint32) { + volatile.StoreUint32(&o.CALI_DATA.Reg, volatile.LoadUint32(&o.CALI_DATA.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIO_Type) GetCALI_DATA_CALI_RDY_SYNC2() uint32 { + return (volatile.LoadUint32(&o.CALI_DATA.Reg) & 0x80000000) >> 31 +} + +// GPIO.FUNC0_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC1_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC2_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC3_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC4_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC5_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC6_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC7_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC8_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC9_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC10_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC11_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC12_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC13_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC14_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC15_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC16_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC17_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC18_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC19_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC20_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC21_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC22_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC23_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC24_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC25_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC26_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC27_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC28_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC29_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC30_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC31_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC32_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC33_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC34_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC35_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC36_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC37_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC38_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC39_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC40_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC41_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC42_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC43_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC44_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC45_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC46_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC47_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC48_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC49_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC50_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC51_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC52_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC53_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC54_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC55_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC56_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC57_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC58_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC59_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC60_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC61_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC62_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC63_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC64_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC65_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC66_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC67_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC68_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC69_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC70_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC71_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC72_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC73_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC74_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC75_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC76_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC77_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC78_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC79_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC80_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC81_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC82_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC83_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC84_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC85_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC86_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC87_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC88_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC89_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC90_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC91_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC92_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC93_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC94_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC95_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC96_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC97_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC98_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC99_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC100_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC101_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC102_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC103_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC104_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC105_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC106_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC107_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC108_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC109_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC110_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC111_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC112_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC113_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC114_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC115_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC116_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC117_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC118_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC119_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC120_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC121_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC122_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC123_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC124_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC125_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC126_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC127_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC128_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC129_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC130_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC131_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC132_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC133_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC134_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC135_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC136_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC137_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC138_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC139_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC140_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC141_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC142_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC143_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC144_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC145_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC146_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC147_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC148_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC149_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC150_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC151_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC152_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC153_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC154_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC155_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC156_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC157_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC158_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC159_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC160_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC161_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC162_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC163_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC164_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC165_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC166_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC167_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC168_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC169_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC170_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC171_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC172_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC173_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC174_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC175_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC176_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC177_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC178_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC179_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC180_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC181_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC182_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC183_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC184_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC185_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC186_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC187_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC188_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC189_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC190_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC191_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC192_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC193_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC194_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC195_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC196_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC197_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC198_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC199_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC200_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC201_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC202_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC203_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC204_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC205_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC206_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC207_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC208_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC209_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC210_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC211_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC212_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC213_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC214_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC215_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC216_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC217_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC218_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC219_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC220_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC221_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC222_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC223_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC224_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC225_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC226_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC227_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC228_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC229_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC230_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC231_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC232_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC233_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC234_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC235_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC236_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC237_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC238_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC239_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC240_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC241_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC242_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC243_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC244_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC245_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC246_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC247_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC248_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC249_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC250_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC251_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC252_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC253_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC254_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC255_IN_SEL_CFG +func (o *GPIO_Type) SetFUNC255_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC255_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC255_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC255_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC255_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC255_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC255_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC255_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC255_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC0_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC1_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC2_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC3_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC4_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC5_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC6_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC7_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC8_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC9_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC10_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC11_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC12_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC13_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC14_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC15_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC16_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC17_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC18_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC19_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC20_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC21_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC22_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC23_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC24_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC25_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC26_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC27_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC28_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC29_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC30_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC31_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC32_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC33_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC34_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC35_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC36_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC37_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC38_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC39_OUT_SEL_CFG +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// Sigma-Delta Modulation +type GPIO_SIGMADELTA_Type struct { + SIGMADELTA0 volatile.Register32 // 0x0 + SIGMADELTA1 volatile.Register32 // 0x4 + SIGMADELTA2 volatile.Register32 // 0x8 + SIGMADELTA3 volatile.Register32 // 0xC + SIGMADELTA4 volatile.Register32 // 0x10 + SIGMADELTA5 volatile.Register32 // 0x14 + SIGMADELTA6 volatile.Register32 // 0x18 + SIGMADELTA7 volatile.Register32 // 0x1C + CG volatile.Register32 // 0x20 + MISC volatile.Register32 // 0x24 + VERSION volatile.Register32 // 0x28 +} + +// GPIO_SIGMADELTA.SIGMADELTA0 +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA0_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff)|value) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA0_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff +} +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA0_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff00)|value<<8) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA0_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff00) >> 8 +} + +// GPIO_SIGMADELTA.SIGMADELTA1 +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA1_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff)|value) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA1_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff +} +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA1_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff00)|value<<8) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA1_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff00) >> 8 +} + +// GPIO_SIGMADELTA.SIGMADELTA2 +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA2_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff)|value) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA2_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff +} +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA2_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff00)|value<<8) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA2_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff00) >> 8 +} + +// GPIO_SIGMADELTA.SIGMADELTA3 +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA3_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff)|value) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA3_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff +} +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA3_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff00)|value<<8) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA3_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff00) >> 8 +} + +// GPIO_SIGMADELTA.SIGMADELTA4 +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA4_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff)|value) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA4_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff +} +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA4_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff00)|value<<8) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA4_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff00) >> 8 +} + +// GPIO_SIGMADELTA.SIGMADELTA5 +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA5_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff)|value) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA5_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff +} +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA5_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff00)|value<<8) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA5_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff00) >> 8 +} + +// GPIO_SIGMADELTA.SIGMADELTA6 +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA6_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff)|value) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA6_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff +} +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA6_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff00)|value<<8) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA6_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff00) >> 8 +} + +// GPIO_SIGMADELTA.SIGMADELTA7 +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA7_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff)|value) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA7_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff +} +func (o *GPIO_SIGMADELTA_Type) SetSIGMADELTA7_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff00)|value<<8) +} +func (o *GPIO_SIGMADELTA_Type) GetSIGMADELTA7_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff00) >> 8 +} + +// GPIO_SIGMADELTA.CG +func (o *GPIO_SIGMADELTA_Type) SetCG_SD_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CG.Reg, volatile.LoadUint32(&o.CG.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIO_SIGMADELTA_Type) GetCG_SD_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CG.Reg) & 0x80000000) >> 31 +} + +// GPIO_SIGMADELTA.MISC +func (o *GPIO_SIGMADELTA_Type) SetMISC_SPI_SWAP(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIO_SIGMADELTA_Type) GetMISC_SPI_SWAP() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000000) >> 31 +} + +// GPIO_SIGMADELTA.VERSION +func (o *GPIO_SIGMADELTA_Type) SetVERSION_SD_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *GPIO_SIGMADELTA_Type) GetVERSION_SD_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// HINF Peripheral +type HINF_Type struct { + CFG_DATA0 volatile.Register32 // 0x0 + CFG_DATA1 volatile.Register32 // 0x4 + _ [20]byte + CFG_DATA7 volatile.Register32 // 0x1C + CIS_CONF0 volatile.Register32 // 0x20 + CIS_CONF1 volatile.Register32 // 0x24 + CIS_CONF2 volatile.Register32 // 0x28 + CIS_CONF3 volatile.Register32 // 0x2C + CIS_CONF4 volatile.Register32 // 0x30 + CIS_CONF5 volatile.Register32 // 0x34 + CIS_CONF6 volatile.Register32 // 0x38 + CIS_CONF7 volatile.Register32 // 0x3C + CFG_DATA16 volatile.Register32 // 0x40 + _ [184]byte + DATE volatile.Register32 // 0xFC +} + +// HINF.CFG_DATA0 +func (o *HINF_Type) SetCFG_DATA0_USER_ID_FN1(value uint32) { + volatile.StoreUint32(&o.CFG_DATA0.Reg, volatile.LoadUint32(&o.CFG_DATA0.Reg)&^(0xffff)|value) +} +func (o *HINF_Type) GetCFG_DATA0_USER_ID_FN1() uint32 { + return volatile.LoadUint32(&o.CFG_DATA0.Reg) & 0xffff +} +func (o *HINF_Type) SetCFG_DATA0_DEVICE_ID_FN1(value uint32) { + volatile.StoreUint32(&o.CFG_DATA0.Reg, volatile.LoadUint32(&o.CFG_DATA0.Reg)&^(0xffff0000)|value<<16) +} +func (o *HINF_Type) GetCFG_DATA0_DEVICE_ID_FN1() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA0.Reg) & 0xffff0000) >> 16 +} + +// HINF.CFG_DATA1 +func (o *HINF_Type) SetCFG_DATA1_SDIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x1)|value) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_ENABLE() uint32 { + return volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x1 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_IOREADY1(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x2)|value<<1) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_IOREADY1() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x2) >> 1 +} +func (o *HINF_Type) SetCFG_DATA1_HIGHSPEED_ENABLE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x4)|value<<2) +} +func (o *HINF_Type) GetCFG_DATA1_HIGHSPEED_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x4) >> 2 +} +func (o *HINF_Type) SetCFG_DATA1_HIGHSPEED_MODE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x8)|value<<3) +} +func (o *HINF_Type) GetCFG_DATA1_HIGHSPEED_MODE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x8) >> 3 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_CD_ENABLE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x10)|value<<4) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_CD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x10) >> 4 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_IOREADY2(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x20)|value<<5) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_IOREADY2() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x20) >> 5 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_INT_MASK(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x40)|value<<6) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_INT_MASK() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x40) >> 6 +} +func (o *HINF_Type) SetCFG_DATA1_IOENABLE2(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x80)|value<<7) +} +func (o *HINF_Type) GetCFG_DATA1_IOENABLE2() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x80) >> 7 +} +func (o *HINF_Type) SetCFG_DATA1_CD_DISABLE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x100)|value<<8) +} +func (o *HINF_Type) GetCFG_DATA1_CD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x100) >> 8 +} +func (o *HINF_Type) SetCFG_DATA1_FUNC1_EPS(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x200)|value<<9) +} +func (o *HINF_Type) GetCFG_DATA1_FUNC1_EPS() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x200) >> 9 +} +func (o *HINF_Type) SetCFG_DATA1_EMP(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x400)|value<<10) +} +func (o *HINF_Type) GetCFG_DATA1_EMP() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x400) >> 10 +} +func (o *HINF_Type) SetCFG_DATA1_IOENABLE1(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x800)|value<<11) +} +func (o *HINF_Type) GetCFG_DATA1_IOENABLE1() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x800) >> 11 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO20_CONF0(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0xf000)|value<<12) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO20_CONF0() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0xf000) >> 12 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_VER(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0xfff0000)|value<<16) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_VER() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0xfff0000) >> 16 +} +func (o *HINF_Type) SetCFG_DATA1_FUNC2_EPS(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x10000000)|value<<28) +} +func (o *HINF_Type) GetCFG_DATA1_FUNC2_EPS() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x10000000) >> 28 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO20_CONF1(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0xe0000000)|value<<29) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO20_CONF1() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0xe0000000) >> 29 +} + +// HINF.CFG_DATA7 +func (o *HINF_Type) SetCFG_DATA7_PIN_STATE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0xff)|value) +} +func (o *HINF_Type) GetCFG_DATA7_PIN_STATE() uint32 { + return volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0xff +} +func (o *HINF_Type) SetCFG_DATA7_CHIP_STATE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0xff00)|value<<8) +} +func (o *HINF_Type) GetCFG_DATA7_CHIP_STATE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0xff00) >> 8 +} +func (o *HINF_Type) SetCFG_DATA7_SDIO_RST(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x10000)|value<<16) +} +func (o *HINF_Type) GetCFG_DATA7_SDIO_RST() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x10000) >> 16 +} +func (o *HINF_Type) SetCFG_DATA7_SDIO_IOREADY0(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x20000)|value<<17) +} +func (o *HINF_Type) GetCFG_DATA7_SDIO_IOREADY0() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x20000) >> 17 +} + +// HINF.CIS_CONF0 +func (o *HINF_Type) SetCIS_CONF0(value uint32) { + volatile.StoreUint32(&o.CIS_CONF0.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF0() uint32 { + return volatile.LoadUint32(&o.CIS_CONF0.Reg) +} + +// HINF.CIS_CONF1 +func (o *HINF_Type) SetCIS_CONF1(value uint32) { + volatile.StoreUint32(&o.CIS_CONF1.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF1() uint32 { + return volatile.LoadUint32(&o.CIS_CONF1.Reg) +} + +// HINF.CIS_CONF2 +func (o *HINF_Type) SetCIS_CONF2(value uint32) { + volatile.StoreUint32(&o.CIS_CONF2.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF2() uint32 { + return volatile.LoadUint32(&o.CIS_CONF2.Reg) +} + +// HINF.CIS_CONF3 +func (o *HINF_Type) SetCIS_CONF3(value uint32) { + volatile.StoreUint32(&o.CIS_CONF3.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF3() uint32 { + return volatile.LoadUint32(&o.CIS_CONF3.Reg) +} + +// HINF.CIS_CONF4 +func (o *HINF_Type) SetCIS_CONF4(value uint32) { + volatile.StoreUint32(&o.CIS_CONF4.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF4() uint32 { + return volatile.LoadUint32(&o.CIS_CONF4.Reg) +} + +// HINF.CIS_CONF5 +func (o *HINF_Type) SetCIS_CONF5(value uint32) { + volatile.StoreUint32(&o.CIS_CONF5.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF5() uint32 { + return volatile.LoadUint32(&o.CIS_CONF5.Reg) +} + +// HINF.CIS_CONF6 +func (o *HINF_Type) SetCIS_CONF6(value uint32) { + volatile.StoreUint32(&o.CIS_CONF6.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF6() uint32 { + return volatile.LoadUint32(&o.CIS_CONF6.Reg) +} + +// HINF.CIS_CONF7 +func (o *HINF_Type) SetCIS_CONF7(value uint32) { + volatile.StoreUint32(&o.CIS_CONF7.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF7() uint32 { + return volatile.LoadUint32(&o.CIS_CONF7.Reg) +} + +// HINF.CFG_DATA16 +func (o *HINF_Type) SetCFG_DATA16_USER_ID_FN2(value uint32) { + volatile.StoreUint32(&o.CFG_DATA16.Reg, volatile.LoadUint32(&o.CFG_DATA16.Reg)&^(0xffff)|value) +} +func (o *HINF_Type) GetCFG_DATA16_USER_ID_FN2() uint32 { + return volatile.LoadUint32(&o.CFG_DATA16.Reg) & 0xffff +} +func (o *HINF_Type) SetCFG_DATA16_DEVICE_ID_FN2(value uint32) { + volatile.StoreUint32(&o.CFG_DATA16.Reg, volatile.LoadUint32(&o.CFG_DATA16.Reg)&^(0xffff0000)|value<<16) +} +func (o *HINF_Type) GetCFG_DATA16_DEVICE_ID_FN2() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA16.Reg) & 0xffff0000) >> 16 +} + +// HINF.DATE +func (o *HINF_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *HINF_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2C (Inter-Integrated Circuit) Controller 0 +type I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + RXFIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + SCL_FILTER_CFG volatile.Register32 // 0x50 + SDA_FILTER_CFG volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + COMD8 volatile.Register32 // 0x78 + COMD9 volatile.Register32 // 0x7C + COMD10 volatile.Register32 // 0x80 + COMD11 volatile.Register32 // 0x84 + COMD12 volatile.Register32 // 0x88 + COMD13 volatile.Register32 // 0x8C + COMD14 volatile.Register32 // 0x90 + COMD15 volatile.Register32 // 0x94 + _ [96]byte + DATE volatile.Register32 // 0xF8 + _ [4]byte + FIFO_START_ADDR volatile.Register32 // 0x100 +} + +// I2C.SCL_LOW_PERIOD +func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x3fff +} + +// I2C.CTR +func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetCTR_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetCTR_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} + +// I2C.SR +func (o *I2C_Type) SetSR_ACK_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSR_ACK_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *I2C_Type) SetSR_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetSR_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetSR_TIME_OUT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetSR_TIME_OUT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetSR_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetSR_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetSR_BYTE_TRANS(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSR_BYTE_TRANS() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xfc0000) >> 18 +} +func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// I2C.TO +func (o *I2C_Type) SetTO_TIME_OUT(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0xfffff)|value) +} +func (o *I2C_Type) GetTO_TIME_OUT() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0xfffff +} + +// I2C.SLAVE_ADDR +func (o *I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// I2C.RXFIFO_ST +func (o *I2C_Type) SetRXFIFO_ST_RXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_ST.Reg, volatile.LoadUint32(&o.RXFIFO_ST.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetRXFIFO_ST_RXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.RXFIFO_ST.Reg) & 0x1f +} +func (o *I2C_Type) SetRXFIFO_ST_RXFIFO_END_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_ST.Reg, volatile.LoadUint32(&o.RXFIFO_ST.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetRXFIFO_ST_RXFIFO_END_ADDR() uint32 { + return (volatile.LoadUint32(&o.RXFIFO_ST.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetRXFIFO_ST_TXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_ST.Reg, volatile.LoadUint32(&o.RXFIFO_ST.Reg)&^(0x7c00)|value<<10) +} +func (o *I2C_Type) GetRXFIFO_ST_TXFIFO_START_ADDR() uint32 { + return (volatile.LoadUint32(&o.RXFIFO_ST.Reg) & 0x7c00) >> 10 +} +func (o *I2C_Type) SetRXFIFO_ST_TXFIFO_END_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_ST.Reg, volatile.LoadUint32(&o.RXFIFO_ST.Reg)&^(0xf8000)|value<<15) +} +func (o *I2C_Type) GetRXFIFO_ST_TXFIFO_END_ADDR() uint32 { + return (volatile.LoadUint32(&o.RXFIFO_ST.Reg) & 0xf8000) >> 15 +} + +// I2C.FIFO_CONF +func (o *I2C_Type) SetFIFO_CONF_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_CONF_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_CONF_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_CONF_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_ADDR_CFG_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_ADDR_CFG_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_RX_THRES(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_RX_THRES() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_TX_THRES(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3f00000)|value<<20) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_TX_THRES() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3f00000) >> 20 +} + +// I2C.DATA +func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// I2C.INT_RAW +func (o *I2C_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_TRAN_COMP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_RAW_MASTER_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_RAW_MASTER_TRAN_COMP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_RAW_ACK_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_RAW_ACK_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_RAW_RX_REC_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_RAW_RX_REC_FULL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_RAW_TX_SEND_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_RAW_TX_SEND_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} + +// I2C.INT_CLR +func (o *I2C_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_TRAN_COMP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_CLR_MASTER_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_CLR_MASTER_TRAN_COMP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_CLR_ACK_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_CLR_ACK_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_CLR_RX_REC_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_CLR_RX_REC_FULL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_CLR_TX_SEND_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_CLR_TX_SEND_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} + +// I2C.INT_ENA +func (o *I2C_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_TRAN_COMP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_ENA_MASTER_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_ENA_MASTER_TRAN_COMP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_ENA_ACK_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_ENA_ACK_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_ENA_RX_REC_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_ENA_RX_REC_FULL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_ENA_TX_SEND_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_ENA_TX_SEND_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} + +// I2C.INT_STATUS +func (o *I2C_Type) SetINT_STATUS_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_TRAN_COMP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_STATUS_MASTER_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_STATUS_MASTER_TRAN_COMP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_STATUS_ACK_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_STATUS_ACK_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_STATUS_RX_REC_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_STATUS_RX_REC_FULL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_STATUS_TX_SEND_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_STATUS_TX_SEND_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} + +// I2C.SDA_HOLD +func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x3ff +} + +// I2C.SDA_SAMPLE +func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x3ff +} + +// I2C.SCL_HIGH_PERIOD +func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x3fff +} + +// I2C.SCL_START_HOLD +func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x3ff +} + +// I2C.SCL_RSTART_SETUP +func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x3ff +} + +// I2C.SCL_STOP_HOLD +func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x3fff +} + +// I2C.SCL_STOP_SETUP +func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x3ff +} + +// I2C.SCL_FILTER_CFG +func (o *I2C_Type) SetSCL_FILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.SCL_FILTER_CFG.Reg, volatile.LoadUint32(&o.SCL_FILTER_CFG.Reg)&^(0x7)|value) +} +func (o *I2C_Type) GetSCL_FILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.SCL_FILTER_CFG.Reg) & 0x7 +} +func (o *I2C_Type) SetSCL_FILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.SCL_FILTER_CFG.Reg, volatile.LoadUint32(&o.SCL_FILTER_CFG.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSCL_FILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_FILTER_CFG.Reg) & 0x8) >> 3 +} + +// I2C.SDA_FILTER_CFG +func (o *I2C_Type) SetSDA_FILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.SDA_FILTER_CFG.Reg, volatile.LoadUint32(&o.SDA_FILTER_CFG.Reg)&^(0x7)|value) +} +func (o *I2C_Type) GetSDA_FILTER_CFG_SDA_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.SDA_FILTER_CFG.Reg) & 0x7 +} +func (o *I2C_Type) SetSDA_FILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.SDA_FILTER_CFG.Reg, volatile.LoadUint32(&o.SDA_FILTER_CFG.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSDA_FILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.SDA_FILTER_CFG.Reg) & 0x8) >> 3 +} + +// I2C.COMD0 +func (o *I2C_Type) SetCOMD0_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD0_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD0_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD0_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD1 +func (o *I2C_Type) SetCOMD1_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD1_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD1_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD1_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD2 +func (o *I2C_Type) SetCOMD2_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD2_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD2_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD2_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD3 +func (o *I2C_Type) SetCOMD3_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD3_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD3_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD3_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD4 +func (o *I2C_Type) SetCOMD4_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD4_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD4_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD4_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD5 +func (o *I2C_Type) SetCOMD5_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD5_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD5_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD5_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD6 +func (o *I2C_Type) SetCOMD6_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD6_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD6_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD6_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD7 +func (o *I2C_Type) SetCOMD7_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD7_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD7_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD7_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD8 +func (o *I2C_Type) SetCOMD8_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD8.Reg, volatile.LoadUint32(&o.COMD8.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD8_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD8.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD8_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD8.Reg, volatile.LoadUint32(&o.COMD8.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD8_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD8.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD9 +func (o *I2C_Type) SetCOMD9_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD9.Reg, volatile.LoadUint32(&o.COMD9.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD9_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD9.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD9_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD9.Reg, volatile.LoadUint32(&o.COMD9.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD9_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD9.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD10 +func (o *I2C_Type) SetCOMD10_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD10.Reg, volatile.LoadUint32(&o.COMD10.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD10_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD10.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD10_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD10.Reg, volatile.LoadUint32(&o.COMD10.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD10_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD10.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD11 +func (o *I2C_Type) SetCOMD11_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD11.Reg, volatile.LoadUint32(&o.COMD11.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD11_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD11.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD11_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD11.Reg, volatile.LoadUint32(&o.COMD11.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD11_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD11.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD12 +func (o *I2C_Type) SetCOMD12_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD12.Reg, volatile.LoadUint32(&o.COMD12.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD12_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD12.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD12_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD12.Reg, volatile.LoadUint32(&o.COMD12.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD12_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD12.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD13 +func (o *I2C_Type) SetCOMD13_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD13.Reg, volatile.LoadUint32(&o.COMD13.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD13_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD13.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD13_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD13.Reg, volatile.LoadUint32(&o.COMD13.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD13_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD13.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD14 +func (o *I2C_Type) SetCOMD14_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD14.Reg, volatile.LoadUint32(&o.COMD14.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD14_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD14.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD14_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD14.Reg, volatile.LoadUint32(&o.COMD14.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD14_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD14.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD15 +func (o *I2C_Type) SetCOMD15_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD15.Reg, volatile.LoadUint32(&o.COMD15.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD15_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD15.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD15_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD15.Reg, volatile.LoadUint32(&o.COMD15.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD15_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD15.Reg) & 0x80000000) >> 31 +} + +// I2C.DATE +func (o *I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2S (Inter-IC Sound) Controller 0 +type I2S_Type struct { + _ [8]byte + CONF volatile.Register32 // 0x8 + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + TIMING volatile.Register32 // 0x1C + FIFO_CONF volatile.Register32 // 0x20 + RXEOF_NUM volatile.Register32 // 0x24 + CONF_SIGLE_DATA volatile.Register32 // 0x28 + CONF_CHAN volatile.Register32 // 0x2C + OUT_LINK volatile.Register32 // 0x30 + IN_LINK volatile.Register32 // 0x34 + OUT_EOF_DES_ADDR volatile.Register32 // 0x38 + IN_EOF_DES_ADDR volatile.Register32 // 0x3C + OUT_EOF_BFR_DES_ADDR volatile.Register32 // 0x40 + AHB_TEST volatile.Register32 // 0x44 + INLINK_DSCR volatile.Register32 // 0x48 + INLINK_DSCR_BF0 volatile.Register32 // 0x4C + INLINK_DSCR_BF1 volatile.Register32 // 0x50 + OUTLINK_DSCR volatile.Register32 // 0x54 + OUTLINK_DSCR_BF0 volatile.Register32 // 0x58 + OUTLINK_DSCR_BF1 volatile.Register32 // 0x5C + LC_CONF volatile.Register32 // 0x60 + OUTFIFO_PUSH volatile.Register32 // 0x64 + INFIFO_POP volatile.Register32 // 0x68 + LC_STATE0 volatile.Register32 // 0x6C + LC_STATE1 volatile.Register32 // 0x70 + LC_HUNG_CONF volatile.Register32 // 0x74 + _ [8]byte + CVSD_CONF0 volatile.Register32 // 0x80 + CVSD_CONF1 volatile.Register32 // 0x84 + CVSD_CONF2 volatile.Register32 // 0x88 + PLC_CONF0 volatile.Register32 // 0x8C + PLC_CONF1 volatile.Register32 // 0x90 + PLC_CONF2 volatile.Register32 // 0x94 + ESCO_CONF0 volatile.Register32 // 0x98 + SCO_CONF0 volatile.Register32 // 0x9C + CONF1 volatile.Register32 // 0xA0 + PD_CONF volatile.Register32 // 0xA4 + CONF2 volatile.Register32 // 0xA8 + CLKM_CONF volatile.Register32 // 0xAC + SAMPLE_RATE_CONF volatile.Register32 // 0xB0 + PDM_CONF volatile.Register32 // 0xB4 + PDM_FREQ_CONF volatile.Register32 // 0xB8 + STATE volatile.Register32 // 0xBC + _ [60]byte + DATE volatile.Register32 // 0xFC +} + +// I2S.CONF +func (o *I2S_Type) SetCONF_TX_RESET(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetCONF_TX_RESET() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetCONF_RX_RESET(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetCONF_RX_RESET() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetCONF_TX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetCONF_TX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetCONF_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetCONF_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetCONF_TX_START(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetCONF_TX_START() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetCONF_RX_START(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetCONF_RX_START() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetCONF_TX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetCONF_TX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetCONF_RX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetCONF_RX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetCONF_TX_RIGHT_FIRST(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetCONF_TX_RIGHT_FIRST() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetCONF_RX_RIGHT_FIRST(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetCONF_RX_RIGHT_FIRST() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetCONF_TX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetCONF_TX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetCONF_RX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetCONF_RX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetCONF_TX_SHORT_SYNC(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetCONF_TX_SHORT_SYNC() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetCONF_RX_SHORT_SYNC(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetCONF_RX_SHORT_SYNC() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetCONF_TX_MONO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetCONF_TX_MONO() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetCONF_RX_MONO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetCONF_RX_MONO() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetCONF_TX_MSB_RIGHT(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetCONF_TX_MSB_RIGHT() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetCONF_RX_MSB_RIGHT(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetCONF_RX_MSB_RIGHT() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetCONF_SIG_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetCONF_SIG_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000) >> 18 +} + +// I2S.INT_RAW +func (o *I2S_Type) SetINT_RAW_RX_TAKE_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_RAW_RX_TAKE_DATA_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_RAW_TX_PUT_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_RAW_TX_PUT_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_RAW_RX_WFULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_RAW_RX_WFULL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_RAW_RX_REMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_RAW_RX_REMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetINT_RAW_TX_WFULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetINT_RAW_TX_WFULL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetINT_RAW_TX_REMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetINT_RAW_TX_REMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetINT_RAW_IN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetINT_RAW_IN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetINT_RAW_IN_SUC_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetINT_RAW_IN_SUC_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetINT_RAW_IN_ERR_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetINT_RAW_IN_ERR_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetINT_RAW_OUT_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetINT_RAW_OUT_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetINT_RAW_IN_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetINT_RAW_IN_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetINT_RAW_OUT_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetINT_RAW_OUT_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetINT_RAW_IN_DSCR_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetINT_RAW_IN_DSCR_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetINT_RAW_OUT_TOTAL_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINT_RAW_OUT_TOTAL_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} + +// I2S.INT_ST +func (o *I2S_Type) SetINT_ST_RX_TAKE_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ST_RX_TAKE_DATA_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ST_TX_PUT_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ST_TX_PUT_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ST_RX_WFULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ST_RX_WFULL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ST_RX_REMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ST_RX_REMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetINT_ST_TX_WFULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetINT_ST_TX_WFULL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetINT_ST_TX_REMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetINT_ST_TX_REMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetINT_ST_IN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetINT_ST_IN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetINT_ST_IN_SUC_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetINT_ST_IN_SUC_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetINT_ST_IN_ERR_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetINT_ST_IN_ERR_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetINT_ST_OUT_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetINT_ST_OUT_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetINT_ST_OUT_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetINT_ST_OUT_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetINT_ST_IN_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetINT_ST_IN_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetINT_ST_OUT_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetINT_ST_OUT_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetINT_ST_IN_DSCR_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetINT_ST_IN_DSCR_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetINT_ST_OUT_TOTAL_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINT_ST_OUT_TOTAL_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} + +// I2S.INT_ENA +func (o *I2S_Type) SetINT_ENA_RX_TAKE_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ENA_RX_TAKE_DATA_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ENA_TX_PUT_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ENA_TX_PUT_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ENA_RX_WFULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ENA_RX_WFULL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ENA_RX_REMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ENA_RX_REMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetINT_ENA_TX_WFULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetINT_ENA_TX_WFULL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetINT_ENA_TX_REMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetINT_ENA_TX_REMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetINT_ENA_IN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetINT_ENA_IN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetINT_ENA_IN_SUC_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetINT_ENA_IN_SUC_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetINT_ENA_IN_ERR_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetINT_ENA_IN_ERR_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetINT_ENA_OUT_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetINT_ENA_OUT_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetINT_ENA_OUT_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetINT_ENA_OUT_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetINT_ENA_IN_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetINT_ENA_IN_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetINT_ENA_OUT_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetINT_ENA_OUT_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetINT_ENA_IN_DSCR_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetINT_ENA_IN_DSCR_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetINT_ENA_OUT_TOTAL_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINT_ENA_OUT_TOTAL_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} + +// I2S.INT_CLR +func (o *I2S_Type) SetINT_CLR_TAKE_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_CLR_TAKE_DATA_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_CLR_PUT_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_CLR_PUT_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_CLR_RX_WFULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_CLR_RX_WFULL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_CLR_RX_REMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_CLR_RX_REMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetINT_CLR_TX_WFULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetINT_CLR_TX_WFULL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetINT_CLR_TX_REMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetINT_CLR_TX_REMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetINT_CLR_IN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetINT_CLR_IN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetINT_CLR_IN_SUC_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetINT_CLR_IN_SUC_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetINT_CLR_IN_ERR_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetINT_CLR_IN_ERR_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetINT_CLR_OUT_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetINT_CLR_OUT_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetINT_CLR_OUT_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetINT_CLR_OUT_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetINT_CLR_IN_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetINT_CLR_IN_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetINT_CLR_OUT_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetINT_CLR_OUT_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetINT_CLR_IN_DSCR_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetINT_CLR_IN_DSCR_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetINT_CLR_OUT_TOTAL_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINT_CLR_OUT_TOTAL_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} + +// I2S.TIMING +func (o *I2S_Type) SetTIMING_TX_BCK_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetTIMING_TX_BCK_IN_DELAY() uint32 { + return volatile.LoadUint32(&o.TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetTIMING_TX_WS_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc)|value<<2) +} +func (o *I2S_Type) GetTIMING_TX_WS_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc) >> 2 +} +func (o *I2S_Type) SetTIMING_RX_BCK_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetTIMING_RX_BCK_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetTIMING_RX_WS_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc0)|value<<6) +} +func (o *I2S_Type) GetTIMING_RX_WS_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc0) >> 6 +} +func (o *I2S_Type) SetTIMING_RX_SD_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x300)|value<<8) +} +func (o *I2S_Type) GetTIMING_RX_SD_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x300) >> 8 +} +func (o *I2S_Type) SetTIMING_TX_BCK_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetTIMING_TX_BCK_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetTIMING_TX_WS_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x3000)|value<<12) +} +func (o *I2S_Type) GetTIMING_TX_WS_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x3000) >> 12 +} +func (o *I2S_Type) SetTIMING_TX_SD_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc000)|value<<14) +} +func (o *I2S_Type) GetTIMING_TX_SD_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc000) >> 14 +} +func (o *I2S_Type) SetTIMING_RX_WS_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetTIMING_RX_WS_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetTIMING_RX_BCK_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc0000)|value<<18) +} +func (o *I2S_Type) GetTIMING_RX_BCK_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc0000) >> 18 +} +func (o *I2S_Type) SetTIMING_TX_DSYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTIMING_TX_DSYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetTIMING_RX_DSYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetTIMING_RX_DSYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetTIMING_DATA_ENABLE_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc00000)|value<<22) +} +func (o *I2S_Type) GetTIMING_DATA_ENABLE_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc00000) >> 22 +} +func (o *I2S_Type) SetTIMING_TX_BCK_IN_INV(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x1000000)|value<<24) +} +func (o *I2S_Type) GetTIMING_TX_BCK_IN_INV() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x1000000) >> 24 +} + +// I2S.FIFO_CONF +func (o *I2S_Type) SetFIFO_CONF_RX_DATA_NUM(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3f)|value) +} +func (o *I2S_Type) GetFIFO_CONF_RX_DATA_NUM() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3f +} +func (o *I2S_Type) SetFIFO_CONF_TX_DATA_NUM(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *I2S_Type) GetFIFO_CONF_TX_DATA_NUM() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xfc0) >> 6 +} +func (o *I2S_Type) SetFIFO_CONF_DSCR_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetFIFO_CONF_DSCR_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetFIFO_CONF_TX_FIFO_MOD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xe000)|value<<13) +} +func (o *I2S_Type) GetFIFO_CONF_TX_FIFO_MOD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xe000) >> 13 +} +func (o *I2S_Type) SetFIFO_CONF_RX_FIFO_MOD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x70000)|value<<16) +} +func (o *I2S_Type) GetFIFO_CONF_RX_FIFO_MOD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x70000) >> 16 +} +func (o *I2S_Type) SetFIFO_CONF_TX_FIFO_MOD_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetFIFO_CONF_TX_FIFO_MOD_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetFIFO_CONF_RX_FIFO_MOD_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetFIFO_CONF_RX_FIFO_MOD_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x100000) >> 20 +} + +// I2S.RXEOF_NUM +func (o *I2S_Type) SetRXEOF_NUM(value uint32) { + volatile.StoreUint32(&o.RXEOF_NUM.Reg, value) +} +func (o *I2S_Type) GetRXEOF_NUM() uint32 { + return volatile.LoadUint32(&o.RXEOF_NUM.Reg) +} + +// I2S.CONF_SIGLE_DATA +func (o *I2S_Type) SetCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value) +} +func (o *I2S_Type) GetCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg) +} + +// I2S.CONF_CHAN +func (o *I2S_Type) SetCONF_CHAN_TX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.CONF_CHAN.Reg, volatile.LoadUint32(&o.CONF_CHAN.Reg)&^(0x7)|value) +} +func (o *I2S_Type) GetCONF_CHAN_TX_CHAN_MOD() uint32 { + return volatile.LoadUint32(&o.CONF_CHAN.Reg) & 0x7 +} +func (o *I2S_Type) SetCONF_CHAN_RX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.CONF_CHAN.Reg, volatile.LoadUint32(&o.CONF_CHAN.Reg)&^(0x18)|value<<3) +} +func (o *I2S_Type) GetCONF_CHAN_RX_CHAN_MOD() uint32 { + return (volatile.LoadUint32(&o.CONF_CHAN.Reg) & 0x18) >> 3 +} + +// I2S.OUT_LINK +func (o *I2S_Type) SetOUT_LINK_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0xfffff)|value) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK.Reg) & 0xfffff +} +func (o *I2S_Type) SetOUT_LINK_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK.Reg) & 0x10000000) >> 28 +} +func (o *I2S_Type) SetOUT_LINK_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK.Reg) & 0x20000000) >> 29 +} +func (o *I2S_Type) SetOUT_LINK_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK.Reg) & 0x40000000) >> 30 +} +func (o *I2S_Type) SetOUT_LINK_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK.Reg) & 0x80000000) >> 31 +} + +// I2S.IN_LINK +func (o *I2S_Type) SetIN_LINK_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0xfffff)|value) +} +func (o *I2S_Type) GetIN_LINK_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK.Reg) & 0xfffff +} +func (o *I2S_Type) SetIN_LINK_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *I2S_Type) GetIN_LINK_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK.Reg) & 0x10000000) >> 28 +} +func (o *I2S_Type) SetIN_LINK_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetIN_LINK_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK.Reg) & 0x20000000) >> 29 +} +func (o *I2S_Type) SetIN_LINK_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetIN_LINK_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK.Reg) & 0x40000000) >> 30 +} +func (o *I2S_Type) SetIN_LINK_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *I2S_Type) GetIN_LINK_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK.Reg) & 0x80000000) >> 31 +} + +// I2S.OUT_EOF_DES_ADDR +func (o *I2S_Type) SetOUT_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR.Reg, value) +} +func (o *I2S_Type) GetOUT_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR.Reg) +} + +// I2S.IN_EOF_DES_ADDR +func (o *I2S_Type) SetIN_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EOF_DES_ADDR.Reg, value) +} +func (o *I2S_Type) GetIN_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_EOF_DES_ADDR.Reg) +} + +// I2S.OUT_EOF_BFR_DES_ADDR +func (o *I2S_Type) SetOUT_EOF_BFR_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR.Reg, value) +} +func (o *I2S_Type) GetOUT_EOF_BFR_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR.Reg) +} + +// I2S.AHB_TEST +func (o *I2S_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *I2S_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *I2S_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// I2S.INLINK_DSCR +func (o *I2S_Type) SetINLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR.Reg, value) +} +func (o *I2S_Type) GetINLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR.Reg) +} + +// I2S.INLINK_DSCR_BF0 +func (o *I2S_Type) SetINLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR_BF0.Reg, value) +} +func (o *I2S_Type) GetINLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR_BF0.Reg) +} + +// I2S.INLINK_DSCR_BF1 +func (o *I2S_Type) SetINLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR_BF1.Reg, value) +} +func (o *I2S_Type) GetINLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR_BF1.Reg) +} + +// I2S.OUTLINK_DSCR +func (o *I2S_Type) SetOUTLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR.Reg, value) +} +func (o *I2S_Type) GetOUTLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR.Reg) +} + +// I2S.OUTLINK_DSCR_BF0 +func (o *I2S_Type) SetOUTLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR_BF0.Reg, value) +} +func (o *I2S_Type) GetOUTLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR_BF0.Reg) +} + +// I2S.OUTLINK_DSCR_BF1 +func (o *I2S_Type) SetOUTLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR_BF1.Reg, value) +} +func (o *I2S_Type) GetOUTLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR_BF1.Reg) +} + +// I2S.LC_CONF +func (o *I2S_Type) SetLC_CONF_IN_RST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetLC_CONF_IN_RST() uint32 { + return volatile.LoadUint32(&o.LC_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetLC_CONF_OUT_RST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetLC_CONF_OUT_RST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetLC_CONF_AHBM_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetLC_CONF_AHBM_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetLC_CONF_AHBM_RST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetLC_CONF_AHBM_RST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetLC_CONF_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetLC_CONF_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetLC_CONF_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetLC_CONF_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetLC_CONF_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetLC_CONF_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetLC_CONF_OUT_NO_RESTART_CLR(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetLC_CONF_OUT_NO_RESTART_CLR() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetLC_CONF_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetLC_CONF_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetLC_CONF_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetLC_CONF_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetLC_CONF_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetLC_CONF_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetLC_CONF_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetLC_CONF_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetLC_CONF_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetLC_CONF_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetLC_CONF_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetLC_CONF_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x2000) >> 13 +} + +// I2S.OUTFIFO_PUSH +func (o *I2S_Type) SetOUTFIFO_PUSH_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_PUSH.Reg, volatile.LoadUint32(&o.OUTFIFO_PUSH.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetOUTFIFO_PUSH_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_PUSH.Reg) & 0x1ff +} +func (o *I2S_Type) SetOUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_PUSH.Reg, volatile.LoadUint32(&o.OUTFIFO_PUSH.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetOUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_PUSH.Reg) & 0x10000) >> 16 +} + +// I2S.INFIFO_POP +func (o *I2S_Type) SetINFIFO_POP_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.INFIFO_POP.Reg, volatile.LoadUint32(&o.INFIFO_POP.Reg)&^(0xfff)|value) +} +func (o *I2S_Type) GetINFIFO_POP_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.INFIFO_POP.Reg) & 0xfff +} +func (o *I2S_Type) SetINFIFO_POP(value uint32) { + volatile.StoreUint32(&o.INFIFO_POP.Reg, volatile.LoadUint32(&o.INFIFO_POP.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.INFIFO_POP.Reg) & 0x10000) >> 16 +} + +// I2S.LC_STATE0 +func (o *I2S_Type) SetLC_STATE0(value uint32) { + volatile.StoreUint32(&o.LC_STATE0.Reg, value) +} +func (o *I2S_Type) GetLC_STATE0() uint32 { + return volatile.LoadUint32(&o.LC_STATE0.Reg) +} + +// I2S.LC_STATE1 +func (o *I2S_Type) SetLC_STATE1(value uint32) { + volatile.StoreUint32(&o.LC_STATE1.Reg, value) +} +func (o *I2S_Type) GetLC_STATE1() uint32 { + return volatile.LoadUint32(&o.LC_STATE1.Reg) +} + +// I2S.LC_HUNG_CONF +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11 +} + +// I2S.CVSD_CONF0 +func (o *I2S_Type) SetCVSD_CONF0_CVSD_Y_MAX(value uint32) { + volatile.StoreUint32(&o.CVSD_CONF0.Reg, volatile.LoadUint32(&o.CVSD_CONF0.Reg)&^(0xffff)|value) +} +func (o *I2S_Type) GetCVSD_CONF0_CVSD_Y_MAX() uint32 { + return volatile.LoadUint32(&o.CVSD_CONF0.Reg) & 0xffff +} +func (o *I2S_Type) SetCVSD_CONF0_CVSD_Y_MIN(value uint32) { + volatile.StoreUint32(&o.CVSD_CONF0.Reg, volatile.LoadUint32(&o.CVSD_CONF0.Reg)&^(0xffff0000)|value<<16) +} +func (o *I2S_Type) GetCVSD_CONF0_CVSD_Y_MIN() uint32 { + return (volatile.LoadUint32(&o.CVSD_CONF0.Reg) & 0xffff0000) >> 16 +} + +// I2S.CVSD_CONF1 +func (o *I2S_Type) SetCVSD_CONF1_CVSD_SIGMA_MAX(value uint32) { + volatile.StoreUint32(&o.CVSD_CONF1.Reg, volatile.LoadUint32(&o.CVSD_CONF1.Reg)&^(0xffff)|value) +} +func (o *I2S_Type) GetCVSD_CONF1_CVSD_SIGMA_MAX() uint32 { + return volatile.LoadUint32(&o.CVSD_CONF1.Reg) & 0xffff +} +func (o *I2S_Type) SetCVSD_CONF1_CVSD_SIGMA_MIN(value uint32) { + volatile.StoreUint32(&o.CVSD_CONF1.Reg, volatile.LoadUint32(&o.CVSD_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *I2S_Type) GetCVSD_CONF1_CVSD_SIGMA_MIN() uint32 { + return (volatile.LoadUint32(&o.CVSD_CONF1.Reg) & 0xffff0000) >> 16 +} + +// I2S.CVSD_CONF2 +func (o *I2S_Type) SetCVSD_CONF2_CVSD_K(value uint32) { + volatile.StoreUint32(&o.CVSD_CONF2.Reg, volatile.LoadUint32(&o.CVSD_CONF2.Reg)&^(0x7)|value) +} +func (o *I2S_Type) GetCVSD_CONF2_CVSD_K() uint32 { + return volatile.LoadUint32(&o.CVSD_CONF2.Reg) & 0x7 +} +func (o *I2S_Type) SetCVSD_CONF2_CVSD_J(value uint32) { + volatile.StoreUint32(&o.CVSD_CONF2.Reg, volatile.LoadUint32(&o.CVSD_CONF2.Reg)&^(0x38)|value<<3) +} +func (o *I2S_Type) GetCVSD_CONF2_CVSD_J() uint32 { + return (volatile.LoadUint32(&o.CVSD_CONF2.Reg) & 0x38) >> 3 +} +func (o *I2S_Type) SetCVSD_CONF2_CVSD_BETA(value uint32) { + volatile.StoreUint32(&o.CVSD_CONF2.Reg, volatile.LoadUint32(&o.CVSD_CONF2.Reg)&^(0xffc0)|value<<6) +} +func (o *I2S_Type) GetCVSD_CONF2_CVSD_BETA() uint32 { + return (volatile.LoadUint32(&o.CVSD_CONF2.Reg) & 0xffc0) >> 6 +} +func (o *I2S_Type) SetCVSD_CONF2_CVSD_H(value uint32) { + volatile.StoreUint32(&o.CVSD_CONF2.Reg, volatile.LoadUint32(&o.CVSD_CONF2.Reg)&^(0x70000)|value<<16) +} +func (o *I2S_Type) GetCVSD_CONF2_CVSD_H() uint32 { + return (volatile.LoadUint32(&o.CVSD_CONF2.Reg) & 0x70000) >> 16 +} + +// I2S.PLC_CONF0 +func (o *I2S_Type) SetPLC_CONF0_GOOD_PACK_MAX(value uint32) { + volatile.StoreUint32(&o.PLC_CONF0.Reg, volatile.LoadUint32(&o.PLC_CONF0.Reg)&^(0x3f)|value) +} +func (o *I2S_Type) GetPLC_CONF0_GOOD_PACK_MAX() uint32 { + return volatile.LoadUint32(&o.PLC_CONF0.Reg) & 0x3f +} +func (o *I2S_Type) SetPLC_CONF0_N_ERR_SEG(value uint32) { + volatile.StoreUint32(&o.PLC_CONF0.Reg, volatile.LoadUint32(&o.PLC_CONF0.Reg)&^(0x1c0)|value<<6) +} +func (o *I2S_Type) GetPLC_CONF0_N_ERR_SEG() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF0.Reg) & 0x1c0) >> 6 +} +func (o *I2S_Type) SetPLC_CONF0_SHIFT_RATE(value uint32) { + volatile.StoreUint32(&o.PLC_CONF0.Reg, volatile.LoadUint32(&o.PLC_CONF0.Reg)&^(0xe00)|value<<9) +} +func (o *I2S_Type) GetPLC_CONF0_SHIFT_RATE() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF0.Reg) & 0xe00) >> 9 +} +func (o *I2S_Type) SetPLC_CONF0_MAX_SLIDE_SAMPLE(value uint32) { + volatile.StoreUint32(&o.PLC_CONF0.Reg, volatile.LoadUint32(&o.PLC_CONF0.Reg)&^(0xff000)|value<<12) +} +func (o *I2S_Type) GetPLC_CONF0_MAX_SLIDE_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF0.Reg) & 0xff000) >> 12 +} +func (o *I2S_Type) SetPLC_CONF0_PACK_LEN_8K(value uint32) { + volatile.StoreUint32(&o.PLC_CONF0.Reg, volatile.LoadUint32(&o.PLC_CONF0.Reg)&^(0x1f00000)|value<<20) +} +func (o *I2S_Type) GetPLC_CONF0_PACK_LEN_8K() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF0.Reg) & 0x1f00000) >> 20 +} +func (o *I2S_Type) SetPLC_CONF0_N_MIN_ERR(value uint32) { + volatile.StoreUint32(&o.PLC_CONF0.Reg, volatile.LoadUint32(&o.PLC_CONF0.Reg)&^(0xe000000)|value<<25) +} +func (o *I2S_Type) GetPLC_CONF0_N_MIN_ERR() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF0.Reg) & 0xe000000) >> 25 +} + +// I2S.PLC_CONF1 +func (o *I2S_Type) SetPLC_CONF1_BAD_CEF_ATTEN_PARA(value uint32) { + volatile.StoreUint32(&o.PLC_CONF1.Reg, volatile.LoadUint32(&o.PLC_CONF1.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetPLC_CONF1_BAD_CEF_ATTEN_PARA() uint32 { + return volatile.LoadUint32(&o.PLC_CONF1.Reg) & 0xff +} +func (o *I2S_Type) SetPLC_CONF1_BAD_CEF_ATTEN_PARA_SHIFT(value uint32) { + volatile.StoreUint32(&o.PLC_CONF1.Reg, volatile.LoadUint32(&o.PLC_CONF1.Reg)&^(0xf00)|value<<8) +} +func (o *I2S_Type) GetPLC_CONF1_BAD_CEF_ATTEN_PARA_SHIFT() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF1.Reg) & 0xf00) >> 8 +} +func (o *I2S_Type) SetPLC_CONF1_BAD_OLA_WIN2_PARA_SHIFT(value uint32) { + volatile.StoreUint32(&o.PLC_CONF1.Reg, volatile.LoadUint32(&o.PLC_CONF1.Reg)&^(0xf000)|value<<12) +} +func (o *I2S_Type) GetPLC_CONF1_BAD_OLA_WIN2_PARA_SHIFT() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF1.Reg) & 0xf000) >> 12 +} +func (o *I2S_Type) SetPLC_CONF1_BAD_OLA_WIN2_PARA(value uint32) { + volatile.StoreUint32(&o.PLC_CONF1.Reg, volatile.LoadUint32(&o.PLC_CONF1.Reg)&^(0xff0000)|value<<16) +} +func (o *I2S_Type) GetPLC_CONF1_BAD_OLA_WIN2_PARA() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF1.Reg) & 0xff0000) >> 16 +} +func (o *I2S_Type) SetPLC_CONF1_SLIDE_WIN_LEN(value uint32) { + volatile.StoreUint32(&o.PLC_CONF1.Reg, volatile.LoadUint32(&o.PLC_CONF1.Reg)&^(0xff000000)|value<<24) +} +func (o *I2S_Type) GetPLC_CONF1_SLIDE_WIN_LEN() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF1.Reg) & 0xff000000) >> 24 +} + +// I2S.PLC_CONF2 +func (o *I2S_Type) SetPLC_CONF2_CVSD_SEG_MOD(value uint32) { + volatile.StoreUint32(&o.PLC_CONF2.Reg, volatile.LoadUint32(&o.PLC_CONF2.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetPLC_CONF2_CVSD_SEG_MOD() uint32 { + return volatile.LoadUint32(&o.PLC_CONF2.Reg) & 0x3 +} +func (o *I2S_Type) SetPLC_CONF2_MIN_PERIOD(value uint32) { + volatile.StoreUint32(&o.PLC_CONF2.Reg, volatile.LoadUint32(&o.PLC_CONF2.Reg)&^(0x7c)|value<<2) +} +func (o *I2S_Type) GetPLC_CONF2_MIN_PERIOD() uint32 { + return (volatile.LoadUint32(&o.PLC_CONF2.Reg) & 0x7c) >> 2 +} + +// I2S.ESCO_CONF0 +func (o *I2S_Type) SetESCO_CONF0_ESCO_EN(value uint32) { + volatile.StoreUint32(&o.ESCO_CONF0.Reg, volatile.LoadUint32(&o.ESCO_CONF0.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetESCO_CONF0_ESCO_EN() uint32 { + return volatile.LoadUint32(&o.ESCO_CONF0.Reg) & 0x1 +} +func (o *I2S_Type) SetESCO_CONF0_ESCO_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.ESCO_CONF0.Reg, volatile.LoadUint32(&o.ESCO_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetESCO_CONF0_ESCO_CHAN_MOD() uint32 { + return (volatile.LoadUint32(&o.ESCO_CONF0.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetESCO_CONF0_ESCO_CVSD_DEC_PACK_ERR(value uint32) { + volatile.StoreUint32(&o.ESCO_CONF0.Reg, volatile.LoadUint32(&o.ESCO_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetESCO_CONF0_ESCO_CVSD_DEC_PACK_ERR() uint32 { + return (volatile.LoadUint32(&o.ESCO_CONF0.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetESCO_CONF0_ESCO_CVSD_PACK_LEN_8K(value uint32) { + volatile.StoreUint32(&o.ESCO_CONF0.Reg, volatile.LoadUint32(&o.ESCO_CONF0.Reg)&^(0xf8)|value<<3) +} +func (o *I2S_Type) GetESCO_CONF0_ESCO_CVSD_PACK_LEN_8K() uint32 { + return (volatile.LoadUint32(&o.ESCO_CONF0.Reg) & 0xf8) >> 3 +} +func (o *I2S_Type) SetESCO_CONF0_ESCO_CVSD_INF_EN(value uint32) { + volatile.StoreUint32(&o.ESCO_CONF0.Reg, volatile.LoadUint32(&o.ESCO_CONF0.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetESCO_CONF0_ESCO_CVSD_INF_EN() uint32 { + return (volatile.LoadUint32(&o.ESCO_CONF0.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetESCO_CONF0_CVSD_DEC_START(value uint32) { + volatile.StoreUint32(&o.ESCO_CONF0.Reg, volatile.LoadUint32(&o.ESCO_CONF0.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetESCO_CONF0_CVSD_DEC_START() uint32 { + return (volatile.LoadUint32(&o.ESCO_CONF0.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetESCO_CONF0_CVSD_DEC_RESET(value uint32) { + volatile.StoreUint32(&o.ESCO_CONF0.Reg, volatile.LoadUint32(&o.ESCO_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetESCO_CONF0_CVSD_DEC_RESET() uint32 { + return (volatile.LoadUint32(&o.ESCO_CONF0.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetESCO_CONF0_PLC_EN(value uint32) { + volatile.StoreUint32(&o.ESCO_CONF0.Reg, volatile.LoadUint32(&o.ESCO_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetESCO_CONF0_PLC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCO_CONF0.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetESCO_CONF0_PLC2DMA_EN(value uint32) { + volatile.StoreUint32(&o.ESCO_CONF0.Reg, volatile.LoadUint32(&o.ESCO_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetESCO_CONF0_PLC2DMA_EN() uint32 { + return (volatile.LoadUint32(&o.ESCO_CONF0.Reg) & 0x1000) >> 12 +} + +// I2S.SCO_CONF0 +func (o *I2S_Type) SetSCO_CONF0_SCO_WITH_I2S_EN(value uint32) { + volatile.StoreUint32(&o.SCO_CONF0.Reg, volatile.LoadUint32(&o.SCO_CONF0.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetSCO_CONF0_SCO_WITH_I2S_EN() uint32 { + return volatile.LoadUint32(&o.SCO_CONF0.Reg) & 0x1 +} +func (o *I2S_Type) SetSCO_CONF0_SCO_NO_I2S_EN(value uint32) { + volatile.StoreUint32(&o.SCO_CONF0.Reg, volatile.LoadUint32(&o.SCO_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetSCO_CONF0_SCO_NO_I2S_EN() uint32 { + return (volatile.LoadUint32(&o.SCO_CONF0.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetSCO_CONF0_CVSD_ENC_START(value uint32) { + volatile.StoreUint32(&o.SCO_CONF0.Reg, volatile.LoadUint32(&o.SCO_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetSCO_CONF0_CVSD_ENC_START() uint32 { + return (volatile.LoadUint32(&o.SCO_CONF0.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetSCO_CONF0_CVSD_ENC_RESET(value uint32) { + volatile.StoreUint32(&o.SCO_CONF0.Reg, volatile.LoadUint32(&o.SCO_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetSCO_CONF0_CVSD_ENC_RESET() uint32 { + return (volatile.LoadUint32(&o.SCO_CONF0.Reg) & 0x8) >> 3 +} + +// I2S.CONF1 +func (o *I2S_Type) SetCONF1_TX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x7)|value) +} +func (o *I2S_Type) GetCONF1_TX_PCM_CONF() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x7 +} +func (o *I2S_Type) SetCONF1_TX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetCONF1_TX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetCONF1_RX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x70)|value<<4) +} +func (o *I2S_Type) GetCONF1_RX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x70) >> 4 +} +func (o *I2S_Type) SetCONF1_RX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetCONF1_RX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetCONF1_TX_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetCONF1_TX_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetCONF1_TX_ZEROS_RM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetCONF1_TX_ZEROS_RM_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200) >> 9 +} + +// I2S.PD_CONF +func (o *I2S_Type) SetPD_CONF_FIFO_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetPD_CONF_FIFO_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.PD_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetPD_CONF_FIFO_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetPD_CONF_FIFO_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetPD_CONF_PLC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetPD_CONF_PLC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetPD_CONF_PLC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetPD_CONF_PLC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x8) >> 3 +} + +// I2S.CONF2 +func (o *I2S_Type) SetCONF2_CAMERA_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetCONF2_CAMERA_EN() uint32 { + return volatile.LoadUint32(&o.CONF2.Reg) & 0x1 +} +func (o *I2S_Type) SetCONF2_LCD_TX_WRX2_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetCONF2_LCD_TX_WRX2_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetCONF2_LCD_TX_SDX2_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetCONF2_LCD_TX_SDX2_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetCONF2_DATA_ENABLE_TEST_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetCONF2_DATA_ENABLE_TEST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetCONF2_DATA_ENABLE(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetCONF2_DATA_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetCONF2_LCD_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetCONF2_LCD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetCONF2_EXT_ADC_START_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetCONF2_EXT_ADC_START_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetCONF2_INTER_VALID_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetCONF2_INTER_VALID_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x80) >> 7 +} + +// I2S.CLKM_CONF +func (o *I2S_Type) SetCLKM_CONF_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetCLKM_CONF_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetCLKM_CONF_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *I2S_Type) GetCLKM_CONF_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x3f00) >> 8 +} +func (o *I2S_Type) SetCLKM_CONF_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2S_Type) GetCLKM_CONF_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2S_Type) SetCLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetCLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetCLKM_CONF_CLKA_ENA(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetCLKM_CONF_CLKA_ENA() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x200000) >> 21 +} + +// I2S.SAMPLE_RATE_CONF +func (o *I2S_Type) SetSAMPLE_RATE_CONF_TX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SAMPLE_RATE_CONF.Reg, volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg)&^(0x3f)|value) +} +func (o *I2S_Type) GetSAMPLE_RATE_CONF_TX_BCK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg) & 0x3f +} +func (o *I2S_Type) SetSAMPLE_RATE_CONF_RX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SAMPLE_RATE_CONF.Reg, volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *I2S_Type) GetSAMPLE_RATE_CONF_RX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg) & 0xfc0) >> 6 +} +func (o *I2S_Type) SetSAMPLE_RATE_CONF_TX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.SAMPLE_RATE_CONF.Reg, volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg)&^(0x3f000)|value<<12) +} +func (o *I2S_Type) GetSAMPLE_RATE_CONF_TX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg) & 0x3f000) >> 12 +} +func (o *I2S_Type) SetSAMPLE_RATE_CONF_RX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.SAMPLE_RATE_CONF.Reg, volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S_Type) GetSAMPLE_RATE_CONF_RX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg) & 0xfc0000) >> 18 +} + +// I2S.PDM_CONF +func (o *I2S_Type) SetPDM_CONF_TX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetPDM_CONF_TX_PDM_EN() uint32 { + return volatile.LoadUint32(&o.PDM_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetPDM_CONF_RX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetPDM_CONF_RX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetPDM_CONF_PCM2PDM_CONV_EN(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetPDM_CONF_PCM2PDM_CONV_EN() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetPDM_CONF_PDM2PCM_CONV_EN(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetPDM_CONF_PDM2PCM_CONV_EN() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetPDM_CONF_TX_PDM_SINC_OSR2(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *I2S_Type) GetPDM_CONF_TX_PDM_SINC_OSR2() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0xf0) >> 4 +} +func (o *I2S_Type) SetPDM_CONF_TX_PDM_PRESCALE(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *I2S_Type) GetPDM_CONF_TX_PDM_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0xff00) >> 8 +} +func (o *I2S_Type) SetPDM_CONF_TX_PDM_HP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetPDM_CONF_TX_PDM_HP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetPDM_CONF_TX_PDM_LP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0xc0000)|value<<18) +} +func (o *I2S_Type) GetPDM_CONF_TX_PDM_LP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0xc0000) >> 18 +} +func (o *I2S_Type) SetPDM_CONF_TX_PDM_SINC_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetPDM_CONF_TX_PDM_SINC_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetPDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0xc00000)|value<<22) +} +func (o *I2S_Type) GetPDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0xc00000) >> 22 +} +func (o *I2S_Type) SetPDM_CONF_RX_PDM_SINC_DSR_16_EN(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *I2S_Type) GetPDM_CONF_RX_PDM_SINC_DSR_16_EN() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0x1000000) >> 24 +} +func (o *I2S_Type) SetPDM_CONF_TX_PDM_HP_BYPASS(value uint32) { + volatile.StoreUint32(&o.PDM_CONF.Reg, volatile.LoadUint32(&o.PDM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *I2S_Type) GetPDM_CONF_TX_PDM_HP_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PDM_CONF.Reg) & 0x2000000) >> 25 +} + +// I2S.PDM_FREQ_CONF +func (o *I2S_Type) SetPDM_FREQ_CONF_TX_PDM_FS(value uint32) { + volatile.StoreUint32(&o.PDM_FREQ_CONF.Reg, volatile.LoadUint32(&o.PDM_FREQ_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2S_Type) GetPDM_FREQ_CONF_TX_PDM_FS() uint32 { + return volatile.LoadUint32(&o.PDM_FREQ_CONF.Reg) & 0x3ff +} +func (o *I2S_Type) SetPDM_FREQ_CONF_TX_PDM_FP(value uint32) { + volatile.StoreUint32(&o.PDM_FREQ_CONF.Reg, volatile.LoadUint32(&o.PDM_FREQ_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *I2S_Type) GetPDM_FREQ_CONF_TX_PDM_FP() uint32 { + return (volatile.LoadUint32(&o.PDM_FREQ_CONF.Reg) & 0xffc00) >> 10 +} + +// I2S.STATE +func (o *I2S_Type) SetSTATE_TX_IDLE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetSTATE_TX_IDLE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x1 +} +func (o *I2S_Type) SetSTATE_TX_FIFO_RESET_BACK(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetSTATE_TX_FIFO_RESET_BACK() uint32 { + return (volatile.LoadUint32(&o.STATE.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetSTATE_RX_FIFO_RESET_BACK(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetSTATE_RX_FIFO_RESET_BACK() uint32 { + return (volatile.LoadUint32(&o.STATE.Reg) & 0x4) >> 2 +} + +// I2S.DATE +func (o *I2S_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2S_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Input/Output Multiplexer +type IO_MUX_Type struct { + PIN_CTRL volatile.Register32 // 0x0 + GPIO36 volatile.Register32 // 0x4 + GPIO37 volatile.Register32 // 0x8 + GPIO38 volatile.Register32 // 0xC + GPIO39 volatile.Register32 // 0x10 + GPIO34 volatile.Register32 // 0x14 + GPIO35 volatile.Register32 // 0x18 + GPIO32 volatile.Register32 // 0x1C + GPIO33 volatile.Register32 // 0x20 + GPIO25 volatile.Register32 // 0x24 + GPIO26 volatile.Register32 // 0x28 + GPIO27 volatile.Register32 // 0x2C + GPIO14 volatile.Register32 // 0x30 + GPIO12 volatile.Register32 // 0x34 + GPIO13 volatile.Register32 // 0x38 + GPIO15 volatile.Register32 // 0x3C + GPIO2 volatile.Register32 // 0x40 + GPIO0 volatile.Register32 // 0x44 + GPIO4 volatile.Register32 // 0x48 + GPIO16 volatile.Register32 // 0x4C + GPIO17 volatile.Register32 // 0x50 + GPIO9 volatile.Register32 // 0x54 + GPIO10 volatile.Register32 // 0x58 + GPIO11 volatile.Register32 // 0x5C + GPIO6 volatile.Register32 // 0x60 + GPIO7 volatile.Register32 // 0x64 + GPIO8 volatile.Register32 // 0x68 + GPIO5 volatile.Register32 // 0x6C + GPIO18 volatile.Register32 // 0x70 + GPIO19 volatile.Register32 // 0x74 + GPIO20 volatile.Register32 // 0x78 + GPIO21 volatile.Register32 // 0x7C + GPIO22 volatile.Register32 // 0x80 + GPIO3 volatile.Register32 // 0x84 + GPIO1 volatile.Register32 // 0x88 + GPIO23 volatile.Register32 // 0x8C + GPIO24 volatile.Register32 // 0x90 +} + +// IO_MUX.PIN_CTRL +func (o *IO_MUX_Type) SetPIN_CTRL_CLK1(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf)|value) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK1() uint32 { + return volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK2(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf0)|value<<4) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK2() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf0) >> 4 +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK3(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf00)|value<<8) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK3() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf00) >> 8 +} + +// IO_MUX.GPIO36 +func (o *IO_MUX_Type) SetGPIO36_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO36.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO36_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO36_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO37 +func (o *IO_MUX_Type) SetGPIO37_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO37.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO37_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO37_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO38 +func (o *IO_MUX_Type) SetGPIO38_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO38.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO38_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO38_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO39 +func (o *IO_MUX_Type) SetGPIO39_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO39.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO39_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO39_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO34 +func (o *IO_MUX_Type) SetGPIO34_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO34.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO34_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO34_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO35 +func (o *IO_MUX_Type) SetGPIO35_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO35.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO35_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO35_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO32 +func (o *IO_MUX_Type) SetGPIO32_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO32.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO32_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO32_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO33 +func (o *IO_MUX_Type) SetGPIO33_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO33.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO33_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO33_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO25 +func (o *IO_MUX_Type) SetGPIO25_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO25.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO25_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO25_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO26 +func (o *IO_MUX_Type) SetGPIO26_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO26.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO26_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO26_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO27 +func (o *IO_MUX_Type) SetGPIO27_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO27.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO27_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO27_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO14 +func (o *IO_MUX_Type) SetGPIO14_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO14.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO12 +func (o *IO_MUX_Type) SetGPIO12_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO12.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO13 +func (o *IO_MUX_Type) SetGPIO13_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO13.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO15 +func (o *IO_MUX_Type) SetGPIO15_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO15.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO15_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO15_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO2 +func (o *IO_MUX_Type) SetGPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO0 +func (o *IO_MUX_Type) SetGPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO4 +func (o *IO_MUX_Type) SetGPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO16 +func (o *IO_MUX_Type) SetGPIO16_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO16.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO16_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO16_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO17 +func (o *IO_MUX_Type) SetGPIO17_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO17.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO17_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO17_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO9 +func (o *IO_MUX_Type) SetGPIO9_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO9.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO10 +func (o *IO_MUX_Type) SetGPIO10_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO10.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO11 +func (o *IO_MUX_Type) SetGPIO11_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO11.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO6 +func (o *IO_MUX_Type) SetGPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO7 +func (o *IO_MUX_Type) SetGPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO8 +func (o *IO_MUX_Type) SetGPIO8_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO8.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO5 +func (o *IO_MUX_Type) SetGPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO18 +func (o *IO_MUX_Type) SetGPIO18_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO18.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO18_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO18_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO19 +func (o *IO_MUX_Type) SetGPIO19_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO19.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO20 +func (o *IO_MUX_Type) SetGPIO20_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO20.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO21 +func (o *IO_MUX_Type) SetGPIO21_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO21.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO22 +func (o *IO_MUX_Type) SetGPIO22_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO22.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO22_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO22_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO3 +func (o *IO_MUX_Type) SetGPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO1 +func (o *IO_MUX_Type) SetGPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO23 +func (o *IO_MUX_Type) SetGPIO23_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO23.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO23_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO23_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x7000) >> 12 +} + +// IO_MUX.GPIO24 +func (o *IO_MUX_Type) SetGPIO24_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO24.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO24_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO24_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x7000) >> 12 +} + +// LED Control PWM (Pulse Width Modulation) +type LEDC_Type struct { + HSCH0_CONF0 volatile.Register32 // 0x0 + HSCH0_HPOINT volatile.Register32 // 0x4 + HSCH0_DUTY volatile.Register32 // 0x8 + HSCH0_CONF1 volatile.Register32 // 0xC + HSCH0_DUTY_R volatile.Register32 // 0x10 + HSCH1_CONF0 volatile.Register32 // 0x14 + HSCH1_HPOINT volatile.Register32 // 0x18 + HSCH1_DUTY volatile.Register32 // 0x1C + HSCH1_CONF1 volatile.Register32 // 0x20 + HSCH1_DUTY_R volatile.Register32 // 0x24 + HSCH2_CONF0 volatile.Register32 // 0x28 + HSCH2_HPOINT volatile.Register32 // 0x2C + HSCH2_DUTY volatile.Register32 // 0x30 + HSCH2_CONF1 volatile.Register32 // 0x34 + HSCH2_DUTY_R volatile.Register32 // 0x38 + HSCH3_CONF0 volatile.Register32 // 0x3C + HSCH3_HPOINT volatile.Register32 // 0x40 + HSCH3_DUTY volatile.Register32 // 0x44 + HSCH3_CONF1 volatile.Register32 // 0x48 + HSCH3_DUTY_R volatile.Register32 // 0x4C + HSCH4_CONF0 volatile.Register32 // 0x50 + HSCH4_HPOINT volatile.Register32 // 0x54 + HSCH4_DUTY volatile.Register32 // 0x58 + HSCH4_CONF1 volatile.Register32 // 0x5C + HSCH4_DUTY_R volatile.Register32 // 0x60 + HSCH5_CONF0 volatile.Register32 // 0x64 + HSCH5_HPOINT volatile.Register32 // 0x68 + HSCH5_DUTY volatile.Register32 // 0x6C + HSCH5_CONF1 volatile.Register32 // 0x70 + HSCH5_DUTY_R volatile.Register32 // 0x74 + HSCH6_CONF0 volatile.Register32 // 0x78 + HSCH6_HPOINT volatile.Register32 // 0x7C + HSCH6_DUTY volatile.Register32 // 0x80 + HSCH6_CONF1 volatile.Register32 // 0x84 + HSCH6_DUTY_R volatile.Register32 // 0x88 + HSCH7_CONF0 volatile.Register32 // 0x8C + HSCH7_HPOINT volatile.Register32 // 0x90 + HSCH7_DUTY volatile.Register32 // 0x94 + HSCH7_CONF1 volatile.Register32 // 0x98 + HSCH7_DUTY_R volatile.Register32 // 0x9C + LSCH0_CONF0 volatile.Register32 // 0xA0 + LSCH0_HPOINT volatile.Register32 // 0xA4 + LSCH0_DUTY volatile.Register32 // 0xA8 + LSCH0_CONF1 volatile.Register32 // 0xAC + LSCH0_DUTY_R volatile.Register32 // 0xB0 + LSCH1_CONF0 volatile.Register32 // 0xB4 + LSCH1_HPOINT volatile.Register32 // 0xB8 + LSCH1_DUTY volatile.Register32 // 0xBC + LSCH1_CONF1 volatile.Register32 // 0xC0 + LSCH1_DUTY_R volatile.Register32 // 0xC4 + LSCH2_CONF0 volatile.Register32 // 0xC8 + LSCH2_HPOINT volatile.Register32 // 0xCC + LSCH2_DUTY volatile.Register32 // 0xD0 + LSCH2_CONF1 volatile.Register32 // 0xD4 + LSCH2_DUTY_R volatile.Register32 // 0xD8 + LSCH3_CONF0 volatile.Register32 // 0xDC + LSCH3_HPOINT volatile.Register32 // 0xE0 + LSCH3_DUTY volatile.Register32 // 0xE4 + LSCH3_CONF1 volatile.Register32 // 0xE8 + LSCH3_DUTY_R volatile.Register32 // 0xEC + LSCH4_CONF0 volatile.Register32 // 0xF0 + LSCH4_HPOINT volatile.Register32 // 0xF4 + LSCH4_DUTY volatile.Register32 // 0xF8 + LSCH4_CONF1 volatile.Register32 // 0xFC + LSCH4_DUTY_R volatile.Register32 // 0x100 + LSCH5_CONF0 volatile.Register32 // 0x104 + LSCH5_HPOINT volatile.Register32 // 0x108 + LSCH5_DUTY volatile.Register32 // 0x10C + LSCH5_CONF1 volatile.Register32 // 0x110 + LSCH5_DUTY_R volatile.Register32 // 0x114 + LSCH6_CONF0 volatile.Register32 // 0x118 + LSCH6_HPOINT volatile.Register32 // 0x11C + LSCH6_DUTY volatile.Register32 // 0x120 + LSCH6_CONF1 volatile.Register32 // 0x124 + LSCH6_DUTY_R volatile.Register32 // 0x128 + LSCH7_CONF0 volatile.Register32 // 0x12C + LSCH7_HPOINT volatile.Register32 // 0x130 + LSCH7_DUTY volatile.Register32 // 0x134 + LSCH7_CONF1 volatile.Register32 // 0x138 + LSCH7_DUTY_R volatile.Register32 // 0x13C + HSTIMER0_CONF volatile.Register32 // 0x140 + HSTIMER0_VALUE volatile.Register32 // 0x144 + HSTIMER1_CONF volatile.Register32 // 0x148 + HSTIMER1_VALUE volatile.Register32 // 0x14C + HSTIMER2_CONF volatile.Register32 // 0x150 + HSTIMER2_VALUE volatile.Register32 // 0x154 + HSTIMER3_CONF volatile.Register32 // 0x158 + HSTIMER3_VALUE volatile.Register32 // 0x15C + LSTIMER0_CONF volatile.Register32 // 0x160 + LSTIMER0_VALUE volatile.Register32 // 0x164 + LSTIMER1_CONF volatile.Register32 // 0x168 + LSTIMER1_VALUE volatile.Register32 // 0x16C + LSTIMER2_CONF volatile.Register32 // 0x170 + LSTIMER2_VALUE volatile.Register32 // 0x174 + LSTIMER3_CONF volatile.Register32 // 0x178 + LSTIMER3_VALUE volatile.Register32 // 0x17C + INT_RAW volatile.Register32 // 0x180 + INT_ST volatile.Register32 // 0x184 + INT_ENA volatile.Register32 // 0x188 + INT_CLR volatile.Register32 // 0x18C + CONF volatile.Register32 // 0x190 + _ [104]byte + DATE volatile.Register32 // 0x1FC +} + +// LEDC.HSCH0_CONF0 +func (o *LEDC_Type) SetHSCH0_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.HSCH0_CONF0.Reg, volatile.LoadUint32(&o.HSCH0_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetHSCH0_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.HSCH0_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetHSCH0_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.HSCH0_CONF0.Reg, volatile.LoadUint32(&o.HSCH0_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetHSCH0_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.HSCH0_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetHSCH0_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.HSCH0_CONF0.Reg, volatile.LoadUint32(&o.HSCH0_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetHSCH0_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.HSCH0_CONF0.Reg) & 0x8) >> 3 +} + +// LEDC.HSCH0_HPOINT +func (o *LEDC_Type) SetHSCH0_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.HSCH0_HPOINT.Reg, volatile.LoadUint32(&o.HSCH0_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSCH0_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.HSCH0_HPOINT.Reg) & 0xfffff +} + +// LEDC.HSCH0_DUTY +func (o *LEDC_Type) SetHSCH0_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.HSCH0_DUTY.Reg, volatile.LoadUint32(&o.HSCH0_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH0_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.HSCH0_DUTY.Reg) & 0x1ffffff +} + +// LEDC.HSCH0_CONF1 +func (o *LEDC_Type) SetHSCH0_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.HSCH0_CONF1.Reg, volatile.LoadUint32(&o.HSCH0_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetHSCH0_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.HSCH0_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetHSCH0_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.HSCH0_CONF1.Reg, volatile.LoadUint32(&o.HSCH0_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetHSCH0_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.HSCH0_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetHSCH0_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.HSCH0_CONF1.Reg, volatile.LoadUint32(&o.HSCH0_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetHSCH0_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.HSCH0_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetHSCH0_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.HSCH0_CONF1.Reg, volatile.LoadUint32(&o.HSCH0_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetHSCH0_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.HSCH0_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetHSCH0_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.HSCH0_CONF1.Reg, volatile.LoadUint32(&o.HSCH0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetHSCH0_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.HSCH0_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.HSCH0_DUTY_R +func (o *LEDC_Type) SetHSCH0_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.HSCH0_DUTY_R.Reg, volatile.LoadUint32(&o.HSCH0_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH0_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.HSCH0_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.HSCH1_CONF0 +func (o *LEDC_Type) SetHSCH1_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.HSCH1_CONF0.Reg, volatile.LoadUint32(&o.HSCH1_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetHSCH1_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.HSCH1_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetHSCH1_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.HSCH1_CONF0.Reg, volatile.LoadUint32(&o.HSCH1_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetHSCH1_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.HSCH1_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetHSCH1_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.HSCH1_CONF0.Reg, volatile.LoadUint32(&o.HSCH1_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetHSCH1_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.HSCH1_CONF0.Reg) & 0x8) >> 3 +} + +// LEDC.HSCH1_HPOINT +func (o *LEDC_Type) SetHSCH1_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.HSCH1_HPOINT.Reg, volatile.LoadUint32(&o.HSCH1_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSCH1_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.HSCH1_HPOINT.Reg) & 0xfffff +} + +// LEDC.HSCH1_DUTY +func (o *LEDC_Type) SetHSCH1_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.HSCH1_DUTY.Reg, volatile.LoadUint32(&o.HSCH1_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH1_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.HSCH1_DUTY.Reg) & 0x1ffffff +} + +// LEDC.HSCH1_CONF1 +func (o *LEDC_Type) SetHSCH1_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.HSCH1_CONF1.Reg, volatile.LoadUint32(&o.HSCH1_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetHSCH1_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.HSCH1_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetHSCH1_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.HSCH1_CONF1.Reg, volatile.LoadUint32(&o.HSCH1_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetHSCH1_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.HSCH1_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetHSCH1_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.HSCH1_CONF1.Reg, volatile.LoadUint32(&o.HSCH1_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetHSCH1_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.HSCH1_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetHSCH1_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.HSCH1_CONF1.Reg, volatile.LoadUint32(&o.HSCH1_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetHSCH1_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.HSCH1_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetHSCH1_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.HSCH1_CONF1.Reg, volatile.LoadUint32(&o.HSCH1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetHSCH1_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.HSCH1_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.HSCH1_DUTY_R +func (o *LEDC_Type) SetHSCH1_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.HSCH1_DUTY_R.Reg, volatile.LoadUint32(&o.HSCH1_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH1_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.HSCH1_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.HSCH2_CONF0 +func (o *LEDC_Type) SetHSCH2_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.HSCH2_CONF0.Reg, volatile.LoadUint32(&o.HSCH2_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetHSCH2_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.HSCH2_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetHSCH2_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.HSCH2_CONF0.Reg, volatile.LoadUint32(&o.HSCH2_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetHSCH2_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.HSCH2_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetHSCH2_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.HSCH2_CONF0.Reg, volatile.LoadUint32(&o.HSCH2_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetHSCH2_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.HSCH2_CONF0.Reg) & 0x8) >> 3 +} + +// LEDC.HSCH2_HPOINT +func (o *LEDC_Type) SetHSCH2_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.HSCH2_HPOINT.Reg, volatile.LoadUint32(&o.HSCH2_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSCH2_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.HSCH2_HPOINT.Reg) & 0xfffff +} + +// LEDC.HSCH2_DUTY +func (o *LEDC_Type) SetHSCH2_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.HSCH2_DUTY.Reg, volatile.LoadUint32(&o.HSCH2_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH2_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.HSCH2_DUTY.Reg) & 0x1ffffff +} + +// LEDC.HSCH2_CONF1 +func (o *LEDC_Type) SetHSCH2_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.HSCH2_CONF1.Reg, volatile.LoadUint32(&o.HSCH2_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetHSCH2_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.HSCH2_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetHSCH2_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.HSCH2_CONF1.Reg, volatile.LoadUint32(&o.HSCH2_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetHSCH2_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.HSCH2_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetHSCH2_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.HSCH2_CONF1.Reg, volatile.LoadUint32(&o.HSCH2_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetHSCH2_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.HSCH2_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetHSCH2_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.HSCH2_CONF1.Reg, volatile.LoadUint32(&o.HSCH2_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetHSCH2_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.HSCH2_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetHSCH2_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.HSCH2_CONF1.Reg, volatile.LoadUint32(&o.HSCH2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetHSCH2_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.HSCH2_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.HSCH2_DUTY_R +func (o *LEDC_Type) SetHSCH2_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.HSCH2_DUTY_R.Reg, volatile.LoadUint32(&o.HSCH2_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH2_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.HSCH2_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.HSCH3_CONF0 +func (o *LEDC_Type) SetHSCH3_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.HSCH3_CONF0.Reg, volatile.LoadUint32(&o.HSCH3_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetHSCH3_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.HSCH3_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetHSCH3_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.HSCH3_CONF0.Reg, volatile.LoadUint32(&o.HSCH3_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetHSCH3_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.HSCH3_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetHSCH3_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.HSCH3_CONF0.Reg, volatile.LoadUint32(&o.HSCH3_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetHSCH3_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.HSCH3_CONF0.Reg) & 0x8) >> 3 +} + +// LEDC.HSCH3_HPOINT +func (o *LEDC_Type) SetHSCH3_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.HSCH3_HPOINT.Reg, volatile.LoadUint32(&o.HSCH3_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSCH3_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.HSCH3_HPOINT.Reg) & 0xfffff +} + +// LEDC.HSCH3_DUTY +func (o *LEDC_Type) SetHSCH3_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.HSCH3_DUTY.Reg, volatile.LoadUint32(&o.HSCH3_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH3_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.HSCH3_DUTY.Reg) & 0x1ffffff +} + +// LEDC.HSCH3_CONF1 +func (o *LEDC_Type) SetHSCH3_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.HSCH3_CONF1.Reg, volatile.LoadUint32(&o.HSCH3_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetHSCH3_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.HSCH3_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetHSCH3_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.HSCH3_CONF1.Reg, volatile.LoadUint32(&o.HSCH3_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetHSCH3_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.HSCH3_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetHSCH3_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.HSCH3_CONF1.Reg, volatile.LoadUint32(&o.HSCH3_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetHSCH3_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.HSCH3_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetHSCH3_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.HSCH3_CONF1.Reg, volatile.LoadUint32(&o.HSCH3_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetHSCH3_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.HSCH3_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetHSCH3_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.HSCH3_CONF1.Reg, volatile.LoadUint32(&o.HSCH3_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetHSCH3_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.HSCH3_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.HSCH3_DUTY_R +func (o *LEDC_Type) SetHSCH3_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.HSCH3_DUTY_R.Reg, volatile.LoadUint32(&o.HSCH3_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH3_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.HSCH3_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.HSCH4_CONF0 +func (o *LEDC_Type) SetHSCH4_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.HSCH4_CONF0.Reg, volatile.LoadUint32(&o.HSCH4_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetHSCH4_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.HSCH4_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetHSCH4_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.HSCH4_CONF0.Reg, volatile.LoadUint32(&o.HSCH4_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetHSCH4_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.HSCH4_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetHSCH4_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.HSCH4_CONF0.Reg, volatile.LoadUint32(&o.HSCH4_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetHSCH4_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.HSCH4_CONF0.Reg) & 0x8) >> 3 +} + +// LEDC.HSCH4_HPOINT +func (o *LEDC_Type) SetHSCH4_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.HSCH4_HPOINT.Reg, volatile.LoadUint32(&o.HSCH4_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSCH4_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.HSCH4_HPOINT.Reg) & 0xfffff +} + +// LEDC.HSCH4_DUTY +func (o *LEDC_Type) SetHSCH4_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.HSCH4_DUTY.Reg, volatile.LoadUint32(&o.HSCH4_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH4_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.HSCH4_DUTY.Reg) & 0x1ffffff +} + +// LEDC.HSCH4_CONF1 +func (o *LEDC_Type) SetHSCH4_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.HSCH4_CONF1.Reg, volatile.LoadUint32(&o.HSCH4_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetHSCH4_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.HSCH4_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetHSCH4_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.HSCH4_CONF1.Reg, volatile.LoadUint32(&o.HSCH4_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetHSCH4_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.HSCH4_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetHSCH4_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.HSCH4_CONF1.Reg, volatile.LoadUint32(&o.HSCH4_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetHSCH4_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.HSCH4_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetHSCH4_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.HSCH4_CONF1.Reg, volatile.LoadUint32(&o.HSCH4_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetHSCH4_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.HSCH4_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetHSCH4_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.HSCH4_CONF1.Reg, volatile.LoadUint32(&o.HSCH4_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetHSCH4_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.HSCH4_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.HSCH4_DUTY_R +func (o *LEDC_Type) SetHSCH4_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.HSCH4_DUTY_R.Reg, volatile.LoadUint32(&o.HSCH4_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH4_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.HSCH4_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.HSCH5_CONF0 +func (o *LEDC_Type) SetHSCH5_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.HSCH5_CONF0.Reg, volatile.LoadUint32(&o.HSCH5_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetHSCH5_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.HSCH5_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetHSCH5_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.HSCH5_CONF0.Reg, volatile.LoadUint32(&o.HSCH5_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetHSCH5_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.HSCH5_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetHSCH5_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.HSCH5_CONF0.Reg, volatile.LoadUint32(&o.HSCH5_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetHSCH5_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.HSCH5_CONF0.Reg) & 0x8) >> 3 +} + +// LEDC.HSCH5_HPOINT +func (o *LEDC_Type) SetHSCH5_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.HSCH5_HPOINT.Reg, volatile.LoadUint32(&o.HSCH5_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSCH5_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.HSCH5_HPOINT.Reg) & 0xfffff +} + +// LEDC.HSCH5_DUTY +func (o *LEDC_Type) SetHSCH5_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.HSCH5_DUTY.Reg, volatile.LoadUint32(&o.HSCH5_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH5_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.HSCH5_DUTY.Reg) & 0x1ffffff +} + +// LEDC.HSCH5_CONF1 +func (o *LEDC_Type) SetHSCH5_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.HSCH5_CONF1.Reg, volatile.LoadUint32(&o.HSCH5_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetHSCH5_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.HSCH5_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetHSCH5_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.HSCH5_CONF1.Reg, volatile.LoadUint32(&o.HSCH5_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetHSCH5_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.HSCH5_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetHSCH5_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.HSCH5_CONF1.Reg, volatile.LoadUint32(&o.HSCH5_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetHSCH5_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.HSCH5_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetHSCH5_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.HSCH5_CONF1.Reg, volatile.LoadUint32(&o.HSCH5_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetHSCH5_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.HSCH5_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetHSCH5_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.HSCH5_CONF1.Reg, volatile.LoadUint32(&o.HSCH5_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetHSCH5_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.HSCH5_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.HSCH5_DUTY_R +func (o *LEDC_Type) SetHSCH5_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.HSCH5_DUTY_R.Reg, volatile.LoadUint32(&o.HSCH5_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH5_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.HSCH5_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.HSCH6_CONF0 +func (o *LEDC_Type) SetHSCH6_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.HSCH6_CONF0.Reg, volatile.LoadUint32(&o.HSCH6_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetHSCH6_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.HSCH6_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetHSCH6_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.HSCH6_CONF0.Reg, volatile.LoadUint32(&o.HSCH6_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetHSCH6_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.HSCH6_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetHSCH6_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.HSCH6_CONF0.Reg, volatile.LoadUint32(&o.HSCH6_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetHSCH6_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.HSCH6_CONF0.Reg) & 0x8) >> 3 +} + +// LEDC.HSCH6_HPOINT +func (o *LEDC_Type) SetHSCH6_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.HSCH6_HPOINT.Reg, volatile.LoadUint32(&o.HSCH6_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSCH6_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.HSCH6_HPOINT.Reg) & 0xfffff +} + +// LEDC.HSCH6_DUTY +func (o *LEDC_Type) SetHSCH6_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.HSCH6_DUTY.Reg, volatile.LoadUint32(&o.HSCH6_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH6_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.HSCH6_DUTY.Reg) & 0x1ffffff +} + +// LEDC.HSCH6_CONF1 +func (o *LEDC_Type) SetHSCH6_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.HSCH6_CONF1.Reg, volatile.LoadUint32(&o.HSCH6_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetHSCH6_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.HSCH6_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetHSCH6_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.HSCH6_CONF1.Reg, volatile.LoadUint32(&o.HSCH6_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetHSCH6_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.HSCH6_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetHSCH6_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.HSCH6_CONF1.Reg, volatile.LoadUint32(&o.HSCH6_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetHSCH6_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.HSCH6_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetHSCH6_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.HSCH6_CONF1.Reg, volatile.LoadUint32(&o.HSCH6_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetHSCH6_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.HSCH6_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetHSCH6_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.HSCH6_CONF1.Reg, volatile.LoadUint32(&o.HSCH6_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetHSCH6_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.HSCH6_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.HSCH6_DUTY_R +func (o *LEDC_Type) SetHSCH6_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.HSCH6_DUTY_R.Reg, volatile.LoadUint32(&o.HSCH6_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH6_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.HSCH6_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.HSCH7_CONF0 +func (o *LEDC_Type) SetHSCH7_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.HSCH7_CONF0.Reg, volatile.LoadUint32(&o.HSCH7_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetHSCH7_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.HSCH7_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetHSCH7_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.HSCH7_CONF0.Reg, volatile.LoadUint32(&o.HSCH7_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetHSCH7_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.HSCH7_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetHSCH7_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.HSCH7_CONF0.Reg, volatile.LoadUint32(&o.HSCH7_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetHSCH7_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.HSCH7_CONF0.Reg) & 0x8) >> 3 +} + +// LEDC.HSCH7_HPOINT +func (o *LEDC_Type) SetHSCH7_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.HSCH7_HPOINT.Reg, volatile.LoadUint32(&o.HSCH7_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSCH7_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.HSCH7_HPOINT.Reg) & 0xfffff +} + +// LEDC.HSCH7_DUTY +func (o *LEDC_Type) SetHSCH7_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.HSCH7_DUTY.Reg, volatile.LoadUint32(&o.HSCH7_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH7_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.HSCH7_DUTY.Reg) & 0x1ffffff +} + +// LEDC.HSCH7_CONF1 +func (o *LEDC_Type) SetHSCH7_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.HSCH7_CONF1.Reg, volatile.LoadUint32(&o.HSCH7_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetHSCH7_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.HSCH7_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetHSCH7_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.HSCH7_CONF1.Reg, volatile.LoadUint32(&o.HSCH7_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetHSCH7_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.HSCH7_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetHSCH7_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.HSCH7_CONF1.Reg, volatile.LoadUint32(&o.HSCH7_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetHSCH7_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.HSCH7_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetHSCH7_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.HSCH7_CONF1.Reg, volatile.LoadUint32(&o.HSCH7_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetHSCH7_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.HSCH7_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetHSCH7_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.HSCH7_CONF1.Reg, volatile.LoadUint32(&o.HSCH7_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetHSCH7_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.HSCH7_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.HSCH7_DUTY_R +func (o *LEDC_Type) SetHSCH7_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.HSCH7_DUTY_R.Reg, volatile.LoadUint32(&o.HSCH7_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetHSCH7_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.HSCH7_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.LSCH0_CONF0 +func (o *LEDC_Type) SetLSCH0_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.LSCH0_CONF0.Reg, volatile.LoadUint32(&o.LSCH0_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetLSCH0_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.LSCH0_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetLSCH0_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LSCH0_CONF0.Reg, volatile.LoadUint32(&o.LSCH0_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetLSCH0_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LSCH0_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetLSCH0_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.LSCH0_CONF0.Reg, volatile.LoadUint32(&o.LSCH0_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetLSCH0_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.LSCH0_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetLSCH0_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSCH0_CONF0.Reg, volatile.LoadUint32(&o.LSCH0_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetLSCH0_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSCH0_CONF0.Reg) & 0x10) >> 4 +} + +// LEDC.LSCH0_HPOINT +func (o *LEDC_Type) SetLSCH0_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.LSCH0_HPOINT.Reg, volatile.LoadUint32(&o.LSCH0_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSCH0_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.LSCH0_HPOINT.Reg) & 0xfffff +} + +// LEDC.LSCH0_DUTY +func (o *LEDC_Type) SetLSCH0_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.LSCH0_DUTY.Reg, volatile.LoadUint32(&o.LSCH0_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH0_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.LSCH0_DUTY.Reg) & 0x1ffffff +} + +// LEDC.LSCH0_CONF1 +func (o *LEDC_Type) SetLSCH0_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.LSCH0_CONF1.Reg, volatile.LoadUint32(&o.LSCH0_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetLSCH0_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.LSCH0_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetLSCH0_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.LSCH0_CONF1.Reg, volatile.LoadUint32(&o.LSCH0_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetLSCH0_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.LSCH0_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetLSCH0_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.LSCH0_CONF1.Reg, volatile.LoadUint32(&o.LSCH0_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetLSCH0_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.LSCH0_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetLSCH0_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.LSCH0_CONF1.Reg, volatile.LoadUint32(&o.LSCH0_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetLSCH0_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.LSCH0_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetLSCH0_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.LSCH0_CONF1.Reg, volatile.LoadUint32(&o.LSCH0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetLSCH0_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.LSCH0_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.LSCH0_DUTY_R +func (o *LEDC_Type) SetLSCH0_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.LSCH0_DUTY_R.Reg, volatile.LoadUint32(&o.LSCH0_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH0_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.LSCH0_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.LSCH1_CONF0 +func (o *LEDC_Type) SetLSCH1_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.LSCH1_CONF0.Reg, volatile.LoadUint32(&o.LSCH1_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetLSCH1_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.LSCH1_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetLSCH1_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LSCH1_CONF0.Reg, volatile.LoadUint32(&o.LSCH1_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetLSCH1_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LSCH1_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetLSCH1_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.LSCH1_CONF0.Reg, volatile.LoadUint32(&o.LSCH1_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetLSCH1_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.LSCH1_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetLSCH1_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSCH1_CONF0.Reg, volatile.LoadUint32(&o.LSCH1_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetLSCH1_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSCH1_CONF0.Reg) & 0x10) >> 4 +} + +// LEDC.LSCH1_HPOINT +func (o *LEDC_Type) SetLSCH1_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.LSCH1_HPOINT.Reg, volatile.LoadUint32(&o.LSCH1_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSCH1_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.LSCH1_HPOINT.Reg) & 0xfffff +} + +// LEDC.LSCH1_DUTY +func (o *LEDC_Type) SetLSCH1_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.LSCH1_DUTY.Reg, volatile.LoadUint32(&o.LSCH1_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH1_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.LSCH1_DUTY.Reg) & 0x1ffffff +} + +// LEDC.LSCH1_CONF1 +func (o *LEDC_Type) SetLSCH1_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.LSCH1_CONF1.Reg, volatile.LoadUint32(&o.LSCH1_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetLSCH1_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.LSCH1_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetLSCH1_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.LSCH1_CONF1.Reg, volatile.LoadUint32(&o.LSCH1_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetLSCH1_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.LSCH1_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetLSCH1_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.LSCH1_CONF1.Reg, volatile.LoadUint32(&o.LSCH1_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetLSCH1_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.LSCH1_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetLSCH1_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.LSCH1_CONF1.Reg, volatile.LoadUint32(&o.LSCH1_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetLSCH1_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.LSCH1_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetLSCH1_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.LSCH1_CONF1.Reg, volatile.LoadUint32(&o.LSCH1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetLSCH1_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.LSCH1_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.LSCH1_DUTY_R +func (o *LEDC_Type) SetLSCH1_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.LSCH1_DUTY_R.Reg, volatile.LoadUint32(&o.LSCH1_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH1_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.LSCH1_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.LSCH2_CONF0 +func (o *LEDC_Type) SetLSCH2_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.LSCH2_CONF0.Reg, volatile.LoadUint32(&o.LSCH2_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetLSCH2_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.LSCH2_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetLSCH2_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LSCH2_CONF0.Reg, volatile.LoadUint32(&o.LSCH2_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetLSCH2_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LSCH2_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetLSCH2_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.LSCH2_CONF0.Reg, volatile.LoadUint32(&o.LSCH2_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetLSCH2_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.LSCH2_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetLSCH2_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSCH2_CONF0.Reg, volatile.LoadUint32(&o.LSCH2_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetLSCH2_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSCH2_CONF0.Reg) & 0x10) >> 4 +} + +// LEDC.LSCH2_HPOINT +func (o *LEDC_Type) SetLSCH2_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.LSCH2_HPOINT.Reg, volatile.LoadUint32(&o.LSCH2_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSCH2_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.LSCH2_HPOINT.Reg) & 0xfffff +} + +// LEDC.LSCH2_DUTY +func (o *LEDC_Type) SetLSCH2_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.LSCH2_DUTY.Reg, volatile.LoadUint32(&o.LSCH2_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH2_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.LSCH2_DUTY.Reg) & 0x1ffffff +} + +// LEDC.LSCH2_CONF1 +func (o *LEDC_Type) SetLSCH2_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.LSCH2_CONF1.Reg, volatile.LoadUint32(&o.LSCH2_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetLSCH2_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.LSCH2_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetLSCH2_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.LSCH2_CONF1.Reg, volatile.LoadUint32(&o.LSCH2_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetLSCH2_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.LSCH2_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetLSCH2_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.LSCH2_CONF1.Reg, volatile.LoadUint32(&o.LSCH2_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetLSCH2_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.LSCH2_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetLSCH2_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.LSCH2_CONF1.Reg, volatile.LoadUint32(&o.LSCH2_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetLSCH2_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.LSCH2_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetLSCH2_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.LSCH2_CONF1.Reg, volatile.LoadUint32(&o.LSCH2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetLSCH2_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.LSCH2_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.LSCH2_DUTY_R +func (o *LEDC_Type) SetLSCH2_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.LSCH2_DUTY_R.Reg, volatile.LoadUint32(&o.LSCH2_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH2_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.LSCH2_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.LSCH3_CONF0 +func (o *LEDC_Type) SetLSCH3_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.LSCH3_CONF0.Reg, volatile.LoadUint32(&o.LSCH3_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetLSCH3_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.LSCH3_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetLSCH3_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LSCH3_CONF0.Reg, volatile.LoadUint32(&o.LSCH3_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetLSCH3_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LSCH3_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetLSCH3_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.LSCH3_CONF0.Reg, volatile.LoadUint32(&o.LSCH3_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetLSCH3_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.LSCH3_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetLSCH3_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSCH3_CONF0.Reg, volatile.LoadUint32(&o.LSCH3_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetLSCH3_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSCH3_CONF0.Reg) & 0x10) >> 4 +} + +// LEDC.LSCH3_HPOINT +func (o *LEDC_Type) SetLSCH3_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.LSCH3_HPOINT.Reg, volatile.LoadUint32(&o.LSCH3_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSCH3_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.LSCH3_HPOINT.Reg) & 0xfffff +} + +// LEDC.LSCH3_DUTY +func (o *LEDC_Type) SetLSCH3_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.LSCH3_DUTY.Reg, volatile.LoadUint32(&o.LSCH3_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH3_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.LSCH3_DUTY.Reg) & 0x1ffffff +} + +// LEDC.LSCH3_CONF1 +func (o *LEDC_Type) SetLSCH3_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.LSCH3_CONF1.Reg, volatile.LoadUint32(&o.LSCH3_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetLSCH3_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.LSCH3_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetLSCH3_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.LSCH3_CONF1.Reg, volatile.LoadUint32(&o.LSCH3_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetLSCH3_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.LSCH3_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetLSCH3_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.LSCH3_CONF1.Reg, volatile.LoadUint32(&o.LSCH3_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetLSCH3_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.LSCH3_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetLSCH3_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.LSCH3_CONF1.Reg, volatile.LoadUint32(&o.LSCH3_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetLSCH3_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.LSCH3_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetLSCH3_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.LSCH3_CONF1.Reg, volatile.LoadUint32(&o.LSCH3_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetLSCH3_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.LSCH3_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.LSCH3_DUTY_R +func (o *LEDC_Type) SetLSCH3_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.LSCH3_DUTY_R.Reg, volatile.LoadUint32(&o.LSCH3_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH3_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.LSCH3_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.LSCH4_CONF0 +func (o *LEDC_Type) SetLSCH4_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.LSCH4_CONF0.Reg, volatile.LoadUint32(&o.LSCH4_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetLSCH4_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.LSCH4_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetLSCH4_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LSCH4_CONF0.Reg, volatile.LoadUint32(&o.LSCH4_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetLSCH4_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LSCH4_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetLSCH4_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.LSCH4_CONF0.Reg, volatile.LoadUint32(&o.LSCH4_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetLSCH4_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.LSCH4_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetLSCH4_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSCH4_CONF0.Reg, volatile.LoadUint32(&o.LSCH4_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetLSCH4_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSCH4_CONF0.Reg) & 0x10) >> 4 +} + +// LEDC.LSCH4_HPOINT +func (o *LEDC_Type) SetLSCH4_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.LSCH4_HPOINT.Reg, volatile.LoadUint32(&o.LSCH4_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSCH4_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.LSCH4_HPOINT.Reg) & 0xfffff +} + +// LEDC.LSCH4_DUTY +func (o *LEDC_Type) SetLSCH4_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.LSCH4_DUTY.Reg, volatile.LoadUint32(&o.LSCH4_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH4_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.LSCH4_DUTY.Reg) & 0x1ffffff +} + +// LEDC.LSCH4_CONF1 +func (o *LEDC_Type) SetLSCH4_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.LSCH4_CONF1.Reg, volatile.LoadUint32(&o.LSCH4_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetLSCH4_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.LSCH4_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetLSCH4_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.LSCH4_CONF1.Reg, volatile.LoadUint32(&o.LSCH4_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetLSCH4_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.LSCH4_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetLSCH4_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.LSCH4_CONF1.Reg, volatile.LoadUint32(&o.LSCH4_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetLSCH4_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.LSCH4_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetLSCH4_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.LSCH4_CONF1.Reg, volatile.LoadUint32(&o.LSCH4_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetLSCH4_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.LSCH4_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetLSCH4_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.LSCH4_CONF1.Reg, volatile.LoadUint32(&o.LSCH4_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetLSCH4_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.LSCH4_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.LSCH4_DUTY_R +func (o *LEDC_Type) SetLSCH4_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.LSCH4_DUTY_R.Reg, volatile.LoadUint32(&o.LSCH4_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH4_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.LSCH4_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.LSCH5_CONF0 +func (o *LEDC_Type) SetLSCH5_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.LSCH5_CONF0.Reg, volatile.LoadUint32(&o.LSCH5_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetLSCH5_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.LSCH5_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetLSCH5_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LSCH5_CONF0.Reg, volatile.LoadUint32(&o.LSCH5_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetLSCH5_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LSCH5_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetLSCH5_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.LSCH5_CONF0.Reg, volatile.LoadUint32(&o.LSCH5_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetLSCH5_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.LSCH5_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetLSCH5_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSCH5_CONF0.Reg, volatile.LoadUint32(&o.LSCH5_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetLSCH5_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSCH5_CONF0.Reg) & 0x10) >> 4 +} + +// LEDC.LSCH5_HPOINT +func (o *LEDC_Type) SetLSCH5_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.LSCH5_HPOINT.Reg, volatile.LoadUint32(&o.LSCH5_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSCH5_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.LSCH5_HPOINT.Reg) & 0xfffff +} + +// LEDC.LSCH5_DUTY +func (o *LEDC_Type) SetLSCH5_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.LSCH5_DUTY.Reg, volatile.LoadUint32(&o.LSCH5_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH5_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.LSCH5_DUTY.Reg) & 0x1ffffff +} + +// LEDC.LSCH5_CONF1 +func (o *LEDC_Type) SetLSCH5_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.LSCH5_CONF1.Reg, volatile.LoadUint32(&o.LSCH5_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetLSCH5_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.LSCH5_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetLSCH5_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.LSCH5_CONF1.Reg, volatile.LoadUint32(&o.LSCH5_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetLSCH5_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.LSCH5_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetLSCH5_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.LSCH5_CONF1.Reg, volatile.LoadUint32(&o.LSCH5_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetLSCH5_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.LSCH5_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetLSCH5_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.LSCH5_CONF1.Reg, volatile.LoadUint32(&o.LSCH5_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetLSCH5_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.LSCH5_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetLSCH5_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.LSCH5_CONF1.Reg, volatile.LoadUint32(&o.LSCH5_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetLSCH5_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.LSCH5_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.LSCH5_DUTY_R +func (o *LEDC_Type) SetLSCH5_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.LSCH5_DUTY_R.Reg, volatile.LoadUint32(&o.LSCH5_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH5_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.LSCH5_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.LSCH6_CONF0 +func (o *LEDC_Type) SetLSCH6_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.LSCH6_CONF0.Reg, volatile.LoadUint32(&o.LSCH6_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetLSCH6_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.LSCH6_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetLSCH6_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LSCH6_CONF0.Reg, volatile.LoadUint32(&o.LSCH6_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetLSCH6_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LSCH6_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetLSCH6_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.LSCH6_CONF0.Reg, volatile.LoadUint32(&o.LSCH6_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetLSCH6_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.LSCH6_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetLSCH6_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSCH6_CONF0.Reg, volatile.LoadUint32(&o.LSCH6_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetLSCH6_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSCH6_CONF0.Reg) & 0x10) >> 4 +} + +// LEDC.LSCH6_HPOINT +func (o *LEDC_Type) SetLSCH6_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.LSCH6_HPOINT.Reg, volatile.LoadUint32(&o.LSCH6_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSCH6_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.LSCH6_HPOINT.Reg) & 0xfffff +} + +// LEDC.LSCH6_DUTY +func (o *LEDC_Type) SetLSCH6_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.LSCH6_DUTY.Reg, volatile.LoadUint32(&o.LSCH6_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH6_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.LSCH6_DUTY.Reg) & 0x1ffffff +} + +// LEDC.LSCH6_CONF1 +func (o *LEDC_Type) SetLSCH6_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.LSCH6_CONF1.Reg, volatile.LoadUint32(&o.LSCH6_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetLSCH6_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.LSCH6_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetLSCH6_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.LSCH6_CONF1.Reg, volatile.LoadUint32(&o.LSCH6_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetLSCH6_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.LSCH6_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetLSCH6_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.LSCH6_CONF1.Reg, volatile.LoadUint32(&o.LSCH6_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetLSCH6_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.LSCH6_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetLSCH6_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.LSCH6_CONF1.Reg, volatile.LoadUint32(&o.LSCH6_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetLSCH6_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.LSCH6_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetLSCH6_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.LSCH6_CONF1.Reg, volatile.LoadUint32(&o.LSCH6_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetLSCH6_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.LSCH6_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.LSCH6_DUTY_R +func (o *LEDC_Type) SetLSCH6_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.LSCH6_DUTY_R.Reg, volatile.LoadUint32(&o.LSCH6_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH6_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.LSCH6_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.LSCH7_CONF0 +func (o *LEDC_Type) SetLSCH7_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.LSCH7_CONF0.Reg, volatile.LoadUint32(&o.LSCH7_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetLSCH7_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.LSCH7_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetLSCH7_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LSCH7_CONF0.Reg, volatile.LoadUint32(&o.LSCH7_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetLSCH7_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LSCH7_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetLSCH7_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.LSCH7_CONF0.Reg, volatile.LoadUint32(&o.LSCH7_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetLSCH7_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.LSCH7_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetLSCH7_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSCH7_CONF0.Reg, volatile.LoadUint32(&o.LSCH7_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetLSCH7_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSCH7_CONF0.Reg) & 0x10) >> 4 +} + +// LEDC.LSCH7_HPOINT +func (o *LEDC_Type) SetLSCH7_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.LSCH7_HPOINT.Reg, volatile.LoadUint32(&o.LSCH7_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSCH7_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.LSCH7_HPOINT.Reg) & 0xfffff +} + +// LEDC.LSCH7_DUTY +func (o *LEDC_Type) SetLSCH7_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.LSCH7_DUTY.Reg, volatile.LoadUint32(&o.LSCH7_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH7_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.LSCH7_DUTY.Reg) & 0x1ffffff +} + +// LEDC.LSCH7_CONF1 +func (o *LEDC_Type) SetLSCH7_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.LSCH7_CONF1.Reg, volatile.LoadUint32(&o.LSCH7_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetLSCH7_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.LSCH7_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetLSCH7_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.LSCH7_CONF1.Reg, volatile.LoadUint32(&o.LSCH7_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetLSCH7_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.LSCH7_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetLSCH7_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.LSCH7_CONF1.Reg, volatile.LoadUint32(&o.LSCH7_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetLSCH7_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.LSCH7_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetLSCH7_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.LSCH7_CONF1.Reg, volatile.LoadUint32(&o.LSCH7_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetLSCH7_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.LSCH7_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetLSCH7_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.LSCH7_CONF1.Reg, volatile.LoadUint32(&o.LSCH7_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetLSCH7_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.LSCH7_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.LSCH7_DUTY_R +func (o *LEDC_Type) SetLSCH7_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.LSCH7_DUTY_R.Reg, volatile.LoadUint32(&o.LSCH7_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetLSCH7_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.LSCH7_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.HSTIMER0_CONF +func (o *LEDC_Type) SetHSTIMER0_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.HSTIMER0_CONF.Reg, volatile.LoadUint32(&o.HSTIMER0_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetHSTIMER0_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.HSTIMER0_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetHSTIMER0_CONF_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.HSTIMER0_CONF.Reg, volatile.LoadUint32(&o.HSTIMER0_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetHSTIMER0_CONF_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.HSTIMER0_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetHSTIMER0_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.HSTIMER0_CONF.Reg, volatile.LoadUint32(&o.HSTIMER0_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetHSTIMER0_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.HSTIMER0_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetHSTIMER0_CONF_RST(value uint32) { + volatile.StoreUint32(&o.HSTIMER0_CONF.Reg, volatile.LoadUint32(&o.HSTIMER0_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetHSTIMER0_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.HSTIMER0_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetHSTIMER0_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.HSTIMER0_CONF.Reg, volatile.LoadUint32(&o.HSTIMER0_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetHSTIMER0_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.HSTIMER0_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.HSTIMER0_VALUE +func (o *LEDC_Type) SetHSTIMER0_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.HSTIMER0_VALUE.Reg, volatile.LoadUint32(&o.HSTIMER0_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSTIMER0_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.HSTIMER0_VALUE.Reg) & 0xfffff +} + +// LEDC.HSTIMER1_CONF +func (o *LEDC_Type) SetHSTIMER1_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.HSTIMER1_CONF.Reg, volatile.LoadUint32(&o.HSTIMER1_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetHSTIMER1_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.HSTIMER1_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetHSTIMER1_CONF_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.HSTIMER1_CONF.Reg, volatile.LoadUint32(&o.HSTIMER1_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetHSTIMER1_CONF_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.HSTIMER1_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetHSTIMER1_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.HSTIMER1_CONF.Reg, volatile.LoadUint32(&o.HSTIMER1_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetHSTIMER1_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.HSTIMER1_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetHSTIMER1_CONF_RST(value uint32) { + volatile.StoreUint32(&o.HSTIMER1_CONF.Reg, volatile.LoadUint32(&o.HSTIMER1_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetHSTIMER1_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.HSTIMER1_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetHSTIMER1_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.HSTIMER1_CONF.Reg, volatile.LoadUint32(&o.HSTIMER1_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetHSTIMER1_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.HSTIMER1_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.HSTIMER1_VALUE +func (o *LEDC_Type) SetHSTIMER1_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.HSTIMER1_VALUE.Reg, volatile.LoadUint32(&o.HSTIMER1_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSTIMER1_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.HSTIMER1_VALUE.Reg) & 0xfffff +} + +// LEDC.HSTIMER2_CONF +func (o *LEDC_Type) SetHSTIMER2_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.HSTIMER2_CONF.Reg, volatile.LoadUint32(&o.HSTIMER2_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetHSTIMER2_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.HSTIMER2_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetHSTIMER2_CONF_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.HSTIMER2_CONF.Reg, volatile.LoadUint32(&o.HSTIMER2_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetHSTIMER2_CONF_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.HSTIMER2_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetHSTIMER2_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.HSTIMER2_CONF.Reg, volatile.LoadUint32(&o.HSTIMER2_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetHSTIMER2_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.HSTIMER2_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetHSTIMER2_CONF_RST(value uint32) { + volatile.StoreUint32(&o.HSTIMER2_CONF.Reg, volatile.LoadUint32(&o.HSTIMER2_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetHSTIMER2_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.HSTIMER2_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetHSTIMER2_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.HSTIMER2_CONF.Reg, volatile.LoadUint32(&o.HSTIMER2_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetHSTIMER2_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.HSTIMER2_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.HSTIMER2_VALUE +func (o *LEDC_Type) SetHSTIMER2_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.HSTIMER2_VALUE.Reg, volatile.LoadUint32(&o.HSTIMER2_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSTIMER2_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.HSTIMER2_VALUE.Reg) & 0xfffff +} + +// LEDC.HSTIMER3_CONF +func (o *LEDC_Type) SetHSTIMER3_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.HSTIMER3_CONF.Reg, volatile.LoadUint32(&o.HSTIMER3_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetHSTIMER3_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.HSTIMER3_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetHSTIMER3_CONF_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.HSTIMER3_CONF.Reg, volatile.LoadUint32(&o.HSTIMER3_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetHSTIMER3_CONF_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.HSTIMER3_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetHSTIMER3_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.HSTIMER3_CONF.Reg, volatile.LoadUint32(&o.HSTIMER3_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetHSTIMER3_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.HSTIMER3_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetHSTIMER3_CONF_RST(value uint32) { + volatile.StoreUint32(&o.HSTIMER3_CONF.Reg, volatile.LoadUint32(&o.HSTIMER3_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetHSTIMER3_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.HSTIMER3_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetHSTIMER3_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.HSTIMER3_CONF.Reg, volatile.LoadUint32(&o.HSTIMER3_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetHSTIMER3_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.HSTIMER3_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.HSTIMER3_VALUE +func (o *LEDC_Type) SetHSTIMER3_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.HSTIMER3_VALUE.Reg, volatile.LoadUint32(&o.HSTIMER3_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetHSTIMER3_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.HSTIMER3_VALUE.Reg) & 0xfffff +} + +// LEDC.LSTIMER0_CONF +func (o *LEDC_Type) SetLSTIMER0_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.LSTIMER0_CONF.Reg, volatile.LoadUint32(&o.LSTIMER0_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetLSTIMER0_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.LSTIMER0_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetLSTIMER0_CONF_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LSTIMER0_CONF.Reg, volatile.LoadUint32(&o.LSTIMER0_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetLSTIMER0_CONF_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LSTIMER0_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetLSTIMER0_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.LSTIMER0_CONF.Reg, volatile.LoadUint32(&o.LSTIMER0_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetLSTIMER0_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.LSTIMER0_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetLSTIMER0_CONF_RST(value uint32) { + volatile.StoreUint32(&o.LSTIMER0_CONF.Reg, volatile.LoadUint32(&o.LSTIMER0_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetLSTIMER0_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.LSTIMER0_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetLSTIMER0_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.LSTIMER0_CONF.Reg, volatile.LoadUint32(&o.LSTIMER0_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetLSTIMER0_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.LSTIMER0_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetLSTIMER0_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSTIMER0_CONF.Reg, volatile.LoadUint32(&o.LSTIMER0_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetLSTIMER0_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSTIMER0_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.LSTIMER0_VALUE +func (o *LEDC_Type) SetLSTIMER0_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.LSTIMER0_VALUE.Reg, volatile.LoadUint32(&o.LSTIMER0_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSTIMER0_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.LSTIMER0_VALUE.Reg) & 0xfffff +} + +// LEDC.LSTIMER1_CONF +func (o *LEDC_Type) SetLSTIMER1_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.LSTIMER1_CONF.Reg, volatile.LoadUint32(&o.LSTIMER1_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetLSTIMER1_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.LSTIMER1_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetLSTIMER1_CONF_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LSTIMER1_CONF.Reg, volatile.LoadUint32(&o.LSTIMER1_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetLSTIMER1_CONF_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LSTIMER1_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetLSTIMER1_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.LSTIMER1_CONF.Reg, volatile.LoadUint32(&o.LSTIMER1_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetLSTIMER1_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.LSTIMER1_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetLSTIMER1_CONF_RST(value uint32) { + volatile.StoreUint32(&o.LSTIMER1_CONF.Reg, volatile.LoadUint32(&o.LSTIMER1_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetLSTIMER1_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.LSTIMER1_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetLSTIMER1_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.LSTIMER1_CONF.Reg, volatile.LoadUint32(&o.LSTIMER1_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetLSTIMER1_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.LSTIMER1_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetLSTIMER1_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSTIMER1_CONF.Reg, volatile.LoadUint32(&o.LSTIMER1_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetLSTIMER1_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSTIMER1_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.LSTIMER1_VALUE +func (o *LEDC_Type) SetLSTIMER1_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.LSTIMER1_VALUE.Reg, volatile.LoadUint32(&o.LSTIMER1_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSTIMER1_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.LSTIMER1_VALUE.Reg) & 0xfffff +} + +// LEDC.LSTIMER2_CONF +func (o *LEDC_Type) SetLSTIMER2_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.LSTIMER2_CONF.Reg, volatile.LoadUint32(&o.LSTIMER2_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetLSTIMER2_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.LSTIMER2_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetLSTIMER2_CONF_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LSTIMER2_CONF.Reg, volatile.LoadUint32(&o.LSTIMER2_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetLSTIMER2_CONF_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LSTIMER2_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetLSTIMER2_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.LSTIMER2_CONF.Reg, volatile.LoadUint32(&o.LSTIMER2_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetLSTIMER2_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.LSTIMER2_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetLSTIMER2_CONF_RST(value uint32) { + volatile.StoreUint32(&o.LSTIMER2_CONF.Reg, volatile.LoadUint32(&o.LSTIMER2_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetLSTIMER2_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.LSTIMER2_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetLSTIMER2_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.LSTIMER2_CONF.Reg, volatile.LoadUint32(&o.LSTIMER2_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetLSTIMER2_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.LSTIMER2_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetLSTIMER2_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSTIMER2_CONF.Reg, volatile.LoadUint32(&o.LSTIMER2_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetLSTIMER2_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSTIMER2_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.LSTIMER2_VALUE +func (o *LEDC_Type) SetLSTIMER2_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.LSTIMER2_VALUE.Reg, volatile.LoadUint32(&o.LSTIMER2_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSTIMER2_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.LSTIMER2_VALUE.Reg) & 0xfffff +} + +// LEDC.LSTIMER3_CONF +func (o *LEDC_Type) SetLSTIMER3_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.LSTIMER3_CONF.Reg, volatile.LoadUint32(&o.LSTIMER3_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetLSTIMER3_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.LSTIMER3_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetLSTIMER3_CONF_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LSTIMER3_CONF.Reg, volatile.LoadUint32(&o.LSTIMER3_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetLSTIMER3_CONF_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LSTIMER3_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetLSTIMER3_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.LSTIMER3_CONF.Reg, volatile.LoadUint32(&o.LSTIMER3_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetLSTIMER3_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.LSTIMER3_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetLSTIMER3_CONF_RST(value uint32) { + volatile.StoreUint32(&o.LSTIMER3_CONF.Reg, volatile.LoadUint32(&o.LSTIMER3_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetLSTIMER3_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.LSTIMER3_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetLSTIMER3_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.LSTIMER3_CONF.Reg, volatile.LoadUint32(&o.LSTIMER3_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetLSTIMER3_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.LSTIMER3_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetLSTIMER3_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.LSTIMER3_CONF.Reg, volatile.LoadUint32(&o.LSTIMER3_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetLSTIMER3_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.LSTIMER3_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.LSTIMER3_VALUE +func (o *LEDC_Type) SetLSTIMER3_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.LSTIMER3_VALUE.Reg, volatile.LoadUint32(&o.LSTIMER3_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetLSTIMER3_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.LSTIMER3_VALUE.Reg) & 0xfffff +} + +// LEDC.INT_RAW +func (o *LEDC_Type) SetINT_RAW_HSTIMER0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_RAW_HSTIMER0_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_RAW_HSTIMER1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_RAW_HSTIMER1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_RAW_HSTIMER2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_RAW_HSTIMER2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_RAW_HSTIMER3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_RAW_HSTIMER3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_RAW_LSTIMER0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_RAW_LSTIMER0_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_RAW_LSTIMER1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_RAW_LSTIMER1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_RAW_LSTIMER2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_RAW_LSTIMER2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_RAW_LSTIMER3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_RAW_LSTIMER3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_HSCH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_HSCH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_HSCH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_HSCH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_HSCH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_HSCH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_HSCH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_HSCH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_HSCH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_HSCH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_HSCH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_HSCH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_HSCH6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_HSCH6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_HSCH7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_HSCH7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} + +// LEDC.INT_ST +func (o *LEDC_Type) SetINT_ST_HSTIMER0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ST_HSTIMER0_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ST_HSTIMER1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ST_HSTIMER1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ST_HSTIMER2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ST_HSTIMER2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ST_HSTIMER3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ST_HSTIMER3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ST_LSTIMER0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ST_LSTIMER0_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ST_LSTIMER1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ST_LSTIMER1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ST_LSTIMER2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ST_LSTIMER2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ST_LSTIMER3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ST_LSTIMER3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_HSCH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_HSCH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_HSCH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_HSCH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_HSCH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_HSCH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_HSCH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_HSCH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_HSCH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_HSCH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_HSCH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_HSCH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_HSCH6_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_HSCH6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_HSCH7_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_HSCH7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH6_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH7_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23 +} + +// LEDC.INT_ENA +func (o *LEDC_Type) SetINT_ENA_HSTIMER0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ENA_HSTIMER0_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ENA_HSTIMER1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ENA_HSTIMER1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ENA_HSTIMER2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ENA_HSTIMER2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ENA_HSTIMER3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ENA_HSTIMER3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ENA_LSTIMER0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ENA_LSTIMER0_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ENA_LSTIMER1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ENA_LSTIMER1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ENA_LSTIMER2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ENA_LSTIMER2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ENA_LSTIMER3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ENA_LSTIMER3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_HSCH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_HSCH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_HSCH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_HSCH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_HSCH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_HSCH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_HSCH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_HSCH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_HSCH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_HSCH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_HSCH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_HSCH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_HSCH6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_HSCH6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_HSCH7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_HSCH7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23 +} + +// LEDC.INT_CLR +func (o *LEDC_Type) SetINT_CLR_HSTIMER0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_CLR_HSTIMER0_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_CLR_HSTIMER1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_CLR_HSTIMER1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_CLR_HSTIMER2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_CLR_HSTIMER2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_CLR_HSTIMER3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_CLR_HSTIMER3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_CLR_LSTIMER0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_CLR_LSTIMER0_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_CLR_LSTIMER1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_CLR_LSTIMER1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_CLR_LSTIMER2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_CLR_LSTIMER2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_CLR_LSTIMER3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_CLR_LSTIMER3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_HSCH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_HSCH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_HSCH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_HSCH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_HSCH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_HSCH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_HSCH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_HSCH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_HSCH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_HSCH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_HSCH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_HSCH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_HSCH6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_HSCH6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_HSCH7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_HSCH7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23 +} + +// LEDC.CONF +func (o *LEDC_Type) SetCONF_APB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCONF_APB_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} + +// LEDC.DATE +func (o *LEDC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *LEDC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Motor Control Pulse-Width Modulation 0 +type MCPWM_Type struct { + CLK_CFG volatile.Register32 // 0x0 + TIMER0_CFG0 volatile.Register32 // 0x4 + TIMER0_CFG1 volatile.Register32 // 0x8 + TIMER0_SYNC volatile.Register32 // 0xC + TIMER0_STATUS volatile.Register32 // 0x10 + TIMER1_CFG0 volatile.Register32 // 0x14 + TIMER1_CFG1 volatile.Register32 // 0x18 + TIMER1_SYNC volatile.Register32 // 0x1C + TIMER1_STATUS volatile.Register32 // 0x20 + TIMER2_CFG0 volatile.Register32 // 0x24 + TIMER2_CFG1 volatile.Register32 // 0x28 + TIMER2_SYNC volatile.Register32 // 0x2C + TIMER2_STATUS volatile.Register32 // 0x30 + TIMER_SYNCI_CFG volatile.Register32 // 0x34 + OPERATOR_TIMERSEL volatile.Register32 // 0x38 + GEN0_STMP_CFG volatile.Register32 // 0x3C + GEN0_TSTMP_A volatile.Register32 // 0x40 + GEN0_TSTMP_B volatile.Register32 // 0x44 + GEN0_CFG0 volatile.Register32 // 0x48 + GEN0_FORCE volatile.Register32 // 0x4C + GEN0_A volatile.Register32 // 0x50 + GEN0_B volatile.Register32 // 0x54 + DT0_CFG volatile.Register32 // 0x58 + DT0_FED_CFG volatile.Register32 // 0x5C + DT0_RED_CFG volatile.Register32 // 0x60 + CARRIER0_CFG volatile.Register32 // 0x64 + FH0_CFG0 volatile.Register32 // 0x68 + FH0_CFG1 volatile.Register32 // 0x6C + FH0_STATUS volatile.Register32 // 0x70 + GEN1_STMP_CFG volatile.Register32 // 0x74 + GEN1_TSTMP_A volatile.Register32 // 0x78 + GEN1_TSTMP_B volatile.Register32 // 0x7C + GEN1_CFG0 volatile.Register32 // 0x80 + GEN1_FORCE volatile.Register32 // 0x84 + GEN1_A volatile.Register32 // 0x88 + GEN1_B volatile.Register32 // 0x8C + DT1_CFG volatile.Register32 // 0x90 + DT1_FED_CFG volatile.Register32 // 0x94 + DT1_RED_CFG volatile.Register32 // 0x98 + CARRIER1_CFG volatile.Register32 // 0x9C + FH1_CFG0 volatile.Register32 // 0xA0 + FH1_CFG1 volatile.Register32 // 0xA4 + FH1_STATUS volatile.Register32 // 0xA8 + GEN2_STMP_CFG volatile.Register32 // 0xAC + GEN2_TSTMP_A volatile.Register32 // 0xB0 + GEN2_TSTMP_B volatile.Register32 // 0xB4 + GEN2_CFG0 volatile.Register32 // 0xB8 + GEN2_FORCE volatile.Register32 // 0xBC + GEN2_A volatile.Register32 // 0xC0 + GEN2_B volatile.Register32 // 0xC4 + DT2_CFG volatile.Register32 // 0xC8 + DT2_FED_CFG volatile.Register32 // 0xCC + DT2_RED_CFG volatile.Register32 // 0xD0 + CARRIER2_CFG volatile.Register32 // 0xD4 + FH2_CFG0 volatile.Register32 // 0xD8 + FH2_CFG1 volatile.Register32 // 0xDC + FH2_STATUS volatile.Register32 // 0xE0 + FAULT_DETECT volatile.Register32 // 0xE4 + CAP_TIMER_CFG volatile.Register32 // 0xE8 + CAP_TIMER_PHASE volatile.Register32 // 0xEC + CAP_CH0_CFG volatile.Register32 // 0xF0 + CAP_CH1_CFG volatile.Register32 // 0xF4 + CAP_CH2_CFG volatile.Register32 // 0xF8 + CAP_CH0 volatile.Register32 // 0xFC + CAP_CH1 volatile.Register32 // 0x100 + CAP_CH2 volatile.Register32 // 0x104 + CAP_STATUS volatile.Register32 // 0x108 + UPDATE_CFG volatile.Register32 // 0x10C + INT_ENA volatile.Register32 // 0x110 + INT_RAW volatile.Register32 // 0x114 + INT_ST volatile.Register32 // 0x118 + INT_CLR volatile.Register32 // 0x11C + CLK volatile.Register32 // 0x120 + VERSION volatile.Register32 // 0x124 +} + +// MCPWM.CLK_CFG +func (o *MCPWM_Type) SetCLK_CFG_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetCLK_CFG_CLK_PRESCALE() uint32 { + return volatile.LoadUint32(&o.CLK_CFG.Reg) & 0xff +} + +// MCPWM.TIMER0_CFG0 +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER0_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER0_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER0_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER0_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER0_CFG1 +func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER0_START(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER0_START() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER0_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER0_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER0_SYNC +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER0_STATUS +func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER0_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER0_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER0_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER0_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER1_CFG0 +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER1_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER1_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER1_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER1_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER1_CFG1 +func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER1_START(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER1_START() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER1_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER1_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER1_SYNC +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER1_STATUS +func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER1_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER1_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER1_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER1_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER2_CFG0 +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER2_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER2_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER2_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER2_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER2_CFG1 +func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER2_START(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER2_START() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER2_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER2_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER2_SYNC +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER2_STATUS +func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER2_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER2_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER2_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER2_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER_SYNCI_CFG +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER0_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER0_SYNCISEL() uint32 { + return volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER1_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x38)|value<<3) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER1_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x38) >> 3 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER2_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x1c0)|value<<6) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER2_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x1c0) >> 6 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x800) >> 11 +} + +// MCPWM.OPERATOR_TIMERSEL +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL() uint32 { + return volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x3 +} +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x30) >> 4 +} + +// MCPWM.GEN0_STMP_CFG +func (o *MCPWM_Type) SetGEN0_STMP_CFG_GEN0_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_GEN0_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_GEN0_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_GEN0_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_GEN0_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_GEN0_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_GEN0_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_GEN0_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN0_TSTMP_A +func (o *MCPWM_Type) SetGEN0_TSTMP_A_GEN0_A(value uint32) { + volatile.StoreUint32(&o.GEN0_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN0_TSTMP_A_GEN0_A() uint32 { + return volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN0_TSTMP_B +func (o *MCPWM_Type) SetGEN0_TSTMP_B_GEN0_B(value uint32) { + volatile.StoreUint32(&o.GEN0_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN0_TSTMP_B_GEN0_B() uint32 { + return volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN0_CFG0 +func (o *MCPWM_Type) SetGEN0_CFG0_GEN0_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN0_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN0_CFG0_GEN0_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN0_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN0_CFG0_GEN0_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN0_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN0_FORCE +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN0_A +func (o *MCPWM_Type) SetGEN0_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN0_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN0_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN0_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN0_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN0_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN0_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN0_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN0_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN0_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN0_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN0_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN0_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN0_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN0_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN0_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN0_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN0_B +func (o *MCPWM_Type) SetGEN0_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN0_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN0_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN0_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN0_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN0_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN0_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN0_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN0_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN0_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN0_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN0_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN0_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN0_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN0_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN0_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN0_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT0_CFG +func (o *MCPWM_Type) SetDT0_CFG_DT0_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT0_CFG_DT0_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT0_CFG_DT0_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT0_FED_CFG +func (o *MCPWM_Type) SetDT0_FED_CFG_DT0_FED(value uint32) { + volatile.StoreUint32(&o.DT0_FED_CFG.Reg, volatile.LoadUint32(&o.DT0_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT0_FED_CFG_DT0_FED() uint32 { + return volatile.LoadUint32(&o.DT0_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT0_RED_CFG +func (o *MCPWM_Type) SetDT0_RED_CFG_DT0_RED(value uint32) { + volatile.StoreUint32(&o.DT0_RED_CFG.Reg, volatile.LoadUint32(&o.DT0_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT0_RED_CFG_DT0_RED() uint32 { + return volatile.LoadUint32(&o.DT0_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER0_CFG +func (o *MCPWM_Type) SetCARRIER0_CFG_CARRIER0_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CARRIER0_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CARRIER0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CARRIER0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CARRIER0_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CARRIER0_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CARRIER0_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CARRIER0_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CARRIER0_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CARRIER0_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CARRIER0_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CARRIER0_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH0_CFG0 +func (o *MCPWM_Type) SetFH0_CFG0_FH0_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH0_CFG0_FH0_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH0_CFG0_FH0_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH0_CFG1 +func (o *MCPWM_Type) SetFH0_CFG1_FH0_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_CFG1_FH0_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_CFG1_FH0_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH0_CFG1_FH0_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH0_CFG1_FH0_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH0_CFG1_FH0_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH0_CFG1_FH0_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH0_CFG1_FH0_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH0_STATUS +func (o *MCPWM_Type) SetFH0_STATUS_FH0_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_STATUS_FH0_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_STATUS_FH0_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH0_STATUS_FH0_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.GEN1_STMP_CFG +func (o *MCPWM_Type) SetGEN1_STMP_CFG_GEN1_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_GEN1_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_GEN1_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_GEN1_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_GEN1_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_GEN1_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_GEN1_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_GEN1_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN1_TSTMP_A +func (o *MCPWM_Type) SetGEN1_TSTMP_A_GEN1_A(value uint32) { + volatile.StoreUint32(&o.GEN1_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN1_TSTMP_A_GEN1_A() uint32 { + return volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN1_TSTMP_B +func (o *MCPWM_Type) SetGEN1_TSTMP_B_GEN1_B(value uint32) { + volatile.StoreUint32(&o.GEN1_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN1_TSTMP_B_GEN1_B() uint32 { + return volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN1_CFG0 +func (o *MCPWM_Type) SetGEN1_CFG0_GEN1_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN1_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN1_CFG0_GEN1_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN1_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN1_CFG0_GEN1_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN1_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN1_FORCE +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN1_A +func (o *MCPWM_Type) SetGEN1_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN1_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN1_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN1_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN1_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN1_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN1_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN1_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN1_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN1_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN1_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN1_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN1_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN1_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN1_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN1_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN1_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN1_B +func (o *MCPWM_Type) SetGEN1_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN1_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN1_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN1_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN1_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN1_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN1_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN1_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN1_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN1_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN1_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN1_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN1_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN1_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN1_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN1_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN1_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT1_CFG +func (o *MCPWM_Type) SetDT1_CFG_DT1_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT1_CFG_DT1_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT1_CFG_DT1_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT1_FED_CFG +func (o *MCPWM_Type) SetDT1_FED_CFG_DT1_FED(value uint32) { + volatile.StoreUint32(&o.DT1_FED_CFG.Reg, volatile.LoadUint32(&o.DT1_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT1_FED_CFG_DT1_FED() uint32 { + return volatile.LoadUint32(&o.DT1_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT1_RED_CFG +func (o *MCPWM_Type) SetDT1_RED_CFG_DT1_RED(value uint32) { + volatile.StoreUint32(&o.DT1_RED_CFG.Reg, volatile.LoadUint32(&o.DT1_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT1_RED_CFG_DT1_RED() uint32 { + return volatile.LoadUint32(&o.DT1_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER1_CFG +func (o *MCPWM_Type) SetCARRIER1_CFG_CARRIER1_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CARRIER1_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CARRIER1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CARRIER1_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CARRIER1_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CARRIER1_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CARRIER1_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CARRIER1_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CARRIER1_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CARRIER1_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CARRIER1_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CARRIER1_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH1_CFG0 +func (o *MCPWM_Type) SetFH1_CFG0_FH1_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH1_CFG0_FH1_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH1_CFG0_FH1_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH1_CFG1 +func (o *MCPWM_Type) SetFH1_CFG1_FH1_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_CFG1_FH1_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_CFG1_FH1_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH1_CFG1_FH1_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH1_CFG1_FH1_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH1_CFG1_FH1_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH1_CFG1_FH1_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH1_CFG1_FH1_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH1_STATUS +func (o *MCPWM_Type) SetFH1_STATUS_FH1_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_STATUS_FH1_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_STATUS_FH1_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH1_STATUS_FH1_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.GEN2_STMP_CFG +func (o *MCPWM_Type) SetGEN2_STMP_CFG_GEN2_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_GEN2_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_GEN2_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_GEN2_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_GEN2_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_GEN2_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_GEN2_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_GEN2_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN2_TSTMP_A +func (o *MCPWM_Type) SetGEN2_TSTMP_A_GEN2_A(value uint32) { + volatile.StoreUint32(&o.GEN2_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN2_TSTMP_A_GEN2_A() uint32 { + return volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN2_TSTMP_B +func (o *MCPWM_Type) SetGEN2_TSTMP_B_GEN2_B(value uint32) { + volatile.StoreUint32(&o.GEN2_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN2_TSTMP_B_GEN2_B() uint32 { + return volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN2_CFG0 +func (o *MCPWM_Type) SetGEN2_CFG0_GEN2_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN2_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN2_CFG0_GEN2_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN2_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN2_CFG0_GEN2_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN2_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN2_FORCE +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN2_A +func (o *MCPWM_Type) SetGEN2_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN2_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN2_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN2_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN2_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN2_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN2_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN2_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN2_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN2_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN2_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN2_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN2_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN2_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN2_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN2_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN2_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN2_B +func (o *MCPWM_Type) SetGEN2_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN2_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN2_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN2_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN2_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN2_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN2_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN2_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN2_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN2_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN2_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN2_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN2_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN2_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN2_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN2_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN2_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT2_CFG +func (o *MCPWM_Type) SetDT2_CFG_DT2_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT2_CFG_DT2_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT2_CFG_DT2_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT2_FED_CFG +func (o *MCPWM_Type) SetDT2_FED_CFG_DT2_FED(value uint32) { + volatile.StoreUint32(&o.DT2_FED_CFG.Reg, volatile.LoadUint32(&o.DT2_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT2_FED_CFG_DT2_FED() uint32 { + return volatile.LoadUint32(&o.DT2_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT2_RED_CFG +func (o *MCPWM_Type) SetDT2_RED_CFG_DT2_RED(value uint32) { + volatile.StoreUint32(&o.DT2_RED_CFG.Reg, volatile.LoadUint32(&o.DT2_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT2_RED_CFG_DT2_RED() uint32 { + return volatile.LoadUint32(&o.DT2_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER2_CFG +func (o *MCPWM_Type) SetCARRIER2_CFG_CARRIER2_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CARRIER2_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CARRIER2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CARRIER2_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CARRIER2_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CARRIER2_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CARRIER2_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CARRIER2_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CARRIER2_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CARRIER2_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CARRIER2_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CARRIER2_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH2_CFG0 +func (o *MCPWM_Type) SetFH2_CFG0_FH2_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH2_CFG0_FH2_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH2_CFG0_FH2_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH2_CFG1 +func (o *MCPWM_Type) SetFH2_CFG1_FH2_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_CFG1_FH2_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_CFG1_FH2_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH2_CFG1_FH2_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH2_CFG1_FH2_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH2_CFG1_FH2_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH2_CFG1_FH2_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH2_CFG1_FH2_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH2_STATUS +func (o *MCPWM_Type) SetFH2_STATUS_FH2_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_STATUS_FH2_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_STATUS_FH2_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH2_STATUS_FH2_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.FAULT_DETECT +func (o *MCPWM_Type) SetFAULT_DETECT_F0_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F0_EN() uint32 { + return volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F1_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F1_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F2_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F2_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F0_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F0_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F1_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F1_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F2_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F2_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F0(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F0() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F1(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F1() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F2(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F2() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x100) >> 8 +} + +// MCPWM.CAP_TIMER_CFG +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_TIMER_EN() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_EN() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_SEL(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1c)|value<<2) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_SEL() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1c) >> 2 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x20) >> 5 +} + +// MCPWM.CAP_TIMER_PHASE +func (o *MCPWM_Type) SetCAP_TIMER_PHASE(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_PHASE.Reg, value) +} +func (o *MCPWM_Type) GetCAP_TIMER_PHASE() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_PHASE.Reg) +} + +// MCPWM.CAP_CH0_CFG +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH1_CFG +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH2_CFG +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH0 +func (o *MCPWM_Type) SetCAP_CH0(value uint32) { + volatile.StoreUint32(&o.CAP_CH0.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH0() uint32 { + return volatile.LoadUint32(&o.CAP_CH0.Reg) +} + +// MCPWM.CAP_CH1 +func (o *MCPWM_Type) SetCAP_CH1(value uint32) { + volatile.StoreUint32(&o.CAP_CH1.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH1() uint32 { + return volatile.LoadUint32(&o.CAP_CH1.Reg) +} + +// MCPWM.CAP_CH2 +func (o *MCPWM_Type) SetCAP_CH2(value uint32) { + volatile.StoreUint32(&o.CAP_CH2.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH2() uint32 { + return volatile.LoadUint32(&o.CAP_CH2.Reg) +} + +// MCPWM.CAP_STATUS +func (o *MCPWM_Type) SetCAP_STATUS_CAP0_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP0_EDGE() uint32 { + return volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_STATUS_CAP1_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP1_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetCAP_STATUS_CAP2_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP2_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x4) >> 2 +} + +// MCPWM.UPDATE_CFG +func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_UP_EN() uint32 { + return volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP0_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP0_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP0_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP0_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP1_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP1_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP1_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP1_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP2_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP2_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP2_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP2_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x80) >> 7 +} + +// MCPWM.INT_ENA +func (o *MCPWM_Type) SetINT_ENA_TIMER0_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_STOP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT0_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT0_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT1_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT1_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT2_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT2_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_ENA_OP0_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_ENA_OP0_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_ENA_OP1_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_ENA_OP1_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_ENA_OP2_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_ENA_OP2_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_ENA_OP0_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_ENA_OP0_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_ENA_OP1_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_ENA_OP1_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_ENA_OP2_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_ENA_OP2_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_ENA_FH0_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_ENA_FH0_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_ENA_FH1_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_ENA_FH1_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_ENA_FH2_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_ENA_FH2_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_ENA_FH0_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_ENA_FH0_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_ENA_FH1_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_ENA_FH1_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_ENA_FH2_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_ENA_FH2_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_ENA_CAP0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_ENA_CAP0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_ENA_CAP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_ENA_CAP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_ENA_CAP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_ENA_CAP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_RAW +func (o *MCPWM_Type) SetINT_RAW_TIMER0_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_STOP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT0_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT0_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT1_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT1_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT2_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT2_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_RAW_OP0_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_RAW_OP0_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_RAW_OP1_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_RAW_OP1_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_RAW_OP2_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_RAW_OP2_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_RAW_OP0_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_RAW_OP0_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_RAW_OP1_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_RAW_OP1_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_RAW_OP2_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_RAW_OP2_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_RAW_FH0_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_RAW_FH0_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_RAW_FH1_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_RAW_FH1_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_RAW_FH2_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_RAW_FH2_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_RAW_FH0_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_RAW_FH0_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_RAW_FH1_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_RAW_FH1_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_RAW_FH2_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_RAW_FH2_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_RAW_CAP0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_RAW_CAP0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_RAW_CAP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_RAW_CAP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_RAW_CAP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_RAW_CAP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_ST +func (o *MCPWM_Type) SetINT_ST_TIMER0_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_STOP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_ST_TIMER0_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_ST_TIMER0_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_ST_FAULT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_ST_FAULT0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_ST_FAULT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_ST_FAULT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_ST_FAULT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_ST_FAULT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_ST_FAULT0_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_ST_FAULT0_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_ST_FAULT1_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_ST_FAULT1_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_ST_FAULT2_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_ST_FAULT2_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_ST_OP0_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_ST_OP0_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_ST_OP1_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_ST_OP1_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_ST_OP2_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_ST_OP2_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_ST_OP0_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_ST_OP0_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_ST_OP1_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_ST_OP1_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_ST_OP2_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_ST_OP2_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_ST_FH0_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_ST_FH0_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_ST_FH1_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_ST_FH1_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_ST_FH2_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_ST_FH2_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_ST_FH0_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_ST_FH0_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_ST_FH1_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_ST_FH1_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_ST_FH2_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_ST_FH2_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_ST_CAP0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_ST_CAP0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_ST_CAP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_ST_CAP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_ST_CAP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_ST_CAP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_CLR +func (o *MCPWM_Type) SetINT_CLR_TIMER0_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_STOP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT0_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT0_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT1_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT1_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT2_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT2_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_CLR_OP0_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_CLR_OP0_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_CLR_OP1_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_CLR_OP1_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_CLR_OP2_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_CLR_OP2_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_CLR_OP0_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_CLR_OP0_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_CLR_OP1_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_CLR_OP1_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_CLR_OP2_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_CLR_OP2_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_CLR_FH0_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_CLR_FH0_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_CLR_FH1_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_CLR_FH1_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_CLR_FH2_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_CLR_FH2_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_CLR_FH0_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_CLR_FH0_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_CLR_FH1_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_CLR_FH1_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_CLR_FH2_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_CLR_FH2_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_CLR_CAP0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_CLR_CAP0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_CLR_CAP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_CLR_CAP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_CLR_CAP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_CLR_CAP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} + +// MCPWM.CLK +func (o *MCPWM_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} + +// MCPWM.VERSION +func (o *MCPWM_Type) SetVERSION_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *MCPWM_Type) GetVERSION_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// NRX Peripheral +type NRX_Type struct { + _ [212]byte + NRXPD_CTRL volatile.Register32 // 0xD4 +} + +// NRX.NRXPD_CTRL: WiFi RX control register +func (o *NRX_Type) SetNRXPD_CTRL_DEMAP_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.NRXPD_CTRL.Reg, volatile.LoadUint32(&o.NRXPD_CTRL.Reg)&^(0x1)|value) +} +func (o *NRX_Type) GetNRXPD_CTRL_DEMAP_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.NRXPD_CTRL.Reg) & 0x1 +} +func (o *NRX_Type) SetNRXPD_CTRL_DEMAP_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.NRXPD_CTRL.Reg, volatile.LoadUint32(&o.NRXPD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *NRX_Type) GetNRXPD_CTRL_DEMAP_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.NRXPD_CTRL.Reg) & 0x2) >> 1 +} +func (o *NRX_Type) SetNRXPD_CTRL_VIT_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.NRXPD_CTRL.Reg, volatile.LoadUint32(&o.NRXPD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *NRX_Type) GetNRXPD_CTRL_VIT_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.NRXPD_CTRL.Reg) & 0x4) >> 2 +} +func (o *NRX_Type) SetNRXPD_CTRL_VIT_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.NRXPD_CTRL.Reg, volatile.LoadUint32(&o.NRXPD_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *NRX_Type) GetNRXPD_CTRL_VIT_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.NRXPD_CTRL.Reg) & 0x8) >> 3 +} +func (o *NRX_Type) SetNRXPD_CTRL_RX_ROT_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.NRXPD_CTRL.Reg, volatile.LoadUint32(&o.NRXPD_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *NRX_Type) GetNRXPD_CTRL_RX_ROT_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.NRXPD_CTRL.Reg) & 0x10) >> 4 +} +func (o *NRX_Type) SetNRXPD_CTRL_RX_ROT_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.NRXPD_CTRL.Reg, volatile.LoadUint32(&o.NRXPD_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *NRX_Type) GetNRXPD_CTRL_RX_ROT_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.NRXPD_CTRL.Reg) & 0x20) >> 5 +} +func (o *NRX_Type) SetNRXPD_CTRL_CHAN_EST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.NRXPD_CTRL.Reg, volatile.LoadUint32(&o.NRXPD_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *NRX_Type) GetNRXPD_CTRL_CHAN_EST_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.NRXPD_CTRL.Reg) & 0x40) >> 6 +} +func (o *NRX_Type) SetNRXPD_CTRL_CHAN_EST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.NRXPD_CTRL.Reg, volatile.LoadUint32(&o.NRXPD_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *NRX_Type) GetNRXPD_CTRL_CHAN_EST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.NRXPD_CTRL.Reg) & 0x80) >> 7 +} + +// Pulse Count Controller +type PCNT_Type struct { + U0_CONF0 volatile.Register32 // 0x0 + U0_CONF1 volatile.Register32 // 0x4 + U0_CONF2 volatile.Register32 // 0x8 + U1_CONF0 volatile.Register32 // 0xC + U1_CONF1 volatile.Register32 // 0x10 + U1_CONF2 volatile.Register32 // 0x14 + U2_CONF0 volatile.Register32 // 0x18 + U2_CONF1 volatile.Register32 // 0x1C + U2_CONF2 volatile.Register32 // 0x20 + U3_CONF0 volatile.Register32 // 0x24 + U3_CONF1 volatile.Register32 // 0x28 + U3_CONF2 volatile.Register32 // 0x2C + U4_CONF0 volatile.Register32 // 0x30 + U4_CONF1 volatile.Register32 // 0x34 + U4_CONF2 volatile.Register32 // 0x38 + U5_CONF0 volatile.Register32 // 0x3C + U5_CONF1 volatile.Register32 // 0x40 + U5_CONF2 volatile.Register32 // 0x44 + U6_CONF0 volatile.Register32 // 0x48 + U6_CONF1 volatile.Register32 // 0x4C + U6_CONF2 volatile.Register32 // 0x50 + U7_CONF0 volatile.Register32 // 0x54 + U7_CONF1 volatile.Register32 // 0x58 + U7_CONF2 volatile.Register32 // 0x5C + U0_CNT volatile.Register32 // 0x60 + U1_CNT volatile.Register32 // 0x64 + U2_CNT volatile.Register32 // 0x68 + U3_CNT volatile.Register32 // 0x6C + U4_CNT volatile.Register32 // 0x70 + U5_CNT volatile.Register32 // 0x74 + U6_CNT volatile.Register32 // 0x78 + U7_CNT volatile.Register32 // 0x7C + INT_RAW volatile.Register32 // 0x80 + INT_ST volatile.Register32 // 0x84 + INT_ENA volatile.Register32 // 0x88 + INT_CLR volatile.Register32 // 0x8C + U0_STATUS volatile.Register32 // 0x90 + U1_STATUS volatile.Register32 // 0x94 + U2_STATUS volatile.Register32 // 0x98 + U3_STATUS volatile.Register32 // 0x9C + U4_STATUS volatile.Register32 // 0xA0 + U5_STATUS volatile.Register32 // 0xA4 + U6_STATUS volatile.Register32 // 0xA8 + U7_STATUS volatile.Register32 // 0xAC + CTRL volatile.Register32 // 0xB0 + _ [72]byte + DATE volatile.Register32 // 0xFC +} + +// PCNT.U0_CONF0 +func (o *PCNT_Type) SetU0_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU0_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU0_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU0_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU0_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU0_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU0_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU0_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U0_CONF1 +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CONF2 +func (o *PCNT_Type) SetU0_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF0 +func (o *PCNT_Type) SetU1_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU1_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU1_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU1_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU1_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU1_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU1_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU1_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U1_CONF1 +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF2 +func (o *PCNT_Type) SetU1_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF0 +func (o *PCNT_Type) SetU2_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU2_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU2_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU2_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU2_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU2_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU2_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU2_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U2_CONF1 +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF2 +func (o *PCNT_Type) SetU2_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF0 +func (o *PCNT_Type) SetU3_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU3_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU3_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU3_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU3_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU3_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU3_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU3_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U3_CONF1 +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF2 +func (o *PCNT_Type) SetU3_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U4_CONF0 +func (o *PCNT_Type) SetU4_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU4_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU4_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU4_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU4_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU4_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU4_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU4_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU4_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU4_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU4_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU4_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU4_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU4_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU4_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU4_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU4_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU4_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU4_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU4_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU4_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU4_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU4_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU4_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU4_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU4_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU4_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU4_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU4_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U4_CONF0.Reg, volatile.LoadUint32(&o.U4_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU4_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U4_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U4_CONF1 +func (o *PCNT_Type) SetU4_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U4_CONF1.Reg, volatile.LoadUint32(&o.U4_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU4_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U4_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU4_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U4_CONF1.Reg, volatile.LoadUint32(&o.U4_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU4_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U4_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U4_CONF2 +func (o *PCNT_Type) SetU4_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U4_CONF2.Reg, volatile.LoadUint32(&o.U4_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU4_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U4_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU4_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U4_CONF2.Reg, volatile.LoadUint32(&o.U4_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU4_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U4_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U5_CONF0 +func (o *PCNT_Type) SetU5_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU5_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU5_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU5_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU5_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU5_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU5_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU5_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU5_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU5_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU5_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU5_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU5_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU5_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU5_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU5_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU5_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU5_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU5_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU5_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU5_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU5_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU5_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU5_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU5_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU5_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU5_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU5_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU5_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U5_CONF0.Reg, volatile.LoadUint32(&o.U5_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU5_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U5_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U5_CONF1 +func (o *PCNT_Type) SetU5_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U5_CONF1.Reg, volatile.LoadUint32(&o.U5_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU5_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U5_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU5_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U5_CONF1.Reg, volatile.LoadUint32(&o.U5_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU5_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U5_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U5_CONF2 +func (o *PCNT_Type) SetU5_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U5_CONF2.Reg, volatile.LoadUint32(&o.U5_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU5_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U5_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU5_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U5_CONF2.Reg, volatile.LoadUint32(&o.U5_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU5_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U5_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U6_CONF0 +func (o *PCNT_Type) SetU6_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU6_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU6_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU6_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU6_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU6_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU6_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU6_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU6_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU6_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU6_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU6_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU6_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU6_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU6_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU6_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU6_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU6_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU6_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU6_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU6_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU6_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU6_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU6_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU6_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU6_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU6_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU6_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU6_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U6_CONF0.Reg, volatile.LoadUint32(&o.U6_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU6_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U6_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U6_CONF1 +func (o *PCNT_Type) SetU6_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U6_CONF1.Reg, volatile.LoadUint32(&o.U6_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU6_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U6_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU6_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U6_CONF1.Reg, volatile.LoadUint32(&o.U6_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU6_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U6_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U6_CONF2 +func (o *PCNT_Type) SetU6_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U6_CONF2.Reg, volatile.LoadUint32(&o.U6_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU6_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U6_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU6_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U6_CONF2.Reg, volatile.LoadUint32(&o.U6_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU6_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U6_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U7_CONF0 +func (o *PCNT_Type) SetU7_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU7_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU7_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU7_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU7_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU7_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU7_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU7_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU7_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU7_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU7_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU7_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU7_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU7_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU7_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU7_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU7_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU7_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU7_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU7_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU7_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU7_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU7_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU7_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU7_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU7_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU7_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU7_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU7_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U7_CONF0.Reg, volatile.LoadUint32(&o.U7_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU7_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U7_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U7_CONF1 +func (o *PCNT_Type) SetU7_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U7_CONF1.Reg, volatile.LoadUint32(&o.U7_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU7_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U7_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU7_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U7_CONF1.Reg, volatile.LoadUint32(&o.U7_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU7_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U7_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U7_CONF2 +func (o *PCNT_Type) SetU7_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U7_CONF2.Reg, volatile.LoadUint32(&o.U7_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU7_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U7_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU7_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U7_CONF2.Reg, volatile.LoadUint32(&o.U7_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU7_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U7_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CNT +func (o *PCNT_Type) SetU0_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U0_CNT.Reg, volatile.LoadUint32(&o.U0_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U0_CNT.Reg) & 0xffff +} + +// PCNT.U1_CNT +func (o *PCNT_Type) SetU1_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U1_CNT.Reg, volatile.LoadUint32(&o.U1_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U1_CNT.Reg) & 0xffff +} + +// PCNT.U2_CNT +func (o *PCNT_Type) SetU2_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U2_CNT.Reg, volatile.LoadUint32(&o.U2_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U2_CNT.Reg) & 0xffff +} + +// PCNT.U3_CNT +func (o *PCNT_Type) SetU3_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U3_CNT.Reg, volatile.LoadUint32(&o.U3_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U3_CNT.Reg) & 0xffff +} + +// PCNT.U4_CNT +func (o *PCNT_Type) SetU4_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U4_CNT.Reg, volatile.LoadUint32(&o.U4_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU4_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U4_CNT.Reg) & 0xffff +} + +// PCNT.U5_CNT +func (o *PCNT_Type) SetU5_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U5_CNT.Reg, volatile.LoadUint32(&o.U5_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU5_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U5_CNT.Reg) & 0xffff +} + +// PCNT.U6_CNT +func (o *PCNT_Type) SetU6_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U6_CNT.Reg, volatile.LoadUint32(&o.U6_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU6_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U6_CNT.Reg) & 0xffff +} + +// PCNT.U7_CNT +func (o *PCNT_Type) SetU7_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U7_CNT.Reg, volatile.LoadUint32(&o.U7_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU7_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U7_CNT.Reg) & 0xffff +} + +// PCNT.INT_RAW +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U4(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U4() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U5(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U5() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U6(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U6() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U7(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U7() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} + +// PCNT.INT_ST +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U4(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U4() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U5(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U5() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U6(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U6() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U7(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U7() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} + +// PCNT.INT_ENA +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U4(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U4() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U5(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U5() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U6(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U6() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U7(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U7() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} + +// PCNT.INT_CLR +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U4(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U4() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U5(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U5() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U6(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U6() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U7(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U7() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} + +// PCNT.U0_STATUS +func (o *PCNT_Type) SetU0_STATUS(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, value) +} +func (o *PCNT_Type) GetU0_STATUS() uint32 { + return volatile.LoadUint32(&o.U0_STATUS.Reg) +} +func (o *PCNT_Type) SetU0_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU0_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU0_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU0_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU0_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU0_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU0_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU0_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU0_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU0_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U1_STATUS +func (o *PCNT_Type) SetU1_STATUS(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, value) +} +func (o *PCNT_Type) GetU1_STATUS() uint32 { + return volatile.LoadUint32(&o.U1_STATUS.Reg) +} +func (o *PCNT_Type) SetU1_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU1_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU1_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU1_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU1_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU1_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU1_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU1_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU1_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU1_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U2_STATUS +func (o *PCNT_Type) SetU2_STATUS(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, value) +} +func (o *PCNT_Type) GetU2_STATUS() uint32 { + return volatile.LoadUint32(&o.U2_STATUS.Reg) +} +func (o *PCNT_Type) SetU2_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU2_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU2_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU2_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU2_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU2_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU2_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU2_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU2_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU2_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U3_STATUS +func (o *PCNT_Type) SetU3_STATUS(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, value) +} +func (o *PCNT_Type) GetU3_STATUS() uint32 { + return volatile.LoadUint32(&o.U3_STATUS.Reg) +} +func (o *PCNT_Type) SetU3_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU3_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU3_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU3_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU3_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU3_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU3_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU3_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU3_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU3_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U4_STATUS +func (o *PCNT_Type) SetU4_STATUS(value uint32) { + volatile.StoreUint32(&o.U4_STATUS.Reg, value) +} +func (o *PCNT_Type) GetU4_STATUS() uint32 { + return volatile.LoadUint32(&o.U4_STATUS.Reg) +} +func (o *PCNT_Type) SetU4_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U4_STATUS.Reg, volatile.LoadUint32(&o.U4_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU4_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U4_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU4_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U4_STATUS.Reg, volatile.LoadUint32(&o.U4_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU4_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U4_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU4_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U4_STATUS.Reg, volatile.LoadUint32(&o.U4_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU4_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U4_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU4_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U4_STATUS.Reg, volatile.LoadUint32(&o.U4_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU4_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U4_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU4_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U4_STATUS.Reg, volatile.LoadUint32(&o.U4_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU4_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U4_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU4_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U4_STATUS.Reg, volatile.LoadUint32(&o.U4_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU4_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U4_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U5_STATUS +func (o *PCNT_Type) SetU5_STATUS(value uint32) { + volatile.StoreUint32(&o.U5_STATUS.Reg, value) +} +func (o *PCNT_Type) GetU5_STATUS() uint32 { + return volatile.LoadUint32(&o.U5_STATUS.Reg) +} +func (o *PCNT_Type) SetU5_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U5_STATUS.Reg, volatile.LoadUint32(&o.U5_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU5_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U5_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU5_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U5_STATUS.Reg, volatile.LoadUint32(&o.U5_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU5_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U5_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU5_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U5_STATUS.Reg, volatile.LoadUint32(&o.U5_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU5_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U5_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU5_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U5_STATUS.Reg, volatile.LoadUint32(&o.U5_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU5_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U5_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU5_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U5_STATUS.Reg, volatile.LoadUint32(&o.U5_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU5_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U5_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU5_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U5_STATUS.Reg, volatile.LoadUint32(&o.U5_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU5_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U5_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U6_STATUS +func (o *PCNT_Type) SetU6_STATUS(value uint32) { + volatile.StoreUint32(&o.U6_STATUS.Reg, value) +} +func (o *PCNT_Type) GetU6_STATUS() uint32 { + return volatile.LoadUint32(&o.U6_STATUS.Reg) +} +func (o *PCNT_Type) SetU6_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U6_STATUS.Reg, volatile.LoadUint32(&o.U6_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU6_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U6_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU6_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U6_STATUS.Reg, volatile.LoadUint32(&o.U6_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU6_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U6_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU6_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U6_STATUS.Reg, volatile.LoadUint32(&o.U6_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU6_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U6_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU6_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U6_STATUS.Reg, volatile.LoadUint32(&o.U6_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU6_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U6_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU6_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U6_STATUS.Reg, volatile.LoadUint32(&o.U6_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU6_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U6_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU6_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U6_STATUS.Reg, volatile.LoadUint32(&o.U6_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU6_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U6_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U7_STATUS +func (o *PCNT_Type) SetU7_STATUS(value uint32) { + volatile.StoreUint32(&o.U7_STATUS.Reg, value) +} +func (o *PCNT_Type) GetU7_STATUS() uint32 { + return volatile.LoadUint32(&o.U7_STATUS.Reg) +} +func (o *PCNT_Type) SetU7_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U7_STATUS.Reg, volatile.LoadUint32(&o.U7_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU7_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U7_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU7_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U7_STATUS.Reg, volatile.LoadUint32(&o.U7_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU7_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U7_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU7_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U7_STATUS.Reg, volatile.LoadUint32(&o.U7_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU7_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U7_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU7_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U7_STATUS.Reg, volatile.LoadUint32(&o.U7_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU7_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U7_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU7_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U7_STATUS.Reg, volatile.LoadUint32(&o.U7_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU7_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U7_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU7_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U7_STATUS.Reg, volatile.LoadUint32(&o.U7_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU7_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U7_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.CTRL +func (o *PCNT_Type) SetCTRL_CNT_RST_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U0() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U0() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U4(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U4() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U4(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U4() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U5(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U5() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U5(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U5() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U6(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U6() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U6(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U6() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U7(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U7() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U7(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U7() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetCTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *PCNT_Type) GetCTRL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} + +// PCNT.DATE +func (o *PCNT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *PCNT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Remote Control +type RMT_Type struct { + CH0DATA volatile.Register32 // 0x0 + CH1DATA volatile.Register32 // 0x4 + CH2DATA volatile.Register32 // 0x8 + CH3DATA volatile.Register32 // 0xC + CH4DATA volatile.Register32 // 0x10 + CH5DATA volatile.Register32 // 0x14 + CH6DATA volatile.Register32 // 0x18 + CH7DATA volatile.Register32 // 0x1C + CH0CONF0 volatile.Register32 // 0x20 + CH0CONF1 volatile.Register32 // 0x24 + CH1CONF0 volatile.Register32 // 0x28 + CH1CONF1 volatile.Register32 // 0x2C + CH2CONF0 volatile.Register32 // 0x30 + CH2CONF1 volatile.Register32 // 0x34 + CH3CONF0 volatile.Register32 // 0x38 + CH3CONF1 volatile.Register32 // 0x3C + CH4CONF0 volatile.Register32 // 0x40 + CH4CONF1 volatile.Register32 // 0x44 + CH5CONF0 volatile.Register32 // 0x48 + CH5CONF1 volatile.Register32 // 0x4C + CH6CONF0 volatile.Register32 // 0x50 + CH6CONF1 volatile.Register32 // 0x54 + CH7CONF0 volatile.Register32 // 0x58 + CH7CONF1 volatile.Register32 // 0x5C + CH0STATUS volatile.Register32 // 0x60 + CH1STATUS volatile.Register32 // 0x64 + CH2STATUS volatile.Register32 // 0x68 + CH3STATUS volatile.Register32 // 0x6C + CH4STATUS volatile.Register32 // 0x70 + CH5STATUS volatile.Register32 // 0x74 + CH6STATUS volatile.Register32 // 0x78 + CH7STATUS volatile.Register32 // 0x7C + CH0ADDR volatile.Register32 // 0x80 + CH1ADDR volatile.Register32 // 0x84 + CH2ADDR volatile.Register32 // 0x88 + CH3ADDR volatile.Register32 // 0x8C + CH4ADDR volatile.Register32 // 0x90 + CH5ADDR volatile.Register32 // 0x94 + CH6ADDR volatile.Register32 // 0x98 + CH7ADDR volatile.Register32 // 0x9C + INT_RAW volatile.Register32 // 0xA0 + INT_ST volatile.Register32 // 0xA4 + INT_ENA volatile.Register32 // 0xA8 + INT_CLR volatile.Register32 // 0xAC + CH0CARRIER_DUTY volatile.Register32 // 0xB0 + CH1CARRIER_DUTY volatile.Register32 // 0xB4 + CH2CARRIER_DUTY volatile.Register32 // 0xB8 + CH3CARRIER_DUTY volatile.Register32 // 0xBC + CH4CARRIER_DUTY volatile.Register32 // 0xC0 + CH5CARRIER_DUTY volatile.Register32 // 0xC4 + CH6CARRIER_DUTY volatile.Register32 // 0xC8 + CH7CARRIER_DUTY volatile.Register32 // 0xCC + CH0_TX_LIM volatile.Register32 // 0xD0 + CH1_TX_LIM volatile.Register32 // 0xD4 + CH2_TX_LIM volatile.Register32 // 0xD8 + CH3_TX_LIM volatile.Register32 // 0xDC + CH4_TX_LIM volatile.Register32 // 0xE0 + CH5_TX_LIM volatile.Register32 // 0xE4 + CH6_TX_LIM volatile.Register32 // 0xE8 + CH7_TX_LIM volatile.Register32 // 0xEC + APB_CONF volatile.Register32 // 0xF0 + _ [8]byte + DATE volatile.Register32 // 0xFC +} + +// RMT.CH0CONF0 +func (o *RMT_Type) SetCH0CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH0CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH0CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH0CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH0CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH0CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH0CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH0CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH0CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH0CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH0CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH0CONF0_MEM_PD(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH0CONF0_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH0CONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH0CONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0x80000000) >> 31 +} + +// RMT.CH0CONF1 +func (o *RMT_Type) SetCH0CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH0CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH0CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH0CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH0CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH0CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH0CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH0CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH0CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH0CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH0CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH0CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH0CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH0CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH0CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH0CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH0CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH0CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH0CONF1_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH0CONF1_REF_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH0CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH0CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH0CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH0CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH0CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH0CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x80000) >> 19 +} + +// RMT.CH1CONF0 +func (o *RMT_Type) SetCH1CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH1CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH1CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH1CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH1CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH1CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH1CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH1CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH1CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH1CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH1CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH1CONF0_MEM_PD(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH1CONF0_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH1CONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH1CONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0x80000000) >> 31 +} + +// RMT.CH1CONF1 +func (o *RMT_Type) SetCH1CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH1CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH1CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH1CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH1CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH1CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH1CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH1CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH1CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH1CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH1CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH1CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH1CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH1CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH1CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH1CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH1CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH1CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH1CONF1_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH1CONF1_REF_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH1CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH1CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH1CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH1CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH1CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH1CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x80000) >> 19 +} + +// RMT.CH2CONF0 +func (o *RMT_Type) SetCH2CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH2CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH2CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH2CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH2CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH2CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH2CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH2CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH2CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH2CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH2CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH2CONF0_MEM_PD(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH2CONF0_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH2CONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH2CONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0x80000000) >> 31 +} + +// RMT.CH2CONF1 +func (o *RMT_Type) SetCH2CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH2CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH2CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH2CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH2CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH2CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH2CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH2CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH2CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH2CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH2CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH2CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH2CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH2CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH2CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH2CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH2CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH2CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH2CONF1_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH2CONF1_REF_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH2CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH2CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH2CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH2CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH2CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH2CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x80000) >> 19 +} + +// RMT.CH3CONF0 +func (o *RMT_Type) SetCH3CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH3CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH3CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH3CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH3CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH3CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH3CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH3CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH3CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH3CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH3CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH3CONF0_MEM_PD(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH3CONF0_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH3CONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH3CONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0x80000000) >> 31 +} + +// RMT.CH3CONF1 +func (o *RMT_Type) SetCH3CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH3CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH3CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH3CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH3CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH3CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH3CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH3CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH3CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH3CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH3CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH3CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH3CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH3CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH3CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH3CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH3CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH3CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH3CONF1_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH3CONF1_REF_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH3CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH3CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH3CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH3CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH3CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH3CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x80000) >> 19 +} + +// RMT.CH4CONF0 +func (o *RMT_Type) SetCH4CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH4CONF0.Reg, volatile.LoadUint32(&o.CH4CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH4CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH4CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH4CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH4CONF0.Reg, volatile.LoadUint32(&o.CH4CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH4CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH4CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH4CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH4CONF0.Reg, volatile.LoadUint32(&o.CH4CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH4CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH4CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH4CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH4CONF0.Reg, volatile.LoadUint32(&o.CH4CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH4CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH4CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH4CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH4CONF0.Reg, volatile.LoadUint32(&o.CH4CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH4CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH4CONF0.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH4CONF0_MEM_PD(value uint32) { + volatile.StoreUint32(&o.CH4CONF0.Reg, volatile.LoadUint32(&o.CH4CONF0.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH4CONF0_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.CH4CONF0.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH4CONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CH4CONF0.Reg, volatile.LoadUint32(&o.CH4CONF0.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH4CONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CH4CONF0.Reg) & 0x80000000) >> 31 +} + +// RMT.CH4CONF1 +func (o *RMT_Type) SetCH4CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH4CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH4CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH4CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH4CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH4CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH4CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH4CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH4CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH4CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH4CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH4CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH4CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH4CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH4CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH4CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH4CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH4CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH4CONF1_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH4CONF1_REF_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH4CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH4CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH4CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH4CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH4CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH4CONF1.Reg, volatile.LoadUint32(&o.CH4CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH4CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4CONF1.Reg) & 0x80000) >> 19 +} + +// RMT.CH5CONF0 +func (o *RMT_Type) SetCH5CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH5CONF0.Reg, volatile.LoadUint32(&o.CH5CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH5CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH5CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH5CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH5CONF0.Reg, volatile.LoadUint32(&o.CH5CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH5CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH5CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH5CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH5CONF0.Reg, volatile.LoadUint32(&o.CH5CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH5CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH5CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH5CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH5CONF0.Reg, volatile.LoadUint32(&o.CH5CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH5CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH5CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH5CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH5CONF0.Reg, volatile.LoadUint32(&o.CH5CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH5CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH5CONF0.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH5CONF0_MEM_PD(value uint32) { + volatile.StoreUint32(&o.CH5CONF0.Reg, volatile.LoadUint32(&o.CH5CONF0.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH5CONF0_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.CH5CONF0.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH5CONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CH5CONF0.Reg, volatile.LoadUint32(&o.CH5CONF0.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH5CONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CH5CONF0.Reg) & 0x80000000) >> 31 +} + +// RMT.CH5CONF1 +func (o *RMT_Type) SetCH5CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH5CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH5CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH5CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH5CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH5CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH5CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH5CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH5CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH5CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH5CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH5CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH5CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH5CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH5CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH5CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH5CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH5CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH5CONF1_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH5CONF1_REF_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH5CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH5CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH5CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH5CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH5CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH5CONF1.Reg, volatile.LoadUint32(&o.CH5CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH5CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5CONF1.Reg) & 0x80000) >> 19 +} + +// RMT.CH6CONF0 +func (o *RMT_Type) SetCH6CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH6CONF0.Reg, volatile.LoadUint32(&o.CH6CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH6CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH6CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH6CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH6CONF0.Reg, volatile.LoadUint32(&o.CH6CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH6CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH6CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH6CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH6CONF0.Reg, volatile.LoadUint32(&o.CH6CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH6CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH6CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH6CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH6CONF0.Reg, volatile.LoadUint32(&o.CH6CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH6CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH6CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH6CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH6CONF0.Reg, volatile.LoadUint32(&o.CH6CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH6CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH6CONF0.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH6CONF0_MEM_PD(value uint32) { + volatile.StoreUint32(&o.CH6CONF0.Reg, volatile.LoadUint32(&o.CH6CONF0.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH6CONF0_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.CH6CONF0.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH6CONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CH6CONF0.Reg, volatile.LoadUint32(&o.CH6CONF0.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH6CONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CH6CONF0.Reg) & 0x80000000) >> 31 +} + +// RMT.CH6CONF1 +func (o *RMT_Type) SetCH6CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH6CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH6CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH6CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH6CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH6CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH6CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH6CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH6CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH6CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH6CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH6CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH6CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH6CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH6CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH6CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH6CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH6CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH6CONF1_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH6CONF1_REF_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH6CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH6CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH6CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH6CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH6CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH6CONF1.Reg, volatile.LoadUint32(&o.CH6CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH6CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH6CONF1.Reg) & 0x80000) >> 19 +} + +// RMT.CH7CONF0 +func (o *RMT_Type) SetCH7CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH7CONF0.Reg, volatile.LoadUint32(&o.CH7CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH7CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH7CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH7CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH7CONF0.Reg, volatile.LoadUint32(&o.CH7CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH7CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH7CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH7CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH7CONF0.Reg, volatile.LoadUint32(&o.CH7CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH7CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH7CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH7CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH7CONF0.Reg, volatile.LoadUint32(&o.CH7CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH7CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH7CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH7CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH7CONF0.Reg, volatile.LoadUint32(&o.CH7CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH7CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH7CONF0.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH7CONF0_MEM_PD(value uint32) { + volatile.StoreUint32(&o.CH7CONF0.Reg, volatile.LoadUint32(&o.CH7CONF0.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH7CONF0_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.CH7CONF0.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH7CONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CH7CONF0.Reg, volatile.LoadUint32(&o.CH7CONF0.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH7CONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CH7CONF0.Reg) & 0x80000000) >> 31 +} + +// RMT.CH7CONF1 +func (o *RMT_Type) SetCH7CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH7CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH7CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH7CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH7CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH7CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH7CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH7CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH7CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH7CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH7CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH7CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH7CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH7CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH7CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH7CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH7CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH7CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH7CONF1_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH7CONF1_REF_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH7CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH7CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH7CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH7CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH7CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH7CONF1.Reg, volatile.LoadUint32(&o.CH7CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH7CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH7CONF1.Reg) & 0x80000) >> 19 +} + +// RMT.CH0STATUS +func (o *RMT_Type) SetCH0STATUS(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, value) +} +func (o *RMT_Type) GetCH0STATUS() uint32 { + return volatile.LoadUint32(&o.CH0STATUS.Reg) +} +func (o *RMT_Type) SetCH0STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH0STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH0STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x3ff000)|value<<12) +} +func (o *RMT_Type) GetCH0STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x3ff000) >> 12 +} +func (o *RMT_Type) SetCH0STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH0STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH0STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH0STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH0STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH0STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH0STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH0STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH0STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH0STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH0STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH0STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x80000000) >> 31 +} + +// RMT.CH1STATUS +func (o *RMT_Type) SetCH1STATUS(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, value) +} +func (o *RMT_Type) GetCH1STATUS() uint32 { + return volatile.LoadUint32(&o.CH1STATUS.Reg) +} +func (o *RMT_Type) SetCH1STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH1STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH1STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x3ff000)|value<<12) +} +func (o *RMT_Type) GetCH1STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x3ff000) >> 12 +} +func (o *RMT_Type) SetCH1STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH1STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH1STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH1STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH1STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH1STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH1STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH1STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH1STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH1STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH1STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH1STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x80000000) >> 31 +} + +// RMT.CH2STATUS +func (o *RMT_Type) SetCH2STATUS(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, value) +} +func (o *RMT_Type) GetCH2STATUS() uint32 { + return volatile.LoadUint32(&o.CH2STATUS.Reg) +} +func (o *RMT_Type) SetCH2STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH2STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH2STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x3ff000)|value<<12) +} +func (o *RMT_Type) GetCH2STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x3ff000) >> 12 +} +func (o *RMT_Type) SetCH2STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH2STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH2STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH2STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH2STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH2STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH2STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH2STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH2STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH2STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH2STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH2STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x80000000) >> 31 +} + +// RMT.CH3STATUS +func (o *RMT_Type) SetCH3STATUS(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, value) +} +func (o *RMT_Type) GetCH3STATUS() uint32 { + return volatile.LoadUint32(&o.CH3STATUS.Reg) +} +func (o *RMT_Type) SetCH3STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH3STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH3STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x3ff000)|value<<12) +} +func (o *RMT_Type) GetCH3STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x3ff000) >> 12 +} +func (o *RMT_Type) SetCH3STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH3STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH3STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH3STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH3STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH3STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH3STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH3STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH3STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH3STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH3STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH3STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x80000000) >> 31 +} + +// RMT.CH4STATUS +func (o *RMT_Type) SetCH4STATUS(value uint32) { + volatile.StoreUint32(&o.CH4STATUS.Reg, value) +} +func (o *RMT_Type) GetCH4STATUS() uint32 { + return volatile.LoadUint32(&o.CH4STATUS.Reg) +} +func (o *RMT_Type) SetCH4STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH4STATUS.Reg, volatile.LoadUint32(&o.CH4STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH4STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH4STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH4STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH4STATUS.Reg, volatile.LoadUint32(&o.CH4STATUS.Reg)&^(0x3ff000)|value<<12) +} +func (o *RMT_Type) GetCH4STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH4STATUS.Reg) & 0x3ff000) >> 12 +} +func (o *RMT_Type) SetCH4STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH4STATUS.Reg, volatile.LoadUint32(&o.CH4STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH4STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH4STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH4STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH4STATUS.Reg, volatile.LoadUint32(&o.CH4STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH4STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH4STATUS.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH4STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH4STATUS.Reg, volatile.LoadUint32(&o.CH4STATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH4STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH4STATUS.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH4STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH4STATUS.Reg, volatile.LoadUint32(&o.CH4STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH4STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH4STATUS.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH4STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH4STATUS.Reg, volatile.LoadUint32(&o.CH4STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH4STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH4STATUS.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH4STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH4STATUS.Reg, volatile.LoadUint32(&o.CH4STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH4STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH4STATUS.Reg) & 0x80000000) >> 31 +} + +// RMT.CH5STATUS +func (o *RMT_Type) SetCH5STATUS(value uint32) { + volatile.StoreUint32(&o.CH5STATUS.Reg, value) +} +func (o *RMT_Type) GetCH5STATUS() uint32 { + return volatile.LoadUint32(&o.CH5STATUS.Reg) +} +func (o *RMT_Type) SetCH5STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH5STATUS.Reg, volatile.LoadUint32(&o.CH5STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH5STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH5STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH5STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH5STATUS.Reg, volatile.LoadUint32(&o.CH5STATUS.Reg)&^(0x3ff000)|value<<12) +} +func (o *RMT_Type) GetCH5STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH5STATUS.Reg) & 0x3ff000) >> 12 +} +func (o *RMT_Type) SetCH5STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH5STATUS.Reg, volatile.LoadUint32(&o.CH5STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH5STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH5STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH5STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH5STATUS.Reg, volatile.LoadUint32(&o.CH5STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH5STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH5STATUS.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH5STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH5STATUS.Reg, volatile.LoadUint32(&o.CH5STATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH5STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH5STATUS.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH5STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH5STATUS.Reg, volatile.LoadUint32(&o.CH5STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH5STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH5STATUS.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH5STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH5STATUS.Reg, volatile.LoadUint32(&o.CH5STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH5STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH5STATUS.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH5STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH5STATUS.Reg, volatile.LoadUint32(&o.CH5STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH5STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH5STATUS.Reg) & 0x80000000) >> 31 +} + +// RMT.CH6STATUS +func (o *RMT_Type) SetCH6STATUS(value uint32) { + volatile.StoreUint32(&o.CH6STATUS.Reg, value) +} +func (o *RMT_Type) GetCH6STATUS() uint32 { + return volatile.LoadUint32(&o.CH6STATUS.Reg) +} +func (o *RMT_Type) SetCH6STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH6STATUS.Reg, volatile.LoadUint32(&o.CH6STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH6STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH6STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH6STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH6STATUS.Reg, volatile.LoadUint32(&o.CH6STATUS.Reg)&^(0x3ff000)|value<<12) +} +func (o *RMT_Type) GetCH6STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH6STATUS.Reg) & 0x3ff000) >> 12 +} +func (o *RMT_Type) SetCH6STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH6STATUS.Reg, volatile.LoadUint32(&o.CH6STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH6STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH6STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH6STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH6STATUS.Reg, volatile.LoadUint32(&o.CH6STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH6STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH6STATUS.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH6STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH6STATUS.Reg, volatile.LoadUint32(&o.CH6STATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH6STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH6STATUS.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH6STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH6STATUS.Reg, volatile.LoadUint32(&o.CH6STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH6STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH6STATUS.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH6STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH6STATUS.Reg, volatile.LoadUint32(&o.CH6STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH6STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH6STATUS.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH6STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH6STATUS.Reg, volatile.LoadUint32(&o.CH6STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH6STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH6STATUS.Reg) & 0x80000000) >> 31 +} + +// RMT.CH7STATUS +func (o *RMT_Type) SetCH7STATUS(value uint32) { + volatile.StoreUint32(&o.CH7STATUS.Reg, value) +} +func (o *RMT_Type) GetCH7STATUS() uint32 { + return volatile.LoadUint32(&o.CH7STATUS.Reg) +} +func (o *RMT_Type) SetCH7STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH7STATUS.Reg, volatile.LoadUint32(&o.CH7STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH7STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH7STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH7STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH7STATUS.Reg, volatile.LoadUint32(&o.CH7STATUS.Reg)&^(0x3ff000)|value<<12) +} +func (o *RMT_Type) GetCH7STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH7STATUS.Reg) & 0x3ff000) >> 12 +} +func (o *RMT_Type) SetCH7STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH7STATUS.Reg, volatile.LoadUint32(&o.CH7STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH7STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH7STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH7STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH7STATUS.Reg, volatile.LoadUint32(&o.CH7STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH7STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH7STATUS.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH7STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH7STATUS.Reg, volatile.LoadUint32(&o.CH7STATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH7STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH7STATUS.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH7STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH7STATUS.Reg, volatile.LoadUint32(&o.CH7STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH7STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH7STATUS.Reg) & 0x20000000) >> 29 +} +func (o *RMT_Type) SetCH7STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH7STATUS.Reg, volatile.LoadUint32(&o.CH7STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *RMT_Type) GetCH7STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH7STATUS.Reg) & 0x40000000) >> 30 +} +func (o *RMT_Type) SetCH7STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH7STATUS.Reg, volatile.LoadUint32(&o.CH7STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetCH7STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH7STATUS.Reg) & 0x80000000) >> 31 +} + +// RMT.CH0ADDR +func (o *RMT_Type) SetCH0ADDR(value uint32) { + volatile.StoreUint32(&o.CH0ADDR.Reg, value) +} +func (o *RMT_Type) GetCH0ADDR() uint32 { + return volatile.LoadUint32(&o.CH0ADDR.Reg) +} + +// RMT.CH1ADDR +func (o *RMT_Type) SetCH1ADDR(value uint32) { + volatile.StoreUint32(&o.CH1ADDR.Reg, value) +} +func (o *RMT_Type) GetCH1ADDR() uint32 { + return volatile.LoadUint32(&o.CH1ADDR.Reg) +} + +// RMT.CH2ADDR +func (o *RMT_Type) SetCH2ADDR(value uint32) { + volatile.StoreUint32(&o.CH2ADDR.Reg, value) +} +func (o *RMT_Type) GetCH2ADDR() uint32 { + return volatile.LoadUint32(&o.CH2ADDR.Reg) +} + +// RMT.CH3ADDR +func (o *RMT_Type) SetCH3ADDR(value uint32) { + volatile.StoreUint32(&o.CH3ADDR.Reg, value) +} +func (o *RMT_Type) GetCH3ADDR() uint32 { + return volatile.LoadUint32(&o.CH3ADDR.Reg) +} + +// RMT.CH4ADDR +func (o *RMT_Type) SetCH4ADDR(value uint32) { + volatile.StoreUint32(&o.CH4ADDR.Reg, value) +} +func (o *RMT_Type) GetCH4ADDR() uint32 { + return volatile.LoadUint32(&o.CH4ADDR.Reg) +} + +// RMT.CH5ADDR +func (o *RMT_Type) SetCH5ADDR(value uint32) { + volatile.StoreUint32(&o.CH5ADDR.Reg, value) +} +func (o *RMT_Type) GetCH5ADDR() uint32 { + return volatile.LoadUint32(&o.CH5ADDR.Reg) +} + +// RMT.CH6ADDR +func (o *RMT_Type) SetCH6ADDR(value uint32) { + volatile.StoreUint32(&o.CH6ADDR.Reg, value) +} +func (o *RMT_Type) GetCH6ADDR() uint32 { + return volatile.LoadUint32(&o.CH6ADDR.Reg) +} + +// RMT.CH7ADDR +func (o *RMT_Type) SetCH7ADDR(value uint32) { + volatile.StoreUint32(&o.CH7ADDR.Reg, value) +} +func (o *RMT_Type) GetCH7ADDR() uint32 { + return volatile.LoadUint32(&o.CH7ADDR.Reg) +} + +// RMT.INT_RAW +func (o *RMT_Type) SetINT_RAW_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_RAW_CH_s_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_RAW_CH_s_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} + +// RMT.INT_ST +func (o *RMT_Type) SetINT_ST_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_ST_CH_s_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ST_CH_s_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} + +// RMT.INT_ENA +func (o *RMT_Type) SetINT_ENA_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_ENA_CH_s_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ENA_CH_s_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} + +// RMT.INT_CLR +func (o *RMT_Type) SetINT_CLR_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_CLR_CH_s_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_CLR_CH_s_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} + +// RMT.CH0CARRIER_DUTY +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1CARRIER_DUTY +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH2CARRIER_DUTY +func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH3CARRIER_DUTY +func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH4CARRIER_DUTY +func (o *RMT_Type) SetCH4CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH4CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH4CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH4CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH4CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH4CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH4CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH4CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH4CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH4CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH5CARRIER_DUTY +func (o *RMT_Type) SetCH5CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH5CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH5CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH5CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH5CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH5CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH5CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH5CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH5CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH5CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH6CARRIER_DUTY +func (o *RMT_Type) SetCH6CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH6CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH6CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH6CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH6CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH6CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH6CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH6CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH6CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH6CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH7CARRIER_DUTY +func (o *RMT_Type) SetCH7CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH7CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH7CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH7CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH7CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH7CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH7CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH7CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH7CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH7CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_TX_LIM +func (o *RMT_Type) SetCH0_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x1ff +} + +// RMT.CH1_TX_LIM +func (o *RMT_Type) SetCH1_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x1ff +} + +// RMT.CH2_TX_LIM +func (o *RMT_Type) SetCH2_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x1ff +} + +// RMT.CH3_TX_LIM +func (o *RMT_Type) SetCH3_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x1ff +} + +// RMT.CH4_TX_LIM +func (o *RMT_Type) SetCH4_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH4_TX_LIM.Reg, volatile.LoadUint32(&o.CH4_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH4_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH4_TX_LIM.Reg) & 0x1ff +} + +// RMT.CH5_TX_LIM +func (o *RMT_Type) SetCH5_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH5_TX_LIM.Reg, volatile.LoadUint32(&o.CH5_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH5_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH5_TX_LIM.Reg) & 0x1ff +} + +// RMT.CH6_TX_LIM +func (o *RMT_Type) SetCH6_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH6_TX_LIM.Reg, volatile.LoadUint32(&o.CH6_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH6_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH6_TX_LIM.Reg) & 0x1ff +} + +// RMT.CH7_TX_LIM +func (o *RMT_Type) SetCH7_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH7_TX_LIM.Reg, volatile.LoadUint32(&o.CH7_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH7_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH7_TX_LIM.Reg) & 0x1ff +} + +// RMT.APB_CONF +func (o *RMT_Type) SetAPB_CONF_APB_FIFO_MASK(value uint32) { + volatile.StoreUint32(&o.APB_CONF.Reg, volatile.LoadUint32(&o.APB_CONF.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetAPB_CONF_APB_FIFO_MASK() uint32 { + return volatile.LoadUint32(&o.APB_CONF.Reg) & 0x1 +} +func (o *RMT_Type) SetAPB_CONF_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.APB_CONF.Reg, volatile.LoadUint32(&o.APB_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetAPB_CONF_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.APB_CONF.Reg) & 0x2) >> 1 +} + +// RMT.DATE +func (o *RMT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *RMT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Hardware Random Number Generator +type RNG_Type struct { + _ [324]byte + DATA volatile.Register32 // 0x144 +} + +// RSA (Rivest Shamir Adleman) Accelerator +type RSA_Type struct { + M_MEM [128]volatile.Register8 // 0x0 + _ [384]byte + Z_MEM [128]volatile.Register8 // 0x200 + _ [384]byte + Y_MEM [128]volatile.Register8 // 0x400 + _ [384]byte + X_MEM [128]volatile.Register8 // 0x600 + _ [384]byte + M_PRIME volatile.Register32 // 0x800 + MODEXP_MODE volatile.Register32 // 0x804 + MODEXP_START volatile.Register32 // 0x808 + MULT_MODE volatile.Register32 // 0x80C + MULT_START volatile.Register32 // 0x810 + INTERRUPT volatile.Register32 // 0x814 + CLEAN volatile.Register32 // 0x818 +} + +// RSA.M_PRIME +func (o *RSA_Type) SetM_PRIME(value uint32) { + volatile.StoreUint32(&o.M_PRIME.Reg, volatile.LoadUint32(&o.M_PRIME.Reg)&^(0xff)|value) +} +func (o *RSA_Type) GetM_PRIME() uint32 { + return volatile.LoadUint32(&o.M_PRIME.Reg) & 0xff +} + +// RSA.MODEXP_MODE +func (o *RSA_Type) SetMODEXP_MODE(value uint32) { + volatile.StoreUint32(&o.MODEXP_MODE.Reg, volatile.LoadUint32(&o.MODEXP_MODE.Reg)&^(0x7)|value) +} +func (o *RSA_Type) GetMODEXP_MODE() uint32 { + return volatile.LoadUint32(&o.MODEXP_MODE.Reg) & 0x7 +} + +// RSA.MODEXP_START +func (o *RSA_Type) SetMODEXP_START(value uint32) { + volatile.StoreUint32(&o.MODEXP_START.Reg, volatile.LoadUint32(&o.MODEXP_START.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetMODEXP_START() uint32 { + return volatile.LoadUint32(&o.MODEXP_START.Reg) & 0x1 +} + +// RSA.MULT_MODE +func (o *RSA_Type) SetMULT_MODE(value uint32) { + volatile.StoreUint32(&o.MULT_MODE.Reg, volatile.LoadUint32(&o.MULT_MODE.Reg)&^(0xf)|value) +} +func (o *RSA_Type) GetMULT_MODE() uint32 { + return volatile.LoadUint32(&o.MULT_MODE.Reg) & 0xf +} + +// RSA.MULT_START +func (o *RSA_Type) SetMULT_START(value uint32) { + volatile.StoreUint32(&o.MULT_START.Reg, volatile.LoadUint32(&o.MULT_START.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetMULT_START() uint32 { + return volatile.LoadUint32(&o.MULT_START.Reg) & 0x1 +} + +// RSA.INTERRUPT +func (o *RSA_Type) SetINTERRUPT(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINTERRUPT() uint32 { + return volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x1 +} + +// RSA.CLEAN +func (o *RSA_Type) SetCLEAN(value uint32) { + volatile.StoreUint32(&o.CLEAN.Reg, volatile.LoadUint32(&o.CLEAN.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCLEAN() uint32 { + return volatile.LoadUint32(&o.CLEAN.Reg) & 0x1 +} + +// Real-Time Clock Control +type RTC_CNTL_Type struct { + OPTIONS0 volatile.Register32 // 0x0 + SLP_TIMER0 volatile.Register32 // 0x4 + SLP_TIMER1 volatile.Register32 // 0x8 + TIME_UPDATE volatile.Register32 // 0xC + TIME0 volatile.Register32 // 0x10 + TIME1 volatile.Register32 // 0x14 + STATE0 volatile.Register32 // 0x18 + TIMER1 volatile.Register32 // 0x1C + TIMER2 volatile.Register32 // 0x20 + TIMER3 volatile.Register32 // 0x24 + TIMER4 volatile.Register32 // 0x28 + TIMER5 volatile.Register32 // 0x2C + ANA_CONF volatile.Register32 // 0x30 + RESET_STATE volatile.Register32 // 0x34 + WAKEUP_STATE volatile.Register32 // 0x38 + INT_ENA volatile.Register32 // 0x3C + INT_RAW volatile.Register32 // 0x40 + INT_ST volatile.Register32 // 0x44 + INT_CLR volatile.Register32 // 0x48 + STORE0 volatile.Register32 // 0x4C + STORE1 volatile.Register32 // 0x50 + STORE2 volatile.Register32 // 0x54 + STORE3 volatile.Register32 // 0x58 + EXT_XTL_CONF volatile.Register32 // 0x5C + EXT_WAKEUP_CONF volatile.Register32 // 0x60 + SLP_REJECT_CONF volatile.Register32 // 0x64 + CPU_PERIOD_CONF volatile.Register32 // 0x68 + SDIO_ACT_CONF volatile.Register32 // 0x6C + CLK_CONF volatile.Register32 // 0x70 + SDIO_CONF volatile.Register32 // 0x74 + BIAS_CONF volatile.Register32 // 0x78 + REG volatile.Register32 // 0x7C + PWC volatile.Register32 // 0x80 + DIG_PWC volatile.Register32 // 0x84 + DIG_ISO volatile.Register32 // 0x88 + WDTCONFIG0 volatile.Register32 // 0x8C + WDTCONFIG1 volatile.Register32 // 0x90 + WDTCONFIG2 volatile.Register32 // 0x94 + WDTCONFIG3 volatile.Register32 // 0x98 + WDTCONFIG4 volatile.Register32 // 0x9C + WDTFEED volatile.Register32 // 0xA0 + WDTWPROTECT volatile.Register32 // 0xA4 + TEST_MUX volatile.Register32 // 0xA8 + SW_CPU_STALL volatile.Register32 // 0xAC + STORE4 volatile.Register32 // 0xB0 + STORE5 volatile.Register32 // 0xB4 + STORE6 volatile.Register32 // 0xB8 + STORE7 volatile.Register32 // 0xBC + LOW_POWER_ST volatile.Register32 // 0xC0 + DIAG1 volatile.Register32 // 0xC4 + HOLD_FORCE volatile.Register32 // 0xC8 + EXT_WAKEUP1 volatile.Register32 // 0xCC + EXT_WAKEUP1_STATUS volatile.Register32 // 0xD0 + BROWN_OUT volatile.Register32 // 0xD4 + _ [100]byte + DATE volatile.Register32 // 0x13C +} + +// RTC_CNTL.OPTIONS0 +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_STALL_APPCPU_C0(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_STALL_APPCPU_C0() uint32 { + return volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_STALL_PROCPU_C0(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0xc)|value<<2) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_STALL_PROCPU_C0() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0xc) >> 2 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_APPCPU_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_APPCPU_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_PROCPU_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_PROCPU_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BIAS_SLEEP_FOLW_8M(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BIAS_SLEEP_FOLW_8M() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BIAS_FORCE_SLEEP(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BIAS_FORCE_SLEEP() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BIAS_FORCE_NOSLEEP(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BIAS_FORCE_NOSLEEP() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BIAS_I2C_FOLW_8M(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BIAS_I2C_FOLW_8M() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BIAS_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BIAS_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BIAS_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BIAS_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BIAS_CORE_FOLW_8M(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BIAS_CORE_FOLW_8M() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BIAS_CORE_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BIAS_CORE_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BIAS_CORE_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BIAS_CORE_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_PLL_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_PLL_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_PLL_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_PLL_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_NORST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_NORST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_SYS_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_TIMER0 +func (o *RTC_CNTL_Type) SetSLP_TIMER0(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER0() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER0.Reg) +} + +// RTC_CNTL.SLP_TIMER1 +func (o *RTC_CNTL_Type) SetSLP_TIMER1_SLP_VAL_HI(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_SLP_VAL_HI() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0xffff +} +func (o *RTC_CNTL_Type) SetSLP_TIMER1_MAIN_TIMER_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_MAIN_TIMER_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0x10000) >> 16 +} + +// RTC_CNTL.TIME_UPDATE +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIME_VALID(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIME_VALID() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIME0 +func (o *RTC_CNTL_Type) SetTIME0(value uint32) { + volatile.StoreUint32(&o.TIME0.Reg, value) +} +func (o *RTC_CNTL_Type) GetTIME0() uint32 { + return volatile.LoadUint32(&o.TIME0.Reg) +} + +// RTC_CNTL.TIME1 +func (o *RTC_CNTL_Type) SetTIME1_TIME_HI(value uint32) { + volatile.StoreUint32(&o.TIME1.Reg, volatile.LoadUint32(&o.TIME1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTIME1_TIME_HI() uint32 { + return volatile.LoadUint32(&o.TIME1.Reg) & 0xffff +} + +// RTC_CNTL.STATE0 +func (o *RTC_CNTL_Type) SetSTATE0_TOUCH_WAKEUP_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetSTATE0_TOUCH_WAKEUP_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetSTATE0_ULP_CP_WAKEUP_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetSTATE0_ULP_CP_WAKEUP_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetSTATE0_APB2RTC_BRIDGE_SEL(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSTATE0_APB2RTC_BRIDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSTATE0_TOUCH_SLP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetSTATE0_TOUCH_SLP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetSTATE0_ULP_CP_SLP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetSTATE0_ULP_CP_SLP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetSTATE0_SDIO_ACTIVE_IND(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSTATE0_SDIO_ACTIVE_IND() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_WAKEUP(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_REJECT(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_REJECT() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLEEP_EN(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLEEP_EN() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIMER1 +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3e)|value<<1) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3e) >> 1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CK8M_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3fc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetTIMER1_CK8M_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3fc0) >> 6 +} +func (o *RTC_CNTL_Type) SetTIMER1_XTL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xffc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetTIMER1_XTL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xffc000) >> 14 +} +func (o *RTC_CNTL_Type) SetTIMER1_PLL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER1_PLL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER2 +func (o *RTC_CNTL_Type) SetTIMER2_ULPCP_TOUCH_START_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER2.Reg, volatile.LoadUint32(&o.TIMER2.Reg)&^(0xff8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetTIMER2_ULPCP_TOUCH_START_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER2.Reg) & 0xff8000) >> 15 +} +func (o *RTC_CNTL_Type) SetTIMER2_MIN_TIME_CK8M_OFF(value uint32) { + volatile.StoreUint32(&o.TIMER2.Reg, volatile.LoadUint32(&o.TIMER2.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER2_MIN_TIME_CK8M_OFF() uint32 { + return (volatile.LoadUint32(&o.TIMER2.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER3 +func (o *RTC_CNTL_Type) SetTIMER3_WIFI_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0x1ff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER3_WIFI_WAIT_TIMER() uint32 { + return volatile.LoadUint32(&o.TIMER3.Reg) & 0x1ff +} +func (o *RTC_CNTL_Type) SetTIMER3_WIFI_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0xfe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTIMER3_WIFI_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0xfe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTIMER3_ROM_RAM_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER3_ROM_RAM_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER3_ROM_RAM_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER3_ROM_RAM_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER4 +func (o *RTC_CNTL_Type) SetTIMER4_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0x1ff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER4_WAIT_TIMER() uint32 { + return volatile.LoadUint32(&o.TIMER4.Reg) & 0x1ff +} +func (o *RTC_CNTL_Type) SetTIMER4_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0xfe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTIMER4_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0xfe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER5 +func (o *RTC_CNTL_Type) SetTIMER5_ULP_CP_SUBTIMER_PREDIV(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER5_ULP_CP_SUBTIMER_PREDIV() uint32 { + return volatile.LoadUint32(&o.TIMER5.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetTIMER5_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetTIMER5_MIN_SLP_VAL() uint32 { + return (volatile.LoadUint32(&o.TIMER5.Reg) & 0xff00) >> 8 +} +func (o *RTC_CNTL_Type) SetTIMER5_RTCMEM_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER5_RTCMEM_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER5.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER5_RTCMEM_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER5_RTCMEM_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER5.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.ANA_CONF +func (o *RTC_CNTL_Type) SetANA_CONF_PLLA_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLLA_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLLA_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLLA_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetANA_CONF_BBPLL_CAL_SLP_START(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetANA_CONF_BBPLL_CAL_SLP_START() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PVTMON_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PVTMON_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetANA_CONF_TXRF_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetANA_CONF_TXRF_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetANA_CONF_RFRX_PBUS_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetANA_CONF_RFRX_PBUS_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetANA_CONF_CKGEN_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetANA_CONF_CKGEN_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLL_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLL_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.RESET_STATE +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_CAUSE_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x3f)|value) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_CAUSE_PROCPU() uint32 { + return volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x3f +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_CAUSE_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0xfc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_CAUSE_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0xfc0) >> 6 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_APPCPU_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_APPCPU_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_PROCPU_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_PROCPU_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x2000) >> 13 +} + +// RTC_CNTL.WAKEUP_STATE +func (o *RTC_CNTL_Type) SetWAKEUP_STATE_WAKEUP_CAUSE(value uint32) { + volatile.StoreUint32(&o.WAKEUP_STATE.Reg, volatile.LoadUint32(&o.WAKEUP_STATE.Reg)&^(0x7ff)|value) +} +func (o *RTC_CNTL_Type) GetWAKEUP_STATE_WAKEUP_CAUSE() uint32 { + return volatile.LoadUint32(&o.WAKEUP_STATE.Reg) & 0x7ff +} +func (o *RTC_CNTL_Type) SetWAKEUP_STATE_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.WAKEUP_STATE.Reg, volatile.LoadUint32(&o.WAKEUP_STATE.Reg)&^(0x3ff800)|value<<11) +} +func (o *RTC_CNTL_Type) GetWAKEUP_STATE_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_STATE.Reg) & 0x3ff800) >> 11 +} +func (o *RTC_CNTL_Type) SetWAKEUP_STATE_GPIO_WAKEUP_FILTER(value uint32) { + volatile.StoreUint32(&o.WAKEUP_STATE.Reg, volatile.LoadUint32(&o.WAKEUP_STATE.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetWAKEUP_STATE_GPIO_WAKEUP_FILTER() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_STATE.Reg) & 0x400000) >> 22 +} + +// RTC_CNTL.INT_ENA +func (o *RTC_CNTL_Type) SetINT_ENA_SLP_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_SLP_WAKEUP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_SLP_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_SLP_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_SDIO_IDLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_ENA_SDIO_IDLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_ENA_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_TIME_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_ENA_TIME_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_ENA_ULP_CP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_ENA_ULP_CP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_ENA_TOUCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_ENA_TOUCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_ENA_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_ENA_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_ENA_MAIN_TIMER_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_ENA_MAIN_TIMER_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// RTC_CNTL.INT_RAW +func (o *RTC_CNTL_Type) SetINT_RAW_SLP_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_RAW_SLP_WAKEUP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_SLP_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_RAW_SLP_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_SDIO_IDLE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_RAW_SDIO_IDLE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_RAW_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_RAW_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_RAW_TIME_VALID_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_RAW_TIME_VALID_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_RAW_ULP_CP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_RAW_ULP_CP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_RAW_TOUCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_RAW_TOUCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_RAW_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_RAW_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_RAW_MAIN_TIMER_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_RAW_MAIN_TIMER_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// RTC_CNTL.INT_ST +func (o *RTC_CNTL_Type) SetINT_ST_SLP_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ST_SLP_WAKEUP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ST_SLP_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ST_SLP_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ST_SDIO_IDLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_ST_SDIO_IDLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_ST_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ST_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ST_TIME_VALID_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_ST_TIME_VALID_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_ST_SAR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_ST_SAR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_ST_TOUCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_ST_TOUCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_ST_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_ST_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_ST_MAIN_TIMER_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_ST_MAIN_TIMER_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// RTC_CNTL.INT_CLR +func (o *RTC_CNTL_Type) SetINT_CLR_SLP_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_CLR_SLP_WAKEUP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_SLP_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_CLR_SLP_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_SDIO_IDLE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_CLR_SDIO_IDLE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_CLR_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_CLR_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_CLR_TIME_VALID_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_CLR_TIME_VALID_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_CLR_SAR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_CLR_SAR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_CLR_TOUCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_CLR_TOUCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_CLR_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_CLR_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_CLR_MAIN_TIMER_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_CLR_MAIN_TIMER_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// RTC_CNTL.STORE0 +func (o *RTC_CNTL_Type) SetSTORE0(value uint32) { + volatile.StoreUint32(&o.STORE0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE0() uint32 { + return volatile.LoadUint32(&o.STORE0.Reg) +} + +// RTC_CNTL.STORE1 +func (o *RTC_CNTL_Type) SetSTORE1(value uint32) { + volatile.StoreUint32(&o.STORE1.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE1() uint32 { + return volatile.LoadUint32(&o.STORE1.Reg) +} + +// RTC_CNTL.STORE2 +func (o *RTC_CNTL_Type) SetSTORE2(value uint32) { + volatile.StoreUint32(&o.STORE2.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE2() uint32 { + return volatile.LoadUint32(&o.STORE2.Reg) +} + +// RTC_CNTL.STORE3 +func (o *RTC_CNTL_Type) SetSTORE3(value uint32) { + volatile.StoreUint32(&o.STORE3.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE3() uint32 { + return volatile.LoadUint32(&o.STORE3.Reg) +} + +// RTC_CNTL.EXT_XTL_CONF +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_LV(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_EN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_EN() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.EXT_WAKEUP_CONF +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_EXT_WAKEUP0_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_EXT_WAKEUP0_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_EXT_WAKEUP1_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_EXT_WAKEUP1_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_REJECT_CONF +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_GPIO_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_GPIO_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_SDIO_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_SDIO_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_REJECT_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_REJECT_CAUSE() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.CPU_PERIOD_CONF +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUSEL_CONF(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUSEL_CONF() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUPERIOD_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.SDIO_ACT_CONF +func (o *RTC_CNTL_Type) SetSDIO_ACT_CONF_SDIO_ACT_DNUM(value uint32) { + volatile.StoreUint32(&o.SDIO_ACT_CONF.Reg, volatile.LoadUint32(&o.SDIO_ACT_CONF.Reg)&^(0xffc00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSDIO_ACT_CONF_SDIO_ACT_DNUM() uint32 { + return (volatile.LoadUint32(&o.SDIO_ACT_CONF.Reg) & 0xffc00000) >> 22 +} + +// RTC_CNTL.CLK_CONF +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x30)|value<<4) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x30) >> 4 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_XTAL32K_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_XTAL32K_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_D256_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_D256_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DFREQ_FORCE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DFREQ_FORCE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x7000)|value<<12) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x7000) >> 12 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DFREQ(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1fe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DFREQ() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1fe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_SOC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_SOC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x18000000) >> 27 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_FAST_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_FAST_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ANA_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ANA_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.SDIO_CONF +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_PD_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_FORCE(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_FORCE() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_TIEH(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_TIEH() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_REG1P8_READY(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_REG1P8_READY() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFL_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x6000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFL_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x6000000) >> 25 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFM_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFM_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x18000000) >> 27 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFH_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFH_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x60000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_XPD_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_XPD_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.BIAS_CONF +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3000000) >> 24 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_ENB_SCK_XTAL(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_ENB_SCK_XTAL() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_INC_HEARTBEAT_REFRESH(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_INC_HEARTBEAT_REFRESH() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DEC_HEARTBEAT_PERIOD(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DEC_HEARTBEAT_PERIOD() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_INC_HEARTBEAT_PERIOD(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_INC_HEARTBEAT_PERIOD() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DEC_HEARTBEAT_WIDTH(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DEC_HEARTBEAT_WIDTH() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_RST_BIAS_I2C(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_RST_BIAS_I2C() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.REG +func (o *RTC_CNTL_Type) SetREG_SCK_DCAP_FORCE(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetREG_SCK_DCAP_FORCE() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetREG_DIG_DBIAS_SLP(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x700)|value<<8) +} +func (o *RTC_CNTL_Type) GetREG_DIG_DBIAS_SLP() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x700) >> 8 +} +func (o *RTC_CNTL_Type) SetREG_DIG_DBIAS_WAK(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x3800)|value<<11) +} +func (o *RTC_CNTL_Type) GetREG_DIG_DBIAS_WAK() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x3800) >> 11 +} +func (o *RTC_CNTL_Type) SetREG_SCK_DCAP(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x3fc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetREG_SCK_DCAP() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x3fc000) >> 14 +} +func (o *RTC_CNTL_Type) SetREG_DBIAS_SLP(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x1c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetREG_DBIAS_SLP() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x1c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetREG_DBIAS_WAK(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetREG_DBIAS_WAK() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetREG_DBOOST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetREG_DBOOST_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetREG_DBOOST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetREG_DBOOST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetREG_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetREG_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetREG_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetREG_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.PWC +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_NOISO() uint32 { + return volatile.LoadUint32(&o.PWC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FOLW_CPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FOLW_CPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_LPD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_LPD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_LPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_LPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FOLW_CPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FOLW_CPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_LPD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_LPD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_LPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_LPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetPWC_PD_EN(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetPWC_PD_EN() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.DIG_PWC +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_ROM0_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_ROM0_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_ROM0_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_ROM0_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM0_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM0_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM0_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM0_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM1_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM1_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM1_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM1_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM2_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM2_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM2_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM2_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM3_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM3_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM3_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM3_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM4_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM4_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM4_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM4_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_ROM0_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_ROM0_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM0_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM0_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM1_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM1_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM2_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM2_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM3_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM3_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM4_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM4_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.DIG_ISO +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_OFF(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_OFF() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_CLR_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_CLR_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_UNHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_UNHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_HOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_ROM0_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_ROM0_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_ROM0_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_ROM0_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM0_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM0_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM0_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM0_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM1_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM1_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM1_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM1_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM2_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM2_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM2_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM2_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM3_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM3_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM3_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM3_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM4_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM4_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM4_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM4_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_WIFI_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_WIFI_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_WIFI_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_WIFI_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG0 +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PAUSE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PAUSE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x3800)|value<<11) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x3800) >> 11 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c000)|value<<14) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c000) >> 14 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_LEVEL_INT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_LEVEL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_EDGE_INT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_EDGE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x380000)|value<<19) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x380000) >> 19 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000000) >> 28 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG1 +func (o *RTC_CNTL_Type) SetWDTCONFIG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG1() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) +} + +// RTC_CNTL.WDTCONFIG2 +func (o *RTC_CNTL_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// RTC_CNTL.WDTCONFIG3 +func (o *RTC_CNTL_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// RTC_CNTL.WDTCONFIG4 +func (o *RTC_CNTL_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// RTC_CNTL.WDTFEED +func (o *RTC_CNTL_Type) SetWDTFEED_WDT_FEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, volatile.LoadUint32(&o.WDTFEED.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTFEED_WDT_FEED() uint32 { + return (volatile.LoadUint32(&o.WDTFEED.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTWPROTECT +func (o *RTC_CNTL_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// RTC_CNTL.TEST_MUX +func (o *RTC_CNTL_Type) SetTEST_MUX_ENT_RTC(value uint32) { + volatile.StoreUint32(&o.TEST_MUX.Reg, volatile.LoadUint32(&o.TEST_MUX.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetTEST_MUX_ENT_RTC() uint32 { + return (volatile.LoadUint32(&o.TEST_MUX.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetTEST_MUX_DTEST_RTC(value uint32) { + volatile.StoreUint32(&o.TEST_MUX.Reg, volatile.LoadUint32(&o.TEST_MUX.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetTEST_MUX_DTEST_RTC() uint32 { + return (volatile.LoadUint32(&o.TEST_MUX.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.SW_CPU_STALL +func (o *RTC_CNTL_Type) SetSW_CPU_STALL_SW_STALL_APPCPU_C1(value uint32) { + volatile.StoreUint32(&o.SW_CPU_STALL.Reg, volatile.LoadUint32(&o.SW_CPU_STALL.Reg)&^(0x3f00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetSW_CPU_STALL_SW_STALL_APPCPU_C1() uint32 { + return (volatile.LoadUint32(&o.SW_CPU_STALL.Reg) & 0x3f00000) >> 20 +} +func (o *RTC_CNTL_Type) SetSW_CPU_STALL_SW_STALL_PROCPU_C1(value uint32) { + volatile.StoreUint32(&o.SW_CPU_STALL.Reg, volatile.LoadUint32(&o.SW_CPU_STALL.Reg)&^(0xfc000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetSW_CPU_STALL_SW_STALL_PROCPU_C1() uint32 { + return (volatile.LoadUint32(&o.SW_CPU_STALL.Reg) & 0xfc000000) >> 26 +} + +// RTC_CNTL.STORE4 +func (o *RTC_CNTL_Type) SetSTORE4(value uint32) { + volatile.StoreUint32(&o.STORE4.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE4() uint32 { + return volatile.LoadUint32(&o.STORE4.Reg) +} + +// RTC_CNTL.STORE5 +func (o *RTC_CNTL_Type) SetSTORE5(value uint32) { + volatile.StoreUint32(&o.STORE5.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE5() uint32 { + return volatile.LoadUint32(&o.STORE5.Reg) +} + +// RTC_CNTL.STORE6 +func (o *RTC_CNTL_Type) SetSTORE6(value uint32) { + volatile.StoreUint32(&o.STORE6.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE6() uint32 { + return volatile.LoadUint32(&o.STORE6.Reg) +} + +// RTC_CNTL.STORE7 +func (o *RTC_CNTL_Type) SetSTORE7(value uint32) { + volatile.StoreUint32(&o.STORE7.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE7() uint32 { + return volatile.LoadUint32(&o.STORE7.Reg) +} + +// RTC_CNTL.LOW_POWER_ST +func (o *RTC_CNTL_Type) SetLOW_POWER_ST(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, value) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST() uint32 { + return volatile.LoadUint32(&o.LOW_POWER_ST.Reg) +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_RDY_FOR_WAKEUP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_RDY_FOR_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x80000) >> 19 +} + +// RTC_CNTL.DIAG1 +func (o *RTC_CNTL_Type) SetDIAG1(value uint32) { + volatile.StoreUint32(&o.DIAG1.Reg, value) +} +func (o *RTC_CNTL_Type) GetDIAG1() uint32 { + return volatile.LoadUint32(&o.DIAG1.Reg) +} + +// RTC_CNTL.HOLD_FORCE +func (o *RTC_CNTL_Type) SetHOLD_FORCE_ADC1_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_ADC1_HOLD_FORCE() uint32 { + return volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_ADC2_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_ADC2_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_PDAC1_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_PDAC1_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_PDAC2_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_PDAC2_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_SENSE1_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_SENSE1_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_SENSE2_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_SENSE2_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_SENSE3_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_SENSE3_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_SENSE4_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_SENSE4_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_TOUCH_PAD0_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_TOUCH_PAD0_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_TOUCH_PAD1_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_TOUCH_PAD1_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_TOUCH_PAD2_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_TOUCH_PAD2_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_TOUCH_PAD3_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_TOUCH_PAD3_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_TOUCH_PAD4_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_TOUCH_PAD4_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_TOUCH_PAD5_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_TOUCH_PAD5_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_TOUCH_PAD6_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_TOUCH_PAD6_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_TOUCH_PAD7_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_TOUCH_PAD7_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_X32P_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_X32P_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetHOLD_FORCE_X32N_HOLD_FORCE(value uint32) { + volatile.StoreUint32(&o.HOLD_FORCE.Reg, volatile.LoadUint32(&o.HOLD_FORCE.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetHOLD_FORCE_X32N_HOLD_FORCE() uint32 { + return (volatile.LoadUint32(&o.HOLD_FORCE.Reg) & 0x20000) >> 17 +} + +// RTC_CNTL.EXT_WAKEUP1 +func (o *RTC_CNTL_Type) SetEXT_WAKEUP1_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0x3ffff)|value) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP1_SEL() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0x3ffff +} +func (o *RTC_CNTL_Type) SetEXT_WAKEUP1_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP1_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0x40000) >> 18 +} + +// RTC_CNTL.EXT_WAKEUP1_STATUS +func (o *RTC_CNTL_Type) SetEXT_WAKEUP1_STATUS(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1_STATUS.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg)&^(0x3ffff)|value) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP1_STATUS() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg) & 0x3ffff +} + +// RTC_CNTL.BROWN_OUT +func (o *RTC_CNTL_Type) SetBROWN_OUT_RTC_MEM_PID_CONF(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RTC_MEM_PID_CONF() uint32 { + return volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_RTC_MEM_CRC_START(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RTC_MEM_CRC_START() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_RTC_MEM_CRC_ADDR(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0xffe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RTC_MEM_CRC_ADDR() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0xffe00) >> 9 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_CLOSE_FLASH_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_CLOSE_FLASH_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_PD_RF_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_PD_RF_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_RST_WAIT(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x3ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RST_WAIT() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x3ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_RTC_MEM_CRC_LEN(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x7ff00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RTC_MEM_CRC_LEN() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x7ff00000) >> 20 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_RST_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RST_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_DBROWN_OUT_THRES(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x38000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_DBROWN_OUT_THRES() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x38000000) >> 27 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_DET(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_DET() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x80000000) >> 31 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_RTC_MEM_CRC_FINISH(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RTC_MEM_CRC_FINISH() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.DATE +func (o *RTC_CNTL_Type) SetDATE_CNTL_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_CNTL_Type) GetDATE_CNTL_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power Input/Output +type RTC_GPIO_Type struct { + OUT volatile.Register32 // 0x0 + OUT_W1TS volatile.Register32 // 0x4 + OUT_W1TC volatile.Register32 // 0x8 + ENABLE volatile.Register32 // 0xC + ENABLE_W1TS volatile.Register32 // 0x10 + ENABLE_W1TC volatile.Register32 // 0x14 + STATUS volatile.Register32 // 0x18 + STATUS_W1TS volatile.Register32 // 0x1C + STATUS_W1TC volatile.Register32 // 0x20 + IN volatile.Register32 // 0x24 + PIN0 volatile.Register32 // 0x28 + PIN1 volatile.Register32 // 0x2C + PIN2 volatile.Register32 // 0x30 + PIN3 volatile.Register32 // 0x34 + PIN4 volatile.Register32 // 0x38 + PIN5 volatile.Register32 // 0x3C + PIN6 volatile.Register32 // 0x40 + PIN7 volatile.Register32 // 0x44 + PIN8 volatile.Register32 // 0x48 + PIN9 volatile.Register32 // 0x4C + PIN10 volatile.Register32 // 0x50 + PIN11 volatile.Register32 // 0x54 + PIN12 volatile.Register32 // 0x58 + PIN13 volatile.Register32 // 0x5C + PIN14 volatile.Register32 // 0x60 + PIN15 volatile.Register32 // 0x64 + PIN16 volatile.Register32 // 0x68 + PIN17 volatile.Register32 // 0x6C + RTC_DEBUG_SEL volatile.Register32 // 0x70 + DIG_PAD_HOLD volatile.Register32 // 0x74 + HALL_SENS volatile.Register32 // 0x78 + SENSOR_PADS volatile.Register32 // 0x7C + ADC_PAD volatile.Register32 // 0x80 + PAD_DAC1 volatile.Register32 // 0x84 + PAD_DAC2 volatile.Register32 // 0x88 + XTAL_32K_PAD volatile.Register32 // 0x8C + TOUCH_CFG volatile.Register32 // 0x90 + TOUCH_PAD0 volatile.Register32 // 0x94 + TOUCH_PAD1 volatile.Register32 // 0x98 + TOUCH_PAD2 volatile.Register32 // 0x9C + TOUCH_PAD3 volatile.Register32 // 0xA0 + TOUCH_PAD4 volatile.Register32 // 0xA4 + TOUCH_PAD5 volatile.Register32 // 0xA8 + TOUCH_PAD6 volatile.Register32 // 0xAC + TOUCH_PAD7 volatile.Register32 // 0xB0 + TOUCH_PAD8 volatile.Register32 // 0xB4 + TOUCH_PAD9 volatile.Register32 // 0xB8 + EXT_WAKEUP0 volatile.Register32 // 0xBC + XTL_EXT_CTR volatile.Register32 // 0xC0 + SAR_I2C_IO volatile.Register32 // 0xC4 + DATE volatile.Register32 // 0xC8 +} + +// RTC_GPIO.OUT +func (o *RTC_GPIO_Type) SetOUT_DATA(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, volatile.LoadUint32(&o.OUT.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetOUT_DATA() uint32 { + return (volatile.LoadUint32(&o.OUT.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.OUT_W1TS +func (o *RTC_GPIO_Type) SetOUT_W1TS_OUT_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, volatile.LoadUint32(&o.OUT_W1TS.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetOUT_W1TS_OUT_DATA_W1TS() uint32 { + return (volatile.LoadUint32(&o.OUT_W1TS.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.OUT_W1TC +func (o *RTC_GPIO_Type) SetOUT_W1TC_OUT_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, volatile.LoadUint32(&o.OUT_W1TC.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetOUT_W1TC_OUT_DATA_W1TC() uint32 { + return (volatile.LoadUint32(&o.OUT_W1TC.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.ENABLE +func (o *RTC_GPIO_Type) SetENABLE(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, volatile.LoadUint32(&o.ENABLE.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetENABLE() uint32 { + return (volatile.LoadUint32(&o.ENABLE.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.ENABLE_W1TS +func (o *RTC_GPIO_Type) SetENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, volatile.LoadUint32(&o.ENABLE_W1TS.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetENABLE_W1TS() uint32 { + return (volatile.LoadUint32(&o.ENABLE_W1TS.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.ENABLE_W1TC +func (o *RTC_GPIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, volatile.LoadUint32(&o.ENABLE_W1TC.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetENABLE_W1TC() uint32 { + return (volatile.LoadUint32(&o.ENABLE_W1TC.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.STATUS +func (o *RTC_GPIO_Type) SetSTATUS_INT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetSTATUS_INT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.STATUS_W1TS +func (o *RTC_GPIO_Type) SetSTATUS_W1TS_STATUS_INT_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, volatile.LoadUint32(&o.STATUS_W1TS.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetSTATUS_W1TS_STATUS_INT_W1TS() uint32 { + return (volatile.LoadUint32(&o.STATUS_W1TS.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.STATUS_W1TC +func (o *RTC_GPIO_Type) SetSTATUS_W1TC_STATUS_INT_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, volatile.LoadUint32(&o.STATUS_W1TC.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetSTATUS_W1TC_STATUS_INT_W1TC() uint32 { + return (volatile.LoadUint32(&o.STATUS_W1TC.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.IN +func (o *RTC_GPIO_Type) SetIN_NEXT(value uint32) { + volatile.StoreUint32(&o.IN.Reg, volatile.LoadUint32(&o.IN.Reg)&^(0xffffc000)|value<<14) +} +func (o *RTC_GPIO_Type) GetIN_NEXT() uint32 { + return (volatile.LoadUint32(&o.IN.Reg) & 0xffffc000) >> 14 +} + +// RTC_GPIO.PIN0 +func (o *RTC_GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN1 +func (o *RTC_GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN2 +func (o *RTC_GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN3 +func (o *RTC_GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN4 +func (o *RTC_GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN5 +func (o *RTC_GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN6 +func (o *RTC_GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN7 +func (o *RTC_GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN8 +func (o *RTC_GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN9 +func (o *RTC_GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN10 +func (o *RTC_GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN11 +func (o *RTC_GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN12 +func (o *RTC_GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN13 +func (o *RTC_GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN14 +func (o *RTC_GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN15 +func (o *RTC_GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN16 +func (o *RTC_GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.PIN17 +func (o *RTC_GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *RTC_GPIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *RTC_GPIO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *RTC_GPIO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *RTC_GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} + +// RTC_GPIO.RTC_DEBUG_SEL +func (o *RTC_GPIO_Type) SetRTC_DEBUG_SEL_DEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f)|value) +} +func (o *RTC_GPIO_Type) GetRTC_DEBUG_SEL_DEBUG_SEL0() uint32 { + return volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f +} +func (o *RTC_GPIO_Type) SetRTC_DEBUG_SEL_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x3e0)|value<<5) +} +func (o *RTC_GPIO_Type) GetRTC_DEBUG_SEL_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x3e0) >> 5 +} +func (o *RTC_GPIO_Type) SetRTC_DEBUG_SEL_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x7c00)|value<<10) +} +func (o *RTC_GPIO_Type) GetRTC_DEBUG_SEL_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x7c00) >> 10 +} +func (o *RTC_GPIO_Type) SetRTC_DEBUG_SEL_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0xf8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetRTC_DEBUG_SEL_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0xf8000) >> 15 +} +func (o *RTC_GPIO_Type) SetRTC_DEBUG_SEL_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f00000)|value<<20) +} +func (o *RTC_GPIO_Type) GetRTC_DEBUG_SEL_DEBUG_SEL4() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f00000) >> 20 +} +func (o *RTC_GPIO_Type) SetRTC_DEBUG_SEL_DEBUG_12M_NO_GATING(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_GPIO_Type) GetRTC_DEBUG_SEL_DEBUG_12M_NO_GATING() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x2000000) >> 25 +} + +// RTC_GPIO.DIG_PAD_HOLD +func (o *RTC_GPIO_Type) SetDIG_PAD_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_PAD_HOLD.Reg, value) +} +func (o *RTC_GPIO_Type) GetDIG_PAD_HOLD() uint32 { + return volatile.LoadUint32(&o.DIG_PAD_HOLD.Reg) +} + +// RTC_GPIO.HALL_SENS +func (o *RTC_GPIO_Type) SetHALL_SENS_HALL_PHASE(value uint32) { + volatile.StoreUint32(&o.HALL_SENS.Reg, volatile.LoadUint32(&o.HALL_SENS.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_GPIO_Type) GetHALL_SENS_HALL_PHASE() uint32 { + return (volatile.LoadUint32(&o.HALL_SENS.Reg) & 0x40000000) >> 30 +} +func (o *RTC_GPIO_Type) SetHALL_SENS_XPD_HALL(value uint32) { + volatile.StoreUint32(&o.HALL_SENS.Reg, volatile.LoadUint32(&o.HALL_SENS.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetHALL_SENS_XPD_HALL() uint32 { + return (volatile.LoadUint32(&o.HALL_SENS.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.SENSOR_PADS +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x10)|value<<4) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x10) >> 4 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE4_SLP_IE(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x20)|value<<5) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE4_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x20) >> 5 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x40)|value<<6) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x40) >> 6 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE4_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x180)|value<<7) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE4_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x180) >> 7 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x200)|value<<9) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x200) >> 9 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE3_SLP_IE(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE3_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x400) >> 10 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x800)|value<<11) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x800) >> 11 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE3_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x3000)|value<<12) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE3_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x3000) >> 12 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x8000) >> 15 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x10000) >> 16 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x60000) >> 17 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0xc00000)|value<<22) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0xc00000) >> 22 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE4_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE4_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x1000000) >> 24 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE3_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE3_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x2000000) >> 25 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x4000000) >> 26 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE4_HOLD(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE4_HOLD() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE3_HOLD(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE3_HOLD() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x20000000) >> 29 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE2_HOLD(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE2_HOLD() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x40000000) >> 30 +} +func (o *RTC_GPIO_Type) SetSENSOR_PADS_SENSE1_HOLD(value uint32) { + volatile.StoreUint32(&o.SENSOR_PADS.Reg, volatile.LoadUint32(&o.SENSOR_PADS.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetSENSOR_PADS_SENSE1_HOLD() uint32 { + return (volatile.LoadUint32(&o.SENSOR_PADS.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.ADC_PAD +func (o *RTC_GPIO_Type) SetADC_PAD_ADC2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x40000) >> 18 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x600000)|value<<21) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x600000) >> 21 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x800000) >> 23 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x1000000) >> 24 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x2000000) >> 25 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0xc000000)|value<<26) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0xc000000) >> 26 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x20000000) >> 29 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC2_HOLD(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC2_HOLD() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x40000000) >> 30 +} +func (o *RTC_GPIO_Type) SetADC_PAD_ADC1_HOLD(value uint32) { + volatile.StoreUint32(&o.ADC_PAD.Reg, volatile.LoadUint32(&o.ADC_PAD.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetADC_PAD_ADC1_HOLD() uint32 { + return (volatile.LoadUint32(&o.ADC_PAD.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.PAD_DAC1 +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x400) >> 10 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x800)|value<<11) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x800) >> 11 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x18000)|value<<15) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x18000) >> 15 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x20000) >> 17 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x40000) >> 18 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x7f80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x7f80000) >> 19 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x20000000) >> 29 +} +func (o *RTC_GPIO_Type) SetPAD_DAC1_PDAC1_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_GPIO_Type) GetPAD_DAC1_PDAC1_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0xc0000000) >> 30 +} + +// RTC_GPIO.PAD_DAC2 +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x400)|value<<10) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x400) >> 10 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x800)|value<<11) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x800) >> 11 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x18000)|value<<15) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x18000) >> 15 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x20000) >> 17 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x40000) >> 18 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x7f80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x7f80000) >> 19 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x20000000) >> 29 +} +func (o *RTC_GPIO_Type) SetPAD_DAC2_PDAC2_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_GPIO_Type) GetPAD_DAC2_PDAC2_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0xc0000000) >> 30 +} + +// RTC_GPIO.XTAL_32K_PAD +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_DBIAS_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x6)|value<<1) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_DBIAS_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x6) >> 1 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_DRES_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x18)|value<<3) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_DRES_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x18) >> 3 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x20)|value<<5) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x20) >> 5 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x40)|value<<6) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x40) >> 6 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x80)|value<<7) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x80) >> 7 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x100)|value<<8) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x100) >> 8 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x600)|value<<9) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x600) >> 9 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x800)|value<<11) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x800) >> 11 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x18000)|value<<15) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x18000) >> 15 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x20000) >> 17 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x40000) >> 18 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_XPD_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_XPD_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_DAC_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x300000)|value<<20) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_DAC_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x300000) >> 20 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x800000) >> 23 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_HOLD(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_HOLD() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x1000000) >> 24 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32P_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x6000000)|value<<25) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32P_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x6000000) >> 25 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_HOLD(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_HOLD() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0x20000000) >> 29 +} +func (o *RTC_GPIO_Type) SetXTAL_32K_PAD_X32N_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32K_PAD.Reg, volatile.LoadUint32(&o.XTAL_32K_PAD.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_GPIO_Type) GetXTAL_32K_PAD_X32N_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32K_PAD.Reg) & 0xc0000000) >> 30 +} + +// RTC_GPIO.TOUCH_CFG +func (o *RTC_GPIO_Type) SetTOUCH_CFG_TOUCH_DCUR(value uint32) { + volatile.StoreUint32(&o.TOUCH_CFG.Reg, volatile.LoadUint32(&o.TOUCH_CFG.Reg)&^(0x1800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_CFG_TOUCH_DCUR() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CFG.Reg) & 0x1800000) >> 23 +} +func (o *RTC_GPIO_Type) SetTOUCH_CFG_TOUCH_DRANGE(value uint32) { + volatile.StoreUint32(&o.TOUCH_CFG.Reg, volatile.LoadUint32(&o.TOUCH_CFG.Reg)&^(0x6000000)|value<<25) +} +func (o *RTC_GPIO_Type) GetTOUCH_CFG_TOUCH_DRANGE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CFG.Reg) & 0x6000000) >> 25 +} +func (o *RTC_GPIO_Type) SetTOUCH_CFG_TOUCH_DREFL(value uint32) { + volatile.StoreUint32(&o.TOUCH_CFG.Reg, volatile.LoadUint32(&o.TOUCH_CFG.Reg)&^(0x18000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetTOUCH_CFG_TOUCH_DREFL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CFG.Reg) & 0x18000000) >> 27 +} +func (o *RTC_GPIO_Type) SetTOUCH_CFG_TOUCH_DREFH(value uint32) { + volatile.StoreUint32(&o.TOUCH_CFG.Reg, volatile.LoadUint32(&o.TOUCH_CFG.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetTOUCH_CFG_TOUCH_DREFH() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CFG.Reg) & 0x60000000) >> 29 +} +func (o *RTC_GPIO_Type) SetTOUCH_CFG_TOUCH_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.TOUCH_CFG.Reg, volatile.LoadUint32(&o.TOUCH_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetTOUCH_CFG_TOUCH_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CFG.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.TOUCH_PAD0 +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000) >> 15 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000) >> 16 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000) >> 17 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x3800000) >> 23 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000000) >> 29 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD0_HOLD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD0_HOLD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.TOUCH_PAD1 +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000) >> 15 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000) >> 16 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000) >> 17 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x3800000) >> 23 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000000) >> 29 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD1_HOLD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD1_HOLD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.TOUCH_PAD2 +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000) >> 15 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000) >> 16 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000) >> 17 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x3800000) >> 23 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000000) >> 29 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD2_HOLD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD2_HOLD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.TOUCH_PAD3 +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000) >> 15 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000) >> 16 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000) >> 17 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x3800000) >> 23 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000000) >> 29 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD3_HOLD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD3_HOLD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.TOUCH_PAD4 +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000) >> 15 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000) >> 16 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000) >> 17 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x3800000) >> 23 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000000) >> 29 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD4_HOLD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD4_HOLD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.TOUCH_PAD5 +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000) >> 15 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000) >> 16 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000) >> 17 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x3800000) >> 23 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000000) >> 29 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD5_HOLD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD5_HOLD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.TOUCH_PAD6 +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000) >> 15 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000) >> 16 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000) >> 17 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x3800000) >> 23 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000000) >> 29 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD6_HOLD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD6_HOLD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.TOUCH_PAD7 +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x1000) >> 12 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x2000) >> 13 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x4000) >> 14 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000) >> 15 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000) >> 16 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000) >> 17 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x3800000) >> 23 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000000) >> 27 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000000) >> 28 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000000) >> 29 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD7_HOLD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD7_HOLD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x80000000) >> 31 +} + +// RTC_GPIO.TOUCH_PAD8 +func (o *RTC_GPIO_Type) SetTOUCH_PAD8_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD8_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD8_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD8_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD8_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD8_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD8_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD8_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD8_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD8_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x3800000) >> 23 +} + +// RTC_GPIO.TOUCH_PAD9 +func (o *RTC_GPIO_Type) SetTOUCH_PAD9_TO_GPIO(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD9_TO_GPIO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x80000) >> 19 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD9_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD9_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x100000) >> 20 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD9_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD9_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x200000) >> 21 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD9_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD9_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x400000) >> 22 +} +func (o *RTC_GPIO_Type) SetTOUCH_PAD9_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetTOUCH_PAD9_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x3800000) >> 23 +} + +// RTC_GPIO.EXT_WAKEUP0 +func (o *RTC_GPIO_Type) SetEXT_WAKEUP0_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP0.Reg, volatile.LoadUint32(&o.EXT_WAKEUP0.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetEXT_WAKEUP0_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP0.Reg) & 0xf8000000) >> 27 +} + +// RTC_GPIO.XTL_EXT_CTR +func (o *RTC_GPIO_Type) SetXTL_EXT_CTR_SEL(value uint32) { + volatile.StoreUint32(&o.XTL_EXT_CTR.Reg, volatile.LoadUint32(&o.XTL_EXT_CTR.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_GPIO_Type) GetXTL_EXT_CTR_SEL() uint32 { + return (volatile.LoadUint32(&o.XTL_EXT_CTR.Reg) & 0xf8000000) >> 27 +} + +// RTC_GPIO.SAR_I2C_IO +func (o *RTC_GPIO_Type) SetSAR_I2C_IO_SAR_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xf800000)|value<<23) +} +func (o *RTC_GPIO_Type) GetSAR_I2C_IO_SAR_DEBUG_BIT_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xf800000) >> 23 +} +func (o *RTC_GPIO_Type) SetSAR_I2C_IO_SAR_I2C_SCL_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0x30000000)|value<<28) +} +func (o *RTC_GPIO_Type) GetSAR_I2C_IO_SAR_I2C_SCL_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0x30000000) >> 28 +} +func (o *RTC_GPIO_Type) SetSAR_I2C_IO_SAR_I2C_SDA_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_GPIO_Type) GetSAR_I2C_IO_SAR_I2C_SDA_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xc0000000) >> 30 +} + +// RTC_GPIO.DATE +func (o *RTC_GPIO_Type) SetDATE_IO_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_GPIO_Type) GetDATE_IO_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power I2C (Inter-Integrated Circuit) Controller +type RTC_I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTRL volatile.Register32 // 0x4 + DEBUG_STATUS volatile.Register32 // 0x8 + TIMEOUT volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + _ [8]byte + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_EN volatile.Register32 // 0x28 + INT_ST volatile.Register32 // 0x2C + SDA_DUTY volatile.Register32 // 0x30 + _ [4]byte + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_PERIOD volatile.Register32 // 0x40 + SCL_STOP_PERIOD volatile.Register32 // 0x44 + CMD volatile.Register32 // 0x48 +} + +// RTC_I2C.SCL_LOW_PERIOD +func (o *RTC_I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ffffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ffffff +} + +// RTC_I2C.CTRL +func (o *RTC_I2C_Type) SetCTRL_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetCTRL_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetCTRL_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetCTRL_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetCTRL_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetCTRL_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetCTRL_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetCTRL_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetCTRL_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetCTRL_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetCTRL_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetCTRL_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} + +// RTC_I2C.DEBUG_STATUS +func (o *RTC_I2C_Type) SetDEBUG_STATUS_ACK_VAL(value uint32) { + volatile.StoreUint32(&o.DEBUG_STATUS.Reg, volatile.LoadUint32(&o.DEBUG_STATUS.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetDEBUG_STATUS_ACK_VAL() uint32 { + return volatile.LoadUint32(&o.DEBUG_STATUS.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetDEBUG_STATUS_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.DEBUG_STATUS.Reg, volatile.LoadUint32(&o.DEBUG_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetDEBUG_STATUS_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.DEBUG_STATUS.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetDEBUG_STATUS_TIMED_OUT(value uint32) { + volatile.StoreUint32(&o.DEBUG_STATUS.Reg, volatile.LoadUint32(&o.DEBUG_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetDEBUG_STATUS_TIMED_OUT() uint32 { + return (volatile.LoadUint32(&o.DEBUG_STATUS.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetDEBUG_STATUS_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.DEBUG_STATUS.Reg, volatile.LoadUint32(&o.DEBUG_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetDEBUG_STATUS_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.DEBUG_STATUS.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetDEBUG_STATUS_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.DEBUG_STATUS.Reg, volatile.LoadUint32(&o.DEBUG_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetDEBUG_STATUS_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.DEBUG_STATUS.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetDEBUG_STATUS_SLAVE_ADDR_MATCH(value uint32) { + volatile.StoreUint32(&o.DEBUG_STATUS.Reg, volatile.LoadUint32(&o.DEBUG_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetDEBUG_STATUS_SLAVE_ADDR_MATCH() uint32 { + return (volatile.LoadUint32(&o.DEBUG_STATUS.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetDEBUG_STATUS_BYTE_TRANS(value uint32) { + volatile.StoreUint32(&o.DEBUG_STATUS.Reg, volatile.LoadUint32(&o.DEBUG_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetDEBUG_STATUS_BYTE_TRANS() uint32 { + return (volatile.LoadUint32(&o.DEBUG_STATUS.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetDEBUG_STATUS_MAIN_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_STATUS.Reg, volatile.LoadUint32(&o.DEBUG_STATUS.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_I2C_Type) GetDEBUG_STATUS_MAIN_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_STATUS.Reg) & 0xe000000) >> 25 +} +func (o *RTC_I2C_Type) SetDEBUG_STATUS_SCL_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_STATUS.Reg, volatile.LoadUint32(&o.DEBUG_STATUS.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_I2C_Type) GetDEBUG_STATUS_SCL_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_STATUS.Reg) & 0x70000000) >> 28 +} + +// RTC_I2C.TIMEOUT +func (o *RTC_I2C_Type) SetTIMEOUT(value uint32) { + volatile.StoreUint32(&o.TIMEOUT.Reg, volatile.LoadUint32(&o.TIMEOUT.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetTIMEOUT() uint32 { + return volatile.LoadUint32(&o.TIMEOUT.Reg) & 0xfffff +} + +// RTC_I2C.SLAVE_ADDR +func (o *RTC_I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *RTC_I2C_Type) SetSLAVE_ADDR__10BIT(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR__10BIT() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.INT_RAW +func (o *RTC_I2C_Type) SetINT_RAW_SLAVE_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_RAW_SLAVE_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_RAW_MASTER_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_RAW_MASTER_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} + +// RTC_I2C.INT_CLR +func (o *RTC_I2C_Type) SetINT_CLR_SLAVE_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_CLR_SLAVE_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_CLR_MASTER_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_CLR_MASTER_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// RTC_I2C.SDA_DUTY +func (o *RTC_I2C_Type) SetSDA_DUTY(value uint32) { + volatile.StoreUint32(&o.SDA_DUTY.Reg, volatile.LoadUint32(&o.SDA_DUTY.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSDA_DUTY() uint32 { + return volatile.LoadUint32(&o.SDA_DUTY.Reg) & 0xfffff +} + +// RTC_I2C.SCL_HIGH_PERIOD +func (o *RTC_I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.SCL_START_PERIOD +func (o *RTC_I2C_Type) SetSCL_START_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_START_PERIOD.Reg, volatile.LoadUint32(&o.SCL_START_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_START_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_START_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.SCL_STOP_PERIOD +func (o *RTC_I2C_Type) SetSCL_STOP_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_PERIOD.Reg, volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_STOP_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.CMD +func (o *RTC_I2C_Type) SetCMD_VAL(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD_VAL() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD_DONE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31 +} + +// SD/MMC Host Controller +type SDHOST_Type struct { + CTRL volatile.Register32 // 0x0 + _ [4]byte + CLKDIV volatile.Register32 // 0x8 + CLKSRC volatile.Register32 // 0xC + CLKENA volatile.Register32 // 0x10 + TMOUT volatile.Register32 // 0x14 + CTYPE volatile.Register32 // 0x18 + BLKSIZ volatile.Register32 // 0x1C + BYTCNT volatile.Register32 // 0x20 + INTMASK volatile.Register32 // 0x24 + CMDARG volatile.Register32 // 0x28 + CMD volatile.Register32 // 0x2C + RESP0 volatile.Register32 // 0x30 + RESP1 volatile.Register32 // 0x34 + RESP2 volatile.Register32 // 0x38 + RESP3 volatile.Register32 // 0x3C + MINTSTS volatile.Register32 // 0x40 + RINTSTS volatile.Register32 // 0x44 + STATUS volatile.Register32 // 0x48 + FIFOTH volatile.Register32 // 0x4C + CDETECT volatile.Register32 // 0x50 + WRTPRT volatile.Register32 // 0x54 + _ [4]byte + TCBCNT volatile.Register32 // 0x5C + TBBCNT volatile.Register32 // 0x60 + DEBNCE volatile.Register32 // 0x64 + USRID volatile.Register32 // 0x68 + VERID volatile.Register32 // 0x6C + HCON volatile.Register32 // 0x70 + UHS volatile.Register32 // 0x74 + RST_N volatile.Register32 // 0x78 + _ [4]byte + BMOD volatile.Register32 // 0x80 + PLDMND volatile.Register32 // 0x84 + DBADDR volatile.Register32 // 0x88 + IDSTS volatile.Register32 // 0x8C + IDINTEN volatile.Register32 // 0x90 + DSCADDR volatile.Register32 // 0x94 + BUFADDR volatile.Register32 // 0x98 + _ [100]byte + CARDTHRCTL volatile.Register32 // 0x100 + _ [8]byte + EMMCDDR volatile.Register32 // 0x10C + ENSHIFT volatile.Register32 // 0x110 + _ [236]byte + BUFFIFO volatile.Register32 // 0x200 + _ [1532]byte + CLK_EDGE_SEL volatile.Register32 // 0x800 +} + +// SDHOST.CTRL: Control register +func (o *SDHOST_Type) SetCTRL_CONTROLLER_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetCTRL_CONTROLLER_RESET() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *SDHOST_Type) SetCTRL_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetCTRL_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetCTRL_DMA_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetCTRL_DMA_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetCTRL_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SDHOST_Type) GetCTRL_INT_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *SDHOST_Type) SetCTRL_READ_WAIT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SDHOST_Type) GetCTRL_READ_WAIT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SDHOST_Type) SetCTRL_SEND_IRQ_RESPONSE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SDHOST_Type) GetCTRL_SEND_IRQ_RESPONSE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SDHOST_Type) SetCTRL_ABORT_READ_DATA(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetCTRL_ABORT_READ_DATA() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetCTRL_SEND_CCSD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetCTRL_SEND_CCSD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetCTRL_SEND_AUTO_STOP_CCSD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SDHOST_Type) GetCTRL_SEND_AUTO_STOP_CCSD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SDHOST_Type) SetCTRL_CEATA_DEVICE_INTERRUPT_STATUS(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SDHOST_Type) GetCTRL_CEATA_DEVICE_INTERRUPT_STATUS() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11 +} + +// SDHOST.CLKDIV: Clock divider configuration register +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER0(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff)|value) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER0() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff +} +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER1(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff00)|value<<8) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER1() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff00) >> 8 +} +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER2(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff0000)|value<<16) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER2() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff0000) >> 16 +} +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER3(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff000000)|value<<24) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER3() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff000000) >> 24 +} + +// SDHOST.CLKSRC: Clock source selection register +func (o *SDHOST_Type) SetCLKSRC(value uint32) { + volatile.StoreUint32(&o.CLKSRC.Reg, volatile.LoadUint32(&o.CLKSRC.Reg)&^(0xf)|value) +} +func (o *SDHOST_Type) GetCLKSRC() uint32 { + return volatile.LoadUint32(&o.CLKSRC.Reg) & 0xf +} + +// SDHOST.CLKENA: Clock enable register +func (o *SDHOST_Type) SetCLKENA_CCLK_ENABLE(value uint32) { + volatile.StoreUint32(&o.CLKENA.Reg, volatile.LoadUint32(&o.CLKENA.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetCLKENA_CCLK_ENABLE() uint32 { + return volatile.LoadUint32(&o.CLKENA.Reg) & 0x3 +} +func (o *SDHOST_Type) SetCLKENA_LP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CLKENA.Reg, volatile.LoadUint32(&o.CLKENA.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetCLKENA_LP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CLKENA.Reg) & 0x30000) >> 16 +} + +// SDHOST.TMOUT: Data and response timeout configuration register +func (o *SDHOST_Type) SetTMOUT_RESPONSE_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.TMOUT.Reg, volatile.LoadUint32(&o.TMOUT.Reg)&^(0xff)|value) +} +func (o *SDHOST_Type) GetTMOUT_RESPONSE_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.TMOUT.Reg) & 0xff +} +func (o *SDHOST_Type) SetTMOUT_DATA_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.TMOUT.Reg, volatile.LoadUint32(&o.TMOUT.Reg)&^(0xffffff00)|value<<8) +} +func (o *SDHOST_Type) GetTMOUT_DATA_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.TMOUT.Reg) & 0xffffff00) >> 8 +} + +// SDHOST.CTYPE: Card bus width configuration register +func (o *SDHOST_Type) SetCTYPE_CARD_WIDTH4(value uint32) { + volatile.StoreUint32(&o.CTYPE.Reg, volatile.LoadUint32(&o.CTYPE.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetCTYPE_CARD_WIDTH4() uint32 { + return volatile.LoadUint32(&o.CTYPE.Reg) & 0x3 +} +func (o *SDHOST_Type) SetCTYPE_CARD_WIDTH8(value uint32) { + volatile.StoreUint32(&o.CTYPE.Reg, volatile.LoadUint32(&o.CTYPE.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetCTYPE_CARD_WIDTH8() uint32 { + return (volatile.LoadUint32(&o.CTYPE.Reg) & 0x30000) >> 16 +} + +// SDHOST.BLKSIZ: Card data block size configuration register +func (o *SDHOST_Type) SetBLKSIZ_BLOCK_SIZE(value uint32) { + volatile.StoreUint32(&o.BLKSIZ.Reg, volatile.LoadUint32(&o.BLKSIZ.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetBLKSIZ_BLOCK_SIZE() uint32 { + return volatile.LoadUint32(&o.BLKSIZ.Reg) & 0xffff +} + +// SDHOST.BYTCNT: Data transfer length configuration register +func (o *SDHOST_Type) SetBYTCNT(value uint32) { + volatile.StoreUint32(&o.BYTCNT.Reg, value) +} +func (o *SDHOST_Type) GetBYTCNT() uint32 { + return volatile.LoadUint32(&o.BYTCNT.Reg) +} + +// SDHOST.INTMASK: SDIO interrupt mask register +func (o *SDHOST_Type) SetINTMASK_INT_MASK(value uint32) { + volatile.StoreUint32(&o.INTMASK.Reg, volatile.LoadUint32(&o.INTMASK.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetINTMASK_INT_MASK() uint32 { + return volatile.LoadUint32(&o.INTMASK.Reg) & 0xffff +} +func (o *SDHOST_Type) SetINTMASK_SDIO_INT_MASK(value uint32) { + volatile.StoreUint32(&o.INTMASK.Reg, volatile.LoadUint32(&o.INTMASK.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetINTMASK_SDIO_INT_MASK() uint32 { + return (volatile.LoadUint32(&o.INTMASK.Reg) & 0x30000) >> 16 +} + +// SDHOST.CMDARG: Command argument data register +func (o *SDHOST_Type) SetCMDARG(value uint32) { + volatile.StoreUint32(&o.CMDARG.Reg, value) +} +func (o *SDHOST_Type) GetCMDARG() uint32 { + return volatile.LoadUint32(&o.CMDARG.Reg) +} + +// SDHOST.CMD: Command and boot configuration register +func (o *SDHOST_Type) SetCMD_INDEX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3f)|value) +} +func (o *SDHOST_Type) GetCMD_INDEX() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x3f +} +func (o *SDHOST_Type) SetCMD_RESPONSE_EXPECT(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40)|value<<6) +} +func (o *SDHOST_Type) GetCMD_RESPONSE_EXPECT() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40) >> 6 +} +func (o *SDHOST_Type) SetCMD_RESPONSE_LENGTH(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80)|value<<7) +} +func (o *SDHOST_Type) GetCMD_RESPONSE_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80) >> 7 +} +func (o *SDHOST_Type) SetCMD_CHECK_RESPONSE_CRC(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetCMD_CHECK_RESPONSE_CRC() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetCMD_DATA_EXPECTED(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetCMD_DATA_EXPECTED() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetCMD_READ_WRITE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400)|value<<10) +} +func (o *SDHOST_Type) GetCMD_READ_WRITE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400) >> 10 +} +func (o *SDHOST_Type) SetCMD_TRANSFER_MODE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800)|value<<11) +} +func (o *SDHOST_Type) GetCMD_TRANSFER_MODE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800) >> 11 +} +func (o *SDHOST_Type) SetCMD_SEND_AUTO_STOP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000)|value<<12) +} +func (o *SDHOST_Type) GetCMD_SEND_AUTO_STOP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000) >> 12 +} +func (o *SDHOST_Type) SetCMD_WAIT_PRVDATA_COMPLETE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2000)|value<<13) +} +func (o *SDHOST_Type) GetCMD_WAIT_PRVDATA_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2000) >> 13 +} +func (o *SDHOST_Type) SetCMD_STOP_ABORT_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4000)|value<<14) +} +func (o *SDHOST_Type) GetCMD_STOP_ABORT_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4000) >> 14 +} +func (o *SDHOST_Type) SetCMD_SEND_INITIALIZATION(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8000)|value<<15) +} +func (o *SDHOST_Type) GetCMD_SEND_INITIALIZATION() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8000) >> 15 +} +func (o *SDHOST_Type) SetCMD_CARD_NUMBER(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1f0000)|value<<16) +} +func (o *SDHOST_Type) GetCMD_CARD_NUMBER() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1f0000) >> 16 +} +func (o *SDHOST_Type) SetCMD_UPDATE_CLOCK_REGISTERS_ONLY(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SDHOST_Type) GetCMD_UPDATE_CLOCK_REGISTERS_ONLY() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200000) >> 21 +} +func (o *SDHOST_Type) SetCMD_READ_CEATA_DEVICE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SDHOST_Type) GetCMD_READ_CEATA_DEVICE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400000) >> 22 +} +func (o *SDHOST_Type) SetCMD_CCS_EXPECTED(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SDHOST_Type) GetCMD_CCS_EXPECTED() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SDHOST_Type) SetCMD_USE_HOLE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SDHOST_Type) GetCMD_USE_HOLE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29 +} +func (o *SDHOST_Type) SetCMD_START_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SDHOST_Type) GetCMD_START_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31 +} + +// SDHOST.RESP0: Response data register +func (o *SDHOST_Type) SetRESP0(value uint32) { + volatile.StoreUint32(&o.RESP0.Reg, value) +} +func (o *SDHOST_Type) GetRESP0() uint32 { + return volatile.LoadUint32(&o.RESP0.Reg) +} + +// SDHOST.RESP1: Long response data register +func (o *SDHOST_Type) SetRESP1(value uint32) { + volatile.StoreUint32(&o.RESP1.Reg, value) +} +func (o *SDHOST_Type) GetRESP1() uint32 { + return volatile.LoadUint32(&o.RESP1.Reg) +} + +// SDHOST.RESP2: Long response data register +func (o *SDHOST_Type) SetRESP2(value uint32) { + volatile.StoreUint32(&o.RESP2.Reg, value) +} +func (o *SDHOST_Type) GetRESP2() uint32 { + return volatile.LoadUint32(&o.RESP2.Reg) +} + +// SDHOST.RESP3: Long response data register +func (o *SDHOST_Type) SetRESP3(value uint32) { + volatile.StoreUint32(&o.RESP3.Reg, value) +} +func (o *SDHOST_Type) GetRESP3() uint32 { + return volatile.LoadUint32(&o.RESP3.Reg) +} + +// SDHOST.MINTSTS: Masked interrupt status register +func (o *SDHOST_Type) SetMINTSTS_INT_STATUS_MSK(value uint32) { + volatile.StoreUint32(&o.MINTSTS.Reg, volatile.LoadUint32(&o.MINTSTS.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetMINTSTS_INT_STATUS_MSK() uint32 { + return volatile.LoadUint32(&o.MINTSTS.Reg) & 0xffff +} +func (o *SDHOST_Type) SetMINTSTS_SDIO_INTERRUPT_MSK(value uint32) { + volatile.StoreUint32(&o.MINTSTS.Reg, volatile.LoadUint32(&o.MINTSTS.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetMINTSTS_SDIO_INTERRUPT_MSK() uint32 { + return (volatile.LoadUint32(&o.MINTSTS.Reg) & 0x30000) >> 16 +} + +// SDHOST.RINTSTS: Raw interrupt status register +func (o *SDHOST_Type) SetRINTSTS_INT_STATUS_RAW(value uint32) { + volatile.StoreUint32(&o.RINTSTS.Reg, volatile.LoadUint32(&o.RINTSTS.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetRINTSTS_INT_STATUS_RAW() uint32 { + return volatile.LoadUint32(&o.RINTSTS.Reg) & 0xffff +} +func (o *SDHOST_Type) SetRINTSTS_SDIO_INTERRUPT_RAW(value uint32) { + volatile.StoreUint32(&o.RINTSTS.Reg, volatile.LoadUint32(&o.RINTSTS.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetRINTSTS_SDIO_INTERRUPT_RAW() uint32 { + return (volatile.LoadUint32(&o.RINTSTS.Reg) & 0x30000) >> 16 +} + +// SDHOST.STATUS: SD/MMC status register +func (o *SDHOST_Type) SetSTATUS_FIFO_RX_WATERMARK(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_RX_WATERMARK() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_TX_WATERMARK(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_TX_WATERMARK() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *SDHOST_Type) SetSTATUS_COMMAND_FSM_STATES(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *SDHOST_Type) GetSTATUS_COMMAND_FSM_STATES() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf0) >> 4 +} +func (o *SDHOST_Type) SetSTATUS_DATA_3_STATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetSTATUS_DATA_3_STATUS() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetSTATUS_DATA_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetSTATUS_DATA_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetSTATUS_DATA_STATE_MC_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400)|value<<10) +} +func (o *SDHOST_Type) GetSTATUS_DATA_STATE_MC_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400) >> 10 +} +func (o *SDHOST_Type) SetSTATUS_RESPONSE_INDEX(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1f800)|value<<11) +} +func (o *SDHOST_Type) GetSTATUS_RESPONSE_INDEX() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1f800) >> 11 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_COUNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ffe0000)|value<<17) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_COUNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3ffe0000) >> 17 +} + +// SDHOST.FIFOTH: FIFO configuration register +func (o *SDHOST_Type) SetFIFOTH_TX_WMARK(value uint32) { + volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0xfff)|value) +} +func (o *SDHOST_Type) GetFIFOTH_TX_WMARK() uint32 { + return volatile.LoadUint32(&o.FIFOTH.Reg) & 0xfff +} +func (o *SDHOST_Type) SetFIFOTH_RX_WMARK(value uint32) { + volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0x7ff0000)|value<<16) +} +func (o *SDHOST_Type) GetFIFOTH_RX_WMARK() uint32 { + return (volatile.LoadUint32(&o.FIFOTH.Reg) & 0x7ff0000) >> 16 +} +func (o *SDHOST_Type) SetFIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE(value uint32) { + volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0x70000000)|value<<28) +} +func (o *SDHOST_Type) GetFIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE() uint32 { + return (volatile.LoadUint32(&o.FIFOTH.Reg) & 0x70000000) >> 28 +} + +// SDHOST.CDETECT: Card detect register +func (o *SDHOST_Type) SetCDETECT_CARD_DETECT_N(value uint32) { + volatile.StoreUint32(&o.CDETECT.Reg, volatile.LoadUint32(&o.CDETECT.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetCDETECT_CARD_DETECT_N() uint32 { + return volatile.LoadUint32(&o.CDETECT.Reg) & 0x3 +} + +// SDHOST.WRTPRT: Card write protection (WP) status register +func (o *SDHOST_Type) SetWRTPRT_WRITE_PROTECT(value uint32) { + volatile.StoreUint32(&o.WRTPRT.Reg, volatile.LoadUint32(&o.WRTPRT.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetWRTPRT_WRITE_PROTECT() uint32 { + return volatile.LoadUint32(&o.WRTPRT.Reg) & 0x3 +} + +// SDHOST.TCBCNT: Transferred byte count register +func (o *SDHOST_Type) SetTCBCNT(value uint32) { + volatile.StoreUint32(&o.TCBCNT.Reg, value) +} +func (o *SDHOST_Type) GetTCBCNT() uint32 { + return volatile.LoadUint32(&o.TCBCNT.Reg) +} + +// SDHOST.TBBCNT: Transferred byte count register +func (o *SDHOST_Type) SetTBBCNT(value uint32) { + volatile.StoreUint32(&o.TBBCNT.Reg, value) +} +func (o *SDHOST_Type) GetTBBCNT() uint32 { + return volatile.LoadUint32(&o.TBBCNT.Reg) +} + +// SDHOST.DEBNCE: Debounce filter time configuration register +func (o *SDHOST_Type) SetDEBNCE_DEBOUNCE_COUNT(value uint32) { + volatile.StoreUint32(&o.DEBNCE.Reg, volatile.LoadUint32(&o.DEBNCE.Reg)&^(0xffffff)|value) +} +func (o *SDHOST_Type) GetDEBNCE_DEBOUNCE_COUNT() uint32 { + return volatile.LoadUint32(&o.DEBNCE.Reg) & 0xffffff +} + +// SDHOST.USRID: User ID (scratchpad) register +func (o *SDHOST_Type) SetUSRID(value uint32) { + volatile.StoreUint32(&o.USRID.Reg, value) +} +func (o *SDHOST_Type) GetUSRID() uint32 { + return volatile.LoadUint32(&o.USRID.Reg) +} + +// SDHOST.VERID: Version ID (scratchpad) register +func (o *SDHOST_Type) SetVERID(value uint32) { + volatile.StoreUint32(&o.VERID.Reg, value) +} +func (o *SDHOST_Type) GetVERID() uint32 { + return volatile.LoadUint32(&o.VERID.Reg) +} + +// SDHOST.HCON: Hardware feature register +func (o *SDHOST_Type) SetHCON_CARD_TYPE(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetHCON_CARD_TYPE() uint32 { + return volatile.LoadUint32(&o.HCON.Reg) & 0x1 +} +func (o *SDHOST_Type) SetHCON_CARD_NUM(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x3e)|value<<1) +} +func (o *SDHOST_Type) GetHCON_CARD_NUM() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x3e) >> 1 +} +func (o *SDHOST_Type) SetHCON_BUS_TYPE(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x40)|value<<6) +} +func (o *SDHOST_Type) GetHCON_BUS_TYPE() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x40) >> 6 +} +func (o *SDHOST_Type) SetHCON_DATA_WIDTH(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x380)|value<<7) +} +func (o *SDHOST_Type) GetHCON_DATA_WIDTH() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x380) >> 7 +} +func (o *SDHOST_Type) SetHCON_ADDR_WIDTH(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0xfc00)|value<<10) +} +func (o *SDHOST_Type) GetHCON_ADDR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0xfc00) >> 10 +} +func (o *SDHOST_Type) SetHCON_DMA_WIDTH(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x1c0000)|value<<18) +} +func (o *SDHOST_Type) GetHCON_DMA_WIDTH() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x1c0000) >> 18 +} +func (o *SDHOST_Type) SetHCON_RAM_INDISE(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x200000)|value<<21) +} +func (o *SDHOST_Type) GetHCON_RAM_INDISE() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x200000) >> 21 +} +func (o *SDHOST_Type) SetHCON_HOLD(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x400000)|value<<22) +} +func (o *SDHOST_Type) GetHCON_HOLD() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x400000) >> 22 +} +func (o *SDHOST_Type) SetHCON_NUM_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x3000000)|value<<24) +} +func (o *SDHOST_Type) GetHCON_NUM_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x3000000) >> 24 +} + +// SDHOST.UHS: UHS-1 register +func (o *SDHOST_Type) SetUHS_DDR(value uint32) { + volatile.StoreUint32(&o.UHS.Reg, volatile.LoadUint32(&o.UHS.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetUHS_DDR() uint32 { + return (volatile.LoadUint32(&o.UHS.Reg) & 0x30000) >> 16 +} + +// SDHOST.RST_N: Card reset register +func (o *SDHOST_Type) SetRST_N_CARD_RESET(value uint32) { + volatile.StoreUint32(&o.RST_N.Reg, volatile.LoadUint32(&o.RST_N.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetRST_N_CARD_RESET() uint32 { + return volatile.LoadUint32(&o.RST_N.Reg) & 0x3 +} + +// SDHOST.BMOD: Burst mode transfer configuration register +func (o *SDHOST_Type) SetBMOD_SWR(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetBMOD_SWR() uint32 { + return volatile.LoadUint32(&o.BMOD.Reg) & 0x1 +} +func (o *SDHOST_Type) SetBMOD_FB(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetBMOD_FB() uint32 { + return (volatile.LoadUint32(&o.BMOD.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetBMOD_DE(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x80)|value<<7) +} +func (o *SDHOST_Type) GetBMOD_DE() uint32 { + return (volatile.LoadUint32(&o.BMOD.Reg) & 0x80) >> 7 +} +func (o *SDHOST_Type) SetBMOD_PBL(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x700)|value<<8) +} +func (o *SDHOST_Type) GetBMOD_PBL() uint32 { + return (volatile.LoadUint32(&o.BMOD.Reg) & 0x700) >> 8 +} + +// SDHOST.PLDMND: Poll demand configuration register +func (o *SDHOST_Type) SetPLDMND(value uint32) { + volatile.StoreUint32(&o.PLDMND.Reg, value) +} +func (o *SDHOST_Type) GetPLDMND() uint32 { + return volatile.LoadUint32(&o.PLDMND.Reg) +} + +// SDHOST.DBADDR: Descriptor base address register +func (o *SDHOST_Type) SetDBADDR(value uint32) { + volatile.StoreUint32(&o.DBADDR.Reg, value) +} +func (o *SDHOST_Type) GetDBADDR() uint32 { + return volatile.LoadUint32(&o.DBADDR.Reg) +} + +// SDHOST.IDSTS: IDMAC status register +func (o *SDHOST_Type) SetIDSTS_TI(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetIDSTS_TI() uint32 { + return volatile.LoadUint32(&o.IDSTS.Reg) & 0x1 +} +func (o *SDHOST_Type) SetIDSTS_RI(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetIDSTS_RI() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetIDSTS_FBE(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetIDSTS_FBE() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetIDSTS_DU(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x10)|value<<4) +} +func (o *SDHOST_Type) GetIDSTS_DU() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x10) >> 4 +} +func (o *SDHOST_Type) SetIDSTS_CES(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x20)|value<<5) +} +func (o *SDHOST_Type) GetIDSTS_CES() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x20) >> 5 +} +func (o *SDHOST_Type) SetIDSTS_NIS(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetIDSTS_NIS() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetIDSTS_AIS(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetIDSTS_AIS() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetIDSTS_FBE_CODE(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1c00)|value<<10) +} +func (o *SDHOST_Type) GetIDSTS_FBE_CODE() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x1c00) >> 10 +} +func (o *SDHOST_Type) SetIDSTS_FSM(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1e000)|value<<13) +} +func (o *SDHOST_Type) GetIDSTS_FSM() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x1e000) >> 13 +} + +// SDHOST.IDINTEN: IDMAC interrupt enable register +func (o *SDHOST_Type) SetIDINTEN_TI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetIDINTEN_TI() uint32 { + return volatile.LoadUint32(&o.IDINTEN.Reg) & 0x1 +} +func (o *SDHOST_Type) SetIDINTEN_RI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetIDINTEN_RI() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetIDINTEN_FBE(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetIDINTEN_FBE() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetIDINTEN_DU(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x10)|value<<4) +} +func (o *SDHOST_Type) GetIDINTEN_DU() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x10) >> 4 +} +func (o *SDHOST_Type) SetIDINTEN_CES(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x20)|value<<5) +} +func (o *SDHOST_Type) GetIDINTEN_CES() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x20) >> 5 +} +func (o *SDHOST_Type) SetIDINTEN_NI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetIDINTEN_NI() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetIDINTEN_AI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetIDINTEN_AI() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x200) >> 9 +} + +// SDHOST.DSCADDR: Host descriptor address pointer +func (o *SDHOST_Type) SetDSCADDR(value uint32) { + volatile.StoreUint32(&o.DSCADDR.Reg, value) +} +func (o *SDHOST_Type) GetDSCADDR() uint32 { + return volatile.LoadUint32(&o.DSCADDR.Reg) +} + +// SDHOST.BUFADDR: Host buffer address pointer register +func (o *SDHOST_Type) SetBUFADDR(value uint32) { + volatile.StoreUint32(&o.BUFADDR.Reg, value) +} +func (o *SDHOST_Type) GetBUFADDR() uint32 { + return volatile.LoadUint32(&o.BUFADDR.Reg) +} + +// SDHOST.CARDTHRCTL: Card Threshold Control register +func (o *SDHOST_Type) SetCARDTHRCTL_CARDRDTHREN(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDRDTHREN() uint32 { + return volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x1 +} +func (o *SDHOST_Type) SetCARDTHRCTL_CARDCLRINTEN(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDCLRINTEN() uint32 { + return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetCARDTHRCTL_CARDWRTHREN(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDWRTHREN() uint32 { + return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetCARDTHRCTL_CARDTHRESHOLD(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0xffff0000)|value<<16) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDTHRESHOLD() uint32 { + return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0xffff0000) >> 16 +} + +// SDHOST.EMMCDDR: eMMC DDR register +func (o *SDHOST_Type) SetEMMCDDR_HALFSTARTBIT(value uint32) { + volatile.StoreUint32(&o.EMMCDDR.Reg, volatile.LoadUint32(&o.EMMCDDR.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetEMMCDDR_HALFSTARTBIT() uint32 { + return volatile.LoadUint32(&o.EMMCDDR.Reg) & 0x3 +} +func (o *SDHOST_Type) SetEMMCDDR_HS400_MODE(value uint32) { + volatile.StoreUint32(&o.EMMCDDR.Reg, volatile.LoadUint32(&o.EMMCDDR.Reg)&^(0x80000000)|value<<31) +} +func (o *SDHOST_Type) GetEMMCDDR_HS400_MODE() uint32 { + return (volatile.LoadUint32(&o.EMMCDDR.Reg) & 0x80000000) >> 31 +} + +// SDHOST.ENSHIFT: Enable Phase Shift register +func (o *SDHOST_Type) SetENSHIFT_ENABLE_SHIFT(value uint32) { + volatile.StoreUint32(&o.ENSHIFT.Reg, volatile.LoadUint32(&o.ENSHIFT.Reg)&^(0xf)|value) +} +func (o *SDHOST_Type) GetENSHIFT_ENABLE_SHIFT() uint32 { + return volatile.LoadUint32(&o.ENSHIFT.Reg) & 0xf +} + +// SDHOST.BUFFIFO: CPU write and read transmit data by FIFO +func (o *SDHOST_Type) SetBUFFIFO(value uint32) { + volatile.StoreUint32(&o.BUFFIFO.Reg, value) +} +func (o *SDHOST_Type) GetBUFFIFO() uint32 { + return volatile.LoadUint32(&o.BUFFIFO.Reg) +} + +// SDHOST.CLK_EDGE_SEL: SDIO control register. +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x7)|value) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL() uint32 { + return volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x7 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x38)|value<<3) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x38) >> 3 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1c0)|value<<6) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1c0) >> 6 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_H(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e00)|value<<9) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_H() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e00) >> 9 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_L(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e000)|value<<13) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_L() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e000) >> 13 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_N(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e0000)|value<<17) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_N() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e0000) >> 17 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_ESDIO_MODE(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x200000)|value<<21) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_ESDIO_MODE() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x200000) >> 21 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_ESD_MODE(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x400000)|value<<22) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_ESD_MODE() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x400000) >> 22 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x800000)|value<<23) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x800000) >> 23 +} + +// SENS Peripheral +type SENS_Type struct { + SAR_READ_CTRL volatile.Register32 // 0x0 + SAR_READ_STATUS1 volatile.Register32 // 0x4 + SAR_MEAS_WAIT1 volatile.Register32 // 0x8 + SAR_MEAS_WAIT2 volatile.Register32 // 0xC + SAR_MEAS_CTRL volatile.Register32 // 0x10 + SAR_READ_STATUS2 volatile.Register32 // 0x14 + ULP_CP_SLEEP_CYC0 volatile.Register32 // 0x18 + ULP_CP_SLEEP_CYC1 volatile.Register32 // 0x1C + ULP_CP_SLEEP_CYC2 volatile.Register32 // 0x20 + ULP_CP_SLEEP_CYC3 volatile.Register32 // 0x24 + ULP_CP_SLEEP_CYC4 volatile.Register32 // 0x28 + SAR_START_FORCE volatile.Register32 // 0x2C + SAR_MEM_WR_CTRL volatile.Register32 // 0x30 + SAR_ATTEN1 volatile.Register32 // 0x34 + SAR_ATTEN2 volatile.Register32 // 0x38 + SAR_SLAVE_ADDR1 volatile.Register32 // 0x3C + SAR_SLAVE_ADDR2 volatile.Register32 // 0x40 + SAR_SLAVE_ADDR3 volatile.Register32 // 0x44 + SAR_SLAVE_ADDR4 volatile.Register32 // 0x48 + SAR_TSENS_CTRL volatile.Register32 // 0x4C + SAR_I2C_CTRL volatile.Register32 // 0x50 + SAR_MEAS_START1 volatile.Register32 // 0x54 + SAR_TOUCH_CTRL1 volatile.Register32 // 0x58 + SAR_TOUCH_THRES1 volatile.Register32 // 0x5C + SAR_TOUCH_THRES2 volatile.Register32 // 0x60 + SAR_TOUCH_THRES3 volatile.Register32 // 0x64 + SAR_TOUCH_THRES4 volatile.Register32 // 0x68 + SAR_TOUCH_THRES5 volatile.Register32 // 0x6C + SAR_TOUCH_OUT1 volatile.Register32 // 0x70 + SAR_TOUCH_OUT2 volatile.Register32 // 0x74 + SAR_TOUCH_OUT3 volatile.Register32 // 0x78 + SAR_TOUCH_OUT4 volatile.Register32 // 0x7C + SAR_TOUCH_OUT5 volatile.Register32 // 0x80 + SAR_TOUCH_CTRL2 volatile.Register32 // 0x84 + _ [4]byte + SAR_TOUCH_ENABLE volatile.Register32 // 0x8C + SAR_READ_CTRL2 volatile.Register32 // 0x90 + SAR_MEAS_START2 volatile.Register32 // 0x94 + SAR_DAC_CTRL1 volatile.Register32 // 0x98 + SAR_DAC_CTRL2 volatile.Register32 // 0x9C + SAR_MEAS_CTRL2 volatile.Register32 // 0xA0 + _ [84]byte + SAR_NOUSE volatile.Register32 // 0xF8 + SARDATE volatile.Register32 // 0xFC +} + +// SENS.SAR_READ_CTRL +func (o *SENS_Type) SetSAR_READ_CTRL_SAR1_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_READ_CTRL_SAR1_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.SAR_READ_CTRL.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_READ_CTRL_SAR1_SAMPLE_CYCLE(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *SENS_Type) GetSAR_READ_CTRL_SAR1_SAMPLE_CYCLE() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL.Reg) & 0xff00) >> 8 +} +func (o *SENS_Type) SetSAR_READ_CTRL_SAR1_SAMPLE_BIT(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL.Reg)&^(0x30000)|value<<16) +} +func (o *SENS_Type) GetSAR_READ_CTRL_SAR1_SAMPLE_BIT() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL.Reg) & 0x30000) >> 16 +} +func (o *SENS_Type) SetSAR_READ_CTRL_SAR1_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_READ_CTRL_SAR1_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_READ_CTRL_SAR1_SAMPLE_NUM(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL.Reg)&^(0x7f80000)|value<<19) +} +func (o *SENS_Type) GetSAR_READ_CTRL_SAR1_SAMPLE_NUM() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL.Reg) & 0x7f80000) >> 19 +} +func (o *SENS_Type) SetSAR_READ_CTRL_SAR1_DIG_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *SENS_Type) GetSAR_READ_CTRL_SAR1_DIG_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *SENS_Type) SetSAR_READ_CTRL_SAR1_DATA_INV(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_READ_CTRL_SAR1_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL.Reg) & 0x10000000) >> 28 +} + +// SENS.SAR_READ_STATUS1 +func (o *SENS_Type) SetSAR_READ_STATUS1(value uint32) { + volatile.StoreUint32(&o.SAR_READ_STATUS1.Reg, value) +} +func (o *SENS_Type) GetSAR_READ_STATUS1() uint32 { + return volatile.LoadUint32(&o.SAR_READ_STATUS1.Reg) +} + +// SENS.SAR_MEAS_WAIT1 +func (o *SENS_Type) SetSAR_MEAS_WAIT1_SAR_AMP_WAIT1(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_WAIT1.Reg, volatile.LoadUint32(&o.SAR_MEAS_WAIT1.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_MEAS_WAIT1_SAR_AMP_WAIT1() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS_WAIT1.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_MEAS_WAIT1_SAR_AMP_WAIT2(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_WAIT1.Reg, volatile.LoadUint32(&o.SAR_MEAS_WAIT1.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS_WAIT1_SAR_AMP_WAIT2() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_WAIT1.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_MEAS_WAIT2 +func (o *SENS_Type) SetSAR_MEAS_WAIT2_FORCE_XPD_SAR_SW(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_WAIT2.Reg, volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_MEAS_WAIT2_FORCE_XPD_SAR_SW() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_MEAS_WAIT2_SAR_AMP_WAIT3(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_WAIT2.Reg, volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_MEAS_WAIT2_SAR_AMP_WAIT3() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_MEAS_WAIT2_FORCE_XPD_AMP(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_WAIT2.Reg, volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg)&^(0x30000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS_WAIT2_FORCE_XPD_AMP() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg) & 0x30000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS_WAIT2_FORCE_XPD_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_WAIT2.Reg, volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg)&^(0xc0000)|value<<18) +} +func (o *SENS_Type) GetSAR_MEAS_WAIT2_FORCE_XPD_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg) & 0xc0000) >> 18 +} +func (o *SENS_Type) SetSAR_MEAS_WAIT2_SAR2_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_WAIT2.Reg, volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg)&^(0xff00000)|value<<20) +} +func (o *SENS_Type) GetSAR_MEAS_WAIT2_SAR2_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_WAIT2.Reg) & 0xff00000) >> 20 +} + +// SENS.SAR_MEAS_CTRL +func (o *SENS_Type) SetSAR_MEAS_CTRL_XPD_SAR_AMP_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg)&^(0xf)|value) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL_XPD_SAR_AMP_FSM() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg) & 0xf +} +func (o *SENS_Type) SetSAR_MEAS_CTRL_AMP_RST_FB_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg)&^(0xf0)|value<<4) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL_AMP_RST_FB_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg) & 0xf0) >> 4 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL_AMP_SHORT_REF_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg)&^(0xf00)|value<<8) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL_AMP_SHORT_REF_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg) & 0xf00) >> 8 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL_AMP_SHORT_REF_GND_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg)&^(0xf000)|value<<12) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL_AMP_SHORT_REF_GND_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg) & 0xf000) >> 12 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL_XPD_SAR_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL_XPD_SAR_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg) & 0xf0000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL_SAR_RSTB_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg)&^(0xf00000)|value<<20) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL_SAR_RSTB_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg) & 0xf00000) >> 20 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL_SAR2_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg)&^(0xff000000)|value<<24) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL_SAR2_XPD_WAIT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL.Reg) & 0xff000000) >> 24 +} + +// SENS.SAR_READ_STATUS2 +func (o *SENS_Type) SetSAR_READ_STATUS2(value uint32) { + volatile.StoreUint32(&o.SAR_READ_STATUS2.Reg, value) +} +func (o *SENS_Type) GetSAR_READ_STATUS2() uint32 { + return volatile.LoadUint32(&o.SAR_READ_STATUS2.Reg) +} + +// SENS.ULP_CP_SLEEP_CYC0 +func (o *SENS_Type) SetULP_CP_SLEEP_CYC0(value uint32) { + volatile.StoreUint32(&o.ULP_CP_SLEEP_CYC0.Reg, value) +} +func (o *SENS_Type) GetULP_CP_SLEEP_CYC0() uint32 { + return volatile.LoadUint32(&o.ULP_CP_SLEEP_CYC0.Reg) +} + +// SENS.ULP_CP_SLEEP_CYC1 +func (o *SENS_Type) SetULP_CP_SLEEP_CYC1(value uint32) { + volatile.StoreUint32(&o.ULP_CP_SLEEP_CYC1.Reg, value) +} +func (o *SENS_Type) GetULP_CP_SLEEP_CYC1() uint32 { + return volatile.LoadUint32(&o.ULP_CP_SLEEP_CYC1.Reg) +} + +// SENS.ULP_CP_SLEEP_CYC2 +func (o *SENS_Type) SetULP_CP_SLEEP_CYC2(value uint32) { + volatile.StoreUint32(&o.ULP_CP_SLEEP_CYC2.Reg, value) +} +func (o *SENS_Type) GetULP_CP_SLEEP_CYC2() uint32 { + return volatile.LoadUint32(&o.ULP_CP_SLEEP_CYC2.Reg) +} + +// SENS.ULP_CP_SLEEP_CYC3 +func (o *SENS_Type) SetULP_CP_SLEEP_CYC3(value uint32) { + volatile.StoreUint32(&o.ULP_CP_SLEEP_CYC3.Reg, value) +} +func (o *SENS_Type) GetULP_CP_SLEEP_CYC3() uint32 { + return volatile.LoadUint32(&o.ULP_CP_SLEEP_CYC3.Reg) +} + +// SENS.ULP_CP_SLEEP_CYC4 +func (o *SENS_Type) SetULP_CP_SLEEP_CYC4(value uint32) { + volatile.StoreUint32(&o.ULP_CP_SLEEP_CYC4.Reg, value) +} +func (o *SENS_Type) GetULP_CP_SLEEP_CYC4() uint32 { + return volatile.LoadUint32(&o.ULP_CP_SLEEP_CYC4.Reg) +} + +// SENS.SAR_START_FORCE +func (o *SENS_Type) SetSAR_START_FORCE_SAR1_BIT_WIDTH(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0x3)|value) +} +func (o *SENS_Type) GetSAR_START_FORCE_SAR1_BIT_WIDTH() uint32 { + return volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0x3 +} +func (o *SENS_Type) SetSAR_START_FORCE_SAR2_BIT_WIDTH(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0xc)|value<<2) +} +func (o *SENS_Type) GetSAR_START_FORCE_SAR2_BIT_WIDTH() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0xc) >> 2 +} +func (o *SENS_Type) SetSAR_START_FORCE_SAR2_EN_TEST(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_START_FORCE_SAR2_EN_TEST() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_START_FORCE_SAR2_PWDET_CCT(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0xe0)|value<<5) +} +func (o *SENS_Type) GetSAR_START_FORCE_SAR2_PWDET_CCT() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0xe0) >> 5 +} +func (o *SENS_Type) SetSAR_START_FORCE_ULP_CP_FORCE_START_TOP(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_START_FORCE_ULP_CP_FORCE_START_TOP() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_START_FORCE_ULP_CP_START_TOP(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_START_FORCE_ULP_CP_START_TOP() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_START_FORCE_SARCLK_EN(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_START_FORCE_SARCLK_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_START_FORCE_PC_INIT(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_START_FORCE_PC_INIT() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0x3ff800) >> 11 +} +func (o *SENS_Type) SetSAR_START_FORCE_SAR2_STOP(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0x400000)|value<<22) +} +func (o *SENS_Type) GetSAR_START_FORCE_SAR2_STOP() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0x400000) >> 22 +} +func (o *SENS_Type) SetSAR_START_FORCE_SAR1_STOP(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0x800000)|value<<23) +} +func (o *SENS_Type) GetSAR_START_FORCE_SAR1_STOP() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0x800000) >> 23 +} +func (o *SENS_Type) SetSAR_START_FORCE_SAR2_PWDET_EN(value uint32) { + volatile.StoreUint32(&o.SAR_START_FORCE.Reg, volatile.LoadUint32(&o.SAR_START_FORCE.Reg)&^(0x1000000)|value<<24) +} +func (o *SENS_Type) GetSAR_START_FORCE_SAR2_PWDET_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_START_FORCE.Reg) & 0x1000000) >> 24 +} + +// SENS.SAR_MEM_WR_CTRL +func (o *SENS_Type) SetSAR_MEM_WR_CTRL_MEM_WR_ADDR_INIT(value uint32) { + volatile.StoreUint32(&o.SAR_MEM_WR_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEM_WR_CTRL.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_MEM_WR_CTRL_MEM_WR_ADDR_INIT() uint32 { + return volatile.LoadUint32(&o.SAR_MEM_WR_CTRL.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_MEM_WR_CTRL_MEM_WR_ADDR_SIZE(value uint32) { + volatile.StoreUint32(&o.SAR_MEM_WR_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEM_WR_CTRL.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_MEM_WR_CTRL_MEM_WR_ADDR_SIZE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEM_WR_CTRL.Reg) & 0x3ff800) >> 11 +} +func (o *SENS_Type) SetSAR_MEM_WR_CTRL_RTC_MEM_WR_OFFST_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_MEM_WR_CTRL.Reg, volatile.LoadUint32(&o.SAR_MEM_WR_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SENS_Type) GetSAR_MEM_WR_CTRL_RTC_MEM_WR_OFFST_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEM_WR_CTRL.Reg) & 0x400000) >> 22 +} + +// SENS.SAR_ATTEN1 +func (o *SENS_Type) SetSAR_ATTEN1(value uint32) { + volatile.StoreUint32(&o.SAR_ATTEN1.Reg, value) +} +func (o *SENS_Type) GetSAR_ATTEN1() uint32 { + return volatile.LoadUint32(&o.SAR_ATTEN1.Reg) +} + +// SENS.SAR_ATTEN2 +func (o *SENS_Type) SetSAR_ATTEN2(value uint32) { + volatile.StoreUint32(&o.SAR_ATTEN2.Reg, value) +} +func (o *SENS_Type) GetSAR_ATTEN2() uint32 { + return volatile.LoadUint32(&o.SAR_ATTEN2.Reg) +} + +// SENS.SAR_SLAVE_ADDR1 +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3ff800) >> 11 +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_MEAS_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3fc00000)|value<<22) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_MEAS_STATUS() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3fc00000) >> 22 +} + +// SENS.SAR_SLAVE_ADDR2 +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_SLAVE_ADDR3 +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x3ff800) >> 11 +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_TSENS_OUT(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x3fc00000)|value<<22) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_TSENS_OUT() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x3fc00000) >> 22 +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_TSENS_RDY_OUT(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_TSENS_RDY_OUT() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x40000000) >> 30 +} + +// SENS.SAR_SLAVE_ADDR4 +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x3ff800) >> 11 +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_I2C_RDATA(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x3fc00000)|value<<22) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_I2C_RDATA() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x3fc00000) >> 22 +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_I2C_DONE(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_I2C_DONE() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x40000000) >> 30 +} + +// SENS.SAR_TSENS_CTRL +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0xfff)|value) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0xfff +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x1000) >> 12 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_CLK_INV(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x2000) >> 13 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_IN_INV(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_IN_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x8000) >> 15 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_POWER_UP(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_POWER_UP() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_POWER_UP_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_POWER_UP_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_DUMP_OUT(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_DUMP_OUT() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x4000000) >> 26 +} + +// SENS.SAR_I2C_CTRL +func (o *SENS_Type) SetSAR_I2C_CTRL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0xfffffff)|value) +} +func (o *SENS_Type) GetSAR_I2C_CTRL() uint32 { + return volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0xfffffff +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x20000000) >> 29 +} + +// SENS.SAR_MEAS_START1 +func (o *SENS_Type) SetSAR_MEAS_START1_MEAS1_DATA_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START1.Reg, volatile.LoadUint32(&o.SAR_MEAS_START1.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_MEAS_START1_MEAS1_DATA_SAR() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS_START1.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_MEAS_START1_MEAS1_DONE_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START1.Reg, volatile.LoadUint32(&o.SAR_MEAS_START1.Reg)&^(0x10000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS_START1_MEAS1_DONE_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START1.Reg) & 0x10000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS_START1_MEAS1_START_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START1.Reg, volatile.LoadUint32(&o.SAR_MEAS_START1.Reg)&^(0x20000)|value<<17) +} +func (o *SENS_Type) GetSAR_MEAS_START1_MEAS1_START_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START1.Reg) & 0x20000) >> 17 +} +func (o *SENS_Type) SetSAR_MEAS_START1_MEAS1_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START1.Reg, volatile.LoadUint32(&o.SAR_MEAS_START1.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_MEAS_START1_MEAS1_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START1.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_MEAS_START1_SAR1_EN_PAD(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START1.Reg, volatile.LoadUint32(&o.SAR_MEAS_START1.Reg)&^(0x7ff80000)|value<<19) +} +func (o *SENS_Type) GetSAR_MEAS_START1_SAR1_EN_PAD() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START1.Reg) & 0x7ff80000) >> 19 +} +func (o *SENS_Type) SetSAR_MEAS_START1_SAR1_EN_PAD_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START1.Reg, volatile.LoadUint32(&o.SAR_MEAS_START1.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS_START1_SAR1_EN_PAD_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START1.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_TOUCH_CTRL1 +func (o *SENS_Type) SetSAR_TOUCH_CTRL1_TOUCH_MEAS_DELAY(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL1_TOUCH_MEAS_DELAY() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL1_TOUCH_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg)&^(0xff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL1_TOUCH_XPD_WAIT() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg) & 0xff0000) >> 16 +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL1_TOUCH_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL1_TOUCH_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL1_TOUCH_OUT_1EN(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL1_TOUCH_OUT_1EN() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg) & 0x2000000) >> 25 +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL1_XPD_HALL_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg)&^(0x4000000)|value<<26) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL1_XPD_HALL_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg) & 0x4000000) >> 26 +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL1_HALL_PHASE_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg)&^(0x8000000)|value<<27) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL1_HALL_PHASE_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL1.Reg) & 0x8000000) >> 27 +} + +// SENS.SAR_TOUCH_THRES1 +func (o *SENS_Type) SetSAR_TOUCH_THRES1_TOUCH_OUT_TH1(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES1.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES1_TOUCH_OUT_TH1() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES1.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_THRES1_TOUCH_OUT_TH0(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES1.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES1_TOUCH_OUT_TH0() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_THRES1.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_THRES2 +func (o *SENS_Type) SetSAR_TOUCH_THRES2_TOUCH_OUT_TH3(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES2.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES2_TOUCH_OUT_TH3() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES2.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_THRES2_TOUCH_OUT_TH2(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES2.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES2_TOUCH_OUT_TH2() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_THRES2.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_THRES3 +func (o *SENS_Type) SetSAR_TOUCH_THRES3_TOUCH_OUT_TH5(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES3.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES3_TOUCH_OUT_TH5() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES3.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_THRES3_TOUCH_OUT_TH4(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES3.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES3_TOUCH_OUT_TH4() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_THRES3.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_THRES4 +func (o *SENS_Type) SetSAR_TOUCH_THRES4_TOUCH_OUT_TH7(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES4.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES4_TOUCH_OUT_TH7() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES4.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_THRES4_TOUCH_OUT_TH6(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES4.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES4_TOUCH_OUT_TH6() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_THRES4.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_THRES5 +func (o *SENS_Type) SetSAR_TOUCH_THRES5_TOUCH_OUT_TH9(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES5.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES5_TOUCH_OUT_TH9() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES5.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_THRES5_TOUCH_OUT_TH8(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES5.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES5_TOUCH_OUT_TH8() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_THRES5.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_OUT1 +func (o *SENS_Type) SetSAR_TOUCH_OUT1_TOUCH_MEAS_OUT1(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT1.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT1_TOUCH_MEAS_OUT1() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_OUT1.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_OUT1_TOUCH_MEAS_OUT0(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT1.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT1_TOUCH_MEAS_OUT0() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_OUT1.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_OUT2 +func (o *SENS_Type) SetSAR_TOUCH_OUT2_TOUCH_MEAS_OUT3(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT2.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT2_TOUCH_MEAS_OUT3() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_OUT2.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_OUT2_TOUCH_MEAS_OUT2(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT2.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT2_TOUCH_MEAS_OUT2() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_OUT2.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_OUT3 +func (o *SENS_Type) SetSAR_TOUCH_OUT3_TOUCH_MEAS_OUT5(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT3.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT3_TOUCH_MEAS_OUT5() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_OUT3.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_OUT3_TOUCH_MEAS_OUT4(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT3.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT3_TOUCH_MEAS_OUT4() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_OUT3.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_OUT4 +func (o *SENS_Type) SetSAR_TOUCH_OUT4_TOUCH_MEAS_OUT7(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT4.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT4_TOUCH_MEAS_OUT7() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_OUT4.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_OUT4_TOUCH_MEAS_OUT6(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT4.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT4_TOUCH_MEAS_OUT6() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_OUT4.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_OUT5 +func (o *SENS_Type) SetSAR_TOUCH_OUT5_TOUCH_MEAS_OUT9(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT5.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT5_TOUCH_MEAS_OUT9() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_OUT5.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_TOUCH_OUT5_TOUCH_MEAS_OUT8(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_OUT5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_OUT5.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_OUT5_TOUCH_MEAS_OUT8() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_OUT5.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_TOUCH_CTRL2 +func (o *SENS_Type) SetSAR_TOUCH_CTRL2_TOUCH_MEAS_EN(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg)&^(0x3ff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL2_TOUCH_MEAS_EN() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg) & 0x3ff +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL2_TOUCH_MEAS_DONE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL2_TOUCH_MEAS_DONE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL2_TOUCH_START_FSM_EN(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL2_TOUCH_START_FSM_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg) & 0x800) >> 11 +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL2_TOUCH_START_EN(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg)&^(0x1000)|value<<12) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL2_TOUCH_START_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg) & 0x1000) >> 12 +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL2_TOUCH_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg)&^(0x2000)|value<<13) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL2_TOUCH_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg) & 0x2000) >> 13 +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL2_TOUCH_SLEEP_CYCLES(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg)&^(0x3fffc000)|value<<14) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL2_TOUCH_SLEEP_CYCLES() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg) & 0x3fffc000) >> 14 +} +func (o *SENS_Type) SetSAR_TOUCH_CTRL2_TOUCH_MEAS_EN_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_TOUCH_CTRL2_TOUCH_MEAS_EN_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CTRL2.Reg) & 0x40000000) >> 30 +} + +// SENS.SAR_TOUCH_ENABLE +func (o *SENS_Type) SetSAR_TOUCH_ENABLE_TOUCH_PAD_WORKEN(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_ENABLE.Reg, volatile.LoadUint32(&o.SAR_TOUCH_ENABLE.Reg)&^(0x3ff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_ENABLE_TOUCH_PAD_WORKEN() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_ENABLE.Reg) & 0x3ff +} +func (o *SENS_Type) SetSAR_TOUCH_ENABLE_TOUCH_PAD_OUTEN2(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_ENABLE.Reg, volatile.LoadUint32(&o.SAR_TOUCH_ENABLE.Reg)&^(0xffc00)|value<<10) +} +func (o *SENS_Type) GetSAR_TOUCH_ENABLE_TOUCH_PAD_OUTEN2() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_ENABLE.Reg) & 0xffc00) >> 10 +} +func (o *SENS_Type) SetSAR_TOUCH_ENABLE_TOUCH_PAD_OUTEN1(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_ENABLE.Reg, volatile.LoadUint32(&o.SAR_TOUCH_ENABLE.Reg)&^(0x3ff00000)|value<<20) +} +func (o *SENS_Type) GetSAR_TOUCH_ENABLE_TOUCH_PAD_OUTEN1() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_ENABLE.Reg) & 0x3ff00000) >> 20 +} + +// SENS.SAR_READ_CTRL2 +func (o *SENS_Type) SetSAR_READ_CTRL2_SAR2_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL2.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_READ_CTRL2_SAR2_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_READ_CTRL2_SAR2_SAMPLE_CYCLE(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL2.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg)&^(0xff00)|value<<8) +} +func (o *SENS_Type) GetSAR_READ_CTRL2_SAR2_SAMPLE_CYCLE() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg) & 0xff00) >> 8 +} +func (o *SENS_Type) SetSAR_READ_CTRL2_SAR2_SAMPLE_BIT(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL2.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg)&^(0x30000)|value<<16) +} +func (o *SENS_Type) GetSAR_READ_CTRL2_SAR2_SAMPLE_BIT() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg) & 0x30000) >> 16 +} +func (o *SENS_Type) SetSAR_READ_CTRL2_SAR2_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL2.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_READ_CTRL2_SAR2_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_READ_CTRL2_SAR2_SAMPLE_NUM(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL2.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg)&^(0x7f80000)|value<<19) +} +func (o *SENS_Type) GetSAR_READ_CTRL2_SAR2_SAMPLE_NUM() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg) & 0x7f80000) >> 19 +} +func (o *SENS_Type) SetSAR_READ_CTRL2_SAR2_PWDET_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL2.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg)&^(0x8000000)|value<<27) +} +func (o *SENS_Type) GetSAR_READ_CTRL2_SAR2_PWDET_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg) & 0x8000000) >> 27 +} +func (o *SENS_Type) SetSAR_READ_CTRL2_SAR2_DIG_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL2.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_READ_CTRL2_SAR2_DIG_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_READ_CTRL2_SAR2_DATA_INV(value uint32) { + volatile.StoreUint32(&o.SAR_READ_CTRL2.Reg, volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_READ_CTRL2_SAR2_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_READ_CTRL2.Reg) & 0x20000000) >> 29 +} + +// SENS.SAR_MEAS_START2 +func (o *SENS_Type) SetSAR_MEAS_START2_MEAS2_DATA_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START2.Reg, volatile.LoadUint32(&o.SAR_MEAS_START2.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_MEAS_START2_MEAS2_DATA_SAR() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS_START2.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_MEAS_START2_MEAS2_DONE_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START2.Reg, volatile.LoadUint32(&o.SAR_MEAS_START2.Reg)&^(0x10000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS_START2_MEAS2_DONE_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START2.Reg) & 0x10000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS_START2_MEAS2_START_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START2.Reg, volatile.LoadUint32(&o.SAR_MEAS_START2.Reg)&^(0x20000)|value<<17) +} +func (o *SENS_Type) GetSAR_MEAS_START2_MEAS2_START_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START2.Reg) & 0x20000) >> 17 +} +func (o *SENS_Type) SetSAR_MEAS_START2_MEAS2_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START2.Reg, volatile.LoadUint32(&o.SAR_MEAS_START2.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_MEAS_START2_MEAS2_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START2.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_MEAS_START2_SAR2_EN_PAD(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START2.Reg, volatile.LoadUint32(&o.SAR_MEAS_START2.Reg)&^(0x7ff80000)|value<<19) +} +func (o *SENS_Type) GetSAR_MEAS_START2_SAR2_EN_PAD() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START2.Reg) & 0x7ff80000) >> 19 +} +func (o *SENS_Type) SetSAR_MEAS_START2_SAR2_EN_PAD_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_START2.Reg, volatile.LoadUint32(&o.SAR_MEAS_START2.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS_START2_SAR2_EN_PAD_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_START2.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_DAC_CTRL1 +func (o *SENS_Type) SetSAR_DAC_CTRL1_SW_FSTEP(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_SW_FSTEP() uint32 { + return volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_SW_TONE_EN(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x10000)|value<<16) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_SW_TONE_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x10000) >> 16 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x3e0000)|value<<17) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DEBUG_BIT_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x3e0000) >> 17 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_DIG_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x400000)|value<<22) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_DIG_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x400000) >> 22 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_CLK_FORCE_LOW(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x800000)|value<<23) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_CLK_FORCE_LOW() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x800000) >> 23 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_CLK_INV(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x2000000) >> 25 +} + +// SENS.SAR_DAC_CTRL2 +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_DC1(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_DC1() uint32 { + return volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_DC2(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0xff00)|value<<8) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_DC2() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0xff00) >> 8 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_SCALE1(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0x30000)|value<<16) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_SCALE1() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0x30000) >> 16 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_SCALE2(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0xc0000)|value<<18) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_SCALE2() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0xc0000) >> 18 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_INV1(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0x300000)|value<<20) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_INV1() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0x300000) >> 20 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_INV2(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0xc00000)|value<<22) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_INV2() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0xc00000) >> 22 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_CW_EN1(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_CW_EN1() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0x1000000) >> 24 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_CW_EN2(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0x2000000)|value<<25) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_CW_EN2() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0x2000000) >> 25 +} + +// SENS.SAR_MEAS_CTRL2 +func (o *SENS_Type) SetSAR_MEAS_CTRL2_SAR1_DAC_XPD_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0xf)|value) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_SAR1_DAC_XPD_FSM() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0xf +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_SAR1_DAC_XPD_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_SAR1_DAC_XPD_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_XPD_SAR_AMP_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_XPD_SAR_AMP_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_AMP_RST_FB_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_AMP_RST_FB_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_AMP_SHORT_REF_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_AMP_SHORT_REF_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_XPD_SAR_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_XPD_SAR_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_SAR_RSTB_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_SAR_RSTB_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_SAR2_RSTB_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x1800)|value<<11) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_SAR2_RSTB_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x1800) >> 11 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_AMP_RST_FB_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x6000)|value<<13) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_AMP_RST_FB_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x6000) >> 13 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_AMP_SHORT_REF_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x18000)|value<<15) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_AMP_SHORT_REF_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x18000) >> 15 +} +func (o *SENS_Type) SetSAR_MEAS_CTRL2_AMP_SHORT_REF_GND_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg)&^(0x60000)|value<<17) +} +func (o *SENS_Type) GetSAR_MEAS_CTRL2_AMP_SHORT_REF_GND_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS_CTRL2.Reg) & 0x60000) >> 17 +} + +// SENS.SAR_NOUSE +func (o *SENS_Type) SetSAR_NOUSE(value uint32) { + volatile.StoreUint32(&o.SAR_NOUSE.Reg, value) +} +func (o *SENS_Type) GetSAR_NOUSE() uint32 { + return volatile.LoadUint32(&o.SAR_NOUSE.Reg) +} + +// SENS.SARDATE +func (o *SENS_Type) SetSARDATE_SAR_DATE(value uint32) { + volatile.StoreUint32(&o.SARDATE.Reg, volatile.LoadUint32(&o.SARDATE.Reg)&^(0xfffffff)|value) +} +func (o *SENS_Type) GetSARDATE_SAR_DATE() uint32 { + return volatile.LoadUint32(&o.SARDATE.Reg) & 0xfffffff +} + +// SHA (Secure Hash Algorithm) Accelerator +type SHA_Type struct { + TEXT0 volatile.Register32 // 0x0 + TEXT1 volatile.Register32 // 0x4 + TEXT2 volatile.Register32 // 0x8 + TEXT3 volatile.Register32 // 0xC + TEXT4 volatile.Register32 // 0x10 + TEXT5 volatile.Register32 // 0x14 + TEXT6 volatile.Register32 // 0x18 + TEXT7 volatile.Register32 // 0x1C + TEXT8 volatile.Register32 // 0x20 + TEXT9 volatile.Register32 // 0x24 + TEXT10 volatile.Register32 // 0x28 + TEXT11 volatile.Register32 // 0x2C + TEXT12 volatile.Register32 // 0x30 + TEXT13 volatile.Register32 // 0x34 + TEXT14 volatile.Register32 // 0x38 + TEXT15 volatile.Register32 // 0x3C + TEXT16 volatile.Register32 // 0x40 + TEXT17 volatile.Register32 // 0x44 + TEXT18 volatile.Register32 // 0x48 + TEXT19 volatile.Register32 // 0x4C + TEXT20 volatile.Register32 // 0x50 + TEXT21 volatile.Register32 // 0x54 + TEXT22 volatile.Register32 // 0x58 + TEXT23 volatile.Register32 // 0x5C + TEXT24 volatile.Register32 // 0x60 + TEXT25 volatile.Register32 // 0x64 + TEXT26 volatile.Register32 // 0x68 + TEXT27 volatile.Register32 // 0x6C + TEXT28 volatile.Register32 // 0x70 + TEXT29 volatile.Register32 // 0x74 + TEXT30 volatile.Register32 // 0x78 + TEXT31 volatile.Register32 // 0x7C + SHA1_START volatile.Register32 // 0x80 + SHA1_CONTINUE volatile.Register32 // 0x84 + SHA1_LOAD volatile.Register32 // 0x88 + SHA1_BUSY volatile.Register32 // 0x8C + SHA256_START volatile.Register32 // 0x90 + SHA256_CONTINUE volatile.Register32 // 0x94 + SHA256_LOAD volatile.Register32 // 0x98 + SHA256_BUSY volatile.Register32 // 0x9C + SHA384_START volatile.Register32 // 0xA0 + SHA384_CONTINUE volatile.Register32 // 0xA4 + SHA384_LOAD volatile.Register32 // 0xA8 + SHA384_BUSY volatile.Register32 // 0xAC + SHA512_START volatile.Register32 // 0xB0 + SHA512_CONTINUE volatile.Register32 // 0xB4 + SHA512_LOAD volatile.Register32 // 0xB8 + SHA512_BUSY volatile.Register32 // 0xBC +} + +// SHA.TEXT0 +func (o *SHA_Type) SetTEXT0(value uint32) { + volatile.StoreUint32(&o.TEXT0.Reg, value) +} +func (o *SHA_Type) GetTEXT0() uint32 { + return volatile.LoadUint32(&o.TEXT0.Reg) +} + +// SHA.TEXT1 +func (o *SHA_Type) SetTEXT1(value uint32) { + volatile.StoreUint32(&o.TEXT1.Reg, value) +} +func (o *SHA_Type) GetTEXT1() uint32 { + return volatile.LoadUint32(&o.TEXT1.Reg) +} + +// SHA.TEXT2 +func (o *SHA_Type) SetTEXT2(value uint32) { + volatile.StoreUint32(&o.TEXT2.Reg, value) +} +func (o *SHA_Type) GetTEXT2() uint32 { + return volatile.LoadUint32(&o.TEXT2.Reg) +} + +// SHA.TEXT3 +func (o *SHA_Type) SetTEXT3(value uint32) { + volatile.StoreUint32(&o.TEXT3.Reg, value) +} +func (o *SHA_Type) GetTEXT3() uint32 { + return volatile.LoadUint32(&o.TEXT3.Reg) +} + +// SHA.TEXT4 +func (o *SHA_Type) SetTEXT4(value uint32) { + volatile.StoreUint32(&o.TEXT4.Reg, value) +} +func (o *SHA_Type) GetTEXT4() uint32 { + return volatile.LoadUint32(&o.TEXT4.Reg) +} + +// SHA.TEXT5 +func (o *SHA_Type) SetTEXT5(value uint32) { + volatile.StoreUint32(&o.TEXT5.Reg, value) +} +func (o *SHA_Type) GetTEXT5() uint32 { + return volatile.LoadUint32(&o.TEXT5.Reg) +} + +// SHA.TEXT6 +func (o *SHA_Type) SetTEXT6(value uint32) { + volatile.StoreUint32(&o.TEXT6.Reg, value) +} +func (o *SHA_Type) GetTEXT6() uint32 { + return volatile.LoadUint32(&o.TEXT6.Reg) +} + +// SHA.TEXT7 +func (o *SHA_Type) SetTEXT7(value uint32) { + volatile.StoreUint32(&o.TEXT7.Reg, value) +} +func (o *SHA_Type) GetTEXT7() uint32 { + return volatile.LoadUint32(&o.TEXT7.Reg) +} + +// SHA.TEXT8 +func (o *SHA_Type) SetTEXT8(value uint32) { + volatile.StoreUint32(&o.TEXT8.Reg, value) +} +func (o *SHA_Type) GetTEXT8() uint32 { + return volatile.LoadUint32(&o.TEXT8.Reg) +} + +// SHA.TEXT9 +func (o *SHA_Type) SetTEXT9(value uint32) { + volatile.StoreUint32(&o.TEXT9.Reg, value) +} +func (o *SHA_Type) GetTEXT9() uint32 { + return volatile.LoadUint32(&o.TEXT9.Reg) +} + +// SHA.TEXT10 +func (o *SHA_Type) SetTEXT10(value uint32) { + volatile.StoreUint32(&o.TEXT10.Reg, value) +} +func (o *SHA_Type) GetTEXT10() uint32 { + return volatile.LoadUint32(&o.TEXT10.Reg) +} + +// SHA.TEXT11 +func (o *SHA_Type) SetTEXT11(value uint32) { + volatile.StoreUint32(&o.TEXT11.Reg, value) +} +func (o *SHA_Type) GetTEXT11() uint32 { + return volatile.LoadUint32(&o.TEXT11.Reg) +} + +// SHA.TEXT12 +func (o *SHA_Type) SetTEXT12(value uint32) { + volatile.StoreUint32(&o.TEXT12.Reg, value) +} +func (o *SHA_Type) GetTEXT12() uint32 { + return volatile.LoadUint32(&o.TEXT12.Reg) +} + +// SHA.TEXT13 +func (o *SHA_Type) SetTEXT13(value uint32) { + volatile.StoreUint32(&o.TEXT13.Reg, value) +} +func (o *SHA_Type) GetTEXT13() uint32 { + return volatile.LoadUint32(&o.TEXT13.Reg) +} + +// SHA.TEXT14 +func (o *SHA_Type) SetTEXT14(value uint32) { + volatile.StoreUint32(&o.TEXT14.Reg, value) +} +func (o *SHA_Type) GetTEXT14() uint32 { + return volatile.LoadUint32(&o.TEXT14.Reg) +} + +// SHA.TEXT15 +func (o *SHA_Type) SetTEXT15(value uint32) { + volatile.StoreUint32(&o.TEXT15.Reg, value) +} +func (o *SHA_Type) GetTEXT15() uint32 { + return volatile.LoadUint32(&o.TEXT15.Reg) +} + +// SHA.TEXT16 +func (o *SHA_Type) SetTEXT16(value uint32) { + volatile.StoreUint32(&o.TEXT16.Reg, value) +} +func (o *SHA_Type) GetTEXT16() uint32 { + return volatile.LoadUint32(&o.TEXT16.Reg) +} + +// SHA.TEXT17 +func (o *SHA_Type) SetTEXT17(value uint32) { + volatile.StoreUint32(&o.TEXT17.Reg, value) +} +func (o *SHA_Type) GetTEXT17() uint32 { + return volatile.LoadUint32(&o.TEXT17.Reg) +} + +// SHA.TEXT18 +func (o *SHA_Type) SetTEXT18(value uint32) { + volatile.StoreUint32(&o.TEXT18.Reg, value) +} +func (o *SHA_Type) GetTEXT18() uint32 { + return volatile.LoadUint32(&o.TEXT18.Reg) +} + +// SHA.TEXT19 +func (o *SHA_Type) SetTEXT19(value uint32) { + volatile.StoreUint32(&o.TEXT19.Reg, value) +} +func (o *SHA_Type) GetTEXT19() uint32 { + return volatile.LoadUint32(&o.TEXT19.Reg) +} + +// SHA.TEXT20 +func (o *SHA_Type) SetTEXT20(value uint32) { + volatile.StoreUint32(&o.TEXT20.Reg, value) +} +func (o *SHA_Type) GetTEXT20() uint32 { + return volatile.LoadUint32(&o.TEXT20.Reg) +} + +// SHA.TEXT21 +func (o *SHA_Type) SetTEXT21(value uint32) { + volatile.StoreUint32(&o.TEXT21.Reg, value) +} +func (o *SHA_Type) GetTEXT21() uint32 { + return volatile.LoadUint32(&o.TEXT21.Reg) +} + +// SHA.TEXT22 +func (o *SHA_Type) SetTEXT22(value uint32) { + volatile.StoreUint32(&o.TEXT22.Reg, value) +} +func (o *SHA_Type) GetTEXT22() uint32 { + return volatile.LoadUint32(&o.TEXT22.Reg) +} + +// SHA.TEXT23 +func (o *SHA_Type) SetTEXT23(value uint32) { + volatile.StoreUint32(&o.TEXT23.Reg, value) +} +func (o *SHA_Type) GetTEXT23() uint32 { + return volatile.LoadUint32(&o.TEXT23.Reg) +} + +// SHA.TEXT24 +func (o *SHA_Type) SetTEXT24(value uint32) { + volatile.StoreUint32(&o.TEXT24.Reg, value) +} +func (o *SHA_Type) GetTEXT24() uint32 { + return volatile.LoadUint32(&o.TEXT24.Reg) +} + +// SHA.TEXT25 +func (o *SHA_Type) SetTEXT25(value uint32) { + volatile.StoreUint32(&o.TEXT25.Reg, value) +} +func (o *SHA_Type) GetTEXT25() uint32 { + return volatile.LoadUint32(&o.TEXT25.Reg) +} + +// SHA.TEXT26 +func (o *SHA_Type) SetTEXT26(value uint32) { + volatile.StoreUint32(&o.TEXT26.Reg, value) +} +func (o *SHA_Type) GetTEXT26() uint32 { + return volatile.LoadUint32(&o.TEXT26.Reg) +} + +// SHA.TEXT27 +func (o *SHA_Type) SetTEXT27(value uint32) { + volatile.StoreUint32(&o.TEXT27.Reg, value) +} +func (o *SHA_Type) GetTEXT27() uint32 { + return volatile.LoadUint32(&o.TEXT27.Reg) +} + +// SHA.TEXT28 +func (o *SHA_Type) SetTEXT28(value uint32) { + volatile.StoreUint32(&o.TEXT28.Reg, value) +} +func (o *SHA_Type) GetTEXT28() uint32 { + return volatile.LoadUint32(&o.TEXT28.Reg) +} + +// SHA.TEXT29 +func (o *SHA_Type) SetTEXT29(value uint32) { + volatile.StoreUint32(&o.TEXT29.Reg, value) +} +func (o *SHA_Type) GetTEXT29() uint32 { + return volatile.LoadUint32(&o.TEXT29.Reg) +} + +// SHA.TEXT30 +func (o *SHA_Type) SetTEXT30(value uint32) { + volatile.StoreUint32(&o.TEXT30.Reg, value) +} +func (o *SHA_Type) GetTEXT30() uint32 { + return volatile.LoadUint32(&o.TEXT30.Reg) +} + +// SHA.TEXT31 +func (o *SHA_Type) SetTEXT31(value uint32) { + volatile.StoreUint32(&o.TEXT31.Reg, value) +} +func (o *SHA_Type) GetTEXT31() uint32 { + return volatile.LoadUint32(&o.TEXT31.Reg) +} + +// SHA.SHA1_START +func (o *SHA_Type) SetSHA1_START(value uint32) { + volatile.StoreUint32(&o.SHA1_START.Reg, volatile.LoadUint32(&o.SHA1_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA1_START() uint32 { + return volatile.LoadUint32(&o.SHA1_START.Reg) & 0x1 +} + +// SHA.SHA1_CONTINUE +func (o *SHA_Type) SetSHA1_CONTINUE(value uint32) { + volatile.StoreUint32(&o.SHA1_CONTINUE.Reg, volatile.LoadUint32(&o.SHA1_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA1_CONTINUE() uint32 { + return volatile.LoadUint32(&o.SHA1_CONTINUE.Reg) & 0x1 +} + +// SHA.SHA1_LOAD +func (o *SHA_Type) SetSHA1_LOAD(value uint32) { + volatile.StoreUint32(&o.SHA1_LOAD.Reg, volatile.LoadUint32(&o.SHA1_LOAD.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA1_LOAD() uint32 { + return volatile.LoadUint32(&o.SHA1_LOAD.Reg) & 0x1 +} + +// SHA.SHA1_BUSY +func (o *SHA_Type) SetSHA1_BUSY(value uint32) { + volatile.StoreUint32(&o.SHA1_BUSY.Reg, volatile.LoadUint32(&o.SHA1_BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA1_BUSY() uint32 { + return volatile.LoadUint32(&o.SHA1_BUSY.Reg) & 0x1 +} + +// SHA.SHA256_START +func (o *SHA_Type) SetSHA256_START(value uint32) { + volatile.StoreUint32(&o.SHA256_START.Reg, volatile.LoadUint32(&o.SHA256_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA256_START() uint32 { + return volatile.LoadUint32(&o.SHA256_START.Reg) & 0x1 +} + +// SHA.SHA256_CONTINUE +func (o *SHA_Type) SetSHA256_CONTINUE(value uint32) { + volatile.StoreUint32(&o.SHA256_CONTINUE.Reg, volatile.LoadUint32(&o.SHA256_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA256_CONTINUE() uint32 { + return volatile.LoadUint32(&o.SHA256_CONTINUE.Reg) & 0x1 +} + +// SHA.SHA256_LOAD +func (o *SHA_Type) SetSHA256_LOAD(value uint32) { + volatile.StoreUint32(&o.SHA256_LOAD.Reg, volatile.LoadUint32(&o.SHA256_LOAD.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA256_LOAD() uint32 { + return volatile.LoadUint32(&o.SHA256_LOAD.Reg) & 0x1 +} + +// SHA.SHA256_BUSY +func (o *SHA_Type) SetSHA256_BUSY(value uint32) { + volatile.StoreUint32(&o.SHA256_BUSY.Reg, volatile.LoadUint32(&o.SHA256_BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA256_BUSY() uint32 { + return volatile.LoadUint32(&o.SHA256_BUSY.Reg) & 0x1 +} + +// SHA.SHA384_START +func (o *SHA_Type) SetSHA384_START(value uint32) { + volatile.StoreUint32(&o.SHA384_START.Reg, volatile.LoadUint32(&o.SHA384_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA384_START() uint32 { + return volatile.LoadUint32(&o.SHA384_START.Reg) & 0x1 +} + +// SHA.SHA384_CONTINUE +func (o *SHA_Type) SetSHA384_CONTINUE(value uint32) { + volatile.StoreUint32(&o.SHA384_CONTINUE.Reg, volatile.LoadUint32(&o.SHA384_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA384_CONTINUE() uint32 { + return volatile.LoadUint32(&o.SHA384_CONTINUE.Reg) & 0x1 +} + +// SHA.SHA384_LOAD +func (o *SHA_Type) SetSHA384_LOAD(value uint32) { + volatile.StoreUint32(&o.SHA384_LOAD.Reg, volatile.LoadUint32(&o.SHA384_LOAD.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA384_LOAD() uint32 { + return volatile.LoadUint32(&o.SHA384_LOAD.Reg) & 0x1 +} + +// SHA.SHA384_BUSY +func (o *SHA_Type) SetSHA384_BUSY(value uint32) { + volatile.StoreUint32(&o.SHA384_BUSY.Reg, volatile.LoadUint32(&o.SHA384_BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA384_BUSY() uint32 { + return volatile.LoadUint32(&o.SHA384_BUSY.Reg) & 0x1 +} + +// SHA.SHA512_START +func (o *SHA_Type) SetSHA512_START(value uint32) { + volatile.StoreUint32(&o.SHA512_START.Reg, volatile.LoadUint32(&o.SHA512_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA512_START() uint32 { + return volatile.LoadUint32(&o.SHA512_START.Reg) & 0x1 +} + +// SHA.SHA512_CONTINUE +func (o *SHA_Type) SetSHA512_CONTINUE(value uint32) { + volatile.StoreUint32(&o.SHA512_CONTINUE.Reg, volatile.LoadUint32(&o.SHA512_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA512_CONTINUE() uint32 { + return volatile.LoadUint32(&o.SHA512_CONTINUE.Reg) & 0x1 +} + +// SHA.SHA512_LOAD +func (o *SHA_Type) SetSHA512_LOAD(value uint32) { + volatile.StoreUint32(&o.SHA512_LOAD.Reg, volatile.LoadUint32(&o.SHA512_LOAD.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA512_LOAD() uint32 { + return volatile.LoadUint32(&o.SHA512_LOAD.Reg) & 0x1 +} + +// SHA.SHA512_BUSY +func (o *SHA_Type) SetSHA512_BUSY(value uint32) { + volatile.StoreUint32(&o.SHA512_BUSY.Reg, volatile.LoadUint32(&o.SHA512_BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSHA512_BUSY() uint32 { + return volatile.LoadUint32(&o.SHA512_BUSY.Reg) & 0x1 +} + +// SLC Peripheral +type SLC_Type struct { + CONF0 volatile.Register32 // 0x0 + _0INT_RAW volatile.Register32 // 0x4 + _0INT_ST volatile.Register32 // 0x8 + _0INT_ENA volatile.Register32 // 0xC + _0INT_CLR volatile.Register32 // 0x10 + _1INT_RAW volatile.Register32 // 0x14 + _1INT_ST volatile.Register32 // 0x18 + _1INT_ENA volatile.Register32 // 0x1C + _1INT_CLR volatile.Register32 // 0x20 + RX_STATUS volatile.Register32 // 0x24 + _0RXFIFO_PUSH volatile.Register32 // 0x28 + _1RXFIFO_PUSH volatile.Register32 // 0x2C + TX_STATUS volatile.Register32 // 0x30 + _0TXFIFO_POP volatile.Register32 // 0x34 + _1TXFIFO_POP volatile.Register32 // 0x38 + _0RX_LINK volatile.Register32 // 0x3C + _0TX_LINK volatile.Register32 // 0x40 + _1RX_LINK volatile.Register32 // 0x44 + _1TX_LINK volatile.Register32 // 0x48 + INTVEC_TOHOST volatile.Register32 // 0x4C + _0TOKEN0 volatile.Register32 // 0x50 + _0TOKEN1 volatile.Register32 // 0x54 + _1TOKEN0 volatile.Register32 // 0x58 + _1TOKEN1 volatile.Register32 // 0x5C + CONF1 volatile.Register32 // 0x60 + _0_STATE0 volatile.Register32 // 0x64 + _0_STATE1 volatile.Register32 // 0x68 + _1_STATE0 volatile.Register32 // 0x6C + _1_STATE1 volatile.Register32 // 0x70 + BRIDGE_CONF volatile.Register32 // 0x74 + _0_TO_EOF_DES_ADDR volatile.Register32 // 0x78 + _0_TX_EOF_DES_ADDR volatile.Register32 // 0x7C + _0_TO_EOF_BFR_DES_ADDR volatile.Register32 // 0x80 + _1_TO_EOF_DES_ADDR volatile.Register32 // 0x84 + _1_TX_EOF_DES_ADDR volatile.Register32 // 0x88 + _1_TO_EOF_BFR_DES_ADDR volatile.Register32 // 0x8C + AHB_TEST volatile.Register32 // 0x90 + SDIO_ST volatile.Register32 // 0x94 + RX_DSCR_CONF volatile.Register32 // 0x98 + _0_TXLINK_DSCR volatile.Register32 // 0x9C + _0_TXLINK_DSCR_BF0 volatile.Register32 // 0xA0 + _0_TXLINK_DSCR_BF1 volatile.Register32 // 0xA4 + _0_RXLINK_DSCR volatile.Register32 // 0xA8 + _0_RXLINK_DSCR_BF0 volatile.Register32 // 0xAC + _0_RXLINK_DSCR_BF1 volatile.Register32 // 0xB0 + _1_TXLINK_DSCR volatile.Register32 // 0xB4 + _1_TXLINK_DSCR_BF0 volatile.Register32 // 0xB8 + _1_TXLINK_DSCR_BF1 volatile.Register32 // 0xBC + _1_RXLINK_DSCR volatile.Register32 // 0xC0 + _1_RXLINK_DSCR_BF0 volatile.Register32 // 0xC4 + _1_RXLINK_DSCR_BF1 volatile.Register32 // 0xC8 + _0_TX_ERREOF_DES_ADDR volatile.Register32 // 0xCC + _1_TX_ERREOF_DES_ADDR volatile.Register32 // 0xD0 + TOKEN_LAT volatile.Register32 // 0xD4 + TX_DSCR_CONF volatile.Register32 // 0xD8 + CMD_INFOR0 volatile.Register32 // 0xDC + CMD_INFOR1 volatile.Register32 // 0xE0 + _0_LEN_CONF volatile.Register32 // 0xE4 + _0_LENGTH volatile.Register32 // 0xE8 + _0_TXPKT_H_DSCR volatile.Register32 // 0xEC + _0_TXPKT_E_DSCR volatile.Register32 // 0xF0 + _0_RXPKT_H_DSCR volatile.Register32 // 0xF4 + _0_RXPKT_E_DSCR volatile.Register32 // 0xF8 + _0_TXPKTU_H_DSCR volatile.Register32 // 0xFC + _0_TXPKTU_E_DSCR volatile.Register32 // 0x100 + _0_RXPKTU_H_DSCR volatile.Register32 // 0x104 + _0_RXPKTU_E_DSCR volatile.Register32 // 0x108 + _ [8]byte + SEQ_POSITION volatile.Register32 // 0x114 + _0_DSCR_REC_CONF volatile.Register32 // 0x118 + SDIO_CRC_ST0 volatile.Register32 // 0x11C + SDIO_CRC_ST1 volatile.Register32 // 0x120 + _0_EOF_START_DES volatile.Register32 // 0x124 + _0_PUSH_DSCR_ADDR volatile.Register32 // 0x128 + _0_DONE_DSCR_ADDR volatile.Register32 // 0x12C + _0_SUB_START_DES volatile.Register32 // 0x130 + _0_DSCR_CNT volatile.Register32 // 0x134 + _0_LEN_LIM_CONF volatile.Register32 // 0x138 + _0INT_ST1 volatile.Register32 // 0x13C + _0INT_ENA1 volatile.Register32 // 0x140 + _1INT_ST1 volatile.Register32 // 0x144 + _1INT_ENA1 volatile.Register32 // 0x148 + _ [172]byte + DATE volatile.Register32 // 0x1F8 + ID volatile.Register32 // 0x1FC +} + +// SLC.CONF0 +func (o *SLC_Type) SetCONF0_SLC0_TX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetCONF0_SLC0_TX_RST() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *SLC_Type) SetCONF0_SLC0_RX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetCONF0_SLC0_RX_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetCONF0_AHBM_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) GetCONF0_AHBM_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) SetCONF0_AHBM_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) GetCONF0_AHBM_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) SetCONF0_SLC0_TX_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) GetCONF0_SLC0_TX_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) SetCONF0_SLC0_RX_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) GetCONF0_SLC0_RX_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) SetCONF0_SLC0_RX_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) GetCONF0_SLC0_RX_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) SetCONF0_SLC0_RX_NO_RESTART_CLR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) GetCONF0_SLC0_RX_NO_RESTART_CLR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) SetCONF0_SLC0_RXDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) GetCONF0_SLC0_RXDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) SetCONF0_SLC0_RXDATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) GetCONF0_SLC0_RXDATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) SetCONF0_SLC0_RXLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) GetCONF0_SLC0_RXLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) SetCONF0_SLC0_TXLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) GetCONF0_SLC0_TXLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) SetCONF0_SLC0_TXDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) GetCONF0_SLC0_TXDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) SetCONF0_SLC0_TXDATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) GetCONF0_SLC0_TXDATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) SetCONF0_SLC0_TOKEN_AUTO_CLR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) GetCONF0_SLC0_TOKEN_AUTO_CLR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) SetCONF0_SLC0_TOKEN_SEL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) GetCONF0_SLC0_TOKEN_SEL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) SetCONF0_SLC1_TX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetCONF0_SLC1_TX_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetCONF0_SLC1_RX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) GetCONF0_SLC1_RX_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) SetCONF0_SLC0_WR_RETRY_MASK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) GetCONF0_SLC0_WR_RETRY_MASK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) SetCONF0_SLC1_WR_RETRY_MASK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) GetCONF0_SLC1_WR_RETRY_MASK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) SetCONF0_SLC1_TX_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) GetCONF0_SLC1_TX_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) SetCONF0_SLC1_RX_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) GetCONF0_SLC1_RX_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) SetCONF0_SLC1_RX_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) GetCONF0_SLC1_RX_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) SetCONF0_SLC1_RX_NO_RESTART_CLR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) GetCONF0_SLC1_RX_NO_RESTART_CLR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) SetCONF0_SLC1_RXDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) GetCONF0_SLC1_RXDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000000) >> 24 +} +func (o *SLC_Type) SetCONF0_SLC1_RXDATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000000)|value<<25) +} +func (o *SLC_Type) GetCONF0_SLC1_RXDATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000000) >> 25 +} +func (o *SLC_Type) SetCONF0_SLC1_RXLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000000)|value<<26) +} +func (o *SLC_Type) GetCONF0_SLC1_RXLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000000) >> 26 +} +func (o *SLC_Type) SetCONF0_SLC1_TXLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *SLC_Type) GetCONF0_SLC1_TXLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000000) >> 27 +} +func (o *SLC_Type) SetCONF0_SLC1_TXDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *SLC_Type) GetCONF0_SLC1_TXDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000000) >> 28 +} +func (o *SLC_Type) SetCONF0_SLC1_TXDATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *SLC_Type) GetCONF0_SLC1_TXDATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000000) >> 29 +} +func (o *SLC_Type) SetCONF0_SLC1_TOKEN_AUTO_CLR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000000)|value<<30) +} +func (o *SLC_Type) GetCONF0_SLC1_TOKEN_AUTO_CLR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000000) >> 30 +} +func (o *SLC_Type) SetCONF0_SLC1_TOKEN_SEL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000000)|value<<31) +} +func (o *SLC_Type) GetCONF0_SLC1_TOKEN_SEL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000000) >> 31 +} + +// SLC._0INT_RAW +func (o *SLC_Type) Set_0INT_RAW_FRHOST_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_0INT_RAW_FRHOST_BIT0_INT_RAW() uint32 { + return volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x1 +} +func (o *SLC_Type) Set_0INT_RAW_FRHOST_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_0INT_RAW_FRHOST_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_0INT_RAW_FRHOST_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_0INT_RAW_FRHOST_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_0INT_RAW_FRHOST_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_0INT_RAW_FRHOST_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_0INT_RAW_FRHOST_BIT4_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_0INT_RAW_FRHOST_BIT4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_0INT_RAW_FRHOST_BIT5_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_0INT_RAW_FRHOST_BIT5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_0INT_RAW_FRHOST_BIT6_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_0INT_RAW_FRHOST_BIT6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_0INT_RAW_FRHOST_BIT7_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_0INT_RAW_FRHOST_BIT7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_RX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_RX_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_RX_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TX_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TX_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TX_SUC_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TX_SUC_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_RX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_RX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_RX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TOHOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TOHOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TX_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TX_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_RX_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_RX_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TX_DSCR_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TX_DSCR_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_HOST_RD_ACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_HOST_RD_ACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_WR_RETRY_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_WR_RETRY_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_TX_ERR_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_TX_ERR_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *SLC_Type) Set_0INT_RAW_CMD_DTC_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *SLC_Type) Get_0INT_RAW_CMD_DTC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *SLC_Type) Set_0INT_RAW_SLC0_RX_QUICK_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._0INT_RAW.Reg, volatile.LoadUint32(&o._0INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *SLC_Type) Get_0INT_RAW_SLC0_RX_QUICK_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._0INT_RAW.Reg) & 0x4000000) >> 26 +} + +// SLC._0INT_ST +func (o *SLC_Type) Set_0INT_ST_FRHOST_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_0INT_ST_FRHOST_BIT0_INT_ST() uint32 { + return volatile.LoadUint32(&o._0INT_ST.Reg) & 0x1 +} +func (o *SLC_Type) Set_0INT_ST_FRHOST_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_0INT_ST_FRHOST_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_0INT_ST_FRHOST_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_0INT_ST_FRHOST_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_0INT_ST_FRHOST_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_0INT_ST_FRHOST_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_0INT_ST_FRHOST_BIT4_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_0INT_ST_FRHOST_BIT4_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_0INT_ST_FRHOST_BIT5_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_0INT_ST_FRHOST_BIT5_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_0INT_ST_FRHOST_BIT6_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_0INT_ST_FRHOST_BIT6_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_0INT_ST_FRHOST_BIT7_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_0INT_ST_FRHOST_BIT7_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_RX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_RX_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_RX_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TX_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TX_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TOKEN0_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TOKEN0_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TOKEN1_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TOKEN1_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TX_SUC_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TX_SUC_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_RX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_RX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_RX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TOHOST_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TOHOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TX_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TX_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_RX_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_RX_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TX_DSCR_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TX_DSCR_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_HOST_RD_ACK_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_HOST_RD_ACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_WR_RETRY_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_WR_RETRY_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_TX_ERR_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_TX_ERR_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *SLC_Type) Set_0INT_ST_CMD_DTC_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *SLC_Type) Get_0INT_ST_CMD_DTC_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *SLC_Type) Set_0INT_ST_SLC0_RX_QUICK_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o._0INT_ST.Reg, volatile.LoadUint32(&o._0INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *SLC_Type) Get_0INT_ST_SLC0_RX_QUICK_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._0INT_ST.Reg) & 0x4000000) >> 26 +} + +// SLC._0INT_ENA +func (o *SLC_Type) Set_0INT_ENA_FRHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_0INT_ENA_FRHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x1 +} +func (o *SLC_Type) Set_0INT_ENA_FRHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_0INT_ENA_FRHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_0INT_ENA_FRHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_0INT_ENA_FRHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_0INT_ENA_FRHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_0INT_ENA_FRHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_0INT_ENA_FRHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_0INT_ENA_FRHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_0INT_ENA_FRHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_0INT_ENA_FRHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_0INT_ENA_FRHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_0INT_ENA_FRHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_0INT_ENA_FRHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_0INT_ENA_FRHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TX_SUC_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TX_SUC_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_RX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TOHOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TOHOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TX_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TX_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_RX_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_RX_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TX_DSCR_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TX_DSCR_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_HOST_RD_ACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_HOST_RD_ACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_WR_RETRY_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_WR_RETRY_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_TX_ERR_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_TX_ERR_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLC_Type) Set_0INT_ENA_CMD_DTC_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLC_Type) Get_0INT_ENA_CMD_DTC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *SLC_Type) Set_0INT_ENA_SLC0_RX_QUICK_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._0INT_ENA.Reg, volatile.LoadUint32(&o._0INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *SLC_Type) Get_0INT_ENA_SLC0_RX_QUICK_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA.Reg) & 0x4000000) >> 26 +} + +// SLC._0INT_CLR +func (o *SLC_Type) Set_0INT_CLR_FRHOST_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_0INT_CLR_FRHOST_BIT0_INT_CLR() uint32 { + return volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x1 +} +func (o *SLC_Type) Set_0INT_CLR_FRHOST_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_0INT_CLR_FRHOST_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_0INT_CLR_FRHOST_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_0INT_CLR_FRHOST_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_0INT_CLR_FRHOST_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_0INT_CLR_FRHOST_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_0INT_CLR_FRHOST_BIT4_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_0INT_CLR_FRHOST_BIT4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_0INT_CLR_FRHOST_BIT5_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_0INT_CLR_FRHOST_BIT5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_0INT_CLR_FRHOST_BIT6_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_0INT_CLR_FRHOST_BIT6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_0INT_CLR_FRHOST_BIT7_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_0INT_CLR_FRHOST_BIT7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_RX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_RX_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_RX_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TX_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TX_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TX_SUC_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TX_SUC_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_RX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_RX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_RX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TOHOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TOHOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TX_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TX_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_RX_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_RX_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TX_DSCR_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TX_DSCR_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_HOST_RD_ACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_HOST_RD_ACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_WR_RETRY_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_WR_RETRY_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_TX_ERR_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_TX_ERR_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SLC_Type) Set_0INT_CLR_CMD_DTC_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SLC_Type) Get_0INT_CLR_CMD_DTC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SLC_Type) Set_0INT_CLR_SLC0_RX_QUICK_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._0INT_CLR.Reg, volatile.LoadUint32(&o._0INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SLC_Type) Get_0INT_CLR_SLC0_RX_QUICK_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._0INT_CLR.Reg) & 0x4000000) >> 26 +} + +// SLC._1INT_RAW +func (o *SLC_Type) Set_1INT_RAW_FRHOST_BIT8_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_1INT_RAW_FRHOST_BIT8_INT_RAW() uint32 { + return volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x1 +} +func (o *SLC_Type) Set_1INT_RAW_FRHOST_BIT9_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_1INT_RAW_FRHOST_BIT9_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_1INT_RAW_FRHOST_BIT10_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_1INT_RAW_FRHOST_BIT10_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_1INT_RAW_FRHOST_BIT11_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_1INT_RAW_FRHOST_BIT11_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_1INT_RAW_FRHOST_BIT12_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_1INT_RAW_FRHOST_BIT12_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_1INT_RAW_FRHOST_BIT13_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_1INT_RAW_FRHOST_BIT13_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_1INT_RAW_FRHOST_BIT14_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_1INT_RAW_FRHOST_BIT14_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_1INT_RAW_FRHOST_BIT15_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_1INT_RAW_FRHOST_BIT15_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_RX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_RX_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_RX_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TX_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TX_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TX_SUC_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TX_SUC_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_RX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_RX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_RX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TOHOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TOHOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TX_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TX_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_RX_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_RX_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TX_DSCR_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TX_DSCR_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_HOST_RD_ACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_HOST_RD_ACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_WR_RETRY_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_WR_RETRY_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_1INT_RAW_SLC1_TX_ERR_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o._1INT_RAW.Reg, volatile.LoadUint32(&o._1INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_1INT_RAW_SLC1_TX_ERR_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o._1INT_RAW.Reg) & 0x1000000) >> 24 +} + +// SLC._1INT_ST +func (o *SLC_Type) Set_1INT_ST_FRHOST_BIT8_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_1INT_ST_FRHOST_BIT8_INT_ST() uint32 { + return volatile.LoadUint32(&o._1INT_ST.Reg) & 0x1 +} +func (o *SLC_Type) Set_1INT_ST_FRHOST_BIT9_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_1INT_ST_FRHOST_BIT9_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_1INT_ST_FRHOST_BIT10_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_1INT_ST_FRHOST_BIT10_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_1INT_ST_FRHOST_BIT11_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_1INT_ST_FRHOST_BIT11_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_1INT_ST_FRHOST_BIT12_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_1INT_ST_FRHOST_BIT12_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_1INT_ST_FRHOST_BIT13_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_1INT_ST_FRHOST_BIT13_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_1INT_ST_FRHOST_BIT14_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_1INT_ST_FRHOST_BIT14_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_1INT_ST_FRHOST_BIT15_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_1INT_ST_FRHOST_BIT15_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_RX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_RX_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_RX_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TX_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TX_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TOKEN0_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TOKEN0_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TOKEN1_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TOKEN1_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TX_SUC_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TX_SUC_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_RX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_RX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_RX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TOHOST_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TOHOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TX_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TX_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_RX_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_RX_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TX_DSCR_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TX_DSCR_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_HOST_RD_ACK_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_HOST_RD_ACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_WR_RETRY_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_WR_RETRY_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_1INT_ST_SLC1_TX_ERR_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o._1INT_ST.Reg, volatile.LoadUint32(&o._1INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_1INT_ST_SLC1_TX_ERR_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o._1INT_ST.Reg) & 0x1000000) >> 24 +} + +// SLC._1INT_ENA +func (o *SLC_Type) Set_1INT_ENA_FRHOST_BIT8_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_1INT_ENA_FRHOST_BIT8_INT_ENA() uint32 { + return volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x1 +} +func (o *SLC_Type) Set_1INT_ENA_FRHOST_BIT9_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_1INT_ENA_FRHOST_BIT9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_1INT_ENA_FRHOST_BIT10_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_1INT_ENA_FRHOST_BIT10_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_1INT_ENA_FRHOST_BIT11_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_1INT_ENA_FRHOST_BIT11_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_1INT_ENA_FRHOST_BIT12_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_1INT_ENA_FRHOST_BIT12_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_1INT_ENA_FRHOST_BIT13_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_1INT_ENA_FRHOST_BIT13_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_1INT_ENA_FRHOST_BIT14_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_1INT_ENA_FRHOST_BIT14_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_1INT_ENA_FRHOST_BIT15_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_1INT_ENA_FRHOST_BIT15_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TX_SUC_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TX_SUC_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_RX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TOHOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TOHOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TX_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TX_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_RX_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_RX_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TX_DSCR_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TX_DSCR_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_HOST_RD_ACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_HOST_RD_ACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_WR_RETRY_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_WR_RETRY_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_1INT_ENA_SLC1_TX_ERR_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o._1INT_ENA.Reg, volatile.LoadUint32(&o._1INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_1INT_ENA_SLC1_TX_ERR_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA.Reg) & 0x1000000) >> 24 +} + +// SLC._1INT_CLR +func (o *SLC_Type) Set_1INT_CLR_FRHOST_BIT8_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_1INT_CLR_FRHOST_BIT8_INT_CLR() uint32 { + return volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x1 +} +func (o *SLC_Type) Set_1INT_CLR_FRHOST_BIT9_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_1INT_CLR_FRHOST_BIT9_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_1INT_CLR_FRHOST_BIT10_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_1INT_CLR_FRHOST_BIT10_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_1INT_CLR_FRHOST_BIT11_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_1INT_CLR_FRHOST_BIT11_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_1INT_CLR_FRHOST_BIT12_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_1INT_CLR_FRHOST_BIT12_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_1INT_CLR_FRHOST_BIT13_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_1INT_CLR_FRHOST_BIT13_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_1INT_CLR_FRHOST_BIT14_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_1INT_CLR_FRHOST_BIT14_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_1INT_CLR_FRHOST_BIT15_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_1INT_CLR_FRHOST_BIT15_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_RX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_RX_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_RX_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TX_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TX_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TX_SUC_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TX_SUC_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_RX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_RX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_RX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TOHOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TOHOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TX_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TX_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_RX_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_RX_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TX_DSCR_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TX_DSCR_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_HOST_RD_ACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_HOST_RD_ACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_WR_RETRY_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_WR_RETRY_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_1INT_CLR_SLC1_TX_ERR_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o._1INT_CLR.Reg, volatile.LoadUint32(&o._1INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_1INT_CLR_SLC1_TX_ERR_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o._1INT_CLR.Reg) & 0x1000000) >> 24 +} + +// SLC.RX_STATUS +func (o *SLC_Type) SetRX_STATUS_SLC0_RX_FULL(value uint32) { + volatile.StoreUint32(&o.RX_STATUS.Reg, volatile.LoadUint32(&o.RX_STATUS.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetRX_STATUS_SLC0_RX_FULL() uint32 { + return volatile.LoadUint32(&o.RX_STATUS.Reg) & 0x1 +} +func (o *SLC_Type) SetRX_STATUS_SLC0_RX_EMPTY(value uint32) { + volatile.StoreUint32(&o.RX_STATUS.Reg, volatile.LoadUint32(&o.RX_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetRX_STATUS_SLC0_RX_EMPTY() uint32 { + return (volatile.LoadUint32(&o.RX_STATUS.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetRX_STATUS_SLC1_RX_FULL(value uint32) { + volatile.StoreUint32(&o.RX_STATUS.Reg, volatile.LoadUint32(&o.RX_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetRX_STATUS_SLC1_RX_FULL() uint32 { + return (volatile.LoadUint32(&o.RX_STATUS.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetRX_STATUS_SLC1_RX_EMPTY(value uint32) { + volatile.StoreUint32(&o.RX_STATUS.Reg, volatile.LoadUint32(&o.RX_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) GetRX_STATUS_SLC1_RX_EMPTY() uint32 { + return (volatile.LoadUint32(&o.RX_STATUS.Reg) & 0x20000) >> 17 +} + +// SLC._0RXFIFO_PUSH +func (o *SLC_Type) Set_0RXFIFO_PUSH_SLC0_RXFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o._0RXFIFO_PUSH.Reg, volatile.LoadUint32(&o._0RXFIFO_PUSH.Reg)&^(0x1ff)|value) +} +func (o *SLC_Type) Get_0RXFIFO_PUSH_SLC0_RXFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o._0RXFIFO_PUSH.Reg) & 0x1ff +} +func (o *SLC_Type) Set_0RXFIFO_PUSH_SLC0_RXFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o._0RXFIFO_PUSH.Reg, volatile.LoadUint32(&o._0RXFIFO_PUSH.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_0RXFIFO_PUSH_SLC0_RXFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o._0RXFIFO_PUSH.Reg) & 0x10000) >> 16 +} + +// SLC._1RXFIFO_PUSH +func (o *SLC_Type) Set_1RXFIFO_PUSH_SLC1_RXFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o._1RXFIFO_PUSH.Reg, volatile.LoadUint32(&o._1RXFIFO_PUSH.Reg)&^(0x1ff)|value) +} +func (o *SLC_Type) Get_1RXFIFO_PUSH_SLC1_RXFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o._1RXFIFO_PUSH.Reg) & 0x1ff +} +func (o *SLC_Type) Set_1RXFIFO_PUSH_SLC1_RXFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o._1RXFIFO_PUSH.Reg, volatile.LoadUint32(&o._1RXFIFO_PUSH.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_1RXFIFO_PUSH_SLC1_RXFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o._1RXFIFO_PUSH.Reg) & 0x10000) >> 16 +} + +// SLC.TX_STATUS +func (o *SLC_Type) SetTX_STATUS_SLC0_TX_FULL(value uint32) { + volatile.StoreUint32(&o.TX_STATUS.Reg, volatile.LoadUint32(&o.TX_STATUS.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetTX_STATUS_SLC0_TX_FULL() uint32 { + return volatile.LoadUint32(&o.TX_STATUS.Reg) & 0x1 +} +func (o *SLC_Type) SetTX_STATUS_SLC0_TX_EMPTY(value uint32) { + volatile.StoreUint32(&o.TX_STATUS.Reg, volatile.LoadUint32(&o.TX_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetTX_STATUS_SLC0_TX_EMPTY() uint32 { + return (volatile.LoadUint32(&o.TX_STATUS.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetTX_STATUS_SLC1_TX_FULL(value uint32) { + volatile.StoreUint32(&o.TX_STATUS.Reg, volatile.LoadUint32(&o.TX_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetTX_STATUS_SLC1_TX_FULL() uint32 { + return (volatile.LoadUint32(&o.TX_STATUS.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetTX_STATUS_SLC1_TX_EMPTY(value uint32) { + volatile.StoreUint32(&o.TX_STATUS.Reg, volatile.LoadUint32(&o.TX_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) GetTX_STATUS_SLC1_TX_EMPTY() uint32 { + return (volatile.LoadUint32(&o.TX_STATUS.Reg) & 0x20000) >> 17 +} + +// SLC._0TXFIFO_POP +func (o *SLC_Type) Set_0TXFIFO_POP_SLC0_TXFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o._0TXFIFO_POP.Reg, volatile.LoadUint32(&o._0TXFIFO_POP.Reg)&^(0x7ff)|value) +} +func (o *SLC_Type) Get_0TXFIFO_POP_SLC0_TXFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o._0TXFIFO_POP.Reg) & 0x7ff +} +func (o *SLC_Type) Set_0TXFIFO_POP_SLC0_TXFIFO_POP(value uint32) { + volatile.StoreUint32(&o._0TXFIFO_POP.Reg, volatile.LoadUint32(&o._0TXFIFO_POP.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_0TXFIFO_POP_SLC0_TXFIFO_POP() uint32 { + return (volatile.LoadUint32(&o._0TXFIFO_POP.Reg) & 0x10000) >> 16 +} + +// SLC._1TXFIFO_POP +func (o *SLC_Type) Set_1TXFIFO_POP_SLC1_TXFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o._1TXFIFO_POP.Reg, volatile.LoadUint32(&o._1TXFIFO_POP.Reg)&^(0x7ff)|value) +} +func (o *SLC_Type) Get_1TXFIFO_POP_SLC1_TXFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o._1TXFIFO_POP.Reg) & 0x7ff +} +func (o *SLC_Type) Set_1TXFIFO_POP_SLC1_TXFIFO_POP(value uint32) { + volatile.StoreUint32(&o._1TXFIFO_POP.Reg, volatile.LoadUint32(&o._1TXFIFO_POP.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_1TXFIFO_POP_SLC1_TXFIFO_POP() uint32 { + return (volatile.LoadUint32(&o._1TXFIFO_POP.Reg) & 0x10000) >> 16 +} + +// SLC._0RX_LINK +func (o *SLC_Type) Set_0RX_LINK_SLC0_RXLINK_ADDR(value uint32) { + volatile.StoreUint32(&o._0RX_LINK.Reg, volatile.LoadUint32(&o._0RX_LINK.Reg)&^(0xfffff)|value) +} +func (o *SLC_Type) Get_0RX_LINK_SLC0_RXLINK_ADDR() uint32 { + return volatile.LoadUint32(&o._0RX_LINK.Reg) & 0xfffff +} +func (o *SLC_Type) Set_0RX_LINK_SLC0_RXLINK_STOP(value uint32) { + volatile.StoreUint32(&o._0RX_LINK.Reg, volatile.LoadUint32(&o._0RX_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SLC_Type) Get_0RX_LINK_SLC0_RXLINK_STOP() uint32 { + return (volatile.LoadUint32(&o._0RX_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SLC_Type) Set_0RX_LINK_SLC0_RXLINK_START(value uint32) { + volatile.StoreUint32(&o._0RX_LINK.Reg, volatile.LoadUint32(&o._0RX_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SLC_Type) Get_0RX_LINK_SLC0_RXLINK_START() uint32 { + return (volatile.LoadUint32(&o._0RX_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SLC_Type) Set_0RX_LINK_SLC0_RXLINK_RESTART(value uint32) { + volatile.StoreUint32(&o._0RX_LINK.Reg, volatile.LoadUint32(&o._0RX_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SLC_Type) Get_0RX_LINK_SLC0_RXLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o._0RX_LINK.Reg) & 0x40000000) >> 30 +} +func (o *SLC_Type) Set_0RX_LINK_SLC0_RXLINK_PARK(value uint32) { + volatile.StoreUint32(&o._0RX_LINK.Reg, volatile.LoadUint32(&o._0RX_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *SLC_Type) Get_0RX_LINK_SLC0_RXLINK_PARK() uint32 { + return (volatile.LoadUint32(&o._0RX_LINK.Reg) & 0x80000000) >> 31 +} + +// SLC._0TX_LINK +func (o *SLC_Type) Set_0TX_LINK_SLC0_TXLINK_ADDR(value uint32) { + volatile.StoreUint32(&o._0TX_LINK.Reg, volatile.LoadUint32(&o._0TX_LINK.Reg)&^(0xfffff)|value) +} +func (o *SLC_Type) Get_0TX_LINK_SLC0_TXLINK_ADDR() uint32 { + return volatile.LoadUint32(&o._0TX_LINK.Reg) & 0xfffff +} +func (o *SLC_Type) Set_0TX_LINK_SLC0_TXLINK_STOP(value uint32) { + volatile.StoreUint32(&o._0TX_LINK.Reg, volatile.LoadUint32(&o._0TX_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SLC_Type) Get_0TX_LINK_SLC0_TXLINK_STOP() uint32 { + return (volatile.LoadUint32(&o._0TX_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SLC_Type) Set_0TX_LINK_SLC0_TXLINK_START(value uint32) { + volatile.StoreUint32(&o._0TX_LINK.Reg, volatile.LoadUint32(&o._0TX_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SLC_Type) Get_0TX_LINK_SLC0_TXLINK_START() uint32 { + return (volatile.LoadUint32(&o._0TX_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SLC_Type) Set_0TX_LINK_SLC0_TXLINK_RESTART(value uint32) { + volatile.StoreUint32(&o._0TX_LINK.Reg, volatile.LoadUint32(&o._0TX_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SLC_Type) Get_0TX_LINK_SLC0_TXLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o._0TX_LINK.Reg) & 0x40000000) >> 30 +} +func (o *SLC_Type) Set_0TX_LINK_SLC0_TXLINK_PARK(value uint32) { + volatile.StoreUint32(&o._0TX_LINK.Reg, volatile.LoadUint32(&o._0TX_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *SLC_Type) Get_0TX_LINK_SLC0_TXLINK_PARK() uint32 { + return (volatile.LoadUint32(&o._0TX_LINK.Reg) & 0x80000000) >> 31 +} + +// SLC._1RX_LINK +func (o *SLC_Type) Set_1RX_LINK_SLC1_RXLINK_ADDR(value uint32) { + volatile.StoreUint32(&o._1RX_LINK.Reg, volatile.LoadUint32(&o._1RX_LINK.Reg)&^(0xfffff)|value) +} +func (o *SLC_Type) Get_1RX_LINK_SLC1_RXLINK_ADDR() uint32 { + return volatile.LoadUint32(&o._1RX_LINK.Reg) & 0xfffff +} +func (o *SLC_Type) Set_1RX_LINK_SLC1_BT_PACKET(value uint32) { + volatile.StoreUint32(&o._1RX_LINK.Reg, volatile.LoadUint32(&o._1RX_LINK.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_1RX_LINK_SLC1_BT_PACKET() uint32 { + return (volatile.LoadUint32(&o._1RX_LINK.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_1RX_LINK_SLC1_RXLINK_STOP(value uint32) { + volatile.StoreUint32(&o._1RX_LINK.Reg, volatile.LoadUint32(&o._1RX_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SLC_Type) Get_1RX_LINK_SLC1_RXLINK_STOP() uint32 { + return (volatile.LoadUint32(&o._1RX_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SLC_Type) Set_1RX_LINK_SLC1_RXLINK_START(value uint32) { + volatile.StoreUint32(&o._1RX_LINK.Reg, volatile.LoadUint32(&o._1RX_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SLC_Type) Get_1RX_LINK_SLC1_RXLINK_START() uint32 { + return (volatile.LoadUint32(&o._1RX_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SLC_Type) Set_1RX_LINK_SLC1_RXLINK_RESTART(value uint32) { + volatile.StoreUint32(&o._1RX_LINK.Reg, volatile.LoadUint32(&o._1RX_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SLC_Type) Get_1RX_LINK_SLC1_RXLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o._1RX_LINK.Reg) & 0x40000000) >> 30 +} +func (o *SLC_Type) Set_1RX_LINK_SLC1_RXLINK_PARK(value uint32) { + volatile.StoreUint32(&o._1RX_LINK.Reg, volatile.LoadUint32(&o._1RX_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *SLC_Type) Get_1RX_LINK_SLC1_RXLINK_PARK() uint32 { + return (volatile.LoadUint32(&o._1RX_LINK.Reg) & 0x80000000) >> 31 +} + +// SLC._1TX_LINK +func (o *SLC_Type) Set_1TX_LINK_SLC1_TXLINK_ADDR(value uint32) { + volatile.StoreUint32(&o._1TX_LINK.Reg, volatile.LoadUint32(&o._1TX_LINK.Reg)&^(0xfffff)|value) +} +func (o *SLC_Type) Get_1TX_LINK_SLC1_TXLINK_ADDR() uint32 { + return volatile.LoadUint32(&o._1TX_LINK.Reg) & 0xfffff +} +func (o *SLC_Type) Set_1TX_LINK_SLC1_TXLINK_STOP(value uint32) { + volatile.StoreUint32(&o._1TX_LINK.Reg, volatile.LoadUint32(&o._1TX_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SLC_Type) Get_1TX_LINK_SLC1_TXLINK_STOP() uint32 { + return (volatile.LoadUint32(&o._1TX_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SLC_Type) Set_1TX_LINK_SLC1_TXLINK_START(value uint32) { + volatile.StoreUint32(&o._1TX_LINK.Reg, volatile.LoadUint32(&o._1TX_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SLC_Type) Get_1TX_LINK_SLC1_TXLINK_START() uint32 { + return (volatile.LoadUint32(&o._1TX_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SLC_Type) Set_1TX_LINK_SLC1_TXLINK_RESTART(value uint32) { + volatile.StoreUint32(&o._1TX_LINK.Reg, volatile.LoadUint32(&o._1TX_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SLC_Type) Get_1TX_LINK_SLC1_TXLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o._1TX_LINK.Reg) & 0x40000000) >> 30 +} +func (o *SLC_Type) Set_1TX_LINK_SLC1_TXLINK_PARK(value uint32) { + volatile.StoreUint32(&o._1TX_LINK.Reg, volatile.LoadUint32(&o._1TX_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *SLC_Type) Get_1TX_LINK_SLC1_TXLINK_PARK() uint32 { + return (volatile.LoadUint32(&o._1TX_LINK.Reg) & 0x80000000) >> 31 +} + +// SLC.INTVEC_TOHOST +func (o *SLC_Type) SetINTVEC_TOHOST_SLC0_TOHOST_INTVEC(value uint32) { + volatile.StoreUint32(&o.INTVEC_TOHOST.Reg, volatile.LoadUint32(&o.INTVEC_TOHOST.Reg)&^(0xff)|value) +} +func (o *SLC_Type) GetINTVEC_TOHOST_SLC0_TOHOST_INTVEC() uint32 { + return volatile.LoadUint32(&o.INTVEC_TOHOST.Reg) & 0xff +} +func (o *SLC_Type) SetINTVEC_TOHOST_SLC1_TOHOST_INTVEC(value uint32) { + volatile.StoreUint32(&o.INTVEC_TOHOST.Reg, volatile.LoadUint32(&o.INTVEC_TOHOST.Reg)&^(0xff0000)|value<<16) +} +func (o *SLC_Type) GetINTVEC_TOHOST_SLC1_TOHOST_INTVEC() uint32 { + return (volatile.LoadUint32(&o.INTVEC_TOHOST.Reg) & 0xff0000) >> 16 +} + +// SLC._0TOKEN0 +func (o *SLC_Type) Set_0TOKEN0_SLC0_TOKEN0_WDATA(value uint32) { + volatile.StoreUint32(&o._0TOKEN0.Reg, volatile.LoadUint32(&o._0TOKEN0.Reg)&^(0xfff)|value) +} +func (o *SLC_Type) Get_0TOKEN0_SLC0_TOKEN0_WDATA() uint32 { + return volatile.LoadUint32(&o._0TOKEN0.Reg) & 0xfff +} +func (o *SLC_Type) Set_0TOKEN0_SLC0_TOKEN0_WR(value uint32) { + volatile.StoreUint32(&o._0TOKEN0.Reg, volatile.LoadUint32(&o._0TOKEN0.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_0TOKEN0_SLC0_TOKEN0_WR() uint32 { + return (volatile.LoadUint32(&o._0TOKEN0.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_0TOKEN0_SLC0_TOKEN0_INC(value uint32) { + volatile.StoreUint32(&o._0TOKEN0.Reg, volatile.LoadUint32(&o._0TOKEN0.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_0TOKEN0_SLC0_TOKEN0_INC() uint32 { + return (volatile.LoadUint32(&o._0TOKEN0.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_0TOKEN0_SLC0_TOKEN0_INC_MORE(value uint32) { + volatile.StoreUint32(&o._0TOKEN0.Reg, volatile.LoadUint32(&o._0TOKEN0.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_0TOKEN0_SLC0_TOKEN0_INC_MORE() uint32 { + return (volatile.LoadUint32(&o._0TOKEN0.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_0TOKEN0_SLC0_TOKEN0(value uint32) { + volatile.StoreUint32(&o._0TOKEN0.Reg, volatile.LoadUint32(&o._0TOKEN0.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLC_Type) Get_0TOKEN0_SLC0_TOKEN0() uint32 { + return (volatile.LoadUint32(&o._0TOKEN0.Reg) & 0xfff0000) >> 16 +} + +// SLC._0TOKEN1 +func (o *SLC_Type) Set_0TOKEN1_SLC0_TOKEN1_WDATA(value uint32) { + volatile.StoreUint32(&o._0TOKEN1.Reg, volatile.LoadUint32(&o._0TOKEN1.Reg)&^(0xfff)|value) +} +func (o *SLC_Type) Get_0TOKEN1_SLC0_TOKEN1_WDATA() uint32 { + return volatile.LoadUint32(&o._0TOKEN1.Reg) & 0xfff +} +func (o *SLC_Type) Set_0TOKEN1_SLC0_TOKEN1_WR(value uint32) { + volatile.StoreUint32(&o._0TOKEN1.Reg, volatile.LoadUint32(&o._0TOKEN1.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_0TOKEN1_SLC0_TOKEN1_WR() uint32 { + return (volatile.LoadUint32(&o._0TOKEN1.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_0TOKEN1_SLC0_TOKEN1_INC(value uint32) { + volatile.StoreUint32(&o._0TOKEN1.Reg, volatile.LoadUint32(&o._0TOKEN1.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_0TOKEN1_SLC0_TOKEN1_INC() uint32 { + return (volatile.LoadUint32(&o._0TOKEN1.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_0TOKEN1_SLC0_TOKEN1_INC_MORE(value uint32) { + volatile.StoreUint32(&o._0TOKEN1.Reg, volatile.LoadUint32(&o._0TOKEN1.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_0TOKEN1_SLC0_TOKEN1_INC_MORE() uint32 { + return (volatile.LoadUint32(&o._0TOKEN1.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_0TOKEN1_SLC0_TOKEN1(value uint32) { + volatile.StoreUint32(&o._0TOKEN1.Reg, volatile.LoadUint32(&o._0TOKEN1.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLC_Type) Get_0TOKEN1_SLC0_TOKEN1() uint32 { + return (volatile.LoadUint32(&o._0TOKEN1.Reg) & 0xfff0000) >> 16 +} + +// SLC._1TOKEN0 +func (o *SLC_Type) Set_1TOKEN0_SLC1_TOKEN0_WDATA(value uint32) { + volatile.StoreUint32(&o._1TOKEN0.Reg, volatile.LoadUint32(&o._1TOKEN0.Reg)&^(0xfff)|value) +} +func (o *SLC_Type) Get_1TOKEN0_SLC1_TOKEN0_WDATA() uint32 { + return volatile.LoadUint32(&o._1TOKEN0.Reg) & 0xfff +} +func (o *SLC_Type) Set_1TOKEN0_SLC1_TOKEN0_WR(value uint32) { + volatile.StoreUint32(&o._1TOKEN0.Reg, volatile.LoadUint32(&o._1TOKEN0.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_1TOKEN0_SLC1_TOKEN0_WR() uint32 { + return (volatile.LoadUint32(&o._1TOKEN0.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_1TOKEN0_SLC1_TOKEN0_INC(value uint32) { + volatile.StoreUint32(&o._1TOKEN0.Reg, volatile.LoadUint32(&o._1TOKEN0.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_1TOKEN0_SLC1_TOKEN0_INC() uint32 { + return (volatile.LoadUint32(&o._1TOKEN0.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_1TOKEN0_SLC1_TOKEN0_INC_MORE(value uint32) { + volatile.StoreUint32(&o._1TOKEN0.Reg, volatile.LoadUint32(&o._1TOKEN0.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_1TOKEN0_SLC1_TOKEN0_INC_MORE() uint32 { + return (volatile.LoadUint32(&o._1TOKEN0.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_1TOKEN0_SLC1_TOKEN0(value uint32) { + volatile.StoreUint32(&o._1TOKEN0.Reg, volatile.LoadUint32(&o._1TOKEN0.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLC_Type) Get_1TOKEN0_SLC1_TOKEN0() uint32 { + return (volatile.LoadUint32(&o._1TOKEN0.Reg) & 0xfff0000) >> 16 +} + +// SLC._1TOKEN1 +func (o *SLC_Type) Set_1TOKEN1_SLC1_TOKEN1_WDATA(value uint32) { + volatile.StoreUint32(&o._1TOKEN1.Reg, volatile.LoadUint32(&o._1TOKEN1.Reg)&^(0xfff)|value) +} +func (o *SLC_Type) Get_1TOKEN1_SLC1_TOKEN1_WDATA() uint32 { + return volatile.LoadUint32(&o._1TOKEN1.Reg) & 0xfff +} +func (o *SLC_Type) Set_1TOKEN1_SLC1_TOKEN1_WR(value uint32) { + volatile.StoreUint32(&o._1TOKEN1.Reg, volatile.LoadUint32(&o._1TOKEN1.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_1TOKEN1_SLC1_TOKEN1_WR() uint32 { + return (volatile.LoadUint32(&o._1TOKEN1.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_1TOKEN1_SLC1_TOKEN1_INC(value uint32) { + volatile.StoreUint32(&o._1TOKEN1.Reg, volatile.LoadUint32(&o._1TOKEN1.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_1TOKEN1_SLC1_TOKEN1_INC() uint32 { + return (volatile.LoadUint32(&o._1TOKEN1.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_1TOKEN1_SLC1_TOKEN1_INC_MORE(value uint32) { + volatile.StoreUint32(&o._1TOKEN1.Reg, volatile.LoadUint32(&o._1TOKEN1.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_1TOKEN1_SLC1_TOKEN1_INC_MORE() uint32 { + return (volatile.LoadUint32(&o._1TOKEN1.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_1TOKEN1_SLC1_TOKEN1(value uint32) { + volatile.StoreUint32(&o._1TOKEN1.Reg, volatile.LoadUint32(&o._1TOKEN1.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLC_Type) Get_1TOKEN1_SLC1_TOKEN1() uint32 { + return (volatile.LoadUint32(&o._1TOKEN1.Reg) & 0xfff0000) >> 16 +} + +// SLC.CONF1 +func (o *SLC_Type) SetCONF1_SLC0_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetCONF1_SLC0_CHECK_OWNER() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1 +} +func (o *SLC_Type) SetCONF1_SLC0_TX_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetCONF1_SLC0_TX_CHECK_SUM_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetCONF1_SLC0_RX_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) GetCONF1_SLC0_RX_CHECK_SUM_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) SetCONF1_CMD_HOLD_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) GetCONF1_CMD_HOLD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) SetCONF1_SLC0_LEN_AUTO_CLR(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) GetCONF1_SLC0_LEN_AUTO_CLR() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) SetCONF1_SLC0_TX_STITCH_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) GetCONF1_SLC0_TX_STITCH_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) SetCONF1_SLC0_RX_STITCH_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) GetCONF1_SLC0_RX_STITCH_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) SetCONF1_SLC1_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetCONF1_SLC1_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetCONF1_SLC1_TX_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) GetCONF1_SLC1_TX_CHECK_SUM_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) SetCONF1_SLC1_RX_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) GetCONF1_SLC1_RX_CHECK_SUM_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) SetCONF1_HOST_INT_LEVEL_SEL(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) GetCONF1_HOST_INT_LEVEL_SEL() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) SetCONF1_SLC1_TX_STITCH_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) GetCONF1_SLC1_TX_STITCH_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) SetCONF1_SLC1_RX_STITCH_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) GetCONF1_SLC1_RX_STITCH_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) SetCONF1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) GetCONF1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x400000) >> 22 +} + +// SLC._0_STATE0 +func (o *SLC_Type) Set_0_STATE0(value uint32) { + volatile.StoreUint32(&o._0_STATE0.Reg, value) +} +func (o *SLC_Type) Get_0_STATE0() uint32 { + return volatile.LoadUint32(&o._0_STATE0.Reg) +} + +// SLC._0_STATE1 +func (o *SLC_Type) Set_0_STATE1(value uint32) { + volatile.StoreUint32(&o._0_STATE1.Reg, value) +} +func (o *SLC_Type) Get_0_STATE1() uint32 { + return volatile.LoadUint32(&o._0_STATE1.Reg) +} + +// SLC._1_STATE0 +func (o *SLC_Type) Set_1_STATE0(value uint32) { + volatile.StoreUint32(&o._1_STATE0.Reg, value) +} +func (o *SLC_Type) Get_1_STATE0() uint32 { + return volatile.LoadUint32(&o._1_STATE0.Reg) +} + +// SLC._1_STATE1 +func (o *SLC_Type) Set_1_STATE1(value uint32) { + volatile.StoreUint32(&o._1_STATE1.Reg, value) +} +func (o *SLC_Type) Get_1_STATE1() uint32 { + return volatile.LoadUint32(&o._1_STATE1.Reg) +} + +// SLC.BRIDGE_CONF +func (o *SLC_Type) SetBRIDGE_CONF_TXEOF_ENA(value uint32) { + volatile.StoreUint32(&o.BRIDGE_CONF.Reg, volatile.LoadUint32(&o.BRIDGE_CONF.Reg)&^(0x3f)|value) +} +func (o *SLC_Type) GetBRIDGE_CONF_TXEOF_ENA() uint32 { + return volatile.LoadUint32(&o.BRIDGE_CONF.Reg) & 0x3f +} +func (o *SLC_Type) SetBRIDGE_CONF_FIFO_MAP_ENA(value uint32) { + volatile.StoreUint32(&o.BRIDGE_CONF.Reg, volatile.LoadUint32(&o.BRIDGE_CONF.Reg)&^(0xf00)|value<<8) +} +func (o *SLC_Type) GetBRIDGE_CONF_FIFO_MAP_ENA() uint32 { + return (volatile.LoadUint32(&o.BRIDGE_CONF.Reg) & 0xf00) >> 8 +} +func (o *SLC_Type) SetBRIDGE_CONF_SLC0_TX_DUMMY_MODE(value uint32) { + volatile.StoreUint32(&o.BRIDGE_CONF.Reg, volatile.LoadUint32(&o.BRIDGE_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) GetBRIDGE_CONF_SLC0_TX_DUMMY_MODE() uint32 { + return (volatile.LoadUint32(&o.BRIDGE_CONF.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) SetBRIDGE_CONF_HDA_MAP_128K(value uint32) { + volatile.StoreUint32(&o.BRIDGE_CONF.Reg, volatile.LoadUint32(&o.BRIDGE_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) GetBRIDGE_CONF_HDA_MAP_128K() uint32 { + return (volatile.LoadUint32(&o.BRIDGE_CONF.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) SetBRIDGE_CONF_SLC1_TX_DUMMY_MODE(value uint32) { + volatile.StoreUint32(&o.BRIDGE_CONF.Reg, volatile.LoadUint32(&o.BRIDGE_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) GetBRIDGE_CONF_SLC1_TX_DUMMY_MODE() uint32 { + return (volatile.LoadUint32(&o.BRIDGE_CONF.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) SetBRIDGE_CONF_TX_PUSH_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.BRIDGE_CONF.Reg, volatile.LoadUint32(&o.BRIDGE_CONF.Reg)&^(0xffff0000)|value<<16) +} +func (o *SLC_Type) GetBRIDGE_CONF_TX_PUSH_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.BRIDGE_CONF.Reg) & 0xffff0000) >> 16 +} + +// SLC._0_TO_EOF_DES_ADDR +func (o *SLC_Type) Set_0_TO_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o._0_TO_EOF_DES_ADDR.Reg, value) +} +func (o *SLC_Type) Get_0_TO_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o._0_TO_EOF_DES_ADDR.Reg) +} + +// SLC._0_TX_EOF_DES_ADDR +func (o *SLC_Type) Set_0_TX_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o._0_TX_EOF_DES_ADDR.Reg, value) +} +func (o *SLC_Type) Get_0_TX_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o._0_TX_EOF_DES_ADDR.Reg) +} + +// SLC._0_TO_EOF_BFR_DES_ADDR +func (o *SLC_Type) Set_0_TO_EOF_BFR_DES_ADDR(value uint32) { + volatile.StoreUint32(&o._0_TO_EOF_BFR_DES_ADDR.Reg, value) +} +func (o *SLC_Type) Get_0_TO_EOF_BFR_DES_ADDR() uint32 { + return volatile.LoadUint32(&o._0_TO_EOF_BFR_DES_ADDR.Reg) +} + +// SLC._1_TO_EOF_DES_ADDR +func (o *SLC_Type) Set_1_TO_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o._1_TO_EOF_DES_ADDR.Reg, value) +} +func (o *SLC_Type) Get_1_TO_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o._1_TO_EOF_DES_ADDR.Reg) +} + +// SLC._1_TX_EOF_DES_ADDR +func (o *SLC_Type) Set_1_TX_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o._1_TX_EOF_DES_ADDR.Reg, value) +} +func (o *SLC_Type) Get_1_TX_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o._1_TX_EOF_DES_ADDR.Reg) +} + +// SLC._1_TO_EOF_BFR_DES_ADDR +func (o *SLC_Type) Set_1_TO_EOF_BFR_DES_ADDR(value uint32) { + volatile.StoreUint32(&o._1_TO_EOF_BFR_DES_ADDR.Reg, value) +} +func (o *SLC_Type) Get_1_TO_EOF_BFR_DES_ADDR() uint32 { + return volatile.LoadUint32(&o._1_TO_EOF_BFR_DES_ADDR.Reg) +} + +// SLC.AHB_TEST +func (o *SLC_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *SLC_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *SLC_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *SLC_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// SLC.SDIO_ST +func (o *SLC_Type) SetSDIO_ST_CMD_ST(value uint32) { + volatile.StoreUint32(&o.SDIO_ST.Reg, volatile.LoadUint32(&o.SDIO_ST.Reg)&^(0x7)|value) +} +func (o *SLC_Type) GetSDIO_ST_CMD_ST() uint32 { + return volatile.LoadUint32(&o.SDIO_ST.Reg) & 0x7 +} +func (o *SLC_Type) SetSDIO_ST_FUNC_ST(value uint32) { + volatile.StoreUint32(&o.SDIO_ST.Reg, volatile.LoadUint32(&o.SDIO_ST.Reg)&^(0xf0)|value<<4) +} +func (o *SLC_Type) GetSDIO_ST_FUNC_ST() uint32 { + return (volatile.LoadUint32(&o.SDIO_ST.Reg) & 0xf0) >> 4 +} +func (o *SLC_Type) SetSDIO_ST_SDIO_WAKEUP(value uint32) { + volatile.StoreUint32(&o.SDIO_ST.Reg, volatile.LoadUint32(&o.SDIO_ST.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) GetSDIO_ST_SDIO_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.SDIO_ST.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) SetSDIO_ST_BUS_ST(value uint32) { + volatile.StoreUint32(&o.SDIO_ST.Reg, volatile.LoadUint32(&o.SDIO_ST.Reg)&^(0x7000)|value<<12) +} +func (o *SLC_Type) GetSDIO_ST_BUS_ST() uint32 { + return (volatile.LoadUint32(&o.SDIO_ST.Reg) & 0x7000) >> 12 +} +func (o *SLC_Type) SetSDIO_ST_FUNC1_ACC_STATE(value uint32) { + volatile.StoreUint32(&o.SDIO_ST.Reg, volatile.LoadUint32(&o.SDIO_ST.Reg)&^(0x1f0000)|value<<16) +} +func (o *SLC_Type) GetSDIO_ST_FUNC1_ACC_STATE() uint32 { + return (volatile.LoadUint32(&o.SDIO_ST.Reg) & 0x1f0000) >> 16 +} +func (o *SLC_Type) SetSDIO_ST_FUNC2_ACC_STATE(value uint32) { + volatile.StoreUint32(&o.SDIO_ST.Reg, volatile.LoadUint32(&o.SDIO_ST.Reg)&^(0x1f000000)|value<<24) +} +func (o *SLC_Type) GetSDIO_ST_FUNC2_ACC_STATE() uint32 { + return (volatile.LoadUint32(&o.SDIO_ST.Reg) & 0x1f000000) >> 24 +} + +// SLC.RX_DSCR_CONF +func (o *SLC_Type) SetRX_DSCR_CONF_SLC0_TOKEN_NO_REPLACE(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC0_TOKEN_NO_REPLACE() uint32 { + return volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x1 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC0_INFOR_NO_REPLACE(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC0_INFOR_NO_REPLACE() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC0_RX_FILL_MODE(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC0_RX_FILL_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC0_RX_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC0_RX_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC0_RX_FILL_EN(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC0_RX_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC0_RD_RETRY_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0xffe0)|value<<5) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC0_RD_RETRY_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0xffe0) >> 5 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC1_TOKEN_NO_REPLACE(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC1_TOKEN_NO_REPLACE() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC1_INFOR_NO_REPLACE(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC1_INFOR_NO_REPLACE() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC1_RX_FILL_MODE(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC1_RX_FILL_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC1_RX_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC1_RX_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC1_RX_FILL_EN(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC1_RX_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) SetRX_DSCR_CONF_SLC1_RD_RETRY_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.RX_DSCR_CONF.Reg)&^(0xffe00000)|value<<21) +} +func (o *SLC_Type) GetRX_DSCR_CONF_SLC1_RD_RETRY_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.RX_DSCR_CONF.Reg) & 0xffe00000) >> 21 +} + +// SLC._0_TXLINK_DSCR +func (o *SLC_Type) Set_0_TXLINK_DSCR(value uint32) { + volatile.StoreUint32(&o._0_TXLINK_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_TXLINK_DSCR() uint32 { + return volatile.LoadUint32(&o._0_TXLINK_DSCR.Reg) +} + +// SLC._0_TXLINK_DSCR_BF0 +func (o *SLC_Type) Set_0_TXLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o._0_TXLINK_DSCR_BF0.Reg, value) +} +func (o *SLC_Type) Get_0_TXLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o._0_TXLINK_DSCR_BF0.Reg) +} + +// SLC._0_TXLINK_DSCR_BF1 +func (o *SLC_Type) Set_0_TXLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o._0_TXLINK_DSCR_BF1.Reg, value) +} +func (o *SLC_Type) Get_0_TXLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o._0_TXLINK_DSCR_BF1.Reg) +} + +// SLC._0_RXLINK_DSCR +func (o *SLC_Type) Set_0_RXLINK_DSCR(value uint32) { + volatile.StoreUint32(&o._0_RXLINK_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_RXLINK_DSCR() uint32 { + return volatile.LoadUint32(&o._0_RXLINK_DSCR.Reg) +} + +// SLC._0_RXLINK_DSCR_BF0 +func (o *SLC_Type) Set_0_RXLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o._0_RXLINK_DSCR_BF0.Reg, value) +} +func (o *SLC_Type) Get_0_RXLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o._0_RXLINK_DSCR_BF0.Reg) +} + +// SLC._0_RXLINK_DSCR_BF1 +func (o *SLC_Type) Set_0_RXLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o._0_RXLINK_DSCR_BF1.Reg, value) +} +func (o *SLC_Type) Get_0_RXLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o._0_RXLINK_DSCR_BF1.Reg) +} + +// SLC._1_TXLINK_DSCR +func (o *SLC_Type) Set_1_TXLINK_DSCR(value uint32) { + volatile.StoreUint32(&o._1_TXLINK_DSCR.Reg, value) +} +func (o *SLC_Type) Get_1_TXLINK_DSCR() uint32 { + return volatile.LoadUint32(&o._1_TXLINK_DSCR.Reg) +} + +// SLC._1_TXLINK_DSCR_BF0 +func (o *SLC_Type) Set_1_TXLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o._1_TXLINK_DSCR_BF0.Reg, value) +} +func (o *SLC_Type) Get_1_TXLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o._1_TXLINK_DSCR_BF0.Reg) +} + +// SLC._1_TXLINK_DSCR_BF1 +func (o *SLC_Type) Set_1_TXLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o._1_TXLINK_DSCR_BF1.Reg, value) +} +func (o *SLC_Type) Get_1_TXLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o._1_TXLINK_DSCR_BF1.Reg) +} + +// SLC._1_RXLINK_DSCR +func (o *SLC_Type) Set_1_RXLINK_DSCR(value uint32) { + volatile.StoreUint32(&o._1_RXLINK_DSCR.Reg, value) +} +func (o *SLC_Type) Get_1_RXLINK_DSCR() uint32 { + return volatile.LoadUint32(&o._1_RXLINK_DSCR.Reg) +} + +// SLC._1_RXLINK_DSCR_BF0 +func (o *SLC_Type) Set_1_RXLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o._1_RXLINK_DSCR_BF0.Reg, value) +} +func (o *SLC_Type) Get_1_RXLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o._1_RXLINK_DSCR_BF0.Reg) +} + +// SLC._1_RXLINK_DSCR_BF1 +func (o *SLC_Type) Set_1_RXLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o._1_RXLINK_DSCR_BF1.Reg, value) +} +func (o *SLC_Type) Get_1_RXLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o._1_RXLINK_DSCR_BF1.Reg) +} + +// SLC._0_TX_ERREOF_DES_ADDR +func (o *SLC_Type) Set_0_TX_ERREOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o._0_TX_ERREOF_DES_ADDR.Reg, value) +} +func (o *SLC_Type) Get_0_TX_ERREOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o._0_TX_ERREOF_DES_ADDR.Reg) +} + +// SLC._1_TX_ERREOF_DES_ADDR +func (o *SLC_Type) Set_1_TX_ERREOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o._1_TX_ERREOF_DES_ADDR.Reg, value) +} +func (o *SLC_Type) Get_1_TX_ERREOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o._1_TX_ERREOF_DES_ADDR.Reg) +} + +// SLC.TOKEN_LAT +func (o *SLC_Type) SetTOKEN_LAT_SLC0_TOKEN(value uint32) { + volatile.StoreUint32(&o.TOKEN_LAT.Reg, volatile.LoadUint32(&o.TOKEN_LAT.Reg)&^(0xfff)|value) +} +func (o *SLC_Type) GetTOKEN_LAT_SLC0_TOKEN() uint32 { + return volatile.LoadUint32(&o.TOKEN_LAT.Reg) & 0xfff +} +func (o *SLC_Type) SetTOKEN_LAT_SLC1_TOKEN(value uint32) { + volatile.StoreUint32(&o.TOKEN_LAT.Reg, volatile.LoadUint32(&o.TOKEN_LAT.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLC_Type) GetTOKEN_LAT_SLC1_TOKEN() uint32 { + return (volatile.LoadUint32(&o.TOKEN_LAT.Reg) & 0xfff0000) >> 16 +} + +// SLC.TX_DSCR_CONF +func (o *SLC_Type) SetTX_DSCR_CONF_WR_RETRY_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.TX_DSCR_CONF.Reg, volatile.LoadUint32(&o.TX_DSCR_CONF.Reg)&^(0x7ff)|value) +} +func (o *SLC_Type) GetTX_DSCR_CONF_WR_RETRY_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.TX_DSCR_CONF.Reg) & 0x7ff +} + +// SLC.CMD_INFOR0 +func (o *SLC_Type) SetCMD_INFOR0(value uint32) { + volatile.StoreUint32(&o.CMD_INFOR0.Reg, value) +} +func (o *SLC_Type) GetCMD_INFOR0() uint32 { + return volatile.LoadUint32(&o.CMD_INFOR0.Reg) +} + +// SLC.CMD_INFOR1 +func (o *SLC_Type) SetCMD_INFOR1(value uint32) { + volatile.StoreUint32(&o.CMD_INFOR1.Reg, value) +} +func (o *SLC_Type) GetCMD_INFOR1() uint32 { + return volatile.LoadUint32(&o.CMD_INFOR1.Reg) +} + +// SLC._0_LEN_CONF +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_LEN_WDATA(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0xfffff)|value) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_LEN_WDATA() uint32 { + return volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0xfffff +} +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_LEN_WR(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_LEN_WR() uint32 { + return (volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_LEN_INC(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_LEN_INC() uint32 { + return (volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_LEN_INC_MORE(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_LEN_INC_MORE() uint32 { + return (volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_RX_PACKET_LOAD_EN(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_RX_PACKET_LOAD_EN() uint32 { + return (volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_TX_PACKET_LOAD_EN(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_TX_PACKET_LOAD_EN() uint32 { + return (volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0x1000000) >> 24 +} +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_RX_GET_USED_DSCR(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_RX_GET_USED_DSCR() uint32 { + return (volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0x2000000) >> 25 +} +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_TX_GET_USED_DSCR(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_TX_GET_USED_DSCR() uint32 { + return (volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0x4000000) >> 26 +} +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_RX_NEW_PKT_IND(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_RX_NEW_PKT_IND() uint32 { + return (volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SLC_Type) Set_0_LEN_CONF_SLC0_TX_NEW_PKT_IND(value uint32) { + volatile.StoreUint32(&o._0_LEN_CONF.Reg, volatile.LoadUint32(&o._0_LEN_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SLC_Type) Get_0_LEN_CONF_SLC0_TX_NEW_PKT_IND() uint32 { + return (volatile.LoadUint32(&o._0_LEN_CONF.Reg) & 0x10000000) >> 28 +} + +// SLC._0_LENGTH +func (o *SLC_Type) Set_0_LENGTH_SLC0_LEN(value uint32) { + volatile.StoreUint32(&o._0_LENGTH.Reg, volatile.LoadUint32(&o._0_LENGTH.Reg)&^(0xfffff)|value) +} +func (o *SLC_Type) Get_0_LENGTH_SLC0_LEN() uint32 { + return volatile.LoadUint32(&o._0_LENGTH.Reg) & 0xfffff +} + +// SLC._0_TXPKT_H_DSCR +func (o *SLC_Type) Set_0_TXPKT_H_DSCR(value uint32) { + volatile.StoreUint32(&o._0_TXPKT_H_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_TXPKT_H_DSCR() uint32 { + return volatile.LoadUint32(&o._0_TXPKT_H_DSCR.Reg) +} + +// SLC._0_TXPKT_E_DSCR +func (o *SLC_Type) Set_0_TXPKT_E_DSCR(value uint32) { + volatile.StoreUint32(&o._0_TXPKT_E_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_TXPKT_E_DSCR() uint32 { + return volatile.LoadUint32(&o._0_TXPKT_E_DSCR.Reg) +} + +// SLC._0_RXPKT_H_DSCR +func (o *SLC_Type) Set_0_RXPKT_H_DSCR(value uint32) { + volatile.StoreUint32(&o._0_RXPKT_H_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_RXPKT_H_DSCR() uint32 { + return volatile.LoadUint32(&o._0_RXPKT_H_DSCR.Reg) +} + +// SLC._0_RXPKT_E_DSCR +func (o *SLC_Type) Set_0_RXPKT_E_DSCR(value uint32) { + volatile.StoreUint32(&o._0_RXPKT_E_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_RXPKT_E_DSCR() uint32 { + return volatile.LoadUint32(&o._0_RXPKT_E_DSCR.Reg) +} + +// SLC._0_TXPKTU_H_DSCR +func (o *SLC_Type) Set_0_TXPKTU_H_DSCR(value uint32) { + volatile.StoreUint32(&o._0_TXPKTU_H_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_TXPKTU_H_DSCR() uint32 { + return volatile.LoadUint32(&o._0_TXPKTU_H_DSCR.Reg) +} + +// SLC._0_TXPKTU_E_DSCR +func (o *SLC_Type) Set_0_TXPKTU_E_DSCR(value uint32) { + volatile.StoreUint32(&o._0_TXPKTU_E_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_TXPKTU_E_DSCR() uint32 { + return volatile.LoadUint32(&o._0_TXPKTU_E_DSCR.Reg) +} + +// SLC._0_RXPKTU_H_DSCR +func (o *SLC_Type) Set_0_RXPKTU_H_DSCR(value uint32) { + volatile.StoreUint32(&o._0_RXPKTU_H_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_RXPKTU_H_DSCR() uint32 { + return volatile.LoadUint32(&o._0_RXPKTU_H_DSCR.Reg) +} + +// SLC._0_RXPKTU_E_DSCR +func (o *SLC_Type) Set_0_RXPKTU_E_DSCR(value uint32) { + volatile.StoreUint32(&o._0_RXPKTU_E_DSCR.Reg, value) +} +func (o *SLC_Type) Get_0_RXPKTU_E_DSCR() uint32 { + return volatile.LoadUint32(&o._0_RXPKTU_E_DSCR.Reg) +} + +// SLC.SEQ_POSITION +func (o *SLC_Type) SetSEQ_POSITION_SLC0_SEQ_POSITION(value uint32) { + volatile.StoreUint32(&o.SEQ_POSITION.Reg, volatile.LoadUint32(&o.SEQ_POSITION.Reg)&^(0xff)|value) +} +func (o *SLC_Type) GetSEQ_POSITION_SLC0_SEQ_POSITION() uint32 { + return volatile.LoadUint32(&o.SEQ_POSITION.Reg) & 0xff +} +func (o *SLC_Type) SetSEQ_POSITION_SLC1_SEQ_POSITION(value uint32) { + volatile.StoreUint32(&o.SEQ_POSITION.Reg, volatile.LoadUint32(&o.SEQ_POSITION.Reg)&^(0xff00)|value<<8) +} +func (o *SLC_Type) GetSEQ_POSITION_SLC1_SEQ_POSITION() uint32 { + return (volatile.LoadUint32(&o.SEQ_POSITION.Reg) & 0xff00) >> 8 +} + +// SLC._0_DSCR_REC_CONF +func (o *SLC_Type) Set_0_DSCR_REC_CONF_SLC0_RX_DSCR_REC_LIM(value uint32) { + volatile.StoreUint32(&o._0_DSCR_REC_CONF.Reg, volatile.LoadUint32(&o._0_DSCR_REC_CONF.Reg)&^(0x3ff)|value) +} +func (o *SLC_Type) Get_0_DSCR_REC_CONF_SLC0_RX_DSCR_REC_LIM() uint32 { + return volatile.LoadUint32(&o._0_DSCR_REC_CONF.Reg) & 0x3ff +} + +// SLC.SDIO_CRC_ST0 +func (o *SLC_Type) SetSDIO_CRC_ST0_DAT0_CRC_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.SDIO_CRC_ST0.Reg, volatile.LoadUint32(&o.SDIO_CRC_ST0.Reg)&^(0xff)|value) +} +func (o *SLC_Type) GetSDIO_CRC_ST0_DAT0_CRC_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.SDIO_CRC_ST0.Reg) & 0xff +} +func (o *SLC_Type) SetSDIO_CRC_ST0_DAT1_CRC_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.SDIO_CRC_ST0.Reg, volatile.LoadUint32(&o.SDIO_CRC_ST0.Reg)&^(0xff00)|value<<8) +} +func (o *SLC_Type) GetSDIO_CRC_ST0_DAT1_CRC_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.SDIO_CRC_ST0.Reg) & 0xff00) >> 8 +} +func (o *SLC_Type) SetSDIO_CRC_ST0_DAT2_CRC_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.SDIO_CRC_ST0.Reg, volatile.LoadUint32(&o.SDIO_CRC_ST0.Reg)&^(0xff0000)|value<<16) +} +func (o *SLC_Type) GetSDIO_CRC_ST0_DAT2_CRC_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.SDIO_CRC_ST0.Reg) & 0xff0000) >> 16 +} +func (o *SLC_Type) SetSDIO_CRC_ST0_DAT3_CRC_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.SDIO_CRC_ST0.Reg, volatile.LoadUint32(&o.SDIO_CRC_ST0.Reg)&^(0xff000000)|value<<24) +} +func (o *SLC_Type) GetSDIO_CRC_ST0_DAT3_CRC_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.SDIO_CRC_ST0.Reg) & 0xff000000) >> 24 +} + +// SLC.SDIO_CRC_ST1 +func (o *SLC_Type) SetSDIO_CRC_ST1_CMD_CRC_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.SDIO_CRC_ST1.Reg, volatile.LoadUint32(&o.SDIO_CRC_ST1.Reg)&^(0xff)|value) +} +func (o *SLC_Type) GetSDIO_CRC_ST1_CMD_CRC_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.SDIO_CRC_ST1.Reg) & 0xff +} +func (o *SLC_Type) SetSDIO_CRC_ST1_ERR_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.SDIO_CRC_ST1.Reg, volatile.LoadUint32(&o.SDIO_CRC_ST1.Reg)&^(0x80000000)|value<<31) +} +func (o *SLC_Type) GetSDIO_CRC_ST1_ERR_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.SDIO_CRC_ST1.Reg) & 0x80000000) >> 31 +} + +// SLC._0_EOF_START_DES +func (o *SLC_Type) Set_0_EOF_START_DES(value uint32) { + volatile.StoreUint32(&o._0_EOF_START_DES.Reg, value) +} +func (o *SLC_Type) Get_0_EOF_START_DES() uint32 { + return volatile.LoadUint32(&o._0_EOF_START_DES.Reg) +} + +// SLC._0_PUSH_DSCR_ADDR +func (o *SLC_Type) Set_0_PUSH_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o._0_PUSH_DSCR_ADDR.Reg, value) +} +func (o *SLC_Type) Get_0_PUSH_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o._0_PUSH_DSCR_ADDR.Reg) +} + +// SLC._0_DONE_DSCR_ADDR +func (o *SLC_Type) Set_0_DONE_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o._0_DONE_DSCR_ADDR.Reg, value) +} +func (o *SLC_Type) Get_0_DONE_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o._0_DONE_DSCR_ADDR.Reg) +} + +// SLC._0_SUB_START_DES +func (o *SLC_Type) Set_0_SUB_START_DES(value uint32) { + volatile.StoreUint32(&o._0_SUB_START_DES.Reg, value) +} +func (o *SLC_Type) Get_0_SUB_START_DES() uint32 { + return volatile.LoadUint32(&o._0_SUB_START_DES.Reg) +} + +// SLC._0_DSCR_CNT +func (o *SLC_Type) Set_0_DSCR_CNT_SLC0_RX_DSCR_CNT_LAT(value uint32) { + volatile.StoreUint32(&o._0_DSCR_CNT.Reg, volatile.LoadUint32(&o._0_DSCR_CNT.Reg)&^(0x3ff)|value) +} +func (o *SLC_Type) Get_0_DSCR_CNT_SLC0_RX_DSCR_CNT_LAT() uint32 { + return volatile.LoadUint32(&o._0_DSCR_CNT.Reg) & 0x3ff +} +func (o *SLC_Type) Set_0_DSCR_CNT_SLC0_RX_GET_EOF_OCC(value uint32) { + volatile.StoreUint32(&o._0_DSCR_CNT.Reg, volatile.LoadUint32(&o._0_DSCR_CNT.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_0_DSCR_CNT_SLC0_RX_GET_EOF_OCC() uint32 { + return (volatile.LoadUint32(&o._0_DSCR_CNT.Reg) & 0x10000) >> 16 +} + +// SLC._0_LEN_LIM_CONF +func (o *SLC_Type) Set_0_LEN_LIM_CONF_SLC0_LEN_LIM(value uint32) { + volatile.StoreUint32(&o._0_LEN_LIM_CONF.Reg, volatile.LoadUint32(&o._0_LEN_LIM_CONF.Reg)&^(0xfffff)|value) +} +func (o *SLC_Type) Get_0_LEN_LIM_CONF_SLC0_LEN_LIM() uint32 { + return volatile.LoadUint32(&o._0_LEN_LIM_CONF.Reg) & 0xfffff +} + +// SLC._0INT_ST1 +func (o *SLC_Type) Set_0INT_ST1_FRHOST_BIT0_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_0INT_ST1_FRHOST_BIT0_INT_ST1() uint32 { + return volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x1 +} +func (o *SLC_Type) Set_0INT_ST1_FRHOST_BIT1_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_0INT_ST1_FRHOST_BIT1_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_0INT_ST1_FRHOST_BIT2_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_0INT_ST1_FRHOST_BIT2_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_0INT_ST1_FRHOST_BIT3_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_0INT_ST1_FRHOST_BIT3_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_0INT_ST1_FRHOST_BIT4_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_0INT_ST1_FRHOST_BIT4_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_0INT_ST1_FRHOST_BIT5_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_0INT_ST1_FRHOST_BIT5_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_0INT_ST1_FRHOST_BIT6_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_0INT_ST1_FRHOST_BIT6_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_0INT_ST1_FRHOST_BIT7_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_0INT_ST1_FRHOST_BIT7_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_RX_START_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_RX_START_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TX_START_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TX_START_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_RX_UDF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_RX_UDF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TX_OVF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TX_OVF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TOKEN0_1TO0_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TOKEN0_1TO0_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TOKEN1_1TO0_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TOKEN1_1TO0_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TX_DONE_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TX_DONE_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TX_SUC_EOF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TX_SUC_EOF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_RX_DONE_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_RX_DONE_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_RX_EOF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_RX_EOF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TOHOST_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TOHOST_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TX_DSCR_ERR_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TX_DSCR_ERR_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_RX_DSCR_ERR_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_RX_DSCR_ERR_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TX_DSCR_EMPTY_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TX_DSCR_EMPTY_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_HOST_RD_ACK_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_HOST_RD_ACK_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_WR_RETRY_DONE_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_WR_RETRY_DONE_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_TX_ERR_EOF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_TX_ERR_EOF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x1000000) >> 24 +} +func (o *SLC_Type) Set_0INT_ST1_CMD_DTC_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x2000000)|value<<25) +} +func (o *SLC_Type) Get_0INT_ST1_CMD_DTC_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x2000000) >> 25 +} +func (o *SLC_Type) Set_0INT_ST1_SLC0_RX_QUICK_EOF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._0INT_ST1.Reg, volatile.LoadUint32(&o._0INT_ST1.Reg)&^(0x4000000)|value<<26) +} +func (o *SLC_Type) Get_0INT_ST1_SLC0_RX_QUICK_EOF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._0INT_ST1.Reg) & 0x4000000) >> 26 +} + +// SLC._0INT_ENA1 +func (o *SLC_Type) Set_0INT_ENA1_FRHOST_BIT0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_0INT_ENA1_FRHOST_BIT0_INT_ENA1() uint32 { + return volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x1 +} +func (o *SLC_Type) Set_0INT_ENA1_FRHOST_BIT1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_0INT_ENA1_FRHOST_BIT1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_0INT_ENA1_FRHOST_BIT2_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_0INT_ENA1_FRHOST_BIT2_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_0INT_ENA1_FRHOST_BIT3_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_0INT_ENA1_FRHOST_BIT3_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_0INT_ENA1_FRHOST_BIT4_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_0INT_ENA1_FRHOST_BIT4_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_0INT_ENA1_FRHOST_BIT5_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_0INT_ENA1_FRHOST_BIT5_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_0INT_ENA1_FRHOST_BIT6_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_0INT_ENA1_FRHOST_BIT6_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_0INT_ENA1_FRHOST_BIT7_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_0INT_ENA1_FRHOST_BIT7_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_RX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_RX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_RX_UDF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_RX_UDF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TX_OVF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TX_OVF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TX_DONE_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TX_DONE_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TX_SUC_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TX_SUC_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_RX_DONE_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_RX_DONE_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_RX_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_RX_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TOHOST_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TOHOST_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TX_DSCR_ERR_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TX_DSCR_ERR_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_RX_DSCR_ERR_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_RX_DSCR_ERR_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TX_DSCR_EMPTY_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TX_DSCR_EMPTY_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_HOST_RD_ACK_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_HOST_RD_ACK_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_WR_RETRY_DONE_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_WR_RETRY_DONE_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_TX_ERR_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_TX_ERR_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x1000000) >> 24 +} +func (o *SLC_Type) Set_0INT_ENA1_CMD_DTC_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x2000000)|value<<25) +} +func (o *SLC_Type) Get_0INT_ENA1_CMD_DTC_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x2000000) >> 25 +} +func (o *SLC_Type) Set_0INT_ENA1_SLC0_RX_QUICK_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._0INT_ENA1.Reg, volatile.LoadUint32(&o._0INT_ENA1.Reg)&^(0x4000000)|value<<26) +} +func (o *SLC_Type) Get_0INT_ENA1_SLC0_RX_QUICK_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._0INT_ENA1.Reg) & 0x4000000) >> 26 +} + +// SLC._1INT_ST1 +func (o *SLC_Type) Set_1INT_ST1_FRHOST_BIT8_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_1INT_ST1_FRHOST_BIT8_INT_ST1() uint32 { + return volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x1 +} +func (o *SLC_Type) Set_1INT_ST1_FRHOST_BIT9_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_1INT_ST1_FRHOST_BIT9_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_1INT_ST1_FRHOST_BIT10_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_1INT_ST1_FRHOST_BIT10_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_1INT_ST1_FRHOST_BIT11_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_1INT_ST1_FRHOST_BIT11_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_1INT_ST1_FRHOST_BIT12_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_1INT_ST1_FRHOST_BIT12_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_1INT_ST1_FRHOST_BIT13_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_1INT_ST1_FRHOST_BIT13_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_1INT_ST1_FRHOST_BIT14_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_1INT_ST1_FRHOST_BIT14_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_1INT_ST1_FRHOST_BIT15_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_1INT_ST1_FRHOST_BIT15_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_RX_START_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_RX_START_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TX_START_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TX_START_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_RX_UDF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_RX_UDF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TX_OVF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TX_OVF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TOKEN0_1TO0_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TOKEN0_1TO0_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TOKEN1_1TO0_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TOKEN1_1TO0_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TX_DONE_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TX_DONE_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TX_SUC_EOF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TX_SUC_EOF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_RX_DONE_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_RX_DONE_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_RX_EOF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_RX_EOF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TOHOST_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TOHOST_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TX_DSCR_ERR_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TX_DSCR_ERR_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_RX_DSCR_ERR_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_RX_DSCR_ERR_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TX_DSCR_EMPTY_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TX_DSCR_EMPTY_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_HOST_RD_ACK_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_HOST_RD_ACK_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_WR_RETRY_DONE_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_WR_RETRY_DONE_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_1INT_ST1_SLC1_TX_ERR_EOF_INT_ST1(value uint32) { + volatile.StoreUint32(&o._1INT_ST1.Reg, volatile.LoadUint32(&o._1INT_ST1.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_1INT_ST1_SLC1_TX_ERR_EOF_INT_ST1() uint32 { + return (volatile.LoadUint32(&o._1INT_ST1.Reg) & 0x1000000) >> 24 +} + +// SLC._1INT_ENA1 +func (o *SLC_Type) Set_1INT_ENA1_FRHOST_BIT8_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x1)|value) +} +func (o *SLC_Type) Get_1INT_ENA1_FRHOST_BIT8_INT_ENA1() uint32 { + return volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x1 +} +func (o *SLC_Type) Set_1INT_ENA1_FRHOST_BIT9_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) Get_1INT_ENA1_FRHOST_BIT9_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) Set_1INT_ENA1_FRHOST_BIT10_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) Get_1INT_ENA1_FRHOST_BIT10_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) Set_1INT_ENA1_FRHOST_BIT11_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) Get_1INT_ENA1_FRHOST_BIT11_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) Set_1INT_ENA1_FRHOST_BIT12_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) Get_1INT_ENA1_FRHOST_BIT12_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) Set_1INT_ENA1_FRHOST_BIT13_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) Get_1INT_ENA1_FRHOST_BIT13_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) Set_1INT_ENA1_FRHOST_BIT14_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) Get_1INT_ENA1_FRHOST_BIT14_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) Set_1INT_ENA1_FRHOST_BIT15_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) Get_1INT_ENA1_FRHOST_BIT15_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_RX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_RX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_RX_UDF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_RX_UDF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TX_OVF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TX_OVF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TX_DONE_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TX_DONE_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TX_SUC_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TX_SUC_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_RX_DONE_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_RX_DONE_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_RX_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_RX_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TOHOST_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TOHOST_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TX_DSCR_ERR_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TX_DSCR_ERR_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_RX_DSCR_ERR_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_RX_DSCR_ERR_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TX_DSCR_EMPTY_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TX_DSCR_EMPTY_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_HOST_RD_ACK_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x400000)|value<<22) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_HOST_RD_ACK_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x400000) >> 22 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_WR_RETRY_DONE_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x800000)|value<<23) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_WR_RETRY_DONE_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x800000) >> 23 +} +func (o *SLC_Type) Set_1INT_ENA1_SLC1_TX_ERR_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o._1INT_ENA1.Reg, volatile.LoadUint32(&o._1INT_ENA1.Reg)&^(0x1000000)|value<<24) +} +func (o *SLC_Type) Get_1INT_ENA1_SLC1_TX_ERR_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o._1INT_ENA1.Reg) & 0x1000000) >> 24 +} + +// SLC.DATE +func (o *SLC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *SLC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// SLC.ID +func (o *SLC_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, value) +} +func (o *SLC_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) +} + +// SLCHOST Peripheral +type SLCHOST_Type struct { + _ [16]byte + HOST_SLCHOST_FUNC2_0 volatile.Register32 // 0x10 + HOST_SLCHOST_FUNC2_1 volatile.Register32 // 0x14 + _ [8]byte + HOST_SLCHOST_FUNC2_2 volatile.Register32 // 0x20 + _ [16]byte + HOST_SLCHOST_GPIO_STATUS0 volatile.Register32 // 0x34 + HOST_SLCHOST_GPIO_STATUS1 volatile.Register32 // 0x38 + HOST_SLCHOST_GPIO_IN0 volatile.Register32 // 0x3C + HOST_SLCHOST_GPIO_IN1 volatile.Register32 // 0x40 + HOST_SLC0HOST_TOKEN_RDATA volatile.Register32 // 0x44 + HOST_SLC0_HOST_PF volatile.Register32 // 0x48 + HOST_SLC1_HOST_PF volatile.Register32 // 0x4C + HOST_SLC0HOST_INT_RAW volatile.Register32 // 0x50 + HOST_SLC1HOST_INT_RAW volatile.Register32 // 0x54 + HOST_SLC0HOST_INT_ST volatile.Register32 // 0x58 + HOST_SLC1HOST_INT_ST volatile.Register32 // 0x5C + HOST_SLCHOST_PKT_LEN volatile.Register32 // 0x60 + HOST_SLCHOST_STATE_W0 volatile.Register32 // 0x64 + HOST_SLCHOST_STATE_W1 volatile.Register32 // 0x68 + HOST_SLCHOST_CONF_W0 volatile.Register32 // 0x6C + HOST_SLCHOST_CONF_W1 volatile.Register32 // 0x70 + HOST_SLCHOST_CONF_W2 volatile.Register32 // 0x74 + HOST_SLCHOST_CONF_W3 volatile.Register32 // 0x78 + HOST_SLCHOST_CONF_W4 volatile.Register32 // 0x7C + HOST_SLCHOST_CONF_W5 volatile.Register32 // 0x80 + HOST_SLCHOST_WIN_CMD volatile.Register32 // 0x84 + HOST_SLCHOST_CONF_W6 volatile.Register32 // 0x88 + HOST_SLCHOST_CONF_W7 volatile.Register32 // 0x8C + HOST_SLCHOST_PKT_LEN0 volatile.Register32 // 0x90 + HOST_SLCHOST_PKT_LEN1 volatile.Register32 // 0x94 + HOST_SLCHOST_PKT_LEN2 volatile.Register32 // 0x98 + HOST_SLCHOST_CONF_W8 volatile.Register32 // 0x9C + HOST_SLCHOST_CONF_W9 volatile.Register32 // 0xA0 + HOST_SLCHOST_CONF_W10 volatile.Register32 // 0xA4 + HOST_SLCHOST_CONF_W11 volatile.Register32 // 0xA8 + HOST_SLCHOST_CONF_W12 volatile.Register32 // 0xAC + HOST_SLCHOST_CONF_W13 volatile.Register32 // 0xB0 + HOST_SLCHOST_CONF_W14 volatile.Register32 // 0xB4 + HOST_SLCHOST_CONF_W15 volatile.Register32 // 0xB8 + HOST_SLCHOST_CHECK_SUM0 volatile.Register32 // 0xBC + HOST_SLCHOST_CHECK_SUM1 volatile.Register32 // 0xC0 + HOST_SLC1HOST_TOKEN_RDATA volatile.Register32 // 0xC4 + HOST_SLC0HOST_TOKEN_WDATA volatile.Register32 // 0xC8 + HOST_SLC1HOST_TOKEN_WDATA volatile.Register32 // 0xCC + HOST_SLCHOST_TOKEN_CON volatile.Register32 // 0xD0 + HOST_SLC0HOST_INT_CLR volatile.Register32 // 0xD4 + HOST_SLC1HOST_INT_CLR volatile.Register32 // 0xD8 + HOST_SLC0HOST_FUNC1_INT_ENA volatile.Register32 // 0xDC + HOST_SLC1HOST_FUNC1_INT_ENA volatile.Register32 // 0xE0 + HOST_SLC0HOST_FUNC2_INT_ENA volatile.Register32 // 0xE4 + HOST_SLC1HOST_FUNC2_INT_ENA volatile.Register32 // 0xE8 + HOST_SLC0HOST_INT_ENA volatile.Register32 // 0xEC + HOST_SLC1HOST_INT_ENA volatile.Register32 // 0xF0 + HOST_SLC0HOST_RX_INFOR volatile.Register32 // 0xF4 + HOST_SLC1HOST_RX_INFOR volatile.Register32 // 0xF8 + HOST_SLC0HOST_LEN_WD volatile.Register32 // 0xFC + HOST_SLC_APBWIN_WDATA volatile.Register32 // 0x100 + HOST_SLC_APBWIN_CONF volatile.Register32 // 0x104 + HOST_SLC_APBWIN_RDATA volatile.Register32 // 0x108 + HOST_SLCHOST_RDCLR0 volatile.Register32 // 0x10C + HOST_SLCHOST_RDCLR1 volatile.Register32 // 0x110 + HOST_SLC0HOST_INT_ENA1 volatile.Register32 // 0x114 + HOST_SLC1HOST_INT_ENA1 volatile.Register32 // 0x118 + _ [92]byte + HOST_SLCHOSTDATE volatile.Register32 // 0x178 + HOST_SLCHOSTID volatile.Register32 // 0x17C + _ [112]byte + HOST_SLCHOST_CONF volatile.Register32 // 0x1F0 + HOST_SLCHOST_INF_ST volatile.Register32 // 0x1F4 +} + +// SLCHOST.HOST_SLCHOST_FUNC2_0 +func (o *SLCHOST_Type) SetHOST_SLCHOST_FUNC2_0_HOST_SLC_FUNC2_INT(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_FUNC2_0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_FUNC2_0.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_FUNC2_0_HOST_SLC_FUNC2_INT() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_FUNC2_0.Reg) & 0x1000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_FUNC2_1 +func (o *SLCHOST_Type) SetHOST_SLCHOST_FUNC2_1_HOST_SLC_FUNC2_INT_EN(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_FUNC2_1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_FUNC2_1.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_FUNC2_1_HOST_SLC_FUNC2_INT_EN() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_FUNC2_1.Reg) & 0x1 +} + +// SLCHOST.HOST_SLCHOST_FUNC2_2 +func (o *SLCHOST_Type) SetHOST_SLCHOST_FUNC2_2_HOST_SLC_FUNC1_MDSTAT(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_FUNC2_2.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_FUNC2_2.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_FUNC2_2_HOST_SLC_FUNC1_MDSTAT() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_FUNC2_2.Reg) & 0x1 +} + +// SLCHOST.HOST_SLCHOST_GPIO_STATUS0 +func (o *SLCHOST_Type) SetHOST_SLCHOST_GPIO_STATUS0(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_GPIO_STATUS0.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_GPIO_STATUS0() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_GPIO_STATUS0.Reg) +} + +// SLCHOST.HOST_SLCHOST_GPIO_STATUS1 +func (o *SLCHOST_Type) SetHOST_SLCHOST_GPIO_STATUS1_HOST_GPIO_SDIO_INT1(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_GPIO_STATUS1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_GPIO_STATUS1.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_GPIO_STATUS1_HOST_GPIO_SDIO_INT1() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_GPIO_STATUS1.Reg) & 0xff +} + +// SLCHOST.HOST_SLCHOST_GPIO_IN0 +func (o *SLCHOST_Type) SetHOST_SLCHOST_GPIO_IN0(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_GPIO_IN0.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_GPIO_IN0() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_GPIO_IN0.Reg) +} + +// SLCHOST.HOST_SLCHOST_GPIO_IN1 +func (o *SLCHOST_Type) SetHOST_SLCHOST_GPIO_IN1_HOST_GPIO_SDIO_IN1(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_GPIO_IN1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_GPIO_IN1.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_GPIO_IN1_HOST_GPIO_SDIO_IN1() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_GPIO_IN1.Reg) & 0xff +} + +// SLCHOST.HOST_SLC0HOST_TOKEN_RDATA +func (o *SLCHOST_Type) SetHOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_TOKEN0(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg)&^(0xfff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_TOKEN0() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg) & 0xfff +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_RX_PF_VALID(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_RX_PF_VALID() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_TOKEN_RDATA_HOST_HOSTSLC0_TOKEN1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_TOKEN_RDATA_HOST_HOSTSLC0_TOKEN1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg) & 0xfff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_RX_PF_EOF(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg)&^(0xf0000000)|value<<28) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_RX_PF_EOF() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_RDATA.Reg) & 0xf0000000) >> 28 +} + +// SLCHOST.HOST_SLC0_HOST_PF +func (o *SLCHOST_Type) SetHOST_SLC0_HOST_PF(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0_HOST_PF.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLC0_HOST_PF() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0_HOST_PF.Reg) +} + +// SLCHOST.HOST_SLC1_HOST_PF +func (o *SLCHOST_Type) SetHOST_SLC1_HOST_PF(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1_HOST_PF.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLC1_HOST_PF() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1_HOST_PF.Reg) +} + +// SLCHOST.HOST_SLC0HOST_INT_RAW +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_0TO1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_0TO1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_0TO1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_0TO1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_SOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_SOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TX_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_TX_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_PF_VALID_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_PF_VALID_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_NEW_PACKET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_NEW_PACKET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_SLC0_HOST_RD_RETRY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_SLC0_HOST_RD_RETRY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_RAW_HOST_GPIO_SDIO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_RAW_HOST_GPIO_SDIO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_RAW.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC1HOST_INT_RAW +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_0TO1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_0TO1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_0TO1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_0TO1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_SOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_SOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TX_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_TX_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_PF_VALID_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_PF_VALID_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_HOST_RD_RETRY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_HOST_RD_RETRY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_RAW_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_RAW_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_RAW.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC0HOST_INT_ST +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT0_INT_ST() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT4_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT5_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT6_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT7_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_0TO1_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_0TO1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_0TO1_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_0TO1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_SOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_SOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0HOST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0HOST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_RX_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_RX_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_TX_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_TX_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_RX_PF_VALID_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_RX_PF_VALID_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_RX_NEW_PACKET_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_RX_NEW_PACKET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_SLC0_HOST_RD_RETRY_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_SLC0_HOST_RD_RETRY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ST_HOST_GPIO_SDIO_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ST_HOST_GPIO_SDIO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ST.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC1HOST_INT_ST +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT0_INT_ST() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT4_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT5_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT6_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT7_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_0TO1_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_0TO1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_0TO1_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_0TO1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_SOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_SOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1HOST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1HOST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_RX_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_RX_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_TX_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_TX_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_RX_PF_VALID_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_RX_PF_VALID_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_HOST_RD_RETRY_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_HOST_RD_RETRY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ST_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ST_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ST.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLCHOST_PKT_LEN +func (o *SLCHOST_Type) SetHOST_SLCHOST_PKT_LEN_HOST_HOSTSLC0_LEN(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_PKT_LEN.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_PKT_LEN_HOST_HOSTSLC0_LEN() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN.Reg) & 0xfffff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_PKT_LEN_HOST_HOSTSLC0_LEN_CHECK(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_PKT_LEN.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN.Reg)&^(0xfff00000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_PKT_LEN_HOST_HOSTSLC0_LEN_CHECK() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN.Reg) & 0xfff00000) >> 20 +} + +// SLCHOST.HOST_SLCHOST_STATE_W0 +func (o *SLCHOST_Type) SetHOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE0(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_STATE_W0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W0.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE0() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W0.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE1(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_STATE_W0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W0.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W0.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE2(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_STATE_W0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W0.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE2() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W0.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE3(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_STATE_W0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W0.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE3() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W0.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_STATE_W1 +func (o *SLCHOST_Type) SetHOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE4(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_STATE_W1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W1.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE4() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W1.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE5(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_STATE_W1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W1.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE5() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W1.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE6(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_STATE_W1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE6() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W1.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE7(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_STATE_W1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W1.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE7() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_STATE_W1.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W0 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF0(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W0.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF0() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W0.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF1(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W0.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W0.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF2(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W0.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF2() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W0.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF3(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W0.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF3() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W0.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W1 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF4(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W1.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF4() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W1.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF5(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W1.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF5() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W1.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF6(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF6() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W1.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF7(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W1.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF7() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W1.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W2 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF8(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W2.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W2.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF8() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W2.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF9(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W2.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W2.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF9() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W2.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF10(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W2.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W2.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF10() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W2.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF11(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W2.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W2.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF11() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W2.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W3 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF12(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W3.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W3.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF12() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W3.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF13(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W3.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W3.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF13() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W3.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF14(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W3.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W3.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF14() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W3.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF15(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W3.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W3.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF15() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W3.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W4 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF16(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W4.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W4.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF16() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W4.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF17(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W4.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W4.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF17() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W4.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF18(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W4.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W4.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF18() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W4.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF19(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W4.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W4.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF19() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W4.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W5 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF20(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W5.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W5.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF20() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W5.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF21(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W5.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W5.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF21() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W5.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF22(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W5.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W5.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF22() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W5.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF23(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W5.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W5.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF23() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W5.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W6 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF24(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W6.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W6.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF24() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W6.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF25(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W6.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W6.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF25() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W6.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF26(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W6.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W6.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF26() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W6.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF27(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W6.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W6.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF27() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W6.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W7 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF28(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W7.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W7.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF28() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W7.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF29(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W7.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W7.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF29() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W7.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF30(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W7.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W7.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF30() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W7.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF31(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W7.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W7.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF31() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W7.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_PKT_LEN0 +func (o *SLCHOST_Type) SetHOST_SLCHOST_PKT_LEN0_HOST_HOSTSLC0_LEN0(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_PKT_LEN0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN0.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_PKT_LEN0_HOST_HOSTSLC0_LEN0() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN0.Reg) & 0xfffff +} + +// SLCHOST.HOST_SLCHOST_PKT_LEN1 +func (o *SLCHOST_Type) SetHOST_SLCHOST_PKT_LEN1_HOST_HOSTSLC0_LEN1(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_PKT_LEN1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN1.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_PKT_LEN1_HOST_HOSTSLC0_LEN1() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN1.Reg) & 0xfffff +} + +// SLCHOST.HOST_SLCHOST_PKT_LEN2 +func (o *SLCHOST_Type) SetHOST_SLCHOST_PKT_LEN2_HOST_HOSTSLC0_LEN2(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_PKT_LEN2.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN2.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_PKT_LEN2_HOST_HOSTSLC0_LEN2() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_PKT_LEN2.Reg) & 0xfffff +} + +// SLCHOST.HOST_SLCHOST_CONF_W8 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF32(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W8.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W8.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF32() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W8.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF33(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W8.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W8.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF33() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W8.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF34(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W8.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W8.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF34() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W8.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF35(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W8.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W8.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF35() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W8.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W9 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF36(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W9.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W9.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF36() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W9.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF37(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W9.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W9.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF37() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W9.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF38(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W9.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W9.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF38() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W9.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF39(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W9.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W9.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF39() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W9.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W10 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF40(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W10.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W10.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF40() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W10.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF41(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W10.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W10.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF41() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W10.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF42(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W10.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W10.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF42() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W10.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF43(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W10.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W10.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF43() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W10.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W11 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF44(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W11.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W11.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF44() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W11.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF45(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W11.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W11.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF45() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W11.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF46(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W11.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W11.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF46() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W11.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF47(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W11.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W11.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF47() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W11.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W12 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF48(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W12.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W12.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF48() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W12.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF49(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W12.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W12.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF49() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W12.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF50(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W12.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W12.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF50() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W12.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF51(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W12.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W12.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF51() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W12.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W13 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF52(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W13.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W13.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF52() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W13.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF53(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W13.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W13.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF53() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W13.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF54(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W13.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W13.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF54() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W13.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF55(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W13.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W13.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF55() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W13.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W14 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF56(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W14.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W14.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF56() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W14.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF57(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W14.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W14.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF57() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W14.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF58(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W14.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W14.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF58() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W14.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF59(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W14.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W14.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF59() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W14.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CONF_W15 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF60(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W15.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W15.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF60() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W15.Reg) & 0xff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF61(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W15.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W15.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF61() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W15.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF62(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W15.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W15.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF62() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W15.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF63(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF_W15.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W15.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF63() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF_W15.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.HOST_SLCHOST_CHECK_SUM0 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CHECK_SUM0(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CHECK_SUM0.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CHECK_SUM0() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CHECK_SUM0.Reg) +} + +// SLCHOST.HOST_SLCHOST_CHECK_SUM1 +func (o *SLCHOST_Type) SetHOST_SLCHOST_CHECK_SUM1(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CHECK_SUM1.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CHECK_SUM1() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CHECK_SUM1.Reg) +} + +// SLCHOST.HOST_SLC1HOST_TOKEN_RDATA +func (o *SLCHOST_Type) SetHOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_TOKEN0(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg)&^(0xfff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_TOKEN0() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg) & 0xfff +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_RX_PF_VALID(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_RX_PF_VALID() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_TOKEN_RDATA_HOST_HOSTSLC1_TOKEN1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_TOKEN_RDATA_HOST_HOSTSLC1_TOKEN1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg) & 0xfff0000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_RX_PF_EOF(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg)&^(0xf0000000)|value<<28) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_RX_PF_EOF() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_RDATA.Reg) & 0xf0000000) >> 28 +} + +// SLCHOST.HOST_SLC0HOST_TOKEN_WDATA +func (o *SLCHOST_Type) SetHOST_SLC0HOST_TOKEN_WDATA_HOST_SLC0HOST_TOKEN0_WD(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_TOKEN_WDATA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_WDATA.Reg)&^(0xfff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_TOKEN_WDATA_HOST_SLC0HOST_TOKEN0_WD() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_WDATA.Reg) & 0xfff +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_TOKEN_WDATA_HOST_SLC0HOST_TOKEN1_WD(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_TOKEN_WDATA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_WDATA.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_TOKEN_WDATA_HOST_SLC0HOST_TOKEN1_WD() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_TOKEN_WDATA.Reg) & 0xfff0000) >> 16 +} + +// SLCHOST.HOST_SLC1HOST_TOKEN_WDATA +func (o *SLCHOST_Type) SetHOST_SLC1HOST_TOKEN_WDATA_HOST_SLC1HOST_TOKEN0_WD(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_TOKEN_WDATA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_WDATA.Reg)&^(0xfff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_TOKEN_WDATA_HOST_SLC1HOST_TOKEN0_WD() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_WDATA.Reg) & 0xfff +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_TOKEN_WDATA_HOST_SLC1HOST_TOKEN1_WD(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_TOKEN_WDATA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_WDATA.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_TOKEN_WDATA_HOST_SLC1HOST_TOKEN1_WD() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_TOKEN_WDATA.Reg) & 0xfff0000) >> 16 +} + +// SLCHOST.HOST_SLCHOST_TOKEN_CON +func (o *SLCHOST_Type) SetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_DEC(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_DEC() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_DEC(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_DEC() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_WR(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_WR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_WR(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_WR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_DEC(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_DEC() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_DEC(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_DEC() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_WR(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_WR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_WR(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_WR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_LEN_WR(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_LEN_WR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_TOKEN_CON.Reg) & 0x100) >> 8 +} + +// SLCHOST.HOST_SLC0HOST_INT_CLR +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_0TO1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_0TO1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_0TO1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_0TO1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_SOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_SOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TX_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_TX_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_PF_VALID_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_PF_VALID_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_NEW_PACKET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_NEW_PACKET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_SLC0_HOST_RD_RETRY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_SLC0_HOST_RD_RETRY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_CLR_HOST_GPIO_SDIO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_CLR_HOST_GPIO_SDIO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_CLR.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC1HOST_INT_CLR +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_0TO1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_0TO1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_0TO1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_0TO1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_SOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_SOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TX_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_TX_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_PF_VALID_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_PF_VALID_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_HOST_RD_RETRY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_HOST_RD_RETRY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_CLR_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_CLR_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_CLR.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC0HOST_FUNC1_INT_ENA +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_GPIO_SDIO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_GPIO_SDIO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC1_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC1HOST_FUNC1_INT_ENA +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC1_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC0HOST_FUNC2_INT_ENA +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_GPIO_SDIO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_GPIO_SDIO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_FUNC2_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC1HOST_FUNC2_INT_ENA +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_FUNC2_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC0HOST_INT_ENA +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_SLC0_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_SLC0_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA_HOST_GPIO_SDIO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA_HOST_GPIO_SDIO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC1HOST_INT_ENA +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC0HOST_RX_INFOR +func (o *SLCHOST_Type) SetHOST_SLC0HOST_RX_INFOR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_RX_INFOR.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_RX_INFOR.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_RX_INFOR() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_RX_INFOR.Reg) & 0xfffff +} + +// SLCHOST.HOST_SLC1HOST_RX_INFOR +func (o *SLCHOST_Type) SetHOST_SLC1HOST_RX_INFOR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_RX_INFOR.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_RX_INFOR.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_RX_INFOR() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_RX_INFOR.Reg) & 0xfffff +} + +// SLCHOST.HOST_SLC0HOST_LEN_WD +func (o *SLCHOST_Type) SetHOST_SLC0HOST_LEN_WD(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_LEN_WD.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_LEN_WD() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_LEN_WD.Reg) +} + +// SLCHOST.HOST_SLC_APBWIN_WDATA +func (o *SLCHOST_Type) SetHOST_SLC_APBWIN_WDATA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC_APBWIN_WDATA.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLC_APBWIN_WDATA() uint32 { + return volatile.LoadUint32(&o.HOST_SLC_APBWIN_WDATA.Reg) +} + +// SLCHOST.HOST_SLC_APBWIN_CONF +func (o *SLCHOST_Type) SetHOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_ADDR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC_APBWIN_CONF.Reg, volatile.LoadUint32(&o.HOST_SLC_APBWIN_CONF.Reg)&^(0xfffffff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_ADDR() uint32 { + return volatile.LoadUint32(&o.HOST_SLC_APBWIN_CONF.Reg) & 0xfffffff +} +func (o *SLCHOST_Type) SetHOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_WR(value uint32) { + volatile.StoreUint32(&o.HOST_SLC_APBWIN_CONF.Reg, volatile.LoadUint32(&o.HOST_SLC_APBWIN_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SLCHOST_Type) GetHOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_WR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC_APBWIN_CONF.Reg) & 0x10000000) >> 28 +} +func (o *SLCHOST_Type) SetHOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_START(value uint32) { + volatile.StoreUint32(&o.HOST_SLC_APBWIN_CONF.Reg, volatile.LoadUint32(&o.HOST_SLC_APBWIN_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SLCHOST_Type) GetHOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_START() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC_APBWIN_CONF.Reg) & 0x20000000) >> 29 +} + +// SLCHOST.HOST_SLC_APBWIN_RDATA +func (o *SLCHOST_Type) SetHOST_SLC_APBWIN_RDATA(value uint32) { + volatile.StoreUint32(&o.HOST_SLC_APBWIN_RDATA.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLC_APBWIN_RDATA() uint32 { + return volatile.LoadUint32(&o.HOST_SLC_APBWIN_RDATA.Reg) +} + +// SLCHOST.HOST_SLCHOST_RDCLR0 +func (o *SLCHOST_Type) SetHOST_SLCHOST_RDCLR0_HOST_SLCHOST_SLC0_BIT7_CLRADDR(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_RDCLR0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_RDCLR0.Reg)&^(0x1ff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_RDCLR0_HOST_SLCHOST_SLC0_BIT7_CLRADDR() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_RDCLR0.Reg) & 0x1ff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_RDCLR0_HOST_SLCHOST_SLC0_BIT6_CLRADDR(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_RDCLR0.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_RDCLR0.Reg)&^(0x3fe00)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_RDCLR0_HOST_SLCHOST_SLC0_BIT6_CLRADDR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_RDCLR0.Reg) & 0x3fe00) >> 9 +} + +// SLCHOST.HOST_SLCHOST_RDCLR1 +func (o *SLCHOST_Type) SetHOST_SLCHOST_RDCLR1_HOST_SLCHOST_SLC1_BIT7_CLRADDR(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_RDCLR1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_RDCLR1.Reg)&^(0x1ff)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_RDCLR1_HOST_SLCHOST_SLC1_BIT7_CLRADDR() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_RDCLR1.Reg) & 0x1ff +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_RDCLR1_HOST_SLCHOST_SLC1_BIT6_CLRADDR(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_RDCLR1.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_RDCLR1.Reg)&^(0x3fe00)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_RDCLR1_HOST_SLCHOST_SLC1_BIT6_CLRADDR() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_RDCLR1.Reg) & 0x3fe00) >> 9 +} + +// SLCHOST.HOST_SLC0HOST_INT_ENA1 +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT0_INT_ENA1() uint32 { + return volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT2_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT2_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT3_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT3_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT4_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT4_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT5_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT5_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT6_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT6_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT7_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT7_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_0TO1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_0TO1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_0TO1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_0TO1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_SOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_SOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_TX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_TX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_UDF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_UDF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TX_OVF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_TX_OVF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_PF_VALID_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_PF_VALID_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT2_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT2_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT3_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT3_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_NEW_PACKET_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_NEW_PACKET_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_HOST_RD_RETRY_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_SLC0_HOST_RD_RETRY_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC0HOST_INT_ENA1_HOST_GPIO_SDIO_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC0HOST_INT_ENA1_HOST_GPIO_SDIO_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC0HOST_INT_ENA1.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLC1HOST_INT_ENA1 +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT0_INT_ENA1() uint32 { + return volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT2_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT2_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT3_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT3_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT4_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT4_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT5_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT5_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT6_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT6_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT7_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT7_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_0TO1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_0TO1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_0TO1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_0TO1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_SOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_SOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_TX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_TX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_UDF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_UDF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TX_OVF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_TX_OVF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_PF_VALID_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_PF_VALID_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT2_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT2_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT3_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT3_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_HOST_RD_RETRY_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_HOST_RD_RETRY_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLC1HOST_INT_ENA1_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.HOST_SLC1HOST_INT_ENA1.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.HOST_SLCHOSTDATE +func (o *SLCHOST_Type) SetHOST_SLCHOSTDATE(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOSTDATE.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOSTDATE() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOSTDATE.Reg) +} + +// SLCHOST.HOST_SLCHOSTID +func (o *SLCHOST_Type) SetHOST_SLCHOSTID(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOSTID.Reg, value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOSTID() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOSTID.Reg) +} + +// SLCHOST.HOST_SLCHOST_CONF +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_HOST_FRC_SDIO11(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg)&^(0x1f)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_HOST_FRC_SDIO11() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg) & 0x1f +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_HOST_FRC_SDIO20(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg)&^(0x3e0)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_HOST_FRC_SDIO20() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg) & 0x3e0) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_HOST_FRC_NEG_SAMP(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg)&^(0x7c00)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_HOST_FRC_NEG_SAMP() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg) & 0x7c00) >> 10 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_HOST_FRC_POS_SAMP(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg)&^(0xf8000)|value<<15) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_HOST_FRC_POS_SAMP() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg) & 0xf8000) >> 15 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_HOST_FRC_QUICK_IN(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg)&^(0x1f00000)|value<<20) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_HOST_FRC_QUICK_IN() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg) & 0x1f00000) >> 20 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_HOST_SDIO20_INT_DELAY(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_HOST_SDIO20_INT_DELAY() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg) & 0x2000000) >> 25 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_HOST_SDIO_PAD_PULLUP(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_HOST_SDIO_PAD_PULLUP() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg) & 0x4000000) >> 26 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_CONF_HOST_HSPEED_CON_EN(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_CONF.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_CONF_HOST_HSPEED_CON_EN() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_CONF.Reg) & 0x8000000) >> 27 +} + +// SLCHOST.HOST_SLCHOST_INF_ST +func (o *SLCHOST_Type) SetHOST_SLCHOST_INF_ST_HOST_SDIO20_MODE(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_INF_ST.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_INF_ST.Reg)&^(0x1f)|value) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_INF_ST_HOST_SDIO20_MODE() uint32 { + return volatile.LoadUint32(&o.HOST_SLCHOST_INF_ST.Reg) & 0x1f +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_INF_ST_HOST_SDIO_NEG_SAMP(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_INF_ST.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_INF_ST.Reg)&^(0x3e0)|value<<5) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_INF_ST_HOST_SDIO_NEG_SAMP() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_INF_ST.Reg) & 0x3e0) >> 5 +} +func (o *SLCHOST_Type) SetHOST_SLCHOST_INF_ST_HOST_SDIO_QUICK_IN(value uint32) { + volatile.StoreUint32(&o.HOST_SLCHOST_INF_ST.Reg, volatile.LoadUint32(&o.HOST_SLCHOST_INF_ST.Reg)&^(0x7c00)|value<<10) +} +func (o *SLCHOST_Type) GetHOST_SLCHOST_INF_ST_HOST_SDIO_QUICK_IN() uint32 { + return (volatile.LoadUint32(&o.HOST_SLCHOST_INF_ST.Reg) & 0x7c00) >> 10 +} + +// SPI (Serial Peripheral Interface) Controller 0 +type SPI_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CTRL1 volatile.Register32 // 0xC + RD_STATUS volatile.Register32 // 0x10 + CTRL2 volatile.Register32 // 0x14 + CLOCK volatile.Register32 // 0x18 + USER volatile.Register32 // 0x1C + USER1 volatile.Register32 // 0x20 + USER2 volatile.Register32 // 0x24 + MOSI_DLEN volatile.Register32 // 0x28 + MISO_DLEN volatile.Register32 // 0x2C + SLV_WR_STATUS volatile.Register32 // 0x30 + PIN volatile.Register32 // 0x34 + SLAVE volatile.Register32 // 0x38 + SLAVE1 volatile.Register32 // 0x3C + SLAVE2 volatile.Register32 // 0x40 + SLAVE3 volatile.Register32 // 0x44 + SLV_WRBUF_DLEN volatile.Register32 // 0x48 + SLV_RDBUF_DLEN volatile.Register32 // 0x4C + CACHE_FCTRL volatile.Register32 // 0x50 + CACHE_SCTRL volatile.Register32 // 0x54 + SRAM_CMD volatile.Register32 // 0x58 + SRAM_DRD_CMD volatile.Register32 // 0x5C + SRAM_DWR_CMD volatile.Register32 // 0x60 + SLV_RD_BIT volatile.Register32 // 0x64 + _ [24]byte + W0 volatile.Register32 // 0x80 + W1 volatile.Register32 // 0x84 + W2 volatile.Register32 // 0x88 + W3 volatile.Register32 // 0x8C + W4 volatile.Register32 // 0x90 + W5 volatile.Register32 // 0x94 + W6 volatile.Register32 // 0x98 + W7 volatile.Register32 // 0x9C + W8 volatile.Register32 // 0xA0 + W9 volatile.Register32 // 0xA4 + W10 volatile.Register32 // 0xA8 + W11 volatile.Register32 // 0xAC + W12 volatile.Register32 // 0xB0 + W13 volatile.Register32 // 0xB4 + W14 volatile.Register32 // 0xB8 + W15 volatile.Register32 // 0xBC + TX_CRC volatile.Register32 // 0xC0 + _ [44]byte + EXT0 volatile.Register32 // 0xF0 + EXT1 volatile.Register32 // 0xF4 + EXT2 volatile.Register32 // 0xF8 + EXT3 volatile.Register32 // 0xFC + DMA_CONF volatile.Register32 // 0x100 + DMA_OUT_LINK volatile.Register32 // 0x104 + DMA_IN_LINK volatile.Register32 // 0x108 + DMA_STATUS volatile.Register32 // 0x10C + DMA_INT_ENA volatile.Register32 // 0x110 + DMA_INT_RAW volatile.Register32 // 0x114 + DMA_INT_ST volatile.Register32 // 0x118 + DMA_INT_CLR volatile.Register32 // 0x11C + IN_ERR_EOF_DES_ADDR volatile.Register32 // 0x120 + IN_SUC_EOF_DES_ADDR volatile.Register32 // 0x124 + INLINK_DSCR volatile.Register32 // 0x128 + INLINK_DSCR_BF0 volatile.Register32 // 0x12C + INLINK_DSCR_BF1 volatile.Register32 // 0x130 + OUT_EOF_BFR_DES_ADDR volatile.Register32 // 0x134 + OUT_EOF_DES_ADDR volatile.Register32 // 0x138 + OUTLINK_DSCR volatile.Register32 // 0x13C + OUTLINK_DSCR_BF0 volatile.Register32 // 0x140 + OUTLINK_DSCR_BF1 volatile.Register32 // 0x144 + DMA_RSTATUS volatile.Register32 // 0x148 + DMA_TSTATUS volatile.Register32 // 0x14C + _ [684]byte + DATE volatile.Register32 // 0x3FC +} + +// SPI.CMD +func (o *SPI_Type) SetCMD_FLASH_PER(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10000)|value<<16) +} +func (o *SPI_Type) GetCMD_FLASH_PER() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10000) >> 16 +} +func (o *SPI_Type) SetCMD_FLASH_PES(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI_Type) GetCMD_FLASH_PES() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI_Type) SetCMD_FLASH_HPM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI_Type) GetCMD_FLASH_HPM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI_Type) SetCMD_FLASH_RES(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI_Type) GetCMD_FLASH_RES() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI_Type) SetCMD_FLASH_DP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI_Type) GetCMD_FLASH_DP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI_Type) SetCMD_FLASH_CE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI_Type) GetCMD_FLASH_CE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI_Type) SetCMD_FLASH_BE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI_Type) GetCMD_FLASH_BE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI_Type) SetCMD_FLASH_SE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI_Type) GetCMD_FLASH_SE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI_Type) SetCMD_FLASH_PP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI_Type) GetCMD_FLASH_PP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI_Type) SetCMD_FLASH_WRSR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI_Type) GetCMD_FLASH_WRSR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI_Type) SetCMD_FLASH_RDSR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI_Type) GetCMD_FLASH_RDSR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI_Type) SetCMD_FLASH_RDID(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetCMD_FLASH_RDID() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10000000) >> 28 +} +func (o *SPI_Type) SetCMD_FLASH_WRDI(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetCMD_FLASH_WRDI() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetCMD_FLASH_WREN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetCMD_FLASH_WREN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetCMD_FLASH_READ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetCMD_FLASH_READ() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31 +} + +// SPI.CTRL +func (o *SPI_Type) SetCTRL_FCS_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetCTRL_FCS_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetCTRL_TX_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetCTRL_TX_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetCTRL_WAIT_FLASH_IDLE_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetCTRL_WAIT_FLASH_IDLE_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetCTRL_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI_Type) GetCTRL_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetCTRL_RESANDRES(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetCTRL_RESANDRES() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI_Type) SetCTRL_WP(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI_Type) GetCTRL_WP() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI_Type) SetCTRL_WRSR_2B(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI_Type) GetCTRL_WRSR_2B() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI_Type) SetCTRL_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI_Type) GetCTRL_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI_Type) SetCTRL_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI_Type) GetCTRL_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI_Type) SetCTRL_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI_Type) GetCTRL_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000000) >> 25 +} +func (o *SPI_Type) SetCTRL_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI_Type) GetCTRL_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000000) >> 26 +} + +// SPI.CTRL1 +func (o *SPI_Type) SetCTRL1_CS_HOLD_DELAY_RES(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0xfff0000)|value<<16) +} +func (o *SPI_Type) GetCTRL1_CS_HOLD_DELAY_RES() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0xfff0000) >> 16 +} +func (o *SPI_Type) SetCTRL1_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI_Type) GetCTRL1_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0xf0000000) >> 28 +} + +// SPI.RD_STATUS +func (o *SPI_Type) SetRD_STATUS_STATUS(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xffff)|value) +} +func (o *SPI_Type) GetRD_STATUS_STATUS() uint32 { + return volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xffff +} +func (o *SPI_Type) SetRD_STATUS_WB_MODE(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI_Type) GetRD_STATUS_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xff0000) >> 16 +} +func (o *SPI_Type) SetRD_STATUS_STATUS_EXT(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI_Type) GetRD_STATUS_STATUS_EXT() uint32 { + return (volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xff000000) >> 24 +} + +// SPI.CTRL2 +func (o *SPI_Type) SetCTRL2_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xf)|value) +} +func (o *SPI_Type) GetCTRL2_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0xf +} +func (o *SPI_Type) SetCTRL2_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xf0)|value<<4) +} +func (o *SPI_Type) GetCTRL2_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xf0) >> 4 +} +func (o *SPI_Type) SetCTRL2_CK_OUT_LOW_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xf00)|value<<8) +} +func (o *SPI_Type) GetCTRL2_CK_OUT_LOW_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xf00) >> 8 +} +func (o *SPI_Type) SetCTRL2_CK_OUT_HIGH_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xf000)|value<<12) +} +func (o *SPI_Type) GetCTRL2_CK_OUT_HIGH_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xf000) >> 12 +} +func (o *SPI_Type) SetCTRL2_MISO_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x30000)|value<<16) +} +func (o *SPI_Type) GetCTRL2_MISO_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x30000) >> 16 +} +func (o *SPI_Type) SetCTRL2_MISO_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI_Type) GetCTRL2_MISO_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1c0000) >> 18 +} +func (o *SPI_Type) SetCTRL2_MOSI_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x600000)|value<<21) +} +func (o *SPI_Type) GetCTRL2_MOSI_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x600000) >> 21 +} +func (o *SPI_Type) SetCTRL2_MOSI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x3800000)|value<<23) +} +func (o *SPI_Type) GetCTRL2_MOSI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x3800000) >> 23 +} +func (o *SPI_Type) SetCTRL2_CS_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xc000000)|value<<26) +} +func (o *SPI_Type) GetCTRL2_CS_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xc000000) >> 26 +} +func (o *SPI_Type) SetCTRL2_CS_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI_Type) GetCTRL2_CS_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xf0000000) >> 28 +} + +// SPI.CLOCK +func (o *SPI_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f +} +func (o *SPI_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI_Type) SetCLOCK_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *SPI_Type) GetCLOCK_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x7ffc0000) >> 18 +} +func (o *SPI_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI.USER +func (o *SPI_Type) SetUSER_DOUTDIN(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetUSER_DOUTDIN() uint32 { + return volatile.LoadUint32(&o.USER.Reg) & 0x1 +} +func (o *SPI_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetUSER_CK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetUSER_CK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetUSER_RD_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetUSER_RD_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetUSER_WR_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetUSER_WR_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI_Type) SetUSER_FWRITE_DIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetUSER_FWRITE_DIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetUSER_FWRITE_QIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetUSER_FWRITE_QIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI_Type) SetUSER_SIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000)|value<<16) +} +func (o *SPI_Type) GetUSER_SIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000) >> 16 +} +func (o *SPI_Type) SetUSER_USR_HOLD_POL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000)|value<<17) +} +func (o *SPI_Type) GetUSER_USR_HOLD_POL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000) >> 17 +} +func (o *SPI_Type) SetUSER_USR_DOUT_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000)|value<<18) +} +func (o *SPI_Type) GetUSER_USR_DOUT_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000) >> 18 +} +func (o *SPI_Type) SetUSER_USR_DIN_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000)|value<<19) +} +func (o *SPI_Type) GetUSER_USR_DIN_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000) >> 19 +} +func (o *SPI_Type) SetUSER_USR_DUMMY_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x100000)|value<<20) +} +func (o *SPI_Type) GetUSER_USR_DUMMY_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x100000) >> 20 +} +func (o *SPI_Type) SetUSER_USR_ADDR_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200000)|value<<21) +} +func (o *SPI_Type) GetUSER_USR_ADDR_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200000) >> 21 +} +func (o *SPI_Type) SetUSER_USR_CMD_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x400000)|value<<22) +} +func (o *SPI_Type) GetUSER_USR_CMD_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x400000) >> 22 +} +func (o *SPI_Type) SetUSER_USR_PREP_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x800000)|value<<23) +} +func (o *SPI_Type) GetUSER_USR_PREP_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x800000) >> 23 +} +func (o *SPI_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI.USER1 +func (o *SPI_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xff)|value) +} +func (o *SPI_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0xff +} +func (o *SPI_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI.USER2 +func (o *SPI_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI.MOSI_DLEN +func (o *SPI_Type) SetMOSI_DLEN_USR_MOSI_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MOSI_DLEN.Reg, volatile.LoadUint32(&o.MOSI_DLEN.Reg)&^(0xffffff)|value) +} +func (o *SPI_Type) GetMOSI_DLEN_USR_MOSI_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MOSI_DLEN.Reg) & 0xffffff +} + +// SPI.MISO_DLEN +func (o *SPI_Type) SetMISO_DLEN_USR_MISO_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MISO_DLEN.Reg, volatile.LoadUint32(&o.MISO_DLEN.Reg)&^(0xffffff)|value) +} +func (o *SPI_Type) GetMISO_DLEN_USR_MISO_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MISO_DLEN.Reg) & 0xffffff +} + +// SPI.SLV_WR_STATUS +func (o *SPI_Type) SetSLV_WR_STATUS(value uint32) { + volatile.StoreUint32(&o.SLV_WR_STATUS.Reg, value) +} +func (o *SPI_Type) GetSLV_WR_STATUS() uint32 { + return volatile.LoadUint32(&o.SLV_WR_STATUS.Reg) +} + +// SPI.PIN +func (o *SPI_Type) SetPIN_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.PIN.Reg, volatile.LoadUint32(&o.PIN.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetPIN_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.PIN.Reg) & 0x1 +} +func (o *SPI_Type) SetPIN_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.PIN.Reg, volatile.LoadUint32(&o.PIN.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetPIN_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.PIN.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetPIN_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.PIN.Reg, volatile.LoadUint32(&o.PIN.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetPIN_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.PIN.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetPIN_CK_DIS(value uint32) { + volatile.StoreUint32(&o.PIN.Reg, volatile.LoadUint32(&o.PIN.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetPIN_CK_DIS() uint32 { + return (volatile.LoadUint32(&o.PIN.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetPIN_MASTER_CS_POL(value uint32) { + volatile.StoreUint32(&o.PIN.Reg, volatile.LoadUint32(&o.PIN.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI_Type) GetPIN_MASTER_CS_POL() uint32 { + return (volatile.LoadUint32(&o.PIN.Reg) & 0x1c0) >> 6 +} +func (o *SPI_Type) SetPIN_MASTER_CK_SEL(value uint32) { + volatile.StoreUint32(&o.PIN.Reg, volatile.LoadUint32(&o.PIN.Reg)&^(0x3800)|value<<11) +} +func (o *SPI_Type) GetPIN_MASTER_CK_SEL() uint32 { + return (volatile.LoadUint32(&o.PIN.Reg) & 0x3800) >> 11 +} +func (o *SPI_Type) SetPIN_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.PIN.Reg, volatile.LoadUint32(&o.PIN.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetPIN_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.PIN.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetPIN_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.PIN.Reg, volatile.LoadUint32(&o.PIN.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetPIN_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.PIN.Reg) & 0x40000000) >> 30 +} + +// SPI.SLAVE +func (o *SPI_Type) SetSLAVE_SLV_RD_BUF_DONE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetSLAVE_SLV_RD_BUF_DONE() uint32 { + return volatile.LoadUint32(&o.SLAVE.Reg) & 0x1 +} +func (o *SPI_Type) SetSLAVE_SLV_WR_BUF_DONE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetSLAVE_SLV_WR_BUF_DONE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetSLAVE_SLV_RD_STA_DONE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetSLAVE_SLV_RD_STA_DONE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetSLAVE_SLV_WR_STA_DONE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetSLAVE_SLV_WR_STA_DONE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetSLAVE_TRANS_DONE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetSLAVE_TRANS_DONE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetSLAVE_INT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3e0)|value<<5) +} +func (o *SPI_Type) GetSLAVE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x3e0) >> 5 +} +func (o *SPI_Type) SetSLAVE_CS_I_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0xc00)|value<<10) +} +func (o *SPI_Type) GetSLAVE_CS_I_MODE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0xc00) >> 10 +} +func (o *SPI_Type) SetSLAVE_SLV_LAST_COMMAND(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0xe0000)|value<<17) +} +func (o *SPI_Type) GetSLAVE_SLV_LAST_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0xe0000) >> 17 +} +func (o *SPI_Type) SetSLAVE_SLV_LAST_STATE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x700000)|value<<20) +} +func (o *SPI_Type) GetSLAVE_SLV_LAST_STATE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x700000) >> 20 +} +func (o *SPI_Type) SetSLAVE_TRANS_CNT(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x7800000)|value<<23) +} +func (o *SPI_Type) GetSLAVE_TRANS_CNT() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x7800000) >> 23 +} +func (o *SPI_Type) SetSLAVE_SLV_CMD_DEFINE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI_Type) GetSLAVE_SLV_CMD_DEFINE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI_Type) SetSLAVE_SLV_WR_RD_STA_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetSLAVE_SLV_WR_RD_STA_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x10000000) >> 28 +} +func (o *SPI_Type) SetSLAVE_SLV_WR_RD_BUF_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetSLAVE_SLV_WR_RD_BUF_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetSLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetSLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetSLAVE_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetSLAVE_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x80000000) >> 31 +} + +// SPI.SLAVE1 +func (o *SPI_Type) SetSLAVE1_SLV_RDBUF_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetSLAVE1_SLV_RDBUF_DUMMY_EN() uint32 { + return volatile.LoadUint32(&o.SLAVE1.Reg) & 0x1 +} +func (o *SPI_Type) SetSLAVE1_SLV_WRBUF_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetSLAVE1_SLV_WRBUF_DUMMY_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetSLAVE1_SLV_RDSTA_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetSLAVE1_SLV_RDSTA_DUMMY_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetSLAVE1_SLV_WRSTA_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetSLAVE1_SLV_WRSTA_DUMMY_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetSLAVE1_SLV_WR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3f0)|value<<4) +} +func (o *SPI_Type) GetSLAVE1_SLV_WR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3f0) >> 4 +} +func (o *SPI_Type) SetSLAVE1_SLV_RD_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0xfc00)|value<<10) +} +func (o *SPI_Type) GetSLAVE1_SLV_RD_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0xfc00) >> 10 +} +func (o *SPI_Type) SetSLAVE1_SLV_STATUS_READBACK(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI_Type) GetSLAVE1_SLV_STATUS_READBACK() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x2000000) >> 25 +} +func (o *SPI_Type) SetSLAVE1_SLV_STATUS_FAST_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI_Type) GetSLAVE1_SLV_STATUS_FAST_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x4000000) >> 26 +} +func (o *SPI_Type) SetSLAVE1_SLV_STATUS_BITLEN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI_Type) GetSLAVE1_SLV_STATUS_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0xf8000000) >> 27 +} + +// SPI.SLAVE2 +func (o *SPI_Type) SetSLAVE2_SLV_RDSTA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SLAVE2.Reg, volatile.LoadUint32(&o.SLAVE2.Reg)&^(0xff)|value) +} +func (o *SPI_Type) GetSLAVE2_SLV_RDSTA_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SLAVE2.Reg) & 0xff +} +func (o *SPI_Type) SetSLAVE2_SLV_WRSTA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SLAVE2.Reg, volatile.LoadUint32(&o.SLAVE2.Reg)&^(0xff00)|value<<8) +} +func (o *SPI_Type) GetSLAVE2_SLV_WRSTA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SLAVE2.Reg) & 0xff00) >> 8 +} +func (o *SPI_Type) SetSLAVE2_SLV_RDBUF_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SLAVE2.Reg, volatile.LoadUint32(&o.SLAVE2.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI_Type) GetSLAVE2_SLV_RDBUF_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SLAVE2.Reg) & 0xff0000) >> 16 +} +func (o *SPI_Type) SetSLAVE2_SLV_WRBUF_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SLAVE2.Reg, volatile.LoadUint32(&o.SLAVE2.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI_Type) GetSLAVE2_SLV_WRBUF_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SLAVE2.Reg) & 0xff000000) >> 24 +} + +// SPI.SLAVE3 +func (o *SPI_Type) SetSLAVE3_SLV_RDBUF_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SLAVE3.Reg, volatile.LoadUint32(&o.SLAVE3.Reg)&^(0xff)|value) +} +func (o *SPI_Type) GetSLAVE3_SLV_RDBUF_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SLAVE3.Reg) & 0xff +} +func (o *SPI_Type) SetSLAVE3_SLV_WRBUF_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SLAVE3.Reg, volatile.LoadUint32(&o.SLAVE3.Reg)&^(0xff00)|value<<8) +} +func (o *SPI_Type) GetSLAVE3_SLV_WRBUF_CMD_VALUE() uint32 { + return (volatile.LoadUint32(&o.SLAVE3.Reg) & 0xff00) >> 8 +} +func (o *SPI_Type) SetSLAVE3_SLV_RDSTA_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SLAVE3.Reg, volatile.LoadUint32(&o.SLAVE3.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI_Type) GetSLAVE3_SLV_RDSTA_CMD_VALUE() uint32 { + return (volatile.LoadUint32(&o.SLAVE3.Reg) & 0xff0000) >> 16 +} +func (o *SPI_Type) SetSLAVE3_SLV_WRSTA_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SLAVE3.Reg, volatile.LoadUint32(&o.SLAVE3.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI_Type) GetSLAVE3_SLV_WRSTA_CMD_VALUE() uint32 { + return (volatile.LoadUint32(&o.SLAVE3.Reg) & 0xff000000) >> 24 +} + +// SPI.SLV_WRBUF_DLEN +func (o *SPI_Type) SetSLV_WRBUF_DLEN_SLV_WRBUF_DBITLEN(value uint32) { + volatile.StoreUint32(&o.SLV_WRBUF_DLEN.Reg, volatile.LoadUint32(&o.SLV_WRBUF_DLEN.Reg)&^(0xffffff)|value) +} +func (o *SPI_Type) GetSLV_WRBUF_DLEN_SLV_WRBUF_DBITLEN() uint32 { + return volatile.LoadUint32(&o.SLV_WRBUF_DLEN.Reg) & 0xffffff +} + +// SPI.SLV_RDBUF_DLEN +func (o *SPI_Type) SetSLV_RDBUF_DLEN_SLV_RDBUF_DBITLEN(value uint32) { + volatile.StoreUint32(&o.SLV_RDBUF_DLEN.Reg, volatile.LoadUint32(&o.SLV_RDBUF_DLEN.Reg)&^(0xffffff)|value) +} +func (o *SPI_Type) GetSLV_RDBUF_DLEN_SLV_RDBUF_DBITLEN() uint32 { + return volatile.LoadUint32(&o.SLV_RDBUF_DLEN.Reg) & 0xffffff +} + +// SPI.CACHE_FCTRL +func (o *SPI_Type) SetCACHE_FCTRL_CACHE_REQ_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetCACHE_FCTRL_CACHE_REQ_EN() uint32 { + return volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x1 +} +func (o *SPI_Type) SetCACHE_FCTRL_CACHE_USR_CMD_4BYTE(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetCACHE_FCTRL_CACHE_USR_CMD_4BYTE() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetCACHE_FCTRL_CACHE_FLASH_USR_CMD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetCACHE_FCTRL_CACHE_FLASH_USR_CMD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetCACHE_FCTRL_CACHE_FLASH_PES_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetCACHE_FCTRL_CACHE_FLASH_PES_EN() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x8) >> 3 +} + +// SPI.CACHE_SCTRL +func (o *SPI_Type) SetCACHE_SCTRL_USR_SRAM_DIO(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetCACHE_SCTRL_USR_SRAM_DIO() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetCACHE_SCTRL_USR_SRAM_QIO(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetCACHE_SCTRL_USR_SRAM_QIO() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetCACHE_SCTRL_USR_WR_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetCACHE_SCTRL_USR_WR_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetCACHE_SCTRL_USR_RD_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetCACHE_SCTRL_USR_RD_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetCACHE_SCTRL_CACHE_SRAM_USR_RCMD(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetCACHE_SCTRL_CACHE_SRAM_USR_RCMD() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetCACHE_SCTRL_SRAM_BYTES_LEN(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x3fc0)|value<<6) +} +func (o *SPI_Type) GetCACHE_SCTRL_SRAM_BYTES_LEN() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x3fc0) >> 6 +} +func (o *SPI_Type) SetCACHE_SCTRL_SRAM_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *SPI_Type) GetCACHE_SCTRL_SRAM_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x3fc000) >> 14 +} +func (o *SPI_Type) SetCACHE_SCTRL_SRAM_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0xfc00000)|value<<22) +} +func (o *SPI_Type) GetCACHE_SCTRL_SRAM_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0xfc00000) >> 22 +} +func (o *SPI_Type) SetCACHE_SCTRL_CACHE_SRAM_USR_WCMD(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetCACHE_SCTRL_CACHE_SRAM_USR_WCMD() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x10000000) >> 28 +} + +// SPI.SRAM_CMD +func (o *SPI_Type) SetSRAM_CMD_SRAM_DIO(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetSRAM_CMD_SRAM_DIO() uint32 { + return volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x1 +} +func (o *SPI_Type) SetSRAM_CMD_SRAM_QIO(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetSRAM_CMD_SRAM_QIO() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetSRAM_CMD_SRAM_RSTIO(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetSRAM_CMD_SRAM_RSTIO() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x10) >> 4 +} + +// SPI.SRAM_DRD_CMD +func (o *SPI_Type) SetSRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SRAM_DRD_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI_Type) GetSRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SRAM_DRD_CMD.Reg) & 0xffff +} +func (o *SPI_Type) SetSRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SRAM_DRD_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI_Type) GetSRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SRAM_DRD_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI.SRAM_DWR_CMD +func (o *SPI_Type) SetSRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SRAM_DWR_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI_Type) GetSRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SRAM_DWR_CMD.Reg) & 0xffff +} +func (o *SPI_Type) SetSRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SRAM_DWR_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI_Type) GetSRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SRAM_DWR_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI.SLV_RD_BIT +func (o *SPI_Type) SetSLV_RD_BIT_SLV_RDATA_BIT(value uint32) { + volatile.StoreUint32(&o.SLV_RD_BIT.Reg, volatile.LoadUint32(&o.SLV_RD_BIT.Reg)&^(0xffffff)|value) +} +func (o *SPI_Type) GetSLV_RD_BIT_SLV_RDATA_BIT() uint32 { + return volatile.LoadUint32(&o.SLV_RD_BIT.Reg) & 0xffffff +} + +// SPI.W0 +func (o *SPI_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI.W1 +func (o *SPI_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI.W2 +func (o *SPI_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI.W3 +func (o *SPI_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI.W4 +func (o *SPI_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI.W5 +func (o *SPI_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI.W6 +func (o *SPI_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI.W7 +func (o *SPI_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI.W8 +func (o *SPI_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI.W9 +func (o *SPI_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI.W10 +func (o *SPI_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI.W11 +func (o *SPI_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI.W12 +func (o *SPI_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI.W13 +func (o *SPI_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI.W14 +func (o *SPI_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI.W15 +func (o *SPI_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI.TX_CRC +func (o *SPI_Type) SetTX_CRC(value uint32) { + volatile.StoreUint32(&o.TX_CRC.Reg, value) +} +func (o *SPI_Type) GetTX_CRC() uint32 { + return volatile.LoadUint32(&o.TX_CRC.Reg) +} + +// SPI.EXT0 +func (o *SPI_Type) SetEXT0_T_PP_TIME(value uint32) { + volatile.StoreUint32(&o.EXT0.Reg, volatile.LoadUint32(&o.EXT0.Reg)&^(0xfff)|value) +} +func (o *SPI_Type) GetEXT0_T_PP_TIME() uint32 { + return volatile.LoadUint32(&o.EXT0.Reg) & 0xfff +} +func (o *SPI_Type) SetEXT0_T_PP_SHIFT(value uint32) { + volatile.StoreUint32(&o.EXT0.Reg, volatile.LoadUint32(&o.EXT0.Reg)&^(0xf0000)|value<<16) +} +func (o *SPI_Type) GetEXT0_T_PP_SHIFT() uint32 { + return (volatile.LoadUint32(&o.EXT0.Reg) & 0xf0000) >> 16 +} +func (o *SPI_Type) SetEXT0_T_PP_ENA(value uint32) { + volatile.StoreUint32(&o.EXT0.Reg, volatile.LoadUint32(&o.EXT0.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetEXT0_T_PP_ENA() uint32 { + return (volatile.LoadUint32(&o.EXT0.Reg) & 0x80000000) >> 31 +} + +// SPI.EXT1 +func (o *SPI_Type) SetEXT1_T_ERASE_TIME(value uint32) { + volatile.StoreUint32(&o.EXT1.Reg, volatile.LoadUint32(&o.EXT1.Reg)&^(0xfff)|value) +} +func (o *SPI_Type) GetEXT1_T_ERASE_TIME() uint32 { + return volatile.LoadUint32(&o.EXT1.Reg) & 0xfff +} +func (o *SPI_Type) SetEXT1_T_ERASE_SHIFT(value uint32) { + volatile.StoreUint32(&o.EXT1.Reg, volatile.LoadUint32(&o.EXT1.Reg)&^(0xf0000)|value<<16) +} +func (o *SPI_Type) GetEXT1_T_ERASE_SHIFT() uint32 { + return (volatile.LoadUint32(&o.EXT1.Reg) & 0xf0000) >> 16 +} +func (o *SPI_Type) SetEXT1_T_ERASE_ENA(value uint32) { + volatile.StoreUint32(&o.EXT1.Reg, volatile.LoadUint32(&o.EXT1.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetEXT1_T_ERASE_ENA() uint32 { + return (volatile.LoadUint32(&o.EXT1.Reg) & 0x80000000) >> 31 +} + +// SPI.EXT2 +func (o *SPI_Type) SetEXT2_ST(value uint32) { + volatile.StoreUint32(&o.EXT2.Reg, volatile.LoadUint32(&o.EXT2.Reg)&^(0x7)|value) +} +func (o *SPI_Type) GetEXT2_ST() uint32 { + return volatile.LoadUint32(&o.EXT2.Reg) & 0x7 +} + +// SPI.EXT3 +func (o *SPI_Type) SetEXT3_INT_HOLD_ENA(value uint32) { + volatile.StoreUint32(&o.EXT3.Reg, volatile.LoadUint32(&o.EXT3.Reg)&^(0x3)|value) +} +func (o *SPI_Type) GetEXT3_INT_HOLD_ENA() uint32 { + return volatile.LoadUint32(&o.EXT3.Reg) & 0x3 +} + +// SPI.DMA_CONF +func (o *SPI_Type) SetDMA_CONF_IN_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_CONF_IN_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_CONF_OUT_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_CONF_OUT_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_CONF_AHBM_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_CONF_AHBM_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_CONF_AHBM_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_CONF_AHBM_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_CONF_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_CONF_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_CONF_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_CONF_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_CONF_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_CONF_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x100) >> 8 +} +func (o *SPI_Type) SetDMA_CONF_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x200)|value<<9) +} +func (o *SPI_Type) GetDMA_CONF_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x200) >> 9 +} +func (o *SPI_Type) SetDMA_CONF_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetDMA_CONF_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetDMA_CONF_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetDMA_CONF_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetDMA_CONF_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetDMA_CONF_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetDMA_CONF_DMA_RX_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetDMA_CONF_DMA_RX_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetDMA_CONF_DMA_TX_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetDMA_CONF_DMA_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x8000) >> 15 +} +func (o *SPI_Type) SetDMA_CONF_DMA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *SPI_Type) GetDMA_CONF_DMA_CONTINUE() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10000) >> 16 +} + +// SPI.DMA_OUT_LINK +func (o *SPI_Type) SetDMA_OUT_LINK_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0xfffff)|value) +} +func (o *SPI_Type) GetDMA_OUT_LINK_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0xfffff +} +func (o *SPI_Type) SetDMA_OUT_LINK_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetDMA_OUT_LINK_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SPI_Type) SetDMA_OUT_LINK_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetDMA_OUT_LINK_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetDMA_OUT_LINK_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetDMA_OUT_LINK_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x40000000) >> 30 +} + +// SPI.DMA_IN_LINK +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0xfffff)|value) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0xfffff +} +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x100000)|value<<20) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x100000) >> 20 +} +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_START(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x40000000) >> 30 +} + +// SPI.DMA_STATUS +func (o *SPI_Type) SetDMA_STATUS_DMA_RX_EN(value uint32) { + volatile.StoreUint32(&o.DMA_STATUS.Reg, volatile.LoadUint32(&o.DMA_STATUS.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetDMA_STATUS_DMA_RX_EN() uint32 { + return volatile.LoadUint32(&o.DMA_STATUS.Reg) & 0x1 +} +func (o *SPI_Type) SetDMA_STATUS_DMA_TX_EN(value uint32) { + volatile.StoreUint32(&o.DMA_STATUS.Reg, volatile.LoadUint32(&o.DMA_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetDMA_STATUS_DMA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_STATUS.Reg) & 0x2) >> 1 +} + +// SPI.DMA_INT_ENA +func (o *SPI_Type) SetDMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetDMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1 +} +func (o *SPI_Type) SetDMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetDMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetDMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_INT_ENA_IN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_INT_ENA_IN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_INT_ENA_IN_ERR_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_INT_ENA_IN_ERR_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_INT_ENA_IN_SUC_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_INT_ENA_IN_SUC_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_INT_ENA_OUT_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_INT_ENA_OUT_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_INT_ENA_OUT_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_INT_ENA_OUT_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100) >> 8 +} + +// SPI.DMA_INT_RAW +func (o *SPI_Type) SetDMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetDMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW() uint32 { + return volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1 +} +func (o *SPI_Type) SetDMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetDMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetDMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_INT_RAW_IN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_INT_RAW_IN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_INT_RAW_IN_ERR_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_INT_RAW_IN_ERR_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_INT_RAW_IN_SUC_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_INT_RAW_IN_SUC_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_INT_RAW_OUT_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_INT_RAW_OUT_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_INT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_INT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100) >> 8 +} + +// SPI.DMA_INT_ST +func (o *SPI_Type) SetDMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetDMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1 +} +func (o *SPI_Type) SetDMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetDMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetDMA_INT_ST_INLINK_DSCR_ERROR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_INT_ST_INLINK_DSCR_ERROR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_INT_ST_IN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_INT_ST_IN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_INT_ST_IN_ERR_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_INT_ST_IN_ERR_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_INT_ST_IN_SUC_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_INT_ST_IN_SUC_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_INT_ST_OUT_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_INT_ST_OUT_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_INT_ST_OUT_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_INT_ST_OUT_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_INT_ST_OUT_TOTAL_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_INT_ST_OUT_TOTAL_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100) >> 8 +} + +// SPI.DMA_INT_CLR +func (o *SPI_Type) SetDMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetDMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1 +} +func (o *SPI_Type) SetDMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetDMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetDMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_INT_CLR_IN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_INT_CLR_IN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_INT_CLR_IN_ERR_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_INT_CLR_IN_ERR_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_INT_CLR_IN_SUC_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_INT_CLR_IN_SUC_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_INT_CLR_OUT_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_INT_CLR_OUT_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_INT_CLR_OUT_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_INT_CLR_OUT_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100) >> 8 +} + +// SPI.IN_ERR_EOF_DES_ADDR +func (o *SPI_Type) SetIN_ERR_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR.Reg, value) +} +func (o *SPI_Type) GetIN_ERR_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR.Reg) +} + +// SPI.IN_SUC_EOF_DES_ADDR +func (o *SPI_Type) SetIN_SUC_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR.Reg, value) +} +func (o *SPI_Type) GetIN_SUC_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR.Reg) +} + +// SPI.INLINK_DSCR +func (o *SPI_Type) SetINLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR.Reg, value) +} +func (o *SPI_Type) GetINLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR.Reg) +} + +// SPI.INLINK_DSCR_BF0 +func (o *SPI_Type) SetINLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR_BF0.Reg, value) +} +func (o *SPI_Type) GetINLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR_BF0.Reg) +} + +// SPI.INLINK_DSCR_BF1 +func (o *SPI_Type) SetINLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR_BF1.Reg, value) +} +func (o *SPI_Type) GetINLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR_BF1.Reg) +} + +// SPI.OUT_EOF_BFR_DES_ADDR +func (o *SPI_Type) SetOUT_EOF_BFR_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR.Reg, value) +} +func (o *SPI_Type) GetOUT_EOF_BFR_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR.Reg) +} + +// SPI.OUT_EOF_DES_ADDR +func (o *SPI_Type) SetOUT_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR.Reg, value) +} +func (o *SPI_Type) GetOUT_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR.Reg) +} + +// SPI.OUTLINK_DSCR +func (o *SPI_Type) SetOUTLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR.Reg, value) +} +func (o *SPI_Type) GetOUTLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR.Reg) +} + +// SPI.OUTLINK_DSCR_BF0 +func (o *SPI_Type) SetOUTLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR_BF0.Reg, value) +} +func (o *SPI_Type) GetOUTLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR_BF0.Reg) +} + +// SPI.OUTLINK_DSCR_BF1 +func (o *SPI_Type) SetOUTLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR_BF1.Reg, value) +} +func (o *SPI_Type) GetOUTLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR_BF1.Reg) +} + +// SPI.DMA_RSTATUS +func (o *SPI_Type) SetDMA_RSTATUS(value uint32) { + volatile.StoreUint32(&o.DMA_RSTATUS.Reg, value) +} +func (o *SPI_Type) GetDMA_RSTATUS() uint32 { + return volatile.LoadUint32(&o.DMA_RSTATUS.Reg) +} + +// SPI.DMA_TSTATUS +func (o *SPI_Type) SetDMA_TSTATUS(value uint32) { + volatile.StoreUint32(&o.DMA_TSTATUS.Reg, value) +} +func (o *SPI_Type) GetDMA_TSTATUS() uint32 { + return volatile.LoadUint32(&o.DMA_TSTATUS.Reg) +} + +// SPI.DATE +func (o *SPI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Timer Group 0 +type TIMG_Type struct { + T0CONFIG volatile.Register32 // 0x0 + T0LO volatile.Register32 // 0x4 + T0HI volatile.Register32 // 0x8 + T0UPDATE volatile.Register32 // 0xC + T0ALARMLO volatile.Register32 // 0x10 + T0ALARMHI volatile.Register32 // 0x14 + T0LOADLO volatile.Register32 // 0x18 + T0LOADHI volatile.Register32 // 0x1C + T0LOAD volatile.Register32 // 0x20 + T1CONFIG volatile.Register32 // 0x24 + T1LO volatile.Register32 // 0x28 + T1HI volatile.Register32 // 0x2C + T1UPDATE volatile.Register32 // 0x30 + T1ALARMLO volatile.Register32 // 0x34 + T1ALARMHI volatile.Register32 // 0x38 + T1LOADLO volatile.Register32 // 0x3C + T1LOADHI volatile.Register32 // 0x40 + T1LOAD volatile.Register32 // 0x44 + WDTCONFIG0 volatile.Register32 // 0x48 + WDTCONFIG1 volatile.Register32 // 0x4C + WDTCONFIG2 volatile.Register32 // 0x50 + WDTCONFIG3 volatile.Register32 // 0x54 + WDTCONFIG4 volatile.Register32 // 0x58 + WDTCONFIG5 volatile.Register32 // 0x5C + WDTFEED volatile.Register32 // 0x60 + WDTWPROTECT volatile.Register32 // 0x64 + RTCCALICFG volatile.Register32 // 0x68 + RTCCALICFG1 volatile.Register32 // 0x6C + LACTCONFIG volatile.Register32 // 0x70 + LACTRTC volatile.Register32 // 0x74 + LACTLO volatile.Register32 // 0x78 + LACTHI volatile.Register32 // 0x7C + LACTUPDATE volatile.Register32 // 0x80 + LACTALARMLO volatile.Register32 // 0x84 + LACTALARMHI volatile.Register32 // 0x88 + LACTLOADLO volatile.Register32 // 0x8C + LACTLOADHI volatile.Register32 // 0x90 + LACTLOAD volatile.Register32 // 0x94 + INT_ENA_TIMERS volatile.Register32 // 0x98 + INT_RAW_TIMERS volatile.Register32 // 0x9C + INT_ST_TIMERS volatile.Register32 // 0xA0 + INT_CLR_TIMERS volatile.Register32 // 0xA4 + _ [80]byte + NTIMERS_DATE volatile.Register32 // 0xF8 + TIMGCLK volatile.Register32 // 0xFC +} + +// TIMG.T0CONFIG +func (o *TIMG_Type) SetT0CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT0CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT0CONFIG_LEVEL_INT_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x800)|value<<11) +} +func (o *TIMG_Type) GetT0CONFIG_LEVEL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x800) >> 11 +} +func (o *TIMG_Type) SetT0CONFIG_EDGE_INT_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetT0CONFIG_EDGE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetT0CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT0CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT0CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT0CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT0CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT0CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT0CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0LO +func (o *TIMG_Type) SetT0LO(value uint32) { + volatile.StoreUint32(&o.T0LO.Reg, value) +} +func (o *TIMG_Type) GetT0LO() uint32 { + return volatile.LoadUint32(&o.T0LO.Reg) +} + +// TIMG.T0HI +func (o *TIMG_Type) SetT0HI(value uint32) { + volatile.StoreUint32(&o.T0HI.Reg, value) +} +func (o *TIMG_Type) GetT0HI() uint32 { + return volatile.LoadUint32(&o.T0HI.Reg) +} + +// TIMG.T0UPDATE +func (o *TIMG_Type) SetT0UPDATE(value uint32) { + volatile.StoreUint32(&o.T0UPDATE.Reg, value) +} +func (o *TIMG_Type) GetT0UPDATE() uint32 { + return volatile.LoadUint32(&o.T0UPDATE.Reg) +} + +// TIMG.T0ALARMLO +func (o *TIMG_Type) SetT0ALARMLO(value uint32) { + volatile.StoreUint32(&o.T0ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMLO() uint32 { + return volatile.LoadUint32(&o.T0ALARMLO.Reg) +} + +// TIMG.T0ALARMHI +func (o *TIMG_Type) SetT0ALARMHI(value uint32) { + volatile.StoreUint32(&o.T0ALARMHI.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMHI() uint32 { + return volatile.LoadUint32(&o.T0ALARMHI.Reg) +} + +// TIMG.T0LOADLO +func (o *TIMG_Type) SetT0LOADLO(value uint32) { + volatile.StoreUint32(&o.T0LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT0LOADLO() uint32 { + return volatile.LoadUint32(&o.T0LOADLO.Reg) +} + +// TIMG.T0LOADHI +func (o *TIMG_Type) SetT0LOADHI(value uint32) { + volatile.StoreUint32(&o.T0LOADHI.Reg, value) +} +func (o *TIMG_Type) GetT0LOADHI() uint32 { + return volatile.LoadUint32(&o.T0LOADHI.Reg) +} + +// TIMG.T0LOAD +func (o *TIMG_Type) SetT0LOAD(value uint32) { + volatile.StoreUint32(&o.T0LOAD.Reg, value) +} +func (o *TIMG_Type) GetT0LOAD() uint32 { + return volatile.LoadUint32(&o.T0LOAD.Reg) +} + +// TIMG.T1CONFIG +func (o *TIMG_Type) SetT1CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT1CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT1CONFIG_LEVEL_INT_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x800)|value<<11) +} +func (o *TIMG_Type) GetT1CONFIG_LEVEL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x800) >> 11 +} +func (o *TIMG_Type) SetT1CONFIG_EDGE_INT_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetT1CONFIG_EDGE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetT1CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT1CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT1CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT1CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT1CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT1CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT1CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT1CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T1LO +func (o *TIMG_Type) SetT1LO(value uint32) { + volatile.StoreUint32(&o.T1LO.Reg, value) +} +func (o *TIMG_Type) GetT1LO() uint32 { + return volatile.LoadUint32(&o.T1LO.Reg) +} + +// TIMG.T1HI +func (o *TIMG_Type) SetT1HI(value uint32) { + volatile.StoreUint32(&o.T1HI.Reg, value) +} +func (o *TIMG_Type) GetT1HI() uint32 { + return volatile.LoadUint32(&o.T1HI.Reg) +} + +// TIMG.T1UPDATE +func (o *TIMG_Type) SetT1UPDATE(value uint32) { + volatile.StoreUint32(&o.T1UPDATE.Reg, value) +} +func (o *TIMG_Type) GetT1UPDATE() uint32 { + return volatile.LoadUint32(&o.T1UPDATE.Reg) +} + +// TIMG.T1ALARMLO +func (o *TIMG_Type) SetT1ALARMLO(value uint32) { + volatile.StoreUint32(&o.T1ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT1ALARMLO() uint32 { + return volatile.LoadUint32(&o.T1ALARMLO.Reg) +} + +// TIMG.T1ALARMHI +func (o *TIMG_Type) SetT1ALARMHI(value uint32) { + volatile.StoreUint32(&o.T1ALARMHI.Reg, value) +} +func (o *TIMG_Type) GetT1ALARMHI() uint32 { + return volatile.LoadUint32(&o.T1ALARMHI.Reg) +} + +// TIMG.T1LOADLO +func (o *TIMG_Type) SetT1LOADLO(value uint32) { + volatile.StoreUint32(&o.T1LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT1LOADLO() uint32 { + return volatile.LoadUint32(&o.T1LOADLO.Reg) +} + +// TIMG.T1LOADHI +func (o *TIMG_Type) SetT1LOADHI(value uint32) { + volatile.StoreUint32(&o.T1LOADHI.Reg, value) +} +func (o *TIMG_Type) GetT1LOADHI() uint32 { + return volatile.LoadUint32(&o.T1LOADHI.Reg) +} + +// TIMG.T1LOAD +func (o *TIMG_Type) SetT1LOAD(value uint32) { + volatile.StoreUint32(&o.T1LOAD.Reg, value) +} +func (o *TIMG_Type) GetT1LOAD() uint32 { + return volatile.LoadUint32(&o.T1LOAD.Reg) +} + +// TIMG.WDTCONFIG0 +func (o *TIMG_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x4000)|value<<14) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x4000) >> 14 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x38000)|value<<15) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x38000) >> 15 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c0000)|value<<18) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c0000) >> 18 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_LEVEL_INT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200000)|value<<21) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_LEVEL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200000) >> 21 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EDGE_INT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400000)|value<<22) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EDGE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400000) >> 22 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1800000)|value<<23) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1800000) >> 23 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x6000000)|value<<25) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x6000000) >> 25 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x18000000)|value<<27) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x18000000) >> 27 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x60000000)|value<<29) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x60000000) >> 29 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// TIMG.WDTCONFIG1 +func (o *TIMG_Type) SetWDTCONFIG1_WDT_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_CLK_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0xffff0000) >> 16 +} + +// TIMG.WDTCONFIG2 +func (o *TIMG_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// TIMG.WDTCONFIG3 +func (o *TIMG_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// TIMG.WDTCONFIG4 +func (o *TIMG_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// TIMG.WDTCONFIG5 +func (o *TIMG_Type) SetWDTCONFIG5(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG5.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG5() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG5.Reg) +} + +// TIMG.WDTFEED +func (o *TIMG_Type) SetWDTFEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, value) +} +func (o *TIMG_Type) GetWDTFEED() uint32 { + return volatile.LoadUint32(&o.WDTFEED.Reg) +} + +// TIMG.WDTWPROTECT +func (o *TIMG_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *TIMG_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// TIMG.RTCCALICFG +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START_CYCLING(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START_CYCLING() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x6000)|value<<13) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x6000) >> 13 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_RDY(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x8000)|value<<15) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_RDY() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x8000) >> 15 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_MAX(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x7fff0000)|value<<16) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_MAX() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x7fff0000) >> 16 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x80000000) >> 31 +} + +// TIMG.RTCCALICFG1 +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_VALUE(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_VALUE() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0xffffff80) >> 7 +} + +// TIMG.LACTCONFIG +func (o *TIMG_Type) SetLACTCONFIG_LACT_RTC_ONLY(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x80)|value<<7) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_RTC_ONLY() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x80) >> 7 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_CPST_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x100)|value<<8) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_CPST_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x100) >> 8 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_LAC_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_LAC_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_LEVEL_INT_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x800)|value<<11) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_LEVEL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x800) >> 11 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_EDGE_INT_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_EDGE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_DIVIDER(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_INCREASE(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_INCREASE() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.LACTRTC +func (o *TIMG_Type) SetLACTRTC_LACT_RTC_STEP_LEN(value uint32) { + volatile.StoreUint32(&o.LACTRTC.Reg, volatile.LoadUint32(&o.LACTRTC.Reg)&^(0xffffffc0)|value<<6) +} +func (o *TIMG_Type) GetLACTRTC_LACT_RTC_STEP_LEN() uint32 { + return (volatile.LoadUint32(&o.LACTRTC.Reg) & 0xffffffc0) >> 6 +} + +// TIMG.LACTLO +func (o *TIMG_Type) SetLACTLO(value uint32) { + volatile.StoreUint32(&o.LACTLO.Reg, value) +} +func (o *TIMG_Type) GetLACTLO() uint32 { + return volatile.LoadUint32(&o.LACTLO.Reg) +} + +// TIMG.LACTHI +func (o *TIMG_Type) SetLACTHI(value uint32) { + volatile.StoreUint32(&o.LACTHI.Reg, value) +} +func (o *TIMG_Type) GetLACTHI() uint32 { + return volatile.LoadUint32(&o.LACTHI.Reg) +} + +// TIMG.LACTUPDATE +func (o *TIMG_Type) SetLACTUPDATE(value uint32) { + volatile.StoreUint32(&o.LACTUPDATE.Reg, value) +} +func (o *TIMG_Type) GetLACTUPDATE() uint32 { + return volatile.LoadUint32(&o.LACTUPDATE.Reg) +} + +// TIMG.LACTALARMLO +func (o *TIMG_Type) SetLACTALARMLO(value uint32) { + volatile.StoreUint32(&o.LACTALARMLO.Reg, value) +} +func (o *TIMG_Type) GetLACTALARMLO() uint32 { + return volatile.LoadUint32(&o.LACTALARMLO.Reg) +} + +// TIMG.LACTALARMHI +func (o *TIMG_Type) SetLACTALARMHI(value uint32) { + volatile.StoreUint32(&o.LACTALARMHI.Reg, value) +} +func (o *TIMG_Type) GetLACTALARMHI() uint32 { + return volatile.LoadUint32(&o.LACTALARMHI.Reg) +} + +// TIMG.LACTLOADLO +func (o *TIMG_Type) SetLACTLOADLO(value uint32) { + volatile.StoreUint32(&o.LACTLOADLO.Reg, value) +} +func (o *TIMG_Type) GetLACTLOADLO() uint32 { + return volatile.LoadUint32(&o.LACTLOADLO.Reg) +} + +// TIMG.LACTLOADHI +func (o *TIMG_Type) SetLACTLOADHI(value uint32) { + volatile.StoreUint32(&o.LACTLOADHI.Reg, value) +} +func (o *TIMG_Type) GetLACTLOADHI() uint32 { + return volatile.LoadUint32(&o.LACTLOADHI.Reg) +} + +// TIMG.LACTLOAD +func (o *TIMG_Type) SetLACTLOAD(value uint32) { + volatile.StoreUint32(&o.LACTLOAD.Reg, value) +} +func (o *TIMG_Type) GetLACTLOAD() uint32 { + return volatile.LoadUint32(&o.LACTLOAD.Reg) +} + +// TIMG.INT_ENA_TIMERS +func (o *TIMG_Type) SetINT_ENA_TIMERS_T0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_T1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x4) >> 2 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_LACT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x8)|value<<3) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_LACT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x8) >> 3 +} + +// TIMG.INT_RAW_TIMERS +func (o *TIMG_Type) SetINT_RAW_TIMERS_T0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_T1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x4) >> 2 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_LACT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x8)|value<<3) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_LACT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x8) >> 3 +} + +// TIMG.INT_ST_TIMERS +func (o *TIMG_Type) SetINT_ST_TIMERS_T0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_T1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x4) >> 2 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_LACT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x8)|value<<3) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_LACT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x8) >> 3 +} + +// TIMG.INT_CLR_TIMERS +func (o *TIMG_Type) SetINT_CLR_TIMERS_T0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_T1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x4) >> 2 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_LACT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x8)|value<<3) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_LACT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x8) >> 3 +} + +// TIMG.NTIMERS_DATE +func (o *TIMG_Type) SetNTIMERS_DATE(value uint32) { + volatile.StoreUint32(&o.NTIMERS_DATE.Reg, volatile.LoadUint32(&o.NTIMERS_DATE.Reg)&^(0xfffffff)|value) +} +func (o *TIMG_Type) GetNTIMERS_DATE() uint32 { + return volatile.LoadUint32(&o.NTIMERS_DATE.Reg) & 0xfffffff +} + +// TIMG.TIMGCLK +func (o *TIMG_Type) SetTIMGCLK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMGCLK.Reg, volatile.LoadUint32(&o.TIMGCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetTIMGCLK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TIMGCLK.Reg) & 0x80000000) >> 31 +} + +// Two-Wire Automotive Interface +type TWAI_Type struct { + MODE volatile.Register32 // 0x0 + CMD volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + INT_RAW volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + _ [4]byte + BUS_TIMING_0 volatile.Register32 // 0x18 + BUS_TIMING_1 volatile.Register32 // 0x1C + _ [12]byte + ARB_LOST_CAP volatile.Register32 // 0x2C + ERR_CODE_CAP volatile.Register32 // 0x30 + ERR_WARNING_LIMIT volatile.Register32 // 0x34 + RX_ERR_CNT volatile.Register32 // 0x38 + TX_ERR_CNT volatile.Register32 // 0x3C + DATA_0 volatile.Register32 // 0x40 + DATA_1 volatile.Register32 // 0x44 + DATA_2 volatile.Register32 // 0x48 + DATA_3 volatile.Register32 // 0x4C + DATA_4 volatile.Register32 // 0x50 + DATA_5 volatile.Register32 // 0x54 + DATA_6 volatile.Register32 // 0x58 + DATA_7 volatile.Register32 // 0x5C + DATA_8 volatile.Register32 // 0x60 + DATA_9 volatile.Register32 // 0x64 + DATA_10 volatile.Register32 // 0x68 + DATA_11 volatile.Register32 // 0x6C + DATA_12 volatile.Register32 // 0x70 + RX_MESSAGE_CNT volatile.Register32 // 0x74 + _ [4]byte + CLOCK_DIVIDER volatile.Register32 // 0x7C +} + +// TWAI.MODE: Mode Register +func (o *TWAI_Type) SetMODE_RESET_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetMODE_RESET_MODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x1 +} +func (o *TWAI_Type) SetMODE_LISTEN_ONLY_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetMODE_LISTEN_ONLY_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetMODE_SELF_TEST_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetMODE_SELF_TEST_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetMODE_RX_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetMODE_RX_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x8) >> 3 +} + +// TWAI.CMD: Command Register +func (o *TWAI_Type) SetCMD_TX_REQ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetCMD_TX_REQ() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *TWAI_Type) SetCMD_ABORT_TX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetCMD_ABORT_TX() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetCMD_RELEASE_BUF(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetCMD_RELEASE_BUF() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetCMD_CLR_OVERRUN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetCMD_CLR_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetCMD_SELF_RX_REQ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetCMD_SELF_RX_REQ() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10) >> 4 +} + +// TWAI.STATUS: Status register +func (o *TWAI_Type) SetSTATUS_RX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSTATUS_RX_BUF_ST() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *TWAI_Type) SetSTATUS_OVERRUN_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSTATUS_OVERRUN_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetSTATUS_TX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetSTATUS_TX_BUF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetSTATUS_TX_COMPLETE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetSTATUS_TX_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetSTATUS_RX_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetSTATUS_RX_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *TWAI_Type) SetSTATUS_TX_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetSTATUS_TX_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetSTATUS_ERR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetSTATUS_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetSTATUS_BUS_OFF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetSTATUS_BUS_OFF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetSTATUS_MISS_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetSTATUS_MISS_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} + +// TWAI.INT_RAW: Interrupt Register +func (o *TWAI_Type) SetINT_RAW_RX_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINT_RAW_RX_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *TWAI_Type) SetINT_RAW_TX_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINT_RAW_TX_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINT_RAW_ERR_WARN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINT_RAW_ERR_WARN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINT_RAW_OVERRUN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINT_RAW_OVERRUN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINT_RAW_ERR_PASSIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINT_RAW_ERR_PASSIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINT_RAW_ARB_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINT_RAW_ARB_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINT_RAW_BUS_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINT_RAW_BUS_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} + +// TWAI.INT_ENA: Interrupt Enable Register +func (o *TWAI_Type) SetINT_ENA_RX_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINT_ENA_RX_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *TWAI_Type) SetINT_ENA_TX_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINT_ENA_TX_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINT_ENA_ERR_WARN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINT_ENA_ERR_WARN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINT_ENA_OVERRUN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINT_ENA_OVERRUN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINT_ENA_ERR_PASSIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINT_ENA_ERR_PASSIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINT_ENA_ARB_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINT_ENA_ARB_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINT_ENA_BUS_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINT_ENA_BUS_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} + +// TWAI.BUS_TIMING_0: Bus Timing Register 0 +func (o *TWAI_Type) SetBUS_TIMING_0_BAUD_PRESC(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0x3f)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_0_BAUD_PRESC() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0x3f +} +func (o *TWAI_Type) SetBUS_TIMING_0_SYNC_JUMP_WIDTH(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0xc0)|value<<6) +} +func (o *TWAI_Type) GetBUS_TIMING_0_SYNC_JUMP_WIDTH() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0xc0) >> 6 +} + +// TWAI.BUS_TIMING_1: Bus Timing Register 1 +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG1(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0xf)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG1() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0xf +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG2(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x70)|value<<4) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG2() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x70) >> 4 +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SAMP(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SAMP() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x80) >> 7 +} + +// TWAI.ARB_LOST_CAP: Arbitration Lost Capture Register +func (o *TWAI_Type) SetARB_LOST_CAP(value uint32) { + volatile.StoreUint32(&o.ARB_LOST_CAP.Reg, volatile.LoadUint32(&o.ARB_LOST_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetARB_LOST_CAP() uint32 { + return volatile.LoadUint32(&o.ARB_LOST_CAP.Reg) & 0x1f +} + +// TWAI.ERR_CODE_CAP: Error Code Capture Register +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_SEGMENT(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_SEGMENT() uint32 { + return volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x1f +} +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_DIRECTION(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_TYPE(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0xc0)|value<<6) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_TYPE() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0xc0) >> 6 +} + +// TWAI.ERR_WARNING_LIMIT: Error Warning Limit Register +func (o *TWAI_Type) SetERR_WARNING_LIMIT(value uint32) { + volatile.StoreUint32(&o.ERR_WARNING_LIMIT.Reg, volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetERR_WARNING_LIMIT() uint32 { + return volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg) & 0xff +} + +// TWAI.RX_ERR_CNT: Receive Error Counter Register +func (o *TWAI_Type) SetRX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ERR_CNT.Reg, volatile.LoadUint32(&o.RX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetRX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.RX_ERR_CNT.Reg) & 0xff +} + +// TWAI.TX_ERR_CNT: Transmit Error Counter Register +func (o *TWAI_Type) SetTX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ERR_CNT.Reg, volatile.LoadUint32(&o.TX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetTX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.TX_ERR_CNT.Reg) & 0xff +} + +// TWAI.DATA_0: Data register 0 +func (o *TWAI_Type) SetDATA_0_TX_BYTE_0(value uint32) { + volatile.StoreUint32(&o.DATA_0.Reg, volatile.LoadUint32(&o.DATA_0.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_0_TX_BYTE_0() uint32 { + return volatile.LoadUint32(&o.DATA_0.Reg) & 0xff +} + +// TWAI.DATA_1: Data register 1 +func (o *TWAI_Type) SetDATA_1_TX_BYTE_1(value uint32) { + volatile.StoreUint32(&o.DATA_1.Reg, volatile.LoadUint32(&o.DATA_1.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_1_TX_BYTE_1() uint32 { + return volatile.LoadUint32(&o.DATA_1.Reg) & 0xff +} + +// TWAI.DATA_2: Data register 2 +func (o *TWAI_Type) SetDATA_2_TX_BYTE_2(value uint32) { + volatile.StoreUint32(&o.DATA_2.Reg, volatile.LoadUint32(&o.DATA_2.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_2_TX_BYTE_2() uint32 { + return volatile.LoadUint32(&o.DATA_2.Reg) & 0xff +} + +// TWAI.DATA_3: Data register 3 +func (o *TWAI_Type) SetDATA_3_TX_BYTE_3(value uint32) { + volatile.StoreUint32(&o.DATA_3.Reg, volatile.LoadUint32(&o.DATA_3.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_3_TX_BYTE_3() uint32 { + return volatile.LoadUint32(&o.DATA_3.Reg) & 0xff +} + +// TWAI.DATA_4: Data register 4 +func (o *TWAI_Type) SetDATA_4_TX_BYTE_4(value uint32) { + volatile.StoreUint32(&o.DATA_4.Reg, volatile.LoadUint32(&o.DATA_4.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_4_TX_BYTE_4() uint32 { + return volatile.LoadUint32(&o.DATA_4.Reg) & 0xff +} + +// TWAI.DATA_5: Data register 5 +func (o *TWAI_Type) SetDATA_5_TX_BYTE_5(value uint32) { + volatile.StoreUint32(&o.DATA_5.Reg, volatile.LoadUint32(&o.DATA_5.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_5_TX_BYTE_5() uint32 { + return volatile.LoadUint32(&o.DATA_5.Reg) & 0xff +} + +// TWAI.DATA_6: Data register 6 +func (o *TWAI_Type) SetDATA_6_TX_BYTE_6(value uint32) { + volatile.StoreUint32(&o.DATA_6.Reg, volatile.LoadUint32(&o.DATA_6.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_6_TX_BYTE_6() uint32 { + return volatile.LoadUint32(&o.DATA_6.Reg) & 0xff +} + +// TWAI.DATA_7: Data register 7 +func (o *TWAI_Type) SetDATA_7_TX_BYTE_7(value uint32) { + volatile.StoreUint32(&o.DATA_7.Reg, volatile.LoadUint32(&o.DATA_7.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_7_TX_BYTE_7() uint32 { + return volatile.LoadUint32(&o.DATA_7.Reg) & 0xff +} + +// TWAI.DATA_8: Data register 8 +func (o *TWAI_Type) SetDATA_8_TX_BYTE_8(value uint32) { + volatile.StoreUint32(&o.DATA_8.Reg, volatile.LoadUint32(&o.DATA_8.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_8_TX_BYTE_8() uint32 { + return volatile.LoadUint32(&o.DATA_8.Reg) & 0xff +} + +// TWAI.DATA_9: Data register 9 +func (o *TWAI_Type) SetDATA_9_TX_BYTE_9(value uint32) { + volatile.StoreUint32(&o.DATA_9.Reg, volatile.LoadUint32(&o.DATA_9.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_9_TX_BYTE_9() uint32 { + return volatile.LoadUint32(&o.DATA_9.Reg) & 0xff +} + +// TWAI.DATA_10: Data register 10 +func (o *TWAI_Type) SetDATA_10_TX_BYTE_10(value uint32) { + volatile.StoreUint32(&o.DATA_10.Reg, volatile.LoadUint32(&o.DATA_10.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_10_TX_BYTE_10() uint32 { + return volatile.LoadUint32(&o.DATA_10.Reg) & 0xff +} + +// TWAI.DATA_11: Data register 11 +func (o *TWAI_Type) SetDATA_11_TX_BYTE_11(value uint32) { + volatile.StoreUint32(&o.DATA_11.Reg, volatile.LoadUint32(&o.DATA_11.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_11_TX_BYTE_11() uint32 { + return volatile.LoadUint32(&o.DATA_11.Reg) & 0xff +} + +// TWAI.DATA_12: Data register 12 +func (o *TWAI_Type) SetDATA_12_TX_BYTE_12(value uint32) { + volatile.StoreUint32(&o.DATA_12.Reg, volatile.LoadUint32(&o.DATA_12.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_12_TX_BYTE_12() uint32 { + return volatile.LoadUint32(&o.DATA_12.Reg) & 0xff +} + +// TWAI.RX_MESSAGE_CNT: Receive Message Counter Register +func (o *TWAI_Type) SetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER(value uint32) { + volatile.StoreUint32(&o.RX_MESSAGE_CNT.Reg, volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg)&^(0x7f)|value) +} +func (o *TWAI_Type) GetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER() uint32 { + return volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg) & 0x7f +} + +// TWAI.CLOCK_DIVIDER: Clock Divider register +func (o *TWAI_Type) SetCLOCK_DIVIDER_CD(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CD() uint32 { + return volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0xff +} +func (o *TWAI_Type) SetCLOCK_DIVIDER_CLOCK_OFF(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CLOCK_OFF() uint32 { + return (volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0x100) >> 8 +} + +// UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +type UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV volatile.Register32 // 0x14 + AUTOBAUD volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0 volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + LOWPULSE volatile.Register32 // 0x28 + HIGHPULSE volatile.Register32 // 0x2C + RXD_CNT volatile.Register32 // 0x30 + FLOW_CONF volatile.Register32 // 0x34 + SLEEP_CONF volatile.Register32 // 0x38 + SWFC_CONF volatile.Register32 // 0x3C + IDLE_CONF volatile.Register32 // 0x40 + RS485_CONF volatile.Register32 // 0x44 + AT_CMD_PRECNT volatile.Register32 // 0x48 + AT_CMD_POSTCNT volatile.Register32 // 0x4C + AT_CMD_GAPTOUT volatile.Register32 // 0x50 + AT_CMD_CHAR volatile.Register32 // 0x54 + MEM_CONF volatile.Register32 // 0x58 + MEM_TX_STATUS volatile.Register32 // 0x5C + MEM_RX_STATUS volatile.Register32 // 0x60 + MEM_CNT_STATUS volatile.Register32 // 0x64 + POSPULSE volatile.Register32 // 0x68 + NEGPULSE volatile.Register32 // 0x6C + _ [8]byte + DATE volatile.Register32 // 0x78 + ID volatile.Register32 // 0x7C +} + +// UART.FIFO +func (o *UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// UART.INT_RAW +func (o *UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_RAW_RS485_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_RAW_RS485_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_RAW_RS485_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_RAW_RS485_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_RAW_RS485_CLASH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_RAW_RS485_CLASH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} + +// UART.INT_ST +func (o *UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ST_RS485_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ST_RS485_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ST_RS485_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ST_RS485_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ST_RS485_CLASH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ST_RS485_CLASH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} + +// UART.INT_ENA +func (o *UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ENA_RS485_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ENA_RS485_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ENA_RS485_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ENA_RS485_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ENA_RS485_CLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ENA_RS485_CLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} + +// UART.INT_CLR +func (o *UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_CLR_RS485_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_CLR_RS485_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_CLR_RS485_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_CLR_RS485_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_CLR_RS485_CLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_CLR_RS485_CLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} + +// UART.CLKDIV +func (o *UART_Type) SetCLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetCLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xfffff +} +func (o *UART_Type) SetCLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xf00000)|value<<20) +} +func (o *UART_Type) GetCLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xf00000) >> 20 +} + +// UART.AUTOBAUD +func (o *UART_Type) SetAUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.AUTOBAUD.Reg, volatile.LoadUint32(&o.AUTOBAUD.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetAUTOBAUD_EN() uint32 { + return volatile.LoadUint32(&o.AUTOBAUD.Reg) & 0x1 +} +func (o *UART_Type) SetAUTOBAUD_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.AUTOBAUD.Reg, volatile.LoadUint32(&o.AUTOBAUD.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAUTOBAUD_GLITCH_FILT() uint32 { + return (volatile.LoadUint32(&o.AUTOBAUD.Reg) & 0xff00) >> 8 +} + +// UART.STATUS +func (o *UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xff +} +func (o *UART_Type) SetSTATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf00)|value<<8) +} +func (o *UART_Type) GetSTATUS_ST_URX_OUT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf00) >> 8 +} +func (o *UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xff0000) >> 16 +} +func (o *UART_Type) SetSTATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf000000)|value<<24) +} +func (o *UART_Type) GetSTATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf000000) >> 24 +} +func (o *UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// UART.CONF0 +func (o *UART_Type) SetCONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetCONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UART_Type) SetCONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetCONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetCONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0xc)|value<<2) +} +func (o *UART_Type) GetCONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0xc) >> 2 +} +func (o *UART_Type) SetCONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x30)|value<<4) +} +func (o *UART_Type) GetCONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x30) >> 4 +} +func (o *UART_Type) SetCONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetCONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetCONF0_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetCONF0_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetCONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetCONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetCONF0_IRDA_DPLX(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetCONF0_IRDA_DPLX() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetCONF0_IRDA_TX_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetCONF0_IRDA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetCONF0_IRDA_WCTL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetCONF0_IRDA_WCTL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetCONF0_IRDA_TX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetCONF0_IRDA_TX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetCONF0_IRDA_RX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetCONF0_IRDA_RX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetCONF0_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetCONF0_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetCONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetCONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetCONF0_IRDA_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF0_IRDA_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF0_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF0_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF0_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF0_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF0_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF0_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetCONF0_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCONF0_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCONF0_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF0_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCONF0_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCONF0_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCONF0_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCONF0_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCONF0_TICK_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCONF0_TICK_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000000) >> 27 +} + +// UART.CONF1 +func (o *UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x7f)|value) +} +func (o *UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x7f +} +func (o *UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x7f00)|value<<8) +} +func (o *UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x7f00) >> 8 +} +func (o *UART_Type) SetCONF1_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x7f0000)|value<<16) +} +func (o *UART_Type) GetCONF1_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x7f0000) >> 16 +} +func (o *UART_Type) SetCONF1_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF1_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCONF1_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x7f000000)|value<<24) +} +func (o *UART_Type) GetCONF1_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x7f000000) >> 24 +} +func (o *UART_Type) SetCONF1_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetCONF1_RX_TOUT_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000000) >> 31 +} + +// UART.LOWPULSE +func (o *UART_Type) SetLOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.LOWPULSE.Reg, volatile.LoadUint32(&o.LOWPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetLOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.LOWPULSE.Reg) & 0xfffff +} + +// UART.HIGHPULSE +func (o *UART_Type) SetHIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.HIGHPULSE.Reg, volatile.LoadUint32(&o.HIGHPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetHIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.HIGHPULSE.Reg) & 0xfffff +} + +// UART.RXD_CNT +func (o *UART_Type) SetRXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.RXD_CNT.Reg, volatile.LoadUint32(&o.RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetRXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.RXD_CNT.Reg) & 0x3ff +} + +// UART.FLOW_CONF +func (o *UART_Type) SetFLOW_CONF_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetFLOW_CONF_SW_FLOW_CON_EN() uint32 { + return volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetFLOW_CONF_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetFLOW_CONF_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x20) >> 5 +} + +// UART.SLEEP_CONF +func (o *UART_Type) SetSLEEP_CONF_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF.Reg, volatile.LoadUint32(&o.SLEEP_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSLEEP_CONF_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF.Reg) & 0x3ff +} + +// UART.SWFC_CONF +func (o *UART_Type) SetSWFC_CONF_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF.Reg, volatile.LoadUint32(&o.SWFC_CONF.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSWFC_CONF_XON_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF.Reg) & 0xff +} +func (o *UART_Type) SetSWFC_CONF_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF.Reg, volatile.LoadUint32(&o.SWFC_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSWFC_CONF_XOFF_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetSWFC_CONF_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF.Reg, volatile.LoadUint32(&o.SWFC_CONF.Reg)&^(0xff0000)|value<<16) +} +func (o *UART_Type) GetSWFC_CONF_XON_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF.Reg) & 0xff0000) >> 16 +} +func (o *UART_Type) SetSWFC_CONF_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF.Reg, volatile.LoadUint32(&o.SWFC_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *UART_Type) GetSWFC_CONF_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF.Reg) & 0xff000000) >> 24 +} + +// UART.IDLE_CONF +func (o *UART_Type) SetIDLE_CONF_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetIDLE_CONF_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0x3ff +} +func (o *UART_Type) SetIDLE_CONF_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *UART_Type) GetIDLE_CONF_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xffc00) >> 10 +} +func (o *UART_Type) SetIDLE_CONF_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xff00000)|value<<20) +} +func (o *UART_Type) GetIDLE_CONF_TX_BRK_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xff00000) >> 20 +} + +// UART.RS485_CONF +func (o *UART_Type) SetRS485_CONF_RS485_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetRS485_CONF_RS485_EN() uint32 { + return volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetRS485_CONF_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetRS485_CONF_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetRS485_CONF_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetRS485_CONF_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetRS485_CONF_RS485TX_RX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetRS485_CONF_RS485TX_RX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetRS485_CONF_RS485RXBY_TX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetRS485_CONF_RS485RXBY_TX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetRS485_CONF_RS485_RX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetRS485_CONF_RS485_RX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetRS485_CONF_RS485_TX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x3c0)|value<<6) +} +func (o *UART_Type) GetRS485_CONF_RS485_TX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x3c0) >> 6 +} + +// UART.AT_CMD_PRECNT +func (o *UART_Type) SetAT_CMD_PRECNT_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg)&^(0xffffff)|value) +} +func (o *UART_Type) GetAT_CMD_PRECNT_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg) & 0xffffff +} + +// UART.AT_CMD_POSTCNT +func (o *UART_Type) SetAT_CMD_POSTCNT_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg)&^(0xffffff)|value) +} +func (o *UART_Type) GetAT_CMD_POSTCNT_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg) & 0xffffff +} + +// UART.AT_CMD_GAPTOUT +func (o *UART_Type) SetAT_CMD_GAPTOUT_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg)&^(0xffffff)|value) +} +func (o *UART_Type) GetAT_CMD_GAPTOUT_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg) & 0xffffff +} + +// UART.AT_CMD_CHAR +func (o *UART_Type) SetAT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetAT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff +} +func (o *UART_Type) SetAT_CMD_CHAR_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAT_CMD_CHAR_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff00) >> 8 +} + +// UART.MEM_CONF +func (o *UART_Type) SetMEM_CONF_MEM_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetMEM_CONF_MEM_PD() uint32 { + return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetMEM_CONF_RX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x78)|value<<3) +} +func (o *UART_Type) GetMEM_CONF_RX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x78) >> 3 +} +func (o *UART_Type) SetMEM_CONF_TX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x780)|value<<7) +} +func (o *UART_Type) GetMEM_CONF_TX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x780) >> 7 +} +func (o *UART_Type) SetMEM_CONF_RX_FLOW_THRHD_H3(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x38000)|value<<15) +} +func (o *UART_Type) GetMEM_CONF_RX_FLOW_THRHD_H3() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x38000) >> 15 +} +func (o *UART_Type) SetMEM_CONF_RX_TOUT_THRHD_H3(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1c0000)|value<<18) +} +func (o *UART_Type) GetMEM_CONF_RX_TOUT_THRHD_H3() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1c0000) >> 18 +} +func (o *UART_Type) SetMEM_CONF_XON_THRESHOLD_H2(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x600000)|value<<21) +} +func (o *UART_Type) GetMEM_CONF_XON_THRESHOLD_H2() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x600000) >> 21 +} +func (o *UART_Type) SetMEM_CONF_XOFF_THRESHOLD_H2(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1800000)|value<<23) +} +func (o *UART_Type) GetMEM_CONF_XOFF_THRESHOLD_H2() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1800000) >> 23 +} +func (o *UART_Type) SetMEM_CONF_RX_MEM_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xe000000)|value<<25) +} +func (o *UART_Type) GetMEM_CONF_RX_MEM_FULL_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xe000000) >> 25 +} +func (o *UART_Type) SetMEM_CONF_TX_MEM_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x70000000)|value<<28) +} +func (o *UART_Type) GetMEM_CONF_TX_MEM_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x70000000) >> 28 +} + +// UART.MEM_TX_STATUS +func (o *UART_Type) SetMEM_TX_STATUS(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0xffffff)|value) +} +func (o *UART_Type) GetMEM_TX_STATUS() uint32 { + return volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0xffffff +} + +// UART.MEM_RX_STATUS +func (o *UART_Type) SetMEM_RX_STATUS(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xffffff)|value) +} +func (o *UART_Type) GetMEM_RX_STATUS() uint32 { + return volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xffffff +} +func (o *UART_Type) SetMEM_RX_STATUS_MEM_RX_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1ffc)|value<<2) +} +func (o *UART_Type) GetMEM_RX_STATUS_MEM_RX_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1ffc) >> 2 +} +func (o *UART_Type) SetMEM_RX_STATUS_MEM_RX_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xffe000)|value<<13) +} +func (o *UART_Type) GetMEM_RX_STATUS_MEM_RX_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xffe000) >> 13 +} + +// UART.MEM_CNT_STATUS +func (o *UART_Type) SetMEM_CNT_STATUS_RX_MEM_CNT(value uint32) { + volatile.StoreUint32(&o.MEM_CNT_STATUS.Reg, volatile.LoadUint32(&o.MEM_CNT_STATUS.Reg)&^(0x7)|value) +} +func (o *UART_Type) GetMEM_CNT_STATUS_RX_MEM_CNT() uint32 { + return volatile.LoadUint32(&o.MEM_CNT_STATUS.Reg) & 0x7 +} +func (o *UART_Type) SetMEM_CNT_STATUS_TX_MEM_CNT(value uint32) { + volatile.StoreUint32(&o.MEM_CNT_STATUS.Reg, volatile.LoadUint32(&o.MEM_CNT_STATUS.Reg)&^(0x38)|value<<3) +} +func (o *UART_Type) GetMEM_CNT_STATUS_TX_MEM_CNT() uint32 { + return (volatile.LoadUint32(&o.MEM_CNT_STATUS.Reg) & 0x38) >> 3 +} + +// UART.POSPULSE +func (o *UART_Type) SetPOSPULSE_POSEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.POSPULSE.Reg, volatile.LoadUint32(&o.POSPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetPOSPULSE_POSEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.POSPULSE.Reg) & 0xfffff +} + +// UART.NEGPULSE +func (o *UART_Type) SetNEGPULSE_NEGEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.NEGPULSE.Reg, volatile.LoadUint32(&o.NEGPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetNEGPULSE_NEGEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.NEGPULSE.Reg) & 0xfffff +} + +// UART.DATE +func (o *UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// UART.ID +func (o *UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, value) +} +func (o *UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) +} + +// Universal Host Controller Interface 0 +type UHCI_Type struct { + CONF0 volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + DMA_OUT_STATUS volatile.Register32 // 0x14 + DMA_OUT_PUSH volatile.Register32 // 0x18 + DMA_IN_STATUS volatile.Register32 // 0x1C + DMA_IN_POP volatile.Register32 // 0x20 + DMA_OUT_LINK volatile.Register32 // 0x24 + DMA_IN_LINK volatile.Register32 // 0x28 + CONF1 volatile.Register32 // 0x2C + STATE0 volatile.Register32 // 0x30 + STATE1 volatile.Register32 // 0x34 + DMA_OUT_EOF_DES_ADDR volatile.Register32 // 0x38 + DMA_IN_SUC_EOF_DES_ADDR volatile.Register32 // 0x3C + DMA_IN_ERR_EOF_DES_ADDR volatile.Register32 // 0x40 + DMA_OUT_EOF_BFR_DES_ADDR volatile.Register32 // 0x44 + AHB_TEST volatile.Register32 // 0x48 + DMA_IN_DSCR volatile.Register32 // 0x4C + DMA_IN_DSCR_BF0 volatile.Register32 // 0x50 + DMA_IN_DSCR_BF1 volatile.Register32 // 0x54 + DMA_OUT_DSCR volatile.Register32 // 0x58 + DMA_OUT_DSCR_BF0 volatile.Register32 // 0x5C + DMA_OUT_DSCR_BF1 volatile.Register32 // 0x60 + ESCAPE_CONF volatile.Register32 // 0x64 + HUNG_CONF volatile.Register32 // 0x68 + ACK_NUM volatile.Register32 // 0x6C + RX_HEAD volatile.Register32 // 0x70 + QUICK_SENT volatile.Register32 // 0x74 + Q0_WORD0 volatile.Register32 // 0x78 + Q0_WORD1 volatile.Register32 // 0x7C + Q1_WORD0 volatile.Register32 // 0x80 + Q1_WORD1 volatile.Register32 // 0x84 + Q2_WORD0 volatile.Register32 // 0x88 + Q2_WORD1 volatile.Register32 // 0x8C + Q3_WORD0 volatile.Register32 // 0x90 + Q3_WORD1 volatile.Register32 // 0x94 + Q4_WORD0 volatile.Register32 // 0x98 + Q4_WORD1 volatile.Register32 // 0x9C + Q5_WORD0 volatile.Register32 // 0xA0 + Q5_WORD1 volatile.Register32 // 0xA4 + Q6_WORD0 volatile.Register32 // 0xA8 + Q6_WORD1 volatile.Register32 // 0xAC + ESC_CONF0 volatile.Register32 // 0xB0 + ESC_CONF1 volatile.Register32 // 0xB4 + ESC_CONF2 volatile.Register32 // 0xB8 + ESC_CONF3 volatile.Register32 // 0xBC + PKT_THRES volatile.Register32 // 0xC0 + _ [56]byte + DATE volatile.Register32 // 0xFC +} + +// UHCI.CONF0 +func (o *UHCI_Type) SetCONF0_IN_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF0_IN_RST() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF0_OUT_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF0_OUT_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF0_AHBM_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF0_AHBM_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF0_AHBM_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF0_AHBM_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF0_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF0_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF0_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF0_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF0_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetCONF0_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetCONF0_OUT_NO_RESTART_CLR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF0_OUT_NO_RESTART_CLR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF0_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF0_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetCONF0_UART0_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetCONF0_UART0_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetCONF0_UART1_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetCONF0_UART1_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetCONF0_UART2_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetCONF0_UART2_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetCONF0_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetCONF0_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetCONF0_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetCONF0_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetCONF0_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UHCI_Type) GetCONF0_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *UHCI_Type) SetCONF0_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetCONF0_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetCONF0_SEPER_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetCONF0_SEPER_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *UHCI_Type) SetCONF0_HEAD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UHCI_Type) GetCONF0_HEAD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *UHCI_Type) SetCONF0_CRC_REC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UHCI_Type) GetCONF0_CRC_REC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *UHCI_Type) SetCONF0_UART_IDLE_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UHCI_Type) GetCONF0_UART_IDLE_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *UHCI_Type) SetCONF0_LEN_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UHCI_Type) GetCONF0_LEN_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *UHCI_Type) SetCONF0_ENCODE_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UHCI_Type) GetCONF0_ENCODE_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *UHCI_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UHCI_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *UHCI_Type) SetCONF0_UART_RX_BRK_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UHCI_Type) GetCONF0_UART_RX_BRK_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} + +// UHCI.INT_RAW +func (o *UHCI_Type) SetINT_RAW_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_RAW_RX_START_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_RAW_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_RAW_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_RAW_IN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_RAW_IN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_RAW_IN_SUC_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_RAW_IN_SUC_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_RAW_IN_ERR_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_RAW_IN_ERR_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_RAW_OUT_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_RAW_OUT_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetINT_RAW_IN_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetINT_RAW_IN_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetINT_RAW_OUT_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetINT_RAW_OUT_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetINT_RAW_IN_DSCR_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetINT_RAW_IN_DSCR_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetINT_RAW_OUTLINK_EOF_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetINT_RAW_OUTLINK_EOF_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetINT_RAW_OUT_TOTAL_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetINT_RAW_OUT_TOTAL_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetINT_RAW_SEND_S_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UHCI_Type) GetINT_RAW_SEND_S_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UHCI_Type) SetINT_RAW_SEND_A_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetINT_RAW_SEND_A_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetINT_RAW_DMA_INFIFO_FULL_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetINT_RAW_DMA_INFIFO_FULL_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} + +// UHCI.INT_ST +func (o *UHCI_Type) SetINT_ST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ST_RX_START_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ST_IN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ST_IN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ST_IN_SUC_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ST_IN_SUC_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ST_IN_ERR_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ST_IN_ERR_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ST_OUT_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ST_OUT_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ST_OUT_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ST_OUT_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetINT_ST_IN_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetINT_ST_IN_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetINT_ST_OUT_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetINT_ST_OUT_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetINT_ST_IN_DSCR_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetINT_ST_IN_DSCR_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetINT_ST_OUTLINK_EOF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetINT_ST_OUTLINK_EOF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetINT_ST_OUT_TOTAL_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetINT_ST_OUT_TOTAL_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetINT_ST_SEND_S_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UHCI_Type) GetINT_ST_SEND_S_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UHCI_Type) SetINT_ST_SEND_A_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetINT_ST_SEND_A_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetINT_ST_DMA_INFIFO_FULL_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetINT_ST_DMA_INFIFO_FULL_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} + +// UHCI.INT_ENA +func (o *UHCI_Type) SetINT_ENA_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ENA_RX_START_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ENA_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ENA_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ENA_IN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ENA_IN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ENA_IN_SUC_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ENA_IN_SUC_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ENA_IN_ERR_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ENA_IN_ERR_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ENA_OUT_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ENA_OUT_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ENA_OUT_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ENA_OUT_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetINT_ENA_IN_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetINT_ENA_IN_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetINT_ENA_OUT_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetINT_ENA_OUT_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetINT_ENA_IN_DSCR_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetINT_ENA_IN_DSCR_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetINT_ENA_OUTLINK_EOF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetINT_ENA_OUTLINK_EOF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetINT_ENA_OUT_TOTAL_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetINT_ENA_OUT_TOTAL_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetINT_ENA_SEND_S_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UHCI_Type) GetINT_ENA_SEND_S_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UHCI_Type) SetINT_ENA_SEND_A_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetINT_ENA_SEND_A_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetINT_ENA_DMA_INFIFO_FULL_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetINT_ENA_DMA_INFIFO_FULL_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} + +// UHCI.INT_CLR +func (o *UHCI_Type) SetINT_CLR_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_CLR_RX_START_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_CLR_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_CLR_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_CLR_IN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_CLR_IN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_CLR_IN_SUC_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_CLR_IN_SUC_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_CLR_IN_ERR_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_CLR_IN_ERR_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_CLR_OUT_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_CLR_OUT_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_CLR_OUT_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_CLR_OUT_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetINT_CLR_IN_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetINT_CLR_IN_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetINT_CLR_OUT_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetINT_CLR_OUT_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetINT_CLR_IN_DSCR_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetINT_CLR_IN_DSCR_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetINT_CLR_OUTLINK_EOF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetINT_CLR_OUTLINK_EOF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetINT_CLR_OUT_TOTAL_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetINT_CLR_OUT_TOTAL_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetINT_CLR_SEND_S_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UHCI_Type) GetINT_CLR_SEND_S_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UHCI_Type) SetINT_CLR_SEND_A_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetINT_CLR_SEND_A_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetINT_CLR_DMA_INFIFO_FULL_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetINT_CLR_DMA_INFIFO_FULL_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} + +// UHCI.DMA_OUT_STATUS +func (o *UHCI_Type) SetDMA_OUT_STATUS_OUT_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_STATUS.Reg, volatile.LoadUint32(&o.DMA_OUT_STATUS.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetDMA_OUT_STATUS_OUT_FULL() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_STATUS.Reg) & 0x1 +} +func (o *UHCI_Type) SetDMA_OUT_STATUS_OUT_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_STATUS.Reg, volatile.LoadUint32(&o.DMA_OUT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetDMA_OUT_STATUS_OUT_EMPTY() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_STATUS.Reg) & 0x2) >> 1 +} + +// UHCI.DMA_OUT_PUSH +func (o *UHCI_Type) SetDMA_OUT_PUSH_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_PUSH.Reg, volatile.LoadUint32(&o.DMA_OUT_PUSH.Reg)&^(0x1ff)|value) +} +func (o *UHCI_Type) GetDMA_OUT_PUSH_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_PUSH.Reg) & 0x1ff +} +func (o *UHCI_Type) SetDMA_OUT_PUSH_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_PUSH.Reg, volatile.LoadUint32(&o.DMA_OUT_PUSH.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetDMA_OUT_PUSH_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_PUSH.Reg) & 0x10000) >> 16 +} + +// UHCI.DMA_IN_STATUS +func (o *UHCI_Type) SetDMA_IN_STATUS_IN_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_IN_STATUS.Reg, volatile.LoadUint32(&o.DMA_IN_STATUS.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetDMA_IN_STATUS_IN_FULL() uint32 { + return volatile.LoadUint32(&o.DMA_IN_STATUS.Reg) & 0x1 +} +func (o *UHCI_Type) SetDMA_IN_STATUS_IN_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_IN_STATUS.Reg, volatile.LoadUint32(&o.DMA_IN_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetDMA_IN_STATUS_IN_EMPTY() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_STATUS.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetDMA_IN_STATUS_RX_ERR_CAUSE(value uint32) { + volatile.StoreUint32(&o.DMA_IN_STATUS.Reg, volatile.LoadUint32(&o.DMA_IN_STATUS.Reg)&^(0x70)|value<<4) +} +func (o *UHCI_Type) GetDMA_IN_STATUS_RX_ERR_CAUSE() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_STATUS.Reg) & 0x70) >> 4 +} + +// UHCI.DMA_IN_POP +func (o *UHCI_Type) SetDMA_IN_POP_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DMA_IN_POP.Reg, volatile.LoadUint32(&o.DMA_IN_POP.Reg)&^(0xfff)|value) +} +func (o *UHCI_Type) GetDMA_IN_POP_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DMA_IN_POP.Reg) & 0xfff +} +func (o *UHCI_Type) SetDMA_IN_POP_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_POP.Reg, volatile.LoadUint32(&o.DMA_IN_POP.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetDMA_IN_POP_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_POP.Reg) & 0x10000) >> 16 +} + +// UHCI.DMA_OUT_LINK +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0xfffff)|value) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0xfffff +} +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x10000000) >> 28 +} +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x20000000) >> 29 +} +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x40000000) >> 30 +} +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x80000000) >> 31 +} + +// UHCI.DMA_IN_LINK +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0xfffff)|value) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0xfffff +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x100000)|value<<20) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x100000) >> 20 +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x10000000) >> 28 +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_START(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x20000000) >> 29 +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x40000000) >> 30 +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x80000000) >> 31 +} + +// UHCI.CONF1 +func (o *UHCI_Type) SetCONF1_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF1_CHECK_SUM_EN() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF1_CHECK_SEQ_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF1_CHECK_SEQ_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF1_CRC_DISABLE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF1_CRC_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF1_SAVE_HEAD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF1_SAVE_HEAD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF1_TX_CHECK_SUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF1_TX_CHECK_SUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF1_TX_ACK_NUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF1_TX_ACK_NUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF1_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetCONF1_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetCONF1_WAIT_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF1_WAIT_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF1_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF1_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetCONF1_DMA_INFIFO_FULL_THRS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1ffe00)|value<<9) +} +func (o *UHCI_Type) GetCONF1_DMA_INFIFO_FULL_THRS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x1ffe00) >> 9 +} + +// UHCI.STATE0 +func (o *UHCI_Type) SetSTATE0(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, value) +} +func (o *UHCI_Type) GetSTATE0() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) +} + +// UHCI.STATE1 +func (o *UHCI_Type) SetSTATE1(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, value) +} +func (o *UHCI_Type) GetSTATE1() uint32 { + return volatile.LoadUint32(&o.STATE1.Reg) +} + +// UHCI.DMA_OUT_EOF_DES_ADDR +func (o *UHCI_Type) SetDMA_OUT_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_EOF_DES_ADDR.Reg, value) +} +func (o *UHCI_Type) GetDMA_OUT_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_EOF_DES_ADDR.Reg) +} + +// UHCI.DMA_IN_SUC_EOF_DES_ADDR +func (o *UHCI_Type) SetDMA_IN_SUC_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_SUC_EOF_DES_ADDR.Reg, value) +} +func (o *UHCI_Type) GetDMA_IN_SUC_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_SUC_EOF_DES_ADDR.Reg) +} + +// UHCI.DMA_IN_ERR_EOF_DES_ADDR +func (o *UHCI_Type) SetDMA_IN_ERR_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_ERR_EOF_DES_ADDR.Reg, value) +} +func (o *UHCI_Type) GetDMA_IN_ERR_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_ERR_EOF_DES_ADDR.Reg) +} + +// UHCI.DMA_OUT_EOF_BFR_DES_ADDR +func (o *UHCI_Type) SetDMA_OUT_EOF_BFR_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_EOF_BFR_DES_ADDR.Reg, value) +} +func (o *UHCI_Type) GetDMA_OUT_EOF_BFR_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_EOF_BFR_DES_ADDR.Reg) +} + +// UHCI.AHB_TEST +func (o *UHCI_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *UHCI_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *UHCI_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// UHCI.DMA_IN_DSCR +func (o *UHCI_Type) SetDMA_IN_DSCR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_DSCR.Reg, value) +} +func (o *UHCI_Type) GetDMA_IN_DSCR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_DSCR.Reg) +} + +// UHCI.DMA_IN_DSCR_BF0 +func (o *UHCI_Type) SetDMA_IN_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.DMA_IN_DSCR_BF0.Reg, value) +} +func (o *UHCI_Type) GetDMA_IN_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.DMA_IN_DSCR_BF0.Reg) +} + +// UHCI.DMA_IN_DSCR_BF1 +func (o *UHCI_Type) SetDMA_IN_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.DMA_IN_DSCR_BF1.Reg, value) +} +func (o *UHCI_Type) GetDMA_IN_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.DMA_IN_DSCR_BF1.Reg) +} + +// UHCI.DMA_OUT_DSCR +func (o *UHCI_Type) SetDMA_OUT_DSCR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_DSCR.Reg, value) +} +func (o *UHCI_Type) GetDMA_OUT_DSCR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_DSCR.Reg) +} + +// UHCI.DMA_OUT_DSCR_BF0 +func (o *UHCI_Type) SetDMA_OUT_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_DSCR_BF0.Reg, value) +} +func (o *UHCI_Type) GetDMA_OUT_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_DSCR_BF0.Reg) +} + +// UHCI.DMA_OUT_DSCR_BF1 +func (o *UHCI_Type) SetDMA_OUT_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_DSCR_BF1.Reg, value) +} +func (o *UHCI_Type) GetDMA_OUT_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_DSCR_BF1.Reg) +} + +// UHCI.ESCAPE_CONF +func (o *UHCI_Type) SetESCAPE_CONF_TX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_C0_ESC_EN() uint32 { + return volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_C0_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x80) >> 7 +} + +// UHCI.HUNG_CONF +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff000) >> 12 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700000) >> 20 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800000) >> 23 +} + +// UHCI.RX_HEAD +func (o *UHCI_Type) SetRX_HEAD(value uint32) { + volatile.StoreUint32(&o.RX_HEAD.Reg, value) +} +func (o *UHCI_Type) GetRX_HEAD() uint32 { + return volatile.LoadUint32(&o.RX_HEAD.Reg) +} + +// UHCI.QUICK_SENT +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_NUM() uint32 { + return volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x7 +} +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x70)|value<<4) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_NUM() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x70) >> 4 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x80) >> 7 +} + +// UHCI.Q0_WORD0 +func (o *UHCI_Type) SetQ0_WORD0(value uint32) { + volatile.StoreUint32(&o.Q0_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ0_WORD0() uint32 { + return volatile.LoadUint32(&o.Q0_WORD0.Reg) +} + +// UHCI.Q0_WORD1 +func (o *UHCI_Type) SetQ0_WORD1(value uint32) { + volatile.StoreUint32(&o.Q0_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ0_WORD1() uint32 { + return volatile.LoadUint32(&o.Q0_WORD1.Reg) +} + +// UHCI.Q1_WORD0 +func (o *UHCI_Type) SetQ1_WORD0(value uint32) { + volatile.StoreUint32(&o.Q1_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ1_WORD0() uint32 { + return volatile.LoadUint32(&o.Q1_WORD0.Reg) +} + +// UHCI.Q1_WORD1 +func (o *UHCI_Type) SetQ1_WORD1(value uint32) { + volatile.StoreUint32(&o.Q1_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ1_WORD1() uint32 { + return volatile.LoadUint32(&o.Q1_WORD1.Reg) +} + +// UHCI.Q2_WORD0 +func (o *UHCI_Type) SetQ2_WORD0(value uint32) { + volatile.StoreUint32(&o.Q2_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ2_WORD0() uint32 { + return volatile.LoadUint32(&o.Q2_WORD0.Reg) +} + +// UHCI.Q2_WORD1 +func (o *UHCI_Type) SetQ2_WORD1(value uint32) { + volatile.StoreUint32(&o.Q2_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ2_WORD1() uint32 { + return volatile.LoadUint32(&o.Q2_WORD1.Reg) +} + +// UHCI.Q3_WORD0 +func (o *UHCI_Type) SetQ3_WORD0(value uint32) { + volatile.StoreUint32(&o.Q3_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ3_WORD0() uint32 { + return volatile.LoadUint32(&o.Q3_WORD0.Reg) +} + +// UHCI.Q3_WORD1 +func (o *UHCI_Type) SetQ3_WORD1(value uint32) { + volatile.StoreUint32(&o.Q3_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ3_WORD1() uint32 { + return volatile.LoadUint32(&o.Q3_WORD1.Reg) +} + +// UHCI.Q4_WORD0 +func (o *UHCI_Type) SetQ4_WORD0(value uint32) { + volatile.StoreUint32(&o.Q4_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ4_WORD0() uint32 { + return volatile.LoadUint32(&o.Q4_WORD0.Reg) +} + +// UHCI.Q4_WORD1 +func (o *UHCI_Type) SetQ4_WORD1(value uint32) { + volatile.StoreUint32(&o.Q4_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ4_WORD1() uint32 { + return volatile.LoadUint32(&o.Q4_WORD1.Reg) +} + +// UHCI.Q5_WORD0 +func (o *UHCI_Type) SetQ5_WORD0(value uint32) { + volatile.StoreUint32(&o.Q5_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ5_WORD0() uint32 { + return volatile.LoadUint32(&o.Q5_WORD0.Reg) +} + +// UHCI.Q5_WORD1 +func (o *UHCI_Type) SetQ5_WORD1(value uint32) { + volatile.StoreUint32(&o.Q5_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ5_WORD1() uint32 { + return volatile.LoadUint32(&o.Q5_WORD1.Reg) +} + +// UHCI.Q6_WORD0 +func (o *UHCI_Type) SetQ6_WORD0(value uint32) { + volatile.StoreUint32(&o.Q6_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ6_WORD0() uint32 { + return volatile.LoadUint32(&o.Q6_WORD0.Reg) +} + +// UHCI.Q6_WORD1 +func (o *UHCI_Type) SetQ6_WORD1(value uint32) { + volatile.StoreUint32(&o.Q6_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ6_WORD1() uint32 { + return volatile.LoadUint32(&o.Q6_WORD1.Reg) +} + +// UHCI.ESC_CONF0 +func (o *UHCI_Type) SetESC_CONF0_SEPER_CHAR(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_CHAR() uint32 { + return volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF1 +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0() uint32 { + return volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF2 +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1() uint32 { + return volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF3 +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2() uint32 { + return volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff0000) >> 16 +} + +// UHCI.PKT_THRES +func (o *UHCI_Type) SetPKT_THRES_PKT_THRS(value uint32) { + volatile.StoreUint32(&o.PKT_THRES.Reg, volatile.LoadUint32(&o.PKT_THRES.Reg)&^(0x1fff)|value) +} +func (o *UHCI_Type) GetPKT_THRES_PKT_THRS() uint32 { + return volatile.LoadUint32(&o.PKT_THRES.Reg) & 0x1fff +} + +// UHCI.DATE +func (o *UHCI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UHCI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Constants for AES: AES (Advanced Encryption Standard) Accelerator +const ( + // START + // Position of START field. + AES_START_START_Pos = 0x0 + // Bit mask of START field. + AES_START_START_Msk = 0x1 + // Bit START. + AES_START_START = 0x1 + + // IDLE + // Position of IDLE field. + AES_IDLE_IDLE_Pos = 0x0 + // Bit mask of IDLE field. + AES_IDLE_IDLE_Msk = 0x1 + // Bit IDLE. + AES_IDLE_IDLE = 0x1 + + // MODE + // Position of MODE field. + AES_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + AES_MODE_MODE_Msk = 0xff + + // KEY_0 + // Position of KEY field. + AES_KEY_KEY_Pos = 0x0 + // Bit mask of KEY field. + AES_KEY_KEY_Msk = 0xff + + // TEXT_0 + // Position of TEXT field. + AES_TEXT_TEXT_Pos = 0x0 + // Bit mask of TEXT field. + AES_TEXT_TEXT_Msk = 0xff + + // ENDIAN + // Position of ENDIAN field. + AES_ENDIAN_ENDIAN_Pos = 0x0 + // Bit mask of ENDIAN field. + AES_ENDIAN_ENDIAN_Msk = 0x3 +) + +// Constants for APB_CTRL: APB (Advanced Peripheral Bus) Controller +const ( + // SYSCLK_CONF + // Position of PRE_DIV_CNT field. + APB_CTRL_SYSCLK_CONF_PRE_DIV_CNT_Pos = 0x0 + // Bit mask of PRE_DIV_CNT field. + APB_CTRL_SYSCLK_CONF_PRE_DIV_CNT_Msk = 0x3ff + // Position of CLK_320M_EN field. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN_Pos = 0xa + // Bit mask of CLK_320M_EN field. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN_Msk = 0x400 + // Bit CLK_320M_EN. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN = 0x400 + // Position of CLK_EN field. + APB_CTRL_SYSCLK_CONF_CLK_EN_Pos = 0xb + // Bit mask of CLK_EN field. + APB_CTRL_SYSCLK_CONF_CLK_EN_Msk = 0x800 + // Bit CLK_EN. + APB_CTRL_SYSCLK_CONF_CLK_EN = 0x800 + // Position of RST_TICK_CNT field. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT_Pos = 0xc + // Bit mask of RST_TICK_CNT field. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT_Msk = 0x1000 + // Bit RST_TICK_CNT. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT = 0x1000 + // Position of QUICK_CLK_CHNG field. + APB_CTRL_SYSCLK_CONF_QUICK_CLK_CHNG_Pos = 0xd + // Bit mask of QUICK_CLK_CHNG field. + APB_CTRL_SYSCLK_CONF_QUICK_CLK_CHNG_Msk = 0x2000 + // Bit QUICK_CLK_CHNG. + APB_CTRL_SYSCLK_CONF_QUICK_CLK_CHNG = 0x2000 + + // XTAL_TICK_CONF + // Position of XTAL_TICK_NUM field. + APB_CTRL_XTAL_TICK_CONF_XTAL_TICK_NUM_Pos = 0x0 + // Bit mask of XTAL_TICK_NUM field. + APB_CTRL_XTAL_TICK_CONF_XTAL_TICK_NUM_Msk = 0xff + + // PLL_TICK_CONF + // Position of PLL_TICK_NUM field. + APB_CTRL_PLL_TICK_CONF_PLL_TICK_NUM_Pos = 0x0 + // Bit mask of PLL_TICK_NUM field. + APB_CTRL_PLL_TICK_CONF_PLL_TICK_NUM_Msk = 0xff + + // CK8M_TICK_CONF + // Position of CK8M_TICK_NUM field. + APB_CTRL_CK8M_TICK_CONF_CK8M_TICK_NUM_Pos = 0x0 + // Bit mask of CK8M_TICK_NUM field. + APB_CTRL_CK8M_TICK_CONF_CK8M_TICK_NUM_Msk = 0xff + + // APB_SARADC_CTRL + // Position of SARADC_START_FORCE field. + APB_CTRL_APB_SARADC_CTRL_SARADC_START_FORCE_Pos = 0x0 + // Bit mask of SARADC_START_FORCE field. + APB_CTRL_APB_SARADC_CTRL_SARADC_START_FORCE_Msk = 0x1 + // Bit SARADC_START_FORCE. + APB_CTRL_APB_SARADC_CTRL_SARADC_START_FORCE = 0x1 + // Position of SARADC_START field. + APB_CTRL_APB_SARADC_CTRL_SARADC_START_Pos = 0x1 + // Bit mask of SARADC_START field. + APB_CTRL_APB_SARADC_CTRL_SARADC_START_Msk = 0x2 + // Bit SARADC_START. + APB_CTRL_APB_SARADC_CTRL_SARADC_START = 0x2 + // Position of SARADC_SAR2_MUX field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR2_MUX_Pos = 0x2 + // Bit mask of SARADC_SAR2_MUX field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR2_MUX_Msk = 0x4 + // Bit SARADC_SAR2_MUX. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR2_MUX = 0x4 + // Position of SARADC_WORK_MODE field. + APB_CTRL_APB_SARADC_CTRL_SARADC_WORK_MODE_Pos = 0x3 + // Bit mask of SARADC_WORK_MODE field. + APB_CTRL_APB_SARADC_CTRL_SARADC_WORK_MODE_Msk = 0x18 + // Position of SARADC_SAR_SEL field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR_SEL_Pos = 0x5 + // Bit mask of SARADC_SAR_SEL field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR_SEL_Msk = 0x20 + // Bit SARADC_SAR_SEL. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR_SEL = 0x20 + // Position of SARADC_SAR_CLK_GATED field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Pos = 0x6 + // Bit mask of SARADC_SAR_CLK_GATED field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Msk = 0x40 + // Bit SARADC_SAR_CLK_GATED. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR_CLK_GATED = 0x40 + // Position of SARADC_SAR_CLK_DIV field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Pos = 0x7 + // Bit mask of SARADC_SAR_CLK_DIV field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Msk = 0x7f80 + // Position of SARADC_SAR1_PATT_LEN field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR1_PATT_LEN_Pos = 0xf + // Bit mask of SARADC_SAR1_PATT_LEN field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR1_PATT_LEN_Msk = 0x78000 + // Position of SARADC_SAR2_PATT_LEN field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR2_PATT_LEN_Pos = 0x13 + // Bit mask of SARADC_SAR2_PATT_LEN field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR2_PATT_LEN_Msk = 0x780000 + // Position of SARADC_SAR1_PATT_P_CLEAR field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR1_PATT_P_CLEAR_Pos = 0x17 + // Bit mask of SARADC_SAR1_PATT_P_CLEAR field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR1_PATT_P_CLEAR_Msk = 0x800000 + // Bit SARADC_SAR1_PATT_P_CLEAR. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR1_PATT_P_CLEAR = 0x800000 + // Position of SARADC_SAR2_PATT_P_CLEAR field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR2_PATT_P_CLEAR_Pos = 0x18 + // Bit mask of SARADC_SAR2_PATT_P_CLEAR field. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR2_PATT_P_CLEAR_Msk = 0x1000000 + // Bit SARADC_SAR2_PATT_P_CLEAR. + APB_CTRL_APB_SARADC_CTRL_SARADC_SAR2_PATT_P_CLEAR = 0x1000000 + // Position of SARADC_DATA_SAR_SEL field. + APB_CTRL_APB_SARADC_CTRL_SARADC_DATA_SAR_SEL_Pos = 0x19 + // Bit mask of SARADC_DATA_SAR_SEL field. + APB_CTRL_APB_SARADC_CTRL_SARADC_DATA_SAR_SEL_Msk = 0x2000000 + // Bit SARADC_DATA_SAR_SEL. + APB_CTRL_APB_SARADC_CTRL_SARADC_DATA_SAR_SEL = 0x2000000 + // Position of SARADC_DATA_TO_I2S field. + APB_CTRL_APB_SARADC_CTRL_SARADC_DATA_TO_I2S_Pos = 0x1a + // Bit mask of SARADC_DATA_TO_I2S field. + APB_CTRL_APB_SARADC_CTRL_SARADC_DATA_TO_I2S_Msk = 0x4000000 + // Bit SARADC_DATA_TO_I2S. + APB_CTRL_APB_SARADC_CTRL_SARADC_DATA_TO_I2S = 0x4000000 + + // APB_SARADC_CTRL2 + // Position of SARADC_MEAS_NUM_LIMIT field. + APB_CTRL_APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Pos = 0x0 + // Bit mask of SARADC_MEAS_NUM_LIMIT field. + APB_CTRL_APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Msk = 0x1 + // Bit SARADC_MEAS_NUM_LIMIT. + APB_CTRL_APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT = 0x1 + // Position of SARADC_MAX_MEAS_NUM field. + APB_CTRL_APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Pos = 0x1 + // Bit mask of SARADC_MAX_MEAS_NUM field. + APB_CTRL_APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Msk = 0x1fe + // Position of SARADC_SAR1_INV field. + APB_CTRL_APB_SARADC_CTRL2_SARADC_SAR1_INV_Pos = 0x9 + // Bit mask of SARADC_SAR1_INV field. + APB_CTRL_APB_SARADC_CTRL2_SARADC_SAR1_INV_Msk = 0x200 + // Bit SARADC_SAR1_INV. + APB_CTRL_APB_SARADC_CTRL2_SARADC_SAR1_INV = 0x200 + // Position of SARADC_SAR2_INV field. + APB_CTRL_APB_SARADC_CTRL2_SARADC_SAR2_INV_Pos = 0xa + // Bit mask of SARADC_SAR2_INV field. + APB_CTRL_APB_SARADC_CTRL2_SARADC_SAR2_INV_Msk = 0x400 + // Bit SARADC_SAR2_INV. + APB_CTRL_APB_SARADC_CTRL2_SARADC_SAR2_INV = 0x400 + + // APB_SARADC_FSM + // Position of SARADC_RSTB_WAIT field. + APB_CTRL_APB_SARADC_FSM_SARADC_RSTB_WAIT_Pos = 0x0 + // Bit mask of SARADC_RSTB_WAIT field. + APB_CTRL_APB_SARADC_FSM_SARADC_RSTB_WAIT_Msk = 0xff + // Position of SARADC_STANDBY_WAIT field. + APB_CTRL_APB_SARADC_FSM_SARADC_STANDBY_WAIT_Pos = 0x8 + // Bit mask of SARADC_STANDBY_WAIT field. + APB_CTRL_APB_SARADC_FSM_SARADC_STANDBY_WAIT_Msk = 0xff00 + // Position of SARADC_START_WAIT field. + APB_CTRL_APB_SARADC_FSM_SARADC_START_WAIT_Pos = 0x10 + // Bit mask of SARADC_START_WAIT field. + APB_CTRL_APB_SARADC_FSM_SARADC_START_WAIT_Msk = 0xff0000 + // Position of SARADC_SAMPLE_CYCLE field. + APB_CTRL_APB_SARADC_FSM_SARADC_SAMPLE_CYCLE_Pos = 0x18 + // Bit mask of SARADC_SAMPLE_CYCLE field. + APB_CTRL_APB_SARADC_FSM_SARADC_SAMPLE_CYCLE_Msk = 0xff000000 + + // APB_SARADC_SAR1_PATT_TAB1 + // Position of SARADC_SAR1_PATT_TAB1 field. + APB_CTRL_APB_SARADC_SAR1_PATT_TAB_SARADC_SAR1_PATT_TAB1_Pos = 0x0 + // Bit mask of SARADC_SAR1_PATT_TAB1 field. + APB_CTRL_APB_SARADC_SAR1_PATT_TAB_SARADC_SAR1_PATT_TAB1_Msk = 0xffffffff + + // APB_SARADC_SAR2_PATT_TAB1 + // Position of SARADC_SAR2_PATT_TAB1 field. + APB_CTRL_APB_SARADC_SAR2_PATT_TAB_SARADC_SAR2_PATT_TAB1_Pos = 0x0 + // Bit mask of SARADC_SAR2_PATT_TAB1 field. + APB_CTRL_APB_SARADC_SAR2_PATT_TAB_SARADC_SAR2_PATT_TAB1_Msk = 0xffffffff + + // APLL_TICK_CONF + // Position of APLL_TICK_NUM field. + APB_CTRL_APLL_TICK_CONF_APLL_TICK_NUM_Pos = 0x0 + // Bit mask of APLL_TICK_NUM field. + APB_CTRL_APLL_TICK_CONF_APLL_TICK_NUM_Msk = 0xff + + // DATE + // Position of DATE field. + APB_CTRL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + APB_CTRL_DATE_DATE_Msk = 0xffffffff +) + +// Constants for BB: BB Peripheral +const ( + // BBPD_CTRL: Baseband control register + // Position of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Pos = 0x0 + // Bit mask of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Msk = 0x1 + // Bit DC_EST_FORCE_PD. + BB_BBPD_CTRL_DC_EST_FORCE_PD = 0x1 + // Position of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Pos = 0x1 + // Bit mask of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Msk = 0x2 + // Bit DC_EST_FORCE_PU. + BB_BBPD_CTRL_DC_EST_FORCE_PU = 0x2 + // Position of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Pos = 0x2 + // Bit mask of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Msk = 0x4 + // Bit FFT_FORCE_PD. + BB_BBPD_CTRL_FFT_FORCE_PD = 0x4 + // Position of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Pos = 0x3 + // Bit mask of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Msk = 0x8 + // Bit FFT_FORCE_PU. + BB_BBPD_CTRL_FFT_FORCE_PU = 0x8 +) + +// Constants for DPORT: DPORT Peripheral +const ( + // PRO_BOOT_REMAP_CTRL + // Position of PRO_BOOT_REMAP field. + DPORT_PRO_BOOT_REMAP_CTRL_PRO_BOOT_REMAP_Pos = 0x0 + // Bit mask of PRO_BOOT_REMAP field. + DPORT_PRO_BOOT_REMAP_CTRL_PRO_BOOT_REMAP_Msk = 0x1 + // Bit PRO_BOOT_REMAP. + DPORT_PRO_BOOT_REMAP_CTRL_PRO_BOOT_REMAP = 0x1 + + // APP_BOOT_REMAP_CTRL + // Position of APP_BOOT_REMAP field. + DPORT_APP_BOOT_REMAP_CTRL_APP_BOOT_REMAP_Pos = 0x0 + // Bit mask of APP_BOOT_REMAP field. + DPORT_APP_BOOT_REMAP_CTRL_APP_BOOT_REMAP_Msk = 0x1 + // Bit APP_BOOT_REMAP. + DPORT_APP_BOOT_REMAP_CTRL_APP_BOOT_REMAP = 0x1 + + // ACCESS_CHECK + // Position of PRO field. + DPORT_ACCESS_CHECK_PRO_Pos = 0x0 + // Bit mask of PRO field. + DPORT_ACCESS_CHECK_PRO_Msk = 0x1 + // Bit PRO. + DPORT_ACCESS_CHECK_PRO = 0x1 + // Position of APP field. + DPORT_ACCESS_CHECK_APP_Pos = 0x8 + // Bit mask of APP field. + DPORT_ACCESS_CHECK_APP_Msk = 0x100 + // Bit APP. + DPORT_ACCESS_CHECK_APP = 0x100 + + // PRO_DPORT_APB_MASK0 + // Position of PRODPORT_APB_MASK0 field. + DPORT_PRO_DPORT_APB_MASK0_PRODPORT_APB_MASK0_Pos = 0x0 + // Bit mask of PRODPORT_APB_MASK0 field. + DPORT_PRO_DPORT_APB_MASK0_PRODPORT_APB_MASK0_Msk = 0xffffffff + + // PRO_DPORT_APB_MASK1 + // Position of PRODPORT_APB_MASK1 field. + DPORT_PRO_DPORT_APB_MASK1_PRODPORT_APB_MASK1_Pos = 0x0 + // Bit mask of PRODPORT_APB_MASK1 field. + DPORT_PRO_DPORT_APB_MASK1_PRODPORT_APB_MASK1_Msk = 0xffffffff + + // APP_DPORT_APB_MASK0 + // Position of APPDPORT_APB_MASK0 field. + DPORT_APP_DPORT_APB_MASK0_APPDPORT_APB_MASK0_Pos = 0x0 + // Bit mask of APPDPORT_APB_MASK0 field. + DPORT_APP_DPORT_APB_MASK0_APPDPORT_APB_MASK0_Msk = 0xffffffff + + // APP_DPORT_APB_MASK1 + // Position of APPDPORT_APB_MASK1 field. + DPORT_APP_DPORT_APB_MASK1_APPDPORT_APB_MASK1_Pos = 0x0 + // Bit mask of APPDPORT_APB_MASK1 field. + DPORT_APP_DPORT_APB_MASK1_APPDPORT_APB_MASK1_Msk = 0xffffffff + + // PERI_CLK_EN + // Position of PERI_CLK_EN field. + DPORT_PERI_CLK_EN_PERI_CLK_EN_Pos = 0x0 + // Bit mask of PERI_CLK_EN field. + DPORT_PERI_CLK_EN_PERI_CLK_EN_Msk = 0xffffffff + + // PERI_RST_EN + // Position of PERI_RST_EN field. + DPORT_PERI_RST_EN_PERI_RST_EN_Pos = 0x0 + // Bit mask of PERI_RST_EN field. + DPORT_PERI_RST_EN_PERI_RST_EN_Msk = 0xffffffff + + // WIFI_BB_CFG + // Position of WIFI_BB_CFG field. + DPORT_WIFI_BB_CFG_WIFI_BB_CFG_Pos = 0x0 + // Bit mask of WIFI_BB_CFG field. + DPORT_WIFI_BB_CFG_WIFI_BB_CFG_Msk = 0xffffffff + + // WIFI_BB_CFG_2 + // Position of WIFI_BB_CFG_2 field. + DPORT_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Pos = 0x0 + // Bit mask of WIFI_BB_CFG_2 field. + DPORT_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Msk = 0xffffffff + + // APPCPU_CTRL_A + // Position of APPCPU_RESETTING field. + DPORT_APPCPU_CTRL_A_APPCPU_RESETTING_Pos = 0x0 + // Bit mask of APPCPU_RESETTING field. + DPORT_APPCPU_CTRL_A_APPCPU_RESETTING_Msk = 0x1 + // Bit APPCPU_RESETTING. + DPORT_APPCPU_CTRL_A_APPCPU_RESETTING = 0x1 + + // APPCPU_CTRL_B + // Position of APPCPU_CLKGATE_EN field. + DPORT_APPCPU_CTRL_B_APPCPU_CLKGATE_EN_Pos = 0x0 + // Bit mask of APPCPU_CLKGATE_EN field. + DPORT_APPCPU_CTRL_B_APPCPU_CLKGATE_EN_Msk = 0x1 + // Bit APPCPU_CLKGATE_EN. + DPORT_APPCPU_CTRL_B_APPCPU_CLKGATE_EN = 0x1 + + // APPCPU_CTRL_C + // Position of APPCPU_RUNSTALL field. + DPORT_APPCPU_CTRL_C_APPCPU_RUNSTALL_Pos = 0x0 + // Bit mask of APPCPU_RUNSTALL field. + DPORT_APPCPU_CTRL_C_APPCPU_RUNSTALL_Msk = 0x1 + // Bit APPCPU_RUNSTALL. + DPORT_APPCPU_CTRL_C_APPCPU_RUNSTALL = 0x1 + + // APPCPU_CTRL_D + // Position of APPCPU_BOOT_ADDR field. + DPORT_APPCPU_CTRL_D_APPCPU_BOOT_ADDR_Pos = 0x0 + // Bit mask of APPCPU_BOOT_ADDR field. + DPORT_APPCPU_CTRL_D_APPCPU_BOOT_ADDR_Msk = 0xffffffff + + // CPU_PER_CONF + // Position of CPUPERIOD_SEL field. + DPORT_CPU_PER_CONF_CPUPERIOD_SEL_Pos = 0x0 + // Bit mask of CPUPERIOD_SEL field. + DPORT_CPU_PER_CONF_CPUPERIOD_SEL_Msk = 0x3 + // Position of LOWSPEED_CLK_SEL field. + DPORT_CPU_PER_CONF_LOWSPEED_CLK_SEL_Pos = 0x2 + // Bit mask of LOWSPEED_CLK_SEL field. + DPORT_CPU_PER_CONF_LOWSPEED_CLK_SEL_Msk = 0x4 + // Bit LOWSPEED_CLK_SEL. + DPORT_CPU_PER_CONF_LOWSPEED_CLK_SEL = 0x4 + // Position of FAST_CLK_RTC_SEL field. + DPORT_CPU_PER_CONF_FAST_CLK_RTC_SEL_Pos = 0x3 + // Bit mask of FAST_CLK_RTC_SEL field. + DPORT_CPU_PER_CONF_FAST_CLK_RTC_SEL_Msk = 0x8 + // Bit FAST_CLK_RTC_SEL. + DPORT_CPU_PER_CONF_FAST_CLK_RTC_SEL = 0x8 + + // PRO_CACHE_CTRL + // Position of PRO_CACHE_MODE field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_MODE_Pos = 0x2 + // Bit mask of PRO_CACHE_MODE field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_MODE_Msk = 0x4 + // Bit PRO_CACHE_MODE. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_MODE = 0x4 + // Position of PRO_CACHE_ENABLE field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_ENABLE_Pos = 0x3 + // Bit mask of PRO_CACHE_ENABLE field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_ENABLE_Msk = 0x8 + // Bit PRO_CACHE_ENABLE. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_ENABLE = 0x8 + // Position of PRO_CACHE_FLUSH_ENA field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_FLUSH_ENA_Pos = 0x4 + // Bit mask of PRO_CACHE_FLUSH_ENA field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_FLUSH_ENA_Msk = 0x10 + // Bit PRO_CACHE_FLUSH_ENA. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_FLUSH_ENA = 0x10 + // Position of PRO_CACHE_FLUSH_DONE field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_FLUSH_DONE_Pos = 0x5 + // Bit mask of PRO_CACHE_FLUSH_DONE field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_FLUSH_DONE_Msk = 0x20 + // Bit PRO_CACHE_FLUSH_DONE. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_FLUSH_DONE = 0x20 + // Position of PRO_CACHE_LOCK_0_EN field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_0_EN_Pos = 0x6 + // Bit mask of PRO_CACHE_LOCK_0_EN field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_0_EN_Msk = 0x40 + // Bit PRO_CACHE_LOCK_0_EN. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_0_EN = 0x40 + // Position of PRO_CACHE_LOCK_1_EN field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_1_EN_Pos = 0x7 + // Bit mask of PRO_CACHE_LOCK_1_EN field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_1_EN_Msk = 0x80 + // Bit PRO_CACHE_LOCK_1_EN. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_1_EN = 0x80 + // Position of PRO_CACHE_LOCK_2_EN field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_2_EN_Pos = 0x8 + // Bit mask of PRO_CACHE_LOCK_2_EN field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_2_EN_Msk = 0x100 + // Bit PRO_CACHE_LOCK_2_EN. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_2_EN = 0x100 + // Position of PRO_CACHE_LOCK_3_EN field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_3_EN_Pos = 0x9 + // Bit mask of PRO_CACHE_LOCK_3_EN field. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_3_EN_Msk = 0x200 + // Bit PRO_CACHE_LOCK_3_EN. + DPORT_PRO_CACHE_CTRL_PRO_CACHE_LOCK_3_EN = 0x200 + // Position of PRO_SINGLE_IRAM_ENA field. + DPORT_PRO_CACHE_CTRL_PRO_SINGLE_IRAM_ENA_Pos = 0xa + // Bit mask of PRO_SINGLE_IRAM_ENA field. + DPORT_PRO_CACHE_CTRL_PRO_SINGLE_IRAM_ENA_Msk = 0x400 + // Bit PRO_SINGLE_IRAM_ENA. + DPORT_PRO_CACHE_CTRL_PRO_SINGLE_IRAM_ENA = 0x400 + // Position of PRO_DRAM_SPLIT field. + DPORT_PRO_CACHE_CTRL_PRO_DRAM_SPLIT_Pos = 0xb + // Bit mask of PRO_DRAM_SPLIT field. + DPORT_PRO_CACHE_CTRL_PRO_DRAM_SPLIT_Msk = 0x800 + // Bit PRO_DRAM_SPLIT. + DPORT_PRO_CACHE_CTRL_PRO_DRAM_SPLIT = 0x800 + // Position of PRO_AHB_SPI_REQ field. + DPORT_PRO_CACHE_CTRL_PRO_AHB_SPI_REQ_Pos = 0xc + // Bit mask of PRO_AHB_SPI_REQ field. + DPORT_PRO_CACHE_CTRL_PRO_AHB_SPI_REQ_Msk = 0x1000 + // Bit PRO_AHB_SPI_REQ. + DPORT_PRO_CACHE_CTRL_PRO_AHB_SPI_REQ = 0x1000 + // Position of PRO_SLAVE_REQ field. + DPORT_PRO_CACHE_CTRL_PRO_SLAVE_REQ_Pos = 0xd + // Bit mask of PRO_SLAVE_REQ field. + DPORT_PRO_CACHE_CTRL_PRO_SLAVE_REQ_Msk = 0x2000 + // Bit PRO_SLAVE_REQ. + DPORT_PRO_CACHE_CTRL_PRO_SLAVE_REQ = 0x2000 + // Position of AHB_SPI_REQ field. + DPORT_PRO_CACHE_CTRL_AHB_SPI_REQ_Pos = 0xe + // Bit mask of AHB_SPI_REQ field. + DPORT_PRO_CACHE_CTRL_AHB_SPI_REQ_Msk = 0x4000 + // Bit AHB_SPI_REQ. + DPORT_PRO_CACHE_CTRL_AHB_SPI_REQ = 0x4000 + // Position of SLAVE_REQ field. + DPORT_PRO_CACHE_CTRL_SLAVE_REQ_Pos = 0xf + // Bit mask of SLAVE_REQ field. + DPORT_PRO_CACHE_CTRL_SLAVE_REQ_Msk = 0x8000 + // Bit SLAVE_REQ. + DPORT_PRO_CACHE_CTRL_SLAVE_REQ = 0x8000 + // Position of PRO_DRAM_HL field. + DPORT_PRO_CACHE_CTRL_PRO_DRAM_HL_Pos = 0x10 + // Bit mask of PRO_DRAM_HL field. + DPORT_PRO_CACHE_CTRL_PRO_DRAM_HL_Msk = 0x10000 + // Bit PRO_DRAM_HL. + DPORT_PRO_CACHE_CTRL_PRO_DRAM_HL = 0x10000 + + // PRO_CACHE_CTRL1 + // Position of PRO_CACHE_MASK_IRAM0 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM0_Pos = 0x0 + // Bit mask of PRO_CACHE_MASK_IRAM0 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM0_Msk = 0x1 + // Bit PRO_CACHE_MASK_IRAM0. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM0 = 0x1 + // Position of PRO_CACHE_MASK_IRAM1 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM1_Pos = 0x1 + // Bit mask of PRO_CACHE_MASK_IRAM1 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM1_Msk = 0x2 + // Bit PRO_CACHE_MASK_IRAM1. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_IRAM1 = 0x2 + // Position of PRO_CACHE_MASK_IROM0 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_IROM0_Pos = 0x2 + // Bit mask of PRO_CACHE_MASK_IROM0 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_IROM0_Msk = 0x4 + // Bit PRO_CACHE_MASK_IROM0. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_IROM0 = 0x4 + // Position of PRO_CACHE_MASK_DRAM1 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_DRAM1_Pos = 0x3 + // Bit mask of PRO_CACHE_MASK_DRAM1 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_DRAM1_Msk = 0x8 + // Bit PRO_CACHE_MASK_DRAM1. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_DRAM1 = 0x8 + // Position of PRO_CACHE_MASK_DROM0 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_DROM0_Pos = 0x4 + // Bit mask of PRO_CACHE_MASK_DROM0 field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_DROM0_Msk = 0x10 + // Bit PRO_CACHE_MASK_DROM0. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_DROM0 = 0x10 + // Position of PRO_CACHE_MASK_OPSDRAM field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_OPSDRAM_Pos = 0x5 + // Bit mask of PRO_CACHE_MASK_OPSDRAM field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_OPSDRAM_Msk = 0x20 + // Bit PRO_CACHE_MASK_OPSDRAM. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MASK_OPSDRAM = 0x20 + // Position of PRO_CMMU_SRAM_PAGE_MODE field. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_SRAM_PAGE_MODE_Pos = 0x6 + // Bit mask of PRO_CMMU_SRAM_PAGE_MODE field. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_SRAM_PAGE_MODE_Msk = 0x1c0 + // Position of PRO_CMMU_FLASH_PAGE_MODE field. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_FLASH_PAGE_MODE_Pos = 0x9 + // Bit mask of PRO_CMMU_FLASH_PAGE_MODE field. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_FLASH_PAGE_MODE_Msk = 0x600 + // Position of PRO_CMMU_FORCE_ON field. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_FORCE_ON_Pos = 0xb + // Bit mask of PRO_CMMU_FORCE_ON field. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_FORCE_ON_Msk = 0x800 + // Bit PRO_CMMU_FORCE_ON. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_FORCE_ON = 0x800 + // Position of PRO_CMMU_PD field. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_PD_Pos = 0xc + // Bit mask of PRO_CMMU_PD field. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_PD_Msk = 0x1000 + // Bit PRO_CMMU_PD. + DPORT_PRO_CACHE_CTRL1_PRO_CMMU_PD = 0x1000 + // Position of PRO_CACHE_MMU_IA_CLR field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MMU_IA_CLR_Pos = 0xd + // Bit mask of PRO_CACHE_MMU_IA_CLR field. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MMU_IA_CLR_Msk = 0x2000 + // Bit PRO_CACHE_MMU_IA_CLR. + DPORT_PRO_CACHE_CTRL1_PRO_CACHE_MMU_IA_CLR = 0x2000 + + // PRO_CACHE_LOCK_0_ADDR + // Position of PRE field. + DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_Pos = 0x0 + // Bit mask of PRE field. + DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_Msk = 0x3fff + // Position of MIN field. + DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_Pos = 0xe + // Bit mask of MIN field. + DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_Msk = 0x3c000 + // Position of MAX field. + DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_Pos = 0x12 + // Bit mask of MAX field. + DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_Msk = 0x3c0000 + + // PRO_CACHE_LOCK_1_ADDR + // Position of PRE field. + DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_Pos = 0x0 + // Bit mask of PRE field. + DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_Msk = 0x3fff + // Position of MIN field. + DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_Pos = 0xe + // Bit mask of MIN field. + DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_Msk = 0x3c000 + // Position of MAX field. + DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_Pos = 0x12 + // Bit mask of MAX field. + DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_Msk = 0x3c0000 + + // PRO_CACHE_LOCK_2_ADDR + // Position of PRE field. + DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_Pos = 0x0 + // Bit mask of PRE field. + DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_Msk = 0x3fff + // Position of MIN field. + DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_Pos = 0xe + // Bit mask of MIN field. + DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_Msk = 0x3c000 + // Position of MAX field. + DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_Pos = 0x12 + // Bit mask of MAX field. + DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_Msk = 0x3c0000 + + // PRO_CACHE_LOCK_3_ADDR + // Position of PRE field. + DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_Pos = 0x0 + // Bit mask of PRE field. + DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_Msk = 0x3fff + // Position of MIN field. + DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_Pos = 0xe + // Bit mask of MIN field. + DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_Msk = 0x3c000 + // Position of MAX field. + DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_Pos = 0x12 + // Bit mask of MAX field. + DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_Msk = 0x3c0000 + + // APP_CACHE_CTRL + // Position of APP_CACHE_MODE field. + DPORT_APP_CACHE_CTRL_APP_CACHE_MODE_Pos = 0x2 + // Bit mask of APP_CACHE_MODE field. + DPORT_APP_CACHE_CTRL_APP_CACHE_MODE_Msk = 0x4 + // Bit APP_CACHE_MODE. + DPORT_APP_CACHE_CTRL_APP_CACHE_MODE = 0x4 + // Position of APP_CACHE_ENABLE field. + DPORT_APP_CACHE_CTRL_APP_CACHE_ENABLE_Pos = 0x3 + // Bit mask of APP_CACHE_ENABLE field. + DPORT_APP_CACHE_CTRL_APP_CACHE_ENABLE_Msk = 0x8 + // Bit APP_CACHE_ENABLE. + DPORT_APP_CACHE_CTRL_APP_CACHE_ENABLE = 0x8 + // Position of APP_CACHE_FLUSH_ENA field. + DPORT_APP_CACHE_CTRL_APP_CACHE_FLUSH_ENA_Pos = 0x4 + // Bit mask of APP_CACHE_FLUSH_ENA field. + DPORT_APP_CACHE_CTRL_APP_CACHE_FLUSH_ENA_Msk = 0x10 + // Bit APP_CACHE_FLUSH_ENA. + DPORT_APP_CACHE_CTRL_APP_CACHE_FLUSH_ENA = 0x10 + // Position of APP_CACHE_FLUSH_DONE field. + DPORT_APP_CACHE_CTRL_APP_CACHE_FLUSH_DONE_Pos = 0x5 + // Bit mask of APP_CACHE_FLUSH_DONE field. + DPORT_APP_CACHE_CTRL_APP_CACHE_FLUSH_DONE_Msk = 0x20 + // Bit APP_CACHE_FLUSH_DONE. + DPORT_APP_CACHE_CTRL_APP_CACHE_FLUSH_DONE = 0x20 + // Position of APP_CACHE_LOCK_0_EN field. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_0_EN_Pos = 0x6 + // Bit mask of APP_CACHE_LOCK_0_EN field. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_0_EN_Msk = 0x40 + // Bit APP_CACHE_LOCK_0_EN. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_0_EN = 0x40 + // Position of APP_CACHE_LOCK_1_EN field. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_1_EN_Pos = 0x7 + // Bit mask of APP_CACHE_LOCK_1_EN field. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_1_EN_Msk = 0x80 + // Bit APP_CACHE_LOCK_1_EN. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_1_EN = 0x80 + // Position of APP_CACHE_LOCK_2_EN field. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_2_EN_Pos = 0x8 + // Bit mask of APP_CACHE_LOCK_2_EN field. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_2_EN_Msk = 0x100 + // Bit APP_CACHE_LOCK_2_EN. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_2_EN = 0x100 + // Position of APP_CACHE_LOCK_3_EN field. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_3_EN_Pos = 0x9 + // Bit mask of APP_CACHE_LOCK_3_EN field. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_3_EN_Msk = 0x200 + // Bit APP_CACHE_LOCK_3_EN. + DPORT_APP_CACHE_CTRL_APP_CACHE_LOCK_3_EN = 0x200 + // Position of APP_SINGLE_IRAM_ENA field. + DPORT_APP_CACHE_CTRL_APP_SINGLE_IRAM_ENA_Pos = 0xa + // Bit mask of APP_SINGLE_IRAM_ENA field. + DPORT_APP_CACHE_CTRL_APP_SINGLE_IRAM_ENA_Msk = 0x400 + // Bit APP_SINGLE_IRAM_ENA. + DPORT_APP_CACHE_CTRL_APP_SINGLE_IRAM_ENA = 0x400 + // Position of APP_DRAM_SPLIT field. + DPORT_APP_CACHE_CTRL_APP_DRAM_SPLIT_Pos = 0xb + // Bit mask of APP_DRAM_SPLIT field. + DPORT_APP_CACHE_CTRL_APP_DRAM_SPLIT_Msk = 0x800 + // Bit APP_DRAM_SPLIT. + DPORT_APP_CACHE_CTRL_APP_DRAM_SPLIT = 0x800 + // Position of APP_AHB_SPI_REQ field. + DPORT_APP_CACHE_CTRL_APP_AHB_SPI_REQ_Pos = 0xc + // Bit mask of APP_AHB_SPI_REQ field. + DPORT_APP_CACHE_CTRL_APP_AHB_SPI_REQ_Msk = 0x1000 + // Bit APP_AHB_SPI_REQ. + DPORT_APP_CACHE_CTRL_APP_AHB_SPI_REQ = 0x1000 + // Position of APP_SLAVE_REQ field. + DPORT_APP_CACHE_CTRL_APP_SLAVE_REQ_Pos = 0xd + // Bit mask of APP_SLAVE_REQ field. + DPORT_APP_CACHE_CTRL_APP_SLAVE_REQ_Msk = 0x2000 + // Bit APP_SLAVE_REQ. + DPORT_APP_CACHE_CTRL_APP_SLAVE_REQ = 0x2000 + // Position of APP_DRAM_HL field. + DPORT_APP_CACHE_CTRL_APP_DRAM_HL_Pos = 0xe + // Bit mask of APP_DRAM_HL field. + DPORT_APP_CACHE_CTRL_APP_DRAM_HL_Msk = 0x4000 + // Bit APP_DRAM_HL. + DPORT_APP_CACHE_CTRL_APP_DRAM_HL = 0x4000 + + // APP_CACHE_CTRL1 + // Position of APP_CACHE_MASK_IRAM0 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_IRAM0_Pos = 0x0 + // Bit mask of APP_CACHE_MASK_IRAM0 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_IRAM0_Msk = 0x1 + // Bit APP_CACHE_MASK_IRAM0. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_IRAM0 = 0x1 + // Position of APP_CACHE_MASK_IRAM1 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_IRAM1_Pos = 0x1 + // Bit mask of APP_CACHE_MASK_IRAM1 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_IRAM1_Msk = 0x2 + // Bit APP_CACHE_MASK_IRAM1. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_IRAM1 = 0x2 + // Position of APP_CACHE_MASK_IROM0 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_IROM0_Pos = 0x2 + // Bit mask of APP_CACHE_MASK_IROM0 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_IROM0_Msk = 0x4 + // Bit APP_CACHE_MASK_IROM0. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_IROM0 = 0x4 + // Position of APP_CACHE_MASK_DRAM1 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_DRAM1_Pos = 0x3 + // Bit mask of APP_CACHE_MASK_DRAM1 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_DRAM1_Msk = 0x8 + // Bit APP_CACHE_MASK_DRAM1. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_DRAM1 = 0x8 + // Position of APP_CACHE_MASK_DROM0 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_DROM0_Pos = 0x4 + // Bit mask of APP_CACHE_MASK_DROM0 field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_DROM0_Msk = 0x10 + // Bit APP_CACHE_MASK_DROM0. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_DROM0 = 0x10 + // Position of APP_CACHE_MASK_OPSDRAM field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_OPSDRAM_Pos = 0x5 + // Bit mask of APP_CACHE_MASK_OPSDRAM field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_OPSDRAM_Msk = 0x20 + // Bit APP_CACHE_MASK_OPSDRAM. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MASK_OPSDRAM = 0x20 + // Position of APP_CMMU_SRAM_PAGE_MODE field. + DPORT_APP_CACHE_CTRL1_APP_CMMU_SRAM_PAGE_MODE_Pos = 0x6 + // Bit mask of APP_CMMU_SRAM_PAGE_MODE field. + DPORT_APP_CACHE_CTRL1_APP_CMMU_SRAM_PAGE_MODE_Msk = 0x1c0 + // Position of APP_CMMU_FLASH_PAGE_MODE field. + DPORT_APP_CACHE_CTRL1_APP_CMMU_FLASH_PAGE_MODE_Pos = 0x9 + // Bit mask of APP_CMMU_FLASH_PAGE_MODE field. + DPORT_APP_CACHE_CTRL1_APP_CMMU_FLASH_PAGE_MODE_Msk = 0x600 + // Position of APP_CMMU_FORCE_ON field. + DPORT_APP_CACHE_CTRL1_APP_CMMU_FORCE_ON_Pos = 0xb + // Bit mask of APP_CMMU_FORCE_ON field. + DPORT_APP_CACHE_CTRL1_APP_CMMU_FORCE_ON_Msk = 0x800 + // Bit APP_CMMU_FORCE_ON. + DPORT_APP_CACHE_CTRL1_APP_CMMU_FORCE_ON = 0x800 + // Position of APP_CMMU_PD field. + DPORT_APP_CACHE_CTRL1_APP_CMMU_PD_Pos = 0xc + // Bit mask of APP_CMMU_PD field. + DPORT_APP_CACHE_CTRL1_APP_CMMU_PD_Msk = 0x1000 + // Bit APP_CMMU_PD. + DPORT_APP_CACHE_CTRL1_APP_CMMU_PD = 0x1000 + // Position of APP_CACHE_MMU_IA_CLR field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MMU_IA_CLR_Pos = 0xd + // Bit mask of APP_CACHE_MMU_IA_CLR field. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MMU_IA_CLR_Msk = 0x2000 + // Bit APP_CACHE_MMU_IA_CLR. + DPORT_APP_CACHE_CTRL1_APP_CACHE_MMU_IA_CLR = 0x2000 + + // APP_CACHE_LOCK_0_ADDR + // Position of PRE field. + DPORT_APP_CACHE_LOCK_0_ADDR_PRE_Pos = 0x0 + // Bit mask of PRE field. + DPORT_APP_CACHE_LOCK_0_ADDR_PRE_Msk = 0x3fff + // Position of MIN field. + DPORT_APP_CACHE_LOCK_0_ADDR_MIN_Pos = 0xe + // Bit mask of MIN field. + DPORT_APP_CACHE_LOCK_0_ADDR_MIN_Msk = 0x3c000 + // Position of MAX field. + DPORT_APP_CACHE_LOCK_0_ADDR_MAX_Pos = 0x12 + // Bit mask of MAX field. + DPORT_APP_CACHE_LOCK_0_ADDR_MAX_Msk = 0x3c0000 + + // APP_CACHE_LOCK_1_ADDR + // Position of PRE field. + DPORT_APP_CACHE_LOCK_1_ADDR_PRE_Pos = 0x0 + // Bit mask of PRE field. + DPORT_APP_CACHE_LOCK_1_ADDR_PRE_Msk = 0x3fff + // Position of MIN field. + DPORT_APP_CACHE_LOCK_1_ADDR_MIN_Pos = 0xe + // Bit mask of MIN field. + DPORT_APP_CACHE_LOCK_1_ADDR_MIN_Msk = 0x3c000 + // Position of MAX field. + DPORT_APP_CACHE_LOCK_1_ADDR_MAX_Pos = 0x12 + // Bit mask of MAX field. + DPORT_APP_CACHE_LOCK_1_ADDR_MAX_Msk = 0x3c0000 + + // APP_CACHE_LOCK_2_ADDR + // Position of PRE field. + DPORT_APP_CACHE_LOCK_2_ADDR_PRE_Pos = 0x0 + // Bit mask of PRE field. + DPORT_APP_CACHE_LOCK_2_ADDR_PRE_Msk = 0x3fff + // Position of MIN field. + DPORT_APP_CACHE_LOCK_2_ADDR_MIN_Pos = 0xe + // Bit mask of MIN field. + DPORT_APP_CACHE_LOCK_2_ADDR_MIN_Msk = 0x3c000 + // Position of MAX field. + DPORT_APP_CACHE_LOCK_2_ADDR_MAX_Pos = 0x12 + // Bit mask of MAX field. + DPORT_APP_CACHE_LOCK_2_ADDR_MAX_Msk = 0x3c0000 + + // APP_CACHE_LOCK_3_ADDR + // Position of PRE field. + DPORT_APP_CACHE_LOCK_3_ADDR_PRE_Pos = 0x0 + // Bit mask of PRE field. + DPORT_APP_CACHE_LOCK_3_ADDR_PRE_Msk = 0x3fff + // Position of MIN field. + DPORT_APP_CACHE_LOCK_3_ADDR_MIN_Pos = 0xe + // Bit mask of MIN field. + DPORT_APP_CACHE_LOCK_3_ADDR_MIN_Msk = 0x3c000 + // Position of MAX field. + DPORT_APP_CACHE_LOCK_3_ADDR_MAX_Pos = 0x12 + // Bit mask of MAX field. + DPORT_APP_CACHE_LOCK_3_ADDR_MAX_Msk = 0x3c0000 + + // TRACEMEM_MUX_MODE + // Position of TRACEMEM_MUX_MODE field. + DPORT_TRACEMEM_MUX_MODE_TRACEMEM_MUX_MODE_Pos = 0x0 + // Bit mask of TRACEMEM_MUX_MODE field. + DPORT_TRACEMEM_MUX_MODE_TRACEMEM_MUX_MODE_Msk = 0x3 + + // PRO_TRACEMEM_ENA + // Position of PRO_TRACEMEM_ENA field. + DPORT_PRO_TRACEMEM_ENA_PRO_TRACEMEM_ENA_Pos = 0x0 + // Bit mask of PRO_TRACEMEM_ENA field. + DPORT_PRO_TRACEMEM_ENA_PRO_TRACEMEM_ENA_Msk = 0x1 + // Bit PRO_TRACEMEM_ENA. + DPORT_PRO_TRACEMEM_ENA_PRO_TRACEMEM_ENA = 0x1 + + // APP_TRACEMEM_ENA + // Position of APP_TRACEMEM_ENA field. + DPORT_APP_TRACEMEM_ENA_APP_TRACEMEM_ENA_Pos = 0x0 + // Bit mask of APP_TRACEMEM_ENA field. + DPORT_APP_TRACEMEM_ENA_APP_TRACEMEM_ENA_Msk = 0x1 + // Bit APP_TRACEMEM_ENA. + DPORT_APP_TRACEMEM_ENA_APP_TRACEMEM_ENA = 0x1 + + // CACHE_MUX_MODE + // Position of CACHE_MUX_MODE field. + DPORT_CACHE_MUX_MODE_CACHE_MUX_MODE_Pos = 0x0 + // Bit mask of CACHE_MUX_MODE field. + DPORT_CACHE_MUX_MODE_CACHE_MUX_MODE_Msk = 0x3 + + // IMMU_PAGE_MODE + // Position of INTERNAL_SRAM_IMMU_ENA field. + DPORT_IMMU_PAGE_MODE_INTERNAL_SRAM_IMMU_ENA_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_IMMU_ENA field. + DPORT_IMMU_PAGE_MODE_INTERNAL_SRAM_IMMU_ENA_Msk = 0x1 + // Bit INTERNAL_SRAM_IMMU_ENA. + DPORT_IMMU_PAGE_MODE_INTERNAL_SRAM_IMMU_ENA = 0x1 + // Position of IMMU_PAGE_MODE field. + DPORT_IMMU_PAGE_MODE_IMMU_PAGE_MODE_Pos = 0x1 + // Bit mask of IMMU_PAGE_MODE field. + DPORT_IMMU_PAGE_MODE_IMMU_PAGE_MODE_Msk = 0x6 + + // DMMU_PAGE_MODE + // Position of INTERNAL_SRAM_DMMU_ENA field. + DPORT_DMMU_PAGE_MODE_INTERNAL_SRAM_DMMU_ENA_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_DMMU_ENA field. + DPORT_DMMU_PAGE_MODE_INTERNAL_SRAM_DMMU_ENA_Msk = 0x1 + // Bit INTERNAL_SRAM_DMMU_ENA. + DPORT_DMMU_PAGE_MODE_INTERNAL_SRAM_DMMU_ENA = 0x1 + // Position of DMMU_PAGE_MODE field. + DPORT_DMMU_PAGE_MODE_DMMU_PAGE_MODE_Pos = 0x1 + // Bit mask of DMMU_PAGE_MODE field. + DPORT_DMMU_PAGE_MODE_DMMU_PAGE_MODE_Msk = 0x6 + + // ROM_MPU_ENA + // Position of SHARE_ROM_MPU_ENA field. + DPORT_ROM_MPU_ENA_SHARE_ROM_MPU_ENA_Pos = 0x0 + // Bit mask of SHARE_ROM_MPU_ENA field. + DPORT_ROM_MPU_ENA_SHARE_ROM_MPU_ENA_Msk = 0x1 + // Bit SHARE_ROM_MPU_ENA. + DPORT_ROM_MPU_ENA_SHARE_ROM_MPU_ENA = 0x1 + // Position of PRO_ROM_MPU_ENA field. + DPORT_ROM_MPU_ENA_PRO_ROM_MPU_ENA_Pos = 0x1 + // Bit mask of PRO_ROM_MPU_ENA field. + DPORT_ROM_MPU_ENA_PRO_ROM_MPU_ENA_Msk = 0x2 + // Bit PRO_ROM_MPU_ENA. + DPORT_ROM_MPU_ENA_PRO_ROM_MPU_ENA = 0x2 + // Position of APP_ROM_MPU_ENA field. + DPORT_ROM_MPU_ENA_APP_ROM_MPU_ENA_Pos = 0x2 + // Bit mask of APP_ROM_MPU_ENA field. + DPORT_ROM_MPU_ENA_APP_ROM_MPU_ENA_Msk = 0x4 + // Bit APP_ROM_MPU_ENA. + DPORT_ROM_MPU_ENA_APP_ROM_MPU_ENA = 0x4 + + // MEM_PD_MASK + // Position of LSLP_MEM_PD_MASK field. + DPORT_MEM_PD_MASK_LSLP_MEM_PD_MASK_Pos = 0x0 + // Bit mask of LSLP_MEM_PD_MASK field. + DPORT_MEM_PD_MASK_LSLP_MEM_PD_MASK_Msk = 0x1 + // Bit LSLP_MEM_PD_MASK. + DPORT_MEM_PD_MASK_LSLP_MEM_PD_MASK = 0x1 + + // ROM_PD_CTRL + // Position of PRO_ROM_PD field. + DPORT_ROM_PD_CTRL_PRO_ROM_PD_Pos = 0x0 + // Bit mask of PRO_ROM_PD field. + DPORT_ROM_PD_CTRL_PRO_ROM_PD_Msk = 0x1 + // Bit PRO_ROM_PD. + DPORT_ROM_PD_CTRL_PRO_ROM_PD = 0x1 + // Position of APP_ROM_PD field. + DPORT_ROM_PD_CTRL_APP_ROM_PD_Pos = 0x1 + // Bit mask of APP_ROM_PD field. + DPORT_ROM_PD_CTRL_APP_ROM_PD_Msk = 0x2 + // Bit APP_ROM_PD. + DPORT_ROM_PD_CTRL_APP_ROM_PD = 0x2 + // Position of SHARE_ROM_PD field. + DPORT_ROM_PD_CTRL_SHARE_ROM_PD_Pos = 0x2 + // Bit mask of SHARE_ROM_PD field. + DPORT_ROM_PD_CTRL_SHARE_ROM_PD_Msk = 0xfc + + // ROM_FO_CTRL + // Position of PRO_ROM_FO field. + DPORT_ROM_FO_CTRL_PRO_ROM_FO_Pos = 0x0 + // Bit mask of PRO_ROM_FO field. + DPORT_ROM_FO_CTRL_PRO_ROM_FO_Msk = 0x1 + // Bit PRO_ROM_FO. + DPORT_ROM_FO_CTRL_PRO_ROM_FO = 0x1 + // Position of APP_ROM_FO field. + DPORT_ROM_FO_CTRL_APP_ROM_FO_Pos = 0x1 + // Bit mask of APP_ROM_FO field. + DPORT_ROM_FO_CTRL_APP_ROM_FO_Msk = 0x2 + // Bit APP_ROM_FO. + DPORT_ROM_FO_CTRL_APP_ROM_FO = 0x2 + // Position of SHARE_ROM_FO field. + DPORT_ROM_FO_CTRL_SHARE_ROM_FO_Pos = 0x2 + // Bit mask of SHARE_ROM_FO field. + DPORT_ROM_FO_CTRL_SHARE_ROM_FO_Msk = 0xfc + + // SRAM_PD_CTRL_0 + // Position of SRAM_PD_0 field. + DPORT_SRAM_PD_CTRL_0_SRAM_PD_0_Pos = 0x0 + // Bit mask of SRAM_PD_0 field. + DPORT_SRAM_PD_CTRL_0_SRAM_PD_0_Msk = 0xffffffff + + // SRAM_PD_CTRL_1 + // Position of SRAM_PD_1 field. + DPORT_SRAM_PD_CTRL_1_SRAM_PD_1_Pos = 0x0 + // Bit mask of SRAM_PD_1 field. + DPORT_SRAM_PD_CTRL_1_SRAM_PD_1_Msk = 0x1 + // Bit SRAM_PD_1. + DPORT_SRAM_PD_CTRL_1_SRAM_PD_1 = 0x1 + + // SRAM_FO_CTRL_0 + // Position of SRAM_FO_0 field. + DPORT_SRAM_FO_CTRL_0_SRAM_FO_0_Pos = 0x0 + // Bit mask of SRAM_FO_0 field. + DPORT_SRAM_FO_CTRL_0_SRAM_FO_0_Msk = 0xffffffff + + // SRAM_FO_CTRL_1 + // Position of SRAM_FO_1 field. + DPORT_SRAM_FO_CTRL_1_SRAM_FO_1_Pos = 0x0 + // Bit mask of SRAM_FO_1 field. + DPORT_SRAM_FO_CTRL_1_SRAM_FO_1_Msk = 0x1 + // Bit SRAM_FO_1. + DPORT_SRAM_FO_CTRL_1_SRAM_FO_1 = 0x1 + + // IRAM_DRAM_AHB_SEL + // Position of MASK_PRO_IRAM field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_PRO_IRAM_Pos = 0x0 + // Bit mask of MASK_PRO_IRAM field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_PRO_IRAM_Msk = 0x1 + // Bit MASK_PRO_IRAM. + DPORT_IRAM_DRAM_AHB_SEL_MASK_PRO_IRAM = 0x1 + // Position of MASK_APP_IRAM field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_APP_IRAM_Pos = 0x1 + // Bit mask of MASK_APP_IRAM field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_APP_IRAM_Msk = 0x2 + // Bit MASK_APP_IRAM. + DPORT_IRAM_DRAM_AHB_SEL_MASK_APP_IRAM = 0x2 + // Position of MASK_PRO_DRAM field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_PRO_DRAM_Pos = 0x2 + // Bit mask of MASK_PRO_DRAM field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_PRO_DRAM_Msk = 0x4 + // Bit MASK_PRO_DRAM. + DPORT_IRAM_DRAM_AHB_SEL_MASK_PRO_DRAM = 0x4 + // Position of MASK_APP_DRAM field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_APP_DRAM_Pos = 0x3 + // Bit mask of MASK_APP_DRAM field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_APP_DRAM_Msk = 0x8 + // Bit MASK_APP_DRAM. + DPORT_IRAM_DRAM_AHB_SEL_MASK_APP_DRAM = 0x8 + // Position of MASK_AHB field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_AHB_Pos = 0x4 + // Bit mask of MASK_AHB field. + DPORT_IRAM_DRAM_AHB_SEL_MASK_AHB_Msk = 0x10 + // Bit MASK_AHB. + DPORT_IRAM_DRAM_AHB_SEL_MASK_AHB = 0x10 + // Position of MAC_DUMP_MODE field. + DPORT_IRAM_DRAM_AHB_SEL_MAC_DUMP_MODE_Pos = 0x5 + // Bit mask of MAC_DUMP_MODE field. + DPORT_IRAM_DRAM_AHB_SEL_MAC_DUMP_MODE_Msk = 0x60 + + // TAG_FO_CTRL + // Position of PRO_CACHE_TAG_FORCE_ON field. + DPORT_TAG_FO_CTRL_PRO_CACHE_TAG_FORCE_ON_Pos = 0x0 + // Bit mask of PRO_CACHE_TAG_FORCE_ON field. + DPORT_TAG_FO_CTRL_PRO_CACHE_TAG_FORCE_ON_Msk = 0x1 + // Bit PRO_CACHE_TAG_FORCE_ON. + DPORT_TAG_FO_CTRL_PRO_CACHE_TAG_FORCE_ON = 0x1 + // Position of PRO_CACHE_TAG_PD field. + DPORT_TAG_FO_CTRL_PRO_CACHE_TAG_PD_Pos = 0x1 + // Bit mask of PRO_CACHE_TAG_PD field. + DPORT_TAG_FO_CTRL_PRO_CACHE_TAG_PD_Msk = 0x2 + // Bit PRO_CACHE_TAG_PD. + DPORT_TAG_FO_CTRL_PRO_CACHE_TAG_PD = 0x2 + // Position of APP_CACHE_TAG_FORCE_ON field. + DPORT_TAG_FO_CTRL_APP_CACHE_TAG_FORCE_ON_Pos = 0x8 + // Bit mask of APP_CACHE_TAG_FORCE_ON field. + DPORT_TAG_FO_CTRL_APP_CACHE_TAG_FORCE_ON_Msk = 0x100 + // Bit APP_CACHE_TAG_FORCE_ON. + DPORT_TAG_FO_CTRL_APP_CACHE_TAG_FORCE_ON = 0x100 + // Position of APP_CACHE_TAG_PD field. + DPORT_TAG_FO_CTRL_APP_CACHE_TAG_PD_Pos = 0x9 + // Bit mask of APP_CACHE_TAG_PD field. + DPORT_TAG_FO_CTRL_APP_CACHE_TAG_PD_Msk = 0x200 + // Bit APP_CACHE_TAG_PD. + DPORT_TAG_FO_CTRL_APP_CACHE_TAG_PD = 0x200 + + // AHB_LITE_MASK + // Position of PRO field. + DPORT_AHB_LITE_MASK_PRO_Pos = 0x0 + // Bit mask of PRO field. + DPORT_AHB_LITE_MASK_PRO_Msk = 0x1 + // Bit PRO. + DPORT_AHB_LITE_MASK_PRO = 0x1 + // Position of APP field. + DPORT_AHB_LITE_MASK_APP_Pos = 0x4 + // Bit mask of APP field. + DPORT_AHB_LITE_MASK_APP_Msk = 0x10 + // Bit APP. + DPORT_AHB_LITE_MASK_APP = 0x10 + // Position of SDIO field. + DPORT_AHB_LITE_MASK_SDIO_Pos = 0x8 + // Bit mask of SDIO field. + DPORT_AHB_LITE_MASK_SDIO_Msk = 0x100 + // Bit SDIO. + DPORT_AHB_LITE_MASK_SDIO = 0x100 + // Position of PRODPORT field. + DPORT_AHB_LITE_MASK_PRODPORT_Pos = 0x9 + // Bit mask of PRODPORT field. + DPORT_AHB_LITE_MASK_PRODPORT_Msk = 0x200 + // Bit PRODPORT. + DPORT_AHB_LITE_MASK_PRODPORT = 0x200 + // Position of APPDPORT field. + DPORT_AHB_LITE_MASK_APPDPORT_Pos = 0xa + // Bit mask of APPDPORT field. + DPORT_AHB_LITE_MASK_APPDPORT_Msk = 0x400 + // Bit APPDPORT. + DPORT_AHB_LITE_MASK_APPDPORT = 0x400 + // Position of AHB_LITE_SDHOST_PID field. + DPORT_AHB_LITE_MASK_AHB_LITE_SDHOST_PID_Pos = 0xb + // Bit mask of AHB_LITE_SDHOST_PID field. + DPORT_AHB_LITE_MASK_AHB_LITE_SDHOST_PID_Msk = 0x3800 + + // AHB_MPU_TABLE_0 + // Position of AHB_ACCESS_GRANT_0 field. + DPORT_AHB_MPU_TABLE_0_AHB_ACCESS_GRANT_0_Pos = 0x0 + // Bit mask of AHB_ACCESS_GRANT_0 field. + DPORT_AHB_MPU_TABLE_0_AHB_ACCESS_GRANT_0_Msk = 0xffffffff + + // AHB_MPU_TABLE_1 + // Position of AHB_ACCESS_GRANT_1 field. + DPORT_AHB_MPU_TABLE_1_AHB_ACCESS_GRANT_1_Pos = 0x0 + // Bit mask of AHB_ACCESS_GRANT_1 field. + DPORT_AHB_MPU_TABLE_1_AHB_ACCESS_GRANT_1_Msk = 0x1ff + + // HOST_INF_SEL + // Position of PERI_IO_SWAP field. + DPORT_HOST_INF_SEL_PERI_IO_SWAP_Pos = 0x0 + // Bit mask of PERI_IO_SWAP field. + DPORT_HOST_INF_SEL_PERI_IO_SWAP_Msk = 0xff + // Position of LINK_DEVICE_SEL field. + DPORT_HOST_INF_SEL_LINK_DEVICE_SEL_Pos = 0x8 + // Bit mask of LINK_DEVICE_SEL field. + DPORT_HOST_INF_SEL_LINK_DEVICE_SEL_Msk = 0xff00 + + // PERIP_CLK_EN + // Position of TIMERS_CLK_EN field. + DPORT_PERIP_CLK_EN_TIMERS_CLK_EN_Pos = 0x0 + // Bit mask of TIMERS_CLK_EN field. + DPORT_PERIP_CLK_EN_TIMERS_CLK_EN_Msk = 0x1 + // Bit TIMERS_CLK_EN. + DPORT_PERIP_CLK_EN_TIMERS_CLK_EN = 0x1 + // Position of SPI01_CLK_EN field. + DPORT_PERIP_CLK_EN_SPI01_CLK_EN_Pos = 0x1 + // Bit mask of SPI01_CLK_EN field. + DPORT_PERIP_CLK_EN_SPI01_CLK_EN_Msk = 0x2 + // Bit SPI01_CLK_EN. + DPORT_PERIP_CLK_EN_SPI01_CLK_EN = 0x2 + // Position of UART_CLK_EN field. + DPORT_PERIP_CLK_EN_UART_CLK_EN_Pos = 0x2 + // Bit mask of UART_CLK_EN field. + DPORT_PERIP_CLK_EN_UART_CLK_EN_Msk = 0x4 + // Bit UART_CLK_EN. + DPORT_PERIP_CLK_EN_UART_CLK_EN = 0x4 + // Position of WDG_CLK_EN field. + DPORT_PERIP_CLK_EN_WDG_CLK_EN_Pos = 0x3 + // Bit mask of WDG_CLK_EN field. + DPORT_PERIP_CLK_EN_WDG_CLK_EN_Msk = 0x8 + // Bit WDG_CLK_EN. + DPORT_PERIP_CLK_EN_WDG_CLK_EN = 0x8 + // Position of I2S0_CLK_EN field. + DPORT_PERIP_CLK_EN_I2S0_CLK_EN_Pos = 0x4 + // Bit mask of I2S0_CLK_EN field. + DPORT_PERIP_CLK_EN_I2S0_CLK_EN_Msk = 0x10 + // Bit I2S0_CLK_EN. + DPORT_PERIP_CLK_EN_I2S0_CLK_EN = 0x10 + // Position of UART1_CLK_EN field. + DPORT_PERIP_CLK_EN_UART1_CLK_EN_Pos = 0x5 + // Bit mask of UART1_CLK_EN field. + DPORT_PERIP_CLK_EN_UART1_CLK_EN_Msk = 0x20 + // Bit UART1_CLK_EN. + DPORT_PERIP_CLK_EN_UART1_CLK_EN = 0x20 + // Position of SPI2_CLK_EN field. + DPORT_PERIP_CLK_EN_SPI2_CLK_EN_Pos = 0x6 + // Bit mask of SPI2_CLK_EN field. + DPORT_PERIP_CLK_EN_SPI2_CLK_EN_Msk = 0x40 + // Bit SPI2_CLK_EN. + DPORT_PERIP_CLK_EN_SPI2_CLK_EN = 0x40 + // Position of I2C0_EXT0_CLK_EN field. + DPORT_PERIP_CLK_EN_I2C0_EXT0_CLK_EN_Pos = 0x7 + // Bit mask of I2C0_EXT0_CLK_EN field. + DPORT_PERIP_CLK_EN_I2C0_EXT0_CLK_EN_Msk = 0x80 + // Bit I2C0_EXT0_CLK_EN. + DPORT_PERIP_CLK_EN_I2C0_EXT0_CLK_EN = 0x80 + // Position of UHCI0_CLK_EN field. + DPORT_PERIP_CLK_EN_UHCI0_CLK_EN_Pos = 0x8 + // Bit mask of UHCI0_CLK_EN field. + DPORT_PERIP_CLK_EN_UHCI0_CLK_EN_Msk = 0x100 + // Bit UHCI0_CLK_EN. + DPORT_PERIP_CLK_EN_UHCI0_CLK_EN = 0x100 + // Position of RMT_CLK_EN field. + DPORT_PERIP_CLK_EN_RMT_CLK_EN_Pos = 0x9 + // Bit mask of RMT_CLK_EN field. + DPORT_PERIP_CLK_EN_RMT_CLK_EN_Msk = 0x200 + // Bit RMT_CLK_EN. + DPORT_PERIP_CLK_EN_RMT_CLK_EN = 0x200 + // Position of PCNT_CLK_EN field. + DPORT_PERIP_CLK_EN_PCNT_CLK_EN_Pos = 0xa + // Bit mask of PCNT_CLK_EN field. + DPORT_PERIP_CLK_EN_PCNT_CLK_EN_Msk = 0x400 + // Bit PCNT_CLK_EN. + DPORT_PERIP_CLK_EN_PCNT_CLK_EN = 0x400 + // Position of LEDC_CLK_EN field. + DPORT_PERIP_CLK_EN_LEDC_CLK_EN_Pos = 0xb + // Bit mask of LEDC_CLK_EN field. + DPORT_PERIP_CLK_EN_LEDC_CLK_EN_Msk = 0x800 + // Bit LEDC_CLK_EN. + DPORT_PERIP_CLK_EN_LEDC_CLK_EN = 0x800 + // Position of UHCI1_CLK_EN field. + DPORT_PERIP_CLK_EN_UHCI1_CLK_EN_Pos = 0xc + // Bit mask of UHCI1_CLK_EN field. + DPORT_PERIP_CLK_EN_UHCI1_CLK_EN_Msk = 0x1000 + // Bit UHCI1_CLK_EN. + DPORT_PERIP_CLK_EN_UHCI1_CLK_EN = 0x1000 + // Position of TIMERGROUP_CLK_EN field. + DPORT_PERIP_CLK_EN_TIMERGROUP_CLK_EN_Pos = 0xd + // Bit mask of TIMERGROUP_CLK_EN field. + DPORT_PERIP_CLK_EN_TIMERGROUP_CLK_EN_Msk = 0x2000 + // Bit TIMERGROUP_CLK_EN. + DPORT_PERIP_CLK_EN_TIMERGROUP_CLK_EN = 0x2000 + // Position of EFUSE_CLK_EN field. + DPORT_PERIP_CLK_EN_EFUSE_CLK_EN_Pos = 0xe + // Bit mask of EFUSE_CLK_EN field. + DPORT_PERIP_CLK_EN_EFUSE_CLK_EN_Msk = 0x4000 + // Bit EFUSE_CLK_EN. + DPORT_PERIP_CLK_EN_EFUSE_CLK_EN = 0x4000 + // Position of TIMERGROUP1_CLK_EN field. + DPORT_PERIP_CLK_EN_TIMERGROUP1_CLK_EN_Pos = 0xf + // Bit mask of TIMERGROUP1_CLK_EN field. + DPORT_PERIP_CLK_EN_TIMERGROUP1_CLK_EN_Msk = 0x8000 + // Bit TIMERGROUP1_CLK_EN. + DPORT_PERIP_CLK_EN_TIMERGROUP1_CLK_EN = 0x8000 + // Position of SPI3_CLK_EN field. + DPORT_PERIP_CLK_EN_SPI3_CLK_EN_Pos = 0x10 + // Bit mask of SPI3_CLK_EN field. + DPORT_PERIP_CLK_EN_SPI3_CLK_EN_Msk = 0x10000 + // Bit SPI3_CLK_EN. + DPORT_PERIP_CLK_EN_SPI3_CLK_EN = 0x10000 + // Position of PWM0_CLK_EN field. + DPORT_PERIP_CLK_EN_PWM0_CLK_EN_Pos = 0x11 + // Bit mask of PWM0_CLK_EN field. + DPORT_PERIP_CLK_EN_PWM0_CLK_EN_Msk = 0x20000 + // Bit PWM0_CLK_EN. + DPORT_PERIP_CLK_EN_PWM0_CLK_EN = 0x20000 + // Position of I2C_EXT1_CLK_EN field. + DPORT_PERIP_CLK_EN_I2C_EXT1_CLK_EN_Pos = 0x12 + // Bit mask of I2C_EXT1_CLK_EN field. + DPORT_PERIP_CLK_EN_I2C_EXT1_CLK_EN_Msk = 0x40000 + // Bit I2C_EXT1_CLK_EN. + DPORT_PERIP_CLK_EN_I2C_EXT1_CLK_EN = 0x40000 + // Position of TWAI_CLK_EN field. + DPORT_PERIP_CLK_EN_TWAI_CLK_EN_Pos = 0x13 + // Bit mask of TWAI_CLK_EN field. + DPORT_PERIP_CLK_EN_TWAI_CLK_EN_Msk = 0x80000 + // Bit TWAI_CLK_EN. + DPORT_PERIP_CLK_EN_TWAI_CLK_EN = 0x80000 + // Position of PWM1_CLK_EN field. + DPORT_PERIP_CLK_EN_PWM1_CLK_EN_Pos = 0x14 + // Bit mask of PWM1_CLK_EN field. + DPORT_PERIP_CLK_EN_PWM1_CLK_EN_Msk = 0x100000 + // Bit PWM1_CLK_EN. + DPORT_PERIP_CLK_EN_PWM1_CLK_EN = 0x100000 + // Position of I2S1_CLK_EN field. + DPORT_PERIP_CLK_EN_I2S1_CLK_EN_Pos = 0x15 + // Bit mask of I2S1_CLK_EN field. + DPORT_PERIP_CLK_EN_I2S1_CLK_EN_Msk = 0x200000 + // Bit I2S1_CLK_EN. + DPORT_PERIP_CLK_EN_I2S1_CLK_EN = 0x200000 + // Position of SPI_DMA_CLK_EN field. + DPORT_PERIP_CLK_EN_SPI_DMA_CLK_EN_Pos = 0x16 + // Bit mask of SPI_DMA_CLK_EN field. + DPORT_PERIP_CLK_EN_SPI_DMA_CLK_EN_Msk = 0x400000 + // Bit SPI_DMA_CLK_EN. + DPORT_PERIP_CLK_EN_SPI_DMA_CLK_EN = 0x400000 + // Position of UART2_CLK_EN field. + DPORT_PERIP_CLK_EN_UART2_CLK_EN_Pos = 0x17 + // Bit mask of UART2_CLK_EN field. + DPORT_PERIP_CLK_EN_UART2_CLK_EN_Msk = 0x800000 + // Bit UART2_CLK_EN. + DPORT_PERIP_CLK_EN_UART2_CLK_EN = 0x800000 + // Position of UART_MEM_CLK_EN field. + DPORT_PERIP_CLK_EN_UART_MEM_CLK_EN_Pos = 0x18 + // Bit mask of UART_MEM_CLK_EN field. + DPORT_PERIP_CLK_EN_UART_MEM_CLK_EN_Msk = 0x1000000 + // Bit UART_MEM_CLK_EN. + DPORT_PERIP_CLK_EN_UART_MEM_CLK_EN = 0x1000000 + // Position of PWM2_CLK_EN field. + DPORT_PERIP_CLK_EN_PWM2_CLK_EN_Pos = 0x19 + // Bit mask of PWM2_CLK_EN field. + DPORT_PERIP_CLK_EN_PWM2_CLK_EN_Msk = 0x2000000 + // Bit PWM2_CLK_EN. + DPORT_PERIP_CLK_EN_PWM2_CLK_EN = 0x2000000 + // Position of PWM3_CLK_EN field. + DPORT_PERIP_CLK_EN_PWM3_CLK_EN_Pos = 0x1a + // Bit mask of PWM3_CLK_EN field. + DPORT_PERIP_CLK_EN_PWM3_CLK_EN_Msk = 0x4000000 + // Bit PWM3_CLK_EN. + DPORT_PERIP_CLK_EN_PWM3_CLK_EN = 0x4000000 + + // PERIP_RST_EN + // Position of TIMERS_RST field. + DPORT_PERIP_RST_EN_TIMERS_RST_Pos = 0x0 + // Bit mask of TIMERS_RST field. + DPORT_PERIP_RST_EN_TIMERS_RST_Msk = 0x1 + // Bit TIMERS_RST. + DPORT_PERIP_RST_EN_TIMERS_RST = 0x1 + // Position of SPI01_RST field. + DPORT_PERIP_RST_EN_SPI01_RST_Pos = 0x1 + // Bit mask of SPI01_RST field. + DPORT_PERIP_RST_EN_SPI01_RST_Msk = 0x2 + // Bit SPI01_RST. + DPORT_PERIP_RST_EN_SPI01_RST = 0x2 + // Position of UART_RST field. + DPORT_PERIP_RST_EN_UART_RST_Pos = 0x2 + // Bit mask of UART_RST field. + DPORT_PERIP_RST_EN_UART_RST_Msk = 0x4 + // Bit UART_RST. + DPORT_PERIP_RST_EN_UART_RST = 0x4 + // Position of WDG_RST field. + DPORT_PERIP_RST_EN_WDG_RST_Pos = 0x3 + // Bit mask of WDG_RST field. + DPORT_PERIP_RST_EN_WDG_RST_Msk = 0x8 + // Bit WDG_RST. + DPORT_PERIP_RST_EN_WDG_RST = 0x8 + // Position of I2S0_RST field. + DPORT_PERIP_RST_EN_I2S0_RST_Pos = 0x4 + // Bit mask of I2S0_RST field. + DPORT_PERIP_RST_EN_I2S0_RST_Msk = 0x10 + // Bit I2S0_RST. + DPORT_PERIP_RST_EN_I2S0_RST = 0x10 + // Position of UART1_RST field. + DPORT_PERIP_RST_EN_UART1_RST_Pos = 0x5 + // Bit mask of UART1_RST field. + DPORT_PERIP_RST_EN_UART1_RST_Msk = 0x20 + // Bit UART1_RST. + DPORT_PERIP_RST_EN_UART1_RST = 0x20 + // Position of SPI2_RST field. + DPORT_PERIP_RST_EN_SPI2_RST_Pos = 0x6 + // Bit mask of SPI2_RST field. + DPORT_PERIP_RST_EN_SPI2_RST_Msk = 0x40 + // Bit SPI2_RST. + DPORT_PERIP_RST_EN_SPI2_RST = 0x40 + // Position of I2C0_EXT0_RST field. + DPORT_PERIP_RST_EN_I2C0_EXT0_RST_Pos = 0x7 + // Bit mask of I2C0_EXT0_RST field. + DPORT_PERIP_RST_EN_I2C0_EXT0_RST_Msk = 0x80 + // Bit I2C0_EXT0_RST. + DPORT_PERIP_RST_EN_I2C0_EXT0_RST = 0x80 + // Position of UHCI0_RST field. + DPORT_PERIP_RST_EN_UHCI0_RST_Pos = 0x8 + // Bit mask of UHCI0_RST field. + DPORT_PERIP_RST_EN_UHCI0_RST_Msk = 0x100 + // Bit UHCI0_RST. + DPORT_PERIP_RST_EN_UHCI0_RST = 0x100 + // Position of RMT_RST field. + DPORT_PERIP_RST_EN_RMT_RST_Pos = 0x9 + // Bit mask of RMT_RST field. + DPORT_PERIP_RST_EN_RMT_RST_Msk = 0x200 + // Bit RMT_RST. + DPORT_PERIP_RST_EN_RMT_RST = 0x200 + // Position of PCNT_RST field. + DPORT_PERIP_RST_EN_PCNT_RST_Pos = 0xa + // Bit mask of PCNT_RST field. + DPORT_PERIP_RST_EN_PCNT_RST_Msk = 0x400 + // Bit PCNT_RST. + DPORT_PERIP_RST_EN_PCNT_RST = 0x400 + // Position of LEDC_RST field. + DPORT_PERIP_RST_EN_LEDC_RST_Pos = 0xb + // Bit mask of LEDC_RST field. + DPORT_PERIP_RST_EN_LEDC_RST_Msk = 0x800 + // Bit LEDC_RST. + DPORT_PERIP_RST_EN_LEDC_RST = 0x800 + // Position of UHCI1_RST field. + DPORT_PERIP_RST_EN_UHCI1_RST_Pos = 0xc + // Bit mask of UHCI1_RST field. + DPORT_PERIP_RST_EN_UHCI1_RST_Msk = 0x1000 + // Bit UHCI1_RST. + DPORT_PERIP_RST_EN_UHCI1_RST = 0x1000 + // Position of TIMERGROUP_RST field. + DPORT_PERIP_RST_EN_TIMERGROUP_RST_Pos = 0xd + // Bit mask of TIMERGROUP_RST field. + DPORT_PERIP_RST_EN_TIMERGROUP_RST_Msk = 0x2000 + // Bit TIMERGROUP_RST. + DPORT_PERIP_RST_EN_TIMERGROUP_RST = 0x2000 + // Position of EFUSE_RST field. + DPORT_PERIP_RST_EN_EFUSE_RST_Pos = 0xe + // Bit mask of EFUSE_RST field. + DPORT_PERIP_RST_EN_EFUSE_RST_Msk = 0x4000 + // Bit EFUSE_RST. + DPORT_PERIP_RST_EN_EFUSE_RST = 0x4000 + // Position of TIMERGROUP1_RST field. + DPORT_PERIP_RST_EN_TIMERGROUP1_RST_Pos = 0xf + // Bit mask of TIMERGROUP1_RST field. + DPORT_PERIP_RST_EN_TIMERGROUP1_RST_Msk = 0x8000 + // Bit TIMERGROUP1_RST. + DPORT_PERIP_RST_EN_TIMERGROUP1_RST = 0x8000 + // Position of SPI3_RST field. + DPORT_PERIP_RST_EN_SPI3_RST_Pos = 0x10 + // Bit mask of SPI3_RST field. + DPORT_PERIP_RST_EN_SPI3_RST_Msk = 0x10000 + // Bit SPI3_RST. + DPORT_PERIP_RST_EN_SPI3_RST = 0x10000 + // Position of PWM0_RST field. + DPORT_PERIP_RST_EN_PWM0_RST_Pos = 0x11 + // Bit mask of PWM0_RST field. + DPORT_PERIP_RST_EN_PWM0_RST_Msk = 0x20000 + // Bit PWM0_RST. + DPORT_PERIP_RST_EN_PWM0_RST = 0x20000 + // Position of I2C_EXT1_RST field. + DPORT_PERIP_RST_EN_I2C_EXT1_RST_Pos = 0x12 + // Bit mask of I2C_EXT1_RST field. + DPORT_PERIP_RST_EN_I2C_EXT1_RST_Msk = 0x40000 + // Bit I2C_EXT1_RST. + DPORT_PERIP_RST_EN_I2C_EXT1_RST = 0x40000 + // Position of TWAI_RST field. + DPORT_PERIP_RST_EN_TWAI_RST_Pos = 0x13 + // Bit mask of TWAI_RST field. + DPORT_PERIP_RST_EN_TWAI_RST_Msk = 0x80000 + // Bit TWAI_RST. + DPORT_PERIP_RST_EN_TWAI_RST = 0x80000 + // Position of PWM1_RST field. + DPORT_PERIP_RST_EN_PWM1_RST_Pos = 0x14 + // Bit mask of PWM1_RST field. + DPORT_PERIP_RST_EN_PWM1_RST_Msk = 0x100000 + // Bit PWM1_RST. + DPORT_PERIP_RST_EN_PWM1_RST = 0x100000 + // Position of I2S1_RST field. + DPORT_PERIP_RST_EN_I2S1_RST_Pos = 0x15 + // Bit mask of I2S1_RST field. + DPORT_PERIP_RST_EN_I2S1_RST_Msk = 0x200000 + // Bit I2S1_RST. + DPORT_PERIP_RST_EN_I2S1_RST = 0x200000 + // Position of SPI_DMA_RST field. + DPORT_PERIP_RST_EN_SPI_DMA_RST_Pos = 0x16 + // Bit mask of SPI_DMA_RST field. + DPORT_PERIP_RST_EN_SPI_DMA_RST_Msk = 0x400000 + // Bit SPI_DMA_RST. + DPORT_PERIP_RST_EN_SPI_DMA_RST = 0x400000 + // Position of UART2_RST field. + DPORT_PERIP_RST_EN_UART2_RST_Pos = 0x17 + // Bit mask of UART2_RST field. + DPORT_PERIP_RST_EN_UART2_RST_Msk = 0x800000 + // Bit UART2_RST. + DPORT_PERIP_RST_EN_UART2_RST = 0x800000 + // Position of UART_MEM_RST field. + DPORT_PERIP_RST_EN_UART_MEM_RST_Pos = 0x18 + // Bit mask of UART_MEM_RST field. + DPORT_PERIP_RST_EN_UART_MEM_RST_Msk = 0x1000000 + // Bit UART_MEM_RST. + DPORT_PERIP_RST_EN_UART_MEM_RST = 0x1000000 + // Position of PWM2_RST field. + DPORT_PERIP_RST_EN_PWM2_RST_Pos = 0x19 + // Bit mask of PWM2_RST field. + DPORT_PERIP_RST_EN_PWM2_RST_Msk = 0x2000000 + // Bit PWM2_RST. + DPORT_PERIP_RST_EN_PWM2_RST = 0x2000000 + // Position of PWM3_RST field. + DPORT_PERIP_RST_EN_PWM3_RST_Pos = 0x1a + // Bit mask of PWM3_RST field. + DPORT_PERIP_RST_EN_PWM3_RST_Msk = 0x4000000 + // Bit PWM3_RST. + DPORT_PERIP_RST_EN_PWM3_RST = 0x4000000 + + // SLAVE_SPI_CONFIG + // Position of SLAVE_SPI_MASK_PRO field. + DPORT_SLAVE_SPI_CONFIG_SLAVE_SPI_MASK_PRO_Pos = 0x0 + // Bit mask of SLAVE_SPI_MASK_PRO field. + DPORT_SLAVE_SPI_CONFIG_SLAVE_SPI_MASK_PRO_Msk = 0x1 + // Bit SLAVE_SPI_MASK_PRO. + DPORT_SLAVE_SPI_CONFIG_SLAVE_SPI_MASK_PRO = 0x1 + // Position of SLAVE_SPI_MASK_APP field. + DPORT_SLAVE_SPI_CONFIG_SLAVE_SPI_MASK_APP_Pos = 0x4 + // Bit mask of SLAVE_SPI_MASK_APP field. + DPORT_SLAVE_SPI_CONFIG_SLAVE_SPI_MASK_APP_Msk = 0x10 + // Bit SLAVE_SPI_MASK_APP. + DPORT_SLAVE_SPI_CONFIG_SLAVE_SPI_MASK_APP = 0x10 + // Position of SPI_ENCRYPT_ENABLE field. + DPORT_SLAVE_SPI_CONFIG_SPI_ENCRYPT_ENABLE_Pos = 0x8 + // Bit mask of SPI_ENCRYPT_ENABLE field. + DPORT_SLAVE_SPI_CONFIG_SPI_ENCRYPT_ENABLE_Msk = 0x100 + // Bit SPI_ENCRYPT_ENABLE. + DPORT_SLAVE_SPI_CONFIG_SPI_ENCRYPT_ENABLE = 0x100 + // Position of SPI_DECRYPT_ENABLE field. + DPORT_SLAVE_SPI_CONFIG_SPI_DECRYPT_ENABLE_Pos = 0xc + // Bit mask of SPI_DECRYPT_ENABLE field. + DPORT_SLAVE_SPI_CONFIG_SPI_DECRYPT_ENABLE_Msk = 0x1000 + // Bit SPI_DECRYPT_ENABLE. + DPORT_SLAVE_SPI_CONFIG_SPI_DECRYPT_ENABLE = 0x1000 + + // WIFI_CLK_EN + // Position of WIFI_CLK_EN field. + DPORT_WIFI_CLK_EN_WIFI_CLK_EN_Pos = 0x0 + // Bit mask of WIFI_CLK_EN field. + DPORT_WIFI_CLK_EN_WIFI_CLK_EN_Msk = 0xffffffff + // Position of WIFI_CLK_WIFI_EN field. + DPORT_WIFI_CLK_EN_WIFI_CLK_WIFI_EN_Pos = 0x0 + // Bit mask of WIFI_CLK_WIFI_EN field. + DPORT_WIFI_CLK_EN_WIFI_CLK_WIFI_EN_Msk = 0x7 + // Position of WIFI_CLK_WIFI_BT_COMMON field. + DPORT_WIFI_CLK_EN_WIFI_CLK_WIFI_BT_COMMON_Pos = 0x0 + // Bit mask of WIFI_CLK_WIFI_BT_COMMON field. + DPORT_WIFI_CLK_EN_WIFI_CLK_WIFI_BT_COMMON_Msk = 0x3f + // Position of WIFI_CLK_BT_EN field. + DPORT_WIFI_CLK_EN_WIFI_CLK_BT_EN_Pos = 0xb + // Bit mask of WIFI_CLK_BT_EN field. + DPORT_WIFI_CLK_EN_WIFI_CLK_BT_EN_Msk = 0x3800 + + // CORE_RST_EN + // Position of CORE_RST field. + DPORT_CORE_RST_EN_CORE_RST_Pos = 0x0 + // Bit mask of CORE_RST field. + DPORT_CORE_RST_EN_CORE_RST_Msk = 0xff + + // BT_LPCK_DIV_INT + // Position of BT_LPCK_DIV_NUM field. + DPORT_BT_LPCK_DIV_INT_BT_LPCK_DIV_NUM_Pos = 0x0 + // Bit mask of BT_LPCK_DIV_NUM field. + DPORT_BT_LPCK_DIV_INT_BT_LPCK_DIV_NUM_Msk = 0xfff + // Position of BTEXTWAKEUP_REQ field. + DPORT_BT_LPCK_DIV_INT_BTEXTWAKEUP_REQ_Pos = 0xc + // Bit mask of BTEXTWAKEUP_REQ field. + DPORT_BT_LPCK_DIV_INT_BTEXTWAKEUP_REQ_Msk = 0x1000 + // Bit BTEXTWAKEUP_REQ. + DPORT_BT_LPCK_DIV_INT_BTEXTWAKEUP_REQ = 0x1000 + + // BT_LPCK_DIV_FRAC + // Position of BT_LPCK_DIV_B field. + DPORT_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_B_Pos = 0x0 + // Bit mask of BT_LPCK_DIV_B field. + DPORT_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_B_Msk = 0xfff + // Position of BT_LPCK_DIV_A field. + DPORT_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_A_Pos = 0xc + // Bit mask of BT_LPCK_DIV_A field. + DPORT_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_A_Msk = 0xfff000 + // Position of LPCLK_SEL_RTC_SLOW field. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Pos = 0x18 + // Bit mask of LPCLK_SEL_RTC_SLOW field. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Msk = 0x1000000 + // Bit LPCLK_SEL_RTC_SLOW. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW = 0x1000000 + // Position of LPCLK_SEL_8M field. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Pos = 0x19 + // Bit mask of LPCLK_SEL_8M field. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Msk = 0x2000000 + // Bit LPCLK_SEL_8M. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M = 0x2000000 + // Position of LPCLK_SEL_XTAL field. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Pos = 0x1a + // Bit mask of LPCLK_SEL_XTAL field. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Msk = 0x4000000 + // Bit LPCLK_SEL_XTAL. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL = 0x4000000 + // Position of LPCLK_SEL_XTAL32K field. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Pos = 0x1b + // Bit mask of LPCLK_SEL_XTAL32K field. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Msk = 0x8000000 + // Bit LPCLK_SEL_XTAL32K. + DPORT_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K = 0x8000000 + + // CPU_INTR_FROM_CPU_0 + // Position of CPU_INTR_FROM_CPU_0 field. + DPORT_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0 field. + DPORT_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_0. + DPORT_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0 = 0x1 + + // CPU_INTR_FROM_CPU_1 + // Position of CPU_INTR_FROM_CPU_1 field. + DPORT_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1 field. + DPORT_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_1. + DPORT_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1 = 0x1 + + // CPU_INTR_FROM_CPU_2 + // Position of CPU_INTR_FROM_CPU_2 field. + DPORT_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2 field. + DPORT_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_2. + DPORT_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2 = 0x1 + + // CPU_INTR_FROM_CPU_3 + // Position of CPU_INTR_FROM_CPU_3 field. + DPORT_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3 field. + DPORT_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_3. + DPORT_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3 = 0x1 + + // PRO_INTR_STATUS_0 + // Position of PRO_INTR_STATUS_0 field. + DPORT_PRO_INTR_STATUS_0_PRO_INTR_STATUS_0_Pos = 0x0 + // Bit mask of PRO_INTR_STATUS_0 field. + DPORT_PRO_INTR_STATUS_0_PRO_INTR_STATUS_0_Msk = 0xffffffff + + // PRO_INTR_STATUS_1 + // Position of PRO_INTR_STATUS_1 field. + DPORT_PRO_INTR_STATUS_1_PRO_INTR_STATUS_1_Pos = 0x0 + // Bit mask of PRO_INTR_STATUS_1 field. + DPORT_PRO_INTR_STATUS_1_PRO_INTR_STATUS_1_Msk = 0xffffffff + + // PRO_INTR_STATUS_2 + // Position of PRO_INTR_STATUS_2 field. + DPORT_PRO_INTR_STATUS_2_PRO_INTR_STATUS_2_Pos = 0x0 + // Bit mask of PRO_INTR_STATUS_2 field. + DPORT_PRO_INTR_STATUS_2_PRO_INTR_STATUS_2_Msk = 0xffffffff + + // APP_INTR_STATUS_0 + // Position of APP_INTR_STATUS_0 field. + DPORT_APP_INTR_STATUS_0_APP_INTR_STATUS_0_Pos = 0x0 + // Bit mask of APP_INTR_STATUS_0 field. + DPORT_APP_INTR_STATUS_0_APP_INTR_STATUS_0_Msk = 0xffffffff + + // APP_INTR_STATUS_1 + // Position of APP_INTR_STATUS_1 field. + DPORT_APP_INTR_STATUS_1_APP_INTR_STATUS_1_Pos = 0x0 + // Bit mask of APP_INTR_STATUS_1 field. + DPORT_APP_INTR_STATUS_1_APP_INTR_STATUS_1_Msk = 0xffffffff + + // APP_INTR_STATUS_2 + // Position of APP_INTR_STATUS_2 field. + DPORT_APP_INTR_STATUS_2_APP_INTR_STATUS_2_Pos = 0x0 + // Bit mask of APP_INTR_STATUS_2 field. + DPORT_APP_INTR_STATUS_2_APP_INTR_STATUS_2_Msk = 0xffffffff + + // PRO_MAC_INTR_MAP + // Position of PRO_MAC_INTR_MAP field. + DPORT_PRO_MAC_INTR_MAP_PRO_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_MAC_INTR_MAP field. + DPORT_PRO_MAC_INTR_MAP_PRO_MAC_INTR_MAP_Msk = 0x1f + + // PRO_MAC_NMI_MAP + // Position of PRO_MAC_NMI_MAP field. + DPORT_PRO_MAC_NMI_MAP_PRO_MAC_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_MAC_NMI_MAP field. + DPORT_PRO_MAC_NMI_MAP_PRO_MAC_NMI_MAP_Msk = 0x1f + + // PRO_BB_INT_MAP + // Position of PRO_BB_INT_MAP field. + DPORT_PRO_BB_INT_MAP_PRO_BB_INT_MAP_Pos = 0x0 + // Bit mask of PRO_BB_INT_MAP field. + DPORT_PRO_BB_INT_MAP_PRO_BB_INT_MAP_Msk = 0x1f + + // PRO_BT_MAC_INT_MAP + // Position of PRO_BT_MAC_INT_MAP field. + DPORT_PRO_BT_MAC_INT_MAP_PRO_BT_MAC_INT_MAP_Pos = 0x0 + // Bit mask of PRO_BT_MAC_INT_MAP field. + DPORT_PRO_BT_MAC_INT_MAP_PRO_BT_MAC_INT_MAP_Msk = 0x1f + + // PRO_BT_BB_INT_MAP + // Position of PRO_BT_BB_INT_MAP field. + DPORT_PRO_BT_BB_INT_MAP_PRO_BT_BB_INT_MAP_Pos = 0x0 + // Bit mask of PRO_BT_BB_INT_MAP field. + DPORT_PRO_BT_BB_INT_MAP_PRO_BT_BB_INT_MAP_Msk = 0x1f + + // PRO_BT_BB_NMI_MAP + // Position of PRO_BT_BB_NMI_MAP field. + DPORT_PRO_BT_BB_NMI_MAP_PRO_BT_BB_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_BT_BB_NMI_MAP field. + DPORT_PRO_BT_BB_NMI_MAP_PRO_BT_BB_NMI_MAP_Msk = 0x1f + + // PRO_RWBT_IRQ_MAP + // Position of PRO_RWBT_IRQ_MAP field. + DPORT_PRO_RWBT_IRQ_MAP_PRO_RWBT_IRQ_MAP_Pos = 0x0 + // Bit mask of PRO_RWBT_IRQ_MAP field. + DPORT_PRO_RWBT_IRQ_MAP_PRO_RWBT_IRQ_MAP_Msk = 0x1f + + // PRO_RWBLE_IRQ_MAP + // Position of PRO_RWBLE_IRQ_MAP field. + DPORT_PRO_RWBLE_IRQ_MAP_PRO_RWBLE_IRQ_MAP_Pos = 0x0 + // Bit mask of PRO_RWBLE_IRQ_MAP field. + DPORT_PRO_RWBLE_IRQ_MAP_PRO_RWBLE_IRQ_MAP_Msk = 0x1f + + // PRO_RWBT_NMI_MAP + // Position of PRO_RWBT_NMI_MAP field. + DPORT_PRO_RWBT_NMI_MAP_PRO_RWBT_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_RWBT_NMI_MAP field. + DPORT_PRO_RWBT_NMI_MAP_PRO_RWBT_NMI_MAP_Msk = 0x1f + + // PRO_RWBLE_NMI_MAP + // Position of PRO_RWBLE_NMI_MAP field. + DPORT_PRO_RWBLE_NMI_MAP_PRO_RWBLE_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_RWBLE_NMI_MAP field. + DPORT_PRO_RWBLE_NMI_MAP_PRO_RWBLE_NMI_MAP_Msk = 0x1f + + // PRO_SLC0_INTR_MAP + // Position of PRO_SLC0_INTR_MAP field. + DPORT_PRO_SLC0_INTR_MAP_PRO_SLC0_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_SLC0_INTR_MAP field. + DPORT_PRO_SLC0_INTR_MAP_PRO_SLC0_INTR_MAP_Msk = 0x1f + + // PRO_SLC1_INTR_MAP + // Position of PRO_SLC1_INTR_MAP field. + DPORT_PRO_SLC1_INTR_MAP_PRO_SLC1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_SLC1_INTR_MAP field. + DPORT_PRO_SLC1_INTR_MAP_PRO_SLC1_INTR_MAP_Msk = 0x1f + + // PRO_UHCI0_INTR_MAP + // Position of PRO_UHCI0_INTR_MAP field. + DPORT_PRO_UHCI0_INTR_MAP_PRO_UHCI0_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UHCI0_INTR_MAP field. + DPORT_PRO_UHCI0_INTR_MAP_PRO_UHCI0_INTR_MAP_Msk = 0x1f + + // PRO_UHCI1_INTR_MAP + // Position of PRO_UHCI1_INTR_MAP field. + DPORT_PRO_UHCI1_INTR_MAP_PRO_UHCI1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UHCI1_INTR_MAP field. + DPORT_PRO_UHCI1_INTR_MAP_PRO_UHCI1_INTR_MAP_Msk = 0x1f + + // PRO_TG_T0_LEVEL_INT_MAP + // Position of PRO_TG_T0_LEVEL_INT_MAP field. + DPORT_PRO_TG_T0_LEVEL_INT_MAP_PRO_TG_T0_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_T0_LEVEL_INT_MAP field. + DPORT_PRO_TG_T0_LEVEL_INT_MAP_PRO_TG_T0_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG_T1_LEVEL_INT_MAP + // Position of PRO_TG_T1_LEVEL_INT_MAP field. + DPORT_PRO_TG_T1_LEVEL_INT_MAP_PRO_TG_T1_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_T1_LEVEL_INT_MAP field. + DPORT_PRO_TG_T1_LEVEL_INT_MAP_PRO_TG_T1_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG_WDT_LEVEL_INT_MAP + // Position of PRO_TG_WDT_LEVEL_INT_MAP field. + DPORT_PRO_TG_WDT_LEVEL_INT_MAP_PRO_TG_WDT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_WDT_LEVEL_INT_MAP field. + DPORT_PRO_TG_WDT_LEVEL_INT_MAP_PRO_TG_WDT_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG_LACT_LEVEL_INT_MAP + // Position of PRO_TG_LACT_LEVEL_INT_MAP field. + DPORT_PRO_TG_LACT_LEVEL_INT_MAP_PRO_TG_LACT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_LACT_LEVEL_INT_MAP field. + DPORT_PRO_TG_LACT_LEVEL_INT_MAP_PRO_TG_LACT_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG1_T0_LEVEL_INT_MAP + // Position of PRO_TG1_T0_LEVEL_INT_MAP field. + DPORT_PRO_TG1_T0_LEVEL_INT_MAP_PRO_TG1_T0_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_T0_LEVEL_INT_MAP field. + DPORT_PRO_TG1_T0_LEVEL_INT_MAP_PRO_TG1_T0_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG1_T1_LEVEL_INT_MAP + // Position of PRO_TG1_T1_LEVEL_INT_MAP field. + DPORT_PRO_TG1_T1_LEVEL_INT_MAP_PRO_TG1_T1_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_T1_LEVEL_INT_MAP field. + DPORT_PRO_TG1_T1_LEVEL_INT_MAP_PRO_TG1_T1_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG1_WDT_LEVEL_INT_MAP + // Position of PRO_TG1_WDT_LEVEL_INT_MAP field. + DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_PRO_TG1_WDT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_WDT_LEVEL_INT_MAP field. + DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_PRO_TG1_WDT_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG1_LACT_LEVEL_INT_MAP + // Position of PRO_TG1_LACT_LEVEL_INT_MAP field. + DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_PRO_TG1_LACT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_LACT_LEVEL_INT_MAP field. + DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_PRO_TG1_LACT_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_GPIO_INTERRUPT_MAP + // Position of PRO_GPIO_INTERRUPT_PRO_MAP field. + DPORT_PRO_GPIO_INTERRUPT_MAP_PRO_GPIO_INTERRUPT_PRO_MAP_Pos = 0x0 + // Bit mask of PRO_GPIO_INTERRUPT_PRO_MAP field. + DPORT_PRO_GPIO_INTERRUPT_MAP_PRO_GPIO_INTERRUPT_PRO_MAP_Msk = 0x1f + + // PRO_GPIO_INTERRUPT_NMI_MAP + // Position of PRO_GPIO_INTERRUPT_PRO_NMI_MAP field. + DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_GPIO_INTERRUPT_PRO_NMI_MAP field. + DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_Msk = 0x1f + + // PRO_CPU_INTR_FROM_CPU_0_MAP + // Position of PRO_CPU_INTR_FROM_CPU_0_MAP field. + DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_PRO_CPU_INTR_FROM_CPU_0_MAP_Pos = 0x0 + // Bit mask of PRO_CPU_INTR_FROM_CPU_0_MAP field. + DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_PRO_CPU_INTR_FROM_CPU_0_MAP_Msk = 0x1f + + // PRO_CPU_INTR_FROM_CPU_1_MAP + // Position of PRO_CPU_INTR_FROM_CPU_1_MAP field. + DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_PRO_CPU_INTR_FROM_CPU_1_MAP_Pos = 0x0 + // Bit mask of PRO_CPU_INTR_FROM_CPU_1_MAP field. + DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_PRO_CPU_INTR_FROM_CPU_1_MAP_Msk = 0x1f + + // PRO_CPU_INTR_FROM_CPU_2_MAP + // Position of PRO_CPU_INTR_FROM_CPU_2_MAP field. + DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_PRO_CPU_INTR_FROM_CPU_2_MAP_Pos = 0x0 + // Bit mask of PRO_CPU_INTR_FROM_CPU_2_MAP field. + DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_PRO_CPU_INTR_FROM_CPU_2_MAP_Msk = 0x1f + + // PRO_CPU_INTR_FROM_CPU_3_MAP + // Position of PRO_CPU_INTR_FROM_CPU_3_MAP field. + DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_PRO_CPU_INTR_FROM_CPU_3_MAP_Pos = 0x0 + // Bit mask of PRO_CPU_INTR_FROM_CPU_3_MAP field. + DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_PRO_CPU_INTR_FROM_CPU_3_MAP_Msk = 0x1f + + // PRO_SPI_INTR_0_MAP + // Position of PRO_SPI_INTR_0_MAP field. + DPORT_PRO_SPI_INTR_0_MAP_PRO_SPI_INTR_0_MAP_Pos = 0x0 + // Bit mask of PRO_SPI_INTR_0_MAP field. + DPORT_PRO_SPI_INTR_0_MAP_PRO_SPI_INTR_0_MAP_Msk = 0x1f + + // PRO_SPI_INTR_1_MAP + // Position of PRO_SPI_INTR_1_MAP field. + DPORT_PRO_SPI_INTR_1_MAP_PRO_SPI_INTR_1_MAP_Pos = 0x0 + // Bit mask of PRO_SPI_INTR_1_MAP field. + DPORT_PRO_SPI_INTR_1_MAP_PRO_SPI_INTR_1_MAP_Msk = 0x1f + + // PRO_SPI_INTR_2_MAP + // Position of PRO_SPI_INTR_2_MAP field. + DPORT_PRO_SPI_INTR_2_MAP_PRO_SPI_INTR_2_MAP_Pos = 0x0 + // Bit mask of PRO_SPI_INTR_2_MAP field. + DPORT_PRO_SPI_INTR_2_MAP_PRO_SPI_INTR_2_MAP_Msk = 0x1f + + // PRO_SPI_INTR_3_MAP + // Position of PRO_SPI_INTR_3_MAP field. + DPORT_PRO_SPI_INTR_3_MAP_PRO_SPI_INTR_3_MAP_Pos = 0x0 + // Bit mask of PRO_SPI_INTR_3_MAP field. + DPORT_PRO_SPI_INTR_3_MAP_PRO_SPI_INTR_3_MAP_Msk = 0x1f + + // PRO_I2S0_INT_MAP + // Position of PRO_I2S0_INT_MAP field. + DPORT_PRO_I2S0_INT_MAP_PRO_I2S0_INT_MAP_Pos = 0x0 + // Bit mask of PRO_I2S0_INT_MAP field. + DPORT_PRO_I2S0_INT_MAP_PRO_I2S0_INT_MAP_Msk = 0x1f + + // PRO_I2S1_INT_MAP + // Position of PRO_I2S1_INT_MAP field. + DPORT_PRO_I2S1_INT_MAP_PRO_I2S1_INT_MAP_Pos = 0x0 + // Bit mask of PRO_I2S1_INT_MAP field. + DPORT_PRO_I2S1_INT_MAP_PRO_I2S1_INT_MAP_Msk = 0x1f + + // PRO_UART_INTR_MAP + // Position of PRO_UART_INTR_MAP field. + DPORT_PRO_UART_INTR_MAP_PRO_UART_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UART_INTR_MAP field. + DPORT_PRO_UART_INTR_MAP_PRO_UART_INTR_MAP_Msk = 0x1f + + // PRO_UART1_INTR_MAP + // Position of PRO_UART1_INTR_MAP field. + DPORT_PRO_UART1_INTR_MAP_PRO_UART1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UART1_INTR_MAP field. + DPORT_PRO_UART1_INTR_MAP_PRO_UART1_INTR_MAP_Msk = 0x1f + + // PRO_UART2_INTR_MAP + // Position of PRO_UART2_INTR_MAP field. + DPORT_PRO_UART2_INTR_MAP_PRO_UART2_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UART2_INTR_MAP field. + DPORT_PRO_UART2_INTR_MAP_PRO_UART2_INTR_MAP_Msk = 0x1f + + // PRO_SDIO_HOST_INTERRUPT_MAP + // Position of PRO_SDIO_HOST_INTERRUPT_MAP field. + DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_PRO_SDIO_HOST_INTERRUPT_MAP_Pos = 0x0 + // Bit mask of PRO_SDIO_HOST_INTERRUPT_MAP field. + DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_PRO_SDIO_HOST_INTERRUPT_MAP_Msk = 0x1f + + // PRO_EMAC_INT_MAP + // Position of PRO_EMAC_INT_MAP field. + DPORT_PRO_EMAC_INT_MAP_PRO_EMAC_INT_MAP_Pos = 0x0 + // Bit mask of PRO_EMAC_INT_MAP field. + DPORT_PRO_EMAC_INT_MAP_PRO_EMAC_INT_MAP_Msk = 0x1f + + // PRO_PWM0_INTR_MAP + // Position of PRO_PWM0_INTR_MAP field. + DPORT_PRO_PWM0_INTR_MAP_PRO_PWM0_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PWM0_INTR_MAP field. + DPORT_PRO_PWM0_INTR_MAP_PRO_PWM0_INTR_MAP_Msk = 0x1f + + // PRO_PWM1_INTR_MAP + // Position of PRO_PWM1_INTR_MAP field. + DPORT_PRO_PWM1_INTR_MAP_PRO_PWM1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PWM1_INTR_MAP field. + DPORT_PRO_PWM1_INTR_MAP_PRO_PWM1_INTR_MAP_Msk = 0x1f + + // PRO_PWM2_INTR_MAP + // Position of PRO_PWM2_INTR_MAP field. + DPORT_PRO_PWM2_INTR_MAP_PRO_PWM2_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PWM2_INTR_MAP field. + DPORT_PRO_PWM2_INTR_MAP_PRO_PWM2_INTR_MAP_Msk = 0x1f + + // PRO_PWM3_INTR_MAP + // Position of PRO_PWM3_INTR_MAP field. + DPORT_PRO_PWM3_INTR_MAP_PRO_PWM3_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PWM3_INTR_MAP field. + DPORT_PRO_PWM3_INTR_MAP_PRO_PWM3_INTR_MAP_Msk = 0x1f + + // PRO_LEDC_INT_MAP + // Position of PRO_LEDC_INT_MAP field. + DPORT_PRO_LEDC_INT_MAP_PRO_LEDC_INT_MAP_Pos = 0x0 + // Bit mask of PRO_LEDC_INT_MAP field. + DPORT_PRO_LEDC_INT_MAP_PRO_LEDC_INT_MAP_Msk = 0x1f + + // PRO_EFUSE_INT_MAP + // Position of PRO_EFUSE_INT_MAP field. + DPORT_PRO_EFUSE_INT_MAP_PRO_EFUSE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_EFUSE_INT_MAP field. + DPORT_PRO_EFUSE_INT_MAP_PRO_EFUSE_INT_MAP_Msk = 0x1f + + // PRO_CAN_INT_MAP + // Position of PRO_CAN_INT_MAP field. + DPORT_PRO_CAN_INT_MAP_PRO_CAN_INT_MAP_Pos = 0x0 + // Bit mask of PRO_CAN_INT_MAP field. + DPORT_PRO_CAN_INT_MAP_PRO_CAN_INT_MAP_Msk = 0x1f + + // PRO_RTC_CORE_INTR_MAP + // Position of PRO_RTC_CORE_INTR_MAP field. + DPORT_PRO_RTC_CORE_INTR_MAP_PRO_RTC_CORE_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_RTC_CORE_INTR_MAP field. + DPORT_PRO_RTC_CORE_INTR_MAP_PRO_RTC_CORE_INTR_MAP_Msk = 0x1f + + // PRO_RMT_INTR_MAP + // Position of PRO_RMT_INTR_MAP field. + DPORT_PRO_RMT_INTR_MAP_PRO_RMT_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_RMT_INTR_MAP field. + DPORT_PRO_RMT_INTR_MAP_PRO_RMT_INTR_MAP_Msk = 0x1f + + // PRO_PCNT_INTR_MAP + // Position of PRO_PCNT_INTR_MAP field. + DPORT_PRO_PCNT_INTR_MAP_PRO_PCNT_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PCNT_INTR_MAP field. + DPORT_PRO_PCNT_INTR_MAP_PRO_PCNT_INTR_MAP_Msk = 0x1f + + // PRO_I2C_EXT0_INTR_MAP + // Position of PRO_I2C_EXT0_INTR_MAP field. + DPORT_PRO_I2C_EXT0_INTR_MAP_PRO_I2C_EXT0_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_I2C_EXT0_INTR_MAP field. + DPORT_PRO_I2C_EXT0_INTR_MAP_PRO_I2C_EXT0_INTR_MAP_Msk = 0x1f + + // PRO_I2C_EXT1_INTR_MAP + // Position of PRO_I2C_EXT1_INTR_MAP field. + DPORT_PRO_I2C_EXT1_INTR_MAP_PRO_I2C_EXT1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_I2C_EXT1_INTR_MAP field. + DPORT_PRO_I2C_EXT1_INTR_MAP_PRO_I2C_EXT1_INTR_MAP_Msk = 0x1f + + // PRO_RSA_INTR_MAP + // Position of PRO_RSA_INTR_MAP field. + DPORT_PRO_RSA_INTR_MAP_PRO_RSA_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_RSA_INTR_MAP field. + DPORT_PRO_RSA_INTR_MAP_PRO_RSA_INTR_MAP_Msk = 0x1f + + // PRO_SPI1_DMA_INT_MAP + // Position of PRO_SPI1_DMA_INT_MAP field. + DPORT_PRO_SPI1_DMA_INT_MAP_PRO_SPI1_DMA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_SPI1_DMA_INT_MAP field. + DPORT_PRO_SPI1_DMA_INT_MAP_PRO_SPI1_DMA_INT_MAP_Msk = 0x1f + + // PRO_SPI2_DMA_INT_MAP + // Position of PRO_SPI2_DMA_INT_MAP field. + DPORT_PRO_SPI2_DMA_INT_MAP_PRO_SPI2_DMA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_SPI2_DMA_INT_MAP field. + DPORT_PRO_SPI2_DMA_INT_MAP_PRO_SPI2_DMA_INT_MAP_Msk = 0x1f + + // PRO_SPI3_DMA_INT_MAP + // Position of PRO_SPI3_DMA_INT_MAP field. + DPORT_PRO_SPI3_DMA_INT_MAP_PRO_SPI3_DMA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_SPI3_DMA_INT_MAP field. + DPORT_PRO_SPI3_DMA_INT_MAP_PRO_SPI3_DMA_INT_MAP_Msk = 0x1f + + // PRO_WDG_INT_MAP + // Position of PRO_WDG_INT_MAP field. + DPORT_PRO_WDG_INT_MAP_PRO_WDG_INT_MAP_Pos = 0x0 + // Bit mask of PRO_WDG_INT_MAP field. + DPORT_PRO_WDG_INT_MAP_PRO_WDG_INT_MAP_Msk = 0x1f + + // PRO_TIMER_INT1_MAP + // Position of PRO_TIMER_INT1_MAP field. + DPORT_PRO_TIMER_INT1_MAP_PRO_TIMER_INT1_MAP_Pos = 0x0 + // Bit mask of PRO_TIMER_INT1_MAP field. + DPORT_PRO_TIMER_INT1_MAP_PRO_TIMER_INT1_MAP_Msk = 0x1f + + // PRO_TIMER_INT2_MAP + // Position of PRO_TIMER_INT2_MAP field. + DPORT_PRO_TIMER_INT2_MAP_PRO_TIMER_INT2_MAP_Pos = 0x0 + // Bit mask of PRO_TIMER_INT2_MAP field. + DPORT_PRO_TIMER_INT2_MAP_PRO_TIMER_INT2_MAP_Msk = 0x1f + + // PRO_TG_T0_EDGE_INT_MAP + // Position of PRO_TG_T0_EDGE_INT_MAP field. + DPORT_PRO_TG_T0_EDGE_INT_MAP_PRO_TG_T0_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_T0_EDGE_INT_MAP field. + DPORT_PRO_TG_T0_EDGE_INT_MAP_PRO_TG_T0_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG_T1_EDGE_INT_MAP + // Position of PRO_TG_T1_EDGE_INT_MAP field. + DPORT_PRO_TG_T1_EDGE_INT_MAP_PRO_TG_T1_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_T1_EDGE_INT_MAP field. + DPORT_PRO_TG_T1_EDGE_INT_MAP_PRO_TG_T1_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG_WDT_EDGE_INT_MAP + // Position of PRO_TG_WDT_EDGE_INT_MAP field. + DPORT_PRO_TG_WDT_EDGE_INT_MAP_PRO_TG_WDT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_WDT_EDGE_INT_MAP field. + DPORT_PRO_TG_WDT_EDGE_INT_MAP_PRO_TG_WDT_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG_LACT_EDGE_INT_MAP + // Position of PRO_TG_LACT_EDGE_INT_MAP field. + DPORT_PRO_TG_LACT_EDGE_INT_MAP_PRO_TG_LACT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_LACT_EDGE_INT_MAP field. + DPORT_PRO_TG_LACT_EDGE_INT_MAP_PRO_TG_LACT_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG1_T0_EDGE_INT_MAP + // Position of PRO_TG1_T0_EDGE_INT_MAP field. + DPORT_PRO_TG1_T0_EDGE_INT_MAP_PRO_TG1_T0_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_T0_EDGE_INT_MAP field. + DPORT_PRO_TG1_T0_EDGE_INT_MAP_PRO_TG1_T0_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG1_T1_EDGE_INT_MAP + // Position of PRO_TG1_T1_EDGE_INT_MAP field. + DPORT_PRO_TG1_T1_EDGE_INT_MAP_PRO_TG1_T1_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_T1_EDGE_INT_MAP field. + DPORT_PRO_TG1_T1_EDGE_INT_MAP_PRO_TG1_T1_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG1_WDT_EDGE_INT_MAP + // Position of PRO_TG1_WDT_EDGE_INT_MAP field. + DPORT_PRO_TG1_WDT_EDGE_INT_MAP_PRO_TG1_WDT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_WDT_EDGE_INT_MAP field. + DPORT_PRO_TG1_WDT_EDGE_INT_MAP_PRO_TG1_WDT_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG1_LACT_EDGE_INT_MAP + // Position of PRO_TG1_LACT_EDGE_INT_MAP field. + DPORT_PRO_TG1_LACT_EDGE_INT_MAP_PRO_TG1_LACT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_LACT_EDGE_INT_MAP field. + DPORT_PRO_TG1_LACT_EDGE_INT_MAP_PRO_TG1_LACT_EDGE_INT_MAP_Msk = 0x1f + + // PRO_MMU_IA_INT_MAP + // Position of PRO_MMU_IA_INT_MAP field. + DPORT_PRO_MMU_IA_INT_MAP_PRO_MMU_IA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_MMU_IA_INT_MAP field. + DPORT_PRO_MMU_IA_INT_MAP_PRO_MMU_IA_INT_MAP_Msk = 0x1f + + // PRO_MPU_IA_INT_MAP + // Position of PRO_MPU_IA_INT_MAP field. + DPORT_PRO_MPU_IA_INT_MAP_PRO_MPU_IA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_MPU_IA_INT_MAP field. + DPORT_PRO_MPU_IA_INT_MAP_PRO_MPU_IA_INT_MAP_Msk = 0x1f + + // PRO_CACHE_IA_INT_MAP + // Position of PRO_CACHE_IA_INT_MAP field. + DPORT_PRO_CACHE_IA_INT_MAP_PRO_CACHE_IA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_CACHE_IA_INT_MAP field. + DPORT_PRO_CACHE_IA_INT_MAP_PRO_CACHE_IA_INT_MAP_Msk = 0x1f + + // APP_MAC_INTR_MAP + // Position of APP_MAC_INTR_MAP field. + DPORT_APP_MAC_INTR_MAP_APP_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of APP_MAC_INTR_MAP field. + DPORT_APP_MAC_INTR_MAP_APP_MAC_INTR_MAP_Msk = 0x1f + + // APP_MAC_NMI_MAP + // Position of APP_MAC_NMI_MAP field. + DPORT_APP_MAC_NMI_MAP_APP_MAC_NMI_MAP_Pos = 0x0 + // Bit mask of APP_MAC_NMI_MAP field. + DPORT_APP_MAC_NMI_MAP_APP_MAC_NMI_MAP_Msk = 0x1f + + // APP_BB_INT_MAP + // Position of APP_BB_INT_MAP field. + DPORT_APP_BB_INT_MAP_APP_BB_INT_MAP_Pos = 0x0 + // Bit mask of APP_BB_INT_MAP field. + DPORT_APP_BB_INT_MAP_APP_BB_INT_MAP_Msk = 0x1f + + // APP_BT_MAC_INT_MAP + // Position of APP_BT_MAC_INT_MAP field. + DPORT_APP_BT_MAC_INT_MAP_APP_BT_MAC_INT_MAP_Pos = 0x0 + // Bit mask of APP_BT_MAC_INT_MAP field. + DPORT_APP_BT_MAC_INT_MAP_APP_BT_MAC_INT_MAP_Msk = 0x1f + + // APP_BT_BB_INT_MAP + // Position of APP_BT_BB_INT_MAP field. + DPORT_APP_BT_BB_INT_MAP_APP_BT_BB_INT_MAP_Pos = 0x0 + // Bit mask of APP_BT_BB_INT_MAP field. + DPORT_APP_BT_BB_INT_MAP_APP_BT_BB_INT_MAP_Msk = 0x1f + + // APP_BT_BB_NMI_MAP + // Position of APP_BT_BB_NMI_MAP field. + DPORT_APP_BT_BB_NMI_MAP_APP_BT_BB_NMI_MAP_Pos = 0x0 + // Bit mask of APP_BT_BB_NMI_MAP field. + DPORT_APP_BT_BB_NMI_MAP_APP_BT_BB_NMI_MAP_Msk = 0x1f + + // APP_RWBT_IRQ_MAP + // Position of APP_RWBT_IRQ_MAP field. + DPORT_APP_RWBT_IRQ_MAP_APP_RWBT_IRQ_MAP_Pos = 0x0 + // Bit mask of APP_RWBT_IRQ_MAP field. + DPORT_APP_RWBT_IRQ_MAP_APP_RWBT_IRQ_MAP_Msk = 0x1f + + // APP_RWBLE_IRQ_MAP + // Position of APP_RWBLE_IRQ_MAP field. + DPORT_APP_RWBLE_IRQ_MAP_APP_RWBLE_IRQ_MAP_Pos = 0x0 + // Bit mask of APP_RWBLE_IRQ_MAP field. + DPORT_APP_RWBLE_IRQ_MAP_APP_RWBLE_IRQ_MAP_Msk = 0x1f + + // APP_RWBT_NMI_MAP + // Position of APP_RWBT_NMI_MAP field. + DPORT_APP_RWBT_NMI_MAP_APP_RWBT_NMI_MAP_Pos = 0x0 + // Bit mask of APP_RWBT_NMI_MAP field. + DPORT_APP_RWBT_NMI_MAP_APP_RWBT_NMI_MAP_Msk = 0x1f + + // APP_RWBLE_NMI_MAP + // Position of APP_RWBLE_NMI_MAP field. + DPORT_APP_RWBLE_NMI_MAP_APP_RWBLE_NMI_MAP_Pos = 0x0 + // Bit mask of APP_RWBLE_NMI_MAP field. + DPORT_APP_RWBLE_NMI_MAP_APP_RWBLE_NMI_MAP_Msk = 0x1f + + // APP_SLC0_INTR_MAP + // Position of APP_SLC0_INTR_MAP field. + DPORT_APP_SLC0_INTR_MAP_APP_SLC0_INTR_MAP_Pos = 0x0 + // Bit mask of APP_SLC0_INTR_MAP field. + DPORT_APP_SLC0_INTR_MAP_APP_SLC0_INTR_MAP_Msk = 0x1f + + // APP_SLC1_INTR_MAP + // Position of APP_SLC1_INTR_MAP field. + DPORT_APP_SLC1_INTR_MAP_APP_SLC1_INTR_MAP_Pos = 0x0 + // Bit mask of APP_SLC1_INTR_MAP field. + DPORT_APP_SLC1_INTR_MAP_APP_SLC1_INTR_MAP_Msk = 0x1f + + // APP_UHCI0_INTR_MAP + // Position of APP_UHCI0_INTR_MAP field. + DPORT_APP_UHCI0_INTR_MAP_APP_UHCI0_INTR_MAP_Pos = 0x0 + // Bit mask of APP_UHCI0_INTR_MAP field. + DPORT_APP_UHCI0_INTR_MAP_APP_UHCI0_INTR_MAP_Msk = 0x1f + + // APP_UHCI1_INTR_MAP + // Position of APP_UHCI1_INTR_MAP field. + DPORT_APP_UHCI1_INTR_MAP_APP_UHCI1_INTR_MAP_Pos = 0x0 + // Bit mask of APP_UHCI1_INTR_MAP field. + DPORT_APP_UHCI1_INTR_MAP_APP_UHCI1_INTR_MAP_Msk = 0x1f + + // APP_TG_T0_LEVEL_INT_MAP + // Position of APP_TG_T0_LEVEL_INT_MAP field. + DPORT_APP_TG_T0_LEVEL_INT_MAP_APP_TG_T0_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG_T0_LEVEL_INT_MAP field. + DPORT_APP_TG_T0_LEVEL_INT_MAP_APP_TG_T0_LEVEL_INT_MAP_Msk = 0x1f + + // APP_TG_T1_LEVEL_INT_MAP + // Position of APP_TG_T1_LEVEL_INT_MAP field. + DPORT_APP_TG_T1_LEVEL_INT_MAP_APP_TG_T1_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG_T1_LEVEL_INT_MAP field. + DPORT_APP_TG_T1_LEVEL_INT_MAP_APP_TG_T1_LEVEL_INT_MAP_Msk = 0x1f + + // APP_TG_WDT_LEVEL_INT_MAP + // Position of APP_TG_WDT_LEVEL_INT_MAP field. + DPORT_APP_TG_WDT_LEVEL_INT_MAP_APP_TG_WDT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG_WDT_LEVEL_INT_MAP field. + DPORT_APP_TG_WDT_LEVEL_INT_MAP_APP_TG_WDT_LEVEL_INT_MAP_Msk = 0x1f + + // APP_TG_LACT_LEVEL_INT_MAP + // Position of APP_TG_LACT_LEVEL_INT_MAP field. + DPORT_APP_TG_LACT_LEVEL_INT_MAP_APP_TG_LACT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG_LACT_LEVEL_INT_MAP field. + DPORT_APP_TG_LACT_LEVEL_INT_MAP_APP_TG_LACT_LEVEL_INT_MAP_Msk = 0x1f + + // APP_TG1_T0_LEVEL_INT_MAP + // Position of APP_TG1_T0_LEVEL_INT_MAP field. + DPORT_APP_TG1_T0_LEVEL_INT_MAP_APP_TG1_T0_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG1_T0_LEVEL_INT_MAP field. + DPORT_APP_TG1_T0_LEVEL_INT_MAP_APP_TG1_T0_LEVEL_INT_MAP_Msk = 0x1f + + // APP_TG1_T1_LEVEL_INT_MAP + // Position of APP_TG1_T1_LEVEL_INT_MAP field. + DPORT_APP_TG1_T1_LEVEL_INT_MAP_APP_TG1_T1_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG1_T1_LEVEL_INT_MAP field. + DPORT_APP_TG1_T1_LEVEL_INT_MAP_APP_TG1_T1_LEVEL_INT_MAP_Msk = 0x1f + + // APP_TG1_WDT_LEVEL_INT_MAP + // Position of APP_TG1_WDT_LEVEL_INT_MAP field. + DPORT_APP_TG1_WDT_LEVEL_INT_MAP_APP_TG1_WDT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG1_WDT_LEVEL_INT_MAP field. + DPORT_APP_TG1_WDT_LEVEL_INT_MAP_APP_TG1_WDT_LEVEL_INT_MAP_Msk = 0x1f + + // APP_TG1_LACT_LEVEL_INT_MAP + // Position of APP_TG1_LACT_LEVEL_INT_MAP field. + DPORT_APP_TG1_LACT_LEVEL_INT_MAP_APP_TG1_LACT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG1_LACT_LEVEL_INT_MAP field. + DPORT_APP_TG1_LACT_LEVEL_INT_MAP_APP_TG1_LACT_LEVEL_INT_MAP_Msk = 0x1f + + // APP_GPIO_INTERRUPT_MAP + // Position of APP_GPIO_INTERRUPT_APP_MAP field. + DPORT_APP_GPIO_INTERRUPT_MAP_APP_GPIO_INTERRUPT_APP_MAP_Pos = 0x0 + // Bit mask of APP_GPIO_INTERRUPT_APP_MAP field. + DPORT_APP_GPIO_INTERRUPT_MAP_APP_GPIO_INTERRUPT_APP_MAP_Msk = 0x1f + + // APP_GPIO_INTERRUPT_NMI_MAP + // Position of APP_GPIO_INTERRUPT_APP_NMI_MAP field. + DPORT_APP_GPIO_INTERRUPT_NMI_MAP_APP_GPIO_INTERRUPT_APP_NMI_MAP_Pos = 0x0 + // Bit mask of APP_GPIO_INTERRUPT_APP_NMI_MAP field. + DPORT_APP_GPIO_INTERRUPT_NMI_MAP_APP_GPIO_INTERRUPT_APP_NMI_MAP_Msk = 0x1f + + // APP_CPU_INTR_FROM_CPU_0_MAP + // Position of APP_CPU_INTR_FROM_CPU_0_MAP field. + DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_APP_CPU_INTR_FROM_CPU_0_MAP_Pos = 0x0 + // Bit mask of APP_CPU_INTR_FROM_CPU_0_MAP field. + DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_APP_CPU_INTR_FROM_CPU_0_MAP_Msk = 0x1f + + // APP_CPU_INTR_FROM_CPU_1_MAP + // Position of APP_CPU_INTR_FROM_CPU_1_MAP field. + DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_APP_CPU_INTR_FROM_CPU_1_MAP_Pos = 0x0 + // Bit mask of APP_CPU_INTR_FROM_CPU_1_MAP field. + DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_APP_CPU_INTR_FROM_CPU_1_MAP_Msk = 0x1f + + // APP_CPU_INTR_FROM_CPU_2_MAP + // Position of APP_CPU_INTR_FROM_CPU_2_MAP field. + DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_APP_CPU_INTR_FROM_CPU_2_MAP_Pos = 0x0 + // Bit mask of APP_CPU_INTR_FROM_CPU_2_MAP field. + DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_APP_CPU_INTR_FROM_CPU_2_MAP_Msk = 0x1f + + // APP_CPU_INTR_FROM_CPU_3_MAP + // Position of APP_CPU_INTR_FROM_CPU_3_MAP field. + DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_APP_CPU_INTR_FROM_CPU_3_MAP_Pos = 0x0 + // Bit mask of APP_CPU_INTR_FROM_CPU_3_MAP field. + DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_APP_CPU_INTR_FROM_CPU_3_MAP_Msk = 0x1f + + // APP_SPI_INTR_0_MAP + // Position of APP_SPI_INTR_0_MAP field. + DPORT_APP_SPI_INTR_0_MAP_APP_SPI_INTR_0_MAP_Pos = 0x0 + // Bit mask of APP_SPI_INTR_0_MAP field. + DPORT_APP_SPI_INTR_0_MAP_APP_SPI_INTR_0_MAP_Msk = 0x1f + + // APP_SPI_INTR_1_MAP + // Position of APP_SPI_INTR_1_MAP field. + DPORT_APP_SPI_INTR_1_MAP_APP_SPI_INTR_1_MAP_Pos = 0x0 + // Bit mask of APP_SPI_INTR_1_MAP field. + DPORT_APP_SPI_INTR_1_MAP_APP_SPI_INTR_1_MAP_Msk = 0x1f + + // APP_SPI_INTR_2_MAP + // Position of APP_SPI_INTR_2_MAP field. + DPORT_APP_SPI_INTR_2_MAP_APP_SPI_INTR_2_MAP_Pos = 0x0 + // Bit mask of APP_SPI_INTR_2_MAP field. + DPORT_APP_SPI_INTR_2_MAP_APP_SPI_INTR_2_MAP_Msk = 0x1f + + // APP_SPI_INTR_3_MAP + // Position of APP_SPI_INTR_3_MAP field. + DPORT_APP_SPI_INTR_3_MAP_APP_SPI_INTR_3_MAP_Pos = 0x0 + // Bit mask of APP_SPI_INTR_3_MAP field. + DPORT_APP_SPI_INTR_3_MAP_APP_SPI_INTR_3_MAP_Msk = 0x1f + + // APP_I2S0_INT_MAP + // Position of APP_I2S0_INT_MAP field. + DPORT_APP_I2S0_INT_MAP_APP_I2S0_INT_MAP_Pos = 0x0 + // Bit mask of APP_I2S0_INT_MAP field. + DPORT_APP_I2S0_INT_MAP_APP_I2S0_INT_MAP_Msk = 0x1f + + // APP_I2S1_INT_MAP + // Position of APP_I2S1_INT_MAP field. + DPORT_APP_I2S1_INT_MAP_APP_I2S1_INT_MAP_Pos = 0x0 + // Bit mask of APP_I2S1_INT_MAP field. + DPORT_APP_I2S1_INT_MAP_APP_I2S1_INT_MAP_Msk = 0x1f + + // APP_UART_INTR_MAP + // Position of APP_UART_INTR_MAP field. + DPORT_APP_UART_INTR_MAP_APP_UART_INTR_MAP_Pos = 0x0 + // Bit mask of APP_UART_INTR_MAP field. + DPORT_APP_UART_INTR_MAP_APP_UART_INTR_MAP_Msk = 0x1f + + // APP_UART1_INTR_MAP + // Position of APP_UART1_INTR_MAP field. + DPORT_APP_UART1_INTR_MAP_APP_UART1_INTR_MAP_Pos = 0x0 + // Bit mask of APP_UART1_INTR_MAP field. + DPORT_APP_UART1_INTR_MAP_APP_UART1_INTR_MAP_Msk = 0x1f + + // APP_UART2_INTR_MAP + // Position of APP_UART2_INTR_MAP field. + DPORT_APP_UART2_INTR_MAP_APP_UART2_INTR_MAP_Pos = 0x0 + // Bit mask of APP_UART2_INTR_MAP field. + DPORT_APP_UART2_INTR_MAP_APP_UART2_INTR_MAP_Msk = 0x1f + + // APP_SDIO_HOST_INTERRUPT_MAP + // Position of APP_SDIO_HOST_INTERRUPT_MAP field. + DPORT_APP_SDIO_HOST_INTERRUPT_MAP_APP_SDIO_HOST_INTERRUPT_MAP_Pos = 0x0 + // Bit mask of APP_SDIO_HOST_INTERRUPT_MAP field. + DPORT_APP_SDIO_HOST_INTERRUPT_MAP_APP_SDIO_HOST_INTERRUPT_MAP_Msk = 0x1f + + // APP_EMAC_INT_MAP + // Position of APP_EMAC_INT_MAP field. + DPORT_APP_EMAC_INT_MAP_APP_EMAC_INT_MAP_Pos = 0x0 + // Bit mask of APP_EMAC_INT_MAP field. + DPORT_APP_EMAC_INT_MAP_APP_EMAC_INT_MAP_Msk = 0x1f + + // APP_PWM0_INTR_MAP + // Position of APP_PWM0_INTR_MAP field. + DPORT_APP_PWM0_INTR_MAP_APP_PWM0_INTR_MAP_Pos = 0x0 + // Bit mask of APP_PWM0_INTR_MAP field. + DPORT_APP_PWM0_INTR_MAP_APP_PWM0_INTR_MAP_Msk = 0x1f + + // APP_PWM1_INTR_MAP + // Position of APP_PWM1_INTR_MAP field. + DPORT_APP_PWM1_INTR_MAP_APP_PWM1_INTR_MAP_Pos = 0x0 + // Bit mask of APP_PWM1_INTR_MAP field. + DPORT_APP_PWM1_INTR_MAP_APP_PWM1_INTR_MAP_Msk = 0x1f + + // APP_PWM2_INTR_MAP + // Position of APP_PWM2_INTR_MAP field. + DPORT_APP_PWM2_INTR_MAP_APP_PWM2_INTR_MAP_Pos = 0x0 + // Bit mask of APP_PWM2_INTR_MAP field. + DPORT_APP_PWM2_INTR_MAP_APP_PWM2_INTR_MAP_Msk = 0x1f + + // APP_PWM3_INTR_MAP + // Position of APP_PWM3_INTR_MAP field. + DPORT_APP_PWM3_INTR_MAP_APP_PWM3_INTR_MAP_Pos = 0x0 + // Bit mask of APP_PWM3_INTR_MAP field. + DPORT_APP_PWM3_INTR_MAP_APP_PWM3_INTR_MAP_Msk = 0x1f + + // APP_LEDC_INT_MAP + // Position of APP_LEDC_INT_MAP field. + DPORT_APP_LEDC_INT_MAP_APP_LEDC_INT_MAP_Pos = 0x0 + // Bit mask of APP_LEDC_INT_MAP field. + DPORT_APP_LEDC_INT_MAP_APP_LEDC_INT_MAP_Msk = 0x1f + + // APP_EFUSE_INT_MAP + // Position of APP_EFUSE_INT_MAP field. + DPORT_APP_EFUSE_INT_MAP_APP_EFUSE_INT_MAP_Pos = 0x0 + // Bit mask of APP_EFUSE_INT_MAP field. + DPORT_APP_EFUSE_INT_MAP_APP_EFUSE_INT_MAP_Msk = 0x1f + + // APP_CAN_INT_MAP + // Position of APP_CAN_INT_MAP field. + DPORT_APP_CAN_INT_MAP_APP_CAN_INT_MAP_Pos = 0x0 + // Bit mask of APP_CAN_INT_MAP field. + DPORT_APP_CAN_INT_MAP_APP_CAN_INT_MAP_Msk = 0x1f + + // APP_RTC_CORE_INTR_MAP + // Position of APP_RTC_CORE_INTR_MAP field. + DPORT_APP_RTC_CORE_INTR_MAP_APP_RTC_CORE_INTR_MAP_Pos = 0x0 + // Bit mask of APP_RTC_CORE_INTR_MAP field. + DPORT_APP_RTC_CORE_INTR_MAP_APP_RTC_CORE_INTR_MAP_Msk = 0x1f + + // APP_RMT_INTR_MAP + // Position of APP_RMT_INTR_MAP field. + DPORT_APP_RMT_INTR_MAP_APP_RMT_INTR_MAP_Pos = 0x0 + // Bit mask of APP_RMT_INTR_MAP field. + DPORT_APP_RMT_INTR_MAP_APP_RMT_INTR_MAP_Msk = 0x1f + + // APP_PCNT_INTR_MAP + // Position of APP_PCNT_INTR_MAP field. + DPORT_APP_PCNT_INTR_MAP_APP_PCNT_INTR_MAP_Pos = 0x0 + // Bit mask of APP_PCNT_INTR_MAP field. + DPORT_APP_PCNT_INTR_MAP_APP_PCNT_INTR_MAP_Msk = 0x1f + + // APP_I2C_EXT0_INTR_MAP + // Position of APP_I2C_EXT0_INTR_MAP field. + DPORT_APP_I2C_EXT0_INTR_MAP_APP_I2C_EXT0_INTR_MAP_Pos = 0x0 + // Bit mask of APP_I2C_EXT0_INTR_MAP field. + DPORT_APP_I2C_EXT0_INTR_MAP_APP_I2C_EXT0_INTR_MAP_Msk = 0x1f + + // APP_I2C_EXT1_INTR_MAP + // Position of APP_I2C_EXT1_INTR_MAP field. + DPORT_APP_I2C_EXT1_INTR_MAP_APP_I2C_EXT1_INTR_MAP_Pos = 0x0 + // Bit mask of APP_I2C_EXT1_INTR_MAP field. + DPORT_APP_I2C_EXT1_INTR_MAP_APP_I2C_EXT1_INTR_MAP_Msk = 0x1f + + // APP_RSA_INTR_MAP + // Position of APP_RSA_INTR_MAP field. + DPORT_APP_RSA_INTR_MAP_APP_RSA_INTR_MAP_Pos = 0x0 + // Bit mask of APP_RSA_INTR_MAP field. + DPORT_APP_RSA_INTR_MAP_APP_RSA_INTR_MAP_Msk = 0x1f + + // APP_SPI1_DMA_INT_MAP + // Position of APP_SPI1_DMA_INT_MAP field. + DPORT_APP_SPI1_DMA_INT_MAP_APP_SPI1_DMA_INT_MAP_Pos = 0x0 + // Bit mask of APP_SPI1_DMA_INT_MAP field. + DPORT_APP_SPI1_DMA_INT_MAP_APP_SPI1_DMA_INT_MAP_Msk = 0x1f + + // APP_SPI2_DMA_INT_MAP + // Position of APP_SPI2_DMA_INT_MAP field. + DPORT_APP_SPI2_DMA_INT_MAP_APP_SPI2_DMA_INT_MAP_Pos = 0x0 + // Bit mask of APP_SPI2_DMA_INT_MAP field. + DPORT_APP_SPI2_DMA_INT_MAP_APP_SPI2_DMA_INT_MAP_Msk = 0x1f + + // APP_SPI3_DMA_INT_MAP + // Position of APP_SPI3_DMA_INT_MAP field. + DPORT_APP_SPI3_DMA_INT_MAP_APP_SPI3_DMA_INT_MAP_Pos = 0x0 + // Bit mask of APP_SPI3_DMA_INT_MAP field. + DPORT_APP_SPI3_DMA_INT_MAP_APP_SPI3_DMA_INT_MAP_Msk = 0x1f + + // APP_WDG_INT_MAP + // Position of APP_WDG_INT_MAP field. + DPORT_APP_WDG_INT_MAP_APP_WDG_INT_MAP_Pos = 0x0 + // Bit mask of APP_WDG_INT_MAP field. + DPORT_APP_WDG_INT_MAP_APP_WDG_INT_MAP_Msk = 0x1f + + // APP_TIMER_INT1_MAP + // Position of APP_TIMER_INT1_MAP field. + DPORT_APP_TIMER_INT1_MAP_APP_TIMER_INT1_MAP_Pos = 0x0 + // Bit mask of APP_TIMER_INT1_MAP field. + DPORT_APP_TIMER_INT1_MAP_APP_TIMER_INT1_MAP_Msk = 0x1f + + // APP_TIMER_INT2_MAP + // Position of APP_TIMER_INT2_MAP field. + DPORT_APP_TIMER_INT2_MAP_APP_TIMER_INT2_MAP_Pos = 0x0 + // Bit mask of APP_TIMER_INT2_MAP field. + DPORT_APP_TIMER_INT2_MAP_APP_TIMER_INT2_MAP_Msk = 0x1f + + // APP_TG_T0_EDGE_INT_MAP + // Position of APP_TG_T0_EDGE_INT_MAP field. + DPORT_APP_TG_T0_EDGE_INT_MAP_APP_TG_T0_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG_T0_EDGE_INT_MAP field. + DPORT_APP_TG_T0_EDGE_INT_MAP_APP_TG_T0_EDGE_INT_MAP_Msk = 0x1f + + // APP_TG_T1_EDGE_INT_MAP + // Position of APP_TG_T1_EDGE_INT_MAP field. + DPORT_APP_TG_T1_EDGE_INT_MAP_APP_TG_T1_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG_T1_EDGE_INT_MAP field. + DPORT_APP_TG_T1_EDGE_INT_MAP_APP_TG_T1_EDGE_INT_MAP_Msk = 0x1f + + // APP_TG_WDT_EDGE_INT_MAP + // Position of APP_TG_WDT_EDGE_INT_MAP field. + DPORT_APP_TG_WDT_EDGE_INT_MAP_APP_TG_WDT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG_WDT_EDGE_INT_MAP field. + DPORT_APP_TG_WDT_EDGE_INT_MAP_APP_TG_WDT_EDGE_INT_MAP_Msk = 0x1f + + // APP_TG_LACT_EDGE_INT_MAP + // Position of APP_TG_LACT_EDGE_INT_MAP field. + DPORT_APP_TG_LACT_EDGE_INT_MAP_APP_TG_LACT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG_LACT_EDGE_INT_MAP field. + DPORT_APP_TG_LACT_EDGE_INT_MAP_APP_TG_LACT_EDGE_INT_MAP_Msk = 0x1f + + // APP_TG1_T0_EDGE_INT_MAP + // Position of APP_TG1_T0_EDGE_INT_MAP field. + DPORT_APP_TG1_T0_EDGE_INT_MAP_APP_TG1_T0_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG1_T0_EDGE_INT_MAP field. + DPORT_APP_TG1_T0_EDGE_INT_MAP_APP_TG1_T0_EDGE_INT_MAP_Msk = 0x1f + + // APP_TG1_T1_EDGE_INT_MAP + // Position of APP_TG1_T1_EDGE_INT_MAP field. + DPORT_APP_TG1_T1_EDGE_INT_MAP_APP_TG1_T1_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG1_T1_EDGE_INT_MAP field. + DPORT_APP_TG1_T1_EDGE_INT_MAP_APP_TG1_T1_EDGE_INT_MAP_Msk = 0x1f + + // APP_TG1_WDT_EDGE_INT_MAP + // Position of APP_TG1_WDT_EDGE_INT_MAP field. + DPORT_APP_TG1_WDT_EDGE_INT_MAP_APP_TG1_WDT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG1_WDT_EDGE_INT_MAP field. + DPORT_APP_TG1_WDT_EDGE_INT_MAP_APP_TG1_WDT_EDGE_INT_MAP_Msk = 0x1f + + // APP_TG1_LACT_EDGE_INT_MAP + // Position of APP_TG1_LACT_EDGE_INT_MAP field. + DPORT_APP_TG1_LACT_EDGE_INT_MAP_APP_TG1_LACT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of APP_TG1_LACT_EDGE_INT_MAP field. + DPORT_APP_TG1_LACT_EDGE_INT_MAP_APP_TG1_LACT_EDGE_INT_MAP_Msk = 0x1f + + // APP_MMU_IA_INT_MAP + // Position of APP_MMU_IA_INT_MAP field. + DPORT_APP_MMU_IA_INT_MAP_APP_MMU_IA_INT_MAP_Pos = 0x0 + // Bit mask of APP_MMU_IA_INT_MAP field. + DPORT_APP_MMU_IA_INT_MAP_APP_MMU_IA_INT_MAP_Msk = 0x1f + + // APP_MPU_IA_INT_MAP + // Position of APP_MPU_IA_INT_MAP field. + DPORT_APP_MPU_IA_INT_MAP_APP_MPU_IA_INT_MAP_Pos = 0x0 + // Bit mask of APP_MPU_IA_INT_MAP field. + DPORT_APP_MPU_IA_INT_MAP_APP_MPU_IA_INT_MAP_Msk = 0x1f + + // APP_CACHE_IA_INT_MAP + // Position of APP_CACHE_IA_INT_MAP field. + DPORT_APP_CACHE_IA_INT_MAP_APP_CACHE_IA_INT_MAP_Pos = 0x0 + // Bit mask of APP_CACHE_IA_INT_MAP field. + DPORT_APP_CACHE_IA_INT_MAP_APP_CACHE_IA_INT_MAP_Msk = 0x1f + + // AHBLITE_MPU_TABLE_UART + // Position of UART_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UART_UART_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of UART_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UART_UART_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_SPI1 + // Position of SPI1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI1_SPI1_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of SPI1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI1_SPI1_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_SPI0 + // Position of SPI0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI0_SPI0_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of SPI0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI0_SPI0_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_GPIO + // Position of GPIO_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_GPIO_GPIO_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of GPIO_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_GPIO_GPIO_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_FE2 + // Position of FE2_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_FE2_FE2_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of FE2_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_FE2_FE2_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_FE + // Position of FE_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_FE_FE_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of FE_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_FE_FE_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_TIMER + // Position of TIMER_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_TIMER_TIMER_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of TIMER_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_TIMER_TIMER_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_RTC + // Position of RTC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_RTC_RTC_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of RTC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_RTC_RTC_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_IO_MUX + // Position of IOMUX_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_IO_MUX_IOMUX_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of IOMUX_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_IO_MUX_IOMUX_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_WDG + // Position of WDG_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_WDG_WDG_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of WDG_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_WDG_WDG_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_HINF + // Position of HINF_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_HINF_HINF_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of HINF_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_HINF_HINF_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_UHCI1 + // Position of UHCI1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UHCI1_UHCI1_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of UHCI1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UHCI1_UHCI1_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_MISC + // Position of MISC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_MISC_MISC_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of MISC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_MISC_MISC_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_I2C + // Position of I2C_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2C_I2C_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of I2C_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2C_I2C_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_I2S0 + // Position of I2S0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2S0_I2S0_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of I2S0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2S0_I2S0_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_UART1 + // Position of UART1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UART1_UART1_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of UART1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UART1_UART1_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_BT + // Position of BT_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_BT_BT_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of BT_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_BT_BT_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_BT_BUFFER + // Position of BTBUFFER_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_BTBUFFER_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of BTBUFFER_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_BTBUFFER_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_I2C_EXT0 + // Position of I2CEXT0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_I2CEXT0_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of I2CEXT0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_I2CEXT0_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_UHCI0 + // Position of UHCI0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UHCI0_UHCI0_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of UHCI0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UHCI0_UHCI0_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_SLCHOST + // Position of SLCHOST_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SLCHOST_SLCHOST_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of SLCHOST_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SLCHOST_SLCHOST_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_RMT + // Position of RMT_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_RMT_RMT_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of RMT_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_RMT_RMT_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_PCNT + // Position of PCNT_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PCNT_PCNT_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of PCNT_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PCNT_PCNT_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_SLC + // Position of SLC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SLC_SLC_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of SLC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SLC_SLC_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_LEDC + // Position of LEDC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_LEDC_LEDC_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of LEDC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_LEDC_LEDC_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_EFUSE + // Position of EFUSE_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_EFUSE_EFUSE_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of EFUSE_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_EFUSE_EFUSE_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_SPI_ENCRYPT + // Position of SPI_ENCRYPY_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of SPI_ENCRYPY_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_BB + // Position of BB_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_BB_BB_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of BB_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_BB_BB_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_PWM0 + // Position of PWM0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWM0_PWM0_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of PWM0_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWM0_PWM0_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_TIMERGROUP + // Position of TIMERGROUP_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_TIMERGROUP_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of TIMERGROUP_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_TIMERGROUP_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_TIMERGROUP1 + // Position of TIMERGROUP1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_TIMERGROUP1_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of TIMERGROUP1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_TIMERGROUP1_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_SPI2 + // Position of SPI2_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI2_SPI2_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of SPI2_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI2_SPI2_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_SPI3 + // Position of SPI3_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI3_SPI3_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of SPI3_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SPI3_SPI3_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_APB_CTRL + // Position of APBCTRL_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_APB_CTRL_APBCTRL_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of APBCTRL_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_APB_CTRL_APBCTRL_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_I2C_EXT1 + // Position of I2CEXT1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_I2CEXT1_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of I2CEXT1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_I2CEXT1_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_SDIO_HOST + // Position of SDIOHOST_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_SDIOHOST_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of SDIOHOST_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_SDIOHOST_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_EMAC + // Position of EMAC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_EMAC_EMAC_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of EMAC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_EMAC_EMAC_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_CAN + // Position of CAN_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_CAN_CAN_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of CAN_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_CAN_CAN_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_PWM1 + // Position of PWM1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWM1_PWM1_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of PWM1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWM1_PWM1_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_I2S1 + // Position of I2S1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2S1_I2S1_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of I2S1_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_I2S1_I2S1_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_UART2 + // Position of UART2_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UART2_UART2_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of UART2_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_UART2_UART2_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_PWM2 + // Position of PWM2_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWM2_PWM2_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of PWM2_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWM2_PWM2_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_PWM3 + // Position of PWM3_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWM3_PWM3_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of PWM3_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWM3_PWM3_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_RWBT + // Position of RWBT_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_RWBT_RWBT_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of RWBT_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_RWBT_RWBT_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_BTMAC + // Position of BTMAC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_BTMAC_BTMAC_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of BTMAC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_BTMAC_BTMAC_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_WIFIMAC + // Position of WIFIMAC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_WIFIMAC_WIFIMAC_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of WIFIMAC_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_WIFIMAC_WIFIMAC_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // AHBLITE_MPU_TABLE_PWR + // Position of PWR_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWR_PWR_ACCESS_GRANT_CONFIG_Pos = 0x0 + // Bit mask of PWR_ACCESS_GRANT_CONFIG field. + DPORT_AHBLITE_MPU_TABLE_PWR_PWR_ACCESS_GRANT_CONFIG_Msk = 0x3f + + // MEM_ACCESS_DBUG0 + // Position of PRO_ROM_MPU_AD field. + DPORT_MEM_ACCESS_DBUG0_PRO_ROM_MPU_AD_Pos = 0x0 + // Bit mask of PRO_ROM_MPU_AD field. + DPORT_MEM_ACCESS_DBUG0_PRO_ROM_MPU_AD_Msk = 0x1 + // Bit PRO_ROM_MPU_AD. + DPORT_MEM_ACCESS_DBUG0_PRO_ROM_MPU_AD = 0x1 + // Position of PRO_ROM_IA field. + DPORT_MEM_ACCESS_DBUG0_PRO_ROM_IA_Pos = 0x1 + // Bit mask of PRO_ROM_IA field. + DPORT_MEM_ACCESS_DBUG0_PRO_ROM_IA_Msk = 0x2 + // Bit PRO_ROM_IA. + DPORT_MEM_ACCESS_DBUG0_PRO_ROM_IA = 0x2 + // Position of APP_ROM_MPU_AD field. + DPORT_MEM_ACCESS_DBUG0_APP_ROM_MPU_AD_Pos = 0x2 + // Bit mask of APP_ROM_MPU_AD field. + DPORT_MEM_ACCESS_DBUG0_APP_ROM_MPU_AD_Msk = 0x4 + // Bit APP_ROM_MPU_AD. + DPORT_MEM_ACCESS_DBUG0_APP_ROM_MPU_AD = 0x4 + // Position of APP_ROM_IA field. + DPORT_MEM_ACCESS_DBUG0_APP_ROM_IA_Pos = 0x3 + // Bit mask of APP_ROM_IA field. + DPORT_MEM_ACCESS_DBUG0_APP_ROM_IA_Msk = 0x8 + // Bit APP_ROM_IA. + DPORT_MEM_ACCESS_DBUG0_APP_ROM_IA = 0x8 + // Position of SHARE_ROM_MPU_AD field. + DPORT_MEM_ACCESS_DBUG0_SHARE_ROM_MPU_AD_Pos = 0x4 + // Bit mask of SHARE_ROM_MPU_AD field. + DPORT_MEM_ACCESS_DBUG0_SHARE_ROM_MPU_AD_Msk = 0x30 + // Position of SHARE_ROM_IA field. + DPORT_MEM_ACCESS_DBUG0_SHARE_ROM_IA_Pos = 0x6 + // Bit mask of SHARE_ROM_IA field. + DPORT_MEM_ACCESS_DBUG0_SHARE_ROM_IA_Msk = 0x3c0 + // Position of INTERNAL_SRAM_MMU_AD field. + DPORT_MEM_ACCESS_DBUG0_INTERNAL_SRAM_MMU_AD_Pos = 0xa + // Bit mask of INTERNAL_SRAM_MMU_AD field. + DPORT_MEM_ACCESS_DBUG0_INTERNAL_SRAM_MMU_AD_Msk = 0x3c00 + // Position of INTERNAL_SRAM_IA field. + DPORT_MEM_ACCESS_DBUG0_INTERNAL_SRAM_IA_Pos = 0xe + // Bit mask of INTERNAL_SRAM_IA field. + DPORT_MEM_ACCESS_DBUG0_INTERNAL_SRAM_IA_Msk = 0x3ffc000 + // Position of INTERNAL_SRAM_MMU_MULTI_HIT field. + DPORT_MEM_ACCESS_DBUG0_INTERNAL_SRAM_MMU_MULTI_HIT_Pos = 0x1a + // Bit mask of INTERNAL_SRAM_MMU_MULTI_HIT field. + DPORT_MEM_ACCESS_DBUG0_INTERNAL_SRAM_MMU_MULTI_HIT_Msk = 0x3c000000 + + // MEM_ACCESS_DBUG1 + // Position of INTERNAL_SRAM_MMU_MISS field. + DPORT_MEM_ACCESS_DBUG1_INTERNAL_SRAM_MMU_MISS_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_MMU_MISS field. + DPORT_MEM_ACCESS_DBUG1_INTERNAL_SRAM_MMU_MISS_Msk = 0xf + // Position of ARB_IA field. + DPORT_MEM_ACCESS_DBUG1_ARB_IA_Pos = 0x4 + // Bit mask of ARB_IA field. + DPORT_MEM_ACCESS_DBUG1_ARB_IA_Msk = 0x30 + // Position of PIDGEN_IA field. + DPORT_MEM_ACCESS_DBUG1_PIDGEN_IA_Pos = 0x6 + // Bit mask of PIDGEN_IA field. + DPORT_MEM_ACCESS_DBUG1_PIDGEN_IA_Msk = 0xc0 + // Position of AHB_ACCESS_DENY field. + DPORT_MEM_ACCESS_DBUG1_AHB_ACCESS_DENY_Pos = 0x8 + // Bit mask of AHB_ACCESS_DENY field. + DPORT_MEM_ACCESS_DBUG1_AHB_ACCESS_DENY_Msk = 0x100 + // Bit AHB_ACCESS_DENY. + DPORT_MEM_ACCESS_DBUG1_AHB_ACCESS_DENY = 0x100 + // Position of AHBLITE_ACCESS_DENY field. + DPORT_MEM_ACCESS_DBUG1_AHBLITE_ACCESS_DENY_Pos = 0x9 + // Bit mask of AHBLITE_ACCESS_DENY field. + DPORT_MEM_ACCESS_DBUG1_AHBLITE_ACCESS_DENY_Msk = 0x200 + // Bit AHBLITE_ACCESS_DENY. + DPORT_MEM_ACCESS_DBUG1_AHBLITE_ACCESS_DENY = 0x200 + // Position of AHBLITE_IA field. + DPORT_MEM_ACCESS_DBUG1_AHBLITE_IA_Pos = 0xa + // Bit mask of AHBLITE_IA field. + DPORT_MEM_ACCESS_DBUG1_AHBLITE_IA_Msk = 0x400 + // Bit AHBLITE_IA. + DPORT_MEM_ACCESS_DBUG1_AHBLITE_IA = 0x400 + + // PRO_DCACHE_DBUG0 + // Position of PRO_SLAVE_WDATA field. + DPORT_PRO_DCACHE_DBUG0_PRO_SLAVE_WDATA_Pos = 0x0 + // Bit mask of PRO_SLAVE_WDATA field. + DPORT_PRO_DCACHE_DBUG0_PRO_SLAVE_WDATA_Msk = 0x1 + // Bit PRO_SLAVE_WDATA. + DPORT_PRO_DCACHE_DBUG0_PRO_SLAVE_WDATA = 0x1 + // Position of PRO_CACHE_MMU_IA field. + DPORT_PRO_DCACHE_DBUG0_PRO_CACHE_MMU_IA_Pos = 0x0 + // Bit mask of PRO_CACHE_MMU_IA field. + DPORT_PRO_DCACHE_DBUG0_PRO_CACHE_MMU_IA_Msk = 0x1 + // Bit PRO_CACHE_MMU_IA. + DPORT_PRO_DCACHE_DBUG0_PRO_CACHE_MMU_IA = 0x1 + // Position of PRO_CACHE_IA field. + DPORT_PRO_DCACHE_DBUG0_PRO_CACHE_IA_Pos = 0x1 + // Bit mask of PRO_CACHE_IA field. + DPORT_PRO_DCACHE_DBUG0_PRO_CACHE_IA_Msk = 0x7e + // Position of PRO_CACHE_STATE field. + DPORT_PRO_DCACHE_DBUG0_PRO_CACHE_STATE_Pos = 0x7 + // Bit mask of PRO_CACHE_STATE field. + DPORT_PRO_DCACHE_DBUG0_PRO_CACHE_STATE_Msk = 0x7ff80 + // Position of PRO_WR_BAK_TO_READ field. + DPORT_PRO_DCACHE_DBUG0_PRO_WR_BAK_TO_READ_Pos = 0x13 + // Bit mask of PRO_WR_BAK_TO_READ field. + DPORT_PRO_DCACHE_DBUG0_PRO_WR_BAK_TO_READ_Msk = 0x80000 + // Bit PRO_WR_BAK_TO_READ. + DPORT_PRO_DCACHE_DBUG0_PRO_WR_BAK_TO_READ = 0x80000 + // Position of PRO_TX_END field. + DPORT_PRO_DCACHE_DBUG0_PRO_TX_END_Pos = 0x14 + // Bit mask of PRO_TX_END field. + DPORT_PRO_DCACHE_DBUG0_PRO_TX_END_Msk = 0x100000 + // Bit PRO_TX_END. + DPORT_PRO_DCACHE_DBUG0_PRO_TX_END = 0x100000 + // Position of PRO_SLAVE_WR field. + DPORT_PRO_DCACHE_DBUG0_PRO_SLAVE_WR_Pos = 0x15 + // Bit mask of PRO_SLAVE_WR field. + DPORT_PRO_DCACHE_DBUG0_PRO_SLAVE_WR_Msk = 0x200000 + // Bit PRO_SLAVE_WR. + DPORT_PRO_DCACHE_DBUG0_PRO_SLAVE_WR = 0x200000 + // Position of PRO_SLAVE_WDATA_V field. + DPORT_PRO_DCACHE_DBUG0_PRO_SLAVE_WDATA_V_Pos = 0x16 + // Bit mask of PRO_SLAVE_WDATA_V field. + DPORT_PRO_DCACHE_DBUG0_PRO_SLAVE_WDATA_V_Msk = 0x400000 + // Bit PRO_SLAVE_WDATA_V. + DPORT_PRO_DCACHE_DBUG0_PRO_SLAVE_WDATA_V = 0x400000 + // Position of PRO_RX_END field. + DPORT_PRO_DCACHE_DBUG0_PRO_RX_END_Pos = 0x17 + // Bit mask of PRO_RX_END field. + DPORT_PRO_DCACHE_DBUG0_PRO_RX_END_Msk = 0x800000 + // Bit PRO_RX_END. + DPORT_PRO_DCACHE_DBUG0_PRO_RX_END = 0x800000 + + // PRO_DCACHE_DBUG1 + // Position of PRO_CTAG_RAM_RDATA field. + DPORT_PRO_DCACHE_DBUG1_PRO_CTAG_RAM_RDATA_Pos = 0x0 + // Bit mask of PRO_CTAG_RAM_RDATA field. + DPORT_PRO_DCACHE_DBUG1_PRO_CTAG_RAM_RDATA_Msk = 0xffffffff + + // PRO_DCACHE_DBUG2 + // Position of PRO_CACHE_VADDR field. + DPORT_PRO_DCACHE_DBUG2_PRO_CACHE_VADDR_Pos = 0x0 + // Bit mask of PRO_CACHE_VADDR field. + DPORT_PRO_DCACHE_DBUG2_PRO_CACHE_VADDR_Msk = 0x7ffffff + + // PRO_DCACHE_DBUG3 + // Position of PRO_MMU_RDATA field. + DPORT_PRO_DCACHE_DBUG3_PRO_MMU_RDATA_Pos = 0x0 + // Bit mask of PRO_MMU_RDATA field. + DPORT_PRO_DCACHE_DBUG3_PRO_MMU_RDATA_Msk = 0x1ff + // Position of PRO_CPU_DISABLED_CACHE_IA field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_Pos = 0x9 + // Bit mask of PRO_CPU_DISABLED_CACHE_IA field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_Msk = 0x7e00 + // Position of PRO_CPU_DISABLED_CACHE_IA_OPPOSITE field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_Pos = 0x9 + // Bit mask of PRO_CPU_DISABLED_CACHE_IA_OPPOSITE field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_Msk = 0x200 + // Bit PRO_CPU_DISABLED_CACHE_IA_OPPOSITE. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE = 0x200 + // Position of PRO_CPU_DISABLED_CACHE_IA_DRAM1 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DRAM1_Pos = 0xa + // Bit mask of PRO_CPU_DISABLED_CACHE_IA_DRAM1 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DRAM1_Msk = 0x400 + // Bit PRO_CPU_DISABLED_CACHE_IA_DRAM1. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DRAM1 = 0x400 + // Position of PRO_CPU_DISABLED_CACHE_IA_IROM0 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IROM0_Pos = 0xb + // Bit mask of PRO_CPU_DISABLED_CACHE_IA_IROM0 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IROM0_Msk = 0x800 + // Bit PRO_CPU_DISABLED_CACHE_IA_IROM0. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IROM0 = 0x800 + // Position of PRO_CPU_DISABLED_CACHE_IA_IRAM1 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM1_Pos = 0xc + // Bit mask of PRO_CPU_DISABLED_CACHE_IA_IRAM1 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM1_Msk = 0x1000 + // Bit PRO_CPU_DISABLED_CACHE_IA_IRAM1. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM1 = 0x1000 + // Position of PRO_CPU_DISABLED_CACHE_IA_IRAM0 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM0_Pos = 0xd + // Bit mask of PRO_CPU_DISABLED_CACHE_IA_IRAM0 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM0_Msk = 0x2000 + // Bit PRO_CPU_DISABLED_CACHE_IA_IRAM0. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_IRAM0 = 0x2000 + // Position of PRO_CPU_DISABLED_CACHE_IA_DROM0 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DROM0_Pos = 0xe + // Bit mask of PRO_CPU_DISABLED_CACHE_IA_DROM0 field. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DROM0_Msk = 0x4000 + // Bit PRO_CPU_DISABLED_CACHE_IA_DROM0. + DPORT_PRO_DCACHE_DBUG3_PRO_CPU_DISABLED_CACHE_IA_DROM0 = 0x4000 + // Position of PRO_CACHE_IRAM0_PID_ERROR field. + DPORT_PRO_DCACHE_DBUG3_PRO_CACHE_IRAM0_PID_ERROR_Pos = 0xf + // Bit mask of PRO_CACHE_IRAM0_PID_ERROR field. + DPORT_PRO_DCACHE_DBUG3_PRO_CACHE_IRAM0_PID_ERROR_Msk = 0x8000 + // Bit PRO_CACHE_IRAM0_PID_ERROR. + DPORT_PRO_DCACHE_DBUG3_PRO_CACHE_IRAM0_PID_ERROR = 0x8000 + + // PRO_DCACHE_DBUG4 + // Position of PRO_DRAM1ADDR0_IA field. + DPORT_PRO_DCACHE_DBUG4_PRO_DRAM1ADDR0_IA_Pos = 0x0 + // Bit mask of PRO_DRAM1ADDR0_IA field. + DPORT_PRO_DCACHE_DBUG4_PRO_DRAM1ADDR0_IA_Msk = 0xfffff + + // PRO_DCACHE_DBUG5 + // Position of PRO_DROM0ADDR0_IA field. + DPORT_PRO_DCACHE_DBUG5_PRO_DROM0ADDR0_IA_Pos = 0x0 + // Bit mask of PRO_DROM0ADDR0_IA field. + DPORT_PRO_DCACHE_DBUG5_PRO_DROM0ADDR0_IA_Msk = 0xfffff + + // PRO_DCACHE_DBUG6 + // Position of PRO_IRAM0ADDR_IA field. + DPORT_PRO_DCACHE_DBUG6_PRO_IRAM0ADDR_IA_Pos = 0x0 + // Bit mask of PRO_IRAM0ADDR_IA field. + DPORT_PRO_DCACHE_DBUG6_PRO_IRAM0ADDR_IA_Msk = 0xfffff + + // PRO_DCACHE_DBUG7 + // Position of PRO_IRAM1ADDR_IA field. + DPORT_PRO_DCACHE_DBUG7_PRO_IRAM1ADDR_IA_Pos = 0x0 + // Bit mask of PRO_IRAM1ADDR_IA field. + DPORT_PRO_DCACHE_DBUG7_PRO_IRAM1ADDR_IA_Msk = 0xfffff + + // PRO_DCACHE_DBUG8 + // Position of PRO_IROM0ADDR_IA field. + DPORT_PRO_DCACHE_DBUG8_PRO_IROM0ADDR_IA_Pos = 0x0 + // Bit mask of PRO_IROM0ADDR_IA field. + DPORT_PRO_DCACHE_DBUG8_PRO_IROM0ADDR_IA_Msk = 0xfffff + + // PRO_DCACHE_DBUG9 + // Position of PRO_OPSDRAMADDR_IA field. + DPORT_PRO_DCACHE_DBUG9_PRO_OPSDRAMADDR_IA_Pos = 0x0 + // Bit mask of PRO_OPSDRAMADDR_IA field. + DPORT_PRO_DCACHE_DBUG9_PRO_OPSDRAMADDR_IA_Msk = 0xfffff + + // APP_DCACHE_DBUG0 + // Position of APP_SLAVE_WDATA field. + DPORT_APP_DCACHE_DBUG0_APP_SLAVE_WDATA_Pos = 0x0 + // Bit mask of APP_SLAVE_WDATA field. + DPORT_APP_DCACHE_DBUG0_APP_SLAVE_WDATA_Msk = 0x1 + // Bit APP_SLAVE_WDATA. + DPORT_APP_DCACHE_DBUG0_APP_SLAVE_WDATA = 0x1 + // Position of APP_CACHE_MMU_IA field. + DPORT_APP_DCACHE_DBUG0_APP_CACHE_MMU_IA_Pos = 0x0 + // Bit mask of APP_CACHE_MMU_IA field. + DPORT_APP_DCACHE_DBUG0_APP_CACHE_MMU_IA_Msk = 0x1 + // Bit APP_CACHE_MMU_IA. + DPORT_APP_DCACHE_DBUG0_APP_CACHE_MMU_IA = 0x1 + // Position of APP_CACHE_IA field. + DPORT_APP_DCACHE_DBUG0_APP_CACHE_IA_Pos = 0x1 + // Bit mask of APP_CACHE_IA field. + DPORT_APP_DCACHE_DBUG0_APP_CACHE_IA_Msk = 0x7e + // Position of APP_CACHE_STATE field. + DPORT_APP_DCACHE_DBUG0_APP_CACHE_STATE_Pos = 0x7 + // Bit mask of APP_CACHE_STATE field. + DPORT_APP_DCACHE_DBUG0_APP_CACHE_STATE_Msk = 0x7ff80 + // Position of APP_WR_BAK_TO_READ field. + DPORT_APP_DCACHE_DBUG0_APP_WR_BAK_TO_READ_Pos = 0x13 + // Bit mask of APP_WR_BAK_TO_READ field. + DPORT_APP_DCACHE_DBUG0_APP_WR_BAK_TO_READ_Msk = 0x80000 + // Bit APP_WR_BAK_TO_READ. + DPORT_APP_DCACHE_DBUG0_APP_WR_BAK_TO_READ = 0x80000 + // Position of APP_TX_END field. + DPORT_APP_DCACHE_DBUG0_APP_TX_END_Pos = 0x14 + // Bit mask of APP_TX_END field. + DPORT_APP_DCACHE_DBUG0_APP_TX_END_Msk = 0x100000 + // Bit APP_TX_END. + DPORT_APP_DCACHE_DBUG0_APP_TX_END = 0x100000 + // Position of APP_SLAVE_WR field. + DPORT_APP_DCACHE_DBUG0_APP_SLAVE_WR_Pos = 0x15 + // Bit mask of APP_SLAVE_WR field. + DPORT_APP_DCACHE_DBUG0_APP_SLAVE_WR_Msk = 0x200000 + // Bit APP_SLAVE_WR. + DPORT_APP_DCACHE_DBUG0_APP_SLAVE_WR = 0x200000 + // Position of APP_SLAVE_WDATA_V field. + DPORT_APP_DCACHE_DBUG0_APP_SLAVE_WDATA_V_Pos = 0x16 + // Bit mask of APP_SLAVE_WDATA_V field. + DPORT_APP_DCACHE_DBUG0_APP_SLAVE_WDATA_V_Msk = 0x400000 + // Bit APP_SLAVE_WDATA_V. + DPORT_APP_DCACHE_DBUG0_APP_SLAVE_WDATA_V = 0x400000 + // Position of APP_RX_END field. + DPORT_APP_DCACHE_DBUG0_APP_RX_END_Pos = 0x17 + // Bit mask of APP_RX_END field. + DPORT_APP_DCACHE_DBUG0_APP_RX_END_Msk = 0x800000 + // Bit APP_RX_END. + DPORT_APP_DCACHE_DBUG0_APP_RX_END = 0x800000 + + // APP_DCACHE_DBUG1 + // Position of APP_CTAG_RAM_RDATA field. + DPORT_APP_DCACHE_DBUG1_APP_CTAG_RAM_RDATA_Pos = 0x0 + // Bit mask of APP_CTAG_RAM_RDATA field. + DPORT_APP_DCACHE_DBUG1_APP_CTAG_RAM_RDATA_Msk = 0xffffffff + + // APP_DCACHE_DBUG2 + // Position of APP_CACHE_VADDR field. + DPORT_APP_DCACHE_DBUG2_APP_CACHE_VADDR_Pos = 0x0 + // Bit mask of APP_CACHE_VADDR field. + DPORT_APP_DCACHE_DBUG2_APP_CACHE_VADDR_Msk = 0x7ffffff + + // APP_DCACHE_DBUG3 + // Position of APP_MMU_RDATA field. + DPORT_APP_DCACHE_DBUG3_APP_MMU_RDATA_Pos = 0x0 + // Bit mask of APP_MMU_RDATA field. + DPORT_APP_DCACHE_DBUG3_APP_MMU_RDATA_Msk = 0x1ff + // Position of APP_CPU_DISABLED_CACHE_IA field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_Pos = 0x9 + // Bit mask of APP_CPU_DISABLED_CACHE_IA field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_Msk = 0x7e00 + // Position of APP_CPU_DISABLED_CACHE_IA_OPPOSITE field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_Pos = 0x9 + // Bit mask of APP_CPU_DISABLED_CACHE_IA_OPPOSITE field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_Msk = 0x200 + // Bit APP_CPU_DISABLED_CACHE_IA_OPPOSITE. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_OPPOSITE = 0x200 + // Position of APP_CPU_DISABLED_CACHE_IA_DRAM1 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DRAM1_Pos = 0xa + // Bit mask of APP_CPU_DISABLED_CACHE_IA_DRAM1 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DRAM1_Msk = 0x400 + // Bit APP_CPU_DISABLED_CACHE_IA_DRAM1. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DRAM1 = 0x400 + // Position of APP_CPU_DISABLED_CACHE_IA_IROM0 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IROM0_Pos = 0xb + // Bit mask of APP_CPU_DISABLED_CACHE_IA_IROM0 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IROM0_Msk = 0x800 + // Bit APP_CPU_DISABLED_CACHE_IA_IROM0. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IROM0 = 0x800 + // Position of APP_CPU_DISABLED_CACHE_IA_IRAM1 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM1_Pos = 0xc + // Bit mask of APP_CPU_DISABLED_CACHE_IA_IRAM1 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM1_Msk = 0x1000 + // Bit APP_CPU_DISABLED_CACHE_IA_IRAM1. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM1 = 0x1000 + // Position of APP_CPU_DISABLED_CACHE_IA_IRAM0 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM0_Pos = 0xd + // Bit mask of APP_CPU_DISABLED_CACHE_IA_IRAM0 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM0_Msk = 0x2000 + // Bit APP_CPU_DISABLED_CACHE_IA_IRAM0. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_IRAM0 = 0x2000 + // Position of APP_CPU_DISABLED_CACHE_IA_DROM0 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DROM0_Pos = 0xe + // Bit mask of APP_CPU_DISABLED_CACHE_IA_DROM0 field. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DROM0_Msk = 0x4000 + // Bit APP_CPU_DISABLED_CACHE_IA_DROM0. + DPORT_APP_DCACHE_DBUG3_APP_CPU_DISABLED_CACHE_IA_DROM0 = 0x4000 + // Position of APP_CACHE_IRAM0_PID_ERROR field. + DPORT_APP_DCACHE_DBUG3_APP_CACHE_IRAM0_PID_ERROR_Pos = 0xf + // Bit mask of APP_CACHE_IRAM0_PID_ERROR field. + DPORT_APP_DCACHE_DBUG3_APP_CACHE_IRAM0_PID_ERROR_Msk = 0x8000 + // Bit APP_CACHE_IRAM0_PID_ERROR. + DPORT_APP_DCACHE_DBUG3_APP_CACHE_IRAM0_PID_ERROR = 0x8000 + + // APP_DCACHE_DBUG4 + // Position of APP_DRAM1ADDR0_IA field. + DPORT_APP_DCACHE_DBUG4_APP_DRAM1ADDR0_IA_Pos = 0x0 + // Bit mask of APP_DRAM1ADDR0_IA field. + DPORT_APP_DCACHE_DBUG4_APP_DRAM1ADDR0_IA_Msk = 0xfffff + + // APP_DCACHE_DBUG5 + // Position of APP_DROM0ADDR0_IA field. + DPORT_APP_DCACHE_DBUG5_APP_DROM0ADDR0_IA_Pos = 0x0 + // Bit mask of APP_DROM0ADDR0_IA field. + DPORT_APP_DCACHE_DBUG5_APP_DROM0ADDR0_IA_Msk = 0xfffff + + // APP_DCACHE_DBUG6 + // Position of APP_IRAM0ADDR_IA field. + DPORT_APP_DCACHE_DBUG6_APP_IRAM0ADDR_IA_Pos = 0x0 + // Bit mask of APP_IRAM0ADDR_IA field. + DPORT_APP_DCACHE_DBUG6_APP_IRAM0ADDR_IA_Msk = 0xfffff + + // APP_DCACHE_DBUG7 + // Position of APP_IRAM1ADDR_IA field. + DPORT_APP_DCACHE_DBUG7_APP_IRAM1ADDR_IA_Pos = 0x0 + // Bit mask of APP_IRAM1ADDR_IA field. + DPORT_APP_DCACHE_DBUG7_APP_IRAM1ADDR_IA_Msk = 0xfffff + + // APP_DCACHE_DBUG8 + // Position of APP_IROM0ADDR_IA field. + DPORT_APP_DCACHE_DBUG8_APP_IROM0ADDR_IA_Pos = 0x0 + // Bit mask of APP_IROM0ADDR_IA field. + DPORT_APP_DCACHE_DBUG8_APP_IROM0ADDR_IA_Msk = 0xfffff + + // APP_DCACHE_DBUG9 + // Position of APP_OPSDRAMADDR_IA field. + DPORT_APP_DCACHE_DBUG9_APP_OPSDRAMADDR_IA_Pos = 0x0 + // Bit mask of APP_OPSDRAMADDR_IA field. + DPORT_APP_DCACHE_DBUG9_APP_OPSDRAMADDR_IA_Msk = 0xfffff + + // PRO_CPU_RECORD_CTRL + // Position of PRO_CPU_RECORD_ENABLE field. + DPORT_PRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_ENABLE_Pos = 0x0 + // Bit mask of PRO_CPU_RECORD_ENABLE field. + DPORT_PRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_ENABLE_Msk = 0x1 + // Bit PRO_CPU_RECORD_ENABLE. + DPORT_PRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_ENABLE = 0x1 + // Position of PRO_CPU_RECORD_DISABLE field. + DPORT_PRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_DISABLE_Pos = 0x4 + // Bit mask of PRO_CPU_RECORD_DISABLE field. + DPORT_PRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_DISABLE_Msk = 0x10 + // Bit PRO_CPU_RECORD_DISABLE. + DPORT_PRO_CPU_RECORD_CTRL_PRO_CPU_RECORD_DISABLE = 0x10 + // Position of PRO_CPU_PDEBUG_ENABLE field. + DPORT_PRO_CPU_RECORD_CTRL_PRO_CPU_PDEBUG_ENABLE_Pos = 0x8 + // Bit mask of PRO_CPU_PDEBUG_ENABLE field. + DPORT_PRO_CPU_RECORD_CTRL_PRO_CPU_PDEBUG_ENABLE_Msk = 0x100 + // Bit PRO_CPU_PDEBUG_ENABLE. + DPORT_PRO_CPU_RECORD_CTRL_PRO_CPU_PDEBUG_ENABLE = 0x100 + + // PRO_CPU_RECORD_STATUS + // Position of PRO_CPU_RECORDING field. + DPORT_PRO_CPU_RECORD_STATUS_PRO_CPU_RECORDING_Pos = 0x0 + // Bit mask of PRO_CPU_RECORDING field. + DPORT_PRO_CPU_RECORD_STATUS_PRO_CPU_RECORDING_Msk = 0x1 + // Bit PRO_CPU_RECORDING. + DPORT_PRO_CPU_RECORD_STATUS_PRO_CPU_RECORDING = 0x1 + + // PRO_CPU_RECORD_PID + // Position of RECORD_PRO_PID field. + DPORT_PRO_CPU_RECORD_PID_RECORD_PRO_PID_Pos = 0x0 + // Bit mask of RECORD_PRO_PID field. + DPORT_PRO_CPU_RECORD_PID_RECORD_PRO_PID_Msk = 0x7 + + // PRO_CPU_RECORD_PDEBUGINST + // Position of RECORD_PRO_PDEBUGINST field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PRO_PDEBUGINST_Pos = 0x0 + // Bit mask of RECORD_PRO_PDEBUGINST field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PRO_PDEBUGINST_Msk = 0xffffffff + // Position of RECORD_PDEBUGINST_SZ field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_SZ_Pos = 0x0 + // Bit mask of RECORD_PDEBUGINST_SZ field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_SZ_Msk = 0xff + // Position of RECORD_PDEBUGINST_ISRC field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_ISRC_Pos = 0xc + // Bit mask of RECORD_PDEBUGINST_ISRC field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_ISRC_Msk = 0x7000 + // Position of RECORD_PDEBUGINST_LOOP_REP field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP_REP_Pos = 0x14 + // Bit mask of RECORD_PDEBUGINST_LOOP_REP field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP_REP_Msk = 0x100000 + // Bit RECORD_PDEBUGINST_LOOP_REP. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP_REP = 0x100000 + // Position of RECORD_PDEBUGINST_LOOP field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP_Pos = 0x15 + // Bit mask of RECORD_PDEBUGINST_LOOP field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP_Msk = 0x200000 + // Bit RECORD_PDEBUGINST_LOOP. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_LOOP = 0x200000 + // Position of RECORD_PDEBUGINST_CINTL field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_CINTL_Pos = 0x18 + // Bit mask of RECORD_PDEBUGINST_CINTL field. + DPORT_PRO_CPU_RECORD_PDEBUGINST_RECORD_PDEBUGINST_CINTL_Msk = 0xf000000 + + // PRO_CPU_RECORD_PDEBUGSTATUS + // Position of RECORD_PRO_PDEBUGSTATUS field. + DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PRO_PDEBUGSTATUS_Pos = 0x0 + // Bit mask of RECORD_PRO_PDEBUGSTATUS field. + DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PRO_PDEBUGSTATUS_Msk = 0xff + // Position of RECORD_PDEBUGSTATUS_BBCAUSE field. + DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PDEBUGSTATUS_BBCAUSE_Pos = 0x0 + // Bit mask of RECORD_PDEBUGSTATUS_BBCAUSE field. + DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PDEBUGSTATUS_BBCAUSE_Msk = 0x3f + // Position of RECORD_PDEBUGSTATUS_INSNTYPE field. + DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PDEBUGSTATUS_INSNTYPE_Pos = 0x0 + // Bit mask of RECORD_PDEBUGSTATUS_INSNTYPE field. + DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_RECORD_PDEBUGSTATUS_INSNTYPE_Msk = 0x3f + + // PRO_CPU_RECORD_PDEBUGDATA + // Position of RECORD_PRO_PDEBUGDATA field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PRO_PDEBUGDATA_Pos = 0x0 + // Bit mask of RECORD_PRO_PDEBUGDATA field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PRO_PDEBUGDATA_Msk = 0xffffffff + // Position of RECORD_PDEBUGDATA_DEP_OTHER field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_OTHER_Pos = 0x0 + // Bit mask of RECORD_PDEBUGDATA_DEP_OTHER field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_OTHER_Msk = 0x1 + // Bit RECORD_PDEBUGDATA_DEP_OTHER. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_OTHER = 0x1 + // Position of RECORD_PDEBUGDATA_EXCVEC field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_EXCVEC_Pos = 0x0 + // Bit mask of RECORD_PDEBUGDATA_EXCVEC field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_EXCVEC_Msk = 0x1f + // Position of RECORD_PDEBUGDATA_INSNTYPE_SR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_SR_Pos = 0x0 + // Bit mask of RECORD_PDEBUGDATA_INSNTYPE_SR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_SR_Msk = 0xff + // Position of RECORD_PDEBUGDATA_INSNTYPE_RER field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RER_Pos = 0x0 + // Bit mask of RECORD_PDEBUGDATA_INSNTYPE_RER field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RER_Msk = 0x1 + // Bit RECORD_PDEBUGDATA_INSNTYPE_RER. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RER = 0x1 + // Position of RECORD_PDEBUGDATA_STALL_BUFF field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFF_Pos = 0x1 + // Bit mask of RECORD_PDEBUGDATA_STALL_BUFF field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFF_Msk = 0x2 + // Bit RECORD_PDEBUGDATA_STALL_BUFF. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFF = 0x2 + // Position of RECORD_PDEBUGDATA_INSNTYPE_WER field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WER_Pos = 0x1 + // Bit mask of RECORD_PDEBUGDATA_INSNTYPE_WER field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WER_Msk = 0x2 + // Bit RECORD_PDEBUGDATA_INSNTYPE_WER. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WER = 0x2 + // Position of RECORD_PDEBUGDATA_STALL_BUFFCONFL field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFFCONFL_Pos = 0x2 + // Bit mask of RECORD_PDEBUGDATA_STALL_BUFFCONFL field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFFCONFL_Msk = 0x4 + // Bit RECORD_PDEBUGDATA_STALL_BUFFCONFL. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BUFFCONFL = 0x4 + // Position of RECORD_PDEBUGDATA_INSNTYPE_ER field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_ER_Pos = 0x2 + // Bit mask of RECORD_PDEBUGDATA_INSNTYPE_ER field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_ER_Msk = 0x3ffc + // Position of RECORD_PDEBUGDATA_STALL_DCM field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_DCM_Pos = 0x3 + // Bit mask of RECORD_PDEBUGDATA_STALL_DCM field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_DCM_Msk = 0x8 + // Bit RECORD_PDEBUGDATA_STALL_DCM. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_DCM = 0x8 + // Position of RECORD_PDEBUGDATA_STALL_LSU field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSU_Pos = 0x4 + // Bit mask of RECORD_PDEBUGDATA_STALL_LSU field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSU_Msk = 0x10 + // Bit RECORD_PDEBUGDATA_STALL_LSU. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSU = 0x10 + // Position of RECORD_PDEBUGDATA_STALL_ICM field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ICM_Pos = 0x6 + // Bit mask of RECORD_PDEBUGDATA_STALL_ICM field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ICM_Msk = 0x40 + // Bit RECORD_PDEBUGDATA_STALL_ICM. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ICM = 0x40 + // Position of RECORD_PDEBUGDATA_STALL_IRAMBUSY field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IRAMBUSY_Pos = 0x7 + // Bit mask of RECORD_PDEBUGDATA_STALL_IRAMBUSY field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IRAMBUSY_Msk = 0x80 + // Bit RECORD_PDEBUGDATA_STALL_IRAMBUSY. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IRAMBUSY = 0x80 + // Position of RECORD_PDEBUGDATA_DEP_LSU field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_LSU_Pos = 0x8 + // Bit mask of RECORD_PDEBUGDATA_DEP_LSU field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_LSU_Msk = 0x100 + // Bit RECORD_PDEBUGDATA_DEP_LSU. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_LSU = 0x100 + // Position of RECORD_PDEBUGDATA_STALL_IPIF field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IPIF_Pos = 0x8 + // Bit mask of RECORD_PDEBUGDATA_STALL_IPIF field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IPIF_Msk = 0x100 + // Bit RECORD_PDEBUGDATA_STALL_IPIF. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_IPIF = 0x100 + // Position of RECORD_PDEBUGDATA_INSNTYPE_RSR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RSR_Pos = 0x8 + // Bit mask of RECORD_PDEBUGDATA_INSNTYPE_RSR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RSR_Msk = 0x100 + // Bit RECORD_PDEBUGDATA_INSNTYPE_RSR. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_RSR = 0x100 + // Position of RECORD_PDEBUGDATA_STALL_TIE field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_TIE_Pos = 0x9 + // Bit mask of RECORD_PDEBUGDATA_STALL_TIE field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_TIE_Msk = 0x200 + // Bit RECORD_PDEBUGDATA_STALL_TIE. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_TIE = 0x200 + // Position of RECORD_PDEBUGDATA_INSNTYPE_WSR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WSR_Pos = 0x9 + // Bit mask of RECORD_PDEBUGDATA_INSNTYPE_WSR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WSR_Msk = 0x200 + // Bit RECORD_PDEBUGDATA_INSNTYPE_WSR. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_WSR = 0x200 + // Position of RECORD_PDEBUGDATA_STALL_RUN field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_RUN_Pos = 0xa + // Bit mask of RECORD_PDEBUGDATA_STALL_RUN field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_RUN_Msk = 0x400 + // Bit RECORD_PDEBUGDATA_STALL_RUN. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_RUN = 0x400 + // Position of RECORD_PDEBUGDATA_INSNTYPE_XSR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_XSR_Pos = 0xa + // Bit mask of RECORD_PDEBUGDATA_INSNTYPE_XSR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_XSR_Msk = 0x400 + // Bit RECORD_PDEBUGDATA_INSNTYPE_XSR. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_INSNTYPE_XSR = 0x400 + // Position of RECORD_PDEBUGDATA_DEP_STR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_STR_Pos = 0xb + // Bit mask of RECORD_PDEBUGDATA_DEP_STR field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_STR_Msk = 0x800 + // Bit RECORD_PDEBUGDATA_DEP_STR. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_STR = 0x800 + // Position of RECORD_PDEBUGDATA_DEP field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_Pos = 0xc + // Bit mask of RECORD_PDEBUGDATA_DEP field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_Msk = 0x1000 + // Bit RECORD_PDEBUGDATA_DEP. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP = 0x1000 + // Position of RECORD_PDEBUGDATA_STALL_BPIFETCH field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPIFETCH_Pos = 0xc + // Bit mask of RECORD_PDEBUGDATA_STALL_BPIFETCH field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPIFETCH_Msk = 0x1000 + // Bit RECORD_PDEBUGDATA_STALL_BPIFETCH. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPIFETCH = 0x1000 + // Position of RECORD_PDEBUGDATA_STALL_L32R field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_L32R_Pos = 0xd + // Bit mask of RECORD_PDEBUGDATA_STALL_L32R field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_L32R_Msk = 0x2000 + // Bit RECORD_PDEBUGDATA_STALL_L32R. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_L32R = 0x2000 + // Position of RECORD_PDEBUGDATA_STALL_LSPROC field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSPROC_Pos = 0xe + // Bit mask of RECORD_PDEBUGDATA_STALL_LSPROC field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSPROC_Msk = 0x4000 + // Bit RECORD_PDEBUGDATA_STALL_LSPROC. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_LSPROC = 0x4000 + // Position of RECORD_PDEBUGDATA_STALL_BPLOAD field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPLOAD_Pos = 0xf + // Bit mask of RECORD_PDEBUGDATA_STALL_BPLOAD field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPLOAD_Msk = 0x8000 + // Bit RECORD_PDEBUGDATA_STALL_BPLOAD. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BPLOAD = 0x8000 + // Position of RECORD_PDEBUGDATA_DEP_MEMW field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_MEMW_Pos = 0x10 + // Bit mask of RECORD_PDEBUGDATA_DEP_MEMW field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_MEMW_Msk = 0x10000 + // Bit RECORD_PDEBUGDATA_DEP_MEMW. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_MEMW = 0x10000 + // Position of RECORD_PDEBUGDATA_EXCCAUSE field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_EXCCAUSE_Pos = 0x10 + // Bit mask of RECORD_PDEBUGDATA_EXCCAUSE field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_EXCCAUSE_Msk = 0x3f0000 + // Position of RECORD_PDEBUGDATA_STALL_BANKCONFL field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BANKCONFL_Pos = 0x10 + // Bit mask of RECORD_PDEBUGDATA_STALL_BANKCONFL field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BANKCONFL_Msk = 0x10000 + // Bit RECORD_PDEBUGDATA_STALL_BANKCONFL. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_BANKCONFL = 0x10000 + // Position of RECORD_PDEBUGDATA_DEP_HALT field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_HALT_Pos = 0x11 + // Bit mask of RECORD_PDEBUGDATA_DEP_HALT field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_HALT_Msk = 0x20000 + // Bit RECORD_PDEBUGDATA_DEP_HALT. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_DEP_HALT = 0x20000 + // Position of RECORD_PDEBUGDATA_STALL_ITERMUL field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERMUL_Pos = 0x12 + // Bit mask of RECORD_PDEBUGDATA_STALL_ITERMUL field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERMUL_Msk = 0x40000 + // Bit RECORD_PDEBUGDATA_STALL_ITERMUL. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERMUL = 0x40000 + // Position of RECORD_PDEBUGDATA_STALL_ITERDIV field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERDIV_Pos = 0x13 + // Bit mask of RECORD_PDEBUGDATA_STALL_ITERDIV field. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERDIV_Msk = 0x80000 + // Bit RECORD_PDEBUGDATA_STALL_ITERDIV. + DPORT_PRO_CPU_RECORD_PDEBUGDATA_RECORD_PDEBUGDATA_STALL_ITERDIV = 0x80000 + + // PRO_CPU_RECORD_PDEBUGPC + // Position of RECORD_PRO_PDEBUGPC field. + DPORT_PRO_CPU_RECORD_PDEBUGPC_RECORD_PRO_PDEBUGPC_Pos = 0x0 + // Bit mask of RECORD_PRO_PDEBUGPC field. + DPORT_PRO_CPU_RECORD_PDEBUGPC_RECORD_PRO_PDEBUGPC_Msk = 0xffffffff + + // PRO_CPU_RECORD_PDEBUGLS0STAT + // Position of RECORD_PRO_PDEBUGLS0STAT field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PRO_PDEBUGLS0STAT_Pos = 0x0 + // Bit mask of RECORD_PRO_PDEBUGLS0STAT field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PRO_PDEBUGLS0STAT_Msk = 0xffffffff + // Position of RECORD_PDEBUGLS0STAT_TYPE field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_TYPE_Pos = 0x0 + // Bit mask of RECORD_PDEBUGLS0STAT_TYPE field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_TYPE_Msk = 0xf + // Position of RECORD_PDEBUGLS0STAT_SZ field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_SZ_Pos = 0x4 + // Bit mask of RECORD_PDEBUGLS0STAT_SZ field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_SZ_Msk = 0xf0 + // Position of RECORD_PDEBUGLS0STAT_DTLBM field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DTLBM_Pos = 0x8 + // Bit mask of RECORD_PDEBUGLS0STAT_DTLBM field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DTLBM_Msk = 0x100 + // Bit RECORD_PDEBUGLS0STAT_DTLBM. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DTLBM = 0x100 + // Position of RECORD_PDEBUGLS0STAT_DCM field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCM_Pos = 0x9 + // Bit mask of RECORD_PDEBUGLS0STAT_DCM field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCM_Msk = 0x200 + // Bit RECORD_PDEBUGLS0STAT_DCM. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCM = 0x200 + // Position of RECORD_PDEBUGLS0STAT_DCH field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCH_Pos = 0xa + // Bit mask of RECORD_PDEBUGLS0STAT_DCH field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCH_Msk = 0x400 + // Bit RECORD_PDEBUGLS0STAT_DCH. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_DCH = 0x400 + // Position of RECORD_PDEBUGLS0STAT_UC field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_UC_Pos = 0xc + // Bit mask of RECORD_PDEBUGLS0STAT_UC field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_UC_Msk = 0x1000 + // Bit RECORD_PDEBUGLS0STAT_UC. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_UC = 0x1000 + // Position of RECORD_PDEBUGLS0STAT_WB field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_WB_Pos = 0xd + // Bit mask of RECORD_PDEBUGLS0STAT_WB field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_WB_Msk = 0x2000 + // Bit RECORD_PDEBUGLS0STAT_WB. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_WB = 0x2000 + // Position of RECORD_PDEBUGLS0STAT_COH field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_COH_Pos = 0x10 + // Bit mask of RECORD_PDEBUGLS0STAT_COH field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_COH_Msk = 0x10000 + // Bit RECORD_PDEBUGLS0STAT_COH. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_COH = 0x10000 + // Position of RECORD_PDEBUGLS0STAT_STCOH field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_STCOH_Pos = 0x11 + // Bit mask of RECORD_PDEBUGLS0STAT_STCOH field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_STCOH_Msk = 0x60000 + // Position of RECORD_PDEBUGLS0STAT_TGT field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_TGT_Pos = 0x14 + // Bit mask of RECORD_PDEBUGLS0STAT_TGT field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_RECORD_PDEBUGLS0STAT_TGT_Msk = 0xf00000 + + // PRO_CPU_RECORD_PDEBUGLS0ADDR + // Position of RECORD_PRO_PDEBUGLS0ADDR field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_RECORD_PRO_PDEBUGLS0ADDR_Pos = 0x0 + // Bit mask of RECORD_PRO_PDEBUGLS0ADDR field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_RECORD_PRO_PDEBUGLS0ADDR_Msk = 0xffffffff + + // PRO_CPU_RECORD_PDEBUGLS0DATA + // Position of RECORD_PRO_PDEBUGLS0DATA field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_RECORD_PRO_PDEBUGLS0DATA_Pos = 0x0 + // Bit mask of RECORD_PRO_PDEBUGLS0DATA field. + DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_RECORD_PRO_PDEBUGLS0DATA_Msk = 0xffffffff + + // APP_CPU_RECORD_CTRL + // Position of APP_CPU_RECORD_ENABLE field. + DPORT_APP_CPU_RECORD_CTRL_APP_CPU_RECORD_ENABLE_Pos = 0x0 + // Bit mask of APP_CPU_RECORD_ENABLE field. + DPORT_APP_CPU_RECORD_CTRL_APP_CPU_RECORD_ENABLE_Msk = 0x1 + // Bit APP_CPU_RECORD_ENABLE. + DPORT_APP_CPU_RECORD_CTRL_APP_CPU_RECORD_ENABLE = 0x1 + // Position of APP_CPU_RECORD_DISABLE field. + DPORT_APP_CPU_RECORD_CTRL_APP_CPU_RECORD_DISABLE_Pos = 0x4 + // Bit mask of APP_CPU_RECORD_DISABLE field. + DPORT_APP_CPU_RECORD_CTRL_APP_CPU_RECORD_DISABLE_Msk = 0x10 + // Bit APP_CPU_RECORD_DISABLE. + DPORT_APP_CPU_RECORD_CTRL_APP_CPU_RECORD_DISABLE = 0x10 + // Position of APP_CPU_PDEBUG_ENABLE field. + DPORT_APP_CPU_RECORD_CTRL_APP_CPU_PDEBUG_ENABLE_Pos = 0x8 + // Bit mask of APP_CPU_PDEBUG_ENABLE field. + DPORT_APP_CPU_RECORD_CTRL_APP_CPU_PDEBUG_ENABLE_Msk = 0x100 + // Bit APP_CPU_PDEBUG_ENABLE. + DPORT_APP_CPU_RECORD_CTRL_APP_CPU_PDEBUG_ENABLE = 0x100 + + // APP_CPU_RECORD_STATUS + // Position of APP_CPU_RECORDING field. + DPORT_APP_CPU_RECORD_STATUS_APP_CPU_RECORDING_Pos = 0x0 + // Bit mask of APP_CPU_RECORDING field. + DPORT_APP_CPU_RECORD_STATUS_APP_CPU_RECORDING_Msk = 0x1 + // Bit APP_CPU_RECORDING. + DPORT_APP_CPU_RECORD_STATUS_APP_CPU_RECORDING = 0x1 + + // APP_CPU_RECORD_PID + // Position of RECORD_APP_PID field. + DPORT_APP_CPU_RECORD_PID_RECORD_APP_PID_Pos = 0x0 + // Bit mask of RECORD_APP_PID field. + DPORT_APP_CPU_RECORD_PID_RECORD_APP_PID_Msk = 0x7 + + // APP_CPU_RECORD_PDEBUGINST + // Position of RECORD_APP_PDEBUGINST field. + DPORT_APP_CPU_RECORD_PDEBUGINST_RECORD_APP_PDEBUGINST_Pos = 0x0 + // Bit mask of RECORD_APP_PDEBUGINST field. + DPORT_APP_CPU_RECORD_PDEBUGINST_RECORD_APP_PDEBUGINST_Msk = 0xffffffff + + // APP_CPU_RECORD_PDEBUGSTATUS + // Position of RECORD_APP_PDEBUGSTATUS field. + DPORT_APP_CPU_RECORD_PDEBUGSTATUS_RECORD_APP_PDEBUGSTATUS_Pos = 0x0 + // Bit mask of RECORD_APP_PDEBUGSTATUS field. + DPORT_APP_CPU_RECORD_PDEBUGSTATUS_RECORD_APP_PDEBUGSTATUS_Msk = 0xff + + // APP_CPU_RECORD_PDEBUGDATA + // Position of RECORD_APP_PDEBUGDATA field. + DPORT_APP_CPU_RECORD_PDEBUGDATA_RECORD_APP_PDEBUGDATA_Pos = 0x0 + // Bit mask of RECORD_APP_PDEBUGDATA field. + DPORT_APP_CPU_RECORD_PDEBUGDATA_RECORD_APP_PDEBUGDATA_Msk = 0xffffffff + + // APP_CPU_RECORD_PDEBUGPC + // Position of RECORD_APP_PDEBUGPC field. + DPORT_APP_CPU_RECORD_PDEBUGPC_RECORD_APP_PDEBUGPC_Pos = 0x0 + // Bit mask of RECORD_APP_PDEBUGPC field. + DPORT_APP_CPU_RECORD_PDEBUGPC_RECORD_APP_PDEBUGPC_Msk = 0xffffffff + + // APP_CPU_RECORD_PDEBUGLS0STAT + // Position of RECORD_APP_PDEBUGLS0STAT field. + DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_RECORD_APP_PDEBUGLS0STAT_Pos = 0x0 + // Bit mask of RECORD_APP_PDEBUGLS0STAT field. + DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_RECORD_APP_PDEBUGLS0STAT_Msk = 0xffffffff + + // APP_CPU_RECORD_PDEBUGLS0ADDR + // Position of RECORD_APP_PDEBUGLS0ADDR field. + DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_RECORD_APP_PDEBUGLS0ADDR_Pos = 0x0 + // Bit mask of RECORD_APP_PDEBUGLS0ADDR field. + DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_RECORD_APP_PDEBUGLS0ADDR_Msk = 0xffffffff + + // APP_CPU_RECORD_PDEBUGLS0DATA + // Position of RECORD_APP_PDEBUGLS0DATA field. + DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_RECORD_APP_PDEBUGLS0DATA_Pos = 0x0 + // Bit mask of RECORD_APP_PDEBUGLS0DATA field. + DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_RECORD_APP_PDEBUGLS0DATA_Msk = 0xffffffff + + // RSA_PD_CTRL + // Position of RSA_PD field. + DPORT_RSA_PD_CTRL_RSA_PD_Pos = 0x0 + // Bit mask of RSA_PD field. + DPORT_RSA_PD_CTRL_RSA_PD_Msk = 0x1 + // Bit RSA_PD. + DPORT_RSA_PD_CTRL_RSA_PD = 0x1 + + // ROM_MPU_TABLE0 + // Position of ROM_MPU_TABLE0 field. + DPORT_ROM_MPU_TABLE0_ROM_MPU_TABLE0_Pos = 0x0 + // Bit mask of ROM_MPU_TABLE0 field. + DPORT_ROM_MPU_TABLE0_ROM_MPU_TABLE0_Msk = 0x3 + + // ROM_MPU_TABLE1 + // Position of ROM_MPU_TABLE1 field. + DPORT_ROM_MPU_TABLE1_ROM_MPU_TABLE1_Pos = 0x0 + // Bit mask of ROM_MPU_TABLE1 field. + DPORT_ROM_MPU_TABLE1_ROM_MPU_TABLE1_Msk = 0x3 + + // ROM_MPU_TABLE2 + // Position of ROM_MPU_TABLE2 field. + DPORT_ROM_MPU_TABLE2_ROM_MPU_TABLE2_Pos = 0x0 + // Bit mask of ROM_MPU_TABLE2 field. + DPORT_ROM_MPU_TABLE2_ROM_MPU_TABLE2_Msk = 0x3 + + // ROM_MPU_TABLE3 + // Position of ROM_MPU_TABLE3 field. + DPORT_ROM_MPU_TABLE3_ROM_MPU_TABLE3_Pos = 0x0 + // Bit mask of ROM_MPU_TABLE3 field. + DPORT_ROM_MPU_TABLE3_ROM_MPU_TABLE3_Msk = 0x3 + + // SHROM_MPU_TABLE0 + // Position of SHROM_MPU_TABLE0 field. + DPORT_SHROM_MPU_TABLE0_SHROM_MPU_TABLE0_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE0 field. + DPORT_SHROM_MPU_TABLE0_SHROM_MPU_TABLE0_Msk = 0x3 + + // SHROM_MPU_TABLE1 + // Position of SHROM_MPU_TABLE1 field. + DPORT_SHROM_MPU_TABLE1_SHROM_MPU_TABLE1_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE1 field. + DPORT_SHROM_MPU_TABLE1_SHROM_MPU_TABLE1_Msk = 0x3 + + // SHROM_MPU_TABLE2 + // Position of SHROM_MPU_TABLE2 field. + DPORT_SHROM_MPU_TABLE2_SHROM_MPU_TABLE2_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE2 field. + DPORT_SHROM_MPU_TABLE2_SHROM_MPU_TABLE2_Msk = 0x3 + + // SHROM_MPU_TABLE3 + // Position of SHROM_MPU_TABLE3 field. + DPORT_SHROM_MPU_TABLE3_SHROM_MPU_TABLE3_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE3 field. + DPORT_SHROM_MPU_TABLE3_SHROM_MPU_TABLE3_Msk = 0x3 + + // SHROM_MPU_TABLE4 + // Position of SHROM_MPU_TABLE4 field. + DPORT_SHROM_MPU_TABLE4_SHROM_MPU_TABLE4_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE4 field. + DPORT_SHROM_MPU_TABLE4_SHROM_MPU_TABLE4_Msk = 0x3 + + // SHROM_MPU_TABLE5 + // Position of SHROM_MPU_TABLE5 field. + DPORT_SHROM_MPU_TABLE5_SHROM_MPU_TABLE5_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE5 field. + DPORT_SHROM_MPU_TABLE5_SHROM_MPU_TABLE5_Msk = 0x3 + + // SHROM_MPU_TABLE6 + // Position of SHROM_MPU_TABLE6 field. + DPORT_SHROM_MPU_TABLE6_SHROM_MPU_TABLE6_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE6 field. + DPORT_SHROM_MPU_TABLE6_SHROM_MPU_TABLE6_Msk = 0x3 + + // SHROM_MPU_TABLE7 + // Position of SHROM_MPU_TABLE7 field. + DPORT_SHROM_MPU_TABLE7_SHROM_MPU_TABLE7_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE7 field. + DPORT_SHROM_MPU_TABLE7_SHROM_MPU_TABLE7_Msk = 0x3 + + // SHROM_MPU_TABLE8 + // Position of SHROM_MPU_TABLE8 field. + DPORT_SHROM_MPU_TABLE8_SHROM_MPU_TABLE8_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE8 field. + DPORT_SHROM_MPU_TABLE8_SHROM_MPU_TABLE8_Msk = 0x3 + + // SHROM_MPU_TABLE9 + // Position of SHROM_MPU_TABLE9 field. + DPORT_SHROM_MPU_TABLE9_SHROM_MPU_TABLE9_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE9 field. + DPORT_SHROM_MPU_TABLE9_SHROM_MPU_TABLE9_Msk = 0x3 + + // SHROM_MPU_TABLE10 + // Position of SHROM_MPU_TABLE10 field. + DPORT_SHROM_MPU_TABLE10_SHROM_MPU_TABLE10_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE10 field. + DPORT_SHROM_MPU_TABLE10_SHROM_MPU_TABLE10_Msk = 0x3 + + // SHROM_MPU_TABLE11 + // Position of SHROM_MPU_TABLE11 field. + DPORT_SHROM_MPU_TABLE11_SHROM_MPU_TABLE11_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE11 field. + DPORT_SHROM_MPU_TABLE11_SHROM_MPU_TABLE11_Msk = 0x3 + + // SHROM_MPU_TABLE12 + // Position of SHROM_MPU_TABLE12 field. + DPORT_SHROM_MPU_TABLE12_SHROM_MPU_TABLE12_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE12 field. + DPORT_SHROM_MPU_TABLE12_SHROM_MPU_TABLE12_Msk = 0x3 + + // SHROM_MPU_TABLE13 + // Position of SHROM_MPU_TABLE13 field. + DPORT_SHROM_MPU_TABLE13_SHROM_MPU_TABLE13_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE13 field. + DPORT_SHROM_MPU_TABLE13_SHROM_MPU_TABLE13_Msk = 0x3 + + // SHROM_MPU_TABLE14 + // Position of SHROM_MPU_TABLE14 field. + DPORT_SHROM_MPU_TABLE14_SHROM_MPU_TABLE14_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE14 field. + DPORT_SHROM_MPU_TABLE14_SHROM_MPU_TABLE14_Msk = 0x3 + + // SHROM_MPU_TABLE15 + // Position of SHROM_MPU_TABLE15 field. + DPORT_SHROM_MPU_TABLE15_SHROM_MPU_TABLE15_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE15 field. + DPORT_SHROM_MPU_TABLE15_SHROM_MPU_TABLE15_Msk = 0x3 + + // SHROM_MPU_TABLE16 + // Position of SHROM_MPU_TABLE16 field. + DPORT_SHROM_MPU_TABLE16_SHROM_MPU_TABLE16_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE16 field. + DPORT_SHROM_MPU_TABLE16_SHROM_MPU_TABLE16_Msk = 0x3 + + // SHROM_MPU_TABLE17 + // Position of SHROM_MPU_TABLE17 field. + DPORT_SHROM_MPU_TABLE17_SHROM_MPU_TABLE17_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE17 field. + DPORT_SHROM_MPU_TABLE17_SHROM_MPU_TABLE17_Msk = 0x3 + + // SHROM_MPU_TABLE18 + // Position of SHROM_MPU_TABLE18 field. + DPORT_SHROM_MPU_TABLE18_SHROM_MPU_TABLE18_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE18 field. + DPORT_SHROM_MPU_TABLE18_SHROM_MPU_TABLE18_Msk = 0x3 + + // SHROM_MPU_TABLE19 + // Position of SHROM_MPU_TABLE19 field. + DPORT_SHROM_MPU_TABLE19_SHROM_MPU_TABLE19_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE19 field. + DPORT_SHROM_MPU_TABLE19_SHROM_MPU_TABLE19_Msk = 0x3 + + // SHROM_MPU_TABLE20 + // Position of SHROM_MPU_TABLE20 field. + DPORT_SHROM_MPU_TABLE20_SHROM_MPU_TABLE20_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE20 field. + DPORT_SHROM_MPU_TABLE20_SHROM_MPU_TABLE20_Msk = 0x3 + + // SHROM_MPU_TABLE21 + // Position of SHROM_MPU_TABLE21 field. + DPORT_SHROM_MPU_TABLE21_SHROM_MPU_TABLE21_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE21 field. + DPORT_SHROM_MPU_TABLE21_SHROM_MPU_TABLE21_Msk = 0x3 + + // SHROM_MPU_TABLE22 + // Position of SHROM_MPU_TABLE22 field. + DPORT_SHROM_MPU_TABLE22_SHROM_MPU_TABLE22_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE22 field. + DPORT_SHROM_MPU_TABLE22_SHROM_MPU_TABLE22_Msk = 0x3 + + // SHROM_MPU_TABLE23 + // Position of SHROM_MPU_TABLE23 field. + DPORT_SHROM_MPU_TABLE23_SHROM_MPU_TABLE23_Pos = 0x0 + // Bit mask of SHROM_MPU_TABLE23 field. + DPORT_SHROM_MPU_TABLE23_SHROM_MPU_TABLE23_Msk = 0x3 + + // IMMU_TABLE0 + // Position of IMMU_TABLE0 field. + DPORT_IMMU_TABLE0_IMMU_TABLE0_Pos = 0x0 + // Bit mask of IMMU_TABLE0 field. + DPORT_IMMU_TABLE0_IMMU_TABLE0_Msk = 0x7f + + // IMMU_TABLE1 + // Position of IMMU_TABLE1 field. + DPORT_IMMU_TABLE1_IMMU_TABLE1_Pos = 0x0 + // Bit mask of IMMU_TABLE1 field. + DPORT_IMMU_TABLE1_IMMU_TABLE1_Msk = 0x7f + + // IMMU_TABLE2 + // Position of IMMU_TABLE2 field. + DPORT_IMMU_TABLE2_IMMU_TABLE2_Pos = 0x0 + // Bit mask of IMMU_TABLE2 field. + DPORT_IMMU_TABLE2_IMMU_TABLE2_Msk = 0x7f + + // IMMU_TABLE3 + // Position of IMMU_TABLE3 field. + DPORT_IMMU_TABLE3_IMMU_TABLE3_Pos = 0x0 + // Bit mask of IMMU_TABLE3 field. + DPORT_IMMU_TABLE3_IMMU_TABLE3_Msk = 0x7f + + // IMMU_TABLE4 + // Position of IMMU_TABLE4 field. + DPORT_IMMU_TABLE4_IMMU_TABLE4_Pos = 0x0 + // Bit mask of IMMU_TABLE4 field. + DPORT_IMMU_TABLE4_IMMU_TABLE4_Msk = 0x7f + + // IMMU_TABLE5 + // Position of IMMU_TABLE5 field. + DPORT_IMMU_TABLE5_IMMU_TABLE5_Pos = 0x0 + // Bit mask of IMMU_TABLE5 field. + DPORT_IMMU_TABLE5_IMMU_TABLE5_Msk = 0x7f + + // IMMU_TABLE6 + // Position of IMMU_TABLE6 field. + DPORT_IMMU_TABLE6_IMMU_TABLE6_Pos = 0x0 + // Bit mask of IMMU_TABLE6 field. + DPORT_IMMU_TABLE6_IMMU_TABLE6_Msk = 0x7f + + // IMMU_TABLE7 + // Position of IMMU_TABLE7 field. + DPORT_IMMU_TABLE7_IMMU_TABLE7_Pos = 0x0 + // Bit mask of IMMU_TABLE7 field. + DPORT_IMMU_TABLE7_IMMU_TABLE7_Msk = 0x7f + + // IMMU_TABLE8 + // Position of IMMU_TABLE8 field. + DPORT_IMMU_TABLE8_IMMU_TABLE8_Pos = 0x0 + // Bit mask of IMMU_TABLE8 field. + DPORT_IMMU_TABLE8_IMMU_TABLE8_Msk = 0x7f + + // IMMU_TABLE9 + // Position of IMMU_TABLE9 field. + DPORT_IMMU_TABLE9_IMMU_TABLE9_Pos = 0x0 + // Bit mask of IMMU_TABLE9 field. + DPORT_IMMU_TABLE9_IMMU_TABLE9_Msk = 0x7f + + // IMMU_TABLE10 + // Position of IMMU_TABLE10 field. + DPORT_IMMU_TABLE10_IMMU_TABLE10_Pos = 0x0 + // Bit mask of IMMU_TABLE10 field. + DPORT_IMMU_TABLE10_IMMU_TABLE10_Msk = 0x7f + + // IMMU_TABLE11 + // Position of IMMU_TABLE11 field. + DPORT_IMMU_TABLE11_IMMU_TABLE11_Pos = 0x0 + // Bit mask of IMMU_TABLE11 field. + DPORT_IMMU_TABLE11_IMMU_TABLE11_Msk = 0x7f + + // IMMU_TABLE12 + // Position of IMMU_TABLE12 field. + DPORT_IMMU_TABLE12_IMMU_TABLE12_Pos = 0x0 + // Bit mask of IMMU_TABLE12 field. + DPORT_IMMU_TABLE12_IMMU_TABLE12_Msk = 0x7f + + // IMMU_TABLE13 + // Position of IMMU_TABLE13 field. + DPORT_IMMU_TABLE13_IMMU_TABLE13_Pos = 0x0 + // Bit mask of IMMU_TABLE13 field. + DPORT_IMMU_TABLE13_IMMU_TABLE13_Msk = 0x7f + + // IMMU_TABLE14 + // Position of IMMU_TABLE14 field. + DPORT_IMMU_TABLE14_IMMU_TABLE14_Pos = 0x0 + // Bit mask of IMMU_TABLE14 field. + DPORT_IMMU_TABLE14_IMMU_TABLE14_Msk = 0x7f + + // IMMU_TABLE15 + // Position of IMMU_TABLE15 field. + DPORT_IMMU_TABLE15_IMMU_TABLE15_Pos = 0x0 + // Bit mask of IMMU_TABLE15 field. + DPORT_IMMU_TABLE15_IMMU_TABLE15_Msk = 0x7f + + // DMMU_TABLE0 + // Position of DMMU_TABLE0 field. + DPORT_DMMU_TABLE0_DMMU_TABLE0_Pos = 0x0 + // Bit mask of DMMU_TABLE0 field. + DPORT_DMMU_TABLE0_DMMU_TABLE0_Msk = 0x7f + + // DMMU_TABLE1 + // Position of DMMU_TABLE1 field. + DPORT_DMMU_TABLE1_DMMU_TABLE1_Pos = 0x0 + // Bit mask of DMMU_TABLE1 field. + DPORT_DMMU_TABLE1_DMMU_TABLE1_Msk = 0x7f + + // DMMU_TABLE2 + // Position of DMMU_TABLE2 field. + DPORT_DMMU_TABLE2_DMMU_TABLE2_Pos = 0x0 + // Bit mask of DMMU_TABLE2 field. + DPORT_DMMU_TABLE2_DMMU_TABLE2_Msk = 0x7f + + // DMMU_TABLE3 + // Position of DMMU_TABLE3 field. + DPORT_DMMU_TABLE3_DMMU_TABLE3_Pos = 0x0 + // Bit mask of DMMU_TABLE3 field. + DPORT_DMMU_TABLE3_DMMU_TABLE3_Msk = 0x7f + + // DMMU_TABLE4 + // Position of DMMU_TABLE4 field. + DPORT_DMMU_TABLE4_DMMU_TABLE4_Pos = 0x0 + // Bit mask of DMMU_TABLE4 field. + DPORT_DMMU_TABLE4_DMMU_TABLE4_Msk = 0x7f + + // DMMU_TABLE5 + // Position of DMMU_TABLE5 field. + DPORT_DMMU_TABLE5_DMMU_TABLE5_Pos = 0x0 + // Bit mask of DMMU_TABLE5 field. + DPORT_DMMU_TABLE5_DMMU_TABLE5_Msk = 0x7f + + // DMMU_TABLE6 + // Position of DMMU_TABLE6 field. + DPORT_DMMU_TABLE6_DMMU_TABLE6_Pos = 0x0 + // Bit mask of DMMU_TABLE6 field. + DPORT_DMMU_TABLE6_DMMU_TABLE6_Msk = 0x7f + + // DMMU_TABLE7 + // Position of DMMU_TABLE7 field. + DPORT_DMMU_TABLE7_DMMU_TABLE7_Pos = 0x0 + // Bit mask of DMMU_TABLE7 field. + DPORT_DMMU_TABLE7_DMMU_TABLE7_Msk = 0x7f + + // DMMU_TABLE8 + // Position of DMMU_TABLE8 field. + DPORT_DMMU_TABLE8_DMMU_TABLE8_Pos = 0x0 + // Bit mask of DMMU_TABLE8 field. + DPORT_DMMU_TABLE8_DMMU_TABLE8_Msk = 0x7f + + // DMMU_TABLE9 + // Position of DMMU_TABLE9 field. + DPORT_DMMU_TABLE9_DMMU_TABLE9_Pos = 0x0 + // Bit mask of DMMU_TABLE9 field. + DPORT_DMMU_TABLE9_DMMU_TABLE9_Msk = 0x7f + + // DMMU_TABLE10 + // Position of DMMU_TABLE10 field. + DPORT_DMMU_TABLE10_DMMU_TABLE10_Pos = 0x0 + // Bit mask of DMMU_TABLE10 field. + DPORT_DMMU_TABLE10_DMMU_TABLE10_Msk = 0x7f + + // DMMU_TABLE11 + // Position of DMMU_TABLE11 field. + DPORT_DMMU_TABLE11_DMMU_TABLE11_Pos = 0x0 + // Bit mask of DMMU_TABLE11 field. + DPORT_DMMU_TABLE11_DMMU_TABLE11_Msk = 0x7f + + // DMMU_TABLE12 + // Position of DMMU_TABLE12 field. + DPORT_DMMU_TABLE12_DMMU_TABLE12_Pos = 0x0 + // Bit mask of DMMU_TABLE12 field. + DPORT_DMMU_TABLE12_DMMU_TABLE12_Msk = 0x7f + + // DMMU_TABLE13 + // Position of DMMU_TABLE13 field. + DPORT_DMMU_TABLE13_DMMU_TABLE13_Pos = 0x0 + // Bit mask of DMMU_TABLE13 field. + DPORT_DMMU_TABLE13_DMMU_TABLE13_Msk = 0x7f + + // DMMU_TABLE14 + // Position of DMMU_TABLE14 field. + DPORT_DMMU_TABLE14_DMMU_TABLE14_Pos = 0x0 + // Bit mask of DMMU_TABLE14 field. + DPORT_DMMU_TABLE14_DMMU_TABLE14_Msk = 0x7f + + // DMMU_TABLE15 + // Position of DMMU_TABLE15 field. + DPORT_DMMU_TABLE15_DMMU_TABLE15_Pos = 0x0 + // Bit mask of DMMU_TABLE15 field. + DPORT_DMMU_TABLE15_DMMU_TABLE15_Msk = 0x7f + + // PRO_INTRUSION_CTRL + // Position of PRO_INTRUSION_RECORD_RESET_N field. + DPORT_PRO_INTRUSION_CTRL_PRO_INTRUSION_RECORD_RESET_N_Pos = 0x0 + // Bit mask of PRO_INTRUSION_RECORD_RESET_N field. + DPORT_PRO_INTRUSION_CTRL_PRO_INTRUSION_RECORD_RESET_N_Msk = 0x1 + // Bit PRO_INTRUSION_RECORD_RESET_N. + DPORT_PRO_INTRUSION_CTRL_PRO_INTRUSION_RECORD_RESET_N = 0x1 + + // PRO_INTRUSION_STATUS + // Position of PRO_INTRUSION_RECORD field. + DPORT_PRO_INTRUSION_STATUS_PRO_INTRUSION_RECORD_Pos = 0x0 + // Bit mask of PRO_INTRUSION_RECORD field. + DPORT_PRO_INTRUSION_STATUS_PRO_INTRUSION_RECORD_Msk = 0xf + + // APP_INTRUSION_CTRL + // Position of APP_INTRUSION_RECORD_RESET_N field. + DPORT_APP_INTRUSION_CTRL_APP_INTRUSION_RECORD_RESET_N_Pos = 0x0 + // Bit mask of APP_INTRUSION_RECORD_RESET_N field. + DPORT_APP_INTRUSION_CTRL_APP_INTRUSION_RECORD_RESET_N_Msk = 0x1 + // Bit APP_INTRUSION_RECORD_RESET_N. + DPORT_APP_INTRUSION_CTRL_APP_INTRUSION_RECORD_RESET_N = 0x1 + + // APP_INTRUSION_STATUS + // Position of APP_INTRUSION_RECORD field. + DPORT_APP_INTRUSION_STATUS_APP_INTRUSION_RECORD_Pos = 0x0 + // Bit mask of APP_INTRUSION_RECORD field. + DPORT_APP_INTRUSION_STATUS_APP_INTRUSION_RECORD_Msk = 0xf + + // FRONT_END_MEM_PD + // Position of AGC_MEM_FORCE_PU field. + DPORT_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Pos = 0x0 + // Bit mask of AGC_MEM_FORCE_PU field. + DPORT_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Msk = 0x1 + // Bit AGC_MEM_FORCE_PU. + DPORT_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU = 0x1 + // Position of AGC_MEM_FORCE_PD field. + DPORT_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of AGC_MEM_FORCE_PD field. + DPORT_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Msk = 0x2 + // Bit AGC_MEM_FORCE_PD. + DPORT_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD = 0x2 + // Position of PBUS_MEM_FORCE_PU field. + DPORT_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of PBUS_MEM_FORCE_PU field. + DPORT_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Msk = 0x4 + // Bit PBUS_MEM_FORCE_PU. + DPORT_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU = 0x4 + // Position of PBUS_MEM_FORCE_PD field. + DPORT_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of PBUS_MEM_FORCE_PD field. + DPORT_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Msk = 0x8 + // Bit PBUS_MEM_FORCE_PD. + DPORT_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD = 0x8 + + // MMU_IA_INT_EN + // Position of MMU_IA_INT_EN field. + DPORT_MMU_IA_INT_EN_MMU_IA_INT_EN_Pos = 0x0 + // Bit mask of MMU_IA_INT_EN field. + DPORT_MMU_IA_INT_EN_MMU_IA_INT_EN_Msk = 0xffffff + + // MPU_IA_INT_EN + // Position of MPU_IA_INT_EN field. + DPORT_MPU_IA_INT_EN_MPU_IA_INT_EN_Pos = 0x0 + // Bit mask of MPU_IA_INT_EN field. + DPORT_MPU_IA_INT_EN_MPU_IA_INT_EN_Msk = 0x1ffff + + // CACHE_IA_INT_EN + // Position of CACHE_IA_INT_EN field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_EN_Pos = 0x0 + // Bit mask of CACHE_IA_INT_EN field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_EN_Msk = 0xfffffff + // Position of CACHE_IA_INT_APP_DROM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_DROM0_Pos = 0x0 + // Bit mask of CACHE_IA_INT_APP_DROM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_DROM0_Msk = 0x1 + // Bit CACHE_IA_INT_APP_DROM0. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_DROM0 = 0x1 + // Position of CACHE_IA_INT_APP_IRAM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM0_Pos = 0x1 + // Bit mask of CACHE_IA_INT_APP_IRAM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM0_Msk = 0x2 + // Bit CACHE_IA_INT_APP_IRAM0. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM0 = 0x2 + // Position of CACHE_IA_INT_APP_IRAM1 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM1_Pos = 0x2 + // Bit mask of CACHE_IA_INT_APP_IRAM1 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM1_Msk = 0x4 + // Bit CACHE_IA_INT_APP_IRAM1. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_IRAM1 = 0x4 + // Position of CACHE_IA_INT_APP_IROM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_IROM0_Pos = 0x3 + // Bit mask of CACHE_IA_INT_APP_IROM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_IROM0_Msk = 0x8 + // Bit CACHE_IA_INT_APP_IROM0. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_IROM0 = 0x8 + // Position of CACHE_IA_INT_APP_DRAM1 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_DRAM1_Pos = 0x4 + // Bit mask of CACHE_IA_INT_APP_DRAM1 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_DRAM1_Msk = 0x10 + // Bit CACHE_IA_INT_APP_DRAM1. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_DRAM1 = 0x10 + // Position of CACHE_IA_INT_APP_OPPOSITE field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_OPPOSITE_Pos = 0x5 + // Bit mask of CACHE_IA_INT_APP_OPPOSITE field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_OPPOSITE_Msk = 0x20 + // Bit CACHE_IA_INT_APP_OPPOSITE. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_APP_OPPOSITE = 0x20 + // Position of CACHE_IA_INT_PRO_DROM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_DROM0_Pos = 0xe + // Bit mask of CACHE_IA_INT_PRO_DROM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_DROM0_Msk = 0x4000 + // Bit CACHE_IA_INT_PRO_DROM0. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_DROM0 = 0x4000 + // Position of CACHE_IA_INT_PRO_IRAM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM0_Pos = 0xf + // Bit mask of CACHE_IA_INT_PRO_IRAM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM0_Msk = 0x8000 + // Bit CACHE_IA_INT_PRO_IRAM0. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM0 = 0x8000 + // Position of CACHE_IA_INT_PRO_IRAM1 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM1_Pos = 0x10 + // Bit mask of CACHE_IA_INT_PRO_IRAM1 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM1_Msk = 0x10000 + // Bit CACHE_IA_INT_PRO_IRAM1. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_IRAM1 = 0x10000 + // Position of CACHE_IA_INT_PRO_IROM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_IROM0_Pos = 0x11 + // Bit mask of CACHE_IA_INT_PRO_IROM0 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_IROM0_Msk = 0x20000 + // Bit CACHE_IA_INT_PRO_IROM0. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_IROM0 = 0x20000 + // Position of CACHE_IA_INT_PRO_DRAM1 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_DRAM1_Pos = 0x12 + // Bit mask of CACHE_IA_INT_PRO_DRAM1 field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_DRAM1_Msk = 0x40000 + // Bit CACHE_IA_INT_PRO_DRAM1. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_DRAM1 = 0x40000 + // Position of CACHE_IA_INT_PRO_OPPOSITE field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_OPPOSITE_Pos = 0x13 + // Bit mask of CACHE_IA_INT_PRO_OPPOSITE field. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_OPPOSITE_Msk = 0x80000 + // Bit CACHE_IA_INT_PRO_OPPOSITE. + DPORT_CACHE_IA_INT_EN_CACHE_IA_INT_PRO_OPPOSITE = 0x80000 + + // SECURE_BOOT_CTRL + // Position of SW_BOOTLOADER_SEL field. + DPORT_SECURE_BOOT_CTRL_SW_BOOTLOADER_SEL_Pos = 0x0 + // Bit mask of SW_BOOTLOADER_SEL field. + DPORT_SECURE_BOOT_CTRL_SW_BOOTLOADER_SEL_Msk = 0x1 + // Bit SW_BOOTLOADER_SEL. + DPORT_SECURE_BOOT_CTRL_SW_BOOTLOADER_SEL = 0x1 + + // SPI_DMA_CHAN_SEL + // Position of SPI1_DMA_CHAN_SEL field. + DPORT_SPI_DMA_CHAN_SEL_SPI1_DMA_CHAN_SEL_Pos = 0x0 + // Bit mask of SPI1_DMA_CHAN_SEL field. + DPORT_SPI_DMA_CHAN_SEL_SPI1_DMA_CHAN_SEL_Msk = 0x3 + // Position of SPI2_DMA_CHAN_SEL field. + DPORT_SPI_DMA_CHAN_SEL_SPI2_DMA_CHAN_SEL_Pos = 0x2 + // Bit mask of SPI2_DMA_CHAN_SEL field. + DPORT_SPI_DMA_CHAN_SEL_SPI2_DMA_CHAN_SEL_Msk = 0xc + // Position of SPI3_DMA_CHAN_SEL field. + DPORT_SPI_DMA_CHAN_SEL_SPI3_DMA_CHAN_SEL_Pos = 0x4 + // Bit mask of SPI3_DMA_CHAN_SEL field. + DPORT_SPI_DMA_CHAN_SEL_SPI3_DMA_CHAN_SEL_Msk = 0x30 + + // PRO_VECBASE_CTRL + // Position of PRO_OUT_VECBASE_SEL field. + DPORT_PRO_VECBASE_CTRL_PRO_OUT_VECBASE_SEL_Pos = 0x0 + // Bit mask of PRO_OUT_VECBASE_SEL field. + DPORT_PRO_VECBASE_CTRL_PRO_OUT_VECBASE_SEL_Msk = 0x3 + + // PRO_VECBASE_SET + // Position of PRO_OUT_VECBASE field. + DPORT_PRO_VECBASE_SET_PRO_OUT_VECBASE_Pos = 0x0 + // Bit mask of PRO_OUT_VECBASE field. + DPORT_PRO_VECBASE_SET_PRO_OUT_VECBASE_Msk = 0x3fffff + + // APP_VECBASE_CTRL + // Position of APP_OUT_VECBASE_SEL field. + DPORT_APP_VECBASE_CTRL_APP_OUT_VECBASE_SEL_Pos = 0x0 + // Bit mask of APP_OUT_VECBASE_SEL field. + DPORT_APP_VECBASE_CTRL_APP_OUT_VECBASE_SEL_Msk = 0x3 + + // APP_VECBASE_SET + // Position of APP_OUT_VECBASE field. + DPORT_APP_VECBASE_SET_APP_OUT_VECBASE_Pos = 0x0 + // Bit mask of APP_OUT_VECBASE field. + DPORT_APP_VECBASE_SET_APP_OUT_VECBASE_Msk = 0x3fffff + + // DATE + // Position of DATE field. + DPORT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DPORT_DATE_DATE_Msk = 0xfffffff +) + +// Constants for EFUSE: eFuse Controller +const ( + // BLK0_RDATA0 + // Position of RD_EFUSE_WR_DIS field. + EFUSE_BLK0_RDATA0_RD_EFUSE_WR_DIS_Pos = 0x0 + // Bit mask of RD_EFUSE_WR_DIS field. + EFUSE_BLK0_RDATA0_RD_EFUSE_WR_DIS_Msk = 0xffff + // Position of RD_EFUSE_RD_DIS field. + EFUSE_BLK0_RDATA0_RD_EFUSE_RD_DIS_Pos = 0x10 + // Bit mask of RD_EFUSE_RD_DIS field. + EFUSE_BLK0_RDATA0_RD_EFUSE_RD_DIS_Msk = 0xf0000 + // Position of RD_FLASH_CRYPT_CNT field. + EFUSE_BLK0_RDATA0_RD_FLASH_CRYPT_CNT_Pos = 0x14 + // Bit mask of RD_FLASH_CRYPT_CNT field. + EFUSE_BLK0_RDATA0_RD_FLASH_CRYPT_CNT_Msk = 0x7f00000 + // Position of RD_UART_DOWNLOAD_DIS field. + EFUSE_BLK0_RDATA0_RD_UART_DOWNLOAD_DIS_Pos = 0x1b + // Bit mask of RD_UART_DOWNLOAD_DIS field. + EFUSE_BLK0_RDATA0_RD_UART_DOWNLOAD_DIS_Msk = 0x8000000 + // Bit RD_UART_DOWNLOAD_DIS. + EFUSE_BLK0_RDATA0_RD_UART_DOWNLOAD_DIS = 0x8000000 + // Position of RESERVED_0_28 field. + EFUSE_BLK0_RDATA0_RESERVED_0_28_Pos = 0x1c + // Bit mask of RESERVED_0_28 field. + EFUSE_BLK0_RDATA0_RESERVED_0_28_Msk = 0xf0000000 + + // BLK0_RDATA1 + // Position of RD_MAC field. + EFUSE_BLK0_RDATA1_RD_MAC_Pos = 0x0 + // Bit mask of RD_MAC field. + EFUSE_BLK0_RDATA1_RD_MAC_Msk = 0xffffffff + + // BLK0_RDATA2 + // Position of RD_MAC_1 field. + EFUSE_BLK0_RDATA2_RD_MAC_1_Pos = 0x0 + // Bit mask of RD_MAC_1 field. + EFUSE_BLK0_RDATA2_RD_MAC_1_Msk = 0xffff + // Position of RD_MAC_CRC field. + EFUSE_BLK0_RDATA2_RD_MAC_CRC_Pos = 0x10 + // Bit mask of RD_MAC_CRC field. + EFUSE_BLK0_RDATA2_RD_MAC_CRC_Msk = 0xff0000 + // Position of RD_RESERVE_0_88 field. + EFUSE_BLK0_RDATA2_RD_RESERVE_0_88_Pos = 0x18 + // Bit mask of RD_RESERVE_0_88 field. + EFUSE_BLK0_RDATA2_RD_RESERVE_0_88_Msk = 0xff000000 + + // BLK0_RDATA3 + // Position of RD_DISABLE_APP_CPU field. + EFUSE_BLK0_RDATA3_RD_DISABLE_APP_CPU_Pos = 0x0 + // Bit mask of RD_DISABLE_APP_CPU field. + EFUSE_BLK0_RDATA3_RD_DISABLE_APP_CPU_Msk = 0x1 + // Bit RD_DISABLE_APP_CPU. + EFUSE_BLK0_RDATA3_RD_DISABLE_APP_CPU = 0x1 + // Position of RD_DISABLE_BT field. + EFUSE_BLK0_RDATA3_RD_DISABLE_BT_Pos = 0x1 + // Bit mask of RD_DISABLE_BT field. + EFUSE_BLK0_RDATA3_RD_DISABLE_BT_Msk = 0x2 + // Bit RD_DISABLE_BT. + EFUSE_BLK0_RDATA3_RD_DISABLE_BT = 0x2 + // Position of RD_CHIP_PACKAGE_4BIT field. + EFUSE_BLK0_RDATA3_RD_CHIP_PACKAGE_4BIT_Pos = 0x2 + // Bit mask of RD_CHIP_PACKAGE_4BIT field. + EFUSE_BLK0_RDATA3_RD_CHIP_PACKAGE_4BIT_Msk = 0x4 + // Bit RD_CHIP_PACKAGE_4BIT. + EFUSE_BLK0_RDATA3_RD_CHIP_PACKAGE_4BIT = 0x4 + // Position of RD_DIS_CACHE field. + EFUSE_BLK0_RDATA3_RD_DIS_CACHE_Pos = 0x3 + // Bit mask of RD_DIS_CACHE field. + EFUSE_BLK0_RDATA3_RD_DIS_CACHE_Msk = 0x8 + // Bit RD_DIS_CACHE. + EFUSE_BLK0_RDATA3_RD_DIS_CACHE = 0x8 + // Position of RD_SPI_PAD_CONFIG_HD field. + EFUSE_BLK0_RDATA3_RD_SPI_PAD_CONFIG_HD_Pos = 0x4 + // Bit mask of RD_SPI_PAD_CONFIG_HD field. + EFUSE_BLK0_RDATA3_RD_SPI_PAD_CONFIG_HD_Msk = 0x1f0 + // Position of RD_CHIP_PACKAGE field. + EFUSE_BLK0_RDATA3_RD_CHIP_PACKAGE_Pos = 0x9 + // Bit mask of RD_CHIP_PACKAGE field. + EFUSE_BLK0_RDATA3_RD_CHIP_PACKAGE_Msk = 0xe00 + // Position of RD_CHIP_CPU_FREQ_LOW field. + EFUSE_BLK0_RDATA3_RD_CHIP_CPU_FREQ_LOW_Pos = 0xc + // Bit mask of RD_CHIP_CPU_FREQ_LOW field. + EFUSE_BLK0_RDATA3_RD_CHIP_CPU_FREQ_LOW_Msk = 0x1000 + // Bit RD_CHIP_CPU_FREQ_LOW. + EFUSE_BLK0_RDATA3_RD_CHIP_CPU_FREQ_LOW = 0x1000 + // Position of RD_CHIP_CPU_FREQ_RATED field. + EFUSE_BLK0_RDATA3_RD_CHIP_CPU_FREQ_RATED_Pos = 0xd + // Bit mask of RD_CHIP_CPU_FREQ_RATED field. + EFUSE_BLK0_RDATA3_RD_CHIP_CPU_FREQ_RATED_Msk = 0x2000 + // Bit RD_CHIP_CPU_FREQ_RATED. + EFUSE_BLK0_RDATA3_RD_CHIP_CPU_FREQ_RATED = 0x2000 + // Position of RD_BLK3_PART_RESERVE field. + EFUSE_BLK0_RDATA3_RD_BLK3_PART_RESERVE_Pos = 0xe + // Bit mask of RD_BLK3_PART_RESERVE field. + EFUSE_BLK0_RDATA3_RD_BLK3_PART_RESERVE_Msk = 0x4000 + // Bit RD_BLK3_PART_RESERVE. + EFUSE_BLK0_RDATA3_RD_BLK3_PART_RESERVE = 0x4000 + // Position of RD_CHIP_VER_REV1 field. + EFUSE_BLK0_RDATA3_RD_CHIP_VER_REV1_Pos = 0xf + // Bit mask of RD_CHIP_VER_REV1 field. + EFUSE_BLK0_RDATA3_RD_CHIP_VER_REV1_Msk = 0x8000 + // Bit RD_CHIP_VER_REV1. + EFUSE_BLK0_RDATA3_RD_CHIP_VER_REV1 = 0x8000 + // Position of RD_RESERVE_0_112 field. + EFUSE_BLK0_RDATA3_RD_RESERVE_0_112_Pos = 0x10 + // Bit mask of RD_RESERVE_0_112 field. + EFUSE_BLK0_RDATA3_RD_RESERVE_0_112_Msk = 0xffff0000 + + // BLK0_RDATA4 + // Position of RD_CLK8M_FREQ field. + EFUSE_BLK0_RDATA4_RD_CLK8M_FREQ_Pos = 0x0 + // Bit mask of RD_CLK8M_FREQ field. + EFUSE_BLK0_RDATA4_RD_CLK8M_FREQ_Msk = 0xff + // Position of RD_ADC_VREF field. + EFUSE_BLK0_RDATA4_RD_ADC_VREF_Pos = 0x8 + // Bit mask of RD_ADC_VREF field. + EFUSE_BLK0_RDATA4_RD_ADC_VREF_Msk = 0x1f00 + // Position of RD_RESERVE_0_141 field. + EFUSE_BLK0_RDATA4_RD_RESERVE_0_141_Pos = 0xd + // Bit mask of RD_RESERVE_0_141 field. + EFUSE_BLK0_RDATA4_RD_RESERVE_0_141_Msk = 0x2000 + // Bit RD_RESERVE_0_141. + EFUSE_BLK0_RDATA4_RD_RESERVE_0_141 = 0x2000 + // Position of RD_XPD_SDIO field. + EFUSE_BLK0_RDATA4_RD_XPD_SDIO_Pos = 0xe + // Bit mask of RD_XPD_SDIO field. + EFUSE_BLK0_RDATA4_RD_XPD_SDIO_Msk = 0x4000 + // Bit RD_XPD_SDIO. + EFUSE_BLK0_RDATA4_RD_XPD_SDIO = 0x4000 + // Position of RD_XPD_SDIO_TIEH field. + EFUSE_BLK0_RDATA4_RD_XPD_SDIO_TIEH_Pos = 0xf + // Bit mask of RD_XPD_SDIO_TIEH field. + EFUSE_BLK0_RDATA4_RD_XPD_SDIO_TIEH_Msk = 0x8000 + // Bit RD_XPD_SDIO_TIEH. + EFUSE_BLK0_RDATA4_RD_XPD_SDIO_TIEH = 0x8000 + // Position of RD_XPD_SDIO_FORCE field. + EFUSE_BLK0_RDATA4_RD_XPD_SDIO_FORCE_Pos = 0x10 + // Bit mask of RD_XPD_SDIO_FORCE field. + EFUSE_BLK0_RDATA4_RD_XPD_SDIO_FORCE_Msk = 0x10000 + // Bit RD_XPD_SDIO_FORCE. + EFUSE_BLK0_RDATA4_RD_XPD_SDIO_FORCE = 0x10000 + // Position of RD_RESERVE_0_145 field. + EFUSE_BLK0_RDATA4_RD_RESERVE_0_145_Pos = 0x11 + // Bit mask of RD_RESERVE_0_145 field. + EFUSE_BLK0_RDATA4_RD_RESERVE_0_145_Msk = 0xfffe0000 + + // BLK0_RDATA5 + // Position of RD_SPI_PAD_CONFIG_CLK field. + EFUSE_BLK0_RDATA5_RD_SPI_PAD_CONFIG_CLK_Pos = 0x0 + // Bit mask of RD_SPI_PAD_CONFIG_CLK field. + EFUSE_BLK0_RDATA5_RD_SPI_PAD_CONFIG_CLK_Msk = 0x1f + // Position of RD_SPI_PAD_CONFIG_Q field. + EFUSE_BLK0_RDATA5_RD_SPI_PAD_CONFIG_Q_Pos = 0x5 + // Bit mask of RD_SPI_PAD_CONFIG_Q field. + EFUSE_BLK0_RDATA5_RD_SPI_PAD_CONFIG_Q_Msk = 0x3e0 + // Position of RD_SPI_PAD_CONFIG_D field. + EFUSE_BLK0_RDATA5_RD_SPI_PAD_CONFIG_D_Pos = 0xa + // Bit mask of RD_SPI_PAD_CONFIG_D field. + EFUSE_BLK0_RDATA5_RD_SPI_PAD_CONFIG_D_Msk = 0x7c00 + // Position of RD_SPI_PAD_CONFIG_CS0 field. + EFUSE_BLK0_RDATA5_RD_SPI_PAD_CONFIG_CS0_Pos = 0xf + // Bit mask of RD_SPI_PAD_CONFIG_CS0 field. + EFUSE_BLK0_RDATA5_RD_SPI_PAD_CONFIG_CS0_Msk = 0xf8000 + // Position of RD_CHIP_VER_REV2 field. + EFUSE_BLK0_RDATA5_RD_CHIP_VER_REV2_Pos = 0x14 + // Bit mask of RD_CHIP_VER_REV2 field. + EFUSE_BLK0_RDATA5_RD_CHIP_VER_REV2_Msk = 0x100000 + // Bit RD_CHIP_VER_REV2. + EFUSE_BLK0_RDATA5_RD_CHIP_VER_REV2 = 0x100000 + // Position of RD_RESERVE_0_181 field. + EFUSE_BLK0_RDATA5_RD_RESERVE_0_181_Pos = 0x15 + // Bit mask of RD_RESERVE_0_181 field. + EFUSE_BLK0_RDATA5_RD_RESERVE_0_181_Msk = 0x200000 + // Bit RD_RESERVE_0_181. + EFUSE_BLK0_RDATA5_RD_RESERVE_0_181 = 0x200000 + // Position of RD_VOL_LEVEL_HP_INV field. + EFUSE_BLK0_RDATA5_RD_VOL_LEVEL_HP_INV_Pos = 0x16 + // Bit mask of RD_VOL_LEVEL_HP_INV field. + EFUSE_BLK0_RDATA5_RD_VOL_LEVEL_HP_INV_Msk = 0xc00000 + // Position of RD_WAFER_VERSION_MINOR field. + EFUSE_BLK0_RDATA5_RD_WAFER_VERSION_MINOR_Pos = 0x18 + // Bit mask of RD_WAFER_VERSION_MINOR field. + EFUSE_BLK0_RDATA5_RD_WAFER_VERSION_MINOR_Msk = 0x3000000 + // Position of RD_RESERVE_0_186 field. + EFUSE_BLK0_RDATA5_RD_RESERVE_0_186_Pos = 0x1a + // Bit mask of RD_RESERVE_0_186 field. + EFUSE_BLK0_RDATA5_RD_RESERVE_0_186_Msk = 0xc000000 + // Position of RD_FLASH_CRYPT_CONFIG field. + EFUSE_BLK0_RDATA5_RD_FLASH_CRYPT_CONFIG_Pos = 0x1c + // Bit mask of RD_FLASH_CRYPT_CONFIG field. + EFUSE_BLK0_RDATA5_RD_FLASH_CRYPT_CONFIG_Msk = 0xf0000000 + + // BLK0_RDATA6 + // Position of RD_CODING_SCHEME field. + EFUSE_BLK0_RDATA6_RD_CODING_SCHEME_Pos = 0x0 + // Bit mask of RD_CODING_SCHEME field. + EFUSE_BLK0_RDATA6_RD_CODING_SCHEME_Msk = 0x3 + // Position of RD_CONSOLE_DEBUG_DISABLE field. + EFUSE_BLK0_RDATA6_RD_CONSOLE_DEBUG_DISABLE_Pos = 0x2 + // Bit mask of RD_CONSOLE_DEBUG_DISABLE field. + EFUSE_BLK0_RDATA6_RD_CONSOLE_DEBUG_DISABLE_Msk = 0x4 + // Bit RD_CONSOLE_DEBUG_DISABLE. + EFUSE_BLK0_RDATA6_RD_CONSOLE_DEBUG_DISABLE = 0x4 + // Position of RD_DISABLE_SDIO_HOST field. + EFUSE_BLK0_RDATA6_RD_DISABLE_SDIO_HOST_Pos = 0x3 + // Bit mask of RD_DISABLE_SDIO_HOST field. + EFUSE_BLK0_RDATA6_RD_DISABLE_SDIO_HOST_Msk = 0x8 + // Bit RD_DISABLE_SDIO_HOST. + EFUSE_BLK0_RDATA6_RD_DISABLE_SDIO_HOST = 0x8 + // Position of RD_ABS_DONE_0 field. + EFUSE_BLK0_RDATA6_RD_ABS_DONE_0_Pos = 0x4 + // Bit mask of RD_ABS_DONE_0 field. + EFUSE_BLK0_RDATA6_RD_ABS_DONE_0_Msk = 0x10 + // Bit RD_ABS_DONE_0. + EFUSE_BLK0_RDATA6_RD_ABS_DONE_0 = 0x10 + // Position of RD_ABS_DONE_1 field. + EFUSE_BLK0_RDATA6_RD_ABS_DONE_1_Pos = 0x5 + // Bit mask of RD_ABS_DONE_1 field. + EFUSE_BLK0_RDATA6_RD_ABS_DONE_1_Msk = 0x20 + // Bit RD_ABS_DONE_1. + EFUSE_BLK0_RDATA6_RD_ABS_DONE_1 = 0x20 + // Position of RD_JTAG_DISABLE field. + EFUSE_BLK0_RDATA6_RD_JTAG_DISABLE_Pos = 0x6 + // Bit mask of RD_JTAG_DISABLE field. + EFUSE_BLK0_RDATA6_RD_JTAG_DISABLE_Msk = 0x40 + // Bit RD_JTAG_DISABLE. + EFUSE_BLK0_RDATA6_RD_JTAG_DISABLE = 0x40 + // Position of RD_DISABLE_DL_ENCRYPT field. + EFUSE_BLK0_RDATA6_RD_DISABLE_DL_ENCRYPT_Pos = 0x7 + // Bit mask of RD_DISABLE_DL_ENCRYPT field. + EFUSE_BLK0_RDATA6_RD_DISABLE_DL_ENCRYPT_Msk = 0x80 + // Bit RD_DISABLE_DL_ENCRYPT. + EFUSE_BLK0_RDATA6_RD_DISABLE_DL_ENCRYPT = 0x80 + // Position of RD_DISABLE_DL_DECRYPT field. + EFUSE_BLK0_RDATA6_RD_DISABLE_DL_DECRYPT_Pos = 0x8 + // Bit mask of RD_DISABLE_DL_DECRYPT field. + EFUSE_BLK0_RDATA6_RD_DISABLE_DL_DECRYPT_Msk = 0x100 + // Bit RD_DISABLE_DL_DECRYPT. + EFUSE_BLK0_RDATA6_RD_DISABLE_DL_DECRYPT = 0x100 + // Position of RD_DISABLE_DL_CACHE field. + EFUSE_BLK0_RDATA6_RD_DISABLE_DL_CACHE_Pos = 0x9 + // Bit mask of RD_DISABLE_DL_CACHE field. + EFUSE_BLK0_RDATA6_RD_DISABLE_DL_CACHE_Msk = 0x200 + // Bit RD_DISABLE_DL_CACHE. + EFUSE_BLK0_RDATA6_RD_DISABLE_DL_CACHE = 0x200 + // Position of RD_KEY_STATUS field. + EFUSE_BLK0_RDATA6_RD_KEY_STATUS_Pos = 0xa + // Bit mask of RD_KEY_STATUS field. + EFUSE_BLK0_RDATA6_RD_KEY_STATUS_Msk = 0x400 + // Bit RD_KEY_STATUS. + EFUSE_BLK0_RDATA6_RD_KEY_STATUS = 0x400 + // Position of RD_RESERVE_0_203 field. + EFUSE_BLK0_RDATA6_RD_RESERVE_0_203_Pos = 0xb + // Bit mask of RD_RESERVE_0_203 field. + EFUSE_BLK0_RDATA6_RD_RESERVE_0_203_Msk = 0xfffff800 + + // BLK0_WDATA0 + // Position of WR_DIS field. + EFUSE_BLK0_WDATA0_WR_DIS_Pos = 0x0 + // Bit mask of WR_DIS field. + EFUSE_BLK0_WDATA0_WR_DIS_Msk = 0xffff + // Position of RD_DIS field. + EFUSE_BLK0_WDATA0_RD_DIS_Pos = 0x10 + // Bit mask of RD_DIS field. + EFUSE_BLK0_WDATA0_RD_DIS_Msk = 0xf0000 + // Position of FLASH_CRYPT_CNT field. + EFUSE_BLK0_WDATA0_FLASH_CRYPT_CNT_Pos = 0x14 + // Bit mask of FLASH_CRYPT_CNT field. + EFUSE_BLK0_WDATA0_FLASH_CRYPT_CNT_Msk = 0x7f00000 + + // BLK0_WDATA1 + // Position of WIFI_MAC_CRC_LOW field. + EFUSE_BLK0_WDATA1_WIFI_MAC_CRC_LOW_Pos = 0x0 + // Bit mask of WIFI_MAC_CRC_LOW field. + EFUSE_BLK0_WDATA1_WIFI_MAC_CRC_LOW_Msk = 0xffffffff + + // BLK0_WDATA2 + // Position of WIFI_MAC_CRC_HIGH field. + EFUSE_BLK0_WDATA2_WIFI_MAC_CRC_HIGH_Pos = 0x0 + // Bit mask of WIFI_MAC_CRC_HIGH field. + EFUSE_BLK0_WDATA2_WIFI_MAC_CRC_HIGH_Msk = 0xffffff + + // BLK0_WDATA3 + // Position of DISABLE_APP_CPU field. + EFUSE_BLK0_WDATA3_DISABLE_APP_CPU_Pos = 0x0 + // Bit mask of DISABLE_APP_CPU field. + EFUSE_BLK0_WDATA3_DISABLE_APP_CPU_Msk = 0x1 + // Bit DISABLE_APP_CPU. + EFUSE_BLK0_WDATA3_DISABLE_APP_CPU = 0x1 + // Position of DISABLE_BT field. + EFUSE_BLK0_WDATA3_DISABLE_BT_Pos = 0x1 + // Bit mask of DISABLE_BT field. + EFUSE_BLK0_WDATA3_DISABLE_BT_Msk = 0x2 + // Bit DISABLE_BT. + EFUSE_BLK0_WDATA3_DISABLE_BT = 0x2 + // Position of CHIP_PACKAGE_4BIT field. + EFUSE_BLK0_WDATA3_CHIP_PACKAGE_4BIT_Pos = 0x2 + // Bit mask of CHIP_PACKAGE_4BIT field. + EFUSE_BLK0_WDATA3_CHIP_PACKAGE_4BIT_Msk = 0x4 + // Bit CHIP_PACKAGE_4BIT. + EFUSE_BLK0_WDATA3_CHIP_PACKAGE_4BIT = 0x4 + // Position of DIS_CACHE field. + EFUSE_BLK0_WDATA3_DIS_CACHE_Pos = 0x3 + // Bit mask of DIS_CACHE field. + EFUSE_BLK0_WDATA3_DIS_CACHE_Msk = 0x8 + // Bit DIS_CACHE. + EFUSE_BLK0_WDATA3_DIS_CACHE = 0x8 + // Position of SPI_PAD_CONFIG_HD field. + EFUSE_BLK0_WDATA3_SPI_PAD_CONFIG_HD_Pos = 0x4 + // Bit mask of SPI_PAD_CONFIG_HD field. + EFUSE_BLK0_WDATA3_SPI_PAD_CONFIG_HD_Msk = 0x1f0 + // Position of CHIP_PACKAGE field. + EFUSE_BLK0_WDATA3_CHIP_PACKAGE_Pos = 0x9 + // Bit mask of CHIP_PACKAGE field. + EFUSE_BLK0_WDATA3_CHIP_PACKAGE_Msk = 0xe00 + // Position of CHIP_CPU_FREQ_LOW field. + EFUSE_BLK0_WDATA3_CHIP_CPU_FREQ_LOW_Pos = 0xc + // Bit mask of CHIP_CPU_FREQ_LOW field. + EFUSE_BLK0_WDATA3_CHIP_CPU_FREQ_LOW_Msk = 0x1000 + // Bit CHIP_CPU_FREQ_LOW. + EFUSE_BLK0_WDATA3_CHIP_CPU_FREQ_LOW = 0x1000 + // Position of CHIP_CPU_FREQ_RATED field. + EFUSE_BLK0_WDATA3_CHIP_CPU_FREQ_RATED_Pos = 0xd + // Bit mask of CHIP_CPU_FREQ_RATED field. + EFUSE_BLK0_WDATA3_CHIP_CPU_FREQ_RATED_Msk = 0x2000 + // Bit CHIP_CPU_FREQ_RATED. + EFUSE_BLK0_WDATA3_CHIP_CPU_FREQ_RATED = 0x2000 + // Position of BLK3_PART_RESERVE field. + EFUSE_BLK0_WDATA3_BLK3_PART_RESERVE_Pos = 0xe + // Bit mask of BLK3_PART_RESERVE field. + EFUSE_BLK0_WDATA3_BLK3_PART_RESERVE_Msk = 0x4000 + // Bit BLK3_PART_RESERVE. + EFUSE_BLK0_WDATA3_BLK3_PART_RESERVE = 0x4000 + // Position of CHIP_VER_REV1 field. + EFUSE_BLK0_WDATA3_CHIP_VER_REV1_Pos = 0xf + // Bit mask of CHIP_VER_REV1 field. + EFUSE_BLK0_WDATA3_CHIP_VER_REV1_Msk = 0x8000 + // Bit CHIP_VER_REV1. + EFUSE_BLK0_WDATA3_CHIP_VER_REV1 = 0x8000 + // Position of RESERVE_0_112 field. + EFUSE_BLK0_WDATA3_RESERVE_0_112_Pos = 0x10 + // Bit mask of RESERVE_0_112 field. + EFUSE_BLK0_WDATA3_RESERVE_0_112_Msk = 0xffff0000 + + // BLK0_WDATA4 + // Position of CLK8M_FREQ field. + EFUSE_BLK0_WDATA4_CLK8M_FREQ_Pos = 0x0 + // Bit mask of CLK8M_FREQ field. + EFUSE_BLK0_WDATA4_CLK8M_FREQ_Msk = 0xff + // Position of ADC_VREF field. + EFUSE_BLK0_WDATA4_ADC_VREF_Pos = 0x8 + // Bit mask of ADC_VREF field. + EFUSE_BLK0_WDATA4_ADC_VREF_Msk = 0x1f00 + // Position of RESERVE_0_141 field. + EFUSE_BLK0_WDATA4_RESERVE_0_141_Pos = 0xd + // Bit mask of RESERVE_0_141 field. + EFUSE_BLK0_WDATA4_RESERVE_0_141_Msk = 0x2000 + // Bit RESERVE_0_141. + EFUSE_BLK0_WDATA4_RESERVE_0_141 = 0x2000 + // Position of XPD_SDIO field. + EFUSE_BLK0_WDATA4_XPD_SDIO_Pos = 0xe + // Bit mask of XPD_SDIO field. + EFUSE_BLK0_WDATA4_XPD_SDIO_Msk = 0x4000 + // Bit XPD_SDIO. + EFUSE_BLK0_WDATA4_XPD_SDIO = 0x4000 + // Position of XPD_SDIO_TIEH field. + EFUSE_BLK0_WDATA4_XPD_SDIO_TIEH_Pos = 0xf + // Bit mask of XPD_SDIO_TIEH field. + EFUSE_BLK0_WDATA4_XPD_SDIO_TIEH_Msk = 0x8000 + // Bit XPD_SDIO_TIEH. + EFUSE_BLK0_WDATA4_XPD_SDIO_TIEH = 0x8000 + // Position of XPD_SDIO_FORCE field. + EFUSE_BLK0_WDATA4_XPD_SDIO_FORCE_Pos = 0x10 + // Bit mask of XPD_SDIO_FORCE field. + EFUSE_BLK0_WDATA4_XPD_SDIO_FORCE_Msk = 0x10000 + // Bit XPD_SDIO_FORCE. + EFUSE_BLK0_WDATA4_XPD_SDIO_FORCE = 0x10000 + // Position of RESERVE_0_145 field. + EFUSE_BLK0_WDATA4_RESERVE_0_145_Pos = 0x11 + // Bit mask of RESERVE_0_145 field. + EFUSE_BLK0_WDATA4_RESERVE_0_145_Msk = 0xfffe0000 + + // BLK0_WDATA5 + // Position of SPI_PAD_CONFIG_CLK field. + EFUSE_BLK0_WDATA5_SPI_PAD_CONFIG_CLK_Pos = 0x0 + // Bit mask of SPI_PAD_CONFIG_CLK field. + EFUSE_BLK0_WDATA5_SPI_PAD_CONFIG_CLK_Msk = 0x1f + // Position of SPI_PAD_CONFIG_Q field. + EFUSE_BLK0_WDATA5_SPI_PAD_CONFIG_Q_Pos = 0x5 + // Bit mask of SPI_PAD_CONFIG_Q field. + EFUSE_BLK0_WDATA5_SPI_PAD_CONFIG_Q_Msk = 0x3e0 + // Position of SPI_PAD_CONFIG_D field. + EFUSE_BLK0_WDATA5_SPI_PAD_CONFIG_D_Pos = 0xa + // Bit mask of SPI_PAD_CONFIG_D field. + EFUSE_BLK0_WDATA5_SPI_PAD_CONFIG_D_Msk = 0x7c00 + // Position of SPI_PAD_CONFIG_CS0 field. + EFUSE_BLK0_WDATA5_SPI_PAD_CONFIG_CS0_Pos = 0xf + // Bit mask of SPI_PAD_CONFIG_CS0 field. + EFUSE_BLK0_WDATA5_SPI_PAD_CONFIG_CS0_Msk = 0xf8000 + // Position of CHIP_VER_REV2 field. + EFUSE_BLK0_WDATA5_CHIP_VER_REV2_Pos = 0x14 + // Bit mask of CHIP_VER_REV2 field. + EFUSE_BLK0_WDATA5_CHIP_VER_REV2_Msk = 0x100000 + // Bit CHIP_VER_REV2. + EFUSE_BLK0_WDATA5_CHIP_VER_REV2 = 0x100000 + // Position of RESERVE_0_181 field. + EFUSE_BLK0_WDATA5_RESERVE_0_181_Pos = 0x15 + // Bit mask of RESERVE_0_181 field. + EFUSE_BLK0_WDATA5_RESERVE_0_181_Msk = 0x200000 + // Bit RESERVE_0_181. + EFUSE_BLK0_WDATA5_RESERVE_0_181 = 0x200000 + // Position of VOL_LEVEL_HP_INV field. + EFUSE_BLK0_WDATA5_VOL_LEVEL_HP_INV_Pos = 0x16 + // Bit mask of VOL_LEVEL_HP_INV field. + EFUSE_BLK0_WDATA5_VOL_LEVEL_HP_INV_Msk = 0xc00000 + // Position of WAFER_VERSION_MINOR field. + EFUSE_BLK0_WDATA5_WAFER_VERSION_MINOR_Pos = 0x18 + // Bit mask of WAFER_VERSION_MINOR field. + EFUSE_BLK0_WDATA5_WAFER_VERSION_MINOR_Msk = 0x3000000 + // Position of RESERVE_0_186 field. + EFUSE_BLK0_WDATA5_RESERVE_0_186_Pos = 0x1a + // Bit mask of RESERVE_0_186 field. + EFUSE_BLK0_WDATA5_RESERVE_0_186_Msk = 0xc000000 + // Position of FLASH_CRYPT_CONFIG field. + EFUSE_BLK0_WDATA5_FLASH_CRYPT_CONFIG_Pos = 0x1c + // Bit mask of FLASH_CRYPT_CONFIG field. + EFUSE_BLK0_WDATA5_FLASH_CRYPT_CONFIG_Msk = 0xf0000000 + + // BLK0_WDATA6 + // Position of CODING_SCHEME field. + EFUSE_BLK0_WDATA6_CODING_SCHEME_Pos = 0x0 + // Bit mask of CODING_SCHEME field. + EFUSE_BLK0_WDATA6_CODING_SCHEME_Msk = 0x3 + // Position of CONSOLE_DEBUG_DISABLE field. + EFUSE_BLK0_WDATA6_CONSOLE_DEBUG_DISABLE_Pos = 0x2 + // Bit mask of CONSOLE_DEBUG_DISABLE field. + EFUSE_BLK0_WDATA6_CONSOLE_DEBUG_DISABLE_Msk = 0x4 + // Bit CONSOLE_DEBUG_DISABLE. + EFUSE_BLK0_WDATA6_CONSOLE_DEBUG_DISABLE = 0x4 + // Position of DISABLE_SDIO_HOST field. + EFUSE_BLK0_WDATA6_DISABLE_SDIO_HOST_Pos = 0x3 + // Bit mask of DISABLE_SDIO_HOST field. + EFUSE_BLK0_WDATA6_DISABLE_SDIO_HOST_Msk = 0x8 + // Bit DISABLE_SDIO_HOST. + EFUSE_BLK0_WDATA6_DISABLE_SDIO_HOST = 0x8 + // Position of ABS_DONE_0 field. + EFUSE_BLK0_WDATA6_ABS_DONE_0_Pos = 0x4 + // Bit mask of ABS_DONE_0 field. + EFUSE_BLK0_WDATA6_ABS_DONE_0_Msk = 0x10 + // Bit ABS_DONE_0. + EFUSE_BLK0_WDATA6_ABS_DONE_0 = 0x10 + // Position of ABS_DONE_1 field. + EFUSE_BLK0_WDATA6_ABS_DONE_1_Pos = 0x5 + // Bit mask of ABS_DONE_1 field. + EFUSE_BLK0_WDATA6_ABS_DONE_1_Msk = 0x20 + // Bit ABS_DONE_1. + EFUSE_BLK0_WDATA6_ABS_DONE_1 = 0x20 + // Position of DISABLE_JTAG field. + EFUSE_BLK0_WDATA6_DISABLE_JTAG_Pos = 0x6 + // Bit mask of DISABLE_JTAG field. + EFUSE_BLK0_WDATA6_DISABLE_JTAG_Msk = 0x40 + // Bit DISABLE_JTAG. + EFUSE_BLK0_WDATA6_DISABLE_JTAG = 0x40 + // Position of DISABLE_DL_ENCRYPT field. + EFUSE_BLK0_WDATA6_DISABLE_DL_ENCRYPT_Pos = 0x7 + // Bit mask of DISABLE_DL_ENCRYPT field. + EFUSE_BLK0_WDATA6_DISABLE_DL_ENCRYPT_Msk = 0x80 + // Bit DISABLE_DL_ENCRYPT. + EFUSE_BLK0_WDATA6_DISABLE_DL_ENCRYPT = 0x80 + // Position of DISABLE_DL_DECRYPT field. + EFUSE_BLK0_WDATA6_DISABLE_DL_DECRYPT_Pos = 0x8 + // Bit mask of DISABLE_DL_DECRYPT field. + EFUSE_BLK0_WDATA6_DISABLE_DL_DECRYPT_Msk = 0x100 + // Bit DISABLE_DL_DECRYPT. + EFUSE_BLK0_WDATA6_DISABLE_DL_DECRYPT = 0x100 + // Position of DISABLE_DL_CACHE field. + EFUSE_BLK0_WDATA6_DISABLE_DL_CACHE_Pos = 0x9 + // Bit mask of DISABLE_DL_CACHE field. + EFUSE_BLK0_WDATA6_DISABLE_DL_CACHE_Msk = 0x200 + // Bit DISABLE_DL_CACHE. + EFUSE_BLK0_WDATA6_DISABLE_DL_CACHE = 0x200 + // Position of KEY_STATUS field. + EFUSE_BLK0_WDATA6_KEY_STATUS_Pos = 0xa + // Bit mask of KEY_STATUS field. + EFUSE_BLK0_WDATA6_KEY_STATUS_Msk = 0x400 + // Bit KEY_STATUS. + EFUSE_BLK0_WDATA6_KEY_STATUS = 0x400 + + // BLK1_RDATA0 + // Position of RD_BLOCK1 field. + EFUSE_BLK1_RDATA0_RD_BLOCK1_Pos = 0x0 + // Bit mask of RD_BLOCK1 field. + EFUSE_BLK1_RDATA0_RD_BLOCK1_Msk = 0xffffffff + + // BLK1_RDATA1 + // Position of RD_BLOCK1_1 field. + EFUSE_BLK1_RDATA1_RD_BLOCK1_1_Pos = 0x0 + // Bit mask of RD_BLOCK1_1 field. + EFUSE_BLK1_RDATA1_RD_BLOCK1_1_Msk = 0xffffffff + + // BLK1_RDATA2 + // Position of RD_BLOCK1_2 field. + EFUSE_BLK1_RDATA2_RD_BLOCK1_2_Pos = 0x0 + // Bit mask of RD_BLOCK1_2 field. + EFUSE_BLK1_RDATA2_RD_BLOCK1_2_Msk = 0xffffffff + + // BLK1_RDATA3 + // Position of RD_BLOCK1_3 field. + EFUSE_BLK1_RDATA3_RD_BLOCK1_3_Pos = 0x0 + // Bit mask of RD_BLOCK1_3 field. + EFUSE_BLK1_RDATA3_RD_BLOCK1_3_Msk = 0xffffffff + + // BLK1_RDATA4 + // Position of RD_BLOCK1_4 field. + EFUSE_BLK1_RDATA4_RD_BLOCK1_4_Pos = 0x0 + // Bit mask of RD_BLOCK1_4 field. + EFUSE_BLK1_RDATA4_RD_BLOCK1_4_Msk = 0xffffffff + + // BLK1_RDATA5 + // Position of RD_BLOCK1_5 field. + EFUSE_BLK1_RDATA5_RD_BLOCK1_5_Pos = 0x0 + // Bit mask of RD_BLOCK1_5 field. + EFUSE_BLK1_RDATA5_RD_BLOCK1_5_Msk = 0xffffffff + + // BLK1_RDATA6 + // Position of RD_BLOCK1_6 field. + EFUSE_BLK1_RDATA6_RD_BLOCK1_6_Pos = 0x0 + // Bit mask of RD_BLOCK1_6 field. + EFUSE_BLK1_RDATA6_RD_BLOCK1_6_Msk = 0xffffffff + + // BLK1_RDATA7 + // Position of RD_BLOCK1_7 field. + EFUSE_BLK1_RDATA7_RD_BLOCK1_7_Pos = 0x0 + // Bit mask of RD_BLOCK1_7 field. + EFUSE_BLK1_RDATA7_RD_BLOCK1_7_Msk = 0xffffffff + + // BLK2_RDATA0 + // Position of RD_BLOCK2 field. + EFUSE_BLK2_RDATA0_RD_BLOCK2_Pos = 0x0 + // Bit mask of RD_BLOCK2 field. + EFUSE_BLK2_RDATA0_RD_BLOCK2_Msk = 0xffffffff + + // BLK2_RDATA1 + // Position of RD_BLOCK2_1 field. + EFUSE_BLK2_RDATA1_RD_BLOCK2_1_Pos = 0x0 + // Bit mask of RD_BLOCK2_1 field. + EFUSE_BLK2_RDATA1_RD_BLOCK2_1_Msk = 0xffffffff + + // BLK2_RDATA2 + // Position of RD_BLOCK2_2 field. + EFUSE_BLK2_RDATA2_RD_BLOCK2_2_Pos = 0x0 + // Bit mask of RD_BLOCK2_2 field. + EFUSE_BLK2_RDATA2_RD_BLOCK2_2_Msk = 0xffffffff + + // BLK2_RDATA3 + // Position of RD_BLOCK2_3 field. + EFUSE_BLK2_RDATA3_RD_BLOCK2_3_Pos = 0x0 + // Bit mask of RD_BLOCK2_3 field. + EFUSE_BLK2_RDATA3_RD_BLOCK2_3_Msk = 0xffffffff + + // BLK2_RDATA4 + // Position of RD_BLOCK2_4 field. + EFUSE_BLK2_RDATA4_RD_BLOCK2_4_Pos = 0x0 + // Bit mask of RD_BLOCK2_4 field. + EFUSE_BLK2_RDATA4_RD_BLOCK2_4_Msk = 0xffffffff + + // BLK2_RDATA5 + // Position of RD_BLOCK2_5 field. + EFUSE_BLK2_RDATA5_RD_BLOCK2_5_Pos = 0x0 + // Bit mask of RD_BLOCK2_5 field. + EFUSE_BLK2_RDATA5_RD_BLOCK2_5_Msk = 0xffffffff + + // BLK2_RDATA6 + // Position of RD_BLOCK2_6 field. + EFUSE_BLK2_RDATA6_RD_BLOCK2_6_Pos = 0x0 + // Bit mask of RD_BLOCK2_6 field. + EFUSE_BLK2_RDATA6_RD_BLOCK2_6_Msk = 0xffffffff + + // BLK2_RDATA7 + // Position of RD_BLOCK2_7 field. + EFUSE_BLK2_RDATA7_RD_BLOCK2_7_Pos = 0x0 + // Bit mask of RD_BLOCK2_7 field. + EFUSE_BLK2_RDATA7_RD_BLOCK2_7_Msk = 0xffffffff + + // BLK3_RDATA0 + // Position of RD_CUSTOM_MAC_CRC field. + EFUSE_BLK3_RDATA0_RD_CUSTOM_MAC_CRC_Pos = 0x0 + // Bit mask of RD_CUSTOM_MAC_CRC field. + EFUSE_BLK3_RDATA0_RD_CUSTOM_MAC_CRC_Msk = 0xff + // Position of RD_CUSTOM_MAC field. + EFUSE_BLK3_RDATA0_RD_CUSTOM_MAC_Pos = 0x8 + // Bit mask of RD_CUSTOM_MAC field. + EFUSE_BLK3_RDATA0_RD_CUSTOM_MAC_Msk = 0xffffff00 + + // BLK3_RDATA1 + // Position of RD_CUSTOM_MAC_1 field. + EFUSE_BLK3_RDATA1_RD_CUSTOM_MAC_1_Pos = 0x0 + // Bit mask of RD_CUSTOM_MAC_1 field. + EFUSE_BLK3_RDATA1_RD_CUSTOM_MAC_1_Msk = 0xffffff + // Position of RESERVED_3_56 field. + EFUSE_BLK3_RDATA1_RESERVED_3_56_Pos = 0x18 + // Bit mask of RESERVED_3_56 field. + EFUSE_BLK3_RDATA1_RESERVED_3_56_Msk = 0xff000000 + + // BLK3_RDATA2 + // Position of RD_BLK3_RESERVED_2 field. + EFUSE_BLK3_RDATA2_RD_BLK3_RESERVED_2_Pos = 0x0 + // Bit mask of RD_BLK3_RESERVED_2 field. + EFUSE_BLK3_RDATA2_RD_BLK3_RESERVED_2_Msk = 0xffffffff + + // BLK3_RDATA3 + // Position of RD_ADC1_TP_LOW field. + EFUSE_BLK3_RDATA3_RD_ADC1_TP_LOW_Pos = 0x0 + // Bit mask of RD_ADC1_TP_LOW field. + EFUSE_BLK3_RDATA3_RD_ADC1_TP_LOW_Msk = 0x7f + // Position of RD_ADC1_TP_HIGH field. + EFUSE_BLK3_RDATA3_RD_ADC1_TP_HIGH_Pos = 0x7 + // Bit mask of RD_ADC1_TP_HIGH field. + EFUSE_BLK3_RDATA3_RD_ADC1_TP_HIGH_Msk = 0xff80 + // Position of RD_ADC2_TP_LOW field. + EFUSE_BLK3_RDATA3_RD_ADC2_TP_LOW_Pos = 0x10 + // Bit mask of RD_ADC2_TP_LOW field. + EFUSE_BLK3_RDATA3_RD_ADC2_TP_LOW_Msk = 0x7f0000 + // Position of RD_ADC2_TP_HIGH field. + EFUSE_BLK3_RDATA3_RD_ADC2_TP_HIGH_Pos = 0x17 + // Bit mask of RD_ADC2_TP_HIGH field. + EFUSE_BLK3_RDATA3_RD_ADC2_TP_HIGH_Msk = 0xff800000 + + // BLK3_RDATA4 + // Position of RD_SECURE_VERSION field. + EFUSE_BLK3_RDATA4_RD_SECURE_VERSION_Pos = 0x0 + // Bit mask of RD_SECURE_VERSION field. + EFUSE_BLK3_RDATA4_RD_SECURE_VERSION_Msk = 0xffffffff + + // BLK3_RDATA5 + // Position of RESERVED_3_160 field. + EFUSE_BLK3_RDATA5_RESERVED_3_160_Pos = 0x0 + // Bit mask of RESERVED_3_160 field. + EFUSE_BLK3_RDATA5_RESERVED_3_160_Msk = 0xffffff + // Position of RD_MAC_VERSION field. + EFUSE_BLK3_RDATA5_RD_MAC_VERSION_Pos = 0x18 + // Bit mask of RD_MAC_VERSION field. + EFUSE_BLK3_RDATA5_RD_MAC_VERSION_Msk = 0xff000000 + + // BLK3_RDATA6 + // Position of RD_BLK3_RESERVED_6 field. + EFUSE_BLK3_RDATA6_RD_BLK3_RESERVED_6_Pos = 0x0 + // Bit mask of RD_BLK3_RESERVED_6 field. + EFUSE_BLK3_RDATA6_RD_BLK3_RESERVED_6_Msk = 0xffffffff + + // BLK3_RDATA7 + // Position of RD_BLK3_RESERVED_7 field. + EFUSE_BLK3_RDATA7_RD_BLK3_RESERVED_7_Pos = 0x0 + // Bit mask of RD_BLK3_RESERVED_7 field. + EFUSE_BLK3_RDATA7_RD_BLK3_RESERVED_7_Msk = 0xffffffff + + // BLK1_WDATA0 + // Position of BLK1_DIN0 field. + EFUSE_BLK1_WDATA0_BLK1_DIN0_Pos = 0x0 + // Bit mask of BLK1_DIN0 field. + EFUSE_BLK1_WDATA0_BLK1_DIN0_Msk = 0xffffffff + + // BLK1_WDATA1 + // Position of BLK1_DIN1 field. + EFUSE_BLK1_WDATA1_BLK1_DIN1_Pos = 0x0 + // Bit mask of BLK1_DIN1 field. + EFUSE_BLK1_WDATA1_BLK1_DIN1_Msk = 0xffffffff + + // BLK1_WDATA2 + // Position of BLK1_DIN2 field. + EFUSE_BLK1_WDATA2_BLK1_DIN2_Pos = 0x0 + // Bit mask of BLK1_DIN2 field. + EFUSE_BLK1_WDATA2_BLK1_DIN2_Msk = 0xffffffff + + // BLK1_WDATA3 + // Position of BLK1_DIN3 field. + EFUSE_BLK1_WDATA3_BLK1_DIN3_Pos = 0x0 + // Bit mask of BLK1_DIN3 field. + EFUSE_BLK1_WDATA3_BLK1_DIN3_Msk = 0xffffffff + + // BLK1_WDATA4 + // Position of BLK1_DIN4 field. + EFUSE_BLK1_WDATA4_BLK1_DIN4_Pos = 0x0 + // Bit mask of BLK1_DIN4 field. + EFUSE_BLK1_WDATA4_BLK1_DIN4_Msk = 0xffffffff + + // BLK1_WDATA5 + // Position of BLK1_DIN5 field. + EFUSE_BLK1_WDATA5_BLK1_DIN5_Pos = 0x0 + // Bit mask of BLK1_DIN5 field. + EFUSE_BLK1_WDATA5_BLK1_DIN5_Msk = 0xffffffff + + // BLK1_WDATA6 + // Position of BLK1_DIN6 field. + EFUSE_BLK1_WDATA6_BLK1_DIN6_Pos = 0x0 + // Bit mask of BLK1_DIN6 field. + EFUSE_BLK1_WDATA6_BLK1_DIN6_Msk = 0xffffffff + + // BLK1_WDATA7 + // Position of BLK1_DIN7 field. + EFUSE_BLK1_WDATA7_BLK1_DIN7_Pos = 0x0 + // Bit mask of BLK1_DIN7 field. + EFUSE_BLK1_WDATA7_BLK1_DIN7_Msk = 0xffffffff + + // BLK2_WDATA0 + // Position of BLK2_DIN0 field. + EFUSE_BLK2_WDATA0_BLK2_DIN0_Pos = 0x0 + // Bit mask of BLK2_DIN0 field. + EFUSE_BLK2_WDATA0_BLK2_DIN0_Msk = 0xffffffff + + // BLK2_WDATA1 + // Position of BLK2_DIN1 field. + EFUSE_BLK2_WDATA1_BLK2_DIN1_Pos = 0x0 + // Bit mask of BLK2_DIN1 field. + EFUSE_BLK2_WDATA1_BLK2_DIN1_Msk = 0xffffffff + + // BLK2_WDATA2 + // Position of BLK2_DIN2 field. + EFUSE_BLK2_WDATA2_BLK2_DIN2_Pos = 0x0 + // Bit mask of BLK2_DIN2 field. + EFUSE_BLK2_WDATA2_BLK2_DIN2_Msk = 0xffffffff + + // BLK2_WDATA3 + // Position of BLK2_DIN3 field. + EFUSE_BLK2_WDATA3_BLK2_DIN3_Pos = 0x0 + // Bit mask of BLK2_DIN3 field. + EFUSE_BLK2_WDATA3_BLK2_DIN3_Msk = 0xffffffff + + // BLK2_WDATA4 + // Position of BLK2_DIN4 field. + EFUSE_BLK2_WDATA4_BLK2_DIN4_Pos = 0x0 + // Bit mask of BLK2_DIN4 field. + EFUSE_BLK2_WDATA4_BLK2_DIN4_Msk = 0xffffffff + + // BLK2_WDATA5 + // Position of BLK2_DIN5 field. + EFUSE_BLK2_WDATA5_BLK2_DIN5_Pos = 0x0 + // Bit mask of BLK2_DIN5 field. + EFUSE_BLK2_WDATA5_BLK2_DIN5_Msk = 0xffffffff + + // BLK2_WDATA6 + // Position of BLK2_DIN6 field. + EFUSE_BLK2_WDATA6_BLK2_DIN6_Pos = 0x0 + // Bit mask of BLK2_DIN6 field. + EFUSE_BLK2_WDATA6_BLK2_DIN6_Msk = 0xffffffff + + // BLK2_WDATA7 + // Position of BLK2_DIN7 field. + EFUSE_BLK2_WDATA7_BLK2_DIN7_Pos = 0x0 + // Bit mask of BLK2_DIN7 field. + EFUSE_BLK2_WDATA7_BLK2_DIN7_Msk = 0xffffffff + + // BLK3_WDATA0 + // Position of BLK3_DIN0 field. + EFUSE_BLK3_WDATA0_BLK3_DIN0_Pos = 0x0 + // Bit mask of BLK3_DIN0 field. + EFUSE_BLK3_WDATA0_BLK3_DIN0_Msk = 0xffffffff + + // BLK3_WDATA1 + // Position of BLK3_DIN1 field. + EFUSE_BLK3_WDATA1_BLK3_DIN1_Pos = 0x0 + // Bit mask of BLK3_DIN1 field. + EFUSE_BLK3_WDATA1_BLK3_DIN1_Msk = 0xffffffff + + // BLK3_WDATA2 + // Position of BLK3_DIN2 field. + EFUSE_BLK3_WDATA2_BLK3_DIN2_Pos = 0x0 + // Bit mask of BLK3_DIN2 field. + EFUSE_BLK3_WDATA2_BLK3_DIN2_Msk = 0xffffffff + + // BLK3_WDATA3 + // Position of ADC1_TP_LOW field. + EFUSE_BLK3_WDATA3_ADC1_TP_LOW_Pos = 0x0 + // Bit mask of ADC1_TP_LOW field. + EFUSE_BLK3_WDATA3_ADC1_TP_LOW_Msk = 0x7f + // Position of ADC1_TP_HIGH field. + EFUSE_BLK3_WDATA3_ADC1_TP_HIGH_Pos = 0x7 + // Bit mask of ADC1_TP_HIGH field. + EFUSE_BLK3_WDATA3_ADC1_TP_HIGH_Msk = 0xff80 + // Position of ADC2_TP_LOW field. + EFUSE_BLK3_WDATA3_ADC2_TP_LOW_Pos = 0x10 + // Bit mask of ADC2_TP_LOW field. + EFUSE_BLK3_WDATA3_ADC2_TP_LOW_Msk = 0x7f0000 + // Position of ADC2_TP_HIGH field. + EFUSE_BLK3_WDATA3_ADC2_TP_HIGH_Pos = 0x17 + // Bit mask of ADC2_TP_HIGH field. + EFUSE_BLK3_WDATA3_ADC2_TP_HIGH_Msk = 0xff800000 + + // BLK3_WDATA4 + // Position of SECURE_VERSION field. + EFUSE_BLK3_WDATA4_SECURE_VERSION_Pos = 0x0 + // Bit mask of SECURE_VERSION field. + EFUSE_BLK3_WDATA4_SECURE_VERSION_Msk = 0xffffffff + + // BLK3_WDATA5 + // Position of BLK3_DIN5 field. + EFUSE_BLK3_WDATA5_BLK3_DIN5_Pos = 0x0 + // Bit mask of BLK3_DIN5 field. + EFUSE_BLK3_WDATA5_BLK3_DIN5_Msk = 0xffffffff + + // BLK3_WDATA6 + // Position of BLK3_DIN6 field. + EFUSE_BLK3_WDATA6_BLK3_DIN6_Pos = 0x0 + // Bit mask of BLK3_DIN6 field. + EFUSE_BLK3_WDATA6_BLK3_DIN6_Msk = 0xffffffff + + // BLK3_WDATA7 + // Position of BLK3_DIN7 field. + EFUSE_BLK3_WDATA7_BLK3_DIN7_Pos = 0x0 + // Bit mask of BLK3_DIN7 field. + EFUSE_BLK3_WDATA7_BLK3_DIN7_Msk = 0xffffffff + + // CLK + // Position of SEL0 field. + EFUSE_CLK_SEL0_Pos = 0x0 + // Bit mask of SEL0 field. + EFUSE_CLK_SEL0_Msk = 0xff + // Position of SEL1 field. + EFUSE_CLK_SEL1_Pos = 0x8 + // Bit mask of SEL1 field. + EFUSE_CLK_SEL1_Msk = 0xff00 + // Position of EN field. + EFUSE_CLK_EN_Pos = 0x10 + // Bit mask of EN field. + EFUSE_CLK_EN_Msk = 0x10000 + // Bit EN. + EFUSE_CLK_EN = 0x10000 + + // CONF + // Position of OP_CODE field. + EFUSE_CONF_OP_CODE_Pos = 0x0 + // Bit mask of OP_CODE field. + EFUSE_CONF_OP_CODE_Msk = 0xffff + // Position of FORCE_NO_WR_RD_DIS field. + EFUSE_CONF_FORCE_NO_WR_RD_DIS_Pos = 0x10 + // Bit mask of FORCE_NO_WR_RD_DIS field. + EFUSE_CONF_FORCE_NO_WR_RD_DIS_Msk = 0x10000 + // Bit FORCE_NO_WR_RD_DIS. + EFUSE_CONF_FORCE_NO_WR_RD_DIS = 0x10000 + + // STATUS + // Position of DEBUG field. + EFUSE_STATUS_DEBUG_Pos = 0x0 + // Bit mask of DEBUG field. + EFUSE_STATUS_DEBUG_Msk = 0xffffffff + + // CMD + // Position of READ_CMD field. + EFUSE_CMD_READ_CMD_Pos = 0x0 + // Bit mask of READ_CMD field. + EFUSE_CMD_READ_CMD_Msk = 0x1 + // Bit READ_CMD. + EFUSE_CMD_READ_CMD = 0x1 + // Position of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Pos = 0x1 + // Bit mask of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Msk = 0x2 + // Bit PGM_CMD. + EFUSE_CMD_PGM_CMD = 0x2 + + // INT_RAW + // Position of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Pos = 0x0 + // Bit mask of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Msk = 0x1 + // Bit READ_DONE_INT_RAW. + EFUSE_INT_RAW_READ_DONE_INT_RAW = 0x1 + // Position of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Pos = 0x1 + // Bit mask of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Msk = 0x2 + // Bit PGM_DONE_INT_RAW. + EFUSE_INT_RAW_PGM_DONE_INT_RAW = 0x2 + + // INT_ST + // Position of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Pos = 0x0 + // Bit mask of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Msk = 0x1 + // Bit READ_DONE_INT_ST. + EFUSE_INT_ST_READ_DONE_INT_ST = 0x1 + // Position of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Msk = 0x2 + // Bit PGM_DONE_INT_ST. + EFUSE_INT_ST_PGM_DONE_INT_ST = 0x2 + + // INT_ENA + // Position of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Pos = 0x0 + // Bit mask of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Msk = 0x1 + // Bit READ_DONE_INT_ENA. + EFUSE_INT_ENA_READ_DONE_INT_ENA = 0x1 + // Position of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Msk = 0x2 + // Bit PGM_DONE_INT_ENA. + EFUSE_INT_ENA_PGM_DONE_INT_ENA = 0x2 + + // INT_CLR + // Position of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Pos = 0x0 + // Bit mask of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Msk = 0x1 + // Bit READ_DONE_INT_CLR. + EFUSE_INT_CLR_READ_DONE_INT_CLR = 0x1 + // Position of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Pos = 0x1 + // Bit mask of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Msk = 0x2 + // Bit PGM_DONE_INT_CLR. + EFUSE_INT_CLR_PGM_DONE_INT_CLR = 0x2 + + // DAC_CONF + // Position of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Pos = 0x0 + // Bit mask of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Msk = 0xff + // Position of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Pos = 0x8 + // Bit mask of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Msk = 0x100 + // Bit DAC_CLK_PAD_SEL. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL = 0x100 + + // DEC_STATUS + // Position of DEC_WARNINGS field. + EFUSE_DEC_STATUS_DEC_WARNINGS_Pos = 0x0 + // Bit mask of DEC_WARNINGS field. + EFUSE_DEC_STATUS_DEC_WARNINGS_Msk = 0xfff + + // DATE + // Position of DATE field. + EFUSE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EFUSE_DATE_DATE_Msk = 0xffffffff +) + +// Constants for EMAC_DMA: Ethernet DMA configuration and control registers +const ( + // DMABUSMODE: Bus mode configuration + // Position of SW_RST field. + EMAC_DMA_DMABUSMODE_SW_RST_Pos = 0x0 + // Bit mask of SW_RST field. + EMAC_DMA_DMABUSMODE_SW_RST_Msk = 0x1 + // Bit SW_RST. + EMAC_DMA_DMABUSMODE_SW_RST = 0x1 + // Position of DMA_ARB_SCH field. + EMAC_DMA_DMABUSMODE_DMA_ARB_SCH_Pos = 0x1 + // Bit mask of DMA_ARB_SCH field. + EMAC_DMA_DMABUSMODE_DMA_ARB_SCH_Msk = 0x2 + // Bit DMA_ARB_SCH. + EMAC_DMA_DMABUSMODE_DMA_ARB_SCH = 0x2 + // Position of DESC_SKIP_LEN field. + EMAC_DMA_DMABUSMODE_DESC_SKIP_LEN_Pos = 0x2 + // Bit mask of DESC_SKIP_LEN field. + EMAC_DMA_DMABUSMODE_DESC_SKIP_LEN_Msk = 0x7c + // Position of ALT_DESC_SIZE field. + EMAC_DMA_DMABUSMODE_ALT_DESC_SIZE_Pos = 0x7 + // Bit mask of ALT_DESC_SIZE field. + EMAC_DMA_DMABUSMODE_ALT_DESC_SIZE_Msk = 0x80 + // Bit ALT_DESC_SIZE. + EMAC_DMA_DMABUSMODE_ALT_DESC_SIZE = 0x80 + // Position of PROG_BURST_LEN field. + EMAC_DMA_DMABUSMODE_PROG_BURST_LEN_Pos = 0x8 + // Bit mask of PROG_BURST_LEN field. + EMAC_DMA_DMABUSMODE_PROG_BURST_LEN_Msk = 0x3f00 + // Position of PRI_RATIO field. + EMAC_DMA_DMABUSMODE_PRI_RATIO_Pos = 0xe + // Bit mask of PRI_RATIO field. + EMAC_DMA_DMABUSMODE_PRI_RATIO_Msk = 0xc000 + // Position of FIXED_BURST field. + EMAC_DMA_DMABUSMODE_FIXED_BURST_Pos = 0x10 + // Bit mask of FIXED_BURST field. + EMAC_DMA_DMABUSMODE_FIXED_BURST_Msk = 0x10000 + // Bit FIXED_BURST. + EMAC_DMA_DMABUSMODE_FIXED_BURST = 0x10000 + // Position of RX_DMA_PBL field. + EMAC_DMA_DMABUSMODE_RX_DMA_PBL_Pos = 0x11 + // Bit mask of RX_DMA_PBL field. + EMAC_DMA_DMABUSMODE_RX_DMA_PBL_Msk = 0x7e0000 + // Position of USE_SEP_PBL field. + EMAC_DMA_DMABUSMODE_USE_SEP_PBL_Pos = 0x17 + // Bit mask of USE_SEP_PBL field. + EMAC_DMA_DMABUSMODE_USE_SEP_PBL_Msk = 0x800000 + // Bit USE_SEP_PBL. + EMAC_DMA_DMABUSMODE_USE_SEP_PBL = 0x800000 + // Position of PBLX8_MODE field. + EMAC_DMA_DMABUSMODE_PBLX8_MODE_Pos = 0x18 + // Bit mask of PBLX8_MODE field. + EMAC_DMA_DMABUSMODE_PBLX8_MODE_Msk = 0x1000000 + // Bit PBLX8_MODE. + EMAC_DMA_DMABUSMODE_PBLX8_MODE = 0x1000000 + // Position of DMAADDRALIBEA field. + EMAC_DMA_DMABUSMODE_DMAADDRALIBEA_Pos = 0x19 + // Bit mask of DMAADDRALIBEA field. + EMAC_DMA_DMABUSMODE_DMAADDRALIBEA_Msk = 0x2000000 + // Bit DMAADDRALIBEA. + EMAC_DMA_DMABUSMODE_DMAADDRALIBEA = 0x2000000 + // Position of DMAMIXEDBURST field. + EMAC_DMA_DMABUSMODE_DMAMIXEDBURST_Pos = 0x1a + // Bit mask of DMAMIXEDBURST field. + EMAC_DMA_DMABUSMODE_DMAMIXEDBURST_Msk = 0x4000000 + // Bit DMAMIXEDBURST. + EMAC_DMA_DMABUSMODE_DMAMIXEDBURST = 0x4000000 + + // DMASTATUS: State of interrupts, errors and other events + // Position of TRANS_INT field. + EMAC_DMA_DMASTATUS_TRANS_INT_Pos = 0x0 + // Bit mask of TRANS_INT field. + EMAC_DMA_DMASTATUS_TRANS_INT_Msk = 0x1 + // Bit TRANS_INT. + EMAC_DMA_DMASTATUS_TRANS_INT = 0x1 + // Position of TRANS_PROC_STOP field. + EMAC_DMA_DMASTATUS_TRANS_PROC_STOP_Pos = 0x1 + // Bit mask of TRANS_PROC_STOP field. + EMAC_DMA_DMASTATUS_TRANS_PROC_STOP_Msk = 0x2 + // Bit TRANS_PROC_STOP. + EMAC_DMA_DMASTATUS_TRANS_PROC_STOP = 0x2 + // Position of TRANS_BUF_UNAVAIL field. + EMAC_DMA_DMASTATUS_TRANS_BUF_UNAVAIL_Pos = 0x2 + // Bit mask of TRANS_BUF_UNAVAIL field. + EMAC_DMA_DMASTATUS_TRANS_BUF_UNAVAIL_Msk = 0x4 + // Bit TRANS_BUF_UNAVAIL. + EMAC_DMA_DMASTATUS_TRANS_BUF_UNAVAIL = 0x4 + // Position of TRANS_JABBER_TO field. + EMAC_DMA_DMASTATUS_TRANS_JABBER_TO_Pos = 0x3 + // Bit mask of TRANS_JABBER_TO field. + EMAC_DMA_DMASTATUS_TRANS_JABBER_TO_Msk = 0x8 + // Bit TRANS_JABBER_TO. + EMAC_DMA_DMASTATUS_TRANS_JABBER_TO = 0x8 + // Position of RECV_OVFLOW field. + EMAC_DMA_DMASTATUS_RECV_OVFLOW_Pos = 0x4 + // Bit mask of RECV_OVFLOW field. + EMAC_DMA_DMASTATUS_RECV_OVFLOW_Msk = 0x10 + // Bit RECV_OVFLOW. + EMAC_DMA_DMASTATUS_RECV_OVFLOW = 0x10 + // Position of TRANS_UNDFLOW field. + EMAC_DMA_DMASTATUS_TRANS_UNDFLOW_Pos = 0x5 + // Bit mask of TRANS_UNDFLOW field. + EMAC_DMA_DMASTATUS_TRANS_UNDFLOW_Msk = 0x20 + // Bit TRANS_UNDFLOW. + EMAC_DMA_DMASTATUS_TRANS_UNDFLOW = 0x20 + // Position of RECV_INT field. + EMAC_DMA_DMASTATUS_RECV_INT_Pos = 0x6 + // Bit mask of RECV_INT field. + EMAC_DMA_DMASTATUS_RECV_INT_Msk = 0x40 + // Bit RECV_INT. + EMAC_DMA_DMASTATUS_RECV_INT = 0x40 + // Position of RECV_BUF_UNAVAIL field. + EMAC_DMA_DMASTATUS_RECV_BUF_UNAVAIL_Pos = 0x7 + // Bit mask of RECV_BUF_UNAVAIL field. + EMAC_DMA_DMASTATUS_RECV_BUF_UNAVAIL_Msk = 0x80 + // Bit RECV_BUF_UNAVAIL. + EMAC_DMA_DMASTATUS_RECV_BUF_UNAVAIL = 0x80 + // Position of RECV_PROC_STOP field. + EMAC_DMA_DMASTATUS_RECV_PROC_STOP_Pos = 0x8 + // Bit mask of RECV_PROC_STOP field. + EMAC_DMA_DMASTATUS_RECV_PROC_STOP_Msk = 0x100 + // Bit RECV_PROC_STOP. + EMAC_DMA_DMASTATUS_RECV_PROC_STOP = 0x100 + // Position of RECV_WDT_TO field. + EMAC_DMA_DMASTATUS_RECV_WDT_TO_Pos = 0x9 + // Bit mask of RECV_WDT_TO field. + EMAC_DMA_DMASTATUS_RECV_WDT_TO_Msk = 0x200 + // Bit RECV_WDT_TO. + EMAC_DMA_DMASTATUS_RECV_WDT_TO = 0x200 + // Position of EARLY_TRANS_INT field. + EMAC_DMA_DMASTATUS_EARLY_TRANS_INT_Pos = 0xa + // Bit mask of EARLY_TRANS_INT field. + EMAC_DMA_DMASTATUS_EARLY_TRANS_INT_Msk = 0x400 + // Bit EARLY_TRANS_INT. + EMAC_DMA_DMASTATUS_EARLY_TRANS_INT = 0x400 + // Position of FATAL_BUS_ERR_INT field. + EMAC_DMA_DMASTATUS_FATAL_BUS_ERR_INT_Pos = 0xd + // Bit mask of FATAL_BUS_ERR_INT field. + EMAC_DMA_DMASTATUS_FATAL_BUS_ERR_INT_Msk = 0x2000 + // Bit FATAL_BUS_ERR_INT. + EMAC_DMA_DMASTATUS_FATAL_BUS_ERR_INT = 0x2000 + // Position of EARLY_RECV_INT field. + EMAC_DMA_DMASTATUS_EARLY_RECV_INT_Pos = 0xe + // Bit mask of EARLY_RECV_INT field. + EMAC_DMA_DMASTATUS_EARLY_RECV_INT_Msk = 0x4000 + // Bit EARLY_RECV_INT. + EMAC_DMA_DMASTATUS_EARLY_RECV_INT = 0x4000 + // Position of ABN_INT_SUMM field. + EMAC_DMA_DMASTATUS_ABN_INT_SUMM_Pos = 0xf + // Bit mask of ABN_INT_SUMM field. + EMAC_DMA_DMASTATUS_ABN_INT_SUMM_Msk = 0x8000 + // Bit ABN_INT_SUMM. + EMAC_DMA_DMASTATUS_ABN_INT_SUMM = 0x8000 + // Position of NORM_INT_SUMM field. + EMAC_DMA_DMASTATUS_NORM_INT_SUMM_Pos = 0x10 + // Bit mask of NORM_INT_SUMM field. + EMAC_DMA_DMASTATUS_NORM_INT_SUMM_Msk = 0x10000 + // Bit NORM_INT_SUMM. + EMAC_DMA_DMASTATUS_NORM_INT_SUMM = 0x10000 + // Position of RECV_PROC_STATE field. + EMAC_DMA_DMASTATUS_RECV_PROC_STATE_Pos = 0x11 + // Bit mask of RECV_PROC_STATE field. + EMAC_DMA_DMASTATUS_RECV_PROC_STATE_Msk = 0xe0000 + // Position of TRANS_PROC_STATE field. + EMAC_DMA_DMASTATUS_TRANS_PROC_STATE_Pos = 0x14 + // Bit mask of TRANS_PROC_STATE field. + EMAC_DMA_DMASTATUS_TRANS_PROC_STATE_Msk = 0x700000 + // Position of ERROR_BITS field. + EMAC_DMA_DMASTATUS_ERROR_BITS_Pos = 0x17 + // Bit mask of ERROR_BITS field. + EMAC_DMA_DMASTATUS_ERROR_BITS_Msk = 0x3800000 + // Position of PMT_INT field. + EMAC_DMA_DMASTATUS_PMT_INT_Pos = 0x1c + // Bit mask of PMT_INT field. + EMAC_DMA_DMASTATUS_PMT_INT_Msk = 0x10000000 + // Bit PMT_INT. + EMAC_DMA_DMASTATUS_PMT_INT = 0x10000000 + // Position of TS_TRI_INT field. + EMAC_DMA_DMASTATUS_TS_TRI_INT_Pos = 0x1d + // Bit mask of TS_TRI_INT field. + EMAC_DMA_DMASTATUS_TS_TRI_INT_Msk = 0x20000000 + // Bit TS_TRI_INT. + EMAC_DMA_DMASTATUS_TS_TRI_INT = 0x20000000 + + // DMAOPERATION_MODE: Receive and Transmit operating modes and command + // Position of START_STOP_RX field. + EMAC_DMA_DMAOPERATION_MODE_START_STOP_RX_Pos = 0x1 + // Bit mask of START_STOP_RX field. + EMAC_DMA_DMAOPERATION_MODE_START_STOP_RX_Msk = 0x2 + // Bit START_STOP_RX. + EMAC_DMA_DMAOPERATION_MODE_START_STOP_RX = 0x2 + // Position of OPT_SECOND_FRAME field. + EMAC_DMA_DMAOPERATION_MODE_OPT_SECOND_FRAME_Pos = 0x2 + // Bit mask of OPT_SECOND_FRAME field. + EMAC_DMA_DMAOPERATION_MODE_OPT_SECOND_FRAME_Msk = 0x4 + // Bit OPT_SECOND_FRAME. + EMAC_DMA_DMAOPERATION_MODE_OPT_SECOND_FRAME = 0x4 + // Position of RX_THRESH_CTRL field. + EMAC_DMA_DMAOPERATION_MODE_RX_THRESH_CTRL_Pos = 0x3 + // Bit mask of RX_THRESH_CTRL field. + EMAC_DMA_DMAOPERATION_MODE_RX_THRESH_CTRL_Msk = 0x18 + // Position of DROP_GFRM field. + EMAC_DMA_DMAOPERATION_MODE_DROP_GFRM_Pos = 0x5 + // Bit mask of DROP_GFRM field. + EMAC_DMA_DMAOPERATION_MODE_DROP_GFRM_Msk = 0x20 + // Bit DROP_GFRM. + EMAC_DMA_DMAOPERATION_MODE_DROP_GFRM = 0x20 + // Position of FWD_UNDER_GF field. + EMAC_DMA_DMAOPERATION_MODE_FWD_UNDER_GF_Pos = 0x6 + // Bit mask of FWD_UNDER_GF field. + EMAC_DMA_DMAOPERATION_MODE_FWD_UNDER_GF_Msk = 0x40 + // Bit FWD_UNDER_GF. + EMAC_DMA_DMAOPERATION_MODE_FWD_UNDER_GF = 0x40 + // Position of FWD_ERR_FRAME field. + EMAC_DMA_DMAOPERATION_MODE_FWD_ERR_FRAME_Pos = 0x7 + // Bit mask of FWD_ERR_FRAME field. + EMAC_DMA_DMAOPERATION_MODE_FWD_ERR_FRAME_Msk = 0x80 + // Bit FWD_ERR_FRAME. + EMAC_DMA_DMAOPERATION_MODE_FWD_ERR_FRAME = 0x80 + // Position of START_STOP_TRANSMISSION_COMMAND field. + EMAC_DMA_DMAOPERATION_MODE_START_STOP_TRANSMISSION_COMMAND_Pos = 0xd + // Bit mask of START_STOP_TRANSMISSION_COMMAND field. + EMAC_DMA_DMAOPERATION_MODE_START_STOP_TRANSMISSION_COMMAND_Msk = 0x2000 + // Bit START_STOP_TRANSMISSION_COMMAND. + EMAC_DMA_DMAOPERATION_MODE_START_STOP_TRANSMISSION_COMMAND = 0x2000 + // Position of TX_THRESH_CTRL field. + EMAC_DMA_DMAOPERATION_MODE_TX_THRESH_CTRL_Pos = 0xe + // Bit mask of TX_THRESH_CTRL field. + EMAC_DMA_DMAOPERATION_MODE_TX_THRESH_CTRL_Msk = 0x1c000 + // Position of FLUSH_TX_FIFO field. + EMAC_DMA_DMAOPERATION_MODE_FLUSH_TX_FIFO_Pos = 0x14 + // Bit mask of FLUSH_TX_FIFO field. + EMAC_DMA_DMAOPERATION_MODE_FLUSH_TX_FIFO_Msk = 0x100000 + // Bit FLUSH_TX_FIFO. + EMAC_DMA_DMAOPERATION_MODE_FLUSH_TX_FIFO = 0x100000 + // Position of TX_STR_FWD field. + EMAC_DMA_DMAOPERATION_MODE_TX_STR_FWD_Pos = 0x15 + // Bit mask of TX_STR_FWD field. + EMAC_DMA_DMAOPERATION_MODE_TX_STR_FWD_Msk = 0x200000 + // Bit TX_STR_FWD. + EMAC_DMA_DMAOPERATION_MODE_TX_STR_FWD = 0x200000 + // Position of DIS_FLUSH_RECV_FRAMES field. + EMAC_DMA_DMAOPERATION_MODE_DIS_FLUSH_RECV_FRAMES_Pos = 0x18 + // Bit mask of DIS_FLUSH_RECV_FRAMES field. + EMAC_DMA_DMAOPERATION_MODE_DIS_FLUSH_RECV_FRAMES_Msk = 0x1000000 + // Bit DIS_FLUSH_RECV_FRAMES. + EMAC_DMA_DMAOPERATION_MODE_DIS_FLUSH_RECV_FRAMES = 0x1000000 + // Position of RX_STORE_FORWARD field. + EMAC_DMA_DMAOPERATION_MODE_RX_STORE_FORWARD_Pos = 0x19 + // Bit mask of RX_STORE_FORWARD field. + EMAC_DMA_DMAOPERATION_MODE_RX_STORE_FORWARD_Msk = 0x2000000 + // Bit RX_STORE_FORWARD. + EMAC_DMA_DMAOPERATION_MODE_RX_STORE_FORWARD = 0x2000000 + // Position of DIS_DROP_TCPIP_ERR_FRAM field. + EMAC_DMA_DMAOPERATION_MODE_DIS_DROP_TCPIP_ERR_FRAM_Pos = 0x1a + // Bit mask of DIS_DROP_TCPIP_ERR_FRAM field. + EMAC_DMA_DMAOPERATION_MODE_DIS_DROP_TCPIP_ERR_FRAM_Msk = 0x4000000 + // Bit DIS_DROP_TCPIP_ERR_FRAM. + EMAC_DMA_DMAOPERATION_MODE_DIS_DROP_TCPIP_ERR_FRAM = 0x4000000 + + // DMAIN_EN + // Position of DMAIN_TIE field. + EMAC_DMA_DMAIN_EN_DMAIN_TIE_Pos = 0x0 + // Bit mask of DMAIN_TIE field. + EMAC_DMA_DMAIN_EN_DMAIN_TIE_Msk = 0x1 + // Bit DMAIN_TIE. + EMAC_DMA_DMAIN_EN_DMAIN_TIE = 0x1 + // Position of DMAIN_TSE field. + EMAC_DMA_DMAIN_EN_DMAIN_TSE_Pos = 0x1 + // Bit mask of DMAIN_TSE field. + EMAC_DMA_DMAIN_EN_DMAIN_TSE_Msk = 0x2 + // Bit DMAIN_TSE. + EMAC_DMA_DMAIN_EN_DMAIN_TSE = 0x2 + // Position of DMAIN_TBUE field. + EMAC_DMA_DMAIN_EN_DMAIN_TBUE_Pos = 0x2 + // Bit mask of DMAIN_TBUE field. + EMAC_DMA_DMAIN_EN_DMAIN_TBUE_Msk = 0x4 + // Bit DMAIN_TBUE. + EMAC_DMA_DMAIN_EN_DMAIN_TBUE = 0x4 + // Position of DMAIN_TJTE field. + EMAC_DMA_DMAIN_EN_DMAIN_TJTE_Pos = 0x3 + // Bit mask of DMAIN_TJTE field. + EMAC_DMA_DMAIN_EN_DMAIN_TJTE_Msk = 0x8 + // Bit DMAIN_TJTE. + EMAC_DMA_DMAIN_EN_DMAIN_TJTE = 0x8 + // Position of DMAIN_OIE field. + EMAC_DMA_DMAIN_EN_DMAIN_OIE_Pos = 0x4 + // Bit mask of DMAIN_OIE field. + EMAC_DMA_DMAIN_EN_DMAIN_OIE_Msk = 0x10 + // Bit DMAIN_OIE. + EMAC_DMA_DMAIN_EN_DMAIN_OIE = 0x10 + // Position of DMAIN_UIE field. + EMAC_DMA_DMAIN_EN_DMAIN_UIE_Pos = 0x5 + // Bit mask of DMAIN_UIE field. + EMAC_DMA_DMAIN_EN_DMAIN_UIE_Msk = 0x20 + // Bit DMAIN_UIE. + EMAC_DMA_DMAIN_EN_DMAIN_UIE = 0x20 + // Position of DMAIN_RIE field. + EMAC_DMA_DMAIN_EN_DMAIN_RIE_Pos = 0x6 + // Bit mask of DMAIN_RIE field. + EMAC_DMA_DMAIN_EN_DMAIN_RIE_Msk = 0x40 + // Bit DMAIN_RIE. + EMAC_DMA_DMAIN_EN_DMAIN_RIE = 0x40 + // Position of DMAIN_RBUE field. + EMAC_DMA_DMAIN_EN_DMAIN_RBUE_Pos = 0x7 + // Bit mask of DMAIN_RBUE field. + EMAC_DMA_DMAIN_EN_DMAIN_RBUE_Msk = 0x80 + // Bit DMAIN_RBUE. + EMAC_DMA_DMAIN_EN_DMAIN_RBUE = 0x80 + // Position of DMAIN_RSE field. + EMAC_DMA_DMAIN_EN_DMAIN_RSE_Pos = 0x8 + // Bit mask of DMAIN_RSE field. + EMAC_DMA_DMAIN_EN_DMAIN_RSE_Msk = 0x100 + // Bit DMAIN_RSE. + EMAC_DMA_DMAIN_EN_DMAIN_RSE = 0x100 + // Position of DMAIN_RWTE field. + EMAC_DMA_DMAIN_EN_DMAIN_RWTE_Pos = 0x9 + // Bit mask of DMAIN_RWTE field. + EMAC_DMA_DMAIN_EN_DMAIN_RWTE_Msk = 0x200 + // Bit DMAIN_RWTE. + EMAC_DMA_DMAIN_EN_DMAIN_RWTE = 0x200 + // Position of DMAIN_ETIE field. + EMAC_DMA_DMAIN_EN_DMAIN_ETIE_Pos = 0xa + // Bit mask of DMAIN_ETIE field. + EMAC_DMA_DMAIN_EN_DMAIN_ETIE_Msk = 0x400 + // Bit DMAIN_ETIE. + EMAC_DMA_DMAIN_EN_DMAIN_ETIE = 0x400 + // Position of DMAIN_FBEE field. + EMAC_DMA_DMAIN_EN_DMAIN_FBEE_Pos = 0xd + // Bit mask of DMAIN_FBEE field. + EMAC_DMA_DMAIN_EN_DMAIN_FBEE_Msk = 0x2000 + // Bit DMAIN_FBEE. + EMAC_DMA_DMAIN_EN_DMAIN_FBEE = 0x2000 + // Position of DMAIN_ERIE field. + EMAC_DMA_DMAIN_EN_DMAIN_ERIE_Pos = 0xe + // Bit mask of DMAIN_ERIE field. + EMAC_DMA_DMAIN_EN_DMAIN_ERIE_Msk = 0x4000 + // Bit DMAIN_ERIE. + EMAC_DMA_DMAIN_EN_DMAIN_ERIE = 0x4000 + // Position of DMAIN_AISE field. + EMAC_DMA_DMAIN_EN_DMAIN_AISE_Pos = 0xf + // Bit mask of DMAIN_AISE field. + EMAC_DMA_DMAIN_EN_DMAIN_AISE_Msk = 0x8000 + // Bit DMAIN_AISE. + EMAC_DMA_DMAIN_EN_DMAIN_AISE = 0x8000 + // Position of DMAIN_NISE field. + EMAC_DMA_DMAIN_EN_DMAIN_NISE_Pos = 0x10 + // Bit mask of DMAIN_NISE field. + EMAC_DMA_DMAIN_EN_DMAIN_NISE_Msk = 0x10000 + // Bit DMAIN_NISE. + EMAC_DMA_DMAIN_EN_DMAIN_NISE = 0x10000 + + // DMAMISSEDFR: Missed Frame and Buffer Overflow Counter Register + // Position of MISSED_FC field. + EMAC_DMA_DMAMISSEDFR_MISSED_FC_Pos = 0x0 + // Bit mask of MISSED_FC field. + EMAC_DMA_DMAMISSEDFR_MISSED_FC_Msk = 0xffff + // Position of OVERFLOW_BMFC field. + EMAC_DMA_DMAMISSEDFR_OVERFLOW_BMFC_Pos = 0x10 + // Bit mask of OVERFLOW_BMFC field. + EMAC_DMA_DMAMISSEDFR_OVERFLOW_BMFC_Msk = 0x10000 + // Bit OVERFLOW_BMFC. + EMAC_DMA_DMAMISSEDFR_OVERFLOW_BMFC = 0x10000 + // Position of OVERFLOW_FC field. + EMAC_DMA_DMAMISSEDFR_OVERFLOW_FC_Pos = 0x11 + // Bit mask of OVERFLOW_FC field. + EMAC_DMA_DMAMISSEDFR_OVERFLOW_FC_Msk = 0xffe0000 + // Position of OVERFLOW_BFOC field. + EMAC_DMA_DMAMISSEDFR_OVERFLOW_BFOC_Pos = 0x1c + // Bit mask of OVERFLOW_BFOC field. + EMAC_DMA_DMAMISSEDFR_OVERFLOW_BFOC_Msk = 0x10000000 + // Bit OVERFLOW_BFOC. + EMAC_DMA_DMAMISSEDFR_OVERFLOW_BFOC = 0x10000000 + + // DMARINTWDTIMER: Watchdog timer count on receive + // Position of RIWTC field. + EMAC_DMA_DMARINTWDTIMER_RIWTC_Pos = 0x0 + // Bit mask of RIWTC field. + EMAC_DMA_DMARINTWDTIMER_RIWTC_Msk = 0xff +) + +// Constants for EMAC_EXT: Ethernet Clock, PHY type, and SRAM configuration registers +const ( + // EX_CLKOUT_CONF: RMII clock divider setting + // Position of DIV_NUM field. + EMAC_EXT_EX_CLKOUT_CONF_DIV_NUM_Pos = 0x0 + // Bit mask of DIV_NUM field. + EMAC_EXT_EX_CLKOUT_CONF_DIV_NUM_Msk = 0xf + // Position of H_DIV_NUM field. + EMAC_EXT_EX_CLKOUT_CONF_H_DIV_NUM_Pos = 0x4 + // Bit mask of H_DIV_NUM field. + EMAC_EXT_EX_CLKOUT_CONF_H_DIV_NUM_Msk = 0xf0 + // Position of DLY_NUM field. + EMAC_EXT_EX_CLKOUT_CONF_DLY_NUM_Pos = 0x8 + // Bit mask of DLY_NUM field. + EMAC_EXT_EX_CLKOUT_CONF_DLY_NUM_Msk = 0x300 + + // EX_OSCCLK_CONF: RMII clock half and whole divider settings + // Position of DIV_NUM_10M field. + EMAC_EXT_EX_OSCCLK_CONF_DIV_NUM_10M_Pos = 0x0 + // Bit mask of DIV_NUM_10M field. + EMAC_EXT_EX_OSCCLK_CONF_DIV_NUM_10M_Msk = 0x3f + // Position of H_DIV_NUM_10M field. + EMAC_EXT_EX_OSCCLK_CONF_H_DIV_NUM_10M_Pos = 0x6 + // Bit mask of H_DIV_NUM_10M field. + EMAC_EXT_EX_OSCCLK_CONF_H_DIV_NUM_10M_Msk = 0xfc0 + // Position of DIV_NUM_100M field. + EMAC_EXT_EX_OSCCLK_CONF_DIV_NUM_100M_Pos = 0xc + // Bit mask of DIV_NUM_100M field. + EMAC_EXT_EX_OSCCLK_CONF_DIV_NUM_100M_Msk = 0x3f000 + // Position of H_DIV_NUM_100M field. + EMAC_EXT_EX_OSCCLK_CONF_H_DIV_NUM_100M_Pos = 0x12 + // Bit mask of H_DIV_NUM_100M field. + EMAC_EXT_EX_OSCCLK_CONF_H_DIV_NUM_100M_Msk = 0xfc0000 + // Position of CLK_SEL field. + EMAC_EXT_EX_OSCCLK_CONF_CLK_SEL_Pos = 0x18 + // Bit mask of CLK_SEL field. + EMAC_EXT_EX_OSCCLK_CONF_CLK_SEL_Msk = 0x1000000 + // Bit CLK_SEL. + EMAC_EXT_EX_OSCCLK_CONF_CLK_SEL = 0x1000000 + + // EX_CLK_CTRL: Clock enable and external/internal clock selection + // Position of EXT_EN field. + EMAC_EXT_EX_CLK_CTRL_EXT_EN_Pos = 0x0 + // Bit mask of EXT_EN field. + EMAC_EXT_EX_CLK_CTRL_EXT_EN_Msk = 0x1 + // Bit EXT_EN. + EMAC_EXT_EX_CLK_CTRL_EXT_EN = 0x1 + // Position of INT_EN field. + EMAC_EXT_EX_CLK_CTRL_INT_EN_Pos = 0x1 + // Bit mask of INT_EN field. + EMAC_EXT_EX_CLK_CTRL_INT_EN_Msk = 0x2 + // Bit INT_EN. + EMAC_EXT_EX_CLK_CTRL_INT_EN = 0x2 + // Position of RX_125_CLK_EN field. + EMAC_EXT_EX_CLK_CTRL_RX_125_CLK_EN_Pos = 0x2 + // Bit mask of RX_125_CLK_EN field. + EMAC_EXT_EX_CLK_CTRL_RX_125_CLK_EN_Msk = 0x4 + // Bit RX_125_CLK_EN. + EMAC_EXT_EX_CLK_CTRL_RX_125_CLK_EN = 0x4 + // Position of MII_CLK_TX_EN field. + EMAC_EXT_EX_CLK_CTRL_MII_CLK_TX_EN_Pos = 0x3 + // Bit mask of MII_CLK_TX_EN field. + EMAC_EXT_EX_CLK_CTRL_MII_CLK_TX_EN_Msk = 0x8 + // Bit MII_CLK_TX_EN. + EMAC_EXT_EX_CLK_CTRL_MII_CLK_TX_EN = 0x8 + // Position of MII_CLK_RX_EN field. + EMAC_EXT_EX_CLK_CTRL_MII_CLK_RX_EN_Pos = 0x4 + // Bit mask of MII_CLK_RX_EN field. + EMAC_EXT_EX_CLK_CTRL_MII_CLK_RX_EN_Msk = 0x10 + // Bit MII_CLK_RX_EN. + EMAC_EXT_EX_CLK_CTRL_MII_CLK_RX_EN = 0x10 + // Position of CLK_EN field. + EMAC_EXT_EX_CLK_CTRL_CLK_EN_Pos = 0x5 + // Bit mask of CLK_EN field. + EMAC_EXT_EX_CLK_CTRL_CLK_EN_Msk = 0x20 + // Bit CLK_EN. + EMAC_EXT_EX_CLK_CTRL_CLK_EN = 0x20 + + // EX_PHYINF_CONF: Selection of MII/RMII phy + // Position of INT_REVMII_RX_CLK_SEL field. + EMAC_EXT_EX_PHYINF_CONF_INT_REVMII_RX_CLK_SEL_Pos = 0x0 + // Bit mask of INT_REVMII_RX_CLK_SEL field. + EMAC_EXT_EX_PHYINF_CONF_INT_REVMII_RX_CLK_SEL_Msk = 0x1 + // Bit INT_REVMII_RX_CLK_SEL. + EMAC_EXT_EX_PHYINF_CONF_INT_REVMII_RX_CLK_SEL = 0x1 + // Position of EXT_REVMII_RX_CLK_SEL field. + EMAC_EXT_EX_PHYINF_CONF_EXT_REVMII_RX_CLK_SEL_Pos = 0x1 + // Bit mask of EXT_REVMII_RX_CLK_SEL field. + EMAC_EXT_EX_PHYINF_CONF_EXT_REVMII_RX_CLK_SEL_Msk = 0x2 + // Bit EXT_REVMII_RX_CLK_SEL. + EMAC_EXT_EX_PHYINF_CONF_EXT_REVMII_RX_CLK_SEL = 0x2 + // Position of SBD_FLOWCTRL field. + EMAC_EXT_EX_PHYINF_CONF_SBD_FLOWCTRL_Pos = 0x2 + // Bit mask of SBD_FLOWCTRL field. + EMAC_EXT_EX_PHYINF_CONF_SBD_FLOWCTRL_Msk = 0x4 + // Bit SBD_FLOWCTRL. + EMAC_EXT_EX_PHYINF_CONF_SBD_FLOWCTRL = 0x4 + // Position of CORE_PHY_ADDR field. + EMAC_EXT_EX_PHYINF_CONF_CORE_PHY_ADDR_Pos = 0x3 + // Bit mask of CORE_PHY_ADDR field. + EMAC_EXT_EX_PHYINF_CONF_CORE_PHY_ADDR_Msk = 0xf8 + // Position of REVMII_PHY_ADDR field. + EMAC_EXT_EX_PHYINF_CONF_REVMII_PHY_ADDR_Pos = 0x8 + // Bit mask of REVMII_PHY_ADDR field. + EMAC_EXT_EX_PHYINF_CONF_REVMII_PHY_ADDR_Msk = 0x1f00 + // Position of PHY_INTF_SEL field. + EMAC_EXT_EX_PHYINF_CONF_PHY_INTF_SEL_Pos = 0xd + // Bit mask of PHY_INTF_SEL field. + EMAC_EXT_EX_PHYINF_CONF_PHY_INTF_SEL_Msk = 0xe000 + // Position of SS_MODE field. + EMAC_EXT_EX_PHYINF_CONF_SS_MODE_Pos = 0x10 + // Bit mask of SS_MODE field. + EMAC_EXT_EX_PHYINF_CONF_SS_MODE_Msk = 0x10000 + // Bit SS_MODE. + EMAC_EXT_EX_PHYINF_CONF_SS_MODE = 0x10000 + // Position of SBD_CLK_GATING_EN field. + EMAC_EXT_EX_PHYINF_CONF_SBD_CLK_GATING_EN_Pos = 0x11 + // Bit mask of SBD_CLK_GATING_EN field. + EMAC_EXT_EX_PHYINF_CONF_SBD_CLK_GATING_EN_Msk = 0x20000 + // Bit SBD_CLK_GATING_EN. + EMAC_EXT_EX_PHYINF_CONF_SBD_CLK_GATING_EN = 0x20000 + // Position of PMT_CTRL_EN field. + EMAC_EXT_EX_PHYINF_CONF_PMT_CTRL_EN_Pos = 0x12 + // Bit mask of PMT_CTRL_EN field. + EMAC_EXT_EX_PHYINF_CONF_PMT_CTRL_EN_Msk = 0x40000 + // Bit PMT_CTRL_EN. + EMAC_EXT_EX_PHYINF_CONF_PMT_CTRL_EN = 0x40000 + // Position of SCR_SMI_DLY_RX_SYNC field. + EMAC_EXT_EX_PHYINF_CONF_SCR_SMI_DLY_RX_SYNC_Pos = 0x13 + // Bit mask of SCR_SMI_DLY_RX_SYNC field. + EMAC_EXT_EX_PHYINF_CONF_SCR_SMI_DLY_RX_SYNC_Msk = 0x80000 + // Bit SCR_SMI_DLY_RX_SYNC. + EMAC_EXT_EX_PHYINF_CONF_SCR_SMI_DLY_RX_SYNC = 0x80000 + // Position of TX_ERR_OUT_EN field. + EMAC_EXT_EX_PHYINF_CONF_TX_ERR_OUT_EN_Pos = 0x14 + // Bit mask of TX_ERR_OUT_EN field. + EMAC_EXT_EX_PHYINF_CONF_TX_ERR_OUT_EN_Msk = 0x100000 + // Bit TX_ERR_OUT_EN. + EMAC_EXT_EX_PHYINF_CONF_TX_ERR_OUT_EN = 0x100000 + + // PD_SEL: Ethernet RAM power-down enable + // Position of RAM_PD_EN field. + EMAC_EXT_PD_SEL_RAM_PD_EN_Pos = 0x0 + // Bit mask of RAM_PD_EN field. + EMAC_EXT_PD_SEL_RAM_PD_EN_Msk = 0x3 +) + +// Constants for EMAC_MAC: Ethernet MAC configuration and control registers +const ( + // EMACCONFIG: MAC configuration + // Position of PLTF field. + EMAC_MAC_EMACCONFIG_PLTF_Pos = 0x0 + // Bit mask of PLTF field. + EMAC_MAC_EMACCONFIG_PLTF_Msk = 0x3 + // Position of RX field. + EMAC_MAC_EMACCONFIG_RX_Pos = 0x2 + // Bit mask of RX field. + EMAC_MAC_EMACCONFIG_RX_Msk = 0x4 + // Bit RX. + EMAC_MAC_EMACCONFIG_RX = 0x4 + // Position of TX field. + EMAC_MAC_EMACCONFIG_TX_Pos = 0x3 + // Bit mask of TX field. + EMAC_MAC_EMACCONFIG_TX_Msk = 0x8 + // Bit TX. + EMAC_MAC_EMACCONFIG_TX = 0x8 + // Position of DEFERRALCHECK field. + EMAC_MAC_EMACCONFIG_DEFERRALCHECK_Pos = 0x4 + // Bit mask of DEFERRALCHECK field. + EMAC_MAC_EMACCONFIG_DEFERRALCHECK_Msk = 0x10 + // Bit DEFERRALCHECK. + EMAC_MAC_EMACCONFIG_DEFERRALCHECK = 0x10 + // Position of BACKOFFLIMIT field. + EMAC_MAC_EMACCONFIG_BACKOFFLIMIT_Pos = 0x5 + // Bit mask of BACKOFFLIMIT field. + EMAC_MAC_EMACCONFIG_BACKOFFLIMIT_Msk = 0x60 + // Position of PADCRCSTRIP field. + EMAC_MAC_EMACCONFIG_PADCRCSTRIP_Pos = 0x7 + // Bit mask of PADCRCSTRIP field. + EMAC_MAC_EMACCONFIG_PADCRCSTRIP_Msk = 0x80 + // Bit PADCRCSTRIP. + EMAC_MAC_EMACCONFIG_PADCRCSTRIP = 0x80 + // Position of RETRY field. + EMAC_MAC_EMACCONFIG_RETRY_Pos = 0x9 + // Bit mask of RETRY field. + EMAC_MAC_EMACCONFIG_RETRY_Msk = 0x200 + // Bit RETRY. + EMAC_MAC_EMACCONFIG_RETRY = 0x200 + // Position of RXIPCOFFLOAD field. + EMAC_MAC_EMACCONFIG_RXIPCOFFLOAD_Pos = 0xa + // Bit mask of RXIPCOFFLOAD field. + EMAC_MAC_EMACCONFIG_RXIPCOFFLOAD_Msk = 0x400 + // Bit RXIPCOFFLOAD. + EMAC_MAC_EMACCONFIG_RXIPCOFFLOAD = 0x400 + // Position of DUPLEX field. + EMAC_MAC_EMACCONFIG_DUPLEX_Pos = 0xb + // Bit mask of DUPLEX field. + EMAC_MAC_EMACCONFIG_DUPLEX_Msk = 0x800 + // Bit DUPLEX. + EMAC_MAC_EMACCONFIG_DUPLEX = 0x800 + // Position of LOOPBACK field. + EMAC_MAC_EMACCONFIG_LOOPBACK_Pos = 0xc + // Bit mask of LOOPBACK field. + EMAC_MAC_EMACCONFIG_LOOPBACK_Msk = 0x1000 + // Bit LOOPBACK. + EMAC_MAC_EMACCONFIG_LOOPBACK = 0x1000 + // Position of RXOWN field. + EMAC_MAC_EMACCONFIG_RXOWN_Pos = 0xd + // Bit mask of RXOWN field. + EMAC_MAC_EMACCONFIG_RXOWN_Msk = 0x2000 + // Bit RXOWN. + EMAC_MAC_EMACCONFIG_RXOWN = 0x2000 + // Position of FESPEED field. + EMAC_MAC_EMACCONFIG_FESPEED_Pos = 0xe + // Bit mask of FESPEED field. + EMAC_MAC_EMACCONFIG_FESPEED_Msk = 0x4000 + // Bit FESPEED. + EMAC_MAC_EMACCONFIG_FESPEED = 0x4000 + // Position of MII field. + EMAC_MAC_EMACCONFIG_MII_Pos = 0xf + // Bit mask of MII field. + EMAC_MAC_EMACCONFIG_MII_Msk = 0x8000 + // Bit MII. + EMAC_MAC_EMACCONFIG_MII = 0x8000 + // Position of DISABLECRS field. + EMAC_MAC_EMACCONFIG_DISABLECRS_Pos = 0x10 + // Bit mask of DISABLECRS field. + EMAC_MAC_EMACCONFIG_DISABLECRS_Msk = 0x10000 + // Bit DISABLECRS. + EMAC_MAC_EMACCONFIG_DISABLECRS = 0x10000 + // Position of INTERFRAMEGAP field. + EMAC_MAC_EMACCONFIG_INTERFRAMEGAP_Pos = 0x11 + // Bit mask of INTERFRAMEGAP field. + EMAC_MAC_EMACCONFIG_INTERFRAMEGAP_Msk = 0xe0000 + // Position of JUMBOFRAME field. + EMAC_MAC_EMACCONFIG_JUMBOFRAME_Pos = 0x14 + // Bit mask of JUMBOFRAME field. + EMAC_MAC_EMACCONFIG_JUMBOFRAME_Msk = 0x100000 + // Bit JUMBOFRAME. + EMAC_MAC_EMACCONFIG_JUMBOFRAME = 0x100000 + // Position of JABBER field. + EMAC_MAC_EMACCONFIG_JABBER_Pos = 0x16 + // Bit mask of JABBER field. + EMAC_MAC_EMACCONFIG_JABBER_Msk = 0x400000 + // Bit JABBER. + EMAC_MAC_EMACCONFIG_JABBER = 0x400000 + // Position of WATCHDOG field. + EMAC_MAC_EMACCONFIG_WATCHDOG_Pos = 0x17 + // Bit mask of WATCHDOG field. + EMAC_MAC_EMACCONFIG_WATCHDOG_Msk = 0x800000 + // Bit WATCHDOG. + EMAC_MAC_EMACCONFIG_WATCHDOG = 0x800000 + // Position of ASS2KP field. + EMAC_MAC_EMACCONFIG_ASS2KP_Pos = 0x1b + // Bit mask of ASS2KP field. + EMAC_MAC_EMACCONFIG_ASS2KP_Msk = 0x8000000 + // Bit ASS2KP. + EMAC_MAC_EMACCONFIG_ASS2KP = 0x8000000 + // Position of SAIRC field. + EMAC_MAC_EMACCONFIG_SAIRC_Pos = 0x1c + // Bit mask of SAIRC field. + EMAC_MAC_EMACCONFIG_SAIRC_Msk = 0x70000000 + + // EMACFF: Frame filter settings + // Position of PMODE field. + EMAC_MAC_EMACFF_PMODE_Pos = 0x0 + // Bit mask of PMODE field. + EMAC_MAC_EMACFF_PMODE_Msk = 0x1 + // Bit PMODE. + EMAC_MAC_EMACFF_PMODE = 0x1 + // Position of DAIF field. + EMAC_MAC_EMACFF_DAIF_Pos = 0x3 + // Bit mask of DAIF field. + EMAC_MAC_EMACFF_DAIF_Msk = 0x8 + // Bit DAIF. + EMAC_MAC_EMACFF_DAIF = 0x8 + // Position of PAM field. + EMAC_MAC_EMACFF_PAM_Pos = 0x4 + // Bit mask of PAM field. + EMAC_MAC_EMACFF_PAM_Msk = 0x10 + // Bit PAM. + EMAC_MAC_EMACFF_PAM = 0x10 + // Position of DBF field. + EMAC_MAC_EMACFF_DBF_Pos = 0x5 + // Bit mask of DBF field. + EMAC_MAC_EMACFF_DBF_Msk = 0x20 + // Bit DBF. + EMAC_MAC_EMACFF_DBF = 0x20 + // Position of PCF field. + EMAC_MAC_EMACFF_PCF_Pos = 0x6 + // Bit mask of PCF field. + EMAC_MAC_EMACFF_PCF_Msk = 0xc0 + // Position of SAIF field. + EMAC_MAC_EMACFF_SAIF_Pos = 0x8 + // Bit mask of SAIF field. + EMAC_MAC_EMACFF_SAIF_Msk = 0x100 + // Bit SAIF. + EMAC_MAC_EMACFF_SAIF = 0x100 + // Position of SAFE field. + EMAC_MAC_EMACFF_SAFE_Pos = 0x9 + // Bit mask of SAFE field. + EMAC_MAC_EMACFF_SAFE_Msk = 0x200 + // Bit SAFE. + EMAC_MAC_EMACFF_SAFE = 0x200 + // Position of RECEIVE_ALL field. + EMAC_MAC_EMACFF_RECEIVE_ALL_Pos = 0x1f + // Bit mask of RECEIVE_ALL field. + EMAC_MAC_EMACFF_RECEIVE_ALL_Msk = 0x80000000 + // Bit RECEIVE_ALL. + EMAC_MAC_EMACFF_RECEIVE_ALL = 0x80000000 + + // EMACGMIIADDR: PHY configuration access + // Position of MIIBUSY field. + EMAC_MAC_EMACGMIIADDR_MIIBUSY_Pos = 0x0 + // Bit mask of MIIBUSY field. + EMAC_MAC_EMACGMIIADDR_MIIBUSY_Msk = 0x1 + // Bit MIIBUSY. + EMAC_MAC_EMACGMIIADDR_MIIBUSY = 0x1 + // Position of MIIWRITE field. + EMAC_MAC_EMACGMIIADDR_MIIWRITE_Pos = 0x1 + // Bit mask of MIIWRITE field. + EMAC_MAC_EMACGMIIADDR_MIIWRITE_Msk = 0x2 + // Bit MIIWRITE. + EMAC_MAC_EMACGMIIADDR_MIIWRITE = 0x2 + // Position of MIICSRCLK field. + EMAC_MAC_EMACGMIIADDR_MIICSRCLK_Pos = 0x2 + // Bit mask of MIICSRCLK field. + EMAC_MAC_EMACGMIIADDR_MIICSRCLK_Msk = 0x3c + // Position of MIIREG field. + EMAC_MAC_EMACGMIIADDR_MIIREG_Pos = 0x6 + // Bit mask of MIIREG field. + EMAC_MAC_EMACGMIIADDR_MIIREG_Msk = 0x7c0 + // Position of MIIDEV field. + EMAC_MAC_EMACGMIIADDR_MIIDEV_Pos = 0xb + // Bit mask of MIIDEV field. + EMAC_MAC_EMACGMIIADDR_MIIDEV_Msk = 0xf800 + + // EMACMIIDATA: PHY data read write + // Position of MII_DATA field. + EMAC_MAC_EMACMIIDATA_MII_DATA_Pos = 0x0 + // Bit mask of MII_DATA field. + EMAC_MAC_EMACMIIDATA_MII_DATA_Msk = 0xffff + + // EMACFC: Frame flow control + // Position of FCBBA field. + EMAC_MAC_EMACFC_FCBBA_Pos = 0x0 + // Bit mask of FCBBA field. + EMAC_MAC_EMACFC_FCBBA_Msk = 0x1 + // Bit FCBBA. + EMAC_MAC_EMACFC_FCBBA = 0x1 + // Position of TFCE field. + EMAC_MAC_EMACFC_TFCE_Pos = 0x1 + // Bit mask of TFCE field. + EMAC_MAC_EMACFC_TFCE_Msk = 0x2 + // Bit TFCE. + EMAC_MAC_EMACFC_TFCE = 0x2 + // Position of RFCE field. + EMAC_MAC_EMACFC_RFCE_Pos = 0x2 + // Bit mask of RFCE field. + EMAC_MAC_EMACFC_RFCE_Msk = 0x4 + // Bit RFCE. + EMAC_MAC_EMACFC_RFCE = 0x4 + // Position of UPFD field. + EMAC_MAC_EMACFC_UPFD_Pos = 0x3 + // Bit mask of UPFD field. + EMAC_MAC_EMACFC_UPFD_Msk = 0x8 + // Bit UPFD. + EMAC_MAC_EMACFC_UPFD = 0x8 + // Position of PLT field. + EMAC_MAC_EMACFC_PLT_Pos = 0x4 + // Bit mask of PLT field. + EMAC_MAC_EMACFC_PLT_Msk = 0x30 + // Position of DZPQ field. + EMAC_MAC_EMACFC_DZPQ_Pos = 0x7 + // Bit mask of DZPQ field. + EMAC_MAC_EMACFC_DZPQ_Msk = 0x80 + // Bit DZPQ. + EMAC_MAC_EMACFC_DZPQ = 0x80 + // Position of PAUSE_TIME field. + EMAC_MAC_EMACFC_PAUSE_TIME_Pos = 0x10 + // Bit mask of PAUSE_TIME field. + EMAC_MAC_EMACFC_PAUSE_TIME_Msk = 0xffff0000 + + // EMACDEBUG: Status debugging bits + // Position of MACRPES field. + EMAC_MAC_EMACDEBUG_MACRPES_Pos = 0x0 + // Bit mask of MACRPES field. + EMAC_MAC_EMACDEBUG_MACRPES_Msk = 0x1 + // Bit MACRPES. + EMAC_MAC_EMACDEBUG_MACRPES = 0x1 + // Position of MACRFFCS field. + EMAC_MAC_EMACDEBUG_MACRFFCS_Pos = 0x1 + // Bit mask of MACRFFCS field. + EMAC_MAC_EMACDEBUG_MACRFFCS_Msk = 0x6 + // Position of MTLRFWCAS field. + EMAC_MAC_EMACDEBUG_MTLRFWCAS_Pos = 0x4 + // Bit mask of MTLRFWCAS field. + EMAC_MAC_EMACDEBUG_MTLRFWCAS_Msk = 0x10 + // Bit MTLRFWCAS. + EMAC_MAC_EMACDEBUG_MTLRFWCAS = 0x10 + // Position of MTLRFRCS field. + EMAC_MAC_EMACDEBUG_MTLRFRCS_Pos = 0x5 + // Bit mask of MTLRFRCS field. + EMAC_MAC_EMACDEBUG_MTLRFRCS_Msk = 0x60 + // Position of MTLRFFLS field. + EMAC_MAC_EMACDEBUG_MTLRFFLS_Pos = 0x8 + // Bit mask of MTLRFFLS field. + EMAC_MAC_EMACDEBUG_MTLRFFLS_Msk = 0x300 + // Position of MACTPES field. + EMAC_MAC_EMACDEBUG_MACTPES_Pos = 0x10 + // Bit mask of MACTPES field. + EMAC_MAC_EMACDEBUG_MACTPES_Msk = 0x10000 + // Bit MACTPES. + EMAC_MAC_EMACDEBUG_MACTPES = 0x10000 + // Position of MACTFCS field. + EMAC_MAC_EMACDEBUG_MACTFCS_Pos = 0x11 + // Bit mask of MACTFCS field. + EMAC_MAC_EMACDEBUG_MACTFCS_Msk = 0x60000 + // Position of MACTP field. + EMAC_MAC_EMACDEBUG_MACTP_Pos = 0x13 + // Bit mask of MACTP field. + EMAC_MAC_EMACDEBUG_MACTP_Msk = 0x80000 + // Bit MACTP. + EMAC_MAC_EMACDEBUG_MACTP = 0x80000 + // Position of MTLTFRCS field. + EMAC_MAC_EMACDEBUG_MTLTFRCS_Pos = 0x14 + // Bit mask of MTLTFRCS field. + EMAC_MAC_EMACDEBUG_MTLTFRCS_Msk = 0x300000 + // Position of MTLTFWCS field. + EMAC_MAC_EMACDEBUG_MTLTFWCS_Pos = 0x16 + // Bit mask of MTLTFWCS field. + EMAC_MAC_EMACDEBUG_MTLTFWCS_Msk = 0x400000 + // Bit MTLTFWCS. + EMAC_MAC_EMACDEBUG_MTLTFWCS = 0x400000 + // Position of MTLTFNES field. + EMAC_MAC_EMACDEBUG_MTLTFNES_Pos = 0x18 + // Bit mask of MTLTFNES field. + EMAC_MAC_EMACDEBUG_MTLTFNES_Msk = 0x1000000 + // Bit MTLTFNES. + EMAC_MAC_EMACDEBUG_MTLTFNES = 0x1000000 + // Position of MTLTSFFS field. + EMAC_MAC_EMACDEBUG_MTLTSFFS_Pos = 0x19 + // Bit mask of MTLTSFFS field. + EMAC_MAC_EMACDEBUG_MTLTSFFS_Msk = 0x2000000 + // Bit MTLTSFFS. + EMAC_MAC_EMACDEBUG_MTLTSFFS = 0x2000000 + + // PMT_CSR: PMT Control and Status + // Position of PWRDWN field. + EMAC_MAC_PMT_CSR_PWRDWN_Pos = 0x0 + // Bit mask of PWRDWN field. + EMAC_MAC_PMT_CSR_PWRDWN_Msk = 0x1 + // Bit PWRDWN. + EMAC_MAC_PMT_CSR_PWRDWN = 0x1 + // Position of MGKPKTEN field. + EMAC_MAC_PMT_CSR_MGKPKTEN_Pos = 0x1 + // Bit mask of MGKPKTEN field. + EMAC_MAC_PMT_CSR_MGKPKTEN_Msk = 0x2 + // Bit MGKPKTEN. + EMAC_MAC_PMT_CSR_MGKPKTEN = 0x2 + // Position of RWKPKTEN field. + EMAC_MAC_PMT_CSR_RWKPKTEN_Pos = 0x2 + // Bit mask of RWKPKTEN field. + EMAC_MAC_PMT_CSR_RWKPKTEN_Msk = 0x4 + // Bit RWKPKTEN. + EMAC_MAC_PMT_CSR_RWKPKTEN = 0x4 + // Position of MGKPRCVD field. + EMAC_MAC_PMT_CSR_MGKPRCVD_Pos = 0x5 + // Bit mask of MGKPRCVD field. + EMAC_MAC_PMT_CSR_MGKPRCVD_Msk = 0x20 + // Bit MGKPRCVD. + EMAC_MAC_PMT_CSR_MGKPRCVD = 0x20 + // Position of RWKPRCVD field. + EMAC_MAC_PMT_CSR_RWKPRCVD_Pos = 0x6 + // Bit mask of RWKPRCVD field. + EMAC_MAC_PMT_CSR_RWKPRCVD_Msk = 0x40 + // Bit RWKPRCVD. + EMAC_MAC_PMT_CSR_RWKPRCVD = 0x40 + // Position of GLBLUCAST field. + EMAC_MAC_PMT_CSR_GLBLUCAST_Pos = 0x9 + // Bit mask of GLBLUCAST field. + EMAC_MAC_PMT_CSR_GLBLUCAST_Msk = 0x200 + // Bit GLBLUCAST. + EMAC_MAC_PMT_CSR_GLBLUCAST = 0x200 + // Position of RWKPTR field. + EMAC_MAC_PMT_CSR_RWKPTR_Pos = 0x18 + // Bit mask of RWKPTR field. + EMAC_MAC_PMT_CSR_RWKPTR_Msk = 0x1f000000 + // Position of RWKFILTRST field. + EMAC_MAC_PMT_CSR_RWKFILTRST_Pos = 0x1f + // Bit mask of RWKFILTRST field. + EMAC_MAC_PMT_CSR_RWKFILTRST_Msk = 0x80000000 + // Bit RWKFILTRST. + EMAC_MAC_PMT_CSR_RWKFILTRST = 0x80000000 + + // EMACLPI_CRS: LPI Control and Status + // Position of TLPIEN field. + EMAC_MAC_EMACLPI_CRS_TLPIEN_Pos = 0x0 + // Bit mask of TLPIEN field. + EMAC_MAC_EMACLPI_CRS_TLPIEN_Msk = 0x1 + // Bit TLPIEN. + EMAC_MAC_EMACLPI_CRS_TLPIEN = 0x1 + // Position of TLPIEX field. + EMAC_MAC_EMACLPI_CRS_TLPIEX_Pos = 0x1 + // Bit mask of TLPIEX field. + EMAC_MAC_EMACLPI_CRS_TLPIEX_Msk = 0x2 + // Bit TLPIEX. + EMAC_MAC_EMACLPI_CRS_TLPIEX = 0x2 + // Position of RLPIEN field. + EMAC_MAC_EMACLPI_CRS_RLPIEN_Pos = 0x2 + // Bit mask of RLPIEN field. + EMAC_MAC_EMACLPI_CRS_RLPIEN_Msk = 0x4 + // Bit RLPIEN. + EMAC_MAC_EMACLPI_CRS_RLPIEN = 0x4 + // Position of RLPIEX field. + EMAC_MAC_EMACLPI_CRS_RLPIEX_Pos = 0x3 + // Bit mask of RLPIEX field. + EMAC_MAC_EMACLPI_CRS_RLPIEX_Msk = 0x8 + // Bit RLPIEX. + EMAC_MAC_EMACLPI_CRS_RLPIEX = 0x8 + // Position of TLPIST field. + EMAC_MAC_EMACLPI_CRS_TLPIST_Pos = 0x8 + // Bit mask of TLPIST field. + EMAC_MAC_EMACLPI_CRS_TLPIST_Msk = 0x100 + // Bit TLPIST. + EMAC_MAC_EMACLPI_CRS_TLPIST = 0x100 + // Position of RLPIST field. + EMAC_MAC_EMACLPI_CRS_RLPIST_Pos = 0x9 + // Bit mask of RLPIST field. + EMAC_MAC_EMACLPI_CRS_RLPIST_Msk = 0x200 + // Bit RLPIST. + EMAC_MAC_EMACLPI_CRS_RLPIST = 0x200 + // Position of LPIEN field. + EMAC_MAC_EMACLPI_CRS_LPIEN_Pos = 0x10 + // Bit mask of LPIEN field. + EMAC_MAC_EMACLPI_CRS_LPIEN_Msk = 0x10000 + // Bit LPIEN. + EMAC_MAC_EMACLPI_CRS_LPIEN = 0x10000 + // Position of PLS field. + EMAC_MAC_EMACLPI_CRS_PLS_Pos = 0x11 + // Bit mask of PLS field. + EMAC_MAC_EMACLPI_CRS_PLS_Msk = 0x20000 + // Bit PLS. + EMAC_MAC_EMACLPI_CRS_PLS = 0x20000 + // Position of LPITXA field. + EMAC_MAC_EMACLPI_CRS_LPITXA_Pos = 0x13 + // Bit mask of LPITXA field. + EMAC_MAC_EMACLPI_CRS_LPITXA_Msk = 0x80000 + // Bit LPITXA. + EMAC_MAC_EMACLPI_CRS_LPITXA = 0x80000 + + // EMACLPITIMERSCONTROL: LPI Timers Control + // Position of LPI_TW_TIMER field. + EMAC_MAC_EMACLPITIMERSCONTROL_LPI_TW_TIMER_Pos = 0x0 + // Bit mask of LPI_TW_TIMER field. + EMAC_MAC_EMACLPITIMERSCONTROL_LPI_TW_TIMER_Msk = 0xffff + // Position of LPI_LS_TIMER field. + EMAC_MAC_EMACLPITIMERSCONTROL_LPI_LS_TIMER_Pos = 0x10 + // Bit mask of LPI_LS_TIMER field. + EMAC_MAC_EMACLPITIMERSCONTROL_LPI_LS_TIMER_Msk = 0x3ff0000 + + // EMACINTS: Interrupt status + // Position of PMTINTS field. + EMAC_MAC_EMACINTS_PMTINTS_Pos = 0x3 + // Bit mask of PMTINTS field. + EMAC_MAC_EMACINTS_PMTINTS_Msk = 0x8 + // Bit PMTINTS. + EMAC_MAC_EMACINTS_PMTINTS = 0x8 + // Position of LPIIS field. + EMAC_MAC_EMACINTS_LPIIS_Pos = 0xa + // Bit mask of LPIIS field. + EMAC_MAC_EMACINTS_LPIIS_Msk = 0x400 + // Bit LPIIS. + EMAC_MAC_EMACINTS_LPIIS = 0x400 + + // EMACINTMASK: Interrupt mask + // Position of PMTINTMASK field. + EMAC_MAC_EMACINTMASK_PMTINTMASK_Pos = 0x3 + // Bit mask of PMTINTMASK field. + EMAC_MAC_EMACINTMASK_PMTINTMASK_Msk = 0x8 + // Bit PMTINTMASK. + EMAC_MAC_EMACINTMASK_PMTINTMASK = 0x8 + // Position of LPIINTMASK field. + EMAC_MAC_EMACINTMASK_LPIINTMASK_Pos = 0xa + // Bit mask of LPIINTMASK field. + EMAC_MAC_EMACINTMASK_LPIINTMASK_Msk = 0x400 + // Bit LPIINTMASK. + EMAC_MAC_EMACINTMASK_LPIINTMASK = 0x400 + + // EMACADDR0HIGH: Upper 16 bits of the first 6-byte MAC address + // Position of ADDRESS0_HI field. + EMAC_MAC_EMACADDR0HIGH_ADDRESS0_HI_Pos = 0x0 + // Bit mask of ADDRESS0_HI field. + EMAC_MAC_EMACADDR0HIGH_ADDRESS0_HI_Msk = 0xffff + // Position of ADDRESS_ENABLE0 field. + EMAC_MAC_EMACADDR0HIGH_ADDRESS_ENABLE0_Pos = 0x1f + // Bit mask of ADDRESS_ENABLE0 field. + EMAC_MAC_EMACADDR0HIGH_ADDRESS_ENABLE0_Msk = 0x80000000 + // Bit ADDRESS_ENABLE0. + EMAC_MAC_EMACADDR0HIGH_ADDRESS_ENABLE0 = 0x80000000 + + // EMACADDR1HIGH: Upper 16 bits of the second 6-byte MAC address + // Position of MAC_ADDRESS1_HI field. + EMAC_MAC_EMACADDR1HIGH_MAC_ADDRESS1_HI_Pos = 0x0 + // Bit mask of MAC_ADDRESS1_HI field. + EMAC_MAC_EMACADDR1HIGH_MAC_ADDRESS1_HI_Msk = 0xffff + // Position of MASK_BYTE_CONTROL field. + EMAC_MAC_EMACADDR1HIGH_MASK_BYTE_CONTROL_Pos = 0x18 + // Bit mask of MASK_BYTE_CONTROL field. + EMAC_MAC_EMACADDR1HIGH_MASK_BYTE_CONTROL_Msk = 0x3f000000 + // Position of SOURCE_ADDRESS field. + EMAC_MAC_EMACADDR1HIGH_SOURCE_ADDRESS_Pos = 0x1e + // Bit mask of SOURCE_ADDRESS field. + EMAC_MAC_EMACADDR1HIGH_SOURCE_ADDRESS_Msk = 0x40000000 + // Bit SOURCE_ADDRESS. + EMAC_MAC_EMACADDR1HIGH_SOURCE_ADDRESS = 0x40000000 + // Position of ADDRESS_ENABLE1 field. + EMAC_MAC_EMACADDR1HIGH_ADDRESS_ENABLE1_Pos = 0x1f + // Bit mask of ADDRESS_ENABLE1 field. + EMAC_MAC_EMACADDR1HIGH_ADDRESS_ENABLE1_Msk = 0x80000000 + // Bit ADDRESS_ENABLE1. + EMAC_MAC_EMACADDR1HIGH_ADDRESS_ENABLE1 = 0x80000000 + + // EMACADDR2HIGH: Upper 16 bits of the third 6-byte MAC address + // Position of MAC_ADDRESS2_HI field. + EMAC_MAC_EMACADDR2HIGH_MAC_ADDRESS2_HI_Pos = 0x0 + // Bit mask of MAC_ADDRESS2_HI field. + EMAC_MAC_EMACADDR2HIGH_MAC_ADDRESS2_HI_Msk = 0xffff + // Position of MASK_BYTE_CONTROL2 field. + EMAC_MAC_EMACADDR2HIGH_MASK_BYTE_CONTROL2_Pos = 0x18 + // Bit mask of MASK_BYTE_CONTROL2 field. + EMAC_MAC_EMACADDR2HIGH_MASK_BYTE_CONTROL2_Msk = 0x3f000000 + // Position of SOURCE_ADDRESS2 field. + EMAC_MAC_EMACADDR2HIGH_SOURCE_ADDRESS2_Pos = 0x1e + // Bit mask of SOURCE_ADDRESS2 field. + EMAC_MAC_EMACADDR2HIGH_SOURCE_ADDRESS2_Msk = 0x40000000 + // Bit SOURCE_ADDRESS2. + EMAC_MAC_EMACADDR2HIGH_SOURCE_ADDRESS2 = 0x40000000 + // Position of ADDRESS_ENABLE2 field. + EMAC_MAC_EMACADDR2HIGH_ADDRESS_ENABLE2_Pos = 0x1f + // Bit mask of ADDRESS_ENABLE2 field. + EMAC_MAC_EMACADDR2HIGH_ADDRESS_ENABLE2_Msk = 0x80000000 + // Bit ADDRESS_ENABLE2. + EMAC_MAC_EMACADDR2HIGH_ADDRESS_ENABLE2 = 0x80000000 + + // EMACADDR3HIGH: Upper 16 bits of the fourth 6-byte MAC address + // Position of MAC_ADDRESS3_HI field. + EMAC_MAC_EMACADDR3HIGH_MAC_ADDRESS3_HI_Pos = 0x0 + // Bit mask of MAC_ADDRESS3_HI field. + EMAC_MAC_EMACADDR3HIGH_MAC_ADDRESS3_HI_Msk = 0xffff + // Position of MASK_BYTE_CONTROL3 field. + EMAC_MAC_EMACADDR3HIGH_MASK_BYTE_CONTROL3_Pos = 0x18 + // Bit mask of MASK_BYTE_CONTROL3 field. + EMAC_MAC_EMACADDR3HIGH_MASK_BYTE_CONTROL3_Msk = 0x3f000000 + // Position of SOURCE_ADDRESS3 field. + EMAC_MAC_EMACADDR3HIGH_SOURCE_ADDRESS3_Pos = 0x1e + // Bit mask of SOURCE_ADDRESS3 field. + EMAC_MAC_EMACADDR3HIGH_SOURCE_ADDRESS3_Msk = 0x40000000 + // Bit SOURCE_ADDRESS3. + EMAC_MAC_EMACADDR3HIGH_SOURCE_ADDRESS3 = 0x40000000 + // Position of ADDRESS_ENABLE3 field. + EMAC_MAC_EMACADDR3HIGH_ADDRESS_ENABLE3_Pos = 0x1f + // Bit mask of ADDRESS_ENABLE3 field. + EMAC_MAC_EMACADDR3HIGH_ADDRESS_ENABLE3_Msk = 0x80000000 + // Bit ADDRESS_ENABLE3. + EMAC_MAC_EMACADDR3HIGH_ADDRESS_ENABLE3 = 0x80000000 + + // EMACADDR4HIGH: Upper 16 bits of the fifth 6-byte MAC address + // Position of MAC_ADDRESS4_HI field. + EMAC_MAC_EMACADDR4HIGH_MAC_ADDRESS4_HI_Pos = 0x0 + // Bit mask of MAC_ADDRESS4_HI field. + EMAC_MAC_EMACADDR4HIGH_MAC_ADDRESS4_HI_Msk = 0xffff + // Position of MASK_BYTE_CONTROL4 field. + EMAC_MAC_EMACADDR4HIGH_MASK_BYTE_CONTROL4_Pos = 0x18 + // Bit mask of MASK_BYTE_CONTROL4 field. + EMAC_MAC_EMACADDR4HIGH_MASK_BYTE_CONTROL4_Msk = 0x3f000000 + // Position of SOURCE_ADDRESS4 field. + EMAC_MAC_EMACADDR4HIGH_SOURCE_ADDRESS4_Pos = 0x1e + // Bit mask of SOURCE_ADDRESS4 field. + EMAC_MAC_EMACADDR4HIGH_SOURCE_ADDRESS4_Msk = 0x40000000 + // Bit SOURCE_ADDRESS4. + EMAC_MAC_EMACADDR4HIGH_SOURCE_ADDRESS4 = 0x40000000 + // Position of ADDRESS_ENABLE4 field. + EMAC_MAC_EMACADDR4HIGH_ADDRESS_ENABLE4_Pos = 0x1f + // Bit mask of ADDRESS_ENABLE4 field. + EMAC_MAC_EMACADDR4HIGH_ADDRESS_ENABLE4_Msk = 0x80000000 + // Bit ADDRESS_ENABLE4. + EMAC_MAC_EMACADDR4HIGH_ADDRESS_ENABLE4 = 0x80000000 + + // EMACADDR5HIGH: Upper 16 bits of the sixth 6-byte MAC address + // Position of MAC_ADDRESS5_HI field. + EMAC_MAC_EMACADDR5HIGH_MAC_ADDRESS5_HI_Pos = 0x0 + // Bit mask of MAC_ADDRESS5_HI field. + EMAC_MAC_EMACADDR5HIGH_MAC_ADDRESS5_HI_Msk = 0xffff + // Position of MASK_BYTE_CONTROL5 field. + EMAC_MAC_EMACADDR5HIGH_MASK_BYTE_CONTROL5_Pos = 0x18 + // Bit mask of MASK_BYTE_CONTROL5 field. + EMAC_MAC_EMACADDR5HIGH_MASK_BYTE_CONTROL5_Msk = 0x3f000000 + // Position of SOURCE_ADDRESS5 field. + EMAC_MAC_EMACADDR5HIGH_SOURCE_ADDRESS5_Pos = 0x1e + // Bit mask of SOURCE_ADDRESS5 field. + EMAC_MAC_EMACADDR5HIGH_SOURCE_ADDRESS5_Msk = 0x40000000 + // Bit SOURCE_ADDRESS5. + EMAC_MAC_EMACADDR5HIGH_SOURCE_ADDRESS5 = 0x40000000 + // Position of ADDRESS_ENABLE5 field. + EMAC_MAC_EMACADDR5HIGH_ADDRESS_ENABLE5_Pos = 0x1f + // Bit mask of ADDRESS_ENABLE5 field. + EMAC_MAC_EMACADDR5HIGH_ADDRESS_ENABLE5_Msk = 0x80000000 + // Bit ADDRESS_ENABLE5. + EMAC_MAC_EMACADDR5HIGH_ADDRESS_ENABLE5 = 0x80000000 + + // EMACADDR6HIGH: Upper 16 bits of the seventh 6-byte MAC address + // Position of MAC_ADDRESS6_HI field. + EMAC_MAC_EMACADDR6HIGH_MAC_ADDRESS6_HI_Pos = 0x0 + // Bit mask of MAC_ADDRESS6_HI field. + EMAC_MAC_EMACADDR6HIGH_MAC_ADDRESS6_HI_Msk = 0xffff + // Position of MASK_BYTE_CONTROL6 field. + EMAC_MAC_EMACADDR6HIGH_MASK_BYTE_CONTROL6_Pos = 0x18 + // Bit mask of MASK_BYTE_CONTROL6 field. + EMAC_MAC_EMACADDR6HIGH_MASK_BYTE_CONTROL6_Msk = 0x3f000000 + // Position of SOURCE_ADDRESS6 field. + EMAC_MAC_EMACADDR6HIGH_SOURCE_ADDRESS6_Pos = 0x1e + // Bit mask of SOURCE_ADDRESS6 field. + EMAC_MAC_EMACADDR6HIGH_SOURCE_ADDRESS6_Msk = 0x40000000 + // Bit SOURCE_ADDRESS6. + EMAC_MAC_EMACADDR6HIGH_SOURCE_ADDRESS6 = 0x40000000 + // Position of ADDRESS_ENABLE6 field. + EMAC_MAC_EMACADDR6HIGH_ADDRESS_ENABLE6_Pos = 0x1f + // Bit mask of ADDRESS_ENABLE6 field. + EMAC_MAC_EMACADDR6HIGH_ADDRESS_ENABLE6_Msk = 0x80000000 + // Bit ADDRESS_ENABLE6. + EMAC_MAC_EMACADDR6HIGH_ADDRESS_ENABLE6 = 0x80000000 + + // EMACADDR7HIGH: Upper 16 bits of the eighth 6-byte MAC address + // Position of MAC_ADDRESS7_HI field. + EMAC_MAC_EMACADDR7HIGH_MAC_ADDRESS7_HI_Pos = 0x0 + // Bit mask of MAC_ADDRESS7_HI field. + EMAC_MAC_EMACADDR7HIGH_MAC_ADDRESS7_HI_Msk = 0xffff + // Position of MASK_BYTE_CONTROL7 field. + EMAC_MAC_EMACADDR7HIGH_MASK_BYTE_CONTROL7_Pos = 0x18 + // Bit mask of MASK_BYTE_CONTROL7 field. + EMAC_MAC_EMACADDR7HIGH_MASK_BYTE_CONTROL7_Msk = 0x3f000000 + // Position of SOURCE_ADDRESS7 field. + EMAC_MAC_EMACADDR7HIGH_SOURCE_ADDRESS7_Pos = 0x1e + // Bit mask of SOURCE_ADDRESS7 field. + EMAC_MAC_EMACADDR7HIGH_SOURCE_ADDRESS7_Msk = 0x40000000 + // Bit SOURCE_ADDRESS7. + EMAC_MAC_EMACADDR7HIGH_SOURCE_ADDRESS7 = 0x40000000 + // Position of ADDRESS_ENABLE7 field. + EMAC_MAC_EMACADDR7HIGH_ADDRESS_ENABLE7_Pos = 0x1f + // Bit mask of ADDRESS_ENABLE7 field. + EMAC_MAC_EMACADDR7HIGH_ADDRESS_ENABLE7_Msk = 0x80000000 + // Bit ADDRESS_ENABLE7. + EMAC_MAC_EMACADDR7HIGH_ADDRESS_ENABLE7 = 0x80000000 + + // EMACCSTATUS: Link communication status + // Position of LINK_MODE field. + EMAC_MAC_EMACCSTATUS_LINK_MODE_Pos = 0x0 + // Bit mask of LINK_MODE field. + EMAC_MAC_EMACCSTATUS_LINK_MODE_Msk = 0x1 + // Bit LINK_MODE. + EMAC_MAC_EMACCSTATUS_LINK_MODE = 0x1 + // Position of LINK_SPEED field. + EMAC_MAC_EMACCSTATUS_LINK_SPEED_Pos = 0x1 + // Bit mask of LINK_SPEED field. + EMAC_MAC_EMACCSTATUS_LINK_SPEED_Msk = 0x6 + // Position of JABBER_TIMEOUT field. + EMAC_MAC_EMACCSTATUS_JABBER_TIMEOUT_Pos = 0x4 + // Bit mask of JABBER_TIMEOUT field. + EMAC_MAC_EMACCSTATUS_JABBER_TIMEOUT_Msk = 0x10 + // Bit JABBER_TIMEOUT. + EMAC_MAC_EMACCSTATUS_JABBER_TIMEOUT = 0x10 + + // EMACWDOGTO: Watchdog timeout control + // Position of WDOGTO field. + EMAC_MAC_EMACWDOGTO_WDOGTO_Pos = 0x0 + // Bit mask of WDOGTO field. + EMAC_MAC_EMACWDOGTO_WDOGTO_Msk = 0x3fff + // Position of PWDOGEN field. + EMAC_MAC_EMACWDOGTO_PWDOGEN_Pos = 0x10 + // Bit mask of PWDOGEN field. + EMAC_MAC_EMACWDOGTO_PWDOGEN_Msk = 0x10000 + // Bit PWDOGEN. + EMAC_MAC_EMACWDOGTO_PWDOGEN = 0x10000 +) + +// Constants for FLASH_ENCRYPTION: FLASH_ENCRYPTION Peripheral +const ( + // BUFFER_0 + // Position of BUFFER field. + FLASH_ENCRYPTION_BUFFER_BUFFER_Pos = 0x0 + // Bit mask of BUFFER field. + FLASH_ENCRYPTION_BUFFER_BUFFER_Msk = 0xff + + // START + // Position of FLASH_START field. + FLASH_ENCRYPTION_START_FLASH_START_Pos = 0x0 + // Bit mask of FLASH_START field. + FLASH_ENCRYPTION_START_FLASH_START_Msk = 0xff + + // ADDRESS + // Position of ADDRESS field. + FLASH_ENCRYPTION_ADDRESS_ADDRESS_Pos = 0x0 + // Bit mask of ADDRESS field. + FLASH_ENCRYPTION_ADDRESS_ADDRESS_Msk = 0xff + + // DONE + // Position of FLASH_DONE field. + FLASH_ENCRYPTION_DONE_FLASH_DONE_Pos = 0x0 + // Bit mask of FLASH_DONE field. + FLASH_ENCRYPTION_DONE_FLASH_DONE_Msk = 0x1 + // Bit FLASH_DONE. + FLASH_ENCRYPTION_DONE_FLASH_DONE = 0x1 +) + +// Constants for FRC_TIMER: FRC_TIMER Peripheral +const ( + // TIMER_LOAD + // Position of VALUE field. + FRC_TIMER_LOAD_VALUE_Pos = 0x0 + // Bit mask of VALUE field. + FRC_TIMER_LOAD_VALUE_Msk = 0xff + + // TIMER_COUNT + // Position of TIMER_COUNT field. + FRC_TIMER_COUNT_TIMER_COUNT_Pos = 0x0 + // Bit mask of TIMER_COUNT field. + FRC_TIMER_COUNT_TIMER_COUNT_Msk = 0xff + + // TIMER_CTRL + // Position of TIMER_PRESCALER field. + FRC_TIMER_CTRL_TIMER_PRESCALER_Pos = 0x1 + // Bit mask of TIMER_PRESCALER field. + FRC_TIMER_CTRL_TIMER_PRESCALER_Msk = 0x1fe + + // TIMER_INT + // Position of CLR field. + FRC_TIMER_INT_CLR_Pos = 0x0 + // Bit mask of CLR field. + FRC_TIMER_INT_CLR_Msk = 0x1 + // Bit CLR. + FRC_TIMER_INT_CLR = 0x1 + + // TIMER_ALARM + // Position of TIMER_ALARM field. + FRC_TIMER_ALARM_TIMER_ALARM_Pos = 0x0 + // Bit mask of TIMER_ALARM field. + FRC_TIMER_ALARM_TIMER_ALARM_Msk = 0xff +) + +// Constants for GPIO: General Purpose Input/Output +const ( + // BT_SELECT + // Position of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Pos = 0x0 + // Bit mask of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Msk = 0xffffffff + + // OUT + // Position of DATA field. + GPIO_OUT_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_OUT_DATA_Msk = 0xffffffff + + // OUT_W1TS + // Position of OUT_DATA_W1TS field. + GPIO_OUT_W1TS_OUT_DATA_W1TS_Pos = 0x0 + // Bit mask of OUT_DATA_W1TS field. + GPIO_OUT_W1TS_OUT_DATA_W1TS_Msk = 0xffffffff + + // OUT_W1TC + // Position of OUT_DATA_W1TC field. + GPIO_OUT_W1TC_OUT_DATA_W1TC_Pos = 0x0 + // Bit mask of OUT_DATA_W1TC field. + GPIO_OUT_W1TC_OUT_DATA_W1TC_Msk = 0xffffffff + + // OUT1 + // Position of DATA field. + GPIO_OUT1_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_OUT1_DATA_Msk = 0xff + + // OUT1_W1TS + // Position of OUT1_DATA_W1TS field. + GPIO_OUT1_W1TS_OUT1_DATA_W1TS_Pos = 0x0 + // Bit mask of OUT1_DATA_W1TS field. + GPIO_OUT1_W1TS_OUT1_DATA_W1TS_Msk = 0xff + + // OUT1_W1TC + // Position of OUT1_DATA_W1TC field. + GPIO_OUT1_W1TC_OUT1_DATA_W1TC_Pos = 0x0 + // Bit mask of OUT1_DATA_W1TC field. + GPIO_OUT1_W1TC_OUT1_DATA_W1TC_Msk = 0xff + + // SDIO_SELECT + // Position of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Pos = 0x0 + // Bit mask of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Msk = 0xff + + // ENABLE + // Position of DATA field. + GPIO_ENABLE_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE_DATA_Msk = 0xffffffff + + // ENABLE_W1TS + // Position of ENABLE_DATA_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_DATA_W1TS_Pos = 0x0 + // Bit mask of ENABLE_DATA_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_DATA_W1TS_Msk = 0xffffffff + + // ENABLE_W1TC + // Position of ENABLE_DATA_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_DATA_W1TC_Pos = 0x0 + // Bit mask of ENABLE_DATA_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_DATA_W1TC_Msk = 0xffffffff + + // ENABLE1 + // Position of DATA field. + GPIO_ENABLE1_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE1_DATA_Msk = 0xff + + // ENABLE1_W1TS + // Position of ENABLE1_DATA_W1TS field. + GPIO_ENABLE1_W1TS_ENABLE1_DATA_W1TS_Pos = 0x0 + // Bit mask of ENABLE1_DATA_W1TS field. + GPIO_ENABLE1_W1TS_ENABLE1_DATA_W1TS_Msk = 0xff + + // ENABLE1_W1TC + // Position of ENABLE1_DATA_W1TC field. + GPIO_ENABLE1_W1TC_ENABLE1_DATA_W1TC_Pos = 0x0 + // Bit mask of ENABLE1_DATA_W1TC field. + GPIO_ENABLE1_W1TC_ENABLE1_DATA_W1TC_Msk = 0xff + + // STRAP + // Position of STRAPPING field. + GPIO_STRAP_STRAPPING_Pos = 0x0 + // Bit mask of STRAPPING field. + GPIO_STRAP_STRAPPING_Msk = 0xffff + + // IN + // Position of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Msk = 0xffffffff + + // IN1 + // Position of DATA_NEXT field. + GPIO_IN1_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN1_DATA_NEXT_Msk = 0xff + + // STATUS + // Position of INT field. + GPIO_STATUS_INT_Pos = 0x0 + // Bit mask of INT field. + GPIO_STATUS_INT_Msk = 0xffffffff + + // STATUS_W1TS + // Position of STATUS_INT_W1TS field. + GPIO_STATUS_W1TS_STATUS_INT_W1TS_Pos = 0x0 + // Bit mask of STATUS_INT_W1TS field. + GPIO_STATUS_W1TS_STATUS_INT_W1TS_Msk = 0xffffffff + + // STATUS_W1TC + // Position of STATUS_INT_W1TC field. + GPIO_STATUS_W1TC_STATUS_INT_W1TC_Pos = 0x0 + // Bit mask of STATUS_INT_W1TC field. + GPIO_STATUS_W1TC_STATUS_INT_W1TC_Msk = 0xffffffff + + // STATUS1 + // Position of INT field. + GPIO_STATUS1_INT_Pos = 0x0 + // Bit mask of INT field. + GPIO_STATUS1_INT_Msk = 0xff + + // STATUS1_W1TS + // Position of STATUS1_INT_W1TS field. + GPIO_STATUS1_W1TS_STATUS1_INT_W1TS_Pos = 0x0 + // Bit mask of STATUS1_INT_W1TS field. + GPIO_STATUS1_W1TS_STATUS1_INT_W1TS_Msk = 0xff + + // STATUS1_W1TC + // Position of STATUS1_INT_W1TC field. + GPIO_STATUS1_W1TC_STATUS1_INT_W1TC_Pos = 0x0 + // Bit mask of STATUS1_INT_W1TC field. + GPIO_STATUS1_W1TC_STATUS1_INT_W1TC_Msk = 0xff + + // ACPU_INT + // Position of APPCPU_INT field. + GPIO_ACPU_INT_APPCPU_INT_Pos = 0x0 + // Bit mask of APPCPU_INT field. + GPIO_ACPU_INT_APPCPU_INT_Msk = 0xffffffff + + // ACPU_NMI_INT + // Position of APPCPU_NMI_INT field. + GPIO_ACPU_NMI_INT_APPCPU_NMI_INT_Pos = 0x0 + // Bit mask of APPCPU_NMI_INT field. + GPIO_ACPU_NMI_INT_APPCPU_NMI_INT_Msk = 0xffffffff + + // PCPU_INT + // Position of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Pos = 0x0 + // Bit mask of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Msk = 0xffffffff + + // PCPU_NMI_INT + // Position of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Msk = 0xffffffff + + // CPUSDIO_INT + // Position of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Pos = 0x0 + // Bit mask of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Msk = 0xffffffff + + // ACPU_INT1 + // Position of APPCPU_INT_H field. + GPIO_ACPU_INT1_APPCPU_INT_H_Pos = 0x0 + // Bit mask of APPCPU_INT_H field. + GPIO_ACPU_INT1_APPCPU_INT_H_Msk = 0xff + + // ACPU_NMI_INT1 + // Position of APPCPU_NMI_INT_H field. + GPIO_ACPU_NMI_INT1_APPCPU_NMI_INT_H_Pos = 0x0 + // Bit mask of APPCPU_NMI_INT_H field. + GPIO_ACPU_NMI_INT1_APPCPU_NMI_INT_H_Msk = 0xff + + // PCPU_INT1 + // Position of PROCPU_INT_H field. + GPIO_PCPU_INT1_PROCPU_INT_H_Pos = 0x0 + // Bit mask of PROCPU_INT_H field. + GPIO_PCPU_INT1_PROCPU_INT_H_Msk = 0xff + + // PCPU_NMI_INT1 + // Position of PROCPU_NMI_INT_H field. + GPIO_PCPU_NMI_INT1_PROCPU_NMI_INT_H_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT_H field. + GPIO_PCPU_NMI_INT1_PROCPU_NMI_INT_H_Msk = 0xff + + // CPUSDIO_INT1 + // Position of SDIO_INT_H field. + GPIO_CPUSDIO_INT1_SDIO_INT_H_Pos = 0x0 + // Bit mask of SDIO_INT_H field. + GPIO_CPUSDIO_INT1_SDIO_INT_H_Msk = 0xff + // Position of PIN_PAD_DRIVER field. + GPIO_CPUSDIO_INT1_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PIN_PAD_DRIVER field. + GPIO_CPUSDIO_INT1_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PIN_PAD_DRIVER. + GPIO_CPUSDIO_INT1_PIN_PAD_DRIVER = 0x4 + // Position of PIN_INT_TYPE field. + GPIO_CPUSDIO_INT1_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of PIN_INT_TYPE field. + GPIO_CPUSDIO_INT1_PIN_INT_TYPE_Msk = 0x380 + // Position of PIN_WAKEUP_ENABLE field. + GPIO_CPUSDIO_INT1_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of PIN_WAKEUP_ENABLE field. + GPIO_CPUSDIO_INT1_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit PIN_WAKEUP_ENABLE. + GPIO_CPUSDIO_INT1_PIN_WAKEUP_ENABLE = 0x400 + // Position of PIN_CONFIG field. + GPIO_CPUSDIO_INT1_PIN_CONFIG_Pos = 0xb + // Bit mask of PIN_CONFIG field. + GPIO_CPUSDIO_INT1_PIN_CONFIG_Msk = 0x1800 + // Position of PIN_INT_ENA field. + GPIO_CPUSDIO_INT1_PIN_INT_ENA_Pos = 0xd + // Bit mask of PIN_INT_ENA field. + GPIO_CPUSDIO_INT1_PIN_INT_ENA_Msk = 0x3e000 + + // PIN0 + // Position of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + GPIO_PIN_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + GPIO_PIN_WAKEUP_ENABLE = 0x400 + // Position of CONFIG field. + GPIO_PIN_CONFIG_Pos = 0xb + // Bit mask of CONFIG field. + GPIO_PIN_CONFIG_Msk = 0x1800 + // Position of INT_ENA field. + GPIO_PIN_INT_ENA_Pos = 0xd + // Bit mask of INT_ENA field. + GPIO_PIN_INT_ENA_Msk = 0x3e000 + + // CALI_CONF + // Position of CALI_RTC_MAX field. + GPIO_CALI_CONF_CALI_RTC_MAX_Pos = 0x0 + // Bit mask of CALI_RTC_MAX field. + GPIO_CALI_CONF_CALI_RTC_MAX_Msk = 0x3ff + // Position of CALI_START field. + GPIO_CALI_CONF_CALI_START_Pos = 0x1f + // Bit mask of CALI_START field. + GPIO_CALI_CONF_CALI_START_Msk = 0x80000000 + // Bit CALI_START. + GPIO_CALI_CONF_CALI_START = 0x80000000 + + // CALI_DATA + // Position of CALI_VALUE_SYNC2 field. + GPIO_CALI_DATA_CALI_VALUE_SYNC2_Pos = 0x0 + // Bit mask of CALI_VALUE_SYNC2 field. + GPIO_CALI_DATA_CALI_VALUE_SYNC2_Msk = 0xfffff + // Position of CALI_RDY_REAL field. + GPIO_CALI_DATA_CALI_RDY_REAL_Pos = 0x1e + // Bit mask of CALI_RDY_REAL field. + GPIO_CALI_DATA_CALI_RDY_REAL_Msk = 0x40000000 + // Bit CALI_RDY_REAL. + GPIO_CALI_DATA_CALI_RDY_REAL = 0x40000000 + // Position of CALI_RDY_SYNC2 field. + GPIO_CALI_DATA_CALI_RDY_SYNC2_Pos = 0x1f + // Bit mask of CALI_RDY_SYNC2 field. + GPIO_CALI_DATA_CALI_RDY_SYNC2_Msk = 0x80000000 + // Bit CALI_RDY_SYNC2. + GPIO_CALI_DATA_CALI_RDY_SYNC2 = 0x80000000 + + // FUNC0_IN_SEL_CFG + // Position of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Pos = 0x0 + // Bit mask of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Msk = 0x3f + // Position of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Pos = 0x6 + // Bit mask of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Msk = 0x40 + // Bit IN_INV_SEL. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL = 0x40 + // Position of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Pos = 0x7 + // Bit mask of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Msk = 0x80 + // Bit SEL. + GPIO_FUNC_IN_SEL_CFG_SEL = 0x80 + + // FUNC0_OUT_SEL_CFG + // Position of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Pos = 0x0 + // Bit mask of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Msk = 0x1ff + // Position of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Pos = 0x9 + // Bit mask of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Msk = 0x200 + // Bit INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL = 0x200 + // Position of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Pos = 0xa + // Bit mask of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Msk = 0x400 + // Bit OEN_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL = 0x400 + // Position of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Pos = 0xb + // Bit mask of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Msk = 0x800 + // Bit OEN_INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL = 0x800 +) + +// Constants for GPIO_SD: Sigma-Delta Modulation +const ( + // SIGMADELTA0 + // Position of SD0_IN field. + GPIO_SIGMADELTA_SIGMADELTA_SD0_IN_Pos = 0x0 + // Bit mask of SD0_IN field. + GPIO_SIGMADELTA_SIGMADELTA_SD0_IN_Msk = 0xff + // Position of SD0_PRESCALE field. + GPIO_SIGMADELTA_SIGMADELTA_SD0_PRESCALE_Pos = 0x8 + // Bit mask of SD0_PRESCALE field. + GPIO_SIGMADELTA_SIGMADELTA_SD0_PRESCALE_Msk = 0xff00 + + // CG + // Position of SD_CLK_EN field. + GPIO_SIGMADELTA_CG_SD_CLK_EN_Pos = 0x1f + // Bit mask of SD_CLK_EN field. + GPIO_SIGMADELTA_CG_SD_CLK_EN_Msk = 0x80000000 + // Bit SD_CLK_EN. + GPIO_SIGMADELTA_CG_SD_CLK_EN = 0x80000000 + + // MISC + // Position of SPI_SWAP field. + GPIO_SIGMADELTA_MISC_SPI_SWAP_Pos = 0x1f + // Bit mask of SPI_SWAP field. + GPIO_SIGMADELTA_MISC_SPI_SWAP_Msk = 0x80000000 + // Bit SPI_SWAP. + GPIO_SIGMADELTA_MISC_SPI_SWAP = 0x80000000 + + // VERSION + // Position of SD_DATE field. + GPIO_SIGMADELTA_VERSION_SD_DATE_Pos = 0x0 + // Bit mask of SD_DATE field. + GPIO_SIGMADELTA_VERSION_SD_DATE_Msk = 0xfffffff +) + +// Constants for HINF: HINF Peripheral +const ( + // CFG_DATA0 + // Position of USER_ID_FN1 field. + HINF_CFG_DATA0_USER_ID_FN1_Pos = 0x0 + // Bit mask of USER_ID_FN1 field. + HINF_CFG_DATA0_USER_ID_FN1_Msk = 0xffff + // Position of DEVICE_ID_FN1 field. + HINF_CFG_DATA0_DEVICE_ID_FN1_Pos = 0x10 + // Bit mask of DEVICE_ID_FN1 field. + HINF_CFG_DATA0_DEVICE_ID_FN1_Msk = 0xffff0000 + + // CFG_DATA1 + // Position of SDIO_ENABLE field. + HINF_CFG_DATA1_SDIO_ENABLE_Pos = 0x0 + // Bit mask of SDIO_ENABLE field. + HINF_CFG_DATA1_SDIO_ENABLE_Msk = 0x1 + // Bit SDIO_ENABLE. + HINF_CFG_DATA1_SDIO_ENABLE = 0x1 + // Position of SDIO_IOREADY1 field. + HINF_CFG_DATA1_SDIO_IOREADY1_Pos = 0x1 + // Bit mask of SDIO_IOREADY1 field. + HINF_CFG_DATA1_SDIO_IOREADY1_Msk = 0x2 + // Bit SDIO_IOREADY1. + HINF_CFG_DATA1_SDIO_IOREADY1 = 0x2 + // Position of HIGHSPEED_ENABLE field. + HINF_CFG_DATA1_HIGHSPEED_ENABLE_Pos = 0x2 + // Bit mask of HIGHSPEED_ENABLE field. + HINF_CFG_DATA1_HIGHSPEED_ENABLE_Msk = 0x4 + // Bit HIGHSPEED_ENABLE. + HINF_CFG_DATA1_HIGHSPEED_ENABLE = 0x4 + // Position of HIGHSPEED_MODE field. + HINF_CFG_DATA1_HIGHSPEED_MODE_Pos = 0x3 + // Bit mask of HIGHSPEED_MODE field. + HINF_CFG_DATA1_HIGHSPEED_MODE_Msk = 0x8 + // Bit HIGHSPEED_MODE. + HINF_CFG_DATA1_HIGHSPEED_MODE = 0x8 + // Position of SDIO_CD_ENABLE field. + HINF_CFG_DATA1_SDIO_CD_ENABLE_Pos = 0x4 + // Bit mask of SDIO_CD_ENABLE field. + HINF_CFG_DATA1_SDIO_CD_ENABLE_Msk = 0x10 + // Bit SDIO_CD_ENABLE. + HINF_CFG_DATA1_SDIO_CD_ENABLE = 0x10 + // Position of SDIO_IOREADY2 field. + HINF_CFG_DATA1_SDIO_IOREADY2_Pos = 0x5 + // Bit mask of SDIO_IOREADY2 field. + HINF_CFG_DATA1_SDIO_IOREADY2_Msk = 0x20 + // Bit SDIO_IOREADY2. + HINF_CFG_DATA1_SDIO_IOREADY2 = 0x20 + // Position of SDIO_INT_MASK field. + HINF_CFG_DATA1_SDIO_INT_MASK_Pos = 0x6 + // Bit mask of SDIO_INT_MASK field. + HINF_CFG_DATA1_SDIO_INT_MASK_Msk = 0x40 + // Bit SDIO_INT_MASK. + HINF_CFG_DATA1_SDIO_INT_MASK = 0x40 + // Position of IOENABLE2 field. + HINF_CFG_DATA1_IOENABLE2_Pos = 0x7 + // Bit mask of IOENABLE2 field. + HINF_CFG_DATA1_IOENABLE2_Msk = 0x80 + // Bit IOENABLE2. + HINF_CFG_DATA1_IOENABLE2 = 0x80 + // Position of CD_DISABLE field. + HINF_CFG_DATA1_CD_DISABLE_Pos = 0x8 + // Bit mask of CD_DISABLE field. + HINF_CFG_DATA1_CD_DISABLE_Msk = 0x100 + // Bit CD_DISABLE. + HINF_CFG_DATA1_CD_DISABLE = 0x100 + // Position of FUNC1_EPS field. + HINF_CFG_DATA1_FUNC1_EPS_Pos = 0x9 + // Bit mask of FUNC1_EPS field. + HINF_CFG_DATA1_FUNC1_EPS_Msk = 0x200 + // Bit FUNC1_EPS. + HINF_CFG_DATA1_FUNC1_EPS = 0x200 + // Position of EMP field. + HINF_CFG_DATA1_EMP_Pos = 0xa + // Bit mask of EMP field. + HINF_CFG_DATA1_EMP_Msk = 0x400 + // Bit EMP. + HINF_CFG_DATA1_EMP = 0x400 + // Position of IOENABLE1 field. + HINF_CFG_DATA1_IOENABLE1_Pos = 0xb + // Bit mask of IOENABLE1 field. + HINF_CFG_DATA1_IOENABLE1_Msk = 0x800 + // Bit IOENABLE1. + HINF_CFG_DATA1_IOENABLE1 = 0x800 + // Position of SDIO20_CONF0 field. + HINF_CFG_DATA1_SDIO20_CONF0_Pos = 0xc + // Bit mask of SDIO20_CONF0 field. + HINF_CFG_DATA1_SDIO20_CONF0_Msk = 0xf000 + // Position of SDIO_VER field. + HINF_CFG_DATA1_SDIO_VER_Pos = 0x10 + // Bit mask of SDIO_VER field. + HINF_CFG_DATA1_SDIO_VER_Msk = 0xfff0000 + // Position of FUNC2_EPS field. + HINF_CFG_DATA1_FUNC2_EPS_Pos = 0x1c + // Bit mask of FUNC2_EPS field. + HINF_CFG_DATA1_FUNC2_EPS_Msk = 0x10000000 + // Bit FUNC2_EPS. + HINF_CFG_DATA1_FUNC2_EPS = 0x10000000 + // Position of SDIO20_CONF1 field. + HINF_CFG_DATA1_SDIO20_CONF1_Pos = 0x1d + // Bit mask of SDIO20_CONF1 field. + HINF_CFG_DATA1_SDIO20_CONF1_Msk = 0xe0000000 + + // CFG_DATA7 + // Position of PIN_STATE field. + HINF_CFG_DATA7_PIN_STATE_Pos = 0x0 + // Bit mask of PIN_STATE field. + HINF_CFG_DATA7_PIN_STATE_Msk = 0xff + // Position of CHIP_STATE field. + HINF_CFG_DATA7_CHIP_STATE_Pos = 0x8 + // Bit mask of CHIP_STATE field. + HINF_CFG_DATA7_CHIP_STATE_Msk = 0xff00 + // Position of SDIO_RST field. + HINF_CFG_DATA7_SDIO_RST_Pos = 0x10 + // Bit mask of SDIO_RST field. + HINF_CFG_DATA7_SDIO_RST_Msk = 0x10000 + // Bit SDIO_RST. + HINF_CFG_DATA7_SDIO_RST = 0x10000 + // Position of SDIO_IOREADY0 field. + HINF_CFG_DATA7_SDIO_IOREADY0_Pos = 0x11 + // Bit mask of SDIO_IOREADY0 field. + HINF_CFG_DATA7_SDIO_IOREADY0_Msk = 0x20000 + // Bit SDIO_IOREADY0. + HINF_CFG_DATA7_SDIO_IOREADY0 = 0x20000 + + // CIS_CONF0 + // Position of CIS_CONF_W0 field. + HINF_CIS_CONF0_CIS_CONF_W0_Pos = 0x0 + // Bit mask of CIS_CONF_W0 field. + HINF_CIS_CONF0_CIS_CONF_W0_Msk = 0xffffffff + + // CIS_CONF1 + // Position of CIS_CONF_W1 field. + HINF_CIS_CONF1_CIS_CONF_W1_Pos = 0x0 + // Bit mask of CIS_CONF_W1 field. + HINF_CIS_CONF1_CIS_CONF_W1_Msk = 0xffffffff + + // CIS_CONF2 + // Position of CIS_CONF_W2 field. + HINF_CIS_CONF2_CIS_CONF_W2_Pos = 0x0 + // Bit mask of CIS_CONF_W2 field. + HINF_CIS_CONF2_CIS_CONF_W2_Msk = 0xffffffff + + // CIS_CONF3 + // Position of CIS_CONF_W3 field. + HINF_CIS_CONF3_CIS_CONF_W3_Pos = 0x0 + // Bit mask of CIS_CONF_W3 field. + HINF_CIS_CONF3_CIS_CONF_W3_Msk = 0xffffffff + + // CIS_CONF4 + // Position of CIS_CONF_W4 field. + HINF_CIS_CONF4_CIS_CONF_W4_Pos = 0x0 + // Bit mask of CIS_CONF_W4 field. + HINF_CIS_CONF4_CIS_CONF_W4_Msk = 0xffffffff + + // CIS_CONF5 + // Position of CIS_CONF_W5 field. + HINF_CIS_CONF5_CIS_CONF_W5_Pos = 0x0 + // Bit mask of CIS_CONF_W5 field. + HINF_CIS_CONF5_CIS_CONF_W5_Msk = 0xffffffff + + // CIS_CONF6 + // Position of CIS_CONF_W6 field. + HINF_CIS_CONF6_CIS_CONF_W6_Pos = 0x0 + // Bit mask of CIS_CONF_W6 field. + HINF_CIS_CONF6_CIS_CONF_W6_Msk = 0xffffffff + + // CIS_CONF7 + // Position of CIS_CONF_W7 field. + HINF_CIS_CONF7_CIS_CONF_W7_Pos = 0x0 + // Bit mask of CIS_CONF_W7 field. + HINF_CIS_CONF7_CIS_CONF_W7_Msk = 0xffffffff + + // CFG_DATA16 + // Position of USER_ID_FN2 field. + HINF_CFG_DATA16_USER_ID_FN2_Pos = 0x0 + // Bit mask of USER_ID_FN2 field. + HINF_CFG_DATA16_USER_ID_FN2_Msk = 0xffff + // Position of DEVICE_ID_FN2 field. + HINF_CFG_DATA16_DEVICE_ID_FN2_Pos = 0x10 + // Bit mask of DEVICE_ID_FN2 field. + HINF_CFG_DATA16_DEVICE_ID_FN2_Msk = 0xffff0000 + + // DATE + // Position of SDIO_DATE field. + HINF_DATE_SDIO_DATE_Pos = 0x0 + // Bit mask of SDIO_DATE field. + HINF_DATE_SDIO_DATE_Msk = 0xffffffff +) + +// Constants for I2C0: I2C (Inter-Integrated Circuit) Controller 0 +const ( + // SCL_LOW_PERIOD + // Position of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x3fff + + // CTR + // Position of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + I2C_CTR_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + I2C_CTR_SCL_FORCE_OUT = 0x2 + // Position of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2 + // Bit mask of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4 + // Bit SAMPLE_SCL_LEVEL. + I2C_CTR_SAMPLE_SCL_LEVEL = 0x4 + // Position of MS_MODE field. + I2C_CTR_MS_MODE_Pos = 0x4 + // Bit mask of MS_MODE field. + I2C_CTR_MS_MODE_Msk = 0x10 + // Bit MS_MODE. + I2C_CTR_MS_MODE = 0x10 + // Position of TRANS_START field. + I2C_CTR_TRANS_START_Pos = 0x5 + // Bit mask of TRANS_START field. + I2C_CTR_TRANS_START_Msk = 0x20 + // Bit TRANS_START. + I2C_CTR_TRANS_START = 0x20 + // Position of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Msk = 0x40 + // Bit TX_LSB_FIRST. + I2C_CTR_TX_LSB_FIRST = 0x40 + // Position of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Msk = 0x80 + // Bit RX_LSB_FIRST. + I2C_CTR_RX_LSB_FIRST = 0x80 + // Position of CLK_EN field. + I2C_CTR_CLK_EN_Pos = 0x8 + // Bit mask of CLK_EN field. + I2C_CTR_CLK_EN_Msk = 0x100 + // Bit CLK_EN. + I2C_CTR_CLK_EN = 0x100 + + // SR + // Position of ACK_REC field. + I2C_SR_ACK_REC_Pos = 0x0 + // Bit mask of ACK_REC field. + I2C_SR_ACK_REC_Msk = 0x1 + // Bit ACK_REC. + I2C_SR_ACK_REC = 0x1 + // Position of SLAVE_RW field. + I2C_SR_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + I2C_SR_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + I2C_SR_SLAVE_RW = 0x2 + // Position of TIME_OUT field. + I2C_SR_TIME_OUT_Pos = 0x2 + // Bit mask of TIME_OUT field. + I2C_SR_TIME_OUT_Msk = 0x4 + // Bit TIME_OUT. + I2C_SR_TIME_OUT = 0x4 + // Position of ARB_LOST field. + I2C_SR_ARB_LOST_Pos = 0x3 + // Bit mask of ARB_LOST field. + I2C_SR_ARB_LOST_Msk = 0x8 + // Bit ARB_LOST. + I2C_SR_ARB_LOST = 0x8 + // Position of BUS_BUSY field. + I2C_SR_BUS_BUSY_Pos = 0x4 + // Bit mask of BUS_BUSY field. + I2C_SR_BUS_BUSY_Msk = 0x10 + // Bit BUS_BUSY. + I2C_SR_BUS_BUSY = 0x10 + // Position of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Pos = 0x5 + // Bit mask of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Msk = 0x20 + // Bit SLAVE_ADDRESSED. + I2C_SR_SLAVE_ADDRESSED = 0x20 + // Position of BYTE_TRANS field. + I2C_SR_BYTE_TRANS_Pos = 0x6 + // Bit mask of BYTE_TRANS field. + I2C_SR_BYTE_TRANS_Msk = 0x40 + // Bit BYTE_TRANS. + I2C_SR_BYTE_TRANS = 0x40 + // Position of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Pos = 0x8 + // Bit mask of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Msk = 0x3f00 + // Position of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Pos = 0x12 + // Bit mask of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Msk = 0xfc0000 + // Position of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Msk = 0x70000000 + + // TO + // Position of TIME_OUT field. + I2C_TO_TIME_OUT_Pos = 0x0 + // Bit mask of TIME_OUT field. + I2C_TO_TIME_OUT_Msk = 0xfffff + + // SLAVE_ADDR + // Position of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // RXFIFO_ST + // Position of RXFIFO_START_ADDR field. + I2C_RXFIFO_ST_RXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of RXFIFO_START_ADDR field. + I2C_RXFIFO_ST_RXFIFO_START_ADDR_Msk = 0x1f + // Position of RXFIFO_END_ADDR field. + I2C_RXFIFO_ST_RXFIFO_END_ADDR_Pos = 0x5 + // Bit mask of RXFIFO_END_ADDR field. + I2C_RXFIFO_ST_RXFIFO_END_ADDR_Msk = 0x3e0 + // Position of TXFIFO_START_ADDR field. + I2C_RXFIFO_ST_TXFIFO_START_ADDR_Pos = 0xa + // Bit mask of TXFIFO_START_ADDR field. + I2C_RXFIFO_ST_TXFIFO_START_ADDR_Msk = 0x7c00 + // Position of TXFIFO_END_ADDR field. + I2C_RXFIFO_ST_TXFIFO_END_ADDR_Pos = 0xf + // Bit mask of TXFIFO_END_ADDR field. + I2C_RXFIFO_ST_TXFIFO_END_ADDR_Msk = 0xf8000 + + // FIFO_CONF + // Position of RXFIFO_FULL_THRHD field. + I2C_FIFO_CONF_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + I2C_FIFO_CONF_RXFIFO_FULL_THRHD_Msk = 0x1f + // Position of TXFIFO_EMPTY_THRHD field. + I2C_FIFO_CONF_TXFIFO_EMPTY_THRHD_Pos = 0x5 + // Bit mask of TXFIFO_EMPTY_THRHD field. + I2C_FIFO_CONF_TXFIFO_EMPTY_THRHD_Msk = 0x3e0 + // Position of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa + // Bit mask of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400 + // Bit NONFIFO_EN. + I2C_FIFO_CONF_NONFIFO_EN = 0x400 + // Position of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Pos = 0xb + // Bit mask of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Msk = 0x800 + // Bit FIFO_ADDR_CFG_EN. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN = 0x800 + // Position of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc + // Bit mask of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000 + // Bit RX_FIFO_RST. + I2C_FIFO_CONF_RX_FIFO_RST = 0x1000 + // Position of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd + // Bit mask of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000 + // Bit TX_FIFO_RST. + I2C_FIFO_CONF_TX_FIFO_RST = 0x2000 + // Position of NONFIFO_RX_THRES field. + I2C_FIFO_CONF_NONFIFO_RX_THRES_Pos = 0xe + // Bit mask of NONFIFO_RX_THRES field. + I2C_FIFO_CONF_NONFIFO_RX_THRES_Msk = 0xfc000 + // Position of NONFIFO_TX_THRES field. + I2C_FIFO_CONF_NONFIFO_TX_THRES_Pos = 0x14 + // Bit mask of NONFIFO_TX_THRES field. + I2C_FIFO_CONF_NONFIFO_TX_THRES_Msk = 0x3f00000 + + // DATA + // Position of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Pos = 0x0 + // Bit mask of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Msk = 0xff + + // INT_RAW + // Position of RXFIFO_FULL_INT_RAW field. + I2C_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + I2C_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + I2C_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + I2C_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + I2C_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + I2C_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4 + // Bit RXFIFO_OVF_INT_RAW. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4 + // Position of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3 + // Bit mask of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8 + // Bit END_DETECT_INT_RAW. + I2C_INT_RAW_END_DETECT_INT_RAW = 0x8 + // Position of SLAVE_TRAN_COMP_INT_RAW field. + I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Pos = 0x4 + // Bit mask of SLAVE_TRAN_COMP_INT_RAW field. + I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Msk = 0x10 + // Bit SLAVE_TRAN_COMP_INT_RAW. + I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW = 0x10 + // Position of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_RAW. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20 + // Position of MASTER_TRAN_COMP_INT_RAW field. + I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Pos = 0x6 + // Bit mask of MASTER_TRAN_COMP_INT_RAW field. + I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Msk = 0x40 + // Bit MASTER_TRAN_COMP_INT_RAW. + I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW = 0x40 + // Position of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_RAW. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80 + // Position of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8 + // Bit mask of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100 + // Bit TIME_OUT_INT_RAW. + I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100 + // Position of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9 + // Bit mask of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200 + // Bit TRANS_START_INT_RAW. + I2C_INT_RAW_TRANS_START_INT_RAW = 0x200 + // Position of ACK_ERR_INT_RAW field. + I2C_INT_RAW_ACK_ERR_INT_RAW_Pos = 0xa + // Bit mask of ACK_ERR_INT_RAW field. + I2C_INT_RAW_ACK_ERR_INT_RAW_Msk = 0x400 + // Bit ACK_ERR_INT_RAW. + I2C_INT_RAW_ACK_ERR_INT_RAW = 0x400 + // Position of RX_REC_FULL_INT_RAW field. + I2C_INT_RAW_RX_REC_FULL_INT_RAW_Pos = 0xb + // Bit mask of RX_REC_FULL_INT_RAW field. + I2C_INT_RAW_RX_REC_FULL_INT_RAW_Msk = 0x800 + // Bit RX_REC_FULL_INT_RAW. + I2C_INT_RAW_RX_REC_FULL_INT_RAW = 0x800 + // Position of TX_SEND_EMPTY_INT_RAW field. + I2C_INT_RAW_TX_SEND_EMPTY_INT_RAW_Pos = 0xc + // Bit mask of TX_SEND_EMPTY_INT_RAW field. + I2C_INT_RAW_TX_SEND_EMPTY_INT_RAW_Msk = 0x1000 + // Bit TX_SEND_EMPTY_INT_RAW. + I2C_INT_RAW_TX_SEND_EMPTY_INT_RAW = 0x1000 + + // INT_CLR + // Position of RXFIFO_FULL_INT_CLR field. + I2C_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + I2C_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + I2C_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + I2C_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + I2C_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + I2C_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4 + // Bit RXFIFO_OVF_INT_CLR. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4 + // Position of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3 + // Bit mask of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8 + // Bit END_DETECT_INT_CLR. + I2C_INT_CLR_END_DETECT_INT_CLR = 0x8 + // Position of SLAVE_TRAN_COMP_INT_CLR field. + I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Pos = 0x4 + // Bit mask of SLAVE_TRAN_COMP_INT_CLR field. + I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Msk = 0x10 + // Bit SLAVE_TRAN_COMP_INT_CLR. + I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR = 0x10 + // Position of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_CLR. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of MASTER_TRAN_COMP_INT_CLR field. + I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Pos = 0x6 + // Bit mask of MASTER_TRAN_COMP_INT_CLR field. + I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Msk = 0x40 + // Bit MASTER_TRAN_COMP_INT_CLR. + I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR = 0x40 + // Position of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_CLR. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit TIME_OUT_INT_CLR. + I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100 + // Position of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9 + // Bit mask of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200 + // Bit TRANS_START_INT_CLR. + I2C_INT_CLR_TRANS_START_INT_CLR = 0x200 + // Position of ACK_ERR_INT_CLR field. + I2C_INT_CLR_ACK_ERR_INT_CLR_Pos = 0xa + // Bit mask of ACK_ERR_INT_CLR field. + I2C_INT_CLR_ACK_ERR_INT_CLR_Msk = 0x400 + // Bit ACK_ERR_INT_CLR. + I2C_INT_CLR_ACK_ERR_INT_CLR = 0x400 + // Position of RX_REC_FULL_INT_CLR field. + I2C_INT_CLR_RX_REC_FULL_INT_CLR_Pos = 0xb + // Bit mask of RX_REC_FULL_INT_CLR field. + I2C_INT_CLR_RX_REC_FULL_INT_CLR_Msk = 0x800 + // Bit RX_REC_FULL_INT_CLR. + I2C_INT_CLR_RX_REC_FULL_INT_CLR = 0x800 + // Position of TX_SEND_EMPTY_INT_CLR field. + I2C_INT_CLR_TX_SEND_EMPTY_INT_CLR_Pos = 0xc + // Bit mask of TX_SEND_EMPTY_INT_CLR field. + I2C_INT_CLR_TX_SEND_EMPTY_INT_CLR_Msk = 0x1000 + // Bit TX_SEND_EMPTY_INT_CLR. + I2C_INT_CLR_TX_SEND_EMPTY_INT_CLR = 0x1000 + + // INT_ENA + // Position of RXFIFO_FULL_INT_ENA field. + I2C_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + I2C_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + I2C_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + I2C_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + I2C_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + I2C_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ENA. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4 + // Position of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3 + // Bit mask of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8 + // Bit END_DETECT_INT_ENA. + I2C_INT_ENA_END_DETECT_INT_ENA = 0x8 + // Position of SLAVE_TRAN_COMP_INT_ENA field. + I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Pos = 0x4 + // Bit mask of SLAVE_TRAN_COMP_INT_ENA field. + I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Msk = 0x10 + // Bit SLAVE_TRAN_COMP_INT_ENA. + I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA = 0x10 + // Position of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ENA. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20 + // Position of MASTER_TRAN_COMP_INT_ENA field. + I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Pos = 0x6 + // Bit mask of MASTER_TRAN_COMP_INT_ENA field. + I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Msk = 0x40 + // Bit MASTER_TRAN_COMP_INT_ENA. + I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA = 0x40 + // Position of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ENA. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80 + // Position of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100 + // Bit TIME_OUT_INT_ENA. + I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100 + // Position of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9 + // Bit mask of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200 + // Bit TRANS_START_INT_ENA. + I2C_INT_ENA_TRANS_START_INT_ENA = 0x200 + // Position of ACK_ERR_INT_ENA field. + I2C_INT_ENA_ACK_ERR_INT_ENA_Pos = 0xa + // Bit mask of ACK_ERR_INT_ENA field. + I2C_INT_ENA_ACK_ERR_INT_ENA_Msk = 0x400 + // Bit ACK_ERR_INT_ENA. + I2C_INT_ENA_ACK_ERR_INT_ENA = 0x400 + // Position of RX_REC_FULL_INT_ENA field. + I2C_INT_ENA_RX_REC_FULL_INT_ENA_Pos = 0xb + // Bit mask of RX_REC_FULL_INT_ENA field. + I2C_INT_ENA_RX_REC_FULL_INT_ENA_Msk = 0x800 + // Bit RX_REC_FULL_INT_ENA. + I2C_INT_ENA_RX_REC_FULL_INT_ENA = 0x800 + // Position of TX_SEND_EMPTY_INT_ENA field. + I2C_INT_ENA_TX_SEND_EMPTY_INT_ENA_Pos = 0xc + // Bit mask of TX_SEND_EMPTY_INT_ENA field. + I2C_INT_ENA_TX_SEND_EMPTY_INT_ENA_Msk = 0x1000 + // Bit TX_SEND_EMPTY_INT_ENA. + I2C_INT_ENA_TX_SEND_EMPTY_INT_ENA = 0x1000 + + // INT_STATUS + // Position of RXFIFO_FULL_INT_ST field. + I2C_INT_STATUS_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + I2C_INT_STATUS_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + I2C_INT_STATUS_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + I2C_INT_STATUS_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + I2C_INT_STATUS_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + I2C_INT_STATUS_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ST. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4 + // Position of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3 + // Bit mask of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8 + // Bit END_DETECT_INT_ST. + I2C_INT_STATUS_END_DETECT_INT_ST = 0x8 + // Position of SLAVE_TRAN_COMP_INT_ST field. + I2C_INT_STATUS_SLAVE_TRAN_COMP_INT_ST_Pos = 0x4 + // Bit mask of SLAVE_TRAN_COMP_INT_ST field. + I2C_INT_STATUS_SLAVE_TRAN_COMP_INT_ST_Msk = 0x10 + // Bit SLAVE_TRAN_COMP_INT_ST. + I2C_INT_STATUS_SLAVE_TRAN_COMP_INT_ST = 0x10 + // Position of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ST. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20 + // Position of MASTER_TRAN_COMP_INT_ST field. + I2C_INT_STATUS_MASTER_TRAN_COMP_INT_ST_Pos = 0x6 + // Bit mask of MASTER_TRAN_COMP_INT_ST field. + I2C_INT_STATUS_MASTER_TRAN_COMP_INT_ST_Msk = 0x40 + // Bit MASTER_TRAN_COMP_INT_ST. + I2C_INT_STATUS_MASTER_TRAN_COMP_INT_ST = 0x40 + // Position of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ST. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80 + // Position of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100 + // Bit TIME_OUT_INT_ST. + I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100 + // Position of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9 + // Bit mask of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200 + // Bit TRANS_START_INT_ST. + I2C_INT_STATUS_TRANS_START_INT_ST = 0x200 + // Position of ACK_ERR_INT_ST field. + I2C_INT_STATUS_ACK_ERR_INT_ST_Pos = 0xa + // Bit mask of ACK_ERR_INT_ST field. + I2C_INT_STATUS_ACK_ERR_INT_ST_Msk = 0x400 + // Bit ACK_ERR_INT_ST. + I2C_INT_STATUS_ACK_ERR_INT_ST = 0x400 + // Position of RX_REC_FULL_INT_ST field. + I2C_INT_STATUS_RX_REC_FULL_INT_ST_Pos = 0xb + // Bit mask of RX_REC_FULL_INT_ST field. + I2C_INT_STATUS_RX_REC_FULL_INT_ST_Msk = 0x800 + // Bit RX_REC_FULL_INT_ST. + I2C_INT_STATUS_RX_REC_FULL_INT_ST = 0x800 + // Position of TX_SEND_EMPTY_INT_ST field. + I2C_INT_STATUS_TX_SEND_EMPTY_INT_ST_Pos = 0xc + // Bit mask of TX_SEND_EMPTY_INT_ST field. + I2C_INT_STATUS_TX_SEND_EMPTY_INT_ST_Msk = 0x1000 + // Bit TX_SEND_EMPTY_INT_ST. + I2C_INT_STATUS_TX_SEND_EMPTY_INT_ST = 0x1000 + + // SDA_HOLD + // Position of TIME field. + I2C_SDA_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_HOLD_TIME_Msk = 0x3ff + + // SDA_SAMPLE + // Position of TIME field. + I2C_SDA_SAMPLE_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_SAMPLE_TIME_Msk = 0x3ff + + // SCL_HIGH_PERIOD + // Position of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x3fff + + // SCL_START_HOLD + // Position of TIME field. + I2C_SCL_START_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_START_HOLD_TIME_Msk = 0x3ff + + // SCL_RSTART_SETUP + // Position of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Msk = 0x3ff + + // SCL_STOP_HOLD + // Position of TIME field. + I2C_SCL_STOP_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_HOLD_TIME_Msk = 0x3fff + + // SCL_STOP_SETUP + // Position of TIME field. + I2C_SCL_STOP_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_SETUP_TIME_Msk = 0x3ff + + // SCL_FILTER_CFG + // Position of SCL_FILTER_THRES field. + I2C_SCL_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0 + // Bit mask of SCL_FILTER_THRES field. + I2C_SCL_FILTER_CFG_SCL_FILTER_THRES_Msk = 0x7 + // Position of SCL_FILTER_EN field. + I2C_SCL_FILTER_CFG_SCL_FILTER_EN_Pos = 0x3 + // Bit mask of SCL_FILTER_EN field. + I2C_SCL_FILTER_CFG_SCL_FILTER_EN_Msk = 0x8 + // Bit SCL_FILTER_EN. + I2C_SCL_FILTER_CFG_SCL_FILTER_EN = 0x8 + + // SDA_FILTER_CFG + // Position of SDA_FILTER_THRES field. + I2C_SDA_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x0 + // Bit mask of SDA_FILTER_THRES field. + I2C_SDA_FILTER_CFG_SDA_FILTER_THRES_Msk = 0x7 + // Position of SDA_FILTER_EN field. + I2C_SDA_FILTER_CFG_SDA_FILTER_EN_Pos = 0x3 + // Bit mask of SDA_FILTER_EN field. + I2C_SDA_FILTER_CFG_SDA_FILTER_EN_Msk = 0x8 + // Bit SDA_FILTER_EN. + I2C_SDA_FILTER_CFG_SDA_FILTER_EN = 0x8 + + // COMD0 + // Position of COMMAND field. + I2C_COMD_COMMAND_Pos = 0x0 + // Bit mask of COMMAND field. + I2C_COMD_COMMAND_Msk = 0x3fff + // Position of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Pos = 0x1f + // Bit mask of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Msk = 0x80000000 + // Bit COMMAND_DONE. + I2C_COMD_COMMAND_DONE = 0x80000000 + + // DATE + // Position of DATE field. + I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2C_DATE_DATE_Msk = 0xffffffff +) + +// Constants for I2S0: I2S (Inter-IC Sound) Controller 0 +const ( + // CONF + // Position of TX_RESET field. + I2S_CONF_TX_RESET_Pos = 0x0 + // Bit mask of TX_RESET field. + I2S_CONF_TX_RESET_Msk = 0x1 + // Bit TX_RESET. + I2S_CONF_TX_RESET = 0x1 + // Position of RX_RESET field. + I2S_CONF_RX_RESET_Pos = 0x1 + // Bit mask of RX_RESET field. + I2S_CONF_RX_RESET_Msk = 0x2 + // Bit RX_RESET. + I2S_CONF_RX_RESET = 0x2 + // Position of TX_FIFO_RESET field. + I2S_CONF_TX_FIFO_RESET_Pos = 0x2 + // Bit mask of TX_FIFO_RESET field. + I2S_CONF_TX_FIFO_RESET_Msk = 0x4 + // Bit TX_FIFO_RESET. + I2S_CONF_TX_FIFO_RESET = 0x4 + // Position of RX_FIFO_RESET field. + I2S_CONF_RX_FIFO_RESET_Pos = 0x3 + // Bit mask of RX_FIFO_RESET field. + I2S_CONF_RX_FIFO_RESET_Msk = 0x8 + // Bit RX_FIFO_RESET. + I2S_CONF_RX_FIFO_RESET = 0x8 + // Position of TX_START field. + I2S_CONF_TX_START_Pos = 0x4 + // Bit mask of TX_START field. + I2S_CONF_TX_START_Msk = 0x10 + // Bit TX_START. + I2S_CONF_TX_START = 0x10 + // Position of RX_START field. + I2S_CONF_RX_START_Pos = 0x5 + // Bit mask of RX_START field. + I2S_CONF_RX_START_Msk = 0x20 + // Bit RX_START. + I2S_CONF_RX_START = 0x20 + // Position of TX_SLAVE_MOD field. + I2S_CONF_TX_SLAVE_MOD_Pos = 0x6 + // Bit mask of TX_SLAVE_MOD field. + I2S_CONF_TX_SLAVE_MOD_Msk = 0x40 + // Bit TX_SLAVE_MOD. + I2S_CONF_TX_SLAVE_MOD = 0x40 + // Position of RX_SLAVE_MOD field. + I2S_CONF_RX_SLAVE_MOD_Pos = 0x7 + // Bit mask of RX_SLAVE_MOD field. + I2S_CONF_RX_SLAVE_MOD_Msk = 0x80 + // Bit RX_SLAVE_MOD. + I2S_CONF_RX_SLAVE_MOD = 0x80 + // Position of TX_RIGHT_FIRST field. + I2S_CONF_TX_RIGHT_FIRST_Pos = 0x8 + // Bit mask of TX_RIGHT_FIRST field. + I2S_CONF_TX_RIGHT_FIRST_Msk = 0x100 + // Bit TX_RIGHT_FIRST. + I2S_CONF_TX_RIGHT_FIRST = 0x100 + // Position of RX_RIGHT_FIRST field. + I2S_CONF_RX_RIGHT_FIRST_Pos = 0x9 + // Bit mask of RX_RIGHT_FIRST field. + I2S_CONF_RX_RIGHT_FIRST_Msk = 0x200 + // Bit RX_RIGHT_FIRST. + I2S_CONF_RX_RIGHT_FIRST = 0x200 + // Position of TX_MSB_SHIFT field. + I2S_CONF_TX_MSB_SHIFT_Pos = 0xa + // Bit mask of TX_MSB_SHIFT field. + I2S_CONF_TX_MSB_SHIFT_Msk = 0x400 + // Bit TX_MSB_SHIFT. + I2S_CONF_TX_MSB_SHIFT = 0x400 + // Position of RX_MSB_SHIFT field. + I2S_CONF_RX_MSB_SHIFT_Pos = 0xb + // Bit mask of RX_MSB_SHIFT field. + I2S_CONF_RX_MSB_SHIFT_Msk = 0x800 + // Bit RX_MSB_SHIFT. + I2S_CONF_RX_MSB_SHIFT = 0x800 + // Position of TX_SHORT_SYNC field. + I2S_CONF_TX_SHORT_SYNC_Pos = 0xc + // Bit mask of TX_SHORT_SYNC field. + I2S_CONF_TX_SHORT_SYNC_Msk = 0x1000 + // Bit TX_SHORT_SYNC. + I2S_CONF_TX_SHORT_SYNC = 0x1000 + // Position of RX_SHORT_SYNC field. + I2S_CONF_RX_SHORT_SYNC_Pos = 0xd + // Bit mask of RX_SHORT_SYNC field. + I2S_CONF_RX_SHORT_SYNC_Msk = 0x2000 + // Bit RX_SHORT_SYNC. + I2S_CONF_RX_SHORT_SYNC = 0x2000 + // Position of TX_MONO field. + I2S_CONF_TX_MONO_Pos = 0xe + // Bit mask of TX_MONO field. + I2S_CONF_TX_MONO_Msk = 0x4000 + // Bit TX_MONO. + I2S_CONF_TX_MONO = 0x4000 + // Position of RX_MONO field. + I2S_CONF_RX_MONO_Pos = 0xf + // Bit mask of RX_MONO field. + I2S_CONF_RX_MONO_Msk = 0x8000 + // Bit RX_MONO. + I2S_CONF_RX_MONO = 0x8000 + // Position of TX_MSB_RIGHT field. + I2S_CONF_TX_MSB_RIGHT_Pos = 0x10 + // Bit mask of TX_MSB_RIGHT field. + I2S_CONF_TX_MSB_RIGHT_Msk = 0x10000 + // Bit TX_MSB_RIGHT. + I2S_CONF_TX_MSB_RIGHT = 0x10000 + // Position of RX_MSB_RIGHT field. + I2S_CONF_RX_MSB_RIGHT_Pos = 0x11 + // Bit mask of RX_MSB_RIGHT field. + I2S_CONF_RX_MSB_RIGHT_Msk = 0x20000 + // Bit RX_MSB_RIGHT. + I2S_CONF_RX_MSB_RIGHT = 0x20000 + // Position of SIG_LOOPBACK field. + I2S_CONF_SIG_LOOPBACK_Pos = 0x12 + // Bit mask of SIG_LOOPBACK field. + I2S_CONF_SIG_LOOPBACK_Msk = 0x40000 + // Bit SIG_LOOPBACK. + I2S_CONF_SIG_LOOPBACK = 0x40000 + + // INT_RAW + // Position of RX_TAKE_DATA_INT_RAW field. + I2S_INT_RAW_RX_TAKE_DATA_INT_RAW_Pos = 0x0 + // Bit mask of RX_TAKE_DATA_INT_RAW field. + I2S_INT_RAW_RX_TAKE_DATA_INT_RAW_Msk = 0x1 + // Bit RX_TAKE_DATA_INT_RAW. + I2S_INT_RAW_RX_TAKE_DATA_INT_RAW = 0x1 + // Position of TX_PUT_DATA_INT_RAW field. + I2S_INT_RAW_TX_PUT_DATA_INT_RAW_Pos = 0x1 + // Bit mask of TX_PUT_DATA_INT_RAW field. + I2S_INT_RAW_TX_PUT_DATA_INT_RAW_Msk = 0x2 + // Bit TX_PUT_DATA_INT_RAW. + I2S_INT_RAW_TX_PUT_DATA_INT_RAW = 0x2 + // Position of RX_WFULL_INT_RAW field. + I2S_INT_RAW_RX_WFULL_INT_RAW_Pos = 0x2 + // Bit mask of RX_WFULL_INT_RAW field. + I2S_INT_RAW_RX_WFULL_INT_RAW_Msk = 0x4 + // Bit RX_WFULL_INT_RAW. + I2S_INT_RAW_RX_WFULL_INT_RAW = 0x4 + // Position of RX_REMPTY_INT_RAW field. + I2S_INT_RAW_RX_REMPTY_INT_RAW_Pos = 0x3 + // Bit mask of RX_REMPTY_INT_RAW field. + I2S_INT_RAW_RX_REMPTY_INT_RAW_Msk = 0x8 + // Bit RX_REMPTY_INT_RAW. + I2S_INT_RAW_RX_REMPTY_INT_RAW = 0x8 + // Position of TX_WFULL_INT_RAW field. + I2S_INT_RAW_TX_WFULL_INT_RAW_Pos = 0x4 + // Bit mask of TX_WFULL_INT_RAW field. + I2S_INT_RAW_TX_WFULL_INT_RAW_Msk = 0x10 + // Bit TX_WFULL_INT_RAW. + I2S_INT_RAW_TX_WFULL_INT_RAW = 0x10 + // Position of TX_REMPTY_INT_RAW field. + I2S_INT_RAW_TX_REMPTY_INT_RAW_Pos = 0x5 + // Bit mask of TX_REMPTY_INT_RAW field. + I2S_INT_RAW_TX_REMPTY_INT_RAW_Msk = 0x20 + // Bit TX_REMPTY_INT_RAW. + I2S_INT_RAW_TX_REMPTY_INT_RAW = 0x20 + // Position of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x6 + // Bit mask of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x40 + // Bit RX_HUNG_INT_RAW. + I2S_INT_RAW_RX_HUNG_INT_RAW = 0x40 + // Position of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x7 + // Bit mask of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x80 + // Bit TX_HUNG_INT_RAW. + I2S_INT_RAW_TX_HUNG_INT_RAW = 0x80 + // Position of IN_DONE_INT_RAW field. + I2S_INT_RAW_IN_DONE_INT_RAW_Pos = 0x8 + // Bit mask of IN_DONE_INT_RAW field. + I2S_INT_RAW_IN_DONE_INT_RAW_Msk = 0x100 + // Bit IN_DONE_INT_RAW. + I2S_INT_RAW_IN_DONE_INT_RAW = 0x100 + // Position of IN_SUC_EOF_INT_RAW field. + I2S_INT_RAW_IN_SUC_EOF_INT_RAW_Pos = 0x9 + // Bit mask of IN_SUC_EOF_INT_RAW field. + I2S_INT_RAW_IN_SUC_EOF_INT_RAW_Msk = 0x200 + // Bit IN_SUC_EOF_INT_RAW. + I2S_INT_RAW_IN_SUC_EOF_INT_RAW = 0x200 + // Position of IN_ERR_EOF_INT_RAW field. + I2S_INT_RAW_IN_ERR_EOF_INT_RAW_Pos = 0xa + // Bit mask of IN_ERR_EOF_INT_RAW field. + I2S_INT_RAW_IN_ERR_EOF_INT_RAW_Msk = 0x400 + // Bit IN_ERR_EOF_INT_RAW. + I2S_INT_RAW_IN_ERR_EOF_INT_RAW = 0x400 + // Position of OUT_DONE_INT_RAW field. + I2S_INT_RAW_OUT_DONE_INT_RAW_Pos = 0xb + // Bit mask of OUT_DONE_INT_RAW field. + I2S_INT_RAW_OUT_DONE_INT_RAW_Msk = 0x800 + // Bit OUT_DONE_INT_RAW. + I2S_INT_RAW_OUT_DONE_INT_RAW = 0x800 + // Position of OUT_EOF_INT_RAW field. + I2S_INT_RAW_OUT_EOF_INT_RAW_Pos = 0xc + // Bit mask of OUT_EOF_INT_RAW field. + I2S_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x1000 + // Bit OUT_EOF_INT_RAW. + I2S_INT_RAW_OUT_EOF_INT_RAW = 0x1000 + // Position of IN_DSCR_ERR_INT_RAW field. + I2S_INT_RAW_IN_DSCR_ERR_INT_RAW_Pos = 0xd + // Bit mask of IN_DSCR_ERR_INT_RAW field. + I2S_INT_RAW_IN_DSCR_ERR_INT_RAW_Msk = 0x2000 + // Bit IN_DSCR_ERR_INT_RAW. + I2S_INT_RAW_IN_DSCR_ERR_INT_RAW = 0x2000 + // Position of OUT_DSCR_ERR_INT_RAW field. + I2S_INT_RAW_OUT_DSCR_ERR_INT_RAW_Pos = 0xe + // Bit mask of OUT_DSCR_ERR_INT_RAW field. + I2S_INT_RAW_OUT_DSCR_ERR_INT_RAW_Msk = 0x4000 + // Bit OUT_DSCR_ERR_INT_RAW. + I2S_INT_RAW_OUT_DSCR_ERR_INT_RAW = 0x4000 + // Position of IN_DSCR_EMPTY_INT_RAW field. + I2S_INT_RAW_IN_DSCR_EMPTY_INT_RAW_Pos = 0xf + // Bit mask of IN_DSCR_EMPTY_INT_RAW field. + I2S_INT_RAW_IN_DSCR_EMPTY_INT_RAW_Msk = 0x8000 + // Bit IN_DSCR_EMPTY_INT_RAW. + I2S_INT_RAW_IN_DSCR_EMPTY_INT_RAW = 0x8000 + // Position of OUT_TOTAL_EOF_INT_RAW field. + I2S_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Pos = 0x10 + // Bit mask of OUT_TOTAL_EOF_INT_RAW field. + I2S_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Msk = 0x10000 + // Bit OUT_TOTAL_EOF_INT_RAW. + I2S_INT_RAW_OUT_TOTAL_EOF_INT_RAW = 0x10000 + + // INT_ST + // Position of RX_TAKE_DATA_INT_ST field. + I2S_INT_ST_RX_TAKE_DATA_INT_ST_Pos = 0x0 + // Bit mask of RX_TAKE_DATA_INT_ST field. + I2S_INT_ST_RX_TAKE_DATA_INT_ST_Msk = 0x1 + // Bit RX_TAKE_DATA_INT_ST. + I2S_INT_ST_RX_TAKE_DATA_INT_ST = 0x1 + // Position of TX_PUT_DATA_INT_ST field. + I2S_INT_ST_TX_PUT_DATA_INT_ST_Pos = 0x1 + // Bit mask of TX_PUT_DATA_INT_ST field. + I2S_INT_ST_TX_PUT_DATA_INT_ST_Msk = 0x2 + // Bit TX_PUT_DATA_INT_ST. + I2S_INT_ST_TX_PUT_DATA_INT_ST = 0x2 + // Position of RX_WFULL_INT_ST field. + I2S_INT_ST_RX_WFULL_INT_ST_Pos = 0x2 + // Bit mask of RX_WFULL_INT_ST field. + I2S_INT_ST_RX_WFULL_INT_ST_Msk = 0x4 + // Bit RX_WFULL_INT_ST. + I2S_INT_ST_RX_WFULL_INT_ST = 0x4 + // Position of RX_REMPTY_INT_ST field. + I2S_INT_ST_RX_REMPTY_INT_ST_Pos = 0x3 + // Bit mask of RX_REMPTY_INT_ST field. + I2S_INT_ST_RX_REMPTY_INT_ST_Msk = 0x8 + // Bit RX_REMPTY_INT_ST. + I2S_INT_ST_RX_REMPTY_INT_ST = 0x8 + // Position of TX_WFULL_INT_ST field. + I2S_INT_ST_TX_WFULL_INT_ST_Pos = 0x4 + // Bit mask of TX_WFULL_INT_ST field. + I2S_INT_ST_TX_WFULL_INT_ST_Msk = 0x10 + // Bit TX_WFULL_INT_ST. + I2S_INT_ST_TX_WFULL_INT_ST = 0x10 + // Position of TX_REMPTY_INT_ST field. + I2S_INT_ST_TX_REMPTY_INT_ST_Pos = 0x5 + // Bit mask of TX_REMPTY_INT_ST field. + I2S_INT_ST_TX_REMPTY_INT_ST_Msk = 0x20 + // Bit TX_REMPTY_INT_ST. + I2S_INT_ST_TX_REMPTY_INT_ST = 0x20 + // Position of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Pos = 0x6 + // Bit mask of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Msk = 0x40 + // Bit RX_HUNG_INT_ST. + I2S_INT_ST_RX_HUNG_INT_ST = 0x40 + // Position of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Pos = 0x7 + // Bit mask of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Msk = 0x80 + // Bit TX_HUNG_INT_ST. + I2S_INT_ST_TX_HUNG_INT_ST = 0x80 + // Position of IN_DONE_INT_ST field. + I2S_INT_ST_IN_DONE_INT_ST_Pos = 0x8 + // Bit mask of IN_DONE_INT_ST field. + I2S_INT_ST_IN_DONE_INT_ST_Msk = 0x100 + // Bit IN_DONE_INT_ST. + I2S_INT_ST_IN_DONE_INT_ST = 0x100 + // Position of IN_SUC_EOF_INT_ST field. + I2S_INT_ST_IN_SUC_EOF_INT_ST_Pos = 0x9 + // Bit mask of IN_SUC_EOF_INT_ST field. + I2S_INT_ST_IN_SUC_EOF_INT_ST_Msk = 0x200 + // Bit IN_SUC_EOF_INT_ST. + I2S_INT_ST_IN_SUC_EOF_INT_ST = 0x200 + // Position of IN_ERR_EOF_INT_ST field. + I2S_INT_ST_IN_ERR_EOF_INT_ST_Pos = 0xa + // Bit mask of IN_ERR_EOF_INT_ST field. + I2S_INT_ST_IN_ERR_EOF_INT_ST_Msk = 0x400 + // Bit IN_ERR_EOF_INT_ST. + I2S_INT_ST_IN_ERR_EOF_INT_ST = 0x400 + // Position of OUT_DONE_INT_ST field. + I2S_INT_ST_OUT_DONE_INT_ST_Pos = 0xb + // Bit mask of OUT_DONE_INT_ST field. + I2S_INT_ST_OUT_DONE_INT_ST_Msk = 0x800 + // Bit OUT_DONE_INT_ST. + I2S_INT_ST_OUT_DONE_INT_ST = 0x800 + // Position of OUT_EOF_INT_ST field. + I2S_INT_ST_OUT_EOF_INT_ST_Pos = 0xc + // Bit mask of OUT_EOF_INT_ST field. + I2S_INT_ST_OUT_EOF_INT_ST_Msk = 0x1000 + // Bit OUT_EOF_INT_ST. + I2S_INT_ST_OUT_EOF_INT_ST = 0x1000 + // Position of IN_DSCR_ERR_INT_ST field. + I2S_INT_ST_IN_DSCR_ERR_INT_ST_Pos = 0xd + // Bit mask of IN_DSCR_ERR_INT_ST field. + I2S_INT_ST_IN_DSCR_ERR_INT_ST_Msk = 0x2000 + // Bit IN_DSCR_ERR_INT_ST. + I2S_INT_ST_IN_DSCR_ERR_INT_ST = 0x2000 + // Position of OUT_DSCR_ERR_INT_ST field. + I2S_INT_ST_OUT_DSCR_ERR_INT_ST_Pos = 0xe + // Bit mask of OUT_DSCR_ERR_INT_ST field. + I2S_INT_ST_OUT_DSCR_ERR_INT_ST_Msk = 0x4000 + // Bit OUT_DSCR_ERR_INT_ST. + I2S_INT_ST_OUT_DSCR_ERR_INT_ST = 0x4000 + // Position of IN_DSCR_EMPTY_INT_ST field. + I2S_INT_ST_IN_DSCR_EMPTY_INT_ST_Pos = 0xf + // Bit mask of IN_DSCR_EMPTY_INT_ST field. + I2S_INT_ST_IN_DSCR_EMPTY_INT_ST_Msk = 0x8000 + // Bit IN_DSCR_EMPTY_INT_ST. + I2S_INT_ST_IN_DSCR_EMPTY_INT_ST = 0x8000 + // Position of OUT_TOTAL_EOF_INT_ST field. + I2S_INT_ST_OUT_TOTAL_EOF_INT_ST_Pos = 0x10 + // Bit mask of OUT_TOTAL_EOF_INT_ST field. + I2S_INT_ST_OUT_TOTAL_EOF_INT_ST_Msk = 0x10000 + // Bit OUT_TOTAL_EOF_INT_ST. + I2S_INT_ST_OUT_TOTAL_EOF_INT_ST = 0x10000 + + // INT_ENA + // Position of RX_TAKE_DATA_INT_ENA field. + I2S_INT_ENA_RX_TAKE_DATA_INT_ENA_Pos = 0x0 + // Bit mask of RX_TAKE_DATA_INT_ENA field. + I2S_INT_ENA_RX_TAKE_DATA_INT_ENA_Msk = 0x1 + // Bit RX_TAKE_DATA_INT_ENA. + I2S_INT_ENA_RX_TAKE_DATA_INT_ENA = 0x1 + // Position of TX_PUT_DATA_INT_ENA field. + I2S_INT_ENA_TX_PUT_DATA_INT_ENA_Pos = 0x1 + // Bit mask of TX_PUT_DATA_INT_ENA field. + I2S_INT_ENA_TX_PUT_DATA_INT_ENA_Msk = 0x2 + // Bit TX_PUT_DATA_INT_ENA. + I2S_INT_ENA_TX_PUT_DATA_INT_ENA = 0x2 + // Position of RX_WFULL_INT_ENA field. + I2S_INT_ENA_RX_WFULL_INT_ENA_Pos = 0x2 + // Bit mask of RX_WFULL_INT_ENA field. + I2S_INT_ENA_RX_WFULL_INT_ENA_Msk = 0x4 + // Bit RX_WFULL_INT_ENA. + I2S_INT_ENA_RX_WFULL_INT_ENA = 0x4 + // Position of RX_REMPTY_INT_ENA field. + I2S_INT_ENA_RX_REMPTY_INT_ENA_Pos = 0x3 + // Bit mask of RX_REMPTY_INT_ENA field. + I2S_INT_ENA_RX_REMPTY_INT_ENA_Msk = 0x8 + // Bit RX_REMPTY_INT_ENA. + I2S_INT_ENA_RX_REMPTY_INT_ENA = 0x8 + // Position of TX_WFULL_INT_ENA field. + I2S_INT_ENA_TX_WFULL_INT_ENA_Pos = 0x4 + // Bit mask of TX_WFULL_INT_ENA field. + I2S_INT_ENA_TX_WFULL_INT_ENA_Msk = 0x10 + // Bit TX_WFULL_INT_ENA. + I2S_INT_ENA_TX_WFULL_INT_ENA = 0x10 + // Position of TX_REMPTY_INT_ENA field. + I2S_INT_ENA_TX_REMPTY_INT_ENA_Pos = 0x5 + // Bit mask of TX_REMPTY_INT_ENA field. + I2S_INT_ENA_TX_REMPTY_INT_ENA_Msk = 0x20 + // Bit TX_REMPTY_INT_ENA. + I2S_INT_ENA_TX_REMPTY_INT_ENA = 0x20 + // Position of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x6 + // Bit mask of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x40 + // Bit RX_HUNG_INT_ENA. + I2S_INT_ENA_RX_HUNG_INT_ENA = 0x40 + // Position of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x7 + // Bit mask of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x80 + // Bit TX_HUNG_INT_ENA. + I2S_INT_ENA_TX_HUNG_INT_ENA = 0x80 + // Position of IN_DONE_INT_ENA field. + I2S_INT_ENA_IN_DONE_INT_ENA_Pos = 0x8 + // Bit mask of IN_DONE_INT_ENA field. + I2S_INT_ENA_IN_DONE_INT_ENA_Msk = 0x100 + // Bit IN_DONE_INT_ENA. + I2S_INT_ENA_IN_DONE_INT_ENA = 0x100 + // Position of IN_SUC_EOF_INT_ENA field. + I2S_INT_ENA_IN_SUC_EOF_INT_ENA_Pos = 0x9 + // Bit mask of IN_SUC_EOF_INT_ENA field. + I2S_INT_ENA_IN_SUC_EOF_INT_ENA_Msk = 0x200 + // Bit IN_SUC_EOF_INT_ENA. + I2S_INT_ENA_IN_SUC_EOF_INT_ENA = 0x200 + // Position of IN_ERR_EOF_INT_ENA field. + I2S_INT_ENA_IN_ERR_EOF_INT_ENA_Pos = 0xa + // Bit mask of IN_ERR_EOF_INT_ENA field. + I2S_INT_ENA_IN_ERR_EOF_INT_ENA_Msk = 0x400 + // Bit IN_ERR_EOF_INT_ENA. + I2S_INT_ENA_IN_ERR_EOF_INT_ENA = 0x400 + // Position of OUT_DONE_INT_ENA field. + I2S_INT_ENA_OUT_DONE_INT_ENA_Pos = 0xb + // Bit mask of OUT_DONE_INT_ENA field. + I2S_INT_ENA_OUT_DONE_INT_ENA_Msk = 0x800 + // Bit OUT_DONE_INT_ENA. + I2S_INT_ENA_OUT_DONE_INT_ENA = 0x800 + // Position of OUT_EOF_INT_ENA field. + I2S_INT_ENA_OUT_EOF_INT_ENA_Pos = 0xc + // Bit mask of OUT_EOF_INT_ENA field. + I2S_INT_ENA_OUT_EOF_INT_ENA_Msk = 0x1000 + // Bit OUT_EOF_INT_ENA. + I2S_INT_ENA_OUT_EOF_INT_ENA = 0x1000 + // Position of IN_DSCR_ERR_INT_ENA field. + I2S_INT_ENA_IN_DSCR_ERR_INT_ENA_Pos = 0xd + // Bit mask of IN_DSCR_ERR_INT_ENA field. + I2S_INT_ENA_IN_DSCR_ERR_INT_ENA_Msk = 0x2000 + // Bit IN_DSCR_ERR_INT_ENA. + I2S_INT_ENA_IN_DSCR_ERR_INT_ENA = 0x2000 + // Position of OUT_DSCR_ERR_INT_ENA field. + I2S_INT_ENA_OUT_DSCR_ERR_INT_ENA_Pos = 0xe + // Bit mask of OUT_DSCR_ERR_INT_ENA field. + I2S_INT_ENA_OUT_DSCR_ERR_INT_ENA_Msk = 0x4000 + // Bit OUT_DSCR_ERR_INT_ENA. + I2S_INT_ENA_OUT_DSCR_ERR_INT_ENA = 0x4000 + // Position of IN_DSCR_EMPTY_INT_ENA field. + I2S_INT_ENA_IN_DSCR_EMPTY_INT_ENA_Pos = 0xf + // Bit mask of IN_DSCR_EMPTY_INT_ENA field. + I2S_INT_ENA_IN_DSCR_EMPTY_INT_ENA_Msk = 0x8000 + // Bit IN_DSCR_EMPTY_INT_ENA. + I2S_INT_ENA_IN_DSCR_EMPTY_INT_ENA = 0x8000 + // Position of OUT_TOTAL_EOF_INT_ENA field. + I2S_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Pos = 0x10 + // Bit mask of OUT_TOTAL_EOF_INT_ENA field. + I2S_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Msk = 0x10000 + // Bit OUT_TOTAL_EOF_INT_ENA. + I2S_INT_ENA_OUT_TOTAL_EOF_INT_ENA = 0x10000 + + // INT_CLR + // Position of TAKE_DATA_INT_CLR field. + I2S_INT_CLR_TAKE_DATA_INT_CLR_Pos = 0x0 + // Bit mask of TAKE_DATA_INT_CLR field. + I2S_INT_CLR_TAKE_DATA_INT_CLR_Msk = 0x1 + // Bit TAKE_DATA_INT_CLR. + I2S_INT_CLR_TAKE_DATA_INT_CLR = 0x1 + // Position of PUT_DATA_INT_CLR field. + I2S_INT_CLR_PUT_DATA_INT_CLR_Pos = 0x1 + // Bit mask of PUT_DATA_INT_CLR field. + I2S_INT_CLR_PUT_DATA_INT_CLR_Msk = 0x2 + // Bit PUT_DATA_INT_CLR. + I2S_INT_CLR_PUT_DATA_INT_CLR = 0x2 + // Position of RX_WFULL_INT_CLR field. + I2S_INT_CLR_RX_WFULL_INT_CLR_Pos = 0x2 + // Bit mask of RX_WFULL_INT_CLR field. + I2S_INT_CLR_RX_WFULL_INT_CLR_Msk = 0x4 + // Bit RX_WFULL_INT_CLR. + I2S_INT_CLR_RX_WFULL_INT_CLR = 0x4 + // Position of RX_REMPTY_INT_CLR field. + I2S_INT_CLR_RX_REMPTY_INT_CLR_Pos = 0x3 + // Bit mask of RX_REMPTY_INT_CLR field. + I2S_INT_CLR_RX_REMPTY_INT_CLR_Msk = 0x8 + // Bit RX_REMPTY_INT_CLR. + I2S_INT_CLR_RX_REMPTY_INT_CLR = 0x8 + // Position of TX_WFULL_INT_CLR field. + I2S_INT_CLR_TX_WFULL_INT_CLR_Pos = 0x4 + // Bit mask of TX_WFULL_INT_CLR field. + I2S_INT_CLR_TX_WFULL_INT_CLR_Msk = 0x10 + // Bit TX_WFULL_INT_CLR. + I2S_INT_CLR_TX_WFULL_INT_CLR = 0x10 + // Position of TX_REMPTY_INT_CLR field. + I2S_INT_CLR_TX_REMPTY_INT_CLR_Pos = 0x5 + // Bit mask of TX_REMPTY_INT_CLR field. + I2S_INT_CLR_TX_REMPTY_INT_CLR_Msk = 0x20 + // Bit TX_REMPTY_INT_CLR. + I2S_INT_CLR_TX_REMPTY_INT_CLR = 0x20 + // Position of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x6 + // Bit mask of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x40 + // Bit RX_HUNG_INT_CLR. + I2S_INT_CLR_RX_HUNG_INT_CLR = 0x40 + // Position of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x7 + // Bit mask of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x80 + // Bit TX_HUNG_INT_CLR. + I2S_INT_CLR_TX_HUNG_INT_CLR = 0x80 + // Position of IN_DONE_INT_CLR field. + I2S_INT_CLR_IN_DONE_INT_CLR_Pos = 0x8 + // Bit mask of IN_DONE_INT_CLR field. + I2S_INT_CLR_IN_DONE_INT_CLR_Msk = 0x100 + // Bit IN_DONE_INT_CLR. + I2S_INT_CLR_IN_DONE_INT_CLR = 0x100 + // Position of IN_SUC_EOF_INT_CLR field. + I2S_INT_CLR_IN_SUC_EOF_INT_CLR_Pos = 0x9 + // Bit mask of IN_SUC_EOF_INT_CLR field. + I2S_INT_CLR_IN_SUC_EOF_INT_CLR_Msk = 0x200 + // Bit IN_SUC_EOF_INT_CLR. + I2S_INT_CLR_IN_SUC_EOF_INT_CLR = 0x200 + // Position of IN_ERR_EOF_INT_CLR field. + I2S_INT_CLR_IN_ERR_EOF_INT_CLR_Pos = 0xa + // Bit mask of IN_ERR_EOF_INT_CLR field. + I2S_INT_CLR_IN_ERR_EOF_INT_CLR_Msk = 0x400 + // Bit IN_ERR_EOF_INT_CLR. + I2S_INT_CLR_IN_ERR_EOF_INT_CLR = 0x400 + // Position of OUT_DONE_INT_CLR field. + I2S_INT_CLR_OUT_DONE_INT_CLR_Pos = 0xb + // Bit mask of OUT_DONE_INT_CLR field. + I2S_INT_CLR_OUT_DONE_INT_CLR_Msk = 0x800 + // Bit OUT_DONE_INT_CLR. + I2S_INT_CLR_OUT_DONE_INT_CLR = 0x800 + // Position of OUT_EOF_INT_CLR field. + I2S_INT_CLR_OUT_EOF_INT_CLR_Pos = 0xc + // Bit mask of OUT_EOF_INT_CLR field. + I2S_INT_CLR_OUT_EOF_INT_CLR_Msk = 0x1000 + // Bit OUT_EOF_INT_CLR. + I2S_INT_CLR_OUT_EOF_INT_CLR = 0x1000 + // Position of IN_DSCR_ERR_INT_CLR field. + I2S_INT_CLR_IN_DSCR_ERR_INT_CLR_Pos = 0xd + // Bit mask of IN_DSCR_ERR_INT_CLR field. + I2S_INT_CLR_IN_DSCR_ERR_INT_CLR_Msk = 0x2000 + // Bit IN_DSCR_ERR_INT_CLR. + I2S_INT_CLR_IN_DSCR_ERR_INT_CLR = 0x2000 + // Position of OUT_DSCR_ERR_INT_CLR field. + I2S_INT_CLR_OUT_DSCR_ERR_INT_CLR_Pos = 0xe + // Bit mask of OUT_DSCR_ERR_INT_CLR field. + I2S_INT_CLR_OUT_DSCR_ERR_INT_CLR_Msk = 0x4000 + // Bit OUT_DSCR_ERR_INT_CLR. + I2S_INT_CLR_OUT_DSCR_ERR_INT_CLR = 0x4000 + // Position of IN_DSCR_EMPTY_INT_CLR field. + I2S_INT_CLR_IN_DSCR_EMPTY_INT_CLR_Pos = 0xf + // Bit mask of IN_DSCR_EMPTY_INT_CLR field. + I2S_INT_CLR_IN_DSCR_EMPTY_INT_CLR_Msk = 0x8000 + // Bit IN_DSCR_EMPTY_INT_CLR. + I2S_INT_CLR_IN_DSCR_EMPTY_INT_CLR = 0x8000 + // Position of OUT_TOTAL_EOF_INT_CLR field. + I2S_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Pos = 0x10 + // Bit mask of OUT_TOTAL_EOF_INT_CLR field. + I2S_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Msk = 0x10000 + // Bit OUT_TOTAL_EOF_INT_CLR. + I2S_INT_CLR_OUT_TOTAL_EOF_INT_CLR = 0x10000 + + // TIMING + // Position of TX_BCK_IN_DELAY field. + I2S_TIMING_TX_BCK_IN_DELAY_Pos = 0x0 + // Bit mask of TX_BCK_IN_DELAY field. + I2S_TIMING_TX_BCK_IN_DELAY_Msk = 0x3 + // Position of TX_WS_IN_DELAY field. + I2S_TIMING_TX_WS_IN_DELAY_Pos = 0x2 + // Bit mask of TX_WS_IN_DELAY field. + I2S_TIMING_TX_WS_IN_DELAY_Msk = 0xc + // Position of RX_BCK_IN_DELAY field. + I2S_TIMING_RX_BCK_IN_DELAY_Pos = 0x4 + // Bit mask of RX_BCK_IN_DELAY field. + I2S_TIMING_RX_BCK_IN_DELAY_Msk = 0x30 + // Position of RX_WS_IN_DELAY field. + I2S_TIMING_RX_WS_IN_DELAY_Pos = 0x6 + // Bit mask of RX_WS_IN_DELAY field. + I2S_TIMING_RX_WS_IN_DELAY_Msk = 0xc0 + // Position of RX_SD_IN_DELAY field. + I2S_TIMING_RX_SD_IN_DELAY_Pos = 0x8 + // Bit mask of RX_SD_IN_DELAY field. + I2S_TIMING_RX_SD_IN_DELAY_Msk = 0x300 + // Position of TX_BCK_OUT_DELAY field. + I2S_TIMING_TX_BCK_OUT_DELAY_Pos = 0xa + // Bit mask of TX_BCK_OUT_DELAY field. + I2S_TIMING_TX_BCK_OUT_DELAY_Msk = 0xc00 + // Position of TX_WS_OUT_DELAY field. + I2S_TIMING_TX_WS_OUT_DELAY_Pos = 0xc + // Bit mask of TX_WS_OUT_DELAY field. + I2S_TIMING_TX_WS_OUT_DELAY_Msk = 0x3000 + // Position of TX_SD_OUT_DELAY field. + I2S_TIMING_TX_SD_OUT_DELAY_Pos = 0xe + // Bit mask of TX_SD_OUT_DELAY field. + I2S_TIMING_TX_SD_OUT_DELAY_Msk = 0xc000 + // Position of RX_WS_OUT_DELAY field. + I2S_TIMING_RX_WS_OUT_DELAY_Pos = 0x10 + // Bit mask of RX_WS_OUT_DELAY field. + I2S_TIMING_RX_WS_OUT_DELAY_Msk = 0x30000 + // Position of RX_BCK_OUT_DELAY field. + I2S_TIMING_RX_BCK_OUT_DELAY_Pos = 0x12 + // Bit mask of RX_BCK_OUT_DELAY field. + I2S_TIMING_RX_BCK_OUT_DELAY_Msk = 0xc0000 + // Position of TX_DSYNC_SW field. + I2S_TIMING_TX_DSYNC_SW_Pos = 0x14 + // Bit mask of TX_DSYNC_SW field. + I2S_TIMING_TX_DSYNC_SW_Msk = 0x100000 + // Bit TX_DSYNC_SW. + I2S_TIMING_TX_DSYNC_SW = 0x100000 + // Position of RX_DSYNC_SW field. + I2S_TIMING_RX_DSYNC_SW_Pos = 0x15 + // Bit mask of RX_DSYNC_SW field. + I2S_TIMING_RX_DSYNC_SW_Msk = 0x200000 + // Bit RX_DSYNC_SW. + I2S_TIMING_RX_DSYNC_SW = 0x200000 + // Position of DATA_ENABLE_DELAY field. + I2S_TIMING_DATA_ENABLE_DELAY_Pos = 0x16 + // Bit mask of DATA_ENABLE_DELAY field. + I2S_TIMING_DATA_ENABLE_DELAY_Msk = 0xc00000 + // Position of TX_BCK_IN_INV field. + I2S_TIMING_TX_BCK_IN_INV_Pos = 0x18 + // Bit mask of TX_BCK_IN_INV field. + I2S_TIMING_TX_BCK_IN_INV_Msk = 0x1000000 + // Bit TX_BCK_IN_INV. + I2S_TIMING_TX_BCK_IN_INV = 0x1000000 + + // FIFO_CONF + // Position of RX_DATA_NUM field. + I2S_FIFO_CONF_RX_DATA_NUM_Pos = 0x0 + // Bit mask of RX_DATA_NUM field. + I2S_FIFO_CONF_RX_DATA_NUM_Msk = 0x3f + // Position of TX_DATA_NUM field. + I2S_FIFO_CONF_TX_DATA_NUM_Pos = 0x6 + // Bit mask of TX_DATA_NUM field. + I2S_FIFO_CONF_TX_DATA_NUM_Msk = 0xfc0 + // Position of DSCR_EN field. + I2S_FIFO_CONF_DSCR_EN_Pos = 0xc + // Bit mask of DSCR_EN field. + I2S_FIFO_CONF_DSCR_EN_Msk = 0x1000 + // Bit DSCR_EN. + I2S_FIFO_CONF_DSCR_EN = 0x1000 + // Position of TX_FIFO_MOD field. + I2S_FIFO_CONF_TX_FIFO_MOD_Pos = 0xd + // Bit mask of TX_FIFO_MOD field. + I2S_FIFO_CONF_TX_FIFO_MOD_Msk = 0xe000 + // Position of RX_FIFO_MOD field. + I2S_FIFO_CONF_RX_FIFO_MOD_Pos = 0x10 + // Bit mask of RX_FIFO_MOD field. + I2S_FIFO_CONF_RX_FIFO_MOD_Msk = 0x70000 + // Position of TX_FIFO_MOD_FORCE_EN field. + I2S_FIFO_CONF_TX_FIFO_MOD_FORCE_EN_Pos = 0x13 + // Bit mask of TX_FIFO_MOD_FORCE_EN field. + I2S_FIFO_CONF_TX_FIFO_MOD_FORCE_EN_Msk = 0x80000 + // Bit TX_FIFO_MOD_FORCE_EN. + I2S_FIFO_CONF_TX_FIFO_MOD_FORCE_EN = 0x80000 + // Position of RX_FIFO_MOD_FORCE_EN field. + I2S_FIFO_CONF_RX_FIFO_MOD_FORCE_EN_Pos = 0x14 + // Bit mask of RX_FIFO_MOD_FORCE_EN field. + I2S_FIFO_CONF_RX_FIFO_MOD_FORCE_EN_Msk = 0x100000 + // Bit RX_FIFO_MOD_FORCE_EN. + I2S_FIFO_CONF_RX_FIFO_MOD_FORCE_EN = 0x100000 + + // RXEOF_NUM + // Position of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Pos = 0x0 + // Bit mask of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Msk = 0xffffffff + + // CONF_SIGLE_DATA + // Position of SIGLE_DATA field. + I2S_CONF_SIGLE_DATA_SIGLE_DATA_Pos = 0x0 + // Bit mask of SIGLE_DATA field. + I2S_CONF_SIGLE_DATA_SIGLE_DATA_Msk = 0xffffffff + + // CONF_CHAN + // Position of TX_CHAN_MOD field. + I2S_CONF_CHAN_TX_CHAN_MOD_Pos = 0x0 + // Bit mask of TX_CHAN_MOD field. + I2S_CONF_CHAN_TX_CHAN_MOD_Msk = 0x7 + // Position of RX_CHAN_MOD field. + I2S_CONF_CHAN_RX_CHAN_MOD_Pos = 0x3 + // Bit mask of RX_CHAN_MOD field. + I2S_CONF_CHAN_RX_CHAN_MOD_Msk = 0x18 + + // OUT_LINK + // Position of OUTLINK_ADDR field. + I2S_OUT_LINK_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + I2S_OUT_LINK_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + I2S_OUT_LINK_OUTLINK_STOP_Pos = 0x1c + // Bit mask of OUTLINK_STOP field. + I2S_OUT_LINK_OUTLINK_STOP_Msk = 0x10000000 + // Bit OUTLINK_STOP. + I2S_OUT_LINK_OUTLINK_STOP = 0x10000000 + // Position of OUTLINK_START field. + I2S_OUT_LINK_OUTLINK_START_Pos = 0x1d + // Bit mask of OUTLINK_START field. + I2S_OUT_LINK_OUTLINK_START_Msk = 0x20000000 + // Bit OUTLINK_START. + I2S_OUT_LINK_OUTLINK_START = 0x20000000 + // Position of OUTLINK_RESTART field. + I2S_OUT_LINK_OUTLINK_RESTART_Pos = 0x1e + // Bit mask of OUTLINK_RESTART field. + I2S_OUT_LINK_OUTLINK_RESTART_Msk = 0x40000000 + // Bit OUTLINK_RESTART. + I2S_OUT_LINK_OUTLINK_RESTART = 0x40000000 + // Position of OUTLINK_PARK field. + I2S_OUT_LINK_OUTLINK_PARK_Pos = 0x1f + // Bit mask of OUTLINK_PARK field. + I2S_OUT_LINK_OUTLINK_PARK_Msk = 0x80000000 + // Bit OUTLINK_PARK. + I2S_OUT_LINK_OUTLINK_PARK = 0x80000000 + + // IN_LINK + // Position of INLINK_ADDR field. + I2S_IN_LINK_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + I2S_IN_LINK_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_STOP field. + I2S_IN_LINK_INLINK_STOP_Pos = 0x1c + // Bit mask of INLINK_STOP field. + I2S_IN_LINK_INLINK_STOP_Msk = 0x10000000 + // Bit INLINK_STOP. + I2S_IN_LINK_INLINK_STOP = 0x10000000 + // Position of INLINK_START field. + I2S_IN_LINK_INLINK_START_Pos = 0x1d + // Bit mask of INLINK_START field. + I2S_IN_LINK_INLINK_START_Msk = 0x20000000 + // Bit INLINK_START. + I2S_IN_LINK_INLINK_START = 0x20000000 + // Position of INLINK_RESTART field. + I2S_IN_LINK_INLINK_RESTART_Pos = 0x1e + // Bit mask of INLINK_RESTART field. + I2S_IN_LINK_INLINK_RESTART_Msk = 0x40000000 + // Bit INLINK_RESTART. + I2S_IN_LINK_INLINK_RESTART = 0x40000000 + // Position of INLINK_PARK field. + I2S_IN_LINK_INLINK_PARK_Pos = 0x1f + // Bit mask of INLINK_PARK field. + I2S_IN_LINK_INLINK_PARK_Msk = 0x80000000 + // Bit INLINK_PARK. + I2S_IN_LINK_INLINK_PARK = 0x80000000 + + // OUT_EOF_DES_ADDR + // Position of OUT_EOF_DES_ADDR field. + I2S_OUT_EOF_DES_ADDR_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + I2S_OUT_EOF_DES_ADDR_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_EOF_DES_ADDR + // Position of IN_SUC_EOF_DES_ADDR field. + I2S_IN_EOF_DES_ADDR_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + I2S_IN_EOF_DES_ADDR_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR + // Position of OUT_EOF_BFR_DES_ADDR field. + I2S_OUT_EOF_BFR_DES_ADDR_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + I2S_OUT_EOF_BFR_DES_ADDR_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // AHB_TEST + // Position of AHB_TESTMODE field. + I2S_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + I2S_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + I2S_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + I2S_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // INLINK_DSCR + // Position of INLINK_DSCR field. + I2S_INLINK_DSCR_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + I2S_INLINK_DSCR_INLINK_DSCR_Msk = 0xffffffff + + // INLINK_DSCR_BF0 + // Position of INLINK_DSCR_BF0 field. + I2S_INLINK_DSCR_BF0_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + I2S_INLINK_DSCR_BF0_INLINK_DSCR_BF0_Msk = 0xffffffff + + // INLINK_DSCR_BF1 + // Position of INLINK_DSCR_BF1 field. + I2S_INLINK_DSCR_BF1_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + I2S_INLINK_DSCR_BF1_INLINK_DSCR_BF1_Msk = 0xffffffff + + // OUTLINK_DSCR + // Position of OUTLINK_DSCR field. + I2S_OUTLINK_DSCR_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + I2S_OUTLINK_DSCR_OUTLINK_DSCR_Msk = 0xffffffff + + // OUTLINK_DSCR_BF0 + // Position of OUTLINK_DSCR_BF0 field. + I2S_OUTLINK_DSCR_BF0_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + I2S_OUTLINK_DSCR_BF0_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUTLINK_DSCR_BF1 + // Position of OUTLINK_DSCR_BF1 field. + I2S_OUTLINK_DSCR_BF1_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + I2S_OUTLINK_DSCR_BF1_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // LC_CONF + // Position of IN_RST field. + I2S_LC_CONF_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + I2S_LC_CONF_IN_RST_Msk = 0x1 + // Bit IN_RST. + I2S_LC_CONF_IN_RST = 0x1 + // Position of OUT_RST field. + I2S_LC_CONF_OUT_RST_Pos = 0x1 + // Bit mask of OUT_RST field. + I2S_LC_CONF_OUT_RST_Msk = 0x2 + // Bit OUT_RST. + I2S_LC_CONF_OUT_RST = 0x2 + // Position of AHBM_FIFO_RST field. + I2S_LC_CONF_AHBM_FIFO_RST_Pos = 0x2 + // Bit mask of AHBM_FIFO_RST field. + I2S_LC_CONF_AHBM_FIFO_RST_Msk = 0x4 + // Bit AHBM_FIFO_RST. + I2S_LC_CONF_AHBM_FIFO_RST = 0x4 + // Position of AHBM_RST field. + I2S_LC_CONF_AHBM_RST_Pos = 0x3 + // Bit mask of AHBM_RST field. + I2S_LC_CONF_AHBM_RST_Msk = 0x8 + // Bit AHBM_RST. + I2S_LC_CONF_AHBM_RST = 0x8 + // Position of OUT_LOOP_TEST field. + I2S_LC_CONF_OUT_LOOP_TEST_Pos = 0x4 + // Bit mask of OUT_LOOP_TEST field. + I2S_LC_CONF_OUT_LOOP_TEST_Msk = 0x10 + // Bit OUT_LOOP_TEST. + I2S_LC_CONF_OUT_LOOP_TEST = 0x10 + // Position of IN_LOOP_TEST field. + I2S_LC_CONF_IN_LOOP_TEST_Pos = 0x5 + // Bit mask of IN_LOOP_TEST field. + I2S_LC_CONF_IN_LOOP_TEST_Msk = 0x20 + // Bit IN_LOOP_TEST. + I2S_LC_CONF_IN_LOOP_TEST = 0x20 + // Position of OUT_AUTO_WRBACK field. + I2S_LC_CONF_OUT_AUTO_WRBACK_Pos = 0x6 + // Bit mask of OUT_AUTO_WRBACK field. + I2S_LC_CONF_OUT_AUTO_WRBACK_Msk = 0x40 + // Bit OUT_AUTO_WRBACK. + I2S_LC_CONF_OUT_AUTO_WRBACK = 0x40 + // Position of OUT_NO_RESTART_CLR field. + I2S_LC_CONF_OUT_NO_RESTART_CLR_Pos = 0x7 + // Bit mask of OUT_NO_RESTART_CLR field. + I2S_LC_CONF_OUT_NO_RESTART_CLR_Msk = 0x80 + // Bit OUT_NO_RESTART_CLR. + I2S_LC_CONF_OUT_NO_RESTART_CLR = 0x80 + // Position of OUT_EOF_MODE field. + I2S_LC_CONF_OUT_EOF_MODE_Pos = 0x8 + // Bit mask of OUT_EOF_MODE field. + I2S_LC_CONF_OUT_EOF_MODE_Msk = 0x100 + // Bit OUT_EOF_MODE. + I2S_LC_CONF_OUT_EOF_MODE = 0x100 + // Position of OUTDSCR_BURST_EN field. + I2S_LC_CONF_OUTDSCR_BURST_EN_Pos = 0x9 + // Bit mask of OUTDSCR_BURST_EN field. + I2S_LC_CONF_OUTDSCR_BURST_EN_Msk = 0x200 + // Bit OUTDSCR_BURST_EN. + I2S_LC_CONF_OUTDSCR_BURST_EN = 0x200 + // Position of INDSCR_BURST_EN field. + I2S_LC_CONF_INDSCR_BURST_EN_Pos = 0xa + // Bit mask of INDSCR_BURST_EN field. + I2S_LC_CONF_INDSCR_BURST_EN_Msk = 0x400 + // Bit INDSCR_BURST_EN. + I2S_LC_CONF_INDSCR_BURST_EN = 0x400 + // Position of OUT_DATA_BURST_EN field. + I2S_LC_CONF_OUT_DATA_BURST_EN_Pos = 0xb + // Bit mask of OUT_DATA_BURST_EN field. + I2S_LC_CONF_OUT_DATA_BURST_EN_Msk = 0x800 + // Bit OUT_DATA_BURST_EN. + I2S_LC_CONF_OUT_DATA_BURST_EN = 0x800 + // Position of CHECK_OWNER field. + I2S_LC_CONF_CHECK_OWNER_Pos = 0xc + // Bit mask of CHECK_OWNER field. + I2S_LC_CONF_CHECK_OWNER_Msk = 0x1000 + // Bit CHECK_OWNER. + I2S_LC_CONF_CHECK_OWNER = 0x1000 + // Position of MEM_TRANS_EN field. + I2S_LC_CONF_MEM_TRANS_EN_Pos = 0xd + // Bit mask of MEM_TRANS_EN field. + I2S_LC_CONF_MEM_TRANS_EN_Msk = 0x2000 + // Bit MEM_TRANS_EN. + I2S_LC_CONF_MEM_TRANS_EN = 0x2000 + + // OUTFIFO_PUSH + // Position of OUTFIFO_WDATA field. + I2S_OUTFIFO_PUSH_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + I2S_OUTFIFO_PUSH_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + I2S_OUTFIFO_PUSH_OUTFIFO_PUSH_Pos = 0x10 + // Bit mask of OUTFIFO_PUSH field. + I2S_OUTFIFO_PUSH_OUTFIFO_PUSH_Msk = 0x10000 + // Bit OUTFIFO_PUSH. + I2S_OUTFIFO_PUSH_OUTFIFO_PUSH = 0x10000 + + // INFIFO_POP + // Position of INFIFO_RDATA field. + I2S_INFIFO_POP_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + I2S_INFIFO_POP_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + I2S_INFIFO_POP_INFIFO_POP_Pos = 0x10 + // Bit mask of INFIFO_POP field. + I2S_INFIFO_POP_INFIFO_POP_Msk = 0x10000 + // Bit INFIFO_POP. + I2S_INFIFO_POP_INFIFO_POP = 0x10000 + + // LC_STATE0 + // Position of LC_STATE0 field. + I2S_LC_STATE0_LC_STATE0_Pos = 0x0 + // Bit mask of LC_STATE0 field. + I2S_LC_STATE0_LC_STATE0_Msk = 0xffffffff + + // LC_STATE1 + // Position of LC_STATE1 field. + I2S_LC_STATE1_LC_STATE1_Pos = 0x0 + // Bit mask of LC_STATE1 field. + I2S_LC_STATE1_LC_STATE1_Msk = 0xffffffff + + // LC_HUNG_CONF + // Position of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Pos = 0x0 + // Bit mask of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Msk = 0xff + // Position of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit LC_FIFO_TIMEOUT_ENA. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA = 0x800 + + // CVSD_CONF0 + // Position of CVSD_Y_MAX field. + I2S_CVSD_CONF0_CVSD_Y_MAX_Pos = 0x0 + // Bit mask of CVSD_Y_MAX field. + I2S_CVSD_CONF0_CVSD_Y_MAX_Msk = 0xffff + // Position of CVSD_Y_MIN field. + I2S_CVSD_CONF0_CVSD_Y_MIN_Pos = 0x10 + // Bit mask of CVSD_Y_MIN field. + I2S_CVSD_CONF0_CVSD_Y_MIN_Msk = 0xffff0000 + + // CVSD_CONF1 + // Position of CVSD_SIGMA_MAX field. + I2S_CVSD_CONF1_CVSD_SIGMA_MAX_Pos = 0x0 + // Bit mask of CVSD_SIGMA_MAX field. + I2S_CVSD_CONF1_CVSD_SIGMA_MAX_Msk = 0xffff + // Position of CVSD_SIGMA_MIN field. + I2S_CVSD_CONF1_CVSD_SIGMA_MIN_Pos = 0x10 + // Bit mask of CVSD_SIGMA_MIN field. + I2S_CVSD_CONF1_CVSD_SIGMA_MIN_Msk = 0xffff0000 + + // CVSD_CONF2 + // Position of CVSD_K field. + I2S_CVSD_CONF2_CVSD_K_Pos = 0x0 + // Bit mask of CVSD_K field. + I2S_CVSD_CONF2_CVSD_K_Msk = 0x7 + // Position of CVSD_J field. + I2S_CVSD_CONF2_CVSD_J_Pos = 0x3 + // Bit mask of CVSD_J field. + I2S_CVSD_CONF2_CVSD_J_Msk = 0x38 + // Position of CVSD_BETA field. + I2S_CVSD_CONF2_CVSD_BETA_Pos = 0x6 + // Bit mask of CVSD_BETA field. + I2S_CVSD_CONF2_CVSD_BETA_Msk = 0xffc0 + // Position of CVSD_H field. + I2S_CVSD_CONF2_CVSD_H_Pos = 0x10 + // Bit mask of CVSD_H field. + I2S_CVSD_CONF2_CVSD_H_Msk = 0x70000 + + // PLC_CONF0 + // Position of GOOD_PACK_MAX field. + I2S_PLC_CONF0_GOOD_PACK_MAX_Pos = 0x0 + // Bit mask of GOOD_PACK_MAX field. + I2S_PLC_CONF0_GOOD_PACK_MAX_Msk = 0x3f + // Position of N_ERR_SEG field. + I2S_PLC_CONF0_N_ERR_SEG_Pos = 0x6 + // Bit mask of N_ERR_SEG field. + I2S_PLC_CONF0_N_ERR_SEG_Msk = 0x1c0 + // Position of SHIFT_RATE field. + I2S_PLC_CONF0_SHIFT_RATE_Pos = 0x9 + // Bit mask of SHIFT_RATE field. + I2S_PLC_CONF0_SHIFT_RATE_Msk = 0xe00 + // Position of MAX_SLIDE_SAMPLE field. + I2S_PLC_CONF0_MAX_SLIDE_SAMPLE_Pos = 0xc + // Bit mask of MAX_SLIDE_SAMPLE field. + I2S_PLC_CONF0_MAX_SLIDE_SAMPLE_Msk = 0xff000 + // Position of PACK_LEN_8K field. + I2S_PLC_CONF0_PACK_LEN_8K_Pos = 0x14 + // Bit mask of PACK_LEN_8K field. + I2S_PLC_CONF0_PACK_LEN_8K_Msk = 0x1f00000 + // Position of N_MIN_ERR field. + I2S_PLC_CONF0_N_MIN_ERR_Pos = 0x19 + // Bit mask of N_MIN_ERR field. + I2S_PLC_CONF0_N_MIN_ERR_Msk = 0xe000000 + + // PLC_CONF1 + // Position of BAD_CEF_ATTEN_PARA field. + I2S_PLC_CONF1_BAD_CEF_ATTEN_PARA_Pos = 0x0 + // Bit mask of BAD_CEF_ATTEN_PARA field. + I2S_PLC_CONF1_BAD_CEF_ATTEN_PARA_Msk = 0xff + // Position of BAD_CEF_ATTEN_PARA_SHIFT field. + I2S_PLC_CONF1_BAD_CEF_ATTEN_PARA_SHIFT_Pos = 0x8 + // Bit mask of BAD_CEF_ATTEN_PARA_SHIFT field. + I2S_PLC_CONF1_BAD_CEF_ATTEN_PARA_SHIFT_Msk = 0xf00 + // Position of BAD_OLA_WIN2_PARA_SHIFT field. + I2S_PLC_CONF1_BAD_OLA_WIN2_PARA_SHIFT_Pos = 0xc + // Bit mask of BAD_OLA_WIN2_PARA_SHIFT field. + I2S_PLC_CONF1_BAD_OLA_WIN2_PARA_SHIFT_Msk = 0xf000 + // Position of BAD_OLA_WIN2_PARA field. + I2S_PLC_CONF1_BAD_OLA_WIN2_PARA_Pos = 0x10 + // Bit mask of BAD_OLA_WIN2_PARA field. + I2S_PLC_CONF1_BAD_OLA_WIN2_PARA_Msk = 0xff0000 + // Position of SLIDE_WIN_LEN field. + I2S_PLC_CONF1_SLIDE_WIN_LEN_Pos = 0x18 + // Bit mask of SLIDE_WIN_LEN field. + I2S_PLC_CONF1_SLIDE_WIN_LEN_Msk = 0xff000000 + + // PLC_CONF2 + // Position of CVSD_SEG_MOD field. + I2S_PLC_CONF2_CVSD_SEG_MOD_Pos = 0x0 + // Bit mask of CVSD_SEG_MOD field. + I2S_PLC_CONF2_CVSD_SEG_MOD_Msk = 0x3 + // Position of MIN_PERIOD field. + I2S_PLC_CONF2_MIN_PERIOD_Pos = 0x2 + // Bit mask of MIN_PERIOD field. + I2S_PLC_CONF2_MIN_PERIOD_Msk = 0x7c + + // ESCO_CONF0 + // Position of ESCO_EN field. + I2S_ESCO_CONF0_ESCO_EN_Pos = 0x0 + // Bit mask of ESCO_EN field. + I2S_ESCO_CONF0_ESCO_EN_Msk = 0x1 + // Bit ESCO_EN. + I2S_ESCO_CONF0_ESCO_EN = 0x1 + // Position of ESCO_CHAN_MOD field. + I2S_ESCO_CONF0_ESCO_CHAN_MOD_Pos = 0x1 + // Bit mask of ESCO_CHAN_MOD field. + I2S_ESCO_CONF0_ESCO_CHAN_MOD_Msk = 0x2 + // Bit ESCO_CHAN_MOD. + I2S_ESCO_CONF0_ESCO_CHAN_MOD = 0x2 + // Position of ESCO_CVSD_DEC_PACK_ERR field. + I2S_ESCO_CONF0_ESCO_CVSD_DEC_PACK_ERR_Pos = 0x2 + // Bit mask of ESCO_CVSD_DEC_PACK_ERR field. + I2S_ESCO_CONF0_ESCO_CVSD_DEC_PACK_ERR_Msk = 0x4 + // Bit ESCO_CVSD_DEC_PACK_ERR. + I2S_ESCO_CONF0_ESCO_CVSD_DEC_PACK_ERR = 0x4 + // Position of ESCO_CVSD_PACK_LEN_8K field. + I2S_ESCO_CONF0_ESCO_CVSD_PACK_LEN_8K_Pos = 0x3 + // Bit mask of ESCO_CVSD_PACK_LEN_8K field. + I2S_ESCO_CONF0_ESCO_CVSD_PACK_LEN_8K_Msk = 0xf8 + // Position of ESCO_CVSD_INF_EN field. + I2S_ESCO_CONF0_ESCO_CVSD_INF_EN_Pos = 0x8 + // Bit mask of ESCO_CVSD_INF_EN field. + I2S_ESCO_CONF0_ESCO_CVSD_INF_EN_Msk = 0x100 + // Bit ESCO_CVSD_INF_EN. + I2S_ESCO_CONF0_ESCO_CVSD_INF_EN = 0x100 + // Position of CVSD_DEC_START field. + I2S_ESCO_CONF0_CVSD_DEC_START_Pos = 0x9 + // Bit mask of CVSD_DEC_START field. + I2S_ESCO_CONF0_CVSD_DEC_START_Msk = 0x200 + // Bit CVSD_DEC_START. + I2S_ESCO_CONF0_CVSD_DEC_START = 0x200 + // Position of CVSD_DEC_RESET field. + I2S_ESCO_CONF0_CVSD_DEC_RESET_Pos = 0xa + // Bit mask of CVSD_DEC_RESET field. + I2S_ESCO_CONF0_CVSD_DEC_RESET_Msk = 0x400 + // Bit CVSD_DEC_RESET. + I2S_ESCO_CONF0_CVSD_DEC_RESET = 0x400 + // Position of PLC_EN field. + I2S_ESCO_CONF0_PLC_EN_Pos = 0xb + // Bit mask of PLC_EN field. + I2S_ESCO_CONF0_PLC_EN_Msk = 0x800 + // Bit PLC_EN. + I2S_ESCO_CONF0_PLC_EN = 0x800 + // Position of PLC2DMA_EN field. + I2S_ESCO_CONF0_PLC2DMA_EN_Pos = 0xc + // Bit mask of PLC2DMA_EN field. + I2S_ESCO_CONF0_PLC2DMA_EN_Msk = 0x1000 + // Bit PLC2DMA_EN. + I2S_ESCO_CONF0_PLC2DMA_EN = 0x1000 + + // SCO_CONF0 + // Position of SCO_WITH_I2S_EN field. + I2S_SCO_CONF0_SCO_WITH_I2S_EN_Pos = 0x0 + // Bit mask of SCO_WITH_I2S_EN field. + I2S_SCO_CONF0_SCO_WITH_I2S_EN_Msk = 0x1 + // Bit SCO_WITH_I2S_EN. + I2S_SCO_CONF0_SCO_WITH_I2S_EN = 0x1 + // Position of SCO_NO_I2S_EN field. + I2S_SCO_CONF0_SCO_NO_I2S_EN_Pos = 0x1 + // Bit mask of SCO_NO_I2S_EN field. + I2S_SCO_CONF0_SCO_NO_I2S_EN_Msk = 0x2 + // Bit SCO_NO_I2S_EN. + I2S_SCO_CONF0_SCO_NO_I2S_EN = 0x2 + // Position of CVSD_ENC_START field. + I2S_SCO_CONF0_CVSD_ENC_START_Pos = 0x2 + // Bit mask of CVSD_ENC_START field. + I2S_SCO_CONF0_CVSD_ENC_START_Msk = 0x4 + // Bit CVSD_ENC_START. + I2S_SCO_CONF0_CVSD_ENC_START = 0x4 + // Position of CVSD_ENC_RESET field. + I2S_SCO_CONF0_CVSD_ENC_RESET_Pos = 0x3 + // Bit mask of CVSD_ENC_RESET field. + I2S_SCO_CONF0_CVSD_ENC_RESET_Msk = 0x8 + // Bit CVSD_ENC_RESET. + I2S_SCO_CONF0_CVSD_ENC_RESET = 0x8 + + // CONF1 + // Position of TX_PCM_CONF field. + I2S_CONF1_TX_PCM_CONF_Pos = 0x0 + // Bit mask of TX_PCM_CONF field. + I2S_CONF1_TX_PCM_CONF_Msk = 0x7 + // Position of TX_PCM_BYPASS field. + I2S_CONF1_TX_PCM_BYPASS_Pos = 0x3 + // Bit mask of TX_PCM_BYPASS field. + I2S_CONF1_TX_PCM_BYPASS_Msk = 0x8 + // Bit TX_PCM_BYPASS. + I2S_CONF1_TX_PCM_BYPASS = 0x8 + // Position of RX_PCM_CONF field. + I2S_CONF1_RX_PCM_CONF_Pos = 0x4 + // Bit mask of RX_PCM_CONF field. + I2S_CONF1_RX_PCM_CONF_Msk = 0x70 + // Position of RX_PCM_BYPASS field. + I2S_CONF1_RX_PCM_BYPASS_Pos = 0x7 + // Bit mask of RX_PCM_BYPASS field. + I2S_CONF1_RX_PCM_BYPASS_Msk = 0x80 + // Bit RX_PCM_BYPASS. + I2S_CONF1_RX_PCM_BYPASS = 0x80 + // Position of TX_STOP_EN field. + I2S_CONF1_TX_STOP_EN_Pos = 0x8 + // Bit mask of TX_STOP_EN field. + I2S_CONF1_TX_STOP_EN_Msk = 0x100 + // Bit TX_STOP_EN. + I2S_CONF1_TX_STOP_EN = 0x100 + // Position of TX_ZEROS_RM_EN field. + I2S_CONF1_TX_ZEROS_RM_EN_Pos = 0x9 + // Bit mask of TX_ZEROS_RM_EN field. + I2S_CONF1_TX_ZEROS_RM_EN_Msk = 0x200 + // Bit TX_ZEROS_RM_EN. + I2S_CONF1_TX_ZEROS_RM_EN = 0x200 + + // PD_CONF + // Position of FIFO_FORCE_PD field. + I2S_PD_CONF_FIFO_FORCE_PD_Pos = 0x0 + // Bit mask of FIFO_FORCE_PD field. + I2S_PD_CONF_FIFO_FORCE_PD_Msk = 0x1 + // Bit FIFO_FORCE_PD. + I2S_PD_CONF_FIFO_FORCE_PD = 0x1 + // Position of FIFO_FORCE_PU field. + I2S_PD_CONF_FIFO_FORCE_PU_Pos = 0x1 + // Bit mask of FIFO_FORCE_PU field. + I2S_PD_CONF_FIFO_FORCE_PU_Msk = 0x2 + // Bit FIFO_FORCE_PU. + I2S_PD_CONF_FIFO_FORCE_PU = 0x2 + // Position of PLC_MEM_FORCE_PD field. + I2S_PD_CONF_PLC_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of PLC_MEM_FORCE_PD field. + I2S_PD_CONF_PLC_MEM_FORCE_PD_Msk = 0x4 + // Bit PLC_MEM_FORCE_PD. + I2S_PD_CONF_PLC_MEM_FORCE_PD = 0x4 + // Position of PLC_MEM_FORCE_PU field. + I2S_PD_CONF_PLC_MEM_FORCE_PU_Pos = 0x3 + // Bit mask of PLC_MEM_FORCE_PU field. + I2S_PD_CONF_PLC_MEM_FORCE_PU_Msk = 0x8 + // Bit PLC_MEM_FORCE_PU. + I2S_PD_CONF_PLC_MEM_FORCE_PU = 0x8 + + // CONF2 + // Position of CAMERA_EN field. + I2S_CONF2_CAMERA_EN_Pos = 0x0 + // Bit mask of CAMERA_EN field. + I2S_CONF2_CAMERA_EN_Msk = 0x1 + // Bit CAMERA_EN. + I2S_CONF2_CAMERA_EN = 0x1 + // Position of LCD_TX_WRX2_EN field. + I2S_CONF2_LCD_TX_WRX2_EN_Pos = 0x1 + // Bit mask of LCD_TX_WRX2_EN field. + I2S_CONF2_LCD_TX_WRX2_EN_Msk = 0x2 + // Bit LCD_TX_WRX2_EN. + I2S_CONF2_LCD_TX_WRX2_EN = 0x2 + // Position of LCD_TX_SDX2_EN field. + I2S_CONF2_LCD_TX_SDX2_EN_Pos = 0x2 + // Bit mask of LCD_TX_SDX2_EN field. + I2S_CONF2_LCD_TX_SDX2_EN_Msk = 0x4 + // Bit LCD_TX_SDX2_EN. + I2S_CONF2_LCD_TX_SDX2_EN = 0x4 + // Position of DATA_ENABLE_TEST_EN field. + I2S_CONF2_DATA_ENABLE_TEST_EN_Pos = 0x3 + // Bit mask of DATA_ENABLE_TEST_EN field. + I2S_CONF2_DATA_ENABLE_TEST_EN_Msk = 0x8 + // Bit DATA_ENABLE_TEST_EN. + I2S_CONF2_DATA_ENABLE_TEST_EN = 0x8 + // Position of DATA_ENABLE field. + I2S_CONF2_DATA_ENABLE_Pos = 0x4 + // Bit mask of DATA_ENABLE field. + I2S_CONF2_DATA_ENABLE_Msk = 0x10 + // Bit DATA_ENABLE. + I2S_CONF2_DATA_ENABLE = 0x10 + // Position of LCD_EN field. + I2S_CONF2_LCD_EN_Pos = 0x5 + // Bit mask of LCD_EN field. + I2S_CONF2_LCD_EN_Msk = 0x20 + // Bit LCD_EN. + I2S_CONF2_LCD_EN = 0x20 + // Position of EXT_ADC_START_EN field. + I2S_CONF2_EXT_ADC_START_EN_Pos = 0x6 + // Bit mask of EXT_ADC_START_EN field. + I2S_CONF2_EXT_ADC_START_EN_Msk = 0x40 + // Bit EXT_ADC_START_EN. + I2S_CONF2_EXT_ADC_START_EN = 0x40 + // Position of INTER_VALID_EN field. + I2S_CONF2_INTER_VALID_EN_Pos = 0x7 + // Bit mask of INTER_VALID_EN field. + I2S_CONF2_INTER_VALID_EN_Msk = 0x80 + // Bit INTER_VALID_EN. + I2S_CONF2_INTER_VALID_EN = 0x80 + + // CLKM_CONF + // Position of CLKM_DIV_NUM field. + I2S_CLKM_CONF_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of CLKM_DIV_NUM field. + I2S_CLKM_CONF_CLKM_DIV_NUM_Msk = 0xff + // Position of CLKM_DIV_B field. + I2S_CLKM_CONF_CLKM_DIV_B_Pos = 0x8 + // Bit mask of CLKM_DIV_B field. + I2S_CLKM_CONF_CLKM_DIV_B_Msk = 0x3f00 + // Position of CLKM_DIV_A field. + I2S_CLKM_CONF_CLKM_DIV_A_Pos = 0xe + // Bit mask of CLKM_DIV_A field. + I2S_CLKM_CONF_CLKM_DIV_A_Msk = 0xfc000 + // Position of CLK_EN field. + I2S_CLKM_CONF_CLK_EN_Pos = 0x14 + // Bit mask of CLK_EN field. + I2S_CLKM_CONF_CLK_EN_Msk = 0x100000 + // Bit CLK_EN. + I2S_CLKM_CONF_CLK_EN = 0x100000 + // Position of CLKA_ENA field. + I2S_CLKM_CONF_CLKA_ENA_Pos = 0x15 + // Bit mask of CLKA_ENA field. + I2S_CLKM_CONF_CLKA_ENA_Msk = 0x200000 + // Bit CLKA_ENA. + I2S_CLKM_CONF_CLKA_ENA = 0x200000 + + // SAMPLE_RATE_CONF + // Position of TX_BCK_DIV_NUM field. + I2S_SAMPLE_RATE_CONF_TX_BCK_DIV_NUM_Pos = 0x0 + // Bit mask of TX_BCK_DIV_NUM field. + I2S_SAMPLE_RATE_CONF_TX_BCK_DIV_NUM_Msk = 0x3f + // Position of RX_BCK_DIV_NUM field. + I2S_SAMPLE_RATE_CONF_RX_BCK_DIV_NUM_Pos = 0x6 + // Bit mask of RX_BCK_DIV_NUM field. + I2S_SAMPLE_RATE_CONF_RX_BCK_DIV_NUM_Msk = 0xfc0 + // Position of TX_BITS_MOD field. + I2S_SAMPLE_RATE_CONF_TX_BITS_MOD_Pos = 0xc + // Bit mask of TX_BITS_MOD field. + I2S_SAMPLE_RATE_CONF_TX_BITS_MOD_Msk = 0x3f000 + // Position of RX_BITS_MOD field. + I2S_SAMPLE_RATE_CONF_RX_BITS_MOD_Pos = 0x12 + // Bit mask of RX_BITS_MOD field. + I2S_SAMPLE_RATE_CONF_RX_BITS_MOD_Msk = 0xfc0000 + + // PDM_CONF + // Position of TX_PDM_EN field. + I2S_PDM_CONF_TX_PDM_EN_Pos = 0x0 + // Bit mask of TX_PDM_EN field. + I2S_PDM_CONF_TX_PDM_EN_Msk = 0x1 + // Bit TX_PDM_EN. + I2S_PDM_CONF_TX_PDM_EN = 0x1 + // Position of RX_PDM_EN field. + I2S_PDM_CONF_RX_PDM_EN_Pos = 0x1 + // Bit mask of RX_PDM_EN field. + I2S_PDM_CONF_RX_PDM_EN_Msk = 0x2 + // Bit RX_PDM_EN. + I2S_PDM_CONF_RX_PDM_EN = 0x2 + // Position of PCM2PDM_CONV_EN field. + I2S_PDM_CONF_PCM2PDM_CONV_EN_Pos = 0x2 + // Bit mask of PCM2PDM_CONV_EN field. + I2S_PDM_CONF_PCM2PDM_CONV_EN_Msk = 0x4 + // Bit PCM2PDM_CONV_EN. + I2S_PDM_CONF_PCM2PDM_CONV_EN = 0x4 + // Position of PDM2PCM_CONV_EN field. + I2S_PDM_CONF_PDM2PCM_CONV_EN_Pos = 0x3 + // Bit mask of PDM2PCM_CONV_EN field. + I2S_PDM_CONF_PDM2PCM_CONV_EN_Msk = 0x8 + // Bit PDM2PCM_CONV_EN. + I2S_PDM_CONF_PDM2PCM_CONV_EN = 0x8 + // Position of TX_PDM_SINC_OSR2 field. + I2S_PDM_CONF_TX_PDM_SINC_OSR2_Pos = 0x4 + // Bit mask of TX_PDM_SINC_OSR2 field. + I2S_PDM_CONF_TX_PDM_SINC_OSR2_Msk = 0xf0 + // Position of TX_PDM_PRESCALE field. + I2S_PDM_CONF_TX_PDM_PRESCALE_Pos = 0x8 + // Bit mask of TX_PDM_PRESCALE field. + I2S_PDM_CONF_TX_PDM_PRESCALE_Msk = 0xff00 + // Position of TX_PDM_HP_IN_SHIFT field. + I2S_PDM_CONF_TX_PDM_HP_IN_SHIFT_Pos = 0x10 + // Bit mask of TX_PDM_HP_IN_SHIFT field. + I2S_PDM_CONF_TX_PDM_HP_IN_SHIFT_Msk = 0x30000 + // Position of TX_PDM_LP_IN_SHIFT field. + I2S_PDM_CONF_TX_PDM_LP_IN_SHIFT_Pos = 0x12 + // Bit mask of TX_PDM_LP_IN_SHIFT field. + I2S_PDM_CONF_TX_PDM_LP_IN_SHIFT_Msk = 0xc0000 + // Position of TX_PDM_SINC_IN_SHIFT field. + I2S_PDM_CONF_TX_PDM_SINC_IN_SHIFT_Pos = 0x14 + // Bit mask of TX_PDM_SINC_IN_SHIFT field. + I2S_PDM_CONF_TX_PDM_SINC_IN_SHIFT_Msk = 0x300000 + // Position of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Pos = 0x16 + // Bit mask of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Msk = 0xc00000 + // Position of RX_PDM_SINC_DSR_16_EN field. + I2S_PDM_CONF_RX_PDM_SINC_DSR_16_EN_Pos = 0x18 + // Bit mask of RX_PDM_SINC_DSR_16_EN field. + I2S_PDM_CONF_RX_PDM_SINC_DSR_16_EN_Msk = 0x1000000 + // Bit RX_PDM_SINC_DSR_16_EN. + I2S_PDM_CONF_RX_PDM_SINC_DSR_16_EN = 0x1000000 + // Position of TX_PDM_HP_BYPASS field. + I2S_PDM_CONF_TX_PDM_HP_BYPASS_Pos = 0x19 + // Bit mask of TX_PDM_HP_BYPASS field. + I2S_PDM_CONF_TX_PDM_HP_BYPASS_Msk = 0x2000000 + // Bit TX_PDM_HP_BYPASS. + I2S_PDM_CONF_TX_PDM_HP_BYPASS = 0x2000000 + + // PDM_FREQ_CONF + // Position of TX_PDM_FS field. + I2S_PDM_FREQ_CONF_TX_PDM_FS_Pos = 0x0 + // Bit mask of TX_PDM_FS field. + I2S_PDM_FREQ_CONF_TX_PDM_FS_Msk = 0x3ff + // Position of TX_PDM_FP field. + I2S_PDM_FREQ_CONF_TX_PDM_FP_Pos = 0xa + // Bit mask of TX_PDM_FP field. + I2S_PDM_FREQ_CONF_TX_PDM_FP_Msk = 0xffc00 + + // STATE + // Position of TX_IDLE field. + I2S_STATE_TX_IDLE_Pos = 0x0 + // Bit mask of TX_IDLE field. + I2S_STATE_TX_IDLE_Msk = 0x1 + // Bit TX_IDLE. + I2S_STATE_TX_IDLE = 0x1 + // Position of TX_FIFO_RESET_BACK field. + I2S_STATE_TX_FIFO_RESET_BACK_Pos = 0x1 + // Bit mask of TX_FIFO_RESET_BACK field. + I2S_STATE_TX_FIFO_RESET_BACK_Msk = 0x2 + // Bit TX_FIFO_RESET_BACK. + I2S_STATE_TX_FIFO_RESET_BACK = 0x2 + // Position of RX_FIFO_RESET_BACK field. + I2S_STATE_RX_FIFO_RESET_BACK_Pos = 0x2 + // Bit mask of RX_FIFO_RESET_BACK field. + I2S_STATE_RX_FIFO_RESET_BACK_Msk = 0x4 + // Bit RX_FIFO_RESET_BACK. + I2S_STATE_RX_FIFO_RESET_BACK = 0x4 + + // DATE + // Position of I2SDATE field. + I2S_DATE_I2SDATE_Pos = 0x0 + // Bit mask of I2SDATE field. + I2S_DATE_I2SDATE_Msk = 0xffffffff +) + +// Constants for IO_MUX: Input/Output Multiplexer +const ( + // PIN_CTRL + // Position of CLK1 field. + IO_MUX_PIN_CTRL_CLK1_Pos = 0x0 + // Bit mask of CLK1 field. + IO_MUX_PIN_CTRL_CLK1_Msk = 0xf + // Position of CLK2 field. + IO_MUX_PIN_CTRL_CLK2_Pos = 0x4 + // Bit mask of CLK2 field. + IO_MUX_PIN_CTRL_CLK2_Msk = 0xf0 + // Position of CLK3 field. + IO_MUX_PIN_CTRL_CLK3_Pos = 0x8 + // Bit mask of CLK3 field. + IO_MUX_PIN_CTRL_CLK3_Msk = 0xf00 + + // GPIO36 + // Position of MCU_OE field. + IO_MUX_GPIO36_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO36_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO36_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO36_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO36_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO36_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO36_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO36_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO36_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO36_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO36_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO36_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO36_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO36_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO36_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO36_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO36_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO36_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO36_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO36_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO36_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO36_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO36_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO36_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO36_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO36_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO36_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO36_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO36_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO36_MCU_SEL_Msk = 0x7000 + + // GPIO37 + // Position of MCU_OE field. + IO_MUX_GPIO37_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO37_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO37_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO37_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO37_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO37_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO37_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO37_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO37_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO37_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO37_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO37_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO37_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO37_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO37_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO37_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO37_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO37_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO37_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO37_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO37_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO37_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO37_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO37_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO37_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO37_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO37_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO37_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO37_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO37_MCU_SEL_Msk = 0x7000 + + // GPIO38 + // Position of MCU_OE field. + IO_MUX_GPIO38_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO38_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO38_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO38_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO38_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO38_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO38_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO38_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO38_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO38_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO38_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO38_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO38_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO38_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO38_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO38_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO38_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO38_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO38_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO38_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO38_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO38_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO38_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO38_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO38_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO38_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO38_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO38_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO38_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO38_MCU_SEL_Msk = 0x7000 + + // GPIO39 + // Position of MCU_OE field. + IO_MUX_GPIO39_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO39_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO39_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO39_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO39_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO39_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO39_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO39_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO39_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO39_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO39_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO39_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO39_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO39_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO39_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO39_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO39_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO39_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO39_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO39_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO39_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO39_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO39_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO39_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO39_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO39_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO39_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO39_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO39_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO39_MCU_SEL_Msk = 0x7000 + + // GPIO34 + // Position of MCU_OE field. + IO_MUX_GPIO34_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO34_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO34_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO34_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO34_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO34_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO34_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO34_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO34_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO34_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO34_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO34_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO34_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO34_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO34_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO34_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO34_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO34_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO34_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO34_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO34_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO34_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO34_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO34_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO34_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO34_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO34_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO34_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO34_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO34_MCU_SEL_Msk = 0x7000 + + // GPIO35 + // Position of MCU_OE field. + IO_MUX_GPIO35_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO35_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO35_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO35_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO35_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO35_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO35_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO35_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO35_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO35_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO35_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO35_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO35_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO35_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO35_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO35_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO35_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO35_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO35_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO35_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO35_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO35_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO35_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO35_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO35_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO35_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO35_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO35_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO35_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO35_MCU_SEL_Msk = 0x7000 + + // GPIO32 + // Position of MCU_OE field. + IO_MUX_GPIO32_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO32_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO32_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO32_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO32_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO32_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO32_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO32_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO32_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO32_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO32_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO32_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO32_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO32_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO32_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO32_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO32_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO32_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO32_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO32_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO32_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO32_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO32_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO32_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO32_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO32_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO32_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO32_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO32_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO32_MCU_SEL_Msk = 0x7000 + + // GPIO33 + // Position of MCU_OE field. + IO_MUX_GPIO33_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO33_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO33_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO33_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO33_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO33_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO33_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO33_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO33_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO33_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO33_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO33_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO33_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO33_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO33_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO33_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO33_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO33_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO33_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO33_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO33_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO33_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO33_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO33_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO33_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO33_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO33_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO33_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO33_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO33_MCU_SEL_Msk = 0x7000 + + // GPIO25 + // Position of MCU_OE field. + IO_MUX_GPIO25_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO25_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO25_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO25_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO25_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO25_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO25_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO25_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO25_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO25_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO25_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO25_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO25_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO25_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO25_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO25_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO25_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO25_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO25_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO25_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO25_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO25_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO25_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO25_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO25_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO25_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO25_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO25_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO25_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO25_MCU_SEL_Msk = 0x7000 + + // GPIO26 + // Position of MCU_OE field. + IO_MUX_GPIO26_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO26_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO26_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO26_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO26_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO26_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO26_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO26_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO26_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO26_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO26_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO26_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO26_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO26_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO26_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO26_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO26_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO26_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO26_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO26_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO26_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO26_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO26_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO26_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO26_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO26_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO26_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO26_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO26_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO26_MCU_SEL_Msk = 0x7000 + + // GPIO27 + // Position of MCU_OE field. + IO_MUX_GPIO27_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO27_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO27_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO27_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO27_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO27_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO27_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO27_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO27_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO27_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO27_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO27_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO27_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO27_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO27_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO27_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO27_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO27_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO27_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO27_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO27_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO27_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO27_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO27_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO27_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO27_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO27_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO27_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO27_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO27_MCU_SEL_Msk = 0x7000 + + // GPIO14 + // Position of MCU_OE field. + IO_MUX_GPIO14_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO14_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO14_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO14_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO14_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO14_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO14_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO14_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO14_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO14_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO14_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO14_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO14_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO14_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO14_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO14_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO14_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO14_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO14_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO14_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO14_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO14_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO14_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO14_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO14_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO14_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO14_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO14_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO14_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO14_MCU_SEL_Msk = 0x7000 + + // GPIO12 + // Position of MCU_OE field. + IO_MUX_GPIO12_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO12_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO12_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO12_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO12_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO12_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO12_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO12_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO12_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO12_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO12_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO12_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO12_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO12_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO12_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO12_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO12_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO12_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO12_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO12_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO12_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO12_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO12_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO12_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO12_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO12_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO12_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO12_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO12_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO12_MCU_SEL_Msk = 0x7000 + + // GPIO13 + // Position of MCU_OE field. + IO_MUX_GPIO13_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO13_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO13_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO13_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO13_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO13_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO13_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO13_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO13_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO13_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO13_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO13_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO13_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO13_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO13_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO13_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO13_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO13_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO13_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO13_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO13_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO13_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO13_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO13_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO13_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO13_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO13_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO13_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO13_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO13_MCU_SEL_Msk = 0x7000 + + // GPIO15 + // Position of MCU_OE field. + IO_MUX_GPIO15_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO15_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO15_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO15_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO15_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO15_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO15_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO15_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO15_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO15_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO15_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO15_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO15_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO15_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO15_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO15_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO15_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO15_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO15_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO15_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO15_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO15_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO15_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO15_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO15_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO15_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO15_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO15_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO15_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO15_MCU_SEL_Msk = 0x7000 + + // GPIO2 + // Position of MCU_OE field. + IO_MUX_GPIO2_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO2_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO2_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO2_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO2_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO2_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO2_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO2_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO2_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO2_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO2_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO2_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO2_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO2_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO2_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO2_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO2_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO2_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO2_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO2_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO2_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO2_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO2_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO2_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO2_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO2_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO2_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO2_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO2_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO2_MCU_SEL_Msk = 0x7000 + + // GPIO0 + // Position of MCU_OE field. + IO_MUX_GPIO0_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO0_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO0_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO0_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO0_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO0_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO0_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO0_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO0_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO0_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO0_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO0_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO0_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO0_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO0_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO0_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO0_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO0_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO0_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO0_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO0_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO0_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO0_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO0_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO0_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO0_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO0_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO0_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO0_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO0_MCU_SEL_Msk = 0x7000 + + // GPIO4 + // Position of MCU_OE field. + IO_MUX_GPIO4_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO4_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO4_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO4_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO4_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO4_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO4_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO4_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO4_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO4_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO4_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO4_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO4_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO4_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO4_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO4_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO4_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO4_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO4_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO4_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO4_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO4_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO4_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO4_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO4_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO4_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO4_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO4_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO4_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO4_MCU_SEL_Msk = 0x7000 + + // GPIO16 + // Position of MCU_OE field. + IO_MUX_GPIO16_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO16_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO16_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO16_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO16_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO16_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO16_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO16_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO16_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO16_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO16_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO16_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO16_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO16_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO16_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO16_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO16_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO16_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO16_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO16_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO16_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO16_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO16_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO16_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO16_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO16_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO16_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO16_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO16_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO16_MCU_SEL_Msk = 0x7000 + + // GPIO17 + // Position of MCU_OE field. + IO_MUX_GPIO17_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO17_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO17_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO17_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO17_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO17_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO17_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO17_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO17_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO17_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO17_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO17_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO17_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO17_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO17_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO17_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO17_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO17_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO17_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO17_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO17_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO17_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO17_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO17_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO17_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO17_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO17_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO17_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO17_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO17_MCU_SEL_Msk = 0x7000 + + // GPIO9 + // Position of MCU_OE field. + IO_MUX_GPIO9_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO9_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO9_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO9_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO9_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO9_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO9_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO9_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO9_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO9_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO9_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO9_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO9_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO9_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO9_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO9_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO9_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO9_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO9_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO9_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO9_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO9_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO9_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO9_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO9_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO9_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO9_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO9_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO9_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO9_MCU_SEL_Msk = 0x7000 + + // GPIO10 + // Position of MCU_OE field. + IO_MUX_GPIO10_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO10_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO10_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO10_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO10_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO10_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO10_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO10_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO10_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO10_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO10_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO10_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO10_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO10_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO10_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO10_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO10_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO10_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO10_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO10_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO10_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO10_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO10_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO10_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO10_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO10_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO10_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO10_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO10_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO10_MCU_SEL_Msk = 0x7000 + + // GPIO11 + // Position of MCU_OE field. + IO_MUX_GPIO11_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO11_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO11_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO11_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO11_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO11_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO11_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO11_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO11_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO11_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO11_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO11_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO11_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO11_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO11_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO11_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO11_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO11_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO11_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO11_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO11_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO11_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO11_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO11_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO11_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO11_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO11_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO11_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO11_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO11_MCU_SEL_Msk = 0x7000 + + // GPIO6 + // Position of MCU_OE field. + IO_MUX_GPIO6_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO6_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO6_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO6_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO6_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO6_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO6_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO6_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO6_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO6_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO6_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO6_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO6_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO6_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO6_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO6_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO6_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO6_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO6_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO6_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO6_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO6_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO6_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO6_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO6_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO6_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO6_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO6_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO6_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO6_MCU_SEL_Msk = 0x7000 + + // GPIO7 + // Position of MCU_OE field. + IO_MUX_GPIO7_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO7_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO7_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO7_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO7_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO7_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO7_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO7_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO7_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO7_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO7_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO7_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO7_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO7_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO7_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO7_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO7_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO7_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO7_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO7_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO7_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO7_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO7_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO7_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO7_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO7_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO7_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO7_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO7_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO7_MCU_SEL_Msk = 0x7000 + + // GPIO8 + // Position of MCU_OE field. + IO_MUX_GPIO8_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO8_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO8_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO8_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO8_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO8_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO8_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO8_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO8_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO8_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO8_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO8_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO8_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO8_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO8_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO8_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO8_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO8_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO8_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO8_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO8_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO8_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO8_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO8_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO8_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO8_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO8_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO8_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO8_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO8_MCU_SEL_Msk = 0x7000 + + // GPIO5 + // Position of MCU_OE field. + IO_MUX_GPIO5_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO5_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO5_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO5_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO5_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO5_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO5_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO5_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO5_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO5_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO5_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO5_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO5_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO5_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO5_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO5_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO5_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO5_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO5_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO5_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO5_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO5_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO5_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO5_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO5_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO5_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO5_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO5_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO5_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO5_MCU_SEL_Msk = 0x7000 + + // GPIO18 + // Position of MCU_OE field. + IO_MUX_GPIO18_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO18_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO18_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO18_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO18_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO18_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO18_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO18_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO18_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO18_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO18_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO18_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO18_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO18_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO18_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO18_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO18_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO18_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO18_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO18_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO18_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO18_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO18_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO18_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO18_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO18_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO18_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO18_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO18_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO18_MCU_SEL_Msk = 0x7000 + + // GPIO19 + // Position of MCU_OE field. + IO_MUX_GPIO19_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO19_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO19_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO19_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO19_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO19_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO19_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO19_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO19_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO19_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO19_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO19_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO19_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO19_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO19_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO19_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO19_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO19_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO19_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO19_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO19_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO19_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO19_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO19_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO19_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO19_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO19_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO19_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO19_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO19_MCU_SEL_Msk = 0x7000 + + // GPIO20 + // Position of MCU_OE field. + IO_MUX_GPIO20_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO20_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO20_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO20_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO20_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO20_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO20_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO20_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO20_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO20_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO20_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO20_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO20_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO20_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO20_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO20_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO20_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO20_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO20_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO20_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO20_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO20_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO20_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO20_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO20_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO20_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO20_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO20_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO20_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO20_MCU_SEL_Msk = 0x7000 + + // GPIO21 + // Position of MCU_OE field. + IO_MUX_GPIO21_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO21_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO21_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO21_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO21_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO21_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO21_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO21_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO21_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO21_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO21_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO21_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO21_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO21_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO21_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO21_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO21_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO21_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO21_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO21_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO21_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO21_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO21_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO21_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO21_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO21_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO21_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO21_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO21_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO21_MCU_SEL_Msk = 0x7000 + + // GPIO22 + // Position of MCU_OE field. + IO_MUX_GPIO22_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO22_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO22_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO22_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO22_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO22_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO22_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO22_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO22_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO22_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO22_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO22_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO22_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO22_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO22_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO22_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO22_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO22_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO22_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO22_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO22_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO22_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO22_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO22_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO22_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO22_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO22_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO22_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO22_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO22_MCU_SEL_Msk = 0x7000 + + // GPIO3 + // Position of MCU_OE field. + IO_MUX_GPIO3_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO3_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO3_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO3_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO3_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO3_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO3_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO3_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO3_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO3_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO3_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO3_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO3_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO3_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO3_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO3_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO3_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO3_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO3_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO3_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO3_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO3_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO3_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO3_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO3_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO3_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO3_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO3_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO3_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO3_MCU_SEL_Msk = 0x7000 + + // GPIO1 + // Position of MCU_OE field. + IO_MUX_GPIO1_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO1_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO1_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO1_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO1_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO1_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO1_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO1_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO1_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO1_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO1_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO1_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO1_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO1_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO1_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO1_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO1_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO1_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO1_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO1_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO1_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO1_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO1_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO1_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO1_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO1_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO1_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO1_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO1_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO1_MCU_SEL_Msk = 0x7000 + + // GPIO23 + // Position of MCU_OE field. + IO_MUX_GPIO23_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO23_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO23_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO23_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO23_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO23_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO23_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO23_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO23_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO23_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO23_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO23_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO23_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO23_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO23_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO23_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO23_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO23_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO23_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO23_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO23_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO23_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO23_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO23_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO23_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO23_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO23_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO23_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO23_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO23_MCU_SEL_Msk = 0x7000 + + // GPIO24 + // Position of MCU_OE field. + IO_MUX_GPIO24_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO24_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO24_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO24_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO24_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO24_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO24_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO24_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO24_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO24_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO24_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO24_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO24_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO24_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO24_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO24_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO24_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO24_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO24_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO24_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO24_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO24_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO24_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO24_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO24_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO24_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO24_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO24_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO24_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO24_MCU_SEL_Msk = 0x7000 +) + +// Constants for LEDC: LED Control PWM (Pulse Width Modulation) +const ( + // HSCH0_CONF0 + // Position of TIMER_SEL field. + LEDC_HSCH_CONF0_TIMER_SEL_Pos = 0x0 + // Bit mask of TIMER_SEL field. + LEDC_HSCH_CONF0_TIMER_SEL_Msk = 0x3 + // Position of SIG_OUT_EN field. + LEDC_HSCH_CONF0_SIG_OUT_EN_Pos = 0x2 + // Bit mask of SIG_OUT_EN field. + LEDC_HSCH_CONF0_SIG_OUT_EN_Msk = 0x4 + // Bit SIG_OUT_EN. + LEDC_HSCH_CONF0_SIG_OUT_EN = 0x4 + // Position of IDLE_LV field. + LEDC_HSCH_CONF0_IDLE_LV_Pos = 0x3 + // Bit mask of IDLE_LV field. + LEDC_HSCH_CONF0_IDLE_LV_Msk = 0x8 + // Bit IDLE_LV. + LEDC_HSCH_CONF0_IDLE_LV = 0x8 + + // HSCH0_HPOINT + // Position of HPOINT field. + LEDC_HSCH_HPOINT_HPOINT_Pos = 0x0 + // Bit mask of HPOINT field. + LEDC_HSCH_HPOINT_HPOINT_Msk = 0xfffff + + // HSCH0_DUTY + // Position of DUTY field. + LEDC_HSCH_DUTY_DUTY_Pos = 0x0 + // Bit mask of DUTY field. + LEDC_HSCH_DUTY_DUTY_Msk = 0x1ffffff + + // HSCH0_CONF1 + // Position of DUTY_SCALE field. + LEDC_HSCH_CONF1_DUTY_SCALE_Pos = 0x0 + // Bit mask of DUTY_SCALE field. + LEDC_HSCH_CONF1_DUTY_SCALE_Msk = 0x3ff + // Position of DUTY_CYCLE field. + LEDC_HSCH_CONF1_DUTY_CYCLE_Pos = 0xa + // Bit mask of DUTY_CYCLE field. + LEDC_HSCH_CONF1_DUTY_CYCLE_Msk = 0xffc00 + // Position of DUTY_NUM field. + LEDC_HSCH_CONF1_DUTY_NUM_Pos = 0x14 + // Bit mask of DUTY_NUM field. + LEDC_HSCH_CONF1_DUTY_NUM_Msk = 0x3ff00000 + // Position of DUTY_INC field. + LEDC_HSCH_CONF1_DUTY_INC_Pos = 0x1e + // Bit mask of DUTY_INC field. + LEDC_HSCH_CONF1_DUTY_INC_Msk = 0x40000000 + // Bit DUTY_INC. + LEDC_HSCH_CONF1_DUTY_INC = 0x40000000 + // Position of DUTY_START field. + LEDC_HSCH_CONF1_DUTY_START_Pos = 0x1f + // Bit mask of DUTY_START field. + LEDC_HSCH_CONF1_DUTY_START_Msk = 0x80000000 + // Bit DUTY_START. + LEDC_HSCH_CONF1_DUTY_START = 0x80000000 + + // HSCH0_DUTY_R + // Position of DUTY_R field. + LEDC_HSCH_DUTY_R_DUTY_R_Pos = 0x0 + // Bit mask of DUTY_R field. + LEDC_HSCH_DUTY_R_DUTY_R_Msk = 0x1ffffff + + // LSCH0_CONF0 + // Position of TIMER_SEL field. + LEDC_LSCH_CONF0_TIMER_SEL_Pos = 0x0 + // Bit mask of TIMER_SEL field. + LEDC_LSCH_CONF0_TIMER_SEL_Msk = 0x3 + // Position of SIG_OUT_EN field. + LEDC_LSCH_CONF0_SIG_OUT_EN_Pos = 0x2 + // Bit mask of SIG_OUT_EN field. + LEDC_LSCH_CONF0_SIG_OUT_EN_Msk = 0x4 + // Bit SIG_OUT_EN. + LEDC_LSCH_CONF0_SIG_OUT_EN = 0x4 + // Position of IDLE_LV field. + LEDC_LSCH_CONF0_IDLE_LV_Pos = 0x3 + // Bit mask of IDLE_LV field. + LEDC_LSCH_CONF0_IDLE_LV_Msk = 0x8 + // Bit IDLE_LV. + LEDC_LSCH_CONF0_IDLE_LV = 0x8 + // Position of PARA_UP field. + LEDC_LSCH_CONF0_PARA_UP_Pos = 0x4 + // Bit mask of PARA_UP field. + LEDC_LSCH_CONF0_PARA_UP_Msk = 0x10 + // Bit PARA_UP. + LEDC_LSCH_CONF0_PARA_UP = 0x10 + + // LSCH0_HPOINT + // Position of HPOINT field. + LEDC_LSCH_HPOINT_HPOINT_Pos = 0x0 + // Bit mask of HPOINT field. + LEDC_LSCH_HPOINT_HPOINT_Msk = 0xfffff + + // LSCH0_DUTY + // Position of DUTY field. + LEDC_LSCH_DUTY_DUTY_Pos = 0x0 + // Bit mask of DUTY field. + LEDC_LSCH_DUTY_DUTY_Msk = 0x1ffffff + + // LSCH0_CONF1 + // Position of DUTY_SCALE field. + LEDC_LSCH_CONF1_DUTY_SCALE_Pos = 0x0 + // Bit mask of DUTY_SCALE field. + LEDC_LSCH_CONF1_DUTY_SCALE_Msk = 0x3ff + // Position of DUTY_CYCLE field. + LEDC_LSCH_CONF1_DUTY_CYCLE_Pos = 0xa + // Bit mask of DUTY_CYCLE field. + LEDC_LSCH_CONF1_DUTY_CYCLE_Msk = 0xffc00 + // Position of DUTY_NUM field. + LEDC_LSCH_CONF1_DUTY_NUM_Pos = 0x14 + // Bit mask of DUTY_NUM field. + LEDC_LSCH_CONF1_DUTY_NUM_Msk = 0x3ff00000 + // Position of DUTY_INC field. + LEDC_LSCH_CONF1_DUTY_INC_Pos = 0x1e + // Bit mask of DUTY_INC field. + LEDC_LSCH_CONF1_DUTY_INC_Msk = 0x40000000 + // Bit DUTY_INC. + LEDC_LSCH_CONF1_DUTY_INC = 0x40000000 + // Position of DUTY_START field. + LEDC_LSCH_CONF1_DUTY_START_Pos = 0x1f + // Bit mask of DUTY_START field. + LEDC_LSCH_CONF1_DUTY_START_Msk = 0x80000000 + // Bit DUTY_START. + LEDC_LSCH_CONF1_DUTY_START = 0x80000000 + + // LSCH0_DUTY_R + // Position of DUTY_R field. + LEDC_LSCH_DUTY_R_DUTY_R_Pos = 0x0 + // Bit mask of DUTY_R field. + LEDC_LSCH_DUTY_R_DUTY_R_Msk = 0x1ffffff + + // HSTIMER0_CONF + // Position of DUTY_RES field. + LEDC_HSTIMER_CONF_DUTY_RES_Pos = 0x0 + // Bit mask of DUTY_RES field. + LEDC_HSTIMER_CONF_DUTY_RES_Msk = 0x1f + // Position of DIV_NUM field. + LEDC_HSTIMER_CONF_DIV_NUM_Pos = 0x5 + // Bit mask of DIV_NUM field. + LEDC_HSTIMER_CONF_DIV_NUM_Msk = 0x7fffe0 + // Position of PAUSE field. + LEDC_HSTIMER_CONF_PAUSE_Pos = 0x17 + // Bit mask of PAUSE field. + LEDC_HSTIMER_CONF_PAUSE_Msk = 0x800000 + // Bit PAUSE. + LEDC_HSTIMER_CONF_PAUSE = 0x800000 + // Position of RST field. + LEDC_HSTIMER_CONF_RST_Pos = 0x18 + // Bit mask of RST field. + LEDC_HSTIMER_CONF_RST_Msk = 0x1000000 + // Bit RST. + LEDC_HSTIMER_CONF_RST = 0x1000000 + // Position of TICK_SEL field. + LEDC_HSTIMER_CONF_TICK_SEL_Pos = 0x19 + // Bit mask of TICK_SEL field. + LEDC_HSTIMER_CONF_TICK_SEL_Msk = 0x2000000 + // Bit TICK_SEL. + LEDC_HSTIMER_CONF_TICK_SEL = 0x2000000 + + // HSTIMER0_VALUE + // Position of CNT field. + LEDC_HSTIMER_VALUE_CNT_Pos = 0x0 + // Bit mask of CNT field. + LEDC_HSTIMER_VALUE_CNT_Msk = 0xfffff + + // LSTIMER0_CONF + // Position of DUTY_RES field. + LEDC_LSTIMER_CONF_DUTY_RES_Pos = 0x0 + // Bit mask of DUTY_RES field. + LEDC_LSTIMER_CONF_DUTY_RES_Msk = 0x1f + // Position of DIV_NUM field. + LEDC_LSTIMER_CONF_DIV_NUM_Pos = 0x5 + // Bit mask of DIV_NUM field. + LEDC_LSTIMER_CONF_DIV_NUM_Msk = 0x7fffe0 + // Position of PAUSE field. + LEDC_LSTIMER_CONF_PAUSE_Pos = 0x17 + // Bit mask of PAUSE field. + LEDC_LSTIMER_CONF_PAUSE_Msk = 0x800000 + // Bit PAUSE. + LEDC_LSTIMER_CONF_PAUSE = 0x800000 + // Position of RST field. + LEDC_LSTIMER_CONF_RST_Pos = 0x18 + // Bit mask of RST field. + LEDC_LSTIMER_CONF_RST_Msk = 0x1000000 + // Bit RST. + LEDC_LSTIMER_CONF_RST = 0x1000000 + // Position of TICK_SEL field. + LEDC_LSTIMER_CONF_TICK_SEL_Pos = 0x19 + // Bit mask of TICK_SEL field. + LEDC_LSTIMER_CONF_TICK_SEL_Msk = 0x2000000 + // Bit TICK_SEL. + LEDC_LSTIMER_CONF_TICK_SEL = 0x2000000 + // Position of PARA_UP field. + LEDC_LSTIMER_CONF_PARA_UP_Pos = 0x1a + // Bit mask of PARA_UP field. + LEDC_LSTIMER_CONF_PARA_UP_Msk = 0x4000000 + // Bit PARA_UP. + LEDC_LSTIMER_CONF_PARA_UP = 0x4000000 + + // LSTIMER0_VALUE + // Position of CNT field. + LEDC_LSTIMER_VALUE_CNT_Pos = 0x0 + // Bit mask of CNT field. + LEDC_LSTIMER_VALUE_CNT_Msk = 0xfffff + + // INT_RAW + // Position of HSTIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_HSTIMER0_OVF_INT_RAW_Pos = 0x0 + // Bit mask of HSTIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_HSTIMER0_OVF_INT_RAW_Msk = 0x1 + // Bit HSTIMER0_OVF_INT_RAW. + LEDC_INT_RAW_HSTIMER0_OVF_INT_RAW = 0x1 + // Position of HSTIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_HSTIMER1_OVF_INT_RAW_Pos = 0x1 + // Bit mask of HSTIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_HSTIMER1_OVF_INT_RAW_Msk = 0x2 + // Bit HSTIMER1_OVF_INT_RAW. + LEDC_INT_RAW_HSTIMER1_OVF_INT_RAW = 0x2 + // Position of HSTIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_HSTIMER2_OVF_INT_RAW_Pos = 0x2 + // Bit mask of HSTIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_HSTIMER2_OVF_INT_RAW_Msk = 0x4 + // Bit HSTIMER2_OVF_INT_RAW. + LEDC_INT_RAW_HSTIMER2_OVF_INT_RAW = 0x4 + // Position of HSTIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_HSTIMER3_OVF_INT_RAW_Pos = 0x3 + // Bit mask of HSTIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_HSTIMER3_OVF_INT_RAW_Msk = 0x8 + // Bit HSTIMER3_OVF_INT_RAW. + LEDC_INT_RAW_HSTIMER3_OVF_INT_RAW = 0x8 + // Position of LSTIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER0_OVF_INT_RAW_Pos = 0x4 + // Bit mask of LSTIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER0_OVF_INT_RAW_Msk = 0x10 + // Bit LSTIMER0_OVF_INT_RAW. + LEDC_INT_RAW_LSTIMER0_OVF_INT_RAW = 0x10 + // Position of LSTIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER1_OVF_INT_RAW_Pos = 0x5 + // Bit mask of LSTIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER1_OVF_INT_RAW_Msk = 0x20 + // Bit LSTIMER1_OVF_INT_RAW. + LEDC_INT_RAW_LSTIMER1_OVF_INT_RAW = 0x20 + // Position of LSTIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER2_OVF_INT_RAW_Pos = 0x6 + // Bit mask of LSTIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER2_OVF_INT_RAW_Msk = 0x40 + // Bit LSTIMER2_OVF_INT_RAW. + LEDC_INT_RAW_LSTIMER2_OVF_INT_RAW = 0x40 + // Position of LSTIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER3_OVF_INT_RAW_Pos = 0x7 + // Bit mask of LSTIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER3_OVF_INT_RAW_Msk = 0x80 + // Bit LSTIMER3_OVF_INT_RAW. + LEDC_INT_RAW_LSTIMER3_OVF_INT_RAW = 0x80 + // Position of DUTY_CHNG_END_HSCH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH0_INT_RAW_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_HSCH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH0_INT_RAW_Msk = 0x100 + // Bit DUTY_CHNG_END_HSCH0_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH0_INT_RAW = 0x100 + // Position of DUTY_CHNG_END_HSCH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH1_INT_RAW_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_HSCH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH1_INT_RAW_Msk = 0x200 + // Bit DUTY_CHNG_END_HSCH1_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH1_INT_RAW = 0x200 + // Position of DUTY_CHNG_END_HSCH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH2_INT_RAW_Pos = 0xa + // Bit mask of DUTY_CHNG_END_HSCH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH2_INT_RAW_Msk = 0x400 + // Bit DUTY_CHNG_END_HSCH2_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH2_INT_RAW = 0x400 + // Position of DUTY_CHNG_END_HSCH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH3_INT_RAW_Pos = 0xb + // Bit mask of DUTY_CHNG_END_HSCH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH3_INT_RAW_Msk = 0x800 + // Bit DUTY_CHNG_END_HSCH3_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH3_INT_RAW = 0x800 + // Position of DUTY_CHNG_END_HSCH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH4_INT_RAW_Pos = 0xc + // Bit mask of DUTY_CHNG_END_HSCH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH4_INT_RAW_Msk = 0x1000 + // Bit DUTY_CHNG_END_HSCH4_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH4_INT_RAW = 0x1000 + // Position of DUTY_CHNG_END_HSCH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH5_INT_RAW_Pos = 0xd + // Bit mask of DUTY_CHNG_END_HSCH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH5_INT_RAW_Msk = 0x2000 + // Bit DUTY_CHNG_END_HSCH5_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH5_INT_RAW = 0x2000 + // Position of DUTY_CHNG_END_HSCH6_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH6_INT_RAW_Pos = 0xe + // Bit mask of DUTY_CHNG_END_HSCH6_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH6_INT_RAW_Msk = 0x4000 + // Bit DUTY_CHNG_END_HSCH6_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH6_INT_RAW = 0x4000 + // Position of DUTY_CHNG_END_HSCH7_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH7_INT_RAW_Pos = 0xf + // Bit mask of DUTY_CHNG_END_HSCH7_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH7_INT_RAW_Msk = 0x8000 + // Bit DUTY_CHNG_END_HSCH7_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_HSCH7_INT_RAW = 0x8000 + // Position of DUTY_CHNG_END_LSCH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW_Pos = 0x10 + // Bit mask of DUTY_CHNG_END_LSCH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW_Msk = 0x10000 + // Bit DUTY_CHNG_END_LSCH0_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW = 0x10000 + // Position of DUTY_CHNG_END_LSCH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW_Pos = 0x11 + // Bit mask of DUTY_CHNG_END_LSCH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW_Msk = 0x20000 + // Bit DUTY_CHNG_END_LSCH1_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW = 0x20000 + // Position of DUTY_CHNG_END_LSCH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW_Pos = 0x12 + // Bit mask of DUTY_CHNG_END_LSCH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW_Msk = 0x40000 + // Bit DUTY_CHNG_END_LSCH2_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW = 0x40000 + // Position of DUTY_CHNG_END_LSCH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW_Pos = 0x13 + // Bit mask of DUTY_CHNG_END_LSCH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW_Msk = 0x80000 + // Bit DUTY_CHNG_END_LSCH3_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW = 0x80000 + // Position of DUTY_CHNG_END_LSCH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW_Pos = 0x14 + // Bit mask of DUTY_CHNG_END_LSCH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW_Msk = 0x100000 + // Bit DUTY_CHNG_END_LSCH4_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW = 0x100000 + // Position of DUTY_CHNG_END_LSCH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW_Pos = 0x15 + // Bit mask of DUTY_CHNG_END_LSCH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW_Msk = 0x200000 + // Bit DUTY_CHNG_END_LSCH5_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW = 0x200000 + // Position of DUTY_CHNG_END_LSCH6_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH6_INT_RAW_Pos = 0x16 + // Bit mask of DUTY_CHNG_END_LSCH6_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH6_INT_RAW_Msk = 0x400000 + // Bit DUTY_CHNG_END_LSCH6_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH6_INT_RAW = 0x400000 + // Position of DUTY_CHNG_END_LSCH7_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH7_INT_RAW_Pos = 0x17 + // Bit mask of DUTY_CHNG_END_LSCH7_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH7_INT_RAW_Msk = 0x800000 + // Bit DUTY_CHNG_END_LSCH7_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH7_INT_RAW = 0x800000 + + // INT_ST + // Position of HSTIMER0_OVF_INT_ST field. + LEDC_INT_ST_HSTIMER0_OVF_INT_ST_Pos = 0x0 + // Bit mask of HSTIMER0_OVF_INT_ST field. + LEDC_INT_ST_HSTIMER0_OVF_INT_ST_Msk = 0x1 + // Bit HSTIMER0_OVF_INT_ST. + LEDC_INT_ST_HSTIMER0_OVF_INT_ST = 0x1 + // Position of HSTIMER1_OVF_INT_ST field. + LEDC_INT_ST_HSTIMER1_OVF_INT_ST_Pos = 0x1 + // Bit mask of HSTIMER1_OVF_INT_ST field. + LEDC_INT_ST_HSTIMER1_OVF_INT_ST_Msk = 0x2 + // Bit HSTIMER1_OVF_INT_ST. + LEDC_INT_ST_HSTIMER1_OVF_INT_ST = 0x2 + // Position of HSTIMER2_OVF_INT_ST field. + LEDC_INT_ST_HSTIMER2_OVF_INT_ST_Pos = 0x2 + // Bit mask of HSTIMER2_OVF_INT_ST field. + LEDC_INT_ST_HSTIMER2_OVF_INT_ST_Msk = 0x4 + // Bit HSTIMER2_OVF_INT_ST. + LEDC_INT_ST_HSTIMER2_OVF_INT_ST = 0x4 + // Position of HSTIMER3_OVF_INT_ST field. + LEDC_INT_ST_HSTIMER3_OVF_INT_ST_Pos = 0x3 + // Bit mask of HSTIMER3_OVF_INT_ST field. + LEDC_INT_ST_HSTIMER3_OVF_INT_ST_Msk = 0x8 + // Bit HSTIMER3_OVF_INT_ST. + LEDC_INT_ST_HSTIMER3_OVF_INT_ST = 0x8 + // Position of LSTIMER0_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER0_OVF_INT_ST_Pos = 0x4 + // Bit mask of LSTIMER0_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER0_OVF_INT_ST_Msk = 0x10 + // Bit LSTIMER0_OVF_INT_ST. + LEDC_INT_ST_LSTIMER0_OVF_INT_ST = 0x10 + // Position of LSTIMER1_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER1_OVF_INT_ST_Pos = 0x5 + // Bit mask of LSTIMER1_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER1_OVF_INT_ST_Msk = 0x20 + // Bit LSTIMER1_OVF_INT_ST. + LEDC_INT_ST_LSTIMER1_OVF_INT_ST = 0x20 + // Position of LSTIMER2_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER2_OVF_INT_ST_Pos = 0x6 + // Bit mask of LSTIMER2_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER2_OVF_INT_ST_Msk = 0x40 + // Bit LSTIMER2_OVF_INT_ST. + LEDC_INT_ST_LSTIMER2_OVF_INT_ST = 0x40 + // Position of LSTIMER3_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER3_OVF_INT_ST_Pos = 0x7 + // Bit mask of LSTIMER3_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER3_OVF_INT_ST_Msk = 0x80 + // Bit LSTIMER3_OVF_INT_ST. + LEDC_INT_ST_LSTIMER3_OVF_INT_ST = 0x80 + // Position of DUTY_CHNG_END_HSCH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH0_INT_ST_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_HSCH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH0_INT_ST_Msk = 0x100 + // Bit DUTY_CHNG_END_HSCH0_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_HSCH0_INT_ST = 0x100 + // Position of DUTY_CHNG_END_HSCH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH1_INT_ST_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_HSCH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH1_INT_ST_Msk = 0x200 + // Bit DUTY_CHNG_END_HSCH1_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_HSCH1_INT_ST = 0x200 + // Position of DUTY_CHNG_END_HSCH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH2_INT_ST_Pos = 0xa + // Bit mask of DUTY_CHNG_END_HSCH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH2_INT_ST_Msk = 0x400 + // Bit DUTY_CHNG_END_HSCH2_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_HSCH2_INT_ST = 0x400 + // Position of DUTY_CHNG_END_HSCH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH3_INT_ST_Pos = 0xb + // Bit mask of DUTY_CHNG_END_HSCH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH3_INT_ST_Msk = 0x800 + // Bit DUTY_CHNG_END_HSCH3_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_HSCH3_INT_ST = 0x800 + // Position of DUTY_CHNG_END_HSCH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH4_INT_ST_Pos = 0xc + // Bit mask of DUTY_CHNG_END_HSCH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH4_INT_ST_Msk = 0x1000 + // Bit DUTY_CHNG_END_HSCH4_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_HSCH4_INT_ST = 0x1000 + // Position of DUTY_CHNG_END_HSCH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH5_INT_ST_Pos = 0xd + // Bit mask of DUTY_CHNG_END_HSCH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH5_INT_ST_Msk = 0x2000 + // Bit DUTY_CHNG_END_HSCH5_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_HSCH5_INT_ST = 0x2000 + // Position of DUTY_CHNG_END_HSCH6_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH6_INT_ST_Pos = 0xe + // Bit mask of DUTY_CHNG_END_HSCH6_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH6_INT_ST_Msk = 0x4000 + // Bit DUTY_CHNG_END_HSCH6_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_HSCH6_INT_ST = 0x4000 + // Position of DUTY_CHNG_END_HSCH7_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH7_INT_ST_Pos = 0xf + // Bit mask of DUTY_CHNG_END_HSCH7_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_HSCH7_INT_ST_Msk = 0x8000 + // Bit DUTY_CHNG_END_HSCH7_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_HSCH7_INT_ST = 0x8000 + // Position of DUTY_CHNG_END_LSCH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH0_INT_ST_Pos = 0x10 + // Bit mask of DUTY_CHNG_END_LSCH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH0_INT_ST_Msk = 0x10000 + // Bit DUTY_CHNG_END_LSCH0_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH0_INT_ST = 0x10000 + // Position of DUTY_CHNG_END_LSCH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH1_INT_ST_Pos = 0x11 + // Bit mask of DUTY_CHNG_END_LSCH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH1_INT_ST_Msk = 0x20000 + // Bit DUTY_CHNG_END_LSCH1_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH1_INT_ST = 0x20000 + // Position of DUTY_CHNG_END_LSCH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH2_INT_ST_Pos = 0x12 + // Bit mask of DUTY_CHNG_END_LSCH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH2_INT_ST_Msk = 0x40000 + // Bit DUTY_CHNG_END_LSCH2_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH2_INT_ST = 0x40000 + // Position of DUTY_CHNG_END_LSCH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH3_INT_ST_Pos = 0x13 + // Bit mask of DUTY_CHNG_END_LSCH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH3_INT_ST_Msk = 0x80000 + // Bit DUTY_CHNG_END_LSCH3_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH3_INT_ST = 0x80000 + // Position of DUTY_CHNG_END_LSCH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH4_INT_ST_Pos = 0x14 + // Bit mask of DUTY_CHNG_END_LSCH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH4_INT_ST_Msk = 0x100000 + // Bit DUTY_CHNG_END_LSCH4_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH4_INT_ST = 0x100000 + // Position of DUTY_CHNG_END_LSCH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH5_INT_ST_Pos = 0x15 + // Bit mask of DUTY_CHNG_END_LSCH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH5_INT_ST_Msk = 0x200000 + // Bit DUTY_CHNG_END_LSCH5_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH5_INT_ST = 0x200000 + // Position of DUTY_CHNG_END_LSCH6_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH6_INT_ST_Pos = 0x16 + // Bit mask of DUTY_CHNG_END_LSCH6_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH6_INT_ST_Msk = 0x400000 + // Bit DUTY_CHNG_END_LSCH6_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH6_INT_ST = 0x400000 + // Position of DUTY_CHNG_END_LSCH7_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH7_INT_ST_Pos = 0x17 + // Bit mask of DUTY_CHNG_END_LSCH7_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH7_INT_ST_Msk = 0x800000 + // Bit DUTY_CHNG_END_LSCH7_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH7_INT_ST = 0x800000 + + // INT_ENA + // Position of HSTIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_HSTIMER0_OVF_INT_ENA_Pos = 0x0 + // Bit mask of HSTIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_HSTIMER0_OVF_INT_ENA_Msk = 0x1 + // Bit HSTIMER0_OVF_INT_ENA. + LEDC_INT_ENA_HSTIMER0_OVF_INT_ENA = 0x1 + // Position of HSTIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_HSTIMER1_OVF_INT_ENA_Pos = 0x1 + // Bit mask of HSTIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_HSTIMER1_OVF_INT_ENA_Msk = 0x2 + // Bit HSTIMER1_OVF_INT_ENA. + LEDC_INT_ENA_HSTIMER1_OVF_INT_ENA = 0x2 + // Position of HSTIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_HSTIMER2_OVF_INT_ENA_Pos = 0x2 + // Bit mask of HSTIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_HSTIMER2_OVF_INT_ENA_Msk = 0x4 + // Bit HSTIMER2_OVF_INT_ENA. + LEDC_INT_ENA_HSTIMER2_OVF_INT_ENA = 0x4 + // Position of HSTIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_HSTIMER3_OVF_INT_ENA_Pos = 0x3 + // Bit mask of HSTIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_HSTIMER3_OVF_INT_ENA_Msk = 0x8 + // Bit HSTIMER3_OVF_INT_ENA. + LEDC_INT_ENA_HSTIMER3_OVF_INT_ENA = 0x8 + // Position of LSTIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER0_OVF_INT_ENA_Pos = 0x4 + // Bit mask of LSTIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER0_OVF_INT_ENA_Msk = 0x10 + // Bit LSTIMER0_OVF_INT_ENA. + LEDC_INT_ENA_LSTIMER0_OVF_INT_ENA = 0x10 + // Position of LSTIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER1_OVF_INT_ENA_Pos = 0x5 + // Bit mask of LSTIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER1_OVF_INT_ENA_Msk = 0x20 + // Bit LSTIMER1_OVF_INT_ENA. + LEDC_INT_ENA_LSTIMER1_OVF_INT_ENA = 0x20 + // Position of LSTIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER2_OVF_INT_ENA_Pos = 0x6 + // Bit mask of LSTIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER2_OVF_INT_ENA_Msk = 0x40 + // Bit LSTIMER2_OVF_INT_ENA. + LEDC_INT_ENA_LSTIMER2_OVF_INT_ENA = 0x40 + // Position of LSTIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER3_OVF_INT_ENA_Pos = 0x7 + // Bit mask of LSTIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER3_OVF_INT_ENA_Msk = 0x80 + // Bit LSTIMER3_OVF_INT_ENA. + LEDC_INT_ENA_LSTIMER3_OVF_INT_ENA = 0x80 + // Position of DUTY_CHNG_END_HSCH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH0_INT_ENA_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_HSCH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH0_INT_ENA_Msk = 0x100 + // Bit DUTY_CHNG_END_HSCH0_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH0_INT_ENA = 0x100 + // Position of DUTY_CHNG_END_HSCH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH1_INT_ENA_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_HSCH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH1_INT_ENA_Msk = 0x200 + // Bit DUTY_CHNG_END_HSCH1_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH1_INT_ENA = 0x200 + // Position of DUTY_CHNG_END_HSCH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH2_INT_ENA_Pos = 0xa + // Bit mask of DUTY_CHNG_END_HSCH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH2_INT_ENA_Msk = 0x400 + // Bit DUTY_CHNG_END_HSCH2_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH2_INT_ENA = 0x400 + // Position of DUTY_CHNG_END_HSCH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH3_INT_ENA_Pos = 0xb + // Bit mask of DUTY_CHNG_END_HSCH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH3_INT_ENA_Msk = 0x800 + // Bit DUTY_CHNG_END_HSCH3_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH3_INT_ENA = 0x800 + // Position of DUTY_CHNG_END_HSCH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH4_INT_ENA_Pos = 0xc + // Bit mask of DUTY_CHNG_END_HSCH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH4_INT_ENA_Msk = 0x1000 + // Bit DUTY_CHNG_END_HSCH4_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH4_INT_ENA = 0x1000 + // Position of DUTY_CHNG_END_HSCH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH5_INT_ENA_Pos = 0xd + // Bit mask of DUTY_CHNG_END_HSCH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH5_INT_ENA_Msk = 0x2000 + // Bit DUTY_CHNG_END_HSCH5_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH5_INT_ENA = 0x2000 + // Position of DUTY_CHNG_END_HSCH6_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH6_INT_ENA_Pos = 0xe + // Bit mask of DUTY_CHNG_END_HSCH6_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH6_INT_ENA_Msk = 0x4000 + // Bit DUTY_CHNG_END_HSCH6_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH6_INT_ENA = 0x4000 + // Position of DUTY_CHNG_END_HSCH7_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH7_INT_ENA_Pos = 0xf + // Bit mask of DUTY_CHNG_END_HSCH7_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH7_INT_ENA_Msk = 0x8000 + // Bit DUTY_CHNG_END_HSCH7_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_HSCH7_INT_ENA = 0x8000 + // Position of DUTY_CHNG_END_LSCH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA_Pos = 0x10 + // Bit mask of DUTY_CHNG_END_LSCH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA_Msk = 0x10000 + // Bit DUTY_CHNG_END_LSCH0_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA = 0x10000 + // Position of DUTY_CHNG_END_LSCH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA_Pos = 0x11 + // Bit mask of DUTY_CHNG_END_LSCH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA_Msk = 0x20000 + // Bit DUTY_CHNG_END_LSCH1_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA = 0x20000 + // Position of DUTY_CHNG_END_LSCH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA_Pos = 0x12 + // Bit mask of DUTY_CHNG_END_LSCH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA_Msk = 0x40000 + // Bit DUTY_CHNG_END_LSCH2_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA = 0x40000 + // Position of DUTY_CHNG_END_LSCH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA_Pos = 0x13 + // Bit mask of DUTY_CHNG_END_LSCH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA_Msk = 0x80000 + // Bit DUTY_CHNG_END_LSCH3_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA = 0x80000 + // Position of DUTY_CHNG_END_LSCH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA_Pos = 0x14 + // Bit mask of DUTY_CHNG_END_LSCH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA_Msk = 0x100000 + // Bit DUTY_CHNG_END_LSCH4_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA = 0x100000 + // Position of DUTY_CHNG_END_LSCH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA_Pos = 0x15 + // Bit mask of DUTY_CHNG_END_LSCH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA_Msk = 0x200000 + // Bit DUTY_CHNG_END_LSCH5_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA = 0x200000 + // Position of DUTY_CHNG_END_LSCH6_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH6_INT_ENA_Pos = 0x16 + // Bit mask of DUTY_CHNG_END_LSCH6_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH6_INT_ENA_Msk = 0x400000 + // Bit DUTY_CHNG_END_LSCH6_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH6_INT_ENA = 0x400000 + // Position of DUTY_CHNG_END_LSCH7_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH7_INT_ENA_Pos = 0x17 + // Bit mask of DUTY_CHNG_END_LSCH7_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH7_INT_ENA_Msk = 0x800000 + // Bit DUTY_CHNG_END_LSCH7_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH7_INT_ENA = 0x800000 + + // INT_CLR + // Position of HSTIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_HSTIMER0_OVF_INT_CLR_Pos = 0x0 + // Bit mask of HSTIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_HSTIMER0_OVF_INT_CLR_Msk = 0x1 + // Bit HSTIMER0_OVF_INT_CLR. + LEDC_INT_CLR_HSTIMER0_OVF_INT_CLR = 0x1 + // Position of HSTIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_HSTIMER1_OVF_INT_CLR_Pos = 0x1 + // Bit mask of HSTIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_HSTIMER1_OVF_INT_CLR_Msk = 0x2 + // Bit HSTIMER1_OVF_INT_CLR. + LEDC_INT_CLR_HSTIMER1_OVF_INT_CLR = 0x2 + // Position of HSTIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_HSTIMER2_OVF_INT_CLR_Pos = 0x2 + // Bit mask of HSTIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_HSTIMER2_OVF_INT_CLR_Msk = 0x4 + // Bit HSTIMER2_OVF_INT_CLR. + LEDC_INT_CLR_HSTIMER2_OVF_INT_CLR = 0x4 + // Position of HSTIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_HSTIMER3_OVF_INT_CLR_Pos = 0x3 + // Bit mask of HSTIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_HSTIMER3_OVF_INT_CLR_Msk = 0x8 + // Bit HSTIMER3_OVF_INT_CLR. + LEDC_INT_CLR_HSTIMER3_OVF_INT_CLR = 0x8 + // Position of LSTIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER0_OVF_INT_CLR_Pos = 0x4 + // Bit mask of LSTIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER0_OVF_INT_CLR_Msk = 0x10 + // Bit LSTIMER0_OVF_INT_CLR. + LEDC_INT_CLR_LSTIMER0_OVF_INT_CLR = 0x10 + // Position of LSTIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER1_OVF_INT_CLR_Pos = 0x5 + // Bit mask of LSTIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER1_OVF_INT_CLR_Msk = 0x20 + // Bit LSTIMER1_OVF_INT_CLR. + LEDC_INT_CLR_LSTIMER1_OVF_INT_CLR = 0x20 + // Position of LSTIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER2_OVF_INT_CLR_Pos = 0x6 + // Bit mask of LSTIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER2_OVF_INT_CLR_Msk = 0x40 + // Bit LSTIMER2_OVF_INT_CLR. + LEDC_INT_CLR_LSTIMER2_OVF_INT_CLR = 0x40 + // Position of LSTIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER3_OVF_INT_CLR_Pos = 0x7 + // Bit mask of LSTIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER3_OVF_INT_CLR_Msk = 0x80 + // Bit LSTIMER3_OVF_INT_CLR. + LEDC_INT_CLR_LSTIMER3_OVF_INT_CLR = 0x80 + // Position of DUTY_CHNG_END_HSCH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH0_INT_CLR_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_HSCH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH0_INT_CLR_Msk = 0x100 + // Bit DUTY_CHNG_END_HSCH0_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH0_INT_CLR = 0x100 + // Position of DUTY_CHNG_END_HSCH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH1_INT_CLR_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_HSCH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH1_INT_CLR_Msk = 0x200 + // Bit DUTY_CHNG_END_HSCH1_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH1_INT_CLR = 0x200 + // Position of DUTY_CHNG_END_HSCH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH2_INT_CLR_Pos = 0xa + // Bit mask of DUTY_CHNG_END_HSCH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH2_INT_CLR_Msk = 0x400 + // Bit DUTY_CHNG_END_HSCH2_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH2_INT_CLR = 0x400 + // Position of DUTY_CHNG_END_HSCH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH3_INT_CLR_Pos = 0xb + // Bit mask of DUTY_CHNG_END_HSCH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH3_INT_CLR_Msk = 0x800 + // Bit DUTY_CHNG_END_HSCH3_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH3_INT_CLR = 0x800 + // Position of DUTY_CHNG_END_HSCH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH4_INT_CLR_Pos = 0xc + // Bit mask of DUTY_CHNG_END_HSCH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH4_INT_CLR_Msk = 0x1000 + // Bit DUTY_CHNG_END_HSCH4_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH4_INT_CLR = 0x1000 + // Position of DUTY_CHNG_END_HSCH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH5_INT_CLR_Pos = 0xd + // Bit mask of DUTY_CHNG_END_HSCH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH5_INT_CLR_Msk = 0x2000 + // Bit DUTY_CHNG_END_HSCH5_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH5_INT_CLR = 0x2000 + // Position of DUTY_CHNG_END_HSCH6_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH6_INT_CLR_Pos = 0xe + // Bit mask of DUTY_CHNG_END_HSCH6_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH6_INT_CLR_Msk = 0x4000 + // Bit DUTY_CHNG_END_HSCH6_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH6_INT_CLR = 0x4000 + // Position of DUTY_CHNG_END_HSCH7_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH7_INT_CLR_Pos = 0xf + // Bit mask of DUTY_CHNG_END_HSCH7_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH7_INT_CLR_Msk = 0x8000 + // Bit DUTY_CHNG_END_HSCH7_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_HSCH7_INT_CLR = 0x8000 + // Position of DUTY_CHNG_END_LSCH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR_Pos = 0x10 + // Bit mask of DUTY_CHNG_END_LSCH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR_Msk = 0x10000 + // Bit DUTY_CHNG_END_LSCH0_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR = 0x10000 + // Position of DUTY_CHNG_END_LSCH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR_Pos = 0x11 + // Bit mask of DUTY_CHNG_END_LSCH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR_Msk = 0x20000 + // Bit DUTY_CHNG_END_LSCH1_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR = 0x20000 + // Position of DUTY_CHNG_END_LSCH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR_Pos = 0x12 + // Bit mask of DUTY_CHNG_END_LSCH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR_Msk = 0x40000 + // Bit DUTY_CHNG_END_LSCH2_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR = 0x40000 + // Position of DUTY_CHNG_END_LSCH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR_Pos = 0x13 + // Bit mask of DUTY_CHNG_END_LSCH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR_Msk = 0x80000 + // Bit DUTY_CHNG_END_LSCH3_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR = 0x80000 + // Position of DUTY_CHNG_END_LSCH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR_Pos = 0x14 + // Bit mask of DUTY_CHNG_END_LSCH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR_Msk = 0x100000 + // Bit DUTY_CHNG_END_LSCH4_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR = 0x100000 + // Position of DUTY_CHNG_END_LSCH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR_Pos = 0x15 + // Bit mask of DUTY_CHNG_END_LSCH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR_Msk = 0x200000 + // Bit DUTY_CHNG_END_LSCH5_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR = 0x200000 + // Position of DUTY_CHNG_END_LSCH6_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH6_INT_CLR_Pos = 0x16 + // Bit mask of DUTY_CHNG_END_LSCH6_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH6_INT_CLR_Msk = 0x400000 + // Bit DUTY_CHNG_END_LSCH6_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH6_INT_CLR = 0x400000 + // Position of DUTY_CHNG_END_LSCH7_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH7_INT_CLR_Pos = 0x17 + // Bit mask of DUTY_CHNG_END_LSCH7_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH7_INT_CLR_Msk = 0x800000 + // Bit DUTY_CHNG_END_LSCH7_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH7_INT_CLR = 0x800000 + + // CONF + // Position of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Pos = 0x0 + // Bit mask of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Msk = 0x1 + // Bit APB_CLK_SEL. + LEDC_CONF_APB_CLK_SEL = 0x1 + + // DATE + // Position of DATE field. + LEDC_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LEDC_DATE_DATE_Msk = 0xffffffff +) + +// Constants for MCPWM0: Motor Control Pulse-Width Modulation 0 +const ( + // CLK_CFG + // Position of CLK_PRESCALE field. + MCPWM_CLK_CFG_CLK_PRESCALE_Pos = 0x0 + // Bit mask of CLK_PRESCALE field. + MCPWM_CLK_CFG_CLK_PRESCALE_Msk = 0xff + + // TIMER0_CFG0 + // Position of TIMER0_PRESCALE field. + MCPWM_TIMER0_CFG0_TIMER0_PRESCALE_Pos = 0x0 + // Bit mask of TIMER0_PRESCALE field. + MCPWM_TIMER0_CFG0_TIMER0_PRESCALE_Msk = 0xff + // Position of TIMER0_PERIOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_Pos = 0x8 + // Bit mask of TIMER0_PERIOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_Msk = 0xffff00 + // Position of TIMER0_PERIOD_UPMETHOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER0_PERIOD_UPMETHOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER0_CFG1 + // Position of TIMER0_START field. + MCPWM_TIMER0_CFG1_TIMER0_START_Pos = 0x0 + // Bit mask of TIMER0_START field. + MCPWM_TIMER0_CFG1_TIMER0_START_Msk = 0x7 + // Position of TIMER0_MOD field. + MCPWM_TIMER0_CFG1_TIMER0_MOD_Pos = 0x3 + // Bit mask of TIMER0_MOD field. + MCPWM_TIMER0_CFG1_TIMER0_MOD_Msk = 0x18 + + // TIMER0_SYNC + // Position of TIMER0_SYNCI_EN field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER0_SYNCI_EN field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCI_EN_Msk = 0x1 + // Bit TIMER0_SYNCI_EN. + MCPWM_TIMER0_SYNC_TIMER0_SYNCI_EN = 0x1 + // Position of SW field. + MCPWM_TIMER0_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + MCPWM_TIMER0_SYNC_SW_Msk = 0x2 + // Bit SW. + MCPWM_TIMER0_SYNC_SW = 0x2 + // Position of TIMER0_SYNCO_SEL field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER0_SYNCO_SEL field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCO_SEL_Msk = 0xc + // Position of TIMER0_PHASE field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_Pos = 0x4 + // Bit mask of TIMER0_PHASE field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_Msk = 0xffff0 + // Position of TIMER0_PHASE_DIRECTION field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER0_PHASE_DIRECTION field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER0_PHASE_DIRECTION. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION = 0x100000 + + // TIMER0_STATUS + // Position of TIMER0_VALUE field. + MCPWM_TIMER0_STATUS_TIMER0_VALUE_Pos = 0x0 + // Bit mask of TIMER0_VALUE field. + MCPWM_TIMER0_STATUS_TIMER0_VALUE_Msk = 0xffff + // Position of TIMER0_DIRECTION field. + MCPWM_TIMER0_STATUS_TIMER0_DIRECTION_Pos = 0x10 + // Bit mask of TIMER0_DIRECTION field. + MCPWM_TIMER0_STATUS_TIMER0_DIRECTION_Msk = 0x10000 + // Bit TIMER0_DIRECTION. + MCPWM_TIMER0_STATUS_TIMER0_DIRECTION = 0x10000 + + // TIMER1_CFG0 + // Position of TIMER1_PRESCALE field. + MCPWM_TIMER1_CFG0_TIMER1_PRESCALE_Pos = 0x0 + // Bit mask of TIMER1_PRESCALE field. + MCPWM_TIMER1_CFG0_TIMER1_PRESCALE_Msk = 0xff + // Position of TIMER1_PERIOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_Pos = 0x8 + // Bit mask of TIMER1_PERIOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_Msk = 0xffff00 + // Position of TIMER1_PERIOD_UPMETHOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER1_PERIOD_UPMETHOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER1_CFG1 + // Position of TIMER1_START field. + MCPWM_TIMER1_CFG1_TIMER1_START_Pos = 0x0 + // Bit mask of TIMER1_START field. + MCPWM_TIMER1_CFG1_TIMER1_START_Msk = 0x7 + // Position of TIMER1_MOD field. + MCPWM_TIMER1_CFG1_TIMER1_MOD_Pos = 0x3 + // Bit mask of TIMER1_MOD field. + MCPWM_TIMER1_CFG1_TIMER1_MOD_Msk = 0x18 + + // TIMER1_SYNC + // Position of TIMER1_SYNCI_EN field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER1_SYNCI_EN field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCI_EN_Msk = 0x1 + // Bit TIMER1_SYNCI_EN. + MCPWM_TIMER1_SYNC_TIMER1_SYNCI_EN = 0x1 + // Position of SW field. + MCPWM_TIMER1_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + MCPWM_TIMER1_SYNC_SW_Msk = 0x2 + // Bit SW. + MCPWM_TIMER1_SYNC_SW = 0x2 + // Position of TIMER1_SYNCO_SEL field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER1_SYNCO_SEL field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCO_SEL_Msk = 0xc + // Position of TIMER1_PHASE field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_Pos = 0x4 + // Bit mask of TIMER1_PHASE field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_Msk = 0xffff0 + // Position of TIMER1_PHASE_DIRECTION field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER1_PHASE_DIRECTION field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER1_PHASE_DIRECTION. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION = 0x100000 + + // TIMER1_STATUS + // Position of TIMER1_VALUE field. + MCPWM_TIMER1_STATUS_TIMER1_VALUE_Pos = 0x0 + // Bit mask of TIMER1_VALUE field. + MCPWM_TIMER1_STATUS_TIMER1_VALUE_Msk = 0xffff + // Position of TIMER1_DIRECTION field. + MCPWM_TIMER1_STATUS_TIMER1_DIRECTION_Pos = 0x10 + // Bit mask of TIMER1_DIRECTION field. + MCPWM_TIMER1_STATUS_TIMER1_DIRECTION_Msk = 0x10000 + // Bit TIMER1_DIRECTION. + MCPWM_TIMER1_STATUS_TIMER1_DIRECTION = 0x10000 + + // TIMER2_CFG0 + // Position of TIMER2_PRESCALE field. + MCPWM_TIMER2_CFG0_TIMER2_PRESCALE_Pos = 0x0 + // Bit mask of TIMER2_PRESCALE field. + MCPWM_TIMER2_CFG0_TIMER2_PRESCALE_Msk = 0xff + // Position of TIMER2_PERIOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_Pos = 0x8 + // Bit mask of TIMER2_PERIOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_Msk = 0xffff00 + // Position of TIMER2_PERIOD_UPMETHOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER2_PERIOD_UPMETHOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER2_CFG1 + // Position of TIMER2_START field. + MCPWM_TIMER2_CFG1_TIMER2_START_Pos = 0x0 + // Bit mask of TIMER2_START field. + MCPWM_TIMER2_CFG1_TIMER2_START_Msk = 0x7 + // Position of TIMER2_MOD field. + MCPWM_TIMER2_CFG1_TIMER2_MOD_Pos = 0x3 + // Bit mask of TIMER2_MOD field. + MCPWM_TIMER2_CFG1_TIMER2_MOD_Msk = 0x18 + + // TIMER2_SYNC + // Position of TIMER2_SYNCI_EN field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER2_SYNCI_EN field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCI_EN_Msk = 0x1 + // Bit TIMER2_SYNCI_EN. + MCPWM_TIMER2_SYNC_TIMER2_SYNCI_EN = 0x1 + // Position of SW field. + MCPWM_TIMER2_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + MCPWM_TIMER2_SYNC_SW_Msk = 0x2 + // Bit SW. + MCPWM_TIMER2_SYNC_SW = 0x2 + // Position of TIMER2_SYNCO_SEL field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER2_SYNCO_SEL field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCO_SEL_Msk = 0xc + // Position of TIMER2_PHASE field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_Pos = 0x4 + // Bit mask of TIMER2_PHASE field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_Msk = 0xffff0 + // Position of TIMER2_PHASE_DIRECTION field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER2_PHASE_DIRECTION field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER2_PHASE_DIRECTION. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION = 0x100000 + + // TIMER2_STATUS + // Position of TIMER2_VALUE field. + MCPWM_TIMER2_STATUS_TIMER2_VALUE_Pos = 0x0 + // Bit mask of TIMER2_VALUE field. + MCPWM_TIMER2_STATUS_TIMER2_VALUE_Msk = 0xffff + // Position of TIMER2_DIRECTION field. + MCPWM_TIMER2_STATUS_TIMER2_DIRECTION_Pos = 0x10 + // Bit mask of TIMER2_DIRECTION field. + MCPWM_TIMER2_STATUS_TIMER2_DIRECTION_Msk = 0x10000 + // Bit TIMER2_DIRECTION. + MCPWM_TIMER2_STATUS_TIMER2_DIRECTION = 0x10000 + + // TIMER_SYNCI_CFG + // Position of TIMER0_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Pos = 0x0 + // Bit mask of TIMER0_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Msk = 0x7 + // Position of TIMER1_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Pos = 0x3 + // Bit mask of TIMER1_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Msk = 0x38 + // Position of TIMER2_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Pos = 0x6 + // Bit mask of TIMER2_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Msk = 0x1c0 + // Position of EXTERNAL_SYNCI0_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Pos = 0x9 + // Bit mask of EXTERNAL_SYNCI0_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Msk = 0x200 + // Bit EXTERNAL_SYNCI0_INVERT. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT = 0x200 + // Position of EXTERNAL_SYNCI1_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Pos = 0xa + // Bit mask of EXTERNAL_SYNCI1_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Msk = 0x400 + // Bit EXTERNAL_SYNCI1_INVERT. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT = 0x400 + // Position of EXTERNAL_SYNCI2_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Pos = 0xb + // Bit mask of EXTERNAL_SYNCI2_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Msk = 0x800 + // Bit EXTERNAL_SYNCI2_INVERT. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT = 0x800 + + // OPERATOR_TIMERSEL + // Position of OPERATOR0_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Pos = 0x0 + // Bit mask of OPERATOR0_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Msk = 0x3 + // Position of OPERATOR1_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Pos = 0x2 + // Bit mask of OPERATOR1_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Msk = 0xc + // Position of OPERATOR2_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Pos = 0x4 + // Bit mask of OPERATOR2_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Msk = 0x30 + + // GEN0_STMP_CFG + // Position of GEN0_A_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_GEN0_A_UPMETHOD_Pos = 0x0 + // Bit mask of GEN0_A_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_GEN0_A_UPMETHOD_Msk = 0xf + // Position of GEN0_B_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_GEN0_B_UPMETHOD_Pos = 0x4 + // Bit mask of GEN0_B_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_GEN0_B_UPMETHOD_Msk = 0xf0 + // Position of GEN0_A_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_GEN0_A_SHDW_FULL_Pos = 0x8 + // Bit mask of GEN0_A_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_GEN0_A_SHDW_FULL_Msk = 0x100 + // Bit GEN0_A_SHDW_FULL. + MCPWM_GEN0_STMP_CFG_GEN0_A_SHDW_FULL = 0x100 + // Position of GEN0_B_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_GEN0_B_SHDW_FULL_Pos = 0x9 + // Bit mask of GEN0_B_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_GEN0_B_SHDW_FULL_Msk = 0x200 + // Bit GEN0_B_SHDW_FULL. + MCPWM_GEN0_STMP_CFG_GEN0_B_SHDW_FULL = 0x200 + + // GEN0_TSTMP_A + // Position of GEN0_A field. + MCPWM_GEN0_TSTMP_A_GEN0_A_Pos = 0x0 + // Bit mask of GEN0_A field. + MCPWM_GEN0_TSTMP_A_GEN0_A_Msk = 0xffff + + // GEN0_TSTMP_B + // Position of GEN0_B field. + MCPWM_GEN0_TSTMP_B_GEN0_B_Pos = 0x0 + // Bit mask of GEN0_B field. + MCPWM_GEN0_TSTMP_B_GEN0_B_Msk = 0xffff + + // GEN0_CFG0 + // Position of GEN0_CFG_UPMETHOD field. + MCPWM_GEN0_CFG0_GEN0_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN0_CFG_UPMETHOD field. + MCPWM_GEN0_CFG0_GEN0_CFG_UPMETHOD_Msk = 0xf + // Position of GEN0_T0_SEL field. + MCPWM_GEN0_CFG0_GEN0_T0_SEL_Pos = 0x4 + // Bit mask of GEN0_T0_SEL field. + MCPWM_GEN0_CFG0_GEN0_T0_SEL_Msk = 0x70 + // Position of GEN0_T1_SEL field. + MCPWM_GEN0_CFG0_GEN0_T1_SEL_Pos = 0x7 + // Bit mask of GEN0_T1_SEL field. + MCPWM_GEN0_CFG0_GEN0_T1_SEL_Msk = 0x380 + + // GEN0_FORCE + // Position of GEN0_CNTUFORCE_UPMETHOD field. + MCPWM_GEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN0_CNTUFORCE_UPMETHOD field. + MCPWM_GEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN0_A_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN0_A_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN0_B_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN0_B_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN0_A_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN0_A_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_Msk = 0x400 + // Bit GEN0_A_NCIFORCE. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE = 0x400 + // Position of GEN0_A_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN0_A_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN0_B_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN0_B_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_Msk = 0x2000 + // Bit GEN0_B_NCIFORCE. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE = 0x2000 + // Position of GEN0_B_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN0_B_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN0_A + // Position of UTEZ field. + MCPWM_GEN0_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN0_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN0_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN0_A_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN0_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN0_A_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN0_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN0_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN0_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN0_A_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN0_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN0_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN0_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN0_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN0_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN0_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN0_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN0_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN0_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN0_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN0_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN0_A_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN0_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN0_A_DT1_Msk = 0xc00000 + + // GEN0_B + // Position of UTEZ field. + MCPWM_GEN0_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN0_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN0_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN0_B_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN0_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN0_B_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN0_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN0_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN0_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN0_B_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN0_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN0_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN0_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN0_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN0_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN0_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN0_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN0_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN0_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN0_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN0_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN0_B_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN0_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN0_B_DT1_Msk = 0xc00000 + + // DT0_CFG + // Position of DT0_FED_UPMETHOD field. + MCPWM_DT0_CFG_DT0_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DT0_FED_UPMETHOD field. + MCPWM_DT0_CFG_DT0_FED_UPMETHOD_Msk = 0xf + // Position of DT0_RED_UPMETHOD field. + MCPWM_DT0_CFG_DT0_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DT0_RED_UPMETHOD field. + MCPWM_DT0_CFG_DT0_RED_UPMETHOD_Msk = 0xf0 + // Position of DT0_DEB_MODE field. + MCPWM_DT0_CFG_DT0_DEB_MODE_Pos = 0x8 + // Bit mask of DT0_DEB_MODE field. + MCPWM_DT0_CFG_DT0_DEB_MODE_Msk = 0x100 + // Bit DT0_DEB_MODE. + MCPWM_DT0_CFG_DT0_DEB_MODE = 0x100 + // Position of DT0_A_OUTSWAP field. + MCPWM_DT0_CFG_DT0_A_OUTSWAP_Pos = 0x9 + // Bit mask of DT0_A_OUTSWAP field. + MCPWM_DT0_CFG_DT0_A_OUTSWAP_Msk = 0x200 + // Bit DT0_A_OUTSWAP. + MCPWM_DT0_CFG_DT0_A_OUTSWAP = 0x200 + // Position of DT0_B_OUTSWAP field. + MCPWM_DT0_CFG_DT0_B_OUTSWAP_Pos = 0xa + // Bit mask of DT0_B_OUTSWAP field. + MCPWM_DT0_CFG_DT0_B_OUTSWAP_Msk = 0x400 + // Bit DT0_B_OUTSWAP. + MCPWM_DT0_CFG_DT0_B_OUTSWAP = 0x400 + // Position of DT0_RED_INSEL field. + MCPWM_DT0_CFG_DT0_RED_INSEL_Pos = 0xb + // Bit mask of DT0_RED_INSEL field. + MCPWM_DT0_CFG_DT0_RED_INSEL_Msk = 0x800 + // Bit DT0_RED_INSEL. + MCPWM_DT0_CFG_DT0_RED_INSEL = 0x800 + // Position of DT0_FED_INSEL field. + MCPWM_DT0_CFG_DT0_FED_INSEL_Pos = 0xc + // Bit mask of DT0_FED_INSEL field. + MCPWM_DT0_CFG_DT0_FED_INSEL_Msk = 0x1000 + // Bit DT0_FED_INSEL. + MCPWM_DT0_CFG_DT0_FED_INSEL = 0x1000 + // Position of DT0_RED_OUTINVERT field. + MCPWM_DT0_CFG_DT0_RED_OUTINVERT_Pos = 0xd + // Bit mask of DT0_RED_OUTINVERT field. + MCPWM_DT0_CFG_DT0_RED_OUTINVERT_Msk = 0x2000 + // Bit DT0_RED_OUTINVERT. + MCPWM_DT0_CFG_DT0_RED_OUTINVERT = 0x2000 + // Position of DT0_FED_OUTINVERT field. + MCPWM_DT0_CFG_DT0_FED_OUTINVERT_Pos = 0xe + // Bit mask of DT0_FED_OUTINVERT field. + MCPWM_DT0_CFG_DT0_FED_OUTINVERT_Msk = 0x4000 + // Bit DT0_FED_OUTINVERT. + MCPWM_DT0_CFG_DT0_FED_OUTINVERT = 0x4000 + // Position of DT0_A_OUTBYPASS field. + MCPWM_DT0_CFG_DT0_A_OUTBYPASS_Pos = 0xf + // Bit mask of DT0_A_OUTBYPASS field. + MCPWM_DT0_CFG_DT0_A_OUTBYPASS_Msk = 0x8000 + // Bit DT0_A_OUTBYPASS. + MCPWM_DT0_CFG_DT0_A_OUTBYPASS = 0x8000 + // Position of DT0_B_OUTBYPASS field. + MCPWM_DT0_CFG_DT0_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DT0_B_OUTBYPASS field. + MCPWM_DT0_CFG_DT0_B_OUTBYPASS_Msk = 0x10000 + // Bit DT0_B_OUTBYPASS. + MCPWM_DT0_CFG_DT0_B_OUTBYPASS = 0x10000 + // Position of DT0_CLK_SEL field. + MCPWM_DT0_CFG_DT0_CLK_SEL_Pos = 0x11 + // Bit mask of DT0_CLK_SEL field. + MCPWM_DT0_CFG_DT0_CLK_SEL_Msk = 0x20000 + // Bit DT0_CLK_SEL. + MCPWM_DT0_CFG_DT0_CLK_SEL = 0x20000 + + // DT0_FED_CFG + // Position of DT0_FED field. + MCPWM_DT0_FED_CFG_DT0_FED_Pos = 0x0 + // Bit mask of DT0_FED field. + MCPWM_DT0_FED_CFG_DT0_FED_Msk = 0xffff + + // DT0_RED_CFG + // Position of DT0_RED field. + MCPWM_DT0_RED_CFG_DT0_RED_Pos = 0x0 + // Bit mask of DT0_RED field. + MCPWM_DT0_RED_CFG_DT0_RED_Msk = 0xffff + + // CARRIER0_CFG + // Position of CARRIER0_EN field. + MCPWM_CARRIER0_CFG_CARRIER0_EN_Pos = 0x0 + // Bit mask of CARRIER0_EN field. + MCPWM_CARRIER0_CFG_CARRIER0_EN_Msk = 0x1 + // Bit CARRIER0_EN. + MCPWM_CARRIER0_CFG_CARRIER0_EN = 0x1 + // Position of CARRIER0_PRESCALE field. + MCPWM_CARRIER0_CFG_CARRIER0_PRESCALE_Pos = 0x1 + // Bit mask of CARRIER0_PRESCALE field. + MCPWM_CARRIER0_CFG_CARRIER0_PRESCALE_Msk = 0x1e + // Position of CARRIER0_DUTY field. + MCPWM_CARRIER0_CFG_CARRIER0_DUTY_Pos = 0x5 + // Bit mask of CARRIER0_DUTY field. + MCPWM_CARRIER0_CFG_CARRIER0_DUTY_Msk = 0xe0 + // Position of CARRIER0_OSHTWTH field. + MCPWM_CARRIER0_CFG_CARRIER0_OSHTWTH_Pos = 0x8 + // Bit mask of CARRIER0_OSHTWTH field. + MCPWM_CARRIER0_CFG_CARRIER0_OSHTWTH_Msk = 0xf00 + // Position of CARRIER0_OUT_INVERT field. + MCPWM_CARRIER0_CFG_CARRIER0_OUT_INVERT_Pos = 0xc + // Bit mask of CARRIER0_OUT_INVERT field. + MCPWM_CARRIER0_CFG_CARRIER0_OUT_INVERT_Msk = 0x1000 + // Bit CARRIER0_OUT_INVERT. + MCPWM_CARRIER0_CFG_CARRIER0_OUT_INVERT = 0x1000 + // Position of CARRIER0_IN_INVERT field. + MCPWM_CARRIER0_CFG_CARRIER0_IN_INVERT_Pos = 0xd + // Bit mask of CARRIER0_IN_INVERT field. + MCPWM_CARRIER0_CFG_CARRIER0_IN_INVERT_Msk = 0x2000 + // Bit CARRIER0_IN_INVERT. + MCPWM_CARRIER0_CFG_CARRIER0_IN_INVERT = 0x2000 + + // FH0_CFG0 + // Position of FH0_SW_CBC field. + MCPWM_FH0_CFG0_FH0_SW_CBC_Pos = 0x0 + // Bit mask of FH0_SW_CBC field. + MCPWM_FH0_CFG0_FH0_SW_CBC_Msk = 0x1 + // Bit FH0_SW_CBC. + MCPWM_FH0_CFG0_FH0_SW_CBC = 0x1 + // Position of FH0_F2_CBC field. + MCPWM_FH0_CFG0_FH0_F2_CBC_Pos = 0x1 + // Bit mask of FH0_F2_CBC field. + MCPWM_FH0_CFG0_FH0_F2_CBC_Msk = 0x2 + // Bit FH0_F2_CBC. + MCPWM_FH0_CFG0_FH0_F2_CBC = 0x2 + // Position of FH0_F1_CBC field. + MCPWM_FH0_CFG0_FH0_F1_CBC_Pos = 0x2 + // Bit mask of FH0_F1_CBC field. + MCPWM_FH0_CFG0_FH0_F1_CBC_Msk = 0x4 + // Bit FH0_F1_CBC. + MCPWM_FH0_CFG0_FH0_F1_CBC = 0x4 + // Position of FH0_F0_CBC field. + MCPWM_FH0_CFG0_FH0_F0_CBC_Pos = 0x3 + // Bit mask of FH0_F0_CBC field. + MCPWM_FH0_CFG0_FH0_F0_CBC_Msk = 0x8 + // Bit FH0_F0_CBC. + MCPWM_FH0_CFG0_FH0_F0_CBC = 0x8 + // Position of FH0_SW_OST field. + MCPWM_FH0_CFG0_FH0_SW_OST_Pos = 0x4 + // Bit mask of FH0_SW_OST field. + MCPWM_FH0_CFG0_FH0_SW_OST_Msk = 0x10 + // Bit FH0_SW_OST. + MCPWM_FH0_CFG0_FH0_SW_OST = 0x10 + // Position of FH0_F2_OST field. + MCPWM_FH0_CFG0_FH0_F2_OST_Pos = 0x5 + // Bit mask of FH0_F2_OST field. + MCPWM_FH0_CFG0_FH0_F2_OST_Msk = 0x20 + // Bit FH0_F2_OST. + MCPWM_FH0_CFG0_FH0_F2_OST = 0x20 + // Position of FH0_F1_OST field. + MCPWM_FH0_CFG0_FH0_F1_OST_Pos = 0x6 + // Bit mask of FH0_F1_OST field. + MCPWM_FH0_CFG0_FH0_F1_OST_Msk = 0x40 + // Bit FH0_F1_OST. + MCPWM_FH0_CFG0_FH0_F1_OST = 0x40 + // Position of FH0_F0_OST field. + MCPWM_FH0_CFG0_FH0_F0_OST_Pos = 0x7 + // Bit mask of FH0_F0_OST field. + MCPWM_FH0_CFG0_FH0_F0_OST_Msk = 0x80 + // Bit FH0_F0_OST. + MCPWM_FH0_CFG0_FH0_F0_OST = 0x80 + // Position of FH0_A_CBC_D field. + MCPWM_FH0_CFG0_FH0_A_CBC_D_Pos = 0x8 + // Bit mask of FH0_A_CBC_D field. + MCPWM_FH0_CFG0_FH0_A_CBC_D_Msk = 0x300 + // Position of FH0_A_CBC_U field. + MCPWM_FH0_CFG0_FH0_A_CBC_U_Pos = 0xa + // Bit mask of FH0_A_CBC_U field. + MCPWM_FH0_CFG0_FH0_A_CBC_U_Msk = 0xc00 + // Position of FH0_A_OST_D field. + MCPWM_FH0_CFG0_FH0_A_OST_D_Pos = 0xc + // Bit mask of FH0_A_OST_D field. + MCPWM_FH0_CFG0_FH0_A_OST_D_Msk = 0x3000 + // Position of FH0_A_OST_U field. + MCPWM_FH0_CFG0_FH0_A_OST_U_Pos = 0xe + // Bit mask of FH0_A_OST_U field. + MCPWM_FH0_CFG0_FH0_A_OST_U_Msk = 0xc000 + // Position of FH0_B_CBC_D field. + MCPWM_FH0_CFG0_FH0_B_CBC_D_Pos = 0x10 + // Bit mask of FH0_B_CBC_D field. + MCPWM_FH0_CFG0_FH0_B_CBC_D_Msk = 0x30000 + // Position of FH0_B_CBC_U field. + MCPWM_FH0_CFG0_FH0_B_CBC_U_Pos = 0x12 + // Bit mask of FH0_B_CBC_U field. + MCPWM_FH0_CFG0_FH0_B_CBC_U_Msk = 0xc0000 + // Position of FH0_B_OST_D field. + MCPWM_FH0_CFG0_FH0_B_OST_D_Pos = 0x14 + // Bit mask of FH0_B_OST_D field. + MCPWM_FH0_CFG0_FH0_B_OST_D_Msk = 0x300000 + // Position of FH0_B_OST_U field. + MCPWM_FH0_CFG0_FH0_B_OST_U_Pos = 0x16 + // Bit mask of FH0_B_OST_U field. + MCPWM_FH0_CFG0_FH0_B_OST_U_Msk = 0xc00000 + + // FH0_CFG1 + // Position of FH0_CLR_OST field. + MCPWM_FH0_CFG1_FH0_CLR_OST_Pos = 0x0 + // Bit mask of FH0_CLR_OST field. + MCPWM_FH0_CFG1_FH0_CLR_OST_Msk = 0x1 + // Bit FH0_CLR_OST. + MCPWM_FH0_CFG1_FH0_CLR_OST = 0x1 + // Position of FH0_CBCPULSE field. + MCPWM_FH0_CFG1_FH0_CBCPULSE_Pos = 0x1 + // Bit mask of FH0_CBCPULSE field. + MCPWM_FH0_CFG1_FH0_CBCPULSE_Msk = 0x6 + // Position of FH0_FORCE_CBC field. + MCPWM_FH0_CFG1_FH0_FORCE_CBC_Pos = 0x3 + // Bit mask of FH0_FORCE_CBC field. + MCPWM_FH0_CFG1_FH0_FORCE_CBC_Msk = 0x8 + // Bit FH0_FORCE_CBC. + MCPWM_FH0_CFG1_FH0_FORCE_CBC = 0x8 + // Position of FH0_FORCE_OST field. + MCPWM_FH0_CFG1_FH0_FORCE_OST_Pos = 0x4 + // Bit mask of FH0_FORCE_OST field. + MCPWM_FH0_CFG1_FH0_FORCE_OST_Msk = 0x10 + // Bit FH0_FORCE_OST. + MCPWM_FH0_CFG1_FH0_FORCE_OST = 0x10 + + // FH0_STATUS + // Position of FH0_CBC_ON field. + MCPWM_FH0_STATUS_FH0_CBC_ON_Pos = 0x0 + // Bit mask of FH0_CBC_ON field. + MCPWM_FH0_STATUS_FH0_CBC_ON_Msk = 0x1 + // Bit FH0_CBC_ON. + MCPWM_FH0_STATUS_FH0_CBC_ON = 0x1 + // Position of FH0_OST_ON field. + MCPWM_FH0_STATUS_FH0_OST_ON_Pos = 0x1 + // Bit mask of FH0_OST_ON field. + MCPWM_FH0_STATUS_FH0_OST_ON_Msk = 0x2 + // Bit FH0_OST_ON. + MCPWM_FH0_STATUS_FH0_OST_ON = 0x2 + + // GEN1_STMP_CFG + // Position of GEN1_A_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_GEN1_A_UPMETHOD_Pos = 0x0 + // Bit mask of GEN1_A_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_GEN1_A_UPMETHOD_Msk = 0xf + // Position of GEN1_B_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_GEN1_B_UPMETHOD_Pos = 0x4 + // Bit mask of GEN1_B_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_GEN1_B_UPMETHOD_Msk = 0xf0 + // Position of GEN1_A_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_GEN1_A_SHDW_FULL_Pos = 0x8 + // Bit mask of GEN1_A_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_GEN1_A_SHDW_FULL_Msk = 0x100 + // Bit GEN1_A_SHDW_FULL. + MCPWM_GEN1_STMP_CFG_GEN1_A_SHDW_FULL = 0x100 + // Position of GEN1_B_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_GEN1_B_SHDW_FULL_Pos = 0x9 + // Bit mask of GEN1_B_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_GEN1_B_SHDW_FULL_Msk = 0x200 + // Bit GEN1_B_SHDW_FULL. + MCPWM_GEN1_STMP_CFG_GEN1_B_SHDW_FULL = 0x200 + + // GEN1_TSTMP_A + // Position of GEN1_A field. + MCPWM_GEN1_TSTMP_A_GEN1_A_Pos = 0x0 + // Bit mask of GEN1_A field. + MCPWM_GEN1_TSTMP_A_GEN1_A_Msk = 0xffff + + // GEN1_TSTMP_B + // Position of GEN1_B field. + MCPWM_GEN1_TSTMP_B_GEN1_B_Pos = 0x0 + // Bit mask of GEN1_B field. + MCPWM_GEN1_TSTMP_B_GEN1_B_Msk = 0xffff + + // GEN1_CFG0 + // Position of GEN1_CFG_UPMETHOD field. + MCPWM_GEN1_CFG0_GEN1_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN1_CFG_UPMETHOD field. + MCPWM_GEN1_CFG0_GEN1_CFG_UPMETHOD_Msk = 0xf + // Position of GEN1_T0_SEL field. + MCPWM_GEN1_CFG0_GEN1_T0_SEL_Pos = 0x4 + // Bit mask of GEN1_T0_SEL field. + MCPWM_GEN1_CFG0_GEN1_T0_SEL_Msk = 0x70 + // Position of GEN1_T1_SEL field. + MCPWM_GEN1_CFG0_GEN1_T1_SEL_Pos = 0x7 + // Bit mask of GEN1_T1_SEL field. + MCPWM_GEN1_CFG0_GEN1_T1_SEL_Msk = 0x380 + + // GEN1_FORCE + // Position of GEN1_CNTUFORCE_UPMETHOD field. + MCPWM_GEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN1_CNTUFORCE_UPMETHOD field. + MCPWM_GEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN1_A_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN1_A_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN1_B_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN1_B_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN1_A_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN1_A_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_Msk = 0x400 + // Bit GEN1_A_NCIFORCE. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE = 0x400 + // Position of GEN1_A_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN1_A_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN1_B_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN1_B_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_Msk = 0x2000 + // Bit GEN1_B_NCIFORCE. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE = 0x2000 + // Position of GEN1_B_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN1_B_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN1_A + // Position of UTEZ field. + MCPWM_GEN1_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN1_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN1_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN1_A_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN1_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN1_A_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN1_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN1_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN1_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN1_A_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN1_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN1_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN1_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN1_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN1_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN1_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN1_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN1_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN1_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN1_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN1_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN1_A_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN1_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN1_A_DT1_Msk = 0xc00000 + + // GEN1_B + // Position of UTEZ field. + MCPWM_GEN1_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN1_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN1_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN1_B_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN1_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN1_B_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN1_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN1_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN1_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN1_B_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN1_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN1_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN1_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN1_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN1_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN1_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN1_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN1_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN1_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN1_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN1_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN1_B_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN1_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN1_B_DT1_Msk = 0xc00000 + + // DT1_CFG + // Position of DT1_FED_UPMETHOD field. + MCPWM_DT1_CFG_DT1_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DT1_FED_UPMETHOD field. + MCPWM_DT1_CFG_DT1_FED_UPMETHOD_Msk = 0xf + // Position of DT1_RED_UPMETHOD field. + MCPWM_DT1_CFG_DT1_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DT1_RED_UPMETHOD field. + MCPWM_DT1_CFG_DT1_RED_UPMETHOD_Msk = 0xf0 + // Position of DT1_DEB_MODE field. + MCPWM_DT1_CFG_DT1_DEB_MODE_Pos = 0x8 + // Bit mask of DT1_DEB_MODE field. + MCPWM_DT1_CFG_DT1_DEB_MODE_Msk = 0x100 + // Bit DT1_DEB_MODE. + MCPWM_DT1_CFG_DT1_DEB_MODE = 0x100 + // Position of DT1_A_OUTSWAP field. + MCPWM_DT1_CFG_DT1_A_OUTSWAP_Pos = 0x9 + // Bit mask of DT1_A_OUTSWAP field. + MCPWM_DT1_CFG_DT1_A_OUTSWAP_Msk = 0x200 + // Bit DT1_A_OUTSWAP. + MCPWM_DT1_CFG_DT1_A_OUTSWAP = 0x200 + // Position of DT1_B_OUTSWAP field. + MCPWM_DT1_CFG_DT1_B_OUTSWAP_Pos = 0xa + // Bit mask of DT1_B_OUTSWAP field. + MCPWM_DT1_CFG_DT1_B_OUTSWAP_Msk = 0x400 + // Bit DT1_B_OUTSWAP. + MCPWM_DT1_CFG_DT1_B_OUTSWAP = 0x400 + // Position of DT1_RED_INSEL field. + MCPWM_DT1_CFG_DT1_RED_INSEL_Pos = 0xb + // Bit mask of DT1_RED_INSEL field. + MCPWM_DT1_CFG_DT1_RED_INSEL_Msk = 0x800 + // Bit DT1_RED_INSEL. + MCPWM_DT1_CFG_DT1_RED_INSEL = 0x800 + // Position of DT1_FED_INSEL field. + MCPWM_DT1_CFG_DT1_FED_INSEL_Pos = 0xc + // Bit mask of DT1_FED_INSEL field. + MCPWM_DT1_CFG_DT1_FED_INSEL_Msk = 0x1000 + // Bit DT1_FED_INSEL. + MCPWM_DT1_CFG_DT1_FED_INSEL = 0x1000 + // Position of DT1_RED_OUTINVERT field. + MCPWM_DT1_CFG_DT1_RED_OUTINVERT_Pos = 0xd + // Bit mask of DT1_RED_OUTINVERT field. + MCPWM_DT1_CFG_DT1_RED_OUTINVERT_Msk = 0x2000 + // Bit DT1_RED_OUTINVERT. + MCPWM_DT1_CFG_DT1_RED_OUTINVERT = 0x2000 + // Position of DT1_FED_OUTINVERT field. + MCPWM_DT1_CFG_DT1_FED_OUTINVERT_Pos = 0xe + // Bit mask of DT1_FED_OUTINVERT field. + MCPWM_DT1_CFG_DT1_FED_OUTINVERT_Msk = 0x4000 + // Bit DT1_FED_OUTINVERT. + MCPWM_DT1_CFG_DT1_FED_OUTINVERT = 0x4000 + // Position of DT1_A_OUTBYPASS field. + MCPWM_DT1_CFG_DT1_A_OUTBYPASS_Pos = 0xf + // Bit mask of DT1_A_OUTBYPASS field. + MCPWM_DT1_CFG_DT1_A_OUTBYPASS_Msk = 0x8000 + // Bit DT1_A_OUTBYPASS. + MCPWM_DT1_CFG_DT1_A_OUTBYPASS = 0x8000 + // Position of DT1_B_OUTBYPASS field. + MCPWM_DT1_CFG_DT1_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DT1_B_OUTBYPASS field. + MCPWM_DT1_CFG_DT1_B_OUTBYPASS_Msk = 0x10000 + // Bit DT1_B_OUTBYPASS. + MCPWM_DT1_CFG_DT1_B_OUTBYPASS = 0x10000 + // Position of DT1_CLK_SEL field. + MCPWM_DT1_CFG_DT1_CLK_SEL_Pos = 0x11 + // Bit mask of DT1_CLK_SEL field. + MCPWM_DT1_CFG_DT1_CLK_SEL_Msk = 0x20000 + // Bit DT1_CLK_SEL. + MCPWM_DT1_CFG_DT1_CLK_SEL = 0x20000 + + // DT1_FED_CFG + // Position of DT1_FED field. + MCPWM_DT1_FED_CFG_DT1_FED_Pos = 0x0 + // Bit mask of DT1_FED field. + MCPWM_DT1_FED_CFG_DT1_FED_Msk = 0xffff + + // DT1_RED_CFG + // Position of DT1_RED field. + MCPWM_DT1_RED_CFG_DT1_RED_Pos = 0x0 + // Bit mask of DT1_RED field. + MCPWM_DT1_RED_CFG_DT1_RED_Msk = 0xffff + + // CARRIER1_CFG + // Position of CARRIER1_EN field. + MCPWM_CARRIER1_CFG_CARRIER1_EN_Pos = 0x0 + // Bit mask of CARRIER1_EN field. + MCPWM_CARRIER1_CFG_CARRIER1_EN_Msk = 0x1 + // Bit CARRIER1_EN. + MCPWM_CARRIER1_CFG_CARRIER1_EN = 0x1 + // Position of CARRIER1_PRESCALE field. + MCPWM_CARRIER1_CFG_CARRIER1_PRESCALE_Pos = 0x1 + // Bit mask of CARRIER1_PRESCALE field. + MCPWM_CARRIER1_CFG_CARRIER1_PRESCALE_Msk = 0x1e + // Position of CARRIER1_DUTY field. + MCPWM_CARRIER1_CFG_CARRIER1_DUTY_Pos = 0x5 + // Bit mask of CARRIER1_DUTY field. + MCPWM_CARRIER1_CFG_CARRIER1_DUTY_Msk = 0xe0 + // Position of CARRIER1_OSHTWTH field. + MCPWM_CARRIER1_CFG_CARRIER1_OSHTWTH_Pos = 0x8 + // Bit mask of CARRIER1_OSHTWTH field. + MCPWM_CARRIER1_CFG_CARRIER1_OSHTWTH_Msk = 0xf00 + // Position of CARRIER1_OUT_INVERT field. + MCPWM_CARRIER1_CFG_CARRIER1_OUT_INVERT_Pos = 0xc + // Bit mask of CARRIER1_OUT_INVERT field. + MCPWM_CARRIER1_CFG_CARRIER1_OUT_INVERT_Msk = 0x1000 + // Bit CARRIER1_OUT_INVERT. + MCPWM_CARRIER1_CFG_CARRIER1_OUT_INVERT = 0x1000 + // Position of CARRIER1_IN_INVERT field. + MCPWM_CARRIER1_CFG_CARRIER1_IN_INVERT_Pos = 0xd + // Bit mask of CARRIER1_IN_INVERT field. + MCPWM_CARRIER1_CFG_CARRIER1_IN_INVERT_Msk = 0x2000 + // Bit CARRIER1_IN_INVERT. + MCPWM_CARRIER1_CFG_CARRIER1_IN_INVERT = 0x2000 + + // FH1_CFG0 + // Position of FH1_SW_CBC field. + MCPWM_FH1_CFG0_FH1_SW_CBC_Pos = 0x0 + // Bit mask of FH1_SW_CBC field. + MCPWM_FH1_CFG0_FH1_SW_CBC_Msk = 0x1 + // Bit FH1_SW_CBC. + MCPWM_FH1_CFG0_FH1_SW_CBC = 0x1 + // Position of FH1_F2_CBC field. + MCPWM_FH1_CFG0_FH1_F2_CBC_Pos = 0x1 + // Bit mask of FH1_F2_CBC field. + MCPWM_FH1_CFG0_FH1_F2_CBC_Msk = 0x2 + // Bit FH1_F2_CBC. + MCPWM_FH1_CFG0_FH1_F2_CBC = 0x2 + // Position of FH1_F1_CBC field. + MCPWM_FH1_CFG0_FH1_F1_CBC_Pos = 0x2 + // Bit mask of FH1_F1_CBC field. + MCPWM_FH1_CFG0_FH1_F1_CBC_Msk = 0x4 + // Bit FH1_F1_CBC. + MCPWM_FH1_CFG0_FH1_F1_CBC = 0x4 + // Position of FH1_F0_CBC field. + MCPWM_FH1_CFG0_FH1_F0_CBC_Pos = 0x3 + // Bit mask of FH1_F0_CBC field. + MCPWM_FH1_CFG0_FH1_F0_CBC_Msk = 0x8 + // Bit FH1_F0_CBC. + MCPWM_FH1_CFG0_FH1_F0_CBC = 0x8 + // Position of FH1_SW_OST field. + MCPWM_FH1_CFG0_FH1_SW_OST_Pos = 0x4 + // Bit mask of FH1_SW_OST field. + MCPWM_FH1_CFG0_FH1_SW_OST_Msk = 0x10 + // Bit FH1_SW_OST. + MCPWM_FH1_CFG0_FH1_SW_OST = 0x10 + // Position of FH1_F2_OST field. + MCPWM_FH1_CFG0_FH1_F2_OST_Pos = 0x5 + // Bit mask of FH1_F2_OST field. + MCPWM_FH1_CFG0_FH1_F2_OST_Msk = 0x20 + // Bit FH1_F2_OST. + MCPWM_FH1_CFG0_FH1_F2_OST = 0x20 + // Position of FH1_F1_OST field. + MCPWM_FH1_CFG0_FH1_F1_OST_Pos = 0x6 + // Bit mask of FH1_F1_OST field. + MCPWM_FH1_CFG0_FH1_F1_OST_Msk = 0x40 + // Bit FH1_F1_OST. + MCPWM_FH1_CFG0_FH1_F1_OST = 0x40 + // Position of FH1_F0_OST field. + MCPWM_FH1_CFG0_FH1_F0_OST_Pos = 0x7 + // Bit mask of FH1_F0_OST field. + MCPWM_FH1_CFG0_FH1_F0_OST_Msk = 0x80 + // Bit FH1_F0_OST. + MCPWM_FH1_CFG0_FH1_F0_OST = 0x80 + // Position of FH1_A_CBC_D field. + MCPWM_FH1_CFG0_FH1_A_CBC_D_Pos = 0x8 + // Bit mask of FH1_A_CBC_D field. + MCPWM_FH1_CFG0_FH1_A_CBC_D_Msk = 0x300 + // Position of FH1_A_CBC_U field. + MCPWM_FH1_CFG0_FH1_A_CBC_U_Pos = 0xa + // Bit mask of FH1_A_CBC_U field. + MCPWM_FH1_CFG0_FH1_A_CBC_U_Msk = 0xc00 + // Position of FH1_A_OST_D field. + MCPWM_FH1_CFG0_FH1_A_OST_D_Pos = 0xc + // Bit mask of FH1_A_OST_D field. + MCPWM_FH1_CFG0_FH1_A_OST_D_Msk = 0x3000 + // Position of FH1_A_OST_U field. + MCPWM_FH1_CFG0_FH1_A_OST_U_Pos = 0xe + // Bit mask of FH1_A_OST_U field. + MCPWM_FH1_CFG0_FH1_A_OST_U_Msk = 0xc000 + // Position of FH1_B_CBC_D field. + MCPWM_FH1_CFG0_FH1_B_CBC_D_Pos = 0x10 + // Bit mask of FH1_B_CBC_D field. + MCPWM_FH1_CFG0_FH1_B_CBC_D_Msk = 0x30000 + // Position of FH1_B_CBC_U field. + MCPWM_FH1_CFG0_FH1_B_CBC_U_Pos = 0x12 + // Bit mask of FH1_B_CBC_U field. + MCPWM_FH1_CFG0_FH1_B_CBC_U_Msk = 0xc0000 + // Position of FH1_B_OST_D field. + MCPWM_FH1_CFG0_FH1_B_OST_D_Pos = 0x14 + // Bit mask of FH1_B_OST_D field. + MCPWM_FH1_CFG0_FH1_B_OST_D_Msk = 0x300000 + // Position of FH1_B_OST_U field. + MCPWM_FH1_CFG0_FH1_B_OST_U_Pos = 0x16 + // Bit mask of FH1_B_OST_U field. + MCPWM_FH1_CFG0_FH1_B_OST_U_Msk = 0xc00000 + + // FH1_CFG1 + // Position of FH1_CLR_OST field. + MCPWM_FH1_CFG1_FH1_CLR_OST_Pos = 0x0 + // Bit mask of FH1_CLR_OST field. + MCPWM_FH1_CFG1_FH1_CLR_OST_Msk = 0x1 + // Bit FH1_CLR_OST. + MCPWM_FH1_CFG1_FH1_CLR_OST = 0x1 + // Position of FH1_CBCPULSE field. + MCPWM_FH1_CFG1_FH1_CBCPULSE_Pos = 0x1 + // Bit mask of FH1_CBCPULSE field. + MCPWM_FH1_CFG1_FH1_CBCPULSE_Msk = 0x6 + // Position of FH1_FORCE_CBC field. + MCPWM_FH1_CFG1_FH1_FORCE_CBC_Pos = 0x3 + // Bit mask of FH1_FORCE_CBC field. + MCPWM_FH1_CFG1_FH1_FORCE_CBC_Msk = 0x8 + // Bit FH1_FORCE_CBC. + MCPWM_FH1_CFG1_FH1_FORCE_CBC = 0x8 + // Position of FH1_FORCE_OST field. + MCPWM_FH1_CFG1_FH1_FORCE_OST_Pos = 0x4 + // Bit mask of FH1_FORCE_OST field. + MCPWM_FH1_CFG1_FH1_FORCE_OST_Msk = 0x10 + // Bit FH1_FORCE_OST. + MCPWM_FH1_CFG1_FH1_FORCE_OST = 0x10 + + // FH1_STATUS + // Position of FH1_CBC_ON field. + MCPWM_FH1_STATUS_FH1_CBC_ON_Pos = 0x0 + // Bit mask of FH1_CBC_ON field. + MCPWM_FH1_STATUS_FH1_CBC_ON_Msk = 0x1 + // Bit FH1_CBC_ON. + MCPWM_FH1_STATUS_FH1_CBC_ON = 0x1 + // Position of FH1_OST_ON field. + MCPWM_FH1_STATUS_FH1_OST_ON_Pos = 0x1 + // Bit mask of FH1_OST_ON field. + MCPWM_FH1_STATUS_FH1_OST_ON_Msk = 0x2 + // Bit FH1_OST_ON. + MCPWM_FH1_STATUS_FH1_OST_ON = 0x2 + + // GEN2_STMP_CFG + // Position of GEN2_A_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_GEN2_A_UPMETHOD_Pos = 0x0 + // Bit mask of GEN2_A_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_GEN2_A_UPMETHOD_Msk = 0xf + // Position of GEN2_B_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_GEN2_B_UPMETHOD_Pos = 0x4 + // Bit mask of GEN2_B_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_GEN2_B_UPMETHOD_Msk = 0xf0 + // Position of GEN2_A_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_GEN2_A_SHDW_FULL_Pos = 0x8 + // Bit mask of GEN2_A_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_GEN2_A_SHDW_FULL_Msk = 0x100 + // Bit GEN2_A_SHDW_FULL. + MCPWM_GEN2_STMP_CFG_GEN2_A_SHDW_FULL = 0x100 + // Position of GEN2_B_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_GEN2_B_SHDW_FULL_Pos = 0x9 + // Bit mask of GEN2_B_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_GEN2_B_SHDW_FULL_Msk = 0x200 + // Bit GEN2_B_SHDW_FULL. + MCPWM_GEN2_STMP_CFG_GEN2_B_SHDW_FULL = 0x200 + + // GEN2_TSTMP_A + // Position of GEN2_A field. + MCPWM_GEN2_TSTMP_A_GEN2_A_Pos = 0x0 + // Bit mask of GEN2_A field. + MCPWM_GEN2_TSTMP_A_GEN2_A_Msk = 0xffff + + // GEN2_TSTMP_B + // Position of GEN2_B field. + MCPWM_GEN2_TSTMP_B_GEN2_B_Pos = 0x0 + // Bit mask of GEN2_B field. + MCPWM_GEN2_TSTMP_B_GEN2_B_Msk = 0xffff + + // GEN2_CFG0 + // Position of GEN2_CFG_UPMETHOD field. + MCPWM_GEN2_CFG0_GEN2_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN2_CFG_UPMETHOD field. + MCPWM_GEN2_CFG0_GEN2_CFG_UPMETHOD_Msk = 0xf + // Position of GEN2_T0_SEL field. + MCPWM_GEN2_CFG0_GEN2_T0_SEL_Pos = 0x4 + // Bit mask of GEN2_T0_SEL field. + MCPWM_GEN2_CFG0_GEN2_T0_SEL_Msk = 0x70 + // Position of GEN2_T1_SEL field. + MCPWM_GEN2_CFG0_GEN2_T1_SEL_Pos = 0x7 + // Bit mask of GEN2_T1_SEL field. + MCPWM_GEN2_CFG0_GEN2_T1_SEL_Msk = 0x380 + + // GEN2_FORCE + // Position of GEN2_CNTUFORCE_UPMETHOD field. + MCPWM_GEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN2_CNTUFORCE_UPMETHOD field. + MCPWM_GEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN2_A_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN2_A_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN2_B_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN2_B_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN2_A_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN2_A_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_Msk = 0x400 + // Bit GEN2_A_NCIFORCE. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE = 0x400 + // Position of GEN2_A_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN2_A_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN2_B_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN2_B_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_Msk = 0x2000 + // Bit GEN2_B_NCIFORCE. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE = 0x2000 + // Position of GEN2_B_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN2_B_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN2_A + // Position of UTEZ field. + MCPWM_GEN2_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN2_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN2_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN2_A_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN2_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN2_A_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN2_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN2_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN2_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN2_A_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN2_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN2_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN2_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN2_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN2_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN2_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN2_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN2_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN2_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN2_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN2_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN2_A_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN2_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN2_A_DT1_Msk = 0xc00000 + + // GEN2_B + // Position of UTEZ field. + MCPWM_GEN2_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN2_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN2_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN2_B_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN2_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN2_B_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN2_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN2_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN2_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN2_B_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN2_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN2_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN2_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN2_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN2_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN2_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN2_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN2_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN2_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN2_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN2_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN2_B_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN2_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN2_B_DT1_Msk = 0xc00000 + + // DT2_CFG + // Position of DT2_FED_UPMETHOD field. + MCPWM_DT2_CFG_DT2_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DT2_FED_UPMETHOD field. + MCPWM_DT2_CFG_DT2_FED_UPMETHOD_Msk = 0xf + // Position of DT2_RED_UPMETHOD field. + MCPWM_DT2_CFG_DT2_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DT2_RED_UPMETHOD field. + MCPWM_DT2_CFG_DT2_RED_UPMETHOD_Msk = 0xf0 + // Position of DT2_DEB_MODE field. + MCPWM_DT2_CFG_DT2_DEB_MODE_Pos = 0x8 + // Bit mask of DT2_DEB_MODE field. + MCPWM_DT2_CFG_DT2_DEB_MODE_Msk = 0x100 + // Bit DT2_DEB_MODE. + MCPWM_DT2_CFG_DT2_DEB_MODE = 0x100 + // Position of DT2_A_OUTSWAP field. + MCPWM_DT2_CFG_DT2_A_OUTSWAP_Pos = 0x9 + // Bit mask of DT2_A_OUTSWAP field. + MCPWM_DT2_CFG_DT2_A_OUTSWAP_Msk = 0x200 + // Bit DT2_A_OUTSWAP. + MCPWM_DT2_CFG_DT2_A_OUTSWAP = 0x200 + // Position of DT2_B_OUTSWAP field. + MCPWM_DT2_CFG_DT2_B_OUTSWAP_Pos = 0xa + // Bit mask of DT2_B_OUTSWAP field. + MCPWM_DT2_CFG_DT2_B_OUTSWAP_Msk = 0x400 + // Bit DT2_B_OUTSWAP. + MCPWM_DT2_CFG_DT2_B_OUTSWAP = 0x400 + // Position of DT2_RED_INSEL field. + MCPWM_DT2_CFG_DT2_RED_INSEL_Pos = 0xb + // Bit mask of DT2_RED_INSEL field. + MCPWM_DT2_CFG_DT2_RED_INSEL_Msk = 0x800 + // Bit DT2_RED_INSEL. + MCPWM_DT2_CFG_DT2_RED_INSEL = 0x800 + // Position of DT2_FED_INSEL field. + MCPWM_DT2_CFG_DT2_FED_INSEL_Pos = 0xc + // Bit mask of DT2_FED_INSEL field. + MCPWM_DT2_CFG_DT2_FED_INSEL_Msk = 0x1000 + // Bit DT2_FED_INSEL. + MCPWM_DT2_CFG_DT2_FED_INSEL = 0x1000 + // Position of DT2_RED_OUTINVERT field. + MCPWM_DT2_CFG_DT2_RED_OUTINVERT_Pos = 0xd + // Bit mask of DT2_RED_OUTINVERT field. + MCPWM_DT2_CFG_DT2_RED_OUTINVERT_Msk = 0x2000 + // Bit DT2_RED_OUTINVERT. + MCPWM_DT2_CFG_DT2_RED_OUTINVERT = 0x2000 + // Position of DT2_FED_OUTINVERT field. + MCPWM_DT2_CFG_DT2_FED_OUTINVERT_Pos = 0xe + // Bit mask of DT2_FED_OUTINVERT field. + MCPWM_DT2_CFG_DT2_FED_OUTINVERT_Msk = 0x4000 + // Bit DT2_FED_OUTINVERT. + MCPWM_DT2_CFG_DT2_FED_OUTINVERT = 0x4000 + // Position of DT2_A_OUTBYPASS field. + MCPWM_DT2_CFG_DT2_A_OUTBYPASS_Pos = 0xf + // Bit mask of DT2_A_OUTBYPASS field. + MCPWM_DT2_CFG_DT2_A_OUTBYPASS_Msk = 0x8000 + // Bit DT2_A_OUTBYPASS. + MCPWM_DT2_CFG_DT2_A_OUTBYPASS = 0x8000 + // Position of DT2_B_OUTBYPASS field. + MCPWM_DT2_CFG_DT2_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DT2_B_OUTBYPASS field. + MCPWM_DT2_CFG_DT2_B_OUTBYPASS_Msk = 0x10000 + // Bit DT2_B_OUTBYPASS. + MCPWM_DT2_CFG_DT2_B_OUTBYPASS = 0x10000 + // Position of DT2_CLK_SEL field. + MCPWM_DT2_CFG_DT2_CLK_SEL_Pos = 0x11 + // Bit mask of DT2_CLK_SEL field. + MCPWM_DT2_CFG_DT2_CLK_SEL_Msk = 0x20000 + // Bit DT2_CLK_SEL. + MCPWM_DT2_CFG_DT2_CLK_SEL = 0x20000 + + // DT2_FED_CFG + // Position of DT2_FED field. + MCPWM_DT2_FED_CFG_DT2_FED_Pos = 0x0 + // Bit mask of DT2_FED field. + MCPWM_DT2_FED_CFG_DT2_FED_Msk = 0xffff + + // DT2_RED_CFG + // Position of DT2_RED field. + MCPWM_DT2_RED_CFG_DT2_RED_Pos = 0x0 + // Bit mask of DT2_RED field. + MCPWM_DT2_RED_CFG_DT2_RED_Msk = 0xffff + + // CARRIER2_CFG + // Position of CARRIER2_EN field. + MCPWM_CARRIER2_CFG_CARRIER2_EN_Pos = 0x0 + // Bit mask of CARRIER2_EN field. + MCPWM_CARRIER2_CFG_CARRIER2_EN_Msk = 0x1 + // Bit CARRIER2_EN. + MCPWM_CARRIER2_CFG_CARRIER2_EN = 0x1 + // Position of CARRIER2_PRESCALE field. + MCPWM_CARRIER2_CFG_CARRIER2_PRESCALE_Pos = 0x1 + // Bit mask of CARRIER2_PRESCALE field. + MCPWM_CARRIER2_CFG_CARRIER2_PRESCALE_Msk = 0x1e + // Position of CARRIER2_DUTY field. + MCPWM_CARRIER2_CFG_CARRIER2_DUTY_Pos = 0x5 + // Bit mask of CARRIER2_DUTY field. + MCPWM_CARRIER2_CFG_CARRIER2_DUTY_Msk = 0xe0 + // Position of CARRIER2_OSHTWTH field. + MCPWM_CARRIER2_CFG_CARRIER2_OSHTWTH_Pos = 0x8 + // Bit mask of CARRIER2_OSHTWTH field. + MCPWM_CARRIER2_CFG_CARRIER2_OSHTWTH_Msk = 0xf00 + // Position of CARRIER2_OUT_INVERT field. + MCPWM_CARRIER2_CFG_CARRIER2_OUT_INVERT_Pos = 0xc + // Bit mask of CARRIER2_OUT_INVERT field. + MCPWM_CARRIER2_CFG_CARRIER2_OUT_INVERT_Msk = 0x1000 + // Bit CARRIER2_OUT_INVERT. + MCPWM_CARRIER2_CFG_CARRIER2_OUT_INVERT = 0x1000 + // Position of CARRIER2_IN_INVERT field. + MCPWM_CARRIER2_CFG_CARRIER2_IN_INVERT_Pos = 0xd + // Bit mask of CARRIER2_IN_INVERT field. + MCPWM_CARRIER2_CFG_CARRIER2_IN_INVERT_Msk = 0x2000 + // Bit CARRIER2_IN_INVERT. + MCPWM_CARRIER2_CFG_CARRIER2_IN_INVERT = 0x2000 + + // FH2_CFG0 + // Position of FH2_SW_CBC field. + MCPWM_FH2_CFG0_FH2_SW_CBC_Pos = 0x0 + // Bit mask of FH2_SW_CBC field. + MCPWM_FH2_CFG0_FH2_SW_CBC_Msk = 0x1 + // Bit FH2_SW_CBC. + MCPWM_FH2_CFG0_FH2_SW_CBC = 0x1 + // Position of FH2_F2_CBC field. + MCPWM_FH2_CFG0_FH2_F2_CBC_Pos = 0x1 + // Bit mask of FH2_F2_CBC field. + MCPWM_FH2_CFG0_FH2_F2_CBC_Msk = 0x2 + // Bit FH2_F2_CBC. + MCPWM_FH2_CFG0_FH2_F2_CBC = 0x2 + // Position of FH2_F1_CBC field. + MCPWM_FH2_CFG0_FH2_F1_CBC_Pos = 0x2 + // Bit mask of FH2_F1_CBC field. + MCPWM_FH2_CFG0_FH2_F1_CBC_Msk = 0x4 + // Bit FH2_F1_CBC. + MCPWM_FH2_CFG0_FH2_F1_CBC = 0x4 + // Position of FH2_F0_CBC field. + MCPWM_FH2_CFG0_FH2_F0_CBC_Pos = 0x3 + // Bit mask of FH2_F0_CBC field. + MCPWM_FH2_CFG0_FH2_F0_CBC_Msk = 0x8 + // Bit FH2_F0_CBC. + MCPWM_FH2_CFG0_FH2_F0_CBC = 0x8 + // Position of FH2_SW_OST field. + MCPWM_FH2_CFG0_FH2_SW_OST_Pos = 0x4 + // Bit mask of FH2_SW_OST field. + MCPWM_FH2_CFG0_FH2_SW_OST_Msk = 0x10 + // Bit FH2_SW_OST. + MCPWM_FH2_CFG0_FH2_SW_OST = 0x10 + // Position of FH2_F2_OST field. + MCPWM_FH2_CFG0_FH2_F2_OST_Pos = 0x5 + // Bit mask of FH2_F2_OST field. + MCPWM_FH2_CFG0_FH2_F2_OST_Msk = 0x20 + // Bit FH2_F2_OST. + MCPWM_FH2_CFG0_FH2_F2_OST = 0x20 + // Position of FH2_F1_OST field. + MCPWM_FH2_CFG0_FH2_F1_OST_Pos = 0x6 + // Bit mask of FH2_F1_OST field. + MCPWM_FH2_CFG0_FH2_F1_OST_Msk = 0x40 + // Bit FH2_F1_OST. + MCPWM_FH2_CFG0_FH2_F1_OST = 0x40 + // Position of FH2_F0_OST field. + MCPWM_FH2_CFG0_FH2_F0_OST_Pos = 0x7 + // Bit mask of FH2_F0_OST field. + MCPWM_FH2_CFG0_FH2_F0_OST_Msk = 0x80 + // Bit FH2_F0_OST. + MCPWM_FH2_CFG0_FH2_F0_OST = 0x80 + // Position of FH2_A_CBC_D field. + MCPWM_FH2_CFG0_FH2_A_CBC_D_Pos = 0x8 + // Bit mask of FH2_A_CBC_D field. + MCPWM_FH2_CFG0_FH2_A_CBC_D_Msk = 0x300 + // Position of FH2_A_CBC_U field. + MCPWM_FH2_CFG0_FH2_A_CBC_U_Pos = 0xa + // Bit mask of FH2_A_CBC_U field. + MCPWM_FH2_CFG0_FH2_A_CBC_U_Msk = 0xc00 + // Position of FH2_A_OST_D field. + MCPWM_FH2_CFG0_FH2_A_OST_D_Pos = 0xc + // Bit mask of FH2_A_OST_D field. + MCPWM_FH2_CFG0_FH2_A_OST_D_Msk = 0x3000 + // Position of FH2_A_OST_U field. + MCPWM_FH2_CFG0_FH2_A_OST_U_Pos = 0xe + // Bit mask of FH2_A_OST_U field. + MCPWM_FH2_CFG0_FH2_A_OST_U_Msk = 0xc000 + // Position of FH2_B_CBC_D field. + MCPWM_FH2_CFG0_FH2_B_CBC_D_Pos = 0x10 + // Bit mask of FH2_B_CBC_D field. + MCPWM_FH2_CFG0_FH2_B_CBC_D_Msk = 0x30000 + // Position of FH2_B_CBC_U field. + MCPWM_FH2_CFG0_FH2_B_CBC_U_Pos = 0x12 + // Bit mask of FH2_B_CBC_U field. + MCPWM_FH2_CFG0_FH2_B_CBC_U_Msk = 0xc0000 + // Position of FH2_B_OST_D field. + MCPWM_FH2_CFG0_FH2_B_OST_D_Pos = 0x14 + // Bit mask of FH2_B_OST_D field. + MCPWM_FH2_CFG0_FH2_B_OST_D_Msk = 0x300000 + // Position of FH2_B_OST_U field. + MCPWM_FH2_CFG0_FH2_B_OST_U_Pos = 0x16 + // Bit mask of FH2_B_OST_U field. + MCPWM_FH2_CFG0_FH2_B_OST_U_Msk = 0xc00000 + + // FH2_CFG1 + // Position of FH2_CLR_OST field. + MCPWM_FH2_CFG1_FH2_CLR_OST_Pos = 0x0 + // Bit mask of FH2_CLR_OST field. + MCPWM_FH2_CFG1_FH2_CLR_OST_Msk = 0x1 + // Bit FH2_CLR_OST. + MCPWM_FH2_CFG1_FH2_CLR_OST = 0x1 + // Position of FH2_CBCPULSE field. + MCPWM_FH2_CFG1_FH2_CBCPULSE_Pos = 0x1 + // Bit mask of FH2_CBCPULSE field. + MCPWM_FH2_CFG1_FH2_CBCPULSE_Msk = 0x6 + // Position of FH2_FORCE_CBC field. + MCPWM_FH2_CFG1_FH2_FORCE_CBC_Pos = 0x3 + // Bit mask of FH2_FORCE_CBC field. + MCPWM_FH2_CFG1_FH2_FORCE_CBC_Msk = 0x8 + // Bit FH2_FORCE_CBC. + MCPWM_FH2_CFG1_FH2_FORCE_CBC = 0x8 + // Position of FH2_FORCE_OST field. + MCPWM_FH2_CFG1_FH2_FORCE_OST_Pos = 0x4 + // Bit mask of FH2_FORCE_OST field. + MCPWM_FH2_CFG1_FH2_FORCE_OST_Msk = 0x10 + // Bit FH2_FORCE_OST. + MCPWM_FH2_CFG1_FH2_FORCE_OST = 0x10 + + // FH2_STATUS + // Position of FH2_CBC_ON field. + MCPWM_FH2_STATUS_FH2_CBC_ON_Pos = 0x0 + // Bit mask of FH2_CBC_ON field. + MCPWM_FH2_STATUS_FH2_CBC_ON_Msk = 0x1 + // Bit FH2_CBC_ON. + MCPWM_FH2_STATUS_FH2_CBC_ON = 0x1 + // Position of FH2_OST_ON field. + MCPWM_FH2_STATUS_FH2_OST_ON_Pos = 0x1 + // Bit mask of FH2_OST_ON field. + MCPWM_FH2_STATUS_FH2_OST_ON_Msk = 0x2 + // Bit FH2_OST_ON. + MCPWM_FH2_STATUS_FH2_OST_ON = 0x2 + + // FAULT_DETECT + // Position of F0_EN field. + MCPWM_FAULT_DETECT_F0_EN_Pos = 0x0 + // Bit mask of F0_EN field. + MCPWM_FAULT_DETECT_F0_EN_Msk = 0x1 + // Bit F0_EN. + MCPWM_FAULT_DETECT_F0_EN = 0x1 + // Position of F1_EN field. + MCPWM_FAULT_DETECT_F1_EN_Pos = 0x1 + // Bit mask of F1_EN field. + MCPWM_FAULT_DETECT_F1_EN_Msk = 0x2 + // Bit F1_EN. + MCPWM_FAULT_DETECT_F1_EN = 0x2 + // Position of F2_EN field. + MCPWM_FAULT_DETECT_F2_EN_Pos = 0x2 + // Bit mask of F2_EN field. + MCPWM_FAULT_DETECT_F2_EN_Msk = 0x4 + // Bit F2_EN. + MCPWM_FAULT_DETECT_F2_EN = 0x4 + // Position of F0_POLE field. + MCPWM_FAULT_DETECT_F0_POLE_Pos = 0x3 + // Bit mask of F0_POLE field. + MCPWM_FAULT_DETECT_F0_POLE_Msk = 0x8 + // Bit F0_POLE. + MCPWM_FAULT_DETECT_F0_POLE = 0x8 + // Position of F1_POLE field. + MCPWM_FAULT_DETECT_F1_POLE_Pos = 0x4 + // Bit mask of F1_POLE field. + MCPWM_FAULT_DETECT_F1_POLE_Msk = 0x10 + // Bit F1_POLE. + MCPWM_FAULT_DETECT_F1_POLE = 0x10 + // Position of F2_POLE field. + MCPWM_FAULT_DETECT_F2_POLE_Pos = 0x5 + // Bit mask of F2_POLE field. + MCPWM_FAULT_DETECT_F2_POLE_Msk = 0x20 + // Bit F2_POLE. + MCPWM_FAULT_DETECT_F2_POLE = 0x20 + // Position of EVENT_F0 field. + MCPWM_FAULT_DETECT_EVENT_F0_Pos = 0x6 + // Bit mask of EVENT_F0 field. + MCPWM_FAULT_DETECT_EVENT_F0_Msk = 0x40 + // Bit EVENT_F0. + MCPWM_FAULT_DETECT_EVENT_F0 = 0x40 + // Position of EVENT_F1 field. + MCPWM_FAULT_DETECT_EVENT_F1_Pos = 0x7 + // Bit mask of EVENT_F1 field. + MCPWM_FAULT_DETECT_EVENT_F1_Msk = 0x80 + // Bit EVENT_F1. + MCPWM_FAULT_DETECT_EVENT_F1 = 0x80 + // Position of EVENT_F2 field. + MCPWM_FAULT_DETECT_EVENT_F2_Pos = 0x8 + // Bit mask of EVENT_F2 field. + MCPWM_FAULT_DETECT_EVENT_F2_Msk = 0x100 + // Bit EVENT_F2. + MCPWM_FAULT_DETECT_EVENT_F2 = 0x100 + + // CAP_TIMER_CFG + // Position of CAP_TIMER_EN field. + MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN_Pos = 0x0 + // Bit mask of CAP_TIMER_EN field. + MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN_Msk = 0x1 + // Bit CAP_TIMER_EN. + MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN = 0x1 + // Position of CAP_SYNCI_EN field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Pos = 0x1 + // Bit mask of CAP_SYNCI_EN field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Msk = 0x2 + // Bit CAP_SYNCI_EN. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN = 0x2 + // Position of CAP_SYNCI_SEL field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Pos = 0x2 + // Bit mask of CAP_SYNCI_SEL field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Msk = 0x1c + // Position of CAP_SYNC_SW field. + MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW_Pos = 0x5 + // Bit mask of CAP_SYNC_SW field. + MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW_Msk = 0x20 + // Bit CAP_SYNC_SW. + MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW = 0x20 + + // CAP_TIMER_PHASE + // Position of CAP_TIMER_PHASE field. + MCPWM_CAP_TIMER_PHASE_CAP_TIMER_PHASE_Pos = 0x0 + // Bit mask of CAP_TIMER_PHASE field. + MCPWM_CAP_TIMER_PHASE_CAP_TIMER_PHASE_Msk = 0xffffffff + + // CAP_CH0_CFG + // Position of CAP0_EN field. + MCPWM_CAP_CH0_CFG_CAP0_EN_Pos = 0x0 + // Bit mask of CAP0_EN field. + MCPWM_CAP_CH0_CFG_CAP0_EN_Msk = 0x1 + // Bit CAP0_EN. + MCPWM_CAP_CH0_CFG_CAP0_EN = 0x1 + // Position of CAP0_MODE field. + MCPWM_CAP_CH0_CFG_CAP0_MODE_Pos = 0x1 + // Bit mask of CAP0_MODE field. + MCPWM_CAP_CH0_CFG_CAP0_MODE_Msk = 0x6 + // Position of CAP0_PRESCALE field. + MCPWM_CAP_CH0_CFG_CAP0_PRESCALE_Pos = 0x3 + // Bit mask of CAP0_PRESCALE field. + MCPWM_CAP_CH0_CFG_CAP0_PRESCALE_Msk = 0x7f8 + // Position of CAP0_IN_INVERT field. + MCPWM_CAP_CH0_CFG_CAP0_IN_INVERT_Pos = 0xb + // Bit mask of CAP0_IN_INVERT field. + MCPWM_CAP_CH0_CFG_CAP0_IN_INVERT_Msk = 0x800 + // Bit CAP0_IN_INVERT. + MCPWM_CAP_CH0_CFG_CAP0_IN_INVERT = 0x800 + // Position of CAP0_SW field. + MCPWM_CAP_CH0_CFG_CAP0_SW_Pos = 0xc + // Bit mask of CAP0_SW field. + MCPWM_CAP_CH0_CFG_CAP0_SW_Msk = 0x1000 + // Bit CAP0_SW. + MCPWM_CAP_CH0_CFG_CAP0_SW = 0x1000 + + // CAP_CH1_CFG + // Position of CAP1_EN field. + MCPWM_CAP_CH1_CFG_CAP1_EN_Pos = 0x0 + // Bit mask of CAP1_EN field. + MCPWM_CAP_CH1_CFG_CAP1_EN_Msk = 0x1 + // Bit CAP1_EN. + MCPWM_CAP_CH1_CFG_CAP1_EN = 0x1 + // Position of CAP1_MODE field. + MCPWM_CAP_CH1_CFG_CAP1_MODE_Pos = 0x1 + // Bit mask of CAP1_MODE field. + MCPWM_CAP_CH1_CFG_CAP1_MODE_Msk = 0x6 + // Position of CAP1_PRESCALE field. + MCPWM_CAP_CH1_CFG_CAP1_PRESCALE_Pos = 0x3 + // Bit mask of CAP1_PRESCALE field. + MCPWM_CAP_CH1_CFG_CAP1_PRESCALE_Msk = 0x7f8 + // Position of CAP1_IN_INVERT field. + MCPWM_CAP_CH1_CFG_CAP1_IN_INVERT_Pos = 0xb + // Bit mask of CAP1_IN_INVERT field. + MCPWM_CAP_CH1_CFG_CAP1_IN_INVERT_Msk = 0x800 + // Bit CAP1_IN_INVERT. + MCPWM_CAP_CH1_CFG_CAP1_IN_INVERT = 0x800 + // Position of CAP1_SW field. + MCPWM_CAP_CH1_CFG_CAP1_SW_Pos = 0xc + // Bit mask of CAP1_SW field. + MCPWM_CAP_CH1_CFG_CAP1_SW_Msk = 0x1000 + // Bit CAP1_SW. + MCPWM_CAP_CH1_CFG_CAP1_SW = 0x1000 + + // CAP_CH2_CFG + // Position of CAP2_EN field. + MCPWM_CAP_CH2_CFG_CAP2_EN_Pos = 0x0 + // Bit mask of CAP2_EN field. + MCPWM_CAP_CH2_CFG_CAP2_EN_Msk = 0x1 + // Bit CAP2_EN. + MCPWM_CAP_CH2_CFG_CAP2_EN = 0x1 + // Position of CAP2_MODE field. + MCPWM_CAP_CH2_CFG_CAP2_MODE_Pos = 0x1 + // Bit mask of CAP2_MODE field. + MCPWM_CAP_CH2_CFG_CAP2_MODE_Msk = 0x6 + // Position of CAP2_PRESCALE field. + MCPWM_CAP_CH2_CFG_CAP2_PRESCALE_Pos = 0x3 + // Bit mask of CAP2_PRESCALE field. + MCPWM_CAP_CH2_CFG_CAP2_PRESCALE_Msk = 0x7f8 + // Position of CAP2_IN_INVERT field. + MCPWM_CAP_CH2_CFG_CAP2_IN_INVERT_Pos = 0xb + // Bit mask of CAP2_IN_INVERT field. + MCPWM_CAP_CH2_CFG_CAP2_IN_INVERT_Msk = 0x800 + // Bit CAP2_IN_INVERT. + MCPWM_CAP_CH2_CFG_CAP2_IN_INVERT = 0x800 + // Position of CAP2_SW field. + MCPWM_CAP_CH2_CFG_CAP2_SW_Pos = 0xc + // Bit mask of CAP2_SW field. + MCPWM_CAP_CH2_CFG_CAP2_SW_Msk = 0x1000 + // Bit CAP2_SW. + MCPWM_CAP_CH2_CFG_CAP2_SW = 0x1000 + + // CAP_CH0 + // Position of CAP0_VALUE field. + MCPWM_CAP_CH0_CAP0_VALUE_Pos = 0x0 + // Bit mask of CAP0_VALUE field. + MCPWM_CAP_CH0_CAP0_VALUE_Msk = 0xffffffff + + // CAP_CH1 + // Position of CAP1_VALUE field. + MCPWM_CAP_CH1_CAP1_VALUE_Pos = 0x0 + // Bit mask of CAP1_VALUE field. + MCPWM_CAP_CH1_CAP1_VALUE_Msk = 0xffffffff + + // CAP_CH2 + // Position of CAP2_VALUE field. + MCPWM_CAP_CH2_CAP2_VALUE_Pos = 0x0 + // Bit mask of CAP2_VALUE field. + MCPWM_CAP_CH2_CAP2_VALUE_Msk = 0xffffffff + + // CAP_STATUS + // Position of CAP0_EDGE field. + MCPWM_CAP_STATUS_CAP0_EDGE_Pos = 0x0 + // Bit mask of CAP0_EDGE field. + MCPWM_CAP_STATUS_CAP0_EDGE_Msk = 0x1 + // Bit CAP0_EDGE. + MCPWM_CAP_STATUS_CAP0_EDGE = 0x1 + // Position of CAP1_EDGE field. + MCPWM_CAP_STATUS_CAP1_EDGE_Pos = 0x1 + // Bit mask of CAP1_EDGE field. + MCPWM_CAP_STATUS_CAP1_EDGE_Msk = 0x2 + // Bit CAP1_EDGE. + MCPWM_CAP_STATUS_CAP1_EDGE = 0x2 + // Position of CAP2_EDGE field. + MCPWM_CAP_STATUS_CAP2_EDGE_Pos = 0x2 + // Bit mask of CAP2_EDGE field. + MCPWM_CAP_STATUS_CAP2_EDGE_Msk = 0x4 + // Bit CAP2_EDGE. + MCPWM_CAP_STATUS_CAP2_EDGE = 0x4 + + // UPDATE_CFG + // Position of GLOBAL_UP_EN field. + MCPWM_UPDATE_CFG_GLOBAL_UP_EN_Pos = 0x0 + // Bit mask of GLOBAL_UP_EN field. + MCPWM_UPDATE_CFG_GLOBAL_UP_EN_Msk = 0x1 + // Bit GLOBAL_UP_EN. + MCPWM_UPDATE_CFG_GLOBAL_UP_EN = 0x1 + // Position of GLOBAL_FORCE_UP field. + MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP_Pos = 0x1 + // Bit mask of GLOBAL_FORCE_UP field. + MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP_Msk = 0x2 + // Bit GLOBAL_FORCE_UP. + MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP = 0x2 + // Position of OP0_UP_EN field. + MCPWM_UPDATE_CFG_OP0_UP_EN_Pos = 0x2 + // Bit mask of OP0_UP_EN field. + MCPWM_UPDATE_CFG_OP0_UP_EN_Msk = 0x4 + // Bit OP0_UP_EN. + MCPWM_UPDATE_CFG_OP0_UP_EN = 0x4 + // Position of OP0_FORCE_UP field. + MCPWM_UPDATE_CFG_OP0_FORCE_UP_Pos = 0x3 + // Bit mask of OP0_FORCE_UP field. + MCPWM_UPDATE_CFG_OP0_FORCE_UP_Msk = 0x8 + // Bit OP0_FORCE_UP. + MCPWM_UPDATE_CFG_OP0_FORCE_UP = 0x8 + // Position of OP1_UP_EN field. + MCPWM_UPDATE_CFG_OP1_UP_EN_Pos = 0x4 + // Bit mask of OP1_UP_EN field. + MCPWM_UPDATE_CFG_OP1_UP_EN_Msk = 0x10 + // Bit OP1_UP_EN. + MCPWM_UPDATE_CFG_OP1_UP_EN = 0x10 + // Position of OP1_FORCE_UP field. + MCPWM_UPDATE_CFG_OP1_FORCE_UP_Pos = 0x5 + // Bit mask of OP1_FORCE_UP field. + MCPWM_UPDATE_CFG_OP1_FORCE_UP_Msk = 0x20 + // Bit OP1_FORCE_UP. + MCPWM_UPDATE_CFG_OP1_FORCE_UP = 0x20 + // Position of OP2_UP_EN field. + MCPWM_UPDATE_CFG_OP2_UP_EN_Pos = 0x6 + // Bit mask of OP2_UP_EN field. + MCPWM_UPDATE_CFG_OP2_UP_EN_Msk = 0x40 + // Bit OP2_UP_EN. + MCPWM_UPDATE_CFG_OP2_UP_EN = 0x40 + // Position of OP2_FORCE_UP field. + MCPWM_UPDATE_CFG_OP2_FORCE_UP_Pos = 0x7 + // Bit mask of OP2_FORCE_UP field. + MCPWM_UPDATE_CFG_OP2_FORCE_UP_Msk = 0x80 + // Bit OP2_FORCE_UP. + MCPWM_UPDATE_CFG_OP2_FORCE_UP = 0x80 + + // INT_ENA + // Position of TIMER0_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_STOP_INT_ENA_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_STOP_INT_ENA_Msk = 0x1 + // Bit TIMER0_STOP_INT_ENA. + MCPWM_INT_ENA_TIMER0_STOP_INT_ENA = 0x1 + // Position of TIMER1_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_STOP_INT_ENA_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_STOP_INT_ENA_Msk = 0x2 + // Bit TIMER1_STOP_INT_ENA. + MCPWM_INT_ENA_TIMER1_STOP_INT_ENA = 0x2 + // Position of TIMER2_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_STOP_INT_ENA_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_STOP_INT_ENA_Msk = 0x4 + // Bit TIMER2_STOP_INT_ENA. + MCPWM_INT_ENA_TIMER2_STOP_INT_ENA = 0x4 + // Position of TIMER0_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA_Msk = 0x8 + // Bit TIMER0_TEZ_INT_ENA. + MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA = 0x8 + // Position of TIMER1_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA_Msk = 0x10 + // Bit TIMER1_TEZ_INT_ENA. + MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA = 0x10 + // Position of TIMER2_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA_Msk = 0x20 + // Bit TIMER2_TEZ_INT_ENA. + MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA = 0x20 + // Position of TIMER0_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEP_INT_ENA_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEP_INT_ENA_Msk = 0x40 + // Bit TIMER0_TEP_INT_ENA. + MCPWM_INT_ENA_TIMER0_TEP_INT_ENA = 0x40 + // Position of TIMER1_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEP_INT_ENA_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEP_INT_ENA_Msk = 0x80 + // Bit TIMER1_TEP_INT_ENA. + MCPWM_INT_ENA_TIMER1_TEP_INT_ENA = 0x80 + // Position of TIMER2_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEP_INT_ENA_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEP_INT_ENA_Msk = 0x100 + // Bit TIMER2_TEP_INT_ENA. + MCPWM_INT_ENA_TIMER2_TEP_INT_ENA = 0x100 + // Position of FAULT0_INT_ENA field. + MCPWM_INT_ENA_FAULT0_INT_ENA_Pos = 0x9 + // Bit mask of FAULT0_INT_ENA field. + MCPWM_INT_ENA_FAULT0_INT_ENA_Msk = 0x200 + // Bit FAULT0_INT_ENA. + MCPWM_INT_ENA_FAULT0_INT_ENA = 0x200 + // Position of FAULT1_INT_ENA field. + MCPWM_INT_ENA_FAULT1_INT_ENA_Pos = 0xa + // Bit mask of FAULT1_INT_ENA field. + MCPWM_INT_ENA_FAULT1_INT_ENA_Msk = 0x400 + // Bit FAULT1_INT_ENA. + MCPWM_INT_ENA_FAULT1_INT_ENA = 0x400 + // Position of FAULT2_INT_ENA field. + MCPWM_INT_ENA_FAULT2_INT_ENA_Pos = 0xb + // Bit mask of FAULT2_INT_ENA field. + MCPWM_INT_ENA_FAULT2_INT_ENA_Msk = 0x800 + // Bit FAULT2_INT_ENA. + MCPWM_INT_ENA_FAULT2_INT_ENA = 0x800 + // Position of FAULT0_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT0_CLR_INT_ENA_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT0_CLR_INT_ENA_Msk = 0x1000 + // Bit FAULT0_CLR_INT_ENA. + MCPWM_INT_ENA_FAULT0_CLR_INT_ENA = 0x1000 + // Position of FAULT1_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT1_CLR_INT_ENA_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT1_CLR_INT_ENA_Msk = 0x2000 + // Bit FAULT1_CLR_INT_ENA. + MCPWM_INT_ENA_FAULT1_CLR_INT_ENA = 0x2000 + // Position of FAULT2_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT2_CLR_INT_ENA_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT2_CLR_INT_ENA_Msk = 0x4000 + // Bit FAULT2_CLR_INT_ENA. + MCPWM_INT_ENA_FAULT2_CLR_INT_ENA = 0x4000 + // Position of OP0_TEA_INT_ENA field. + MCPWM_INT_ENA_OP0_TEA_INT_ENA_Pos = 0xf + // Bit mask of OP0_TEA_INT_ENA field. + MCPWM_INT_ENA_OP0_TEA_INT_ENA_Msk = 0x8000 + // Bit OP0_TEA_INT_ENA. + MCPWM_INT_ENA_OP0_TEA_INT_ENA = 0x8000 + // Position of OP1_TEA_INT_ENA field. + MCPWM_INT_ENA_OP1_TEA_INT_ENA_Pos = 0x10 + // Bit mask of OP1_TEA_INT_ENA field. + MCPWM_INT_ENA_OP1_TEA_INT_ENA_Msk = 0x10000 + // Bit OP1_TEA_INT_ENA. + MCPWM_INT_ENA_OP1_TEA_INT_ENA = 0x10000 + // Position of OP2_TEA_INT_ENA field. + MCPWM_INT_ENA_OP2_TEA_INT_ENA_Pos = 0x11 + // Bit mask of OP2_TEA_INT_ENA field. + MCPWM_INT_ENA_OP2_TEA_INT_ENA_Msk = 0x20000 + // Bit OP2_TEA_INT_ENA. + MCPWM_INT_ENA_OP2_TEA_INT_ENA = 0x20000 + // Position of OP0_TEB_INT_ENA field. + MCPWM_INT_ENA_OP0_TEB_INT_ENA_Pos = 0x12 + // Bit mask of OP0_TEB_INT_ENA field. + MCPWM_INT_ENA_OP0_TEB_INT_ENA_Msk = 0x40000 + // Bit OP0_TEB_INT_ENA. + MCPWM_INT_ENA_OP0_TEB_INT_ENA = 0x40000 + // Position of OP1_TEB_INT_ENA field. + MCPWM_INT_ENA_OP1_TEB_INT_ENA_Pos = 0x13 + // Bit mask of OP1_TEB_INT_ENA field. + MCPWM_INT_ENA_OP1_TEB_INT_ENA_Msk = 0x80000 + // Bit OP1_TEB_INT_ENA. + MCPWM_INT_ENA_OP1_TEB_INT_ENA = 0x80000 + // Position of OP2_TEB_INT_ENA field. + MCPWM_INT_ENA_OP2_TEB_INT_ENA_Pos = 0x14 + // Bit mask of OP2_TEB_INT_ENA field. + MCPWM_INT_ENA_OP2_TEB_INT_ENA_Msk = 0x100000 + // Bit OP2_TEB_INT_ENA. + MCPWM_INT_ENA_OP2_TEB_INT_ENA = 0x100000 + // Position of FH0_CBC_INT_ENA field. + MCPWM_INT_ENA_FH0_CBC_INT_ENA_Pos = 0x15 + // Bit mask of FH0_CBC_INT_ENA field. + MCPWM_INT_ENA_FH0_CBC_INT_ENA_Msk = 0x200000 + // Bit FH0_CBC_INT_ENA. + MCPWM_INT_ENA_FH0_CBC_INT_ENA = 0x200000 + // Position of FH1_CBC_INT_ENA field. + MCPWM_INT_ENA_FH1_CBC_INT_ENA_Pos = 0x16 + // Bit mask of FH1_CBC_INT_ENA field. + MCPWM_INT_ENA_FH1_CBC_INT_ENA_Msk = 0x400000 + // Bit FH1_CBC_INT_ENA. + MCPWM_INT_ENA_FH1_CBC_INT_ENA = 0x400000 + // Position of FH2_CBC_INT_ENA field. + MCPWM_INT_ENA_FH2_CBC_INT_ENA_Pos = 0x17 + // Bit mask of FH2_CBC_INT_ENA field. + MCPWM_INT_ENA_FH2_CBC_INT_ENA_Msk = 0x800000 + // Bit FH2_CBC_INT_ENA. + MCPWM_INT_ENA_FH2_CBC_INT_ENA = 0x800000 + // Position of FH0_OST_INT_ENA field. + MCPWM_INT_ENA_FH0_OST_INT_ENA_Pos = 0x18 + // Bit mask of FH0_OST_INT_ENA field. + MCPWM_INT_ENA_FH0_OST_INT_ENA_Msk = 0x1000000 + // Bit FH0_OST_INT_ENA. + MCPWM_INT_ENA_FH0_OST_INT_ENA = 0x1000000 + // Position of FH1_OST_INT_ENA field. + MCPWM_INT_ENA_FH1_OST_INT_ENA_Pos = 0x19 + // Bit mask of FH1_OST_INT_ENA field. + MCPWM_INT_ENA_FH1_OST_INT_ENA_Msk = 0x2000000 + // Bit FH1_OST_INT_ENA. + MCPWM_INT_ENA_FH1_OST_INT_ENA = 0x2000000 + // Position of FH2_OST_INT_ENA field. + MCPWM_INT_ENA_FH2_OST_INT_ENA_Pos = 0x1a + // Bit mask of FH2_OST_INT_ENA field. + MCPWM_INT_ENA_FH2_OST_INT_ENA_Msk = 0x4000000 + // Bit FH2_OST_INT_ENA. + MCPWM_INT_ENA_FH2_OST_INT_ENA = 0x4000000 + // Position of CAP0_INT_ENA field. + MCPWM_INT_ENA_CAP0_INT_ENA_Pos = 0x1b + // Bit mask of CAP0_INT_ENA field. + MCPWM_INT_ENA_CAP0_INT_ENA_Msk = 0x8000000 + // Bit CAP0_INT_ENA. + MCPWM_INT_ENA_CAP0_INT_ENA = 0x8000000 + // Position of CAP1_INT_ENA field. + MCPWM_INT_ENA_CAP1_INT_ENA_Pos = 0x1c + // Bit mask of CAP1_INT_ENA field. + MCPWM_INT_ENA_CAP1_INT_ENA_Msk = 0x10000000 + // Bit CAP1_INT_ENA. + MCPWM_INT_ENA_CAP1_INT_ENA = 0x10000000 + // Position of CAP2_INT_ENA field. + MCPWM_INT_ENA_CAP2_INT_ENA_Pos = 0x1d + // Bit mask of CAP2_INT_ENA field. + MCPWM_INT_ENA_CAP2_INT_ENA_Msk = 0x20000000 + // Bit CAP2_INT_ENA. + MCPWM_INT_ENA_CAP2_INT_ENA = 0x20000000 + + // INT_RAW + // Position of TIMER0_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_STOP_INT_RAW_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_STOP_INT_RAW_Msk = 0x1 + // Bit TIMER0_STOP_INT_RAW. + MCPWM_INT_RAW_TIMER0_STOP_INT_RAW = 0x1 + // Position of TIMER1_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_STOP_INT_RAW_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_STOP_INT_RAW_Msk = 0x2 + // Bit TIMER1_STOP_INT_RAW. + MCPWM_INT_RAW_TIMER1_STOP_INT_RAW = 0x2 + // Position of TIMER2_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_STOP_INT_RAW_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_STOP_INT_RAW_Msk = 0x4 + // Bit TIMER2_STOP_INT_RAW. + MCPWM_INT_RAW_TIMER2_STOP_INT_RAW = 0x4 + // Position of TIMER0_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW_Msk = 0x8 + // Bit TIMER0_TEZ_INT_RAW. + MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW = 0x8 + // Position of TIMER1_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW_Msk = 0x10 + // Bit TIMER1_TEZ_INT_RAW. + MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW = 0x10 + // Position of TIMER2_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW_Msk = 0x20 + // Bit TIMER2_TEZ_INT_RAW. + MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW = 0x20 + // Position of TIMER0_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEP_INT_RAW_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEP_INT_RAW_Msk = 0x40 + // Bit TIMER0_TEP_INT_RAW. + MCPWM_INT_RAW_TIMER0_TEP_INT_RAW = 0x40 + // Position of TIMER1_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEP_INT_RAW_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEP_INT_RAW_Msk = 0x80 + // Bit TIMER1_TEP_INT_RAW. + MCPWM_INT_RAW_TIMER1_TEP_INT_RAW = 0x80 + // Position of TIMER2_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEP_INT_RAW_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEP_INT_RAW_Msk = 0x100 + // Bit TIMER2_TEP_INT_RAW. + MCPWM_INT_RAW_TIMER2_TEP_INT_RAW = 0x100 + // Position of FAULT0_INT_RAW field. + MCPWM_INT_RAW_FAULT0_INT_RAW_Pos = 0x9 + // Bit mask of FAULT0_INT_RAW field. + MCPWM_INT_RAW_FAULT0_INT_RAW_Msk = 0x200 + // Bit FAULT0_INT_RAW. + MCPWM_INT_RAW_FAULT0_INT_RAW = 0x200 + // Position of FAULT1_INT_RAW field. + MCPWM_INT_RAW_FAULT1_INT_RAW_Pos = 0xa + // Bit mask of FAULT1_INT_RAW field. + MCPWM_INT_RAW_FAULT1_INT_RAW_Msk = 0x400 + // Bit FAULT1_INT_RAW. + MCPWM_INT_RAW_FAULT1_INT_RAW = 0x400 + // Position of FAULT2_INT_RAW field. + MCPWM_INT_RAW_FAULT2_INT_RAW_Pos = 0xb + // Bit mask of FAULT2_INT_RAW field. + MCPWM_INT_RAW_FAULT2_INT_RAW_Msk = 0x800 + // Bit FAULT2_INT_RAW. + MCPWM_INT_RAW_FAULT2_INT_RAW = 0x800 + // Position of FAULT0_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT0_CLR_INT_RAW_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT0_CLR_INT_RAW_Msk = 0x1000 + // Bit FAULT0_CLR_INT_RAW. + MCPWM_INT_RAW_FAULT0_CLR_INT_RAW = 0x1000 + // Position of FAULT1_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT1_CLR_INT_RAW_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT1_CLR_INT_RAW_Msk = 0x2000 + // Bit FAULT1_CLR_INT_RAW. + MCPWM_INT_RAW_FAULT1_CLR_INT_RAW = 0x2000 + // Position of FAULT2_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT2_CLR_INT_RAW_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT2_CLR_INT_RAW_Msk = 0x4000 + // Bit FAULT2_CLR_INT_RAW. + MCPWM_INT_RAW_FAULT2_CLR_INT_RAW = 0x4000 + // Position of OP0_TEA_INT_RAW field. + MCPWM_INT_RAW_OP0_TEA_INT_RAW_Pos = 0xf + // Bit mask of OP0_TEA_INT_RAW field. + MCPWM_INT_RAW_OP0_TEA_INT_RAW_Msk = 0x8000 + // Bit OP0_TEA_INT_RAW. + MCPWM_INT_RAW_OP0_TEA_INT_RAW = 0x8000 + // Position of OP1_TEA_INT_RAW field. + MCPWM_INT_RAW_OP1_TEA_INT_RAW_Pos = 0x10 + // Bit mask of OP1_TEA_INT_RAW field. + MCPWM_INT_RAW_OP1_TEA_INT_RAW_Msk = 0x10000 + // Bit OP1_TEA_INT_RAW. + MCPWM_INT_RAW_OP1_TEA_INT_RAW = 0x10000 + // Position of OP2_TEA_INT_RAW field. + MCPWM_INT_RAW_OP2_TEA_INT_RAW_Pos = 0x11 + // Bit mask of OP2_TEA_INT_RAW field. + MCPWM_INT_RAW_OP2_TEA_INT_RAW_Msk = 0x20000 + // Bit OP2_TEA_INT_RAW. + MCPWM_INT_RAW_OP2_TEA_INT_RAW = 0x20000 + // Position of OP0_TEB_INT_RAW field. + MCPWM_INT_RAW_OP0_TEB_INT_RAW_Pos = 0x12 + // Bit mask of OP0_TEB_INT_RAW field. + MCPWM_INT_RAW_OP0_TEB_INT_RAW_Msk = 0x40000 + // Bit OP0_TEB_INT_RAW. + MCPWM_INT_RAW_OP0_TEB_INT_RAW = 0x40000 + // Position of OP1_TEB_INT_RAW field. + MCPWM_INT_RAW_OP1_TEB_INT_RAW_Pos = 0x13 + // Bit mask of OP1_TEB_INT_RAW field. + MCPWM_INT_RAW_OP1_TEB_INT_RAW_Msk = 0x80000 + // Bit OP1_TEB_INT_RAW. + MCPWM_INT_RAW_OP1_TEB_INT_RAW = 0x80000 + // Position of OP2_TEB_INT_RAW field. + MCPWM_INT_RAW_OP2_TEB_INT_RAW_Pos = 0x14 + // Bit mask of OP2_TEB_INT_RAW field. + MCPWM_INT_RAW_OP2_TEB_INT_RAW_Msk = 0x100000 + // Bit OP2_TEB_INT_RAW. + MCPWM_INT_RAW_OP2_TEB_INT_RAW = 0x100000 + // Position of FH0_CBC_INT_RAW field. + MCPWM_INT_RAW_FH0_CBC_INT_RAW_Pos = 0x15 + // Bit mask of FH0_CBC_INT_RAW field. + MCPWM_INT_RAW_FH0_CBC_INT_RAW_Msk = 0x200000 + // Bit FH0_CBC_INT_RAW. + MCPWM_INT_RAW_FH0_CBC_INT_RAW = 0x200000 + // Position of FH1_CBC_INT_RAW field. + MCPWM_INT_RAW_FH1_CBC_INT_RAW_Pos = 0x16 + // Bit mask of FH1_CBC_INT_RAW field. + MCPWM_INT_RAW_FH1_CBC_INT_RAW_Msk = 0x400000 + // Bit FH1_CBC_INT_RAW. + MCPWM_INT_RAW_FH1_CBC_INT_RAW = 0x400000 + // Position of FH2_CBC_INT_RAW field. + MCPWM_INT_RAW_FH2_CBC_INT_RAW_Pos = 0x17 + // Bit mask of FH2_CBC_INT_RAW field. + MCPWM_INT_RAW_FH2_CBC_INT_RAW_Msk = 0x800000 + // Bit FH2_CBC_INT_RAW. + MCPWM_INT_RAW_FH2_CBC_INT_RAW = 0x800000 + // Position of FH0_OST_INT_RAW field. + MCPWM_INT_RAW_FH0_OST_INT_RAW_Pos = 0x18 + // Bit mask of FH0_OST_INT_RAW field. + MCPWM_INT_RAW_FH0_OST_INT_RAW_Msk = 0x1000000 + // Bit FH0_OST_INT_RAW. + MCPWM_INT_RAW_FH0_OST_INT_RAW = 0x1000000 + // Position of FH1_OST_INT_RAW field. + MCPWM_INT_RAW_FH1_OST_INT_RAW_Pos = 0x19 + // Bit mask of FH1_OST_INT_RAW field. + MCPWM_INT_RAW_FH1_OST_INT_RAW_Msk = 0x2000000 + // Bit FH1_OST_INT_RAW. + MCPWM_INT_RAW_FH1_OST_INT_RAW = 0x2000000 + // Position of FH2_OST_INT_RAW field. + MCPWM_INT_RAW_FH2_OST_INT_RAW_Pos = 0x1a + // Bit mask of FH2_OST_INT_RAW field. + MCPWM_INT_RAW_FH2_OST_INT_RAW_Msk = 0x4000000 + // Bit FH2_OST_INT_RAW. + MCPWM_INT_RAW_FH2_OST_INT_RAW = 0x4000000 + // Position of CAP0_INT_RAW field. + MCPWM_INT_RAW_CAP0_INT_RAW_Pos = 0x1b + // Bit mask of CAP0_INT_RAW field. + MCPWM_INT_RAW_CAP0_INT_RAW_Msk = 0x8000000 + // Bit CAP0_INT_RAW. + MCPWM_INT_RAW_CAP0_INT_RAW = 0x8000000 + // Position of CAP1_INT_RAW field. + MCPWM_INT_RAW_CAP1_INT_RAW_Pos = 0x1c + // Bit mask of CAP1_INT_RAW field. + MCPWM_INT_RAW_CAP1_INT_RAW_Msk = 0x10000000 + // Bit CAP1_INT_RAW. + MCPWM_INT_RAW_CAP1_INT_RAW = 0x10000000 + // Position of CAP2_INT_RAW field. + MCPWM_INT_RAW_CAP2_INT_RAW_Pos = 0x1d + // Bit mask of CAP2_INT_RAW field. + MCPWM_INT_RAW_CAP2_INT_RAW_Msk = 0x20000000 + // Bit CAP2_INT_RAW. + MCPWM_INT_RAW_CAP2_INT_RAW = 0x20000000 + + // INT_ST + // Position of TIMER0_STOP_INT_ST field. + MCPWM_INT_ST_TIMER0_STOP_INT_ST_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_ST field. + MCPWM_INT_ST_TIMER0_STOP_INT_ST_Msk = 0x1 + // Bit TIMER0_STOP_INT_ST. + MCPWM_INT_ST_TIMER0_STOP_INT_ST = 0x1 + // Position of TIMER1_STOP_INT_ST field. + MCPWM_INT_ST_TIMER1_STOP_INT_ST_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_ST field. + MCPWM_INT_ST_TIMER1_STOP_INT_ST_Msk = 0x2 + // Bit TIMER1_STOP_INT_ST. + MCPWM_INT_ST_TIMER1_STOP_INT_ST = 0x2 + // Position of TIMER2_STOP_INT_ST field. + MCPWM_INT_ST_TIMER2_STOP_INT_ST_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_ST field. + MCPWM_INT_ST_TIMER2_STOP_INT_ST_Msk = 0x4 + // Bit TIMER2_STOP_INT_ST. + MCPWM_INT_ST_TIMER2_STOP_INT_ST = 0x4 + // Position of TIMER0_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER0_TEZ_INT_ST_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER0_TEZ_INT_ST_Msk = 0x8 + // Bit TIMER0_TEZ_INT_ST. + MCPWM_INT_ST_TIMER0_TEZ_INT_ST = 0x8 + // Position of TIMER1_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER1_TEZ_INT_ST_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER1_TEZ_INT_ST_Msk = 0x10 + // Bit TIMER1_TEZ_INT_ST. + MCPWM_INT_ST_TIMER1_TEZ_INT_ST = 0x10 + // Position of TIMER2_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER2_TEZ_INT_ST_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER2_TEZ_INT_ST_Msk = 0x20 + // Bit TIMER2_TEZ_INT_ST. + MCPWM_INT_ST_TIMER2_TEZ_INT_ST = 0x20 + // Position of TIMER0_TEP_INT_ST field. + MCPWM_INT_ST_TIMER0_TEP_INT_ST_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_ST field. + MCPWM_INT_ST_TIMER0_TEP_INT_ST_Msk = 0x40 + // Bit TIMER0_TEP_INT_ST. + MCPWM_INT_ST_TIMER0_TEP_INT_ST = 0x40 + // Position of TIMER1_TEP_INT_ST field. + MCPWM_INT_ST_TIMER1_TEP_INT_ST_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_ST field. + MCPWM_INT_ST_TIMER1_TEP_INT_ST_Msk = 0x80 + // Bit TIMER1_TEP_INT_ST. + MCPWM_INT_ST_TIMER1_TEP_INT_ST = 0x80 + // Position of TIMER2_TEP_INT_ST field. + MCPWM_INT_ST_TIMER2_TEP_INT_ST_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_ST field. + MCPWM_INT_ST_TIMER2_TEP_INT_ST_Msk = 0x100 + // Bit TIMER2_TEP_INT_ST. + MCPWM_INT_ST_TIMER2_TEP_INT_ST = 0x100 + // Position of FAULT0_INT_ST field. + MCPWM_INT_ST_FAULT0_INT_ST_Pos = 0x9 + // Bit mask of FAULT0_INT_ST field. + MCPWM_INT_ST_FAULT0_INT_ST_Msk = 0x200 + // Bit FAULT0_INT_ST. + MCPWM_INT_ST_FAULT0_INT_ST = 0x200 + // Position of FAULT1_INT_ST field. + MCPWM_INT_ST_FAULT1_INT_ST_Pos = 0xa + // Bit mask of FAULT1_INT_ST field. + MCPWM_INT_ST_FAULT1_INT_ST_Msk = 0x400 + // Bit FAULT1_INT_ST. + MCPWM_INT_ST_FAULT1_INT_ST = 0x400 + // Position of FAULT2_INT_ST field. + MCPWM_INT_ST_FAULT2_INT_ST_Pos = 0xb + // Bit mask of FAULT2_INT_ST field. + MCPWM_INT_ST_FAULT2_INT_ST_Msk = 0x800 + // Bit FAULT2_INT_ST. + MCPWM_INT_ST_FAULT2_INT_ST = 0x800 + // Position of FAULT0_CLR_INT_ST field. + MCPWM_INT_ST_FAULT0_CLR_INT_ST_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_ST field. + MCPWM_INT_ST_FAULT0_CLR_INT_ST_Msk = 0x1000 + // Bit FAULT0_CLR_INT_ST. + MCPWM_INT_ST_FAULT0_CLR_INT_ST = 0x1000 + // Position of FAULT1_CLR_INT_ST field. + MCPWM_INT_ST_FAULT1_CLR_INT_ST_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_ST field. + MCPWM_INT_ST_FAULT1_CLR_INT_ST_Msk = 0x2000 + // Bit FAULT1_CLR_INT_ST. + MCPWM_INT_ST_FAULT1_CLR_INT_ST = 0x2000 + // Position of FAULT2_CLR_INT_ST field. + MCPWM_INT_ST_FAULT2_CLR_INT_ST_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_ST field. + MCPWM_INT_ST_FAULT2_CLR_INT_ST_Msk = 0x4000 + // Bit FAULT2_CLR_INT_ST. + MCPWM_INT_ST_FAULT2_CLR_INT_ST = 0x4000 + // Position of OP0_TEA_INT_ST field. + MCPWM_INT_ST_OP0_TEA_INT_ST_Pos = 0xf + // Bit mask of OP0_TEA_INT_ST field. + MCPWM_INT_ST_OP0_TEA_INT_ST_Msk = 0x8000 + // Bit OP0_TEA_INT_ST. + MCPWM_INT_ST_OP0_TEA_INT_ST = 0x8000 + // Position of OP1_TEA_INT_ST field. + MCPWM_INT_ST_OP1_TEA_INT_ST_Pos = 0x10 + // Bit mask of OP1_TEA_INT_ST field. + MCPWM_INT_ST_OP1_TEA_INT_ST_Msk = 0x10000 + // Bit OP1_TEA_INT_ST. + MCPWM_INT_ST_OP1_TEA_INT_ST = 0x10000 + // Position of OP2_TEA_INT_ST field. + MCPWM_INT_ST_OP2_TEA_INT_ST_Pos = 0x11 + // Bit mask of OP2_TEA_INT_ST field. + MCPWM_INT_ST_OP2_TEA_INT_ST_Msk = 0x20000 + // Bit OP2_TEA_INT_ST. + MCPWM_INT_ST_OP2_TEA_INT_ST = 0x20000 + // Position of OP0_TEB_INT_ST field. + MCPWM_INT_ST_OP0_TEB_INT_ST_Pos = 0x12 + // Bit mask of OP0_TEB_INT_ST field. + MCPWM_INT_ST_OP0_TEB_INT_ST_Msk = 0x40000 + // Bit OP0_TEB_INT_ST. + MCPWM_INT_ST_OP0_TEB_INT_ST = 0x40000 + // Position of OP1_TEB_INT_ST field. + MCPWM_INT_ST_OP1_TEB_INT_ST_Pos = 0x13 + // Bit mask of OP1_TEB_INT_ST field. + MCPWM_INT_ST_OP1_TEB_INT_ST_Msk = 0x80000 + // Bit OP1_TEB_INT_ST. + MCPWM_INT_ST_OP1_TEB_INT_ST = 0x80000 + // Position of OP2_TEB_INT_ST field. + MCPWM_INT_ST_OP2_TEB_INT_ST_Pos = 0x14 + // Bit mask of OP2_TEB_INT_ST field. + MCPWM_INT_ST_OP2_TEB_INT_ST_Msk = 0x100000 + // Bit OP2_TEB_INT_ST. + MCPWM_INT_ST_OP2_TEB_INT_ST = 0x100000 + // Position of FH0_CBC_INT_ST field. + MCPWM_INT_ST_FH0_CBC_INT_ST_Pos = 0x15 + // Bit mask of FH0_CBC_INT_ST field. + MCPWM_INT_ST_FH0_CBC_INT_ST_Msk = 0x200000 + // Bit FH0_CBC_INT_ST. + MCPWM_INT_ST_FH0_CBC_INT_ST = 0x200000 + // Position of FH1_CBC_INT_ST field. + MCPWM_INT_ST_FH1_CBC_INT_ST_Pos = 0x16 + // Bit mask of FH1_CBC_INT_ST field. + MCPWM_INT_ST_FH1_CBC_INT_ST_Msk = 0x400000 + // Bit FH1_CBC_INT_ST. + MCPWM_INT_ST_FH1_CBC_INT_ST = 0x400000 + // Position of FH2_CBC_INT_ST field. + MCPWM_INT_ST_FH2_CBC_INT_ST_Pos = 0x17 + // Bit mask of FH2_CBC_INT_ST field. + MCPWM_INT_ST_FH2_CBC_INT_ST_Msk = 0x800000 + // Bit FH2_CBC_INT_ST. + MCPWM_INT_ST_FH2_CBC_INT_ST = 0x800000 + // Position of FH0_OST_INT_ST field. + MCPWM_INT_ST_FH0_OST_INT_ST_Pos = 0x18 + // Bit mask of FH0_OST_INT_ST field. + MCPWM_INT_ST_FH0_OST_INT_ST_Msk = 0x1000000 + // Bit FH0_OST_INT_ST. + MCPWM_INT_ST_FH0_OST_INT_ST = 0x1000000 + // Position of FH1_OST_INT_ST field. + MCPWM_INT_ST_FH1_OST_INT_ST_Pos = 0x19 + // Bit mask of FH1_OST_INT_ST field. + MCPWM_INT_ST_FH1_OST_INT_ST_Msk = 0x2000000 + // Bit FH1_OST_INT_ST. + MCPWM_INT_ST_FH1_OST_INT_ST = 0x2000000 + // Position of FH2_OST_INT_ST field. + MCPWM_INT_ST_FH2_OST_INT_ST_Pos = 0x1a + // Bit mask of FH2_OST_INT_ST field. + MCPWM_INT_ST_FH2_OST_INT_ST_Msk = 0x4000000 + // Bit FH2_OST_INT_ST. + MCPWM_INT_ST_FH2_OST_INT_ST = 0x4000000 + // Position of CAP0_INT_ST field. + MCPWM_INT_ST_CAP0_INT_ST_Pos = 0x1b + // Bit mask of CAP0_INT_ST field. + MCPWM_INT_ST_CAP0_INT_ST_Msk = 0x8000000 + // Bit CAP0_INT_ST. + MCPWM_INT_ST_CAP0_INT_ST = 0x8000000 + // Position of CAP1_INT_ST field. + MCPWM_INT_ST_CAP1_INT_ST_Pos = 0x1c + // Bit mask of CAP1_INT_ST field. + MCPWM_INT_ST_CAP1_INT_ST_Msk = 0x10000000 + // Bit CAP1_INT_ST. + MCPWM_INT_ST_CAP1_INT_ST = 0x10000000 + // Position of CAP2_INT_ST field. + MCPWM_INT_ST_CAP2_INT_ST_Pos = 0x1d + // Bit mask of CAP2_INT_ST field. + MCPWM_INT_ST_CAP2_INT_ST_Msk = 0x20000000 + // Bit CAP2_INT_ST. + MCPWM_INT_ST_CAP2_INT_ST = 0x20000000 + + // INT_CLR + // Position of TIMER0_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_STOP_INT_CLR_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_STOP_INT_CLR_Msk = 0x1 + // Bit TIMER0_STOP_INT_CLR. + MCPWM_INT_CLR_TIMER0_STOP_INT_CLR = 0x1 + // Position of TIMER1_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_STOP_INT_CLR_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_STOP_INT_CLR_Msk = 0x2 + // Bit TIMER1_STOP_INT_CLR. + MCPWM_INT_CLR_TIMER1_STOP_INT_CLR = 0x2 + // Position of TIMER2_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_STOP_INT_CLR_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_STOP_INT_CLR_Msk = 0x4 + // Bit TIMER2_STOP_INT_CLR. + MCPWM_INT_CLR_TIMER2_STOP_INT_CLR = 0x4 + // Position of TIMER0_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR_Msk = 0x8 + // Bit TIMER0_TEZ_INT_CLR. + MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR = 0x8 + // Position of TIMER1_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR_Msk = 0x10 + // Bit TIMER1_TEZ_INT_CLR. + MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR = 0x10 + // Position of TIMER2_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR_Msk = 0x20 + // Bit TIMER2_TEZ_INT_CLR. + MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR = 0x20 + // Position of TIMER0_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEP_INT_CLR_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEP_INT_CLR_Msk = 0x40 + // Bit TIMER0_TEP_INT_CLR. + MCPWM_INT_CLR_TIMER0_TEP_INT_CLR = 0x40 + // Position of TIMER1_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEP_INT_CLR_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEP_INT_CLR_Msk = 0x80 + // Bit TIMER1_TEP_INT_CLR. + MCPWM_INT_CLR_TIMER1_TEP_INT_CLR = 0x80 + // Position of TIMER2_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEP_INT_CLR_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEP_INT_CLR_Msk = 0x100 + // Bit TIMER2_TEP_INT_CLR. + MCPWM_INT_CLR_TIMER2_TEP_INT_CLR = 0x100 + // Position of FAULT0_INT_CLR field. + MCPWM_INT_CLR_FAULT0_INT_CLR_Pos = 0x9 + // Bit mask of FAULT0_INT_CLR field. + MCPWM_INT_CLR_FAULT0_INT_CLR_Msk = 0x200 + // Bit FAULT0_INT_CLR. + MCPWM_INT_CLR_FAULT0_INT_CLR = 0x200 + // Position of FAULT1_INT_CLR field. + MCPWM_INT_CLR_FAULT1_INT_CLR_Pos = 0xa + // Bit mask of FAULT1_INT_CLR field. + MCPWM_INT_CLR_FAULT1_INT_CLR_Msk = 0x400 + // Bit FAULT1_INT_CLR. + MCPWM_INT_CLR_FAULT1_INT_CLR = 0x400 + // Position of FAULT2_INT_CLR field. + MCPWM_INT_CLR_FAULT2_INT_CLR_Pos = 0xb + // Bit mask of FAULT2_INT_CLR field. + MCPWM_INT_CLR_FAULT2_INT_CLR_Msk = 0x800 + // Bit FAULT2_INT_CLR. + MCPWM_INT_CLR_FAULT2_INT_CLR = 0x800 + // Position of FAULT0_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT0_CLR_INT_CLR_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT0_CLR_INT_CLR_Msk = 0x1000 + // Bit FAULT0_CLR_INT_CLR. + MCPWM_INT_CLR_FAULT0_CLR_INT_CLR = 0x1000 + // Position of FAULT1_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT1_CLR_INT_CLR_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT1_CLR_INT_CLR_Msk = 0x2000 + // Bit FAULT1_CLR_INT_CLR. + MCPWM_INT_CLR_FAULT1_CLR_INT_CLR = 0x2000 + // Position of FAULT2_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT2_CLR_INT_CLR_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT2_CLR_INT_CLR_Msk = 0x4000 + // Bit FAULT2_CLR_INT_CLR. + MCPWM_INT_CLR_FAULT2_CLR_INT_CLR = 0x4000 + // Position of OP0_TEA_INT_CLR field. + MCPWM_INT_CLR_OP0_TEA_INT_CLR_Pos = 0xf + // Bit mask of OP0_TEA_INT_CLR field. + MCPWM_INT_CLR_OP0_TEA_INT_CLR_Msk = 0x8000 + // Bit OP0_TEA_INT_CLR. + MCPWM_INT_CLR_OP0_TEA_INT_CLR = 0x8000 + // Position of OP1_TEA_INT_CLR field. + MCPWM_INT_CLR_OP1_TEA_INT_CLR_Pos = 0x10 + // Bit mask of OP1_TEA_INT_CLR field. + MCPWM_INT_CLR_OP1_TEA_INT_CLR_Msk = 0x10000 + // Bit OP1_TEA_INT_CLR. + MCPWM_INT_CLR_OP1_TEA_INT_CLR = 0x10000 + // Position of OP2_TEA_INT_CLR field. + MCPWM_INT_CLR_OP2_TEA_INT_CLR_Pos = 0x11 + // Bit mask of OP2_TEA_INT_CLR field. + MCPWM_INT_CLR_OP2_TEA_INT_CLR_Msk = 0x20000 + // Bit OP2_TEA_INT_CLR. + MCPWM_INT_CLR_OP2_TEA_INT_CLR = 0x20000 + // Position of OP0_TEB_INT_CLR field. + MCPWM_INT_CLR_OP0_TEB_INT_CLR_Pos = 0x12 + // Bit mask of OP0_TEB_INT_CLR field. + MCPWM_INT_CLR_OP0_TEB_INT_CLR_Msk = 0x40000 + // Bit OP0_TEB_INT_CLR. + MCPWM_INT_CLR_OP0_TEB_INT_CLR = 0x40000 + // Position of OP1_TEB_INT_CLR field. + MCPWM_INT_CLR_OP1_TEB_INT_CLR_Pos = 0x13 + // Bit mask of OP1_TEB_INT_CLR field. + MCPWM_INT_CLR_OP1_TEB_INT_CLR_Msk = 0x80000 + // Bit OP1_TEB_INT_CLR. + MCPWM_INT_CLR_OP1_TEB_INT_CLR = 0x80000 + // Position of OP2_TEB_INT_CLR field. + MCPWM_INT_CLR_OP2_TEB_INT_CLR_Pos = 0x14 + // Bit mask of OP2_TEB_INT_CLR field. + MCPWM_INT_CLR_OP2_TEB_INT_CLR_Msk = 0x100000 + // Bit OP2_TEB_INT_CLR. + MCPWM_INT_CLR_OP2_TEB_INT_CLR = 0x100000 + // Position of FH0_CBC_INT_CLR field. + MCPWM_INT_CLR_FH0_CBC_INT_CLR_Pos = 0x15 + // Bit mask of FH0_CBC_INT_CLR field. + MCPWM_INT_CLR_FH0_CBC_INT_CLR_Msk = 0x200000 + // Bit FH0_CBC_INT_CLR. + MCPWM_INT_CLR_FH0_CBC_INT_CLR = 0x200000 + // Position of FH1_CBC_INT_CLR field. + MCPWM_INT_CLR_FH1_CBC_INT_CLR_Pos = 0x16 + // Bit mask of FH1_CBC_INT_CLR field. + MCPWM_INT_CLR_FH1_CBC_INT_CLR_Msk = 0x400000 + // Bit FH1_CBC_INT_CLR. + MCPWM_INT_CLR_FH1_CBC_INT_CLR = 0x400000 + // Position of FH2_CBC_INT_CLR field. + MCPWM_INT_CLR_FH2_CBC_INT_CLR_Pos = 0x17 + // Bit mask of FH2_CBC_INT_CLR field. + MCPWM_INT_CLR_FH2_CBC_INT_CLR_Msk = 0x800000 + // Bit FH2_CBC_INT_CLR. + MCPWM_INT_CLR_FH2_CBC_INT_CLR = 0x800000 + // Position of FH0_OST_INT_CLR field. + MCPWM_INT_CLR_FH0_OST_INT_CLR_Pos = 0x18 + // Bit mask of FH0_OST_INT_CLR field. + MCPWM_INT_CLR_FH0_OST_INT_CLR_Msk = 0x1000000 + // Bit FH0_OST_INT_CLR. + MCPWM_INT_CLR_FH0_OST_INT_CLR = 0x1000000 + // Position of FH1_OST_INT_CLR field. + MCPWM_INT_CLR_FH1_OST_INT_CLR_Pos = 0x19 + // Bit mask of FH1_OST_INT_CLR field. + MCPWM_INT_CLR_FH1_OST_INT_CLR_Msk = 0x2000000 + // Bit FH1_OST_INT_CLR. + MCPWM_INT_CLR_FH1_OST_INT_CLR = 0x2000000 + // Position of FH2_OST_INT_CLR field. + MCPWM_INT_CLR_FH2_OST_INT_CLR_Pos = 0x1a + // Bit mask of FH2_OST_INT_CLR field. + MCPWM_INT_CLR_FH2_OST_INT_CLR_Msk = 0x4000000 + // Bit FH2_OST_INT_CLR. + MCPWM_INT_CLR_FH2_OST_INT_CLR = 0x4000000 + // Position of CAP0_INT_CLR field. + MCPWM_INT_CLR_CAP0_INT_CLR_Pos = 0x1b + // Bit mask of CAP0_INT_CLR field. + MCPWM_INT_CLR_CAP0_INT_CLR_Msk = 0x8000000 + // Bit CAP0_INT_CLR. + MCPWM_INT_CLR_CAP0_INT_CLR = 0x8000000 + // Position of CAP1_INT_CLR field. + MCPWM_INT_CLR_CAP1_INT_CLR_Pos = 0x1c + // Bit mask of CAP1_INT_CLR field. + MCPWM_INT_CLR_CAP1_INT_CLR_Msk = 0x10000000 + // Bit CAP1_INT_CLR. + MCPWM_INT_CLR_CAP1_INT_CLR = 0x10000000 + // Position of CAP2_INT_CLR field. + MCPWM_INT_CLR_CAP2_INT_CLR_Pos = 0x1d + // Bit mask of CAP2_INT_CLR field. + MCPWM_INT_CLR_CAP2_INT_CLR_Msk = 0x20000000 + // Bit CAP2_INT_CLR. + MCPWM_INT_CLR_CAP2_INT_CLR = 0x20000000 + + // CLK + // Position of EN field. + MCPWM_CLK_EN_Pos = 0x0 + // Bit mask of EN field. + MCPWM_CLK_EN_Msk = 0x1 + // Bit EN. + MCPWM_CLK_EN = 0x1 + + // VERSION + // Position of DATE field. + MCPWM_VERSION_DATE_Pos = 0x0 + // Bit mask of DATE field. + MCPWM_VERSION_DATE_Msk = 0xfffffff +) + +// Constants for NRX: NRX Peripheral +const ( + // NRXPD_CTRL: WiFi RX control register + // Position of DEMAP_FORCE_PD field. + NRX_NRXPD_CTRL_DEMAP_FORCE_PD_Pos = 0x0 + // Bit mask of DEMAP_FORCE_PD field. + NRX_NRXPD_CTRL_DEMAP_FORCE_PD_Msk = 0x1 + // Bit DEMAP_FORCE_PD. + NRX_NRXPD_CTRL_DEMAP_FORCE_PD = 0x1 + // Position of DEMAP_FORCE_PU field. + NRX_NRXPD_CTRL_DEMAP_FORCE_PU_Pos = 0x1 + // Bit mask of DEMAP_FORCE_PU field. + NRX_NRXPD_CTRL_DEMAP_FORCE_PU_Msk = 0x2 + // Bit DEMAP_FORCE_PU. + NRX_NRXPD_CTRL_DEMAP_FORCE_PU = 0x2 + // Position of VIT_FORCE_PD field. + NRX_NRXPD_CTRL_VIT_FORCE_PD_Pos = 0x2 + // Bit mask of VIT_FORCE_PD field. + NRX_NRXPD_CTRL_VIT_FORCE_PD_Msk = 0x4 + // Bit VIT_FORCE_PD. + NRX_NRXPD_CTRL_VIT_FORCE_PD = 0x4 + // Position of VIT_FORCE_PU field. + NRX_NRXPD_CTRL_VIT_FORCE_PU_Pos = 0x3 + // Bit mask of VIT_FORCE_PU field. + NRX_NRXPD_CTRL_VIT_FORCE_PU_Msk = 0x8 + // Bit VIT_FORCE_PU. + NRX_NRXPD_CTRL_VIT_FORCE_PU = 0x8 + // Position of RX_ROT_FORCE_PD field. + NRX_NRXPD_CTRL_RX_ROT_FORCE_PD_Pos = 0x4 + // Bit mask of RX_ROT_FORCE_PD field. + NRX_NRXPD_CTRL_RX_ROT_FORCE_PD_Msk = 0x10 + // Bit RX_ROT_FORCE_PD. + NRX_NRXPD_CTRL_RX_ROT_FORCE_PD = 0x10 + // Position of RX_ROT_FORCE_PU field. + NRX_NRXPD_CTRL_RX_ROT_FORCE_PU_Pos = 0x5 + // Bit mask of RX_ROT_FORCE_PU field. + NRX_NRXPD_CTRL_RX_ROT_FORCE_PU_Msk = 0x20 + // Bit RX_ROT_FORCE_PU. + NRX_NRXPD_CTRL_RX_ROT_FORCE_PU = 0x20 + // Position of CHAN_EST_FORCE_PD field. + NRX_NRXPD_CTRL_CHAN_EST_FORCE_PD_Pos = 0x6 + // Bit mask of CHAN_EST_FORCE_PD field. + NRX_NRXPD_CTRL_CHAN_EST_FORCE_PD_Msk = 0x40 + // Bit CHAN_EST_FORCE_PD. + NRX_NRXPD_CTRL_CHAN_EST_FORCE_PD = 0x40 + // Position of CHAN_EST_FORCE_PU field. + NRX_NRXPD_CTRL_CHAN_EST_FORCE_PU_Pos = 0x7 + // Bit mask of CHAN_EST_FORCE_PU field. + NRX_NRXPD_CTRL_CHAN_EST_FORCE_PU_Msk = 0x80 + // Bit CHAN_EST_FORCE_PU. + NRX_NRXPD_CTRL_CHAN_EST_FORCE_PU = 0x80 +) + +// Constants for PCNT: Pulse Count Controller +const ( + // U0_CONF0 + // Position of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Pos = 0x0 + // Bit mask of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Msk = 0x3ff + // Position of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Pos = 0xa + // Bit mask of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Msk = 0x400 + // Bit FILTER_EN. + PCNT_U_CONF0_FILTER_EN = 0x400 + // Position of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Pos = 0xb + // Bit mask of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Msk = 0x800 + // Bit THR_ZERO_EN. + PCNT_U_CONF0_THR_ZERO_EN = 0x800 + // Position of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Pos = 0xc + // Bit mask of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Msk = 0x1000 + // Bit THR_H_LIM_EN. + PCNT_U_CONF0_THR_H_LIM_EN = 0x1000 + // Position of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Pos = 0xd + // Bit mask of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Msk = 0x2000 + // Bit THR_L_LIM_EN. + PCNT_U_CONF0_THR_L_LIM_EN = 0x2000 + // Position of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Pos = 0xe + // Bit mask of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Msk = 0x4000 + // Bit THR_THRES0_EN. + PCNT_U_CONF0_THR_THRES0_EN = 0x4000 + // Position of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Pos = 0xf + // Bit mask of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Msk = 0x8000 + // Bit THR_THRES1_EN. + PCNT_U_CONF0_THR_THRES1_EN = 0x8000 + // Position of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Pos = 0x10 + // Bit mask of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Msk = 0x30000 + // Position of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Pos = 0x12 + // Bit mask of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Msk = 0xc0000 + // Position of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Pos = 0x14 + // Bit mask of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Msk = 0x300000 + // Position of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Pos = 0x16 + // Bit mask of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Msk = 0xc00000 + // Position of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Pos = 0x18 + // Bit mask of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Msk = 0x3000000 + // Position of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Pos = 0x1a + // Bit mask of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Msk = 0xc000000 + // Position of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Pos = 0x1c + // Bit mask of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Msk = 0x30000000 + // Position of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Pos = 0x1e + // Bit mask of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Msk = 0xc0000000 + + // U0_CONF1 + // Position of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Pos = 0x0 + // Bit mask of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Msk = 0xffff + // Position of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Pos = 0x10 + // Bit mask of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Msk = 0xffff0000 + + // U0_CONF2 + // Position of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Pos = 0x0 + // Bit mask of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Msk = 0xffff + // Position of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Pos = 0x10 + // Bit mask of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Msk = 0xffff0000 + + // U0_CNT + // Position of CNT field. + PCNT_U_CNT_CNT_Pos = 0x0 + // Bit mask of CNT field. + PCNT_U_CNT_CNT_Msk = 0xffff + + // INT_RAW + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_RAW_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_RAW_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_RAW_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_RAW_CNT_THR_EVENT_U3 = 0x8 + // Position of CNT_THR_EVENT_U4 field. + PCNT_INT_RAW_CNT_THR_EVENT_U4_Pos = 0x4 + // Bit mask of CNT_THR_EVENT_U4 field. + PCNT_INT_RAW_CNT_THR_EVENT_U4_Msk = 0x10 + // Bit CNT_THR_EVENT_U4. + PCNT_INT_RAW_CNT_THR_EVENT_U4 = 0x10 + // Position of CNT_THR_EVENT_U5 field. + PCNT_INT_RAW_CNT_THR_EVENT_U5_Pos = 0x5 + // Bit mask of CNT_THR_EVENT_U5 field. + PCNT_INT_RAW_CNT_THR_EVENT_U5_Msk = 0x20 + // Bit CNT_THR_EVENT_U5. + PCNT_INT_RAW_CNT_THR_EVENT_U5 = 0x20 + // Position of CNT_THR_EVENT_U6 field. + PCNT_INT_RAW_CNT_THR_EVENT_U6_Pos = 0x6 + // Bit mask of CNT_THR_EVENT_U6 field. + PCNT_INT_RAW_CNT_THR_EVENT_U6_Msk = 0x40 + // Bit CNT_THR_EVENT_U6. + PCNT_INT_RAW_CNT_THR_EVENT_U6 = 0x40 + // Position of CNT_THR_EVENT_U7 field. + PCNT_INT_RAW_CNT_THR_EVENT_U7_Pos = 0x7 + // Bit mask of CNT_THR_EVENT_U7 field. + PCNT_INT_RAW_CNT_THR_EVENT_U7_Msk = 0x80 + // Bit CNT_THR_EVENT_U7. + PCNT_INT_RAW_CNT_THR_EVENT_U7 = 0x80 + + // INT_ST + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ST_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ST_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ST_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ST_CNT_THR_EVENT_U3 = 0x8 + // Position of CNT_THR_EVENT_U4 field. + PCNT_INT_ST_CNT_THR_EVENT_U4_Pos = 0x4 + // Bit mask of CNT_THR_EVENT_U4 field. + PCNT_INT_ST_CNT_THR_EVENT_U4_Msk = 0x10 + // Bit CNT_THR_EVENT_U4. + PCNT_INT_ST_CNT_THR_EVENT_U4 = 0x10 + // Position of CNT_THR_EVENT_U5 field. + PCNT_INT_ST_CNT_THR_EVENT_U5_Pos = 0x5 + // Bit mask of CNT_THR_EVENT_U5 field. + PCNT_INT_ST_CNT_THR_EVENT_U5_Msk = 0x20 + // Bit CNT_THR_EVENT_U5. + PCNT_INT_ST_CNT_THR_EVENT_U5 = 0x20 + // Position of CNT_THR_EVENT_U6 field. + PCNT_INT_ST_CNT_THR_EVENT_U6_Pos = 0x6 + // Bit mask of CNT_THR_EVENT_U6 field. + PCNT_INT_ST_CNT_THR_EVENT_U6_Msk = 0x40 + // Bit CNT_THR_EVENT_U6. + PCNT_INT_ST_CNT_THR_EVENT_U6 = 0x40 + // Position of CNT_THR_EVENT_U7 field. + PCNT_INT_ST_CNT_THR_EVENT_U7_Pos = 0x7 + // Bit mask of CNT_THR_EVENT_U7 field. + PCNT_INT_ST_CNT_THR_EVENT_U7_Msk = 0x80 + // Bit CNT_THR_EVENT_U7. + PCNT_INT_ST_CNT_THR_EVENT_U7 = 0x80 + + // INT_ENA + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ENA_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ENA_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ENA_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ENA_CNT_THR_EVENT_U3 = 0x8 + // Position of CNT_THR_EVENT_U4 field. + PCNT_INT_ENA_CNT_THR_EVENT_U4_Pos = 0x4 + // Bit mask of CNT_THR_EVENT_U4 field. + PCNT_INT_ENA_CNT_THR_EVENT_U4_Msk = 0x10 + // Bit CNT_THR_EVENT_U4. + PCNT_INT_ENA_CNT_THR_EVENT_U4 = 0x10 + // Position of CNT_THR_EVENT_U5 field. + PCNT_INT_ENA_CNT_THR_EVENT_U5_Pos = 0x5 + // Bit mask of CNT_THR_EVENT_U5 field. + PCNT_INT_ENA_CNT_THR_EVENT_U5_Msk = 0x20 + // Bit CNT_THR_EVENT_U5. + PCNT_INT_ENA_CNT_THR_EVENT_U5 = 0x20 + // Position of CNT_THR_EVENT_U6 field. + PCNT_INT_ENA_CNT_THR_EVENT_U6_Pos = 0x6 + // Bit mask of CNT_THR_EVENT_U6 field. + PCNT_INT_ENA_CNT_THR_EVENT_U6_Msk = 0x40 + // Bit CNT_THR_EVENT_U6. + PCNT_INT_ENA_CNT_THR_EVENT_U6 = 0x40 + // Position of CNT_THR_EVENT_U7 field. + PCNT_INT_ENA_CNT_THR_EVENT_U7_Pos = 0x7 + // Bit mask of CNT_THR_EVENT_U7 field. + PCNT_INT_ENA_CNT_THR_EVENT_U7_Msk = 0x80 + // Bit CNT_THR_EVENT_U7. + PCNT_INT_ENA_CNT_THR_EVENT_U7 = 0x80 + + // INT_CLR + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_CLR_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_CLR_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_CLR_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_CLR_CNT_THR_EVENT_U3 = 0x8 + // Position of CNT_THR_EVENT_U4 field. + PCNT_INT_CLR_CNT_THR_EVENT_U4_Pos = 0x4 + // Bit mask of CNT_THR_EVENT_U4 field. + PCNT_INT_CLR_CNT_THR_EVENT_U4_Msk = 0x10 + // Bit CNT_THR_EVENT_U4. + PCNT_INT_CLR_CNT_THR_EVENT_U4 = 0x10 + // Position of CNT_THR_EVENT_U5 field. + PCNT_INT_CLR_CNT_THR_EVENT_U5_Pos = 0x5 + // Bit mask of CNT_THR_EVENT_U5 field. + PCNT_INT_CLR_CNT_THR_EVENT_U5_Msk = 0x20 + // Bit CNT_THR_EVENT_U5. + PCNT_INT_CLR_CNT_THR_EVENT_U5 = 0x20 + // Position of CNT_THR_EVENT_U6 field. + PCNT_INT_CLR_CNT_THR_EVENT_U6_Pos = 0x6 + // Bit mask of CNT_THR_EVENT_U6 field. + PCNT_INT_CLR_CNT_THR_EVENT_U6_Msk = 0x40 + // Bit CNT_THR_EVENT_U6. + PCNT_INT_CLR_CNT_THR_EVENT_U6 = 0x40 + // Position of CNT_THR_EVENT_U7 field. + PCNT_INT_CLR_CNT_THR_EVENT_U7_Pos = 0x7 + // Bit mask of CNT_THR_EVENT_U7 field. + PCNT_INT_CLR_CNT_THR_EVENT_U7_Msk = 0x80 + // Bit CNT_THR_EVENT_U7. + PCNT_INT_CLR_CNT_THR_EVENT_U7 = 0x80 + + // U0_STATUS + // Position of CORE_STATUS_U0 field. + PCNT_U_STATUS_CORE_STATUS_U0_Pos = 0x0 + // Bit mask of CORE_STATUS_U0 field. + PCNT_U_STATUS_CORE_STATUS_U0_Msk = 0xffffffff + // Position of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Pos = 0x0 + // Bit mask of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Msk = 0x3 + // Position of THRES1 field. + PCNT_U_STATUS_THRES1_Pos = 0x2 + // Bit mask of THRES1 field. + PCNT_U_STATUS_THRES1_Msk = 0x4 + // Bit THRES1. + PCNT_U_STATUS_THRES1 = 0x4 + // Position of THRES0 field. + PCNT_U_STATUS_THRES0_Pos = 0x3 + // Bit mask of THRES0 field. + PCNT_U_STATUS_THRES0_Msk = 0x8 + // Bit THRES0. + PCNT_U_STATUS_THRES0 = 0x8 + // Position of L_LIM field. + PCNT_U_STATUS_L_LIM_Pos = 0x4 + // Bit mask of L_LIM field. + PCNT_U_STATUS_L_LIM_Msk = 0x10 + // Bit L_LIM. + PCNT_U_STATUS_L_LIM = 0x10 + // Position of H_LIM field. + PCNT_U_STATUS_H_LIM_Pos = 0x5 + // Bit mask of H_LIM field. + PCNT_U_STATUS_H_LIM_Msk = 0x20 + // Bit H_LIM. + PCNT_U_STATUS_H_LIM = 0x20 + // Position of ZERO field. + PCNT_U_STATUS_ZERO_Pos = 0x6 + // Bit mask of ZERO field. + PCNT_U_STATUS_ZERO_Msk = 0x40 + // Bit ZERO. + PCNT_U_STATUS_ZERO = 0x40 + + // CTRL + // Position of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Pos = 0x0 + // Bit mask of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Msk = 0x1 + // Bit CNT_RST_U0. + PCNT_CTRL_CNT_RST_U0 = 0x1 + // Position of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Pos = 0x1 + // Bit mask of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Msk = 0x2 + // Bit CNT_PAUSE_U0. + PCNT_CTRL_CNT_PAUSE_U0 = 0x2 + // Position of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Pos = 0x2 + // Bit mask of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Msk = 0x4 + // Bit CNT_RST_U1. + PCNT_CTRL_CNT_RST_U1 = 0x4 + // Position of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Pos = 0x3 + // Bit mask of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Msk = 0x8 + // Bit CNT_PAUSE_U1. + PCNT_CTRL_CNT_PAUSE_U1 = 0x8 + // Position of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Pos = 0x4 + // Bit mask of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Msk = 0x10 + // Bit CNT_RST_U2. + PCNT_CTRL_CNT_RST_U2 = 0x10 + // Position of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Pos = 0x5 + // Bit mask of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Msk = 0x20 + // Bit CNT_PAUSE_U2. + PCNT_CTRL_CNT_PAUSE_U2 = 0x20 + // Position of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Pos = 0x6 + // Bit mask of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Msk = 0x40 + // Bit CNT_RST_U3. + PCNT_CTRL_CNT_RST_U3 = 0x40 + // Position of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Pos = 0x7 + // Bit mask of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Msk = 0x80 + // Bit CNT_PAUSE_U3. + PCNT_CTRL_CNT_PAUSE_U3 = 0x80 + // Position of CNT_RST_U4 field. + PCNT_CTRL_CNT_RST_U4_Pos = 0x8 + // Bit mask of CNT_RST_U4 field. + PCNT_CTRL_CNT_RST_U4_Msk = 0x100 + // Bit CNT_RST_U4. + PCNT_CTRL_CNT_RST_U4 = 0x100 + // Position of CNT_PAUSE_U4 field. + PCNT_CTRL_CNT_PAUSE_U4_Pos = 0x9 + // Bit mask of CNT_PAUSE_U4 field. + PCNT_CTRL_CNT_PAUSE_U4_Msk = 0x200 + // Bit CNT_PAUSE_U4. + PCNT_CTRL_CNT_PAUSE_U4 = 0x200 + // Position of CNT_RST_U5 field. + PCNT_CTRL_CNT_RST_U5_Pos = 0xa + // Bit mask of CNT_RST_U5 field. + PCNT_CTRL_CNT_RST_U5_Msk = 0x400 + // Bit CNT_RST_U5. + PCNT_CTRL_CNT_RST_U5 = 0x400 + // Position of CNT_PAUSE_U5 field. + PCNT_CTRL_CNT_PAUSE_U5_Pos = 0xb + // Bit mask of CNT_PAUSE_U5 field. + PCNT_CTRL_CNT_PAUSE_U5_Msk = 0x800 + // Bit CNT_PAUSE_U5. + PCNT_CTRL_CNT_PAUSE_U5 = 0x800 + // Position of CNT_RST_U6 field. + PCNT_CTRL_CNT_RST_U6_Pos = 0xc + // Bit mask of CNT_RST_U6 field. + PCNT_CTRL_CNT_RST_U6_Msk = 0x1000 + // Bit CNT_RST_U6. + PCNT_CTRL_CNT_RST_U6 = 0x1000 + // Position of CNT_PAUSE_U6 field. + PCNT_CTRL_CNT_PAUSE_U6_Pos = 0xd + // Bit mask of CNT_PAUSE_U6 field. + PCNT_CTRL_CNT_PAUSE_U6_Msk = 0x2000 + // Bit CNT_PAUSE_U6. + PCNT_CTRL_CNT_PAUSE_U6 = 0x2000 + // Position of CNT_RST_U7 field. + PCNT_CTRL_CNT_RST_U7_Pos = 0xe + // Bit mask of CNT_RST_U7 field. + PCNT_CTRL_CNT_RST_U7_Msk = 0x4000 + // Bit CNT_RST_U7. + PCNT_CTRL_CNT_RST_U7 = 0x4000 + // Position of CNT_PAUSE_U7 field. + PCNT_CTRL_CNT_PAUSE_U7_Pos = 0xf + // Bit mask of CNT_PAUSE_U7 field. + PCNT_CTRL_CNT_PAUSE_U7_Msk = 0x8000 + // Bit CNT_PAUSE_U7. + PCNT_CTRL_CNT_PAUSE_U7 = 0x8000 + // Position of CLK_EN field. + PCNT_CTRL_CLK_EN_Pos = 0x10 + // Bit mask of CLK_EN field. + PCNT_CTRL_CLK_EN_Msk = 0x10000 + // Bit CLK_EN. + PCNT_CTRL_CLK_EN = 0x10000 + + // DATE + // Position of DATE field. + PCNT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PCNT_DATE_DATE_Msk = 0xffffffff +) + +// Constants for RMT: Remote Control +const ( + // CH0CONF0 + // Position of DIV_CNT field. + RMT_CHCONF0_DIV_CNT_Pos = 0x0 + // Bit mask of DIV_CNT field. + RMT_CHCONF0_DIV_CNT_Msk = 0xff + // Position of IDLE_THRES field. + RMT_CHCONF0_IDLE_THRES_Pos = 0x8 + // Bit mask of IDLE_THRES field. + RMT_CHCONF0_IDLE_THRES_Msk = 0xffff00 + // Position of MEM_SIZE field. + RMT_CHCONF0_MEM_SIZE_Pos = 0x18 + // Bit mask of MEM_SIZE field. + RMT_CHCONF0_MEM_SIZE_Msk = 0xf000000 + // Position of CARRIER_EN field. + RMT_CHCONF0_CARRIER_EN_Pos = 0x1c + // Bit mask of CARRIER_EN field. + RMT_CHCONF0_CARRIER_EN_Msk = 0x10000000 + // Bit CARRIER_EN. + RMT_CHCONF0_CARRIER_EN = 0x10000000 + // Position of CARRIER_OUT_LV field. + RMT_CHCONF0_CARRIER_OUT_LV_Pos = 0x1d + // Bit mask of CARRIER_OUT_LV field. + RMT_CHCONF0_CARRIER_OUT_LV_Msk = 0x20000000 + // Bit CARRIER_OUT_LV. + RMT_CHCONF0_CARRIER_OUT_LV = 0x20000000 + // Position of MEM_PD field. + RMT_CHCONF0_MEM_PD_Pos = 0x1e + // Bit mask of MEM_PD field. + RMT_CHCONF0_MEM_PD_Msk = 0x40000000 + // Bit MEM_PD. + RMT_CHCONF0_MEM_PD = 0x40000000 + // Position of CLK_EN field. + RMT_CHCONF0_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + RMT_CHCONF0_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + RMT_CHCONF0_CLK_EN = 0x80000000 + + // CH0CONF1 + // Position of TX_START field. + RMT_CHCONF1_TX_START_Pos = 0x0 + // Bit mask of TX_START field. + RMT_CHCONF1_TX_START_Msk = 0x1 + // Bit TX_START. + RMT_CHCONF1_TX_START = 0x1 + // Position of RX_EN field. + RMT_CHCONF1_RX_EN_Pos = 0x1 + // Bit mask of RX_EN field. + RMT_CHCONF1_RX_EN_Msk = 0x2 + // Bit RX_EN. + RMT_CHCONF1_RX_EN = 0x2 + // Position of MEM_WR_RST field. + RMT_CHCONF1_MEM_WR_RST_Pos = 0x2 + // Bit mask of MEM_WR_RST field. + RMT_CHCONF1_MEM_WR_RST_Msk = 0x4 + // Bit MEM_WR_RST. + RMT_CHCONF1_MEM_WR_RST = 0x4 + // Position of MEM_RD_RST field. + RMT_CHCONF1_MEM_RD_RST_Pos = 0x3 + // Bit mask of MEM_RD_RST field. + RMT_CHCONF1_MEM_RD_RST_Msk = 0x8 + // Bit MEM_RD_RST. + RMT_CHCONF1_MEM_RD_RST = 0x8 + // Position of APB_MEM_RST field. + RMT_CHCONF1_APB_MEM_RST_Pos = 0x4 + // Bit mask of APB_MEM_RST field. + RMT_CHCONF1_APB_MEM_RST_Msk = 0x10 + // Bit APB_MEM_RST. + RMT_CHCONF1_APB_MEM_RST = 0x10 + // Position of MEM_OWNER field. + RMT_CHCONF1_MEM_OWNER_Pos = 0x5 + // Bit mask of MEM_OWNER field. + RMT_CHCONF1_MEM_OWNER_Msk = 0x20 + // Bit MEM_OWNER. + RMT_CHCONF1_MEM_OWNER = 0x20 + // Position of TX_CONTI_MODE field. + RMT_CHCONF1_TX_CONTI_MODE_Pos = 0x6 + // Bit mask of TX_CONTI_MODE field. + RMT_CHCONF1_TX_CONTI_MODE_Msk = 0x40 + // Bit TX_CONTI_MODE. + RMT_CHCONF1_TX_CONTI_MODE = 0x40 + // Position of RX_FILTER_EN field. + RMT_CHCONF1_RX_FILTER_EN_Pos = 0x7 + // Bit mask of RX_FILTER_EN field. + RMT_CHCONF1_RX_FILTER_EN_Msk = 0x80 + // Bit RX_FILTER_EN. + RMT_CHCONF1_RX_FILTER_EN = 0x80 + // Position of RX_FILTER_THRES field. + RMT_CHCONF1_RX_FILTER_THRES_Pos = 0x8 + // Bit mask of RX_FILTER_THRES field. + RMT_CHCONF1_RX_FILTER_THRES_Msk = 0xff00 + // Position of REF_CNT_RST field. + RMT_CHCONF1_REF_CNT_RST_Pos = 0x10 + // Bit mask of REF_CNT_RST field. + RMT_CHCONF1_REF_CNT_RST_Msk = 0x10000 + // Bit REF_CNT_RST. + RMT_CHCONF1_REF_CNT_RST = 0x10000 + // Position of REF_ALWAYS_ON field. + RMT_CHCONF1_REF_ALWAYS_ON_Pos = 0x11 + // Bit mask of REF_ALWAYS_ON field. + RMT_CHCONF1_REF_ALWAYS_ON_Msk = 0x20000 + // Bit REF_ALWAYS_ON. + RMT_CHCONF1_REF_ALWAYS_ON = 0x20000 + // Position of IDLE_OUT_LV field. + RMT_CHCONF1_IDLE_OUT_LV_Pos = 0x12 + // Bit mask of IDLE_OUT_LV field. + RMT_CHCONF1_IDLE_OUT_LV_Msk = 0x40000 + // Bit IDLE_OUT_LV. + RMT_CHCONF1_IDLE_OUT_LV = 0x40000 + // Position of IDLE_OUT_EN field. + RMT_CHCONF1_IDLE_OUT_EN_Pos = 0x13 + // Bit mask of IDLE_OUT_EN field. + RMT_CHCONF1_IDLE_OUT_EN_Msk = 0x80000 + // Bit IDLE_OUT_EN. + RMT_CHCONF1_IDLE_OUT_EN = 0x80000 + + // CH0STATUS + // Position of STATUS field. + RMT_CHSTATUS_STATUS_Pos = 0x0 + // Bit mask of STATUS field. + RMT_CHSTATUS_STATUS_Msk = 0xffffffff + // Position of MEM_WADDR_EX field. + RMT_CHSTATUS_MEM_WADDR_EX_Pos = 0x0 + // Bit mask of MEM_WADDR_EX field. + RMT_CHSTATUS_MEM_WADDR_EX_Msk = 0x3ff + // Position of MEM_RADDR_EX field. + RMT_CHSTATUS_MEM_RADDR_EX_Pos = 0xc + // Bit mask of MEM_RADDR_EX field. + RMT_CHSTATUS_MEM_RADDR_EX_Msk = 0x3ff000 + // Position of STATE field. + RMT_CHSTATUS_STATE_Pos = 0x18 + // Bit mask of STATE field. + RMT_CHSTATUS_STATE_Msk = 0x7000000 + // Position of MEM_OWNER_ERR field. + RMT_CHSTATUS_MEM_OWNER_ERR_Pos = 0x1b + // Bit mask of MEM_OWNER_ERR field. + RMT_CHSTATUS_MEM_OWNER_ERR_Msk = 0x8000000 + // Bit MEM_OWNER_ERR. + RMT_CHSTATUS_MEM_OWNER_ERR = 0x8000000 + // Position of MEM_FULL field. + RMT_CHSTATUS_MEM_FULL_Pos = 0x1c + // Bit mask of MEM_FULL field. + RMT_CHSTATUS_MEM_FULL_Msk = 0x10000000 + // Bit MEM_FULL. + RMT_CHSTATUS_MEM_FULL = 0x10000000 + // Position of MEM_EMPTY field. + RMT_CHSTATUS_MEM_EMPTY_Pos = 0x1d + // Bit mask of MEM_EMPTY field. + RMT_CHSTATUS_MEM_EMPTY_Msk = 0x20000000 + // Bit MEM_EMPTY. + RMT_CHSTATUS_MEM_EMPTY = 0x20000000 + // Position of APB_MEM_WR_ERR field. + RMT_CHSTATUS_APB_MEM_WR_ERR_Pos = 0x1e + // Bit mask of APB_MEM_WR_ERR field. + RMT_CHSTATUS_APB_MEM_WR_ERR_Msk = 0x40000000 + // Bit APB_MEM_WR_ERR. + RMT_CHSTATUS_APB_MEM_WR_ERR = 0x40000000 + // Position of APB_MEM_RD_ERR field. + RMT_CHSTATUS_APB_MEM_RD_ERR_Pos = 0x1f + // Bit mask of APB_MEM_RD_ERR field. + RMT_CHSTATUS_APB_MEM_RD_ERR_Msk = 0x80000000 + // Bit APB_MEM_RD_ERR. + RMT_CHSTATUS_APB_MEM_RD_ERR = 0x80000000 + + // CH0ADDR + // Position of APB_MEM_ADDR field. + RMT_CHADDR_APB_MEM_ADDR_Pos = 0x0 + // Bit mask of APB_MEM_ADDR field. + RMT_CHADDR_APB_MEM_ADDR_Msk = 0xffffffff + + // INT_RAW + // Position of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_RAW_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Pos = 0x1 + // Bit mask of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Msk = 0x2 + // Bit CH_s_RX_END. + RMT_INT_RAW_CH_s_RX_END = 0x2 + // Position of CH_s_ERR field. + RMT_INT_RAW_CH_s_ERR_Pos = 0x2 + // Bit mask of CH_s_ERR field. + RMT_INT_RAW_CH_s_ERR_Msk = 0x4 + // Bit CH_s_ERR. + RMT_INT_RAW_CH_s_ERR = 0x4 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Pos = 0x18 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Msk = 0x1000000 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_RAW_CH_s_TX_THR_EVENT = 0x1000000 + + // INT_ST + // Position of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ST_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Pos = 0x1 + // Bit mask of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Msk = 0x2 + // Bit CH_s_RX_END. + RMT_INT_ST_CH_s_RX_END = 0x2 + // Position of CH_s_ERR field. + RMT_INT_ST_CH_s_ERR_Pos = 0x2 + // Bit mask of CH_s_ERR field. + RMT_INT_ST_CH_s_ERR_Msk = 0x4 + // Bit CH_s_ERR. + RMT_INT_ST_CH_s_ERR = 0x4 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Pos = 0x18 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Msk = 0x1000000 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ST_CH_s_TX_THR_EVENT = 0x1000000 + + // INT_ENA + // Position of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ENA_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Pos = 0x1 + // Bit mask of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Msk = 0x2 + // Bit CH_s_RX_END. + RMT_INT_ENA_CH_s_RX_END = 0x2 + // Position of CH_s_ERR field. + RMT_INT_ENA_CH_s_ERR_Pos = 0x2 + // Bit mask of CH_s_ERR field. + RMT_INT_ENA_CH_s_ERR_Msk = 0x4 + // Bit CH_s_ERR. + RMT_INT_ENA_CH_s_ERR = 0x4 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Pos = 0x18 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Msk = 0x1000000 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ENA_CH_s_TX_THR_EVENT = 0x1000000 + + // INT_CLR + // Position of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_CLR_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Pos = 0x1 + // Bit mask of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Msk = 0x2 + // Bit CH_s_RX_END. + RMT_INT_CLR_CH_s_RX_END = 0x2 + // Position of CH_s_ERR field. + RMT_INT_CLR_CH_s_ERR_Pos = 0x2 + // Bit mask of CH_s_ERR field. + RMT_INT_CLR_CH_s_ERR_Msk = 0x4 + // Bit CH_s_ERR. + RMT_INT_CLR_CH_s_ERR = 0x4 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Pos = 0x18 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Msk = 0x1000000 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_CLR_CH_s_TX_THR_EVENT = 0x1000000 + + // CH0CARRIER_DUTY + // Position of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Pos = 0x0 + // Bit mask of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Msk = 0xffff + // Position of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Pos = 0x10 + // Bit mask of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Msk = 0xffff0000 + + // CH0_TX_LIM + // Position of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Pos = 0x0 + // Bit mask of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Msk = 0x1ff + + // APB_CONF + // Position of APB_FIFO_MASK field. + RMT_APB_CONF_APB_FIFO_MASK_Pos = 0x0 + // Bit mask of APB_FIFO_MASK field. + RMT_APB_CONF_APB_FIFO_MASK_Msk = 0x1 + // Bit APB_FIFO_MASK. + RMT_APB_CONF_APB_FIFO_MASK = 0x1 + // Position of MEM_TX_WRAP_EN field. + RMT_APB_CONF_MEM_TX_WRAP_EN_Pos = 0x1 + // Bit mask of MEM_TX_WRAP_EN field. + RMT_APB_CONF_MEM_TX_WRAP_EN_Msk = 0x2 + // Bit MEM_TX_WRAP_EN. + RMT_APB_CONF_MEM_TX_WRAP_EN = 0x2 + + // DATE + // Position of DATE field. + RMT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RMT_DATE_DATE_Msk = 0xffffffff +) + +// Constants for RNG: Hardware Random Number Generator +const () + +// Constants for RSA: RSA (Rivest Shamir Adleman) Accelerator +const ( + // M_PRIME + // Position of M_PRIME field. + RSA_M_PRIME_M_PRIME_Pos = 0x0 + // Bit mask of M_PRIME field. + RSA_M_PRIME_M_PRIME_Msk = 0xff + + // MODEXP_MODE + // Position of MODEXP_MODE field. + RSA_MODEXP_MODE_MODEXP_MODE_Pos = 0x0 + // Bit mask of MODEXP_MODE field. + RSA_MODEXP_MODE_MODEXP_MODE_Msk = 0x7 + + // MODEXP_START + // Position of MODEXP_START field. + RSA_MODEXP_START_MODEXP_START_Pos = 0x0 + // Bit mask of MODEXP_START field. + RSA_MODEXP_START_MODEXP_START_Msk = 0x1 + // Bit MODEXP_START. + RSA_MODEXP_START_MODEXP_START = 0x1 + + // MULT_MODE + // Position of MULT_MODE field. + RSA_MULT_MODE_MULT_MODE_Pos = 0x0 + // Bit mask of MULT_MODE field. + RSA_MULT_MODE_MULT_MODE_Msk = 0xf + + // MULT_START + // Position of MULT_START field. + RSA_MULT_START_MULT_START_Pos = 0x0 + // Bit mask of MULT_START field. + RSA_MULT_START_MULT_START_Msk = 0x1 + // Bit MULT_START. + RSA_MULT_START_MULT_START = 0x1 + + // INTERRUPT + // Position of INTERRUPT field. + RSA_INTERRUPT_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + RSA_INTERRUPT_INTERRUPT_Msk = 0x1 + // Bit INTERRUPT. + RSA_INTERRUPT_INTERRUPT = 0x1 + + // CLEAN + // Position of CLEAN field. + RSA_CLEAN_CLEAN_Pos = 0x0 + // Bit mask of CLEAN field. + RSA_CLEAN_CLEAN_Msk = 0x1 + // Bit CLEAN. + RSA_CLEAN_CLEAN = 0x1 +) + +// Constants for RTC_CNTL: Real-Time Clock Control +const ( + // OPTIONS0 + // Position of SW_STALL_APPCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_APPCPU_C0_Pos = 0x0 + // Bit mask of SW_STALL_APPCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_APPCPU_C0_Msk = 0x3 + // Position of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Pos = 0x2 + // Bit mask of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Msk = 0xc + // Position of SW_APPCPU_RST field. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST_Pos = 0x4 + // Bit mask of SW_APPCPU_RST field. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST_Msk = 0x10 + // Bit SW_APPCPU_RST. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST = 0x10 + // Position of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Pos = 0x5 + // Bit mask of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Msk = 0x20 + // Bit SW_PROCPU_RST. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST = 0x20 + // Position of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Pos = 0x6 + // Bit mask of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Msk = 0x40 + // Bit BB_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD = 0x40 + // Position of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Pos = 0x7 + // Bit mask of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Msk = 0x80 + // Bit BB_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU = 0x80 + // Position of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Pos = 0x8 + // Bit mask of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Msk = 0x100 + // Bit BBPLL_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD = 0x100 + // Position of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Pos = 0x9 + // Bit mask of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Msk = 0x200 + // Bit BBPLL_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU = 0x200 + // Position of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Pos = 0xa + // Bit mask of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Msk = 0x400 + // Bit BBPLL_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD = 0x400 + // Position of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Pos = 0xb + // Bit mask of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Msk = 0x800 + // Bit BBPLL_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU = 0x800 + // Position of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Pos = 0xc + // Bit mask of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Msk = 0x1000 + // Bit XTL_FORCE_PD. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD = 0x1000 + // Position of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Pos = 0xd + // Bit mask of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Msk = 0x2000 + // Bit XTL_FORCE_PU. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU = 0x2000 + // Position of BIAS_SLEEP_FOLW_8M field. + RTC_CNTL_OPTIONS0_BIAS_SLEEP_FOLW_8M_Pos = 0xe + // Bit mask of BIAS_SLEEP_FOLW_8M field. + RTC_CNTL_OPTIONS0_BIAS_SLEEP_FOLW_8M_Msk = 0x4000 + // Bit BIAS_SLEEP_FOLW_8M. + RTC_CNTL_OPTIONS0_BIAS_SLEEP_FOLW_8M = 0x4000 + // Position of BIAS_FORCE_SLEEP field. + RTC_CNTL_OPTIONS0_BIAS_FORCE_SLEEP_Pos = 0xf + // Bit mask of BIAS_FORCE_SLEEP field. + RTC_CNTL_OPTIONS0_BIAS_FORCE_SLEEP_Msk = 0x8000 + // Bit BIAS_FORCE_SLEEP. + RTC_CNTL_OPTIONS0_BIAS_FORCE_SLEEP = 0x8000 + // Position of BIAS_FORCE_NOSLEEP field. + RTC_CNTL_OPTIONS0_BIAS_FORCE_NOSLEEP_Pos = 0x10 + // Bit mask of BIAS_FORCE_NOSLEEP field. + RTC_CNTL_OPTIONS0_BIAS_FORCE_NOSLEEP_Msk = 0x10000 + // Bit BIAS_FORCE_NOSLEEP. + RTC_CNTL_OPTIONS0_BIAS_FORCE_NOSLEEP = 0x10000 + // Position of BIAS_I2C_FOLW_8M field. + RTC_CNTL_OPTIONS0_BIAS_I2C_FOLW_8M_Pos = 0x11 + // Bit mask of BIAS_I2C_FOLW_8M field. + RTC_CNTL_OPTIONS0_BIAS_I2C_FOLW_8M_Msk = 0x20000 + // Bit BIAS_I2C_FOLW_8M. + RTC_CNTL_OPTIONS0_BIAS_I2C_FOLW_8M = 0x20000 + // Position of BIAS_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BIAS_I2C_FORCE_PD_Pos = 0x12 + // Bit mask of BIAS_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BIAS_I2C_FORCE_PD_Msk = 0x40000 + // Bit BIAS_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BIAS_I2C_FORCE_PD = 0x40000 + // Position of BIAS_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BIAS_I2C_FORCE_PU_Pos = 0x13 + // Bit mask of BIAS_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BIAS_I2C_FORCE_PU_Msk = 0x80000 + // Bit BIAS_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BIAS_I2C_FORCE_PU = 0x80000 + // Position of BIAS_CORE_FOLW_8M field. + RTC_CNTL_OPTIONS0_BIAS_CORE_FOLW_8M_Pos = 0x14 + // Bit mask of BIAS_CORE_FOLW_8M field. + RTC_CNTL_OPTIONS0_BIAS_CORE_FOLW_8M_Msk = 0x100000 + // Bit BIAS_CORE_FOLW_8M. + RTC_CNTL_OPTIONS0_BIAS_CORE_FOLW_8M = 0x100000 + // Position of BIAS_CORE_FORCE_PD field. + RTC_CNTL_OPTIONS0_BIAS_CORE_FORCE_PD_Pos = 0x15 + // Bit mask of BIAS_CORE_FORCE_PD field. + RTC_CNTL_OPTIONS0_BIAS_CORE_FORCE_PD_Msk = 0x200000 + // Bit BIAS_CORE_FORCE_PD. + RTC_CNTL_OPTIONS0_BIAS_CORE_FORCE_PD = 0x200000 + // Position of BIAS_CORE_FORCE_PU field. + RTC_CNTL_OPTIONS0_BIAS_CORE_FORCE_PU_Pos = 0x16 + // Bit mask of BIAS_CORE_FORCE_PU field. + RTC_CNTL_OPTIONS0_BIAS_CORE_FORCE_PU_Msk = 0x400000 + // Bit BIAS_CORE_FORCE_PU. + RTC_CNTL_OPTIONS0_BIAS_CORE_FORCE_PU = 0x400000 + // Position of XTL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO_Pos = 0x17 + // Bit mask of XTL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO_Msk = 0x800000 + // Bit XTL_FORCE_ISO. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO = 0x800000 + // Position of PLL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO_Pos = 0x18 + // Bit mask of PLL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO_Msk = 0x1000000 + // Bit PLL_FORCE_ISO. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO = 0x1000000 + // Position of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Pos = 0x19 + // Bit mask of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Msk = 0x2000000 + // Bit ANALOG_FORCE_ISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO = 0x2000000 + // Position of XTL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO_Pos = 0x1a + // Bit mask of XTL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO_Msk = 0x4000000 + // Bit XTL_FORCE_NOISO. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO = 0x4000000 + // Position of PLL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO_Pos = 0x1b + // Bit mask of PLL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO_Msk = 0x8000000 + // Bit PLL_FORCE_NOISO. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO = 0x8000000 + // Position of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Pos = 0x1c + // Bit mask of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Msk = 0x10000000 + // Bit ANALOG_FORCE_NOISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO = 0x10000000 + // Position of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Pos = 0x1d + // Bit mask of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Msk = 0x20000000 + // Bit DG_WRAP_FORCE_RST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST = 0x20000000 + // Position of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_NORST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST = 0x40000000 + // Position of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Pos = 0x1f + // Bit mask of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Msk = 0x80000000 + // Bit SW_SYS_RST. + RTC_CNTL_OPTIONS0_SW_SYS_RST = 0x80000000 + + // SLP_TIMER0 + // Position of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Pos = 0x0 + // Bit mask of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Msk = 0xffffffff + + // SLP_TIMER1 + // Position of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Pos = 0x0 + // Bit mask of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Msk = 0xffff + // Position of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Pos = 0x10 + // Bit mask of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Msk = 0x10000 + // Bit MAIN_TIMER_ALARM_EN. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN = 0x10000 + + // TIME_UPDATE + // Position of TIME_VALID field. + RTC_CNTL_TIME_UPDATE_TIME_VALID_Pos = 0x1e + // Bit mask of TIME_VALID field. + RTC_CNTL_TIME_UPDATE_TIME_VALID_Msk = 0x40000000 + // Bit TIME_VALID. + RTC_CNTL_TIME_UPDATE_TIME_VALID = 0x40000000 + // Position of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Pos = 0x1f + // Bit mask of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Msk = 0x80000000 + // Bit TIME_UPDATE. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE = 0x80000000 + + // TIME0 + // Position of TIME_LO field. + RTC_CNTL_TIME0_TIME_LO_Pos = 0x0 + // Bit mask of TIME_LO field. + RTC_CNTL_TIME0_TIME_LO_Msk = 0xffffffff + + // TIME1 + // Position of TIME_HI field. + RTC_CNTL_TIME1_TIME_HI_Pos = 0x0 + // Bit mask of TIME_HI field. + RTC_CNTL_TIME1_TIME_HI_Msk = 0xffff + + // STATE0 + // Position of TOUCH_WAKEUP_FORCE_EN field. + RTC_CNTL_STATE0_TOUCH_WAKEUP_FORCE_EN_Pos = 0x14 + // Bit mask of TOUCH_WAKEUP_FORCE_EN field. + RTC_CNTL_STATE0_TOUCH_WAKEUP_FORCE_EN_Msk = 0x100000 + // Bit TOUCH_WAKEUP_FORCE_EN. + RTC_CNTL_STATE0_TOUCH_WAKEUP_FORCE_EN = 0x100000 + // Position of ULP_CP_WAKEUP_FORCE_EN field. + RTC_CNTL_STATE0_ULP_CP_WAKEUP_FORCE_EN_Pos = 0x15 + // Bit mask of ULP_CP_WAKEUP_FORCE_EN field. + RTC_CNTL_STATE0_ULP_CP_WAKEUP_FORCE_EN_Msk = 0x200000 + // Bit ULP_CP_WAKEUP_FORCE_EN. + RTC_CNTL_STATE0_ULP_CP_WAKEUP_FORCE_EN = 0x200000 + // Position of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Pos = 0x16 + // Bit mask of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Msk = 0x400000 + // Bit APB2RTC_BRIDGE_SEL. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL = 0x400000 + // Position of TOUCH_SLP_TIMER_EN field. + RTC_CNTL_STATE0_TOUCH_SLP_TIMER_EN_Pos = 0x17 + // Bit mask of TOUCH_SLP_TIMER_EN field. + RTC_CNTL_STATE0_TOUCH_SLP_TIMER_EN_Msk = 0x800000 + // Bit TOUCH_SLP_TIMER_EN. + RTC_CNTL_STATE0_TOUCH_SLP_TIMER_EN = 0x800000 + // Position of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_STATE0_ULP_CP_SLP_TIMER_EN_Pos = 0x18 + // Bit mask of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_STATE0_ULP_CP_SLP_TIMER_EN_Msk = 0x1000000 + // Bit ULP_CP_SLP_TIMER_EN. + RTC_CNTL_STATE0_ULP_CP_SLP_TIMER_EN = 0x1000000 + // Position of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Pos = 0x1c + // Bit mask of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Msk = 0x10000000 + // Bit SDIO_ACTIVE_IND. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND = 0x10000000 + // Position of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Pos = 0x1d + // Bit mask of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Msk = 0x20000000 + // Bit SLP_WAKEUP. + RTC_CNTL_STATE0_SLP_WAKEUP = 0x20000000 + // Position of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Pos = 0x1e + // Bit mask of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Msk = 0x40000000 + // Bit SLP_REJECT. + RTC_CNTL_STATE0_SLP_REJECT = 0x40000000 + // Position of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Pos = 0x1f + // Bit mask of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Msk = 0x80000000 + // Bit SLEEP_EN. + RTC_CNTL_STATE0_SLEEP_EN = 0x80000000 + + // TIMER1 + // Position of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Pos = 0x0 + // Bit mask of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Msk = 0x1 + // Bit CPU_STALL_EN. + RTC_CNTL_TIMER1_CPU_STALL_EN = 0x1 + // Position of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Pos = 0x1 + // Bit mask of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Msk = 0x3e + // Position of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Pos = 0x6 + // Bit mask of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Msk = 0x3fc0 + // Position of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Pos = 0xe + // Bit mask of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Msk = 0xffc000 + // Position of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Pos = 0x18 + // Bit mask of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Msk = 0xff000000 + + // TIMER2 + // Position of ULPCP_TOUCH_START_WAIT field. + RTC_CNTL_TIMER2_ULPCP_TOUCH_START_WAIT_Pos = 0xf + // Bit mask of ULPCP_TOUCH_START_WAIT field. + RTC_CNTL_TIMER2_ULPCP_TOUCH_START_WAIT_Msk = 0xff8000 + // Position of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Pos = 0x18 + // Bit mask of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Msk = 0xff000000 + + // TIMER3 + // Position of WIFI_WAIT_TIMER field. + RTC_CNTL_TIMER3_WIFI_WAIT_TIMER_Pos = 0x0 + // Bit mask of WIFI_WAIT_TIMER field. + RTC_CNTL_TIMER3_WIFI_WAIT_TIMER_Msk = 0x1ff + // Position of WIFI_POWERUP_TIMER field. + RTC_CNTL_TIMER3_WIFI_POWERUP_TIMER_Pos = 0x9 + // Bit mask of WIFI_POWERUP_TIMER field. + RTC_CNTL_TIMER3_WIFI_POWERUP_TIMER_Msk = 0xfe00 + // Position of ROM_RAM_WAIT_TIMER field. + RTC_CNTL_TIMER3_ROM_RAM_WAIT_TIMER_Pos = 0x10 + // Bit mask of ROM_RAM_WAIT_TIMER field. + RTC_CNTL_TIMER3_ROM_RAM_WAIT_TIMER_Msk = 0x1ff0000 + // Position of ROM_RAM_POWERUP_TIMER field. + RTC_CNTL_TIMER3_ROM_RAM_POWERUP_TIMER_Pos = 0x19 + // Bit mask of ROM_RAM_POWERUP_TIMER field. + RTC_CNTL_TIMER3_ROM_RAM_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER4 + // Position of WAIT_TIMER field. + RTC_CNTL_TIMER4_WAIT_TIMER_Pos = 0x0 + // Bit mask of WAIT_TIMER field. + RTC_CNTL_TIMER4_WAIT_TIMER_Msk = 0x1ff + // Position of POWERUP_TIMER field. + RTC_CNTL_TIMER4_POWERUP_TIMER_Pos = 0x9 + // Bit mask of POWERUP_TIMER field. + RTC_CNTL_TIMER4_POWERUP_TIMER_Msk = 0xfe00 + // Position of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Pos = 0x10 + // Bit mask of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Msk = 0x1ff0000 + // Position of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Pos = 0x19 + // Bit mask of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER5 + // Position of ULP_CP_SUBTIMER_PREDIV field. + RTC_CNTL_TIMER5_ULP_CP_SUBTIMER_PREDIV_Pos = 0x0 + // Bit mask of ULP_CP_SUBTIMER_PREDIV field. + RTC_CNTL_TIMER5_ULP_CP_SUBTIMER_PREDIV_Msk = 0xff + // Position of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Pos = 0x8 + // Bit mask of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Msk = 0xff00 + // Position of RTCMEM_WAIT_TIMER field. + RTC_CNTL_TIMER5_RTCMEM_WAIT_TIMER_Pos = 0x10 + // Bit mask of RTCMEM_WAIT_TIMER field. + RTC_CNTL_TIMER5_RTCMEM_WAIT_TIMER_Msk = 0x1ff0000 + // Position of RTCMEM_POWERUP_TIMER field. + RTC_CNTL_TIMER5_RTCMEM_POWERUP_TIMER_Pos = 0x19 + // Bit mask of RTCMEM_POWERUP_TIMER field. + RTC_CNTL_TIMER5_RTCMEM_POWERUP_TIMER_Msk = 0xfe000000 + + // ANA_CONF + // Position of PLLA_FORCE_PD field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD_Pos = 0x17 + // Bit mask of PLLA_FORCE_PD field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD_Msk = 0x800000 + // Bit PLLA_FORCE_PD. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD = 0x800000 + // Position of PLLA_FORCE_PU field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU_Pos = 0x18 + // Bit mask of PLLA_FORCE_PU field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU_Msk = 0x1000000 + // Bit PLLA_FORCE_PU. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU = 0x1000000 + // Position of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Pos = 0x19 + // Bit mask of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Msk = 0x2000000 + // Bit BBPLL_CAL_SLP_START. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START = 0x2000000 + // Position of PVTMON_PU field. + RTC_CNTL_ANA_CONF_PVTMON_PU_Pos = 0x1a + // Bit mask of PVTMON_PU field. + RTC_CNTL_ANA_CONF_PVTMON_PU_Msk = 0x4000000 + // Bit PVTMON_PU. + RTC_CNTL_ANA_CONF_PVTMON_PU = 0x4000000 + // Position of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Pos = 0x1b + // Bit mask of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Msk = 0x8000000 + // Bit TXRF_I2C_PU. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU = 0x8000000 + // Position of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Pos = 0x1c + // Bit mask of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Msk = 0x10000000 + // Bit RFRX_PBUS_PU. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU = 0x10000000 + // Position of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Pos = 0x1e + // Bit mask of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Msk = 0x40000000 + // Bit CKGEN_I2C_PU. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU = 0x40000000 + // Position of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Pos = 0x1f + // Bit mask of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Msk = 0x80000000 + // Bit PLL_I2C_PU. + RTC_CNTL_ANA_CONF_PLL_I2C_PU = 0x80000000 + + // RESET_STATE + // Position of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Pos = 0x0 + // Bit mask of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Msk = 0x3f + // Position of RESET_CAUSE_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_APPCPU_Pos = 0x6 + // Bit mask of RESET_CAUSE_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_APPCPU_Msk = 0xfc0 + // Position of APPCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_APPCPU_STAT_VECTOR_SEL_Pos = 0xc + // Bit mask of APPCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_APPCPU_STAT_VECTOR_SEL_Msk = 0x1000 + // Bit APPCPU_STAT_VECTOR_SEL. + RTC_CNTL_RESET_STATE_APPCPU_STAT_VECTOR_SEL = 0x1000 + // Position of PROCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_PROCPU_STAT_VECTOR_SEL_Pos = 0xd + // Bit mask of PROCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_PROCPU_STAT_VECTOR_SEL_Msk = 0x2000 + // Bit PROCPU_STAT_VECTOR_SEL. + RTC_CNTL_RESET_STATE_PROCPU_STAT_VECTOR_SEL = 0x2000 + + // WAKEUP_STATE + // Position of WAKEUP_CAUSE field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_CAUSE_Pos = 0x0 + // Bit mask of WAKEUP_CAUSE field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_CAUSE_Msk = 0x7ff + // Position of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Pos = 0xb + // Bit mask of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Msk = 0x3ff800 + // Position of GPIO_WAKEUP_FILTER field. + RTC_CNTL_WAKEUP_STATE_GPIO_WAKEUP_FILTER_Pos = 0x16 + // Bit mask of GPIO_WAKEUP_FILTER field. + RTC_CNTL_WAKEUP_STATE_GPIO_WAKEUP_FILTER_Msk = 0x400000 + // Bit GPIO_WAKEUP_FILTER. + RTC_CNTL_WAKEUP_STATE_GPIO_WAKEUP_FILTER = 0x400000 + + // INT_ENA + // Position of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_SLP_WAKEUP_INT_ENA_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_SLP_WAKEUP_INT_ENA_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA. + RTC_CNTL_INT_ENA_SLP_WAKEUP_INT_ENA = 0x1 + // Position of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_SLP_REJECT_INT_ENA_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_SLP_REJECT_INT_ENA_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA. + RTC_CNTL_INT_ENA_SLP_REJECT_INT_ENA = 0x2 + // Position of SDIO_IDLE_INT_ENA field. + RTC_CNTL_INT_ENA_SDIO_IDLE_INT_ENA_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_ENA field. + RTC_CNTL_INT_ENA_SDIO_IDLE_INT_ENA_Msk = 0x4 + // Bit SDIO_IDLE_INT_ENA. + RTC_CNTL_INT_ENA_SDIO_IDLE_INT_ENA = 0x4 + // Position of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_WDT_INT_ENA_Pos = 0x3 + // Bit mask of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_WDT_INT_ENA_Msk = 0x8 + // Bit WDT_INT_ENA. + RTC_CNTL_INT_ENA_WDT_INT_ENA = 0x8 + // Position of TIME_VALID_INT_ENA field. + RTC_CNTL_INT_ENA_TIME_VALID_INT_ENA_Pos = 0x4 + // Bit mask of TIME_VALID_INT_ENA field. + RTC_CNTL_INT_ENA_TIME_VALID_INT_ENA_Msk = 0x10 + // Bit TIME_VALID_INT_ENA. + RTC_CNTL_INT_ENA_TIME_VALID_INT_ENA = 0x10 + // Position of ULP_CP_INT_ENA field. + RTC_CNTL_INT_ENA_ULP_CP_INT_ENA_Pos = 0x5 + // Bit mask of ULP_CP_INT_ENA field. + RTC_CNTL_INT_ENA_ULP_CP_INT_ENA_Msk = 0x20 + // Bit ULP_CP_INT_ENA. + RTC_CNTL_INT_ENA_ULP_CP_INT_ENA = 0x20 + // Position of TOUCH_INT_ENA field. + RTC_CNTL_INT_ENA_TOUCH_INT_ENA_Pos = 0x6 + // Bit mask of TOUCH_INT_ENA field. + RTC_CNTL_INT_ENA_TOUCH_INT_ENA_Msk = 0x40 + // Bit TOUCH_INT_ENA. + RTC_CNTL_INT_ENA_TOUCH_INT_ENA = 0x40 + // Position of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_BROWN_OUT_INT_ENA_Pos = 0x7 + // Bit mask of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_BROWN_OUT_INT_ENA_Msk = 0x80 + // Bit BROWN_OUT_INT_ENA. + RTC_CNTL_INT_ENA_BROWN_OUT_INT_ENA = 0x80 + // Position of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_MAIN_TIMER_INT_ENA_Pos = 0x8 + // Bit mask of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_MAIN_TIMER_INT_ENA_Msk = 0x100 + // Bit MAIN_TIMER_INT_ENA. + RTC_CNTL_INT_ENA_MAIN_TIMER_INT_ENA = 0x100 + + // INT_RAW + // Position of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_SLP_WAKEUP_INT_RAW_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_SLP_WAKEUP_INT_RAW_Msk = 0x1 + // Bit SLP_WAKEUP_INT_RAW. + RTC_CNTL_INT_RAW_SLP_WAKEUP_INT_RAW = 0x1 + // Position of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_SLP_REJECT_INT_RAW_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_SLP_REJECT_INT_RAW_Msk = 0x2 + // Bit SLP_REJECT_INT_RAW. + RTC_CNTL_INT_RAW_SLP_REJECT_INT_RAW = 0x2 + // Position of SDIO_IDLE_INT_RAW field. + RTC_CNTL_INT_RAW_SDIO_IDLE_INT_RAW_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_RAW field. + RTC_CNTL_INT_RAW_SDIO_IDLE_INT_RAW_Msk = 0x4 + // Bit SDIO_IDLE_INT_RAW. + RTC_CNTL_INT_RAW_SDIO_IDLE_INT_RAW = 0x4 + // Position of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_WDT_INT_RAW_Pos = 0x3 + // Bit mask of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_WDT_INT_RAW_Msk = 0x8 + // Bit WDT_INT_RAW. + RTC_CNTL_INT_RAW_WDT_INT_RAW = 0x8 + // Position of TIME_VALID_INT_RAW field. + RTC_CNTL_INT_RAW_TIME_VALID_INT_RAW_Pos = 0x4 + // Bit mask of TIME_VALID_INT_RAW field. + RTC_CNTL_INT_RAW_TIME_VALID_INT_RAW_Msk = 0x10 + // Bit TIME_VALID_INT_RAW. + RTC_CNTL_INT_RAW_TIME_VALID_INT_RAW = 0x10 + // Position of ULP_CP_INT_RAW field. + RTC_CNTL_INT_RAW_ULP_CP_INT_RAW_Pos = 0x5 + // Bit mask of ULP_CP_INT_RAW field. + RTC_CNTL_INT_RAW_ULP_CP_INT_RAW_Msk = 0x20 + // Bit ULP_CP_INT_RAW. + RTC_CNTL_INT_RAW_ULP_CP_INT_RAW = 0x20 + // Position of TOUCH_INT_RAW field. + RTC_CNTL_INT_RAW_TOUCH_INT_RAW_Pos = 0x6 + // Bit mask of TOUCH_INT_RAW field. + RTC_CNTL_INT_RAW_TOUCH_INT_RAW_Msk = 0x40 + // Bit TOUCH_INT_RAW. + RTC_CNTL_INT_RAW_TOUCH_INT_RAW = 0x40 + // Position of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_BROWN_OUT_INT_RAW_Pos = 0x7 + // Bit mask of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_BROWN_OUT_INT_RAW_Msk = 0x80 + // Bit BROWN_OUT_INT_RAW. + RTC_CNTL_INT_RAW_BROWN_OUT_INT_RAW = 0x80 + // Position of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_MAIN_TIMER_INT_RAW_Pos = 0x8 + // Bit mask of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_MAIN_TIMER_INT_RAW_Msk = 0x100 + // Bit MAIN_TIMER_INT_RAW. + RTC_CNTL_INT_RAW_MAIN_TIMER_INT_RAW = 0x100 + + // INT_ST + // Position of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_SLP_WAKEUP_INT_ST_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_SLP_WAKEUP_INT_ST_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ST. + RTC_CNTL_INT_ST_SLP_WAKEUP_INT_ST = 0x1 + // Position of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_SLP_REJECT_INT_ST_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_SLP_REJECT_INT_ST_Msk = 0x2 + // Bit SLP_REJECT_INT_ST. + RTC_CNTL_INT_ST_SLP_REJECT_INT_ST = 0x2 + // Position of SDIO_IDLE_INT_ST field. + RTC_CNTL_INT_ST_SDIO_IDLE_INT_ST_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_ST field. + RTC_CNTL_INT_ST_SDIO_IDLE_INT_ST_Msk = 0x4 + // Bit SDIO_IDLE_INT_ST. + RTC_CNTL_INT_ST_SDIO_IDLE_INT_ST = 0x4 + // Position of WDT_INT_ST field. + RTC_CNTL_INT_ST_WDT_INT_ST_Pos = 0x3 + // Bit mask of WDT_INT_ST field. + RTC_CNTL_INT_ST_WDT_INT_ST_Msk = 0x8 + // Bit WDT_INT_ST. + RTC_CNTL_INT_ST_WDT_INT_ST = 0x8 + // Position of TIME_VALID_INT_ST field. + RTC_CNTL_INT_ST_TIME_VALID_INT_ST_Pos = 0x4 + // Bit mask of TIME_VALID_INT_ST field. + RTC_CNTL_INT_ST_TIME_VALID_INT_ST_Msk = 0x10 + // Bit TIME_VALID_INT_ST. + RTC_CNTL_INT_ST_TIME_VALID_INT_ST = 0x10 + // Position of SAR_INT_ST field. + RTC_CNTL_INT_ST_SAR_INT_ST_Pos = 0x5 + // Bit mask of SAR_INT_ST field. + RTC_CNTL_INT_ST_SAR_INT_ST_Msk = 0x20 + // Bit SAR_INT_ST. + RTC_CNTL_INT_ST_SAR_INT_ST = 0x20 + // Position of TOUCH_INT_ST field. + RTC_CNTL_INT_ST_TOUCH_INT_ST_Pos = 0x6 + // Bit mask of TOUCH_INT_ST field. + RTC_CNTL_INT_ST_TOUCH_INT_ST_Msk = 0x40 + // Bit TOUCH_INT_ST. + RTC_CNTL_INT_ST_TOUCH_INT_ST = 0x40 + // Position of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_BROWN_OUT_INT_ST_Pos = 0x7 + // Bit mask of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_BROWN_OUT_INT_ST_Msk = 0x80 + // Bit BROWN_OUT_INT_ST. + RTC_CNTL_INT_ST_BROWN_OUT_INT_ST = 0x80 + // Position of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_MAIN_TIMER_INT_ST_Pos = 0x8 + // Bit mask of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_MAIN_TIMER_INT_ST_Msk = 0x100 + // Bit MAIN_TIMER_INT_ST. + RTC_CNTL_INT_ST_MAIN_TIMER_INT_ST = 0x100 + + // INT_CLR + // Position of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_SLP_WAKEUP_INT_CLR_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_SLP_WAKEUP_INT_CLR_Msk = 0x1 + // Bit SLP_WAKEUP_INT_CLR. + RTC_CNTL_INT_CLR_SLP_WAKEUP_INT_CLR = 0x1 + // Position of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_SLP_REJECT_INT_CLR_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_SLP_REJECT_INT_CLR_Msk = 0x2 + // Bit SLP_REJECT_INT_CLR. + RTC_CNTL_INT_CLR_SLP_REJECT_INT_CLR = 0x2 + // Position of SDIO_IDLE_INT_CLR field. + RTC_CNTL_INT_CLR_SDIO_IDLE_INT_CLR_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_CLR field. + RTC_CNTL_INT_CLR_SDIO_IDLE_INT_CLR_Msk = 0x4 + // Bit SDIO_IDLE_INT_CLR. + RTC_CNTL_INT_CLR_SDIO_IDLE_INT_CLR = 0x4 + // Position of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_WDT_INT_CLR_Pos = 0x3 + // Bit mask of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_WDT_INT_CLR_Msk = 0x8 + // Bit WDT_INT_CLR. + RTC_CNTL_INT_CLR_WDT_INT_CLR = 0x8 + // Position of TIME_VALID_INT_CLR field. + RTC_CNTL_INT_CLR_TIME_VALID_INT_CLR_Pos = 0x4 + // Bit mask of TIME_VALID_INT_CLR field. + RTC_CNTL_INT_CLR_TIME_VALID_INT_CLR_Msk = 0x10 + // Bit TIME_VALID_INT_CLR. + RTC_CNTL_INT_CLR_TIME_VALID_INT_CLR = 0x10 + // Position of SAR_INT_CLR field. + RTC_CNTL_INT_CLR_SAR_INT_CLR_Pos = 0x5 + // Bit mask of SAR_INT_CLR field. + RTC_CNTL_INT_CLR_SAR_INT_CLR_Msk = 0x20 + // Bit SAR_INT_CLR. + RTC_CNTL_INT_CLR_SAR_INT_CLR = 0x20 + // Position of TOUCH_INT_CLR field. + RTC_CNTL_INT_CLR_TOUCH_INT_CLR_Pos = 0x6 + // Bit mask of TOUCH_INT_CLR field. + RTC_CNTL_INT_CLR_TOUCH_INT_CLR_Msk = 0x40 + // Bit TOUCH_INT_CLR. + RTC_CNTL_INT_CLR_TOUCH_INT_CLR = 0x40 + // Position of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_BROWN_OUT_INT_CLR_Pos = 0x7 + // Bit mask of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_BROWN_OUT_INT_CLR_Msk = 0x80 + // Bit BROWN_OUT_INT_CLR. + RTC_CNTL_INT_CLR_BROWN_OUT_INT_CLR = 0x80 + // Position of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_MAIN_TIMER_INT_CLR_Pos = 0x8 + // Bit mask of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_MAIN_TIMER_INT_CLR_Msk = 0x100 + // Bit MAIN_TIMER_INT_CLR. + RTC_CNTL_INT_CLR_MAIN_TIMER_INT_CLR = 0x100 + + // STORE0 + // Position of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Pos = 0x0 + // Bit mask of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Msk = 0xffffffff + + // STORE1 + // Position of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Pos = 0x0 + // Bit mask of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Msk = 0xffffffff + + // STORE2 + // Position of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Pos = 0x0 + // Bit mask of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Msk = 0xffffffff + + // STORE3 + // Position of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Pos = 0x0 + // Bit mask of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Msk = 0xffffffff + + // EXT_XTL_CONF + // Position of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Pos = 0x1e + // Bit mask of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Msk = 0x40000000 + // Bit XTL_EXT_CTR_LV. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV = 0x40000000 + // Position of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Pos = 0x1f + // Bit mask of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Msk = 0x80000000 + // Bit XTL_EXT_CTR_EN. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN = 0x80000000 + + // EXT_WAKEUP_CONF + // Position of EXT_WAKEUP0_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP0_LV_Pos = 0x1e + // Bit mask of EXT_WAKEUP0_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP0_LV_Msk = 0x40000000 + // Bit EXT_WAKEUP0_LV. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP0_LV = 0x40000000 + // Position of EXT_WAKEUP1_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP1_LV_Pos = 0x1f + // Bit mask of EXT_WAKEUP1_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP1_LV_Msk = 0x80000000 + // Bit EXT_WAKEUP1_LV. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP1_LV = 0x80000000 + + // SLP_REJECT_CONF + // Position of GPIO_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_GPIO_REJECT_EN_Pos = 0x18 + // Bit mask of GPIO_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_GPIO_REJECT_EN_Msk = 0x1000000 + // Bit GPIO_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_GPIO_REJECT_EN = 0x1000000 + // Position of SDIO_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_SDIO_REJECT_EN_Pos = 0x19 + // Bit mask of SDIO_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_SDIO_REJECT_EN_Msk = 0x2000000 + // Bit SDIO_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_SDIO_REJECT_EN = 0x2000000 + // Position of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Pos = 0x1a + // Bit mask of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Msk = 0x4000000 + // Bit LIGHT_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN = 0x4000000 + // Position of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Pos = 0x1b + // Bit mask of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Msk = 0x8000000 + // Bit DEEP_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN = 0x8000000 + // Position of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CONF_REJECT_CAUSE_Pos = 0x1c + // Bit mask of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CONF_REJECT_CAUSE_Msk = 0xf0000000 + + // CPU_PERIOD_CONF + // Position of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Pos = 0x1d + // Bit mask of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Msk = 0x20000000 + // Bit CPUSEL_CONF. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF = 0x20000000 + // Position of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Pos = 0x1e + // Bit mask of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Msk = 0xc0000000 + + // SDIO_ACT_CONF + // Position of SDIO_ACT_DNUM field. + RTC_CNTL_SDIO_ACT_CONF_SDIO_ACT_DNUM_Pos = 0x16 + // Bit mask of SDIO_ACT_DNUM field. + RTC_CNTL_SDIO_ACT_CONF_SDIO_ACT_DNUM_Msk = 0xffc00000 + + // CLK_CONF + // Position of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Pos = 0x4 + // Bit mask of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Msk = 0x30 + // DIV128 + RTC_CNTL_CLK_CONF_CK8M_DIV_DIV128 = 0x0 + // DIV256 + RTC_CNTL_CLK_CONF_CK8M_DIV_DIV256 = 0x1 + // DIV512 + RTC_CNTL_CLK_CONF_CK8M_DIV_DIV512 = 0x2 + // DIV1024 + RTC_CNTL_CLK_CONF_CK8M_DIV_DIV1024 = 0x3 + // Position of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Pos = 0x6 + // Bit mask of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Msk = 0x40 + // Bit ENB_CK8M. + RTC_CNTL_CLK_CONF_ENB_CK8M = 0x40 + // Position of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Pos = 0x7 + // Bit mask of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Msk = 0x80 + // Bit ENB_CK8M_DIV. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV = 0x80 + // CK8M_DIV_256 + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_CK8M_DIV_256 = 0x0 + // CK8M + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_CK8M = 0x1 + // Position of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Pos = 0x8 + // Bit mask of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Msk = 0x100 + // Bit DIG_XTAL32K_EN. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN = 0x100 + // Position of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Pos = 0x9 + // Bit mask of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Msk = 0x200 + // Bit DIG_CLK8M_D256_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN = 0x200 + // Position of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Pos = 0xa + // Bit mask of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Msk = 0x400 + // Bit DIG_CLK8M_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN = 0x400 + // Position of CK8M_DFREQ_FORCE field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_FORCE_Pos = 0xb + // Bit mask of CK8M_DFREQ_FORCE field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_FORCE_Msk = 0x800 + // Bit CK8M_DFREQ_FORCE. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_FORCE = 0x800 + // Position of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Pos = 0xc + // Bit mask of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Msk = 0x7000 + // Position of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Pos = 0xf + // Bit mask of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Msk = 0x8000 + // Bit XTAL_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING = 0x8000 + // Position of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Pos = 0x10 + // Bit mask of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Msk = 0x10000 + // Bit CK8M_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING = 0x10000 + // Position of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Pos = 0x11 + // Bit mask of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Msk = 0x1fe0000 + // Position of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Pos = 0x19 + // Bit mask of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Msk = 0x2000000 + // Bit CK8M_FORCE_PD. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD = 0x2000000 + // Position of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Pos = 0x1a + // Bit mask of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Msk = 0x4000000 + // Bit CK8M_FORCE_PU. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU = 0x4000000 + // Position of SOC_CLK_SEL field. + RTC_CNTL_CLK_CONF_SOC_CLK_SEL_Pos = 0x1b + // Bit mask of SOC_CLK_SEL field. + RTC_CNTL_CLK_CONF_SOC_CLK_SEL_Msk = 0x18000000 + // XTAL + RTC_CNTL_CLK_CONF_SOC_CLK_SEL_XTAL = 0x0 + // PLL + RTC_CNTL_CLK_CONF_SOC_CLK_SEL_PLL = 0x1 + // CK8M + RTC_CNTL_CLK_CONF_SOC_CLK_SEL_CK8M = 0x2 + // APLL + RTC_CNTL_CLK_CONF_SOC_CLK_SEL_APLL = 0x3 + // Position of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Pos = 0x1d + // Bit mask of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Msk = 0x20000000 + // Bit FAST_CLK_RTC_SEL. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL = 0x20000000 + // XTAL_DIV_4 + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_XTAL_DIV_4 = 0x0 + // CK8M + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_CK8M = 0x1 + // Position of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Pos = 0x1e + // Bit mask of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Msk = 0xc0000000 + // SLOW_CK + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_SLOW_CK = 0x0 + // CK_XTAL_32K + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_CK_XTAL_32K = 0x1 + // CK8M_D256_OUT + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_CK8M_D256_OUT = 0x2 + + // SDIO_CONF + // Position of SDIO_PD_EN field. + RTC_CNTL_SDIO_CONF_SDIO_PD_EN_Pos = 0x15 + // Bit mask of SDIO_PD_EN field. + RTC_CNTL_SDIO_CONF_SDIO_PD_EN_Msk = 0x200000 + // Bit SDIO_PD_EN. + RTC_CNTL_SDIO_CONF_SDIO_PD_EN = 0x200000 + // Position of SDIO_FORCE field. + RTC_CNTL_SDIO_CONF_SDIO_FORCE_Pos = 0x16 + // Bit mask of SDIO_FORCE field. + RTC_CNTL_SDIO_CONF_SDIO_FORCE_Msk = 0x400000 + // Bit SDIO_FORCE. + RTC_CNTL_SDIO_CONF_SDIO_FORCE = 0x400000 + // Position of SDIO_TIEH field. + RTC_CNTL_SDIO_CONF_SDIO_TIEH_Pos = 0x17 + // Bit mask of SDIO_TIEH field. + RTC_CNTL_SDIO_CONF_SDIO_TIEH_Msk = 0x800000 + // Bit SDIO_TIEH. + RTC_CNTL_SDIO_CONF_SDIO_TIEH = 0x800000 + // Position of REG1P8_READY field. + RTC_CNTL_SDIO_CONF_REG1P8_READY_Pos = 0x18 + // Bit mask of REG1P8_READY field. + RTC_CNTL_SDIO_CONF_REG1P8_READY_Msk = 0x1000000 + // Bit REG1P8_READY. + RTC_CNTL_SDIO_CONF_REG1P8_READY = 0x1000000 + // Position of DREFL_SDIO field. + RTC_CNTL_SDIO_CONF_DREFL_SDIO_Pos = 0x19 + // Bit mask of DREFL_SDIO field. + RTC_CNTL_SDIO_CONF_DREFL_SDIO_Msk = 0x6000000 + // Position of DREFM_SDIO field. + RTC_CNTL_SDIO_CONF_DREFM_SDIO_Pos = 0x1b + // Bit mask of DREFM_SDIO field. + RTC_CNTL_SDIO_CONF_DREFM_SDIO_Msk = 0x18000000 + // Position of DREFH_SDIO field. + RTC_CNTL_SDIO_CONF_DREFH_SDIO_Pos = 0x1d + // Bit mask of DREFH_SDIO field. + RTC_CNTL_SDIO_CONF_DREFH_SDIO_Msk = 0x60000000 + // Position of XPD_SDIO field. + RTC_CNTL_SDIO_CONF_XPD_SDIO_Pos = 0x1f + // Bit mask of XPD_SDIO field. + RTC_CNTL_SDIO_CONF_XPD_SDIO_Msk = 0x80000000 + // Bit XPD_SDIO. + RTC_CNTL_SDIO_CONF_XPD_SDIO = 0x80000000 + + // BIAS_CONF + // Position of DBG_ATTEN field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_Pos = 0x18 + // Bit mask of DBG_ATTEN field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_Msk = 0x3000000 + // Position of ENB_SCK_XTAL field. + RTC_CNTL_BIAS_CONF_ENB_SCK_XTAL_Pos = 0x1a + // Bit mask of ENB_SCK_XTAL field. + RTC_CNTL_BIAS_CONF_ENB_SCK_XTAL_Msk = 0x4000000 + // Bit ENB_SCK_XTAL. + RTC_CNTL_BIAS_CONF_ENB_SCK_XTAL = 0x4000000 + // Position of INC_HEARTBEAT_REFRESH field. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_REFRESH_Pos = 0x1b + // Bit mask of INC_HEARTBEAT_REFRESH field. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_REFRESH_Msk = 0x8000000 + // Bit INC_HEARTBEAT_REFRESH. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_REFRESH = 0x8000000 + // Position of DEC_HEARTBEAT_PERIOD field. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_PERIOD_Pos = 0x1c + // Bit mask of DEC_HEARTBEAT_PERIOD field. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_PERIOD_Msk = 0x10000000 + // Bit DEC_HEARTBEAT_PERIOD. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_PERIOD = 0x10000000 + // Position of INC_HEARTBEAT_PERIOD field. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_PERIOD_Pos = 0x1d + // Bit mask of INC_HEARTBEAT_PERIOD field. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_PERIOD_Msk = 0x20000000 + // Bit INC_HEARTBEAT_PERIOD. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_PERIOD = 0x20000000 + // Position of DEC_HEARTBEAT_WIDTH field. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_WIDTH_Pos = 0x1e + // Bit mask of DEC_HEARTBEAT_WIDTH field. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_WIDTH_Msk = 0x40000000 + // Bit DEC_HEARTBEAT_WIDTH. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_WIDTH = 0x40000000 + // Position of RST_BIAS_I2C field. + RTC_CNTL_BIAS_CONF_RST_BIAS_I2C_Pos = 0x1f + // Bit mask of RST_BIAS_I2C field. + RTC_CNTL_BIAS_CONF_RST_BIAS_I2C_Msk = 0x80000000 + // Bit RST_BIAS_I2C. + RTC_CNTL_BIAS_CONF_RST_BIAS_I2C = 0x80000000 + + // REG + // Position of SCK_DCAP_FORCE field. + RTC_CNTL_REG_SCK_DCAP_FORCE_Pos = 0x7 + // Bit mask of SCK_DCAP_FORCE field. + RTC_CNTL_REG_SCK_DCAP_FORCE_Msk = 0x80 + // Bit SCK_DCAP_FORCE. + RTC_CNTL_REG_SCK_DCAP_FORCE = 0x80 + // Position of DIG_DBIAS_SLP field. + RTC_CNTL_REG_DIG_DBIAS_SLP_Pos = 0x8 + // Bit mask of DIG_DBIAS_SLP field. + RTC_CNTL_REG_DIG_DBIAS_SLP_Msk = 0x700 + // Position of DIG_DBIAS_WAK field. + RTC_CNTL_REG_DIG_DBIAS_WAK_Pos = 0xb + // Bit mask of DIG_DBIAS_WAK field. + RTC_CNTL_REG_DIG_DBIAS_WAK_Msk = 0x3800 + // Position of SCK_DCAP field. + RTC_CNTL_REG_SCK_DCAP_Pos = 0xe + // Bit mask of SCK_DCAP field. + RTC_CNTL_REG_SCK_DCAP_Msk = 0x3fc000 + // Position of DBIAS_SLP field. + RTC_CNTL_REG_DBIAS_SLP_Pos = 0x16 + // Bit mask of DBIAS_SLP field. + RTC_CNTL_REG_DBIAS_SLP_Msk = 0x1c00000 + // Position of DBIAS_WAK field. + RTC_CNTL_REG_DBIAS_WAK_Pos = 0x19 + // Bit mask of DBIAS_WAK field. + RTC_CNTL_REG_DBIAS_WAK_Msk = 0xe000000 + // Position of DBOOST_FORCE_PD field. + RTC_CNTL_REG_DBOOST_FORCE_PD_Pos = 0x1c + // Bit mask of DBOOST_FORCE_PD field. + RTC_CNTL_REG_DBOOST_FORCE_PD_Msk = 0x10000000 + // Bit DBOOST_FORCE_PD. + RTC_CNTL_REG_DBOOST_FORCE_PD = 0x10000000 + // Position of DBOOST_FORCE_PU field. + RTC_CNTL_REG_DBOOST_FORCE_PU_Pos = 0x1d + // Bit mask of DBOOST_FORCE_PU field. + RTC_CNTL_REG_DBOOST_FORCE_PU_Msk = 0x20000000 + // Bit DBOOST_FORCE_PU. + RTC_CNTL_REG_DBOOST_FORCE_PU = 0x20000000 + // Position of FORCE_PD field. + RTC_CNTL_REG_FORCE_PD_Pos = 0x1e + // Bit mask of FORCE_PD field. + RTC_CNTL_REG_FORCE_PD_Msk = 0x40000000 + // Bit FORCE_PD. + RTC_CNTL_REG_FORCE_PD = 0x40000000 + // Position of FORCE_PU field. + RTC_CNTL_REG_FORCE_PU_Pos = 0x1f + // Bit mask of FORCE_PU field. + RTC_CNTL_REG_FORCE_PU_Msk = 0x80000000 + // Bit FORCE_PU. + RTC_CNTL_REG_FORCE_PU = 0x80000000 + + // PWC + // Position of FASTMEM_FORCE_NOISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_NOISO_Pos = 0x0 + // Bit mask of FASTMEM_FORCE_NOISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_NOISO_Msk = 0x1 + // Bit FASTMEM_FORCE_NOISO. + RTC_CNTL_PWC_FASTMEM_FORCE_NOISO = 0x1 + // Position of FASTMEM_FORCE_ISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_ISO_Pos = 0x1 + // Bit mask of FASTMEM_FORCE_ISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_ISO_Msk = 0x2 + // Bit FASTMEM_FORCE_ISO. + RTC_CNTL_PWC_FASTMEM_FORCE_ISO = 0x2 + // Position of SLOWMEM_FORCE_NOISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_NOISO_Pos = 0x2 + // Bit mask of SLOWMEM_FORCE_NOISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_NOISO_Msk = 0x4 + // Bit SLOWMEM_FORCE_NOISO. + RTC_CNTL_PWC_SLOWMEM_FORCE_NOISO = 0x4 + // Position of SLOWMEM_FORCE_ISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_ISO_Pos = 0x3 + // Bit mask of SLOWMEM_FORCE_ISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_ISO_Msk = 0x8 + // Bit SLOWMEM_FORCE_ISO. + RTC_CNTL_PWC_SLOWMEM_FORCE_ISO = 0x8 + // Position of FORCE_ISO field. + RTC_CNTL_PWC_FORCE_ISO_Pos = 0x4 + // Bit mask of FORCE_ISO field. + RTC_CNTL_PWC_FORCE_ISO_Msk = 0x10 + // Bit FORCE_ISO. + RTC_CNTL_PWC_FORCE_ISO = 0x10 + // Position of FORCE_NOISO field. + RTC_CNTL_PWC_FORCE_NOISO_Pos = 0x5 + // Bit mask of FORCE_NOISO field. + RTC_CNTL_PWC_FORCE_NOISO_Msk = 0x20 + // Bit FORCE_NOISO. + RTC_CNTL_PWC_FORCE_NOISO = 0x20 + // Position of FASTMEM_FOLW_CPU field. + RTC_CNTL_PWC_FASTMEM_FOLW_CPU_Pos = 0x6 + // Bit mask of FASTMEM_FOLW_CPU field. + RTC_CNTL_PWC_FASTMEM_FOLW_CPU_Msk = 0x40 + // Bit FASTMEM_FOLW_CPU. + RTC_CNTL_PWC_FASTMEM_FOLW_CPU = 0x40 + // Position of FASTMEM_FORCE_LPD field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPD_Pos = 0x7 + // Bit mask of FASTMEM_FORCE_LPD field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPD_Msk = 0x80 + // Bit FASTMEM_FORCE_LPD. + RTC_CNTL_PWC_FASTMEM_FORCE_LPD = 0x80 + // Position of FASTMEM_FORCE_LPU field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPU_Pos = 0x8 + // Bit mask of FASTMEM_FORCE_LPU field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPU_Msk = 0x100 + // Bit FASTMEM_FORCE_LPU. + RTC_CNTL_PWC_FASTMEM_FORCE_LPU = 0x100 + // Position of SLOWMEM_FOLW_CPU field. + RTC_CNTL_PWC_SLOWMEM_FOLW_CPU_Pos = 0x9 + // Bit mask of SLOWMEM_FOLW_CPU field. + RTC_CNTL_PWC_SLOWMEM_FOLW_CPU_Msk = 0x200 + // Bit SLOWMEM_FOLW_CPU. + RTC_CNTL_PWC_SLOWMEM_FOLW_CPU = 0x200 + // Position of SLOWMEM_FORCE_LPD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPD_Pos = 0xa + // Bit mask of SLOWMEM_FORCE_LPD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPD_Msk = 0x400 + // Bit SLOWMEM_FORCE_LPD. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPD = 0x400 + // Position of SLOWMEM_FORCE_LPU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPU_Pos = 0xb + // Bit mask of SLOWMEM_FORCE_LPU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPU_Msk = 0x800 + // Bit SLOWMEM_FORCE_LPU. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPU = 0x800 + // Position of FASTMEM_FORCE_PD field. + RTC_CNTL_PWC_FASTMEM_FORCE_PD_Pos = 0xc + // Bit mask of FASTMEM_FORCE_PD field. + RTC_CNTL_PWC_FASTMEM_FORCE_PD_Msk = 0x1000 + // Bit FASTMEM_FORCE_PD. + RTC_CNTL_PWC_FASTMEM_FORCE_PD = 0x1000 + // Position of FASTMEM_FORCE_PU field. + RTC_CNTL_PWC_FASTMEM_FORCE_PU_Pos = 0xd + // Bit mask of FASTMEM_FORCE_PU field. + RTC_CNTL_PWC_FASTMEM_FORCE_PU_Msk = 0x2000 + // Bit FASTMEM_FORCE_PU. + RTC_CNTL_PWC_FASTMEM_FORCE_PU = 0x2000 + // Position of FASTMEM_PD_EN field. + RTC_CNTL_PWC_FASTMEM_PD_EN_Pos = 0xe + // Bit mask of FASTMEM_PD_EN field. + RTC_CNTL_PWC_FASTMEM_PD_EN_Msk = 0x4000 + // Bit FASTMEM_PD_EN. + RTC_CNTL_PWC_FASTMEM_PD_EN = 0x4000 + // Position of SLOWMEM_FORCE_PD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_PD_Pos = 0xf + // Bit mask of SLOWMEM_FORCE_PD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_PD_Msk = 0x8000 + // Bit SLOWMEM_FORCE_PD. + RTC_CNTL_PWC_SLOWMEM_FORCE_PD = 0x8000 + // Position of SLOWMEM_FORCE_PU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_PU_Pos = 0x10 + // Bit mask of SLOWMEM_FORCE_PU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_PU_Msk = 0x10000 + // Bit SLOWMEM_FORCE_PU. + RTC_CNTL_PWC_SLOWMEM_FORCE_PU = 0x10000 + // Position of SLOWMEM_PD_EN field. + RTC_CNTL_PWC_SLOWMEM_PD_EN_Pos = 0x11 + // Bit mask of SLOWMEM_PD_EN field. + RTC_CNTL_PWC_SLOWMEM_PD_EN_Msk = 0x20000 + // Bit SLOWMEM_PD_EN. + RTC_CNTL_PWC_SLOWMEM_PD_EN = 0x20000 + // Position of FORCE_PD field. + RTC_CNTL_PWC_FORCE_PD_Pos = 0x12 + // Bit mask of FORCE_PD field. + RTC_CNTL_PWC_FORCE_PD_Msk = 0x40000 + // Bit FORCE_PD. + RTC_CNTL_PWC_FORCE_PD = 0x40000 + // Position of FORCE_PU field. + RTC_CNTL_PWC_FORCE_PU_Pos = 0x13 + // Bit mask of FORCE_PU field. + RTC_CNTL_PWC_FORCE_PU_Msk = 0x80000 + // Bit FORCE_PU. + RTC_CNTL_PWC_FORCE_PU = 0x80000 + // Position of PD_EN field. + RTC_CNTL_PWC_PD_EN_Pos = 0x14 + // Bit mask of PD_EN field. + RTC_CNTL_PWC_PD_EN_Msk = 0x100000 + // Bit PD_EN. + RTC_CNTL_PWC_PD_EN = 0x100000 + + // DIG_PWC + // Position of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Msk = 0x8 + // Bit LSLP_MEM_FORCE_PD. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD = 0x8 + // Position of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Msk = 0x10 + // Bit LSLP_MEM_FORCE_PU. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU = 0x10 + // Position of ROM0_FORCE_PD field. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PD_Pos = 0x5 + // Bit mask of ROM0_FORCE_PD field. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PD_Msk = 0x20 + // Bit ROM0_FORCE_PD. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PD = 0x20 + // Position of ROM0_FORCE_PU field. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PU_Pos = 0x6 + // Bit mask of ROM0_FORCE_PU field. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PU_Msk = 0x40 + // Bit ROM0_FORCE_PU. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PU = 0x40 + // Position of INTER_RAM0_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PD_Pos = 0x7 + // Bit mask of INTER_RAM0_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PD_Msk = 0x80 + // Bit INTER_RAM0_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PD = 0x80 + // Position of INTER_RAM0_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PU_Pos = 0x8 + // Bit mask of INTER_RAM0_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PU_Msk = 0x100 + // Bit INTER_RAM0_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PU = 0x100 + // Position of INTER_RAM1_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PD_Pos = 0x9 + // Bit mask of INTER_RAM1_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PD_Msk = 0x200 + // Bit INTER_RAM1_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PD = 0x200 + // Position of INTER_RAM1_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PU_Pos = 0xa + // Bit mask of INTER_RAM1_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PU_Msk = 0x400 + // Bit INTER_RAM1_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PU = 0x400 + // Position of INTER_RAM2_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PD_Pos = 0xb + // Bit mask of INTER_RAM2_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PD_Msk = 0x800 + // Bit INTER_RAM2_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PD = 0x800 + // Position of INTER_RAM2_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PU_Pos = 0xc + // Bit mask of INTER_RAM2_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PU_Msk = 0x1000 + // Bit INTER_RAM2_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PU = 0x1000 + // Position of INTER_RAM3_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PD_Pos = 0xd + // Bit mask of INTER_RAM3_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PD_Msk = 0x2000 + // Bit INTER_RAM3_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PD = 0x2000 + // Position of INTER_RAM3_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PU_Pos = 0xe + // Bit mask of INTER_RAM3_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PU_Msk = 0x4000 + // Bit INTER_RAM3_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PU = 0x4000 + // Position of INTER_RAM4_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PD_Pos = 0xf + // Bit mask of INTER_RAM4_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PD_Msk = 0x8000 + // Bit INTER_RAM4_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PD = 0x8000 + // Position of INTER_RAM4_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PU_Pos = 0x10 + // Bit mask of INTER_RAM4_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PU_Msk = 0x10000 + // Bit INTER_RAM4_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PU = 0x10000 + // Position of WIFI_FORCE_PD field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD_Pos = 0x11 + // Bit mask of WIFI_FORCE_PD field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD_Msk = 0x20000 + // Bit WIFI_FORCE_PD. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD = 0x20000 + // Position of WIFI_FORCE_PU field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU_Pos = 0x12 + // Bit mask of WIFI_FORCE_PU field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU_Msk = 0x40000 + // Bit WIFI_FORCE_PU. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU = 0x40000 + // Position of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Pos = 0x13 + // Bit mask of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Msk = 0x80000 + // Bit DG_WRAP_FORCE_PD. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD = 0x80000 + // Position of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Pos = 0x14 + // Bit mask of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Msk = 0x100000 + // Bit DG_WRAP_FORCE_PU. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU = 0x100000 + // Position of ROM0_PD_EN field. + RTC_CNTL_DIG_PWC_ROM0_PD_EN_Pos = 0x18 + // Bit mask of ROM0_PD_EN field. + RTC_CNTL_DIG_PWC_ROM0_PD_EN_Msk = 0x1000000 + // Bit ROM0_PD_EN. + RTC_CNTL_DIG_PWC_ROM0_PD_EN = 0x1000000 + // Position of INTER_RAM0_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM0_PD_EN_Pos = 0x19 + // Bit mask of INTER_RAM0_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM0_PD_EN_Msk = 0x2000000 + // Bit INTER_RAM0_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM0_PD_EN = 0x2000000 + // Position of INTER_RAM1_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM1_PD_EN_Pos = 0x1a + // Bit mask of INTER_RAM1_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM1_PD_EN_Msk = 0x4000000 + // Bit INTER_RAM1_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM1_PD_EN = 0x4000000 + // Position of INTER_RAM2_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM2_PD_EN_Pos = 0x1b + // Bit mask of INTER_RAM2_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM2_PD_EN_Msk = 0x8000000 + // Bit INTER_RAM2_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM2_PD_EN = 0x8000000 + // Position of INTER_RAM3_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM3_PD_EN_Pos = 0x1c + // Bit mask of INTER_RAM3_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM3_PD_EN_Msk = 0x10000000 + // Bit INTER_RAM3_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM3_PD_EN = 0x10000000 + // Position of INTER_RAM4_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM4_PD_EN_Pos = 0x1d + // Bit mask of INTER_RAM4_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM4_PD_EN_Msk = 0x20000000 + // Bit INTER_RAM4_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM4_PD_EN = 0x20000000 + // Position of WIFI_PD_EN field. + RTC_CNTL_DIG_PWC_WIFI_PD_EN_Pos = 0x1e + // Bit mask of WIFI_PD_EN field. + RTC_CNTL_DIG_PWC_WIFI_PD_EN_Msk = 0x40000000 + // Bit WIFI_PD_EN. + RTC_CNTL_DIG_PWC_WIFI_PD_EN = 0x40000000 + // Position of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Pos = 0x1f + // Bit mask of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Msk = 0x80000000 + // Bit DG_WRAP_PD_EN. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN = 0x80000000 + + // DIG_ISO + // Position of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Pos = 0x7 + // Bit mask of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Msk = 0x80 + // Bit FORCE_OFF. + RTC_CNTL_DIG_ISO_FORCE_OFF = 0x80 + // Position of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Pos = 0x8 + // Bit mask of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Msk = 0x100 + // Bit FORCE_ON. + RTC_CNTL_DIG_ISO_FORCE_ON = 0x100 + // Position of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Pos = 0x9 + // Bit mask of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Msk = 0x200 + // Bit DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD = 0x200 + // Position of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Pos = 0xa + // Bit mask of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Msk = 0x400 + // Bit CLR_DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD = 0x400 + // Position of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Pos = 0xb + // Bit mask of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Msk = 0x800 + // Bit DG_PAD_AUTOHOLD_EN. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN = 0x800 + // Position of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Pos = 0xc + // Bit mask of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Msk = 0x1000 + // Bit DG_PAD_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO = 0x1000 + // Position of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Pos = 0xd + // Bit mask of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Msk = 0x2000 + // Bit DG_PAD_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO = 0x2000 + // Position of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Pos = 0xe + // Bit mask of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Msk = 0x4000 + // Bit DG_PAD_FORCE_UNHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD = 0x4000 + // Position of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Pos = 0xf + // Bit mask of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Msk = 0x8000 + // Bit DG_PAD_FORCE_HOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD = 0x8000 + // Position of ROM0_FORCE_ISO field. + RTC_CNTL_DIG_ISO_ROM0_FORCE_ISO_Pos = 0x10 + // Bit mask of ROM0_FORCE_ISO field. + RTC_CNTL_DIG_ISO_ROM0_FORCE_ISO_Msk = 0x10000 + // Bit ROM0_FORCE_ISO. + RTC_CNTL_DIG_ISO_ROM0_FORCE_ISO = 0x10000 + // Position of ROM0_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_ROM0_FORCE_NOISO_Pos = 0x11 + // Bit mask of ROM0_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_ROM0_FORCE_NOISO_Msk = 0x20000 + // Bit ROM0_FORCE_NOISO. + RTC_CNTL_DIG_ISO_ROM0_FORCE_NOISO = 0x20000 + // Position of INTER_RAM0_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_ISO_Pos = 0x12 + // Bit mask of INTER_RAM0_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_ISO_Msk = 0x40000 + // Bit INTER_RAM0_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_ISO = 0x40000 + // Position of INTER_RAM0_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_NOISO_Pos = 0x13 + // Bit mask of INTER_RAM0_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_NOISO_Msk = 0x80000 + // Bit INTER_RAM0_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_NOISO = 0x80000 + // Position of INTER_RAM1_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_ISO_Pos = 0x14 + // Bit mask of INTER_RAM1_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_ISO_Msk = 0x100000 + // Bit INTER_RAM1_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_ISO = 0x100000 + // Position of INTER_RAM1_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_NOISO_Pos = 0x15 + // Bit mask of INTER_RAM1_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_NOISO_Msk = 0x200000 + // Bit INTER_RAM1_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_NOISO = 0x200000 + // Position of INTER_RAM2_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_ISO_Pos = 0x16 + // Bit mask of INTER_RAM2_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_ISO_Msk = 0x400000 + // Bit INTER_RAM2_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_ISO = 0x400000 + // Position of INTER_RAM2_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_NOISO_Pos = 0x17 + // Bit mask of INTER_RAM2_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_NOISO_Msk = 0x800000 + // Bit INTER_RAM2_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_NOISO = 0x800000 + // Position of INTER_RAM3_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_ISO_Pos = 0x18 + // Bit mask of INTER_RAM3_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_ISO_Msk = 0x1000000 + // Bit INTER_RAM3_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_ISO = 0x1000000 + // Position of INTER_RAM3_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_NOISO_Pos = 0x19 + // Bit mask of INTER_RAM3_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_NOISO_Msk = 0x2000000 + // Bit INTER_RAM3_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_NOISO = 0x2000000 + // Position of INTER_RAM4_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_ISO_Pos = 0x1a + // Bit mask of INTER_RAM4_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_ISO_Msk = 0x4000000 + // Bit INTER_RAM4_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_ISO = 0x4000000 + // Position of INTER_RAM4_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_NOISO_Pos = 0x1b + // Bit mask of INTER_RAM4_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_NOISO_Msk = 0x8000000 + // Bit INTER_RAM4_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_NOISO = 0x8000000 + // Position of WIFI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO_Pos = 0x1c + // Bit mask of WIFI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO_Msk = 0x10000000 + // Bit WIFI_FORCE_ISO. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO = 0x10000000 + // Position of WIFI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO_Pos = 0x1d + // Bit mask of WIFI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO_Msk = 0x20000000 + // Bit WIFI_FORCE_NOISO. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO = 0x20000000 + // Position of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO = 0x40000000 + // Position of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Pos = 0x1f + // Bit mask of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Msk = 0x80000000 + // Bit DG_WRAP_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO = 0x80000000 + + // WDTCONFIG0 + // Position of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Pos = 0x7 + // Bit mask of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Msk = 0x80 + // Bit WDT_PAUSE_IN_SLP. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP = 0x80 + // Position of WDT_APPCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0x8 + // Bit mask of WDT_APPCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x100 + // Bit WDT_APPCPU_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x100 + // Position of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0x9 + // Bit mask of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x200 + // Bit WDT_PROCPU_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x200 + // Position of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xa + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x400 + // Bit WDT_FLASHBOOT_MOD_EN. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x400 + // Position of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xb + // Bit mask of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0x3800 + // Position of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0xe + // Bit mask of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x1c000 + // Position of WDT_LEVEL_INT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_LEVEL_INT_EN_Pos = 0x11 + // Bit mask of WDT_LEVEL_INT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_LEVEL_INT_EN_Msk = 0x20000 + // Bit WDT_LEVEL_INT_EN. + RTC_CNTL_WDTCONFIG0_WDT_LEVEL_INT_EN = 0x20000 + // Position of WDT_EDGE_INT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EDGE_INT_EN_Pos = 0x12 + // Bit mask of WDT_EDGE_INT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EDGE_INT_EN_Msk = 0x40000 + // Bit WDT_EDGE_INT_EN. + RTC_CNTL_WDTCONFIG0_WDT_EDGE_INT_EN = 0x40000 + // Position of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Pos = 0x13 + // Bit mask of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Msk = 0x380000 + // Position of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Pos = 0x16 + // Bit mask of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Msk = 0x1c00000 + // Position of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Pos = 0x19 + // Bit mask of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Msk = 0xe000000 + // Position of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Pos = 0x1c + // Bit mask of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Msk = 0x70000000 + // Position of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + RTC_CNTL_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1 + // Position of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG2 + // Position of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG3 + // Position of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG4 + // Position of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED + // Position of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Pos = 0x1f + // Bit mask of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Msk = 0x80000000 + // Bit WDT_FEED. + RTC_CNTL_WDTFEED_WDT_FEED = 0x80000000 + + // WDTWPROTECT + // Position of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // TEST_MUX + // Position of ENT_RTC field. + RTC_CNTL_TEST_MUX_ENT_RTC_Pos = 0x1d + // Bit mask of ENT_RTC field. + RTC_CNTL_TEST_MUX_ENT_RTC_Msk = 0x20000000 + // Bit ENT_RTC. + RTC_CNTL_TEST_MUX_ENT_RTC = 0x20000000 + // Position of DTEST_RTC field. + RTC_CNTL_TEST_MUX_DTEST_RTC_Pos = 0x1e + // Bit mask of DTEST_RTC field. + RTC_CNTL_TEST_MUX_DTEST_RTC_Msk = 0xc0000000 + + // SW_CPU_STALL + // Position of SW_STALL_APPCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_APPCPU_C1_Pos = 0x14 + // Bit mask of SW_STALL_APPCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_APPCPU_C1_Msk = 0x3f00000 + // Position of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Pos = 0x1a + // Bit mask of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Msk = 0xfc000000 + + // STORE4 + // Position of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Pos = 0x0 + // Bit mask of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Msk = 0xffffffff + + // STORE5 + // Position of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Pos = 0x0 + // Bit mask of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Msk = 0xffffffff + + // STORE6 + // Position of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Pos = 0x0 + // Bit mask of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Msk = 0xffffffff + + // STORE7 + // Position of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Pos = 0x0 + // Bit mask of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Msk = 0xffffffff + + // LOW_POWER_ST + // Position of LOW_POWER_DIAG0 field. + RTC_CNTL_LOW_POWER_ST_LOW_POWER_DIAG0_Pos = 0x0 + // Bit mask of LOW_POWER_DIAG0 field. + RTC_CNTL_LOW_POWER_ST_LOW_POWER_DIAG0_Msk = 0xffffffff + // Position of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Pos = 0x13 + // Bit mask of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Msk = 0x80000 + // Bit RDY_FOR_WAKEUP. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP = 0x80000 + + // DIAG1 + // Position of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG1_LOW_POWER_DIAG1_Pos = 0x0 + // Bit mask of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG1_LOW_POWER_DIAG1_Msk = 0xffffffff + + // HOLD_FORCE + // Position of ADC1_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_ADC1_HOLD_FORCE_Pos = 0x0 + // Bit mask of ADC1_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_ADC1_HOLD_FORCE_Msk = 0x1 + // Bit ADC1_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_ADC1_HOLD_FORCE = 0x1 + // Position of ADC2_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_ADC2_HOLD_FORCE_Pos = 0x1 + // Bit mask of ADC2_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_ADC2_HOLD_FORCE_Msk = 0x2 + // Bit ADC2_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_ADC2_HOLD_FORCE = 0x2 + // Position of PDAC1_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_PDAC1_HOLD_FORCE_Pos = 0x2 + // Bit mask of PDAC1_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_PDAC1_HOLD_FORCE_Msk = 0x4 + // Bit PDAC1_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_PDAC1_HOLD_FORCE = 0x4 + // Position of PDAC2_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_PDAC2_HOLD_FORCE_Pos = 0x3 + // Bit mask of PDAC2_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_PDAC2_HOLD_FORCE_Msk = 0x8 + // Bit PDAC2_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_PDAC2_HOLD_FORCE = 0x8 + // Position of SENSE1_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_SENSE1_HOLD_FORCE_Pos = 0x4 + // Bit mask of SENSE1_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_SENSE1_HOLD_FORCE_Msk = 0x10 + // Bit SENSE1_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_SENSE1_HOLD_FORCE = 0x10 + // Position of SENSE2_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_SENSE2_HOLD_FORCE_Pos = 0x5 + // Bit mask of SENSE2_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_SENSE2_HOLD_FORCE_Msk = 0x20 + // Bit SENSE2_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_SENSE2_HOLD_FORCE = 0x20 + // Position of SENSE3_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_SENSE3_HOLD_FORCE_Pos = 0x6 + // Bit mask of SENSE3_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_SENSE3_HOLD_FORCE_Msk = 0x40 + // Bit SENSE3_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_SENSE3_HOLD_FORCE = 0x40 + // Position of SENSE4_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_SENSE4_HOLD_FORCE_Pos = 0x7 + // Bit mask of SENSE4_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_SENSE4_HOLD_FORCE_Msk = 0x80 + // Bit SENSE4_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_SENSE4_HOLD_FORCE = 0x80 + // Position of TOUCH_PAD0_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD0_HOLD_FORCE_Pos = 0x8 + // Bit mask of TOUCH_PAD0_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD0_HOLD_FORCE_Msk = 0x100 + // Bit TOUCH_PAD0_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD0_HOLD_FORCE = 0x100 + // Position of TOUCH_PAD1_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD1_HOLD_FORCE_Pos = 0x9 + // Bit mask of TOUCH_PAD1_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD1_HOLD_FORCE_Msk = 0x200 + // Bit TOUCH_PAD1_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD1_HOLD_FORCE = 0x200 + // Position of TOUCH_PAD2_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD2_HOLD_FORCE_Pos = 0xa + // Bit mask of TOUCH_PAD2_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD2_HOLD_FORCE_Msk = 0x400 + // Bit TOUCH_PAD2_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD2_HOLD_FORCE = 0x400 + // Position of TOUCH_PAD3_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD3_HOLD_FORCE_Pos = 0xb + // Bit mask of TOUCH_PAD3_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD3_HOLD_FORCE_Msk = 0x800 + // Bit TOUCH_PAD3_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD3_HOLD_FORCE = 0x800 + // Position of TOUCH_PAD4_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD4_HOLD_FORCE_Pos = 0xc + // Bit mask of TOUCH_PAD4_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD4_HOLD_FORCE_Msk = 0x1000 + // Bit TOUCH_PAD4_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD4_HOLD_FORCE = 0x1000 + // Position of TOUCH_PAD5_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD5_HOLD_FORCE_Pos = 0xd + // Bit mask of TOUCH_PAD5_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD5_HOLD_FORCE_Msk = 0x2000 + // Bit TOUCH_PAD5_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD5_HOLD_FORCE = 0x2000 + // Position of TOUCH_PAD6_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD6_HOLD_FORCE_Pos = 0xe + // Bit mask of TOUCH_PAD6_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD6_HOLD_FORCE_Msk = 0x4000 + // Bit TOUCH_PAD6_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD6_HOLD_FORCE = 0x4000 + // Position of TOUCH_PAD7_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD7_HOLD_FORCE_Pos = 0xf + // Bit mask of TOUCH_PAD7_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD7_HOLD_FORCE_Msk = 0x8000 + // Bit TOUCH_PAD7_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_TOUCH_PAD7_HOLD_FORCE = 0x8000 + // Position of X32P_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_X32P_HOLD_FORCE_Pos = 0x10 + // Bit mask of X32P_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_X32P_HOLD_FORCE_Msk = 0x10000 + // Bit X32P_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_X32P_HOLD_FORCE = 0x10000 + // Position of X32N_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_X32N_HOLD_FORCE_Pos = 0x11 + // Bit mask of X32N_HOLD_FORCE field. + RTC_CNTL_HOLD_FORCE_X32N_HOLD_FORCE_Msk = 0x20000 + // Bit X32N_HOLD_FORCE. + RTC_CNTL_HOLD_FORCE_X32N_HOLD_FORCE = 0x20000 + + // EXT_WAKEUP1 + // Position of SEL field. + RTC_CNTL_EXT_WAKEUP1_SEL_Pos = 0x0 + // Bit mask of SEL field. + RTC_CNTL_EXT_WAKEUP1_SEL_Msk = 0x3ffff + // Position of STATUS_CLR field. + RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_Pos = 0x12 + // Bit mask of STATUS_CLR field. + RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_Msk = 0x40000 + // Bit STATUS_CLR. + RTC_CNTL_EXT_WAKEUP1_STATUS_CLR = 0x40000 + + // EXT_WAKEUP1_STATUS + // Position of EXT_WAKEUP1_STATUS field. + RTC_CNTL_EXT_WAKEUP1_STATUS_EXT_WAKEUP1_STATUS_Pos = 0x0 + // Bit mask of EXT_WAKEUP1_STATUS field. + RTC_CNTL_EXT_WAKEUP1_STATUS_EXT_WAKEUP1_STATUS_Msk = 0x3ffff + + // BROWN_OUT + // Position of RTC_MEM_PID_CONF field. + RTC_CNTL_BROWN_OUT_RTC_MEM_PID_CONF_Pos = 0x0 + // Bit mask of RTC_MEM_PID_CONF field. + RTC_CNTL_BROWN_OUT_RTC_MEM_PID_CONF_Msk = 0xff + // Position of RTC_MEM_CRC_START field. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_START_Pos = 0x8 + // Bit mask of RTC_MEM_CRC_START field. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_START_Msk = 0x100 + // Bit RTC_MEM_CRC_START. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_START = 0x100 + // Position of RTC_MEM_CRC_ADDR field. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_ADDR_Pos = 0x9 + // Bit mask of RTC_MEM_CRC_ADDR field. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_ADDR_Msk = 0xffe00 + // Position of CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_Pos = 0xe + // Bit mask of CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_Msk = 0x4000 + // Bit CLOSE_FLASH_ENA. + RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA = 0x4000 + // Position of PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_PD_RF_ENA_Pos = 0xf + // Bit mask of PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_PD_RF_ENA_Msk = 0x8000 + // Bit PD_RF_ENA. + RTC_CNTL_BROWN_OUT_PD_RF_ENA = 0x8000 + // Position of RST_WAIT field. + RTC_CNTL_BROWN_OUT_RST_WAIT_Pos = 0x10 + // Bit mask of RST_WAIT field. + RTC_CNTL_BROWN_OUT_RST_WAIT_Msk = 0x3ff0000 + // Position of RTC_MEM_CRC_LEN field. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_LEN_Pos = 0x14 + // Bit mask of RTC_MEM_CRC_LEN field. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_LEN_Msk = 0x7ff00000 + // Position of RST_ENA field. + RTC_CNTL_BROWN_OUT_RST_ENA_Pos = 0x1a + // Bit mask of RST_ENA field. + RTC_CNTL_BROWN_OUT_RST_ENA_Msk = 0x4000000 + // Bit RST_ENA. + RTC_CNTL_BROWN_OUT_RST_ENA = 0x4000000 + // Position of DBROWN_OUT_THRES field. + RTC_CNTL_BROWN_OUT_DBROWN_OUT_THRES_Pos = 0x1b + // Bit mask of DBROWN_OUT_THRES field. + RTC_CNTL_BROWN_OUT_DBROWN_OUT_THRES_Msk = 0x38000000 + // Position of ENA field. + RTC_CNTL_BROWN_OUT_ENA_Pos = 0x1e + // Bit mask of ENA field. + RTC_CNTL_BROWN_OUT_ENA_Msk = 0x40000000 + // Bit ENA. + RTC_CNTL_BROWN_OUT_ENA = 0x40000000 + // Position of DET field. + RTC_CNTL_BROWN_OUT_DET_Pos = 0x1f + // Bit mask of DET field. + RTC_CNTL_BROWN_OUT_DET_Msk = 0x80000000 + // Bit DET. + RTC_CNTL_BROWN_OUT_DET = 0x80000000 + // Position of RTC_MEM_CRC_FINISH field. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_FINISH_Pos = 0x1f + // Bit mask of RTC_MEM_CRC_FINISH field. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_FINISH_Msk = 0x80000000 + // Bit RTC_MEM_CRC_FINISH. + RTC_CNTL_BROWN_OUT_RTC_MEM_CRC_FINISH = 0x80000000 + + // DATE + // Position of CNTL_DATE field. + RTC_CNTL_DATE_CNTL_DATE_Pos = 0x0 + // Bit mask of CNTL_DATE field. + RTC_CNTL_DATE_CNTL_DATE_Msk = 0xfffffff +) + +// Constants for RTC_IO: Low-power Input/Output +const ( + // OUT + // Position of DATA field. + RTC_GPIO_OUT_DATA_Pos = 0xe + // Bit mask of DATA field. + RTC_GPIO_OUT_DATA_Msk = 0xffffc000 + + // OUT_W1TS + // Position of OUT_DATA_W1TS field. + RTC_GPIO_OUT_W1TS_OUT_DATA_W1TS_Pos = 0xe + // Bit mask of OUT_DATA_W1TS field. + RTC_GPIO_OUT_W1TS_OUT_DATA_W1TS_Msk = 0xffffc000 + + // OUT_W1TC + // Position of OUT_DATA_W1TC field. + RTC_GPIO_OUT_W1TC_OUT_DATA_W1TC_Pos = 0xe + // Bit mask of OUT_DATA_W1TC field. + RTC_GPIO_OUT_W1TC_OUT_DATA_W1TC_Msk = 0xffffc000 + + // ENABLE + // Position of ENABLE field. + RTC_GPIO_ENABLE_ENABLE_Pos = 0xe + // Bit mask of ENABLE field. + RTC_GPIO_ENABLE_ENABLE_Msk = 0xffffc000 + + // ENABLE_W1TS + // Position of ENABLE_W1TS field. + RTC_GPIO_ENABLE_W1TS_ENABLE_W1TS_Pos = 0xe + // Bit mask of ENABLE_W1TS field. + RTC_GPIO_ENABLE_W1TS_ENABLE_W1TS_Msk = 0xffffc000 + + // ENABLE_W1TC + // Position of ENABLE_W1TC field. + RTC_GPIO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0xe + // Bit mask of ENABLE_W1TC field. + RTC_GPIO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0xffffc000 + + // STATUS + // Position of INT field. + RTC_GPIO_STATUS_INT_Pos = 0xe + // Bit mask of INT field. + RTC_GPIO_STATUS_INT_Msk = 0xffffc000 + + // STATUS_W1TS + // Position of STATUS_INT_W1TS field. + RTC_GPIO_STATUS_W1TS_STATUS_INT_W1TS_Pos = 0xe + // Bit mask of STATUS_INT_W1TS field. + RTC_GPIO_STATUS_W1TS_STATUS_INT_W1TS_Msk = 0xffffc000 + + // STATUS_W1TC + // Position of STATUS_INT_W1TC field. + RTC_GPIO_STATUS_W1TC_STATUS_INT_W1TC_Pos = 0xe + // Bit mask of STATUS_INT_W1TC field. + RTC_GPIO_STATUS_W1TC_STATUS_INT_W1TC_Msk = 0xffffc000 + + // IN + // Position of NEXT field. + RTC_GPIO_IN_NEXT_Pos = 0xe + // Bit mask of NEXT field. + RTC_GPIO_IN_NEXT_Msk = 0xffffc000 + + // PIN0 + // Position of PAD_DRIVER field. + RTC_GPIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_GPIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_GPIO_PIN_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_GPIO_PIN_WAKEUP_ENABLE = 0x400 + + // RTC_DEBUG_SEL + // Position of DEBUG_SEL0 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL0_Pos = 0x0 + // Bit mask of DEBUG_SEL0 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL0_Msk = 0x1f + // Position of DEBUG_SEL1 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL1_Pos = 0x5 + // Bit mask of DEBUG_SEL1 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL1_Msk = 0x3e0 + // Position of DEBUG_SEL2 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL2_Pos = 0xa + // Bit mask of DEBUG_SEL2 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL2_Msk = 0x7c00 + // Position of DEBUG_SEL3 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL3_Pos = 0xf + // Bit mask of DEBUG_SEL3 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL3_Msk = 0xf8000 + // Position of DEBUG_SEL4 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL4_Pos = 0x14 + // Bit mask of DEBUG_SEL4 field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_SEL4_Msk = 0x1f00000 + // Position of DEBUG_12M_NO_GATING field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_12M_NO_GATING_Pos = 0x19 + // Bit mask of DEBUG_12M_NO_GATING field. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_12M_NO_GATING_Msk = 0x2000000 + // Bit DEBUG_12M_NO_GATING. + RTC_GPIO_RTC_DEBUG_SEL_DEBUG_12M_NO_GATING = 0x2000000 + + // DIG_PAD_HOLD + // Position of DIG_PAD_HOLD field. + RTC_GPIO_DIG_PAD_HOLD_DIG_PAD_HOLD_Pos = 0x0 + // Bit mask of DIG_PAD_HOLD field. + RTC_GPIO_DIG_PAD_HOLD_DIG_PAD_HOLD_Msk = 0xffffffff + + // HALL_SENS + // Position of HALL_PHASE field. + RTC_GPIO_HALL_SENS_HALL_PHASE_Pos = 0x1e + // Bit mask of HALL_PHASE field. + RTC_GPIO_HALL_SENS_HALL_PHASE_Msk = 0x40000000 + // Bit HALL_PHASE. + RTC_GPIO_HALL_SENS_HALL_PHASE = 0x40000000 + // Position of XPD_HALL field. + RTC_GPIO_HALL_SENS_XPD_HALL_Pos = 0x1f + // Bit mask of XPD_HALL field. + RTC_GPIO_HALL_SENS_XPD_HALL_Msk = 0x80000000 + // Bit XPD_HALL. + RTC_GPIO_HALL_SENS_XPD_HALL = 0x80000000 + + // SENSOR_PADS + // Position of SENSE4_FUN_IE field. + RTC_GPIO_SENSOR_PADS_SENSE4_FUN_IE_Pos = 0x4 + // Bit mask of SENSE4_FUN_IE field. + RTC_GPIO_SENSOR_PADS_SENSE4_FUN_IE_Msk = 0x10 + // Bit SENSE4_FUN_IE. + RTC_GPIO_SENSOR_PADS_SENSE4_FUN_IE = 0x10 + // Position of SENSE4_SLP_IE field. + RTC_GPIO_SENSOR_PADS_SENSE4_SLP_IE_Pos = 0x5 + // Bit mask of SENSE4_SLP_IE field. + RTC_GPIO_SENSOR_PADS_SENSE4_SLP_IE_Msk = 0x20 + // Bit SENSE4_SLP_IE. + RTC_GPIO_SENSOR_PADS_SENSE4_SLP_IE = 0x20 + // Position of SENSE4_SLP_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE4_SLP_SEL_Pos = 0x6 + // Bit mask of SENSE4_SLP_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE4_SLP_SEL_Msk = 0x40 + // Bit SENSE4_SLP_SEL. + RTC_GPIO_SENSOR_PADS_SENSE4_SLP_SEL = 0x40 + // Position of SENSE4_FUN_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE4_FUN_SEL_Pos = 0x7 + // Bit mask of SENSE4_FUN_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE4_FUN_SEL_Msk = 0x180 + // Position of SENSE3_FUN_IE field. + RTC_GPIO_SENSOR_PADS_SENSE3_FUN_IE_Pos = 0x9 + // Bit mask of SENSE3_FUN_IE field. + RTC_GPIO_SENSOR_PADS_SENSE3_FUN_IE_Msk = 0x200 + // Bit SENSE3_FUN_IE. + RTC_GPIO_SENSOR_PADS_SENSE3_FUN_IE = 0x200 + // Position of SENSE3_SLP_IE field. + RTC_GPIO_SENSOR_PADS_SENSE3_SLP_IE_Pos = 0xa + // Bit mask of SENSE3_SLP_IE field. + RTC_GPIO_SENSOR_PADS_SENSE3_SLP_IE_Msk = 0x400 + // Bit SENSE3_SLP_IE. + RTC_GPIO_SENSOR_PADS_SENSE3_SLP_IE = 0x400 + // Position of SENSE3_SLP_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE3_SLP_SEL_Pos = 0xb + // Bit mask of SENSE3_SLP_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE3_SLP_SEL_Msk = 0x800 + // Bit SENSE3_SLP_SEL. + RTC_GPIO_SENSOR_PADS_SENSE3_SLP_SEL = 0x800 + // Position of SENSE3_FUN_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE3_FUN_SEL_Pos = 0xc + // Bit mask of SENSE3_FUN_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE3_FUN_SEL_Msk = 0x3000 + // Position of SENSE2_FUN_IE field. + RTC_GPIO_SENSOR_PADS_SENSE2_FUN_IE_Pos = 0xe + // Bit mask of SENSE2_FUN_IE field. + RTC_GPIO_SENSOR_PADS_SENSE2_FUN_IE_Msk = 0x4000 + // Bit SENSE2_FUN_IE. + RTC_GPIO_SENSOR_PADS_SENSE2_FUN_IE = 0x4000 + // Position of SENSE2_SLP_IE field. + RTC_GPIO_SENSOR_PADS_SENSE2_SLP_IE_Pos = 0xf + // Bit mask of SENSE2_SLP_IE field. + RTC_GPIO_SENSOR_PADS_SENSE2_SLP_IE_Msk = 0x8000 + // Bit SENSE2_SLP_IE. + RTC_GPIO_SENSOR_PADS_SENSE2_SLP_IE = 0x8000 + // Position of SENSE2_SLP_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE2_SLP_SEL_Pos = 0x10 + // Bit mask of SENSE2_SLP_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE2_SLP_SEL_Msk = 0x10000 + // Bit SENSE2_SLP_SEL. + RTC_GPIO_SENSOR_PADS_SENSE2_SLP_SEL = 0x10000 + // Position of SENSE2_FUN_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE2_FUN_SEL_Pos = 0x11 + // Bit mask of SENSE2_FUN_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE2_FUN_SEL_Msk = 0x60000 + // Position of SENSE1_FUN_IE field. + RTC_GPIO_SENSOR_PADS_SENSE1_FUN_IE_Pos = 0x13 + // Bit mask of SENSE1_FUN_IE field. + RTC_GPIO_SENSOR_PADS_SENSE1_FUN_IE_Msk = 0x80000 + // Bit SENSE1_FUN_IE. + RTC_GPIO_SENSOR_PADS_SENSE1_FUN_IE = 0x80000 + // Position of SENSE1_SLP_IE field. + RTC_GPIO_SENSOR_PADS_SENSE1_SLP_IE_Pos = 0x14 + // Bit mask of SENSE1_SLP_IE field. + RTC_GPIO_SENSOR_PADS_SENSE1_SLP_IE_Msk = 0x100000 + // Bit SENSE1_SLP_IE. + RTC_GPIO_SENSOR_PADS_SENSE1_SLP_IE = 0x100000 + // Position of SENSE1_SLP_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE1_SLP_SEL_Pos = 0x15 + // Bit mask of SENSE1_SLP_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE1_SLP_SEL_Msk = 0x200000 + // Bit SENSE1_SLP_SEL. + RTC_GPIO_SENSOR_PADS_SENSE1_SLP_SEL = 0x200000 + // Position of SENSE1_FUN_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE1_FUN_SEL_Pos = 0x16 + // Bit mask of SENSE1_FUN_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE1_FUN_SEL_Msk = 0xc00000 + // Position of SENSE4_MUX_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE4_MUX_SEL_Pos = 0x18 + // Bit mask of SENSE4_MUX_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE4_MUX_SEL_Msk = 0x1000000 + // Bit SENSE4_MUX_SEL. + RTC_GPIO_SENSOR_PADS_SENSE4_MUX_SEL = 0x1000000 + // Position of SENSE3_MUX_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE3_MUX_SEL_Pos = 0x19 + // Bit mask of SENSE3_MUX_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE3_MUX_SEL_Msk = 0x2000000 + // Bit SENSE3_MUX_SEL. + RTC_GPIO_SENSOR_PADS_SENSE3_MUX_SEL = 0x2000000 + // Position of SENSE2_MUX_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE2_MUX_SEL_Pos = 0x1a + // Bit mask of SENSE2_MUX_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE2_MUX_SEL_Msk = 0x4000000 + // Bit SENSE2_MUX_SEL. + RTC_GPIO_SENSOR_PADS_SENSE2_MUX_SEL = 0x4000000 + // Position of SENSE1_MUX_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE1_MUX_SEL_Pos = 0x1b + // Bit mask of SENSE1_MUX_SEL field. + RTC_GPIO_SENSOR_PADS_SENSE1_MUX_SEL_Msk = 0x8000000 + // Bit SENSE1_MUX_SEL. + RTC_GPIO_SENSOR_PADS_SENSE1_MUX_SEL = 0x8000000 + // Position of SENSE4_HOLD field. + RTC_GPIO_SENSOR_PADS_SENSE4_HOLD_Pos = 0x1c + // Bit mask of SENSE4_HOLD field. + RTC_GPIO_SENSOR_PADS_SENSE4_HOLD_Msk = 0x10000000 + // Bit SENSE4_HOLD. + RTC_GPIO_SENSOR_PADS_SENSE4_HOLD = 0x10000000 + // Position of SENSE3_HOLD field. + RTC_GPIO_SENSOR_PADS_SENSE3_HOLD_Pos = 0x1d + // Bit mask of SENSE3_HOLD field. + RTC_GPIO_SENSOR_PADS_SENSE3_HOLD_Msk = 0x20000000 + // Bit SENSE3_HOLD. + RTC_GPIO_SENSOR_PADS_SENSE3_HOLD = 0x20000000 + // Position of SENSE2_HOLD field. + RTC_GPIO_SENSOR_PADS_SENSE2_HOLD_Pos = 0x1e + // Bit mask of SENSE2_HOLD field. + RTC_GPIO_SENSOR_PADS_SENSE2_HOLD_Msk = 0x40000000 + // Bit SENSE2_HOLD. + RTC_GPIO_SENSOR_PADS_SENSE2_HOLD = 0x40000000 + // Position of SENSE1_HOLD field. + RTC_GPIO_SENSOR_PADS_SENSE1_HOLD_Pos = 0x1f + // Bit mask of SENSE1_HOLD field. + RTC_GPIO_SENSOR_PADS_SENSE1_HOLD_Msk = 0x80000000 + // Bit SENSE1_HOLD. + RTC_GPIO_SENSOR_PADS_SENSE1_HOLD = 0x80000000 + + // ADC_PAD + // Position of ADC2_FUN_IE field. + RTC_GPIO_ADC_PAD_ADC2_FUN_IE_Pos = 0x12 + // Bit mask of ADC2_FUN_IE field. + RTC_GPIO_ADC_PAD_ADC2_FUN_IE_Msk = 0x40000 + // Bit ADC2_FUN_IE. + RTC_GPIO_ADC_PAD_ADC2_FUN_IE = 0x40000 + // Position of ADC2_SLP_IE field. + RTC_GPIO_ADC_PAD_ADC2_SLP_IE_Pos = 0x13 + // Bit mask of ADC2_SLP_IE field. + RTC_GPIO_ADC_PAD_ADC2_SLP_IE_Msk = 0x80000 + // Bit ADC2_SLP_IE. + RTC_GPIO_ADC_PAD_ADC2_SLP_IE = 0x80000 + // Position of ADC2_SLP_SEL field. + RTC_GPIO_ADC_PAD_ADC2_SLP_SEL_Pos = 0x14 + // Bit mask of ADC2_SLP_SEL field. + RTC_GPIO_ADC_PAD_ADC2_SLP_SEL_Msk = 0x100000 + // Bit ADC2_SLP_SEL. + RTC_GPIO_ADC_PAD_ADC2_SLP_SEL = 0x100000 + // Position of ADC2_FUN_SEL field. + RTC_GPIO_ADC_PAD_ADC2_FUN_SEL_Pos = 0x15 + // Bit mask of ADC2_FUN_SEL field. + RTC_GPIO_ADC_PAD_ADC2_FUN_SEL_Msk = 0x600000 + // Position of ADC1_FUN_IE field. + RTC_GPIO_ADC_PAD_ADC1_FUN_IE_Pos = 0x17 + // Bit mask of ADC1_FUN_IE field. + RTC_GPIO_ADC_PAD_ADC1_FUN_IE_Msk = 0x800000 + // Bit ADC1_FUN_IE. + RTC_GPIO_ADC_PAD_ADC1_FUN_IE = 0x800000 + // Position of ADC1_SLP_IE field. + RTC_GPIO_ADC_PAD_ADC1_SLP_IE_Pos = 0x18 + // Bit mask of ADC1_SLP_IE field. + RTC_GPIO_ADC_PAD_ADC1_SLP_IE_Msk = 0x1000000 + // Bit ADC1_SLP_IE. + RTC_GPIO_ADC_PAD_ADC1_SLP_IE = 0x1000000 + // Position of ADC1_SLP_SEL field. + RTC_GPIO_ADC_PAD_ADC1_SLP_SEL_Pos = 0x19 + // Bit mask of ADC1_SLP_SEL field. + RTC_GPIO_ADC_PAD_ADC1_SLP_SEL_Msk = 0x2000000 + // Bit ADC1_SLP_SEL. + RTC_GPIO_ADC_PAD_ADC1_SLP_SEL = 0x2000000 + // Position of ADC1_FUN_SEL field. + RTC_GPIO_ADC_PAD_ADC1_FUN_SEL_Pos = 0x1a + // Bit mask of ADC1_FUN_SEL field. + RTC_GPIO_ADC_PAD_ADC1_FUN_SEL_Msk = 0xc000000 + // Position of ADC2_MUX_SEL field. + RTC_GPIO_ADC_PAD_ADC2_MUX_SEL_Pos = 0x1c + // Bit mask of ADC2_MUX_SEL field. + RTC_GPIO_ADC_PAD_ADC2_MUX_SEL_Msk = 0x10000000 + // Bit ADC2_MUX_SEL. + RTC_GPIO_ADC_PAD_ADC2_MUX_SEL = 0x10000000 + // Position of ADC1_MUX_SEL field. + RTC_GPIO_ADC_PAD_ADC1_MUX_SEL_Pos = 0x1d + // Bit mask of ADC1_MUX_SEL field. + RTC_GPIO_ADC_PAD_ADC1_MUX_SEL_Msk = 0x20000000 + // Bit ADC1_MUX_SEL. + RTC_GPIO_ADC_PAD_ADC1_MUX_SEL = 0x20000000 + // Position of ADC2_HOLD field. + RTC_GPIO_ADC_PAD_ADC2_HOLD_Pos = 0x1e + // Bit mask of ADC2_HOLD field. + RTC_GPIO_ADC_PAD_ADC2_HOLD_Msk = 0x40000000 + // Bit ADC2_HOLD. + RTC_GPIO_ADC_PAD_ADC2_HOLD = 0x40000000 + // Position of ADC1_HOLD field. + RTC_GPIO_ADC_PAD_ADC1_HOLD_Pos = 0x1f + // Bit mask of ADC1_HOLD field. + RTC_GPIO_ADC_PAD_ADC1_HOLD_Msk = 0x80000000 + // Bit ADC1_HOLD. + RTC_GPIO_ADC_PAD_ADC1_HOLD = 0x80000000 + + // PAD_DAC1 + // Position of PDAC1_DAC_XPD_FORCE field. + RTC_GPIO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Pos = 0xa + // Bit mask of PDAC1_DAC_XPD_FORCE field. + RTC_GPIO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Msk = 0x400 + // Bit PDAC1_DAC_XPD_FORCE. + RTC_GPIO_PAD_DAC1_PDAC1_DAC_XPD_FORCE = 0x400 + // Position of PDAC1_FUN_IE field. + RTC_GPIO_PAD_DAC1_PDAC1_FUN_IE_Pos = 0xb + // Bit mask of PDAC1_FUN_IE field. + RTC_GPIO_PAD_DAC1_PDAC1_FUN_IE_Msk = 0x800 + // Bit PDAC1_FUN_IE. + RTC_GPIO_PAD_DAC1_PDAC1_FUN_IE = 0x800 + // Position of PDAC1_SLP_OE field. + RTC_GPIO_PAD_DAC1_PDAC1_SLP_OE_Pos = 0xc + // Bit mask of PDAC1_SLP_OE field. + RTC_GPIO_PAD_DAC1_PDAC1_SLP_OE_Msk = 0x1000 + // Bit PDAC1_SLP_OE. + RTC_GPIO_PAD_DAC1_PDAC1_SLP_OE = 0x1000 + // Position of PDAC1_SLP_IE field. + RTC_GPIO_PAD_DAC1_PDAC1_SLP_IE_Pos = 0xd + // Bit mask of PDAC1_SLP_IE field. + RTC_GPIO_PAD_DAC1_PDAC1_SLP_IE_Msk = 0x2000 + // Bit PDAC1_SLP_IE. + RTC_GPIO_PAD_DAC1_PDAC1_SLP_IE = 0x2000 + // Position of PDAC1_SLP_SEL field. + RTC_GPIO_PAD_DAC1_PDAC1_SLP_SEL_Pos = 0xe + // Bit mask of PDAC1_SLP_SEL field. + RTC_GPIO_PAD_DAC1_PDAC1_SLP_SEL_Msk = 0x4000 + // Bit PDAC1_SLP_SEL. + RTC_GPIO_PAD_DAC1_PDAC1_SLP_SEL = 0x4000 + // Position of PDAC1_FUN_SEL field. + RTC_GPIO_PAD_DAC1_PDAC1_FUN_SEL_Pos = 0xf + // Bit mask of PDAC1_FUN_SEL field. + RTC_GPIO_PAD_DAC1_PDAC1_FUN_SEL_Msk = 0x18000 + // Position of PDAC1_MUX_SEL field. + RTC_GPIO_PAD_DAC1_PDAC1_MUX_SEL_Pos = 0x11 + // Bit mask of PDAC1_MUX_SEL field. + RTC_GPIO_PAD_DAC1_PDAC1_MUX_SEL_Msk = 0x20000 + // Bit PDAC1_MUX_SEL. + RTC_GPIO_PAD_DAC1_PDAC1_MUX_SEL = 0x20000 + // Position of PDAC1_XPD_DAC field. + RTC_GPIO_PAD_DAC1_PDAC1_XPD_DAC_Pos = 0x12 + // Bit mask of PDAC1_XPD_DAC field. + RTC_GPIO_PAD_DAC1_PDAC1_XPD_DAC_Msk = 0x40000 + // Bit PDAC1_XPD_DAC. + RTC_GPIO_PAD_DAC1_PDAC1_XPD_DAC = 0x40000 + // Position of PDAC1_DAC field. + RTC_GPIO_PAD_DAC1_PDAC1_DAC_Pos = 0x13 + // Bit mask of PDAC1_DAC field. + RTC_GPIO_PAD_DAC1_PDAC1_DAC_Msk = 0x7f80000 + // Position of PDAC1_RUE field. + RTC_GPIO_PAD_DAC1_PDAC1_RUE_Pos = 0x1b + // Bit mask of PDAC1_RUE field. + RTC_GPIO_PAD_DAC1_PDAC1_RUE_Msk = 0x8000000 + // Bit PDAC1_RUE. + RTC_GPIO_PAD_DAC1_PDAC1_RUE = 0x8000000 + // Position of PDAC1_RDE field. + RTC_GPIO_PAD_DAC1_PDAC1_RDE_Pos = 0x1c + // Bit mask of PDAC1_RDE field. + RTC_GPIO_PAD_DAC1_PDAC1_RDE_Msk = 0x10000000 + // Bit PDAC1_RDE. + RTC_GPIO_PAD_DAC1_PDAC1_RDE = 0x10000000 + // Position of PDAC1_HOLD field. + RTC_GPIO_PAD_DAC1_PDAC1_HOLD_Pos = 0x1d + // Bit mask of PDAC1_HOLD field. + RTC_GPIO_PAD_DAC1_PDAC1_HOLD_Msk = 0x20000000 + // Bit PDAC1_HOLD. + RTC_GPIO_PAD_DAC1_PDAC1_HOLD = 0x20000000 + // Position of PDAC1_DRV field. + RTC_GPIO_PAD_DAC1_PDAC1_DRV_Pos = 0x1e + // Bit mask of PDAC1_DRV field. + RTC_GPIO_PAD_DAC1_PDAC1_DRV_Msk = 0xc0000000 + + // PAD_DAC2 + // Position of PDAC2_DAC_XPD_FORCE field. + RTC_GPIO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Pos = 0xa + // Bit mask of PDAC2_DAC_XPD_FORCE field. + RTC_GPIO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Msk = 0x400 + // Bit PDAC2_DAC_XPD_FORCE. + RTC_GPIO_PAD_DAC2_PDAC2_DAC_XPD_FORCE = 0x400 + // Position of PDAC2_FUN_IE field. + RTC_GPIO_PAD_DAC2_PDAC2_FUN_IE_Pos = 0xb + // Bit mask of PDAC2_FUN_IE field. + RTC_GPIO_PAD_DAC2_PDAC2_FUN_IE_Msk = 0x800 + // Bit PDAC2_FUN_IE. + RTC_GPIO_PAD_DAC2_PDAC2_FUN_IE = 0x800 + // Position of PDAC2_SLP_OE field. + RTC_GPIO_PAD_DAC2_PDAC2_SLP_OE_Pos = 0xc + // Bit mask of PDAC2_SLP_OE field. + RTC_GPIO_PAD_DAC2_PDAC2_SLP_OE_Msk = 0x1000 + // Bit PDAC2_SLP_OE. + RTC_GPIO_PAD_DAC2_PDAC2_SLP_OE = 0x1000 + // Position of PDAC2_SLP_IE field. + RTC_GPIO_PAD_DAC2_PDAC2_SLP_IE_Pos = 0xd + // Bit mask of PDAC2_SLP_IE field. + RTC_GPIO_PAD_DAC2_PDAC2_SLP_IE_Msk = 0x2000 + // Bit PDAC2_SLP_IE. + RTC_GPIO_PAD_DAC2_PDAC2_SLP_IE = 0x2000 + // Position of PDAC2_SLP_SEL field. + RTC_GPIO_PAD_DAC2_PDAC2_SLP_SEL_Pos = 0xe + // Bit mask of PDAC2_SLP_SEL field. + RTC_GPIO_PAD_DAC2_PDAC2_SLP_SEL_Msk = 0x4000 + // Bit PDAC2_SLP_SEL. + RTC_GPIO_PAD_DAC2_PDAC2_SLP_SEL = 0x4000 + // Position of PDAC2_FUN_SEL field. + RTC_GPIO_PAD_DAC2_PDAC2_FUN_SEL_Pos = 0xf + // Bit mask of PDAC2_FUN_SEL field. + RTC_GPIO_PAD_DAC2_PDAC2_FUN_SEL_Msk = 0x18000 + // Position of PDAC2_MUX_SEL field. + RTC_GPIO_PAD_DAC2_PDAC2_MUX_SEL_Pos = 0x11 + // Bit mask of PDAC2_MUX_SEL field. + RTC_GPIO_PAD_DAC2_PDAC2_MUX_SEL_Msk = 0x20000 + // Bit PDAC2_MUX_SEL. + RTC_GPIO_PAD_DAC2_PDAC2_MUX_SEL = 0x20000 + // Position of PDAC2_XPD_DAC field. + RTC_GPIO_PAD_DAC2_PDAC2_XPD_DAC_Pos = 0x12 + // Bit mask of PDAC2_XPD_DAC field. + RTC_GPIO_PAD_DAC2_PDAC2_XPD_DAC_Msk = 0x40000 + // Bit PDAC2_XPD_DAC. + RTC_GPIO_PAD_DAC2_PDAC2_XPD_DAC = 0x40000 + // Position of PDAC2_DAC field. + RTC_GPIO_PAD_DAC2_PDAC2_DAC_Pos = 0x13 + // Bit mask of PDAC2_DAC field. + RTC_GPIO_PAD_DAC2_PDAC2_DAC_Msk = 0x7f80000 + // Position of PDAC2_RUE field. + RTC_GPIO_PAD_DAC2_PDAC2_RUE_Pos = 0x1b + // Bit mask of PDAC2_RUE field. + RTC_GPIO_PAD_DAC2_PDAC2_RUE_Msk = 0x8000000 + // Bit PDAC2_RUE. + RTC_GPIO_PAD_DAC2_PDAC2_RUE = 0x8000000 + // Position of PDAC2_RDE field. + RTC_GPIO_PAD_DAC2_PDAC2_RDE_Pos = 0x1c + // Bit mask of PDAC2_RDE field. + RTC_GPIO_PAD_DAC2_PDAC2_RDE_Msk = 0x10000000 + // Bit PDAC2_RDE. + RTC_GPIO_PAD_DAC2_PDAC2_RDE = 0x10000000 + // Position of PDAC2_HOLD field. + RTC_GPIO_PAD_DAC2_PDAC2_HOLD_Pos = 0x1d + // Bit mask of PDAC2_HOLD field. + RTC_GPIO_PAD_DAC2_PDAC2_HOLD_Msk = 0x20000000 + // Bit PDAC2_HOLD. + RTC_GPIO_PAD_DAC2_PDAC2_HOLD = 0x20000000 + // Position of PDAC2_DRV field. + RTC_GPIO_PAD_DAC2_PDAC2_DRV_Pos = 0x1e + // Bit mask of PDAC2_DRV field. + RTC_GPIO_PAD_DAC2_PDAC2_DRV_Msk = 0xc0000000 + + // XTAL_32K_PAD + // Position of DBIAS_XTAL_32K field. + RTC_GPIO_XTAL_32K_PAD_DBIAS_XTAL_32K_Pos = 0x1 + // Bit mask of DBIAS_XTAL_32K field. + RTC_GPIO_XTAL_32K_PAD_DBIAS_XTAL_32K_Msk = 0x6 + // Position of DRES_XTAL_32K field. + RTC_GPIO_XTAL_32K_PAD_DRES_XTAL_32K_Pos = 0x3 + // Bit mask of DRES_XTAL_32K field. + RTC_GPIO_XTAL_32K_PAD_DRES_XTAL_32K_Msk = 0x18 + // Position of X32P_FUN_IE field. + RTC_GPIO_XTAL_32K_PAD_X32P_FUN_IE_Pos = 0x5 + // Bit mask of X32P_FUN_IE field. + RTC_GPIO_XTAL_32K_PAD_X32P_FUN_IE_Msk = 0x20 + // Bit X32P_FUN_IE. + RTC_GPIO_XTAL_32K_PAD_X32P_FUN_IE = 0x20 + // Position of X32P_SLP_OE field. + RTC_GPIO_XTAL_32K_PAD_X32P_SLP_OE_Pos = 0x6 + // Bit mask of X32P_SLP_OE field. + RTC_GPIO_XTAL_32K_PAD_X32P_SLP_OE_Msk = 0x40 + // Bit X32P_SLP_OE. + RTC_GPIO_XTAL_32K_PAD_X32P_SLP_OE = 0x40 + // Position of X32P_SLP_IE field. + RTC_GPIO_XTAL_32K_PAD_X32P_SLP_IE_Pos = 0x7 + // Bit mask of X32P_SLP_IE field. + RTC_GPIO_XTAL_32K_PAD_X32P_SLP_IE_Msk = 0x80 + // Bit X32P_SLP_IE. + RTC_GPIO_XTAL_32K_PAD_X32P_SLP_IE = 0x80 + // Position of X32P_SLP_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32P_SLP_SEL_Pos = 0x8 + // Bit mask of X32P_SLP_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32P_SLP_SEL_Msk = 0x100 + // Bit X32P_SLP_SEL. + RTC_GPIO_XTAL_32K_PAD_X32P_SLP_SEL = 0x100 + // Position of X32P_FUN_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32P_FUN_SEL_Pos = 0x9 + // Bit mask of X32P_FUN_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32P_FUN_SEL_Msk = 0x600 + // Position of X32N_FUN_IE field. + RTC_GPIO_XTAL_32K_PAD_X32N_FUN_IE_Pos = 0xb + // Bit mask of X32N_FUN_IE field. + RTC_GPIO_XTAL_32K_PAD_X32N_FUN_IE_Msk = 0x800 + // Bit X32N_FUN_IE. + RTC_GPIO_XTAL_32K_PAD_X32N_FUN_IE = 0x800 + // Position of X32N_SLP_OE field. + RTC_GPIO_XTAL_32K_PAD_X32N_SLP_OE_Pos = 0xc + // Bit mask of X32N_SLP_OE field. + RTC_GPIO_XTAL_32K_PAD_X32N_SLP_OE_Msk = 0x1000 + // Bit X32N_SLP_OE. + RTC_GPIO_XTAL_32K_PAD_X32N_SLP_OE = 0x1000 + // Position of X32N_SLP_IE field. + RTC_GPIO_XTAL_32K_PAD_X32N_SLP_IE_Pos = 0xd + // Bit mask of X32N_SLP_IE field. + RTC_GPIO_XTAL_32K_PAD_X32N_SLP_IE_Msk = 0x2000 + // Bit X32N_SLP_IE. + RTC_GPIO_XTAL_32K_PAD_X32N_SLP_IE = 0x2000 + // Position of X32N_SLP_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32N_SLP_SEL_Pos = 0xe + // Bit mask of X32N_SLP_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32N_SLP_SEL_Msk = 0x4000 + // Bit X32N_SLP_SEL. + RTC_GPIO_XTAL_32K_PAD_X32N_SLP_SEL = 0x4000 + // Position of X32N_FUN_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32N_FUN_SEL_Pos = 0xf + // Bit mask of X32N_FUN_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32N_FUN_SEL_Msk = 0x18000 + // Position of X32P_MUX_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32P_MUX_SEL_Pos = 0x11 + // Bit mask of X32P_MUX_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32P_MUX_SEL_Msk = 0x20000 + // Bit X32P_MUX_SEL. + RTC_GPIO_XTAL_32K_PAD_X32P_MUX_SEL = 0x20000 + // Position of X32N_MUX_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32N_MUX_SEL_Pos = 0x12 + // Bit mask of X32N_MUX_SEL field. + RTC_GPIO_XTAL_32K_PAD_X32N_MUX_SEL_Msk = 0x40000 + // Bit X32N_MUX_SEL. + RTC_GPIO_XTAL_32K_PAD_X32N_MUX_SEL = 0x40000 + // Position of XPD_XTAL_32K field. + RTC_GPIO_XTAL_32K_PAD_XPD_XTAL_32K_Pos = 0x13 + // Bit mask of XPD_XTAL_32K field. + RTC_GPIO_XTAL_32K_PAD_XPD_XTAL_32K_Msk = 0x80000 + // Bit XPD_XTAL_32K. + RTC_GPIO_XTAL_32K_PAD_XPD_XTAL_32K = 0x80000 + // Position of DAC_XTAL_32K field. + RTC_GPIO_XTAL_32K_PAD_DAC_XTAL_32K_Pos = 0x14 + // Bit mask of DAC_XTAL_32K field. + RTC_GPIO_XTAL_32K_PAD_DAC_XTAL_32K_Msk = 0x300000 + // Position of X32P_RUE field. + RTC_GPIO_XTAL_32K_PAD_X32P_RUE_Pos = 0x16 + // Bit mask of X32P_RUE field. + RTC_GPIO_XTAL_32K_PAD_X32P_RUE_Msk = 0x400000 + // Bit X32P_RUE. + RTC_GPIO_XTAL_32K_PAD_X32P_RUE = 0x400000 + // Position of X32P_RDE field. + RTC_GPIO_XTAL_32K_PAD_X32P_RDE_Pos = 0x17 + // Bit mask of X32P_RDE field. + RTC_GPIO_XTAL_32K_PAD_X32P_RDE_Msk = 0x800000 + // Bit X32P_RDE. + RTC_GPIO_XTAL_32K_PAD_X32P_RDE = 0x800000 + // Position of X32P_HOLD field. + RTC_GPIO_XTAL_32K_PAD_X32P_HOLD_Pos = 0x18 + // Bit mask of X32P_HOLD field. + RTC_GPIO_XTAL_32K_PAD_X32P_HOLD_Msk = 0x1000000 + // Bit X32P_HOLD. + RTC_GPIO_XTAL_32K_PAD_X32P_HOLD = 0x1000000 + // Position of X32P_DRV field. + RTC_GPIO_XTAL_32K_PAD_X32P_DRV_Pos = 0x19 + // Bit mask of X32P_DRV field. + RTC_GPIO_XTAL_32K_PAD_X32P_DRV_Msk = 0x6000000 + // Position of X32N_RUE field. + RTC_GPIO_XTAL_32K_PAD_X32N_RUE_Pos = 0x1b + // Bit mask of X32N_RUE field. + RTC_GPIO_XTAL_32K_PAD_X32N_RUE_Msk = 0x8000000 + // Bit X32N_RUE. + RTC_GPIO_XTAL_32K_PAD_X32N_RUE = 0x8000000 + // Position of X32N_RDE field. + RTC_GPIO_XTAL_32K_PAD_X32N_RDE_Pos = 0x1c + // Bit mask of X32N_RDE field. + RTC_GPIO_XTAL_32K_PAD_X32N_RDE_Msk = 0x10000000 + // Bit X32N_RDE. + RTC_GPIO_XTAL_32K_PAD_X32N_RDE = 0x10000000 + // Position of X32N_HOLD field. + RTC_GPIO_XTAL_32K_PAD_X32N_HOLD_Pos = 0x1d + // Bit mask of X32N_HOLD field. + RTC_GPIO_XTAL_32K_PAD_X32N_HOLD_Msk = 0x20000000 + // Bit X32N_HOLD. + RTC_GPIO_XTAL_32K_PAD_X32N_HOLD = 0x20000000 + // Position of X32N_DRV field. + RTC_GPIO_XTAL_32K_PAD_X32N_DRV_Pos = 0x1e + // Bit mask of X32N_DRV field. + RTC_GPIO_XTAL_32K_PAD_X32N_DRV_Msk = 0xc0000000 + + // TOUCH_CFG + // Position of TOUCH_DCUR field. + RTC_GPIO_TOUCH_CFG_TOUCH_DCUR_Pos = 0x17 + // Bit mask of TOUCH_DCUR field. + RTC_GPIO_TOUCH_CFG_TOUCH_DCUR_Msk = 0x1800000 + // Position of TOUCH_DRANGE field. + RTC_GPIO_TOUCH_CFG_TOUCH_DRANGE_Pos = 0x19 + // Bit mask of TOUCH_DRANGE field. + RTC_GPIO_TOUCH_CFG_TOUCH_DRANGE_Msk = 0x6000000 + // Position of TOUCH_DREFL field. + RTC_GPIO_TOUCH_CFG_TOUCH_DREFL_Pos = 0x1b + // Bit mask of TOUCH_DREFL field. + RTC_GPIO_TOUCH_CFG_TOUCH_DREFL_Msk = 0x18000000 + // Position of TOUCH_DREFH field. + RTC_GPIO_TOUCH_CFG_TOUCH_DREFH_Pos = 0x1d + // Bit mask of TOUCH_DREFH field. + RTC_GPIO_TOUCH_CFG_TOUCH_DREFH_Msk = 0x60000000 + // Position of TOUCH_XPD_BIAS field. + RTC_GPIO_TOUCH_CFG_TOUCH_XPD_BIAS_Pos = 0x1f + // Bit mask of TOUCH_XPD_BIAS field. + RTC_GPIO_TOUCH_CFG_TOUCH_XPD_BIAS_Msk = 0x80000000 + // Bit TOUCH_XPD_BIAS. + RTC_GPIO_TOUCH_CFG_TOUCH_XPD_BIAS = 0x80000000 + + // TOUCH_PAD0 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD0_TO_GPIO_Pos = 0xc + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD0_TO_GPIO_Msk = 0x1000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD0_TO_GPIO = 0x1000 + // Position of FUN_IE field. + RTC_GPIO_TOUCH_PAD0_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_GPIO_TOUCH_PAD0_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_GPIO_TOUCH_PAD0_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_GPIO_TOUCH_PAD0_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_GPIO_TOUCH_PAD0_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_GPIO_TOUCH_PAD0_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_GPIO_TOUCH_PAD0_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_GPIO_TOUCH_PAD0_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_GPIO_TOUCH_PAD0_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_GPIO_TOUCH_PAD0_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_GPIO_TOUCH_PAD0_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_GPIO_TOUCH_PAD0_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_GPIO_TOUCH_PAD0_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_GPIO_TOUCH_PAD0_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_GPIO_TOUCH_PAD0_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_GPIO_TOUCH_PAD0_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_GPIO_TOUCH_PAD0_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD0_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD0_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD0_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD0_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD0_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD0_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD0_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD0_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD0_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD0_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD0_DAC_Msk = 0x3800000 + // Position of RUE field. + RTC_GPIO_TOUCH_PAD0_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_GPIO_TOUCH_PAD0_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_GPIO_TOUCH_PAD0_RUE = 0x8000000 + // Position of RDE field. + RTC_GPIO_TOUCH_PAD0_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_GPIO_TOUCH_PAD0_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_GPIO_TOUCH_PAD0_RDE = 0x10000000 + // Position of DRV field. + RTC_GPIO_TOUCH_PAD0_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_GPIO_TOUCH_PAD0_DRV_Msk = 0x60000000 + // Position of HOLD field. + RTC_GPIO_TOUCH_PAD0_HOLD_Pos = 0x1f + // Bit mask of HOLD field. + RTC_GPIO_TOUCH_PAD0_HOLD_Msk = 0x80000000 + // Bit HOLD. + RTC_GPIO_TOUCH_PAD0_HOLD = 0x80000000 + + // TOUCH_PAD1 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD1_TO_GPIO_Pos = 0xc + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD1_TO_GPIO_Msk = 0x1000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD1_TO_GPIO = 0x1000 + // Position of FUN_IE field. + RTC_GPIO_TOUCH_PAD1_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_GPIO_TOUCH_PAD1_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_GPIO_TOUCH_PAD1_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_GPIO_TOUCH_PAD1_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_GPIO_TOUCH_PAD1_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_GPIO_TOUCH_PAD1_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_GPIO_TOUCH_PAD1_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_GPIO_TOUCH_PAD1_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_GPIO_TOUCH_PAD1_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_GPIO_TOUCH_PAD1_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_GPIO_TOUCH_PAD1_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_GPIO_TOUCH_PAD1_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_GPIO_TOUCH_PAD1_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_GPIO_TOUCH_PAD1_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_GPIO_TOUCH_PAD1_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_GPIO_TOUCH_PAD1_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_GPIO_TOUCH_PAD1_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD1_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD1_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD1_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD1_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD1_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD1_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD1_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD1_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD1_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD1_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD1_DAC_Msk = 0x3800000 + // Position of RUE field. + RTC_GPIO_TOUCH_PAD1_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_GPIO_TOUCH_PAD1_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_GPIO_TOUCH_PAD1_RUE = 0x8000000 + // Position of RDE field. + RTC_GPIO_TOUCH_PAD1_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_GPIO_TOUCH_PAD1_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_GPIO_TOUCH_PAD1_RDE = 0x10000000 + // Position of DRV field. + RTC_GPIO_TOUCH_PAD1_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_GPIO_TOUCH_PAD1_DRV_Msk = 0x60000000 + // Position of HOLD field. + RTC_GPIO_TOUCH_PAD1_HOLD_Pos = 0x1f + // Bit mask of HOLD field. + RTC_GPIO_TOUCH_PAD1_HOLD_Msk = 0x80000000 + // Bit HOLD. + RTC_GPIO_TOUCH_PAD1_HOLD = 0x80000000 + + // TOUCH_PAD2 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD2_TO_GPIO_Pos = 0xc + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD2_TO_GPIO_Msk = 0x1000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD2_TO_GPIO = 0x1000 + // Position of FUN_IE field. + RTC_GPIO_TOUCH_PAD2_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_GPIO_TOUCH_PAD2_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_GPIO_TOUCH_PAD2_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_GPIO_TOUCH_PAD2_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_GPIO_TOUCH_PAD2_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_GPIO_TOUCH_PAD2_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_GPIO_TOUCH_PAD2_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_GPIO_TOUCH_PAD2_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_GPIO_TOUCH_PAD2_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_GPIO_TOUCH_PAD2_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_GPIO_TOUCH_PAD2_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_GPIO_TOUCH_PAD2_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_GPIO_TOUCH_PAD2_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_GPIO_TOUCH_PAD2_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_GPIO_TOUCH_PAD2_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_GPIO_TOUCH_PAD2_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_GPIO_TOUCH_PAD2_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD2_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD2_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD2_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD2_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD2_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD2_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD2_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD2_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD2_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD2_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD2_DAC_Msk = 0x3800000 + // Position of RUE field. + RTC_GPIO_TOUCH_PAD2_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_GPIO_TOUCH_PAD2_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_GPIO_TOUCH_PAD2_RUE = 0x8000000 + // Position of RDE field. + RTC_GPIO_TOUCH_PAD2_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_GPIO_TOUCH_PAD2_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_GPIO_TOUCH_PAD2_RDE = 0x10000000 + // Position of DRV field. + RTC_GPIO_TOUCH_PAD2_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_GPIO_TOUCH_PAD2_DRV_Msk = 0x60000000 + // Position of HOLD field. + RTC_GPIO_TOUCH_PAD2_HOLD_Pos = 0x1f + // Bit mask of HOLD field. + RTC_GPIO_TOUCH_PAD2_HOLD_Msk = 0x80000000 + // Bit HOLD. + RTC_GPIO_TOUCH_PAD2_HOLD = 0x80000000 + + // TOUCH_PAD3 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD3_TO_GPIO_Pos = 0xc + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD3_TO_GPIO_Msk = 0x1000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD3_TO_GPIO = 0x1000 + // Position of FUN_IE field. + RTC_GPIO_TOUCH_PAD3_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_GPIO_TOUCH_PAD3_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_GPIO_TOUCH_PAD3_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_GPIO_TOUCH_PAD3_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_GPIO_TOUCH_PAD3_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_GPIO_TOUCH_PAD3_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_GPIO_TOUCH_PAD3_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_GPIO_TOUCH_PAD3_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_GPIO_TOUCH_PAD3_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_GPIO_TOUCH_PAD3_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_GPIO_TOUCH_PAD3_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_GPIO_TOUCH_PAD3_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_GPIO_TOUCH_PAD3_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_GPIO_TOUCH_PAD3_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_GPIO_TOUCH_PAD3_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_GPIO_TOUCH_PAD3_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_GPIO_TOUCH_PAD3_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD3_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD3_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD3_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD3_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD3_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD3_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD3_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD3_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD3_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD3_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD3_DAC_Msk = 0x3800000 + // Position of RUE field. + RTC_GPIO_TOUCH_PAD3_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_GPIO_TOUCH_PAD3_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_GPIO_TOUCH_PAD3_RUE = 0x8000000 + // Position of RDE field. + RTC_GPIO_TOUCH_PAD3_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_GPIO_TOUCH_PAD3_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_GPIO_TOUCH_PAD3_RDE = 0x10000000 + // Position of DRV field. + RTC_GPIO_TOUCH_PAD3_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_GPIO_TOUCH_PAD3_DRV_Msk = 0x60000000 + // Position of HOLD field. + RTC_GPIO_TOUCH_PAD3_HOLD_Pos = 0x1f + // Bit mask of HOLD field. + RTC_GPIO_TOUCH_PAD3_HOLD_Msk = 0x80000000 + // Bit HOLD. + RTC_GPIO_TOUCH_PAD3_HOLD = 0x80000000 + + // TOUCH_PAD4 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD4_TO_GPIO_Pos = 0xc + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD4_TO_GPIO_Msk = 0x1000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD4_TO_GPIO = 0x1000 + // Position of FUN_IE field. + RTC_GPIO_TOUCH_PAD4_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_GPIO_TOUCH_PAD4_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_GPIO_TOUCH_PAD4_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_GPIO_TOUCH_PAD4_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_GPIO_TOUCH_PAD4_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_GPIO_TOUCH_PAD4_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_GPIO_TOUCH_PAD4_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_GPIO_TOUCH_PAD4_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_GPIO_TOUCH_PAD4_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_GPIO_TOUCH_PAD4_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_GPIO_TOUCH_PAD4_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_GPIO_TOUCH_PAD4_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_GPIO_TOUCH_PAD4_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_GPIO_TOUCH_PAD4_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_GPIO_TOUCH_PAD4_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_GPIO_TOUCH_PAD4_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_GPIO_TOUCH_PAD4_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD4_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD4_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD4_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD4_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD4_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD4_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD4_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD4_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD4_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD4_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD4_DAC_Msk = 0x3800000 + // Position of RUE field. + RTC_GPIO_TOUCH_PAD4_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_GPIO_TOUCH_PAD4_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_GPIO_TOUCH_PAD4_RUE = 0x8000000 + // Position of RDE field. + RTC_GPIO_TOUCH_PAD4_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_GPIO_TOUCH_PAD4_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_GPIO_TOUCH_PAD4_RDE = 0x10000000 + // Position of DRV field. + RTC_GPIO_TOUCH_PAD4_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_GPIO_TOUCH_PAD4_DRV_Msk = 0x60000000 + // Position of HOLD field. + RTC_GPIO_TOUCH_PAD4_HOLD_Pos = 0x1f + // Bit mask of HOLD field. + RTC_GPIO_TOUCH_PAD4_HOLD_Msk = 0x80000000 + // Bit HOLD. + RTC_GPIO_TOUCH_PAD4_HOLD = 0x80000000 + + // TOUCH_PAD5 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD5_TO_GPIO_Pos = 0xc + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD5_TO_GPIO_Msk = 0x1000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD5_TO_GPIO = 0x1000 + // Position of FUN_IE field. + RTC_GPIO_TOUCH_PAD5_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_GPIO_TOUCH_PAD5_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_GPIO_TOUCH_PAD5_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_GPIO_TOUCH_PAD5_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_GPIO_TOUCH_PAD5_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_GPIO_TOUCH_PAD5_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_GPIO_TOUCH_PAD5_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_GPIO_TOUCH_PAD5_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_GPIO_TOUCH_PAD5_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_GPIO_TOUCH_PAD5_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_GPIO_TOUCH_PAD5_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_GPIO_TOUCH_PAD5_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_GPIO_TOUCH_PAD5_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_GPIO_TOUCH_PAD5_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_GPIO_TOUCH_PAD5_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_GPIO_TOUCH_PAD5_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_GPIO_TOUCH_PAD5_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD5_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD5_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD5_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD5_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD5_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD5_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD5_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD5_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD5_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD5_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD5_DAC_Msk = 0x3800000 + // Position of RUE field. + RTC_GPIO_TOUCH_PAD5_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_GPIO_TOUCH_PAD5_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_GPIO_TOUCH_PAD5_RUE = 0x8000000 + // Position of RDE field. + RTC_GPIO_TOUCH_PAD5_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_GPIO_TOUCH_PAD5_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_GPIO_TOUCH_PAD5_RDE = 0x10000000 + // Position of DRV field. + RTC_GPIO_TOUCH_PAD5_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_GPIO_TOUCH_PAD5_DRV_Msk = 0x60000000 + // Position of HOLD field. + RTC_GPIO_TOUCH_PAD5_HOLD_Pos = 0x1f + // Bit mask of HOLD field. + RTC_GPIO_TOUCH_PAD5_HOLD_Msk = 0x80000000 + // Bit HOLD. + RTC_GPIO_TOUCH_PAD5_HOLD = 0x80000000 + + // TOUCH_PAD6 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD6_TO_GPIO_Pos = 0xc + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD6_TO_GPIO_Msk = 0x1000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD6_TO_GPIO = 0x1000 + // Position of FUN_IE field. + RTC_GPIO_TOUCH_PAD6_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_GPIO_TOUCH_PAD6_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_GPIO_TOUCH_PAD6_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_GPIO_TOUCH_PAD6_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_GPIO_TOUCH_PAD6_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_GPIO_TOUCH_PAD6_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_GPIO_TOUCH_PAD6_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_GPIO_TOUCH_PAD6_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_GPIO_TOUCH_PAD6_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_GPIO_TOUCH_PAD6_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_GPIO_TOUCH_PAD6_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_GPIO_TOUCH_PAD6_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_GPIO_TOUCH_PAD6_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_GPIO_TOUCH_PAD6_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_GPIO_TOUCH_PAD6_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_GPIO_TOUCH_PAD6_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_GPIO_TOUCH_PAD6_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD6_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD6_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD6_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD6_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD6_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD6_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD6_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD6_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD6_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD6_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD6_DAC_Msk = 0x3800000 + // Position of RUE field. + RTC_GPIO_TOUCH_PAD6_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_GPIO_TOUCH_PAD6_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_GPIO_TOUCH_PAD6_RUE = 0x8000000 + // Position of RDE field. + RTC_GPIO_TOUCH_PAD6_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_GPIO_TOUCH_PAD6_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_GPIO_TOUCH_PAD6_RDE = 0x10000000 + // Position of DRV field. + RTC_GPIO_TOUCH_PAD6_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_GPIO_TOUCH_PAD6_DRV_Msk = 0x60000000 + // Position of HOLD field. + RTC_GPIO_TOUCH_PAD6_HOLD_Pos = 0x1f + // Bit mask of HOLD field. + RTC_GPIO_TOUCH_PAD6_HOLD_Msk = 0x80000000 + // Bit HOLD. + RTC_GPIO_TOUCH_PAD6_HOLD = 0x80000000 + + // TOUCH_PAD7 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD7_TO_GPIO_Pos = 0xc + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD7_TO_GPIO_Msk = 0x1000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD7_TO_GPIO = 0x1000 + // Position of FUN_IE field. + RTC_GPIO_TOUCH_PAD7_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_GPIO_TOUCH_PAD7_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_GPIO_TOUCH_PAD7_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_GPIO_TOUCH_PAD7_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_GPIO_TOUCH_PAD7_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_GPIO_TOUCH_PAD7_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_GPIO_TOUCH_PAD7_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_GPIO_TOUCH_PAD7_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_GPIO_TOUCH_PAD7_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_GPIO_TOUCH_PAD7_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_GPIO_TOUCH_PAD7_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_GPIO_TOUCH_PAD7_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_GPIO_TOUCH_PAD7_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_GPIO_TOUCH_PAD7_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_GPIO_TOUCH_PAD7_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_GPIO_TOUCH_PAD7_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_GPIO_TOUCH_PAD7_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD7_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD7_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD7_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD7_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD7_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD7_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD7_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD7_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD7_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD7_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD7_DAC_Msk = 0x3800000 + // Position of RUE field. + RTC_GPIO_TOUCH_PAD7_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_GPIO_TOUCH_PAD7_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_GPIO_TOUCH_PAD7_RUE = 0x8000000 + // Position of RDE field. + RTC_GPIO_TOUCH_PAD7_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_GPIO_TOUCH_PAD7_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_GPIO_TOUCH_PAD7_RDE = 0x10000000 + // Position of DRV field. + RTC_GPIO_TOUCH_PAD7_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_GPIO_TOUCH_PAD7_DRV_Msk = 0x60000000 + // Position of HOLD field. + RTC_GPIO_TOUCH_PAD7_HOLD_Pos = 0x1f + // Bit mask of HOLD field. + RTC_GPIO_TOUCH_PAD7_HOLD_Msk = 0x80000000 + // Bit HOLD. + RTC_GPIO_TOUCH_PAD7_HOLD = 0x80000000 + + // TOUCH_PAD8 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD8_TO_GPIO_Pos = 0x13 + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD8_TO_GPIO_Msk = 0x80000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD8_TO_GPIO = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD8_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD8_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD8_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD8_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD8_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD8_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD8_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD8_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD8_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD8_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD8_DAC_Msk = 0x3800000 + + // TOUCH_PAD9 + // Position of TO_GPIO field. + RTC_GPIO_TOUCH_PAD9_TO_GPIO_Pos = 0x13 + // Bit mask of TO_GPIO field. + RTC_GPIO_TOUCH_PAD9_TO_GPIO_Msk = 0x80000 + // Bit TO_GPIO. + RTC_GPIO_TOUCH_PAD9_TO_GPIO = 0x80000 + // Position of XPD field. + RTC_GPIO_TOUCH_PAD9_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_GPIO_TOUCH_PAD9_XPD_Msk = 0x100000 + // Bit XPD. + RTC_GPIO_TOUCH_PAD9_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_GPIO_TOUCH_PAD9_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_GPIO_TOUCH_PAD9_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_GPIO_TOUCH_PAD9_TIE_OPT = 0x200000 + // Position of START field. + RTC_GPIO_TOUCH_PAD9_START_Pos = 0x16 + // Bit mask of START field. + RTC_GPIO_TOUCH_PAD9_START_Msk = 0x400000 + // Bit START. + RTC_GPIO_TOUCH_PAD9_START = 0x400000 + // Position of DAC field. + RTC_GPIO_TOUCH_PAD9_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTC_GPIO_TOUCH_PAD9_DAC_Msk = 0x3800000 + + // EXT_WAKEUP0 + // Position of SEL field. + RTC_GPIO_EXT_WAKEUP0_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTC_GPIO_EXT_WAKEUP0_SEL_Msk = 0xf8000000 + + // XTL_EXT_CTR + // Position of SEL field. + RTC_GPIO_XTL_EXT_CTR_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTC_GPIO_XTL_EXT_CTR_SEL_Msk = 0xf8000000 + + // SAR_I2C_IO + // Position of SAR_DEBUG_BIT_SEL field. + RTC_GPIO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Pos = 0x17 + // Bit mask of SAR_DEBUG_BIT_SEL field. + RTC_GPIO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Msk = 0xf800000 + // Position of SAR_I2C_SCL_SEL field. + RTC_GPIO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Pos = 0x1c + // Bit mask of SAR_I2C_SCL_SEL field. + RTC_GPIO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Msk = 0x30000000 + // Position of SAR_I2C_SDA_SEL field. + RTC_GPIO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Pos = 0x1e + // Bit mask of SAR_I2C_SDA_SEL field. + RTC_GPIO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Msk = 0xc0000000 + + // DATE + // Position of IO_DATE field. + RTC_GPIO_DATE_IO_DATE_Pos = 0x0 + // Bit mask of IO_DATE field. + RTC_GPIO_DATE_IO_DATE_Msk = 0xfffffff +) + +// Constants for RTC_I2C: Low-power I2C (Inter-Integrated Circuit) Controller +const ( + // SCL_LOW_PERIOD + // Position of SCL_LOW_PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of SCL_LOW_PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x1ffffff + + // CTRL + // Position of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + RTC_I2C_CTRL_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + RTC_I2C_CTRL_SCL_FORCE_OUT = 0x2 + // Position of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Pos = 0x4 + // Bit mask of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Msk = 0x10 + // Bit MS_MODE. + RTC_I2C_CTRL_MS_MODE = 0x10 + // Position of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Pos = 0x5 + // Bit mask of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Msk = 0x20 + // Bit TRANS_START. + RTC_I2C_CTRL_TRANS_START = 0x20 + // Position of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Msk = 0x40 + // Bit TX_LSB_FIRST. + RTC_I2C_CTRL_TX_LSB_FIRST = 0x40 + // Position of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Msk = 0x80 + // Bit RX_LSB_FIRST. + RTC_I2C_CTRL_RX_LSB_FIRST = 0x80 + + // DEBUG_STATUS + // Position of ACK_VAL field. + RTC_I2C_DEBUG_STATUS_ACK_VAL_Pos = 0x0 + // Bit mask of ACK_VAL field. + RTC_I2C_DEBUG_STATUS_ACK_VAL_Msk = 0x1 + // Bit ACK_VAL. + RTC_I2C_DEBUG_STATUS_ACK_VAL = 0x1 + // Position of SLAVE_RW field. + RTC_I2C_DEBUG_STATUS_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + RTC_I2C_DEBUG_STATUS_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + RTC_I2C_DEBUG_STATUS_SLAVE_RW = 0x2 + // Position of TIMED_OUT field. + RTC_I2C_DEBUG_STATUS_TIMED_OUT_Pos = 0x2 + // Bit mask of TIMED_OUT field. + RTC_I2C_DEBUG_STATUS_TIMED_OUT_Msk = 0x4 + // Bit TIMED_OUT. + RTC_I2C_DEBUG_STATUS_TIMED_OUT = 0x4 + // Position of ARB_LOST field. + RTC_I2C_DEBUG_STATUS_ARB_LOST_Pos = 0x3 + // Bit mask of ARB_LOST field. + RTC_I2C_DEBUG_STATUS_ARB_LOST_Msk = 0x8 + // Bit ARB_LOST. + RTC_I2C_DEBUG_STATUS_ARB_LOST = 0x8 + // Position of BUS_BUSY field. + RTC_I2C_DEBUG_STATUS_BUS_BUSY_Pos = 0x4 + // Bit mask of BUS_BUSY field. + RTC_I2C_DEBUG_STATUS_BUS_BUSY_Msk = 0x10 + // Bit BUS_BUSY. + RTC_I2C_DEBUG_STATUS_BUS_BUSY = 0x10 + // Position of SLAVE_ADDR_MATCH field. + RTC_I2C_DEBUG_STATUS_SLAVE_ADDR_MATCH_Pos = 0x5 + // Bit mask of SLAVE_ADDR_MATCH field. + RTC_I2C_DEBUG_STATUS_SLAVE_ADDR_MATCH_Msk = 0x20 + // Bit SLAVE_ADDR_MATCH. + RTC_I2C_DEBUG_STATUS_SLAVE_ADDR_MATCH = 0x20 + // Position of BYTE_TRANS field. + RTC_I2C_DEBUG_STATUS_BYTE_TRANS_Pos = 0x6 + // Bit mask of BYTE_TRANS field. + RTC_I2C_DEBUG_STATUS_BYTE_TRANS_Msk = 0x40 + // Bit BYTE_TRANS. + RTC_I2C_DEBUG_STATUS_BYTE_TRANS = 0x40 + // Position of MAIN_STATE field. + RTC_I2C_DEBUG_STATUS_MAIN_STATE_Pos = 0x19 + // Bit mask of MAIN_STATE field. + RTC_I2C_DEBUG_STATUS_MAIN_STATE_Msk = 0xe000000 + // Position of SCL_STATE field. + RTC_I2C_DEBUG_STATUS_SCL_STATE_Pos = 0x1c + // Bit mask of SCL_STATE field. + RTC_I2C_DEBUG_STATUS_SCL_STATE_Msk = 0x70000000 + + // TIMEOUT + // Position of TIMEOUT field. + RTC_I2C_TIMEOUT_TIMEOUT_Pos = 0x0 + // Bit mask of TIMEOUT field. + RTC_I2C_TIMEOUT_TIMEOUT_Msk = 0xfffff + + // SLAVE_ADDR + // Position of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of _10BIT field. + RTC_I2C_SLAVE_ADDR__10BIT_Pos = 0x1f + // Bit mask of _10BIT field. + RTC_I2C_SLAVE_ADDR__10BIT_Msk = 0x80000000 + // Bit _10BIT. + RTC_I2C_SLAVE_ADDR__10BIT = 0x80000000 + + // INT_RAW + // Position of SLAVE_TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRANS_COMPLETE_INT_RAW_Pos = 0x3 + // Bit mask of SLAVE_TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRANS_COMPLETE_INT_RAW_Msk = 0x8 + // Bit SLAVE_TRANS_COMPLETE_INT_RAW. + RTC_I2C_INT_RAW_SLAVE_TRANS_COMPLETE_INT_RAW = 0x8 + // Position of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x4 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x10 + // Bit ARBITRATION_LOST_INT_RAW. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x10 + // Position of MASTER_TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRANS_COMPLETE_INT_RAW_Pos = 0x5 + // Bit mask of MASTER_TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRANS_COMPLETE_INT_RAW_Msk = 0x20 + // Bit MASTER_TRANS_COMPLETE_INT_RAW. + RTC_I2C_INT_RAW_MASTER_TRANS_COMPLETE_INT_RAW = 0x20 + // Position of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x6 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x40 + // Bit TRANS_COMPLETE_INT_RAW. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x40 + // Position of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x7 + // Bit mask of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x80 + // Bit TIME_OUT_INT_RAW. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW = 0x80 + + // INT_CLR + // Position of SLAVE_TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRANS_COMPLETE_INT_CLR_Pos = 0x4 + // Bit mask of SLAVE_TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRANS_COMPLETE_INT_CLR_Msk = 0x10 + // Bit SLAVE_TRANS_COMPLETE_INT_CLR. + RTC_I2C_INT_CLR_SLAVE_TRANS_COMPLETE_INT_CLR = 0x10 + // Position of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_CLR. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of MASTER_TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRANS_COMPLETE_INT_CLR_Pos = 0x6 + // Bit mask of MASTER_TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRANS_COMPLETE_INT_CLR_Msk = 0x40 + // Bit MASTER_TRANS_COMPLETE_INT_CLR. + RTC_I2C_INT_CLR_MASTER_TRANS_COMPLETE_INT_CLR = 0x40 + // Position of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_CLR. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit TIME_OUT_INT_CLR. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100 + + // SDA_DUTY + // Position of SDA_DUTY field. + RTC_I2C_SDA_DUTY_SDA_DUTY_Pos = 0x0 + // Bit mask of SDA_DUTY field. + RTC_I2C_SDA_DUTY_SDA_DUTY_Msk = 0xfffff + + // SCL_HIGH_PERIOD + // Position of SCL_HIGH_PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of SCL_HIGH_PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0xfffff + + // SCL_START_PERIOD + // Position of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Pos = 0x0 + // Bit mask of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Msk = 0xfffff + + // SCL_STOP_PERIOD + // Position of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Pos = 0x0 + // Bit mask of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Msk = 0xfffff + + // CMD + // Position of VAL field. + RTC_I2C_CMD_VAL_Pos = 0x0 + // Bit mask of VAL field. + RTC_I2C_CMD_VAL_Msk = 0x3fff + // Position of DONE field. + RTC_I2C_CMD_DONE_Pos = 0x1f + // Bit mask of DONE field. + RTC_I2C_CMD_DONE_Msk = 0x80000000 + // Bit DONE. + RTC_I2C_CMD_DONE = 0x80000000 +) + +// Constants for SDHOST: SD/MMC Host Controller +const ( + // CTRL: Control register + // Position of CONTROLLER_RESET field. + SDHOST_CTRL_CONTROLLER_RESET_Pos = 0x0 + // Bit mask of CONTROLLER_RESET field. + SDHOST_CTRL_CONTROLLER_RESET_Msk = 0x1 + // Bit CONTROLLER_RESET. + SDHOST_CTRL_CONTROLLER_RESET = 0x1 + // Position of FIFO_RESET field. + SDHOST_CTRL_FIFO_RESET_Pos = 0x1 + // Bit mask of FIFO_RESET field. + SDHOST_CTRL_FIFO_RESET_Msk = 0x2 + // Bit FIFO_RESET. + SDHOST_CTRL_FIFO_RESET = 0x2 + // Position of DMA_RESET field. + SDHOST_CTRL_DMA_RESET_Pos = 0x2 + // Bit mask of DMA_RESET field. + SDHOST_CTRL_DMA_RESET_Msk = 0x4 + // Bit DMA_RESET. + SDHOST_CTRL_DMA_RESET = 0x4 + // Position of INT_ENABLE field. + SDHOST_CTRL_INT_ENABLE_Pos = 0x4 + // Bit mask of INT_ENABLE field. + SDHOST_CTRL_INT_ENABLE_Msk = 0x10 + // Bit INT_ENABLE. + SDHOST_CTRL_INT_ENABLE = 0x10 + // Position of READ_WAIT field. + SDHOST_CTRL_READ_WAIT_Pos = 0x6 + // Bit mask of READ_WAIT field. + SDHOST_CTRL_READ_WAIT_Msk = 0x40 + // Bit READ_WAIT. + SDHOST_CTRL_READ_WAIT = 0x40 + // Position of SEND_IRQ_RESPONSE field. + SDHOST_CTRL_SEND_IRQ_RESPONSE_Pos = 0x7 + // Bit mask of SEND_IRQ_RESPONSE field. + SDHOST_CTRL_SEND_IRQ_RESPONSE_Msk = 0x80 + // Bit SEND_IRQ_RESPONSE. + SDHOST_CTRL_SEND_IRQ_RESPONSE = 0x80 + // Position of ABORT_READ_DATA field. + SDHOST_CTRL_ABORT_READ_DATA_Pos = 0x8 + // Bit mask of ABORT_READ_DATA field. + SDHOST_CTRL_ABORT_READ_DATA_Msk = 0x100 + // Bit ABORT_READ_DATA. + SDHOST_CTRL_ABORT_READ_DATA = 0x100 + // Position of SEND_CCSD field. + SDHOST_CTRL_SEND_CCSD_Pos = 0x9 + // Bit mask of SEND_CCSD field. + SDHOST_CTRL_SEND_CCSD_Msk = 0x200 + // Bit SEND_CCSD. + SDHOST_CTRL_SEND_CCSD = 0x200 + // Position of SEND_AUTO_STOP_CCSD field. + SDHOST_CTRL_SEND_AUTO_STOP_CCSD_Pos = 0xa + // Bit mask of SEND_AUTO_STOP_CCSD field. + SDHOST_CTRL_SEND_AUTO_STOP_CCSD_Msk = 0x400 + // Bit SEND_AUTO_STOP_CCSD. + SDHOST_CTRL_SEND_AUTO_STOP_CCSD = 0x400 + // Position of CEATA_DEVICE_INTERRUPT_STATUS field. + SDHOST_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos = 0xb + // Bit mask of CEATA_DEVICE_INTERRUPT_STATUS field. + SDHOST_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk = 0x800 + // Bit CEATA_DEVICE_INTERRUPT_STATUS. + SDHOST_CTRL_CEATA_DEVICE_INTERRUPT_STATUS = 0x800 + + // CLKDIV: Clock divider configuration register + // Position of CLK_DIVIDER0 field. + SDHOST_CLKDIV_CLK_DIVIDER0_Pos = 0x0 + // Bit mask of CLK_DIVIDER0 field. + SDHOST_CLKDIV_CLK_DIVIDER0_Msk = 0xff + // Position of CLK_DIVIDER1 field. + SDHOST_CLKDIV_CLK_DIVIDER1_Pos = 0x8 + // Bit mask of CLK_DIVIDER1 field. + SDHOST_CLKDIV_CLK_DIVIDER1_Msk = 0xff00 + // Position of CLK_DIVIDER2 field. + SDHOST_CLKDIV_CLK_DIVIDER2_Pos = 0x10 + // Bit mask of CLK_DIVIDER2 field. + SDHOST_CLKDIV_CLK_DIVIDER2_Msk = 0xff0000 + // Position of CLK_DIVIDER3 field. + SDHOST_CLKDIV_CLK_DIVIDER3_Pos = 0x18 + // Bit mask of CLK_DIVIDER3 field. + SDHOST_CLKDIV_CLK_DIVIDER3_Msk = 0xff000000 + + // CLKSRC: Clock source selection register + // Position of CLKSRC field. + SDHOST_CLKSRC_CLKSRC_Pos = 0x0 + // Bit mask of CLKSRC field. + SDHOST_CLKSRC_CLKSRC_Msk = 0xf + + // CLKENA: Clock enable register + // Position of CCLK_ENABLE field. + SDHOST_CLKENA_CCLK_ENABLE_Pos = 0x0 + // Bit mask of CCLK_ENABLE field. + SDHOST_CLKENA_CCLK_ENABLE_Msk = 0x3 + // Position of LP_ENABLE field. + SDHOST_CLKENA_LP_ENABLE_Pos = 0x10 + // Bit mask of LP_ENABLE field. + SDHOST_CLKENA_LP_ENABLE_Msk = 0x30000 + + // TMOUT: Data and response timeout configuration register + // Position of RESPONSE_TIMEOUT field. + SDHOST_TMOUT_RESPONSE_TIMEOUT_Pos = 0x0 + // Bit mask of RESPONSE_TIMEOUT field. + SDHOST_TMOUT_RESPONSE_TIMEOUT_Msk = 0xff + // Position of DATA_TIMEOUT field. + SDHOST_TMOUT_DATA_TIMEOUT_Pos = 0x8 + // Bit mask of DATA_TIMEOUT field. + SDHOST_TMOUT_DATA_TIMEOUT_Msk = 0xffffff00 + + // CTYPE: Card bus width configuration register + // Position of CARD_WIDTH4 field. + SDHOST_CTYPE_CARD_WIDTH4_Pos = 0x0 + // Bit mask of CARD_WIDTH4 field. + SDHOST_CTYPE_CARD_WIDTH4_Msk = 0x3 + // Position of CARD_WIDTH8 field. + SDHOST_CTYPE_CARD_WIDTH8_Pos = 0x10 + // Bit mask of CARD_WIDTH8 field. + SDHOST_CTYPE_CARD_WIDTH8_Msk = 0x30000 + + // BLKSIZ: Card data block size configuration register + // Position of BLOCK_SIZE field. + SDHOST_BLKSIZ_BLOCK_SIZE_Pos = 0x0 + // Bit mask of BLOCK_SIZE field. + SDHOST_BLKSIZ_BLOCK_SIZE_Msk = 0xffff + + // BYTCNT: Data transfer length configuration register + // Position of BYTE_COUNT field. + SDHOST_BYTCNT_BYTE_COUNT_Pos = 0x0 + // Bit mask of BYTE_COUNT field. + SDHOST_BYTCNT_BYTE_COUNT_Msk = 0xffffffff + + // INTMASK: SDIO interrupt mask register + // Position of INT_MASK field. + SDHOST_INTMASK_INT_MASK_Pos = 0x0 + // Bit mask of INT_MASK field. + SDHOST_INTMASK_INT_MASK_Msk = 0xffff + // Position of SDIO_INT_MASK field. + SDHOST_INTMASK_SDIO_INT_MASK_Pos = 0x10 + // Bit mask of SDIO_INT_MASK field. + SDHOST_INTMASK_SDIO_INT_MASK_Msk = 0x30000 + + // CMDARG: Command argument data register + // Position of CMDARG field. + SDHOST_CMDARG_CMDARG_Pos = 0x0 + // Bit mask of CMDARG field. + SDHOST_CMDARG_CMDARG_Msk = 0xffffffff + + // CMD: Command and boot configuration register + // Position of INDEX field. + SDHOST_CMD_INDEX_Pos = 0x0 + // Bit mask of INDEX field. + SDHOST_CMD_INDEX_Msk = 0x3f + // Position of RESPONSE_EXPECT field. + SDHOST_CMD_RESPONSE_EXPECT_Pos = 0x6 + // Bit mask of RESPONSE_EXPECT field. + SDHOST_CMD_RESPONSE_EXPECT_Msk = 0x40 + // Bit RESPONSE_EXPECT. + SDHOST_CMD_RESPONSE_EXPECT = 0x40 + // Position of RESPONSE_LENGTH field. + SDHOST_CMD_RESPONSE_LENGTH_Pos = 0x7 + // Bit mask of RESPONSE_LENGTH field. + SDHOST_CMD_RESPONSE_LENGTH_Msk = 0x80 + // Bit RESPONSE_LENGTH. + SDHOST_CMD_RESPONSE_LENGTH = 0x80 + // Position of CHECK_RESPONSE_CRC field. + SDHOST_CMD_CHECK_RESPONSE_CRC_Pos = 0x8 + // Bit mask of CHECK_RESPONSE_CRC field. + SDHOST_CMD_CHECK_RESPONSE_CRC_Msk = 0x100 + // Bit CHECK_RESPONSE_CRC. + SDHOST_CMD_CHECK_RESPONSE_CRC = 0x100 + // Position of DATA_EXPECTED field. + SDHOST_CMD_DATA_EXPECTED_Pos = 0x9 + // Bit mask of DATA_EXPECTED field. + SDHOST_CMD_DATA_EXPECTED_Msk = 0x200 + // Bit DATA_EXPECTED. + SDHOST_CMD_DATA_EXPECTED = 0x200 + // Position of READ_WRITE field. + SDHOST_CMD_READ_WRITE_Pos = 0xa + // Bit mask of READ_WRITE field. + SDHOST_CMD_READ_WRITE_Msk = 0x400 + // Bit READ_WRITE. + SDHOST_CMD_READ_WRITE = 0x400 + // Position of TRANSFER_MODE field. + SDHOST_CMD_TRANSFER_MODE_Pos = 0xb + // Bit mask of TRANSFER_MODE field. + SDHOST_CMD_TRANSFER_MODE_Msk = 0x800 + // Bit TRANSFER_MODE. + SDHOST_CMD_TRANSFER_MODE = 0x800 + // Position of SEND_AUTO_STOP field. + SDHOST_CMD_SEND_AUTO_STOP_Pos = 0xc + // Bit mask of SEND_AUTO_STOP field. + SDHOST_CMD_SEND_AUTO_STOP_Msk = 0x1000 + // Bit SEND_AUTO_STOP. + SDHOST_CMD_SEND_AUTO_STOP = 0x1000 + // Position of WAIT_PRVDATA_COMPLETE field. + SDHOST_CMD_WAIT_PRVDATA_COMPLETE_Pos = 0xd + // Bit mask of WAIT_PRVDATA_COMPLETE field. + SDHOST_CMD_WAIT_PRVDATA_COMPLETE_Msk = 0x2000 + // Bit WAIT_PRVDATA_COMPLETE. + SDHOST_CMD_WAIT_PRVDATA_COMPLETE = 0x2000 + // Position of STOP_ABORT_CMD field. + SDHOST_CMD_STOP_ABORT_CMD_Pos = 0xe + // Bit mask of STOP_ABORT_CMD field. + SDHOST_CMD_STOP_ABORT_CMD_Msk = 0x4000 + // Bit STOP_ABORT_CMD. + SDHOST_CMD_STOP_ABORT_CMD = 0x4000 + // Position of SEND_INITIALIZATION field. + SDHOST_CMD_SEND_INITIALIZATION_Pos = 0xf + // Bit mask of SEND_INITIALIZATION field. + SDHOST_CMD_SEND_INITIALIZATION_Msk = 0x8000 + // Bit SEND_INITIALIZATION. + SDHOST_CMD_SEND_INITIALIZATION = 0x8000 + // Position of CARD_NUMBER field. + SDHOST_CMD_CARD_NUMBER_Pos = 0x10 + // Bit mask of CARD_NUMBER field. + SDHOST_CMD_CARD_NUMBER_Msk = 0x1f0000 + // Position of UPDATE_CLOCK_REGISTERS_ONLY field. + SDHOST_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos = 0x15 + // Bit mask of UPDATE_CLOCK_REGISTERS_ONLY field. + SDHOST_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk = 0x200000 + // Bit UPDATE_CLOCK_REGISTERS_ONLY. + SDHOST_CMD_UPDATE_CLOCK_REGISTERS_ONLY = 0x200000 + // Position of READ_CEATA_DEVICE field. + SDHOST_CMD_READ_CEATA_DEVICE_Pos = 0x16 + // Bit mask of READ_CEATA_DEVICE field. + SDHOST_CMD_READ_CEATA_DEVICE_Msk = 0x400000 + // Bit READ_CEATA_DEVICE. + SDHOST_CMD_READ_CEATA_DEVICE = 0x400000 + // Position of CCS_EXPECTED field. + SDHOST_CMD_CCS_EXPECTED_Pos = 0x17 + // Bit mask of CCS_EXPECTED field. + SDHOST_CMD_CCS_EXPECTED_Msk = 0x800000 + // Bit CCS_EXPECTED. + SDHOST_CMD_CCS_EXPECTED = 0x800000 + // Position of USE_HOLE field. + SDHOST_CMD_USE_HOLE_Pos = 0x1d + // Bit mask of USE_HOLE field. + SDHOST_CMD_USE_HOLE_Msk = 0x20000000 + // Bit USE_HOLE. + SDHOST_CMD_USE_HOLE = 0x20000000 + // Position of START_CMD field. + SDHOST_CMD_START_CMD_Pos = 0x1f + // Bit mask of START_CMD field. + SDHOST_CMD_START_CMD_Msk = 0x80000000 + // Bit START_CMD. + SDHOST_CMD_START_CMD = 0x80000000 + + // RESP0: Response data register + // Position of RESPONSE0 field. + SDHOST_RESP0_RESPONSE0_Pos = 0x0 + // Bit mask of RESPONSE0 field. + SDHOST_RESP0_RESPONSE0_Msk = 0xffffffff + + // RESP1: Long response data register + // Position of RESPONSE1 field. + SDHOST_RESP1_RESPONSE1_Pos = 0x0 + // Bit mask of RESPONSE1 field. + SDHOST_RESP1_RESPONSE1_Msk = 0xffffffff + + // RESP2: Long response data register + // Position of RESPONSE2 field. + SDHOST_RESP2_RESPONSE2_Pos = 0x0 + // Bit mask of RESPONSE2 field. + SDHOST_RESP2_RESPONSE2_Msk = 0xffffffff + + // RESP3: Long response data register + // Position of RESPONSE3 field. + SDHOST_RESP3_RESPONSE3_Pos = 0x0 + // Bit mask of RESPONSE3 field. + SDHOST_RESP3_RESPONSE3_Msk = 0xffffffff + + // MINTSTS: Masked interrupt status register + // Position of INT_STATUS_MSK field. + SDHOST_MINTSTS_INT_STATUS_MSK_Pos = 0x0 + // Bit mask of INT_STATUS_MSK field. + SDHOST_MINTSTS_INT_STATUS_MSK_Msk = 0xffff + // Position of SDIO_INTERRUPT_MSK field. + SDHOST_MINTSTS_SDIO_INTERRUPT_MSK_Pos = 0x10 + // Bit mask of SDIO_INTERRUPT_MSK field. + SDHOST_MINTSTS_SDIO_INTERRUPT_MSK_Msk = 0x30000 + + // RINTSTS: Raw interrupt status register + // Position of INT_STATUS_RAW field. + SDHOST_RINTSTS_INT_STATUS_RAW_Pos = 0x0 + // Bit mask of INT_STATUS_RAW field. + SDHOST_RINTSTS_INT_STATUS_RAW_Msk = 0xffff + // Position of SDIO_INTERRUPT_RAW field. + SDHOST_RINTSTS_SDIO_INTERRUPT_RAW_Pos = 0x10 + // Bit mask of SDIO_INTERRUPT_RAW field. + SDHOST_RINTSTS_SDIO_INTERRUPT_RAW_Msk = 0x30000 + + // STATUS: SD/MMC status register + // Position of FIFO_RX_WATERMARK field. + SDHOST_STATUS_FIFO_RX_WATERMARK_Pos = 0x0 + // Bit mask of FIFO_RX_WATERMARK field. + SDHOST_STATUS_FIFO_RX_WATERMARK_Msk = 0x1 + // Bit FIFO_RX_WATERMARK. + SDHOST_STATUS_FIFO_RX_WATERMARK = 0x1 + // Position of FIFO_TX_WATERMARK field. + SDHOST_STATUS_FIFO_TX_WATERMARK_Pos = 0x1 + // Bit mask of FIFO_TX_WATERMARK field. + SDHOST_STATUS_FIFO_TX_WATERMARK_Msk = 0x2 + // Bit FIFO_TX_WATERMARK. + SDHOST_STATUS_FIFO_TX_WATERMARK = 0x2 + // Position of FIFO_EMPTY field. + SDHOST_STATUS_FIFO_EMPTY_Pos = 0x2 + // Bit mask of FIFO_EMPTY field. + SDHOST_STATUS_FIFO_EMPTY_Msk = 0x4 + // Bit FIFO_EMPTY. + SDHOST_STATUS_FIFO_EMPTY = 0x4 + // Position of FIFO_FULL field. + SDHOST_STATUS_FIFO_FULL_Pos = 0x3 + // Bit mask of FIFO_FULL field. + SDHOST_STATUS_FIFO_FULL_Msk = 0x8 + // Bit FIFO_FULL. + SDHOST_STATUS_FIFO_FULL = 0x8 + // Position of COMMAND_FSM_STATES field. + SDHOST_STATUS_COMMAND_FSM_STATES_Pos = 0x4 + // Bit mask of COMMAND_FSM_STATES field. + SDHOST_STATUS_COMMAND_FSM_STATES_Msk = 0xf0 + // Position of DATA_3_STATUS field. + SDHOST_STATUS_DATA_3_STATUS_Pos = 0x8 + // Bit mask of DATA_3_STATUS field. + SDHOST_STATUS_DATA_3_STATUS_Msk = 0x100 + // Bit DATA_3_STATUS. + SDHOST_STATUS_DATA_3_STATUS = 0x100 + // Position of DATA_BUSY field. + SDHOST_STATUS_DATA_BUSY_Pos = 0x9 + // Bit mask of DATA_BUSY field. + SDHOST_STATUS_DATA_BUSY_Msk = 0x200 + // Bit DATA_BUSY. + SDHOST_STATUS_DATA_BUSY = 0x200 + // Position of DATA_STATE_MC_BUSY field. + SDHOST_STATUS_DATA_STATE_MC_BUSY_Pos = 0xa + // Bit mask of DATA_STATE_MC_BUSY field. + SDHOST_STATUS_DATA_STATE_MC_BUSY_Msk = 0x400 + // Bit DATA_STATE_MC_BUSY. + SDHOST_STATUS_DATA_STATE_MC_BUSY = 0x400 + // Position of RESPONSE_INDEX field. + SDHOST_STATUS_RESPONSE_INDEX_Pos = 0xb + // Bit mask of RESPONSE_INDEX field. + SDHOST_STATUS_RESPONSE_INDEX_Msk = 0x1f800 + // Position of FIFO_COUNT field. + SDHOST_STATUS_FIFO_COUNT_Pos = 0x11 + // Bit mask of FIFO_COUNT field. + SDHOST_STATUS_FIFO_COUNT_Msk = 0x3ffe0000 + + // FIFOTH: FIFO configuration register + // Position of TX_WMARK field. + SDHOST_FIFOTH_TX_WMARK_Pos = 0x0 + // Bit mask of TX_WMARK field. + SDHOST_FIFOTH_TX_WMARK_Msk = 0xfff + // Position of RX_WMARK field. + SDHOST_FIFOTH_RX_WMARK_Pos = 0x10 + // Bit mask of RX_WMARK field. + SDHOST_FIFOTH_RX_WMARK_Msk = 0x7ff0000 + // Position of DMA_MULTIPLE_TRANSACTION_SIZE field. + SDHOST_FIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE_Pos = 0x1c + // Bit mask of DMA_MULTIPLE_TRANSACTION_SIZE field. + SDHOST_FIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE_Msk = 0x70000000 + + // CDETECT: Card detect register + // Position of CARD_DETECT_N field. + SDHOST_CDETECT_CARD_DETECT_N_Pos = 0x0 + // Bit mask of CARD_DETECT_N field. + SDHOST_CDETECT_CARD_DETECT_N_Msk = 0x3 + + // WRTPRT: Card write protection (WP) status register + // Position of WRITE_PROTECT field. + SDHOST_WRTPRT_WRITE_PROTECT_Pos = 0x0 + // Bit mask of WRITE_PROTECT field. + SDHOST_WRTPRT_WRITE_PROTECT_Msk = 0x3 + + // TCBCNT: Transferred byte count register + // Position of TCBCNT field. + SDHOST_TCBCNT_TCBCNT_Pos = 0x0 + // Bit mask of TCBCNT field. + SDHOST_TCBCNT_TCBCNT_Msk = 0xffffffff + + // TBBCNT: Transferred byte count register + // Position of TBBCNT field. + SDHOST_TBBCNT_TBBCNT_Pos = 0x0 + // Bit mask of TBBCNT field. + SDHOST_TBBCNT_TBBCNT_Msk = 0xffffffff + + // DEBNCE: Debounce filter time configuration register + // Position of DEBOUNCE_COUNT field. + SDHOST_DEBNCE_DEBOUNCE_COUNT_Pos = 0x0 + // Bit mask of DEBOUNCE_COUNT field. + SDHOST_DEBNCE_DEBOUNCE_COUNT_Msk = 0xffffff + + // USRID: User ID (scratchpad) register + // Position of USRID field. + SDHOST_USRID_USRID_Pos = 0x0 + // Bit mask of USRID field. + SDHOST_USRID_USRID_Msk = 0xffffffff + + // VERID: Version ID (scratchpad) register + // Position of VERSIONID field. + SDHOST_VERID_VERSIONID_Pos = 0x0 + // Bit mask of VERSIONID field. + SDHOST_VERID_VERSIONID_Msk = 0xffffffff + + // HCON: Hardware feature register + // Position of CARD_TYPE field. + SDHOST_HCON_CARD_TYPE_Pos = 0x0 + // Bit mask of CARD_TYPE field. + SDHOST_HCON_CARD_TYPE_Msk = 0x1 + // Bit CARD_TYPE. + SDHOST_HCON_CARD_TYPE = 0x1 + // Position of CARD_NUM field. + SDHOST_HCON_CARD_NUM_Pos = 0x1 + // Bit mask of CARD_NUM field. + SDHOST_HCON_CARD_NUM_Msk = 0x3e + // Position of BUS_TYPE field. + SDHOST_HCON_BUS_TYPE_Pos = 0x6 + // Bit mask of BUS_TYPE field. + SDHOST_HCON_BUS_TYPE_Msk = 0x40 + // Bit BUS_TYPE. + SDHOST_HCON_BUS_TYPE = 0x40 + // Position of DATA_WIDTH field. + SDHOST_HCON_DATA_WIDTH_Pos = 0x7 + // Bit mask of DATA_WIDTH field. + SDHOST_HCON_DATA_WIDTH_Msk = 0x380 + // Position of ADDR_WIDTH field. + SDHOST_HCON_ADDR_WIDTH_Pos = 0xa + // Bit mask of ADDR_WIDTH field. + SDHOST_HCON_ADDR_WIDTH_Msk = 0xfc00 + // Position of DMA_WIDTH field. + SDHOST_HCON_DMA_WIDTH_Pos = 0x12 + // Bit mask of DMA_WIDTH field. + SDHOST_HCON_DMA_WIDTH_Msk = 0x1c0000 + // Position of RAM_INDISE field. + SDHOST_HCON_RAM_INDISE_Pos = 0x15 + // Bit mask of RAM_INDISE field. + SDHOST_HCON_RAM_INDISE_Msk = 0x200000 + // Bit RAM_INDISE. + SDHOST_HCON_RAM_INDISE = 0x200000 + // Position of HOLD field. + SDHOST_HCON_HOLD_Pos = 0x16 + // Bit mask of HOLD field. + SDHOST_HCON_HOLD_Msk = 0x400000 + // Bit HOLD. + SDHOST_HCON_HOLD = 0x400000 + // Position of NUM_CLK_DIV field. + SDHOST_HCON_NUM_CLK_DIV_Pos = 0x18 + // Bit mask of NUM_CLK_DIV field. + SDHOST_HCON_NUM_CLK_DIV_Msk = 0x3000000 + + // UHS: UHS-1 register + // Position of DDR field. + SDHOST_UHS_DDR_Pos = 0x10 + // Bit mask of DDR field. + SDHOST_UHS_DDR_Msk = 0x30000 + + // RST_N: Card reset register + // Position of CARD_RESET field. + SDHOST_RST_N_CARD_RESET_Pos = 0x0 + // Bit mask of CARD_RESET field. + SDHOST_RST_N_CARD_RESET_Msk = 0x3 + + // BMOD: Burst mode transfer configuration register + // Position of SWR field. + SDHOST_BMOD_SWR_Pos = 0x0 + // Bit mask of SWR field. + SDHOST_BMOD_SWR_Msk = 0x1 + // Bit SWR. + SDHOST_BMOD_SWR = 0x1 + // Position of FB field. + SDHOST_BMOD_FB_Pos = 0x1 + // Bit mask of FB field. + SDHOST_BMOD_FB_Msk = 0x2 + // Bit FB. + SDHOST_BMOD_FB = 0x2 + // Position of DE field. + SDHOST_BMOD_DE_Pos = 0x7 + // Bit mask of DE field. + SDHOST_BMOD_DE_Msk = 0x80 + // Bit DE. + SDHOST_BMOD_DE = 0x80 + // Position of PBL field. + SDHOST_BMOD_PBL_Pos = 0x8 + // Bit mask of PBL field. + SDHOST_BMOD_PBL_Msk = 0x700 + + // PLDMND: Poll demand configuration register + // Position of PD field. + SDHOST_PLDMND_PD_Pos = 0x0 + // Bit mask of PD field. + SDHOST_PLDMND_PD_Msk = 0xffffffff + + // DBADDR: Descriptor base address register + // Position of DBADDR field. + SDHOST_DBADDR_DBADDR_Pos = 0x0 + // Bit mask of DBADDR field. + SDHOST_DBADDR_DBADDR_Msk = 0xffffffff + + // IDSTS: IDMAC status register + // Position of TI field. + SDHOST_IDSTS_TI_Pos = 0x0 + // Bit mask of TI field. + SDHOST_IDSTS_TI_Msk = 0x1 + // Bit TI. + SDHOST_IDSTS_TI = 0x1 + // Position of RI field. + SDHOST_IDSTS_RI_Pos = 0x1 + // Bit mask of RI field. + SDHOST_IDSTS_RI_Msk = 0x2 + // Bit RI. + SDHOST_IDSTS_RI = 0x2 + // Position of FBE field. + SDHOST_IDSTS_FBE_Pos = 0x2 + // Bit mask of FBE field. + SDHOST_IDSTS_FBE_Msk = 0x4 + // Bit FBE. + SDHOST_IDSTS_FBE = 0x4 + // Position of DU field. + SDHOST_IDSTS_DU_Pos = 0x4 + // Bit mask of DU field. + SDHOST_IDSTS_DU_Msk = 0x10 + // Bit DU. + SDHOST_IDSTS_DU = 0x10 + // Position of CES field. + SDHOST_IDSTS_CES_Pos = 0x5 + // Bit mask of CES field. + SDHOST_IDSTS_CES_Msk = 0x20 + // Bit CES. + SDHOST_IDSTS_CES = 0x20 + // Position of NIS field. + SDHOST_IDSTS_NIS_Pos = 0x8 + // Bit mask of NIS field. + SDHOST_IDSTS_NIS_Msk = 0x100 + // Bit NIS. + SDHOST_IDSTS_NIS = 0x100 + // Position of AIS field. + SDHOST_IDSTS_AIS_Pos = 0x9 + // Bit mask of AIS field. + SDHOST_IDSTS_AIS_Msk = 0x200 + // Bit AIS. + SDHOST_IDSTS_AIS = 0x200 + // Position of FBE_CODE field. + SDHOST_IDSTS_FBE_CODE_Pos = 0xa + // Bit mask of FBE_CODE field. + SDHOST_IDSTS_FBE_CODE_Msk = 0x1c00 + // Position of FSM field. + SDHOST_IDSTS_FSM_Pos = 0xd + // Bit mask of FSM field. + SDHOST_IDSTS_FSM_Msk = 0x1e000 + + // IDINTEN: IDMAC interrupt enable register + // Position of TI field. + SDHOST_IDINTEN_TI_Pos = 0x0 + // Bit mask of TI field. + SDHOST_IDINTEN_TI_Msk = 0x1 + // Bit TI. + SDHOST_IDINTEN_TI = 0x1 + // Position of RI field. + SDHOST_IDINTEN_RI_Pos = 0x1 + // Bit mask of RI field. + SDHOST_IDINTEN_RI_Msk = 0x2 + // Bit RI. + SDHOST_IDINTEN_RI = 0x2 + // Position of FBE field. + SDHOST_IDINTEN_FBE_Pos = 0x2 + // Bit mask of FBE field. + SDHOST_IDINTEN_FBE_Msk = 0x4 + // Bit FBE. + SDHOST_IDINTEN_FBE = 0x4 + // Position of DU field. + SDHOST_IDINTEN_DU_Pos = 0x4 + // Bit mask of DU field. + SDHOST_IDINTEN_DU_Msk = 0x10 + // Bit DU. + SDHOST_IDINTEN_DU = 0x10 + // Position of CES field. + SDHOST_IDINTEN_CES_Pos = 0x5 + // Bit mask of CES field. + SDHOST_IDINTEN_CES_Msk = 0x20 + // Bit CES. + SDHOST_IDINTEN_CES = 0x20 + // Position of NI field. + SDHOST_IDINTEN_NI_Pos = 0x8 + // Bit mask of NI field. + SDHOST_IDINTEN_NI_Msk = 0x100 + // Bit NI. + SDHOST_IDINTEN_NI = 0x100 + // Position of AI field. + SDHOST_IDINTEN_AI_Pos = 0x9 + // Bit mask of AI field. + SDHOST_IDINTEN_AI_Msk = 0x200 + // Bit AI. + SDHOST_IDINTEN_AI = 0x200 + + // DSCADDR: Host descriptor address pointer + // Position of DSCADDR field. + SDHOST_DSCADDR_DSCADDR_Pos = 0x0 + // Bit mask of DSCADDR field. + SDHOST_DSCADDR_DSCADDR_Msk = 0xffffffff + + // BUFADDR: Host buffer address pointer register + // Position of BUFADDR field. + SDHOST_BUFADDR_BUFADDR_Pos = 0x0 + // Bit mask of BUFADDR field. + SDHOST_BUFADDR_BUFADDR_Msk = 0xffffffff + + // CARDTHRCTL: Card Threshold Control register + // Position of CARDRDTHREN field. + SDHOST_CARDTHRCTL_CARDRDTHREN_Pos = 0x0 + // Bit mask of CARDRDTHREN field. + SDHOST_CARDTHRCTL_CARDRDTHREN_Msk = 0x1 + // Bit CARDRDTHREN. + SDHOST_CARDTHRCTL_CARDRDTHREN = 0x1 + // Position of CARDCLRINTEN field. + SDHOST_CARDTHRCTL_CARDCLRINTEN_Pos = 0x1 + // Bit mask of CARDCLRINTEN field. + SDHOST_CARDTHRCTL_CARDCLRINTEN_Msk = 0x2 + // Bit CARDCLRINTEN. + SDHOST_CARDTHRCTL_CARDCLRINTEN = 0x2 + // Position of CARDWRTHREN field. + SDHOST_CARDTHRCTL_CARDWRTHREN_Pos = 0x2 + // Bit mask of CARDWRTHREN field. + SDHOST_CARDTHRCTL_CARDWRTHREN_Msk = 0x4 + // Bit CARDWRTHREN. + SDHOST_CARDTHRCTL_CARDWRTHREN = 0x4 + // Position of CARDTHRESHOLD field. + SDHOST_CARDTHRCTL_CARDTHRESHOLD_Pos = 0x10 + // Bit mask of CARDTHRESHOLD field. + SDHOST_CARDTHRCTL_CARDTHRESHOLD_Msk = 0xffff0000 + + // EMMCDDR: eMMC DDR register + // Position of HALFSTARTBIT field. + SDHOST_EMMCDDR_HALFSTARTBIT_Pos = 0x0 + // Bit mask of HALFSTARTBIT field. + SDHOST_EMMCDDR_HALFSTARTBIT_Msk = 0x3 + // Position of HS400_MODE field. + SDHOST_EMMCDDR_HS400_MODE_Pos = 0x1f + // Bit mask of HS400_MODE field. + SDHOST_EMMCDDR_HS400_MODE_Msk = 0x80000000 + // Bit HS400_MODE. + SDHOST_EMMCDDR_HS400_MODE = 0x80000000 + + // ENSHIFT: Enable Phase Shift register + // Position of ENABLE_SHIFT field. + SDHOST_ENSHIFT_ENABLE_SHIFT_Pos = 0x0 + // Bit mask of ENABLE_SHIFT field. + SDHOST_ENSHIFT_ENABLE_SHIFT_Msk = 0xf + + // BUFFIFO: CPU write and read transmit data by FIFO + // Position of BUFFIFO field. + SDHOST_BUFFIFO_BUFFIFO_Pos = 0x0 + // Bit mask of BUFFIFO field. + SDHOST_BUFFIFO_BUFFIFO_Msk = 0xffffffff + + // CLK_EDGE_SEL: SDIO control register. + // Position of CCLKIN_EDGE_DRV_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL_Pos = 0x0 + // Bit mask of CCLKIN_EDGE_DRV_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL_Msk = 0x7 + // Position of CCLKIN_EDGE_SAM_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL_Pos = 0x3 + // Bit mask of CCLKIN_EDGE_SAM_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL_Msk = 0x38 + // Position of CCLKIN_EDGE_SLF_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL_Pos = 0x6 + // Bit mask of CCLKIN_EDGE_SLF_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL_Msk = 0x1c0 + // Position of CCLLKIN_EDGE_H field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_H_Pos = 0x9 + // Bit mask of CCLLKIN_EDGE_H field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_H_Msk = 0x1e00 + // Position of CCLLKIN_EDGE_L field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_L_Pos = 0xd + // Bit mask of CCLLKIN_EDGE_L field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_L_Msk = 0x1e000 + // Position of CCLLKIN_EDGE_N field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_N_Pos = 0x11 + // Bit mask of CCLLKIN_EDGE_N field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_N_Msk = 0x1e0000 + // Position of ESDIO_MODE field. + SDHOST_CLK_EDGE_SEL_ESDIO_MODE_Pos = 0x15 + // Bit mask of ESDIO_MODE field. + SDHOST_CLK_EDGE_SEL_ESDIO_MODE_Msk = 0x200000 + // Bit ESDIO_MODE. + SDHOST_CLK_EDGE_SEL_ESDIO_MODE = 0x200000 + // Position of ESD_MODE field. + SDHOST_CLK_EDGE_SEL_ESD_MODE_Pos = 0x16 + // Bit mask of ESD_MODE field. + SDHOST_CLK_EDGE_SEL_ESD_MODE_Msk = 0x400000 + // Bit ESD_MODE. + SDHOST_CLK_EDGE_SEL_ESD_MODE = 0x400000 + // Position of CCLK_EN field. + SDHOST_CLK_EDGE_SEL_CCLK_EN_Pos = 0x17 + // Bit mask of CCLK_EN field. + SDHOST_CLK_EDGE_SEL_CCLK_EN_Msk = 0x800000 + // Bit CCLK_EN. + SDHOST_CLK_EDGE_SEL_CCLK_EN = 0x800000 +) + +// Constants for SENS: SENS Peripheral +const ( + // SAR_READ_CTRL + // Position of SAR1_CLK_DIV field. + SENS_SAR_READ_CTRL_SAR1_CLK_DIV_Pos = 0x0 + // Bit mask of SAR1_CLK_DIV field. + SENS_SAR_READ_CTRL_SAR1_CLK_DIV_Msk = 0xff + // Position of SAR1_SAMPLE_CYCLE field. + SENS_SAR_READ_CTRL_SAR1_SAMPLE_CYCLE_Pos = 0x8 + // Bit mask of SAR1_SAMPLE_CYCLE field. + SENS_SAR_READ_CTRL_SAR1_SAMPLE_CYCLE_Msk = 0xff00 + // Position of SAR1_SAMPLE_BIT field. + SENS_SAR_READ_CTRL_SAR1_SAMPLE_BIT_Pos = 0x10 + // Bit mask of SAR1_SAMPLE_BIT field. + SENS_SAR_READ_CTRL_SAR1_SAMPLE_BIT_Msk = 0x30000 + // Position of SAR1_CLK_GATED field. + SENS_SAR_READ_CTRL_SAR1_CLK_GATED_Pos = 0x12 + // Bit mask of SAR1_CLK_GATED field. + SENS_SAR_READ_CTRL_SAR1_CLK_GATED_Msk = 0x40000 + // Bit SAR1_CLK_GATED. + SENS_SAR_READ_CTRL_SAR1_CLK_GATED = 0x40000 + // Position of SAR1_SAMPLE_NUM field. + SENS_SAR_READ_CTRL_SAR1_SAMPLE_NUM_Pos = 0x13 + // Bit mask of SAR1_SAMPLE_NUM field. + SENS_SAR_READ_CTRL_SAR1_SAMPLE_NUM_Msk = 0x7f80000 + // Position of SAR1_DIG_FORCE field. + SENS_SAR_READ_CTRL_SAR1_DIG_FORCE_Pos = 0x1b + // Bit mask of SAR1_DIG_FORCE field. + SENS_SAR_READ_CTRL_SAR1_DIG_FORCE_Msk = 0x8000000 + // Bit SAR1_DIG_FORCE. + SENS_SAR_READ_CTRL_SAR1_DIG_FORCE = 0x8000000 + // Position of SAR1_DATA_INV field. + SENS_SAR_READ_CTRL_SAR1_DATA_INV_Pos = 0x1c + // Bit mask of SAR1_DATA_INV field. + SENS_SAR_READ_CTRL_SAR1_DATA_INV_Msk = 0x10000000 + // Bit SAR1_DATA_INV. + SENS_SAR_READ_CTRL_SAR1_DATA_INV = 0x10000000 + + // SAR_READ_STATUS1 + // Position of SAR1_READER_STATUS field. + SENS_SAR_READ_STATUS1_SAR1_READER_STATUS_Pos = 0x0 + // Bit mask of SAR1_READER_STATUS field. + SENS_SAR_READ_STATUS1_SAR1_READER_STATUS_Msk = 0xffffffff + + // SAR_MEAS_WAIT1 + // Position of SAR_AMP_WAIT1 field. + SENS_SAR_MEAS_WAIT1_SAR_AMP_WAIT1_Pos = 0x0 + // Bit mask of SAR_AMP_WAIT1 field. + SENS_SAR_MEAS_WAIT1_SAR_AMP_WAIT1_Msk = 0xffff + // Position of SAR_AMP_WAIT2 field. + SENS_SAR_MEAS_WAIT1_SAR_AMP_WAIT2_Pos = 0x10 + // Bit mask of SAR_AMP_WAIT2 field. + SENS_SAR_MEAS_WAIT1_SAR_AMP_WAIT2_Msk = 0xffff0000 + + // SAR_MEAS_WAIT2 + // Position of FORCE_XPD_SAR_SW field. + SENS_SAR_MEAS_WAIT2_FORCE_XPD_SAR_SW_Pos = 0x0 + // Bit mask of FORCE_XPD_SAR_SW field. + SENS_SAR_MEAS_WAIT2_FORCE_XPD_SAR_SW_Msk = 0x1 + // Bit FORCE_XPD_SAR_SW. + SENS_SAR_MEAS_WAIT2_FORCE_XPD_SAR_SW = 0x1 + // Position of SAR_AMP_WAIT3 field. + SENS_SAR_MEAS_WAIT2_SAR_AMP_WAIT3_Pos = 0x0 + // Bit mask of SAR_AMP_WAIT3 field. + SENS_SAR_MEAS_WAIT2_SAR_AMP_WAIT3_Msk = 0xffff + // Position of FORCE_XPD_AMP field. + SENS_SAR_MEAS_WAIT2_FORCE_XPD_AMP_Pos = 0x10 + // Bit mask of FORCE_XPD_AMP field. + SENS_SAR_MEAS_WAIT2_FORCE_XPD_AMP_Msk = 0x30000 + // Position of FORCE_XPD_SAR field. + SENS_SAR_MEAS_WAIT2_FORCE_XPD_SAR_Pos = 0x12 + // Bit mask of FORCE_XPD_SAR field. + SENS_SAR_MEAS_WAIT2_FORCE_XPD_SAR_Msk = 0xc0000 + // Position of SAR2_RSTB_WAIT field. + SENS_SAR_MEAS_WAIT2_SAR2_RSTB_WAIT_Pos = 0x14 + // Bit mask of SAR2_RSTB_WAIT field. + SENS_SAR_MEAS_WAIT2_SAR2_RSTB_WAIT_Msk = 0xff00000 + + // SAR_MEAS_CTRL + // Position of XPD_SAR_AMP_FSM field. + SENS_SAR_MEAS_CTRL_XPD_SAR_AMP_FSM_Pos = 0x0 + // Bit mask of XPD_SAR_AMP_FSM field. + SENS_SAR_MEAS_CTRL_XPD_SAR_AMP_FSM_Msk = 0xf + // Position of AMP_RST_FB_FSM field. + SENS_SAR_MEAS_CTRL_AMP_RST_FB_FSM_Pos = 0x4 + // Bit mask of AMP_RST_FB_FSM field. + SENS_SAR_MEAS_CTRL_AMP_RST_FB_FSM_Msk = 0xf0 + // Position of AMP_SHORT_REF_FSM field. + SENS_SAR_MEAS_CTRL_AMP_SHORT_REF_FSM_Pos = 0x8 + // Bit mask of AMP_SHORT_REF_FSM field. + SENS_SAR_MEAS_CTRL_AMP_SHORT_REF_FSM_Msk = 0xf00 + // Position of AMP_SHORT_REF_GND_FSM field. + SENS_SAR_MEAS_CTRL_AMP_SHORT_REF_GND_FSM_Pos = 0xc + // Bit mask of AMP_SHORT_REF_GND_FSM field. + SENS_SAR_MEAS_CTRL_AMP_SHORT_REF_GND_FSM_Msk = 0xf000 + // Position of XPD_SAR_FSM field. + SENS_SAR_MEAS_CTRL_XPD_SAR_FSM_Pos = 0x10 + // Bit mask of XPD_SAR_FSM field. + SENS_SAR_MEAS_CTRL_XPD_SAR_FSM_Msk = 0xf0000 + // Position of SAR_RSTB_FSM field. + SENS_SAR_MEAS_CTRL_SAR_RSTB_FSM_Pos = 0x14 + // Bit mask of SAR_RSTB_FSM field. + SENS_SAR_MEAS_CTRL_SAR_RSTB_FSM_Msk = 0xf00000 + // Position of SAR2_XPD_WAIT field. + SENS_SAR_MEAS_CTRL_SAR2_XPD_WAIT_Pos = 0x18 + // Bit mask of SAR2_XPD_WAIT field. + SENS_SAR_MEAS_CTRL_SAR2_XPD_WAIT_Msk = 0xff000000 + + // SAR_READ_STATUS2 + // Position of SAR2_READER_STATUS field. + SENS_SAR_READ_STATUS2_SAR2_READER_STATUS_Pos = 0x0 + // Bit mask of SAR2_READER_STATUS field. + SENS_SAR_READ_STATUS2_SAR2_READER_STATUS_Msk = 0xffffffff + + // ULP_CP_SLEEP_CYC0 + // Position of SLEEP_CYCLES_S0 field. + SENS_ULP_CP_SLEEP_CYC0_SLEEP_CYCLES_S0_Pos = 0x0 + // Bit mask of SLEEP_CYCLES_S0 field. + SENS_ULP_CP_SLEEP_CYC0_SLEEP_CYCLES_S0_Msk = 0xffffffff + + // ULP_CP_SLEEP_CYC1 + // Position of SLEEP_CYCLES_S1 field. + SENS_ULP_CP_SLEEP_CYC1_SLEEP_CYCLES_S1_Pos = 0x0 + // Bit mask of SLEEP_CYCLES_S1 field. + SENS_ULP_CP_SLEEP_CYC1_SLEEP_CYCLES_S1_Msk = 0xffffffff + + // ULP_CP_SLEEP_CYC2 + // Position of SLEEP_CYCLES_S2 field. + SENS_ULP_CP_SLEEP_CYC2_SLEEP_CYCLES_S2_Pos = 0x0 + // Bit mask of SLEEP_CYCLES_S2 field. + SENS_ULP_CP_SLEEP_CYC2_SLEEP_CYCLES_S2_Msk = 0xffffffff + + // ULP_CP_SLEEP_CYC3 + // Position of SLEEP_CYCLES_S3 field. + SENS_ULP_CP_SLEEP_CYC3_SLEEP_CYCLES_S3_Pos = 0x0 + // Bit mask of SLEEP_CYCLES_S3 field. + SENS_ULP_CP_SLEEP_CYC3_SLEEP_CYCLES_S3_Msk = 0xffffffff + + // ULP_CP_SLEEP_CYC4 + // Position of SLEEP_CYCLES_S4 field. + SENS_ULP_CP_SLEEP_CYC4_SLEEP_CYCLES_S4_Pos = 0x0 + // Bit mask of SLEEP_CYCLES_S4 field. + SENS_ULP_CP_SLEEP_CYC4_SLEEP_CYCLES_S4_Msk = 0xffffffff + + // SAR_START_FORCE + // Position of SAR1_BIT_WIDTH field. + SENS_SAR_START_FORCE_SAR1_BIT_WIDTH_Pos = 0x0 + // Bit mask of SAR1_BIT_WIDTH field. + SENS_SAR_START_FORCE_SAR1_BIT_WIDTH_Msk = 0x3 + // Position of SAR2_BIT_WIDTH field. + SENS_SAR_START_FORCE_SAR2_BIT_WIDTH_Pos = 0x2 + // Bit mask of SAR2_BIT_WIDTH field. + SENS_SAR_START_FORCE_SAR2_BIT_WIDTH_Msk = 0xc + // Position of SAR2_EN_TEST field. + SENS_SAR_START_FORCE_SAR2_EN_TEST_Pos = 0x4 + // Bit mask of SAR2_EN_TEST field. + SENS_SAR_START_FORCE_SAR2_EN_TEST_Msk = 0x10 + // Bit SAR2_EN_TEST. + SENS_SAR_START_FORCE_SAR2_EN_TEST = 0x10 + // Position of SAR2_PWDET_CCT field. + SENS_SAR_START_FORCE_SAR2_PWDET_CCT_Pos = 0x5 + // Bit mask of SAR2_PWDET_CCT field. + SENS_SAR_START_FORCE_SAR2_PWDET_CCT_Msk = 0xe0 + // Position of ULP_CP_FORCE_START_TOP field. + SENS_SAR_START_FORCE_ULP_CP_FORCE_START_TOP_Pos = 0x8 + // Bit mask of ULP_CP_FORCE_START_TOP field. + SENS_SAR_START_FORCE_ULP_CP_FORCE_START_TOP_Msk = 0x100 + // Bit ULP_CP_FORCE_START_TOP. + SENS_SAR_START_FORCE_ULP_CP_FORCE_START_TOP = 0x100 + // Position of ULP_CP_START_TOP field. + SENS_SAR_START_FORCE_ULP_CP_START_TOP_Pos = 0x9 + // Bit mask of ULP_CP_START_TOP field. + SENS_SAR_START_FORCE_ULP_CP_START_TOP_Msk = 0x200 + // Bit ULP_CP_START_TOP. + SENS_SAR_START_FORCE_ULP_CP_START_TOP = 0x200 + // Position of SARCLK_EN field. + SENS_SAR_START_FORCE_SARCLK_EN_Pos = 0xa + // Bit mask of SARCLK_EN field. + SENS_SAR_START_FORCE_SARCLK_EN_Msk = 0x400 + // Bit SARCLK_EN. + SENS_SAR_START_FORCE_SARCLK_EN = 0x400 + // Position of PC_INIT field. + SENS_SAR_START_FORCE_PC_INIT_Pos = 0xb + // Bit mask of PC_INIT field. + SENS_SAR_START_FORCE_PC_INIT_Msk = 0x3ff800 + // Position of SAR2_STOP field. + SENS_SAR_START_FORCE_SAR2_STOP_Pos = 0x16 + // Bit mask of SAR2_STOP field. + SENS_SAR_START_FORCE_SAR2_STOP_Msk = 0x400000 + // Bit SAR2_STOP. + SENS_SAR_START_FORCE_SAR2_STOP = 0x400000 + // Position of SAR1_STOP field. + SENS_SAR_START_FORCE_SAR1_STOP_Pos = 0x17 + // Bit mask of SAR1_STOP field. + SENS_SAR_START_FORCE_SAR1_STOP_Msk = 0x800000 + // Bit SAR1_STOP. + SENS_SAR_START_FORCE_SAR1_STOP = 0x800000 + // Position of SAR2_PWDET_EN field. + SENS_SAR_START_FORCE_SAR2_PWDET_EN_Pos = 0x18 + // Bit mask of SAR2_PWDET_EN field. + SENS_SAR_START_FORCE_SAR2_PWDET_EN_Msk = 0x1000000 + // Bit SAR2_PWDET_EN. + SENS_SAR_START_FORCE_SAR2_PWDET_EN = 0x1000000 + + // SAR_MEM_WR_CTRL + // Position of MEM_WR_ADDR_INIT field. + SENS_SAR_MEM_WR_CTRL_MEM_WR_ADDR_INIT_Pos = 0x0 + // Bit mask of MEM_WR_ADDR_INIT field. + SENS_SAR_MEM_WR_CTRL_MEM_WR_ADDR_INIT_Msk = 0x7ff + // Position of MEM_WR_ADDR_SIZE field. + SENS_SAR_MEM_WR_CTRL_MEM_WR_ADDR_SIZE_Pos = 0xb + // Bit mask of MEM_WR_ADDR_SIZE field. + SENS_SAR_MEM_WR_CTRL_MEM_WR_ADDR_SIZE_Msk = 0x3ff800 + // Position of RTC_MEM_WR_OFFST_CLR field. + SENS_SAR_MEM_WR_CTRL_RTC_MEM_WR_OFFST_CLR_Pos = 0x16 + // Bit mask of RTC_MEM_WR_OFFST_CLR field. + SENS_SAR_MEM_WR_CTRL_RTC_MEM_WR_OFFST_CLR_Msk = 0x400000 + // Bit RTC_MEM_WR_OFFST_CLR. + SENS_SAR_MEM_WR_CTRL_RTC_MEM_WR_OFFST_CLR = 0x400000 + + // SAR_ATTEN1 + // Position of SAR1_ATTEN field. + SENS_SAR_ATTEN1_SAR1_ATTEN_Pos = 0x0 + // Bit mask of SAR1_ATTEN field. + SENS_SAR_ATTEN1_SAR1_ATTEN_Msk = 0xffffffff + + // SAR_ATTEN2 + // Position of SAR2_ATTEN field. + SENS_SAR_ATTEN2_SAR2_ATTEN_Pos = 0x0 + // Bit mask of SAR2_ATTEN field. + SENS_SAR_ATTEN2_SAR2_ATTEN_Msk = 0xffffffff + + // SAR_SLAVE_ADDR1 + // Position of I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0_Msk = 0x3ff800 + // Position of MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_MEAS_STATUS_Pos = 0x16 + // Bit mask of MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_MEAS_STATUS_Msk = 0x3fc00000 + + // SAR_SLAVE_ADDR2 + // Position of I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2_Msk = 0x3ff800 + + // SAR_SLAVE_ADDR3 + // Position of I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4_Msk = 0x3ff800 + // Position of TSENS_OUT field. + SENS_SAR_SLAVE_ADDR3_TSENS_OUT_Pos = 0x16 + // Bit mask of TSENS_OUT field. + SENS_SAR_SLAVE_ADDR3_TSENS_OUT_Msk = 0x3fc00000 + // Position of TSENS_RDY_OUT field. + SENS_SAR_SLAVE_ADDR3_TSENS_RDY_OUT_Pos = 0x1e + // Bit mask of TSENS_RDY_OUT field. + SENS_SAR_SLAVE_ADDR3_TSENS_RDY_OUT_Msk = 0x40000000 + // Bit TSENS_RDY_OUT. + SENS_SAR_SLAVE_ADDR3_TSENS_RDY_OUT = 0x40000000 + + // SAR_SLAVE_ADDR4 + // Position of I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6_Msk = 0x3ff800 + // Position of I2C_RDATA field. + SENS_SAR_SLAVE_ADDR4_I2C_RDATA_Pos = 0x16 + // Bit mask of I2C_RDATA field. + SENS_SAR_SLAVE_ADDR4_I2C_RDATA_Msk = 0x3fc00000 + // Position of I2C_DONE field. + SENS_SAR_SLAVE_ADDR4_I2C_DONE_Pos = 0x1e + // Bit mask of I2C_DONE field. + SENS_SAR_SLAVE_ADDR4_I2C_DONE_Msk = 0x40000000 + // Bit I2C_DONE. + SENS_SAR_SLAVE_ADDR4_I2C_DONE = 0x40000000 + + // SAR_TSENS_CTRL + // Position of TSENS_XPD_WAIT field. + SENS_SAR_TSENS_CTRL_TSENS_XPD_WAIT_Pos = 0x0 + // Bit mask of TSENS_XPD_WAIT field. + SENS_SAR_TSENS_CTRL_TSENS_XPD_WAIT_Msk = 0xfff + // Position of TSENS_XPD_FORCE field. + SENS_SAR_TSENS_CTRL_TSENS_XPD_FORCE_Pos = 0xc + // Bit mask of TSENS_XPD_FORCE field. + SENS_SAR_TSENS_CTRL_TSENS_XPD_FORCE_Msk = 0x1000 + // Bit TSENS_XPD_FORCE. + SENS_SAR_TSENS_CTRL_TSENS_XPD_FORCE = 0x1000 + // Position of TSENS_CLK_INV field. + SENS_SAR_TSENS_CTRL_TSENS_CLK_INV_Pos = 0xd + // Bit mask of TSENS_CLK_INV field. + SENS_SAR_TSENS_CTRL_TSENS_CLK_INV_Msk = 0x2000 + // Bit TSENS_CLK_INV. + SENS_SAR_TSENS_CTRL_TSENS_CLK_INV = 0x2000 + // Position of TSENS_CLK_GATED field. + SENS_SAR_TSENS_CTRL_TSENS_CLK_GATED_Pos = 0xe + // Bit mask of TSENS_CLK_GATED field. + SENS_SAR_TSENS_CTRL_TSENS_CLK_GATED_Msk = 0x4000 + // Bit TSENS_CLK_GATED. + SENS_SAR_TSENS_CTRL_TSENS_CLK_GATED = 0x4000 + // Position of TSENS_IN_INV field. + SENS_SAR_TSENS_CTRL_TSENS_IN_INV_Pos = 0xf + // Bit mask of TSENS_IN_INV field. + SENS_SAR_TSENS_CTRL_TSENS_IN_INV_Msk = 0x8000 + // Bit TSENS_IN_INV. + SENS_SAR_TSENS_CTRL_TSENS_IN_INV = 0x8000 + // Position of TSENS_CLK_DIV field. + SENS_SAR_TSENS_CTRL_TSENS_CLK_DIV_Pos = 0x10 + // Bit mask of TSENS_CLK_DIV field. + SENS_SAR_TSENS_CTRL_TSENS_CLK_DIV_Msk = 0xff0000 + // Position of TSENS_POWER_UP field. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_Pos = 0x18 + // Bit mask of TSENS_POWER_UP field. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_Msk = 0x1000000 + // Bit TSENS_POWER_UP. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP = 0x1000000 + // Position of TSENS_POWER_UP_FORCE field. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_FORCE_Pos = 0x19 + // Bit mask of TSENS_POWER_UP_FORCE field. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_FORCE_Msk = 0x2000000 + // Bit TSENS_POWER_UP_FORCE. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_FORCE = 0x2000000 + // Position of TSENS_DUMP_OUT field. + SENS_SAR_TSENS_CTRL_TSENS_DUMP_OUT_Pos = 0x1a + // Bit mask of TSENS_DUMP_OUT field. + SENS_SAR_TSENS_CTRL_TSENS_DUMP_OUT_Msk = 0x4000000 + // Bit TSENS_DUMP_OUT. + SENS_SAR_TSENS_CTRL_TSENS_DUMP_OUT = 0x4000000 + + // SAR_I2C_CTRL + // Position of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Pos = 0x0 + // Bit mask of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Msk = 0xfffffff + // Position of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Pos = 0x1c + // Bit mask of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Msk = 0x10000000 + // Bit SAR_I2C_START. + SENS_SAR_I2C_CTRL_SAR_I2C_START = 0x10000000 + // Position of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Pos = 0x1d + // Bit mask of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Msk = 0x20000000 + // Bit SAR_I2C_START_FORCE. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE = 0x20000000 + + // SAR_MEAS_START1 + // Position of MEAS1_DATA_SAR field. + SENS_SAR_MEAS_START1_MEAS1_DATA_SAR_Pos = 0x0 + // Bit mask of MEAS1_DATA_SAR field. + SENS_SAR_MEAS_START1_MEAS1_DATA_SAR_Msk = 0xffff + // Position of MEAS1_DONE_SAR field. + SENS_SAR_MEAS_START1_MEAS1_DONE_SAR_Pos = 0x10 + // Bit mask of MEAS1_DONE_SAR field. + SENS_SAR_MEAS_START1_MEAS1_DONE_SAR_Msk = 0x10000 + // Bit MEAS1_DONE_SAR. + SENS_SAR_MEAS_START1_MEAS1_DONE_SAR = 0x10000 + // Position of MEAS1_START_SAR field. + SENS_SAR_MEAS_START1_MEAS1_START_SAR_Pos = 0x11 + // Bit mask of MEAS1_START_SAR field. + SENS_SAR_MEAS_START1_MEAS1_START_SAR_Msk = 0x20000 + // Bit MEAS1_START_SAR. + SENS_SAR_MEAS_START1_MEAS1_START_SAR = 0x20000 + // Position of MEAS1_START_FORCE field. + SENS_SAR_MEAS_START1_MEAS1_START_FORCE_Pos = 0x12 + // Bit mask of MEAS1_START_FORCE field. + SENS_SAR_MEAS_START1_MEAS1_START_FORCE_Msk = 0x40000 + // Bit MEAS1_START_FORCE. + SENS_SAR_MEAS_START1_MEAS1_START_FORCE = 0x40000 + // Position of SAR1_EN_PAD field. + SENS_SAR_MEAS_START1_SAR1_EN_PAD_Pos = 0x13 + // Bit mask of SAR1_EN_PAD field. + SENS_SAR_MEAS_START1_SAR1_EN_PAD_Msk = 0x7ff80000 + // Position of SAR1_EN_PAD_FORCE field. + SENS_SAR_MEAS_START1_SAR1_EN_PAD_FORCE_Pos = 0x1f + // Bit mask of SAR1_EN_PAD_FORCE field. + SENS_SAR_MEAS_START1_SAR1_EN_PAD_FORCE_Msk = 0x80000000 + // Bit SAR1_EN_PAD_FORCE. + SENS_SAR_MEAS_START1_SAR1_EN_PAD_FORCE = 0x80000000 + + // SAR_TOUCH_CTRL1 + // Position of TOUCH_MEAS_DELAY field. + SENS_SAR_TOUCH_CTRL1_TOUCH_MEAS_DELAY_Pos = 0x0 + // Bit mask of TOUCH_MEAS_DELAY field. + SENS_SAR_TOUCH_CTRL1_TOUCH_MEAS_DELAY_Msk = 0xffff + // Position of TOUCH_XPD_WAIT field. + SENS_SAR_TOUCH_CTRL1_TOUCH_XPD_WAIT_Pos = 0x10 + // Bit mask of TOUCH_XPD_WAIT field. + SENS_SAR_TOUCH_CTRL1_TOUCH_XPD_WAIT_Msk = 0xff0000 + // Position of TOUCH_OUT_SEL field. + SENS_SAR_TOUCH_CTRL1_TOUCH_OUT_SEL_Pos = 0x18 + // Bit mask of TOUCH_OUT_SEL field. + SENS_SAR_TOUCH_CTRL1_TOUCH_OUT_SEL_Msk = 0x1000000 + // Bit TOUCH_OUT_SEL. + SENS_SAR_TOUCH_CTRL1_TOUCH_OUT_SEL = 0x1000000 + // Position of TOUCH_OUT_1EN field. + SENS_SAR_TOUCH_CTRL1_TOUCH_OUT_1EN_Pos = 0x19 + // Bit mask of TOUCH_OUT_1EN field. + SENS_SAR_TOUCH_CTRL1_TOUCH_OUT_1EN_Msk = 0x2000000 + // Bit TOUCH_OUT_1EN. + SENS_SAR_TOUCH_CTRL1_TOUCH_OUT_1EN = 0x2000000 + // Position of XPD_HALL_FORCE field. + SENS_SAR_TOUCH_CTRL1_XPD_HALL_FORCE_Pos = 0x1a + // Bit mask of XPD_HALL_FORCE field. + SENS_SAR_TOUCH_CTRL1_XPD_HALL_FORCE_Msk = 0x4000000 + // Bit XPD_HALL_FORCE. + SENS_SAR_TOUCH_CTRL1_XPD_HALL_FORCE = 0x4000000 + // Position of HALL_PHASE_FORCE field. + SENS_SAR_TOUCH_CTRL1_HALL_PHASE_FORCE_Pos = 0x1b + // Bit mask of HALL_PHASE_FORCE field. + SENS_SAR_TOUCH_CTRL1_HALL_PHASE_FORCE_Msk = 0x8000000 + // Bit HALL_PHASE_FORCE. + SENS_SAR_TOUCH_CTRL1_HALL_PHASE_FORCE = 0x8000000 + + // SAR_TOUCH_THRES1 + // Position of TOUCH_OUT_TH1 field. + SENS_SAR_TOUCH_THRES1_TOUCH_OUT_TH1_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH1 field. + SENS_SAR_TOUCH_THRES1_TOUCH_OUT_TH1_Msk = 0xffff + // Position of TOUCH_OUT_TH0 field. + SENS_SAR_TOUCH_THRES1_TOUCH_OUT_TH0_Pos = 0x10 + // Bit mask of TOUCH_OUT_TH0 field. + SENS_SAR_TOUCH_THRES1_TOUCH_OUT_TH0_Msk = 0xffff0000 + + // SAR_TOUCH_THRES2 + // Position of TOUCH_OUT_TH3 field. + SENS_SAR_TOUCH_THRES2_TOUCH_OUT_TH3_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH3 field. + SENS_SAR_TOUCH_THRES2_TOUCH_OUT_TH3_Msk = 0xffff + // Position of TOUCH_OUT_TH2 field. + SENS_SAR_TOUCH_THRES2_TOUCH_OUT_TH2_Pos = 0x10 + // Bit mask of TOUCH_OUT_TH2 field. + SENS_SAR_TOUCH_THRES2_TOUCH_OUT_TH2_Msk = 0xffff0000 + + // SAR_TOUCH_THRES3 + // Position of TOUCH_OUT_TH5 field. + SENS_SAR_TOUCH_THRES3_TOUCH_OUT_TH5_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH5 field. + SENS_SAR_TOUCH_THRES3_TOUCH_OUT_TH5_Msk = 0xffff + // Position of TOUCH_OUT_TH4 field. + SENS_SAR_TOUCH_THRES3_TOUCH_OUT_TH4_Pos = 0x10 + // Bit mask of TOUCH_OUT_TH4 field. + SENS_SAR_TOUCH_THRES3_TOUCH_OUT_TH4_Msk = 0xffff0000 + + // SAR_TOUCH_THRES4 + // Position of TOUCH_OUT_TH7 field. + SENS_SAR_TOUCH_THRES4_TOUCH_OUT_TH7_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH7 field. + SENS_SAR_TOUCH_THRES4_TOUCH_OUT_TH7_Msk = 0xffff + // Position of TOUCH_OUT_TH6 field. + SENS_SAR_TOUCH_THRES4_TOUCH_OUT_TH6_Pos = 0x10 + // Bit mask of TOUCH_OUT_TH6 field. + SENS_SAR_TOUCH_THRES4_TOUCH_OUT_TH6_Msk = 0xffff0000 + + // SAR_TOUCH_THRES5 + // Position of TOUCH_OUT_TH9 field. + SENS_SAR_TOUCH_THRES5_TOUCH_OUT_TH9_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH9 field. + SENS_SAR_TOUCH_THRES5_TOUCH_OUT_TH9_Msk = 0xffff + // Position of TOUCH_OUT_TH8 field. + SENS_SAR_TOUCH_THRES5_TOUCH_OUT_TH8_Pos = 0x10 + // Bit mask of TOUCH_OUT_TH8 field. + SENS_SAR_TOUCH_THRES5_TOUCH_OUT_TH8_Msk = 0xffff0000 + + // SAR_TOUCH_OUT1 + // Position of TOUCH_MEAS_OUT1 field. + SENS_SAR_TOUCH_OUT1_TOUCH_MEAS_OUT1_Pos = 0x0 + // Bit mask of TOUCH_MEAS_OUT1 field. + SENS_SAR_TOUCH_OUT1_TOUCH_MEAS_OUT1_Msk = 0xffff + // Position of TOUCH_MEAS_OUT0 field. + SENS_SAR_TOUCH_OUT1_TOUCH_MEAS_OUT0_Pos = 0x10 + // Bit mask of TOUCH_MEAS_OUT0 field. + SENS_SAR_TOUCH_OUT1_TOUCH_MEAS_OUT0_Msk = 0xffff0000 + + // SAR_TOUCH_OUT2 + // Position of TOUCH_MEAS_OUT3 field. + SENS_SAR_TOUCH_OUT2_TOUCH_MEAS_OUT3_Pos = 0x0 + // Bit mask of TOUCH_MEAS_OUT3 field. + SENS_SAR_TOUCH_OUT2_TOUCH_MEAS_OUT3_Msk = 0xffff + // Position of TOUCH_MEAS_OUT2 field. + SENS_SAR_TOUCH_OUT2_TOUCH_MEAS_OUT2_Pos = 0x10 + // Bit mask of TOUCH_MEAS_OUT2 field. + SENS_SAR_TOUCH_OUT2_TOUCH_MEAS_OUT2_Msk = 0xffff0000 + + // SAR_TOUCH_OUT3 + // Position of TOUCH_MEAS_OUT5 field. + SENS_SAR_TOUCH_OUT3_TOUCH_MEAS_OUT5_Pos = 0x0 + // Bit mask of TOUCH_MEAS_OUT5 field. + SENS_SAR_TOUCH_OUT3_TOUCH_MEAS_OUT5_Msk = 0xffff + // Position of TOUCH_MEAS_OUT4 field. + SENS_SAR_TOUCH_OUT3_TOUCH_MEAS_OUT4_Pos = 0x10 + // Bit mask of TOUCH_MEAS_OUT4 field. + SENS_SAR_TOUCH_OUT3_TOUCH_MEAS_OUT4_Msk = 0xffff0000 + + // SAR_TOUCH_OUT4 + // Position of TOUCH_MEAS_OUT7 field. + SENS_SAR_TOUCH_OUT4_TOUCH_MEAS_OUT7_Pos = 0x0 + // Bit mask of TOUCH_MEAS_OUT7 field. + SENS_SAR_TOUCH_OUT4_TOUCH_MEAS_OUT7_Msk = 0xffff + // Position of TOUCH_MEAS_OUT6 field. + SENS_SAR_TOUCH_OUT4_TOUCH_MEAS_OUT6_Pos = 0x10 + // Bit mask of TOUCH_MEAS_OUT6 field. + SENS_SAR_TOUCH_OUT4_TOUCH_MEAS_OUT6_Msk = 0xffff0000 + + // SAR_TOUCH_OUT5 + // Position of TOUCH_MEAS_OUT9 field. + SENS_SAR_TOUCH_OUT5_TOUCH_MEAS_OUT9_Pos = 0x0 + // Bit mask of TOUCH_MEAS_OUT9 field. + SENS_SAR_TOUCH_OUT5_TOUCH_MEAS_OUT9_Msk = 0xffff + // Position of TOUCH_MEAS_OUT8 field. + SENS_SAR_TOUCH_OUT5_TOUCH_MEAS_OUT8_Pos = 0x10 + // Bit mask of TOUCH_MEAS_OUT8 field. + SENS_SAR_TOUCH_OUT5_TOUCH_MEAS_OUT8_Msk = 0xffff0000 + + // SAR_TOUCH_CTRL2 + // Position of TOUCH_MEAS_EN field. + SENS_SAR_TOUCH_CTRL2_TOUCH_MEAS_EN_Pos = 0x0 + // Bit mask of TOUCH_MEAS_EN field. + SENS_SAR_TOUCH_CTRL2_TOUCH_MEAS_EN_Msk = 0x3ff + // Position of TOUCH_MEAS_DONE field. + SENS_SAR_TOUCH_CTRL2_TOUCH_MEAS_DONE_Pos = 0xa + // Bit mask of TOUCH_MEAS_DONE field. + SENS_SAR_TOUCH_CTRL2_TOUCH_MEAS_DONE_Msk = 0x400 + // Bit TOUCH_MEAS_DONE. + SENS_SAR_TOUCH_CTRL2_TOUCH_MEAS_DONE = 0x400 + // Position of TOUCH_START_FSM_EN field. + SENS_SAR_TOUCH_CTRL2_TOUCH_START_FSM_EN_Pos = 0xb + // Bit mask of TOUCH_START_FSM_EN field. + SENS_SAR_TOUCH_CTRL2_TOUCH_START_FSM_EN_Msk = 0x800 + // Bit TOUCH_START_FSM_EN. + SENS_SAR_TOUCH_CTRL2_TOUCH_START_FSM_EN = 0x800 + // Position of TOUCH_START_EN field. + SENS_SAR_TOUCH_CTRL2_TOUCH_START_EN_Pos = 0xc + // Bit mask of TOUCH_START_EN field. + SENS_SAR_TOUCH_CTRL2_TOUCH_START_EN_Msk = 0x1000 + // Bit TOUCH_START_EN. + SENS_SAR_TOUCH_CTRL2_TOUCH_START_EN = 0x1000 + // Position of TOUCH_START_FORCE field. + SENS_SAR_TOUCH_CTRL2_TOUCH_START_FORCE_Pos = 0xd + // Bit mask of TOUCH_START_FORCE field. + SENS_SAR_TOUCH_CTRL2_TOUCH_START_FORCE_Msk = 0x2000 + // Bit TOUCH_START_FORCE. + SENS_SAR_TOUCH_CTRL2_TOUCH_START_FORCE = 0x2000 + // Position of TOUCH_SLEEP_CYCLES field. + SENS_SAR_TOUCH_CTRL2_TOUCH_SLEEP_CYCLES_Pos = 0xe + // Bit mask of TOUCH_SLEEP_CYCLES field. + SENS_SAR_TOUCH_CTRL2_TOUCH_SLEEP_CYCLES_Msk = 0x3fffc000 + // Position of TOUCH_MEAS_EN_CLR field. + SENS_SAR_TOUCH_CTRL2_TOUCH_MEAS_EN_CLR_Pos = 0x1e + // Bit mask of TOUCH_MEAS_EN_CLR field. + SENS_SAR_TOUCH_CTRL2_TOUCH_MEAS_EN_CLR_Msk = 0x40000000 + // Bit TOUCH_MEAS_EN_CLR. + SENS_SAR_TOUCH_CTRL2_TOUCH_MEAS_EN_CLR = 0x40000000 + + // SAR_TOUCH_ENABLE + // Position of TOUCH_PAD_WORKEN field. + SENS_SAR_TOUCH_ENABLE_TOUCH_PAD_WORKEN_Pos = 0x0 + // Bit mask of TOUCH_PAD_WORKEN field. + SENS_SAR_TOUCH_ENABLE_TOUCH_PAD_WORKEN_Msk = 0x3ff + // Position of TOUCH_PAD_OUTEN2 field. + SENS_SAR_TOUCH_ENABLE_TOUCH_PAD_OUTEN2_Pos = 0xa + // Bit mask of TOUCH_PAD_OUTEN2 field. + SENS_SAR_TOUCH_ENABLE_TOUCH_PAD_OUTEN2_Msk = 0xffc00 + // Position of TOUCH_PAD_OUTEN1 field. + SENS_SAR_TOUCH_ENABLE_TOUCH_PAD_OUTEN1_Pos = 0x14 + // Bit mask of TOUCH_PAD_OUTEN1 field. + SENS_SAR_TOUCH_ENABLE_TOUCH_PAD_OUTEN1_Msk = 0x3ff00000 + + // SAR_READ_CTRL2 + // Position of SAR2_CLK_DIV field. + SENS_SAR_READ_CTRL2_SAR2_CLK_DIV_Pos = 0x0 + // Bit mask of SAR2_CLK_DIV field. + SENS_SAR_READ_CTRL2_SAR2_CLK_DIV_Msk = 0xff + // Position of SAR2_SAMPLE_CYCLE field. + SENS_SAR_READ_CTRL2_SAR2_SAMPLE_CYCLE_Pos = 0x8 + // Bit mask of SAR2_SAMPLE_CYCLE field. + SENS_SAR_READ_CTRL2_SAR2_SAMPLE_CYCLE_Msk = 0xff00 + // Position of SAR2_SAMPLE_BIT field. + SENS_SAR_READ_CTRL2_SAR2_SAMPLE_BIT_Pos = 0x10 + // Bit mask of SAR2_SAMPLE_BIT field. + SENS_SAR_READ_CTRL2_SAR2_SAMPLE_BIT_Msk = 0x30000 + // Position of SAR2_CLK_GATED field. + SENS_SAR_READ_CTRL2_SAR2_CLK_GATED_Pos = 0x12 + // Bit mask of SAR2_CLK_GATED field. + SENS_SAR_READ_CTRL2_SAR2_CLK_GATED_Msk = 0x40000 + // Bit SAR2_CLK_GATED. + SENS_SAR_READ_CTRL2_SAR2_CLK_GATED = 0x40000 + // Position of SAR2_SAMPLE_NUM field. + SENS_SAR_READ_CTRL2_SAR2_SAMPLE_NUM_Pos = 0x13 + // Bit mask of SAR2_SAMPLE_NUM field. + SENS_SAR_READ_CTRL2_SAR2_SAMPLE_NUM_Msk = 0x7f80000 + // Position of SAR2_PWDET_FORCE field. + SENS_SAR_READ_CTRL2_SAR2_PWDET_FORCE_Pos = 0x1b + // Bit mask of SAR2_PWDET_FORCE field. + SENS_SAR_READ_CTRL2_SAR2_PWDET_FORCE_Msk = 0x8000000 + // Bit SAR2_PWDET_FORCE. + SENS_SAR_READ_CTRL2_SAR2_PWDET_FORCE = 0x8000000 + // Position of SAR2_DIG_FORCE field. + SENS_SAR_READ_CTRL2_SAR2_DIG_FORCE_Pos = 0x1c + // Bit mask of SAR2_DIG_FORCE field. + SENS_SAR_READ_CTRL2_SAR2_DIG_FORCE_Msk = 0x10000000 + // Bit SAR2_DIG_FORCE. + SENS_SAR_READ_CTRL2_SAR2_DIG_FORCE = 0x10000000 + // Position of SAR2_DATA_INV field. + SENS_SAR_READ_CTRL2_SAR2_DATA_INV_Pos = 0x1d + // Bit mask of SAR2_DATA_INV field. + SENS_SAR_READ_CTRL2_SAR2_DATA_INV_Msk = 0x20000000 + // Bit SAR2_DATA_INV. + SENS_SAR_READ_CTRL2_SAR2_DATA_INV = 0x20000000 + + // SAR_MEAS_START2 + // Position of MEAS2_DATA_SAR field. + SENS_SAR_MEAS_START2_MEAS2_DATA_SAR_Pos = 0x0 + // Bit mask of MEAS2_DATA_SAR field. + SENS_SAR_MEAS_START2_MEAS2_DATA_SAR_Msk = 0xffff + // Position of MEAS2_DONE_SAR field. + SENS_SAR_MEAS_START2_MEAS2_DONE_SAR_Pos = 0x10 + // Bit mask of MEAS2_DONE_SAR field. + SENS_SAR_MEAS_START2_MEAS2_DONE_SAR_Msk = 0x10000 + // Bit MEAS2_DONE_SAR. + SENS_SAR_MEAS_START2_MEAS2_DONE_SAR = 0x10000 + // Position of MEAS2_START_SAR field. + SENS_SAR_MEAS_START2_MEAS2_START_SAR_Pos = 0x11 + // Bit mask of MEAS2_START_SAR field. + SENS_SAR_MEAS_START2_MEAS2_START_SAR_Msk = 0x20000 + // Bit MEAS2_START_SAR. + SENS_SAR_MEAS_START2_MEAS2_START_SAR = 0x20000 + // Position of MEAS2_START_FORCE field. + SENS_SAR_MEAS_START2_MEAS2_START_FORCE_Pos = 0x12 + // Bit mask of MEAS2_START_FORCE field. + SENS_SAR_MEAS_START2_MEAS2_START_FORCE_Msk = 0x40000 + // Bit MEAS2_START_FORCE. + SENS_SAR_MEAS_START2_MEAS2_START_FORCE = 0x40000 + // Position of SAR2_EN_PAD field. + SENS_SAR_MEAS_START2_SAR2_EN_PAD_Pos = 0x13 + // Bit mask of SAR2_EN_PAD field. + SENS_SAR_MEAS_START2_SAR2_EN_PAD_Msk = 0x7ff80000 + // Position of SAR2_EN_PAD_FORCE field. + SENS_SAR_MEAS_START2_SAR2_EN_PAD_FORCE_Pos = 0x1f + // Bit mask of SAR2_EN_PAD_FORCE field. + SENS_SAR_MEAS_START2_SAR2_EN_PAD_FORCE_Msk = 0x80000000 + // Bit SAR2_EN_PAD_FORCE. + SENS_SAR_MEAS_START2_SAR2_EN_PAD_FORCE = 0x80000000 + + // SAR_DAC_CTRL1 + // Position of SW_FSTEP field. + SENS_SAR_DAC_CTRL1_SW_FSTEP_Pos = 0x0 + // Bit mask of SW_FSTEP field. + SENS_SAR_DAC_CTRL1_SW_FSTEP_Msk = 0xffff + // Position of SW_TONE_EN field. + SENS_SAR_DAC_CTRL1_SW_TONE_EN_Pos = 0x10 + // Bit mask of SW_TONE_EN field. + SENS_SAR_DAC_CTRL1_SW_TONE_EN_Msk = 0x10000 + // Bit SW_TONE_EN. + SENS_SAR_DAC_CTRL1_SW_TONE_EN = 0x10000 + // Position of DEBUG_BIT_SEL field. + SENS_SAR_DAC_CTRL1_DEBUG_BIT_SEL_Pos = 0x11 + // Bit mask of DEBUG_BIT_SEL field. + SENS_SAR_DAC_CTRL1_DEBUG_BIT_SEL_Msk = 0x3e0000 + // Position of DAC_DIG_FORCE field. + SENS_SAR_DAC_CTRL1_DAC_DIG_FORCE_Pos = 0x16 + // Bit mask of DAC_DIG_FORCE field. + SENS_SAR_DAC_CTRL1_DAC_DIG_FORCE_Msk = 0x400000 + // Bit DAC_DIG_FORCE. + SENS_SAR_DAC_CTRL1_DAC_DIG_FORCE = 0x400000 + // Position of DAC_CLK_FORCE_LOW field. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_LOW_Pos = 0x17 + // Bit mask of DAC_CLK_FORCE_LOW field. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_LOW_Msk = 0x800000 + // Bit DAC_CLK_FORCE_LOW. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_LOW = 0x800000 + // Position of DAC_CLK_FORCE_HIGH field. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH_Pos = 0x18 + // Bit mask of DAC_CLK_FORCE_HIGH field. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH_Msk = 0x1000000 + // Bit DAC_CLK_FORCE_HIGH. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH = 0x1000000 + // Position of DAC_CLK_INV field. + SENS_SAR_DAC_CTRL1_DAC_CLK_INV_Pos = 0x19 + // Bit mask of DAC_CLK_INV field. + SENS_SAR_DAC_CTRL1_DAC_CLK_INV_Msk = 0x2000000 + // Bit DAC_CLK_INV. + SENS_SAR_DAC_CTRL1_DAC_CLK_INV = 0x2000000 + + // SAR_DAC_CTRL2 + // Position of DAC_DC1 field. + SENS_SAR_DAC_CTRL2_DAC_DC1_Pos = 0x0 + // Bit mask of DAC_DC1 field. + SENS_SAR_DAC_CTRL2_DAC_DC1_Msk = 0xff + // Position of DAC_DC2 field. + SENS_SAR_DAC_CTRL2_DAC_DC2_Pos = 0x8 + // Bit mask of DAC_DC2 field. + SENS_SAR_DAC_CTRL2_DAC_DC2_Msk = 0xff00 + // Position of DAC_SCALE1 field. + SENS_SAR_DAC_CTRL2_DAC_SCALE1_Pos = 0x10 + // Bit mask of DAC_SCALE1 field. + SENS_SAR_DAC_CTRL2_DAC_SCALE1_Msk = 0x30000 + // Position of DAC_SCALE2 field. + SENS_SAR_DAC_CTRL2_DAC_SCALE2_Pos = 0x12 + // Bit mask of DAC_SCALE2 field. + SENS_SAR_DAC_CTRL2_DAC_SCALE2_Msk = 0xc0000 + // Position of DAC_INV1 field. + SENS_SAR_DAC_CTRL2_DAC_INV1_Pos = 0x14 + // Bit mask of DAC_INV1 field. + SENS_SAR_DAC_CTRL2_DAC_INV1_Msk = 0x300000 + // Position of DAC_INV2 field. + SENS_SAR_DAC_CTRL2_DAC_INV2_Pos = 0x16 + // Bit mask of DAC_INV2 field. + SENS_SAR_DAC_CTRL2_DAC_INV2_Msk = 0xc00000 + // Position of DAC_CW_EN1 field. + SENS_SAR_DAC_CTRL2_DAC_CW_EN1_Pos = 0x18 + // Bit mask of DAC_CW_EN1 field. + SENS_SAR_DAC_CTRL2_DAC_CW_EN1_Msk = 0x1000000 + // Bit DAC_CW_EN1. + SENS_SAR_DAC_CTRL2_DAC_CW_EN1 = 0x1000000 + // Position of DAC_CW_EN2 field. + SENS_SAR_DAC_CTRL2_DAC_CW_EN2_Pos = 0x19 + // Bit mask of DAC_CW_EN2 field. + SENS_SAR_DAC_CTRL2_DAC_CW_EN2_Msk = 0x2000000 + // Bit DAC_CW_EN2. + SENS_SAR_DAC_CTRL2_DAC_CW_EN2 = 0x2000000 + + // SAR_MEAS_CTRL2 + // Position of SAR1_DAC_XPD_FSM field. + SENS_SAR_MEAS_CTRL2_SAR1_DAC_XPD_FSM_Pos = 0x0 + // Bit mask of SAR1_DAC_XPD_FSM field. + SENS_SAR_MEAS_CTRL2_SAR1_DAC_XPD_FSM_Msk = 0xf + // Position of SAR1_DAC_XPD_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_SAR1_DAC_XPD_FSM_IDLE_Pos = 0x4 + // Bit mask of SAR1_DAC_XPD_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_SAR1_DAC_XPD_FSM_IDLE_Msk = 0x10 + // Bit SAR1_DAC_XPD_FSM_IDLE. + SENS_SAR_MEAS_CTRL2_SAR1_DAC_XPD_FSM_IDLE = 0x10 + // Position of XPD_SAR_AMP_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_XPD_SAR_AMP_FSM_IDLE_Pos = 0x5 + // Bit mask of XPD_SAR_AMP_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_XPD_SAR_AMP_FSM_IDLE_Msk = 0x20 + // Bit XPD_SAR_AMP_FSM_IDLE. + SENS_SAR_MEAS_CTRL2_XPD_SAR_AMP_FSM_IDLE = 0x20 + // Position of AMP_RST_FB_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_AMP_RST_FB_FSM_IDLE_Pos = 0x6 + // Bit mask of AMP_RST_FB_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_AMP_RST_FB_FSM_IDLE_Msk = 0x40 + // Bit AMP_RST_FB_FSM_IDLE. + SENS_SAR_MEAS_CTRL2_AMP_RST_FB_FSM_IDLE = 0x40 + // Position of AMP_SHORT_REF_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_FSM_IDLE_Pos = 0x7 + // Bit mask of AMP_SHORT_REF_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_FSM_IDLE_Msk = 0x80 + // Bit AMP_SHORT_REF_FSM_IDLE. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_FSM_IDLE = 0x80 + // Position of AMP_SHORT_REF_GND_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE_Pos = 0x8 + // Bit mask of AMP_SHORT_REF_GND_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE_Msk = 0x100 + // Bit AMP_SHORT_REF_GND_FSM_IDLE. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE = 0x100 + // Position of XPD_SAR_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_XPD_SAR_FSM_IDLE_Pos = 0x9 + // Bit mask of XPD_SAR_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_XPD_SAR_FSM_IDLE_Msk = 0x200 + // Bit XPD_SAR_FSM_IDLE. + SENS_SAR_MEAS_CTRL2_XPD_SAR_FSM_IDLE = 0x200 + // Position of SAR_RSTB_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_SAR_RSTB_FSM_IDLE_Pos = 0xa + // Bit mask of SAR_RSTB_FSM_IDLE field. + SENS_SAR_MEAS_CTRL2_SAR_RSTB_FSM_IDLE_Msk = 0x400 + // Bit SAR_RSTB_FSM_IDLE. + SENS_SAR_MEAS_CTRL2_SAR_RSTB_FSM_IDLE = 0x400 + // Position of SAR2_RSTB_FORCE field. + SENS_SAR_MEAS_CTRL2_SAR2_RSTB_FORCE_Pos = 0xb + // Bit mask of SAR2_RSTB_FORCE field. + SENS_SAR_MEAS_CTRL2_SAR2_RSTB_FORCE_Msk = 0x1800 + // Position of AMP_RST_FB_FORCE field. + SENS_SAR_MEAS_CTRL2_AMP_RST_FB_FORCE_Pos = 0xd + // Bit mask of AMP_RST_FB_FORCE field. + SENS_SAR_MEAS_CTRL2_AMP_RST_FB_FORCE_Msk = 0x6000 + // Position of AMP_SHORT_REF_FORCE field. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_FORCE_Pos = 0xf + // Bit mask of AMP_SHORT_REF_FORCE field. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_FORCE_Msk = 0x18000 + // Position of AMP_SHORT_REF_GND_FORCE field. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_GND_FORCE_Pos = 0x11 + // Bit mask of AMP_SHORT_REF_GND_FORCE field. + SENS_SAR_MEAS_CTRL2_AMP_SHORT_REF_GND_FORCE_Msk = 0x60000 + + // SAR_NOUSE + // Position of SAR_NOUSE field. + SENS_SAR_NOUSE_SAR_NOUSE_Pos = 0x0 + // Bit mask of SAR_NOUSE field. + SENS_SAR_NOUSE_SAR_NOUSE_Msk = 0xffffffff + + // SARDATE + // Position of SAR_DATE field. + SENS_SARDATE_SAR_DATE_Pos = 0x0 + // Bit mask of SAR_DATE field. + SENS_SARDATE_SAR_DATE_Msk = 0xfffffff +) + +// Constants for SHA: SHA (Secure Hash Algorithm) Accelerator +const ( + // TEXT0 + // Position of TEXT field. + SHA_TEXT_TEXT_Pos = 0x0 + // Bit mask of TEXT field. + SHA_TEXT_TEXT_Msk = 0xffffffff + + // SHA1_START + // Position of SHA1_START field. + SHA_SHA1_START_SHA1_START_Pos = 0x0 + // Bit mask of SHA1_START field. + SHA_SHA1_START_SHA1_START_Msk = 0x1 + // Bit SHA1_START. + SHA_SHA1_START_SHA1_START = 0x1 + + // SHA1_CONTINUE + // Position of SHA1_CONTINUE field. + SHA_SHA1_CONTINUE_SHA1_CONTINUE_Pos = 0x0 + // Bit mask of SHA1_CONTINUE field. + SHA_SHA1_CONTINUE_SHA1_CONTINUE_Msk = 0x1 + // Bit SHA1_CONTINUE. + SHA_SHA1_CONTINUE_SHA1_CONTINUE = 0x1 + + // SHA1_LOAD + // Position of SHA1_LOAD field. + SHA_SHA1_LOAD_SHA1_LOAD_Pos = 0x0 + // Bit mask of SHA1_LOAD field. + SHA_SHA1_LOAD_SHA1_LOAD_Msk = 0x1 + // Bit SHA1_LOAD. + SHA_SHA1_LOAD_SHA1_LOAD = 0x1 + + // SHA1_BUSY + // Position of SHA1_BUSY field. + SHA_SHA1_BUSY_SHA1_BUSY_Pos = 0x0 + // Bit mask of SHA1_BUSY field. + SHA_SHA1_BUSY_SHA1_BUSY_Msk = 0x1 + // Bit SHA1_BUSY. + SHA_SHA1_BUSY_SHA1_BUSY = 0x1 + + // SHA256_START + // Position of SHA256_START field. + SHA_SHA256_START_SHA256_START_Pos = 0x0 + // Bit mask of SHA256_START field. + SHA_SHA256_START_SHA256_START_Msk = 0x1 + // Bit SHA256_START. + SHA_SHA256_START_SHA256_START = 0x1 + + // SHA256_CONTINUE + // Position of SHA256_CONTINUE field. + SHA_SHA256_CONTINUE_SHA256_CONTINUE_Pos = 0x0 + // Bit mask of SHA256_CONTINUE field. + SHA_SHA256_CONTINUE_SHA256_CONTINUE_Msk = 0x1 + // Bit SHA256_CONTINUE. + SHA_SHA256_CONTINUE_SHA256_CONTINUE = 0x1 + + // SHA256_LOAD + // Position of SHA256_LOAD field. + SHA_SHA256_LOAD_SHA256_LOAD_Pos = 0x0 + // Bit mask of SHA256_LOAD field. + SHA_SHA256_LOAD_SHA256_LOAD_Msk = 0x1 + // Bit SHA256_LOAD. + SHA_SHA256_LOAD_SHA256_LOAD = 0x1 + + // SHA256_BUSY + // Position of SHA256_BUSY field. + SHA_SHA256_BUSY_SHA256_BUSY_Pos = 0x0 + // Bit mask of SHA256_BUSY field. + SHA_SHA256_BUSY_SHA256_BUSY_Msk = 0x1 + // Bit SHA256_BUSY. + SHA_SHA256_BUSY_SHA256_BUSY = 0x1 + + // SHA384_START + // Position of SHA384_START field. + SHA_SHA384_START_SHA384_START_Pos = 0x0 + // Bit mask of SHA384_START field. + SHA_SHA384_START_SHA384_START_Msk = 0x1 + // Bit SHA384_START. + SHA_SHA384_START_SHA384_START = 0x1 + + // SHA384_CONTINUE + // Position of SHA384_CONTINUE field. + SHA_SHA384_CONTINUE_SHA384_CONTINUE_Pos = 0x0 + // Bit mask of SHA384_CONTINUE field. + SHA_SHA384_CONTINUE_SHA384_CONTINUE_Msk = 0x1 + // Bit SHA384_CONTINUE. + SHA_SHA384_CONTINUE_SHA384_CONTINUE = 0x1 + + // SHA384_LOAD + // Position of SHA384_LOAD field. + SHA_SHA384_LOAD_SHA384_LOAD_Pos = 0x0 + // Bit mask of SHA384_LOAD field. + SHA_SHA384_LOAD_SHA384_LOAD_Msk = 0x1 + // Bit SHA384_LOAD. + SHA_SHA384_LOAD_SHA384_LOAD = 0x1 + + // SHA384_BUSY + // Position of SHA384_BUSY field. + SHA_SHA384_BUSY_SHA384_BUSY_Pos = 0x0 + // Bit mask of SHA384_BUSY field. + SHA_SHA384_BUSY_SHA384_BUSY_Msk = 0x1 + // Bit SHA384_BUSY. + SHA_SHA384_BUSY_SHA384_BUSY = 0x1 + + // SHA512_START + // Position of SHA512_START field. + SHA_SHA512_START_SHA512_START_Pos = 0x0 + // Bit mask of SHA512_START field. + SHA_SHA512_START_SHA512_START_Msk = 0x1 + // Bit SHA512_START. + SHA_SHA512_START_SHA512_START = 0x1 + + // SHA512_CONTINUE + // Position of SHA512_CONTINUE field. + SHA_SHA512_CONTINUE_SHA512_CONTINUE_Pos = 0x0 + // Bit mask of SHA512_CONTINUE field. + SHA_SHA512_CONTINUE_SHA512_CONTINUE_Msk = 0x1 + // Bit SHA512_CONTINUE. + SHA_SHA512_CONTINUE_SHA512_CONTINUE = 0x1 + + // SHA512_LOAD + // Position of SHA512_LOAD field. + SHA_SHA512_LOAD_SHA512_LOAD_Pos = 0x0 + // Bit mask of SHA512_LOAD field. + SHA_SHA512_LOAD_SHA512_LOAD_Msk = 0x1 + // Bit SHA512_LOAD. + SHA_SHA512_LOAD_SHA512_LOAD = 0x1 + + // SHA512_BUSY + // Position of SHA512_BUSY field. + SHA_SHA512_BUSY_SHA512_BUSY_Pos = 0x0 + // Bit mask of SHA512_BUSY field. + SHA_SHA512_BUSY_SHA512_BUSY_Msk = 0x1 + // Bit SHA512_BUSY. + SHA_SHA512_BUSY_SHA512_BUSY = 0x1 +) + +// Constants for SLC: SLC Peripheral +const ( + // CONF0 + // Position of SLC0_TX_RST field. + SLC_CONF0_SLC0_TX_RST_Pos = 0x0 + // Bit mask of SLC0_TX_RST field. + SLC_CONF0_SLC0_TX_RST_Msk = 0x1 + // Bit SLC0_TX_RST. + SLC_CONF0_SLC0_TX_RST = 0x1 + // Position of SLC0_RX_RST field. + SLC_CONF0_SLC0_RX_RST_Pos = 0x1 + // Bit mask of SLC0_RX_RST field. + SLC_CONF0_SLC0_RX_RST_Msk = 0x2 + // Bit SLC0_RX_RST. + SLC_CONF0_SLC0_RX_RST = 0x2 + // Position of AHBM_FIFO_RST field. + SLC_CONF0_AHBM_FIFO_RST_Pos = 0x2 + // Bit mask of AHBM_FIFO_RST field. + SLC_CONF0_AHBM_FIFO_RST_Msk = 0x4 + // Bit AHBM_FIFO_RST. + SLC_CONF0_AHBM_FIFO_RST = 0x4 + // Position of AHBM_RST field. + SLC_CONF0_AHBM_RST_Pos = 0x3 + // Bit mask of AHBM_RST field. + SLC_CONF0_AHBM_RST_Msk = 0x8 + // Bit AHBM_RST. + SLC_CONF0_AHBM_RST = 0x8 + // Position of SLC0_TX_LOOP_TEST field. + SLC_CONF0_SLC0_TX_LOOP_TEST_Pos = 0x4 + // Bit mask of SLC0_TX_LOOP_TEST field. + SLC_CONF0_SLC0_TX_LOOP_TEST_Msk = 0x10 + // Bit SLC0_TX_LOOP_TEST. + SLC_CONF0_SLC0_TX_LOOP_TEST = 0x10 + // Position of SLC0_RX_LOOP_TEST field. + SLC_CONF0_SLC0_RX_LOOP_TEST_Pos = 0x5 + // Bit mask of SLC0_RX_LOOP_TEST field. + SLC_CONF0_SLC0_RX_LOOP_TEST_Msk = 0x20 + // Bit SLC0_RX_LOOP_TEST. + SLC_CONF0_SLC0_RX_LOOP_TEST = 0x20 + // Position of SLC0_RX_AUTO_WRBACK field. + SLC_CONF0_SLC0_RX_AUTO_WRBACK_Pos = 0x6 + // Bit mask of SLC0_RX_AUTO_WRBACK field. + SLC_CONF0_SLC0_RX_AUTO_WRBACK_Msk = 0x40 + // Bit SLC0_RX_AUTO_WRBACK. + SLC_CONF0_SLC0_RX_AUTO_WRBACK = 0x40 + // Position of SLC0_RX_NO_RESTART_CLR field. + SLC_CONF0_SLC0_RX_NO_RESTART_CLR_Pos = 0x7 + // Bit mask of SLC0_RX_NO_RESTART_CLR field. + SLC_CONF0_SLC0_RX_NO_RESTART_CLR_Msk = 0x80 + // Bit SLC0_RX_NO_RESTART_CLR. + SLC_CONF0_SLC0_RX_NO_RESTART_CLR = 0x80 + // Position of SLC0_RXDSCR_BURST_EN field. + SLC_CONF0_SLC0_RXDSCR_BURST_EN_Pos = 0x8 + // Bit mask of SLC0_RXDSCR_BURST_EN field. + SLC_CONF0_SLC0_RXDSCR_BURST_EN_Msk = 0x100 + // Bit SLC0_RXDSCR_BURST_EN. + SLC_CONF0_SLC0_RXDSCR_BURST_EN = 0x100 + // Position of SLC0_RXDATA_BURST_EN field. + SLC_CONF0_SLC0_RXDATA_BURST_EN_Pos = 0x9 + // Bit mask of SLC0_RXDATA_BURST_EN field. + SLC_CONF0_SLC0_RXDATA_BURST_EN_Msk = 0x200 + // Bit SLC0_RXDATA_BURST_EN. + SLC_CONF0_SLC0_RXDATA_BURST_EN = 0x200 + // Position of SLC0_RXLINK_AUTO_RET field. + SLC_CONF0_SLC0_RXLINK_AUTO_RET_Pos = 0xa + // Bit mask of SLC0_RXLINK_AUTO_RET field. + SLC_CONF0_SLC0_RXLINK_AUTO_RET_Msk = 0x400 + // Bit SLC0_RXLINK_AUTO_RET. + SLC_CONF0_SLC0_RXLINK_AUTO_RET = 0x400 + // Position of SLC0_TXLINK_AUTO_RET field. + SLC_CONF0_SLC0_TXLINK_AUTO_RET_Pos = 0xb + // Bit mask of SLC0_TXLINK_AUTO_RET field. + SLC_CONF0_SLC0_TXLINK_AUTO_RET_Msk = 0x800 + // Bit SLC0_TXLINK_AUTO_RET. + SLC_CONF0_SLC0_TXLINK_AUTO_RET = 0x800 + // Position of SLC0_TXDSCR_BURST_EN field. + SLC_CONF0_SLC0_TXDSCR_BURST_EN_Pos = 0xc + // Bit mask of SLC0_TXDSCR_BURST_EN field. + SLC_CONF0_SLC0_TXDSCR_BURST_EN_Msk = 0x1000 + // Bit SLC0_TXDSCR_BURST_EN. + SLC_CONF0_SLC0_TXDSCR_BURST_EN = 0x1000 + // Position of SLC0_TXDATA_BURST_EN field. + SLC_CONF0_SLC0_TXDATA_BURST_EN_Pos = 0xd + // Bit mask of SLC0_TXDATA_BURST_EN field. + SLC_CONF0_SLC0_TXDATA_BURST_EN_Msk = 0x2000 + // Bit SLC0_TXDATA_BURST_EN. + SLC_CONF0_SLC0_TXDATA_BURST_EN = 0x2000 + // Position of SLC0_TOKEN_AUTO_CLR field. + SLC_CONF0_SLC0_TOKEN_AUTO_CLR_Pos = 0xe + // Bit mask of SLC0_TOKEN_AUTO_CLR field. + SLC_CONF0_SLC0_TOKEN_AUTO_CLR_Msk = 0x4000 + // Bit SLC0_TOKEN_AUTO_CLR. + SLC_CONF0_SLC0_TOKEN_AUTO_CLR = 0x4000 + // Position of SLC0_TOKEN_SEL field. + SLC_CONF0_SLC0_TOKEN_SEL_Pos = 0xf + // Bit mask of SLC0_TOKEN_SEL field. + SLC_CONF0_SLC0_TOKEN_SEL_Msk = 0x8000 + // Bit SLC0_TOKEN_SEL. + SLC_CONF0_SLC0_TOKEN_SEL = 0x8000 + // Position of SLC1_TX_RST field. + SLC_CONF0_SLC1_TX_RST_Pos = 0x10 + // Bit mask of SLC1_TX_RST field. + SLC_CONF0_SLC1_TX_RST_Msk = 0x10000 + // Bit SLC1_TX_RST. + SLC_CONF0_SLC1_TX_RST = 0x10000 + // Position of SLC1_RX_RST field. + SLC_CONF0_SLC1_RX_RST_Pos = 0x11 + // Bit mask of SLC1_RX_RST field. + SLC_CONF0_SLC1_RX_RST_Msk = 0x20000 + // Bit SLC1_RX_RST. + SLC_CONF0_SLC1_RX_RST = 0x20000 + // Position of SLC0_WR_RETRY_MASK_EN field. + SLC_CONF0_SLC0_WR_RETRY_MASK_EN_Pos = 0x12 + // Bit mask of SLC0_WR_RETRY_MASK_EN field. + SLC_CONF0_SLC0_WR_RETRY_MASK_EN_Msk = 0x40000 + // Bit SLC0_WR_RETRY_MASK_EN. + SLC_CONF0_SLC0_WR_RETRY_MASK_EN = 0x40000 + // Position of SLC1_WR_RETRY_MASK_EN field. + SLC_CONF0_SLC1_WR_RETRY_MASK_EN_Pos = 0x13 + // Bit mask of SLC1_WR_RETRY_MASK_EN field. + SLC_CONF0_SLC1_WR_RETRY_MASK_EN_Msk = 0x80000 + // Bit SLC1_WR_RETRY_MASK_EN. + SLC_CONF0_SLC1_WR_RETRY_MASK_EN = 0x80000 + // Position of SLC1_TX_LOOP_TEST field. + SLC_CONF0_SLC1_TX_LOOP_TEST_Pos = 0x14 + // Bit mask of SLC1_TX_LOOP_TEST field. + SLC_CONF0_SLC1_TX_LOOP_TEST_Msk = 0x100000 + // Bit SLC1_TX_LOOP_TEST. + SLC_CONF0_SLC1_TX_LOOP_TEST = 0x100000 + // Position of SLC1_RX_LOOP_TEST field. + SLC_CONF0_SLC1_RX_LOOP_TEST_Pos = 0x15 + // Bit mask of SLC1_RX_LOOP_TEST field. + SLC_CONF0_SLC1_RX_LOOP_TEST_Msk = 0x200000 + // Bit SLC1_RX_LOOP_TEST. + SLC_CONF0_SLC1_RX_LOOP_TEST = 0x200000 + // Position of SLC1_RX_AUTO_WRBACK field. + SLC_CONF0_SLC1_RX_AUTO_WRBACK_Pos = 0x16 + // Bit mask of SLC1_RX_AUTO_WRBACK field. + SLC_CONF0_SLC1_RX_AUTO_WRBACK_Msk = 0x400000 + // Bit SLC1_RX_AUTO_WRBACK. + SLC_CONF0_SLC1_RX_AUTO_WRBACK = 0x400000 + // Position of SLC1_RX_NO_RESTART_CLR field. + SLC_CONF0_SLC1_RX_NO_RESTART_CLR_Pos = 0x17 + // Bit mask of SLC1_RX_NO_RESTART_CLR field. + SLC_CONF0_SLC1_RX_NO_RESTART_CLR_Msk = 0x800000 + // Bit SLC1_RX_NO_RESTART_CLR. + SLC_CONF0_SLC1_RX_NO_RESTART_CLR = 0x800000 + // Position of SLC1_RXDSCR_BURST_EN field. + SLC_CONF0_SLC1_RXDSCR_BURST_EN_Pos = 0x18 + // Bit mask of SLC1_RXDSCR_BURST_EN field. + SLC_CONF0_SLC1_RXDSCR_BURST_EN_Msk = 0x1000000 + // Bit SLC1_RXDSCR_BURST_EN. + SLC_CONF0_SLC1_RXDSCR_BURST_EN = 0x1000000 + // Position of SLC1_RXDATA_BURST_EN field. + SLC_CONF0_SLC1_RXDATA_BURST_EN_Pos = 0x19 + // Bit mask of SLC1_RXDATA_BURST_EN field. + SLC_CONF0_SLC1_RXDATA_BURST_EN_Msk = 0x2000000 + // Bit SLC1_RXDATA_BURST_EN. + SLC_CONF0_SLC1_RXDATA_BURST_EN = 0x2000000 + // Position of SLC1_RXLINK_AUTO_RET field. + SLC_CONF0_SLC1_RXLINK_AUTO_RET_Pos = 0x1a + // Bit mask of SLC1_RXLINK_AUTO_RET field. + SLC_CONF0_SLC1_RXLINK_AUTO_RET_Msk = 0x4000000 + // Bit SLC1_RXLINK_AUTO_RET. + SLC_CONF0_SLC1_RXLINK_AUTO_RET = 0x4000000 + // Position of SLC1_TXLINK_AUTO_RET field. + SLC_CONF0_SLC1_TXLINK_AUTO_RET_Pos = 0x1b + // Bit mask of SLC1_TXLINK_AUTO_RET field. + SLC_CONF0_SLC1_TXLINK_AUTO_RET_Msk = 0x8000000 + // Bit SLC1_TXLINK_AUTO_RET. + SLC_CONF0_SLC1_TXLINK_AUTO_RET = 0x8000000 + // Position of SLC1_TXDSCR_BURST_EN field. + SLC_CONF0_SLC1_TXDSCR_BURST_EN_Pos = 0x1c + // Bit mask of SLC1_TXDSCR_BURST_EN field. + SLC_CONF0_SLC1_TXDSCR_BURST_EN_Msk = 0x10000000 + // Bit SLC1_TXDSCR_BURST_EN. + SLC_CONF0_SLC1_TXDSCR_BURST_EN = 0x10000000 + // Position of SLC1_TXDATA_BURST_EN field. + SLC_CONF0_SLC1_TXDATA_BURST_EN_Pos = 0x1d + // Bit mask of SLC1_TXDATA_BURST_EN field. + SLC_CONF0_SLC1_TXDATA_BURST_EN_Msk = 0x20000000 + // Bit SLC1_TXDATA_BURST_EN. + SLC_CONF0_SLC1_TXDATA_BURST_EN = 0x20000000 + // Position of SLC1_TOKEN_AUTO_CLR field. + SLC_CONF0_SLC1_TOKEN_AUTO_CLR_Pos = 0x1e + // Bit mask of SLC1_TOKEN_AUTO_CLR field. + SLC_CONF0_SLC1_TOKEN_AUTO_CLR_Msk = 0x40000000 + // Bit SLC1_TOKEN_AUTO_CLR. + SLC_CONF0_SLC1_TOKEN_AUTO_CLR = 0x40000000 + // Position of SLC1_TOKEN_SEL field. + SLC_CONF0_SLC1_TOKEN_SEL_Pos = 0x1f + // Bit mask of SLC1_TOKEN_SEL field. + SLC_CONF0_SLC1_TOKEN_SEL_Msk = 0x80000000 + // Bit SLC1_TOKEN_SEL. + SLC_CONF0_SLC1_TOKEN_SEL = 0x80000000 + + // _0INT_RAW + // Position of FRHOST_BIT0_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT0_INT_RAW_Pos = 0x0 + // Bit mask of FRHOST_BIT0_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT0_INT_RAW_Msk = 0x1 + // Bit FRHOST_BIT0_INT_RAW. + SLC__0INT_RAW_FRHOST_BIT0_INT_RAW = 0x1 + // Position of FRHOST_BIT1_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT1_INT_RAW_Pos = 0x1 + // Bit mask of FRHOST_BIT1_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT1_INT_RAW_Msk = 0x2 + // Bit FRHOST_BIT1_INT_RAW. + SLC__0INT_RAW_FRHOST_BIT1_INT_RAW = 0x2 + // Position of FRHOST_BIT2_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT2_INT_RAW_Pos = 0x2 + // Bit mask of FRHOST_BIT2_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT2_INT_RAW_Msk = 0x4 + // Bit FRHOST_BIT2_INT_RAW. + SLC__0INT_RAW_FRHOST_BIT2_INT_RAW = 0x4 + // Position of FRHOST_BIT3_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT3_INT_RAW_Pos = 0x3 + // Bit mask of FRHOST_BIT3_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT3_INT_RAW_Msk = 0x8 + // Bit FRHOST_BIT3_INT_RAW. + SLC__0INT_RAW_FRHOST_BIT3_INT_RAW = 0x8 + // Position of FRHOST_BIT4_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT4_INT_RAW_Pos = 0x4 + // Bit mask of FRHOST_BIT4_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT4_INT_RAW_Msk = 0x10 + // Bit FRHOST_BIT4_INT_RAW. + SLC__0INT_RAW_FRHOST_BIT4_INT_RAW = 0x10 + // Position of FRHOST_BIT5_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT5_INT_RAW_Pos = 0x5 + // Bit mask of FRHOST_BIT5_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT5_INT_RAW_Msk = 0x20 + // Bit FRHOST_BIT5_INT_RAW. + SLC__0INT_RAW_FRHOST_BIT5_INT_RAW = 0x20 + // Position of FRHOST_BIT6_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT6_INT_RAW_Pos = 0x6 + // Bit mask of FRHOST_BIT6_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT6_INT_RAW_Msk = 0x40 + // Bit FRHOST_BIT6_INT_RAW. + SLC__0INT_RAW_FRHOST_BIT6_INT_RAW = 0x40 + // Position of FRHOST_BIT7_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT7_INT_RAW_Pos = 0x7 + // Bit mask of FRHOST_BIT7_INT_RAW field. + SLC__0INT_RAW_FRHOST_BIT7_INT_RAW_Msk = 0x80 + // Bit FRHOST_BIT7_INT_RAW. + SLC__0INT_RAW_FRHOST_BIT7_INT_RAW = 0x80 + // Position of SLC0_RX_START_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_START_INT_RAW_Pos = 0x8 + // Bit mask of SLC0_RX_START_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_START_INT_RAW_Msk = 0x100 + // Bit SLC0_RX_START_INT_RAW. + SLC__0INT_RAW_SLC0_RX_START_INT_RAW = 0x100 + // Position of SLC0_TX_START_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_START_INT_RAW_Pos = 0x9 + // Bit mask of SLC0_TX_START_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_START_INT_RAW_Msk = 0x200 + // Bit SLC0_TX_START_INT_RAW. + SLC__0INT_RAW_SLC0_TX_START_INT_RAW = 0x200 + // Position of SLC0_RX_UDF_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_UDF_INT_RAW_Pos = 0xa + // Bit mask of SLC0_RX_UDF_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_UDF_INT_RAW_Msk = 0x400 + // Bit SLC0_RX_UDF_INT_RAW. + SLC__0INT_RAW_SLC0_RX_UDF_INT_RAW = 0x400 + // Position of SLC0_TX_OVF_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_OVF_INT_RAW_Pos = 0xb + // Bit mask of SLC0_TX_OVF_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_OVF_INT_RAW_Msk = 0x800 + // Bit SLC0_TX_OVF_INT_RAW. + SLC__0INT_RAW_SLC0_TX_OVF_INT_RAW = 0x800 + // Position of SLC0_TOKEN0_1TO0_INT_RAW field. + SLC__0INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW_Pos = 0xc + // Bit mask of SLC0_TOKEN0_1TO0_INT_RAW field. + SLC__0INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW_Msk = 0x1000 + // Bit SLC0_TOKEN0_1TO0_INT_RAW. + SLC__0INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW = 0x1000 + // Position of SLC0_TOKEN1_1TO0_INT_RAW field. + SLC__0INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW_Pos = 0xd + // Bit mask of SLC0_TOKEN1_1TO0_INT_RAW field. + SLC__0INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW_Msk = 0x2000 + // Bit SLC0_TOKEN1_1TO0_INT_RAW. + SLC__0INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW = 0x2000 + // Position of SLC0_TX_DONE_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of SLC0_TX_DONE_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit SLC0_TX_DONE_INT_RAW. + SLC__0INT_RAW_SLC0_TX_DONE_INT_RAW = 0x4000 + // Position of SLC0_TX_SUC_EOF_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_SUC_EOF_INT_RAW_Pos = 0xf + // Bit mask of SLC0_TX_SUC_EOF_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_SUC_EOF_INT_RAW_Msk = 0x8000 + // Bit SLC0_TX_SUC_EOF_INT_RAW. + SLC__0INT_RAW_SLC0_TX_SUC_EOF_INT_RAW = 0x8000 + // Position of SLC0_RX_DONE_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_DONE_INT_RAW_Pos = 0x10 + // Bit mask of SLC0_RX_DONE_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_DONE_INT_RAW_Msk = 0x10000 + // Bit SLC0_RX_DONE_INT_RAW. + SLC__0INT_RAW_SLC0_RX_DONE_INT_RAW = 0x10000 + // Position of SLC0_RX_EOF_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_EOF_INT_RAW_Pos = 0x11 + // Bit mask of SLC0_RX_EOF_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_EOF_INT_RAW_Msk = 0x20000 + // Bit SLC0_RX_EOF_INT_RAW. + SLC__0INT_RAW_SLC0_RX_EOF_INT_RAW = 0x20000 + // Position of SLC0_TOHOST_INT_RAW field. + SLC__0INT_RAW_SLC0_TOHOST_INT_RAW_Pos = 0x12 + // Bit mask of SLC0_TOHOST_INT_RAW field. + SLC__0INT_RAW_SLC0_TOHOST_INT_RAW_Msk = 0x40000 + // Bit SLC0_TOHOST_INT_RAW. + SLC__0INT_RAW_SLC0_TOHOST_INT_RAW = 0x40000 + // Position of SLC0_TX_DSCR_ERR_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_DSCR_ERR_INT_RAW_Pos = 0x13 + // Bit mask of SLC0_TX_DSCR_ERR_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_DSCR_ERR_INT_RAW_Msk = 0x80000 + // Bit SLC0_TX_DSCR_ERR_INT_RAW. + SLC__0INT_RAW_SLC0_TX_DSCR_ERR_INT_RAW = 0x80000 + // Position of SLC0_RX_DSCR_ERR_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_DSCR_ERR_INT_RAW_Pos = 0x14 + // Bit mask of SLC0_RX_DSCR_ERR_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_DSCR_ERR_INT_RAW_Msk = 0x100000 + // Bit SLC0_RX_DSCR_ERR_INT_RAW. + SLC__0INT_RAW_SLC0_RX_DSCR_ERR_INT_RAW = 0x100000 + // Position of SLC0_TX_DSCR_EMPTY_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_DSCR_EMPTY_INT_RAW_Pos = 0x15 + // Bit mask of SLC0_TX_DSCR_EMPTY_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_DSCR_EMPTY_INT_RAW_Msk = 0x200000 + // Bit SLC0_TX_DSCR_EMPTY_INT_RAW. + SLC__0INT_RAW_SLC0_TX_DSCR_EMPTY_INT_RAW = 0x200000 + // Position of SLC0_HOST_RD_ACK_INT_RAW field. + SLC__0INT_RAW_SLC0_HOST_RD_ACK_INT_RAW_Pos = 0x16 + // Bit mask of SLC0_HOST_RD_ACK_INT_RAW field. + SLC__0INT_RAW_SLC0_HOST_RD_ACK_INT_RAW_Msk = 0x400000 + // Bit SLC0_HOST_RD_ACK_INT_RAW. + SLC__0INT_RAW_SLC0_HOST_RD_ACK_INT_RAW = 0x400000 + // Position of SLC0_WR_RETRY_DONE_INT_RAW field. + SLC__0INT_RAW_SLC0_WR_RETRY_DONE_INT_RAW_Pos = 0x17 + // Bit mask of SLC0_WR_RETRY_DONE_INT_RAW field. + SLC__0INT_RAW_SLC0_WR_RETRY_DONE_INT_RAW_Msk = 0x800000 + // Bit SLC0_WR_RETRY_DONE_INT_RAW. + SLC__0INT_RAW_SLC0_WR_RETRY_DONE_INT_RAW = 0x800000 + // Position of SLC0_TX_ERR_EOF_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_ERR_EOF_INT_RAW_Pos = 0x18 + // Bit mask of SLC0_TX_ERR_EOF_INT_RAW field. + SLC__0INT_RAW_SLC0_TX_ERR_EOF_INT_RAW_Msk = 0x1000000 + // Bit SLC0_TX_ERR_EOF_INT_RAW. + SLC__0INT_RAW_SLC0_TX_ERR_EOF_INT_RAW = 0x1000000 + // Position of CMD_DTC_INT_RAW field. + SLC__0INT_RAW_CMD_DTC_INT_RAW_Pos = 0x19 + // Bit mask of CMD_DTC_INT_RAW field. + SLC__0INT_RAW_CMD_DTC_INT_RAW_Msk = 0x2000000 + // Bit CMD_DTC_INT_RAW. + SLC__0INT_RAW_CMD_DTC_INT_RAW = 0x2000000 + // Position of SLC0_RX_QUICK_EOF_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_QUICK_EOF_INT_RAW_Pos = 0x1a + // Bit mask of SLC0_RX_QUICK_EOF_INT_RAW field. + SLC__0INT_RAW_SLC0_RX_QUICK_EOF_INT_RAW_Msk = 0x4000000 + // Bit SLC0_RX_QUICK_EOF_INT_RAW. + SLC__0INT_RAW_SLC0_RX_QUICK_EOF_INT_RAW = 0x4000000 + + // _0INT_ST + // Position of FRHOST_BIT0_INT_ST field. + SLC__0INT_ST_FRHOST_BIT0_INT_ST_Pos = 0x0 + // Bit mask of FRHOST_BIT0_INT_ST field. + SLC__0INT_ST_FRHOST_BIT0_INT_ST_Msk = 0x1 + // Bit FRHOST_BIT0_INT_ST. + SLC__0INT_ST_FRHOST_BIT0_INT_ST = 0x1 + // Position of FRHOST_BIT1_INT_ST field. + SLC__0INT_ST_FRHOST_BIT1_INT_ST_Pos = 0x1 + // Bit mask of FRHOST_BIT1_INT_ST field. + SLC__0INT_ST_FRHOST_BIT1_INT_ST_Msk = 0x2 + // Bit FRHOST_BIT1_INT_ST. + SLC__0INT_ST_FRHOST_BIT1_INT_ST = 0x2 + // Position of FRHOST_BIT2_INT_ST field. + SLC__0INT_ST_FRHOST_BIT2_INT_ST_Pos = 0x2 + // Bit mask of FRHOST_BIT2_INT_ST field. + SLC__0INT_ST_FRHOST_BIT2_INT_ST_Msk = 0x4 + // Bit FRHOST_BIT2_INT_ST. + SLC__0INT_ST_FRHOST_BIT2_INT_ST = 0x4 + // Position of FRHOST_BIT3_INT_ST field. + SLC__0INT_ST_FRHOST_BIT3_INT_ST_Pos = 0x3 + // Bit mask of FRHOST_BIT3_INT_ST field. + SLC__0INT_ST_FRHOST_BIT3_INT_ST_Msk = 0x8 + // Bit FRHOST_BIT3_INT_ST. + SLC__0INT_ST_FRHOST_BIT3_INT_ST = 0x8 + // Position of FRHOST_BIT4_INT_ST field. + SLC__0INT_ST_FRHOST_BIT4_INT_ST_Pos = 0x4 + // Bit mask of FRHOST_BIT4_INT_ST field. + SLC__0INT_ST_FRHOST_BIT4_INT_ST_Msk = 0x10 + // Bit FRHOST_BIT4_INT_ST. + SLC__0INT_ST_FRHOST_BIT4_INT_ST = 0x10 + // Position of FRHOST_BIT5_INT_ST field. + SLC__0INT_ST_FRHOST_BIT5_INT_ST_Pos = 0x5 + // Bit mask of FRHOST_BIT5_INT_ST field. + SLC__0INT_ST_FRHOST_BIT5_INT_ST_Msk = 0x20 + // Bit FRHOST_BIT5_INT_ST. + SLC__0INT_ST_FRHOST_BIT5_INT_ST = 0x20 + // Position of FRHOST_BIT6_INT_ST field. + SLC__0INT_ST_FRHOST_BIT6_INT_ST_Pos = 0x6 + // Bit mask of FRHOST_BIT6_INT_ST field. + SLC__0INT_ST_FRHOST_BIT6_INT_ST_Msk = 0x40 + // Bit FRHOST_BIT6_INT_ST. + SLC__0INT_ST_FRHOST_BIT6_INT_ST = 0x40 + // Position of FRHOST_BIT7_INT_ST field. + SLC__0INT_ST_FRHOST_BIT7_INT_ST_Pos = 0x7 + // Bit mask of FRHOST_BIT7_INT_ST field. + SLC__0INT_ST_FRHOST_BIT7_INT_ST_Msk = 0x80 + // Bit FRHOST_BIT7_INT_ST. + SLC__0INT_ST_FRHOST_BIT7_INT_ST = 0x80 + // Position of SLC0_RX_START_INT_ST field. + SLC__0INT_ST_SLC0_RX_START_INT_ST_Pos = 0x8 + // Bit mask of SLC0_RX_START_INT_ST field. + SLC__0INT_ST_SLC0_RX_START_INT_ST_Msk = 0x100 + // Bit SLC0_RX_START_INT_ST. + SLC__0INT_ST_SLC0_RX_START_INT_ST = 0x100 + // Position of SLC0_TX_START_INT_ST field. + SLC__0INT_ST_SLC0_TX_START_INT_ST_Pos = 0x9 + // Bit mask of SLC0_TX_START_INT_ST field. + SLC__0INT_ST_SLC0_TX_START_INT_ST_Msk = 0x200 + // Bit SLC0_TX_START_INT_ST. + SLC__0INT_ST_SLC0_TX_START_INT_ST = 0x200 + // Position of SLC0_RX_UDF_INT_ST field. + SLC__0INT_ST_SLC0_RX_UDF_INT_ST_Pos = 0xa + // Bit mask of SLC0_RX_UDF_INT_ST field. + SLC__0INT_ST_SLC0_RX_UDF_INT_ST_Msk = 0x400 + // Bit SLC0_RX_UDF_INT_ST. + SLC__0INT_ST_SLC0_RX_UDF_INT_ST = 0x400 + // Position of SLC0_TX_OVF_INT_ST field. + SLC__0INT_ST_SLC0_TX_OVF_INT_ST_Pos = 0xb + // Bit mask of SLC0_TX_OVF_INT_ST field. + SLC__0INT_ST_SLC0_TX_OVF_INT_ST_Msk = 0x800 + // Bit SLC0_TX_OVF_INT_ST. + SLC__0INT_ST_SLC0_TX_OVF_INT_ST = 0x800 + // Position of SLC0_TOKEN0_1TO0_INT_ST field. + SLC__0INT_ST_SLC0_TOKEN0_1TO0_INT_ST_Pos = 0xc + // Bit mask of SLC0_TOKEN0_1TO0_INT_ST field. + SLC__0INT_ST_SLC0_TOKEN0_1TO0_INT_ST_Msk = 0x1000 + // Bit SLC0_TOKEN0_1TO0_INT_ST. + SLC__0INT_ST_SLC0_TOKEN0_1TO0_INT_ST = 0x1000 + // Position of SLC0_TOKEN1_1TO0_INT_ST field. + SLC__0INT_ST_SLC0_TOKEN1_1TO0_INT_ST_Pos = 0xd + // Bit mask of SLC0_TOKEN1_1TO0_INT_ST field. + SLC__0INT_ST_SLC0_TOKEN1_1TO0_INT_ST_Msk = 0x2000 + // Bit SLC0_TOKEN1_1TO0_INT_ST. + SLC__0INT_ST_SLC0_TOKEN1_1TO0_INT_ST = 0x2000 + // Position of SLC0_TX_DONE_INT_ST field. + SLC__0INT_ST_SLC0_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of SLC0_TX_DONE_INT_ST field. + SLC__0INT_ST_SLC0_TX_DONE_INT_ST_Msk = 0x4000 + // Bit SLC0_TX_DONE_INT_ST. + SLC__0INT_ST_SLC0_TX_DONE_INT_ST = 0x4000 + // Position of SLC0_TX_SUC_EOF_INT_ST field. + SLC__0INT_ST_SLC0_TX_SUC_EOF_INT_ST_Pos = 0xf + // Bit mask of SLC0_TX_SUC_EOF_INT_ST field. + SLC__0INT_ST_SLC0_TX_SUC_EOF_INT_ST_Msk = 0x8000 + // Bit SLC0_TX_SUC_EOF_INT_ST. + SLC__0INT_ST_SLC0_TX_SUC_EOF_INT_ST = 0x8000 + // Position of SLC0_RX_DONE_INT_ST field. + SLC__0INT_ST_SLC0_RX_DONE_INT_ST_Pos = 0x10 + // Bit mask of SLC0_RX_DONE_INT_ST field. + SLC__0INT_ST_SLC0_RX_DONE_INT_ST_Msk = 0x10000 + // Bit SLC0_RX_DONE_INT_ST. + SLC__0INT_ST_SLC0_RX_DONE_INT_ST = 0x10000 + // Position of SLC0_RX_EOF_INT_ST field. + SLC__0INT_ST_SLC0_RX_EOF_INT_ST_Pos = 0x11 + // Bit mask of SLC0_RX_EOF_INT_ST field. + SLC__0INT_ST_SLC0_RX_EOF_INT_ST_Msk = 0x20000 + // Bit SLC0_RX_EOF_INT_ST. + SLC__0INT_ST_SLC0_RX_EOF_INT_ST = 0x20000 + // Position of SLC0_TOHOST_INT_ST field. + SLC__0INT_ST_SLC0_TOHOST_INT_ST_Pos = 0x12 + // Bit mask of SLC0_TOHOST_INT_ST field. + SLC__0INT_ST_SLC0_TOHOST_INT_ST_Msk = 0x40000 + // Bit SLC0_TOHOST_INT_ST. + SLC__0INT_ST_SLC0_TOHOST_INT_ST = 0x40000 + // Position of SLC0_TX_DSCR_ERR_INT_ST field. + SLC__0INT_ST_SLC0_TX_DSCR_ERR_INT_ST_Pos = 0x13 + // Bit mask of SLC0_TX_DSCR_ERR_INT_ST field. + SLC__0INT_ST_SLC0_TX_DSCR_ERR_INT_ST_Msk = 0x80000 + // Bit SLC0_TX_DSCR_ERR_INT_ST. + SLC__0INT_ST_SLC0_TX_DSCR_ERR_INT_ST = 0x80000 + // Position of SLC0_RX_DSCR_ERR_INT_ST field. + SLC__0INT_ST_SLC0_RX_DSCR_ERR_INT_ST_Pos = 0x14 + // Bit mask of SLC0_RX_DSCR_ERR_INT_ST field. + SLC__0INT_ST_SLC0_RX_DSCR_ERR_INT_ST_Msk = 0x100000 + // Bit SLC0_RX_DSCR_ERR_INT_ST. + SLC__0INT_ST_SLC0_RX_DSCR_ERR_INT_ST = 0x100000 + // Position of SLC0_TX_DSCR_EMPTY_INT_ST field. + SLC__0INT_ST_SLC0_TX_DSCR_EMPTY_INT_ST_Pos = 0x15 + // Bit mask of SLC0_TX_DSCR_EMPTY_INT_ST field. + SLC__0INT_ST_SLC0_TX_DSCR_EMPTY_INT_ST_Msk = 0x200000 + // Bit SLC0_TX_DSCR_EMPTY_INT_ST. + SLC__0INT_ST_SLC0_TX_DSCR_EMPTY_INT_ST = 0x200000 + // Position of SLC0_HOST_RD_ACK_INT_ST field. + SLC__0INT_ST_SLC0_HOST_RD_ACK_INT_ST_Pos = 0x16 + // Bit mask of SLC0_HOST_RD_ACK_INT_ST field. + SLC__0INT_ST_SLC0_HOST_RD_ACK_INT_ST_Msk = 0x400000 + // Bit SLC0_HOST_RD_ACK_INT_ST. + SLC__0INT_ST_SLC0_HOST_RD_ACK_INT_ST = 0x400000 + // Position of SLC0_WR_RETRY_DONE_INT_ST field. + SLC__0INT_ST_SLC0_WR_RETRY_DONE_INT_ST_Pos = 0x17 + // Bit mask of SLC0_WR_RETRY_DONE_INT_ST field. + SLC__0INT_ST_SLC0_WR_RETRY_DONE_INT_ST_Msk = 0x800000 + // Bit SLC0_WR_RETRY_DONE_INT_ST. + SLC__0INT_ST_SLC0_WR_RETRY_DONE_INT_ST = 0x800000 + // Position of SLC0_TX_ERR_EOF_INT_ST field. + SLC__0INT_ST_SLC0_TX_ERR_EOF_INT_ST_Pos = 0x18 + // Bit mask of SLC0_TX_ERR_EOF_INT_ST field. + SLC__0INT_ST_SLC0_TX_ERR_EOF_INT_ST_Msk = 0x1000000 + // Bit SLC0_TX_ERR_EOF_INT_ST. + SLC__0INT_ST_SLC0_TX_ERR_EOF_INT_ST = 0x1000000 + // Position of CMD_DTC_INT_ST field. + SLC__0INT_ST_CMD_DTC_INT_ST_Pos = 0x19 + // Bit mask of CMD_DTC_INT_ST field. + SLC__0INT_ST_CMD_DTC_INT_ST_Msk = 0x2000000 + // Bit CMD_DTC_INT_ST. + SLC__0INT_ST_CMD_DTC_INT_ST = 0x2000000 + // Position of SLC0_RX_QUICK_EOF_INT_ST field. + SLC__0INT_ST_SLC0_RX_QUICK_EOF_INT_ST_Pos = 0x1a + // Bit mask of SLC0_RX_QUICK_EOF_INT_ST field. + SLC__0INT_ST_SLC0_RX_QUICK_EOF_INT_ST_Msk = 0x4000000 + // Bit SLC0_RX_QUICK_EOF_INT_ST. + SLC__0INT_ST_SLC0_RX_QUICK_EOF_INT_ST = 0x4000000 + + // _0INT_ENA + // Position of FRHOST_BIT0_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of FRHOST_BIT0_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit FRHOST_BIT0_INT_ENA. + SLC__0INT_ENA_FRHOST_BIT0_INT_ENA = 0x1 + // Position of FRHOST_BIT1_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of FRHOST_BIT1_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit FRHOST_BIT1_INT_ENA. + SLC__0INT_ENA_FRHOST_BIT1_INT_ENA = 0x2 + // Position of FRHOST_BIT2_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of FRHOST_BIT2_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit FRHOST_BIT2_INT_ENA. + SLC__0INT_ENA_FRHOST_BIT2_INT_ENA = 0x4 + // Position of FRHOST_BIT3_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of FRHOST_BIT3_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit FRHOST_BIT3_INT_ENA. + SLC__0INT_ENA_FRHOST_BIT3_INT_ENA = 0x8 + // Position of FRHOST_BIT4_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of FRHOST_BIT4_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit FRHOST_BIT4_INT_ENA. + SLC__0INT_ENA_FRHOST_BIT4_INT_ENA = 0x10 + // Position of FRHOST_BIT5_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of FRHOST_BIT5_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit FRHOST_BIT5_INT_ENA. + SLC__0INT_ENA_FRHOST_BIT5_INT_ENA = 0x20 + // Position of FRHOST_BIT6_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of FRHOST_BIT6_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit FRHOST_BIT6_INT_ENA. + SLC__0INT_ENA_FRHOST_BIT6_INT_ENA = 0x40 + // Position of FRHOST_BIT7_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of FRHOST_BIT7_INT_ENA field. + SLC__0INT_ENA_FRHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit FRHOST_BIT7_INT_ENA. + SLC__0INT_ENA_FRHOST_BIT7_INT_ENA = 0x80 + // Position of SLC0_RX_START_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_START_INT_ENA_Pos = 0x8 + // Bit mask of SLC0_RX_START_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_START_INT_ENA_Msk = 0x100 + // Bit SLC0_RX_START_INT_ENA. + SLC__0INT_ENA_SLC0_RX_START_INT_ENA = 0x100 + // Position of SLC0_TX_START_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_START_INT_ENA_Pos = 0x9 + // Bit mask of SLC0_TX_START_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_START_INT_ENA_Msk = 0x200 + // Bit SLC0_TX_START_INT_ENA. + SLC__0INT_ENA_SLC0_TX_START_INT_ENA = 0x200 + // Position of SLC0_RX_UDF_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_UDF_INT_ENA_Pos = 0xa + // Bit mask of SLC0_RX_UDF_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_UDF_INT_ENA_Msk = 0x400 + // Bit SLC0_RX_UDF_INT_ENA. + SLC__0INT_ENA_SLC0_RX_UDF_INT_ENA = 0x400 + // Position of SLC0_TX_OVF_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_OVF_INT_ENA_Pos = 0xb + // Bit mask of SLC0_TX_OVF_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_OVF_INT_ENA_Msk = 0x800 + // Bit SLC0_TX_OVF_INT_ENA. + SLC__0INT_ENA_SLC0_TX_OVF_INT_ENA = 0x800 + // Position of SLC0_TOKEN0_1TO0_INT_ENA field. + SLC__0INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA_Pos = 0xc + // Bit mask of SLC0_TOKEN0_1TO0_INT_ENA field. + SLC__0INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA_Msk = 0x1000 + // Bit SLC0_TOKEN0_1TO0_INT_ENA. + SLC__0INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA = 0x1000 + // Position of SLC0_TOKEN1_1TO0_INT_ENA field. + SLC__0INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA_Pos = 0xd + // Bit mask of SLC0_TOKEN1_1TO0_INT_ENA field. + SLC__0INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA_Msk = 0x2000 + // Bit SLC0_TOKEN1_1TO0_INT_ENA. + SLC__0INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA = 0x2000 + // Position of SLC0_TX_DONE_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of SLC0_TX_DONE_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit SLC0_TX_DONE_INT_ENA. + SLC__0INT_ENA_SLC0_TX_DONE_INT_ENA = 0x4000 + // Position of SLC0_TX_SUC_EOF_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_SUC_EOF_INT_ENA_Pos = 0xf + // Bit mask of SLC0_TX_SUC_EOF_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_SUC_EOF_INT_ENA_Msk = 0x8000 + // Bit SLC0_TX_SUC_EOF_INT_ENA. + SLC__0INT_ENA_SLC0_TX_SUC_EOF_INT_ENA = 0x8000 + // Position of SLC0_RX_DONE_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_DONE_INT_ENA_Pos = 0x10 + // Bit mask of SLC0_RX_DONE_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_DONE_INT_ENA_Msk = 0x10000 + // Bit SLC0_RX_DONE_INT_ENA. + SLC__0INT_ENA_SLC0_RX_DONE_INT_ENA = 0x10000 + // Position of SLC0_RX_EOF_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_EOF_INT_ENA_Pos = 0x11 + // Bit mask of SLC0_RX_EOF_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_EOF_INT_ENA_Msk = 0x20000 + // Bit SLC0_RX_EOF_INT_ENA. + SLC__0INT_ENA_SLC0_RX_EOF_INT_ENA = 0x20000 + // Position of SLC0_TOHOST_INT_ENA field. + SLC__0INT_ENA_SLC0_TOHOST_INT_ENA_Pos = 0x12 + // Bit mask of SLC0_TOHOST_INT_ENA field. + SLC__0INT_ENA_SLC0_TOHOST_INT_ENA_Msk = 0x40000 + // Bit SLC0_TOHOST_INT_ENA. + SLC__0INT_ENA_SLC0_TOHOST_INT_ENA = 0x40000 + // Position of SLC0_TX_DSCR_ERR_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_DSCR_ERR_INT_ENA_Pos = 0x13 + // Bit mask of SLC0_TX_DSCR_ERR_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_DSCR_ERR_INT_ENA_Msk = 0x80000 + // Bit SLC0_TX_DSCR_ERR_INT_ENA. + SLC__0INT_ENA_SLC0_TX_DSCR_ERR_INT_ENA = 0x80000 + // Position of SLC0_RX_DSCR_ERR_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_DSCR_ERR_INT_ENA_Pos = 0x14 + // Bit mask of SLC0_RX_DSCR_ERR_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_DSCR_ERR_INT_ENA_Msk = 0x100000 + // Bit SLC0_RX_DSCR_ERR_INT_ENA. + SLC__0INT_ENA_SLC0_RX_DSCR_ERR_INT_ENA = 0x100000 + // Position of SLC0_TX_DSCR_EMPTY_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_DSCR_EMPTY_INT_ENA_Pos = 0x15 + // Bit mask of SLC0_TX_DSCR_EMPTY_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_DSCR_EMPTY_INT_ENA_Msk = 0x200000 + // Bit SLC0_TX_DSCR_EMPTY_INT_ENA. + SLC__0INT_ENA_SLC0_TX_DSCR_EMPTY_INT_ENA = 0x200000 + // Position of SLC0_HOST_RD_ACK_INT_ENA field. + SLC__0INT_ENA_SLC0_HOST_RD_ACK_INT_ENA_Pos = 0x16 + // Bit mask of SLC0_HOST_RD_ACK_INT_ENA field. + SLC__0INT_ENA_SLC0_HOST_RD_ACK_INT_ENA_Msk = 0x400000 + // Bit SLC0_HOST_RD_ACK_INT_ENA. + SLC__0INT_ENA_SLC0_HOST_RD_ACK_INT_ENA = 0x400000 + // Position of SLC0_WR_RETRY_DONE_INT_ENA field. + SLC__0INT_ENA_SLC0_WR_RETRY_DONE_INT_ENA_Pos = 0x17 + // Bit mask of SLC0_WR_RETRY_DONE_INT_ENA field. + SLC__0INT_ENA_SLC0_WR_RETRY_DONE_INT_ENA_Msk = 0x800000 + // Bit SLC0_WR_RETRY_DONE_INT_ENA. + SLC__0INT_ENA_SLC0_WR_RETRY_DONE_INT_ENA = 0x800000 + // Position of SLC0_TX_ERR_EOF_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_ERR_EOF_INT_ENA_Pos = 0x18 + // Bit mask of SLC0_TX_ERR_EOF_INT_ENA field. + SLC__0INT_ENA_SLC0_TX_ERR_EOF_INT_ENA_Msk = 0x1000000 + // Bit SLC0_TX_ERR_EOF_INT_ENA. + SLC__0INT_ENA_SLC0_TX_ERR_EOF_INT_ENA = 0x1000000 + // Position of CMD_DTC_INT_ENA field. + SLC__0INT_ENA_CMD_DTC_INT_ENA_Pos = 0x19 + // Bit mask of CMD_DTC_INT_ENA field. + SLC__0INT_ENA_CMD_DTC_INT_ENA_Msk = 0x2000000 + // Bit CMD_DTC_INT_ENA. + SLC__0INT_ENA_CMD_DTC_INT_ENA = 0x2000000 + // Position of SLC0_RX_QUICK_EOF_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_QUICK_EOF_INT_ENA_Pos = 0x1a + // Bit mask of SLC0_RX_QUICK_EOF_INT_ENA field. + SLC__0INT_ENA_SLC0_RX_QUICK_EOF_INT_ENA_Msk = 0x4000000 + // Bit SLC0_RX_QUICK_EOF_INT_ENA. + SLC__0INT_ENA_SLC0_RX_QUICK_EOF_INT_ENA = 0x4000000 + + // _0INT_CLR + // Position of FRHOST_BIT0_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT0_INT_CLR_Pos = 0x0 + // Bit mask of FRHOST_BIT0_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT0_INT_CLR_Msk = 0x1 + // Bit FRHOST_BIT0_INT_CLR. + SLC__0INT_CLR_FRHOST_BIT0_INT_CLR = 0x1 + // Position of FRHOST_BIT1_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT1_INT_CLR_Pos = 0x1 + // Bit mask of FRHOST_BIT1_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT1_INT_CLR_Msk = 0x2 + // Bit FRHOST_BIT1_INT_CLR. + SLC__0INT_CLR_FRHOST_BIT1_INT_CLR = 0x2 + // Position of FRHOST_BIT2_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT2_INT_CLR_Pos = 0x2 + // Bit mask of FRHOST_BIT2_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT2_INT_CLR_Msk = 0x4 + // Bit FRHOST_BIT2_INT_CLR. + SLC__0INT_CLR_FRHOST_BIT2_INT_CLR = 0x4 + // Position of FRHOST_BIT3_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT3_INT_CLR_Pos = 0x3 + // Bit mask of FRHOST_BIT3_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT3_INT_CLR_Msk = 0x8 + // Bit FRHOST_BIT3_INT_CLR. + SLC__0INT_CLR_FRHOST_BIT3_INT_CLR = 0x8 + // Position of FRHOST_BIT4_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT4_INT_CLR_Pos = 0x4 + // Bit mask of FRHOST_BIT4_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT4_INT_CLR_Msk = 0x10 + // Bit FRHOST_BIT4_INT_CLR. + SLC__0INT_CLR_FRHOST_BIT4_INT_CLR = 0x10 + // Position of FRHOST_BIT5_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT5_INT_CLR_Pos = 0x5 + // Bit mask of FRHOST_BIT5_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT5_INT_CLR_Msk = 0x20 + // Bit FRHOST_BIT5_INT_CLR. + SLC__0INT_CLR_FRHOST_BIT5_INT_CLR = 0x20 + // Position of FRHOST_BIT6_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT6_INT_CLR_Pos = 0x6 + // Bit mask of FRHOST_BIT6_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT6_INT_CLR_Msk = 0x40 + // Bit FRHOST_BIT6_INT_CLR. + SLC__0INT_CLR_FRHOST_BIT6_INT_CLR = 0x40 + // Position of FRHOST_BIT7_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT7_INT_CLR_Pos = 0x7 + // Bit mask of FRHOST_BIT7_INT_CLR field. + SLC__0INT_CLR_FRHOST_BIT7_INT_CLR_Msk = 0x80 + // Bit FRHOST_BIT7_INT_CLR. + SLC__0INT_CLR_FRHOST_BIT7_INT_CLR = 0x80 + // Position of SLC0_RX_START_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_START_INT_CLR_Pos = 0x8 + // Bit mask of SLC0_RX_START_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_START_INT_CLR_Msk = 0x100 + // Bit SLC0_RX_START_INT_CLR. + SLC__0INT_CLR_SLC0_RX_START_INT_CLR = 0x100 + // Position of SLC0_TX_START_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_START_INT_CLR_Pos = 0x9 + // Bit mask of SLC0_TX_START_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_START_INT_CLR_Msk = 0x200 + // Bit SLC0_TX_START_INT_CLR. + SLC__0INT_CLR_SLC0_TX_START_INT_CLR = 0x200 + // Position of SLC0_RX_UDF_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_UDF_INT_CLR_Pos = 0xa + // Bit mask of SLC0_RX_UDF_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_UDF_INT_CLR_Msk = 0x400 + // Bit SLC0_RX_UDF_INT_CLR. + SLC__0INT_CLR_SLC0_RX_UDF_INT_CLR = 0x400 + // Position of SLC0_TX_OVF_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_OVF_INT_CLR_Pos = 0xb + // Bit mask of SLC0_TX_OVF_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_OVF_INT_CLR_Msk = 0x800 + // Bit SLC0_TX_OVF_INT_CLR. + SLC__0INT_CLR_SLC0_TX_OVF_INT_CLR = 0x800 + // Position of SLC0_TOKEN0_1TO0_INT_CLR field. + SLC__0INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR_Pos = 0xc + // Bit mask of SLC0_TOKEN0_1TO0_INT_CLR field. + SLC__0INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR_Msk = 0x1000 + // Bit SLC0_TOKEN0_1TO0_INT_CLR. + SLC__0INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR = 0x1000 + // Position of SLC0_TOKEN1_1TO0_INT_CLR field. + SLC__0INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR_Pos = 0xd + // Bit mask of SLC0_TOKEN1_1TO0_INT_CLR field. + SLC__0INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR_Msk = 0x2000 + // Bit SLC0_TOKEN1_1TO0_INT_CLR. + SLC__0INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR = 0x2000 + // Position of SLC0_TX_DONE_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of SLC0_TX_DONE_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit SLC0_TX_DONE_INT_CLR. + SLC__0INT_CLR_SLC0_TX_DONE_INT_CLR = 0x4000 + // Position of SLC0_TX_SUC_EOF_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_SUC_EOF_INT_CLR_Pos = 0xf + // Bit mask of SLC0_TX_SUC_EOF_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_SUC_EOF_INT_CLR_Msk = 0x8000 + // Bit SLC0_TX_SUC_EOF_INT_CLR. + SLC__0INT_CLR_SLC0_TX_SUC_EOF_INT_CLR = 0x8000 + // Position of SLC0_RX_DONE_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_DONE_INT_CLR_Pos = 0x10 + // Bit mask of SLC0_RX_DONE_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_DONE_INT_CLR_Msk = 0x10000 + // Bit SLC0_RX_DONE_INT_CLR. + SLC__0INT_CLR_SLC0_RX_DONE_INT_CLR = 0x10000 + // Position of SLC0_RX_EOF_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_EOF_INT_CLR_Pos = 0x11 + // Bit mask of SLC0_RX_EOF_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_EOF_INT_CLR_Msk = 0x20000 + // Bit SLC0_RX_EOF_INT_CLR. + SLC__0INT_CLR_SLC0_RX_EOF_INT_CLR = 0x20000 + // Position of SLC0_TOHOST_INT_CLR field. + SLC__0INT_CLR_SLC0_TOHOST_INT_CLR_Pos = 0x12 + // Bit mask of SLC0_TOHOST_INT_CLR field. + SLC__0INT_CLR_SLC0_TOHOST_INT_CLR_Msk = 0x40000 + // Bit SLC0_TOHOST_INT_CLR. + SLC__0INT_CLR_SLC0_TOHOST_INT_CLR = 0x40000 + // Position of SLC0_TX_DSCR_ERR_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_DSCR_ERR_INT_CLR_Pos = 0x13 + // Bit mask of SLC0_TX_DSCR_ERR_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_DSCR_ERR_INT_CLR_Msk = 0x80000 + // Bit SLC0_TX_DSCR_ERR_INT_CLR. + SLC__0INT_CLR_SLC0_TX_DSCR_ERR_INT_CLR = 0x80000 + // Position of SLC0_RX_DSCR_ERR_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_DSCR_ERR_INT_CLR_Pos = 0x14 + // Bit mask of SLC0_RX_DSCR_ERR_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_DSCR_ERR_INT_CLR_Msk = 0x100000 + // Bit SLC0_RX_DSCR_ERR_INT_CLR. + SLC__0INT_CLR_SLC0_RX_DSCR_ERR_INT_CLR = 0x100000 + // Position of SLC0_TX_DSCR_EMPTY_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_DSCR_EMPTY_INT_CLR_Pos = 0x15 + // Bit mask of SLC0_TX_DSCR_EMPTY_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_DSCR_EMPTY_INT_CLR_Msk = 0x200000 + // Bit SLC0_TX_DSCR_EMPTY_INT_CLR. + SLC__0INT_CLR_SLC0_TX_DSCR_EMPTY_INT_CLR = 0x200000 + // Position of SLC0_HOST_RD_ACK_INT_CLR field. + SLC__0INT_CLR_SLC0_HOST_RD_ACK_INT_CLR_Pos = 0x16 + // Bit mask of SLC0_HOST_RD_ACK_INT_CLR field. + SLC__0INT_CLR_SLC0_HOST_RD_ACK_INT_CLR_Msk = 0x400000 + // Bit SLC0_HOST_RD_ACK_INT_CLR. + SLC__0INT_CLR_SLC0_HOST_RD_ACK_INT_CLR = 0x400000 + // Position of SLC0_WR_RETRY_DONE_INT_CLR field. + SLC__0INT_CLR_SLC0_WR_RETRY_DONE_INT_CLR_Pos = 0x17 + // Bit mask of SLC0_WR_RETRY_DONE_INT_CLR field. + SLC__0INT_CLR_SLC0_WR_RETRY_DONE_INT_CLR_Msk = 0x800000 + // Bit SLC0_WR_RETRY_DONE_INT_CLR. + SLC__0INT_CLR_SLC0_WR_RETRY_DONE_INT_CLR = 0x800000 + // Position of SLC0_TX_ERR_EOF_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_ERR_EOF_INT_CLR_Pos = 0x18 + // Bit mask of SLC0_TX_ERR_EOF_INT_CLR field. + SLC__0INT_CLR_SLC0_TX_ERR_EOF_INT_CLR_Msk = 0x1000000 + // Bit SLC0_TX_ERR_EOF_INT_CLR. + SLC__0INT_CLR_SLC0_TX_ERR_EOF_INT_CLR = 0x1000000 + // Position of CMD_DTC_INT_CLR field. + SLC__0INT_CLR_CMD_DTC_INT_CLR_Pos = 0x19 + // Bit mask of CMD_DTC_INT_CLR field. + SLC__0INT_CLR_CMD_DTC_INT_CLR_Msk = 0x2000000 + // Bit CMD_DTC_INT_CLR. + SLC__0INT_CLR_CMD_DTC_INT_CLR = 0x2000000 + // Position of SLC0_RX_QUICK_EOF_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_QUICK_EOF_INT_CLR_Pos = 0x1a + // Bit mask of SLC0_RX_QUICK_EOF_INT_CLR field. + SLC__0INT_CLR_SLC0_RX_QUICK_EOF_INT_CLR_Msk = 0x4000000 + // Bit SLC0_RX_QUICK_EOF_INT_CLR. + SLC__0INT_CLR_SLC0_RX_QUICK_EOF_INT_CLR = 0x4000000 + + // _1INT_RAW + // Position of FRHOST_BIT8_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT8_INT_RAW_Pos = 0x0 + // Bit mask of FRHOST_BIT8_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT8_INT_RAW_Msk = 0x1 + // Bit FRHOST_BIT8_INT_RAW. + SLC__1INT_RAW_FRHOST_BIT8_INT_RAW = 0x1 + // Position of FRHOST_BIT9_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT9_INT_RAW_Pos = 0x1 + // Bit mask of FRHOST_BIT9_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT9_INT_RAW_Msk = 0x2 + // Bit FRHOST_BIT9_INT_RAW. + SLC__1INT_RAW_FRHOST_BIT9_INT_RAW = 0x2 + // Position of FRHOST_BIT10_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT10_INT_RAW_Pos = 0x2 + // Bit mask of FRHOST_BIT10_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT10_INT_RAW_Msk = 0x4 + // Bit FRHOST_BIT10_INT_RAW. + SLC__1INT_RAW_FRHOST_BIT10_INT_RAW = 0x4 + // Position of FRHOST_BIT11_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT11_INT_RAW_Pos = 0x3 + // Bit mask of FRHOST_BIT11_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT11_INT_RAW_Msk = 0x8 + // Bit FRHOST_BIT11_INT_RAW. + SLC__1INT_RAW_FRHOST_BIT11_INT_RAW = 0x8 + // Position of FRHOST_BIT12_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT12_INT_RAW_Pos = 0x4 + // Bit mask of FRHOST_BIT12_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT12_INT_RAW_Msk = 0x10 + // Bit FRHOST_BIT12_INT_RAW. + SLC__1INT_RAW_FRHOST_BIT12_INT_RAW = 0x10 + // Position of FRHOST_BIT13_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT13_INT_RAW_Pos = 0x5 + // Bit mask of FRHOST_BIT13_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT13_INT_RAW_Msk = 0x20 + // Bit FRHOST_BIT13_INT_RAW. + SLC__1INT_RAW_FRHOST_BIT13_INT_RAW = 0x20 + // Position of FRHOST_BIT14_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT14_INT_RAW_Pos = 0x6 + // Bit mask of FRHOST_BIT14_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT14_INT_RAW_Msk = 0x40 + // Bit FRHOST_BIT14_INT_RAW. + SLC__1INT_RAW_FRHOST_BIT14_INT_RAW = 0x40 + // Position of FRHOST_BIT15_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT15_INT_RAW_Pos = 0x7 + // Bit mask of FRHOST_BIT15_INT_RAW field. + SLC__1INT_RAW_FRHOST_BIT15_INT_RAW_Msk = 0x80 + // Bit FRHOST_BIT15_INT_RAW. + SLC__1INT_RAW_FRHOST_BIT15_INT_RAW = 0x80 + // Position of SLC1_RX_START_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_START_INT_RAW_Pos = 0x8 + // Bit mask of SLC1_RX_START_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_START_INT_RAW_Msk = 0x100 + // Bit SLC1_RX_START_INT_RAW. + SLC__1INT_RAW_SLC1_RX_START_INT_RAW = 0x100 + // Position of SLC1_TX_START_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_START_INT_RAW_Pos = 0x9 + // Bit mask of SLC1_TX_START_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_START_INT_RAW_Msk = 0x200 + // Bit SLC1_TX_START_INT_RAW. + SLC__1INT_RAW_SLC1_TX_START_INT_RAW = 0x200 + // Position of SLC1_RX_UDF_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_UDF_INT_RAW_Pos = 0xa + // Bit mask of SLC1_RX_UDF_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_UDF_INT_RAW_Msk = 0x400 + // Bit SLC1_RX_UDF_INT_RAW. + SLC__1INT_RAW_SLC1_RX_UDF_INT_RAW = 0x400 + // Position of SLC1_TX_OVF_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_OVF_INT_RAW_Pos = 0xb + // Bit mask of SLC1_TX_OVF_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_OVF_INT_RAW_Msk = 0x800 + // Bit SLC1_TX_OVF_INT_RAW. + SLC__1INT_RAW_SLC1_TX_OVF_INT_RAW = 0x800 + // Position of SLC1_TOKEN0_1TO0_INT_RAW field. + SLC__1INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW_Pos = 0xc + // Bit mask of SLC1_TOKEN0_1TO0_INT_RAW field. + SLC__1INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW_Msk = 0x1000 + // Bit SLC1_TOKEN0_1TO0_INT_RAW. + SLC__1INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW = 0x1000 + // Position of SLC1_TOKEN1_1TO0_INT_RAW field. + SLC__1INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW_Pos = 0xd + // Bit mask of SLC1_TOKEN1_1TO0_INT_RAW field. + SLC__1INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW_Msk = 0x2000 + // Bit SLC1_TOKEN1_1TO0_INT_RAW. + SLC__1INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW = 0x2000 + // Position of SLC1_TX_DONE_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of SLC1_TX_DONE_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit SLC1_TX_DONE_INT_RAW. + SLC__1INT_RAW_SLC1_TX_DONE_INT_RAW = 0x4000 + // Position of SLC1_TX_SUC_EOF_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_SUC_EOF_INT_RAW_Pos = 0xf + // Bit mask of SLC1_TX_SUC_EOF_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_SUC_EOF_INT_RAW_Msk = 0x8000 + // Bit SLC1_TX_SUC_EOF_INT_RAW. + SLC__1INT_RAW_SLC1_TX_SUC_EOF_INT_RAW = 0x8000 + // Position of SLC1_RX_DONE_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_DONE_INT_RAW_Pos = 0x10 + // Bit mask of SLC1_RX_DONE_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_DONE_INT_RAW_Msk = 0x10000 + // Bit SLC1_RX_DONE_INT_RAW. + SLC__1INT_RAW_SLC1_RX_DONE_INT_RAW = 0x10000 + // Position of SLC1_RX_EOF_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_EOF_INT_RAW_Pos = 0x11 + // Bit mask of SLC1_RX_EOF_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_EOF_INT_RAW_Msk = 0x20000 + // Bit SLC1_RX_EOF_INT_RAW. + SLC__1INT_RAW_SLC1_RX_EOF_INT_RAW = 0x20000 + // Position of SLC1_TOHOST_INT_RAW field. + SLC__1INT_RAW_SLC1_TOHOST_INT_RAW_Pos = 0x12 + // Bit mask of SLC1_TOHOST_INT_RAW field. + SLC__1INT_RAW_SLC1_TOHOST_INT_RAW_Msk = 0x40000 + // Bit SLC1_TOHOST_INT_RAW. + SLC__1INT_RAW_SLC1_TOHOST_INT_RAW = 0x40000 + // Position of SLC1_TX_DSCR_ERR_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_DSCR_ERR_INT_RAW_Pos = 0x13 + // Bit mask of SLC1_TX_DSCR_ERR_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_DSCR_ERR_INT_RAW_Msk = 0x80000 + // Bit SLC1_TX_DSCR_ERR_INT_RAW. + SLC__1INT_RAW_SLC1_TX_DSCR_ERR_INT_RAW = 0x80000 + // Position of SLC1_RX_DSCR_ERR_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_DSCR_ERR_INT_RAW_Pos = 0x14 + // Bit mask of SLC1_RX_DSCR_ERR_INT_RAW field. + SLC__1INT_RAW_SLC1_RX_DSCR_ERR_INT_RAW_Msk = 0x100000 + // Bit SLC1_RX_DSCR_ERR_INT_RAW. + SLC__1INT_RAW_SLC1_RX_DSCR_ERR_INT_RAW = 0x100000 + // Position of SLC1_TX_DSCR_EMPTY_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_DSCR_EMPTY_INT_RAW_Pos = 0x15 + // Bit mask of SLC1_TX_DSCR_EMPTY_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_DSCR_EMPTY_INT_RAW_Msk = 0x200000 + // Bit SLC1_TX_DSCR_EMPTY_INT_RAW. + SLC__1INT_RAW_SLC1_TX_DSCR_EMPTY_INT_RAW = 0x200000 + // Position of SLC1_HOST_RD_ACK_INT_RAW field. + SLC__1INT_RAW_SLC1_HOST_RD_ACK_INT_RAW_Pos = 0x16 + // Bit mask of SLC1_HOST_RD_ACK_INT_RAW field. + SLC__1INT_RAW_SLC1_HOST_RD_ACK_INT_RAW_Msk = 0x400000 + // Bit SLC1_HOST_RD_ACK_INT_RAW. + SLC__1INT_RAW_SLC1_HOST_RD_ACK_INT_RAW = 0x400000 + // Position of SLC1_WR_RETRY_DONE_INT_RAW field. + SLC__1INT_RAW_SLC1_WR_RETRY_DONE_INT_RAW_Pos = 0x17 + // Bit mask of SLC1_WR_RETRY_DONE_INT_RAW field. + SLC__1INT_RAW_SLC1_WR_RETRY_DONE_INT_RAW_Msk = 0x800000 + // Bit SLC1_WR_RETRY_DONE_INT_RAW. + SLC__1INT_RAW_SLC1_WR_RETRY_DONE_INT_RAW = 0x800000 + // Position of SLC1_TX_ERR_EOF_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_ERR_EOF_INT_RAW_Pos = 0x18 + // Bit mask of SLC1_TX_ERR_EOF_INT_RAW field. + SLC__1INT_RAW_SLC1_TX_ERR_EOF_INT_RAW_Msk = 0x1000000 + // Bit SLC1_TX_ERR_EOF_INT_RAW. + SLC__1INT_RAW_SLC1_TX_ERR_EOF_INT_RAW = 0x1000000 + + // _1INT_ST + // Position of FRHOST_BIT8_INT_ST field. + SLC__1INT_ST_FRHOST_BIT8_INT_ST_Pos = 0x0 + // Bit mask of FRHOST_BIT8_INT_ST field. + SLC__1INT_ST_FRHOST_BIT8_INT_ST_Msk = 0x1 + // Bit FRHOST_BIT8_INT_ST. + SLC__1INT_ST_FRHOST_BIT8_INT_ST = 0x1 + // Position of FRHOST_BIT9_INT_ST field. + SLC__1INT_ST_FRHOST_BIT9_INT_ST_Pos = 0x1 + // Bit mask of FRHOST_BIT9_INT_ST field. + SLC__1INT_ST_FRHOST_BIT9_INT_ST_Msk = 0x2 + // Bit FRHOST_BIT9_INT_ST. + SLC__1INT_ST_FRHOST_BIT9_INT_ST = 0x2 + // Position of FRHOST_BIT10_INT_ST field. + SLC__1INT_ST_FRHOST_BIT10_INT_ST_Pos = 0x2 + // Bit mask of FRHOST_BIT10_INT_ST field. + SLC__1INT_ST_FRHOST_BIT10_INT_ST_Msk = 0x4 + // Bit FRHOST_BIT10_INT_ST. + SLC__1INT_ST_FRHOST_BIT10_INT_ST = 0x4 + // Position of FRHOST_BIT11_INT_ST field. + SLC__1INT_ST_FRHOST_BIT11_INT_ST_Pos = 0x3 + // Bit mask of FRHOST_BIT11_INT_ST field. + SLC__1INT_ST_FRHOST_BIT11_INT_ST_Msk = 0x8 + // Bit FRHOST_BIT11_INT_ST. + SLC__1INT_ST_FRHOST_BIT11_INT_ST = 0x8 + // Position of FRHOST_BIT12_INT_ST field. + SLC__1INT_ST_FRHOST_BIT12_INT_ST_Pos = 0x4 + // Bit mask of FRHOST_BIT12_INT_ST field. + SLC__1INT_ST_FRHOST_BIT12_INT_ST_Msk = 0x10 + // Bit FRHOST_BIT12_INT_ST. + SLC__1INT_ST_FRHOST_BIT12_INT_ST = 0x10 + // Position of FRHOST_BIT13_INT_ST field. + SLC__1INT_ST_FRHOST_BIT13_INT_ST_Pos = 0x5 + // Bit mask of FRHOST_BIT13_INT_ST field. + SLC__1INT_ST_FRHOST_BIT13_INT_ST_Msk = 0x20 + // Bit FRHOST_BIT13_INT_ST. + SLC__1INT_ST_FRHOST_BIT13_INT_ST = 0x20 + // Position of FRHOST_BIT14_INT_ST field. + SLC__1INT_ST_FRHOST_BIT14_INT_ST_Pos = 0x6 + // Bit mask of FRHOST_BIT14_INT_ST field. + SLC__1INT_ST_FRHOST_BIT14_INT_ST_Msk = 0x40 + // Bit FRHOST_BIT14_INT_ST. + SLC__1INT_ST_FRHOST_BIT14_INT_ST = 0x40 + // Position of FRHOST_BIT15_INT_ST field. + SLC__1INT_ST_FRHOST_BIT15_INT_ST_Pos = 0x7 + // Bit mask of FRHOST_BIT15_INT_ST field. + SLC__1INT_ST_FRHOST_BIT15_INT_ST_Msk = 0x80 + // Bit FRHOST_BIT15_INT_ST. + SLC__1INT_ST_FRHOST_BIT15_INT_ST = 0x80 + // Position of SLC1_RX_START_INT_ST field. + SLC__1INT_ST_SLC1_RX_START_INT_ST_Pos = 0x8 + // Bit mask of SLC1_RX_START_INT_ST field. + SLC__1INT_ST_SLC1_RX_START_INT_ST_Msk = 0x100 + // Bit SLC1_RX_START_INT_ST. + SLC__1INT_ST_SLC1_RX_START_INT_ST = 0x100 + // Position of SLC1_TX_START_INT_ST field. + SLC__1INT_ST_SLC1_TX_START_INT_ST_Pos = 0x9 + // Bit mask of SLC1_TX_START_INT_ST field. + SLC__1INT_ST_SLC1_TX_START_INT_ST_Msk = 0x200 + // Bit SLC1_TX_START_INT_ST. + SLC__1INT_ST_SLC1_TX_START_INT_ST = 0x200 + // Position of SLC1_RX_UDF_INT_ST field. + SLC__1INT_ST_SLC1_RX_UDF_INT_ST_Pos = 0xa + // Bit mask of SLC1_RX_UDF_INT_ST field. + SLC__1INT_ST_SLC1_RX_UDF_INT_ST_Msk = 0x400 + // Bit SLC1_RX_UDF_INT_ST. + SLC__1INT_ST_SLC1_RX_UDF_INT_ST = 0x400 + // Position of SLC1_TX_OVF_INT_ST field. + SLC__1INT_ST_SLC1_TX_OVF_INT_ST_Pos = 0xb + // Bit mask of SLC1_TX_OVF_INT_ST field. + SLC__1INT_ST_SLC1_TX_OVF_INT_ST_Msk = 0x800 + // Bit SLC1_TX_OVF_INT_ST. + SLC__1INT_ST_SLC1_TX_OVF_INT_ST = 0x800 + // Position of SLC1_TOKEN0_1TO0_INT_ST field. + SLC__1INT_ST_SLC1_TOKEN0_1TO0_INT_ST_Pos = 0xc + // Bit mask of SLC1_TOKEN0_1TO0_INT_ST field. + SLC__1INT_ST_SLC1_TOKEN0_1TO0_INT_ST_Msk = 0x1000 + // Bit SLC1_TOKEN0_1TO0_INT_ST. + SLC__1INT_ST_SLC1_TOKEN0_1TO0_INT_ST = 0x1000 + // Position of SLC1_TOKEN1_1TO0_INT_ST field. + SLC__1INT_ST_SLC1_TOKEN1_1TO0_INT_ST_Pos = 0xd + // Bit mask of SLC1_TOKEN1_1TO0_INT_ST field. + SLC__1INT_ST_SLC1_TOKEN1_1TO0_INT_ST_Msk = 0x2000 + // Bit SLC1_TOKEN1_1TO0_INT_ST. + SLC__1INT_ST_SLC1_TOKEN1_1TO0_INT_ST = 0x2000 + // Position of SLC1_TX_DONE_INT_ST field. + SLC__1INT_ST_SLC1_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of SLC1_TX_DONE_INT_ST field. + SLC__1INT_ST_SLC1_TX_DONE_INT_ST_Msk = 0x4000 + // Bit SLC1_TX_DONE_INT_ST. + SLC__1INT_ST_SLC1_TX_DONE_INT_ST = 0x4000 + // Position of SLC1_TX_SUC_EOF_INT_ST field. + SLC__1INT_ST_SLC1_TX_SUC_EOF_INT_ST_Pos = 0xf + // Bit mask of SLC1_TX_SUC_EOF_INT_ST field. + SLC__1INT_ST_SLC1_TX_SUC_EOF_INT_ST_Msk = 0x8000 + // Bit SLC1_TX_SUC_EOF_INT_ST. + SLC__1INT_ST_SLC1_TX_SUC_EOF_INT_ST = 0x8000 + // Position of SLC1_RX_DONE_INT_ST field. + SLC__1INT_ST_SLC1_RX_DONE_INT_ST_Pos = 0x10 + // Bit mask of SLC1_RX_DONE_INT_ST field. + SLC__1INT_ST_SLC1_RX_DONE_INT_ST_Msk = 0x10000 + // Bit SLC1_RX_DONE_INT_ST. + SLC__1INT_ST_SLC1_RX_DONE_INT_ST = 0x10000 + // Position of SLC1_RX_EOF_INT_ST field. + SLC__1INT_ST_SLC1_RX_EOF_INT_ST_Pos = 0x11 + // Bit mask of SLC1_RX_EOF_INT_ST field. + SLC__1INT_ST_SLC1_RX_EOF_INT_ST_Msk = 0x20000 + // Bit SLC1_RX_EOF_INT_ST. + SLC__1INT_ST_SLC1_RX_EOF_INT_ST = 0x20000 + // Position of SLC1_TOHOST_INT_ST field. + SLC__1INT_ST_SLC1_TOHOST_INT_ST_Pos = 0x12 + // Bit mask of SLC1_TOHOST_INT_ST field. + SLC__1INT_ST_SLC1_TOHOST_INT_ST_Msk = 0x40000 + // Bit SLC1_TOHOST_INT_ST. + SLC__1INT_ST_SLC1_TOHOST_INT_ST = 0x40000 + // Position of SLC1_TX_DSCR_ERR_INT_ST field. + SLC__1INT_ST_SLC1_TX_DSCR_ERR_INT_ST_Pos = 0x13 + // Bit mask of SLC1_TX_DSCR_ERR_INT_ST field. + SLC__1INT_ST_SLC1_TX_DSCR_ERR_INT_ST_Msk = 0x80000 + // Bit SLC1_TX_DSCR_ERR_INT_ST. + SLC__1INT_ST_SLC1_TX_DSCR_ERR_INT_ST = 0x80000 + // Position of SLC1_RX_DSCR_ERR_INT_ST field. + SLC__1INT_ST_SLC1_RX_DSCR_ERR_INT_ST_Pos = 0x14 + // Bit mask of SLC1_RX_DSCR_ERR_INT_ST field. + SLC__1INT_ST_SLC1_RX_DSCR_ERR_INT_ST_Msk = 0x100000 + // Bit SLC1_RX_DSCR_ERR_INT_ST. + SLC__1INT_ST_SLC1_RX_DSCR_ERR_INT_ST = 0x100000 + // Position of SLC1_TX_DSCR_EMPTY_INT_ST field. + SLC__1INT_ST_SLC1_TX_DSCR_EMPTY_INT_ST_Pos = 0x15 + // Bit mask of SLC1_TX_DSCR_EMPTY_INT_ST field. + SLC__1INT_ST_SLC1_TX_DSCR_EMPTY_INT_ST_Msk = 0x200000 + // Bit SLC1_TX_DSCR_EMPTY_INT_ST. + SLC__1INT_ST_SLC1_TX_DSCR_EMPTY_INT_ST = 0x200000 + // Position of SLC1_HOST_RD_ACK_INT_ST field. + SLC__1INT_ST_SLC1_HOST_RD_ACK_INT_ST_Pos = 0x16 + // Bit mask of SLC1_HOST_RD_ACK_INT_ST field. + SLC__1INT_ST_SLC1_HOST_RD_ACK_INT_ST_Msk = 0x400000 + // Bit SLC1_HOST_RD_ACK_INT_ST. + SLC__1INT_ST_SLC1_HOST_RD_ACK_INT_ST = 0x400000 + // Position of SLC1_WR_RETRY_DONE_INT_ST field. + SLC__1INT_ST_SLC1_WR_RETRY_DONE_INT_ST_Pos = 0x17 + // Bit mask of SLC1_WR_RETRY_DONE_INT_ST field. + SLC__1INT_ST_SLC1_WR_RETRY_DONE_INT_ST_Msk = 0x800000 + // Bit SLC1_WR_RETRY_DONE_INT_ST. + SLC__1INT_ST_SLC1_WR_RETRY_DONE_INT_ST = 0x800000 + // Position of SLC1_TX_ERR_EOF_INT_ST field. + SLC__1INT_ST_SLC1_TX_ERR_EOF_INT_ST_Pos = 0x18 + // Bit mask of SLC1_TX_ERR_EOF_INT_ST field. + SLC__1INT_ST_SLC1_TX_ERR_EOF_INT_ST_Msk = 0x1000000 + // Bit SLC1_TX_ERR_EOF_INT_ST. + SLC__1INT_ST_SLC1_TX_ERR_EOF_INT_ST = 0x1000000 + + // _1INT_ENA + // Position of FRHOST_BIT8_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT8_INT_ENA_Pos = 0x0 + // Bit mask of FRHOST_BIT8_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT8_INT_ENA_Msk = 0x1 + // Bit FRHOST_BIT8_INT_ENA. + SLC__1INT_ENA_FRHOST_BIT8_INT_ENA = 0x1 + // Position of FRHOST_BIT9_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT9_INT_ENA_Pos = 0x1 + // Bit mask of FRHOST_BIT9_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT9_INT_ENA_Msk = 0x2 + // Bit FRHOST_BIT9_INT_ENA. + SLC__1INT_ENA_FRHOST_BIT9_INT_ENA = 0x2 + // Position of FRHOST_BIT10_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT10_INT_ENA_Pos = 0x2 + // Bit mask of FRHOST_BIT10_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT10_INT_ENA_Msk = 0x4 + // Bit FRHOST_BIT10_INT_ENA. + SLC__1INT_ENA_FRHOST_BIT10_INT_ENA = 0x4 + // Position of FRHOST_BIT11_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT11_INT_ENA_Pos = 0x3 + // Bit mask of FRHOST_BIT11_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT11_INT_ENA_Msk = 0x8 + // Bit FRHOST_BIT11_INT_ENA. + SLC__1INT_ENA_FRHOST_BIT11_INT_ENA = 0x8 + // Position of FRHOST_BIT12_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT12_INT_ENA_Pos = 0x4 + // Bit mask of FRHOST_BIT12_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT12_INT_ENA_Msk = 0x10 + // Bit FRHOST_BIT12_INT_ENA. + SLC__1INT_ENA_FRHOST_BIT12_INT_ENA = 0x10 + // Position of FRHOST_BIT13_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT13_INT_ENA_Pos = 0x5 + // Bit mask of FRHOST_BIT13_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT13_INT_ENA_Msk = 0x20 + // Bit FRHOST_BIT13_INT_ENA. + SLC__1INT_ENA_FRHOST_BIT13_INT_ENA = 0x20 + // Position of FRHOST_BIT14_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT14_INT_ENA_Pos = 0x6 + // Bit mask of FRHOST_BIT14_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT14_INT_ENA_Msk = 0x40 + // Bit FRHOST_BIT14_INT_ENA. + SLC__1INT_ENA_FRHOST_BIT14_INT_ENA = 0x40 + // Position of FRHOST_BIT15_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT15_INT_ENA_Pos = 0x7 + // Bit mask of FRHOST_BIT15_INT_ENA field. + SLC__1INT_ENA_FRHOST_BIT15_INT_ENA_Msk = 0x80 + // Bit FRHOST_BIT15_INT_ENA. + SLC__1INT_ENA_FRHOST_BIT15_INT_ENA = 0x80 + // Position of SLC1_RX_START_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_START_INT_ENA_Pos = 0x8 + // Bit mask of SLC1_RX_START_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_START_INT_ENA_Msk = 0x100 + // Bit SLC1_RX_START_INT_ENA. + SLC__1INT_ENA_SLC1_RX_START_INT_ENA = 0x100 + // Position of SLC1_TX_START_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_START_INT_ENA_Pos = 0x9 + // Bit mask of SLC1_TX_START_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_START_INT_ENA_Msk = 0x200 + // Bit SLC1_TX_START_INT_ENA. + SLC__1INT_ENA_SLC1_TX_START_INT_ENA = 0x200 + // Position of SLC1_RX_UDF_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_UDF_INT_ENA_Pos = 0xa + // Bit mask of SLC1_RX_UDF_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_UDF_INT_ENA_Msk = 0x400 + // Bit SLC1_RX_UDF_INT_ENA. + SLC__1INT_ENA_SLC1_RX_UDF_INT_ENA = 0x400 + // Position of SLC1_TX_OVF_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_OVF_INT_ENA_Pos = 0xb + // Bit mask of SLC1_TX_OVF_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_OVF_INT_ENA_Msk = 0x800 + // Bit SLC1_TX_OVF_INT_ENA. + SLC__1INT_ENA_SLC1_TX_OVF_INT_ENA = 0x800 + // Position of SLC1_TOKEN0_1TO0_INT_ENA field. + SLC__1INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA_Pos = 0xc + // Bit mask of SLC1_TOKEN0_1TO0_INT_ENA field. + SLC__1INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA_Msk = 0x1000 + // Bit SLC1_TOKEN0_1TO0_INT_ENA. + SLC__1INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA = 0x1000 + // Position of SLC1_TOKEN1_1TO0_INT_ENA field. + SLC__1INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA_Pos = 0xd + // Bit mask of SLC1_TOKEN1_1TO0_INT_ENA field. + SLC__1INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA_Msk = 0x2000 + // Bit SLC1_TOKEN1_1TO0_INT_ENA. + SLC__1INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA = 0x2000 + // Position of SLC1_TX_DONE_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of SLC1_TX_DONE_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit SLC1_TX_DONE_INT_ENA. + SLC__1INT_ENA_SLC1_TX_DONE_INT_ENA = 0x4000 + // Position of SLC1_TX_SUC_EOF_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_SUC_EOF_INT_ENA_Pos = 0xf + // Bit mask of SLC1_TX_SUC_EOF_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_SUC_EOF_INT_ENA_Msk = 0x8000 + // Bit SLC1_TX_SUC_EOF_INT_ENA. + SLC__1INT_ENA_SLC1_TX_SUC_EOF_INT_ENA = 0x8000 + // Position of SLC1_RX_DONE_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_DONE_INT_ENA_Pos = 0x10 + // Bit mask of SLC1_RX_DONE_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_DONE_INT_ENA_Msk = 0x10000 + // Bit SLC1_RX_DONE_INT_ENA. + SLC__1INT_ENA_SLC1_RX_DONE_INT_ENA = 0x10000 + // Position of SLC1_RX_EOF_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_EOF_INT_ENA_Pos = 0x11 + // Bit mask of SLC1_RX_EOF_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_EOF_INT_ENA_Msk = 0x20000 + // Bit SLC1_RX_EOF_INT_ENA. + SLC__1INT_ENA_SLC1_RX_EOF_INT_ENA = 0x20000 + // Position of SLC1_TOHOST_INT_ENA field. + SLC__1INT_ENA_SLC1_TOHOST_INT_ENA_Pos = 0x12 + // Bit mask of SLC1_TOHOST_INT_ENA field. + SLC__1INT_ENA_SLC1_TOHOST_INT_ENA_Msk = 0x40000 + // Bit SLC1_TOHOST_INT_ENA. + SLC__1INT_ENA_SLC1_TOHOST_INT_ENA = 0x40000 + // Position of SLC1_TX_DSCR_ERR_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_DSCR_ERR_INT_ENA_Pos = 0x13 + // Bit mask of SLC1_TX_DSCR_ERR_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_DSCR_ERR_INT_ENA_Msk = 0x80000 + // Bit SLC1_TX_DSCR_ERR_INT_ENA. + SLC__1INT_ENA_SLC1_TX_DSCR_ERR_INT_ENA = 0x80000 + // Position of SLC1_RX_DSCR_ERR_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_DSCR_ERR_INT_ENA_Pos = 0x14 + // Bit mask of SLC1_RX_DSCR_ERR_INT_ENA field. + SLC__1INT_ENA_SLC1_RX_DSCR_ERR_INT_ENA_Msk = 0x100000 + // Bit SLC1_RX_DSCR_ERR_INT_ENA. + SLC__1INT_ENA_SLC1_RX_DSCR_ERR_INT_ENA = 0x100000 + // Position of SLC1_TX_DSCR_EMPTY_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_DSCR_EMPTY_INT_ENA_Pos = 0x15 + // Bit mask of SLC1_TX_DSCR_EMPTY_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_DSCR_EMPTY_INT_ENA_Msk = 0x200000 + // Bit SLC1_TX_DSCR_EMPTY_INT_ENA. + SLC__1INT_ENA_SLC1_TX_DSCR_EMPTY_INT_ENA = 0x200000 + // Position of SLC1_HOST_RD_ACK_INT_ENA field. + SLC__1INT_ENA_SLC1_HOST_RD_ACK_INT_ENA_Pos = 0x16 + // Bit mask of SLC1_HOST_RD_ACK_INT_ENA field. + SLC__1INT_ENA_SLC1_HOST_RD_ACK_INT_ENA_Msk = 0x400000 + // Bit SLC1_HOST_RD_ACK_INT_ENA. + SLC__1INT_ENA_SLC1_HOST_RD_ACK_INT_ENA = 0x400000 + // Position of SLC1_WR_RETRY_DONE_INT_ENA field. + SLC__1INT_ENA_SLC1_WR_RETRY_DONE_INT_ENA_Pos = 0x17 + // Bit mask of SLC1_WR_RETRY_DONE_INT_ENA field. + SLC__1INT_ENA_SLC1_WR_RETRY_DONE_INT_ENA_Msk = 0x800000 + // Bit SLC1_WR_RETRY_DONE_INT_ENA. + SLC__1INT_ENA_SLC1_WR_RETRY_DONE_INT_ENA = 0x800000 + // Position of SLC1_TX_ERR_EOF_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_ERR_EOF_INT_ENA_Pos = 0x18 + // Bit mask of SLC1_TX_ERR_EOF_INT_ENA field. + SLC__1INT_ENA_SLC1_TX_ERR_EOF_INT_ENA_Msk = 0x1000000 + // Bit SLC1_TX_ERR_EOF_INT_ENA. + SLC__1INT_ENA_SLC1_TX_ERR_EOF_INT_ENA = 0x1000000 + + // _1INT_CLR + // Position of FRHOST_BIT8_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT8_INT_CLR_Pos = 0x0 + // Bit mask of FRHOST_BIT8_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT8_INT_CLR_Msk = 0x1 + // Bit FRHOST_BIT8_INT_CLR. + SLC__1INT_CLR_FRHOST_BIT8_INT_CLR = 0x1 + // Position of FRHOST_BIT9_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT9_INT_CLR_Pos = 0x1 + // Bit mask of FRHOST_BIT9_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT9_INT_CLR_Msk = 0x2 + // Bit FRHOST_BIT9_INT_CLR. + SLC__1INT_CLR_FRHOST_BIT9_INT_CLR = 0x2 + // Position of FRHOST_BIT10_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT10_INT_CLR_Pos = 0x2 + // Bit mask of FRHOST_BIT10_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT10_INT_CLR_Msk = 0x4 + // Bit FRHOST_BIT10_INT_CLR. + SLC__1INT_CLR_FRHOST_BIT10_INT_CLR = 0x4 + // Position of FRHOST_BIT11_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT11_INT_CLR_Pos = 0x3 + // Bit mask of FRHOST_BIT11_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT11_INT_CLR_Msk = 0x8 + // Bit FRHOST_BIT11_INT_CLR. + SLC__1INT_CLR_FRHOST_BIT11_INT_CLR = 0x8 + // Position of FRHOST_BIT12_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT12_INT_CLR_Pos = 0x4 + // Bit mask of FRHOST_BIT12_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT12_INT_CLR_Msk = 0x10 + // Bit FRHOST_BIT12_INT_CLR. + SLC__1INT_CLR_FRHOST_BIT12_INT_CLR = 0x10 + // Position of FRHOST_BIT13_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT13_INT_CLR_Pos = 0x5 + // Bit mask of FRHOST_BIT13_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT13_INT_CLR_Msk = 0x20 + // Bit FRHOST_BIT13_INT_CLR. + SLC__1INT_CLR_FRHOST_BIT13_INT_CLR = 0x20 + // Position of FRHOST_BIT14_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT14_INT_CLR_Pos = 0x6 + // Bit mask of FRHOST_BIT14_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT14_INT_CLR_Msk = 0x40 + // Bit FRHOST_BIT14_INT_CLR. + SLC__1INT_CLR_FRHOST_BIT14_INT_CLR = 0x40 + // Position of FRHOST_BIT15_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT15_INT_CLR_Pos = 0x7 + // Bit mask of FRHOST_BIT15_INT_CLR field. + SLC__1INT_CLR_FRHOST_BIT15_INT_CLR_Msk = 0x80 + // Bit FRHOST_BIT15_INT_CLR. + SLC__1INT_CLR_FRHOST_BIT15_INT_CLR = 0x80 + // Position of SLC1_RX_START_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_START_INT_CLR_Pos = 0x8 + // Bit mask of SLC1_RX_START_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_START_INT_CLR_Msk = 0x100 + // Bit SLC1_RX_START_INT_CLR. + SLC__1INT_CLR_SLC1_RX_START_INT_CLR = 0x100 + // Position of SLC1_TX_START_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_START_INT_CLR_Pos = 0x9 + // Bit mask of SLC1_TX_START_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_START_INT_CLR_Msk = 0x200 + // Bit SLC1_TX_START_INT_CLR. + SLC__1INT_CLR_SLC1_TX_START_INT_CLR = 0x200 + // Position of SLC1_RX_UDF_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_UDF_INT_CLR_Pos = 0xa + // Bit mask of SLC1_RX_UDF_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_UDF_INT_CLR_Msk = 0x400 + // Bit SLC1_RX_UDF_INT_CLR. + SLC__1INT_CLR_SLC1_RX_UDF_INT_CLR = 0x400 + // Position of SLC1_TX_OVF_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_OVF_INT_CLR_Pos = 0xb + // Bit mask of SLC1_TX_OVF_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_OVF_INT_CLR_Msk = 0x800 + // Bit SLC1_TX_OVF_INT_CLR. + SLC__1INT_CLR_SLC1_TX_OVF_INT_CLR = 0x800 + // Position of SLC1_TOKEN0_1TO0_INT_CLR field. + SLC__1INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR_Pos = 0xc + // Bit mask of SLC1_TOKEN0_1TO0_INT_CLR field. + SLC__1INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR_Msk = 0x1000 + // Bit SLC1_TOKEN0_1TO0_INT_CLR. + SLC__1INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR = 0x1000 + // Position of SLC1_TOKEN1_1TO0_INT_CLR field. + SLC__1INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR_Pos = 0xd + // Bit mask of SLC1_TOKEN1_1TO0_INT_CLR field. + SLC__1INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR_Msk = 0x2000 + // Bit SLC1_TOKEN1_1TO0_INT_CLR. + SLC__1INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR = 0x2000 + // Position of SLC1_TX_DONE_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of SLC1_TX_DONE_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit SLC1_TX_DONE_INT_CLR. + SLC__1INT_CLR_SLC1_TX_DONE_INT_CLR = 0x4000 + // Position of SLC1_TX_SUC_EOF_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_SUC_EOF_INT_CLR_Pos = 0xf + // Bit mask of SLC1_TX_SUC_EOF_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_SUC_EOF_INT_CLR_Msk = 0x8000 + // Bit SLC1_TX_SUC_EOF_INT_CLR. + SLC__1INT_CLR_SLC1_TX_SUC_EOF_INT_CLR = 0x8000 + // Position of SLC1_RX_DONE_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_DONE_INT_CLR_Pos = 0x10 + // Bit mask of SLC1_RX_DONE_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_DONE_INT_CLR_Msk = 0x10000 + // Bit SLC1_RX_DONE_INT_CLR. + SLC__1INT_CLR_SLC1_RX_DONE_INT_CLR = 0x10000 + // Position of SLC1_RX_EOF_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_EOF_INT_CLR_Pos = 0x11 + // Bit mask of SLC1_RX_EOF_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_EOF_INT_CLR_Msk = 0x20000 + // Bit SLC1_RX_EOF_INT_CLR. + SLC__1INT_CLR_SLC1_RX_EOF_INT_CLR = 0x20000 + // Position of SLC1_TOHOST_INT_CLR field. + SLC__1INT_CLR_SLC1_TOHOST_INT_CLR_Pos = 0x12 + // Bit mask of SLC1_TOHOST_INT_CLR field. + SLC__1INT_CLR_SLC1_TOHOST_INT_CLR_Msk = 0x40000 + // Bit SLC1_TOHOST_INT_CLR. + SLC__1INT_CLR_SLC1_TOHOST_INT_CLR = 0x40000 + // Position of SLC1_TX_DSCR_ERR_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_DSCR_ERR_INT_CLR_Pos = 0x13 + // Bit mask of SLC1_TX_DSCR_ERR_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_DSCR_ERR_INT_CLR_Msk = 0x80000 + // Bit SLC1_TX_DSCR_ERR_INT_CLR. + SLC__1INT_CLR_SLC1_TX_DSCR_ERR_INT_CLR = 0x80000 + // Position of SLC1_RX_DSCR_ERR_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_DSCR_ERR_INT_CLR_Pos = 0x14 + // Bit mask of SLC1_RX_DSCR_ERR_INT_CLR field. + SLC__1INT_CLR_SLC1_RX_DSCR_ERR_INT_CLR_Msk = 0x100000 + // Bit SLC1_RX_DSCR_ERR_INT_CLR. + SLC__1INT_CLR_SLC1_RX_DSCR_ERR_INT_CLR = 0x100000 + // Position of SLC1_TX_DSCR_EMPTY_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_DSCR_EMPTY_INT_CLR_Pos = 0x15 + // Bit mask of SLC1_TX_DSCR_EMPTY_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_DSCR_EMPTY_INT_CLR_Msk = 0x200000 + // Bit SLC1_TX_DSCR_EMPTY_INT_CLR. + SLC__1INT_CLR_SLC1_TX_DSCR_EMPTY_INT_CLR = 0x200000 + // Position of SLC1_HOST_RD_ACK_INT_CLR field. + SLC__1INT_CLR_SLC1_HOST_RD_ACK_INT_CLR_Pos = 0x16 + // Bit mask of SLC1_HOST_RD_ACK_INT_CLR field. + SLC__1INT_CLR_SLC1_HOST_RD_ACK_INT_CLR_Msk = 0x400000 + // Bit SLC1_HOST_RD_ACK_INT_CLR. + SLC__1INT_CLR_SLC1_HOST_RD_ACK_INT_CLR = 0x400000 + // Position of SLC1_WR_RETRY_DONE_INT_CLR field. + SLC__1INT_CLR_SLC1_WR_RETRY_DONE_INT_CLR_Pos = 0x17 + // Bit mask of SLC1_WR_RETRY_DONE_INT_CLR field. + SLC__1INT_CLR_SLC1_WR_RETRY_DONE_INT_CLR_Msk = 0x800000 + // Bit SLC1_WR_RETRY_DONE_INT_CLR. + SLC__1INT_CLR_SLC1_WR_RETRY_DONE_INT_CLR = 0x800000 + // Position of SLC1_TX_ERR_EOF_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_ERR_EOF_INT_CLR_Pos = 0x18 + // Bit mask of SLC1_TX_ERR_EOF_INT_CLR field. + SLC__1INT_CLR_SLC1_TX_ERR_EOF_INT_CLR_Msk = 0x1000000 + // Bit SLC1_TX_ERR_EOF_INT_CLR. + SLC__1INT_CLR_SLC1_TX_ERR_EOF_INT_CLR = 0x1000000 + + // RX_STATUS + // Position of SLC0_RX_FULL field. + SLC_RX_STATUS_SLC0_RX_FULL_Pos = 0x0 + // Bit mask of SLC0_RX_FULL field. + SLC_RX_STATUS_SLC0_RX_FULL_Msk = 0x1 + // Bit SLC0_RX_FULL. + SLC_RX_STATUS_SLC0_RX_FULL = 0x1 + // Position of SLC0_RX_EMPTY field. + SLC_RX_STATUS_SLC0_RX_EMPTY_Pos = 0x1 + // Bit mask of SLC0_RX_EMPTY field. + SLC_RX_STATUS_SLC0_RX_EMPTY_Msk = 0x2 + // Bit SLC0_RX_EMPTY. + SLC_RX_STATUS_SLC0_RX_EMPTY = 0x2 + // Position of SLC1_RX_FULL field. + SLC_RX_STATUS_SLC1_RX_FULL_Pos = 0x10 + // Bit mask of SLC1_RX_FULL field. + SLC_RX_STATUS_SLC1_RX_FULL_Msk = 0x10000 + // Bit SLC1_RX_FULL. + SLC_RX_STATUS_SLC1_RX_FULL = 0x10000 + // Position of SLC1_RX_EMPTY field. + SLC_RX_STATUS_SLC1_RX_EMPTY_Pos = 0x11 + // Bit mask of SLC1_RX_EMPTY field. + SLC_RX_STATUS_SLC1_RX_EMPTY_Msk = 0x20000 + // Bit SLC1_RX_EMPTY. + SLC_RX_STATUS_SLC1_RX_EMPTY = 0x20000 + + // _0RXFIFO_PUSH + // Position of SLC0_RXFIFO_WDATA field. + SLC__0RXFIFO_PUSH_SLC0_RXFIFO_WDATA_Pos = 0x0 + // Bit mask of SLC0_RXFIFO_WDATA field. + SLC__0RXFIFO_PUSH_SLC0_RXFIFO_WDATA_Msk = 0x1ff + // Position of SLC0_RXFIFO_PUSH field. + SLC__0RXFIFO_PUSH_SLC0_RXFIFO_PUSH_Pos = 0x10 + // Bit mask of SLC0_RXFIFO_PUSH field. + SLC__0RXFIFO_PUSH_SLC0_RXFIFO_PUSH_Msk = 0x10000 + // Bit SLC0_RXFIFO_PUSH. + SLC__0RXFIFO_PUSH_SLC0_RXFIFO_PUSH = 0x10000 + + // _1RXFIFO_PUSH + // Position of SLC1_RXFIFO_WDATA field. + SLC__1RXFIFO_PUSH_SLC1_RXFIFO_WDATA_Pos = 0x0 + // Bit mask of SLC1_RXFIFO_WDATA field. + SLC__1RXFIFO_PUSH_SLC1_RXFIFO_WDATA_Msk = 0x1ff + // Position of SLC1_RXFIFO_PUSH field. + SLC__1RXFIFO_PUSH_SLC1_RXFIFO_PUSH_Pos = 0x10 + // Bit mask of SLC1_RXFIFO_PUSH field. + SLC__1RXFIFO_PUSH_SLC1_RXFIFO_PUSH_Msk = 0x10000 + // Bit SLC1_RXFIFO_PUSH. + SLC__1RXFIFO_PUSH_SLC1_RXFIFO_PUSH = 0x10000 + + // TX_STATUS + // Position of SLC0_TX_FULL field. + SLC_TX_STATUS_SLC0_TX_FULL_Pos = 0x0 + // Bit mask of SLC0_TX_FULL field. + SLC_TX_STATUS_SLC0_TX_FULL_Msk = 0x1 + // Bit SLC0_TX_FULL. + SLC_TX_STATUS_SLC0_TX_FULL = 0x1 + // Position of SLC0_TX_EMPTY field. + SLC_TX_STATUS_SLC0_TX_EMPTY_Pos = 0x1 + // Bit mask of SLC0_TX_EMPTY field. + SLC_TX_STATUS_SLC0_TX_EMPTY_Msk = 0x2 + // Bit SLC0_TX_EMPTY. + SLC_TX_STATUS_SLC0_TX_EMPTY = 0x2 + // Position of SLC1_TX_FULL field. + SLC_TX_STATUS_SLC1_TX_FULL_Pos = 0x10 + // Bit mask of SLC1_TX_FULL field. + SLC_TX_STATUS_SLC1_TX_FULL_Msk = 0x10000 + // Bit SLC1_TX_FULL. + SLC_TX_STATUS_SLC1_TX_FULL = 0x10000 + // Position of SLC1_TX_EMPTY field. + SLC_TX_STATUS_SLC1_TX_EMPTY_Pos = 0x11 + // Bit mask of SLC1_TX_EMPTY field. + SLC_TX_STATUS_SLC1_TX_EMPTY_Msk = 0x20000 + // Bit SLC1_TX_EMPTY. + SLC_TX_STATUS_SLC1_TX_EMPTY = 0x20000 + + // _0TXFIFO_POP + // Position of SLC0_TXFIFO_RDATA field. + SLC__0TXFIFO_POP_SLC0_TXFIFO_RDATA_Pos = 0x0 + // Bit mask of SLC0_TXFIFO_RDATA field. + SLC__0TXFIFO_POP_SLC0_TXFIFO_RDATA_Msk = 0x7ff + // Position of SLC0_TXFIFO_POP field. + SLC__0TXFIFO_POP_SLC0_TXFIFO_POP_Pos = 0x10 + // Bit mask of SLC0_TXFIFO_POP field. + SLC__0TXFIFO_POP_SLC0_TXFIFO_POP_Msk = 0x10000 + // Bit SLC0_TXFIFO_POP. + SLC__0TXFIFO_POP_SLC0_TXFIFO_POP = 0x10000 + + // _1TXFIFO_POP + // Position of SLC1_TXFIFO_RDATA field. + SLC__1TXFIFO_POP_SLC1_TXFIFO_RDATA_Pos = 0x0 + // Bit mask of SLC1_TXFIFO_RDATA field. + SLC__1TXFIFO_POP_SLC1_TXFIFO_RDATA_Msk = 0x7ff + // Position of SLC1_TXFIFO_POP field. + SLC__1TXFIFO_POP_SLC1_TXFIFO_POP_Pos = 0x10 + // Bit mask of SLC1_TXFIFO_POP field. + SLC__1TXFIFO_POP_SLC1_TXFIFO_POP_Msk = 0x10000 + // Bit SLC1_TXFIFO_POP. + SLC__1TXFIFO_POP_SLC1_TXFIFO_POP = 0x10000 + + // _0RX_LINK + // Position of SLC0_RXLINK_ADDR field. + SLC__0RX_LINK_SLC0_RXLINK_ADDR_Pos = 0x0 + // Bit mask of SLC0_RXLINK_ADDR field. + SLC__0RX_LINK_SLC0_RXLINK_ADDR_Msk = 0xfffff + // Position of SLC0_RXLINK_STOP field. + SLC__0RX_LINK_SLC0_RXLINK_STOP_Pos = 0x1c + // Bit mask of SLC0_RXLINK_STOP field. + SLC__0RX_LINK_SLC0_RXLINK_STOP_Msk = 0x10000000 + // Bit SLC0_RXLINK_STOP. + SLC__0RX_LINK_SLC0_RXLINK_STOP = 0x10000000 + // Position of SLC0_RXLINK_START field. + SLC__0RX_LINK_SLC0_RXLINK_START_Pos = 0x1d + // Bit mask of SLC0_RXLINK_START field. + SLC__0RX_LINK_SLC0_RXLINK_START_Msk = 0x20000000 + // Bit SLC0_RXLINK_START. + SLC__0RX_LINK_SLC0_RXLINK_START = 0x20000000 + // Position of SLC0_RXLINK_RESTART field. + SLC__0RX_LINK_SLC0_RXLINK_RESTART_Pos = 0x1e + // Bit mask of SLC0_RXLINK_RESTART field. + SLC__0RX_LINK_SLC0_RXLINK_RESTART_Msk = 0x40000000 + // Bit SLC0_RXLINK_RESTART. + SLC__0RX_LINK_SLC0_RXLINK_RESTART = 0x40000000 + // Position of SLC0_RXLINK_PARK field. + SLC__0RX_LINK_SLC0_RXLINK_PARK_Pos = 0x1f + // Bit mask of SLC0_RXLINK_PARK field. + SLC__0RX_LINK_SLC0_RXLINK_PARK_Msk = 0x80000000 + // Bit SLC0_RXLINK_PARK. + SLC__0RX_LINK_SLC0_RXLINK_PARK = 0x80000000 + + // _0TX_LINK + // Position of SLC0_TXLINK_ADDR field. + SLC__0TX_LINK_SLC0_TXLINK_ADDR_Pos = 0x0 + // Bit mask of SLC0_TXLINK_ADDR field. + SLC__0TX_LINK_SLC0_TXLINK_ADDR_Msk = 0xfffff + // Position of SLC0_TXLINK_STOP field. + SLC__0TX_LINK_SLC0_TXLINK_STOP_Pos = 0x1c + // Bit mask of SLC0_TXLINK_STOP field. + SLC__0TX_LINK_SLC0_TXLINK_STOP_Msk = 0x10000000 + // Bit SLC0_TXLINK_STOP. + SLC__0TX_LINK_SLC0_TXLINK_STOP = 0x10000000 + // Position of SLC0_TXLINK_START field. + SLC__0TX_LINK_SLC0_TXLINK_START_Pos = 0x1d + // Bit mask of SLC0_TXLINK_START field. + SLC__0TX_LINK_SLC0_TXLINK_START_Msk = 0x20000000 + // Bit SLC0_TXLINK_START. + SLC__0TX_LINK_SLC0_TXLINK_START = 0x20000000 + // Position of SLC0_TXLINK_RESTART field. + SLC__0TX_LINK_SLC0_TXLINK_RESTART_Pos = 0x1e + // Bit mask of SLC0_TXLINK_RESTART field. + SLC__0TX_LINK_SLC0_TXLINK_RESTART_Msk = 0x40000000 + // Bit SLC0_TXLINK_RESTART. + SLC__0TX_LINK_SLC0_TXLINK_RESTART = 0x40000000 + // Position of SLC0_TXLINK_PARK field. + SLC__0TX_LINK_SLC0_TXLINK_PARK_Pos = 0x1f + // Bit mask of SLC0_TXLINK_PARK field. + SLC__0TX_LINK_SLC0_TXLINK_PARK_Msk = 0x80000000 + // Bit SLC0_TXLINK_PARK. + SLC__0TX_LINK_SLC0_TXLINK_PARK = 0x80000000 + + // _1RX_LINK + // Position of SLC1_RXLINK_ADDR field. + SLC__1RX_LINK_SLC1_RXLINK_ADDR_Pos = 0x0 + // Bit mask of SLC1_RXLINK_ADDR field. + SLC__1RX_LINK_SLC1_RXLINK_ADDR_Msk = 0xfffff + // Position of SLC1_BT_PACKET field. + SLC__1RX_LINK_SLC1_BT_PACKET_Pos = 0x14 + // Bit mask of SLC1_BT_PACKET field. + SLC__1RX_LINK_SLC1_BT_PACKET_Msk = 0x100000 + // Bit SLC1_BT_PACKET. + SLC__1RX_LINK_SLC1_BT_PACKET = 0x100000 + // Position of SLC1_RXLINK_STOP field. + SLC__1RX_LINK_SLC1_RXLINK_STOP_Pos = 0x1c + // Bit mask of SLC1_RXLINK_STOP field. + SLC__1RX_LINK_SLC1_RXLINK_STOP_Msk = 0x10000000 + // Bit SLC1_RXLINK_STOP. + SLC__1RX_LINK_SLC1_RXLINK_STOP = 0x10000000 + // Position of SLC1_RXLINK_START field. + SLC__1RX_LINK_SLC1_RXLINK_START_Pos = 0x1d + // Bit mask of SLC1_RXLINK_START field. + SLC__1RX_LINK_SLC1_RXLINK_START_Msk = 0x20000000 + // Bit SLC1_RXLINK_START. + SLC__1RX_LINK_SLC1_RXLINK_START = 0x20000000 + // Position of SLC1_RXLINK_RESTART field. + SLC__1RX_LINK_SLC1_RXLINK_RESTART_Pos = 0x1e + // Bit mask of SLC1_RXLINK_RESTART field. + SLC__1RX_LINK_SLC1_RXLINK_RESTART_Msk = 0x40000000 + // Bit SLC1_RXLINK_RESTART. + SLC__1RX_LINK_SLC1_RXLINK_RESTART = 0x40000000 + // Position of SLC1_RXLINK_PARK field. + SLC__1RX_LINK_SLC1_RXLINK_PARK_Pos = 0x1f + // Bit mask of SLC1_RXLINK_PARK field. + SLC__1RX_LINK_SLC1_RXLINK_PARK_Msk = 0x80000000 + // Bit SLC1_RXLINK_PARK. + SLC__1RX_LINK_SLC1_RXLINK_PARK = 0x80000000 + + // _1TX_LINK + // Position of SLC1_TXLINK_ADDR field. + SLC__1TX_LINK_SLC1_TXLINK_ADDR_Pos = 0x0 + // Bit mask of SLC1_TXLINK_ADDR field. + SLC__1TX_LINK_SLC1_TXLINK_ADDR_Msk = 0xfffff + // Position of SLC1_TXLINK_STOP field. + SLC__1TX_LINK_SLC1_TXLINK_STOP_Pos = 0x1c + // Bit mask of SLC1_TXLINK_STOP field. + SLC__1TX_LINK_SLC1_TXLINK_STOP_Msk = 0x10000000 + // Bit SLC1_TXLINK_STOP. + SLC__1TX_LINK_SLC1_TXLINK_STOP = 0x10000000 + // Position of SLC1_TXLINK_START field. + SLC__1TX_LINK_SLC1_TXLINK_START_Pos = 0x1d + // Bit mask of SLC1_TXLINK_START field. + SLC__1TX_LINK_SLC1_TXLINK_START_Msk = 0x20000000 + // Bit SLC1_TXLINK_START. + SLC__1TX_LINK_SLC1_TXLINK_START = 0x20000000 + // Position of SLC1_TXLINK_RESTART field. + SLC__1TX_LINK_SLC1_TXLINK_RESTART_Pos = 0x1e + // Bit mask of SLC1_TXLINK_RESTART field. + SLC__1TX_LINK_SLC1_TXLINK_RESTART_Msk = 0x40000000 + // Bit SLC1_TXLINK_RESTART. + SLC__1TX_LINK_SLC1_TXLINK_RESTART = 0x40000000 + // Position of SLC1_TXLINK_PARK field. + SLC__1TX_LINK_SLC1_TXLINK_PARK_Pos = 0x1f + // Bit mask of SLC1_TXLINK_PARK field. + SLC__1TX_LINK_SLC1_TXLINK_PARK_Msk = 0x80000000 + // Bit SLC1_TXLINK_PARK. + SLC__1TX_LINK_SLC1_TXLINK_PARK = 0x80000000 + + // INTVEC_TOHOST + // Position of SLC0_TOHOST_INTVEC field. + SLC_INTVEC_TOHOST_SLC0_TOHOST_INTVEC_Pos = 0x0 + // Bit mask of SLC0_TOHOST_INTVEC field. + SLC_INTVEC_TOHOST_SLC0_TOHOST_INTVEC_Msk = 0xff + // Position of SLC1_TOHOST_INTVEC field. + SLC_INTVEC_TOHOST_SLC1_TOHOST_INTVEC_Pos = 0x10 + // Bit mask of SLC1_TOHOST_INTVEC field. + SLC_INTVEC_TOHOST_SLC1_TOHOST_INTVEC_Msk = 0xff0000 + + // _0TOKEN0 + // Position of SLC0_TOKEN0_WDATA field. + SLC__0TOKEN0_SLC0_TOKEN0_WDATA_Pos = 0x0 + // Bit mask of SLC0_TOKEN0_WDATA field. + SLC__0TOKEN0_SLC0_TOKEN0_WDATA_Msk = 0xfff + // Position of SLC0_TOKEN0_WR field. + SLC__0TOKEN0_SLC0_TOKEN0_WR_Pos = 0xc + // Bit mask of SLC0_TOKEN0_WR field. + SLC__0TOKEN0_SLC0_TOKEN0_WR_Msk = 0x1000 + // Bit SLC0_TOKEN0_WR. + SLC__0TOKEN0_SLC0_TOKEN0_WR = 0x1000 + // Position of SLC0_TOKEN0_INC field. + SLC__0TOKEN0_SLC0_TOKEN0_INC_Pos = 0xd + // Bit mask of SLC0_TOKEN0_INC field. + SLC__0TOKEN0_SLC0_TOKEN0_INC_Msk = 0x2000 + // Bit SLC0_TOKEN0_INC. + SLC__0TOKEN0_SLC0_TOKEN0_INC = 0x2000 + // Position of SLC0_TOKEN0_INC_MORE field. + SLC__0TOKEN0_SLC0_TOKEN0_INC_MORE_Pos = 0xe + // Bit mask of SLC0_TOKEN0_INC_MORE field. + SLC__0TOKEN0_SLC0_TOKEN0_INC_MORE_Msk = 0x4000 + // Bit SLC0_TOKEN0_INC_MORE. + SLC__0TOKEN0_SLC0_TOKEN0_INC_MORE = 0x4000 + // Position of SLC0_TOKEN0 field. + SLC__0TOKEN0_SLC0_TOKEN0_Pos = 0x10 + // Bit mask of SLC0_TOKEN0 field. + SLC__0TOKEN0_SLC0_TOKEN0_Msk = 0xfff0000 + + // _0TOKEN1 + // Position of SLC0_TOKEN1_WDATA field. + SLC__0TOKEN1_SLC0_TOKEN1_WDATA_Pos = 0x0 + // Bit mask of SLC0_TOKEN1_WDATA field. + SLC__0TOKEN1_SLC0_TOKEN1_WDATA_Msk = 0xfff + // Position of SLC0_TOKEN1_WR field. + SLC__0TOKEN1_SLC0_TOKEN1_WR_Pos = 0xc + // Bit mask of SLC0_TOKEN1_WR field. + SLC__0TOKEN1_SLC0_TOKEN1_WR_Msk = 0x1000 + // Bit SLC0_TOKEN1_WR. + SLC__0TOKEN1_SLC0_TOKEN1_WR = 0x1000 + // Position of SLC0_TOKEN1_INC field. + SLC__0TOKEN1_SLC0_TOKEN1_INC_Pos = 0xd + // Bit mask of SLC0_TOKEN1_INC field. + SLC__0TOKEN1_SLC0_TOKEN1_INC_Msk = 0x2000 + // Bit SLC0_TOKEN1_INC. + SLC__0TOKEN1_SLC0_TOKEN1_INC = 0x2000 + // Position of SLC0_TOKEN1_INC_MORE field. + SLC__0TOKEN1_SLC0_TOKEN1_INC_MORE_Pos = 0xe + // Bit mask of SLC0_TOKEN1_INC_MORE field. + SLC__0TOKEN1_SLC0_TOKEN1_INC_MORE_Msk = 0x4000 + // Bit SLC0_TOKEN1_INC_MORE. + SLC__0TOKEN1_SLC0_TOKEN1_INC_MORE = 0x4000 + // Position of SLC0_TOKEN1 field. + SLC__0TOKEN1_SLC0_TOKEN1_Pos = 0x10 + // Bit mask of SLC0_TOKEN1 field. + SLC__0TOKEN1_SLC0_TOKEN1_Msk = 0xfff0000 + + // _1TOKEN0 + // Position of SLC1_TOKEN0_WDATA field. + SLC__1TOKEN0_SLC1_TOKEN0_WDATA_Pos = 0x0 + // Bit mask of SLC1_TOKEN0_WDATA field. + SLC__1TOKEN0_SLC1_TOKEN0_WDATA_Msk = 0xfff + // Position of SLC1_TOKEN0_WR field. + SLC__1TOKEN0_SLC1_TOKEN0_WR_Pos = 0xc + // Bit mask of SLC1_TOKEN0_WR field. + SLC__1TOKEN0_SLC1_TOKEN0_WR_Msk = 0x1000 + // Bit SLC1_TOKEN0_WR. + SLC__1TOKEN0_SLC1_TOKEN0_WR = 0x1000 + // Position of SLC1_TOKEN0_INC field. + SLC__1TOKEN0_SLC1_TOKEN0_INC_Pos = 0xd + // Bit mask of SLC1_TOKEN0_INC field. + SLC__1TOKEN0_SLC1_TOKEN0_INC_Msk = 0x2000 + // Bit SLC1_TOKEN0_INC. + SLC__1TOKEN0_SLC1_TOKEN0_INC = 0x2000 + // Position of SLC1_TOKEN0_INC_MORE field. + SLC__1TOKEN0_SLC1_TOKEN0_INC_MORE_Pos = 0xe + // Bit mask of SLC1_TOKEN0_INC_MORE field. + SLC__1TOKEN0_SLC1_TOKEN0_INC_MORE_Msk = 0x4000 + // Bit SLC1_TOKEN0_INC_MORE. + SLC__1TOKEN0_SLC1_TOKEN0_INC_MORE = 0x4000 + // Position of SLC1_TOKEN0 field. + SLC__1TOKEN0_SLC1_TOKEN0_Pos = 0x10 + // Bit mask of SLC1_TOKEN0 field. + SLC__1TOKEN0_SLC1_TOKEN0_Msk = 0xfff0000 + + // _1TOKEN1 + // Position of SLC1_TOKEN1_WDATA field. + SLC__1TOKEN1_SLC1_TOKEN1_WDATA_Pos = 0x0 + // Bit mask of SLC1_TOKEN1_WDATA field. + SLC__1TOKEN1_SLC1_TOKEN1_WDATA_Msk = 0xfff + // Position of SLC1_TOKEN1_WR field. + SLC__1TOKEN1_SLC1_TOKEN1_WR_Pos = 0xc + // Bit mask of SLC1_TOKEN1_WR field. + SLC__1TOKEN1_SLC1_TOKEN1_WR_Msk = 0x1000 + // Bit SLC1_TOKEN1_WR. + SLC__1TOKEN1_SLC1_TOKEN1_WR = 0x1000 + // Position of SLC1_TOKEN1_INC field. + SLC__1TOKEN1_SLC1_TOKEN1_INC_Pos = 0xd + // Bit mask of SLC1_TOKEN1_INC field. + SLC__1TOKEN1_SLC1_TOKEN1_INC_Msk = 0x2000 + // Bit SLC1_TOKEN1_INC. + SLC__1TOKEN1_SLC1_TOKEN1_INC = 0x2000 + // Position of SLC1_TOKEN1_INC_MORE field. + SLC__1TOKEN1_SLC1_TOKEN1_INC_MORE_Pos = 0xe + // Bit mask of SLC1_TOKEN1_INC_MORE field. + SLC__1TOKEN1_SLC1_TOKEN1_INC_MORE_Msk = 0x4000 + // Bit SLC1_TOKEN1_INC_MORE. + SLC__1TOKEN1_SLC1_TOKEN1_INC_MORE = 0x4000 + // Position of SLC1_TOKEN1 field. + SLC__1TOKEN1_SLC1_TOKEN1_Pos = 0x10 + // Bit mask of SLC1_TOKEN1 field. + SLC__1TOKEN1_SLC1_TOKEN1_Msk = 0xfff0000 + + // CONF1 + // Position of SLC0_CHECK_OWNER field. + SLC_CONF1_SLC0_CHECK_OWNER_Pos = 0x0 + // Bit mask of SLC0_CHECK_OWNER field. + SLC_CONF1_SLC0_CHECK_OWNER_Msk = 0x1 + // Bit SLC0_CHECK_OWNER. + SLC_CONF1_SLC0_CHECK_OWNER = 0x1 + // Position of SLC0_TX_CHECK_SUM_EN field. + SLC_CONF1_SLC0_TX_CHECK_SUM_EN_Pos = 0x1 + // Bit mask of SLC0_TX_CHECK_SUM_EN field. + SLC_CONF1_SLC0_TX_CHECK_SUM_EN_Msk = 0x2 + // Bit SLC0_TX_CHECK_SUM_EN. + SLC_CONF1_SLC0_TX_CHECK_SUM_EN = 0x2 + // Position of SLC0_RX_CHECK_SUM_EN field. + SLC_CONF1_SLC0_RX_CHECK_SUM_EN_Pos = 0x2 + // Bit mask of SLC0_RX_CHECK_SUM_EN field. + SLC_CONF1_SLC0_RX_CHECK_SUM_EN_Msk = 0x4 + // Bit SLC0_RX_CHECK_SUM_EN. + SLC_CONF1_SLC0_RX_CHECK_SUM_EN = 0x4 + // Position of CMD_HOLD_EN field. + SLC_CONF1_CMD_HOLD_EN_Pos = 0x3 + // Bit mask of CMD_HOLD_EN field. + SLC_CONF1_CMD_HOLD_EN_Msk = 0x8 + // Bit CMD_HOLD_EN. + SLC_CONF1_CMD_HOLD_EN = 0x8 + // Position of SLC0_LEN_AUTO_CLR field. + SLC_CONF1_SLC0_LEN_AUTO_CLR_Pos = 0x4 + // Bit mask of SLC0_LEN_AUTO_CLR field. + SLC_CONF1_SLC0_LEN_AUTO_CLR_Msk = 0x10 + // Bit SLC0_LEN_AUTO_CLR. + SLC_CONF1_SLC0_LEN_AUTO_CLR = 0x10 + // Position of SLC0_TX_STITCH_EN field. + SLC_CONF1_SLC0_TX_STITCH_EN_Pos = 0x5 + // Bit mask of SLC0_TX_STITCH_EN field. + SLC_CONF1_SLC0_TX_STITCH_EN_Msk = 0x20 + // Bit SLC0_TX_STITCH_EN. + SLC_CONF1_SLC0_TX_STITCH_EN = 0x20 + // Position of SLC0_RX_STITCH_EN field. + SLC_CONF1_SLC0_RX_STITCH_EN_Pos = 0x6 + // Bit mask of SLC0_RX_STITCH_EN field. + SLC_CONF1_SLC0_RX_STITCH_EN_Msk = 0x40 + // Bit SLC0_RX_STITCH_EN. + SLC_CONF1_SLC0_RX_STITCH_EN = 0x40 + // Position of SLC1_CHECK_OWNER field. + SLC_CONF1_SLC1_CHECK_OWNER_Pos = 0x10 + // Bit mask of SLC1_CHECK_OWNER field. + SLC_CONF1_SLC1_CHECK_OWNER_Msk = 0x10000 + // Bit SLC1_CHECK_OWNER. + SLC_CONF1_SLC1_CHECK_OWNER = 0x10000 + // Position of SLC1_TX_CHECK_SUM_EN field. + SLC_CONF1_SLC1_TX_CHECK_SUM_EN_Pos = 0x11 + // Bit mask of SLC1_TX_CHECK_SUM_EN field. + SLC_CONF1_SLC1_TX_CHECK_SUM_EN_Msk = 0x20000 + // Bit SLC1_TX_CHECK_SUM_EN. + SLC_CONF1_SLC1_TX_CHECK_SUM_EN = 0x20000 + // Position of SLC1_RX_CHECK_SUM_EN field. + SLC_CONF1_SLC1_RX_CHECK_SUM_EN_Pos = 0x12 + // Bit mask of SLC1_RX_CHECK_SUM_EN field. + SLC_CONF1_SLC1_RX_CHECK_SUM_EN_Msk = 0x40000 + // Bit SLC1_RX_CHECK_SUM_EN. + SLC_CONF1_SLC1_RX_CHECK_SUM_EN = 0x40000 + // Position of HOST_INT_LEVEL_SEL field. + SLC_CONF1_HOST_INT_LEVEL_SEL_Pos = 0x13 + // Bit mask of HOST_INT_LEVEL_SEL field. + SLC_CONF1_HOST_INT_LEVEL_SEL_Msk = 0x80000 + // Bit HOST_INT_LEVEL_SEL. + SLC_CONF1_HOST_INT_LEVEL_SEL = 0x80000 + // Position of SLC1_TX_STITCH_EN field. + SLC_CONF1_SLC1_TX_STITCH_EN_Pos = 0x14 + // Bit mask of SLC1_TX_STITCH_EN field. + SLC_CONF1_SLC1_TX_STITCH_EN_Msk = 0x100000 + // Bit SLC1_TX_STITCH_EN. + SLC_CONF1_SLC1_TX_STITCH_EN = 0x100000 + // Position of SLC1_RX_STITCH_EN field. + SLC_CONF1_SLC1_RX_STITCH_EN_Pos = 0x15 + // Bit mask of SLC1_RX_STITCH_EN field. + SLC_CONF1_SLC1_RX_STITCH_EN_Msk = 0x200000 + // Bit SLC1_RX_STITCH_EN. + SLC_CONF1_SLC1_RX_STITCH_EN = 0x200000 + // Position of CLK_EN field. + SLC_CONF1_CLK_EN_Pos = 0x16 + // Bit mask of CLK_EN field. + SLC_CONF1_CLK_EN_Msk = 0x400000 + // Bit CLK_EN. + SLC_CONF1_CLK_EN = 0x400000 + + // _0_STATE0 + // Position of SLC0_STATE0 field. + SLC__0_STATE0_SLC0_STATE0_Pos = 0x0 + // Bit mask of SLC0_STATE0 field. + SLC__0_STATE0_SLC0_STATE0_Msk = 0xffffffff + + // _0_STATE1 + // Position of SLC0_STATE1 field. + SLC__0_STATE1_SLC0_STATE1_Pos = 0x0 + // Bit mask of SLC0_STATE1 field. + SLC__0_STATE1_SLC0_STATE1_Msk = 0xffffffff + + // _1_STATE0 + // Position of SLC1_STATE0 field. + SLC__1_STATE0_SLC1_STATE0_Pos = 0x0 + // Bit mask of SLC1_STATE0 field. + SLC__1_STATE0_SLC1_STATE0_Msk = 0xffffffff + + // _1_STATE1 + // Position of SLC1_STATE1 field. + SLC__1_STATE1_SLC1_STATE1_Pos = 0x0 + // Bit mask of SLC1_STATE1 field. + SLC__1_STATE1_SLC1_STATE1_Msk = 0xffffffff + + // BRIDGE_CONF + // Position of TXEOF_ENA field. + SLC_BRIDGE_CONF_TXEOF_ENA_Pos = 0x0 + // Bit mask of TXEOF_ENA field. + SLC_BRIDGE_CONF_TXEOF_ENA_Msk = 0x3f + // Position of FIFO_MAP_ENA field. + SLC_BRIDGE_CONF_FIFO_MAP_ENA_Pos = 0x8 + // Bit mask of FIFO_MAP_ENA field. + SLC_BRIDGE_CONF_FIFO_MAP_ENA_Msk = 0xf00 + // Position of SLC0_TX_DUMMY_MODE field. + SLC_BRIDGE_CONF_SLC0_TX_DUMMY_MODE_Pos = 0xc + // Bit mask of SLC0_TX_DUMMY_MODE field. + SLC_BRIDGE_CONF_SLC0_TX_DUMMY_MODE_Msk = 0x1000 + // Bit SLC0_TX_DUMMY_MODE. + SLC_BRIDGE_CONF_SLC0_TX_DUMMY_MODE = 0x1000 + // Position of HDA_MAP_128K field. + SLC_BRIDGE_CONF_HDA_MAP_128K_Pos = 0xd + // Bit mask of HDA_MAP_128K field. + SLC_BRIDGE_CONF_HDA_MAP_128K_Msk = 0x2000 + // Bit HDA_MAP_128K. + SLC_BRIDGE_CONF_HDA_MAP_128K = 0x2000 + // Position of SLC1_TX_DUMMY_MODE field. + SLC_BRIDGE_CONF_SLC1_TX_DUMMY_MODE_Pos = 0xe + // Bit mask of SLC1_TX_DUMMY_MODE field. + SLC_BRIDGE_CONF_SLC1_TX_DUMMY_MODE_Msk = 0x4000 + // Bit SLC1_TX_DUMMY_MODE. + SLC_BRIDGE_CONF_SLC1_TX_DUMMY_MODE = 0x4000 + // Position of TX_PUSH_IDLE_NUM field. + SLC_BRIDGE_CONF_TX_PUSH_IDLE_NUM_Pos = 0x10 + // Bit mask of TX_PUSH_IDLE_NUM field. + SLC_BRIDGE_CONF_TX_PUSH_IDLE_NUM_Msk = 0xffff0000 + + // _0_TO_EOF_DES_ADDR + // Position of SLC0_TO_EOF_DES_ADDR field. + SLC__0_TO_EOF_DES_ADDR_SLC0_TO_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of SLC0_TO_EOF_DES_ADDR field. + SLC__0_TO_EOF_DES_ADDR_SLC0_TO_EOF_DES_ADDR_Msk = 0xffffffff + + // _0_TX_EOF_DES_ADDR + // Position of SLC0_TX_SUC_EOF_DES_ADDR field. + SLC__0_TX_EOF_DES_ADDR_SLC0_TX_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of SLC0_TX_SUC_EOF_DES_ADDR field. + SLC__0_TX_EOF_DES_ADDR_SLC0_TX_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // _0_TO_EOF_BFR_DES_ADDR + // Position of SLC0_TO_EOF_BFR_DES_ADDR field. + SLC__0_TO_EOF_BFR_DES_ADDR_SLC0_TO_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of SLC0_TO_EOF_BFR_DES_ADDR field. + SLC__0_TO_EOF_BFR_DES_ADDR_SLC0_TO_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // _1_TO_EOF_DES_ADDR + // Position of SLC1_TO_EOF_DES_ADDR field. + SLC__1_TO_EOF_DES_ADDR_SLC1_TO_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of SLC1_TO_EOF_DES_ADDR field. + SLC__1_TO_EOF_DES_ADDR_SLC1_TO_EOF_DES_ADDR_Msk = 0xffffffff + + // _1_TX_EOF_DES_ADDR + // Position of SLC1_TX_SUC_EOF_DES_ADDR field. + SLC__1_TX_EOF_DES_ADDR_SLC1_TX_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of SLC1_TX_SUC_EOF_DES_ADDR field. + SLC__1_TX_EOF_DES_ADDR_SLC1_TX_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // _1_TO_EOF_BFR_DES_ADDR + // Position of SLC1_TO_EOF_BFR_DES_ADDR field. + SLC__1_TO_EOF_BFR_DES_ADDR_SLC1_TO_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of SLC1_TO_EOF_BFR_DES_ADDR field. + SLC__1_TO_EOF_BFR_DES_ADDR_SLC1_TO_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // AHB_TEST + // Position of AHB_TESTMODE field. + SLC_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + SLC_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + SLC_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + SLC_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // SDIO_ST + // Position of CMD_ST field. + SLC_SDIO_ST_CMD_ST_Pos = 0x0 + // Bit mask of CMD_ST field. + SLC_SDIO_ST_CMD_ST_Msk = 0x7 + // Position of FUNC_ST field. + SLC_SDIO_ST_FUNC_ST_Pos = 0x4 + // Bit mask of FUNC_ST field. + SLC_SDIO_ST_FUNC_ST_Msk = 0xf0 + // Position of SDIO_WAKEUP field. + SLC_SDIO_ST_SDIO_WAKEUP_Pos = 0x8 + // Bit mask of SDIO_WAKEUP field. + SLC_SDIO_ST_SDIO_WAKEUP_Msk = 0x100 + // Bit SDIO_WAKEUP. + SLC_SDIO_ST_SDIO_WAKEUP = 0x100 + // Position of BUS_ST field. + SLC_SDIO_ST_BUS_ST_Pos = 0xc + // Bit mask of BUS_ST field. + SLC_SDIO_ST_BUS_ST_Msk = 0x7000 + // Position of FUNC1_ACC_STATE field. + SLC_SDIO_ST_FUNC1_ACC_STATE_Pos = 0x10 + // Bit mask of FUNC1_ACC_STATE field. + SLC_SDIO_ST_FUNC1_ACC_STATE_Msk = 0x1f0000 + // Position of FUNC2_ACC_STATE field. + SLC_SDIO_ST_FUNC2_ACC_STATE_Pos = 0x18 + // Bit mask of FUNC2_ACC_STATE field. + SLC_SDIO_ST_FUNC2_ACC_STATE_Msk = 0x1f000000 + + // RX_DSCR_CONF + // Position of SLC0_TOKEN_NO_REPLACE field. + SLC_RX_DSCR_CONF_SLC0_TOKEN_NO_REPLACE_Pos = 0x0 + // Bit mask of SLC0_TOKEN_NO_REPLACE field. + SLC_RX_DSCR_CONF_SLC0_TOKEN_NO_REPLACE_Msk = 0x1 + // Bit SLC0_TOKEN_NO_REPLACE. + SLC_RX_DSCR_CONF_SLC0_TOKEN_NO_REPLACE = 0x1 + // Position of SLC0_INFOR_NO_REPLACE field. + SLC_RX_DSCR_CONF_SLC0_INFOR_NO_REPLACE_Pos = 0x1 + // Bit mask of SLC0_INFOR_NO_REPLACE field. + SLC_RX_DSCR_CONF_SLC0_INFOR_NO_REPLACE_Msk = 0x2 + // Bit SLC0_INFOR_NO_REPLACE. + SLC_RX_DSCR_CONF_SLC0_INFOR_NO_REPLACE = 0x2 + // Position of SLC0_RX_FILL_MODE field. + SLC_RX_DSCR_CONF_SLC0_RX_FILL_MODE_Pos = 0x2 + // Bit mask of SLC0_RX_FILL_MODE field. + SLC_RX_DSCR_CONF_SLC0_RX_FILL_MODE_Msk = 0x4 + // Bit SLC0_RX_FILL_MODE. + SLC_RX_DSCR_CONF_SLC0_RX_FILL_MODE = 0x4 + // Position of SLC0_RX_EOF_MODE field. + SLC_RX_DSCR_CONF_SLC0_RX_EOF_MODE_Pos = 0x3 + // Bit mask of SLC0_RX_EOF_MODE field. + SLC_RX_DSCR_CONF_SLC0_RX_EOF_MODE_Msk = 0x8 + // Bit SLC0_RX_EOF_MODE. + SLC_RX_DSCR_CONF_SLC0_RX_EOF_MODE = 0x8 + // Position of SLC0_RX_FILL_EN field. + SLC_RX_DSCR_CONF_SLC0_RX_FILL_EN_Pos = 0x4 + // Bit mask of SLC0_RX_FILL_EN field. + SLC_RX_DSCR_CONF_SLC0_RX_FILL_EN_Msk = 0x10 + // Bit SLC0_RX_FILL_EN. + SLC_RX_DSCR_CONF_SLC0_RX_FILL_EN = 0x10 + // Position of SLC0_RD_RETRY_THRESHOLD field. + SLC_RX_DSCR_CONF_SLC0_RD_RETRY_THRESHOLD_Pos = 0x5 + // Bit mask of SLC0_RD_RETRY_THRESHOLD field. + SLC_RX_DSCR_CONF_SLC0_RD_RETRY_THRESHOLD_Msk = 0xffe0 + // Position of SLC1_TOKEN_NO_REPLACE field. + SLC_RX_DSCR_CONF_SLC1_TOKEN_NO_REPLACE_Pos = 0x10 + // Bit mask of SLC1_TOKEN_NO_REPLACE field. + SLC_RX_DSCR_CONF_SLC1_TOKEN_NO_REPLACE_Msk = 0x10000 + // Bit SLC1_TOKEN_NO_REPLACE. + SLC_RX_DSCR_CONF_SLC1_TOKEN_NO_REPLACE = 0x10000 + // Position of SLC1_INFOR_NO_REPLACE field. + SLC_RX_DSCR_CONF_SLC1_INFOR_NO_REPLACE_Pos = 0x11 + // Bit mask of SLC1_INFOR_NO_REPLACE field. + SLC_RX_DSCR_CONF_SLC1_INFOR_NO_REPLACE_Msk = 0x20000 + // Bit SLC1_INFOR_NO_REPLACE. + SLC_RX_DSCR_CONF_SLC1_INFOR_NO_REPLACE = 0x20000 + // Position of SLC1_RX_FILL_MODE field. + SLC_RX_DSCR_CONF_SLC1_RX_FILL_MODE_Pos = 0x12 + // Bit mask of SLC1_RX_FILL_MODE field. + SLC_RX_DSCR_CONF_SLC1_RX_FILL_MODE_Msk = 0x40000 + // Bit SLC1_RX_FILL_MODE. + SLC_RX_DSCR_CONF_SLC1_RX_FILL_MODE = 0x40000 + // Position of SLC1_RX_EOF_MODE field. + SLC_RX_DSCR_CONF_SLC1_RX_EOF_MODE_Pos = 0x13 + // Bit mask of SLC1_RX_EOF_MODE field. + SLC_RX_DSCR_CONF_SLC1_RX_EOF_MODE_Msk = 0x80000 + // Bit SLC1_RX_EOF_MODE. + SLC_RX_DSCR_CONF_SLC1_RX_EOF_MODE = 0x80000 + // Position of SLC1_RX_FILL_EN field. + SLC_RX_DSCR_CONF_SLC1_RX_FILL_EN_Pos = 0x14 + // Bit mask of SLC1_RX_FILL_EN field. + SLC_RX_DSCR_CONF_SLC1_RX_FILL_EN_Msk = 0x100000 + // Bit SLC1_RX_FILL_EN. + SLC_RX_DSCR_CONF_SLC1_RX_FILL_EN = 0x100000 + // Position of SLC1_RD_RETRY_THRESHOLD field. + SLC_RX_DSCR_CONF_SLC1_RD_RETRY_THRESHOLD_Pos = 0x15 + // Bit mask of SLC1_RD_RETRY_THRESHOLD field. + SLC_RX_DSCR_CONF_SLC1_RD_RETRY_THRESHOLD_Msk = 0xffe00000 + + // _0_TXLINK_DSCR + // Position of SLC0_TXLINK_DSCR field. + SLC__0_TXLINK_DSCR_SLC0_TXLINK_DSCR_Pos = 0x0 + // Bit mask of SLC0_TXLINK_DSCR field. + SLC__0_TXLINK_DSCR_SLC0_TXLINK_DSCR_Msk = 0xffffffff + + // _0_TXLINK_DSCR_BF0 + // Position of SLC0_TXLINK_DSCR_BF0 field. + SLC__0_TXLINK_DSCR_BF0_SLC0_TXLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of SLC0_TXLINK_DSCR_BF0 field. + SLC__0_TXLINK_DSCR_BF0_SLC0_TXLINK_DSCR_BF0_Msk = 0xffffffff + + // _0_TXLINK_DSCR_BF1 + // Position of SLC0_TXLINK_DSCR_BF1 field. + SLC__0_TXLINK_DSCR_BF1_SLC0_TXLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of SLC0_TXLINK_DSCR_BF1 field. + SLC__0_TXLINK_DSCR_BF1_SLC0_TXLINK_DSCR_BF1_Msk = 0xffffffff + + // _0_RXLINK_DSCR + // Position of SLC0_RXLINK_DSCR field. + SLC__0_RXLINK_DSCR_SLC0_RXLINK_DSCR_Pos = 0x0 + // Bit mask of SLC0_RXLINK_DSCR field. + SLC__0_RXLINK_DSCR_SLC0_RXLINK_DSCR_Msk = 0xffffffff + + // _0_RXLINK_DSCR_BF0 + // Position of SLC0_RXLINK_DSCR_BF0 field. + SLC__0_RXLINK_DSCR_BF0_SLC0_RXLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of SLC0_RXLINK_DSCR_BF0 field. + SLC__0_RXLINK_DSCR_BF0_SLC0_RXLINK_DSCR_BF0_Msk = 0xffffffff + + // _0_RXLINK_DSCR_BF1 + // Position of SLC0_RXLINK_DSCR_BF1 field. + SLC__0_RXLINK_DSCR_BF1_SLC0_RXLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of SLC0_RXLINK_DSCR_BF1 field. + SLC__0_RXLINK_DSCR_BF1_SLC0_RXLINK_DSCR_BF1_Msk = 0xffffffff + + // _1_TXLINK_DSCR + // Position of SLC1_TXLINK_DSCR field. + SLC__1_TXLINK_DSCR_SLC1_TXLINK_DSCR_Pos = 0x0 + // Bit mask of SLC1_TXLINK_DSCR field. + SLC__1_TXLINK_DSCR_SLC1_TXLINK_DSCR_Msk = 0xffffffff + + // _1_TXLINK_DSCR_BF0 + // Position of SLC1_TXLINK_DSCR_BF0 field. + SLC__1_TXLINK_DSCR_BF0_SLC1_TXLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of SLC1_TXLINK_DSCR_BF0 field. + SLC__1_TXLINK_DSCR_BF0_SLC1_TXLINK_DSCR_BF0_Msk = 0xffffffff + + // _1_TXLINK_DSCR_BF1 + // Position of SLC1_TXLINK_DSCR_BF1 field. + SLC__1_TXLINK_DSCR_BF1_SLC1_TXLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of SLC1_TXLINK_DSCR_BF1 field. + SLC__1_TXLINK_DSCR_BF1_SLC1_TXLINK_DSCR_BF1_Msk = 0xffffffff + + // _1_RXLINK_DSCR + // Position of SLC1_RXLINK_DSCR field. + SLC__1_RXLINK_DSCR_SLC1_RXLINK_DSCR_Pos = 0x0 + // Bit mask of SLC1_RXLINK_DSCR field. + SLC__1_RXLINK_DSCR_SLC1_RXLINK_DSCR_Msk = 0xffffffff + + // _1_RXLINK_DSCR_BF0 + // Position of SLC1_RXLINK_DSCR_BF0 field. + SLC__1_RXLINK_DSCR_BF0_SLC1_RXLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of SLC1_RXLINK_DSCR_BF0 field. + SLC__1_RXLINK_DSCR_BF0_SLC1_RXLINK_DSCR_BF0_Msk = 0xffffffff + + // _1_RXLINK_DSCR_BF1 + // Position of SLC1_RXLINK_DSCR_BF1 field. + SLC__1_RXLINK_DSCR_BF1_SLC1_RXLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of SLC1_RXLINK_DSCR_BF1 field. + SLC__1_RXLINK_DSCR_BF1_SLC1_RXLINK_DSCR_BF1_Msk = 0xffffffff + + // _0_TX_ERREOF_DES_ADDR + // Position of SLC0_TX_ERR_EOF_DES_ADDR field. + SLC__0_TX_ERREOF_DES_ADDR_SLC0_TX_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of SLC0_TX_ERR_EOF_DES_ADDR field. + SLC__0_TX_ERREOF_DES_ADDR_SLC0_TX_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // _1_TX_ERREOF_DES_ADDR + // Position of SLC1_TX_ERR_EOF_DES_ADDR field. + SLC__1_TX_ERREOF_DES_ADDR_SLC1_TX_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of SLC1_TX_ERR_EOF_DES_ADDR field. + SLC__1_TX_ERREOF_DES_ADDR_SLC1_TX_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // TOKEN_LAT + // Position of SLC0_TOKEN field. + SLC_TOKEN_LAT_SLC0_TOKEN_Pos = 0x0 + // Bit mask of SLC0_TOKEN field. + SLC_TOKEN_LAT_SLC0_TOKEN_Msk = 0xfff + // Position of SLC1_TOKEN field. + SLC_TOKEN_LAT_SLC1_TOKEN_Pos = 0x10 + // Bit mask of SLC1_TOKEN field. + SLC_TOKEN_LAT_SLC1_TOKEN_Msk = 0xfff0000 + + // TX_DSCR_CONF + // Position of WR_RETRY_THRESHOLD field. + SLC_TX_DSCR_CONF_WR_RETRY_THRESHOLD_Pos = 0x0 + // Bit mask of WR_RETRY_THRESHOLD field. + SLC_TX_DSCR_CONF_WR_RETRY_THRESHOLD_Msk = 0x7ff + + // CMD_INFOR0 + // Position of CMD_CONTENT0 field. + SLC_CMD_INFOR0_CMD_CONTENT0_Pos = 0x0 + // Bit mask of CMD_CONTENT0 field. + SLC_CMD_INFOR0_CMD_CONTENT0_Msk = 0xffffffff + + // CMD_INFOR1 + // Position of CMD_CONTENT1 field. + SLC_CMD_INFOR1_CMD_CONTENT1_Pos = 0x0 + // Bit mask of CMD_CONTENT1 field. + SLC_CMD_INFOR1_CMD_CONTENT1_Msk = 0xffffffff + + // _0_LEN_CONF + // Position of SLC0_LEN_WDATA field. + SLC__0_LEN_CONF_SLC0_LEN_WDATA_Pos = 0x0 + // Bit mask of SLC0_LEN_WDATA field. + SLC__0_LEN_CONF_SLC0_LEN_WDATA_Msk = 0xfffff + // Position of SLC0_LEN_WR field. + SLC__0_LEN_CONF_SLC0_LEN_WR_Pos = 0x14 + // Bit mask of SLC0_LEN_WR field. + SLC__0_LEN_CONF_SLC0_LEN_WR_Msk = 0x100000 + // Bit SLC0_LEN_WR. + SLC__0_LEN_CONF_SLC0_LEN_WR = 0x100000 + // Position of SLC0_LEN_INC field. + SLC__0_LEN_CONF_SLC0_LEN_INC_Pos = 0x15 + // Bit mask of SLC0_LEN_INC field. + SLC__0_LEN_CONF_SLC0_LEN_INC_Msk = 0x200000 + // Bit SLC0_LEN_INC. + SLC__0_LEN_CONF_SLC0_LEN_INC = 0x200000 + // Position of SLC0_LEN_INC_MORE field. + SLC__0_LEN_CONF_SLC0_LEN_INC_MORE_Pos = 0x16 + // Bit mask of SLC0_LEN_INC_MORE field. + SLC__0_LEN_CONF_SLC0_LEN_INC_MORE_Msk = 0x400000 + // Bit SLC0_LEN_INC_MORE. + SLC__0_LEN_CONF_SLC0_LEN_INC_MORE = 0x400000 + // Position of SLC0_RX_PACKET_LOAD_EN field. + SLC__0_LEN_CONF_SLC0_RX_PACKET_LOAD_EN_Pos = 0x17 + // Bit mask of SLC0_RX_PACKET_LOAD_EN field. + SLC__0_LEN_CONF_SLC0_RX_PACKET_LOAD_EN_Msk = 0x800000 + // Bit SLC0_RX_PACKET_LOAD_EN. + SLC__0_LEN_CONF_SLC0_RX_PACKET_LOAD_EN = 0x800000 + // Position of SLC0_TX_PACKET_LOAD_EN field. + SLC__0_LEN_CONF_SLC0_TX_PACKET_LOAD_EN_Pos = 0x18 + // Bit mask of SLC0_TX_PACKET_LOAD_EN field. + SLC__0_LEN_CONF_SLC0_TX_PACKET_LOAD_EN_Msk = 0x1000000 + // Bit SLC0_TX_PACKET_LOAD_EN. + SLC__0_LEN_CONF_SLC0_TX_PACKET_LOAD_EN = 0x1000000 + // Position of SLC0_RX_GET_USED_DSCR field. + SLC__0_LEN_CONF_SLC0_RX_GET_USED_DSCR_Pos = 0x19 + // Bit mask of SLC0_RX_GET_USED_DSCR field. + SLC__0_LEN_CONF_SLC0_RX_GET_USED_DSCR_Msk = 0x2000000 + // Bit SLC0_RX_GET_USED_DSCR. + SLC__0_LEN_CONF_SLC0_RX_GET_USED_DSCR = 0x2000000 + // Position of SLC0_TX_GET_USED_DSCR field. + SLC__0_LEN_CONF_SLC0_TX_GET_USED_DSCR_Pos = 0x1a + // Bit mask of SLC0_TX_GET_USED_DSCR field. + SLC__0_LEN_CONF_SLC0_TX_GET_USED_DSCR_Msk = 0x4000000 + // Bit SLC0_TX_GET_USED_DSCR. + SLC__0_LEN_CONF_SLC0_TX_GET_USED_DSCR = 0x4000000 + // Position of SLC0_RX_NEW_PKT_IND field. + SLC__0_LEN_CONF_SLC0_RX_NEW_PKT_IND_Pos = 0x1b + // Bit mask of SLC0_RX_NEW_PKT_IND field. + SLC__0_LEN_CONF_SLC0_RX_NEW_PKT_IND_Msk = 0x8000000 + // Bit SLC0_RX_NEW_PKT_IND. + SLC__0_LEN_CONF_SLC0_RX_NEW_PKT_IND = 0x8000000 + // Position of SLC0_TX_NEW_PKT_IND field. + SLC__0_LEN_CONF_SLC0_TX_NEW_PKT_IND_Pos = 0x1c + // Bit mask of SLC0_TX_NEW_PKT_IND field. + SLC__0_LEN_CONF_SLC0_TX_NEW_PKT_IND_Msk = 0x10000000 + // Bit SLC0_TX_NEW_PKT_IND. + SLC__0_LEN_CONF_SLC0_TX_NEW_PKT_IND = 0x10000000 + + // _0_LENGTH + // Position of SLC0_LEN field. + SLC__0_LENGTH_SLC0_LEN_Pos = 0x0 + // Bit mask of SLC0_LEN field. + SLC__0_LENGTH_SLC0_LEN_Msk = 0xfffff + + // _0_TXPKT_H_DSCR + // Position of SLC0_TX_PKT_H_DSCR_ADDR field. + SLC__0_TXPKT_H_DSCR_SLC0_TX_PKT_H_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_TX_PKT_H_DSCR_ADDR field. + SLC__0_TXPKT_H_DSCR_SLC0_TX_PKT_H_DSCR_ADDR_Msk = 0xffffffff + + // _0_TXPKT_E_DSCR + // Position of SLC0_TX_PKT_E_DSCR_ADDR field. + SLC__0_TXPKT_E_DSCR_SLC0_TX_PKT_E_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_TX_PKT_E_DSCR_ADDR field. + SLC__0_TXPKT_E_DSCR_SLC0_TX_PKT_E_DSCR_ADDR_Msk = 0xffffffff + + // _0_RXPKT_H_DSCR + // Position of SLC0_RX_PKT_H_DSCR_ADDR field. + SLC__0_RXPKT_H_DSCR_SLC0_RX_PKT_H_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_RX_PKT_H_DSCR_ADDR field. + SLC__0_RXPKT_H_DSCR_SLC0_RX_PKT_H_DSCR_ADDR_Msk = 0xffffffff + + // _0_RXPKT_E_DSCR + // Position of SLC0_RX_PKT_E_DSCR_ADDR field. + SLC__0_RXPKT_E_DSCR_SLC0_RX_PKT_E_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_RX_PKT_E_DSCR_ADDR field. + SLC__0_RXPKT_E_DSCR_SLC0_RX_PKT_E_DSCR_ADDR_Msk = 0xffffffff + + // _0_TXPKTU_H_DSCR + // Position of SLC0_TX_PKT_START_DSCR_ADDR field. + SLC__0_TXPKTU_H_DSCR_SLC0_TX_PKT_START_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_TX_PKT_START_DSCR_ADDR field. + SLC__0_TXPKTU_H_DSCR_SLC0_TX_PKT_START_DSCR_ADDR_Msk = 0xffffffff + + // _0_TXPKTU_E_DSCR + // Position of SLC0_TX_PKT_END_DSCR_ADDR field. + SLC__0_TXPKTU_E_DSCR_SLC0_TX_PKT_END_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_TX_PKT_END_DSCR_ADDR field. + SLC__0_TXPKTU_E_DSCR_SLC0_TX_PKT_END_DSCR_ADDR_Msk = 0xffffffff + + // _0_RXPKTU_H_DSCR + // Position of SLC0_RX_PKT_START_DSCR_ADDR field. + SLC__0_RXPKTU_H_DSCR_SLC0_RX_PKT_START_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_RX_PKT_START_DSCR_ADDR field. + SLC__0_RXPKTU_H_DSCR_SLC0_RX_PKT_START_DSCR_ADDR_Msk = 0xffffffff + + // _0_RXPKTU_E_DSCR + // Position of SLC0_RX_PKT_END_DSCR_ADDR field. + SLC__0_RXPKTU_E_DSCR_SLC0_RX_PKT_END_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_RX_PKT_END_DSCR_ADDR field. + SLC__0_RXPKTU_E_DSCR_SLC0_RX_PKT_END_DSCR_ADDR_Msk = 0xffffffff + + // SEQ_POSITION + // Position of SLC0_SEQ_POSITION field. + SLC_SEQ_POSITION_SLC0_SEQ_POSITION_Pos = 0x0 + // Bit mask of SLC0_SEQ_POSITION field. + SLC_SEQ_POSITION_SLC0_SEQ_POSITION_Msk = 0xff + // Position of SLC1_SEQ_POSITION field. + SLC_SEQ_POSITION_SLC1_SEQ_POSITION_Pos = 0x8 + // Bit mask of SLC1_SEQ_POSITION field. + SLC_SEQ_POSITION_SLC1_SEQ_POSITION_Msk = 0xff00 + + // _0_DSCR_REC_CONF + // Position of SLC0_RX_DSCR_REC_LIM field. + SLC__0_DSCR_REC_CONF_SLC0_RX_DSCR_REC_LIM_Pos = 0x0 + // Bit mask of SLC0_RX_DSCR_REC_LIM field. + SLC__0_DSCR_REC_CONF_SLC0_RX_DSCR_REC_LIM_Msk = 0x3ff + + // SDIO_CRC_ST0 + // Position of DAT0_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST0_DAT0_CRC_ERR_CNT_Pos = 0x0 + // Bit mask of DAT0_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST0_DAT0_CRC_ERR_CNT_Msk = 0xff + // Position of DAT1_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST0_DAT1_CRC_ERR_CNT_Pos = 0x8 + // Bit mask of DAT1_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST0_DAT1_CRC_ERR_CNT_Msk = 0xff00 + // Position of DAT2_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST0_DAT2_CRC_ERR_CNT_Pos = 0x10 + // Bit mask of DAT2_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST0_DAT2_CRC_ERR_CNT_Msk = 0xff0000 + // Position of DAT3_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST0_DAT3_CRC_ERR_CNT_Pos = 0x18 + // Bit mask of DAT3_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST0_DAT3_CRC_ERR_CNT_Msk = 0xff000000 + + // SDIO_CRC_ST1 + // Position of CMD_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST1_CMD_CRC_ERR_CNT_Pos = 0x0 + // Bit mask of CMD_CRC_ERR_CNT field. + SLC_SDIO_CRC_ST1_CMD_CRC_ERR_CNT_Msk = 0xff + // Position of ERR_CNT_CLR field. + SLC_SDIO_CRC_ST1_ERR_CNT_CLR_Pos = 0x1f + // Bit mask of ERR_CNT_CLR field. + SLC_SDIO_CRC_ST1_ERR_CNT_CLR_Msk = 0x80000000 + // Bit ERR_CNT_CLR. + SLC_SDIO_CRC_ST1_ERR_CNT_CLR = 0x80000000 + + // _0_EOF_START_DES + // Position of SLC0_EOF_START_DES_ADDR field. + SLC__0_EOF_START_DES_SLC0_EOF_START_DES_ADDR_Pos = 0x0 + // Bit mask of SLC0_EOF_START_DES_ADDR field. + SLC__0_EOF_START_DES_SLC0_EOF_START_DES_ADDR_Msk = 0xffffffff + + // _0_PUSH_DSCR_ADDR + // Position of SLC0_RX_PUSH_DSCR_ADDR field. + SLC__0_PUSH_DSCR_ADDR_SLC0_RX_PUSH_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_RX_PUSH_DSCR_ADDR field. + SLC__0_PUSH_DSCR_ADDR_SLC0_RX_PUSH_DSCR_ADDR_Msk = 0xffffffff + + // _0_DONE_DSCR_ADDR + // Position of SLC0_RX_DONE_DSCR_ADDR field. + SLC__0_DONE_DSCR_ADDR_SLC0_RX_DONE_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_RX_DONE_DSCR_ADDR field. + SLC__0_DONE_DSCR_ADDR_SLC0_RX_DONE_DSCR_ADDR_Msk = 0xffffffff + + // _0_SUB_START_DES + // Position of SLC0_SUB_PAC_START_DSCR_ADDR field. + SLC__0_SUB_START_DES_SLC0_SUB_PAC_START_DSCR_ADDR_Pos = 0x0 + // Bit mask of SLC0_SUB_PAC_START_DSCR_ADDR field. + SLC__0_SUB_START_DES_SLC0_SUB_PAC_START_DSCR_ADDR_Msk = 0xffffffff + + // _0_DSCR_CNT + // Position of SLC0_RX_DSCR_CNT_LAT field. + SLC__0_DSCR_CNT_SLC0_RX_DSCR_CNT_LAT_Pos = 0x0 + // Bit mask of SLC0_RX_DSCR_CNT_LAT field. + SLC__0_DSCR_CNT_SLC0_RX_DSCR_CNT_LAT_Msk = 0x3ff + // Position of SLC0_RX_GET_EOF_OCC field. + SLC__0_DSCR_CNT_SLC0_RX_GET_EOF_OCC_Pos = 0x10 + // Bit mask of SLC0_RX_GET_EOF_OCC field. + SLC__0_DSCR_CNT_SLC0_RX_GET_EOF_OCC_Msk = 0x10000 + // Bit SLC0_RX_GET_EOF_OCC. + SLC__0_DSCR_CNT_SLC0_RX_GET_EOF_OCC = 0x10000 + + // _0_LEN_LIM_CONF + // Position of SLC0_LEN_LIM field. + SLC__0_LEN_LIM_CONF_SLC0_LEN_LIM_Pos = 0x0 + // Bit mask of SLC0_LEN_LIM field. + SLC__0_LEN_LIM_CONF_SLC0_LEN_LIM_Msk = 0xfffff + + // _0INT_ST1 + // Position of FRHOST_BIT0_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT0_INT_ST1_Pos = 0x0 + // Bit mask of FRHOST_BIT0_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT0_INT_ST1_Msk = 0x1 + // Bit FRHOST_BIT0_INT_ST1. + SLC__0INT_ST1_FRHOST_BIT0_INT_ST1 = 0x1 + // Position of FRHOST_BIT1_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT1_INT_ST1_Pos = 0x1 + // Bit mask of FRHOST_BIT1_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT1_INT_ST1_Msk = 0x2 + // Bit FRHOST_BIT1_INT_ST1. + SLC__0INT_ST1_FRHOST_BIT1_INT_ST1 = 0x2 + // Position of FRHOST_BIT2_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT2_INT_ST1_Pos = 0x2 + // Bit mask of FRHOST_BIT2_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT2_INT_ST1_Msk = 0x4 + // Bit FRHOST_BIT2_INT_ST1. + SLC__0INT_ST1_FRHOST_BIT2_INT_ST1 = 0x4 + // Position of FRHOST_BIT3_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT3_INT_ST1_Pos = 0x3 + // Bit mask of FRHOST_BIT3_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT3_INT_ST1_Msk = 0x8 + // Bit FRHOST_BIT3_INT_ST1. + SLC__0INT_ST1_FRHOST_BIT3_INT_ST1 = 0x8 + // Position of FRHOST_BIT4_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT4_INT_ST1_Pos = 0x4 + // Bit mask of FRHOST_BIT4_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT4_INT_ST1_Msk = 0x10 + // Bit FRHOST_BIT4_INT_ST1. + SLC__0INT_ST1_FRHOST_BIT4_INT_ST1 = 0x10 + // Position of FRHOST_BIT5_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT5_INT_ST1_Pos = 0x5 + // Bit mask of FRHOST_BIT5_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT5_INT_ST1_Msk = 0x20 + // Bit FRHOST_BIT5_INT_ST1. + SLC__0INT_ST1_FRHOST_BIT5_INT_ST1 = 0x20 + // Position of FRHOST_BIT6_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT6_INT_ST1_Pos = 0x6 + // Bit mask of FRHOST_BIT6_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT6_INT_ST1_Msk = 0x40 + // Bit FRHOST_BIT6_INT_ST1. + SLC__0INT_ST1_FRHOST_BIT6_INT_ST1 = 0x40 + // Position of FRHOST_BIT7_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT7_INT_ST1_Pos = 0x7 + // Bit mask of FRHOST_BIT7_INT_ST1 field. + SLC__0INT_ST1_FRHOST_BIT7_INT_ST1_Msk = 0x80 + // Bit FRHOST_BIT7_INT_ST1. + SLC__0INT_ST1_FRHOST_BIT7_INT_ST1 = 0x80 + // Position of SLC0_RX_START_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_START_INT_ST1_Pos = 0x8 + // Bit mask of SLC0_RX_START_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_START_INT_ST1_Msk = 0x100 + // Bit SLC0_RX_START_INT_ST1. + SLC__0INT_ST1_SLC0_RX_START_INT_ST1 = 0x100 + // Position of SLC0_TX_START_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_START_INT_ST1_Pos = 0x9 + // Bit mask of SLC0_TX_START_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_START_INT_ST1_Msk = 0x200 + // Bit SLC0_TX_START_INT_ST1. + SLC__0INT_ST1_SLC0_TX_START_INT_ST1 = 0x200 + // Position of SLC0_RX_UDF_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_UDF_INT_ST1_Pos = 0xa + // Bit mask of SLC0_RX_UDF_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_UDF_INT_ST1_Msk = 0x400 + // Bit SLC0_RX_UDF_INT_ST1. + SLC__0INT_ST1_SLC0_RX_UDF_INT_ST1 = 0x400 + // Position of SLC0_TX_OVF_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_OVF_INT_ST1_Pos = 0xb + // Bit mask of SLC0_TX_OVF_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_OVF_INT_ST1_Msk = 0x800 + // Bit SLC0_TX_OVF_INT_ST1. + SLC__0INT_ST1_SLC0_TX_OVF_INT_ST1 = 0x800 + // Position of SLC0_TOKEN0_1TO0_INT_ST1 field. + SLC__0INT_ST1_SLC0_TOKEN0_1TO0_INT_ST1_Pos = 0xc + // Bit mask of SLC0_TOKEN0_1TO0_INT_ST1 field. + SLC__0INT_ST1_SLC0_TOKEN0_1TO0_INT_ST1_Msk = 0x1000 + // Bit SLC0_TOKEN0_1TO0_INT_ST1. + SLC__0INT_ST1_SLC0_TOKEN0_1TO0_INT_ST1 = 0x1000 + // Position of SLC0_TOKEN1_1TO0_INT_ST1 field. + SLC__0INT_ST1_SLC0_TOKEN1_1TO0_INT_ST1_Pos = 0xd + // Bit mask of SLC0_TOKEN1_1TO0_INT_ST1 field. + SLC__0INT_ST1_SLC0_TOKEN1_1TO0_INT_ST1_Msk = 0x2000 + // Bit SLC0_TOKEN1_1TO0_INT_ST1. + SLC__0INT_ST1_SLC0_TOKEN1_1TO0_INT_ST1 = 0x2000 + // Position of SLC0_TX_DONE_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_DONE_INT_ST1_Pos = 0xe + // Bit mask of SLC0_TX_DONE_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_DONE_INT_ST1_Msk = 0x4000 + // Bit SLC0_TX_DONE_INT_ST1. + SLC__0INT_ST1_SLC0_TX_DONE_INT_ST1 = 0x4000 + // Position of SLC0_TX_SUC_EOF_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_SUC_EOF_INT_ST1_Pos = 0xf + // Bit mask of SLC0_TX_SUC_EOF_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_SUC_EOF_INT_ST1_Msk = 0x8000 + // Bit SLC0_TX_SUC_EOF_INT_ST1. + SLC__0INT_ST1_SLC0_TX_SUC_EOF_INT_ST1 = 0x8000 + // Position of SLC0_RX_DONE_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_DONE_INT_ST1_Pos = 0x10 + // Bit mask of SLC0_RX_DONE_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_DONE_INT_ST1_Msk = 0x10000 + // Bit SLC0_RX_DONE_INT_ST1. + SLC__0INT_ST1_SLC0_RX_DONE_INT_ST1 = 0x10000 + // Position of SLC0_RX_EOF_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_EOF_INT_ST1_Pos = 0x11 + // Bit mask of SLC0_RX_EOF_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_EOF_INT_ST1_Msk = 0x20000 + // Bit SLC0_RX_EOF_INT_ST1. + SLC__0INT_ST1_SLC0_RX_EOF_INT_ST1 = 0x20000 + // Position of SLC0_TOHOST_INT_ST1 field. + SLC__0INT_ST1_SLC0_TOHOST_INT_ST1_Pos = 0x12 + // Bit mask of SLC0_TOHOST_INT_ST1 field. + SLC__0INT_ST1_SLC0_TOHOST_INT_ST1_Msk = 0x40000 + // Bit SLC0_TOHOST_INT_ST1. + SLC__0INT_ST1_SLC0_TOHOST_INT_ST1 = 0x40000 + // Position of SLC0_TX_DSCR_ERR_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_DSCR_ERR_INT_ST1_Pos = 0x13 + // Bit mask of SLC0_TX_DSCR_ERR_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_DSCR_ERR_INT_ST1_Msk = 0x80000 + // Bit SLC0_TX_DSCR_ERR_INT_ST1. + SLC__0INT_ST1_SLC0_TX_DSCR_ERR_INT_ST1 = 0x80000 + // Position of SLC0_RX_DSCR_ERR_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_DSCR_ERR_INT_ST1_Pos = 0x14 + // Bit mask of SLC0_RX_DSCR_ERR_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_DSCR_ERR_INT_ST1_Msk = 0x100000 + // Bit SLC0_RX_DSCR_ERR_INT_ST1. + SLC__0INT_ST1_SLC0_RX_DSCR_ERR_INT_ST1 = 0x100000 + // Position of SLC0_TX_DSCR_EMPTY_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_DSCR_EMPTY_INT_ST1_Pos = 0x15 + // Bit mask of SLC0_TX_DSCR_EMPTY_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_DSCR_EMPTY_INT_ST1_Msk = 0x200000 + // Bit SLC0_TX_DSCR_EMPTY_INT_ST1. + SLC__0INT_ST1_SLC0_TX_DSCR_EMPTY_INT_ST1 = 0x200000 + // Position of SLC0_HOST_RD_ACK_INT_ST1 field. + SLC__0INT_ST1_SLC0_HOST_RD_ACK_INT_ST1_Pos = 0x16 + // Bit mask of SLC0_HOST_RD_ACK_INT_ST1 field. + SLC__0INT_ST1_SLC0_HOST_RD_ACK_INT_ST1_Msk = 0x400000 + // Bit SLC0_HOST_RD_ACK_INT_ST1. + SLC__0INT_ST1_SLC0_HOST_RD_ACK_INT_ST1 = 0x400000 + // Position of SLC0_WR_RETRY_DONE_INT_ST1 field. + SLC__0INT_ST1_SLC0_WR_RETRY_DONE_INT_ST1_Pos = 0x17 + // Bit mask of SLC0_WR_RETRY_DONE_INT_ST1 field. + SLC__0INT_ST1_SLC0_WR_RETRY_DONE_INT_ST1_Msk = 0x800000 + // Bit SLC0_WR_RETRY_DONE_INT_ST1. + SLC__0INT_ST1_SLC0_WR_RETRY_DONE_INT_ST1 = 0x800000 + // Position of SLC0_TX_ERR_EOF_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_ERR_EOF_INT_ST1_Pos = 0x18 + // Bit mask of SLC0_TX_ERR_EOF_INT_ST1 field. + SLC__0INT_ST1_SLC0_TX_ERR_EOF_INT_ST1_Msk = 0x1000000 + // Bit SLC0_TX_ERR_EOF_INT_ST1. + SLC__0INT_ST1_SLC0_TX_ERR_EOF_INT_ST1 = 0x1000000 + // Position of CMD_DTC_INT_ST1 field. + SLC__0INT_ST1_CMD_DTC_INT_ST1_Pos = 0x19 + // Bit mask of CMD_DTC_INT_ST1 field. + SLC__0INT_ST1_CMD_DTC_INT_ST1_Msk = 0x2000000 + // Bit CMD_DTC_INT_ST1. + SLC__0INT_ST1_CMD_DTC_INT_ST1 = 0x2000000 + // Position of SLC0_RX_QUICK_EOF_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_QUICK_EOF_INT_ST1_Pos = 0x1a + // Bit mask of SLC0_RX_QUICK_EOF_INT_ST1 field. + SLC__0INT_ST1_SLC0_RX_QUICK_EOF_INT_ST1_Msk = 0x4000000 + // Bit SLC0_RX_QUICK_EOF_INT_ST1. + SLC__0INT_ST1_SLC0_RX_QUICK_EOF_INT_ST1 = 0x4000000 + + // _0INT_ENA1 + // Position of FRHOST_BIT0_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT0_INT_ENA1_Pos = 0x0 + // Bit mask of FRHOST_BIT0_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT0_INT_ENA1_Msk = 0x1 + // Bit FRHOST_BIT0_INT_ENA1. + SLC__0INT_ENA1_FRHOST_BIT0_INT_ENA1 = 0x1 + // Position of FRHOST_BIT1_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT1_INT_ENA1_Pos = 0x1 + // Bit mask of FRHOST_BIT1_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT1_INT_ENA1_Msk = 0x2 + // Bit FRHOST_BIT1_INT_ENA1. + SLC__0INT_ENA1_FRHOST_BIT1_INT_ENA1 = 0x2 + // Position of FRHOST_BIT2_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT2_INT_ENA1_Pos = 0x2 + // Bit mask of FRHOST_BIT2_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT2_INT_ENA1_Msk = 0x4 + // Bit FRHOST_BIT2_INT_ENA1. + SLC__0INT_ENA1_FRHOST_BIT2_INT_ENA1 = 0x4 + // Position of FRHOST_BIT3_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT3_INT_ENA1_Pos = 0x3 + // Bit mask of FRHOST_BIT3_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT3_INT_ENA1_Msk = 0x8 + // Bit FRHOST_BIT3_INT_ENA1. + SLC__0INT_ENA1_FRHOST_BIT3_INT_ENA1 = 0x8 + // Position of FRHOST_BIT4_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT4_INT_ENA1_Pos = 0x4 + // Bit mask of FRHOST_BIT4_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT4_INT_ENA1_Msk = 0x10 + // Bit FRHOST_BIT4_INT_ENA1. + SLC__0INT_ENA1_FRHOST_BIT4_INT_ENA1 = 0x10 + // Position of FRHOST_BIT5_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT5_INT_ENA1_Pos = 0x5 + // Bit mask of FRHOST_BIT5_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT5_INT_ENA1_Msk = 0x20 + // Bit FRHOST_BIT5_INT_ENA1. + SLC__0INT_ENA1_FRHOST_BIT5_INT_ENA1 = 0x20 + // Position of FRHOST_BIT6_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT6_INT_ENA1_Pos = 0x6 + // Bit mask of FRHOST_BIT6_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT6_INT_ENA1_Msk = 0x40 + // Bit FRHOST_BIT6_INT_ENA1. + SLC__0INT_ENA1_FRHOST_BIT6_INT_ENA1 = 0x40 + // Position of FRHOST_BIT7_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT7_INT_ENA1_Pos = 0x7 + // Bit mask of FRHOST_BIT7_INT_ENA1 field. + SLC__0INT_ENA1_FRHOST_BIT7_INT_ENA1_Msk = 0x80 + // Bit FRHOST_BIT7_INT_ENA1. + SLC__0INT_ENA1_FRHOST_BIT7_INT_ENA1 = 0x80 + // Position of SLC0_RX_START_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_START_INT_ENA1_Pos = 0x8 + // Bit mask of SLC0_RX_START_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_START_INT_ENA1_Msk = 0x100 + // Bit SLC0_RX_START_INT_ENA1. + SLC__0INT_ENA1_SLC0_RX_START_INT_ENA1 = 0x100 + // Position of SLC0_TX_START_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_START_INT_ENA1_Pos = 0x9 + // Bit mask of SLC0_TX_START_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_START_INT_ENA1_Msk = 0x200 + // Bit SLC0_TX_START_INT_ENA1. + SLC__0INT_ENA1_SLC0_TX_START_INT_ENA1 = 0x200 + // Position of SLC0_RX_UDF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_UDF_INT_ENA1_Pos = 0xa + // Bit mask of SLC0_RX_UDF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_UDF_INT_ENA1_Msk = 0x400 + // Bit SLC0_RX_UDF_INT_ENA1. + SLC__0INT_ENA1_SLC0_RX_UDF_INT_ENA1 = 0x400 + // Position of SLC0_TX_OVF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_OVF_INT_ENA1_Pos = 0xb + // Bit mask of SLC0_TX_OVF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_OVF_INT_ENA1_Msk = 0x800 + // Bit SLC0_TX_OVF_INT_ENA1. + SLC__0INT_ENA1_SLC0_TX_OVF_INT_ENA1 = 0x800 + // Position of SLC0_TOKEN0_1TO0_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1_Pos = 0xc + // Bit mask of SLC0_TOKEN0_1TO0_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1_Msk = 0x1000 + // Bit SLC0_TOKEN0_1TO0_INT_ENA1. + SLC__0INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1 = 0x1000 + // Position of SLC0_TOKEN1_1TO0_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1_Pos = 0xd + // Bit mask of SLC0_TOKEN1_1TO0_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1_Msk = 0x2000 + // Bit SLC0_TOKEN1_1TO0_INT_ENA1. + SLC__0INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1 = 0x2000 + // Position of SLC0_TX_DONE_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_DONE_INT_ENA1_Pos = 0xe + // Bit mask of SLC0_TX_DONE_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_DONE_INT_ENA1_Msk = 0x4000 + // Bit SLC0_TX_DONE_INT_ENA1. + SLC__0INT_ENA1_SLC0_TX_DONE_INT_ENA1 = 0x4000 + // Position of SLC0_TX_SUC_EOF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_SUC_EOF_INT_ENA1_Pos = 0xf + // Bit mask of SLC0_TX_SUC_EOF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_SUC_EOF_INT_ENA1_Msk = 0x8000 + // Bit SLC0_TX_SUC_EOF_INT_ENA1. + SLC__0INT_ENA1_SLC0_TX_SUC_EOF_INT_ENA1 = 0x8000 + // Position of SLC0_RX_DONE_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_DONE_INT_ENA1_Pos = 0x10 + // Bit mask of SLC0_RX_DONE_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_DONE_INT_ENA1_Msk = 0x10000 + // Bit SLC0_RX_DONE_INT_ENA1. + SLC__0INT_ENA1_SLC0_RX_DONE_INT_ENA1 = 0x10000 + // Position of SLC0_RX_EOF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_EOF_INT_ENA1_Pos = 0x11 + // Bit mask of SLC0_RX_EOF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_EOF_INT_ENA1_Msk = 0x20000 + // Bit SLC0_RX_EOF_INT_ENA1. + SLC__0INT_ENA1_SLC0_RX_EOF_INT_ENA1 = 0x20000 + // Position of SLC0_TOHOST_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TOHOST_INT_ENA1_Pos = 0x12 + // Bit mask of SLC0_TOHOST_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TOHOST_INT_ENA1_Msk = 0x40000 + // Bit SLC0_TOHOST_INT_ENA1. + SLC__0INT_ENA1_SLC0_TOHOST_INT_ENA1 = 0x40000 + // Position of SLC0_TX_DSCR_ERR_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_DSCR_ERR_INT_ENA1_Pos = 0x13 + // Bit mask of SLC0_TX_DSCR_ERR_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_DSCR_ERR_INT_ENA1_Msk = 0x80000 + // Bit SLC0_TX_DSCR_ERR_INT_ENA1. + SLC__0INT_ENA1_SLC0_TX_DSCR_ERR_INT_ENA1 = 0x80000 + // Position of SLC0_RX_DSCR_ERR_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_DSCR_ERR_INT_ENA1_Pos = 0x14 + // Bit mask of SLC0_RX_DSCR_ERR_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_DSCR_ERR_INT_ENA1_Msk = 0x100000 + // Bit SLC0_RX_DSCR_ERR_INT_ENA1. + SLC__0INT_ENA1_SLC0_RX_DSCR_ERR_INT_ENA1 = 0x100000 + // Position of SLC0_TX_DSCR_EMPTY_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_DSCR_EMPTY_INT_ENA1_Pos = 0x15 + // Bit mask of SLC0_TX_DSCR_EMPTY_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_DSCR_EMPTY_INT_ENA1_Msk = 0x200000 + // Bit SLC0_TX_DSCR_EMPTY_INT_ENA1. + SLC__0INT_ENA1_SLC0_TX_DSCR_EMPTY_INT_ENA1 = 0x200000 + // Position of SLC0_HOST_RD_ACK_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_HOST_RD_ACK_INT_ENA1_Pos = 0x16 + // Bit mask of SLC0_HOST_RD_ACK_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_HOST_RD_ACK_INT_ENA1_Msk = 0x400000 + // Bit SLC0_HOST_RD_ACK_INT_ENA1. + SLC__0INT_ENA1_SLC0_HOST_RD_ACK_INT_ENA1 = 0x400000 + // Position of SLC0_WR_RETRY_DONE_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_WR_RETRY_DONE_INT_ENA1_Pos = 0x17 + // Bit mask of SLC0_WR_RETRY_DONE_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_WR_RETRY_DONE_INT_ENA1_Msk = 0x800000 + // Bit SLC0_WR_RETRY_DONE_INT_ENA1. + SLC__0INT_ENA1_SLC0_WR_RETRY_DONE_INT_ENA1 = 0x800000 + // Position of SLC0_TX_ERR_EOF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_ERR_EOF_INT_ENA1_Pos = 0x18 + // Bit mask of SLC0_TX_ERR_EOF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_TX_ERR_EOF_INT_ENA1_Msk = 0x1000000 + // Bit SLC0_TX_ERR_EOF_INT_ENA1. + SLC__0INT_ENA1_SLC0_TX_ERR_EOF_INT_ENA1 = 0x1000000 + // Position of CMD_DTC_INT_ENA1 field. + SLC__0INT_ENA1_CMD_DTC_INT_ENA1_Pos = 0x19 + // Bit mask of CMD_DTC_INT_ENA1 field. + SLC__0INT_ENA1_CMD_DTC_INT_ENA1_Msk = 0x2000000 + // Bit CMD_DTC_INT_ENA1. + SLC__0INT_ENA1_CMD_DTC_INT_ENA1 = 0x2000000 + // Position of SLC0_RX_QUICK_EOF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_QUICK_EOF_INT_ENA1_Pos = 0x1a + // Bit mask of SLC0_RX_QUICK_EOF_INT_ENA1 field. + SLC__0INT_ENA1_SLC0_RX_QUICK_EOF_INT_ENA1_Msk = 0x4000000 + // Bit SLC0_RX_QUICK_EOF_INT_ENA1. + SLC__0INT_ENA1_SLC0_RX_QUICK_EOF_INT_ENA1 = 0x4000000 + + // _1INT_ST1 + // Position of FRHOST_BIT8_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT8_INT_ST1_Pos = 0x0 + // Bit mask of FRHOST_BIT8_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT8_INT_ST1_Msk = 0x1 + // Bit FRHOST_BIT8_INT_ST1. + SLC__1INT_ST1_FRHOST_BIT8_INT_ST1 = 0x1 + // Position of FRHOST_BIT9_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT9_INT_ST1_Pos = 0x1 + // Bit mask of FRHOST_BIT9_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT9_INT_ST1_Msk = 0x2 + // Bit FRHOST_BIT9_INT_ST1. + SLC__1INT_ST1_FRHOST_BIT9_INT_ST1 = 0x2 + // Position of FRHOST_BIT10_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT10_INT_ST1_Pos = 0x2 + // Bit mask of FRHOST_BIT10_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT10_INT_ST1_Msk = 0x4 + // Bit FRHOST_BIT10_INT_ST1. + SLC__1INT_ST1_FRHOST_BIT10_INT_ST1 = 0x4 + // Position of FRHOST_BIT11_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT11_INT_ST1_Pos = 0x3 + // Bit mask of FRHOST_BIT11_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT11_INT_ST1_Msk = 0x8 + // Bit FRHOST_BIT11_INT_ST1. + SLC__1INT_ST1_FRHOST_BIT11_INT_ST1 = 0x8 + // Position of FRHOST_BIT12_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT12_INT_ST1_Pos = 0x4 + // Bit mask of FRHOST_BIT12_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT12_INT_ST1_Msk = 0x10 + // Bit FRHOST_BIT12_INT_ST1. + SLC__1INT_ST1_FRHOST_BIT12_INT_ST1 = 0x10 + // Position of FRHOST_BIT13_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT13_INT_ST1_Pos = 0x5 + // Bit mask of FRHOST_BIT13_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT13_INT_ST1_Msk = 0x20 + // Bit FRHOST_BIT13_INT_ST1. + SLC__1INT_ST1_FRHOST_BIT13_INT_ST1 = 0x20 + // Position of FRHOST_BIT14_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT14_INT_ST1_Pos = 0x6 + // Bit mask of FRHOST_BIT14_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT14_INT_ST1_Msk = 0x40 + // Bit FRHOST_BIT14_INT_ST1. + SLC__1INT_ST1_FRHOST_BIT14_INT_ST1 = 0x40 + // Position of FRHOST_BIT15_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT15_INT_ST1_Pos = 0x7 + // Bit mask of FRHOST_BIT15_INT_ST1 field. + SLC__1INT_ST1_FRHOST_BIT15_INT_ST1_Msk = 0x80 + // Bit FRHOST_BIT15_INT_ST1. + SLC__1INT_ST1_FRHOST_BIT15_INT_ST1 = 0x80 + // Position of SLC1_RX_START_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_START_INT_ST1_Pos = 0x8 + // Bit mask of SLC1_RX_START_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_START_INT_ST1_Msk = 0x100 + // Bit SLC1_RX_START_INT_ST1. + SLC__1INT_ST1_SLC1_RX_START_INT_ST1 = 0x100 + // Position of SLC1_TX_START_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_START_INT_ST1_Pos = 0x9 + // Bit mask of SLC1_TX_START_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_START_INT_ST1_Msk = 0x200 + // Bit SLC1_TX_START_INT_ST1. + SLC__1INT_ST1_SLC1_TX_START_INT_ST1 = 0x200 + // Position of SLC1_RX_UDF_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_UDF_INT_ST1_Pos = 0xa + // Bit mask of SLC1_RX_UDF_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_UDF_INT_ST1_Msk = 0x400 + // Bit SLC1_RX_UDF_INT_ST1. + SLC__1INT_ST1_SLC1_RX_UDF_INT_ST1 = 0x400 + // Position of SLC1_TX_OVF_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_OVF_INT_ST1_Pos = 0xb + // Bit mask of SLC1_TX_OVF_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_OVF_INT_ST1_Msk = 0x800 + // Bit SLC1_TX_OVF_INT_ST1. + SLC__1INT_ST1_SLC1_TX_OVF_INT_ST1 = 0x800 + // Position of SLC1_TOKEN0_1TO0_INT_ST1 field. + SLC__1INT_ST1_SLC1_TOKEN0_1TO0_INT_ST1_Pos = 0xc + // Bit mask of SLC1_TOKEN0_1TO0_INT_ST1 field. + SLC__1INT_ST1_SLC1_TOKEN0_1TO0_INT_ST1_Msk = 0x1000 + // Bit SLC1_TOKEN0_1TO0_INT_ST1. + SLC__1INT_ST1_SLC1_TOKEN0_1TO0_INT_ST1 = 0x1000 + // Position of SLC1_TOKEN1_1TO0_INT_ST1 field. + SLC__1INT_ST1_SLC1_TOKEN1_1TO0_INT_ST1_Pos = 0xd + // Bit mask of SLC1_TOKEN1_1TO0_INT_ST1 field. + SLC__1INT_ST1_SLC1_TOKEN1_1TO0_INT_ST1_Msk = 0x2000 + // Bit SLC1_TOKEN1_1TO0_INT_ST1. + SLC__1INT_ST1_SLC1_TOKEN1_1TO0_INT_ST1 = 0x2000 + // Position of SLC1_TX_DONE_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_DONE_INT_ST1_Pos = 0xe + // Bit mask of SLC1_TX_DONE_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_DONE_INT_ST1_Msk = 0x4000 + // Bit SLC1_TX_DONE_INT_ST1. + SLC__1INT_ST1_SLC1_TX_DONE_INT_ST1 = 0x4000 + // Position of SLC1_TX_SUC_EOF_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_SUC_EOF_INT_ST1_Pos = 0xf + // Bit mask of SLC1_TX_SUC_EOF_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_SUC_EOF_INT_ST1_Msk = 0x8000 + // Bit SLC1_TX_SUC_EOF_INT_ST1. + SLC__1INT_ST1_SLC1_TX_SUC_EOF_INT_ST1 = 0x8000 + // Position of SLC1_RX_DONE_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_DONE_INT_ST1_Pos = 0x10 + // Bit mask of SLC1_RX_DONE_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_DONE_INT_ST1_Msk = 0x10000 + // Bit SLC1_RX_DONE_INT_ST1. + SLC__1INT_ST1_SLC1_RX_DONE_INT_ST1 = 0x10000 + // Position of SLC1_RX_EOF_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_EOF_INT_ST1_Pos = 0x11 + // Bit mask of SLC1_RX_EOF_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_EOF_INT_ST1_Msk = 0x20000 + // Bit SLC1_RX_EOF_INT_ST1. + SLC__1INT_ST1_SLC1_RX_EOF_INT_ST1 = 0x20000 + // Position of SLC1_TOHOST_INT_ST1 field. + SLC__1INT_ST1_SLC1_TOHOST_INT_ST1_Pos = 0x12 + // Bit mask of SLC1_TOHOST_INT_ST1 field. + SLC__1INT_ST1_SLC1_TOHOST_INT_ST1_Msk = 0x40000 + // Bit SLC1_TOHOST_INT_ST1. + SLC__1INT_ST1_SLC1_TOHOST_INT_ST1 = 0x40000 + // Position of SLC1_TX_DSCR_ERR_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_DSCR_ERR_INT_ST1_Pos = 0x13 + // Bit mask of SLC1_TX_DSCR_ERR_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_DSCR_ERR_INT_ST1_Msk = 0x80000 + // Bit SLC1_TX_DSCR_ERR_INT_ST1. + SLC__1INT_ST1_SLC1_TX_DSCR_ERR_INT_ST1 = 0x80000 + // Position of SLC1_RX_DSCR_ERR_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_DSCR_ERR_INT_ST1_Pos = 0x14 + // Bit mask of SLC1_RX_DSCR_ERR_INT_ST1 field. + SLC__1INT_ST1_SLC1_RX_DSCR_ERR_INT_ST1_Msk = 0x100000 + // Bit SLC1_RX_DSCR_ERR_INT_ST1. + SLC__1INT_ST1_SLC1_RX_DSCR_ERR_INT_ST1 = 0x100000 + // Position of SLC1_TX_DSCR_EMPTY_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_DSCR_EMPTY_INT_ST1_Pos = 0x15 + // Bit mask of SLC1_TX_DSCR_EMPTY_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_DSCR_EMPTY_INT_ST1_Msk = 0x200000 + // Bit SLC1_TX_DSCR_EMPTY_INT_ST1. + SLC__1INT_ST1_SLC1_TX_DSCR_EMPTY_INT_ST1 = 0x200000 + // Position of SLC1_HOST_RD_ACK_INT_ST1 field. + SLC__1INT_ST1_SLC1_HOST_RD_ACK_INT_ST1_Pos = 0x16 + // Bit mask of SLC1_HOST_RD_ACK_INT_ST1 field. + SLC__1INT_ST1_SLC1_HOST_RD_ACK_INT_ST1_Msk = 0x400000 + // Bit SLC1_HOST_RD_ACK_INT_ST1. + SLC__1INT_ST1_SLC1_HOST_RD_ACK_INT_ST1 = 0x400000 + // Position of SLC1_WR_RETRY_DONE_INT_ST1 field. + SLC__1INT_ST1_SLC1_WR_RETRY_DONE_INT_ST1_Pos = 0x17 + // Bit mask of SLC1_WR_RETRY_DONE_INT_ST1 field. + SLC__1INT_ST1_SLC1_WR_RETRY_DONE_INT_ST1_Msk = 0x800000 + // Bit SLC1_WR_RETRY_DONE_INT_ST1. + SLC__1INT_ST1_SLC1_WR_RETRY_DONE_INT_ST1 = 0x800000 + // Position of SLC1_TX_ERR_EOF_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_ERR_EOF_INT_ST1_Pos = 0x18 + // Bit mask of SLC1_TX_ERR_EOF_INT_ST1 field. + SLC__1INT_ST1_SLC1_TX_ERR_EOF_INT_ST1_Msk = 0x1000000 + // Bit SLC1_TX_ERR_EOF_INT_ST1. + SLC__1INT_ST1_SLC1_TX_ERR_EOF_INT_ST1 = 0x1000000 + + // _1INT_ENA1 + // Position of FRHOST_BIT8_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT8_INT_ENA1_Pos = 0x0 + // Bit mask of FRHOST_BIT8_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT8_INT_ENA1_Msk = 0x1 + // Bit FRHOST_BIT8_INT_ENA1. + SLC__1INT_ENA1_FRHOST_BIT8_INT_ENA1 = 0x1 + // Position of FRHOST_BIT9_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT9_INT_ENA1_Pos = 0x1 + // Bit mask of FRHOST_BIT9_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT9_INT_ENA1_Msk = 0x2 + // Bit FRHOST_BIT9_INT_ENA1. + SLC__1INT_ENA1_FRHOST_BIT9_INT_ENA1 = 0x2 + // Position of FRHOST_BIT10_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT10_INT_ENA1_Pos = 0x2 + // Bit mask of FRHOST_BIT10_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT10_INT_ENA1_Msk = 0x4 + // Bit FRHOST_BIT10_INT_ENA1. + SLC__1INT_ENA1_FRHOST_BIT10_INT_ENA1 = 0x4 + // Position of FRHOST_BIT11_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT11_INT_ENA1_Pos = 0x3 + // Bit mask of FRHOST_BIT11_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT11_INT_ENA1_Msk = 0x8 + // Bit FRHOST_BIT11_INT_ENA1. + SLC__1INT_ENA1_FRHOST_BIT11_INT_ENA1 = 0x8 + // Position of FRHOST_BIT12_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT12_INT_ENA1_Pos = 0x4 + // Bit mask of FRHOST_BIT12_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT12_INT_ENA1_Msk = 0x10 + // Bit FRHOST_BIT12_INT_ENA1. + SLC__1INT_ENA1_FRHOST_BIT12_INT_ENA1 = 0x10 + // Position of FRHOST_BIT13_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT13_INT_ENA1_Pos = 0x5 + // Bit mask of FRHOST_BIT13_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT13_INT_ENA1_Msk = 0x20 + // Bit FRHOST_BIT13_INT_ENA1. + SLC__1INT_ENA1_FRHOST_BIT13_INT_ENA1 = 0x20 + // Position of FRHOST_BIT14_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT14_INT_ENA1_Pos = 0x6 + // Bit mask of FRHOST_BIT14_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT14_INT_ENA1_Msk = 0x40 + // Bit FRHOST_BIT14_INT_ENA1. + SLC__1INT_ENA1_FRHOST_BIT14_INT_ENA1 = 0x40 + // Position of FRHOST_BIT15_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT15_INT_ENA1_Pos = 0x7 + // Bit mask of FRHOST_BIT15_INT_ENA1 field. + SLC__1INT_ENA1_FRHOST_BIT15_INT_ENA1_Msk = 0x80 + // Bit FRHOST_BIT15_INT_ENA1. + SLC__1INT_ENA1_FRHOST_BIT15_INT_ENA1 = 0x80 + // Position of SLC1_RX_START_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_START_INT_ENA1_Pos = 0x8 + // Bit mask of SLC1_RX_START_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_START_INT_ENA1_Msk = 0x100 + // Bit SLC1_RX_START_INT_ENA1. + SLC__1INT_ENA1_SLC1_RX_START_INT_ENA1 = 0x100 + // Position of SLC1_TX_START_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_START_INT_ENA1_Pos = 0x9 + // Bit mask of SLC1_TX_START_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_START_INT_ENA1_Msk = 0x200 + // Bit SLC1_TX_START_INT_ENA1. + SLC__1INT_ENA1_SLC1_TX_START_INT_ENA1 = 0x200 + // Position of SLC1_RX_UDF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_UDF_INT_ENA1_Pos = 0xa + // Bit mask of SLC1_RX_UDF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_UDF_INT_ENA1_Msk = 0x400 + // Bit SLC1_RX_UDF_INT_ENA1. + SLC__1INT_ENA1_SLC1_RX_UDF_INT_ENA1 = 0x400 + // Position of SLC1_TX_OVF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_OVF_INT_ENA1_Pos = 0xb + // Bit mask of SLC1_TX_OVF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_OVF_INT_ENA1_Msk = 0x800 + // Bit SLC1_TX_OVF_INT_ENA1. + SLC__1INT_ENA1_SLC1_TX_OVF_INT_ENA1 = 0x800 + // Position of SLC1_TOKEN0_1TO0_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1_Pos = 0xc + // Bit mask of SLC1_TOKEN0_1TO0_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1_Msk = 0x1000 + // Bit SLC1_TOKEN0_1TO0_INT_ENA1. + SLC__1INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1 = 0x1000 + // Position of SLC1_TOKEN1_1TO0_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1_Pos = 0xd + // Bit mask of SLC1_TOKEN1_1TO0_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1_Msk = 0x2000 + // Bit SLC1_TOKEN1_1TO0_INT_ENA1. + SLC__1INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1 = 0x2000 + // Position of SLC1_TX_DONE_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_DONE_INT_ENA1_Pos = 0xe + // Bit mask of SLC1_TX_DONE_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_DONE_INT_ENA1_Msk = 0x4000 + // Bit SLC1_TX_DONE_INT_ENA1. + SLC__1INT_ENA1_SLC1_TX_DONE_INT_ENA1 = 0x4000 + // Position of SLC1_TX_SUC_EOF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_SUC_EOF_INT_ENA1_Pos = 0xf + // Bit mask of SLC1_TX_SUC_EOF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_SUC_EOF_INT_ENA1_Msk = 0x8000 + // Bit SLC1_TX_SUC_EOF_INT_ENA1. + SLC__1INT_ENA1_SLC1_TX_SUC_EOF_INT_ENA1 = 0x8000 + // Position of SLC1_RX_DONE_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_DONE_INT_ENA1_Pos = 0x10 + // Bit mask of SLC1_RX_DONE_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_DONE_INT_ENA1_Msk = 0x10000 + // Bit SLC1_RX_DONE_INT_ENA1. + SLC__1INT_ENA1_SLC1_RX_DONE_INT_ENA1 = 0x10000 + // Position of SLC1_RX_EOF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_EOF_INT_ENA1_Pos = 0x11 + // Bit mask of SLC1_RX_EOF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_EOF_INT_ENA1_Msk = 0x20000 + // Bit SLC1_RX_EOF_INT_ENA1. + SLC__1INT_ENA1_SLC1_RX_EOF_INT_ENA1 = 0x20000 + // Position of SLC1_TOHOST_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TOHOST_INT_ENA1_Pos = 0x12 + // Bit mask of SLC1_TOHOST_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TOHOST_INT_ENA1_Msk = 0x40000 + // Bit SLC1_TOHOST_INT_ENA1. + SLC__1INT_ENA1_SLC1_TOHOST_INT_ENA1 = 0x40000 + // Position of SLC1_TX_DSCR_ERR_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_DSCR_ERR_INT_ENA1_Pos = 0x13 + // Bit mask of SLC1_TX_DSCR_ERR_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_DSCR_ERR_INT_ENA1_Msk = 0x80000 + // Bit SLC1_TX_DSCR_ERR_INT_ENA1. + SLC__1INT_ENA1_SLC1_TX_DSCR_ERR_INT_ENA1 = 0x80000 + // Position of SLC1_RX_DSCR_ERR_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_DSCR_ERR_INT_ENA1_Pos = 0x14 + // Bit mask of SLC1_RX_DSCR_ERR_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_RX_DSCR_ERR_INT_ENA1_Msk = 0x100000 + // Bit SLC1_RX_DSCR_ERR_INT_ENA1. + SLC__1INT_ENA1_SLC1_RX_DSCR_ERR_INT_ENA1 = 0x100000 + // Position of SLC1_TX_DSCR_EMPTY_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_DSCR_EMPTY_INT_ENA1_Pos = 0x15 + // Bit mask of SLC1_TX_DSCR_EMPTY_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_DSCR_EMPTY_INT_ENA1_Msk = 0x200000 + // Bit SLC1_TX_DSCR_EMPTY_INT_ENA1. + SLC__1INT_ENA1_SLC1_TX_DSCR_EMPTY_INT_ENA1 = 0x200000 + // Position of SLC1_HOST_RD_ACK_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_HOST_RD_ACK_INT_ENA1_Pos = 0x16 + // Bit mask of SLC1_HOST_RD_ACK_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_HOST_RD_ACK_INT_ENA1_Msk = 0x400000 + // Bit SLC1_HOST_RD_ACK_INT_ENA1. + SLC__1INT_ENA1_SLC1_HOST_RD_ACK_INT_ENA1 = 0x400000 + // Position of SLC1_WR_RETRY_DONE_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_WR_RETRY_DONE_INT_ENA1_Pos = 0x17 + // Bit mask of SLC1_WR_RETRY_DONE_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_WR_RETRY_DONE_INT_ENA1_Msk = 0x800000 + // Bit SLC1_WR_RETRY_DONE_INT_ENA1. + SLC__1INT_ENA1_SLC1_WR_RETRY_DONE_INT_ENA1 = 0x800000 + // Position of SLC1_TX_ERR_EOF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_ERR_EOF_INT_ENA1_Pos = 0x18 + // Bit mask of SLC1_TX_ERR_EOF_INT_ENA1 field. + SLC__1INT_ENA1_SLC1_TX_ERR_EOF_INT_ENA1_Msk = 0x1000000 + // Bit SLC1_TX_ERR_EOF_INT_ENA1. + SLC__1INT_ENA1_SLC1_TX_ERR_EOF_INT_ENA1 = 0x1000000 + + // DATE + // Position of DATE field. + SLC_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SLC_DATE_DATE_Msk = 0xffffffff + + // ID + // Position of ID field. + SLC_ID_ID_Pos = 0x0 + // Bit mask of ID field. + SLC_ID_ID_Msk = 0xffffffff +) + +// Constants for SLCHOST: SLCHOST Peripheral +const ( + // HOST_SLCHOST_FUNC2_0 + // Position of HOST_SLC_FUNC2_INT field. + SLCHOST_HOST_SLCHOST_FUNC2_0_HOST_SLC_FUNC2_INT_Pos = 0x18 + // Bit mask of HOST_SLC_FUNC2_INT field. + SLCHOST_HOST_SLCHOST_FUNC2_0_HOST_SLC_FUNC2_INT_Msk = 0x1000000 + // Bit HOST_SLC_FUNC2_INT. + SLCHOST_HOST_SLCHOST_FUNC2_0_HOST_SLC_FUNC2_INT = 0x1000000 + + // HOST_SLCHOST_FUNC2_1 + // Position of HOST_SLC_FUNC2_INT_EN field. + SLCHOST_HOST_SLCHOST_FUNC2_1_HOST_SLC_FUNC2_INT_EN_Pos = 0x0 + // Bit mask of HOST_SLC_FUNC2_INT_EN field. + SLCHOST_HOST_SLCHOST_FUNC2_1_HOST_SLC_FUNC2_INT_EN_Msk = 0x1 + // Bit HOST_SLC_FUNC2_INT_EN. + SLCHOST_HOST_SLCHOST_FUNC2_1_HOST_SLC_FUNC2_INT_EN = 0x1 + + // HOST_SLCHOST_FUNC2_2 + // Position of HOST_SLC_FUNC1_MDSTAT field. + SLCHOST_HOST_SLCHOST_FUNC2_2_HOST_SLC_FUNC1_MDSTAT_Pos = 0x0 + // Bit mask of HOST_SLC_FUNC1_MDSTAT field. + SLCHOST_HOST_SLCHOST_FUNC2_2_HOST_SLC_FUNC1_MDSTAT_Msk = 0x1 + // Bit HOST_SLC_FUNC1_MDSTAT. + SLCHOST_HOST_SLCHOST_FUNC2_2_HOST_SLC_FUNC1_MDSTAT = 0x1 + + // HOST_SLCHOST_GPIO_STATUS0 + // Position of HOST_GPIO_SDIO_INT0 field. + SLCHOST_HOST_SLCHOST_GPIO_STATUS0_HOST_GPIO_SDIO_INT0_Pos = 0x0 + // Bit mask of HOST_GPIO_SDIO_INT0 field. + SLCHOST_HOST_SLCHOST_GPIO_STATUS0_HOST_GPIO_SDIO_INT0_Msk = 0xffffffff + + // HOST_SLCHOST_GPIO_STATUS1 + // Position of HOST_GPIO_SDIO_INT1 field. + SLCHOST_HOST_SLCHOST_GPIO_STATUS1_HOST_GPIO_SDIO_INT1_Pos = 0x0 + // Bit mask of HOST_GPIO_SDIO_INT1 field. + SLCHOST_HOST_SLCHOST_GPIO_STATUS1_HOST_GPIO_SDIO_INT1_Msk = 0xff + + // HOST_SLCHOST_GPIO_IN0 + // Position of HOST_GPIO_SDIO_IN0 field. + SLCHOST_HOST_SLCHOST_GPIO_IN0_HOST_GPIO_SDIO_IN0_Pos = 0x0 + // Bit mask of HOST_GPIO_SDIO_IN0 field. + SLCHOST_HOST_SLCHOST_GPIO_IN0_HOST_GPIO_SDIO_IN0_Msk = 0xffffffff + + // HOST_SLCHOST_GPIO_IN1 + // Position of HOST_GPIO_SDIO_IN1 field. + SLCHOST_HOST_SLCHOST_GPIO_IN1_HOST_GPIO_SDIO_IN1_Pos = 0x0 + // Bit mask of HOST_GPIO_SDIO_IN1 field. + SLCHOST_HOST_SLCHOST_GPIO_IN1_HOST_GPIO_SDIO_IN1_Msk = 0xff + + // HOST_SLC0HOST_TOKEN_RDATA + // Position of HOST_SLC0_TOKEN0 field. + SLCHOST_HOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_TOKEN0_Pos = 0x0 + // Bit mask of HOST_SLC0_TOKEN0 field. + SLCHOST_HOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_TOKEN0_Msk = 0xfff + // Position of HOST_SLC0_RX_PF_VALID field. + SLCHOST_HOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_RX_PF_VALID_Pos = 0xc + // Bit mask of HOST_SLC0_RX_PF_VALID field. + SLCHOST_HOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_RX_PF_VALID_Msk = 0x1000 + // Bit HOST_SLC0_RX_PF_VALID. + SLCHOST_HOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_RX_PF_VALID = 0x1000 + // Position of HOST_HOSTSLC0_TOKEN1 field. + SLCHOST_HOST_SLC0HOST_TOKEN_RDATA_HOST_HOSTSLC0_TOKEN1_Pos = 0x10 + // Bit mask of HOST_HOSTSLC0_TOKEN1 field. + SLCHOST_HOST_SLC0HOST_TOKEN_RDATA_HOST_HOSTSLC0_TOKEN1_Msk = 0xfff0000 + // Position of HOST_SLC0_RX_PF_EOF field. + SLCHOST_HOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_RX_PF_EOF_Pos = 0x1c + // Bit mask of HOST_SLC0_RX_PF_EOF field. + SLCHOST_HOST_SLC0HOST_TOKEN_RDATA_HOST_SLC0_RX_PF_EOF_Msk = 0xf0000000 + + // HOST_SLC0_HOST_PF + // Position of HOST_SLC0_PF_DATA field. + SLCHOST_HOST_SLC0_HOST_PF_HOST_SLC0_PF_DATA_Pos = 0x0 + // Bit mask of HOST_SLC0_PF_DATA field. + SLCHOST_HOST_SLC0_HOST_PF_HOST_SLC0_PF_DATA_Msk = 0xffffffff + + // HOST_SLC1_HOST_PF + // Position of HOST_SLC1_PF_DATA field. + SLCHOST_HOST_SLC1_HOST_PF_HOST_SLC1_PF_DATA_Pos = 0x0 + // Bit mask of HOST_SLC1_PF_DATA field. + SLCHOST_HOST_SLC1_HOST_PF_HOST_SLC1_PF_DATA_Msk = 0xffffffff + + // HOST_SLC0HOST_INT_RAW + // Position of HOST_SLC0_TOHOST_BIT0_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT0_INT_RAW_Pos = 0x0 + // Bit mask of HOST_SLC0_TOHOST_BIT0_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT0_INT_RAW_Msk = 0x1 + // Bit HOST_SLC0_TOHOST_BIT0_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT0_INT_RAW = 0x1 + // Position of HOST_SLC0_TOHOST_BIT1_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT1_INT_RAW_Pos = 0x1 + // Bit mask of HOST_SLC0_TOHOST_BIT1_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT1_INT_RAW_Msk = 0x2 + // Bit HOST_SLC0_TOHOST_BIT1_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT1_INT_RAW = 0x2 + // Position of HOST_SLC0_TOHOST_BIT2_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT2_INT_RAW_Pos = 0x2 + // Bit mask of HOST_SLC0_TOHOST_BIT2_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT2_INT_RAW_Msk = 0x4 + // Bit HOST_SLC0_TOHOST_BIT2_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT2_INT_RAW = 0x4 + // Position of HOST_SLC0_TOHOST_BIT3_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT3_INT_RAW_Pos = 0x3 + // Bit mask of HOST_SLC0_TOHOST_BIT3_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT3_INT_RAW_Msk = 0x8 + // Bit HOST_SLC0_TOHOST_BIT3_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT3_INT_RAW = 0x8 + // Position of HOST_SLC0_TOHOST_BIT4_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT4_INT_RAW_Pos = 0x4 + // Bit mask of HOST_SLC0_TOHOST_BIT4_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT4_INT_RAW_Msk = 0x10 + // Bit HOST_SLC0_TOHOST_BIT4_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT4_INT_RAW = 0x10 + // Position of HOST_SLC0_TOHOST_BIT5_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT5_INT_RAW_Pos = 0x5 + // Bit mask of HOST_SLC0_TOHOST_BIT5_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT5_INT_RAW_Msk = 0x20 + // Bit HOST_SLC0_TOHOST_BIT5_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT5_INT_RAW = 0x20 + // Position of HOST_SLC0_TOHOST_BIT6_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT6_INT_RAW_Pos = 0x6 + // Bit mask of HOST_SLC0_TOHOST_BIT6_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT6_INT_RAW_Msk = 0x40 + // Bit HOST_SLC0_TOHOST_BIT6_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT6_INT_RAW = 0x40 + // Position of HOST_SLC0_TOHOST_BIT7_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT7_INT_RAW_Pos = 0x7 + // Bit mask of HOST_SLC0_TOHOST_BIT7_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT7_INT_RAW_Msk = 0x80 + // Bit HOST_SLC0_TOHOST_BIT7_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOHOST_BIT7_INT_RAW = 0x80 + // Position of HOST_SLC0_TOKEN0_1TO0_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_1TO0_INT_RAW_Pos = 0x8 + // Bit mask of HOST_SLC0_TOKEN0_1TO0_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_1TO0_INT_RAW_Msk = 0x100 + // Bit HOST_SLC0_TOKEN0_1TO0_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_1TO0_INT_RAW = 0x100 + // Position of HOST_SLC0_TOKEN1_1TO0_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_1TO0_INT_RAW_Pos = 0x9 + // Bit mask of HOST_SLC0_TOKEN1_1TO0_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_1TO0_INT_RAW_Msk = 0x200 + // Bit HOST_SLC0_TOKEN1_1TO0_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_1TO0_INT_RAW = 0x200 + // Position of HOST_SLC0_TOKEN0_0TO1_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_0TO1_INT_RAW_Pos = 0xa + // Bit mask of HOST_SLC0_TOKEN0_0TO1_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_0TO1_INT_RAW_Msk = 0x400 + // Bit HOST_SLC0_TOKEN0_0TO1_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN0_0TO1_INT_RAW = 0x400 + // Position of HOST_SLC0_TOKEN1_0TO1_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_0TO1_INT_RAW_Pos = 0xb + // Bit mask of HOST_SLC0_TOKEN1_0TO1_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_0TO1_INT_RAW_Msk = 0x800 + // Bit HOST_SLC0_TOKEN1_0TO1_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TOKEN1_0TO1_INT_RAW = 0x800 + // Position of HOST_SLC0HOST_RX_SOF_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_SOF_INT_RAW_Pos = 0xc + // Bit mask of HOST_SLC0HOST_RX_SOF_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_SOF_INT_RAW_Msk = 0x1000 + // Bit HOST_SLC0HOST_RX_SOF_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_SOF_INT_RAW = 0x1000 + // Position of HOST_SLC0HOST_RX_EOF_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_EOF_INT_RAW_Pos = 0xd + // Bit mask of HOST_SLC0HOST_RX_EOF_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_EOF_INT_RAW_Msk = 0x2000 + // Bit HOST_SLC0HOST_RX_EOF_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_EOF_INT_RAW = 0x2000 + // Position of HOST_SLC0HOST_RX_START_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_START_INT_RAW_Pos = 0xe + // Bit mask of HOST_SLC0HOST_RX_START_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_START_INT_RAW_Msk = 0x4000 + // Bit HOST_SLC0HOST_RX_START_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_RX_START_INT_RAW = 0x4000 + // Position of HOST_SLC0HOST_TX_START_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_TX_START_INT_RAW_Pos = 0xf + // Bit mask of HOST_SLC0HOST_TX_START_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_TX_START_INT_RAW_Msk = 0x8000 + // Bit HOST_SLC0HOST_TX_START_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0HOST_TX_START_INT_RAW = 0x8000 + // Position of HOST_SLC0_RX_UDF_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_UDF_INT_RAW_Pos = 0x10 + // Bit mask of HOST_SLC0_RX_UDF_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_UDF_INT_RAW_Msk = 0x10000 + // Bit HOST_SLC0_RX_UDF_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_UDF_INT_RAW = 0x10000 + // Position of HOST_SLC0_TX_OVF_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TX_OVF_INT_RAW_Pos = 0x11 + // Bit mask of HOST_SLC0_TX_OVF_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TX_OVF_INT_RAW_Msk = 0x20000 + // Bit HOST_SLC0_TX_OVF_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_TX_OVF_INT_RAW = 0x20000 + // Position of HOST_SLC0_RX_PF_VALID_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_PF_VALID_INT_RAW_Pos = 0x12 + // Bit mask of HOST_SLC0_RX_PF_VALID_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_PF_VALID_INT_RAW_Msk = 0x40000 + // Bit HOST_SLC0_RX_PF_VALID_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_PF_VALID_INT_RAW = 0x40000 + // Position of HOST_SLC0_EXT_BIT0_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT0_INT_RAW_Pos = 0x13 + // Bit mask of HOST_SLC0_EXT_BIT0_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT0_INT_RAW_Msk = 0x80000 + // Bit HOST_SLC0_EXT_BIT0_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT0_INT_RAW = 0x80000 + // Position of HOST_SLC0_EXT_BIT1_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT1_INT_RAW_Pos = 0x14 + // Bit mask of HOST_SLC0_EXT_BIT1_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT1_INT_RAW_Msk = 0x100000 + // Bit HOST_SLC0_EXT_BIT1_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT1_INT_RAW = 0x100000 + // Position of HOST_SLC0_EXT_BIT2_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT2_INT_RAW_Pos = 0x15 + // Bit mask of HOST_SLC0_EXT_BIT2_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT2_INT_RAW_Msk = 0x200000 + // Bit HOST_SLC0_EXT_BIT2_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT2_INT_RAW = 0x200000 + // Position of HOST_SLC0_EXT_BIT3_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT3_INT_RAW_Pos = 0x16 + // Bit mask of HOST_SLC0_EXT_BIT3_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT3_INT_RAW_Msk = 0x400000 + // Bit HOST_SLC0_EXT_BIT3_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_EXT_BIT3_INT_RAW = 0x400000 + // Position of HOST_SLC0_RX_NEW_PACKET_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_NEW_PACKET_INT_RAW_Pos = 0x17 + // Bit mask of HOST_SLC0_RX_NEW_PACKET_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_NEW_PACKET_INT_RAW_Msk = 0x800000 + // Bit HOST_SLC0_RX_NEW_PACKET_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_RX_NEW_PACKET_INT_RAW = 0x800000 + // Position of HOST_SLC0_HOST_RD_RETRY_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_HOST_RD_RETRY_INT_RAW_Pos = 0x18 + // Bit mask of HOST_SLC0_HOST_RD_RETRY_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_HOST_RD_RETRY_INT_RAW_Msk = 0x1000000 + // Bit HOST_SLC0_HOST_RD_RETRY_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_SLC0_HOST_RD_RETRY_INT_RAW = 0x1000000 + // Position of HOST_GPIO_SDIO_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_GPIO_SDIO_INT_RAW_Pos = 0x19 + // Bit mask of HOST_GPIO_SDIO_INT_RAW field. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_GPIO_SDIO_INT_RAW_Msk = 0x2000000 + // Bit HOST_GPIO_SDIO_INT_RAW. + SLCHOST_HOST_SLC0HOST_INT_RAW_HOST_GPIO_SDIO_INT_RAW = 0x2000000 + + // HOST_SLC1HOST_INT_RAW + // Position of HOST_SLC1_TOHOST_BIT0_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT0_INT_RAW_Pos = 0x0 + // Bit mask of HOST_SLC1_TOHOST_BIT0_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT0_INT_RAW_Msk = 0x1 + // Bit HOST_SLC1_TOHOST_BIT0_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT0_INT_RAW = 0x1 + // Position of HOST_SLC1_TOHOST_BIT1_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT1_INT_RAW_Pos = 0x1 + // Bit mask of HOST_SLC1_TOHOST_BIT1_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT1_INT_RAW_Msk = 0x2 + // Bit HOST_SLC1_TOHOST_BIT1_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT1_INT_RAW = 0x2 + // Position of HOST_SLC1_TOHOST_BIT2_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT2_INT_RAW_Pos = 0x2 + // Bit mask of HOST_SLC1_TOHOST_BIT2_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT2_INT_RAW_Msk = 0x4 + // Bit HOST_SLC1_TOHOST_BIT2_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT2_INT_RAW = 0x4 + // Position of HOST_SLC1_TOHOST_BIT3_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT3_INT_RAW_Pos = 0x3 + // Bit mask of HOST_SLC1_TOHOST_BIT3_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT3_INT_RAW_Msk = 0x8 + // Bit HOST_SLC1_TOHOST_BIT3_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT3_INT_RAW = 0x8 + // Position of HOST_SLC1_TOHOST_BIT4_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT4_INT_RAW_Pos = 0x4 + // Bit mask of HOST_SLC1_TOHOST_BIT4_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT4_INT_RAW_Msk = 0x10 + // Bit HOST_SLC1_TOHOST_BIT4_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT4_INT_RAW = 0x10 + // Position of HOST_SLC1_TOHOST_BIT5_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT5_INT_RAW_Pos = 0x5 + // Bit mask of HOST_SLC1_TOHOST_BIT5_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT5_INT_RAW_Msk = 0x20 + // Bit HOST_SLC1_TOHOST_BIT5_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT5_INT_RAW = 0x20 + // Position of HOST_SLC1_TOHOST_BIT6_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT6_INT_RAW_Pos = 0x6 + // Bit mask of HOST_SLC1_TOHOST_BIT6_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT6_INT_RAW_Msk = 0x40 + // Bit HOST_SLC1_TOHOST_BIT6_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT6_INT_RAW = 0x40 + // Position of HOST_SLC1_TOHOST_BIT7_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT7_INT_RAW_Pos = 0x7 + // Bit mask of HOST_SLC1_TOHOST_BIT7_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT7_INT_RAW_Msk = 0x80 + // Bit HOST_SLC1_TOHOST_BIT7_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOHOST_BIT7_INT_RAW = 0x80 + // Position of HOST_SLC1_TOKEN0_1TO0_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_1TO0_INT_RAW_Pos = 0x8 + // Bit mask of HOST_SLC1_TOKEN0_1TO0_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_1TO0_INT_RAW_Msk = 0x100 + // Bit HOST_SLC1_TOKEN0_1TO0_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_1TO0_INT_RAW = 0x100 + // Position of HOST_SLC1_TOKEN1_1TO0_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_1TO0_INT_RAW_Pos = 0x9 + // Bit mask of HOST_SLC1_TOKEN1_1TO0_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_1TO0_INT_RAW_Msk = 0x200 + // Bit HOST_SLC1_TOKEN1_1TO0_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_1TO0_INT_RAW = 0x200 + // Position of HOST_SLC1_TOKEN0_0TO1_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_0TO1_INT_RAW_Pos = 0xa + // Bit mask of HOST_SLC1_TOKEN0_0TO1_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_0TO1_INT_RAW_Msk = 0x400 + // Bit HOST_SLC1_TOKEN0_0TO1_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN0_0TO1_INT_RAW = 0x400 + // Position of HOST_SLC1_TOKEN1_0TO1_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_0TO1_INT_RAW_Pos = 0xb + // Bit mask of HOST_SLC1_TOKEN1_0TO1_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_0TO1_INT_RAW_Msk = 0x800 + // Bit HOST_SLC1_TOKEN1_0TO1_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TOKEN1_0TO1_INT_RAW = 0x800 + // Position of HOST_SLC1HOST_RX_SOF_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_SOF_INT_RAW_Pos = 0xc + // Bit mask of HOST_SLC1HOST_RX_SOF_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_SOF_INT_RAW_Msk = 0x1000 + // Bit HOST_SLC1HOST_RX_SOF_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_SOF_INT_RAW = 0x1000 + // Position of HOST_SLC1HOST_RX_EOF_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_EOF_INT_RAW_Pos = 0xd + // Bit mask of HOST_SLC1HOST_RX_EOF_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_EOF_INT_RAW_Msk = 0x2000 + // Bit HOST_SLC1HOST_RX_EOF_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_EOF_INT_RAW = 0x2000 + // Position of HOST_SLC1HOST_RX_START_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_START_INT_RAW_Pos = 0xe + // Bit mask of HOST_SLC1HOST_RX_START_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_START_INT_RAW_Msk = 0x4000 + // Bit HOST_SLC1HOST_RX_START_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_RX_START_INT_RAW = 0x4000 + // Position of HOST_SLC1HOST_TX_START_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_TX_START_INT_RAW_Pos = 0xf + // Bit mask of HOST_SLC1HOST_TX_START_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_TX_START_INT_RAW_Msk = 0x8000 + // Bit HOST_SLC1HOST_TX_START_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1HOST_TX_START_INT_RAW = 0x8000 + // Position of HOST_SLC1_RX_UDF_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_UDF_INT_RAW_Pos = 0x10 + // Bit mask of HOST_SLC1_RX_UDF_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_UDF_INT_RAW_Msk = 0x10000 + // Bit HOST_SLC1_RX_UDF_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_UDF_INT_RAW = 0x10000 + // Position of HOST_SLC1_TX_OVF_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TX_OVF_INT_RAW_Pos = 0x11 + // Bit mask of HOST_SLC1_TX_OVF_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TX_OVF_INT_RAW_Msk = 0x20000 + // Bit HOST_SLC1_TX_OVF_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_TX_OVF_INT_RAW = 0x20000 + // Position of HOST_SLC1_RX_PF_VALID_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_PF_VALID_INT_RAW_Pos = 0x12 + // Bit mask of HOST_SLC1_RX_PF_VALID_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_PF_VALID_INT_RAW_Msk = 0x40000 + // Bit HOST_SLC1_RX_PF_VALID_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_RX_PF_VALID_INT_RAW = 0x40000 + // Position of HOST_SLC1_EXT_BIT0_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT0_INT_RAW_Pos = 0x13 + // Bit mask of HOST_SLC1_EXT_BIT0_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT0_INT_RAW_Msk = 0x80000 + // Bit HOST_SLC1_EXT_BIT0_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT0_INT_RAW = 0x80000 + // Position of HOST_SLC1_EXT_BIT1_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT1_INT_RAW_Pos = 0x14 + // Bit mask of HOST_SLC1_EXT_BIT1_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT1_INT_RAW_Msk = 0x100000 + // Bit HOST_SLC1_EXT_BIT1_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT1_INT_RAW = 0x100000 + // Position of HOST_SLC1_EXT_BIT2_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT2_INT_RAW_Pos = 0x15 + // Bit mask of HOST_SLC1_EXT_BIT2_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT2_INT_RAW_Msk = 0x200000 + // Bit HOST_SLC1_EXT_BIT2_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT2_INT_RAW = 0x200000 + // Position of HOST_SLC1_EXT_BIT3_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT3_INT_RAW_Pos = 0x16 + // Bit mask of HOST_SLC1_EXT_BIT3_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT3_INT_RAW_Msk = 0x400000 + // Bit HOST_SLC1_EXT_BIT3_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_EXT_BIT3_INT_RAW = 0x400000 + // Position of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_Pos = 0x17 + // Bit mask of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_Msk = 0x800000 + // Bit HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW = 0x800000 + // Position of HOST_SLC1_HOST_RD_RETRY_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_HOST_RD_RETRY_INT_RAW_Pos = 0x18 + // Bit mask of HOST_SLC1_HOST_RD_RETRY_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_HOST_RD_RETRY_INT_RAW_Msk = 0x1000000 + // Bit HOST_SLC1_HOST_RD_RETRY_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_HOST_RD_RETRY_INT_RAW = 0x1000000 + // Position of HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_Pos = 0x19 + // Bit mask of HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW field. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_Msk = 0x2000000 + // Bit HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW. + SLCHOST_HOST_SLC1HOST_INT_RAW_HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW = 0x2000000 + + // HOST_SLC0HOST_INT_ST + // Position of HOST_SLC0_TOHOST_BIT0_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT0_INT_ST_Pos = 0x0 + // Bit mask of HOST_SLC0_TOHOST_BIT0_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT0_INT_ST_Msk = 0x1 + // Bit HOST_SLC0_TOHOST_BIT0_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT0_INT_ST = 0x1 + // Position of HOST_SLC0_TOHOST_BIT1_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT1_INT_ST_Pos = 0x1 + // Bit mask of HOST_SLC0_TOHOST_BIT1_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT1_INT_ST_Msk = 0x2 + // Bit HOST_SLC0_TOHOST_BIT1_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT1_INT_ST = 0x2 + // Position of HOST_SLC0_TOHOST_BIT2_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT2_INT_ST_Pos = 0x2 + // Bit mask of HOST_SLC0_TOHOST_BIT2_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT2_INT_ST_Msk = 0x4 + // Bit HOST_SLC0_TOHOST_BIT2_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT2_INT_ST = 0x4 + // Position of HOST_SLC0_TOHOST_BIT3_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT3_INT_ST_Pos = 0x3 + // Bit mask of HOST_SLC0_TOHOST_BIT3_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT3_INT_ST_Msk = 0x8 + // Bit HOST_SLC0_TOHOST_BIT3_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT3_INT_ST = 0x8 + // Position of HOST_SLC0_TOHOST_BIT4_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT4_INT_ST_Pos = 0x4 + // Bit mask of HOST_SLC0_TOHOST_BIT4_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT4_INT_ST_Msk = 0x10 + // Bit HOST_SLC0_TOHOST_BIT4_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT4_INT_ST = 0x10 + // Position of HOST_SLC0_TOHOST_BIT5_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT5_INT_ST_Pos = 0x5 + // Bit mask of HOST_SLC0_TOHOST_BIT5_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT5_INT_ST_Msk = 0x20 + // Bit HOST_SLC0_TOHOST_BIT5_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT5_INT_ST = 0x20 + // Position of HOST_SLC0_TOHOST_BIT6_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT6_INT_ST_Pos = 0x6 + // Bit mask of HOST_SLC0_TOHOST_BIT6_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT6_INT_ST_Msk = 0x40 + // Bit HOST_SLC0_TOHOST_BIT6_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT6_INT_ST = 0x40 + // Position of HOST_SLC0_TOHOST_BIT7_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT7_INT_ST_Pos = 0x7 + // Bit mask of HOST_SLC0_TOHOST_BIT7_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT7_INT_ST_Msk = 0x80 + // Bit HOST_SLC0_TOHOST_BIT7_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOHOST_BIT7_INT_ST = 0x80 + // Position of HOST_SLC0_TOKEN0_1TO0_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_1TO0_INT_ST_Pos = 0x8 + // Bit mask of HOST_SLC0_TOKEN0_1TO0_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_1TO0_INT_ST_Msk = 0x100 + // Bit HOST_SLC0_TOKEN0_1TO0_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_1TO0_INT_ST = 0x100 + // Position of HOST_SLC0_TOKEN1_1TO0_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_1TO0_INT_ST_Pos = 0x9 + // Bit mask of HOST_SLC0_TOKEN1_1TO0_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_1TO0_INT_ST_Msk = 0x200 + // Bit HOST_SLC0_TOKEN1_1TO0_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_1TO0_INT_ST = 0x200 + // Position of HOST_SLC0_TOKEN0_0TO1_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_0TO1_INT_ST_Pos = 0xa + // Bit mask of HOST_SLC0_TOKEN0_0TO1_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_0TO1_INT_ST_Msk = 0x400 + // Bit HOST_SLC0_TOKEN0_0TO1_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN0_0TO1_INT_ST = 0x400 + // Position of HOST_SLC0_TOKEN1_0TO1_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_0TO1_INT_ST_Pos = 0xb + // Bit mask of HOST_SLC0_TOKEN1_0TO1_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_0TO1_INT_ST_Msk = 0x800 + // Bit HOST_SLC0_TOKEN1_0TO1_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TOKEN1_0TO1_INT_ST = 0x800 + // Position of HOST_SLC0HOST_RX_SOF_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_SOF_INT_ST_Pos = 0xc + // Bit mask of HOST_SLC0HOST_RX_SOF_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_SOF_INT_ST_Msk = 0x1000 + // Bit HOST_SLC0HOST_RX_SOF_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_SOF_INT_ST = 0x1000 + // Position of HOST_SLC0HOST_RX_EOF_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_EOF_INT_ST_Pos = 0xd + // Bit mask of HOST_SLC0HOST_RX_EOF_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_EOF_INT_ST_Msk = 0x2000 + // Bit HOST_SLC0HOST_RX_EOF_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_EOF_INT_ST = 0x2000 + // Position of HOST_SLC0HOST_RX_START_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_START_INT_ST_Pos = 0xe + // Bit mask of HOST_SLC0HOST_RX_START_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_START_INT_ST_Msk = 0x4000 + // Bit HOST_SLC0HOST_RX_START_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_RX_START_INT_ST = 0x4000 + // Position of HOST_SLC0HOST_TX_START_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_TX_START_INT_ST_Pos = 0xf + // Bit mask of HOST_SLC0HOST_TX_START_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_TX_START_INT_ST_Msk = 0x8000 + // Bit HOST_SLC0HOST_TX_START_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0HOST_TX_START_INT_ST = 0x8000 + // Position of HOST_SLC0_RX_UDF_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_RX_UDF_INT_ST_Pos = 0x10 + // Bit mask of HOST_SLC0_RX_UDF_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_RX_UDF_INT_ST_Msk = 0x10000 + // Bit HOST_SLC0_RX_UDF_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_RX_UDF_INT_ST = 0x10000 + // Position of HOST_SLC0_TX_OVF_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TX_OVF_INT_ST_Pos = 0x11 + // Bit mask of HOST_SLC0_TX_OVF_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TX_OVF_INT_ST_Msk = 0x20000 + // Bit HOST_SLC0_TX_OVF_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_TX_OVF_INT_ST = 0x20000 + // Position of HOST_SLC0_RX_PF_VALID_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_RX_PF_VALID_INT_ST_Pos = 0x12 + // Bit mask of HOST_SLC0_RX_PF_VALID_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_RX_PF_VALID_INT_ST_Msk = 0x40000 + // Bit HOST_SLC0_RX_PF_VALID_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_RX_PF_VALID_INT_ST = 0x40000 + // Position of HOST_SLC0_EXT_BIT0_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT0_INT_ST_Pos = 0x13 + // Bit mask of HOST_SLC0_EXT_BIT0_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT0_INT_ST_Msk = 0x80000 + // Bit HOST_SLC0_EXT_BIT0_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT0_INT_ST = 0x80000 + // Position of HOST_SLC0_EXT_BIT1_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT1_INT_ST_Pos = 0x14 + // Bit mask of HOST_SLC0_EXT_BIT1_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT1_INT_ST_Msk = 0x100000 + // Bit HOST_SLC0_EXT_BIT1_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT1_INT_ST = 0x100000 + // Position of HOST_SLC0_EXT_BIT2_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT2_INT_ST_Pos = 0x15 + // Bit mask of HOST_SLC0_EXT_BIT2_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT2_INT_ST_Msk = 0x200000 + // Bit HOST_SLC0_EXT_BIT2_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT2_INT_ST = 0x200000 + // Position of HOST_SLC0_EXT_BIT3_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT3_INT_ST_Pos = 0x16 + // Bit mask of HOST_SLC0_EXT_BIT3_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT3_INT_ST_Msk = 0x400000 + // Bit HOST_SLC0_EXT_BIT3_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_EXT_BIT3_INT_ST = 0x400000 + // Position of HOST_SLC0_RX_NEW_PACKET_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_RX_NEW_PACKET_INT_ST_Pos = 0x17 + // Bit mask of HOST_SLC0_RX_NEW_PACKET_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_RX_NEW_PACKET_INT_ST_Msk = 0x800000 + // Bit HOST_SLC0_RX_NEW_PACKET_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_RX_NEW_PACKET_INT_ST = 0x800000 + // Position of HOST_SLC0_HOST_RD_RETRY_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_HOST_RD_RETRY_INT_ST_Pos = 0x18 + // Bit mask of HOST_SLC0_HOST_RD_RETRY_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_HOST_RD_RETRY_INT_ST_Msk = 0x1000000 + // Bit HOST_SLC0_HOST_RD_RETRY_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_SLC0_HOST_RD_RETRY_INT_ST = 0x1000000 + // Position of HOST_GPIO_SDIO_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_GPIO_SDIO_INT_ST_Pos = 0x19 + // Bit mask of HOST_GPIO_SDIO_INT_ST field. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_GPIO_SDIO_INT_ST_Msk = 0x2000000 + // Bit HOST_GPIO_SDIO_INT_ST. + SLCHOST_HOST_SLC0HOST_INT_ST_HOST_GPIO_SDIO_INT_ST = 0x2000000 + + // HOST_SLC1HOST_INT_ST + // Position of HOST_SLC1_TOHOST_BIT0_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT0_INT_ST_Pos = 0x0 + // Bit mask of HOST_SLC1_TOHOST_BIT0_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT0_INT_ST_Msk = 0x1 + // Bit HOST_SLC1_TOHOST_BIT0_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT0_INT_ST = 0x1 + // Position of HOST_SLC1_TOHOST_BIT1_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT1_INT_ST_Pos = 0x1 + // Bit mask of HOST_SLC1_TOHOST_BIT1_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT1_INT_ST_Msk = 0x2 + // Bit HOST_SLC1_TOHOST_BIT1_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT1_INT_ST = 0x2 + // Position of HOST_SLC1_TOHOST_BIT2_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT2_INT_ST_Pos = 0x2 + // Bit mask of HOST_SLC1_TOHOST_BIT2_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT2_INT_ST_Msk = 0x4 + // Bit HOST_SLC1_TOHOST_BIT2_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT2_INT_ST = 0x4 + // Position of HOST_SLC1_TOHOST_BIT3_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT3_INT_ST_Pos = 0x3 + // Bit mask of HOST_SLC1_TOHOST_BIT3_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT3_INT_ST_Msk = 0x8 + // Bit HOST_SLC1_TOHOST_BIT3_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT3_INT_ST = 0x8 + // Position of HOST_SLC1_TOHOST_BIT4_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT4_INT_ST_Pos = 0x4 + // Bit mask of HOST_SLC1_TOHOST_BIT4_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT4_INT_ST_Msk = 0x10 + // Bit HOST_SLC1_TOHOST_BIT4_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT4_INT_ST = 0x10 + // Position of HOST_SLC1_TOHOST_BIT5_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT5_INT_ST_Pos = 0x5 + // Bit mask of HOST_SLC1_TOHOST_BIT5_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT5_INT_ST_Msk = 0x20 + // Bit HOST_SLC1_TOHOST_BIT5_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT5_INT_ST = 0x20 + // Position of HOST_SLC1_TOHOST_BIT6_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT6_INT_ST_Pos = 0x6 + // Bit mask of HOST_SLC1_TOHOST_BIT6_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT6_INT_ST_Msk = 0x40 + // Bit HOST_SLC1_TOHOST_BIT6_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT6_INT_ST = 0x40 + // Position of HOST_SLC1_TOHOST_BIT7_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT7_INT_ST_Pos = 0x7 + // Bit mask of HOST_SLC1_TOHOST_BIT7_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT7_INT_ST_Msk = 0x80 + // Bit HOST_SLC1_TOHOST_BIT7_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOHOST_BIT7_INT_ST = 0x80 + // Position of HOST_SLC1_TOKEN0_1TO0_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_1TO0_INT_ST_Pos = 0x8 + // Bit mask of HOST_SLC1_TOKEN0_1TO0_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_1TO0_INT_ST_Msk = 0x100 + // Bit HOST_SLC1_TOKEN0_1TO0_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_1TO0_INT_ST = 0x100 + // Position of HOST_SLC1_TOKEN1_1TO0_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_1TO0_INT_ST_Pos = 0x9 + // Bit mask of HOST_SLC1_TOKEN1_1TO0_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_1TO0_INT_ST_Msk = 0x200 + // Bit HOST_SLC1_TOKEN1_1TO0_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_1TO0_INT_ST = 0x200 + // Position of HOST_SLC1_TOKEN0_0TO1_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_0TO1_INT_ST_Pos = 0xa + // Bit mask of HOST_SLC1_TOKEN0_0TO1_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_0TO1_INT_ST_Msk = 0x400 + // Bit HOST_SLC1_TOKEN0_0TO1_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN0_0TO1_INT_ST = 0x400 + // Position of HOST_SLC1_TOKEN1_0TO1_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_0TO1_INT_ST_Pos = 0xb + // Bit mask of HOST_SLC1_TOKEN1_0TO1_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_0TO1_INT_ST_Msk = 0x800 + // Bit HOST_SLC1_TOKEN1_0TO1_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TOKEN1_0TO1_INT_ST = 0x800 + // Position of HOST_SLC1HOST_RX_SOF_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_SOF_INT_ST_Pos = 0xc + // Bit mask of HOST_SLC1HOST_RX_SOF_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_SOF_INT_ST_Msk = 0x1000 + // Bit HOST_SLC1HOST_RX_SOF_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_SOF_INT_ST = 0x1000 + // Position of HOST_SLC1HOST_RX_EOF_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_EOF_INT_ST_Pos = 0xd + // Bit mask of HOST_SLC1HOST_RX_EOF_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_EOF_INT_ST_Msk = 0x2000 + // Bit HOST_SLC1HOST_RX_EOF_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_EOF_INT_ST = 0x2000 + // Position of HOST_SLC1HOST_RX_START_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_START_INT_ST_Pos = 0xe + // Bit mask of HOST_SLC1HOST_RX_START_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_START_INT_ST_Msk = 0x4000 + // Bit HOST_SLC1HOST_RX_START_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_RX_START_INT_ST = 0x4000 + // Position of HOST_SLC1HOST_TX_START_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_TX_START_INT_ST_Pos = 0xf + // Bit mask of HOST_SLC1HOST_TX_START_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_TX_START_INT_ST_Msk = 0x8000 + // Bit HOST_SLC1HOST_TX_START_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1HOST_TX_START_INT_ST = 0x8000 + // Position of HOST_SLC1_RX_UDF_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_RX_UDF_INT_ST_Pos = 0x10 + // Bit mask of HOST_SLC1_RX_UDF_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_RX_UDF_INT_ST_Msk = 0x10000 + // Bit HOST_SLC1_RX_UDF_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_RX_UDF_INT_ST = 0x10000 + // Position of HOST_SLC1_TX_OVF_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TX_OVF_INT_ST_Pos = 0x11 + // Bit mask of HOST_SLC1_TX_OVF_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TX_OVF_INT_ST_Msk = 0x20000 + // Bit HOST_SLC1_TX_OVF_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_TX_OVF_INT_ST = 0x20000 + // Position of HOST_SLC1_RX_PF_VALID_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_RX_PF_VALID_INT_ST_Pos = 0x12 + // Bit mask of HOST_SLC1_RX_PF_VALID_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_RX_PF_VALID_INT_ST_Msk = 0x40000 + // Bit HOST_SLC1_RX_PF_VALID_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_RX_PF_VALID_INT_ST = 0x40000 + // Position of HOST_SLC1_EXT_BIT0_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT0_INT_ST_Pos = 0x13 + // Bit mask of HOST_SLC1_EXT_BIT0_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT0_INT_ST_Msk = 0x80000 + // Bit HOST_SLC1_EXT_BIT0_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT0_INT_ST = 0x80000 + // Position of HOST_SLC1_EXT_BIT1_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT1_INT_ST_Pos = 0x14 + // Bit mask of HOST_SLC1_EXT_BIT1_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT1_INT_ST_Msk = 0x100000 + // Bit HOST_SLC1_EXT_BIT1_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT1_INT_ST = 0x100000 + // Position of HOST_SLC1_EXT_BIT2_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT2_INT_ST_Pos = 0x15 + // Bit mask of HOST_SLC1_EXT_BIT2_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT2_INT_ST_Msk = 0x200000 + // Bit HOST_SLC1_EXT_BIT2_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT2_INT_ST = 0x200000 + // Position of HOST_SLC1_EXT_BIT3_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT3_INT_ST_Pos = 0x16 + // Bit mask of HOST_SLC1_EXT_BIT3_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT3_INT_ST_Msk = 0x400000 + // Bit HOST_SLC1_EXT_BIT3_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_EXT_BIT3_INT_ST = 0x400000 + // Position of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_Pos = 0x17 + // Bit mask of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_Msk = 0x800000 + // Bit HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST = 0x800000 + // Position of HOST_SLC1_HOST_RD_RETRY_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_HOST_RD_RETRY_INT_ST_Pos = 0x18 + // Bit mask of HOST_SLC1_HOST_RD_RETRY_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_HOST_RD_RETRY_INT_ST_Msk = 0x1000000 + // Bit HOST_SLC1_HOST_RD_RETRY_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_HOST_RD_RETRY_INT_ST = 0x1000000 + // Position of HOST_SLC1_BT_RX_NEW_PACKET_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_Pos = 0x19 + // Bit mask of HOST_SLC1_BT_RX_NEW_PACKET_INT_ST field. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_Msk = 0x2000000 + // Bit HOST_SLC1_BT_RX_NEW_PACKET_INT_ST. + SLCHOST_HOST_SLC1HOST_INT_ST_HOST_SLC1_BT_RX_NEW_PACKET_INT_ST = 0x2000000 + + // HOST_SLCHOST_PKT_LEN + // Position of HOST_HOSTSLC0_LEN field. + SLCHOST_HOST_SLCHOST_PKT_LEN_HOST_HOSTSLC0_LEN_Pos = 0x0 + // Bit mask of HOST_HOSTSLC0_LEN field. + SLCHOST_HOST_SLCHOST_PKT_LEN_HOST_HOSTSLC0_LEN_Msk = 0xfffff + // Position of HOST_HOSTSLC0_LEN_CHECK field. + SLCHOST_HOST_SLCHOST_PKT_LEN_HOST_HOSTSLC0_LEN_CHECK_Pos = 0x14 + // Bit mask of HOST_HOSTSLC0_LEN_CHECK field. + SLCHOST_HOST_SLCHOST_PKT_LEN_HOST_HOSTSLC0_LEN_CHECK_Msk = 0xfff00000 + + // HOST_SLCHOST_STATE_W0 + // Position of HOST_SLCHOST_STATE0 field. + SLCHOST_HOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE0_Pos = 0x0 + // Bit mask of HOST_SLCHOST_STATE0 field. + SLCHOST_HOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE0_Msk = 0xff + // Position of HOST_SLCHOST_STATE1 field. + SLCHOST_HOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE1_Pos = 0x8 + // Bit mask of HOST_SLCHOST_STATE1 field. + SLCHOST_HOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE1_Msk = 0xff00 + // Position of HOST_SLCHOST_STATE2 field. + SLCHOST_HOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE2_Pos = 0x10 + // Bit mask of HOST_SLCHOST_STATE2 field. + SLCHOST_HOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE2_Msk = 0xff0000 + // Position of HOST_SLCHOST_STATE3 field. + SLCHOST_HOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE3_Pos = 0x18 + // Bit mask of HOST_SLCHOST_STATE3 field. + SLCHOST_HOST_SLCHOST_STATE_W0_HOST_SLCHOST_STATE3_Msk = 0xff000000 + + // HOST_SLCHOST_STATE_W1 + // Position of HOST_SLCHOST_STATE4 field. + SLCHOST_HOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE4_Pos = 0x0 + // Bit mask of HOST_SLCHOST_STATE4 field. + SLCHOST_HOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE4_Msk = 0xff + // Position of HOST_SLCHOST_STATE5 field. + SLCHOST_HOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE5_Pos = 0x8 + // Bit mask of HOST_SLCHOST_STATE5 field. + SLCHOST_HOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE5_Msk = 0xff00 + // Position of HOST_SLCHOST_STATE6 field. + SLCHOST_HOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE6_Pos = 0x10 + // Bit mask of HOST_SLCHOST_STATE6 field. + SLCHOST_HOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE6_Msk = 0xff0000 + // Position of HOST_SLCHOST_STATE7 field. + SLCHOST_HOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE7_Pos = 0x18 + // Bit mask of HOST_SLCHOST_STATE7 field. + SLCHOST_HOST_SLCHOST_STATE_W1_HOST_SLCHOST_STATE7_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W0 + // Position of HOST_SLCHOST_CONF0 field. + SLCHOST_HOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF0_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF0 field. + SLCHOST_HOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF0_Msk = 0xff + // Position of HOST_SLCHOST_CONF1 field. + SLCHOST_HOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF1_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF1 field. + SLCHOST_HOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF1_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF2 field. + SLCHOST_HOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF2_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF2 field. + SLCHOST_HOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF2_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF3 field. + SLCHOST_HOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF3_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF3 field. + SLCHOST_HOST_SLCHOST_CONF_W0_HOST_SLCHOST_CONF3_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W1 + // Position of HOST_SLCHOST_CONF4 field. + SLCHOST_HOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF4_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF4 field. + SLCHOST_HOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF4_Msk = 0xff + // Position of HOST_SLCHOST_CONF5 field. + SLCHOST_HOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF5_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF5 field. + SLCHOST_HOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF5_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF6 field. + SLCHOST_HOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF6_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF6 field. + SLCHOST_HOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF6_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF7 field. + SLCHOST_HOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF7_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF7 field. + SLCHOST_HOST_SLCHOST_CONF_W1_HOST_SLCHOST_CONF7_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W2 + // Position of HOST_SLCHOST_CONF8 field. + SLCHOST_HOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF8_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF8 field. + SLCHOST_HOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF8_Msk = 0xff + // Position of HOST_SLCHOST_CONF9 field. + SLCHOST_HOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF9_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF9 field. + SLCHOST_HOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF9_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF10 field. + SLCHOST_HOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF10_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF10 field. + SLCHOST_HOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF10_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF11 field. + SLCHOST_HOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF11_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF11 field. + SLCHOST_HOST_SLCHOST_CONF_W2_HOST_SLCHOST_CONF11_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W3 + // Position of HOST_SLCHOST_CONF12 field. + SLCHOST_HOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF12_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF12 field. + SLCHOST_HOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF12_Msk = 0xff + // Position of HOST_SLCHOST_CONF13 field. + SLCHOST_HOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF13_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF13 field. + SLCHOST_HOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF13_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF14 field. + SLCHOST_HOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF14_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF14 field. + SLCHOST_HOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF14_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF15 field. + SLCHOST_HOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF15_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF15 field. + SLCHOST_HOST_SLCHOST_CONF_W3_HOST_SLCHOST_CONF15_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W4 + // Position of HOST_SLCHOST_CONF16 field. + SLCHOST_HOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF16_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF16 field. + SLCHOST_HOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF16_Msk = 0xff + // Position of HOST_SLCHOST_CONF17 field. + SLCHOST_HOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF17_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF17 field. + SLCHOST_HOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF17_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF18 field. + SLCHOST_HOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF18_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF18 field. + SLCHOST_HOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF18_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF19 field. + SLCHOST_HOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF19_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF19 field. + SLCHOST_HOST_SLCHOST_CONF_W4_HOST_SLCHOST_CONF19_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W5 + // Position of HOST_SLCHOST_CONF20 field. + SLCHOST_HOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF20_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF20 field. + SLCHOST_HOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF20_Msk = 0xff + // Position of HOST_SLCHOST_CONF21 field. + SLCHOST_HOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF21_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF21 field. + SLCHOST_HOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF21_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF22 field. + SLCHOST_HOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF22_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF22 field. + SLCHOST_HOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF22_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF23 field. + SLCHOST_HOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF23_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF23 field. + SLCHOST_HOST_SLCHOST_CONF_W5_HOST_SLCHOST_CONF23_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W6 + // Position of HOST_SLCHOST_CONF24 field. + SLCHOST_HOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF24_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF24 field. + SLCHOST_HOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF24_Msk = 0xff + // Position of HOST_SLCHOST_CONF25 field. + SLCHOST_HOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF25_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF25 field. + SLCHOST_HOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF25_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF26 field. + SLCHOST_HOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF26_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF26 field. + SLCHOST_HOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF26_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF27 field. + SLCHOST_HOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF27_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF27 field. + SLCHOST_HOST_SLCHOST_CONF_W6_HOST_SLCHOST_CONF27_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W7 + // Position of HOST_SLCHOST_CONF28 field. + SLCHOST_HOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF28_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF28 field. + SLCHOST_HOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF28_Msk = 0xff + // Position of HOST_SLCHOST_CONF29 field. + SLCHOST_HOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF29_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF29 field. + SLCHOST_HOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF29_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF30 field. + SLCHOST_HOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF30_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF30 field. + SLCHOST_HOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF30_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF31 field. + SLCHOST_HOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF31_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF31 field. + SLCHOST_HOST_SLCHOST_CONF_W7_HOST_SLCHOST_CONF31_Msk = 0xff000000 + + // HOST_SLCHOST_PKT_LEN0 + // Position of HOST_HOSTSLC0_LEN0 field. + SLCHOST_HOST_SLCHOST_PKT_LEN0_HOST_HOSTSLC0_LEN0_Pos = 0x0 + // Bit mask of HOST_HOSTSLC0_LEN0 field. + SLCHOST_HOST_SLCHOST_PKT_LEN0_HOST_HOSTSLC0_LEN0_Msk = 0xfffff + + // HOST_SLCHOST_PKT_LEN1 + // Position of HOST_HOSTSLC0_LEN1 field. + SLCHOST_HOST_SLCHOST_PKT_LEN1_HOST_HOSTSLC0_LEN1_Pos = 0x0 + // Bit mask of HOST_HOSTSLC0_LEN1 field. + SLCHOST_HOST_SLCHOST_PKT_LEN1_HOST_HOSTSLC0_LEN1_Msk = 0xfffff + + // HOST_SLCHOST_PKT_LEN2 + // Position of HOST_HOSTSLC0_LEN2 field. + SLCHOST_HOST_SLCHOST_PKT_LEN2_HOST_HOSTSLC0_LEN2_Pos = 0x0 + // Bit mask of HOST_HOSTSLC0_LEN2 field. + SLCHOST_HOST_SLCHOST_PKT_LEN2_HOST_HOSTSLC0_LEN2_Msk = 0xfffff + + // HOST_SLCHOST_CONF_W8 + // Position of HOST_SLCHOST_CONF32 field. + SLCHOST_HOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF32_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF32 field. + SLCHOST_HOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF32_Msk = 0xff + // Position of HOST_SLCHOST_CONF33 field. + SLCHOST_HOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF33_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF33 field. + SLCHOST_HOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF33_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF34 field. + SLCHOST_HOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF34_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF34 field. + SLCHOST_HOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF34_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF35 field. + SLCHOST_HOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF35_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF35 field. + SLCHOST_HOST_SLCHOST_CONF_W8_HOST_SLCHOST_CONF35_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W9 + // Position of HOST_SLCHOST_CONF36 field. + SLCHOST_HOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF36_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF36 field. + SLCHOST_HOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF36_Msk = 0xff + // Position of HOST_SLCHOST_CONF37 field. + SLCHOST_HOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF37_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF37 field. + SLCHOST_HOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF37_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF38 field. + SLCHOST_HOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF38_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF38 field. + SLCHOST_HOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF38_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF39 field. + SLCHOST_HOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF39_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF39 field. + SLCHOST_HOST_SLCHOST_CONF_W9_HOST_SLCHOST_CONF39_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W10 + // Position of HOST_SLCHOST_CONF40 field. + SLCHOST_HOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF40_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF40 field. + SLCHOST_HOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF40_Msk = 0xff + // Position of HOST_SLCHOST_CONF41 field. + SLCHOST_HOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF41_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF41 field. + SLCHOST_HOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF41_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF42 field. + SLCHOST_HOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF42_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF42 field. + SLCHOST_HOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF42_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF43 field. + SLCHOST_HOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF43_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF43 field. + SLCHOST_HOST_SLCHOST_CONF_W10_HOST_SLCHOST_CONF43_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W11 + // Position of HOST_SLCHOST_CONF44 field. + SLCHOST_HOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF44_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF44 field. + SLCHOST_HOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF44_Msk = 0xff + // Position of HOST_SLCHOST_CONF45 field. + SLCHOST_HOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF45_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF45 field. + SLCHOST_HOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF45_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF46 field. + SLCHOST_HOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF46_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF46 field. + SLCHOST_HOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF46_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF47 field. + SLCHOST_HOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF47_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF47 field. + SLCHOST_HOST_SLCHOST_CONF_W11_HOST_SLCHOST_CONF47_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W12 + // Position of HOST_SLCHOST_CONF48 field. + SLCHOST_HOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF48_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF48 field. + SLCHOST_HOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF48_Msk = 0xff + // Position of HOST_SLCHOST_CONF49 field. + SLCHOST_HOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF49_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF49 field. + SLCHOST_HOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF49_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF50 field. + SLCHOST_HOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF50_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF50 field. + SLCHOST_HOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF50_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF51 field. + SLCHOST_HOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF51_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF51 field. + SLCHOST_HOST_SLCHOST_CONF_W12_HOST_SLCHOST_CONF51_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W13 + // Position of HOST_SLCHOST_CONF52 field. + SLCHOST_HOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF52_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF52 field. + SLCHOST_HOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF52_Msk = 0xff + // Position of HOST_SLCHOST_CONF53 field. + SLCHOST_HOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF53_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF53 field. + SLCHOST_HOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF53_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF54 field. + SLCHOST_HOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF54_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF54 field. + SLCHOST_HOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF54_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF55 field. + SLCHOST_HOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF55_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF55 field. + SLCHOST_HOST_SLCHOST_CONF_W13_HOST_SLCHOST_CONF55_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W14 + // Position of HOST_SLCHOST_CONF56 field. + SLCHOST_HOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF56_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF56 field. + SLCHOST_HOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF56_Msk = 0xff + // Position of HOST_SLCHOST_CONF57 field. + SLCHOST_HOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF57_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF57 field. + SLCHOST_HOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF57_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF58 field. + SLCHOST_HOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF58_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF58 field. + SLCHOST_HOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF58_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF59 field. + SLCHOST_HOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF59_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF59 field. + SLCHOST_HOST_SLCHOST_CONF_W14_HOST_SLCHOST_CONF59_Msk = 0xff000000 + + // HOST_SLCHOST_CONF_W15 + // Position of HOST_SLCHOST_CONF60 field. + SLCHOST_HOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF60_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CONF60 field. + SLCHOST_HOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF60_Msk = 0xff + // Position of HOST_SLCHOST_CONF61 field. + SLCHOST_HOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF61_Pos = 0x8 + // Bit mask of HOST_SLCHOST_CONF61 field. + SLCHOST_HOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF61_Msk = 0xff00 + // Position of HOST_SLCHOST_CONF62 field. + SLCHOST_HOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF62_Pos = 0x10 + // Bit mask of HOST_SLCHOST_CONF62 field. + SLCHOST_HOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF62_Msk = 0xff0000 + // Position of HOST_SLCHOST_CONF63 field. + SLCHOST_HOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF63_Pos = 0x18 + // Bit mask of HOST_SLCHOST_CONF63 field. + SLCHOST_HOST_SLCHOST_CONF_W15_HOST_SLCHOST_CONF63_Msk = 0xff000000 + + // HOST_SLCHOST_CHECK_SUM0 + // Position of HOST_SLCHOST_CHECK_SUM0 field. + SLCHOST_HOST_SLCHOST_CHECK_SUM0_HOST_SLCHOST_CHECK_SUM0_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CHECK_SUM0 field. + SLCHOST_HOST_SLCHOST_CHECK_SUM0_HOST_SLCHOST_CHECK_SUM0_Msk = 0xffffffff + + // HOST_SLCHOST_CHECK_SUM1 + // Position of HOST_SLCHOST_CHECK_SUM1 field. + SLCHOST_HOST_SLCHOST_CHECK_SUM1_HOST_SLCHOST_CHECK_SUM1_Pos = 0x0 + // Bit mask of HOST_SLCHOST_CHECK_SUM1 field. + SLCHOST_HOST_SLCHOST_CHECK_SUM1_HOST_SLCHOST_CHECK_SUM1_Msk = 0xffffffff + + // HOST_SLC1HOST_TOKEN_RDATA + // Position of HOST_SLC1_TOKEN0 field. + SLCHOST_HOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_TOKEN0_Pos = 0x0 + // Bit mask of HOST_SLC1_TOKEN0 field. + SLCHOST_HOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_TOKEN0_Msk = 0xfff + // Position of HOST_SLC1_RX_PF_VALID field. + SLCHOST_HOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_RX_PF_VALID_Pos = 0xc + // Bit mask of HOST_SLC1_RX_PF_VALID field. + SLCHOST_HOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_RX_PF_VALID_Msk = 0x1000 + // Bit HOST_SLC1_RX_PF_VALID. + SLCHOST_HOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_RX_PF_VALID = 0x1000 + // Position of HOST_HOSTSLC1_TOKEN1 field. + SLCHOST_HOST_SLC1HOST_TOKEN_RDATA_HOST_HOSTSLC1_TOKEN1_Pos = 0x10 + // Bit mask of HOST_HOSTSLC1_TOKEN1 field. + SLCHOST_HOST_SLC1HOST_TOKEN_RDATA_HOST_HOSTSLC1_TOKEN1_Msk = 0xfff0000 + // Position of HOST_SLC1_RX_PF_EOF field. + SLCHOST_HOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_RX_PF_EOF_Pos = 0x1c + // Bit mask of HOST_SLC1_RX_PF_EOF field. + SLCHOST_HOST_SLC1HOST_TOKEN_RDATA_HOST_SLC1_RX_PF_EOF_Msk = 0xf0000000 + + // HOST_SLC0HOST_TOKEN_WDATA + // Position of HOST_SLC0HOST_TOKEN0_WD field. + SLCHOST_HOST_SLC0HOST_TOKEN_WDATA_HOST_SLC0HOST_TOKEN0_WD_Pos = 0x0 + // Bit mask of HOST_SLC0HOST_TOKEN0_WD field. + SLCHOST_HOST_SLC0HOST_TOKEN_WDATA_HOST_SLC0HOST_TOKEN0_WD_Msk = 0xfff + // Position of HOST_SLC0HOST_TOKEN1_WD field. + SLCHOST_HOST_SLC0HOST_TOKEN_WDATA_HOST_SLC0HOST_TOKEN1_WD_Pos = 0x10 + // Bit mask of HOST_SLC0HOST_TOKEN1_WD field. + SLCHOST_HOST_SLC0HOST_TOKEN_WDATA_HOST_SLC0HOST_TOKEN1_WD_Msk = 0xfff0000 + + // HOST_SLC1HOST_TOKEN_WDATA + // Position of HOST_SLC1HOST_TOKEN0_WD field. + SLCHOST_HOST_SLC1HOST_TOKEN_WDATA_HOST_SLC1HOST_TOKEN0_WD_Pos = 0x0 + // Bit mask of HOST_SLC1HOST_TOKEN0_WD field. + SLCHOST_HOST_SLC1HOST_TOKEN_WDATA_HOST_SLC1HOST_TOKEN0_WD_Msk = 0xfff + // Position of HOST_SLC1HOST_TOKEN1_WD field. + SLCHOST_HOST_SLC1HOST_TOKEN_WDATA_HOST_SLC1HOST_TOKEN1_WD_Pos = 0x10 + // Bit mask of HOST_SLC1HOST_TOKEN1_WD field. + SLCHOST_HOST_SLC1HOST_TOKEN_WDATA_HOST_SLC1HOST_TOKEN1_WD_Msk = 0xfff0000 + + // HOST_SLCHOST_TOKEN_CON + // Position of HOST_SLC0HOST_TOKEN0_DEC field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_DEC_Pos = 0x0 + // Bit mask of HOST_SLC0HOST_TOKEN0_DEC field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_DEC_Msk = 0x1 + // Bit HOST_SLC0HOST_TOKEN0_DEC. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_DEC = 0x1 + // Position of HOST_SLC0HOST_TOKEN1_DEC field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_DEC_Pos = 0x1 + // Bit mask of HOST_SLC0HOST_TOKEN1_DEC field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_DEC_Msk = 0x2 + // Bit HOST_SLC0HOST_TOKEN1_DEC. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_DEC = 0x2 + // Position of HOST_SLC0HOST_TOKEN0_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_WR_Pos = 0x2 + // Bit mask of HOST_SLC0HOST_TOKEN0_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_WR_Msk = 0x4 + // Bit HOST_SLC0HOST_TOKEN0_WR. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN0_WR = 0x4 + // Position of HOST_SLC0HOST_TOKEN1_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_WR_Pos = 0x3 + // Bit mask of HOST_SLC0HOST_TOKEN1_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_WR_Msk = 0x8 + // Bit HOST_SLC0HOST_TOKEN1_WR. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_TOKEN1_WR = 0x8 + // Position of HOST_SLC1HOST_TOKEN0_DEC field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_DEC_Pos = 0x4 + // Bit mask of HOST_SLC1HOST_TOKEN0_DEC field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_DEC_Msk = 0x10 + // Bit HOST_SLC1HOST_TOKEN0_DEC. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_DEC = 0x10 + // Position of HOST_SLC1HOST_TOKEN1_DEC field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_DEC_Pos = 0x5 + // Bit mask of HOST_SLC1HOST_TOKEN1_DEC field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_DEC_Msk = 0x20 + // Bit HOST_SLC1HOST_TOKEN1_DEC. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_DEC = 0x20 + // Position of HOST_SLC1HOST_TOKEN0_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_WR_Pos = 0x6 + // Bit mask of HOST_SLC1HOST_TOKEN0_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_WR_Msk = 0x40 + // Bit HOST_SLC1HOST_TOKEN0_WR. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN0_WR = 0x40 + // Position of HOST_SLC1HOST_TOKEN1_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_WR_Pos = 0x7 + // Bit mask of HOST_SLC1HOST_TOKEN1_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_WR_Msk = 0x80 + // Bit HOST_SLC1HOST_TOKEN1_WR. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC1HOST_TOKEN1_WR = 0x80 + // Position of HOST_SLC0HOST_LEN_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_LEN_WR_Pos = 0x8 + // Bit mask of HOST_SLC0HOST_LEN_WR field. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_LEN_WR_Msk = 0x100 + // Bit HOST_SLC0HOST_LEN_WR. + SLCHOST_HOST_SLCHOST_TOKEN_CON_HOST_SLC0HOST_LEN_WR = 0x100 + + // HOST_SLC0HOST_INT_CLR + // Position of HOST_SLC0_TOHOST_BIT0_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT0_INT_CLR_Pos = 0x0 + // Bit mask of HOST_SLC0_TOHOST_BIT0_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT0_INT_CLR_Msk = 0x1 + // Bit HOST_SLC0_TOHOST_BIT0_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT0_INT_CLR = 0x1 + // Position of HOST_SLC0_TOHOST_BIT1_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT1_INT_CLR_Pos = 0x1 + // Bit mask of HOST_SLC0_TOHOST_BIT1_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT1_INT_CLR_Msk = 0x2 + // Bit HOST_SLC0_TOHOST_BIT1_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT1_INT_CLR = 0x2 + // Position of HOST_SLC0_TOHOST_BIT2_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT2_INT_CLR_Pos = 0x2 + // Bit mask of HOST_SLC0_TOHOST_BIT2_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT2_INT_CLR_Msk = 0x4 + // Bit HOST_SLC0_TOHOST_BIT2_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT2_INT_CLR = 0x4 + // Position of HOST_SLC0_TOHOST_BIT3_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT3_INT_CLR_Pos = 0x3 + // Bit mask of HOST_SLC0_TOHOST_BIT3_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT3_INT_CLR_Msk = 0x8 + // Bit HOST_SLC0_TOHOST_BIT3_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT3_INT_CLR = 0x8 + // Position of HOST_SLC0_TOHOST_BIT4_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT4_INT_CLR_Pos = 0x4 + // Bit mask of HOST_SLC0_TOHOST_BIT4_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT4_INT_CLR_Msk = 0x10 + // Bit HOST_SLC0_TOHOST_BIT4_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT4_INT_CLR = 0x10 + // Position of HOST_SLC0_TOHOST_BIT5_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT5_INT_CLR_Pos = 0x5 + // Bit mask of HOST_SLC0_TOHOST_BIT5_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT5_INT_CLR_Msk = 0x20 + // Bit HOST_SLC0_TOHOST_BIT5_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT5_INT_CLR = 0x20 + // Position of HOST_SLC0_TOHOST_BIT6_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT6_INT_CLR_Pos = 0x6 + // Bit mask of HOST_SLC0_TOHOST_BIT6_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT6_INT_CLR_Msk = 0x40 + // Bit HOST_SLC0_TOHOST_BIT6_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT6_INT_CLR = 0x40 + // Position of HOST_SLC0_TOHOST_BIT7_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT7_INT_CLR_Pos = 0x7 + // Bit mask of HOST_SLC0_TOHOST_BIT7_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT7_INT_CLR_Msk = 0x80 + // Bit HOST_SLC0_TOHOST_BIT7_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOHOST_BIT7_INT_CLR = 0x80 + // Position of HOST_SLC0_TOKEN0_1TO0_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_1TO0_INT_CLR_Pos = 0x8 + // Bit mask of HOST_SLC0_TOKEN0_1TO0_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_1TO0_INT_CLR_Msk = 0x100 + // Bit HOST_SLC0_TOKEN0_1TO0_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_1TO0_INT_CLR = 0x100 + // Position of HOST_SLC0_TOKEN1_1TO0_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_1TO0_INT_CLR_Pos = 0x9 + // Bit mask of HOST_SLC0_TOKEN1_1TO0_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_1TO0_INT_CLR_Msk = 0x200 + // Bit HOST_SLC0_TOKEN1_1TO0_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_1TO0_INT_CLR = 0x200 + // Position of HOST_SLC0_TOKEN0_0TO1_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_0TO1_INT_CLR_Pos = 0xa + // Bit mask of HOST_SLC0_TOKEN0_0TO1_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_0TO1_INT_CLR_Msk = 0x400 + // Bit HOST_SLC0_TOKEN0_0TO1_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN0_0TO1_INT_CLR = 0x400 + // Position of HOST_SLC0_TOKEN1_0TO1_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_0TO1_INT_CLR_Pos = 0xb + // Bit mask of HOST_SLC0_TOKEN1_0TO1_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_0TO1_INT_CLR_Msk = 0x800 + // Bit HOST_SLC0_TOKEN1_0TO1_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TOKEN1_0TO1_INT_CLR = 0x800 + // Position of HOST_SLC0HOST_RX_SOF_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_SOF_INT_CLR_Pos = 0xc + // Bit mask of HOST_SLC0HOST_RX_SOF_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_SOF_INT_CLR_Msk = 0x1000 + // Bit HOST_SLC0HOST_RX_SOF_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_SOF_INT_CLR = 0x1000 + // Position of HOST_SLC0HOST_RX_EOF_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_EOF_INT_CLR_Pos = 0xd + // Bit mask of HOST_SLC0HOST_RX_EOF_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_EOF_INT_CLR_Msk = 0x2000 + // Bit HOST_SLC0HOST_RX_EOF_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_EOF_INT_CLR = 0x2000 + // Position of HOST_SLC0HOST_RX_START_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_START_INT_CLR_Pos = 0xe + // Bit mask of HOST_SLC0HOST_RX_START_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_START_INT_CLR_Msk = 0x4000 + // Bit HOST_SLC0HOST_RX_START_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_RX_START_INT_CLR = 0x4000 + // Position of HOST_SLC0HOST_TX_START_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_TX_START_INT_CLR_Pos = 0xf + // Bit mask of HOST_SLC0HOST_TX_START_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_TX_START_INT_CLR_Msk = 0x8000 + // Bit HOST_SLC0HOST_TX_START_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0HOST_TX_START_INT_CLR = 0x8000 + // Position of HOST_SLC0_RX_UDF_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_UDF_INT_CLR_Pos = 0x10 + // Bit mask of HOST_SLC0_RX_UDF_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_UDF_INT_CLR_Msk = 0x10000 + // Bit HOST_SLC0_RX_UDF_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_UDF_INT_CLR = 0x10000 + // Position of HOST_SLC0_TX_OVF_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TX_OVF_INT_CLR_Pos = 0x11 + // Bit mask of HOST_SLC0_TX_OVF_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TX_OVF_INT_CLR_Msk = 0x20000 + // Bit HOST_SLC0_TX_OVF_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_TX_OVF_INT_CLR = 0x20000 + // Position of HOST_SLC0_RX_PF_VALID_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_PF_VALID_INT_CLR_Pos = 0x12 + // Bit mask of HOST_SLC0_RX_PF_VALID_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_PF_VALID_INT_CLR_Msk = 0x40000 + // Bit HOST_SLC0_RX_PF_VALID_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_PF_VALID_INT_CLR = 0x40000 + // Position of HOST_SLC0_EXT_BIT0_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT0_INT_CLR_Pos = 0x13 + // Bit mask of HOST_SLC0_EXT_BIT0_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT0_INT_CLR_Msk = 0x80000 + // Bit HOST_SLC0_EXT_BIT0_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT0_INT_CLR = 0x80000 + // Position of HOST_SLC0_EXT_BIT1_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT1_INT_CLR_Pos = 0x14 + // Bit mask of HOST_SLC0_EXT_BIT1_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT1_INT_CLR_Msk = 0x100000 + // Bit HOST_SLC0_EXT_BIT1_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT1_INT_CLR = 0x100000 + // Position of HOST_SLC0_EXT_BIT2_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT2_INT_CLR_Pos = 0x15 + // Bit mask of HOST_SLC0_EXT_BIT2_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT2_INT_CLR_Msk = 0x200000 + // Bit HOST_SLC0_EXT_BIT2_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT2_INT_CLR = 0x200000 + // Position of HOST_SLC0_EXT_BIT3_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT3_INT_CLR_Pos = 0x16 + // Bit mask of HOST_SLC0_EXT_BIT3_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT3_INT_CLR_Msk = 0x400000 + // Bit HOST_SLC0_EXT_BIT3_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_EXT_BIT3_INT_CLR = 0x400000 + // Position of HOST_SLC0_RX_NEW_PACKET_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_NEW_PACKET_INT_CLR_Pos = 0x17 + // Bit mask of HOST_SLC0_RX_NEW_PACKET_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_NEW_PACKET_INT_CLR_Msk = 0x800000 + // Bit HOST_SLC0_RX_NEW_PACKET_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_RX_NEW_PACKET_INT_CLR = 0x800000 + // Position of HOST_SLC0_HOST_RD_RETRY_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_HOST_RD_RETRY_INT_CLR_Pos = 0x18 + // Bit mask of HOST_SLC0_HOST_RD_RETRY_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_HOST_RD_RETRY_INT_CLR_Msk = 0x1000000 + // Bit HOST_SLC0_HOST_RD_RETRY_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_SLC0_HOST_RD_RETRY_INT_CLR = 0x1000000 + // Position of HOST_GPIO_SDIO_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_GPIO_SDIO_INT_CLR_Pos = 0x19 + // Bit mask of HOST_GPIO_SDIO_INT_CLR field. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_GPIO_SDIO_INT_CLR_Msk = 0x2000000 + // Bit HOST_GPIO_SDIO_INT_CLR. + SLCHOST_HOST_SLC0HOST_INT_CLR_HOST_GPIO_SDIO_INT_CLR = 0x2000000 + + // HOST_SLC1HOST_INT_CLR + // Position of HOST_SLC1_TOHOST_BIT0_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT0_INT_CLR_Pos = 0x0 + // Bit mask of HOST_SLC1_TOHOST_BIT0_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT0_INT_CLR_Msk = 0x1 + // Bit HOST_SLC1_TOHOST_BIT0_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT0_INT_CLR = 0x1 + // Position of HOST_SLC1_TOHOST_BIT1_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT1_INT_CLR_Pos = 0x1 + // Bit mask of HOST_SLC1_TOHOST_BIT1_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT1_INT_CLR_Msk = 0x2 + // Bit HOST_SLC1_TOHOST_BIT1_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT1_INT_CLR = 0x2 + // Position of HOST_SLC1_TOHOST_BIT2_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT2_INT_CLR_Pos = 0x2 + // Bit mask of HOST_SLC1_TOHOST_BIT2_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT2_INT_CLR_Msk = 0x4 + // Bit HOST_SLC1_TOHOST_BIT2_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT2_INT_CLR = 0x4 + // Position of HOST_SLC1_TOHOST_BIT3_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT3_INT_CLR_Pos = 0x3 + // Bit mask of HOST_SLC1_TOHOST_BIT3_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT3_INT_CLR_Msk = 0x8 + // Bit HOST_SLC1_TOHOST_BIT3_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT3_INT_CLR = 0x8 + // Position of HOST_SLC1_TOHOST_BIT4_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT4_INT_CLR_Pos = 0x4 + // Bit mask of HOST_SLC1_TOHOST_BIT4_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT4_INT_CLR_Msk = 0x10 + // Bit HOST_SLC1_TOHOST_BIT4_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT4_INT_CLR = 0x10 + // Position of HOST_SLC1_TOHOST_BIT5_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT5_INT_CLR_Pos = 0x5 + // Bit mask of HOST_SLC1_TOHOST_BIT5_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT5_INT_CLR_Msk = 0x20 + // Bit HOST_SLC1_TOHOST_BIT5_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT5_INT_CLR = 0x20 + // Position of HOST_SLC1_TOHOST_BIT6_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT6_INT_CLR_Pos = 0x6 + // Bit mask of HOST_SLC1_TOHOST_BIT6_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT6_INT_CLR_Msk = 0x40 + // Bit HOST_SLC1_TOHOST_BIT6_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT6_INT_CLR = 0x40 + // Position of HOST_SLC1_TOHOST_BIT7_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT7_INT_CLR_Pos = 0x7 + // Bit mask of HOST_SLC1_TOHOST_BIT7_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT7_INT_CLR_Msk = 0x80 + // Bit HOST_SLC1_TOHOST_BIT7_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOHOST_BIT7_INT_CLR = 0x80 + // Position of HOST_SLC1_TOKEN0_1TO0_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_1TO0_INT_CLR_Pos = 0x8 + // Bit mask of HOST_SLC1_TOKEN0_1TO0_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_1TO0_INT_CLR_Msk = 0x100 + // Bit HOST_SLC1_TOKEN0_1TO0_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_1TO0_INT_CLR = 0x100 + // Position of HOST_SLC1_TOKEN1_1TO0_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_1TO0_INT_CLR_Pos = 0x9 + // Bit mask of HOST_SLC1_TOKEN1_1TO0_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_1TO0_INT_CLR_Msk = 0x200 + // Bit HOST_SLC1_TOKEN1_1TO0_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_1TO0_INT_CLR = 0x200 + // Position of HOST_SLC1_TOKEN0_0TO1_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_0TO1_INT_CLR_Pos = 0xa + // Bit mask of HOST_SLC1_TOKEN0_0TO1_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_0TO1_INT_CLR_Msk = 0x400 + // Bit HOST_SLC1_TOKEN0_0TO1_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN0_0TO1_INT_CLR = 0x400 + // Position of HOST_SLC1_TOKEN1_0TO1_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_0TO1_INT_CLR_Pos = 0xb + // Bit mask of HOST_SLC1_TOKEN1_0TO1_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_0TO1_INT_CLR_Msk = 0x800 + // Bit HOST_SLC1_TOKEN1_0TO1_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TOKEN1_0TO1_INT_CLR = 0x800 + // Position of HOST_SLC1HOST_RX_SOF_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_SOF_INT_CLR_Pos = 0xc + // Bit mask of HOST_SLC1HOST_RX_SOF_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_SOF_INT_CLR_Msk = 0x1000 + // Bit HOST_SLC1HOST_RX_SOF_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_SOF_INT_CLR = 0x1000 + // Position of HOST_SLC1HOST_RX_EOF_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_EOF_INT_CLR_Pos = 0xd + // Bit mask of HOST_SLC1HOST_RX_EOF_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_EOF_INT_CLR_Msk = 0x2000 + // Bit HOST_SLC1HOST_RX_EOF_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_EOF_INT_CLR = 0x2000 + // Position of HOST_SLC1HOST_RX_START_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_START_INT_CLR_Pos = 0xe + // Bit mask of HOST_SLC1HOST_RX_START_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_START_INT_CLR_Msk = 0x4000 + // Bit HOST_SLC1HOST_RX_START_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_RX_START_INT_CLR = 0x4000 + // Position of HOST_SLC1HOST_TX_START_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_TX_START_INT_CLR_Pos = 0xf + // Bit mask of HOST_SLC1HOST_TX_START_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_TX_START_INT_CLR_Msk = 0x8000 + // Bit HOST_SLC1HOST_TX_START_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1HOST_TX_START_INT_CLR = 0x8000 + // Position of HOST_SLC1_RX_UDF_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_UDF_INT_CLR_Pos = 0x10 + // Bit mask of HOST_SLC1_RX_UDF_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_UDF_INT_CLR_Msk = 0x10000 + // Bit HOST_SLC1_RX_UDF_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_UDF_INT_CLR = 0x10000 + // Position of HOST_SLC1_TX_OVF_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TX_OVF_INT_CLR_Pos = 0x11 + // Bit mask of HOST_SLC1_TX_OVF_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TX_OVF_INT_CLR_Msk = 0x20000 + // Bit HOST_SLC1_TX_OVF_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_TX_OVF_INT_CLR = 0x20000 + // Position of HOST_SLC1_RX_PF_VALID_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_PF_VALID_INT_CLR_Pos = 0x12 + // Bit mask of HOST_SLC1_RX_PF_VALID_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_PF_VALID_INT_CLR_Msk = 0x40000 + // Bit HOST_SLC1_RX_PF_VALID_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_RX_PF_VALID_INT_CLR = 0x40000 + // Position of HOST_SLC1_EXT_BIT0_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT0_INT_CLR_Pos = 0x13 + // Bit mask of HOST_SLC1_EXT_BIT0_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT0_INT_CLR_Msk = 0x80000 + // Bit HOST_SLC1_EXT_BIT0_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT0_INT_CLR = 0x80000 + // Position of HOST_SLC1_EXT_BIT1_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT1_INT_CLR_Pos = 0x14 + // Bit mask of HOST_SLC1_EXT_BIT1_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT1_INT_CLR_Msk = 0x100000 + // Bit HOST_SLC1_EXT_BIT1_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT1_INT_CLR = 0x100000 + // Position of HOST_SLC1_EXT_BIT2_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT2_INT_CLR_Pos = 0x15 + // Bit mask of HOST_SLC1_EXT_BIT2_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT2_INT_CLR_Msk = 0x200000 + // Bit HOST_SLC1_EXT_BIT2_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT2_INT_CLR = 0x200000 + // Position of HOST_SLC1_EXT_BIT3_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT3_INT_CLR_Pos = 0x16 + // Bit mask of HOST_SLC1_EXT_BIT3_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT3_INT_CLR_Msk = 0x400000 + // Bit HOST_SLC1_EXT_BIT3_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_EXT_BIT3_INT_CLR = 0x400000 + // Position of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_Pos = 0x17 + // Bit mask of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_Msk = 0x800000 + // Bit HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR = 0x800000 + // Position of HOST_SLC1_HOST_RD_RETRY_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_HOST_RD_RETRY_INT_CLR_Pos = 0x18 + // Bit mask of HOST_SLC1_HOST_RD_RETRY_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_HOST_RD_RETRY_INT_CLR_Msk = 0x1000000 + // Bit HOST_SLC1_HOST_RD_RETRY_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_HOST_RD_RETRY_INT_CLR = 0x1000000 + // Position of HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_Pos = 0x19 + // Bit mask of HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR field. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_Msk = 0x2000000 + // Bit HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR. + SLCHOST_HOST_SLC1HOST_INT_CLR_HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR = 0x2000000 + + // HOST_SLC0HOST_FUNC1_INT_ENA + // Position of HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA = 0x1 + // Position of HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA = 0x2 + // Position of HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA = 0x4 + // Position of HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA = 0x8 + // Position of HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA = 0x10 + // Position of HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA = 0x20 + // Position of HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA = 0x40 + // Position of HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA = 0x80 + // Position of HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of HOST_FN1_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of HOST_FN1_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit HOST_FN1_SLC0HOST_RX_SOF_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_SOF_INT_ENA = 0x1000 + // Position of HOST_FN1_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of HOST_FN1_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit HOST_FN1_SLC0HOST_RX_EOF_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_EOF_INT_ENA = 0x2000 + // Position of HOST_FN1_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of HOST_FN1_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit HOST_FN1_SLC0HOST_RX_START_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_RX_START_INT_ENA = 0x4000 + // Position of HOST_FN1_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of HOST_FN1_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit HOST_FN1_SLC0HOST_TX_START_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0HOST_TX_START_INT_ENA = 0x8000 + // Position of HOST_FN1_SLC0_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of HOST_FN1_SLC0_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit HOST_FN1_SLC0_RX_UDF_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_UDF_INT_ENA = 0x10000 + // Position of HOST_FN1_SLC0_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of HOST_FN1_SLC0_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit HOST_FN1_SLC0_TX_OVF_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_TX_OVF_INT_ENA = 0x20000 + // Position of HOST_FN1_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of HOST_FN1_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit HOST_FN1_SLC0_RX_PF_VALID_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_PF_VALID_INT_ENA = 0x40000 + // Position of HOST_FN1_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of HOST_FN1_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit HOST_FN1_SLC0_EXT_BIT0_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT0_INT_ENA = 0x80000 + // Position of HOST_FN1_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of HOST_FN1_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit HOST_FN1_SLC0_EXT_BIT1_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT1_INT_ENA = 0x100000 + // Position of HOST_FN1_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of HOST_FN1_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit HOST_FN1_SLC0_EXT_BIT2_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT2_INT_ENA = 0x200000 + // Position of HOST_FN1_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of HOST_FN1_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit HOST_FN1_SLC0_EXT_BIT3_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_EXT_BIT3_INT_ENA = 0x400000 + // Position of HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of HOST_FN1_GPIO_SDIO_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_GPIO_SDIO_INT_ENA_Pos = 0x19 + // Bit mask of HOST_FN1_GPIO_SDIO_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_GPIO_SDIO_INT_ENA_Msk = 0x2000000 + // Bit HOST_FN1_GPIO_SDIO_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC1_INT_ENA_HOST_FN1_GPIO_SDIO_INT_ENA = 0x2000000 + + // HOST_SLC1HOST_FUNC1_INT_ENA + // Position of HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA = 0x1 + // Position of HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA = 0x2 + // Position of HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA = 0x4 + // Position of HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA = 0x8 + // Position of HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA = 0x10 + // Position of HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA = 0x20 + // Position of HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA = 0x40 + // Position of HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA = 0x80 + // Position of HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of HOST_FN1_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of HOST_FN1_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit HOST_FN1_SLC1HOST_RX_SOF_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_SOF_INT_ENA = 0x1000 + // Position of HOST_FN1_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of HOST_FN1_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit HOST_FN1_SLC1HOST_RX_EOF_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_EOF_INT_ENA = 0x2000 + // Position of HOST_FN1_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of HOST_FN1_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit HOST_FN1_SLC1HOST_RX_START_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_RX_START_INT_ENA = 0x4000 + // Position of HOST_FN1_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of HOST_FN1_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit HOST_FN1_SLC1HOST_TX_START_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1HOST_TX_START_INT_ENA = 0x8000 + // Position of HOST_FN1_SLC1_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of HOST_FN1_SLC1_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit HOST_FN1_SLC1_RX_UDF_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_UDF_INT_ENA = 0x10000 + // Position of HOST_FN1_SLC1_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of HOST_FN1_SLC1_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit HOST_FN1_SLC1_TX_OVF_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_TX_OVF_INT_ENA = 0x20000 + // Position of HOST_FN1_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of HOST_FN1_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit HOST_FN1_SLC1_RX_PF_VALID_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_RX_PF_VALID_INT_ENA = 0x40000 + // Position of HOST_FN1_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of HOST_FN1_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit HOST_FN1_SLC1_EXT_BIT0_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT0_INT_ENA = 0x80000 + // Position of HOST_FN1_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of HOST_FN1_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit HOST_FN1_SLC1_EXT_BIT1_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT1_INT_ENA = 0x100000 + // Position of HOST_FN1_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of HOST_FN1_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit HOST_FN1_SLC1_EXT_BIT2_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT2_INT_ENA = 0x200000 + // Position of HOST_FN1_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of HOST_FN1_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit HOST_FN1_SLC1_EXT_BIT3_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_EXT_BIT3_INT_ENA = 0x400000 + // Position of HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_Pos = 0x19 + // Bit mask of HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_Msk = 0x2000000 + // Bit HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC1_INT_ENA_HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA = 0x2000000 + + // HOST_SLC0HOST_FUNC2_INT_ENA + // Position of HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA = 0x1 + // Position of HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA = 0x2 + // Position of HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA = 0x4 + // Position of HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA = 0x8 + // Position of HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA = 0x10 + // Position of HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA = 0x20 + // Position of HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA = 0x40 + // Position of HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA = 0x80 + // Position of HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of HOST_FN2_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of HOST_FN2_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit HOST_FN2_SLC0HOST_RX_SOF_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_SOF_INT_ENA = 0x1000 + // Position of HOST_FN2_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of HOST_FN2_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit HOST_FN2_SLC0HOST_RX_EOF_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_EOF_INT_ENA = 0x2000 + // Position of HOST_FN2_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of HOST_FN2_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit HOST_FN2_SLC0HOST_RX_START_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_RX_START_INT_ENA = 0x4000 + // Position of HOST_FN2_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of HOST_FN2_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit HOST_FN2_SLC0HOST_TX_START_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0HOST_TX_START_INT_ENA = 0x8000 + // Position of HOST_FN2_SLC0_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of HOST_FN2_SLC0_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit HOST_FN2_SLC0_RX_UDF_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_UDF_INT_ENA = 0x10000 + // Position of HOST_FN2_SLC0_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of HOST_FN2_SLC0_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit HOST_FN2_SLC0_TX_OVF_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_TX_OVF_INT_ENA = 0x20000 + // Position of HOST_FN2_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of HOST_FN2_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit HOST_FN2_SLC0_RX_PF_VALID_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_PF_VALID_INT_ENA = 0x40000 + // Position of HOST_FN2_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of HOST_FN2_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit HOST_FN2_SLC0_EXT_BIT0_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT0_INT_ENA = 0x80000 + // Position of HOST_FN2_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of HOST_FN2_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit HOST_FN2_SLC0_EXT_BIT1_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT1_INT_ENA = 0x100000 + // Position of HOST_FN2_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of HOST_FN2_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit HOST_FN2_SLC0_EXT_BIT2_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT2_INT_ENA = 0x200000 + // Position of HOST_FN2_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of HOST_FN2_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit HOST_FN2_SLC0_EXT_BIT3_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_EXT_BIT3_INT_ENA = 0x400000 + // Position of HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of HOST_FN2_GPIO_SDIO_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_GPIO_SDIO_INT_ENA_Pos = 0x19 + // Bit mask of HOST_FN2_GPIO_SDIO_INT_ENA field. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_GPIO_SDIO_INT_ENA_Msk = 0x2000000 + // Bit HOST_FN2_GPIO_SDIO_INT_ENA. + SLCHOST_HOST_SLC0HOST_FUNC2_INT_ENA_HOST_FN2_GPIO_SDIO_INT_ENA = 0x2000000 + + // HOST_SLC1HOST_FUNC2_INT_ENA + // Position of HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA = 0x1 + // Position of HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA = 0x2 + // Position of HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA = 0x4 + // Position of HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA = 0x8 + // Position of HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA = 0x10 + // Position of HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA = 0x20 + // Position of HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA = 0x40 + // Position of HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA = 0x80 + // Position of HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of HOST_FN2_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of HOST_FN2_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit HOST_FN2_SLC1HOST_RX_SOF_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_SOF_INT_ENA = 0x1000 + // Position of HOST_FN2_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of HOST_FN2_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit HOST_FN2_SLC1HOST_RX_EOF_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_EOF_INT_ENA = 0x2000 + // Position of HOST_FN2_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of HOST_FN2_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit HOST_FN2_SLC1HOST_RX_START_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_RX_START_INT_ENA = 0x4000 + // Position of HOST_FN2_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of HOST_FN2_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit HOST_FN2_SLC1HOST_TX_START_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1HOST_TX_START_INT_ENA = 0x8000 + // Position of HOST_FN2_SLC1_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of HOST_FN2_SLC1_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit HOST_FN2_SLC1_RX_UDF_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_UDF_INT_ENA = 0x10000 + // Position of HOST_FN2_SLC1_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of HOST_FN2_SLC1_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit HOST_FN2_SLC1_TX_OVF_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_TX_OVF_INT_ENA = 0x20000 + // Position of HOST_FN2_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of HOST_FN2_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit HOST_FN2_SLC1_RX_PF_VALID_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_RX_PF_VALID_INT_ENA = 0x40000 + // Position of HOST_FN2_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of HOST_FN2_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit HOST_FN2_SLC1_EXT_BIT0_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT0_INT_ENA = 0x80000 + // Position of HOST_FN2_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of HOST_FN2_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit HOST_FN2_SLC1_EXT_BIT1_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT1_INT_ENA = 0x100000 + // Position of HOST_FN2_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of HOST_FN2_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit HOST_FN2_SLC1_EXT_BIT2_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT2_INT_ENA = 0x200000 + // Position of HOST_FN2_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of HOST_FN2_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit HOST_FN2_SLC1_EXT_BIT3_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_EXT_BIT3_INT_ENA = 0x400000 + // Position of HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_Pos = 0x19 + // Bit mask of HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_Msk = 0x2000000 + // Bit HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA. + SLCHOST_HOST_SLC1HOST_FUNC2_INT_ENA_HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA = 0x2000000 + + // HOST_SLC0HOST_INT_ENA + // Position of HOST_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of HOST_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit HOST_SLC0_TOHOST_BIT0_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT0_INT_ENA = 0x1 + // Position of HOST_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of HOST_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit HOST_SLC0_TOHOST_BIT1_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT1_INT_ENA = 0x2 + // Position of HOST_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of HOST_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit HOST_SLC0_TOHOST_BIT2_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT2_INT_ENA = 0x4 + // Position of HOST_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of HOST_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit HOST_SLC0_TOHOST_BIT3_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT3_INT_ENA = 0x8 + // Position of HOST_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of HOST_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit HOST_SLC0_TOHOST_BIT4_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT4_INT_ENA = 0x10 + // Position of HOST_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of HOST_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit HOST_SLC0_TOHOST_BIT5_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT5_INT_ENA = 0x20 + // Position of HOST_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of HOST_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit HOST_SLC0_TOHOST_BIT6_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT6_INT_ENA = 0x40 + // Position of HOST_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of HOST_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit HOST_SLC0_TOHOST_BIT7_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOHOST_BIT7_INT_ENA = 0x80 + // Position of HOST_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of HOST_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit HOST_SLC0_TOKEN0_1TO0_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of HOST_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of HOST_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit HOST_SLC0_TOKEN1_1TO0_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of HOST_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of HOST_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit HOST_SLC0_TOKEN0_0TO1_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of HOST_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of HOST_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit HOST_SLC0_TOKEN1_0TO1_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of HOST_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of HOST_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit HOST_SLC0HOST_RX_SOF_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_SOF_INT_ENA = 0x1000 + // Position of HOST_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of HOST_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit HOST_SLC0HOST_RX_EOF_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_EOF_INT_ENA = 0x2000 + // Position of HOST_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of HOST_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit HOST_SLC0HOST_RX_START_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_RX_START_INT_ENA = 0x4000 + // Position of HOST_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of HOST_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit HOST_SLC0HOST_TX_START_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0HOST_TX_START_INT_ENA = 0x8000 + // Position of HOST_SLC0_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of HOST_SLC0_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit HOST_SLC0_RX_UDF_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_UDF_INT_ENA = 0x10000 + // Position of HOST_SLC0_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of HOST_SLC0_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit HOST_SLC0_TX_OVF_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_TX_OVF_INT_ENA = 0x20000 + // Position of HOST_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of HOST_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit HOST_SLC0_RX_PF_VALID_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_PF_VALID_INT_ENA = 0x40000 + // Position of HOST_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of HOST_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit HOST_SLC0_EXT_BIT0_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT0_INT_ENA = 0x80000 + // Position of HOST_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of HOST_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit HOST_SLC0_EXT_BIT1_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT1_INT_ENA = 0x100000 + // Position of HOST_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of HOST_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit HOST_SLC0_EXT_BIT2_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT2_INT_ENA = 0x200000 + // Position of HOST_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of HOST_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit HOST_SLC0_EXT_BIT3_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_EXT_BIT3_INT_ENA = 0x400000 + // Position of HOST_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of HOST_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit HOST_SLC0_RX_NEW_PACKET_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of HOST_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of HOST_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit HOST_SLC0_HOST_RD_RETRY_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_SLC0_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of HOST_GPIO_SDIO_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_GPIO_SDIO_INT_ENA_Pos = 0x19 + // Bit mask of HOST_GPIO_SDIO_INT_ENA field. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_GPIO_SDIO_INT_ENA_Msk = 0x2000000 + // Bit HOST_GPIO_SDIO_INT_ENA. + SLCHOST_HOST_SLC0HOST_INT_ENA_HOST_GPIO_SDIO_INT_ENA = 0x2000000 + + // HOST_SLC1HOST_INT_ENA + // Position of HOST_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of HOST_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit HOST_SLC1_TOHOST_BIT0_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT0_INT_ENA = 0x1 + // Position of HOST_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of HOST_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit HOST_SLC1_TOHOST_BIT1_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT1_INT_ENA = 0x2 + // Position of HOST_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of HOST_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit HOST_SLC1_TOHOST_BIT2_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT2_INT_ENA = 0x4 + // Position of HOST_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of HOST_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit HOST_SLC1_TOHOST_BIT3_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT3_INT_ENA = 0x8 + // Position of HOST_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of HOST_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit HOST_SLC1_TOHOST_BIT4_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT4_INT_ENA = 0x10 + // Position of HOST_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of HOST_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit HOST_SLC1_TOHOST_BIT5_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT5_INT_ENA = 0x20 + // Position of HOST_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of HOST_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit HOST_SLC1_TOHOST_BIT6_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT6_INT_ENA = 0x40 + // Position of HOST_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of HOST_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit HOST_SLC1_TOHOST_BIT7_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOHOST_BIT7_INT_ENA = 0x80 + // Position of HOST_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of HOST_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit HOST_SLC1_TOKEN0_1TO0_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of HOST_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of HOST_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit HOST_SLC1_TOKEN1_1TO0_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of HOST_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of HOST_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit HOST_SLC1_TOKEN0_0TO1_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of HOST_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of HOST_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit HOST_SLC1_TOKEN1_0TO1_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of HOST_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of HOST_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit HOST_SLC1HOST_RX_SOF_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_SOF_INT_ENA = 0x1000 + // Position of HOST_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of HOST_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit HOST_SLC1HOST_RX_EOF_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_EOF_INT_ENA = 0x2000 + // Position of HOST_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of HOST_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit HOST_SLC1HOST_RX_START_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_RX_START_INT_ENA = 0x4000 + // Position of HOST_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of HOST_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit HOST_SLC1HOST_TX_START_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1HOST_TX_START_INT_ENA = 0x8000 + // Position of HOST_SLC1_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of HOST_SLC1_RX_UDF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit HOST_SLC1_RX_UDF_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_UDF_INT_ENA = 0x10000 + // Position of HOST_SLC1_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of HOST_SLC1_TX_OVF_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit HOST_SLC1_TX_OVF_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_TX_OVF_INT_ENA = 0x20000 + // Position of HOST_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of HOST_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit HOST_SLC1_RX_PF_VALID_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_RX_PF_VALID_INT_ENA = 0x40000 + // Position of HOST_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of HOST_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit HOST_SLC1_EXT_BIT0_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT0_INT_ENA = 0x80000 + // Position of HOST_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of HOST_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit HOST_SLC1_EXT_BIT1_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT1_INT_ENA = 0x100000 + // Position of HOST_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of HOST_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit HOST_SLC1_EXT_BIT2_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT2_INT_ENA = 0x200000 + // Position of HOST_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of HOST_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit HOST_SLC1_EXT_BIT3_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_EXT_BIT3_INT_ENA = 0x400000 + // Position of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of HOST_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of HOST_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit HOST_SLC1_HOST_RD_RETRY_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_Pos = 0x19 + // Bit mask of HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_Msk = 0x2000000 + // Bit HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA. + SLCHOST_HOST_SLC1HOST_INT_ENA_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA = 0x2000000 + + // HOST_SLC0HOST_RX_INFOR + // Position of HOST_SLC0HOST_RX_INFOR field. + SLCHOST_HOST_SLC0HOST_RX_INFOR_HOST_SLC0HOST_RX_INFOR_Pos = 0x0 + // Bit mask of HOST_SLC0HOST_RX_INFOR field. + SLCHOST_HOST_SLC0HOST_RX_INFOR_HOST_SLC0HOST_RX_INFOR_Msk = 0xfffff + + // HOST_SLC1HOST_RX_INFOR + // Position of HOST_SLC1HOST_RX_INFOR field. + SLCHOST_HOST_SLC1HOST_RX_INFOR_HOST_SLC1HOST_RX_INFOR_Pos = 0x0 + // Bit mask of HOST_SLC1HOST_RX_INFOR field. + SLCHOST_HOST_SLC1HOST_RX_INFOR_HOST_SLC1HOST_RX_INFOR_Msk = 0xfffff + + // HOST_SLC0HOST_LEN_WD + // Position of HOST_SLC0HOST_LEN_WD field. + SLCHOST_HOST_SLC0HOST_LEN_WD_HOST_SLC0HOST_LEN_WD_Pos = 0x0 + // Bit mask of HOST_SLC0HOST_LEN_WD field. + SLCHOST_HOST_SLC0HOST_LEN_WD_HOST_SLC0HOST_LEN_WD_Msk = 0xffffffff + + // HOST_SLC_APBWIN_WDATA + // Position of HOST_SLC_APBWIN_WDATA field. + SLCHOST_HOST_SLC_APBWIN_WDATA_HOST_SLC_APBWIN_WDATA_Pos = 0x0 + // Bit mask of HOST_SLC_APBWIN_WDATA field. + SLCHOST_HOST_SLC_APBWIN_WDATA_HOST_SLC_APBWIN_WDATA_Msk = 0xffffffff + + // HOST_SLC_APBWIN_CONF + // Position of HOST_SLC_APBWIN_ADDR field. + SLCHOST_HOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_ADDR_Pos = 0x0 + // Bit mask of HOST_SLC_APBWIN_ADDR field. + SLCHOST_HOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_ADDR_Msk = 0xfffffff + // Position of HOST_SLC_APBWIN_WR field. + SLCHOST_HOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_WR_Pos = 0x1c + // Bit mask of HOST_SLC_APBWIN_WR field. + SLCHOST_HOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_WR_Msk = 0x10000000 + // Bit HOST_SLC_APBWIN_WR. + SLCHOST_HOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_WR = 0x10000000 + // Position of HOST_SLC_APBWIN_START field. + SLCHOST_HOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_START_Pos = 0x1d + // Bit mask of HOST_SLC_APBWIN_START field. + SLCHOST_HOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_START_Msk = 0x20000000 + // Bit HOST_SLC_APBWIN_START. + SLCHOST_HOST_SLC_APBWIN_CONF_HOST_SLC_APBWIN_START = 0x20000000 + + // HOST_SLC_APBWIN_RDATA + // Position of HOST_SLC_APBWIN_RDATA field. + SLCHOST_HOST_SLC_APBWIN_RDATA_HOST_SLC_APBWIN_RDATA_Pos = 0x0 + // Bit mask of HOST_SLC_APBWIN_RDATA field. + SLCHOST_HOST_SLC_APBWIN_RDATA_HOST_SLC_APBWIN_RDATA_Msk = 0xffffffff + + // HOST_SLCHOST_RDCLR0 + // Position of HOST_SLCHOST_SLC0_BIT7_CLRADDR field. + SLCHOST_HOST_SLCHOST_RDCLR0_HOST_SLCHOST_SLC0_BIT7_CLRADDR_Pos = 0x0 + // Bit mask of HOST_SLCHOST_SLC0_BIT7_CLRADDR field. + SLCHOST_HOST_SLCHOST_RDCLR0_HOST_SLCHOST_SLC0_BIT7_CLRADDR_Msk = 0x1ff + // Position of HOST_SLCHOST_SLC0_BIT6_CLRADDR field. + SLCHOST_HOST_SLCHOST_RDCLR0_HOST_SLCHOST_SLC0_BIT6_CLRADDR_Pos = 0x9 + // Bit mask of HOST_SLCHOST_SLC0_BIT6_CLRADDR field. + SLCHOST_HOST_SLCHOST_RDCLR0_HOST_SLCHOST_SLC0_BIT6_CLRADDR_Msk = 0x3fe00 + + // HOST_SLCHOST_RDCLR1 + // Position of HOST_SLCHOST_SLC1_BIT7_CLRADDR field. + SLCHOST_HOST_SLCHOST_RDCLR1_HOST_SLCHOST_SLC1_BIT7_CLRADDR_Pos = 0x0 + // Bit mask of HOST_SLCHOST_SLC1_BIT7_CLRADDR field. + SLCHOST_HOST_SLCHOST_RDCLR1_HOST_SLCHOST_SLC1_BIT7_CLRADDR_Msk = 0x1ff + // Position of HOST_SLCHOST_SLC1_BIT6_CLRADDR field. + SLCHOST_HOST_SLCHOST_RDCLR1_HOST_SLCHOST_SLC1_BIT6_CLRADDR_Pos = 0x9 + // Bit mask of HOST_SLCHOST_SLC1_BIT6_CLRADDR field. + SLCHOST_HOST_SLCHOST_RDCLR1_HOST_SLCHOST_SLC1_BIT6_CLRADDR_Msk = 0x3fe00 + + // HOST_SLC0HOST_INT_ENA1 + // Position of HOST_SLC0_TOHOST_BIT0_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT0_INT_ENA1_Pos = 0x0 + // Bit mask of HOST_SLC0_TOHOST_BIT0_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT0_INT_ENA1_Msk = 0x1 + // Bit HOST_SLC0_TOHOST_BIT0_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT0_INT_ENA1 = 0x1 + // Position of HOST_SLC0_TOHOST_BIT1_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT1_INT_ENA1_Pos = 0x1 + // Bit mask of HOST_SLC0_TOHOST_BIT1_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT1_INT_ENA1_Msk = 0x2 + // Bit HOST_SLC0_TOHOST_BIT1_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT1_INT_ENA1 = 0x2 + // Position of HOST_SLC0_TOHOST_BIT2_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT2_INT_ENA1_Pos = 0x2 + // Bit mask of HOST_SLC0_TOHOST_BIT2_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT2_INT_ENA1_Msk = 0x4 + // Bit HOST_SLC0_TOHOST_BIT2_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT2_INT_ENA1 = 0x4 + // Position of HOST_SLC0_TOHOST_BIT3_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT3_INT_ENA1_Pos = 0x3 + // Bit mask of HOST_SLC0_TOHOST_BIT3_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT3_INT_ENA1_Msk = 0x8 + // Bit HOST_SLC0_TOHOST_BIT3_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT3_INT_ENA1 = 0x8 + // Position of HOST_SLC0_TOHOST_BIT4_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT4_INT_ENA1_Pos = 0x4 + // Bit mask of HOST_SLC0_TOHOST_BIT4_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT4_INT_ENA1_Msk = 0x10 + // Bit HOST_SLC0_TOHOST_BIT4_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT4_INT_ENA1 = 0x10 + // Position of HOST_SLC0_TOHOST_BIT5_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT5_INT_ENA1_Pos = 0x5 + // Bit mask of HOST_SLC0_TOHOST_BIT5_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT5_INT_ENA1_Msk = 0x20 + // Bit HOST_SLC0_TOHOST_BIT5_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT5_INT_ENA1 = 0x20 + // Position of HOST_SLC0_TOHOST_BIT6_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT6_INT_ENA1_Pos = 0x6 + // Bit mask of HOST_SLC0_TOHOST_BIT6_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT6_INT_ENA1_Msk = 0x40 + // Bit HOST_SLC0_TOHOST_BIT6_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT6_INT_ENA1 = 0x40 + // Position of HOST_SLC0_TOHOST_BIT7_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT7_INT_ENA1_Pos = 0x7 + // Bit mask of HOST_SLC0_TOHOST_BIT7_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT7_INT_ENA1_Msk = 0x80 + // Bit HOST_SLC0_TOHOST_BIT7_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOHOST_BIT7_INT_ENA1 = 0x80 + // Position of HOST_SLC0_TOKEN0_1TO0_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_1TO0_INT_ENA1_Pos = 0x8 + // Bit mask of HOST_SLC0_TOKEN0_1TO0_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_1TO0_INT_ENA1_Msk = 0x100 + // Bit HOST_SLC0_TOKEN0_1TO0_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_1TO0_INT_ENA1 = 0x100 + // Position of HOST_SLC0_TOKEN1_1TO0_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_1TO0_INT_ENA1_Pos = 0x9 + // Bit mask of HOST_SLC0_TOKEN1_1TO0_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_1TO0_INT_ENA1_Msk = 0x200 + // Bit HOST_SLC0_TOKEN1_1TO0_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_1TO0_INT_ENA1 = 0x200 + // Position of HOST_SLC0_TOKEN0_0TO1_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_0TO1_INT_ENA1_Pos = 0xa + // Bit mask of HOST_SLC0_TOKEN0_0TO1_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_0TO1_INT_ENA1_Msk = 0x400 + // Bit HOST_SLC0_TOKEN0_0TO1_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN0_0TO1_INT_ENA1 = 0x400 + // Position of HOST_SLC0_TOKEN1_0TO1_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_0TO1_INT_ENA1_Pos = 0xb + // Bit mask of HOST_SLC0_TOKEN1_0TO1_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_0TO1_INT_ENA1_Msk = 0x800 + // Bit HOST_SLC0_TOKEN1_0TO1_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TOKEN1_0TO1_INT_ENA1 = 0x800 + // Position of HOST_SLC0HOST_RX_SOF_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_SOF_INT_ENA1_Pos = 0xc + // Bit mask of HOST_SLC0HOST_RX_SOF_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_SOF_INT_ENA1_Msk = 0x1000 + // Bit HOST_SLC0HOST_RX_SOF_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_SOF_INT_ENA1 = 0x1000 + // Position of HOST_SLC0HOST_RX_EOF_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_EOF_INT_ENA1_Pos = 0xd + // Bit mask of HOST_SLC0HOST_RX_EOF_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_EOF_INT_ENA1_Msk = 0x2000 + // Bit HOST_SLC0HOST_RX_EOF_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_EOF_INT_ENA1 = 0x2000 + // Position of HOST_SLC0HOST_RX_START_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_START_INT_ENA1_Pos = 0xe + // Bit mask of HOST_SLC0HOST_RX_START_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_START_INT_ENA1_Msk = 0x4000 + // Bit HOST_SLC0HOST_RX_START_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_RX_START_INT_ENA1 = 0x4000 + // Position of HOST_SLC0HOST_TX_START_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_TX_START_INT_ENA1_Pos = 0xf + // Bit mask of HOST_SLC0HOST_TX_START_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_TX_START_INT_ENA1_Msk = 0x8000 + // Bit HOST_SLC0HOST_TX_START_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0HOST_TX_START_INT_ENA1 = 0x8000 + // Position of HOST_SLC0_RX_UDF_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_UDF_INT_ENA1_Pos = 0x10 + // Bit mask of HOST_SLC0_RX_UDF_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_UDF_INT_ENA1_Msk = 0x10000 + // Bit HOST_SLC0_RX_UDF_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_UDF_INT_ENA1 = 0x10000 + // Position of HOST_SLC0_TX_OVF_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TX_OVF_INT_ENA1_Pos = 0x11 + // Bit mask of HOST_SLC0_TX_OVF_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TX_OVF_INT_ENA1_Msk = 0x20000 + // Bit HOST_SLC0_TX_OVF_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_TX_OVF_INT_ENA1 = 0x20000 + // Position of HOST_SLC0_RX_PF_VALID_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_PF_VALID_INT_ENA1_Pos = 0x12 + // Bit mask of HOST_SLC0_RX_PF_VALID_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_PF_VALID_INT_ENA1_Msk = 0x40000 + // Bit HOST_SLC0_RX_PF_VALID_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_PF_VALID_INT_ENA1 = 0x40000 + // Position of HOST_SLC0_EXT_BIT0_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT0_INT_ENA1_Pos = 0x13 + // Bit mask of HOST_SLC0_EXT_BIT0_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT0_INT_ENA1_Msk = 0x80000 + // Bit HOST_SLC0_EXT_BIT0_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT0_INT_ENA1 = 0x80000 + // Position of HOST_SLC0_EXT_BIT1_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT1_INT_ENA1_Pos = 0x14 + // Bit mask of HOST_SLC0_EXT_BIT1_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT1_INT_ENA1_Msk = 0x100000 + // Bit HOST_SLC0_EXT_BIT1_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT1_INT_ENA1 = 0x100000 + // Position of HOST_SLC0_EXT_BIT2_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT2_INT_ENA1_Pos = 0x15 + // Bit mask of HOST_SLC0_EXT_BIT2_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT2_INT_ENA1_Msk = 0x200000 + // Bit HOST_SLC0_EXT_BIT2_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT2_INT_ENA1 = 0x200000 + // Position of HOST_SLC0_EXT_BIT3_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT3_INT_ENA1_Pos = 0x16 + // Bit mask of HOST_SLC0_EXT_BIT3_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT3_INT_ENA1_Msk = 0x400000 + // Bit HOST_SLC0_EXT_BIT3_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_EXT_BIT3_INT_ENA1 = 0x400000 + // Position of HOST_SLC0_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_NEW_PACKET_INT_ENA1_Pos = 0x17 + // Bit mask of HOST_SLC0_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_NEW_PACKET_INT_ENA1_Msk = 0x800000 + // Bit HOST_SLC0_RX_NEW_PACKET_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_RX_NEW_PACKET_INT_ENA1 = 0x800000 + // Position of HOST_SLC0_HOST_RD_RETRY_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_HOST_RD_RETRY_INT_ENA1_Pos = 0x18 + // Bit mask of HOST_SLC0_HOST_RD_RETRY_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_HOST_RD_RETRY_INT_ENA1_Msk = 0x1000000 + // Bit HOST_SLC0_HOST_RD_RETRY_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_SLC0_HOST_RD_RETRY_INT_ENA1 = 0x1000000 + // Position of HOST_GPIO_SDIO_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_GPIO_SDIO_INT_ENA1_Pos = 0x19 + // Bit mask of HOST_GPIO_SDIO_INT_ENA1 field. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_GPIO_SDIO_INT_ENA1_Msk = 0x2000000 + // Bit HOST_GPIO_SDIO_INT_ENA1. + SLCHOST_HOST_SLC0HOST_INT_ENA1_HOST_GPIO_SDIO_INT_ENA1 = 0x2000000 + + // HOST_SLC1HOST_INT_ENA1 + // Position of HOST_SLC1_TOHOST_BIT0_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT0_INT_ENA1_Pos = 0x0 + // Bit mask of HOST_SLC1_TOHOST_BIT0_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT0_INT_ENA1_Msk = 0x1 + // Bit HOST_SLC1_TOHOST_BIT0_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT0_INT_ENA1 = 0x1 + // Position of HOST_SLC1_TOHOST_BIT1_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT1_INT_ENA1_Pos = 0x1 + // Bit mask of HOST_SLC1_TOHOST_BIT1_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT1_INT_ENA1_Msk = 0x2 + // Bit HOST_SLC1_TOHOST_BIT1_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT1_INT_ENA1 = 0x2 + // Position of HOST_SLC1_TOHOST_BIT2_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT2_INT_ENA1_Pos = 0x2 + // Bit mask of HOST_SLC1_TOHOST_BIT2_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT2_INT_ENA1_Msk = 0x4 + // Bit HOST_SLC1_TOHOST_BIT2_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT2_INT_ENA1 = 0x4 + // Position of HOST_SLC1_TOHOST_BIT3_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT3_INT_ENA1_Pos = 0x3 + // Bit mask of HOST_SLC1_TOHOST_BIT3_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT3_INT_ENA1_Msk = 0x8 + // Bit HOST_SLC1_TOHOST_BIT3_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT3_INT_ENA1 = 0x8 + // Position of HOST_SLC1_TOHOST_BIT4_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT4_INT_ENA1_Pos = 0x4 + // Bit mask of HOST_SLC1_TOHOST_BIT4_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT4_INT_ENA1_Msk = 0x10 + // Bit HOST_SLC1_TOHOST_BIT4_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT4_INT_ENA1 = 0x10 + // Position of HOST_SLC1_TOHOST_BIT5_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT5_INT_ENA1_Pos = 0x5 + // Bit mask of HOST_SLC1_TOHOST_BIT5_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT5_INT_ENA1_Msk = 0x20 + // Bit HOST_SLC1_TOHOST_BIT5_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT5_INT_ENA1 = 0x20 + // Position of HOST_SLC1_TOHOST_BIT6_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT6_INT_ENA1_Pos = 0x6 + // Bit mask of HOST_SLC1_TOHOST_BIT6_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT6_INT_ENA1_Msk = 0x40 + // Bit HOST_SLC1_TOHOST_BIT6_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT6_INT_ENA1 = 0x40 + // Position of HOST_SLC1_TOHOST_BIT7_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT7_INT_ENA1_Pos = 0x7 + // Bit mask of HOST_SLC1_TOHOST_BIT7_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT7_INT_ENA1_Msk = 0x80 + // Bit HOST_SLC1_TOHOST_BIT7_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOHOST_BIT7_INT_ENA1 = 0x80 + // Position of HOST_SLC1_TOKEN0_1TO0_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_1TO0_INT_ENA1_Pos = 0x8 + // Bit mask of HOST_SLC1_TOKEN0_1TO0_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_1TO0_INT_ENA1_Msk = 0x100 + // Bit HOST_SLC1_TOKEN0_1TO0_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_1TO0_INT_ENA1 = 0x100 + // Position of HOST_SLC1_TOKEN1_1TO0_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_1TO0_INT_ENA1_Pos = 0x9 + // Bit mask of HOST_SLC1_TOKEN1_1TO0_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_1TO0_INT_ENA1_Msk = 0x200 + // Bit HOST_SLC1_TOKEN1_1TO0_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_1TO0_INT_ENA1 = 0x200 + // Position of HOST_SLC1_TOKEN0_0TO1_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_0TO1_INT_ENA1_Pos = 0xa + // Bit mask of HOST_SLC1_TOKEN0_0TO1_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_0TO1_INT_ENA1_Msk = 0x400 + // Bit HOST_SLC1_TOKEN0_0TO1_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN0_0TO1_INT_ENA1 = 0x400 + // Position of HOST_SLC1_TOKEN1_0TO1_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_0TO1_INT_ENA1_Pos = 0xb + // Bit mask of HOST_SLC1_TOKEN1_0TO1_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_0TO1_INT_ENA1_Msk = 0x800 + // Bit HOST_SLC1_TOKEN1_0TO1_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TOKEN1_0TO1_INT_ENA1 = 0x800 + // Position of HOST_SLC1HOST_RX_SOF_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_SOF_INT_ENA1_Pos = 0xc + // Bit mask of HOST_SLC1HOST_RX_SOF_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_SOF_INT_ENA1_Msk = 0x1000 + // Bit HOST_SLC1HOST_RX_SOF_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_SOF_INT_ENA1 = 0x1000 + // Position of HOST_SLC1HOST_RX_EOF_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_EOF_INT_ENA1_Pos = 0xd + // Bit mask of HOST_SLC1HOST_RX_EOF_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_EOF_INT_ENA1_Msk = 0x2000 + // Bit HOST_SLC1HOST_RX_EOF_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_EOF_INT_ENA1 = 0x2000 + // Position of HOST_SLC1HOST_RX_START_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_START_INT_ENA1_Pos = 0xe + // Bit mask of HOST_SLC1HOST_RX_START_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_START_INT_ENA1_Msk = 0x4000 + // Bit HOST_SLC1HOST_RX_START_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_RX_START_INT_ENA1 = 0x4000 + // Position of HOST_SLC1HOST_TX_START_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_TX_START_INT_ENA1_Pos = 0xf + // Bit mask of HOST_SLC1HOST_TX_START_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_TX_START_INT_ENA1_Msk = 0x8000 + // Bit HOST_SLC1HOST_TX_START_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1HOST_TX_START_INT_ENA1 = 0x8000 + // Position of HOST_SLC1_RX_UDF_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_UDF_INT_ENA1_Pos = 0x10 + // Bit mask of HOST_SLC1_RX_UDF_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_UDF_INT_ENA1_Msk = 0x10000 + // Bit HOST_SLC1_RX_UDF_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_UDF_INT_ENA1 = 0x10000 + // Position of HOST_SLC1_TX_OVF_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TX_OVF_INT_ENA1_Pos = 0x11 + // Bit mask of HOST_SLC1_TX_OVF_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TX_OVF_INT_ENA1_Msk = 0x20000 + // Bit HOST_SLC1_TX_OVF_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_TX_OVF_INT_ENA1 = 0x20000 + // Position of HOST_SLC1_RX_PF_VALID_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_PF_VALID_INT_ENA1_Pos = 0x12 + // Bit mask of HOST_SLC1_RX_PF_VALID_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_PF_VALID_INT_ENA1_Msk = 0x40000 + // Bit HOST_SLC1_RX_PF_VALID_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_RX_PF_VALID_INT_ENA1 = 0x40000 + // Position of HOST_SLC1_EXT_BIT0_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT0_INT_ENA1_Pos = 0x13 + // Bit mask of HOST_SLC1_EXT_BIT0_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT0_INT_ENA1_Msk = 0x80000 + // Bit HOST_SLC1_EXT_BIT0_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT0_INT_ENA1 = 0x80000 + // Position of HOST_SLC1_EXT_BIT1_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT1_INT_ENA1_Pos = 0x14 + // Bit mask of HOST_SLC1_EXT_BIT1_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT1_INT_ENA1_Msk = 0x100000 + // Bit HOST_SLC1_EXT_BIT1_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT1_INT_ENA1 = 0x100000 + // Position of HOST_SLC1_EXT_BIT2_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT2_INT_ENA1_Pos = 0x15 + // Bit mask of HOST_SLC1_EXT_BIT2_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT2_INT_ENA1_Msk = 0x200000 + // Bit HOST_SLC1_EXT_BIT2_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT2_INT_ENA1 = 0x200000 + // Position of HOST_SLC1_EXT_BIT3_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT3_INT_ENA1_Pos = 0x16 + // Bit mask of HOST_SLC1_EXT_BIT3_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT3_INT_ENA1_Msk = 0x400000 + // Bit HOST_SLC1_EXT_BIT3_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_EXT_BIT3_INT_ENA1 = 0x400000 + // Position of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_Pos = 0x17 + // Bit mask of HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_Msk = 0x800000 + // Bit HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 = 0x800000 + // Position of HOST_SLC1_HOST_RD_RETRY_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_HOST_RD_RETRY_INT_ENA1_Pos = 0x18 + // Bit mask of HOST_SLC1_HOST_RD_RETRY_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_HOST_RD_RETRY_INT_ENA1_Msk = 0x1000000 + // Bit HOST_SLC1_HOST_RD_RETRY_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_HOST_RD_RETRY_INT_ENA1 = 0x1000000 + // Position of HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_Pos = 0x19 + // Bit mask of HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_Msk = 0x2000000 + // Bit HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1. + SLCHOST_HOST_SLC1HOST_INT_ENA1_HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 = 0x2000000 + + // HOST_SLCHOSTDATE + // Position of HOST_SLCHOST_DATE field. + SLCHOST_HOST_SLCHOSTDATE_HOST_SLCHOST_DATE_Pos = 0x0 + // Bit mask of HOST_SLCHOST_DATE field. + SLCHOST_HOST_SLCHOSTDATE_HOST_SLCHOST_DATE_Msk = 0xffffffff + + // HOST_SLCHOSTID + // Position of HOST_SLCHOST_ID field. + SLCHOST_HOST_SLCHOSTID_HOST_SLCHOST_ID_Pos = 0x0 + // Bit mask of HOST_SLCHOST_ID field. + SLCHOST_HOST_SLCHOSTID_HOST_SLCHOST_ID_Msk = 0xffffffff + + // HOST_SLCHOST_CONF + // Position of HOST_FRC_SDIO11 field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_SDIO11_Pos = 0x0 + // Bit mask of HOST_FRC_SDIO11 field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_SDIO11_Msk = 0x1f + // Position of HOST_FRC_SDIO20 field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_SDIO20_Pos = 0x5 + // Bit mask of HOST_FRC_SDIO20 field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_SDIO20_Msk = 0x3e0 + // Position of HOST_FRC_NEG_SAMP field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_NEG_SAMP_Pos = 0xa + // Bit mask of HOST_FRC_NEG_SAMP field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_NEG_SAMP_Msk = 0x7c00 + // Position of HOST_FRC_POS_SAMP field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_POS_SAMP_Pos = 0xf + // Bit mask of HOST_FRC_POS_SAMP field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_POS_SAMP_Msk = 0xf8000 + // Position of HOST_FRC_QUICK_IN field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_QUICK_IN_Pos = 0x14 + // Bit mask of HOST_FRC_QUICK_IN field. + SLCHOST_HOST_SLCHOST_CONF_HOST_FRC_QUICK_IN_Msk = 0x1f00000 + // Position of HOST_SDIO20_INT_DELAY field. + SLCHOST_HOST_SLCHOST_CONF_HOST_SDIO20_INT_DELAY_Pos = 0x19 + // Bit mask of HOST_SDIO20_INT_DELAY field. + SLCHOST_HOST_SLCHOST_CONF_HOST_SDIO20_INT_DELAY_Msk = 0x2000000 + // Bit HOST_SDIO20_INT_DELAY. + SLCHOST_HOST_SLCHOST_CONF_HOST_SDIO20_INT_DELAY = 0x2000000 + // Position of HOST_SDIO_PAD_PULLUP field. + SLCHOST_HOST_SLCHOST_CONF_HOST_SDIO_PAD_PULLUP_Pos = 0x1a + // Bit mask of HOST_SDIO_PAD_PULLUP field. + SLCHOST_HOST_SLCHOST_CONF_HOST_SDIO_PAD_PULLUP_Msk = 0x4000000 + // Bit HOST_SDIO_PAD_PULLUP. + SLCHOST_HOST_SLCHOST_CONF_HOST_SDIO_PAD_PULLUP = 0x4000000 + // Position of HOST_HSPEED_CON_EN field. + SLCHOST_HOST_SLCHOST_CONF_HOST_HSPEED_CON_EN_Pos = 0x1b + // Bit mask of HOST_HSPEED_CON_EN field. + SLCHOST_HOST_SLCHOST_CONF_HOST_HSPEED_CON_EN_Msk = 0x8000000 + // Bit HOST_HSPEED_CON_EN. + SLCHOST_HOST_SLCHOST_CONF_HOST_HSPEED_CON_EN = 0x8000000 + + // HOST_SLCHOST_INF_ST + // Position of HOST_SDIO20_MODE field. + SLCHOST_HOST_SLCHOST_INF_ST_HOST_SDIO20_MODE_Pos = 0x0 + // Bit mask of HOST_SDIO20_MODE field. + SLCHOST_HOST_SLCHOST_INF_ST_HOST_SDIO20_MODE_Msk = 0x1f + // Position of HOST_SDIO_NEG_SAMP field. + SLCHOST_HOST_SLCHOST_INF_ST_HOST_SDIO_NEG_SAMP_Pos = 0x5 + // Bit mask of HOST_SDIO_NEG_SAMP field. + SLCHOST_HOST_SLCHOST_INF_ST_HOST_SDIO_NEG_SAMP_Msk = 0x3e0 + // Position of HOST_SDIO_QUICK_IN field. + SLCHOST_HOST_SLCHOST_INF_ST_HOST_SDIO_QUICK_IN_Pos = 0xa + // Bit mask of HOST_SDIO_QUICK_IN field. + SLCHOST_HOST_SLCHOST_INF_ST_HOST_SDIO_QUICK_IN_Msk = 0x7c00 +) + +// Constants for SPI0: SPI (Serial Peripheral Interface) Controller 0 +const ( + // CMD + // Position of FLASH_PER field. + SPI_CMD_FLASH_PER_Pos = 0x10 + // Bit mask of FLASH_PER field. + SPI_CMD_FLASH_PER_Msk = 0x10000 + // Bit FLASH_PER. + SPI_CMD_FLASH_PER = 0x10000 + // Position of FLASH_PES field. + SPI_CMD_FLASH_PES_Pos = 0x11 + // Bit mask of FLASH_PES field. + SPI_CMD_FLASH_PES_Msk = 0x20000 + // Bit FLASH_PES. + SPI_CMD_FLASH_PES = 0x20000 + // Position of USR field. + SPI_CMD_USR_Pos = 0x12 + // Bit mask of USR field. + SPI_CMD_USR_Msk = 0x40000 + // Bit USR. + SPI_CMD_USR = 0x40000 + // Position of FLASH_HPM field. + SPI_CMD_FLASH_HPM_Pos = 0x13 + // Bit mask of FLASH_HPM field. + SPI_CMD_FLASH_HPM_Msk = 0x80000 + // Bit FLASH_HPM. + SPI_CMD_FLASH_HPM = 0x80000 + // Position of FLASH_RES field. + SPI_CMD_FLASH_RES_Pos = 0x14 + // Bit mask of FLASH_RES field. + SPI_CMD_FLASH_RES_Msk = 0x100000 + // Bit FLASH_RES. + SPI_CMD_FLASH_RES = 0x100000 + // Position of FLASH_DP field. + SPI_CMD_FLASH_DP_Pos = 0x15 + // Bit mask of FLASH_DP field. + SPI_CMD_FLASH_DP_Msk = 0x200000 + // Bit FLASH_DP. + SPI_CMD_FLASH_DP = 0x200000 + // Position of FLASH_CE field. + SPI_CMD_FLASH_CE_Pos = 0x16 + // Bit mask of FLASH_CE field. + SPI_CMD_FLASH_CE_Msk = 0x400000 + // Bit FLASH_CE. + SPI_CMD_FLASH_CE = 0x400000 + // Position of FLASH_BE field. + SPI_CMD_FLASH_BE_Pos = 0x17 + // Bit mask of FLASH_BE field. + SPI_CMD_FLASH_BE_Msk = 0x800000 + // Bit FLASH_BE. + SPI_CMD_FLASH_BE = 0x800000 + // Position of FLASH_SE field. + SPI_CMD_FLASH_SE_Pos = 0x18 + // Bit mask of FLASH_SE field. + SPI_CMD_FLASH_SE_Msk = 0x1000000 + // Bit FLASH_SE. + SPI_CMD_FLASH_SE = 0x1000000 + // Position of FLASH_PP field. + SPI_CMD_FLASH_PP_Pos = 0x19 + // Bit mask of FLASH_PP field. + SPI_CMD_FLASH_PP_Msk = 0x2000000 + // Bit FLASH_PP. + SPI_CMD_FLASH_PP = 0x2000000 + // Position of FLASH_WRSR field. + SPI_CMD_FLASH_WRSR_Pos = 0x1a + // Bit mask of FLASH_WRSR field. + SPI_CMD_FLASH_WRSR_Msk = 0x4000000 + // Bit FLASH_WRSR. + SPI_CMD_FLASH_WRSR = 0x4000000 + // Position of FLASH_RDSR field. + SPI_CMD_FLASH_RDSR_Pos = 0x1b + // Bit mask of FLASH_RDSR field. + SPI_CMD_FLASH_RDSR_Msk = 0x8000000 + // Bit FLASH_RDSR. + SPI_CMD_FLASH_RDSR = 0x8000000 + // Position of FLASH_RDID field. + SPI_CMD_FLASH_RDID_Pos = 0x1c + // Bit mask of FLASH_RDID field. + SPI_CMD_FLASH_RDID_Msk = 0x10000000 + // Bit FLASH_RDID. + SPI_CMD_FLASH_RDID = 0x10000000 + // Position of FLASH_WRDI field. + SPI_CMD_FLASH_WRDI_Pos = 0x1d + // Bit mask of FLASH_WRDI field. + SPI_CMD_FLASH_WRDI_Msk = 0x20000000 + // Bit FLASH_WRDI. + SPI_CMD_FLASH_WRDI = 0x20000000 + // Position of FLASH_WREN field. + SPI_CMD_FLASH_WREN_Pos = 0x1e + // Bit mask of FLASH_WREN field. + SPI_CMD_FLASH_WREN_Msk = 0x40000000 + // Bit FLASH_WREN. + SPI_CMD_FLASH_WREN = 0x40000000 + // Position of FLASH_READ field. + SPI_CMD_FLASH_READ_Pos = 0x1f + // Bit mask of FLASH_READ field. + SPI_CMD_FLASH_READ_Msk = 0x80000000 + // Bit FLASH_READ. + SPI_CMD_FLASH_READ = 0x80000000 + + // CTRL + // Position of FCS_CRC_EN field. + SPI_CTRL_FCS_CRC_EN_Pos = 0xa + // Bit mask of FCS_CRC_EN field. + SPI_CTRL_FCS_CRC_EN_Msk = 0x400 + // Bit FCS_CRC_EN. + SPI_CTRL_FCS_CRC_EN = 0x400 + // Position of TX_CRC_EN field. + SPI_CTRL_TX_CRC_EN_Pos = 0xb + // Bit mask of TX_CRC_EN field. + SPI_CTRL_TX_CRC_EN_Msk = 0x800 + // Bit TX_CRC_EN. + SPI_CTRL_TX_CRC_EN = 0x800 + // Position of WAIT_FLASH_IDLE_EN field. + SPI_CTRL_WAIT_FLASH_IDLE_EN_Pos = 0xc + // Bit mask of WAIT_FLASH_IDLE_EN field. + SPI_CTRL_WAIT_FLASH_IDLE_EN_Msk = 0x1000 + // Bit WAIT_FLASH_IDLE_EN. + SPI_CTRL_WAIT_FLASH_IDLE_EN = 0x1000 + // Position of FASTRD_MODE field. + SPI_CTRL_FASTRD_MODE_Pos = 0xd + // Bit mask of FASTRD_MODE field. + SPI_CTRL_FASTRD_MODE_Msk = 0x2000 + // Bit FASTRD_MODE. + SPI_CTRL_FASTRD_MODE = 0x2000 + // Position of FREAD_DUAL field. + SPI_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI_CTRL_FREAD_DUAL = 0x4000 + // Position of RESANDRES field. + SPI_CTRL_RESANDRES_Pos = 0xf + // Bit mask of RESANDRES field. + SPI_CTRL_RESANDRES_Msk = 0x8000 + // Bit RESANDRES. + SPI_CTRL_RESANDRES = 0x8000 + // Position of FREAD_QUAD field. + SPI_CTRL_FREAD_QUAD_Pos = 0x14 + // Bit mask of FREAD_QUAD field. + SPI_CTRL_FREAD_QUAD_Msk = 0x100000 + // Bit FREAD_QUAD. + SPI_CTRL_FREAD_QUAD = 0x100000 + // Position of WP field. + SPI_CTRL_WP_Pos = 0x15 + // Bit mask of WP field. + SPI_CTRL_WP_Msk = 0x200000 + // Bit WP. + SPI_CTRL_WP = 0x200000 + // Position of WRSR_2B field. + SPI_CTRL_WRSR_2B_Pos = 0x16 + // Bit mask of WRSR_2B field. + SPI_CTRL_WRSR_2B_Msk = 0x400000 + // Bit WRSR_2B. + SPI_CTRL_WRSR_2B = 0x400000 + // Position of FREAD_DIO field. + SPI_CTRL_FREAD_DIO_Pos = 0x17 + // Bit mask of FREAD_DIO field. + SPI_CTRL_FREAD_DIO_Msk = 0x800000 + // Bit FREAD_DIO. + SPI_CTRL_FREAD_DIO = 0x800000 + // Position of FREAD_QIO field. + SPI_CTRL_FREAD_QIO_Pos = 0x18 + // Bit mask of FREAD_QIO field. + SPI_CTRL_FREAD_QIO_Msk = 0x1000000 + // Bit FREAD_QIO. + SPI_CTRL_FREAD_QIO = 0x1000000 + // Position of RD_BIT_ORDER field. + SPI_CTRL_RD_BIT_ORDER_Pos = 0x19 + // Bit mask of RD_BIT_ORDER field. + SPI_CTRL_RD_BIT_ORDER_Msk = 0x2000000 + // Bit RD_BIT_ORDER. + SPI_CTRL_RD_BIT_ORDER = 0x2000000 + // Position of WR_BIT_ORDER field. + SPI_CTRL_WR_BIT_ORDER_Pos = 0x1a + // Bit mask of WR_BIT_ORDER field. + SPI_CTRL_WR_BIT_ORDER_Msk = 0x4000000 + // Bit WR_BIT_ORDER. + SPI_CTRL_WR_BIT_ORDER = 0x4000000 + + // CTRL1 + // Position of CS_HOLD_DELAY_RES field. + SPI_CTRL1_CS_HOLD_DELAY_RES_Pos = 0x10 + // Bit mask of CS_HOLD_DELAY_RES field. + SPI_CTRL1_CS_HOLD_DELAY_RES_Msk = 0xfff0000 + // Position of CS_HOLD_DELAY field. + SPI_CTRL1_CS_HOLD_DELAY_Pos = 0x1c + // Bit mask of CS_HOLD_DELAY field. + SPI_CTRL1_CS_HOLD_DELAY_Msk = 0xf0000000 + + // RD_STATUS + // Position of STATUS field. + SPI_RD_STATUS_STATUS_Pos = 0x0 + // Bit mask of STATUS field. + SPI_RD_STATUS_STATUS_Msk = 0xffff + // Position of WB_MODE field. + SPI_RD_STATUS_WB_MODE_Pos = 0x10 + // Bit mask of WB_MODE field. + SPI_RD_STATUS_WB_MODE_Msk = 0xff0000 + // Position of STATUS_EXT field. + SPI_RD_STATUS_STATUS_EXT_Pos = 0x18 + // Bit mask of STATUS_EXT field. + SPI_RD_STATUS_STATUS_EXT_Msk = 0xff000000 + + // CTRL2 + // Position of SETUP_TIME field. + SPI_CTRL2_SETUP_TIME_Pos = 0x0 + // Bit mask of SETUP_TIME field. + SPI_CTRL2_SETUP_TIME_Msk = 0xf + // Position of HOLD_TIME field. + SPI_CTRL2_HOLD_TIME_Pos = 0x4 + // Bit mask of HOLD_TIME field. + SPI_CTRL2_HOLD_TIME_Msk = 0xf0 + // Position of CK_OUT_LOW_MODE field. + SPI_CTRL2_CK_OUT_LOW_MODE_Pos = 0x8 + // Bit mask of CK_OUT_LOW_MODE field. + SPI_CTRL2_CK_OUT_LOW_MODE_Msk = 0xf00 + // Position of CK_OUT_HIGH_MODE field. + SPI_CTRL2_CK_OUT_HIGH_MODE_Pos = 0xc + // Bit mask of CK_OUT_HIGH_MODE field. + SPI_CTRL2_CK_OUT_HIGH_MODE_Msk = 0xf000 + // Position of MISO_DELAY_MODE field. + SPI_CTRL2_MISO_DELAY_MODE_Pos = 0x10 + // Bit mask of MISO_DELAY_MODE field. + SPI_CTRL2_MISO_DELAY_MODE_Msk = 0x30000 + // Position of MISO_DELAY_NUM field. + SPI_CTRL2_MISO_DELAY_NUM_Pos = 0x12 + // Bit mask of MISO_DELAY_NUM field. + SPI_CTRL2_MISO_DELAY_NUM_Msk = 0x1c0000 + // Position of MOSI_DELAY_MODE field. + SPI_CTRL2_MOSI_DELAY_MODE_Pos = 0x15 + // Bit mask of MOSI_DELAY_MODE field. + SPI_CTRL2_MOSI_DELAY_MODE_Msk = 0x600000 + // Position of MOSI_DELAY_NUM field. + SPI_CTRL2_MOSI_DELAY_NUM_Pos = 0x17 + // Bit mask of MOSI_DELAY_NUM field. + SPI_CTRL2_MOSI_DELAY_NUM_Msk = 0x3800000 + // Position of CS_DELAY_MODE field. + SPI_CTRL2_CS_DELAY_MODE_Pos = 0x1a + // Bit mask of CS_DELAY_MODE field. + SPI_CTRL2_CS_DELAY_MODE_Msk = 0xc000000 + // Position of CS_DELAY_NUM field. + SPI_CTRL2_CS_DELAY_NUM_Pos = 0x1c + // Bit mask of CS_DELAY_NUM field. + SPI_CTRL2_CS_DELAY_NUM_Msk = 0xf0000000 + + // CLOCK + // Position of CLKCNT_L field. + SPI_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI_CLOCK_CLKCNT_L_Msk = 0x3f + // Position of CLKCNT_H field. + SPI_CLOCK_CLKCNT_H_Pos = 0x6 + // Bit mask of CLKCNT_H field. + SPI_CLOCK_CLKCNT_H_Msk = 0xfc0 + // Position of CLKCNT_N field. + SPI_CLOCK_CLKCNT_N_Pos = 0xc + // Bit mask of CLKCNT_N field. + SPI_CLOCK_CLKCNT_N_Msk = 0x3f000 + // Position of CLKDIV_PRE field. + SPI_CLOCK_CLKDIV_PRE_Pos = 0x12 + // Bit mask of CLKDIV_PRE field. + SPI_CLOCK_CLKDIV_PRE_Msk = 0x7ffc0000 + // Position of CLK_EQU_SYSCLK field. + SPI_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER + // Position of DOUTDIN field. + SPI_USER_DOUTDIN_Pos = 0x0 + // Bit mask of DOUTDIN field. + SPI_USER_DOUTDIN_Msk = 0x1 + // Bit DOUTDIN. + SPI_USER_DOUTDIN = 0x1 + // Position of CS_HOLD field. + SPI_USER_CS_HOLD_Pos = 0x4 + // Bit mask of CS_HOLD field. + SPI_USER_CS_HOLD_Msk = 0x10 + // Bit CS_HOLD. + SPI_USER_CS_HOLD = 0x10 + // Position of CS_SETUP field. + SPI_USER_CS_SETUP_Pos = 0x5 + // Bit mask of CS_SETUP field. + SPI_USER_CS_SETUP_Msk = 0x20 + // Bit CS_SETUP. + SPI_USER_CS_SETUP = 0x20 + // Position of CK_I_EDGE field. + SPI_USER_CK_I_EDGE_Pos = 0x6 + // Bit mask of CK_I_EDGE field. + SPI_USER_CK_I_EDGE_Msk = 0x40 + // Bit CK_I_EDGE. + SPI_USER_CK_I_EDGE = 0x40 + // Position of CK_OUT_EDGE field. + SPI_USER_CK_OUT_EDGE_Pos = 0x7 + // Bit mask of CK_OUT_EDGE field. + SPI_USER_CK_OUT_EDGE_Msk = 0x80 + // Bit CK_OUT_EDGE. + SPI_USER_CK_OUT_EDGE = 0x80 + // Position of RD_BYTE_ORDER field. + SPI_USER_RD_BYTE_ORDER_Pos = 0xa + // Bit mask of RD_BYTE_ORDER field. + SPI_USER_RD_BYTE_ORDER_Msk = 0x400 + // Bit RD_BYTE_ORDER. + SPI_USER_RD_BYTE_ORDER = 0x400 + // Position of WR_BYTE_ORDER field. + SPI_USER_WR_BYTE_ORDER_Pos = 0xb + // Bit mask of WR_BYTE_ORDER field. + SPI_USER_WR_BYTE_ORDER_Msk = 0x800 + // Bit WR_BYTE_ORDER. + SPI_USER_WR_BYTE_ORDER = 0x800 + // Position of FWRITE_DUAL field. + SPI_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI_USER_FWRITE_QUAD = 0x2000 + // Position of FWRITE_DIO field. + SPI_USER_FWRITE_DIO_Pos = 0xe + // Bit mask of FWRITE_DIO field. + SPI_USER_FWRITE_DIO_Msk = 0x4000 + // Bit FWRITE_DIO. + SPI_USER_FWRITE_DIO = 0x4000 + // Position of FWRITE_QIO field. + SPI_USER_FWRITE_QIO_Pos = 0xf + // Bit mask of FWRITE_QIO field. + SPI_USER_FWRITE_QIO_Msk = 0x8000 + // Bit FWRITE_QIO. + SPI_USER_FWRITE_QIO = 0x8000 + // Position of SIO field. + SPI_USER_SIO_Pos = 0x10 + // Bit mask of SIO field. + SPI_USER_SIO_Msk = 0x10000 + // Bit SIO. + SPI_USER_SIO = 0x10000 + // Position of USR_HOLD_POL field. + SPI_USER_USR_HOLD_POL_Pos = 0x11 + // Bit mask of USR_HOLD_POL field. + SPI_USER_USR_HOLD_POL_Msk = 0x20000 + // Bit USR_HOLD_POL. + SPI_USER_USR_HOLD_POL = 0x20000 + // Position of USR_DOUT_HOLD field. + SPI_USER_USR_DOUT_HOLD_Pos = 0x12 + // Bit mask of USR_DOUT_HOLD field. + SPI_USER_USR_DOUT_HOLD_Msk = 0x40000 + // Bit USR_DOUT_HOLD. + SPI_USER_USR_DOUT_HOLD = 0x40000 + // Position of USR_DIN_HOLD field. + SPI_USER_USR_DIN_HOLD_Pos = 0x13 + // Bit mask of USR_DIN_HOLD field. + SPI_USER_USR_DIN_HOLD_Msk = 0x80000 + // Bit USR_DIN_HOLD. + SPI_USER_USR_DIN_HOLD = 0x80000 + // Position of USR_DUMMY_HOLD field. + SPI_USER_USR_DUMMY_HOLD_Pos = 0x14 + // Bit mask of USR_DUMMY_HOLD field. + SPI_USER_USR_DUMMY_HOLD_Msk = 0x100000 + // Bit USR_DUMMY_HOLD. + SPI_USER_USR_DUMMY_HOLD = 0x100000 + // Position of USR_ADDR_HOLD field. + SPI_USER_USR_ADDR_HOLD_Pos = 0x15 + // Bit mask of USR_ADDR_HOLD field. + SPI_USER_USR_ADDR_HOLD_Msk = 0x200000 + // Bit USR_ADDR_HOLD. + SPI_USER_USR_ADDR_HOLD = 0x200000 + // Position of USR_CMD_HOLD field. + SPI_USER_USR_CMD_HOLD_Pos = 0x16 + // Bit mask of USR_CMD_HOLD field. + SPI_USER_USR_CMD_HOLD_Msk = 0x400000 + // Bit USR_CMD_HOLD. + SPI_USER_USR_CMD_HOLD = 0x400000 + // Position of USR_PREP_HOLD field. + SPI_USER_USR_PREP_HOLD_Pos = 0x17 + // Bit mask of USR_PREP_HOLD field. + SPI_USER_USR_PREP_HOLD_Msk = 0x800000 + // Bit USR_PREP_HOLD. + SPI_USER_USR_PREP_HOLD = 0x800000 + // Position of USR_MISO_HIGHPART field. + SPI_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI_USER_USR_COMMAND = 0x80000000 + + // USER1 + // Position of USR_DUMMY_CYCLELEN field. + SPI_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI_USER1_USR_DUMMY_CYCLELEN_Msk = 0xff + // Position of USR_ADDR_BITLEN field. + SPI_USER1_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of USR_ADDR_BITLEN field. + SPI_USER1_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // USER2 + // Position of USR_COMMAND_VALUE field. + SPI_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of USR_COMMAND_BITLEN field. + SPI_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MOSI_DLEN + // Position of USR_MOSI_DBITLEN field. + SPI_MOSI_DLEN_USR_MOSI_DBITLEN_Pos = 0x0 + // Bit mask of USR_MOSI_DBITLEN field. + SPI_MOSI_DLEN_USR_MOSI_DBITLEN_Msk = 0xffffff + + // MISO_DLEN + // Position of USR_MISO_DBITLEN field. + SPI_MISO_DLEN_USR_MISO_DBITLEN_Pos = 0x0 + // Bit mask of USR_MISO_DBITLEN field. + SPI_MISO_DLEN_USR_MISO_DBITLEN_Msk = 0xffffff + + // SLV_WR_STATUS + // Position of SLV_WR_ST field. + SPI_SLV_WR_STATUS_SLV_WR_ST_Pos = 0x0 + // Bit mask of SLV_WR_ST field. + SPI_SLV_WR_STATUS_SLV_WR_ST_Msk = 0xffffffff + + // PIN + // Position of CS0_DIS field. + SPI_PIN_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI_PIN_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI_PIN_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI_PIN_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI_PIN_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI_PIN_CS1_DIS = 0x2 + // Position of CS2_DIS field. + SPI_PIN_CS2_DIS_Pos = 0x2 + // Bit mask of CS2_DIS field. + SPI_PIN_CS2_DIS_Msk = 0x4 + // Bit CS2_DIS. + SPI_PIN_CS2_DIS = 0x4 + // Position of CK_DIS field. + SPI_PIN_CK_DIS_Pos = 0x5 + // Bit mask of CK_DIS field. + SPI_PIN_CK_DIS_Msk = 0x20 + // Bit CK_DIS. + SPI_PIN_CK_DIS = 0x20 + // Position of MASTER_CS_POL field. + SPI_PIN_MASTER_CS_POL_Pos = 0x6 + // Bit mask of MASTER_CS_POL field. + SPI_PIN_MASTER_CS_POL_Msk = 0x1c0 + // Position of MASTER_CK_SEL field. + SPI_PIN_MASTER_CK_SEL_Pos = 0xb + // Bit mask of MASTER_CK_SEL field. + SPI_PIN_MASTER_CK_SEL_Msk = 0x3800 + // Position of CK_IDLE_EDGE field. + SPI_PIN_CK_IDLE_EDGE_Pos = 0x1d + // Bit mask of CK_IDLE_EDGE field. + SPI_PIN_CK_IDLE_EDGE_Msk = 0x20000000 + // Bit CK_IDLE_EDGE. + SPI_PIN_CK_IDLE_EDGE = 0x20000000 + // Position of CS_KEEP_ACTIVE field. + SPI_PIN_CS_KEEP_ACTIVE_Pos = 0x1e + // Bit mask of CS_KEEP_ACTIVE field. + SPI_PIN_CS_KEEP_ACTIVE_Msk = 0x40000000 + // Bit CS_KEEP_ACTIVE. + SPI_PIN_CS_KEEP_ACTIVE = 0x40000000 + + // SLAVE + // Position of SLV_RD_BUF_DONE field. + SPI_SLAVE_SLV_RD_BUF_DONE_Pos = 0x0 + // Bit mask of SLV_RD_BUF_DONE field. + SPI_SLAVE_SLV_RD_BUF_DONE_Msk = 0x1 + // Bit SLV_RD_BUF_DONE. + SPI_SLAVE_SLV_RD_BUF_DONE = 0x1 + // Position of SLV_WR_BUF_DONE field. + SPI_SLAVE_SLV_WR_BUF_DONE_Pos = 0x1 + // Bit mask of SLV_WR_BUF_DONE field. + SPI_SLAVE_SLV_WR_BUF_DONE_Msk = 0x2 + // Bit SLV_WR_BUF_DONE. + SPI_SLAVE_SLV_WR_BUF_DONE = 0x2 + // Position of SLV_RD_STA_DONE field. + SPI_SLAVE_SLV_RD_STA_DONE_Pos = 0x2 + // Bit mask of SLV_RD_STA_DONE field. + SPI_SLAVE_SLV_RD_STA_DONE_Msk = 0x4 + // Bit SLV_RD_STA_DONE. + SPI_SLAVE_SLV_RD_STA_DONE = 0x4 + // Position of SLV_WR_STA_DONE field. + SPI_SLAVE_SLV_WR_STA_DONE_Pos = 0x3 + // Bit mask of SLV_WR_STA_DONE field. + SPI_SLAVE_SLV_WR_STA_DONE_Msk = 0x8 + // Bit SLV_WR_STA_DONE. + SPI_SLAVE_SLV_WR_STA_DONE = 0x8 + // Position of TRANS_DONE field. + SPI_SLAVE_TRANS_DONE_Pos = 0x4 + // Bit mask of TRANS_DONE field. + SPI_SLAVE_TRANS_DONE_Msk = 0x10 + // Bit TRANS_DONE. + SPI_SLAVE_TRANS_DONE = 0x10 + // Position of INT_EN field. + SPI_SLAVE_INT_EN_Pos = 0x5 + // Bit mask of INT_EN field. + SPI_SLAVE_INT_EN_Msk = 0x3e0 + // Position of CS_I_MODE field. + SPI_SLAVE_CS_I_MODE_Pos = 0xa + // Bit mask of CS_I_MODE field. + SPI_SLAVE_CS_I_MODE_Msk = 0xc00 + // Position of SLV_LAST_COMMAND field. + SPI_SLAVE_SLV_LAST_COMMAND_Pos = 0x11 + // Bit mask of SLV_LAST_COMMAND field. + SPI_SLAVE_SLV_LAST_COMMAND_Msk = 0xe0000 + // Position of SLV_LAST_STATE field. + SPI_SLAVE_SLV_LAST_STATE_Pos = 0x14 + // Bit mask of SLV_LAST_STATE field. + SPI_SLAVE_SLV_LAST_STATE_Msk = 0x700000 + // Position of TRANS_CNT field. + SPI_SLAVE_TRANS_CNT_Pos = 0x17 + // Bit mask of TRANS_CNT field. + SPI_SLAVE_TRANS_CNT_Msk = 0x7800000 + // Position of SLV_CMD_DEFINE field. + SPI_SLAVE_SLV_CMD_DEFINE_Pos = 0x1b + // Bit mask of SLV_CMD_DEFINE field. + SPI_SLAVE_SLV_CMD_DEFINE_Msk = 0x8000000 + // Bit SLV_CMD_DEFINE. + SPI_SLAVE_SLV_CMD_DEFINE = 0x8000000 + // Position of SLV_WR_RD_STA_EN field. + SPI_SLAVE_SLV_WR_RD_STA_EN_Pos = 0x1c + // Bit mask of SLV_WR_RD_STA_EN field. + SPI_SLAVE_SLV_WR_RD_STA_EN_Msk = 0x10000000 + // Bit SLV_WR_RD_STA_EN. + SPI_SLAVE_SLV_WR_RD_STA_EN = 0x10000000 + // Position of SLV_WR_RD_BUF_EN field. + SPI_SLAVE_SLV_WR_RD_BUF_EN_Pos = 0x1d + // Bit mask of SLV_WR_RD_BUF_EN field. + SPI_SLAVE_SLV_WR_RD_BUF_EN_Msk = 0x20000000 + // Bit SLV_WR_RD_BUF_EN. + SPI_SLAVE_SLV_WR_RD_BUF_EN = 0x20000000 + // Position of MODE field. + SPI_SLAVE_MODE_Pos = 0x1e + // Bit mask of MODE field. + SPI_SLAVE_MODE_Msk = 0x40000000 + // Bit MODE. + SPI_SLAVE_MODE = 0x40000000 + // Position of SYNC_RESET field. + SPI_SLAVE_SYNC_RESET_Pos = 0x1f + // Bit mask of SYNC_RESET field. + SPI_SLAVE_SYNC_RESET_Msk = 0x80000000 + // Bit SYNC_RESET. + SPI_SLAVE_SYNC_RESET = 0x80000000 + + // SLAVE1 + // Position of SLV_RDBUF_DUMMY_EN field. + SPI_SLAVE1_SLV_RDBUF_DUMMY_EN_Pos = 0x0 + // Bit mask of SLV_RDBUF_DUMMY_EN field. + SPI_SLAVE1_SLV_RDBUF_DUMMY_EN_Msk = 0x1 + // Bit SLV_RDBUF_DUMMY_EN. + SPI_SLAVE1_SLV_RDBUF_DUMMY_EN = 0x1 + // Position of SLV_WRBUF_DUMMY_EN field. + SPI_SLAVE1_SLV_WRBUF_DUMMY_EN_Pos = 0x1 + // Bit mask of SLV_WRBUF_DUMMY_EN field. + SPI_SLAVE1_SLV_WRBUF_DUMMY_EN_Msk = 0x2 + // Bit SLV_WRBUF_DUMMY_EN. + SPI_SLAVE1_SLV_WRBUF_DUMMY_EN = 0x2 + // Position of SLV_RDSTA_DUMMY_EN field. + SPI_SLAVE1_SLV_RDSTA_DUMMY_EN_Pos = 0x2 + // Bit mask of SLV_RDSTA_DUMMY_EN field. + SPI_SLAVE1_SLV_RDSTA_DUMMY_EN_Msk = 0x4 + // Bit SLV_RDSTA_DUMMY_EN. + SPI_SLAVE1_SLV_RDSTA_DUMMY_EN = 0x4 + // Position of SLV_WRSTA_DUMMY_EN field. + SPI_SLAVE1_SLV_WRSTA_DUMMY_EN_Pos = 0x3 + // Bit mask of SLV_WRSTA_DUMMY_EN field. + SPI_SLAVE1_SLV_WRSTA_DUMMY_EN_Msk = 0x8 + // Bit SLV_WRSTA_DUMMY_EN. + SPI_SLAVE1_SLV_WRSTA_DUMMY_EN = 0x8 + // Position of SLV_WR_ADDR_BITLEN field. + SPI_SLAVE1_SLV_WR_ADDR_BITLEN_Pos = 0x4 + // Bit mask of SLV_WR_ADDR_BITLEN field. + SPI_SLAVE1_SLV_WR_ADDR_BITLEN_Msk = 0x3f0 + // Position of SLV_RD_ADDR_BITLEN field. + SPI_SLAVE1_SLV_RD_ADDR_BITLEN_Pos = 0xa + // Bit mask of SLV_RD_ADDR_BITLEN field. + SPI_SLAVE1_SLV_RD_ADDR_BITLEN_Msk = 0xfc00 + // Position of SLV_STATUS_READBACK field. + SPI_SLAVE1_SLV_STATUS_READBACK_Pos = 0x19 + // Bit mask of SLV_STATUS_READBACK field. + SPI_SLAVE1_SLV_STATUS_READBACK_Msk = 0x2000000 + // Bit SLV_STATUS_READBACK. + SPI_SLAVE1_SLV_STATUS_READBACK = 0x2000000 + // Position of SLV_STATUS_FAST_EN field. + SPI_SLAVE1_SLV_STATUS_FAST_EN_Pos = 0x1a + // Bit mask of SLV_STATUS_FAST_EN field. + SPI_SLAVE1_SLV_STATUS_FAST_EN_Msk = 0x4000000 + // Bit SLV_STATUS_FAST_EN. + SPI_SLAVE1_SLV_STATUS_FAST_EN = 0x4000000 + // Position of SLV_STATUS_BITLEN field. + SPI_SLAVE1_SLV_STATUS_BITLEN_Pos = 0x1b + // Bit mask of SLV_STATUS_BITLEN field. + SPI_SLAVE1_SLV_STATUS_BITLEN_Msk = 0xf8000000 + + // SLAVE2 + // Position of SLV_RDSTA_DUMMY_CYCLELEN field. + SPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of SLV_RDSTA_DUMMY_CYCLELEN field. + SPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN_Msk = 0xff + // Position of SLV_WRSTA_DUMMY_CYCLELEN field. + SPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN_Pos = 0x8 + // Bit mask of SLV_WRSTA_DUMMY_CYCLELEN field. + SPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN_Msk = 0xff00 + // Position of SLV_RDBUF_DUMMY_CYCLELEN field. + SPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN_Pos = 0x10 + // Bit mask of SLV_RDBUF_DUMMY_CYCLELEN field. + SPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN_Msk = 0xff0000 + // Position of SLV_WRBUF_DUMMY_CYCLELEN field. + SPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN_Pos = 0x18 + // Bit mask of SLV_WRBUF_DUMMY_CYCLELEN field. + SPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN_Msk = 0xff000000 + + // SLAVE3 + // Position of SLV_RDBUF_CMD_VALUE field. + SPI_SLAVE3_SLV_RDBUF_CMD_VALUE_Pos = 0x0 + // Bit mask of SLV_RDBUF_CMD_VALUE field. + SPI_SLAVE3_SLV_RDBUF_CMD_VALUE_Msk = 0xff + // Position of SLV_WRBUF_CMD_VALUE field. + SPI_SLAVE3_SLV_WRBUF_CMD_VALUE_Pos = 0x8 + // Bit mask of SLV_WRBUF_CMD_VALUE field. + SPI_SLAVE3_SLV_WRBUF_CMD_VALUE_Msk = 0xff00 + // Position of SLV_RDSTA_CMD_VALUE field. + SPI_SLAVE3_SLV_RDSTA_CMD_VALUE_Pos = 0x10 + // Bit mask of SLV_RDSTA_CMD_VALUE field. + SPI_SLAVE3_SLV_RDSTA_CMD_VALUE_Msk = 0xff0000 + // Position of SLV_WRSTA_CMD_VALUE field. + SPI_SLAVE3_SLV_WRSTA_CMD_VALUE_Pos = 0x18 + // Bit mask of SLV_WRSTA_CMD_VALUE field. + SPI_SLAVE3_SLV_WRSTA_CMD_VALUE_Msk = 0xff000000 + + // SLV_WRBUF_DLEN + // Position of SLV_WRBUF_DBITLEN field. + SPI_SLV_WRBUF_DLEN_SLV_WRBUF_DBITLEN_Pos = 0x0 + // Bit mask of SLV_WRBUF_DBITLEN field. + SPI_SLV_WRBUF_DLEN_SLV_WRBUF_DBITLEN_Msk = 0xffffff + + // SLV_RDBUF_DLEN + // Position of SLV_RDBUF_DBITLEN field. + SPI_SLV_RDBUF_DLEN_SLV_RDBUF_DBITLEN_Pos = 0x0 + // Bit mask of SLV_RDBUF_DBITLEN field. + SPI_SLV_RDBUF_DLEN_SLV_RDBUF_DBITLEN_Msk = 0xffffff + + // CACHE_FCTRL + // Position of CACHE_REQ_EN field. + SPI_CACHE_FCTRL_CACHE_REQ_EN_Pos = 0x0 + // Bit mask of CACHE_REQ_EN field. + SPI_CACHE_FCTRL_CACHE_REQ_EN_Msk = 0x1 + // Bit CACHE_REQ_EN. + SPI_CACHE_FCTRL_CACHE_REQ_EN = 0x1 + // Position of CACHE_USR_CMD_4BYTE field. + SPI_CACHE_FCTRL_CACHE_USR_CMD_4BYTE_Pos = 0x1 + // Bit mask of CACHE_USR_CMD_4BYTE field. + SPI_CACHE_FCTRL_CACHE_USR_CMD_4BYTE_Msk = 0x2 + // Bit CACHE_USR_CMD_4BYTE. + SPI_CACHE_FCTRL_CACHE_USR_CMD_4BYTE = 0x2 + // Position of CACHE_FLASH_USR_CMD field. + SPI_CACHE_FCTRL_CACHE_FLASH_USR_CMD_Pos = 0x2 + // Bit mask of CACHE_FLASH_USR_CMD field. + SPI_CACHE_FCTRL_CACHE_FLASH_USR_CMD_Msk = 0x4 + // Bit CACHE_FLASH_USR_CMD. + SPI_CACHE_FCTRL_CACHE_FLASH_USR_CMD = 0x4 + // Position of CACHE_FLASH_PES_EN field. + SPI_CACHE_FCTRL_CACHE_FLASH_PES_EN_Pos = 0x3 + // Bit mask of CACHE_FLASH_PES_EN field. + SPI_CACHE_FCTRL_CACHE_FLASH_PES_EN_Msk = 0x8 + // Bit CACHE_FLASH_PES_EN. + SPI_CACHE_FCTRL_CACHE_FLASH_PES_EN = 0x8 + + // CACHE_SCTRL + // Position of USR_SRAM_DIO field. + SPI_CACHE_SCTRL_USR_SRAM_DIO_Pos = 0x1 + // Bit mask of USR_SRAM_DIO field. + SPI_CACHE_SCTRL_USR_SRAM_DIO_Msk = 0x2 + // Bit USR_SRAM_DIO. + SPI_CACHE_SCTRL_USR_SRAM_DIO = 0x2 + // Position of USR_SRAM_QIO field. + SPI_CACHE_SCTRL_USR_SRAM_QIO_Pos = 0x2 + // Bit mask of USR_SRAM_QIO field. + SPI_CACHE_SCTRL_USR_SRAM_QIO_Msk = 0x4 + // Bit USR_SRAM_QIO. + SPI_CACHE_SCTRL_USR_SRAM_QIO = 0x4 + // Position of USR_WR_SRAM_DUMMY field. + SPI_CACHE_SCTRL_USR_WR_SRAM_DUMMY_Pos = 0x3 + // Bit mask of USR_WR_SRAM_DUMMY field. + SPI_CACHE_SCTRL_USR_WR_SRAM_DUMMY_Msk = 0x8 + // Bit USR_WR_SRAM_DUMMY. + SPI_CACHE_SCTRL_USR_WR_SRAM_DUMMY = 0x8 + // Position of USR_RD_SRAM_DUMMY field. + SPI_CACHE_SCTRL_USR_RD_SRAM_DUMMY_Pos = 0x4 + // Bit mask of USR_RD_SRAM_DUMMY field. + SPI_CACHE_SCTRL_USR_RD_SRAM_DUMMY_Msk = 0x10 + // Bit USR_RD_SRAM_DUMMY. + SPI_CACHE_SCTRL_USR_RD_SRAM_DUMMY = 0x10 + // Position of CACHE_SRAM_USR_RCMD field. + SPI_CACHE_SCTRL_CACHE_SRAM_USR_RCMD_Pos = 0x5 + // Bit mask of CACHE_SRAM_USR_RCMD field. + SPI_CACHE_SCTRL_CACHE_SRAM_USR_RCMD_Msk = 0x20 + // Bit CACHE_SRAM_USR_RCMD. + SPI_CACHE_SCTRL_CACHE_SRAM_USR_RCMD = 0x20 + // Position of SRAM_BYTES_LEN field. + SPI_CACHE_SCTRL_SRAM_BYTES_LEN_Pos = 0x6 + // Bit mask of SRAM_BYTES_LEN field. + SPI_CACHE_SCTRL_SRAM_BYTES_LEN_Msk = 0x3fc0 + // Position of SRAM_DUMMY_CYCLELEN field. + SPI_CACHE_SCTRL_SRAM_DUMMY_CYCLELEN_Pos = 0xe + // Bit mask of SRAM_DUMMY_CYCLELEN field. + SPI_CACHE_SCTRL_SRAM_DUMMY_CYCLELEN_Msk = 0x3fc000 + // Position of SRAM_ADDR_BITLEN field. + SPI_CACHE_SCTRL_SRAM_ADDR_BITLEN_Pos = 0x16 + // Bit mask of SRAM_ADDR_BITLEN field. + SPI_CACHE_SCTRL_SRAM_ADDR_BITLEN_Msk = 0xfc00000 + // Position of CACHE_SRAM_USR_WCMD field. + SPI_CACHE_SCTRL_CACHE_SRAM_USR_WCMD_Pos = 0x1c + // Bit mask of CACHE_SRAM_USR_WCMD field. + SPI_CACHE_SCTRL_CACHE_SRAM_USR_WCMD_Msk = 0x10000000 + // Bit CACHE_SRAM_USR_WCMD. + SPI_CACHE_SCTRL_CACHE_SRAM_USR_WCMD = 0x10000000 + + // SRAM_CMD + // Position of SRAM_DIO field. + SPI_SRAM_CMD_SRAM_DIO_Pos = 0x0 + // Bit mask of SRAM_DIO field. + SPI_SRAM_CMD_SRAM_DIO_Msk = 0x1 + // Bit SRAM_DIO. + SPI_SRAM_CMD_SRAM_DIO = 0x1 + // Position of SRAM_QIO field. + SPI_SRAM_CMD_SRAM_QIO_Pos = 0x1 + // Bit mask of SRAM_QIO field. + SPI_SRAM_CMD_SRAM_QIO_Msk = 0x2 + // Bit SRAM_QIO. + SPI_SRAM_CMD_SRAM_QIO = 0x2 + // Position of SRAM_RSTIO field. + SPI_SRAM_CMD_SRAM_RSTIO_Pos = 0x4 + // Bit mask of SRAM_RSTIO field. + SPI_SRAM_CMD_SRAM_RSTIO_Msk = 0x10 + // Bit SRAM_RSTIO. + SPI_SRAM_CMD_SRAM_RSTIO = 0x10 + + // SRAM_DRD_CMD + // Position of CACHE_SRAM_USR_RD_CMD_VALUE field. + SPI_SRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_VALUE_Pos = 0x0 + // Bit mask of CACHE_SRAM_USR_RD_CMD_VALUE field. + SPI_SRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_VALUE_Msk = 0xffff + // Position of CACHE_SRAM_USR_RD_CMD_BITLEN field. + SPI_SRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_BITLEN_Pos = 0x1c + // Bit mask of CACHE_SRAM_USR_RD_CMD_BITLEN field. + SPI_SRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_BITLEN_Msk = 0xf0000000 + + // SRAM_DWR_CMD + // Position of CACHE_SRAM_USR_WR_CMD_VALUE field. + SPI_SRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_VALUE_Pos = 0x0 + // Bit mask of CACHE_SRAM_USR_WR_CMD_VALUE field. + SPI_SRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_VALUE_Msk = 0xffff + // Position of CACHE_SRAM_USR_WR_CMD_BITLEN field. + SPI_SRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_BITLEN_Pos = 0x1c + // Bit mask of CACHE_SRAM_USR_WR_CMD_BITLEN field. + SPI_SRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_BITLEN_Msk = 0xf0000000 + + // SLV_RD_BIT + // Position of SLV_RDATA_BIT field. + SPI_SLV_RD_BIT_SLV_RDATA_BIT_Pos = 0x0 + // Bit mask of SLV_RDATA_BIT field. + SPI_SLV_RD_BIT_SLV_RDATA_BIT_Msk = 0xffffff + + // W0 + // Position of BUF0 field. + SPI_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI_W0_BUF0_Msk = 0xffffffff + + // W1 + // Position of BUF1 field. + SPI_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI_W1_BUF1_Msk = 0xffffffff + + // W2 + // Position of BUF2 field. + SPI_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI_W2_BUF2_Msk = 0xffffffff + + // W3 + // Position of BUF3 field. + SPI_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI_W3_BUF3_Msk = 0xffffffff + + // W4 + // Position of BUF4 field. + SPI_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI_W4_BUF4_Msk = 0xffffffff + + // W5 + // Position of BUF5 field. + SPI_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI_W5_BUF5_Msk = 0xffffffff + + // W6 + // Position of BUF6 field. + SPI_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI_W6_BUF6_Msk = 0xffffffff + + // W7 + // Position of BUF7 field. + SPI_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI_W7_BUF7_Msk = 0xffffffff + + // W8 + // Position of BUF8 field. + SPI_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI_W8_BUF8_Msk = 0xffffffff + + // W9 + // Position of BUF9 field. + SPI_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI_W9_BUF9_Msk = 0xffffffff + + // W10 + // Position of BUF10 field. + SPI_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI_W10_BUF10_Msk = 0xffffffff + + // W11 + // Position of BUF11 field. + SPI_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI_W11_BUF11_Msk = 0xffffffff + + // W12 + // Position of BUF12 field. + SPI_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI_W12_BUF12_Msk = 0xffffffff + + // W13 + // Position of BUF13 field. + SPI_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI_W13_BUF13_Msk = 0xffffffff + + // W14 + // Position of BUF14 field. + SPI_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI_W14_BUF14_Msk = 0xffffffff + + // W15 + // Position of BUF15 field. + SPI_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI_W15_BUF15_Msk = 0xffffffff + + // TX_CRC + // Position of DATA field. + SPI_TX_CRC_DATA_Pos = 0x0 + // Bit mask of DATA field. + SPI_TX_CRC_DATA_Msk = 0xffffffff + + // EXT0 + // Position of T_PP_TIME field. + SPI_EXT0_T_PP_TIME_Pos = 0x0 + // Bit mask of T_PP_TIME field. + SPI_EXT0_T_PP_TIME_Msk = 0xfff + // Position of T_PP_SHIFT field. + SPI_EXT0_T_PP_SHIFT_Pos = 0x10 + // Bit mask of T_PP_SHIFT field. + SPI_EXT0_T_PP_SHIFT_Msk = 0xf0000 + // Position of T_PP_ENA field. + SPI_EXT0_T_PP_ENA_Pos = 0x1f + // Bit mask of T_PP_ENA field. + SPI_EXT0_T_PP_ENA_Msk = 0x80000000 + // Bit T_PP_ENA. + SPI_EXT0_T_PP_ENA = 0x80000000 + + // EXT1 + // Position of T_ERASE_TIME field. + SPI_EXT1_T_ERASE_TIME_Pos = 0x0 + // Bit mask of T_ERASE_TIME field. + SPI_EXT1_T_ERASE_TIME_Msk = 0xfff + // Position of T_ERASE_SHIFT field. + SPI_EXT1_T_ERASE_SHIFT_Pos = 0x10 + // Bit mask of T_ERASE_SHIFT field. + SPI_EXT1_T_ERASE_SHIFT_Msk = 0xf0000 + // Position of T_ERASE_ENA field. + SPI_EXT1_T_ERASE_ENA_Pos = 0x1f + // Bit mask of T_ERASE_ENA field. + SPI_EXT1_T_ERASE_ENA_Msk = 0x80000000 + // Bit T_ERASE_ENA. + SPI_EXT1_T_ERASE_ENA = 0x80000000 + + // EXT2 + // Position of ST field. + SPI_EXT2_ST_Pos = 0x0 + // Bit mask of ST field. + SPI_EXT2_ST_Msk = 0x7 + + // EXT3 + // Position of INT_HOLD_ENA field. + SPI_EXT3_INT_HOLD_ENA_Pos = 0x0 + // Bit mask of INT_HOLD_ENA field. + SPI_EXT3_INT_HOLD_ENA_Msk = 0x3 + + // DMA_CONF + // Position of IN_RST field. + SPI_DMA_CONF_IN_RST_Pos = 0x2 + // Bit mask of IN_RST field. + SPI_DMA_CONF_IN_RST_Msk = 0x4 + // Bit IN_RST. + SPI_DMA_CONF_IN_RST = 0x4 + // Position of OUT_RST field. + SPI_DMA_CONF_OUT_RST_Pos = 0x3 + // Bit mask of OUT_RST field. + SPI_DMA_CONF_OUT_RST_Msk = 0x8 + // Bit OUT_RST. + SPI_DMA_CONF_OUT_RST = 0x8 + // Position of AHBM_FIFO_RST field. + SPI_DMA_CONF_AHBM_FIFO_RST_Pos = 0x4 + // Bit mask of AHBM_FIFO_RST field. + SPI_DMA_CONF_AHBM_FIFO_RST_Msk = 0x10 + // Bit AHBM_FIFO_RST. + SPI_DMA_CONF_AHBM_FIFO_RST = 0x10 + // Position of AHBM_RST field. + SPI_DMA_CONF_AHBM_RST_Pos = 0x5 + // Bit mask of AHBM_RST field. + SPI_DMA_CONF_AHBM_RST_Msk = 0x20 + // Bit AHBM_RST. + SPI_DMA_CONF_AHBM_RST = 0x20 + // Position of IN_LOOP_TEST field. + SPI_DMA_CONF_IN_LOOP_TEST_Pos = 0x6 + // Bit mask of IN_LOOP_TEST field. + SPI_DMA_CONF_IN_LOOP_TEST_Msk = 0x40 + // Bit IN_LOOP_TEST. + SPI_DMA_CONF_IN_LOOP_TEST = 0x40 + // Position of OUT_LOOP_TEST field. + SPI_DMA_CONF_OUT_LOOP_TEST_Pos = 0x7 + // Bit mask of OUT_LOOP_TEST field. + SPI_DMA_CONF_OUT_LOOP_TEST_Msk = 0x80 + // Bit OUT_LOOP_TEST. + SPI_DMA_CONF_OUT_LOOP_TEST = 0x80 + // Position of OUT_AUTO_WRBACK field. + SPI_DMA_CONF_OUT_AUTO_WRBACK_Pos = 0x8 + // Bit mask of OUT_AUTO_WRBACK field. + SPI_DMA_CONF_OUT_AUTO_WRBACK_Msk = 0x100 + // Bit OUT_AUTO_WRBACK. + SPI_DMA_CONF_OUT_AUTO_WRBACK = 0x100 + // Position of OUT_EOF_MODE field. + SPI_DMA_CONF_OUT_EOF_MODE_Pos = 0x9 + // Bit mask of OUT_EOF_MODE field. + SPI_DMA_CONF_OUT_EOF_MODE_Msk = 0x200 + // Bit OUT_EOF_MODE. + SPI_DMA_CONF_OUT_EOF_MODE = 0x200 + // Position of OUTDSCR_BURST_EN field. + SPI_DMA_CONF_OUTDSCR_BURST_EN_Pos = 0xa + // Bit mask of OUTDSCR_BURST_EN field. + SPI_DMA_CONF_OUTDSCR_BURST_EN_Msk = 0x400 + // Bit OUTDSCR_BURST_EN. + SPI_DMA_CONF_OUTDSCR_BURST_EN = 0x400 + // Position of INDSCR_BURST_EN field. + SPI_DMA_CONF_INDSCR_BURST_EN_Pos = 0xb + // Bit mask of INDSCR_BURST_EN field. + SPI_DMA_CONF_INDSCR_BURST_EN_Msk = 0x800 + // Bit INDSCR_BURST_EN. + SPI_DMA_CONF_INDSCR_BURST_EN = 0x800 + // Position of OUT_DATA_BURST_EN field. + SPI_DMA_CONF_OUT_DATA_BURST_EN_Pos = 0xc + // Bit mask of OUT_DATA_BURST_EN field. + SPI_DMA_CONF_OUT_DATA_BURST_EN_Msk = 0x1000 + // Bit OUT_DATA_BURST_EN. + SPI_DMA_CONF_OUT_DATA_BURST_EN = 0x1000 + // Position of DMA_RX_STOP field. + SPI_DMA_CONF_DMA_RX_STOP_Pos = 0xe + // Bit mask of DMA_RX_STOP field. + SPI_DMA_CONF_DMA_RX_STOP_Msk = 0x4000 + // Bit DMA_RX_STOP. + SPI_DMA_CONF_DMA_RX_STOP = 0x4000 + // Position of DMA_TX_STOP field. + SPI_DMA_CONF_DMA_TX_STOP_Pos = 0xf + // Bit mask of DMA_TX_STOP field. + SPI_DMA_CONF_DMA_TX_STOP_Msk = 0x8000 + // Bit DMA_TX_STOP. + SPI_DMA_CONF_DMA_TX_STOP = 0x8000 + // Position of DMA_CONTINUE field. + SPI_DMA_CONF_DMA_CONTINUE_Pos = 0x10 + // Bit mask of DMA_CONTINUE field. + SPI_DMA_CONF_DMA_CONTINUE_Msk = 0x10000 + // Bit DMA_CONTINUE. + SPI_DMA_CONF_DMA_CONTINUE = 0x10000 + + // DMA_OUT_LINK + // Position of OUTLINK_ADDR field. + SPI_DMA_OUT_LINK_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + SPI_DMA_OUT_LINK_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + SPI_DMA_OUT_LINK_OUTLINK_STOP_Pos = 0x1c + // Bit mask of OUTLINK_STOP field. + SPI_DMA_OUT_LINK_OUTLINK_STOP_Msk = 0x10000000 + // Bit OUTLINK_STOP. + SPI_DMA_OUT_LINK_OUTLINK_STOP = 0x10000000 + // Position of OUTLINK_START field. + SPI_DMA_OUT_LINK_OUTLINK_START_Pos = 0x1d + // Bit mask of OUTLINK_START field. + SPI_DMA_OUT_LINK_OUTLINK_START_Msk = 0x20000000 + // Bit OUTLINK_START. + SPI_DMA_OUT_LINK_OUTLINK_START = 0x20000000 + // Position of OUTLINK_RESTART field. + SPI_DMA_OUT_LINK_OUTLINK_RESTART_Pos = 0x1e + // Bit mask of OUTLINK_RESTART field. + SPI_DMA_OUT_LINK_OUTLINK_RESTART_Msk = 0x40000000 + // Bit OUTLINK_RESTART. + SPI_DMA_OUT_LINK_OUTLINK_RESTART = 0x40000000 + + // DMA_IN_LINK + // Position of INLINK_ADDR field. + SPI_DMA_IN_LINK_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + SPI_DMA_IN_LINK_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + SPI_DMA_IN_LINK_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + SPI_DMA_IN_LINK_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + SPI_DMA_IN_LINK_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + SPI_DMA_IN_LINK_INLINK_STOP_Pos = 0x1c + // Bit mask of INLINK_STOP field. + SPI_DMA_IN_LINK_INLINK_STOP_Msk = 0x10000000 + // Bit INLINK_STOP. + SPI_DMA_IN_LINK_INLINK_STOP = 0x10000000 + // Position of INLINK_START field. + SPI_DMA_IN_LINK_INLINK_START_Pos = 0x1d + // Bit mask of INLINK_START field. + SPI_DMA_IN_LINK_INLINK_START_Msk = 0x20000000 + // Bit INLINK_START. + SPI_DMA_IN_LINK_INLINK_START = 0x20000000 + // Position of INLINK_RESTART field. + SPI_DMA_IN_LINK_INLINK_RESTART_Pos = 0x1e + // Bit mask of INLINK_RESTART field. + SPI_DMA_IN_LINK_INLINK_RESTART_Msk = 0x40000000 + // Bit INLINK_RESTART. + SPI_DMA_IN_LINK_INLINK_RESTART = 0x40000000 + + // DMA_STATUS + // Position of DMA_RX_EN field. + SPI_DMA_STATUS_DMA_RX_EN_Pos = 0x0 + // Bit mask of DMA_RX_EN field. + SPI_DMA_STATUS_DMA_RX_EN_Msk = 0x1 + // Bit DMA_RX_EN. + SPI_DMA_STATUS_DMA_RX_EN = 0x1 + // Position of DMA_TX_EN field. + SPI_DMA_STATUS_DMA_TX_EN_Pos = 0x1 + // Bit mask of DMA_TX_EN field. + SPI_DMA_STATUS_DMA_TX_EN_Msk = 0x2 + // Bit DMA_TX_EN. + SPI_DMA_STATUS_DMA_TX_EN = 0x2 + + // DMA_INT_ENA + // Position of INLINK_DSCR_EMPTY_INT_ENA field. + SPI_DMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA_Pos = 0x0 + // Bit mask of INLINK_DSCR_EMPTY_INT_ENA field. + SPI_DMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA_Msk = 0x1 + // Bit INLINK_DSCR_EMPTY_INT_ENA. + SPI_DMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA = 0x1 + // Position of OUTLINK_DSCR_ERROR_INT_ENA field. + SPI_DMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA_Pos = 0x1 + // Bit mask of OUTLINK_DSCR_ERROR_INT_ENA field. + SPI_DMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA_Msk = 0x2 + // Bit OUTLINK_DSCR_ERROR_INT_ENA. + SPI_DMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA = 0x2 + // Position of INLINK_DSCR_ERROR_INT_ENA field. + SPI_DMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA_Pos = 0x2 + // Bit mask of INLINK_DSCR_ERROR_INT_ENA field. + SPI_DMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA_Msk = 0x4 + // Bit INLINK_DSCR_ERROR_INT_ENA. + SPI_DMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA = 0x4 + // Position of IN_DONE_INT_ENA field. + SPI_DMA_INT_ENA_IN_DONE_INT_ENA_Pos = 0x3 + // Bit mask of IN_DONE_INT_ENA field. + SPI_DMA_INT_ENA_IN_DONE_INT_ENA_Msk = 0x8 + // Bit IN_DONE_INT_ENA. + SPI_DMA_INT_ENA_IN_DONE_INT_ENA = 0x8 + // Position of IN_ERR_EOF_INT_ENA field. + SPI_DMA_INT_ENA_IN_ERR_EOF_INT_ENA_Pos = 0x4 + // Bit mask of IN_ERR_EOF_INT_ENA field. + SPI_DMA_INT_ENA_IN_ERR_EOF_INT_ENA_Msk = 0x10 + // Bit IN_ERR_EOF_INT_ENA. + SPI_DMA_INT_ENA_IN_ERR_EOF_INT_ENA = 0x10 + // Position of IN_SUC_EOF_INT_ENA field. + SPI_DMA_INT_ENA_IN_SUC_EOF_INT_ENA_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_ENA field. + SPI_DMA_INT_ENA_IN_SUC_EOF_INT_ENA_Msk = 0x20 + // Bit IN_SUC_EOF_INT_ENA. + SPI_DMA_INT_ENA_IN_SUC_EOF_INT_ENA = 0x20 + // Position of OUT_DONE_INT_ENA field. + SPI_DMA_INT_ENA_OUT_DONE_INT_ENA_Pos = 0x6 + // Bit mask of OUT_DONE_INT_ENA field. + SPI_DMA_INT_ENA_OUT_DONE_INT_ENA_Msk = 0x40 + // Bit OUT_DONE_INT_ENA. + SPI_DMA_INT_ENA_OUT_DONE_INT_ENA = 0x40 + // Position of OUT_EOF_INT_ENA field. + SPI_DMA_INT_ENA_OUT_EOF_INT_ENA_Pos = 0x7 + // Bit mask of OUT_EOF_INT_ENA field. + SPI_DMA_INT_ENA_OUT_EOF_INT_ENA_Msk = 0x80 + // Bit OUT_EOF_INT_ENA. + SPI_DMA_INT_ENA_OUT_EOF_INT_ENA = 0x80 + // Position of OUT_TOTAL_EOF_INT_ENA field. + SPI_DMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF_INT_ENA field. + SPI_DMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Msk = 0x100 + // Bit OUT_TOTAL_EOF_INT_ENA. + SPI_DMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA = 0x100 + + // DMA_INT_RAW + // Position of INLINK_DSCR_EMPTY_INT_RAW field. + SPI_DMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW_Pos = 0x0 + // Bit mask of INLINK_DSCR_EMPTY_INT_RAW field. + SPI_DMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW_Msk = 0x1 + // Bit INLINK_DSCR_EMPTY_INT_RAW. + SPI_DMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW = 0x1 + // Position of OUTLINK_DSCR_ERROR_INT_RAW field. + SPI_DMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW_Pos = 0x1 + // Bit mask of OUTLINK_DSCR_ERROR_INT_RAW field. + SPI_DMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW_Msk = 0x2 + // Bit OUTLINK_DSCR_ERROR_INT_RAW. + SPI_DMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW = 0x2 + // Position of INLINK_DSCR_ERROR_INT_RAW field. + SPI_DMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW_Pos = 0x2 + // Bit mask of INLINK_DSCR_ERROR_INT_RAW field. + SPI_DMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW_Msk = 0x4 + // Bit INLINK_DSCR_ERROR_INT_RAW. + SPI_DMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW = 0x4 + // Position of IN_DONE_INT_RAW field. + SPI_DMA_INT_RAW_IN_DONE_INT_RAW_Pos = 0x3 + // Bit mask of IN_DONE_INT_RAW field. + SPI_DMA_INT_RAW_IN_DONE_INT_RAW_Msk = 0x8 + // Bit IN_DONE_INT_RAW. + SPI_DMA_INT_RAW_IN_DONE_INT_RAW = 0x8 + // Position of IN_ERR_EOF_INT_RAW field. + SPI_DMA_INT_RAW_IN_ERR_EOF_INT_RAW_Pos = 0x4 + // Bit mask of IN_ERR_EOF_INT_RAW field. + SPI_DMA_INT_RAW_IN_ERR_EOF_INT_RAW_Msk = 0x10 + // Bit IN_ERR_EOF_INT_RAW. + SPI_DMA_INT_RAW_IN_ERR_EOF_INT_RAW = 0x10 + // Position of IN_SUC_EOF_INT_RAW field. + SPI_DMA_INT_RAW_IN_SUC_EOF_INT_RAW_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_RAW field. + SPI_DMA_INT_RAW_IN_SUC_EOF_INT_RAW_Msk = 0x20 + // Bit IN_SUC_EOF_INT_RAW. + SPI_DMA_INT_RAW_IN_SUC_EOF_INT_RAW = 0x20 + // Position of OUT_DONE_INT_RAW field. + SPI_DMA_INT_RAW_OUT_DONE_INT_RAW_Pos = 0x6 + // Bit mask of OUT_DONE_INT_RAW field. + SPI_DMA_INT_RAW_OUT_DONE_INT_RAW_Msk = 0x40 + // Bit OUT_DONE_INT_RAW. + SPI_DMA_INT_RAW_OUT_DONE_INT_RAW = 0x40 + // Position of OUT_EOF_INT_RAW field. + SPI_DMA_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x7 + // Bit mask of OUT_EOF_INT_RAW field. + SPI_DMA_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x80 + // Bit OUT_EOF_INT_RAW. + SPI_DMA_INT_RAW_OUT_EOF_INT_RAW = 0x80 + // Position of OUT_TOTAL_EOF_INT_RAW field. + SPI_DMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF_INT_RAW field. + SPI_DMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Msk = 0x100 + // Bit OUT_TOTAL_EOF_INT_RAW. + SPI_DMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW = 0x100 + + // DMA_INT_ST + // Position of INLINK_DSCR_EMPTY_INT_ST field. + SPI_DMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST_Pos = 0x0 + // Bit mask of INLINK_DSCR_EMPTY_INT_ST field. + SPI_DMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST_Msk = 0x1 + // Bit INLINK_DSCR_EMPTY_INT_ST. + SPI_DMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST = 0x1 + // Position of OUTLINK_DSCR_ERROR_INT_ST field. + SPI_DMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST_Pos = 0x1 + // Bit mask of OUTLINK_DSCR_ERROR_INT_ST field. + SPI_DMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST_Msk = 0x2 + // Bit OUTLINK_DSCR_ERROR_INT_ST. + SPI_DMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST = 0x2 + // Position of INLINK_DSCR_ERROR_INT_ST field. + SPI_DMA_INT_ST_INLINK_DSCR_ERROR_INT_ST_Pos = 0x2 + // Bit mask of INLINK_DSCR_ERROR_INT_ST field. + SPI_DMA_INT_ST_INLINK_DSCR_ERROR_INT_ST_Msk = 0x4 + // Bit INLINK_DSCR_ERROR_INT_ST. + SPI_DMA_INT_ST_INLINK_DSCR_ERROR_INT_ST = 0x4 + // Position of IN_DONE_INT_ST field. + SPI_DMA_INT_ST_IN_DONE_INT_ST_Pos = 0x3 + // Bit mask of IN_DONE_INT_ST field. + SPI_DMA_INT_ST_IN_DONE_INT_ST_Msk = 0x8 + // Bit IN_DONE_INT_ST. + SPI_DMA_INT_ST_IN_DONE_INT_ST = 0x8 + // Position of IN_ERR_EOF_INT_ST field. + SPI_DMA_INT_ST_IN_ERR_EOF_INT_ST_Pos = 0x4 + // Bit mask of IN_ERR_EOF_INT_ST field. + SPI_DMA_INT_ST_IN_ERR_EOF_INT_ST_Msk = 0x10 + // Bit IN_ERR_EOF_INT_ST. + SPI_DMA_INT_ST_IN_ERR_EOF_INT_ST = 0x10 + // Position of IN_SUC_EOF_INT_ST field. + SPI_DMA_INT_ST_IN_SUC_EOF_INT_ST_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_ST field. + SPI_DMA_INT_ST_IN_SUC_EOF_INT_ST_Msk = 0x20 + // Bit IN_SUC_EOF_INT_ST. + SPI_DMA_INT_ST_IN_SUC_EOF_INT_ST = 0x20 + // Position of OUT_DONE_INT_ST field. + SPI_DMA_INT_ST_OUT_DONE_INT_ST_Pos = 0x6 + // Bit mask of OUT_DONE_INT_ST field. + SPI_DMA_INT_ST_OUT_DONE_INT_ST_Msk = 0x40 + // Bit OUT_DONE_INT_ST. + SPI_DMA_INT_ST_OUT_DONE_INT_ST = 0x40 + // Position of OUT_EOF_INT_ST field. + SPI_DMA_INT_ST_OUT_EOF_INT_ST_Pos = 0x7 + // Bit mask of OUT_EOF_INT_ST field. + SPI_DMA_INT_ST_OUT_EOF_INT_ST_Msk = 0x80 + // Bit OUT_EOF_INT_ST. + SPI_DMA_INT_ST_OUT_EOF_INT_ST = 0x80 + // Position of OUT_TOTAL_EOF_INT_ST field. + SPI_DMA_INT_ST_OUT_TOTAL_EOF_INT_ST_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF_INT_ST field. + SPI_DMA_INT_ST_OUT_TOTAL_EOF_INT_ST_Msk = 0x100 + // Bit OUT_TOTAL_EOF_INT_ST. + SPI_DMA_INT_ST_OUT_TOTAL_EOF_INT_ST = 0x100 + + // DMA_INT_CLR + // Position of INLINK_DSCR_EMPTY_INT_CLR field. + SPI_DMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR_Pos = 0x0 + // Bit mask of INLINK_DSCR_EMPTY_INT_CLR field. + SPI_DMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR_Msk = 0x1 + // Bit INLINK_DSCR_EMPTY_INT_CLR. + SPI_DMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR = 0x1 + // Position of OUTLINK_DSCR_ERROR_INT_CLR field. + SPI_DMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR_Pos = 0x1 + // Bit mask of OUTLINK_DSCR_ERROR_INT_CLR field. + SPI_DMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR_Msk = 0x2 + // Bit OUTLINK_DSCR_ERROR_INT_CLR. + SPI_DMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR = 0x2 + // Position of INLINK_DSCR_ERROR_INT_CLR field. + SPI_DMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR_Pos = 0x2 + // Bit mask of INLINK_DSCR_ERROR_INT_CLR field. + SPI_DMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR_Msk = 0x4 + // Bit INLINK_DSCR_ERROR_INT_CLR. + SPI_DMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR = 0x4 + // Position of IN_DONE_INT_CLR field. + SPI_DMA_INT_CLR_IN_DONE_INT_CLR_Pos = 0x3 + // Bit mask of IN_DONE_INT_CLR field. + SPI_DMA_INT_CLR_IN_DONE_INT_CLR_Msk = 0x8 + // Bit IN_DONE_INT_CLR. + SPI_DMA_INT_CLR_IN_DONE_INT_CLR = 0x8 + // Position of IN_ERR_EOF_INT_CLR field. + SPI_DMA_INT_CLR_IN_ERR_EOF_INT_CLR_Pos = 0x4 + // Bit mask of IN_ERR_EOF_INT_CLR field. + SPI_DMA_INT_CLR_IN_ERR_EOF_INT_CLR_Msk = 0x10 + // Bit IN_ERR_EOF_INT_CLR. + SPI_DMA_INT_CLR_IN_ERR_EOF_INT_CLR = 0x10 + // Position of IN_SUC_EOF_INT_CLR field. + SPI_DMA_INT_CLR_IN_SUC_EOF_INT_CLR_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_CLR field. + SPI_DMA_INT_CLR_IN_SUC_EOF_INT_CLR_Msk = 0x20 + // Bit IN_SUC_EOF_INT_CLR. + SPI_DMA_INT_CLR_IN_SUC_EOF_INT_CLR = 0x20 + // Position of OUT_DONE_INT_CLR field. + SPI_DMA_INT_CLR_OUT_DONE_INT_CLR_Pos = 0x6 + // Bit mask of OUT_DONE_INT_CLR field. + SPI_DMA_INT_CLR_OUT_DONE_INT_CLR_Msk = 0x40 + // Bit OUT_DONE_INT_CLR. + SPI_DMA_INT_CLR_OUT_DONE_INT_CLR = 0x40 + // Position of OUT_EOF_INT_CLR field. + SPI_DMA_INT_CLR_OUT_EOF_INT_CLR_Pos = 0x7 + // Bit mask of OUT_EOF_INT_CLR field. + SPI_DMA_INT_CLR_OUT_EOF_INT_CLR_Msk = 0x80 + // Bit OUT_EOF_INT_CLR. + SPI_DMA_INT_CLR_OUT_EOF_INT_CLR = 0x80 + // Position of OUT_TOTAL_EOF_INT_CLR field. + SPI_DMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF_INT_CLR field. + SPI_DMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Msk = 0x100 + // Bit OUT_TOTAL_EOF_INT_CLR. + SPI_DMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR = 0x100 + + // IN_ERR_EOF_DES_ADDR + // Position of DMA_IN_ERR_EOF_DES_ADDR field. + SPI_IN_ERR_EOF_DES_ADDR_DMA_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of DMA_IN_ERR_EOF_DES_ADDR field. + SPI_IN_ERR_EOF_DES_ADDR_DMA_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_SUC_EOF_DES_ADDR + // Position of DMA_IN_SUC_EOF_DES_ADDR field. + SPI_IN_SUC_EOF_DES_ADDR_DMA_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of DMA_IN_SUC_EOF_DES_ADDR field. + SPI_IN_SUC_EOF_DES_ADDR_DMA_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // INLINK_DSCR + // Position of DMA_INLINK_DSCR field. + SPI_INLINK_DSCR_DMA_INLINK_DSCR_Pos = 0x0 + // Bit mask of DMA_INLINK_DSCR field. + SPI_INLINK_DSCR_DMA_INLINK_DSCR_Msk = 0xffffffff + + // INLINK_DSCR_BF0 + // Position of DMA_INLINK_DSCR_BF0 field. + SPI_INLINK_DSCR_BF0_DMA_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of DMA_INLINK_DSCR_BF0 field. + SPI_INLINK_DSCR_BF0_DMA_INLINK_DSCR_BF0_Msk = 0xffffffff + + // INLINK_DSCR_BF1 + // Position of DMA_INLINK_DSCR_BF1 field. + SPI_INLINK_DSCR_BF1_DMA_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of DMA_INLINK_DSCR_BF1 field. + SPI_INLINK_DSCR_BF1_DMA_INLINK_DSCR_BF1_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR + // Position of DMA_OUT_EOF_BFR_DES_ADDR field. + SPI_OUT_EOF_BFR_DES_ADDR_DMA_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of DMA_OUT_EOF_BFR_DES_ADDR field. + SPI_OUT_EOF_BFR_DES_ADDR_DMA_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_DES_ADDR + // Position of DMA_OUT_EOF_DES_ADDR field. + SPI_OUT_EOF_DES_ADDR_DMA_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of DMA_OUT_EOF_DES_ADDR field. + SPI_OUT_EOF_DES_ADDR_DMA_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // OUTLINK_DSCR + // Position of DMA_OUTLINK_DSCR field. + SPI_OUTLINK_DSCR_DMA_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of DMA_OUTLINK_DSCR field. + SPI_OUTLINK_DSCR_DMA_OUTLINK_DSCR_Msk = 0xffffffff + + // OUTLINK_DSCR_BF0 + // Position of DMA_OUTLINK_DSCR_BF0 field. + SPI_OUTLINK_DSCR_BF0_DMA_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of DMA_OUTLINK_DSCR_BF0 field. + SPI_OUTLINK_DSCR_BF0_DMA_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUTLINK_DSCR_BF1 + // Position of DMA_OUTLINK_DSCR_BF1 field. + SPI_OUTLINK_DSCR_BF1_DMA_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of DMA_OUTLINK_DSCR_BF1 field. + SPI_OUTLINK_DSCR_BF1_DMA_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // DMA_RSTATUS + // Position of DMA_OUT_STATUS field. + SPI_DMA_RSTATUS_DMA_OUT_STATUS_Pos = 0x0 + // Bit mask of DMA_OUT_STATUS field. + SPI_DMA_RSTATUS_DMA_OUT_STATUS_Msk = 0xffffffff + + // DMA_TSTATUS + // Position of DMA_IN_STATUS field. + SPI_DMA_TSTATUS_DMA_IN_STATUS_Pos = 0x0 + // Bit mask of DMA_IN_STATUS field. + SPI_DMA_TSTATUS_DMA_IN_STATUS_Msk = 0xffffffff + + // DATE + // Position of DATE field. + SPI_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI_DATE_DATE_Msk = 0xfffffff +) + +// Constants for TIMG0: Timer Group 0 +const ( + // T0CONFIG + // Position of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Pos = 0xa + // Bit mask of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Msk = 0x400 + // Bit ALARM_EN. + TIMG_T0CONFIG_ALARM_EN = 0x400 + // Position of LEVEL_INT_EN field. + TIMG_T0CONFIG_LEVEL_INT_EN_Pos = 0xb + // Bit mask of LEVEL_INT_EN field. + TIMG_T0CONFIG_LEVEL_INT_EN_Msk = 0x800 + // Bit LEVEL_INT_EN. + TIMG_T0CONFIG_LEVEL_INT_EN = 0x800 + // Position of EDGE_INT_EN field. + TIMG_T0CONFIG_EDGE_INT_EN_Pos = 0xc + // Bit mask of EDGE_INT_EN field. + TIMG_T0CONFIG_EDGE_INT_EN_Msk = 0x1000 + // Bit EDGE_INT_EN. + TIMG_T0CONFIG_EDGE_INT_EN = 0x1000 + // Position of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Pos = 0xd + // Bit mask of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Msk = 0x1fffe000 + // Position of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Pos = 0x1d + // Bit mask of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Msk = 0x20000000 + // Bit AUTORELOAD. + TIMG_T0CONFIG_AUTORELOAD = 0x20000000 + // Position of INCREASE field. + TIMG_T0CONFIG_INCREASE_Pos = 0x1e + // Bit mask of INCREASE field. + TIMG_T0CONFIG_INCREASE_Msk = 0x40000000 + // Bit INCREASE. + TIMG_T0CONFIG_INCREASE = 0x40000000 + // Position of EN field. + TIMG_T0CONFIG_EN_Pos = 0x1f + // Bit mask of EN field. + TIMG_T0CONFIG_EN_Msk = 0x80000000 + // Bit EN. + TIMG_T0CONFIG_EN = 0x80000000 + + // T0LO + // Position of LO field. + TIMG_T0LO_LO_Pos = 0x0 + // Bit mask of LO field. + TIMG_T0LO_LO_Msk = 0xffffffff + + // T0HI + // Position of HI field. + TIMG_T0HI_HI_Pos = 0x0 + // Bit mask of HI field. + TIMG_T0HI_HI_Msk = 0xffffffff + + // T0UPDATE + // Position of UPDATE field. + TIMG_T0UPDATE_UPDATE_Pos = 0x0 + // Bit mask of UPDATE field. + TIMG_T0UPDATE_UPDATE_Msk = 0xffffffff + + // T0ALARMLO + // Position of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Pos = 0x0 + // Bit mask of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Msk = 0xffffffff + + // T0ALARMHI + // Position of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Pos = 0x0 + // Bit mask of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Msk = 0xffffffff + + // T0LOADLO + // Position of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Pos = 0x0 + // Bit mask of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Msk = 0xffffffff + + // T0LOADHI + // Position of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Pos = 0x0 + // Bit mask of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Msk = 0xffffffff + + // T0LOAD + // Position of LOAD field. + TIMG_T0LOAD_LOAD_Pos = 0x0 + // Bit mask of LOAD field. + TIMG_T0LOAD_LOAD_Msk = 0xffffffff + + // T1CONFIG + // Position of ALARM_EN field. + TIMG_T1CONFIG_ALARM_EN_Pos = 0xa + // Bit mask of ALARM_EN field. + TIMG_T1CONFIG_ALARM_EN_Msk = 0x400 + // Bit ALARM_EN. + TIMG_T1CONFIG_ALARM_EN = 0x400 + // Position of LEVEL_INT_EN field. + TIMG_T1CONFIG_LEVEL_INT_EN_Pos = 0xb + // Bit mask of LEVEL_INT_EN field. + TIMG_T1CONFIG_LEVEL_INT_EN_Msk = 0x800 + // Bit LEVEL_INT_EN. + TIMG_T1CONFIG_LEVEL_INT_EN = 0x800 + // Position of EDGE_INT_EN field. + TIMG_T1CONFIG_EDGE_INT_EN_Pos = 0xc + // Bit mask of EDGE_INT_EN field. + TIMG_T1CONFIG_EDGE_INT_EN_Msk = 0x1000 + // Bit EDGE_INT_EN. + TIMG_T1CONFIG_EDGE_INT_EN = 0x1000 + // Position of DIVIDER field. + TIMG_T1CONFIG_DIVIDER_Pos = 0xd + // Bit mask of DIVIDER field. + TIMG_T1CONFIG_DIVIDER_Msk = 0x1fffe000 + // Position of AUTORELOAD field. + TIMG_T1CONFIG_AUTORELOAD_Pos = 0x1d + // Bit mask of AUTORELOAD field. + TIMG_T1CONFIG_AUTORELOAD_Msk = 0x20000000 + // Bit AUTORELOAD. + TIMG_T1CONFIG_AUTORELOAD = 0x20000000 + // Position of INCREASE field. + TIMG_T1CONFIG_INCREASE_Pos = 0x1e + // Bit mask of INCREASE field. + TIMG_T1CONFIG_INCREASE_Msk = 0x40000000 + // Bit INCREASE. + TIMG_T1CONFIG_INCREASE = 0x40000000 + // Position of EN field. + TIMG_T1CONFIG_EN_Pos = 0x1f + // Bit mask of EN field. + TIMG_T1CONFIG_EN_Msk = 0x80000000 + // Bit EN. + TIMG_T1CONFIG_EN = 0x80000000 + + // T1LO + // Position of LO field. + TIMG_T1LO_LO_Pos = 0x0 + // Bit mask of LO field. + TIMG_T1LO_LO_Msk = 0xffffffff + + // T1HI + // Position of HI field. + TIMG_T1HI_HI_Pos = 0x0 + // Bit mask of HI field. + TIMG_T1HI_HI_Msk = 0xffffffff + + // T1UPDATE + // Position of UPDATE field. + TIMG_T1UPDATE_UPDATE_Pos = 0x0 + // Bit mask of UPDATE field. + TIMG_T1UPDATE_UPDATE_Msk = 0xffffffff + + // T1ALARMLO + // Position of ALARM_LO field. + TIMG_T1ALARMLO_ALARM_LO_Pos = 0x0 + // Bit mask of ALARM_LO field. + TIMG_T1ALARMLO_ALARM_LO_Msk = 0xffffffff + + // T1ALARMHI + // Position of ALARM_HI field. + TIMG_T1ALARMHI_ALARM_HI_Pos = 0x0 + // Bit mask of ALARM_HI field. + TIMG_T1ALARMHI_ALARM_HI_Msk = 0xffffffff + + // T1LOADLO + // Position of LOAD_LO field. + TIMG_T1LOADLO_LOAD_LO_Pos = 0x0 + // Bit mask of LOAD_LO field. + TIMG_T1LOADLO_LOAD_LO_Msk = 0xffffffff + + // T1LOADHI + // Position of LOAD_HI field. + TIMG_T1LOADHI_LOAD_HI_Pos = 0x0 + // Bit mask of LOAD_HI field. + TIMG_T1LOADHI_LOAD_HI_Msk = 0xffffffff + + // T1LOAD + // Position of LOAD field. + TIMG_T1LOAD_LOAD_Pos = 0x0 + // Bit mask of LOAD field. + TIMG_T1LOAD_LOAD_Msk = 0xffffffff + + // WDTCONFIG0 + // Position of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xe + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x4000 + // Bit WDT_FLASHBOOT_MOD_EN. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x4000 + // Position of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xf + // Bit mask of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0x38000 + // 100ns + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_NS100 = 0x0 + // 200ns + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_NS200 = 0x1 + // 300ns + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_NS300 = 0x2 + // 400ns + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_NS400 = 0x3 + // 500ns + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_NS500 = 0x4 + // 800ns + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_NS800 = 0x5 + // 1.6us + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_NS1600 = 0x6 + // 3.2us + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_NS3200 = 0x7 + // Position of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x12 + // Bit mask of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x1c0000 + // 100ns + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_NS100 = 0x0 + // 200ns + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_NS200 = 0x1 + // 300ns + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_NS300 = 0x2 + // 400ns + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_NS400 = 0x3 + // 500ns + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_NS500 = 0x4 + // 800ns + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_NS800 = 0x5 + // 1.6us + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_NS1600 = 0x6 + // 3.2us + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_NS3200 = 0x7 + // Position of WDT_LEVEL_INT_EN field. + TIMG_WDTCONFIG0_WDT_LEVEL_INT_EN_Pos = 0x15 + // Bit mask of WDT_LEVEL_INT_EN field. + TIMG_WDTCONFIG0_WDT_LEVEL_INT_EN_Msk = 0x200000 + // Bit WDT_LEVEL_INT_EN. + TIMG_WDTCONFIG0_WDT_LEVEL_INT_EN = 0x200000 + // Position of WDT_EDGE_INT_EN field. + TIMG_WDTCONFIG0_WDT_EDGE_INT_EN_Pos = 0x16 + // Bit mask of WDT_EDGE_INT_EN field. + TIMG_WDTCONFIG0_WDT_EDGE_INT_EN_Msk = 0x400000 + // Bit WDT_EDGE_INT_EN. + TIMG_WDTCONFIG0_WDT_EDGE_INT_EN = 0x400000 + // Position of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Pos = 0x17 + // Bit mask of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Msk = 0x1800000 + // Off + TIMG_WDTCONFIG0_WDT_STG3_OFF = 0x0 + // Interrupt + TIMG_WDTCONFIG0_WDT_STG3_INTERRUPT = 0x1 + // Reset CPU + TIMG_WDTCONFIG0_WDT_STG3_RESET = 0x2 + // Reset system + TIMG_WDTCONFIG0_WDT_STG3_RESET_SYS = 0x3 + // Position of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Pos = 0x19 + // Bit mask of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Msk = 0x6000000 + // Off + TIMG_WDTCONFIG0_WDT_STG2_OFF = 0x0 + // Interrupt + TIMG_WDTCONFIG0_WDT_STG2_INTERRUPT = 0x1 + // Reset CPU + TIMG_WDTCONFIG0_WDT_STG2_RESET = 0x2 + // Reset system + TIMG_WDTCONFIG0_WDT_STG2_RESET_SYS = 0x3 + // Position of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Pos = 0x1b + // Bit mask of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Msk = 0x18000000 + // Off + TIMG_WDTCONFIG0_WDT_STG1_OFF = 0x0 + // Interrupt + TIMG_WDTCONFIG0_WDT_STG1_INTERRUPT = 0x1 + // Reset CPU + TIMG_WDTCONFIG0_WDT_STG1_RESET = 0x2 + // Reset system + TIMG_WDTCONFIG0_WDT_STG1_RESET_SYS = 0x3 + // Position of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Pos = 0x1d + // Bit mask of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Msk = 0x60000000 + // Off + TIMG_WDTCONFIG0_WDT_STG0_OFF = 0x0 + // Interrupt + TIMG_WDTCONFIG0_WDT_STG0_INTERRUPT = 0x1 + // Reset CPU + TIMG_WDTCONFIG0_WDT_STG0_RESET = 0x2 + // Reset system + TIMG_WDTCONFIG0_WDT_STG0_RESET_SYS = 0x3 + // Position of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + TIMG_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1 + // Position of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Pos = 0x10 + // Bit mask of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Msk = 0xffff0000 + + // WDTCONFIG2 + // Position of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG3 + // Position of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG4 + // Position of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG5 + // Position of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED + // Position of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Pos = 0x0 + // Bit mask of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Msk = 0xffffffff + + // WDTWPROTECT + // Position of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // RTCCALICFG + // Position of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Pos = 0xc + // Bit mask of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Msk = 0x1000 + // Bit RTC_CALI_START_CYCLING. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING = 0x1000 + // Position of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Pos = 0xd + // Bit mask of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Msk = 0x6000 + // Position of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Pos = 0xf + // Bit mask of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Msk = 0x8000 + // Bit RTC_CALI_RDY. + TIMG_RTCCALICFG_RTC_CALI_RDY = 0x8000 + // Position of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Pos = 0x10 + // Bit mask of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Msk = 0x7fff0000 + // Position of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Pos = 0x1f + // Bit mask of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Msk = 0x80000000 + // Bit RTC_CALI_START. + TIMG_RTCCALICFG_RTC_CALI_START = 0x80000000 + + // RTCCALICFG1 + // Position of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Pos = 0x7 + // Bit mask of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Msk = 0xffffff80 + + // LACTCONFIG + // Position of LACT_RTC_ONLY field. + TIMG_LACTCONFIG_LACT_RTC_ONLY_Pos = 0x7 + // Bit mask of LACT_RTC_ONLY field. + TIMG_LACTCONFIG_LACT_RTC_ONLY_Msk = 0x80 + // Bit LACT_RTC_ONLY. + TIMG_LACTCONFIG_LACT_RTC_ONLY = 0x80 + // Position of LACT_CPST_EN field. + TIMG_LACTCONFIG_LACT_CPST_EN_Pos = 0x8 + // Bit mask of LACT_CPST_EN field. + TIMG_LACTCONFIG_LACT_CPST_EN_Msk = 0x100 + // Bit LACT_CPST_EN. + TIMG_LACTCONFIG_LACT_CPST_EN = 0x100 + // Position of LACT_LAC_EN field. + TIMG_LACTCONFIG_LACT_LAC_EN_Pos = 0x9 + // Bit mask of LACT_LAC_EN field. + TIMG_LACTCONFIG_LACT_LAC_EN_Msk = 0x200 + // Bit LACT_LAC_EN. + TIMG_LACTCONFIG_LACT_LAC_EN = 0x200 + // Position of LACT_ALARM_EN field. + TIMG_LACTCONFIG_LACT_ALARM_EN_Pos = 0xa + // Bit mask of LACT_ALARM_EN field. + TIMG_LACTCONFIG_LACT_ALARM_EN_Msk = 0x400 + // Bit LACT_ALARM_EN. + TIMG_LACTCONFIG_LACT_ALARM_EN = 0x400 + // Position of LACT_LEVEL_INT_EN field. + TIMG_LACTCONFIG_LACT_LEVEL_INT_EN_Pos = 0xb + // Bit mask of LACT_LEVEL_INT_EN field. + TIMG_LACTCONFIG_LACT_LEVEL_INT_EN_Msk = 0x800 + // Bit LACT_LEVEL_INT_EN. + TIMG_LACTCONFIG_LACT_LEVEL_INT_EN = 0x800 + // Position of LACT_EDGE_INT_EN field. + TIMG_LACTCONFIG_LACT_EDGE_INT_EN_Pos = 0xc + // Bit mask of LACT_EDGE_INT_EN field. + TIMG_LACTCONFIG_LACT_EDGE_INT_EN_Msk = 0x1000 + // Bit LACT_EDGE_INT_EN. + TIMG_LACTCONFIG_LACT_EDGE_INT_EN = 0x1000 + // Position of LACT_DIVIDER field. + TIMG_LACTCONFIG_LACT_DIVIDER_Pos = 0xd + // Bit mask of LACT_DIVIDER field. + TIMG_LACTCONFIG_LACT_DIVIDER_Msk = 0x1fffe000 + // Position of LACT_AUTORELOAD field. + TIMG_LACTCONFIG_LACT_AUTORELOAD_Pos = 0x1d + // Bit mask of LACT_AUTORELOAD field. + TIMG_LACTCONFIG_LACT_AUTORELOAD_Msk = 0x20000000 + // Bit LACT_AUTORELOAD. + TIMG_LACTCONFIG_LACT_AUTORELOAD = 0x20000000 + // Position of LACT_INCREASE field. + TIMG_LACTCONFIG_LACT_INCREASE_Pos = 0x1e + // Bit mask of LACT_INCREASE field. + TIMG_LACTCONFIG_LACT_INCREASE_Msk = 0x40000000 + // Bit LACT_INCREASE. + TIMG_LACTCONFIG_LACT_INCREASE = 0x40000000 + // Position of LACT_EN field. + TIMG_LACTCONFIG_LACT_EN_Pos = 0x1f + // Bit mask of LACT_EN field. + TIMG_LACTCONFIG_LACT_EN_Msk = 0x80000000 + // Bit LACT_EN. + TIMG_LACTCONFIG_LACT_EN = 0x80000000 + + // LACTRTC + // Position of LACT_RTC_STEP_LEN field. + TIMG_LACTRTC_LACT_RTC_STEP_LEN_Pos = 0x6 + // Bit mask of LACT_RTC_STEP_LEN field. + TIMG_LACTRTC_LACT_RTC_STEP_LEN_Msk = 0xffffffc0 + + // LACTLO + // Position of LACT_LO field. + TIMG_LACTLO_LACT_LO_Pos = 0x0 + // Bit mask of LACT_LO field. + TIMG_LACTLO_LACT_LO_Msk = 0xffffffff + + // LACTHI + // Position of LACT_HI field. + TIMG_LACTHI_LACT_HI_Pos = 0x0 + // Bit mask of LACT_HI field. + TIMG_LACTHI_LACT_HI_Msk = 0xffffffff + + // LACTUPDATE + // Position of LACT_UPDATE field. + TIMG_LACTUPDATE_LACT_UPDATE_Pos = 0x0 + // Bit mask of LACT_UPDATE field. + TIMG_LACTUPDATE_LACT_UPDATE_Msk = 0xffffffff + + // LACTALARMLO + // Position of LACT_ALARM_LO field. + TIMG_LACTALARMLO_LACT_ALARM_LO_Pos = 0x0 + // Bit mask of LACT_ALARM_LO field. + TIMG_LACTALARMLO_LACT_ALARM_LO_Msk = 0xffffffff + + // LACTALARMHI + // Position of LACT_ALARM_HI field. + TIMG_LACTALARMHI_LACT_ALARM_HI_Pos = 0x0 + // Bit mask of LACT_ALARM_HI field. + TIMG_LACTALARMHI_LACT_ALARM_HI_Msk = 0xffffffff + + // LACTLOADLO + // Position of LACT_LOAD_LO field. + TIMG_LACTLOADLO_LACT_LOAD_LO_Pos = 0x0 + // Bit mask of LACT_LOAD_LO field. + TIMG_LACTLOADLO_LACT_LOAD_LO_Msk = 0xffffffff + + // LACTLOADHI + // Position of LACT_LOAD_HI field. + TIMG_LACTLOADHI_LACT_LOAD_HI_Pos = 0x0 + // Bit mask of LACT_LOAD_HI field. + TIMG_LACTLOADHI_LACT_LOAD_HI_Msk = 0xffffffff + + // LACTLOAD + // Position of LACT_LOAD field. + TIMG_LACTLOAD_LACT_LOAD_Pos = 0x0 + // Bit mask of LACT_LOAD field. + TIMG_LACTLOAD_LACT_LOAD_Msk = 0xffffffff + + // INT_ENA_TIMERS + // Position of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Pos = 0x0 + // Bit mask of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Msk = 0x1 + // Bit T0_INT_ENA. + TIMG_INT_ENA_TIMERS_T0_INT_ENA = 0x1 + // Position of T1_INT_ENA field. + TIMG_INT_ENA_TIMERS_T1_INT_ENA_Pos = 0x1 + // Bit mask of T1_INT_ENA field. + TIMG_INT_ENA_TIMERS_T1_INT_ENA_Msk = 0x2 + // Bit T1_INT_ENA. + TIMG_INT_ENA_TIMERS_T1_INT_ENA = 0x2 + // Position of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Pos = 0x2 + // Bit mask of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Msk = 0x4 + // Bit WDT_INT_ENA. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA = 0x4 + // Position of LACT_INT_ENA field. + TIMG_INT_ENA_TIMERS_LACT_INT_ENA_Pos = 0x3 + // Bit mask of LACT_INT_ENA field. + TIMG_INT_ENA_TIMERS_LACT_INT_ENA_Msk = 0x8 + // Bit LACT_INT_ENA. + TIMG_INT_ENA_TIMERS_LACT_INT_ENA = 0x8 + + // INT_RAW_TIMERS + // Position of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Pos = 0x0 + // Bit mask of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Msk = 0x1 + // Bit T0_INT_RAW. + TIMG_INT_RAW_TIMERS_T0_INT_RAW = 0x1 + // Position of T1_INT_RAW field. + TIMG_INT_RAW_TIMERS_T1_INT_RAW_Pos = 0x1 + // Bit mask of T1_INT_RAW field. + TIMG_INT_RAW_TIMERS_T1_INT_RAW_Msk = 0x2 + // Bit T1_INT_RAW. + TIMG_INT_RAW_TIMERS_T1_INT_RAW = 0x2 + // Position of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Pos = 0x2 + // Bit mask of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Msk = 0x4 + // Bit WDT_INT_RAW. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW = 0x4 + // Position of LACT_INT_RAW field. + TIMG_INT_RAW_TIMERS_LACT_INT_RAW_Pos = 0x3 + // Bit mask of LACT_INT_RAW field. + TIMG_INT_RAW_TIMERS_LACT_INT_RAW_Msk = 0x8 + // Bit LACT_INT_RAW. + TIMG_INT_RAW_TIMERS_LACT_INT_RAW = 0x8 + + // INT_ST_TIMERS + // Position of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Pos = 0x0 + // Bit mask of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Msk = 0x1 + // Bit T0_INT_ST. + TIMG_INT_ST_TIMERS_T0_INT_ST = 0x1 + // Position of T1_INT_ST field. + TIMG_INT_ST_TIMERS_T1_INT_ST_Pos = 0x1 + // Bit mask of T1_INT_ST field. + TIMG_INT_ST_TIMERS_T1_INT_ST_Msk = 0x2 + // Bit T1_INT_ST. + TIMG_INT_ST_TIMERS_T1_INT_ST = 0x2 + // Position of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Pos = 0x2 + // Bit mask of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Msk = 0x4 + // Bit WDT_INT_ST. + TIMG_INT_ST_TIMERS_WDT_INT_ST = 0x4 + // Position of LACT_INT_ST field. + TIMG_INT_ST_TIMERS_LACT_INT_ST_Pos = 0x3 + // Bit mask of LACT_INT_ST field. + TIMG_INT_ST_TIMERS_LACT_INT_ST_Msk = 0x8 + // Bit LACT_INT_ST. + TIMG_INT_ST_TIMERS_LACT_INT_ST = 0x8 + + // INT_CLR_TIMERS + // Position of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Pos = 0x0 + // Bit mask of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Msk = 0x1 + // Bit T0_INT_CLR. + TIMG_INT_CLR_TIMERS_T0_INT_CLR = 0x1 + // Position of T1_INT_CLR field. + TIMG_INT_CLR_TIMERS_T1_INT_CLR_Pos = 0x1 + // Bit mask of T1_INT_CLR field. + TIMG_INT_CLR_TIMERS_T1_INT_CLR_Msk = 0x2 + // Bit T1_INT_CLR. + TIMG_INT_CLR_TIMERS_T1_INT_CLR = 0x2 + // Position of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Pos = 0x2 + // Bit mask of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Msk = 0x4 + // Bit WDT_INT_CLR. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR = 0x4 + // Position of LACT_INT_CLR field. + TIMG_INT_CLR_TIMERS_LACT_INT_CLR_Pos = 0x3 + // Bit mask of LACT_INT_CLR field. + TIMG_INT_CLR_TIMERS_LACT_INT_CLR_Msk = 0x8 + // Bit LACT_INT_CLR. + TIMG_INT_CLR_TIMERS_LACT_INT_CLR = 0x8 + + // NTIMERS_DATE + // Position of NTIMERS_DATE field. + TIMG_NTIMERS_DATE_NTIMERS_DATE_Pos = 0x0 + // Bit mask of NTIMERS_DATE field. + TIMG_NTIMERS_DATE_NTIMERS_DATE_Msk = 0xfffffff + + // TIMGCLK + // Position of CLK_EN field. + TIMG_TIMGCLK_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + TIMG_TIMGCLK_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + TIMG_TIMGCLK_CLK_EN = 0x80000000 +) + +// Constants for TWAI0: Two-Wire Automotive Interface +const ( + // MODE: Mode Register + // Position of RESET_MODE field. + TWAI_MODE_RESET_MODE_Pos = 0x0 + // Bit mask of RESET_MODE field. + TWAI_MODE_RESET_MODE_Msk = 0x1 + // Bit RESET_MODE. + TWAI_MODE_RESET_MODE = 0x1 + // Position of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Pos = 0x1 + // Bit mask of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Msk = 0x2 + // Bit LISTEN_ONLY_MODE. + TWAI_MODE_LISTEN_ONLY_MODE = 0x2 + // Position of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Pos = 0x2 + // Bit mask of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Msk = 0x4 + // Bit SELF_TEST_MODE. + TWAI_MODE_SELF_TEST_MODE = 0x4 + // Position of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Pos = 0x3 + // Bit mask of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Msk = 0x8 + // Bit RX_FILTER_MODE. + TWAI_MODE_RX_FILTER_MODE = 0x8 + + // CMD: Command Register + // Position of TX_REQ field. + TWAI_CMD_TX_REQ_Pos = 0x0 + // Bit mask of TX_REQ field. + TWAI_CMD_TX_REQ_Msk = 0x1 + // Bit TX_REQ. + TWAI_CMD_TX_REQ = 0x1 + // Position of ABORT_TX field. + TWAI_CMD_ABORT_TX_Pos = 0x1 + // Bit mask of ABORT_TX field. + TWAI_CMD_ABORT_TX_Msk = 0x2 + // Bit ABORT_TX. + TWAI_CMD_ABORT_TX = 0x2 + // Position of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Pos = 0x2 + // Bit mask of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Msk = 0x4 + // Bit RELEASE_BUF. + TWAI_CMD_RELEASE_BUF = 0x4 + // Position of CLR_OVERRUN field. + TWAI_CMD_CLR_OVERRUN_Pos = 0x3 + // Bit mask of CLR_OVERRUN field. + TWAI_CMD_CLR_OVERRUN_Msk = 0x8 + // Bit CLR_OVERRUN. + TWAI_CMD_CLR_OVERRUN = 0x8 + // Position of SELF_RX_REQ field. + TWAI_CMD_SELF_RX_REQ_Pos = 0x4 + // Bit mask of SELF_RX_REQ field. + TWAI_CMD_SELF_RX_REQ_Msk = 0x10 + // Bit SELF_RX_REQ. + TWAI_CMD_SELF_RX_REQ = 0x10 + + // STATUS: Status register + // Position of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Pos = 0x0 + // Bit mask of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Msk = 0x1 + // Bit RX_BUF_ST. + TWAI_STATUS_RX_BUF_ST = 0x1 + // Position of OVERRUN_ST field. + TWAI_STATUS_OVERRUN_ST_Pos = 0x1 + // Bit mask of OVERRUN_ST field. + TWAI_STATUS_OVERRUN_ST_Msk = 0x2 + // Bit OVERRUN_ST. + TWAI_STATUS_OVERRUN_ST = 0x2 + // Position of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Pos = 0x2 + // Bit mask of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Msk = 0x4 + // Bit TX_BUF_ST. + TWAI_STATUS_TX_BUF_ST = 0x4 + // Position of TX_COMPLETE field. + TWAI_STATUS_TX_COMPLETE_Pos = 0x3 + // Bit mask of TX_COMPLETE field. + TWAI_STATUS_TX_COMPLETE_Msk = 0x8 + // Bit TX_COMPLETE. + TWAI_STATUS_TX_COMPLETE = 0x8 + // Position of RX_ST field. + TWAI_STATUS_RX_ST_Pos = 0x4 + // Bit mask of RX_ST field. + TWAI_STATUS_RX_ST_Msk = 0x10 + // Bit RX_ST. + TWAI_STATUS_RX_ST = 0x10 + // Position of TX_ST field. + TWAI_STATUS_TX_ST_Pos = 0x5 + // Bit mask of TX_ST field. + TWAI_STATUS_TX_ST_Msk = 0x20 + // Bit TX_ST. + TWAI_STATUS_TX_ST = 0x20 + // Position of ERR_ST field. + TWAI_STATUS_ERR_ST_Pos = 0x6 + // Bit mask of ERR_ST field. + TWAI_STATUS_ERR_ST_Msk = 0x40 + // Bit ERR_ST. + TWAI_STATUS_ERR_ST = 0x40 + // Position of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Pos = 0x7 + // Bit mask of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Msk = 0x80 + // Bit BUS_OFF_ST. + TWAI_STATUS_BUS_OFF_ST = 0x80 + // Position of MISS_ST field. + TWAI_STATUS_MISS_ST_Pos = 0x8 + // Bit mask of MISS_ST field. + TWAI_STATUS_MISS_ST_Msk = 0x100 + // Bit MISS_ST. + TWAI_STATUS_MISS_ST = 0x100 + + // INT_RAW: Interrupt Register + // Position of RX_INT_ST field. + TWAI_INT_RAW_RX_INT_ST_Pos = 0x0 + // Bit mask of RX_INT_ST field. + TWAI_INT_RAW_RX_INT_ST_Msk = 0x1 + // Bit RX_INT_ST. + TWAI_INT_RAW_RX_INT_ST = 0x1 + // Position of TX_INT_ST field. + TWAI_INT_RAW_TX_INT_ST_Pos = 0x1 + // Bit mask of TX_INT_ST field. + TWAI_INT_RAW_TX_INT_ST_Msk = 0x2 + // Bit TX_INT_ST. + TWAI_INT_RAW_TX_INT_ST = 0x2 + // Position of ERR_WARN_INT_ST field. + TWAI_INT_RAW_ERR_WARN_INT_ST_Pos = 0x2 + // Bit mask of ERR_WARN_INT_ST field. + TWAI_INT_RAW_ERR_WARN_INT_ST_Msk = 0x4 + // Bit ERR_WARN_INT_ST. + TWAI_INT_RAW_ERR_WARN_INT_ST = 0x4 + // Position of OVERRUN_INT_ST field. + TWAI_INT_RAW_OVERRUN_INT_ST_Pos = 0x3 + // Bit mask of OVERRUN_INT_ST field. + TWAI_INT_RAW_OVERRUN_INT_ST_Msk = 0x8 + // Bit OVERRUN_INT_ST. + TWAI_INT_RAW_OVERRUN_INT_ST = 0x8 + // Position of ERR_PASSIVE_INT_ST field. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ST field. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ST. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST = 0x20 + // Position of ARB_LOST_INT_ST field. + TWAI_INT_RAW_ARB_LOST_INT_ST_Pos = 0x6 + // Bit mask of ARB_LOST_INT_ST field. + TWAI_INT_RAW_ARB_LOST_INT_ST_Msk = 0x40 + // Bit ARB_LOST_INT_ST. + TWAI_INT_RAW_ARB_LOST_INT_ST = 0x40 + // Position of BUS_ERR_INT_ST field. + TWAI_INT_RAW_BUS_ERR_INT_ST_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ST field. + TWAI_INT_RAW_BUS_ERR_INT_ST_Msk = 0x80 + // Bit BUS_ERR_INT_ST. + TWAI_INT_RAW_BUS_ERR_INT_ST = 0x80 + + // INT_ENA: Interrupt Enable Register + // Position of RX_INT_ENA field. + TWAI_INT_ENA_RX_INT_ENA_Pos = 0x0 + // Bit mask of RX_INT_ENA field. + TWAI_INT_ENA_RX_INT_ENA_Msk = 0x1 + // Bit RX_INT_ENA. + TWAI_INT_ENA_RX_INT_ENA = 0x1 + // Position of TX_INT_ENA field. + TWAI_INT_ENA_TX_INT_ENA_Pos = 0x1 + // Bit mask of TX_INT_ENA field. + TWAI_INT_ENA_TX_INT_ENA_Msk = 0x2 + // Bit TX_INT_ENA. + TWAI_INT_ENA_TX_INT_ENA = 0x2 + // Position of ERR_WARN_INT_ENA field. + TWAI_INT_ENA_ERR_WARN_INT_ENA_Pos = 0x2 + // Bit mask of ERR_WARN_INT_ENA field. + TWAI_INT_ENA_ERR_WARN_INT_ENA_Msk = 0x4 + // Bit ERR_WARN_INT_ENA. + TWAI_INT_ENA_ERR_WARN_INT_ENA = 0x4 + // Position of OVERRUN_INT_ENA field. + TWAI_INT_ENA_OVERRUN_INT_ENA_Pos = 0x3 + // Bit mask of OVERRUN_INT_ENA field. + TWAI_INT_ENA_OVERRUN_INT_ENA_Msk = 0x8 + // Bit OVERRUN_INT_ENA. + TWAI_INT_ENA_OVERRUN_INT_ENA = 0x8 + // Position of ERR_PASSIVE_INT_ENA field. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ENA field. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ENA. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA = 0x20 + // Position of ARB_LOST_INT_ENA field. + TWAI_INT_ENA_ARB_LOST_INT_ENA_Pos = 0x6 + // Bit mask of ARB_LOST_INT_ENA field. + TWAI_INT_ENA_ARB_LOST_INT_ENA_Msk = 0x40 + // Bit ARB_LOST_INT_ENA. + TWAI_INT_ENA_ARB_LOST_INT_ENA = 0x40 + // Position of BUS_ERR_INT_ENA field. + TWAI_INT_ENA_BUS_ERR_INT_ENA_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ENA field. + TWAI_INT_ENA_BUS_ERR_INT_ENA_Msk = 0x80 + // Bit BUS_ERR_INT_ENA. + TWAI_INT_ENA_BUS_ERR_INT_ENA = 0x80 + + // BUS_TIMING_0: Bus Timing Register 0 + // Position of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Pos = 0x0 + // Bit mask of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Msk = 0x3f + // Position of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Pos = 0x6 + // Bit mask of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Msk = 0xc0 + + // BUS_TIMING_1: Bus Timing Register 1 + // Position of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Pos = 0x0 + // Bit mask of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Msk = 0xf + // Position of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Pos = 0x4 + // Bit mask of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Msk = 0x70 + // Position of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Pos = 0x7 + // Bit mask of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Msk = 0x80 + // Bit TIME_SAMP. + TWAI_BUS_TIMING_1_TIME_SAMP = 0x80 + + // ARB_LOST_CAP: Arbitration Lost Capture Register + // Position of ARB_LOST_CAP field. + TWAI_ARB_LOST_CAP_ARB_LOST_CAP_Pos = 0x0 + // Bit mask of ARB_LOST_CAP field. + TWAI_ARB_LOST_CAP_ARB_LOST_CAP_Msk = 0x1f + + // ERR_CODE_CAP: Error Code Capture Register + // Position of ECC_SEGMENT field. + TWAI_ERR_CODE_CAP_ECC_SEGMENT_Pos = 0x0 + // Bit mask of ECC_SEGMENT field. + TWAI_ERR_CODE_CAP_ECC_SEGMENT_Msk = 0x1f + // Position of ECC_DIRECTION field. + TWAI_ERR_CODE_CAP_ECC_DIRECTION_Pos = 0x5 + // Bit mask of ECC_DIRECTION field. + TWAI_ERR_CODE_CAP_ECC_DIRECTION_Msk = 0x20 + // Bit ECC_DIRECTION. + TWAI_ERR_CODE_CAP_ECC_DIRECTION = 0x20 + // Position of ECC_TYPE field. + TWAI_ERR_CODE_CAP_ECC_TYPE_Pos = 0x6 + // Bit mask of ECC_TYPE field. + TWAI_ERR_CODE_CAP_ECC_TYPE_Msk = 0xc0 + + // ERR_WARNING_LIMIT: Error Warning Limit Register + // Position of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Pos = 0x0 + // Bit mask of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Msk = 0xff + + // RX_ERR_CNT: Receive Error Counter Register + // Position of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Pos = 0x0 + // Bit mask of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Msk = 0xff + + // TX_ERR_CNT: Transmit Error Counter Register + // Position of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Pos = 0x0 + // Bit mask of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Msk = 0xff + + // DATA_0: Data register 0 + // Position of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Pos = 0x0 + // Bit mask of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Msk = 0xff + + // DATA_1: Data register 1 + // Position of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Pos = 0x0 + // Bit mask of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Msk = 0xff + + // DATA_2: Data register 2 + // Position of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Pos = 0x0 + // Bit mask of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Msk = 0xff + + // DATA_3: Data register 3 + // Position of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Pos = 0x0 + // Bit mask of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Msk = 0xff + + // DATA_4: Data register 4 + // Position of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Pos = 0x0 + // Bit mask of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Msk = 0xff + + // DATA_5: Data register 5 + // Position of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Pos = 0x0 + // Bit mask of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Msk = 0xff + + // DATA_6: Data register 6 + // Position of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Pos = 0x0 + // Bit mask of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Msk = 0xff + + // DATA_7: Data register 7 + // Position of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Pos = 0x0 + // Bit mask of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Msk = 0xff + + // DATA_8: Data register 8 + // Position of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Pos = 0x0 + // Bit mask of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Msk = 0xff + + // DATA_9: Data register 9 + // Position of TX_BYTE_9 field. + TWAI_DATA_9_TX_BYTE_9_Pos = 0x0 + // Bit mask of TX_BYTE_9 field. + TWAI_DATA_9_TX_BYTE_9_Msk = 0xff + + // DATA_10: Data register 10 + // Position of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Pos = 0x0 + // Bit mask of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Msk = 0xff + + // DATA_11: Data register 11 + // Position of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Pos = 0x0 + // Bit mask of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Msk = 0xff + + // DATA_12: Data register 12 + // Position of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Pos = 0x0 + // Bit mask of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Msk = 0xff + + // RX_MESSAGE_CNT: Receive Message Counter Register + // Position of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Pos = 0x0 + // Bit mask of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Msk = 0x7f + + // CLOCK_DIVIDER: Clock Divider register + // Position of CD field. + TWAI_CLOCK_DIVIDER_CD_Pos = 0x0 + // Bit mask of CD field. + TWAI_CLOCK_DIVIDER_CD_Msk = 0xff + // Position of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Pos = 0x8 + // Bit mask of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Msk = 0x100 + // Bit CLOCK_OFF. + TWAI_CLOCK_DIVIDER_CLOCK_OFF = 0x100 +) + +// Constants for UART0: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +const ( + // FIFO + // Position of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + + // INT_RAW + // Position of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9 + // Bit mask of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200 + // Bit SW_XON_INT_RAW. + UART_INT_RAW_SW_XON_INT_RAW = 0x200 + // Position of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa + // Bit mask of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400 + // Bit SW_XOFF_INT_RAW. + UART_INT_RAW_SW_XOFF_INT_RAW = 0x400 + // Position of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb + // Bit mask of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800 + // Bit GLITCH_DET_INT_RAW. + UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800 + // Position of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000 + // Position of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit TX_DONE_INT_RAW. + UART_INT_RAW_TX_DONE_INT_RAW = 0x4000 + // Position of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_RAW. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW = 0x8000 + // Position of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_RAW. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW = 0x10000 + // Position of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Msk = 0x20000 + // Bit RS485_CLASH_INT_RAW. + UART_INT_RAW_RS485_CLASH_INT_RAW = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_RAW. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000 + + // INT_ST + // Position of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Pos = 0x9 + // Bit mask of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Msk = 0x200 + // Bit SW_XON_INT_ST. + UART_INT_ST_SW_XON_INT_ST = 0x200 + // Position of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa + // Bit mask of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400 + // Bit SW_XOFF_INT_ST. + UART_INT_ST_SW_XOFF_INT_ST = 0x400 + // Position of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800 + // Bit GLITCH_DET_INT_ST. + UART_INT_ST_GLITCH_DET_INT_ST = 0x800 + // Position of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ST. + UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ST. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000 + // Position of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000 + // Bit TX_DONE_INT_ST. + UART_INT_ST_TX_DONE_INT_ST = 0x4000 + // Position of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ST. + UART_INT_ST_RS485_PARITY_ERR_INT_ST = 0x8000 + // Position of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ST. + UART_INT_ST_RS485_FRM_ERR_INT_ST = 0x10000 + // Position of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Msk = 0x20000 + // Bit RS485_CLASH_INT_ST. + UART_INT_ST_RS485_CLASH_INT_ST = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ST. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000 + + // INT_ENA + // Position of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9 + // Bit mask of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200 + // Bit SW_XON_INT_ENA. + UART_INT_ENA_SW_XON_INT_ENA = 0x200 + // Position of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa + // Bit mask of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400 + // Bit SW_XOFF_INT_ENA. + UART_INT_ENA_SW_XOFF_INT_ENA = 0x400 + // Position of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800 + // Bit GLITCH_DET_INT_ENA. + UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800 + // Position of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000 + // Position of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit TX_DONE_INT_ENA. + UART_INT_ENA_TX_DONE_INT_ENA = 0x4000 + // Position of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ENA. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA = 0x8000 + // Position of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ENA. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA = 0x10000 + // Position of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Msk = 0x20000 + // Bit RS485_CLASH_INT_ENA. + UART_INT_ENA_RS485_CLASH_INT_ENA = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ENA. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000 + + // INT_CLR + // Position of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9 + // Bit mask of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200 + // Bit SW_XON_INT_CLR. + UART_INT_CLR_SW_XON_INT_CLR = 0x200 + // Position of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa + // Bit mask of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400 + // Bit SW_XOFF_INT_CLR. + UART_INT_CLR_SW_XOFF_INT_CLR = 0x400 + // Position of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb + // Bit mask of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800 + // Bit GLITCH_DET_INT_CLR. + UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800 + // Position of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000 + // Position of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit TX_DONE_INT_CLR. + UART_INT_CLR_TX_DONE_INT_CLR = 0x4000 + // Position of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_CLR. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR = 0x8000 + // Position of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_CLR. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR = 0x10000 + // Position of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Msk = 0x20000 + // Bit RS485_CLASH_INT_CLR. + UART_INT_CLR_RS485_CLASH_INT_CLR = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_CLR. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000 + + // CLKDIV + // Position of CLKDIV field. + UART_CLKDIV_CLKDIV_Pos = 0x0 + // Bit mask of CLKDIV field. + UART_CLKDIV_CLKDIV_Msk = 0xfffff + // Position of FRAG field. + UART_CLKDIV_FRAG_Pos = 0x14 + // Bit mask of FRAG field. + UART_CLKDIV_FRAG_Msk = 0xf00000 + + // AUTOBAUD + // Position of EN field. + UART_AUTOBAUD_EN_Pos = 0x0 + // Bit mask of EN field. + UART_AUTOBAUD_EN_Msk = 0x1 + // Bit EN. + UART_AUTOBAUD_EN = 0x1 + // Position of GLITCH_FILT field. + UART_AUTOBAUD_GLITCH_FILT_Pos = 0x8 + // Bit mask of GLITCH_FILT field. + UART_AUTOBAUD_GLITCH_FILT_Msk = 0xff00 + + // STATUS + // Position of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Pos = 0x0 + // Bit mask of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Msk = 0xff + // Position of ST_URX_OUT field. + UART_STATUS_ST_URX_OUT_Pos = 0x8 + // Bit mask of ST_URX_OUT field. + UART_STATUS_ST_URX_OUT_Msk = 0xf00 + // Position of DSRN field. + UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + UART_STATUS_DSRN = 0x2000 + // Position of CTSN field. + UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + UART_STATUS_CTSN = 0x4000 + // Position of RXD field. + UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + UART_STATUS_RXD = 0x8000 + // Position of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Pos = 0x10 + // Bit mask of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Msk = 0xff0000 + // Position of ST_UTX_OUT field. + UART_STATUS_ST_UTX_OUT_Pos = 0x18 + // Bit mask of ST_UTX_OUT field. + UART_STATUS_ST_UTX_OUT_Msk = 0xf000000 + // Position of DTRN field. + UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + UART_STATUS_DTRN = 0x20000000 + // Position of RTSN field. + UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + UART_STATUS_RTSN = 0x40000000 + // Position of TXD field. + UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + UART_STATUS_TXD = 0x80000000 + + // CONF0 + // Position of PARITY field. + UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + UART_CONF0_PARITY = 0x1 + // Position of PARITY_EN field. + UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + UART_CONF0_PARITY_EN = 0x2 + // Position of BIT_NUM field. + UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + UART_CONF0_BIT_NUM_Msk = 0xc + // Position of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of SW_RTS field. + UART_CONF0_SW_RTS_Pos = 0x6 + // Bit mask of SW_RTS field. + UART_CONF0_SW_RTS_Msk = 0x40 + // Bit SW_RTS. + UART_CONF0_SW_RTS = 0x40 + // Position of SW_DTR field. + UART_CONF0_SW_DTR_Pos = 0x7 + // Bit mask of SW_DTR field. + UART_CONF0_SW_DTR_Msk = 0x80 + // Bit SW_DTR. + UART_CONF0_SW_DTR = 0x80 + // Position of TXD_BRK field. + UART_CONF0_TXD_BRK_Pos = 0x8 + // Bit mask of TXD_BRK field. + UART_CONF0_TXD_BRK_Msk = 0x100 + // Bit TXD_BRK. + UART_CONF0_TXD_BRK = 0x100 + // Position of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Pos = 0x9 + // Bit mask of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Msk = 0x200 + // Bit IRDA_DPLX. + UART_CONF0_IRDA_DPLX = 0x200 + // Position of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Pos = 0xa + // Bit mask of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Msk = 0x400 + // Bit IRDA_TX_EN. + UART_CONF0_IRDA_TX_EN = 0x400 + // Position of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Pos = 0xb + // Bit mask of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Msk = 0x800 + // Bit IRDA_WCTL. + UART_CONF0_IRDA_WCTL = 0x800 + // Position of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Pos = 0xc + // Bit mask of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Msk = 0x1000 + // Bit IRDA_TX_INV. + UART_CONF0_IRDA_TX_INV = 0x1000 + // Position of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Pos = 0xd + // Bit mask of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Msk = 0x2000 + // Bit IRDA_RX_INV. + UART_CONF0_IRDA_RX_INV = 0x2000 + // Position of LOOPBACK field. + UART_CONF0_LOOPBACK_Pos = 0xe + // Bit mask of LOOPBACK field. + UART_CONF0_LOOPBACK_Msk = 0x4000 + // Bit LOOPBACK. + UART_CONF0_LOOPBACK = 0x4000 + // Position of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Pos = 0xf + // Bit mask of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Msk = 0x8000 + // Bit TX_FLOW_EN. + UART_CONF0_TX_FLOW_EN = 0x8000 + // Position of IRDA_EN field. + UART_CONF0_IRDA_EN_Pos = 0x10 + // Bit mask of IRDA_EN field. + UART_CONF0_IRDA_EN_Msk = 0x10000 + // Bit IRDA_EN. + UART_CONF0_IRDA_EN = 0x10000 + // Position of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Pos = 0x11 + // Bit mask of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Msk = 0x20000 + // Bit RXFIFO_RST. + UART_CONF0_RXFIFO_RST = 0x20000 + // Position of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Pos = 0x12 + // Bit mask of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Msk = 0x40000 + // Bit TXFIFO_RST. + UART_CONF0_TXFIFO_RST = 0x40000 + // Position of RXD_INV field. + UART_CONF0_RXD_INV_Pos = 0x13 + // Bit mask of RXD_INV field. + UART_CONF0_RXD_INV_Msk = 0x80000 + // Bit RXD_INV. + UART_CONF0_RXD_INV = 0x80000 + // Position of CTS_INV field. + UART_CONF0_CTS_INV_Pos = 0x14 + // Bit mask of CTS_INV field. + UART_CONF0_CTS_INV_Msk = 0x100000 + // Bit CTS_INV. + UART_CONF0_CTS_INV = 0x100000 + // Position of DSR_INV field. + UART_CONF0_DSR_INV_Pos = 0x15 + // Bit mask of DSR_INV field. + UART_CONF0_DSR_INV_Msk = 0x200000 + // Bit DSR_INV. + UART_CONF0_DSR_INV = 0x200000 + // Position of TXD_INV field. + UART_CONF0_TXD_INV_Pos = 0x16 + // Bit mask of TXD_INV field. + UART_CONF0_TXD_INV_Msk = 0x400000 + // Bit TXD_INV. + UART_CONF0_TXD_INV = 0x400000 + // Position of RTS_INV field. + UART_CONF0_RTS_INV_Pos = 0x17 + // Bit mask of RTS_INV field. + UART_CONF0_RTS_INV_Msk = 0x800000 + // Bit RTS_INV. + UART_CONF0_RTS_INV = 0x800000 + // Position of DTR_INV field. + UART_CONF0_DTR_INV_Pos = 0x18 + // Bit mask of DTR_INV field. + UART_CONF0_DTR_INV_Msk = 0x1000000 + // Bit DTR_INV. + UART_CONF0_DTR_INV = 0x1000000 + // Position of CLK_EN field. + UART_CONF0_CLK_EN_Pos = 0x19 + // Bit mask of CLK_EN field. + UART_CONF0_CLK_EN_Msk = 0x2000000 + // Bit CLK_EN. + UART_CONF0_CLK_EN = 0x2000000 + // Position of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Pos = 0x1a + // Bit mask of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Msk = 0x4000000 + // Bit ERR_WR_MASK. + UART_CONF0_ERR_WR_MASK = 0x4000000 + // Position of TICK_REF_ALWAYS_ON field. + UART_CONF0_TICK_REF_ALWAYS_ON_Pos = 0x1b + // Bit mask of TICK_REF_ALWAYS_ON field. + UART_CONF0_TICK_REF_ALWAYS_ON_Msk = 0x8000000 + // Bit TICK_REF_ALWAYS_ON. + UART_CONF0_TICK_REF_ALWAYS_ON = 0x8000000 + + // CONF1 + // Position of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0x7f + // Position of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0x8 + // Bit mask of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0x7f00 + // Position of RX_FLOW_THRHD field. + UART_CONF1_RX_FLOW_THRHD_Pos = 0x10 + // Bit mask of RX_FLOW_THRHD field. + UART_CONF1_RX_FLOW_THRHD_Msk = 0x7f0000 + // Position of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Pos = 0x17 + // Bit mask of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Msk = 0x800000 + // Bit RX_FLOW_EN. + UART_CONF1_RX_FLOW_EN = 0x800000 + // Position of RX_TOUT_THRHD field. + UART_CONF1_RX_TOUT_THRHD_Pos = 0x18 + // Bit mask of RX_TOUT_THRHD field. + UART_CONF1_RX_TOUT_THRHD_Msk = 0x7f000000 + // Position of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Pos = 0x1f + // Bit mask of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Msk = 0x80000000 + // Bit RX_TOUT_EN. + UART_CONF1_RX_TOUT_EN = 0x80000000 + + // LOWPULSE + // Position of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Msk = 0xfffff + + // HIGHPULSE + // Position of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Msk = 0xfffff + + // RXD_CNT + // Position of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0 + // Bit mask of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff + + // FLOW_CONF + // Position of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Pos = 0x0 + // Bit mask of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Msk = 0x1 + // Bit SW_FLOW_CON_EN. + UART_FLOW_CONF_SW_FLOW_CON_EN = 0x1 + // Position of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Pos = 0x1 + // Bit mask of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Msk = 0x2 + // Bit XONOFF_DEL. + UART_FLOW_CONF_XONOFF_DEL = 0x2 + // Position of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Pos = 0x2 + // Bit mask of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Msk = 0x4 + // Bit FORCE_XON. + UART_FLOW_CONF_FORCE_XON = 0x4 + // Position of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Pos = 0x3 + // Bit mask of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Msk = 0x8 + // Bit FORCE_XOFF. + UART_FLOW_CONF_FORCE_XOFF = 0x8 + // Position of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Pos = 0x4 + // Bit mask of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Msk = 0x10 + // Bit SEND_XON. + UART_FLOW_CONF_SEND_XON = 0x10 + // Position of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Pos = 0x5 + // Bit mask of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Msk = 0x20 + // Bit SEND_XOFF. + UART_FLOW_CONF_SEND_XOFF = 0x20 + + // SLEEP_CONF + // Position of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Pos = 0x0 + // Bit mask of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Msk = 0x3ff + + // SWFC_CONF + // Position of XON_THRESHOLD field. + UART_SWFC_CONF_XON_THRESHOLD_Pos = 0x0 + // Bit mask of XON_THRESHOLD field. + UART_SWFC_CONF_XON_THRESHOLD_Msk = 0xff + // Position of XOFF_THRESHOLD field. + UART_SWFC_CONF_XOFF_THRESHOLD_Pos = 0x8 + // Bit mask of XOFF_THRESHOLD field. + UART_SWFC_CONF_XOFF_THRESHOLD_Msk = 0xff00 + // Position of XON_CHAR field. + UART_SWFC_CONF_XON_CHAR_Pos = 0x10 + // Bit mask of XON_CHAR field. + UART_SWFC_CONF_XON_CHAR_Msk = 0xff0000 + // Position of XOFF_CHAR field. + UART_SWFC_CONF_XOFF_CHAR_Pos = 0x18 + // Bit mask of XOFF_CHAR field. + UART_SWFC_CONF_XOFF_CHAR_Msk = 0xff000000 + + // IDLE_CONF + // Position of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Pos = 0x0 + // Bit mask of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Msk = 0x3ff + // Position of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Pos = 0xa + // Bit mask of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Msk = 0xffc00 + // Position of TX_BRK_NUM field. + UART_IDLE_CONF_TX_BRK_NUM_Pos = 0x14 + // Bit mask of TX_BRK_NUM field. + UART_IDLE_CONF_TX_BRK_NUM_Msk = 0xff00000 + + // RS485_CONF + // Position of RS485_EN field. + UART_RS485_CONF_RS485_EN_Pos = 0x0 + // Bit mask of RS485_EN field. + UART_RS485_CONF_RS485_EN_Msk = 0x1 + // Bit RS485_EN. + UART_RS485_CONF_RS485_EN = 0x1 + // Position of DL0_EN field. + UART_RS485_CONF_DL0_EN_Pos = 0x1 + // Bit mask of DL0_EN field. + UART_RS485_CONF_DL0_EN_Msk = 0x2 + // Bit DL0_EN. + UART_RS485_CONF_DL0_EN = 0x2 + // Position of DL1_EN field. + UART_RS485_CONF_DL1_EN_Pos = 0x2 + // Bit mask of DL1_EN field. + UART_RS485_CONF_DL1_EN_Msk = 0x4 + // Bit DL1_EN. + UART_RS485_CONF_DL1_EN = 0x4 + // Position of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Pos = 0x3 + // Bit mask of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Msk = 0x8 + // Bit RS485TX_RX_EN. + UART_RS485_CONF_RS485TX_RX_EN = 0x8 + // Position of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Pos = 0x4 + // Bit mask of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Msk = 0x10 + // Bit RS485RXBY_TX_EN. + UART_RS485_CONF_RS485RXBY_TX_EN = 0x10 + // Position of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Pos = 0x5 + // Bit mask of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Msk = 0x20 + // Bit RS485_RX_DLY_NUM. + UART_RS485_CONF_RS485_RX_DLY_NUM = 0x20 + // Position of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Pos = 0x6 + // Bit mask of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Msk = 0x3c0 + + // AT_CMD_PRECNT + // Position of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Pos = 0x0 + // Bit mask of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Msk = 0xffffff + + // AT_CMD_POSTCNT + // Position of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Pos = 0x0 + // Bit mask of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Msk = 0xffffff + + // AT_CMD_GAPTOUT + // Position of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Pos = 0x0 + // Bit mask of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Msk = 0xffffff + + // AT_CMD_CHAR + // Position of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Pos = 0x0 + // Bit mask of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Msk = 0xff + // Position of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Pos = 0x8 + // Bit mask of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Msk = 0xff00 + + // MEM_CONF + // Position of MEM_PD field. + UART_MEM_CONF_MEM_PD_Pos = 0x0 + // Bit mask of MEM_PD field. + UART_MEM_CONF_MEM_PD_Msk = 0x1 + // Bit MEM_PD. + UART_MEM_CONF_MEM_PD = 0x1 + // Position of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Pos = 0x3 + // Bit mask of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Msk = 0x78 + // Position of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Pos = 0x7 + // Bit mask of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Msk = 0x780 + // Position of RX_FLOW_THRHD_H3 field. + UART_MEM_CONF_RX_FLOW_THRHD_H3_Pos = 0xf + // Bit mask of RX_FLOW_THRHD_H3 field. + UART_MEM_CONF_RX_FLOW_THRHD_H3_Msk = 0x38000 + // Position of RX_TOUT_THRHD_H3 field. + UART_MEM_CONF_RX_TOUT_THRHD_H3_Pos = 0x12 + // Bit mask of RX_TOUT_THRHD_H3 field. + UART_MEM_CONF_RX_TOUT_THRHD_H3_Msk = 0x1c0000 + // Position of XON_THRESHOLD_H2 field. + UART_MEM_CONF_XON_THRESHOLD_H2_Pos = 0x15 + // Bit mask of XON_THRESHOLD_H2 field. + UART_MEM_CONF_XON_THRESHOLD_H2_Msk = 0x600000 + // Position of XOFF_THRESHOLD_H2 field. + UART_MEM_CONF_XOFF_THRESHOLD_H2_Pos = 0x17 + // Bit mask of XOFF_THRESHOLD_H2 field. + UART_MEM_CONF_XOFF_THRESHOLD_H2_Msk = 0x1800000 + // Position of RX_MEM_FULL_THRHD field. + UART_MEM_CONF_RX_MEM_FULL_THRHD_Pos = 0x19 + // Bit mask of RX_MEM_FULL_THRHD field. + UART_MEM_CONF_RX_MEM_FULL_THRHD_Msk = 0xe000000 + // Position of TX_MEM_EMPTY_THRHD field. + UART_MEM_CONF_TX_MEM_EMPTY_THRHD_Pos = 0x1c + // Bit mask of TX_MEM_EMPTY_THRHD field. + UART_MEM_CONF_TX_MEM_EMPTY_THRHD_Msk = 0x70000000 + + // MEM_TX_STATUS + // Position of MEM_TX_STATUS field. + UART_MEM_TX_STATUS_MEM_TX_STATUS_Pos = 0x0 + // Bit mask of MEM_TX_STATUS field. + UART_MEM_TX_STATUS_MEM_TX_STATUS_Msk = 0xffffff + + // MEM_RX_STATUS + // Position of MEM_RX_STATUS field. + UART_MEM_RX_STATUS_MEM_RX_STATUS_Pos = 0x0 + // Bit mask of MEM_RX_STATUS field. + UART_MEM_RX_STATUS_MEM_RX_STATUS_Msk = 0xffffff + // Position of MEM_RX_RD_ADDR field. + UART_MEM_RX_STATUS_MEM_RX_RD_ADDR_Pos = 0x2 + // Bit mask of MEM_RX_RD_ADDR field. + UART_MEM_RX_STATUS_MEM_RX_RD_ADDR_Msk = 0x1ffc + // Position of MEM_RX_WR_ADDR field. + UART_MEM_RX_STATUS_MEM_RX_WR_ADDR_Pos = 0xd + // Bit mask of MEM_RX_WR_ADDR field. + UART_MEM_RX_STATUS_MEM_RX_WR_ADDR_Msk = 0xffe000 + + // MEM_CNT_STATUS + // Position of RX_MEM_CNT field. + UART_MEM_CNT_STATUS_RX_MEM_CNT_Pos = 0x0 + // Bit mask of RX_MEM_CNT field. + UART_MEM_CNT_STATUS_RX_MEM_CNT_Msk = 0x7 + // Position of TX_MEM_CNT field. + UART_MEM_CNT_STATUS_TX_MEM_CNT_Pos = 0x3 + // Bit mask of TX_MEM_CNT field. + UART_MEM_CNT_STATUS_TX_MEM_CNT_Msk = 0x38 + + // POSPULSE + // Position of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Msk = 0xfffff + + // NEGPULSE + // Position of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Msk = 0xfffff + + // DATE + // Position of DATE field. + UART_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UART_DATE_DATE_Msk = 0xffffffff + + // ID + // Position of ID field. + UART_ID_ID_Pos = 0x0 + // Bit mask of ID field. + UART_ID_ID_Msk = 0xffffffff +) + +// Constants for UHCI0: Universal Host Controller Interface 0 +const ( + // CONF0 + // Position of IN_RST field. + UHCI_CONF0_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + UHCI_CONF0_IN_RST_Msk = 0x1 + // Bit IN_RST. + UHCI_CONF0_IN_RST = 0x1 + // Position of OUT_RST field. + UHCI_CONF0_OUT_RST_Pos = 0x1 + // Bit mask of OUT_RST field. + UHCI_CONF0_OUT_RST_Msk = 0x2 + // Bit OUT_RST. + UHCI_CONF0_OUT_RST = 0x2 + // Position of AHBM_FIFO_RST field. + UHCI_CONF0_AHBM_FIFO_RST_Pos = 0x2 + // Bit mask of AHBM_FIFO_RST field. + UHCI_CONF0_AHBM_FIFO_RST_Msk = 0x4 + // Bit AHBM_FIFO_RST. + UHCI_CONF0_AHBM_FIFO_RST = 0x4 + // Position of AHBM_RST field. + UHCI_CONF0_AHBM_RST_Pos = 0x3 + // Bit mask of AHBM_RST field. + UHCI_CONF0_AHBM_RST_Msk = 0x8 + // Bit AHBM_RST. + UHCI_CONF0_AHBM_RST = 0x8 + // Position of IN_LOOP_TEST field. + UHCI_CONF0_IN_LOOP_TEST_Pos = 0x4 + // Bit mask of IN_LOOP_TEST field. + UHCI_CONF0_IN_LOOP_TEST_Msk = 0x10 + // Bit IN_LOOP_TEST. + UHCI_CONF0_IN_LOOP_TEST = 0x10 + // Position of OUT_LOOP_TEST field. + UHCI_CONF0_OUT_LOOP_TEST_Pos = 0x5 + // Bit mask of OUT_LOOP_TEST field. + UHCI_CONF0_OUT_LOOP_TEST_Msk = 0x20 + // Bit OUT_LOOP_TEST. + UHCI_CONF0_OUT_LOOP_TEST = 0x20 + // Position of OUT_AUTO_WRBACK field. + UHCI_CONF0_OUT_AUTO_WRBACK_Pos = 0x6 + // Bit mask of OUT_AUTO_WRBACK field. + UHCI_CONF0_OUT_AUTO_WRBACK_Msk = 0x40 + // Bit OUT_AUTO_WRBACK. + UHCI_CONF0_OUT_AUTO_WRBACK = 0x40 + // Position of OUT_NO_RESTART_CLR field. + UHCI_CONF0_OUT_NO_RESTART_CLR_Pos = 0x7 + // Bit mask of OUT_NO_RESTART_CLR field. + UHCI_CONF0_OUT_NO_RESTART_CLR_Msk = 0x80 + // Bit OUT_NO_RESTART_CLR. + UHCI_CONF0_OUT_NO_RESTART_CLR = 0x80 + // Position of OUT_EOF_MODE field. + UHCI_CONF0_OUT_EOF_MODE_Pos = 0x8 + // Bit mask of OUT_EOF_MODE field. + UHCI_CONF0_OUT_EOF_MODE_Msk = 0x100 + // Bit OUT_EOF_MODE. + UHCI_CONF0_OUT_EOF_MODE = 0x100 + // Position of UART0_CE field. + UHCI_CONF0_UART0_CE_Pos = 0x9 + // Bit mask of UART0_CE field. + UHCI_CONF0_UART0_CE_Msk = 0x200 + // Bit UART0_CE. + UHCI_CONF0_UART0_CE = 0x200 + // Position of UART1_CE field. + UHCI_CONF0_UART1_CE_Pos = 0xa + // Bit mask of UART1_CE field. + UHCI_CONF0_UART1_CE_Msk = 0x400 + // Bit UART1_CE. + UHCI_CONF0_UART1_CE = 0x400 + // Position of UART2_CE field. + UHCI_CONF0_UART2_CE_Pos = 0xb + // Bit mask of UART2_CE field. + UHCI_CONF0_UART2_CE_Msk = 0x800 + // Bit UART2_CE. + UHCI_CONF0_UART2_CE = 0x800 + // Position of OUTDSCR_BURST_EN field. + UHCI_CONF0_OUTDSCR_BURST_EN_Pos = 0xc + // Bit mask of OUTDSCR_BURST_EN field. + UHCI_CONF0_OUTDSCR_BURST_EN_Msk = 0x1000 + // Bit OUTDSCR_BURST_EN. + UHCI_CONF0_OUTDSCR_BURST_EN = 0x1000 + // Position of INDSCR_BURST_EN field. + UHCI_CONF0_INDSCR_BURST_EN_Pos = 0xd + // Bit mask of INDSCR_BURST_EN field. + UHCI_CONF0_INDSCR_BURST_EN_Msk = 0x2000 + // Bit INDSCR_BURST_EN. + UHCI_CONF0_INDSCR_BURST_EN = 0x2000 + // Position of OUT_DATA_BURST_EN field. + UHCI_CONF0_OUT_DATA_BURST_EN_Pos = 0xe + // Bit mask of OUT_DATA_BURST_EN field. + UHCI_CONF0_OUT_DATA_BURST_EN_Msk = 0x4000 + // Bit OUT_DATA_BURST_EN. + UHCI_CONF0_OUT_DATA_BURST_EN = 0x4000 + // Position of MEM_TRANS_EN field. + UHCI_CONF0_MEM_TRANS_EN_Pos = 0xf + // Bit mask of MEM_TRANS_EN field. + UHCI_CONF0_MEM_TRANS_EN_Msk = 0x8000 + // Bit MEM_TRANS_EN. + UHCI_CONF0_MEM_TRANS_EN = 0x8000 + // Position of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Pos = 0x10 + // Bit mask of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Msk = 0x10000 + // Bit SEPER_EN. + UHCI_CONF0_SEPER_EN = 0x10000 + // Position of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Pos = 0x11 + // Bit mask of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Msk = 0x20000 + // Bit HEAD_EN. + UHCI_CONF0_HEAD_EN = 0x20000 + // Position of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Pos = 0x12 + // Bit mask of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Msk = 0x40000 + // Bit CRC_REC_EN. + UHCI_CONF0_CRC_REC_EN = 0x40000 + // Position of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Pos = 0x13 + // Bit mask of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Msk = 0x80000 + // Bit UART_IDLE_EOF_EN. + UHCI_CONF0_UART_IDLE_EOF_EN = 0x80000 + // Position of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Pos = 0x14 + // Bit mask of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Msk = 0x100000 + // Bit LEN_EOF_EN. + UHCI_CONF0_LEN_EOF_EN = 0x100000 + // Position of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Pos = 0x15 + // Bit mask of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Msk = 0x200000 + // Bit ENCODE_CRC_EN. + UHCI_CONF0_ENCODE_CRC_EN = 0x200000 + // Position of CLK_EN field. + UHCI_CONF0_CLK_EN_Pos = 0x16 + // Bit mask of CLK_EN field. + UHCI_CONF0_CLK_EN_Msk = 0x400000 + // Bit CLK_EN. + UHCI_CONF0_CLK_EN = 0x400000 + // Position of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Pos = 0x17 + // Bit mask of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Msk = 0x800000 + // Bit UART_RX_BRK_EOF_EN. + UHCI_CONF0_UART_RX_BRK_EOF_EN = 0x800000 + + // INT_RAW + // Position of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Pos = 0x0 + // Bit mask of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Msk = 0x1 + // Bit RX_START_INT_RAW. + UHCI_INT_RAW_RX_START_INT_RAW = 0x1 + // Position of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Pos = 0x1 + // Bit mask of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Msk = 0x2 + // Bit TX_START_INT_RAW. + UHCI_INT_RAW_TX_START_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + UHCI_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + UHCI_INT_RAW_TX_HUNG_INT_RAW = 0x8 + // Position of IN_DONE_INT_RAW field. + UHCI_INT_RAW_IN_DONE_INT_RAW_Pos = 0x4 + // Bit mask of IN_DONE_INT_RAW field. + UHCI_INT_RAW_IN_DONE_INT_RAW_Msk = 0x10 + // Bit IN_DONE_INT_RAW. + UHCI_INT_RAW_IN_DONE_INT_RAW = 0x10 + // Position of IN_SUC_EOF_INT_RAW field. + UHCI_INT_RAW_IN_SUC_EOF_INT_RAW_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_RAW field. + UHCI_INT_RAW_IN_SUC_EOF_INT_RAW_Msk = 0x20 + // Bit IN_SUC_EOF_INT_RAW. + UHCI_INT_RAW_IN_SUC_EOF_INT_RAW = 0x20 + // Position of IN_ERR_EOF_INT_RAW field. + UHCI_INT_RAW_IN_ERR_EOF_INT_RAW_Pos = 0x6 + // Bit mask of IN_ERR_EOF_INT_RAW field. + UHCI_INT_RAW_IN_ERR_EOF_INT_RAW_Msk = 0x40 + // Bit IN_ERR_EOF_INT_RAW. + UHCI_INT_RAW_IN_ERR_EOF_INT_RAW = 0x40 + // Position of OUT_DONE_INT_RAW field. + UHCI_INT_RAW_OUT_DONE_INT_RAW_Pos = 0x7 + // Bit mask of OUT_DONE_INT_RAW field. + UHCI_INT_RAW_OUT_DONE_INT_RAW_Msk = 0x80 + // Bit OUT_DONE_INT_RAW. + UHCI_INT_RAW_OUT_DONE_INT_RAW = 0x80 + // Position of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x8 + // Bit mask of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x100 + // Bit OUT_EOF_INT_RAW. + UHCI_INT_RAW_OUT_EOF_INT_RAW = 0x100 + // Position of IN_DSCR_ERR_INT_RAW field. + UHCI_INT_RAW_IN_DSCR_ERR_INT_RAW_Pos = 0x9 + // Bit mask of IN_DSCR_ERR_INT_RAW field. + UHCI_INT_RAW_IN_DSCR_ERR_INT_RAW_Msk = 0x200 + // Bit IN_DSCR_ERR_INT_RAW. + UHCI_INT_RAW_IN_DSCR_ERR_INT_RAW = 0x200 + // Position of OUT_DSCR_ERR_INT_RAW field. + UHCI_INT_RAW_OUT_DSCR_ERR_INT_RAW_Pos = 0xa + // Bit mask of OUT_DSCR_ERR_INT_RAW field. + UHCI_INT_RAW_OUT_DSCR_ERR_INT_RAW_Msk = 0x400 + // Bit OUT_DSCR_ERR_INT_RAW. + UHCI_INT_RAW_OUT_DSCR_ERR_INT_RAW = 0x400 + // Position of IN_DSCR_EMPTY_INT_RAW field. + UHCI_INT_RAW_IN_DSCR_EMPTY_INT_RAW_Pos = 0xb + // Bit mask of IN_DSCR_EMPTY_INT_RAW field. + UHCI_INT_RAW_IN_DSCR_EMPTY_INT_RAW_Msk = 0x800 + // Bit IN_DSCR_EMPTY_INT_RAW. + UHCI_INT_RAW_IN_DSCR_EMPTY_INT_RAW = 0x800 + // Position of OUTLINK_EOF_ERR_INT_RAW field. + UHCI_INT_RAW_OUTLINK_EOF_ERR_INT_RAW_Pos = 0xc + // Bit mask of OUTLINK_EOF_ERR_INT_RAW field. + UHCI_INT_RAW_OUTLINK_EOF_ERR_INT_RAW_Msk = 0x1000 + // Bit OUTLINK_EOF_ERR_INT_RAW. + UHCI_INT_RAW_OUTLINK_EOF_ERR_INT_RAW = 0x1000 + // Position of OUT_TOTAL_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Pos = 0xd + // Bit mask of OUT_TOTAL_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Msk = 0x2000 + // Bit OUT_TOTAL_EOF_INT_RAW. + UHCI_INT_RAW_OUT_TOTAL_EOF_INT_RAW = 0x2000 + // Position of SEND_S_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_Q_INT_RAW_Pos = 0xe + // Bit mask of SEND_S_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_Q_INT_RAW_Msk = 0x4000 + // Bit SEND_S_Q_INT_RAW. + UHCI_INT_RAW_SEND_S_Q_INT_RAW = 0x4000 + // Position of SEND_A_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_Q_INT_RAW_Pos = 0xf + // Bit mask of SEND_A_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_Q_INT_RAW_Msk = 0x8000 + // Bit SEND_A_Q_INT_RAW. + UHCI_INT_RAW_SEND_A_Q_INT_RAW = 0x8000 + // Position of DMA_INFIFO_FULL_WM_INT_RAW field. + UHCI_INT_RAW_DMA_INFIFO_FULL_WM_INT_RAW_Pos = 0x10 + // Bit mask of DMA_INFIFO_FULL_WM_INT_RAW field. + UHCI_INT_RAW_DMA_INFIFO_FULL_WM_INT_RAW_Msk = 0x10000 + // Bit DMA_INFIFO_FULL_WM_INT_RAW. + UHCI_INT_RAW_DMA_INFIFO_FULL_WM_INT_RAW = 0x10000 + + // INT_ST + // Position of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Pos = 0x0 + // Bit mask of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Msk = 0x1 + // Bit RX_START_INT_ST. + UHCI_INT_ST_RX_START_INT_ST = 0x1 + // Position of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Pos = 0x1 + // Bit mask of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Msk = 0x2 + // Bit TX_START_INT_ST. + UHCI_INT_ST_TX_START_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + UHCI_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + UHCI_INT_ST_TX_HUNG_INT_ST = 0x8 + // Position of IN_DONE_INT_ST field. + UHCI_INT_ST_IN_DONE_INT_ST_Pos = 0x4 + // Bit mask of IN_DONE_INT_ST field. + UHCI_INT_ST_IN_DONE_INT_ST_Msk = 0x10 + // Bit IN_DONE_INT_ST. + UHCI_INT_ST_IN_DONE_INT_ST = 0x10 + // Position of IN_SUC_EOF_INT_ST field. + UHCI_INT_ST_IN_SUC_EOF_INT_ST_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_ST field. + UHCI_INT_ST_IN_SUC_EOF_INT_ST_Msk = 0x20 + // Bit IN_SUC_EOF_INT_ST. + UHCI_INT_ST_IN_SUC_EOF_INT_ST = 0x20 + // Position of IN_ERR_EOF_INT_ST field. + UHCI_INT_ST_IN_ERR_EOF_INT_ST_Pos = 0x6 + // Bit mask of IN_ERR_EOF_INT_ST field. + UHCI_INT_ST_IN_ERR_EOF_INT_ST_Msk = 0x40 + // Bit IN_ERR_EOF_INT_ST. + UHCI_INT_ST_IN_ERR_EOF_INT_ST = 0x40 + // Position of OUT_DONE_INT_ST field. + UHCI_INT_ST_OUT_DONE_INT_ST_Pos = 0x7 + // Bit mask of OUT_DONE_INT_ST field. + UHCI_INT_ST_OUT_DONE_INT_ST_Msk = 0x80 + // Bit OUT_DONE_INT_ST. + UHCI_INT_ST_OUT_DONE_INT_ST = 0x80 + // Position of OUT_EOF_INT_ST field. + UHCI_INT_ST_OUT_EOF_INT_ST_Pos = 0x8 + // Bit mask of OUT_EOF_INT_ST field. + UHCI_INT_ST_OUT_EOF_INT_ST_Msk = 0x100 + // Bit OUT_EOF_INT_ST. + UHCI_INT_ST_OUT_EOF_INT_ST = 0x100 + // Position of IN_DSCR_ERR_INT_ST field. + UHCI_INT_ST_IN_DSCR_ERR_INT_ST_Pos = 0x9 + // Bit mask of IN_DSCR_ERR_INT_ST field. + UHCI_INT_ST_IN_DSCR_ERR_INT_ST_Msk = 0x200 + // Bit IN_DSCR_ERR_INT_ST. + UHCI_INT_ST_IN_DSCR_ERR_INT_ST = 0x200 + // Position of OUT_DSCR_ERR_INT_ST field. + UHCI_INT_ST_OUT_DSCR_ERR_INT_ST_Pos = 0xa + // Bit mask of OUT_DSCR_ERR_INT_ST field. + UHCI_INT_ST_OUT_DSCR_ERR_INT_ST_Msk = 0x400 + // Bit OUT_DSCR_ERR_INT_ST. + UHCI_INT_ST_OUT_DSCR_ERR_INT_ST = 0x400 + // Position of IN_DSCR_EMPTY_INT_ST field. + UHCI_INT_ST_IN_DSCR_EMPTY_INT_ST_Pos = 0xb + // Bit mask of IN_DSCR_EMPTY_INT_ST field. + UHCI_INT_ST_IN_DSCR_EMPTY_INT_ST_Msk = 0x800 + // Bit IN_DSCR_EMPTY_INT_ST. + UHCI_INT_ST_IN_DSCR_EMPTY_INT_ST = 0x800 + // Position of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Pos = 0xc + // Bit mask of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Msk = 0x1000 + // Bit OUTLINK_EOF_ERR_INT_ST. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST = 0x1000 + // Position of OUT_TOTAL_EOF_INT_ST field. + UHCI_INT_ST_OUT_TOTAL_EOF_INT_ST_Pos = 0xd + // Bit mask of OUT_TOTAL_EOF_INT_ST field. + UHCI_INT_ST_OUT_TOTAL_EOF_INT_ST_Msk = 0x2000 + // Bit OUT_TOTAL_EOF_INT_ST. + UHCI_INT_ST_OUT_TOTAL_EOF_INT_ST = 0x2000 + // Position of SEND_S_Q_INT_ST field. + UHCI_INT_ST_SEND_S_Q_INT_ST_Pos = 0xe + // Bit mask of SEND_S_Q_INT_ST field. + UHCI_INT_ST_SEND_S_Q_INT_ST_Msk = 0x4000 + // Bit SEND_S_Q_INT_ST. + UHCI_INT_ST_SEND_S_Q_INT_ST = 0x4000 + // Position of SEND_A_Q_INT_ST field. + UHCI_INT_ST_SEND_A_Q_INT_ST_Pos = 0xf + // Bit mask of SEND_A_Q_INT_ST field. + UHCI_INT_ST_SEND_A_Q_INT_ST_Msk = 0x8000 + // Bit SEND_A_Q_INT_ST. + UHCI_INT_ST_SEND_A_Q_INT_ST = 0x8000 + // Position of DMA_INFIFO_FULL_WM_INT_ST field. + UHCI_INT_ST_DMA_INFIFO_FULL_WM_INT_ST_Pos = 0x10 + // Bit mask of DMA_INFIFO_FULL_WM_INT_ST field. + UHCI_INT_ST_DMA_INFIFO_FULL_WM_INT_ST_Msk = 0x10000 + // Bit DMA_INFIFO_FULL_WM_INT_ST. + UHCI_INT_ST_DMA_INFIFO_FULL_WM_INT_ST = 0x10000 + + // INT_ENA + // Position of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Pos = 0x0 + // Bit mask of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Msk = 0x1 + // Bit RX_START_INT_ENA. + UHCI_INT_ENA_RX_START_INT_ENA = 0x1 + // Position of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Pos = 0x1 + // Bit mask of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Msk = 0x2 + // Bit TX_START_INT_ENA. + UHCI_INT_ENA_TX_START_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + UHCI_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + UHCI_INT_ENA_TX_HUNG_INT_ENA = 0x8 + // Position of IN_DONE_INT_ENA field. + UHCI_INT_ENA_IN_DONE_INT_ENA_Pos = 0x4 + // Bit mask of IN_DONE_INT_ENA field. + UHCI_INT_ENA_IN_DONE_INT_ENA_Msk = 0x10 + // Bit IN_DONE_INT_ENA. + UHCI_INT_ENA_IN_DONE_INT_ENA = 0x10 + // Position of IN_SUC_EOF_INT_ENA field. + UHCI_INT_ENA_IN_SUC_EOF_INT_ENA_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_ENA field. + UHCI_INT_ENA_IN_SUC_EOF_INT_ENA_Msk = 0x20 + // Bit IN_SUC_EOF_INT_ENA. + UHCI_INT_ENA_IN_SUC_EOF_INT_ENA = 0x20 + // Position of IN_ERR_EOF_INT_ENA field. + UHCI_INT_ENA_IN_ERR_EOF_INT_ENA_Pos = 0x6 + // Bit mask of IN_ERR_EOF_INT_ENA field. + UHCI_INT_ENA_IN_ERR_EOF_INT_ENA_Msk = 0x40 + // Bit IN_ERR_EOF_INT_ENA. + UHCI_INT_ENA_IN_ERR_EOF_INT_ENA = 0x40 + // Position of OUT_DONE_INT_ENA field. + UHCI_INT_ENA_OUT_DONE_INT_ENA_Pos = 0x7 + // Bit mask of OUT_DONE_INT_ENA field. + UHCI_INT_ENA_OUT_DONE_INT_ENA_Msk = 0x80 + // Bit OUT_DONE_INT_ENA. + UHCI_INT_ENA_OUT_DONE_INT_ENA = 0x80 + // Position of OUT_EOF_INT_ENA field. + UHCI_INT_ENA_OUT_EOF_INT_ENA_Pos = 0x8 + // Bit mask of OUT_EOF_INT_ENA field. + UHCI_INT_ENA_OUT_EOF_INT_ENA_Msk = 0x100 + // Bit OUT_EOF_INT_ENA. + UHCI_INT_ENA_OUT_EOF_INT_ENA = 0x100 + // Position of IN_DSCR_ERR_INT_ENA field. + UHCI_INT_ENA_IN_DSCR_ERR_INT_ENA_Pos = 0x9 + // Bit mask of IN_DSCR_ERR_INT_ENA field. + UHCI_INT_ENA_IN_DSCR_ERR_INT_ENA_Msk = 0x200 + // Bit IN_DSCR_ERR_INT_ENA. + UHCI_INT_ENA_IN_DSCR_ERR_INT_ENA = 0x200 + // Position of OUT_DSCR_ERR_INT_ENA field. + UHCI_INT_ENA_OUT_DSCR_ERR_INT_ENA_Pos = 0xa + // Bit mask of OUT_DSCR_ERR_INT_ENA field. + UHCI_INT_ENA_OUT_DSCR_ERR_INT_ENA_Msk = 0x400 + // Bit OUT_DSCR_ERR_INT_ENA. + UHCI_INT_ENA_OUT_DSCR_ERR_INT_ENA = 0x400 + // Position of IN_DSCR_EMPTY_INT_ENA field. + UHCI_INT_ENA_IN_DSCR_EMPTY_INT_ENA_Pos = 0xb + // Bit mask of IN_DSCR_EMPTY_INT_ENA field. + UHCI_INT_ENA_IN_DSCR_EMPTY_INT_ENA_Msk = 0x800 + // Bit IN_DSCR_EMPTY_INT_ENA. + UHCI_INT_ENA_IN_DSCR_EMPTY_INT_ENA = 0x800 + // Position of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Pos = 0xc + // Bit mask of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Msk = 0x1000 + // Bit OUTLINK_EOF_ERR_INT_ENA. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA = 0x1000 + // Position of OUT_TOTAL_EOF_INT_ENA field. + UHCI_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Pos = 0xd + // Bit mask of OUT_TOTAL_EOF_INT_ENA field. + UHCI_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Msk = 0x2000 + // Bit OUT_TOTAL_EOF_INT_ENA. + UHCI_INT_ENA_OUT_TOTAL_EOF_INT_ENA = 0x2000 + // Position of SEND_S_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_Q_INT_ENA_Pos = 0xe + // Bit mask of SEND_S_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_Q_INT_ENA_Msk = 0x4000 + // Bit SEND_S_Q_INT_ENA. + UHCI_INT_ENA_SEND_S_Q_INT_ENA = 0x4000 + // Position of SEND_A_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_Q_INT_ENA_Pos = 0xf + // Bit mask of SEND_A_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_Q_INT_ENA_Msk = 0x8000 + // Bit SEND_A_Q_INT_ENA. + UHCI_INT_ENA_SEND_A_Q_INT_ENA = 0x8000 + // Position of DMA_INFIFO_FULL_WM_INT_ENA field. + UHCI_INT_ENA_DMA_INFIFO_FULL_WM_INT_ENA_Pos = 0x10 + // Bit mask of DMA_INFIFO_FULL_WM_INT_ENA field. + UHCI_INT_ENA_DMA_INFIFO_FULL_WM_INT_ENA_Msk = 0x10000 + // Bit DMA_INFIFO_FULL_WM_INT_ENA. + UHCI_INT_ENA_DMA_INFIFO_FULL_WM_INT_ENA = 0x10000 + + // INT_CLR + // Position of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Pos = 0x0 + // Bit mask of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Msk = 0x1 + // Bit RX_START_INT_CLR. + UHCI_INT_CLR_RX_START_INT_CLR = 0x1 + // Position of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Pos = 0x1 + // Bit mask of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Msk = 0x2 + // Bit TX_START_INT_CLR. + UHCI_INT_CLR_TX_START_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + UHCI_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + UHCI_INT_CLR_TX_HUNG_INT_CLR = 0x8 + // Position of IN_DONE_INT_CLR field. + UHCI_INT_CLR_IN_DONE_INT_CLR_Pos = 0x4 + // Bit mask of IN_DONE_INT_CLR field. + UHCI_INT_CLR_IN_DONE_INT_CLR_Msk = 0x10 + // Bit IN_DONE_INT_CLR. + UHCI_INT_CLR_IN_DONE_INT_CLR = 0x10 + // Position of IN_SUC_EOF_INT_CLR field. + UHCI_INT_CLR_IN_SUC_EOF_INT_CLR_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_CLR field. + UHCI_INT_CLR_IN_SUC_EOF_INT_CLR_Msk = 0x20 + // Bit IN_SUC_EOF_INT_CLR. + UHCI_INT_CLR_IN_SUC_EOF_INT_CLR = 0x20 + // Position of IN_ERR_EOF_INT_CLR field. + UHCI_INT_CLR_IN_ERR_EOF_INT_CLR_Pos = 0x6 + // Bit mask of IN_ERR_EOF_INT_CLR field. + UHCI_INT_CLR_IN_ERR_EOF_INT_CLR_Msk = 0x40 + // Bit IN_ERR_EOF_INT_CLR. + UHCI_INT_CLR_IN_ERR_EOF_INT_CLR = 0x40 + // Position of OUT_DONE_INT_CLR field. + UHCI_INT_CLR_OUT_DONE_INT_CLR_Pos = 0x7 + // Bit mask of OUT_DONE_INT_CLR field. + UHCI_INT_CLR_OUT_DONE_INT_CLR_Msk = 0x80 + // Bit OUT_DONE_INT_CLR. + UHCI_INT_CLR_OUT_DONE_INT_CLR = 0x80 + // Position of OUT_EOF_INT_CLR field. + UHCI_INT_CLR_OUT_EOF_INT_CLR_Pos = 0x8 + // Bit mask of OUT_EOF_INT_CLR field. + UHCI_INT_CLR_OUT_EOF_INT_CLR_Msk = 0x100 + // Bit OUT_EOF_INT_CLR. + UHCI_INT_CLR_OUT_EOF_INT_CLR = 0x100 + // Position of IN_DSCR_ERR_INT_CLR field. + UHCI_INT_CLR_IN_DSCR_ERR_INT_CLR_Pos = 0x9 + // Bit mask of IN_DSCR_ERR_INT_CLR field. + UHCI_INT_CLR_IN_DSCR_ERR_INT_CLR_Msk = 0x200 + // Bit IN_DSCR_ERR_INT_CLR. + UHCI_INT_CLR_IN_DSCR_ERR_INT_CLR = 0x200 + // Position of OUT_DSCR_ERR_INT_CLR field. + UHCI_INT_CLR_OUT_DSCR_ERR_INT_CLR_Pos = 0xa + // Bit mask of OUT_DSCR_ERR_INT_CLR field. + UHCI_INT_CLR_OUT_DSCR_ERR_INT_CLR_Msk = 0x400 + // Bit OUT_DSCR_ERR_INT_CLR. + UHCI_INT_CLR_OUT_DSCR_ERR_INT_CLR = 0x400 + // Position of IN_DSCR_EMPTY_INT_CLR field. + UHCI_INT_CLR_IN_DSCR_EMPTY_INT_CLR_Pos = 0xb + // Bit mask of IN_DSCR_EMPTY_INT_CLR field. + UHCI_INT_CLR_IN_DSCR_EMPTY_INT_CLR_Msk = 0x800 + // Bit IN_DSCR_EMPTY_INT_CLR. + UHCI_INT_CLR_IN_DSCR_EMPTY_INT_CLR = 0x800 + // Position of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Pos = 0xc + // Bit mask of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Msk = 0x1000 + // Bit OUTLINK_EOF_ERR_INT_CLR. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR = 0x1000 + // Position of OUT_TOTAL_EOF_INT_CLR field. + UHCI_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Pos = 0xd + // Bit mask of OUT_TOTAL_EOF_INT_CLR field. + UHCI_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Msk = 0x2000 + // Bit OUT_TOTAL_EOF_INT_CLR. + UHCI_INT_CLR_OUT_TOTAL_EOF_INT_CLR = 0x2000 + // Position of SEND_S_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_Q_INT_CLR_Pos = 0xe + // Bit mask of SEND_S_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_Q_INT_CLR_Msk = 0x4000 + // Bit SEND_S_Q_INT_CLR. + UHCI_INT_CLR_SEND_S_Q_INT_CLR = 0x4000 + // Position of SEND_A_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_Q_INT_CLR_Pos = 0xf + // Bit mask of SEND_A_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_Q_INT_CLR_Msk = 0x8000 + // Bit SEND_A_Q_INT_CLR. + UHCI_INT_CLR_SEND_A_Q_INT_CLR = 0x8000 + // Position of DMA_INFIFO_FULL_WM_INT_CLR field. + UHCI_INT_CLR_DMA_INFIFO_FULL_WM_INT_CLR_Pos = 0x10 + // Bit mask of DMA_INFIFO_FULL_WM_INT_CLR field. + UHCI_INT_CLR_DMA_INFIFO_FULL_WM_INT_CLR_Msk = 0x10000 + // Bit DMA_INFIFO_FULL_WM_INT_CLR. + UHCI_INT_CLR_DMA_INFIFO_FULL_WM_INT_CLR = 0x10000 + + // DMA_OUT_STATUS + // Position of OUT_FULL field. + UHCI_DMA_OUT_STATUS_OUT_FULL_Pos = 0x0 + // Bit mask of OUT_FULL field. + UHCI_DMA_OUT_STATUS_OUT_FULL_Msk = 0x1 + // Bit OUT_FULL. + UHCI_DMA_OUT_STATUS_OUT_FULL = 0x1 + // Position of OUT_EMPTY field. + UHCI_DMA_OUT_STATUS_OUT_EMPTY_Pos = 0x1 + // Bit mask of OUT_EMPTY field. + UHCI_DMA_OUT_STATUS_OUT_EMPTY_Msk = 0x2 + // Bit OUT_EMPTY. + UHCI_DMA_OUT_STATUS_OUT_EMPTY = 0x2 + + // DMA_OUT_PUSH + // Position of OUTFIFO_WDATA field. + UHCI_DMA_OUT_PUSH_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + UHCI_DMA_OUT_PUSH_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + UHCI_DMA_OUT_PUSH_OUTFIFO_PUSH_Pos = 0x10 + // Bit mask of OUTFIFO_PUSH field. + UHCI_DMA_OUT_PUSH_OUTFIFO_PUSH_Msk = 0x10000 + // Bit OUTFIFO_PUSH. + UHCI_DMA_OUT_PUSH_OUTFIFO_PUSH = 0x10000 + + // DMA_IN_STATUS + // Position of IN_FULL field. + UHCI_DMA_IN_STATUS_IN_FULL_Pos = 0x0 + // Bit mask of IN_FULL field. + UHCI_DMA_IN_STATUS_IN_FULL_Msk = 0x1 + // Bit IN_FULL. + UHCI_DMA_IN_STATUS_IN_FULL = 0x1 + // Position of IN_EMPTY field. + UHCI_DMA_IN_STATUS_IN_EMPTY_Pos = 0x1 + // Bit mask of IN_EMPTY field. + UHCI_DMA_IN_STATUS_IN_EMPTY_Msk = 0x2 + // Bit IN_EMPTY. + UHCI_DMA_IN_STATUS_IN_EMPTY = 0x2 + // Position of RX_ERR_CAUSE field. + UHCI_DMA_IN_STATUS_RX_ERR_CAUSE_Pos = 0x4 + // Bit mask of RX_ERR_CAUSE field. + UHCI_DMA_IN_STATUS_RX_ERR_CAUSE_Msk = 0x70 + + // DMA_IN_POP + // Position of INFIFO_RDATA field. + UHCI_DMA_IN_POP_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + UHCI_DMA_IN_POP_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + UHCI_DMA_IN_POP_INFIFO_POP_Pos = 0x10 + // Bit mask of INFIFO_POP field. + UHCI_DMA_IN_POP_INFIFO_POP_Msk = 0x10000 + // Bit INFIFO_POP. + UHCI_DMA_IN_POP_INFIFO_POP = 0x10000 + + // DMA_OUT_LINK + // Position of OUTLINK_ADDR field. + UHCI_DMA_OUT_LINK_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + UHCI_DMA_OUT_LINK_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + UHCI_DMA_OUT_LINK_OUTLINK_STOP_Pos = 0x1c + // Bit mask of OUTLINK_STOP field. + UHCI_DMA_OUT_LINK_OUTLINK_STOP_Msk = 0x10000000 + // Bit OUTLINK_STOP. + UHCI_DMA_OUT_LINK_OUTLINK_STOP = 0x10000000 + // Position of OUTLINK_START field. + UHCI_DMA_OUT_LINK_OUTLINK_START_Pos = 0x1d + // Bit mask of OUTLINK_START field. + UHCI_DMA_OUT_LINK_OUTLINK_START_Msk = 0x20000000 + // Bit OUTLINK_START. + UHCI_DMA_OUT_LINK_OUTLINK_START = 0x20000000 + // Position of OUTLINK_RESTART field. + UHCI_DMA_OUT_LINK_OUTLINK_RESTART_Pos = 0x1e + // Bit mask of OUTLINK_RESTART field. + UHCI_DMA_OUT_LINK_OUTLINK_RESTART_Msk = 0x40000000 + // Bit OUTLINK_RESTART. + UHCI_DMA_OUT_LINK_OUTLINK_RESTART = 0x40000000 + // Position of OUTLINK_PARK field. + UHCI_DMA_OUT_LINK_OUTLINK_PARK_Pos = 0x1f + // Bit mask of OUTLINK_PARK field. + UHCI_DMA_OUT_LINK_OUTLINK_PARK_Msk = 0x80000000 + // Bit OUTLINK_PARK. + UHCI_DMA_OUT_LINK_OUTLINK_PARK = 0x80000000 + + // DMA_IN_LINK + // Position of INLINK_ADDR field. + UHCI_DMA_IN_LINK_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + UHCI_DMA_IN_LINK_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + UHCI_DMA_IN_LINK_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + UHCI_DMA_IN_LINK_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + UHCI_DMA_IN_LINK_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + UHCI_DMA_IN_LINK_INLINK_STOP_Pos = 0x1c + // Bit mask of INLINK_STOP field. + UHCI_DMA_IN_LINK_INLINK_STOP_Msk = 0x10000000 + // Bit INLINK_STOP. + UHCI_DMA_IN_LINK_INLINK_STOP = 0x10000000 + // Position of INLINK_START field. + UHCI_DMA_IN_LINK_INLINK_START_Pos = 0x1d + // Bit mask of INLINK_START field. + UHCI_DMA_IN_LINK_INLINK_START_Msk = 0x20000000 + // Bit INLINK_START. + UHCI_DMA_IN_LINK_INLINK_START = 0x20000000 + // Position of INLINK_RESTART field. + UHCI_DMA_IN_LINK_INLINK_RESTART_Pos = 0x1e + // Bit mask of INLINK_RESTART field. + UHCI_DMA_IN_LINK_INLINK_RESTART_Msk = 0x40000000 + // Bit INLINK_RESTART. + UHCI_DMA_IN_LINK_INLINK_RESTART = 0x40000000 + // Position of INLINK_PARK field. + UHCI_DMA_IN_LINK_INLINK_PARK_Pos = 0x1f + // Bit mask of INLINK_PARK field. + UHCI_DMA_IN_LINK_INLINK_PARK_Msk = 0x80000000 + // Bit INLINK_PARK. + UHCI_DMA_IN_LINK_INLINK_PARK = 0x80000000 + + // CONF1 + // Position of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Pos = 0x0 + // Bit mask of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Msk = 0x1 + // Bit CHECK_SUM_EN. + UHCI_CONF1_CHECK_SUM_EN = 0x1 + // Position of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Pos = 0x1 + // Bit mask of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Msk = 0x2 + // Bit CHECK_SEQ_EN. + UHCI_CONF1_CHECK_SEQ_EN = 0x2 + // Position of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Pos = 0x2 + // Bit mask of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Msk = 0x4 + // Bit CRC_DISABLE. + UHCI_CONF1_CRC_DISABLE = 0x4 + // Position of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Pos = 0x3 + // Bit mask of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Msk = 0x8 + // Bit SAVE_HEAD. + UHCI_CONF1_SAVE_HEAD = 0x8 + // Position of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Pos = 0x4 + // Bit mask of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Msk = 0x10 + // Bit TX_CHECK_SUM_RE. + UHCI_CONF1_TX_CHECK_SUM_RE = 0x10 + // Position of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Pos = 0x5 + // Bit mask of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Msk = 0x20 + // Bit TX_ACK_NUM_RE. + UHCI_CONF1_TX_ACK_NUM_RE = 0x20 + // Position of CHECK_OWNER field. + UHCI_CONF1_CHECK_OWNER_Pos = 0x6 + // Bit mask of CHECK_OWNER field. + UHCI_CONF1_CHECK_OWNER_Msk = 0x40 + // Bit CHECK_OWNER. + UHCI_CONF1_CHECK_OWNER = 0x40 + // Position of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Pos = 0x7 + // Bit mask of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Msk = 0x80 + // Bit WAIT_SW_START. + UHCI_CONF1_WAIT_SW_START = 0x80 + // Position of SW_START field. + UHCI_CONF1_SW_START_Pos = 0x8 + // Bit mask of SW_START field. + UHCI_CONF1_SW_START_Msk = 0x100 + // Bit SW_START. + UHCI_CONF1_SW_START = 0x100 + // Position of DMA_INFIFO_FULL_THRS field. + UHCI_CONF1_DMA_INFIFO_FULL_THRS_Pos = 0x9 + // Bit mask of DMA_INFIFO_FULL_THRS field. + UHCI_CONF1_DMA_INFIFO_FULL_THRS_Msk = 0x1ffe00 + + // STATE0 + // Position of STATE0 field. + UHCI_STATE0_STATE0_Pos = 0x0 + // Bit mask of STATE0 field. + UHCI_STATE0_STATE0_Msk = 0xffffffff + + // STATE1 + // Position of STATE1 field. + UHCI_STATE1_STATE1_Pos = 0x0 + // Bit mask of STATE1 field. + UHCI_STATE1_STATE1_Msk = 0xffffffff + + // DMA_OUT_EOF_DES_ADDR + // Position of OUT_EOF_DES_ADDR field. + UHCI_DMA_OUT_EOF_DES_ADDR_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + UHCI_DMA_OUT_EOF_DES_ADDR_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // DMA_IN_SUC_EOF_DES_ADDR + // Position of IN_SUC_EOF_DES_ADDR field. + UHCI_DMA_IN_SUC_EOF_DES_ADDR_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + UHCI_DMA_IN_SUC_EOF_DES_ADDR_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // DMA_IN_ERR_EOF_DES_ADDR + // Position of IN_ERR_EOF_DES_ADDR field. + UHCI_DMA_IN_ERR_EOF_DES_ADDR_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR field. + UHCI_DMA_IN_ERR_EOF_DES_ADDR_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // DMA_OUT_EOF_BFR_DES_ADDR + // Position of OUT_EOF_BFR_DES_ADDR field. + UHCI_DMA_OUT_EOF_BFR_DES_ADDR_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + UHCI_DMA_OUT_EOF_BFR_DES_ADDR_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // AHB_TEST + // Position of AHB_TESTMODE field. + UHCI_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + UHCI_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + UHCI_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + UHCI_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // DMA_IN_DSCR + // Position of INLINK_DSCR field. + UHCI_DMA_IN_DSCR_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + UHCI_DMA_IN_DSCR_INLINK_DSCR_Msk = 0xffffffff + + // DMA_IN_DSCR_BF0 + // Position of INLINK_DSCR_BF0 field. + UHCI_DMA_IN_DSCR_BF0_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + UHCI_DMA_IN_DSCR_BF0_INLINK_DSCR_BF0_Msk = 0xffffffff + + // DMA_IN_DSCR_BF1 + // Position of INLINK_DSCR_BF1 field. + UHCI_DMA_IN_DSCR_BF1_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + UHCI_DMA_IN_DSCR_BF1_INLINK_DSCR_BF1_Msk = 0xffffffff + + // DMA_OUT_DSCR + // Position of OUTLINK_DSCR field. + UHCI_DMA_OUT_DSCR_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + UHCI_DMA_OUT_DSCR_OUTLINK_DSCR_Msk = 0xffffffff + + // DMA_OUT_DSCR_BF0 + // Position of OUTLINK_DSCR_BF0 field. + UHCI_DMA_OUT_DSCR_BF0_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + UHCI_DMA_OUT_DSCR_BF0_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // DMA_OUT_DSCR_BF1 + // Position of OUTLINK_DSCR_BF1 field. + UHCI_DMA_OUT_DSCR_BF1_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + UHCI_DMA_OUT_DSCR_BF1_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // ESCAPE_CONF + // Position of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Pos = 0x0 + // Bit mask of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Msk = 0x1 + // Bit TX_C0_ESC_EN. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN = 0x1 + // Position of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Pos = 0x1 + // Bit mask of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Msk = 0x2 + // Bit TX_DB_ESC_EN. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN = 0x2 + // Position of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Pos = 0x2 + // Bit mask of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Msk = 0x4 + // Bit TX_11_ESC_EN. + UHCI_ESCAPE_CONF_TX_11_ESC_EN = 0x4 + // Position of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Pos = 0x3 + // Bit mask of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Msk = 0x8 + // Bit TX_13_ESC_EN. + UHCI_ESCAPE_CONF_TX_13_ESC_EN = 0x8 + // Position of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Pos = 0x4 + // Bit mask of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Msk = 0x10 + // Bit RX_C0_ESC_EN. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN = 0x10 + // Position of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Pos = 0x5 + // Bit mask of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Msk = 0x20 + // Bit RX_DB_ESC_EN. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN = 0x20 + // Position of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Pos = 0x6 + // Bit mask of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Msk = 0x40 + // Bit RX_11_ESC_EN. + UHCI_ESCAPE_CONF_RX_11_ESC_EN = 0x40 + // Position of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Pos = 0x7 + // Bit mask of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Msk = 0x80 + // Bit RX_13_ESC_EN. + UHCI_ESCAPE_CONF_RX_13_ESC_EN = 0x80 + + // HUNG_CONF + // Position of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Pos = 0x0 + // Bit mask of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Msk = 0xff + // Position of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit TXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA = 0x800 + // Position of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Pos = 0xc + // Bit mask of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Msk = 0xff000 + // Position of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Pos = 0x14 + // Bit mask of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Msk = 0x700000 + // Position of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Pos = 0x17 + // Bit mask of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Msk = 0x800000 + // Bit RXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA = 0x800000 + + // RX_HEAD + // Position of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Pos = 0x0 + // Bit mask of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Msk = 0xffffffff + + // QUICK_SENT + // Position of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Pos = 0x0 + // Bit mask of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Msk = 0x7 + // Position of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Pos = 0x3 + // Bit mask of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Msk = 0x8 + // Bit SINGLE_SEND_EN. + UHCI_QUICK_SENT_SINGLE_SEND_EN = 0x8 + // Position of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Pos = 0x4 + // Bit mask of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Msk = 0x70 + // Position of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Pos = 0x7 + // Bit mask of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Msk = 0x80 + // Bit ALWAYS_SEND_EN. + UHCI_QUICK_SENT_ALWAYS_SEND_EN = 0x80 + + // Q0_WORD0 + // Position of SEND_Q0_WORD0 field. + UHCI_Q0_WORD0_SEND_Q0_WORD0_Pos = 0x0 + // Bit mask of SEND_Q0_WORD0 field. + UHCI_Q0_WORD0_SEND_Q0_WORD0_Msk = 0xffffffff + + // Q0_WORD1 + // Position of SEND_Q0_WORD1 field. + UHCI_Q0_WORD1_SEND_Q0_WORD1_Pos = 0x0 + // Bit mask of SEND_Q0_WORD1 field. + UHCI_Q0_WORD1_SEND_Q0_WORD1_Msk = 0xffffffff + + // Q1_WORD0 + // Position of SEND_Q1_WORD0 field. + UHCI_Q1_WORD0_SEND_Q1_WORD0_Pos = 0x0 + // Bit mask of SEND_Q1_WORD0 field. + UHCI_Q1_WORD0_SEND_Q1_WORD0_Msk = 0xffffffff + + // Q1_WORD1 + // Position of SEND_Q1_WORD1 field. + UHCI_Q1_WORD1_SEND_Q1_WORD1_Pos = 0x0 + // Bit mask of SEND_Q1_WORD1 field. + UHCI_Q1_WORD1_SEND_Q1_WORD1_Msk = 0xffffffff + + // Q2_WORD0 + // Position of SEND_Q2_WORD0 field. + UHCI_Q2_WORD0_SEND_Q2_WORD0_Pos = 0x0 + // Bit mask of SEND_Q2_WORD0 field. + UHCI_Q2_WORD0_SEND_Q2_WORD0_Msk = 0xffffffff + + // Q2_WORD1 + // Position of SEND_Q2_WORD1 field. + UHCI_Q2_WORD1_SEND_Q2_WORD1_Pos = 0x0 + // Bit mask of SEND_Q2_WORD1 field. + UHCI_Q2_WORD1_SEND_Q2_WORD1_Msk = 0xffffffff + + // Q3_WORD0 + // Position of SEND_Q3_WORD0 field. + UHCI_Q3_WORD0_SEND_Q3_WORD0_Pos = 0x0 + // Bit mask of SEND_Q3_WORD0 field. + UHCI_Q3_WORD0_SEND_Q3_WORD0_Msk = 0xffffffff + + // Q3_WORD1 + // Position of SEND_Q3_WORD1 field. + UHCI_Q3_WORD1_SEND_Q3_WORD1_Pos = 0x0 + // Bit mask of SEND_Q3_WORD1 field. + UHCI_Q3_WORD1_SEND_Q3_WORD1_Msk = 0xffffffff + + // Q4_WORD0 + // Position of SEND_Q4_WORD0 field. + UHCI_Q4_WORD0_SEND_Q4_WORD0_Pos = 0x0 + // Bit mask of SEND_Q4_WORD0 field. + UHCI_Q4_WORD0_SEND_Q4_WORD0_Msk = 0xffffffff + + // Q4_WORD1 + // Position of SEND_Q4_WORD1 field. + UHCI_Q4_WORD1_SEND_Q4_WORD1_Pos = 0x0 + // Bit mask of SEND_Q4_WORD1 field. + UHCI_Q4_WORD1_SEND_Q4_WORD1_Msk = 0xffffffff + + // Q5_WORD0 + // Position of SEND_Q5_WORD0 field. + UHCI_Q5_WORD0_SEND_Q5_WORD0_Pos = 0x0 + // Bit mask of SEND_Q5_WORD0 field. + UHCI_Q5_WORD0_SEND_Q5_WORD0_Msk = 0xffffffff + + // Q5_WORD1 + // Position of SEND_Q5_WORD1 field. + UHCI_Q5_WORD1_SEND_Q5_WORD1_Pos = 0x0 + // Bit mask of SEND_Q5_WORD1 field. + UHCI_Q5_WORD1_SEND_Q5_WORD1_Msk = 0xffffffff + + // Q6_WORD0 + // Position of SEND_Q6_WORD0 field. + UHCI_Q6_WORD0_SEND_Q6_WORD0_Pos = 0x0 + // Bit mask of SEND_Q6_WORD0 field. + UHCI_Q6_WORD0_SEND_Q6_WORD0_Msk = 0xffffffff + + // Q6_WORD1 + // Position of SEND_Q6_WORD1 field. + UHCI_Q6_WORD1_SEND_Q6_WORD1_Pos = 0x0 + // Bit mask of SEND_Q6_WORD1 field. + UHCI_Q6_WORD1_SEND_Q6_WORD1_Msk = 0xffffffff + + // ESC_CONF0 + // Position of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Pos = 0x0 + // Bit mask of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Msk = 0xff + // Position of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Pos = 0x8 + // Bit mask of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Msk = 0xff00 + // Position of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Pos = 0x10 + // Bit mask of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Msk = 0xff0000 + + // ESC_CONF1 + // Position of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Pos = 0x0 + // Bit mask of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Msk = 0xff + // Position of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Msk = 0xff0000 + + // ESC_CONF2 + // Position of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Pos = 0x0 + // Bit mask of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Msk = 0xff + // Position of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Msk = 0xff0000 + + // ESC_CONF3 + // Position of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Pos = 0x0 + // Bit mask of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Msk = 0xff + // Position of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Msk = 0xff0000 + + // PKT_THRES + // Position of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Pos = 0x0 + // Bit mask of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Msk = 0x1fff + + // DATE + // Position of DATE field. + UHCI_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UHCI_DATE_DATE_Msk = 0xffffffff +) diff --git a/emb/device/esp/esp32c2.go b/emb/device/esp/esp32c2.go new file mode 100644 index 0000000..74a4181 --- /dev/null +++ b/emb/device/esp/esp32c2.go @@ -0,0 +1,34249 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32c2.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32c2 + +/* +// 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) +*/ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32-C2" + CPU = "RV32IMC" + FPUPresent = false + NVICPrioBits = 4 +) + +// Interrupt numbers. +const ( + // Interrupt Controller (Core 0) + IRQ_WIFI_MAC = 0 + + // Interrupt Controller (Core 0) + IRQ_WIFI_MAC_NMI = 1 + + // Interrupt Controller (Core 0) + IRQ_WIFI_PWR = 2 + + // Interrupt Controller (Core 0) + IRQ_WIFI_BB = 3 + + // Interrupt Controller (Core 0) + IRQ_BT_MAC = 4 + + // Interrupt Controller (Core 0) + IRQ_BT_BB = 5 + + // Interrupt Controller (Core 0) + IRQ_BT_BB_NMI = 6 + + // Interrupt Controller (Core 0) + IRQ_LP_TIMER = 7 + + // Interrupt Controller (Core 0) + IRQ_COEX = 8 + + // Interrupt Controller (Core 0) + IRQ_BLE_TIMER = 9 + + // Interrupt Controller (Core 0) + IRQ_BLE_SEC = 10 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_MST = 11 + + // APB (Advanced Peripheral Bus) Controller + IRQ_APB_CTRL = 12 + + // General Purpose Input/Output + IRQ_GPIO = 13 + + // General Purpose Input/Output + IRQ_GPIO_NMI = 14 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_SPI_INTR_1 = 15 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_SPI_INTR_2 = 16 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + IRQ_UART0 = 17 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + IRQ_UART1 = 18 + + // LED Control PWM (Pulse Width Modulation) + IRQ_LEDC = 19 + + // eFuse Controller + IRQ_EFUSE = 20 + + // Real-Time Clock Control + IRQ_RTC_CORE = 21 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_EXT0 = 22 + + // Timer Group 0 + IRQ_TG0_T0_LEVEL = 23 + + // Timer Group 0 + IRQ_TG0_WDT_LEVEL = 24 + + // Interrupt Controller (Core 0) + IRQ_CACHE_IA = 25 + + // System Timer + IRQ_SYSTIMER_TARGET0 = 26 + + // System Timer + IRQ_SYSTIMER_TARGET1 = 27 + + // System Timer + IRQ_SYSTIMER_TARGET2 = 28 + + // SPI (Serial Peripheral Interface) Controller 0 + IRQ_SPI_MEM_REJECT_CACHE = 29 + + // Interrupt Controller (Core 0) + IRQ_ICACHE_PRELOAD0 = 30 + + // Interrupt Controller (Core 0) + IRQ_ICACHE_SYNC0 = 31 + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + IRQ_APB_ADC = 32 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_CH0 = 33 + + // SHA (Secure Hash Algorithm) Accelerator + IRQ_SHA = 34 + + // Interrupt Controller (Core 0) + IRQ_ECC = 35 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR0 = 36 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR1 = 37 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR2 = 38 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR3 = 39 + + // Debug Assist + IRQ_ASSIST_DEBUG = 40 + + // Interrupt Controller (Core 0) + IRQ_ETS_CORE0_PIF_PMS_SIZE = 41 + + // Highest interrupt number on this device. + IRQ_max = 41 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_WIFI_MAC: + callHandlers(IRQ_WIFI_MAC) + case IRQ_WIFI_MAC_NMI: + callHandlers(IRQ_WIFI_MAC_NMI) + case IRQ_WIFI_PWR: + callHandlers(IRQ_WIFI_PWR) + case IRQ_WIFI_BB: + callHandlers(IRQ_WIFI_BB) + case IRQ_BT_MAC: + callHandlers(IRQ_BT_MAC) + case IRQ_BT_BB: + callHandlers(IRQ_BT_BB) + case IRQ_BT_BB_NMI: + callHandlers(IRQ_BT_BB_NMI) + case IRQ_LP_TIMER: + callHandlers(IRQ_LP_TIMER) + case IRQ_COEX: + callHandlers(IRQ_COEX) + case IRQ_BLE_TIMER: + callHandlers(IRQ_BLE_TIMER) + case IRQ_BLE_SEC: + callHandlers(IRQ_BLE_SEC) + case IRQ_I2C_MST: + callHandlers(IRQ_I2C_MST) + case IRQ_APB_CTRL: + callHandlers(IRQ_APB_CTRL) + case IRQ_GPIO: + callHandlers(IRQ_GPIO) + case IRQ_GPIO_NMI: + callHandlers(IRQ_GPIO_NMI) + case IRQ_SPI_INTR_1: + callHandlers(IRQ_SPI_INTR_1) + case IRQ_SPI_INTR_2: + callHandlers(IRQ_SPI_INTR_2) + case IRQ_UART0: + callHandlers(IRQ_UART0) + case IRQ_UART1: + callHandlers(IRQ_UART1) + case IRQ_LEDC: + callHandlers(IRQ_LEDC) + case IRQ_EFUSE: + callHandlers(IRQ_EFUSE) + case IRQ_RTC_CORE: + callHandlers(IRQ_RTC_CORE) + case IRQ_I2C_EXT0: + callHandlers(IRQ_I2C_EXT0) + case IRQ_TG0_T0_LEVEL: + callHandlers(IRQ_TG0_T0_LEVEL) + case IRQ_TG0_WDT_LEVEL: + callHandlers(IRQ_TG0_WDT_LEVEL) + case IRQ_CACHE_IA: + callHandlers(IRQ_CACHE_IA) + case IRQ_SYSTIMER_TARGET0: + callHandlers(IRQ_SYSTIMER_TARGET0) + case IRQ_SYSTIMER_TARGET1: + callHandlers(IRQ_SYSTIMER_TARGET1) + case IRQ_SYSTIMER_TARGET2: + callHandlers(IRQ_SYSTIMER_TARGET2) + case IRQ_SPI_MEM_REJECT_CACHE: + callHandlers(IRQ_SPI_MEM_REJECT_CACHE) + case IRQ_ICACHE_PRELOAD0: + callHandlers(IRQ_ICACHE_PRELOAD0) + case IRQ_ICACHE_SYNC0: + callHandlers(IRQ_ICACHE_SYNC0) + case IRQ_APB_ADC: + callHandlers(IRQ_APB_ADC) + case IRQ_DMA_CH0: + callHandlers(IRQ_DMA_CH0) + case IRQ_SHA: + callHandlers(IRQ_SHA) + case IRQ_ECC: + callHandlers(IRQ_ECC) + case IRQ_FROM_CPU_INTR0: + callHandlers(IRQ_FROM_CPU_INTR0) + case IRQ_FROM_CPU_INTR1: + callHandlers(IRQ_FROM_CPU_INTR1) + case IRQ_FROM_CPU_INTR2: + callHandlers(IRQ_FROM_CPU_INTR2) + case IRQ_FROM_CPU_INTR3: + callHandlers(IRQ_FROM_CPU_INTR3) + case IRQ_ASSIST_DEBUG: + callHandlers(IRQ_ASSIST_DEBUG) + case IRQ_ETS_CORE0_PIF_PMS_SIZE: + callHandlers(IRQ_ETS_CORE0_PIF_PMS_SIZE) + } +} + +// Peripherals. +var ( + // APB (Advanced Peripheral Bus) Controller + APB_CTRL = (*APB_CTRL_Type)(unsafe.Pointer(uintptr(0x60026000))) + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + APB_SARADC = (*APB_SARADC_Type)(unsafe.Pointer(uintptr(0x60040000))) + + // Debug Assist + ASSIST_DEBUG = (*ASSIST_DEBUG_Type)(unsafe.Pointer(uintptr(0x600ce000))) + + // BB Peripheral + BB = (*BB_Type)(unsafe.Pointer(uintptr(0x6001d000))) + + // DMA (Direct Memory Access) Controller + DMA = (*DMA_Type)(unsafe.Pointer(uintptr(0x6003f000))) + + // ECC (ECC Hardware Accelerator) + ECC = (*ECC_Type)(unsafe.Pointer(uintptr(0x6003e000))) + + // eFuse Controller + EFUSE = (*EFUSE_Type)(unsafe.Pointer(uintptr(0x60008800))) + + // External Memory + EXTMEM = (*EXTMEM_Type)(unsafe.Pointer(uintptr(0x600c4000))) + + // General Purpose Input/Output + GPIO = (*GPIO_Type)(unsafe.Pointer(uintptr(0x60004000))) + + // I2C (Inter-Integrated Circuit) Controller 0 + I2C0 = (*I2C_Type)(unsafe.Pointer(uintptr(0x60013000))) + + // Interrupt Controller (Core 0) + INTERRUPT_CORE0 = (*INTERRUPT_CORE0_Type)(unsafe.Pointer(uintptr(0x600c2000))) + + // Input/Output Multiplexer + IO_MUX = (*IO_MUX_Type)(unsafe.Pointer(uintptr(0x60009000))) + + // LED Control PWM (Pulse Width Modulation) + LEDC = (*LEDC_Type)(unsafe.Pointer(uintptr(0x60019000))) + + // MODEM_CLKRST Peripheral + MODEM_CLKRST = (*MODEM_CLKRST_Type)(unsafe.Pointer(uintptr(0x6004d800))) + + // Hardware Random Number Generator + RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x60026000))) + + // Real-Time Clock Control + RTC_CNTL = (*RTC_CNTL_Type)(unsafe.Pointer(uintptr(0x60008000))) + + // SENSITIVE Peripheral + SENSITIVE = (*SENSITIVE_Type)(unsafe.Pointer(uintptr(0x600c1000))) + + // SHA (Secure Hash Algorithm) Accelerator + SHA = (*SHA_Type)(unsafe.Pointer(uintptr(0x6003b000))) + + // SPI (Serial Peripheral Interface) Controller 0 + SPI0 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x60003000))) + + // SPI (Serial Peripheral Interface) Controller 1 + SPI1 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x60002000))) + + // SPI (Serial Peripheral Interface) Controller 2 + SPI2 = (*SPI2_Type)(unsafe.Pointer(uintptr(0x60024000))) + + // System Configuration Registers + SYSTEM = (*SYSTEM_Type)(unsafe.Pointer(uintptr(0x600c0000))) + + // System Timer + SYSTIMER = (*SYSTIMER_Type)(unsafe.Pointer(uintptr(0x60023000))) + + // Timer Group 0 + TIMG0 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x6001f000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART0 = (*UART_Type)(unsafe.Pointer(uintptr(0x60000000))) + + // XTS-AES-128 Flash Encryption + XTS_AES = (*XTS_AES_Type)(unsafe.Pointer(uintptr(0x600cc000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + UART1 = (*UART_Type)(unsafe.Pointer(uintptr(0x60010000))) +) + +// APB (Advanced Peripheral Bus) Controller +type APB_CTRL_Type struct { + SYSCLK_CONF volatile.Register32 // 0x0 + TICK_CONF volatile.Register32 // 0x4 + CLK_OUT_EN volatile.Register32 // 0x8 + WIFI_BB_CFG volatile.Register32 // 0xC + WIFI_BB_CFG_2 volatile.Register32 // 0x10 + WIFI_CLK_EN volatile.Register32 // 0x14 + WIFI_RST_EN volatile.Register32 // 0x18 + HOST_INF_SEL volatile.Register32 // 0x1C + EXT_MEM_PMS_LOCK volatile.Register32 // 0x20 + _ [4]byte + FLASH_ACE0_ATTR volatile.Register32 // 0x28 + FLASH_ACE1_ATTR volatile.Register32 // 0x2C + FLASH_ACE2_ATTR volatile.Register32 // 0x30 + FLASH_ACE3_ATTR volatile.Register32 // 0x34 + FLASH_ACE0_ADDR volatile.Register32 // 0x38 + FLASH_ACE1_ADDR volatile.Register32 // 0x3C + FLASH_ACE2_ADDR volatile.Register32 // 0x40 + FLASH_ACE3_ADDR volatile.Register32 // 0x44 + FLASH_ACE0_SIZE volatile.Register32 // 0x48 + FLASH_ACE1_SIZE volatile.Register32 // 0x4C + FLASH_ACE2_SIZE volatile.Register32 // 0x50 + FLASH_ACE3_SIZE volatile.Register32 // 0x54 + _ [48]byte + SPI_MEM_PMS_CTRL volatile.Register32 // 0x88 + SPI_MEM_REJECT_ADDR volatile.Register32 // 0x8C + SDIO_CTRL volatile.Register32 // 0x90 + REDCY_SIG0 volatile.Register32 // 0x94 + REDCY_SIG1 volatile.Register32 // 0x98 + FRONT_END_MEM_PD volatile.Register32 // 0x9C + RETENTION_CTRL volatile.Register32 // 0xA0 + CLKGATE_FORCE_ON volatile.Register32 // 0xA4 + MEM_POWER_DOWN volatile.Register32 // 0xA8 + MEM_POWER_UP volatile.Register32 // 0xAC + RND_DATA volatile.Register32 // 0xB0 + PERI_BACKUP_CONFIG volatile.Register32 // 0xB4 + PERI_BACKUP_APB_ADDR volatile.Register32 // 0xB8 + PERI_BACKUP_MEM_ADDR volatile.Register32 // 0xBC + PERI_BACKUP_INT_RAW volatile.Register32 // 0xC0 + PERI_BACKUP_INT_ST volatile.Register32 // 0xC4 + PERI_BACKUP_INT_ENA volatile.Register32 // 0xC8 + _ [4]byte + PERI_BACKUP_INT_CLR volatile.Register32 // 0xD0 + _ [808]byte + DATE volatile.Register32 // 0x3FC +} + +// APB_CTRL.SYSCLK_CONF: APB_CTRL_SYSCLK_CONF_REG +func (o *APB_CTRL_Type) SetSYSCLK_CONF_PRE_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x3ff)|value) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_PRE_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x3ff +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_CLK_320M_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_CLK_320M_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x400) >> 10 +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x800)|value<<11) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x800) >> 11 +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_RST_TICK_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_RST_TICK_CNT() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x1000) >> 12 +} + +// APB_CTRL.TICK_CONF: APB_CTRL_TICK_CONF_REG +func (o *APB_CTRL_Type) SetTICK_CONF_XTAL_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetTICK_CONF_XTAL_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.TICK_CONF.Reg) & 0xff +} +func (o *APB_CTRL_Type) SetTICK_CONF_CK8M_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *APB_CTRL_Type) GetTICK_CONF_CK8M_TICK_NUM() uint32 { + return (volatile.LoadUint32(&o.TICK_CONF.Reg) & 0xff00) >> 8 +} +func (o *APB_CTRL_Type) SetTICK_CONF_TICK_ENABLE(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *APB_CTRL_Type) GetTICK_CONF_TICK_ENABLE() uint32 { + return (volatile.LoadUint32(&o.TICK_CONF.Reg) & 0x10000) >> 16 +} + +// APB_CTRL.CLK_OUT_EN: APB_CTRL_CLK_OUT_EN_REG +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK20_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK20_OEN() uint32 { + return volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK22_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK22_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK44_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x4)|value<<2) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK44_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x4) >> 2 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x8)|value<<3) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x8) >> 3 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK80_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x10)|value<<4) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK80_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x10) >> 4 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK160_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x20)|value<<5) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK160_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x20) >> 5 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_320M_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x40)|value<<6) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_320M_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x40) >> 6 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_ADC_INF_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x80)|value<<7) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_ADC_INF_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x80) >> 7 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_DAC_CPU_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x100)|value<<8) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_DAC_CPU_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x100) >> 8 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK40X_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x200)|value<<9) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK40X_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x200) >> 9 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_XTAL_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x400)|value<<10) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_XTAL_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x400) >> 10 +} + +// APB_CTRL.WIFI_BB_CFG: APB_CTRL_WIFI_BB_CFG_REG +func (o *APB_CTRL_Type) SetWIFI_BB_CFG(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_BB_CFG() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG.Reg) +} + +// APB_CTRL.WIFI_BB_CFG_2: APB_CTRL_WIFI_BB_CFG_2_REG +func (o *APB_CTRL_Type) SetWIFI_BB_CFG_2(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG_2.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_BB_CFG_2() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG_2.Reg) +} + +// APB_CTRL.WIFI_CLK_EN: APB_CTRL_WIFI_CLK_EN_REG +func (o *APB_CTRL_Type) SetWIFI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_CLK_EN.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_CLK_EN.Reg) +} + +// APB_CTRL.WIFI_RST_EN: APB_CTRL_WIFI_RST_EN_REG +func (o *APB_CTRL_Type) SetWIFI_RST_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_RST_EN.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_RST_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_RST_EN.Reg) +} + +// APB_CTRL.HOST_INF_SEL: APB_CTRL_HOST_INF_SEL_REG +func (o *APB_CTRL_Type) SetHOST_INF_SEL_PERI_IO_SWAP(value uint32) { + volatile.StoreUint32(&o.HOST_INF_SEL.Reg, volatile.LoadUint32(&o.HOST_INF_SEL.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetHOST_INF_SEL_PERI_IO_SWAP() uint32 { + return volatile.LoadUint32(&o.HOST_INF_SEL.Reg) & 0xff +} + +// APB_CTRL.EXT_MEM_PMS_LOCK: APB_CTRL_EXT_MEM_PMS_LOCK_REG +func (o *APB_CTRL_Type) SetEXT_MEM_PMS_LOCK(value uint32) { + volatile.StoreUint32(&o.EXT_MEM_PMS_LOCK.Reg, volatile.LoadUint32(&o.EXT_MEM_PMS_LOCK.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetEXT_MEM_PMS_LOCK() uint32 { + return volatile.LoadUint32(&o.EXT_MEM_PMS_LOCK.Reg) & 0x1 +} + +// APB_CTRL.FLASH_ACE0_ATTR: APB_CTRL_FLASH_ACE0_ATTR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE0_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE0_ATTR.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE0_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_ATTR.Reg) & 0x3 +} + +// APB_CTRL.FLASH_ACE1_ATTR: APB_CTRL_FLASH_ACE1_ATTR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE1_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE1_ATTR.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE1_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_ATTR.Reg) & 0x3 +} + +// APB_CTRL.FLASH_ACE2_ATTR: APB_CTRL_FLASH_ACE2_ATTR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE2_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE2_ATTR.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE2_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_ATTR.Reg) & 0x3 +} + +// APB_CTRL.FLASH_ACE3_ATTR: APB_CTRL_FLASH_ACE3_ATTR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE3_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE3_ATTR.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE3_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_ATTR.Reg) & 0x3 +} + +// APB_CTRL.FLASH_ACE0_ADDR: APB_CTRL_FLASH_ACE0_ADDR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE0_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE0_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE1_ADDR: APB_CTRL_FLASH_ACE1_ADDR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE1_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE1_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE2_ADDR: APB_CTRL_FLASH_ACE2_ADDR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE2_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE2_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE3_ADDR: APB_CTRL_FLASH_ACE3_ADDR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE3_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE3_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE0_SIZE: APB_CTRL_FLASH_ACE0_SIZE_REG +func (o *APB_CTRL_Type) SetFLASH_ACE0_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE0_SIZE.Reg)&^(0x1fff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE0_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_SIZE.Reg) & 0x1fff +} + +// APB_CTRL.FLASH_ACE1_SIZE: APB_CTRL_FLASH_ACE1_SIZE_REG +func (o *APB_CTRL_Type) SetFLASH_ACE1_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE1_SIZE.Reg)&^(0x1fff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE1_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_SIZE.Reg) & 0x1fff +} + +// APB_CTRL.FLASH_ACE2_SIZE: APB_CTRL_FLASH_ACE2_SIZE_REG +func (o *APB_CTRL_Type) SetFLASH_ACE2_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE2_SIZE.Reg)&^(0x1fff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE2_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_SIZE.Reg) & 0x1fff +} + +// APB_CTRL.FLASH_ACE3_SIZE: APB_CTRL_FLASH_ACE3_SIZE_REG +func (o *APB_CTRL_Type) SetFLASH_ACE3_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE3_SIZE.Reg)&^(0x1fff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE3_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_SIZE.Reg) & 0x1fff +} + +// APB_CTRL.SPI_MEM_PMS_CTRL: APB_CTRL_SPI_MEM_PMS_CTRL_REG +func (o *APB_CTRL_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x7c)|value<<2) +} +func (o *APB_CTRL_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x7c) >> 2 +} + +// APB_CTRL.SPI_MEM_REJECT_ADDR: APB_CTRL_SPI_MEM_REJECT_ADDR_REG +func (o *APB_CTRL_Type) SetSPI_MEM_REJECT_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REJECT_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetSPI_MEM_REJECT_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REJECT_ADDR.Reg) +} + +// APB_CTRL.SDIO_CTRL: APB_CTRL_SDIO_CTRL_REG +func (o *APB_CTRL_Type) SetSDIO_CTRL_SDIO_WIN_ACCESS_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_CTRL.Reg, volatile.LoadUint32(&o.SDIO_CTRL.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetSDIO_CTRL_SDIO_WIN_ACCESS_EN() uint32 { + return volatile.LoadUint32(&o.SDIO_CTRL.Reg) & 0x1 +} + +// APB_CTRL.REDCY_SIG0: APB_CTRL_REDCY_SIG0_REG_REG +func (o *APB_CTRL_Type) SetREDCY_SIG0(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG0.Reg, volatile.LoadUint32(&o.REDCY_SIG0.Reg)&^(0x7fffffff)|value) +} +func (o *APB_CTRL_Type) GetREDCY_SIG0() uint32 { + return volatile.LoadUint32(&o.REDCY_SIG0.Reg) & 0x7fffffff +} +func (o *APB_CTRL_Type) SetREDCY_SIG0_REDCY_ANDOR(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG0.Reg, volatile.LoadUint32(&o.REDCY_SIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetREDCY_SIG0_REDCY_ANDOR() uint32 { + return (volatile.LoadUint32(&o.REDCY_SIG0.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.REDCY_SIG1: APB_CTRL_REDCY_SIG1_REG_REG +func (o *APB_CTRL_Type) SetREDCY_SIG1(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG1.Reg, volatile.LoadUint32(&o.REDCY_SIG1.Reg)&^(0x7fffffff)|value) +} +func (o *APB_CTRL_Type) GetREDCY_SIG1() uint32 { + return volatile.LoadUint32(&o.REDCY_SIG1.Reg) & 0x7fffffff +} +func (o *APB_CTRL_Type) SetREDCY_SIG1_REDCY_NANDOR(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG1.Reg, volatile.LoadUint32(&o.REDCY_SIG1.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetREDCY_SIG1_REDCY_NANDOR() uint32 { + return (volatile.LoadUint32(&o.REDCY_SIG1.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.FRONT_END_MEM_PD: APB_CTRL_FRONT_END_MEM_PD_REG +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU() uint32 { + return volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x4)|value<<2) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x4) >> 2 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x8)|value<<3) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x8) >> 3 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_DC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x10)|value<<4) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_DC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x10) >> 4 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_DC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x20)|value<<5) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_DC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x20) >> 5 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_FREQ_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x40)|value<<6) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_FREQ_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x40) >> 6 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_FREQ_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x80)|value<<7) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_FREQ_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x80) >> 7 +} + +// APB_CTRL.RETENTION_CTRL: APB_CTRL_RETENTION_CTRL_REG +func (o *APB_CTRL_Type) SetRETENTION_CTRL_RETENTION_LINK_ADDR(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x7ffffff)|value) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL_RETENTION_LINK_ADDR() uint32 { + return volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x7ffffff +} +func (o *APB_CTRL_Type) SetRETENTION_CTRL_NOBYPASS_CPU_ISO_RST(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL_NOBYPASS_CPU_ISO_RST() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x8000000) >> 27 +} + +// APB_CTRL.CLKGATE_FORCE_ON: Memory power configuration registers +func (o *APB_CTRL_Type) SetCLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLKGATE_FORCE_ON.Reg, volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg)&^(0x7)|value) +} +func (o *APB_CTRL_Type) GetCLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg) & 0x7 +} +func (o *APB_CTRL_Type) SetCLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLKGATE_FORCE_ON.Reg, volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg)&^(0x78)|value<<3) +} +func (o *APB_CTRL_Type) GetCLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg) & 0x78) >> 3 +} + +// APB_CTRL.MEM_POWER_DOWN: Memory power configuration registers +func (o *APB_CTRL_Type) SetMEM_POWER_DOWN_ROM_POWER_DOWN(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_DOWN.Reg, volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg)&^(0x7)|value) +} +func (o *APB_CTRL_Type) GetMEM_POWER_DOWN_ROM_POWER_DOWN() uint32 { + return volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg) & 0x7 +} +func (o *APB_CTRL_Type) SetMEM_POWER_DOWN_SRAM_POWER_DOWN(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_DOWN.Reg, volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg)&^(0x78)|value<<3) +} +func (o *APB_CTRL_Type) GetMEM_POWER_DOWN_SRAM_POWER_DOWN() uint32 { + return (volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg) & 0x78) >> 3 +} + +// APB_CTRL.MEM_POWER_UP: Memory power configuration registers +func (o *APB_CTRL_Type) SetMEM_POWER_UP_ROM_POWER_UP(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_UP.Reg, volatile.LoadUint32(&o.MEM_POWER_UP.Reg)&^(0x7)|value) +} +func (o *APB_CTRL_Type) GetMEM_POWER_UP_ROM_POWER_UP() uint32 { + return volatile.LoadUint32(&o.MEM_POWER_UP.Reg) & 0x7 +} +func (o *APB_CTRL_Type) SetMEM_POWER_UP_SRAM_POWER_UP(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_UP.Reg, volatile.LoadUint32(&o.MEM_POWER_UP.Reg)&^(0x78)|value<<3) +} +func (o *APB_CTRL_Type) GetMEM_POWER_UP_SRAM_POWER_UP() uint32 { + return (volatile.LoadUint32(&o.MEM_POWER_UP.Reg) & 0x78) >> 3 +} + +// APB_CTRL.RND_DATA: APB_CTRL_RND_DATA_REG +func (o *APB_CTRL_Type) SetRND_DATA(value uint32) { + volatile.StoreUint32(&o.RND_DATA.Reg, value) +} +func (o *APB_CTRL_Type) GetRND_DATA() uint32 { + return volatile.LoadUint32(&o.RND_DATA.Reg) +} + +// APB_CTRL.PERI_BACKUP_CONFIG: APB_CTRL_PERI_BACKUP_CONFIG_REG_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_FLOW_ERR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x6)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_FLOW_ERR() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x6) >> 1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_BURST_LIMIT(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x1f0)|value<<4) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_BURST_LIMIT() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x1f0) >> 4 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_TOUT_THRES(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x7fe00)|value<<9) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_TOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x7fe00) >> 9 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_SIZE(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x1ff80000)|value<<19) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_SIZE() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x1ff80000) >> 19 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_START(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_START() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_ENA(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_ENA() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.PERI_BACKUP_APB_ADDR: APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_APB_ADDR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_APB_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_APB_ADDR() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_APB_ADDR.Reg) +} + +// APB_CTRL.PERI_BACKUP_MEM_ADDR: APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_MEM_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_MEM_ADDR() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_MEM_ADDR.Reg) +} + +// APB_CTRL.PERI_BACKUP_INT_RAW: APB_CTRL_PERI_BACKUP_INT_RAW_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_RAW.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_RAW.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_RAW.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_RAW.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_INT_RAW.Reg) & 0x2) >> 1 +} + +// APB_CTRL.PERI_BACKUP_INT_ST: APB_CTRL_PERI_BACKUP_INT_ST_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_ST.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_ST.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_ST.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_ST.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_INT_ST.Reg) & 0x2) >> 1 +} + +// APB_CTRL.PERI_BACKUP_INT_ENA: APB_CTRL_PERI_BACKUP_INT_ENA_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_ENA.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_ENA.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_ENA.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_ENA.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_INT_ENA.Reg) & 0x2) >> 1 +} + +// APB_CTRL.PERI_BACKUP_INT_CLR: APB_CTRL_PERI_BACKUP_INT_CLR_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_CLR.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_CLR.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_CLR.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_CLR.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_INT_CLR.Reg) & 0x2) >> 1 +} + +// APB_CTRL.DATE: APB_CTRL_DATE_REG +func (o *APB_CTRL_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *APB_CTRL_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// SAR (Successive Approximation Register) Analog-to-Digital Converter +type APB_SARADC_Type struct { + CTRL volatile.Register32 // 0x0 + CTRL2 volatile.Register32 // 0x4 + FILTER_CTRL1 volatile.Register32 // 0x8 + FSM_WAIT volatile.Register32 // 0xC + SAR1_STATUS volatile.Register32 // 0x10 + SAR2_STATUS volatile.Register32 // 0x14 + SAR_PATT_TAB1 volatile.Register32 // 0x18 + SAR_PATT_TAB2 volatile.Register32 // 0x1C + ONETIME_SAMPLE volatile.Register32 // 0x20 + APB_ADC_ARB_CTRL volatile.Register32 // 0x24 + FILTER_CTRL0 volatile.Register32 // 0x28 + SAR1DATA_STATUS volatile.Register32 // 0x2C + SAR2DATA_STATUS volatile.Register32 // 0x30 + THRES0_CTRL volatile.Register32 // 0x34 + THRES1_CTRL volatile.Register32 // 0x38 + THRES_CTRL volatile.Register32 // 0x3C + INT_ENA volatile.Register32 // 0x40 + INT_RAW volatile.Register32 // 0x44 + INT_ST volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + DMA_CONF volatile.Register32 // 0x50 + APB_ADC_CLKM_CONF volatile.Register32 // 0x54 + APB_TSENS_CTRL volatile.Register32 // 0x58 + APB_TSENS_CTRL2 volatile.Register32 // 0x5C + CALI volatile.Register32 // 0x60 + _ [920]byte + APB_CTRL_DATE volatile.Register32 // 0x3FC +} + +// APB_SARADC.CTRL: register description +func (o *APB_SARADC_Type) SetCTRL_SARADC_START_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START_FORCE() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x7f80)|value<<7) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x7f80) >> 7 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x38000)|value<<15) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x38000) >> 15 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_XPD_SAR_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x18000000)|value<<27) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_XPD_SAR_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x18000000) >> 27 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc0000000) >> 30 +} + +// APB_SARADC.CTRL2: register description +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MEAS_NUM_LIMIT(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MEAS_NUM_LIMIT() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MAX_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1fe)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MAX_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1fe) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR1_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR1_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x200) >> 9 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR2_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR2_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x400) >> 10 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff000)|value<<12) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_TARGET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff000) >> 12 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1000000) >> 24 +} + +// APB_SARADC.FILTER_CTRL1: register description +func (o *APB_SARADC_Type) SetFILTER_CTRL1_FILTER_FACTOR1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0x1c000000)|value<<26) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_FILTER_FACTOR1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0x1c000000) >> 26 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL1_FILTER_FACTOR0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0xe0000000)|value<<29) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_FILTER_FACTOR0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0xe0000000) >> 29 +} + +// APB_SARADC.FSM_WAIT: register description +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff00)|value<<8) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff00) >> 8 +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff0000)|value<<16) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff0000) >> 16 +} + +// APB_SARADC.SAR1_STATUS: register description +func (o *APB_SARADC_Type) SetSAR1_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR1_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR1_STATUS.Reg) +} + +// APB_SARADC.SAR2_STATUS: register description +func (o *APB_SARADC_Type) SetSAR2_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR2_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR2_STATUS.Reg) +} + +// APB_SARADC.SAR_PATT_TAB1: register description +func (o *APB_SARADC_Type) SetSAR_PATT_TAB1_SARADC_SAR_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR_PATT_TAB1.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR_PATT_TAB1_SARADC_SAR_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR_PATT_TAB1.Reg) & 0xffffff +} + +// APB_SARADC.SAR_PATT_TAB2: register description +func (o *APB_SARADC_Type) SetSAR_PATT_TAB2_SARADC_SAR_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR_PATT_TAB2.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR_PATT_TAB2_SARADC_SAR_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR_PATT_TAB2.Reg) & 0xffffff +} + +// APB_SARADC.ONETIME_SAMPLE: register description +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_ATTEN(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x1800000)|value<<23) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_ATTEN() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x1800000) >> 23 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x1e000000)|value<<25) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x1e000000) >> 25 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_START(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_START() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.APB_ADC_ARB_CTRL: register description +func (o *APB_SARADC_Type) SetAPB_ADC_ARB_CTRL_ADC_ARB_APB_FORCE(value uint32) { + volatile.StoreUint32(&o.APB_ADC_ARB_CTRL.Reg, volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *APB_SARADC_Type) GetAPB_ADC_ARB_CTRL_ADC_ARB_APB_FORCE() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg) & 0x4) >> 2 +} +func (o *APB_SARADC_Type) SetAPB_ADC_ARB_CTRL_ADC_ARB_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.APB_ADC_ARB_CTRL.Reg, volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *APB_SARADC_Type) GetAPB_ADC_ARB_CTRL_ADC_ARB_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg) & 0x8) >> 3 +} +func (o *APB_SARADC_Type) SetAPB_ADC_ARB_CTRL_ADC_ARB_WIFI_FORCE(value uint32) { + volatile.StoreUint32(&o.APB_ADC_ARB_CTRL.Reg, volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *APB_SARADC_Type) GetAPB_ADC_ARB_CTRL_ADC_ARB_WIFI_FORCE() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg) & 0x10) >> 4 +} +func (o *APB_SARADC_Type) SetAPB_ADC_ARB_CTRL_ADC_ARB_GRANT_FORCE(value uint32) { + volatile.StoreUint32(&o.APB_ADC_ARB_CTRL.Reg, volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *APB_SARADC_Type) GetAPB_ADC_ARB_CTRL_ADC_ARB_GRANT_FORCE() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg) & 0x20) >> 5 +} +func (o *APB_SARADC_Type) SetAPB_ADC_ARB_CTRL_ADC_ARB_APB_PRIORITY(value uint32) { + volatile.StoreUint32(&o.APB_ADC_ARB_CTRL.Reg, volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg)&^(0xc0)|value<<6) +} +func (o *APB_SARADC_Type) GetAPB_ADC_ARB_CTRL_ADC_ARB_APB_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg) & 0xc0) >> 6 +} +func (o *APB_SARADC_Type) SetAPB_ADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY(value uint32) { + volatile.StoreUint32(&o.APB_ADC_ARB_CTRL.Reg, volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg)&^(0x300)|value<<8) +} +func (o *APB_SARADC_Type) GetAPB_ADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg) & 0x300) >> 8 +} +func (o *APB_SARADC_Type) SetAPB_ADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY(value uint32) { + volatile.StoreUint32(&o.APB_ADC_ARB_CTRL.Reg, volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg)&^(0xc00)|value<<10) +} +func (o *APB_SARADC_Type) GetAPB_ADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg) & 0xc00) >> 10 +} +func (o *APB_SARADC_Type) SetAPB_ADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY(value uint32) { + volatile.StoreUint32(&o.APB_ADC_ARB_CTRL.Reg, volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *APB_SARADC_Type) GetAPB_ADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_ARB_CTRL.Reg) & 0x1000) >> 12 +} + +// APB_SARADC.FILTER_CTRL0: register description +func (o *APB_SARADC_Type) SetFILTER_CTRL0_FILTER_CHANNEL1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x3c0000)|value<<18) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_FILTER_CHANNEL1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x3c0000) >> 18 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_FILTER_CHANNEL0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_FILTER_CHANNEL0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x3c00000) >> 22 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_FILTER_RESET(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_FILTER_RESET() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.SAR1DATA_STATUS: register description +func (o *APB_SARADC_Type) SetSAR1DATA_STATUS_APB_SARADC1_DATA(value uint32) { + volatile.StoreUint32(&o.SAR1DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR1DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetSAR1DATA_STATUS_APB_SARADC1_DATA() uint32 { + return volatile.LoadUint32(&o.SAR1DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.SAR2DATA_STATUS: register description +func (o *APB_SARADC_Type) SetSAR2DATA_STATUS_APB_SARADC2_DATA(value uint32) { + volatile.StoreUint32(&o.SAR2DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR2DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetSAR2DATA_STATUS_APB_SARADC2_DATA() uint32 { + return volatile.LoadUint32(&o.SAR2DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.THRES0_CTRL: register description +func (o *APB_SARADC_Type) SetTHRES0_CTRL_THRES0_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0xf)|value) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_THRES0_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0xf +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_THRES0_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_THRES0_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_THRES0_LOW(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_THRES0_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES1_CTRL: register description +func (o *APB_SARADC_Type) SetTHRES1_CTRL_THRES1_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0xf)|value) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_THRES1_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0xf +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_THRES1_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_THRES1_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_THRES1_LOW(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_THRES1_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES_CTRL: register description +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES_ALL_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES_ALL_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES3_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES3_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES2_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES2_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ENA: register description +func (o *APB_SARADC_Type) SetINT_ENA_THRES1_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ENA_THRES1_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ENA_THRES0_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ENA_THRES0_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ENA_THRES1_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ENA_THRES1_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ENA_THRES0_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ENA_THRES0_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC2_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC2_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC1_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC1_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_RAW: register description +func (o *APB_SARADC_Type) SetINT_RAW_THRES1_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_RAW_THRES1_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_RAW_THRES0_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_RAW_THRES0_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_RAW_THRES1_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_RAW_THRES1_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_RAW_THRES0_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_RAW_THRES0_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC2_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC2_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC1_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC1_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ST: register description +func (o *APB_SARADC_Type) SetINT_ST_THRES1_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ST_THRES1_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ST_THRES0_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ST_THRES0_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ST_THRES1_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ST_THRES1_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ST_THRES0_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ST_THRES0_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC2_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC2_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC1_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC1_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_CLR: register description +func (o *APB_SARADC_Type) SetINT_CLR_THRES1_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_CLR_THRES1_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_CLR_THRES0_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_CLR_THRES0_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_CLR_THRES1_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_CLR_THRES1_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_CLR_THRES0_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_CLR_THRES0_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC2_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC2_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC1_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC1_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.DMA_CONF: register description +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0xffff)|value) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0xffff +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_RESET_FSM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_RESET_FSM() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_TRANS(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_TRANS() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.APB_ADC_CLKM_CONF: register description +func (o *APB_SARADC_Type) SetAPB_ADC_CLKM_CONF_REG_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.APB_ADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetAPB_ADC_CLKM_CONF_REG_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetAPB_ADC_CLKM_CONF_REG_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.APB_ADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *APB_SARADC_Type) GetAPB_ADC_CLKM_CONF_REG_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg) & 0x3f00) >> 8 +} +func (o *APB_SARADC_Type) SetAPB_ADC_CLKM_CONF_REG_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.APB_ADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *APB_SARADC_Type) GetAPB_ADC_CLKM_CONF_REG_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg) & 0xfc000) >> 14 +} +func (o *APB_SARADC_Type) SetAPB_ADC_CLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.APB_ADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *APB_SARADC_Type) GetAPB_ADC_CLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg) & 0x100000) >> 20 +} +func (o *APB_SARADC_Type) SetAPB_ADC_CLKM_CONF_REG_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.APB_ADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg)&^(0x600000)|value<<21) +} +func (o *APB_SARADC_Type) GetAPB_ADC_CLKM_CONF_REG_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.APB_ADC_CLKM_CONF.Reg) & 0x600000) >> 21 +} + +// APB_SARADC.APB_TSENS_CTRL: register description +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_REG_TSENS_OUT(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_REG_TSENS_OUT() uint32 { + return volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_REG_TSENS_IN_INV(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_REG_TSENS_IN_INV() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x2000) >> 13 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_REG_TSENS_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_REG_TSENS_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_REG_TSENS_PU(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_REG_TSENS_PU() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x400000) >> 22 +} + +// APB_SARADC.APB_TSENS_CTRL2: register description +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL2_REG_TSENS_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL2.Reg)&^(0xfff)|value) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL2_REG_TSENS_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.APB_TSENS_CTRL2.Reg) & 0xfff +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL2_REG_TSENS_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL2.Reg)&^(0x3000)|value<<12) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL2_REG_TSENS_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL2.Reg) & 0x3000) >> 12 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL2_REG_TSENS_CLK_INV(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL2_REG_TSENS_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL2_TSENS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL2.Reg)&^(0x8000)|value<<15) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL2_TSENS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL2.Reg) & 0x8000) >> 15 +} + +// APB_SARADC.CALI: register description +func (o *APB_SARADC_Type) SetCALI_CFG(value uint32) { + volatile.StoreUint32(&o.CALI.Reg, volatile.LoadUint32(&o.CALI.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetCALI_CFG() uint32 { + return volatile.LoadUint32(&o.CALI.Reg) & 0x1ffff +} + +// APB_SARADC.APB_CTRL_DATE: register description +func (o *APB_SARADC_Type) SetAPB_CTRL_DATE(value uint32) { + volatile.StoreUint32(&o.APB_CTRL_DATE.Reg, value) +} +func (o *APB_SARADC_Type) GetAPB_CTRL_DATE() uint32 { + return volatile.LoadUint32(&o.APB_CTRL_DATE.Reg) +} + +// Debug Assist +type ASSIST_DEBUG_Type struct { + CORE_0_MONTR_ENA volatile.Register32 // 0x0 + CORE_0_INTR_RAW volatile.Register32 // 0x4 + CORE_0_INTR_ENA volatile.Register32 // 0x8 + CORE_0_INTR_CLR volatile.Register32 // 0xC + CORE_0_SP_MIN volatile.Register32 // 0x10 + CORE_0_SP_MAX volatile.Register32 // 0x14 + CORE_0_SP_PC volatile.Register32 // 0x18 + CORE_0_RCD_EN volatile.Register32 // 0x1C + CORE_0_RCD_PDEBUGPC volatile.Register32 // 0x20 + CORE_0_RCD_PDEBUGSP volatile.Register32 // 0x24 + CORE_0_LASTPC_BEFORE_EXCEPTION volatile.Register32 // 0x28 + CORE_0_DEBUG_MODE volatile.Register32 // 0x2C + CLOCK_GATE volatile.Register32 // 0x30 + _ [456]byte + DATE volatile.Register32 // 0x1FC +} + +// ASSIST_DEBUG.CORE_0_MONTR_ENA: core0 monitor enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_0_INTR_RAW: core0 monitor interrupt status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_0_INTR_ENA: core0 monitor interrupt enable register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_0_INTR_CLR: core0 monitor interrupt clr register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_0_SP_MIN: stack min value +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_MAX: stack max value +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_PC: stack monitor pc status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_PC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_EN: record enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGPC: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGPC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGPC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGSP: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGSP(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGSP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGSP() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGSP.Reg) +} + +// ASSIST_DEBUG.CORE_0_LASTPC_BEFORE_EXCEPTION: cpu status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_LASTPC_BEFORE_EXCEPTION(value uint32) { + volatile.StoreUint32(&o.CORE_0_LASTPC_BEFORE_EXCEPTION.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_LASTPC_BEFORE_EXCEPTION() uint32 { + return volatile.LoadUint32(&o.CORE_0_LASTPC_BEFORE_EXCEPTION.Reg) +} + +// ASSIST_DEBUG.CORE_0_DEBUG_MODE: cpu status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_DEBUG_MODE(value uint32) { + volatile.StoreUint32(&o.CORE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DEBUG_MODE() uint32 { + return volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CORE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CLOCK_GATE: clock gate register +func (o *ASSIST_DEBUG_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// ASSIST_DEBUG.DATE: version register +func (o *ASSIST_DEBUG_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// BB Peripheral +type BB_Type struct { + _ [84]byte + BBPD_CTRL volatile.Register32 // 0x54 +} + +// BB.BBPD_CTRL: Baseband control register +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x1)|value) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x1 +} +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x2) >> 1 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x4) >> 2 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x8) >> 3 +} + +// DMA (Direct Memory Access) Controller +type DMA_Type struct { + INT_RAW_CH0 volatile.Register32 // 0x0 + INT_ST_CH0 volatile.Register32 // 0x4 + INT_ENA_CH0 volatile.Register32 // 0x8 + INT_CLR_CH0 volatile.Register32 // 0xC + _ [48]byte + AHB_TEST volatile.Register32 // 0x40 + MISC_CONF volatile.Register32 // 0x44 + DATE volatile.Register32 // 0x48 + _ [36]byte + IN_CONF0_CH0 volatile.Register32 // 0x70 + IN_CONF1_CH0 volatile.Register32 // 0x74 + INFIFO_STATUS_CH0 volatile.Register32 // 0x78 + IN_POP_CH0 volatile.Register32 // 0x7C + IN_LINK_CH0 volatile.Register32 // 0x80 + IN_STATE_CH0 volatile.Register32 // 0x84 + IN_SUC_EOF_DES_ADDR_CH0 volatile.Register32 // 0x88 + IN_ERR_EOF_DES_ADDR_CH0 volatile.Register32 // 0x8C + IN_DSCR_CH0 volatile.Register32 // 0x90 + IN_DSCR_BF0_CH0 volatile.Register32 // 0x94 + IN_DSCR_BF1_CH0 volatile.Register32 // 0x98 + IN_PRI_CH0 volatile.Register32 // 0x9C + IN_PERI_SEL_CH0 volatile.Register32 // 0xA0 + _ [44]byte + OUT_CONF0_CH0 volatile.Register32 // 0xD0 + OUT_CONF1_CH0 volatile.Register32 // 0xD4 + OUTFIFO_STATUS_CH0 volatile.Register32 // 0xD8 + OUT_PUSH_CH0 volatile.Register32 // 0xDC + OUT_LINK_CH0 volatile.Register32 // 0xE0 + OUT_STATE_CH0 volatile.Register32 // 0xE4 + OUT_EOF_DES_ADDR_CH0 volatile.Register32 // 0xE8 + OUT_EOF_BFR_DES_ADDR_CH0 volatile.Register32 // 0xEC + OUT_DSCR_CH0 volatile.Register32 // 0xF0 + OUT_DSCR_BF0_CH0 volatile.Register32 // 0xF4 + OUT_DSCR_BF1_CH0 volatile.Register32 // 0xF8 + OUT_PRI_CH0 volatile.Register32 // 0xFC + OUT_PERI_SEL_CH0 volatile.Register32 // 0x100 +} + +// DMA.INT_RAW_CH0: DMA_INT_RAW_CH0_REG. +func (o *DMA_Type) SetINT_RAW_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_RAW_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_RAW_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_RAW_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_RAW_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_RAW_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_RAW_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_RAW_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_RAW_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INT_ST_CH0: DMA_INT_ST_CH0_REG. +func (o *DMA_Type) SetINT_ST_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_ST_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_ST_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_ST_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_ST_CH0_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_ST_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_ST_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_ST_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_ST_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_ST_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_ST_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_ST_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_ST_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_ST_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_ST_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_ST_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_ST_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_ST_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_ST_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_ST_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_ST_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INT_ENA_CH0: DMA_INT_ENA_CH0_REG. +func (o *DMA_Type) SetINT_ENA_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_ENA_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_ENA_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_ENA_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_ENA_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_ENA_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_ENA_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_ENA_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_ENA_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INT_CLR_CH0: DMA_INT_CLR_CH0_REG. +func (o *DMA_Type) SetINT_CLR_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_CLR_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_CLR_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_CLR_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_CLR_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_CLR_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_CLR_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_CLR_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_CLR_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.AHB_TEST: DMA_AHB_TEST_REG. +func (o *DMA_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *DMA_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// DMA.MISC_CONF: DMA_MISC_CONF_REG. +func (o *DMA_Type) SetMISC_CONF_AHBM_RST_INTER(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetMISC_CONF_AHBM_RST_INTER() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} +func (o *DMA_Type) SetMISC_CONF_ARB_PRI_DIS(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetMISC_CONF_ARB_PRI_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetMISC_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x8) >> 3 +} + +// DMA.DATE: DMA_DATE_REG. +func (o *DMA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *DMA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// DMA.IN_CONF0_CH0: DMA_IN_CONF0_CH0_REG. +func (o *DMA_Type) SetIN_CONF0_CH0_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH0_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH0_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x10) >> 4 +} + +// DMA.IN_CONF1_CH0: DMA_IN_CONF1_CH0_REG. +func (o *DMA_Type) SetIN_CONF1_CH0_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH0_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH0: DMA_INFIFO_STATUS_CH0_REG. +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH0: DMA_IN_POP_CH0_REG. +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH0: DMA_IN_LINK_CH0_REG. +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH0: DMA_IN_STATE_CH0_REG. +func (o *DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH0: DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH0: DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_DSCR_CH0: DMA_IN_DSCR_CH0_REG. +func (o *DMA_Type) SetIN_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg) +} + +// DMA.IN_DSCR_BF0_CH0: DMA_IN_DSCR_BF0_CH0_REG. +func (o *DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg) +} + +// DMA.IN_DSCR_BF1_CH0: DMA_IN_DSCR_BF1_CH0_REG. +func (o *DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg) +} + +// DMA.IN_PRI_CH0: DMA_IN_PRI_CH0_REG. +func (o *DMA_Type) SetIN_PRI_CH0_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH0_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH0: DMA_IN_PERI_SEL_CH0_REG. +func (o *DMA_Type) SetIN_PERI_SEL_CH0_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH0_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH0: DMA_OUT_CONF0_CH0_REG. +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_CONF1_CH0: DMA_OUT_CONF1_CH0_REG. +func (o *DMA_Type) SetOUT_CONF1_CH0_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH0_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH0: DMA_OUTFIFO_STATUS_CH0_REG. +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH0: DMA_OUT_PUSH_CH0_REG. +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH0: DMA_OUT_LINK_CH0_REG. +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH0: DMA_OUT_STATE_CH0_REG. +func (o *DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH0: DMA_OUT_EOF_DES_ADDR_CH0_REG. +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH0: DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_DSCR_CH0: DMA_OUT_DSCR_CH0_REG. +func (o *DMA_Type) SetOUT_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg) +} + +// DMA.OUT_DSCR_BF0_CH0: DMA_OUT_DSCR_BF0_CH0_REG. +func (o *DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg) +} + +// DMA.OUT_DSCR_BF1_CH0: DMA_OUT_DSCR_BF1_CH0_REG. +func (o *DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg) +} + +// DMA.OUT_PRI_CH0: DMA_OUT_PRI_CH0_REG. +func (o *DMA_Type) SetOUT_PRI_CH0_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH0_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH0: DMA_OUT_PERI_SEL_CH0_REG. +func (o *DMA_Type) SetOUT_PERI_SEL_CH0_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH0_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg) & 0x3f +} + +// ECC (ECC Hardware Accelerator) +type ECC_Type struct { + _ [12]byte + MULT_INT_RAW volatile.Register32 // 0xC + MULT_INT_ST volatile.Register32 // 0x10 + MULT_INT_ENA volatile.Register32 // 0x14 + MULT_INT_CLR volatile.Register32 // 0x18 + MULT_CONF volatile.Register32 // 0x1C + _ [220]byte + MULT_DATE volatile.Register32 // 0xFC + K_MEM [32]volatile.Register8 // 0x100 + PX_MEM [32]volatile.Register8 // 0x120 + PY_MEM [32]volatile.Register8 // 0x140 +} + +// ECC.MULT_INT_RAW: I2S interrupt raw register, valid in level. +func (o *ECC_Type) SetMULT_INT_RAW_CALC_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.MULT_INT_RAW.Reg, volatile.LoadUint32(&o.MULT_INT_RAW.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_RAW_CALC_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.MULT_INT_RAW.Reg) & 0x1 +} + +// ECC.MULT_INT_ST: I2S interrupt status register. +func (o *ECC_Type) SetMULT_INT_ST_CALC_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.MULT_INT_ST.Reg, volatile.LoadUint32(&o.MULT_INT_ST.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_ST_CALC_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.MULT_INT_ST.Reg) & 0x1 +} + +// ECC.MULT_INT_ENA: I2S interrupt enable register. +func (o *ECC_Type) SetMULT_INT_ENA_CALC_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.MULT_INT_ENA.Reg, volatile.LoadUint32(&o.MULT_INT_ENA.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_ENA_CALC_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.MULT_INT_ENA.Reg) & 0x1 +} + +// ECC.MULT_INT_CLR: I2S interrupt clear register. +func (o *ECC_Type) SetMULT_INT_CLR_CALC_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.MULT_INT_CLR.Reg, volatile.LoadUint32(&o.MULT_INT_CLR.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_CLR_CALC_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.MULT_INT_CLR.Reg) & 0x1 +} + +// ECC.MULT_CONF: I2S RX configure register +func (o *ECC_Type) SetMULT_CONF_START(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_CONF_START() uint32 { + return volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x1 +} +func (o *ECC_Type) SetMULT_CONF_RESET(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *ECC_Type) GetMULT_CONF_RESET() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x2) >> 1 +} +func (o *ECC_Type) SetMULT_CONF_KEY_LENGTH(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x4)|value<<2) +} +func (o *ECC_Type) GetMULT_CONF_KEY_LENGTH() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x4) >> 2 +} +func (o *ECC_Type) SetMULT_CONF_SECURITY_MODE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x8)|value<<3) +} +func (o *ECC_Type) GetMULT_CONF_SECURITY_MODE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x8) >> 3 +} +func (o *ECC_Type) SetMULT_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x10)|value<<4) +} +func (o *ECC_Type) GetMULT_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x10) >> 4 +} +func (o *ECC_Type) SetMULT_CONF_WORK_MODE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0xe0)|value<<5) +} +func (o *ECC_Type) GetMULT_CONF_WORK_MODE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0xe0) >> 5 +} +func (o *ECC_Type) SetMULT_CONF_VERIFICATION_RESULT(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x100)|value<<8) +} +func (o *ECC_Type) GetMULT_CONF_VERIFICATION_RESULT() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x100) >> 8 +} + +// ECC.MULT_DATE: Version control register +func (o *ECC_Type) SetMULT_DATE_DATE(value uint32) { + volatile.StoreUint32(&o.MULT_DATE.Reg, volatile.LoadUint32(&o.MULT_DATE.Reg)&^(0xfffffff)|value) +} +func (o *ECC_Type) GetMULT_DATE_DATE() uint32 { + return volatile.LoadUint32(&o.MULT_DATE.Reg) & 0xfffffff +} + +// eFuse Controller +type EFUSE_Type struct { + PGM_DATA0 volatile.Register32 // 0x0 + PGM_DATA1 volatile.Register32 // 0x4 + PGM_DATA2 volatile.Register32 // 0x8 + PGM_DATA3 volatile.Register32 // 0xC + PGM_DATA4 volatile.Register32 // 0x10 + PGM_DATA5 volatile.Register32 // 0x14 + PGM_DATA6 volatile.Register32 // 0x18 + PGM_DATA7 volatile.Register32 // 0x1C + PGM_CHECK_VALUE0 volatile.Register32 // 0x20 + PGM_CHECK_VALUE1 volatile.Register32 // 0x24 + PGM_CHECK_VALUE2 volatile.Register32 // 0x28 + RD_WR_DIS volatile.Register32 // 0x2C + RD_REPEAT_DATA0 volatile.Register32 // 0x30 + RD_BLK1_DATA0 volatile.Register32 // 0x34 + RD_BLK1_DATA1 volatile.Register32 // 0x38 + RD_BLK1_DATA2 volatile.Register32 // 0x3C + RD_BLK2_DATA0 volatile.Register32 // 0x40 + RD_BLK2_DATA1 volatile.Register32 // 0x44 + RD_BLK2_DATA2 volatile.Register32 // 0x48 + RD_BLK2_DATA3 volatile.Register32 // 0x4C + RD_BLK2_DATA4 volatile.Register32 // 0x50 + RD_BLK2_DATA5 volatile.Register32 // 0x54 + RD_BLK2_DATA6 volatile.Register32 // 0x58 + RD_BLK2_DATA7 volatile.Register32 // 0x5C + RD_BLK3_DATA0 volatile.Register32 // 0x60 + RD_BLK3_DATA1 volatile.Register32 // 0x64 + RD_BLK3_DATA2 volatile.Register32 // 0x68 + RD_BLK3_DATA3 volatile.Register32 // 0x6C + RD_BLK3_DATA4 volatile.Register32 // 0x70 + RD_BLK3_DATA5 volatile.Register32 // 0x74 + RD_BLK3_DATA6 volatile.Register32 // 0x78 + RD_BLK3_DATA7 volatile.Register32 // 0x7C + RD_REPEAT_ERR volatile.Register32 // 0x80 + RD_RS_ERR volatile.Register32 // 0x84 + CLK volatile.Register32 // 0x88 + CONF volatile.Register32 // 0x8C + STATUS volatile.Register32 // 0x90 + CMD volatile.Register32 // 0x94 + INT_RAW volatile.Register32 // 0x98 + INT_ST volatile.Register32 // 0x9C + _ [96]byte + INT_ENA volatile.Register32 // 0x100 + INT_CLR volatile.Register32 // 0x104 + DAC_CONF volatile.Register32 // 0x108 + RD_TIM_CONF volatile.Register32 // 0x10C + WR_TIM_CONF0 volatile.Register32 // 0x110 + WR_TIM_CONF1 volatile.Register32 // 0x114 + WR_TIM_CONF2 volatile.Register32 // 0x118 + _ [224]byte + DATE volatile.Register32 // 0x1FC +} + +// EFUSE.PGM_DATA0: Register 0 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA0(value uint32) { + volatile.StoreUint32(&o.PGM_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA0() uint32 { + return volatile.LoadUint32(&o.PGM_DATA0.Reg) +} + +// EFUSE.PGM_DATA1: Register 1 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA1(value uint32) { + volatile.StoreUint32(&o.PGM_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA1() uint32 { + return volatile.LoadUint32(&o.PGM_DATA1.Reg) +} + +// EFUSE.PGM_DATA2: Register 2 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA2(value uint32) { + volatile.StoreUint32(&o.PGM_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA2() uint32 { + return volatile.LoadUint32(&o.PGM_DATA2.Reg) +} + +// EFUSE.PGM_DATA3: Register 3 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA3(value uint32) { + volatile.StoreUint32(&o.PGM_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA3() uint32 { + return volatile.LoadUint32(&o.PGM_DATA3.Reg) +} + +// EFUSE.PGM_DATA4: Register 4 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA4(value uint32) { + volatile.StoreUint32(&o.PGM_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA4() uint32 { + return volatile.LoadUint32(&o.PGM_DATA4.Reg) +} + +// EFUSE.PGM_DATA5: Register 5 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA5(value uint32) { + volatile.StoreUint32(&o.PGM_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA5() uint32 { + return volatile.LoadUint32(&o.PGM_DATA5.Reg) +} + +// EFUSE.PGM_DATA6: Register 6 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA6(value uint32) { + volatile.StoreUint32(&o.PGM_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA6() uint32 { + return volatile.LoadUint32(&o.PGM_DATA6.Reg) +} + +// EFUSE.PGM_DATA7: Register 7 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA7(value uint32) { + volatile.StoreUint32(&o.PGM_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA7() uint32 { + return volatile.LoadUint32(&o.PGM_DATA7.Reg) +} + +// EFUSE.PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE0(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE0() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE0.Reg) +} + +// EFUSE.PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE1(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE1() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE1.Reg) +} + +// EFUSE.PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE2(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE2() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE2.Reg) +} + +// EFUSE.RD_WR_DIS: BLOCK0 data register 0. +func (o *EFUSE_Type) SetRD_WR_DIS_WR_DIS(value uint32) { + volatile.StoreUint32(&o.RD_WR_DIS.Reg, volatile.LoadUint32(&o.RD_WR_DIS.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetRD_WR_DIS_WR_DIS() uint32 { + return volatile.LoadUint32(&o.RD_WR_DIS.Reg) & 0xff +} + +// EFUSE.RD_REPEAT_DATA0: BLOCK0 data register 1. +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RD_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RD_DIS() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_WDT_DELAY_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xc)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_WDT_DELAY_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xc) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_PAD_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_PAD_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SPI_BOOT_ENCRYPT_DECRYPT_CNT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x380)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SPI_BOOT_ENCRYPT_DECRYPT_CNT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x380) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_XTS_KEY_LENGTH_256(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_XTS_KEY_LENGTH_256() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_UART_PRINT_CONTROL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_UART_PRINT_CONTROL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_FORCE_SEND_RESUME(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_FORCE_SEND_RESUME() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DIRECT_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DIRECT_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_ENABLE_SECURITY_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_ENABLE_SECURITY_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x10000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_FLASH_TPUW(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1e0000)|value<<17) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_FLASH_TPUW() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1e0000) >> 17 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SECURE_BOOT_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SECURE_BOOT_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xffc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xffc00000) >> 22 +} + +// EFUSE.RD_BLK1_DATA0: BLOCK1 data register 0. +func (o *EFUSE_Type) SetRD_BLK1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_BLK1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_BLK1_DATA0.Reg) +} + +// EFUSE.RD_BLK1_DATA1: BLOCK1 data register 1. +func (o *EFUSE_Type) SetRD_BLK1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_BLK1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_BLK1_DATA1.Reg) +} + +// EFUSE.RD_BLK1_DATA2: BLOCK1 data register 2. +func (o *EFUSE_Type) SetRD_BLK1_DATA2_SYSTEM_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_BLK1_DATA2.Reg, volatile.LoadUint32(&o.RD_BLK1_DATA2.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetRD_BLK1_DATA2_SYSTEM_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_BLK1_DATA2.Reg) & 0xffffff +} + +// EFUSE.RD_BLK2_DATA0: Register 0 of BLOCK2. +func (o *EFUSE_Type) SetRD_BLK2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_BLK2_DATA0.Reg) +} + +// EFUSE.RD_BLK2_DATA1: Register 1 of BLOCK2. +func (o *EFUSE_Type) SetRD_BLK2_DATA1_MAC_ID_HIGH(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA1.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA1_MAC_ID_HIGH() uint32 { + return volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_BLK2_DATA1_WAFER_VERSION(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA1.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA1_WAFER_VERSION() uint32 { + return (volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_BLK2_DATA1_PKG_VERSION(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA1.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg)&^(0x380000)|value<<19) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA1_PKG_VERSION() uint32 { + return (volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg) & 0x380000) >> 19 +} +func (o *EFUSE_Type) SetRD_BLK2_DATA1_BLK2_EFUSE_VERSION(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA1.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg)&^(0x1c00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA1_BLK2_EFUSE_VERSION() uint32 { + return (volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg) & 0x1c00000) >> 22 +} +func (o *EFUSE_Type) SetRD_BLK2_DATA1_RF_REF_I_BIAS_CONFIG(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA1.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg)&^(0x1e000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA1_RF_REF_I_BIAS_CONFIG() uint32 { + return (volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg) & 0x1e000000) >> 25 +} +func (o *EFUSE_Type) SetRD_BLK2_DATA1_LDO_VOL_BIAS_CONFIG_LOW(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA1.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg)&^(0xe0000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA1_LDO_VOL_BIAS_CONFIG_LOW() uint32 { + return (volatile.LoadUint32(&o.RD_BLK2_DATA1.Reg) & 0xe0000000) >> 29 +} + +// EFUSE.RD_BLK2_DATA2: Register 2 of BLOCK2. +func (o *EFUSE_Type) SetRD_BLK2_DATA2_LDO_VOL_BIAS_CONFIG_HIGH(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA2.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA2.Reg)&^(0x7ffffff)|value) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA2_LDO_VOL_BIAS_CONFIG_HIGH() uint32 { + return volatile.LoadUint32(&o.RD_BLK2_DATA2.Reg) & 0x7ffffff +} +func (o *EFUSE_Type) SetRD_BLK2_DATA2_PVT_LOW(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA2.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA2.Reg)&^(0xf8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA2_PVT_LOW() uint32 { + return (volatile.LoadUint32(&o.RD_BLK2_DATA2.Reg) & 0xf8000000) >> 27 +} + +// EFUSE.RD_BLK2_DATA3: Register 3 of BLOCK2. +func (o *EFUSE_Type) SetRD_BLK2_DATA3_PVT_HIGH(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA3.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA3.Reg)&^(0x3ff)|value) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA3_PVT_HIGH() uint32 { + return volatile.LoadUint32(&o.RD_BLK2_DATA3.Reg) & 0x3ff +} +func (o *EFUSE_Type) SetRD_BLK2_DATA3_ADC_CALIBRATION_0(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA3.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA3.Reg)&^(0xfffffc00)|value<<10) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA3_ADC_CALIBRATION_0() uint32 { + return (volatile.LoadUint32(&o.RD_BLK2_DATA3.Reg) & 0xfffffc00) >> 10 +} + +// EFUSE.RD_BLK2_DATA4: Register 4 of BLOCK2. +func (o *EFUSE_Type) SetRD_BLK2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_BLK2_DATA4.Reg) +} + +// EFUSE.RD_BLK2_DATA5: Register 5 of BLOCK2. +func (o *EFUSE_Type) SetRD_BLK2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_BLK2_DATA5.Reg) +} + +// EFUSE.RD_BLK2_DATA6: Register 6 of BLOCK2. +func (o *EFUSE_Type) SetRD_BLK2_DATA6_ADC_CALIBRATION_3(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA6.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA6.Reg)&^(0x7ff)|value) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA6_ADC_CALIBRATION_3() uint32 { + return volatile.LoadUint32(&o.RD_BLK2_DATA6.Reg) & 0x7ff +} +func (o *EFUSE_Type) SetRD_BLK2_DATA6_BLK2_RESERVED_DATA_0(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA6.Reg, volatile.LoadUint32(&o.RD_BLK2_DATA6.Reg)&^(0xfffff800)|value<<11) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA6_BLK2_RESERVED_DATA_0() uint32 { + return (volatile.LoadUint32(&o.RD_BLK2_DATA6.Reg) & 0xfffff800) >> 11 +} + +// EFUSE.RD_BLK2_DATA7: Register 7 of BLOCK2. +func (o *EFUSE_Type) SetRD_BLK2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_BLK2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_BLK2_DATA7.Reg) +} + +// EFUSE.RD_BLK3_DATA0: Register 0 of BLOCK3. +func (o *EFUSE_Type) SetRD_BLK3_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_BLK3_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK3_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_BLK3_DATA0.Reg) +} + +// EFUSE.RD_BLK3_DATA1: Register 1 of BLOCK3. +func (o *EFUSE_Type) SetRD_BLK3_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_BLK3_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK3_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_BLK3_DATA1.Reg) +} + +// EFUSE.RD_BLK3_DATA2: Register 2 of BLOCK3. +func (o *EFUSE_Type) SetRD_BLK3_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_BLK3_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK3_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_BLK3_DATA2.Reg) +} + +// EFUSE.RD_BLK3_DATA3: Register 3 of BLOCK3. +func (o *EFUSE_Type) SetRD_BLK3_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_BLK3_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK3_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_BLK3_DATA3.Reg) +} + +// EFUSE.RD_BLK3_DATA4: Register 4 of BLOCK3. +func (o *EFUSE_Type) SetRD_BLK3_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_BLK3_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK3_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_BLK3_DATA4.Reg) +} + +// EFUSE.RD_BLK3_DATA5: Register 5 of BLOCK3. +func (o *EFUSE_Type) SetRD_BLK3_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_BLK3_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK3_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_BLK3_DATA5.Reg) +} + +// EFUSE.RD_BLK3_DATA6: Register 6 of BLOCK3. +func (o *EFUSE_Type) SetRD_BLK3_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_BLK3_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK3_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_BLK3_DATA6.Reg) +} + +// EFUSE.RD_BLK3_DATA7: Register 7 of BLOCK3. +func (o *EFUSE_Type) SetRD_BLK3_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_BLK3_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_BLK3_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_BLK3_DATA7.Reg) +} + +// EFUSE.RD_REPEAT_ERR: Programming error record register 0 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR_RD_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_RD_DIS_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_WDT_DELAY_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0xc)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_WDT_DELAY_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0xc) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_DIS_PAD_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_DIS_PAD_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_DIS_DOWNLOAD_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_DIS_DOWNLOAD_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x380)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x380) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_XTS_KEY_LENGTH_256_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_XTS_KEY_LENGTH_256_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_UART_PRINT_CONTROL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x1800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_UART_PRINT_CONTROL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x1800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_FORCE_SEND_RESUME_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_FORCE_SEND_RESUME_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_DIS_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_DIS_DOWNLOAD_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_DIS_DIRECT_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_DIS_DIRECT_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_ENABLE_SECURITY_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_ENABLE_SECURITY_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x10000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_FLASH_TPUW_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x1e0000)|value<<17) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_FLASH_TPUW_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x1e0000) >> 17 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_SECURE_BOOT_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_SECURE_BOOT_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR_RPT4_RESERVED_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg)&^(0xffc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR_RPT4_RESERVED_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR.Reg) & 0xffc00000) >> 22 +} + +// EFUSE.RD_RS_ERR: Programming error record register 0 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR_BLK1_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR.Reg, volatile.LoadUint32(&o.RD_RS_ERR.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR_BLK1_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR_BLK1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR.Reg, volatile.LoadUint32(&o.RD_RS_ERR.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR_BLK1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR_BLK2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR.Reg, volatile.LoadUint32(&o.RD_RS_ERR.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR_BLK2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR_BLK2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR.Reg, volatile.LoadUint32(&o.RD_RS_ERR.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR_BLK2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_RS_ERR_BLK3_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR.Reg, volatile.LoadUint32(&o.RD_RS_ERR.Reg)&^(0x700)|value<<8) +} +func (o *EFUSE_Type) GetRD_RS_ERR_BLK3_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR.Reg) & 0x700) >> 8 +} +func (o *EFUSE_Type) SetRD_RS_ERR_BLK3_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR.Reg, volatile.LoadUint32(&o.RD_RS_ERR.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_RS_ERR_BLK3_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR.Reg) & 0x800) >> 11 +} + +// EFUSE.CLK: eFuse clcok configuration register. +func (o *EFUSE_Type) SetCLK_EFUSE_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCLK_EFUSE_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCLK_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCLK_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCLK_EFUSE_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetCLK_EFUSE_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x10000) >> 16 +} + +// EFUSE.CONF: eFuse operation mode configuraiton register +func (o *EFUSE_Type) SetCONF_OP_CODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetCONF_OP_CODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0xffff +} + +// EFUSE.STATUS: eFuse status register. +func (o *EFUSE_Type) SetSTATUS_STATE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetSTATUS_STATE() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xf +} +func (o *EFUSE_Type) SetSTATUS_OTP_LOAD_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetSTATUS_OTP_LOAD_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_C_SYNC2(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_C_SYNC2() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetSTATUS_OTP_STROBE_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetSTATUS_OTP_STROBE_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetSTATUS_OTP_CSB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetSTATUS_OTP_CSB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetSTATUS_OTP_PGENB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetSTATUS_OTP_PGENB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_IS_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_IS_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetSTATUS_BLK0_VALID_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xfc00)|value<<10) +} +func (o *EFUSE_Type) GetSTATUS_BLK0_VALID_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xfc00) >> 10 +} + +// EFUSE.CMD: eFuse command register. +func (o *EFUSE_Type) SetCMD_READ_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCMD_READ_CMD() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCMD_PGM_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCMD_PGM_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCMD_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0xc)|value<<2) +} +func (o *EFUSE_Type) GetCMD_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0xc) >> 2 +} + +// EFUSE.INT_RAW: eFuse raw interrupt register. +func (o *EFUSE_Type) SetINT_RAW_READ_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_RAW_READ_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_RAW_PGM_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_RAW_PGM_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ST: eFuse interrupt status register. +func (o *EFUSE_Type) SetINT_ST_READ_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ST_READ_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ST_PGM_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ST_PGM_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ENA: eFuse interrupt enable register. +func (o *EFUSE_Type) SetINT_ENA_READ_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ENA_READ_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ENA_PGM_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ENA_PGM_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_CLR: eFuse interrupt clear register. +func (o *EFUSE_Type) SetINT_CLR_READ_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_CLR_READ_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_CLR_PGM_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_CLR_PGM_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// EFUSE.DAC_CONF: Controls the eFuse programming voltage. +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.DAC_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_PAD_SEL(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_PAD_SEL() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_NUM(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x1fe00)|value<<9) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_NUM() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x1fe00) >> 9 +} +func (o *EFUSE_Type) SetDAC_CONF_OE_CLR(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EFUSE_Type) GetDAC_CONF_OE_CLR() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x20000) >> 17 +} + +// EFUSE.RD_TIM_CONF: Configures read timing parameters. +func (o *EFUSE_Type) SetRD_TIM_CONF_THR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_THR_A() uint32 { + return volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TRD(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TRD() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff00) >> 8 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TSUR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TSUR_A() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff0000) >> 16 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_READ_INIT_NUM(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_READ_INIT_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF0: Configurarion register 0 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF0_THP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_THP_A() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF0.Reg) & 0xff +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_TPGM_INACTIVE(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_TPGM_INACTIVE() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0.Reg) & 0xff00) >> 8 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_TPGM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_TPGM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF1_TSUP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_TSUP_A() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff +} +func (o *EFUSE_Type) SetWR_TIM_CONF1_PWR_ON_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xffff00)|value<<8) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_PWR_ON_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xffff00) >> 8 +} + +// EFUSE.WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF2_PWR_OFF_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_PWR_OFF_NUM() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff +} + +// EFUSE.DATE: eFuse version register. +func (o *EFUSE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *EFUSE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// External Memory +type EXTMEM_Type struct { + ICACHE_CTRL volatile.Register32 // 0x0 + ICACHE_CTRL1 volatile.Register32 // 0x4 + ICACHE_TAG_POWER_CTRL volatile.Register32 // 0x8 + _ [28]byte + ICACHE_SYNC_CTRL volatile.Register32 // 0x28 + ICACHE_SYNC_ADDR volatile.Register32 // 0x2C + ICACHE_SYNC_SIZE volatile.Register32 // 0x30 + _ [32]byte + IBUS_TO_FLASH_START_VADDR volatile.Register32 // 0x54 + IBUS_TO_FLASH_END_VADDR volatile.Register32 // 0x58 + DBUS_TO_FLASH_START_VADDR volatile.Register32 // 0x5C + DBUS_TO_FLASH_END_VADDR volatile.Register32 // 0x60 + CACHE_ACS_CNT_CLR volatile.Register32 // 0x64 + _ [16]byte + CACHE_ILG_INT_ENA volatile.Register32 // 0x78 + CACHE_ILG_INT_CLR volatile.Register32 // 0x7C + CACHE_ILG_INT_ST volatile.Register32 // 0x80 + CORE0_ACS_CACHE_INT_ENA volatile.Register32 // 0x84 + CORE0_ACS_CACHE_INT_CLR volatile.Register32 // 0x88 + CORE0_ACS_CACHE_INT_ST volatile.Register32 // 0x8C + CORE0_DBUS_REJECT_ST volatile.Register32 // 0x90 + CORE0_DBUS_REJECT_VADDR volatile.Register32 // 0x94 + CORE0_IBUS_REJECT_ST volatile.Register32 // 0x98 + CORE0_IBUS_REJECT_VADDR volatile.Register32 // 0x9C + CACHE_MMU_FAULT_CONTENT volatile.Register32 // 0xA0 + CACHE_MMU_FAULT_VADDR volatile.Register32 // 0xA4 + CACHE_WRAP_AROUND_CTRL volatile.Register32 // 0xA8 + CACHE_MMU_POWER_CTRL volatile.Register32 // 0xAC + CACHE_STATE volatile.Register32 // 0xB0 + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE volatile.Register32 // 0xB4 + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON volatile.Register32 // 0xB8 + CACHE_PRELOAD_INT_CTRL volatile.Register32 // 0xBC + CACHE_SYNC_INT_CTRL volatile.Register32 // 0xC0 + CACHE_MMU_OWNER volatile.Register32 // 0xC4 + CACHE_CONF_MISC volatile.Register32 // 0xC8 + ICACHE_FREEZE volatile.Register32 // 0xCC + ICACHE_ATOMIC_OPERATE_ENA volatile.Register32 // 0xD0 + CACHE_REQUEST volatile.Register32 // 0xD4 + _ [40]byte + CLOCK_GATE volatile.Register32 // 0x100 + _ [760]byte + REG_DATE volatile.Register32 // 0x3FC +} + +// EXTMEM.ICACHE_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_CTRL_ICACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_CTRL_ICACHE_ENABLE() uint32 { + return volatile.LoadUint32(&o.ICACHE_CTRL.Reg) & 0x1 +} + +// EXTMEM.ICACHE_CTRL1: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_CTRL1_ICACHE_SHUT_IBUS(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL1.Reg, volatile.LoadUint32(&o.ICACHE_CTRL1.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_CTRL1_ICACHE_SHUT_IBUS() uint32 { + return volatile.LoadUint32(&o.ICACHE_CTRL1.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_CTRL1_ICACHE_SHUT_DBUS(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL1.Reg, volatile.LoadUint32(&o.ICACHE_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_CTRL1_ICACHE_SHUT_DBUS() uint32 { + return (volatile.LoadUint32(&o.ICACHE_CTRL1.Reg) & 0x2) >> 1 +} + +// EXTMEM.ICACHE_TAG_POWER_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_SYNC_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_SYNC_CTRL_ICACHE_SYNC_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_CTRL_ICACHE_SYNC_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.ICACHE_SYNC_ADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_SYNC_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_ADDR.Reg) +} + +// EXTMEM.ICACHE_SYNC_SIZE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_SYNC_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_SIZE.Reg)&^(0x7fffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_SIZE.Reg) & 0x7fffff +} + +// EXTMEM.IBUS_TO_FLASH_START_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_TO_FLASH_START_VADDR(value uint32) { + volatile.StoreUint32(&o.IBUS_TO_FLASH_START_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_TO_FLASH_START_VADDR() uint32 { + return volatile.LoadUint32(&o.IBUS_TO_FLASH_START_VADDR.Reg) +} + +// EXTMEM.IBUS_TO_FLASH_END_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_TO_FLASH_END_VADDR(value uint32) { + volatile.StoreUint32(&o.IBUS_TO_FLASH_END_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_TO_FLASH_END_VADDR() uint32 { + return volatile.LoadUint32(&o.IBUS_TO_FLASH_END_VADDR.Reg) +} + +// EXTMEM.DBUS_TO_FLASH_START_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_TO_FLASH_START_VADDR(value uint32) { + volatile.StoreUint32(&o.DBUS_TO_FLASH_START_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_TO_FLASH_START_VADDR() uint32 { + return volatile.LoadUint32(&o.DBUS_TO_FLASH_START_VADDR.Reg) +} + +// EXTMEM.DBUS_TO_FLASH_END_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_TO_FLASH_END_VADDR(value uint32) { + volatile.StoreUint32(&o.DBUS_TO_FLASH_END_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_TO_FLASH_END_VADDR() uint32 { + return volatile.LoadUint32(&o.DBUS_TO_FLASH_END_VADDR.Reg) +} + +// EXTMEM.CACHE_ACS_CNT_CLR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ACS_CNT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR() uint32 { + return volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ACS_CNT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg) & 0x2) >> 1 +} + +// EXTMEM.CACHE_ILG_INT_ENA: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA() uint32 { + return volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x100) >> 8 +} + +// EXTMEM.CACHE_ILG_INT_CLR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR() uint32 { + return volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x100) >> 8 +} + +// EXTMEM.CACHE_ILG_INT_ST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x400) >> 10 +} + +// EXTMEM.CORE0_ACS_CACHE_INT_ENA: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA() uint32 { + return volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x20) >> 5 +} + +// EXTMEM.CORE0_ACS_CACHE_INT_CLR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR() uint32 { + return volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x20) >> 5 +} + +// EXTMEM.CORE0_ACS_CACHE_INT_ST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST() uint32 { + return volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x20) >> 5 +} + +// EXTMEM.CORE0_DBUS_REJECT_ST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR() uint32 { + return volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg) & 0x8) >> 3 +} + +// EXTMEM.CORE0_DBUS_REJECT_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.CORE0_DBUS_REJECT_VADDR.Reg) +} + +// EXTMEM.CORE0_IBUS_REJECT_ST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR() uint32 { + return volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg) & 0x8) >> 3 +} + +// EXTMEM.CORE0_IBUS_REJECT_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.CORE0_IBUS_REJECT_VADDR.Reg) +} + +// EXTMEM.CACHE_MMU_FAULT_CONTENT: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_MMU_FAULT_CONTENT(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg, volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg)&^(0xff)|value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_FAULT_CONTENT() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg) & 0xff +} +func (o *EXTMEM_Type) SetCACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg, volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg)&^(0x3c00)|value<<10) +} +func (o *EXTMEM_Type) GetCACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg) & 0x3c00) >> 10 +} + +// EXTMEM.CACHE_MMU_FAULT_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_MMU_FAULT_VADDR(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_FAULT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_FAULT_VADDR() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_FAULT_VADDR.Reg) +} + +// EXTMEM.CACHE_WRAP_AROUND_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND(value uint32) { + volatile.StoreUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND() uint32 { + return volatile.LoadUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg) & 0x1 +} + +// EXTMEM.CACHE_MMU_POWER_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_STATE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_STATE_ICACHE_STATE(value uint32) { + volatile.StoreUint32(&o.CACHE_STATE.Reg, volatile.LoadUint32(&o.CACHE_STATE.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetCACHE_STATE_ICACHE_STATE() uint32 { + return volatile.LoadUint32(&o.CACHE_STATE.Reg) & 0xfff +} + +// EXTMEM.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg) & 0x2) >> 1 +} + +// EXTMEM.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT() uint32 { + return volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_PRELOAD_INT_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_SYNC_INT_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_MMU_OWNER: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_MMU_OWNER(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_OWNER.Reg, volatile.LoadUint32(&o.CACHE_MMU_OWNER.Reg)&^(0xf)|value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_OWNER() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_OWNER.Reg) & 0xf +} + +// EXTMEM.CACHE_CONF_MISC: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT() uint32 { + return volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_TRACE_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_TRACE_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_MMU_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x18)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_MMU_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x18) >> 3 +} + +// EXTMEM.ICACHE_FREEZE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_FREEZE_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_FREEZE.Reg, volatile.LoadUint32(&o.ICACHE_FREEZE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_FREEZE_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_FREEZE.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.ICACHE_FREEZE.Reg, volatile.LoadUint32(&o.ICACHE_FREEZE.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_FREEZE.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_FREEZE.Reg, volatile.LoadUint32(&o.ICACHE_FREEZE.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_FREEZE.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_ATOMIC_OPERATE_ENA: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_ATOMIC_OPERATE_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_ATOMIC_OPERATE_ENA.Reg, volatile.LoadUint32(&o.ICACHE_ATOMIC_OPERATE_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_ATOMIC_OPERATE_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_ATOMIC_OPERATE_ENA.Reg) & 0x1 +} + +// EXTMEM.CACHE_REQUEST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_REQUEST_BYPASS(value uint32) { + volatile.StoreUint32(&o.CACHE_REQUEST.Reg, volatile.LoadUint32(&o.CACHE_REQUEST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_REQUEST_BYPASS() uint32 { + return volatile.LoadUint32(&o.CACHE_REQUEST.Reg) & 0x1 +} + +// EXTMEM.CLOCK_GATE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// EXTMEM.REG_DATE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetREG_DATE_DATE(value uint32) { + volatile.StoreUint32(&o.REG_DATE.Reg, volatile.LoadUint32(&o.REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetREG_DATE_DATE() uint32 { + return volatile.LoadUint32(&o.REG_DATE.Reg) & 0xfffffff +} + +// General Purpose Input/Output +type GPIO_Type struct { + BT_SELECT volatile.Register32 // 0x0 + OUT volatile.Register32 // 0x4 + OUT_W1TS volatile.Register32 // 0x8 + OUT_W1TC volatile.Register32 // 0xC + _ [12]byte + SDIO_SELECT volatile.Register32 // 0x1C + ENABLE volatile.Register32 // 0x20 + ENABLE_W1TS volatile.Register32 // 0x24 + ENABLE_W1TC volatile.Register32 // 0x28 + _ [12]byte + STRAP volatile.Register32 // 0x38 + IN volatile.Register32 // 0x3C + _ [4]byte + STATUS volatile.Register32 // 0x44 + STATUS_W1TS volatile.Register32 // 0x48 + STATUS_W1TC volatile.Register32 // 0x4C + _ [12]byte + PCPU_INT volatile.Register32 // 0x5C + PCPU_NMI_INT volatile.Register32 // 0x60 + CPUSDIO_INT volatile.Register32 // 0x64 + _ [12]byte + PIN0 volatile.Register32 // 0x74 + PIN1 volatile.Register32 // 0x78 + PIN2 volatile.Register32 // 0x7C + PIN3 volatile.Register32 // 0x80 + PIN4 volatile.Register32 // 0x84 + PIN5 volatile.Register32 // 0x88 + PIN6 volatile.Register32 // 0x8C + PIN7 volatile.Register32 // 0x90 + PIN8 volatile.Register32 // 0x94 + PIN9 volatile.Register32 // 0x98 + PIN10 volatile.Register32 // 0x9C + PIN11 volatile.Register32 // 0xA0 + PIN12 volatile.Register32 // 0xA4 + PIN13 volatile.Register32 // 0xA8 + PIN14 volatile.Register32 // 0xAC + PIN15 volatile.Register32 // 0xB0 + PIN16 volatile.Register32 // 0xB4 + PIN17 volatile.Register32 // 0xB8 + PIN18 volatile.Register32 // 0xBC + PIN19 volatile.Register32 // 0xC0 + PIN20 volatile.Register32 // 0xC4 + PIN21 volatile.Register32 // 0xC8 + PIN22 volatile.Register32 // 0xCC + PIN23 volatile.Register32 // 0xD0 + PIN24 volatile.Register32 // 0xD4 + _ [116]byte + STATUS_NEXT volatile.Register32 // 0x14C + _ [4]byte + FUNC0_IN_SEL_CFG volatile.Register32 // 0x154 + FUNC1_IN_SEL_CFG volatile.Register32 // 0x158 + FUNC2_IN_SEL_CFG volatile.Register32 // 0x15C + FUNC3_IN_SEL_CFG volatile.Register32 // 0x160 + FUNC4_IN_SEL_CFG volatile.Register32 // 0x164 + FUNC5_IN_SEL_CFG volatile.Register32 // 0x168 + FUNC6_IN_SEL_CFG volatile.Register32 // 0x16C + FUNC7_IN_SEL_CFG volatile.Register32 // 0x170 + FUNC8_IN_SEL_CFG volatile.Register32 // 0x174 + FUNC9_IN_SEL_CFG volatile.Register32 // 0x178 + FUNC10_IN_SEL_CFG volatile.Register32 // 0x17C + FUNC11_IN_SEL_CFG volatile.Register32 // 0x180 + FUNC12_IN_SEL_CFG volatile.Register32 // 0x184 + FUNC13_IN_SEL_CFG volatile.Register32 // 0x188 + FUNC14_IN_SEL_CFG volatile.Register32 // 0x18C + FUNC15_IN_SEL_CFG volatile.Register32 // 0x190 + FUNC16_IN_SEL_CFG volatile.Register32 // 0x194 + FUNC17_IN_SEL_CFG volatile.Register32 // 0x198 + FUNC18_IN_SEL_CFG volatile.Register32 // 0x19C + FUNC19_IN_SEL_CFG volatile.Register32 // 0x1A0 + FUNC20_IN_SEL_CFG volatile.Register32 // 0x1A4 + FUNC21_IN_SEL_CFG volatile.Register32 // 0x1A8 + FUNC22_IN_SEL_CFG volatile.Register32 // 0x1AC + FUNC23_IN_SEL_CFG volatile.Register32 // 0x1B0 + FUNC24_IN_SEL_CFG volatile.Register32 // 0x1B4 + FUNC25_IN_SEL_CFG volatile.Register32 // 0x1B8 + FUNC26_IN_SEL_CFG volatile.Register32 // 0x1BC + FUNC27_IN_SEL_CFG volatile.Register32 // 0x1C0 + FUNC28_IN_SEL_CFG volatile.Register32 // 0x1C4 + FUNC29_IN_SEL_CFG volatile.Register32 // 0x1C8 + FUNC30_IN_SEL_CFG volatile.Register32 // 0x1CC + FUNC31_IN_SEL_CFG volatile.Register32 // 0x1D0 + FUNC32_IN_SEL_CFG volatile.Register32 // 0x1D4 + FUNC33_IN_SEL_CFG volatile.Register32 // 0x1D8 + FUNC34_IN_SEL_CFG volatile.Register32 // 0x1DC + FUNC35_IN_SEL_CFG volatile.Register32 // 0x1E0 + FUNC36_IN_SEL_CFG volatile.Register32 // 0x1E4 + FUNC37_IN_SEL_CFG volatile.Register32 // 0x1E8 + FUNC38_IN_SEL_CFG volatile.Register32 // 0x1EC + FUNC39_IN_SEL_CFG volatile.Register32 // 0x1F0 + FUNC40_IN_SEL_CFG volatile.Register32 // 0x1F4 + FUNC41_IN_SEL_CFG volatile.Register32 // 0x1F8 + FUNC42_IN_SEL_CFG volatile.Register32 // 0x1FC + FUNC43_IN_SEL_CFG volatile.Register32 // 0x200 + FUNC44_IN_SEL_CFG volatile.Register32 // 0x204 + FUNC45_IN_SEL_CFG volatile.Register32 // 0x208 + FUNC46_IN_SEL_CFG volatile.Register32 // 0x20C + FUNC47_IN_SEL_CFG volatile.Register32 // 0x210 + FUNC48_IN_SEL_CFG volatile.Register32 // 0x214 + FUNC49_IN_SEL_CFG volatile.Register32 // 0x218 + FUNC50_IN_SEL_CFG volatile.Register32 // 0x21C + FUNC51_IN_SEL_CFG volatile.Register32 // 0x220 + FUNC52_IN_SEL_CFG volatile.Register32 // 0x224 + FUNC53_IN_SEL_CFG volatile.Register32 // 0x228 + FUNC54_IN_SEL_CFG volatile.Register32 // 0x22C + FUNC55_IN_SEL_CFG volatile.Register32 // 0x230 + FUNC56_IN_SEL_CFG volatile.Register32 // 0x234 + FUNC57_IN_SEL_CFG volatile.Register32 // 0x238 + FUNC58_IN_SEL_CFG volatile.Register32 // 0x23C + FUNC59_IN_SEL_CFG volatile.Register32 // 0x240 + FUNC60_IN_SEL_CFG volatile.Register32 // 0x244 + FUNC61_IN_SEL_CFG volatile.Register32 // 0x248 + FUNC62_IN_SEL_CFG volatile.Register32 // 0x24C + FUNC63_IN_SEL_CFG volatile.Register32 // 0x250 + FUNC64_IN_SEL_CFG volatile.Register32 // 0x254 + FUNC65_IN_SEL_CFG volatile.Register32 // 0x258 + FUNC66_IN_SEL_CFG volatile.Register32 // 0x25C + FUNC67_IN_SEL_CFG volatile.Register32 // 0x260 + FUNC68_IN_SEL_CFG volatile.Register32 // 0x264 + FUNC69_IN_SEL_CFG volatile.Register32 // 0x268 + FUNC70_IN_SEL_CFG volatile.Register32 // 0x26C + FUNC71_IN_SEL_CFG volatile.Register32 // 0x270 + FUNC72_IN_SEL_CFG volatile.Register32 // 0x274 + FUNC73_IN_SEL_CFG volatile.Register32 // 0x278 + FUNC74_IN_SEL_CFG volatile.Register32 // 0x27C + FUNC75_IN_SEL_CFG volatile.Register32 // 0x280 + FUNC76_IN_SEL_CFG volatile.Register32 // 0x284 + FUNC77_IN_SEL_CFG volatile.Register32 // 0x288 + FUNC78_IN_SEL_CFG volatile.Register32 // 0x28C + FUNC79_IN_SEL_CFG volatile.Register32 // 0x290 + FUNC80_IN_SEL_CFG volatile.Register32 // 0x294 + FUNC81_IN_SEL_CFG volatile.Register32 // 0x298 + FUNC82_IN_SEL_CFG volatile.Register32 // 0x29C + FUNC83_IN_SEL_CFG volatile.Register32 // 0x2A0 + FUNC84_IN_SEL_CFG volatile.Register32 // 0x2A4 + FUNC85_IN_SEL_CFG volatile.Register32 // 0x2A8 + FUNC86_IN_SEL_CFG volatile.Register32 // 0x2AC + FUNC87_IN_SEL_CFG volatile.Register32 // 0x2B0 + FUNC88_IN_SEL_CFG volatile.Register32 // 0x2B4 + FUNC89_IN_SEL_CFG volatile.Register32 // 0x2B8 + FUNC90_IN_SEL_CFG volatile.Register32 // 0x2BC + FUNC91_IN_SEL_CFG volatile.Register32 // 0x2C0 + FUNC92_IN_SEL_CFG volatile.Register32 // 0x2C4 + FUNC93_IN_SEL_CFG volatile.Register32 // 0x2C8 + FUNC94_IN_SEL_CFG volatile.Register32 // 0x2CC + FUNC95_IN_SEL_CFG volatile.Register32 // 0x2D0 + FUNC96_IN_SEL_CFG volatile.Register32 // 0x2D4 + FUNC97_IN_SEL_CFG volatile.Register32 // 0x2D8 + FUNC98_IN_SEL_CFG volatile.Register32 // 0x2DC + FUNC99_IN_SEL_CFG volatile.Register32 // 0x2E0 + FUNC100_IN_SEL_CFG volatile.Register32 // 0x2E4 + FUNC101_IN_SEL_CFG volatile.Register32 // 0x2E8 + FUNC102_IN_SEL_CFG volatile.Register32 // 0x2EC + FUNC103_IN_SEL_CFG volatile.Register32 // 0x2F0 + FUNC104_IN_SEL_CFG volatile.Register32 // 0x2F4 + FUNC105_IN_SEL_CFG volatile.Register32 // 0x2F8 + FUNC106_IN_SEL_CFG volatile.Register32 // 0x2FC + FUNC107_IN_SEL_CFG volatile.Register32 // 0x300 + FUNC108_IN_SEL_CFG volatile.Register32 // 0x304 + FUNC109_IN_SEL_CFG volatile.Register32 // 0x308 + FUNC110_IN_SEL_CFG volatile.Register32 // 0x30C + FUNC111_IN_SEL_CFG volatile.Register32 // 0x310 + FUNC112_IN_SEL_CFG volatile.Register32 // 0x314 + FUNC113_IN_SEL_CFG volatile.Register32 // 0x318 + FUNC114_IN_SEL_CFG volatile.Register32 // 0x31C + FUNC115_IN_SEL_CFG volatile.Register32 // 0x320 + FUNC116_IN_SEL_CFG volatile.Register32 // 0x324 + FUNC117_IN_SEL_CFG volatile.Register32 // 0x328 + FUNC118_IN_SEL_CFG volatile.Register32 // 0x32C + FUNC119_IN_SEL_CFG volatile.Register32 // 0x330 + FUNC120_IN_SEL_CFG volatile.Register32 // 0x334 + FUNC121_IN_SEL_CFG volatile.Register32 // 0x338 + FUNC122_IN_SEL_CFG volatile.Register32 // 0x33C + FUNC123_IN_SEL_CFG volatile.Register32 // 0x340 + FUNC124_IN_SEL_CFG volatile.Register32 // 0x344 + FUNC125_IN_SEL_CFG volatile.Register32 // 0x348 + FUNC126_IN_SEL_CFG volatile.Register32 // 0x34C + FUNC127_IN_SEL_CFG volatile.Register32 // 0x350 + _ [512]byte + FUNC0_OUT_SEL_CFG volatile.Register32 // 0x554 + FUNC1_OUT_SEL_CFG volatile.Register32 // 0x558 + FUNC2_OUT_SEL_CFG volatile.Register32 // 0x55C + FUNC3_OUT_SEL_CFG volatile.Register32 // 0x560 + FUNC4_OUT_SEL_CFG volatile.Register32 // 0x564 + FUNC5_OUT_SEL_CFG volatile.Register32 // 0x568 + FUNC6_OUT_SEL_CFG volatile.Register32 // 0x56C + FUNC7_OUT_SEL_CFG volatile.Register32 // 0x570 + FUNC8_OUT_SEL_CFG volatile.Register32 // 0x574 + FUNC9_OUT_SEL_CFG volatile.Register32 // 0x578 + FUNC10_OUT_SEL_CFG volatile.Register32 // 0x57C + FUNC11_OUT_SEL_CFG volatile.Register32 // 0x580 + FUNC12_OUT_SEL_CFG volatile.Register32 // 0x584 + FUNC13_OUT_SEL_CFG volatile.Register32 // 0x588 + FUNC14_OUT_SEL_CFG volatile.Register32 // 0x58C + FUNC15_OUT_SEL_CFG volatile.Register32 // 0x590 + FUNC16_OUT_SEL_CFG volatile.Register32 // 0x594 + FUNC17_OUT_SEL_CFG volatile.Register32 // 0x598 + FUNC18_OUT_SEL_CFG volatile.Register32 // 0x59C + FUNC19_OUT_SEL_CFG volatile.Register32 // 0x5A0 + FUNC20_OUT_SEL_CFG volatile.Register32 // 0x5A4 + FUNC21_OUT_SEL_CFG volatile.Register32 // 0x5A8 + FUNC22_OUT_SEL_CFG volatile.Register32 // 0x5AC + FUNC23_OUT_SEL_CFG volatile.Register32 // 0x5B0 + FUNC24_OUT_SEL_CFG volatile.Register32 // 0x5B4 + _ [116]byte + CLOCK_GATE volatile.Register32 // 0x62C + _ [204]byte + REG_DATE volatile.Register32 // 0x6FC +} + +// GPIO.BT_SELECT: GPIO bit select register +func (o *GPIO_Type) SetBT_SELECT(value uint32) { + volatile.StoreUint32(&o.BT_SELECT.Reg, value) +} +func (o *GPIO_Type) GetBT_SELECT() uint32 { + return volatile.LoadUint32(&o.BT_SELECT.Reg) +} + +// GPIO.OUT: GPIO output register +func (o *GPIO_Type) SetOUT_DATA_ORIG(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, volatile.LoadUint32(&o.OUT.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetOUT_DATA_ORIG() uint32 { + return volatile.LoadUint32(&o.OUT.Reg) & 0x1ffffff +} + +// GPIO.OUT_W1TS: GPIO output set register +func (o *GPIO_Type) SetOUT_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, volatile.LoadUint32(&o.OUT_W1TS.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetOUT_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_W1TS.Reg) & 0x1ffffff +} + +// GPIO.OUT_W1TC: GPIO output clear register +func (o *GPIO_Type) SetOUT_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, volatile.LoadUint32(&o.OUT_W1TC.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetOUT_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_W1TC.Reg) & 0x1ffffff +} + +// GPIO.SDIO_SELECT: GPIO sdio select register +func (o *GPIO_Type) SetSDIO_SELECT_SDIO_SEL(value uint32) { + volatile.StoreUint32(&o.SDIO_SELECT.Reg, volatile.LoadUint32(&o.SDIO_SELECT.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSDIO_SELECT_SDIO_SEL() uint32 { + return volatile.LoadUint32(&o.SDIO_SELECT.Reg) & 0xff +} + +// GPIO.ENABLE: GPIO output enable register +func (o *GPIO_Type) SetENABLE_DATA(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, volatile.LoadUint32(&o.ENABLE.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetENABLE_DATA() uint32 { + return volatile.LoadUint32(&o.ENABLE.Reg) & 0x1ffffff +} + +// GPIO.ENABLE_W1TS: GPIO output enable set register +func (o *GPIO_Type) SetENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, volatile.LoadUint32(&o.ENABLE_W1TS.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) & 0x1ffffff +} + +// GPIO.ENABLE_W1TC: GPIO output enable clear register +func (o *GPIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, volatile.LoadUint32(&o.ENABLE_W1TC.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) & 0x1ffffff +} + +// GPIO.STRAP: pad strapping register +func (o *GPIO_Type) SetSTRAP_STRAPPING(value uint32) { + volatile.StoreUint32(&o.STRAP.Reg, volatile.LoadUint32(&o.STRAP.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetSTRAP_STRAPPING() uint32 { + return volatile.LoadUint32(&o.STRAP.Reg) & 0xffff +} + +// GPIO.IN: GPIO input register +func (o *GPIO_Type) SetIN_DATA_NEXT(value uint32) { + volatile.StoreUint32(&o.IN.Reg, volatile.LoadUint32(&o.IN.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetIN_DATA_NEXT() uint32 { + return volatile.LoadUint32(&o.IN.Reg) & 0x1ffffff +} + +// GPIO.STATUS: GPIO interrupt status register +func (o *GPIO_Type) SetSTATUS_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1ffffff +} + +// GPIO.STATUS_W1TS: GPIO interrupt status set register +func (o *GPIO_Type) SetSTATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, volatile.LoadUint32(&o.STATUS_W1TS.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) & 0x1ffffff +} + +// GPIO.STATUS_W1TC: GPIO interrupt status clear register +func (o *GPIO_Type) SetSTATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, volatile.LoadUint32(&o.STATUS_W1TC.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) & 0x1ffffff +} + +// GPIO.PCPU_INT: GPIO PRO_CPU interrupt status register +func (o *GPIO_Type) SetPCPU_INT_PROCPU_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_INT.Reg, volatile.LoadUint32(&o.PCPU_INT.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetPCPU_INT_PROCPU_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_INT.Reg) & 0x1ffffff +} + +// GPIO.PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register +func (o *GPIO_Type) SetPCPU_NMI_INT_PROCPU_NMI_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT.Reg, volatile.LoadUint32(&o.PCPU_NMI_INT.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT_PROCPU_NMI_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT.Reg) & 0x1ffffff +} + +// GPIO.CPUSDIO_INT: GPIO CPUSDIO interrupt status register +func (o *GPIO_Type) SetCPUSDIO_INT_SDIO_INT(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT.Reg, volatile.LoadUint32(&o.CPUSDIO_INT.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetCPUSDIO_INT_SDIO_INT() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT.Reg) & 0x1ffffff +} + +// GPIO.PIN0: GPIO pin configuration register +func (o *GPIO_Type) SetPIN0_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN0_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN0_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN0_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN0_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN0_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN1: GPIO pin configuration register +func (o *GPIO_Type) SetPIN1_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN1_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN1_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN1_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN1_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN1_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN2: GPIO pin configuration register +func (o *GPIO_Type) SetPIN2_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN2_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN2_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN2_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN2_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN2_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN3: GPIO pin configuration register +func (o *GPIO_Type) SetPIN3_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN3_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN3_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN3_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN3_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN3_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN4: GPIO pin configuration register +func (o *GPIO_Type) SetPIN4_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN4_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN4_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN4_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN4_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN4_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN5: GPIO pin configuration register +func (o *GPIO_Type) SetPIN5_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN5_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN5_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN5_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN5_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN5_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN6: GPIO pin configuration register +func (o *GPIO_Type) SetPIN6_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN6_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN6_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN6_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN6_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN6_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN7: GPIO pin configuration register +func (o *GPIO_Type) SetPIN7_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN7_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN7_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN7_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN7_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN7_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN8: GPIO pin configuration register +func (o *GPIO_Type) SetPIN8_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN8_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN8.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN8_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN8_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN8_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN8_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN9: GPIO pin configuration register +func (o *GPIO_Type) SetPIN9_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN9_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN9.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN9_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN9_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN9_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN9_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN10: GPIO pin configuration register +func (o *GPIO_Type) SetPIN10_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN10_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN10.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN10_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN10_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN10_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN10_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN10_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN10_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN11: GPIO pin configuration register +func (o *GPIO_Type) SetPIN11_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN11_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN11.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN11_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN11_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN11_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN11_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN11_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN11_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN12: GPIO pin configuration register +func (o *GPIO_Type) SetPIN12_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN12_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN12.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN12_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN12_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN12_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN12_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN12_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN12_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN13: GPIO pin configuration register +func (o *GPIO_Type) SetPIN13_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN13_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN13.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN13_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN13_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN13_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN13_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN13_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN13_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN14: GPIO pin configuration register +func (o *GPIO_Type) SetPIN14_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN14_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN14.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN14_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN14_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN14_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN14_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN14_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN14_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN15: GPIO pin configuration register +func (o *GPIO_Type) SetPIN15_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN15_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN15.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN15_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN15_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN15_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN15_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN15_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN15_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN16: GPIO pin configuration register +func (o *GPIO_Type) SetPIN16_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN16_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN16.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN16_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN16_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN16_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN16_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN16_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN16_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN17: GPIO pin configuration register +func (o *GPIO_Type) SetPIN17_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN17_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN17.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN17_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN17_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN17_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN17_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN17_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN17_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN18: GPIO pin configuration register +func (o *GPIO_Type) SetPIN18_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN18_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN18.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN18_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN18_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN18_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN18_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN18_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN18_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN19: GPIO pin configuration register +func (o *GPIO_Type) SetPIN19_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN19_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN19.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN19_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN19_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN19_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN19_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN19_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN19_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN20: GPIO pin configuration register +func (o *GPIO_Type) SetPIN20_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN20_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN20.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN20_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN20_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN20_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN20_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN20_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN20_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN21: GPIO pin configuration register +func (o *GPIO_Type) SetPIN21_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN21_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN21.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN21_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN21_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN21_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN21_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN21_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN21_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN22: GPIO pin configuration register +func (o *GPIO_Type) SetPIN22_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN22_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN22.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN22_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN22_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN22_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN22_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN22_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN22_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN22_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN22_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN22_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN22_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN22_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN22_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN23: GPIO pin configuration register +func (o *GPIO_Type) SetPIN23_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN23_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN23.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN23_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN23_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN23_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN23_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN23_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN23_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN23_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN23_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN23_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN23_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN23_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN23_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN24: GPIO pin configuration register +func (o *GPIO_Type) SetPIN24_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN24_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN24.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN24_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN24_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN24_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN24_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN24_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN24_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN24_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN24_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN24_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN24_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN24_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN24_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x3e000) >> 13 +} + +// GPIO.STATUS_NEXT: GPIO interrupt source register +func (o *GPIO_Type) SetSTATUS_NEXT_STATUS_INTERRUPT_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT.Reg, volatile.LoadUint32(&o.STATUS_NEXT.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS_NEXT_STATUS_INTERRUPT_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT.Reg) & 0x3ffffff +} + +// GPIO.FUNC0_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC1_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC2_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC3_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC4_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC5_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC6_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC7_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC8_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC9_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC10_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC11_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC12_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC13_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC14_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC15_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC16_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC17_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC18_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC19_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC20_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC21_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC22_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC23_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC24_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC25_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC26_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC27_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC28_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC29_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC30_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC31_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC32_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC33_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC34_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC35_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC36_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC37_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC38_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC39_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC40_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC41_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC42_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC43_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC44_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC45_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC46_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC47_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC48_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC49_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC50_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC51_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC52_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC53_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC54_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC55_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC56_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC57_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC58_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC59_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC60_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC61_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC62_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC63_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC64_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC65_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC66_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC67_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC68_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC69_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC70_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC71_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC72_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC73_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC74_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC75_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC76_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC77_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC78_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC79_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC80_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC81_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC82_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC83_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC84_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC85_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC86_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC87_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC88_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC89_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC90_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC91_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC92_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC93_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC94_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC95_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC96_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC97_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC98_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC99_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC100_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC101_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC102_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC103_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC104_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC105_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC106_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC107_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC108_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC109_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC110_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC111_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC112_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC113_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC114_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC115_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC116_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC117_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC118_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC119_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC120_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC121_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC122_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC123_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC124_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC125_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC126_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC127_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC0_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC1_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC2_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC3_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC4_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC5_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC6_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC7_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC8_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC9_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC10_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC11_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC12_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC13_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC14_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC15_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC16_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC17_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC18_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC19_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC20_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC21_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC22_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC23_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC24_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.CLOCK_GATE: GPIO clock gate register +func (o *GPIO_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIO.REG_DATE: GPIO version register +func (o *GPIO_Type) SetREG_DATE(value uint32) { + volatile.StoreUint32(&o.REG_DATE.Reg, volatile.LoadUint32(&o.REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *GPIO_Type) GetREG_DATE() uint32 { + return volatile.LoadUint32(&o.REG_DATE.Reg) & 0xfffffff +} + +// I2C (Inter-Integrated Circuit) Controller 0 +type I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + _ [4]byte + FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + FILTER_CFG volatile.Register32 // 0x50 + CLK_CONF volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + SCL_ST_TIME_OUT volatile.Register32 // 0x78 + SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C + SCL_SP_CONF volatile.Register32 // 0x80 + _ [116]byte + DATE volatile.Register32 // 0xF8 + _ [4]byte + TXFIFO_START_ADDR volatile.Register32 // 0x100 + _ [124]byte + RXFIFO_START_ADDR volatile.Register32 // 0x180 +} + +// I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL Clock +func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff +} + +// I2C.CTR: Transmission setting +func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetCTR_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetCTR_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetCTR_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetCTR_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetCTR_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetCTR_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetCTR_CONF_UPGATE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetCTR_CONF_UPGATE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetCTR_SLV_TX_AUTO_START_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetCTR_SLV_TX_AUTO_START_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x1000) >> 12 +} + +// I2C.SR: Describe I2C work status. +func (o *I2C_Type) SetSR_RESP_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSR_RESP_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1f00)|value<<8) +} +func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x1f00) >> 8 +} +func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7c0000)|value<<18) +} +func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7c0000) >> 18 +} +func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// I2C.TO: Setting time out control for receiving data. +func (o *I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetTO_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0x1f +} +func (o *I2C_Type) SetTO_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetTO_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5 +} + +// I2C.FIFO_ST: FIFO status register. +func (o *I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 { + return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf +} +func (o *I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1e0) >> 5 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3c00)|value<<10) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3c00) >> 10 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x78000)|value<<15) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x78000) >> 15 +} + +// I2C.FIFO_CONF: FIFO configuration register. +func (o *I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xf +} +func (o *I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1e0) >> 5 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14 +} + +// I2C.DATA: Rx FIFO read data. +func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// I2C.INT_RAW: Raw interrupt status +func (o *I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} + +// I2C.INT_CLR: Interrupt clear bits +func (o *I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} + +// I2C.INT_ENA: Interrupt enable bits +func (o *I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} + +// I2C.INT_STATUS: Status of captured I2C communication events +func (o *I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15 +} + +// I2C.SDA_HOLD: Configures the hold time after a negative SCL edge. +func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff +} + +// I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge. +func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff +} + +// I2C.SCL_HIGH_PERIOD: Configures the high level width of SCL +func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff +} +func (o *I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9 +} + +// I2C.SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition +func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA +func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff +} + +// I2C.FILTER_CFG: SCL and SDA filter configuration register +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4 +} +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9 +} + +// I2C.CLK_CONF: I2C CLK configuration register +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} + +// I2C.COMD0: I2C command register %s +func (o *I2C_Type) SetCOMD0_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD0_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD0_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD0_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD1: I2C command register %s +func (o *I2C_Type) SetCOMD1_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD1_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD1_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD1_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD2: I2C command register %s +func (o *I2C_Type) SetCOMD2_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD2_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD2_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD2_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD3: I2C command register %s +func (o *I2C_Type) SetCOMD3_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD3_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD3_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD3_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD4: I2C command register %s +func (o *I2C_Type) SetCOMD4_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD4_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD4_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD4_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD5: I2C command register %s +func (o *I2C_Type) SetCOMD5_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD5_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD5_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD5_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD6: I2C command register %s +func (o *I2C_Type) SetCOMD6_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD6_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD6_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD6_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD7: I2C command register %s +func (o *I2C_Type) SetCOMD7_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD7_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD7_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD7_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// I2C.SCL_ST_TIME_OUT: SCL status time out register +func (o *I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register +func (o *I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_SP_CONF: Power configuration register +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// I2C.DATE: Version register +func (o *I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2C.TXFIFO_START_ADDR: I2C TXFIFO base address register +func (o *I2C_Type) SetTXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetTXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg) +} + +// I2C.RXFIFO_START_ADDR: I2C RXFIFO base address register +func (o *I2C_Type) SetRXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetRXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg) +} + +// Interrupt Controller (Core 0) +type INTERRUPT_CORE0_Type struct { + MAC_INTR_MAP volatile.Register32 // 0x0 + WIFI_MAC_NMI_MAP volatile.Register32 // 0x4 + WIFI_PWR_INT_MAP volatile.Register32 // 0x8 + WIFI_BB_INT_MAP volatile.Register32 // 0xC + BT_MAC_INT_MAP volatile.Register32 // 0x10 + BT_BB_INT_MAP volatile.Register32 // 0x14 + BT_BB_NMI_MAP volatile.Register32 // 0x18 + LP_TIMER_INT_MAP volatile.Register32 // 0x1C + COEX_INT_MAP volatile.Register32 // 0x20 + BLE_TIMER_INT_MAP volatile.Register32 // 0x24 + BLE_SEC_INT_MAP volatile.Register32 // 0x28 + I2C_MST_INT_MAP volatile.Register32 // 0x2C + APB_CTRL_INTR_MAP volatile.Register32 // 0x30 + GPIO_INTERRUPT_PRO_MAP volatile.Register32 // 0x34 + GPIO_INTERRUPT_PRO_NMI_MAP volatile.Register32 // 0x38 + SPI_INTR_1_MAP volatile.Register32 // 0x3C + SPI_INTR_2_MAP volatile.Register32 // 0x40 + UART_INTR_MAP volatile.Register32 // 0x44 + UART1_INTR_MAP volatile.Register32 // 0x48 + LEDC_INT_MAP volatile.Register32 // 0x4C + EFUSE_INT_MAP volatile.Register32 // 0x50 + RTC_CORE_INTR_MAP volatile.Register32 // 0x54 + I2C_EXT0_INTR_MAP volatile.Register32 // 0x58 + TG_T0_INT_MAP volatile.Register32 // 0x5C + TG_WDT_INT_MAP volatile.Register32 // 0x60 + CACHE_IA_INT_MAP volatile.Register32 // 0x64 + SYSTIMER_TARGET0_INT_MAP volatile.Register32 // 0x68 + SYSTIMER_TARGET1_INT_MAP volatile.Register32 // 0x6C + SYSTIMER_TARGET2_INT_MAP volatile.Register32 // 0x70 + SPI_MEM_REJECT_INTR_MAP volatile.Register32 // 0x74 + ICACHE_PRELOAD_INT_MAP volatile.Register32 // 0x78 + ICACHE_SYNC_INT_MAP volatile.Register32 // 0x7C + APB_ADC_INT_MAP volatile.Register32 // 0x80 + DMA_CH0_INT_MAP volatile.Register32 // 0x84 + SHA_INT_MAP volatile.Register32 // 0x88 + ECC_INT_MAP volatile.Register32 // 0x8C + CPU_INTR_FROM_CPU_0_MAP volatile.Register32 // 0x90 + CPU_INTR_FROM_CPU_1_MAP volatile.Register32 // 0x94 + CPU_INTR_FROM_CPU_2_MAP volatile.Register32 // 0x98 + CPU_INTR_FROM_CPU_3_MAP volatile.Register32 // 0x9C + ASSIST_DEBUG_INTR_MAP volatile.Register32 // 0xA0 + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP volatile.Register32 // 0xA4 + CACHE_CORE0_ACS_INT_MAP volatile.Register32 // 0xA8 + INTR_STATUS_REG_0 volatile.Register32 // 0xAC + INTR_STATUS_REG_1 volatile.Register32 // 0xB0 + CLOCK_GATE volatile.Register32 // 0xB4 + CPU_INT_ENABLE volatile.Register32 // 0xB8 + CPU_INT_TYPE volatile.Register32 // 0xBC + CPU_INT_CLEAR volatile.Register32 // 0xC0 + CPU_INT_EIP_STATUS volatile.Register32 // 0xC4 + CPU_INT_PRI_0 volatile.Register32 // 0xC8 + CPU_INT_PRI_1 volatile.Register32 // 0xCC + CPU_INT_PRI_2 volatile.Register32 // 0xD0 + CPU_INT_PRI_3 volatile.Register32 // 0xD4 + CPU_INT_PRI_4 volatile.Register32 // 0xD8 + CPU_INT_PRI_5 volatile.Register32 // 0xDC + CPU_INT_PRI_6 volatile.Register32 // 0xE0 + CPU_INT_PRI_7 volatile.Register32 // 0xE4 + CPU_INT_PRI_8 volatile.Register32 // 0xE8 + CPU_INT_PRI_9 volatile.Register32 // 0xEC + CPU_INT_PRI_10 volatile.Register32 // 0xF0 + CPU_INT_PRI_11 volatile.Register32 // 0xF4 + CPU_INT_PRI_12 volatile.Register32 // 0xF8 + CPU_INT_PRI_13 volatile.Register32 // 0xFC + CPU_INT_PRI_14 volatile.Register32 // 0x100 + CPU_INT_PRI_15 volatile.Register32 // 0x104 + CPU_INT_PRI_16 volatile.Register32 // 0x108 + CPU_INT_PRI_17 volatile.Register32 // 0x10C + CPU_INT_PRI_18 volatile.Register32 // 0x110 + CPU_INT_PRI_19 volatile.Register32 // 0x114 + CPU_INT_PRI_20 volatile.Register32 // 0x118 + CPU_INT_PRI_21 volatile.Register32 // 0x11C + CPU_INT_PRI_22 volatile.Register32 // 0x120 + CPU_INT_PRI_23 volatile.Register32 // 0x124 + CPU_INT_PRI_24 volatile.Register32 // 0x128 + CPU_INT_PRI_25 volatile.Register32 // 0x12C + CPU_INT_PRI_26 volatile.Register32 // 0x130 + CPU_INT_PRI_27 volatile.Register32 // 0x134 + CPU_INT_PRI_28 volatile.Register32 // 0x138 + CPU_INT_PRI_29 volatile.Register32 // 0x13C + CPU_INT_PRI_30 volatile.Register32 // 0x140 + CPU_INT_PRI_31 volatile.Register32 // 0x144 + CPU_INT_THRESH volatile.Register32 // 0x148 + _ [1712]byte + INTERRUPT_REG_DATE volatile.Register32 // 0x7FC +} + +// INTERRUPT_CORE0.MAC_INTR_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetMAC_INTR_MAP_WIFI_MAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetMAC_INTR_MAP_WIFI_MAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.MAC_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.WIFI_MAC_NMI_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetWIFI_MAC_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.WIFI_MAC_NMI_MAP.Reg, volatile.LoadUint32(&o.WIFI_MAC_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetWIFI_MAC_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.WIFI_MAC_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.WIFI_PWR_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetWIFI_PWR_INT_MAP(value uint32) { + volatile.StoreUint32(&o.WIFI_PWR_INT_MAP.Reg, volatile.LoadUint32(&o.WIFI_PWR_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetWIFI_PWR_INT_MAP() uint32 { + return volatile.LoadUint32(&o.WIFI_PWR_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.WIFI_BB_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetWIFI_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_INT_MAP.Reg, volatile.LoadUint32(&o.WIFI_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetWIFI_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BT_MAC_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetBT_MAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BT_MAC_INT_MAP.Reg, volatile.LoadUint32(&o.BT_MAC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBT_MAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BT_MAC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BT_BB_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetBT_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_INT_MAP.Reg, volatile.LoadUint32(&o.BT_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBT_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BT_BB_NMI_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetBT_BB_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_NMI_MAP.Reg, volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBT_BB_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.LP_TIMER_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetLP_TIMER_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetLP_TIMER_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TIMER_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.COEX_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetCOEX_INT_MAP(value uint32) { + volatile.StoreUint32(&o.COEX_INT_MAP.Reg, volatile.LoadUint32(&o.COEX_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCOEX_INT_MAP() uint32 { + return volatile.LoadUint32(&o.COEX_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BLE_TIMER_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetBLE_TIMER_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BLE_TIMER_INT_MAP.Reg, volatile.LoadUint32(&o.BLE_TIMER_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBLE_TIMER_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BLE_TIMER_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BLE_SEC_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetBLE_SEC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BLE_SEC_INT_MAP.Reg, volatile.LoadUint32(&o.BLE_SEC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBLE_SEC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BLE_SEC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2C_MST_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetI2C_MST_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_MST_INT_MAP.Reg, volatile.LoadUint32(&o.I2C_MST_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2C_MST_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_MST_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.APB_CTRL_INTR_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetAPB_CTRL_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APB_CTRL_INTR_MAP.Reg, volatile.LoadUint32(&o.APB_CTRL_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetAPB_CTRL_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APB_CTRL_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.GPIO_INTERRUPT_PRO_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetGPIO_INTERRUPT_PRO_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetGPIO_INTERRUPT_PRO_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.GPIO_INTERRUPT_PRO_NMI_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetGPIO_INTERRUPT_PRO_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetGPIO_INTERRUPT_PRO_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_INTR_1_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetSPI_INTR_1_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_1_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_INTR_1_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_INTR_2_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetSPI_INTR_2_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_2_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_INTR_2_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UART_INTR_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetUART_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART_INTR_MAP.Reg, volatile.LoadUint32(&o.UART_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUART_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UART1_INTR_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetUART1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART1_INTR_MAP.Reg, volatile.LoadUint32(&o.UART1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUART1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.LEDC_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetLEDC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.LEDC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetLEDC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LEDC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.EFUSE_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetEFUSE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.EFUSE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetEFUSE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.EFUSE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RTC_CORE_INTR_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetRTC_CORE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RTC_CORE_INTR_MAP.Reg, volatile.LoadUint32(&o.RTC_CORE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRTC_CORE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RTC_CORE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2C_EXT0_INTR_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetI2C_EXT0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_EXT0_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2C_EXT0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG_T0_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetTG_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TG_T0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_T0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG_WDT_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetTG_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TG_WDT_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_WDT_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CACHE_IA_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetCACHE_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCACHE_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_IA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SYSTIMER_TARGET0_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetSYSTIMER_TARGET0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSYSTIMER_TARGET0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SYSTIMER_TARGET1_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetSYSTIMER_TARGET1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSYSTIMER_TARGET1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SYSTIMER_TARGET2_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetSYSTIMER_TARGET2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSYSTIMER_TARGET2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_MEM_REJECT_INTR_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetSPI_MEM_REJECT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg, volatile.LoadUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_MEM_REJECT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ICACHE_PRELOAD_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetICACHE_PRELOAD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetICACHE_PRELOAD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ICACHE_SYNC_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetICACHE_SYNC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_INT_MAP.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetICACHE_SYNC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.APB_ADC_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetAPB_ADC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APB_ADC_INT_MAP.Reg, volatile.LoadUint32(&o.APB_ADC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetAPB_ADC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APB_ADC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_CH0_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetDMA_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_CH0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_CH0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SHA_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetSHA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SHA_INT_MAP.Reg, volatile.LoadUint32(&o.SHA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSHA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SHA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ECC_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetECC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ECC_INT_MAP.Reg, volatile.LoadUint32(&o.ECC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetECC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ECC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_0_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_1_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_2_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_3_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ASSIST_DEBUG_INTR_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetASSIST_DEBUG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetASSIST_DEBUG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetCORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CACHE_CORE0_ACS_INT_MAP: register description +func (o *INTERRUPT_CORE0_Type) SetCACHE_CORE0_ACS_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCACHE_CORE0_ACS_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.INTR_STATUS_REG_0: register description +func (o *INTERRUPT_CORE0_Type) SetINTR_STATUS_REG_0(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_0.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetINTR_STATUS_REG_0() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_0.Reg) +} + +// INTERRUPT_CORE0.INTR_STATUS_REG_1: register description +func (o *INTERRUPT_CORE0_Type) SetINTR_STATUS_REG_1(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_1.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetINTR_STATUS_REG_1() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_1.Reg) +} + +// INTERRUPT_CORE0.CLOCK_GATE: register description +func (o *INTERRUPT_CORE0_Type) SetCLOCK_GATE_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCLOCK_GATE_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// INTERRUPT_CORE0.CPU_INT_ENABLE: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.CPU_INT_ENABLE.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_ENABLE() uint32 { + return volatile.LoadUint32(&o.CPU_INT_ENABLE.Reg) +} + +// INTERRUPT_CORE0.CPU_INT_TYPE: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CPU_INT_TYPE.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_TYPE() uint32 { + return volatile.LoadUint32(&o.CPU_INT_TYPE.Reg) +} + +// INTERRUPT_CORE0.CPU_INT_CLEAR: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.CPU_INT_CLEAR.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_CLEAR() uint32 { + return volatile.LoadUint32(&o.CPU_INT_CLEAR.Reg) +} + +// INTERRUPT_CORE0.CPU_INT_EIP_STATUS: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_EIP_STATUS(value uint32) { + volatile.StoreUint32(&o.CPU_INT_EIP_STATUS.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_EIP_STATUS() uint32 { + return volatile.LoadUint32(&o.CPU_INT_EIP_STATUS.Reg) +} + +// INTERRUPT_CORE0.CPU_INT_PRI_0: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_0_CPU_PRI_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_0.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_0.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_0_CPU_PRI_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_0.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_1: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_1_CPU_PRI_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_1.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_1.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_1_CPU_PRI_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_1.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_2: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_2_CPU_PRI_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_2.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_2.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_2_CPU_PRI_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_2.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_3: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_3_CPU_PRI_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_3.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_3.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_3_CPU_PRI_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_3.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_4: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_4_CPU_PRI_4_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_4.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_4.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_4_CPU_PRI_4_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_4.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_5: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_5_CPU_PRI_5_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_5.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_5.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_5_CPU_PRI_5_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_5.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_6: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_6_CPU_PRI_6_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_6.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_6.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_6_CPU_PRI_6_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_6.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_7: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_7_CPU_PRI_7_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_7.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_7.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_7_CPU_PRI_7_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_7.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_8: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_8_CPU_PRI_8_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_8.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_8.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_8_CPU_PRI_8_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_8.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_9: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_9_CPU_PRI_9_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_9.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_9.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_9_CPU_PRI_9_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_9.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_10: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_10_CPU_PRI_10_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_10.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_10.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_10_CPU_PRI_10_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_10.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_11: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_11_CPU_PRI_11_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_11.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_11.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_11_CPU_PRI_11_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_11.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_12: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_12_CPU_PRI_12_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_12.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_12.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_12_CPU_PRI_12_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_12.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_13: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_13_CPU_PRI_13_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_13.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_13.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_13_CPU_PRI_13_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_13.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_14: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_14_CPU_PRI_14_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_14.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_14.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_14_CPU_PRI_14_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_14.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_15: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_15_CPU_PRI_15_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_15.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_15.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_15_CPU_PRI_15_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_15.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_16: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_16_CPU_PRI_16_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_16.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_16.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_16_CPU_PRI_16_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_16.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_17: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_17_CPU_PRI_17_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_17.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_17.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_17_CPU_PRI_17_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_17.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_18: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_18_CPU_PRI_18_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_18.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_18.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_18_CPU_PRI_18_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_18.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_19: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_19_CPU_PRI_19_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_19.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_19.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_19_CPU_PRI_19_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_19.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_20: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_20_CPU_PRI_20_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_20.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_20.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_20_CPU_PRI_20_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_20.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_21: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_21_CPU_PRI_21_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_21.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_21.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_21_CPU_PRI_21_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_21.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_22: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_22_CPU_PRI_22_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_22.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_22.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_22_CPU_PRI_22_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_22.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_23: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_23_CPU_PRI_23_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_23.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_23.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_23_CPU_PRI_23_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_23.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_24: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_24_CPU_PRI_24_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_24.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_24.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_24_CPU_PRI_24_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_24.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_25: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_25_CPU_PRI_25_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_25.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_25.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_25_CPU_PRI_25_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_25.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_26: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_26_CPU_PRI_26_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_26.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_26.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_26_CPU_PRI_26_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_26.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_27: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_27_CPU_PRI_27_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_27.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_27.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_27_CPU_PRI_27_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_27.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_28: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_28_CPU_PRI_28_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_28.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_28.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_28_CPU_PRI_28_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_28.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_29: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_29_CPU_PRI_29_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_29.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_29.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_29_CPU_PRI_29_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_29.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_30: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_30_CPU_PRI_30_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_30.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_30.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_30_CPU_PRI_30_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_30.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_31: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_31_CPU_PRI_31_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_31.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_31.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_31_CPU_PRI_31_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_31.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_THRESH: register description +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_THRESH(value uint32) { + volatile.StoreUint32(&o.CPU_INT_THRESH.Reg, volatile.LoadUint32(&o.CPU_INT_THRESH.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_THRESH() uint32 { + return volatile.LoadUint32(&o.CPU_INT_THRESH.Reg) & 0xf +} + +// INTERRUPT_CORE0.INTERRUPT_REG_DATE: register description +func (o *INTERRUPT_CORE0_Type) SetINTERRUPT_REG_DATE(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_REG_DATE.Reg, volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *INTERRUPT_CORE0_Type) GetINTERRUPT_REG_DATE() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg) & 0xfffffff +} + +// Input/Output Multiplexer +type IO_MUX_Type struct { + PIN_CTRL volatile.Register32 // 0x0 + GPIO0 volatile.Register32 // 0x4 + GPIO1 volatile.Register32 // 0x8 + GPIO2 volatile.Register32 // 0xC + GPIO3 volatile.Register32 // 0x10 + GPIO4 volatile.Register32 // 0x14 + GPIO5 volatile.Register32 // 0x18 + GPIO6 volatile.Register32 // 0x1C + GPIO7 volatile.Register32 // 0x20 + GPIO8 volatile.Register32 // 0x24 + GPIO9 volatile.Register32 // 0x28 + GPIO10 volatile.Register32 // 0x2C + GPIO11 volatile.Register32 // 0x30 + GPIO12 volatile.Register32 // 0x34 + GPIO13 volatile.Register32 // 0x38 + GPIO14 volatile.Register32 // 0x3C + GPIO15 volatile.Register32 // 0x40 + GPIO16 volatile.Register32 // 0x44 + GPIO17 volatile.Register32 // 0x48 + GPIO18 volatile.Register32 // 0x4C + GPIO19 volatile.Register32 // 0x50 + GPIO20 volatile.Register32 // 0x54 + _ [164]byte + DATE volatile.Register32 // 0xFC +} + +// IO_MUX.PIN_CTRL: Clock Output Configuration Register +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT1(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf)|value) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT1() uint32 { + return volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT2(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf0)|value<<4) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT2() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf0) >> 4 +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT3(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf00)|value<<8) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT3() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf00) >> 8 +} + +// IO_MUX.GPIO0: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO1: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO2: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO3: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO4: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO5: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO6: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO7: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO8: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO8_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO8.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO8_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO8_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO9: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO9_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO9.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO9_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO9_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO10: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO10_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO10.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO10_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO10_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO11: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO11_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO11.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO11_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO11_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO12: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO12_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO12.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO12_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO12_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO13: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO13_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO13.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO13_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO13_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO14: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO14_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO14.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO14_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO14_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO15: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO15_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO15.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO15_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO15_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO15_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO15_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO16: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO16_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO16.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO16_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO16_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO16_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO16_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO17: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO17_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO17.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO17_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO17_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO17_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO17_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO18: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO18_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO18.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO18_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO18_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO18_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO18_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO19: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO19_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO19.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO19_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO19_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO20: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO20_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO20.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO20_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO20_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8000) >> 15 +} + +// IO_MUX.DATE: IO MUX Version Control Register +func (o *IO_MUX_Type) SetDATE_REG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *IO_MUX_Type) GetDATE_REG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LED Control PWM (Pulse Width Modulation) +type LEDC_Type struct { + CH0_CONF0 volatile.Register32 // 0x0 + CH0_HPOINT volatile.Register32 // 0x4 + CH0_DUTY volatile.Register32 // 0x8 + CH0_CONF1 volatile.Register32 // 0xC + CH0_DUTY_R volatile.Register32 // 0x10 + CH1_CONF0 volatile.Register32 // 0x14 + CH1_HPOINT volatile.Register32 // 0x18 + CH1_DUTY volatile.Register32 // 0x1C + CH1_CONF1 volatile.Register32 // 0x20 + CH1_DUTY_R volatile.Register32 // 0x24 + CH2_CONF0 volatile.Register32 // 0x28 + CH2_HPOINT volatile.Register32 // 0x2C + CH2_DUTY volatile.Register32 // 0x30 + CH2_CONF1 volatile.Register32 // 0x34 + CH2_DUTY_R volatile.Register32 // 0x38 + CH3_CONF0 volatile.Register32 // 0x3C + CH3_HPOINT volatile.Register32 // 0x40 + CH3_DUTY volatile.Register32 // 0x44 + CH3_CONF1 volatile.Register32 // 0x48 + CH3_DUTY_R volatile.Register32 // 0x4C + CH4_CONF0 volatile.Register32 // 0x50 + CH4_HPOINT volatile.Register32 // 0x54 + CH4_DUTY volatile.Register32 // 0x58 + CH4_CONF1 volatile.Register32 // 0x5C + CH4_DUTY_R volatile.Register32 // 0x60 + CH5_CONF0 volatile.Register32 // 0x64 + CH5_HPOINT volatile.Register32 // 0x68 + CH5_DUTY volatile.Register32 // 0x6C + CH5_CONF1 volatile.Register32 // 0x70 + CH5_DUTY_R volatile.Register32 // 0x74 + _ [40]byte + TIMER0_CONF volatile.Register32 // 0xA0 + TIMER0_VALUE volatile.Register32 // 0xA4 + TIMER1_CONF volatile.Register32 // 0xA8 + TIMER1_VALUE volatile.Register32 // 0xAC + TIMER2_CONF volatile.Register32 // 0xB0 + TIMER2_VALUE volatile.Register32 // 0xB4 + TIMER3_CONF volatile.Register32 // 0xB8 + TIMER3_VALUE volatile.Register32 // 0xBC + INT_RAW volatile.Register32 // 0xC0 + INT_ST volatile.Register32 // 0xC4 + INT_ENA volatile.Register32 // 0xC8 + INT_CLR volatile.Register32 // 0xCC + CONF volatile.Register32 // 0xD0 + _ [40]byte + DATE volatile.Register32 // 0xFC +} + +// LEDC.CH0_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH0_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH0_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH0_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH0_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH0_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH0_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH0_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH0_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH0_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH0_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH0_HPOINT.Reg, volatile.LoadUint32(&o.CH0_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH0_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH0_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH0_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY.Reg, volatile.LoadUint32(&o.CH0_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH0_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH0_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH0_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_R_DUTY_CH0_R(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY_R.Reg, volatile.LoadUint32(&o.CH0_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_R_DUTY_CH0_R() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH1_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH1_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH1_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH1_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH1_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH1_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH1_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH1_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH1_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH1_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH1_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH1_HPOINT.Reg, volatile.LoadUint32(&o.CH1_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH1_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH1_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH1_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY.Reg, volatile.LoadUint32(&o.CH1_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH1_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH1_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH1_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_R_DUTY_CH0_R(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY_R.Reg, volatile.LoadUint32(&o.CH1_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_R_DUTY_CH0_R() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH2_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH2_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH2_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH2_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH2_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH2_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH2_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH2_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH2_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH2_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH2_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH2_HPOINT.Reg, volatile.LoadUint32(&o.CH2_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH2_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH2_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH2_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY.Reg, volatile.LoadUint32(&o.CH2_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH2_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH2_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH2_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_R_DUTY_CH0_R(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY_R.Reg, volatile.LoadUint32(&o.CH2_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_R_DUTY_CH0_R() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH3_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH3_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH3_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH3_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH3_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH3_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH3_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH3_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH3_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH3_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH3_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH3_HPOINT.Reg, volatile.LoadUint32(&o.CH3_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH3_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH3_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH3_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY.Reg, volatile.LoadUint32(&o.CH3_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH3_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH3_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH3_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_R_DUTY_CH0_R(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY_R.Reg, volatile.LoadUint32(&o.CH3_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_R_DUTY_CH0_R() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH4_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH4_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH4_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH4_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH4_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH4_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH4_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH4_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH4_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH4_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH4_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH4_HPOINT.Reg, volatile.LoadUint32(&o.CH4_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH4_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH4_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH4_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY.Reg, volatile.LoadUint32(&o.CH4_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH4_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH4_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH4_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_R_DUTY_CH0_R(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY_R.Reg, volatile.LoadUint32(&o.CH4_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_R_DUTY_CH0_R() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH5_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH5_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH5_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH5_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH5_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH5_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH5_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH5_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH5_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH5_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH5_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH5_HPOINT.Reg, volatile.LoadUint32(&o.CH5_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH5_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH5_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH5_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY.Reg, volatile.LoadUint32(&o.CH5_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH5_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH5_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH5_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_R_DUTY_CH0_R(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY_R.Reg, volatile.LoadUint32(&o.CH5_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_R_DUTY_CH0_R() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.TIMER0_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER0_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER0_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER0_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER0_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER0_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER0_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER0_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER0_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER0_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER0_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER0_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER0_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER0_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER0_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER0_VALUE.Reg, volatile.LoadUint32(&o.TIMER0_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER0_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER0_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER1_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER1_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER1_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER1_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER1_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER1_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER1_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER1_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER1_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER1_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER1_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER1_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER1_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER1_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER1_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER1_VALUE.Reg, volatile.LoadUint32(&o.TIMER1_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER1_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER1_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER2_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER2_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER2_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER2_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER2_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER2_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER2_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER2_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER2_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER2_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER2_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER2_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER2_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER2_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER2_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER2_VALUE.Reg, volatile.LoadUint32(&o.TIMER2_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER2_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER2_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER3_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER3_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER3_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER3_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER3_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER3_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER3_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER3_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER3_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER3_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER3_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER3_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER3_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER3_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER3_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER3_VALUE.Reg, volatile.LoadUint32(&o.TIMER3_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER3_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER3_VALUE.Reg) & 0x3fff +} + +// LEDC.INT_RAW: Raw interrupt status +func (o *LEDC_Type) SetINT_RAW_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_RAW_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_RAW_TIMER1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_RAW_TIMER2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_RAW_TIMER3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_RAW_TIMER3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} + +// LEDC.INT_ST: Masked interrupt status +func (o *LEDC_Type) SetINT_ST_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ST_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ST_TIMER1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ST_TIMER1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ST_TIMER2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ST_TIMER2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ST_TIMER3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ST_TIMER3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} + +// LEDC.INT_ENA: Interrupt enable bits +func (o *LEDC_Type) SetINT_ENA_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ENA_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ENA_TIMER1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ENA_TIMER2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ENA_TIMER3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ENA_TIMER3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} + +// LEDC.INT_CLR: Interrupt clear bits +func (o *LEDC_Type) SetINT_CLR_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_CLR_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_CLR_TIMER1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_CLR_TIMER2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_CLR_TIMER3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_CLR_TIMER3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} + +// LEDC.CONF: Global ledc configuration register +func (o *LEDC_Type) SetCONF_APB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCONF_APB_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x3 +} +func (o *LEDC_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// LEDC.DATE: Version control register +func (o *LEDC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *LEDC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// MODEM_CLKRST Peripheral +type MODEM_CLKRST_Type struct { + CLK_CONF volatile.Register32 // 0x0 + MODEM_LP_TIMER_CONF volatile.Register32 // 0x4 + COEX_LP_CLK_CONF volatile.Register32 // 0x8 + BLE_TIMER_CLK_CONF volatile.Register32 // 0xC + ETM_CLK_CONF volatile.Register32 // 0x10 +} + +// MODEM_CLKRST.CLK_CONF +func (o *MODEM_CLKRST_Type) SetCLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_CLKRST_Type) GetCLK_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1 +} + +// MODEM_CLKRST.MODEM_LP_TIMER_CONF +func (o *MODEM_CLKRST_Type) SetMODEM_LP_TIMER_CONF_LP_TIMER_SEL_RTC_SLOW(value uint32) { + volatile.StoreUint32(&o.MODEM_LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_CLKRST_Type) GetMODEM_LP_TIMER_CONF_LP_TIMER_SEL_RTC_SLOW() uint32 { + return volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg) & 0x1 +} +func (o *MODEM_CLKRST_Type) SetMODEM_LP_TIMER_CONF_LP_TIMER_SEL_8M(value uint32) { + volatile.StoreUint32(&o.MODEM_LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_CLKRST_Type) GetMODEM_LP_TIMER_CONF_LP_TIMER_SEL_8M() uint32 { + return (volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_CLKRST_Type) SetMODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.MODEM_LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_CLKRST_Type) GetMODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_CLKRST_Type) SetMODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.MODEM_LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_CLKRST_Type) GetMODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg) & 0x8) >> 3 +} +func (o *MODEM_CLKRST_Type) SetMODEM_LP_TIMER_CONF_LP_TIMER_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.MODEM_LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg)&^(0xff0)|value<<4) +} +func (o *MODEM_CLKRST_Type) GetMODEM_LP_TIMER_CONF_LP_TIMER_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.MODEM_LP_TIMER_CONF.Reg) & 0xff0) >> 4 +} + +// MODEM_CLKRST.COEX_LP_CLK_CONF +func (o *MODEM_CLKRST_Type) SetCOEX_LP_CLK_CONF_COEX_LPCLK_SEL_RTC_SLOW(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_CLKRST_Type) GetCOEX_LP_CLK_CONF_COEX_LPCLK_SEL_RTC_SLOW() uint32 { + return volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x1 +} +func (o *MODEM_CLKRST_Type) SetCOEX_LP_CLK_CONF_COEX_LPCLK_SEL_8M(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_CLKRST_Type) GetCOEX_LP_CLK_CONF_COEX_LPCLK_SEL_8M() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_CLKRST_Type) SetCOEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_CLKRST_Type) GetCOEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_CLKRST_Type) SetCOEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_CLKRST_Type) GetCOEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x8) >> 3 +} +func (o *MODEM_CLKRST_Type) SetCOEX_LP_CLK_CONF_COEX_LPCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0xff0)|value<<4) +} +func (o *MODEM_CLKRST_Type) GetCOEX_LP_CLK_CONF_COEX_LPCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0xff0) >> 4 +} + +// MODEM_CLKRST.BLE_TIMER_CLK_CONF +func (o *MODEM_CLKRST_Type) SetBLE_TIMER_CLK_CONF_BLETIMER_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.BLE_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.BLE_TIMER_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_CLKRST_Type) GetBLE_TIMER_CLK_CONF_BLETIMER_USE_XTAL() uint32 { + return volatile.LoadUint32(&o.BLE_TIMER_CLK_CONF.Reg) & 0x1 +} +func (o *MODEM_CLKRST_Type) SetBLE_TIMER_CLK_CONF_BLETIMER_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.BLE_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.BLE_TIMER_CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_CLKRST_Type) GetBLE_TIMER_CLK_CONF_BLETIMER_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.BLE_TIMER_CLK_CONF.Reg) & 0x2) >> 1 +} + +// MODEM_CLKRST.ETM_CLK_CONF +func (o *MODEM_CLKRST_Type) SetETM_CLK_CONF_ETM_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_CLK_CONF.Reg, volatile.LoadUint32(&o.ETM_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_CLKRST_Type) GetETM_CLK_CONF_ETM_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_CLK_CONF.Reg) & 0x1 +} +func (o *MODEM_CLKRST_Type) SetETM_CLK_CONF_ETM_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.ETM_CLK_CONF.Reg, volatile.LoadUint32(&o.ETM_CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_CLKRST_Type) GetETM_CLK_CONF_ETM_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.ETM_CLK_CONF.Reg) & 0x2) >> 1 +} + +// Hardware Random Number Generator +type RNG_Type struct { + _ [176]byte + DATA volatile.Register32 // 0xB0 +} + +// Real-Time Clock Control +type RTC_CNTL_Type struct { + OPTIONS0 volatile.Register32 // 0x0 + SLP_TIMER0 volatile.Register32 // 0x4 + SLP_TIMER1 volatile.Register32 // 0x8 + TIME_UPDATE volatile.Register32 // 0xC + TIME_LOW0 volatile.Register32 // 0x10 + TIME_HIGH0 volatile.Register32 // 0x14 + STATE0 volatile.Register32 // 0x18 + TIMER1 volatile.Register32 // 0x1C + TIMER2 volatile.Register32 // 0x20 + TIMER4 volatile.Register32 // 0x24 + TIMER5 volatile.Register32 // 0x28 + ANA_CONF volatile.Register32 // 0x2C + RESET_STATE volatile.Register32 // 0x30 + WAKEUP_STATE volatile.Register32 // 0x34 + INT_ENA_RTC volatile.Register32 // 0x38 + INT_RAW_RTC volatile.Register32 // 0x3C + INT_ST_RTC volatile.Register32 // 0x40 + INT_CLR_RTC volatile.Register32 // 0x44 + STORE0 volatile.Register32 // 0x48 + STORE1 volatile.Register32 // 0x4C + STORE2 volatile.Register32 // 0x50 + STORE3 volatile.Register32 // 0x54 + EXT_XTL_CONF volatile.Register32 // 0x58 + EXT_WAKEUP_CONF volatile.Register32 // 0x5C + SLP_REJECT_CONF volatile.Register32 // 0x60 + CPU_PERIOD_CONF volatile.Register32 // 0x64 + CLK_CONF volatile.Register32 // 0x68 + SLOW_CLK_CONF volatile.Register32 // 0x6C + BIAS_CONF volatile.Register32 // 0x70 + RTC_CNTL volatile.Register32 // 0x74 + PWC volatile.Register32 // 0x78 + DIG_PWC volatile.Register32 // 0x7C + DIG_ISO volatile.Register32 // 0x80 + WDTCONFIG0 volatile.Register32 // 0x84 + WDTCONFIG1 volatile.Register32 // 0x88 + WDTCONFIG2 volatile.Register32 // 0x8C + WDTCONFIG3 volatile.Register32 // 0x90 + WDTCONFIG4 volatile.Register32 // 0x94 + WDTFEED volatile.Register32 // 0x98 + WDTWPROTECT volatile.Register32 // 0x9C + SWD_CONF volatile.Register32 // 0xA0 + SWD_WPROTECT volatile.Register32 // 0xA4 + SW_CPU_STALL volatile.Register32 // 0xA8 + STORE4 volatile.Register32 // 0xAC + STORE5 volatile.Register32 // 0xB0 + STORE6 volatile.Register32 // 0xB4 + STORE7 volatile.Register32 // 0xB8 + LOW_POWER_ST volatile.Register32 // 0xBC + DIAG0 volatile.Register32 // 0xC0 + PAD_HOLD volatile.Register32 // 0xC4 + DIG_PAD_HOLD volatile.Register32 // 0xC8 + BROWN_OUT volatile.Register32 // 0xCC + TIME_LOW1 volatile.Register32 // 0xD0 + TIME_HIGH1 volatile.Register32 // 0xD4 + USB_CONF volatile.Register32 // 0xD8 + SLP_REJECT_CAUSE volatile.Register32 // 0xDC + OPTION1 volatile.Register32 // 0xE0 + SLP_WAKEUP_CAUSE volatile.Register32 // 0xE4 + ULP_CP_TIMER_1 volatile.Register32 // 0xE8 + INT_ENA_RTC_W1TS volatile.Register32 // 0xEC + INT_ENA_RTC_W1TC volatile.Register32 // 0xF0 + CNTL_RETENTION_CTRL volatile.Register32 // 0xF4 + FIB_SEL volatile.Register32 // 0xF8 + CNTL_GPIO_WAKEUP volatile.Register32 // 0xFC + CNTL_DBG_SEL volatile.Register32 // 0x100 + CNTL_DBG_MAP volatile.Register32 // 0x104 + CNTL_SENSOR_CTRL volatile.Register32 // 0x108 + CNTL_DBG_SAR_SEL volatile.Register32 // 0x10C + _ [236]byte + CNTL_DATE volatile.Register32 // 0x1FC +} + +// RTC_CNTL.OPTIONS0: register description +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_STALL_PROCPU_C0(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0xc)|value<<2) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_STALL_PROCPU_C0() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0xc) >> 2 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_PROCPU_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_PROCPU_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_EN_WAIT(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x3c000)|value<<14) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_EN_WAIT() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x3c000) >> 14 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_EXT_CTR_SEL(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x700000)|value<<20) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_EXT_CTR_SEL() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x700000) >> 20 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_NORST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_NORST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_SYS_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_TIMER0: register description +func (o *RTC_CNTL_Type) SetSLP_TIMER0(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER0() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER0.Reg) +} + +// RTC_CNTL.SLP_TIMER1: register description +func (o *RTC_CNTL_Type) SetSLP_TIMER1_SLP_VAL_HI(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_SLP_VAL_HI() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0xffff +} +func (o *RTC_CNTL_Type) SetSLP_TIMER1_MAIN_TIMER_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_MAIN_TIMER_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0x10000) >> 16 +} + +// RTC_CNTL.TIME_UPDATE: register description +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_SYS_STALL(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_SYS_STALL() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_XTL_OFF(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_XTL_OFF() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_SYS_RST(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIME_LOW0: register description +func (o *RTC_CNTL_Type) SetTIME_LOW0(value uint32) { + volatile.StoreUint32(&o.TIME_LOW0.Reg, value) +} +func (o *RTC_CNTL_Type) GetTIME_LOW0() uint32 { + return volatile.LoadUint32(&o.TIME_LOW0.Reg) +} + +// RTC_CNTL.TIME_HIGH0: register description +func (o *RTC_CNTL_Type) SetTIME_HIGH0_TIMER_VALUE0_HIGH(value uint32) { + volatile.StoreUint32(&o.TIME_HIGH0.Reg, volatile.LoadUint32(&o.TIME_HIGH0.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTIME_HIGH0_TIMER_VALUE0_HIGH() uint32 { + return volatile.LoadUint32(&o.TIME_HIGH0.Reg) & 0xffff +} + +// RTC_CNTL.STATE0: register description +func (o *RTC_CNTL_Type) SetSTATE0_SW_CPU_INT(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetSTATE0_SW_CPU_INT() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_REJECT_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_REJECT_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetSTATE0_APB2RTC_BRIDGE_SEL(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSTATE0_APB2RTC_BRIDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSTATE0_SDIO_ACTIVE_IND(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSTATE0_SDIO_ACTIVE_IND() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_WAKEUP(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_REJECT(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_REJECT() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLEEP_EN(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLEEP_EN() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIMER1: register description +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3e)|value<<1) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3e) >> 1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CK8M_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3fc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetTIMER1_CK8M_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3fc0) >> 6 +} +func (o *RTC_CNTL_Type) SetTIMER1_XTL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xffc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetTIMER1_XTL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xffc000) >> 14 +} +func (o *RTC_CNTL_Type) SetTIMER1_PLL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER1_PLL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER2: register description +func (o *RTC_CNTL_Type) SetTIMER2_MIN_TIME_CK8M_OFF(value uint32) { + volatile.StoreUint32(&o.TIMER2.Reg, volatile.LoadUint32(&o.TIMER2.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER2_MIN_TIME_CK8M_OFF() uint32 { + return (volatile.LoadUint32(&o.TIMER2.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER4: register description +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER5: register description +func (o *RTC_CNTL_Type) SetTIMER5_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetTIMER5_MIN_SLP_VAL() uint32 { + return (volatile.LoadUint32(&o.TIMER5.Reg) & 0xff00) >> 8 +} + +// RTC_CNTL.ANA_CONF: register description +func (o *RTC_CNTL_Type) SetANA_CONF_I2C_RESET_POR_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetANA_CONF_I2C_RESET_POR_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetANA_CONF_I2C_RESET_POR_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetANA_CONF_I2C_RESET_POR_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetANA_CONF_SAR_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetANA_CONF_SAR_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetANA_CONF_BBPLL_CAL_SLP_START(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetANA_CONF_BBPLL_CAL_SLP_START() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetANA_CONF_TXRF_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetANA_CONF_TXRF_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetANA_CONF_RFRX_PBUS_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetANA_CONF_RFRX_PBUS_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetANA_CONF_CKGEN_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetANA_CONF_CKGEN_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLL_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLL_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x80000000) >> 31 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLLA_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLLA_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLLA_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLLA_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x1000000) >> 24 +} + +// RTC_CNTL.RESET_STATE: register description +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_CAUSE_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x3f)|value) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_CAUSE_PROCPU() uint32 { + return volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x3f +} +func (o *RTC_CNTL_Type) SetRESET_STATE_STAT_VECTOR_SEL_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_STAT_VECTOR_SEL_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_OCD_HALT_ON_RESET_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_OCD_HALT_ON_RESET_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_DRESET_MASK_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_DRESET_MASK_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.WAKEUP_STATE: register description +func (o *RTC_CNTL_Type) SetWAKEUP_STATE_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.WAKEUP_STATE.Reg, volatile.LoadUint32(&o.WAKEUP_STATE.Reg)&^(0xffff8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetWAKEUP_STATE_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_STATE.Reg) & 0xffff8000) >> 15 +} + +// RTC_CNTL.INT_ENA_RTC: register description +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SLP_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SLP_WAKEUP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SLP_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SLP_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_MAIN_TIMER_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_MAIN_TIMER_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SWD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SWD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_BBPLL_CAL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_BBPLL_CAL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_RAW_RTC: register description +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SLP_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SLP_WAKEUP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SLP_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SLP_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_MAIN_TIMER_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_MAIN_TIMER_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SWD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SWD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_BBPLL_CAL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_BBPLL_CAL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_ST_RTC: register description +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SLP_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SLP_WAKEUP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SLP_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SLP_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_MAIN_TIMER_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_MAIN_TIMER_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SWD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SWD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_BBPLL_CAL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_BBPLL_CAL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_CLR_RTC: register description +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SLP_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SLP_WAKEUP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SLP_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SLP_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_MAIN_TIMER_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_MAIN_TIMER_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SWD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SWD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_BBPLL_CAL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_BBPLL_CAL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.STORE0: register description +func (o *RTC_CNTL_Type) SetSTORE0(value uint32) { + volatile.StoreUint32(&o.STORE0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE0() uint32 { + return volatile.LoadUint32(&o.STORE0.Reg) +} + +// RTC_CNTL.STORE1: register description +func (o *RTC_CNTL_Type) SetSTORE1(value uint32) { + volatile.StoreUint32(&o.STORE1.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE1() uint32 { + return volatile.LoadUint32(&o.STORE1.Reg) +} + +// RTC_CNTL.STORE2: register description +func (o *RTC_CNTL_Type) SetSTORE2(value uint32) { + volatile.StoreUint32(&o.STORE2.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE2() uint32 { + return volatile.LoadUint32(&o.STORE2.Reg) +} + +// RTC_CNTL.STORE3: register description +func (o *RTC_CNTL_Type) SetSTORE3(value uint32) { + volatile.StoreUint32(&o.STORE3.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE3() uint32 { + return volatile.LoadUint32(&o.STORE3.Reg) +} + +// RTC_CNTL.EXT_XTL_CONF: register description +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_LV(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_EN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_EN() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.EXT_WAKEUP_CONF: register description +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_REJECT_CONF: register description +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_SLEEP_REJECT_ENA(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x3ffff000)|value<<12) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_SLEEP_REJECT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x3ffff000) >> 12 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.CPU_PERIOD_CONF: register description +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUSEL_CONF(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUSEL_CONF() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUPERIOD_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.CLK_CONF: register description +func (o *RTC_CNTL_Type) SetCLK_CONF_EFUSE_CLK_FORCE_GATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_EFUSE_CLK_FORCE_GATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_EFUSE_CLK_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_EFUSE_CLK_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV_SEL_VLD(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV_SEL_VLD() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x30)|value<<4) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x30) >> 4 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_XTAL32K_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_XTAL32K_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_D256_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_D256_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x7000)|value<<12) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x7000) >> 12 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DFREQ(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1fe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DFREQ() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1fe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_GLOBAL_FORCE_GATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_GLOBAL_FORCE_GATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_GLOBAL_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_GLOBAL_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_FAST_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_FAST_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ANA_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ANA_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.SLOW_CLK_CONF: register description +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_ANA_CLK_DIV_VLD(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_ANA_CLK_DIV_VLD() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_ANA_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x7f800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_ANA_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x7f800000) >> 23 +} +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.BIAS_CONF: register description +func (o *RTC_CNTL_Type) SetBIAS_CONF_DG_VDD_DRV_B_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DG_VDD_DRV_B_SLP() uint32 { + return volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DG_VDD_DRV_B_SLP_EN(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DG_VDD_DRV_B_SLP_EN() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_IDLE(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_IDLE() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_WAKE(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_WAKE() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_PD_CUR_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_PD_CUR_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_PD_CUR_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_PD_CUR_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_SLEEP_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_SLEEP_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_SLEEP_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_SLEEP_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c0000)|value<<18) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c0000) >> 18 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_ACTIVE(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c000000) >> 26 +} + +// RTC_CNTL.RTC_CNTL: register description +func (o *RTC_CNTL_Type) SetRTC_CNTL_DIG_REG_CAL_EN(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_DIG_REG_CAL_EN() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetRTC_CNTL_SCK_DCAP(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x3fc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_SCK_DCAP() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x3fc000) >> 14 +} +func (o *RTC_CNTL_Type) SetRTC_CNTL_REGULATOR_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_REGULATOR_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetRTC_CNTL_REGULATOR_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_REGULATOR_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.PWC: register description +func (o *RTC_CNTL_Type) SetPWC_PAD_FORCE_HOLD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetPWC_PAD_FORCE_HOLD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x200000) >> 21 +} + +// RTC_CNTL.DIG_PWC: register description +func (o *RTC_CNTL_Type) SetDIG_PWC_VDD_SPI_PWR_DRV(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_VDD_SPI_PWR_DRV() uint32 { + return volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_VDD_SPI_PWR_FORCE(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_VDD_SPI_PWR_FORCE() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_VDD_SPI_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_VDD_SPI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.DIG_ISO: register description +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_OFF(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_OFF() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_CLR_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_CLR_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_UNHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_UNHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_HOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG0: register description +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CHIP_RESET_WIDTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CHIP_RESET_WIDTH() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CHIP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CHIP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PAUSE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PAUSE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000)|value<<13) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000) >> 13 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000) >> 16 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x380000)|value<<19) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x380000) >> 19 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000000) >> 28 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG1: register description +func (o *RTC_CNTL_Type) SetWDTCONFIG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG1() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) +} + +// RTC_CNTL.WDTCONFIG2: register description +func (o *RTC_CNTL_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// RTC_CNTL.WDTCONFIG3: register description +func (o *RTC_CNTL_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// RTC_CNTL.WDTCONFIG4: register description +func (o *RTC_CNTL_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// RTC_CNTL.WDTFEED: register description +func (o *RTC_CNTL_Type) SetWDTFEED_WDT_FEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, volatile.LoadUint32(&o.WDTFEED.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTFEED_WDT_FEED() uint32 { + return (volatile.LoadUint32(&o.WDTFEED.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTWPROTECT: register description +func (o *RTC_CNTL_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// RTC_CNTL.SWD_CONF: register description +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_RESET_FLAG() uint32 { + return volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_FEED_INT(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_FEED_INT() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_BYPASS_RST(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_BYPASS_RST() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_SIGNAL_WIDTH(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0xffc0000)|value<<18) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_SIGNAL_WIDTH() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0xffc0000) >> 18 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_RST_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_RST_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_FEED(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_FEED() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_DISABLE(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_AUTO_FEED_EN(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_AUTO_FEED_EN() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SWD_WPROTECT: register description +func (o *RTC_CNTL_Type) SetSWD_WPROTECT(value uint32) { + volatile.StoreUint32(&o.SWD_WPROTECT.Reg, value) +} +func (o *RTC_CNTL_Type) GetSWD_WPROTECT() uint32 { + return volatile.LoadUint32(&o.SWD_WPROTECT.Reg) +} + +// RTC_CNTL.SW_CPU_STALL: register description +func (o *RTC_CNTL_Type) SetSW_CPU_STALL_SW_STALL_PROCPU_C1(value uint32) { + volatile.StoreUint32(&o.SW_CPU_STALL.Reg, volatile.LoadUint32(&o.SW_CPU_STALL.Reg)&^(0xfc000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetSW_CPU_STALL_SW_STALL_PROCPU_C1() uint32 { + return (volatile.LoadUint32(&o.SW_CPU_STALL.Reg) & 0xfc000000) >> 26 +} + +// RTC_CNTL.STORE4: register description +func (o *RTC_CNTL_Type) SetSTORE4(value uint32) { + volatile.StoreUint32(&o.STORE4.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE4() uint32 { + return volatile.LoadUint32(&o.STORE4.Reg) +} + +// RTC_CNTL.STORE5: register description +func (o *RTC_CNTL_Type) SetSTORE5(value uint32) { + volatile.StoreUint32(&o.STORE5.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE5() uint32 { + return volatile.LoadUint32(&o.STORE5.Reg) +} + +// RTC_CNTL.STORE6: register description +func (o *RTC_CNTL_Type) SetSTORE6(value uint32) { + volatile.StoreUint32(&o.STORE6.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE6() uint32 { + return volatile.LoadUint32(&o.STORE6.Reg) +} + +// RTC_CNTL.STORE7: register description +func (o *RTC_CNTL_Type) SetSTORE7(value uint32) { + volatile.StoreUint32(&o.STORE7.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE7() uint32 { + return volatile.LoadUint32(&o.STORE7.Reg) +} + +// RTC_CNTL.LOW_POWER_ST: register description +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_DIG(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_DIG() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_START(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_START() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_SWITCH(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_SWITCH() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_DONE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_DONE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_START(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_START() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_SWITCH(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_SWITCH() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_DONE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_DONE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_XTAL_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_XTAL_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_PLL_ON(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_PLL_ON() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_RDY_FOR_WAKEUP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_RDY_FOR_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_WAIT_END(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_WAIT_END() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_IN_WAKEUP_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_IN_WAKEUP_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_IN_LOW_POWER_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_IN_LOW_POWER_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_8M(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_8M() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_IDLE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_IDLE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.DIAG0: register description +func (o *RTC_CNTL_Type) SetDIAG0(value uint32) { + volatile.StoreUint32(&o.DIAG0.Reg, value) +} +func (o *RTC_CNTL_Type) GetDIAG0() uint32 { + return volatile.LoadUint32(&o.DIAG0.Reg) +} + +// RTC_CNTL.PAD_HOLD: register description +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN0_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN0_HOLD() uint32 { + return volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN1_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN1_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN2_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN2_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN3_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN3_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN4_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN4_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN5_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN5_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x20) >> 5 +} + +// RTC_CNTL.DIG_PAD_HOLD: register description +func (o *RTC_CNTL_Type) SetDIG_PAD_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_PAD_HOLD.Reg, value) +} +func (o *RTC_CNTL_Type) GetDIG_PAD_HOLD() uint32 { + return volatile.LoadUint32(&o.DIG_PAD_HOLD.Reg) +} + +// RTC_CNTL.BROWN_OUT: register description +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_INT_WAIT(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x3ff0)|value<<4) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_INT_WAIT() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x3ff0) >> 4 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_PD_RF_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_PD_RF_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_RST_WAIT(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x3ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_RST_WAIT() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x3ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_RST_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_RST_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_RST_SEL(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_RST_SEL() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_ANA_RST_EN(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_ANA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_DET(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_DET() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIME_LOW1: register description +func (o *RTC_CNTL_Type) SetTIME_LOW1(value uint32) { + volatile.StoreUint32(&o.TIME_LOW1.Reg, value) +} +func (o *RTC_CNTL_Type) GetTIME_LOW1() uint32 { + return volatile.LoadUint32(&o.TIME_LOW1.Reg) +} + +// RTC_CNTL.TIME_HIGH1: register description +func (o *RTC_CNTL_Type) SetTIME_HIGH1_TIMER_VALUE1_HIGH(value uint32) { + volatile.StoreUint32(&o.TIME_HIGH1.Reg, volatile.LoadUint32(&o.TIME_HIGH1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTIME_HIGH1_TIMER_VALUE1_HIGH() uint32 { + return volatile.LoadUint32(&o.TIME_HIGH1.Reg) & 0xffff +} + +// RTC_CNTL.USB_CONF: register description +func (o *RTC_CNTL_Type) SetUSB_CONF_IO_MUX_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_IO_MUX_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x40000) >> 18 +} + +// RTC_CNTL.SLP_REJECT_CAUSE: register description +func (o *RTC_CNTL_Type) SetSLP_REJECT_CAUSE_REJECT_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CAUSE.Reg, volatile.LoadUint32(&o.SLP_REJECT_CAUSE.Reg)&^(0x3ffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CAUSE_REJECT_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_REJECT_CAUSE.Reg) & 0x3ffff +} + +// RTC_CNTL.OPTION1: register description +func (o *RTC_CNTL_Type) SetOPTION1_FORCE_DOWNLOAD_BOOT(value uint32) { + volatile.StoreUint32(&o.OPTION1.Reg, volatile.LoadUint32(&o.OPTION1.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetOPTION1_FORCE_DOWNLOAD_BOOT() uint32 { + return volatile.LoadUint32(&o.OPTION1.Reg) & 0x1 +} + +// RTC_CNTL.SLP_WAKEUP_CAUSE: register description +func (o *RTC_CNTL_Type) SetSLP_WAKEUP_CAUSE_WAKEUP_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CAUSE.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CAUSE.Reg)&^(0x1ffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_WAKEUP_CAUSE_WAKEUP_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CAUSE.Reg) & 0x1ffff +} + +// RTC_CNTL.ULP_CP_TIMER_1: register description +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER_1.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg)&^(0xffffff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg) & 0xffffff00) >> 8 +} + +// RTC_CNTL.INT_ENA_RTC_W1TS: register description +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_ENA_RTC_W1TC: register description +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.CNTL_RETENTION_CTRL: register description +func (o *RTC_CNTL_Type) SetCNTL_RETENTION_CTRL_RETENTION_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_RETENTION_CTRL.Reg, volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetCNTL_RETENTION_CTRL_RETENTION_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetCNTL_RETENTION_CTRL_RETENTION_DONE_WAIT(value uint32) { + volatile.StoreUint32(&o.CNTL_RETENTION_CTRL.Reg, volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg)&^(0x380000)|value<<19) +} +func (o *RTC_CNTL_Type) GetCNTL_RETENTION_CTRL_RETENTION_DONE_WAIT() uint32 { + return (volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg) & 0x380000) >> 19 +} +func (o *RTC_CNTL_Type) SetCNTL_RETENTION_CTRL_RETENTION_CLKOFF_WAIT(value uint32) { + volatile.StoreUint32(&o.CNTL_RETENTION_CTRL.Reg, volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg)&^(0x3c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetCNTL_RETENTION_CTRL_RETENTION_CLKOFF_WAIT() uint32 { + return (volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg) & 0x3c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetCNTL_RETENTION_CTRL_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.CNTL_RETENTION_CTRL.Reg, volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCNTL_RETENTION_CTRL_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetCNTL_RETENTION_CTRL_RETENTION_WAIT(value uint32) { + volatile.StoreUint32(&o.CNTL_RETENTION_CTRL.Reg, volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCNTL_RETENTION_CTRL_RETENTION_WAIT() uint32 { + return (volatile.LoadUint32(&o.CNTL_RETENTION_CTRL.Reg) & 0xf8000000) >> 27 +} + +// RTC_CNTL.FIB_SEL: register description +func (o *RTC_CNTL_Type) SetFIB_SEL(value uint32) { + volatile.StoreUint32(&o.FIB_SEL.Reg, volatile.LoadUint32(&o.FIB_SEL.Reg)&^(0x7)|value) +} +func (o *RTC_CNTL_Type) GetFIB_SEL() uint32 { + return volatile.LoadUint32(&o.FIB_SEL.Reg) & 0x7 +} + +// RTC_CNTL.CNTL_GPIO_WAKEUP: register description +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x3f)|value) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS() uint32 { + return volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x3f +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN_CLK_GATE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN_CLK_GATE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x700)|value<<8) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x700) >> 8 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x3800)|value<<11) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x3800) >> 11 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x1c000)|value<<14) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x1c000) >> 14 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0xe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0xe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x700000)|value<<20) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x700000) >> 20 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x3800000) >> 23 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetCNTL_GPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CNTL_GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetCNTL_GPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CNTL_GPIO_WAKEUP.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.CNTL_DBG_SEL: register description +func (o *RTC_CNTL_Type) SetCNTL_DBG_SEL_DEBUG_12M_NO_GATING(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_SEL.Reg, volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_SEL_DEBUG_12M_NO_GATING() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_SEL_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_SEL.Reg, volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg)&^(0x7c)|value<<2) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_SEL_DEBUG_BIT_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg) & 0x7c) >> 2 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_SEL_DEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_SEL.Reg, volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg)&^(0xf80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_SEL_DEBUG_SEL0() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg) & 0xf80) >> 7 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_SEL_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_SEL.Reg, volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg)&^(0x1f000)|value<<12) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_SEL_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg) & 0x1f000) >> 12 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_SEL_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_SEL.Reg, volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg)&^(0x3e0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_SEL_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg) & 0x3e0000) >> 17 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_SEL_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_SEL.Reg, volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg)&^(0x7c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_SEL_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg) & 0x7c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_SEL_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_SEL.Reg, volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_SEL_DEBUG_SEL4() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_SEL.Reg) & 0xf8000000) >> 27 +} + +// RTC_CNTL.CNTL_DBG_MAP: register description +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN5_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN5_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN4_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN4_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN3_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN3_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN0_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN0_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN5_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0xf00)|value<<8) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN5_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0xf00) >> 8 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN4_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0xf000)|value<<12) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN4_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0xf000) >> 12 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN3_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0xf0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN3_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0xf0000) >> 16 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0xf00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0xf00000) >> 20 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0xf000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0xf000000) >> 24 +} +func (o *RTC_CNTL_Type) SetCNTL_DBG_MAP_GPIO_PIN0_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_MAP.Reg, volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_MAP_GPIO_PIN0_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_MAP.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.CNTL_SENSOR_CTRL: register description +func (o *RTC_CNTL_Type) SetCNTL_SENSOR_CTRL_SAR2_PWDET_CCT(value uint32) { + volatile.StoreUint32(&o.CNTL_SENSOR_CTRL.Reg, volatile.LoadUint32(&o.CNTL_SENSOR_CTRL.Reg)&^(0x38000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCNTL_SENSOR_CTRL_SAR2_PWDET_CCT() uint32 { + return (volatile.LoadUint32(&o.CNTL_SENSOR_CTRL.Reg) & 0x38000000) >> 27 +} +func (o *RTC_CNTL_Type) SetCNTL_SENSOR_CTRL_FORCE_XPD_SAR(value uint32) { + volatile.StoreUint32(&o.CNTL_SENSOR_CTRL.Reg, volatile.LoadUint32(&o.CNTL_SENSOR_CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCNTL_SENSOR_CTRL_FORCE_XPD_SAR() uint32 { + return (volatile.LoadUint32(&o.CNTL_SENSOR_CTRL.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.CNTL_DBG_SAR_SEL: register description +func (o *RTC_CNTL_Type) SetCNTL_DBG_SAR_SEL_SAR_DEBUG_SEL(value uint32) { + volatile.StoreUint32(&o.CNTL_DBG_SAR_SEL.Reg, volatile.LoadUint32(&o.CNTL_DBG_SAR_SEL.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCNTL_DBG_SAR_SEL_SAR_DEBUG_SEL() uint32 { + return (volatile.LoadUint32(&o.CNTL_DBG_SAR_SEL.Reg) & 0xf8000000) >> 27 +} + +// RTC_CNTL.CNTL_DATE: register description +func (o *RTC_CNTL_Type) SetCNTL_DATE(value uint32) { + volatile.StoreUint32(&o.CNTL_DATE.Reg, volatile.LoadUint32(&o.CNTL_DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_CNTL_Type) GetCNTL_DATE() uint32 { + return volatile.LoadUint32(&o.CNTL_DATE.Reg) & 0xfffffff +} + +// SENSITIVE Peripheral +type SENSITIVE_Type struct { + ROM_TABLE_LOCK volatile.Register32 // 0x0 + ROM_TABLE volatile.Register32 // 0x4 + APB_PERIPHERAL_ACCESS_0 volatile.Register32 // 0x8 + APB_PERIPHERAL_ACCESS_1 volatile.Register32 // 0xC + INTERNAL_SRAM_USAGE_0 volatile.Register32 // 0x10 + INTERNAL_SRAM_USAGE_1 volatile.Register32 // 0x14 + INTERNAL_SRAM_USAGE_3 volatile.Register32 // 0x18 + CACHE_TAG_ACCESS_0 volatile.Register32 // 0x1C + CACHE_TAG_ACCESS_1 volatile.Register32 // 0x20 + CACHE_MMU_ACCESS_0 volatile.Register32 // 0x24 + CACHE_MMU_ACCESS_1 volatile.Register32 // 0x28 + PIF_ACCESS_MONITOR_0 volatile.Register32 // 0x2C + PIF_ACCESS_MONITOR_1 volatile.Register32 // 0x30 + PIF_ACCESS_MONITOR_2 volatile.Register32 // 0x34 + PIF_ACCESS_MONITOR_3 volatile.Register32 // 0x38 + XTS_AES_KEY_UPDATE volatile.Register32 // 0x3C + CLOCK_GATE volatile.Register32 // 0x40 + _ [4024]byte + SENSITIVE_REG_DATE volatile.Register32 // 0xFFC +} + +// SENSITIVE.ROM_TABLE_LOCK: register description +func (o *SENSITIVE_Type) SetROM_TABLE_LOCK(value uint32) { + volatile.StoreUint32(&o.ROM_TABLE_LOCK.Reg, volatile.LoadUint32(&o.ROM_TABLE_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetROM_TABLE_LOCK() uint32 { + return volatile.LoadUint32(&o.ROM_TABLE_LOCK.Reg) & 0x1 +} + +// SENSITIVE.ROM_TABLE: register description +func (o *SENSITIVE_Type) SetROM_TABLE(value uint32) { + volatile.StoreUint32(&o.ROM_TABLE.Reg, value) +} +func (o *SENSITIVE_Type) GetROM_TABLE() uint32 { + return volatile.LoadUint32(&o.ROM_TABLE.Reg) +} + +// SENSITIVE.APB_PERIPHERAL_ACCESS_0: register description +func (o *SENSITIVE_Type) SetAPB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_ACCESS_0.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetAPB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_0.Reg) & 0x1 +} + +// SENSITIVE.APB_PERIPHERAL_ACCESS_1: register description +func (o *SENSITIVE_Type) SetAPB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_ACCESS_1.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetAPB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_1.Reg) & 0x1 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_0: register description +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_0.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_0.Reg) & 0x1 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_1: register description +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_1.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_SRAM(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_1.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg)&^(0xe)|value<<1) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_SRAM() uint32 { + return (volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg) & 0xe) >> 1 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_3: register description +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_3.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_3.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg)&^(0x8)|value<<3) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP() uint32 { + return (volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg) & 0x8) >> 3 +} + +// SENSITIVE.CACHE_TAG_ACCESS_0: register description +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_0.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_ACCESS_0.Reg) & 0x1 +} + +// SENSITIVE.CACHE_TAG_ACCESS_1: register description +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x4)|value<<2) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x4) >> 2 +} +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x8)|value<<3) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x8) >> 3 +} + +// SENSITIVE.CACHE_MMU_ACCESS_0: register description +func (o *SENSITIVE_Type) SetCACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_0.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_ACCESS_0.Reg) & 0x1 +} + +// SENSITIVE.CACHE_MMU_ACCESS_1: register description +func (o *SENSITIVE_Type) SetCACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.PIF_ACCESS_MONITOR_0: register description +func (o *SENSITIVE_Type) SetPIF_ACCESS_MONITOR_0_PIF_ACCESS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.PIF_ACCESS_MONITOR_0.Reg, volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetPIF_ACCESS_MONITOR_0_PIF_ACCESS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.PIF_ACCESS_MONITOR_1: register description +func (o *SENSITIVE_Type) SetPIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.PIF_ACCESS_MONITOR_1.Reg, volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetPIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetPIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.PIF_ACCESS_MONITOR_1.Reg, volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetPIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.PIF_ACCESS_MONITOR_2: register description +func (o *SENSITIVE_Type) SetPIF_ACCESS_MONITOR_2_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.PIF_ACCESS_MONITOR_2.Reg, volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetPIF_ACCESS_MONITOR_2_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetPIF_ACCESS_MONITOR_2_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE(value uint32) { + volatile.StoreUint32(&o.PIF_ACCESS_MONITOR_2.Reg, volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_2.Reg)&^(0x6)|value<<1) +} +func (o *SENSITIVE_Type) GetPIF_ACCESS_MONITOR_2_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE() uint32 { + return (volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_2.Reg) & 0x6) >> 1 +} + +// SENSITIVE.PIF_ACCESS_MONITOR_3: register description +func (o *SENSITIVE_Type) SetPIF_ACCESS_MONITOR_3(value uint32) { + volatile.StoreUint32(&o.PIF_ACCESS_MONITOR_3.Reg, value) +} +func (o *SENSITIVE_Type) GetPIF_ACCESS_MONITOR_3() uint32 { + return volatile.LoadUint32(&o.PIF_ACCESS_MONITOR_3.Reg) +} + +// SENSITIVE.XTS_AES_KEY_UPDATE: register description +func (o *SENSITIVE_Type) SetXTS_AES_KEY_UPDATE(value uint32) { + volatile.StoreUint32(&o.XTS_AES_KEY_UPDATE.Reg, volatile.LoadUint32(&o.XTS_AES_KEY_UPDATE.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetXTS_AES_KEY_UPDATE() uint32 { + return volatile.LoadUint32(&o.XTS_AES_KEY_UPDATE.Reg) & 0x1 +} + +// SENSITIVE.CLOCK_GATE: register description +func (o *SENSITIVE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SENSITIVE.SENSITIVE_REG_DATE: register description +func (o *SENSITIVE_Type) SetSENSITIVE_REG_DATE(value uint32) { + volatile.StoreUint32(&o.SENSITIVE_REG_DATE.Reg, volatile.LoadUint32(&o.SENSITIVE_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SENSITIVE_Type) GetSENSITIVE_REG_DATE() uint32 { + return volatile.LoadUint32(&o.SENSITIVE_REG_DATE.Reg) & 0xfffffff +} + +// SHA (Secure Hash Algorithm) Accelerator +type SHA_Type struct { + MODE volatile.Register32 // 0x0 + T_STRING volatile.Register32 // 0x4 + T_LENGTH volatile.Register32 // 0x8 + DMA_BLOCK_NUM volatile.Register32 // 0xC + START volatile.Register32 // 0x10 + CONTINUE volatile.Register32 // 0x14 + BUSY volatile.Register32 // 0x18 + DMA_START volatile.Register32 // 0x1C + DMA_CONTINUE volatile.Register32 // 0x20 + CLEAR_IRQ volatile.Register32 // 0x24 + IRQ_ENA volatile.Register32 // 0x28 + DATE volatile.Register32 // 0x2C + _ [16]byte + H_MEM [64]volatile.Register8 // 0x40 + M_MEM [64]volatile.Register8 // 0x80 +} + +// SHA.MODE: Initial configuration register. +func (o *SHA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *SHA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// SHA.T_STRING: SHA 512/t configuration register 0. +func (o *SHA_Type) SetT_STRING(value uint32) { + volatile.StoreUint32(&o.T_STRING.Reg, value) +} +func (o *SHA_Type) GetT_STRING() uint32 { + return volatile.LoadUint32(&o.T_STRING.Reg) +} + +// SHA.T_LENGTH: SHA 512/t configuration register 1. +func (o *SHA_Type) SetT_LENGTH(value uint32) { + volatile.StoreUint32(&o.T_LENGTH.Reg, volatile.LoadUint32(&o.T_LENGTH.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetT_LENGTH() uint32 { + return volatile.LoadUint32(&o.T_LENGTH.Reg) & 0x3f +} + +// SHA.DMA_BLOCK_NUM: DMA configuration register 0. +func (o *SHA_Type) SetDMA_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_NUM.Reg, volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetDMA_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg) & 0x3f +} + +// SHA.START: Typical SHA configuration register 0. +func (o *SHA_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetSTART() uint32 { + return (volatile.LoadUint32(&o.START.Reg) & 0xfffffffe) >> 1 +} + +// SHA.CONTINUE: Typical SHA configuration register 1. +func (o *SHA_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetCONTINUE() uint32 { + return (volatile.LoadUint32(&o.CONTINUE.Reg) & 0xfffffffe) >> 1 +} + +// SHA.BUSY: Busy register. +func (o *SHA_Type) SetBUSY_STATE(value uint32) { + volatile.StoreUint32(&o.BUSY.Reg, volatile.LoadUint32(&o.BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetBUSY_STATE() uint32 { + return volatile.LoadUint32(&o.BUSY.Reg) & 0x1 +} + +// SHA.DMA_START: DMA configuration register 1. +func (o *SHA_Type) SetDMA_START(value uint32) { + volatile.StoreUint32(&o.DMA_START.Reg, volatile.LoadUint32(&o.DMA_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_START() uint32 { + return volatile.LoadUint32(&o.DMA_START.Reg) & 0x1 +} + +// SHA.DMA_CONTINUE: DMA configuration register 2. +func (o *SHA_Type) SetDMA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.DMA_CONTINUE.Reg, volatile.LoadUint32(&o.DMA_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_CONTINUE() uint32 { + return volatile.LoadUint32(&o.DMA_CONTINUE.Reg) & 0x1 +} + +// SHA.CLEAR_IRQ: Interrupt clear register. +func (o *SHA_Type) SetCLEAR_IRQ_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CLEAR_IRQ.Reg, volatile.LoadUint32(&o.CLEAR_IRQ.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetCLEAR_IRQ_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.CLEAR_IRQ.Reg) & 0x1 +} + +// SHA.IRQ_ENA: Interrupt enable register. +func (o *SHA_Type) SetIRQ_ENA_INTERRUPT_ENA(value uint32) { + volatile.StoreUint32(&o.IRQ_ENA.Reg, volatile.LoadUint32(&o.IRQ_ENA.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetIRQ_ENA_INTERRUPT_ENA() uint32 { + return volatile.LoadUint32(&o.IRQ_ENA.Reg) & 0x1 +} + +// SHA.DATE: Date register. +func (o *SHA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SHA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// SPI (Serial Peripheral Interface) Controller 0 +type SPI0_Type struct { + _ [8]byte + CTRL volatile.Register32 // 0x8 + CTRL1 volatile.Register32 // 0xC + CTRL2 volatile.Register32 // 0x10 + CLOCK volatile.Register32 // 0x14 + USER volatile.Register32 // 0x18 + USER1 volatile.Register32 // 0x1C + USER2 volatile.Register32 // 0x20 + _ [8]byte + RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + MISC volatile.Register32 // 0x34 + _ [4]byte + CACHE_FCTRL volatile.Register32 // 0x3C + _ [20]byte + FSM volatile.Register32 // 0x54 + _ [80]byte + TIMING_CALI volatile.Register32 // 0xA8 + DIN_MODE volatile.Register32 // 0xAC + DIN_NUM volatile.Register32 // 0xB0 + DOUT_MODE volatile.Register32 // 0xB4 + _ [36]byte + CLOCK_GATE volatile.Register32 // 0xDC + CORE_CLK_SEL volatile.Register32 // 0xE0 + _ [792]byte + DATE volatile.Register32 // 0x3FC +} + +// SPI0.CTRL: SPI0 control register. +func (o *SPI0_Type) SetCTRL_FDUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetCTRL_FDUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetCTRL_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetCTRL_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetCTRL_WP(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetCTRL_WP() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetCTRL_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetCTRL_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetCTRL_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetCTRL_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} + +// SPI0.CTRL1: SPI0 control1 register. +func (o *SPI0_Type) SetCTRL1_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetCTRL1_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.CTRL1.Reg) & 0x3 +} +func (o *SPI0_Type) SetCTRL1_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetCTRL1_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0x40000000) >> 30 +} + +// SPI0.CTRL2: SPI0 control2 register. +func (o *SPI0_Type) SetCTRL2_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1f)|value) +} +func (o *SPI0_Type) GetCTRL2_CS_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1f +} +func (o *SPI0_Type) SetCTRL2_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x3e0)|value<<5) +} +func (o *SPI0_Type) GetCTRL2_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x3e0) >> 5 +} +func (o *SPI0_Type) SetCTRL2_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetCTRL2_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x7e000000) >> 25 +} +func (o *SPI0_Type) SetCTRL2_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetCTRL2_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI0.CLOCK: SPI clock division control register. +func (o *SPI0_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0xff +} +func (o *SPI0_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI0.USER: SPI0 user register. +func (o *SPI0_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} + +// SPI0.USER1: SPI0 user1 register. +func (o *SPI0_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3f)|value) +} +func (o *SPI0_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0x3f +} +func (o *SPI0_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI0_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI0.USER2: SPI0 user2 register. +func (o *SPI0_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI0_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI0.RD_STATUS: SPI0 read control register. +func (o *SPI0_Type) SetRD_STATUS_WB_MODE(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetRD_STATUS_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI0.MISC: SPI0 misc register +func (o *SPI0_Type) SetMISC_TRANS_END(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetMISC_TRANS_END() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetMISC_TRANS_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetMISC_TRANS_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetMISC_CSPI_ST_TRANS_END(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetMISC_CSPI_ST_TRANS_END() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetMISC_CSPI_ST_TRANS_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetMISC_CSPI_ST_TRANS_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x400) >> 10 +} + +// SPI0.CACHE_FCTRL: SPI0 bit mode control register. +func (o *SPI0_Type) SetCACHE_FCTRL_CACHE_REQ_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetCACHE_FCTRL_CACHE_REQ_EN() uint32 { + return volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetCACHE_FCTRL_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetCACHE_FCTRL_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetCACHE_FCTRL_CACHE_FLASH_USR_CMD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetCACHE_FCTRL_CACHE_FLASH_USR_CMD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x100) >> 8 +} + +// SPI0.FSM: SPI0 FSM status register +func (o *SPI0_Type) SetFSM_CSPI_ST(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0xf)|value) +} +func (o *SPI0_Type) GetFSM_CSPI_ST() uint32 { + return volatile.LoadUint32(&o.FSM.Reg) & 0xf +} +func (o *SPI0_Type) SetFSM_EM_ST(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0x70)|value<<4) +} +func (o *SPI0_Type) GetFSM_EM_ST() uint32 { + return (volatile.LoadUint32(&o.FSM.Reg) & 0x70) >> 4 +} +func (o *SPI0_Type) SetFSM_CSPI_LOCK_DELAY_TIME(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0xf80)|value<<7) +} +func (o *SPI0_Type) GetFSM_CSPI_LOCK_DELAY_TIME() uint32 { + return (volatile.LoadUint32(&o.FSM.Reg) & 0xf80) >> 7 +} + +// SPI0.TIMING_CALI: SPI0 timing calibration register +func (o *SPI0_Type) SetTIMING_CALI_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetTIMING_CALI_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetTIMING_CALI(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetTIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetTIMING_CALI_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetTIMING_CALI_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI0.DIN_MODE: SPI0 input delay mode control register +func (o *SPI0_Type) SetDIN_MODE_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetDIN_MODE_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3 +} +func (o *SPI0_Type) SetDIN_MODE_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetDIN_MODE_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetDIN_MODE_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetDIN_MODE_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetDIN_MODE_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetDIN_MODE_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc0) >> 6 +} + +// SPI0.DIN_NUM: SPI0 input delay number control register +func (o *SPI0_Type) SetDIN_NUM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetDIN_NUM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x1 +} +func (o *SPI0_Type) SetDIN_NUM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetDIN_NUM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetDIN_NUM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetDIN_NUM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetDIN_NUM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetDIN_NUM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x8) >> 3 +} + +// SPI0.DOUT_MODE: SPI0 output delay mode control register +func (o *SPI0_Type) SetDOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x8) >> 3 +} + +// SPI0.CLOCK_GATE: SPI0 clk_gate register +func (o *SPI0_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SPI0.CORE_CLK_SEL: SPI0 module clock select register +func (o *SPI0_Type) SetCORE_CLK_SEL_SPI01_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetCORE_CLK_SEL_SPI01_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0x3 +} + +// SPI0.DATE: Version control register +func (o *SPI0_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI0_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 1 +type SPI1_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CTRL1 volatile.Register32 // 0xC + CTRL2 volatile.Register32 // 0x10 + CLOCK volatile.Register32 // 0x14 + USER volatile.Register32 // 0x18 + USER1 volatile.Register32 // 0x1C + USER2 volatile.Register32 // 0x20 + MOSI_DLEN volatile.Register32 // 0x24 + MISO_DLEN volatile.Register32 // 0x28 + RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + MISC volatile.Register32 // 0x34 + TX_CRC volatile.Register32 // 0x38 + CACHE_FCTRL volatile.Register32 // 0x3C + _ [24]byte + W0 volatile.Register32 // 0x58 + W1 volatile.Register32 // 0x5C + W2 volatile.Register32 // 0x60 + W3 volatile.Register32 // 0x64 + W4 volatile.Register32 // 0x68 + W5 volatile.Register32 // 0x6C + W6 volatile.Register32 // 0x70 + W7 volatile.Register32 // 0x74 + W8 volatile.Register32 // 0x78 + W9 volatile.Register32 // 0x7C + W10 volatile.Register32 // 0x80 + W11 volatile.Register32 // 0x84 + W12 volatile.Register32 // 0x88 + W13 volatile.Register32 // 0x8C + W14 volatile.Register32 // 0x90 + W15 volatile.Register32 // 0x94 + FLASH_WAITI_CTRL volatile.Register32 // 0x98 + FLASH_SUS_CTRL volatile.Register32 // 0x9C + FLASH_SUS_CMD volatile.Register32 // 0xA0 + SUS_STATUS volatile.Register32 // 0xA4 + TIMING_CALI volatile.Register32 // 0xA8 + _ [20]byte + INT_ENA volatile.Register32 // 0xC0 + INT_CLR volatile.Register32 // 0xC4 + INT_RAW volatile.Register32 // 0xC8 + INT_ST volatile.Register32 // 0xCC + _ [12]byte + CLOCK_GATE volatile.Register32 // 0xDC + _ [796]byte + DATE volatile.Register32 // 0x3FC +} + +// SPI1.CMD: SPI1 memory command register +func (o *SPI1_Type) SetCMD_SPI1_MST_ST(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0xf)|value) +} +func (o *SPI1_Type) GetCMD_SPI1_MST_ST() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0xf +} +func (o *SPI1_Type) SetCMD_MSPI_ST(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0xf0)|value<<4) +} +func (o *SPI1_Type) GetCMD_MSPI_ST() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0xf0) >> 4 +} +func (o *SPI1_Type) SetCMD_FLASH_PE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI1_Type) GetCMD_FLASH_PE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI1_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetCMD_FLASH_HPM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetCMD_FLASH_HPM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetCMD_FLASH_RES(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetCMD_FLASH_RES() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetCMD_FLASH_DP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetCMD_FLASH_DP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetCMD_FLASH_CE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetCMD_FLASH_CE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetCMD_FLASH_BE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetCMD_FLASH_BE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetCMD_FLASH_SE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetCMD_FLASH_SE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetCMD_FLASH_PP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetCMD_FLASH_PP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetCMD_FLASH_WRSR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetCMD_FLASH_WRSR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetCMD_FLASH_RDSR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetCMD_FLASH_RDSR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetCMD_FLASH_RDID(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetCMD_FLASH_RDID() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetCMD_FLASH_WRDI(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetCMD_FLASH_WRDI() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetCMD_FLASH_WREN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetCMD_FLASH_WREN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetCMD_FLASH_READ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetCMD_FLASH_READ() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31 +} + +// SPI1.ADDR: SPI1 address register +func (o *SPI1_Type) SetADDR(value uint32) { + volatile.StoreUint32(&o.ADDR.Reg, value) +} +func (o *SPI1_Type) GetADDR() uint32 { + return volatile.LoadUint32(&o.ADDR.Reg) +} + +// SPI1.CTRL: SPI1 control register. +func (o *SPI1_Type) SetCTRL_FDUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetCTRL_FDUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI1_Type) SetCTRL_FCS_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetCTRL_FCS_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI1_Type) SetCTRL_TX_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SPI1_Type) GetCTRL_TX_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11 +} +func (o *SPI1_Type) SetCTRL_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetCTRL_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetCTRL_RESANDRES(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetCTRL_RESANDRES() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetCTRL_WP(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetCTRL_WP() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetCTRL_WRSR_2B(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetCTRL_WRSR_2B() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetCTRL_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetCTRL_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetCTRL_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetCTRL_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} + +// SPI1.CTRL1: SPI1 control1 register. +func (o *SPI1_Type) SetCTRL1_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI1_Type) GetCTRL1_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.CTRL1.Reg) & 0x3 +} +func (o *SPI1_Type) SetCTRL1_CS_HOLD_DLY_RES(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0xffc)|value<<2) +} +func (o *SPI1_Type) GetCTRL1_CS_HOLD_DLY_RES() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0xffc) >> 2 +} + +// SPI1.CTRL2: SPI1 control2 register. +func (o *SPI1_Type) SetCTRL2_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetCTRL2_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI1.CLOCK: SPI1 clock division control register. +func (o *SPI1_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0xff +} +func (o *SPI1_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI1_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI1.USER: SPI1 user register. +func (o *SPI1_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI1_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI1_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetUSER_FWRITE_DIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetUSER_FWRITE_DIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetUSER_FWRITE_QIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetUSER_FWRITE_QIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI1.USER1: SPI1 user1 register. +func (o *SPI1_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3f)|value) +} +func (o *SPI1_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0x3f +} +func (o *SPI1_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI1_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI1.USER2: SPI1 user2 register. +func (o *SPI1_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI1_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI1_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI1.MOSI_DLEN: SPI1 send data bit length control register. +func (o *SPI1_Type) SetMOSI_DLEN_USR_MOSI_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MOSI_DLEN.Reg, volatile.LoadUint32(&o.MOSI_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetMOSI_DLEN_USR_MOSI_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MOSI_DLEN.Reg) & 0x3ff +} + +// SPI1.MISO_DLEN: SPI1 receive data bit length control register. +func (o *SPI1_Type) SetMISO_DLEN_USR_MISO_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MISO_DLEN.Reg, volatile.LoadUint32(&o.MISO_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetMISO_DLEN_USR_MISO_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MISO_DLEN.Reg) & 0x3ff +} + +// SPI1.RD_STATUS: SPI1 status register. +func (o *SPI1_Type) SetRD_STATUS_STATUS(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetRD_STATUS_STATUS() uint32 { + return volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xffff +} +func (o *SPI1_Type) SetRD_STATUS_WB_MODE(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetRD_STATUS_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI1.MISC: SPI1 misc register +func (o *SPI1_Type) SetMISC_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetMISC_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.MISC.Reg) & 0x1 +} +func (o *SPI1_Type) SetMISC_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetMISC_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x400) >> 10 +} + +// SPI1.TX_CRC: SPI1 TX CRC data register. +func (o *SPI1_Type) SetTX_CRC(value uint32) { + volatile.StoreUint32(&o.TX_CRC.Reg, value) +} +func (o *SPI1_Type) GetTX_CRC() uint32 { + return volatile.LoadUint32(&o.TX_CRC.Reg) +} + +// SPI1.CACHE_FCTRL: SPI1 bit mode control register. +func (o *SPI1_Type) SetCACHE_FCTRL_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetCACHE_FCTRL_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x100) >> 8 +} + +// SPI1.W0: SPI1 memory data buffer0 +func (o *SPI1_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI1_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI1.W1: SPI1 memory data buffer1 +func (o *SPI1_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI1_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI1.W2: SPI1 memory data buffer2 +func (o *SPI1_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI1_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI1.W3: SPI1 memory data buffer3 +func (o *SPI1_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI1_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI1.W4: SPI1 memory data buffer4 +func (o *SPI1_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI1_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI1.W5: SPI1 memory data buffer5 +func (o *SPI1_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI1_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI1.W6: SPI1 memory data buffer6 +func (o *SPI1_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI1_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI1.W7: SPI1 memory data buffer7 +func (o *SPI1_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI1_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI1.W8: SPI1 memory data buffer8 +func (o *SPI1_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI1_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI1.W9: SPI1 memory data buffer9 +func (o *SPI1_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI1_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI1.W10: SPI1 memory data buffer10 +func (o *SPI1_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI1_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI1.W11: SPI1 memory data buffer11 +func (o *SPI1_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI1_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI1.W12: SPI1 memory data buffer12 +func (o *SPI1_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI1_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI1.W13: SPI1 memory data buffer13 +func (o *SPI1_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI1_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI1.W14: SPI1 memory data buffer14 +func (o *SPI1_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI1_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI1.W15: SPI1 memory data buffer15 +func (o *SPI1_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI1_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI1.FLASH_WAITI_CTRL: SPI1 wait idle control register +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_DUMMY(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_DUMMY() uint32 { + return (volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_CMD(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0x3fc)|value<<2) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_CMD() uint32 { + return (volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0x3fc) >> 2 +} +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0xfc00)|value<<10) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0xfc00) >> 10 +} + +// SPI1.FLASH_SUS_CTRL: SPI1 flash suspend control register +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PER(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PER() uint32 { + return volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PES(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PES() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PER_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PER_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PES_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PES_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_PES_PER_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_PES_PER_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PES_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PES_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_PESR_END_MSK(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x3fffc0)|value<<6) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_PESR_END_MSK() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x3fffc0) >> 6 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_PER_END_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_PER_END_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_PES_END_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_PES_END_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_SUS_TIMEOUT_CNT(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0xfe000000)|value<<25) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_SUS_TIMEOUT_CNT() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0xfe000000) >> 25 +} + +// SPI1.FLASH_SUS_CMD: SPI1 flash suspend command register +func (o *SPI1_Type) SetFLASH_SUS_CMD_FLASH_PER_COMMAND(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_FLASH_PER_COMMAND() uint32 { + return volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0xff +} +func (o *SPI1_Type) SetFLASH_SUS_CMD_FLASH_PES_COMMAND(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_FLASH_PES_COMMAND() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetFLASH_SUS_CMD_WAIT_PESR_COMMAND(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_WAIT_PESR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SUS_STATUS: SPI1 flash suspend status register +func (o *SPI1_Type) SetSUS_STATUS_FLASH_SUS(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_SUS() uint32 { + return volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x1 +} +func (o *SPI1_Type) SetSUS_STATUS_WAIT_PESR_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSUS_STATUS_WAIT_PESR_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_HPM_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_HPM_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_RES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_RES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_DP_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_DP_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_PER_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_PER_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_PES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_PES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSUS_STATUS_SPI0_LOCK_EN(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetSUS_STATUS_SPI0_LOCK_EN() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x80) >> 7 +} + +// SPI1.TIMING_CALI: SPI1 timing control register +func (o *SPI1_Type) SetTIMING_CALI(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetTIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetTIMING_CALI_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI1_Type) GetTIMING_CALI_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI1.INT_ENA: SPI1 interrupt enable register +func (o *SPI1_Type) SetINT_ENA_PER_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_ENA_PER_END_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_ENA_PES_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_ENA_PES_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_ENA_WPE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_ENA_WPE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_ENA_SLV_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_ENA_SLV_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetINT_ENA_MST_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetINT_ENA_MST_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetINT_ENA_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetINT_ENA_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} + +// SPI1.INT_CLR: SPI1 interrupt clear register +func (o *SPI1_Type) SetINT_CLR_PER_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_CLR_PER_END_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_CLR_PES_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_CLR_PES_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_CLR_WPE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_CLR_WPE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_CLR_SLV_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_CLR_SLV_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetINT_CLR_MST_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetINT_CLR_MST_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetINT_CLR_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetINT_CLR_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} + +// SPI1.INT_RAW: SPI1 interrupt raw register +func (o *SPI1_Type) SetINT_RAW_PER_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_RAW_PER_END_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_RAW_PES_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_RAW_PES_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_RAW_WPE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_RAW_WPE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_RAW_SLV_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_RAW_SLV_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetINT_RAW_MST_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetINT_RAW_MST_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetINT_RAW_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetINT_RAW_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} + +// SPI1.INT_ST: SPI1 interrupt status register +func (o *SPI1_Type) SetINT_ST_PER_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_ST_PER_END_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_ST_PES_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_ST_PES_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_ST_WPE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_ST_WPE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_ST_SLV_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_ST_SLV_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetINT_ST_MST_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetINT_ST_MST_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetINT_ST_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetINT_ST_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} + +// SPI1.CLOCK_GATE: SPI1 clk_gate register +func (o *SPI1_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SPI1.DATE: Version control register +func (o *SPI1_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI1_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 2 +type SPI2_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CLOCK volatile.Register32 // 0xC + USER volatile.Register32 // 0x10 + USER1 volatile.Register32 // 0x14 + USER2 volatile.Register32 // 0x18 + MS_DLEN volatile.Register32 // 0x1C + MISC volatile.Register32 // 0x20 + DIN_MODE volatile.Register32 // 0x24 + DIN_NUM volatile.Register32 // 0x28 + DOUT_MODE volatile.Register32 // 0x2C + DMA_CONF volatile.Register32 // 0x30 + DMA_INT_ENA volatile.Register32 // 0x34 + DMA_INT_CLR volatile.Register32 // 0x38 + DMA_INT_RAW volatile.Register32 // 0x3C + DMA_INT_ST volatile.Register32 // 0x40 + DMA_INT_SET volatile.Register32 // 0x44 + _ [80]byte + W0 volatile.Register32 // 0x98 + W1 volatile.Register32 // 0x9C + W2 volatile.Register32 // 0xA0 + W3 volatile.Register32 // 0xA4 + W4 volatile.Register32 // 0xA8 + W5 volatile.Register32 // 0xAC + W6 volatile.Register32 // 0xB0 + W7 volatile.Register32 // 0xB4 + W8 volatile.Register32 // 0xB8 + W9 volatile.Register32 // 0xBC + W10 volatile.Register32 // 0xC0 + W11 volatile.Register32 // 0xC4 + W12 volatile.Register32 // 0xC8 + W13 volatile.Register32 // 0xCC + W14 volatile.Register32 // 0xD0 + W15 volatile.Register32 // 0xD4 + _ [8]byte + SLAVE volatile.Register32 // 0xE0 + SLAVE1 volatile.Register32 // 0xE4 + CLK_GATE volatile.Register32 // 0xE8 + _ [4]byte + DATE volatile.Register32 // 0xF0 +} + +// SPI2.CMD: Command control register +func (o *SPI2_Type) SetCMD_CONF_BITLEN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetCMD_CONF_BITLEN() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetCMD_UPDATE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetCMD_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} + +// SPI2.ADDR: Address value register +func (o *SPI2_Type) SetADDR(value uint32) { + volatile.StoreUint32(&o.ADDR.Reg, value) +} +func (o *SPI2_Type) GetADDR() uint32 { + return volatile.LoadUint32(&o.ADDR.Reg) +} + +// SPI2.CTRL: SPI control register +func (o *SPI2_Type) SetCTRL_DUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetCTRL_DUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetCTRL_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetCTRL_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetCTRL_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetCTRL_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetCTRL_FREAD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetCTRL_FREAD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetCTRL_HOLD_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetCTRL_HOLD_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetCTRL_WP_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetCTRL_WP_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetCTRL_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1800000)|value<<23) +} +func (o *SPI2_Type) GetCTRL_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1800000) >> 23 +} +func (o *SPI2_Type) SetCTRL_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x6000000)|value<<25) +} +func (o *SPI2_Type) GetCTRL_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x6000000) >> 25 +} + +// SPI2.CLOCK: SPI clock control register +func (o *SPI2_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI2_Type) SetCLOCK_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3c0000)|value<<18) +} +func (o *SPI2_Type) GetCLOCK_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3c0000) >> 18 +} +func (o *SPI2_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER: SPI USER control register +func (o *SPI2_Type) SetUSER_DOUTDIN(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetUSER_DOUTDIN() uint32 { + return volatile.LoadUint32(&o.USER.Reg) & 0x1 +} +func (o *SPI2_Type) SetUSER_QPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetUSER_QPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetUSER_OPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetUSER_OPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetUSER_TSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetUSER_TSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetUSER_RSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetUSER_RSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetUSER_FWRITE_OCT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetUSER_FWRITE_OCT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetUSER_USR_CONF_NXT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetUSER_USR_CONF_NXT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetUSER_SIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetUSER_SIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI2_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER1: SPI USER control register 1 +func (o *SPI2_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xff)|value) +} +func (o *SPI2_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0xff +} +func (o *SPI2_Type) SetUSER1_MST_WFULL_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetUSER1_MST_WFULL_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetUSER1_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3e0000)|value<<17) +} +func (o *SPI2_Type) GetUSER1_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x3e0000) >> 17 +} +func (o *SPI2_Type) SetUSER1_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x7c00000)|value<<22) +} +func (o *SPI2_Type) GetUSER1_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x7c00000) >> 22 +} +func (o *SPI2_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xf8000000) >> 27 +} + +// SPI2.USER2: SPI USER control register 2 +func (o *SPI2_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI2_Type) SetUSER2_MST_REMPTY_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER2_MST_REMPTY_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI2.MS_DLEN: SPI data bit length control register +func (o *SPI2_Type) SetMS_DLEN_MS_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.MS_DLEN.Reg, volatile.LoadUint32(&o.MS_DLEN.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetMS_DLEN_MS_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.MS_DLEN.Reg) & 0x3ffff +} + +// SPI2.MISC: SPI misc register +func (o *SPI2_Type) SetMISC_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetMISC_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.MISC.Reg) & 0x1 +} +func (o *SPI2_Type) SetMISC_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetMISC_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetMISC_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetMISC_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetMISC_CS3_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetMISC_CS3_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetMISC_CS4_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetMISC_CS4_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetMISC_CS5_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetMISC_CS5_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetMISC_CK_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetMISC_CK_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetMISC_MASTER_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1f80)|value<<7) +} +func (o *SPI2_Type) GetMISC_MASTER_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1f80) >> 7 +} +func (o *SPI2_Type) SetMISC_CLK_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetMISC_CLK_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetMISC_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetMISC_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetMISC_ADDR_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetMISC_ADDR_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetMISC_CMD_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetMISC_CMD_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetMISC_SLAVE_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetMISC_SLAVE_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetMISC_DQS_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetMISC_DQS_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetMISC_QUAD_DIN_PIN_SWAP(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetMISC_QUAD_DIN_PIN_SWAP() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000000) >> 31 +} + +// SPI2.DIN_MODE: SPI input delay mode configuration +func (o *SPI2_Type) SetDIN_MODE_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_MODE_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_MODE_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_MODE_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_MODE_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_MODE_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_MODE_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_MODE_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetDIN_MODE_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetDIN_MODE_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetDIN_MODE_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetDIN_MODE_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetDIN_MODE_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetDIN_MODE_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetDIN_MODE_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetDIN_MODE_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc000) >> 14 +} +func (o *SPI2_Type) SetDIN_MODE_TIMING_HCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDIN_MODE_TIMING_HCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x10000) >> 16 +} + +// SPI2.DIN_NUM: SPI input delay number configuration +func (o *SPI2_Type) SetDIN_NUM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_NUM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_NUM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_NUM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_NUM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_NUM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_NUM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_NUM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetDIN_NUM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetDIN_NUM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetDIN_NUM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetDIN_NUM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetDIN_NUM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetDIN_NUM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetDIN_NUM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetDIN_NUM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc000) >> 14 +} + +// SPI2.DOUT_MODE: SPI output delay mode configuration +func (o *SPI2_Type) SetDOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDOUT_MODE_D_DQS_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDOUT_MODE_D_DQS_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI2.DMA_CONF: SPI DMA control register +func (o *SPI2_Type) SetDMA_CONF_DMA_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_OUTFIFO_EMPTY() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_INFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_SLV_SEG_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_SLV_SEG_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetDMA_CONF_RX_EOF_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetDMA_CONF_RX_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_RX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_RX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_TX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_TX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetDMA_CONF_RX_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetDMA_CONF_RX_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetDMA_CONF_BUF_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetDMA_CONF_BUF_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// SPI2.DMA_INT_ENA: SPI interrupt enable register +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EX_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EX_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EN_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EN_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMDA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMDA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ENA_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ENA_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_CLR: SPI interrupt clear register +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EX_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EX_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EN_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EN_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD8_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD8_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD9_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD9_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMDA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMDA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_CLR_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_CLR_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_RAW: SPI interrupt raw register +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EX_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EX_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EN_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EN_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD8_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD8_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD9_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD9_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMDA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMDA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_RAW_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_RAW_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_ST: SPI interrupt status register +func (o *SPI2_Type) SetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EX_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EX_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EN_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EN_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD7_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD8_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD8_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD9_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD9_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMDA_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMDA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ST_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ST_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_SET: SPI interrupt software set register +func (o *SPI2_Type) SetDMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET() uint32 { + return volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_EX_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_EX_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_EN_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_EN_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD7_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD7_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD8_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD8_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD9_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD9_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMDA_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMDA_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_RD_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_RD_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_WR_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_WR_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_RD_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_RD_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_WR_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_WR_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_SET_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_SET_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_SET_SEG_MAGIC_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_SET_SEG_MAGIC_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_SET_APP2_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_SET_APP2_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_SET_APP1_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_SET_APP1_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x100000) >> 20 +} + +// SPI2.W0: SPI CPU-controlled buffer0 +func (o *SPI2_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI2_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI2.W1: SPI CPU-controlled buffer1 +func (o *SPI2_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI2_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI2.W2: SPI CPU-controlled buffer2 +func (o *SPI2_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI2_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI2.W3: SPI CPU-controlled buffer3 +func (o *SPI2_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI2_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI2.W4: SPI CPU-controlled buffer4 +func (o *SPI2_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI2_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI2.W5: SPI CPU-controlled buffer5 +func (o *SPI2_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI2_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI2.W6: SPI CPU-controlled buffer6 +func (o *SPI2_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI2_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI2.W7: SPI CPU-controlled buffer7 +func (o *SPI2_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI2_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI2.W8: SPI CPU-controlled buffer8 +func (o *SPI2_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI2_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI2.W9: SPI CPU-controlled buffer9 +func (o *SPI2_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI2_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI2.W10: SPI CPU-controlled buffer10 +func (o *SPI2_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI2_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI2.W11: SPI CPU-controlled buffer11 +func (o *SPI2_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI2_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI2.W12: SPI CPU-controlled buffer12 +func (o *SPI2_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI2_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI2.W13: SPI CPU-controlled buffer13 +func (o *SPI2_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI2_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI2.W14: SPI CPU-controlled buffer14 +func (o *SPI2_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI2_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI2.W15: SPI CPU-controlled buffer15 +func (o *SPI2_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI2_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI2.SLAVE: SPI slave control register +func (o *SPI2_Type) SetSLAVE_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SLAVE.Reg) & 0x3 +} +func (o *SPI2_Type) SetSLAVE_CLK_MODE_13(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE_13() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSLAVE_RSCK_DATA_OUT(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSLAVE_RSCK_DATA_OUT() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSLAVE_DMA_SEG_MAGIC_VALUE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3c00000)|value<<22) +} +func (o *SPI2_Type) GetSLAVE_DMA_SEG_MAGIC_VALUE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x3c00000) >> 22 +} +func (o *SPI2_Type) SetSLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetSLAVE_SOFT_RESET(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetSLAVE_SOFT_RESET() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetSLAVE_USR_CONF(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetSLAVE_USR_CONF() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x10000000) >> 28 +} + +// SPI2.SLAVE1: SPI slave control register 1 +func (o *SPI2_Type) SetSLAVE1_SLV_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetSLAVE1_SLV_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_COMMAND(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3fc0000)|value<<18) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3fc0000) >> 18 +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_ADDR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0xfc000000) >> 26 +} + +// SPI2.CLK_GATE: SPI module clock and register clock control +func (o *SPI2_Type) SetCLK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetCLK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x4) >> 2 +} + +// SPI2.DATE: Version control +func (o *SPI2_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI2_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// System Configuration Registers +type SYSTEM_Type struct { + CPU_PERI_CLK_EN volatile.Register32 // 0x0 + CPU_PERI_RST_EN volatile.Register32 // 0x4 + CPU_PER_CONF volatile.Register32 // 0x8 + MEM_PD_MASK volatile.Register32 // 0xC + PERIP_CLK_EN0 volatile.Register32 // 0x10 + PERIP_CLK_EN1 volatile.Register32 // 0x14 + PERIP_RST_EN0 volatile.Register32 // 0x18 + PERIP_RST_EN1 volatile.Register32 // 0x1C + BT_LPCK_DIV_INT volatile.Register32 // 0x20 + BT_LPCK_DIV_FRAC volatile.Register32 // 0x24 + CPU_INTR_FROM_CPU_0 volatile.Register32 // 0x28 + CPU_INTR_FROM_CPU_1 volatile.Register32 // 0x2C + CPU_INTR_FROM_CPU_2 volatile.Register32 // 0x30 + CPU_INTR_FROM_CPU_3 volatile.Register32 // 0x34 + RSA_PD_CTRL volatile.Register32 // 0x38 + EDMA_CTRL volatile.Register32 // 0x3C + CACHE_CONTROL volatile.Register32 // 0x40 + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL volatile.Register32 // 0x44 + RTC_FASTMEM_CONFIG volatile.Register32 // 0x48 + RTC_FASTMEM_CRC volatile.Register32 // 0x4C + REDUNDANT_ECO_CTRL volatile.Register32 // 0x50 + CLOCK_GATE volatile.Register32 // 0x54 + SYSCLK_CONF volatile.Register32 // 0x58 + MEM_PVT volatile.Register32 // 0x5C + COMB_PVT_LVT_CONF volatile.Register32 // 0x60 + COMB_PVT_NVT_CONF volatile.Register32 // 0x64 + COMB_PVT_HVT_CONF volatile.Register32 // 0x68 + COMB_PVT_ERR_LVT_SITE0 volatile.Register32 // 0x6C + COMB_PVT_ERR_NVT_SITE0 volatile.Register32 // 0x70 + COMB_PVT_ERR_HVT_SITE0 volatile.Register32 // 0x74 + COMB_PVT_ERR_LVT_SITE1 volatile.Register32 // 0x78 + COMB_PVT_ERR_NVT_SITE1 volatile.Register32 // 0x7C + COMB_PVT_ERR_HVT_SITE1 volatile.Register32 // 0x80 + COMB_PVT_ERR_LVT_SITE2 volatile.Register32 // 0x84 + COMB_PVT_ERR_NVT_SITE2 volatile.Register32 // 0x88 + COMB_PVT_ERR_HVT_SITE2 volatile.Register32 // 0x8C + COMB_PVT_ERR_LVT_SITE3 volatile.Register32 // 0x90 + COMB_PVT_ERR_NVT_SITE3 volatile.Register32 // 0x94 + COMB_PVT_ERR_HVT_SITE3 volatile.Register32 // 0x98 + _ [3936]byte + REG_DATE volatile.Register32 // 0xFFC +} + +// SYSTEM.CPU_PERI_CLK_EN: cpu_peripheral clock gating register +func (o *SYSTEM_Type) SetCPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_CLK_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetCPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_CLK_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg) & 0x80) >> 7 +} + +// SYSTEM.CPU_PERI_RST_EN: cpu_peripheral reset register +func (o *SYSTEM_Type) SetCPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_RST_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetCPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_RST_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg) & 0x80) >> 7 +} + +// SYSTEM.CPU_PER_CONF: cpu clock config register +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x3)|value) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPUPERIOD_SEL() uint32 { + return volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x3 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_PLL_FREQ_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_PLL_FREQ_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPU_WAITI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPU_WAITI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0xf0) >> 4 +} + +// SYSTEM.MEM_PD_MASK: memory power down mask register +func (o *SYSTEM_Type) SetMEM_PD_MASK_LSLP_MEM_PD_MASK(value uint32) { + volatile.StoreUint32(&o.MEM_PD_MASK.Reg, volatile.LoadUint32(&o.MEM_PD_MASK.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetMEM_PD_MASK_LSLP_MEM_PD_MASK() uint32 { + return volatile.LoadUint32(&o.MEM_PD_MASK.Reg) & 0x1 +} + +// SYSTEM.PERIP_CLK_EN0: peripheral clock gating register +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI01_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI01_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2C_EXT0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2C_EXT0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_LEDC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x800)|value<<11) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_LEDC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x800) >> 11 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERGROUP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERGROUP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2000) >> 13 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_APB_SARADC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_APB_SARADC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10000000) >> 28 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SYSTIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SYSTIMER_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20000000) >> 29 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_ADC2_ARB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_ADC2_ARB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40000000) >> 30 +} + +// SYSTEM.PERIP_CLK_EN1: peripheral clock gating register +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_ECC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_ECC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_SHA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_SHA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_TSENS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_TSENS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x400) >> 10 +} + +// SYSTEM.PERIP_RST_EN0: reserved +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI01_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI01_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2C_EXT0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2C_EXT0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_LEDC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x800)|value<<11) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_LEDC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x800) >> 11 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERGROUP_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERGROUP_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2000) >> 13 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART_MEM_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_APB_SARADC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_APB_SARADC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10000000) >> 28 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SYSTIMER_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SYSTIMER_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20000000) >> 29 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_ADC2_ARB_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_ADC2_ARB_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40000000) >> 30 +} + +// SYSTEM.PERIP_RST_EN1: peripheral reset register +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_ECC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_ECC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_SHA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_SHA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_TSENS_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_TSENS_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x400) >> 10 +} + +// SYSTEM.BT_LPCK_DIV_INT: clock config register +func (o *SYSTEM_Type) SetBT_LPCK_DIV_INT_BT_LPCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_INT.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg)&^(0xfff)|value) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_INT_BT_LPCK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg) & 0xfff +} + +// SYSTEM.BT_LPCK_DIV_FRAC: low power clock configuration register +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_B(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0xfff)|value) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_B() uint32 { + return volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0xfff +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_A(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0xfff000)|value<<12) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0xfff000) >> 12 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_RTC_EN(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_RTC_EN() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x10000000) >> 28 +} + +// SYSTEM.CPU_INTR_FROM_CPU_0: interrupt generate register +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_0(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_0() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_1: interrupt generate register +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_1(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_1() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_2: interrupt generate register +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_2(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_2() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_3: interrupt generate register +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_3(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_3() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg) & 0x1 +} + +// SYSTEM.RSA_PD_CTRL: rsa memory power control register +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_PD() uint32 { + return volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x4) >> 2 +} + +// SYSTEM.EDMA_CTRL: edma clcok and reset register +func (o *SYSTEM_Type) SetEDMA_CTRL_EDMA_CLK_ON(value uint32) { + volatile.StoreUint32(&o.EDMA_CTRL.Reg, volatile.LoadUint32(&o.EDMA_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetEDMA_CTRL_EDMA_CLK_ON() uint32 { + return volatile.LoadUint32(&o.EDMA_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetEDMA_CTRL_EDMA_RESET(value uint32) { + volatile.StoreUint32(&o.EDMA_CTRL.Reg, volatile.LoadUint32(&o.EDMA_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetEDMA_CTRL_EDMA_RESET() uint32 { + return (volatile.LoadUint32(&o.EDMA_CTRL.Reg) & 0x2) >> 1 +} + +// SYSTEM.CACHE_CONTROL: cache control register +func (o *SYSTEM_Type) SetCACHE_CONTROL_ICACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_ICACHE_CLK_ON() uint32 { + return volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_ICACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_ICACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_DCACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_DCACHE_CLK_ON() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_DCACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_DCACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x8) >> 3 +} + +// SYSTEM.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x8) >> 3 +} + +// SYSTEM.RTC_FASTMEM_CONFIG: fast memory config register +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_START(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_START() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0xffe00)|value<<9) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0xffe00) >> 9 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x7ff00000)|value<<20) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x7ff00000) >> 20 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.RTC_FASTMEM_CRC: reserved +func (o *SYSTEM_Type) SetRTC_FASTMEM_CRC(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CRC.Reg, value) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CRC() uint32 { + return volatile.LoadUint32(&o.RTC_FASTMEM_CRC.Reg) +} + +// SYSTEM.REDUNDANT_ECO_CTRL: eco register +func (o *SYSTEM_Type) SetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE(value uint32) { + volatile.StoreUint32(&o.REDUNDANT_ECO_CTRL.Reg, volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE() uint32 { + return volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.REDUNDANT_ECO_CTRL.Reg, volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg) & 0x2) >> 1 +} + +// SYSTEM.CLOCK_GATE: clock gating register +func (o *SYSTEM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SYSTEM.SYSCLK_CONF: system clock config register +func (o *SYSTEM_Type) SetSYSCLK_CONF_PRE_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x3ff)|value) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_PRE_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x3ff +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_SOC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_SOC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0xc00) >> 10 +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_CLK_XTAL_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x7f000)|value<<12) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_CLK_XTAL_FREQ() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x7f000) >> 12 +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_CLK_DIV_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_CLK_DIV_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x80000) >> 19 +} + +// SYSTEM.MEM_PVT: mem pvt register +func (o *SYSTEM_Type) SetMEM_PVT_MEM_PATH_LEN(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0xf)|value) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_PATH_LEN() uint32 { + return volatile.LoadUint32(&o.MEM_PVT.Reg) & 0xf +} +func (o *SYSTEM_Type) SetMEM_PVT_MEM_ERR_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_ERR_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetMEM_PVT_MONITOR_EN(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetMEM_PVT_MONITOR_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetMEM_PVT_MEM_TIMING_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0x3fffc0)|value<<6) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_TIMING_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0x3fffc0) >> 6 +} +func (o *SYSTEM_Type) SetMEM_PVT_MEM_VT_SEL(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0xc00000)|value<<22) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_VT_SEL() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0xc00000) >> 22 +} + +// SYSTEM.COMB_PVT_LVT_CONF: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_LVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg)&^(0x3f)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg) & 0x3f +} +func (o *SYSTEM_Type) SetCOMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_LVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCOMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetCOMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_LVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCOMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg) & 0x80) >> 7 +} + +// SYSTEM.COMB_PVT_NVT_CONF: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_NVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg)&^(0x3f)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg) & 0x3f +} +func (o *SYSTEM_Type) SetCOMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_NVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCOMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetCOMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_NVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCOMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg) & 0x80) >> 7 +} + +// SYSTEM.COMB_PVT_HVT_CONF: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_HVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg)&^(0x3f)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg) & 0x3f +} +func (o *SYSTEM_Type) SetCOMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_HVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCOMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetCOMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_HVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCOMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg) & 0x80) >> 7 +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE0: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE0.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE0.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE0.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE0: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE0.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE0.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE0.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE0: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE0.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE0.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE0.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE1: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE1.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE1.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE1.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE1: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE1.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE1.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE1.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE1: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE1.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE1.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE1.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE2: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE2.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE2.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE2.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE2: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE2.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE2.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE2.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE2: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE2.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE2.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE2.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE3: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE3.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE3.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE3.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE3: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE3.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE3.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE3.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE3: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE3.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE3.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE3.Reg) & 0xffff +} + +// SYSTEM.REG_DATE: Version register +func (o *SYSTEM_Type) SetREG_DATE_SYSTEM_REG_DATE(value uint32) { + volatile.StoreUint32(&o.REG_DATE.Reg, volatile.LoadUint32(&o.REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SYSTEM_Type) GetREG_DATE_SYSTEM_REG_DATE() uint32 { + return volatile.LoadUint32(&o.REG_DATE.Reg) & 0xfffffff +} + +// System Timer +type SYSTIMER_Type struct { + CONF volatile.Register32 // 0x0 + UNIT0_OP volatile.Register32 // 0x4 + UNIT1_OP volatile.Register32 // 0x8 + UNIT0_LOAD_HI volatile.Register32 // 0xC + UNIT0_LOAD_LO volatile.Register32 // 0x10 + UNIT1_LOAD_HI volatile.Register32 // 0x14 + UNIT1_LOAD_LO volatile.Register32 // 0x18 + TARGET0_HI volatile.Register32 // 0x1C + TARGET0_LO volatile.Register32 // 0x20 + TARGET1_HI volatile.Register32 // 0x24 + TARGET1_LO volatile.Register32 // 0x28 + TARGET2_HI volatile.Register32 // 0x2C + TARGET2_LO volatile.Register32 // 0x30 + TARGET0_CONF volatile.Register32 // 0x34 + TARGET1_CONF volatile.Register32 // 0x38 + TARGET2_CONF volatile.Register32 // 0x3C + UNIT0_VALUE_HI volatile.Register32 // 0x40 + UNIT0_VALUE_LO volatile.Register32 // 0x44 + UNIT1_VALUE_HI volatile.Register32 // 0x48 + UNIT1_VALUE_LO volatile.Register32 // 0x4C + COMP0_LOAD volatile.Register32 // 0x50 + COMP1_LOAD volatile.Register32 // 0x54 + COMP2_LOAD volatile.Register32 // 0x58 + UNIT0_LOAD volatile.Register32 // 0x5C + UNIT1_LOAD volatile.Register32 // 0x60 + INT_ENA volatile.Register32 // 0x64 + INT_RAW volatile.Register32 // 0x68 + INT_CLR volatile.Register32 // 0x6C + INT_ST volatile.Register32 // 0x70 + _ [136]byte + DATE volatile.Register32 // 0xFC +} + +// SYSTIMER.CONF: Configure system timer clock +func (o *SYSTIMER_Type) SetCONF_SYSTIMER_CLK_FO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCONF_SYSTIMER_CLK_FO() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetCONF_TARGET2_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTIMER_Type) GetCONF_TARGET2_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22 +} +func (o *SYSTIMER_Type) SetCONF_TARGET1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTIMER_Type) GetCONF_TARGET1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23 +} +func (o *SYSTIMER_Type) SetCONF_TARGET0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTIMER_Type) GetCONF_TARGET0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000000) >> 26 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000000) >> 27 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000000) >> 28 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_OP: system timer unit0 value update register +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT1_OP: system timer unit1 value update register +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT0_LOAD_HI: system timer unit0 value high load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_LOAD_LO: system timer unit0 value low load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_LO.Reg) +} + +// SYSTIMER.UNIT1_LOAD_HI: system timer unit1 value high load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_LOAD_LO: system timer unit1 value low load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_LO.Reg) +} + +// SYSTIMER.TARGET0_HI: system timer comp0 value high register +func (o *SYSTIMER_Type) SetTARGET0_HI_TIMER_TARGET0_HI(value uint32) { + volatile.StoreUint32(&o.TARGET0_HI.Reg, volatile.LoadUint32(&o.TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_HI_TIMER_TARGET0_HI() uint32 { + return volatile.LoadUint32(&o.TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET0_LO: system timer comp0 value low register +func (o *SYSTIMER_Type) SetTARGET0_LO(value uint32) { + volatile.StoreUint32(&o.TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET0_LO() uint32 { + return volatile.LoadUint32(&o.TARGET0_LO.Reg) +} + +// SYSTIMER.TARGET1_HI: system timer comp1 value high register +func (o *SYSTIMER_Type) SetTARGET1_HI_TIMER_TARGET1_HI(value uint32) { + volatile.StoreUint32(&o.TARGET1_HI.Reg, volatile.LoadUint32(&o.TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_HI_TIMER_TARGET1_HI() uint32 { + return volatile.LoadUint32(&o.TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET1_LO: system timer comp1 value low register +func (o *SYSTIMER_Type) SetTARGET1_LO(value uint32) { + volatile.StoreUint32(&o.TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET1_LO() uint32 { + return volatile.LoadUint32(&o.TARGET1_LO.Reg) +} + +// SYSTIMER.TARGET2_HI: system timer comp2 value high register +func (o *SYSTIMER_Type) SetTARGET2_HI_TIMER_TARGET2_HI(value uint32) { + volatile.StoreUint32(&o.TARGET2_HI.Reg, volatile.LoadUint32(&o.TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_HI_TIMER_TARGET2_HI() uint32 { + return volatile.LoadUint32(&o.TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET2_LO: system timer comp2 value low register +func (o *SYSTIMER_Type) SetTARGET2_LO(value uint32) { + volatile.StoreUint32(&o.TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET2_LO() uint32 { + return volatile.LoadUint32(&o.TARGET2_LO.Reg) +} + +// SYSTIMER.TARGET0_CONF: system timer comp0 target mode register +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET1_CONF: system timer comp1 target mode register +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET2_CONF: system timer comp2 target mode register +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_VALUE_HI: system timer unit0 value high register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_VALUE_LO: system timer unit0 value low register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_LO.Reg) +} + +// SYSTIMER.UNIT1_VALUE_HI: system timer unit1 value high register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_VALUE_LO: system timer unit1 value low register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_LO.Reg) +} + +// SYSTIMER.COMP0_LOAD: system timer comp0 conf sync register +func (o *SYSTIMER_Type) SetCOMP0_LOAD_TIMER_COMP0_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP0_LOAD.Reg, volatile.LoadUint32(&o.COMP0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP0_LOAD_TIMER_COMP0_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP1_LOAD: system timer comp1 conf sync register +func (o *SYSTIMER_Type) SetCOMP1_LOAD_TIMER_COMP1_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP1_LOAD.Reg, volatile.LoadUint32(&o.COMP1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP1_LOAD_TIMER_COMP1_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP2_LOAD: system timer comp2 conf sync register +func (o *SYSTIMER_Type) SetCOMP2_LOAD_TIMER_COMP2_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP2_LOAD.Reg, volatile.LoadUint32(&o.COMP2_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP2_LOAD_TIMER_COMP2_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP2_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT0_LOAD: system timer unit0 conf sync register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_TIMER_UNIT0_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD.Reg, volatile.LoadUint32(&o.UNIT0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_TIMER_UNIT0_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT1_LOAD: system timer unit1 conf sync register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_TIMER_UNIT1_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD.Reg, volatile.LoadUint32(&o.UNIT1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_TIMER_UNIT1_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.INT_ENA: systimer interrupt enable register +func (o *SYSTIMER_Type) SetINT_ENA_TARGET0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_RAW: systimer interrupt raw register +func (o *SYSTIMER_Type) SetINT_RAW_TARGET0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_CLR: systimer interrupt clear register +func (o *SYSTIMER_Type) SetINT_CLR_TARGET0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_ST: systimer interrupt status register +func (o *SYSTIMER_Type) SetINT_ST_TARGET0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// SYSTIMER.DATE: system timer version control register +func (o *SYSTIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *SYSTIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Timer Group 0 +type TIMG_Type struct { + T0CONFIG volatile.Register32 // 0x0 + T0LO volatile.Register32 // 0x4 + T0HI volatile.Register32 // 0x8 + T0UPDATE volatile.Register32 // 0xC + T0ALARMLO volatile.Register32 // 0x10 + T0ALARMHI volatile.Register32 // 0x14 + T0LOADLO volatile.Register32 // 0x18 + T0LOADHI volatile.Register32 // 0x1C + T0LOAD volatile.Register32 // 0x20 + _ [36]byte + WDTCONFIG0 volatile.Register32 // 0x48 + WDTCONFIG1 volatile.Register32 // 0x4C + WDTCONFIG2 volatile.Register32 // 0x50 + WDTCONFIG3 volatile.Register32 // 0x54 + WDTCONFIG4 volatile.Register32 // 0x58 + WDTCONFIG5 volatile.Register32 // 0x5C + WDTFEED volatile.Register32 // 0x60 + WDTWPROTECT volatile.Register32 // 0x64 + RTCCALICFG volatile.Register32 // 0x68 + RTCCALICFG1 volatile.Register32 // 0x6C + INT_ENA_TIMERS volatile.Register32 // 0x70 + INT_RAW_TIMERS volatile.Register32 // 0x74 + INT_ST_TIMERS volatile.Register32 // 0x78 + INT_CLR_TIMERS volatile.Register32 // 0x7C + RTCCALICFG2 volatile.Register32 // 0x80 + _ [116]byte + NTIMERS_DATE volatile.Register32 // 0xF8 + REGCLK volatile.Register32 // 0xFC +} + +// TIMG.T0CONFIG: Timer %s configuration register +func (o *TIMG_Type) SetT0CONFIG_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetT0CONFIG_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetT0CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT0CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT0CONFIG_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetT0CONFIG_DIVCNT_RST() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetT0CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT0CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT0CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT0CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT0CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT0CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT0CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0LO: Timer %s current value, low 32 bits +func (o *TIMG_Type) SetT0LO(value uint32) { + volatile.StoreUint32(&o.T0LO.Reg, value) +} +func (o *TIMG_Type) GetT0LO() uint32 { + return volatile.LoadUint32(&o.T0LO.Reg) +} + +// TIMG.T0HI: Timer %s current value, high 22 bits +func (o *TIMG_Type) SetT0HI_T0_HI(value uint32) { + volatile.StoreUint32(&o.T0HI.Reg, volatile.LoadUint32(&o.T0HI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0HI_T0_HI() uint32 { + return volatile.LoadUint32(&o.T0HI.Reg) & 0x3fffff +} + +// TIMG.T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG +func (o *TIMG_Type) SetT0UPDATE_T0_UPDATE(value uint32) { + volatile.StoreUint32(&o.T0UPDATE.Reg, volatile.LoadUint32(&o.T0UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0UPDATE_T0_UPDATE() uint32 { + return (volatile.LoadUint32(&o.T0UPDATE.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0ALARMLO: Timer %s alarm value, low 32 bits +func (o *TIMG_Type) SetT0ALARMLO(value uint32) { + volatile.StoreUint32(&o.T0ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMLO() uint32 { + return volatile.LoadUint32(&o.T0ALARMLO.Reg) +} + +// TIMG.T0ALARMHI: Timer %s alarm value, high bits +func (o *TIMG_Type) SetT0ALARMHI_ALARM_HI(value uint32) { + volatile.StoreUint32(&o.T0ALARMHI.Reg, volatile.LoadUint32(&o.T0ALARMHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0ALARMHI_ALARM_HI() uint32 { + return volatile.LoadUint32(&o.T0ALARMHI.Reg) & 0x3fffff +} + +// TIMG.T0LOADLO: Timer %s reload value, low 32 bits +func (o *TIMG_Type) SetT0LOADLO(value uint32) { + volatile.StoreUint32(&o.T0LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT0LOADLO() uint32 { + return volatile.LoadUint32(&o.T0LOADLO.Reg) +} + +// TIMG.T0LOADHI: Timer %s reload value, high 22 bits +func (o *TIMG_Type) SetT0LOADHI_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.T0LOADHI.Reg, volatile.LoadUint32(&o.T0LOADHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0LOADHI_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.T0LOADHI.Reg) & 0x3fffff +} + +// TIMG.T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG +func (o *TIMG_Type) SetT0LOAD(value uint32) { + volatile.StoreUint32(&o.T0LOAD.Reg, value) +} +func (o *TIMG_Type) GetT0LOAD() uint32 { + return volatile.LoadUint32(&o.T0LOAD.Reg) +} + +// TIMG.WDTCONFIG0: Watchdog timer configuration register +func (o *TIMG_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x2000)|value<<13) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x2000) >> 13 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x4000)|value<<14) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x4000) >> 14 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x38000)|value<<15) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x38000) >> 15 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c0000)|value<<18) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c0000) >> 18 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200000)|value<<21) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200000) >> 21 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CONF_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400000)|value<<22) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CONF_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400000) >> 22 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1800000)|value<<23) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1800000) >> 23 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x6000000)|value<<25) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x6000000) >> 25 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x18000000)|value<<27) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x18000000) >> 27 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x60000000)|value<<29) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x60000000) >> 29 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// TIMG.WDTCONFIG1: Watchdog timer prescaler register +func (o *TIMG_Type) SetWDTCONFIG1_WDT_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_DIVCNT_RST() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetWDTCONFIG1_WDT_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_CLK_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0xffff0000) >> 16 +} + +// TIMG.WDTCONFIG2: Watchdog timer stage 0 timeout value +func (o *TIMG_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// TIMG.WDTCONFIG3: Watchdog timer stage 1 timeout value +func (o *TIMG_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// TIMG.WDTCONFIG4: Watchdog timer stage 2 timeout value +func (o *TIMG_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// TIMG.WDTCONFIG5: Watchdog timer stage 3 timeout value +func (o *TIMG_Type) SetWDTCONFIG5(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG5.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG5() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG5.Reg) +} + +// TIMG.WDTFEED: Write to feed the watchdog timer +func (o *TIMG_Type) SetWDTFEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, value) +} +func (o *TIMG_Type) GetWDTFEED() uint32 { + return volatile.LoadUint32(&o.WDTFEED.Reg) +} + +// TIMG.WDTWPROTECT: Watchdog write protect register +func (o *TIMG_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *TIMG_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// TIMG.RTCCALICFG: RTC calibration configure register +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START_CYCLING(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START_CYCLING() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x6000)|value<<13) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x6000) >> 13 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_RDY(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x8000)|value<<15) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_RDY() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x8000) >> 15 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_MAX(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x7fff0000)|value<<16) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_MAX() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x7fff0000) >> 16 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x80000000) >> 31 +} + +// TIMG.RTCCALICFG1: RTC calibration configure1 register +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_VALUE(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_VALUE() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0xffffff80) >> 7 +} + +// TIMG.INT_ENA_TIMERS: Interrupt enable bits +func (o *TIMG_Type) SetINT_ENA_TIMERS_T0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_RAW_TIMERS: Raw interrupt status +func (o *TIMG_Type) SetINT_RAW_TIMERS_T0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_ST_TIMERS: Masked interrupt status +func (o *TIMG_Type) SetINT_ST_TIMERS_T0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_CLR_TIMERS: Interrupt clear bits +func (o *TIMG_Type) SetINT_CLR_TIMERS_T0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.RTCCALICFG2: Timer group calibration register +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x78)|value<<3) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x78) >> 3 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0xffffff80) >> 7 +} + +// TIMG.NTIMERS_DATE: Timer version control register +func (o *TIMG_Type) SetNTIMERS_DATE_NTIMGS_DATE(value uint32) { + volatile.StoreUint32(&o.NTIMERS_DATE.Reg, volatile.LoadUint32(&o.NTIMERS_DATE.Reg)&^(0xfffffff)|value) +} +func (o *TIMG_Type) GetNTIMERS_DATE_NTIMGS_DATE() uint32 { + return volatile.LoadUint32(&o.NTIMERS_DATE.Reg) & 0xfffffff +} + +// TIMG.REGCLK: Timer group clock gate register +func (o *TIMG_Type) SetREGCLK_WDT_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetREGCLK_WDT_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetREGCLK_TIMER_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetREGCLK_TIMER_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetREGCLK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetREGCLK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x80000000) >> 31 +} + +// UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +type UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV volatile.Register32 // 0x14 + RX_FILT volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0 volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + LOWPULSE volatile.Register32 // 0x28 + HIGHPULSE volatile.Register32 // 0x2C + RXD_CNT volatile.Register32 // 0x30 + FLOW_CONF volatile.Register32 // 0x34 + SLEEP_CONF volatile.Register32 // 0x38 + SWFC_CONF0 volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + TXBRK_CONF volatile.Register32 // 0x44 + IDLE_CONF volatile.Register32 // 0x48 + RS485_CONF volatile.Register32 // 0x4C + AT_CMD_PRECNT volatile.Register32 // 0x50 + AT_CMD_POSTCNT volatile.Register32 // 0x54 + AT_CMD_GAPTOUT volatile.Register32 // 0x58 + AT_CMD_CHAR volatile.Register32 // 0x5C + MEM_CONF volatile.Register32 // 0x60 + MEM_TX_STATUS volatile.Register32 // 0x64 + MEM_RX_STATUS volatile.Register32 // 0x68 + FSM_STATUS volatile.Register32 // 0x6C + POSPULSE volatile.Register32 // 0x70 + NEGPULSE volatile.Register32 // 0x74 + CLK_CONF volatile.Register32 // 0x78 + DATE volatile.Register32 // 0x7C + ID volatile.Register32 // 0x80 +} + +// UART.FIFO: FIFO data register +func (o *UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// UART.INT_RAW: Raw interrupt status +func (o *UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_RAW_RS485_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_RAW_RS485_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_RAW_RS485_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_RAW_RS485_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_RAW_RS485_CLASH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_RAW_RS485_CLASH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// UART.INT_ST: Masked interrupt status +func (o *UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ST_RS485_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ST_RS485_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ST_RS485_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ST_RS485_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ST_RS485_CLASH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ST_RS485_CLASH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// UART.INT_ENA: Interrupt enable bits +func (o *UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ENA_RS485_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ENA_RS485_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ENA_RS485_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ENA_RS485_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ENA_RS485_CLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ENA_RS485_CLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// UART.INT_CLR: Interrupt clear bits +func (o *UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_CLR_RS485_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_CLR_RS485_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_CLR_RS485_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_CLR_RS485_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_CLR_RS485_CLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_CLR_RS485_CLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// UART.CLKDIV: Clock divider configuration +func (o *UART_Type) SetCLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetCLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xfff +} +func (o *UART_Type) SetCLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xf00000)|value<<20) +} +func (o *UART_Type) GetCLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xf00000) >> 20 +} + +// UART.RX_FILT: Rx Filter configuration +func (o *UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT() uint32 { + return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff +} +func (o *UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8 +} + +// UART.STATUS: UART status register +func (o *UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ff0000)|value<<16) +} +func (o *UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3ff0000) >> 16 +} +func (o *UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// UART.CONF0: a +func (o *UART_Type) SetCONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetCONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UART_Type) SetCONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetCONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetCONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0xc)|value<<2) +} +func (o *UART_Type) GetCONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0xc) >> 2 +} +func (o *UART_Type) SetCONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x30)|value<<4) +} +func (o *UART_Type) GetCONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x30) >> 4 +} +func (o *UART_Type) SetCONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetCONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetCONF0_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetCONF0_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetCONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetCONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetCONF0_IRDA_DPLX(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetCONF0_IRDA_DPLX() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetCONF0_IRDA_TX_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetCONF0_IRDA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetCONF0_IRDA_WCTL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetCONF0_IRDA_WCTL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetCONF0_IRDA_TX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetCONF0_IRDA_TX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetCONF0_IRDA_RX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetCONF0_IRDA_RX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetCONF0_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetCONF0_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetCONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetCONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetCONF0_IRDA_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF0_IRDA_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF0_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF0_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF0_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF0_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF0_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF0_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetCONF0_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCONF0_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCONF0_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF0_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCONF0_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCONF0_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCONF0_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCONF0_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCONF0_AUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCONF0_AUTOBAUD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000000) >> 27 +} +func (o *UART_Type) SetCONF0_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *UART_Type) GetCONF0_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000000) >> 28 +} + +// UART.CONF1: Configuration register 1 +func (o *UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1ff)|value) +} +func (o *UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1ff +} +func (o *UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x3fe00)|value<<9) +} +func (o *UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x3fe00) >> 9 +} +func (o *UART_Type) SetCONF1_DIS_RX_DAT_OVF(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF1_DIS_RX_DAT_OVF() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF1_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF1_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF1_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF1_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF1_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF1_RX_TOUT_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} + +// UART.LOWPULSE: Autobaud minimum low pulse duration register +func (o *UART_Type) SetLOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.LOWPULSE.Reg, volatile.LoadUint32(&o.LOWPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetLOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.LOWPULSE.Reg) & 0xfff +} + +// UART.HIGHPULSE: Autobaud minimum high pulse duration register +func (o *UART_Type) SetHIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.HIGHPULSE.Reg, volatile.LoadUint32(&o.HIGHPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetHIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.HIGHPULSE.Reg) & 0xfff +} + +// UART.RXD_CNT: Autobaud edge change count register +func (o *UART_Type) SetRXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.RXD_CNT.Reg, volatile.LoadUint32(&o.RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetRXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.RXD_CNT.Reg) & 0x3ff +} + +// UART.FLOW_CONF: Software flow-control configuration +func (o *UART_Type) SetFLOW_CONF_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetFLOW_CONF_SW_FLOW_CON_EN() uint32 { + return volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetFLOW_CONF_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetFLOW_CONF_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x20) >> 5 +} + +// UART.SLEEP_CONF: Sleep-mode configuration +func (o *UART_Type) SetSLEEP_CONF_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF.Reg, volatile.LoadUint32(&o.SLEEP_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSLEEP_CONF_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF.Reg) & 0x3ff +} + +// UART.SWFC_CONF0: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF0_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x1ff)|value) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x1ff +} +func (o *UART_Type) SetSWFC_CONF0_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x1fe00) >> 9 +} + +// UART.SWFC_CONF1: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0x1ff)|value) +} +func (o *UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0x1ff +} +func (o *UART_Type) SetSWFC_CONF1_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetSWFC_CONF1_XON_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0x1fe00) >> 9 +} + +// UART.TXBRK_CONF: Tx Break character configuration +func (o *UART_Type) SetTXBRK_CONF_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.TXBRK_CONF.Reg, volatile.LoadUint32(&o.TXBRK_CONF.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetTXBRK_CONF_TX_BRK_NUM() uint32 { + return volatile.LoadUint32(&o.TXBRK_CONF.Reg) & 0xff +} + +// UART.IDLE_CONF: Frame-end idle configuration +func (o *UART_Type) SetIDLE_CONF_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetIDLE_CONF_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0x3ff +} +func (o *UART_Type) SetIDLE_CONF_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *UART_Type) GetIDLE_CONF_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xffc00) >> 10 +} + +// UART.RS485_CONF: RS485 mode configuration +func (o *UART_Type) SetRS485_CONF_RS485_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetRS485_CONF_RS485_EN() uint32 { + return volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetRS485_CONF_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetRS485_CONF_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetRS485_CONF_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetRS485_CONF_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetRS485_CONF_RS485TX_RX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetRS485_CONF_RS485TX_RX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetRS485_CONF_RS485RXBY_TX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetRS485_CONF_RS485RXBY_TX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetRS485_CONF_RS485_RX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetRS485_CONF_RS485_RX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetRS485_CONF_RS485_TX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x3c0)|value<<6) +} +func (o *UART_Type) GetRS485_CONF_RS485_TX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x3c0) >> 6 +} + +// UART.AT_CMD_PRECNT: Pre-sequence timing configuration +func (o *UART_Type) SetAT_CMD_PRECNT_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_PRECNT_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg) & 0xffff +} + +// UART.AT_CMD_POSTCNT: Post-sequence timing configuration +func (o *UART_Type) SetAT_CMD_POSTCNT_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_POSTCNT_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg) & 0xffff +} + +// UART.AT_CMD_GAPTOUT: Timeout configuration +func (o *UART_Type) SetAT_CMD_GAPTOUT_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_GAPTOUT_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg) & 0xffff +} + +// UART.AT_CMD_CHAR: AT escape sequence detection configuration +func (o *UART_Type) SetAT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetAT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff +} +func (o *UART_Type) SetAT_CMD_CHAR_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAT_CMD_CHAR_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff00) >> 8 +} + +// UART.MEM_CONF: UART threshold and allocation configuration +func (o *UART_Type) SetMEM_CONF_RX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xe)|value<<1) +} +func (o *UART_Type) GetMEM_CONF_RX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xe) >> 1 +} +func (o *UART_Type) SetMEM_CONF_TX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x70)|value<<4) +} +func (o *UART_Type) GetMEM_CONF_TX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x70) >> 4 +} +func (o *UART_Type) SetMEM_CONF_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xff80)|value<<7) +} +func (o *UART_Type) GetMEM_CONF_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xff80) >> 7 +} +func (o *UART_Type) SetMEM_CONF_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x3ff0000)|value<<16) +} +func (o *UART_Type) GetMEM_CONF_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x3ff0000) >> 16 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x8000000) >> 27 +} + +// UART.MEM_TX_STATUS: Tx-FIFO write and read offset address. +func (o *UART_Type) SetMEM_TX_STATUS_APB_TX_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetMEM_TX_STATUS_APB_TX_WADDR() uint32 { + return volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetMEM_TX_STATUS_TX_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1ff800) >> 11 +} + +// UART.MEM_RX_STATUS: Rx-FIFO write and read offset address. +func (o *UART_Type) SetMEM_RX_STATUS_APB_RX_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetMEM_RX_STATUS_APB_RX_RADDR() uint32 { + return volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetMEM_RX_STATUS_RX_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1ff800) >> 11 +} + +// UART.FSM_STATUS: UART transmit and receive status. +func (o *UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// UART.POSPULSE: Autobaud high pulse register +func (o *UART_Type) SetPOSPULSE_POSEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.POSPULSE.Reg, volatile.LoadUint32(&o.POSPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetPOSPULSE_POSEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.POSPULSE.Reg) & 0xfff +} + +// UART.NEGPULSE: Autobaud low pulse register +func (o *UART_Type) SetNEGPULSE_NEGEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.NEGPULSE.Reg, volatile.LoadUint32(&o.NEGPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetNEGPULSE_NEGEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.NEGPULSE.Reg) & 0xfff +} + +// UART.CLK_CONF: UART core clock configuration +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f)|value) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f +} +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *UART_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *UART_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *UART_Type) SetCLK_CONF_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCLK_CONF_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCLK_CONF_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCLK_CONF_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} + +// UART.DATE: UART Version register +func (o *UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// UART.ID: UART ID register +func (o *UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0x3fffffff)|value) +} +func (o *UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) & 0x3fffffff +} +func (o *UART_Type) SetID_HIGH_SPEED(value uint32) { + volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetID_HIGH_SPEED() uint32 { + return (volatile.LoadUint32(&o.ID.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetID_REG_UPDATE(value uint32) { + volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetID_REG_UPDATE() uint32 { + return (volatile.LoadUint32(&o.ID.Reg) & 0x80000000) >> 31 +} + +// XTS-AES-128 Flash Encryption +type XTS_AES_Type struct { + PLAIN_MEM [16]volatile.Register8 // 0x0 + _ [48]byte + LINESIZE volatile.Register32 // 0x40 + DESTINATION volatile.Register32 // 0x44 + PHYSICAL_ADDRESS volatile.Register32 // 0x48 + TRIGGER volatile.Register32 // 0x4C + RELEASE volatile.Register32 // 0x50 + DESTROY volatile.Register32 // 0x54 + STATE volatile.Register32 // 0x58 + DATE volatile.Register32 // 0x5C +} + +// XTS_AES.LINESIZE: XTS-AES line-size register +func (o *XTS_AES_Type) SetLINESIZE(value uint32) { + volatile.StoreUint32(&o.LINESIZE.Reg, volatile.LoadUint32(&o.LINESIZE.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetLINESIZE() uint32 { + return volatile.LoadUint32(&o.LINESIZE.Reg) & 0x1 +} + +// XTS_AES.DESTINATION: XTS-AES destination register +func (o *XTS_AES_Type) SetDESTINATION(value uint32) { + volatile.StoreUint32(&o.DESTINATION.Reg, volatile.LoadUint32(&o.DESTINATION.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetDESTINATION() uint32 { + return volatile.LoadUint32(&o.DESTINATION.Reg) & 0x1 +} + +// XTS_AES.PHYSICAL_ADDRESS: XTS-AES physical address register +func (o *XTS_AES_Type) SetPHYSICAL_ADDRESS(value uint32) { + volatile.StoreUint32(&o.PHYSICAL_ADDRESS.Reg, volatile.LoadUint32(&o.PHYSICAL_ADDRESS.Reg)&^(0x3fffffff)|value) +} +func (o *XTS_AES_Type) GetPHYSICAL_ADDRESS() uint32 { + return volatile.LoadUint32(&o.PHYSICAL_ADDRESS.Reg) & 0x3fffffff +} + +// XTS_AES.TRIGGER: XTS-AES trigger register +func (o *XTS_AES_Type) SetTRIGGER(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetTRIGGER() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} + +// XTS_AES.RELEASE: XTS-AES release register +func (o *XTS_AES_Type) SetRELEASE(value uint32) { + volatile.StoreUint32(&o.RELEASE.Reg, volatile.LoadUint32(&o.RELEASE.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetRELEASE() uint32 { + return volatile.LoadUint32(&o.RELEASE.Reg) & 0x1 +} + +// XTS_AES.DESTROY: XTS-AES destroy register +func (o *XTS_AES_Type) SetDESTROY(value uint32) { + volatile.StoreUint32(&o.DESTROY.Reg, volatile.LoadUint32(&o.DESTROY.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetDESTROY() uint32 { + return volatile.LoadUint32(&o.DESTROY.Reg) & 0x1 +} + +// XTS_AES.STATE: XTS-AES status register +func (o *XTS_AES_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *XTS_AES_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// XTS_AES.DATE: XTS-AES version control register +func (o *XTS_AES_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *XTS_AES_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Constants for APB_CTRL: APB (Advanced Peripheral Bus) Controller +const ( + // SYSCLK_CONF: APB_CTRL_SYSCLK_CONF_REG + // Position of PRE_DIV_CNT field. + APB_CTRL_SYSCLK_CONF_PRE_DIV_CNT_Pos = 0x0 + // Bit mask of PRE_DIV_CNT field. + APB_CTRL_SYSCLK_CONF_PRE_DIV_CNT_Msk = 0x3ff + // Position of CLK_320M_EN field. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN_Pos = 0xa + // Bit mask of CLK_320M_EN field. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN_Msk = 0x400 + // Bit CLK_320M_EN. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN = 0x400 + // Position of CLK_EN field. + APB_CTRL_SYSCLK_CONF_CLK_EN_Pos = 0xb + // Bit mask of CLK_EN field. + APB_CTRL_SYSCLK_CONF_CLK_EN_Msk = 0x800 + // Bit CLK_EN. + APB_CTRL_SYSCLK_CONF_CLK_EN = 0x800 + // Position of RST_TICK_CNT field. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT_Pos = 0xc + // Bit mask of RST_TICK_CNT field. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT_Msk = 0x1000 + // Bit RST_TICK_CNT. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT = 0x1000 + + // TICK_CONF: APB_CTRL_TICK_CONF_REG + // Position of XTAL_TICK_NUM field. + APB_CTRL_TICK_CONF_XTAL_TICK_NUM_Pos = 0x0 + // Bit mask of XTAL_TICK_NUM field. + APB_CTRL_TICK_CONF_XTAL_TICK_NUM_Msk = 0xff + // Position of CK8M_TICK_NUM field. + APB_CTRL_TICK_CONF_CK8M_TICK_NUM_Pos = 0x8 + // Bit mask of CK8M_TICK_NUM field. + APB_CTRL_TICK_CONF_CK8M_TICK_NUM_Msk = 0xff00 + // Position of TICK_ENABLE field. + APB_CTRL_TICK_CONF_TICK_ENABLE_Pos = 0x10 + // Bit mask of TICK_ENABLE field. + APB_CTRL_TICK_CONF_TICK_ENABLE_Msk = 0x10000 + // Bit TICK_ENABLE. + APB_CTRL_TICK_CONF_TICK_ENABLE = 0x10000 + + // CLK_OUT_EN: APB_CTRL_CLK_OUT_EN_REG + // Position of CLK20_OEN field. + APB_CTRL_CLK_OUT_EN_CLK20_OEN_Pos = 0x0 + // Bit mask of CLK20_OEN field. + APB_CTRL_CLK_OUT_EN_CLK20_OEN_Msk = 0x1 + // Bit CLK20_OEN. + APB_CTRL_CLK_OUT_EN_CLK20_OEN = 0x1 + // Position of CLK22_OEN field. + APB_CTRL_CLK_OUT_EN_CLK22_OEN_Pos = 0x1 + // Bit mask of CLK22_OEN field. + APB_CTRL_CLK_OUT_EN_CLK22_OEN_Msk = 0x2 + // Bit CLK22_OEN. + APB_CTRL_CLK_OUT_EN_CLK22_OEN = 0x2 + // Position of CLK44_OEN field. + APB_CTRL_CLK_OUT_EN_CLK44_OEN_Pos = 0x2 + // Bit mask of CLK44_OEN field. + APB_CTRL_CLK_OUT_EN_CLK44_OEN_Msk = 0x4 + // Bit CLK44_OEN. + APB_CTRL_CLK_OUT_EN_CLK44_OEN = 0x4 + // Position of CLK_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_BB_OEN_Pos = 0x3 + // Bit mask of CLK_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_BB_OEN_Msk = 0x8 + // Bit CLK_BB_OEN. + APB_CTRL_CLK_OUT_EN_CLK_BB_OEN = 0x8 + // Position of CLK80_OEN field. + APB_CTRL_CLK_OUT_EN_CLK80_OEN_Pos = 0x4 + // Bit mask of CLK80_OEN field. + APB_CTRL_CLK_OUT_EN_CLK80_OEN_Msk = 0x10 + // Bit CLK80_OEN. + APB_CTRL_CLK_OUT_EN_CLK80_OEN = 0x10 + // Position of CLK160_OEN field. + APB_CTRL_CLK_OUT_EN_CLK160_OEN_Pos = 0x5 + // Bit mask of CLK160_OEN field. + APB_CTRL_CLK_OUT_EN_CLK160_OEN_Msk = 0x20 + // Bit CLK160_OEN. + APB_CTRL_CLK_OUT_EN_CLK160_OEN = 0x20 + // Position of CLK_320M_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_320M_OEN_Pos = 0x6 + // Bit mask of CLK_320M_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_320M_OEN_Msk = 0x40 + // Bit CLK_320M_OEN. + APB_CTRL_CLK_OUT_EN_CLK_320M_OEN = 0x40 + // Position of CLK_ADC_INF_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Pos = 0x7 + // Bit mask of CLK_ADC_INF_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Msk = 0x80 + // Bit CLK_ADC_INF_OEN. + APB_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN = 0x80 + // Position of CLK_DAC_CPU_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN_Pos = 0x8 + // Bit mask of CLK_DAC_CPU_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN_Msk = 0x100 + // Bit CLK_DAC_CPU_OEN. + APB_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN = 0x100 + // Position of CLK40X_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK40X_BB_OEN_Pos = 0x9 + // Bit mask of CLK40X_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK40X_BB_OEN_Msk = 0x200 + // Bit CLK40X_BB_OEN. + APB_CTRL_CLK_OUT_EN_CLK40X_BB_OEN = 0x200 + // Position of CLK_XTAL_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Pos = 0xa + // Bit mask of CLK_XTAL_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Msk = 0x400 + // Bit CLK_XTAL_OEN. + APB_CTRL_CLK_OUT_EN_CLK_XTAL_OEN = 0x400 + + // WIFI_BB_CFG: APB_CTRL_WIFI_BB_CFG_REG + // Position of WIFI_BB_CFG field. + APB_CTRL_WIFI_BB_CFG_WIFI_BB_CFG_Pos = 0x0 + // Bit mask of WIFI_BB_CFG field. + APB_CTRL_WIFI_BB_CFG_WIFI_BB_CFG_Msk = 0xffffffff + + // WIFI_BB_CFG_2: APB_CTRL_WIFI_BB_CFG_2_REG + // Position of WIFI_BB_CFG_2 field. + APB_CTRL_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Pos = 0x0 + // Bit mask of WIFI_BB_CFG_2 field. + APB_CTRL_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Msk = 0xffffffff + + // WIFI_CLK_EN: APB_CTRL_WIFI_CLK_EN_REG + // Position of WIFI_CLK_EN field. + APB_CTRL_WIFI_CLK_EN_WIFI_CLK_EN_Pos = 0x0 + // Bit mask of WIFI_CLK_EN field. + APB_CTRL_WIFI_CLK_EN_WIFI_CLK_EN_Msk = 0xffffffff + + // WIFI_RST_EN: APB_CTRL_WIFI_RST_EN_REG + // Position of WIFI_RST field. + APB_CTRL_WIFI_RST_EN_WIFI_RST_Pos = 0x0 + // Bit mask of WIFI_RST field. + APB_CTRL_WIFI_RST_EN_WIFI_RST_Msk = 0xffffffff + + // HOST_INF_SEL: APB_CTRL_HOST_INF_SEL_REG + // Position of PERI_IO_SWAP field. + APB_CTRL_HOST_INF_SEL_PERI_IO_SWAP_Pos = 0x0 + // Bit mask of PERI_IO_SWAP field. + APB_CTRL_HOST_INF_SEL_PERI_IO_SWAP_Msk = 0xff + + // EXT_MEM_PMS_LOCK: APB_CTRL_EXT_MEM_PMS_LOCK_REG + // Position of EXT_MEM_PMS_LOCK field. + APB_CTRL_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK_Pos = 0x0 + // Bit mask of EXT_MEM_PMS_LOCK field. + APB_CTRL_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK_Msk = 0x1 + // Bit EXT_MEM_PMS_LOCK. + APB_CTRL_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK = 0x1 + + // FLASH_ACE0_ATTR: APB_CTRL_FLASH_ACE0_ATTR_REG + // Position of FLASH_ACE0_ATTR field. + APB_CTRL_FLASH_ACE0_ATTR_FLASH_ACE0_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE0_ATTR field. + APB_CTRL_FLASH_ACE0_ATTR_FLASH_ACE0_ATTR_Msk = 0x3 + + // FLASH_ACE1_ATTR: APB_CTRL_FLASH_ACE1_ATTR_REG + // Position of FLASH_ACE1_ATTR field. + APB_CTRL_FLASH_ACE1_ATTR_FLASH_ACE1_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE1_ATTR field. + APB_CTRL_FLASH_ACE1_ATTR_FLASH_ACE1_ATTR_Msk = 0x3 + + // FLASH_ACE2_ATTR: APB_CTRL_FLASH_ACE2_ATTR_REG + // Position of FLASH_ACE2_ATTR field. + APB_CTRL_FLASH_ACE2_ATTR_FLASH_ACE2_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE2_ATTR field. + APB_CTRL_FLASH_ACE2_ATTR_FLASH_ACE2_ATTR_Msk = 0x3 + + // FLASH_ACE3_ATTR: APB_CTRL_FLASH_ACE3_ATTR_REG + // Position of FLASH_ACE3_ATTR field. + APB_CTRL_FLASH_ACE3_ATTR_FLASH_ACE3_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE3_ATTR field. + APB_CTRL_FLASH_ACE3_ATTR_FLASH_ACE3_ATTR_Msk = 0x3 + + // FLASH_ACE0_ADDR: APB_CTRL_FLASH_ACE0_ADDR_REG + // Position of S field. + APB_CTRL_FLASH_ACE0_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE0_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE1_ADDR: APB_CTRL_FLASH_ACE1_ADDR_REG + // Position of S field. + APB_CTRL_FLASH_ACE1_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE1_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE2_ADDR: APB_CTRL_FLASH_ACE2_ADDR_REG + // Position of S field. + APB_CTRL_FLASH_ACE2_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE2_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE3_ADDR: APB_CTRL_FLASH_ACE3_ADDR_REG + // Position of S field. + APB_CTRL_FLASH_ACE3_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE3_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE0_SIZE: APB_CTRL_FLASH_ACE0_SIZE_REG + // Position of FLASH_ACE0_SIZE field. + APB_CTRL_FLASH_ACE0_SIZE_FLASH_ACE0_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE0_SIZE field. + APB_CTRL_FLASH_ACE0_SIZE_FLASH_ACE0_SIZE_Msk = 0x1fff + + // FLASH_ACE1_SIZE: APB_CTRL_FLASH_ACE1_SIZE_REG + // Position of FLASH_ACE1_SIZE field. + APB_CTRL_FLASH_ACE1_SIZE_FLASH_ACE1_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE1_SIZE field. + APB_CTRL_FLASH_ACE1_SIZE_FLASH_ACE1_SIZE_Msk = 0x1fff + + // FLASH_ACE2_SIZE: APB_CTRL_FLASH_ACE2_SIZE_REG + // Position of FLASH_ACE2_SIZE field. + APB_CTRL_FLASH_ACE2_SIZE_FLASH_ACE2_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE2_SIZE field. + APB_CTRL_FLASH_ACE2_SIZE_FLASH_ACE2_SIZE_Msk = 0x1fff + + // FLASH_ACE3_SIZE: APB_CTRL_FLASH_ACE3_SIZE_REG + // Position of FLASH_ACE3_SIZE field. + APB_CTRL_FLASH_ACE3_SIZE_FLASH_ACE3_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE3_SIZE field. + APB_CTRL_FLASH_ACE3_SIZE_FLASH_ACE3_SIZE_Msk = 0x1fff + + // SPI_MEM_PMS_CTRL: APB_CTRL_SPI_MEM_PMS_CTRL_REG + // Position of SPI_MEM_REJECT_INT field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_INT field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT_Msk = 0x1 + // Bit SPI_MEM_REJECT_INT. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT = 0x1 + // Position of SPI_MEM_REJECT_CLR field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR_Pos = 0x1 + // Bit mask of SPI_MEM_REJECT_CLR field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR_Msk = 0x2 + // Bit SPI_MEM_REJECT_CLR. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR = 0x2 + // Position of SPI_MEM_REJECT_CDE field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE_Pos = 0x2 + // Bit mask of SPI_MEM_REJECT_CDE field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE_Msk = 0x7c + + // SPI_MEM_REJECT_ADDR: APB_CTRL_SPI_MEM_REJECT_ADDR_REG + // Position of SPI_MEM_REJECT_ADDR field. + APB_CTRL_SPI_MEM_REJECT_ADDR_SPI_MEM_REJECT_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_ADDR field. + APB_CTRL_SPI_MEM_REJECT_ADDR_SPI_MEM_REJECT_ADDR_Msk = 0xffffffff + + // SDIO_CTRL: APB_CTRL_SDIO_CTRL_REG + // Position of SDIO_WIN_ACCESS_EN field. + APB_CTRL_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Pos = 0x0 + // Bit mask of SDIO_WIN_ACCESS_EN field. + APB_CTRL_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Msk = 0x1 + // Bit SDIO_WIN_ACCESS_EN. + APB_CTRL_SDIO_CTRL_SDIO_WIN_ACCESS_EN = 0x1 + + // REDCY_SIG0: APB_CTRL_REDCY_SIG0_REG_REG + // Position of REDCY_SIG0 field. + APB_CTRL_REDCY_SIG0_REDCY_SIG0_Pos = 0x0 + // Bit mask of REDCY_SIG0 field. + APB_CTRL_REDCY_SIG0_REDCY_SIG0_Msk = 0x7fffffff + // Position of REDCY_ANDOR field. + APB_CTRL_REDCY_SIG0_REDCY_ANDOR_Pos = 0x1f + // Bit mask of REDCY_ANDOR field. + APB_CTRL_REDCY_SIG0_REDCY_ANDOR_Msk = 0x80000000 + // Bit REDCY_ANDOR. + APB_CTRL_REDCY_SIG0_REDCY_ANDOR = 0x80000000 + + // REDCY_SIG1: APB_CTRL_REDCY_SIG1_REG_REG + // Position of REDCY_SIG1 field. + APB_CTRL_REDCY_SIG1_REDCY_SIG1_Pos = 0x0 + // Bit mask of REDCY_SIG1 field. + APB_CTRL_REDCY_SIG1_REDCY_SIG1_Msk = 0x7fffffff + // Position of REDCY_NANDOR field. + APB_CTRL_REDCY_SIG1_REDCY_NANDOR_Pos = 0x1f + // Bit mask of REDCY_NANDOR field. + APB_CTRL_REDCY_SIG1_REDCY_NANDOR_Msk = 0x80000000 + // Bit REDCY_NANDOR. + APB_CTRL_REDCY_SIG1_REDCY_NANDOR = 0x80000000 + + // FRONT_END_MEM_PD: APB_CTRL_FRONT_END_MEM_PD_REG + // Position of AGC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Pos = 0x0 + // Bit mask of AGC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Msk = 0x1 + // Bit AGC_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU = 0x1 + // Position of AGC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of AGC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Msk = 0x2 + // Bit AGC_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD = 0x2 + // Position of PBUS_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of PBUS_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Msk = 0x4 + // Bit PBUS_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU = 0x4 + // Position of PBUS_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of PBUS_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Msk = 0x8 + // Bit PBUS_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD = 0x8 + // Position of DC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of DC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PU_Msk = 0x10 + // Bit DC_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PU = 0x10 + // Position of DC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PD_Pos = 0x5 + // Bit mask of DC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PD_Msk = 0x20 + // Bit DC_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PD = 0x20 + // Position of FREQ_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PU_Pos = 0x6 + // Bit mask of FREQ_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PU_Msk = 0x40 + // Bit FREQ_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PU = 0x40 + // Position of FREQ_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PD_Pos = 0x7 + // Bit mask of FREQ_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PD_Msk = 0x80 + // Bit FREQ_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PD = 0x80 + + // RETENTION_CTRL: APB_CTRL_RETENTION_CTRL_REG + // Position of RETENTION_LINK_ADDR field. + APB_CTRL_RETENTION_CTRL_RETENTION_LINK_ADDR_Pos = 0x0 + // Bit mask of RETENTION_LINK_ADDR field. + APB_CTRL_RETENTION_CTRL_RETENTION_LINK_ADDR_Msk = 0x7ffffff + // Position of NOBYPASS_CPU_ISO_RST field. + APB_CTRL_RETENTION_CTRL_NOBYPASS_CPU_ISO_RST_Pos = 0x1b + // Bit mask of NOBYPASS_CPU_ISO_RST field. + APB_CTRL_RETENTION_CTRL_NOBYPASS_CPU_ISO_RST_Msk = 0x8000000 + // Bit NOBYPASS_CPU_ISO_RST. + APB_CTRL_RETENTION_CTRL_NOBYPASS_CPU_ISO_RST = 0x8000000 + + // CLKGATE_FORCE_ON: Memory power configuration registers + // Position of ROM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON_Pos = 0x0 + // Bit mask of ROM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON_Msk = 0x7 + // Position of SRAM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON_Pos = 0x3 + // Bit mask of SRAM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON_Msk = 0x78 + + // MEM_POWER_DOWN: Memory power configuration registers + // Position of ROM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_ROM_POWER_DOWN_Pos = 0x0 + // Bit mask of ROM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_ROM_POWER_DOWN_Msk = 0x7 + // Position of SRAM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_SRAM_POWER_DOWN_Pos = 0x3 + // Bit mask of SRAM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_SRAM_POWER_DOWN_Msk = 0x78 + + // MEM_POWER_UP: Memory power configuration registers + // Position of ROM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_ROM_POWER_UP_Pos = 0x0 + // Bit mask of ROM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_ROM_POWER_UP_Msk = 0x7 + // Position of SRAM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_SRAM_POWER_UP_Pos = 0x3 + // Bit mask of SRAM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_SRAM_POWER_UP_Msk = 0x78 + + // RND_DATA: APB_CTRL_RND_DATA_REG + // Position of RND_DATA field. + APB_CTRL_RND_DATA_RND_DATA_Pos = 0x0 + // Bit mask of RND_DATA field. + APB_CTRL_RND_DATA_RND_DATA_Msk = 0xffffffff + + // PERI_BACKUP_CONFIG: APB_CTRL_PERI_BACKUP_CONFIG_REG_REG + // Position of PERI_BACKUP_FLOW_ERR field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_FLOW_ERR_Pos = 0x1 + // Bit mask of PERI_BACKUP_FLOW_ERR field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_FLOW_ERR_Msk = 0x6 + // Position of PERI_BACKUP_BURST_LIMIT field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_BURST_LIMIT_Pos = 0x4 + // Bit mask of PERI_BACKUP_BURST_LIMIT field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_BURST_LIMIT_Msk = 0x1f0 + // Position of PERI_BACKUP_TOUT_THRES field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TOUT_THRES_Pos = 0x9 + // Bit mask of PERI_BACKUP_TOUT_THRES field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TOUT_THRES_Msk = 0x7fe00 + // Position of PERI_BACKUP_SIZE field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_SIZE_Pos = 0x13 + // Bit mask of PERI_BACKUP_SIZE field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_SIZE_Msk = 0x1ff80000 + // Position of PERI_BACKUP_START field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_START_Pos = 0x1d + // Bit mask of PERI_BACKUP_START field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_START_Msk = 0x20000000 + // Bit PERI_BACKUP_START. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_START = 0x20000000 + // Position of PERI_BACKUP_TO_MEM field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM_Pos = 0x1e + // Bit mask of PERI_BACKUP_TO_MEM field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM_Msk = 0x40000000 + // Bit PERI_BACKUP_TO_MEM. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM = 0x40000000 + // Position of PERI_BACKUP_ENA field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_ENA_Pos = 0x1f + // Bit mask of PERI_BACKUP_ENA field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_ENA_Msk = 0x80000000 + // Bit PERI_BACKUP_ENA. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_ENA = 0x80000000 + + // PERI_BACKUP_APB_ADDR: APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG + // Position of BACKUP_APB_START_ADDR field. + APB_CTRL_PERI_BACKUP_APB_ADDR_BACKUP_APB_START_ADDR_Pos = 0x0 + // Bit mask of BACKUP_APB_START_ADDR field. + APB_CTRL_PERI_BACKUP_APB_ADDR_BACKUP_APB_START_ADDR_Msk = 0xffffffff + + // PERI_BACKUP_MEM_ADDR: APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG + // Position of BACKUP_MEM_START_ADDR field. + APB_CTRL_PERI_BACKUP_MEM_ADDR_BACKUP_MEM_START_ADDR_Pos = 0x0 + // Bit mask of BACKUP_MEM_START_ADDR field. + APB_CTRL_PERI_BACKUP_MEM_ADDR_BACKUP_MEM_START_ADDR_Msk = 0xffffffff + + // PERI_BACKUP_INT_RAW: APB_CTRL_PERI_BACKUP_INT_RAW_REG + // Position of PERI_BACKUP_DONE_INT_RAW field. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW_Pos = 0x0 + // Bit mask of PERI_BACKUP_DONE_INT_RAW field. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW_Msk = 0x1 + // Bit PERI_BACKUP_DONE_INT_RAW. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW = 0x1 + // Position of PERI_BACKUP_ERR_INT_RAW field. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW_Pos = 0x1 + // Bit mask of PERI_BACKUP_ERR_INT_RAW field. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW_Msk = 0x2 + // Bit PERI_BACKUP_ERR_INT_RAW. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW = 0x2 + + // PERI_BACKUP_INT_ST: APB_CTRL_PERI_BACKUP_INT_ST_REG + // Position of PERI_BACKUP_DONE_INT_ST field. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST_Pos = 0x0 + // Bit mask of PERI_BACKUP_DONE_INT_ST field. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST_Msk = 0x1 + // Bit PERI_BACKUP_DONE_INT_ST. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST = 0x1 + // Position of PERI_BACKUP_ERR_INT_ST field. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST_Pos = 0x1 + // Bit mask of PERI_BACKUP_ERR_INT_ST field. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST_Msk = 0x2 + // Bit PERI_BACKUP_ERR_INT_ST. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST = 0x2 + + // PERI_BACKUP_INT_ENA: APB_CTRL_PERI_BACKUP_INT_ENA_REG + // Position of PERI_BACKUP_DONE_INT_ENA field. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA_Pos = 0x0 + // Bit mask of PERI_BACKUP_DONE_INT_ENA field. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA_Msk = 0x1 + // Bit PERI_BACKUP_DONE_INT_ENA. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA = 0x1 + // Position of PERI_BACKUP_ERR_INT_ENA field. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA_Pos = 0x1 + // Bit mask of PERI_BACKUP_ERR_INT_ENA field. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA_Msk = 0x2 + // Bit PERI_BACKUP_ERR_INT_ENA. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA = 0x2 + + // PERI_BACKUP_INT_CLR: APB_CTRL_PERI_BACKUP_INT_CLR_REG + // Position of PERI_BACKUP_DONE_INT_CLR field. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR_Pos = 0x0 + // Bit mask of PERI_BACKUP_DONE_INT_CLR field. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR_Msk = 0x1 + // Bit PERI_BACKUP_DONE_INT_CLR. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR = 0x1 + // Position of PERI_BACKUP_ERR_INT_CLR field. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR_Pos = 0x1 + // Bit mask of PERI_BACKUP_ERR_INT_CLR field. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR_Msk = 0x2 + // Bit PERI_BACKUP_ERR_INT_CLR. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR = 0x2 + + // DATE: APB_CTRL_DATE_REG + // Position of DATE field. + APB_CTRL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + APB_CTRL_DATE_DATE_Msk = 0xffffffff +) + +// Constants for APB_SARADC: SAR (Successive Approximation Register) Analog-to-Digital Converter +const ( + // CTRL: register description + // Position of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Pos = 0x0 + // Bit mask of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Msk = 0x1 + // Bit SARADC_START_FORCE. + APB_SARADC_CTRL_SARADC_START_FORCE = 0x1 + // Position of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Pos = 0x1 + // Bit mask of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Msk = 0x2 + // Bit SARADC_START. + APB_SARADC_CTRL_SARADC_START = 0x2 + // Position of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Pos = 0x6 + // Bit mask of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Msk = 0x40 + // Bit SARADC_SAR_CLK_GATED. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED = 0x40 + // Position of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Pos = 0x7 + // Bit mask of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Msk = 0x7f80 + // Position of SARADC_SAR_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR_PATT_LEN_Pos = 0xf + // Bit mask of SARADC_SAR_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR_PATT_LEN_Msk = 0x38000 + // Position of SARADC_SAR_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR_Pos = 0x17 + // Bit mask of SARADC_SAR_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR_Msk = 0x800000 + // Bit SARADC_SAR_PATT_P_CLEAR. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR = 0x800000 + // Position of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Pos = 0x1b + // Bit mask of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Msk = 0x18000000 + // Position of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Pos = 0x1e + // Bit mask of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Msk = 0xc0000000 + + // CTRL2: register description + // Position of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Pos = 0x0 + // Bit mask of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Msk = 0x1 + // Bit SARADC_MEAS_NUM_LIMIT. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT = 0x1 + // Position of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Pos = 0x1 + // Bit mask of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Msk = 0x1fe + // Position of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Pos = 0x9 + // Bit mask of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Msk = 0x200 + // Bit SARADC_SAR1_INV. + APB_SARADC_CTRL2_SARADC_SAR1_INV = 0x200 + // Position of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Pos = 0xa + // Bit mask of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Msk = 0x400 + // Bit SARADC_SAR2_INV. + APB_SARADC_CTRL2_SARADC_SAR2_INV = 0x400 + // Position of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Pos = 0xc + // Bit mask of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Msk = 0xfff000 + // Position of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Pos = 0x18 + // Bit mask of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Msk = 0x1000000 + // Bit SARADC_TIMER_EN. + APB_SARADC_CTRL2_SARADC_TIMER_EN = 0x1000000 + + // FILTER_CTRL1: register description + // Position of FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_FILTER_FACTOR1_Pos = 0x1a + // Bit mask of FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_FILTER_FACTOR1_Msk = 0x1c000000 + // Position of FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_FILTER_FACTOR0_Pos = 0x1d + // Bit mask of FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_FILTER_FACTOR0_Msk = 0xe0000000 + + // FSM_WAIT: register description + // Position of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Pos = 0x0 + // Bit mask of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Msk = 0xff + // Position of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Pos = 0x8 + // Bit mask of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Msk = 0xff00 + // Position of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Pos = 0x10 + // Bit mask of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Msk = 0xff0000 + + // SAR1_STATUS: register description + // Position of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Msk = 0xffffffff + + // SAR2_STATUS: register description + // Position of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Msk = 0xffffffff + + // SAR_PATT_TAB1: register description + // Position of SARADC_SAR_PATT_TAB1 field. + APB_SARADC_SAR_PATT_TAB1_SARADC_SAR_PATT_TAB1_Pos = 0x0 + // Bit mask of SARADC_SAR_PATT_TAB1 field. + APB_SARADC_SAR_PATT_TAB1_SARADC_SAR_PATT_TAB1_Msk = 0xffffff + + // SAR_PATT_TAB2: register description + // Position of SARADC_SAR_PATT_TAB2 field. + APB_SARADC_SAR_PATT_TAB2_SARADC_SAR_PATT_TAB2_Pos = 0x0 + // Bit mask of SARADC_SAR_PATT_TAB2 field. + APB_SARADC_SAR_PATT_TAB2_SARADC_SAR_PATT_TAB2_Msk = 0xffffff + + // ONETIME_SAMPLE: register description + // Position of SARADC_ONETIME_ATTEN field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_ATTEN_Pos = 0x17 + // Bit mask of SARADC_ONETIME_ATTEN field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_ATTEN_Msk = 0x1800000 + // Position of SARADC_ONETIME_CHANNEL field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_CHANNEL_Pos = 0x19 + // Bit mask of SARADC_ONETIME_CHANNEL field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_CHANNEL_Msk = 0x1e000000 + // Position of SARADC_ONETIME_START field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START_Pos = 0x1d + // Bit mask of SARADC_ONETIME_START field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START_Msk = 0x20000000 + // Bit SARADC_ONETIME_START. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START = 0x20000000 + // Position of SARADC2_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE_Pos = 0x1e + // Bit mask of SARADC2_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE_Msk = 0x40000000 + // Bit SARADC2_ONETIME_SAMPLE. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE = 0x40000000 + // Position of SARADC1_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE_Pos = 0x1f + // Bit mask of SARADC1_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE_Msk = 0x80000000 + // Bit SARADC1_ONETIME_SAMPLE. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE = 0x80000000 + + // APB_ADC_ARB_CTRL: register description + // Position of ADC_ARB_APB_FORCE field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_APB_FORCE_Pos = 0x2 + // Bit mask of ADC_ARB_APB_FORCE field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_APB_FORCE_Msk = 0x4 + // Bit ADC_ARB_APB_FORCE. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_APB_FORCE = 0x4 + // Position of ADC_ARB_RTC_FORCE field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Pos = 0x3 + // Bit mask of ADC_ARB_RTC_FORCE field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Msk = 0x8 + // Bit ADC_ARB_RTC_FORCE. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_RTC_FORCE = 0x8 + // Position of ADC_ARB_WIFI_FORCE field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Pos = 0x4 + // Bit mask of ADC_ARB_WIFI_FORCE field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Msk = 0x10 + // Bit ADC_ARB_WIFI_FORCE. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_WIFI_FORCE = 0x10 + // Position of ADC_ARB_GRANT_FORCE field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Pos = 0x5 + // Bit mask of ADC_ARB_GRANT_FORCE field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Msk = 0x20 + // Bit ADC_ARB_GRANT_FORCE. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_GRANT_FORCE = 0x20 + // Position of ADC_ARB_APB_PRIORITY field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Pos = 0x6 + // Bit mask of ADC_ARB_APB_PRIORITY field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Msk = 0xc0 + // Position of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Pos = 0x8 + // Bit mask of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Msk = 0x300 + // Position of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Pos = 0xa + // Bit mask of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Msk = 0xc00 + // Position of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Pos = 0xc + // Bit mask of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Msk = 0x1000 + // Bit ADC_ARB_FIX_PRIORITY. + APB_SARADC_APB_ADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY = 0x1000 + + // FILTER_CTRL0: register description + // Position of FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_FILTER_CHANNEL1_Pos = 0x12 + // Bit mask of FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_FILTER_CHANNEL1_Msk = 0x3c0000 + // Position of FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_FILTER_CHANNEL0_Pos = 0x16 + // Bit mask of FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_FILTER_CHANNEL0_Msk = 0x3c00000 + // Position of FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_FILTER_RESET_Pos = 0x1f + // Bit mask of FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_FILTER_RESET_Msk = 0x80000000 + // Bit FILTER_RESET. + APB_SARADC_FILTER_CTRL0_FILTER_RESET = 0x80000000 + + // SAR1DATA_STATUS: register description + // Position of APB_SARADC1_DATA field. + APB_SARADC_SAR1DATA_STATUS_APB_SARADC1_DATA_Pos = 0x0 + // Bit mask of APB_SARADC1_DATA field. + APB_SARADC_SAR1DATA_STATUS_APB_SARADC1_DATA_Msk = 0x1ffff + + // SAR2DATA_STATUS: register description + // Position of APB_SARADC2_DATA field. + APB_SARADC_SAR2DATA_STATUS_APB_SARADC2_DATA_Pos = 0x0 + // Bit mask of APB_SARADC2_DATA field. + APB_SARADC_SAR2DATA_STATUS_APB_SARADC2_DATA_Msk = 0x1ffff + + // THRES0_CTRL: register description + // Position of THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_THRES0_CHANNEL_Pos = 0x0 + // Bit mask of THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_THRES0_CHANNEL_Msk = 0xf + // Position of THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_THRES0_HIGH_Pos = 0x5 + // Bit mask of THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_THRES0_HIGH_Msk = 0x3ffe0 + // Position of THRES0_LOW field. + APB_SARADC_THRES0_CTRL_THRES0_LOW_Pos = 0x12 + // Bit mask of THRES0_LOW field. + APB_SARADC_THRES0_CTRL_THRES0_LOW_Msk = 0x7ffc0000 + + // THRES1_CTRL: register description + // Position of THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_THRES1_CHANNEL_Pos = 0x0 + // Bit mask of THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_THRES1_CHANNEL_Msk = 0xf + // Position of THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_THRES1_HIGH_Pos = 0x5 + // Bit mask of THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_THRES1_HIGH_Msk = 0x3ffe0 + // Position of THRES1_LOW field. + APB_SARADC_THRES1_CTRL_THRES1_LOW_Pos = 0x12 + // Bit mask of THRES1_LOW field. + APB_SARADC_THRES1_CTRL_THRES1_LOW_Msk = 0x7ffc0000 + + // THRES_CTRL: register description + // Position of THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_THRES_ALL_EN_Pos = 0x1b + // Bit mask of THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_THRES_ALL_EN_Msk = 0x8000000 + // Bit THRES_ALL_EN. + APB_SARADC_THRES_CTRL_THRES_ALL_EN = 0x8000000 + // Position of THRES3_EN field. + APB_SARADC_THRES_CTRL_THRES3_EN_Pos = 0x1c + // Bit mask of THRES3_EN field. + APB_SARADC_THRES_CTRL_THRES3_EN_Msk = 0x10000000 + // Bit THRES3_EN. + APB_SARADC_THRES_CTRL_THRES3_EN = 0x10000000 + // Position of THRES2_EN field. + APB_SARADC_THRES_CTRL_THRES2_EN_Pos = 0x1d + // Bit mask of THRES2_EN field. + APB_SARADC_THRES_CTRL_THRES2_EN_Msk = 0x20000000 + // Bit THRES2_EN. + APB_SARADC_THRES_CTRL_THRES2_EN = 0x20000000 + // Position of THRES1_EN field. + APB_SARADC_THRES_CTRL_THRES1_EN_Pos = 0x1e + // Bit mask of THRES1_EN field. + APB_SARADC_THRES_CTRL_THRES1_EN_Msk = 0x40000000 + // Bit THRES1_EN. + APB_SARADC_THRES_CTRL_THRES1_EN = 0x40000000 + // Position of THRES0_EN field. + APB_SARADC_THRES_CTRL_THRES0_EN_Pos = 0x1f + // Bit mask of THRES0_EN field. + APB_SARADC_THRES_CTRL_THRES0_EN_Msk = 0x80000000 + // Bit THRES0_EN. + APB_SARADC_THRES_CTRL_THRES0_EN = 0x80000000 + + // INT_ENA: register description + // Position of THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_THRES1_LOW_INT_ENA_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_THRES1_LOW_INT_ENA_Msk = 0x4000000 + // Bit THRES1_LOW_INT_ENA. + APB_SARADC_INT_ENA_THRES1_LOW_INT_ENA = 0x4000000 + // Position of THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_THRES0_LOW_INT_ENA_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_THRES0_LOW_INT_ENA_Msk = 0x8000000 + // Bit THRES0_LOW_INT_ENA. + APB_SARADC_INT_ENA_THRES0_LOW_INT_ENA = 0x8000000 + // Position of THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_THRES1_HIGH_INT_ENA_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_THRES1_HIGH_INT_ENA_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_ENA. + APB_SARADC_INT_ENA_THRES1_HIGH_INT_ENA = 0x10000000 + // Position of THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_THRES0_HIGH_INT_ENA_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_THRES0_HIGH_INT_ENA_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_ENA. + APB_SARADC_INT_ENA_THRES0_HIGH_INT_ENA = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA = 0x80000000 + + // INT_RAW: register description + // Position of THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_THRES1_LOW_INT_RAW_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_THRES1_LOW_INT_RAW_Msk = 0x4000000 + // Bit THRES1_LOW_INT_RAW. + APB_SARADC_INT_RAW_THRES1_LOW_INT_RAW = 0x4000000 + // Position of THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_THRES0_LOW_INT_RAW_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_THRES0_LOW_INT_RAW_Msk = 0x8000000 + // Bit THRES0_LOW_INT_RAW. + APB_SARADC_INT_RAW_THRES0_LOW_INT_RAW = 0x8000000 + // Position of THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_THRES1_HIGH_INT_RAW_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_THRES1_HIGH_INT_RAW_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_RAW. + APB_SARADC_INT_RAW_THRES1_HIGH_INT_RAW = 0x10000000 + // Position of THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_THRES0_HIGH_INT_RAW_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_THRES0_HIGH_INT_RAW_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_RAW. + APB_SARADC_INT_RAW_THRES0_HIGH_INT_RAW = 0x20000000 + // Position of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW = 0x40000000 + // Position of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW = 0x80000000 + + // INT_ST: register description + // Position of THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_THRES1_LOW_INT_ST_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_THRES1_LOW_INT_ST_Msk = 0x4000000 + // Bit THRES1_LOW_INT_ST. + APB_SARADC_INT_ST_THRES1_LOW_INT_ST = 0x4000000 + // Position of THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_THRES0_LOW_INT_ST_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_THRES0_LOW_INT_ST_Msk = 0x8000000 + // Bit THRES0_LOW_INT_ST. + APB_SARADC_INT_ST_THRES0_LOW_INT_ST = 0x8000000 + // Position of THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_THRES1_HIGH_INT_ST_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_THRES1_HIGH_INT_ST_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_ST. + APB_SARADC_INT_ST_THRES1_HIGH_INT_ST = 0x10000000 + // Position of THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_THRES0_HIGH_INT_ST_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_THRES0_HIGH_INT_ST_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_ST. + APB_SARADC_INT_ST_THRES0_HIGH_INT_ST = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST = 0x80000000 + + // INT_CLR: register description + // Position of THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_THRES1_LOW_INT_CLR_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_THRES1_LOW_INT_CLR_Msk = 0x4000000 + // Bit THRES1_LOW_INT_CLR. + APB_SARADC_INT_CLR_THRES1_LOW_INT_CLR = 0x4000000 + // Position of THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_THRES0_LOW_INT_CLR_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_THRES0_LOW_INT_CLR_Msk = 0x8000000 + // Bit THRES0_LOW_INT_CLR. + APB_SARADC_INT_CLR_THRES0_LOW_INT_CLR = 0x8000000 + // Position of THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_THRES1_HIGH_INT_CLR_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_THRES1_HIGH_INT_CLR_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_CLR. + APB_SARADC_INT_CLR_THRES1_HIGH_INT_CLR = 0x10000000 + // Position of THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_THRES0_HIGH_INT_CLR_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_THRES0_HIGH_INT_CLR_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_CLR. + APB_SARADC_INT_CLR_THRES0_HIGH_INT_CLR = 0x20000000 + // Position of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR = 0x40000000 + // Position of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR = 0x80000000 + + // DMA_CONF: register description + // Position of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Pos = 0x0 + // Bit mask of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Msk = 0xffff + // Position of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Pos = 0x1e + // Bit mask of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Msk = 0x40000000 + // Bit APB_ADC_RESET_FSM. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM = 0x40000000 + // Position of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Pos = 0x1f + // Bit mask of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Msk = 0x80000000 + // Bit APB_ADC_TRANS. + APB_SARADC_DMA_CONF_APB_ADC_TRANS = 0x80000000 + + // APB_ADC_CLKM_CONF: register description + // Position of REG_CLKM_DIV_NUM field. + APB_SARADC_APB_ADC_CLKM_CONF_REG_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of REG_CLKM_DIV_NUM field. + APB_SARADC_APB_ADC_CLKM_CONF_REG_CLKM_DIV_NUM_Msk = 0xff + // Position of REG_CLKM_DIV_B field. + APB_SARADC_APB_ADC_CLKM_CONF_REG_CLKM_DIV_B_Pos = 0x8 + // Bit mask of REG_CLKM_DIV_B field. + APB_SARADC_APB_ADC_CLKM_CONF_REG_CLKM_DIV_B_Msk = 0x3f00 + // Position of REG_CLKM_DIV_A field. + APB_SARADC_APB_ADC_CLKM_CONF_REG_CLKM_DIV_A_Pos = 0xe + // Bit mask of REG_CLKM_DIV_A field. + APB_SARADC_APB_ADC_CLKM_CONF_REG_CLKM_DIV_A_Msk = 0xfc000 + // Position of CLK_EN field. + APB_SARADC_APB_ADC_CLKM_CONF_CLK_EN_Pos = 0x14 + // Bit mask of CLK_EN field. + APB_SARADC_APB_ADC_CLKM_CONF_CLK_EN_Msk = 0x100000 + // Bit CLK_EN. + APB_SARADC_APB_ADC_CLKM_CONF_CLK_EN = 0x100000 + // Position of REG_CLK_SEL field. + APB_SARADC_APB_ADC_CLKM_CONF_REG_CLK_SEL_Pos = 0x15 + // Bit mask of REG_CLK_SEL field. + APB_SARADC_APB_ADC_CLKM_CONF_REG_CLK_SEL_Msk = 0x600000 + + // APB_TSENS_CTRL: register description + // Position of REG_TSENS_OUT field. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_OUT_Pos = 0x0 + // Bit mask of REG_TSENS_OUT field. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_OUT_Msk = 0xff + // Position of REG_TSENS_IN_INV field. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_IN_INV_Pos = 0xd + // Bit mask of REG_TSENS_IN_INV field. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_IN_INV_Msk = 0x2000 + // Bit REG_TSENS_IN_INV. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_IN_INV = 0x2000 + // Position of REG_TSENS_CLK_DIV field. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_CLK_DIV_Pos = 0xe + // Bit mask of REG_TSENS_CLK_DIV field. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_CLK_DIV_Msk = 0x3fc000 + // Position of REG_TSENS_PU field. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_PU_Pos = 0x16 + // Bit mask of REG_TSENS_PU field. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_PU_Msk = 0x400000 + // Bit REG_TSENS_PU. + APB_SARADC_APB_TSENS_CTRL_REG_TSENS_PU = 0x400000 + + // APB_TSENS_CTRL2: register description + // Position of REG_TSENS_XPD_WAIT field. + APB_SARADC_APB_TSENS_CTRL2_REG_TSENS_XPD_WAIT_Pos = 0x0 + // Bit mask of REG_TSENS_XPD_WAIT field. + APB_SARADC_APB_TSENS_CTRL2_REG_TSENS_XPD_WAIT_Msk = 0xfff + // Position of REG_TSENS_XPD_FORCE field. + APB_SARADC_APB_TSENS_CTRL2_REG_TSENS_XPD_FORCE_Pos = 0xc + // Bit mask of REG_TSENS_XPD_FORCE field. + APB_SARADC_APB_TSENS_CTRL2_REG_TSENS_XPD_FORCE_Msk = 0x3000 + // Position of REG_TSENS_CLK_INV field. + APB_SARADC_APB_TSENS_CTRL2_REG_TSENS_CLK_INV_Pos = 0xe + // Bit mask of REG_TSENS_CLK_INV field. + APB_SARADC_APB_TSENS_CTRL2_REG_TSENS_CLK_INV_Msk = 0x4000 + // Bit REG_TSENS_CLK_INV. + APB_SARADC_APB_TSENS_CTRL2_REG_TSENS_CLK_INV = 0x4000 + // Position of TSENS_CLK_SEL field. + APB_SARADC_APB_TSENS_CTRL2_TSENS_CLK_SEL_Pos = 0xf + // Bit mask of TSENS_CLK_SEL field. + APB_SARADC_APB_TSENS_CTRL2_TSENS_CLK_SEL_Msk = 0x8000 + // Bit TSENS_CLK_SEL. + APB_SARADC_APB_TSENS_CTRL2_TSENS_CLK_SEL = 0x8000 + + // CALI: register description + // Position of CFG field. + APB_SARADC_CALI_CFG_Pos = 0x0 + // Bit mask of CFG field. + APB_SARADC_CALI_CFG_Msk = 0x1ffff + + // APB_CTRL_DATE: register description + // Position of DATE field. + APB_SARADC_APB_CTRL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + APB_SARADC_APB_CTRL_DATE_DATE_Msk = 0xffffffff +) + +// Constants for ASSIST_DEBUG: Debug Assist +const ( + // CORE_0_MONTR_ENA: core0 monitor enable configuration register + // Position of CORE_0_SP_SPILL_MIN_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Pos = 0x0 + // Bit mask of CORE_0_SP_SPILL_MIN_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Msk = 0x1 + // Bit CORE_0_SP_SPILL_MIN_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA = 0x1 + // Position of CORE_0_SP_SPILL_MAX_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Pos = 0x1 + // Bit mask of CORE_0_SP_SPILL_MAX_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Msk = 0x2 + // Bit CORE_0_SP_SPILL_MAX_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA = 0x2 + + // CORE_0_INTR_RAW: core0 monitor interrupt status register + // Position of CORE_0_SP_SPILL_MIN_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Pos = 0x0 + // Bit mask of CORE_0_SP_SPILL_MIN_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Msk = 0x1 + // Bit CORE_0_SP_SPILL_MIN_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW = 0x1 + // Position of CORE_0_SP_SPILL_MAX_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Pos = 0x1 + // Bit mask of CORE_0_SP_SPILL_MAX_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Msk = 0x2 + // Bit CORE_0_SP_SPILL_MAX_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW = 0x2 + + // CORE_0_INTR_ENA: core0 monitor interrupt enable register + // Position of CORE_0_SP_SPILL_MIN_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Pos = 0x0 + // Bit mask of CORE_0_SP_SPILL_MIN_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Msk = 0x1 + // Bit CORE_0_SP_SPILL_MIN_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA = 0x1 + // Position of CORE_0_SP_SPILL_MAX_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Pos = 0x1 + // Bit mask of CORE_0_SP_SPILL_MAX_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Msk = 0x2 + // Bit CORE_0_SP_SPILL_MAX_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA = 0x2 + + // CORE_0_INTR_CLR: core0 monitor interrupt clr register + // Position of CORE_0_SP_SPILL_MIN_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Pos = 0x0 + // Bit mask of CORE_0_SP_SPILL_MIN_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Msk = 0x1 + // Bit CORE_0_SP_SPILL_MIN_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR = 0x1 + // Position of CORE_0_SP_SPILL_MAX_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Pos = 0x1 + // Bit mask of CORE_0_SP_SPILL_MAX_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Msk = 0x2 + // Bit CORE_0_SP_SPILL_MAX_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR = 0x2 + + // CORE_0_SP_MIN: stack min value + // Position of CORE_0_SP_MIN field. + ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Pos = 0x0 + // Bit mask of CORE_0_SP_MIN field. + ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Msk = 0xffffffff + + // CORE_0_SP_MAX: stack max value + // Position of CORE_0_SP_MAX field. + ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Pos = 0x0 + // Bit mask of CORE_0_SP_MAX field. + ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Msk = 0xffffffff + + // CORE_0_SP_PC: stack monitor pc status register + // Position of CORE_0_SP_PC field. + ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Pos = 0x0 + // Bit mask of CORE_0_SP_PC field. + ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Msk = 0xffffffff + + // CORE_0_RCD_EN: record enable configuration register + // Position of CORE_0_RCD_RECORDEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Pos = 0x0 + // Bit mask of CORE_0_RCD_RECORDEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Msk = 0x1 + // Bit CORE_0_RCD_RECORDEN. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN = 0x1 + // Position of CORE_0_RCD_PDEBUGEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Pos = 0x1 + // Bit mask of CORE_0_RCD_PDEBUGEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Msk = 0x2 + // Bit CORE_0_RCD_PDEBUGEN. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN = 0x2 + + // CORE_0_RCD_PDEBUGPC: record status regsiter + // Position of CORE_0_RCD_PDEBUGPC field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGPC field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGSP: record status regsiter + // Position of CORE_0_RCD_PDEBUGSP field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGSP field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Msk = 0xffffffff + + // CORE_0_LASTPC_BEFORE_EXCEPTION: cpu status register + // Position of CORE_0_LASTPC_BEFORE_EXC field. + ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Pos = 0x0 + // Bit mask of CORE_0_LASTPC_BEFORE_EXC field. + ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Msk = 0xffffffff + + // CORE_0_DEBUG_MODE: cpu status register + // Position of CORE_0_DEBUG_MODE field. + ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Pos = 0x0 + // Bit mask of CORE_0_DEBUG_MODE field. + ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Msk = 0x1 + // Bit CORE_0_DEBUG_MODE. + ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODE = 0x1 + // Position of CORE_0_DEBUG_MODULE_ACTIVE field. + ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Pos = 0x1 + // Bit mask of CORE_0_DEBUG_MODULE_ACTIVE field. + ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Msk = 0x2 + // Bit CORE_0_DEBUG_MODULE_ACTIVE. + ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE = 0x2 + + // CLOCK_GATE: clock gate register + // Position of CLK_EN field. + ASSIST_DEBUG_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + ASSIST_DEBUG_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + ASSIST_DEBUG_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: version register + // Position of DATE field. + ASSIST_DEBUG_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + ASSIST_DEBUG_DATE_DATE_Msk = 0xfffffff +) + +// Constants for BB: BB Peripheral +const ( + // BBPD_CTRL: Baseband control register + // Position of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Pos = 0x0 + // Bit mask of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Msk = 0x1 + // Bit DC_EST_FORCE_PD. + BB_BBPD_CTRL_DC_EST_FORCE_PD = 0x1 + // Position of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Pos = 0x1 + // Bit mask of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Msk = 0x2 + // Bit DC_EST_FORCE_PU. + BB_BBPD_CTRL_DC_EST_FORCE_PU = 0x2 + // Position of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Pos = 0x2 + // Bit mask of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Msk = 0x4 + // Bit FFT_FORCE_PD. + BB_BBPD_CTRL_FFT_FORCE_PD = 0x4 + // Position of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Pos = 0x3 + // Bit mask of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Msk = 0x8 + // Bit FFT_FORCE_PU. + BB_BBPD_CTRL_FFT_FORCE_PU = 0x8 +) + +// Constants for DMA: DMA (Direct Memory Access) Controller +const ( + // INT_RAW_CH0: DMA_INT_RAW_CH0_REG. + // Position of IN_DONE field. + DMA_INT_RAW_CH0_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_RAW_CH0_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_RAW_CH0_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_RAW_CH0_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_RAW_CH0_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_RAW_CH0_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_RAW_CH0_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_RAW_CH0_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_RAW_CH0_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_RAW_CH0_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_RAW_CH0_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_RAW_CH0_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_RAW_CH0_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_RAW_CH0_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_RAW_CH0_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_RAW_CH0_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_RAW_CH0_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_RAW_CH0_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_RAW_CH0_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_RAW_CH0_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_RAW_CH0_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_RAW_CH0_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_RAW_CH0_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_RAW_CH0_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_RAW_CH0_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_RAW_CH0_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_RAW_CH0_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_RAW_CH0_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_RAW_CH0_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_RAW_CH0_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_RAW_CH0_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_RAW_CH0_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_RAW_CH0_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_RAW_CH0_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_RAW_CH0_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_RAW_CH0_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_RAW_CH0_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_RAW_CH0_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_RAW_CH0_OUTFIFO_UDF = 0x1000 + + // INT_ST_CH0: DMA_INT_ST_CH0_REG. + // Position of IN_DONE field. + DMA_INT_ST_CH0_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_ST_CH0_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_ST_CH0_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_ST_CH0_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_ST_CH0_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_ST_CH0_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_ST_CH0_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_ST_CH0_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_ST_CH0_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_ST_CH0_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_ST_CH0_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_ST_CH0_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_ST_CH0_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_ST_CH0_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_ST_CH0_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_ST_CH0_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_ST_CH0_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_ST_CH0_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_ST_CH0_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_ST_CH0_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_ST_CH0_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_ST_CH0_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_ST_CH0_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_ST_CH0_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_ST_CH0_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_ST_CH0_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_ST_CH0_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_ST_CH0_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_ST_CH0_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_ST_CH0_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_ST_CH0_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_ST_CH0_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_ST_CH0_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_ST_CH0_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_ST_CH0_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_ST_CH0_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_ST_CH0_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_ST_CH0_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_ST_CH0_OUTFIFO_UDF = 0x1000 + + // INT_ENA_CH0: DMA_INT_ENA_CH0_REG. + // Position of IN_DONE field. + DMA_INT_ENA_CH0_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_ENA_CH0_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_ENA_CH0_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_ENA_CH0_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_ENA_CH0_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_ENA_CH0_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_ENA_CH0_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_ENA_CH0_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_ENA_CH0_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_ENA_CH0_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_ENA_CH0_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_ENA_CH0_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_ENA_CH0_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_ENA_CH0_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_ENA_CH0_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_ENA_CH0_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_ENA_CH0_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_ENA_CH0_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_ENA_CH0_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_ENA_CH0_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_ENA_CH0_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_ENA_CH0_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_ENA_CH0_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_ENA_CH0_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_ENA_CH0_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_ENA_CH0_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_ENA_CH0_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_ENA_CH0_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_ENA_CH0_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_ENA_CH0_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_ENA_CH0_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_ENA_CH0_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_ENA_CH0_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_ENA_CH0_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_ENA_CH0_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_ENA_CH0_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_ENA_CH0_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_ENA_CH0_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_ENA_CH0_OUTFIFO_UDF = 0x1000 + + // INT_CLR_CH0: DMA_INT_CLR_CH0_REG. + // Position of IN_DONE field. + DMA_INT_CLR_CH0_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_CLR_CH0_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_CLR_CH0_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_CLR_CH0_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_CLR_CH0_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_CLR_CH0_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_CLR_CH0_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_CLR_CH0_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_CLR_CH0_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_CLR_CH0_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_CLR_CH0_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_CLR_CH0_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_CLR_CH0_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_CLR_CH0_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_CLR_CH0_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_CLR_CH0_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_CLR_CH0_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_CLR_CH0_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_CLR_CH0_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_CLR_CH0_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_CLR_CH0_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_CLR_CH0_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_CLR_CH0_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_CLR_CH0_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_CLR_CH0_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_CLR_CH0_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_CLR_CH0_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_CLR_CH0_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_CLR_CH0_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_CLR_CH0_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_CLR_CH0_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_CLR_CH0_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_CLR_CH0_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_CLR_CH0_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_CLR_CH0_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_CLR_CH0_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_CLR_CH0_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_CLR_CH0_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_CLR_CH0_OUTFIFO_UDF = 0x1000 + + // AHB_TEST: DMA_AHB_TEST_REG. + // Position of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // MISC_CONF: DMA_MISC_CONF_REG. + // Position of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Pos = 0x0 + // Bit mask of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Msk = 0x1 + // Bit AHBM_RST_INTER. + DMA_MISC_CONF_AHBM_RST_INTER = 0x1 + // Position of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Pos = 0x2 + // Bit mask of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Msk = 0x4 + // Bit ARB_PRI_DIS. + DMA_MISC_CONF_ARB_PRI_DIS = 0x4 + // Position of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Pos = 0x3 + // Bit mask of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Msk = 0x8 + // Bit CLK_EN. + DMA_MISC_CONF_CLK_EN = 0x8 + + // DATE: DMA_DATE_REG. + // Position of DATE field. + DMA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DMA_DATE_DATE_Msk = 0xffffffff + + // IN_CONF0_CH0: DMA_IN_CONF0_CH0_REG. + // Position of IN_RST field. + DMA_IN_CONF0_CH0_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + DMA_IN_CONF0_CH0_IN_RST_Msk = 0x1 + // Bit IN_RST. + DMA_IN_CONF0_CH0_IN_RST = 0x1 + // Position of IN_LOOP_TEST field. + DMA_IN_CONF0_CH0_IN_LOOP_TEST_Pos = 0x1 + // Bit mask of IN_LOOP_TEST field. + DMA_IN_CONF0_CH0_IN_LOOP_TEST_Msk = 0x2 + // Bit IN_LOOP_TEST. + DMA_IN_CONF0_CH0_IN_LOOP_TEST = 0x2 + // Position of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH0_INDSCR_BURST_EN_Pos = 0x2 + // Bit mask of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH0_INDSCR_BURST_EN_Msk = 0x4 + // Bit INDSCR_BURST_EN. + DMA_IN_CONF0_CH0_INDSCR_BURST_EN = 0x4 + // Position of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH0_IN_DATA_BURST_EN_Pos = 0x3 + // Bit mask of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH0_IN_DATA_BURST_EN_Msk = 0x8 + // Bit IN_DATA_BURST_EN. + DMA_IN_CONF0_CH0_IN_DATA_BURST_EN = 0x8 + // Position of MEM_TRANS_EN field. + DMA_IN_CONF0_CH0_MEM_TRANS_EN_Pos = 0x4 + // Bit mask of MEM_TRANS_EN field. + DMA_IN_CONF0_CH0_MEM_TRANS_EN_Msk = 0x10 + // Bit MEM_TRANS_EN. + DMA_IN_CONF0_CH0_MEM_TRANS_EN = 0x10 + + // IN_CONF1_CH0: DMA_IN_CONF1_CH0_REG. + // Position of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH0_IN_CHECK_OWNER_Pos = 0xc + // Bit mask of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH0_IN_CHECK_OWNER_Msk = 0x1000 + // Bit IN_CHECK_OWNER. + DMA_IN_CONF1_CH0_IN_CHECK_OWNER = 0x1000 + + // INFIFO_STATUS_CH0: DMA_INFIFO_STATUS_CH0_REG. + // Position of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH0_INFIFO_FULL_Pos = 0x0 + // Bit mask of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH0_INFIFO_FULL_Msk = 0x1 + // Bit INFIFO_FULL. + DMA_INFIFO_STATUS_CH0_INFIFO_FULL = 0x1 + // Position of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_Pos = 0x1 + // Bit mask of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_Msk = 0x2 + // Bit INFIFO_EMPTY. + DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY = 0x2 + // Position of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH0_INFIFO_CNT_Pos = 0x2 + // Bit mask of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH0_INFIFO_CNT_Msk = 0xfc + // Position of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit IN_REMAIN_UNDER_1B. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B = 0x800000 + // Position of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit IN_REMAIN_UNDER_2B. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B = 0x1000000 + // Position of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit IN_REMAIN_UNDER_3B. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B = 0x2000000 + // Position of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit IN_REMAIN_UNDER_4B. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B = 0x4000000 + // Position of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH0_IN_BUF_HUNGRY_Pos = 0x1b + // Bit mask of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH0_IN_BUF_HUNGRY_Msk = 0x8000000 + // Bit IN_BUF_HUNGRY. + DMA_INFIFO_STATUS_CH0_IN_BUF_HUNGRY = 0x8000000 + + // IN_POP_CH0: DMA_IN_POP_CH0_REG. + // Position of INFIFO_RDATA field. + DMA_IN_POP_CH0_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + DMA_IN_POP_CH0_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + DMA_IN_POP_CH0_INFIFO_POP_Pos = 0xc + // Bit mask of INFIFO_POP field. + DMA_IN_POP_CH0_INFIFO_POP_Msk = 0x1000 + // Bit INFIFO_POP. + DMA_IN_POP_CH0_INFIFO_POP = 0x1000 + + // IN_LINK_CH0: DMA_IN_LINK_CH0_REG. + // Position of INLINK_ADDR field. + DMA_IN_LINK_CH0_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + DMA_IN_LINK_CH0_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + DMA_IN_LINK_CH0_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + DMA_IN_LINK_CH0_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + DMA_IN_LINK_CH0_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + DMA_IN_LINK_CH0_INLINK_STOP_Pos = 0x15 + // Bit mask of INLINK_STOP field. + DMA_IN_LINK_CH0_INLINK_STOP_Msk = 0x200000 + // Bit INLINK_STOP. + DMA_IN_LINK_CH0_INLINK_STOP = 0x200000 + // Position of INLINK_START field. + DMA_IN_LINK_CH0_INLINK_START_Pos = 0x16 + // Bit mask of INLINK_START field. + DMA_IN_LINK_CH0_INLINK_START_Msk = 0x400000 + // Bit INLINK_START. + DMA_IN_LINK_CH0_INLINK_START = 0x400000 + // Position of INLINK_RESTART field. + DMA_IN_LINK_CH0_INLINK_RESTART_Pos = 0x17 + // Bit mask of INLINK_RESTART field. + DMA_IN_LINK_CH0_INLINK_RESTART_Msk = 0x800000 + // Bit INLINK_RESTART. + DMA_IN_LINK_CH0_INLINK_RESTART = 0x800000 + // Position of INLINK_PARK field. + DMA_IN_LINK_CH0_INLINK_PARK_Pos = 0x18 + // Bit mask of INLINK_PARK field. + DMA_IN_LINK_CH0_INLINK_PARK_Msk = 0x1000000 + // Bit INLINK_PARK. + DMA_IN_LINK_CH0_INLINK_PARK = 0x1000000 + + // IN_STATE_CH0: DMA_IN_STATE_CH0_REG. + // Position of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH0_INLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH0_INLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of IN_DSCR_STATE field. + DMA_IN_STATE_CH0_IN_DSCR_STATE_Pos = 0x12 + // Bit mask of IN_DSCR_STATE field. + DMA_IN_STATE_CH0_IN_DSCR_STATE_Msk = 0xc0000 + // Position of IN_STATE field. + DMA_IN_STATE_CH0_IN_STATE_Pos = 0x14 + // Bit mask of IN_STATE field. + DMA_IN_STATE_CH0_IN_STATE_Msk = 0x700000 + + // IN_SUC_EOF_DES_ADDR_CH0: DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. + // Position of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH0_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH0_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_ERR_EOF_DES_ADDR_CH0: DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. + // Position of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH0_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH0_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_DSCR_CH0: DMA_IN_DSCR_CH0_REG. + // Position of INLINK_DSCR field. + DMA_IN_DSCR_CH0_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + DMA_IN_DSCR_CH0_INLINK_DSCR_Msk = 0xffffffff + + // IN_DSCR_BF0_CH0: DMA_IN_DSCR_BF0_CH0_REG. + // Position of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH0_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH0_INLINK_DSCR_BF0_Msk = 0xffffffff + + // IN_DSCR_BF1_CH0: DMA_IN_DSCR_BF1_CH0_REG. + // Position of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH0_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH0_INLINK_DSCR_BF1_Msk = 0xffffffff + + // IN_PRI_CH0: DMA_IN_PRI_CH0_REG. + // Position of RX_PRI field. + DMA_IN_PRI_CH0_RX_PRI_Pos = 0x0 + // Bit mask of RX_PRI field. + DMA_IN_PRI_CH0_RX_PRI_Msk = 0xf + + // IN_PERI_SEL_CH0: DMA_IN_PERI_SEL_CH0_REG. + // Position of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH0_PERI_IN_SEL_Pos = 0x0 + // Bit mask of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH0_PERI_IN_SEL_Msk = 0x3f + + // OUT_CONF0_CH0: DMA_OUT_CONF0_CH0_REG. + // Position of OUT_RST field. + DMA_OUT_CONF0_CH0_OUT_RST_Pos = 0x0 + // Bit mask of OUT_RST field. + DMA_OUT_CONF0_CH0_OUT_RST_Msk = 0x1 + // Bit OUT_RST. + DMA_OUT_CONF0_CH0_OUT_RST = 0x1 + // Position of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_Pos = 0x1 + // Bit mask of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_Msk = 0x2 + // Bit OUT_LOOP_TEST. + DMA_OUT_CONF0_CH0_OUT_LOOP_TEST = 0x2 + // Position of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_Pos = 0x2 + // Bit mask of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_Msk = 0x4 + // Bit OUT_AUTO_WRBACK. + DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK = 0x4 + // Position of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH0_OUT_EOF_MODE_Pos = 0x3 + // Bit mask of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH0_OUT_EOF_MODE_Msk = 0x8 + // Bit OUT_EOF_MODE. + DMA_OUT_CONF0_CH0_OUT_EOF_MODE = 0x8 + // Position of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_Pos = 0x4 + // Bit mask of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_Msk = 0x10 + // Bit OUTDSCR_BURST_EN. + DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN = 0x10 + // Position of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_Pos = 0x5 + // Bit mask of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_Msk = 0x20 + // Bit OUT_DATA_BURST_EN. + DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN = 0x20 + + // OUT_CONF1_CH0: DMA_OUT_CONF1_CH0_REG. + // Position of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH0_OUT_CHECK_OWNER_Pos = 0xc + // Bit mask of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH0_OUT_CHECK_OWNER_Msk = 0x1000 + // Bit OUT_CHECK_OWNER. + DMA_OUT_CONF1_CH0_OUT_CHECK_OWNER = 0x1000 + + // OUTFIFO_STATUS_CH0: DMA_OUTFIFO_STATUS_CH0_REG. + // Position of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_Pos = 0x0 + // Bit mask of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_Msk = 0x1 + // Bit OUTFIFO_FULL. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL = 0x1 + // Position of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_Pos = 0x1 + // Bit mask of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_Msk = 0x2 + // Bit OUTFIFO_EMPTY. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY = 0x2 + // Position of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_Pos = 0x2 + // Bit mask of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_Msk = 0xfc + // Position of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit OUT_REMAIN_UNDER_1B. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B = 0x800000 + // Position of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit OUT_REMAIN_UNDER_2B. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B = 0x1000000 + // Position of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit OUT_REMAIN_UNDER_3B. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B = 0x2000000 + // Position of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit OUT_REMAIN_UNDER_4B. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B = 0x4000000 + + // OUT_PUSH_CH0: DMA_OUT_PUSH_CH0_REG. + // Position of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH0_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH0_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH0_OUTFIFO_PUSH_Pos = 0x9 + // Bit mask of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH0_OUTFIFO_PUSH_Msk = 0x200 + // Bit OUTFIFO_PUSH. + DMA_OUT_PUSH_CH0_OUTFIFO_PUSH = 0x200 + + // OUT_LINK_CH0: DMA_OUT_LINK_CH0_REG. + // Position of OUTLINK_ADDR field. + DMA_OUT_LINK_CH0_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + DMA_OUT_LINK_CH0_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + DMA_OUT_LINK_CH0_OUTLINK_STOP_Pos = 0x14 + // Bit mask of OUTLINK_STOP field. + DMA_OUT_LINK_CH0_OUTLINK_STOP_Msk = 0x100000 + // Bit OUTLINK_STOP. + DMA_OUT_LINK_CH0_OUTLINK_STOP = 0x100000 + // Position of OUTLINK_START field. + DMA_OUT_LINK_CH0_OUTLINK_START_Pos = 0x15 + // Bit mask of OUTLINK_START field. + DMA_OUT_LINK_CH0_OUTLINK_START_Msk = 0x200000 + // Bit OUTLINK_START. + DMA_OUT_LINK_CH0_OUTLINK_START = 0x200000 + // Position of OUTLINK_RESTART field. + DMA_OUT_LINK_CH0_OUTLINK_RESTART_Pos = 0x16 + // Bit mask of OUTLINK_RESTART field. + DMA_OUT_LINK_CH0_OUTLINK_RESTART_Msk = 0x400000 + // Bit OUTLINK_RESTART. + DMA_OUT_LINK_CH0_OUTLINK_RESTART = 0x400000 + // Position of OUTLINK_PARK field. + DMA_OUT_LINK_CH0_OUTLINK_PARK_Pos = 0x17 + // Bit mask of OUTLINK_PARK field. + DMA_OUT_LINK_CH0_OUTLINK_PARK_Msk = 0x800000 + // Bit OUTLINK_PARK. + DMA_OUT_LINK_CH0_OUTLINK_PARK = 0x800000 + + // OUT_STATE_CH0: DMA_OUT_STATE_CH0_REG. + // Position of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH0_OUTLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH0_OUTLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH0_OUT_DSCR_STATE_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH0_OUT_DSCR_STATE_Msk = 0xc0000 + // Position of OUT_STATE field. + DMA_OUT_STATE_CH0_OUT_STATE_Pos = 0x14 + // Bit mask of OUT_STATE field. + DMA_OUT_STATE_CH0_OUT_STATE_Msk = 0x700000 + + // OUT_EOF_DES_ADDR_CH0: DMA_OUT_EOF_DES_ADDR_CH0_REG. + // Position of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH0_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH0_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR_CH0: DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. + // Position of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH0_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH0_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // OUT_DSCR_CH0: DMA_OUT_DSCR_CH0_REG. + // Position of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH0_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH0_OUTLINK_DSCR_Msk = 0xffffffff + + // OUT_DSCR_BF0_CH0: DMA_OUT_DSCR_BF0_CH0_REG. + // Position of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH0_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH0_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUT_DSCR_BF1_CH0: DMA_OUT_DSCR_BF1_CH0_REG. + // Position of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH0_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH0_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // OUT_PRI_CH0: DMA_OUT_PRI_CH0_REG. + // Position of TX_PRI field. + DMA_OUT_PRI_CH0_TX_PRI_Pos = 0x0 + // Bit mask of TX_PRI field. + DMA_OUT_PRI_CH0_TX_PRI_Msk = 0xf + + // OUT_PERI_SEL_CH0: DMA_OUT_PERI_SEL_CH0_REG. + // Position of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH0_PERI_OUT_SEL_Pos = 0x0 + // Bit mask of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH0_PERI_OUT_SEL_Msk = 0x3f +) + +// Constants for ECC: ECC (ECC Hardware Accelerator) +const ( + // MULT_INT_RAW: I2S interrupt raw register, valid in level. + // Position of CALC_DONE_INT_RAW field. + ECC_MULT_INT_RAW_CALC_DONE_INT_RAW_Pos = 0x0 + // Bit mask of CALC_DONE_INT_RAW field. + ECC_MULT_INT_RAW_CALC_DONE_INT_RAW_Msk = 0x1 + // Bit CALC_DONE_INT_RAW. + ECC_MULT_INT_RAW_CALC_DONE_INT_RAW = 0x1 + + // MULT_INT_ST: I2S interrupt status register. + // Position of CALC_DONE_INT_ST field. + ECC_MULT_INT_ST_CALC_DONE_INT_ST_Pos = 0x0 + // Bit mask of CALC_DONE_INT_ST field. + ECC_MULT_INT_ST_CALC_DONE_INT_ST_Msk = 0x1 + // Bit CALC_DONE_INT_ST. + ECC_MULT_INT_ST_CALC_DONE_INT_ST = 0x1 + + // MULT_INT_ENA: I2S interrupt enable register. + // Position of CALC_DONE_INT_ENA field. + ECC_MULT_INT_ENA_CALC_DONE_INT_ENA_Pos = 0x0 + // Bit mask of CALC_DONE_INT_ENA field. + ECC_MULT_INT_ENA_CALC_DONE_INT_ENA_Msk = 0x1 + // Bit CALC_DONE_INT_ENA. + ECC_MULT_INT_ENA_CALC_DONE_INT_ENA = 0x1 + + // MULT_INT_CLR: I2S interrupt clear register. + // Position of CALC_DONE_INT_CLR field. + ECC_MULT_INT_CLR_CALC_DONE_INT_CLR_Pos = 0x0 + // Bit mask of CALC_DONE_INT_CLR field. + ECC_MULT_INT_CLR_CALC_DONE_INT_CLR_Msk = 0x1 + // Bit CALC_DONE_INT_CLR. + ECC_MULT_INT_CLR_CALC_DONE_INT_CLR = 0x1 + + // MULT_CONF: I2S RX configure register + // Position of START field. + ECC_MULT_CONF_START_Pos = 0x0 + // Bit mask of START field. + ECC_MULT_CONF_START_Msk = 0x1 + // Bit START. + ECC_MULT_CONF_START = 0x1 + // Position of RESET field. + ECC_MULT_CONF_RESET_Pos = 0x1 + // Bit mask of RESET field. + ECC_MULT_CONF_RESET_Msk = 0x2 + // Bit RESET. + ECC_MULT_CONF_RESET = 0x2 + // Position of KEY_LENGTH field. + ECC_MULT_CONF_KEY_LENGTH_Pos = 0x2 + // Bit mask of KEY_LENGTH field. + ECC_MULT_CONF_KEY_LENGTH_Msk = 0x4 + // Bit KEY_LENGTH. + ECC_MULT_CONF_KEY_LENGTH = 0x4 + // Position of SECURITY_MODE field. + ECC_MULT_CONF_SECURITY_MODE_Pos = 0x3 + // Bit mask of SECURITY_MODE field. + ECC_MULT_CONF_SECURITY_MODE_Msk = 0x8 + // Bit SECURITY_MODE. + ECC_MULT_CONF_SECURITY_MODE = 0x8 + // Position of CLK_EN field. + ECC_MULT_CONF_CLK_EN_Pos = 0x4 + // Bit mask of CLK_EN field. + ECC_MULT_CONF_CLK_EN_Msk = 0x10 + // Bit CLK_EN. + ECC_MULT_CONF_CLK_EN = 0x10 + // Position of WORK_MODE field. + ECC_MULT_CONF_WORK_MODE_Pos = 0x5 + // Bit mask of WORK_MODE field. + ECC_MULT_CONF_WORK_MODE_Msk = 0xe0 + // Position of VERIFICATION_RESULT field. + ECC_MULT_CONF_VERIFICATION_RESULT_Pos = 0x8 + // Bit mask of VERIFICATION_RESULT field. + ECC_MULT_CONF_VERIFICATION_RESULT_Msk = 0x100 + // Bit VERIFICATION_RESULT. + ECC_MULT_CONF_VERIFICATION_RESULT = 0x100 + + // MULT_DATE: Version control register + // Position of DATE field. + ECC_MULT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + ECC_MULT_DATE_DATE_Msk = 0xfffffff +) + +// Constants for EFUSE: eFuse Controller +const ( + // PGM_DATA0: Register 0 that stores data to be programmed. + // Position of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Pos = 0x0 + // Bit mask of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Msk = 0xffffffff + + // PGM_DATA1: Register 1 that stores data to be programmed. + // Position of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Pos = 0x0 + // Bit mask of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Msk = 0xffffffff + + // PGM_DATA2: Register 2 that stores data to be programmed. + // Position of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Pos = 0x0 + // Bit mask of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Msk = 0xffffffff + + // PGM_DATA3: Register 3 that stores data to be programmed. + // Position of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Pos = 0x0 + // Bit mask of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Msk = 0xffffffff + + // PGM_DATA4: Register 4 that stores data to be programmed. + // Position of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Pos = 0x0 + // Bit mask of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Msk = 0xffffffff + + // PGM_DATA5: Register 5 that stores data to be programmed. + // Position of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Pos = 0x0 + // Bit mask of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Msk = 0xffffffff + + // PGM_DATA6: Register 6 that stores data to be programmed. + // Position of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Pos = 0x0 + // Bit mask of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Msk = 0xffffffff + + // PGM_DATA7: Register 7 that stores data to be programmed. + // Position of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Pos = 0x0 + // Bit mask of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Msk = 0xffffffff + + // PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Pos = 0x0 + // Bit mask of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Msk = 0xffffffff + + // PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Pos = 0x0 + // Bit mask of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Msk = 0xffffffff + + // PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Pos = 0x0 + // Bit mask of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Msk = 0xffffffff + + // RD_WR_DIS: BLOCK0 data register 0. + // Position of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Pos = 0x0 + // Bit mask of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Msk = 0xff + + // RD_REPEAT_DATA0: BLOCK0 data register 1. + // Position of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Pos = 0x0 + // Bit mask of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Msk = 0x3 + // Position of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA0_WDT_DELAY_SEL_Pos = 0x2 + // Bit mask of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA0_WDT_DELAY_SEL_Msk = 0xc + // Position of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Pos = 0x4 + // Bit mask of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Msk = 0x10 + // Bit DIS_PAD_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG = 0x10 + // Position of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Pos = 0x5 + // Bit mask of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Msk = 0x20 + // Bit DIS_DOWNLOAD_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE = 0x20 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x6 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x40 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT = 0x40 + // Position of SPI_BOOT_ENCRYPT_DECRYPT_CNT field. + EFUSE_RD_REPEAT_DATA0_SPI_BOOT_ENCRYPT_DECRYPT_CNT_Pos = 0x7 + // Bit mask of SPI_BOOT_ENCRYPT_DECRYPT_CNT field. + EFUSE_RD_REPEAT_DATA0_SPI_BOOT_ENCRYPT_DECRYPT_CNT_Msk = 0x380 + // Position of XTS_KEY_LENGTH_256 field. + EFUSE_RD_REPEAT_DATA0_XTS_KEY_LENGTH_256_Pos = 0xa + // Bit mask of XTS_KEY_LENGTH_256 field. + EFUSE_RD_REPEAT_DATA0_XTS_KEY_LENGTH_256_Msk = 0x400 + // Bit XTS_KEY_LENGTH_256. + EFUSE_RD_REPEAT_DATA0_XTS_KEY_LENGTH_256 = 0x400 + // Position of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA0_UART_PRINT_CONTROL_Pos = 0xb + // Bit mask of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA0_UART_PRINT_CONTROL_Msk = 0x1800 + // Position of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA0_FORCE_SEND_RESUME_Pos = 0xd + // Bit mask of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA0_FORCE_SEND_RESUME_Msk = 0x2000 + // Bit FORCE_SEND_RESUME. + EFUSE_RD_REPEAT_DATA0_FORCE_SEND_RESUME = 0x2000 + // Position of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MODE_Pos = 0xe + // Bit mask of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MODE_Msk = 0x4000 + // Bit DIS_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MODE = 0x4000 + // Position of DIS_DIRECT_BOOT field. + EFUSE_RD_REPEAT_DATA0_DIS_DIRECT_BOOT_Pos = 0xf + // Bit mask of DIS_DIRECT_BOOT field. + EFUSE_RD_REPEAT_DATA0_DIS_DIRECT_BOOT_Msk = 0x8000 + // Bit DIS_DIRECT_BOOT. + EFUSE_RD_REPEAT_DATA0_DIS_DIRECT_BOOT = 0x8000 + // Position of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_ENABLE_SECURITY_DOWNLOAD_Pos = 0x10 + // Bit mask of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_ENABLE_SECURITY_DOWNLOAD_Msk = 0x10000 + // Bit ENABLE_SECURITY_DOWNLOAD. + EFUSE_RD_REPEAT_DATA0_ENABLE_SECURITY_DOWNLOAD = 0x10000 + // Position of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA0_FLASH_TPUW_Pos = 0x11 + // Bit mask of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA0_FLASH_TPUW_Msk = 0x1e0000 + // Position of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA0_SECURE_BOOT_EN_Pos = 0x15 + // Bit mask of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA0_SECURE_BOOT_EN_Msk = 0x200000 + // Bit SECURE_BOOT_EN. + EFUSE_RD_REPEAT_DATA0_SECURE_BOOT_EN = 0x200000 + // Position of RPT4_RESERVED field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED_Pos = 0x16 + // Bit mask of RPT4_RESERVED field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED_Msk = 0xffc00000 + + // RD_BLK1_DATA0: BLOCK1 data register 0. + // Position of SYSTEM_DATA0 field. + EFUSE_RD_BLK1_DATA0_SYSTEM_DATA0_Pos = 0x0 + // Bit mask of SYSTEM_DATA0 field. + EFUSE_RD_BLK1_DATA0_SYSTEM_DATA0_Msk = 0xffffffff + + // RD_BLK1_DATA1: BLOCK1 data register 1. + // Position of SYSTEM_DATA1 field. + EFUSE_RD_BLK1_DATA1_SYSTEM_DATA1_Pos = 0x0 + // Bit mask of SYSTEM_DATA1 field. + EFUSE_RD_BLK1_DATA1_SYSTEM_DATA1_Msk = 0xffffffff + + // RD_BLK1_DATA2: BLOCK1 data register 2. + // Position of SYSTEM_DATA2 field. + EFUSE_RD_BLK1_DATA2_SYSTEM_DATA2_Pos = 0x0 + // Bit mask of SYSTEM_DATA2 field. + EFUSE_RD_BLK1_DATA2_SYSTEM_DATA2_Msk = 0xffffff + + // RD_BLK2_DATA0: Register 0 of BLOCK2. + // Position of BLK2_DATA0 field. + EFUSE_RD_BLK2_DATA0_BLK2_DATA0_Pos = 0x0 + // Bit mask of BLK2_DATA0 field. + EFUSE_RD_BLK2_DATA0_BLK2_DATA0_Msk = 0xffffffff + + // RD_BLK2_DATA1: Register 1 of BLOCK2. + // Position of MAC_ID_HIGH field. + EFUSE_RD_BLK2_DATA1_MAC_ID_HIGH_Pos = 0x0 + // Bit mask of MAC_ID_HIGH field. + EFUSE_RD_BLK2_DATA1_MAC_ID_HIGH_Msk = 0xffff + // Position of WAFER_VERSION field. + EFUSE_RD_BLK2_DATA1_WAFER_VERSION_Pos = 0x10 + // Bit mask of WAFER_VERSION field. + EFUSE_RD_BLK2_DATA1_WAFER_VERSION_Msk = 0x70000 + // Position of PKG_VERSION field. + EFUSE_RD_BLK2_DATA1_PKG_VERSION_Pos = 0x13 + // Bit mask of PKG_VERSION field. + EFUSE_RD_BLK2_DATA1_PKG_VERSION_Msk = 0x380000 + // Position of BLK2_EFUSE_VERSION field. + EFUSE_RD_BLK2_DATA1_BLK2_EFUSE_VERSION_Pos = 0x16 + // Bit mask of BLK2_EFUSE_VERSION field. + EFUSE_RD_BLK2_DATA1_BLK2_EFUSE_VERSION_Msk = 0x1c00000 + // Position of RF_REF_I_BIAS_CONFIG field. + EFUSE_RD_BLK2_DATA1_RF_REF_I_BIAS_CONFIG_Pos = 0x19 + // Bit mask of RF_REF_I_BIAS_CONFIG field. + EFUSE_RD_BLK2_DATA1_RF_REF_I_BIAS_CONFIG_Msk = 0x1e000000 + // Position of LDO_VOL_BIAS_CONFIG_LOW field. + EFUSE_RD_BLK2_DATA1_LDO_VOL_BIAS_CONFIG_LOW_Pos = 0x1d + // Bit mask of LDO_VOL_BIAS_CONFIG_LOW field. + EFUSE_RD_BLK2_DATA1_LDO_VOL_BIAS_CONFIG_LOW_Msk = 0xe0000000 + + // RD_BLK2_DATA2: Register 2 of BLOCK2. + // Position of LDO_VOL_BIAS_CONFIG_HIGH field. + EFUSE_RD_BLK2_DATA2_LDO_VOL_BIAS_CONFIG_HIGH_Pos = 0x0 + // Bit mask of LDO_VOL_BIAS_CONFIG_HIGH field. + EFUSE_RD_BLK2_DATA2_LDO_VOL_BIAS_CONFIG_HIGH_Msk = 0x7ffffff + // Position of PVT_LOW field. + EFUSE_RD_BLK2_DATA2_PVT_LOW_Pos = 0x1b + // Bit mask of PVT_LOW field. + EFUSE_RD_BLK2_DATA2_PVT_LOW_Msk = 0xf8000000 + + // RD_BLK2_DATA3: Register 3 of BLOCK2. + // Position of PVT_HIGH field. + EFUSE_RD_BLK2_DATA3_PVT_HIGH_Pos = 0x0 + // Bit mask of PVT_HIGH field. + EFUSE_RD_BLK2_DATA3_PVT_HIGH_Msk = 0x3ff + // Position of ADC_CALIBRATION_0 field. + EFUSE_RD_BLK2_DATA3_ADC_CALIBRATION_0_Pos = 0xa + // Bit mask of ADC_CALIBRATION_0 field. + EFUSE_RD_BLK2_DATA3_ADC_CALIBRATION_0_Msk = 0xfffffc00 + + // RD_BLK2_DATA4: Register 4 of BLOCK2. + // Position of ADC_CALIBRATION_1 field. + EFUSE_RD_BLK2_DATA4_ADC_CALIBRATION_1_Pos = 0x0 + // Bit mask of ADC_CALIBRATION_1 field. + EFUSE_RD_BLK2_DATA4_ADC_CALIBRATION_1_Msk = 0xffffffff + + // RD_BLK2_DATA5: Register 5 of BLOCK2. + // Position of ADC_CALIBRATION_2 field. + EFUSE_RD_BLK2_DATA5_ADC_CALIBRATION_2_Pos = 0x0 + // Bit mask of ADC_CALIBRATION_2 field. + EFUSE_RD_BLK2_DATA5_ADC_CALIBRATION_2_Msk = 0xffffffff + + // RD_BLK2_DATA6: Register 6 of BLOCK2. + // Position of ADC_CALIBRATION_3 field. + EFUSE_RD_BLK2_DATA6_ADC_CALIBRATION_3_Pos = 0x0 + // Bit mask of ADC_CALIBRATION_3 field. + EFUSE_RD_BLK2_DATA6_ADC_CALIBRATION_3_Msk = 0x7ff + // Position of BLK2_RESERVED_DATA_0 field. + EFUSE_RD_BLK2_DATA6_BLK2_RESERVED_DATA_0_Pos = 0xb + // Bit mask of BLK2_RESERVED_DATA_0 field. + EFUSE_RD_BLK2_DATA6_BLK2_RESERVED_DATA_0_Msk = 0xfffff800 + + // RD_BLK2_DATA7: Register 7 of BLOCK2. + // Position of BLK2_RESERVED_DATA_1 field. + EFUSE_RD_BLK2_DATA7_BLK2_RESERVED_DATA_1_Pos = 0x0 + // Bit mask of BLK2_RESERVED_DATA_1 field. + EFUSE_RD_BLK2_DATA7_BLK2_RESERVED_DATA_1_Msk = 0xffffffff + + // RD_BLK3_DATA0: Register 0 of BLOCK3. + // Position of BLK3_DATA0 field. + EFUSE_RD_BLK3_DATA0_BLK3_DATA0_Pos = 0x0 + // Bit mask of BLK3_DATA0 field. + EFUSE_RD_BLK3_DATA0_BLK3_DATA0_Msk = 0xffffffff + + // RD_BLK3_DATA1: Register 1 of BLOCK3. + // Position of BLK3_DATA1 field. + EFUSE_RD_BLK3_DATA1_BLK3_DATA1_Pos = 0x0 + // Bit mask of BLK3_DATA1 field. + EFUSE_RD_BLK3_DATA1_BLK3_DATA1_Msk = 0xffffffff + + // RD_BLK3_DATA2: Register 2 of BLOCK3. + // Position of BLK3_DATA2 field. + EFUSE_RD_BLK3_DATA2_BLK3_DATA2_Pos = 0x0 + // Bit mask of BLK3_DATA2 field. + EFUSE_RD_BLK3_DATA2_BLK3_DATA2_Msk = 0xffffffff + + // RD_BLK3_DATA3: Register 3 of BLOCK3. + // Position of BLK3_DATA3 field. + EFUSE_RD_BLK3_DATA3_BLK3_DATA3_Pos = 0x0 + // Bit mask of BLK3_DATA3 field. + EFUSE_RD_BLK3_DATA3_BLK3_DATA3_Msk = 0xffffffff + + // RD_BLK3_DATA4: Register 4 of BLOCK3. + // Position of BLK3_DATA4 field. + EFUSE_RD_BLK3_DATA4_BLK3_DATA4_Pos = 0x0 + // Bit mask of BLK3_DATA4 field. + EFUSE_RD_BLK3_DATA4_BLK3_DATA4_Msk = 0xffffffff + + // RD_BLK3_DATA5: Register 5 of BLOCK3. + // Position of BLK3_DATA5 field. + EFUSE_RD_BLK3_DATA5_BLK3_DATA5_Pos = 0x0 + // Bit mask of BLK3_DATA5 field. + EFUSE_RD_BLK3_DATA5_BLK3_DATA5_Msk = 0xffffffff + + // RD_BLK3_DATA6: Register 6 of BLOCK3. + // Position of BLK3_DATA6 field. + EFUSE_RD_BLK3_DATA6_BLK3_DATA6_Pos = 0x0 + // Bit mask of BLK3_DATA6 field. + EFUSE_RD_BLK3_DATA6_BLK3_DATA6_Msk = 0xffffffff + + // RD_BLK3_DATA7: Register 7 of BLOCK3. + // Position of BLK3_DATA7 field. + EFUSE_RD_BLK3_DATA7_BLK3_DATA7_Pos = 0x0 + // Bit mask of BLK3_DATA7 field. + EFUSE_RD_BLK3_DATA7_BLK3_DATA7_Msk = 0xffffffff + + // RD_REPEAT_ERR: Programming error record register 0 of BLOCK0. + // Position of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR_RD_DIS_ERR_Pos = 0x0 + // Bit mask of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR_RD_DIS_ERR_Msk = 0x3 + // Position of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR_WDT_DELAY_SEL_ERR_Pos = 0x2 + // Bit mask of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR_WDT_DELAY_SEL_ERR_Msk = 0xc + // Position of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_PAD_JTAG_ERR_Pos = 0x4 + // Bit mask of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_PAD_JTAG_ERR_Msk = 0x10 + // Bit DIS_PAD_JTAG_ERR. + EFUSE_RD_REPEAT_ERR_DIS_PAD_JTAG_ERR = 0x10 + // Position of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_DOWNLOAD_ICACHE_ERR_Pos = 0x5 + // Bit mask of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_DOWNLOAD_ICACHE_ERR_Msk = 0x20 + // Bit DIS_DOWNLOAD_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR_DIS_DOWNLOAD_ICACHE_ERR = 0x20 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Pos = 0x6 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Msk = 0x40 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR. + EFUSE_RD_REPEAT_ERR_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR = 0x40 + // Position of SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_Pos = 0x7 + // Bit mask of SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_Msk = 0x380 + // Position of XTS_KEY_LENGTH_256_ERR field. + EFUSE_RD_REPEAT_ERR_XTS_KEY_LENGTH_256_ERR_Pos = 0xa + // Bit mask of XTS_KEY_LENGTH_256_ERR field. + EFUSE_RD_REPEAT_ERR_XTS_KEY_LENGTH_256_ERR_Msk = 0x400 + // Bit XTS_KEY_LENGTH_256_ERR. + EFUSE_RD_REPEAT_ERR_XTS_KEY_LENGTH_256_ERR = 0x400 + // Position of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR_UART_PRINT_CONTROL_ERR_Pos = 0xb + // Bit mask of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR_UART_PRINT_CONTROL_ERR_Msk = 0x1800 + // Position of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR_FORCE_SEND_RESUME_ERR_Pos = 0xd + // Bit mask of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR_FORCE_SEND_RESUME_ERR_Msk = 0x2000 + // Bit FORCE_SEND_RESUME_ERR. + EFUSE_RD_REPEAT_ERR_FORCE_SEND_RESUME_ERR = 0x2000 + // Position of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_DOWNLOAD_MODE_ERR_Pos = 0xe + // Bit mask of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_DOWNLOAD_MODE_ERR_Msk = 0x4000 + // Bit DIS_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR_DIS_DOWNLOAD_MODE_ERR = 0x4000 + // Position of DIS_DIRECT_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_DIRECT_BOOT_ERR_Pos = 0xf + // Bit mask of DIS_DIRECT_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR_DIS_DIRECT_BOOT_ERR_Msk = 0x8000 + // Bit DIS_DIRECT_BOOT_ERR. + EFUSE_RD_REPEAT_ERR_DIS_DIRECT_BOOT_ERR = 0x8000 + // Position of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR_ENABLE_SECURITY_DOWNLOAD_ERR_Pos = 0x10 + // Bit mask of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR_ENABLE_SECURITY_DOWNLOAD_ERR_Msk = 0x10000 + // Bit ENABLE_SECURITY_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR_ENABLE_SECURITY_DOWNLOAD_ERR = 0x10000 + // Position of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR_FLASH_TPUW_ERR_Pos = 0x11 + // Bit mask of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR_FLASH_TPUW_ERR_Msk = 0x1e0000 + // Position of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR_SECURE_BOOT_EN_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR_SECURE_BOOT_EN_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_EN_ERR. + EFUSE_RD_REPEAT_ERR_SECURE_BOOT_EN_ERR = 0x200000 + // Position of RPT4_RESERVED_ERR field. + EFUSE_RD_REPEAT_ERR_RPT4_RESERVED_ERR_Pos = 0x16 + // Bit mask of RPT4_RESERVED_ERR field. + EFUSE_RD_REPEAT_ERR_RPT4_RESERVED_ERR_Msk = 0xffc00000 + + // RD_RS_ERR: Programming error record register 0 of BLOCK1-10. + // Position of BLK1_ERR_NUM field. + EFUSE_RD_RS_ERR_BLK1_ERR_NUM_Pos = 0x0 + // Bit mask of BLK1_ERR_NUM field. + EFUSE_RD_RS_ERR_BLK1_ERR_NUM_Msk = 0x7 + // Position of BLK1_FAIL field. + EFUSE_RD_RS_ERR_BLK1_FAIL_Pos = 0x3 + // Bit mask of BLK1_FAIL field. + EFUSE_RD_RS_ERR_BLK1_FAIL_Msk = 0x8 + // Bit BLK1_FAIL. + EFUSE_RD_RS_ERR_BLK1_FAIL = 0x8 + // Position of BLK2_ERR_NUM field. + EFUSE_RD_RS_ERR_BLK2_ERR_NUM_Pos = 0x4 + // Bit mask of BLK2_ERR_NUM field. + EFUSE_RD_RS_ERR_BLK2_ERR_NUM_Msk = 0x70 + // Position of BLK2_FAIL field. + EFUSE_RD_RS_ERR_BLK2_FAIL_Pos = 0x7 + // Bit mask of BLK2_FAIL field. + EFUSE_RD_RS_ERR_BLK2_FAIL_Msk = 0x80 + // Bit BLK2_FAIL. + EFUSE_RD_RS_ERR_BLK2_FAIL = 0x80 + // Position of BLK3_ERR_NUM field. + EFUSE_RD_RS_ERR_BLK3_ERR_NUM_Pos = 0x8 + // Bit mask of BLK3_ERR_NUM field. + EFUSE_RD_RS_ERR_BLK3_ERR_NUM_Msk = 0x700 + // Position of BLK3_FAIL field. + EFUSE_RD_RS_ERR_BLK3_FAIL_Pos = 0xb + // Bit mask of BLK3_FAIL field. + EFUSE_RD_RS_ERR_BLK3_FAIL_Msk = 0x800 + // Bit BLK3_FAIL. + EFUSE_RD_RS_ERR_BLK3_FAIL = 0x800 + + // CLK: eFuse clcok configuration register. + // Position of EFUSE_MEM_FORCE_PD field. + EFUSE_CLK_EFUSE_MEM_FORCE_PD_Pos = 0x0 + // Bit mask of EFUSE_MEM_FORCE_PD field. + EFUSE_CLK_EFUSE_MEM_FORCE_PD_Msk = 0x1 + // Bit EFUSE_MEM_FORCE_PD. + EFUSE_CLK_EFUSE_MEM_FORCE_PD = 0x1 + // Position of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + EFUSE_CLK_MEM_CLK_FORCE_ON = 0x2 + // Position of EFUSE_MEM_FORCE_PU field. + EFUSE_CLK_EFUSE_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of EFUSE_MEM_FORCE_PU field. + EFUSE_CLK_EFUSE_MEM_FORCE_PU_Msk = 0x4 + // Bit EFUSE_MEM_FORCE_PU. + EFUSE_CLK_EFUSE_MEM_FORCE_PU = 0x4 + // Position of EN field. + EFUSE_CLK_EN_Pos = 0x10 + // Bit mask of EN field. + EFUSE_CLK_EN_Msk = 0x10000 + // Bit EN. + EFUSE_CLK_EN = 0x10000 + + // CONF: eFuse operation mode configuraiton register + // Position of OP_CODE field. + EFUSE_CONF_OP_CODE_Pos = 0x0 + // Bit mask of OP_CODE field. + EFUSE_CONF_OP_CODE_Msk = 0xffff + + // STATUS: eFuse status register. + // Position of STATE field. + EFUSE_STATUS_STATE_Pos = 0x0 + // Bit mask of STATE field. + EFUSE_STATUS_STATE_Msk = 0xf + // Position of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Pos = 0x4 + // Bit mask of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Msk = 0x10 + // Bit OTP_LOAD_SW. + EFUSE_STATUS_OTP_LOAD_SW = 0x10 + // Position of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Pos = 0x5 + // Bit mask of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Msk = 0x20 + // Bit OTP_VDDQ_C_SYNC2. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2 = 0x20 + // Position of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Pos = 0x6 + // Bit mask of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Msk = 0x40 + // Bit OTP_STROBE_SW. + EFUSE_STATUS_OTP_STROBE_SW = 0x40 + // Position of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Pos = 0x7 + // Bit mask of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Msk = 0x80 + // Bit OTP_CSB_SW. + EFUSE_STATUS_OTP_CSB_SW = 0x80 + // Position of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Pos = 0x8 + // Bit mask of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Msk = 0x100 + // Bit OTP_PGENB_SW. + EFUSE_STATUS_OTP_PGENB_SW = 0x100 + // Position of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Pos = 0x9 + // Bit mask of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Msk = 0x200 + // Bit OTP_VDDQ_IS_SW. + EFUSE_STATUS_OTP_VDDQ_IS_SW = 0x200 + // Position of BLK0_VALID_BIT_CNT field. + EFUSE_STATUS_BLK0_VALID_BIT_CNT_Pos = 0xa + // Bit mask of BLK0_VALID_BIT_CNT field. + EFUSE_STATUS_BLK0_VALID_BIT_CNT_Msk = 0xfc00 + + // CMD: eFuse command register. + // Position of READ_CMD field. + EFUSE_CMD_READ_CMD_Pos = 0x0 + // Bit mask of READ_CMD field. + EFUSE_CMD_READ_CMD_Msk = 0x1 + // Bit READ_CMD. + EFUSE_CMD_READ_CMD = 0x1 + // Position of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Pos = 0x1 + // Bit mask of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Msk = 0x2 + // Bit PGM_CMD. + EFUSE_CMD_PGM_CMD = 0x2 + // Position of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Pos = 0x2 + // Bit mask of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Msk = 0xc + + // INT_RAW: eFuse raw interrupt register. + // Position of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Pos = 0x0 + // Bit mask of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Msk = 0x1 + // Bit READ_DONE_INT_RAW. + EFUSE_INT_RAW_READ_DONE_INT_RAW = 0x1 + // Position of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Pos = 0x1 + // Bit mask of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Msk = 0x2 + // Bit PGM_DONE_INT_RAW. + EFUSE_INT_RAW_PGM_DONE_INT_RAW = 0x2 + + // INT_ST: eFuse interrupt status register. + // Position of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Pos = 0x0 + // Bit mask of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Msk = 0x1 + // Bit READ_DONE_INT_ST. + EFUSE_INT_ST_READ_DONE_INT_ST = 0x1 + // Position of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Msk = 0x2 + // Bit PGM_DONE_INT_ST. + EFUSE_INT_ST_PGM_DONE_INT_ST = 0x2 + + // INT_ENA: eFuse interrupt enable register. + // Position of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Pos = 0x0 + // Bit mask of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Msk = 0x1 + // Bit READ_DONE_INT_ENA. + EFUSE_INT_ENA_READ_DONE_INT_ENA = 0x1 + // Position of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Msk = 0x2 + // Bit PGM_DONE_INT_ENA. + EFUSE_INT_ENA_PGM_DONE_INT_ENA = 0x2 + + // INT_CLR: eFuse interrupt clear register. + // Position of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Pos = 0x0 + // Bit mask of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Msk = 0x1 + // Bit READ_DONE_INT_CLR. + EFUSE_INT_CLR_READ_DONE_INT_CLR = 0x1 + // Position of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Pos = 0x1 + // Bit mask of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Msk = 0x2 + // Bit PGM_DONE_INT_CLR. + EFUSE_INT_CLR_PGM_DONE_INT_CLR = 0x2 + + // DAC_CONF: Controls the eFuse programming voltage. + // Position of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Pos = 0x0 + // Bit mask of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Msk = 0xff + // Position of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Pos = 0x8 + // Bit mask of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Msk = 0x100 + // Bit DAC_CLK_PAD_SEL. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL = 0x100 + // Position of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Pos = 0x9 + // Bit mask of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Msk = 0x1fe00 + // Position of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Pos = 0x11 + // Bit mask of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Msk = 0x20000 + // Bit OE_CLR. + EFUSE_DAC_CONF_OE_CLR = 0x20000 + + // RD_TIM_CONF: Configures read timing parameters. + // Position of THR_A field. + EFUSE_RD_TIM_CONF_THR_A_Pos = 0x0 + // Bit mask of THR_A field. + EFUSE_RD_TIM_CONF_THR_A_Msk = 0xff + // Position of TRD field. + EFUSE_RD_TIM_CONF_TRD_Pos = 0x8 + // Bit mask of TRD field. + EFUSE_RD_TIM_CONF_TRD_Msk = 0xff00 + // Position of TSUR_A field. + EFUSE_RD_TIM_CONF_TSUR_A_Pos = 0x10 + // Bit mask of TSUR_A field. + EFUSE_RD_TIM_CONF_TSUR_A_Msk = 0xff0000 + // Position of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Pos = 0x18 + // Bit mask of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Msk = 0xff000000 + + // WR_TIM_CONF0: Configurarion register 0 of eFuse programming timing parameters. + // Position of THP_A field. + EFUSE_WR_TIM_CONF0_THP_A_Pos = 0x0 + // Bit mask of THP_A field. + EFUSE_WR_TIM_CONF0_THP_A_Msk = 0xff + // Position of TPGM_INACTIVE field. + EFUSE_WR_TIM_CONF0_TPGM_INACTIVE_Pos = 0x8 + // Bit mask of TPGM_INACTIVE field. + EFUSE_WR_TIM_CONF0_TPGM_INACTIVE_Msk = 0xff00 + // Position of TPGM field. + EFUSE_WR_TIM_CONF0_TPGM_Pos = 0x10 + // Bit mask of TPGM field. + EFUSE_WR_TIM_CONF0_TPGM_Msk = 0xffff0000 + + // WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters. + // Position of TSUP_A field. + EFUSE_WR_TIM_CONF1_TSUP_A_Pos = 0x0 + // Bit mask of TSUP_A field. + EFUSE_WR_TIM_CONF1_TSUP_A_Msk = 0xff + // Position of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Pos = 0x8 + // Bit mask of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Msk = 0xffff00 + + // WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters. + // Position of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Pos = 0x0 + // Bit mask of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Msk = 0xffff + + // DATE: eFuse version register. + // Position of DATE field. + EFUSE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EFUSE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for EXTMEM: External Memory +const ( + // ICACHE_CTRL: This description will be updated in the near future. + // Position of ICACHE_ENABLE field. + EXTMEM_ICACHE_CTRL_ICACHE_ENABLE_Pos = 0x0 + // Bit mask of ICACHE_ENABLE field. + EXTMEM_ICACHE_CTRL_ICACHE_ENABLE_Msk = 0x1 + // Bit ICACHE_ENABLE. + EXTMEM_ICACHE_CTRL_ICACHE_ENABLE = 0x1 + + // ICACHE_CTRL1: This description will be updated in the near future. + // Position of ICACHE_SHUT_IBUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_IBUS_Pos = 0x0 + // Bit mask of ICACHE_SHUT_IBUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_IBUS_Msk = 0x1 + // Bit ICACHE_SHUT_IBUS. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_IBUS = 0x1 + // Position of ICACHE_SHUT_DBUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_DBUS_Pos = 0x1 + // Bit mask of ICACHE_SHUT_DBUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_DBUS_Msk = 0x2 + // Bit ICACHE_SHUT_DBUS. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_DBUS = 0x2 + + // ICACHE_TAG_POWER_CTRL: This description will be updated in the near future. + // Position of ICACHE_TAG_MEM_FORCE_ON field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of ICACHE_TAG_MEM_FORCE_ON field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON_Msk = 0x1 + // Bit ICACHE_TAG_MEM_FORCE_ON. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON = 0x1 + // Position of ICACHE_TAG_MEM_FORCE_PD field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of ICACHE_TAG_MEM_FORCE_PD field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD_Msk = 0x2 + // Bit ICACHE_TAG_MEM_FORCE_PD. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD = 0x2 + // Position of ICACHE_TAG_MEM_FORCE_PU field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of ICACHE_TAG_MEM_FORCE_PU field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU_Msk = 0x4 + // Bit ICACHE_TAG_MEM_FORCE_PU. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU = 0x4 + + // ICACHE_SYNC_CTRL: This description will be updated in the near future. + // Position of ICACHE_INVALIDATE_ENA field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA_Pos = 0x0 + // Bit mask of ICACHE_INVALIDATE_ENA field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA_Msk = 0x1 + // Bit ICACHE_INVALIDATE_ENA. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA = 0x1 + // Position of ICACHE_SYNC_DONE field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_SYNC_DONE_Pos = 0x1 + // Bit mask of ICACHE_SYNC_DONE field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_SYNC_DONE_Msk = 0x2 + // Bit ICACHE_SYNC_DONE. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_SYNC_DONE = 0x2 + + // ICACHE_SYNC_ADDR: This description will be updated in the near future. + // Position of ICACHE_SYNC_ADDR field. + EXTMEM_ICACHE_SYNC_ADDR_ICACHE_SYNC_ADDR_Pos = 0x0 + // Bit mask of ICACHE_SYNC_ADDR field. + EXTMEM_ICACHE_SYNC_ADDR_ICACHE_SYNC_ADDR_Msk = 0xffffffff + + // ICACHE_SYNC_SIZE: This description will be updated in the near future. + // Position of ICACHE_SYNC_SIZE field. + EXTMEM_ICACHE_SYNC_SIZE_ICACHE_SYNC_SIZE_Pos = 0x0 + // Bit mask of ICACHE_SYNC_SIZE field. + EXTMEM_ICACHE_SYNC_SIZE_ICACHE_SYNC_SIZE_Msk = 0x7fffff + + // IBUS_TO_FLASH_START_VADDR: This description will be updated in the near future. + // Position of IBUS_TO_FLASH_START_VADDR field. + EXTMEM_IBUS_TO_FLASH_START_VADDR_IBUS_TO_FLASH_START_VADDR_Pos = 0x0 + // Bit mask of IBUS_TO_FLASH_START_VADDR field. + EXTMEM_IBUS_TO_FLASH_START_VADDR_IBUS_TO_FLASH_START_VADDR_Msk = 0xffffffff + + // IBUS_TO_FLASH_END_VADDR: This description will be updated in the near future. + // Position of IBUS_TO_FLASH_END_VADDR field. + EXTMEM_IBUS_TO_FLASH_END_VADDR_IBUS_TO_FLASH_END_VADDR_Pos = 0x0 + // Bit mask of IBUS_TO_FLASH_END_VADDR field. + EXTMEM_IBUS_TO_FLASH_END_VADDR_IBUS_TO_FLASH_END_VADDR_Msk = 0xffffffff + + // DBUS_TO_FLASH_START_VADDR: This description will be updated in the near future. + // Position of DBUS_TO_FLASH_START_VADDR field. + EXTMEM_DBUS_TO_FLASH_START_VADDR_DBUS_TO_FLASH_START_VADDR_Pos = 0x0 + // Bit mask of DBUS_TO_FLASH_START_VADDR field. + EXTMEM_DBUS_TO_FLASH_START_VADDR_DBUS_TO_FLASH_START_VADDR_Msk = 0xffffffff + + // DBUS_TO_FLASH_END_VADDR: This description will be updated in the near future. + // Position of DBUS_TO_FLASH_END_VADDR field. + EXTMEM_DBUS_TO_FLASH_END_VADDR_DBUS_TO_FLASH_END_VADDR_Pos = 0x0 + // Bit mask of DBUS_TO_FLASH_END_VADDR field. + EXTMEM_DBUS_TO_FLASH_END_VADDR_DBUS_TO_FLASH_END_VADDR_Msk = 0xffffffff + + // CACHE_ACS_CNT_CLR: This description will be updated in the near future. + // Position of IBUS_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR_Pos = 0x0 + // Bit mask of IBUS_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR_Msk = 0x1 + // Bit IBUS_ACS_CNT_CLR. + EXTMEM_CACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR = 0x1 + // Position of DBUS_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR_Pos = 0x1 + // Bit mask of DBUS_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR_Msk = 0x2 + // Bit DBUS_ACS_CNT_CLR. + EXTMEM_CACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR = 0x2 + + // CACHE_ILG_INT_ENA: This description will be updated in the near future. + // Position of ICACHE_SYNC_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA_Pos = 0x0 + // Bit mask of ICACHE_SYNC_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA_Msk = 0x1 + // Bit ICACHE_SYNC_OP_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA = 0x1 + // Position of ICACHE_PRELOAD_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA_Msk = 0x2 + // Bit ICACHE_PRELOAD_OP_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA = 0x2 + // Position of MMU_ENTRY_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA_Pos = 0x5 + // Bit mask of MMU_ENTRY_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA_Msk = 0x20 + // Bit MMU_ENTRY_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA = 0x20 + // Position of IBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA_Pos = 0x7 + // Bit mask of IBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA_Msk = 0x80 + // Bit IBUS_CNT_OVF_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA = 0x80 + // Position of DBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA_Pos = 0x8 + // Bit mask of DBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA_Msk = 0x100 + // Bit DBUS_CNT_OVF_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA = 0x100 + + // CACHE_ILG_INT_CLR: This description will be updated in the near future. + // Position of ICACHE_SYNC_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR_Pos = 0x0 + // Bit mask of ICACHE_SYNC_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR_Msk = 0x1 + // Bit ICACHE_SYNC_OP_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR = 0x1 + // Position of ICACHE_PRELOAD_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR_Msk = 0x2 + // Bit ICACHE_PRELOAD_OP_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR = 0x2 + // Position of MMU_ENTRY_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR_Pos = 0x5 + // Bit mask of MMU_ENTRY_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR_Msk = 0x20 + // Bit MMU_ENTRY_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR = 0x20 + // Position of IBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR_Pos = 0x7 + // Bit mask of IBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR_Msk = 0x80 + // Bit IBUS_CNT_OVF_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR = 0x80 + // Position of DBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR_Pos = 0x8 + // Bit mask of DBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR_Msk = 0x100 + // Bit DBUS_CNT_OVF_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR = 0x100 + + // CACHE_ILG_INT_ST: This description will be updated in the near future. + // Position of ICACHE_SYNC_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST_Pos = 0x0 + // Bit mask of ICACHE_SYNC_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST_Msk = 0x1 + // Bit ICACHE_SYNC_OP_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST = 0x1 + // Position of ICACHE_PRELOAD_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST_Msk = 0x2 + // Bit ICACHE_PRELOAD_OP_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST = 0x2 + // Position of MMU_ENTRY_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST_Pos = 0x5 + // Bit mask of MMU_ENTRY_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST_Msk = 0x20 + // Bit MMU_ENTRY_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST = 0x20 + // Position of IBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST_Pos = 0x7 + // Bit mask of IBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST_Msk = 0x80 + // Bit IBUS_ACS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST = 0x80 + // Position of IBUS_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST_Pos = 0x8 + // Bit mask of IBUS_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST_Msk = 0x100 + // Bit IBUS_ACS_MISS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST = 0x100 + // Position of DBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST_Pos = 0x9 + // Bit mask of DBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST_Msk = 0x200 + // Bit DBUS_ACS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST = 0x200 + // Position of DBUS_ACS_FLASH_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_Pos = 0xa + // Bit mask of DBUS_ACS_FLASH_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_Msk = 0x400 + // Bit DBUS_ACS_FLASH_MISS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST = 0x400 + + // CORE0_ACS_CACHE_INT_ENA: This description will be updated in the near future. + // Position of CORE0_IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA_Pos = 0x0 + // Bit mask of CORE0_IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA_Msk = 0x1 + // Bit CORE0_IBUS_ACS_MSK_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA = 0x1 + // Position of CORE0_IBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA_Pos = 0x1 + // Bit mask of CORE0_IBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA_Msk = 0x2 + // Bit CORE0_IBUS_WR_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA = 0x2 + // Position of CORE0_IBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA_Pos = 0x2 + // Bit mask of CORE0_IBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA_Msk = 0x4 + // Bit CORE0_IBUS_REJECT_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA = 0x4 + // Position of CORE0_DBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA_Pos = 0x3 + // Bit mask of CORE0_DBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA_Msk = 0x8 + // Bit CORE0_DBUS_ACS_MSK_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA = 0x8 + // Position of CORE0_DBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA_Pos = 0x4 + // Bit mask of CORE0_DBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA_Msk = 0x10 + // Bit CORE0_DBUS_REJECT_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA = 0x10 + // Position of CORE0_DBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA_Pos = 0x5 + // Bit mask of CORE0_DBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA_Msk = 0x20 + // Bit CORE0_DBUS_WR_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA = 0x20 + + // CORE0_ACS_CACHE_INT_CLR: This description will be updated in the near future. + // Position of CORE0_IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR_Pos = 0x0 + // Bit mask of CORE0_IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR_Msk = 0x1 + // Bit CORE0_IBUS_ACS_MSK_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR = 0x1 + // Position of CORE0_IBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR_Pos = 0x1 + // Bit mask of CORE0_IBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR_Msk = 0x2 + // Bit CORE0_IBUS_WR_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR = 0x2 + // Position of CORE0_IBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR_Pos = 0x2 + // Bit mask of CORE0_IBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR_Msk = 0x4 + // Bit CORE0_IBUS_REJECT_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR = 0x4 + // Position of CORE0_DBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR_Pos = 0x3 + // Bit mask of CORE0_DBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR_Msk = 0x8 + // Bit CORE0_DBUS_ACS_MSK_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR = 0x8 + // Position of CORE0_DBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR_Pos = 0x4 + // Bit mask of CORE0_DBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR_Msk = 0x10 + // Bit CORE0_DBUS_REJECT_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR = 0x10 + // Position of CORE0_DBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR_Pos = 0x5 + // Bit mask of CORE0_DBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR_Msk = 0x20 + // Bit CORE0_DBUS_WR_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR = 0x20 + + // CORE0_ACS_CACHE_INT_ST: This description will be updated in the near future. + // Position of CORE0_IBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST_Pos = 0x0 + // Bit mask of CORE0_IBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST_Msk = 0x1 + // Bit CORE0_IBUS_ACS_MSK_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST = 0x1 + // Position of CORE0_IBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST_Pos = 0x1 + // Bit mask of CORE0_IBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST_Msk = 0x2 + // Bit CORE0_IBUS_WR_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST = 0x2 + // Position of CORE0_IBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST_Pos = 0x2 + // Bit mask of CORE0_IBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST_Msk = 0x4 + // Bit CORE0_IBUS_REJECT_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST = 0x4 + // Position of CORE0_DBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST_Pos = 0x3 + // Bit mask of CORE0_DBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST_Msk = 0x8 + // Bit CORE0_DBUS_ACS_MSK_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST = 0x8 + // Position of CORE0_DBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST_Pos = 0x4 + // Bit mask of CORE0_DBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST_Msk = 0x10 + // Bit CORE0_DBUS_REJECT_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST = 0x10 + // Position of CORE0_DBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST_Pos = 0x5 + // Bit mask of CORE0_DBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST_Msk = 0x20 + // Bit CORE0_DBUS_WR_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST = 0x20 + + // CORE0_DBUS_REJECT_ST: This description will be updated in the near future. + // Position of CORE0_DBUS_ATTR field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR_Pos = 0x0 + // Bit mask of CORE0_DBUS_ATTR field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR_Msk = 0x7 + // Position of CORE0_DBUS_WORLD field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD_Pos = 0x3 + // Bit mask of CORE0_DBUS_WORLD field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD_Msk = 0x8 + // Bit CORE0_DBUS_WORLD. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD = 0x8 + + // CORE0_DBUS_REJECT_VADDR: This description will be updated in the near future. + // Position of CORE0_DBUS_VADDR field. + EXTMEM_CORE0_DBUS_REJECT_VADDR_CORE0_DBUS_VADDR_Pos = 0x0 + // Bit mask of CORE0_DBUS_VADDR field. + EXTMEM_CORE0_DBUS_REJECT_VADDR_CORE0_DBUS_VADDR_Msk = 0xffffffff + + // CORE0_IBUS_REJECT_ST: This description will be updated in the near future. + // Position of CORE0_IBUS_ATTR field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR_Pos = 0x0 + // Bit mask of CORE0_IBUS_ATTR field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR_Msk = 0x7 + // Position of CORE0_IBUS_WORLD field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD_Pos = 0x3 + // Bit mask of CORE0_IBUS_WORLD field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD_Msk = 0x8 + // Bit CORE0_IBUS_WORLD. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD = 0x8 + + // CORE0_IBUS_REJECT_VADDR: This description will be updated in the near future. + // Position of CORE0_IBUS_VADDR field. + EXTMEM_CORE0_IBUS_REJECT_VADDR_CORE0_IBUS_VADDR_Pos = 0x0 + // Bit mask of CORE0_IBUS_VADDR field. + EXTMEM_CORE0_IBUS_REJECT_VADDR_CORE0_IBUS_VADDR_Msk = 0xffffffff + + // CACHE_MMU_FAULT_CONTENT: This description will be updated in the near future. + // Position of CACHE_MMU_FAULT_CONTENT field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CONTENT_Pos = 0x0 + // Bit mask of CACHE_MMU_FAULT_CONTENT field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CONTENT_Msk = 0xff + // Position of CACHE_MMU_FAULT_CODE field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE_Pos = 0xa + // Bit mask of CACHE_MMU_FAULT_CODE field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE_Msk = 0x3c00 + + // CACHE_MMU_FAULT_VADDR: This description will be updated in the near future. + // Position of CACHE_MMU_FAULT_VADDR field. + EXTMEM_CACHE_MMU_FAULT_VADDR_CACHE_MMU_FAULT_VADDR_Pos = 0x0 + // Bit mask of CACHE_MMU_FAULT_VADDR field. + EXTMEM_CACHE_MMU_FAULT_VADDR_CACHE_MMU_FAULT_VADDR_Msk = 0xffffffff + + // CACHE_WRAP_AROUND_CTRL: This description will be updated in the near future. + // Position of CACHE_FLASH_WRAP_AROUND field. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND_Pos = 0x0 + // Bit mask of CACHE_FLASH_WRAP_AROUND field. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND_Msk = 0x1 + // Bit CACHE_FLASH_WRAP_AROUND. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND = 0x1 + + // CACHE_MMU_POWER_CTRL: This description will be updated in the near future. + // Position of CACHE_MMU_MEM_FORCE_ON field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of CACHE_MMU_MEM_FORCE_ON field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON_Msk = 0x1 + // Bit CACHE_MMU_MEM_FORCE_ON. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON = 0x1 + // Position of CACHE_MMU_MEM_FORCE_PD field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of CACHE_MMU_MEM_FORCE_PD field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD_Msk = 0x2 + // Bit CACHE_MMU_MEM_FORCE_PD. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD = 0x2 + // Position of CACHE_MMU_MEM_FORCE_PU field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of CACHE_MMU_MEM_FORCE_PU field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU_Msk = 0x4 + // Bit CACHE_MMU_MEM_FORCE_PU. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU = 0x4 + + // CACHE_STATE: This description will be updated in the near future. + // Position of ICACHE_STATE field. + EXTMEM_CACHE_STATE_ICACHE_STATE_Pos = 0x0 + // Bit mask of ICACHE_STATE field. + EXTMEM_CACHE_STATE_ICACHE_STATE_Msk = 0xfff + + // CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: This description will be updated in the near future. + // Position of RECORD_DISABLE_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT_Pos = 0x0 + // Bit mask of RECORD_DISABLE_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT_Msk = 0x1 + // Bit RECORD_DISABLE_DB_ENCRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT = 0x1 + // Position of RECORD_DISABLE_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT_Pos = 0x1 + // Bit mask of RECORD_DISABLE_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT_Msk = 0x2 + // Bit RECORD_DISABLE_G0CB_DECRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT = 0x2 + + // CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: This description will be updated in the near future. + // Position of CLK_FORCE_ON_MANUAL_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT_Pos = 0x0 + // Bit mask of CLK_FORCE_ON_MANUAL_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT_Msk = 0x1 + // Bit CLK_FORCE_ON_MANUAL_CRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT = 0x1 + // Position of CLK_FORCE_ON_AUTO_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT_Pos = 0x1 + // Bit mask of CLK_FORCE_ON_AUTO_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT_Msk = 0x2 + // Bit CLK_FORCE_ON_AUTO_CRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT = 0x2 + // Position of CLK_FORCE_ON_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT_Pos = 0x2 + // Bit mask of CLK_FORCE_ON_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT_Msk = 0x4 + // Bit CLK_FORCE_ON_CRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT = 0x4 + + // CACHE_PRELOAD_INT_CTRL: This description will be updated in the near future. + // Position of ICACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST_Msk = 0x1 + // Bit ICACHE_PRELOAD_INT_ST. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST = 0x1 + // Position of ICACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA_Msk = 0x2 + // Bit ICACHE_PRELOAD_INT_ENA. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA = 0x2 + // Position of ICACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR_Pos = 0x2 + // Bit mask of ICACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR_Msk = 0x4 + // Bit ICACHE_PRELOAD_INT_CLR. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR = 0x4 + + // CACHE_SYNC_INT_CTRL: This description will be updated in the near future. + // Position of ICACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST_Pos = 0x0 + // Bit mask of ICACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST_Msk = 0x1 + // Bit ICACHE_SYNC_INT_ST. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST = 0x1 + // Position of ICACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA_Pos = 0x1 + // Bit mask of ICACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA_Msk = 0x2 + // Bit ICACHE_SYNC_INT_ENA. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA = 0x2 + // Position of ICACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR_Pos = 0x2 + // Bit mask of ICACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR_Msk = 0x4 + // Bit ICACHE_SYNC_INT_CLR. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR = 0x4 + + // CACHE_MMU_OWNER: This description will be updated in the near future. + // Position of CACHE_MMU_OWNER field. + EXTMEM_CACHE_MMU_OWNER_CACHE_MMU_OWNER_Pos = 0x0 + // Bit mask of CACHE_MMU_OWNER field. + EXTMEM_CACHE_MMU_OWNER_CACHE_MMU_OWNER_Msk = 0xf + + // CACHE_CONF_MISC: This description will be updated in the near future. + // Position of CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_Pos = 0x0 + // Bit mask of CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_Msk = 0x1 + // Bit CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT = 0x1 + // Position of CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_Pos = 0x1 + // Bit mask of CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_Msk = 0x2 + // Bit CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT = 0x2 + // Position of CACHE_TRACE_ENA field. + EXTMEM_CACHE_CONF_MISC_CACHE_TRACE_ENA_Pos = 0x2 + // Bit mask of CACHE_TRACE_ENA field. + EXTMEM_CACHE_CONF_MISC_CACHE_TRACE_ENA_Msk = 0x4 + // Bit CACHE_TRACE_ENA. + EXTMEM_CACHE_CONF_MISC_CACHE_TRACE_ENA = 0x4 + // Position of CACHE_MMU_PAGE_SIZE field. + EXTMEM_CACHE_CONF_MISC_CACHE_MMU_PAGE_SIZE_Pos = 0x3 + // Bit mask of CACHE_MMU_PAGE_SIZE field. + EXTMEM_CACHE_CONF_MISC_CACHE_MMU_PAGE_SIZE_Msk = 0x18 + + // ICACHE_FREEZE: This description will be updated in the near future. + // Position of ENA field. + EXTMEM_ICACHE_FREEZE_ENA_Pos = 0x0 + // Bit mask of ENA field. + EXTMEM_ICACHE_FREEZE_ENA_Msk = 0x1 + // Bit ENA. + EXTMEM_ICACHE_FREEZE_ENA = 0x1 + // Position of MODE field. + EXTMEM_ICACHE_FREEZE_MODE_Pos = 0x1 + // Bit mask of MODE field. + EXTMEM_ICACHE_FREEZE_MODE_Msk = 0x2 + // Bit MODE. + EXTMEM_ICACHE_FREEZE_MODE = 0x2 + // Position of DONE field. + EXTMEM_ICACHE_FREEZE_DONE_Pos = 0x2 + // Bit mask of DONE field. + EXTMEM_ICACHE_FREEZE_DONE_Msk = 0x4 + // Bit DONE. + EXTMEM_ICACHE_FREEZE_DONE = 0x4 + + // ICACHE_ATOMIC_OPERATE_ENA: This description will be updated in the near future. + // Position of ICACHE_ATOMIC_OPERATE_ENA field. + EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_ICACHE_ATOMIC_OPERATE_ENA_Pos = 0x0 + // Bit mask of ICACHE_ATOMIC_OPERATE_ENA field. + EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_ICACHE_ATOMIC_OPERATE_ENA_Msk = 0x1 + // Bit ICACHE_ATOMIC_OPERATE_ENA. + EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_ICACHE_ATOMIC_OPERATE_ENA = 0x1 + + // CACHE_REQUEST: This description will be updated in the near future. + // Position of BYPASS field. + EXTMEM_CACHE_REQUEST_BYPASS_Pos = 0x0 + // Bit mask of BYPASS field. + EXTMEM_CACHE_REQUEST_BYPASS_Msk = 0x1 + // Bit BYPASS. + EXTMEM_CACHE_REQUEST_BYPASS = 0x1 + + // CLOCK_GATE: This description will be updated in the near future. + // Position of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + EXTMEM_CLOCK_GATE_CLK_EN = 0x1 + + // REG_DATE: This description will be updated in the near future. + // Position of DATE field. + EXTMEM_REG_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EXTMEM_REG_DATE_DATE_Msk = 0xfffffff +) + +// Constants for GPIO: General Purpose Input/Output +const ( + // BT_SELECT: GPIO bit select register + // Position of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Pos = 0x0 + // Bit mask of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Msk = 0xffffffff + + // OUT: GPIO output register + // Position of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Pos = 0x0 + // Bit mask of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Msk = 0x1ffffff + + // OUT_W1TS: GPIO output set register + // Position of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Pos = 0x0 + // Bit mask of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Msk = 0x1ffffff + + // OUT_W1TC: GPIO output clear register + // Position of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Pos = 0x0 + // Bit mask of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Msk = 0x1ffffff + + // SDIO_SELECT: GPIO sdio select register + // Position of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Pos = 0x0 + // Bit mask of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Msk = 0xff + + // ENABLE: GPIO output enable register + // Position of DATA field. + GPIO_ENABLE_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE_DATA_Msk = 0x1ffffff + + // ENABLE_W1TS: GPIO output enable set register + // Position of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Pos = 0x0 + // Bit mask of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Msk = 0x1ffffff + + // ENABLE_W1TC: GPIO output enable clear register + // Position of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0x0 + // Bit mask of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0x1ffffff + + // STRAP: pad strapping register + // Position of STRAPPING field. + GPIO_STRAP_STRAPPING_Pos = 0x0 + // Bit mask of STRAPPING field. + GPIO_STRAP_STRAPPING_Msk = 0xffff + + // IN: GPIO input register + // Position of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Msk = 0x1ffffff + + // STATUS: GPIO interrupt status register + // Position of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Msk = 0x1ffffff + + // STATUS_W1TS: GPIO interrupt status set register + // Position of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Pos = 0x0 + // Bit mask of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Msk = 0x1ffffff + + // STATUS_W1TC: GPIO interrupt status clear register + // Position of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Pos = 0x0 + // Bit mask of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Msk = 0x1ffffff + + // PCPU_INT: GPIO PRO_CPU interrupt status register + // Position of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Pos = 0x0 + // Bit mask of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Msk = 0x1ffffff + + // PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register + // Position of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Msk = 0x1ffffff + + // CPUSDIO_INT: GPIO CPUSDIO interrupt status register + // Position of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Pos = 0x0 + // Bit mask of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Msk = 0x1ffffff + + // PIN0: GPIO pin configuration register + // Position of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Pos = 0x0 + // Bit mask of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Msk = 0x3 + // Position of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + GPIO_PIN_PAD_DRIVER = 0x4 + // Position of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Pos = 0x3 + // Bit mask of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Msk = 0x18 + // Position of INT_TYPE field. + GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + GPIO_PIN_WAKEUP_ENABLE = 0x400 + // Position of CONFIG field. + GPIO_PIN_CONFIG_Pos = 0xb + // Bit mask of CONFIG field. + GPIO_PIN_CONFIG_Msk = 0x1800 + // Position of INT_ENA field. + GPIO_PIN_INT_ENA_Pos = 0xd + // Bit mask of INT_ENA field. + GPIO_PIN_INT_ENA_Msk = 0x3e000 + + // STATUS_NEXT: GPIO interrupt source register + // Position of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Pos = 0x0 + // Bit mask of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Msk = 0x3ffffff + + // FUNC0_IN_SEL_CFG: GPIO input function configuration register + // Position of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Pos = 0x0 + // Bit mask of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Msk = 0x1f + // Position of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Pos = 0x5 + // Bit mask of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Msk = 0x20 + // Bit IN_INV_SEL. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL = 0x20 + // Position of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Pos = 0x6 + // Bit mask of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Msk = 0x40 + // Bit SEL. + GPIO_FUNC_IN_SEL_CFG_SEL = 0x40 + + // FUNC0_OUT_SEL_CFG: GPIO output function select register + // Position of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Pos = 0x0 + // Bit mask of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Msk = 0xff + // Position of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Pos = 0x8 + // Bit mask of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Msk = 0x100 + // Bit INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL = 0x100 + // Position of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Pos = 0x9 + // Bit mask of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Msk = 0x200 + // Bit OEN_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL = 0x200 + // Position of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Pos = 0xa + // Bit mask of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Msk = 0x400 + // Bit OEN_INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL = 0x400 + + // CLOCK_GATE: GPIO clock gate register + // Position of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + GPIO_CLOCK_GATE_CLK_EN = 0x1 + + // REG_DATE: GPIO version register + // Position of REG_DATE field. + GPIO_REG_DATE_REG_DATE_Pos = 0x0 + // Bit mask of REG_DATE field. + GPIO_REG_DATE_REG_DATE_Msk = 0xfffffff +) + +// Constants for I2C0: I2C (Inter-Integrated Circuit) Controller 0 +const ( + // SCL_LOW_PERIOD: Configures the low level width of the SCL Clock + // Position of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x1ff + + // CTR: Transmission setting + // Position of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + I2C_CTR_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + I2C_CTR_SCL_FORCE_OUT = 0x2 + // Position of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2 + // Bit mask of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4 + // Bit SAMPLE_SCL_LEVEL. + I2C_CTR_SAMPLE_SCL_LEVEL = 0x4 + // Position of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Pos = 0x3 + // Bit mask of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Msk = 0x8 + // Bit RX_FULL_ACK_LEVEL. + I2C_CTR_RX_FULL_ACK_LEVEL = 0x8 + // Position of MS_MODE field. + I2C_CTR_MS_MODE_Pos = 0x4 + // Bit mask of MS_MODE field. + I2C_CTR_MS_MODE_Msk = 0x10 + // Bit MS_MODE. + I2C_CTR_MS_MODE = 0x10 + // Position of TRANS_START field. + I2C_CTR_TRANS_START_Pos = 0x5 + // Bit mask of TRANS_START field. + I2C_CTR_TRANS_START_Msk = 0x20 + // Bit TRANS_START. + I2C_CTR_TRANS_START = 0x20 + // Position of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Msk = 0x40 + // Bit TX_LSB_FIRST. + I2C_CTR_TX_LSB_FIRST = 0x40 + // Position of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Msk = 0x80 + // Bit RX_LSB_FIRST. + I2C_CTR_RX_LSB_FIRST = 0x80 + // Position of CLK_EN field. + I2C_CTR_CLK_EN_Pos = 0x8 + // Bit mask of CLK_EN field. + I2C_CTR_CLK_EN_Msk = 0x100 + // Bit CLK_EN. + I2C_CTR_CLK_EN = 0x100 + // Position of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Pos = 0x9 + // Bit mask of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Msk = 0x200 + // Bit ARBITRATION_EN. + I2C_CTR_ARBITRATION_EN = 0x200 + // Position of FSM_RST field. + I2C_CTR_FSM_RST_Pos = 0xa + // Bit mask of FSM_RST field. + I2C_CTR_FSM_RST_Msk = 0x400 + // Bit FSM_RST. + I2C_CTR_FSM_RST = 0x400 + // Position of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Pos = 0xb + // Bit mask of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Msk = 0x800 + // Bit CONF_UPGATE. + I2C_CTR_CONF_UPGATE = 0x800 + // Position of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Pos = 0xc + // Bit mask of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Msk = 0x1000 + // Bit SLV_TX_AUTO_START_EN. + I2C_CTR_SLV_TX_AUTO_START_EN = 0x1000 + + // SR: Describe I2C work status. + // Position of RESP_REC field. + I2C_SR_RESP_REC_Pos = 0x0 + // Bit mask of RESP_REC field. + I2C_SR_RESP_REC_Msk = 0x1 + // Bit RESP_REC. + I2C_SR_RESP_REC = 0x1 + // Position of ARB_LOST field. + I2C_SR_ARB_LOST_Pos = 0x3 + // Bit mask of ARB_LOST field. + I2C_SR_ARB_LOST_Msk = 0x8 + // Bit ARB_LOST. + I2C_SR_ARB_LOST = 0x8 + // Position of BUS_BUSY field. + I2C_SR_BUS_BUSY_Pos = 0x4 + // Bit mask of BUS_BUSY field. + I2C_SR_BUS_BUSY_Msk = 0x10 + // Bit BUS_BUSY. + I2C_SR_BUS_BUSY = 0x10 + // Position of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Pos = 0x8 + // Bit mask of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Msk = 0x1f00 + // Position of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Pos = 0x12 + // Bit mask of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Msk = 0x7c0000 + // Position of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: Setting time out control for receiving data. + // Position of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Pos = 0x0 + // Bit mask of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Msk = 0x1f + // Position of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Pos = 0x5 + // Bit mask of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Msk = 0x20 + // Bit TIME_OUT_EN. + I2C_TO_TIME_OUT_EN = 0x20 + + // FIFO_ST: FIFO status register. + // Position of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Pos = 0x0 + // Bit mask of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Msk = 0xf + // Position of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Pos = 0x5 + // Bit mask of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Msk = 0x1e0 + // Position of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Pos = 0xa + // Bit mask of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Msk = 0x3c00 + // Position of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Pos = 0xf + // Bit mask of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Msk = 0x78000 + + // FIFO_CONF: FIFO configuration register. + // Position of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0xf + // Position of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5 + // Bit mask of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x1e0 + // Position of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa + // Bit mask of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400 + // Bit NONFIFO_EN. + I2C_FIFO_CONF_NONFIFO_EN = 0x400 + // Position of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc + // Bit mask of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000 + // Bit RX_FIFO_RST. + I2C_FIFO_CONF_RX_FIFO_RST = 0x1000 + // Position of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd + // Bit mask of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000 + // Bit TX_FIFO_RST. + I2C_FIFO_CONF_TX_FIFO_RST = 0x2000 + // Position of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Pos = 0xe + // Bit mask of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000 + // Bit FIFO_PRT_EN. + I2C_FIFO_CONF_FIFO_PRT_EN = 0x4000 + + // DATA: Rx FIFO read data. + // Position of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Pos = 0x0 + // Bit mask of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Msk = 0x1 + // Bit RXFIFO_WM_INT_RAW. + I2C_INT_RAW_RXFIFO_WM_INT_RAW = 0x1 + // Position of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Msk = 0x2 + // Bit TXFIFO_WM_INT_RAW. + I2C_INT_RAW_TXFIFO_WM_INT_RAW = 0x2 + // Position of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4 + // Bit RXFIFO_OVF_INT_RAW. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4 + // Position of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3 + // Bit mask of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8 + // Bit END_DETECT_INT_RAW. + I2C_INT_RAW_END_DETECT_INT_RAW = 0x8 + // Position of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_RAW. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW = 0x10 + // Position of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_RAW. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20 + // Position of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_RAW. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW = 0x40 + // Position of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_RAW. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80 + // Position of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8 + // Bit mask of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100 + // Bit TIME_OUT_INT_RAW. + I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100 + // Position of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9 + // Bit mask of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200 + // Bit TRANS_START_INT_RAW. + I2C_INT_RAW_TRANS_START_INT_RAW = 0x200 + // Position of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Pos = 0xa + // Bit mask of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Msk = 0x400 + // Bit NACK_INT_RAW. + I2C_INT_RAW_NACK_INT_RAW = 0x400 + // Position of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Msk = 0x800 + // Bit TXFIFO_OVF_INT_RAW. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW = 0x800 + // Position of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_RAW. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW = 0x1000 + // Position of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Msk = 0x2000 + // Bit SCL_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_ST_TO_INT_RAW = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW = 0x4000 + // Position of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Pos = 0xf + // Bit mask of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Msk = 0x8000 + // Bit DET_START_INT_RAW. + I2C_INT_RAW_DET_START_INT_RAW = 0x8000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Msk = 0x1 + // Bit RXFIFO_WM_INT_CLR. + I2C_INT_CLR_RXFIFO_WM_INT_CLR = 0x1 + // Position of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Msk = 0x2 + // Bit TXFIFO_WM_INT_CLR. + I2C_INT_CLR_TXFIFO_WM_INT_CLR = 0x2 + // Position of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4 + // Bit RXFIFO_OVF_INT_CLR. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4 + // Position of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3 + // Bit mask of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8 + // Bit END_DETECT_INT_CLR. + I2C_INT_CLR_END_DETECT_INT_CLR = 0x8 + // Position of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_CLR. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR = 0x10 + // Position of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_CLR. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_CLR. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR = 0x40 + // Position of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_CLR. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit TIME_OUT_INT_CLR. + I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100 + // Position of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9 + // Bit mask of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200 + // Bit TRANS_START_INT_CLR. + I2C_INT_CLR_TRANS_START_INT_CLR = 0x200 + // Position of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Pos = 0xa + // Bit mask of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Msk = 0x400 + // Bit NACK_INT_CLR. + I2C_INT_CLR_NACK_INT_CLR = 0x400 + // Position of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Msk = 0x800 + // Bit TXFIFO_OVF_INT_CLR. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR = 0x800 + // Position of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_CLR. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR = 0x1000 + // Position of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Msk = 0x2000 + // Bit SCL_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_ST_TO_INT_CLR = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR = 0x4000 + // Position of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Pos = 0xf + // Bit mask of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Msk = 0x8000 + // Bit DET_START_INT_CLR. + I2C_INT_CLR_DET_START_INT_CLR = 0x8000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Msk = 0x1 + // Bit RXFIFO_WM_INT_ENA. + I2C_INT_ENA_RXFIFO_WM_INT_ENA = 0x1 + // Position of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Msk = 0x2 + // Bit TXFIFO_WM_INT_ENA. + I2C_INT_ENA_TXFIFO_WM_INT_ENA = 0x2 + // Position of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ENA. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4 + // Position of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3 + // Bit mask of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8 + // Bit END_DETECT_INT_ENA. + I2C_INT_ENA_END_DETECT_INT_ENA = 0x8 + // Position of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ENA. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA = 0x10 + // Position of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ENA. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20 + // Position of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ENA. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA = 0x40 + // Position of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ENA. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80 + // Position of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100 + // Bit TIME_OUT_INT_ENA. + I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100 + // Position of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9 + // Bit mask of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200 + // Bit TRANS_START_INT_ENA. + I2C_INT_ENA_TRANS_START_INT_ENA = 0x200 + // Position of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Pos = 0xa + // Bit mask of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Msk = 0x400 + // Bit NACK_INT_ENA. + I2C_INT_ENA_NACK_INT_ENA = 0x400 + // Position of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ENA. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA = 0x800 + // Position of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ENA. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA = 0x1000 + // Position of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_ST_TO_INT_ENA = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA = 0x4000 + // Position of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Pos = 0xf + // Bit mask of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Msk = 0x8000 + // Bit DET_START_INT_ENA. + I2C_INT_ENA_DET_START_INT_ENA = 0x8000 + + // INT_STATUS: Status of captured I2C communication events + // Position of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Msk = 0x1 + // Bit RXFIFO_WM_INT_ST. + I2C_INT_STATUS_RXFIFO_WM_INT_ST = 0x1 + // Position of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Msk = 0x2 + // Bit TXFIFO_WM_INT_ST. + I2C_INT_STATUS_TXFIFO_WM_INT_ST = 0x2 + // Position of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ST. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4 + // Position of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3 + // Bit mask of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8 + // Bit END_DETECT_INT_ST. + I2C_INT_STATUS_END_DETECT_INT_ST = 0x8 + // Position of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ST. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST = 0x10 + // Position of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ST. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20 + // Position of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ST. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST = 0x40 + // Position of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ST. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80 + // Position of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100 + // Bit TIME_OUT_INT_ST. + I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100 + // Position of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9 + // Bit mask of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200 + // Bit TRANS_START_INT_ST. + I2C_INT_STATUS_TRANS_START_INT_ST = 0x200 + // Position of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Pos = 0xa + // Bit mask of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Msk = 0x400 + // Bit NACK_INT_ST. + I2C_INT_STATUS_NACK_INT_ST = 0x400 + // Position of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ST. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST = 0x800 + // Position of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ST. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST = 0x1000 + // Position of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_ST_TO_INT_ST = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST = 0x4000 + // Position of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Pos = 0xf + // Bit mask of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Msk = 0x8000 + // Bit DET_START_INT_ST. + I2C_INT_STATUS_DET_START_INT_ST = 0x8000 + + // SDA_HOLD: Configures the hold time after a negative SCL edge. + // Position of TIME field. + I2C_SDA_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_HOLD_TIME_Msk = 0x1ff + + // SDA_SAMPLE: Configures the sample time after a positive SCL edge. + // Position of TIME field. + I2C_SDA_SAMPLE_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_SAMPLE_TIME_Msk = 0x1ff + + // SCL_HIGH_PERIOD: Configures the high level width of SCL + // Position of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x1ff + // Position of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Pos = 0x9 + // Bit mask of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Msk = 0xfe00 + + // SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition + // Position of TIME field. + I2C_SCL_START_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_START_HOLD_TIME_Msk = 0x1ff + + // SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA + // Position of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Msk = 0x1ff + + // SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_HOLD_TIME_Msk = 0x1ff + + // SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_SETUP_TIME_Msk = 0x1ff + + // FILTER_CFG: SCL and SDA filter configuration register + // Position of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0 + // Bit mask of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Msk = 0xf + // Position of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x4 + // Bit mask of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Msk = 0xf0 + // Position of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Pos = 0x8 + // Bit mask of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Msk = 0x100 + // Bit SCL_FILTER_EN. + I2C_FILTER_CFG_SCL_FILTER_EN = 0x100 + // Position of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Pos = 0x9 + // Bit mask of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Msk = 0x200 + // Bit SDA_FILTER_EN. + I2C_FILTER_CFG_SDA_FILTER_EN = 0x200 + + // CLK_CONF: I2C CLK configuration register + // Position of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Pos = 0x0 + // Bit mask of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff + // Position of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Pos = 0x8 + // Bit mask of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Msk = 0x3f00 + // Position of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Pos = 0xe + // Bit mask of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Msk = 0xfc000 + // Position of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Msk = 0x100000 + // Bit SCLK_SEL. + I2C_CLK_CONF_SCLK_SEL = 0x100000 + // Position of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Pos = 0x15 + // Bit mask of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Msk = 0x200000 + // Bit SCLK_ACTIVE. + I2C_CLK_CONF_SCLK_ACTIVE = 0x200000 + + // COMD0: I2C command register %s + // Position of COMMAND field. + I2C_COMD_COMMAND_Pos = 0x0 + // Bit mask of COMMAND field. + I2C_COMD_COMMAND_Msk = 0x3fff + // Position of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Pos = 0x1f + // Bit mask of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Msk = 0x80000000 + // Bit COMMAND_DONE. + I2C_COMD_COMMAND_DONE = 0x80000000 + + // SCL_ST_TIME_OUT: SCL status time out register + // Position of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Msk = 0x1f + + // SCL_MAIN_ST_TIME_OUT: SCL main status time out register + // Position of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Msk = 0x1f + + // SCL_SP_CONF: Power configuration register + // Position of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Pos = 0x0 + // Bit mask of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Msk = 0x1 + // Bit SCL_RST_SLV_EN. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN = 0x1 + // Position of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Pos = 0x1 + // Bit mask of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Msk = 0x3e + // Position of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Pos = 0x6 + // Bit mask of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Msk = 0x40 + // Bit SCL_PD_EN. + I2C_SCL_SP_CONF_SCL_PD_EN = 0x40 + // Position of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Pos = 0x7 + // Bit mask of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Msk = 0x80 + // Bit SDA_PD_EN. + I2C_SCL_SP_CONF_SDA_PD_EN = 0x80 + + // DATE: Version register + // Position of DATE field. + I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2C_DATE_DATE_Msk = 0xffffffff + + // TXFIFO_START_ADDR: I2C TXFIFO base address register + // Position of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Msk = 0xffffffff + + // RXFIFO_START_ADDR: I2C RXFIFO base address register + // Position of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Msk = 0xffffffff +) + +// Constants for INTERRUPT_CORE0: Interrupt Controller (Core 0) +const ( + // MAC_INTR_MAP: register description + // Position of WIFI_MAC_INT_MAP field. + INTERRUPT_CORE0_MAC_INTR_MAP_WIFI_MAC_INT_MAP_Pos = 0x0 + // Bit mask of WIFI_MAC_INT_MAP field. + INTERRUPT_CORE0_MAC_INTR_MAP_WIFI_MAC_INT_MAP_Msk = 0x1f + + // WIFI_MAC_NMI_MAP: register description + // Position of WIFI_MAC_NMI_MAP field. + INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_WIFI_MAC_NMI_MAP_Pos = 0x0 + // Bit mask of WIFI_MAC_NMI_MAP field. + INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_WIFI_MAC_NMI_MAP_Msk = 0x1f + + // WIFI_PWR_INT_MAP: register description + // Position of WIFI_PWR_INT_MAP field. + INTERRUPT_CORE0_WIFI_PWR_INT_MAP_WIFI_PWR_INT_MAP_Pos = 0x0 + // Bit mask of WIFI_PWR_INT_MAP field. + INTERRUPT_CORE0_WIFI_PWR_INT_MAP_WIFI_PWR_INT_MAP_Msk = 0x1f + + // WIFI_BB_INT_MAP: register description + // Position of WIFI_BB_INT_MAP field. + INTERRUPT_CORE0_WIFI_BB_INT_MAP_WIFI_BB_INT_MAP_Pos = 0x0 + // Bit mask of WIFI_BB_INT_MAP field. + INTERRUPT_CORE0_WIFI_BB_INT_MAP_WIFI_BB_INT_MAP_Msk = 0x1f + + // BT_MAC_INT_MAP: register description + // Position of BT_MAC_INT_MAP field. + INTERRUPT_CORE0_BT_MAC_INT_MAP_BT_MAC_INT_MAP_Pos = 0x0 + // Bit mask of BT_MAC_INT_MAP field. + INTERRUPT_CORE0_BT_MAC_INT_MAP_BT_MAC_INT_MAP_Msk = 0x1f + + // BT_BB_INT_MAP: register description + // Position of BT_BB_INT_MAP field. + INTERRUPT_CORE0_BT_BB_INT_MAP_BT_BB_INT_MAP_Pos = 0x0 + // Bit mask of BT_BB_INT_MAP field. + INTERRUPT_CORE0_BT_BB_INT_MAP_BT_BB_INT_MAP_Msk = 0x1f + + // BT_BB_NMI_MAP: register description + // Position of BT_BB_NMI_MAP field. + INTERRUPT_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Pos = 0x0 + // Bit mask of BT_BB_NMI_MAP field. + INTERRUPT_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Msk = 0x1f + + // LP_TIMER_INT_MAP: register description + // Position of LP_TIMER_INT_MAP field. + INTERRUPT_CORE0_LP_TIMER_INT_MAP_LP_TIMER_INT_MAP_Pos = 0x0 + // Bit mask of LP_TIMER_INT_MAP field. + INTERRUPT_CORE0_LP_TIMER_INT_MAP_LP_TIMER_INT_MAP_Msk = 0x1f + + // COEX_INT_MAP: register description + // Position of COEX_INT_MAP field. + INTERRUPT_CORE0_COEX_INT_MAP_COEX_INT_MAP_Pos = 0x0 + // Bit mask of COEX_INT_MAP field. + INTERRUPT_CORE0_COEX_INT_MAP_COEX_INT_MAP_Msk = 0x1f + + // BLE_TIMER_INT_MAP: register description + // Position of BLE_TIMER_INT_MAP field. + INTERRUPT_CORE0_BLE_TIMER_INT_MAP_BLE_TIMER_INT_MAP_Pos = 0x0 + // Bit mask of BLE_TIMER_INT_MAP field. + INTERRUPT_CORE0_BLE_TIMER_INT_MAP_BLE_TIMER_INT_MAP_Msk = 0x1f + + // BLE_SEC_INT_MAP: register description + // Position of BLE_SEC_INT_MAP field. + INTERRUPT_CORE0_BLE_SEC_INT_MAP_BLE_SEC_INT_MAP_Pos = 0x0 + // Bit mask of BLE_SEC_INT_MAP field. + INTERRUPT_CORE0_BLE_SEC_INT_MAP_BLE_SEC_INT_MAP_Msk = 0x1f + + // I2C_MST_INT_MAP: register description + // Position of I2C_MST_INT_MAP field. + INTERRUPT_CORE0_I2C_MST_INT_MAP_I2C_MST_INT_MAP_Pos = 0x0 + // Bit mask of I2C_MST_INT_MAP field. + INTERRUPT_CORE0_I2C_MST_INT_MAP_I2C_MST_INT_MAP_Msk = 0x1f + + // APB_CTRL_INTR_MAP: register description + // Position of APB_CTRL_INTR_MAP field. + INTERRUPT_CORE0_APB_CTRL_INTR_MAP_APB_CTRL_INTR_MAP_Pos = 0x0 + // Bit mask of APB_CTRL_INTR_MAP field. + INTERRUPT_CORE0_APB_CTRL_INTR_MAP_APB_CTRL_INTR_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_MAP: register description + // Position of GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_NMI_MAP: register description + // Position of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Msk = 0x1f + + // SPI_INTR_1_MAP: register description + // Position of SPI_INTR_1_MAP field. + INTERRUPT_CORE0_SPI_INTR_1_MAP_SPI_INTR_1_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_1_MAP field. + INTERRUPT_CORE0_SPI_INTR_1_MAP_SPI_INTR_1_MAP_Msk = 0x1f + + // SPI_INTR_2_MAP: register description + // Position of SPI_INTR_2_MAP field. + INTERRUPT_CORE0_SPI_INTR_2_MAP_SPI_INTR_2_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_2_MAP field. + INTERRUPT_CORE0_SPI_INTR_2_MAP_SPI_INTR_2_MAP_Msk = 0x1f + + // UART_INTR_MAP: register description + // Position of UART_INTR_MAP field. + INTERRUPT_CORE0_UART_INTR_MAP_UART_INTR_MAP_Pos = 0x0 + // Bit mask of UART_INTR_MAP field. + INTERRUPT_CORE0_UART_INTR_MAP_UART_INTR_MAP_Msk = 0x1f + + // UART1_INTR_MAP: register description + // Position of UART1_INTR_MAP field. + INTERRUPT_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Pos = 0x0 + // Bit mask of UART1_INTR_MAP field. + INTERRUPT_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Msk = 0x1f + + // LEDC_INT_MAP: register description + // Position of LEDC_INT_MAP field. + INTERRUPT_CORE0_LEDC_INT_MAP_LEDC_INT_MAP_Pos = 0x0 + // Bit mask of LEDC_INT_MAP field. + INTERRUPT_CORE0_LEDC_INT_MAP_LEDC_INT_MAP_Msk = 0x1f + + // EFUSE_INT_MAP: register description + // Position of EFUSE_INT_MAP field. + INTERRUPT_CORE0_EFUSE_INT_MAP_EFUSE_INT_MAP_Pos = 0x0 + // Bit mask of EFUSE_INT_MAP field. + INTERRUPT_CORE0_EFUSE_INT_MAP_EFUSE_INT_MAP_Msk = 0x1f + + // RTC_CORE_INTR_MAP: register description + // Position of RTC_CORE_INTR_MAP field. + INTERRUPT_CORE0_RTC_CORE_INTR_MAP_RTC_CORE_INTR_MAP_Pos = 0x0 + // Bit mask of RTC_CORE_INTR_MAP field. + INTERRUPT_CORE0_RTC_CORE_INTR_MAP_RTC_CORE_INTR_MAP_Msk = 0x1f + + // I2C_EXT0_INTR_MAP: register description + // Position of I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Msk = 0x1f + + // TG_T0_INT_MAP: register description + // Position of TG_T0_INT_MAP field. + INTERRUPT_CORE0_TG_T0_INT_MAP_TG_T0_INT_MAP_Pos = 0x0 + // Bit mask of TG_T0_INT_MAP field. + INTERRUPT_CORE0_TG_T0_INT_MAP_TG_T0_INT_MAP_Msk = 0x1f + + // TG_WDT_INT_MAP: register description + // Position of TG_WDT_INT_MAP field. + INTERRUPT_CORE0_TG_WDT_INT_MAP_TG_WDT_INT_MAP_Pos = 0x0 + // Bit mask of TG_WDT_INT_MAP field. + INTERRUPT_CORE0_TG_WDT_INT_MAP_TG_WDT_INT_MAP_Msk = 0x1f + + // CACHE_IA_INT_MAP: register description + // Position of CACHE_IA_INT_MAP field. + INTERRUPT_CORE0_CACHE_IA_INT_MAP_CACHE_IA_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_IA_INT_MAP field. + INTERRUPT_CORE0_CACHE_IA_INT_MAP_CACHE_IA_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET0_INT_MAP: register description + // Position of SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_SYSTIMER_TARGET0_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_SYSTIMER_TARGET0_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET1_INT_MAP: register description + // Position of SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_SYSTIMER_TARGET1_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_SYSTIMER_TARGET1_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET2_INT_MAP: register description + // Position of SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_SYSTIMER_TARGET2_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_SYSTIMER_TARGET2_INT_MAP_Msk = 0x1f + + // SPI_MEM_REJECT_INTR_MAP: register description + // Position of SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_SPI_MEM_REJECT_INTR_MAP_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_SPI_MEM_REJECT_INTR_MAP_Msk = 0x1f + + // ICACHE_PRELOAD_INT_MAP: register description + // Position of ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_ICACHE_PRELOAD_INT_MAP_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_ICACHE_PRELOAD_INT_MAP_Msk = 0x1f + + // ICACHE_SYNC_INT_MAP: register description + // Position of ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_ICACHE_SYNC_INT_MAP_Pos = 0x0 + // Bit mask of ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_ICACHE_SYNC_INT_MAP_Msk = 0x1f + + // APB_ADC_INT_MAP: register description + // Position of APB_ADC_INT_MAP field. + INTERRUPT_CORE0_APB_ADC_INT_MAP_APB_ADC_INT_MAP_Pos = 0x0 + // Bit mask of APB_ADC_INT_MAP field. + INTERRUPT_CORE0_APB_ADC_INT_MAP_APB_ADC_INT_MAP_Msk = 0x1f + + // DMA_CH0_INT_MAP: register description + // Position of DMA_CH0_INT_MAP field. + INTERRUPT_CORE0_DMA_CH0_INT_MAP_DMA_CH0_INT_MAP_Pos = 0x0 + // Bit mask of DMA_CH0_INT_MAP field. + INTERRUPT_CORE0_DMA_CH0_INT_MAP_DMA_CH0_INT_MAP_Msk = 0x1f + + // SHA_INT_MAP: register description + // Position of SHA_INT_MAP field. + INTERRUPT_CORE0_SHA_INT_MAP_SHA_INT_MAP_Pos = 0x0 + // Bit mask of SHA_INT_MAP field. + INTERRUPT_CORE0_SHA_INT_MAP_SHA_INT_MAP_Msk = 0x1f + + // ECC_INT_MAP: register description + // Position of ECC_INT_MAP field. + INTERRUPT_CORE0_ECC_INT_MAP_ECC_INT_MAP_Pos = 0x0 + // Bit mask of ECC_INT_MAP field. + INTERRUPT_CORE0_ECC_INT_MAP_ECC_INT_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_0_MAP: register description + // Position of CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_1_MAP: register description + // Position of CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_2_MAP: register description + // Position of CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_3_MAP: register description + // Position of CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Msk = 0x1f + + // ASSIST_DEBUG_INTR_MAP: register description + // Position of ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Pos = 0x0 + // Bit mask of ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Msk = 0x1f + + // CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: register description + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Msk = 0x1f + + // CACHE_CORE0_ACS_INT_MAP: register description + // Position of CACHE_CORE0_ACS_INT_MAP field. + INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_CACHE_CORE0_ACS_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_CORE0_ACS_INT_MAP field. + INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_CACHE_CORE0_ACS_INT_MAP_Msk = 0x1f + + // INTR_STATUS_REG_0: register description + // Position of INTR_STATUS_0 field. + INTERRUPT_CORE0_INTR_STATUS_REG_0_INTR_STATUS_0_Pos = 0x0 + // Bit mask of INTR_STATUS_0 field. + INTERRUPT_CORE0_INTR_STATUS_REG_0_INTR_STATUS_0_Msk = 0xffffffff + + // INTR_STATUS_REG_1: register description + // Position of INTR_STATUS_1 field. + INTERRUPT_CORE0_INTR_STATUS_REG_1_INTR_STATUS_1_Pos = 0x0 + // Bit mask of INTR_STATUS_1 field. + INTERRUPT_CORE0_INTR_STATUS_REG_1_INTR_STATUS_1_Msk = 0xffffffff + + // CLOCK_GATE: register description + // Position of REG_CLK_EN field. + INTERRUPT_CORE0_CLOCK_GATE_REG_CLK_EN_Pos = 0x0 + // Bit mask of REG_CLK_EN field. + INTERRUPT_CORE0_CLOCK_GATE_REG_CLK_EN_Msk = 0x1 + // Bit REG_CLK_EN. + INTERRUPT_CORE0_CLOCK_GATE_REG_CLK_EN = 0x1 + + // CPU_INT_ENABLE: register description + // Position of CPU_INT_ENABLE field. + INTERRUPT_CORE0_CPU_INT_ENABLE_CPU_INT_ENABLE_Pos = 0x0 + // Bit mask of CPU_INT_ENABLE field. + INTERRUPT_CORE0_CPU_INT_ENABLE_CPU_INT_ENABLE_Msk = 0xffffffff + + // CPU_INT_TYPE: register description + // Position of CPU_INT_TYPE field. + INTERRUPT_CORE0_CPU_INT_TYPE_CPU_INT_TYPE_Pos = 0x0 + // Bit mask of CPU_INT_TYPE field. + INTERRUPT_CORE0_CPU_INT_TYPE_CPU_INT_TYPE_Msk = 0xffffffff + + // CPU_INT_CLEAR: register description + // Position of CPU_INT_CLEAR field. + INTERRUPT_CORE0_CPU_INT_CLEAR_CPU_INT_CLEAR_Pos = 0x0 + // Bit mask of CPU_INT_CLEAR field. + INTERRUPT_CORE0_CPU_INT_CLEAR_CPU_INT_CLEAR_Msk = 0xffffffff + + // CPU_INT_EIP_STATUS: register description + // Position of CPU_INT_EIP_STATUS field. + INTERRUPT_CORE0_CPU_INT_EIP_STATUS_CPU_INT_EIP_STATUS_Pos = 0x0 + // Bit mask of CPU_INT_EIP_STATUS field. + INTERRUPT_CORE0_CPU_INT_EIP_STATUS_CPU_INT_EIP_STATUS_Msk = 0xffffffff + + // CPU_INT_PRI_0: register description + // Position of CPU_PRI_0_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_0_CPU_PRI_0_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_0_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_0_CPU_PRI_0_MAP_Msk = 0xf + + // CPU_INT_PRI_1: register description + // Position of CPU_PRI_1_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_1_CPU_PRI_1_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_1_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_1_CPU_PRI_1_MAP_Msk = 0xf + + // CPU_INT_PRI_2: register description + // Position of CPU_PRI_2_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_2_CPU_PRI_2_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_2_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_2_CPU_PRI_2_MAP_Msk = 0xf + + // CPU_INT_PRI_3: register description + // Position of CPU_PRI_3_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_3_CPU_PRI_3_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_3_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_3_CPU_PRI_3_MAP_Msk = 0xf + + // CPU_INT_PRI_4: register description + // Position of CPU_PRI_4_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_4_CPU_PRI_4_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_4_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_4_CPU_PRI_4_MAP_Msk = 0xf + + // CPU_INT_PRI_5: register description + // Position of CPU_PRI_5_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_5_CPU_PRI_5_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_5_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_5_CPU_PRI_5_MAP_Msk = 0xf + + // CPU_INT_PRI_6: register description + // Position of CPU_PRI_6_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_6_CPU_PRI_6_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_6_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_6_CPU_PRI_6_MAP_Msk = 0xf + + // CPU_INT_PRI_7: register description + // Position of CPU_PRI_7_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_7_CPU_PRI_7_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_7_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_7_CPU_PRI_7_MAP_Msk = 0xf + + // CPU_INT_PRI_8: register description + // Position of CPU_PRI_8_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_8_CPU_PRI_8_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_8_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_8_CPU_PRI_8_MAP_Msk = 0xf + + // CPU_INT_PRI_9: register description + // Position of CPU_PRI_9_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_9_CPU_PRI_9_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_9_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_9_CPU_PRI_9_MAP_Msk = 0xf + + // CPU_INT_PRI_10: register description + // Position of CPU_PRI_10_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_10_CPU_PRI_10_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_10_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_10_CPU_PRI_10_MAP_Msk = 0xf + + // CPU_INT_PRI_11: register description + // Position of CPU_PRI_11_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_11_CPU_PRI_11_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_11_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_11_CPU_PRI_11_MAP_Msk = 0xf + + // CPU_INT_PRI_12: register description + // Position of CPU_PRI_12_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_12_CPU_PRI_12_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_12_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_12_CPU_PRI_12_MAP_Msk = 0xf + + // CPU_INT_PRI_13: register description + // Position of CPU_PRI_13_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_13_CPU_PRI_13_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_13_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_13_CPU_PRI_13_MAP_Msk = 0xf + + // CPU_INT_PRI_14: register description + // Position of CPU_PRI_14_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_14_CPU_PRI_14_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_14_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_14_CPU_PRI_14_MAP_Msk = 0xf + + // CPU_INT_PRI_15: register description + // Position of CPU_PRI_15_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_15_CPU_PRI_15_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_15_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_15_CPU_PRI_15_MAP_Msk = 0xf + + // CPU_INT_PRI_16: register description + // Position of CPU_PRI_16_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_16_CPU_PRI_16_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_16_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_16_CPU_PRI_16_MAP_Msk = 0xf + + // CPU_INT_PRI_17: register description + // Position of CPU_PRI_17_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_17_CPU_PRI_17_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_17_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_17_CPU_PRI_17_MAP_Msk = 0xf + + // CPU_INT_PRI_18: register description + // Position of CPU_PRI_18_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_18_CPU_PRI_18_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_18_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_18_CPU_PRI_18_MAP_Msk = 0xf + + // CPU_INT_PRI_19: register description + // Position of CPU_PRI_19_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_19_CPU_PRI_19_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_19_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_19_CPU_PRI_19_MAP_Msk = 0xf + + // CPU_INT_PRI_20: register description + // Position of CPU_PRI_20_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_20_CPU_PRI_20_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_20_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_20_CPU_PRI_20_MAP_Msk = 0xf + + // CPU_INT_PRI_21: register description + // Position of CPU_PRI_21_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_21_CPU_PRI_21_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_21_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_21_CPU_PRI_21_MAP_Msk = 0xf + + // CPU_INT_PRI_22: register description + // Position of CPU_PRI_22_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_22_CPU_PRI_22_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_22_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_22_CPU_PRI_22_MAP_Msk = 0xf + + // CPU_INT_PRI_23: register description + // Position of CPU_PRI_23_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_23_CPU_PRI_23_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_23_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_23_CPU_PRI_23_MAP_Msk = 0xf + + // CPU_INT_PRI_24: register description + // Position of CPU_PRI_24_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_24_CPU_PRI_24_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_24_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_24_CPU_PRI_24_MAP_Msk = 0xf + + // CPU_INT_PRI_25: register description + // Position of CPU_PRI_25_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_25_CPU_PRI_25_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_25_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_25_CPU_PRI_25_MAP_Msk = 0xf + + // CPU_INT_PRI_26: register description + // Position of CPU_PRI_26_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_26_CPU_PRI_26_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_26_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_26_CPU_PRI_26_MAP_Msk = 0xf + + // CPU_INT_PRI_27: register description + // Position of CPU_PRI_27_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_27_CPU_PRI_27_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_27_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_27_CPU_PRI_27_MAP_Msk = 0xf + + // CPU_INT_PRI_28: register description + // Position of CPU_PRI_28_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_28_CPU_PRI_28_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_28_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_28_CPU_PRI_28_MAP_Msk = 0xf + + // CPU_INT_PRI_29: register description + // Position of CPU_PRI_29_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_29_CPU_PRI_29_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_29_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_29_CPU_PRI_29_MAP_Msk = 0xf + + // CPU_INT_PRI_30: register description + // Position of CPU_PRI_30_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_30_CPU_PRI_30_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_30_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_30_CPU_PRI_30_MAP_Msk = 0xf + + // CPU_INT_PRI_31: register description + // Position of CPU_PRI_31_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_31_CPU_PRI_31_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_31_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_31_CPU_PRI_31_MAP_Msk = 0xf + + // CPU_INT_THRESH: register description + // Position of CPU_INT_THRESH field. + INTERRUPT_CORE0_CPU_INT_THRESH_CPU_INT_THRESH_Pos = 0x0 + // Bit mask of CPU_INT_THRESH field. + INTERRUPT_CORE0_CPU_INT_THRESH_CPU_INT_THRESH_Msk = 0xf + + // INTERRUPT_REG_DATE: register description + // Position of INTERRUPT_REG_DATE field. + INTERRUPT_CORE0_INTERRUPT_REG_DATE_INTERRUPT_REG_DATE_Pos = 0x0 + // Bit mask of INTERRUPT_REG_DATE field. + INTERRUPT_CORE0_INTERRUPT_REG_DATE_INTERRUPT_REG_DATE_Msk = 0xfffffff +) + +// Constants for IO_MUX: Input/Output Multiplexer +const ( + // PIN_CTRL: Clock Output Configuration Register + // Position of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Pos = 0x0 + // Bit mask of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Msk = 0xf + // Position of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Pos = 0x4 + // Bit mask of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Msk = 0xf0 + // Position of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Pos = 0x8 + // Bit mask of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Msk = 0xf00 + + // GPIO0: IO MUX Configure Register for pad XTAL_32K_P + // Position of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO_FILTER_EN = 0x8000 + + // DATE: IO MUX Version Control Register + // Position of REG_DATE field. + IO_MUX_DATE_REG_DATE_Pos = 0x0 + // Bit mask of REG_DATE field. + IO_MUX_DATE_REG_DATE_Msk = 0xfffffff +) + +// Constants for LEDC: LED Control PWM (Pulse Width Modulation) +const ( + // CH0_CONF0: Configuration register 0 for channel %s + // Position of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Pos = 0x0 + // Bit mask of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Msk = 0x3 + // Position of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Pos = 0x2 + // Bit mask of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Msk = 0x4 + // Bit SIG_OUT_EN. + LEDC_CH_CONF0_SIG_OUT_EN = 0x4 + // Position of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Pos = 0x3 + // Bit mask of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Msk = 0x8 + // Bit IDLE_LV. + LEDC_CH_CONF0_IDLE_LV = 0x8 + // Position of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Pos = 0x4 + // Bit mask of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Msk = 0x10 + // Bit PARA_UP. + LEDC_CH_CONF0_PARA_UP = 0x10 + // Position of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Pos = 0x5 + // Bit mask of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Msk = 0x7fe0 + // Position of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Pos = 0xf + // Bit mask of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Msk = 0x8000 + // Bit OVF_CNT_EN. + LEDC_CH_CONF0_OVF_CNT_EN = 0x8000 + // Position of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Pos = 0x10 + // Bit mask of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Msk = 0x10000 + // Bit OVF_CNT_RESET. + LEDC_CH_CONF0_OVF_CNT_RESET = 0x10000 + + // CH0_HPOINT: High point register for channel %s + // Position of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Pos = 0x0 + // Bit mask of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Msk = 0x3fff + + // CH0_DUTY: Initial duty cycle for channel %s + // Position of DUTY field. + LEDC_CH_DUTY_DUTY_Pos = 0x0 + // Bit mask of DUTY field. + LEDC_CH_DUTY_DUTY_Msk = 0x7ffff + + // CH0_CONF1: Configuration register 1 for channel %s + // Position of DUTY_SCALE field. + LEDC_CH_CONF1_DUTY_SCALE_Pos = 0x0 + // Bit mask of DUTY_SCALE field. + LEDC_CH_CONF1_DUTY_SCALE_Msk = 0x3ff + // Position of DUTY_CYCLE field. + LEDC_CH_CONF1_DUTY_CYCLE_Pos = 0xa + // Bit mask of DUTY_CYCLE field. + LEDC_CH_CONF1_DUTY_CYCLE_Msk = 0xffc00 + // Position of DUTY_NUM field. + LEDC_CH_CONF1_DUTY_NUM_Pos = 0x14 + // Bit mask of DUTY_NUM field. + LEDC_CH_CONF1_DUTY_NUM_Msk = 0x3ff00000 + // Position of DUTY_INC field. + LEDC_CH_CONF1_DUTY_INC_Pos = 0x1e + // Bit mask of DUTY_INC field. + LEDC_CH_CONF1_DUTY_INC_Msk = 0x40000000 + // Bit DUTY_INC. + LEDC_CH_CONF1_DUTY_INC = 0x40000000 + // Position of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Pos = 0x1f + // Bit mask of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Msk = 0x80000000 + // Bit DUTY_START. + LEDC_CH_CONF1_DUTY_START = 0x80000000 + + // CH0_DUTY_R: Current duty cycle for channel %s + // Position of DUTY_CH0_R field. + LEDC_CH_DUTY_R_DUTY_CH0_R_Pos = 0x0 + // Bit mask of DUTY_CH0_R field. + LEDC_CH_DUTY_R_DUTY_CH0_R_Msk = 0x7ffff + + // TIMER0_CONF: Timer %s configuration + // Position of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Pos = 0x0 + // Bit mask of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Msk = 0xf + // Position of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Pos = 0x4 + // Bit mask of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Msk = 0x3ffff0 + // Position of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Pos = 0x16 + // Bit mask of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Msk = 0x400000 + // Bit PAUSE. + LEDC_TIMER_CONF_PAUSE = 0x400000 + // Position of RST field. + LEDC_TIMER_CONF_RST_Pos = 0x17 + // Bit mask of RST field. + LEDC_TIMER_CONF_RST_Msk = 0x800000 + // Bit RST. + LEDC_TIMER_CONF_RST = 0x800000 + // Position of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Pos = 0x18 + // Bit mask of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Msk = 0x1000000 + // Bit TICK_SEL. + LEDC_TIMER_CONF_TICK_SEL = 0x1000000 + // Position of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Pos = 0x19 + // Bit mask of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Msk = 0x2000000 + // Bit PARA_UP. + LEDC_TIMER_CONF_PARA_UP = 0x2000000 + + // TIMER0_VALUE: Timer %s current counter value + // Position of CNT field. + LEDC_TIMER_VALUE_CNT_Pos = 0x0 + // Bit mask of CNT field. + LEDC_TIMER_VALUE_CNT_Msk = 0x3fff + + // INT_RAW: Raw interrupt status + // Position of OVF_INT_RAW field. + LEDC_INT_RAW_OVF_INT_RAW_Pos = 0x0 + // Bit mask of OVF_INT_RAW field. + LEDC_INT_RAW_OVF_INT_RAW_Msk = 0x1 + // Bit OVF_INT_RAW. + LEDC_INT_RAW_OVF_INT_RAW = 0x1 + // Position of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Msk = 0x2 + // Bit TIMER1_OVF_INT_RAW. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW = 0x2 + // Position of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Msk = 0x4 + // Bit TIMER2_OVF_INT_RAW. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW = 0x4 + // Position of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Msk = 0x8 + // Bit TIMER3_OVF_INT_RAW. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW = 0x200 + // Position of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Pos = 0xa + // Bit mask of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Msk = 0x400 + // Bit OVF_CNT_CH0_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW = 0x400 + // Position of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Pos = 0xb + // Bit mask of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Msk = 0x800 + // Bit OVF_CNT_CH1_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW = 0x800 + // Position of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Pos = 0xc + // Bit mask of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Msk = 0x1000 + // Bit OVF_CNT_CH2_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW = 0x1000 + // Position of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Pos = 0xd + // Bit mask of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Msk = 0x2000 + // Bit OVF_CNT_CH3_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW = 0x2000 + // Position of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Pos = 0xe + // Bit mask of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Msk = 0x4000 + // Bit OVF_CNT_CH4_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW = 0x4000 + // Position of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Pos = 0xf + // Bit mask of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Msk = 0x8000 + // Bit OVF_CNT_CH5_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW = 0x8000 + + // INT_ST: Masked interrupt status + // Position of OVF_INT_ST field. + LEDC_INT_ST_OVF_INT_ST_Pos = 0x0 + // Bit mask of OVF_INT_ST field. + LEDC_INT_ST_OVF_INT_ST_Msk = 0x1 + // Bit OVF_INT_ST. + LEDC_INT_ST_OVF_INT_ST = 0x1 + // Position of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Msk = 0x2 + // Bit TIMER1_OVF_INT_ST. + LEDC_INT_ST_TIMER1_OVF_INT_ST = 0x2 + // Position of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Msk = 0x4 + // Bit TIMER2_OVF_INT_ST. + LEDC_INT_ST_TIMER2_OVF_INT_ST = 0x4 + // Position of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Msk = 0x8 + // Bit TIMER3_OVF_INT_ST. + LEDC_INT_ST_TIMER3_OVF_INT_ST = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST = 0x200 + // Position of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Pos = 0xa + // Bit mask of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Msk = 0x400 + // Bit OVF_CNT_CH0_INT_ST. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST = 0x400 + // Position of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Pos = 0xb + // Bit mask of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Msk = 0x800 + // Bit OVF_CNT_CH1_INT_ST. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST = 0x800 + // Position of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Pos = 0xc + // Bit mask of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Msk = 0x1000 + // Bit OVF_CNT_CH2_INT_ST. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST = 0x1000 + // Position of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Pos = 0xd + // Bit mask of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Msk = 0x2000 + // Bit OVF_CNT_CH3_INT_ST. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST = 0x2000 + // Position of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Pos = 0xe + // Bit mask of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Msk = 0x4000 + // Bit OVF_CNT_CH4_INT_ST. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST = 0x4000 + // Position of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Pos = 0xf + // Bit mask of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Msk = 0x8000 + // Bit OVF_CNT_CH5_INT_ST. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST = 0x8000 + + // INT_ENA: Interrupt enable bits + // Position of OVF_INT_ENA field. + LEDC_INT_ENA_OVF_INT_ENA_Pos = 0x0 + // Bit mask of OVF_INT_ENA field. + LEDC_INT_ENA_OVF_INT_ENA_Msk = 0x1 + // Bit OVF_INT_ENA. + LEDC_INT_ENA_OVF_INT_ENA = 0x1 + // Position of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Msk = 0x2 + // Bit TIMER1_OVF_INT_ENA. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA = 0x2 + // Position of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Msk = 0x4 + // Bit TIMER2_OVF_INT_ENA. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA = 0x4 + // Position of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Msk = 0x8 + // Bit TIMER3_OVF_INT_ENA. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA = 0x200 + // Position of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Pos = 0xa + // Bit mask of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Msk = 0x400 + // Bit OVF_CNT_CH0_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA = 0x400 + // Position of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Pos = 0xb + // Bit mask of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Msk = 0x800 + // Bit OVF_CNT_CH1_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA = 0x800 + // Position of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Pos = 0xc + // Bit mask of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Msk = 0x1000 + // Bit OVF_CNT_CH2_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA = 0x1000 + // Position of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Pos = 0xd + // Bit mask of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Msk = 0x2000 + // Bit OVF_CNT_CH3_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA = 0x2000 + // Position of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Pos = 0xe + // Bit mask of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Msk = 0x4000 + // Bit OVF_CNT_CH4_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA = 0x4000 + // Position of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Pos = 0xf + // Bit mask of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Msk = 0x8000 + // Bit OVF_CNT_CH5_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA = 0x8000 + + // INT_CLR: Interrupt clear bits + // Position of OVF_INT_CLR field. + LEDC_INT_CLR_OVF_INT_CLR_Pos = 0x0 + // Bit mask of OVF_INT_CLR field. + LEDC_INT_CLR_OVF_INT_CLR_Msk = 0x1 + // Bit OVF_INT_CLR. + LEDC_INT_CLR_OVF_INT_CLR = 0x1 + // Position of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Msk = 0x2 + // Bit TIMER1_OVF_INT_CLR. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR = 0x2 + // Position of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Msk = 0x4 + // Bit TIMER2_OVF_INT_CLR. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR = 0x4 + // Position of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Msk = 0x8 + // Bit TIMER3_OVF_INT_CLR. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR = 0x200 + // Position of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Pos = 0xa + // Bit mask of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Msk = 0x400 + // Bit OVF_CNT_CH0_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR = 0x400 + // Position of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Pos = 0xb + // Bit mask of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Msk = 0x800 + // Bit OVF_CNT_CH1_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR = 0x800 + // Position of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Pos = 0xc + // Bit mask of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Msk = 0x1000 + // Bit OVF_CNT_CH2_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR = 0x1000 + // Position of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Pos = 0xd + // Bit mask of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Msk = 0x2000 + // Bit OVF_CNT_CH3_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR = 0x2000 + // Position of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Pos = 0xe + // Bit mask of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Msk = 0x4000 + // Bit OVF_CNT_CH4_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR = 0x4000 + // Position of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Pos = 0xf + // Bit mask of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Msk = 0x8000 + // Bit OVF_CNT_CH5_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR = 0x8000 + + // CONF: Global ledc configuration register + // Position of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Pos = 0x0 + // Bit mask of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Msk = 0x3 + // Position of CLK_EN field. + LEDC_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LEDC_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LEDC_CONF_CLK_EN = 0x80000000 + + // DATE: Version control register + // Position of LEDC_DATE field. + LEDC_DATE_LEDC_DATE_Pos = 0x0 + // Bit mask of LEDC_DATE field. + LEDC_DATE_LEDC_DATE_Msk = 0xffffffff +) + +// Constants for MODEM_CLKRST: MODEM_CLKRST Peripheral +const ( + // CLK_CONF + // Position of CLK_EN field. + MODEM_CLKRST_CLK_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + MODEM_CLKRST_CLK_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + MODEM_CLKRST_CLK_CONF_CLK_EN = 0x1 + + // MODEM_LP_TIMER_CONF + // Position of LP_TIMER_SEL_RTC_SLOW field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_RTC_SLOW_Pos = 0x0 + // Bit mask of LP_TIMER_SEL_RTC_SLOW field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_RTC_SLOW_Msk = 0x1 + // Bit LP_TIMER_SEL_RTC_SLOW. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_RTC_SLOW = 0x1 + // Position of LP_TIMER_SEL_8M field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_8M_Pos = 0x1 + // Bit mask of LP_TIMER_SEL_8M field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_8M_Msk = 0x2 + // Bit LP_TIMER_SEL_8M. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_8M = 0x2 + // Position of LP_TIMER_SEL_XTAL field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL_Pos = 0x2 + // Bit mask of LP_TIMER_SEL_XTAL field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL_Msk = 0x4 + // Bit LP_TIMER_SEL_XTAL. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL = 0x4 + // Position of LP_TIMER_SEL_XTAL32K field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL32K_Pos = 0x3 + // Bit mask of LP_TIMER_SEL_XTAL32K field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL32K_Msk = 0x8 + // Bit LP_TIMER_SEL_XTAL32K. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_SEL_XTAL32K = 0x8 + // Position of LP_TIMER_CLK_DIV_NUM field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_CLK_DIV_NUM_Pos = 0x4 + // Bit mask of LP_TIMER_CLK_DIV_NUM field. + MODEM_CLKRST_MODEM_LP_TIMER_CONF_LP_TIMER_CLK_DIV_NUM_Msk = 0xff0 + + // COEX_LP_CLK_CONF + // Position of COEX_LPCLK_SEL_RTC_SLOW field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_RTC_SLOW_Pos = 0x0 + // Bit mask of COEX_LPCLK_SEL_RTC_SLOW field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_RTC_SLOW_Msk = 0x1 + // Bit COEX_LPCLK_SEL_RTC_SLOW. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_RTC_SLOW = 0x1 + // Position of COEX_LPCLK_SEL_8M field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_8M_Pos = 0x1 + // Bit mask of COEX_LPCLK_SEL_8M field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_8M_Msk = 0x2 + // Bit COEX_LPCLK_SEL_8M. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_8M = 0x2 + // Position of COEX_LPCLK_SEL_XTAL field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL_Pos = 0x2 + // Bit mask of COEX_LPCLK_SEL_XTAL field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL_Msk = 0x4 + // Bit COEX_LPCLK_SEL_XTAL. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL = 0x4 + // Position of COEX_LPCLK_SEL_XTAL32K field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL32K_Pos = 0x3 + // Bit mask of COEX_LPCLK_SEL_XTAL32K field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL32K_Msk = 0x8 + // Bit COEX_LPCLK_SEL_XTAL32K. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_SEL_XTAL32K = 0x8 + // Position of COEX_LPCLK_DIV_NUM field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_DIV_NUM_Pos = 0x4 + // Bit mask of COEX_LPCLK_DIV_NUM field. + MODEM_CLKRST_COEX_LP_CLK_CONF_COEX_LPCLK_DIV_NUM_Msk = 0xff0 + + // BLE_TIMER_CLK_CONF + // Position of BLETIMER_USE_XTAL field. + MODEM_CLKRST_BLE_TIMER_CLK_CONF_BLETIMER_USE_XTAL_Pos = 0x0 + // Bit mask of BLETIMER_USE_XTAL field. + MODEM_CLKRST_BLE_TIMER_CLK_CONF_BLETIMER_USE_XTAL_Msk = 0x1 + // Bit BLETIMER_USE_XTAL. + MODEM_CLKRST_BLE_TIMER_CLK_CONF_BLETIMER_USE_XTAL = 0x1 + // Position of BLETIMER_CLK_IS_ACTIVE field. + MODEM_CLKRST_BLE_TIMER_CLK_CONF_BLETIMER_CLK_IS_ACTIVE_Pos = 0x1 + // Bit mask of BLETIMER_CLK_IS_ACTIVE field. + MODEM_CLKRST_BLE_TIMER_CLK_CONF_BLETIMER_CLK_IS_ACTIVE_Msk = 0x2 + // Bit BLETIMER_CLK_IS_ACTIVE. + MODEM_CLKRST_BLE_TIMER_CLK_CONF_BLETIMER_CLK_IS_ACTIVE = 0x2 + + // DATE + // Position of DATE field. + MODEM_CLKRST_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + MODEM_CLKRST_DATE_DATE_Msk = 0xfffffff + + // ETM_CLK_CONF + // Position of ETM_CLK_SEL field. + MODEM_CLKRST_ETM_CLK_CONF_ETM_CLK_SEL_Pos = 0x0 + // Bit mask of ETM_CLK_SEL field. + MODEM_CLKRST_ETM_CLK_CONF_ETM_CLK_SEL_Msk = 0x1 + // Bit ETM_CLK_SEL. + MODEM_CLKRST_ETM_CLK_CONF_ETM_CLK_SEL = 0x1 + // Position of ETM_CLK_ACTIVE field. + MODEM_CLKRST_ETM_CLK_CONF_ETM_CLK_ACTIVE_Pos = 0x1 + // Bit mask of ETM_CLK_ACTIVE field. + MODEM_CLKRST_ETM_CLK_CONF_ETM_CLK_ACTIVE_Msk = 0x2 + // Bit ETM_CLK_ACTIVE. + MODEM_CLKRST_ETM_CLK_CONF_ETM_CLK_ACTIVE = 0x2 +) + +// Constants for RNG: Hardware Random Number Generator +const () + +// Constants for RTC_CNTL: Real-Time Clock Control +const ( + // OPTIONS0: register description + // Position of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Pos = 0x2 + // Bit mask of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Msk = 0xc + // Position of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Pos = 0x5 + // Bit mask of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Msk = 0x20 + // Bit SW_PROCPU_RST. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST = 0x20 + // Position of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Pos = 0x6 + // Bit mask of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Msk = 0x40 + // Bit BB_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD = 0x40 + // Position of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Pos = 0x7 + // Bit mask of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Msk = 0x80 + // Bit BB_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU = 0x80 + // Position of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Pos = 0x8 + // Bit mask of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Msk = 0x100 + // Bit BBPLL_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD = 0x100 + // Position of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Pos = 0x9 + // Bit mask of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Msk = 0x200 + // Bit BBPLL_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU = 0x200 + // Position of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Pos = 0xa + // Bit mask of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Msk = 0x400 + // Bit BBPLL_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD = 0x400 + // Position of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Pos = 0xb + // Bit mask of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Msk = 0x800 + // Bit BBPLL_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU = 0x800 + // Position of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Pos = 0xc + // Bit mask of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Msk = 0x1000 + // Bit XTL_FORCE_PD. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD = 0x1000 + // Position of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Pos = 0xd + // Bit mask of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Msk = 0x2000 + // Bit XTL_FORCE_PU. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU = 0x2000 + // Position of XTL_EN_WAIT field. + RTC_CNTL_OPTIONS0_XTL_EN_WAIT_Pos = 0xe + // Bit mask of XTL_EN_WAIT field. + RTC_CNTL_OPTIONS0_XTL_EN_WAIT_Msk = 0x3c000 + // Position of XTL_EXT_CTR_SEL field. + RTC_CNTL_OPTIONS0_XTL_EXT_CTR_SEL_Pos = 0x14 + // Bit mask of XTL_EXT_CTR_SEL field. + RTC_CNTL_OPTIONS0_XTL_EXT_CTR_SEL_Msk = 0x700000 + // Position of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Pos = 0x19 + // Bit mask of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Msk = 0x2000000 + // Bit ANALOG_FORCE_ISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO = 0x2000000 + // Position of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Pos = 0x1c + // Bit mask of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Msk = 0x10000000 + // Bit ANALOG_FORCE_NOISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO = 0x10000000 + // Position of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Pos = 0x1d + // Bit mask of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Msk = 0x20000000 + // Bit DG_WRAP_FORCE_RST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST = 0x20000000 + // Position of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_NORST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST = 0x40000000 + // Position of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Pos = 0x1f + // Bit mask of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Msk = 0x80000000 + // Bit SW_SYS_RST. + RTC_CNTL_OPTIONS0_SW_SYS_RST = 0x80000000 + + // SLP_TIMER0: register description + // Position of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Pos = 0x0 + // Bit mask of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Msk = 0xffffffff + + // SLP_TIMER1: register description + // Position of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Pos = 0x0 + // Bit mask of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Msk = 0xffff + // Position of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Pos = 0x10 + // Bit mask of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Msk = 0x10000 + // Bit MAIN_TIMER_ALARM_EN. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN = 0x10000 + + // TIME_UPDATE: register description + // Position of TIMER_SYS_STALL field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL_Pos = 0x1b + // Bit mask of TIMER_SYS_STALL field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL_Msk = 0x8000000 + // Bit TIMER_SYS_STALL. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL = 0x8000000 + // Position of TIMER_XTL_OFF field. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF_Pos = 0x1c + // Bit mask of TIMER_XTL_OFF field. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF_Msk = 0x10000000 + // Bit TIMER_XTL_OFF. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF = 0x10000000 + // Position of TIMER_SYS_RST field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST_Pos = 0x1d + // Bit mask of TIMER_SYS_RST field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST_Msk = 0x20000000 + // Bit TIMER_SYS_RST. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST = 0x20000000 + // Position of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Pos = 0x1f + // Bit mask of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Msk = 0x80000000 + // Bit TIME_UPDATE. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE = 0x80000000 + + // TIME_LOW0: register description + // Position of TIMER_VALUE0_LOW field. + RTC_CNTL_TIME_LOW0_TIMER_VALUE0_LOW_Pos = 0x0 + // Bit mask of TIMER_VALUE0_LOW field. + RTC_CNTL_TIME_LOW0_TIMER_VALUE0_LOW_Msk = 0xffffffff + + // TIME_HIGH0: register description + // Position of TIMER_VALUE0_HIGH field. + RTC_CNTL_TIME_HIGH0_TIMER_VALUE0_HIGH_Pos = 0x0 + // Bit mask of TIMER_VALUE0_HIGH field. + RTC_CNTL_TIME_HIGH0_TIMER_VALUE0_HIGH_Msk = 0xffff + + // STATE0: register description + // Position of SW_CPU_INT field. + RTC_CNTL_STATE0_SW_CPU_INT_Pos = 0x0 + // Bit mask of SW_CPU_INT field. + RTC_CNTL_STATE0_SW_CPU_INT_Msk = 0x1 + // Bit SW_CPU_INT. + RTC_CNTL_STATE0_SW_CPU_INT = 0x1 + // Position of SLP_REJECT_CAUSE_CLR field. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR_Pos = 0x1 + // Bit mask of SLP_REJECT_CAUSE_CLR field. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR_Msk = 0x2 + // Bit SLP_REJECT_CAUSE_CLR. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR = 0x2 + // Position of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Pos = 0x16 + // Bit mask of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Msk = 0x400000 + // Bit APB2RTC_BRIDGE_SEL. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL = 0x400000 + // Position of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Pos = 0x1c + // Bit mask of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Msk = 0x10000000 + // Bit SDIO_ACTIVE_IND. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND = 0x10000000 + // Position of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Pos = 0x1d + // Bit mask of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Msk = 0x20000000 + // Bit SLP_WAKEUP. + RTC_CNTL_STATE0_SLP_WAKEUP = 0x20000000 + // Position of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Pos = 0x1e + // Bit mask of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Msk = 0x40000000 + // Bit SLP_REJECT. + RTC_CNTL_STATE0_SLP_REJECT = 0x40000000 + // Position of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Pos = 0x1f + // Bit mask of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Msk = 0x80000000 + // Bit SLEEP_EN. + RTC_CNTL_STATE0_SLEEP_EN = 0x80000000 + + // TIMER1: register description + // Position of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Pos = 0x0 + // Bit mask of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Msk = 0x1 + // Bit CPU_STALL_EN. + RTC_CNTL_TIMER1_CPU_STALL_EN = 0x1 + // Position of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Pos = 0x1 + // Bit mask of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Msk = 0x3e + // Position of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Pos = 0x6 + // Bit mask of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Msk = 0x3fc0 + // Position of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Pos = 0xe + // Bit mask of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Msk = 0xffc000 + // Position of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Pos = 0x18 + // Bit mask of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Msk = 0xff000000 + + // TIMER2: register description + // Position of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Pos = 0x18 + // Bit mask of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Msk = 0xff000000 + + // TIMER4: register description + // Position of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Pos = 0x10 + // Bit mask of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Msk = 0x1ff0000 + // Position of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Pos = 0x19 + // Bit mask of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER5: register description + // Position of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Pos = 0x8 + // Bit mask of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Msk = 0xff00 + + // ANA_CONF: register description + // Position of I2C_RESET_POR_FORCE_PD field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PD_Pos = 0x12 + // Bit mask of I2C_RESET_POR_FORCE_PD field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PD_Msk = 0x40000 + // Bit I2C_RESET_POR_FORCE_PD. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PD = 0x40000 + // Position of I2C_RESET_POR_FORCE_PU field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PU_Pos = 0x13 + // Bit mask of I2C_RESET_POR_FORCE_PU field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PU_Msk = 0x80000 + // Bit I2C_RESET_POR_FORCE_PU. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PU = 0x80000 + // Position of SAR_I2C_PU field. + RTC_CNTL_ANA_CONF_SAR_I2C_PU_Pos = 0x16 + // Bit mask of SAR_I2C_PU field. + RTC_CNTL_ANA_CONF_SAR_I2C_PU_Msk = 0x400000 + // Bit SAR_I2C_PU. + RTC_CNTL_ANA_CONF_SAR_I2C_PU = 0x400000 + // Position of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Pos = 0x19 + // Bit mask of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Msk = 0x2000000 + // Bit BBPLL_CAL_SLP_START. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START = 0x2000000 + // Position of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Pos = 0x1b + // Bit mask of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Msk = 0x8000000 + // Bit TXRF_I2C_PU. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU = 0x8000000 + // Position of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Pos = 0x1c + // Bit mask of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Msk = 0x10000000 + // Bit RFRX_PBUS_PU. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU = 0x10000000 + // Position of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Pos = 0x1e + // Bit mask of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Msk = 0x40000000 + // Bit CKGEN_I2C_PU. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU = 0x40000000 + // Position of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Pos = 0x1f + // Bit mask of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Msk = 0x80000000 + // Bit PLL_I2C_PU. + RTC_CNTL_ANA_CONF_PLL_I2C_PU = 0x80000000 + // Position of PLLA_FORCE_PD field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD_Pos = 0x17 + // Bit mask of PLLA_FORCE_PD field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD_Msk = 0x800000 + // Bit PLLA_FORCE_PD. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD = 0x800000 + // Position of PLLA_FORCE_PU field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU_Pos = 0x18 + // Bit mask of PLLA_FORCE_PU field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU_Msk = 0x1000000 + // Bit PLLA_FORCE_PU. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU = 0x1000000 + + // RESET_STATE: register description + // Position of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Pos = 0x0 + // Bit mask of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Msk = 0x3f + // Position of STAT_VECTOR_SEL_PROCPU field. + RTC_CNTL_RESET_STATE_STAT_VECTOR_SEL_PROCPU_Pos = 0xd + // Bit mask of STAT_VECTOR_SEL_PROCPU field. + RTC_CNTL_RESET_STATE_STAT_VECTOR_SEL_PROCPU_Msk = 0x2000 + // Bit STAT_VECTOR_SEL_PROCPU. + RTC_CNTL_RESET_STATE_STAT_VECTOR_SEL_PROCPU = 0x2000 + // Position of OCD_HALT_ON_RESET_PROCPU field. + RTC_CNTL_RESET_STATE_OCD_HALT_ON_RESET_PROCPU_Pos = 0x13 + // Bit mask of OCD_HALT_ON_RESET_PROCPU field. + RTC_CNTL_RESET_STATE_OCD_HALT_ON_RESET_PROCPU_Msk = 0x80000 + // Bit OCD_HALT_ON_RESET_PROCPU. + RTC_CNTL_RESET_STATE_OCD_HALT_ON_RESET_PROCPU = 0x80000 + // Position of DRESET_MASK_PROCPU field. + RTC_CNTL_RESET_STATE_DRESET_MASK_PROCPU_Pos = 0x14 + // Bit mask of DRESET_MASK_PROCPU field. + RTC_CNTL_RESET_STATE_DRESET_MASK_PROCPU_Msk = 0x100000 + // Bit DRESET_MASK_PROCPU. + RTC_CNTL_RESET_STATE_DRESET_MASK_PROCPU = 0x100000 + + // WAKEUP_STATE: register description + // Position of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Pos = 0xf + // Bit mask of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Msk = 0xffff8000 + + // INT_ENA_RTC: register description + // Position of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA = 0x1 + // Position of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA = 0x2 + // Position of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA_Pos = 0x3 + // Bit mask of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA_Msk = 0x8 + // Bit WDT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA = 0x8 + // Position of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA = 0x200 + // Position of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA = 0x400 + // Position of SWD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA_Pos = 0xf + // Bit mask of SWD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA_Msk = 0x8000 + // Bit SWD_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA = 0x8000 + // Position of BBPLL_CAL_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BBPLL_CAL_INT_ENA_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BBPLL_CAL_INT_ENA_Msk = 0x100000 + // Bit BBPLL_CAL_INT_ENA. + RTC_CNTL_INT_ENA_RTC_BBPLL_CAL_INT_ENA = 0x100000 + + // INT_RAW_RTC: register description + // Position of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW_Msk = 0x1 + // Bit SLP_WAKEUP_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW = 0x1 + // Position of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW_Msk = 0x2 + // Bit SLP_REJECT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW = 0x2 + // Position of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW_Pos = 0x3 + // Bit mask of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW_Msk = 0x8 + // Bit WDT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW = 0x8 + // Position of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW_Msk = 0x200 + // Bit BROWN_OUT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW = 0x200 + // Position of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW_Msk = 0x400 + // Bit MAIN_TIMER_INT_RAW. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW = 0x400 + // Position of SWD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW_Pos = 0xf + // Bit mask of SWD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW_Msk = 0x8000 + // Bit SWD_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW = 0x8000 + // Position of BBPLL_CAL_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BBPLL_CAL_INT_RAW_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BBPLL_CAL_INT_RAW_Msk = 0x100000 + // Bit BBPLL_CAL_INT_RAW. + RTC_CNTL_INT_RAW_RTC_BBPLL_CAL_INT_RAW = 0x100000 + + // INT_ST_RTC: register description + // Position of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ST. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST = 0x1 + // Position of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST_Msk = 0x2 + // Bit SLP_REJECT_INT_ST. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST = 0x2 + // Position of WDT_INT_ST field. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST_Pos = 0x3 + // Bit mask of WDT_INT_ST field. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST_Msk = 0x8 + // Bit WDT_INT_ST. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST = 0x8 + // Position of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST_Msk = 0x200 + // Bit BROWN_OUT_INT_ST. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST = 0x200 + // Position of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST_Msk = 0x400 + // Bit MAIN_TIMER_INT_ST. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST = 0x400 + // Position of SWD_INT_ST field. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST_Pos = 0xf + // Bit mask of SWD_INT_ST field. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST_Msk = 0x8000 + // Bit SWD_INT_ST. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST = 0x8000 + // Position of BBPLL_CAL_INT_ST field. + RTC_CNTL_INT_ST_RTC_BBPLL_CAL_INT_ST_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_ST field. + RTC_CNTL_INT_ST_RTC_BBPLL_CAL_INT_ST_Msk = 0x100000 + // Bit BBPLL_CAL_INT_ST. + RTC_CNTL_INT_ST_RTC_BBPLL_CAL_INT_ST = 0x100000 + + // INT_CLR_RTC: register description + // Position of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR_Msk = 0x1 + // Bit SLP_WAKEUP_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR = 0x1 + // Position of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR_Msk = 0x2 + // Bit SLP_REJECT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR = 0x2 + // Position of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR_Pos = 0x3 + // Bit mask of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR_Msk = 0x8 + // Bit WDT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR = 0x8 + // Position of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR_Msk = 0x200 + // Bit BROWN_OUT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR = 0x200 + // Position of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR_Msk = 0x400 + // Bit MAIN_TIMER_INT_CLR. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR = 0x400 + // Position of SWD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR_Pos = 0xf + // Bit mask of SWD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR_Msk = 0x8000 + // Bit SWD_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR = 0x8000 + // Position of BBPLL_CAL_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BBPLL_CAL_INT_CLR_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BBPLL_CAL_INT_CLR_Msk = 0x100000 + // Bit BBPLL_CAL_INT_CLR. + RTC_CNTL_INT_CLR_RTC_BBPLL_CAL_INT_CLR = 0x100000 + + // STORE0: register description + // Position of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Pos = 0x0 + // Bit mask of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Msk = 0xffffffff + + // STORE1: register description + // Position of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Pos = 0x0 + // Bit mask of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Msk = 0xffffffff + + // STORE2: register description + // Position of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Pos = 0x0 + // Bit mask of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Msk = 0xffffffff + + // STORE3: register description + // Position of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Pos = 0x0 + // Bit mask of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Msk = 0xffffffff + + // EXT_XTL_CONF: register description + // Position of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Pos = 0x1e + // Bit mask of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Msk = 0x40000000 + // Bit XTL_EXT_CTR_LV. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV = 0x40000000 + // Position of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Pos = 0x1f + // Bit mask of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Msk = 0x80000000 + // Bit XTL_EXT_CTR_EN. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN = 0x80000000 + + // EXT_WAKEUP_CONF: register description + // Position of GPIO_WAKEUP_FILTER field. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER_Pos = 0x1f + // Bit mask of GPIO_WAKEUP_FILTER field. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER_Msk = 0x80000000 + // Bit GPIO_WAKEUP_FILTER. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER = 0x80000000 + + // SLP_REJECT_CONF: register description + // Position of SLEEP_REJECT_ENA field. + RTC_CNTL_SLP_REJECT_CONF_SLEEP_REJECT_ENA_Pos = 0xc + // Bit mask of SLEEP_REJECT_ENA field. + RTC_CNTL_SLP_REJECT_CONF_SLEEP_REJECT_ENA_Msk = 0x3ffff000 + // Position of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Pos = 0x1e + // Bit mask of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Msk = 0x40000000 + // Bit LIGHT_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN = 0x40000000 + // Position of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Pos = 0x1f + // Bit mask of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Msk = 0x80000000 + // Bit DEEP_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN = 0x80000000 + + // CPU_PERIOD_CONF: register description + // Position of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Pos = 0x1d + // Bit mask of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Msk = 0x20000000 + // Bit CPUSEL_CONF. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF = 0x20000000 + // Position of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Pos = 0x1e + // Bit mask of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Msk = 0xc0000000 + + // CLK_CONF: register description + // Position of EFUSE_CLK_FORCE_GATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_GATING_Pos = 0x1 + // Bit mask of EFUSE_CLK_FORCE_GATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_GATING_Msk = 0x2 + // Bit EFUSE_CLK_FORCE_GATING. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_GATING = 0x2 + // Position of EFUSE_CLK_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_NOGATING_Pos = 0x2 + // Bit mask of EFUSE_CLK_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_NOGATING_Msk = 0x4 + // Bit EFUSE_CLK_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_NOGATING = 0x4 + // Position of CK8M_DIV_SEL_VLD field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD_Pos = 0x3 + // Bit mask of CK8M_DIV_SEL_VLD field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD_Msk = 0x8 + // Bit CK8M_DIV_SEL_VLD. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD = 0x8 + // Position of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Pos = 0x4 + // Bit mask of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Msk = 0x30 + // Position of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Pos = 0x6 + // Bit mask of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Msk = 0x40 + // Bit ENB_CK8M. + RTC_CNTL_CLK_CONF_ENB_CK8M = 0x40 + // Position of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Pos = 0x7 + // Bit mask of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Msk = 0x80 + // Bit ENB_CK8M_DIV. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV = 0x80 + // Position of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Pos = 0x8 + // Bit mask of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Msk = 0x100 + // Bit DIG_XTAL32K_EN. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN = 0x100 + // Position of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Pos = 0x9 + // Bit mask of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Msk = 0x200 + // Bit DIG_CLK8M_D256_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN = 0x200 + // Position of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Pos = 0xa + // Bit mask of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Msk = 0x400 + // Bit DIG_CLK8M_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN = 0x400 + // Position of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Pos = 0xc + // Bit mask of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Msk = 0x7000 + // Position of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Pos = 0xf + // Bit mask of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Msk = 0x8000 + // Bit XTAL_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING = 0x8000 + // Position of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Pos = 0x10 + // Bit mask of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Msk = 0x10000 + // Bit CK8M_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING = 0x10000 + // Position of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Pos = 0x11 + // Bit mask of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Msk = 0x1fe0000 + // Position of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Pos = 0x19 + // Bit mask of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Msk = 0x2000000 + // Bit CK8M_FORCE_PD. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD = 0x2000000 + // Position of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Pos = 0x1a + // Bit mask of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Msk = 0x4000000 + // Bit CK8M_FORCE_PU. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU = 0x4000000 + // Position of XTAL_GLOBAL_FORCE_GATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_GATING_Pos = 0x1b + // Bit mask of XTAL_GLOBAL_FORCE_GATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_GATING_Msk = 0x8000000 + // Bit XTAL_GLOBAL_FORCE_GATING. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_GATING = 0x8000000 + // Position of XTAL_GLOBAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_NOGATING_Pos = 0x1c + // Bit mask of XTAL_GLOBAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_NOGATING_Msk = 0x10000000 + // Bit XTAL_GLOBAL_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_NOGATING = 0x10000000 + // Position of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Pos = 0x1d + // Bit mask of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Msk = 0x20000000 + // Bit FAST_CLK_RTC_SEL. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL = 0x20000000 + // Position of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Pos = 0x1e + // Bit mask of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Msk = 0xc0000000 + + // SLOW_CLK_CONF: register description + // Position of ANA_CLK_DIV_VLD field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD_Pos = 0x16 + // Bit mask of ANA_CLK_DIV_VLD field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD_Msk = 0x400000 + // Bit ANA_CLK_DIV_VLD. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD = 0x400000 + // Position of ANA_CLK_DIV field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_Pos = 0x17 + // Bit mask of ANA_CLK_DIV field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_Msk = 0x7f800000 + // Position of SLOW_CLK_NEXT_EDGE field. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE_Pos = 0x1f + // Bit mask of SLOW_CLK_NEXT_EDGE field. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE_Msk = 0x80000000 + // Bit SLOW_CLK_NEXT_EDGE. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE = 0x80000000 + + // BIAS_CONF: register description + // Position of DG_VDD_DRV_B_SLP field. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_Pos = 0x0 + // Bit mask of DG_VDD_DRV_B_SLP field. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_Msk = 0xff + // Position of DG_VDD_DRV_B_SLP_EN field. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_EN_Pos = 0x8 + // Bit mask of DG_VDD_DRV_B_SLP_EN field. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_EN_Msk = 0x100 + // Bit DG_VDD_DRV_B_SLP_EN. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_EN = 0x100 + // Position of BIAS_BUF_IDLE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE_Pos = 0xa + // Bit mask of BIAS_BUF_IDLE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE_Msk = 0x400 + // Bit BIAS_BUF_IDLE. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE = 0x400 + // Position of BIAS_BUF_WAKE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE_Pos = 0xb + // Bit mask of BIAS_BUF_WAKE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE_Msk = 0x800 + // Bit BIAS_BUF_WAKE. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE = 0x800 + // Position of BIAS_BUF_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP_Pos = 0xc + // Bit mask of BIAS_BUF_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP_Msk = 0x1000 + // Bit BIAS_BUF_DEEP_SLP. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP = 0x1000 + // Position of BIAS_BUF_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR_Pos = 0xd + // Bit mask of BIAS_BUF_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR_Msk = 0x2000 + // Bit BIAS_BUF_MONITOR. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR = 0x2000 + // Position of PD_CUR_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP_Pos = 0xe + // Bit mask of PD_CUR_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP_Msk = 0x4000 + // Bit PD_CUR_DEEP_SLP. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP = 0x4000 + // Position of PD_CUR_MONITOR field. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR_Pos = 0xf + // Bit mask of PD_CUR_MONITOR field. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR_Msk = 0x8000 + // Bit PD_CUR_MONITOR. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR = 0x8000 + // Position of BIAS_SLEEP_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP_Pos = 0x10 + // Bit mask of BIAS_SLEEP_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP_Msk = 0x10000 + // Bit BIAS_SLEEP_DEEP_SLP. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP = 0x10000 + // Position of BIAS_SLEEP_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR_Pos = 0x11 + // Bit mask of BIAS_SLEEP_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR_Msk = 0x20000 + // Bit BIAS_SLEEP_MONITOR. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR = 0x20000 + // Position of DBG_ATTEN_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_DEEP_SLP_Pos = 0x12 + // Bit mask of DBG_ATTEN_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_DEEP_SLP_Msk = 0x3c0000 + // Position of DBG_ATTEN_MONITOR field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_MONITOR_Pos = 0x16 + // Bit mask of DBG_ATTEN_MONITOR field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_MONITOR_Msk = 0x3c00000 + // Position of DBG_ATTEN_ACTIVE field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_ACTIVE_Pos = 0x1a + // Bit mask of DBG_ATTEN_ACTIVE field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_ACTIVE_Msk = 0x3c000000 + + // RTC_CNTL: register description + // Position of DIG_REG_CAL_EN field. + RTC_CNTL_RTC_CNTL_DIG_REG_CAL_EN_Pos = 0x7 + // Bit mask of DIG_REG_CAL_EN field. + RTC_CNTL_RTC_CNTL_DIG_REG_CAL_EN_Msk = 0x80 + // Bit DIG_REG_CAL_EN. + RTC_CNTL_RTC_CNTL_DIG_REG_CAL_EN = 0x80 + // Position of SCK_DCAP field. + RTC_CNTL_RTC_CNTL_SCK_DCAP_Pos = 0xe + // Bit mask of SCK_DCAP field. + RTC_CNTL_RTC_CNTL_SCK_DCAP_Msk = 0x3fc000 + // Position of REGULATOR_FORCE_PD field. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PD_Pos = 0x1e + // Bit mask of REGULATOR_FORCE_PD field. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PD_Msk = 0x40000000 + // Bit REGULATOR_FORCE_PD. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PD = 0x40000000 + // Position of REGULATOR_FORCE_PU field. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PU_Pos = 0x1f + // Bit mask of REGULATOR_FORCE_PU field. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PU_Msk = 0x80000000 + // Bit REGULATOR_FORCE_PU. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PU = 0x80000000 + + // PWC: register description + // Position of PAD_FORCE_HOLD field. + RTC_CNTL_PWC_PAD_FORCE_HOLD_Pos = 0x15 + // Bit mask of PAD_FORCE_HOLD field. + RTC_CNTL_PWC_PAD_FORCE_HOLD_Msk = 0x200000 + // Bit PAD_FORCE_HOLD. + RTC_CNTL_PWC_PAD_FORCE_HOLD = 0x200000 + + // DIG_PWC: register description + // Position of VDD_SPI_PWR_DRV field. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_DRV_Pos = 0x0 + // Bit mask of VDD_SPI_PWR_DRV field. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_DRV_Msk = 0x3 + // Position of VDD_SPI_PWR_FORCE field. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_FORCE_Pos = 0x2 + // Bit mask of VDD_SPI_PWR_FORCE field. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_FORCE_Msk = 0x4 + // Bit VDD_SPI_PWR_FORCE. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_FORCE = 0x4 + // Position of VDD_SPI_PD_EN field. + RTC_CNTL_DIG_PWC_VDD_SPI_PD_EN_Pos = 0x3 + // Bit mask of VDD_SPI_PD_EN field. + RTC_CNTL_DIG_PWC_VDD_SPI_PD_EN_Msk = 0x8 + // Bit VDD_SPI_PD_EN. + RTC_CNTL_DIG_PWC_VDD_SPI_PD_EN = 0x8 + // Position of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Pos = 0x4 + // Bit mask of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Msk = 0x10 + // Bit LSLP_MEM_FORCE_PD. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD = 0x10 + // Position of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Pos = 0x5 + // Bit mask of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Msk = 0x20 + // Bit LSLP_MEM_FORCE_PU. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU = 0x20 + // Position of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Pos = 0x13 + // Bit mask of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Msk = 0x80000 + // Bit DG_WRAP_FORCE_PD. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD = 0x80000 + // Position of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Pos = 0x14 + // Bit mask of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Msk = 0x100000 + // Bit DG_WRAP_FORCE_PU. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU = 0x100000 + // Position of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Pos = 0x1f + // Bit mask of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Msk = 0x80000000 + // Bit DG_WRAP_PD_EN. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN = 0x80000000 + + // DIG_ISO: register description + // Position of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Pos = 0x7 + // Bit mask of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Msk = 0x80 + // Bit FORCE_OFF. + RTC_CNTL_DIG_ISO_FORCE_OFF = 0x80 + // Position of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Pos = 0x8 + // Bit mask of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Msk = 0x100 + // Bit FORCE_ON. + RTC_CNTL_DIG_ISO_FORCE_ON = 0x100 + // Position of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Pos = 0x9 + // Bit mask of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Msk = 0x200 + // Bit DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD = 0x200 + // Position of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Pos = 0xa + // Bit mask of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Msk = 0x400 + // Bit CLR_DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD = 0x400 + // Position of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Pos = 0xb + // Bit mask of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Msk = 0x800 + // Bit DG_PAD_AUTOHOLD_EN. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN = 0x800 + // Position of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Pos = 0xc + // Bit mask of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Msk = 0x1000 + // Bit DG_PAD_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO = 0x1000 + // Position of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Pos = 0xd + // Bit mask of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Msk = 0x2000 + // Bit DG_PAD_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO = 0x2000 + // Position of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Pos = 0xe + // Bit mask of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Msk = 0x4000 + // Bit DG_PAD_FORCE_UNHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD = 0x4000 + // Position of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Pos = 0xf + // Bit mask of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Msk = 0x8000 + // Bit DG_PAD_FORCE_HOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD = 0x8000 + // Position of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO = 0x40000000 + // Position of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Pos = 0x1f + // Bit mask of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Msk = 0x80000000 + // Bit DG_WRAP_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO = 0x80000000 + + // WDTCONFIG0: register description + // Position of WDT_CHIP_RESET_WIDTH field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Pos = 0x0 + // Bit mask of WDT_CHIP_RESET_WIDTH field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Msk = 0xff + // Position of WDT_CHIP_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN_Pos = 0x8 + // Bit mask of WDT_CHIP_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN_Msk = 0x100 + // Bit WDT_CHIP_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN = 0x100 + // Position of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Pos = 0x9 + // Bit mask of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Msk = 0x200 + // Bit WDT_PAUSE_IN_SLP. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP = 0x200 + // Position of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xb + // Bit mask of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x800 + // Bit WDT_PROCPU_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x800 + // Position of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xc + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x1000 + // Bit WDT_FLASHBOOT_MOD_EN. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x1000 + // Position of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xd + // Bit mask of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0xe000 + // Position of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x10 + // Bit mask of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x70000 + // Position of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Pos = 0x13 + // Bit mask of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Msk = 0x380000 + // Position of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Pos = 0x16 + // Bit mask of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Msk = 0x1c00000 + // Position of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Pos = 0x19 + // Bit mask of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Msk = 0xe000000 + // Position of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Pos = 0x1c + // Bit mask of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Msk = 0x70000000 + // Position of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + RTC_CNTL_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: register description + // Position of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG2: register description + // Position of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: register description + // Position of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: register description + // Position of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: register description + // Position of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Pos = 0x1f + // Bit mask of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Msk = 0x80000000 + // Bit WDT_FEED. + RTC_CNTL_WDTFEED_WDT_FEED = 0x80000000 + + // WDTWPROTECT: register description + // Position of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // SWD_CONF: register description + // Position of SWD_RESET_FLAG field. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG_Pos = 0x0 + // Bit mask of SWD_RESET_FLAG field. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG_Msk = 0x1 + // Bit SWD_RESET_FLAG. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG = 0x1 + // Position of SWD_FEED_INT field. + RTC_CNTL_SWD_CONF_SWD_FEED_INT_Pos = 0x1 + // Bit mask of SWD_FEED_INT field. + RTC_CNTL_SWD_CONF_SWD_FEED_INT_Msk = 0x2 + // Bit SWD_FEED_INT. + RTC_CNTL_SWD_CONF_SWD_FEED_INT = 0x2 + // Position of SWD_BYPASS_RST field. + RTC_CNTL_SWD_CONF_SWD_BYPASS_RST_Pos = 0x11 + // Bit mask of SWD_BYPASS_RST field. + RTC_CNTL_SWD_CONF_SWD_BYPASS_RST_Msk = 0x20000 + // Bit SWD_BYPASS_RST. + RTC_CNTL_SWD_CONF_SWD_BYPASS_RST = 0x20000 + // Position of SWD_SIGNAL_WIDTH field. + RTC_CNTL_SWD_CONF_SWD_SIGNAL_WIDTH_Pos = 0x12 + // Bit mask of SWD_SIGNAL_WIDTH field. + RTC_CNTL_SWD_CONF_SWD_SIGNAL_WIDTH_Msk = 0xffc0000 + // Position of SWD_RST_FLAG_CLR field. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR_Pos = 0x1c + // Bit mask of SWD_RST_FLAG_CLR field. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR_Msk = 0x10000000 + // Bit SWD_RST_FLAG_CLR. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR = 0x10000000 + // Position of SWD_FEED field. + RTC_CNTL_SWD_CONF_SWD_FEED_Pos = 0x1d + // Bit mask of SWD_FEED field. + RTC_CNTL_SWD_CONF_SWD_FEED_Msk = 0x20000000 + // Bit SWD_FEED. + RTC_CNTL_SWD_CONF_SWD_FEED = 0x20000000 + // Position of SWD_DISABLE field. + RTC_CNTL_SWD_CONF_SWD_DISABLE_Pos = 0x1e + // Bit mask of SWD_DISABLE field. + RTC_CNTL_SWD_CONF_SWD_DISABLE_Msk = 0x40000000 + // Bit SWD_DISABLE. + RTC_CNTL_SWD_CONF_SWD_DISABLE = 0x40000000 + // Position of SWD_AUTO_FEED_EN field. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN_Pos = 0x1f + // Bit mask of SWD_AUTO_FEED_EN field. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN_Msk = 0x80000000 + // Bit SWD_AUTO_FEED_EN. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN = 0x80000000 + + // SWD_WPROTECT: register description + // Position of SWD_WKEY field. + RTC_CNTL_SWD_WPROTECT_SWD_WKEY_Pos = 0x0 + // Bit mask of SWD_WKEY field. + RTC_CNTL_SWD_WPROTECT_SWD_WKEY_Msk = 0xffffffff + + // SW_CPU_STALL: register description + // Position of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Pos = 0x1a + // Bit mask of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Msk = 0xfc000000 + + // STORE4: register description + // Position of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Pos = 0x0 + // Bit mask of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Msk = 0xffffffff + + // STORE5: register description + // Position of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Pos = 0x0 + // Bit mask of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Msk = 0xffffffff + + // STORE6: register description + // Position of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Pos = 0x0 + // Bit mask of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Msk = 0xffffffff + + // STORE7: register description + // Position of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Pos = 0x0 + // Bit mask of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Msk = 0xffffffff + + // LOW_POWER_ST: register description + // Position of XPD_DIG field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_Pos = 0x8 + // Bit mask of XPD_DIG field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_Msk = 0x100 + // Bit XPD_DIG. + RTC_CNTL_LOW_POWER_ST_XPD_DIG = 0x100 + // Position of TOUCH_STATE_START field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START_Pos = 0x9 + // Bit mask of TOUCH_STATE_START field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START_Msk = 0x200 + // Bit TOUCH_STATE_START. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START = 0x200 + // Position of TOUCH_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH_Pos = 0xa + // Bit mask of TOUCH_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH_Msk = 0x400 + // Bit TOUCH_STATE_SWITCH. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH = 0x400 + // Position of TOUCH_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP_Pos = 0xb + // Bit mask of TOUCH_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP_Msk = 0x800 + // Bit TOUCH_STATE_SLP. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP = 0x800 + // Position of TOUCH_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE_Pos = 0xc + // Bit mask of TOUCH_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE_Msk = 0x1000 + // Bit TOUCH_STATE_DONE. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE = 0x1000 + // Position of COCPU_STATE_START field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START_Pos = 0xd + // Bit mask of COCPU_STATE_START field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START_Msk = 0x2000 + // Bit COCPU_STATE_START. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START = 0x2000 + // Position of COCPU_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH_Pos = 0xe + // Bit mask of COCPU_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH_Msk = 0x4000 + // Bit COCPU_STATE_SWITCH. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH = 0x4000 + // Position of COCPU_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP_Pos = 0xf + // Bit mask of COCPU_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP_Msk = 0x8000 + // Bit COCPU_STATE_SLP. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP = 0x8000 + // Position of COCPU_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE_Pos = 0x10 + // Bit mask of COCPU_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE_Msk = 0x10000 + // Bit COCPU_STATE_DONE. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE = 0x10000 + // Position of MAIN_STATE_XTAL_ISO field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO_Pos = 0x11 + // Bit mask of MAIN_STATE_XTAL_ISO field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO_Msk = 0x20000 + // Bit MAIN_STATE_XTAL_ISO. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO = 0x20000 + // Position of MAIN_STATE_PLL_ON field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON_Pos = 0x12 + // Bit mask of MAIN_STATE_PLL_ON field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON_Msk = 0x40000 + // Bit MAIN_STATE_PLL_ON. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON = 0x40000 + // Position of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Pos = 0x13 + // Bit mask of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Msk = 0x80000 + // Bit RDY_FOR_WAKEUP. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP = 0x80000 + // Position of MAIN_STATE_WAIT_END field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END_Pos = 0x14 + // Bit mask of MAIN_STATE_WAIT_END field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END_Msk = 0x100000 + // Bit MAIN_STATE_WAIT_END. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END = 0x100000 + // Position of IN_WAKEUP_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE_Pos = 0x15 + // Bit mask of IN_WAKEUP_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE_Msk = 0x200000 + // Bit IN_WAKEUP_STATE. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE = 0x200000 + // Position of IN_LOW_POWER_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE_Pos = 0x16 + // Bit mask of IN_LOW_POWER_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE_Msk = 0x400000 + // Bit IN_LOW_POWER_STATE. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE = 0x400000 + // Position of MAIN_STATE_IN_WAIT_8M field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M_Pos = 0x17 + // Bit mask of MAIN_STATE_IN_WAIT_8M field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M_Msk = 0x800000 + // Bit MAIN_STATE_IN_WAIT_8M. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M = 0x800000 + // Position of MAIN_STATE_IN_WAIT_PLL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL_Pos = 0x18 + // Bit mask of MAIN_STATE_IN_WAIT_PLL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL_Msk = 0x1000000 + // Bit MAIN_STATE_IN_WAIT_PLL. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL = 0x1000000 + // Position of MAIN_STATE_IN_WAIT_XTL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL_Pos = 0x19 + // Bit mask of MAIN_STATE_IN_WAIT_XTL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL_Msk = 0x2000000 + // Bit MAIN_STATE_IN_WAIT_XTL. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL = 0x2000000 + // Position of MAIN_STATE_IN_SLP field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP_Pos = 0x1a + // Bit mask of MAIN_STATE_IN_SLP field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP_Msk = 0x4000000 + // Bit MAIN_STATE_IN_SLP. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP = 0x4000000 + // Position of MAIN_STATE_IN_IDLE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE_Pos = 0x1b + // Bit mask of MAIN_STATE_IN_IDLE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE_Msk = 0x8000000 + // Bit MAIN_STATE_IN_IDLE. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE = 0x8000000 + // Position of MAIN_STATE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_Pos = 0x1c + // Bit mask of MAIN_STATE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_Msk = 0xf0000000 + + // DIAG0: register description + // Position of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG0_LOW_POWER_DIAG1_Pos = 0x0 + // Bit mask of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG0_LOW_POWER_DIAG1_Msk = 0xffffffff + + // PAD_HOLD: register description + // Position of GPIO_PIN0_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN0_HOLD_Pos = 0x0 + // Bit mask of GPIO_PIN0_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN0_HOLD_Msk = 0x1 + // Bit GPIO_PIN0_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN0_HOLD = 0x1 + // Position of GPIO_PIN1_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN1_HOLD_Pos = 0x1 + // Bit mask of GPIO_PIN1_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN1_HOLD_Msk = 0x2 + // Bit GPIO_PIN1_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN1_HOLD = 0x2 + // Position of GPIO_PIN2_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN2_HOLD_Pos = 0x2 + // Bit mask of GPIO_PIN2_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN2_HOLD_Msk = 0x4 + // Bit GPIO_PIN2_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN2_HOLD = 0x4 + // Position of GPIO_PIN3_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN3_HOLD_Pos = 0x3 + // Bit mask of GPIO_PIN3_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN3_HOLD_Msk = 0x8 + // Bit GPIO_PIN3_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN3_HOLD = 0x8 + // Position of GPIO_PIN4_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN4_HOLD_Pos = 0x4 + // Bit mask of GPIO_PIN4_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN4_HOLD_Msk = 0x10 + // Bit GPIO_PIN4_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN4_HOLD = 0x10 + // Position of GPIO_PIN5_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN5_HOLD_Pos = 0x5 + // Bit mask of GPIO_PIN5_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN5_HOLD_Msk = 0x20 + // Bit GPIO_PIN5_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN5_HOLD = 0x20 + + // DIG_PAD_HOLD: register description + // Position of DIG_PAD_HOLD field. + RTC_CNTL_DIG_PAD_HOLD_DIG_PAD_HOLD_Pos = 0x0 + // Bit mask of DIG_PAD_HOLD field. + RTC_CNTL_DIG_PAD_HOLD_DIG_PAD_HOLD_Msk = 0xffffffff + + // BROWN_OUT: register description + // Position of BROWN_OUT_INT_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_INT_WAIT_Pos = 0x4 + // Bit mask of BROWN_OUT_INT_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_INT_WAIT_Msk = 0x3ff0 + // Position of BROWN_OUT_CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA_Pos = 0xe + // Bit mask of BROWN_OUT_CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA_Msk = 0x4000 + // Bit BROWN_OUT_CLOSE_FLASH_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA = 0x4000 + // Position of BROWN_OUT_PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_PD_RF_ENA_Pos = 0xf + // Bit mask of BROWN_OUT_PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_PD_RF_ENA_Msk = 0x8000 + // Bit BROWN_OUT_PD_RF_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_PD_RF_ENA = 0x8000 + // Position of BROWN_OUT_RST_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_WAIT_Pos = 0x10 + // Bit mask of BROWN_OUT_RST_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_WAIT_Msk = 0x3ff0000 + // Position of BROWN_OUT_RST_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_ENA_Pos = 0x1a + // Bit mask of BROWN_OUT_RST_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_ENA_Msk = 0x4000000 + // Bit BROWN_OUT_RST_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_ENA = 0x4000000 + // Position of BROWN_OUT_RST_SEL field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_SEL_Pos = 0x1b + // Bit mask of BROWN_OUT_RST_SEL field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_SEL_Msk = 0x8000000 + // Bit BROWN_OUT_RST_SEL. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_SEL = 0x8000000 + // Position of BROWN_OUT_ANA_RST_EN field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ANA_RST_EN_Pos = 0x1c + // Bit mask of BROWN_OUT_ANA_RST_EN field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ANA_RST_EN_Msk = 0x10000000 + // Bit BROWN_OUT_ANA_RST_EN. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ANA_RST_EN = 0x10000000 + // Position of BROWN_OUT_CNT_CLR field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CNT_CLR_Pos = 0x1d + // Bit mask of BROWN_OUT_CNT_CLR field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CNT_CLR_Msk = 0x20000000 + // Bit BROWN_OUT_CNT_CLR. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CNT_CLR = 0x20000000 + // Position of BROWN_OUT_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ENA_Pos = 0x1e + // Bit mask of BROWN_OUT_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ENA_Msk = 0x40000000 + // Bit BROWN_OUT_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ENA = 0x40000000 + // Position of DET field. + RTC_CNTL_BROWN_OUT_DET_Pos = 0x1f + // Bit mask of DET field. + RTC_CNTL_BROWN_OUT_DET_Msk = 0x80000000 + // Bit DET. + RTC_CNTL_BROWN_OUT_DET = 0x80000000 + + // TIME_LOW1: register description + // Position of TIMER_VALUE1_LOW field. + RTC_CNTL_TIME_LOW1_TIMER_VALUE1_LOW_Pos = 0x0 + // Bit mask of TIMER_VALUE1_LOW field. + RTC_CNTL_TIME_LOW1_TIMER_VALUE1_LOW_Msk = 0xffffffff + + // TIME_HIGH1: register description + // Position of TIMER_VALUE1_HIGH field. + RTC_CNTL_TIME_HIGH1_TIMER_VALUE1_HIGH_Pos = 0x0 + // Bit mask of TIMER_VALUE1_HIGH field. + RTC_CNTL_TIME_HIGH1_TIMER_VALUE1_HIGH_Msk = 0xffff + + // USB_CONF: register description + // Position of IO_MUX_RESET_DISABLE field. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE_Pos = 0x12 + // Bit mask of IO_MUX_RESET_DISABLE field. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE_Msk = 0x40000 + // Bit IO_MUX_RESET_DISABLE. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE = 0x40000 + + // SLP_REJECT_CAUSE: register description + // Position of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CAUSE_REJECT_CAUSE_Pos = 0x0 + // Bit mask of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CAUSE_REJECT_CAUSE_Msk = 0x3ffff + + // OPTION1: register description + // Position of FORCE_DOWNLOAD_BOOT field. + RTC_CNTL_OPTION1_FORCE_DOWNLOAD_BOOT_Pos = 0x0 + // Bit mask of FORCE_DOWNLOAD_BOOT field. + RTC_CNTL_OPTION1_FORCE_DOWNLOAD_BOOT_Msk = 0x1 + // Bit FORCE_DOWNLOAD_BOOT. + RTC_CNTL_OPTION1_FORCE_DOWNLOAD_BOOT = 0x1 + + // SLP_WAKEUP_CAUSE: register description + // Position of WAKEUP_CAUSE field. + RTC_CNTL_SLP_WAKEUP_CAUSE_WAKEUP_CAUSE_Pos = 0x0 + // Bit mask of WAKEUP_CAUSE field. + RTC_CNTL_SLP_WAKEUP_CAUSE_WAKEUP_CAUSE_Msk = 0x1ffff + + // ULP_CP_TIMER_1: register description + // Position of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Pos = 0x8 + // Bit mask of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Msk = 0xffffff00 + + // INT_ENA_RTC_W1TS: register description + // Position of SLP_WAKEUP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS = 0x1 + // Position of SLP_REJECT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS = 0x2 + // Position of WDT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS_Pos = 0x3 + // Bit mask of WDT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS_Msk = 0x8 + // Bit WDT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS = 0x8 + // Position of BROWN_OUT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS = 0x200 + // Position of MAIN_TIMER_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS = 0x400 + // Position of SWD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS_Pos = 0xf + // Bit mask of SWD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS_Msk = 0x8000 + // Bit SWD_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS = 0x8000 + // Position of BBPLL_CAL_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS_Msk = 0x100000 + // Bit BBPLL_CAL_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS = 0x100000 + + // INT_ENA_RTC_W1TC: register description + // Position of SLP_WAKEUP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC = 0x1 + // Position of SLP_REJECT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC = 0x2 + // Position of WDT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC_Pos = 0x3 + // Bit mask of WDT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC_Msk = 0x8 + // Bit WDT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC = 0x8 + // Position of BROWN_OUT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC = 0x200 + // Position of MAIN_TIMER_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC = 0x400 + // Position of SWD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC_Pos = 0xf + // Bit mask of SWD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC_Msk = 0x8000 + // Bit SWD_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC = 0x8000 + // Position of BBPLL_CAL_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC_Msk = 0x100000 + // Bit BBPLL_CAL_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC = 0x100000 + + // CNTL_RETENTION_CTRL: register description + // Position of RETENTION_CLK_SEL field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_CLK_SEL_Pos = 0x12 + // Bit mask of RETENTION_CLK_SEL field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_CLK_SEL_Msk = 0x40000 + // Bit RETENTION_CLK_SEL. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_CLK_SEL = 0x40000 + // Position of RETENTION_DONE_WAIT field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_DONE_WAIT_Pos = 0x13 + // Bit mask of RETENTION_DONE_WAIT field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_DONE_WAIT_Msk = 0x380000 + // Position of RETENTION_CLKOFF_WAIT field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_CLKOFF_WAIT_Pos = 0x16 + // Bit mask of RETENTION_CLKOFF_WAIT field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_CLKOFF_WAIT_Msk = 0x3c00000 + // Position of RETENTION_EN field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_EN_Pos = 0x1a + // Bit mask of RETENTION_EN field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_EN_Msk = 0x4000000 + // Bit RETENTION_EN. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_EN = 0x4000000 + // Position of RETENTION_WAIT field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_WAIT_Pos = 0x1b + // Bit mask of RETENTION_WAIT field. + RTC_CNTL_CNTL_RETENTION_CTRL_RETENTION_WAIT_Msk = 0xf8000000 + + // FIB_SEL: register description + // Position of FIB_SEL field. + RTC_CNTL_FIB_SEL_FIB_SEL_Pos = 0x0 + // Bit mask of FIB_SEL field. + RTC_CNTL_FIB_SEL_FIB_SEL_Msk = 0x7 + + // CNTL_GPIO_WAKEUP: register description + // Position of GPIO_WAKEUP_STATUS field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_Pos = 0x0 + // Bit mask of GPIO_WAKEUP_STATUS field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_Msk = 0x3f + // Position of GPIO_WAKEUP_STATUS_CLR field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR_Pos = 0x6 + // Bit mask of GPIO_WAKEUP_STATUS_CLR field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR_Msk = 0x40 + // Bit GPIO_WAKEUP_STATUS_CLR. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR = 0x40 + // Position of GPIO_PIN_CLK_GATE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN_CLK_GATE_Pos = 0x7 + // Bit mask of GPIO_PIN_CLK_GATE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN_CLK_GATE_Msk = 0x80 + // Bit GPIO_PIN_CLK_GATE. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN_CLK_GATE = 0x80 + // Position of GPIO_PIN5_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN5_INT_TYPE_Pos = 0x8 + // Bit mask of GPIO_PIN5_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN5_INT_TYPE_Msk = 0x700 + // Position of GPIO_PIN4_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN4_INT_TYPE_Pos = 0xb + // Bit mask of GPIO_PIN4_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN4_INT_TYPE_Msk = 0x3800 + // Position of GPIO_PIN3_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN3_INT_TYPE_Pos = 0xe + // Bit mask of GPIO_PIN3_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN3_INT_TYPE_Msk = 0x1c000 + // Position of GPIO_PIN2_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN2_INT_TYPE_Pos = 0x11 + // Bit mask of GPIO_PIN2_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN2_INT_TYPE_Msk = 0xe0000 + // Position of GPIO_PIN1_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN1_INT_TYPE_Pos = 0x14 + // Bit mask of GPIO_PIN1_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN1_INT_TYPE_Msk = 0x700000 + // Position of GPIO_PIN0_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN0_INT_TYPE_Pos = 0x17 + // Bit mask of GPIO_PIN0_INT_TYPE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN0_INT_TYPE_Msk = 0x3800000 + // Position of GPIO_PIN5_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE_Pos = 0x1a + // Bit mask of GPIO_PIN5_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE_Msk = 0x4000000 + // Bit GPIO_PIN5_WAKEUP_ENABLE. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE = 0x4000000 + // Position of GPIO_PIN4_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE_Pos = 0x1b + // Bit mask of GPIO_PIN4_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE_Msk = 0x8000000 + // Bit GPIO_PIN4_WAKEUP_ENABLE. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE = 0x8000000 + // Position of GPIO_PIN3_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE_Pos = 0x1c + // Bit mask of GPIO_PIN3_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE_Msk = 0x10000000 + // Bit GPIO_PIN3_WAKEUP_ENABLE. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE = 0x10000000 + // Position of GPIO_PIN2_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE_Pos = 0x1d + // Bit mask of GPIO_PIN2_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE_Msk = 0x20000000 + // Bit GPIO_PIN2_WAKEUP_ENABLE. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE = 0x20000000 + // Position of GPIO_PIN1_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE_Pos = 0x1e + // Bit mask of GPIO_PIN1_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE_Msk = 0x40000000 + // Bit GPIO_PIN1_WAKEUP_ENABLE. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE = 0x40000000 + // Position of GPIO_PIN0_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE_Pos = 0x1f + // Bit mask of GPIO_PIN0_WAKEUP_ENABLE field. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE_Msk = 0x80000000 + // Bit GPIO_PIN0_WAKEUP_ENABLE. + RTC_CNTL_CNTL_GPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE = 0x80000000 + + // CNTL_DBG_SEL: register description + // Position of DEBUG_12M_NO_GATING field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_12M_NO_GATING_Pos = 0x1 + // Bit mask of DEBUG_12M_NO_GATING field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_12M_NO_GATING_Msk = 0x2 + // Bit DEBUG_12M_NO_GATING. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_12M_NO_GATING = 0x2 + // Position of DEBUG_BIT_SEL field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_BIT_SEL_Pos = 0x2 + // Bit mask of DEBUG_BIT_SEL field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_BIT_SEL_Msk = 0x7c + // Position of DEBUG_SEL0 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL0_Pos = 0x7 + // Bit mask of DEBUG_SEL0 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL0_Msk = 0xf80 + // Position of DEBUG_SEL1 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL1_Pos = 0xc + // Bit mask of DEBUG_SEL1 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL1_Msk = 0x1f000 + // Position of DEBUG_SEL2 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL2_Pos = 0x11 + // Bit mask of DEBUG_SEL2 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL2_Msk = 0x3e0000 + // Position of DEBUG_SEL3 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL3_Pos = 0x16 + // Bit mask of DEBUG_SEL3 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL3_Msk = 0x7c00000 + // Position of DEBUG_SEL4 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL4_Pos = 0x1b + // Bit mask of DEBUG_SEL4 field. + RTC_CNTL_CNTL_DBG_SEL_DEBUG_SEL4_Msk = 0xf8000000 + + // CNTL_DBG_MAP: register description + // Position of GPIO_PIN5_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN5_MUX_SEL_Pos = 0x2 + // Bit mask of GPIO_PIN5_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN5_MUX_SEL_Msk = 0x4 + // Bit GPIO_PIN5_MUX_SEL. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN5_MUX_SEL = 0x4 + // Position of GPIO_PIN4_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN4_MUX_SEL_Pos = 0x3 + // Bit mask of GPIO_PIN4_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN4_MUX_SEL_Msk = 0x8 + // Bit GPIO_PIN4_MUX_SEL. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN4_MUX_SEL = 0x8 + // Position of GPIO_PIN3_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN3_MUX_SEL_Pos = 0x4 + // Bit mask of GPIO_PIN3_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN3_MUX_SEL_Msk = 0x10 + // Bit GPIO_PIN3_MUX_SEL. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN3_MUX_SEL = 0x10 + // Position of GPIO_PIN2_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN2_MUX_SEL_Pos = 0x5 + // Bit mask of GPIO_PIN2_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN2_MUX_SEL_Msk = 0x20 + // Bit GPIO_PIN2_MUX_SEL. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN2_MUX_SEL = 0x20 + // Position of GPIO_PIN1_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN1_MUX_SEL_Pos = 0x6 + // Bit mask of GPIO_PIN1_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN1_MUX_SEL_Msk = 0x40 + // Bit GPIO_PIN1_MUX_SEL. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN1_MUX_SEL = 0x40 + // Position of GPIO_PIN0_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN0_MUX_SEL_Pos = 0x7 + // Bit mask of GPIO_PIN0_MUX_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN0_MUX_SEL_Msk = 0x80 + // Bit GPIO_PIN0_MUX_SEL. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN0_MUX_SEL = 0x80 + // Position of GPIO_PIN5_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN5_FUN_SEL_Pos = 0x8 + // Bit mask of GPIO_PIN5_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN5_FUN_SEL_Msk = 0xf00 + // Position of GPIO_PIN4_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN4_FUN_SEL_Pos = 0xc + // Bit mask of GPIO_PIN4_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN4_FUN_SEL_Msk = 0xf000 + // Position of GPIO_PIN3_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN3_FUN_SEL_Pos = 0x10 + // Bit mask of GPIO_PIN3_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN3_FUN_SEL_Msk = 0xf0000 + // Position of GPIO_PIN2_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN2_FUN_SEL_Pos = 0x14 + // Bit mask of GPIO_PIN2_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN2_FUN_SEL_Msk = 0xf00000 + // Position of GPIO_PIN1_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN1_FUN_SEL_Pos = 0x18 + // Bit mask of GPIO_PIN1_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN1_FUN_SEL_Msk = 0xf000000 + // Position of GPIO_PIN0_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN0_FUN_SEL_Pos = 0x1c + // Bit mask of GPIO_PIN0_FUN_SEL field. + RTC_CNTL_CNTL_DBG_MAP_GPIO_PIN0_FUN_SEL_Msk = 0xf0000000 + + // CNTL_SENSOR_CTRL: register description + // Position of SAR2_PWDET_CCT field. + RTC_CNTL_CNTL_SENSOR_CTRL_SAR2_PWDET_CCT_Pos = 0x1b + // Bit mask of SAR2_PWDET_CCT field. + RTC_CNTL_CNTL_SENSOR_CTRL_SAR2_PWDET_CCT_Msk = 0x38000000 + // Position of FORCE_XPD_SAR field. + RTC_CNTL_CNTL_SENSOR_CTRL_FORCE_XPD_SAR_Pos = 0x1e + // Bit mask of FORCE_XPD_SAR field. + RTC_CNTL_CNTL_SENSOR_CTRL_FORCE_XPD_SAR_Msk = 0xc0000000 + + // CNTL_DBG_SAR_SEL: register description + // Position of SAR_DEBUG_SEL field. + RTC_CNTL_CNTL_DBG_SAR_SEL_SAR_DEBUG_SEL_Pos = 0x1b + // Bit mask of SAR_DEBUG_SEL field. + RTC_CNTL_CNTL_DBG_SAR_SEL_SAR_DEBUG_SEL_Msk = 0xf8000000 + + // CNTL_DATE: register description + // Position of CNTL_DATE field. + RTC_CNTL_CNTL_DATE_CNTL_DATE_Pos = 0x0 + // Bit mask of CNTL_DATE field. + RTC_CNTL_CNTL_DATE_CNTL_DATE_Msk = 0xfffffff +) + +// Constants for SENSITIVE: SENSITIVE Peripheral +const ( + // ROM_TABLE_LOCK: register description + // Position of ROM_TABLE_LOCK field. + SENSITIVE_ROM_TABLE_LOCK_ROM_TABLE_LOCK_Pos = 0x0 + // Bit mask of ROM_TABLE_LOCK field. + SENSITIVE_ROM_TABLE_LOCK_ROM_TABLE_LOCK_Msk = 0x1 + // Bit ROM_TABLE_LOCK. + SENSITIVE_ROM_TABLE_LOCK_ROM_TABLE_LOCK = 0x1 + + // ROM_TABLE: register description + // Position of ROM_TABLE field. + SENSITIVE_ROM_TABLE_ROM_TABLE_Pos = 0x0 + // Bit mask of ROM_TABLE field. + SENSITIVE_ROM_TABLE_ROM_TABLE_Msk = 0xffffffff + + // APB_PERIPHERAL_ACCESS_0: register description + // Position of APB_PERIPHERAL_ACCESS_LOCK field. + SENSITIVE_APB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK_Pos = 0x0 + // Bit mask of APB_PERIPHERAL_ACCESS_LOCK field. + SENSITIVE_APB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK_Msk = 0x1 + // Bit APB_PERIPHERAL_ACCESS_LOCK. + SENSITIVE_APB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK = 0x1 + + // APB_PERIPHERAL_ACCESS_1: register description + // Position of APB_PERIPHERAL_ACCESS_SPLIT_BURST field. + SENSITIVE_APB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST_Pos = 0x0 + // Bit mask of APB_PERIPHERAL_ACCESS_SPLIT_BURST field. + SENSITIVE_APB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST_Msk = 0x1 + // Bit APB_PERIPHERAL_ACCESS_SPLIT_BURST. + SENSITIVE_APB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST = 0x1 + + // INTERNAL_SRAM_USAGE_0: register description + // Position of INTERNAL_SRAM_USAGE_LOCK field. + SENSITIVE_INTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_USAGE_LOCK field. + SENSITIVE_INTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK_Msk = 0x1 + // Bit INTERNAL_SRAM_USAGE_LOCK. + SENSITIVE_INTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK = 0x1 + + // INTERNAL_SRAM_USAGE_1: register description + // Position of INTERNAL_SRAM_USAGE_CPU_CACHE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_USAGE_CPU_CACHE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE_Msk = 0x1 + // Bit INTERNAL_SRAM_USAGE_CPU_CACHE. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE = 0x1 + // Position of INTERNAL_SRAM_USAGE_CPU_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_SRAM_Pos = 0x1 + // Bit mask of INTERNAL_SRAM_USAGE_CPU_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_SRAM_Msk = 0xe + + // INTERNAL_SRAM_USAGE_3: register description + // Position of INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_Msk = 0x7 + // Position of INTERNAL_SRAM_ALLOC_MAC_DUMP field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP_Pos = 0x3 + // Bit mask of INTERNAL_SRAM_ALLOC_MAC_DUMP field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP_Msk = 0x8 + // Bit INTERNAL_SRAM_ALLOC_MAC_DUMP. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP = 0x8 + + // CACHE_TAG_ACCESS_0: register description + // Position of CACHE_TAG_ACCESS_LOCK field. + SENSITIVE_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK_Pos = 0x0 + // Bit mask of CACHE_TAG_ACCESS_LOCK field. + SENSITIVE_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK_Msk = 0x1 + // Bit CACHE_TAG_ACCESS_LOCK. + SENSITIVE_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK = 0x1 + + // CACHE_TAG_ACCESS_1: register description + // Position of PRO_I_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS_Pos = 0x0 + // Bit mask of PRO_I_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS_Msk = 0x1 + // Bit PRO_I_TAG_RD_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS = 0x1 + // Position of PRO_I_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS_Pos = 0x1 + // Bit mask of PRO_I_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS_Msk = 0x2 + // Bit PRO_I_TAG_WR_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS = 0x2 + // Position of PRO_D_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS_Pos = 0x2 + // Bit mask of PRO_D_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS_Msk = 0x4 + // Bit PRO_D_TAG_RD_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS = 0x4 + // Position of PRO_D_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS_Pos = 0x3 + // Bit mask of PRO_D_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS_Msk = 0x8 + // Bit PRO_D_TAG_WR_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS = 0x8 + + // CACHE_MMU_ACCESS_0: register description + // Position of CACHE_MMU_ACCESS_LOCK field. + SENSITIVE_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK_Pos = 0x0 + // Bit mask of CACHE_MMU_ACCESS_LOCK field. + SENSITIVE_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK_Msk = 0x1 + // Bit CACHE_MMU_ACCESS_LOCK. + SENSITIVE_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK = 0x1 + + // CACHE_MMU_ACCESS_1: register description + // Position of PRO_MMU_RD_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS_Pos = 0x0 + // Bit mask of PRO_MMU_RD_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS_Msk = 0x1 + // Bit PRO_MMU_RD_ACS. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS = 0x1 + // Position of PRO_MMU_WR_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS_Pos = 0x1 + // Bit mask of PRO_MMU_WR_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS_Msk = 0x2 + // Bit PRO_MMU_WR_ACS. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS = 0x2 + + // PIF_ACCESS_MONITOR_0: register description + // Position of PIF_ACCESS_MONITOR_LOCK field. + SENSITIVE_PIF_ACCESS_MONITOR_0_PIF_ACCESS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of PIF_ACCESS_MONITOR_LOCK field. + SENSITIVE_PIF_ACCESS_MONITOR_0_PIF_ACCESS_MONITOR_LOCK_Msk = 0x1 + // Bit PIF_ACCESS_MONITOR_LOCK. + SENSITIVE_PIF_ACCESS_MONITOR_0_PIF_ACCESS_MONITOR_LOCK = 0x1 + + // PIF_ACCESS_MONITOR_1: register description + // Position of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR field. + SENSITIVE_PIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_Pos = 0x0 + // Bit mask of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR field. + SENSITIVE_PIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_Msk = 0x1 + // Bit PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR. + SENSITIVE_PIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR = 0x1 + // Position of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN field. + SENSITIVE_PIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_Pos = 0x1 + // Bit mask of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN field. + SENSITIVE_PIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_Msk = 0x2 + // Bit PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN. + SENSITIVE_PIF_ACCESS_MONITOR_1_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN = 0x2 + + // PIF_ACCESS_MONITOR_2: register description + // Position of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR field. + SENSITIVE_PIF_ACCESS_MONITOR_2_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_Pos = 0x0 + // Bit mask of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR field. + SENSITIVE_PIF_ACCESS_MONITOR_2_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_Msk = 0x1 + // Bit PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR. + SENSITIVE_PIF_ACCESS_MONITOR_2_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR = 0x1 + // Position of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE field. + SENSITIVE_PIF_ACCESS_MONITOR_2_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_Pos = 0x1 + // Bit mask of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE field. + SENSITIVE_PIF_ACCESS_MONITOR_2_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_Msk = 0x6 + + // PIF_ACCESS_MONITOR_3: register description + // Position of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR field. + SENSITIVE_PIF_ACCESS_MONITOR_3_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_Pos = 0x0 + // Bit mask of PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR field. + SENSITIVE_PIF_ACCESS_MONITOR_3_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_Msk = 0xffffffff + + // XTS_AES_KEY_UPDATE: register description + // Position of XTS_AES_KEY_UPDATE field. + SENSITIVE_XTS_AES_KEY_UPDATE_XTS_AES_KEY_UPDATE_Pos = 0x0 + // Bit mask of XTS_AES_KEY_UPDATE field. + SENSITIVE_XTS_AES_KEY_UPDATE_XTS_AES_KEY_UPDATE_Msk = 0x1 + // Bit XTS_AES_KEY_UPDATE. + SENSITIVE_XTS_AES_KEY_UPDATE_XTS_AES_KEY_UPDATE = 0x1 + + // CLOCK_GATE: register description + // Position of CLK_EN field. + SENSITIVE_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SENSITIVE_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SENSITIVE_CLOCK_GATE_CLK_EN = 0x1 + + // SENSITIVE_REG_DATE: register description + // Position of SENSITIVE_REG_DATE field. + SENSITIVE_SENSITIVE_REG_DATE_SENSITIVE_REG_DATE_Pos = 0x0 + // Bit mask of SENSITIVE_REG_DATE field. + SENSITIVE_SENSITIVE_REG_DATE_SENSITIVE_REG_DATE_Msk = 0xfffffff +) + +// Constants for SHA: SHA (Secure Hash Algorithm) Accelerator +const ( + // MODE: Initial configuration register. + // Position of MODE field. + SHA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + SHA_MODE_MODE_Msk = 0x7 + + // T_STRING: SHA 512/t configuration register 0. + // Position of T_STRING field. + SHA_T_STRING_T_STRING_Pos = 0x0 + // Bit mask of T_STRING field. + SHA_T_STRING_T_STRING_Msk = 0xffffffff + + // T_LENGTH: SHA 512/t configuration register 1. + // Position of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Pos = 0x0 + // Bit mask of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Msk = 0x3f + + // DMA_BLOCK_NUM: DMA configuration register 0. + // Position of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Pos = 0x0 + // Bit mask of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Msk = 0x3f + + // START: Typical SHA configuration register 0. + // Position of START field. + SHA_START_START_Pos = 0x1 + // Bit mask of START field. + SHA_START_START_Msk = 0xfffffffe + + // CONTINUE: Typical SHA configuration register 1. + // Position of CONTINUE field. + SHA_CONTINUE_CONTINUE_Pos = 0x1 + // Bit mask of CONTINUE field. + SHA_CONTINUE_CONTINUE_Msk = 0xfffffffe + + // BUSY: Busy register. + // Position of STATE field. + SHA_BUSY_STATE_Pos = 0x0 + // Bit mask of STATE field. + SHA_BUSY_STATE_Msk = 0x1 + // Bit STATE. + SHA_BUSY_STATE = 0x1 + + // DMA_START: DMA configuration register 1. + // Position of DMA_START field. + SHA_DMA_START_DMA_START_Pos = 0x0 + // Bit mask of DMA_START field. + SHA_DMA_START_DMA_START_Msk = 0x1 + // Bit DMA_START. + SHA_DMA_START_DMA_START = 0x1 + + // DMA_CONTINUE: DMA configuration register 2. + // Position of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Pos = 0x0 + // Bit mask of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Msk = 0x1 + // Bit DMA_CONTINUE. + SHA_DMA_CONTINUE_DMA_CONTINUE = 0x1 + + // CLEAR_IRQ: Interrupt clear register. + // Position of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT = 0x1 + + // IRQ_ENA: Interrupt enable register. + // Position of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Pos = 0x0 + // Bit mask of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Msk = 0x1 + // Bit INTERRUPT_ENA. + SHA_IRQ_ENA_INTERRUPT_ENA = 0x1 + + // DATE: Date register. + // Position of DATE field. + SHA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SHA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for SPI0: SPI (Serial Peripheral Interface) Controller 0 +const ( + // CTRL: SPI0 control register. + // Position of FDUMMY_OUT field. + SPI0_CTRL_FDUMMY_OUT_Pos = 0x3 + // Bit mask of FDUMMY_OUT field. + SPI0_CTRL_FDUMMY_OUT_Msk = 0x8 + // Bit FDUMMY_OUT. + SPI0_CTRL_FDUMMY_OUT = 0x8 + // Position of FCMD_DUAL field. + SPI0_CTRL_FCMD_DUAL_Pos = 0x7 + // Bit mask of FCMD_DUAL field. + SPI0_CTRL_FCMD_DUAL_Msk = 0x80 + // Bit FCMD_DUAL. + SPI0_CTRL_FCMD_DUAL = 0x80 + // Position of FCMD_QUAD field. + SPI0_CTRL_FCMD_QUAD_Pos = 0x8 + // Bit mask of FCMD_QUAD field. + SPI0_CTRL_FCMD_QUAD_Msk = 0x100 + // Bit FCMD_QUAD. + SPI0_CTRL_FCMD_QUAD = 0x100 + // Position of FASTRD_MODE field. + SPI0_CTRL_FASTRD_MODE_Pos = 0xd + // Bit mask of FASTRD_MODE field. + SPI0_CTRL_FASTRD_MODE_Msk = 0x2000 + // Bit FASTRD_MODE. + SPI0_CTRL_FASTRD_MODE = 0x2000 + // Position of FREAD_DUAL field. + SPI0_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI0_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI0_CTRL_FREAD_DUAL = 0x4000 + // Position of Q_POL field. + SPI0_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI0_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI0_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI0_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI0_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI0_CTRL_D_POL = 0x80000 + // Position of FREAD_QUAD field. + SPI0_CTRL_FREAD_QUAD_Pos = 0x14 + // Bit mask of FREAD_QUAD field. + SPI0_CTRL_FREAD_QUAD_Msk = 0x100000 + // Bit FREAD_QUAD. + SPI0_CTRL_FREAD_QUAD = 0x100000 + // Position of WP field. + SPI0_CTRL_WP_Pos = 0x15 + // Bit mask of WP field. + SPI0_CTRL_WP_Msk = 0x200000 + // Bit WP. + SPI0_CTRL_WP = 0x200000 + // Position of FREAD_DIO field. + SPI0_CTRL_FREAD_DIO_Pos = 0x17 + // Bit mask of FREAD_DIO field. + SPI0_CTRL_FREAD_DIO_Msk = 0x800000 + // Bit FREAD_DIO. + SPI0_CTRL_FREAD_DIO = 0x800000 + // Position of FREAD_QIO field. + SPI0_CTRL_FREAD_QIO_Pos = 0x18 + // Bit mask of FREAD_QIO field. + SPI0_CTRL_FREAD_QIO_Msk = 0x1000000 + // Bit FREAD_QIO. + SPI0_CTRL_FREAD_QIO = 0x1000000 + + // CTRL1: SPI0 control1 register. + // Position of CLK_MODE field. + SPI0_CTRL1_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI0_CTRL1_CLK_MODE_Msk = 0x3 + // Position of RXFIFO_RST field. + SPI0_CTRL1_RXFIFO_RST_Pos = 0x1e + // Bit mask of RXFIFO_RST field. + SPI0_CTRL1_RXFIFO_RST_Msk = 0x40000000 + // Bit RXFIFO_RST. + SPI0_CTRL1_RXFIFO_RST = 0x40000000 + + // CTRL2: SPI0 control2 register. + // Position of CS_SETUP_TIME field. + SPI0_CTRL2_CS_SETUP_TIME_Pos = 0x0 + // Bit mask of CS_SETUP_TIME field. + SPI0_CTRL2_CS_SETUP_TIME_Msk = 0x1f + // Position of CS_HOLD_TIME field. + SPI0_CTRL2_CS_HOLD_TIME_Pos = 0x5 + // Bit mask of CS_HOLD_TIME field. + SPI0_CTRL2_CS_HOLD_TIME_Msk = 0x3e0 + // Position of CS_HOLD_DELAY field. + SPI0_CTRL2_CS_HOLD_DELAY_Pos = 0x19 + // Bit mask of CS_HOLD_DELAY field. + SPI0_CTRL2_CS_HOLD_DELAY_Msk = 0x7e000000 + // Position of SYNC_RESET field. + SPI0_CTRL2_SYNC_RESET_Pos = 0x1f + // Bit mask of SYNC_RESET field. + SPI0_CTRL2_SYNC_RESET_Msk = 0x80000000 + // Bit SYNC_RESET. + SPI0_CTRL2_SYNC_RESET = 0x80000000 + + // CLOCK: SPI clock division control register. + // Position of CLKCNT_L field. + SPI0_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI0_CLOCK_CLKCNT_L_Msk = 0xff + // Position of CLKCNT_H field. + SPI0_CLOCK_CLKCNT_H_Pos = 0x8 + // Bit mask of CLKCNT_H field. + SPI0_CLOCK_CLKCNT_H_Msk = 0xff00 + // Position of CLKCNT_N field. + SPI0_CLOCK_CLKCNT_N_Pos = 0x10 + // Bit mask of CLKCNT_N field. + SPI0_CLOCK_CLKCNT_N_Msk = 0xff0000 + // Position of CLK_EQU_SYSCLK field. + SPI0_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI0_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI0_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI0 user register. + // Position of CS_HOLD field. + SPI0_USER_CS_HOLD_Pos = 0x6 + // Bit mask of CS_HOLD field. + SPI0_USER_CS_HOLD_Msk = 0x40 + // Bit CS_HOLD. + SPI0_USER_CS_HOLD = 0x40 + // Position of CS_SETUP field. + SPI0_USER_CS_SETUP_Pos = 0x7 + // Bit mask of CS_SETUP field. + SPI0_USER_CS_SETUP_Msk = 0x80 + // Bit CS_SETUP. + SPI0_USER_CS_SETUP = 0x80 + // Position of CK_OUT_EDGE field. + SPI0_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI0_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI0_USER_CK_OUT_EDGE = 0x200 + // Position of USR_DUMMY_IDLE field. + SPI0_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI0_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI0_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_DUMMY field. + SPI0_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI0_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI0_USER_USR_DUMMY = 0x20000000 + + // USER1: SPI0 user1 register. + // Position of USR_DUMMY_CYCLELEN field. + SPI0_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI0_USER1_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of USR_ADDR_BITLEN field. + SPI0_USER1_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of USR_ADDR_BITLEN field. + SPI0_USER1_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // USER2: SPI0 user2 register. + // Position of USR_COMMAND_VALUE field. + SPI0_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI0_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of USR_COMMAND_BITLEN field. + SPI0_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI0_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // RD_STATUS: SPI0 read control register. + // Position of WB_MODE field. + SPI0_RD_STATUS_WB_MODE_Pos = 0x10 + // Bit mask of WB_MODE field. + SPI0_RD_STATUS_WB_MODE_Msk = 0xff0000 + + // MISC: SPI0 misc register + // Position of TRANS_END field. + SPI0_MISC_TRANS_END_Pos = 0x3 + // Bit mask of TRANS_END field. + SPI0_MISC_TRANS_END_Msk = 0x8 + // Bit TRANS_END. + SPI0_MISC_TRANS_END = 0x8 + // Position of TRANS_END_INT_ENA field. + SPI0_MISC_TRANS_END_INT_ENA_Pos = 0x4 + // Bit mask of TRANS_END_INT_ENA field. + SPI0_MISC_TRANS_END_INT_ENA_Msk = 0x10 + // Bit TRANS_END_INT_ENA. + SPI0_MISC_TRANS_END_INT_ENA = 0x10 + // Position of CSPI_ST_TRANS_END field. + SPI0_MISC_CSPI_ST_TRANS_END_Pos = 0x5 + // Bit mask of CSPI_ST_TRANS_END field. + SPI0_MISC_CSPI_ST_TRANS_END_Msk = 0x20 + // Bit CSPI_ST_TRANS_END. + SPI0_MISC_CSPI_ST_TRANS_END = 0x20 + // Position of CSPI_ST_TRANS_END_INT_ENA field. + SPI0_MISC_CSPI_ST_TRANS_END_INT_ENA_Pos = 0x6 + // Bit mask of CSPI_ST_TRANS_END_INT_ENA field. + SPI0_MISC_CSPI_ST_TRANS_END_INT_ENA_Msk = 0x40 + // Bit CSPI_ST_TRANS_END_INT_ENA. + SPI0_MISC_CSPI_ST_TRANS_END_INT_ENA = 0x40 + // Position of CK_IDLE_EDGE field. + SPI0_MISC_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of CK_IDLE_EDGE field. + SPI0_MISC_CK_IDLE_EDGE_Msk = 0x200 + // Bit CK_IDLE_EDGE. + SPI0_MISC_CK_IDLE_EDGE = 0x200 + // Position of CS_KEEP_ACTIVE field. + SPI0_MISC_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of CS_KEEP_ACTIVE field. + SPI0_MISC_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit CS_KEEP_ACTIVE. + SPI0_MISC_CS_KEEP_ACTIVE = 0x400 + + // CACHE_FCTRL: SPI0 bit mode control register. + // Position of CACHE_REQ_EN field. + SPI0_CACHE_FCTRL_CACHE_REQ_EN_Pos = 0x0 + // Bit mask of CACHE_REQ_EN field. + SPI0_CACHE_FCTRL_CACHE_REQ_EN_Msk = 0x1 + // Bit CACHE_REQ_EN. + SPI0_CACHE_FCTRL_CACHE_REQ_EN = 0x1 + // Position of CACHE_USR_ADDR_4BYTE field. + SPI0_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE_Pos = 0x1 + // Bit mask of CACHE_USR_ADDR_4BYTE field. + SPI0_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE_Msk = 0x2 + // Bit CACHE_USR_ADDR_4BYTE. + SPI0_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE = 0x2 + // Position of CACHE_FLASH_USR_CMD field. + SPI0_CACHE_FCTRL_CACHE_FLASH_USR_CMD_Pos = 0x2 + // Bit mask of CACHE_FLASH_USR_CMD field. + SPI0_CACHE_FCTRL_CACHE_FLASH_USR_CMD_Msk = 0x4 + // Bit CACHE_FLASH_USR_CMD. + SPI0_CACHE_FCTRL_CACHE_FLASH_USR_CMD = 0x4 + // Position of FDIN_DUAL field. + SPI0_CACHE_FCTRL_FDIN_DUAL_Pos = 0x3 + // Bit mask of FDIN_DUAL field. + SPI0_CACHE_FCTRL_FDIN_DUAL_Msk = 0x8 + // Bit FDIN_DUAL. + SPI0_CACHE_FCTRL_FDIN_DUAL = 0x8 + // Position of FDOUT_DUAL field. + SPI0_CACHE_FCTRL_FDOUT_DUAL_Pos = 0x4 + // Bit mask of FDOUT_DUAL field. + SPI0_CACHE_FCTRL_FDOUT_DUAL_Msk = 0x10 + // Bit FDOUT_DUAL. + SPI0_CACHE_FCTRL_FDOUT_DUAL = 0x10 + // Position of FADDR_DUAL field. + SPI0_CACHE_FCTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI0_CACHE_FCTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI0_CACHE_FCTRL_FADDR_DUAL = 0x20 + // Position of FDIN_QUAD field. + SPI0_CACHE_FCTRL_FDIN_QUAD_Pos = 0x6 + // Bit mask of FDIN_QUAD field. + SPI0_CACHE_FCTRL_FDIN_QUAD_Msk = 0x40 + // Bit FDIN_QUAD. + SPI0_CACHE_FCTRL_FDIN_QUAD = 0x40 + // Position of FDOUT_QUAD field. + SPI0_CACHE_FCTRL_FDOUT_QUAD_Pos = 0x7 + // Bit mask of FDOUT_QUAD field. + SPI0_CACHE_FCTRL_FDOUT_QUAD_Msk = 0x80 + // Bit FDOUT_QUAD. + SPI0_CACHE_FCTRL_FDOUT_QUAD = 0x80 + // Position of FADDR_QUAD field. + SPI0_CACHE_FCTRL_FADDR_QUAD_Pos = 0x8 + // Bit mask of FADDR_QUAD field. + SPI0_CACHE_FCTRL_FADDR_QUAD_Msk = 0x100 + // Bit FADDR_QUAD. + SPI0_CACHE_FCTRL_FADDR_QUAD = 0x100 + + // FSM: SPI0 FSM status register + // Position of CSPI_ST field. + SPI0_FSM_CSPI_ST_Pos = 0x0 + // Bit mask of CSPI_ST field. + SPI0_FSM_CSPI_ST_Msk = 0xf + // Position of EM_ST field. + SPI0_FSM_EM_ST_Pos = 0x4 + // Bit mask of EM_ST field. + SPI0_FSM_EM_ST_Msk = 0x70 + // Position of CSPI_LOCK_DELAY_TIME field. + SPI0_FSM_CSPI_LOCK_DELAY_TIME_Pos = 0x7 + // Bit mask of CSPI_LOCK_DELAY_TIME field. + SPI0_FSM_CSPI_LOCK_DELAY_TIME_Msk = 0xf80 + + // TIMING_CALI: SPI0 timing calibration register + // Position of TIMING_CLK_ENA field. + SPI0_TIMING_CALI_TIMING_CLK_ENA_Pos = 0x0 + // Bit mask of TIMING_CLK_ENA field. + SPI0_TIMING_CALI_TIMING_CLK_ENA_Msk = 0x1 + // Bit TIMING_CLK_ENA. + SPI0_TIMING_CALI_TIMING_CLK_ENA = 0x1 + // Position of TIMING_CALI field. + SPI0_TIMING_CALI_TIMING_CALI_Pos = 0x1 + // Bit mask of TIMING_CALI field. + SPI0_TIMING_CALI_TIMING_CALI_Msk = 0x2 + // Bit TIMING_CALI. + SPI0_TIMING_CALI_TIMING_CALI = 0x2 + // Position of EXTRA_DUMMY_CYCLELEN field. + SPI0_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of EXTRA_DUMMY_CYCLELEN field. + SPI0_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + + // DIN_MODE: SPI0 input delay mode control register + // Position of DIN0_MODE field. + SPI0_DIN_MODE_DIN0_MODE_Pos = 0x0 + // Bit mask of DIN0_MODE field. + SPI0_DIN_MODE_DIN0_MODE_Msk = 0x3 + // Position of DIN1_MODE field. + SPI0_DIN_MODE_DIN1_MODE_Pos = 0x2 + // Bit mask of DIN1_MODE field. + SPI0_DIN_MODE_DIN1_MODE_Msk = 0xc + // Position of DIN2_MODE field. + SPI0_DIN_MODE_DIN2_MODE_Pos = 0x4 + // Bit mask of DIN2_MODE field. + SPI0_DIN_MODE_DIN2_MODE_Msk = 0x30 + // Position of DIN3_MODE field. + SPI0_DIN_MODE_DIN3_MODE_Pos = 0x6 + // Bit mask of DIN3_MODE field. + SPI0_DIN_MODE_DIN3_MODE_Msk = 0xc0 + + // DIN_NUM: SPI0 input delay number control register + // Position of DIN0_NUM field. + SPI0_DIN_NUM_DIN0_NUM_Pos = 0x0 + // Bit mask of DIN0_NUM field. + SPI0_DIN_NUM_DIN0_NUM_Msk = 0x1 + // Bit DIN0_NUM. + SPI0_DIN_NUM_DIN0_NUM = 0x1 + // Position of DIN1_NUM field. + SPI0_DIN_NUM_DIN1_NUM_Pos = 0x1 + // Bit mask of DIN1_NUM field. + SPI0_DIN_NUM_DIN1_NUM_Msk = 0x2 + // Bit DIN1_NUM. + SPI0_DIN_NUM_DIN1_NUM = 0x2 + // Position of DIN2_NUM field. + SPI0_DIN_NUM_DIN2_NUM_Pos = 0x2 + // Bit mask of DIN2_NUM field. + SPI0_DIN_NUM_DIN2_NUM_Msk = 0x4 + // Bit DIN2_NUM. + SPI0_DIN_NUM_DIN2_NUM = 0x4 + // Position of DIN3_NUM field. + SPI0_DIN_NUM_DIN3_NUM_Pos = 0x3 + // Bit mask of DIN3_NUM field. + SPI0_DIN_NUM_DIN3_NUM_Msk = 0x8 + // Bit DIN3_NUM. + SPI0_DIN_NUM_DIN3_NUM = 0x8 + + // DOUT_MODE: SPI0 output delay mode control register + // Position of DOUT0_MODE field. + SPI0_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + SPI0_DOUT_MODE_DOUT0_MODE_Msk = 0x1 + // Bit DOUT0_MODE. + SPI0_DOUT_MODE_DOUT0_MODE = 0x1 + // Position of DOUT1_MODE field. + SPI0_DOUT_MODE_DOUT1_MODE_Pos = 0x1 + // Bit mask of DOUT1_MODE field. + SPI0_DOUT_MODE_DOUT1_MODE_Msk = 0x2 + // Bit DOUT1_MODE. + SPI0_DOUT_MODE_DOUT1_MODE = 0x2 + // Position of DOUT2_MODE field. + SPI0_DOUT_MODE_DOUT2_MODE_Pos = 0x2 + // Bit mask of DOUT2_MODE field. + SPI0_DOUT_MODE_DOUT2_MODE_Msk = 0x4 + // Bit DOUT2_MODE. + SPI0_DOUT_MODE_DOUT2_MODE = 0x4 + // Position of DOUT3_MODE field. + SPI0_DOUT_MODE_DOUT3_MODE_Pos = 0x3 + // Bit mask of DOUT3_MODE field. + SPI0_DOUT_MODE_DOUT3_MODE_Msk = 0x8 + // Bit DOUT3_MODE. + SPI0_DOUT_MODE_DOUT3_MODE = 0x8 + + // CLOCK_GATE: SPI0 clk_gate register + // Position of CLK_EN field. + SPI0_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI0_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI0_CLOCK_GATE_CLK_EN = 0x1 + + // CORE_CLK_SEL: SPI0 module clock select register + // Position of SPI01_CLK_SEL field. + SPI0_CORE_CLK_SEL_SPI01_CLK_SEL_Pos = 0x0 + // Bit mask of SPI01_CLK_SEL field. + SPI0_CORE_CLK_SEL_SPI01_CLK_SEL_Msk = 0x3 + + // DATE: Version control register + // Position of DATE field. + SPI0_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI0_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SPI1: SPI (Serial Peripheral Interface) Controller 1 +const ( + // CMD: SPI1 memory command register + // Position of SPI1_MST_ST field. + SPI1_CMD_SPI1_MST_ST_Pos = 0x0 + // Bit mask of SPI1_MST_ST field. + SPI1_CMD_SPI1_MST_ST_Msk = 0xf + // Position of MSPI_ST field. + SPI1_CMD_MSPI_ST_Pos = 0x4 + // Bit mask of MSPI_ST field. + SPI1_CMD_MSPI_ST_Msk = 0xf0 + // Position of FLASH_PE field. + SPI1_CMD_FLASH_PE_Pos = 0x11 + // Bit mask of FLASH_PE field. + SPI1_CMD_FLASH_PE_Msk = 0x20000 + // Bit FLASH_PE. + SPI1_CMD_FLASH_PE = 0x20000 + // Position of USR field. + SPI1_CMD_USR_Pos = 0x12 + // Bit mask of USR field. + SPI1_CMD_USR_Msk = 0x40000 + // Bit USR. + SPI1_CMD_USR = 0x40000 + // Position of FLASH_HPM field. + SPI1_CMD_FLASH_HPM_Pos = 0x13 + // Bit mask of FLASH_HPM field. + SPI1_CMD_FLASH_HPM_Msk = 0x80000 + // Bit FLASH_HPM. + SPI1_CMD_FLASH_HPM = 0x80000 + // Position of FLASH_RES field. + SPI1_CMD_FLASH_RES_Pos = 0x14 + // Bit mask of FLASH_RES field. + SPI1_CMD_FLASH_RES_Msk = 0x100000 + // Bit FLASH_RES. + SPI1_CMD_FLASH_RES = 0x100000 + // Position of FLASH_DP field. + SPI1_CMD_FLASH_DP_Pos = 0x15 + // Bit mask of FLASH_DP field. + SPI1_CMD_FLASH_DP_Msk = 0x200000 + // Bit FLASH_DP. + SPI1_CMD_FLASH_DP = 0x200000 + // Position of FLASH_CE field. + SPI1_CMD_FLASH_CE_Pos = 0x16 + // Bit mask of FLASH_CE field. + SPI1_CMD_FLASH_CE_Msk = 0x400000 + // Bit FLASH_CE. + SPI1_CMD_FLASH_CE = 0x400000 + // Position of FLASH_BE field. + SPI1_CMD_FLASH_BE_Pos = 0x17 + // Bit mask of FLASH_BE field. + SPI1_CMD_FLASH_BE_Msk = 0x800000 + // Bit FLASH_BE. + SPI1_CMD_FLASH_BE = 0x800000 + // Position of FLASH_SE field. + SPI1_CMD_FLASH_SE_Pos = 0x18 + // Bit mask of FLASH_SE field. + SPI1_CMD_FLASH_SE_Msk = 0x1000000 + // Bit FLASH_SE. + SPI1_CMD_FLASH_SE = 0x1000000 + // Position of FLASH_PP field. + SPI1_CMD_FLASH_PP_Pos = 0x19 + // Bit mask of FLASH_PP field. + SPI1_CMD_FLASH_PP_Msk = 0x2000000 + // Bit FLASH_PP. + SPI1_CMD_FLASH_PP = 0x2000000 + // Position of FLASH_WRSR field. + SPI1_CMD_FLASH_WRSR_Pos = 0x1a + // Bit mask of FLASH_WRSR field. + SPI1_CMD_FLASH_WRSR_Msk = 0x4000000 + // Bit FLASH_WRSR. + SPI1_CMD_FLASH_WRSR = 0x4000000 + // Position of FLASH_RDSR field. + SPI1_CMD_FLASH_RDSR_Pos = 0x1b + // Bit mask of FLASH_RDSR field. + SPI1_CMD_FLASH_RDSR_Msk = 0x8000000 + // Bit FLASH_RDSR. + SPI1_CMD_FLASH_RDSR = 0x8000000 + // Position of FLASH_RDID field. + SPI1_CMD_FLASH_RDID_Pos = 0x1c + // Bit mask of FLASH_RDID field. + SPI1_CMD_FLASH_RDID_Msk = 0x10000000 + // Bit FLASH_RDID. + SPI1_CMD_FLASH_RDID = 0x10000000 + // Position of FLASH_WRDI field. + SPI1_CMD_FLASH_WRDI_Pos = 0x1d + // Bit mask of FLASH_WRDI field. + SPI1_CMD_FLASH_WRDI_Msk = 0x20000000 + // Bit FLASH_WRDI. + SPI1_CMD_FLASH_WRDI = 0x20000000 + // Position of FLASH_WREN field. + SPI1_CMD_FLASH_WREN_Pos = 0x1e + // Bit mask of FLASH_WREN field. + SPI1_CMD_FLASH_WREN_Msk = 0x40000000 + // Bit FLASH_WREN. + SPI1_CMD_FLASH_WREN = 0x40000000 + // Position of FLASH_READ field. + SPI1_CMD_FLASH_READ_Pos = 0x1f + // Bit mask of FLASH_READ field. + SPI1_CMD_FLASH_READ_Msk = 0x80000000 + // Bit FLASH_READ. + SPI1_CMD_FLASH_READ = 0x80000000 + + // ADDR: SPI1 address register + // Position of USR_ADDR_VALUE field. + SPI1_ADDR_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of USR_ADDR_VALUE field. + SPI1_ADDR_USR_ADDR_VALUE_Msk = 0xffffffff + + // CTRL: SPI1 control register. + // Position of FDUMMY_OUT field. + SPI1_CTRL_FDUMMY_OUT_Pos = 0x3 + // Bit mask of FDUMMY_OUT field. + SPI1_CTRL_FDUMMY_OUT_Msk = 0x8 + // Bit FDUMMY_OUT. + SPI1_CTRL_FDUMMY_OUT = 0x8 + // Position of FCMD_DUAL field. + SPI1_CTRL_FCMD_DUAL_Pos = 0x7 + // Bit mask of FCMD_DUAL field. + SPI1_CTRL_FCMD_DUAL_Msk = 0x80 + // Bit FCMD_DUAL. + SPI1_CTRL_FCMD_DUAL = 0x80 + // Position of FCMD_QUAD field. + SPI1_CTRL_FCMD_QUAD_Pos = 0x8 + // Bit mask of FCMD_QUAD field. + SPI1_CTRL_FCMD_QUAD_Msk = 0x100 + // Bit FCMD_QUAD. + SPI1_CTRL_FCMD_QUAD = 0x100 + // Position of FCS_CRC_EN field. + SPI1_CTRL_FCS_CRC_EN_Pos = 0xa + // Bit mask of FCS_CRC_EN field. + SPI1_CTRL_FCS_CRC_EN_Msk = 0x400 + // Bit FCS_CRC_EN. + SPI1_CTRL_FCS_CRC_EN = 0x400 + // Position of TX_CRC_EN field. + SPI1_CTRL_TX_CRC_EN_Pos = 0xb + // Bit mask of TX_CRC_EN field. + SPI1_CTRL_TX_CRC_EN_Msk = 0x800 + // Bit TX_CRC_EN. + SPI1_CTRL_TX_CRC_EN = 0x800 + // Position of FASTRD_MODE field. + SPI1_CTRL_FASTRD_MODE_Pos = 0xd + // Bit mask of FASTRD_MODE field. + SPI1_CTRL_FASTRD_MODE_Msk = 0x2000 + // Bit FASTRD_MODE. + SPI1_CTRL_FASTRD_MODE = 0x2000 + // Position of FREAD_DUAL field. + SPI1_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI1_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI1_CTRL_FREAD_DUAL = 0x4000 + // Position of RESANDRES field. + SPI1_CTRL_RESANDRES_Pos = 0xf + // Bit mask of RESANDRES field. + SPI1_CTRL_RESANDRES_Msk = 0x8000 + // Bit RESANDRES. + SPI1_CTRL_RESANDRES = 0x8000 + // Position of Q_POL field. + SPI1_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI1_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI1_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI1_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI1_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI1_CTRL_D_POL = 0x80000 + // Position of FREAD_QUAD field. + SPI1_CTRL_FREAD_QUAD_Pos = 0x14 + // Bit mask of FREAD_QUAD field. + SPI1_CTRL_FREAD_QUAD_Msk = 0x100000 + // Bit FREAD_QUAD. + SPI1_CTRL_FREAD_QUAD = 0x100000 + // Position of WP field. + SPI1_CTRL_WP_Pos = 0x15 + // Bit mask of WP field. + SPI1_CTRL_WP_Msk = 0x200000 + // Bit WP. + SPI1_CTRL_WP = 0x200000 + // Position of WRSR_2B field. + SPI1_CTRL_WRSR_2B_Pos = 0x16 + // Bit mask of WRSR_2B field. + SPI1_CTRL_WRSR_2B_Msk = 0x400000 + // Bit WRSR_2B. + SPI1_CTRL_WRSR_2B = 0x400000 + // Position of FREAD_DIO field. + SPI1_CTRL_FREAD_DIO_Pos = 0x17 + // Bit mask of FREAD_DIO field. + SPI1_CTRL_FREAD_DIO_Msk = 0x800000 + // Bit FREAD_DIO. + SPI1_CTRL_FREAD_DIO = 0x800000 + // Position of FREAD_QIO field. + SPI1_CTRL_FREAD_QIO_Pos = 0x18 + // Bit mask of FREAD_QIO field. + SPI1_CTRL_FREAD_QIO_Msk = 0x1000000 + // Bit FREAD_QIO. + SPI1_CTRL_FREAD_QIO = 0x1000000 + + // CTRL1: SPI1 control1 register. + // Position of CLK_MODE field. + SPI1_CTRL1_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI1_CTRL1_CLK_MODE_Msk = 0x3 + // Position of CS_HOLD_DLY_RES field. + SPI1_CTRL1_CS_HOLD_DLY_RES_Pos = 0x2 + // Bit mask of CS_HOLD_DLY_RES field. + SPI1_CTRL1_CS_HOLD_DLY_RES_Msk = 0xffc + + // CTRL2: SPI1 control2 register. + // Position of SYNC_RESET field. + SPI1_CTRL2_SYNC_RESET_Pos = 0x1f + // Bit mask of SYNC_RESET field. + SPI1_CTRL2_SYNC_RESET_Msk = 0x80000000 + // Bit SYNC_RESET. + SPI1_CTRL2_SYNC_RESET = 0x80000000 + + // CLOCK: SPI1 clock division control register. + // Position of CLKCNT_L field. + SPI1_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI1_CLOCK_CLKCNT_L_Msk = 0xff + // Position of CLKCNT_H field. + SPI1_CLOCK_CLKCNT_H_Pos = 0x8 + // Bit mask of CLKCNT_H field. + SPI1_CLOCK_CLKCNT_H_Msk = 0xff00 + // Position of CLKCNT_N field. + SPI1_CLOCK_CLKCNT_N_Pos = 0x10 + // Bit mask of CLKCNT_N field. + SPI1_CLOCK_CLKCNT_N_Msk = 0xff0000 + // Position of CLK_EQU_SYSCLK field. + SPI1_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI1_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI1_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI1 user register. + // Position of CK_OUT_EDGE field. + SPI1_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI1_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI1_USER_CK_OUT_EDGE = 0x200 + // Position of FWRITE_DUAL field. + SPI1_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI1_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI1_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI1_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI1_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI1_USER_FWRITE_QUAD = 0x2000 + // Position of FWRITE_DIO field. + SPI1_USER_FWRITE_DIO_Pos = 0xe + // Bit mask of FWRITE_DIO field. + SPI1_USER_FWRITE_DIO_Msk = 0x4000 + // Bit FWRITE_DIO. + SPI1_USER_FWRITE_DIO = 0x4000 + // Position of FWRITE_QIO field. + SPI1_USER_FWRITE_QIO_Pos = 0xf + // Bit mask of FWRITE_QIO field. + SPI1_USER_FWRITE_QIO_Msk = 0x8000 + // Bit FWRITE_QIO. + SPI1_USER_FWRITE_QIO = 0x8000 + // Position of USR_MISO_HIGHPART field. + SPI1_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI1_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI1_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI1_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI1_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI1_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI1_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI1_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI1_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI1_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI1_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI1_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI1_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI1_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI1_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI1_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI1_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI1_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI1_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI1_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI1_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI1_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI1_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI1_USER_USR_COMMAND = 0x80000000 + + // USER1: SPI1 user1 register. + // Position of USR_DUMMY_CYCLELEN field. + SPI1_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI1_USER1_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of USR_ADDR_BITLEN field. + SPI1_USER1_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of USR_ADDR_BITLEN field. + SPI1_USER1_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // USER2: SPI1 user2 register. + // Position of USR_COMMAND_VALUE field. + SPI1_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI1_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of USR_COMMAND_BITLEN field. + SPI1_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI1_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MOSI_DLEN: SPI1 send data bit length control register. + // Position of USR_MOSI_DBITLEN field. + SPI1_MOSI_DLEN_USR_MOSI_DBITLEN_Pos = 0x0 + // Bit mask of USR_MOSI_DBITLEN field. + SPI1_MOSI_DLEN_USR_MOSI_DBITLEN_Msk = 0x3ff + + // MISO_DLEN: SPI1 receive data bit length control register. + // Position of USR_MISO_DBITLEN field. + SPI1_MISO_DLEN_USR_MISO_DBITLEN_Pos = 0x0 + // Bit mask of USR_MISO_DBITLEN field. + SPI1_MISO_DLEN_USR_MISO_DBITLEN_Msk = 0x3ff + + // RD_STATUS: SPI1 status register. + // Position of STATUS field. + SPI1_RD_STATUS_STATUS_Pos = 0x0 + // Bit mask of STATUS field. + SPI1_RD_STATUS_STATUS_Msk = 0xffff + // Position of WB_MODE field. + SPI1_RD_STATUS_WB_MODE_Pos = 0x10 + // Bit mask of WB_MODE field. + SPI1_RD_STATUS_WB_MODE_Msk = 0xff0000 + + // MISC: SPI1 misc register + // Position of CS0_DIS field. + SPI1_MISC_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI1_MISC_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI1_MISC_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI1_MISC_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI1_MISC_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI1_MISC_CS1_DIS = 0x2 + // Position of CK_IDLE_EDGE field. + SPI1_MISC_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of CK_IDLE_EDGE field. + SPI1_MISC_CK_IDLE_EDGE_Msk = 0x200 + // Bit CK_IDLE_EDGE. + SPI1_MISC_CK_IDLE_EDGE = 0x200 + // Position of CS_KEEP_ACTIVE field. + SPI1_MISC_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of CS_KEEP_ACTIVE field. + SPI1_MISC_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit CS_KEEP_ACTIVE. + SPI1_MISC_CS_KEEP_ACTIVE = 0x400 + + // TX_CRC: SPI1 TX CRC data register. + // Position of DATA field. + SPI1_TX_CRC_DATA_Pos = 0x0 + // Bit mask of DATA field. + SPI1_TX_CRC_DATA_Msk = 0xffffffff + + // CACHE_FCTRL: SPI1 bit mode control register. + // Position of CACHE_USR_ADDR_4BYTE field. + SPI1_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE_Pos = 0x1 + // Bit mask of CACHE_USR_ADDR_4BYTE field. + SPI1_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE_Msk = 0x2 + // Bit CACHE_USR_ADDR_4BYTE. + SPI1_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE = 0x2 + // Position of FDIN_DUAL field. + SPI1_CACHE_FCTRL_FDIN_DUAL_Pos = 0x3 + // Bit mask of FDIN_DUAL field. + SPI1_CACHE_FCTRL_FDIN_DUAL_Msk = 0x8 + // Bit FDIN_DUAL. + SPI1_CACHE_FCTRL_FDIN_DUAL = 0x8 + // Position of FDOUT_DUAL field. + SPI1_CACHE_FCTRL_FDOUT_DUAL_Pos = 0x4 + // Bit mask of FDOUT_DUAL field. + SPI1_CACHE_FCTRL_FDOUT_DUAL_Msk = 0x10 + // Bit FDOUT_DUAL. + SPI1_CACHE_FCTRL_FDOUT_DUAL = 0x10 + // Position of FADDR_DUAL field. + SPI1_CACHE_FCTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI1_CACHE_FCTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI1_CACHE_FCTRL_FADDR_DUAL = 0x20 + // Position of FDIN_QUAD field. + SPI1_CACHE_FCTRL_FDIN_QUAD_Pos = 0x6 + // Bit mask of FDIN_QUAD field. + SPI1_CACHE_FCTRL_FDIN_QUAD_Msk = 0x40 + // Bit FDIN_QUAD. + SPI1_CACHE_FCTRL_FDIN_QUAD = 0x40 + // Position of FDOUT_QUAD field. + SPI1_CACHE_FCTRL_FDOUT_QUAD_Pos = 0x7 + // Bit mask of FDOUT_QUAD field. + SPI1_CACHE_FCTRL_FDOUT_QUAD_Msk = 0x80 + // Bit FDOUT_QUAD. + SPI1_CACHE_FCTRL_FDOUT_QUAD = 0x80 + // Position of FADDR_QUAD field. + SPI1_CACHE_FCTRL_FADDR_QUAD_Pos = 0x8 + // Bit mask of FADDR_QUAD field. + SPI1_CACHE_FCTRL_FADDR_QUAD_Msk = 0x100 + // Bit FADDR_QUAD. + SPI1_CACHE_FCTRL_FADDR_QUAD = 0x100 + + // W0: SPI1 memory data buffer0 + // Position of BUF0 field. + SPI1_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI1_W0_BUF0_Msk = 0xffffffff + + // W1: SPI1 memory data buffer1 + // Position of BUF1 field. + SPI1_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI1_W1_BUF1_Msk = 0xffffffff + + // W2: SPI1 memory data buffer2 + // Position of BUF2 field. + SPI1_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI1_W2_BUF2_Msk = 0xffffffff + + // W3: SPI1 memory data buffer3 + // Position of BUF3 field. + SPI1_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI1_W3_BUF3_Msk = 0xffffffff + + // W4: SPI1 memory data buffer4 + // Position of BUF4 field. + SPI1_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI1_W4_BUF4_Msk = 0xffffffff + + // W5: SPI1 memory data buffer5 + // Position of BUF5 field. + SPI1_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI1_W5_BUF5_Msk = 0xffffffff + + // W6: SPI1 memory data buffer6 + // Position of BUF6 field. + SPI1_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI1_W6_BUF6_Msk = 0xffffffff + + // W7: SPI1 memory data buffer7 + // Position of BUF7 field. + SPI1_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI1_W7_BUF7_Msk = 0xffffffff + + // W8: SPI1 memory data buffer8 + // Position of BUF8 field. + SPI1_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI1_W8_BUF8_Msk = 0xffffffff + + // W9: SPI1 memory data buffer9 + // Position of BUF9 field. + SPI1_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI1_W9_BUF9_Msk = 0xffffffff + + // W10: SPI1 memory data buffer10 + // Position of BUF10 field. + SPI1_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI1_W10_BUF10_Msk = 0xffffffff + + // W11: SPI1 memory data buffer11 + // Position of BUF11 field. + SPI1_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI1_W11_BUF11_Msk = 0xffffffff + + // W12: SPI1 memory data buffer12 + // Position of BUF12 field. + SPI1_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI1_W12_BUF12_Msk = 0xffffffff + + // W13: SPI1 memory data buffer13 + // Position of BUF13 field. + SPI1_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI1_W13_BUF13_Msk = 0xffffffff + + // W14: SPI1 memory data buffer14 + // Position of BUF14 field. + SPI1_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI1_W14_BUF14_Msk = 0xffffffff + + // W15: SPI1 memory data buffer15 + // Position of BUF15 field. + SPI1_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI1_W15_BUF15_Msk = 0xffffffff + + // FLASH_WAITI_CTRL: SPI1 wait idle control register + // Position of WAITI_DUMMY field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_Pos = 0x1 + // Bit mask of WAITI_DUMMY field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_Msk = 0x2 + // Bit WAITI_DUMMY. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY = 0x2 + // Position of WAITI_CMD field. + SPI1_FLASH_WAITI_CTRL_WAITI_CMD_Pos = 0x2 + // Bit mask of WAITI_CMD field. + SPI1_FLASH_WAITI_CTRL_WAITI_CMD_Msk = 0x3fc + // Position of WAITI_DUMMY_CYCLELEN field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN_Pos = 0xa + // Bit mask of WAITI_DUMMY_CYCLELEN field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN_Msk = 0xfc00 + + // FLASH_SUS_CTRL: SPI1 flash suspend control register + // Position of FLASH_PER field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_Pos = 0x0 + // Bit mask of FLASH_PER field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_Msk = 0x1 + // Bit FLASH_PER. + SPI1_FLASH_SUS_CTRL_FLASH_PER = 0x1 + // Position of FLASH_PES field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_Pos = 0x1 + // Bit mask of FLASH_PES field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_Msk = 0x2 + // Bit FLASH_PES. + SPI1_FLASH_SUS_CTRL_FLASH_PES = 0x2 + // Position of FLASH_PER_WAIT_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_WAIT_EN_Pos = 0x2 + // Bit mask of FLASH_PER_WAIT_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_WAIT_EN_Msk = 0x4 + // Bit FLASH_PER_WAIT_EN. + SPI1_FLASH_SUS_CTRL_FLASH_PER_WAIT_EN = 0x4 + // Position of FLASH_PES_WAIT_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_WAIT_EN_Pos = 0x3 + // Bit mask of FLASH_PES_WAIT_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_WAIT_EN_Msk = 0x8 + // Bit FLASH_PES_WAIT_EN. + SPI1_FLASH_SUS_CTRL_FLASH_PES_WAIT_EN = 0x8 + // Position of PES_PER_EN field. + SPI1_FLASH_SUS_CTRL_PES_PER_EN_Pos = 0x4 + // Bit mask of PES_PER_EN field. + SPI1_FLASH_SUS_CTRL_PES_PER_EN_Msk = 0x10 + // Bit PES_PER_EN. + SPI1_FLASH_SUS_CTRL_PES_PER_EN = 0x10 + // Position of FLASH_PES_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_EN_Pos = 0x5 + // Bit mask of FLASH_PES_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_EN_Msk = 0x20 + // Bit FLASH_PES_EN. + SPI1_FLASH_SUS_CTRL_FLASH_PES_EN = 0x20 + // Position of PESR_END_MSK field. + SPI1_FLASH_SUS_CTRL_PESR_END_MSK_Pos = 0x6 + // Bit mask of PESR_END_MSK field. + SPI1_FLASH_SUS_CTRL_PESR_END_MSK_Msk = 0x3fffc0 + // Position of SPI_FMEM_RD_SUS_2B field. + SPI1_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B_Pos = 0x16 + // Bit mask of SPI_FMEM_RD_SUS_2B field. + SPI1_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B_Msk = 0x400000 + // Bit SPI_FMEM_RD_SUS_2B. + SPI1_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B = 0x400000 + // Position of PER_END_EN field. + SPI1_FLASH_SUS_CTRL_PER_END_EN_Pos = 0x17 + // Bit mask of PER_END_EN field. + SPI1_FLASH_SUS_CTRL_PER_END_EN_Msk = 0x800000 + // Bit PER_END_EN. + SPI1_FLASH_SUS_CTRL_PER_END_EN = 0x800000 + // Position of PES_END_EN field. + SPI1_FLASH_SUS_CTRL_PES_END_EN_Pos = 0x18 + // Bit mask of PES_END_EN field. + SPI1_FLASH_SUS_CTRL_PES_END_EN_Msk = 0x1000000 + // Bit PES_END_EN. + SPI1_FLASH_SUS_CTRL_PES_END_EN = 0x1000000 + // Position of SUS_TIMEOUT_CNT field. + SPI1_FLASH_SUS_CTRL_SUS_TIMEOUT_CNT_Pos = 0x19 + // Bit mask of SUS_TIMEOUT_CNT field. + SPI1_FLASH_SUS_CTRL_SUS_TIMEOUT_CNT_Msk = 0xfe000000 + + // FLASH_SUS_CMD: SPI1 flash suspend command register + // Position of FLASH_PER_COMMAND field. + SPI1_FLASH_SUS_CMD_FLASH_PER_COMMAND_Pos = 0x0 + // Bit mask of FLASH_PER_COMMAND field. + SPI1_FLASH_SUS_CMD_FLASH_PER_COMMAND_Msk = 0xff + // Position of FLASH_PES_COMMAND field. + SPI1_FLASH_SUS_CMD_FLASH_PES_COMMAND_Pos = 0x8 + // Bit mask of FLASH_PES_COMMAND field. + SPI1_FLASH_SUS_CMD_FLASH_PES_COMMAND_Msk = 0xff00 + // Position of WAIT_PESR_COMMAND field. + SPI1_FLASH_SUS_CMD_WAIT_PESR_COMMAND_Pos = 0x10 + // Bit mask of WAIT_PESR_COMMAND field. + SPI1_FLASH_SUS_CMD_WAIT_PESR_COMMAND_Msk = 0xffff0000 + + // SUS_STATUS: SPI1 flash suspend status register + // Position of FLASH_SUS field. + SPI1_SUS_STATUS_FLASH_SUS_Pos = 0x0 + // Bit mask of FLASH_SUS field. + SPI1_SUS_STATUS_FLASH_SUS_Msk = 0x1 + // Bit FLASH_SUS. + SPI1_SUS_STATUS_FLASH_SUS = 0x1 + // Position of WAIT_PESR_CMD_2B field. + SPI1_SUS_STATUS_WAIT_PESR_CMD_2B_Pos = 0x1 + // Bit mask of WAIT_PESR_CMD_2B field. + SPI1_SUS_STATUS_WAIT_PESR_CMD_2B_Msk = 0x2 + // Bit WAIT_PESR_CMD_2B. + SPI1_SUS_STATUS_WAIT_PESR_CMD_2B = 0x2 + // Position of FLASH_HPM_DLY_128 field. + SPI1_SUS_STATUS_FLASH_HPM_DLY_128_Pos = 0x2 + // Bit mask of FLASH_HPM_DLY_128 field. + SPI1_SUS_STATUS_FLASH_HPM_DLY_128_Msk = 0x4 + // Bit FLASH_HPM_DLY_128. + SPI1_SUS_STATUS_FLASH_HPM_DLY_128 = 0x4 + // Position of FLASH_RES_DLY_128 field. + SPI1_SUS_STATUS_FLASH_RES_DLY_128_Pos = 0x3 + // Bit mask of FLASH_RES_DLY_128 field. + SPI1_SUS_STATUS_FLASH_RES_DLY_128_Msk = 0x8 + // Bit FLASH_RES_DLY_128. + SPI1_SUS_STATUS_FLASH_RES_DLY_128 = 0x8 + // Position of FLASH_DP_DLY_128 field. + SPI1_SUS_STATUS_FLASH_DP_DLY_128_Pos = 0x4 + // Bit mask of FLASH_DP_DLY_128 field. + SPI1_SUS_STATUS_FLASH_DP_DLY_128_Msk = 0x10 + // Bit FLASH_DP_DLY_128. + SPI1_SUS_STATUS_FLASH_DP_DLY_128 = 0x10 + // Position of FLASH_PER_DLY_128 field. + SPI1_SUS_STATUS_FLASH_PER_DLY_128_Pos = 0x5 + // Bit mask of FLASH_PER_DLY_128 field. + SPI1_SUS_STATUS_FLASH_PER_DLY_128_Msk = 0x20 + // Bit FLASH_PER_DLY_128. + SPI1_SUS_STATUS_FLASH_PER_DLY_128 = 0x20 + // Position of FLASH_PES_DLY_128 field. + SPI1_SUS_STATUS_FLASH_PES_DLY_128_Pos = 0x6 + // Bit mask of FLASH_PES_DLY_128 field. + SPI1_SUS_STATUS_FLASH_PES_DLY_128_Msk = 0x40 + // Bit FLASH_PES_DLY_128. + SPI1_SUS_STATUS_FLASH_PES_DLY_128 = 0x40 + // Position of SPI0_LOCK_EN field. + SPI1_SUS_STATUS_SPI0_LOCK_EN_Pos = 0x7 + // Bit mask of SPI0_LOCK_EN field. + SPI1_SUS_STATUS_SPI0_LOCK_EN_Msk = 0x80 + // Bit SPI0_LOCK_EN. + SPI1_SUS_STATUS_SPI0_LOCK_EN = 0x80 + + // TIMING_CALI: SPI1 timing control register + // Position of TIMING_CALI field. + SPI1_TIMING_CALI_TIMING_CALI_Pos = 0x1 + // Bit mask of TIMING_CALI field. + SPI1_TIMING_CALI_TIMING_CALI_Msk = 0x2 + // Bit TIMING_CALI. + SPI1_TIMING_CALI_TIMING_CALI = 0x2 + // Position of EXTRA_DUMMY_CYCLELEN field. + SPI1_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of EXTRA_DUMMY_CYCLELEN field. + SPI1_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + + // INT_ENA: SPI1 interrupt enable register + // Position of PER_END_INT_ENA field. + SPI1_INT_ENA_PER_END_INT_ENA_Pos = 0x0 + // Bit mask of PER_END_INT_ENA field. + SPI1_INT_ENA_PER_END_INT_ENA_Msk = 0x1 + // Bit PER_END_INT_ENA. + SPI1_INT_ENA_PER_END_INT_ENA = 0x1 + // Position of PES_END_INT_ENA field. + SPI1_INT_ENA_PES_END_INT_ENA_Pos = 0x1 + // Bit mask of PES_END_INT_ENA field. + SPI1_INT_ENA_PES_END_INT_ENA_Msk = 0x2 + // Bit PES_END_INT_ENA. + SPI1_INT_ENA_PES_END_INT_ENA = 0x2 + // Position of WPE_END_INT_ENA field. + SPI1_INT_ENA_WPE_END_INT_ENA_Pos = 0x2 + // Bit mask of WPE_END_INT_ENA field. + SPI1_INT_ENA_WPE_END_INT_ENA_Msk = 0x4 + // Bit WPE_END_INT_ENA. + SPI1_INT_ENA_WPE_END_INT_ENA = 0x4 + // Position of SLV_ST_END_INT_ENA field. + SPI1_INT_ENA_SLV_ST_END_INT_ENA_Pos = 0x3 + // Bit mask of SLV_ST_END_INT_ENA field. + SPI1_INT_ENA_SLV_ST_END_INT_ENA_Msk = 0x8 + // Bit SLV_ST_END_INT_ENA. + SPI1_INT_ENA_SLV_ST_END_INT_ENA = 0x8 + // Position of MST_ST_END_INT_ENA field. + SPI1_INT_ENA_MST_ST_END_INT_ENA_Pos = 0x4 + // Bit mask of MST_ST_END_INT_ENA field. + SPI1_INT_ENA_MST_ST_END_INT_ENA_Msk = 0x10 + // Bit MST_ST_END_INT_ENA. + SPI1_INT_ENA_MST_ST_END_INT_ENA = 0x10 + // Position of BROWN_OUT_INT_ENA field. + SPI1_INT_ENA_BROWN_OUT_INT_ENA_Pos = 0x5 + // Bit mask of BROWN_OUT_INT_ENA field. + SPI1_INT_ENA_BROWN_OUT_INT_ENA_Msk = 0x20 + // Bit BROWN_OUT_INT_ENA. + SPI1_INT_ENA_BROWN_OUT_INT_ENA = 0x20 + + // INT_CLR: SPI1 interrupt clear register + // Position of PER_END_INT_CLR field. + SPI1_INT_CLR_PER_END_INT_CLR_Pos = 0x0 + // Bit mask of PER_END_INT_CLR field. + SPI1_INT_CLR_PER_END_INT_CLR_Msk = 0x1 + // Bit PER_END_INT_CLR. + SPI1_INT_CLR_PER_END_INT_CLR = 0x1 + // Position of PES_END_INT_CLR field. + SPI1_INT_CLR_PES_END_INT_CLR_Pos = 0x1 + // Bit mask of PES_END_INT_CLR field. + SPI1_INT_CLR_PES_END_INT_CLR_Msk = 0x2 + // Bit PES_END_INT_CLR. + SPI1_INT_CLR_PES_END_INT_CLR = 0x2 + // Position of WPE_END_INT_CLR field. + SPI1_INT_CLR_WPE_END_INT_CLR_Pos = 0x2 + // Bit mask of WPE_END_INT_CLR field. + SPI1_INT_CLR_WPE_END_INT_CLR_Msk = 0x4 + // Bit WPE_END_INT_CLR. + SPI1_INT_CLR_WPE_END_INT_CLR = 0x4 + // Position of SLV_ST_END_INT_CLR field. + SPI1_INT_CLR_SLV_ST_END_INT_CLR_Pos = 0x3 + // Bit mask of SLV_ST_END_INT_CLR field. + SPI1_INT_CLR_SLV_ST_END_INT_CLR_Msk = 0x8 + // Bit SLV_ST_END_INT_CLR. + SPI1_INT_CLR_SLV_ST_END_INT_CLR = 0x8 + // Position of MST_ST_END_INT_CLR field. + SPI1_INT_CLR_MST_ST_END_INT_CLR_Pos = 0x4 + // Bit mask of MST_ST_END_INT_CLR field. + SPI1_INT_CLR_MST_ST_END_INT_CLR_Msk = 0x10 + // Bit MST_ST_END_INT_CLR. + SPI1_INT_CLR_MST_ST_END_INT_CLR = 0x10 + // Position of BROWN_OUT_INT_CLR field. + SPI1_INT_CLR_BROWN_OUT_INT_CLR_Pos = 0x5 + // Bit mask of BROWN_OUT_INT_CLR field. + SPI1_INT_CLR_BROWN_OUT_INT_CLR_Msk = 0x20 + // Bit BROWN_OUT_INT_CLR. + SPI1_INT_CLR_BROWN_OUT_INT_CLR = 0x20 + + // INT_RAW: SPI1 interrupt raw register + // Position of PER_END_INT_RAW field. + SPI1_INT_RAW_PER_END_INT_RAW_Pos = 0x0 + // Bit mask of PER_END_INT_RAW field. + SPI1_INT_RAW_PER_END_INT_RAW_Msk = 0x1 + // Bit PER_END_INT_RAW. + SPI1_INT_RAW_PER_END_INT_RAW = 0x1 + // Position of PES_END_INT_RAW field. + SPI1_INT_RAW_PES_END_INT_RAW_Pos = 0x1 + // Bit mask of PES_END_INT_RAW field. + SPI1_INT_RAW_PES_END_INT_RAW_Msk = 0x2 + // Bit PES_END_INT_RAW. + SPI1_INT_RAW_PES_END_INT_RAW = 0x2 + // Position of WPE_END_INT_RAW field. + SPI1_INT_RAW_WPE_END_INT_RAW_Pos = 0x2 + // Bit mask of WPE_END_INT_RAW field. + SPI1_INT_RAW_WPE_END_INT_RAW_Msk = 0x4 + // Bit WPE_END_INT_RAW. + SPI1_INT_RAW_WPE_END_INT_RAW = 0x4 + // Position of SLV_ST_END_INT_RAW field. + SPI1_INT_RAW_SLV_ST_END_INT_RAW_Pos = 0x3 + // Bit mask of SLV_ST_END_INT_RAW field. + SPI1_INT_RAW_SLV_ST_END_INT_RAW_Msk = 0x8 + // Bit SLV_ST_END_INT_RAW. + SPI1_INT_RAW_SLV_ST_END_INT_RAW = 0x8 + // Position of MST_ST_END_INT_RAW field. + SPI1_INT_RAW_MST_ST_END_INT_RAW_Pos = 0x4 + // Bit mask of MST_ST_END_INT_RAW field. + SPI1_INT_RAW_MST_ST_END_INT_RAW_Msk = 0x10 + // Bit MST_ST_END_INT_RAW. + SPI1_INT_RAW_MST_ST_END_INT_RAW = 0x10 + // Position of BROWN_OUT_INT_RAW field. + SPI1_INT_RAW_BROWN_OUT_INT_RAW_Pos = 0x5 + // Bit mask of BROWN_OUT_INT_RAW field. + SPI1_INT_RAW_BROWN_OUT_INT_RAW_Msk = 0x20 + // Bit BROWN_OUT_INT_RAW. + SPI1_INT_RAW_BROWN_OUT_INT_RAW = 0x20 + + // INT_ST: SPI1 interrupt status register + // Position of PER_END_INT_ST field. + SPI1_INT_ST_PER_END_INT_ST_Pos = 0x0 + // Bit mask of PER_END_INT_ST field. + SPI1_INT_ST_PER_END_INT_ST_Msk = 0x1 + // Bit PER_END_INT_ST. + SPI1_INT_ST_PER_END_INT_ST = 0x1 + // Position of PES_END_INT_ST field. + SPI1_INT_ST_PES_END_INT_ST_Pos = 0x1 + // Bit mask of PES_END_INT_ST field. + SPI1_INT_ST_PES_END_INT_ST_Msk = 0x2 + // Bit PES_END_INT_ST. + SPI1_INT_ST_PES_END_INT_ST = 0x2 + // Position of WPE_END_INT_ST field. + SPI1_INT_ST_WPE_END_INT_ST_Pos = 0x2 + // Bit mask of WPE_END_INT_ST field. + SPI1_INT_ST_WPE_END_INT_ST_Msk = 0x4 + // Bit WPE_END_INT_ST. + SPI1_INT_ST_WPE_END_INT_ST = 0x4 + // Position of SLV_ST_END_INT_ST field. + SPI1_INT_ST_SLV_ST_END_INT_ST_Pos = 0x3 + // Bit mask of SLV_ST_END_INT_ST field. + SPI1_INT_ST_SLV_ST_END_INT_ST_Msk = 0x8 + // Bit SLV_ST_END_INT_ST. + SPI1_INT_ST_SLV_ST_END_INT_ST = 0x8 + // Position of MST_ST_END_INT_ST field. + SPI1_INT_ST_MST_ST_END_INT_ST_Pos = 0x4 + // Bit mask of MST_ST_END_INT_ST field. + SPI1_INT_ST_MST_ST_END_INT_ST_Msk = 0x10 + // Bit MST_ST_END_INT_ST. + SPI1_INT_ST_MST_ST_END_INT_ST = 0x10 + // Position of BROWN_OUT_INT_ST field. + SPI1_INT_ST_BROWN_OUT_INT_ST_Pos = 0x5 + // Bit mask of BROWN_OUT_INT_ST field. + SPI1_INT_ST_BROWN_OUT_INT_ST_Msk = 0x20 + // Bit BROWN_OUT_INT_ST. + SPI1_INT_ST_BROWN_OUT_INT_ST = 0x20 + + // CLOCK_GATE: SPI1 clk_gate register + // Position of CLK_EN field. + SPI1_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI1_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI1_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version control register + // Position of DATE field. + SPI1_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI1_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SPI2: SPI (Serial Peripheral Interface) Controller 2 +const ( + // CMD: Command control register + // Position of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Pos = 0x0 + // Bit mask of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Msk = 0x3ffff + // Position of UPDATE field. + SPI2_CMD_UPDATE_Pos = 0x17 + // Bit mask of UPDATE field. + SPI2_CMD_UPDATE_Msk = 0x800000 + // Bit UPDATE. + SPI2_CMD_UPDATE = 0x800000 + // Position of USR field. + SPI2_CMD_USR_Pos = 0x18 + // Bit mask of USR field. + SPI2_CMD_USR_Msk = 0x1000000 + // Bit USR. + SPI2_CMD_USR = 0x1000000 + + // ADDR: Address value register + // Position of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Msk = 0xffffffff + + // CTRL: SPI control register + // Position of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Pos = 0x3 + // Bit mask of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Msk = 0x8 + // Bit DUMMY_OUT. + SPI2_CTRL_DUMMY_OUT = 0x8 + // Position of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI2_CTRL_FADDR_DUAL = 0x20 + // Position of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Pos = 0x6 + // Bit mask of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Msk = 0x40 + // Bit FADDR_QUAD. + SPI2_CTRL_FADDR_QUAD = 0x40 + // Position of FADDR_OCT field. + SPI2_CTRL_FADDR_OCT_Pos = 0x7 + // Bit mask of FADDR_OCT field. + SPI2_CTRL_FADDR_OCT_Msk = 0x80 + // Bit FADDR_OCT. + SPI2_CTRL_FADDR_OCT = 0x80 + // Position of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Pos = 0x8 + // Bit mask of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Msk = 0x100 + // Bit FCMD_DUAL. + SPI2_CTRL_FCMD_DUAL = 0x100 + // Position of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Pos = 0x9 + // Bit mask of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Msk = 0x200 + // Bit FCMD_QUAD. + SPI2_CTRL_FCMD_QUAD = 0x200 + // Position of FCMD_OCT field. + SPI2_CTRL_FCMD_OCT_Pos = 0xa + // Bit mask of FCMD_OCT field. + SPI2_CTRL_FCMD_OCT_Msk = 0x400 + // Bit FCMD_OCT. + SPI2_CTRL_FCMD_OCT = 0x400 + // Position of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI2_CTRL_FREAD_DUAL = 0x4000 + // Position of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Pos = 0xf + // Bit mask of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Msk = 0x8000 + // Bit FREAD_QUAD. + SPI2_CTRL_FREAD_QUAD = 0x8000 + // Position of FREAD_OCT field. + SPI2_CTRL_FREAD_OCT_Pos = 0x10 + // Bit mask of FREAD_OCT field. + SPI2_CTRL_FREAD_OCT_Msk = 0x10000 + // Bit FREAD_OCT. + SPI2_CTRL_FREAD_OCT = 0x10000 + // Position of Q_POL field. + SPI2_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI2_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI2_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI2_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI2_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI2_CTRL_D_POL = 0x80000 + // Position of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Pos = 0x14 + // Bit mask of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Msk = 0x100000 + // Bit HOLD_POL. + SPI2_CTRL_HOLD_POL = 0x100000 + // Position of WP_POL field. + SPI2_CTRL_WP_POL_Pos = 0x15 + // Bit mask of WP_POL field. + SPI2_CTRL_WP_POL_Msk = 0x200000 + // Bit WP_POL. + SPI2_CTRL_WP_POL = 0x200000 + // Position of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Pos = 0x17 + // Bit mask of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Msk = 0x1800000 + // Position of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Pos = 0x19 + // Bit mask of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Msk = 0x6000000 + + // CLOCK: SPI clock control register + // Position of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Msk = 0x3f + // Position of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Pos = 0x6 + // Bit mask of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Msk = 0xfc0 + // Position of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Pos = 0xc + // Bit mask of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Msk = 0x3f000 + // Position of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Pos = 0x12 + // Bit mask of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Msk = 0x3c0000 + // Position of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI2_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI USER control register + // Position of DOUTDIN field. + SPI2_USER_DOUTDIN_Pos = 0x0 + // Bit mask of DOUTDIN field. + SPI2_USER_DOUTDIN_Msk = 0x1 + // Bit DOUTDIN. + SPI2_USER_DOUTDIN = 0x1 + // Position of QPI_MODE field. + SPI2_USER_QPI_MODE_Pos = 0x3 + // Bit mask of QPI_MODE field. + SPI2_USER_QPI_MODE_Msk = 0x8 + // Bit QPI_MODE. + SPI2_USER_QPI_MODE = 0x8 + // Position of OPI_MODE field. + SPI2_USER_OPI_MODE_Pos = 0x4 + // Bit mask of OPI_MODE field. + SPI2_USER_OPI_MODE_Msk = 0x10 + // Bit OPI_MODE. + SPI2_USER_OPI_MODE = 0x10 + // Position of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Pos = 0x5 + // Bit mask of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Msk = 0x20 + // Bit TSCK_I_EDGE. + SPI2_USER_TSCK_I_EDGE = 0x20 + // Position of CS_HOLD field. + SPI2_USER_CS_HOLD_Pos = 0x6 + // Bit mask of CS_HOLD field. + SPI2_USER_CS_HOLD_Msk = 0x40 + // Bit CS_HOLD. + SPI2_USER_CS_HOLD = 0x40 + // Position of CS_SETUP field. + SPI2_USER_CS_SETUP_Pos = 0x7 + // Bit mask of CS_SETUP field. + SPI2_USER_CS_SETUP_Msk = 0x80 + // Bit CS_SETUP. + SPI2_USER_CS_SETUP = 0x80 + // Position of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Pos = 0x8 + // Bit mask of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Msk = 0x100 + // Bit RSCK_I_EDGE. + SPI2_USER_RSCK_I_EDGE = 0x100 + // Position of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI2_USER_CK_OUT_EDGE = 0x200 + // Position of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI2_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI2_USER_FWRITE_QUAD = 0x2000 + // Position of FWRITE_OCT field. + SPI2_USER_FWRITE_OCT_Pos = 0xe + // Bit mask of FWRITE_OCT field. + SPI2_USER_FWRITE_OCT_Msk = 0x4000 + // Bit FWRITE_OCT. + SPI2_USER_FWRITE_OCT = 0x4000 + // Position of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Pos = 0xf + // Bit mask of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Msk = 0x8000 + // Bit USR_CONF_NXT. + SPI2_USER_USR_CONF_NXT = 0x8000 + // Position of SIO field. + SPI2_USER_SIO_Pos = 0x11 + // Bit mask of SIO field. + SPI2_USER_SIO_Msk = 0x20000 + // Bit SIO. + SPI2_USER_SIO = 0x20000 + // Position of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI2_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI2_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI2_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI2_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI2_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI2_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI2_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI2_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI2_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI2_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI2_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI2_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI2_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI2_USER_USR_COMMAND = 0x80000000 + + // USER1: SPI USER control register 1 + // Position of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Msk = 0xff + // Position of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Pos = 0x10 + // Bit mask of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Msk = 0x10000 + // Bit MST_WFULL_ERR_END_EN. + SPI2_USER1_MST_WFULL_ERR_END_EN = 0x10000 + // Position of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Pos = 0x11 + // Bit mask of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Msk = 0x3e0000 + // Position of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Pos = 0x16 + // Bit mask of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Msk = 0x7c00000 + // Position of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Pos = 0x1b + // Bit mask of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Msk = 0xf8000000 + + // USER2: SPI USER control register 2 + // Position of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Pos = 0x1b + // Bit mask of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Msk = 0x8000000 + // Bit MST_REMPTY_ERR_END_EN. + SPI2_USER2_MST_REMPTY_ERR_END_EN = 0x8000000 + // Position of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MS_DLEN: SPI data bit length control register + // Position of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Pos = 0x0 + // Bit mask of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Msk = 0x3ffff + + // MISC: SPI misc register + // Position of CS0_DIS field. + SPI2_MISC_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI2_MISC_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI2_MISC_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI2_MISC_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI2_MISC_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI2_MISC_CS1_DIS = 0x2 + // Position of CS2_DIS field. + SPI2_MISC_CS2_DIS_Pos = 0x2 + // Bit mask of CS2_DIS field. + SPI2_MISC_CS2_DIS_Msk = 0x4 + // Bit CS2_DIS. + SPI2_MISC_CS2_DIS = 0x4 + // Position of CS3_DIS field. + SPI2_MISC_CS3_DIS_Pos = 0x3 + // Bit mask of CS3_DIS field. + SPI2_MISC_CS3_DIS_Msk = 0x8 + // Bit CS3_DIS. + SPI2_MISC_CS3_DIS = 0x8 + // Position of CS4_DIS field. + SPI2_MISC_CS4_DIS_Pos = 0x4 + // Bit mask of CS4_DIS field. + SPI2_MISC_CS4_DIS_Msk = 0x10 + // Bit CS4_DIS. + SPI2_MISC_CS4_DIS = 0x10 + // Position of CS5_DIS field. + SPI2_MISC_CS5_DIS_Pos = 0x5 + // Bit mask of CS5_DIS field. + SPI2_MISC_CS5_DIS_Msk = 0x20 + // Bit CS5_DIS. + SPI2_MISC_CS5_DIS = 0x20 + // Position of CK_DIS field. + SPI2_MISC_CK_DIS_Pos = 0x6 + // Bit mask of CK_DIS field. + SPI2_MISC_CK_DIS_Msk = 0x40 + // Bit CK_DIS. + SPI2_MISC_CK_DIS = 0x40 + // Position of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Pos = 0x7 + // Bit mask of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Msk = 0x1f80 + // Position of CLK_DATA_DTR_EN field. + SPI2_MISC_CLK_DATA_DTR_EN_Pos = 0x10 + // Bit mask of CLK_DATA_DTR_EN field. + SPI2_MISC_CLK_DATA_DTR_EN_Msk = 0x10000 + // Bit CLK_DATA_DTR_EN. + SPI2_MISC_CLK_DATA_DTR_EN = 0x10000 + // Position of DATA_DTR_EN field. + SPI2_MISC_DATA_DTR_EN_Pos = 0x11 + // Bit mask of DATA_DTR_EN field. + SPI2_MISC_DATA_DTR_EN_Msk = 0x20000 + // Bit DATA_DTR_EN. + SPI2_MISC_DATA_DTR_EN = 0x20000 + // Position of ADDR_DTR_EN field. + SPI2_MISC_ADDR_DTR_EN_Pos = 0x12 + // Bit mask of ADDR_DTR_EN field. + SPI2_MISC_ADDR_DTR_EN_Msk = 0x40000 + // Bit ADDR_DTR_EN. + SPI2_MISC_ADDR_DTR_EN = 0x40000 + // Position of CMD_DTR_EN field. + SPI2_MISC_CMD_DTR_EN_Pos = 0x13 + // Bit mask of CMD_DTR_EN field. + SPI2_MISC_CMD_DTR_EN_Msk = 0x80000 + // Bit CMD_DTR_EN. + SPI2_MISC_CMD_DTR_EN = 0x80000 + // Position of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Pos = 0x17 + // Bit mask of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Msk = 0x800000 + // Bit SLAVE_CS_POL. + SPI2_MISC_SLAVE_CS_POL = 0x800000 + // Position of DQS_IDLE_EDGE field. + SPI2_MISC_DQS_IDLE_EDGE_Pos = 0x18 + // Bit mask of DQS_IDLE_EDGE field. + SPI2_MISC_DQS_IDLE_EDGE_Msk = 0x1000000 + // Bit DQS_IDLE_EDGE. + SPI2_MISC_DQS_IDLE_EDGE = 0x1000000 + // Position of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Pos = 0x1d + // Bit mask of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Msk = 0x20000000 + // Bit CK_IDLE_EDGE. + SPI2_MISC_CK_IDLE_EDGE = 0x20000000 + // Position of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Pos = 0x1e + // Bit mask of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Msk = 0x40000000 + // Bit CS_KEEP_ACTIVE. + SPI2_MISC_CS_KEEP_ACTIVE = 0x40000000 + // Position of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Pos = 0x1f + // Bit mask of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Msk = 0x80000000 + // Bit QUAD_DIN_PIN_SWAP. + SPI2_MISC_QUAD_DIN_PIN_SWAP = 0x80000000 + + // DIN_MODE: SPI input delay mode configuration + // Position of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Pos = 0x0 + // Bit mask of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Msk = 0x3 + // Position of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Pos = 0x2 + // Bit mask of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Msk = 0xc + // Position of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Pos = 0x4 + // Bit mask of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Msk = 0x30 + // Position of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Pos = 0x6 + // Bit mask of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Msk = 0xc0 + // Position of DIN4_MODE field. + SPI2_DIN_MODE_DIN4_MODE_Pos = 0x8 + // Bit mask of DIN4_MODE field. + SPI2_DIN_MODE_DIN4_MODE_Msk = 0x300 + // Position of DIN5_MODE field. + SPI2_DIN_MODE_DIN5_MODE_Pos = 0xa + // Bit mask of DIN5_MODE field. + SPI2_DIN_MODE_DIN5_MODE_Msk = 0xc00 + // Position of DIN6_MODE field. + SPI2_DIN_MODE_DIN6_MODE_Pos = 0xc + // Bit mask of DIN6_MODE field. + SPI2_DIN_MODE_DIN6_MODE_Msk = 0x3000 + // Position of DIN7_MODE field. + SPI2_DIN_MODE_DIN7_MODE_Pos = 0xe + // Bit mask of DIN7_MODE field. + SPI2_DIN_MODE_DIN7_MODE_Msk = 0xc000 + // Position of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Pos = 0x10 + // Bit mask of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Msk = 0x10000 + // Bit TIMING_HCLK_ACTIVE. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE = 0x10000 + + // DIN_NUM: SPI input delay number configuration + // Position of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Pos = 0x0 + // Bit mask of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Msk = 0x3 + // Position of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Pos = 0x2 + // Bit mask of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Msk = 0xc + // Position of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Pos = 0x4 + // Bit mask of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Msk = 0x30 + // Position of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Pos = 0x6 + // Bit mask of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Msk = 0xc0 + // Position of DIN4_NUM field. + SPI2_DIN_NUM_DIN4_NUM_Pos = 0x8 + // Bit mask of DIN4_NUM field. + SPI2_DIN_NUM_DIN4_NUM_Msk = 0x300 + // Position of DIN5_NUM field. + SPI2_DIN_NUM_DIN5_NUM_Pos = 0xa + // Bit mask of DIN5_NUM field. + SPI2_DIN_NUM_DIN5_NUM_Msk = 0xc00 + // Position of DIN6_NUM field. + SPI2_DIN_NUM_DIN6_NUM_Pos = 0xc + // Bit mask of DIN6_NUM field. + SPI2_DIN_NUM_DIN6_NUM_Msk = 0x3000 + // Position of DIN7_NUM field. + SPI2_DIN_NUM_DIN7_NUM_Pos = 0xe + // Bit mask of DIN7_NUM field. + SPI2_DIN_NUM_DIN7_NUM_Msk = 0xc000 + + // DOUT_MODE: SPI output delay mode configuration + // Position of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Msk = 0x1 + // Bit DOUT0_MODE. + SPI2_DOUT_MODE_DOUT0_MODE = 0x1 + // Position of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Pos = 0x1 + // Bit mask of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Msk = 0x2 + // Bit DOUT1_MODE. + SPI2_DOUT_MODE_DOUT1_MODE = 0x2 + // Position of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Pos = 0x2 + // Bit mask of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Msk = 0x4 + // Bit DOUT2_MODE. + SPI2_DOUT_MODE_DOUT2_MODE = 0x4 + // Position of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Pos = 0x3 + // Bit mask of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Msk = 0x8 + // Bit DOUT3_MODE. + SPI2_DOUT_MODE_DOUT3_MODE = 0x8 + // Position of DOUT4_MODE field. + SPI2_DOUT_MODE_DOUT4_MODE_Pos = 0x4 + // Bit mask of DOUT4_MODE field. + SPI2_DOUT_MODE_DOUT4_MODE_Msk = 0x10 + // Bit DOUT4_MODE. + SPI2_DOUT_MODE_DOUT4_MODE = 0x10 + // Position of DOUT5_MODE field. + SPI2_DOUT_MODE_DOUT5_MODE_Pos = 0x5 + // Bit mask of DOUT5_MODE field. + SPI2_DOUT_MODE_DOUT5_MODE_Msk = 0x20 + // Bit DOUT5_MODE. + SPI2_DOUT_MODE_DOUT5_MODE = 0x20 + // Position of DOUT6_MODE field. + SPI2_DOUT_MODE_DOUT6_MODE_Pos = 0x6 + // Bit mask of DOUT6_MODE field. + SPI2_DOUT_MODE_DOUT6_MODE_Msk = 0x40 + // Bit DOUT6_MODE. + SPI2_DOUT_MODE_DOUT6_MODE = 0x40 + // Position of DOUT7_MODE field. + SPI2_DOUT_MODE_DOUT7_MODE_Pos = 0x7 + // Bit mask of DOUT7_MODE field. + SPI2_DOUT_MODE_DOUT7_MODE_Msk = 0x80 + // Bit DOUT7_MODE. + SPI2_DOUT_MODE_DOUT7_MODE = 0x80 + // Position of D_DQS_MODE field. + SPI2_DOUT_MODE_D_DQS_MODE_Pos = 0x8 + // Bit mask of D_DQS_MODE field. + SPI2_DOUT_MODE_D_DQS_MODE_Msk = 0x100 + // Bit D_DQS_MODE. + SPI2_DOUT_MODE_D_DQS_MODE = 0x100 + + // DMA_CONF: SPI DMA control register + // Position of DMA_OUTFIFO_EMPTY field. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY_Pos = 0x0 + // Bit mask of DMA_OUTFIFO_EMPTY field. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY_Msk = 0x1 + // Bit DMA_OUTFIFO_EMPTY. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY = 0x1 + // Position of DMA_INFIFO_FULL field. + SPI2_DMA_CONF_DMA_INFIFO_FULL_Pos = 0x1 + // Bit mask of DMA_INFIFO_FULL field. + SPI2_DMA_CONF_DMA_INFIFO_FULL_Msk = 0x2 + // Bit DMA_INFIFO_FULL. + SPI2_DMA_CONF_DMA_INFIFO_FULL = 0x2 + // Position of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Pos = 0x12 + // Bit mask of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Msk = 0x40000 + // Bit DMA_SLV_SEG_TRANS_EN. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN = 0x40000 + // Position of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Pos = 0x13 + // Bit mask of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Msk = 0x80000 + // Bit SLV_RX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN = 0x80000 + // Position of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Pos = 0x14 + // Bit mask of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Msk = 0x100000 + // Bit SLV_TX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN = 0x100000 + // Position of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Pos = 0x15 + // Bit mask of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Msk = 0x200000 + // Bit RX_EOF_EN. + SPI2_DMA_CONF_RX_EOF_EN = 0x200000 + // Position of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Pos = 0x1b + // Bit mask of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Msk = 0x8000000 + // Bit DMA_RX_ENA. + SPI2_DMA_CONF_DMA_RX_ENA = 0x8000000 + // Position of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Pos = 0x1c + // Bit mask of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Msk = 0x10000000 + // Bit DMA_TX_ENA. + SPI2_DMA_CONF_DMA_TX_ENA = 0x10000000 + // Position of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Pos = 0x1d + // Bit mask of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Msk = 0x20000000 + // Bit RX_AFIFO_RST. + SPI2_DMA_CONF_RX_AFIFO_RST = 0x20000000 + // Position of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Pos = 0x1e + // Bit mask of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Msk = 0x40000000 + // Bit BUF_AFIFO_RST. + SPI2_DMA_CONF_BUF_AFIFO_RST = 0x40000000 + // Position of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Pos = 0x1f + // Bit mask of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Msk = 0x80000000 + // Bit DMA_AFIFO_RST. + SPI2_DMA_CONF_DMA_AFIFO_RST = 0x80000000 + + // DMA_INT_ENA: SPI interrupt enable register + // Position of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA = 0x2 + // Position of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA = 0x4 + // Position of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA = 0x8 + // Position of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Msk = 0x10 + // Bit SLV_CMD7_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA = 0x10 + // Position of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Msk = 0x20 + // Bit SLV_CMD8_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA = 0x20 + // Position of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Msk = 0x40 + // Bit SLV_CMD9_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA = 0x40 + // Position of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Msk = 0x80 + // Bit SLV_CMDA_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA = 0x800 + // Position of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Msk = 0x1000 + // Bit TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA = 0x8000 + // Position of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA = 0x40000 + // Position of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Pos = 0x13 + // Bit mask of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Msk = 0x80000 + // Bit APP2_INT_ENA. + SPI2_DMA_INT_ENA_APP2_INT_ENA = 0x80000 + // Position of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Pos = 0x14 + // Bit mask of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Msk = 0x100000 + // Bit APP1_INT_ENA. + SPI2_DMA_INT_ENA_APP1_INT_ENA = 0x100000 + + // DMA_INT_CLR: SPI interrupt clear register + // Position of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR = 0x2 + // Position of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Msk = 0x4 + // Bit SLV_EX_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR = 0x4 + // Position of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Msk = 0x8 + // Bit SLV_EN_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR = 0x8 + // Position of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Msk = 0x10 + // Bit SLV_CMD7_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR = 0x10 + // Position of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Msk = 0x20 + // Bit SLV_CMD8_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR = 0x20 + // Position of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Msk = 0x40 + // Bit SLV_CMD9_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR = 0x40 + // Position of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Msk = 0x80 + // Bit SLV_CMDA_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR = 0x80 + // Position of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR = 0x100 + // Position of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR = 0x200 + // Position of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR = 0x400 + // Position of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR = 0x800 + // Position of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Pos = 0xc + // Bit mask of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Msk = 0x1000 + // Bit TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR = 0x2000 + // Position of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR = 0x8000 + // Position of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR = 0x40000 + // Position of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Pos = 0x13 + // Bit mask of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Msk = 0x80000 + // Bit APP2_INT_CLR. + SPI2_DMA_INT_CLR_APP2_INT_CLR = 0x80000 + // Position of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Pos = 0x14 + // Bit mask of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Msk = 0x100000 + // Bit APP1_INT_CLR. + SPI2_DMA_INT_CLR_APP1_INT_CLR = 0x100000 + + // DMA_INT_RAW: SPI interrupt raw register + // Position of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW = 0x2 + // Position of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Msk = 0x4 + // Bit SLV_EX_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW = 0x4 + // Position of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Msk = 0x8 + // Bit SLV_EN_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW = 0x8 + // Position of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Msk = 0x10 + // Bit SLV_CMD7_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW = 0x10 + // Position of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Msk = 0x20 + // Bit SLV_CMD8_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW = 0x20 + // Position of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Msk = 0x40 + // Bit SLV_CMD9_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW = 0x40 + // Position of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Msk = 0x80 + // Bit SLV_CMDA_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW = 0x80 + // Position of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW = 0x100 + // Position of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW = 0x200 + // Position of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW = 0x400 + // Position of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW = 0x800 + // Position of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Pos = 0xc + // Bit mask of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Msk = 0x1000 + // Bit TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW = 0x2000 + // Position of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW = 0x8000 + // Position of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW = 0x40000 + // Position of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Pos = 0x13 + // Bit mask of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Msk = 0x80000 + // Bit APP2_INT_RAW. + SPI2_DMA_INT_RAW_APP2_INT_RAW = 0x80000 + // Position of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Pos = 0x14 + // Bit mask of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Msk = 0x100000 + // Bit APP1_INT_RAW. + SPI2_DMA_INT_RAW_APP1_INT_RAW = 0x100000 + + // DMA_INT_ST: SPI interrupt status register + // Position of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST = 0x2 + // Position of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST = 0x4 + // Position of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST = 0x8 + // Position of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Msk = 0x10 + // Bit SLV_CMD7_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST = 0x10 + // Position of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Msk = 0x20 + // Bit SLV_CMD8_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST = 0x20 + // Position of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Msk = 0x40 + // Bit SLV_CMD9_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST = 0x40 + // Position of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Msk = 0x80 + // Bit SLV_CMDA_INT_ST. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST = 0x800 + // Position of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Msk = 0x1000 + // Bit TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ST. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST = 0x8000 + // Position of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST = 0x40000 + // Position of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Pos = 0x13 + // Bit mask of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Msk = 0x80000 + // Bit APP2_INT_ST. + SPI2_DMA_INT_ST_APP2_INT_ST = 0x80000 + // Position of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Pos = 0x14 + // Bit mask of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Msk = 0x100000 + // Bit APP1_INT_ST. + SPI2_DMA_INT_ST_APP1_INT_ST = 0x100000 + + // DMA_INT_SET: SPI interrupt software set register + // Position of DMA_INFIFO_FULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_SET. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_SET. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET = 0x2 + // Position of SLV_EX_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET_Msk = 0x4 + // Bit SLV_EX_QPI_INT_SET. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET = 0x4 + // Position of SLV_EN_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET_Msk = 0x8 + // Bit SLV_EN_QPI_INT_SET. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET = 0x8 + // Position of SLV_CMD7_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET_Msk = 0x10 + // Bit SLV_CMD7_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET = 0x10 + // Position of SLV_CMD8_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET_Msk = 0x20 + // Bit SLV_CMD8_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET = 0x20 + // Position of SLV_CMD9_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET_Msk = 0x40 + // Bit SLV_CMD9_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET = 0x40 + // Position of SLV_CMDA_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET_Msk = 0x80 + // Bit SLV_CMDA_INT_SET. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET = 0x80 + // Position of SLV_RD_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET = 0x100 + // Position of SLV_WR_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET = 0x200 + // Position of SLV_RD_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET = 0x400 + // Position of SLV_WR_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET = 0x800 + // Position of TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET_Pos = 0xc + // Bit mask of TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET_Msk = 0x1000 + // Bit TRANS_DONE_INT_SET. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_SET. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET = 0x2000 + // Position of SEG_MAGIC_ERR_INT_SET field. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_SET field. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_SET. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_SET. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET = 0x8000 + // Position of SLV_CMD_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_SET. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_SET. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET = 0x40000 + // Position of APP2_INT_SET field. + SPI2_DMA_INT_SET_APP2_INT_SET_Pos = 0x13 + // Bit mask of APP2_INT_SET field. + SPI2_DMA_INT_SET_APP2_INT_SET_Msk = 0x80000 + // Bit APP2_INT_SET. + SPI2_DMA_INT_SET_APP2_INT_SET = 0x80000 + // Position of APP1_INT_SET field. + SPI2_DMA_INT_SET_APP1_INT_SET_Pos = 0x14 + // Bit mask of APP1_INT_SET field. + SPI2_DMA_INT_SET_APP1_INT_SET_Msk = 0x100000 + // Bit APP1_INT_SET. + SPI2_DMA_INT_SET_APP1_INT_SET = 0x100000 + + // W0: SPI CPU-controlled buffer0 + // Position of BUF0 field. + SPI2_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI2_W0_BUF0_Msk = 0xffffffff + + // W1: SPI CPU-controlled buffer1 + // Position of BUF1 field. + SPI2_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI2_W1_BUF1_Msk = 0xffffffff + + // W2: SPI CPU-controlled buffer2 + // Position of BUF2 field. + SPI2_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI2_W2_BUF2_Msk = 0xffffffff + + // W3: SPI CPU-controlled buffer3 + // Position of BUF3 field. + SPI2_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI2_W3_BUF3_Msk = 0xffffffff + + // W4: SPI CPU-controlled buffer4 + // Position of BUF4 field. + SPI2_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI2_W4_BUF4_Msk = 0xffffffff + + // W5: SPI CPU-controlled buffer5 + // Position of BUF5 field. + SPI2_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI2_W5_BUF5_Msk = 0xffffffff + + // W6: SPI CPU-controlled buffer6 + // Position of BUF6 field. + SPI2_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI2_W6_BUF6_Msk = 0xffffffff + + // W7: SPI CPU-controlled buffer7 + // Position of BUF7 field. + SPI2_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI2_W7_BUF7_Msk = 0xffffffff + + // W8: SPI CPU-controlled buffer8 + // Position of BUF8 field. + SPI2_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI2_W8_BUF8_Msk = 0xffffffff + + // W9: SPI CPU-controlled buffer9 + // Position of BUF9 field. + SPI2_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI2_W9_BUF9_Msk = 0xffffffff + + // W10: SPI CPU-controlled buffer10 + // Position of BUF10 field. + SPI2_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI2_W10_BUF10_Msk = 0xffffffff + + // W11: SPI CPU-controlled buffer11 + // Position of BUF11 field. + SPI2_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI2_W11_BUF11_Msk = 0xffffffff + + // W12: SPI CPU-controlled buffer12 + // Position of BUF12 field. + SPI2_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI2_W12_BUF12_Msk = 0xffffffff + + // W13: SPI CPU-controlled buffer13 + // Position of BUF13 field. + SPI2_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI2_W13_BUF13_Msk = 0xffffffff + + // W14: SPI CPU-controlled buffer14 + // Position of BUF14 field. + SPI2_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI2_W14_BUF14_Msk = 0xffffffff + + // W15: SPI CPU-controlled buffer15 + // Position of BUF15 field. + SPI2_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI2_W15_BUF15_Msk = 0xffffffff + + // SLAVE: SPI slave control register + // Position of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Msk = 0x3 + // Position of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Pos = 0x2 + // Bit mask of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Msk = 0x4 + // Bit CLK_MODE_13. + SPI2_SLAVE_CLK_MODE_13 = 0x4 + // Position of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Pos = 0x3 + // Bit mask of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Msk = 0x8 + // Bit RSCK_DATA_OUT. + SPI2_SLAVE_RSCK_DATA_OUT = 0x8 + // Position of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Pos = 0x8 + // Bit mask of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Msk = 0x100 + // Bit SLV_RDDMA_BITLEN_EN. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN = 0x100 + // Position of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Pos = 0x9 + // Bit mask of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Msk = 0x200 + // Bit SLV_WRDMA_BITLEN_EN. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN = 0x200 + // Position of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Pos = 0xa + // Bit mask of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Msk = 0x400 + // Bit SLV_RDBUF_BITLEN_EN. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN = 0x400 + // Position of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Pos = 0xb + // Bit mask of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Msk = 0x800 + // Bit SLV_WRBUF_BITLEN_EN. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN = 0x800 + // Position of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Pos = 0x16 + // Bit mask of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Msk = 0x3c00000 + // Position of MODE field. + SPI2_SLAVE_MODE_Pos = 0x1a + // Bit mask of MODE field. + SPI2_SLAVE_MODE_Msk = 0x4000000 + // Bit MODE. + SPI2_SLAVE_MODE = 0x4000000 + // Position of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Pos = 0x1b + // Bit mask of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Msk = 0x8000000 + // Bit SOFT_RESET. + SPI2_SLAVE_SOFT_RESET = 0x8000000 + // Position of USR_CONF field. + SPI2_SLAVE_USR_CONF_Pos = 0x1c + // Bit mask of USR_CONF field. + SPI2_SLAVE_USR_CONF_Msk = 0x10000000 + // Bit USR_CONF. + SPI2_SLAVE_USR_CONF = 0x10000000 + + // SLAVE1: SPI slave control register 1 + // Position of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Pos = 0x0 + // Bit mask of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Msk = 0x3ffff + // Position of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Pos = 0x12 + // Bit mask of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Msk = 0x3fc0000 + // Position of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Pos = 0x1a + // Bit mask of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Msk = 0xfc000000 + + // CLK_GATE: SPI module clock and register clock control + // Position of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI2_CLK_GATE_CLK_EN = 0x1 + // Position of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Pos = 0x1 + // Bit mask of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Msk = 0x2 + // Bit MST_CLK_ACTIVE. + SPI2_CLK_GATE_MST_CLK_ACTIVE = 0x2 + // Position of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Pos = 0x2 + // Bit mask of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Msk = 0x4 + // Bit MST_CLK_SEL. + SPI2_CLK_GATE_MST_CLK_SEL = 0x4 + + // DATE: Version control + // Position of DATE field. + SPI2_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI2_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SYSTEM: System Configuration Registers +const ( + // CPU_PERI_CLK_EN: cpu_peripheral clock gating register + // Position of CLK_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG_Pos = 0x6 + // Bit mask of CLK_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG_Msk = 0x40 + // Bit CLK_EN_ASSIST_DEBUG. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG = 0x40 + // Position of CLK_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO_Pos = 0x7 + // Bit mask of CLK_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO_Msk = 0x80 + // Bit CLK_EN_DEDICATED_GPIO. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO = 0x80 + + // CPU_PERI_RST_EN: cpu_peripheral reset register + // Position of RST_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG_Pos = 0x6 + // Bit mask of RST_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG_Msk = 0x40 + // Bit RST_EN_ASSIST_DEBUG. + SYSTEM_CPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG = 0x40 + // Position of RST_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO_Pos = 0x7 + // Bit mask of RST_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO_Msk = 0x80 + // Bit RST_EN_DEDICATED_GPIO. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO = 0x80 + + // CPU_PER_CONF: cpu clock config register + // Position of CPUPERIOD_SEL field. + SYSTEM_CPU_PER_CONF_CPUPERIOD_SEL_Pos = 0x0 + // Bit mask of CPUPERIOD_SEL field. + SYSTEM_CPU_PER_CONF_CPUPERIOD_SEL_Msk = 0x3 + // Position of PLL_FREQ_SEL field. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL_Pos = 0x2 + // Bit mask of PLL_FREQ_SEL field. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL_Msk = 0x4 + // Bit PLL_FREQ_SEL. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL = 0x4 + // Position of CPU_WAIT_MODE_FORCE_ON field. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON_Pos = 0x3 + // Bit mask of CPU_WAIT_MODE_FORCE_ON field. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON_Msk = 0x8 + // Bit CPU_WAIT_MODE_FORCE_ON. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON = 0x8 + // Position of CPU_WAITI_DELAY_NUM field. + SYSTEM_CPU_PER_CONF_CPU_WAITI_DELAY_NUM_Pos = 0x4 + // Bit mask of CPU_WAITI_DELAY_NUM field. + SYSTEM_CPU_PER_CONF_CPU_WAITI_DELAY_NUM_Msk = 0xf0 + + // MEM_PD_MASK: memory power down mask register + // Position of LSLP_MEM_PD_MASK field. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK_Pos = 0x0 + // Bit mask of LSLP_MEM_PD_MASK field. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK_Msk = 0x1 + // Bit LSLP_MEM_PD_MASK. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK = 0x1 + + // PERIP_CLK_EN0: peripheral clock gating register + // Position of SPI01_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN_Pos = 0x1 + // Bit mask of SPI01_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN_Msk = 0x2 + // Bit SPI01_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN = 0x2 + // Position of UART_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN_Pos = 0x2 + // Bit mask of UART_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN_Msk = 0x4 + // Bit UART_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN = 0x4 + // Position of UART1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN_Pos = 0x5 + // Bit mask of UART1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN_Msk = 0x20 + // Bit UART1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN = 0x20 + // Position of SPI2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN_Pos = 0x6 + // Bit mask of SPI2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN_Msk = 0x40 + // Bit SPI2_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN = 0x40 + // Position of I2C_EXT0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN_Pos = 0x7 + // Bit mask of I2C_EXT0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN_Msk = 0x80 + // Bit I2C_EXT0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN = 0x80 + // Position of LEDC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN_Pos = 0xb + // Bit mask of LEDC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN_Msk = 0x800 + // Bit LEDC_CLK_EN. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN = 0x800 + // Position of TIMERGROUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN_Pos = 0xd + // Bit mask of TIMERGROUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN_Msk = 0x2000 + // Bit TIMERGROUP_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN = 0x2000 + // Position of UART_MEM_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN_Pos = 0x18 + // Bit mask of UART_MEM_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN_Msk = 0x1000000 + // Bit UART_MEM_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN = 0x1000000 + // Position of APB_SARADC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN_Pos = 0x1c + // Bit mask of APB_SARADC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN_Msk = 0x10000000 + // Bit APB_SARADC_CLK_EN. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN = 0x10000000 + // Position of SYSTIMER_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN_Pos = 0x1d + // Bit mask of SYSTIMER_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN_Msk = 0x20000000 + // Bit SYSTIMER_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN = 0x20000000 + // Position of ADC2_ARB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN_Pos = 0x1e + // Bit mask of ADC2_ARB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN_Msk = 0x40000000 + // Bit ADC2_ARB_CLK_EN. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN = 0x40000000 + + // PERIP_CLK_EN1: peripheral clock gating register + // Position of CRYPTO_ECC_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_ECC_CLK_EN_Pos = 0x1 + // Bit mask of CRYPTO_ECC_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_ECC_CLK_EN_Msk = 0x2 + // Bit CRYPTO_ECC_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_ECC_CLK_EN = 0x2 + // Position of CRYPTO_SHA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN_Pos = 0x2 + // Bit mask of CRYPTO_SHA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN_Msk = 0x4 + // Bit CRYPTO_SHA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN = 0x4 + // Position of DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_DMA_CLK_EN_Pos = 0x6 + // Bit mask of DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_DMA_CLK_EN_Msk = 0x40 + // Bit DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_DMA_CLK_EN = 0x40 + // Position of TSENS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_TSENS_CLK_EN_Pos = 0xa + // Bit mask of TSENS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_TSENS_CLK_EN_Msk = 0x400 + // Bit TSENS_CLK_EN. + SYSTEM_PERIP_CLK_EN1_TSENS_CLK_EN = 0x400 + + // PERIP_RST_EN0: reserved + // Position of SPI01_RST field. + SYSTEM_PERIP_RST_EN0_SPI01_RST_Pos = 0x1 + // Bit mask of SPI01_RST field. + SYSTEM_PERIP_RST_EN0_SPI01_RST_Msk = 0x2 + // Bit SPI01_RST. + SYSTEM_PERIP_RST_EN0_SPI01_RST = 0x2 + // Position of UART_RST field. + SYSTEM_PERIP_RST_EN0_UART_RST_Pos = 0x2 + // Bit mask of UART_RST field. + SYSTEM_PERIP_RST_EN0_UART_RST_Msk = 0x4 + // Bit UART_RST. + SYSTEM_PERIP_RST_EN0_UART_RST = 0x4 + // Position of UART1_RST field. + SYSTEM_PERIP_RST_EN0_UART1_RST_Pos = 0x5 + // Bit mask of UART1_RST field. + SYSTEM_PERIP_RST_EN0_UART1_RST_Msk = 0x20 + // Bit UART1_RST. + SYSTEM_PERIP_RST_EN0_UART1_RST = 0x20 + // Position of SPI2_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_RST_Pos = 0x6 + // Bit mask of SPI2_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_RST_Msk = 0x40 + // Bit SPI2_RST. + SYSTEM_PERIP_RST_EN0_SPI2_RST = 0x40 + // Position of I2C_EXT0_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST_Pos = 0x7 + // Bit mask of I2C_EXT0_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST_Msk = 0x80 + // Bit I2C_EXT0_RST. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST = 0x80 + // Position of LEDC_RST field. + SYSTEM_PERIP_RST_EN0_LEDC_RST_Pos = 0xb + // Bit mask of LEDC_RST field. + SYSTEM_PERIP_RST_EN0_LEDC_RST_Msk = 0x800 + // Bit LEDC_RST. + SYSTEM_PERIP_RST_EN0_LEDC_RST = 0x800 + // Position of TIMERGROUP_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST_Pos = 0xd + // Bit mask of TIMERGROUP_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST_Msk = 0x2000 + // Bit TIMERGROUP_RST. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST = 0x2000 + // Position of UART_MEM_RST field. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST_Pos = 0x18 + // Bit mask of UART_MEM_RST field. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST_Msk = 0x1000000 + // Bit UART_MEM_RST. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST = 0x1000000 + // Position of APB_SARADC_RST field. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST_Pos = 0x1c + // Bit mask of APB_SARADC_RST field. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST_Msk = 0x10000000 + // Bit APB_SARADC_RST. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST = 0x10000000 + // Position of SYSTIMER_RST field. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST_Pos = 0x1d + // Bit mask of SYSTIMER_RST field. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST_Msk = 0x20000000 + // Bit SYSTIMER_RST. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST = 0x20000000 + // Position of ADC2_ARB_RST field. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST_Pos = 0x1e + // Bit mask of ADC2_ARB_RST field. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST_Msk = 0x40000000 + // Bit ADC2_ARB_RST. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST = 0x40000000 + + // PERIP_RST_EN1: peripheral reset register + // Position of CRYPTO_ECC_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_ECC_RST_Pos = 0x1 + // Bit mask of CRYPTO_ECC_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_ECC_RST_Msk = 0x2 + // Bit CRYPTO_ECC_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_ECC_RST = 0x2 + // Position of CRYPTO_SHA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST_Pos = 0x2 + // Bit mask of CRYPTO_SHA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST_Msk = 0x4 + // Bit CRYPTO_SHA_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST = 0x4 + // Position of DMA_RST field. + SYSTEM_PERIP_RST_EN1_DMA_RST_Pos = 0x6 + // Bit mask of DMA_RST field. + SYSTEM_PERIP_RST_EN1_DMA_RST_Msk = 0x40 + // Bit DMA_RST. + SYSTEM_PERIP_RST_EN1_DMA_RST = 0x40 + // Position of TSENS_RST field. + SYSTEM_PERIP_RST_EN1_TSENS_RST_Pos = 0xa + // Bit mask of TSENS_RST field. + SYSTEM_PERIP_RST_EN1_TSENS_RST_Msk = 0x400 + // Bit TSENS_RST. + SYSTEM_PERIP_RST_EN1_TSENS_RST = 0x400 + + // BT_LPCK_DIV_INT: clock config register + // Position of BT_LPCK_DIV_NUM field. + SYSTEM_BT_LPCK_DIV_INT_BT_LPCK_DIV_NUM_Pos = 0x0 + // Bit mask of BT_LPCK_DIV_NUM field. + SYSTEM_BT_LPCK_DIV_INT_BT_LPCK_DIV_NUM_Msk = 0xfff + + // BT_LPCK_DIV_FRAC: low power clock configuration register + // Position of BT_LPCK_DIV_B field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_B_Pos = 0x0 + // Bit mask of BT_LPCK_DIV_B field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_B_Msk = 0xfff + // Position of BT_LPCK_DIV_A field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_A_Pos = 0xc + // Bit mask of BT_LPCK_DIV_A field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_A_Msk = 0xfff000 + // Position of LPCLK_SEL_RTC_SLOW field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Pos = 0x18 + // Bit mask of LPCLK_SEL_RTC_SLOW field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Msk = 0x1000000 + // Bit LPCLK_SEL_RTC_SLOW. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW = 0x1000000 + // Position of LPCLK_SEL_8M field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Pos = 0x19 + // Bit mask of LPCLK_SEL_8M field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Msk = 0x2000000 + // Bit LPCLK_SEL_8M. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M = 0x2000000 + // Position of LPCLK_SEL_XTAL field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Pos = 0x1a + // Bit mask of LPCLK_SEL_XTAL field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Msk = 0x4000000 + // Bit LPCLK_SEL_XTAL. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL = 0x4000000 + // Position of LPCLK_SEL_XTAL32K field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Pos = 0x1b + // Bit mask of LPCLK_SEL_XTAL32K field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Msk = 0x8000000 + // Bit LPCLK_SEL_XTAL32K. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K = 0x8000000 + // Position of LPCLK_RTC_EN field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN_Pos = 0x1c + // Bit mask of LPCLK_RTC_EN field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN_Msk = 0x10000000 + // Bit LPCLK_RTC_EN. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN = 0x10000000 + + // CPU_INTR_FROM_CPU_0: interrupt generate register + // Position of CPU_INTR_FROM_CPU_0 field. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0 field. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_0. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0 = 0x1 + + // CPU_INTR_FROM_CPU_1: interrupt generate register + // Position of CPU_INTR_FROM_CPU_1 field. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1 field. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_1. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1 = 0x1 + + // CPU_INTR_FROM_CPU_2: interrupt generate register + // Position of CPU_INTR_FROM_CPU_2 field. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2 field. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_2. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2 = 0x1 + + // CPU_INTR_FROM_CPU_3: interrupt generate register + // Position of CPU_INTR_FROM_CPU_3 field. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3 field. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_3. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3 = 0x1 + + // RSA_PD_CTRL: rsa memory power control register + // Position of RSA_MEM_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD_Pos = 0x0 + // Bit mask of RSA_MEM_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD_Msk = 0x1 + // Bit RSA_MEM_PD. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD = 0x1 + // Position of RSA_MEM_FORCE_PU field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of RSA_MEM_FORCE_PU field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Msk = 0x2 + // Bit RSA_MEM_FORCE_PU. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU = 0x2 + // Position of RSA_MEM_FORCE_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of RSA_MEM_FORCE_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Msk = 0x4 + // Bit RSA_MEM_FORCE_PD. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD = 0x4 + + // EDMA_CTRL: edma clcok and reset register + // Position of EDMA_CLK_ON field. + SYSTEM_EDMA_CTRL_EDMA_CLK_ON_Pos = 0x0 + // Bit mask of EDMA_CLK_ON field. + SYSTEM_EDMA_CTRL_EDMA_CLK_ON_Msk = 0x1 + // Bit EDMA_CLK_ON. + SYSTEM_EDMA_CTRL_EDMA_CLK_ON = 0x1 + // Position of EDMA_RESET field. + SYSTEM_EDMA_CTRL_EDMA_RESET_Pos = 0x1 + // Bit mask of EDMA_RESET field. + SYSTEM_EDMA_CTRL_EDMA_RESET_Msk = 0x2 + // Bit EDMA_RESET. + SYSTEM_EDMA_CTRL_EDMA_RESET = 0x2 + + // CACHE_CONTROL: cache control register + // Position of ICACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_ICACHE_CLK_ON_Pos = 0x0 + // Bit mask of ICACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_ICACHE_CLK_ON_Msk = 0x1 + // Bit ICACHE_CLK_ON. + SYSTEM_CACHE_CONTROL_ICACHE_CLK_ON = 0x1 + // Position of ICACHE_RESET field. + SYSTEM_CACHE_CONTROL_ICACHE_RESET_Pos = 0x1 + // Bit mask of ICACHE_RESET field. + SYSTEM_CACHE_CONTROL_ICACHE_RESET_Msk = 0x2 + // Bit ICACHE_RESET. + SYSTEM_CACHE_CONTROL_ICACHE_RESET = 0x2 + // Position of DCACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_DCACHE_CLK_ON_Pos = 0x2 + // Bit mask of DCACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_DCACHE_CLK_ON_Msk = 0x4 + // Bit DCACHE_CLK_ON. + SYSTEM_CACHE_CONTROL_DCACHE_CLK_ON = 0x4 + // Position of DCACHE_RESET field. + SYSTEM_CACHE_CONTROL_DCACHE_RESET_Pos = 0x3 + // Bit mask of DCACHE_RESET field. + SYSTEM_CACHE_CONTROL_DCACHE_RESET_Msk = 0x8 + // Bit DCACHE_RESET. + SYSTEM_CACHE_CONTROL_DCACHE_RESET = 0x8 + + // EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG + // Position of ENABLE_SPI_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Pos = 0x0 + // Bit mask of ENABLE_SPI_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Msk = 0x1 + // Bit ENABLE_SPI_MANUAL_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT = 0x1 + // Position of ENABLE_DOWNLOAD_DB_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Pos = 0x1 + // Bit mask of ENABLE_DOWNLOAD_DB_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Msk = 0x2 + // Bit ENABLE_DOWNLOAD_DB_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT = 0x2 + // Position of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Pos = 0x2 + // Bit mask of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Msk = 0x4 + // Bit ENABLE_DOWNLOAD_G0CB_DECRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT = 0x4 + // Position of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x3 + // Bit mask of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x8 + // Bit ENABLE_DOWNLOAD_MANUAL_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT = 0x8 + + // RTC_FASTMEM_CONFIG: fast memory config register + // Position of RTC_MEM_CRC_START field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START_Pos = 0x8 + // Bit mask of RTC_MEM_CRC_START field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START_Msk = 0x100 + // Bit RTC_MEM_CRC_START. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START = 0x100 + // Position of RTC_MEM_CRC_ADDR field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR_Pos = 0x9 + // Bit mask of RTC_MEM_CRC_ADDR field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR_Msk = 0xffe00 + // Position of RTC_MEM_CRC_LEN field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN_Pos = 0x14 + // Bit mask of RTC_MEM_CRC_LEN field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN_Msk = 0x7ff00000 + // Position of RTC_MEM_CRC_FINISH field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH_Pos = 0x1f + // Bit mask of RTC_MEM_CRC_FINISH field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH_Msk = 0x80000000 + // Bit RTC_MEM_CRC_FINISH. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH = 0x80000000 + + // RTC_FASTMEM_CRC: reserved + // Position of RTC_MEM_CRC_RES field. + SYSTEM_RTC_FASTMEM_CRC_RTC_MEM_CRC_RES_Pos = 0x0 + // Bit mask of RTC_MEM_CRC_RES field. + SYSTEM_RTC_FASTMEM_CRC_RTC_MEM_CRC_RES_Msk = 0xffffffff + + // REDUNDANT_ECO_CTRL: eco register + // Position of REDUNDANT_ECO_DRIVE field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE_Pos = 0x0 + // Bit mask of REDUNDANT_ECO_DRIVE field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE_Msk = 0x1 + // Bit REDUNDANT_ECO_DRIVE. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE = 0x1 + // Position of REDUNDANT_ECO_RESULT field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT_Pos = 0x1 + // Bit mask of REDUNDANT_ECO_RESULT field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT_Msk = 0x2 + // Bit REDUNDANT_ECO_RESULT. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT = 0x2 + + // CLOCK_GATE: clock gating register + // Position of CLK_EN field. + SYSTEM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SYSTEM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SYSTEM_CLOCK_GATE_CLK_EN = 0x1 + + // SYSCLK_CONF: system clock config register + // Position of PRE_DIV_CNT field. + SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_Pos = 0x0 + // Bit mask of PRE_DIV_CNT field. + SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_Msk = 0x3ff + // Position of SOC_CLK_SEL field. + SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_Pos = 0xa + // Bit mask of SOC_CLK_SEL field. + SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_Msk = 0xc00 + // Position of CLK_XTAL_FREQ field. + SYSTEM_SYSCLK_CONF_CLK_XTAL_FREQ_Pos = 0xc + // Bit mask of CLK_XTAL_FREQ field. + SYSTEM_SYSCLK_CONF_CLK_XTAL_FREQ_Msk = 0x7f000 + // Position of CLK_DIV_EN field. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN_Pos = 0x13 + // Bit mask of CLK_DIV_EN field. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN_Msk = 0x80000 + // Bit CLK_DIV_EN. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN = 0x80000 + + // MEM_PVT: mem pvt register + // Position of MEM_PATH_LEN field. + SYSTEM_MEM_PVT_MEM_PATH_LEN_Pos = 0x0 + // Bit mask of MEM_PATH_LEN field. + SYSTEM_MEM_PVT_MEM_PATH_LEN_Msk = 0xf + // Position of MEM_ERR_CNT_CLR field. + SYSTEM_MEM_PVT_MEM_ERR_CNT_CLR_Pos = 0x4 + // Bit mask of MEM_ERR_CNT_CLR field. + SYSTEM_MEM_PVT_MEM_ERR_CNT_CLR_Msk = 0x10 + // Bit MEM_ERR_CNT_CLR. + SYSTEM_MEM_PVT_MEM_ERR_CNT_CLR = 0x10 + // Position of MONITOR_EN field. + SYSTEM_MEM_PVT_MONITOR_EN_Pos = 0x5 + // Bit mask of MONITOR_EN field. + SYSTEM_MEM_PVT_MONITOR_EN_Msk = 0x20 + // Bit MONITOR_EN. + SYSTEM_MEM_PVT_MONITOR_EN = 0x20 + // Position of MEM_TIMING_ERR_CNT field. + SYSTEM_MEM_PVT_MEM_TIMING_ERR_CNT_Pos = 0x6 + // Bit mask of MEM_TIMING_ERR_CNT field. + SYSTEM_MEM_PVT_MEM_TIMING_ERR_CNT_Msk = 0x3fffc0 + // Position of MEM_VT_SEL field. + SYSTEM_MEM_PVT_MEM_VT_SEL_Pos = 0x16 + // Bit mask of MEM_VT_SEL field. + SYSTEM_MEM_PVT_MEM_VT_SEL_Msk = 0xc00000 + + // COMB_PVT_LVT_CONF: mem pvt register + // Position of COMB_PATH_LEN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT_Pos = 0x0 + // Bit mask of COMB_PATH_LEN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT_Msk = 0x3f + // Position of COMB_ERR_CNT_CLR_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT_Pos = 0x6 + // Bit mask of COMB_ERR_CNT_CLR_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT_Msk = 0x40 + // Bit COMB_ERR_CNT_CLR_LVT. + SYSTEM_COMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT = 0x40 + // Position of COMB_PVT_MONITOR_EN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT_Pos = 0x7 + // Bit mask of COMB_PVT_MONITOR_EN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT_Msk = 0x80 + // Bit COMB_PVT_MONITOR_EN_LVT. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT = 0x80 + + // COMB_PVT_NVT_CONF: mem pvt register + // Position of COMB_PATH_LEN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT_Pos = 0x0 + // Bit mask of COMB_PATH_LEN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT_Msk = 0x3f + // Position of COMB_ERR_CNT_CLR_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT_Pos = 0x6 + // Bit mask of COMB_ERR_CNT_CLR_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT_Msk = 0x40 + // Bit COMB_ERR_CNT_CLR_NVT. + SYSTEM_COMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT = 0x40 + // Position of COMB_PVT_MONITOR_EN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT_Pos = 0x7 + // Bit mask of COMB_PVT_MONITOR_EN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT_Msk = 0x80 + // Bit COMB_PVT_MONITOR_EN_NVT. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT = 0x80 + + // COMB_PVT_HVT_CONF: mem pvt register + // Position of COMB_PATH_LEN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT_Pos = 0x0 + // Bit mask of COMB_PATH_LEN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT_Msk = 0x3f + // Position of COMB_ERR_CNT_CLR_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT_Pos = 0x6 + // Bit mask of COMB_ERR_CNT_CLR_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT_Msk = 0x40 + // Bit COMB_ERR_CNT_CLR_HVT. + SYSTEM_COMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT = 0x40 + // Position of COMB_PVT_MONITOR_EN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT_Pos = 0x7 + // Bit mask of COMB_PVT_MONITOR_EN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT_Msk = 0x80 + // Bit COMB_PVT_MONITOR_EN_HVT. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT = 0x80 + + // COMB_PVT_ERR_LVT_SITE0: mem pvt register + // Position of COMB_TIMING_ERR_CNT_LVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE0: mem pvt register + // Position of COMB_TIMING_ERR_CNT_NVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE0: mem pvt register + // Position of COMB_TIMING_ERR_CNT_HVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0_Msk = 0xffff + + // COMB_PVT_ERR_LVT_SITE1: mem pvt register + // Position of COMB_TIMING_ERR_CNT_LVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE1: mem pvt register + // Position of COMB_TIMING_ERR_CNT_NVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE1: mem pvt register + // Position of COMB_TIMING_ERR_CNT_HVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1_Msk = 0xffff + + // COMB_PVT_ERR_LVT_SITE2: mem pvt register + // Position of COMB_TIMING_ERR_CNT_LVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE2: mem pvt register + // Position of COMB_TIMING_ERR_CNT_NVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE2: mem pvt register + // Position of COMB_TIMING_ERR_CNT_HVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2_Msk = 0xffff + + // COMB_PVT_ERR_LVT_SITE3: mem pvt register + // Position of COMB_TIMING_ERR_CNT_LVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE3: mem pvt register + // Position of COMB_TIMING_ERR_CNT_NVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE3: mem pvt register + // Position of COMB_TIMING_ERR_CNT_HVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3_Msk = 0xffff + + // REG_DATE: Version register + // Position of SYSTEM_REG_DATE field. + SYSTEM_REG_DATE_SYSTEM_REG_DATE_Pos = 0x0 + // Bit mask of SYSTEM_REG_DATE field. + SYSTEM_REG_DATE_SYSTEM_REG_DATE_Msk = 0xfffffff +) + +// Constants for SYSTIMER: System Timer +const ( + // CONF: Configure system timer clock + // Position of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Pos = 0x0 + // Bit mask of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Msk = 0x1 + // Bit SYSTIMER_CLK_FO. + SYSTIMER_CONF_SYSTIMER_CLK_FO = 0x1 + // Position of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Pos = 0x16 + // Bit mask of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Msk = 0x400000 + // Bit TARGET2_WORK_EN. + SYSTIMER_CONF_TARGET2_WORK_EN = 0x400000 + // Position of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Pos = 0x17 + // Bit mask of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Msk = 0x800000 + // Bit TARGET1_WORK_EN. + SYSTIMER_CONF_TARGET1_WORK_EN = 0x800000 + // Position of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Pos = 0x18 + // Bit mask of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Msk = 0x1000000 + // Bit TARGET0_WORK_EN. + SYSTIMER_CONF_TARGET0_WORK_EN = 0x1000000 + // Position of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Pos = 0x19 + // Bit mask of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Msk = 0x2000000 + // Bit TIMER_UNIT1_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN = 0x2000000 + // Position of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Pos = 0x1a + // Bit mask of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Msk = 0x4000000 + // Bit TIMER_UNIT1_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN = 0x4000000 + // Position of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Pos = 0x1b + // Bit mask of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Msk = 0x8000000 + // Bit TIMER_UNIT0_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN = 0x8000000 + // Position of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Pos = 0x1c + // Bit mask of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Msk = 0x10000000 + // Bit TIMER_UNIT0_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN = 0x10000000 + // Position of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Pos = 0x1d + // Bit mask of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Msk = 0x20000000 + // Bit TIMER_UNIT1_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN = 0x20000000 + // Position of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Pos = 0x1e + // Bit mask of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Msk = 0x40000000 + // Bit TIMER_UNIT0_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN = 0x40000000 + // Position of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + SYSTIMER_CONF_CLK_EN = 0x80000000 + + // UNIT0_OP: system timer unit0 value update register + // Position of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT0_VALUE_VALID. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT0_UPDATE. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE = 0x40000000 + + // UNIT1_OP: system timer unit1 value update register + // Position of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT1_VALUE_VALID. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT1_UPDATE. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE = 0x40000000 + + // UNIT0_LOAD_HI: system timer unit0 value high load register + // Position of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Msk = 0xfffff + + // UNIT0_LOAD_LO: system timer unit0 value low load register + // Position of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Msk = 0xffffffff + + // UNIT1_LOAD_HI: system timer unit1 value high load register + // Position of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Msk = 0xfffff + + // UNIT1_LOAD_LO: system timer unit1 value low load register + // Position of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Msk = 0xffffffff + + // TARGET0_HI: system timer comp0 value high register + // Position of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Msk = 0xfffff + + // TARGET0_LO: system timer comp0 value low register + // Position of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Msk = 0xffffffff + + // TARGET1_HI: system timer comp1 value high register + // Position of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Msk = 0xfffff + + // TARGET1_LO: system timer comp1 value low register + // Position of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Msk = 0xffffffff + + // TARGET2_HI: system timer comp2 value high register + // Position of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Msk = 0xfffff + + // TARGET2_LO: system timer comp2 value low register + // Position of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Msk = 0xffffffff + + // TARGET0_CONF: system timer comp0 target mode register + // Position of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Pos = 0x0 + // Bit mask of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Msk = 0x3ffffff + // Position of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET0_PERIOD_MODE. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE = 0x40000000 + // Position of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET0_TIMER_UNIT_SEL. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL = 0x80000000 + + // TARGET1_CONF: system timer comp1 target mode register + // Position of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Pos = 0x0 + // Bit mask of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Msk = 0x3ffffff + // Position of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET1_PERIOD_MODE. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE = 0x40000000 + // Position of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET1_TIMER_UNIT_SEL. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL = 0x80000000 + + // TARGET2_CONF: system timer comp2 target mode register + // Position of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Pos = 0x0 + // Bit mask of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Msk = 0x3ffffff + // Position of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET2_PERIOD_MODE. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE = 0x40000000 + // Position of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET2_TIMER_UNIT_SEL. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL = 0x80000000 + + // UNIT0_VALUE_HI: system timer unit0 value high register + // Position of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Msk = 0xfffff + + // UNIT0_VALUE_LO: system timer unit0 value low register + // Position of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Msk = 0xffffffff + + // UNIT1_VALUE_HI: system timer unit1 value high register + // Position of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Msk = 0xfffff + + // UNIT1_VALUE_LO: system timer unit1 value low register + // Position of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Msk = 0xffffffff + + // COMP0_LOAD: system timer comp0 conf sync register + // Position of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Msk = 0x1 + // Bit TIMER_COMP0_LOAD. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD = 0x1 + + // COMP1_LOAD: system timer comp1 conf sync register + // Position of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Msk = 0x1 + // Bit TIMER_COMP1_LOAD. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD = 0x1 + + // COMP2_LOAD: system timer comp2 conf sync register + // Position of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Msk = 0x1 + // Bit TIMER_COMP2_LOAD. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD = 0x1 + + // UNIT0_LOAD: system timer unit0 conf sync register + // Position of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Msk = 0x1 + // Bit TIMER_UNIT0_LOAD. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD = 0x1 + + // UNIT1_LOAD: system timer unit1 conf sync register + // Position of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Msk = 0x1 + // Bit TIMER_UNIT1_LOAD. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD = 0x1 + + // INT_ENA: systimer interrupt enable register + // Position of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Pos = 0x0 + // Bit mask of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Msk = 0x1 + // Bit TARGET0_INT_ENA. + SYSTIMER_INT_ENA_TARGET0_INT_ENA = 0x1 + // Position of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Pos = 0x1 + // Bit mask of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Msk = 0x2 + // Bit TARGET1_INT_ENA. + SYSTIMER_INT_ENA_TARGET1_INT_ENA = 0x2 + // Position of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Pos = 0x2 + // Bit mask of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Msk = 0x4 + // Bit TARGET2_INT_ENA. + SYSTIMER_INT_ENA_TARGET2_INT_ENA = 0x4 + + // INT_RAW: systimer interrupt raw register + // Position of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Pos = 0x0 + // Bit mask of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Msk = 0x1 + // Bit TARGET0_INT_RAW. + SYSTIMER_INT_RAW_TARGET0_INT_RAW = 0x1 + // Position of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Pos = 0x1 + // Bit mask of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Msk = 0x2 + // Bit TARGET1_INT_RAW. + SYSTIMER_INT_RAW_TARGET1_INT_RAW = 0x2 + // Position of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Pos = 0x2 + // Bit mask of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Msk = 0x4 + // Bit TARGET2_INT_RAW. + SYSTIMER_INT_RAW_TARGET2_INT_RAW = 0x4 + + // INT_CLR: systimer interrupt clear register + // Position of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Pos = 0x0 + // Bit mask of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Msk = 0x1 + // Bit TARGET0_INT_CLR. + SYSTIMER_INT_CLR_TARGET0_INT_CLR = 0x1 + // Position of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Pos = 0x1 + // Bit mask of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Msk = 0x2 + // Bit TARGET1_INT_CLR. + SYSTIMER_INT_CLR_TARGET1_INT_CLR = 0x2 + // Position of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Pos = 0x2 + // Bit mask of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Msk = 0x4 + // Bit TARGET2_INT_CLR. + SYSTIMER_INT_CLR_TARGET2_INT_CLR = 0x4 + + // INT_ST: systimer interrupt status register + // Position of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Pos = 0x0 + // Bit mask of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Msk = 0x1 + // Bit TARGET0_INT_ST. + SYSTIMER_INT_ST_TARGET0_INT_ST = 0x1 + // Position of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Pos = 0x1 + // Bit mask of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Msk = 0x2 + // Bit TARGET1_INT_ST. + SYSTIMER_INT_ST_TARGET1_INT_ST = 0x2 + // Position of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Pos = 0x2 + // Bit mask of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Msk = 0x4 + // Bit TARGET2_INT_ST. + SYSTIMER_INT_ST_TARGET2_INT_ST = 0x4 + + // DATE: system timer version control register + // Position of DATE field. + SYSTIMER_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SYSTIMER_DATE_DATE_Msk = 0xffffffff +) + +// Constants for TIMG0: Timer Group 0 +const ( + // T0CONFIG: Timer %s configuration register + // Position of USE_XTAL field. + TIMG_T0CONFIG_USE_XTAL_Pos = 0x9 + // Bit mask of USE_XTAL field. + TIMG_T0CONFIG_USE_XTAL_Msk = 0x200 + // Bit USE_XTAL. + TIMG_T0CONFIG_USE_XTAL = 0x200 + // Position of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Pos = 0xa + // Bit mask of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Msk = 0x400 + // Bit ALARM_EN. + TIMG_T0CONFIG_ALARM_EN = 0x400 + // Position of DIVCNT_RST field. + TIMG_T0CONFIG_DIVCNT_RST_Pos = 0xc + // Bit mask of DIVCNT_RST field. + TIMG_T0CONFIG_DIVCNT_RST_Msk = 0x1000 + // Bit DIVCNT_RST. + TIMG_T0CONFIG_DIVCNT_RST = 0x1000 + // Position of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Pos = 0xd + // Bit mask of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Msk = 0x1fffe000 + // Position of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Pos = 0x1d + // Bit mask of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Msk = 0x20000000 + // Bit AUTORELOAD. + TIMG_T0CONFIG_AUTORELOAD = 0x20000000 + // Position of INCREASE field. + TIMG_T0CONFIG_INCREASE_Pos = 0x1e + // Bit mask of INCREASE field. + TIMG_T0CONFIG_INCREASE_Msk = 0x40000000 + // Bit INCREASE. + TIMG_T0CONFIG_INCREASE = 0x40000000 + // Position of EN field. + TIMG_T0CONFIG_EN_Pos = 0x1f + // Bit mask of EN field. + TIMG_T0CONFIG_EN_Msk = 0x80000000 + // Bit EN. + TIMG_T0CONFIG_EN = 0x80000000 + + // T0LO: Timer %s current value, low 32 bits + // Position of LO field. + TIMG_T0LO_LO_Pos = 0x0 + // Bit mask of LO field. + TIMG_T0LO_LO_Msk = 0xffffffff + + // T0HI: Timer %s current value, high 22 bits + // Position of T0_HI field. + TIMG_T0HI_T0_HI_Pos = 0x0 + // Bit mask of T0_HI field. + TIMG_T0HI_T0_HI_Msk = 0x3fffff + + // T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + // Position of T0_UPDATE field. + TIMG_T0UPDATE_T0_UPDATE_Pos = 0x1f + // Bit mask of T0_UPDATE field. + TIMG_T0UPDATE_T0_UPDATE_Msk = 0x80000000 + // Bit T0_UPDATE. + TIMG_T0UPDATE_T0_UPDATE = 0x80000000 + + // T0ALARMLO: Timer %s alarm value, low 32 bits + // Position of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Pos = 0x0 + // Bit mask of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Msk = 0xffffffff + + // T0ALARMHI: Timer %s alarm value, high bits + // Position of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Pos = 0x0 + // Bit mask of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Msk = 0x3fffff + + // T0LOADLO: Timer %s reload value, low 32 bits + // Position of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Pos = 0x0 + // Bit mask of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Msk = 0xffffffff + + // T0LOADHI: Timer %s reload value, high 22 bits + // Position of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Pos = 0x0 + // Bit mask of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Msk = 0x3fffff + + // T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + // Position of LOAD field. + TIMG_T0LOAD_LOAD_Pos = 0x0 + // Bit mask of LOAD field. + TIMG_T0LOAD_LOAD_Msk = 0xffffffff + + // WDTCONFIG0: Watchdog timer configuration register + // Position of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xc + // Bit mask of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x1000 + // Bit WDT_APPCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x1000 + // Position of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xd + // Bit mask of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x2000 + // Bit WDT_PROCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x2000 + // Position of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xe + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x4000 + // Bit WDT_FLASHBOOT_MOD_EN. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x4000 + // Position of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xf + // Bit mask of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0x38000 + // Position of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x12 + // Bit mask of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x1c0000 + // Position of WDT_USE_XTAL field. + TIMG_WDTCONFIG0_WDT_USE_XTAL_Pos = 0x15 + // Bit mask of WDT_USE_XTAL field. + TIMG_WDTCONFIG0_WDT_USE_XTAL_Msk = 0x200000 + // Bit WDT_USE_XTAL. + TIMG_WDTCONFIG0_WDT_USE_XTAL = 0x200000 + // Position of WDT_CONF_UPDATE_EN field. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Pos = 0x16 + // Bit mask of WDT_CONF_UPDATE_EN field. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Msk = 0x400000 + // Bit WDT_CONF_UPDATE_EN. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN = 0x400000 + // Position of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Pos = 0x17 + // Bit mask of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Msk = 0x1800000 + // Position of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Pos = 0x19 + // Bit mask of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Msk = 0x6000000 + // Position of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Pos = 0x1b + // Bit mask of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Msk = 0x18000000 + // Position of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Pos = 0x1d + // Bit mask of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Msk = 0x60000000 + // Position of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + TIMG_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: Watchdog timer prescaler register + // Position of WDT_DIVCNT_RST field. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Pos = 0x0 + // Bit mask of WDT_DIVCNT_RST field. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Msk = 0x1 + // Bit WDT_DIVCNT_RST. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST = 0x1 + // Position of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Pos = 0x10 + // Bit mask of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Msk = 0xffff0000 + + // WDTCONFIG2: Watchdog timer stage 0 timeout value + // Position of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: Watchdog timer stage 1 timeout value + // Position of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: Watchdog timer stage 2 timeout value + // Position of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG5: Watchdog timer stage 3 timeout value + // Position of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: Write to feed the watchdog timer + // Position of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Pos = 0x0 + // Bit mask of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Msk = 0xffffffff + + // WDTWPROTECT: Watchdog write protect register + // Position of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // RTCCALICFG: RTC calibration configure register + // Position of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Pos = 0xc + // Bit mask of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Msk = 0x1000 + // Bit RTC_CALI_START_CYCLING. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING = 0x1000 + // Position of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Pos = 0xd + // Bit mask of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Msk = 0x6000 + // Position of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Pos = 0xf + // Bit mask of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Msk = 0x8000 + // Bit RTC_CALI_RDY. + TIMG_RTCCALICFG_RTC_CALI_RDY = 0x8000 + // Position of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Pos = 0x10 + // Bit mask of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Msk = 0x7fff0000 + // Position of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Pos = 0x1f + // Bit mask of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Msk = 0x80000000 + // Bit RTC_CALI_START. + TIMG_RTCCALICFG_RTC_CALI_START = 0x80000000 + + // RTCCALICFG1: RTC calibration configure1 register + // Position of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Pos = 0x0 + // Bit mask of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Msk = 0x1 + // Bit RTC_CALI_CYCLING_DATA_VLD. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD = 0x1 + // Position of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Pos = 0x7 + // Bit mask of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Msk = 0xffffff80 + + // INT_ENA_TIMERS: Interrupt enable bits + // Position of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Pos = 0x0 + // Bit mask of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Msk = 0x1 + // Bit T0_INT_ENA. + TIMG_INT_ENA_TIMERS_T0_INT_ENA = 0x1 + // Position of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Pos = 0x1 + // Bit mask of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Msk = 0x2 + // Bit WDT_INT_ENA. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA = 0x2 + + // INT_RAW_TIMERS: Raw interrupt status + // Position of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Pos = 0x0 + // Bit mask of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Msk = 0x1 + // Bit T0_INT_RAW. + TIMG_INT_RAW_TIMERS_T0_INT_RAW = 0x1 + // Position of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Pos = 0x1 + // Bit mask of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Msk = 0x2 + // Bit WDT_INT_RAW. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW = 0x2 + + // INT_ST_TIMERS: Masked interrupt status + // Position of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Pos = 0x0 + // Bit mask of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Msk = 0x1 + // Bit T0_INT_ST. + TIMG_INT_ST_TIMERS_T0_INT_ST = 0x1 + // Position of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Pos = 0x1 + // Bit mask of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Msk = 0x2 + // Bit WDT_INT_ST. + TIMG_INT_ST_TIMERS_WDT_INT_ST = 0x2 + + // INT_CLR_TIMERS: Interrupt clear bits + // Position of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Pos = 0x0 + // Bit mask of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Msk = 0x1 + // Bit T0_INT_CLR. + TIMG_INT_CLR_TIMERS_T0_INT_CLR = 0x1 + // Position of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Pos = 0x1 + // Bit mask of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Msk = 0x2 + // Bit WDT_INT_CLR. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR = 0x2 + + // RTCCALICFG2: Timer group calibration register + // Position of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Pos = 0x0 + // Bit mask of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Msk = 0x1 + // Bit RTC_CALI_TIMEOUT. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT = 0x1 + // Position of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Pos = 0x3 + // Bit mask of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Msk = 0x78 + // Position of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Pos = 0x7 + // Bit mask of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Msk = 0xffffff80 + + // NTIMERS_DATE: Timer version control register + // Position of NTIMGS_DATE field. + TIMG_NTIMERS_DATE_NTIMGS_DATE_Pos = 0x0 + // Bit mask of NTIMGS_DATE field. + TIMG_NTIMERS_DATE_NTIMGS_DATE_Msk = 0xfffffff + + // REGCLK: Timer group clock gate register + // Position of WDT_CLK_IS_ACTIVE field. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Pos = 0x1d + // Bit mask of WDT_CLK_IS_ACTIVE field. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Msk = 0x20000000 + // Bit WDT_CLK_IS_ACTIVE. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE = 0x20000000 + // Position of TIMER_CLK_IS_ACTIVE field. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Pos = 0x1e + // Bit mask of TIMER_CLK_IS_ACTIVE field. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Msk = 0x40000000 + // Bit TIMER_CLK_IS_ACTIVE. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE = 0x40000000 + // Position of CLK_EN field. + TIMG_REGCLK_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + TIMG_REGCLK_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + TIMG_REGCLK_CLK_EN = 0x80000000 +) + +// Constants for UART0: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +const ( + // FIFO: FIFO data register + // Position of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9 + // Bit mask of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200 + // Bit SW_XON_INT_RAW. + UART_INT_RAW_SW_XON_INT_RAW = 0x200 + // Position of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa + // Bit mask of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400 + // Bit SW_XOFF_INT_RAW. + UART_INT_RAW_SW_XOFF_INT_RAW = 0x400 + // Position of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb + // Bit mask of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800 + // Bit GLITCH_DET_INT_RAW. + UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800 + // Position of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000 + // Position of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit TX_DONE_INT_RAW. + UART_INT_RAW_TX_DONE_INT_RAW = 0x4000 + // Position of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_RAW. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW = 0x8000 + // Position of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_RAW. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW = 0x10000 + // Position of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Msk = 0x20000 + // Bit RS485_CLASH_INT_RAW. + UART_INT_RAW_RS485_CLASH_INT_RAW = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_RAW. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000 + // Position of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13 + // Bit mask of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000 + // Bit WAKEUP_INT_RAW. + UART_INT_RAW_WAKEUP_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Pos = 0x9 + // Bit mask of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Msk = 0x200 + // Bit SW_XON_INT_ST. + UART_INT_ST_SW_XON_INT_ST = 0x200 + // Position of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa + // Bit mask of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400 + // Bit SW_XOFF_INT_ST. + UART_INT_ST_SW_XOFF_INT_ST = 0x400 + // Position of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800 + // Bit GLITCH_DET_INT_ST. + UART_INT_ST_GLITCH_DET_INT_ST = 0x800 + // Position of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ST. + UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ST. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000 + // Position of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000 + // Bit TX_DONE_INT_ST. + UART_INT_ST_TX_DONE_INT_ST = 0x4000 + // Position of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ST. + UART_INT_ST_RS485_PARITY_ERR_INT_ST = 0x8000 + // Position of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ST. + UART_INT_ST_RS485_FRM_ERR_INT_ST = 0x10000 + // Position of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Msk = 0x20000 + // Bit RS485_CLASH_INT_ST. + UART_INT_ST_RS485_CLASH_INT_ST = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ST. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000 + // Position of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13 + // Bit mask of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000 + // Bit WAKEUP_INT_ST. + UART_INT_ST_WAKEUP_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9 + // Bit mask of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200 + // Bit SW_XON_INT_ENA. + UART_INT_ENA_SW_XON_INT_ENA = 0x200 + // Position of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa + // Bit mask of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400 + // Bit SW_XOFF_INT_ENA. + UART_INT_ENA_SW_XOFF_INT_ENA = 0x400 + // Position of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800 + // Bit GLITCH_DET_INT_ENA. + UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800 + // Position of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000 + // Position of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit TX_DONE_INT_ENA. + UART_INT_ENA_TX_DONE_INT_ENA = 0x4000 + // Position of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ENA. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA = 0x8000 + // Position of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ENA. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA = 0x10000 + // Position of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Msk = 0x20000 + // Bit RS485_CLASH_INT_ENA. + UART_INT_ENA_RS485_CLASH_INT_ENA = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ENA. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000 + // Position of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13 + // Bit mask of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000 + // Bit WAKEUP_INT_ENA. + UART_INT_ENA_WAKEUP_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9 + // Bit mask of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200 + // Bit SW_XON_INT_CLR. + UART_INT_CLR_SW_XON_INT_CLR = 0x200 + // Position of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa + // Bit mask of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400 + // Bit SW_XOFF_INT_CLR. + UART_INT_CLR_SW_XOFF_INT_CLR = 0x400 + // Position of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb + // Bit mask of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800 + // Bit GLITCH_DET_INT_CLR. + UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800 + // Position of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000 + // Position of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit TX_DONE_INT_CLR. + UART_INT_CLR_TX_DONE_INT_CLR = 0x4000 + // Position of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_CLR. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR = 0x8000 + // Position of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_CLR. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR = 0x10000 + // Position of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Msk = 0x20000 + // Bit RS485_CLASH_INT_CLR. + UART_INT_CLR_RS485_CLASH_INT_CLR = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_CLR. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000 + // Position of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13 + // Bit mask of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000 + // Bit WAKEUP_INT_CLR. + UART_INT_CLR_WAKEUP_INT_CLR = 0x80000 + + // CLKDIV: Clock divider configuration + // Position of CLKDIV field. + UART_CLKDIV_CLKDIV_Pos = 0x0 + // Bit mask of CLKDIV field. + UART_CLKDIV_CLKDIV_Msk = 0xfff + // Position of FRAG field. + UART_CLKDIV_FRAG_Pos = 0x14 + // Bit mask of FRAG field. + UART_CLKDIV_FRAG_Msk = 0xf00000 + + // RX_FILT: Rx Filter configuration + // Position of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Pos = 0x0 + // Bit mask of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Msk = 0xff + // Position of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Pos = 0x8 + // Bit mask of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Msk = 0x100 + // Bit GLITCH_FILT_EN. + UART_RX_FILT_GLITCH_FILT_EN = 0x100 + + // STATUS: UART status register + // Position of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Pos = 0x0 + // Bit mask of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Msk = 0x3ff + // Position of DSRN field. + UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + UART_STATUS_DSRN = 0x2000 + // Position of CTSN field. + UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + UART_STATUS_CTSN = 0x4000 + // Position of RXD field. + UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + UART_STATUS_RXD = 0x8000 + // Position of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Pos = 0x10 + // Bit mask of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Msk = 0x3ff0000 + // Position of DTRN field. + UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + UART_STATUS_DTRN = 0x20000000 + // Position of RTSN field. + UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + UART_STATUS_RTSN = 0x40000000 + // Position of TXD field. + UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + UART_STATUS_TXD = 0x80000000 + + // CONF0: a + // Position of PARITY field. + UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + UART_CONF0_PARITY = 0x1 + // Position of PARITY_EN field. + UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + UART_CONF0_PARITY_EN = 0x2 + // Position of BIT_NUM field. + UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + UART_CONF0_BIT_NUM_Msk = 0xc + // Position of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of SW_RTS field. + UART_CONF0_SW_RTS_Pos = 0x6 + // Bit mask of SW_RTS field. + UART_CONF0_SW_RTS_Msk = 0x40 + // Bit SW_RTS. + UART_CONF0_SW_RTS = 0x40 + // Position of SW_DTR field. + UART_CONF0_SW_DTR_Pos = 0x7 + // Bit mask of SW_DTR field. + UART_CONF0_SW_DTR_Msk = 0x80 + // Bit SW_DTR. + UART_CONF0_SW_DTR = 0x80 + // Position of TXD_BRK field. + UART_CONF0_TXD_BRK_Pos = 0x8 + // Bit mask of TXD_BRK field. + UART_CONF0_TXD_BRK_Msk = 0x100 + // Bit TXD_BRK. + UART_CONF0_TXD_BRK = 0x100 + // Position of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Pos = 0x9 + // Bit mask of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Msk = 0x200 + // Bit IRDA_DPLX. + UART_CONF0_IRDA_DPLX = 0x200 + // Position of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Pos = 0xa + // Bit mask of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Msk = 0x400 + // Bit IRDA_TX_EN. + UART_CONF0_IRDA_TX_EN = 0x400 + // Position of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Pos = 0xb + // Bit mask of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Msk = 0x800 + // Bit IRDA_WCTL. + UART_CONF0_IRDA_WCTL = 0x800 + // Position of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Pos = 0xc + // Bit mask of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Msk = 0x1000 + // Bit IRDA_TX_INV. + UART_CONF0_IRDA_TX_INV = 0x1000 + // Position of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Pos = 0xd + // Bit mask of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Msk = 0x2000 + // Bit IRDA_RX_INV. + UART_CONF0_IRDA_RX_INV = 0x2000 + // Position of LOOPBACK field. + UART_CONF0_LOOPBACK_Pos = 0xe + // Bit mask of LOOPBACK field. + UART_CONF0_LOOPBACK_Msk = 0x4000 + // Bit LOOPBACK. + UART_CONF0_LOOPBACK = 0x4000 + // Position of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Pos = 0xf + // Bit mask of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Msk = 0x8000 + // Bit TX_FLOW_EN. + UART_CONF0_TX_FLOW_EN = 0x8000 + // Position of IRDA_EN field. + UART_CONF0_IRDA_EN_Pos = 0x10 + // Bit mask of IRDA_EN field. + UART_CONF0_IRDA_EN_Msk = 0x10000 + // Bit IRDA_EN. + UART_CONF0_IRDA_EN = 0x10000 + // Position of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Pos = 0x11 + // Bit mask of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Msk = 0x20000 + // Bit RXFIFO_RST. + UART_CONF0_RXFIFO_RST = 0x20000 + // Position of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Pos = 0x12 + // Bit mask of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Msk = 0x40000 + // Bit TXFIFO_RST. + UART_CONF0_TXFIFO_RST = 0x40000 + // Position of RXD_INV field. + UART_CONF0_RXD_INV_Pos = 0x13 + // Bit mask of RXD_INV field. + UART_CONF0_RXD_INV_Msk = 0x80000 + // Bit RXD_INV. + UART_CONF0_RXD_INV = 0x80000 + // Position of CTS_INV field. + UART_CONF0_CTS_INV_Pos = 0x14 + // Bit mask of CTS_INV field. + UART_CONF0_CTS_INV_Msk = 0x100000 + // Bit CTS_INV. + UART_CONF0_CTS_INV = 0x100000 + // Position of DSR_INV field. + UART_CONF0_DSR_INV_Pos = 0x15 + // Bit mask of DSR_INV field. + UART_CONF0_DSR_INV_Msk = 0x200000 + // Bit DSR_INV. + UART_CONF0_DSR_INV = 0x200000 + // Position of TXD_INV field. + UART_CONF0_TXD_INV_Pos = 0x16 + // Bit mask of TXD_INV field. + UART_CONF0_TXD_INV_Msk = 0x400000 + // Bit TXD_INV. + UART_CONF0_TXD_INV = 0x400000 + // Position of RTS_INV field. + UART_CONF0_RTS_INV_Pos = 0x17 + // Bit mask of RTS_INV field. + UART_CONF0_RTS_INV_Msk = 0x800000 + // Bit RTS_INV. + UART_CONF0_RTS_INV = 0x800000 + // Position of DTR_INV field. + UART_CONF0_DTR_INV_Pos = 0x18 + // Bit mask of DTR_INV field. + UART_CONF0_DTR_INV_Msk = 0x1000000 + // Bit DTR_INV. + UART_CONF0_DTR_INV = 0x1000000 + // Position of CLK_EN field. + UART_CONF0_CLK_EN_Pos = 0x19 + // Bit mask of CLK_EN field. + UART_CONF0_CLK_EN_Msk = 0x2000000 + // Bit CLK_EN. + UART_CONF0_CLK_EN = 0x2000000 + // Position of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Pos = 0x1a + // Bit mask of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Msk = 0x4000000 + // Bit ERR_WR_MASK. + UART_CONF0_ERR_WR_MASK = 0x4000000 + // Position of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Pos = 0x1b + // Bit mask of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Msk = 0x8000000 + // Bit AUTOBAUD_EN. + UART_CONF0_AUTOBAUD_EN = 0x8000000 + // Position of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Pos = 0x1c + // Bit mask of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Msk = 0x10000000 + // Bit MEM_CLK_EN. + UART_CONF0_MEM_CLK_EN = 0x10000000 + + // CONF1: Configuration register 1 + // Position of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0x1ff + // Position of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0x9 + // Bit mask of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0x3fe00 + // Position of DIS_RX_DAT_OVF field. + UART_CONF1_DIS_RX_DAT_OVF_Pos = 0x12 + // Bit mask of DIS_RX_DAT_OVF field. + UART_CONF1_DIS_RX_DAT_OVF_Msk = 0x40000 + // Bit DIS_RX_DAT_OVF. + UART_CONF1_DIS_RX_DAT_OVF = 0x40000 + // Position of RX_TOUT_FLOW_DIS field. + UART_CONF1_RX_TOUT_FLOW_DIS_Pos = 0x13 + // Bit mask of RX_TOUT_FLOW_DIS field. + UART_CONF1_RX_TOUT_FLOW_DIS_Msk = 0x80000 + // Bit RX_TOUT_FLOW_DIS. + UART_CONF1_RX_TOUT_FLOW_DIS = 0x80000 + // Position of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Pos = 0x14 + // Bit mask of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Msk = 0x100000 + // Bit RX_FLOW_EN. + UART_CONF1_RX_FLOW_EN = 0x100000 + // Position of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Pos = 0x15 + // Bit mask of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Msk = 0x200000 + // Bit RX_TOUT_EN. + UART_CONF1_RX_TOUT_EN = 0x200000 + + // LOWPULSE: Autobaud minimum low pulse duration register + // Position of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Msk = 0xfff + + // HIGHPULSE: Autobaud minimum high pulse duration register + // Position of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Msk = 0xfff + + // RXD_CNT: Autobaud edge change count register + // Position of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0 + // Bit mask of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff + + // FLOW_CONF: Software flow-control configuration + // Position of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Pos = 0x0 + // Bit mask of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Msk = 0x1 + // Bit SW_FLOW_CON_EN. + UART_FLOW_CONF_SW_FLOW_CON_EN = 0x1 + // Position of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Pos = 0x1 + // Bit mask of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Msk = 0x2 + // Bit XONOFF_DEL. + UART_FLOW_CONF_XONOFF_DEL = 0x2 + // Position of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Pos = 0x2 + // Bit mask of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Msk = 0x4 + // Bit FORCE_XON. + UART_FLOW_CONF_FORCE_XON = 0x4 + // Position of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Pos = 0x3 + // Bit mask of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Msk = 0x8 + // Bit FORCE_XOFF. + UART_FLOW_CONF_FORCE_XOFF = 0x8 + // Position of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Pos = 0x4 + // Bit mask of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Msk = 0x10 + // Bit SEND_XON. + UART_FLOW_CONF_SEND_XON = 0x10 + // Position of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Pos = 0x5 + // Bit mask of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Msk = 0x20 + // Bit SEND_XOFF. + UART_FLOW_CONF_SEND_XOFF = 0x20 + + // SLEEP_CONF: Sleep-mode configuration + // Position of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Pos = 0x0 + // Bit mask of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Msk = 0x3ff + + // SWFC_CONF0: Software flow-control character configuration + // Position of XOFF_THRESHOLD field. + UART_SWFC_CONF0_XOFF_THRESHOLD_Pos = 0x0 + // Bit mask of XOFF_THRESHOLD field. + UART_SWFC_CONF0_XOFF_THRESHOLD_Msk = 0x1ff + // Position of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Pos = 0x9 + // Bit mask of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Msk = 0x1fe00 + + // SWFC_CONF1: Software flow-control character configuration + // Position of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x0 + // Bit mask of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0x1ff + // Position of XON_CHAR field. + UART_SWFC_CONF1_XON_CHAR_Pos = 0x9 + // Bit mask of XON_CHAR field. + UART_SWFC_CONF1_XON_CHAR_Msk = 0x1fe00 + + // TXBRK_CONF: Tx Break character configuration + // Position of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Pos = 0x0 + // Bit mask of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Msk = 0xff + + // IDLE_CONF: Frame-end idle configuration + // Position of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Pos = 0x0 + // Bit mask of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Msk = 0x3ff + // Position of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Pos = 0xa + // Bit mask of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Msk = 0xffc00 + + // RS485_CONF: RS485 mode configuration + // Position of RS485_EN field. + UART_RS485_CONF_RS485_EN_Pos = 0x0 + // Bit mask of RS485_EN field. + UART_RS485_CONF_RS485_EN_Msk = 0x1 + // Bit RS485_EN. + UART_RS485_CONF_RS485_EN = 0x1 + // Position of DL0_EN field. + UART_RS485_CONF_DL0_EN_Pos = 0x1 + // Bit mask of DL0_EN field. + UART_RS485_CONF_DL0_EN_Msk = 0x2 + // Bit DL0_EN. + UART_RS485_CONF_DL0_EN = 0x2 + // Position of DL1_EN field. + UART_RS485_CONF_DL1_EN_Pos = 0x2 + // Bit mask of DL1_EN field. + UART_RS485_CONF_DL1_EN_Msk = 0x4 + // Bit DL1_EN. + UART_RS485_CONF_DL1_EN = 0x4 + // Position of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Pos = 0x3 + // Bit mask of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Msk = 0x8 + // Bit RS485TX_RX_EN. + UART_RS485_CONF_RS485TX_RX_EN = 0x8 + // Position of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Pos = 0x4 + // Bit mask of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Msk = 0x10 + // Bit RS485RXBY_TX_EN. + UART_RS485_CONF_RS485RXBY_TX_EN = 0x10 + // Position of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Pos = 0x5 + // Bit mask of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Msk = 0x20 + // Bit RS485_RX_DLY_NUM. + UART_RS485_CONF_RS485_RX_DLY_NUM = 0x20 + // Position of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Pos = 0x6 + // Bit mask of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Msk = 0x3c0 + + // AT_CMD_PRECNT: Pre-sequence timing configuration + // Position of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Pos = 0x0 + // Bit mask of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Msk = 0xffff + + // AT_CMD_POSTCNT: Post-sequence timing configuration + // Position of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Pos = 0x0 + // Bit mask of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Msk = 0xffff + + // AT_CMD_GAPTOUT: Timeout configuration + // Position of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Pos = 0x0 + // Bit mask of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Msk = 0xffff + + // AT_CMD_CHAR: AT escape sequence detection configuration + // Position of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Pos = 0x0 + // Bit mask of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Msk = 0xff + // Position of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Pos = 0x8 + // Bit mask of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Msk = 0xff00 + + // MEM_CONF: UART threshold and allocation configuration + // Position of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Pos = 0x1 + // Bit mask of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Msk = 0xe + // Position of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Pos = 0x4 + // Bit mask of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Msk = 0x70 + // Position of RX_FLOW_THRHD field. + UART_MEM_CONF_RX_FLOW_THRHD_Pos = 0x7 + // Bit mask of RX_FLOW_THRHD field. + UART_MEM_CONF_RX_FLOW_THRHD_Msk = 0xff80 + // Position of RX_TOUT_THRHD field. + UART_MEM_CONF_RX_TOUT_THRHD_Pos = 0x10 + // Bit mask of RX_TOUT_THRHD field. + UART_MEM_CONF_RX_TOUT_THRHD_Msk = 0x3ff0000 + // Position of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x1a + // Bit mask of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x4000000 + // Bit MEM_FORCE_PD. + UART_MEM_CONF_MEM_FORCE_PD = 0x4000000 + // Position of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1b + // Bit mask of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x8000000 + // Bit MEM_FORCE_PU. + UART_MEM_CONF_MEM_FORCE_PU = 0x8000000 + + // MEM_TX_STATUS: Tx-FIFO write and read offset address. + // Position of APB_TX_WADDR field. + UART_MEM_TX_STATUS_APB_TX_WADDR_Pos = 0x0 + // Bit mask of APB_TX_WADDR field. + UART_MEM_TX_STATUS_APB_TX_WADDR_Msk = 0x3ff + // Position of TX_RADDR field. + UART_MEM_TX_STATUS_TX_RADDR_Pos = 0xb + // Bit mask of TX_RADDR field. + UART_MEM_TX_STATUS_TX_RADDR_Msk = 0x1ff800 + + // MEM_RX_STATUS: Rx-FIFO write and read offset address. + // Position of APB_RX_RADDR field. + UART_MEM_RX_STATUS_APB_RX_RADDR_Pos = 0x0 + // Bit mask of APB_RX_RADDR field. + UART_MEM_RX_STATUS_APB_RX_RADDR_Msk = 0x3ff + // Position of RX_WADDR field. + UART_MEM_RX_STATUS_RX_WADDR_Pos = 0xb + // Bit mask of RX_WADDR field. + UART_MEM_RX_STATUS_RX_WADDR_Msk = 0x1ff800 + + // FSM_STATUS: UART transmit and receive status. + // Position of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0 + // Bit mask of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf + // Position of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4 + // Bit mask of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0 + + // POSPULSE: Autobaud high pulse register + // Position of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Msk = 0xfff + + // NEGPULSE: Autobaud low pulse register + // Position of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Msk = 0xfff + + // CLK_CONF: UART core clock configuration + // Position of SCLK_DIV_B field. + UART_CLK_CONF_SCLK_DIV_B_Pos = 0x0 + // Bit mask of SCLK_DIV_B field. + UART_CLK_CONF_SCLK_DIV_B_Msk = 0x3f + // Position of SCLK_DIV_A field. + UART_CLK_CONF_SCLK_DIV_A_Pos = 0x6 + // Bit mask of SCLK_DIV_A field. + UART_CLK_CONF_SCLK_DIV_A_Msk = 0xfc0 + // Position of SCLK_DIV_NUM field. + UART_CLK_CONF_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of SCLK_DIV_NUM field. + UART_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff000 + // Position of SCLK_SEL field. + UART_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + UART_CLK_CONF_SCLK_SEL_Msk = 0x300000 + // Position of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Pos = 0x16 + // Bit mask of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Msk = 0x400000 + // Bit SCLK_EN. + UART_CLK_CONF_SCLK_EN = 0x400000 + // Position of RST_CORE field. + UART_CLK_CONF_RST_CORE_Pos = 0x17 + // Bit mask of RST_CORE field. + UART_CLK_CONF_RST_CORE_Msk = 0x800000 + // Bit RST_CORE. + UART_CLK_CONF_RST_CORE = 0x800000 + // Position of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Pos = 0x18 + // Bit mask of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Msk = 0x1000000 + // Bit TX_SCLK_EN. + UART_CLK_CONF_TX_SCLK_EN = 0x1000000 + // Position of RX_SCLK_EN field. + UART_CLK_CONF_RX_SCLK_EN_Pos = 0x19 + // Bit mask of RX_SCLK_EN field. + UART_CLK_CONF_RX_SCLK_EN_Msk = 0x2000000 + // Bit RX_SCLK_EN. + UART_CLK_CONF_RX_SCLK_EN = 0x2000000 + // Position of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Pos = 0x1a + // Bit mask of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Msk = 0x4000000 + // Bit TX_RST_CORE. + UART_CLK_CONF_TX_RST_CORE = 0x4000000 + // Position of RX_RST_CORE field. + UART_CLK_CONF_RX_RST_CORE_Pos = 0x1b + // Bit mask of RX_RST_CORE field. + UART_CLK_CONF_RX_RST_CORE_Msk = 0x8000000 + // Bit RX_RST_CORE. + UART_CLK_CONF_RX_RST_CORE = 0x8000000 + + // DATE: UART Version register + // Position of DATE field. + UART_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UART_DATE_DATE_Msk = 0xffffffff + + // ID: UART ID register + // Position of ID field. + UART_ID_ID_Pos = 0x0 + // Bit mask of ID field. + UART_ID_ID_Msk = 0x3fffffff + // Position of HIGH_SPEED field. + UART_ID_HIGH_SPEED_Pos = 0x1e + // Bit mask of HIGH_SPEED field. + UART_ID_HIGH_SPEED_Msk = 0x40000000 + // Bit HIGH_SPEED. + UART_ID_HIGH_SPEED = 0x40000000 + // Position of REG_UPDATE field. + UART_ID_REG_UPDATE_Pos = 0x1f + // Bit mask of REG_UPDATE field. + UART_ID_REG_UPDATE_Msk = 0x80000000 + // Bit REG_UPDATE. + UART_ID_REG_UPDATE = 0x80000000 +) + +// Constants for XTS_AES: XTS-AES-128 Flash Encryption +const ( + // LINESIZE: XTS-AES line-size register + // Position of LINESIZE field. + XTS_AES_LINESIZE_LINESIZE_Pos = 0x0 + // Bit mask of LINESIZE field. + XTS_AES_LINESIZE_LINESIZE_Msk = 0x1 + // Bit LINESIZE. + XTS_AES_LINESIZE_LINESIZE = 0x1 + + // DESTINATION: XTS-AES destination register + // Position of DESTINATION field. + XTS_AES_DESTINATION_DESTINATION_Pos = 0x0 + // Bit mask of DESTINATION field. + XTS_AES_DESTINATION_DESTINATION_Msk = 0x1 + // Bit DESTINATION. + XTS_AES_DESTINATION_DESTINATION = 0x1 + + // PHYSICAL_ADDRESS: XTS-AES physical address register + // Position of PHYSICAL_ADDRESS field. + XTS_AES_PHYSICAL_ADDRESS_PHYSICAL_ADDRESS_Pos = 0x0 + // Bit mask of PHYSICAL_ADDRESS field. + XTS_AES_PHYSICAL_ADDRESS_PHYSICAL_ADDRESS_Msk = 0x3fffffff + + // TRIGGER: XTS-AES trigger register + // Position of TRIGGER field. + XTS_AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + XTS_AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + XTS_AES_TRIGGER_TRIGGER = 0x1 + + // RELEASE: XTS-AES release register + // Position of RELEASE field. + XTS_AES_RELEASE_RELEASE_Pos = 0x0 + // Bit mask of RELEASE field. + XTS_AES_RELEASE_RELEASE_Msk = 0x1 + // Bit RELEASE. + XTS_AES_RELEASE_RELEASE = 0x1 + + // DESTROY: XTS-AES destroy register + // Position of DESTROY field. + XTS_AES_DESTROY_DESTROY_Pos = 0x0 + // Bit mask of DESTROY field. + XTS_AES_DESTROY_DESTROY_Msk = 0x1 + // Bit DESTROY. + XTS_AES_DESTROY_DESTROY = 0x1 + + // STATE: XTS-AES status register + // Position of STATE field. + XTS_AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + XTS_AES_STATE_STATE_Msk = 0x3 + + // DATE: XTS-AES version control register + // Position of DATE field. + XTS_AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + XTS_AES_DATE_DATE_Msk = 0x3fffffff +) diff --git a/emb/device/esp/esp32c3.S b/emb/device/esp/esp32c3.S new file mode 100644 index 0000000..0395d73 --- /dev/null +++ b/emb/device/esp/esp32c3.S @@ -0,0 +1,67 @@ +// This is a very minimal bootloader for the ESP32-C3. It only initializes the +// flash and then continues with the generic RISC-V initialization code, which +// in turn will call runtime.main. +// It is written in assembly (and not in a higher level language) to make sure +// it is entirely loaded into IRAM and doesn't accidentally call functions +// stored in IROM. +// +// For reference, here is a nice introduction into RISC-V assembly: +// https://www.imperialviolet.org/2016/12/31/riscv.html + +.section .init +.global call_start_cpu0 +.type call_start_cpu0,@function +call_start_cpu0: + // At this point: + // - The ROM bootloader is finished and has jumped to here. + // - We're running from IRAM: both IRAM and DRAM segments have been loaded + // by the ROM bootloader. + // - We have a usable stack (but not the one we would like to use). + // - No flash mappings (MMU) are set up yet. + + // Reset MMU, see bootloader_reset_mmu in the ESP-IDF. + call Cache_Suspend_ICache + mv s0, a0 // autoload value + call Cache_Invalidate_ICache_All + call Cache_MMU_Init + + // Set up DROM from flash. + // Somehow, this also sets up IROM from flash. Not sure why, but it avoids + // the need for another such call. + // C equivalent: + // Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, 0x3C00_0000, 0, 64, 128, 0) + li a0, 0 // ext_ram: MMU_ACCESS_FLASH + li a1, 0x3C000000 // vaddr: address in the data bus + li a2, 0 // paddr: physical address in the flash chip + li a3, 64 // psize: always 64 (kilobytes) + li a4, 128 // num: pages to be set (8192K / 64K = 128) + li a5, 0 // fixed + call Cache_Dbus_MMU_Set + + // Enable the flash cache. + mv a0, s0 // restore autoload value from Cache_Suspend_ICache call + call Cache_Resume_ICache + + // Jump to generic RISC-V initialization, which initializes the stack + // pointer and globals register. It should not return. + // (It appears that the linker relaxes this jump and instead inserts the + // _start function right after here). + j _start + +.section .text.exception_vectors +.global _vector_table +.type _vector_table,@function + +_vector_table: + + .option push + .option norvc + + .rept 32 + j handleInterruptASM /* interrupt handler */ + .endr + + .option pop + +.size _vector_table, .-_vector_table + diff --git a/emb/device/esp/esp32c3.go b/emb/device/esp/esp32c3.go new file mode 100644 index 0000000..fd94177 --- /dev/null +++ b/emb/device/esp/esp32c3.go @@ -0,0 +1,54203 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32c3.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32c3 + +/* +// 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) +*/ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32-C3" + CPU = "RV32IMC" + FPUPresent = false + NVICPrioBits = 0 +) + +// Interrupt numbers. +const ( + // Interrupt Controller (Core 0) + IRQ_WIFI_MAC = 0 + + // Interrupt Controller (Core 0) + IRQ_WIFI_MAC_NMI = 1 + + // Interrupt Controller (Core 0) + IRQ_WIFI_PWR = 2 + + // Interrupt Controller (Core 0) + IRQ_WIFI_BB = 3 + + // Interrupt Controller (Core 0) + IRQ_BT_MAC = 4 + + // Interrupt Controller (Core 0) + IRQ_BT_BB = 5 + + // Interrupt Controller (Core 0) + IRQ_BT_BB_NMI = 6 + + // Interrupt Controller (Core 0) + IRQ_RWBT = 7 + + // Interrupt Controller (Core 0) + IRQ_RWBLE = 8 + + // Interrupt Controller (Core 0) + IRQ_RWBT_NMI = 9 + + // Interrupt Controller (Core 0) + IRQ_RWBLE_NMI = 10 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_MASTER = 11 + + // Interrupt Controller (Core 0) + IRQ_SLC0 = 12 + + // Interrupt Controller (Core 0) + IRQ_SLC1 = 13 + + // APB (Advanced Peripheral Bus) Controller + IRQ_APB_CTRL = 14 + + // Universal Host Controller Interface 0 + IRQ_UHCI0 = 15 + + // General Purpose Input/Output + IRQ_GPIO = 16 + + // General Purpose Input/Output + IRQ_GPIO_NMI = 17 + + // SPI (Serial Peripheral Interface) Controller 1 + IRQ_SPI1 = 18 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_SPI2 = 19 + + // I2S (Inter-IC Sound) Controller 0 + IRQ_I2S0 = 20 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + IRQ_UART0 = 21 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + IRQ_UART1 = 22 + + // LED Control PWM (Pulse Width Modulation) + IRQ_LEDC = 23 + + // eFuse Controller + IRQ_EFUSE = 24 + + // Two-Wire Automotive Interface + IRQ_TWAI0 = 25 + + // Full-speed USB Serial/JTAG Controller + IRQ_USB_DEVICE = 26 + + // Real-Time Clock Control + IRQ_RTC_CORE = 27 + + // Remote Control + IRQ_RMT = 28 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_EXT0 = 29 + + // LED Control PWM (Pulse Width Modulation) + IRQ_TIMER1 = 30 + + // LED Control PWM (Pulse Width Modulation) + IRQ_TIMER2 = 31 + + // Timer Group 0 + IRQ_TG0_T0_LEVEL = 32 + + // Timer Group 0 + IRQ_TG0_WDT_LEVEL = 33 + + // Timer Group 1 + IRQ_TG1_T0_LEVEL = 34 + + // Timer Group 1 + IRQ_TG1_WDT_LEVEL = 35 + + // Interrupt Controller (Core 0) + IRQ_CACHE_IA = 36 + + // System Timer + IRQ_SYSTIMER_TARGET0 = 37 + + // System Timer + IRQ_SYSTIMER_TARGET1 = 38 + + // System Timer + IRQ_SYSTIMER_TARGET2 = 39 + + // SPI (Serial Peripheral Interface) Controller 0 + IRQ_SPI_MEM_REJECT_CACHE = 40 + + // Interrupt Controller (Core 0) + IRQ_ICACHE_PRELOAD0 = 41 + + // Interrupt Controller (Core 0) + IRQ_ICACHE_SYNC0 = 42 + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + IRQ_APB_ADC = 43 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_CH0 = 44 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_CH1 = 45 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_CH2 = 46 + + // RSA (Rivest Shamir Adleman) Accelerator + IRQ_RSA = 47 + + // AES (Advanced Encryption Standard) Accelerator + IRQ_AES = 48 + + // SHA (Secure Hash Algorithm) Accelerator + IRQ_SHA = 49 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR0 = 50 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR1 = 51 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR2 = 52 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR3 = 53 + + // Debug Assist + IRQ_ASSIST_DEBUG = 54 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_APBPERI_PMS = 55 + + // Interrupt Controller (Core 0) + IRQ_CORE0_IRAM0_PMS = 56 + + // Interrupt Controller (Core 0) + IRQ_CORE0_DRAM0_PMS = 57 + + // Interrupt Controller (Core 0) + IRQ_CORE0_PIF_PMS = 58 + + // Interrupt Controller (Core 0) + IRQ_CORE0_PIF_PMS_SIZE = 59 + + // Interrupt Controller (Core 0) + IRQ_BAK_PMS_VIOLATE = 60 + + // Interrupt Controller (Core 0) + IRQ_CACHE_CORE0_ACS = 61 + + // Highest interrupt number on this device. + IRQ_max = 61 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_WIFI_MAC: + callHandlers(IRQ_WIFI_MAC) + case IRQ_WIFI_MAC_NMI: + callHandlers(IRQ_WIFI_MAC_NMI) + case IRQ_WIFI_PWR: + callHandlers(IRQ_WIFI_PWR) + case IRQ_WIFI_BB: + callHandlers(IRQ_WIFI_BB) + case IRQ_BT_MAC: + callHandlers(IRQ_BT_MAC) + case IRQ_BT_BB: + callHandlers(IRQ_BT_BB) + case IRQ_BT_BB_NMI: + callHandlers(IRQ_BT_BB_NMI) + case IRQ_RWBT: + callHandlers(IRQ_RWBT) + case IRQ_RWBLE: + callHandlers(IRQ_RWBLE) + case IRQ_RWBT_NMI: + callHandlers(IRQ_RWBT_NMI) + case IRQ_RWBLE_NMI: + callHandlers(IRQ_RWBLE_NMI) + case IRQ_I2C_MASTER: + callHandlers(IRQ_I2C_MASTER) + case IRQ_SLC0: + callHandlers(IRQ_SLC0) + case IRQ_SLC1: + callHandlers(IRQ_SLC1) + case IRQ_APB_CTRL: + callHandlers(IRQ_APB_CTRL) + case IRQ_UHCI0: + callHandlers(IRQ_UHCI0) + case IRQ_GPIO: + callHandlers(IRQ_GPIO) + case IRQ_GPIO_NMI: + callHandlers(IRQ_GPIO_NMI) + case IRQ_SPI1: + callHandlers(IRQ_SPI1) + case IRQ_SPI2: + callHandlers(IRQ_SPI2) + case IRQ_I2S0: + callHandlers(IRQ_I2S0) + case IRQ_UART0: + callHandlers(IRQ_UART0) + case IRQ_UART1: + callHandlers(IRQ_UART1) + case IRQ_LEDC: + callHandlers(IRQ_LEDC) + case IRQ_EFUSE: + callHandlers(IRQ_EFUSE) + case IRQ_TWAI0: + callHandlers(IRQ_TWAI0) + case IRQ_USB_DEVICE: + callHandlers(IRQ_USB_DEVICE) + case IRQ_RTC_CORE: + callHandlers(IRQ_RTC_CORE) + case IRQ_RMT: + callHandlers(IRQ_RMT) + case IRQ_I2C_EXT0: + callHandlers(IRQ_I2C_EXT0) + case IRQ_TIMER1: + callHandlers(IRQ_TIMER1) + case IRQ_TIMER2: + callHandlers(IRQ_TIMER2) + case IRQ_TG0_T0_LEVEL: + callHandlers(IRQ_TG0_T0_LEVEL) + case IRQ_TG0_WDT_LEVEL: + callHandlers(IRQ_TG0_WDT_LEVEL) + case IRQ_TG1_T0_LEVEL: + callHandlers(IRQ_TG1_T0_LEVEL) + case IRQ_TG1_WDT_LEVEL: + callHandlers(IRQ_TG1_WDT_LEVEL) + case IRQ_CACHE_IA: + callHandlers(IRQ_CACHE_IA) + case IRQ_SYSTIMER_TARGET0: + callHandlers(IRQ_SYSTIMER_TARGET0) + case IRQ_SYSTIMER_TARGET1: + callHandlers(IRQ_SYSTIMER_TARGET1) + case IRQ_SYSTIMER_TARGET2: + callHandlers(IRQ_SYSTIMER_TARGET2) + case IRQ_SPI_MEM_REJECT_CACHE: + callHandlers(IRQ_SPI_MEM_REJECT_CACHE) + case IRQ_ICACHE_PRELOAD0: + callHandlers(IRQ_ICACHE_PRELOAD0) + case IRQ_ICACHE_SYNC0: + callHandlers(IRQ_ICACHE_SYNC0) + case IRQ_APB_ADC: + callHandlers(IRQ_APB_ADC) + case IRQ_DMA_CH0: + callHandlers(IRQ_DMA_CH0) + case IRQ_DMA_CH1: + callHandlers(IRQ_DMA_CH1) + case IRQ_DMA_CH2: + callHandlers(IRQ_DMA_CH2) + case IRQ_RSA: + callHandlers(IRQ_RSA) + case IRQ_AES: + callHandlers(IRQ_AES) + case IRQ_SHA: + callHandlers(IRQ_SHA) + case IRQ_FROM_CPU_INTR0: + callHandlers(IRQ_FROM_CPU_INTR0) + case IRQ_FROM_CPU_INTR1: + callHandlers(IRQ_FROM_CPU_INTR1) + case IRQ_FROM_CPU_INTR2: + callHandlers(IRQ_FROM_CPU_INTR2) + case IRQ_FROM_CPU_INTR3: + callHandlers(IRQ_FROM_CPU_INTR3) + case IRQ_ASSIST_DEBUG: + callHandlers(IRQ_ASSIST_DEBUG) + case IRQ_DMA_APBPERI_PMS: + callHandlers(IRQ_DMA_APBPERI_PMS) + case IRQ_CORE0_IRAM0_PMS: + callHandlers(IRQ_CORE0_IRAM0_PMS) + case IRQ_CORE0_DRAM0_PMS: + callHandlers(IRQ_CORE0_DRAM0_PMS) + case IRQ_CORE0_PIF_PMS: + callHandlers(IRQ_CORE0_PIF_PMS) + case IRQ_CORE0_PIF_PMS_SIZE: + callHandlers(IRQ_CORE0_PIF_PMS_SIZE) + case IRQ_BAK_PMS_VIOLATE: + callHandlers(IRQ_BAK_PMS_VIOLATE) + case IRQ_CACHE_CORE0_ACS: + callHandlers(IRQ_CACHE_CORE0_ACS) + } +} + +// Peripherals. +var ( + // AES (Advanced Encryption Standard) Accelerator + AES = (*AES_Type)(unsafe.Pointer(uintptr(0x6003a000))) + + // APB (Advanced Peripheral Bus) Controller + APB_CTRL = (*APB_CTRL_Type)(unsafe.Pointer(uintptr(0x60026000))) + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + APB_SARADC = (*APB_SARADC_Type)(unsafe.Pointer(uintptr(0x60040000))) + + // Debug Assist + ASSIST_DEBUG = (*ASSIST_DEBUG_Type)(unsafe.Pointer(uintptr(0x600ce000))) + + // BB Peripheral + BB = (*BB_Type)(unsafe.Pointer(uintptr(0x6001d000))) + + // DMA (Direct Memory Access) Controller + DMA = (*DMA_Type)(unsafe.Pointer(uintptr(0x6003f000))) + + // Digital Signature + DS = (*DS_Type)(unsafe.Pointer(uintptr(0x6003d000))) + + // eFuse Controller + EFUSE = (*EFUSE_Type)(unsafe.Pointer(uintptr(0x60008800))) + + // External Memory + EXTMEM = (*EXTMEM_Type)(unsafe.Pointer(uintptr(0x600c4000))) + + // General Purpose Input/Output + GPIO = (*GPIO_Type)(unsafe.Pointer(uintptr(0x60004000))) + + // Sigma-Delta Modulation + GPIO_SD = (*GPIOSD_Type)(unsafe.Pointer(uintptr(0x60004f00))) + + // HMAC (Hash-based Message Authentication Code) Accelerator + HMAC = (*HMAC_Type)(unsafe.Pointer(uintptr(0x6003e000))) + + // I2C (Inter-Integrated Circuit) Controller 0 + I2C0 = (*I2C_Type)(unsafe.Pointer(uintptr(0x60013000))) + + // I2S (Inter-IC Sound) Controller 0 + I2S0 = (*I2S_Type)(unsafe.Pointer(uintptr(0x6002d000))) + + // Interrupt Controller (Core 0) + INTERRUPT_CORE0 = (*INTERRUPT_CORE0_Type)(unsafe.Pointer(uintptr(0x600c2000))) + + // Input/Output Multiplexer + IO_MUX = (*IO_MUX_Type)(unsafe.Pointer(uintptr(0x60009000))) + + // LED Control PWM (Pulse Width Modulation) + LEDC = (*LEDC_Type)(unsafe.Pointer(uintptr(0x60019000))) + + // Remote Control + RMT = (*RMT_Type)(unsafe.Pointer(uintptr(0x60016000))) + + // Hardware Random Number Generator + RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x60026000))) + + // RSA (Rivest Shamir Adleman) Accelerator + RSA = (*RSA_Type)(unsafe.Pointer(uintptr(0x6003c000))) + + // Real-Time Clock Control + RTC_CNTL = (*RTC_CNTL_Type)(unsafe.Pointer(uintptr(0x60008000))) + + // SENSITIVE Peripheral + SENSITIVE = (*SENSITIVE_Type)(unsafe.Pointer(uintptr(0x600c1000))) + + // SHA (Secure Hash Algorithm) Accelerator + SHA = (*SHA_Type)(unsafe.Pointer(uintptr(0x6003b000))) + + // SPI (Serial Peripheral Interface) Controller 0 + SPI0 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x60003000))) + + // SPI (Serial Peripheral Interface) Controller 1 + SPI1 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x60002000))) + + // SPI (Serial Peripheral Interface) Controller 2 + SPI2 = (*SPI2_Type)(unsafe.Pointer(uintptr(0x60024000))) + + // System Configuration Registers + SYSTEM = (*SYSTEM_Type)(unsafe.Pointer(uintptr(0x600c0000))) + + // System Timer + SYSTIMER = (*SYSTIMER_Type)(unsafe.Pointer(uintptr(0x60023000))) + + // Timer Group 0 + TIMG0 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x6001f000))) + + // Two-Wire Automotive Interface + TWAI0 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x6002b000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART0 = (*UART_Type)(unsafe.Pointer(uintptr(0x60000000))) + + // Universal Host Controller Interface 0 + UHCI0 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x60014000))) + + // Full-speed USB Serial/JTAG Controller + USB_DEVICE = (*USB_DEVICE_Type)(unsafe.Pointer(uintptr(0x60043000))) + + // XTS-AES-128 Flash Encryption + XTS_AES = (*XTS_AES_Type)(unsafe.Pointer(uintptr(0x600cc000))) + + // Timer Group 1 + TIMG1 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x60020000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + UART1 = (*UART_Type)(unsafe.Pointer(uintptr(0x60010000))) + + // Universal Host Controller Interface 1 + UHCI1 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x6000c000))) +) + +// AES (Advanced Encryption Standard) Accelerator +type AES_Type struct { + KEY_0 volatile.Register32 // 0x0 + KEY_1 volatile.Register32 // 0x4 + KEY_2 volatile.Register32 // 0x8 + KEY_3 volatile.Register32 // 0xC + KEY_4 volatile.Register32 // 0x10 + KEY_5 volatile.Register32 // 0x14 + KEY_6 volatile.Register32 // 0x18 + KEY_7 volatile.Register32 // 0x1C + TEXT_IN_0 volatile.Register32 // 0x20 + TEXT_IN_1 volatile.Register32 // 0x24 + TEXT_IN_2 volatile.Register32 // 0x28 + TEXT_IN_3 volatile.Register32 // 0x2C + TEXT_OUT_0 volatile.Register32 // 0x30 + TEXT_OUT_1 volatile.Register32 // 0x34 + TEXT_OUT_2 volatile.Register32 // 0x38 + TEXT_OUT_3 volatile.Register32 // 0x3C + MODE volatile.Register32 // 0x40 + ENDIAN volatile.Register32 // 0x44 + TRIGGER volatile.Register32 // 0x48 + STATE volatile.Register32 // 0x4C + IV_MEM [16]volatile.Register8 // 0x50 + H_MEM [16]volatile.Register8 // 0x60 + J0_MEM [16]volatile.Register8 // 0x70 + T0_MEM [16]volatile.Register8 // 0x80 + DMA_ENABLE volatile.Register32 // 0x90 + BLOCK_MODE volatile.Register32 // 0x94 + BLOCK_NUM volatile.Register32 // 0x98 + INC_SEL volatile.Register32 // 0x9C + AAD_BLOCK_NUM volatile.Register32 // 0xA0 + REMAINDER_BIT_NUM volatile.Register32 // 0xA4 + CONTINUE volatile.Register32 // 0xA8 + INT_CLEAR volatile.Register32 // 0xAC + INT_ENA volatile.Register32 // 0xB0 + DATE volatile.Register32 // 0xB4 + DMA_EXIT volatile.Register32 // 0xB8 +} + +// AES.KEY_0: Key material key_0 configure register +func (o *AES_Type) SetKEY_0(value uint32) { + volatile.StoreUint32(&o.KEY_0.Reg, value) +} +func (o *AES_Type) GetKEY_0() uint32 { + return volatile.LoadUint32(&o.KEY_0.Reg) +} + +// AES.KEY_1: Key material key_1 configure register +func (o *AES_Type) SetKEY_1(value uint32) { + volatile.StoreUint32(&o.KEY_1.Reg, value) +} +func (o *AES_Type) GetKEY_1() uint32 { + return volatile.LoadUint32(&o.KEY_1.Reg) +} + +// AES.KEY_2: Key material key_2 configure register +func (o *AES_Type) SetKEY_2(value uint32) { + volatile.StoreUint32(&o.KEY_2.Reg, value) +} +func (o *AES_Type) GetKEY_2() uint32 { + return volatile.LoadUint32(&o.KEY_2.Reg) +} + +// AES.KEY_3: Key material key_3 configure register +func (o *AES_Type) SetKEY_3(value uint32) { + volatile.StoreUint32(&o.KEY_3.Reg, value) +} +func (o *AES_Type) GetKEY_3() uint32 { + return volatile.LoadUint32(&o.KEY_3.Reg) +} + +// AES.KEY_4: Key material key_4 configure register +func (o *AES_Type) SetKEY_4(value uint32) { + volatile.StoreUint32(&o.KEY_4.Reg, value) +} +func (o *AES_Type) GetKEY_4() uint32 { + return volatile.LoadUint32(&o.KEY_4.Reg) +} + +// AES.KEY_5: Key material key_5 configure register +func (o *AES_Type) SetKEY_5(value uint32) { + volatile.StoreUint32(&o.KEY_5.Reg, value) +} +func (o *AES_Type) GetKEY_5() uint32 { + return volatile.LoadUint32(&o.KEY_5.Reg) +} + +// AES.KEY_6: Key material key_6 configure register +func (o *AES_Type) SetKEY_6(value uint32) { + volatile.StoreUint32(&o.KEY_6.Reg, value) +} +func (o *AES_Type) GetKEY_6() uint32 { + return volatile.LoadUint32(&o.KEY_6.Reg) +} + +// AES.KEY_7: Key material key_7 configure register +func (o *AES_Type) SetKEY_7(value uint32) { + volatile.StoreUint32(&o.KEY_7.Reg, value) +} +func (o *AES_Type) GetKEY_7() uint32 { + return volatile.LoadUint32(&o.KEY_7.Reg) +} + +// AES.TEXT_IN_0: source text material text_in_0 configure register +func (o *AES_Type) SetTEXT_IN_0(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_0.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_0() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_0.Reg) +} + +// AES.TEXT_IN_1: source text material text_in_1 configure register +func (o *AES_Type) SetTEXT_IN_1(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_1.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_1() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_1.Reg) +} + +// AES.TEXT_IN_2: source text material text_in_2 configure register +func (o *AES_Type) SetTEXT_IN_2(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_2.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_2() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_2.Reg) +} + +// AES.TEXT_IN_3: source text material text_in_3 configure register +func (o *AES_Type) SetTEXT_IN_3(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_3.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_3() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_3.Reg) +} + +// AES.TEXT_OUT_0: result text material text_out_0 configure register +func (o *AES_Type) SetTEXT_OUT_0(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_0.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_0() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_0.Reg) +} + +// AES.TEXT_OUT_1: result text material text_out_1 configure register +func (o *AES_Type) SetTEXT_OUT_1(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_1.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_1() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_1.Reg) +} + +// AES.TEXT_OUT_2: result text material text_out_2 configure register +func (o *AES_Type) SetTEXT_OUT_2(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_2.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_2() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_2.Reg) +} + +// AES.TEXT_OUT_3: result text material text_out_3 configure register +func (o *AES_Type) SetTEXT_OUT_3(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_3.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_3() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_3.Reg) +} + +// AES.MODE: AES Mode register +func (o *AES_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// AES.ENDIAN: AES Endian configure register +func (o *AES_Type) SetENDIAN(value uint32) { + volatile.StoreUint32(&o.ENDIAN.Reg, volatile.LoadUint32(&o.ENDIAN.Reg)&^(0x3f)|value) +} +func (o *AES_Type) GetENDIAN() uint32 { + return volatile.LoadUint32(&o.ENDIAN.Reg) & 0x3f +} + +// AES.TRIGGER: AES trigger register +func (o *AES_Type) SetTRIGGER(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetTRIGGER() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} + +// AES.STATE: AES state register +func (o *AES_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *AES_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// AES.DMA_ENABLE: DMA-AES working mode register +func (o *AES_Type) SetDMA_ENABLE(value uint32) { + volatile.StoreUint32(&o.DMA_ENABLE.Reg, volatile.LoadUint32(&o.DMA_ENABLE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_ENABLE() uint32 { + return volatile.LoadUint32(&o.DMA_ENABLE.Reg) & 0x1 +} + +// AES.BLOCK_MODE: AES cipher block mode register +func (o *AES_Type) SetBLOCK_MODE(value uint32) { + volatile.StoreUint32(&o.BLOCK_MODE.Reg, volatile.LoadUint32(&o.BLOCK_MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetBLOCK_MODE() uint32 { + return volatile.LoadUint32(&o.BLOCK_MODE.Reg) & 0x7 +} + +// AES.BLOCK_NUM: AES block number register +func (o *AES_Type) SetBLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetBLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.BLOCK_NUM.Reg) +} + +// AES.INC_SEL: Standard incrementing function configure register +func (o *AES_Type) SetINC_SEL(value uint32) { + volatile.StoreUint32(&o.INC_SEL.Reg, volatile.LoadUint32(&o.INC_SEL.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINC_SEL() uint32 { + return volatile.LoadUint32(&o.INC_SEL.Reg) & 0x1 +} + +// AES.AAD_BLOCK_NUM: Additional Authential Data block number register +func (o *AES_Type) SetAAD_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.AAD_BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetAAD_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.AAD_BLOCK_NUM.Reg) +} + +// AES.REMAINDER_BIT_NUM: AES remainder bit number register +func (o *AES_Type) SetREMAINDER_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.REMAINDER_BIT_NUM.Reg, volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg)&^(0x7f)|value) +} +func (o *AES_Type) GetREMAINDER_BIT_NUM() uint32 { + return volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg) & 0x7f +} + +// AES.CONTINUE: AES continue register +func (o *AES_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetCONTINUE() uint32 { + return volatile.LoadUint32(&o.CONTINUE.Reg) & 0x1 +} + +// AES.INT_CLEAR: AES Interrupt clear register +func (o *AES_Type) SetINT_CLEAR(value uint32) { + volatile.StoreUint32(&o.INT_CLEAR.Reg, volatile.LoadUint32(&o.INT_CLEAR.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_CLEAR() uint32 { + return volatile.LoadUint32(&o.INT_CLEAR.Reg) & 0x1 +} + +// AES.INT_ENA: AES Interrupt enable register +func (o *AES_Type) SetINT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// AES.DATE: AES version control register +func (o *AES_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *AES_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// AES.DMA_EXIT: AES-DMA exit config +func (o *AES_Type) SetDMA_EXIT(value uint32) { + volatile.StoreUint32(&o.DMA_EXIT.Reg, volatile.LoadUint32(&o.DMA_EXIT.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_EXIT() uint32 { + return volatile.LoadUint32(&o.DMA_EXIT.Reg) & 0x1 +} + +// APB (Advanced Peripheral Bus) Controller +type APB_CTRL_Type struct { + SYSCLK_CONF volatile.Register32 // 0x0 + TICK_CONF volatile.Register32 // 0x4 + CLK_OUT_EN volatile.Register32 // 0x8 + WIFI_BB_CFG volatile.Register32 // 0xC + WIFI_BB_CFG_2 volatile.Register32 // 0x10 + WIFI_CLK_EN volatile.Register32 // 0x14 + WIFI_RST_EN volatile.Register32 // 0x18 + HOST_INF_SEL volatile.Register32 // 0x1C + EXT_MEM_PMS_LOCK volatile.Register32 // 0x20 + _ [4]byte + FLASH_ACE0_ATTR volatile.Register32 // 0x28 + FLASH_ACE1_ATTR volatile.Register32 // 0x2C + FLASH_ACE2_ATTR volatile.Register32 // 0x30 + FLASH_ACE3_ATTR volatile.Register32 // 0x34 + FLASH_ACE0_ADDR volatile.Register32 // 0x38 + FLASH_ACE1_ADDR volatile.Register32 // 0x3C + FLASH_ACE2_ADDR volatile.Register32 // 0x40 + FLASH_ACE3_ADDR volatile.Register32 // 0x44 + FLASH_ACE0_SIZE volatile.Register32 // 0x48 + FLASH_ACE1_SIZE volatile.Register32 // 0x4C + FLASH_ACE2_SIZE volatile.Register32 // 0x50 + FLASH_ACE3_SIZE volatile.Register32 // 0x54 + _ [48]byte + SPI_MEM_PMS_CTRL volatile.Register32 // 0x88 + SPI_MEM_REJECT_ADDR volatile.Register32 // 0x8C + SDIO_CTRL volatile.Register32 // 0x90 + REDCY_SIG0 volatile.Register32 // 0x94 + REDCY_SIG1 volatile.Register32 // 0x98 + FRONT_END_MEM_PD volatile.Register32 // 0x9C + RETENTION_CTRL volatile.Register32 // 0xA0 + CLKGATE_FORCE_ON volatile.Register32 // 0xA4 + MEM_POWER_DOWN volatile.Register32 // 0xA8 + MEM_POWER_UP volatile.Register32 // 0xAC + RND_DATA volatile.Register32 // 0xB0 + PERI_BACKUP_CONFIG volatile.Register32 // 0xB4 + PERI_BACKUP_APB_ADDR volatile.Register32 // 0xB8 + PERI_BACKUP_MEM_ADDR volatile.Register32 // 0xBC + PERI_BACKUP_INT_RAW volatile.Register32 // 0xC0 + PERI_BACKUP_INT_ST volatile.Register32 // 0xC4 + PERI_BACKUP_INT_ENA volatile.Register32 // 0xC8 + _ [4]byte + PERI_BACKUP_INT_CLR volatile.Register32 // 0xD0 + _ [808]byte + DATE volatile.Register32 // 0x3FC +} + +// APB_CTRL.SYSCLK_CONF: APB_CTRL_SYSCLK_CONF_REG +func (o *APB_CTRL_Type) SetSYSCLK_CONF_PRE_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x3ff)|value) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_PRE_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x3ff +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_CLK_320M_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_CLK_320M_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x400) >> 10 +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x800)|value<<11) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x800) >> 11 +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_RST_TICK_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_RST_TICK_CNT() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x1000) >> 12 +} + +// APB_CTRL.TICK_CONF: APB_CTRL_TICK_CONF_REG +func (o *APB_CTRL_Type) SetTICK_CONF_XTAL_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetTICK_CONF_XTAL_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.TICK_CONF.Reg) & 0xff +} +func (o *APB_CTRL_Type) SetTICK_CONF_CK8M_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *APB_CTRL_Type) GetTICK_CONF_CK8M_TICK_NUM() uint32 { + return (volatile.LoadUint32(&o.TICK_CONF.Reg) & 0xff00) >> 8 +} +func (o *APB_CTRL_Type) SetTICK_CONF_TICK_ENABLE(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *APB_CTRL_Type) GetTICK_CONF_TICK_ENABLE() uint32 { + return (volatile.LoadUint32(&o.TICK_CONF.Reg) & 0x10000) >> 16 +} + +// APB_CTRL.CLK_OUT_EN: APB_CTRL_CLK_OUT_EN_REG +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK20_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK20_OEN() uint32 { + return volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK22_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK22_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK44_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x4)|value<<2) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK44_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x4) >> 2 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x8)|value<<3) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x8) >> 3 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK80_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x10)|value<<4) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK80_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x10) >> 4 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK160_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x20)|value<<5) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK160_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x20) >> 5 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_320M_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x40)|value<<6) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_320M_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x40) >> 6 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_ADC_INF_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x80)|value<<7) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_ADC_INF_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x80) >> 7 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_DAC_CPU_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x100)|value<<8) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_DAC_CPU_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x100) >> 8 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK40X_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x200)|value<<9) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK40X_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x200) >> 9 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_XTAL_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x400)|value<<10) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_XTAL_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x400) >> 10 +} + +// APB_CTRL.WIFI_BB_CFG: APB_CTRL_WIFI_BB_CFG_REG +func (o *APB_CTRL_Type) SetWIFI_BB_CFG(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_BB_CFG() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG.Reg) +} + +// APB_CTRL.WIFI_BB_CFG_2: APB_CTRL_WIFI_BB_CFG_2_REG +func (o *APB_CTRL_Type) SetWIFI_BB_CFG_2(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG_2.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_BB_CFG_2() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG_2.Reg) +} + +// APB_CTRL.WIFI_CLK_EN: APB_CTRL_WIFI_CLK_EN_REG +func (o *APB_CTRL_Type) SetWIFI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_CLK_EN.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_CLK_EN.Reg) +} + +// APB_CTRL.WIFI_RST_EN: APB_CTRL_WIFI_RST_EN_REG +func (o *APB_CTRL_Type) SetWIFI_RST_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_RST_EN.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_RST_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_RST_EN.Reg) +} + +// APB_CTRL.HOST_INF_SEL: APB_CTRL_HOST_INF_SEL_REG +func (o *APB_CTRL_Type) SetHOST_INF_SEL_PERI_IO_SWAP(value uint32) { + volatile.StoreUint32(&o.HOST_INF_SEL.Reg, volatile.LoadUint32(&o.HOST_INF_SEL.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetHOST_INF_SEL_PERI_IO_SWAP() uint32 { + return volatile.LoadUint32(&o.HOST_INF_SEL.Reg) & 0xff +} + +// APB_CTRL.EXT_MEM_PMS_LOCK: APB_CTRL_EXT_MEM_PMS_LOCK_REG +func (o *APB_CTRL_Type) SetEXT_MEM_PMS_LOCK(value uint32) { + volatile.StoreUint32(&o.EXT_MEM_PMS_LOCK.Reg, volatile.LoadUint32(&o.EXT_MEM_PMS_LOCK.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetEXT_MEM_PMS_LOCK() uint32 { + return volatile.LoadUint32(&o.EXT_MEM_PMS_LOCK.Reg) & 0x1 +} + +// APB_CTRL.FLASH_ACE0_ATTR: APB_CTRL_FLASH_ACE0_ATTR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE0_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE0_ATTR.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE0_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_ATTR.Reg) & 0x3 +} + +// APB_CTRL.FLASH_ACE1_ATTR: APB_CTRL_FLASH_ACE1_ATTR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE1_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE1_ATTR.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE1_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_ATTR.Reg) & 0x3 +} + +// APB_CTRL.FLASH_ACE2_ATTR: APB_CTRL_FLASH_ACE2_ATTR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE2_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE2_ATTR.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE2_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_ATTR.Reg) & 0x3 +} + +// APB_CTRL.FLASH_ACE3_ATTR: APB_CTRL_FLASH_ACE3_ATTR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE3_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE3_ATTR.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE3_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_ATTR.Reg) & 0x3 +} + +// APB_CTRL.FLASH_ACE0_ADDR: APB_CTRL_FLASH_ACE0_ADDR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE0_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE0_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE1_ADDR: APB_CTRL_FLASH_ACE1_ADDR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE1_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE1_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE2_ADDR: APB_CTRL_FLASH_ACE2_ADDR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE2_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE2_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE3_ADDR: APB_CTRL_FLASH_ACE3_ADDR_REG +func (o *APB_CTRL_Type) SetFLASH_ACE3_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE3_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE0_SIZE: APB_CTRL_FLASH_ACE0_SIZE_REG +func (o *APB_CTRL_Type) SetFLASH_ACE0_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE0_SIZE.Reg)&^(0x1fff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE0_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_SIZE.Reg) & 0x1fff +} + +// APB_CTRL.FLASH_ACE1_SIZE: APB_CTRL_FLASH_ACE1_SIZE_REG +func (o *APB_CTRL_Type) SetFLASH_ACE1_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE1_SIZE.Reg)&^(0x1fff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE1_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_SIZE.Reg) & 0x1fff +} + +// APB_CTRL.FLASH_ACE2_SIZE: APB_CTRL_FLASH_ACE2_SIZE_REG +func (o *APB_CTRL_Type) SetFLASH_ACE2_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE2_SIZE.Reg)&^(0x1fff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE2_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_SIZE.Reg) & 0x1fff +} + +// APB_CTRL.FLASH_ACE3_SIZE: APB_CTRL_FLASH_ACE3_SIZE_REG +func (o *APB_CTRL_Type) SetFLASH_ACE3_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE3_SIZE.Reg)&^(0x1fff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE3_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_SIZE.Reg) & 0x1fff +} + +// APB_CTRL.SPI_MEM_PMS_CTRL: APB_CTRL_SPI_MEM_PMS_CTRL_REG +func (o *APB_CTRL_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x7c)|value<<2) +} +func (o *APB_CTRL_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x7c) >> 2 +} + +// APB_CTRL.SPI_MEM_REJECT_ADDR: APB_CTRL_SPI_MEM_REJECT_ADDR_REG +func (o *APB_CTRL_Type) SetSPI_MEM_REJECT_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REJECT_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetSPI_MEM_REJECT_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REJECT_ADDR.Reg) +} + +// APB_CTRL.SDIO_CTRL: APB_CTRL_SDIO_CTRL_REG +func (o *APB_CTRL_Type) SetSDIO_CTRL_SDIO_WIN_ACCESS_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_CTRL.Reg, volatile.LoadUint32(&o.SDIO_CTRL.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetSDIO_CTRL_SDIO_WIN_ACCESS_EN() uint32 { + return volatile.LoadUint32(&o.SDIO_CTRL.Reg) & 0x1 +} + +// APB_CTRL.REDCY_SIG0: APB_CTRL_REDCY_SIG0_REG_REG +func (o *APB_CTRL_Type) SetREDCY_SIG0(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG0.Reg, volatile.LoadUint32(&o.REDCY_SIG0.Reg)&^(0x7fffffff)|value) +} +func (o *APB_CTRL_Type) GetREDCY_SIG0() uint32 { + return volatile.LoadUint32(&o.REDCY_SIG0.Reg) & 0x7fffffff +} +func (o *APB_CTRL_Type) SetREDCY_SIG0_REDCY_ANDOR(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG0.Reg, volatile.LoadUint32(&o.REDCY_SIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetREDCY_SIG0_REDCY_ANDOR() uint32 { + return (volatile.LoadUint32(&o.REDCY_SIG0.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.REDCY_SIG1: APB_CTRL_REDCY_SIG1_REG_REG +func (o *APB_CTRL_Type) SetREDCY_SIG1(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG1.Reg, volatile.LoadUint32(&o.REDCY_SIG1.Reg)&^(0x7fffffff)|value) +} +func (o *APB_CTRL_Type) GetREDCY_SIG1() uint32 { + return volatile.LoadUint32(&o.REDCY_SIG1.Reg) & 0x7fffffff +} +func (o *APB_CTRL_Type) SetREDCY_SIG1_REDCY_NANDOR(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG1.Reg, volatile.LoadUint32(&o.REDCY_SIG1.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetREDCY_SIG1_REDCY_NANDOR() uint32 { + return (volatile.LoadUint32(&o.REDCY_SIG1.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.FRONT_END_MEM_PD: APB_CTRL_FRONT_END_MEM_PD_REG +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU() uint32 { + return volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x4)|value<<2) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x4) >> 2 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x8)|value<<3) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x8) >> 3 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_DC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x10)|value<<4) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_DC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x10) >> 4 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_DC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x20)|value<<5) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_DC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x20) >> 5 +} + +// APB_CTRL.RETENTION_CTRL: APB_CTRL_RETENTION_CTRL_REG +func (o *APB_CTRL_Type) SetRETENTION_CTRL_RETENTION_LINK_ADDR(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x7ffffff)|value) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL_RETENTION_LINK_ADDR() uint32 { + return volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x7ffffff +} +func (o *APB_CTRL_Type) SetRETENTION_CTRL_NOBYPASS_CPU_ISO_RST(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL_NOBYPASS_CPU_ISO_RST() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x8000000) >> 27 +} + +// APB_CTRL.CLKGATE_FORCE_ON: APB_CTRL_CLKGATE_FORCE_ON_REG +func (o *APB_CTRL_Type) SetCLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLKGATE_FORCE_ON.Reg, volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetCLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg) & 0x3 +} +func (o *APB_CTRL_Type) SetCLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLKGATE_FORCE_ON.Reg, volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg)&^(0x3c)|value<<2) +} +func (o *APB_CTRL_Type) GetCLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg) & 0x3c) >> 2 +} + +// APB_CTRL.MEM_POWER_DOWN: APB_CTRL_MEM_POWER_DOWN_REG +func (o *APB_CTRL_Type) SetMEM_POWER_DOWN_ROM_POWER_DOWN(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_DOWN.Reg, volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetMEM_POWER_DOWN_ROM_POWER_DOWN() uint32 { + return volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg) & 0x3 +} +func (o *APB_CTRL_Type) SetMEM_POWER_DOWN_SRAM_POWER_DOWN(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_DOWN.Reg, volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg)&^(0x3c)|value<<2) +} +func (o *APB_CTRL_Type) GetMEM_POWER_DOWN_SRAM_POWER_DOWN() uint32 { + return (volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg) & 0x3c) >> 2 +} + +// APB_CTRL.MEM_POWER_UP: APB_CTRL_MEM_POWER_UP_REG +func (o *APB_CTRL_Type) SetMEM_POWER_UP_ROM_POWER_UP(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_UP.Reg, volatile.LoadUint32(&o.MEM_POWER_UP.Reg)&^(0x3)|value) +} +func (o *APB_CTRL_Type) GetMEM_POWER_UP_ROM_POWER_UP() uint32 { + return volatile.LoadUint32(&o.MEM_POWER_UP.Reg) & 0x3 +} +func (o *APB_CTRL_Type) SetMEM_POWER_UP_SRAM_POWER_UP(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_UP.Reg, volatile.LoadUint32(&o.MEM_POWER_UP.Reg)&^(0x3c)|value<<2) +} +func (o *APB_CTRL_Type) GetMEM_POWER_UP_SRAM_POWER_UP() uint32 { + return (volatile.LoadUint32(&o.MEM_POWER_UP.Reg) & 0x3c) >> 2 +} + +// APB_CTRL.RND_DATA: APB_CTRL_RND_DATA_REG +func (o *APB_CTRL_Type) SetRND_DATA(value uint32) { + volatile.StoreUint32(&o.RND_DATA.Reg, value) +} +func (o *APB_CTRL_Type) GetRND_DATA() uint32 { + return volatile.LoadUint32(&o.RND_DATA.Reg) +} + +// APB_CTRL.PERI_BACKUP_CONFIG: APB_CTRL_PERI_BACKUP_CONFIG_REG_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_FLOW_ERR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x6)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_FLOW_ERR() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x6) >> 1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_BURST_LIMIT(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x1f0)|value<<4) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_BURST_LIMIT() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x1f0) >> 4 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_TOUT_THRES(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x7fe00)|value<<9) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_TOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x7fe00) >> 9 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_SIZE(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x1ff80000)|value<<19) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_SIZE() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x1ff80000) >> 19 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_START(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_START() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_CONFIG_PERI_BACKUP_ENA(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_CONFIG.Reg, volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_CONFIG_PERI_BACKUP_ENA() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_CONFIG.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.PERI_BACKUP_APB_ADDR: APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_APB_ADDR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_APB_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_APB_ADDR() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_APB_ADDR.Reg) +} + +// APB_CTRL.PERI_BACKUP_MEM_ADDR: APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_MEM_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_MEM_ADDR() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_MEM_ADDR.Reg) +} + +// APB_CTRL.PERI_BACKUP_INT_RAW: APB_CTRL_PERI_BACKUP_INT_RAW_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_RAW.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_RAW.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_RAW.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_RAW.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_INT_RAW.Reg) & 0x2) >> 1 +} + +// APB_CTRL.PERI_BACKUP_INT_ST: APB_CTRL_PERI_BACKUP_INT_ST_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_ST.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_ST.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_ST.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_ST.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_INT_ST.Reg) & 0x2) >> 1 +} + +// APB_CTRL.PERI_BACKUP_INT_ENA: APB_CTRL_PERI_BACKUP_INT_ENA_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_ENA.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_ENA.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_ENA.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_ENA.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_INT_ENA.Reg) & 0x2) >> 1 +} + +// APB_CTRL.PERI_BACKUP_INT_CLR: APB_CTRL_PERI_BACKUP_INT_CLR_REG +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_CLR.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_CLR.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_CLR.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetPERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_CLR.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetPERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.PERI_BACKUP_INT_CLR.Reg) & 0x2) >> 1 +} + +// APB_CTRL.DATE: APB_CTRL_DATE_REG +func (o *APB_CTRL_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *APB_CTRL_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// SAR (Successive Approximation Register) Analog-to-Digital Converter +type APB_SARADC_Type struct { + CTRL volatile.Register32 // 0x0 + CTRL2 volatile.Register32 // 0x4 + FILTER_CTRL1 volatile.Register32 // 0x8 + FSM_WAIT volatile.Register32 // 0xC + SAR1_STATUS volatile.Register32 // 0x10 + SAR2_STATUS volatile.Register32 // 0x14 + SAR_PATT_TAB1 volatile.Register32 // 0x18 + SAR_PATT_TAB2 volatile.Register32 // 0x1C + ONETIME_SAMPLE volatile.Register32 // 0x20 + ARB_CTRL volatile.Register32 // 0x24 + FILTER_CTRL0 volatile.Register32 // 0x28 + SAR1DATA_STATUS volatile.Register32 // 0x2C + SAR2DATA_STATUS volatile.Register32 // 0x30 + THRES0_CTRL volatile.Register32 // 0x34 + THRES1_CTRL volatile.Register32 // 0x38 + THRES_CTRL volatile.Register32 // 0x3C + INT_ENA volatile.Register32 // 0x40 + INT_RAW volatile.Register32 // 0x44 + INT_ST volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + DMA_CONF volatile.Register32 // 0x50 + CLKM_CONF volatile.Register32 // 0x54 + APB_TSENS_CTRL volatile.Register32 // 0x58 + TSENS_CTRL2 volatile.Register32 // 0x5C + CALI volatile.Register32 // 0x60 + _ [920]byte + CTRL_DATE volatile.Register32 // 0x3FC +} + +// APB_SARADC.CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetCTRL_SARADC_START_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START_FORCE() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x7f80)|value<<7) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x7f80) >> 7 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x38000)|value<<15) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x38000) >> 15 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_XPD_SAR_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x18000000)|value<<27) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_XPD_SAR_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x18000000) >> 27 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc0000000) >> 30 +} + +// APB_SARADC.CTRL2: digital saradc configure register +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MEAS_NUM_LIMIT(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MEAS_NUM_LIMIT() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MAX_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1fe)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MAX_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1fe) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR1_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR1_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x200) >> 9 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR2_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR2_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x400) >> 10 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff000)|value<<12) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_TARGET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff000) >> 12 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1000000) >> 24 +} + +// APB_SARADC.FILTER_CTRL1: digital saradc configure register +func (o *APB_SARADC_Type) SetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0x1c000000)|value<<26) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0x1c000000) >> 26 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0xe0000000)|value<<29) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0xe0000000) >> 29 +} + +// APB_SARADC.FSM_WAIT: digital saradc configure register +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff00)|value<<8) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff00) >> 8 +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff0000)|value<<16) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff0000) >> 16 +} + +// APB_SARADC.SAR1_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR1_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR1_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR1_STATUS.Reg) +} + +// APB_SARADC.SAR2_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR2_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR2_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR2_STATUS.Reg) +} + +// APB_SARADC.SAR_PATT_TAB1: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR_PATT_TAB1_SARADC_SAR_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR_PATT_TAB1.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR_PATT_TAB1_SARADC_SAR_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR_PATT_TAB1.Reg) & 0xffffff +} + +// APB_SARADC.SAR_PATT_TAB2: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR_PATT_TAB2_SARADC_SAR_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR_PATT_TAB2.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR_PATT_TAB2_SARADC_SAR_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR_PATT_TAB2.Reg) & 0xffffff +} + +// APB_SARADC.ONETIME_SAMPLE: digital saradc configure register +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_ATTEN(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x1800000)|value<<23) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_ATTEN() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x1800000) >> 23 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x1e000000)|value<<25) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x1e000000) >> 25 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_START(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_START() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.ARB_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x4) >> 2 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x8) >> 3 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x10) >> 4 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_GRANT_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_GRANT_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x20) >> 5 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc0)|value<<6) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc0) >> 6 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x300)|value<<8) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x300) >> 8 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc00)|value<<10) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc00) >> 10 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_FIX_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_FIX_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x1000) >> 12 +} + +// APB_SARADC.FILTER_CTRL0: digital saradc configure register +func (o *APB_SARADC_Type) SetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x3c0000)|value<<18) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x3c0000) >> 18 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x3c00000) >> 22 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_APB_SARADC_FILTER_RESET(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_APB_SARADC_FILTER_RESET() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.SAR1DATA_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR1DATA_STATUS_APB_SARADC1_DATA(value uint32) { + volatile.StoreUint32(&o.SAR1DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR1DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetSAR1DATA_STATUS_APB_SARADC1_DATA() uint32 { + return volatile.LoadUint32(&o.SAR1DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.SAR2DATA_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR2DATA_STATUS_APB_SARADC2_DATA(value uint32) { + volatile.StoreUint32(&o.SAR2DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR2DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetSAR2DATA_STATUS_APB_SARADC2_DATA() uint32 { + return volatile.LoadUint32(&o.SAR2DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.THRES0_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetTHRES0_CTRL_APB_SARADC_THRES0_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0xf)|value) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_APB_SARADC_THRES0_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0xf +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_APB_SARADC_THRES0_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_APB_SARADC_THRES0_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_APB_SARADC_THRES0_LOW(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_APB_SARADC_THRES0_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES1_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetTHRES1_CTRL_APB_SARADC_THRES1_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0xf)|value) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_APB_SARADC_THRES1_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0xf +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_APB_SARADC_THRES1_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_APB_SARADC_THRES1_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_APB_SARADC_THRES1_LOW(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_APB_SARADC_THRES1_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetTHRES_CTRL_APB_SARADC_THRES_ALL_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_APB_SARADC_THRES_ALL_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_APB_SARADC_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_APB_SARADC_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_APB_SARADC_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_APB_SARADC_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ENA: digital saradc int register +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES1_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES1_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES0_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES0_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC2_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC2_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC1_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC1_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_RAW: digital saradc int register +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES1_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES1_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES0_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES0_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC2_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC2_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC1_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC1_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ST: digital saradc int register +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES1_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES1_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES0_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES0_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES1_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES1_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES0_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES0_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC2_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC2_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC1_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC1_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_CLR: digital saradc int register +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES1_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES1_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES0_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES0_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC2_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC2_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC1_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC1_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.DMA_CONF: digital saradc configure register +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0xffff)|value) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0xffff +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_RESET_FSM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_RESET_FSM() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_TRANS(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_TRANS() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.CLKM_CONF: digital saradc configure register +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x3f00) >> 8 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xfc000) >> 14 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x100000) >> 20 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x600000)|value<<21) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x600000) >> 21 +} + +// APB_SARADC.APB_TSENS_CTRL: digital tsens configure register +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_OUT(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_OUT() uint32 { + return volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_IN_INV(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_IN_INV() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x2000) >> 13 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_PU(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_PU() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x400000) >> 22 +} + +// APB_SARADC.TSENS_CTRL2: digital tsens configure register +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0xfff)|value) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0xfff +} +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0x3000)|value<<12) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0x3000) >> 12 +} +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_CLK_INV(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0x8000)|value<<15) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0x8000) >> 15 +} + +// APB_SARADC.CALI: digital saradc configure register +func (o *APB_SARADC_Type) SetCALI_APB_SARADC_CALI_CFG(value uint32) { + volatile.StoreUint32(&o.CALI.Reg, volatile.LoadUint32(&o.CALI.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetCALI_APB_SARADC_CALI_CFG() uint32 { + return volatile.LoadUint32(&o.CALI.Reg) & 0x1ffff +} + +// APB_SARADC.CTRL_DATE: version +func (o *APB_SARADC_Type) SetCTRL_DATE(value uint32) { + volatile.StoreUint32(&o.CTRL_DATE.Reg, value) +} +func (o *APB_SARADC_Type) GetCTRL_DATE() uint32 { + return volatile.LoadUint32(&o.CTRL_DATE.Reg) +} + +// Debug Assist +type ASSIST_DEBUG_Type struct { + CORE_0_MONTR_ENA volatile.Register32 // 0x0 + CORE_0_INTR_RAW volatile.Register32 // 0x4 + CORE_0_INTR_ENA volatile.Register32 // 0x8 + CORE_0_INTR_CLR volatile.Register32 // 0xC + CORE_0_AREA_DRAM0_0_MIN volatile.Register32 // 0x10 + CORE_0_AREA_DRAM0_0_MAX volatile.Register32 // 0x14 + CORE_0_AREA_DRAM0_1_MIN volatile.Register32 // 0x18 + CORE_0_AREA_DRAM0_1_MAX volatile.Register32 // 0x1C + CORE_0_AREA_PIF_0_MIN volatile.Register32 // 0x20 + CORE_0_AREA_PIF_0_MAX volatile.Register32 // 0x24 + CORE_0_AREA_PIF_1_MIN volatile.Register32 // 0x28 + CORE_0_AREA_PIF_1_MAX volatile.Register32 // 0x2C + CORE_0_AREA_PC volatile.Register32 // 0x30 + CORE_0_AREA_SP volatile.Register32 // 0x34 + CORE_0_SP_MIN volatile.Register32 // 0x38 + CORE_0_SP_MAX volatile.Register32 // 0x3C + CORE_0_SP_PC volatile.Register32 // 0x40 + CORE_0_RCD_EN volatile.Register32 // 0x44 + CORE_0_RCD_PDEBUGPC volatile.Register32 // 0x48 + CORE_0_RCD_PDEBUGSP volatile.Register32 // 0x4C + CORE_0_IRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x50 + CORE_0_IRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x54 + CORE_0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x58 + CORE_0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x5C + CORE_0_DRAM0_EXCEPTION_MONITOR_2 volatile.Register32 // 0x60 + CORE_0_DRAM0_EXCEPTION_MONITOR_3 volatile.Register32 // 0x64 + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x68 + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x6C + LOG_SETTING volatile.Register32 // 0x70 + LOG_DATA_0 volatile.Register32 // 0x74 + LOG_DATA_MASK volatile.Register32 // 0x78 + LOG_MIN volatile.Register32 // 0x7C + LOG_MAX volatile.Register32 // 0x80 + LOG_MEM_START volatile.Register32 // 0x84 + LOG_MEM_END volatile.Register32 // 0x88 + LOG_MEM_WRITING_ADDR volatile.Register32 // 0x8C + LOG_MEM_FULL_FLAG volatile.Register32 // 0x90 + C0RE_0_LASTPC_BEFORE_EXCEPTION volatile.Register32 // 0x94 + C0RE_0_DEBUG_MODE volatile.Register32 // 0x98 + _ [352]byte + DATE volatile.Register32 // 0x1FC +} + +// ASSIST_DEBUG.CORE_0_MONTR_ENA: ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_RAW: ASSIST_DEBUG_CORE_0_INTR_RAW_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_ENA: ASSIST_DEBUG_CORE_0_INTR_ENA_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_CLR: ASSIST_DEBUG_CORE_0_INTR_CLR_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MIN: ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MAX: ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MIN: ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MAX: ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MIN: ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MAX: ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MIN: ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MAX: ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PC: ASSIST_DEBUG_CORE_0_AREA_PC_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PC.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_SP: ASSIST_DEBUG_CORE_0_AREA_SP_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_SP(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_SP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_SP() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_SP.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_MIN: ASSIST_DEBUG_CORE_0_SP_MIN_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_MAX: ASSIST_DEBUG_CORE_0_SP_MAX_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_PC: ASSIST_DEBUG_CORE_0_SP_PC_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_PC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_EN: ASSIST_DEBUG_CORE_0_RCD_EN_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGPC: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGPC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGPC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGSP: ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGSP(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGSP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGSP() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGSP.Reg) +} + +// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_0: ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_1: ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_0: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1e000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1e000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_1: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg) +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_2: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)&^(0x1e000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) & 0x1e000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_3: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_3() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg) +} + +// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG +func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xfffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0xfffff +} + +// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG +func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xfffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xfffff +} + +// ASSIST_DEBUG.LOG_SETTING: ASSIST_DEBUG_LOG_SETTING +func (o *ASSIST_DEBUG_Type) SetLOG_SETTING_LOG_ENA(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x7)|value) +} +func (o *ASSIST_DEBUG_Type) GetLOG_SETTING_LOG_ENA() uint32 { + return volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x7 +} +func (o *ASSIST_DEBUG_Type) SetLOG_SETTING_LOG_MODE(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x78)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetLOG_SETTING_LOG_MODE() uint32 { + return (volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x78) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetLOG_SETTING_LOG_MEM_LOOP_ENABLE(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetLOG_SETTING_LOG_MEM_LOOP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x80) >> 7 +} + +// ASSIST_DEBUG.LOG_DATA_0: ASSIST_DEBUG_LOG_DATA_0_REG +func (o *ASSIST_DEBUG_Type) SetLOG_DATA_0(value uint32) { + volatile.StoreUint32(&o.LOG_DATA_0.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetLOG_DATA_0() uint32 { + return volatile.LoadUint32(&o.LOG_DATA_0.Reg) +} + +// ASSIST_DEBUG.LOG_DATA_MASK: ASSIST_DEBUG_LOG_DATA_MASK_REG +func (o *ASSIST_DEBUG_Type) SetLOG_DATA_MASK_LOG_DATA_SIZE(value uint32) { + volatile.StoreUint32(&o.LOG_DATA_MASK.Reg, volatile.LoadUint32(&o.LOG_DATA_MASK.Reg)&^(0xffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetLOG_DATA_MASK_LOG_DATA_SIZE() uint32 { + return volatile.LoadUint32(&o.LOG_DATA_MASK.Reg) & 0xffff +} + +// ASSIST_DEBUG.LOG_MIN: ASSIST_DEBUG_LOG_MIN_REG +func (o *ASSIST_DEBUG_Type) SetLOG_MIN(value uint32) { + volatile.StoreUint32(&o.LOG_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetLOG_MIN() uint32 { + return volatile.LoadUint32(&o.LOG_MIN.Reg) +} + +// ASSIST_DEBUG.LOG_MAX: ASSIST_DEBUG_LOG_MAX_REG +func (o *ASSIST_DEBUG_Type) SetLOG_MAX(value uint32) { + volatile.StoreUint32(&o.LOG_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetLOG_MAX() uint32 { + return volatile.LoadUint32(&o.LOG_MAX.Reg) +} + +// ASSIST_DEBUG.LOG_MEM_START: ASSIST_DEBUG_LOG_MEM_START_REG +func (o *ASSIST_DEBUG_Type) SetLOG_MEM_START(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_START.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetLOG_MEM_START() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_START.Reg) +} + +// ASSIST_DEBUG.LOG_MEM_END: ASSIST_DEBUG_LOG_MEM_END_REG +func (o *ASSIST_DEBUG_Type) SetLOG_MEM_END(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_END.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetLOG_MEM_END() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_END.Reg) +} + +// ASSIST_DEBUG.LOG_MEM_WRITING_ADDR: ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG +func (o *ASSIST_DEBUG_Type) SetLOG_MEM_WRITING_ADDR(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_WRITING_ADDR.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetLOG_MEM_WRITING_ADDR() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_WRITING_ADDR.Reg) +} + +// ASSIST_DEBUG.LOG_MEM_FULL_FLAG: ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG +func (o *ASSIST_DEBUG_Type) SetLOG_MEM_FULL_FLAG(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_FULL_FLAG.Reg, volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetLOG_MEM_FULL_FLAG() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetLOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_FULL_FLAG.Reg, volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetLOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG() uint32 { + return (volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.C0RE_0_LASTPC_BEFORE_EXCEPTION: ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION +func (o *ASSIST_DEBUG_Type) SetC0RE_0_LASTPC_BEFORE_EXCEPTION(value uint32) { + volatile.StoreUint32(&o.C0RE_0_LASTPC_BEFORE_EXCEPTION.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetC0RE_0_LASTPC_BEFORE_EXCEPTION() uint32 { + return volatile.LoadUint32(&o.C0RE_0_LASTPC_BEFORE_EXCEPTION.Reg) +} + +// ASSIST_DEBUG.C0RE_0_DEBUG_MODE: ASSIST_DEBUG_C0RE_0_DEBUG_MODE +func (o *ASSIST_DEBUG_Type) SetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE(value uint32) { + volatile.StoreUint32(&o.C0RE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE() uint32 { + return volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE(value uint32) { + volatile.StoreUint32(&o.C0RE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.DATE: ASSIST_DEBUG_DATE_REG +func (o *ASSIST_DEBUG_Type) SetDATE_ASSIST_DEBUG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetDATE_ASSIST_DEBUG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// BB Peripheral +type BB_Type struct { + _ [84]byte + BBPD_CTRL volatile.Register32 // 0x54 +} + +// BB.BBPD_CTRL: Baseband control register +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x1)|value) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x1 +} +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x2) >> 1 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x4) >> 2 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x8) >> 3 +} + +// DMA (Direct Memory Access) Controller +type DMA_Type struct { + INT_RAW_CH0 volatile.Register32 // 0x0 + INT_ST_CH0 volatile.Register32 // 0x4 + INT_ENA_CH0 volatile.Register32 // 0x8 + INT_CLR_CH0 volatile.Register32 // 0xC + INT_RAW_CH1 volatile.Register32 // 0x10 + INT_ST_CH1 volatile.Register32 // 0x14 + INT_ENA_CH1 volatile.Register32 // 0x18 + INT_CLR_CH1 volatile.Register32 // 0x1C + INT_RAW_CH2 volatile.Register32 // 0x20 + INT_ST_CH2 volatile.Register32 // 0x24 + INT_ENA_CH2 volatile.Register32 // 0x28 + INT_CLR_CH2 volatile.Register32 // 0x2C + _ [16]byte + AHB_TEST volatile.Register32 // 0x40 + MISC_CONF volatile.Register32 // 0x44 + DATE volatile.Register32 // 0x48 + _ [36]byte + IN_CONF0_CH0 volatile.Register32 // 0x70 + IN_CONF1_CH0 volatile.Register32 // 0x74 + INFIFO_STATUS_CH0 volatile.Register32 // 0x78 + IN_POP_CH0 volatile.Register32 // 0x7C + IN_LINK_CH0 volatile.Register32 // 0x80 + IN_STATE_CH0 volatile.Register32 // 0x84 + IN_SUC_EOF_DES_ADDR_CH0 volatile.Register32 // 0x88 + IN_ERR_EOF_DES_ADDR_CH0 volatile.Register32 // 0x8C + IN_DSCR_CH0 volatile.Register32 // 0x90 + IN_DSCR_BF0_CH0 volatile.Register32 // 0x94 + IN_DSCR_BF1_CH0 volatile.Register32 // 0x98 + IN_PRI_CH0 volatile.Register32 // 0x9C + IN_PERI_SEL_CH0 volatile.Register32 // 0xA0 + _ [44]byte + OUT_CONF0_CH0 volatile.Register32 // 0xD0 + OUT_CONF1_CH0 volatile.Register32 // 0xD4 + OUTFIFO_STATUS_CH0 volatile.Register32 // 0xD8 + OUT_PUSH_CH0 volatile.Register32 // 0xDC + OUT_LINK_CH0 volatile.Register32 // 0xE0 + OUT_STATE_CH0 volatile.Register32 // 0xE4 + OUT_EOF_DES_ADDR_CH0 volatile.Register32 // 0xE8 + OUT_EOF_BFR_DES_ADDR_CH0 volatile.Register32 // 0xEC + OUT_DSCR_CH0 volatile.Register32 // 0xF0 + OUT_DSCR_BF0_CH0 volatile.Register32 // 0xF4 + OUT_DSCR_BF1_CH0 volatile.Register32 // 0xF8 + OUT_PRI_CH0 volatile.Register32 // 0xFC + OUT_PERI_SEL_CH0 volatile.Register32 // 0x100 + _ [44]byte + IN_CONF0_CH1 volatile.Register32 // 0x130 + IN_CONF1_CH1 volatile.Register32 // 0x134 + INFIFO_STATUS_CH1 volatile.Register32 // 0x138 + IN_POP_CH1 volatile.Register32 // 0x13C + IN_LINK_CH1 volatile.Register32 // 0x140 + IN_STATE_CH1 volatile.Register32 // 0x144 + IN_SUC_EOF_DES_ADDR_CH1 volatile.Register32 // 0x148 + IN_ERR_EOF_DES_ADDR_CH1 volatile.Register32 // 0x14C + IN_DSCR_CH1 volatile.Register32 // 0x150 + IN_DSCR_BF0_CH1 volatile.Register32 // 0x154 + IN_DSCR_BF1_CH1 volatile.Register32 // 0x158 + IN_PRI_CH1 volatile.Register32 // 0x15C + IN_PERI_SEL_CH1 volatile.Register32 // 0x160 + _ [44]byte + OUT_CONF0_CH1 volatile.Register32 // 0x190 + OUT_CONF1_CH1 volatile.Register32 // 0x194 + OUTFIFO_STATUS_CH1 volatile.Register32 // 0x198 + OUT_PUSH_CH1 volatile.Register32 // 0x19C + OUT_LINK_CH1 volatile.Register32 // 0x1A0 + OUT_STATE_CH1 volatile.Register32 // 0x1A4 + OUT_EOF_DES_ADDR_CH1 volatile.Register32 // 0x1A8 + OUT_EOF_BFR_DES_ADDR_CH1 volatile.Register32 // 0x1AC + OUT_DSCR_CH1 volatile.Register32 // 0x1B0 + OUT_DSCR_BF0_CH1 volatile.Register32 // 0x1B4 + OUT_DSCR_BF1_CH1 volatile.Register32 // 0x1B8 + OUT_PRI_CH1 volatile.Register32 // 0x1BC + OUT_PERI_SEL_CH1 volatile.Register32 // 0x1C0 + _ [44]byte + IN_CONF0_CH2 volatile.Register32 // 0x1F0 + IN_CONF1_CH2 volatile.Register32 // 0x1F4 + INFIFO_STATUS_CH2 volatile.Register32 // 0x1F8 + IN_POP_CH2 volatile.Register32 // 0x1FC + IN_LINK_CH2 volatile.Register32 // 0x200 + IN_STATE_CH2 volatile.Register32 // 0x204 + IN_SUC_EOF_DES_ADDR_CH2 volatile.Register32 // 0x208 + IN_ERR_EOF_DES_ADDR_CH2 volatile.Register32 // 0x20C + IN_DSCR_CH2 volatile.Register32 // 0x210 + IN_DSCR_BF0_CH2 volatile.Register32 // 0x214 + IN_DSCR_BF1_CH2 volatile.Register32 // 0x218 + IN_PRI_CH2 volatile.Register32 // 0x21C + IN_PERI_SEL_CH2 volatile.Register32 // 0x220 + _ [44]byte + OUT_CONF0_CH2 volatile.Register32 // 0x250 + OUT_CONF1_CH2 volatile.Register32 // 0x254 + OUTFIFO_STATUS_CH2 volatile.Register32 // 0x258 + OUT_PUSH_CH2 volatile.Register32 // 0x25C + OUT_LINK_CH2 volatile.Register32 // 0x260 + OUT_STATE_CH2 volatile.Register32 // 0x264 + OUT_EOF_DES_ADDR_CH2 volatile.Register32 // 0x268 + OUT_EOF_BFR_DES_ADDR_CH2 volatile.Register32 // 0x26C + OUT_DSCR_CH2 volatile.Register32 // 0x270 + OUT_DSCR_BF0_CH2 volatile.Register32 // 0x274 + OUT_DSCR_BF1_CH2 volatile.Register32 // 0x278 + OUT_PRI_CH2 volatile.Register32 // 0x27C + OUT_PERI_SEL_CH2 volatile.Register32 // 0x280 +} + +// DMA.INT_RAW_CH0: DMA_INT_RAW_CH0_REG. +func (o *DMA_Type) SetINT_RAW_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_RAW_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_RAW_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_RAW_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_RAW_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_RAW_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_RAW_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_RAW_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_RAW_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_RAW_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_RAW_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH0.Reg, volatile.LoadUint32(&o.INT_RAW_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_RAW_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INT_ST_CH0: DMA_INT_ST_CH0_REG. +func (o *DMA_Type) SetINT_ST_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_ST_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_ST_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_ST_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_ST_CH0_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_ST_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_ST_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_ST_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_ST_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_ST_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_ST_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_ST_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_ST_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_ST_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_ST_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_ST_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_ST_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_ST_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_ST_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_ST_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_ST_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH0.Reg, volatile.LoadUint32(&o.INT_ST_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_ST_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INT_ENA_CH0: DMA_INT_ENA_CH0_REG. +func (o *DMA_Type) SetINT_ENA_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_ENA_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_ENA_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_ENA_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_ENA_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_ENA_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_ENA_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_ENA_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_ENA_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_ENA_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_ENA_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH0.Reg, volatile.LoadUint32(&o.INT_ENA_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_ENA_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INT_CLR_CH0: DMA_INT_CLR_CH0_REG. +func (o *DMA_Type) SetINT_CLR_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_CLR_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_CLR_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_CLR_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_CLR_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_CLR_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_CLR_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_CLR_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_CLR_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_CLR_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_CLR_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH0.Reg, volatile.LoadUint32(&o.INT_CLR_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_CLR_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INT_RAW_CH1: DMA_INT_RAW_CH1_REG. +func (o *DMA_Type) SetINT_RAW_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_RAW_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_RAW_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_RAW_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_RAW_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_RAW_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_RAW_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_RAW_CH1_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_RAW_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_RAW_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_RAW_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_RAW_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_RAW_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_RAW_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_RAW_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_RAW_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_RAW_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_RAW_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_RAW_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_RAW_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_RAW_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_RAW_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_RAW_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_RAW_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_RAW_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH1.Reg, volatile.LoadUint32(&o.INT_RAW_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_RAW_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.INT_ST_CH1: DMA_INT_ST_CH1_REG. +func (o *DMA_Type) SetINT_ST_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_ST_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_ST_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_ST_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_ST_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_ST_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_ST_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_ST_CH1_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_ST_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_ST_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_ST_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_ST_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_ST_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_ST_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_ST_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_ST_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_ST_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_ST_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_ST_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_ST_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_ST_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_ST_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_ST_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_ST_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_ST_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH1.Reg, volatile.LoadUint32(&o.INT_ST_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_ST_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.INT_ENA_CH1: DMA_INT_ENA_CH1_REG. +func (o *DMA_Type) SetINT_ENA_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_ENA_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_ENA_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_ENA_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_ENA_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_ENA_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_ENA_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_ENA_CH1_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_ENA_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_ENA_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_ENA_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_ENA_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_ENA_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_ENA_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_ENA_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_ENA_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_ENA_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_ENA_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_ENA_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_ENA_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_ENA_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_ENA_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_ENA_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_ENA_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_ENA_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH1.Reg, volatile.LoadUint32(&o.INT_ENA_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_ENA_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.INT_CLR_CH1: DMA_INT_CLR_CH1_REG. +func (o *DMA_Type) SetINT_CLR_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_CLR_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_CLR_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_CLR_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_CLR_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_CLR_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_CLR_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_CLR_CH1_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_CLR_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_CLR_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_CLR_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_CLR_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_CLR_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_CLR_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_CLR_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_CLR_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_CLR_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_CLR_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_CLR_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_CLR_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_CLR_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_CLR_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_CLR_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_CLR_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_CLR_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH1.Reg, volatile.LoadUint32(&o.INT_CLR_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_CLR_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.INT_RAW_CH2: DMA_INT_RAW_CH2_REG. +func (o *DMA_Type) SetINT_RAW_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_RAW_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_RAW_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_RAW_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_RAW_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_RAW_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_RAW_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_RAW_CH2_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_RAW_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_RAW_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_RAW_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_RAW_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_RAW_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_RAW_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_RAW_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_RAW_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_RAW_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_RAW_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_RAW_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_RAW_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_RAW_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_RAW_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_RAW_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_RAW_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_RAW_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_RAW_CH2.Reg, volatile.LoadUint32(&o.INT_RAW_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_RAW_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.INT_ST_CH2: DMA_INT_ST_CH2_REG. +func (o *DMA_Type) SetINT_ST_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_ST_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_ST_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_ST_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_ST_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_ST_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_ST_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_ST_CH2_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_ST_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_ST_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_ST_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_ST_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_ST_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_ST_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_ST_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_ST_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_ST_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_ST_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_ST_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_ST_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_ST_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_ST_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_ST_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_ST_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_ST_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ST_CH2.Reg, volatile.LoadUint32(&o.INT_ST_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_ST_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.INT_ENA_CH2: DMA_INT_ENA_CH2_REG. +func (o *DMA_Type) SetINT_ENA_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_ENA_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_ENA_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_ENA_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_ENA_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_ENA_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_ENA_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_ENA_CH2_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_ENA_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_ENA_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_ENA_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_ENA_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_ENA_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_ENA_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_ENA_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_ENA_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_ENA_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_ENA_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_ENA_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_ENA_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_ENA_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_ENA_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_ENA_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_ENA_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_ENA_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_ENA_CH2.Reg, volatile.LoadUint32(&o.INT_ENA_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_ENA_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.INT_CLR_CH2: DMA_INT_CLR_CH2_REG. +func (o *DMA_Type) SetINT_CLR_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINT_CLR_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetINT_CLR_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINT_CLR_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINT_CLR_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINT_CLR_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINT_CLR_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINT_CLR_CH2_OUT_DONE() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINT_CLR_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINT_CLR_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINT_CLR_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINT_CLR_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINT_CLR_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetINT_CLR_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetINT_CLR_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetINT_CLR_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetINT_CLR_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetINT_CLR_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetINT_CLR_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetINT_CLR_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x200) >> 9 +} +func (o *DMA_Type) SetINT_CLR_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x400)|value<<10) +} +func (o *DMA_Type) GetINT_CLR_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x400) >> 10 +} +func (o *DMA_Type) SetINT_CLR_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x800)|value<<11) +} +func (o *DMA_Type) GetINT_CLR_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x800) >> 11 +} +func (o *DMA_Type) SetINT_CLR_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.INT_CLR_CH2.Reg, volatile.LoadUint32(&o.INT_CLR_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetINT_CLR_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.AHB_TEST: DMA_AHB_TEST_REG. +func (o *DMA_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *DMA_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// DMA.MISC_CONF: DMA_MISC_CONF_REG. +func (o *DMA_Type) SetMISC_CONF_AHBM_RST_INTER(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetMISC_CONF_AHBM_RST_INTER() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} +func (o *DMA_Type) SetMISC_CONF_ARB_PRI_DIS(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetMISC_CONF_ARB_PRI_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetMISC_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x8) >> 3 +} + +// DMA.DATE: DMA_DATE_REG. +func (o *DMA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *DMA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// DMA.IN_CONF0_CH0: DMA_IN_CONF0_CH0_REG. +func (o *DMA_Type) SetIN_CONF0_CH0_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH0_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH0_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x10) >> 4 +} + +// DMA.IN_CONF1_CH0: DMA_IN_CONF1_CH0_REG. +func (o *DMA_Type) SetIN_CONF1_CH0_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH0_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH0: DMA_INFIFO_STATUS_CH0_REG. +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH0: DMA_IN_POP_CH0_REG. +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH0: DMA_IN_LINK_CH0_REG. +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH0: DMA_IN_STATE_CH0_REG. +func (o *DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH0: DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH0: DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_DSCR_CH0: DMA_IN_DSCR_CH0_REG. +func (o *DMA_Type) SetIN_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg) +} + +// DMA.IN_DSCR_BF0_CH0: DMA_IN_DSCR_BF0_CH0_REG. +func (o *DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg) +} + +// DMA.IN_DSCR_BF1_CH0: DMA_IN_DSCR_BF1_CH0_REG. +func (o *DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg) +} + +// DMA.IN_PRI_CH0: DMA_IN_PRI_CH0_REG. +func (o *DMA_Type) SetIN_PRI_CH0_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH0_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH0: DMA_IN_PERI_SEL_CH0_REG. +func (o *DMA_Type) SetIN_PERI_SEL_CH0_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH0_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH0: DMA_OUT_CONF0_CH0_REG. +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_CONF1_CH0: DMA_OUT_CONF1_CH0_REG. +func (o *DMA_Type) SetOUT_CONF1_CH0_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH0_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH0: DMA_OUTFIFO_STATUS_CH0_REG. +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH0: DMA_OUT_PUSH_CH0_REG. +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH0: DMA_OUT_LINK_CH0_REG. +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH0: DMA_OUT_STATE_CH0_REG. +func (o *DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH0: DMA_OUT_EOF_DES_ADDR_CH0_REG. +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH0: DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_DSCR_CH0: DMA_OUT_DSCR_CH0_REG. +func (o *DMA_Type) SetOUT_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg) +} + +// DMA.OUT_DSCR_BF0_CH0: DMA_OUT_DSCR_BF0_CH0_REG. +func (o *DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg) +} + +// DMA.OUT_DSCR_BF1_CH0: DMA_OUT_DSCR_BF1_CH0_REG. +func (o *DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg) +} + +// DMA.OUT_PRI_CH0: DMA_OUT_PRI_CH0_REG. +func (o *DMA_Type) SetOUT_PRI_CH0_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH0_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH0: DMA_OUT_PERI_SEL_CH0_REG. +func (o *DMA_Type) SetOUT_PERI_SEL_CH0_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH0_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH1: DMA_IN_CONF0_CH1_REG. +func (o *DMA_Type) SetIN_CONF0_CH1_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH1_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH1_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x10) >> 4 +} + +// DMA.IN_CONF1_CH1: DMA_IN_CONF1_CH1_REG. +func (o *DMA_Type) SetIN_CONF1_CH1_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH1_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH1: DMA_INFIFO_STATUS_CH1_REG. +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH1: DMA_IN_POP_CH1_REG. +func (o *DMA_Type) SetIN_POP_CH1_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH1_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH1_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH1_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH1: DMA_IN_LINK_CH1_REG. +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH1: DMA_IN_STATE_CH1_REG. +func (o *DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH1_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH1_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH1: DMA_IN_SUC_EOF_DES_ADDR_CH1_REG. +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH1: DMA_IN_ERR_EOF_DES_ADDR_CH1_REG. +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.IN_DSCR_CH1: DMA_IN_DSCR_CH1_REG. +func (o *DMA_Type) SetIN_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg) +} + +// DMA.IN_DSCR_BF0_CH1: DMA_IN_DSCR_BF0_CH1_REG. +func (o *DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg) +} + +// DMA.IN_DSCR_BF1_CH1: DMA_IN_DSCR_BF1_CH1_REG. +func (o *DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg) +} + +// DMA.IN_PRI_CH1: DMA_IN_PRI_CH1_REG. +func (o *DMA_Type) SetIN_PRI_CH1_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH1_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH1: DMA_IN_PERI_SEL_CH1_REG. +func (o *DMA_Type) SetIN_PERI_SEL_CH1_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH1_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH1: DMA_OUT_CONF0_CH1_REG. +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_CONF1_CH1: DMA_OUT_CONF1_CH1_REG. +func (o *DMA_Type) SetOUT_CONF1_CH1_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH1_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH1: DMA_OUTFIFO_STATUS_CH1_REG. +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH1: DMA_OUT_PUSH_CH1_REG. +func (o *DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH1: DMA_OUT_LINK_CH1_REG. +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH1: DMA_OUT_STATE_CH1_REG. +func (o *DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH1_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH1: DMA_OUT_EOF_DES_ADDR_CH1_REG. +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH1: DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg) +} + +// DMA.OUT_DSCR_CH1: DMA_OUT_DSCR_CH1_REG. +func (o *DMA_Type) SetOUT_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg) +} + +// DMA.OUT_DSCR_BF0_CH1: DMA_OUT_DSCR_BF0_CH1_REG. +func (o *DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg) +} + +// DMA.OUT_DSCR_BF1_CH1: DMA_OUT_DSCR_BF1_CH1_REG. +func (o *DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg) +} + +// DMA.OUT_PRI_CH1: DMA_OUT_PRI_CH1_REG. +func (o *DMA_Type) SetOUT_PRI_CH1_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH1_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH1: DMA_OUT_PERI_SEL_CH1_REG. +func (o *DMA_Type) SetOUT_PERI_SEL_CH1_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH1_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH2: DMA_IN_CONF0_CH2_REG. +func (o *DMA_Type) SetIN_CONF0_CH2_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH2_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH2_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x10) >> 4 +} + +// DMA.IN_CONF1_CH2: DMA_IN_CONF1_CH2_REG. +func (o *DMA_Type) SetIN_CONF1_CH2_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH2_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH2: DMA_INFIFO_STATUS_CH2_REG. +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH2: DMA_IN_POP_CH2_REG. +func (o *DMA_Type) SetIN_POP_CH2_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH2_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH2_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH2_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH2: DMA_IN_LINK_CH2_REG. +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH2: DMA_IN_STATE_CH2_REG. +func (o *DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH2_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH2_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH2: DMA_IN_SUC_EOF_DES_ADDR_CH2_REG. +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH2: DMA_IN_ERR_EOF_DES_ADDR_CH2_REG. +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.IN_DSCR_CH2: DMA_IN_DSCR_CH2_REG. +func (o *DMA_Type) SetIN_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg) +} + +// DMA.IN_DSCR_BF0_CH2: DMA_IN_DSCR_BF0_CH2_REG. +func (o *DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg) +} + +// DMA.IN_DSCR_BF1_CH2: DMA_IN_DSCR_BF1_CH2_REG. +func (o *DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg) +} + +// DMA.IN_PRI_CH2: DMA_IN_PRI_CH2_REG. +func (o *DMA_Type) SetIN_PRI_CH2_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH2_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH2: DMA_IN_PERI_SEL_CH2_REG. +func (o *DMA_Type) SetIN_PERI_SEL_CH2_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH2_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH2: DMA_OUT_CONF0_CH2_REG. +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x20) >> 5 +} + +// DMA.OUT_CONF1_CH2: DMA_OUT_CONF1_CH2_REG. +func (o *DMA_Type) SetOUT_CONF1_CH2_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH2_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH2: DMA_OUTFIFO_STATUS_CH2_REG. +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH2: DMA_OUT_PUSH_CH2_REG. +func (o *DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH2: DMA_OUT_LINK_CH2_REG. +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH2: DMA_OUT_STATE_CH2_REG. +func (o *DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH2_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH2: DMA_OUT_EOF_DES_ADDR_CH2_REG. +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH2: DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg) +} + +// DMA.OUT_DSCR_CH2: DMA_OUT_DSCR_CH2_REG. +func (o *DMA_Type) SetOUT_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg) +} + +// DMA.OUT_DSCR_BF0_CH2: DMA_OUT_DSCR_BF0_CH2_REG. +func (o *DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg) +} + +// DMA.OUT_DSCR_BF1_CH2: DMA_OUT_DSCR_BF1_CH2_REG. +func (o *DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg) +} + +// DMA.OUT_PRI_CH2: DMA_OUT_PRI_CH2_REG. +func (o *DMA_Type) SetOUT_PRI_CH2_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH2_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH2: DMA_OUT_PERI_SEL_CH2_REG. +func (o *DMA_Type) SetOUT_PERI_SEL_CH2_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH2_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg) & 0x3f +} + +// Digital Signature +type DS_Type struct { + Y_MEM [512]volatile.Register8 // 0x0 + M_MEM [512]volatile.Register8 // 0x200 + RB_MEM [512]volatile.Register8 // 0x400 + BOX_MEM [48]volatile.Register8 // 0x600 + _ [464]byte + X_MEM [512]volatile.Register8 // 0x800 + Z_MEM [512]volatile.Register8 // 0xA00 + _ [512]byte + SET_START volatile.Register32 // 0xE00 + SET_CONTINUE volatile.Register32 // 0xE04 + SET_FINISH volatile.Register32 // 0xE08 + QUERY_BUSY volatile.Register32 // 0xE0C + QUERY_KEY_WRONG volatile.Register32 // 0xE10 + QUERY_CHECK volatile.Register32 // 0xE14 + _ [8]byte + DATE volatile.Register32 // 0xE20 +} + +// DS.SET_START: DS start control register +func (o *DS_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// DS.SET_CONTINUE: DS continue control register +func (o *DS_Type) SetSET_CONTINUE(value uint32) { + volatile.StoreUint32(&o.SET_CONTINUE.Reg, volatile.LoadUint32(&o.SET_CONTINUE.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_CONTINUE() uint32 { + return volatile.LoadUint32(&o.SET_CONTINUE.Reg) & 0x1 +} + +// DS.SET_FINISH: DS finish control register +func (o *DS_Type) SetSET_FINISH(value uint32) { + volatile.StoreUint32(&o.SET_FINISH.Reg, volatile.LoadUint32(&o.SET_FINISH.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_FINISH() uint32 { + return volatile.LoadUint32(&o.SET_FINISH.Reg) & 0x1 +} + +// DS.QUERY_BUSY: DS query busy register +func (o *DS_Type) SetQUERY_BUSY(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_BUSY() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// DS.QUERY_KEY_WRONG: DS query key-wrong counter register +func (o *DS_Type) SetQUERY_KEY_WRONG(value uint32) { + volatile.StoreUint32(&o.QUERY_KEY_WRONG.Reg, volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg)&^(0xf)|value) +} +func (o *DS_Type) GetQUERY_KEY_WRONG() uint32 { + return volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg) & 0xf +} + +// DS.QUERY_CHECK: DS query check result register +func (o *DS_Type) SetQUERY_CHECK_MD_ERROR(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_CHECK_MD_ERROR() uint32 { + return volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x1 +} +func (o *DS_Type) SetQUERY_CHECK_PADDING_BAD(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x2)|value<<1) +} +func (o *DS_Type) GetQUERY_CHECK_PADDING_BAD() uint32 { + return (volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x2) >> 1 +} + +// DS.DATE: DS version control register +func (o *DS_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *DS_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// eFuse Controller +type EFUSE_Type struct { + PGM_DATA0 volatile.Register32 // 0x0 + PGM_DATA1 volatile.Register32 // 0x4 + PGM_DATA2 volatile.Register32 // 0x8 + PGM_DATA3 volatile.Register32 // 0xC + PGM_DATA4 volatile.Register32 // 0x10 + PGM_DATA5 volatile.Register32 // 0x14 + PGM_DATA6 volatile.Register32 // 0x18 + PGM_DATA7 volatile.Register32 // 0x1C + PGM_CHECK_VALUE0 volatile.Register32 // 0x20 + PGM_CHECK_VALUE1 volatile.Register32 // 0x24 + PGM_CHECK_VALUE2 volatile.Register32 // 0x28 + RD_WR_DIS volatile.Register32 // 0x2C + RD_REPEAT_DATA0 volatile.Register32 // 0x30 + RD_REPEAT_DATA1 volatile.Register32 // 0x34 + RD_REPEAT_DATA2 volatile.Register32 // 0x38 + RD_REPEAT_DATA3 volatile.Register32 // 0x3C + RD_REPEAT_DATA4 volatile.Register32 // 0x40 + RD_MAC_SPI_SYS_0 volatile.Register32 // 0x44 + RD_MAC_SPI_SYS_1 volatile.Register32 // 0x48 + RD_MAC_SPI_SYS_2 volatile.Register32 // 0x4C + RD_MAC_SPI_SYS_3 volatile.Register32 // 0x50 + RD_MAC_SPI_SYS_4 volatile.Register32 // 0x54 + RD_MAC_SPI_SYS_5 volatile.Register32 // 0x58 + RD_SYS_PART1_DATA0 volatile.Register32 // 0x5C + RD_SYS_PART1_DATA1 volatile.Register32 // 0x60 + RD_SYS_PART1_DATA2 volatile.Register32 // 0x64 + RD_SYS_PART1_DATA3 volatile.Register32 // 0x68 + RD_SYS_PART1_DATA4 volatile.Register32 // 0x6C + RD_SYS_PART1_DATA5 volatile.Register32 // 0x70 + RD_SYS_PART1_DATA6 volatile.Register32 // 0x74 + RD_SYS_PART1_DATA7 volatile.Register32 // 0x78 + RD_USR_DATA0 volatile.Register32 // 0x7C + RD_USR_DATA1 volatile.Register32 // 0x80 + RD_USR_DATA2 volatile.Register32 // 0x84 + RD_USR_DATA3 volatile.Register32 // 0x88 + RD_USR_DATA4 volatile.Register32 // 0x8C + RD_USR_DATA5 volatile.Register32 // 0x90 + RD_USR_DATA6 volatile.Register32 // 0x94 + RD_USR_DATA7 volatile.Register32 // 0x98 + RD_KEY0_DATA0 volatile.Register32 // 0x9C + RD_KEY0_DATA1 volatile.Register32 // 0xA0 + RD_KEY0_DATA2 volatile.Register32 // 0xA4 + RD_KEY0_DATA3 volatile.Register32 // 0xA8 + RD_KEY0_DATA4 volatile.Register32 // 0xAC + RD_KEY0_DATA5 volatile.Register32 // 0xB0 + RD_KEY0_DATA6 volatile.Register32 // 0xB4 + RD_KEY0_DATA7 volatile.Register32 // 0xB8 + RD_KEY1_DATA0 volatile.Register32 // 0xBC + RD_KEY1_DATA1 volatile.Register32 // 0xC0 + RD_KEY1_DATA2 volatile.Register32 // 0xC4 + RD_KEY1_DATA3 volatile.Register32 // 0xC8 + RD_KEY1_DATA4 volatile.Register32 // 0xCC + RD_KEY1_DATA5 volatile.Register32 // 0xD0 + RD_KEY1_DATA6 volatile.Register32 // 0xD4 + RD_KEY1_DATA7 volatile.Register32 // 0xD8 + RD_KEY2_DATA0 volatile.Register32 // 0xDC + RD_KEY2_DATA1 volatile.Register32 // 0xE0 + RD_KEY2_DATA2 volatile.Register32 // 0xE4 + RD_KEY2_DATA3 volatile.Register32 // 0xE8 + RD_KEY2_DATA4 volatile.Register32 // 0xEC + RD_KEY2_DATA5 volatile.Register32 // 0xF0 + RD_KEY2_DATA6 volatile.Register32 // 0xF4 + RD_KEY2_DATA7 volatile.Register32 // 0xF8 + RD_KEY3_DATA0 volatile.Register32 // 0xFC + RD_KEY3_DATA1 volatile.Register32 // 0x100 + RD_KEY3_DATA2 volatile.Register32 // 0x104 + RD_KEY3_DATA3 volatile.Register32 // 0x108 + RD_KEY3_DATA4 volatile.Register32 // 0x10C + RD_KEY3_DATA5 volatile.Register32 // 0x110 + RD_KEY3_DATA6 volatile.Register32 // 0x114 + RD_KEY3_DATA7 volatile.Register32 // 0x118 + RD_KEY4_DATA0 volatile.Register32 // 0x11C + RD_KEY4_DATA1 volatile.Register32 // 0x120 + RD_KEY4_DATA2 volatile.Register32 // 0x124 + RD_KEY4_DATA3 volatile.Register32 // 0x128 + RD_KEY4_DATA4 volatile.Register32 // 0x12C + RD_KEY4_DATA5 volatile.Register32 // 0x130 + RD_KEY4_DATA6 volatile.Register32 // 0x134 + RD_KEY4_DATA7 volatile.Register32 // 0x138 + RD_KEY5_DATA0 volatile.Register32 // 0x13C + RD_KEY5_DATA1 volatile.Register32 // 0x140 + RD_KEY5_DATA2 volatile.Register32 // 0x144 + RD_KEY5_DATA3 volatile.Register32 // 0x148 + RD_KEY5_DATA4 volatile.Register32 // 0x14C + RD_KEY5_DATA5 volatile.Register32 // 0x150 + RD_KEY5_DATA6 volatile.Register32 // 0x154 + RD_KEY5_DATA7 volatile.Register32 // 0x158 + RD_SYS_PART2_DATA0 volatile.Register32 // 0x15C + RD_SYS_PART2_DATA1 volatile.Register32 // 0x160 + RD_SYS_PART2_DATA2 volatile.Register32 // 0x164 + RD_SYS_PART2_DATA3 volatile.Register32 // 0x168 + RD_SYS_PART2_DATA4 volatile.Register32 // 0x16C + RD_SYS_PART2_DATA5 volatile.Register32 // 0x170 + RD_SYS_PART2_DATA6 volatile.Register32 // 0x174 + RD_SYS_PART2_DATA7 volatile.Register32 // 0x178 + RD_REPEAT_ERR0 volatile.Register32 // 0x17C + RD_REPEAT_ERR1 volatile.Register32 // 0x180 + RD_REPEAT_ERR2 volatile.Register32 // 0x184 + RD_REPEAT_ERR3 volatile.Register32 // 0x188 + _ [4]byte + RD_REPEAT_ERR4 volatile.Register32 // 0x190 + _ [44]byte + RD_RS_ERR0 volatile.Register32 // 0x1C0 + RD_RS_ERR1 volatile.Register32 // 0x1C4 + CLK volatile.Register32 // 0x1C8 + CONF volatile.Register32 // 0x1CC + STATUS volatile.Register32 // 0x1D0 + CMD volatile.Register32 // 0x1D4 + INT_RAW volatile.Register32 // 0x1D8 + INT_ST volatile.Register32 // 0x1DC + INT_ENA volatile.Register32 // 0x1E0 + INT_CLR volatile.Register32 // 0x1E4 + DAC_CONF volatile.Register32 // 0x1E8 + RD_TIM_CONF volatile.Register32 // 0x1EC + WR_TIM_CONF1 volatile.Register32 // 0x1F0 + WR_TIM_CONF2 volatile.Register32 // 0x1F4 + _ [4]byte + DATE volatile.Register32 // 0x1FC +} + +// EFUSE.PGM_DATA0: Register 0 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA0(value uint32) { + volatile.StoreUint32(&o.PGM_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA0() uint32 { + return volatile.LoadUint32(&o.PGM_DATA0.Reg) +} + +// EFUSE.PGM_DATA1: Register 1 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA1(value uint32) { + volatile.StoreUint32(&o.PGM_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA1() uint32 { + return volatile.LoadUint32(&o.PGM_DATA1.Reg) +} + +// EFUSE.PGM_DATA2: Register 2 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA2(value uint32) { + volatile.StoreUint32(&o.PGM_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA2() uint32 { + return volatile.LoadUint32(&o.PGM_DATA2.Reg) +} + +// EFUSE.PGM_DATA3: Register 3 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA3(value uint32) { + volatile.StoreUint32(&o.PGM_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA3() uint32 { + return volatile.LoadUint32(&o.PGM_DATA3.Reg) +} + +// EFUSE.PGM_DATA4: Register 4 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA4(value uint32) { + volatile.StoreUint32(&o.PGM_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA4() uint32 { + return volatile.LoadUint32(&o.PGM_DATA4.Reg) +} + +// EFUSE.PGM_DATA5: Register 5 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA5(value uint32) { + volatile.StoreUint32(&o.PGM_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA5() uint32 { + return volatile.LoadUint32(&o.PGM_DATA5.Reg) +} + +// EFUSE.PGM_DATA6: Register 6 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA6(value uint32) { + volatile.StoreUint32(&o.PGM_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA6() uint32 { + return volatile.LoadUint32(&o.PGM_DATA6.Reg) +} + +// EFUSE.PGM_DATA7: Register 7 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA7(value uint32) { + volatile.StoreUint32(&o.PGM_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA7() uint32 { + return volatile.LoadUint32(&o.PGM_DATA7.Reg) +} + +// EFUSE.PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE0(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE0() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE0.Reg) +} + +// EFUSE.PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE1(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE1() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE1.Reg) +} + +// EFUSE.PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE2(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE2() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE2.Reg) +} + +// EFUSE.RD_WR_DIS: BLOCK0 data register 0. +func (o *EFUSE_Type) SetRD_WR_DIS(value uint32) { + volatile.StoreUint32(&o.RD_WR_DIS.Reg, value) +} +func (o *EFUSE_Type) GetRD_WR_DIS() uint32 { + return volatile.LoadUint32(&o.RD_WR_DIS.Reg) +} + +// EFUSE.RD_REPEAT_DATA0: BLOCK0 data register 1. +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RD_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RD_DIS() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_RTC_RAM_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_RTC_RAM_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_DEVICE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED6(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED6() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_CAN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_CAN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_JTAG_SEL_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_JTAG_SEL_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SOFT_DIS_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SOFT_DIS_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_PAD_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_PAD_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_VDD_SPI_AS_GPIO(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_VDD_SPI_AS_GPIO() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_BTLC_GPIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_BTLC_GPIO_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_POWERGLITCH_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_POWERGLITCH_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_POWER_GLITCH_DSENSE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_POWER_GLITCH_DSENSE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_DATA1: BLOCK0 data register 2. +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_RPT4_RESERVED2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_RPT4_RESERVED2() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_WDT_DELAY_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_WDT_DELAY_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA2: BLOCK0 data register 3. +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_2() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_RPT4_RESERVED3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_RPT4_RESERVED3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_RPT4_RESERVED0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xfc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_RPT4_RESERVED0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xfc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_TPUW(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_TPUW() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA3: BLOCK0 data register 4. +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CHANNEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CHANNEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FLASH_ECC_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FLASH_ECC_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CONTROL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CONTROL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_PIN_POWER_SELECTION(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_PIN_POWER_SELECTION() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FLASH_TYPE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FLASH_TYPE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FLASH_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc00)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FLASH_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc00) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FLASH_ECC_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FLASH_ECC_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FORCE_SEND_RESUME(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FORCE_SEND_RESUME() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_VERSION(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x3fffc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_VERSION() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x3fffc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_DATA4: BLOCK0 data register 5. +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_RPT4_RESERVED4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_RPT4_RESERVED4() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xffffff +} + +// EFUSE.RD_MAC_SPI_SYS_0: BLOCK1 data register 0. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_0.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_0() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_0.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_1: BLOCK1 data register 1. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_1_MAC_1(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_1_MAC_1() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_1_SPI_PAD_CONF_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_1_SPI_PAD_CONF_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.RD_MAC_SPI_SYS_2: BLOCK1 data register 2. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_2(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_2.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_2() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_2.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_3: BLOCK1 data register 3. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_3_SPI_PAD_CONF_2(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg)&^(0x3ffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_3_SPI_PAD_CONF_2() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg) & 0x3ffff +} +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_3_SYS_DATA_PART0_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg)&^(0xfffc0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_3_SYS_DATA_PART0_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg) & 0xfffc0000) >> 18 +} + +// EFUSE.RD_MAC_SPI_SYS_4: BLOCK1 data register 4. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_4(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_4.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_4() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_4.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_5: BLOCK1 data register 5. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_5(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_5.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_5() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA0: Register 0 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA1: Register 1 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA2: Register 2 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA3: Register 3 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA4: Register 4 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA5: Register 5 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA6: Register 6 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA7: Register 7 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA7.Reg) +} + +// EFUSE.RD_USR_DATA0: Register 0 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA0.Reg) +} + +// EFUSE.RD_USR_DATA1: Register 1 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA1.Reg) +} + +// EFUSE.RD_USR_DATA2: Register 2 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA2.Reg) +} + +// EFUSE.RD_USR_DATA3: Register 3 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA3.Reg) +} + +// EFUSE.RD_USR_DATA4: Register 4 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA4.Reg) +} + +// EFUSE.RD_USR_DATA5: Register 5 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA5.Reg) +} + +// EFUSE.RD_USR_DATA6: Register 6 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA6.Reg) +} + +// EFUSE.RD_USR_DATA7: Register 7 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA7.Reg) +} + +// EFUSE.RD_KEY0_DATA0: Register 0 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA0.Reg) +} + +// EFUSE.RD_KEY0_DATA1: Register 1 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA1.Reg) +} + +// EFUSE.RD_KEY0_DATA2: Register 2 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA2.Reg) +} + +// EFUSE.RD_KEY0_DATA3: Register 3 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA3.Reg) +} + +// EFUSE.RD_KEY0_DATA4: Register 4 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA4.Reg) +} + +// EFUSE.RD_KEY0_DATA5: Register 5 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA5.Reg) +} + +// EFUSE.RD_KEY0_DATA6: Register 6 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA6.Reg) +} + +// EFUSE.RD_KEY0_DATA7: Register 7 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA7.Reg) +} + +// EFUSE.RD_KEY1_DATA0: Register 0 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA0.Reg) +} + +// EFUSE.RD_KEY1_DATA1: Register 1 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA1.Reg) +} + +// EFUSE.RD_KEY1_DATA2: Register 2 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA2.Reg) +} + +// EFUSE.RD_KEY1_DATA3: Register 3 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA3.Reg) +} + +// EFUSE.RD_KEY1_DATA4: Register 4 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA4.Reg) +} + +// EFUSE.RD_KEY1_DATA5: Register 5 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA5.Reg) +} + +// EFUSE.RD_KEY1_DATA6: Register 6 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA6.Reg) +} + +// EFUSE.RD_KEY1_DATA7: Register 7 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA7.Reg) +} + +// EFUSE.RD_KEY2_DATA0: Register 0 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA0.Reg) +} + +// EFUSE.RD_KEY2_DATA1: Register 1 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA1.Reg) +} + +// EFUSE.RD_KEY2_DATA2: Register 2 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA2.Reg) +} + +// EFUSE.RD_KEY2_DATA3: Register 3 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA3.Reg) +} + +// EFUSE.RD_KEY2_DATA4: Register 4 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA4.Reg) +} + +// EFUSE.RD_KEY2_DATA5: Register 5 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA5.Reg) +} + +// EFUSE.RD_KEY2_DATA6: Register 6 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA6.Reg) +} + +// EFUSE.RD_KEY2_DATA7: Register 7 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA7.Reg) +} + +// EFUSE.RD_KEY3_DATA0: Register 0 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA0.Reg) +} + +// EFUSE.RD_KEY3_DATA1: Register 1 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA1.Reg) +} + +// EFUSE.RD_KEY3_DATA2: Register 2 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA2.Reg) +} + +// EFUSE.RD_KEY3_DATA3: Register 3 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA3.Reg) +} + +// EFUSE.RD_KEY3_DATA4: Register 4 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA4.Reg) +} + +// EFUSE.RD_KEY3_DATA5: Register 5 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA5.Reg) +} + +// EFUSE.RD_KEY3_DATA6: Register 6 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA6.Reg) +} + +// EFUSE.RD_KEY3_DATA7: Register 7 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA7.Reg) +} + +// EFUSE.RD_KEY4_DATA0: Register 0 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA0.Reg) +} + +// EFUSE.RD_KEY4_DATA1: Register 1 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA1.Reg) +} + +// EFUSE.RD_KEY4_DATA2: Register 2 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA2.Reg) +} + +// EFUSE.RD_KEY4_DATA3: Register 3 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA3.Reg) +} + +// EFUSE.RD_KEY4_DATA4: Register 4 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA4.Reg) +} + +// EFUSE.RD_KEY4_DATA5: Register 5 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA5.Reg) +} + +// EFUSE.RD_KEY4_DATA6: Register 6 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA6.Reg) +} + +// EFUSE.RD_KEY4_DATA7: Register 7 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA7.Reg) +} + +// EFUSE.RD_KEY5_DATA0: Register 0 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA0.Reg) +} + +// EFUSE.RD_KEY5_DATA1: Register 1 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA1.Reg) +} + +// EFUSE.RD_KEY5_DATA2: Register 2 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA2.Reg) +} + +// EFUSE.RD_KEY5_DATA3: Register 3 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA3.Reg) +} + +// EFUSE.RD_KEY5_DATA4: Register 4 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA4.Reg) +} + +// EFUSE.RD_KEY5_DATA5: Register 5 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA5.Reg) +} + +// EFUSE.RD_KEY5_DATA6: Register 6 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA6.Reg) +} + +// EFUSE.RD_KEY5_DATA7: Register 7 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA7.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA0: Register 0 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA1: Register 1 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA2: Register 2 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA3: Register 3 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA4: Register 4 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA5: Register 5 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA6: Register 6 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA7: Register 7 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA7.Reg) +} + +// EFUSE.RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RD_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RD_DIS_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_DEVICE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_DEVICE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED6_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED6_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_CAN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_CAN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_BTLC_GPIO_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_BTLC_GPIO_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_POWERGLITCH_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_POWERGLITCH_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_POWER_GLITCH_DSENSE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_POWER_GLITCH_DSENSE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_RPT4_RESERVED2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_RPT4_RESERVED2_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_RPT4_RESERVED3_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_RPT4_RESERVED3_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_RPT4_RESERVED0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xfc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_RPT4_RESERVED0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xfc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_TPUW_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_TPUW_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FLASH_ECC_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FLASH_ECC_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FLASH_TYPE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FLASH_TYPE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FLASH_PAGE_SIZE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc00)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FLASH_PAGE_SIZE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc00) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FLASH_ECC_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FLASH_ECC_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_VERSION_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x3fffc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_VERSION_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x3fffc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xffffff +} + +// EFUSE.RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700)|value<<8) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700) >> 8 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000)|value<<12) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000) >> 12 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700000)|value<<20) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700000) >> 20 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000000) >> 24 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000000) >> 27 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000000) >> 28 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000000)|value<<31) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000000) >> 31 +} + +// EFUSE.RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x80) >> 7 +} + +// EFUSE.CLK: eFuse clock configuration register. +func (o *EFUSE_Type) SetCLK_EFUSE_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCLK_EFUSE_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCLK_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCLK_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCLK_EFUSE_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetCLK_EFUSE_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x10000) >> 16 +} + +// EFUSE.CONF: eFuse operation mode configuration register. +func (o *EFUSE_Type) SetCONF_OP_CODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetCONF_OP_CODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0xffff +} + +// EFUSE.STATUS: eFuse status register. +func (o *EFUSE_Type) SetSTATUS_STATE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetSTATUS_STATE() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xf +} +func (o *EFUSE_Type) SetSTATUS_OTP_LOAD_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetSTATUS_OTP_LOAD_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_C_SYNC2(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_C_SYNC2() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetSTATUS_OTP_STROBE_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetSTATUS_OTP_STROBE_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetSTATUS_OTP_CSB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetSTATUS_OTP_CSB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetSTATUS_OTP_PGENB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetSTATUS_OTP_PGENB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_IS_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_IS_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetSTATUS_REPEAT_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3fc00)|value<<10) +} +func (o *EFUSE_Type) GetSTATUS_REPEAT_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3fc00) >> 10 +} + +// EFUSE.CMD: eFuse command register. +func (o *EFUSE_Type) SetCMD_READ_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCMD_READ_CMD() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCMD_PGM_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCMD_PGM_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCMD_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3c)|value<<2) +} +func (o *EFUSE_Type) GetCMD_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x3c) >> 2 +} + +// EFUSE.INT_RAW: eFuse raw interrupt register. +func (o *EFUSE_Type) SetINT_RAW_READ_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_RAW_READ_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_RAW_PGM_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_RAW_PGM_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ST: eFuse interrupt status register. +func (o *EFUSE_Type) SetINT_ST_READ_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ST_READ_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ST_PGM_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ST_PGM_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ENA: eFuse interrupt enable register. +func (o *EFUSE_Type) SetINT_ENA_READ_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ENA_READ_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ENA_PGM_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ENA_PGM_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_CLR: eFuse interrupt clear register. +func (o *EFUSE_Type) SetINT_CLR_READ_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_CLR_READ_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_CLR_PGM_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_CLR_PGM_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// EFUSE.DAC_CONF: Controls the eFuse programming voltage. +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.DAC_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_PAD_SEL(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_PAD_SEL() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_NUM(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x1fe00)|value<<9) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_NUM() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x1fe00) >> 9 +} +func (o *EFUSE_Type) SetDAC_CONF_OE_CLR(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EFUSE_Type) GetDAC_CONF_OE_CLR() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x20000) >> 17 +} + +// EFUSE.RD_TIM_CONF: Configures read timing parameters. +func (o *EFUSE_Type) SetRD_TIM_CONF_READ_INIT_NUM(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_READ_INIT_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF1: Configuration register 1 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF1_PWR_ON_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xffff00)|value<<8) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_PWR_ON_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xffff00) >> 8 +} + +// EFUSE.WR_TIM_CONF2: Configuration register 2 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF2_PWR_OFF_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_PWR_OFF_NUM() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff +} + +// EFUSE.DATE: eFuse version register. +func (o *EFUSE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *EFUSE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// External Memory +type EXTMEM_Type struct { + ICACHE_CTRL volatile.Register32 // 0x0 + ICACHE_CTRL1 volatile.Register32 // 0x4 + ICACHE_TAG_POWER_CTRL volatile.Register32 // 0x8 + ICACHE_PRELOCK_CTRL volatile.Register32 // 0xC + ICACHE_PRELOCK_SCT0_ADDR volatile.Register32 // 0x10 + ICACHE_PRELOCK_SCT1_ADDR volatile.Register32 // 0x14 + ICACHE_PRELOCK_SCT_SIZE volatile.Register32 // 0x18 + ICACHE_LOCK_CTRL volatile.Register32 // 0x1C + ICACHE_LOCK_ADDR volatile.Register32 // 0x20 + ICACHE_LOCK_SIZE volatile.Register32 // 0x24 + ICACHE_SYNC_CTRL volatile.Register32 // 0x28 + ICACHE_SYNC_ADDR volatile.Register32 // 0x2C + ICACHE_SYNC_SIZE volatile.Register32 // 0x30 + ICACHE_PRELOAD_CTRL volatile.Register32 // 0x34 + ICACHE_PRELOAD_ADDR volatile.Register32 // 0x38 + ICACHE_PRELOAD_SIZE volatile.Register32 // 0x3C + ICACHE_AUTOLOAD_CTRL volatile.Register32 // 0x40 + ICACHE_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x44 + ICACHE_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x48 + ICACHE_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x4C + ICACHE_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x50 + IBUS_TO_FLASH_START_VADDR volatile.Register32 // 0x54 + IBUS_TO_FLASH_END_VADDR volatile.Register32 // 0x58 + DBUS_TO_FLASH_START_VADDR volatile.Register32 // 0x5C + DBUS_TO_FLASH_END_VADDR volatile.Register32 // 0x60 + CACHE_ACS_CNT_CLR volatile.Register32 // 0x64 + IBUS_ACS_MISS_CNT volatile.Register32 // 0x68 + IBUS_ACS_CNT volatile.Register32 // 0x6C + DBUS_ACS_FLASH_MISS_CNT volatile.Register32 // 0x70 + DBUS_ACS_CNT volatile.Register32 // 0x74 + CACHE_ILG_INT_ENA volatile.Register32 // 0x78 + CACHE_ILG_INT_CLR volatile.Register32 // 0x7C + CACHE_ILG_INT_ST volatile.Register32 // 0x80 + CORE0_ACS_CACHE_INT_ENA volatile.Register32 // 0x84 + CORE0_ACS_CACHE_INT_CLR volatile.Register32 // 0x88 + CORE0_ACS_CACHE_INT_ST volatile.Register32 // 0x8C + CORE0_DBUS_REJECT_ST volatile.Register32 // 0x90 + CORE0_DBUS_REJECT_VADDR volatile.Register32 // 0x94 + CORE0_IBUS_REJECT_ST volatile.Register32 // 0x98 + CORE0_IBUS_REJECT_VADDR volatile.Register32 // 0x9C + CACHE_MMU_FAULT_CONTENT volatile.Register32 // 0xA0 + CACHE_MMU_FAULT_VADDR volatile.Register32 // 0xA4 + CACHE_WRAP_AROUND_CTRL volatile.Register32 // 0xA8 + CACHE_MMU_POWER_CTRL volatile.Register32 // 0xAC + CACHE_STATE volatile.Register32 // 0xB0 + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE volatile.Register32 // 0xB4 + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON volatile.Register32 // 0xB8 + CACHE_PRELOAD_INT_CTRL volatile.Register32 // 0xBC + CACHE_SYNC_INT_CTRL volatile.Register32 // 0xC0 + CACHE_MMU_OWNER volatile.Register32 // 0xC4 + CACHE_CONF_MISC volatile.Register32 // 0xC8 + ICACHE_FREEZE volatile.Register32 // 0xCC + ICACHE_ATOMIC_OPERATE_ENA volatile.Register32 // 0xD0 + CACHE_REQUEST volatile.Register32 // 0xD4 + IBUS_PMS_TBL_LOCK volatile.Register32 // 0xD8 + IBUS_PMS_TBL_BOUNDARY0 volatile.Register32 // 0xDC + IBUS_PMS_TBL_BOUNDARY1 volatile.Register32 // 0xE0 + IBUS_PMS_TBL_BOUNDARY2 volatile.Register32 // 0xE4 + IBUS_PMS_TBL_ATTR volatile.Register32 // 0xE8 + DBUS_PMS_TBL_LOCK volatile.Register32 // 0xEC + DBUS_PMS_TBL_BOUNDARY0 volatile.Register32 // 0xF0 + DBUS_PMS_TBL_BOUNDARY1 volatile.Register32 // 0xF4 + DBUS_PMS_TBL_BOUNDARY2 volatile.Register32 // 0xF8 + DBUS_PMS_TBL_ATTR volatile.Register32 // 0xFC + CLOCK_GATE volatile.Register32 // 0x100 + _ [760]byte + REG_DATE volatile.Register32 // 0x3FC +} + +// EXTMEM.ICACHE_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_CTRL_ICACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_CTRL_ICACHE_ENABLE() uint32 { + return volatile.LoadUint32(&o.ICACHE_CTRL.Reg) & 0x1 +} + +// EXTMEM.ICACHE_CTRL1: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_CTRL1_ICACHE_SHUT_IBUS(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL1.Reg, volatile.LoadUint32(&o.ICACHE_CTRL1.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_CTRL1_ICACHE_SHUT_IBUS() uint32 { + return volatile.LoadUint32(&o.ICACHE_CTRL1.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_CTRL1_ICACHE_SHUT_DBUS(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL1.Reg, volatile.LoadUint32(&o.ICACHE_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_CTRL1_ICACHE_SHUT_DBUS() uint32 { + return (volatile.LoadUint32(&o.ICACHE_CTRL1.Reg) & 0x2) >> 1 +} + +// EXTMEM.ICACHE_TAG_POWER_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_PRELOCK_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOCK_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOCK_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOCK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.ICACHE_PRELOCK_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.ICACHE_PRELOCK_SCT0_ADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT0_ADDR.Reg) +} + +// EXTMEM.ICACHE_PRELOCK_SCT1_ADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT1_ADDR.Reg) +} + +// EXTMEM.ICACHE_PRELOCK_SCT_SIZE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT0_SIZE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.ICACHE_LOCK_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_LOCK_CTRL_ICACHE_LOCK_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_CTRL_ICACHE_LOCK_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA() uint32 { + return (volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_LOCK_CTRL_ICACHE_LOCK_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_CTRL_ICACHE_LOCK_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_LOCK_ADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_LOCK_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_LOCK_ADDR.Reg) +} + +// EXTMEM.ICACHE_LOCK_SIZE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_LOCK_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_LOCK_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_LOCK_SIZE.Reg) & 0xffff +} + +// EXTMEM.ICACHE_SYNC_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_SYNC_CTRL_ICACHE_SYNC_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_CTRL_ICACHE_SYNC_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.ICACHE_SYNC_ADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_SYNC_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_ADDR.Reg) +} + +// EXTMEM.ICACHE_SYNC_SIZE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_SYNC_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_SIZE.Reg)&^(0x7fffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_SIZE.Reg) & 0x7fffff +} + +// EXTMEM.ICACHE_PRELOAD_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_PRELOAD_ADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_ADDR.Reg) +} + +// EXTMEM.ICACHE_PRELOAD_SIZE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_SIZE.Reg) & 0xffff +} + +// EXTMEM.ICACHE_AUTOLOAD_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_RQST(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x60)|value<<5) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_RQST() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x60) >> 5 +} + +// EXTMEM.ICACHE_AUTOLOAD_SCT0_ADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT0_ADDR.Reg) +} + +// EXTMEM.ICACHE_AUTOLOAD_SCT0_SIZE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT0_SIZE.Reg)&^(0x7ffffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT0_SIZE.Reg) & 0x7ffffff +} + +// EXTMEM.ICACHE_AUTOLOAD_SCT1_ADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT1_ADDR.Reg) +} + +// EXTMEM.ICACHE_AUTOLOAD_SCT1_SIZE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT1_SIZE.Reg)&^(0x7ffffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT1_SIZE.Reg) & 0x7ffffff +} + +// EXTMEM.IBUS_TO_FLASH_START_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_TO_FLASH_START_VADDR(value uint32) { + volatile.StoreUint32(&o.IBUS_TO_FLASH_START_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_TO_FLASH_START_VADDR() uint32 { + return volatile.LoadUint32(&o.IBUS_TO_FLASH_START_VADDR.Reg) +} + +// EXTMEM.IBUS_TO_FLASH_END_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_TO_FLASH_END_VADDR(value uint32) { + volatile.StoreUint32(&o.IBUS_TO_FLASH_END_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_TO_FLASH_END_VADDR() uint32 { + return volatile.LoadUint32(&o.IBUS_TO_FLASH_END_VADDR.Reg) +} + +// EXTMEM.DBUS_TO_FLASH_START_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_TO_FLASH_START_VADDR(value uint32) { + volatile.StoreUint32(&o.DBUS_TO_FLASH_START_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_TO_FLASH_START_VADDR() uint32 { + return volatile.LoadUint32(&o.DBUS_TO_FLASH_START_VADDR.Reg) +} + +// EXTMEM.DBUS_TO_FLASH_END_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_TO_FLASH_END_VADDR(value uint32) { + volatile.StoreUint32(&o.DBUS_TO_FLASH_END_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_TO_FLASH_END_VADDR() uint32 { + return volatile.LoadUint32(&o.DBUS_TO_FLASH_END_VADDR.Reg) +} + +// EXTMEM.CACHE_ACS_CNT_CLR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ACS_CNT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR() uint32 { + return volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ACS_CNT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg) & 0x2) >> 1 +} + +// EXTMEM.IBUS_ACS_MISS_CNT: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS_ACS_MISS_CNT.Reg) +} + +// EXTMEM.IBUS_ACS_CNT: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS_ACS_CNT.Reg) +} + +// EXTMEM.DBUS_ACS_FLASH_MISS_CNT: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_ACS_FLASH_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS_ACS_FLASH_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_ACS_FLASH_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS_ACS_FLASH_MISS_CNT.Reg) +} + +// EXTMEM.DBUS_ACS_CNT: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS_ACS_CNT.Reg) +} + +// EXTMEM.CACHE_ILG_INT_ENA: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA() uint32 { + return volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x100) >> 8 +} + +// EXTMEM.CACHE_ILG_INT_CLR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR() uint32 { + return volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x100) >> 8 +} + +// EXTMEM.CACHE_ILG_INT_ST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x400) >> 10 +} + +// EXTMEM.CORE0_ACS_CACHE_INT_ENA: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA() uint32 { + return volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x20) >> 5 +} + +// EXTMEM.CORE0_ACS_CACHE_INT_CLR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR() uint32 { + return volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x20) >> 5 +} + +// EXTMEM.CORE0_ACS_CACHE_INT_ST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST() uint32 { + return volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x20) >> 5 +} + +// EXTMEM.CORE0_DBUS_REJECT_ST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR() uint32 { + return volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg) & 0x8) >> 3 +} + +// EXTMEM.CORE0_DBUS_REJECT_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.CORE0_DBUS_REJECT_VADDR.Reg) +} + +// EXTMEM.CORE0_IBUS_REJECT_ST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR() uint32 { + return volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg) & 0x8) >> 3 +} + +// EXTMEM.CORE0_IBUS_REJECT_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.CORE0_IBUS_REJECT_VADDR.Reg) +} + +// EXTMEM.CACHE_MMU_FAULT_CONTENT: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_MMU_FAULT_CONTENT(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg, volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg)&^(0x3ff)|value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_FAULT_CONTENT() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg) & 0x3ff +} +func (o *EXTMEM_Type) SetCACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg, volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg)&^(0x3c00)|value<<10) +} +func (o *EXTMEM_Type) GetCACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg) & 0x3c00) >> 10 +} + +// EXTMEM.CACHE_MMU_FAULT_VADDR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_MMU_FAULT_VADDR(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_FAULT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_FAULT_VADDR() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_FAULT_VADDR.Reg) +} + +// EXTMEM.CACHE_WRAP_AROUND_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND(value uint32) { + volatile.StoreUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND() uint32 { + return volatile.LoadUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg) & 0x1 +} + +// EXTMEM.CACHE_MMU_POWER_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_STATE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_STATE_ICACHE_STATE(value uint32) { + volatile.StoreUint32(&o.CACHE_STATE.Reg, volatile.LoadUint32(&o.CACHE_STATE.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetCACHE_STATE_ICACHE_STATE() uint32 { + return volatile.LoadUint32(&o.CACHE_STATE.Reg) & 0xfff +} + +// EXTMEM.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg) & 0x2) >> 1 +} + +// EXTMEM.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT() uint32 { + return volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_PRELOAD_INT_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_SYNC_INT_CTRL: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_MMU_OWNER: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_MMU_OWNER(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_OWNER.Reg, volatile.LoadUint32(&o.CACHE_MMU_OWNER.Reg)&^(0xf)|value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_OWNER() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_OWNER.Reg) & 0xf +} + +// EXTMEM.CACHE_CONF_MISC: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT() uint32 { + return volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_TRACE_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_TRACE_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_FREEZE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_FREEZE_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_FREEZE.Reg, volatile.LoadUint32(&o.ICACHE_FREEZE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_FREEZE_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_FREEZE.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.ICACHE_FREEZE.Reg, volatile.LoadUint32(&o.ICACHE_FREEZE.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_FREEZE.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_FREEZE.Reg, volatile.LoadUint32(&o.ICACHE_FREEZE.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_FREEZE.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_ATOMIC_OPERATE_ENA: This description will be updated in the near future. +func (o *EXTMEM_Type) SetICACHE_ATOMIC_OPERATE_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_ATOMIC_OPERATE_ENA.Reg, volatile.LoadUint32(&o.ICACHE_ATOMIC_OPERATE_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_ATOMIC_OPERATE_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_ATOMIC_OPERATE_ENA.Reg) & 0x1 +} + +// EXTMEM.CACHE_REQUEST: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCACHE_REQUEST_BYPASS(value uint32) { + volatile.StoreUint32(&o.CACHE_REQUEST.Reg, volatile.LoadUint32(&o.CACHE_REQUEST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_REQUEST_BYPASS() uint32 { + return volatile.LoadUint32(&o.CACHE_REQUEST.Reg) & 0x1 +} + +// EXTMEM.IBUS_PMS_TBL_LOCK: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_PMS_TBL_LOCK_IBUS_PMS_LOCK(value uint32) { + volatile.StoreUint32(&o.IBUS_PMS_TBL_LOCK.Reg, volatile.LoadUint32(&o.IBUS_PMS_TBL_LOCK.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetIBUS_PMS_TBL_LOCK_IBUS_PMS_LOCK() uint32 { + return volatile.LoadUint32(&o.IBUS_PMS_TBL_LOCK.Reg) & 0x1 +} + +// EXTMEM.IBUS_PMS_TBL_BOUNDARY0: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_PMS_TBL_BOUNDARY0_IBUS_PMS_BOUNDARY0(value uint32) { + volatile.StoreUint32(&o.IBUS_PMS_TBL_BOUNDARY0.Reg, volatile.LoadUint32(&o.IBUS_PMS_TBL_BOUNDARY0.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetIBUS_PMS_TBL_BOUNDARY0_IBUS_PMS_BOUNDARY0() uint32 { + return volatile.LoadUint32(&o.IBUS_PMS_TBL_BOUNDARY0.Reg) & 0xfff +} + +// EXTMEM.IBUS_PMS_TBL_BOUNDARY1: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_PMS_TBL_BOUNDARY1_IBUS_PMS_BOUNDARY1(value uint32) { + volatile.StoreUint32(&o.IBUS_PMS_TBL_BOUNDARY1.Reg, volatile.LoadUint32(&o.IBUS_PMS_TBL_BOUNDARY1.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetIBUS_PMS_TBL_BOUNDARY1_IBUS_PMS_BOUNDARY1() uint32 { + return volatile.LoadUint32(&o.IBUS_PMS_TBL_BOUNDARY1.Reg) & 0xfff +} + +// EXTMEM.IBUS_PMS_TBL_BOUNDARY2: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_PMS_TBL_BOUNDARY2_IBUS_PMS_BOUNDARY2(value uint32) { + volatile.StoreUint32(&o.IBUS_PMS_TBL_BOUNDARY2.Reg, volatile.LoadUint32(&o.IBUS_PMS_TBL_BOUNDARY2.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetIBUS_PMS_TBL_BOUNDARY2_IBUS_PMS_BOUNDARY2() uint32 { + return volatile.LoadUint32(&o.IBUS_PMS_TBL_BOUNDARY2.Reg) & 0xfff +} + +// EXTMEM.IBUS_PMS_TBL_ATTR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetIBUS_PMS_TBL_ATTR_IBUS_PMS_SCT1_ATTR(value uint32) { + volatile.StoreUint32(&o.IBUS_PMS_TBL_ATTR.Reg, volatile.LoadUint32(&o.IBUS_PMS_TBL_ATTR.Reg)&^(0xf)|value) +} +func (o *EXTMEM_Type) GetIBUS_PMS_TBL_ATTR_IBUS_PMS_SCT1_ATTR() uint32 { + return volatile.LoadUint32(&o.IBUS_PMS_TBL_ATTR.Reg) & 0xf +} +func (o *EXTMEM_Type) SetIBUS_PMS_TBL_ATTR_IBUS_PMS_SCT2_ATTR(value uint32) { + volatile.StoreUint32(&o.IBUS_PMS_TBL_ATTR.Reg, volatile.LoadUint32(&o.IBUS_PMS_TBL_ATTR.Reg)&^(0xf0)|value<<4) +} +func (o *EXTMEM_Type) GetIBUS_PMS_TBL_ATTR_IBUS_PMS_SCT2_ATTR() uint32 { + return (volatile.LoadUint32(&o.IBUS_PMS_TBL_ATTR.Reg) & 0xf0) >> 4 +} + +// EXTMEM.DBUS_PMS_TBL_LOCK: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_PMS_TBL_LOCK_DBUS_PMS_LOCK(value uint32) { + volatile.StoreUint32(&o.DBUS_PMS_TBL_LOCK.Reg, volatile.LoadUint32(&o.DBUS_PMS_TBL_LOCK.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDBUS_PMS_TBL_LOCK_DBUS_PMS_LOCK() uint32 { + return volatile.LoadUint32(&o.DBUS_PMS_TBL_LOCK.Reg) & 0x1 +} + +// EXTMEM.DBUS_PMS_TBL_BOUNDARY0: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_PMS_TBL_BOUNDARY0_DBUS_PMS_BOUNDARY0(value uint32) { + volatile.StoreUint32(&o.DBUS_PMS_TBL_BOUNDARY0.Reg, volatile.LoadUint32(&o.DBUS_PMS_TBL_BOUNDARY0.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetDBUS_PMS_TBL_BOUNDARY0_DBUS_PMS_BOUNDARY0() uint32 { + return volatile.LoadUint32(&o.DBUS_PMS_TBL_BOUNDARY0.Reg) & 0xfff +} + +// EXTMEM.DBUS_PMS_TBL_BOUNDARY1: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_PMS_TBL_BOUNDARY1_DBUS_PMS_BOUNDARY1(value uint32) { + volatile.StoreUint32(&o.DBUS_PMS_TBL_BOUNDARY1.Reg, volatile.LoadUint32(&o.DBUS_PMS_TBL_BOUNDARY1.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetDBUS_PMS_TBL_BOUNDARY1_DBUS_PMS_BOUNDARY1() uint32 { + return volatile.LoadUint32(&o.DBUS_PMS_TBL_BOUNDARY1.Reg) & 0xfff +} + +// EXTMEM.DBUS_PMS_TBL_BOUNDARY2: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_PMS_TBL_BOUNDARY2_DBUS_PMS_BOUNDARY2(value uint32) { + volatile.StoreUint32(&o.DBUS_PMS_TBL_BOUNDARY2.Reg, volatile.LoadUint32(&o.DBUS_PMS_TBL_BOUNDARY2.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetDBUS_PMS_TBL_BOUNDARY2_DBUS_PMS_BOUNDARY2() uint32 { + return volatile.LoadUint32(&o.DBUS_PMS_TBL_BOUNDARY2.Reg) & 0xfff +} + +// EXTMEM.DBUS_PMS_TBL_ATTR: This description will be updated in the near future. +func (o *EXTMEM_Type) SetDBUS_PMS_TBL_ATTR_DBUS_PMS_SCT1_ATTR(value uint32) { + volatile.StoreUint32(&o.DBUS_PMS_TBL_ATTR.Reg, volatile.LoadUint32(&o.DBUS_PMS_TBL_ATTR.Reg)&^(0x3)|value) +} +func (o *EXTMEM_Type) GetDBUS_PMS_TBL_ATTR_DBUS_PMS_SCT1_ATTR() uint32 { + return volatile.LoadUint32(&o.DBUS_PMS_TBL_ATTR.Reg) & 0x3 +} +func (o *EXTMEM_Type) SetDBUS_PMS_TBL_ATTR_DBUS_PMS_SCT2_ATTR(value uint32) { + volatile.StoreUint32(&o.DBUS_PMS_TBL_ATTR.Reg, volatile.LoadUint32(&o.DBUS_PMS_TBL_ATTR.Reg)&^(0xc)|value<<2) +} +func (o *EXTMEM_Type) GetDBUS_PMS_TBL_ATTR_DBUS_PMS_SCT2_ATTR() uint32 { + return (volatile.LoadUint32(&o.DBUS_PMS_TBL_ATTR.Reg) & 0xc) >> 2 +} + +// EXTMEM.CLOCK_GATE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// EXTMEM.REG_DATE: This description will be updated in the near future. +func (o *EXTMEM_Type) SetREG_DATE_DATE(value uint32) { + volatile.StoreUint32(&o.REG_DATE.Reg, volatile.LoadUint32(&o.REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetREG_DATE_DATE() uint32 { + return volatile.LoadUint32(&o.REG_DATE.Reg) & 0xfffffff +} + +// General Purpose Input/Output +type GPIO_Type struct { + BT_SELECT volatile.Register32 // 0x0 + OUT volatile.Register32 // 0x4 + OUT_W1TS volatile.Register32 // 0x8 + OUT_W1TC volatile.Register32 // 0xC + _ [12]byte + SDIO_SELECT volatile.Register32 // 0x1C + ENABLE volatile.Register32 // 0x20 + ENABLE_W1TS volatile.Register32 // 0x24 + ENABLE_W1TC volatile.Register32 // 0x28 + _ [12]byte + STRAP volatile.Register32 // 0x38 + IN volatile.Register32 // 0x3C + _ [4]byte + STATUS volatile.Register32 // 0x44 + STATUS_W1TS volatile.Register32 // 0x48 + STATUS_W1TC volatile.Register32 // 0x4C + _ [12]byte + PCPU_INT volatile.Register32 // 0x5C + PCPU_NMI_INT volatile.Register32 // 0x60 + CPUSDIO_INT volatile.Register32 // 0x64 + _ [12]byte + PIN0 volatile.Register32 // 0x74 + PIN1 volatile.Register32 // 0x78 + PIN2 volatile.Register32 // 0x7C + PIN3 volatile.Register32 // 0x80 + PIN4 volatile.Register32 // 0x84 + PIN5 volatile.Register32 // 0x88 + PIN6 volatile.Register32 // 0x8C + PIN7 volatile.Register32 // 0x90 + PIN8 volatile.Register32 // 0x94 + PIN9 volatile.Register32 // 0x98 + PIN10 volatile.Register32 // 0x9C + PIN11 volatile.Register32 // 0xA0 + PIN12 volatile.Register32 // 0xA4 + PIN13 volatile.Register32 // 0xA8 + PIN14 volatile.Register32 // 0xAC + PIN15 volatile.Register32 // 0xB0 + PIN16 volatile.Register32 // 0xB4 + PIN17 volatile.Register32 // 0xB8 + PIN18 volatile.Register32 // 0xBC + PIN19 volatile.Register32 // 0xC0 + PIN20 volatile.Register32 // 0xC4 + PIN21 volatile.Register32 // 0xC8 + PIN22 volatile.Register32 // 0xCC + PIN23 volatile.Register32 // 0xD0 + PIN24 volatile.Register32 // 0xD4 + PIN25 volatile.Register32 // 0xD8 + _ [112]byte + STATUS_NEXT volatile.Register32 // 0x14C + _ [4]byte + FUNC0_IN_SEL_CFG volatile.Register32 // 0x154 + FUNC1_IN_SEL_CFG volatile.Register32 // 0x158 + FUNC2_IN_SEL_CFG volatile.Register32 // 0x15C + FUNC3_IN_SEL_CFG volatile.Register32 // 0x160 + FUNC4_IN_SEL_CFG volatile.Register32 // 0x164 + FUNC5_IN_SEL_CFG volatile.Register32 // 0x168 + FUNC6_IN_SEL_CFG volatile.Register32 // 0x16C + FUNC7_IN_SEL_CFG volatile.Register32 // 0x170 + FUNC8_IN_SEL_CFG volatile.Register32 // 0x174 + FUNC9_IN_SEL_CFG volatile.Register32 // 0x178 + FUNC10_IN_SEL_CFG volatile.Register32 // 0x17C + FUNC11_IN_SEL_CFG volatile.Register32 // 0x180 + FUNC12_IN_SEL_CFG volatile.Register32 // 0x184 + FUNC13_IN_SEL_CFG volatile.Register32 // 0x188 + FUNC14_IN_SEL_CFG volatile.Register32 // 0x18C + FUNC15_IN_SEL_CFG volatile.Register32 // 0x190 + FUNC16_IN_SEL_CFG volatile.Register32 // 0x194 + FUNC17_IN_SEL_CFG volatile.Register32 // 0x198 + FUNC18_IN_SEL_CFG volatile.Register32 // 0x19C + FUNC19_IN_SEL_CFG volatile.Register32 // 0x1A0 + FUNC20_IN_SEL_CFG volatile.Register32 // 0x1A4 + FUNC21_IN_SEL_CFG volatile.Register32 // 0x1A8 + FUNC22_IN_SEL_CFG volatile.Register32 // 0x1AC + FUNC23_IN_SEL_CFG volatile.Register32 // 0x1B0 + FUNC24_IN_SEL_CFG volatile.Register32 // 0x1B4 + FUNC25_IN_SEL_CFG volatile.Register32 // 0x1B8 + FUNC26_IN_SEL_CFG volatile.Register32 // 0x1BC + FUNC27_IN_SEL_CFG volatile.Register32 // 0x1C0 + FUNC28_IN_SEL_CFG volatile.Register32 // 0x1C4 + FUNC29_IN_SEL_CFG volatile.Register32 // 0x1C8 + FUNC30_IN_SEL_CFG volatile.Register32 // 0x1CC + FUNC31_IN_SEL_CFG volatile.Register32 // 0x1D0 + FUNC32_IN_SEL_CFG volatile.Register32 // 0x1D4 + FUNC33_IN_SEL_CFG volatile.Register32 // 0x1D8 + FUNC34_IN_SEL_CFG volatile.Register32 // 0x1DC + FUNC35_IN_SEL_CFG volatile.Register32 // 0x1E0 + FUNC36_IN_SEL_CFG volatile.Register32 // 0x1E4 + FUNC37_IN_SEL_CFG volatile.Register32 // 0x1E8 + FUNC38_IN_SEL_CFG volatile.Register32 // 0x1EC + FUNC39_IN_SEL_CFG volatile.Register32 // 0x1F0 + FUNC40_IN_SEL_CFG volatile.Register32 // 0x1F4 + FUNC41_IN_SEL_CFG volatile.Register32 // 0x1F8 + FUNC42_IN_SEL_CFG volatile.Register32 // 0x1FC + FUNC43_IN_SEL_CFG volatile.Register32 // 0x200 + FUNC44_IN_SEL_CFG volatile.Register32 // 0x204 + FUNC45_IN_SEL_CFG volatile.Register32 // 0x208 + FUNC46_IN_SEL_CFG volatile.Register32 // 0x20C + FUNC47_IN_SEL_CFG volatile.Register32 // 0x210 + FUNC48_IN_SEL_CFG volatile.Register32 // 0x214 + FUNC49_IN_SEL_CFG volatile.Register32 // 0x218 + FUNC50_IN_SEL_CFG volatile.Register32 // 0x21C + FUNC51_IN_SEL_CFG volatile.Register32 // 0x220 + FUNC52_IN_SEL_CFG volatile.Register32 // 0x224 + FUNC53_IN_SEL_CFG volatile.Register32 // 0x228 + FUNC54_IN_SEL_CFG volatile.Register32 // 0x22C + FUNC55_IN_SEL_CFG volatile.Register32 // 0x230 + FUNC56_IN_SEL_CFG volatile.Register32 // 0x234 + FUNC57_IN_SEL_CFG volatile.Register32 // 0x238 + FUNC58_IN_SEL_CFG volatile.Register32 // 0x23C + FUNC59_IN_SEL_CFG volatile.Register32 // 0x240 + FUNC60_IN_SEL_CFG volatile.Register32 // 0x244 + FUNC61_IN_SEL_CFG volatile.Register32 // 0x248 + FUNC62_IN_SEL_CFG volatile.Register32 // 0x24C + FUNC63_IN_SEL_CFG volatile.Register32 // 0x250 + FUNC64_IN_SEL_CFG volatile.Register32 // 0x254 + FUNC65_IN_SEL_CFG volatile.Register32 // 0x258 + FUNC66_IN_SEL_CFG volatile.Register32 // 0x25C + FUNC67_IN_SEL_CFG volatile.Register32 // 0x260 + FUNC68_IN_SEL_CFG volatile.Register32 // 0x264 + FUNC69_IN_SEL_CFG volatile.Register32 // 0x268 + FUNC70_IN_SEL_CFG volatile.Register32 // 0x26C + FUNC71_IN_SEL_CFG volatile.Register32 // 0x270 + FUNC72_IN_SEL_CFG volatile.Register32 // 0x274 + FUNC73_IN_SEL_CFG volatile.Register32 // 0x278 + FUNC74_IN_SEL_CFG volatile.Register32 // 0x27C + FUNC75_IN_SEL_CFG volatile.Register32 // 0x280 + FUNC76_IN_SEL_CFG volatile.Register32 // 0x284 + FUNC77_IN_SEL_CFG volatile.Register32 // 0x288 + FUNC78_IN_SEL_CFG volatile.Register32 // 0x28C + FUNC79_IN_SEL_CFG volatile.Register32 // 0x290 + FUNC80_IN_SEL_CFG volatile.Register32 // 0x294 + FUNC81_IN_SEL_CFG volatile.Register32 // 0x298 + FUNC82_IN_SEL_CFG volatile.Register32 // 0x29C + FUNC83_IN_SEL_CFG volatile.Register32 // 0x2A0 + FUNC84_IN_SEL_CFG volatile.Register32 // 0x2A4 + FUNC85_IN_SEL_CFG volatile.Register32 // 0x2A8 + FUNC86_IN_SEL_CFG volatile.Register32 // 0x2AC + FUNC87_IN_SEL_CFG volatile.Register32 // 0x2B0 + FUNC88_IN_SEL_CFG volatile.Register32 // 0x2B4 + FUNC89_IN_SEL_CFG volatile.Register32 // 0x2B8 + FUNC90_IN_SEL_CFG volatile.Register32 // 0x2BC + FUNC91_IN_SEL_CFG volatile.Register32 // 0x2C0 + FUNC92_IN_SEL_CFG volatile.Register32 // 0x2C4 + FUNC93_IN_SEL_CFG volatile.Register32 // 0x2C8 + FUNC94_IN_SEL_CFG volatile.Register32 // 0x2CC + FUNC95_IN_SEL_CFG volatile.Register32 // 0x2D0 + FUNC96_IN_SEL_CFG volatile.Register32 // 0x2D4 + FUNC97_IN_SEL_CFG volatile.Register32 // 0x2D8 + FUNC98_IN_SEL_CFG volatile.Register32 // 0x2DC + FUNC99_IN_SEL_CFG volatile.Register32 // 0x2E0 + FUNC100_IN_SEL_CFG volatile.Register32 // 0x2E4 + FUNC101_IN_SEL_CFG volatile.Register32 // 0x2E8 + FUNC102_IN_SEL_CFG volatile.Register32 // 0x2EC + FUNC103_IN_SEL_CFG volatile.Register32 // 0x2F0 + FUNC104_IN_SEL_CFG volatile.Register32 // 0x2F4 + FUNC105_IN_SEL_CFG volatile.Register32 // 0x2F8 + FUNC106_IN_SEL_CFG volatile.Register32 // 0x2FC + FUNC107_IN_SEL_CFG volatile.Register32 // 0x300 + FUNC108_IN_SEL_CFG volatile.Register32 // 0x304 + FUNC109_IN_SEL_CFG volatile.Register32 // 0x308 + FUNC110_IN_SEL_CFG volatile.Register32 // 0x30C + FUNC111_IN_SEL_CFG volatile.Register32 // 0x310 + FUNC112_IN_SEL_CFG volatile.Register32 // 0x314 + FUNC113_IN_SEL_CFG volatile.Register32 // 0x318 + FUNC114_IN_SEL_CFG volatile.Register32 // 0x31C + FUNC115_IN_SEL_CFG volatile.Register32 // 0x320 + FUNC116_IN_SEL_CFG volatile.Register32 // 0x324 + FUNC117_IN_SEL_CFG volatile.Register32 // 0x328 + FUNC118_IN_SEL_CFG volatile.Register32 // 0x32C + FUNC119_IN_SEL_CFG volatile.Register32 // 0x330 + FUNC120_IN_SEL_CFG volatile.Register32 // 0x334 + FUNC121_IN_SEL_CFG volatile.Register32 // 0x338 + FUNC122_IN_SEL_CFG volatile.Register32 // 0x33C + FUNC123_IN_SEL_CFG volatile.Register32 // 0x340 + FUNC124_IN_SEL_CFG volatile.Register32 // 0x344 + FUNC125_IN_SEL_CFG volatile.Register32 // 0x348 + FUNC126_IN_SEL_CFG volatile.Register32 // 0x34C + FUNC127_IN_SEL_CFG volatile.Register32 // 0x350 + _ [512]byte + FUNC0_OUT_SEL_CFG volatile.Register32 // 0x554 + FUNC1_OUT_SEL_CFG volatile.Register32 // 0x558 + FUNC2_OUT_SEL_CFG volatile.Register32 // 0x55C + FUNC3_OUT_SEL_CFG volatile.Register32 // 0x560 + FUNC4_OUT_SEL_CFG volatile.Register32 // 0x564 + FUNC5_OUT_SEL_CFG volatile.Register32 // 0x568 + FUNC6_OUT_SEL_CFG volatile.Register32 // 0x56C + FUNC7_OUT_SEL_CFG volatile.Register32 // 0x570 + FUNC8_OUT_SEL_CFG volatile.Register32 // 0x574 + FUNC9_OUT_SEL_CFG volatile.Register32 // 0x578 + FUNC10_OUT_SEL_CFG volatile.Register32 // 0x57C + FUNC11_OUT_SEL_CFG volatile.Register32 // 0x580 + FUNC12_OUT_SEL_CFG volatile.Register32 // 0x584 + FUNC13_OUT_SEL_CFG volatile.Register32 // 0x588 + FUNC14_OUT_SEL_CFG volatile.Register32 // 0x58C + FUNC15_OUT_SEL_CFG volatile.Register32 // 0x590 + FUNC16_OUT_SEL_CFG volatile.Register32 // 0x594 + FUNC17_OUT_SEL_CFG volatile.Register32 // 0x598 + FUNC18_OUT_SEL_CFG volatile.Register32 // 0x59C + FUNC19_OUT_SEL_CFG volatile.Register32 // 0x5A0 + FUNC20_OUT_SEL_CFG volatile.Register32 // 0x5A4 + FUNC21_OUT_SEL_CFG volatile.Register32 // 0x5A8 + FUNC22_OUT_SEL_CFG volatile.Register32 // 0x5AC + FUNC23_OUT_SEL_CFG volatile.Register32 // 0x5B0 + FUNC24_OUT_SEL_CFG volatile.Register32 // 0x5B4 + FUNC25_OUT_SEL_CFG volatile.Register32 // 0x5B8 + _ [112]byte + CLOCK_GATE volatile.Register32 // 0x62C + _ [204]byte + REG_DATE volatile.Register32 // 0x6FC +} + +// GPIO.BT_SELECT: GPIO bit select register +func (o *GPIO_Type) SetBT_SELECT(value uint32) { + volatile.StoreUint32(&o.BT_SELECT.Reg, value) +} +func (o *GPIO_Type) GetBT_SELECT() uint32 { + return volatile.LoadUint32(&o.BT_SELECT.Reg) +} + +// GPIO.OUT: GPIO output register +func (o *GPIO_Type) SetOUT_DATA_ORIG(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, volatile.LoadUint32(&o.OUT.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetOUT_DATA_ORIG() uint32 { + return volatile.LoadUint32(&o.OUT.Reg) & 0x3ffffff +} + +// GPIO.OUT_W1TS: GPIO output set register +func (o *GPIO_Type) SetOUT_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, volatile.LoadUint32(&o.OUT_W1TS.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetOUT_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_W1TS.Reg) & 0x3ffffff +} + +// GPIO.OUT_W1TC: GPIO output clear register +func (o *GPIO_Type) SetOUT_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, volatile.LoadUint32(&o.OUT_W1TC.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetOUT_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_W1TC.Reg) & 0x3ffffff +} + +// GPIO.SDIO_SELECT: GPIO sdio select register +func (o *GPIO_Type) SetSDIO_SELECT_SDIO_SEL(value uint32) { + volatile.StoreUint32(&o.SDIO_SELECT.Reg, volatile.LoadUint32(&o.SDIO_SELECT.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSDIO_SELECT_SDIO_SEL() uint32 { + return volatile.LoadUint32(&o.SDIO_SELECT.Reg) & 0xff +} + +// GPIO.ENABLE: GPIO output enable register +func (o *GPIO_Type) SetENABLE_DATA(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, volatile.LoadUint32(&o.ENABLE.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetENABLE_DATA() uint32 { + return volatile.LoadUint32(&o.ENABLE.Reg) & 0x3ffffff +} + +// GPIO.ENABLE_W1TS: GPIO output enable set register +func (o *GPIO_Type) SetENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, volatile.LoadUint32(&o.ENABLE_W1TS.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) & 0x3ffffff +} + +// GPIO.ENABLE_W1TC: GPIO output enable clear register +func (o *GPIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, volatile.LoadUint32(&o.ENABLE_W1TC.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) & 0x3ffffff +} + +// GPIO.STRAP: pad strapping register +func (o *GPIO_Type) SetSTRAP_STRAPPING(value uint32) { + volatile.StoreUint32(&o.STRAP.Reg, volatile.LoadUint32(&o.STRAP.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetSTRAP_STRAPPING() uint32 { + return volatile.LoadUint32(&o.STRAP.Reg) & 0xffff +} + +// GPIO.IN: GPIO input register +func (o *GPIO_Type) SetIN_DATA_NEXT(value uint32) { + volatile.StoreUint32(&o.IN.Reg, volatile.LoadUint32(&o.IN.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetIN_DATA_NEXT() uint32 { + return volatile.LoadUint32(&o.IN.Reg) & 0x3ffffff +} + +// GPIO.STATUS: GPIO interrupt status register +func (o *GPIO_Type) SetSTATUS_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x3ffffff +} + +// GPIO.STATUS_W1TS: GPIO interrupt status set register +func (o *GPIO_Type) SetSTATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, volatile.LoadUint32(&o.STATUS_W1TS.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) & 0x3ffffff +} + +// GPIO.STATUS_W1TC: GPIO interrupt status clear register +func (o *GPIO_Type) SetSTATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, volatile.LoadUint32(&o.STATUS_W1TC.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) & 0x3ffffff +} + +// GPIO.PCPU_INT: GPIO PRO_CPU interrupt status register +func (o *GPIO_Type) SetPCPU_INT_PROCPU_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_INT.Reg, volatile.LoadUint32(&o.PCPU_INT.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetPCPU_INT_PROCPU_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_INT.Reg) & 0x3ffffff +} + +// GPIO.PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register +func (o *GPIO_Type) SetPCPU_NMI_INT_PROCPU_NMI_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT.Reg, volatile.LoadUint32(&o.PCPU_NMI_INT.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT_PROCPU_NMI_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT.Reg) & 0x3ffffff +} + +// GPIO.CPUSDIO_INT: GPIO CPUSDIO interrupt status register +func (o *GPIO_Type) SetCPUSDIO_INT_SDIO_INT(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT.Reg, volatile.LoadUint32(&o.CPUSDIO_INT.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetCPUSDIO_INT_SDIO_INT() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT.Reg) & 0x3ffffff +} + +// GPIO.PIN0: GPIO pin configuration register +func (o *GPIO_Type) SetPIN0_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN0_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN0_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN0_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN0_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN0_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN1: GPIO pin configuration register +func (o *GPIO_Type) SetPIN1_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN1_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN1_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN1_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN1_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN1_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN2: GPIO pin configuration register +func (o *GPIO_Type) SetPIN2_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN2_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN2_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN2_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN2_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN2_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN3: GPIO pin configuration register +func (o *GPIO_Type) SetPIN3_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN3_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN3_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN3_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN3_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN3_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN4: GPIO pin configuration register +func (o *GPIO_Type) SetPIN4_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN4_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN4_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN4_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN4_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN4_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN5: GPIO pin configuration register +func (o *GPIO_Type) SetPIN5_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN5_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN5_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN5_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN5_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN5_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN6: GPIO pin configuration register +func (o *GPIO_Type) SetPIN6_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN6_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN6_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN6_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN6_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN6_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN7: GPIO pin configuration register +func (o *GPIO_Type) SetPIN7_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN7_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN7_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN7_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN7_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN7_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN8: GPIO pin configuration register +func (o *GPIO_Type) SetPIN8_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN8_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN8.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN8_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN8_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN8_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN8_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN9: GPIO pin configuration register +func (o *GPIO_Type) SetPIN9_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN9_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN9.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN9_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN9_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN9_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN9_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN10: GPIO pin configuration register +func (o *GPIO_Type) SetPIN10_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN10_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN10.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN10_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN10_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN10_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN10_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN10_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN10_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN11: GPIO pin configuration register +func (o *GPIO_Type) SetPIN11_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN11_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN11.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN11_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN11_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN11_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN11_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN11_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN11_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN12: GPIO pin configuration register +func (o *GPIO_Type) SetPIN12_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN12_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN12.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN12_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN12_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN12_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN12_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN12_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN12_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN13: GPIO pin configuration register +func (o *GPIO_Type) SetPIN13_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN13_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN13.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN13_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN13_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN13_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN13_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN13_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN13_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN14: GPIO pin configuration register +func (o *GPIO_Type) SetPIN14_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN14_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN14.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN14_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN14_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN14_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN14_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN14_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN14_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN15: GPIO pin configuration register +func (o *GPIO_Type) SetPIN15_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN15_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN15.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN15_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN15_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN15_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN15_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN15_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN15_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN16: GPIO pin configuration register +func (o *GPIO_Type) SetPIN16_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN16_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN16.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN16_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN16_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN16_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN16_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN16_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN16_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN17: GPIO pin configuration register +func (o *GPIO_Type) SetPIN17_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN17_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN17.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN17_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN17_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN17_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN17_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN17_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN17_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN18: GPIO pin configuration register +func (o *GPIO_Type) SetPIN18_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN18_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN18.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN18_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN18_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN18_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN18_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN18_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN18_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN19: GPIO pin configuration register +func (o *GPIO_Type) SetPIN19_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN19_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN19.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN19_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN19_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN19_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN19_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN19_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN19_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN20: GPIO pin configuration register +func (o *GPIO_Type) SetPIN20_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN20_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN20.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN20_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN20_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN20_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN20_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN20_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN20_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN21: GPIO pin configuration register +func (o *GPIO_Type) SetPIN21_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN21_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN21.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN21_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN21_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN21_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN21_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN21_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN21_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN22: GPIO pin configuration register +func (o *GPIO_Type) SetPIN22_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN22_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN22.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN22_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN22_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN22_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN22_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN22_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN22_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN22_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN22_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN22_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN22_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN22_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN22_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN23: GPIO pin configuration register +func (o *GPIO_Type) SetPIN23_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN23_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN23.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN23_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN23_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN23_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN23_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN23_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN23_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN23_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN23_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN23_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN23_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN23_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN23_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN24: GPIO pin configuration register +func (o *GPIO_Type) SetPIN24_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN24_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN24.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN24_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN24_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN24_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN24_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN24_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN24_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN24_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN24_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN24_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN24_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN24_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN24_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN25: GPIO pin configuration register +func (o *GPIO_Type) SetPIN25_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN25_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN25.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN25_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN25_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN25_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN25_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN25_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN25_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN25_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN25_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN25_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN25_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN25_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN25_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x3e000) >> 13 +} + +// GPIO.STATUS_NEXT: GPIO interrupt source register +func (o *GPIO_Type) SetSTATUS_NEXT_STATUS_INTERRUPT_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT.Reg, volatile.LoadUint32(&o.STATUS_NEXT.Reg)&^(0x3ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS_NEXT_STATUS_INTERRUPT_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT.Reg) & 0x3ffffff +} + +// GPIO.FUNC0_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC1_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC2_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC3_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC4_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC5_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC6_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC7_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC8_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC9_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC10_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC11_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC12_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC13_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC14_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC15_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC16_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC17_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC18_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC19_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC20_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC21_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC22_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC23_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC24_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC25_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC26_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC27_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC28_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC29_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC30_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC31_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC32_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC33_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC34_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC35_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC36_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC37_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC38_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC39_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC40_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC41_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC42_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC43_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC44_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC45_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC46_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC47_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC48_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC49_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC50_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC51_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC52_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC53_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC54_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC55_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC56_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC57_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC58_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC59_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC60_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC61_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC62_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC63_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC64_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC65_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC66_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC67_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC68_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC69_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC70_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC71_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC72_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC73_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC74_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC75_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC76_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC77_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC78_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC79_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC80_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC81_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC82_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC83_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC84_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC85_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC86_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC87_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC88_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC89_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC90_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC91_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC92_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC93_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC94_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC95_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC96_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC97_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC98_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC99_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC100_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC101_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC102_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC103_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC104_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC105_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC106_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC107_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC108_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC109_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC110_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC111_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC112_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC113_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC114_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC115_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC116_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC117_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC118_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC119_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC120_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC121_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC122_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC123_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC124_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC125_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC126_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC127_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x1f +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x40) >> 6 +} + +// GPIO.FUNC0_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC1_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC2_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC3_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC4_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC5_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC6_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC7_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC8_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC9_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC10_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC11_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC12_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC13_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC14_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC15_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC16_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC17_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC18_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC19_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC20_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC21_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC22_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC23_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC24_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC25_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.CLOCK_GATE: GPIO clock gate register +func (o *GPIO_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIO.REG_DATE: GPIO version register +func (o *GPIO_Type) SetREG_DATE(value uint32) { + volatile.StoreUint32(&o.REG_DATE.Reg, volatile.LoadUint32(&o.REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *GPIO_Type) GetREG_DATE() uint32 { + return volatile.LoadUint32(&o.REG_DATE.Reg) & 0xfffffff +} + +// Sigma-Delta Modulation +type GPIOSD_Type struct { + SIGMADELTA0 volatile.Register32 // 0x0 + SIGMADELTA1 volatile.Register32 // 0x4 + SIGMADELTA2 volatile.Register32 // 0x8 + SIGMADELTA3 volatile.Register32 // 0xC + _ [16]byte + SIGMADELTA_CG volatile.Register32 // 0x20 + SIGMADELTA_MISC volatile.Register32 // 0x24 + SIGMADELTA_VERSION volatile.Register32 // 0x28 +} + +// GPIOSD.SIGMADELTA0: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA0_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA0_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA1: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA1_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA1_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA2: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA2_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA2_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA3: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA3_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA3_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA_CG: Clock Gating Configure Register +func (o *GPIOSD_Type) SetSIGMADELTA_CG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_CG.Reg, volatile.LoadUint32(&o.SIGMADELTA_CG.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIOSD_Type) GetSIGMADELTA_CG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_CG.Reg) & 0x80000000) >> 31 +} + +// GPIOSD.SIGMADELTA_MISC: MISC Register +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_FUNCTION_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_FUNCTION_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x40000000) >> 30 +} +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_SPI_SWAP(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_SPI_SWAP() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x80000000) >> 31 +} + +// GPIOSD.SIGMADELTA_VERSION: Version Control Register +func (o *GPIOSD_Type) SetSIGMADELTA_VERSION_GPIO_SD_DATE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_VERSION.Reg, volatile.LoadUint32(&o.SIGMADELTA_VERSION.Reg)&^(0xfffffff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA_VERSION_GPIO_SD_DATE() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA_VERSION.Reg) & 0xfffffff +} + +// HMAC (Hash-based Message Authentication Code) Accelerator +type HMAC_Type struct { + _ [64]byte + SET_START volatile.Register32 // 0x40 + SET_PARA_PURPOSE volatile.Register32 // 0x44 + SET_PARA_KEY volatile.Register32 // 0x48 + SET_PARA_FINISH volatile.Register32 // 0x4C + SET_MESSAGE_ONE volatile.Register32 // 0x50 + SET_MESSAGE_ING volatile.Register32 // 0x54 + SET_MESSAGE_END volatile.Register32 // 0x58 + SET_RESULT_FINISH volatile.Register32 // 0x5C + SET_INVALIDATE_JTAG volatile.Register32 // 0x60 + SET_INVALIDATE_DS volatile.Register32 // 0x64 + QUERY_ERROR volatile.Register32 // 0x68 + QUERY_BUSY volatile.Register32 // 0x6C + _ [16]byte + WR_MESSAGE_MEM [64]volatile.Register8 // 0x80 + RD_RESULT_MEM [32]volatile.Register8 // 0xC0 + _ [16]byte + SET_MESSAGE_PAD volatile.Register32 // 0xF0 + ONE_BLOCK volatile.Register32 // 0xF4 + SOFT_JTAG_CTRL volatile.Register32 // 0xF8 + WR_JTAG volatile.Register32 // 0xFC +} + +// HMAC.SET_START: Process control register 0. +func (o *HMAC_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// HMAC.SET_PARA_PURPOSE: Configure purpose. +func (o *HMAC_Type) SetSET_PARA_PURPOSE_PURPOSE_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_PURPOSE.Reg, volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg)&^(0xf)|value) +} +func (o *HMAC_Type) GetSET_PARA_PURPOSE_PURPOSE_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg) & 0xf +} + +// HMAC.SET_PARA_KEY: Configure key. +func (o *HMAC_Type) SetSET_PARA_KEY_KEY_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_KEY.Reg, volatile.LoadUint32(&o.SET_PARA_KEY.Reg)&^(0x7)|value) +} +func (o *HMAC_Type) GetSET_PARA_KEY_KEY_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_KEY.Reg) & 0x7 +} + +// HMAC.SET_PARA_FINISH: Finish initial configuration. +func (o *HMAC_Type) SetSET_PARA_FINISH_SET_PARA_END(value uint32) { + volatile.StoreUint32(&o.SET_PARA_FINISH.Reg, volatile.LoadUint32(&o.SET_PARA_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_PARA_FINISH_SET_PARA_END() uint32 { + return volatile.LoadUint32(&o.SET_PARA_FINISH.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ONE: Process control register 1. +func (o *HMAC_Type) SetSET_MESSAGE_ONE_SET_TEXT_ONE(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ONE.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ONE_SET_TEXT_ONE() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ING: Process control register 2. +func (o *HMAC_Type) SetSET_MESSAGE_ING_SET_TEXT_ING(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ING.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ING_SET_TEXT_ING() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_END: Process control register 3. +func (o *HMAC_Type) SetSET_MESSAGE_END_SET_TEXT_END(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_END.Reg, volatile.LoadUint32(&o.SET_MESSAGE_END.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_END_SET_TEXT_END() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_END.Reg) & 0x1 +} + +// HMAC.SET_RESULT_FINISH: Process control register 4. +func (o *HMAC_Type) SetSET_RESULT_FINISH_SET_RESULT_END(value uint32) { + volatile.StoreUint32(&o.SET_RESULT_FINISH.Reg, volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_RESULT_FINISH_SET_RESULT_END() uint32 { + return volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_JTAG: Invalidate register 0. +func (o *HMAC_Type) SetSET_INVALIDATE_JTAG(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_JTAG.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_JTAG() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_DS: Invalidate register 1. +func (o *HMAC_Type) SetSET_INVALIDATE_DS(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_DS.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_DS() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg) & 0x1 +} + +// HMAC.QUERY_ERROR: Error register. +func (o *HMAC_Type) SetQUERY_ERROR_QUERY_CHECK(value uint32) { + volatile.StoreUint32(&o.QUERY_ERROR.Reg, volatile.LoadUint32(&o.QUERY_ERROR.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_ERROR_QUERY_CHECK() uint32 { + return volatile.LoadUint32(&o.QUERY_ERROR.Reg) & 0x1 +} + +// HMAC.QUERY_BUSY: Busy register. +func (o *HMAC_Type) SetQUERY_BUSY_BUSY_STATE(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_BUSY_BUSY_STATE() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_PAD: Process control register 5. +func (o *HMAC_Type) SetSET_MESSAGE_PAD_SET_TEXT_PAD(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_PAD.Reg, volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_PAD_SET_TEXT_PAD() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg) & 0x1 +} + +// HMAC.ONE_BLOCK: Process control register 6. +func (o *HMAC_Type) SetONE_BLOCK_SET_ONE_BLOCK(value uint32) { + volatile.StoreUint32(&o.ONE_BLOCK.Reg, volatile.LoadUint32(&o.ONE_BLOCK.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetONE_BLOCK_SET_ONE_BLOCK() uint32 { + return volatile.LoadUint32(&o.ONE_BLOCK.Reg) & 0x1 +} + +// HMAC.SOFT_JTAG_CTRL: Jtag register 0. +func (o *HMAC_Type) SetSOFT_JTAG_CTRL(value uint32) { + volatile.StoreUint32(&o.SOFT_JTAG_CTRL.Reg, volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSOFT_JTAG_CTRL() uint32 { + return volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg) & 0x1 +} + +// HMAC.WR_JTAG: Jtag register 1. +func (o *HMAC_Type) SetWR_JTAG(value uint32) { + volatile.StoreUint32(&o.WR_JTAG.Reg, value) +} +func (o *HMAC_Type) GetWR_JTAG() uint32 { + return volatile.LoadUint32(&o.WR_JTAG.Reg) +} + +// I2C (Inter-Integrated Circuit) Controller 0 +type I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + FILTER_CFG volatile.Register32 // 0x50 + CLK_CONF volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + SCL_ST_TIME_OUT volatile.Register32 // 0x78 + SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C + SCL_SP_CONF volatile.Register32 // 0x80 + SCL_STRETCH_CONF volatile.Register32 // 0x84 + _ [112]byte + DATE volatile.Register32 // 0xF8 + _ [4]byte + TXFIFO_START_ADDR volatile.Register32 // 0x100 + _ [124]byte + RXFIFO_START_ADDR volatile.Register32 // 0x180 +} + +// I2C.SCL_LOW_PERIOD: I2C_SCL_LOW_PERIOD_REG +func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff +} + +// I2C.CTR: I2C_CTR_REG +func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetCTR_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetCTR_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetCTR_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetCTR_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetCTR_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetCTR_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetCTR_CONF_UPGATE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetCTR_CONF_UPGATE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetCTR_SLV_TX_AUTO_START_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetCTR_SLV_TX_AUTO_START_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetCTR_ADDR_10BIT_RW_CHECK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetCTR_ADDR_10BIT_RW_CHECK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetCTR_ADDR_BROADCASTING_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetCTR_ADDR_BROADCASTING_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4000) >> 14 +} + +// I2C.SR: I2C_SR_REG +func (o *I2C_Type) SetSR_RESP_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSR_RESP_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *I2C_Type) SetSR_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetSR_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetSR_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetSR_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetSR_STRETCH_CAUSE(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xc000)|value<<14) +} +func (o *I2C_Type) GetSR_STRETCH_CAUSE() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xc000) >> 14 +} +func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xfc0000) >> 18 +} +func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// I2C.TO: I2C_TO_REG +func (o *I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetTO_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0x1f +} +func (o *I2C_Type) SetTO_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetTO_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5 +} + +// I2C.SLAVE_ADDR: I2C_SLAVE_ADDR_REG +func (o *I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// I2C.FIFO_ST: I2C_FIFO_ST_REG +func (o *I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 { + return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x7c00)|value<<10) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x7c00) >> 10 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf8000)|value<<15) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf8000) >> 15 +} +func (o *I2C_Type) SetFIFO_ST_SLAVE_RW_POINT(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3fc00000)|value<<22) +} +func (o *I2C_Type) GetFIFO_ST_SLAVE_RW_POINT() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3fc00000) >> 22 +} + +// I2C.FIFO_CONF: I2C_FIFO_CONF_REG +func (o *I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_ADDR_CFG_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_ADDR_CFG_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14 +} + +// I2C.DATA: I2C_FIFO_DATA_REG +func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// I2C.INT_RAW: I2C_INT_RAW_REG +func (o *I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_STRETCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_STRETCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_RAW_GENERAL_CALL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_RAW_GENERAL_CALL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} + +// I2C.INT_CLR: I2C_INT_CLR_REG +func (o *I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_STRETCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_STRETCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_CLR_GENERAL_CALL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_CLR_GENERAL_CALL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} + +// I2C.INT_ENA: I2C_INT_ENA_REG +func (o *I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_STRETCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_STRETCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_ENA_GENERAL_CALL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_ENA_GENERAL_CALL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} + +// I2C.INT_STATUS: I2C_INT_STATUS_REG +func (o *I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_STRETCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_STRETCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_STATUS_GENERAL_CALL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_STATUS_GENERAL_CALL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20000) >> 17 +} + +// I2C.SDA_HOLD: I2C_SDA_HOLD_REG +func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff +} + +// I2C.SDA_SAMPLE: I2C_SDA_SAMPLE_REG +func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff +} + +// I2C.SCL_HIGH_PERIOD: I2C_SCL_HIGH_PERIOD_REG +func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff +} +func (o *I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9 +} + +// I2C.SCL_START_HOLD: I2C_SCL_START_HOLD_REG +func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_RSTART_SETUP: I2C_SCL_RSTART_SETUP_REG +func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// I2C.SCL_STOP_HOLD: I2C_SCL_STOP_HOLD_REG +func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_STOP_SETUP: I2C_SCL_STOP_SETUP_REG +func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff +} + +// I2C.FILTER_CFG: I2C_FILTER_CFG_REG +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4 +} +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9 +} + +// I2C.CLK_CONF: I2C_CLK_CONF_REG +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} + +// I2C.COMD0: I2C_COMD%s_REG +func (o *I2C_Type) SetCOMD0_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD0_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD0_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD0_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD1: I2C_COMD%s_REG +func (o *I2C_Type) SetCOMD1_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD1_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD1_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD1_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD2: I2C_COMD%s_REG +func (o *I2C_Type) SetCOMD2_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD2_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD2_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD2_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD3: I2C_COMD%s_REG +func (o *I2C_Type) SetCOMD3_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD3_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD3_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD3_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD4: I2C_COMD%s_REG +func (o *I2C_Type) SetCOMD4_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD4_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD4_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD4_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD5: I2C_COMD%s_REG +func (o *I2C_Type) SetCOMD5_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD5_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD5_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD5_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD6: I2C_COMD%s_REG +func (o *I2C_Type) SetCOMD6_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD6_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD6_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD6_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD7: I2C_COMD%s_REG +func (o *I2C_Type) SetCOMD7_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD7_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD7_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD7_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// I2C.SCL_ST_TIME_OUT: I2C_SCL_ST_TIME_OUT_REG +func (o *I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_MAIN_ST_TIME_OUT: I2C_SCL_MAIN_ST_TIME_OUT_REG +func (o *I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_SP_CONF: I2C_SCL_SP_CONF_REG +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// I2C.SCL_STRETCH_CONF: I2C_SCL_STRETCH_CONF_REG +func (o *I2C_Type) SetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM() uint32 { + return volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x3ff +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x2000) >> 13 +} + +// I2C.DATE: I2C_DATE_REG +func (o *I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2C.TXFIFO_START_ADDR: I2C_TXFIFO_START_ADDR_REG +func (o *I2C_Type) SetTXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetTXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg) +} + +// I2C.RXFIFO_START_ADDR: I2C_RXFIFO_START_ADDR_REG +func (o *I2C_Type) SetRXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetRXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg) +} + +// I2S (Inter-IC Sound) Controller 0 +type I2S_Type struct { + _ [12]byte + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + _ [4]byte + RX_CONF volatile.Register32 // 0x20 + TX_CONF volatile.Register32 // 0x24 + RX_CONF1 volatile.Register32 // 0x28 + TX_CONF1 volatile.Register32 // 0x2C + RX_CLKM_CONF volatile.Register32 // 0x30 + TX_CLKM_CONF volatile.Register32 // 0x34 + RX_CLKM_DIV_CONF volatile.Register32 // 0x38 + TX_CLKM_DIV_CONF volatile.Register32 // 0x3C + TX_PCM2PDM_CONF volatile.Register32 // 0x40 + TX_PCM2PDM_CONF1 volatile.Register32 // 0x44 + _ [8]byte + RX_TDM_CTRL volatile.Register32 // 0x50 + TX_TDM_CTRL volatile.Register32 // 0x54 + RX_TIMING volatile.Register32 // 0x58 + TX_TIMING volatile.Register32 // 0x5C + LC_HUNG_CONF volatile.Register32 // 0x60 + RXEOF_NUM volatile.Register32 // 0x64 + CONF_SIGLE_DATA volatile.Register32 // 0x68 + STATE volatile.Register32 // 0x6C + _ [16]byte + DATE volatile.Register32 // 0x80 +} + +// I2S.INT_RAW: I2S interrupt raw register, valid in level. +func (o *I2S_Type) SetINT_RAW_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_RAW_RX_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// I2S.INT_ST: I2S interrupt status register. +func (o *I2S_Type) SetINT_ST_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ST_RX_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// I2S.INT_ENA: I2S interrupt enable register. +func (o *I2S_Type) SetINT_ENA_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ENA_RX_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// I2S.INT_CLR: I2S interrupt clear register. +func (o *I2S_Type) SetINT_CLR_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_CLR_RX_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// I2S.RX_CONF: I2S RX configure register +func (o *I2S_Type) SetRX_CONF_RX_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_CONF_RX_RESET() uint32 { + return volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_CONF_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_CONF_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_CONF_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_CONF_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_CONF_RX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_CONF_RX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetRX_CONF_RX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_CONF_RX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_CONF_RX_UPDATE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_CONF_RX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_CONF_RX_STOP_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *I2S_Type) GetRX_CONF_RX_STOP_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x6000) >> 13 +} +func (o *I2S_Type) SetRX_CONF_RX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_CONF_RX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_CONF_RX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetRX_CONF_RX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetRX_CONF_RX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetRX_CONF_RX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetRX_CONF_RX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetRX_CONF_RX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetRX_CONF_RX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetRX_CONF_RX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetRX_CONF_RX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetRX_CONF_RX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100000) >> 20 +} + +// I2S.TX_CONF: I2S TX configure register +func (o *I2S_Type) SetTX_CONF_TX_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_CONF_TX_RESET() uint32 { + return volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_CONF_TX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_CONF_TX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_CONF_TX_START(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_CONF_TX_START() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_CONF_TX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_CONF_TX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_EQUAL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_EQUAL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_CONF_TX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_CONF_TX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_CONF_TX_UPDATE(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_CONF_TX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_CONF_TX_STOP_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_CONF_TX_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_CONF_TX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_CONF_TX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_CONF_TX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetTX_CONF_TX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetTX_CONF_TX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetTX_CONF_TX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetTX_CONF_TX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetTX_CONF_TX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetTX_CONF_TX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetTX_CONF_TX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetTX_CONF_TX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_CONF_TX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x7000000)|value<<24) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x7000000) >> 24 +} +func (o *I2S_Type) SetTX_CONF_SIG_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetTX_CONF_SIG_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.RX_CONF1: I2S RX configure register 1 +func (o *I2S_Type) SetRX_CONF1_RX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7f)|value) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7f +} +func (o *I2S_Type) SetRX_CONF1_RX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *I2S_Type) GetRX_CONF1_RX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *I2S_Type) SetRX_CONF1_RX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x3e000)|value<<13) +} +func (o *I2S_Type) GetRX_CONF1_RX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x3e000) >> 13 +} +func (o *I2S_Type) SetRX_CONF1_RX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S_Type) GetRX_CONF1_RX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0xfc0000) >> 18 +} +func (o *I2S_Type) SetRX_CONF1_RX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f000000)|value<<24) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f000000) >> 24 +} +func (o *I2S_Type) SetRX_CONF1_RX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetRX_CONF1_RX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x20000000) >> 29 +} + +// I2S.TX_CONF1: I2S TX configure register 1 +func (o *I2S_Type) SetTX_CONF1_TX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7f)|value) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7f +} +func (o *I2S_Type) SetTX_CONF1_TX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *I2S_Type) GetTX_CONF1_TX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *I2S_Type) SetTX_CONF1_TX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x3e000)|value<<13) +} +func (o *I2S_Type) GetTX_CONF1_TX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x3e000) >> 13 +} +func (o *I2S_Type) SetTX_CONF1_TX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S_Type) GetTX_CONF1_TX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0xfc0000) >> 18 +} +func (o *I2S_Type) SetTX_CONF1_TX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1f000000)|value<<24) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1f000000) >> 24 +} +func (o *I2S_Type) SetTX_CONF1_TX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetTX_CONF1_TX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x20000000) >> 29 +} +func (o *I2S_Type) SetTX_CONF1_TX_BCK_NO_DLY(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetTX_CONF1_TX_BCK_NO_DLY() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x40000000) >> 30 +} + +// I2S.RX_CLKM_CONF: I2S RX clock configure register +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S_Type) SetRX_CLKM_CONF_MCLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetRX_CLKM_CONF_MCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S.TX_CLKM_CONF: I2S TX clock configure register +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S_Type) SetTX_CLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetTX_CLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S.RX_CLKM_DIV_CONF: I2S RX module clock divider configure register +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.TX_CLKM_DIV_CONF: I2S TX module clock divider configure register +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1e)|value<<1) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1e) >> 1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1fe0)|value<<5) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1fe0) >> 5 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x6000) >> 13 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x18000)|value<<15) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x18000) >> 15 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x60000)|value<<17) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x60000) >> 17 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x180000)|value<<19) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x180000) >> 19 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x400000) >> 22 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x800000) >> 23 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1000000) >> 24 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x2000000) >> 25 +} + +// I2S.TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FP(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3ff)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FP() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3ff +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FS() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x700000)|value<<20) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x700000) >> 20 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3800000) >> 23 +} + +// I2S.RX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} + +// I2S.TX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100000) >> 20 +} + +// I2S.RX_TIMING: I2S RX timing control register +func (o *I2S_Type) SetRX_TIMING_RX_SD_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD_IN_DM() uint32 { + return volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.TX_TIMING: I2S TX timing control register +func (o *I2S_Type) SetTX_TIMING_TX_SD_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD_OUT_DM() uint32 { + return volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetTX_TIMING_TX_SD1_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD1_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.LC_HUNG_CONF: I2S HUNG configure register. +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11 +} + +// I2S.RXEOF_NUM: I2S RX data number control register. +func (o *I2S_Type) SetRXEOF_NUM_RX_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.RXEOF_NUM.Reg, volatile.LoadUint32(&o.RXEOF_NUM.Reg)&^(0xfff)|value) +} +func (o *I2S_Type) GetRXEOF_NUM_RX_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.RXEOF_NUM.Reg) & 0xfff +} + +// I2S.CONF_SIGLE_DATA: I2S signal data register +func (o *I2S_Type) SetCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value) +} +func (o *I2S_Type) GetCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg) +} + +// I2S.STATE: I2S TX status register +func (o *I2S_Type) SetSTATE_TX_IDLE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetSTATE_TX_IDLE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x1 +} + +// I2S.DATE: Version control register +func (o *I2S_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *I2S_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Interrupt Controller (Core 0) +type INTERRUPT_CORE0_Type struct { + MAC_INTR_MAP volatile.Register32 // 0x0 + MAC_NMI_MAP volatile.Register32 // 0x4 + PWR_INTR_MAP volatile.Register32 // 0x8 + BB_INT_MAP volatile.Register32 // 0xC + BT_MAC_INT_MAP volatile.Register32 // 0x10 + BT_BB_INT_MAP volatile.Register32 // 0x14 + BT_BB_NMI_MAP volatile.Register32 // 0x18 + RWBT_IRQ_MAP volatile.Register32 // 0x1C + RWBLE_IRQ_MAP volatile.Register32 // 0x20 + RWBT_NMI_MAP volatile.Register32 // 0x24 + RWBLE_NMI_MAP volatile.Register32 // 0x28 + I2C_MST_INT_MAP volatile.Register32 // 0x2C + SLC0_INTR_MAP volatile.Register32 // 0x30 + SLC1_INTR_MAP volatile.Register32 // 0x34 + APB_CTRL_INTR_MAP volatile.Register32 // 0x38 + UHCI0_INTR_MAP volatile.Register32 // 0x3C + GPIO_INTERRUPT_PRO_MAP volatile.Register32 // 0x40 + GPIO_INTERRUPT_PRO_NMI_MAP volatile.Register32 // 0x44 + SPI_INTR_1_MAP volatile.Register32 // 0x48 + SPI_INTR_2_MAP volatile.Register32 // 0x4C + I2S1_INT_MAP volatile.Register32 // 0x50 + UART_INTR_MAP volatile.Register32 // 0x54 + UART1_INTR_MAP volatile.Register32 // 0x58 + LEDC_INT_MAP volatile.Register32 // 0x5C + EFUSE_INT_MAP volatile.Register32 // 0x60 + CAN_INT_MAP volatile.Register32 // 0x64 + USB_INTR_MAP volatile.Register32 // 0x68 + RTC_CORE_INTR_MAP volatile.Register32 // 0x6C + RMT_INTR_MAP volatile.Register32 // 0x70 + I2C_EXT0_INTR_MAP volatile.Register32 // 0x74 + TIMER_INT1_MAP volatile.Register32 // 0x78 + TIMER_INT2_MAP volatile.Register32 // 0x7C + TG_T0_INT_MAP volatile.Register32 // 0x80 + TG_WDT_INT_MAP volatile.Register32 // 0x84 + TG1_T0_INT_MAP volatile.Register32 // 0x88 + TG1_WDT_INT_MAP volatile.Register32 // 0x8C + CACHE_IA_INT_MAP volatile.Register32 // 0x90 + SYSTIMER_TARGET0_INT_MAP volatile.Register32 // 0x94 + SYSTIMER_TARGET1_INT_MAP volatile.Register32 // 0x98 + SYSTIMER_TARGET2_INT_MAP volatile.Register32 // 0x9C + SPI_MEM_REJECT_INTR_MAP volatile.Register32 // 0xA0 + ICACHE_PRELOAD_INT_MAP volatile.Register32 // 0xA4 + ICACHE_SYNC_INT_MAP volatile.Register32 // 0xA8 + APB_ADC_INT_MAP volatile.Register32 // 0xAC + DMA_CH0_INT_MAP volatile.Register32 // 0xB0 + DMA_CH1_INT_MAP volatile.Register32 // 0xB4 + DMA_CH2_INT_MAP volatile.Register32 // 0xB8 + RSA_INT_MAP volatile.Register32 // 0xBC + AES_INT_MAP volatile.Register32 // 0xC0 + SHA_INT_MAP volatile.Register32 // 0xC4 + CPU_INTR_FROM_CPU_0_MAP volatile.Register32 // 0xC8 + CPU_INTR_FROM_CPU_1_MAP volatile.Register32 // 0xCC + CPU_INTR_FROM_CPU_2_MAP volatile.Register32 // 0xD0 + CPU_INTR_FROM_CPU_3_MAP volatile.Register32 // 0xD4 + ASSIST_DEBUG_INTR_MAP volatile.Register32 // 0xD8 + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0xDC + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0xE0 + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0xE4 + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0xE8 + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP volatile.Register32 // 0xEC + BACKUP_PMS_VIOLATE_INTR_MAP volatile.Register32 // 0xF0 + CACHE_CORE0_ACS_INT_MAP volatile.Register32 // 0xF4 + INTR_STATUS_REG_0 volatile.Register32 // 0xF8 + INTR_STATUS_REG_1 volatile.Register32 // 0xFC + CLOCK_GATE volatile.Register32 // 0x100 + CPU_INT_ENABLE volatile.Register32 // 0x104 + CPU_INT_TYPE volatile.Register32 // 0x108 + CPU_INT_CLEAR volatile.Register32 // 0x10C + CPU_INT_EIP_STATUS volatile.Register32 // 0x110 + CPU_INT_PRI_0 volatile.Register32 // 0x114 + CPU_INT_PRI_1 volatile.Register32 // 0x118 + CPU_INT_PRI_2 volatile.Register32 // 0x11C + CPU_INT_PRI_3 volatile.Register32 // 0x120 + CPU_INT_PRI_4 volatile.Register32 // 0x124 + CPU_INT_PRI_5 volatile.Register32 // 0x128 + CPU_INT_PRI_6 volatile.Register32 // 0x12C + CPU_INT_PRI_7 volatile.Register32 // 0x130 + CPU_INT_PRI_8 volatile.Register32 // 0x134 + CPU_INT_PRI_9 volatile.Register32 // 0x138 + CPU_INT_PRI_10 volatile.Register32 // 0x13C + CPU_INT_PRI_11 volatile.Register32 // 0x140 + CPU_INT_PRI_12 volatile.Register32 // 0x144 + CPU_INT_PRI_13 volatile.Register32 // 0x148 + CPU_INT_PRI_14 volatile.Register32 // 0x14C + CPU_INT_PRI_15 volatile.Register32 // 0x150 + CPU_INT_PRI_16 volatile.Register32 // 0x154 + CPU_INT_PRI_17 volatile.Register32 // 0x158 + CPU_INT_PRI_18 volatile.Register32 // 0x15C + CPU_INT_PRI_19 volatile.Register32 // 0x160 + CPU_INT_PRI_20 volatile.Register32 // 0x164 + CPU_INT_PRI_21 volatile.Register32 // 0x168 + CPU_INT_PRI_22 volatile.Register32 // 0x16C + CPU_INT_PRI_23 volatile.Register32 // 0x170 + CPU_INT_PRI_24 volatile.Register32 // 0x174 + CPU_INT_PRI_25 volatile.Register32 // 0x178 + CPU_INT_PRI_26 volatile.Register32 // 0x17C + CPU_INT_PRI_27 volatile.Register32 // 0x180 + CPU_INT_PRI_28 volatile.Register32 // 0x184 + CPU_INT_PRI_29 volatile.Register32 // 0x188 + CPU_INT_PRI_30 volatile.Register32 // 0x18C + CPU_INT_PRI_31 volatile.Register32 // 0x190 + CPU_INT_THRESH volatile.Register32 // 0x194 + _ [1636]byte + INTERRUPT_REG_DATE volatile.Register32 // 0x7FC +} + +// INTERRUPT_CORE0.MAC_INTR_MAP: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetMAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetMAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.MAC_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.MAC_NMI_MAP: mac nmi_intr map register +func (o *INTERRUPT_CORE0_Type) SetMAC_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.MAC_NMI_MAP.Reg, volatile.LoadUint32(&o.MAC_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetMAC_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.MAC_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PWR_INTR_MAP: pwr intr map register +func (o *INTERRUPT_CORE0_Type) SetPWR_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWR_INTR_MAP.Reg, volatile.LoadUint32(&o.PWR_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPWR_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWR_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BB_INT_MAP: bb intr map register +func (o *INTERRUPT_CORE0_Type) SetBB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BB_INT_MAP.Reg, volatile.LoadUint32(&o.BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BT_MAC_INT_MAP: bt intr map register +func (o *INTERRUPT_CORE0_Type) SetBT_MAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BT_MAC_INT_MAP.Reg, volatile.LoadUint32(&o.BT_MAC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBT_MAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BT_MAC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BT_BB_INT_MAP: bb_bt intr map register +func (o *INTERRUPT_CORE0_Type) SetBT_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_INT_MAP.Reg, volatile.LoadUint32(&o.BT_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBT_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BT_BB_NMI_MAP: bb_bt_nmi intr map register +func (o *INTERRUPT_CORE0_Type) SetBT_BB_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_NMI_MAP.Reg, volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBT_BB_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RWBT_IRQ_MAP: rwbt intr map register +func (o *INTERRUPT_CORE0_Type) SetRWBT_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.RWBT_IRQ_MAP.Reg, volatile.LoadUint32(&o.RWBT_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRWBT_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.RWBT_IRQ_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RWBLE_IRQ_MAP: rwble intr map register +func (o *INTERRUPT_CORE0_Type) SetRWBLE_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.RWBLE_IRQ_MAP.Reg, volatile.LoadUint32(&o.RWBLE_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRWBLE_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.RWBLE_IRQ_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RWBT_NMI_MAP: rwbt_nmi intr map register +func (o *INTERRUPT_CORE0_Type) SetRWBT_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.RWBT_NMI_MAP.Reg, volatile.LoadUint32(&o.RWBT_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRWBT_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.RWBT_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RWBLE_NMI_MAP: rwble_nmi intr map register +func (o *INTERRUPT_CORE0_Type) SetRWBLE_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.RWBLE_NMI_MAP.Reg, volatile.LoadUint32(&o.RWBLE_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRWBLE_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.RWBLE_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2C_MST_INT_MAP: i2c intr map register +func (o *INTERRUPT_CORE0_Type) SetI2C_MST_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_MST_INT_MAP.Reg, volatile.LoadUint32(&o.I2C_MST_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2C_MST_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_MST_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SLC0_INTR_MAP: slc0 intr map register +func (o *INTERRUPT_CORE0_Type) SetSLC0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SLC0_INTR_MAP.Reg, volatile.LoadUint32(&o.SLC0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSLC0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SLC0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SLC1_INTR_MAP: slc1 intr map register +func (o *INTERRUPT_CORE0_Type) SetSLC1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SLC1_INTR_MAP.Reg, volatile.LoadUint32(&o.SLC1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSLC1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SLC1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.APB_CTRL_INTR_MAP: apb_ctrl intr map register +func (o *INTERRUPT_CORE0_Type) SetAPB_CTRL_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APB_CTRL_INTR_MAP.Reg, volatile.LoadUint32(&o.APB_CTRL_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetAPB_CTRL_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APB_CTRL_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UHCI0_INTR_MAP: uchi0 intr map register +func (o *INTERRUPT_CORE0_Type) SetUHCI0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UHCI0_INTR_MAP.Reg, volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUHCI0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.GPIO_INTERRUPT_PRO_MAP: gpio intr map register +func (o *INTERRUPT_CORE0_Type) SetGPIO_INTERRUPT_PRO_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetGPIO_INTERRUPT_PRO_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.GPIO_INTERRUPT_PRO_NMI_MAP: gpio_pro intr map register +func (o *INTERRUPT_CORE0_Type) SetGPIO_INTERRUPT_PRO_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetGPIO_INTERRUPT_PRO_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_INTR_1_MAP: gpio_pro_nmi intr map register +func (o *INTERRUPT_CORE0_Type) SetSPI_INTR_1_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_1_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_INTR_1_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_INTR_2_MAP: spi1 intr map register +func (o *INTERRUPT_CORE0_Type) SetSPI_INTR_2_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_2_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_INTR_2_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2S1_INT_MAP: spi2 intr map register +func (o *INTERRUPT_CORE0_Type) SetI2S1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.I2S1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2S1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UART_INTR_MAP: i2s1 intr map register +func (o *INTERRUPT_CORE0_Type) SetUART_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART_INTR_MAP.Reg, volatile.LoadUint32(&o.UART_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUART_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UART1_INTR_MAP: uart1 intr map register +func (o *INTERRUPT_CORE0_Type) SetUART1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART1_INTR_MAP.Reg, volatile.LoadUint32(&o.UART1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUART1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.LEDC_INT_MAP: ledc intr map register +func (o *INTERRUPT_CORE0_Type) SetLEDC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.LEDC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetLEDC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LEDC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.EFUSE_INT_MAP: efuse intr map register +func (o *INTERRUPT_CORE0_Type) SetEFUSE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.EFUSE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetEFUSE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.EFUSE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CAN_INT_MAP: can intr map register +func (o *INTERRUPT_CORE0_Type) SetCAN_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CAN_INT_MAP.Reg, volatile.LoadUint32(&o.CAN_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCAN_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CAN_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.USB_INTR_MAP: usb intr map register +func (o *INTERRUPT_CORE0_Type) SetUSB_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.USB_INTR_MAP.Reg, volatile.LoadUint32(&o.USB_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUSB_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.USB_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RTC_CORE_INTR_MAP: rtc intr map register +func (o *INTERRUPT_CORE0_Type) SetRTC_CORE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RTC_CORE_INTR_MAP.Reg, volatile.LoadUint32(&o.RTC_CORE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRTC_CORE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RTC_CORE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RMT_INTR_MAP: rmt intr map register +func (o *INTERRUPT_CORE0_Type) SetRMT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RMT_INTR_MAP.Reg, volatile.LoadUint32(&o.RMT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRMT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RMT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2C_EXT0_INTR_MAP: i2c intr map register +func (o *INTERRUPT_CORE0_Type) SetI2C_EXT0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_EXT0_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2C_EXT0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TIMER_INT1_MAP: timer1 intr map register +func (o *INTERRUPT_CORE0_Type) SetTIMER_INT1_MAP(value uint32) { + volatile.StoreUint32(&o.TIMER_INT1_MAP.Reg, volatile.LoadUint32(&o.TIMER_INT1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTIMER_INT1_MAP() uint32 { + return volatile.LoadUint32(&o.TIMER_INT1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TIMER_INT2_MAP: timer2 intr map register +func (o *INTERRUPT_CORE0_Type) SetTIMER_INT2_MAP(value uint32) { + volatile.StoreUint32(&o.TIMER_INT2_MAP.Reg, volatile.LoadUint32(&o.TIMER_INT2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTIMER_INT2_MAP() uint32 { + return volatile.LoadUint32(&o.TIMER_INT2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG_T0_INT_MAP: tg to intr map register +func (o *INTERRUPT_CORE0_Type) SetTG_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TG_T0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_T0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG_WDT_INT_MAP: tg wdt intr map register +func (o *INTERRUPT_CORE0_Type) SetTG_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TG_WDT_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_WDT_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG1_T0_INT_MAP: tg1 to intr map register +func (o *INTERRUPT_CORE0_Type) SetTG1_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TG1_T0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG1_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_T0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG1_WDT_INT_MAP: tg1 wdt intr map register +func (o *INTERRUPT_CORE0_Type) SetTG1_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TG1_WDT_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG1_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_WDT_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CACHE_IA_INT_MAP: cache ia intr map register +func (o *INTERRUPT_CORE0_Type) SetCACHE_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCACHE_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_IA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SYSTIMER_TARGET0_INT_MAP: systimer intr map register +func (o *INTERRUPT_CORE0_Type) SetSYSTIMER_TARGET0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSYSTIMER_TARGET0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SYSTIMER_TARGET1_INT_MAP: systimer target1 intr map register +func (o *INTERRUPT_CORE0_Type) SetSYSTIMER_TARGET1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSYSTIMER_TARGET1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SYSTIMER_TARGET2_INT_MAP: systimer target2 intr map register +func (o *INTERRUPT_CORE0_Type) SetSYSTIMER_TARGET2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSYSTIMER_TARGET2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_MEM_REJECT_INTR_MAP: spi mem reject intr map register +func (o *INTERRUPT_CORE0_Type) SetSPI_MEM_REJECT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg, volatile.LoadUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_MEM_REJECT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ICACHE_PRELOAD_INT_MAP: icache perload intr map register +func (o *INTERRUPT_CORE0_Type) SetICACHE_PRELOAD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetICACHE_PRELOAD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ICACHE_SYNC_INT_MAP: icache sync intr map register +func (o *INTERRUPT_CORE0_Type) SetICACHE_SYNC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_INT_MAP.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetICACHE_SYNC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.APB_ADC_INT_MAP: adc intr map register +func (o *INTERRUPT_CORE0_Type) SetAPB_ADC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APB_ADC_INT_MAP.Reg, volatile.LoadUint32(&o.APB_ADC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetAPB_ADC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APB_ADC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_CH0_INT_MAP: dma ch0 intr map register +func (o *INTERRUPT_CORE0_Type) SetDMA_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_CH0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_CH0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_CH1_INT_MAP: dma ch1 intr map register +func (o *INTERRUPT_CORE0_Type) SetDMA_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_CH1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_CH1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_CH2_INT_MAP: dma ch2 intr map register +func (o *INTERRUPT_CORE0_Type) SetDMA_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_CH2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_CH2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RSA_INT_MAP: rsa intr map register +func (o *INTERRUPT_CORE0_Type) SetRSA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.RSA_INT_MAP.Reg, volatile.LoadUint32(&o.RSA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRSA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.RSA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.AES_INT_MAP: aes intr map register +func (o *INTERRUPT_CORE0_Type) SetAES_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AES_INT_MAP.Reg, volatile.LoadUint32(&o.AES_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetAES_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AES_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SHA_INT_MAP: sha intr map register +func (o *INTERRUPT_CORE0_Type) SetSHA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SHA_INT_MAP.Reg, volatile.LoadUint32(&o.SHA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSHA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SHA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_0_MAP: cpu from cpu 0 intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_1_MAP: cpu from cpu 0 intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_2_MAP: cpu from cpu 1 intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_3_MAP: cpu from cpu 3 intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ASSIST_DEBUG_INTR_MAP: assist debug intr map register +func (o *INTERRUPT_CORE0_Type) SetASSIST_DEBUG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetASSIST_DEBUG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: dma pms violatile intr map register +func (o *INTERRUPT_CORE0_Type) SetDMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: iram0 pms violatile intr map register +func (o *INTERRUPT_CORE0_Type) SetCORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BACKUP_PMS_VIOLATE_INTR_MAP: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetBACKUP_PMS_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BACKUP_PMS_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.BACKUP_PMS_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBACKUP_PMS_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BACKUP_PMS_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CACHE_CORE0_ACS_INT_MAP: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCACHE_CORE0_ACS_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCACHE_CORE0_ACS_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.INTR_STATUS_REG_0: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetINTR_STATUS_REG_0(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_0.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetINTR_STATUS_REG_0() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_0.Reg) +} + +// INTERRUPT_CORE0.INTR_STATUS_REG_1: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetINTR_STATUS_REG_1(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_1.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetINTR_STATUS_REG_1() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_1.Reg) +} + +// INTERRUPT_CORE0.CLOCK_GATE: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCLOCK_GATE_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCLOCK_GATE_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// INTERRUPT_CORE0.CPU_INT_ENABLE: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.CPU_INT_ENABLE.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_ENABLE() uint32 { + return volatile.LoadUint32(&o.CPU_INT_ENABLE.Reg) +} + +// INTERRUPT_CORE0.CPU_INT_TYPE: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CPU_INT_TYPE.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_TYPE() uint32 { + return volatile.LoadUint32(&o.CPU_INT_TYPE.Reg) +} + +// INTERRUPT_CORE0.CPU_INT_CLEAR: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.CPU_INT_CLEAR.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_CLEAR() uint32 { + return volatile.LoadUint32(&o.CPU_INT_CLEAR.Reg) +} + +// INTERRUPT_CORE0.CPU_INT_EIP_STATUS: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_EIP_STATUS(value uint32) { + volatile.StoreUint32(&o.CPU_INT_EIP_STATUS.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_EIP_STATUS() uint32 { + return volatile.LoadUint32(&o.CPU_INT_EIP_STATUS.Reg) +} + +// INTERRUPT_CORE0.CPU_INT_PRI_0: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_0_CPU_PRI_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_0.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_0.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_0_CPU_PRI_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_0.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_1: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_1_CPU_PRI_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_1.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_1.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_1_CPU_PRI_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_1.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_2: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_2_CPU_PRI_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_2.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_2.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_2_CPU_PRI_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_2.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_3: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_3_CPU_PRI_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_3.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_3.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_3_CPU_PRI_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_3.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_4: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_4_CPU_PRI_4_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_4.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_4.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_4_CPU_PRI_4_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_4.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_5: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_5_CPU_PRI_5_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_5.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_5.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_5_CPU_PRI_5_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_5.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_6: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_6_CPU_PRI_6_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_6.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_6.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_6_CPU_PRI_6_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_6.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_7: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_7_CPU_PRI_7_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_7.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_7.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_7_CPU_PRI_7_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_7.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_8: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_8_CPU_PRI_8_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_8.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_8.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_8_CPU_PRI_8_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_8.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_9: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_9_CPU_PRI_9_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_9.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_9.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_9_CPU_PRI_9_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_9.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_10: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_10_CPU_PRI_10_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_10.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_10.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_10_CPU_PRI_10_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_10.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_11: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_11_CPU_PRI_11_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_11.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_11.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_11_CPU_PRI_11_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_11.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_12: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_12_CPU_PRI_12_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_12.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_12.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_12_CPU_PRI_12_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_12.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_13: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_13_CPU_PRI_13_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_13.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_13.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_13_CPU_PRI_13_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_13.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_14: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_14_CPU_PRI_14_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_14.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_14.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_14_CPU_PRI_14_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_14.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_15: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_15_CPU_PRI_15_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_15.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_15.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_15_CPU_PRI_15_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_15.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_16: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_16_CPU_PRI_16_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_16.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_16.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_16_CPU_PRI_16_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_16.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_17: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_17_CPU_PRI_17_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_17.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_17.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_17_CPU_PRI_17_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_17.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_18: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_18_CPU_PRI_18_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_18.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_18.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_18_CPU_PRI_18_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_18.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_19: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_19_CPU_PRI_19_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_19.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_19.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_19_CPU_PRI_19_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_19.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_20: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_20_CPU_PRI_20_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_20.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_20.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_20_CPU_PRI_20_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_20.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_21: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_21_CPU_PRI_21_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_21.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_21.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_21_CPU_PRI_21_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_21.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_22: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_22_CPU_PRI_22_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_22.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_22.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_22_CPU_PRI_22_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_22.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_23: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_23_CPU_PRI_23_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_23.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_23.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_23_CPU_PRI_23_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_23.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_24: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_24_CPU_PRI_24_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_24.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_24.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_24_CPU_PRI_24_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_24.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_25: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_25_CPU_PRI_25_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_25.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_25.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_25_CPU_PRI_25_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_25.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_26: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_26_CPU_PRI_26_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_26.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_26.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_26_CPU_PRI_26_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_26.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_27: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_27_CPU_PRI_27_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_27.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_27.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_27_CPU_PRI_27_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_27.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_28: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_28_CPU_PRI_28_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_28.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_28.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_28_CPU_PRI_28_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_28.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_29: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_29_CPU_PRI_29_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_29.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_29.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_29_CPU_PRI_29_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_29.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_30: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_30_CPU_PRI_30_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_30.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_30.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_30_CPU_PRI_30_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_30.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_PRI_31: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_PRI_31_CPU_PRI_31_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_31.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_31.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_PRI_31_CPU_PRI_31_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_31.Reg) & 0xf +} + +// INTERRUPT_CORE0.CPU_INT_THRESH: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetCPU_INT_THRESH(value uint32) { + volatile.StoreUint32(&o.CPU_INT_THRESH.Reg, volatile.LoadUint32(&o.CPU_INT_THRESH.Reg)&^(0xf)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INT_THRESH() uint32 { + return volatile.LoadUint32(&o.CPU_INT_THRESH.Reg) & 0xf +} + +// INTERRUPT_CORE0.INTERRUPT_REG_DATE: mac intr map register +func (o *INTERRUPT_CORE0_Type) SetINTERRUPT_REG_DATE(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_REG_DATE.Reg, volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *INTERRUPT_CORE0_Type) GetINTERRUPT_REG_DATE() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg) & 0xfffffff +} + +// Input/Output Multiplexer +type IO_MUX_Type struct { + PIN_CTRL volatile.Register32 // 0x0 + GPIO0 volatile.Register32 // 0x4 + GPIO1 volatile.Register32 // 0x8 + GPIO2 volatile.Register32 // 0xC + GPIO3 volatile.Register32 // 0x10 + GPIO4 volatile.Register32 // 0x14 + GPIO5 volatile.Register32 // 0x18 + GPIO6 volatile.Register32 // 0x1C + GPIO7 volatile.Register32 // 0x20 + GPIO8 volatile.Register32 // 0x24 + GPIO9 volatile.Register32 // 0x28 + GPIO10 volatile.Register32 // 0x2C + GPIO11 volatile.Register32 // 0x30 + GPIO12 volatile.Register32 // 0x34 + GPIO13 volatile.Register32 // 0x38 + GPIO14 volatile.Register32 // 0x3C + GPIO15 volatile.Register32 // 0x40 + GPIO16 volatile.Register32 // 0x44 + GPIO17 volatile.Register32 // 0x48 + GPIO18 volatile.Register32 // 0x4C + GPIO19 volatile.Register32 // 0x50 + GPIO20 volatile.Register32 // 0x54 + GPIO21 volatile.Register32 // 0x58 + _ [160]byte + DATE volatile.Register32 // 0xFC +} + +// IO_MUX.PIN_CTRL: Clock Output Configuration Register +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT1(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf)|value) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT1() uint32 { + return volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT2(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf0)|value<<4) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT2() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf0) >> 4 +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT3(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf00)|value<<8) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT3() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf00) >> 8 +} + +// IO_MUX.GPIO0: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO1: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO2: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO3: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO4: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO5: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO6: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO7: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO8: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO8_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO8.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO8_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO8_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO9: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO9_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO9.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO9_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO9_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO10: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO10_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO10.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO10_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO10_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO11: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO11_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO11.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO11_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO11_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO12: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO12_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO12.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO12_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO12_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO13: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO13_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO13.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO13_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO13_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO14: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO14_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO14.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO14_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO14_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO15: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO15_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO15.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO15_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO15_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO15_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO15_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO16: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO16_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO16.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO16_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO16_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO16_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO16_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO17: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO17_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO17.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO17_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO17_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO17_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO17_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO18: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO18_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO18.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO18_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO18_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO18_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO18_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO19: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO19_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO19.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO19_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO19_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO20: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO20_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO20.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO20_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO20_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO21: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO21_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO21.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO21_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO21_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8000) >> 15 +} + +// IO_MUX.DATE: IO MUX Version Control Register +func (o *IO_MUX_Type) SetDATE_REG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *IO_MUX_Type) GetDATE_REG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LED Control PWM (Pulse Width Modulation) +type LEDC_Type struct { + CH0_CONF0 volatile.Register32 // 0x0 + CH0_HPOINT volatile.Register32 // 0x4 + CH0_DUTY volatile.Register32 // 0x8 + CH0_CONF1 volatile.Register32 // 0xC + CH0_DUTY_R volatile.Register32 // 0x10 + CH1_CONF0 volatile.Register32 // 0x14 + CH1_HPOINT volatile.Register32 // 0x18 + CH1_DUTY volatile.Register32 // 0x1C + CH1_CONF1 volatile.Register32 // 0x20 + CH1_DUTY_R volatile.Register32 // 0x24 + CH2_CONF0 volatile.Register32 // 0x28 + CH2_HPOINT volatile.Register32 // 0x2C + CH2_DUTY volatile.Register32 // 0x30 + CH2_CONF1 volatile.Register32 // 0x34 + CH2_DUTY_R volatile.Register32 // 0x38 + CH3_CONF0 volatile.Register32 // 0x3C + CH3_HPOINT volatile.Register32 // 0x40 + CH3_DUTY volatile.Register32 // 0x44 + CH3_CONF1 volatile.Register32 // 0x48 + CH3_DUTY_R volatile.Register32 // 0x4C + CH4_CONF0 volatile.Register32 // 0x50 + CH4_HPOINT volatile.Register32 // 0x54 + CH4_DUTY volatile.Register32 // 0x58 + CH4_CONF1 volatile.Register32 // 0x5C + CH4_DUTY_R volatile.Register32 // 0x60 + CH5_CONF0 volatile.Register32 // 0x64 + CH5_HPOINT volatile.Register32 // 0x68 + CH5_DUTY volatile.Register32 // 0x6C + CH5_CONF1 volatile.Register32 // 0x70 + CH5_DUTY_R volatile.Register32 // 0x74 + _ [40]byte + TIMER0_CONF volatile.Register32 // 0xA0 + TIMER0_VALUE volatile.Register32 // 0xA4 + TIMER1_CONF volatile.Register32 // 0xA8 + TIMER1_VALUE volatile.Register32 // 0xAC + TIMER2_CONF volatile.Register32 // 0xB0 + TIMER2_VALUE volatile.Register32 // 0xB4 + TIMER3_CONF volatile.Register32 // 0xB8 + TIMER3_VALUE volatile.Register32 // 0xBC + INT_RAW volatile.Register32 // 0xC0 + INT_ST volatile.Register32 // 0xC4 + INT_ENA volatile.Register32 // 0xC8 + INT_CLR volatile.Register32 // 0xCC + CONF volatile.Register32 // 0xD0 + _ [40]byte + DATE volatile.Register32 // 0xFC +} + +// LEDC.CH0_CONF0: LEDC_LSCH%s_CONF%s. +func (o *LEDC_Type) SetCH0_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH0_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH0_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH0_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH0_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH0_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH0_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH0_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH0_HPOINT: LEDC_LSCH%s_HPOINT. +func (o *LEDC_Type) SetCH0_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH0_HPOINT.Reg, volatile.LoadUint32(&o.CH0_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH0_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH0_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH0_DUTY: LEDC_LSCH%s_DUTY. +func (o *LEDC_Type) SetCH0_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY.Reg, volatile.LoadUint32(&o.CH0_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH0_CONF1: LEDC_LSCH%s_CONF1. +func (o *LEDC_Type) SetCH0_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH0_DUTY_R: LEDC_LSCH%s_DUTY_R. +func (o *LEDC_Type) SetCH0_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY_R.Reg, volatile.LoadUint32(&o.CH0_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH1_CONF0: LEDC_LSCH%s_CONF%s. +func (o *LEDC_Type) SetCH1_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH1_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH1_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH1_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH1_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH1_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH1_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH1_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH1_HPOINT: LEDC_LSCH%s_HPOINT. +func (o *LEDC_Type) SetCH1_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH1_HPOINT.Reg, volatile.LoadUint32(&o.CH1_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH1_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH1_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH1_DUTY: LEDC_LSCH%s_DUTY. +func (o *LEDC_Type) SetCH1_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY.Reg, volatile.LoadUint32(&o.CH1_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH1_CONF1: LEDC_LSCH%s_CONF1. +func (o *LEDC_Type) SetCH1_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH1_DUTY_R: LEDC_LSCH%s_DUTY_R. +func (o *LEDC_Type) SetCH1_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY_R.Reg, volatile.LoadUint32(&o.CH1_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH2_CONF0: LEDC_LSCH%s_CONF%s. +func (o *LEDC_Type) SetCH2_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH2_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH2_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH2_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH2_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH2_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH2_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH2_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH2_HPOINT: LEDC_LSCH%s_HPOINT. +func (o *LEDC_Type) SetCH2_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH2_HPOINT.Reg, volatile.LoadUint32(&o.CH2_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH2_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH2_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH2_DUTY: LEDC_LSCH%s_DUTY. +func (o *LEDC_Type) SetCH2_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY.Reg, volatile.LoadUint32(&o.CH2_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH2_CONF1: LEDC_LSCH%s_CONF1. +func (o *LEDC_Type) SetCH2_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH2_DUTY_R: LEDC_LSCH%s_DUTY_R. +func (o *LEDC_Type) SetCH2_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY_R.Reg, volatile.LoadUint32(&o.CH2_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH3_CONF0: LEDC_LSCH%s_CONF%s. +func (o *LEDC_Type) SetCH3_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH3_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH3_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH3_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH3_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH3_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH3_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH3_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH3_HPOINT: LEDC_LSCH%s_HPOINT. +func (o *LEDC_Type) SetCH3_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH3_HPOINT.Reg, volatile.LoadUint32(&o.CH3_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH3_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH3_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH3_DUTY: LEDC_LSCH%s_DUTY. +func (o *LEDC_Type) SetCH3_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY.Reg, volatile.LoadUint32(&o.CH3_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH3_CONF1: LEDC_LSCH%s_CONF1. +func (o *LEDC_Type) SetCH3_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH3_DUTY_R: LEDC_LSCH%s_DUTY_R. +func (o *LEDC_Type) SetCH3_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY_R.Reg, volatile.LoadUint32(&o.CH3_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH4_CONF0: LEDC_LSCH%s_CONF%s. +func (o *LEDC_Type) SetCH4_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH4_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH4_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH4_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH4_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH4_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH4_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH4_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH4_HPOINT: LEDC_LSCH%s_HPOINT. +func (o *LEDC_Type) SetCH4_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH4_HPOINT.Reg, volatile.LoadUint32(&o.CH4_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH4_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH4_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH4_DUTY: LEDC_LSCH%s_DUTY. +func (o *LEDC_Type) SetCH4_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY.Reg, volatile.LoadUint32(&o.CH4_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH4_CONF1: LEDC_LSCH%s_CONF1. +func (o *LEDC_Type) SetCH4_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH4_DUTY_R: LEDC_LSCH%s_DUTY_R. +func (o *LEDC_Type) SetCH4_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY_R.Reg, volatile.LoadUint32(&o.CH4_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH5_CONF0: LEDC_LSCH%s_CONF%s. +func (o *LEDC_Type) SetCH5_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH5_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH5_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH5_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH5_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH5_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH5_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH5_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH5_HPOINT: LEDC_LSCH%s_HPOINT. +func (o *LEDC_Type) SetCH5_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH5_HPOINT.Reg, volatile.LoadUint32(&o.CH5_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH5_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH5_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH5_DUTY: LEDC_LSCH%s_DUTY. +func (o *LEDC_Type) SetCH5_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY.Reg, volatile.LoadUint32(&o.CH5_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH5_CONF1: LEDC_LSCH%s_CONF1. +func (o *LEDC_Type) SetCH5_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH5_DUTY_R: LEDC_LSCH%s_DUTY_R. +func (o *LEDC_Type) SetCH5_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY_R.Reg, volatile.LoadUint32(&o.CH5_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.TIMER0_CONF: LEDC_LSTIMER%s_CONF. +func (o *LEDC_Type) SetTIMER0_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER0_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER0_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER0_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER0_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER0_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER0_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER0_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER0_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER0_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER0_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER0_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER0_VALUE: LEDC_LSTIMER%s_VALUE. +func (o *LEDC_Type) SetTIMER0_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER0_VALUE.Reg, volatile.LoadUint32(&o.TIMER0_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER0_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER0_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER1_CONF: LEDC_LSTIMER%s_CONF. +func (o *LEDC_Type) SetTIMER1_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER1_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER1_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER1_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER1_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER1_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER1_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER1_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER1_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER1_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER1_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER1_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER1_VALUE: LEDC_LSTIMER%s_VALUE. +func (o *LEDC_Type) SetTIMER1_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER1_VALUE.Reg, volatile.LoadUint32(&o.TIMER1_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER1_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER1_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER2_CONF: LEDC_LSTIMER%s_CONF. +func (o *LEDC_Type) SetTIMER2_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER2_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER2_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER2_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER2_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER2_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER2_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER2_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER2_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER2_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER2_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER2_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER2_VALUE: LEDC_LSTIMER%s_VALUE. +func (o *LEDC_Type) SetTIMER2_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER2_VALUE.Reg, volatile.LoadUint32(&o.TIMER2_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER2_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER2_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER3_CONF: LEDC_LSTIMER%s_CONF. +func (o *LEDC_Type) SetTIMER3_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER3_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER3_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER3_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER3_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER3_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER3_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER3_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER3_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER3_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER3_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER3_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER3_VALUE: LEDC_LSTIMER%s_VALUE. +func (o *LEDC_Type) SetTIMER3_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER3_VALUE.Reg, volatile.LoadUint32(&o.TIMER3_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER3_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER3_VALUE.Reg) & 0x3fff +} + +// LEDC.INT_RAW: LEDC_INT_RAW. +func (o *LEDC_Type) SetINT_RAW_LSTIMER0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_RAW_LSTIMER0_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_RAW_LSTIMER1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_RAW_LSTIMER1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_RAW_LSTIMER2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_RAW_LSTIMER2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_RAW_LSTIMER3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_RAW_LSTIMER3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_LSCH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_LSCH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_LSCH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_LSCH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_LSCH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_LSCH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_LSCH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_LSCH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_LSCH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_LSCH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_LSCH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_LSCH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} + +// LEDC.INT_ST: LEDC_INT_ST. +func (o *LEDC_Type) SetINT_ST_LSTIMER0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ST_LSTIMER0_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ST_LSTIMER1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ST_LSTIMER1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ST_LSTIMER2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ST_LSTIMER2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ST_LSTIMER3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ST_LSTIMER3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_LSCH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_LSCH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_LSCH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_LSCH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_LSCH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_LSCH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_LSCH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_LSCH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_LSCH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_LSCH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_LSCH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_LSCH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_LSCH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_LSCH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} + +// LEDC.INT_ENA: LEDC_INT_ENA. +func (o *LEDC_Type) SetINT_ENA_LSTIMER0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ENA_LSTIMER0_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ENA_LSTIMER1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ENA_LSTIMER1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ENA_LSTIMER2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ENA_LSTIMER2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ENA_LSTIMER3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ENA_LSTIMER3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_LSCH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_LSCH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_LSCH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_LSCH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_LSCH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_LSCH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_LSCH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_LSCH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_LSCH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_LSCH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_LSCH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_LSCH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} + +// LEDC.INT_CLR: LEDC_INT_CLR. +func (o *LEDC_Type) SetINT_CLR_LSTIMER0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_CLR_LSTIMER0_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_CLR_LSTIMER1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_CLR_LSTIMER1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_CLR_LSTIMER2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_CLR_LSTIMER2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_CLR_LSTIMER3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_CLR_LSTIMER3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_LSCH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_LSCH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_LSCH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_LSCH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_LSCH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_LSCH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_LSCH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_LSCH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_LSCH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_LSCH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_LSCH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_LSCH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} + +// LEDC.CONF: LEDC_CONF. +func (o *LEDC_Type) SetCONF_APB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCONF_APB_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x3 +} +func (o *LEDC_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// LEDC.DATE: LEDC_DATE. +func (o *LEDC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *LEDC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Remote Control +type RMT_Type struct { + CH0DATA volatile.Register32 // 0x0 + CH1DATA volatile.Register32 // 0x4 + CH2DATA volatile.Register32 // 0x8 + CH3DATA volatile.Register32 // 0xC + CH0_TX_CONF0 volatile.Register32 // 0x10 + CH1_TX_CONF0 volatile.Register32 // 0x14 + CH2_RX_CONF0 volatile.Register32 // 0x18 + CH2_RX_CONF1 volatile.Register32 // 0x1C + CH3_RX_CONF0 volatile.Register32 // 0x20 + CH3_RX_CONF1 volatile.Register32 // 0x24 + CH0_TX_STATUS volatile.Register32 // 0x28 + CH1_TX_STATUS volatile.Register32 // 0x2C + CH2_RX_STATUS volatile.Register32 // 0x30 + CH3_RX_STATUS volatile.Register32 // 0x34 + INT_RAW volatile.Register32 // 0x38 + INT_ST volatile.Register32 // 0x3C + INT_ENA volatile.Register32 // 0x40 + INT_CLR volatile.Register32 // 0x44 + CH0CARRIER_DUTY volatile.Register32 // 0x48 + CH1CARRIER_DUTY volatile.Register32 // 0x4C + CH2_RX_CARRIER_RM volatile.Register32 // 0x50 + CH3_RX_CARRIER_RM volatile.Register32 // 0x54 + CH0_TX_LIM volatile.Register32 // 0x58 + CH1_TX_LIM volatile.Register32 // 0x5C + CH2_RX_LIM volatile.Register32 // 0x60 + CH3_RX_LIM volatile.Register32 // 0x64 + SYS_CONF volatile.Register32 // 0x68 + TX_SIM volatile.Register32 // 0x6C + REF_CNT_RST volatile.Register32 // 0x70 + _ [88]byte + DATE volatile.Register32 // 0xCC +} + +// RMT.CH0DATA: RMT_CH%sDATA_REG. +func (o *RMT_Type) SetCH0DATA(value uint32) { + volatile.StoreUint32(&o.CH0DATA.Reg, value) +} +func (o *RMT_Type) GetCH0DATA() uint32 { + return volatile.LoadUint32(&o.CH0DATA.Reg) +} + +// RMT.CH1DATA: RMT_CH%sDATA_REG. +func (o *RMT_Type) SetCH1DATA(value uint32) { + volatile.StoreUint32(&o.CH1DATA.Reg, value) +} +func (o *RMT_Type) GetCH1DATA() uint32 { + return volatile.LoadUint32(&o.CH1DATA.Reg) +} + +// RMT.CH2DATA: RMT_CH%sDATA_REG. +func (o *RMT_Type) SetCH2DATA(value uint32) { + volatile.StoreUint32(&o.CH2DATA.Reg, value) +} +func (o *RMT_Type) GetCH2DATA() uint32 { + return volatile.LoadUint32(&o.CH2DATA.Reg) +} + +// RMT.CH3DATA: RMT_CH%sDATA_REG. +func (o *RMT_Type) SetCH3DATA(value uint32) { + volatile.StoreUint32(&o.CH3DATA.Reg, value) +} +func (o *RMT_Type) GetCH3DATA() uint32 { + return volatile.LoadUint32(&o.CH3DATA.Reg) +} + +// RMT.CH0_TX_CONF0: RMT_CH%sCONF%s_REG. +func (o *RMT_Type) SetCH0_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH0_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH0_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH0_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH0_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH0_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH0_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH0_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH0_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH0_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH0_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x70000)|value<<16) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x70000) >> 16 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH0_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH0_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH1_TX_CONF0: RMT_CH%sCONF%s_REG. +func (o *RMT_Type) SetCH1_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH1_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH1_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH1_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH1_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH1_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH1_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH1_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH1_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH1_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH1_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x70000)|value<<16) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x70000) >> 16 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH1_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH1_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH2_RX_CONF0: RMT_CH2CONF0_REG. +func (o *RMT_Type) SetCH2_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH2_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH2_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH2_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH2_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x3800000)|value<<23) +} +func (o *RMT_Type) GetCH2_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x3800000) >> 23 +} +func (o *RMT_Type) SetCH2_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH2_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH2_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH2_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH2_RX_CONF1: RMT_CH2CONF1_REG. +func (o *RMT_Type) SetCH2_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH2_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH2_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH2_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH2_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH2_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH2_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH2_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH2_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH2_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH2_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH2_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH2_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH2_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH2_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH2_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH2_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH2_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH3_RX_CONF0: RMT_CH2CONF0_REG. +func (o *RMT_Type) SetCH3_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH3_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH3_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH3_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH3_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x3800000)|value<<23) +} +func (o *RMT_Type) GetCH3_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x3800000) >> 23 +} +func (o *RMT_Type) SetCH3_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH3_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH3_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH3_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH3_RX_CONF1: RMT_CH2CONF1_REG. +func (o *RMT_Type) SetCH3_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH3_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH3_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH3_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH3_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH3_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH3_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH3_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH3_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH3_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH3_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH3_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH3_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH3_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH3_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH3_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH3_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH3_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH0_TX_STATUS: RMT_CH%sSTATUS_REG. +func (o *RMT_Type) SetCH0_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0xe00)|value<<9) +} +func (o *RMT_Type) GetCH0_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0xe00) >> 9 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH0_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH0_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0xff000000)|value<<24) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0xff000000) >> 24 +} + +// RMT.CH1_TX_STATUS: RMT_CH%sSTATUS_REG. +func (o *RMT_Type) SetCH1_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0xe00)|value<<9) +} +func (o *RMT_Type) GetCH1_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0xe00) >> 9 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH1_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH1_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0xff000000)|value<<24) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0xff000000) >> 24 +} + +// RMT.CH2_RX_STATUS: RMT_CH2STATUS_REG. +func (o *RMT_Type) SetCH2_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH2_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH2_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH2_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH2_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH2_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH2_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH2_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH2_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH2_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH2_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH3_RX_STATUS: RMT_CH2STATUS_REG. +func (o *RMT_Type) SetCH3_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH3_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH3_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH3_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH3_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH3_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH3_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH3_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH3_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH3_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH3_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.INT_RAW: RMT_INT_RAW_REG. +func (o *RMT_Type) SetINT_RAW_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} + +// RMT.INT_ST: RMT_INT_ST_REG. +func (o *RMT_Type) SetINT_ST_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} + +// RMT.INT_ENA: RMT_INT_ENA_REG. +func (o *RMT_Type) SetINT_ENA_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} + +// RMT.INT_CLR: RMT_INT_CLR_REG. +func (o *RMT_Type) SetINT_CLR_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} + +// RMT.CH0CARRIER_DUTY: RMT_CH%sCARRIER_DUTY_REG. +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1CARRIER_DUTY: RMT_CH%sCARRIER_DUTY_REG. +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH2_RX_CARRIER_RM: RMT_CH2_RX_CARRIER_RM_REG. +func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH3_RX_CARRIER_RM: RMT_CH2_RX_CARRIER_RM_REG. +func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_TX_LIM: RMT_CH%s_TX_LIM_REG. +func (o *RMT_Type) SetCH0_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x100000) >> 20 +} + +// RMT.CH1_TX_LIM: RMT_CH%s_TX_LIM_REG. +func (o *RMT_Type) SetCH1_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x100000) >> 20 +} + +// RMT.CH2_RX_LIM: RMT_CH2_RX_LIM_REG. +func (o *RMT_Type) SetCH2_RX_LIM_RX_LIM(value uint32) { + volatile.StoreUint32(&o.CH2_RX_LIM.Reg, volatile.LoadUint32(&o.CH2_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2_RX_LIM_RX_LIM() uint32 { + return volatile.LoadUint32(&o.CH2_RX_LIM.Reg) & 0x1ff +} + +// RMT.CH3_RX_LIM: RMT_CH2_RX_LIM_REG. +func (o *RMT_Type) SetCH3_RX_LIM_RX_LIM(value uint32) { + volatile.StoreUint32(&o.CH3_RX_LIM.Reg, volatile.LoadUint32(&o.CH3_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3_RX_LIM_RX_LIM() uint32 { + return volatile.LoadUint32(&o.CH3_RX_LIM.Reg) & 0x1ff +} + +// RMT.SYS_CONF: RMT_SYS_CONF_REG. +func (o *RMT_Type) SetSYS_CONF_APB_FIFO_MASK(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetSYS_CONF_APB_FIFO_MASK() uint32 { + return volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetSYS_CONF_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xff0)|value<<4) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xff0) >> 4 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3f000)|value<<12) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3f000) >> 12 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xfc0000)|value<<18) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xfc0000) >> 18 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3000000)|value<<24) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3000000) >> 24 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetSYS_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetSYS_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x80000000) >> 31 +} + +// RMT.TX_SIM: RMT_TX_SIM_REG. +func (o *RMT_Type) SetTX_SIM_TX_SIM_CH0(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_SIM_TX_SIM_CH0() uint32 { + return volatile.LoadUint32(&o.TX_SIM.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_SIM_TX_SIM_CH1(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_SIM_TX_SIM_CH1() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_SIM_TX_SIM_EN(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_SIM_TX_SIM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x4) >> 2 +} + +// RMT.REF_CNT_RST: RMT_REF_CNT_RST_REG. +func (o *RMT_Type) SetREF_CNT_RST_CH0(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetREF_CNT_RST_CH0() uint32 { + return volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x1 +} +func (o *RMT_Type) SetREF_CNT_RST_CH1(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetREF_CNT_RST_CH1() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetREF_CNT_RST_CH2(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetREF_CNT_RST_CH2() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetREF_CNT_RST_CH3(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetREF_CNT_RST_CH3() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x8) >> 3 +} + +// RMT.DATE: RMT_DATE_REG. +func (o *RMT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RMT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Hardware Random Number Generator +type RNG_Type struct { + _ [176]byte + DATA volatile.Register32 // 0xB0 +} + +// RSA (Rivest Shamir Adleman) Accelerator +type RSA_Type struct { + M_MEM [384]volatile.Register8 // 0x0 + _ [128]byte + Z_MEM [384]volatile.Register8 // 0x200 + _ [128]byte + Y_MEM [384]volatile.Register8 // 0x400 + _ [128]byte + X_MEM [384]volatile.Register8 // 0x600 + _ [128]byte + M_PRIME volatile.Register32 // 0x800 + MODE volatile.Register32 // 0x804 + QUERY_CLEAN volatile.Register32 // 0x808 + SET_START_MODEXP volatile.Register32 // 0x80C + SET_START_MODMULT volatile.Register32 // 0x810 + SET_START_MULT volatile.Register32 // 0x814 + QUERY_IDLE volatile.Register32 // 0x818 + INT_CLR volatile.Register32 // 0x81C + CONSTANT_TIME volatile.Register32 // 0x820 + SEARCH_ENABLE volatile.Register32 // 0x824 + SEARCH_POS volatile.Register32 // 0x828 + INT_ENA volatile.Register32 // 0x82C + DATE volatile.Register32 // 0x830 +} + +// RSA.M_PRIME: RSA M_prime register +func (o *RSA_Type) SetM_PRIME(value uint32) { + volatile.StoreUint32(&o.M_PRIME.Reg, value) +} +func (o *RSA_Type) GetM_PRIME() uint32 { + return volatile.LoadUint32(&o.M_PRIME.Reg) +} + +// RSA.MODE: RSA mode register +func (o *RSA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7f)|value) +} +func (o *RSA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7f +} + +// RSA.QUERY_CLEAN: RSA query clean register +func (o *RSA_Type) SetQUERY_CLEAN(value uint32) { + volatile.StoreUint32(&o.QUERY_CLEAN.Reg, volatile.LoadUint32(&o.QUERY_CLEAN.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetQUERY_CLEAN() uint32 { + return volatile.LoadUint32(&o.QUERY_CLEAN.Reg) & 0x1 +} + +// RSA.SET_START_MODEXP: RSA modular exponentiation trigger register. +func (o *RSA_Type) SetSET_START_MODEXP(value uint32) { + volatile.StoreUint32(&o.SET_START_MODEXP.Reg, volatile.LoadUint32(&o.SET_START_MODEXP.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MODEXP() uint32 { + return volatile.LoadUint32(&o.SET_START_MODEXP.Reg) & 0x1 +} + +// RSA.SET_START_MODMULT: RSA modular multiplication trigger register. +func (o *RSA_Type) SetSET_START_MODMULT(value uint32) { + volatile.StoreUint32(&o.SET_START_MODMULT.Reg, volatile.LoadUint32(&o.SET_START_MODMULT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MODMULT() uint32 { + return volatile.LoadUint32(&o.SET_START_MODMULT.Reg) & 0x1 +} + +// RSA.SET_START_MULT: RSA normal multiplication trigger register. +func (o *RSA_Type) SetSET_START_MULT(value uint32) { + volatile.StoreUint32(&o.SET_START_MULT.Reg, volatile.LoadUint32(&o.SET_START_MULT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MULT() uint32 { + return volatile.LoadUint32(&o.SET_START_MULT.Reg) & 0x1 +} + +// RSA.QUERY_IDLE: RSA query idle register +func (o *RSA_Type) SetQUERY_IDLE(value uint32) { + volatile.StoreUint32(&o.QUERY_IDLE.Reg, volatile.LoadUint32(&o.QUERY_IDLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetQUERY_IDLE() uint32 { + return volatile.LoadUint32(&o.QUERY_IDLE.Reg) & 0x1 +} + +// RSA.INT_CLR: RSA interrupt clear register +func (o *RSA_Type) SetINT_CLR_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINT_CLR_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} + +// RSA.CONSTANT_TIME: RSA constant time option register +func (o *RSA_Type) SetCONSTANT_TIME(value uint32) { + volatile.StoreUint32(&o.CONSTANT_TIME.Reg, volatile.LoadUint32(&o.CONSTANT_TIME.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCONSTANT_TIME() uint32 { + return volatile.LoadUint32(&o.CONSTANT_TIME.Reg) & 0x1 +} + +// RSA.SEARCH_ENABLE: RSA search option +func (o *RSA_Type) SetSEARCH_ENABLE(value uint32) { + volatile.StoreUint32(&o.SEARCH_ENABLE.Reg, volatile.LoadUint32(&o.SEARCH_ENABLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSEARCH_ENABLE() uint32 { + return volatile.LoadUint32(&o.SEARCH_ENABLE.Reg) & 0x1 +} + +// RSA.SEARCH_POS: RSA search position configure register +func (o *RSA_Type) SetSEARCH_POS(value uint32) { + volatile.StoreUint32(&o.SEARCH_POS.Reg, volatile.LoadUint32(&o.SEARCH_POS.Reg)&^(0xfff)|value) +} +func (o *RSA_Type) GetSEARCH_POS() uint32 { + return volatile.LoadUint32(&o.SEARCH_POS.Reg) & 0xfff +} + +// RSA.INT_ENA: RSA interrupt enable register +func (o *RSA_Type) SetINT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// RSA.DATE: RSA version control register +func (o *RSA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *RSA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Real-Time Clock Control +type RTC_CNTL_Type struct { + OPTIONS0 volatile.Register32 // 0x0 + SLP_TIMER0 volatile.Register32 // 0x4 + SLP_TIMER1 volatile.Register32 // 0x8 + TIME_UPDATE volatile.Register32 // 0xC + TIME_LOW0 volatile.Register32 // 0x10 + TIME_HIGH0 volatile.Register32 // 0x14 + STATE0 volatile.Register32 // 0x18 + TIMER1 volatile.Register32 // 0x1C + TIMER2 volatile.Register32 // 0x20 + TIMER3 volatile.Register32 // 0x24 + TIMER4 volatile.Register32 // 0x28 + TIMER5 volatile.Register32 // 0x2C + TIMER6 volatile.Register32 // 0x30 + ANA_CONF volatile.Register32 // 0x34 + RESET_STATE volatile.Register32 // 0x38 + WAKEUP_STATE volatile.Register32 // 0x3C + INT_ENA_RTC volatile.Register32 // 0x40 + INT_RAW_RTC volatile.Register32 // 0x44 + INT_ST_RTC volatile.Register32 // 0x48 + INT_CLR_RTC volatile.Register32 // 0x4C + STORE0 volatile.Register32 // 0x50 + STORE1 volatile.Register32 // 0x54 + STORE2 volatile.Register32 // 0x58 + STORE3 volatile.Register32 // 0x5C + EXT_XTL_CONF volatile.Register32 // 0x60 + EXT_WAKEUP_CONF volatile.Register32 // 0x64 + SLP_REJECT_CONF volatile.Register32 // 0x68 + CPU_PERIOD_CONF volatile.Register32 // 0x6C + CLK_CONF volatile.Register32 // 0x70 + SLOW_CLK_CONF volatile.Register32 // 0x74 + SDIO_CONF volatile.Register32 // 0x78 + BIAS_CONF volatile.Register32 // 0x7C + RTC_CNTL volatile.Register32 // 0x80 + PWC volatile.Register32 // 0x84 + DIG_PWC volatile.Register32 // 0x88 + DIG_ISO volatile.Register32 // 0x8C + WDTCONFIG0 volatile.Register32 // 0x90 + WDTCONFIG1 volatile.Register32 // 0x94 + WDTCONFIG2 volatile.Register32 // 0x98 + WDTCONFIG3 volatile.Register32 // 0x9C + WDTCONFIG4 volatile.Register32 // 0xA0 + WDTFEED volatile.Register32 // 0xA4 + WDTWPROTECT volatile.Register32 // 0xA8 + SWD_CONF volatile.Register32 // 0xAC + SWD_WPROTECT volatile.Register32 // 0xB0 + SW_CPU_STALL volatile.Register32 // 0xB4 + STORE4 volatile.Register32 // 0xB8 + STORE5 volatile.Register32 // 0xBC + STORE6 volatile.Register32 // 0xC0 + STORE7 volatile.Register32 // 0xC4 + LOW_POWER_ST volatile.Register32 // 0xC8 + DIAG0 volatile.Register32 // 0xCC + PAD_HOLD volatile.Register32 // 0xD0 + DIG_PAD_HOLD volatile.Register32 // 0xD4 + BROWN_OUT volatile.Register32 // 0xD8 + TIME_LOW1 volatile.Register32 // 0xDC + TIME_HIGH1 volatile.Register32 // 0xE0 + XTAL32K_CLK_FACTOR volatile.Register32 // 0xE4 + XTAL32K_CONF volatile.Register32 // 0xE8 + USB_CONF volatile.Register32 // 0xEC + SLP_REJECT_CAUSE volatile.Register32 // 0xF0 + OPTION1 volatile.Register32 // 0xF4 + SLP_WAKEUP_CAUSE volatile.Register32 // 0xF8 + ULP_CP_TIMER_1 volatile.Register32 // 0xFC + INT_ENA_RTC_W1TS volatile.Register32 // 0x100 + INT_ENA_RTC_W1TC volatile.Register32 // 0x104 + RETENTION_CTRL volatile.Register32 // 0x108 + FIB_SEL volatile.Register32 // 0x10C + GPIO_WAKEUP volatile.Register32 // 0x110 + DBG_SEL volatile.Register32 // 0x114 + DBG_MAP volatile.Register32 // 0x118 + SENSOR_CTRL volatile.Register32 // 0x11C + DBG_SAR_SEL volatile.Register32 // 0x120 + PG_CTRL volatile.Register32 // 0x124 + _ [212]byte + DATE volatile.Register32 // 0x1FC +} + +// RTC_CNTL.OPTIONS0: rtc configure register +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_STALL_APPCPU_C0(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_STALL_APPCPU_C0() uint32 { + return volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_STALL_PROCPU_C0(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0xc)|value<<2) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_STALL_PROCPU_C0() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0xc) >> 2 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_APPCPU_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_APPCPU_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_PROCPU_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_PROCPU_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_EN_WAIT(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x3c000)|value<<14) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_EN_WAIT() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x3c000) >> 14 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_EXT_CTR_SEL(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x700000)|value<<20) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_EXT_CTR_SEL() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x700000) >> 20 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_PLL_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_PLL_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_PLL_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_PLL_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_NORST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_NORST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_SYS_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_TIMER0: rtc configure register +func (o *RTC_CNTL_Type) SetSLP_TIMER0(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER0() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER0.Reg) +} + +// RTC_CNTL.SLP_TIMER1: rtc configure register +func (o *RTC_CNTL_Type) SetSLP_TIMER1_SLP_VAL_HI(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_SLP_VAL_HI() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0xffff +} +func (o *RTC_CNTL_Type) SetSLP_TIMER1_MAIN_TIMER_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_MAIN_TIMER_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0x10000) >> 16 +} + +// RTC_CNTL.TIME_UPDATE: rtc configure register +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_SYS_STALL(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_SYS_STALL() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_XTL_OFF(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_XTL_OFF() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_SYS_RST(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIME_LOW0: rtc configure register +func (o *RTC_CNTL_Type) SetTIME_LOW0(value uint32) { + volatile.StoreUint32(&o.TIME_LOW0.Reg, value) +} +func (o *RTC_CNTL_Type) GetTIME_LOW0() uint32 { + return volatile.LoadUint32(&o.TIME_LOW0.Reg) +} + +// RTC_CNTL.TIME_HIGH0: rtc configure register +func (o *RTC_CNTL_Type) SetTIME_HIGH0_TIMER_VALUE0_HIGH(value uint32) { + volatile.StoreUint32(&o.TIME_HIGH0.Reg, volatile.LoadUint32(&o.TIME_HIGH0.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTIME_HIGH0_TIMER_VALUE0_HIGH() uint32 { + return volatile.LoadUint32(&o.TIME_HIGH0.Reg) & 0xffff +} + +// RTC_CNTL.STATE0: rtc configure register +func (o *RTC_CNTL_Type) SetSTATE0_SW_CPU_INT(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetSTATE0_SW_CPU_INT() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_REJECT_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_REJECT_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetSTATE0_APB2RTC_BRIDGE_SEL(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSTATE0_APB2RTC_BRIDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSTATE0_SDIO_ACTIVE_IND(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSTATE0_SDIO_ACTIVE_IND() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_WAKEUP(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_REJECT(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_REJECT() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLEEP_EN(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLEEP_EN() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIMER1: rtc configure register +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3e)|value<<1) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3e) >> 1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CK8M_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3fc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetTIMER1_CK8M_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3fc0) >> 6 +} +func (o *RTC_CNTL_Type) SetTIMER1_XTL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xffc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetTIMER1_XTL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xffc000) >> 14 +} +func (o *RTC_CNTL_Type) SetTIMER1_PLL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER1_PLL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER2: rtc configure register +func (o *RTC_CNTL_Type) SetTIMER2_MIN_TIME_CK8M_OFF(value uint32) { + volatile.StoreUint32(&o.TIMER2.Reg, volatile.LoadUint32(&o.TIMER2.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER2_MIN_TIME_CK8M_OFF() uint32 { + return (volatile.LoadUint32(&o.TIMER2.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER3: rtc configure register +func (o *RTC_CNTL_Type) SetTIMER3_WIFI_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0x1ff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER3_WIFI_WAIT_TIMER() uint32 { + return volatile.LoadUint32(&o.TIMER3.Reg) & 0x1ff +} +func (o *RTC_CNTL_Type) SetTIMER3_WIFI_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0xfe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTIMER3_WIFI_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0xfe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTIMER3_BT_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER3_BT_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER3_BT_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER3_BT_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER4: rtc configure register +func (o *RTC_CNTL_Type) SetTIMER4_CPU_TOP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0x1ff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER4_CPU_TOP_WAIT_TIMER() uint32 { + return volatile.LoadUint32(&o.TIMER4.Reg) & 0x1ff +} +func (o *RTC_CNTL_Type) SetTIMER4_CPU_TOP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0xfe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTIMER4_CPU_TOP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0xfe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER5: rtc configure register +func (o *RTC_CNTL_Type) SetTIMER5_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetTIMER5_MIN_SLP_VAL() uint32 { + return (volatile.LoadUint32(&o.TIMER5.Reg) & 0xff00) >> 8 +} + +// RTC_CNTL.TIMER6: rtc configure register +func (o *RTC_CNTL_Type) SetTIMER6_DG_PERI_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER6.Reg, volatile.LoadUint32(&o.TIMER6.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER6_DG_PERI_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER6.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER6_DG_PERI_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER6.Reg, volatile.LoadUint32(&o.TIMER6.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER6_DG_PERI_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER6.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.ANA_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetANA_CONF_RESET_POR_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetANA_CONF_RESET_POR_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetANA_CONF_RESET_POR_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetANA_CONF_RESET_POR_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetANA_CONF_GLITCH_RST_EN(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetANA_CONF_GLITCH_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetANA_CONF_SAR_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetANA_CONF_SAR_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLLA_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLLA_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLLA_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLLA_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetANA_CONF_BBPLL_CAL_SLP_START(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetANA_CONF_BBPLL_CAL_SLP_START() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PVTMON_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PVTMON_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetANA_CONF_TXRF_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetANA_CONF_TXRF_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetANA_CONF_RFRX_PBUS_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetANA_CONF_RFRX_PBUS_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetANA_CONF_CKGEN_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetANA_CONF_CKGEN_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLL_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLL_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.RESET_STATE: rtc configure register +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_CAUSE_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x3f)|value) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_CAUSE_PROCPU() uint32 { + return volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x3f +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_CAUSE_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0xfc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_CAUSE_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0xfc0) >> 6 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_STAT_VECTOR_SEL_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_STAT_VECTOR_SEL_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_STAT_VECTOR_SEL_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_STAT_VECTOR_SEL_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_ALL_RESET_FLAG_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_ALL_RESET_FLAG_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_ALL_RESET_FLAG_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_ALL_RESET_FLAG_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_ALL_RESET_FLAG_CLR_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_ALL_RESET_FLAG_CLR_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_ALL_RESET_FLAG_CLR_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_ALL_RESET_FLAG_CLR_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_OCD_HALT_ON_RESET_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_OCD_HALT_ON_RESET_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_OCD_HALT_ON_RESET_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_OCD_HALT_ON_RESET_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_JTAG_RESET_FLAG_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_JTAG_RESET_FLAG_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_JTAG_RESET_FLAG_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_JTAG_RESET_FLAG_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_JTAG_RESET_FLAG_CLR_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_JTAG_RESET_FLAG_CLR_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_JTAG_RESET_FLAG_CLR_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_JTAG_RESET_FLAG_CLR_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_DRESET_MASK_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_DRESET_MASK_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_DRESET_MASK_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_DRESET_MASK_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x2000000) >> 25 +} + +// RTC_CNTL.WAKEUP_STATE: rtc configure register +func (o *RTC_CNTL_Type) SetWAKEUP_STATE_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.WAKEUP_STATE.Reg, volatile.LoadUint32(&o.WAKEUP_STATE.Reg)&^(0xffff8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetWAKEUP_STATE_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_STATE.Reg) & 0xffff8000) >> 15 +} + +// RTC_CNTL.INT_ENA_RTC: rtc configure register +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SLP_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SLP_WAKEUP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SLP_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SLP_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_MAIN_TIMER_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_MAIN_TIMER_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SWD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SWD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_XTAL32K_DEAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_XTAL32K_DEAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_BBPLL_CAL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_BBPLL_CAL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_RAW_RTC: rtc configure register +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SLP_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SLP_WAKEUP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SLP_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SLP_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_MAIN_TIMER_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_MAIN_TIMER_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SWD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SWD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_XTAL32K_DEAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_XTAL32K_DEAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_BBPLL_CAL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_BBPLL_CAL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_ST_RTC: rtc configure register +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SLP_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SLP_WAKEUP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SLP_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SLP_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_MAIN_TIMER_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_MAIN_TIMER_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SWD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SWD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_XTAL32K_DEAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_XTAL32K_DEAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_BBPLL_CAL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_BBPLL_CAL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_CLR_RTC: rtc configure register +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SLP_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SLP_WAKEUP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SLP_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SLP_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_MAIN_TIMER_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_MAIN_TIMER_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SWD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SWD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_XTAL32K_DEAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_XTAL32K_DEAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_BBPLL_CAL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_BBPLL_CAL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.STORE0: rtc configure register +func (o *RTC_CNTL_Type) SetSTORE0(value uint32) { + volatile.StoreUint32(&o.STORE0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE0() uint32 { + return volatile.LoadUint32(&o.STORE0.Reg) +} + +// RTC_CNTL.STORE1: rtc configure register +func (o *RTC_CNTL_Type) SetSTORE1(value uint32) { + volatile.StoreUint32(&o.STORE1.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE1() uint32 { + return volatile.LoadUint32(&o.STORE1.Reg) +} + +// RTC_CNTL.STORE2: rtc configure register +func (o *RTC_CNTL_Type) SetSTORE2(value uint32) { + volatile.StoreUint32(&o.STORE2.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE2() uint32 { + return volatile.LoadUint32(&o.STORE2.Reg) +} + +// RTC_CNTL.STORE3: rtc configure register +func (o *RTC_CNTL_Type) SetSTORE3(value uint32) { + volatile.StoreUint32(&o.STORE3.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE3() uint32 { + return volatile.LoadUint32(&o.STORE3.Reg) +} + +// RTC_CNTL.EXT_XTL_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_WDT_EN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_WDT_EN() uint32 { + return volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_WDT_CLK_FO(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_WDT_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_WDT_RESET(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_WDT_RESET() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_EXT_CLK_FO(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_EXT_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_AUTO_BACKUP(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_AUTO_BACKUP() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_AUTO_RESTART(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_AUTO_RESTART() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_AUTO_RETURN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_AUTO_RETURN() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_ENCKINIT_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_ENCKINIT_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DBUF_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DBUF_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DGM_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x1c00)|value<<10) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DGM_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x1c00) >> 10 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DRES_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0xe000)|value<<13) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DRES_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0xe000) >> 13 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XPD_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XPD_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DAC_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0xe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DAC_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0xe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_WDT_STATE(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_WDT_STATE() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x700000) >> 20 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_GPIO_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_GPIO_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_LV(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_EN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_EN() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.EXT_WAKEUP_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_REJECT_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_SLEEP_REJECT_ENA(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x3ffff000)|value<<12) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_SLEEP_REJECT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x3ffff000) >> 12 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.CPU_PERIOD_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUSEL_CONF(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUSEL_CONF() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUPERIOD_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.CLK_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetCLK_CONF_EFUSE_CLK_FORCE_GATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_EFUSE_CLK_FORCE_GATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_EFUSE_CLK_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_EFUSE_CLK_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV_SEL_VLD(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV_SEL_VLD() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x30)|value<<4) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x30) >> 4 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_XTAL32K_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_XTAL32K_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_D256_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_D256_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x7000)|value<<12) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x7000) >> 12 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DFREQ(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1fe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DFREQ() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1fe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_GLOBAL_FORCE_GATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_GLOBAL_FORCE_GATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_GLOBAL_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_GLOBAL_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_FAST_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_FAST_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ANA_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ANA_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.SLOW_CLK_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_ANA_CLK_DIV_VLD(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_ANA_CLK_DIV_VLD() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_ANA_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x7f800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_ANA_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x7f800000) >> 23 +} +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SDIO_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_TIMER_TARGET() uint32 { + return volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_DTHDRV(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x600)|value<<9) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_DTHDRV() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x600) >> 9 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_DCAP(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x1800)|value<<11) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_DCAP() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x1800) >> 11 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_INITI(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_INITI() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x6000) >> 13 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_EN_INITI(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_EN_INITI() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_DCURLIM(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_DCURLIM() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x70000) >> 16 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_MODECURLIM(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_MODECURLIM() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_ENCURLIM(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_ENCURLIM() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_REG_PD_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_REG_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_FORCE(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_FORCE() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_TIEH(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_TIEH() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF__1P8_READY(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF__1P8_READY() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFL_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x6000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFL_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x6000000) >> 25 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFM_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFM_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x18000000) >> 27 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFH_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFH_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x60000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_XPD_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_XPD_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.BIAS_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetBIAS_CONF_DG_VDD_DRV_B_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DG_VDD_DRV_B_SLP() uint32 { + return volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DG_VDD_DRV_B_SLP_EN(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DG_VDD_DRV_B_SLP_EN() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_IDLE(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_IDLE() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_WAKE(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_WAKE() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_PD_CUR_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_PD_CUR_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_PD_CUR_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_PD_CUR_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_SLEEP_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_SLEEP_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_SLEEP_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_SLEEP_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c0000)|value<<18) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c0000) >> 18 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c00000) >> 22 +} + +// RTC_CNTL.RTC_CNTL: rtc configure register +func (o *RTC_CNTL_Type) SetRTC_CNTL_DIG_REG_CAL_EN(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_DIG_REG_CAL_EN() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetRTC_CNTL_SCK_DCAP(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x3fc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_SCK_DCAP() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x3fc000) >> 14 +} +func (o *RTC_CNTL_Type) SetRTC_CNTL_DBOOST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_DBOOST_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetRTC_CNTL_DBOOST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_DBOOST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetRTC_CNTL_REGULATOR_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_REGULATOR_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetRTC_CNTL_REGULATOR_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RTC_CNTL.Reg, volatile.LoadUint32(&o.RTC_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetRTC_CNTL_REGULATOR_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RTC_CNTL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.PWC: rtc configure register +func (o *RTC_CNTL_Type) SetPWC_PAD_FORCE_HOLD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetPWC_PAD_FORCE_HOLD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x200000) >> 21 +} + +// RTC_CNTL.DIG_PWC: rtc configure register +func (o *RTC_CNTL_Type) SetDIG_PWC_VDD_SPI_PWR_DRV(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_VDD_SPI_PWR_DRV() uint32 { + return volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_VDD_SPI_PWR_FORCE(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_VDD_SPI_PWR_FORCE() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_BT_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_BT_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_BT_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_BT_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_PERI_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_PERI_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_PERI_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_PERI_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_FASTMEM_FORCE_LPD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_FASTMEM_FORCE_LPD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_FASTMEM_FORCE_LPU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_FASTMEM_FORCE_LPU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_CPU_TOP_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_CPU_TOP_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_CPU_TOP_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_CPU_TOP_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_BT_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_BT_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_PERI_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_PERI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_CPU_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_CPU_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.DIG_ISO: rtc configure register +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_OFF(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_OFF() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_CLR_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_CLR_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_UNHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_UNHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_HOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_BT_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_BT_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_BT_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_BT_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PERI_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PERI_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PERI_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PERI_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_CPU_TOP_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_CPU_TOP_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_CPU_TOP_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_CPU_TOP_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_WIFI_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_WIFI_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_WIFI_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_WIFI_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG0: rtc configure register +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CHIP_RESET_WIDTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CHIP_RESET_WIDTH() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CHIP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CHIP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PAUSE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PAUSE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000)|value<<13) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000) >> 13 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000) >> 16 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x380000)|value<<19) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x380000) >> 19 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000000) >> 28 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG1: rtc configure register +func (o *RTC_CNTL_Type) SetWDTCONFIG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG1() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) +} + +// RTC_CNTL.WDTCONFIG2: rtc configure register +func (o *RTC_CNTL_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// RTC_CNTL.WDTCONFIG3: rtc configure register +func (o *RTC_CNTL_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// RTC_CNTL.WDTCONFIG4: rtc configure register +func (o *RTC_CNTL_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// RTC_CNTL.WDTFEED: rtc configure register +func (o *RTC_CNTL_Type) SetWDTFEED_WDT_FEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, volatile.LoadUint32(&o.WDTFEED.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTFEED_WDT_FEED() uint32 { + return (volatile.LoadUint32(&o.WDTFEED.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTWPROTECT: rtc configure register +func (o *RTC_CNTL_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// RTC_CNTL.SWD_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_RESET_FLAG() uint32 { + return volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_FEED_INT(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_FEED_INT() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_BYPASS_RST(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_BYPASS_RST() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_SIGNAL_WIDTH(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0xffc0000)|value<<18) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_SIGNAL_WIDTH() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0xffc0000) >> 18 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_RST_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_RST_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_FEED(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_FEED() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_DISABLE(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_AUTO_FEED_EN(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_AUTO_FEED_EN() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SWD_WPROTECT: rtc configure register +func (o *RTC_CNTL_Type) SetSWD_WPROTECT(value uint32) { + volatile.StoreUint32(&o.SWD_WPROTECT.Reg, value) +} +func (o *RTC_CNTL_Type) GetSWD_WPROTECT() uint32 { + return volatile.LoadUint32(&o.SWD_WPROTECT.Reg) +} + +// RTC_CNTL.SW_CPU_STALL: rtc configure register +func (o *RTC_CNTL_Type) SetSW_CPU_STALL_SW_STALL_APPCPU_C1(value uint32) { + volatile.StoreUint32(&o.SW_CPU_STALL.Reg, volatile.LoadUint32(&o.SW_CPU_STALL.Reg)&^(0x3f00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetSW_CPU_STALL_SW_STALL_APPCPU_C1() uint32 { + return (volatile.LoadUint32(&o.SW_CPU_STALL.Reg) & 0x3f00000) >> 20 +} +func (o *RTC_CNTL_Type) SetSW_CPU_STALL_SW_STALL_PROCPU_C1(value uint32) { + volatile.StoreUint32(&o.SW_CPU_STALL.Reg, volatile.LoadUint32(&o.SW_CPU_STALL.Reg)&^(0xfc000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetSW_CPU_STALL_SW_STALL_PROCPU_C1() uint32 { + return (volatile.LoadUint32(&o.SW_CPU_STALL.Reg) & 0xfc000000) >> 26 +} + +// RTC_CNTL.STORE4: rtc configure register +func (o *RTC_CNTL_Type) SetSTORE4(value uint32) { + volatile.StoreUint32(&o.STORE4.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE4() uint32 { + return volatile.LoadUint32(&o.STORE4.Reg) +} + +// RTC_CNTL.STORE5: rtc configure register +func (o *RTC_CNTL_Type) SetSTORE5(value uint32) { + volatile.StoreUint32(&o.STORE5.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE5() uint32 { + return volatile.LoadUint32(&o.STORE5.Reg) +} + +// RTC_CNTL.STORE6: rtc configure register +func (o *RTC_CNTL_Type) SetSTORE6(value uint32) { + volatile.StoreUint32(&o.STORE6.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE6() uint32 { + return volatile.LoadUint32(&o.STORE6.Reg) +} + +// RTC_CNTL.STORE7: rtc configure register +func (o *RTC_CNTL_Type) SetSTORE7(value uint32) { + volatile.StoreUint32(&o.STORE7.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE7() uint32 { + return volatile.LoadUint32(&o.STORE7.Reg) +} + +// RTC_CNTL.LOW_POWER_ST: rtc configure register +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_ROM0(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_ROM0() uint32 { + return volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_DIG_DCDC(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_DIG_DCDC() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_PERI_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_PERI_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_RTC_PERI(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_RTC_PERI() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_WIFI_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_WIFI_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_WIFI(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_WIFI() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_DIG_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_DIG_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_DIG(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_DIG() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_START(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_START() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_SWITCH(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_SWITCH() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_DONE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_DONE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_START(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_START() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_SWITCH(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_SWITCH() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_DONE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_DONE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_XTAL_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_XTAL_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_PLL_ON(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_PLL_ON() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_RDY_FOR_WAKEUP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_RDY_FOR_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_WAIT_END(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_WAIT_END() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_IN_WAKEUP_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_IN_WAKEUP_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_IN_LOW_POWER_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_IN_LOW_POWER_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_8M(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_8M() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_IDLE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_IDLE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.DIAG0: rtc configure register +func (o *RTC_CNTL_Type) SetDIAG0(value uint32) { + volatile.StoreUint32(&o.DIAG0.Reg, value) +} +func (o *RTC_CNTL_Type) GetDIAG0() uint32 { + return volatile.LoadUint32(&o.DIAG0.Reg) +} + +// RTC_CNTL.PAD_HOLD: rtc configure register +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN0_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN0_HOLD() uint32 { + return volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN1_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN1_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN2_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN2_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN3_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN3_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN4_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN4_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_GPIO_PIN5_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_GPIO_PIN5_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x20) >> 5 +} + +// RTC_CNTL.DIG_PAD_HOLD: rtc configure register +func (o *RTC_CNTL_Type) SetDIG_PAD_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_PAD_HOLD.Reg, value) +} +func (o *RTC_CNTL_Type) GetDIG_PAD_HOLD() uint32 { + return volatile.LoadUint32(&o.DIG_PAD_HOLD.Reg) +} + +// RTC_CNTL.BROWN_OUT: rtc configure register +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_INT_WAIT(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x3ff0)|value<<4) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_INT_WAIT() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x3ff0) >> 4 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_PD_RF_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_PD_RF_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_RST_WAIT(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x3ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_RST_WAIT() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x3ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_RST_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_RST_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_RST_SEL(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_RST_SEL() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_ANA_RST_EN(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_ANA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_DET(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_DET() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIME_LOW1: rtc configure register +func (o *RTC_CNTL_Type) SetTIME_LOW1(value uint32) { + volatile.StoreUint32(&o.TIME_LOW1.Reg, value) +} +func (o *RTC_CNTL_Type) GetTIME_LOW1() uint32 { + return volatile.LoadUint32(&o.TIME_LOW1.Reg) +} + +// RTC_CNTL.TIME_HIGH1: rtc configure register +func (o *RTC_CNTL_Type) SetTIME_HIGH1_TIMER_VALUE1_HIGH(value uint32) { + volatile.StoreUint32(&o.TIME_HIGH1.Reg, volatile.LoadUint32(&o.TIME_HIGH1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTIME_HIGH1_TIMER_VALUE1_HIGH() uint32 { + return volatile.LoadUint32(&o.TIME_HIGH1.Reg) & 0xffff +} + +// RTC_CNTL.XTAL32K_CLK_FACTOR: rtc configure register +func (o *RTC_CNTL_Type) SetXTAL32K_CLK_FACTOR(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CLK_FACTOR.Reg, value) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CLK_FACTOR() uint32 { + return volatile.LoadUint32(&o.XTAL32K_CLK_FACTOR.Reg) +} + +// RTC_CNTL.XTAL32K_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_RETURN_WAIT(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xf)|value) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_RETURN_WAIT() uint32 { + return volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xf +} +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_RESTART_WAIT(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xffff0)|value<<4) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_RESTART_WAIT() uint32 { + return (volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xffff0) >> 4 +} +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_WDT_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xff00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_WDT_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xff00000) >> 20 +} +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_STABLE_THRES(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_STABLE_THRES() uint32 { + return (volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.USB_CONF: rtc configure register +func (o *RTC_CNTL_Type) SetUSB_CONF_IO_MUX_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_IO_MUX_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x40000) >> 18 +} + +// RTC_CNTL.SLP_REJECT_CAUSE: RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG +func (o *RTC_CNTL_Type) SetSLP_REJECT_CAUSE_REJECT_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CAUSE.Reg, volatile.LoadUint32(&o.SLP_REJECT_CAUSE.Reg)&^(0x3ffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CAUSE_REJECT_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_REJECT_CAUSE.Reg) & 0x3ffff +} + +// RTC_CNTL.OPTION1: rtc configure register +func (o *RTC_CNTL_Type) SetOPTION1_FORCE_DOWNLOAD_BOOT(value uint32) { + volatile.StoreUint32(&o.OPTION1.Reg, volatile.LoadUint32(&o.OPTION1.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetOPTION1_FORCE_DOWNLOAD_BOOT() uint32 { + return volatile.LoadUint32(&o.OPTION1.Reg) & 0x1 +} + +// RTC_CNTL.SLP_WAKEUP_CAUSE: RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG +func (o *RTC_CNTL_Type) SetSLP_WAKEUP_CAUSE_WAKEUP_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CAUSE.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CAUSE.Reg)&^(0x1ffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_WAKEUP_CAUSE_WAKEUP_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CAUSE.Reg) & 0x1ffff +} + +// RTC_CNTL.ULP_CP_TIMER_1: rtc configure register +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER_1.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg)&^(0xffffff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg) & 0xffffff00) >> 8 +} + +// RTC_CNTL.INT_ENA_RTC_W1TS: rtc configure register +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_ENA_RTC_W1TC: rtc configure register +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.RETENTION_CTRL: rtc configure register +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_DONE_WAIT(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x380000)|value<<19) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_DONE_WAIT() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x380000) >> 19 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_CLKOFF_WAIT(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x3c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_CLKOFF_WAIT() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x3c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_WAIT(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_WAIT() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0xf8000000) >> 27 +} + +// RTC_CNTL.FIB_SEL: rtc configure register +func (o *RTC_CNTL_Type) SetFIB_SEL(value uint32) { + volatile.StoreUint32(&o.FIB_SEL.Reg, volatile.LoadUint32(&o.FIB_SEL.Reg)&^(0x7)|value) +} +func (o *RTC_CNTL_Type) GetFIB_SEL() uint32 { + return volatile.LoadUint32(&o.FIB_SEL.Reg) & 0x7 +} + +// RTC_CNTL.GPIO_WAKEUP: rtc configure register +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_WAKEUP_STATUS(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x3f)|value) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_WAKEUP_STATUS() uint32 { + return volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x3f +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN_CLK_GATE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN_CLK_GATE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x700)|value<<8) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x700) >> 8 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x3800)|value<<11) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x3800) >> 11 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x1c000)|value<<14) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x1c000) >> 14 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0xe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0xe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x700000)|value<<20) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x700000) >> 20 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x3800000) >> 23 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetGPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_WAKEUP.Reg, volatile.LoadUint32(&o.GPIO_WAKEUP.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetGPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_WAKEUP.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.DBG_SEL: rtc configure register +func (o *RTC_CNTL_Type) SetDBG_SEL_DEBUG_12M_NO_GATING(value uint32) { + volatile.StoreUint32(&o.DBG_SEL.Reg, volatile.LoadUint32(&o.DBG_SEL.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetDBG_SEL_DEBUG_12M_NO_GATING() uint32 { + return (volatile.LoadUint32(&o.DBG_SEL.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetDBG_SEL_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_SEL.Reg, volatile.LoadUint32(&o.DBG_SEL.Reg)&^(0x7c)|value<<2) +} +func (o *RTC_CNTL_Type) GetDBG_SEL_DEBUG_BIT_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_SEL.Reg) & 0x7c) >> 2 +} +func (o *RTC_CNTL_Type) SetDBG_SEL_DEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.DBG_SEL.Reg, volatile.LoadUint32(&o.DBG_SEL.Reg)&^(0xf80)|value<<7) +} +func (o *RTC_CNTL_Type) GetDBG_SEL_DEBUG_SEL0() uint32 { + return (volatile.LoadUint32(&o.DBG_SEL.Reg) & 0xf80) >> 7 +} +func (o *RTC_CNTL_Type) SetDBG_SEL_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.DBG_SEL.Reg, volatile.LoadUint32(&o.DBG_SEL.Reg)&^(0x1f000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDBG_SEL_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.DBG_SEL.Reg) & 0x1f000) >> 12 +} +func (o *RTC_CNTL_Type) SetDBG_SEL_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.DBG_SEL.Reg, volatile.LoadUint32(&o.DBG_SEL.Reg)&^(0x3e0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetDBG_SEL_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.DBG_SEL.Reg) & 0x3e0000) >> 17 +} +func (o *RTC_CNTL_Type) SetDBG_SEL_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.DBG_SEL.Reg, volatile.LoadUint32(&o.DBG_SEL.Reg)&^(0x7c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetDBG_SEL_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.DBG_SEL.Reg) & 0x7c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetDBG_SEL_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.DBG_SEL.Reg, volatile.LoadUint32(&o.DBG_SEL.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDBG_SEL_DEBUG_SEL4() uint32 { + return (volatile.LoadUint32(&o.DBG_SEL.Reg) & 0xf8000000) >> 27 +} + +// RTC_CNTL.DBG_MAP: rtc configure register +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN5_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN5_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN4_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN4_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN3_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN3_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN0_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN0_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN5_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0xf00)|value<<8) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN5_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0xf00) >> 8 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN4_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0xf000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN4_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0xf000) >> 12 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN3_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0xf0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN3_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0xf0000) >> 16 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0xf00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0xf00000) >> 20 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0xf000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0xf000000) >> 24 +} +func (o *RTC_CNTL_Type) SetDBG_MAP_GPIO_PIN0_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_MAP.Reg, volatile.LoadUint32(&o.DBG_MAP.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetDBG_MAP_GPIO_PIN0_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_MAP.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.SENSOR_CTRL: rtc configure register +func (o *RTC_CNTL_Type) SetSENSOR_CTRL_SAR2_PWDET_CCT(value uint32) { + volatile.StoreUint32(&o.SENSOR_CTRL.Reg, volatile.LoadUint32(&o.SENSOR_CTRL.Reg)&^(0x38000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetSENSOR_CTRL_SAR2_PWDET_CCT() uint32 { + return (volatile.LoadUint32(&o.SENSOR_CTRL.Reg) & 0x38000000) >> 27 +} +func (o *RTC_CNTL_Type) SetSENSOR_CTRL_FORCE_XPD_SAR(value uint32) { + volatile.StoreUint32(&o.SENSOR_CTRL.Reg, volatile.LoadUint32(&o.SENSOR_CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSENSOR_CTRL_FORCE_XPD_SAR() uint32 { + return (volatile.LoadUint32(&o.SENSOR_CTRL.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.DBG_SAR_SEL: rtc configure register +func (o *RTC_CNTL_Type) SetDBG_SAR_SEL_SAR_DEBUG_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_SAR_SEL.Reg, volatile.LoadUint32(&o.DBG_SAR_SEL.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDBG_SAR_SEL_SAR_DEBUG_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_SAR_SEL.Reg) & 0xf8000000) >> 27 +} + +// RTC_CNTL.PG_CTRL: rtc configure register +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_DSENSE(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0xc000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_DSENSE() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0xc000000) >> 26 +} +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_EFUSE_SEL(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_EFUSE_SEL() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_EN(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_EN() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.DATE: rtc configure register +func (o *RTC_CNTL_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_CNTL_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SENSITIVE Peripheral +type SENSITIVE_Type struct { + ROM_TABLE_LOCK volatile.Register32 // 0x0 + ROM_TABLE volatile.Register32 // 0x4 + PRIVILEGE_MODE_SEL_LOCK volatile.Register32 // 0x8 + PRIVILEGE_MODE_SEL volatile.Register32 // 0xC + APB_PERIPHERAL_ACCESS_0 volatile.Register32 // 0x10 + APB_PERIPHERAL_ACCESS_1 volatile.Register32 // 0x14 + INTERNAL_SRAM_USAGE_0 volatile.Register32 // 0x18 + INTERNAL_SRAM_USAGE_1 volatile.Register32 // 0x1C + INTERNAL_SRAM_USAGE_3 volatile.Register32 // 0x20 + INTERNAL_SRAM_USAGE_4 volatile.Register32 // 0x24 + CACHE_TAG_ACCESS_0 volatile.Register32 // 0x28 + CACHE_TAG_ACCESS_1 volatile.Register32 // 0x2C + CACHE_MMU_ACCESS_0 volatile.Register32 // 0x30 + CACHE_MMU_ACCESS_1 volatile.Register32 // 0x34 + DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 volatile.Register32 // 0x38 + DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 volatile.Register32 // 0x3C + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0 volatile.Register32 // 0x40 + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1 volatile.Register32 // 0x44 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 volatile.Register32 // 0x48 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 volatile.Register32 // 0x4C + DMA_APBPERI_MAC_PMS_CONSTRAIN_0 volatile.Register32 // 0x50 + DMA_APBPERI_MAC_PMS_CONSTRAIN_1 volatile.Register32 // 0x54 + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 volatile.Register32 // 0x58 + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 volatile.Register32 // 0x5C + DMA_APBPERI_LC_PMS_CONSTRAIN_0 volatile.Register32 // 0x60 + DMA_APBPERI_LC_PMS_CONSTRAIN_1 volatile.Register32 // 0x64 + DMA_APBPERI_AES_PMS_CONSTRAIN_0 volatile.Register32 // 0x68 + DMA_APBPERI_AES_PMS_CONSTRAIN_1 volatile.Register32 // 0x6C + DMA_APBPERI_SHA_PMS_CONSTRAIN_0 volatile.Register32 // 0x70 + DMA_APBPERI_SHA_PMS_CONSTRAIN_1 volatile.Register32 // 0x74 + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 volatile.Register32 // 0x78 + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 volatile.Register32 // 0x7C + DMA_APBPERI_PMS_MONITOR_0 volatile.Register32 // 0x80 + DMA_APBPERI_PMS_MONITOR_1 volatile.Register32 // 0x84 + DMA_APBPERI_PMS_MONITOR_2 volatile.Register32 // 0x88 + DMA_APBPERI_PMS_MONITOR_3 volatile.Register32 // 0x8C + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 volatile.Register32 // 0x90 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 volatile.Register32 // 0x94 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 volatile.Register32 // 0x98 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 volatile.Register32 // 0x9C + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 volatile.Register32 // 0xA0 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 volatile.Register32 // 0xA4 + CORE_X_IRAM0_PMS_CONSTRAIN_0 volatile.Register32 // 0xA8 + CORE_X_IRAM0_PMS_CONSTRAIN_1 volatile.Register32 // 0xAC + CORE_X_IRAM0_PMS_CONSTRAIN_2 volatile.Register32 // 0xB0 + CORE_0_IRAM0_PMS_MONITOR_0 volatile.Register32 // 0xB4 + CORE_0_IRAM0_PMS_MONITOR_1 volatile.Register32 // 0xB8 + CORE_0_IRAM0_PMS_MONITOR_2 volatile.Register32 // 0xBC + CORE_X_DRAM0_PMS_CONSTRAIN_0 volatile.Register32 // 0xC0 + CORE_X_DRAM0_PMS_CONSTRAIN_1 volatile.Register32 // 0xC4 + CORE_0_DRAM0_PMS_MONITOR_0 volatile.Register32 // 0xC8 + CORE_0_DRAM0_PMS_MONITOR_1 volatile.Register32 // 0xCC + CORE_0_DRAM0_PMS_MONITOR_2 volatile.Register32 // 0xD0 + CORE_0_DRAM0_PMS_MONITOR_3 volatile.Register32 // 0xD4 + CORE_0_PIF_PMS_CONSTRAIN_0 volatile.Register32 // 0xD8 + CORE_0_PIF_PMS_CONSTRAIN_1 volatile.Register32 // 0xDC + CORE_0_PIF_PMS_CONSTRAIN_2 volatile.Register32 // 0xE0 + CORE_0_PIF_PMS_CONSTRAIN_3 volatile.Register32 // 0xE4 + CORE_0_PIF_PMS_CONSTRAIN_4 volatile.Register32 // 0xE8 + CORE_0_PIF_PMS_CONSTRAIN_5 volatile.Register32 // 0xEC + CORE_0_PIF_PMS_CONSTRAIN_6 volatile.Register32 // 0xF0 + CORE_0_PIF_PMS_CONSTRAIN_7 volatile.Register32 // 0xF4 + CORE_0_PIF_PMS_CONSTRAIN_8 volatile.Register32 // 0xF8 + CORE_0_PIF_PMS_CONSTRAIN_9 volatile.Register32 // 0xFC + CORE_0_PIF_PMS_CONSTRAIN_10 volatile.Register32 // 0x100 + REGION_PMS_CONSTRAIN_0 volatile.Register32 // 0x104 + REGION_PMS_CONSTRAIN_1 volatile.Register32 // 0x108 + REGION_PMS_CONSTRAIN_2 volatile.Register32 // 0x10C + REGION_PMS_CONSTRAIN_3 volatile.Register32 // 0x110 + REGION_PMS_CONSTRAIN_4 volatile.Register32 // 0x114 + REGION_PMS_CONSTRAIN_5 volatile.Register32 // 0x118 + REGION_PMS_CONSTRAIN_6 volatile.Register32 // 0x11C + REGION_PMS_CONSTRAIN_7 volatile.Register32 // 0x120 + REGION_PMS_CONSTRAIN_8 volatile.Register32 // 0x124 + REGION_PMS_CONSTRAIN_9 volatile.Register32 // 0x128 + REGION_PMS_CONSTRAIN_10 volatile.Register32 // 0x12C + CORE_0_PIF_PMS_MONITOR_0 volatile.Register32 // 0x130 + CORE_0_PIF_PMS_MONITOR_1 volatile.Register32 // 0x134 + CORE_0_PIF_PMS_MONITOR_2 volatile.Register32 // 0x138 + CORE_0_PIF_PMS_MONITOR_3 volatile.Register32 // 0x13C + CORE_0_PIF_PMS_MONITOR_4 volatile.Register32 // 0x140 + CORE_0_PIF_PMS_MONITOR_5 volatile.Register32 // 0x144 + CORE_0_PIF_PMS_MONITOR_6 volatile.Register32 // 0x148 + BACKUP_BUS_PMS_CONSTRAIN_0 volatile.Register32 // 0x14C + BACKUP_BUS_PMS_CONSTRAIN_1 volatile.Register32 // 0x150 + BACKUP_BUS_PMS_CONSTRAIN_2 volatile.Register32 // 0x154 + BACKUP_BUS_PMS_CONSTRAIN_3 volatile.Register32 // 0x158 + BACKUP_BUS_PMS_CONSTRAIN_4 volatile.Register32 // 0x15C + BACKUP_BUS_PMS_MONITOR_0 volatile.Register32 // 0x160 + BACKUP_BUS_PMS_MONITOR_1 volatile.Register32 // 0x164 + BACKUP_BUS_PMS_MONITOR_2 volatile.Register32 // 0x168 + BACKUP_BUS_PMS_MONITOR_3 volatile.Register32 // 0x16C + CLOCK_GATE volatile.Register32 // 0x170 + _ [3720]byte + DATE volatile.Register32 // 0xFFC +} + +// SENSITIVE.ROM_TABLE_LOCK: SENSITIVE_ROM_TABLE_LOCK_REG +func (o *SENSITIVE_Type) SetROM_TABLE_LOCK(value uint32) { + volatile.StoreUint32(&o.ROM_TABLE_LOCK.Reg, volatile.LoadUint32(&o.ROM_TABLE_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetROM_TABLE_LOCK() uint32 { + return volatile.LoadUint32(&o.ROM_TABLE_LOCK.Reg) & 0x1 +} + +// SENSITIVE.ROM_TABLE: SENSITIVE_ROM_TABLE_REG +func (o *SENSITIVE_Type) SetROM_TABLE(value uint32) { + volatile.StoreUint32(&o.ROM_TABLE.Reg, value) +} +func (o *SENSITIVE_Type) GetROM_TABLE() uint32 { + return volatile.LoadUint32(&o.ROM_TABLE.Reg) +} + +// SENSITIVE.PRIVILEGE_MODE_SEL_LOCK: SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG +func (o *SENSITIVE_Type) SetPRIVILEGE_MODE_SEL_LOCK(value uint32) { + volatile.StoreUint32(&o.PRIVILEGE_MODE_SEL_LOCK.Reg, volatile.LoadUint32(&o.PRIVILEGE_MODE_SEL_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetPRIVILEGE_MODE_SEL_LOCK() uint32 { + return volatile.LoadUint32(&o.PRIVILEGE_MODE_SEL_LOCK.Reg) & 0x1 +} + +// SENSITIVE.PRIVILEGE_MODE_SEL: SENSITIVE_PRIVILEGE_MODE_SEL_REG +func (o *SENSITIVE_Type) SetPRIVILEGE_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.PRIVILEGE_MODE_SEL.Reg, volatile.LoadUint32(&o.PRIVILEGE_MODE_SEL.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetPRIVILEGE_MODE_SEL() uint32 { + return volatile.LoadUint32(&o.PRIVILEGE_MODE_SEL.Reg) & 0x1 +} + +// SENSITIVE.APB_PERIPHERAL_ACCESS_0: SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG +func (o *SENSITIVE_Type) SetAPB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_ACCESS_0.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetAPB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_0.Reg) & 0x1 +} + +// SENSITIVE.APB_PERIPHERAL_ACCESS_1: SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG +func (o *SENSITIVE_Type) SetAPB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_ACCESS_1.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetAPB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_1.Reg) & 0x1 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_0: SENSITIVE_INTERNAL_SRAM_USAGE_0_REG +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_0.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_0.Reg) & 0x1 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_1: SENSITIVE_INTERNAL_SRAM_USAGE_1_REG +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_1.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_SRAM(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_1.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg)&^(0xe)|value<<1) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_SRAM() uint32 { + return (volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg) & 0xe) >> 1 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_3: SENSITIVE_INTERNAL_SRAM_USAGE_3_REG +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_3.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_3.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg)&^(0x8)|value<<3) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP() uint32 { + return (volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg) & 0x8) >> 3 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_4: SENSITIVE_INTERNAL_SRAM_USAGE_4_REG +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_4_INTERNAL_SRAM_USAGE_LOG_SRAM(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_4.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_4.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_4_INTERNAL_SRAM_USAGE_LOG_SRAM() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_4.Reg) & 0x1 +} + +// SENSITIVE.CACHE_TAG_ACCESS_0: SENSITIVE_CACHE_TAG_ACCESS_0_REG +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_0.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_ACCESS_0.Reg) & 0x1 +} + +// SENSITIVE.CACHE_TAG_ACCESS_1: SENSITIVE_CACHE_TAG_ACCESS_1_REG +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x4)|value<<2) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x4) >> 2 +} +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x8)|value<<3) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x8) >> 3 +} + +// SENSITIVE.CACHE_MMU_ACCESS_0: SENSITIVE_CACHE_MMU_ACCESS_0_REG +func (o *SENSITIVE_Type) SetCACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_0.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_ACCESS_0.Reg) & 0x1 +} + +// SENSITIVE.CACHE_MMU_ACCESS_1: SENSITIVE_CACHE_MMU_ACCESS_1_REG +func (o *SENSITIVE_Type) SetCACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.DMA_APBPERI_SPI2_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} + +// SENSITIVE.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} + +// SENSITIVE.DMA_APBPERI_I2S0_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} + +// SENSITIVE.DMA_APBPERI_MAC_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_MAC_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} + +// SENSITIVE.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} + +// SENSITIVE.DMA_APBPERI_LC_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_LC_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} + +// SENSITIVE.DMA_APBPERI_AES_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_AES_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} + +// SENSITIVE.DMA_APBPERI_SHA_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_SHA_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} + +// SENSITIVE.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} + +// SENSITIVE.DMA_APBPERI_PMS_MONITOR_0: SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_PMS_MONITOR_1: SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.DMA_APBPERI_PMS_MONITOR_2: SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg)&^(0x6)|value<<1) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg) & 0x6) >> 1 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg)&^(0x7fffff8)|value<<3) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg) & 0x7fffff8) >> 3 +} + +// SENSITIVE.DMA_APBPERI_PMS_MONITOR_3: SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg)&^(0x1e)|value<<1) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg) & 0x1e) >> 1 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_PMS_CONSTRAIN_0: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_X_IRAM0_PMS_CONSTRAIN_1: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0xe00) >> 9 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x7000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x7000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x1c0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x1c0000) >> 18 +} + +// SENSITIVE.CORE_X_IRAM0_PMS_CONSTRAIN_2: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0xe00) >> 9 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x7000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x7000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x1c0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x1c0000) >> 18 +} + +// SENSITIVE.CORE_0_IRAM0_PMS_MONITOR_0: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_IRAM0_PMS_MONITOR_1: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_0_IRAM0_PMS_MONITOR_2: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x4)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x4) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x18)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x18) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x1fffffe0)|value<<5) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x1fffffe0) >> 5 +} + +// SENSITIVE.CORE_X_DRAM0_PMS_CONSTRAIN_0: SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_X_DRAM0_PMS_CONSTRAIN_1: SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc000000) >> 26 +} + +// SENSITIVE.CORE_0_DRAM0_PMS_MONITOR_0: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_DRAM0_PMS_MONITOR_1: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_0_DRAM0_PMS_MONITOR_2: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg)&^(0xffffff0)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg) & 0xffffff0) >> 4 +} + +// SENSITIVE.CORE_0_DRAM0_PMS_MONITOR_3: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg)&^(0x1e)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg) & 0x1e) >> 1 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_0: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_1: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_2: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_3: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0x30000000) >> 28 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_4: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_5: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_6: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_7: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0x30000000) >> 28 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_8: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_9: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg)&^(0x7ff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg) & 0x7ff +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg) & 0x3ff800) >> 11 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_10: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg) & 0xe00) >> 9 +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_0: SENSITIVE_REGION_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_0_REGION_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_0_REGION_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_1: SENSITIVE_REGION_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_2: SENSITIVE_REGION_PMS_CONSTRAIN_2_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6() uint32 { + return (volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_2.Reg) & 0x3000) >> 12 +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_3: SENSITIVE_REGION_PMS_CONSTRAIN_3_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_3_REGION_PMS_CONSTRAIN_ADDR_0(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_3.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_3_REGION_PMS_CONSTRAIN_ADDR_0() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_3.Reg) & 0x3fffffff +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_4: SENSITIVE_REGION_PMS_CONSTRAIN_4_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_4_REGION_PMS_CONSTRAIN_ADDR_1(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_4.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_4_REGION_PMS_CONSTRAIN_ADDR_1() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_4.Reg) & 0x3fffffff +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_5: SENSITIVE_REGION_PMS_CONSTRAIN_5_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_5_REGION_PMS_CONSTRAIN_ADDR_2(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_5.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_5_REGION_PMS_CONSTRAIN_ADDR_2() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_5.Reg) & 0x3fffffff +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_6: SENSITIVE_REGION_PMS_CONSTRAIN_6_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_6_REGION_PMS_CONSTRAIN_ADDR_3(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_6.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_6_REGION_PMS_CONSTRAIN_ADDR_3() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_6.Reg) & 0x3fffffff +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_7: SENSITIVE_REGION_PMS_CONSTRAIN_7_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_7_REGION_PMS_CONSTRAIN_ADDR_4(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_7.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_7_REGION_PMS_CONSTRAIN_ADDR_4() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_7.Reg) & 0x3fffffff +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_8: SENSITIVE_REGION_PMS_CONSTRAIN_8_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_8_REGION_PMS_CONSTRAIN_ADDR_5(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_8.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_8_REGION_PMS_CONSTRAIN_ADDR_5() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_8.Reg) & 0x3fffffff +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_9: SENSITIVE_REGION_PMS_CONSTRAIN_9_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_9_REGION_PMS_CONSTRAIN_ADDR_6(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_9.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_9.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_9_REGION_PMS_CONSTRAIN_ADDR_6() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_9.Reg) & 0x3fffffff +} + +// SENSITIVE.REGION_PMS_CONSTRAIN_10: SENSITIVE_REGION_PMS_CONSTRAIN_10_REG +func (o *SENSITIVE_Type) SetREGION_PMS_CONSTRAIN_10_REGION_PMS_CONSTRAIN_ADDR_7(value uint32) { + volatile.StoreUint32(&o.REGION_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_10.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetREGION_PMS_CONSTRAIN_10_REGION_PMS_CONSTRAIN_ADDR_7() uint32 { + return volatile.LoadUint32(&o.REGION_PMS_CONSTRAIN_10.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_0: SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_1: SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_2: SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0x1c)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0x1c) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0x20)|value<<5) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0x20) >> 5 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0xc0) >> 6 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_3: SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_3.Reg, value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_3() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_3.Reg) +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_4: SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_5: SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg)&^(0x6)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg) & 0x6) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg)&^(0x18)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg) & 0x18) >> 3 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_6: SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_6(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_6.Reg, value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_6() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_6.Reg) +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_0: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_1: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_GPIO(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_GPIO() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE2(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE2() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_TIMER(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_TIMER() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_RTC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_RTC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_WDG(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_WDG() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_MISC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_MISC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2C(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2C() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_2: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BT(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BT() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_UHCI0(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_UHCI0() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_RMT(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_RMT() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_LEDC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_LEDC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BB(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BB() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_3: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_2(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_2() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_CAN(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_CAN() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2S1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2S1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_RWBT(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_RWBT() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWR(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWR() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0x30000000) >> 28 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_4: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc000) >> 14 +} + +// SENSITIVE.BACKUP_BUS_PMS_MONITOR_0: SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.BACKUP_BUS_PMS_MONITOR_1: SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.BACKUP_BUS_PMS_MONITOR_2: SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg)&^(0x6)|value<<1) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg) & 0x6) >> 1 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg)&^(0x40)|value<<6) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg) & 0x40) >> 6 +} + +// SENSITIVE.BACKUP_BUS_PMS_MONITOR_3: SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_3(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_3.Reg, value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_3() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_3.Reg) +} + +// SENSITIVE.CLOCK_GATE: SENSITIVE_CLOCK_GATE_REG_REG +func (o *SENSITIVE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SENSITIVE.DATE: SENSITIVE_DATE_REG +func (o *SENSITIVE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SENSITIVE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SHA (Secure Hash Algorithm) Accelerator +type SHA_Type struct { + MODE volatile.Register32 // 0x0 + T_STRING volatile.Register32 // 0x4 + T_LENGTH volatile.Register32 // 0x8 + DMA_BLOCK_NUM volatile.Register32 // 0xC + START volatile.Register32 // 0x10 + CONTINUE volatile.Register32 // 0x14 + BUSY volatile.Register32 // 0x18 + DMA_START volatile.Register32 // 0x1C + DMA_CONTINUE volatile.Register32 // 0x20 + CLEAR_IRQ volatile.Register32 // 0x24 + IRQ_ENA volatile.Register32 // 0x28 + DATE volatile.Register32 // 0x2C + _ [16]byte + H_MEM [64]volatile.Register8 // 0x40 + M_MEM [64]volatile.Register8 // 0x80 +} + +// SHA.MODE: Initial configuration register. +func (o *SHA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *SHA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// SHA.T_STRING: SHA 512/t configuration register 0. +func (o *SHA_Type) SetT_STRING(value uint32) { + volatile.StoreUint32(&o.T_STRING.Reg, value) +} +func (o *SHA_Type) GetT_STRING() uint32 { + return volatile.LoadUint32(&o.T_STRING.Reg) +} + +// SHA.T_LENGTH: SHA 512/t configuration register 1. +func (o *SHA_Type) SetT_LENGTH(value uint32) { + volatile.StoreUint32(&o.T_LENGTH.Reg, volatile.LoadUint32(&o.T_LENGTH.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetT_LENGTH() uint32 { + return volatile.LoadUint32(&o.T_LENGTH.Reg) & 0x3f +} + +// SHA.DMA_BLOCK_NUM: DMA configuration register 0. +func (o *SHA_Type) SetDMA_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_NUM.Reg, volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetDMA_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg) & 0x3f +} + +// SHA.START: Typical SHA configuration register 0. +func (o *SHA_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetSTART() uint32 { + return (volatile.LoadUint32(&o.START.Reg) & 0xfffffffe) >> 1 +} + +// SHA.CONTINUE: Typical SHA configuration register 1. +func (o *SHA_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetCONTINUE() uint32 { + return (volatile.LoadUint32(&o.CONTINUE.Reg) & 0xfffffffe) >> 1 +} + +// SHA.BUSY: Busy register. +func (o *SHA_Type) SetBUSY_STATE(value uint32) { + volatile.StoreUint32(&o.BUSY.Reg, volatile.LoadUint32(&o.BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetBUSY_STATE() uint32 { + return volatile.LoadUint32(&o.BUSY.Reg) & 0x1 +} + +// SHA.DMA_START: DMA configuration register 1. +func (o *SHA_Type) SetDMA_START(value uint32) { + volatile.StoreUint32(&o.DMA_START.Reg, volatile.LoadUint32(&o.DMA_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_START() uint32 { + return volatile.LoadUint32(&o.DMA_START.Reg) & 0x1 +} + +// SHA.DMA_CONTINUE: DMA configuration register 2. +func (o *SHA_Type) SetDMA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.DMA_CONTINUE.Reg, volatile.LoadUint32(&o.DMA_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_CONTINUE() uint32 { + return volatile.LoadUint32(&o.DMA_CONTINUE.Reg) & 0x1 +} + +// SHA.CLEAR_IRQ: Interrupt clear register. +func (o *SHA_Type) SetCLEAR_IRQ_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CLEAR_IRQ.Reg, volatile.LoadUint32(&o.CLEAR_IRQ.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetCLEAR_IRQ_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.CLEAR_IRQ.Reg) & 0x1 +} + +// SHA.IRQ_ENA: Interrupt enable register. +func (o *SHA_Type) SetIRQ_ENA_INTERRUPT_ENA(value uint32) { + volatile.StoreUint32(&o.IRQ_ENA.Reg, volatile.LoadUint32(&o.IRQ_ENA.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetIRQ_ENA_INTERRUPT_ENA() uint32 { + return volatile.LoadUint32(&o.IRQ_ENA.Reg) & 0x1 +} + +// SHA.DATE: Date register. +func (o *SHA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SHA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// SPI (Serial Peripheral Interface) Controller 0 +type SPI0_Type struct { + _ [8]byte + CTRL volatile.Register32 // 0x8 + CTRL1 volatile.Register32 // 0xC + CTRL2 volatile.Register32 // 0x10 + CLOCK volatile.Register32 // 0x14 + USER volatile.Register32 // 0x18 + USER1 volatile.Register32 // 0x1C + USER2 volatile.Register32 // 0x20 + _ [8]byte + RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + MISC volatile.Register32 // 0x34 + _ [4]byte + CACHE_FCTRL volatile.Register32 // 0x3C + _ [20]byte + FSM volatile.Register32 // 0x54 + _ [80]byte + TIMING_CALI volatile.Register32 // 0xA8 + DIN_MODE volatile.Register32 // 0xAC + DIN_NUM volatile.Register32 // 0xB0 + DOUT_MODE volatile.Register32 // 0xB4 + _ [36]byte + CLOCK_GATE volatile.Register32 // 0xDC + CORE_CLK_SEL volatile.Register32 // 0xE0 + _ [792]byte + DATE volatile.Register32 // 0x3FC +} + +// SPI0.CTRL: SPI0 control register. +func (o *SPI0_Type) SetCTRL_FDUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetCTRL_FDUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetCTRL_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetCTRL_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetCTRL_WP(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetCTRL_WP() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetCTRL_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetCTRL_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetCTRL_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetCTRL_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} + +// SPI0.CTRL1: SPI0 control1 register. +func (o *SPI0_Type) SetCTRL1_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetCTRL1_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.CTRL1.Reg) & 0x3 +} +func (o *SPI0_Type) SetCTRL1_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetCTRL1_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0x40000000) >> 30 +} + +// SPI0.CTRL2: SPI0 control2 register. +func (o *SPI0_Type) SetCTRL2_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1f)|value) +} +func (o *SPI0_Type) GetCTRL2_CS_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1f +} +func (o *SPI0_Type) SetCTRL2_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x3e0)|value<<5) +} +func (o *SPI0_Type) GetCTRL2_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x3e0) >> 5 +} +func (o *SPI0_Type) SetCTRL2_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetCTRL2_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x7e000000) >> 25 +} +func (o *SPI0_Type) SetCTRL2_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetCTRL2_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI0.CLOCK: SPI clock division control register. +func (o *SPI0_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0xff +} +func (o *SPI0_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI0.USER: SPI0 user register. +func (o *SPI0_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} + +// SPI0.USER1: SPI0 user1 register. +func (o *SPI0_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3f)|value) +} +func (o *SPI0_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0x3f +} +func (o *SPI0_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI0_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI0.USER2: SPI0 user2 register. +func (o *SPI0_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI0_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI0.RD_STATUS: SPI0 read control register. +func (o *SPI0_Type) SetRD_STATUS_WB_MODE(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetRD_STATUS_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI0.MISC: SPI0 misc register +func (o *SPI0_Type) SetMISC_TRANS_END(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetMISC_TRANS_END() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetMISC_TRANS_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetMISC_TRANS_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetMISC_CSPI_ST_TRANS_END(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetMISC_CSPI_ST_TRANS_END() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetMISC_CSPI_ST_TRANS_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetMISC_CSPI_ST_TRANS_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x400) >> 10 +} + +// SPI0.CACHE_FCTRL: SPI0 bit mode control register. +func (o *SPI0_Type) SetCACHE_FCTRL_CACHE_REQ_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetCACHE_FCTRL_CACHE_REQ_EN() uint32 { + return volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetCACHE_FCTRL_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetCACHE_FCTRL_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetCACHE_FCTRL_CACHE_FLASH_USR_CMD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetCACHE_FCTRL_CACHE_FLASH_USR_CMD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x100) >> 8 +} + +// SPI0.FSM: SPI0 FSM status register +func (o *SPI0_Type) SetFSM_CSPI_ST(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0xf)|value) +} +func (o *SPI0_Type) GetFSM_CSPI_ST() uint32 { + return volatile.LoadUint32(&o.FSM.Reg) & 0xf +} +func (o *SPI0_Type) SetFSM_EM_ST(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0x70)|value<<4) +} +func (o *SPI0_Type) GetFSM_EM_ST() uint32 { + return (volatile.LoadUint32(&o.FSM.Reg) & 0x70) >> 4 +} +func (o *SPI0_Type) SetFSM_CSPI_LOCK_DELAY_TIME(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0xf80)|value<<7) +} +func (o *SPI0_Type) GetFSM_CSPI_LOCK_DELAY_TIME() uint32 { + return (volatile.LoadUint32(&o.FSM.Reg) & 0xf80) >> 7 +} + +// SPI0.TIMING_CALI: SPI0 timing calibration register +func (o *SPI0_Type) SetTIMING_CALI_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetTIMING_CALI_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetTIMING_CALI(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetTIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetTIMING_CALI_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetTIMING_CALI_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI0.DIN_MODE: SPI0 input delay mode control register +func (o *SPI0_Type) SetDIN_MODE_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetDIN_MODE_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3 +} +func (o *SPI0_Type) SetDIN_MODE_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetDIN_MODE_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetDIN_MODE_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetDIN_MODE_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetDIN_MODE_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetDIN_MODE_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc0) >> 6 +} + +// SPI0.DIN_NUM: SPI0 input delay number control register +func (o *SPI0_Type) SetDIN_NUM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetDIN_NUM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetDIN_NUM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetDIN_NUM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetDIN_NUM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetDIN_NUM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetDIN_NUM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetDIN_NUM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc0) >> 6 +} + +// SPI0.DOUT_MODE: SPI0 output delay mode control register +func (o *SPI0_Type) SetDOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x8) >> 3 +} + +// SPI0.CLOCK_GATE: SPI0 clk_gate register +func (o *SPI0_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SPI0.CORE_CLK_SEL: SPI0 module clock select register +func (o *SPI0_Type) SetCORE_CLK_SEL_SPI01_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetCORE_CLK_SEL_SPI01_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0x3 +} + +// SPI0.DATE: Version control register +func (o *SPI0_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI0_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 1 +type SPI1_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CTRL1 volatile.Register32 // 0xC + CTRL2 volatile.Register32 // 0x10 + CLOCK volatile.Register32 // 0x14 + USER volatile.Register32 // 0x18 + USER1 volatile.Register32 // 0x1C + USER2 volatile.Register32 // 0x20 + MOSI_DLEN volatile.Register32 // 0x24 + MISO_DLEN volatile.Register32 // 0x28 + RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + MISC volatile.Register32 // 0x34 + TX_CRC volatile.Register32 // 0x38 + CACHE_FCTRL volatile.Register32 // 0x3C + _ [24]byte + W0 volatile.Register32 // 0x58 + W1 volatile.Register32 // 0x5C + W2 volatile.Register32 // 0x60 + W3 volatile.Register32 // 0x64 + W4 volatile.Register32 // 0x68 + W5 volatile.Register32 // 0x6C + W6 volatile.Register32 // 0x70 + W7 volatile.Register32 // 0x74 + W8 volatile.Register32 // 0x78 + W9 volatile.Register32 // 0x7C + W10 volatile.Register32 // 0x80 + W11 volatile.Register32 // 0x84 + W12 volatile.Register32 // 0x88 + W13 volatile.Register32 // 0x8C + W14 volatile.Register32 // 0x90 + W15 volatile.Register32 // 0x94 + FLASH_WAITI_CTRL volatile.Register32 // 0x98 + FLASH_SUS_CTRL volatile.Register32 // 0x9C + FLASH_SUS_CMD volatile.Register32 // 0xA0 + SUS_STATUS volatile.Register32 // 0xA4 + TIMING_CALI volatile.Register32 // 0xA8 + _ [20]byte + INT_ENA volatile.Register32 // 0xC0 + INT_CLR volatile.Register32 // 0xC4 + INT_RAW volatile.Register32 // 0xC8 + INT_ST volatile.Register32 // 0xCC + _ [12]byte + CLOCK_GATE volatile.Register32 // 0xDC + _ [796]byte + DATE volatile.Register32 // 0x3FC +} + +// SPI1.CMD: SPI1 memory command register +func (o *SPI1_Type) SetCMD_SPI1_MST_ST(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0xf)|value) +} +func (o *SPI1_Type) GetCMD_SPI1_MST_ST() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0xf +} +func (o *SPI1_Type) SetCMD_MSPI_ST(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0xf0)|value<<4) +} +func (o *SPI1_Type) GetCMD_MSPI_ST() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0xf0) >> 4 +} +func (o *SPI1_Type) SetCMD_FLASH_PE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI1_Type) GetCMD_FLASH_PE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI1_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetCMD_FLASH_HPM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetCMD_FLASH_HPM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetCMD_FLASH_RES(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetCMD_FLASH_RES() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetCMD_FLASH_DP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetCMD_FLASH_DP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetCMD_FLASH_CE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetCMD_FLASH_CE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetCMD_FLASH_BE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetCMD_FLASH_BE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetCMD_FLASH_SE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetCMD_FLASH_SE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetCMD_FLASH_PP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetCMD_FLASH_PP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetCMD_FLASH_WRSR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetCMD_FLASH_WRSR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetCMD_FLASH_RDSR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetCMD_FLASH_RDSR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetCMD_FLASH_RDID(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetCMD_FLASH_RDID() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetCMD_FLASH_WRDI(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetCMD_FLASH_WRDI() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetCMD_FLASH_WREN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetCMD_FLASH_WREN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetCMD_FLASH_READ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetCMD_FLASH_READ() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31 +} + +// SPI1.ADDR: SPI1 address register +func (o *SPI1_Type) SetADDR(value uint32) { + volatile.StoreUint32(&o.ADDR.Reg, value) +} +func (o *SPI1_Type) GetADDR() uint32 { + return volatile.LoadUint32(&o.ADDR.Reg) +} + +// SPI1.CTRL: SPI1 control register. +func (o *SPI1_Type) SetCTRL_FDUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetCTRL_FDUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI1_Type) SetCTRL_FCS_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetCTRL_FCS_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI1_Type) SetCTRL_TX_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SPI1_Type) GetCTRL_TX_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11 +} +func (o *SPI1_Type) SetCTRL_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetCTRL_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetCTRL_RESANDRES(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetCTRL_RESANDRES() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetCTRL_WP(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetCTRL_WP() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetCTRL_WRSR_2B(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetCTRL_WRSR_2B() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetCTRL_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetCTRL_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetCTRL_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetCTRL_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} + +// SPI1.CTRL1: SPI1 control1 register. +func (o *SPI1_Type) SetCTRL1_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI1_Type) GetCTRL1_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.CTRL1.Reg) & 0x3 +} +func (o *SPI1_Type) SetCTRL1_CS_HOLD_DLY_RES(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0xffc)|value<<2) +} +func (o *SPI1_Type) GetCTRL1_CS_HOLD_DLY_RES() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0xffc) >> 2 +} + +// SPI1.CTRL2: SPI1 control2 register. +func (o *SPI1_Type) SetCTRL2_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetCTRL2_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI1.CLOCK: SPI1 clock division control register. +func (o *SPI1_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0xff +} +func (o *SPI1_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI1_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI1.USER: SPI1 user register. +func (o *SPI1_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI1_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI1_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetUSER_FWRITE_DIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetUSER_FWRITE_DIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetUSER_FWRITE_QIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetUSER_FWRITE_QIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI1.USER1: SPI1 user1 register. +func (o *SPI1_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3f)|value) +} +func (o *SPI1_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0x3f +} +func (o *SPI1_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI1_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI1.USER2: SPI1 user2 register. +func (o *SPI1_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI1_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI1_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI1.MOSI_DLEN: SPI1 send data bit length control register. +func (o *SPI1_Type) SetMOSI_DLEN_USR_MOSI_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MOSI_DLEN.Reg, volatile.LoadUint32(&o.MOSI_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetMOSI_DLEN_USR_MOSI_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MOSI_DLEN.Reg) & 0x3ff +} + +// SPI1.MISO_DLEN: SPI1 receive data bit length control register. +func (o *SPI1_Type) SetMISO_DLEN_USR_MISO_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MISO_DLEN.Reg, volatile.LoadUint32(&o.MISO_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetMISO_DLEN_USR_MISO_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MISO_DLEN.Reg) & 0x3ff +} + +// SPI1.RD_STATUS: SPI1 status register. +func (o *SPI1_Type) SetRD_STATUS_STATUS(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetRD_STATUS_STATUS() uint32 { + return volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xffff +} +func (o *SPI1_Type) SetRD_STATUS_WB_MODE(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetRD_STATUS_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI1.MISC: SPI1 misc register +func (o *SPI1_Type) SetMISC_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetMISC_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.MISC.Reg) & 0x1 +} +func (o *SPI1_Type) SetMISC_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetMISC_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x400) >> 10 +} + +// SPI1.TX_CRC: SPI1 TX CRC data register. +func (o *SPI1_Type) SetTX_CRC(value uint32) { + volatile.StoreUint32(&o.TX_CRC.Reg, value) +} +func (o *SPI1_Type) GetTX_CRC() uint32 { + return volatile.LoadUint32(&o.TX_CRC.Reg) +} + +// SPI1.CACHE_FCTRL: SPI1 bit mode control register. +func (o *SPI1_Type) SetCACHE_FCTRL_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetCACHE_FCTRL_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x100) >> 8 +} + +// SPI1.W0: SPI1 memory data buffer0 +func (o *SPI1_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI1_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI1.W1: SPI1 memory data buffer1 +func (o *SPI1_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI1_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI1.W2: SPI1 memory data buffer2 +func (o *SPI1_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI1_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI1.W3: SPI1 memory data buffer3 +func (o *SPI1_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI1_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI1.W4: SPI1 memory data buffer4 +func (o *SPI1_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI1_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI1.W5: SPI1 memory data buffer5 +func (o *SPI1_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI1_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI1.W6: SPI1 memory data buffer6 +func (o *SPI1_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI1_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI1.W7: SPI1 memory data buffer7 +func (o *SPI1_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI1_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI1.W8: SPI1 memory data buffer8 +func (o *SPI1_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI1_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI1.W9: SPI1 memory data buffer9 +func (o *SPI1_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI1_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI1.W10: SPI1 memory data buffer10 +func (o *SPI1_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI1_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI1.W11: SPI1 memory data buffer11 +func (o *SPI1_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI1_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI1.W12: SPI1 memory data buffer12 +func (o *SPI1_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI1_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI1.W13: SPI1 memory data buffer13 +func (o *SPI1_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI1_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI1.W14: SPI1 memory data buffer14 +func (o *SPI1_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI1_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI1.W15: SPI1 memory data buffer15 +func (o *SPI1_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI1_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI1.FLASH_WAITI_CTRL: SPI1 wait idle control register +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_DUMMY(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_DUMMY() uint32 { + return (volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_CMD(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0x3fc)|value<<2) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_CMD() uint32 { + return (volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0x3fc) >> 2 +} +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0xfc00)|value<<10) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0xfc00) >> 10 +} + +// SPI1.FLASH_SUS_CTRL: SPI1 flash suspend control register +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PER(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PER() uint32 { + return volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PES(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PES() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PER_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PER_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PES_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PES_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_PES_PER_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_PES_PER_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PES_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PES_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_PESR_END_MSK(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x3fffc0)|value<<6) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_PESR_END_MSK() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x3fffc0) >> 6 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_RD_SUS_2B(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_RD_SUS_2B() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_PER_END_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_PER_END_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_PES_END_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_PES_END_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_SUS_TIMEOUT_CNT(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0xfe000000)|value<<25) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_SUS_TIMEOUT_CNT() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0xfe000000) >> 25 +} + +// SPI1.FLASH_SUS_CMD: SPI1 flash suspend command register +func (o *SPI1_Type) SetFLASH_SUS_CMD_FLASH_PER_COMMAND(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_FLASH_PER_COMMAND() uint32 { + return volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0xff +} +func (o *SPI1_Type) SetFLASH_SUS_CMD_FLASH_PES_COMMAND(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_FLASH_PES_COMMAND() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetFLASH_SUS_CMD_WAIT_PESR_COMMAND(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_WAIT_PESR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SUS_STATUS: SPI1 flash suspend status register +func (o *SPI1_Type) SetSUS_STATUS_FLASH_SUS(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_SUS() uint32 { + return volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x1 +} +func (o *SPI1_Type) SetSUS_STATUS_WAIT_PESR_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSUS_STATUS_WAIT_PESR_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_HPM_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_HPM_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_RES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_RES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_DP_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_DP_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_PER_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_PER_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_PES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_PES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSUS_STATUS_SPI0_LOCK_EN(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetSUS_STATUS_SPI0_LOCK_EN() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x80) >> 7 +} + +// SPI1.TIMING_CALI: SPI1 timing control register +func (o *SPI1_Type) SetTIMING_CALI(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetTIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetTIMING_CALI_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI1_Type) GetTIMING_CALI_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI1.INT_ENA: SPI1 interrupt enable register +func (o *SPI1_Type) SetINT_ENA_PER_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_ENA_PER_END_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_ENA_PES_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_ENA_PES_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_ENA_WPE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_ENA_WPE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_ENA_SLV_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_ENA_SLV_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetINT_ENA_MST_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetINT_ENA_MST_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} + +// SPI1.INT_CLR: SPI1 interrupt clear register +func (o *SPI1_Type) SetINT_CLR_PER_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_CLR_PER_END_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_CLR_PES_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_CLR_PES_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_CLR_WPE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_CLR_WPE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_CLR_SLV_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_CLR_SLV_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetINT_CLR_MST_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetINT_CLR_MST_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} + +// SPI1.INT_RAW: SPI1 interrupt raw register +func (o *SPI1_Type) SetINT_RAW_PER_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_RAW_PER_END_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_RAW_PES_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_RAW_PES_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_RAW_WPE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_RAW_WPE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_RAW_SLV_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_RAW_SLV_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetINT_RAW_MST_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetINT_RAW_MST_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} + +// SPI1.INT_ST: SPI1 interrupt status register +func (o *SPI1_Type) SetINT_ST_PER_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_ST_PER_END_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_ST_PES_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_ST_PES_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_ST_WPE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_ST_WPE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_ST_SLV_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_ST_SLV_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetINT_ST_MST_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetINT_ST_MST_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} + +// SPI1.CLOCK_GATE: SPI1 clk_gate register +func (o *SPI1_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SPI1.DATE: Version control register +func (o *SPI1_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI1_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 2 +type SPI2_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CLOCK volatile.Register32 // 0xC + USER volatile.Register32 // 0x10 + USER1 volatile.Register32 // 0x14 + USER2 volatile.Register32 // 0x18 + MS_DLEN volatile.Register32 // 0x1C + MISC volatile.Register32 // 0x20 + DIN_MODE volatile.Register32 // 0x24 + DIN_NUM volatile.Register32 // 0x28 + DOUT_MODE volatile.Register32 // 0x2C + DMA_CONF volatile.Register32 // 0x30 + DMA_INT_ENA volatile.Register32 // 0x34 + DMA_INT_CLR volatile.Register32 // 0x38 + DMA_INT_RAW volatile.Register32 // 0x3C + DMA_INT_ST volatile.Register32 // 0x40 + _ [84]byte + W0 volatile.Register32 // 0x98 + W1 volatile.Register32 // 0x9C + W2 volatile.Register32 // 0xA0 + W3 volatile.Register32 // 0xA4 + W4 volatile.Register32 // 0xA8 + W5 volatile.Register32 // 0xAC + W6 volatile.Register32 // 0xB0 + W7 volatile.Register32 // 0xB4 + W8 volatile.Register32 // 0xB8 + W9 volatile.Register32 // 0xBC + W10 volatile.Register32 // 0xC0 + W11 volatile.Register32 // 0xC4 + W12 volatile.Register32 // 0xC8 + W13 volatile.Register32 // 0xCC + W14 volatile.Register32 // 0xD0 + W15 volatile.Register32 // 0xD4 + _ [8]byte + SLAVE volatile.Register32 // 0xE0 + SLAVE1 volatile.Register32 // 0xE4 + CLK_GATE volatile.Register32 // 0xE8 + _ [4]byte + DATE volatile.Register32 // 0xF0 +} + +// SPI2.CMD: Command control register +func (o *SPI2_Type) SetCMD_CONF_BITLEN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetCMD_CONF_BITLEN() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetCMD_UPDATE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetCMD_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} + +// SPI2.ADDR: Address value register +func (o *SPI2_Type) SetADDR(value uint32) { + volatile.StoreUint32(&o.ADDR.Reg, value) +} +func (o *SPI2_Type) GetADDR() uint32 { + return volatile.LoadUint32(&o.ADDR.Reg) +} + +// SPI2.CTRL: SPI control register +func (o *SPI2_Type) SetCTRL_DUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetCTRL_DUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetCTRL_HOLD_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetCTRL_HOLD_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetCTRL_WP_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetCTRL_WP_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetCTRL_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI2_Type) GetCTRL_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000000) >> 25 +} +func (o *SPI2_Type) SetCTRL_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetCTRL_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000000) >> 26 +} + +// SPI2.CLOCK: SPI clock control register +func (o *SPI2_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI2_Type) SetCLOCK_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3c0000)|value<<18) +} +func (o *SPI2_Type) GetCLOCK_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3c0000) >> 18 +} +func (o *SPI2_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER: SPI USER control register +func (o *SPI2_Type) SetUSER_DOUTDIN(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetUSER_DOUTDIN() uint32 { + return volatile.LoadUint32(&o.USER.Reg) & 0x1 +} +func (o *SPI2_Type) SetUSER_QPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetUSER_QPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetUSER_TSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetUSER_TSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetUSER_RSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetUSER_RSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetUSER_USR_CONF_NXT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetUSER_USR_CONF_NXT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetUSER_SIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetUSER_SIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI2_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER1: SPI USER control register 1 +func (o *SPI2_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xff)|value) +} +func (o *SPI2_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0xff +} +func (o *SPI2_Type) SetUSER1_MST_WFULL_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetUSER1_MST_WFULL_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetUSER1_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3e0000)|value<<17) +} +func (o *SPI2_Type) GetUSER1_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x3e0000) >> 17 +} +func (o *SPI2_Type) SetUSER1_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x7c00000)|value<<22) +} +func (o *SPI2_Type) GetUSER1_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x7c00000) >> 22 +} +func (o *SPI2_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xf8000000) >> 27 +} + +// SPI2.USER2: SPI USER control register 2 +func (o *SPI2_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI2_Type) SetUSER2_MST_REMPTY_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER2_MST_REMPTY_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI2.MS_DLEN: SPI data bit length control register +func (o *SPI2_Type) SetMS_DLEN_MS_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.MS_DLEN.Reg, volatile.LoadUint32(&o.MS_DLEN.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetMS_DLEN_MS_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.MS_DLEN.Reg) & 0x3ffff +} + +// SPI2.MISC: SPI misc register +func (o *SPI2_Type) SetMISC_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetMISC_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.MISC.Reg) & 0x1 +} +func (o *SPI2_Type) SetMISC_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetMISC_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetMISC_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetMISC_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetMISC_CS3_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetMISC_CS3_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetMISC_CS4_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetMISC_CS4_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetMISC_CS5_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetMISC_CS5_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetMISC_CK_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetMISC_CK_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetMISC_MASTER_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1f80)|value<<7) +} +func (o *SPI2_Type) GetMISC_MASTER_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1f80) >> 7 +} +func (o *SPI2_Type) SetMISC_SLAVE_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetMISC_SLAVE_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetMISC_QUAD_DIN_PIN_SWAP(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetMISC_QUAD_DIN_PIN_SWAP() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000000) >> 31 +} + +// SPI2.DIN_MODE: SPI input delay mode configuration +func (o *SPI2_Type) SetDIN_MODE_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_MODE_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_MODE_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_MODE_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_MODE_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_MODE_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_MODE_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_MODE_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetDIN_MODE_TIMING_HCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDIN_MODE_TIMING_HCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x10000) >> 16 +} + +// SPI2.DIN_NUM: SPI input delay number configuration +func (o *SPI2_Type) SetDIN_NUM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_NUM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_NUM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_NUM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_NUM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_NUM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_NUM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_NUM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc0) >> 6 +} + +// SPI2.DOUT_MODE: SPI output delay mode configuration +func (o *SPI2_Type) SetDOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x8) >> 3 +} + +// SPI2.DMA_CONF: SPI DMA control register +func (o *SPI2_Type) SetDMA_CONF_DMA_SLV_SEG_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_SLV_SEG_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetDMA_CONF_RX_EOF_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetDMA_CONF_RX_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_RX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_RX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_TX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_TX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetDMA_CONF_RX_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetDMA_CONF_RX_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetDMA_CONF_BUF_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetDMA_CONF_BUF_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// SPI2.DMA_INT_ENA: SPI DMA interrupt enable register +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EX_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EX_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EN_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EN_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMDA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMDA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ENA_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ENA_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_CLR: SPI DMA interrupt clear register +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EX_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EX_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EN_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EN_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD8_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD8_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD9_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD9_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMDA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMDA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_CLR_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_CLR_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_RAW: SPI DMA interrupt raw register +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EX_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EX_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EN_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EN_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD8_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD8_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD9_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD9_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMDA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMDA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_RAW_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_RAW_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_ST: SPI DMA interrupt status register +func (o *SPI2_Type) SetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EX_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EX_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EN_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EN_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD7_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD8_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD8_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD9_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD9_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMDA_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMDA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ST_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ST_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100000) >> 20 +} + +// SPI2.W0: SPI CPU-controlled buffer0 +func (o *SPI2_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI2_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI2.W1: SPI CPU-controlled buffer1 +func (o *SPI2_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI2_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI2.W2: SPI CPU-controlled buffer2 +func (o *SPI2_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI2_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI2.W3: SPI CPU-controlled buffer3 +func (o *SPI2_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI2_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI2.W4: SPI CPU-controlled buffer4 +func (o *SPI2_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI2_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI2.W5: SPI CPU-controlled buffer5 +func (o *SPI2_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI2_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI2.W6: SPI CPU-controlled buffer6 +func (o *SPI2_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI2_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI2.W7: SPI CPU-controlled buffer7 +func (o *SPI2_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI2_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI2.W8: SPI CPU-controlled buffer8 +func (o *SPI2_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI2_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI2.W9: SPI CPU-controlled buffer9 +func (o *SPI2_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI2_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI2.W10: SPI CPU-controlled buffer10 +func (o *SPI2_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI2_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI2.W11: SPI CPU-controlled buffer11 +func (o *SPI2_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI2_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI2.W12: SPI CPU-controlled buffer12 +func (o *SPI2_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI2_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI2.W13: SPI CPU-controlled buffer13 +func (o *SPI2_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI2_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI2.W14: SPI CPU-controlled buffer14 +func (o *SPI2_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI2_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI2.W15: SPI CPU-controlled buffer15 +func (o *SPI2_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI2_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI2.SLAVE: SPI slave control register +func (o *SPI2_Type) SetSLAVE_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SLAVE.Reg) & 0x3 +} +func (o *SPI2_Type) SetSLAVE_CLK_MODE_13(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE_13() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSLAVE_RSCK_DATA_OUT(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSLAVE_RSCK_DATA_OUT() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSLAVE_DMA_SEG_MAGIC_VALUE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3c00000)|value<<22) +} +func (o *SPI2_Type) GetSLAVE_DMA_SEG_MAGIC_VALUE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x3c00000) >> 22 +} +func (o *SPI2_Type) SetSLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetSLAVE_SOFT_RESET(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetSLAVE_SOFT_RESET() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetSLAVE_USR_CONF(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetSLAVE_USR_CONF() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x10000000) >> 28 +} + +// SPI2.SLAVE1: SPI slave control register 1 +func (o *SPI2_Type) SetSLAVE1_SLV_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetSLAVE1_SLV_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_COMMAND(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3fc0000)|value<<18) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3fc0000) >> 18 +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_ADDR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0xfc000000) >> 26 +} + +// SPI2.CLK_GATE: SPI module clock and register clock control +func (o *SPI2_Type) SetCLK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetCLK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x4) >> 2 +} + +// SPI2.DATE: Version control +func (o *SPI2_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI2_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// System Configuration Registers +type SYSTEM_Type struct { + CPU_PERI_CLK_EN volatile.Register32 // 0x0 + CPU_PERI_RST_EN volatile.Register32 // 0x4 + CPU_PER_CONF volatile.Register32 // 0x8 + MEM_PD_MASK volatile.Register32 // 0xC + PERIP_CLK_EN0 volatile.Register32 // 0x10 + PERIP_CLK_EN1 volatile.Register32 // 0x14 + PERIP_RST_EN0 volatile.Register32 // 0x18 + PERIP_RST_EN1 volatile.Register32 // 0x1C + BT_LPCK_DIV_INT volatile.Register32 // 0x20 + BT_LPCK_DIV_FRAC volatile.Register32 // 0x24 + CPU_INTR_FROM_CPU_0 volatile.Register32 // 0x28 + CPU_INTR_FROM_CPU_1 volatile.Register32 // 0x2C + CPU_INTR_FROM_CPU_2 volatile.Register32 // 0x30 + CPU_INTR_FROM_CPU_3 volatile.Register32 // 0x34 + RSA_PD_CTRL volatile.Register32 // 0x38 + EDMA_CTRL volatile.Register32 // 0x3C + CACHE_CONTROL volatile.Register32 // 0x40 + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL volatile.Register32 // 0x44 + RTC_FASTMEM_CONFIG volatile.Register32 // 0x48 + RTC_FASTMEM_CRC volatile.Register32 // 0x4C + REDUNDANT_ECO_CTRL volatile.Register32 // 0x50 + CLOCK_GATE volatile.Register32 // 0x54 + SYSCLK_CONF volatile.Register32 // 0x58 + MEM_PVT volatile.Register32 // 0x5C + COMB_PVT_LVT_CONF volatile.Register32 // 0x60 + COMB_PVT_NVT_CONF volatile.Register32 // 0x64 + COMB_PVT_HVT_CONF volatile.Register32 // 0x68 + COMB_PVT_ERR_LVT_SITE0 volatile.Register32 // 0x6C + COMB_PVT_ERR_NVT_SITE0 volatile.Register32 // 0x70 + COMB_PVT_ERR_HVT_SITE0 volatile.Register32 // 0x74 + COMB_PVT_ERR_LVT_SITE1 volatile.Register32 // 0x78 + COMB_PVT_ERR_NVT_SITE1 volatile.Register32 // 0x7C + COMB_PVT_ERR_HVT_SITE1 volatile.Register32 // 0x80 + COMB_PVT_ERR_LVT_SITE2 volatile.Register32 // 0x84 + COMB_PVT_ERR_NVT_SITE2 volatile.Register32 // 0x88 + COMB_PVT_ERR_HVT_SITE2 volatile.Register32 // 0x8C + COMB_PVT_ERR_LVT_SITE3 volatile.Register32 // 0x90 + COMB_PVT_ERR_NVT_SITE3 volatile.Register32 // 0x94 + COMB_PVT_ERR_HVT_SITE3 volatile.Register32 // 0x98 + _ [3936]byte + SYSTEM_REG_DATE volatile.Register32 // 0xFFC +} + +// SYSTEM.CPU_PERI_CLK_EN: cpu_peripheral clock gating register +func (o *SYSTEM_Type) SetCPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_CLK_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetCPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_CLK_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg) & 0x80) >> 7 +} + +// SYSTEM.CPU_PERI_RST_EN: cpu_peripheral reset register +func (o *SYSTEM_Type) SetCPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_RST_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetCPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_RST_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg) & 0x80) >> 7 +} + +// SYSTEM.CPU_PER_CONF: cpu clock config register +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x3)|value) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPUPERIOD_SEL() uint32 { + return volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x3 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_PLL_FREQ_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_PLL_FREQ_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPU_WAITI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPU_WAITI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0xf0) >> 4 +} + +// SYSTEM.MEM_PD_MASK: memory power down mask register +func (o *SYSTEM_Type) SetMEM_PD_MASK_LSLP_MEM_PD_MASK(value uint32) { + volatile.StoreUint32(&o.MEM_PD_MASK.Reg, volatile.LoadUint32(&o.MEM_PD_MASK.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetMEM_PD_MASK_LSLP_MEM_PD_MASK() uint32 { + return volatile.LoadUint32(&o.MEM_PD_MASK.Reg) & 0x1 +} + +// SYSTEM.PERIP_CLK_EN0: peripheral clock gating register +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERS_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI01_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI01_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_WDG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_WDG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2S0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2S0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2C_EXT0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2C_EXT0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UHCI0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UHCI0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_RMT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_RMT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PCNT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PCNT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x400) >> 10 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_LEDC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x800)|value<<11) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_LEDC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x800) >> 11 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UHCI1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UHCI1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1000) >> 12 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERGROUP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERGROUP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2000) >> 13 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_EFUSE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4000)|value<<14) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_EFUSE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4000) >> 14 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERGROUP1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x8000)|value<<15) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERGROUP1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x8000) >> 15 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10000) >> 16 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20000) >> 17 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_EXT1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_EXT1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40000) >> 18 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TWAI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TWAI_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80000) >> 19 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x100000) >> 20 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2S1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2S1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x200000) >> 21 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI2_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI2_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x400000) >> 22 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_USB_DEVICE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_USB_DEVICE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x800000) >> 23 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI3_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI3_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_APB_SARADC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_APB_SARADC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10000000) >> 28 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SYSTIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SYSTIMER_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20000000) >> 29 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_ADC2_ARB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_ADC2_ARB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40000000) >> 30 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI4_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI4_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.PERIP_CLK_EN1: peripheral clock gating register +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_AES_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_AES_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_SHA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_SHA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_RSA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_RSA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_DS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_DS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_SDIO_HOST_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_SDIO_HOST_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_LCD_CAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_LCD_CAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_UART2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_UART2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_TSENS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_TSENS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x400) >> 10 +} + +// SYSTEM.PERIP_RST_EN0: reserved +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERS_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERS_RST() uint32 { + return volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI01_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI01_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_WDG_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_WDG_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2S0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2S0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2C_EXT0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2C_EXT0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UHCI0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UHCI0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_RMT_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_RMT_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PCNT_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PCNT_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x400) >> 10 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_LEDC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x800)|value<<11) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_LEDC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x800) >> 11 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UHCI1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UHCI1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1000) >> 12 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERGROUP_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERGROUP_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2000) >> 13 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_EFUSE_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4000)|value<<14) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_EFUSE_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4000) >> 14 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERGROUP1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x8000)|value<<15) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERGROUP1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x8000) >> 15 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI3_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI3_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10000) >> 16 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20000) >> 17 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_EXT1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_EXT1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40000) >> 18 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TWAI_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TWAI_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80000) >> 19 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x100000) >> 20 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2S1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2S1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x200000) >> 21 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI2_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI2_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x400000) >> 22 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_USB_DEVICE_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_USB_DEVICE_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x800000) >> 23 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART_MEM_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM3_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM3_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI3_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI3_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_APB_SARADC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_APB_SARADC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10000000) >> 28 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SYSTIMER_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SYSTIMER_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20000000) >> 29 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_ADC2_ARB_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_ADC2_ARB_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40000000) >> 30 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI4_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI4_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.PERIP_RST_EN1: peripheral reset register +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_AES_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_AES_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_SHA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_SHA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_RSA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_RSA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_DS_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_DS_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_HMAC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_HMAC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_SDIO_HOST_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_SDIO_HOST_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_LCD_CAM_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_LCD_CAM_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_UART2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_UART2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_TSENS_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_TSENS_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x400) >> 10 +} + +// SYSTEM.BT_LPCK_DIV_INT: clock config register +func (o *SYSTEM_Type) SetBT_LPCK_DIV_INT_BT_LPCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_INT.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg)&^(0xfff)|value) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_INT_BT_LPCK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg) & 0xfff +} + +// SYSTEM.BT_LPCK_DIV_FRAC: clock config register +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_B(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0xfff)|value) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_B() uint32 { + return volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0xfff +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_A(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0xfff000)|value<<12) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0xfff000) >> 12 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_RTC_EN(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_RTC_EN() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x10000000) >> 28 +} + +// SYSTEM.CPU_INTR_FROM_CPU_0: interrupt generate register +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_0(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_0() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_1: interrupt generate register +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_1(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_1() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_2: interrupt generate register +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_2(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_2() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_3: interrupt generate register +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_3(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_3() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg) & 0x1 +} + +// SYSTEM.RSA_PD_CTRL: rsa memory power control register +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_PD() uint32 { + return volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x4) >> 2 +} + +// SYSTEM.EDMA_CTRL: EDMA clock and reset register +func (o *SYSTEM_Type) SetEDMA_CTRL_EDMA_CLK_ON(value uint32) { + volatile.StoreUint32(&o.EDMA_CTRL.Reg, volatile.LoadUint32(&o.EDMA_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetEDMA_CTRL_EDMA_CLK_ON() uint32 { + return volatile.LoadUint32(&o.EDMA_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetEDMA_CTRL_EDMA_RESET(value uint32) { + volatile.StoreUint32(&o.EDMA_CTRL.Reg, volatile.LoadUint32(&o.EDMA_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetEDMA_CTRL_EDMA_RESET() uint32 { + return (volatile.LoadUint32(&o.EDMA_CTRL.Reg) & 0x2) >> 1 +} + +// SYSTEM.CACHE_CONTROL: cache control register +func (o *SYSTEM_Type) SetCACHE_CONTROL_ICACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_ICACHE_CLK_ON() uint32 { + return volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_ICACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_ICACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_DCACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_DCACHE_CLK_ON() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_DCACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_DCACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x8) >> 3 +} + +// SYSTEM.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x8) >> 3 +} + +// SYSTEM.RTC_FASTMEM_CONFIG: fast memory config register +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_START(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_START() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0xffe00)|value<<9) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0xffe00) >> 9 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x7ff00000)|value<<20) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x7ff00000) >> 20 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.RTC_FASTMEM_CRC: reserved +func (o *SYSTEM_Type) SetRTC_FASTMEM_CRC(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CRC.Reg, value) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CRC() uint32 { + return volatile.LoadUint32(&o.RTC_FASTMEM_CRC.Reg) +} + +// SYSTEM.REDUNDANT_ECO_CTRL: eco register +func (o *SYSTEM_Type) SetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE(value uint32) { + volatile.StoreUint32(&o.REDUNDANT_ECO_CTRL.Reg, volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE() uint32 { + return volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.REDUNDANT_ECO_CTRL.Reg, volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg) & 0x2) >> 1 +} + +// SYSTEM.CLOCK_GATE: clock gating register +func (o *SYSTEM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SYSTEM.SYSCLK_CONF: system clock config register +func (o *SYSTEM_Type) SetSYSCLK_CONF_PRE_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x3ff)|value) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_PRE_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x3ff +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_SOC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_SOC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0xc00) >> 10 +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_CLK_XTAL_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x7f000)|value<<12) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_CLK_XTAL_FREQ() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x7f000) >> 12 +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_CLK_DIV_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_CLK_DIV_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x80000) >> 19 +} + +// SYSTEM.MEM_PVT: mem pvt register +func (o *SYSTEM_Type) SetMEM_PVT_MEM_PATH_LEN(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0xf)|value) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_PATH_LEN() uint32 { + return volatile.LoadUint32(&o.MEM_PVT.Reg) & 0xf +} +func (o *SYSTEM_Type) SetMEM_PVT_MEM_ERR_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_ERR_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetMEM_PVT_MONITOR_EN(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetMEM_PVT_MONITOR_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetMEM_PVT_MEM_TIMING_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0x3fffc0)|value<<6) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_TIMING_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0x3fffc0) >> 6 +} +func (o *SYSTEM_Type) SetMEM_PVT_MEM_VT_SEL(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0xc00000)|value<<22) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_VT_SEL() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0xc00000) >> 22 +} + +// SYSTEM.COMB_PVT_LVT_CONF: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_LVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg)&^(0x1f)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg) & 0x1f +} +func (o *SYSTEM_Type) SetCOMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_LVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetCOMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetCOMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_LVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCOMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg) & 0x40) >> 6 +} + +// SYSTEM.COMB_PVT_NVT_CONF: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_NVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg)&^(0x1f)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg) & 0x1f +} +func (o *SYSTEM_Type) SetCOMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_NVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetCOMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetCOMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_NVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCOMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg) & 0x40) >> 6 +} + +// SYSTEM.COMB_PVT_HVT_CONF: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_HVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg)&^(0x1f)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg) & 0x1f +} +func (o *SYSTEM_Type) SetCOMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_HVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetCOMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetCOMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_HVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCOMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg) & 0x40) >> 6 +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE0: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE0.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE0.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE0.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE0: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE0.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE0.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE0.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE0: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE0.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE0.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE0.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE1: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE1.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE1.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE1.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE1: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE1.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE1.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE1.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE1: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE1.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE1.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE1.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE2: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE2.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE2.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE2.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE2: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE2.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE2.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE2.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE2: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE2.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE2.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE2.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE3: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE3.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE3.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE3.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE3: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE3.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE3.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE3.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE3: mem pvt register +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE3.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE3.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE3.Reg) & 0xffff +} + +// SYSTEM.SYSTEM_REG_DATE: Version register +func (o *SYSTEM_Type) SetSYSTEM_REG_DATE(value uint32) { + volatile.StoreUint32(&o.SYSTEM_REG_DATE.Reg, volatile.LoadUint32(&o.SYSTEM_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SYSTEM_Type) GetSYSTEM_REG_DATE() uint32 { + return volatile.LoadUint32(&o.SYSTEM_REG_DATE.Reg) & 0xfffffff +} + +// System Timer +type SYSTIMER_Type struct { + CONF volatile.Register32 // 0x0 + UNIT0_OP volatile.Register32 // 0x4 + UNIT1_OP volatile.Register32 // 0x8 + UNIT0_LOAD_HI volatile.Register32 // 0xC + UNIT0_LOAD_LO volatile.Register32 // 0x10 + UNIT1_LOAD_HI volatile.Register32 // 0x14 + UNIT1_LOAD_LO volatile.Register32 // 0x18 + TARGET0_HI volatile.Register32 // 0x1C + TARGET0_LO volatile.Register32 // 0x20 + TARGET1_HI volatile.Register32 // 0x24 + TARGET1_LO volatile.Register32 // 0x28 + TARGET2_HI volatile.Register32 // 0x2C + TARGET2_LO volatile.Register32 // 0x30 + TARGET0_CONF volatile.Register32 // 0x34 + TARGET1_CONF volatile.Register32 // 0x38 + TARGET2_CONF volatile.Register32 // 0x3C + UNIT0_VALUE_HI volatile.Register32 // 0x40 + UNIT0_VALUE_LO volatile.Register32 // 0x44 + UNIT1_VALUE_HI volatile.Register32 // 0x48 + UNIT1_VALUE_LO volatile.Register32 // 0x4C + COMP0_LOAD volatile.Register32 // 0x50 + COMP1_LOAD volatile.Register32 // 0x54 + COMP2_LOAD volatile.Register32 // 0x58 + UNIT0_LOAD volatile.Register32 // 0x5C + UNIT1_LOAD volatile.Register32 // 0x60 + INT_ENA volatile.Register32 // 0x64 + INT_RAW volatile.Register32 // 0x68 + INT_CLR volatile.Register32 // 0x6C + INT_ST volatile.Register32 // 0x70 + _ [136]byte + DATE volatile.Register32 // 0xFC +} + +// SYSTIMER.CONF: SYSTIMER_CONF. +func (o *SYSTIMER_Type) SetCONF_SYSTIMER_CLK_FO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCONF_SYSTIMER_CLK_FO() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetCONF_TARGET2_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTIMER_Type) GetCONF_TARGET2_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22 +} +func (o *SYSTIMER_Type) SetCONF_TARGET1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTIMER_Type) GetCONF_TARGET1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23 +} +func (o *SYSTIMER_Type) SetCONF_TARGET0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTIMER_Type) GetCONF_TARGET0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000000) >> 26 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000000) >> 27 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000000) >> 28 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_OP: SYSTIMER_UNIT0_OP. +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT1_OP: SYSTIMER_UNIT1_OP. +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT0_LOAD_HI: SYSTIMER_UNIT0_LOAD_HI. +func (o *SYSTIMER_Type) SetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_LOAD_LO: SYSTIMER_UNIT0_LOAD_LO. +func (o *SYSTIMER_Type) SetUNIT0_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_LO.Reg) +} + +// SYSTIMER.UNIT1_LOAD_HI: SYSTIMER_UNIT1_LOAD_HI. +func (o *SYSTIMER_Type) SetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_LOAD_LO: SYSTIMER_UNIT1_LOAD_LO. +func (o *SYSTIMER_Type) SetUNIT1_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_LO.Reg) +} + +// SYSTIMER.TARGET0_HI: SYSTIMER_TARGET0_HI. +func (o *SYSTIMER_Type) SetTARGET0_HI_TIMER_TARGET0_HI(value uint32) { + volatile.StoreUint32(&o.TARGET0_HI.Reg, volatile.LoadUint32(&o.TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_HI_TIMER_TARGET0_HI() uint32 { + return volatile.LoadUint32(&o.TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET0_LO: SYSTIMER_TARGET0_LO. +func (o *SYSTIMER_Type) SetTARGET0_LO(value uint32) { + volatile.StoreUint32(&o.TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET0_LO() uint32 { + return volatile.LoadUint32(&o.TARGET0_LO.Reg) +} + +// SYSTIMER.TARGET1_HI: SYSTIMER_TARGET1_HI. +func (o *SYSTIMER_Type) SetTARGET1_HI_TIMER_TARGET1_HI(value uint32) { + volatile.StoreUint32(&o.TARGET1_HI.Reg, volatile.LoadUint32(&o.TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_HI_TIMER_TARGET1_HI() uint32 { + return volatile.LoadUint32(&o.TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET1_LO: SYSTIMER_TARGET1_LO. +func (o *SYSTIMER_Type) SetTARGET1_LO(value uint32) { + volatile.StoreUint32(&o.TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET1_LO() uint32 { + return volatile.LoadUint32(&o.TARGET1_LO.Reg) +} + +// SYSTIMER.TARGET2_HI: SYSTIMER_TARGET2_HI. +func (o *SYSTIMER_Type) SetTARGET2_HI_TIMER_TARGET2_HI(value uint32) { + volatile.StoreUint32(&o.TARGET2_HI.Reg, volatile.LoadUint32(&o.TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_HI_TIMER_TARGET2_HI() uint32 { + return volatile.LoadUint32(&o.TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET2_LO: SYSTIMER_TARGET2_LO. +func (o *SYSTIMER_Type) SetTARGET2_LO(value uint32) { + volatile.StoreUint32(&o.TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET2_LO() uint32 { + return volatile.LoadUint32(&o.TARGET2_LO.Reg) +} + +// SYSTIMER.TARGET0_CONF: SYSTIMER_TARGET0_CONF. +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET1_CONF: SYSTIMER_TARGET1_CONF. +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET2_CONF: SYSTIMER_TARGET2_CONF. +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_VALUE_HI: SYSTIMER_UNIT0_VALUE_HI. +func (o *SYSTIMER_Type) SetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_VALUE_LO: SYSTIMER_UNIT0_VALUE_LO. +func (o *SYSTIMER_Type) SetUNIT0_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_LO.Reg) +} + +// SYSTIMER.UNIT1_VALUE_HI: SYSTIMER_UNIT1_VALUE_HI. +func (o *SYSTIMER_Type) SetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_VALUE_LO: SYSTIMER_UNIT1_VALUE_LO. +func (o *SYSTIMER_Type) SetUNIT1_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_LO.Reg) +} + +// SYSTIMER.COMP0_LOAD: SYSTIMER_COMP0_LOAD. +func (o *SYSTIMER_Type) SetCOMP0_LOAD_TIMER_COMP0_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP0_LOAD.Reg, volatile.LoadUint32(&o.COMP0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP0_LOAD_TIMER_COMP0_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP1_LOAD: SYSTIMER_COMP1_LOAD. +func (o *SYSTIMER_Type) SetCOMP1_LOAD_TIMER_COMP1_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP1_LOAD.Reg, volatile.LoadUint32(&o.COMP1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP1_LOAD_TIMER_COMP1_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP2_LOAD: SYSTIMER_COMP2_LOAD. +func (o *SYSTIMER_Type) SetCOMP2_LOAD_TIMER_COMP2_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP2_LOAD.Reg, volatile.LoadUint32(&o.COMP2_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP2_LOAD_TIMER_COMP2_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP2_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT0_LOAD: SYSTIMER_UNIT0_LOAD. +func (o *SYSTIMER_Type) SetUNIT0_LOAD_TIMER_UNIT0_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD.Reg, volatile.LoadUint32(&o.UNIT0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_TIMER_UNIT0_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT1_LOAD: SYSTIMER_UNIT1_LOAD. +func (o *SYSTIMER_Type) SetUNIT1_LOAD_TIMER_UNIT1_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD.Reg, volatile.LoadUint32(&o.UNIT1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_TIMER_UNIT1_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.INT_ENA: SYSTIMER_INT_ENA. +func (o *SYSTIMER_Type) SetINT_ENA_TARGET0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_RAW: SYSTIMER_INT_RAW. +func (o *SYSTIMER_Type) SetINT_RAW_TARGET0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_CLR: SYSTIMER_INT_CLR. +func (o *SYSTIMER_Type) SetINT_CLR_TARGET0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_ST: SYSTIMER_INT_ST. +func (o *SYSTIMER_Type) SetINT_ST_TARGET0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// SYSTIMER.DATE: SYSTIMER_DATE. +func (o *SYSTIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *SYSTIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Timer Group 0 +type TIMG_Type struct { + T0CONFIG volatile.Register32 // 0x0 + T0LO volatile.Register32 // 0x4 + T0HI volatile.Register32 // 0x8 + T0UPDATE volatile.Register32 // 0xC + T0ALARMLO volatile.Register32 // 0x10 + T0ALARMHI volatile.Register32 // 0x14 + T0LOADLO volatile.Register32 // 0x18 + T0LOADHI volatile.Register32 // 0x1C + T0LOAD volatile.Register32 // 0x20 + _ [36]byte + WDTCONFIG0 volatile.Register32 // 0x48 + WDTCONFIG1 volatile.Register32 // 0x4C + WDTCONFIG2 volatile.Register32 // 0x50 + WDTCONFIG3 volatile.Register32 // 0x54 + WDTCONFIG4 volatile.Register32 // 0x58 + WDTCONFIG5 volatile.Register32 // 0x5C + WDTFEED volatile.Register32 // 0x60 + WDTWPROTECT volatile.Register32 // 0x64 + RTCCALICFG volatile.Register32 // 0x68 + RTCCALICFG1 volatile.Register32 // 0x6C + INT_ENA_TIMERS volatile.Register32 // 0x70 + INT_RAW_TIMERS volatile.Register32 // 0x74 + INT_ST_TIMERS volatile.Register32 // 0x78 + INT_CLR_TIMERS volatile.Register32 // 0x7C + RTCCALICFG2 volatile.Register32 // 0x80 + _ [116]byte + NTIMG_DATE volatile.Register32 // 0xF8 + REGCLK volatile.Register32 // 0xFC +} + +// TIMG.T0CONFIG: TIMG_T0CONFIG_REG. +func (o *TIMG_Type) SetT0CONFIG_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetT0CONFIG_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetT0CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT0CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT0CONFIG_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetT0CONFIG_DIVCNT_RST() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetT0CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT0CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT0CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT0CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT0CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT0CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT0CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0LO: TIMG_T0LO_REG. +func (o *TIMG_Type) SetT0LO(value uint32) { + volatile.StoreUint32(&o.T0LO.Reg, value) +} +func (o *TIMG_Type) GetT0LO() uint32 { + return volatile.LoadUint32(&o.T0LO.Reg) +} + +// TIMG.T0HI: TIMG_T0HI_REG. +func (o *TIMG_Type) SetT0HI_HI(value uint32) { + volatile.StoreUint32(&o.T0HI.Reg, volatile.LoadUint32(&o.T0HI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0HI_HI() uint32 { + return volatile.LoadUint32(&o.T0HI.Reg) & 0x3fffff +} + +// TIMG.T0UPDATE: TIMG_T0UPDATE_REG. +func (o *TIMG_Type) SetT0UPDATE_UPDATE(value uint32) { + volatile.StoreUint32(&o.T0UPDATE.Reg, volatile.LoadUint32(&o.T0UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0UPDATE_UPDATE() uint32 { + return (volatile.LoadUint32(&o.T0UPDATE.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0ALARMLO: TIMG_T0ALARMLO_REG. +func (o *TIMG_Type) SetT0ALARMLO(value uint32) { + volatile.StoreUint32(&o.T0ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMLO() uint32 { + return volatile.LoadUint32(&o.T0ALARMLO.Reg) +} + +// TIMG.T0ALARMHI: TIMG_T0ALARMHI_REG. +func (o *TIMG_Type) SetT0ALARMHI_ALARM_HI(value uint32) { + volatile.StoreUint32(&o.T0ALARMHI.Reg, volatile.LoadUint32(&o.T0ALARMHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0ALARMHI_ALARM_HI() uint32 { + return volatile.LoadUint32(&o.T0ALARMHI.Reg) & 0x3fffff +} + +// TIMG.T0LOADLO: TIMG_T0LOADLO_REG. +func (o *TIMG_Type) SetT0LOADLO(value uint32) { + volatile.StoreUint32(&o.T0LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT0LOADLO() uint32 { + return volatile.LoadUint32(&o.T0LOADLO.Reg) +} + +// TIMG.T0LOADHI: TIMG_T0LOADHI_REG. +func (o *TIMG_Type) SetT0LOADHI_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.T0LOADHI.Reg, volatile.LoadUint32(&o.T0LOADHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0LOADHI_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.T0LOADHI.Reg) & 0x3fffff +} + +// TIMG.T0LOAD: TIMG_T0LOAD_REG. +func (o *TIMG_Type) SetT0LOAD(value uint32) { + volatile.StoreUint32(&o.T0LOAD.Reg, value) +} +func (o *TIMG_Type) GetT0LOAD() uint32 { + return volatile.LoadUint32(&o.T0LOAD.Reg) +} + +// TIMG.WDTCONFIG0: TIMG_WDTCONFIG0_REG. +func (o *TIMG_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x2000)|value<<13) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x2000) >> 13 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x4000)|value<<14) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x4000) >> 14 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x38000)|value<<15) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x38000) >> 15 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c0000)|value<<18) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c0000) >> 18 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200000)|value<<21) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200000) >> 21 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CONF_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400000)|value<<22) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CONF_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400000) >> 22 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1800000)|value<<23) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1800000) >> 23 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x6000000)|value<<25) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x6000000) >> 25 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x18000000)|value<<27) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x18000000) >> 27 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x60000000)|value<<29) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x60000000) >> 29 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// TIMG.WDTCONFIG1: TIMG_WDTCONFIG1_REG. +func (o *TIMG_Type) SetWDTCONFIG1_WDT_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_DIVCNT_RST() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetWDTCONFIG1_WDT_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_CLK_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0xffff0000) >> 16 +} + +// TIMG.WDTCONFIG2: TIMG_WDTCONFIG2_REG. +func (o *TIMG_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// TIMG.WDTCONFIG3: TIMG_WDTCONFIG3_REG. +func (o *TIMG_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// TIMG.WDTCONFIG4: TIMG_WDTCONFIG4_REG. +func (o *TIMG_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// TIMG.WDTCONFIG5: TIMG_WDTCONFIG5_REG. +func (o *TIMG_Type) SetWDTCONFIG5(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG5.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG5() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG5.Reg) +} + +// TIMG.WDTFEED: TIMG_WDTFEED_REG. +func (o *TIMG_Type) SetWDTFEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, value) +} +func (o *TIMG_Type) GetWDTFEED() uint32 { + return volatile.LoadUint32(&o.WDTFEED.Reg) +} + +// TIMG.WDTWPROTECT: TIMG_WDTWPROTECT_REG. +func (o *TIMG_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *TIMG_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// TIMG.RTCCALICFG: TIMG_RTCCALICFG_REG. +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START_CYCLING(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START_CYCLING() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x6000)|value<<13) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x6000) >> 13 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_RDY(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x8000)|value<<15) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_RDY() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x8000) >> 15 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_MAX(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x7fff0000)|value<<16) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_MAX() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x7fff0000) >> 16 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x80000000) >> 31 +} + +// TIMG.RTCCALICFG1: TIMG_RTCCALICFG1_REG. +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_VALUE(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_VALUE() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0xffffff80) >> 7 +} + +// TIMG.INT_ENA_TIMERS: INT_ENA_TIMG_REG +func (o *TIMG_Type) SetINT_ENA_TIMERS_T0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_RAW_TIMERS: INT_RAW_TIMG_REG +func (o *TIMG_Type) SetINT_RAW_TIMERS_T0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_ST_TIMERS: INT_ST_TIMG_REG +func (o *TIMG_Type) SetINT_ST_TIMERS_T0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_CLR_TIMERS: INT_CLR_TIMG_REG +func (o *TIMG_Type) SetINT_CLR_TIMERS_T0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.RTCCALICFG2: TIMG_RTCCALICFG2_REG. +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x78)|value<<3) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x78) >> 3 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0xffffff80) >> 7 +} + +// TIMG.NTIMG_DATE: TIMG_NTIMG_DATE_REG. +func (o *TIMG_Type) SetNTIMG_DATE_NTIMGS_DATE(value uint32) { + volatile.StoreUint32(&o.NTIMG_DATE.Reg, volatile.LoadUint32(&o.NTIMG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *TIMG_Type) GetNTIMG_DATE_NTIMGS_DATE() uint32 { + return volatile.LoadUint32(&o.NTIMG_DATE.Reg) & 0xfffffff +} + +// TIMG.REGCLK: TIMG_REGCLK_REG. +func (o *TIMG_Type) SetREGCLK_WDT_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetREGCLK_WDT_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetREGCLK_TIMER_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetREGCLK_TIMER_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetREGCLK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetREGCLK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x80000000) >> 31 +} + +// Two-Wire Automotive Interface +type TWAI_Type struct { + MODE volatile.Register32 // 0x0 + CMD volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + INT_RAW volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + _ [4]byte + BUS_TIMING_0 volatile.Register32 // 0x18 + BUS_TIMING_1 volatile.Register32 // 0x1C + _ [12]byte + ARB_LOST_CAP volatile.Register32 // 0x2C + ERR_CODE_CAP volatile.Register32 // 0x30 + ERR_WARNING_LIMIT volatile.Register32 // 0x34 + RX_ERR_CNT volatile.Register32 // 0x38 + TX_ERR_CNT volatile.Register32 // 0x3C + DATA_0 volatile.Register32 // 0x40 + DATA_1 volatile.Register32 // 0x44 + DATA_2 volatile.Register32 // 0x48 + DATA_3 volatile.Register32 // 0x4C + DATA_4 volatile.Register32 // 0x50 + DATA_5 volatile.Register32 // 0x54 + DATA_6 volatile.Register32 // 0x58 + DATA_7 volatile.Register32 // 0x5C + DATA_8 volatile.Register32 // 0x60 + DATA_9 volatile.Register32 // 0x64 + DATA_10 volatile.Register32 // 0x68 + DATA_11 volatile.Register32 // 0x6C + DATA_12 volatile.Register32 // 0x70 + RX_MESSAGE_CNT volatile.Register32 // 0x74 + _ [4]byte + CLOCK_DIVIDER volatile.Register32 // 0x7C +} + +// TWAI.MODE: Mode Register +func (o *TWAI_Type) SetMODE_RESET_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetMODE_RESET_MODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x1 +} +func (o *TWAI_Type) SetMODE_LISTEN_ONLY_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetMODE_LISTEN_ONLY_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetMODE_SELF_TEST_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetMODE_SELF_TEST_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetMODE_RX_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetMODE_RX_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x8) >> 3 +} + +// TWAI.CMD: Command Register +func (o *TWAI_Type) SetCMD_TX_REQ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetCMD_TX_REQ() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *TWAI_Type) SetCMD_ABORT_TX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetCMD_ABORT_TX() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetCMD_RELEASE_BUF(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetCMD_RELEASE_BUF() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetCMD_CLR_OVERRUN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetCMD_CLR_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetCMD_SELF_RX_REQ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetCMD_SELF_RX_REQ() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10) >> 4 +} + +// TWAI.STATUS: Status register +func (o *TWAI_Type) SetSTATUS_RX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSTATUS_RX_BUF_ST() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *TWAI_Type) SetSTATUS_OVERRUN_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSTATUS_OVERRUN_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetSTATUS_TX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetSTATUS_TX_BUF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetSTATUS_TX_COMPLETE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetSTATUS_TX_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetSTATUS_RX_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetSTATUS_RX_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *TWAI_Type) SetSTATUS_TX_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetSTATUS_TX_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetSTATUS_ERR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetSTATUS_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetSTATUS_BUS_OFF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetSTATUS_BUS_OFF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetSTATUS_MISS_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetSTATUS_MISS_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} + +// TWAI.INT_RAW: Interrupt Register +func (o *TWAI_Type) SetINT_RAW_RX_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINT_RAW_RX_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *TWAI_Type) SetINT_RAW_TX_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINT_RAW_TX_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINT_RAW_ERR_WARN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINT_RAW_ERR_WARN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINT_RAW_OVERRUN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINT_RAW_OVERRUN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINT_RAW_ERR_PASSIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINT_RAW_ERR_PASSIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINT_RAW_ARB_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINT_RAW_ARB_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINT_RAW_BUS_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINT_RAW_BUS_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} + +// TWAI.INT_ENA: Interrupt Enable Register +func (o *TWAI_Type) SetINT_ENA_RX_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINT_ENA_RX_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *TWAI_Type) SetINT_ENA_TX_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINT_ENA_TX_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINT_ENA_ERR_WARN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINT_ENA_ERR_WARN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINT_ENA_OVERRUN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINT_ENA_OVERRUN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINT_ENA_ERR_PASSIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINT_ENA_ERR_PASSIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINT_ENA_ARB_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINT_ENA_ARB_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINT_ENA_BUS_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINT_ENA_BUS_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} + +// TWAI.BUS_TIMING_0: Bus Timing Register 0 +func (o *TWAI_Type) SetBUS_TIMING_0_BAUD_PRESC(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0x3fff)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_0_BAUD_PRESC() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0x3fff +} +func (o *TWAI_Type) SetBUS_TIMING_0_SYNC_JUMP_WIDTH(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0xc000)|value<<14) +} +func (o *TWAI_Type) GetBUS_TIMING_0_SYNC_JUMP_WIDTH() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0xc000) >> 14 +} + +// TWAI.BUS_TIMING_1: Bus Timing Register 1 +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG1(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0xf)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG1() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0xf +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG2(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x70)|value<<4) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG2() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x70) >> 4 +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SAMP(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SAMP() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x80) >> 7 +} + +// TWAI.ARB_LOST_CAP: Arbitration Lost Capture Register +func (o *TWAI_Type) SetARB_LOST_CAP(value uint32) { + volatile.StoreUint32(&o.ARB_LOST_CAP.Reg, volatile.LoadUint32(&o.ARB_LOST_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetARB_LOST_CAP() uint32 { + return volatile.LoadUint32(&o.ARB_LOST_CAP.Reg) & 0x1f +} + +// TWAI.ERR_CODE_CAP: Error Code Capture Register +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_SEGMENT(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_SEGMENT() uint32 { + return volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x1f +} +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_DIRECTION(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_TYPE(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0xc0)|value<<6) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_TYPE() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0xc0) >> 6 +} + +// TWAI.ERR_WARNING_LIMIT: Error Warning Limit Register +func (o *TWAI_Type) SetERR_WARNING_LIMIT(value uint32) { + volatile.StoreUint32(&o.ERR_WARNING_LIMIT.Reg, volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetERR_WARNING_LIMIT() uint32 { + return volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg) & 0xff +} + +// TWAI.RX_ERR_CNT: Receive Error Counter Register +func (o *TWAI_Type) SetRX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ERR_CNT.Reg, volatile.LoadUint32(&o.RX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetRX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.RX_ERR_CNT.Reg) & 0xff +} + +// TWAI.TX_ERR_CNT: Transmit Error Counter Register +func (o *TWAI_Type) SetTX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ERR_CNT.Reg, volatile.LoadUint32(&o.TX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetTX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.TX_ERR_CNT.Reg) & 0xff +} + +// TWAI.DATA_0: Data register 0 +func (o *TWAI_Type) SetDATA_0_TX_BYTE_0(value uint32) { + volatile.StoreUint32(&o.DATA_0.Reg, volatile.LoadUint32(&o.DATA_0.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_0_TX_BYTE_0() uint32 { + return volatile.LoadUint32(&o.DATA_0.Reg) & 0xff +} + +// TWAI.DATA_1: Data register 1 +func (o *TWAI_Type) SetDATA_1_TX_BYTE_1(value uint32) { + volatile.StoreUint32(&o.DATA_1.Reg, volatile.LoadUint32(&o.DATA_1.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_1_TX_BYTE_1() uint32 { + return volatile.LoadUint32(&o.DATA_1.Reg) & 0xff +} + +// TWAI.DATA_2: Data register 2 +func (o *TWAI_Type) SetDATA_2_TX_BYTE_2(value uint32) { + volatile.StoreUint32(&o.DATA_2.Reg, volatile.LoadUint32(&o.DATA_2.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_2_TX_BYTE_2() uint32 { + return volatile.LoadUint32(&o.DATA_2.Reg) & 0xff +} + +// TWAI.DATA_3: Data register 3 +func (o *TWAI_Type) SetDATA_3_TX_BYTE_3(value uint32) { + volatile.StoreUint32(&o.DATA_3.Reg, volatile.LoadUint32(&o.DATA_3.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_3_TX_BYTE_3() uint32 { + return volatile.LoadUint32(&o.DATA_3.Reg) & 0xff +} + +// TWAI.DATA_4: Data register 4 +func (o *TWAI_Type) SetDATA_4_TX_BYTE_4(value uint32) { + volatile.StoreUint32(&o.DATA_4.Reg, volatile.LoadUint32(&o.DATA_4.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_4_TX_BYTE_4() uint32 { + return volatile.LoadUint32(&o.DATA_4.Reg) & 0xff +} + +// TWAI.DATA_5: Data register 5 +func (o *TWAI_Type) SetDATA_5_TX_BYTE_5(value uint32) { + volatile.StoreUint32(&o.DATA_5.Reg, volatile.LoadUint32(&o.DATA_5.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_5_TX_BYTE_5() uint32 { + return volatile.LoadUint32(&o.DATA_5.Reg) & 0xff +} + +// TWAI.DATA_6: Data register 6 +func (o *TWAI_Type) SetDATA_6_TX_BYTE_6(value uint32) { + volatile.StoreUint32(&o.DATA_6.Reg, volatile.LoadUint32(&o.DATA_6.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_6_TX_BYTE_6() uint32 { + return volatile.LoadUint32(&o.DATA_6.Reg) & 0xff +} + +// TWAI.DATA_7: Data register 7 +func (o *TWAI_Type) SetDATA_7_TX_BYTE_7(value uint32) { + volatile.StoreUint32(&o.DATA_7.Reg, volatile.LoadUint32(&o.DATA_7.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_7_TX_BYTE_7() uint32 { + return volatile.LoadUint32(&o.DATA_7.Reg) & 0xff +} + +// TWAI.DATA_8: Data register 8 +func (o *TWAI_Type) SetDATA_8_TX_BYTE_8(value uint32) { + volatile.StoreUint32(&o.DATA_8.Reg, volatile.LoadUint32(&o.DATA_8.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_8_TX_BYTE_8() uint32 { + return volatile.LoadUint32(&o.DATA_8.Reg) & 0xff +} + +// TWAI.DATA_9: Data register 9 +func (o *TWAI_Type) SetDATA_9_TX_BYTE_9(value uint32) { + volatile.StoreUint32(&o.DATA_9.Reg, volatile.LoadUint32(&o.DATA_9.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_9_TX_BYTE_9() uint32 { + return volatile.LoadUint32(&o.DATA_9.Reg) & 0xff +} + +// TWAI.DATA_10: Data register 10 +func (o *TWAI_Type) SetDATA_10_TX_BYTE_10(value uint32) { + volatile.StoreUint32(&o.DATA_10.Reg, volatile.LoadUint32(&o.DATA_10.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_10_TX_BYTE_10() uint32 { + return volatile.LoadUint32(&o.DATA_10.Reg) & 0xff +} + +// TWAI.DATA_11: Data register 11 +func (o *TWAI_Type) SetDATA_11_TX_BYTE_11(value uint32) { + volatile.StoreUint32(&o.DATA_11.Reg, volatile.LoadUint32(&o.DATA_11.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_11_TX_BYTE_11() uint32 { + return volatile.LoadUint32(&o.DATA_11.Reg) & 0xff +} + +// TWAI.DATA_12: Data register 12 +func (o *TWAI_Type) SetDATA_12_TX_BYTE_12(value uint32) { + volatile.StoreUint32(&o.DATA_12.Reg, volatile.LoadUint32(&o.DATA_12.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_12_TX_BYTE_12() uint32 { + return volatile.LoadUint32(&o.DATA_12.Reg) & 0xff +} + +// TWAI.RX_MESSAGE_CNT: Receive Message Counter Register +func (o *TWAI_Type) SetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER(value uint32) { + volatile.StoreUint32(&o.RX_MESSAGE_CNT.Reg, volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg)&^(0x7f)|value) +} +func (o *TWAI_Type) GetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER() uint32 { + return volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg) & 0x7f +} + +// TWAI.CLOCK_DIVIDER: Clock Divider register +func (o *TWAI_Type) SetCLOCK_DIVIDER_CD(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CD() uint32 { + return volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0xff +} +func (o *TWAI_Type) SetCLOCK_DIVIDER_CLOCK_OFF(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CLOCK_OFF() uint32 { + return (volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0x100) >> 8 +} + +// UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +type UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV volatile.Register32 // 0x14 + RX_FILT volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0 volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + LOWPULSE volatile.Register32 // 0x28 + HIGHPULSE volatile.Register32 // 0x2C + RXD_CNT volatile.Register32 // 0x30 + FLOW_CONF volatile.Register32 // 0x34 + SLEEP_CONF volatile.Register32 // 0x38 + SWFC_CONF0 volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + TXBRK_CONF volatile.Register32 // 0x44 + IDLE_CONF volatile.Register32 // 0x48 + RS485_CONF volatile.Register32 // 0x4C + AT_CMD_PRECNT volatile.Register32 // 0x50 + AT_CMD_POSTCNT volatile.Register32 // 0x54 + AT_CMD_GAPTOUT volatile.Register32 // 0x58 + AT_CMD_CHAR volatile.Register32 // 0x5C + MEM_CONF volatile.Register32 // 0x60 + MEM_TX_STATUS volatile.Register32 // 0x64 + MEM_RX_STATUS volatile.Register32 // 0x68 + FSM_STATUS volatile.Register32 // 0x6C + POSPULSE volatile.Register32 // 0x70 + NEGPULSE volatile.Register32 // 0x74 + CLK_CONF volatile.Register32 // 0x78 + DATE volatile.Register32 // 0x7C + ID volatile.Register32 // 0x80 +} + +// UART.FIFO: FIFO data register +func (o *UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// UART.INT_RAW: Raw interrupt status +func (o *UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_RAW_RS485_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_RAW_RS485_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_RAW_RS485_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_RAW_RS485_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_RAW_RS485_CLASH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_RAW_RS485_CLASH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// UART.INT_ST: Masked interrupt status +func (o *UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ST_RS485_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ST_RS485_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ST_RS485_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ST_RS485_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ST_RS485_CLASH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ST_RS485_CLASH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// UART.INT_ENA: Interrupt enable bits +func (o *UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ENA_RS485_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ENA_RS485_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ENA_RS485_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ENA_RS485_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ENA_RS485_CLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ENA_RS485_CLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// UART.INT_CLR: Interrupt clear bits +func (o *UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_CLR_RS485_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_CLR_RS485_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_CLR_RS485_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_CLR_RS485_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_CLR_RS485_CLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_CLR_RS485_CLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// UART.CLKDIV: Clock divider configuration +func (o *UART_Type) SetCLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetCLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xfff +} +func (o *UART_Type) SetCLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xf00000)|value<<20) +} +func (o *UART_Type) GetCLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xf00000) >> 20 +} + +// UART.RX_FILT: Rx Filter configuration +func (o *UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT() uint32 { + return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff +} +func (o *UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8 +} + +// UART.STATUS: UART status register +func (o *UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ff0000)|value<<16) +} +func (o *UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3ff0000) >> 16 +} +func (o *UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// UART.CONF0: a +func (o *UART_Type) SetCONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetCONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UART_Type) SetCONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetCONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetCONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0xc)|value<<2) +} +func (o *UART_Type) GetCONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0xc) >> 2 +} +func (o *UART_Type) SetCONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x30)|value<<4) +} +func (o *UART_Type) GetCONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x30) >> 4 +} +func (o *UART_Type) SetCONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetCONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetCONF0_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetCONF0_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetCONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetCONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetCONF0_IRDA_DPLX(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetCONF0_IRDA_DPLX() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetCONF0_IRDA_TX_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetCONF0_IRDA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetCONF0_IRDA_WCTL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetCONF0_IRDA_WCTL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetCONF0_IRDA_TX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetCONF0_IRDA_TX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetCONF0_IRDA_RX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetCONF0_IRDA_RX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetCONF0_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetCONF0_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetCONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetCONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetCONF0_IRDA_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF0_IRDA_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF0_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF0_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF0_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF0_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF0_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF0_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetCONF0_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCONF0_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCONF0_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF0_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCONF0_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCONF0_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCONF0_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCONF0_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCONF0_AUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCONF0_AUTOBAUD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000000) >> 27 +} +func (o *UART_Type) SetCONF0_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *UART_Type) GetCONF0_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000000) >> 28 +} + +// UART.CONF1: Configuration register 1 +func (o *UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1ff)|value) +} +func (o *UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1ff +} +func (o *UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x3fe00)|value<<9) +} +func (o *UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x3fe00) >> 9 +} +func (o *UART_Type) SetCONF1_DIS_RX_DAT_OVF(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF1_DIS_RX_DAT_OVF() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF1_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF1_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF1_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF1_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF1_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF1_RX_TOUT_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} + +// UART.LOWPULSE: Autobaud minimum low pulse duration register +func (o *UART_Type) SetLOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.LOWPULSE.Reg, volatile.LoadUint32(&o.LOWPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetLOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.LOWPULSE.Reg) & 0xfff +} + +// UART.HIGHPULSE: Autobaud minimum high pulse duration register +func (o *UART_Type) SetHIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.HIGHPULSE.Reg, volatile.LoadUint32(&o.HIGHPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetHIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.HIGHPULSE.Reg) & 0xfff +} + +// UART.RXD_CNT: Autobaud edge change count register +func (o *UART_Type) SetRXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.RXD_CNT.Reg, volatile.LoadUint32(&o.RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetRXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.RXD_CNT.Reg) & 0x3ff +} + +// UART.FLOW_CONF: Software flow-control configuration +func (o *UART_Type) SetFLOW_CONF_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetFLOW_CONF_SW_FLOW_CON_EN() uint32 { + return volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetFLOW_CONF_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetFLOW_CONF_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x20) >> 5 +} + +// UART.SLEEP_CONF: Sleep-mode configuration +func (o *UART_Type) SetSLEEP_CONF_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF.Reg, volatile.LoadUint32(&o.SLEEP_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSLEEP_CONF_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF.Reg) & 0x3ff +} + +// UART.SWFC_CONF0: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF0_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x1ff)|value) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x1ff +} +func (o *UART_Type) SetSWFC_CONF0_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x1fe00) >> 9 +} + +// UART.SWFC_CONF1: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0x1ff)|value) +} +func (o *UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0x1ff +} +func (o *UART_Type) SetSWFC_CONF1_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetSWFC_CONF1_XON_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0x1fe00) >> 9 +} + +// UART.TXBRK_CONF: Tx Break character configuration +func (o *UART_Type) SetTXBRK_CONF_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.TXBRK_CONF.Reg, volatile.LoadUint32(&o.TXBRK_CONF.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetTXBRK_CONF_TX_BRK_NUM() uint32 { + return volatile.LoadUint32(&o.TXBRK_CONF.Reg) & 0xff +} + +// UART.IDLE_CONF: Frame-end idle configuration +func (o *UART_Type) SetIDLE_CONF_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetIDLE_CONF_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0x3ff +} +func (o *UART_Type) SetIDLE_CONF_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *UART_Type) GetIDLE_CONF_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xffc00) >> 10 +} + +// UART.RS485_CONF: RS485 mode configuration +func (o *UART_Type) SetRS485_CONF_RS485_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetRS485_CONF_RS485_EN() uint32 { + return volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetRS485_CONF_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetRS485_CONF_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetRS485_CONF_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetRS485_CONF_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetRS485_CONF_RS485TX_RX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetRS485_CONF_RS485TX_RX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetRS485_CONF_RS485RXBY_TX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetRS485_CONF_RS485RXBY_TX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetRS485_CONF_RS485_RX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetRS485_CONF_RS485_RX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetRS485_CONF_RS485_TX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x3c0)|value<<6) +} +func (o *UART_Type) GetRS485_CONF_RS485_TX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x3c0) >> 6 +} + +// UART.AT_CMD_PRECNT: Pre-sequence timing configuration +func (o *UART_Type) SetAT_CMD_PRECNT_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_PRECNT_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg) & 0xffff +} + +// UART.AT_CMD_POSTCNT: Post-sequence timing configuration +func (o *UART_Type) SetAT_CMD_POSTCNT_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_POSTCNT_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg) & 0xffff +} + +// UART.AT_CMD_GAPTOUT: Timeout configuration +func (o *UART_Type) SetAT_CMD_GAPTOUT_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_GAPTOUT_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg) & 0xffff +} + +// UART.AT_CMD_CHAR: AT escape sequence detection configuration +func (o *UART_Type) SetAT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetAT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff +} +func (o *UART_Type) SetAT_CMD_CHAR_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAT_CMD_CHAR_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff00) >> 8 +} + +// UART.MEM_CONF: UART threshold and allocation configuration +func (o *UART_Type) SetMEM_CONF_RX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xe)|value<<1) +} +func (o *UART_Type) GetMEM_CONF_RX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xe) >> 1 +} +func (o *UART_Type) SetMEM_CONF_TX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x70)|value<<4) +} +func (o *UART_Type) GetMEM_CONF_TX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x70) >> 4 +} +func (o *UART_Type) SetMEM_CONF_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xff80)|value<<7) +} +func (o *UART_Type) GetMEM_CONF_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xff80) >> 7 +} +func (o *UART_Type) SetMEM_CONF_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x3ff0000)|value<<16) +} +func (o *UART_Type) GetMEM_CONF_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x3ff0000) >> 16 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x8000000) >> 27 +} + +// UART.MEM_TX_STATUS: Tx-FIFO write and read offset address. +func (o *UART_Type) SetMEM_TX_STATUS_APB_TX_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetMEM_TX_STATUS_APB_TX_WADDR() uint32 { + return volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetMEM_TX_STATUS_TX_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1ff800) >> 11 +} + +// UART.MEM_RX_STATUS: Rx-FIFO write and read offset address. +func (o *UART_Type) SetMEM_RX_STATUS_APB_RX_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetMEM_RX_STATUS_APB_RX_RADDR() uint32 { + return volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetMEM_RX_STATUS_RX_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1ff800) >> 11 +} + +// UART.FSM_STATUS: UART transmit and receive status. +func (o *UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// UART.POSPULSE: Autobaud high pulse register +func (o *UART_Type) SetPOSPULSE_POSEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.POSPULSE.Reg, volatile.LoadUint32(&o.POSPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetPOSPULSE_POSEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.POSPULSE.Reg) & 0xfff +} + +// UART.NEGPULSE: Autobaud low pulse register +func (o *UART_Type) SetNEGPULSE_NEGEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.NEGPULSE.Reg, volatile.LoadUint32(&o.NEGPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetNEGPULSE_NEGEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.NEGPULSE.Reg) & 0xfff +} + +// UART.CLK_CONF: UART core clock configuration +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f)|value) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f +} +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *UART_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *UART_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *UART_Type) SetCLK_CONF_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCLK_CONF_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCLK_CONF_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCLK_CONF_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} + +// UART.DATE: UART Version register +func (o *UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// UART.ID: UART ID register +func (o *UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0x3fffffff)|value) +} +func (o *UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) & 0x3fffffff +} +func (o *UART_Type) SetID_HIGH_SPEED(value uint32) { + volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetID_HIGH_SPEED() uint32 { + return (volatile.LoadUint32(&o.ID.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetID_REG_UPDATE(value uint32) { + volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetID_REG_UPDATE() uint32 { + return (volatile.LoadUint32(&o.ID.Reg) & 0x80000000) >> 31 +} + +// Universal Host Controller Interface 0 +type UHCI_Type struct { + CONF0 volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CONF1 volatile.Register32 // 0x14 + STATE0 volatile.Register32 // 0x18 + STATE1 volatile.Register32 // 0x1C + ESCAPE_CONF volatile.Register32 // 0x20 + HUNG_CONF volatile.Register32 // 0x24 + ACK_NUM volatile.Register32 // 0x28 + RX_HEAD volatile.Register32 // 0x2C + QUICK_SENT volatile.Register32 // 0x30 + REG_Q0_WORD0 volatile.Register32 // 0x34 + REG_Q0_WORD1 volatile.Register32 // 0x38 + REG_Q1_WORD0 volatile.Register32 // 0x3C + REG_Q1_WORD1 volatile.Register32 // 0x40 + REG_Q2_WORD0 volatile.Register32 // 0x44 + REG_Q2_WORD1 volatile.Register32 // 0x48 + REG_Q3_WORD0 volatile.Register32 // 0x4C + REG_Q3_WORD1 volatile.Register32 // 0x50 + REG_Q4_WORD0 volatile.Register32 // 0x54 + REG_Q4_WORD1 volatile.Register32 // 0x58 + REG_Q5_WORD0 volatile.Register32 // 0x5C + REG_Q5_WORD1 volatile.Register32 // 0x60 + REG_Q6_WORD0 volatile.Register32 // 0x64 + REG_Q6_WORD1 volatile.Register32 // 0x68 + ESC_CONF0 volatile.Register32 // 0x6C + ESC_CONF1 volatile.Register32 // 0x70 + ESC_CONF2 volatile.Register32 // 0x74 + ESC_CONF3 volatile.Register32 // 0x78 + PKT_THRES volatile.Register32 // 0x7C + DATE volatile.Register32 // 0x80 +} + +// UHCI.CONF0: a +func (o *UHCI_Type) SetCONF0_TX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF0_TX_RST() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF0_RX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF0_RX_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF0_UART0_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF0_UART0_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF0_UART1_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF0_UART1_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF0_SEPER_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF0_SEPER_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF0_HEAD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetCONF0_HEAD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetCONF0_CRC_REC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF0_CRC_REC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF0_UART_IDLE_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF0_UART_IDLE_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetCONF0_LEN_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetCONF0_LEN_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetCONF0_ENCODE_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetCONF0_ENCODE_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetCONF0_UART_RX_BRK_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetCONF0_UART_RX_BRK_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} + +// UHCI.INT_RAW: a +func (o *UHCI_Type) SetINT_RAW_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_RAW_RX_START_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_RAW_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_RAW_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_RAW_SEND_S_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_RAW_SEND_S_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_RAW_SEND_A_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_RAW_SEND_A_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ST: a +func (o *UHCI_Type) SetINT_ST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ST_RX_START_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ST_SEND_S_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ST_SEND_S_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ST_SEND_A_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ST_SEND_A_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ST_OUTLINK_EOF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ST_OUTLINK_EOF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ENA: a +func (o *UHCI_Type) SetINT_ENA_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ENA_RX_START_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ENA_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ENA_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ENA_SEND_S_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ENA_SEND_S_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ENA_SEND_A_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ENA_SEND_A_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ENA_OUTLINK_EOF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ENA_OUTLINK_EOF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// UHCI.INT_CLR: a +func (o *UHCI_Type) SetINT_CLR_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_CLR_RX_START_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_CLR_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_CLR_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_CLR_SEND_S_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_CLR_SEND_S_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_CLR_SEND_A_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_CLR_SEND_A_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_CLR_OUTLINK_EOF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_CLR_OUTLINK_EOF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// UHCI.CONF1: a +func (o *UHCI_Type) SetCONF1_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF1_CHECK_SUM_EN() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF1_CHECK_SEQ_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF1_CHECK_SEQ_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF1_CRC_DISABLE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF1_CRC_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF1_SAVE_HEAD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF1_SAVE_HEAD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF1_TX_CHECK_SUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF1_TX_CHECK_SUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF1_TX_ACK_NUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF1_TX_ACK_NUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF1_WAIT_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF1_WAIT_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF1_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF1_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8 +} + +// UHCI.STATE0: a +func (o *UHCI_Type) SetSTATE0_RX_ERR_CAUSE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE0_RX_ERR_CAUSE() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x7 +} +func (o *UHCI_Type) SetSTATE0_DECODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x38)|value<<3) +} +func (o *UHCI_Type) GetSTATE0_DECODE_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x38) >> 3 +} + +// UHCI.STATE1: a +func (o *UHCI_Type) SetSTATE1_ENCODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE1_ENCODE_STATE() uint32 { + return volatile.LoadUint32(&o.STATE1.Reg) & 0x7 +} + +// UHCI.ESCAPE_CONF: a +func (o *UHCI_Type) SetESCAPE_CONF_TX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_C0_ESC_EN() uint32 { + return volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_C0_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x80) >> 7 +} + +// UHCI.HUNG_CONF: a +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff000) >> 12 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700000) >> 20 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800000) >> 23 +} + +// UHCI.ACK_NUM: a +func (o *UHCI_Type) SetACK_NUM(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetACK_NUM() uint32 { + return volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x7 +} +func (o *UHCI_Type) SetACK_NUM_LOAD(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetACK_NUM_LOAD() uint32 { + return (volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x8) >> 3 +} + +// UHCI.RX_HEAD: a +func (o *UHCI_Type) SetRX_HEAD(value uint32) { + volatile.StoreUint32(&o.RX_HEAD.Reg, value) +} +func (o *UHCI_Type) GetRX_HEAD() uint32 { + return volatile.LoadUint32(&o.RX_HEAD.Reg) +} + +// UHCI.QUICK_SENT: a +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_NUM() uint32 { + return volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x7 +} +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x70)|value<<4) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_NUM() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x70) >> 4 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x80) >> 7 +} + +// UHCI.REG_Q0_WORD0: a +func (o *UHCI_Type) SetREG_Q0_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD0.Reg) +} + +// UHCI.REG_Q0_WORD1: a +func (o *UHCI_Type) SetREG_Q0_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD1.Reg) +} + +// UHCI.REG_Q1_WORD0: a +func (o *UHCI_Type) SetREG_Q1_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD0.Reg) +} + +// UHCI.REG_Q1_WORD1: a +func (o *UHCI_Type) SetREG_Q1_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD1.Reg) +} + +// UHCI.REG_Q2_WORD0: a +func (o *UHCI_Type) SetREG_Q2_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD0.Reg) +} + +// UHCI.REG_Q2_WORD1: a +func (o *UHCI_Type) SetREG_Q2_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD1.Reg) +} + +// UHCI.REG_Q3_WORD0: a +func (o *UHCI_Type) SetREG_Q3_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD0.Reg) +} + +// UHCI.REG_Q3_WORD1: a +func (o *UHCI_Type) SetREG_Q3_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD1.Reg) +} + +// UHCI.REG_Q4_WORD0: a +func (o *UHCI_Type) SetREG_Q4_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD0.Reg) +} + +// UHCI.REG_Q4_WORD1: a +func (o *UHCI_Type) SetREG_Q4_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD1.Reg) +} + +// UHCI.REG_Q5_WORD0: a +func (o *UHCI_Type) SetREG_Q5_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD0.Reg) +} + +// UHCI.REG_Q5_WORD1: a +func (o *UHCI_Type) SetREG_Q5_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD1.Reg) +} + +// UHCI.REG_Q6_WORD0: a +func (o *UHCI_Type) SetREG_Q6_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD0.Reg) +} + +// UHCI.REG_Q6_WORD1: a +func (o *UHCI_Type) SetREG_Q6_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD1.Reg) +} + +// UHCI.ESC_CONF0: a +func (o *UHCI_Type) SetESC_CONF0_SEPER_CHAR(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_CHAR() uint32 { + return volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF1: a +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0() uint32 { + return volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF2: a +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1() uint32 { + return volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF3: a +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2() uint32 { + return volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff0000) >> 16 +} + +// UHCI.PKT_THRES: a +func (o *UHCI_Type) SetPKT_THRES_PKT_THRS(value uint32) { + volatile.StoreUint32(&o.PKT_THRES.Reg, volatile.LoadUint32(&o.PKT_THRES.Reg)&^(0x1fff)|value) +} +func (o *UHCI_Type) GetPKT_THRES_PKT_THRS() uint32 { + return volatile.LoadUint32(&o.PKT_THRES.Reg) & 0x1fff +} + +// UHCI.DATE: a +func (o *UHCI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UHCI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Full-speed USB Serial/JTAG Controller +type USB_DEVICE_Type struct { + EP1 volatile.Register32 // 0x0 + EP1_CONF volatile.Register32 // 0x4 + INT_RAW volatile.Register32 // 0x8 + INT_ST volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + INT_CLR volatile.Register32 // 0x14 + CONF0 volatile.Register32 // 0x18 + TEST volatile.Register32 // 0x1C + JFIFO_ST volatile.Register32 // 0x20 + FRAM_NUM volatile.Register32 // 0x24 + IN_EP0_ST volatile.Register32 // 0x28 + IN_EP1_ST volatile.Register32 // 0x2C + IN_EP2_ST volatile.Register32 // 0x30 + IN_EP3_ST volatile.Register32 // 0x34 + OUT_EP0_ST volatile.Register32 // 0x38 + OUT_EP1_ST volatile.Register32 // 0x3C + OUT_EP2_ST volatile.Register32 // 0x40 + MISC_CONF volatile.Register32 // 0x44 + MEM_CONF volatile.Register32 // 0x48 + _ [52]byte + DATE volatile.Register32 // 0x80 +} + +// USB_DEVICE.EP1: USB_DEVICE_EP1_REG. +func (o *USB_DEVICE_Type) SetEP1_RDWR_BYTE(value uint32) { + volatile.StoreUint32(&o.EP1.Reg, volatile.LoadUint32(&o.EP1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetEP1_RDWR_BYTE() uint32 { + return volatile.LoadUint32(&o.EP1.Reg) & 0xff +} + +// USB_DEVICE.EP1_CONF: USB_DEVICE_EP1_CONF_REG. +func (o *USB_DEVICE_Type) SetEP1_CONF_WR_DONE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_WR_DONE() uint32 { + return volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_SERIAL_IN_EP_DATA_FREE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_SERIAL_IN_EP_DATA_FREE() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_SERIAL_OUT_EP_DATA_AVAIL(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_SERIAL_OUT_EP_DATA_AVAIL() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x4) >> 2 +} + +// USB_DEVICE.INT_RAW: USB_DEVICE_INT_RAW_REG. +func (o *USB_DEVICE_Type) SetINT_RAW_JTAG_IN_FLUSH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_RAW_JTAG_IN_FLUSH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SERIAL_IN_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SERIAL_IN_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_RAW_PID_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_RAW_PID_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_RAW_CRC5_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_RAW_CRC5_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_RAW_CRC16_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_RAW_CRC16_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_RAW_STUFF_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_RAW_STUFF_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_BUS_RESET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_BUS_RESET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} + +// USB_DEVICE.INT_ST: USB_DEVICE_INT_ST_REG. +func (o *USB_DEVICE_Type) SetINT_ST_JTAG_IN_FLUSH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ST_JTAG_IN_FLUSH_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ST_SOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ST_SOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ST_SERIAL_OUT_RECV_PKT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ST_SERIAL_OUT_RECV_PKT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ST_SERIAL_IN_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ST_SERIAL_IN_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ST_PID_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ST_PID_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ST_CRC5_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ST_CRC5_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ST_CRC16_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ST_CRC16_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ST_STUFF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ST_STUFF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ST_IN_TOKEN_REC_IN_EP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ST_IN_TOKEN_REC_IN_EP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_BUS_RESET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_BUS_RESET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} + +// USB_DEVICE.INT_ENA: USB_DEVICE_INT_ENA_REG. +func (o *USB_DEVICE_Type) SetINT_ENA_JTAG_IN_FLUSH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ENA_JTAG_IN_FLUSH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SERIAL_IN_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SERIAL_IN_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ENA_PID_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ENA_PID_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ENA_CRC5_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ENA_CRC5_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ENA_CRC16_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ENA_CRC16_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ENA_STUFF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ENA_STUFF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_BUS_RESET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_BUS_RESET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} + +// USB_DEVICE.INT_CLR: USB_DEVICE_INT_CLR_REG. +func (o *USB_DEVICE_Type) SetINT_CLR_JTAG_IN_FLUSH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_CLR_JTAG_IN_FLUSH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SERIAL_IN_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SERIAL_IN_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_CLR_PID_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_CLR_PID_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_CLR_CRC5_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_CLR_CRC5_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_CLR_CRC16_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_CLR_CRC16_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_CLR_STUFF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_CLR_STUFF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_BUS_RESET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_BUS_RESET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} + +// USB_DEVICE.CONF0: USB_DEVICE_CONF0_REG. +func (o *USB_DEVICE_Type) SetCONF0_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCONF0_PHY_SEL() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetCONF0_EXCHG_PINS_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetCONF0_EXCHG_PINS_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetCONF0_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetCONF0_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetCONF0_VREFH(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x18)|value<<3) +} +func (o *USB_DEVICE_Type) GetCONF0_VREFH() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x18) >> 3 +} +func (o *USB_DEVICE_Type) SetCONF0_VREFL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x60)|value<<5) +} +func (o *USB_DEVICE_Type) GetCONF0_VREFL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x60) >> 5 +} +func (o *USB_DEVICE_Type) SetCONF0_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetCONF0_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetCONF0_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetCONF0_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetCONF0_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetCONF0_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetCONF0_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetCONF0_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetCONF0_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetCONF0_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetCONF0_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetCONF0_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetCONF0_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetCONF0_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} + +// USB_DEVICE.TEST: USB_DEVICE_TEST_REG. +func (o *USB_DEVICE_Type) SetTEST_ENABLE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetTEST_ENABLE() uint32 { + return volatile.LoadUint32(&o.TEST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetTEST_USB_OE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetTEST_USB_OE() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetTEST_TX_DP(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetTEST_TX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetTEST_TX_DM(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetTEST_TX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x8) >> 3 +} + +// USB_DEVICE.JFIFO_ST: USB_DEVICE_JFIFO_ST_REG. +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_CNT() uint32 { + return volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x30)|value<<4) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x30) >> 4 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x200) >> 9 +} + +// USB_DEVICE.FRAM_NUM: USB_DEVICE_FRAM_NUM_REG. +func (o *USB_DEVICE_Type) SetFRAM_NUM_SOF_FRAME_INDEX(value uint32) { + volatile.StoreUint32(&o.FRAM_NUM.Reg, volatile.LoadUint32(&o.FRAM_NUM.Reg)&^(0x7ff)|value) +} +func (o *USB_DEVICE_Type) GetFRAM_NUM_SOF_FRAME_INDEX() uint32 { + return volatile.LoadUint32(&o.FRAM_NUM.Reg) & 0x7ff +} + +// USB_DEVICE.IN_EP0_ST: USB_DEVICE_IN_EP0_ST_REG. +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP1_ST: USB_DEVICE_IN_EP1_ST_REG. +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP2_ST: USB_DEVICE_IN_EP2_ST_REG. +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP3_ST: USB_DEVICE_IN_EP3_ST_REG. +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP0_ST: USB_DEVICE_OUT_EP0_ST_REG. +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP1_ST: USB_DEVICE_OUT_EP1_ST_REG. +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0xfe00) >> 9 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_REC_DATA_CNT(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x7f0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_REC_DATA_CNT() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x7f0000) >> 16 +} + +// USB_DEVICE.OUT_EP2_ST: USB_DEVICE_OUT_EP2_ST_REG. +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.MISC_CONF: USB_DEVICE_MISC_CONF_REG. +func (o *USB_DEVICE_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMISC_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} + +// USB_DEVICE.MEM_CONF: USB_DEVICE_MEM_CONF_REG. +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_MEM_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_MEM_PD() uint32 { + return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2) >> 1 +} + +// USB_DEVICE.DATE: USB_DEVICE_DATE_REG. +func (o *USB_DEVICE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *USB_DEVICE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// XTS-AES-128 Flash Encryption +type XTS_AES_Type struct { + PLAIN_MEM [16]volatile.Register8 // 0x0 + _ [48]byte + LINESIZE volatile.Register32 // 0x40 + DESTINATION volatile.Register32 // 0x44 + PHYSICAL_ADDRESS volatile.Register32 // 0x48 + TRIGGER volatile.Register32 // 0x4C + RELEASE volatile.Register32 // 0x50 + DESTROY volatile.Register32 // 0x54 + STATE volatile.Register32 // 0x58 + DATE volatile.Register32 // 0x5C +} + +// XTS_AES.LINESIZE: XTS-AES line-size register +func (o *XTS_AES_Type) SetLINESIZE(value uint32) { + volatile.StoreUint32(&o.LINESIZE.Reg, volatile.LoadUint32(&o.LINESIZE.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetLINESIZE() uint32 { + return volatile.LoadUint32(&o.LINESIZE.Reg) & 0x1 +} + +// XTS_AES.DESTINATION: XTS-AES destination register +func (o *XTS_AES_Type) SetDESTINATION(value uint32) { + volatile.StoreUint32(&o.DESTINATION.Reg, volatile.LoadUint32(&o.DESTINATION.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetDESTINATION() uint32 { + return volatile.LoadUint32(&o.DESTINATION.Reg) & 0x1 +} + +// XTS_AES.PHYSICAL_ADDRESS: XTS-AES physical address register +func (o *XTS_AES_Type) SetPHYSICAL_ADDRESS(value uint32) { + volatile.StoreUint32(&o.PHYSICAL_ADDRESS.Reg, volatile.LoadUint32(&o.PHYSICAL_ADDRESS.Reg)&^(0x3fffffff)|value) +} +func (o *XTS_AES_Type) GetPHYSICAL_ADDRESS() uint32 { + return volatile.LoadUint32(&o.PHYSICAL_ADDRESS.Reg) & 0x3fffffff +} + +// XTS_AES.TRIGGER: XTS-AES trigger register +func (o *XTS_AES_Type) SetTRIGGER(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetTRIGGER() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} + +// XTS_AES.RELEASE: XTS-AES release register +func (o *XTS_AES_Type) SetRELEASE(value uint32) { + volatile.StoreUint32(&o.RELEASE.Reg, volatile.LoadUint32(&o.RELEASE.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetRELEASE() uint32 { + return volatile.LoadUint32(&o.RELEASE.Reg) & 0x1 +} + +// XTS_AES.DESTROY: XTS-AES destroy register +func (o *XTS_AES_Type) SetDESTROY(value uint32) { + volatile.StoreUint32(&o.DESTROY.Reg, volatile.LoadUint32(&o.DESTROY.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetDESTROY() uint32 { + return volatile.LoadUint32(&o.DESTROY.Reg) & 0x1 +} + +// XTS_AES.STATE: XTS-AES status register +func (o *XTS_AES_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *XTS_AES_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// XTS_AES.DATE: XTS-AES version control register +func (o *XTS_AES_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *XTS_AES_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Constants for AES: AES (Advanced Encryption Standard) Accelerator +const ( + // KEY_0: Key material key_0 configure register + // Position of KEY_0 field. + AES_KEY_0_KEY_0_Pos = 0x0 + // Bit mask of KEY_0 field. + AES_KEY_0_KEY_0_Msk = 0xffffffff + + // KEY_1: Key material key_1 configure register + // Position of KEY_1 field. + AES_KEY_1_KEY_1_Pos = 0x0 + // Bit mask of KEY_1 field. + AES_KEY_1_KEY_1_Msk = 0xffffffff + + // KEY_2: Key material key_2 configure register + // Position of KEY_2 field. + AES_KEY_2_KEY_2_Pos = 0x0 + // Bit mask of KEY_2 field. + AES_KEY_2_KEY_2_Msk = 0xffffffff + + // KEY_3: Key material key_3 configure register + // Position of KEY_3 field. + AES_KEY_3_KEY_3_Pos = 0x0 + // Bit mask of KEY_3 field. + AES_KEY_3_KEY_3_Msk = 0xffffffff + + // KEY_4: Key material key_4 configure register + // Position of KEY_4 field. + AES_KEY_4_KEY_4_Pos = 0x0 + // Bit mask of KEY_4 field. + AES_KEY_4_KEY_4_Msk = 0xffffffff + + // KEY_5: Key material key_5 configure register + // Position of KEY_5 field. + AES_KEY_5_KEY_5_Pos = 0x0 + // Bit mask of KEY_5 field. + AES_KEY_5_KEY_5_Msk = 0xffffffff + + // KEY_6: Key material key_6 configure register + // Position of KEY_6 field. + AES_KEY_6_KEY_6_Pos = 0x0 + // Bit mask of KEY_6 field. + AES_KEY_6_KEY_6_Msk = 0xffffffff + + // KEY_7: Key material key_7 configure register + // Position of KEY_7 field. + AES_KEY_7_KEY_7_Pos = 0x0 + // Bit mask of KEY_7 field. + AES_KEY_7_KEY_7_Msk = 0xffffffff + + // TEXT_IN_0: source text material text_in_0 configure register + // Position of TEXT_IN_0 field. + AES_TEXT_IN_0_TEXT_IN_0_Pos = 0x0 + // Bit mask of TEXT_IN_0 field. + AES_TEXT_IN_0_TEXT_IN_0_Msk = 0xffffffff + + // TEXT_IN_1: source text material text_in_1 configure register + // Position of TEXT_IN_1 field. + AES_TEXT_IN_1_TEXT_IN_1_Pos = 0x0 + // Bit mask of TEXT_IN_1 field. + AES_TEXT_IN_1_TEXT_IN_1_Msk = 0xffffffff + + // TEXT_IN_2: source text material text_in_2 configure register + // Position of TEXT_IN_2 field. + AES_TEXT_IN_2_TEXT_IN_2_Pos = 0x0 + // Bit mask of TEXT_IN_2 field. + AES_TEXT_IN_2_TEXT_IN_2_Msk = 0xffffffff + + // TEXT_IN_3: source text material text_in_3 configure register + // Position of TEXT_IN_3 field. + AES_TEXT_IN_3_TEXT_IN_3_Pos = 0x0 + // Bit mask of TEXT_IN_3 field. + AES_TEXT_IN_3_TEXT_IN_3_Msk = 0xffffffff + + // TEXT_OUT_0: result text material text_out_0 configure register + // Position of TEXT_OUT_0 field. + AES_TEXT_OUT_0_TEXT_OUT_0_Pos = 0x0 + // Bit mask of TEXT_OUT_0 field. + AES_TEXT_OUT_0_TEXT_OUT_0_Msk = 0xffffffff + + // TEXT_OUT_1: result text material text_out_1 configure register + // Position of TEXT_OUT_1 field. + AES_TEXT_OUT_1_TEXT_OUT_1_Pos = 0x0 + // Bit mask of TEXT_OUT_1 field. + AES_TEXT_OUT_1_TEXT_OUT_1_Msk = 0xffffffff + + // TEXT_OUT_2: result text material text_out_2 configure register + // Position of TEXT_OUT_2 field. + AES_TEXT_OUT_2_TEXT_OUT_2_Pos = 0x0 + // Bit mask of TEXT_OUT_2 field. + AES_TEXT_OUT_2_TEXT_OUT_2_Msk = 0xffffffff + + // TEXT_OUT_3: result text material text_out_3 configure register + // Position of TEXT_OUT_3 field. + AES_TEXT_OUT_3_TEXT_OUT_3_Pos = 0x0 + // Bit mask of TEXT_OUT_3 field. + AES_TEXT_OUT_3_TEXT_OUT_3_Msk = 0xffffffff + + // MODE: AES Mode register + // Position of MODE field. + AES_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + AES_MODE_MODE_Msk = 0x7 + + // ENDIAN: AES Endian configure register + // Position of ENDIAN field. + AES_ENDIAN_ENDIAN_Pos = 0x0 + // Bit mask of ENDIAN field. + AES_ENDIAN_ENDIAN_Msk = 0x3f + + // TRIGGER: AES trigger register + // Position of TRIGGER field. + AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + AES_TRIGGER_TRIGGER = 0x1 + + // STATE: AES state register + // Position of STATE field. + AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + AES_STATE_STATE_Msk = 0x3 + + // DMA_ENABLE: DMA-AES working mode register + // Position of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Pos = 0x0 + // Bit mask of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Msk = 0x1 + // Bit DMA_ENABLE. + AES_DMA_ENABLE_DMA_ENABLE = 0x1 + + // BLOCK_MODE: AES cipher block mode register + // Position of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Pos = 0x0 + // Bit mask of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Msk = 0x7 + + // BLOCK_NUM: AES block number register + // Position of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Pos = 0x0 + // Bit mask of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Msk = 0xffffffff + + // INC_SEL: Standard incrementing function configure register + // Position of INC_SEL field. + AES_INC_SEL_INC_SEL_Pos = 0x0 + // Bit mask of INC_SEL field. + AES_INC_SEL_INC_SEL_Msk = 0x1 + // Bit INC_SEL. + AES_INC_SEL_INC_SEL = 0x1 + + // AAD_BLOCK_NUM: Additional Authential Data block number register + // Position of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Pos = 0x0 + // Bit mask of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Msk = 0xffffffff + + // REMAINDER_BIT_NUM: AES remainder bit number register + // Position of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Pos = 0x0 + // Bit mask of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Msk = 0x7f + + // CONTINUE: AES continue register + // Position of CONTINUE field. + AES_CONTINUE_CONTINUE_Pos = 0x0 + // Bit mask of CONTINUE field. + AES_CONTINUE_CONTINUE_Msk = 0x1 + // Bit CONTINUE. + AES_CONTINUE_CONTINUE = 0x1 + + // INT_CLEAR: AES Interrupt clear register + // Position of INT_CLEAR field. + AES_INT_CLEAR_INT_CLEAR_Pos = 0x0 + // Bit mask of INT_CLEAR field. + AES_INT_CLEAR_INT_CLEAR_Msk = 0x1 + // Bit INT_CLEAR. + AES_INT_CLEAR_INT_CLEAR = 0x1 + + // INT_ENA: AES Interrupt enable register + // Position of INT_ENA field. + AES_INT_ENA_INT_ENA_Pos = 0x0 + // Bit mask of INT_ENA field. + AES_INT_ENA_INT_ENA_Msk = 0x1 + // Bit INT_ENA. + AES_INT_ENA_INT_ENA = 0x1 + + // DATE: AES version control register + // Position of DATE field. + AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + AES_DATE_DATE_Msk = 0x3fffffff + + // DMA_EXIT: AES-DMA exit config + // Position of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Pos = 0x0 + // Bit mask of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Msk = 0x1 + // Bit DMA_EXIT. + AES_DMA_EXIT_DMA_EXIT = 0x1 +) + +// Constants for APB_CTRL: APB (Advanced Peripheral Bus) Controller +const ( + // SYSCLK_CONF: APB_CTRL_SYSCLK_CONF_REG + // Position of PRE_DIV_CNT field. + APB_CTRL_SYSCLK_CONF_PRE_DIV_CNT_Pos = 0x0 + // Bit mask of PRE_DIV_CNT field. + APB_CTRL_SYSCLK_CONF_PRE_DIV_CNT_Msk = 0x3ff + // Position of CLK_320M_EN field. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN_Pos = 0xa + // Bit mask of CLK_320M_EN field. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN_Msk = 0x400 + // Bit CLK_320M_EN. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN = 0x400 + // Position of CLK_EN field. + APB_CTRL_SYSCLK_CONF_CLK_EN_Pos = 0xb + // Bit mask of CLK_EN field. + APB_CTRL_SYSCLK_CONF_CLK_EN_Msk = 0x800 + // Bit CLK_EN. + APB_CTRL_SYSCLK_CONF_CLK_EN = 0x800 + // Position of RST_TICK_CNT field. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT_Pos = 0xc + // Bit mask of RST_TICK_CNT field. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT_Msk = 0x1000 + // Bit RST_TICK_CNT. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT = 0x1000 + + // TICK_CONF: APB_CTRL_TICK_CONF_REG + // Position of XTAL_TICK_NUM field. + APB_CTRL_TICK_CONF_XTAL_TICK_NUM_Pos = 0x0 + // Bit mask of XTAL_TICK_NUM field. + APB_CTRL_TICK_CONF_XTAL_TICK_NUM_Msk = 0xff + // Position of CK8M_TICK_NUM field. + APB_CTRL_TICK_CONF_CK8M_TICK_NUM_Pos = 0x8 + // Bit mask of CK8M_TICK_NUM field. + APB_CTRL_TICK_CONF_CK8M_TICK_NUM_Msk = 0xff00 + // Position of TICK_ENABLE field. + APB_CTRL_TICK_CONF_TICK_ENABLE_Pos = 0x10 + // Bit mask of TICK_ENABLE field. + APB_CTRL_TICK_CONF_TICK_ENABLE_Msk = 0x10000 + // Bit TICK_ENABLE. + APB_CTRL_TICK_CONF_TICK_ENABLE = 0x10000 + + // CLK_OUT_EN: APB_CTRL_CLK_OUT_EN_REG + // Position of CLK20_OEN field. + APB_CTRL_CLK_OUT_EN_CLK20_OEN_Pos = 0x0 + // Bit mask of CLK20_OEN field. + APB_CTRL_CLK_OUT_EN_CLK20_OEN_Msk = 0x1 + // Bit CLK20_OEN. + APB_CTRL_CLK_OUT_EN_CLK20_OEN = 0x1 + // Position of CLK22_OEN field. + APB_CTRL_CLK_OUT_EN_CLK22_OEN_Pos = 0x1 + // Bit mask of CLK22_OEN field. + APB_CTRL_CLK_OUT_EN_CLK22_OEN_Msk = 0x2 + // Bit CLK22_OEN. + APB_CTRL_CLK_OUT_EN_CLK22_OEN = 0x2 + // Position of CLK44_OEN field. + APB_CTRL_CLK_OUT_EN_CLK44_OEN_Pos = 0x2 + // Bit mask of CLK44_OEN field. + APB_CTRL_CLK_OUT_EN_CLK44_OEN_Msk = 0x4 + // Bit CLK44_OEN. + APB_CTRL_CLK_OUT_EN_CLK44_OEN = 0x4 + // Position of CLK_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_BB_OEN_Pos = 0x3 + // Bit mask of CLK_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_BB_OEN_Msk = 0x8 + // Bit CLK_BB_OEN. + APB_CTRL_CLK_OUT_EN_CLK_BB_OEN = 0x8 + // Position of CLK80_OEN field. + APB_CTRL_CLK_OUT_EN_CLK80_OEN_Pos = 0x4 + // Bit mask of CLK80_OEN field. + APB_CTRL_CLK_OUT_EN_CLK80_OEN_Msk = 0x10 + // Bit CLK80_OEN. + APB_CTRL_CLK_OUT_EN_CLK80_OEN = 0x10 + // Position of CLK160_OEN field. + APB_CTRL_CLK_OUT_EN_CLK160_OEN_Pos = 0x5 + // Bit mask of CLK160_OEN field. + APB_CTRL_CLK_OUT_EN_CLK160_OEN_Msk = 0x20 + // Bit CLK160_OEN. + APB_CTRL_CLK_OUT_EN_CLK160_OEN = 0x20 + // Position of CLK_320M_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_320M_OEN_Pos = 0x6 + // Bit mask of CLK_320M_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_320M_OEN_Msk = 0x40 + // Bit CLK_320M_OEN. + APB_CTRL_CLK_OUT_EN_CLK_320M_OEN = 0x40 + // Position of CLK_ADC_INF_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Pos = 0x7 + // Bit mask of CLK_ADC_INF_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Msk = 0x80 + // Bit CLK_ADC_INF_OEN. + APB_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN = 0x80 + // Position of CLK_DAC_CPU_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN_Pos = 0x8 + // Bit mask of CLK_DAC_CPU_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN_Msk = 0x100 + // Bit CLK_DAC_CPU_OEN. + APB_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN = 0x100 + // Position of CLK40X_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK40X_BB_OEN_Pos = 0x9 + // Bit mask of CLK40X_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK40X_BB_OEN_Msk = 0x200 + // Bit CLK40X_BB_OEN. + APB_CTRL_CLK_OUT_EN_CLK40X_BB_OEN = 0x200 + // Position of CLK_XTAL_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Pos = 0xa + // Bit mask of CLK_XTAL_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Msk = 0x400 + // Bit CLK_XTAL_OEN. + APB_CTRL_CLK_OUT_EN_CLK_XTAL_OEN = 0x400 + + // WIFI_BB_CFG: APB_CTRL_WIFI_BB_CFG_REG + // Position of WIFI_BB_CFG field. + APB_CTRL_WIFI_BB_CFG_WIFI_BB_CFG_Pos = 0x0 + // Bit mask of WIFI_BB_CFG field. + APB_CTRL_WIFI_BB_CFG_WIFI_BB_CFG_Msk = 0xffffffff + + // WIFI_BB_CFG_2: APB_CTRL_WIFI_BB_CFG_2_REG + // Position of WIFI_BB_CFG_2 field. + APB_CTRL_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Pos = 0x0 + // Bit mask of WIFI_BB_CFG_2 field. + APB_CTRL_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Msk = 0xffffffff + + // WIFI_CLK_EN: APB_CTRL_WIFI_CLK_EN_REG + // Position of WIFI_CLK_EN field. + APB_CTRL_WIFI_CLK_EN_WIFI_CLK_EN_Pos = 0x0 + // Bit mask of WIFI_CLK_EN field. + APB_CTRL_WIFI_CLK_EN_WIFI_CLK_EN_Msk = 0xffffffff + + // WIFI_RST_EN: APB_CTRL_WIFI_RST_EN_REG + // Position of WIFI_RST field. + APB_CTRL_WIFI_RST_EN_WIFI_RST_Pos = 0x0 + // Bit mask of WIFI_RST field. + APB_CTRL_WIFI_RST_EN_WIFI_RST_Msk = 0xffffffff + + // HOST_INF_SEL: APB_CTRL_HOST_INF_SEL_REG + // Position of PERI_IO_SWAP field. + APB_CTRL_HOST_INF_SEL_PERI_IO_SWAP_Pos = 0x0 + // Bit mask of PERI_IO_SWAP field. + APB_CTRL_HOST_INF_SEL_PERI_IO_SWAP_Msk = 0xff + + // EXT_MEM_PMS_LOCK: APB_CTRL_EXT_MEM_PMS_LOCK_REG + // Position of EXT_MEM_PMS_LOCK field. + APB_CTRL_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK_Pos = 0x0 + // Bit mask of EXT_MEM_PMS_LOCK field. + APB_CTRL_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK_Msk = 0x1 + // Bit EXT_MEM_PMS_LOCK. + APB_CTRL_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK = 0x1 + + // FLASH_ACE0_ATTR: APB_CTRL_FLASH_ACE0_ATTR_REG + // Position of FLASH_ACE0_ATTR field. + APB_CTRL_FLASH_ACE0_ATTR_FLASH_ACE0_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE0_ATTR field. + APB_CTRL_FLASH_ACE0_ATTR_FLASH_ACE0_ATTR_Msk = 0x3 + + // FLASH_ACE1_ATTR: APB_CTRL_FLASH_ACE1_ATTR_REG + // Position of FLASH_ACE1_ATTR field. + APB_CTRL_FLASH_ACE1_ATTR_FLASH_ACE1_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE1_ATTR field. + APB_CTRL_FLASH_ACE1_ATTR_FLASH_ACE1_ATTR_Msk = 0x3 + + // FLASH_ACE2_ATTR: APB_CTRL_FLASH_ACE2_ATTR_REG + // Position of FLASH_ACE2_ATTR field. + APB_CTRL_FLASH_ACE2_ATTR_FLASH_ACE2_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE2_ATTR field. + APB_CTRL_FLASH_ACE2_ATTR_FLASH_ACE2_ATTR_Msk = 0x3 + + // FLASH_ACE3_ATTR: APB_CTRL_FLASH_ACE3_ATTR_REG + // Position of FLASH_ACE3_ATTR field. + APB_CTRL_FLASH_ACE3_ATTR_FLASH_ACE3_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE3_ATTR field. + APB_CTRL_FLASH_ACE3_ATTR_FLASH_ACE3_ATTR_Msk = 0x3 + + // FLASH_ACE0_ADDR: APB_CTRL_FLASH_ACE0_ADDR_REG + // Position of S field. + APB_CTRL_FLASH_ACE0_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE0_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE1_ADDR: APB_CTRL_FLASH_ACE1_ADDR_REG + // Position of S field. + APB_CTRL_FLASH_ACE1_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE1_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE2_ADDR: APB_CTRL_FLASH_ACE2_ADDR_REG + // Position of S field. + APB_CTRL_FLASH_ACE2_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE2_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE3_ADDR: APB_CTRL_FLASH_ACE3_ADDR_REG + // Position of S field. + APB_CTRL_FLASH_ACE3_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE3_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE0_SIZE: APB_CTRL_FLASH_ACE0_SIZE_REG + // Position of FLASH_ACE0_SIZE field. + APB_CTRL_FLASH_ACE0_SIZE_FLASH_ACE0_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE0_SIZE field. + APB_CTRL_FLASH_ACE0_SIZE_FLASH_ACE0_SIZE_Msk = 0x1fff + + // FLASH_ACE1_SIZE: APB_CTRL_FLASH_ACE1_SIZE_REG + // Position of FLASH_ACE1_SIZE field. + APB_CTRL_FLASH_ACE1_SIZE_FLASH_ACE1_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE1_SIZE field. + APB_CTRL_FLASH_ACE1_SIZE_FLASH_ACE1_SIZE_Msk = 0x1fff + + // FLASH_ACE2_SIZE: APB_CTRL_FLASH_ACE2_SIZE_REG + // Position of FLASH_ACE2_SIZE field. + APB_CTRL_FLASH_ACE2_SIZE_FLASH_ACE2_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE2_SIZE field. + APB_CTRL_FLASH_ACE2_SIZE_FLASH_ACE2_SIZE_Msk = 0x1fff + + // FLASH_ACE3_SIZE: APB_CTRL_FLASH_ACE3_SIZE_REG + // Position of FLASH_ACE3_SIZE field. + APB_CTRL_FLASH_ACE3_SIZE_FLASH_ACE3_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE3_SIZE field. + APB_CTRL_FLASH_ACE3_SIZE_FLASH_ACE3_SIZE_Msk = 0x1fff + + // SPI_MEM_PMS_CTRL: APB_CTRL_SPI_MEM_PMS_CTRL_REG + // Position of SPI_MEM_REJECT_INT field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_INT field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT_Msk = 0x1 + // Bit SPI_MEM_REJECT_INT. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT = 0x1 + // Position of SPI_MEM_REJECT_CLR field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR_Pos = 0x1 + // Bit mask of SPI_MEM_REJECT_CLR field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR_Msk = 0x2 + // Bit SPI_MEM_REJECT_CLR. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR = 0x2 + // Position of SPI_MEM_REJECT_CDE field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE_Pos = 0x2 + // Bit mask of SPI_MEM_REJECT_CDE field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE_Msk = 0x7c + + // SPI_MEM_REJECT_ADDR: APB_CTRL_SPI_MEM_REJECT_ADDR_REG + // Position of SPI_MEM_REJECT_ADDR field. + APB_CTRL_SPI_MEM_REJECT_ADDR_SPI_MEM_REJECT_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_ADDR field. + APB_CTRL_SPI_MEM_REJECT_ADDR_SPI_MEM_REJECT_ADDR_Msk = 0xffffffff + + // SDIO_CTRL: APB_CTRL_SDIO_CTRL_REG + // Position of SDIO_WIN_ACCESS_EN field. + APB_CTRL_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Pos = 0x0 + // Bit mask of SDIO_WIN_ACCESS_EN field. + APB_CTRL_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Msk = 0x1 + // Bit SDIO_WIN_ACCESS_EN. + APB_CTRL_SDIO_CTRL_SDIO_WIN_ACCESS_EN = 0x1 + + // REDCY_SIG0: APB_CTRL_REDCY_SIG0_REG_REG + // Position of REDCY_SIG0 field. + APB_CTRL_REDCY_SIG0_REDCY_SIG0_Pos = 0x0 + // Bit mask of REDCY_SIG0 field. + APB_CTRL_REDCY_SIG0_REDCY_SIG0_Msk = 0x7fffffff + // Position of REDCY_ANDOR field. + APB_CTRL_REDCY_SIG0_REDCY_ANDOR_Pos = 0x1f + // Bit mask of REDCY_ANDOR field. + APB_CTRL_REDCY_SIG0_REDCY_ANDOR_Msk = 0x80000000 + // Bit REDCY_ANDOR. + APB_CTRL_REDCY_SIG0_REDCY_ANDOR = 0x80000000 + + // REDCY_SIG1: APB_CTRL_REDCY_SIG1_REG_REG + // Position of REDCY_SIG1 field. + APB_CTRL_REDCY_SIG1_REDCY_SIG1_Pos = 0x0 + // Bit mask of REDCY_SIG1 field. + APB_CTRL_REDCY_SIG1_REDCY_SIG1_Msk = 0x7fffffff + // Position of REDCY_NANDOR field. + APB_CTRL_REDCY_SIG1_REDCY_NANDOR_Pos = 0x1f + // Bit mask of REDCY_NANDOR field. + APB_CTRL_REDCY_SIG1_REDCY_NANDOR_Msk = 0x80000000 + // Bit REDCY_NANDOR. + APB_CTRL_REDCY_SIG1_REDCY_NANDOR = 0x80000000 + + // FRONT_END_MEM_PD: APB_CTRL_FRONT_END_MEM_PD_REG + // Position of AGC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Pos = 0x0 + // Bit mask of AGC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Msk = 0x1 + // Bit AGC_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU = 0x1 + // Position of AGC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of AGC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Msk = 0x2 + // Bit AGC_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD = 0x2 + // Position of PBUS_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of PBUS_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Msk = 0x4 + // Bit PBUS_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU = 0x4 + // Position of PBUS_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of PBUS_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Msk = 0x8 + // Bit PBUS_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD = 0x8 + // Position of DC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of DC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PU_Msk = 0x10 + // Bit DC_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PU = 0x10 + // Position of DC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PD_Pos = 0x5 + // Bit mask of DC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PD_Msk = 0x20 + // Bit DC_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PD = 0x20 + + // RETENTION_CTRL: APB_CTRL_RETENTION_CTRL_REG + // Position of RETENTION_LINK_ADDR field. + APB_CTRL_RETENTION_CTRL_RETENTION_LINK_ADDR_Pos = 0x0 + // Bit mask of RETENTION_LINK_ADDR field. + APB_CTRL_RETENTION_CTRL_RETENTION_LINK_ADDR_Msk = 0x7ffffff + // Position of NOBYPASS_CPU_ISO_RST field. + APB_CTRL_RETENTION_CTRL_NOBYPASS_CPU_ISO_RST_Pos = 0x1b + // Bit mask of NOBYPASS_CPU_ISO_RST field. + APB_CTRL_RETENTION_CTRL_NOBYPASS_CPU_ISO_RST_Msk = 0x8000000 + // Bit NOBYPASS_CPU_ISO_RST. + APB_CTRL_RETENTION_CTRL_NOBYPASS_CPU_ISO_RST = 0x8000000 + + // CLKGATE_FORCE_ON: APB_CTRL_CLKGATE_FORCE_ON_REG + // Position of ROM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON_Pos = 0x0 + // Bit mask of ROM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON_Msk = 0x3 + // Position of SRAM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON_Pos = 0x2 + // Bit mask of SRAM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON_Msk = 0x3c + + // MEM_POWER_DOWN: APB_CTRL_MEM_POWER_DOWN_REG + // Position of ROM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_ROM_POWER_DOWN_Pos = 0x0 + // Bit mask of ROM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_ROM_POWER_DOWN_Msk = 0x3 + // Position of SRAM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_SRAM_POWER_DOWN_Pos = 0x2 + // Bit mask of SRAM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_SRAM_POWER_DOWN_Msk = 0x3c + + // MEM_POWER_UP: APB_CTRL_MEM_POWER_UP_REG + // Position of ROM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_ROM_POWER_UP_Pos = 0x0 + // Bit mask of ROM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_ROM_POWER_UP_Msk = 0x3 + // Position of SRAM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_SRAM_POWER_UP_Pos = 0x2 + // Bit mask of SRAM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_SRAM_POWER_UP_Msk = 0x3c + + // RND_DATA: APB_CTRL_RND_DATA_REG + // Position of RND_DATA field. + APB_CTRL_RND_DATA_RND_DATA_Pos = 0x0 + // Bit mask of RND_DATA field. + APB_CTRL_RND_DATA_RND_DATA_Msk = 0xffffffff + + // PERI_BACKUP_CONFIG: APB_CTRL_PERI_BACKUP_CONFIG_REG_REG + // Position of PERI_BACKUP_FLOW_ERR field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_FLOW_ERR_Pos = 0x1 + // Bit mask of PERI_BACKUP_FLOW_ERR field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_FLOW_ERR_Msk = 0x6 + // Position of PERI_BACKUP_BURST_LIMIT field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_BURST_LIMIT_Pos = 0x4 + // Bit mask of PERI_BACKUP_BURST_LIMIT field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_BURST_LIMIT_Msk = 0x1f0 + // Position of PERI_BACKUP_TOUT_THRES field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TOUT_THRES_Pos = 0x9 + // Bit mask of PERI_BACKUP_TOUT_THRES field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TOUT_THRES_Msk = 0x7fe00 + // Position of PERI_BACKUP_SIZE field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_SIZE_Pos = 0x13 + // Bit mask of PERI_BACKUP_SIZE field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_SIZE_Msk = 0x1ff80000 + // Position of PERI_BACKUP_START field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_START_Pos = 0x1d + // Bit mask of PERI_BACKUP_START field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_START_Msk = 0x20000000 + // Bit PERI_BACKUP_START. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_START = 0x20000000 + // Position of PERI_BACKUP_TO_MEM field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM_Pos = 0x1e + // Bit mask of PERI_BACKUP_TO_MEM field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM_Msk = 0x40000000 + // Bit PERI_BACKUP_TO_MEM. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_TO_MEM = 0x40000000 + // Position of PERI_BACKUP_ENA field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_ENA_Pos = 0x1f + // Bit mask of PERI_BACKUP_ENA field. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_ENA_Msk = 0x80000000 + // Bit PERI_BACKUP_ENA. + APB_CTRL_PERI_BACKUP_CONFIG_PERI_BACKUP_ENA = 0x80000000 + + // PERI_BACKUP_APB_ADDR: APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG + // Position of BACKUP_APB_START_ADDR field. + APB_CTRL_PERI_BACKUP_APB_ADDR_BACKUP_APB_START_ADDR_Pos = 0x0 + // Bit mask of BACKUP_APB_START_ADDR field. + APB_CTRL_PERI_BACKUP_APB_ADDR_BACKUP_APB_START_ADDR_Msk = 0xffffffff + + // PERI_BACKUP_MEM_ADDR: APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG + // Position of BACKUP_MEM_START_ADDR field. + APB_CTRL_PERI_BACKUP_MEM_ADDR_BACKUP_MEM_START_ADDR_Pos = 0x0 + // Bit mask of BACKUP_MEM_START_ADDR field. + APB_CTRL_PERI_BACKUP_MEM_ADDR_BACKUP_MEM_START_ADDR_Msk = 0xffffffff + + // PERI_BACKUP_INT_RAW: APB_CTRL_PERI_BACKUP_INT_RAW_REG + // Position of PERI_BACKUP_DONE_INT_RAW field. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW_Pos = 0x0 + // Bit mask of PERI_BACKUP_DONE_INT_RAW field. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW_Msk = 0x1 + // Bit PERI_BACKUP_DONE_INT_RAW. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_DONE_INT_RAW = 0x1 + // Position of PERI_BACKUP_ERR_INT_RAW field. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW_Pos = 0x1 + // Bit mask of PERI_BACKUP_ERR_INT_RAW field. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW_Msk = 0x2 + // Bit PERI_BACKUP_ERR_INT_RAW. + APB_CTRL_PERI_BACKUP_INT_RAW_PERI_BACKUP_ERR_INT_RAW = 0x2 + + // PERI_BACKUP_INT_ST: APB_CTRL_PERI_BACKUP_INT_ST_REG + // Position of PERI_BACKUP_DONE_INT_ST field. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST_Pos = 0x0 + // Bit mask of PERI_BACKUP_DONE_INT_ST field. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST_Msk = 0x1 + // Bit PERI_BACKUP_DONE_INT_ST. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_DONE_INT_ST = 0x1 + // Position of PERI_BACKUP_ERR_INT_ST field. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST_Pos = 0x1 + // Bit mask of PERI_BACKUP_ERR_INT_ST field. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST_Msk = 0x2 + // Bit PERI_BACKUP_ERR_INT_ST. + APB_CTRL_PERI_BACKUP_INT_ST_PERI_BACKUP_ERR_INT_ST = 0x2 + + // PERI_BACKUP_INT_ENA: APB_CTRL_PERI_BACKUP_INT_ENA_REG + // Position of PERI_BACKUP_DONE_INT_ENA field. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA_Pos = 0x0 + // Bit mask of PERI_BACKUP_DONE_INT_ENA field. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA_Msk = 0x1 + // Bit PERI_BACKUP_DONE_INT_ENA. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_DONE_INT_ENA = 0x1 + // Position of PERI_BACKUP_ERR_INT_ENA field. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA_Pos = 0x1 + // Bit mask of PERI_BACKUP_ERR_INT_ENA field. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA_Msk = 0x2 + // Bit PERI_BACKUP_ERR_INT_ENA. + APB_CTRL_PERI_BACKUP_INT_ENA_PERI_BACKUP_ERR_INT_ENA = 0x2 + + // PERI_BACKUP_INT_CLR: APB_CTRL_PERI_BACKUP_INT_CLR_REG + // Position of PERI_BACKUP_DONE_INT_CLR field. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR_Pos = 0x0 + // Bit mask of PERI_BACKUP_DONE_INT_CLR field. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR_Msk = 0x1 + // Bit PERI_BACKUP_DONE_INT_CLR. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_DONE_INT_CLR = 0x1 + // Position of PERI_BACKUP_ERR_INT_CLR field. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR_Pos = 0x1 + // Bit mask of PERI_BACKUP_ERR_INT_CLR field. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR_Msk = 0x2 + // Bit PERI_BACKUP_ERR_INT_CLR. + APB_CTRL_PERI_BACKUP_INT_CLR_PERI_BACKUP_ERR_INT_CLR = 0x2 + + // DATE: APB_CTRL_DATE_REG + // Position of DATE field. + APB_CTRL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + APB_CTRL_DATE_DATE_Msk = 0xffffffff +) + +// Constants for APB_SARADC: SAR (Successive Approximation Register) Analog-to-Digital Converter +const ( + // CTRL: digital saradc configure register + // Position of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Pos = 0x0 + // Bit mask of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Msk = 0x1 + // Bit SARADC_START_FORCE. + APB_SARADC_CTRL_SARADC_START_FORCE = 0x1 + // Position of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Pos = 0x1 + // Bit mask of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Msk = 0x2 + // Bit SARADC_START. + APB_SARADC_CTRL_SARADC_START = 0x2 + // Position of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Pos = 0x6 + // Bit mask of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Msk = 0x40 + // Bit SARADC_SAR_CLK_GATED. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED = 0x40 + // Position of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Pos = 0x7 + // Bit mask of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Msk = 0x7f80 + // Position of SARADC_SAR_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR_PATT_LEN_Pos = 0xf + // Bit mask of SARADC_SAR_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR_PATT_LEN_Msk = 0x38000 + // Position of SARADC_SAR_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR_Pos = 0x17 + // Bit mask of SARADC_SAR_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR_Msk = 0x800000 + // Bit SARADC_SAR_PATT_P_CLEAR. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR = 0x800000 + // Position of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Pos = 0x1b + // Bit mask of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Msk = 0x18000000 + // Position of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Pos = 0x1e + // Bit mask of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Msk = 0xc0000000 + + // CTRL2: digital saradc configure register + // Position of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Pos = 0x0 + // Bit mask of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Msk = 0x1 + // Bit SARADC_MEAS_NUM_LIMIT. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT = 0x1 + // Position of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Pos = 0x1 + // Bit mask of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Msk = 0x1fe + // Position of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Pos = 0x9 + // Bit mask of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Msk = 0x200 + // Bit SARADC_SAR1_INV. + APB_SARADC_CTRL2_SARADC_SAR1_INV = 0x200 + // Position of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Pos = 0xa + // Bit mask of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Msk = 0x400 + // Bit SARADC_SAR2_INV. + APB_SARADC_CTRL2_SARADC_SAR2_INV = 0x400 + // Position of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Pos = 0xc + // Bit mask of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Msk = 0xfff000 + // Position of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Pos = 0x18 + // Bit mask of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Msk = 0x1000000 + // Bit SARADC_TIMER_EN. + APB_SARADC_CTRL2_SARADC_TIMER_EN = 0x1000000 + + // FILTER_CTRL1: digital saradc configure register + // Position of APB_SARADC_FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR1_Pos = 0x1a + // Bit mask of APB_SARADC_FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR1_Msk = 0x1c000000 + // Position of APB_SARADC_FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR0_Pos = 0x1d + // Bit mask of APB_SARADC_FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR0_Msk = 0xe0000000 + + // FSM_WAIT: digital saradc configure register + // Position of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Pos = 0x0 + // Bit mask of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Msk = 0xff + // Position of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Pos = 0x8 + // Bit mask of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Msk = 0xff00 + // Position of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Pos = 0x10 + // Bit mask of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Msk = 0xff0000 + + // SAR1_STATUS: digital saradc configure register + // Position of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Msk = 0xffffffff + + // SAR2_STATUS: digital saradc configure register + // Position of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Msk = 0xffffffff + + // SAR_PATT_TAB1: digital saradc configure register + // Position of SARADC_SAR_PATT_TAB1 field. + APB_SARADC_SAR_PATT_TAB1_SARADC_SAR_PATT_TAB1_Pos = 0x0 + // Bit mask of SARADC_SAR_PATT_TAB1 field. + APB_SARADC_SAR_PATT_TAB1_SARADC_SAR_PATT_TAB1_Msk = 0xffffff + + // SAR_PATT_TAB2: digital saradc configure register + // Position of SARADC_SAR_PATT_TAB2 field. + APB_SARADC_SAR_PATT_TAB2_SARADC_SAR_PATT_TAB2_Pos = 0x0 + // Bit mask of SARADC_SAR_PATT_TAB2 field. + APB_SARADC_SAR_PATT_TAB2_SARADC_SAR_PATT_TAB2_Msk = 0xffffff + + // ONETIME_SAMPLE: digital saradc configure register + // Position of SARADC_ONETIME_ATTEN field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_ATTEN_Pos = 0x17 + // Bit mask of SARADC_ONETIME_ATTEN field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_ATTEN_Msk = 0x1800000 + // Position of SARADC_ONETIME_CHANNEL field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_CHANNEL_Pos = 0x19 + // Bit mask of SARADC_ONETIME_CHANNEL field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_CHANNEL_Msk = 0x1e000000 + // Position of SARADC_ONETIME_START field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START_Pos = 0x1d + // Bit mask of SARADC_ONETIME_START field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START_Msk = 0x20000000 + // Bit SARADC_ONETIME_START. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START = 0x20000000 + // Position of SARADC2_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE_Pos = 0x1e + // Bit mask of SARADC2_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE_Msk = 0x40000000 + // Bit SARADC2_ONETIME_SAMPLE. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE = 0x40000000 + // Position of SARADC1_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE_Pos = 0x1f + // Bit mask of SARADC1_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE_Msk = 0x80000000 + // Bit SARADC1_ONETIME_SAMPLE. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE = 0x80000000 + + // ARB_CTRL: digital saradc configure register + // Position of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Pos = 0x2 + // Bit mask of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Msk = 0x4 + // Bit ADC_ARB_APB_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE = 0x4 + // Position of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Pos = 0x3 + // Bit mask of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Msk = 0x8 + // Bit ADC_ARB_RTC_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE = 0x8 + // Position of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Pos = 0x4 + // Bit mask of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Msk = 0x10 + // Bit ADC_ARB_WIFI_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE = 0x10 + // Position of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Pos = 0x5 + // Bit mask of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Msk = 0x20 + // Bit ADC_ARB_GRANT_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE = 0x20 + // Position of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Pos = 0x6 + // Bit mask of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Msk = 0xc0 + // Position of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Pos = 0x8 + // Bit mask of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Msk = 0x300 + // Position of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Pos = 0xa + // Bit mask of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Msk = 0xc00 + // Position of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Pos = 0xc + // Bit mask of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Msk = 0x1000 + // Bit ADC_ARB_FIX_PRIORITY. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY = 0x1000 + + // FILTER_CTRL0: digital saradc configure register + // Position of APB_SARADC_FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1_Pos = 0x12 + // Bit mask of APB_SARADC_FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1_Msk = 0x3c0000 + // Position of APB_SARADC_FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0_Pos = 0x16 + // Bit mask of APB_SARADC_FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0_Msk = 0x3c00000 + // Position of APB_SARADC_FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_RESET_Pos = 0x1f + // Bit mask of APB_SARADC_FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_RESET_Msk = 0x80000000 + // Bit APB_SARADC_FILTER_RESET. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_RESET = 0x80000000 + + // SAR1DATA_STATUS: digital saradc configure register + // Position of APB_SARADC1_DATA field. + APB_SARADC_SAR1DATA_STATUS_APB_SARADC1_DATA_Pos = 0x0 + // Bit mask of APB_SARADC1_DATA field. + APB_SARADC_SAR1DATA_STATUS_APB_SARADC1_DATA_Msk = 0x1ffff + + // SAR2DATA_STATUS: digital saradc configure register + // Position of APB_SARADC2_DATA field. + APB_SARADC_SAR2DATA_STATUS_APB_SARADC2_DATA_Pos = 0x0 + // Bit mask of APB_SARADC2_DATA field. + APB_SARADC_SAR2DATA_STATUS_APB_SARADC2_DATA_Msk = 0x1ffff + + // THRES0_CTRL: digital saradc configure register + // Position of APB_SARADC_THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_CHANNEL_Pos = 0x0 + // Bit mask of APB_SARADC_THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_CHANNEL_Msk = 0xf + // Position of APB_SARADC_THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_HIGH_Pos = 0x5 + // Bit mask of APB_SARADC_THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_HIGH_Msk = 0x3ffe0 + // Position of APB_SARADC_THRES0_LOW field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_LOW_Pos = 0x12 + // Bit mask of APB_SARADC_THRES0_LOW field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_LOW_Msk = 0x7ffc0000 + + // THRES1_CTRL: digital saradc configure register + // Position of APB_SARADC_THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_CHANNEL_Pos = 0x0 + // Bit mask of APB_SARADC_THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_CHANNEL_Msk = 0xf + // Position of APB_SARADC_THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_HIGH_Pos = 0x5 + // Bit mask of APB_SARADC_THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_HIGH_Msk = 0x3ffe0 + // Position of APB_SARADC_THRES1_LOW field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_LOW_Pos = 0x12 + // Bit mask of APB_SARADC_THRES1_LOW field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_LOW_Msk = 0x7ffc0000 + + // THRES_CTRL: digital saradc configure register + // Position of APB_SARADC_THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES_ALL_EN_Pos = 0x1b + // Bit mask of APB_SARADC_THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES_ALL_EN_Msk = 0x8000000 + // Bit APB_SARADC_THRES_ALL_EN. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES_ALL_EN = 0x8000000 + // Position of APB_SARADC_THRES1_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES1_EN_Pos = 0x1e + // Bit mask of APB_SARADC_THRES1_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES1_EN_Msk = 0x40000000 + // Bit APB_SARADC_THRES1_EN. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES1_EN = 0x40000000 + // Position of APB_SARADC_THRES0_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES0_EN_Pos = 0x1f + // Bit mask of APB_SARADC_THRES0_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES0_EN_Msk = 0x80000000 + // Bit APB_SARADC_THRES0_EN. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES0_EN = 0x80000000 + + // INT_ENA: digital saradc int register + // Position of APB_SARADC_THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_LOW_INT_ENA_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_LOW_INT_ENA_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_LOW_INT_ENA = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_LOW_INT_ENA_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_LOW_INT_ENA_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_LOW_INT_ENA = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA = 0x80000000 + + // INT_RAW: digital saradc int register + // Position of APB_SARADC_THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_LOW_INT_RAW_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_LOW_INT_RAW_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_LOW_INT_RAW = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_LOW_INT_RAW_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_LOW_INT_RAW_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_LOW_INT_RAW = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW = 0x20000000 + // Position of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW = 0x40000000 + // Position of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW = 0x80000000 + + // INT_ST: digital saradc int register + // Position of APB_SARADC_THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_LOW_INT_ST_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_LOW_INT_ST_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES1_LOW_INT_ST = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_LOW_INT_ST_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_LOW_INT_ST_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES0_LOW_INT_ST = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_HIGH_INT_ST_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_HIGH_INT_ST_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES1_HIGH_INT_ST = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_HIGH_INT_ST_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_HIGH_INT_ST_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES0_HIGH_INT_ST = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST = 0x80000000 + + // INT_CLR: digital saradc int register + // Position of APB_SARADC_THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_LOW_INT_CLR_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_LOW_INT_CLR_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_LOW_INT_CLR = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_LOW_INT_CLR_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_LOW_INT_CLR_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_LOW_INT_CLR = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR = 0x20000000 + // Position of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR = 0x40000000 + // Position of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR = 0x80000000 + + // DMA_CONF: digital saradc configure register + // Position of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Pos = 0x0 + // Bit mask of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Msk = 0xffff + // Position of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Pos = 0x1e + // Bit mask of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Msk = 0x40000000 + // Bit APB_ADC_RESET_FSM. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM = 0x40000000 + // Position of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Pos = 0x1f + // Bit mask of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Msk = 0x80000000 + // Bit APB_ADC_TRANS. + APB_SARADC_DMA_CONF_APB_ADC_TRANS = 0x80000000 + + // CLKM_CONF: digital saradc configure register + // Position of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Msk = 0xff + // Position of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Pos = 0x8 + // Bit mask of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Msk = 0x3f00 + // Position of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Pos = 0xe + // Bit mask of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Msk = 0xfc000 + // Position of CLK_EN field. + APB_SARADC_CLKM_CONF_CLK_EN_Pos = 0x14 + // Bit mask of CLK_EN field. + APB_SARADC_CLKM_CONF_CLK_EN_Msk = 0x100000 + // Bit CLK_EN. + APB_SARADC_CLKM_CONF_CLK_EN = 0x100000 + // Position of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Pos = 0x15 + // Bit mask of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Msk = 0x600000 + + // APB_TSENS_CTRL: digital tsens configure register + // Position of TSENS_OUT field. + APB_SARADC_APB_TSENS_CTRL_TSENS_OUT_Pos = 0x0 + // Bit mask of TSENS_OUT field. + APB_SARADC_APB_TSENS_CTRL_TSENS_OUT_Msk = 0xff + // Position of TSENS_IN_INV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_IN_INV_Pos = 0xd + // Bit mask of TSENS_IN_INV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_IN_INV_Msk = 0x2000 + // Bit TSENS_IN_INV. + APB_SARADC_APB_TSENS_CTRL_TSENS_IN_INV = 0x2000 + // Position of TSENS_CLK_DIV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_CLK_DIV_Pos = 0xe + // Bit mask of TSENS_CLK_DIV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_CLK_DIV_Msk = 0x3fc000 + // Position of TSENS_PU field. + APB_SARADC_APB_TSENS_CTRL_TSENS_PU_Pos = 0x16 + // Bit mask of TSENS_PU field. + APB_SARADC_APB_TSENS_CTRL_TSENS_PU_Msk = 0x400000 + // Bit TSENS_PU. + APB_SARADC_APB_TSENS_CTRL_TSENS_PU = 0x400000 + + // TSENS_CTRL2: digital tsens configure register + // Position of TSENS_XPD_WAIT field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_WAIT_Pos = 0x0 + // Bit mask of TSENS_XPD_WAIT field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_WAIT_Msk = 0xfff + // Position of TSENS_XPD_FORCE field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_FORCE_Pos = 0xc + // Bit mask of TSENS_XPD_FORCE field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_FORCE_Msk = 0x3000 + // Position of TSENS_CLK_INV field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_INV_Pos = 0xe + // Bit mask of TSENS_CLK_INV field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_INV_Msk = 0x4000 + // Bit TSENS_CLK_INV. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_INV = 0x4000 + // Position of TSENS_CLK_SEL field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_SEL_Pos = 0xf + // Bit mask of TSENS_CLK_SEL field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_SEL_Msk = 0x8000 + // Bit TSENS_CLK_SEL. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_SEL = 0x8000 + + // CALI: digital saradc configure register + // Position of APB_SARADC_CALI_CFG field. + APB_SARADC_CALI_APB_SARADC_CALI_CFG_Pos = 0x0 + // Bit mask of APB_SARADC_CALI_CFG field. + APB_SARADC_CALI_APB_SARADC_CALI_CFG_Msk = 0x1ffff + + // CTRL_DATE: version + // Position of DATE field. + APB_SARADC_CTRL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + APB_SARADC_CTRL_DATE_DATE_Msk = 0xffffffff +) + +// Constants for ASSIST_DEBUG: Debug Assist +const ( + // CORE_0_MONTR_ENA: ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG + // Position of CORE_0_AREA_DRAM0_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA = 0x80 + // Position of CORE_0_SP_SPILL_MIN_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA = 0x100 + // Position of CORE_0_SP_SPILL_MAX_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA = 0x800 + + // CORE_0_INTR_RAW: ASSIST_DEBUG_CORE_0_INTR_RAW_REG + // Position of CORE_0_AREA_DRAM0_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW = 0x80 + // Position of CORE_0_SP_SPILL_MIN_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW = 0x100 + // Position of CORE_0_SP_SPILL_MAX_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW = 0x800 + + // CORE_0_INTR_ENA: ASSIST_DEBUG_CORE_0_INTR_ENA_REG + // Position of CORE_0_AREA_DRAM0_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA = 0x80 + // Position of CORE_0_SP_SPILL_MIN_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA = 0x100 + // Position of CORE_0_SP_SPILL_MAX_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_RLS field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_RLS field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_RLS. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_RLS field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_RLS field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_RLS. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS = 0x800 + + // CORE_0_INTR_CLR: ASSIST_DEBUG_CORE_0_INTR_CLR_REG + // Position of CORE_0_AREA_DRAM0_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR = 0x80 + // Position of CORE_0_SP_SPILL_MIN_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR = 0x100 + // Position of CORE_0_SP_SPILL_MAX_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR = 0x800 + + // CORE_0_AREA_DRAM0_0_MIN: ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG + // Position of CORE_0_AREA_DRAM0_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_0_MAX: ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG + // Position of CORE_0_AREA_DRAM0_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_1_MIN: ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG + // Position of CORE_0_AREA_DRAM0_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_1_MAX: ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG + // Position of CORE_0_AREA_DRAM0_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PIF_0_MIN: ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG + // Position of CORE_0_AREA_PIF_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Msk = 0xffffffff + + // CORE_0_AREA_PIF_0_MAX: ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG + // Position of CORE_0_AREA_PIF_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PIF_1_MIN: ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG + // Position of CORE_0_AREA_PIF_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Msk = 0xffffffff + + // CORE_0_AREA_PIF_1_MAX: ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG + // Position of CORE_0_AREA_PIF_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PC: ASSIST_DEBUG_CORE_0_AREA_PC_REG + // Position of CORE_0_AREA_PC field. + ASSIST_DEBUG_CORE_0_AREA_PC_CORE_0_AREA_PC_Pos = 0x0 + // Bit mask of CORE_0_AREA_PC field. + ASSIST_DEBUG_CORE_0_AREA_PC_CORE_0_AREA_PC_Msk = 0xffffffff + + // CORE_0_AREA_SP: ASSIST_DEBUG_CORE_0_AREA_SP_REG + // Position of CORE_0_AREA_SP field. + ASSIST_DEBUG_CORE_0_AREA_SP_CORE_0_AREA_SP_Pos = 0x0 + // Bit mask of CORE_0_AREA_SP field. + ASSIST_DEBUG_CORE_0_AREA_SP_CORE_0_AREA_SP_Msk = 0xffffffff + + // CORE_0_SP_MIN: ASSIST_DEBUG_CORE_0_SP_MIN_REG + // Position of CORE_0_SP_MIN field. + ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Pos = 0x0 + // Bit mask of CORE_0_SP_MIN field. + ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Msk = 0xffffffff + + // CORE_0_SP_MAX: ASSIST_DEBUG_CORE_0_SP_MAX_REG + // Position of CORE_0_SP_MAX field. + ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Pos = 0x0 + // Bit mask of CORE_0_SP_MAX field. + ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Msk = 0xffffffff + + // CORE_0_SP_PC: ASSIST_DEBUG_CORE_0_SP_PC_REG + // Position of CORE_0_SP_PC field. + ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Pos = 0x0 + // Bit mask of CORE_0_SP_PC field. + ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Msk = 0xffffffff + + // CORE_0_RCD_EN: ASSIST_DEBUG_CORE_0_RCD_EN_REG + // Position of CORE_0_RCD_RECORDEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Pos = 0x0 + // Bit mask of CORE_0_RCD_RECORDEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Msk = 0x1 + // Bit CORE_0_RCD_RECORDEN. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN = 0x1 + // Position of CORE_0_RCD_PDEBUGEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Pos = 0x1 + // Bit mask of CORE_0_RCD_PDEBUGEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Msk = 0x2 + // Bit CORE_0_RCD_PDEBUGEN. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN = 0x2 + + // CORE_0_RCD_PDEBUGPC: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG + // Position of CORE_0_RCD_PDEBUGPC field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGPC field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGSP: ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG + // Position of CORE_0_RCD_PDEBUGSP field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGSP field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Msk = 0xffffffff + + // CORE_0_IRAM0_EXCEPTION_MONITOR_0: ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG + // Position of CORE_0_IRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Msk = 0xffffff + // Position of CORE_0_IRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Pos = 0x18 + // Bit mask of CORE_0_IRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Msk = 0x1000000 + // Bit CORE_0_IRAM0_RECORDING_WR_0. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0 = 0x1000000 + // Position of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Pos = 0x19 + // Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Msk = 0x2000000 + // Bit CORE_0_IRAM0_RECORDING_LOADSTORE_0. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0 = 0x2000000 + + // CORE_0_IRAM0_EXCEPTION_MONITOR_1: ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG + // Position of CORE_0_IRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Msk = 0xffffff + // Position of CORE_0_IRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Pos = 0x18 + // Bit mask of CORE_0_IRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Msk = 0x1000000 + // Bit CORE_0_IRAM0_RECORDING_WR_1. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1 = 0x1000000 + // Position of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Pos = 0x19 + // Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Msk = 0x2000000 + // Bit CORE_0_IRAM0_RECORDING_LOADSTORE_1. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1 = 0x2000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_0: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG + // Position of CORE_0_DRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0_Msk = 0xffffff + // Position of CORE_0_DRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Pos = 0x18 + // Bit mask of CORE_0_DRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Msk = 0x1000000 + // Bit CORE_0_DRAM0_RECORDING_WR_0. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0 = 0x1000000 + // Position of CORE_0_DRAM0_RECORDING_BYTEEN_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0_Pos = 0x19 + // Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0_Msk = 0x1e000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_1: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG + // Position of CORE_0_DRAM0_RECORDING_PC_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_PC_0_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_PC_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_PC_0_Msk = 0xffffffff + + // CORE_0_DRAM0_EXCEPTION_MONITOR_2: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG + // Position of CORE_0_DRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1_Msk = 0xffffff + // Position of CORE_0_DRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1_Pos = 0x18 + // Bit mask of CORE_0_DRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1_Msk = 0x1000000 + // Bit CORE_0_DRAM0_RECORDING_WR_1. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1 = 0x1000000 + // Position of CORE_0_DRAM0_RECORDING_BYTEEN_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1_Pos = 0x19 + // Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1_Msk = 0x1e000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_3: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG + // Position of CORE_0_DRAM0_RECORDING_PC_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_PC_1_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_PC_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_PC_1_Msk = 0xffffffff + + // CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG + // Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Msk = 0xfffff + + // CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG + // Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Msk = 0xfffff + + // LOG_SETTING: ASSIST_DEBUG_LOG_SETTING + // Position of LOG_ENA field. + ASSIST_DEBUG_LOG_SETTING_LOG_ENA_Pos = 0x0 + // Bit mask of LOG_ENA field. + ASSIST_DEBUG_LOG_SETTING_LOG_ENA_Msk = 0x7 + // Position of LOG_MODE field. + ASSIST_DEBUG_LOG_SETTING_LOG_MODE_Pos = 0x3 + // Bit mask of LOG_MODE field. + ASSIST_DEBUG_LOG_SETTING_LOG_MODE_Msk = 0x78 + // Position of LOG_MEM_LOOP_ENABLE field. + ASSIST_DEBUG_LOG_SETTING_LOG_MEM_LOOP_ENABLE_Pos = 0x7 + // Bit mask of LOG_MEM_LOOP_ENABLE field. + ASSIST_DEBUG_LOG_SETTING_LOG_MEM_LOOP_ENABLE_Msk = 0x80 + // Bit LOG_MEM_LOOP_ENABLE. + ASSIST_DEBUG_LOG_SETTING_LOG_MEM_LOOP_ENABLE = 0x80 + + // LOG_DATA_0: ASSIST_DEBUG_LOG_DATA_0_REG + // Position of LOG_DATA_0 field. + ASSIST_DEBUG_LOG_DATA_0_LOG_DATA_0_Pos = 0x0 + // Bit mask of LOG_DATA_0 field. + ASSIST_DEBUG_LOG_DATA_0_LOG_DATA_0_Msk = 0xffffffff + + // LOG_DATA_MASK: ASSIST_DEBUG_LOG_DATA_MASK_REG + // Position of LOG_DATA_SIZE field. + ASSIST_DEBUG_LOG_DATA_MASK_LOG_DATA_SIZE_Pos = 0x0 + // Bit mask of LOG_DATA_SIZE field. + ASSIST_DEBUG_LOG_DATA_MASK_LOG_DATA_SIZE_Msk = 0xffff + + // LOG_MIN: ASSIST_DEBUG_LOG_MIN_REG + // Position of LOG_MIN field. + ASSIST_DEBUG_LOG_MIN_LOG_MIN_Pos = 0x0 + // Bit mask of LOG_MIN field. + ASSIST_DEBUG_LOG_MIN_LOG_MIN_Msk = 0xffffffff + + // LOG_MAX: ASSIST_DEBUG_LOG_MAX_REG + // Position of LOG_MAX field. + ASSIST_DEBUG_LOG_MAX_LOG_MAX_Pos = 0x0 + // Bit mask of LOG_MAX field. + ASSIST_DEBUG_LOG_MAX_LOG_MAX_Msk = 0xffffffff + + // LOG_MEM_START: ASSIST_DEBUG_LOG_MEM_START_REG + // Position of LOG_MEM_START field. + ASSIST_DEBUG_LOG_MEM_START_LOG_MEM_START_Pos = 0x0 + // Bit mask of LOG_MEM_START field. + ASSIST_DEBUG_LOG_MEM_START_LOG_MEM_START_Msk = 0xffffffff + + // LOG_MEM_END: ASSIST_DEBUG_LOG_MEM_END_REG + // Position of LOG_MEM_END field. + ASSIST_DEBUG_LOG_MEM_END_LOG_MEM_END_Pos = 0x0 + // Bit mask of LOG_MEM_END field. + ASSIST_DEBUG_LOG_MEM_END_LOG_MEM_END_Msk = 0xffffffff + + // LOG_MEM_WRITING_ADDR: ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG + // Position of LOG_MEM_WRITING_ADDR field. + ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_LOG_MEM_WRITING_ADDR_Pos = 0x0 + // Bit mask of LOG_MEM_WRITING_ADDR field. + ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_LOG_MEM_WRITING_ADDR_Msk = 0xffffffff + + // LOG_MEM_FULL_FLAG: ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG + // Position of LOG_MEM_FULL_FLAG field. + ASSIST_DEBUG_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG_Pos = 0x0 + // Bit mask of LOG_MEM_FULL_FLAG field. + ASSIST_DEBUG_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG_Msk = 0x1 + // Bit LOG_MEM_FULL_FLAG. + ASSIST_DEBUG_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG = 0x1 + // Position of CLR_LOG_MEM_FULL_FLAG field. + ASSIST_DEBUG_LOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG_Pos = 0x1 + // Bit mask of CLR_LOG_MEM_FULL_FLAG field. + ASSIST_DEBUG_LOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG_Msk = 0x2 + // Bit CLR_LOG_MEM_FULL_FLAG. + ASSIST_DEBUG_LOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG = 0x2 + + // C0RE_0_LASTPC_BEFORE_EXCEPTION: ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION + // Position of CORE_0_LASTPC_BEFORE_EXC field. + ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Pos = 0x0 + // Bit mask of CORE_0_LASTPC_BEFORE_EXC field. + ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Msk = 0xffffffff + + // C0RE_0_DEBUG_MODE: ASSIST_DEBUG_C0RE_0_DEBUG_MODE + // Position of CORE_0_DEBUG_MODE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Pos = 0x0 + // Bit mask of CORE_0_DEBUG_MODE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Msk = 0x1 + // Bit CORE_0_DEBUG_MODE. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE = 0x1 + // Position of CORE_0_DEBUG_MODULE_ACTIVE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Pos = 0x1 + // Bit mask of CORE_0_DEBUG_MODULE_ACTIVE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Msk = 0x2 + // Bit CORE_0_DEBUG_MODULE_ACTIVE. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE = 0x2 + + // DATE: ASSIST_DEBUG_DATE_REG + // Position of ASSIST_DEBUG_DATE field. + ASSIST_DEBUG_DATE_ASSIST_DEBUG_DATE_Pos = 0x0 + // Bit mask of ASSIST_DEBUG_DATE field. + ASSIST_DEBUG_DATE_ASSIST_DEBUG_DATE_Msk = 0xfffffff +) + +// Constants for BB: BB Peripheral +const ( + // BBPD_CTRL: Baseband control register + // Position of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Pos = 0x0 + // Bit mask of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Msk = 0x1 + // Bit DC_EST_FORCE_PD. + BB_BBPD_CTRL_DC_EST_FORCE_PD = 0x1 + // Position of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Pos = 0x1 + // Bit mask of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Msk = 0x2 + // Bit DC_EST_FORCE_PU. + BB_BBPD_CTRL_DC_EST_FORCE_PU = 0x2 + // Position of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Pos = 0x2 + // Bit mask of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Msk = 0x4 + // Bit FFT_FORCE_PD. + BB_BBPD_CTRL_FFT_FORCE_PD = 0x4 + // Position of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Pos = 0x3 + // Bit mask of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Msk = 0x8 + // Bit FFT_FORCE_PU. + BB_BBPD_CTRL_FFT_FORCE_PU = 0x8 +) + +// Constants for DMA: DMA (Direct Memory Access) Controller +const ( + // INT_RAW_CH0: DMA_INT_RAW_CH0_REG. + // Position of IN_DONE field. + DMA_INT_RAW_CH0_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_RAW_CH0_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_RAW_CH0_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_RAW_CH0_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_RAW_CH0_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_RAW_CH0_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_RAW_CH0_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_RAW_CH0_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_RAW_CH0_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_RAW_CH0_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_RAW_CH0_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_RAW_CH0_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_RAW_CH0_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_RAW_CH0_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_RAW_CH0_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_RAW_CH0_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_RAW_CH0_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_RAW_CH0_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_RAW_CH0_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_RAW_CH0_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_RAW_CH0_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_RAW_CH0_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_RAW_CH0_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_RAW_CH0_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_RAW_CH0_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_RAW_CH0_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_RAW_CH0_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_RAW_CH0_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_RAW_CH0_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_RAW_CH0_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_RAW_CH0_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_RAW_CH0_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_RAW_CH0_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_RAW_CH0_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_RAW_CH0_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_RAW_CH0_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_RAW_CH0_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_RAW_CH0_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_RAW_CH0_OUTFIFO_UDF = 0x1000 + + // INT_ST_CH0: DMA_INT_ST_CH0_REG. + // Position of IN_DONE field. + DMA_INT_ST_CH0_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_ST_CH0_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_ST_CH0_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_ST_CH0_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_ST_CH0_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_ST_CH0_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_ST_CH0_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_ST_CH0_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_ST_CH0_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_ST_CH0_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_ST_CH0_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_ST_CH0_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_ST_CH0_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_ST_CH0_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_ST_CH0_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_ST_CH0_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_ST_CH0_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_ST_CH0_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_ST_CH0_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_ST_CH0_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_ST_CH0_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_ST_CH0_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_ST_CH0_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_ST_CH0_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_ST_CH0_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_ST_CH0_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_ST_CH0_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_ST_CH0_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_ST_CH0_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_ST_CH0_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_ST_CH0_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_ST_CH0_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_ST_CH0_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_ST_CH0_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_ST_CH0_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_ST_CH0_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_ST_CH0_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_ST_CH0_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_ST_CH0_OUTFIFO_UDF = 0x1000 + + // INT_ENA_CH0: DMA_INT_ENA_CH0_REG. + // Position of IN_DONE field. + DMA_INT_ENA_CH0_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_ENA_CH0_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_ENA_CH0_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_ENA_CH0_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_ENA_CH0_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_ENA_CH0_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_ENA_CH0_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_ENA_CH0_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_ENA_CH0_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_ENA_CH0_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_ENA_CH0_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_ENA_CH0_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_ENA_CH0_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_ENA_CH0_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_ENA_CH0_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_ENA_CH0_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_ENA_CH0_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_ENA_CH0_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_ENA_CH0_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_ENA_CH0_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_ENA_CH0_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_ENA_CH0_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_ENA_CH0_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_ENA_CH0_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_ENA_CH0_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_ENA_CH0_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_ENA_CH0_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_ENA_CH0_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_ENA_CH0_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_ENA_CH0_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_ENA_CH0_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_ENA_CH0_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_ENA_CH0_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_ENA_CH0_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_ENA_CH0_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_ENA_CH0_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_ENA_CH0_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_ENA_CH0_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_ENA_CH0_OUTFIFO_UDF = 0x1000 + + // INT_CLR_CH0: DMA_INT_CLR_CH0_REG. + // Position of IN_DONE field. + DMA_INT_CLR_CH0_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_CLR_CH0_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_CLR_CH0_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_CLR_CH0_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_CLR_CH0_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_CLR_CH0_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_CLR_CH0_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_CLR_CH0_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_CLR_CH0_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_CLR_CH0_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_CLR_CH0_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_CLR_CH0_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_CLR_CH0_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_CLR_CH0_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_CLR_CH0_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_CLR_CH0_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_CLR_CH0_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_CLR_CH0_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_CLR_CH0_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_CLR_CH0_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_CLR_CH0_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_CLR_CH0_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_CLR_CH0_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_CLR_CH0_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_CLR_CH0_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_CLR_CH0_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_CLR_CH0_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_CLR_CH0_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_CLR_CH0_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_CLR_CH0_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_CLR_CH0_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_CLR_CH0_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_CLR_CH0_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_CLR_CH0_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_CLR_CH0_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_CLR_CH0_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_CLR_CH0_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_CLR_CH0_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_CLR_CH0_OUTFIFO_UDF = 0x1000 + + // INT_RAW_CH1: DMA_INT_RAW_CH1_REG. + // Position of IN_DONE field. + DMA_INT_RAW_CH1_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_RAW_CH1_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_RAW_CH1_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_RAW_CH1_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_RAW_CH1_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_RAW_CH1_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_RAW_CH1_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_RAW_CH1_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_RAW_CH1_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_RAW_CH1_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_RAW_CH1_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_RAW_CH1_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_RAW_CH1_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_RAW_CH1_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_RAW_CH1_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_RAW_CH1_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_RAW_CH1_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_RAW_CH1_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_RAW_CH1_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_RAW_CH1_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_RAW_CH1_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_RAW_CH1_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_RAW_CH1_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_RAW_CH1_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_RAW_CH1_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_RAW_CH1_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_RAW_CH1_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_RAW_CH1_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_RAW_CH1_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_RAW_CH1_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_RAW_CH1_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_RAW_CH1_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_RAW_CH1_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_RAW_CH1_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_RAW_CH1_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_RAW_CH1_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_RAW_CH1_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_RAW_CH1_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_RAW_CH1_OUTFIFO_UDF = 0x1000 + + // INT_ST_CH1: DMA_INT_ST_CH1_REG. + // Position of IN_DONE field. + DMA_INT_ST_CH1_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_ST_CH1_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_ST_CH1_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_ST_CH1_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_ST_CH1_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_ST_CH1_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_ST_CH1_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_ST_CH1_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_ST_CH1_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_ST_CH1_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_ST_CH1_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_ST_CH1_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_ST_CH1_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_ST_CH1_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_ST_CH1_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_ST_CH1_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_ST_CH1_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_ST_CH1_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_ST_CH1_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_ST_CH1_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_ST_CH1_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_ST_CH1_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_ST_CH1_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_ST_CH1_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_ST_CH1_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_ST_CH1_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_ST_CH1_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_ST_CH1_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_ST_CH1_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_ST_CH1_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_ST_CH1_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_ST_CH1_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_ST_CH1_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_ST_CH1_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_ST_CH1_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_ST_CH1_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_ST_CH1_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_ST_CH1_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_ST_CH1_OUTFIFO_UDF = 0x1000 + + // INT_ENA_CH1: DMA_INT_ENA_CH1_REG. + // Position of IN_DONE field. + DMA_INT_ENA_CH1_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_ENA_CH1_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_ENA_CH1_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_ENA_CH1_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_ENA_CH1_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_ENA_CH1_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_ENA_CH1_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_ENA_CH1_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_ENA_CH1_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_ENA_CH1_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_ENA_CH1_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_ENA_CH1_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_ENA_CH1_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_ENA_CH1_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_ENA_CH1_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_ENA_CH1_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_ENA_CH1_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_ENA_CH1_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_ENA_CH1_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_ENA_CH1_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_ENA_CH1_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_ENA_CH1_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_ENA_CH1_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_ENA_CH1_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_ENA_CH1_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_ENA_CH1_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_ENA_CH1_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_ENA_CH1_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_ENA_CH1_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_ENA_CH1_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_ENA_CH1_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_ENA_CH1_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_ENA_CH1_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_ENA_CH1_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_ENA_CH1_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_ENA_CH1_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_ENA_CH1_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_ENA_CH1_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_ENA_CH1_OUTFIFO_UDF = 0x1000 + + // INT_CLR_CH1: DMA_INT_CLR_CH1_REG. + // Position of IN_DONE field. + DMA_INT_CLR_CH1_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_CLR_CH1_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_CLR_CH1_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_CLR_CH1_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_CLR_CH1_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_CLR_CH1_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_CLR_CH1_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_CLR_CH1_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_CLR_CH1_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_CLR_CH1_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_CLR_CH1_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_CLR_CH1_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_CLR_CH1_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_CLR_CH1_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_CLR_CH1_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_CLR_CH1_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_CLR_CH1_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_CLR_CH1_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_CLR_CH1_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_CLR_CH1_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_CLR_CH1_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_CLR_CH1_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_CLR_CH1_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_CLR_CH1_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_CLR_CH1_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_CLR_CH1_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_CLR_CH1_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_CLR_CH1_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_CLR_CH1_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_CLR_CH1_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_CLR_CH1_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_CLR_CH1_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_CLR_CH1_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_CLR_CH1_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_CLR_CH1_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_CLR_CH1_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_CLR_CH1_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_CLR_CH1_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_CLR_CH1_OUTFIFO_UDF = 0x1000 + + // INT_RAW_CH2: DMA_INT_RAW_CH2_REG. + // Position of IN_DONE field. + DMA_INT_RAW_CH2_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_RAW_CH2_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_RAW_CH2_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_RAW_CH2_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_RAW_CH2_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_RAW_CH2_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_RAW_CH2_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_RAW_CH2_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_RAW_CH2_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_RAW_CH2_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_RAW_CH2_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_RAW_CH2_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_RAW_CH2_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_RAW_CH2_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_RAW_CH2_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_RAW_CH2_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_RAW_CH2_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_RAW_CH2_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_RAW_CH2_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_RAW_CH2_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_RAW_CH2_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_RAW_CH2_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_RAW_CH2_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_RAW_CH2_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_RAW_CH2_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_RAW_CH2_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_RAW_CH2_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_RAW_CH2_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_RAW_CH2_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_RAW_CH2_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_RAW_CH2_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_RAW_CH2_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_RAW_CH2_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_RAW_CH2_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_RAW_CH2_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_RAW_CH2_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_RAW_CH2_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_RAW_CH2_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_RAW_CH2_OUTFIFO_UDF = 0x1000 + + // INT_ST_CH2: DMA_INT_ST_CH2_REG. + // Position of IN_DONE field. + DMA_INT_ST_CH2_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_ST_CH2_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_ST_CH2_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_ST_CH2_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_ST_CH2_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_ST_CH2_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_ST_CH2_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_ST_CH2_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_ST_CH2_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_ST_CH2_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_ST_CH2_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_ST_CH2_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_ST_CH2_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_ST_CH2_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_ST_CH2_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_ST_CH2_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_ST_CH2_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_ST_CH2_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_ST_CH2_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_ST_CH2_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_ST_CH2_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_ST_CH2_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_ST_CH2_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_ST_CH2_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_ST_CH2_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_ST_CH2_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_ST_CH2_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_ST_CH2_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_ST_CH2_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_ST_CH2_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_ST_CH2_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_ST_CH2_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_ST_CH2_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_ST_CH2_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_ST_CH2_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_ST_CH2_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_ST_CH2_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_ST_CH2_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_ST_CH2_OUTFIFO_UDF = 0x1000 + + // INT_ENA_CH2: DMA_INT_ENA_CH2_REG. + // Position of IN_DONE field. + DMA_INT_ENA_CH2_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_ENA_CH2_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_ENA_CH2_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_ENA_CH2_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_ENA_CH2_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_ENA_CH2_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_ENA_CH2_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_ENA_CH2_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_ENA_CH2_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_ENA_CH2_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_ENA_CH2_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_ENA_CH2_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_ENA_CH2_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_ENA_CH2_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_ENA_CH2_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_ENA_CH2_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_ENA_CH2_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_ENA_CH2_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_ENA_CH2_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_ENA_CH2_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_ENA_CH2_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_ENA_CH2_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_ENA_CH2_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_ENA_CH2_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_ENA_CH2_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_ENA_CH2_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_ENA_CH2_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_ENA_CH2_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_ENA_CH2_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_ENA_CH2_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_ENA_CH2_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_ENA_CH2_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_ENA_CH2_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_ENA_CH2_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_ENA_CH2_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_ENA_CH2_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_ENA_CH2_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_ENA_CH2_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_ENA_CH2_OUTFIFO_UDF = 0x1000 + + // INT_CLR_CH2: DMA_INT_CLR_CH2_REG. + // Position of IN_DONE field. + DMA_INT_CLR_CH2_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_INT_CLR_CH2_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_INT_CLR_CH2_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_INT_CLR_CH2_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_INT_CLR_CH2_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_INT_CLR_CH2_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_INT_CLR_CH2_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_INT_CLR_CH2_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_INT_CLR_CH2_IN_ERR_EOF = 0x4 + // Position of OUT_DONE field. + DMA_INT_CLR_CH2_OUT_DONE_Pos = 0x3 + // Bit mask of OUT_DONE field. + DMA_INT_CLR_CH2_OUT_DONE_Msk = 0x8 + // Bit OUT_DONE. + DMA_INT_CLR_CH2_OUT_DONE = 0x8 + // Position of OUT_EOF field. + DMA_INT_CLR_CH2_OUT_EOF_Pos = 0x4 + // Bit mask of OUT_EOF field. + DMA_INT_CLR_CH2_OUT_EOF_Msk = 0x10 + // Bit OUT_EOF. + DMA_INT_CLR_CH2_OUT_EOF = 0x10 + // Position of IN_DSCR_ERR field. + DMA_INT_CLR_CH2_IN_DSCR_ERR_Pos = 0x5 + // Bit mask of IN_DSCR_ERR field. + DMA_INT_CLR_CH2_IN_DSCR_ERR_Msk = 0x20 + // Bit IN_DSCR_ERR. + DMA_INT_CLR_CH2_IN_DSCR_ERR = 0x20 + // Position of OUT_DSCR_ERR field. + DMA_INT_CLR_CH2_OUT_DSCR_ERR_Pos = 0x6 + // Bit mask of OUT_DSCR_ERR field. + DMA_INT_CLR_CH2_OUT_DSCR_ERR_Msk = 0x40 + // Bit OUT_DSCR_ERR. + DMA_INT_CLR_CH2_OUT_DSCR_ERR = 0x40 + // Position of IN_DSCR_EMPTY field. + DMA_INT_CLR_CH2_IN_DSCR_EMPTY_Pos = 0x7 + // Bit mask of IN_DSCR_EMPTY field. + DMA_INT_CLR_CH2_IN_DSCR_EMPTY_Msk = 0x80 + // Bit IN_DSCR_EMPTY. + DMA_INT_CLR_CH2_IN_DSCR_EMPTY = 0x80 + // Position of OUT_TOTAL_EOF field. + DMA_INT_CLR_CH2_OUT_TOTAL_EOF_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF field. + DMA_INT_CLR_CH2_OUT_TOTAL_EOF_Msk = 0x100 + // Bit OUT_TOTAL_EOF. + DMA_INT_CLR_CH2_OUT_TOTAL_EOF = 0x100 + // Position of INFIFO_OVF field. + DMA_INT_CLR_CH2_INFIFO_OVF_Pos = 0x9 + // Bit mask of INFIFO_OVF field. + DMA_INT_CLR_CH2_INFIFO_OVF_Msk = 0x200 + // Bit INFIFO_OVF. + DMA_INT_CLR_CH2_INFIFO_OVF = 0x200 + // Position of INFIFO_UDF field. + DMA_INT_CLR_CH2_INFIFO_UDF_Pos = 0xa + // Bit mask of INFIFO_UDF field. + DMA_INT_CLR_CH2_INFIFO_UDF_Msk = 0x400 + // Bit INFIFO_UDF. + DMA_INT_CLR_CH2_INFIFO_UDF = 0x400 + // Position of OUTFIFO_OVF field. + DMA_INT_CLR_CH2_OUTFIFO_OVF_Pos = 0xb + // Bit mask of OUTFIFO_OVF field. + DMA_INT_CLR_CH2_OUTFIFO_OVF_Msk = 0x800 + // Bit OUTFIFO_OVF. + DMA_INT_CLR_CH2_OUTFIFO_OVF = 0x800 + // Position of OUTFIFO_UDF field. + DMA_INT_CLR_CH2_OUTFIFO_UDF_Pos = 0xc + // Bit mask of OUTFIFO_UDF field. + DMA_INT_CLR_CH2_OUTFIFO_UDF_Msk = 0x1000 + // Bit OUTFIFO_UDF. + DMA_INT_CLR_CH2_OUTFIFO_UDF = 0x1000 + + // AHB_TEST: DMA_AHB_TEST_REG. + // Position of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // MISC_CONF: DMA_MISC_CONF_REG. + // Position of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Pos = 0x0 + // Bit mask of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Msk = 0x1 + // Bit AHBM_RST_INTER. + DMA_MISC_CONF_AHBM_RST_INTER = 0x1 + // Position of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Pos = 0x2 + // Bit mask of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Msk = 0x4 + // Bit ARB_PRI_DIS. + DMA_MISC_CONF_ARB_PRI_DIS = 0x4 + // Position of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Pos = 0x3 + // Bit mask of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Msk = 0x8 + // Bit CLK_EN. + DMA_MISC_CONF_CLK_EN = 0x8 + + // DATE: DMA_DATE_REG. + // Position of DATE field. + DMA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DMA_DATE_DATE_Msk = 0xffffffff + + // IN_CONF0_CH0: DMA_IN_CONF0_CH0_REG. + // Position of IN_RST field. + DMA_IN_CONF0_CH0_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + DMA_IN_CONF0_CH0_IN_RST_Msk = 0x1 + // Bit IN_RST. + DMA_IN_CONF0_CH0_IN_RST = 0x1 + // Position of IN_LOOP_TEST field. + DMA_IN_CONF0_CH0_IN_LOOP_TEST_Pos = 0x1 + // Bit mask of IN_LOOP_TEST field. + DMA_IN_CONF0_CH0_IN_LOOP_TEST_Msk = 0x2 + // Bit IN_LOOP_TEST. + DMA_IN_CONF0_CH0_IN_LOOP_TEST = 0x2 + // Position of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH0_INDSCR_BURST_EN_Pos = 0x2 + // Bit mask of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH0_INDSCR_BURST_EN_Msk = 0x4 + // Bit INDSCR_BURST_EN. + DMA_IN_CONF0_CH0_INDSCR_BURST_EN = 0x4 + // Position of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH0_IN_DATA_BURST_EN_Pos = 0x3 + // Bit mask of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH0_IN_DATA_BURST_EN_Msk = 0x8 + // Bit IN_DATA_BURST_EN. + DMA_IN_CONF0_CH0_IN_DATA_BURST_EN = 0x8 + // Position of MEM_TRANS_EN field. + DMA_IN_CONF0_CH0_MEM_TRANS_EN_Pos = 0x4 + // Bit mask of MEM_TRANS_EN field. + DMA_IN_CONF0_CH0_MEM_TRANS_EN_Msk = 0x10 + // Bit MEM_TRANS_EN. + DMA_IN_CONF0_CH0_MEM_TRANS_EN = 0x10 + + // IN_CONF1_CH0: DMA_IN_CONF1_CH0_REG. + // Position of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH0_IN_CHECK_OWNER_Pos = 0xc + // Bit mask of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH0_IN_CHECK_OWNER_Msk = 0x1000 + // Bit IN_CHECK_OWNER. + DMA_IN_CONF1_CH0_IN_CHECK_OWNER = 0x1000 + + // INFIFO_STATUS_CH0: DMA_INFIFO_STATUS_CH0_REG. + // Position of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH0_INFIFO_FULL_Pos = 0x0 + // Bit mask of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH0_INFIFO_FULL_Msk = 0x1 + // Bit INFIFO_FULL. + DMA_INFIFO_STATUS_CH0_INFIFO_FULL = 0x1 + // Position of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_Pos = 0x1 + // Bit mask of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_Msk = 0x2 + // Bit INFIFO_EMPTY. + DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY = 0x2 + // Position of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH0_INFIFO_CNT_Pos = 0x2 + // Bit mask of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH0_INFIFO_CNT_Msk = 0xfc + // Position of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit IN_REMAIN_UNDER_1B. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B = 0x800000 + // Position of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit IN_REMAIN_UNDER_2B. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B = 0x1000000 + // Position of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit IN_REMAIN_UNDER_3B. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B = 0x2000000 + // Position of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit IN_REMAIN_UNDER_4B. + DMA_INFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B = 0x4000000 + // Position of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH0_IN_BUF_HUNGRY_Pos = 0x1b + // Bit mask of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH0_IN_BUF_HUNGRY_Msk = 0x8000000 + // Bit IN_BUF_HUNGRY. + DMA_INFIFO_STATUS_CH0_IN_BUF_HUNGRY = 0x8000000 + + // IN_POP_CH0: DMA_IN_POP_CH0_REG. + // Position of INFIFO_RDATA field. + DMA_IN_POP_CH0_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + DMA_IN_POP_CH0_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + DMA_IN_POP_CH0_INFIFO_POP_Pos = 0xc + // Bit mask of INFIFO_POP field. + DMA_IN_POP_CH0_INFIFO_POP_Msk = 0x1000 + // Bit INFIFO_POP. + DMA_IN_POP_CH0_INFIFO_POP = 0x1000 + + // IN_LINK_CH0: DMA_IN_LINK_CH0_REG. + // Position of INLINK_ADDR field. + DMA_IN_LINK_CH0_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + DMA_IN_LINK_CH0_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + DMA_IN_LINK_CH0_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + DMA_IN_LINK_CH0_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + DMA_IN_LINK_CH0_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + DMA_IN_LINK_CH0_INLINK_STOP_Pos = 0x15 + // Bit mask of INLINK_STOP field. + DMA_IN_LINK_CH0_INLINK_STOP_Msk = 0x200000 + // Bit INLINK_STOP. + DMA_IN_LINK_CH0_INLINK_STOP = 0x200000 + // Position of INLINK_START field. + DMA_IN_LINK_CH0_INLINK_START_Pos = 0x16 + // Bit mask of INLINK_START field. + DMA_IN_LINK_CH0_INLINK_START_Msk = 0x400000 + // Bit INLINK_START. + DMA_IN_LINK_CH0_INLINK_START = 0x400000 + // Position of INLINK_RESTART field. + DMA_IN_LINK_CH0_INLINK_RESTART_Pos = 0x17 + // Bit mask of INLINK_RESTART field. + DMA_IN_LINK_CH0_INLINK_RESTART_Msk = 0x800000 + // Bit INLINK_RESTART. + DMA_IN_LINK_CH0_INLINK_RESTART = 0x800000 + // Position of INLINK_PARK field. + DMA_IN_LINK_CH0_INLINK_PARK_Pos = 0x18 + // Bit mask of INLINK_PARK field. + DMA_IN_LINK_CH0_INLINK_PARK_Msk = 0x1000000 + // Bit INLINK_PARK. + DMA_IN_LINK_CH0_INLINK_PARK = 0x1000000 + + // IN_STATE_CH0: DMA_IN_STATE_CH0_REG. + // Position of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH0_INLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH0_INLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of IN_DSCR_STATE field. + DMA_IN_STATE_CH0_IN_DSCR_STATE_Pos = 0x12 + // Bit mask of IN_DSCR_STATE field. + DMA_IN_STATE_CH0_IN_DSCR_STATE_Msk = 0xc0000 + // Position of IN_STATE field. + DMA_IN_STATE_CH0_IN_STATE_Pos = 0x14 + // Bit mask of IN_STATE field. + DMA_IN_STATE_CH0_IN_STATE_Msk = 0x700000 + + // IN_SUC_EOF_DES_ADDR_CH0: DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. + // Position of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH0_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH0_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_ERR_EOF_DES_ADDR_CH0: DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. + // Position of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH0_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH0_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_DSCR_CH0: DMA_IN_DSCR_CH0_REG. + // Position of INLINK_DSCR field. + DMA_IN_DSCR_CH0_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + DMA_IN_DSCR_CH0_INLINK_DSCR_Msk = 0xffffffff + + // IN_DSCR_BF0_CH0: DMA_IN_DSCR_BF0_CH0_REG. + // Position of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH0_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH0_INLINK_DSCR_BF0_Msk = 0xffffffff + + // IN_DSCR_BF1_CH0: DMA_IN_DSCR_BF1_CH0_REG. + // Position of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH0_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH0_INLINK_DSCR_BF1_Msk = 0xffffffff + + // IN_PRI_CH0: DMA_IN_PRI_CH0_REG. + // Position of RX_PRI field. + DMA_IN_PRI_CH0_RX_PRI_Pos = 0x0 + // Bit mask of RX_PRI field. + DMA_IN_PRI_CH0_RX_PRI_Msk = 0xf + + // IN_PERI_SEL_CH0: DMA_IN_PERI_SEL_CH0_REG. + // Position of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH0_PERI_IN_SEL_Pos = 0x0 + // Bit mask of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH0_PERI_IN_SEL_Msk = 0x3f + + // OUT_CONF0_CH0: DMA_OUT_CONF0_CH0_REG. + // Position of OUT_RST field. + DMA_OUT_CONF0_CH0_OUT_RST_Pos = 0x0 + // Bit mask of OUT_RST field. + DMA_OUT_CONF0_CH0_OUT_RST_Msk = 0x1 + // Bit OUT_RST. + DMA_OUT_CONF0_CH0_OUT_RST = 0x1 + // Position of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_Pos = 0x1 + // Bit mask of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_Msk = 0x2 + // Bit OUT_LOOP_TEST. + DMA_OUT_CONF0_CH0_OUT_LOOP_TEST = 0x2 + // Position of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_Pos = 0x2 + // Bit mask of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_Msk = 0x4 + // Bit OUT_AUTO_WRBACK. + DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK = 0x4 + // Position of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH0_OUT_EOF_MODE_Pos = 0x3 + // Bit mask of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH0_OUT_EOF_MODE_Msk = 0x8 + // Bit OUT_EOF_MODE. + DMA_OUT_CONF0_CH0_OUT_EOF_MODE = 0x8 + // Position of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_Pos = 0x4 + // Bit mask of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_Msk = 0x10 + // Bit OUTDSCR_BURST_EN. + DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN = 0x10 + // Position of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_Pos = 0x5 + // Bit mask of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_Msk = 0x20 + // Bit OUT_DATA_BURST_EN. + DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN = 0x20 + + // OUT_CONF1_CH0: DMA_OUT_CONF1_CH0_REG. + // Position of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH0_OUT_CHECK_OWNER_Pos = 0xc + // Bit mask of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH0_OUT_CHECK_OWNER_Msk = 0x1000 + // Bit OUT_CHECK_OWNER. + DMA_OUT_CONF1_CH0_OUT_CHECK_OWNER = 0x1000 + + // OUTFIFO_STATUS_CH0: DMA_OUTFIFO_STATUS_CH0_REG. + // Position of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_Pos = 0x0 + // Bit mask of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_Msk = 0x1 + // Bit OUTFIFO_FULL. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL = 0x1 + // Position of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_Pos = 0x1 + // Bit mask of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_Msk = 0x2 + // Bit OUTFIFO_EMPTY. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY = 0x2 + // Position of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_Pos = 0x2 + // Bit mask of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_Msk = 0xfc + // Position of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit OUT_REMAIN_UNDER_1B. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B = 0x800000 + // Position of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit OUT_REMAIN_UNDER_2B. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B = 0x1000000 + // Position of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit OUT_REMAIN_UNDER_3B. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B = 0x2000000 + // Position of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit OUT_REMAIN_UNDER_4B. + DMA_OUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B = 0x4000000 + + // OUT_PUSH_CH0: DMA_OUT_PUSH_CH0_REG. + // Position of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH0_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH0_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH0_OUTFIFO_PUSH_Pos = 0x9 + // Bit mask of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH0_OUTFIFO_PUSH_Msk = 0x200 + // Bit OUTFIFO_PUSH. + DMA_OUT_PUSH_CH0_OUTFIFO_PUSH = 0x200 + + // OUT_LINK_CH0: DMA_OUT_LINK_CH0_REG. + // Position of OUTLINK_ADDR field. + DMA_OUT_LINK_CH0_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + DMA_OUT_LINK_CH0_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + DMA_OUT_LINK_CH0_OUTLINK_STOP_Pos = 0x14 + // Bit mask of OUTLINK_STOP field. + DMA_OUT_LINK_CH0_OUTLINK_STOP_Msk = 0x100000 + // Bit OUTLINK_STOP. + DMA_OUT_LINK_CH0_OUTLINK_STOP = 0x100000 + // Position of OUTLINK_START field. + DMA_OUT_LINK_CH0_OUTLINK_START_Pos = 0x15 + // Bit mask of OUTLINK_START field. + DMA_OUT_LINK_CH0_OUTLINK_START_Msk = 0x200000 + // Bit OUTLINK_START. + DMA_OUT_LINK_CH0_OUTLINK_START = 0x200000 + // Position of OUTLINK_RESTART field. + DMA_OUT_LINK_CH0_OUTLINK_RESTART_Pos = 0x16 + // Bit mask of OUTLINK_RESTART field. + DMA_OUT_LINK_CH0_OUTLINK_RESTART_Msk = 0x400000 + // Bit OUTLINK_RESTART. + DMA_OUT_LINK_CH0_OUTLINK_RESTART = 0x400000 + // Position of OUTLINK_PARK field. + DMA_OUT_LINK_CH0_OUTLINK_PARK_Pos = 0x17 + // Bit mask of OUTLINK_PARK field. + DMA_OUT_LINK_CH0_OUTLINK_PARK_Msk = 0x800000 + // Bit OUTLINK_PARK. + DMA_OUT_LINK_CH0_OUTLINK_PARK = 0x800000 + + // OUT_STATE_CH0: DMA_OUT_STATE_CH0_REG. + // Position of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH0_OUTLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH0_OUTLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH0_OUT_DSCR_STATE_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH0_OUT_DSCR_STATE_Msk = 0xc0000 + // Position of OUT_STATE field. + DMA_OUT_STATE_CH0_OUT_STATE_Pos = 0x14 + // Bit mask of OUT_STATE field. + DMA_OUT_STATE_CH0_OUT_STATE_Msk = 0x700000 + + // OUT_EOF_DES_ADDR_CH0: DMA_OUT_EOF_DES_ADDR_CH0_REG. + // Position of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH0_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH0_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR_CH0: DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. + // Position of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH0_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH0_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // OUT_DSCR_CH0: DMA_OUT_DSCR_CH0_REG. + // Position of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH0_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH0_OUTLINK_DSCR_Msk = 0xffffffff + + // OUT_DSCR_BF0_CH0: DMA_OUT_DSCR_BF0_CH0_REG. + // Position of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH0_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH0_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUT_DSCR_BF1_CH0: DMA_OUT_DSCR_BF1_CH0_REG. + // Position of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH0_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH0_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // OUT_PRI_CH0: DMA_OUT_PRI_CH0_REG. + // Position of TX_PRI field. + DMA_OUT_PRI_CH0_TX_PRI_Pos = 0x0 + // Bit mask of TX_PRI field. + DMA_OUT_PRI_CH0_TX_PRI_Msk = 0xf + + // OUT_PERI_SEL_CH0: DMA_OUT_PERI_SEL_CH0_REG. + // Position of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH0_PERI_OUT_SEL_Pos = 0x0 + // Bit mask of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH0_PERI_OUT_SEL_Msk = 0x3f + + // IN_CONF0_CH1: DMA_IN_CONF0_CH1_REG. + // Position of IN_RST field. + DMA_IN_CONF0_CH1_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + DMA_IN_CONF0_CH1_IN_RST_Msk = 0x1 + // Bit IN_RST. + DMA_IN_CONF0_CH1_IN_RST = 0x1 + // Position of IN_LOOP_TEST field. + DMA_IN_CONF0_CH1_IN_LOOP_TEST_Pos = 0x1 + // Bit mask of IN_LOOP_TEST field. + DMA_IN_CONF0_CH1_IN_LOOP_TEST_Msk = 0x2 + // Bit IN_LOOP_TEST. + DMA_IN_CONF0_CH1_IN_LOOP_TEST = 0x2 + // Position of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH1_INDSCR_BURST_EN_Pos = 0x2 + // Bit mask of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH1_INDSCR_BURST_EN_Msk = 0x4 + // Bit INDSCR_BURST_EN. + DMA_IN_CONF0_CH1_INDSCR_BURST_EN = 0x4 + // Position of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH1_IN_DATA_BURST_EN_Pos = 0x3 + // Bit mask of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH1_IN_DATA_BURST_EN_Msk = 0x8 + // Bit IN_DATA_BURST_EN. + DMA_IN_CONF0_CH1_IN_DATA_BURST_EN = 0x8 + // Position of MEM_TRANS_EN field. + DMA_IN_CONF0_CH1_MEM_TRANS_EN_Pos = 0x4 + // Bit mask of MEM_TRANS_EN field. + DMA_IN_CONF0_CH1_MEM_TRANS_EN_Msk = 0x10 + // Bit MEM_TRANS_EN. + DMA_IN_CONF0_CH1_MEM_TRANS_EN = 0x10 + + // IN_CONF1_CH1: DMA_IN_CONF1_CH1_REG. + // Position of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH1_IN_CHECK_OWNER_Pos = 0xc + // Bit mask of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH1_IN_CHECK_OWNER_Msk = 0x1000 + // Bit IN_CHECK_OWNER. + DMA_IN_CONF1_CH1_IN_CHECK_OWNER = 0x1000 + + // INFIFO_STATUS_CH1: DMA_INFIFO_STATUS_CH1_REG. + // Position of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH1_INFIFO_FULL_Pos = 0x0 + // Bit mask of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH1_INFIFO_FULL_Msk = 0x1 + // Bit INFIFO_FULL. + DMA_INFIFO_STATUS_CH1_INFIFO_FULL = 0x1 + // Position of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_Pos = 0x1 + // Bit mask of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_Msk = 0x2 + // Bit INFIFO_EMPTY. + DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY = 0x2 + // Position of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH1_INFIFO_CNT_Pos = 0x2 + // Bit mask of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH1_INFIFO_CNT_Msk = 0xfc + // Position of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit IN_REMAIN_UNDER_1B. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B = 0x800000 + // Position of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit IN_REMAIN_UNDER_2B. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B = 0x1000000 + // Position of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit IN_REMAIN_UNDER_3B. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B = 0x2000000 + // Position of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit IN_REMAIN_UNDER_4B. + DMA_INFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B = 0x4000000 + // Position of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH1_IN_BUF_HUNGRY_Pos = 0x1b + // Bit mask of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH1_IN_BUF_HUNGRY_Msk = 0x8000000 + // Bit IN_BUF_HUNGRY. + DMA_INFIFO_STATUS_CH1_IN_BUF_HUNGRY = 0x8000000 + + // IN_POP_CH1: DMA_IN_POP_CH1_REG. + // Position of INFIFO_RDATA field. + DMA_IN_POP_CH1_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + DMA_IN_POP_CH1_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + DMA_IN_POP_CH1_INFIFO_POP_Pos = 0xc + // Bit mask of INFIFO_POP field. + DMA_IN_POP_CH1_INFIFO_POP_Msk = 0x1000 + // Bit INFIFO_POP. + DMA_IN_POP_CH1_INFIFO_POP = 0x1000 + + // IN_LINK_CH1: DMA_IN_LINK_CH1_REG. + // Position of INLINK_ADDR field. + DMA_IN_LINK_CH1_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + DMA_IN_LINK_CH1_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + DMA_IN_LINK_CH1_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + DMA_IN_LINK_CH1_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + DMA_IN_LINK_CH1_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + DMA_IN_LINK_CH1_INLINK_STOP_Pos = 0x15 + // Bit mask of INLINK_STOP field. + DMA_IN_LINK_CH1_INLINK_STOP_Msk = 0x200000 + // Bit INLINK_STOP. + DMA_IN_LINK_CH1_INLINK_STOP = 0x200000 + // Position of INLINK_START field. + DMA_IN_LINK_CH1_INLINK_START_Pos = 0x16 + // Bit mask of INLINK_START field. + DMA_IN_LINK_CH1_INLINK_START_Msk = 0x400000 + // Bit INLINK_START. + DMA_IN_LINK_CH1_INLINK_START = 0x400000 + // Position of INLINK_RESTART field. + DMA_IN_LINK_CH1_INLINK_RESTART_Pos = 0x17 + // Bit mask of INLINK_RESTART field. + DMA_IN_LINK_CH1_INLINK_RESTART_Msk = 0x800000 + // Bit INLINK_RESTART. + DMA_IN_LINK_CH1_INLINK_RESTART = 0x800000 + // Position of INLINK_PARK field. + DMA_IN_LINK_CH1_INLINK_PARK_Pos = 0x18 + // Bit mask of INLINK_PARK field. + DMA_IN_LINK_CH1_INLINK_PARK_Msk = 0x1000000 + // Bit INLINK_PARK. + DMA_IN_LINK_CH1_INLINK_PARK = 0x1000000 + + // IN_STATE_CH1: DMA_IN_STATE_CH1_REG. + // Position of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH1_INLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH1_INLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of IN_DSCR_STATE field. + DMA_IN_STATE_CH1_IN_DSCR_STATE_Pos = 0x12 + // Bit mask of IN_DSCR_STATE field. + DMA_IN_STATE_CH1_IN_DSCR_STATE_Msk = 0xc0000 + // Position of IN_STATE field. + DMA_IN_STATE_CH1_IN_STATE_Pos = 0x14 + // Bit mask of IN_STATE field. + DMA_IN_STATE_CH1_IN_STATE_Msk = 0x700000 + + // IN_SUC_EOF_DES_ADDR_CH1: DMA_IN_SUC_EOF_DES_ADDR_CH1_REG. + // Position of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH1_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH1_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_ERR_EOF_DES_ADDR_CH1: DMA_IN_ERR_EOF_DES_ADDR_CH1_REG. + // Position of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH1_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH1_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_DSCR_CH1: DMA_IN_DSCR_CH1_REG. + // Position of INLINK_DSCR field. + DMA_IN_DSCR_CH1_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + DMA_IN_DSCR_CH1_INLINK_DSCR_Msk = 0xffffffff + + // IN_DSCR_BF0_CH1: DMA_IN_DSCR_BF0_CH1_REG. + // Position of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH1_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH1_INLINK_DSCR_BF0_Msk = 0xffffffff + + // IN_DSCR_BF1_CH1: DMA_IN_DSCR_BF1_CH1_REG. + // Position of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH1_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH1_INLINK_DSCR_BF1_Msk = 0xffffffff + + // IN_PRI_CH1: DMA_IN_PRI_CH1_REG. + // Position of RX_PRI field. + DMA_IN_PRI_CH1_RX_PRI_Pos = 0x0 + // Bit mask of RX_PRI field. + DMA_IN_PRI_CH1_RX_PRI_Msk = 0xf + + // IN_PERI_SEL_CH1: DMA_IN_PERI_SEL_CH1_REG. + // Position of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH1_PERI_IN_SEL_Pos = 0x0 + // Bit mask of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH1_PERI_IN_SEL_Msk = 0x3f + + // OUT_CONF0_CH1: DMA_OUT_CONF0_CH1_REG. + // Position of OUT_RST field. + DMA_OUT_CONF0_CH1_OUT_RST_Pos = 0x0 + // Bit mask of OUT_RST field. + DMA_OUT_CONF0_CH1_OUT_RST_Msk = 0x1 + // Bit OUT_RST. + DMA_OUT_CONF0_CH1_OUT_RST = 0x1 + // Position of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH1_OUT_LOOP_TEST_Pos = 0x1 + // Bit mask of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH1_OUT_LOOP_TEST_Msk = 0x2 + // Bit OUT_LOOP_TEST. + DMA_OUT_CONF0_CH1_OUT_LOOP_TEST = 0x2 + // Position of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH1_OUT_AUTO_WRBACK_Pos = 0x2 + // Bit mask of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH1_OUT_AUTO_WRBACK_Msk = 0x4 + // Bit OUT_AUTO_WRBACK. + DMA_OUT_CONF0_CH1_OUT_AUTO_WRBACK = 0x4 + // Position of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH1_OUT_EOF_MODE_Pos = 0x3 + // Bit mask of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH1_OUT_EOF_MODE_Msk = 0x8 + // Bit OUT_EOF_MODE. + DMA_OUT_CONF0_CH1_OUT_EOF_MODE = 0x8 + // Position of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH1_OUTDSCR_BURST_EN_Pos = 0x4 + // Bit mask of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH1_OUTDSCR_BURST_EN_Msk = 0x10 + // Bit OUTDSCR_BURST_EN. + DMA_OUT_CONF0_CH1_OUTDSCR_BURST_EN = 0x10 + // Position of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH1_OUT_DATA_BURST_EN_Pos = 0x5 + // Bit mask of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH1_OUT_DATA_BURST_EN_Msk = 0x20 + // Bit OUT_DATA_BURST_EN. + DMA_OUT_CONF0_CH1_OUT_DATA_BURST_EN = 0x20 + + // OUT_CONF1_CH1: DMA_OUT_CONF1_CH1_REG. + // Position of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH1_OUT_CHECK_OWNER_Pos = 0xc + // Bit mask of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH1_OUT_CHECK_OWNER_Msk = 0x1000 + // Bit OUT_CHECK_OWNER. + DMA_OUT_CONF1_CH1_OUT_CHECK_OWNER = 0x1000 + + // OUTFIFO_STATUS_CH1: DMA_OUTFIFO_STATUS_CH1_REG. + // Position of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_Pos = 0x0 + // Bit mask of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_Msk = 0x1 + // Bit OUTFIFO_FULL. + DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL = 0x1 + // Position of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_Pos = 0x1 + // Bit mask of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_Msk = 0x2 + // Bit OUTFIFO_EMPTY. + DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY = 0x2 + // Position of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH1_OUTFIFO_CNT_Pos = 0x2 + // Bit mask of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH1_OUTFIFO_CNT_Msk = 0xfc + // Position of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit OUT_REMAIN_UNDER_1B. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B = 0x800000 + // Position of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit OUT_REMAIN_UNDER_2B. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B = 0x1000000 + // Position of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit OUT_REMAIN_UNDER_3B. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B = 0x2000000 + // Position of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit OUT_REMAIN_UNDER_4B. + DMA_OUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B = 0x4000000 + + // OUT_PUSH_CH1: DMA_OUT_PUSH_CH1_REG. + // Position of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH1_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH1_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH1_OUTFIFO_PUSH_Pos = 0x9 + // Bit mask of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH1_OUTFIFO_PUSH_Msk = 0x200 + // Bit OUTFIFO_PUSH. + DMA_OUT_PUSH_CH1_OUTFIFO_PUSH = 0x200 + + // OUT_LINK_CH1: DMA_OUT_LINK_CH1_REG. + // Position of OUTLINK_ADDR field. + DMA_OUT_LINK_CH1_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + DMA_OUT_LINK_CH1_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + DMA_OUT_LINK_CH1_OUTLINK_STOP_Pos = 0x14 + // Bit mask of OUTLINK_STOP field. + DMA_OUT_LINK_CH1_OUTLINK_STOP_Msk = 0x100000 + // Bit OUTLINK_STOP. + DMA_OUT_LINK_CH1_OUTLINK_STOP = 0x100000 + // Position of OUTLINK_START field. + DMA_OUT_LINK_CH1_OUTLINK_START_Pos = 0x15 + // Bit mask of OUTLINK_START field. + DMA_OUT_LINK_CH1_OUTLINK_START_Msk = 0x200000 + // Bit OUTLINK_START. + DMA_OUT_LINK_CH1_OUTLINK_START = 0x200000 + // Position of OUTLINK_RESTART field. + DMA_OUT_LINK_CH1_OUTLINK_RESTART_Pos = 0x16 + // Bit mask of OUTLINK_RESTART field. + DMA_OUT_LINK_CH1_OUTLINK_RESTART_Msk = 0x400000 + // Bit OUTLINK_RESTART. + DMA_OUT_LINK_CH1_OUTLINK_RESTART = 0x400000 + // Position of OUTLINK_PARK field. + DMA_OUT_LINK_CH1_OUTLINK_PARK_Pos = 0x17 + // Bit mask of OUTLINK_PARK field. + DMA_OUT_LINK_CH1_OUTLINK_PARK_Msk = 0x800000 + // Bit OUTLINK_PARK. + DMA_OUT_LINK_CH1_OUTLINK_PARK = 0x800000 + + // OUT_STATE_CH1: DMA_OUT_STATE_CH1_REG. + // Position of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH1_OUTLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH1_OUTLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH1_OUT_DSCR_STATE_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH1_OUT_DSCR_STATE_Msk = 0xc0000 + // Position of OUT_STATE field. + DMA_OUT_STATE_CH1_OUT_STATE_Pos = 0x14 + // Bit mask of OUT_STATE field. + DMA_OUT_STATE_CH1_OUT_STATE_Msk = 0x700000 + + // OUT_EOF_DES_ADDR_CH1: DMA_OUT_EOF_DES_ADDR_CH1_REG. + // Position of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH1_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH1_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR_CH1: DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. + // Position of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH1_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH1_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // OUT_DSCR_CH1: DMA_OUT_DSCR_CH1_REG. + // Position of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH1_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH1_OUTLINK_DSCR_Msk = 0xffffffff + + // OUT_DSCR_BF0_CH1: DMA_OUT_DSCR_BF0_CH1_REG. + // Position of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH1_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH1_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUT_DSCR_BF1_CH1: DMA_OUT_DSCR_BF1_CH1_REG. + // Position of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH1_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH1_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // OUT_PRI_CH1: DMA_OUT_PRI_CH1_REG. + // Position of TX_PRI field. + DMA_OUT_PRI_CH1_TX_PRI_Pos = 0x0 + // Bit mask of TX_PRI field. + DMA_OUT_PRI_CH1_TX_PRI_Msk = 0xf + + // OUT_PERI_SEL_CH1: DMA_OUT_PERI_SEL_CH1_REG. + // Position of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH1_PERI_OUT_SEL_Pos = 0x0 + // Bit mask of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH1_PERI_OUT_SEL_Msk = 0x3f + + // IN_CONF0_CH2: DMA_IN_CONF0_CH2_REG. + // Position of IN_RST field. + DMA_IN_CONF0_CH2_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + DMA_IN_CONF0_CH2_IN_RST_Msk = 0x1 + // Bit IN_RST. + DMA_IN_CONF0_CH2_IN_RST = 0x1 + // Position of IN_LOOP_TEST field. + DMA_IN_CONF0_CH2_IN_LOOP_TEST_Pos = 0x1 + // Bit mask of IN_LOOP_TEST field. + DMA_IN_CONF0_CH2_IN_LOOP_TEST_Msk = 0x2 + // Bit IN_LOOP_TEST. + DMA_IN_CONF0_CH2_IN_LOOP_TEST = 0x2 + // Position of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH2_INDSCR_BURST_EN_Pos = 0x2 + // Bit mask of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH2_INDSCR_BURST_EN_Msk = 0x4 + // Bit INDSCR_BURST_EN. + DMA_IN_CONF0_CH2_INDSCR_BURST_EN = 0x4 + // Position of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH2_IN_DATA_BURST_EN_Pos = 0x3 + // Bit mask of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH2_IN_DATA_BURST_EN_Msk = 0x8 + // Bit IN_DATA_BURST_EN. + DMA_IN_CONF0_CH2_IN_DATA_BURST_EN = 0x8 + // Position of MEM_TRANS_EN field. + DMA_IN_CONF0_CH2_MEM_TRANS_EN_Pos = 0x4 + // Bit mask of MEM_TRANS_EN field. + DMA_IN_CONF0_CH2_MEM_TRANS_EN_Msk = 0x10 + // Bit MEM_TRANS_EN. + DMA_IN_CONF0_CH2_MEM_TRANS_EN = 0x10 + + // IN_CONF1_CH2: DMA_IN_CONF1_CH2_REG. + // Position of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH2_IN_CHECK_OWNER_Pos = 0xc + // Bit mask of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH2_IN_CHECK_OWNER_Msk = 0x1000 + // Bit IN_CHECK_OWNER. + DMA_IN_CONF1_CH2_IN_CHECK_OWNER = 0x1000 + + // INFIFO_STATUS_CH2: DMA_INFIFO_STATUS_CH2_REG. + // Position of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH2_INFIFO_FULL_Pos = 0x0 + // Bit mask of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH2_INFIFO_FULL_Msk = 0x1 + // Bit INFIFO_FULL. + DMA_INFIFO_STATUS_CH2_INFIFO_FULL = 0x1 + // Position of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_Pos = 0x1 + // Bit mask of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_Msk = 0x2 + // Bit INFIFO_EMPTY. + DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY = 0x2 + // Position of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH2_INFIFO_CNT_Pos = 0x2 + // Bit mask of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH2_INFIFO_CNT_Msk = 0xfc + // Position of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit IN_REMAIN_UNDER_1B. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B = 0x800000 + // Position of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit IN_REMAIN_UNDER_2B. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B = 0x1000000 + // Position of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit IN_REMAIN_UNDER_3B. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B = 0x2000000 + // Position of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit IN_REMAIN_UNDER_4B. + DMA_INFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B = 0x4000000 + // Position of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH2_IN_BUF_HUNGRY_Pos = 0x1b + // Bit mask of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH2_IN_BUF_HUNGRY_Msk = 0x8000000 + // Bit IN_BUF_HUNGRY. + DMA_INFIFO_STATUS_CH2_IN_BUF_HUNGRY = 0x8000000 + + // IN_POP_CH2: DMA_IN_POP_CH2_REG. + // Position of INFIFO_RDATA field. + DMA_IN_POP_CH2_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + DMA_IN_POP_CH2_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + DMA_IN_POP_CH2_INFIFO_POP_Pos = 0xc + // Bit mask of INFIFO_POP field. + DMA_IN_POP_CH2_INFIFO_POP_Msk = 0x1000 + // Bit INFIFO_POP. + DMA_IN_POP_CH2_INFIFO_POP = 0x1000 + + // IN_LINK_CH2: DMA_IN_LINK_CH2_REG. + // Position of INLINK_ADDR field. + DMA_IN_LINK_CH2_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + DMA_IN_LINK_CH2_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + DMA_IN_LINK_CH2_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + DMA_IN_LINK_CH2_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + DMA_IN_LINK_CH2_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + DMA_IN_LINK_CH2_INLINK_STOP_Pos = 0x15 + // Bit mask of INLINK_STOP field. + DMA_IN_LINK_CH2_INLINK_STOP_Msk = 0x200000 + // Bit INLINK_STOP. + DMA_IN_LINK_CH2_INLINK_STOP = 0x200000 + // Position of INLINK_START field. + DMA_IN_LINK_CH2_INLINK_START_Pos = 0x16 + // Bit mask of INLINK_START field. + DMA_IN_LINK_CH2_INLINK_START_Msk = 0x400000 + // Bit INLINK_START. + DMA_IN_LINK_CH2_INLINK_START = 0x400000 + // Position of INLINK_RESTART field. + DMA_IN_LINK_CH2_INLINK_RESTART_Pos = 0x17 + // Bit mask of INLINK_RESTART field. + DMA_IN_LINK_CH2_INLINK_RESTART_Msk = 0x800000 + // Bit INLINK_RESTART. + DMA_IN_LINK_CH2_INLINK_RESTART = 0x800000 + // Position of INLINK_PARK field. + DMA_IN_LINK_CH2_INLINK_PARK_Pos = 0x18 + // Bit mask of INLINK_PARK field. + DMA_IN_LINK_CH2_INLINK_PARK_Msk = 0x1000000 + // Bit INLINK_PARK. + DMA_IN_LINK_CH2_INLINK_PARK = 0x1000000 + + // IN_STATE_CH2: DMA_IN_STATE_CH2_REG. + // Position of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH2_INLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH2_INLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of IN_DSCR_STATE field. + DMA_IN_STATE_CH2_IN_DSCR_STATE_Pos = 0x12 + // Bit mask of IN_DSCR_STATE field. + DMA_IN_STATE_CH2_IN_DSCR_STATE_Msk = 0xc0000 + // Position of IN_STATE field. + DMA_IN_STATE_CH2_IN_STATE_Pos = 0x14 + // Bit mask of IN_STATE field. + DMA_IN_STATE_CH2_IN_STATE_Msk = 0x700000 + + // IN_SUC_EOF_DES_ADDR_CH2: DMA_IN_SUC_EOF_DES_ADDR_CH2_REG. + // Position of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH2_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH2_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_ERR_EOF_DES_ADDR_CH2: DMA_IN_ERR_EOF_DES_ADDR_CH2_REG. + // Position of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH2_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH2_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_DSCR_CH2: DMA_IN_DSCR_CH2_REG. + // Position of INLINK_DSCR field. + DMA_IN_DSCR_CH2_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + DMA_IN_DSCR_CH2_INLINK_DSCR_Msk = 0xffffffff + + // IN_DSCR_BF0_CH2: DMA_IN_DSCR_BF0_CH2_REG. + // Position of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH2_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH2_INLINK_DSCR_BF0_Msk = 0xffffffff + + // IN_DSCR_BF1_CH2: DMA_IN_DSCR_BF1_CH2_REG. + // Position of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH2_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH2_INLINK_DSCR_BF1_Msk = 0xffffffff + + // IN_PRI_CH2: DMA_IN_PRI_CH2_REG. + // Position of RX_PRI field. + DMA_IN_PRI_CH2_RX_PRI_Pos = 0x0 + // Bit mask of RX_PRI field. + DMA_IN_PRI_CH2_RX_PRI_Msk = 0xf + + // IN_PERI_SEL_CH2: DMA_IN_PERI_SEL_CH2_REG. + // Position of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH2_PERI_IN_SEL_Pos = 0x0 + // Bit mask of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH2_PERI_IN_SEL_Msk = 0x3f + + // OUT_CONF0_CH2: DMA_OUT_CONF0_CH2_REG. + // Position of OUT_RST field. + DMA_OUT_CONF0_CH2_OUT_RST_Pos = 0x0 + // Bit mask of OUT_RST field. + DMA_OUT_CONF0_CH2_OUT_RST_Msk = 0x1 + // Bit OUT_RST. + DMA_OUT_CONF0_CH2_OUT_RST = 0x1 + // Position of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH2_OUT_LOOP_TEST_Pos = 0x1 + // Bit mask of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH2_OUT_LOOP_TEST_Msk = 0x2 + // Bit OUT_LOOP_TEST. + DMA_OUT_CONF0_CH2_OUT_LOOP_TEST = 0x2 + // Position of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH2_OUT_AUTO_WRBACK_Pos = 0x2 + // Bit mask of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH2_OUT_AUTO_WRBACK_Msk = 0x4 + // Bit OUT_AUTO_WRBACK. + DMA_OUT_CONF0_CH2_OUT_AUTO_WRBACK = 0x4 + // Position of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH2_OUT_EOF_MODE_Pos = 0x3 + // Bit mask of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH2_OUT_EOF_MODE_Msk = 0x8 + // Bit OUT_EOF_MODE. + DMA_OUT_CONF0_CH2_OUT_EOF_MODE = 0x8 + // Position of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH2_OUTDSCR_BURST_EN_Pos = 0x4 + // Bit mask of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH2_OUTDSCR_BURST_EN_Msk = 0x10 + // Bit OUTDSCR_BURST_EN. + DMA_OUT_CONF0_CH2_OUTDSCR_BURST_EN = 0x10 + // Position of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH2_OUT_DATA_BURST_EN_Pos = 0x5 + // Bit mask of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH2_OUT_DATA_BURST_EN_Msk = 0x20 + // Bit OUT_DATA_BURST_EN. + DMA_OUT_CONF0_CH2_OUT_DATA_BURST_EN = 0x20 + + // OUT_CONF1_CH2: DMA_OUT_CONF1_CH2_REG. + // Position of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH2_OUT_CHECK_OWNER_Pos = 0xc + // Bit mask of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH2_OUT_CHECK_OWNER_Msk = 0x1000 + // Bit OUT_CHECK_OWNER. + DMA_OUT_CONF1_CH2_OUT_CHECK_OWNER = 0x1000 + + // OUTFIFO_STATUS_CH2: DMA_OUTFIFO_STATUS_CH2_REG. + // Position of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_Pos = 0x0 + // Bit mask of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_Msk = 0x1 + // Bit OUTFIFO_FULL. + DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL = 0x1 + // Position of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_Pos = 0x1 + // Bit mask of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_Msk = 0x2 + // Bit OUTFIFO_EMPTY. + DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY = 0x2 + // Position of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH2_OUTFIFO_CNT_Pos = 0x2 + // Bit mask of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH2_OUTFIFO_CNT_Msk = 0xfc + // Position of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit OUT_REMAIN_UNDER_1B. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B = 0x800000 + // Position of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit OUT_REMAIN_UNDER_2B. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B = 0x1000000 + // Position of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit OUT_REMAIN_UNDER_3B. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B = 0x2000000 + // Position of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit OUT_REMAIN_UNDER_4B. + DMA_OUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B = 0x4000000 + + // OUT_PUSH_CH2: DMA_OUT_PUSH_CH2_REG. + // Position of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH2_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH2_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH2_OUTFIFO_PUSH_Pos = 0x9 + // Bit mask of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH2_OUTFIFO_PUSH_Msk = 0x200 + // Bit OUTFIFO_PUSH. + DMA_OUT_PUSH_CH2_OUTFIFO_PUSH = 0x200 + + // OUT_LINK_CH2: DMA_OUT_LINK_CH2_REG. + // Position of OUTLINK_ADDR field. + DMA_OUT_LINK_CH2_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + DMA_OUT_LINK_CH2_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + DMA_OUT_LINK_CH2_OUTLINK_STOP_Pos = 0x14 + // Bit mask of OUTLINK_STOP field. + DMA_OUT_LINK_CH2_OUTLINK_STOP_Msk = 0x100000 + // Bit OUTLINK_STOP. + DMA_OUT_LINK_CH2_OUTLINK_STOP = 0x100000 + // Position of OUTLINK_START field. + DMA_OUT_LINK_CH2_OUTLINK_START_Pos = 0x15 + // Bit mask of OUTLINK_START field. + DMA_OUT_LINK_CH2_OUTLINK_START_Msk = 0x200000 + // Bit OUTLINK_START. + DMA_OUT_LINK_CH2_OUTLINK_START = 0x200000 + // Position of OUTLINK_RESTART field. + DMA_OUT_LINK_CH2_OUTLINK_RESTART_Pos = 0x16 + // Bit mask of OUTLINK_RESTART field. + DMA_OUT_LINK_CH2_OUTLINK_RESTART_Msk = 0x400000 + // Bit OUTLINK_RESTART. + DMA_OUT_LINK_CH2_OUTLINK_RESTART = 0x400000 + // Position of OUTLINK_PARK field. + DMA_OUT_LINK_CH2_OUTLINK_PARK_Pos = 0x17 + // Bit mask of OUTLINK_PARK field. + DMA_OUT_LINK_CH2_OUTLINK_PARK_Msk = 0x800000 + // Bit OUTLINK_PARK. + DMA_OUT_LINK_CH2_OUTLINK_PARK = 0x800000 + + // OUT_STATE_CH2: DMA_OUT_STATE_CH2_REG. + // Position of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH2_OUTLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH2_OUTLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH2_OUT_DSCR_STATE_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH2_OUT_DSCR_STATE_Msk = 0xc0000 + // Position of OUT_STATE field. + DMA_OUT_STATE_CH2_OUT_STATE_Pos = 0x14 + // Bit mask of OUT_STATE field. + DMA_OUT_STATE_CH2_OUT_STATE_Msk = 0x700000 + + // OUT_EOF_DES_ADDR_CH2: DMA_OUT_EOF_DES_ADDR_CH2_REG. + // Position of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH2_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH2_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR_CH2: DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. + // Position of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH2_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH2_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // OUT_DSCR_CH2: DMA_OUT_DSCR_CH2_REG. + // Position of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH2_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH2_OUTLINK_DSCR_Msk = 0xffffffff + + // OUT_DSCR_BF0_CH2: DMA_OUT_DSCR_BF0_CH2_REG. + // Position of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH2_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH2_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUT_DSCR_BF1_CH2: DMA_OUT_DSCR_BF1_CH2_REG. + // Position of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH2_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH2_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // OUT_PRI_CH2: DMA_OUT_PRI_CH2_REG. + // Position of TX_PRI field. + DMA_OUT_PRI_CH2_TX_PRI_Pos = 0x0 + // Bit mask of TX_PRI field. + DMA_OUT_PRI_CH2_TX_PRI_Msk = 0xf + + // OUT_PERI_SEL_CH2: DMA_OUT_PERI_SEL_CH2_REG. + // Position of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH2_PERI_OUT_SEL_Pos = 0x0 + // Bit mask of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH2_PERI_OUT_SEL_Msk = 0x3f +) + +// Constants for DS: Digital Signature +const ( + // SET_START: DS start control register + // Position of SET_START field. + DS_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + DS_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + DS_SET_START_SET_START = 0x1 + + // SET_CONTINUE: DS continue control register + // Position of SET_CONTINUE field. + DS_SET_CONTINUE_SET_CONTINUE_Pos = 0x0 + // Bit mask of SET_CONTINUE field. + DS_SET_CONTINUE_SET_CONTINUE_Msk = 0x1 + // Bit SET_CONTINUE. + DS_SET_CONTINUE_SET_CONTINUE = 0x1 + + // SET_FINISH: DS finish control register + // Position of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Pos = 0x0 + // Bit mask of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Msk = 0x1 + // Bit SET_FINISH. + DS_SET_FINISH_SET_FINISH = 0x1 + + // QUERY_BUSY: DS query busy register + // Position of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Pos = 0x0 + // Bit mask of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Msk = 0x1 + // Bit QUERY_BUSY. + DS_QUERY_BUSY_QUERY_BUSY = 0x1 + + // QUERY_KEY_WRONG: DS query key-wrong counter register + // Position of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Pos = 0x0 + // Bit mask of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Msk = 0xf + + // QUERY_CHECK: DS query check result register + // Position of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Pos = 0x0 + // Bit mask of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Msk = 0x1 + // Bit MD_ERROR. + DS_QUERY_CHECK_MD_ERROR = 0x1 + // Position of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Pos = 0x1 + // Bit mask of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Msk = 0x2 + // Bit PADDING_BAD. + DS_QUERY_CHECK_PADDING_BAD = 0x2 + + // DATE: DS version control register + // Position of DATE field. + DS_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DS_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for EFUSE: eFuse Controller +const ( + // PGM_DATA0: Register 0 that stores data to be programmed. + // Position of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Pos = 0x0 + // Bit mask of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Msk = 0xffffffff + + // PGM_DATA1: Register 1 that stores data to be programmed. + // Position of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Pos = 0x0 + // Bit mask of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Msk = 0xffffffff + + // PGM_DATA2: Register 2 that stores data to be programmed. + // Position of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Pos = 0x0 + // Bit mask of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Msk = 0xffffffff + + // PGM_DATA3: Register 3 that stores data to be programmed. + // Position of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Pos = 0x0 + // Bit mask of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Msk = 0xffffffff + + // PGM_DATA4: Register 4 that stores data to be programmed. + // Position of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Pos = 0x0 + // Bit mask of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Msk = 0xffffffff + + // PGM_DATA5: Register 5 that stores data to be programmed. + // Position of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Pos = 0x0 + // Bit mask of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Msk = 0xffffffff + + // PGM_DATA6: Register 6 that stores data to be programmed. + // Position of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Pos = 0x0 + // Bit mask of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Msk = 0xffffffff + + // PGM_DATA7: Register 7 that stores data to be programmed. + // Position of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Pos = 0x0 + // Bit mask of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Msk = 0xffffffff + + // PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Pos = 0x0 + // Bit mask of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Msk = 0xffffffff + + // PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Pos = 0x0 + // Bit mask of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Msk = 0xffffffff + + // PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Pos = 0x0 + // Bit mask of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Msk = 0xffffffff + + // RD_WR_DIS: BLOCK0 data register 0. + // Position of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Pos = 0x0 + // Bit mask of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Msk = 0xffffffff + + // RD_REPEAT_DATA0: BLOCK0 data register 1. + // Position of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Pos = 0x0 + // Bit mask of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Msk = 0x7f + // Position of DIS_RTC_RAM_BOOT field. + EFUSE_RD_REPEAT_DATA0_DIS_RTC_RAM_BOOT_Pos = 0x7 + // Bit mask of DIS_RTC_RAM_BOOT field. + EFUSE_RD_REPEAT_DATA0_DIS_RTC_RAM_BOOT_Msk = 0x80 + // Bit DIS_RTC_RAM_BOOT. + EFUSE_RD_REPEAT_DATA0_DIS_RTC_RAM_BOOT = 0x80 + // Position of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Pos = 0x8 + // Bit mask of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Msk = 0x100 + // Bit DIS_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE = 0x100 + // Position of DIS_USB_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG_Pos = 0x9 + // Bit mask of DIS_USB_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG_Msk = 0x200 + // Bit DIS_USB_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG = 0x200 + // Position of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Pos = 0xa + // Bit mask of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Msk = 0x400 + // Bit DIS_DOWNLOAD_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE = 0x400 + // Position of DIS_USB_DEVICE field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_DEVICE_Pos = 0xb + // Bit mask of DIS_USB_DEVICE field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_DEVICE_Msk = 0x800 + // Bit DIS_USB_DEVICE. + EFUSE_RD_REPEAT_DATA0_DIS_USB_DEVICE = 0x800 + // Position of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD = 0x1000 + // Position of RPT4_RESERVED6 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED6_Pos = 0xd + // Bit mask of RPT4_RESERVED6 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED6_Msk = 0x2000 + // Bit RPT4_RESERVED6. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED6 = 0x2000 + // Position of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Pos = 0xe + // Bit mask of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Msk = 0x4000 + // Bit DIS_CAN. + EFUSE_RD_REPEAT_DATA0_DIS_CAN = 0x4000 + // Position of JTAG_SEL_ENABLE field. + EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE_Pos = 0xf + // Bit mask of JTAG_SEL_ENABLE field. + EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE_Msk = 0x8000 + // Bit JTAG_SEL_ENABLE. + EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE = 0x8000 + // Position of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Pos = 0x10 + // Bit mask of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Msk = 0x70000 + // Position of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Pos = 0x13 + // Bit mask of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Msk = 0x80000 + // Bit DIS_PAD_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG = 0x80000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x14 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x100000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT = 0x100000 + // Position of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Pos = 0x15 + // Bit mask of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Msk = 0x600000 + // Position of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Pos = 0x17 + // Bit mask of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Msk = 0x1800000 + // Position of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Pos = 0x19 + // Bit mask of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Msk = 0x2000000 + // Bit USB_EXCHG_PINS. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS = 0x2000000 + // Position of VDD_SPI_AS_GPIO field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_AS_GPIO_Pos = 0x1a + // Bit mask of VDD_SPI_AS_GPIO field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_AS_GPIO_Msk = 0x4000000 + // Bit VDD_SPI_AS_GPIO. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_AS_GPIO = 0x4000000 + // Position of BTLC_GPIO_ENABLE field. + EFUSE_RD_REPEAT_DATA0_BTLC_GPIO_ENABLE_Pos = 0x1b + // Bit mask of BTLC_GPIO_ENABLE field. + EFUSE_RD_REPEAT_DATA0_BTLC_GPIO_ENABLE_Msk = 0x18000000 + // Position of POWERGLITCH_EN field. + EFUSE_RD_REPEAT_DATA0_POWERGLITCH_EN_Pos = 0x1d + // Bit mask of POWERGLITCH_EN field. + EFUSE_RD_REPEAT_DATA0_POWERGLITCH_EN_Msk = 0x20000000 + // Bit POWERGLITCH_EN. + EFUSE_RD_REPEAT_DATA0_POWERGLITCH_EN = 0x20000000 + // Position of POWER_GLITCH_DSENSE field. + EFUSE_RD_REPEAT_DATA0_POWER_GLITCH_DSENSE_Pos = 0x1e + // Bit mask of POWER_GLITCH_DSENSE field. + EFUSE_RD_REPEAT_DATA0_POWER_GLITCH_DSENSE_Msk = 0xc0000000 + + // RD_REPEAT_DATA1: BLOCK0 data register 2. + // Position of RPT4_RESERVED2 field. + EFUSE_RD_REPEAT_DATA1_RPT4_RESERVED2_Pos = 0x0 + // Bit mask of RPT4_RESERVED2 field. + EFUSE_RD_REPEAT_DATA1_RPT4_RESERVED2_Msk = 0xffff + // Position of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0 = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1 = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2 = 0x800000 + // Position of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Msk = 0xf000000 + // Position of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Msk = 0xf0000000 + + // RD_REPEAT_DATA2: BLOCK0 data register 3. + // Position of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Msk = 0xf + // Position of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Msk = 0xf0 + // Position of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Msk = 0xf00 + // Position of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Pos = 0xc + // Bit mask of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Msk = 0xf000 + // Position of RPT4_RESERVED3 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED3_Pos = 0x10 + // Bit mask of RPT4_RESERVED3 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED3_Msk = 0xf0000 + // Position of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Msk = 0x100000 + // Bit SECURE_BOOT_EN. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE = 0x200000 + // Position of RPT4_RESERVED0 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED0_Pos = 0x16 + // Bit mask of RPT4_RESERVED0 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED0_Msk = 0xfc00000 + // Position of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Pos = 0x1c + // Bit mask of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Msk = 0xf0000000 + + // RD_REPEAT_DATA3: BLOCK0 data register 4. + // Position of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE = 0x1 + // Position of DIS_LEGACY_SPI_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT_Pos = 0x1 + // Bit mask of DIS_LEGACY_SPI_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT_Msk = 0x2 + // Bit DIS_LEGACY_SPI_BOOT. + EFUSE_RD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT = 0x2 + // Position of UART_PRINT_CHANNEL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CHANNEL_Pos = 0x2 + // Bit mask of UART_PRINT_CHANNEL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CHANNEL_Msk = 0x4 + // Bit UART_PRINT_CHANNEL. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CHANNEL = 0x4 + // Position of FLASH_ECC_MODE field. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_MODE_Pos = 0x3 + // Bit mask of FLASH_ECC_MODE field. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_MODE_Msk = 0x8 + // Bit FLASH_ECC_MODE. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_MODE = 0x8 + // Position of DIS_USB_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE_Pos = 0x4 + // Bit mask of DIS_USB_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE_Msk = 0x10 + // Bit DIS_USB_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD = 0x20 + // Position of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Msk = 0xc0 + // Position of PIN_POWER_SELECTION field. + EFUSE_RD_REPEAT_DATA3_PIN_POWER_SELECTION_Pos = 0x8 + // Bit mask of PIN_POWER_SELECTION field. + EFUSE_RD_REPEAT_DATA3_PIN_POWER_SELECTION_Msk = 0x100 + // Bit PIN_POWER_SELECTION. + EFUSE_RD_REPEAT_DATA3_PIN_POWER_SELECTION = 0x100 + // Position of FLASH_TYPE field. + EFUSE_RD_REPEAT_DATA3_FLASH_TYPE_Pos = 0x9 + // Bit mask of FLASH_TYPE field. + EFUSE_RD_REPEAT_DATA3_FLASH_TYPE_Msk = 0x200 + // Bit FLASH_TYPE. + EFUSE_RD_REPEAT_DATA3_FLASH_TYPE = 0x200 + // Position of FLASH_PAGE_SIZE field. + EFUSE_RD_REPEAT_DATA3_FLASH_PAGE_SIZE_Pos = 0xa + // Bit mask of FLASH_PAGE_SIZE field. + EFUSE_RD_REPEAT_DATA3_FLASH_PAGE_SIZE_Msk = 0xc00 + // Position of FLASH_ECC_EN field. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_EN_Pos = 0xc + // Bit mask of FLASH_ECC_EN field. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_EN_Msk = 0x1000 + // Bit FLASH_ECC_EN. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_EN = 0x1000 + // Position of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Pos = 0xd + // Bit mask of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Msk = 0x2000 + // Bit FORCE_SEND_RESUME. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME = 0x2000 + // Position of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Pos = 0xe + // Bit mask of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Msk = 0x3fffc000 + // Position of RPT4_RESERVED1 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED1_Pos = 0x1e + // Bit mask of RPT4_RESERVED1 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED1_Msk = 0xc0000000 + + // RD_REPEAT_DATA4: BLOCK0 data register 5. + // Position of RPT4_RESERVED4 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_Pos = 0x0 + // Bit mask of RPT4_RESERVED4 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_Msk = 0xffffff + + // RD_MAC_SPI_SYS_0: BLOCK1 data register 0. + // Position of MAC_0 field. + EFUSE_RD_MAC_SPI_SYS_0_MAC_0_Pos = 0x0 + // Bit mask of MAC_0 field. + EFUSE_RD_MAC_SPI_SYS_0_MAC_0_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_1: BLOCK1 data register 1. + // Position of MAC_1 field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_1_Pos = 0x0 + // Bit mask of MAC_1 field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_1_Msk = 0xffff + // Position of SPI_PAD_CONF_0 field. + EFUSE_RD_MAC_SPI_SYS_1_SPI_PAD_CONF_0_Pos = 0x10 + // Bit mask of SPI_PAD_CONF_0 field. + EFUSE_RD_MAC_SPI_SYS_1_SPI_PAD_CONF_0_Msk = 0xffff0000 + + // RD_MAC_SPI_SYS_2: BLOCK1 data register 2. + // Position of SPI_PAD_CONF_1 field. + EFUSE_RD_MAC_SPI_SYS_2_SPI_PAD_CONF_1_Pos = 0x0 + // Bit mask of SPI_PAD_CONF_1 field. + EFUSE_RD_MAC_SPI_SYS_2_SPI_PAD_CONF_1_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_3: BLOCK1 data register 3. + // Position of SPI_PAD_CONF_2 field. + EFUSE_RD_MAC_SPI_SYS_3_SPI_PAD_CONF_2_Pos = 0x0 + // Bit mask of SPI_PAD_CONF_2 field. + EFUSE_RD_MAC_SPI_SYS_3_SPI_PAD_CONF_2_Msk = 0x3ffff + // Position of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SPI_SYS_3_SYS_DATA_PART0_0_Pos = 0x12 + // Bit mask of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SPI_SYS_3_SYS_DATA_PART0_0_Msk = 0xfffc0000 + + // RD_MAC_SPI_SYS_4: BLOCK1 data register 4. + // Position of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SPI_SYS_4_SYS_DATA_PART0_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SPI_SYS_4_SYS_DATA_PART0_1_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_5: BLOCK1 data register 5. + // Position of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SPI_SYS_5_SYS_DATA_PART0_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SPI_SYS_5_SYS_DATA_PART0_2_Msk = 0xffffffff + + // RD_SYS_PART1_DATA0: Register 0 of BLOCK2 (system). + // Position of SYS_DATA_PART1_0 field. + EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_0 field. + EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Msk = 0xffffffff + + // RD_SYS_PART1_DATA1: Register 1 of BLOCK2 (system). + // Position of SYS_DATA_PART1_1 field. + EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_1 field. + EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Msk = 0xffffffff + + // RD_SYS_PART1_DATA2: Register 2 of BLOCK2 (system). + // Position of SYS_DATA_PART1_2 field. + EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_2 field. + EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Msk = 0xffffffff + + // RD_SYS_PART1_DATA3: Register 3 of BLOCK2 (system). + // Position of SYS_DATA_PART1_3 field. + EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_3 field. + EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Msk = 0xffffffff + + // RD_SYS_PART1_DATA4: Register 4 of BLOCK2 (system). + // Position of SYS_DATA_PART1_4 field. + EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_4 field. + EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Msk = 0xffffffff + + // RD_SYS_PART1_DATA5: Register 5 of BLOCK2 (system). + // Position of SYS_DATA_PART1_5 field. + EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_5 field. + EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Msk = 0xffffffff + + // RD_SYS_PART1_DATA6: Register 6 of BLOCK2 (system). + // Position of SYS_DATA_PART1_6 field. + EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_6 field. + EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Msk = 0xffffffff + + // RD_SYS_PART1_DATA7: Register 7 of BLOCK2 (system). + // Position of SYS_DATA_PART1_7 field. + EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_7 field. + EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Msk = 0xffffffff + + // RD_USR_DATA0: Register 0 of BLOCK3 (user). + // Position of USR_DATA0 field. + EFUSE_RD_USR_DATA0_USR_DATA0_Pos = 0x0 + // Bit mask of USR_DATA0 field. + EFUSE_RD_USR_DATA0_USR_DATA0_Msk = 0xffffffff + + // RD_USR_DATA1: Register 1 of BLOCK3 (user). + // Position of USR_DATA1 field. + EFUSE_RD_USR_DATA1_USR_DATA1_Pos = 0x0 + // Bit mask of USR_DATA1 field. + EFUSE_RD_USR_DATA1_USR_DATA1_Msk = 0xffffffff + + // RD_USR_DATA2: Register 2 of BLOCK3 (user). + // Position of USR_DATA2 field. + EFUSE_RD_USR_DATA2_USR_DATA2_Pos = 0x0 + // Bit mask of USR_DATA2 field. + EFUSE_RD_USR_DATA2_USR_DATA2_Msk = 0xffffffff + + // RD_USR_DATA3: Register 3 of BLOCK3 (user). + // Position of USR_DATA3 field. + EFUSE_RD_USR_DATA3_USR_DATA3_Pos = 0x0 + // Bit mask of USR_DATA3 field. + EFUSE_RD_USR_DATA3_USR_DATA3_Msk = 0xffffffff + + // RD_USR_DATA4: Register 4 of BLOCK3 (user). + // Position of USR_DATA4 field. + EFUSE_RD_USR_DATA4_USR_DATA4_Pos = 0x0 + // Bit mask of USR_DATA4 field. + EFUSE_RD_USR_DATA4_USR_DATA4_Msk = 0xffffffff + + // RD_USR_DATA5: Register 5 of BLOCK3 (user). + // Position of USR_DATA5 field. + EFUSE_RD_USR_DATA5_USR_DATA5_Pos = 0x0 + // Bit mask of USR_DATA5 field. + EFUSE_RD_USR_DATA5_USR_DATA5_Msk = 0xffffffff + + // RD_USR_DATA6: Register 6 of BLOCK3 (user). + // Position of USR_DATA6 field. + EFUSE_RD_USR_DATA6_USR_DATA6_Pos = 0x0 + // Bit mask of USR_DATA6 field. + EFUSE_RD_USR_DATA6_USR_DATA6_Msk = 0xffffffff + + // RD_USR_DATA7: Register 7 of BLOCK3 (user). + // Position of USR_DATA7 field. + EFUSE_RD_USR_DATA7_USR_DATA7_Pos = 0x0 + // Bit mask of USR_DATA7 field. + EFUSE_RD_USR_DATA7_USR_DATA7_Msk = 0xffffffff + + // RD_KEY0_DATA0: Register 0 of BLOCK4 (KEY0). + // Position of KEY0_DATA0 field. + EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Pos = 0x0 + // Bit mask of KEY0_DATA0 field. + EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Msk = 0xffffffff + + // RD_KEY0_DATA1: Register 1 of BLOCK4 (KEY0). + // Position of KEY0_DATA1 field. + EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Pos = 0x0 + // Bit mask of KEY0_DATA1 field. + EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Msk = 0xffffffff + + // RD_KEY0_DATA2: Register 2 of BLOCK4 (KEY0). + // Position of KEY0_DATA2 field. + EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Pos = 0x0 + // Bit mask of KEY0_DATA2 field. + EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Msk = 0xffffffff + + // RD_KEY0_DATA3: Register 3 of BLOCK4 (KEY0). + // Position of KEY0_DATA3 field. + EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Pos = 0x0 + // Bit mask of KEY0_DATA3 field. + EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Msk = 0xffffffff + + // RD_KEY0_DATA4: Register 4 of BLOCK4 (KEY0). + // Position of KEY0_DATA4 field. + EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Pos = 0x0 + // Bit mask of KEY0_DATA4 field. + EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Msk = 0xffffffff + + // RD_KEY0_DATA5: Register 5 of BLOCK4 (KEY0). + // Position of KEY0_DATA5 field. + EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Pos = 0x0 + // Bit mask of KEY0_DATA5 field. + EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Msk = 0xffffffff + + // RD_KEY0_DATA6: Register 6 of BLOCK4 (KEY0). + // Position of KEY0_DATA6 field. + EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Pos = 0x0 + // Bit mask of KEY0_DATA6 field. + EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Msk = 0xffffffff + + // RD_KEY0_DATA7: Register 7 of BLOCK4 (KEY0). + // Position of KEY0_DATA7 field. + EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Pos = 0x0 + // Bit mask of KEY0_DATA7 field. + EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Msk = 0xffffffff + + // RD_KEY1_DATA0: Register 0 of BLOCK5 (KEY1). + // Position of KEY1_DATA0 field. + EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Pos = 0x0 + // Bit mask of KEY1_DATA0 field. + EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Msk = 0xffffffff + + // RD_KEY1_DATA1: Register 1 of BLOCK5 (KEY1). + // Position of KEY1_DATA1 field. + EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Pos = 0x0 + // Bit mask of KEY1_DATA1 field. + EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Msk = 0xffffffff + + // RD_KEY1_DATA2: Register 2 of BLOCK5 (KEY1). + // Position of KEY1_DATA2 field. + EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Pos = 0x0 + // Bit mask of KEY1_DATA2 field. + EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Msk = 0xffffffff + + // RD_KEY1_DATA3: Register 3 of BLOCK5 (KEY1). + // Position of KEY1_DATA3 field. + EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Pos = 0x0 + // Bit mask of KEY1_DATA3 field. + EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Msk = 0xffffffff + + // RD_KEY1_DATA4: Register 4 of BLOCK5 (KEY1). + // Position of KEY1_DATA4 field. + EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Pos = 0x0 + // Bit mask of KEY1_DATA4 field. + EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Msk = 0xffffffff + + // RD_KEY1_DATA5: Register 5 of BLOCK5 (KEY1). + // Position of KEY1_DATA5 field. + EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Pos = 0x0 + // Bit mask of KEY1_DATA5 field. + EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Msk = 0xffffffff + + // RD_KEY1_DATA6: Register 6 of BLOCK5 (KEY1). + // Position of KEY1_DATA6 field. + EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Pos = 0x0 + // Bit mask of KEY1_DATA6 field. + EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Msk = 0xffffffff + + // RD_KEY1_DATA7: Register 7 of BLOCK5 (KEY1). + // Position of KEY1_DATA7 field. + EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Pos = 0x0 + // Bit mask of KEY1_DATA7 field. + EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Msk = 0xffffffff + + // RD_KEY2_DATA0: Register 0 of BLOCK6 (KEY2). + // Position of KEY2_DATA0 field. + EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Pos = 0x0 + // Bit mask of KEY2_DATA0 field. + EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Msk = 0xffffffff + + // RD_KEY2_DATA1: Register 1 of BLOCK6 (KEY2). + // Position of KEY2_DATA1 field. + EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Pos = 0x0 + // Bit mask of KEY2_DATA1 field. + EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Msk = 0xffffffff + + // RD_KEY2_DATA2: Register 2 of BLOCK6 (KEY2). + // Position of KEY2_DATA2 field. + EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Pos = 0x0 + // Bit mask of KEY2_DATA2 field. + EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Msk = 0xffffffff + + // RD_KEY2_DATA3: Register 3 of BLOCK6 (KEY2). + // Position of KEY2_DATA3 field. + EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Pos = 0x0 + // Bit mask of KEY2_DATA3 field. + EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Msk = 0xffffffff + + // RD_KEY2_DATA4: Register 4 of BLOCK6 (KEY2). + // Position of KEY2_DATA4 field. + EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Pos = 0x0 + // Bit mask of KEY2_DATA4 field. + EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Msk = 0xffffffff + + // RD_KEY2_DATA5: Register 5 of BLOCK6 (KEY2). + // Position of KEY2_DATA5 field. + EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Pos = 0x0 + // Bit mask of KEY2_DATA5 field. + EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Msk = 0xffffffff + + // RD_KEY2_DATA6: Register 6 of BLOCK6 (KEY2). + // Position of KEY2_DATA6 field. + EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Pos = 0x0 + // Bit mask of KEY2_DATA6 field. + EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Msk = 0xffffffff + + // RD_KEY2_DATA7: Register 7 of BLOCK6 (KEY2). + // Position of KEY2_DATA7 field. + EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Pos = 0x0 + // Bit mask of KEY2_DATA7 field. + EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Msk = 0xffffffff + + // RD_KEY3_DATA0: Register 0 of BLOCK7 (KEY3). + // Position of KEY3_DATA0 field. + EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Pos = 0x0 + // Bit mask of KEY3_DATA0 field. + EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Msk = 0xffffffff + + // RD_KEY3_DATA1: Register 1 of BLOCK7 (KEY3). + // Position of KEY3_DATA1 field. + EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Pos = 0x0 + // Bit mask of KEY3_DATA1 field. + EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Msk = 0xffffffff + + // RD_KEY3_DATA2: Register 2 of BLOCK7 (KEY3). + // Position of KEY3_DATA2 field. + EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Pos = 0x0 + // Bit mask of KEY3_DATA2 field. + EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Msk = 0xffffffff + + // RD_KEY3_DATA3: Register 3 of BLOCK7 (KEY3). + // Position of KEY3_DATA3 field. + EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Pos = 0x0 + // Bit mask of KEY3_DATA3 field. + EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Msk = 0xffffffff + + // RD_KEY3_DATA4: Register 4 of BLOCK7 (KEY3). + // Position of KEY3_DATA4 field. + EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Pos = 0x0 + // Bit mask of KEY3_DATA4 field. + EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Msk = 0xffffffff + + // RD_KEY3_DATA5: Register 5 of BLOCK7 (KEY3). + // Position of KEY3_DATA5 field. + EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Pos = 0x0 + // Bit mask of KEY3_DATA5 field. + EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Msk = 0xffffffff + + // RD_KEY3_DATA6: Register 6 of BLOCK7 (KEY3). + // Position of KEY3_DATA6 field. + EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Pos = 0x0 + // Bit mask of KEY3_DATA6 field. + EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Msk = 0xffffffff + + // RD_KEY3_DATA7: Register 7 of BLOCK7 (KEY3). + // Position of KEY3_DATA7 field. + EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Pos = 0x0 + // Bit mask of KEY3_DATA7 field. + EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Msk = 0xffffffff + + // RD_KEY4_DATA0: Register 0 of BLOCK8 (KEY4). + // Position of KEY4_DATA0 field. + EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Pos = 0x0 + // Bit mask of KEY4_DATA0 field. + EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Msk = 0xffffffff + + // RD_KEY4_DATA1: Register 1 of BLOCK8 (KEY4). + // Position of KEY4_DATA1 field. + EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Pos = 0x0 + // Bit mask of KEY4_DATA1 field. + EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Msk = 0xffffffff + + // RD_KEY4_DATA2: Register 2 of BLOCK8 (KEY4). + // Position of KEY4_DATA2 field. + EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Pos = 0x0 + // Bit mask of KEY4_DATA2 field. + EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Msk = 0xffffffff + + // RD_KEY4_DATA3: Register 3 of BLOCK8 (KEY4). + // Position of KEY4_DATA3 field. + EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Pos = 0x0 + // Bit mask of KEY4_DATA3 field. + EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Msk = 0xffffffff + + // RD_KEY4_DATA4: Register 4 of BLOCK8 (KEY4). + // Position of KEY4_DATA4 field. + EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Pos = 0x0 + // Bit mask of KEY4_DATA4 field. + EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Msk = 0xffffffff + + // RD_KEY4_DATA5: Register 5 of BLOCK8 (KEY4). + // Position of KEY4_DATA5 field. + EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Pos = 0x0 + // Bit mask of KEY4_DATA5 field. + EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Msk = 0xffffffff + + // RD_KEY4_DATA6: Register 6 of BLOCK8 (KEY4). + // Position of KEY4_DATA6 field. + EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Pos = 0x0 + // Bit mask of KEY4_DATA6 field. + EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Msk = 0xffffffff + + // RD_KEY4_DATA7: Register 7 of BLOCK8 (KEY4). + // Position of KEY4_DATA7 field. + EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Pos = 0x0 + // Bit mask of KEY4_DATA7 field. + EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Msk = 0xffffffff + + // RD_KEY5_DATA0: Register 0 of BLOCK9 (KEY5). + // Position of KEY5_DATA0 field. + EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Pos = 0x0 + // Bit mask of KEY5_DATA0 field. + EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Msk = 0xffffffff + + // RD_KEY5_DATA1: Register 1 of BLOCK9 (KEY5). + // Position of KEY5_DATA1 field. + EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Pos = 0x0 + // Bit mask of KEY5_DATA1 field. + EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Msk = 0xffffffff + + // RD_KEY5_DATA2: Register 2 of BLOCK9 (KEY5). + // Position of KEY5_DATA2 field. + EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Pos = 0x0 + // Bit mask of KEY5_DATA2 field. + EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Msk = 0xffffffff + + // RD_KEY5_DATA3: Register 3 of BLOCK9 (KEY5). + // Position of KEY5_DATA3 field. + EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Pos = 0x0 + // Bit mask of KEY5_DATA3 field. + EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Msk = 0xffffffff + + // RD_KEY5_DATA4: Register 4 of BLOCK9 (KEY5). + // Position of KEY5_DATA4 field. + EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Pos = 0x0 + // Bit mask of KEY5_DATA4 field. + EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Msk = 0xffffffff + + // RD_KEY5_DATA5: Register 5 of BLOCK9 (KEY5). + // Position of KEY5_DATA5 field. + EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Pos = 0x0 + // Bit mask of KEY5_DATA5 field. + EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Msk = 0xffffffff + + // RD_KEY5_DATA6: Register 6 of BLOCK9 (KEY5). + // Position of KEY5_DATA6 field. + EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Pos = 0x0 + // Bit mask of KEY5_DATA6 field. + EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Msk = 0xffffffff + + // RD_KEY5_DATA7: Register 7 of BLOCK9 (KEY5). + // Position of KEY5_DATA7 field. + EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Pos = 0x0 + // Bit mask of KEY5_DATA7 field. + EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Msk = 0xffffffff + + // RD_SYS_PART2_DATA0: Register 0 of BLOCK10 (system). + // Position of SYS_DATA_PART2_0 field. + EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_0 field. + EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Msk = 0xffffffff + + // RD_SYS_PART2_DATA1: Register 1 of BLOCK9 (KEY5). + // Position of SYS_DATA_PART2_1 field. + EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_1 field. + EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Msk = 0xffffffff + + // RD_SYS_PART2_DATA2: Register 2 of BLOCK10 (system). + // Position of SYS_DATA_PART2_2 field. + EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_2 field. + EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Msk = 0xffffffff + + // RD_SYS_PART2_DATA3: Register 3 of BLOCK10 (system). + // Position of SYS_DATA_PART2_3 field. + EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_3 field. + EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Msk = 0xffffffff + + // RD_SYS_PART2_DATA4: Register 4 of BLOCK10 (system). + // Position of SYS_DATA_PART2_4 field. + EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_4 field. + EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Msk = 0xffffffff + + // RD_SYS_PART2_DATA5: Register 5 of BLOCK10 (system). + // Position of SYS_DATA_PART2_5 field. + EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_5 field. + EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Msk = 0xffffffff + + // RD_SYS_PART2_DATA6: Register 6 of BLOCK10 (system). + // Position of SYS_DATA_PART2_6 field. + EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_6 field. + EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Msk = 0xffffffff + + // RD_SYS_PART2_DATA7: Register 7 of BLOCK10 (system). + // Position of SYS_DATA_PART2_7 field. + EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_7 field. + EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Msk = 0xffffffff + + // RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. + // Position of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Pos = 0x0 + // Bit mask of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Msk = 0x7f + // Position of DIS_RTC_RAM_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR_Pos = 0x7 + // Bit mask of DIS_RTC_RAM_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR_Msk = 0x80 + // Bit DIS_RTC_RAM_BOOT_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR = 0x80 + // Position of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Pos = 0x8 + // Bit mask of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Msk = 0x100 + // Bit DIS_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR = 0x100 + // Position of DIS_USB_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR_Pos = 0x9 + // Bit mask of DIS_USB_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR_Msk = 0x200 + // Bit DIS_USB_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR = 0x200 + // Position of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR_Pos = 0xa + // Bit mask of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR_Msk = 0x400 + // Bit DIS_DOWNLOAD_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR = 0x400 + // Position of DIS_USB_DEVICE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_DEVICE_ERR_Pos = 0xb + // Bit mask of DIS_USB_DEVICE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_DEVICE_ERR_Msk = 0x800 + // Bit DIS_USB_DEVICE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_USB_DEVICE_ERR = 0x800 + // Position of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR = 0x1000 + // Position of RPT4_RESERVED6_ERR field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED6_ERR_Pos = 0xd + // Bit mask of RPT4_RESERVED6_ERR field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED6_ERR_Msk = 0x2000 + // Bit RPT4_RESERVED6_ERR. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED6_ERR = 0x2000 + // Position of DIS_CAN_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_CAN_ERR_Pos = 0xe + // Bit mask of DIS_CAN_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_CAN_ERR_Msk = 0x4000 + // Bit DIS_CAN_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_CAN_ERR = 0x4000 + // Position of JTAG_SEL_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR_Pos = 0xf + // Bit mask of JTAG_SEL_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR_Msk = 0x8000 + // Bit JTAG_SEL_ENABLE_ERR. + EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR = 0x8000 + // Position of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Pos = 0x10 + // Bit mask of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Msk = 0x70000 + // Position of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Pos = 0x13 + // Bit mask of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Msk = 0x80000 + // Bit DIS_PAD_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR = 0x80000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Pos = 0x14 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Msk = 0x100000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR = 0x100000 + // Position of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Pos = 0x15 + // Bit mask of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Msk = 0x600000 + // Position of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Pos = 0x17 + // Bit mask of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Msk = 0x1800000 + // Position of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Pos = 0x19 + // Bit mask of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Msk = 0x2000000 + // Bit USB_EXCHG_PINS_ERR. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR = 0x2000000 + // Position of VDD_SPI_AS_GPIO_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR_Pos = 0x1a + // Bit mask of VDD_SPI_AS_GPIO_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR_Msk = 0x4000000 + // Bit VDD_SPI_AS_GPIO_ERR. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR = 0x4000000 + // Position of BTLC_GPIO_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_BTLC_GPIO_ENABLE_ERR_Pos = 0x1b + // Bit mask of BTLC_GPIO_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_BTLC_GPIO_ENABLE_ERR_Msk = 0x18000000 + // Position of POWERGLITCH_EN_ERR field. + EFUSE_RD_REPEAT_ERR0_POWERGLITCH_EN_ERR_Pos = 0x1d + // Bit mask of POWERGLITCH_EN_ERR field. + EFUSE_RD_REPEAT_ERR0_POWERGLITCH_EN_ERR_Msk = 0x20000000 + // Bit POWERGLITCH_EN_ERR. + EFUSE_RD_REPEAT_ERR0_POWERGLITCH_EN_ERR = 0x20000000 + // Position of POWER_GLITCH_DSENSE_ERR field. + EFUSE_RD_REPEAT_ERR0_POWER_GLITCH_DSENSE_ERR_Pos = 0x1e + // Bit mask of POWER_GLITCH_DSENSE_ERR field. + EFUSE_RD_REPEAT_ERR0_POWER_GLITCH_DSENSE_ERR_Msk = 0xc0000000 + + // RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. + // Position of RPT4_RESERVED2_ERR field. + EFUSE_RD_REPEAT_ERR1_RPT4_RESERVED2_ERR_Pos = 0x0 + // Bit mask of RPT4_RESERVED2_ERR field. + EFUSE_RD_REPEAT_ERR1_RPT4_RESERVED2_ERR_Msk = 0xffff + // Position of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR = 0x800000 + // Position of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Msk = 0xf000000 + // Position of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. + // Position of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Msk = 0xf + // Position of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Msk = 0xf0 + // Position of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Msk = 0xf00 + // Position of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Pos = 0xc + // Bit mask of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Msk = 0xf000 + // Position of RPT4_RESERVED3_ERR field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED3_ERR_Pos = 0x10 + // Bit mask of RPT4_RESERVED3_ERR field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED3_ERR_Msk = 0xf0000 + // Position of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Msk = 0x100000 + // Bit SECURE_BOOT_EN_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR = 0x200000 + // Position of RPT4_RESERVED0_ERR field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED0_ERR_Pos = 0x16 + // Bit mask of RPT4_RESERVED0_ERR field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED0_ERR_Msk = 0xfc00000 + // Position of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Pos = 0x1c + // Bit mask of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. + // Position of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR = 0x1 + // Position of DIS_LEGACY_SPI_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR_Pos = 0x1 + // Bit mask of DIS_LEGACY_SPI_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR_Msk = 0x2 + // Bit DIS_LEGACY_SPI_BOOT_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR = 0x2 + // Position of UART_PRINT_CHANNEL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR_Pos = 0x2 + // Bit mask of UART_PRINT_CHANNEL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR_Msk = 0x4 + // Bit UART_PRINT_CHANNEL_ERR. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR = 0x4 + // Position of FLASH_ECC_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_MODE_ERR_Pos = 0x3 + // Bit mask of FLASH_ECC_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_MODE_ERR_Msk = 0x8 + // Bit FLASH_ECC_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_MODE_ERR = 0x8 + // Position of DIS_USB_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR_Pos = 0x4 + // Bit mask of DIS_USB_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR_Msk = 0x10 + // Bit DIS_USB_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR = 0x20 + // Position of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Msk = 0xc0 + // Position of PIN_POWER_SELECTION_ERR field. + EFUSE_RD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR_Pos = 0x8 + // Bit mask of PIN_POWER_SELECTION_ERR field. + EFUSE_RD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR_Msk = 0x100 + // Bit PIN_POWER_SELECTION_ERR. + EFUSE_RD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR = 0x100 + // Position of FLASH_TYPE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_TYPE_ERR_Pos = 0x9 + // Bit mask of FLASH_TYPE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_TYPE_ERR_Msk = 0x200 + // Bit FLASH_TYPE_ERR. + EFUSE_RD_REPEAT_ERR3_FLASH_TYPE_ERR = 0x200 + // Position of FLASH_PAGE_SIZE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_PAGE_SIZE_ERR_Pos = 0xa + // Bit mask of FLASH_PAGE_SIZE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_PAGE_SIZE_ERR_Msk = 0xc00 + // Position of FLASH_ECC_EN_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_EN_ERR_Pos = 0xc + // Bit mask of FLASH_ECC_EN_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_EN_ERR_Msk = 0x1000 + // Bit FLASH_ECC_EN_ERR. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_EN_ERR = 0x1000 + // Position of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Pos = 0xd + // Bit mask of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Msk = 0x2000 + // Bit FORCE_SEND_RESUME_ERR. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR = 0x2000 + // Position of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Pos = 0xe + // Bit mask of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Msk = 0x3fffc000 + // Position of RPT4_RESERVED1_ERR field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED1_ERR_Pos = 0x1e + // Bit mask of RPT4_RESERVED1_ERR field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED1_ERR_Msk = 0xc0000000 + + // RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. + // Position of RPT4_RESERVED4_ERR field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_Pos = 0x0 + // Bit mask of RPT4_RESERVED4_ERR field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_Msk = 0xffffff + + // RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. + // Position of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Pos = 0x0 + // Bit mask of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Msk = 0x7 + // Position of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Pos = 0x3 + // Bit mask of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Msk = 0x8 + // Bit MAC_SPI_8M_FAIL. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL = 0x8 + // Position of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Pos = 0x4 + // Bit mask of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Msk = 0x70 + // Position of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Pos = 0x7 + // Bit mask of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Msk = 0x80 + // Bit SYS_PART1_FAIL. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL = 0x80 + // Position of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Pos = 0x8 + // Bit mask of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Msk = 0x700 + // Position of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Pos = 0xb + // Bit mask of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Msk = 0x800 + // Bit USR_DATA_FAIL. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL = 0x800 + // Position of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Pos = 0xc + // Bit mask of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Msk = 0x7000 + // Position of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Pos = 0xf + // Bit mask of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Msk = 0x8000 + // Bit KEY0_FAIL. + EFUSE_RD_RS_ERR0_KEY0_FAIL = 0x8000 + // Position of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Pos = 0x10 + // Bit mask of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Msk = 0x70000 + // Position of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Pos = 0x13 + // Bit mask of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Msk = 0x80000 + // Bit KEY1_FAIL. + EFUSE_RD_RS_ERR0_KEY1_FAIL = 0x80000 + // Position of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Pos = 0x14 + // Bit mask of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Msk = 0x700000 + // Position of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Pos = 0x17 + // Bit mask of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Msk = 0x800000 + // Bit KEY2_FAIL. + EFUSE_RD_RS_ERR0_KEY2_FAIL = 0x800000 + // Position of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Pos = 0x18 + // Bit mask of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Msk = 0x7000000 + // Position of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Pos = 0x1b + // Bit mask of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Msk = 0x8000000 + // Bit KEY3_FAIL. + EFUSE_RD_RS_ERR0_KEY3_FAIL = 0x8000000 + // Position of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Pos = 0x1c + // Bit mask of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Msk = 0x70000000 + // Position of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Pos = 0x1f + // Bit mask of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Msk = 0x80000000 + // Bit KEY4_FAIL. + EFUSE_RD_RS_ERR0_KEY4_FAIL = 0x80000000 + + // RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. + // Position of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Pos = 0x0 + // Bit mask of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Msk = 0x7 + // Position of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Pos = 0x3 + // Bit mask of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Msk = 0x8 + // Bit KEY5_FAIL. + EFUSE_RD_RS_ERR1_KEY5_FAIL = 0x8 + // Position of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Pos = 0x4 + // Bit mask of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Msk = 0x70 + // Position of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Pos = 0x7 + // Bit mask of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Msk = 0x80 + // Bit SYS_PART2_FAIL. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL = 0x80 + + // CLK: eFuse clock configuration register. + // Position of EFUSE_MEM_FORCE_PD field. + EFUSE_CLK_EFUSE_MEM_FORCE_PD_Pos = 0x0 + // Bit mask of EFUSE_MEM_FORCE_PD field. + EFUSE_CLK_EFUSE_MEM_FORCE_PD_Msk = 0x1 + // Bit EFUSE_MEM_FORCE_PD. + EFUSE_CLK_EFUSE_MEM_FORCE_PD = 0x1 + // Position of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + EFUSE_CLK_MEM_CLK_FORCE_ON = 0x2 + // Position of EFUSE_MEM_FORCE_PU field. + EFUSE_CLK_EFUSE_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of EFUSE_MEM_FORCE_PU field. + EFUSE_CLK_EFUSE_MEM_FORCE_PU_Msk = 0x4 + // Bit EFUSE_MEM_FORCE_PU. + EFUSE_CLK_EFUSE_MEM_FORCE_PU = 0x4 + // Position of EN field. + EFUSE_CLK_EN_Pos = 0x10 + // Bit mask of EN field. + EFUSE_CLK_EN_Msk = 0x10000 + // Bit EN. + EFUSE_CLK_EN = 0x10000 + + // CONF: eFuse operation mode configuration register. + // Position of OP_CODE field. + EFUSE_CONF_OP_CODE_Pos = 0x0 + // Bit mask of OP_CODE field. + EFUSE_CONF_OP_CODE_Msk = 0xffff + + // STATUS: eFuse status register. + // Position of STATE field. + EFUSE_STATUS_STATE_Pos = 0x0 + // Bit mask of STATE field. + EFUSE_STATUS_STATE_Msk = 0xf + // Position of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Pos = 0x4 + // Bit mask of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Msk = 0x10 + // Bit OTP_LOAD_SW. + EFUSE_STATUS_OTP_LOAD_SW = 0x10 + // Position of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Pos = 0x5 + // Bit mask of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Msk = 0x20 + // Bit OTP_VDDQ_C_SYNC2. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2 = 0x20 + // Position of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Pos = 0x6 + // Bit mask of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Msk = 0x40 + // Bit OTP_STROBE_SW. + EFUSE_STATUS_OTP_STROBE_SW = 0x40 + // Position of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Pos = 0x7 + // Bit mask of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Msk = 0x80 + // Bit OTP_CSB_SW. + EFUSE_STATUS_OTP_CSB_SW = 0x80 + // Position of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Pos = 0x8 + // Bit mask of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Msk = 0x100 + // Bit OTP_PGENB_SW. + EFUSE_STATUS_OTP_PGENB_SW = 0x100 + // Position of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Pos = 0x9 + // Bit mask of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Msk = 0x200 + // Bit OTP_VDDQ_IS_SW. + EFUSE_STATUS_OTP_VDDQ_IS_SW = 0x200 + // Position of REPEAT_ERR_CNT field. + EFUSE_STATUS_REPEAT_ERR_CNT_Pos = 0xa + // Bit mask of REPEAT_ERR_CNT field. + EFUSE_STATUS_REPEAT_ERR_CNT_Msk = 0x3fc00 + + // CMD: eFuse command register. + // Position of READ_CMD field. + EFUSE_CMD_READ_CMD_Pos = 0x0 + // Bit mask of READ_CMD field. + EFUSE_CMD_READ_CMD_Msk = 0x1 + // Bit READ_CMD. + EFUSE_CMD_READ_CMD = 0x1 + // Position of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Pos = 0x1 + // Bit mask of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Msk = 0x2 + // Bit PGM_CMD. + EFUSE_CMD_PGM_CMD = 0x2 + // Position of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Pos = 0x2 + // Bit mask of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Msk = 0x3c + + // INT_RAW: eFuse raw interrupt register. + // Position of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Pos = 0x0 + // Bit mask of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Msk = 0x1 + // Bit READ_DONE_INT_RAW. + EFUSE_INT_RAW_READ_DONE_INT_RAW = 0x1 + // Position of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Pos = 0x1 + // Bit mask of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Msk = 0x2 + // Bit PGM_DONE_INT_RAW. + EFUSE_INT_RAW_PGM_DONE_INT_RAW = 0x2 + + // INT_ST: eFuse interrupt status register. + // Position of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Pos = 0x0 + // Bit mask of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Msk = 0x1 + // Bit READ_DONE_INT_ST. + EFUSE_INT_ST_READ_DONE_INT_ST = 0x1 + // Position of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Msk = 0x2 + // Bit PGM_DONE_INT_ST. + EFUSE_INT_ST_PGM_DONE_INT_ST = 0x2 + + // INT_ENA: eFuse interrupt enable register. + // Position of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Pos = 0x0 + // Bit mask of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Msk = 0x1 + // Bit READ_DONE_INT_ENA. + EFUSE_INT_ENA_READ_DONE_INT_ENA = 0x1 + // Position of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Msk = 0x2 + // Bit PGM_DONE_INT_ENA. + EFUSE_INT_ENA_PGM_DONE_INT_ENA = 0x2 + + // INT_CLR: eFuse interrupt clear register. + // Position of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Pos = 0x0 + // Bit mask of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Msk = 0x1 + // Bit READ_DONE_INT_CLR. + EFUSE_INT_CLR_READ_DONE_INT_CLR = 0x1 + // Position of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Pos = 0x1 + // Bit mask of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Msk = 0x2 + // Bit PGM_DONE_INT_CLR. + EFUSE_INT_CLR_PGM_DONE_INT_CLR = 0x2 + + // DAC_CONF: Controls the eFuse programming voltage. + // Position of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Pos = 0x0 + // Bit mask of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Msk = 0xff + // Position of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Pos = 0x8 + // Bit mask of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Msk = 0x100 + // Bit DAC_CLK_PAD_SEL. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL = 0x100 + // Position of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Pos = 0x9 + // Bit mask of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Msk = 0x1fe00 + // Position of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Pos = 0x11 + // Bit mask of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Msk = 0x20000 + // Bit OE_CLR. + EFUSE_DAC_CONF_OE_CLR = 0x20000 + + // RD_TIM_CONF: Configures read timing parameters. + // Position of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Pos = 0x18 + // Bit mask of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Msk = 0xff000000 + + // WR_TIM_CONF1: Configuration register 1 of eFuse programming timing parameters. + // Position of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Pos = 0x8 + // Bit mask of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Msk = 0xffff00 + + // WR_TIM_CONF2: Configuration register 2 of eFuse programming timing parameters. + // Position of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Pos = 0x0 + // Bit mask of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Msk = 0xffff + + // DATE: eFuse version register. + // Position of DATE field. + EFUSE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EFUSE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for EXTMEM: External Memory +const ( + // ICACHE_CTRL: This description will be updated in the near future. + // Position of ICACHE_ENABLE field. + EXTMEM_ICACHE_CTRL_ICACHE_ENABLE_Pos = 0x0 + // Bit mask of ICACHE_ENABLE field. + EXTMEM_ICACHE_CTRL_ICACHE_ENABLE_Msk = 0x1 + // Bit ICACHE_ENABLE. + EXTMEM_ICACHE_CTRL_ICACHE_ENABLE = 0x1 + + // ICACHE_CTRL1: This description will be updated in the near future. + // Position of ICACHE_SHUT_IBUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_IBUS_Pos = 0x0 + // Bit mask of ICACHE_SHUT_IBUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_IBUS_Msk = 0x1 + // Bit ICACHE_SHUT_IBUS. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_IBUS = 0x1 + // Position of ICACHE_SHUT_DBUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_DBUS_Pos = 0x1 + // Bit mask of ICACHE_SHUT_DBUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_DBUS_Msk = 0x2 + // Bit ICACHE_SHUT_DBUS. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_DBUS = 0x2 + + // ICACHE_TAG_POWER_CTRL: This description will be updated in the near future. + // Position of ICACHE_TAG_MEM_FORCE_ON field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of ICACHE_TAG_MEM_FORCE_ON field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON_Msk = 0x1 + // Bit ICACHE_TAG_MEM_FORCE_ON. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON = 0x1 + // Position of ICACHE_TAG_MEM_FORCE_PD field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of ICACHE_TAG_MEM_FORCE_PD field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD_Msk = 0x2 + // Bit ICACHE_TAG_MEM_FORCE_PD. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD = 0x2 + // Position of ICACHE_TAG_MEM_FORCE_PU field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of ICACHE_TAG_MEM_FORCE_PU field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU_Msk = 0x4 + // Bit ICACHE_TAG_MEM_FORCE_PU. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU = 0x4 + + // ICACHE_PRELOCK_CTRL: This description will be updated in the near future. + // Position of ICACHE_PRELOCK_SCT0_EN field. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN_Pos = 0x0 + // Bit mask of ICACHE_PRELOCK_SCT0_EN field. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN_Msk = 0x1 + // Bit ICACHE_PRELOCK_SCT0_EN. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN = 0x1 + // Position of ICACHE_PRELOCK_SCT1_EN field. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN_Pos = 0x1 + // Bit mask of ICACHE_PRELOCK_SCT1_EN field. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN_Msk = 0x2 + // Bit ICACHE_PRELOCK_SCT1_EN. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN = 0x2 + + // ICACHE_PRELOCK_SCT0_ADDR: This description will be updated in the near future. + // Position of ICACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_ICACHE_PRELOCK_SCT0_ADDR_Pos = 0x0 + // Bit mask of ICACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_ICACHE_PRELOCK_SCT0_ADDR_Msk = 0xffffffff + + // ICACHE_PRELOCK_SCT1_ADDR: This description will be updated in the near future. + // Position of ICACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_ICACHE_PRELOCK_SCT1_ADDR_Pos = 0x0 + // Bit mask of ICACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_ICACHE_PRELOCK_SCT1_ADDR_Msk = 0xffffffff + + // ICACHE_PRELOCK_SCT_SIZE: This description will be updated in the near future. + // Position of ICACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_ICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT1_SIZE_Pos = 0x0 + // Bit mask of ICACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_ICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT1_SIZE_Msk = 0xffff + // Position of ICACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_ICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT0_SIZE_Pos = 0x10 + // Bit mask of ICACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_ICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT0_SIZE_Msk = 0xffff0000 + + // ICACHE_LOCK_CTRL: This description will be updated in the near future. + // Position of ICACHE_LOCK_ENA field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_ENA_Pos = 0x0 + // Bit mask of ICACHE_LOCK_ENA field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_ENA_Msk = 0x1 + // Bit ICACHE_LOCK_ENA. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_ENA = 0x1 + // Position of ICACHE_UNLOCK_ENA field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA_Pos = 0x1 + // Bit mask of ICACHE_UNLOCK_ENA field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA_Msk = 0x2 + // Bit ICACHE_UNLOCK_ENA. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA = 0x2 + // Position of ICACHE_LOCK_DONE field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_DONE_Pos = 0x2 + // Bit mask of ICACHE_LOCK_DONE field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_DONE_Msk = 0x4 + // Bit ICACHE_LOCK_DONE. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_DONE = 0x4 + + // ICACHE_LOCK_ADDR: This description will be updated in the near future. + // Position of ICACHE_LOCK_ADDR field. + EXTMEM_ICACHE_LOCK_ADDR_ICACHE_LOCK_ADDR_Pos = 0x0 + // Bit mask of ICACHE_LOCK_ADDR field. + EXTMEM_ICACHE_LOCK_ADDR_ICACHE_LOCK_ADDR_Msk = 0xffffffff + + // ICACHE_LOCK_SIZE: This description will be updated in the near future. + // Position of ICACHE_LOCK_SIZE field. + EXTMEM_ICACHE_LOCK_SIZE_ICACHE_LOCK_SIZE_Pos = 0x0 + // Bit mask of ICACHE_LOCK_SIZE field. + EXTMEM_ICACHE_LOCK_SIZE_ICACHE_LOCK_SIZE_Msk = 0xffff + + // ICACHE_SYNC_CTRL: This description will be updated in the near future. + // Position of ICACHE_INVALIDATE_ENA field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA_Pos = 0x0 + // Bit mask of ICACHE_INVALIDATE_ENA field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA_Msk = 0x1 + // Bit ICACHE_INVALIDATE_ENA. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA = 0x1 + // Position of ICACHE_SYNC_DONE field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_SYNC_DONE_Pos = 0x1 + // Bit mask of ICACHE_SYNC_DONE field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_SYNC_DONE_Msk = 0x2 + // Bit ICACHE_SYNC_DONE. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_SYNC_DONE = 0x2 + + // ICACHE_SYNC_ADDR: This description will be updated in the near future. + // Position of ICACHE_SYNC_ADDR field. + EXTMEM_ICACHE_SYNC_ADDR_ICACHE_SYNC_ADDR_Pos = 0x0 + // Bit mask of ICACHE_SYNC_ADDR field. + EXTMEM_ICACHE_SYNC_ADDR_ICACHE_SYNC_ADDR_Msk = 0xffffffff + + // ICACHE_SYNC_SIZE: This description will be updated in the near future. + // Position of ICACHE_SYNC_SIZE field. + EXTMEM_ICACHE_SYNC_SIZE_ICACHE_SYNC_SIZE_Pos = 0x0 + // Bit mask of ICACHE_SYNC_SIZE field. + EXTMEM_ICACHE_SYNC_SIZE_ICACHE_SYNC_SIZE_Msk = 0x7fffff + + // ICACHE_PRELOAD_CTRL: This description will be updated in the near future. + // Position of ICACHE_PRELOAD_ENA field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_ENA field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA_Msk = 0x1 + // Bit ICACHE_PRELOAD_ENA. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA = 0x1 + // Position of ICACHE_PRELOAD_DONE field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_DONE field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE_Msk = 0x2 + // Bit ICACHE_PRELOAD_DONE. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE = 0x2 + // Position of ICACHE_PRELOAD_ORDER field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER_Pos = 0x2 + // Bit mask of ICACHE_PRELOAD_ORDER field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER_Msk = 0x4 + // Bit ICACHE_PRELOAD_ORDER. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER = 0x4 + + // ICACHE_PRELOAD_ADDR: This description will be updated in the near future. + // Position of ICACHE_PRELOAD_ADDR field. + EXTMEM_ICACHE_PRELOAD_ADDR_ICACHE_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_ADDR field. + EXTMEM_ICACHE_PRELOAD_ADDR_ICACHE_PRELOAD_ADDR_Msk = 0xffffffff + + // ICACHE_PRELOAD_SIZE: This description will be updated in the near future. + // Position of ICACHE_PRELOAD_SIZE field. + EXTMEM_ICACHE_PRELOAD_SIZE_ICACHE_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_SIZE field. + EXTMEM_ICACHE_PRELOAD_SIZE_ICACHE_PRELOAD_SIZE_Msk = 0xffff + + // ICACHE_AUTOLOAD_CTRL: This description will be updated in the near future. + // Position of ICACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA_Msk = 0x1 + // Bit ICACHE_AUTOLOAD_SCT0_ENA. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA = 0x1 + // Position of ICACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA_Pos = 0x1 + // Bit mask of ICACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA_Msk = 0x2 + // Bit ICACHE_AUTOLOAD_SCT1_ENA. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA = 0x2 + // Position of ICACHE_AUTOLOAD_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA_Pos = 0x2 + // Bit mask of ICACHE_AUTOLOAD_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA_Msk = 0x4 + // Bit ICACHE_AUTOLOAD_ENA. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA = 0x4 + // Position of ICACHE_AUTOLOAD_DONE field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE_Pos = 0x3 + // Bit mask of ICACHE_AUTOLOAD_DONE field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE_Msk = 0x8 + // Bit ICACHE_AUTOLOAD_DONE. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE = 0x8 + // Position of ICACHE_AUTOLOAD_ORDER field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER_Pos = 0x4 + // Bit mask of ICACHE_AUTOLOAD_ORDER field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER_Msk = 0x10 + // Bit ICACHE_AUTOLOAD_ORDER. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER = 0x10 + // Position of ICACHE_AUTOLOAD_RQST field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_RQST_Pos = 0x5 + // Bit mask of ICACHE_AUTOLOAD_RQST field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_RQST_Msk = 0x60 + + // ICACHE_AUTOLOAD_SCT0_ADDR: This description will be updated in the near future. + // Position of ICACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_ICACHE_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_ICACHE_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // ICACHE_AUTOLOAD_SCT0_SIZE: This description will be updated in the near future. + // Position of ICACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_ICACHE_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_ICACHE_AUTOLOAD_SCT0_SIZE_Msk = 0x7ffffff + + // ICACHE_AUTOLOAD_SCT1_ADDR: This description will be updated in the near future. + // Position of ICACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_ICACHE_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_ICACHE_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // ICACHE_AUTOLOAD_SCT1_SIZE: This description will be updated in the near future. + // Position of ICACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_ICACHE_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_ICACHE_AUTOLOAD_SCT1_SIZE_Msk = 0x7ffffff + + // IBUS_TO_FLASH_START_VADDR: This description will be updated in the near future. + // Position of IBUS_TO_FLASH_START_VADDR field. + EXTMEM_IBUS_TO_FLASH_START_VADDR_IBUS_TO_FLASH_START_VADDR_Pos = 0x0 + // Bit mask of IBUS_TO_FLASH_START_VADDR field. + EXTMEM_IBUS_TO_FLASH_START_VADDR_IBUS_TO_FLASH_START_VADDR_Msk = 0xffffffff + + // IBUS_TO_FLASH_END_VADDR: This description will be updated in the near future. + // Position of IBUS_TO_FLASH_END_VADDR field. + EXTMEM_IBUS_TO_FLASH_END_VADDR_IBUS_TO_FLASH_END_VADDR_Pos = 0x0 + // Bit mask of IBUS_TO_FLASH_END_VADDR field. + EXTMEM_IBUS_TO_FLASH_END_VADDR_IBUS_TO_FLASH_END_VADDR_Msk = 0xffffffff + + // DBUS_TO_FLASH_START_VADDR: This description will be updated in the near future. + // Position of DBUS_TO_FLASH_START_VADDR field. + EXTMEM_DBUS_TO_FLASH_START_VADDR_DBUS_TO_FLASH_START_VADDR_Pos = 0x0 + // Bit mask of DBUS_TO_FLASH_START_VADDR field. + EXTMEM_DBUS_TO_FLASH_START_VADDR_DBUS_TO_FLASH_START_VADDR_Msk = 0xffffffff + + // DBUS_TO_FLASH_END_VADDR: This description will be updated in the near future. + // Position of DBUS_TO_FLASH_END_VADDR field. + EXTMEM_DBUS_TO_FLASH_END_VADDR_DBUS_TO_FLASH_END_VADDR_Pos = 0x0 + // Bit mask of DBUS_TO_FLASH_END_VADDR field. + EXTMEM_DBUS_TO_FLASH_END_VADDR_DBUS_TO_FLASH_END_VADDR_Msk = 0xffffffff + + // CACHE_ACS_CNT_CLR: This description will be updated in the near future. + // Position of IBUS_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR_Pos = 0x0 + // Bit mask of IBUS_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR_Msk = 0x1 + // Bit IBUS_ACS_CNT_CLR. + EXTMEM_CACHE_ACS_CNT_CLR_IBUS_ACS_CNT_CLR = 0x1 + // Position of DBUS_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR_Pos = 0x1 + // Bit mask of DBUS_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR_Msk = 0x2 + // Bit DBUS_ACS_CNT_CLR. + EXTMEM_CACHE_ACS_CNT_CLR_DBUS_ACS_CNT_CLR = 0x2 + + // IBUS_ACS_MISS_CNT: This description will be updated in the near future. + // Position of IBUS_ACS_MISS_CNT field. + EXTMEM_IBUS_ACS_MISS_CNT_IBUS_ACS_MISS_CNT_Pos = 0x0 + // Bit mask of IBUS_ACS_MISS_CNT field. + EXTMEM_IBUS_ACS_MISS_CNT_IBUS_ACS_MISS_CNT_Msk = 0xffffffff + + // IBUS_ACS_CNT: This description will be updated in the near future. + // Position of IBUS_ACS_CNT field. + EXTMEM_IBUS_ACS_CNT_IBUS_ACS_CNT_Pos = 0x0 + // Bit mask of IBUS_ACS_CNT field. + EXTMEM_IBUS_ACS_CNT_IBUS_ACS_CNT_Msk = 0xffffffff + + // DBUS_ACS_FLASH_MISS_CNT: This description will be updated in the near future. + // Position of DBUS_ACS_FLASH_MISS_CNT field. + EXTMEM_DBUS_ACS_FLASH_MISS_CNT_DBUS_ACS_FLASH_MISS_CNT_Pos = 0x0 + // Bit mask of DBUS_ACS_FLASH_MISS_CNT field. + EXTMEM_DBUS_ACS_FLASH_MISS_CNT_DBUS_ACS_FLASH_MISS_CNT_Msk = 0xffffffff + + // DBUS_ACS_CNT: This description will be updated in the near future. + // Position of DBUS_ACS_CNT field. + EXTMEM_DBUS_ACS_CNT_DBUS_ACS_CNT_Pos = 0x0 + // Bit mask of DBUS_ACS_CNT field. + EXTMEM_DBUS_ACS_CNT_DBUS_ACS_CNT_Msk = 0xffffffff + + // CACHE_ILG_INT_ENA: This description will be updated in the near future. + // Position of ICACHE_SYNC_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA_Pos = 0x0 + // Bit mask of ICACHE_SYNC_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA_Msk = 0x1 + // Bit ICACHE_SYNC_OP_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA = 0x1 + // Position of ICACHE_PRELOAD_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA_Msk = 0x2 + // Bit ICACHE_PRELOAD_OP_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA = 0x2 + // Position of MMU_ENTRY_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA_Pos = 0x5 + // Bit mask of MMU_ENTRY_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA_Msk = 0x20 + // Bit MMU_ENTRY_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA = 0x20 + // Position of IBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA_Pos = 0x7 + // Bit mask of IBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA_Msk = 0x80 + // Bit IBUS_CNT_OVF_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA = 0x80 + // Position of DBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA_Pos = 0x8 + // Bit mask of DBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA_Msk = 0x100 + // Bit DBUS_CNT_OVF_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA = 0x100 + + // CACHE_ILG_INT_CLR: This description will be updated in the near future. + // Position of ICACHE_SYNC_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR_Pos = 0x0 + // Bit mask of ICACHE_SYNC_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR_Msk = 0x1 + // Bit ICACHE_SYNC_OP_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR = 0x1 + // Position of ICACHE_PRELOAD_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR_Msk = 0x2 + // Bit ICACHE_PRELOAD_OP_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR = 0x2 + // Position of MMU_ENTRY_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR_Pos = 0x5 + // Bit mask of MMU_ENTRY_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR_Msk = 0x20 + // Bit MMU_ENTRY_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR = 0x20 + // Position of IBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR_Pos = 0x7 + // Bit mask of IBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR_Msk = 0x80 + // Bit IBUS_CNT_OVF_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR = 0x80 + // Position of DBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR_Pos = 0x8 + // Bit mask of DBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR_Msk = 0x100 + // Bit DBUS_CNT_OVF_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR = 0x100 + + // CACHE_ILG_INT_ST: This description will be updated in the near future. + // Position of ICACHE_SYNC_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST_Pos = 0x0 + // Bit mask of ICACHE_SYNC_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST_Msk = 0x1 + // Bit ICACHE_SYNC_OP_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST = 0x1 + // Position of ICACHE_PRELOAD_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST_Msk = 0x2 + // Bit ICACHE_PRELOAD_OP_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST = 0x2 + // Position of MMU_ENTRY_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST_Pos = 0x5 + // Bit mask of MMU_ENTRY_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST_Msk = 0x20 + // Bit MMU_ENTRY_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST = 0x20 + // Position of IBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST_Pos = 0x7 + // Bit mask of IBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST_Msk = 0x80 + // Bit IBUS_ACS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST = 0x80 + // Position of IBUS_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST_Pos = 0x8 + // Bit mask of IBUS_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST_Msk = 0x100 + // Bit IBUS_ACS_MISS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST = 0x100 + // Position of DBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST_Pos = 0x9 + // Bit mask of DBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST_Msk = 0x200 + // Bit DBUS_ACS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST = 0x200 + // Position of DBUS_ACS_FLASH_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_Pos = 0xa + // Bit mask of DBUS_ACS_FLASH_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_Msk = 0x400 + // Bit DBUS_ACS_FLASH_MISS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST = 0x400 + + // CORE0_ACS_CACHE_INT_ENA: This description will be updated in the near future. + // Position of CORE0_IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA_Pos = 0x0 + // Bit mask of CORE0_IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA_Msk = 0x1 + // Bit CORE0_IBUS_ACS_MSK_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA = 0x1 + // Position of CORE0_IBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA_Pos = 0x1 + // Bit mask of CORE0_IBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA_Msk = 0x2 + // Bit CORE0_IBUS_WR_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA = 0x2 + // Position of CORE0_IBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA_Pos = 0x2 + // Bit mask of CORE0_IBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA_Msk = 0x4 + // Bit CORE0_IBUS_REJECT_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA = 0x4 + // Position of CORE0_DBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA_Pos = 0x3 + // Bit mask of CORE0_DBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA_Msk = 0x8 + // Bit CORE0_DBUS_ACS_MSK_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_IC_INT_ENA = 0x8 + // Position of CORE0_DBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA_Pos = 0x4 + // Bit mask of CORE0_DBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA_Msk = 0x10 + // Bit CORE0_DBUS_REJECT_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA = 0x10 + // Position of CORE0_DBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA_Pos = 0x5 + // Bit mask of CORE0_DBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA_Msk = 0x20 + // Bit CORE0_DBUS_WR_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_WR_IC_INT_ENA = 0x20 + + // CORE0_ACS_CACHE_INT_CLR: This description will be updated in the near future. + // Position of CORE0_IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR_Pos = 0x0 + // Bit mask of CORE0_IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR_Msk = 0x1 + // Bit CORE0_IBUS_ACS_MSK_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR = 0x1 + // Position of CORE0_IBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR_Pos = 0x1 + // Bit mask of CORE0_IBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR_Msk = 0x2 + // Bit CORE0_IBUS_WR_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR = 0x2 + // Position of CORE0_IBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR_Pos = 0x2 + // Bit mask of CORE0_IBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR_Msk = 0x4 + // Bit CORE0_IBUS_REJECT_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR = 0x4 + // Position of CORE0_DBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR_Pos = 0x3 + // Bit mask of CORE0_DBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR_Msk = 0x8 + // Bit CORE0_DBUS_ACS_MSK_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_IC_INT_CLR = 0x8 + // Position of CORE0_DBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR_Pos = 0x4 + // Bit mask of CORE0_DBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR_Msk = 0x10 + // Bit CORE0_DBUS_REJECT_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR = 0x10 + // Position of CORE0_DBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR_Pos = 0x5 + // Bit mask of CORE0_DBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR_Msk = 0x20 + // Bit CORE0_DBUS_WR_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_WR_IC_INT_CLR = 0x20 + + // CORE0_ACS_CACHE_INT_ST: This description will be updated in the near future. + // Position of CORE0_IBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST_Pos = 0x0 + // Bit mask of CORE0_IBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST_Msk = 0x1 + // Bit CORE0_IBUS_ACS_MSK_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST = 0x1 + // Position of CORE0_IBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST_Pos = 0x1 + // Bit mask of CORE0_IBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST_Msk = 0x2 + // Bit CORE0_IBUS_WR_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST = 0x2 + // Position of CORE0_IBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST_Pos = 0x2 + // Bit mask of CORE0_IBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST_Msk = 0x4 + // Bit CORE0_IBUS_REJECT_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST = 0x4 + // Position of CORE0_DBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST_Pos = 0x3 + // Bit mask of CORE0_DBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST_Msk = 0x8 + // Bit CORE0_DBUS_ACS_MSK_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_ICACHE_ST = 0x8 + // Position of CORE0_DBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST_Pos = 0x4 + // Bit mask of CORE0_DBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST_Msk = 0x10 + // Bit CORE0_DBUS_REJECT_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST = 0x10 + // Position of CORE0_DBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST_Pos = 0x5 + // Bit mask of CORE0_DBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST_Msk = 0x20 + // Bit CORE0_DBUS_WR_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_WR_ICACHE_ST = 0x20 + + // CORE0_DBUS_REJECT_ST: This description will be updated in the near future. + // Position of CORE0_DBUS_ATTR field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR_Pos = 0x0 + // Bit mask of CORE0_DBUS_ATTR field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR_Msk = 0x7 + // Position of CORE0_DBUS_WORLD field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD_Pos = 0x3 + // Bit mask of CORE0_DBUS_WORLD field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD_Msk = 0x8 + // Bit CORE0_DBUS_WORLD. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD = 0x8 + + // CORE0_DBUS_REJECT_VADDR: This description will be updated in the near future. + // Position of CORE0_DBUS_VADDR field. + EXTMEM_CORE0_DBUS_REJECT_VADDR_CORE0_DBUS_VADDR_Pos = 0x0 + // Bit mask of CORE0_DBUS_VADDR field. + EXTMEM_CORE0_DBUS_REJECT_VADDR_CORE0_DBUS_VADDR_Msk = 0xffffffff + + // CORE0_IBUS_REJECT_ST: This description will be updated in the near future. + // Position of CORE0_IBUS_ATTR field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR_Pos = 0x0 + // Bit mask of CORE0_IBUS_ATTR field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR_Msk = 0x7 + // Position of CORE0_IBUS_WORLD field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD_Pos = 0x3 + // Bit mask of CORE0_IBUS_WORLD field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD_Msk = 0x8 + // Bit CORE0_IBUS_WORLD. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD = 0x8 + + // CORE0_IBUS_REJECT_VADDR: This description will be updated in the near future. + // Position of CORE0_IBUS_VADDR field. + EXTMEM_CORE0_IBUS_REJECT_VADDR_CORE0_IBUS_VADDR_Pos = 0x0 + // Bit mask of CORE0_IBUS_VADDR field. + EXTMEM_CORE0_IBUS_REJECT_VADDR_CORE0_IBUS_VADDR_Msk = 0xffffffff + + // CACHE_MMU_FAULT_CONTENT: This description will be updated in the near future. + // Position of CACHE_MMU_FAULT_CONTENT field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CONTENT_Pos = 0x0 + // Bit mask of CACHE_MMU_FAULT_CONTENT field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CONTENT_Msk = 0x3ff + // Position of CACHE_MMU_FAULT_CODE field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE_Pos = 0xa + // Bit mask of CACHE_MMU_FAULT_CODE field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE_Msk = 0x3c00 + + // CACHE_MMU_FAULT_VADDR: This description will be updated in the near future. + // Position of CACHE_MMU_FAULT_VADDR field. + EXTMEM_CACHE_MMU_FAULT_VADDR_CACHE_MMU_FAULT_VADDR_Pos = 0x0 + // Bit mask of CACHE_MMU_FAULT_VADDR field. + EXTMEM_CACHE_MMU_FAULT_VADDR_CACHE_MMU_FAULT_VADDR_Msk = 0xffffffff + + // CACHE_WRAP_AROUND_CTRL: This description will be updated in the near future. + // Position of CACHE_FLASH_WRAP_AROUND field. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND_Pos = 0x0 + // Bit mask of CACHE_FLASH_WRAP_AROUND field. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND_Msk = 0x1 + // Bit CACHE_FLASH_WRAP_AROUND. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND = 0x1 + + // CACHE_MMU_POWER_CTRL: This description will be updated in the near future. + // Position of CACHE_MMU_MEM_FORCE_ON field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of CACHE_MMU_MEM_FORCE_ON field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON_Msk = 0x1 + // Bit CACHE_MMU_MEM_FORCE_ON. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON = 0x1 + // Position of CACHE_MMU_MEM_FORCE_PD field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of CACHE_MMU_MEM_FORCE_PD field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD_Msk = 0x2 + // Bit CACHE_MMU_MEM_FORCE_PD. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD = 0x2 + // Position of CACHE_MMU_MEM_FORCE_PU field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of CACHE_MMU_MEM_FORCE_PU field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU_Msk = 0x4 + // Bit CACHE_MMU_MEM_FORCE_PU. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU = 0x4 + + // CACHE_STATE: This description will be updated in the near future. + // Position of ICACHE_STATE field. + EXTMEM_CACHE_STATE_ICACHE_STATE_Pos = 0x0 + // Bit mask of ICACHE_STATE field. + EXTMEM_CACHE_STATE_ICACHE_STATE_Msk = 0xfff + + // CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: This description will be updated in the near future. + // Position of RECORD_DISABLE_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT_Pos = 0x0 + // Bit mask of RECORD_DISABLE_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT_Msk = 0x1 + // Bit RECORD_DISABLE_DB_ENCRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT = 0x1 + // Position of RECORD_DISABLE_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT_Pos = 0x1 + // Bit mask of RECORD_DISABLE_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT_Msk = 0x2 + // Bit RECORD_DISABLE_G0CB_DECRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT = 0x2 + + // CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: This description will be updated in the near future. + // Position of CLK_FORCE_ON_MANUAL_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT_Pos = 0x0 + // Bit mask of CLK_FORCE_ON_MANUAL_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT_Msk = 0x1 + // Bit CLK_FORCE_ON_MANUAL_CRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT = 0x1 + // Position of CLK_FORCE_ON_AUTO_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT_Pos = 0x1 + // Bit mask of CLK_FORCE_ON_AUTO_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT_Msk = 0x2 + // Bit CLK_FORCE_ON_AUTO_CRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT = 0x2 + // Position of CLK_FORCE_ON_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT_Pos = 0x2 + // Bit mask of CLK_FORCE_ON_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT_Msk = 0x4 + // Bit CLK_FORCE_ON_CRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT = 0x4 + + // CACHE_PRELOAD_INT_CTRL: This description will be updated in the near future. + // Position of ICACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST_Msk = 0x1 + // Bit ICACHE_PRELOAD_INT_ST. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST = 0x1 + // Position of ICACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA_Msk = 0x2 + // Bit ICACHE_PRELOAD_INT_ENA. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA = 0x2 + // Position of ICACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR_Pos = 0x2 + // Bit mask of ICACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR_Msk = 0x4 + // Bit ICACHE_PRELOAD_INT_CLR. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR = 0x4 + + // CACHE_SYNC_INT_CTRL: This description will be updated in the near future. + // Position of ICACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST_Pos = 0x0 + // Bit mask of ICACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST_Msk = 0x1 + // Bit ICACHE_SYNC_INT_ST. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST = 0x1 + // Position of ICACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA_Pos = 0x1 + // Bit mask of ICACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA_Msk = 0x2 + // Bit ICACHE_SYNC_INT_ENA. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA = 0x2 + // Position of ICACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR_Pos = 0x2 + // Bit mask of ICACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR_Msk = 0x4 + // Bit ICACHE_SYNC_INT_CLR. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR = 0x4 + + // CACHE_MMU_OWNER: This description will be updated in the near future. + // Position of CACHE_MMU_OWNER field. + EXTMEM_CACHE_MMU_OWNER_CACHE_MMU_OWNER_Pos = 0x0 + // Bit mask of CACHE_MMU_OWNER field. + EXTMEM_CACHE_MMU_OWNER_CACHE_MMU_OWNER_Msk = 0xf + + // CACHE_CONF_MISC: This description will be updated in the near future. + // Position of CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_Pos = 0x0 + // Bit mask of CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_Msk = 0x1 + // Bit CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT = 0x1 + // Position of CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_Pos = 0x1 + // Bit mask of CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_Msk = 0x2 + // Bit CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT = 0x2 + // Position of CACHE_TRACE_ENA field. + EXTMEM_CACHE_CONF_MISC_CACHE_TRACE_ENA_Pos = 0x2 + // Bit mask of CACHE_TRACE_ENA field. + EXTMEM_CACHE_CONF_MISC_CACHE_TRACE_ENA_Msk = 0x4 + // Bit CACHE_TRACE_ENA. + EXTMEM_CACHE_CONF_MISC_CACHE_TRACE_ENA = 0x4 + + // ICACHE_FREEZE: This description will be updated in the near future. + // Position of ENA field. + EXTMEM_ICACHE_FREEZE_ENA_Pos = 0x0 + // Bit mask of ENA field. + EXTMEM_ICACHE_FREEZE_ENA_Msk = 0x1 + // Bit ENA. + EXTMEM_ICACHE_FREEZE_ENA = 0x1 + // Position of MODE field. + EXTMEM_ICACHE_FREEZE_MODE_Pos = 0x1 + // Bit mask of MODE field. + EXTMEM_ICACHE_FREEZE_MODE_Msk = 0x2 + // Bit MODE. + EXTMEM_ICACHE_FREEZE_MODE = 0x2 + // Position of DONE field. + EXTMEM_ICACHE_FREEZE_DONE_Pos = 0x2 + // Bit mask of DONE field. + EXTMEM_ICACHE_FREEZE_DONE_Msk = 0x4 + // Bit DONE. + EXTMEM_ICACHE_FREEZE_DONE = 0x4 + + // ICACHE_ATOMIC_OPERATE_ENA: This description will be updated in the near future. + // Position of ICACHE_ATOMIC_OPERATE_ENA field. + EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_ICACHE_ATOMIC_OPERATE_ENA_Pos = 0x0 + // Bit mask of ICACHE_ATOMIC_OPERATE_ENA field. + EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_ICACHE_ATOMIC_OPERATE_ENA_Msk = 0x1 + // Bit ICACHE_ATOMIC_OPERATE_ENA. + EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_ICACHE_ATOMIC_OPERATE_ENA = 0x1 + + // CACHE_REQUEST: This description will be updated in the near future. + // Position of BYPASS field. + EXTMEM_CACHE_REQUEST_BYPASS_Pos = 0x0 + // Bit mask of BYPASS field. + EXTMEM_CACHE_REQUEST_BYPASS_Msk = 0x1 + // Bit BYPASS. + EXTMEM_CACHE_REQUEST_BYPASS = 0x1 + + // IBUS_PMS_TBL_LOCK: This description will be updated in the near future. + // Position of IBUS_PMS_LOCK field. + EXTMEM_IBUS_PMS_TBL_LOCK_IBUS_PMS_LOCK_Pos = 0x0 + // Bit mask of IBUS_PMS_LOCK field. + EXTMEM_IBUS_PMS_TBL_LOCK_IBUS_PMS_LOCK_Msk = 0x1 + // Bit IBUS_PMS_LOCK. + EXTMEM_IBUS_PMS_TBL_LOCK_IBUS_PMS_LOCK = 0x1 + + // IBUS_PMS_TBL_BOUNDARY0: This description will be updated in the near future. + // Position of IBUS_PMS_BOUNDARY0 field. + EXTMEM_IBUS_PMS_TBL_BOUNDARY0_IBUS_PMS_BOUNDARY0_Pos = 0x0 + // Bit mask of IBUS_PMS_BOUNDARY0 field. + EXTMEM_IBUS_PMS_TBL_BOUNDARY0_IBUS_PMS_BOUNDARY0_Msk = 0xfff + + // IBUS_PMS_TBL_BOUNDARY1: This description will be updated in the near future. + // Position of IBUS_PMS_BOUNDARY1 field. + EXTMEM_IBUS_PMS_TBL_BOUNDARY1_IBUS_PMS_BOUNDARY1_Pos = 0x0 + // Bit mask of IBUS_PMS_BOUNDARY1 field. + EXTMEM_IBUS_PMS_TBL_BOUNDARY1_IBUS_PMS_BOUNDARY1_Msk = 0xfff + + // IBUS_PMS_TBL_BOUNDARY2: This description will be updated in the near future. + // Position of IBUS_PMS_BOUNDARY2 field. + EXTMEM_IBUS_PMS_TBL_BOUNDARY2_IBUS_PMS_BOUNDARY2_Pos = 0x0 + // Bit mask of IBUS_PMS_BOUNDARY2 field. + EXTMEM_IBUS_PMS_TBL_BOUNDARY2_IBUS_PMS_BOUNDARY2_Msk = 0xfff + + // IBUS_PMS_TBL_ATTR: This description will be updated in the near future. + // Position of IBUS_PMS_SCT1_ATTR field. + EXTMEM_IBUS_PMS_TBL_ATTR_IBUS_PMS_SCT1_ATTR_Pos = 0x0 + // Bit mask of IBUS_PMS_SCT1_ATTR field. + EXTMEM_IBUS_PMS_TBL_ATTR_IBUS_PMS_SCT1_ATTR_Msk = 0xf + // Position of IBUS_PMS_SCT2_ATTR field. + EXTMEM_IBUS_PMS_TBL_ATTR_IBUS_PMS_SCT2_ATTR_Pos = 0x4 + // Bit mask of IBUS_PMS_SCT2_ATTR field. + EXTMEM_IBUS_PMS_TBL_ATTR_IBUS_PMS_SCT2_ATTR_Msk = 0xf0 + + // DBUS_PMS_TBL_LOCK: This description will be updated in the near future. + // Position of DBUS_PMS_LOCK field. + EXTMEM_DBUS_PMS_TBL_LOCK_DBUS_PMS_LOCK_Pos = 0x0 + // Bit mask of DBUS_PMS_LOCK field. + EXTMEM_DBUS_PMS_TBL_LOCK_DBUS_PMS_LOCK_Msk = 0x1 + // Bit DBUS_PMS_LOCK. + EXTMEM_DBUS_PMS_TBL_LOCK_DBUS_PMS_LOCK = 0x1 + + // DBUS_PMS_TBL_BOUNDARY0: This description will be updated in the near future. + // Position of DBUS_PMS_BOUNDARY0 field. + EXTMEM_DBUS_PMS_TBL_BOUNDARY0_DBUS_PMS_BOUNDARY0_Pos = 0x0 + // Bit mask of DBUS_PMS_BOUNDARY0 field. + EXTMEM_DBUS_PMS_TBL_BOUNDARY0_DBUS_PMS_BOUNDARY0_Msk = 0xfff + + // DBUS_PMS_TBL_BOUNDARY1: This description will be updated in the near future. + // Position of DBUS_PMS_BOUNDARY1 field. + EXTMEM_DBUS_PMS_TBL_BOUNDARY1_DBUS_PMS_BOUNDARY1_Pos = 0x0 + // Bit mask of DBUS_PMS_BOUNDARY1 field. + EXTMEM_DBUS_PMS_TBL_BOUNDARY1_DBUS_PMS_BOUNDARY1_Msk = 0xfff + + // DBUS_PMS_TBL_BOUNDARY2: This description will be updated in the near future. + // Position of DBUS_PMS_BOUNDARY2 field. + EXTMEM_DBUS_PMS_TBL_BOUNDARY2_DBUS_PMS_BOUNDARY2_Pos = 0x0 + // Bit mask of DBUS_PMS_BOUNDARY2 field. + EXTMEM_DBUS_PMS_TBL_BOUNDARY2_DBUS_PMS_BOUNDARY2_Msk = 0xfff + + // DBUS_PMS_TBL_ATTR: This description will be updated in the near future. + // Position of DBUS_PMS_SCT1_ATTR field. + EXTMEM_DBUS_PMS_TBL_ATTR_DBUS_PMS_SCT1_ATTR_Pos = 0x0 + // Bit mask of DBUS_PMS_SCT1_ATTR field. + EXTMEM_DBUS_PMS_TBL_ATTR_DBUS_PMS_SCT1_ATTR_Msk = 0x3 + // Position of DBUS_PMS_SCT2_ATTR field. + EXTMEM_DBUS_PMS_TBL_ATTR_DBUS_PMS_SCT2_ATTR_Pos = 0x2 + // Bit mask of DBUS_PMS_SCT2_ATTR field. + EXTMEM_DBUS_PMS_TBL_ATTR_DBUS_PMS_SCT2_ATTR_Msk = 0xc + + // CLOCK_GATE: This description will be updated in the near future. + // Position of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + EXTMEM_CLOCK_GATE_CLK_EN = 0x1 + + // REG_DATE: This description will be updated in the near future. + // Position of DATE field. + EXTMEM_REG_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EXTMEM_REG_DATE_DATE_Msk = 0xfffffff +) + +// Constants for GPIO: General Purpose Input/Output +const ( + // BT_SELECT: GPIO bit select register + // Position of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Pos = 0x0 + // Bit mask of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Msk = 0xffffffff + + // OUT: GPIO output register + // Position of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Pos = 0x0 + // Bit mask of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Msk = 0x3ffffff + + // OUT_W1TS: GPIO output set register + // Position of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Pos = 0x0 + // Bit mask of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Msk = 0x3ffffff + + // OUT_W1TC: GPIO output clear register + // Position of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Pos = 0x0 + // Bit mask of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Msk = 0x3ffffff + + // SDIO_SELECT: GPIO sdio select register + // Position of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Pos = 0x0 + // Bit mask of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Msk = 0xff + + // ENABLE: GPIO output enable register + // Position of DATA field. + GPIO_ENABLE_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE_DATA_Msk = 0x3ffffff + + // ENABLE_W1TS: GPIO output enable set register + // Position of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Pos = 0x0 + // Bit mask of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Msk = 0x3ffffff + + // ENABLE_W1TC: GPIO output enable clear register + // Position of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0x0 + // Bit mask of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0x3ffffff + + // STRAP: pad strapping register + // Position of STRAPPING field. + GPIO_STRAP_STRAPPING_Pos = 0x0 + // Bit mask of STRAPPING field. + GPIO_STRAP_STRAPPING_Msk = 0xffff + + // IN: GPIO input register + // Position of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Msk = 0x3ffffff + + // STATUS: GPIO interrupt status register + // Position of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Msk = 0x3ffffff + + // STATUS_W1TS: GPIO interrupt status set register + // Position of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Pos = 0x0 + // Bit mask of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Msk = 0x3ffffff + + // STATUS_W1TC: GPIO interrupt status clear register + // Position of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Pos = 0x0 + // Bit mask of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Msk = 0x3ffffff + + // PCPU_INT: GPIO PRO_CPU interrupt status register + // Position of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Pos = 0x0 + // Bit mask of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Msk = 0x3ffffff + + // PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register + // Position of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Msk = 0x3ffffff + + // CPUSDIO_INT: GPIO CPUSDIO interrupt status register + // Position of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Pos = 0x0 + // Bit mask of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Msk = 0x3ffffff + + // PIN0: GPIO pin configuration register + // Position of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Pos = 0x0 + // Bit mask of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Msk = 0x3 + // Position of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + GPIO_PIN_PAD_DRIVER = 0x4 + // Position of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Pos = 0x3 + // Bit mask of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Msk = 0x18 + // Position of INT_TYPE field. + GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + GPIO_PIN_WAKEUP_ENABLE = 0x400 + // Position of CONFIG field. + GPIO_PIN_CONFIG_Pos = 0xb + // Bit mask of CONFIG field. + GPIO_PIN_CONFIG_Msk = 0x1800 + // Position of INT_ENA field. + GPIO_PIN_INT_ENA_Pos = 0xd + // Bit mask of INT_ENA field. + GPIO_PIN_INT_ENA_Msk = 0x3e000 + + // STATUS_NEXT: GPIO interrupt source register + // Position of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Pos = 0x0 + // Bit mask of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Msk = 0x3ffffff + + // FUNC0_IN_SEL_CFG: GPIO input function configuration register + // Position of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Pos = 0x0 + // Bit mask of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Msk = 0x1f + // Position of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Pos = 0x5 + // Bit mask of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Msk = 0x20 + // Bit IN_INV_SEL. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL = 0x20 + // Position of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Pos = 0x6 + // Bit mask of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Msk = 0x40 + // Bit SEL. + GPIO_FUNC_IN_SEL_CFG_SEL = 0x40 + + // FUNC0_OUT_SEL_CFG: GPIO output function select register + // Position of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Pos = 0x0 + // Bit mask of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Msk = 0xff + // Position of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Pos = 0x8 + // Bit mask of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Msk = 0x100 + // Bit INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL = 0x100 + // Position of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Pos = 0x9 + // Bit mask of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Msk = 0x200 + // Bit OEN_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL = 0x200 + // Position of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Pos = 0xa + // Bit mask of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Msk = 0x400 + // Bit OEN_INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL = 0x400 + + // CLOCK_GATE: GPIO clock gate register + // Position of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + GPIO_CLOCK_GATE_CLK_EN = 0x1 + + // REG_DATE: GPIO version register + // Position of REG_DATE field. + GPIO_REG_DATE_REG_DATE_Pos = 0x0 + // Bit mask of REG_DATE field. + GPIO_REG_DATE_REG_DATE_Msk = 0xfffffff +) + +// Constants for GPIO_SD: Sigma-Delta Modulation +const ( + // SIGMADELTA0: Duty Cycle Configure Register of SDM%s + // Position of SD0_IN field. + GPIOSD_SIGMADELTA_SD0_IN_Pos = 0x0 + // Bit mask of SD0_IN field. + GPIOSD_SIGMADELTA_SD0_IN_Msk = 0xff + // Position of SD0_PRESCALE field. + GPIOSD_SIGMADELTA_SD0_PRESCALE_Pos = 0x8 + // Bit mask of SD0_PRESCALE field. + GPIOSD_SIGMADELTA_SD0_PRESCALE_Msk = 0xff00 + + // SIGMADELTA_CG: Clock Gating Configure Register + // Position of CLK_EN field. + GPIOSD_SIGMADELTA_CG_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + GPIOSD_SIGMADELTA_CG_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + GPIOSD_SIGMADELTA_CG_CLK_EN = 0x80000000 + + // SIGMADELTA_MISC: MISC Register + // Position of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Pos = 0x1e + // Bit mask of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Msk = 0x40000000 + // Bit FUNCTION_CLK_EN. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN = 0x40000000 + // Position of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Pos = 0x1f + // Bit mask of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Msk = 0x80000000 + // Bit SPI_SWAP. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP = 0x80000000 + + // SIGMADELTA_VERSION: Version Control Register + // Position of GPIO_SD_DATE field. + GPIOSD_SIGMADELTA_VERSION_GPIO_SD_DATE_Pos = 0x0 + // Bit mask of GPIO_SD_DATE field. + GPIOSD_SIGMADELTA_VERSION_GPIO_SD_DATE_Msk = 0xfffffff +) + +// Constants for HMAC: HMAC (Hash-based Message Authentication Code) Accelerator +const ( + // SET_START: Process control register 0. + // Position of SET_START field. + HMAC_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + HMAC_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + HMAC_SET_START_SET_START = 0x1 + + // SET_PARA_PURPOSE: Configure purpose. + // Position of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Pos = 0x0 + // Bit mask of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Msk = 0xf + + // SET_PARA_KEY: Configure key. + // Position of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Pos = 0x0 + // Bit mask of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Msk = 0x7 + + // SET_PARA_FINISH: Finish initial configuration. + // Position of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Pos = 0x0 + // Bit mask of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Msk = 0x1 + // Bit SET_PARA_END. + HMAC_SET_PARA_FINISH_SET_PARA_END = 0x1 + + // SET_MESSAGE_ONE: Process control register 1. + // Position of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Pos = 0x0 + // Bit mask of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Msk = 0x1 + // Bit SET_TEXT_ONE. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE = 0x1 + + // SET_MESSAGE_ING: Process control register 2. + // Position of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Pos = 0x0 + // Bit mask of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Msk = 0x1 + // Bit SET_TEXT_ING. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING = 0x1 + + // SET_MESSAGE_END: Process control register 3. + // Position of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Pos = 0x0 + // Bit mask of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Msk = 0x1 + // Bit SET_TEXT_END. + HMAC_SET_MESSAGE_END_SET_TEXT_END = 0x1 + + // SET_RESULT_FINISH: Process control register 4. + // Position of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Pos = 0x0 + // Bit mask of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Msk = 0x1 + // Bit SET_RESULT_END. + HMAC_SET_RESULT_FINISH_SET_RESULT_END = 0x1 + + // SET_INVALIDATE_JTAG: Invalidate register 0. + // Position of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Pos = 0x0 + // Bit mask of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Msk = 0x1 + // Bit SET_INVALIDATE_JTAG. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG = 0x1 + + // SET_INVALIDATE_DS: Invalidate register 1. + // Position of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Pos = 0x0 + // Bit mask of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Msk = 0x1 + // Bit SET_INVALIDATE_DS. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS = 0x1 + + // QUERY_ERROR: Error register. + // Position of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Pos = 0x0 + // Bit mask of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Msk = 0x1 + // Bit QUERY_CHECK. + HMAC_QUERY_ERROR_QUERY_CHECK = 0x1 + + // QUERY_BUSY: Busy register. + // Position of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Pos = 0x0 + // Bit mask of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Msk = 0x1 + // Bit BUSY_STATE. + HMAC_QUERY_BUSY_BUSY_STATE = 0x1 + + // SET_MESSAGE_PAD: Process control register 5. + // Position of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Pos = 0x0 + // Bit mask of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Msk = 0x1 + // Bit SET_TEXT_PAD. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD = 0x1 + + // ONE_BLOCK: Process control register 6. + // Position of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Pos = 0x0 + // Bit mask of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Msk = 0x1 + // Bit SET_ONE_BLOCK. + HMAC_ONE_BLOCK_SET_ONE_BLOCK = 0x1 + + // SOFT_JTAG_CTRL: Jtag register 0. + // Position of SOFT_JTAG_CTRL field. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Pos = 0x0 + // Bit mask of SOFT_JTAG_CTRL field. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Msk = 0x1 + // Bit SOFT_JTAG_CTRL. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL = 0x1 + + // WR_JTAG: Jtag register 1. + // Position of WR_JTAG field. + HMAC_WR_JTAG_WR_JTAG_Pos = 0x0 + // Bit mask of WR_JTAG field. + HMAC_WR_JTAG_WR_JTAG_Msk = 0xffffffff +) + +// Constants for I2C0: I2C (Inter-Integrated Circuit) Controller 0 +const ( + // SCL_LOW_PERIOD: I2C_SCL_LOW_PERIOD_REG + // Position of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x1ff + + // CTR: I2C_CTR_REG + // Position of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + I2C_CTR_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + I2C_CTR_SCL_FORCE_OUT = 0x2 + // Position of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2 + // Bit mask of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4 + // Bit SAMPLE_SCL_LEVEL. + I2C_CTR_SAMPLE_SCL_LEVEL = 0x4 + // Position of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Pos = 0x3 + // Bit mask of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Msk = 0x8 + // Bit RX_FULL_ACK_LEVEL. + I2C_CTR_RX_FULL_ACK_LEVEL = 0x8 + // Position of MS_MODE field. + I2C_CTR_MS_MODE_Pos = 0x4 + // Bit mask of MS_MODE field. + I2C_CTR_MS_MODE_Msk = 0x10 + // Bit MS_MODE. + I2C_CTR_MS_MODE = 0x10 + // Position of TRANS_START field. + I2C_CTR_TRANS_START_Pos = 0x5 + // Bit mask of TRANS_START field. + I2C_CTR_TRANS_START_Msk = 0x20 + // Bit TRANS_START. + I2C_CTR_TRANS_START = 0x20 + // Position of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Msk = 0x40 + // Bit TX_LSB_FIRST. + I2C_CTR_TX_LSB_FIRST = 0x40 + // Position of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Msk = 0x80 + // Bit RX_LSB_FIRST. + I2C_CTR_RX_LSB_FIRST = 0x80 + // Position of CLK_EN field. + I2C_CTR_CLK_EN_Pos = 0x8 + // Bit mask of CLK_EN field. + I2C_CTR_CLK_EN_Msk = 0x100 + // Bit CLK_EN. + I2C_CTR_CLK_EN = 0x100 + // Position of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Pos = 0x9 + // Bit mask of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Msk = 0x200 + // Bit ARBITRATION_EN. + I2C_CTR_ARBITRATION_EN = 0x200 + // Position of FSM_RST field. + I2C_CTR_FSM_RST_Pos = 0xa + // Bit mask of FSM_RST field. + I2C_CTR_FSM_RST_Msk = 0x400 + // Bit FSM_RST. + I2C_CTR_FSM_RST = 0x400 + // Position of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Pos = 0xb + // Bit mask of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Msk = 0x800 + // Bit CONF_UPGATE. + I2C_CTR_CONF_UPGATE = 0x800 + // Position of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Pos = 0xc + // Bit mask of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Msk = 0x1000 + // Bit SLV_TX_AUTO_START_EN. + I2C_CTR_SLV_TX_AUTO_START_EN = 0x1000 + // Position of ADDR_10BIT_RW_CHECK_EN field. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Pos = 0xd + // Bit mask of ADDR_10BIT_RW_CHECK_EN field. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Msk = 0x2000 + // Bit ADDR_10BIT_RW_CHECK_EN. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN = 0x2000 + // Position of ADDR_BROADCASTING_EN field. + I2C_CTR_ADDR_BROADCASTING_EN_Pos = 0xe + // Bit mask of ADDR_BROADCASTING_EN field. + I2C_CTR_ADDR_BROADCASTING_EN_Msk = 0x4000 + // Bit ADDR_BROADCASTING_EN. + I2C_CTR_ADDR_BROADCASTING_EN = 0x4000 + + // SR: I2C_SR_REG + // Position of RESP_REC field. + I2C_SR_RESP_REC_Pos = 0x0 + // Bit mask of RESP_REC field. + I2C_SR_RESP_REC_Msk = 0x1 + // Bit RESP_REC. + I2C_SR_RESP_REC = 0x1 + // Position of SLAVE_RW field. + I2C_SR_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + I2C_SR_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + I2C_SR_SLAVE_RW = 0x2 + // Position of ARB_LOST field. + I2C_SR_ARB_LOST_Pos = 0x3 + // Bit mask of ARB_LOST field. + I2C_SR_ARB_LOST_Msk = 0x8 + // Bit ARB_LOST. + I2C_SR_ARB_LOST = 0x8 + // Position of BUS_BUSY field. + I2C_SR_BUS_BUSY_Pos = 0x4 + // Bit mask of BUS_BUSY field. + I2C_SR_BUS_BUSY_Msk = 0x10 + // Bit BUS_BUSY. + I2C_SR_BUS_BUSY = 0x10 + // Position of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Pos = 0x5 + // Bit mask of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Msk = 0x20 + // Bit SLAVE_ADDRESSED. + I2C_SR_SLAVE_ADDRESSED = 0x20 + // Position of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Pos = 0x8 + // Bit mask of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Msk = 0x3f00 + // Position of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Pos = 0xe + // Bit mask of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Msk = 0xc000 + // Position of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Pos = 0x12 + // Bit mask of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Msk = 0xfc0000 + // Position of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: I2C_TO_REG + // Position of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Pos = 0x0 + // Bit mask of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Msk = 0x1f + // Position of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Pos = 0x5 + // Bit mask of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Msk = 0x20 + // Bit TIME_OUT_EN. + I2C_TO_TIME_OUT_EN = 0x20 + + // SLAVE_ADDR: I2C_SLAVE_ADDR_REG + // Position of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // FIFO_ST: I2C_FIFO_ST_REG + // Position of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Pos = 0x0 + // Bit mask of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Msk = 0x1f + // Position of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Pos = 0x5 + // Bit mask of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Msk = 0x3e0 + // Position of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Pos = 0xa + // Bit mask of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Msk = 0x7c00 + // Position of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Pos = 0xf + // Bit mask of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Msk = 0xf8000 + // Position of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Pos = 0x16 + // Bit mask of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Msk = 0x3fc00000 + + // FIFO_CONF: I2C_FIFO_CONF_REG + // Position of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0x1f + // Position of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5 + // Bit mask of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x3e0 + // Position of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa + // Bit mask of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400 + // Bit NONFIFO_EN. + I2C_FIFO_CONF_NONFIFO_EN = 0x400 + // Position of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Pos = 0xb + // Bit mask of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Msk = 0x800 + // Bit FIFO_ADDR_CFG_EN. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN = 0x800 + // Position of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc + // Bit mask of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000 + // Bit RX_FIFO_RST. + I2C_FIFO_CONF_RX_FIFO_RST = 0x1000 + // Position of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd + // Bit mask of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000 + // Bit TX_FIFO_RST. + I2C_FIFO_CONF_TX_FIFO_RST = 0x2000 + // Position of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Pos = 0xe + // Bit mask of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000 + // Bit FIFO_PRT_EN. + I2C_FIFO_CONF_FIFO_PRT_EN = 0x4000 + + // DATA: I2C_FIFO_DATA_REG + // Position of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Pos = 0x0 + // Bit mask of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Msk = 0xff + + // INT_RAW: I2C_INT_RAW_REG + // Position of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Msk = 0x1 + // Bit RXFIFO_WM_INT_RAW. + I2C_INT_RAW_RXFIFO_WM_INT_RAW = 0x1 + // Position of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Msk = 0x2 + // Bit TXFIFO_WM_INT_RAW. + I2C_INT_RAW_TXFIFO_WM_INT_RAW = 0x2 + // Position of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4 + // Bit RXFIFO_OVF_INT_RAW. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4 + // Position of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3 + // Bit mask of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8 + // Bit END_DETECT_INT_RAW. + I2C_INT_RAW_END_DETECT_INT_RAW = 0x8 + // Position of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_RAW. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW = 0x10 + // Position of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_RAW. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20 + // Position of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_RAW. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW = 0x40 + // Position of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_RAW. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80 + // Position of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8 + // Bit mask of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100 + // Bit TIME_OUT_INT_RAW. + I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100 + // Position of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9 + // Bit mask of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200 + // Bit TRANS_START_INT_RAW. + I2C_INT_RAW_TRANS_START_INT_RAW = 0x200 + // Position of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Pos = 0xa + // Bit mask of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Msk = 0x400 + // Bit NACK_INT_RAW. + I2C_INT_RAW_NACK_INT_RAW = 0x400 + // Position of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Msk = 0x800 + // Bit TXFIFO_OVF_INT_RAW. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW = 0x800 + // Position of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_RAW. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW = 0x1000 + // Position of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Msk = 0x2000 + // Bit SCL_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_ST_TO_INT_RAW = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW = 0x4000 + // Position of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Pos = 0xf + // Bit mask of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Msk = 0x8000 + // Bit DET_START_INT_RAW. + I2C_INT_RAW_DET_START_INT_RAW = 0x8000 + // Position of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_RAW. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW = 0x10000 + // Position of GENERAL_CALL_INT_RAW field. + I2C_INT_RAW_GENERAL_CALL_INT_RAW_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_RAW field. + I2C_INT_RAW_GENERAL_CALL_INT_RAW_Msk = 0x20000 + // Bit GENERAL_CALL_INT_RAW. + I2C_INT_RAW_GENERAL_CALL_INT_RAW = 0x20000 + + // INT_CLR: I2C_INT_CLR_REG + // Position of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Msk = 0x1 + // Bit RXFIFO_WM_INT_CLR. + I2C_INT_CLR_RXFIFO_WM_INT_CLR = 0x1 + // Position of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Msk = 0x2 + // Bit TXFIFO_WM_INT_CLR. + I2C_INT_CLR_TXFIFO_WM_INT_CLR = 0x2 + // Position of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4 + // Bit RXFIFO_OVF_INT_CLR. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4 + // Position of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3 + // Bit mask of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8 + // Bit END_DETECT_INT_CLR. + I2C_INT_CLR_END_DETECT_INT_CLR = 0x8 + // Position of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_CLR. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR = 0x10 + // Position of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_CLR. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_CLR. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR = 0x40 + // Position of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_CLR. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit TIME_OUT_INT_CLR. + I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100 + // Position of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9 + // Bit mask of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200 + // Bit TRANS_START_INT_CLR. + I2C_INT_CLR_TRANS_START_INT_CLR = 0x200 + // Position of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Pos = 0xa + // Bit mask of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Msk = 0x400 + // Bit NACK_INT_CLR. + I2C_INT_CLR_NACK_INT_CLR = 0x400 + // Position of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Msk = 0x800 + // Bit TXFIFO_OVF_INT_CLR. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR = 0x800 + // Position of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_CLR. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR = 0x1000 + // Position of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Msk = 0x2000 + // Bit SCL_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_ST_TO_INT_CLR = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR = 0x4000 + // Position of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Pos = 0xf + // Bit mask of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Msk = 0x8000 + // Bit DET_START_INT_CLR. + I2C_INT_CLR_DET_START_INT_CLR = 0x8000 + // Position of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_CLR. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR = 0x10000 + // Position of GENERAL_CALL_INT_CLR field. + I2C_INT_CLR_GENERAL_CALL_INT_CLR_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_CLR field. + I2C_INT_CLR_GENERAL_CALL_INT_CLR_Msk = 0x20000 + // Bit GENERAL_CALL_INT_CLR. + I2C_INT_CLR_GENERAL_CALL_INT_CLR = 0x20000 + + // INT_ENA: I2C_INT_ENA_REG + // Position of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Msk = 0x1 + // Bit RXFIFO_WM_INT_ENA. + I2C_INT_ENA_RXFIFO_WM_INT_ENA = 0x1 + // Position of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Msk = 0x2 + // Bit TXFIFO_WM_INT_ENA. + I2C_INT_ENA_TXFIFO_WM_INT_ENA = 0x2 + // Position of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ENA. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4 + // Position of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3 + // Bit mask of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8 + // Bit END_DETECT_INT_ENA. + I2C_INT_ENA_END_DETECT_INT_ENA = 0x8 + // Position of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ENA. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA = 0x10 + // Position of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ENA. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20 + // Position of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ENA. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA = 0x40 + // Position of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ENA. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80 + // Position of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100 + // Bit TIME_OUT_INT_ENA. + I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100 + // Position of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9 + // Bit mask of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200 + // Bit TRANS_START_INT_ENA. + I2C_INT_ENA_TRANS_START_INT_ENA = 0x200 + // Position of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Pos = 0xa + // Bit mask of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Msk = 0x400 + // Bit NACK_INT_ENA. + I2C_INT_ENA_NACK_INT_ENA = 0x400 + // Position of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ENA. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA = 0x800 + // Position of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ENA. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA = 0x1000 + // Position of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_ST_TO_INT_ENA = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA = 0x4000 + // Position of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Pos = 0xf + // Bit mask of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Msk = 0x8000 + // Bit DET_START_INT_ENA. + I2C_INT_ENA_DET_START_INT_ENA = 0x8000 + // Position of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ENA. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA = 0x10000 + // Position of GENERAL_CALL_INT_ENA field. + I2C_INT_ENA_GENERAL_CALL_INT_ENA_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_ENA field. + I2C_INT_ENA_GENERAL_CALL_INT_ENA_Msk = 0x20000 + // Bit GENERAL_CALL_INT_ENA. + I2C_INT_ENA_GENERAL_CALL_INT_ENA = 0x20000 + + // INT_STATUS: I2C_INT_STATUS_REG + // Position of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Msk = 0x1 + // Bit RXFIFO_WM_INT_ST. + I2C_INT_STATUS_RXFIFO_WM_INT_ST = 0x1 + // Position of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Msk = 0x2 + // Bit TXFIFO_WM_INT_ST. + I2C_INT_STATUS_TXFIFO_WM_INT_ST = 0x2 + // Position of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ST. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4 + // Position of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3 + // Bit mask of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8 + // Bit END_DETECT_INT_ST. + I2C_INT_STATUS_END_DETECT_INT_ST = 0x8 + // Position of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ST. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST = 0x10 + // Position of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ST. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20 + // Position of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ST. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST = 0x40 + // Position of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ST. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80 + // Position of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100 + // Bit TIME_OUT_INT_ST. + I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100 + // Position of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9 + // Bit mask of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200 + // Bit TRANS_START_INT_ST. + I2C_INT_STATUS_TRANS_START_INT_ST = 0x200 + // Position of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Pos = 0xa + // Bit mask of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Msk = 0x400 + // Bit NACK_INT_ST. + I2C_INT_STATUS_NACK_INT_ST = 0x400 + // Position of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ST. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST = 0x800 + // Position of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ST. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST = 0x1000 + // Position of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_ST_TO_INT_ST = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST = 0x4000 + // Position of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Pos = 0xf + // Bit mask of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Msk = 0x8000 + // Bit DET_START_INT_ST. + I2C_INT_STATUS_DET_START_INT_ST = 0x8000 + // Position of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ST. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST = 0x10000 + // Position of GENERAL_CALL_INT_ST field. + I2C_INT_STATUS_GENERAL_CALL_INT_ST_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_ST field. + I2C_INT_STATUS_GENERAL_CALL_INT_ST_Msk = 0x20000 + // Bit GENERAL_CALL_INT_ST. + I2C_INT_STATUS_GENERAL_CALL_INT_ST = 0x20000 + + // SDA_HOLD: I2C_SDA_HOLD_REG + // Position of TIME field. + I2C_SDA_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_HOLD_TIME_Msk = 0x1ff + + // SDA_SAMPLE: I2C_SDA_SAMPLE_REG + // Position of TIME field. + I2C_SDA_SAMPLE_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_SAMPLE_TIME_Msk = 0x1ff + + // SCL_HIGH_PERIOD: I2C_SCL_HIGH_PERIOD_REG + // Position of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x1ff + // Position of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Pos = 0x9 + // Bit mask of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Msk = 0xfe00 + + // SCL_START_HOLD: I2C_SCL_START_HOLD_REG + // Position of TIME field. + I2C_SCL_START_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_START_HOLD_TIME_Msk = 0x1ff + + // SCL_RSTART_SETUP: I2C_SCL_RSTART_SETUP_REG + // Position of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Msk = 0x1ff + + // SCL_STOP_HOLD: I2C_SCL_STOP_HOLD_REG + // Position of TIME field. + I2C_SCL_STOP_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_HOLD_TIME_Msk = 0x1ff + + // SCL_STOP_SETUP: I2C_SCL_STOP_SETUP_REG + // Position of TIME field. + I2C_SCL_STOP_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_SETUP_TIME_Msk = 0x1ff + + // FILTER_CFG: I2C_FILTER_CFG_REG + // Position of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0 + // Bit mask of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Msk = 0xf + // Position of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x4 + // Bit mask of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Msk = 0xf0 + // Position of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Pos = 0x8 + // Bit mask of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Msk = 0x100 + // Bit SCL_FILTER_EN. + I2C_FILTER_CFG_SCL_FILTER_EN = 0x100 + // Position of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Pos = 0x9 + // Bit mask of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Msk = 0x200 + // Bit SDA_FILTER_EN. + I2C_FILTER_CFG_SDA_FILTER_EN = 0x200 + + // CLK_CONF: I2C_CLK_CONF_REG + // Position of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Pos = 0x0 + // Bit mask of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff + // Position of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Pos = 0x8 + // Bit mask of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Msk = 0x3f00 + // Position of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Pos = 0xe + // Bit mask of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Msk = 0xfc000 + // Position of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Msk = 0x100000 + // Bit SCLK_SEL. + I2C_CLK_CONF_SCLK_SEL = 0x100000 + // Position of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Pos = 0x15 + // Bit mask of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Msk = 0x200000 + // Bit SCLK_ACTIVE. + I2C_CLK_CONF_SCLK_ACTIVE = 0x200000 + + // COMD0: I2C_COMD%s_REG + // Position of COMMAND field. + I2C_COMD_COMMAND_Pos = 0x0 + // Bit mask of COMMAND field. + I2C_COMD_COMMAND_Msk = 0x3fff + // Position of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Pos = 0x1f + // Bit mask of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Msk = 0x80000000 + // Bit COMMAND_DONE. + I2C_COMD_COMMAND_DONE = 0x80000000 + + // SCL_ST_TIME_OUT: I2C_SCL_ST_TIME_OUT_REG + // Position of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Msk = 0x1f + + // SCL_MAIN_ST_TIME_OUT: I2C_SCL_MAIN_ST_TIME_OUT_REG + // Position of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Msk = 0x1f + + // SCL_SP_CONF: I2C_SCL_SP_CONF_REG + // Position of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Pos = 0x0 + // Bit mask of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Msk = 0x1 + // Bit SCL_RST_SLV_EN. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN = 0x1 + // Position of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Pos = 0x1 + // Bit mask of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Msk = 0x3e + // Position of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Pos = 0x6 + // Bit mask of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Msk = 0x40 + // Bit SCL_PD_EN. + I2C_SCL_SP_CONF_SCL_PD_EN = 0x40 + // Position of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Pos = 0x7 + // Bit mask of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Msk = 0x80 + // Bit SDA_PD_EN. + I2C_SCL_SP_CONF_SDA_PD_EN = 0x80 + + // SCL_STRETCH_CONF: I2C_SCL_STRETCH_CONF_REG + // Position of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Pos = 0x0 + // Bit mask of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Msk = 0x3ff + // Position of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Pos = 0xa + // Bit mask of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Msk = 0x400 + // Bit SLAVE_SCL_STRETCH_EN. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN = 0x400 + // Position of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Pos = 0xb + // Bit mask of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Msk = 0x800 + // Bit SLAVE_SCL_STRETCH_CLR. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR = 0x800 + // Position of SLAVE_BYTE_ACK_CTL_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Pos = 0xc + // Bit mask of SLAVE_BYTE_ACK_CTL_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Msk = 0x1000 + // Bit SLAVE_BYTE_ACK_CTL_EN. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN = 0x1000 + // Position of SLAVE_BYTE_ACK_LVL field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Pos = 0xd + // Bit mask of SLAVE_BYTE_ACK_LVL field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Msk = 0x2000 + // Bit SLAVE_BYTE_ACK_LVL. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL = 0x2000 + + // DATE: I2C_DATE_REG + // Position of DATE field. + I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2C_DATE_DATE_Msk = 0xffffffff + + // TXFIFO_START_ADDR: I2C_TXFIFO_START_ADDR_REG + // Position of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Msk = 0xffffffff + + // RXFIFO_START_ADDR: I2C_RXFIFO_START_ADDR_REG + // Position of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Msk = 0xffffffff +) + +// Constants for I2S0: I2S (Inter-IC Sound) Controller 0 +const ( + // INT_RAW: I2S interrupt raw register, valid in level. + // Position of RX_DONE_INT_RAW field. + I2S_INT_RAW_RX_DONE_INT_RAW_Pos = 0x0 + // Bit mask of RX_DONE_INT_RAW field. + I2S_INT_RAW_RX_DONE_INT_RAW_Msk = 0x1 + // Bit RX_DONE_INT_RAW. + I2S_INT_RAW_RX_DONE_INT_RAW = 0x1 + // Position of TX_DONE_INT_RAW field. + I2S_INT_RAW_TX_DONE_INT_RAW_Pos = 0x1 + // Bit mask of TX_DONE_INT_RAW field. + I2S_INT_RAW_TX_DONE_INT_RAW_Msk = 0x2 + // Bit TX_DONE_INT_RAW. + I2S_INT_RAW_TX_DONE_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + I2S_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + I2S_INT_RAW_TX_HUNG_INT_RAW = 0x8 + + // INT_ST: I2S interrupt status register. + // Position of RX_DONE_INT_ST field. + I2S_INT_ST_RX_DONE_INT_ST_Pos = 0x0 + // Bit mask of RX_DONE_INT_ST field. + I2S_INT_ST_RX_DONE_INT_ST_Msk = 0x1 + // Bit RX_DONE_INT_ST. + I2S_INT_ST_RX_DONE_INT_ST = 0x1 + // Position of TX_DONE_INT_ST field. + I2S_INT_ST_TX_DONE_INT_ST_Pos = 0x1 + // Bit mask of TX_DONE_INT_ST field. + I2S_INT_ST_TX_DONE_INT_ST_Msk = 0x2 + // Bit TX_DONE_INT_ST. + I2S_INT_ST_TX_DONE_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + I2S_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + I2S_INT_ST_TX_HUNG_INT_ST = 0x8 + + // INT_ENA: I2S interrupt enable register. + // Position of RX_DONE_INT_ENA field. + I2S_INT_ENA_RX_DONE_INT_ENA_Pos = 0x0 + // Bit mask of RX_DONE_INT_ENA field. + I2S_INT_ENA_RX_DONE_INT_ENA_Msk = 0x1 + // Bit RX_DONE_INT_ENA. + I2S_INT_ENA_RX_DONE_INT_ENA = 0x1 + // Position of TX_DONE_INT_ENA field. + I2S_INT_ENA_TX_DONE_INT_ENA_Pos = 0x1 + // Bit mask of TX_DONE_INT_ENA field. + I2S_INT_ENA_TX_DONE_INT_ENA_Msk = 0x2 + // Bit TX_DONE_INT_ENA. + I2S_INT_ENA_TX_DONE_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + I2S_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + I2S_INT_ENA_TX_HUNG_INT_ENA = 0x8 + + // INT_CLR: I2S interrupt clear register. + // Position of RX_DONE_INT_CLR field. + I2S_INT_CLR_RX_DONE_INT_CLR_Pos = 0x0 + // Bit mask of RX_DONE_INT_CLR field. + I2S_INT_CLR_RX_DONE_INT_CLR_Msk = 0x1 + // Bit RX_DONE_INT_CLR. + I2S_INT_CLR_RX_DONE_INT_CLR = 0x1 + // Position of TX_DONE_INT_CLR field. + I2S_INT_CLR_TX_DONE_INT_CLR_Pos = 0x1 + // Bit mask of TX_DONE_INT_CLR field. + I2S_INT_CLR_TX_DONE_INT_CLR_Msk = 0x2 + // Bit TX_DONE_INT_CLR. + I2S_INT_CLR_TX_DONE_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + I2S_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + I2S_INT_CLR_TX_HUNG_INT_CLR = 0x8 + + // RX_CONF: I2S RX configure register + // Position of RX_RESET field. + I2S_RX_CONF_RX_RESET_Pos = 0x0 + // Bit mask of RX_RESET field. + I2S_RX_CONF_RX_RESET_Msk = 0x1 + // Bit RX_RESET. + I2S_RX_CONF_RX_RESET = 0x1 + // Position of RX_FIFO_RESET field. + I2S_RX_CONF_RX_FIFO_RESET_Pos = 0x1 + // Bit mask of RX_FIFO_RESET field. + I2S_RX_CONF_RX_FIFO_RESET_Msk = 0x2 + // Bit RX_FIFO_RESET. + I2S_RX_CONF_RX_FIFO_RESET = 0x2 + // Position of RX_START field. + I2S_RX_CONF_RX_START_Pos = 0x2 + // Bit mask of RX_START field. + I2S_RX_CONF_RX_START_Msk = 0x4 + // Bit RX_START. + I2S_RX_CONF_RX_START = 0x4 + // Position of RX_SLAVE_MOD field. + I2S_RX_CONF_RX_SLAVE_MOD_Pos = 0x3 + // Bit mask of RX_SLAVE_MOD field. + I2S_RX_CONF_RX_SLAVE_MOD_Msk = 0x8 + // Bit RX_SLAVE_MOD. + I2S_RX_CONF_RX_SLAVE_MOD = 0x8 + // Position of RX_MONO field. + I2S_RX_CONF_RX_MONO_Pos = 0x5 + // Bit mask of RX_MONO field. + I2S_RX_CONF_RX_MONO_Msk = 0x20 + // Bit RX_MONO. + I2S_RX_CONF_RX_MONO = 0x20 + // Position of RX_BIG_ENDIAN field. + I2S_RX_CONF_RX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of RX_BIG_ENDIAN field. + I2S_RX_CONF_RX_BIG_ENDIAN_Msk = 0x80 + // Bit RX_BIG_ENDIAN. + I2S_RX_CONF_RX_BIG_ENDIAN = 0x80 + // Position of RX_UPDATE field. + I2S_RX_CONF_RX_UPDATE_Pos = 0x8 + // Bit mask of RX_UPDATE field. + I2S_RX_CONF_RX_UPDATE_Msk = 0x100 + // Bit RX_UPDATE. + I2S_RX_CONF_RX_UPDATE = 0x100 + // Position of RX_MONO_FST_VLD field. + I2S_RX_CONF_RX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of RX_MONO_FST_VLD field. + I2S_RX_CONF_RX_MONO_FST_VLD_Msk = 0x200 + // Bit RX_MONO_FST_VLD. + I2S_RX_CONF_RX_MONO_FST_VLD = 0x200 + // Position of RX_PCM_CONF field. + I2S_RX_CONF_RX_PCM_CONF_Pos = 0xa + // Bit mask of RX_PCM_CONF field. + I2S_RX_CONF_RX_PCM_CONF_Msk = 0xc00 + // Position of RX_PCM_BYPASS field. + I2S_RX_CONF_RX_PCM_BYPASS_Pos = 0xc + // Bit mask of RX_PCM_BYPASS field. + I2S_RX_CONF_RX_PCM_BYPASS_Msk = 0x1000 + // Bit RX_PCM_BYPASS. + I2S_RX_CONF_RX_PCM_BYPASS = 0x1000 + // Position of RX_STOP_MODE field. + I2S_RX_CONF_RX_STOP_MODE_Pos = 0xd + // Bit mask of RX_STOP_MODE field. + I2S_RX_CONF_RX_STOP_MODE_Msk = 0x6000 + // Position of RX_LEFT_ALIGN field. + I2S_RX_CONF_RX_LEFT_ALIGN_Pos = 0xf + // Bit mask of RX_LEFT_ALIGN field. + I2S_RX_CONF_RX_LEFT_ALIGN_Msk = 0x8000 + // Bit RX_LEFT_ALIGN. + I2S_RX_CONF_RX_LEFT_ALIGN = 0x8000 + // Position of RX_24_FILL_EN field. + I2S_RX_CONF_RX_24_FILL_EN_Pos = 0x10 + // Bit mask of RX_24_FILL_EN field. + I2S_RX_CONF_RX_24_FILL_EN_Msk = 0x10000 + // Bit RX_24_FILL_EN. + I2S_RX_CONF_RX_24_FILL_EN = 0x10000 + // Position of RX_WS_IDLE_POL field. + I2S_RX_CONF_RX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of RX_WS_IDLE_POL field. + I2S_RX_CONF_RX_WS_IDLE_POL_Msk = 0x20000 + // Bit RX_WS_IDLE_POL. + I2S_RX_CONF_RX_WS_IDLE_POL = 0x20000 + // Position of RX_BIT_ORDER field. + I2S_RX_CONF_RX_BIT_ORDER_Pos = 0x12 + // Bit mask of RX_BIT_ORDER field. + I2S_RX_CONF_RX_BIT_ORDER_Msk = 0x40000 + // Bit RX_BIT_ORDER. + I2S_RX_CONF_RX_BIT_ORDER = 0x40000 + // Position of RX_TDM_EN field. + I2S_RX_CONF_RX_TDM_EN_Pos = 0x13 + // Bit mask of RX_TDM_EN field. + I2S_RX_CONF_RX_TDM_EN_Msk = 0x80000 + // Bit RX_TDM_EN. + I2S_RX_CONF_RX_TDM_EN = 0x80000 + // Position of RX_PDM_EN field. + I2S_RX_CONF_RX_PDM_EN_Pos = 0x14 + // Bit mask of RX_PDM_EN field. + I2S_RX_CONF_RX_PDM_EN_Msk = 0x100000 + // Bit RX_PDM_EN. + I2S_RX_CONF_RX_PDM_EN = 0x100000 + + // TX_CONF: I2S TX configure register + // Position of TX_RESET field. + I2S_TX_CONF_TX_RESET_Pos = 0x0 + // Bit mask of TX_RESET field. + I2S_TX_CONF_TX_RESET_Msk = 0x1 + // Bit TX_RESET. + I2S_TX_CONF_TX_RESET = 0x1 + // Position of TX_FIFO_RESET field. + I2S_TX_CONF_TX_FIFO_RESET_Pos = 0x1 + // Bit mask of TX_FIFO_RESET field. + I2S_TX_CONF_TX_FIFO_RESET_Msk = 0x2 + // Bit TX_FIFO_RESET. + I2S_TX_CONF_TX_FIFO_RESET = 0x2 + // Position of TX_START field. + I2S_TX_CONF_TX_START_Pos = 0x2 + // Bit mask of TX_START field. + I2S_TX_CONF_TX_START_Msk = 0x4 + // Bit TX_START. + I2S_TX_CONF_TX_START = 0x4 + // Position of TX_SLAVE_MOD field. + I2S_TX_CONF_TX_SLAVE_MOD_Pos = 0x3 + // Bit mask of TX_SLAVE_MOD field. + I2S_TX_CONF_TX_SLAVE_MOD_Msk = 0x8 + // Bit TX_SLAVE_MOD. + I2S_TX_CONF_TX_SLAVE_MOD = 0x8 + // Position of TX_MONO field. + I2S_TX_CONF_TX_MONO_Pos = 0x5 + // Bit mask of TX_MONO field. + I2S_TX_CONF_TX_MONO_Msk = 0x20 + // Bit TX_MONO. + I2S_TX_CONF_TX_MONO = 0x20 + // Position of TX_CHAN_EQUAL field. + I2S_TX_CONF_TX_CHAN_EQUAL_Pos = 0x6 + // Bit mask of TX_CHAN_EQUAL field. + I2S_TX_CONF_TX_CHAN_EQUAL_Msk = 0x40 + // Bit TX_CHAN_EQUAL. + I2S_TX_CONF_TX_CHAN_EQUAL = 0x40 + // Position of TX_BIG_ENDIAN field. + I2S_TX_CONF_TX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of TX_BIG_ENDIAN field. + I2S_TX_CONF_TX_BIG_ENDIAN_Msk = 0x80 + // Bit TX_BIG_ENDIAN. + I2S_TX_CONF_TX_BIG_ENDIAN = 0x80 + // Position of TX_UPDATE field. + I2S_TX_CONF_TX_UPDATE_Pos = 0x8 + // Bit mask of TX_UPDATE field. + I2S_TX_CONF_TX_UPDATE_Msk = 0x100 + // Bit TX_UPDATE. + I2S_TX_CONF_TX_UPDATE = 0x100 + // Position of TX_MONO_FST_VLD field. + I2S_TX_CONF_TX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of TX_MONO_FST_VLD field. + I2S_TX_CONF_TX_MONO_FST_VLD_Msk = 0x200 + // Bit TX_MONO_FST_VLD. + I2S_TX_CONF_TX_MONO_FST_VLD = 0x200 + // Position of TX_PCM_CONF field. + I2S_TX_CONF_TX_PCM_CONF_Pos = 0xa + // Bit mask of TX_PCM_CONF field. + I2S_TX_CONF_TX_PCM_CONF_Msk = 0xc00 + // Position of TX_PCM_BYPASS field. + I2S_TX_CONF_TX_PCM_BYPASS_Pos = 0xc + // Bit mask of TX_PCM_BYPASS field. + I2S_TX_CONF_TX_PCM_BYPASS_Msk = 0x1000 + // Bit TX_PCM_BYPASS. + I2S_TX_CONF_TX_PCM_BYPASS = 0x1000 + // Position of TX_STOP_EN field. + I2S_TX_CONF_TX_STOP_EN_Pos = 0xd + // Bit mask of TX_STOP_EN field. + I2S_TX_CONF_TX_STOP_EN_Msk = 0x2000 + // Bit TX_STOP_EN. + I2S_TX_CONF_TX_STOP_EN = 0x2000 + // Position of TX_LEFT_ALIGN field. + I2S_TX_CONF_TX_LEFT_ALIGN_Pos = 0xf + // Bit mask of TX_LEFT_ALIGN field. + I2S_TX_CONF_TX_LEFT_ALIGN_Msk = 0x8000 + // Bit TX_LEFT_ALIGN. + I2S_TX_CONF_TX_LEFT_ALIGN = 0x8000 + // Position of TX_24_FILL_EN field. + I2S_TX_CONF_TX_24_FILL_EN_Pos = 0x10 + // Bit mask of TX_24_FILL_EN field. + I2S_TX_CONF_TX_24_FILL_EN_Msk = 0x10000 + // Bit TX_24_FILL_EN. + I2S_TX_CONF_TX_24_FILL_EN = 0x10000 + // Position of TX_WS_IDLE_POL field. + I2S_TX_CONF_TX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of TX_WS_IDLE_POL field. + I2S_TX_CONF_TX_WS_IDLE_POL_Msk = 0x20000 + // Bit TX_WS_IDLE_POL. + I2S_TX_CONF_TX_WS_IDLE_POL = 0x20000 + // Position of TX_BIT_ORDER field. + I2S_TX_CONF_TX_BIT_ORDER_Pos = 0x12 + // Bit mask of TX_BIT_ORDER field. + I2S_TX_CONF_TX_BIT_ORDER_Msk = 0x40000 + // Bit TX_BIT_ORDER. + I2S_TX_CONF_TX_BIT_ORDER = 0x40000 + // Position of TX_TDM_EN field. + I2S_TX_CONF_TX_TDM_EN_Pos = 0x13 + // Bit mask of TX_TDM_EN field. + I2S_TX_CONF_TX_TDM_EN_Msk = 0x80000 + // Bit TX_TDM_EN. + I2S_TX_CONF_TX_TDM_EN = 0x80000 + // Position of TX_PDM_EN field. + I2S_TX_CONF_TX_PDM_EN_Pos = 0x14 + // Bit mask of TX_PDM_EN field. + I2S_TX_CONF_TX_PDM_EN_Msk = 0x100000 + // Bit TX_PDM_EN. + I2S_TX_CONF_TX_PDM_EN = 0x100000 + // Position of TX_CHAN_MOD field. + I2S_TX_CONF_TX_CHAN_MOD_Pos = 0x18 + // Bit mask of TX_CHAN_MOD field. + I2S_TX_CONF_TX_CHAN_MOD_Msk = 0x7000000 + // Position of SIG_LOOPBACK field. + I2S_TX_CONF_SIG_LOOPBACK_Pos = 0x1b + // Bit mask of SIG_LOOPBACK field. + I2S_TX_CONF_SIG_LOOPBACK_Msk = 0x8000000 + // Bit SIG_LOOPBACK. + I2S_TX_CONF_SIG_LOOPBACK = 0x8000000 + + // RX_CONF1: I2S RX configure register 1 + // Position of RX_TDM_WS_WIDTH field. + I2S_RX_CONF1_RX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of RX_TDM_WS_WIDTH field. + I2S_RX_CONF1_RX_TDM_WS_WIDTH_Msk = 0x7f + // Position of RX_BCK_DIV_NUM field. + I2S_RX_CONF1_RX_BCK_DIV_NUM_Pos = 0x7 + // Bit mask of RX_BCK_DIV_NUM field. + I2S_RX_CONF1_RX_BCK_DIV_NUM_Msk = 0x1f80 + // Position of RX_BITS_MOD field. + I2S_RX_CONF1_RX_BITS_MOD_Pos = 0xd + // Bit mask of RX_BITS_MOD field. + I2S_RX_CONF1_RX_BITS_MOD_Msk = 0x3e000 + // Position of RX_HALF_SAMPLE_BITS field. + I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Pos = 0x12 + // Bit mask of RX_HALF_SAMPLE_BITS field. + I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Msk = 0xfc0000 + // Position of RX_TDM_CHAN_BITS field. + I2S_RX_CONF1_RX_TDM_CHAN_BITS_Pos = 0x18 + // Bit mask of RX_TDM_CHAN_BITS field. + I2S_RX_CONF1_RX_TDM_CHAN_BITS_Msk = 0x1f000000 + // Position of RX_MSB_SHIFT field. + I2S_RX_CONF1_RX_MSB_SHIFT_Pos = 0x1d + // Bit mask of RX_MSB_SHIFT field. + I2S_RX_CONF1_RX_MSB_SHIFT_Msk = 0x20000000 + // Bit RX_MSB_SHIFT. + I2S_RX_CONF1_RX_MSB_SHIFT = 0x20000000 + + // TX_CONF1: I2S TX configure register 1 + // Position of TX_TDM_WS_WIDTH field. + I2S_TX_CONF1_TX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of TX_TDM_WS_WIDTH field. + I2S_TX_CONF1_TX_TDM_WS_WIDTH_Msk = 0x7f + // Position of TX_BCK_DIV_NUM field. + I2S_TX_CONF1_TX_BCK_DIV_NUM_Pos = 0x7 + // Bit mask of TX_BCK_DIV_NUM field. + I2S_TX_CONF1_TX_BCK_DIV_NUM_Msk = 0x1f80 + // Position of TX_BITS_MOD field. + I2S_TX_CONF1_TX_BITS_MOD_Pos = 0xd + // Bit mask of TX_BITS_MOD field. + I2S_TX_CONF1_TX_BITS_MOD_Msk = 0x3e000 + // Position of TX_HALF_SAMPLE_BITS field. + I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Pos = 0x12 + // Bit mask of TX_HALF_SAMPLE_BITS field. + I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Msk = 0xfc0000 + // Position of TX_TDM_CHAN_BITS field. + I2S_TX_CONF1_TX_TDM_CHAN_BITS_Pos = 0x18 + // Bit mask of TX_TDM_CHAN_BITS field. + I2S_TX_CONF1_TX_TDM_CHAN_BITS_Msk = 0x1f000000 + // Position of TX_MSB_SHIFT field. + I2S_TX_CONF1_TX_MSB_SHIFT_Pos = 0x1d + // Bit mask of TX_MSB_SHIFT field. + I2S_TX_CONF1_TX_MSB_SHIFT_Msk = 0x20000000 + // Bit TX_MSB_SHIFT. + I2S_TX_CONF1_TX_MSB_SHIFT = 0x20000000 + // Position of TX_BCK_NO_DLY field. + I2S_TX_CONF1_TX_BCK_NO_DLY_Pos = 0x1e + // Bit mask of TX_BCK_NO_DLY field. + I2S_TX_CONF1_TX_BCK_NO_DLY_Msk = 0x40000000 + // Bit TX_BCK_NO_DLY. + I2S_TX_CONF1_TX_BCK_NO_DLY = 0x40000000 + + // RX_CLKM_CONF: I2S RX clock configure register + // Position of RX_CLKM_DIV_NUM field. + I2S_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_NUM field. + I2S_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Msk = 0xff + // Position of RX_CLK_ACTIVE field. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of RX_CLK_ACTIVE field. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE_Msk = 0x4000000 + // Bit RX_CLK_ACTIVE. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE = 0x4000000 + // Position of RX_CLK_SEL field. + I2S_RX_CLKM_CONF_RX_CLK_SEL_Pos = 0x1b + // Bit mask of RX_CLK_SEL field. + I2S_RX_CLKM_CONF_RX_CLK_SEL_Msk = 0x18000000 + // Position of MCLK_SEL field. + I2S_RX_CLKM_CONF_MCLK_SEL_Pos = 0x1d + // Bit mask of MCLK_SEL field. + I2S_RX_CLKM_CONF_MCLK_SEL_Msk = 0x20000000 + // Bit MCLK_SEL. + I2S_RX_CLKM_CONF_MCLK_SEL = 0x20000000 + + // TX_CLKM_CONF: I2S TX clock configure register + // Position of TX_CLKM_DIV_NUM field. + I2S_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_NUM field. + I2S_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Msk = 0xff + // Position of TX_CLK_ACTIVE field. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of TX_CLK_ACTIVE field. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE_Msk = 0x4000000 + // Bit TX_CLK_ACTIVE. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE = 0x4000000 + // Position of TX_CLK_SEL field. + I2S_TX_CLKM_CONF_TX_CLK_SEL_Pos = 0x1b + // Bit mask of TX_CLK_SEL field. + I2S_TX_CLKM_CONF_TX_CLK_SEL_Msk = 0x18000000 + // Position of CLK_EN field. + I2S_TX_CLKM_CONF_CLK_EN_Pos = 0x1d + // Bit mask of CLK_EN field. + I2S_TX_CLKM_CONF_CLK_EN_Msk = 0x20000000 + // Bit CLK_EN. + I2S_TX_CLKM_CONF_CLK_EN = 0x20000000 + + // RX_CLKM_DIV_CONF: I2S RX module clock divider configure register + // Position of RX_CLKM_DIV_Z field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_Z field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Msk = 0x1ff + // Position of RX_CLKM_DIV_Y field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of RX_CLKM_DIV_Y field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of RX_CLKM_DIV_X field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of RX_CLKM_DIV_X field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of RX_CLKM_DIV_YN1 field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of RX_CLKM_DIV_YN1 field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit RX_CLKM_DIV_YN1. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1 = 0x8000000 + + // TX_CLKM_DIV_CONF: I2S TX module clock divider configure register + // Position of TX_CLKM_DIV_Z field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_Z field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Msk = 0x1ff + // Position of TX_CLKM_DIV_Y field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of TX_CLKM_DIV_Y field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of TX_CLKM_DIV_X field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of TX_CLKM_DIV_X field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of TX_CLKM_DIV_YN1 field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of TX_CLKM_DIV_YN1 field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit TX_CLKM_DIV_YN1. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1 = 0x8000000 + + // TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register + // Position of TX_PDM_HP_BYPASS field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Pos = 0x0 + // Bit mask of TX_PDM_HP_BYPASS field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Msk = 0x1 + // Bit TX_PDM_HP_BYPASS. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS = 0x1 + // Position of TX_PDM_SINC_OSR2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Pos = 0x1 + // Bit mask of TX_PDM_SINC_OSR2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Msk = 0x1e + // Position of TX_PDM_PRESCALE field. + I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Pos = 0x5 + // Bit mask of TX_PDM_PRESCALE field. + I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Msk = 0x1fe0 + // Position of TX_PDM_HP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Pos = 0xd + // Bit mask of TX_PDM_HP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Msk = 0x6000 + // Position of TX_PDM_LP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Pos = 0xf + // Bit mask of TX_PDM_LP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Msk = 0x18000 + // Position of TX_PDM_SINC_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Pos = 0x11 + // Bit mask of TX_PDM_SINC_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Msk = 0x60000 + // Position of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Pos = 0x13 + // Bit mask of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Msk = 0x180000 + // Position of TX_PDM_SIGMADELTA_DITHER2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Pos = 0x15 + // Bit mask of TX_PDM_SIGMADELTA_DITHER2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Msk = 0x200000 + // Bit TX_PDM_SIGMADELTA_DITHER2. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2 = 0x200000 + // Position of TX_PDM_SIGMADELTA_DITHER field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Pos = 0x16 + // Bit mask of TX_PDM_SIGMADELTA_DITHER field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Msk = 0x400000 + // Bit TX_PDM_SIGMADELTA_DITHER. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER = 0x400000 + // Position of TX_PDM_DAC_2OUT_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Pos = 0x17 + // Bit mask of TX_PDM_DAC_2OUT_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Msk = 0x800000 + // Bit TX_PDM_DAC_2OUT_EN. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN = 0x800000 + // Position of TX_PDM_DAC_MODE_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Pos = 0x18 + // Bit mask of TX_PDM_DAC_MODE_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Msk = 0x1000000 + // Bit TX_PDM_DAC_MODE_EN. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN = 0x1000000 + // Position of PCM2PDM_CONV_EN field. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Pos = 0x19 + // Bit mask of PCM2PDM_CONV_EN field. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Msk = 0x2000000 + // Bit PCM2PDM_CONV_EN. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN = 0x2000000 + + // TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register + // Position of TX_PDM_FP field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Pos = 0x0 + // Bit mask of TX_PDM_FP field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Msk = 0x3ff + // Position of TX_PDM_FS field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Pos = 0xa + // Bit mask of TX_PDM_FS field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Msk = 0xffc00 + // Position of TX_IIR_HP_MULT12_5 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Pos = 0x14 + // Bit mask of TX_IIR_HP_MULT12_5 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Msk = 0x700000 + // Position of TX_IIR_HP_MULT12_0 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Pos = 0x17 + // Bit mask of TX_IIR_HP_MULT12_0 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Msk = 0x3800000 + + // RX_TDM_CTRL: I2S TX TDM mode control register + // Position of RX_TDM_PDM_CHAN0_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Pos = 0x0 + // Bit mask of RX_TDM_PDM_CHAN0_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Msk = 0x1 + // Bit RX_TDM_PDM_CHAN0_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN = 0x1 + // Position of RX_TDM_PDM_CHAN1_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Pos = 0x1 + // Bit mask of RX_TDM_PDM_CHAN1_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Msk = 0x2 + // Bit RX_TDM_PDM_CHAN1_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN = 0x2 + // Position of RX_TDM_PDM_CHAN2_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Pos = 0x2 + // Bit mask of RX_TDM_PDM_CHAN2_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Msk = 0x4 + // Bit RX_TDM_PDM_CHAN2_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN = 0x4 + // Position of RX_TDM_PDM_CHAN3_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Pos = 0x3 + // Bit mask of RX_TDM_PDM_CHAN3_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Msk = 0x8 + // Bit RX_TDM_PDM_CHAN3_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN = 0x8 + // Position of RX_TDM_PDM_CHAN4_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Pos = 0x4 + // Bit mask of RX_TDM_PDM_CHAN4_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Msk = 0x10 + // Bit RX_TDM_PDM_CHAN4_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN = 0x10 + // Position of RX_TDM_PDM_CHAN5_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Pos = 0x5 + // Bit mask of RX_TDM_PDM_CHAN5_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Msk = 0x20 + // Bit RX_TDM_PDM_CHAN5_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN = 0x20 + // Position of RX_TDM_PDM_CHAN6_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Pos = 0x6 + // Bit mask of RX_TDM_PDM_CHAN6_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Msk = 0x40 + // Bit RX_TDM_PDM_CHAN6_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN = 0x40 + // Position of RX_TDM_PDM_CHAN7_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Pos = 0x7 + // Bit mask of RX_TDM_PDM_CHAN7_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Msk = 0x80 + // Bit RX_TDM_PDM_CHAN7_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN = 0x80 + // Position of RX_TDM_CHAN8_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of RX_TDM_CHAN8_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Msk = 0x100 + // Bit RX_TDM_CHAN8_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN = 0x100 + // Position of RX_TDM_CHAN9_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of RX_TDM_CHAN9_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Msk = 0x200 + // Bit RX_TDM_CHAN9_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN = 0x200 + // Position of RX_TDM_CHAN10_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of RX_TDM_CHAN10_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Msk = 0x400 + // Bit RX_TDM_CHAN10_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN = 0x400 + // Position of RX_TDM_CHAN11_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of RX_TDM_CHAN11_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Msk = 0x800 + // Bit RX_TDM_CHAN11_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN = 0x800 + // Position of RX_TDM_CHAN12_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of RX_TDM_CHAN12_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit RX_TDM_CHAN12_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN = 0x1000 + // Position of RX_TDM_CHAN13_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of RX_TDM_CHAN13_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit RX_TDM_CHAN13_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN = 0x2000 + // Position of RX_TDM_CHAN14_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of RX_TDM_CHAN14_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit RX_TDM_CHAN14_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN = 0x4000 + // Position of RX_TDM_CHAN15_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of RX_TDM_CHAN15_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit RX_TDM_CHAN15_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN = 0x8000 + // Position of RX_TDM_TOT_CHAN_NUM field. + I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of RX_TDM_TOT_CHAN_NUM field. + I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + + // TX_TDM_CTRL: I2S TX TDM mode control register + // Position of TX_TDM_CHAN0_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Pos = 0x0 + // Bit mask of TX_TDM_CHAN0_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Msk = 0x1 + // Bit TX_TDM_CHAN0_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN = 0x1 + // Position of TX_TDM_CHAN1_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Pos = 0x1 + // Bit mask of TX_TDM_CHAN1_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Msk = 0x2 + // Bit TX_TDM_CHAN1_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN = 0x2 + // Position of TX_TDM_CHAN2_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Pos = 0x2 + // Bit mask of TX_TDM_CHAN2_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Msk = 0x4 + // Bit TX_TDM_CHAN2_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN = 0x4 + // Position of TX_TDM_CHAN3_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Pos = 0x3 + // Bit mask of TX_TDM_CHAN3_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Msk = 0x8 + // Bit TX_TDM_CHAN3_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN = 0x8 + // Position of TX_TDM_CHAN4_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Pos = 0x4 + // Bit mask of TX_TDM_CHAN4_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Msk = 0x10 + // Bit TX_TDM_CHAN4_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN = 0x10 + // Position of TX_TDM_CHAN5_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Pos = 0x5 + // Bit mask of TX_TDM_CHAN5_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Msk = 0x20 + // Bit TX_TDM_CHAN5_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN = 0x20 + // Position of TX_TDM_CHAN6_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Pos = 0x6 + // Bit mask of TX_TDM_CHAN6_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Msk = 0x40 + // Bit TX_TDM_CHAN6_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN = 0x40 + // Position of TX_TDM_CHAN7_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Pos = 0x7 + // Bit mask of TX_TDM_CHAN7_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Msk = 0x80 + // Bit TX_TDM_CHAN7_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN = 0x80 + // Position of TX_TDM_CHAN8_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of TX_TDM_CHAN8_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Msk = 0x100 + // Bit TX_TDM_CHAN8_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN = 0x100 + // Position of TX_TDM_CHAN9_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of TX_TDM_CHAN9_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Msk = 0x200 + // Bit TX_TDM_CHAN9_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN = 0x200 + // Position of TX_TDM_CHAN10_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of TX_TDM_CHAN10_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Msk = 0x400 + // Bit TX_TDM_CHAN10_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN = 0x400 + // Position of TX_TDM_CHAN11_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of TX_TDM_CHAN11_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Msk = 0x800 + // Bit TX_TDM_CHAN11_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN = 0x800 + // Position of TX_TDM_CHAN12_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of TX_TDM_CHAN12_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit TX_TDM_CHAN12_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN = 0x1000 + // Position of TX_TDM_CHAN13_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of TX_TDM_CHAN13_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit TX_TDM_CHAN13_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN = 0x2000 + // Position of TX_TDM_CHAN14_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of TX_TDM_CHAN14_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit TX_TDM_CHAN14_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN = 0x4000 + // Position of TX_TDM_CHAN15_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of TX_TDM_CHAN15_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit TX_TDM_CHAN15_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN = 0x8000 + // Position of TX_TDM_TOT_CHAN_NUM field. + I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of TX_TDM_TOT_CHAN_NUM field. + I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + // Position of TX_TDM_SKIP_MSK_EN field. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Pos = 0x14 + // Bit mask of TX_TDM_SKIP_MSK_EN field. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Msk = 0x100000 + // Bit TX_TDM_SKIP_MSK_EN. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN = 0x100000 + + // RX_TIMING: I2S RX timing control register + // Position of RX_SD_IN_DM field. + I2S_RX_TIMING_RX_SD_IN_DM_Pos = 0x0 + // Bit mask of RX_SD_IN_DM field. + I2S_RX_TIMING_RX_SD_IN_DM_Msk = 0x3 + // Position of RX_WS_OUT_DM field. + I2S_RX_TIMING_RX_WS_OUT_DM_Pos = 0x10 + // Bit mask of RX_WS_OUT_DM field. + I2S_RX_TIMING_RX_WS_OUT_DM_Msk = 0x30000 + // Position of RX_BCK_OUT_DM field. + I2S_RX_TIMING_RX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of RX_BCK_OUT_DM field. + I2S_RX_TIMING_RX_BCK_OUT_DM_Msk = 0x300000 + // Position of RX_WS_IN_DM field. + I2S_RX_TIMING_RX_WS_IN_DM_Pos = 0x18 + // Bit mask of RX_WS_IN_DM field. + I2S_RX_TIMING_RX_WS_IN_DM_Msk = 0x3000000 + // Position of RX_BCK_IN_DM field. + I2S_RX_TIMING_RX_BCK_IN_DM_Pos = 0x1c + // Bit mask of RX_BCK_IN_DM field. + I2S_RX_TIMING_RX_BCK_IN_DM_Msk = 0x30000000 + + // TX_TIMING: I2S TX timing control register + // Position of TX_SD_OUT_DM field. + I2S_TX_TIMING_TX_SD_OUT_DM_Pos = 0x0 + // Bit mask of TX_SD_OUT_DM field. + I2S_TX_TIMING_TX_SD_OUT_DM_Msk = 0x3 + // Position of TX_SD1_OUT_DM field. + I2S_TX_TIMING_TX_SD1_OUT_DM_Pos = 0x4 + // Bit mask of TX_SD1_OUT_DM field. + I2S_TX_TIMING_TX_SD1_OUT_DM_Msk = 0x30 + // Position of TX_WS_OUT_DM field. + I2S_TX_TIMING_TX_WS_OUT_DM_Pos = 0x10 + // Bit mask of TX_WS_OUT_DM field. + I2S_TX_TIMING_TX_WS_OUT_DM_Msk = 0x30000 + // Position of TX_BCK_OUT_DM field. + I2S_TX_TIMING_TX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of TX_BCK_OUT_DM field. + I2S_TX_TIMING_TX_BCK_OUT_DM_Msk = 0x300000 + // Position of TX_WS_IN_DM field. + I2S_TX_TIMING_TX_WS_IN_DM_Pos = 0x18 + // Bit mask of TX_WS_IN_DM field. + I2S_TX_TIMING_TX_WS_IN_DM_Msk = 0x3000000 + // Position of TX_BCK_IN_DM field. + I2S_TX_TIMING_TX_BCK_IN_DM_Pos = 0x1c + // Bit mask of TX_BCK_IN_DM field. + I2S_TX_TIMING_TX_BCK_IN_DM_Msk = 0x30000000 + + // LC_HUNG_CONF: I2S HUNG configure register. + // Position of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Pos = 0x0 + // Bit mask of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Msk = 0xff + // Position of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit LC_FIFO_TIMEOUT_ENA. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA = 0x800 + + // RXEOF_NUM: I2S RX data number control register. + // Position of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Pos = 0x0 + // Bit mask of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Msk = 0xfff + + // CONF_SIGLE_DATA: I2S signal data register + // Position of SINGLE_DATA field. + I2S_CONF_SIGLE_DATA_SINGLE_DATA_Pos = 0x0 + // Bit mask of SINGLE_DATA field. + I2S_CONF_SIGLE_DATA_SINGLE_DATA_Msk = 0xffffffff + + // STATE: I2S TX status register + // Position of TX_IDLE field. + I2S_STATE_TX_IDLE_Pos = 0x0 + // Bit mask of TX_IDLE field. + I2S_STATE_TX_IDLE_Msk = 0x1 + // Bit TX_IDLE. + I2S_STATE_TX_IDLE = 0x1 + + // DATE: Version control register + // Position of DATE field. + I2S_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2S_DATE_DATE_Msk = 0xfffffff +) + +// Constants for INTERRUPT_CORE0: Interrupt Controller (Core 0) +const ( + // MAC_INTR_MAP: mac intr map register + // Position of MAC_INTR_MAP field. + INTERRUPT_CORE0_MAC_INTR_MAP_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of MAC_INTR_MAP field. + INTERRUPT_CORE0_MAC_INTR_MAP_MAC_INTR_MAP_Msk = 0x1f + + // MAC_NMI_MAP: mac nmi_intr map register + // Position of MAC_NMI_MAP field. + INTERRUPT_CORE0_MAC_NMI_MAP_MAC_NMI_MAP_Pos = 0x0 + // Bit mask of MAC_NMI_MAP field. + INTERRUPT_CORE0_MAC_NMI_MAP_MAC_NMI_MAP_Msk = 0x1f + + // PWR_INTR_MAP: pwr intr map register + // Position of PWR_INTR_MAP field. + INTERRUPT_CORE0_PWR_INTR_MAP_PWR_INTR_MAP_Pos = 0x0 + // Bit mask of PWR_INTR_MAP field. + INTERRUPT_CORE0_PWR_INTR_MAP_PWR_INTR_MAP_Msk = 0x1f + + // BB_INT_MAP: bb intr map register + // Position of BB_INT_MAP field. + INTERRUPT_CORE0_BB_INT_MAP_BB_INT_MAP_Pos = 0x0 + // Bit mask of BB_INT_MAP field. + INTERRUPT_CORE0_BB_INT_MAP_BB_INT_MAP_Msk = 0x1f + + // BT_MAC_INT_MAP: bt intr map register + // Position of BT_MAC_INT_MAP field. + INTERRUPT_CORE0_BT_MAC_INT_MAP_BT_MAC_INT_MAP_Pos = 0x0 + // Bit mask of BT_MAC_INT_MAP field. + INTERRUPT_CORE0_BT_MAC_INT_MAP_BT_MAC_INT_MAP_Msk = 0x1f + + // BT_BB_INT_MAP: bb_bt intr map register + // Position of BT_BB_INT_MAP field. + INTERRUPT_CORE0_BT_BB_INT_MAP_BT_BB_INT_MAP_Pos = 0x0 + // Bit mask of BT_BB_INT_MAP field. + INTERRUPT_CORE0_BT_BB_INT_MAP_BT_BB_INT_MAP_Msk = 0x1f + + // BT_BB_NMI_MAP: bb_bt_nmi intr map register + // Position of BT_BB_NMI_MAP field. + INTERRUPT_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Pos = 0x0 + // Bit mask of BT_BB_NMI_MAP field. + INTERRUPT_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Msk = 0x1f + + // RWBT_IRQ_MAP: rwbt intr map register + // Position of RWBT_IRQ_MAP field. + INTERRUPT_CORE0_RWBT_IRQ_MAP_RWBT_IRQ_MAP_Pos = 0x0 + // Bit mask of RWBT_IRQ_MAP field. + INTERRUPT_CORE0_RWBT_IRQ_MAP_RWBT_IRQ_MAP_Msk = 0x1f + + // RWBLE_IRQ_MAP: rwble intr map register + // Position of RWBLE_IRQ_MAP field. + INTERRUPT_CORE0_RWBLE_IRQ_MAP_RWBLE_IRQ_MAP_Pos = 0x0 + // Bit mask of RWBLE_IRQ_MAP field. + INTERRUPT_CORE0_RWBLE_IRQ_MAP_RWBLE_IRQ_MAP_Msk = 0x1f + + // RWBT_NMI_MAP: rwbt_nmi intr map register + // Position of RWBT_NMI_MAP field. + INTERRUPT_CORE0_RWBT_NMI_MAP_RWBT_NMI_MAP_Pos = 0x0 + // Bit mask of RWBT_NMI_MAP field. + INTERRUPT_CORE0_RWBT_NMI_MAP_RWBT_NMI_MAP_Msk = 0x1f + + // RWBLE_NMI_MAP: rwble_nmi intr map register + // Position of RWBLE_NMI_MAP field. + INTERRUPT_CORE0_RWBLE_NMI_MAP_RWBLE_NMI_MAP_Pos = 0x0 + // Bit mask of RWBLE_NMI_MAP field. + INTERRUPT_CORE0_RWBLE_NMI_MAP_RWBLE_NMI_MAP_Msk = 0x1f + + // I2C_MST_INT_MAP: i2c intr map register + // Position of I2C_MST_INT_MAP field. + INTERRUPT_CORE0_I2C_MST_INT_MAP_I2C_MST_INT_MAP_Pos = 0x0 + // Bit mask of I2C_MST_INT_MAP field. + INTERRUPT_CORE0_I2C_MST_INT_MAP_I2C_MST_INT_MAP_Msk = 0x1f + + // SLC0_INTR_MAP: slc0 intr map register + // Position of SLC0_INTR_MAP field. + INTERRUPT_CORE0_SLC0_INTR_MAP_SLC0_INTR_MAP_Pos = 0x0 + // Bit mask of SLC0_INTR_MAP field. + INTERRUPT_CORE0_SLC0_INTR_MAP_SLC0_INTR_MAP_Msk = 0x1f + + // SLC1_INTR_MAP: slc1 intr map register + // Position of SLC1_INTR_MAP field. + INTERRUPT_CORE0_SLC1_INTR_MAP_SLC1_INTR_MAP_Pos = 0x0 + // Bit mask of SLC1_INTR_MAP field. + INTERRUPT_CORE0_SLC1_INTR_MAP_SLC1_INTR_MAP_Msk = 0x1f + + // APB_CTRL_INTR_MAP: apb_ctrl intr map register + // Position of APB_CTRL_INTR_MAP field. + INTERRUPT_CORE0_APB_CTRL_INTR_MAP_APB_CTRL_INTR_MAP_Pos = 0x0 + // Bit mask of APB_CTRL_INTR_MAP field. + INTERRUPT_CORE0_APB_CTRL_INTR_MAP_APB_CTRL_INTR_MAP_Msk = 0x1f + + // UHCI0_INTR_MAP: uchi0 intr map register + // Position of UHCI0_INTR_MAP field. + INTERRUPT_CORE0_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Pos = 0x0 + // Bit mask of UHCI0_INTR_MAP field. + INTERRUPT_CORE0_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_MAP: gpio intr map register + // Position of GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_NMI_MAP: gpio_pro intr map register + // Position of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Msk = 0x1f + + // SPI_INTR_1_MAP: gpio_pro_nmi intr map register + // Position of SPI_INTR_1_MAP field. + INTERRUPT_CORE0_SPI_INTR_1_MAP_SPI_INTR_1_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_1_MAP field. + INTERRUPT_CORE0_SPI_INTR_1_MAP_SPI_INTR_1_MAP_Msk = 0x1f + + // SPI_INTR_2_MAP: spi1 intr map register + // Position of SPI_INTR_2_MAP field. + INTERRUPT_CORE0_SPI_INTR_2_MAP_SPI_INTR_2_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_2_MAP field. + INTERRUPT_CORE0_SPI_INTR_2_MAP_SPI_INTR_2_MAP_Msk = 0x1f + + // I2S1_INT_MAP: spi2 intr map register + // Position of I2S1_INT_MAP field. + INTERRUPT_CORE0_I2S1_INT_MAP_I2S1_INT_MAP_Pos = 0x0 + // Bit mask of I2S1_INT_MAP field. + INTERRUPT_CORE0_I2S1_INT_MAP_I2S1_INT_MAP_Msk = 0x1f + + // UART_INTR_MAP: i2s1 intr map register + // Position of UART_INTR_MAP field. + INTERRUPT_CORE0_UART_INTR_MAP_UART_INTR_MAP_Pos = 0x0 + // Bit mask of UART_INTR_MAP field. + INTERRUPT_CORE0_UART_INTR_MAP_UART_INTR_MAP_Msk = 0x1f + + // UART1_INTR_MAP: uart1 intr map register + // Position of UART1_INTR_MAP field. + INTERRUPT_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Pos = 0x0 + // Bit mask of UART1_INTR_MAP field. + INTERRUPT_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Msk = 0x1f + + // LEDC_INT_MAP: ledc intr map register + // Position of LEDC_INT_MAP field. + INTERRUPT_CORE0_LEDC_INT_MAP_LEDC_INT_MAP_Pos = 0x0 + // Bit mask of LEDC_INT_MAP field. + INTERRUPT_CORE0_LEDC_INT_MAP_LEDC_INT_MAP_Msk = 0x1f + + // EFUSE_INT_MAP: efuse intr map register + // Position of EFUSE_INT_MAP field. + INTERRUPT_CORE0_EFUSE_INT_MAP_EFUSE_INT_MAP_Pos = 0x0 + // Bit mask of EFUSE_INT_MAP field. + INTERRUPT_CORE0_EFUSE_INT_MAP_EFUSE_INT_MAP_Msk = 0x1f + + // CAN_INT_MAP: can intr map register + // Position of CAN_INT_MAP field. + INTERRUPT_CORE0_CAN_INT_MAP_CAN_INT_MAP_Pos = 0x0 + // Bit mask of CAN_INT_MAP field. + INTERRUPT_CORE0_CAN_INT_MAP_CAN_INT_MAP_Msk = 0x1f + + // USB_INTR_MAP: usb intr map register + // Position of USB_INTR_MAP field. + INTERRUPT_CORE0_USB_INTR_MAP_USB_INTR_MAP_Pos = 0x0 + // Bit mask of USB_INTR_MAP field. + INTERRUPT_CORE0_USB_INTR_MAP_USB_INTR_MAP_Msk = 0x1f + + // RTC_CORE_INTR_MAP: rtc intr map register + // Position of RTC_CORE_INTR_MAP field. + INTERRUPT_CORE0_RTC_CORE_INTR_MAP_RTC_CORE_INTR_MAP_Pos = 0x0 + // Bit mask of RTC_CORE_INTR_MAP field. + INTERRUPT_CORE0_RTC_CORE_INTR_MAP_RTC_CORE_INTR_MAP_Msk = 0x1f + + // RMT_INTR_MAP: rmt intr map register + // Position of RMT_INTR_MAP field. + INTERRUPT_CORE0_RMT_INTR_MAP_RMT_INTR_MAP_Pos = 0x0 + // Bit mask of RMT_INTR_MAP field. + INTERRUPT_CORE0_RMT_INTR_MAP_RMT_INTR_MAP_Msk = 0x1f + + // I2C_EXT0_INTR_MAP: i2c intr map register + // Position of I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Msk = 0x1f + + // TIMER_INT1_MAP: timer1 intr map register + // Position of TIMER_INT1_MAP field. + INTERRUPT_CORE0_TIMER_INT1_MAP_TIMER_INT1_MAP_Pos = 0x0 + // Bit mask of TIMER_INT1_MAP field. + INTERRUPT_CORE0_TIMER_INT1_MAP_TIMER_INT1_MAP_Msk = 0x1f + + // TIMER_INT2_MAP: timer2 intr map register + // Position of TIMER_INT2_MAP field. + INTERRUPT_CORE0_TIMER_INT2_MAP_TIMER_INT2_MAP_Pos = 0x0 + // Bit mask of TIMER_INT2_MAP field. + INTERRUPT_CORE0_TIMER_INT2_MAP_TIMER_INT2_MAP_Msk = 0x1f + + // TG_T0_INT_MAP: tg to intr map register + // Position of TG_T0_INT_MAP field. + INTERRUPT_CORE0_TG_T0_INT_MAP_TG_T0_INT_MAP_Pos = 0x0 + // Bit mask of TG_T0_INT_MAP field. + INTERRUPT_CORE0_TG_T0_INT_MAP_TG_T0_INT_MAP_Msk = 0x1f + + // TG_WDT_INT_MAP: tg wdt intr map register + // Position of TG_WDT_INT_MAP field. + INTERRUPT_CORE0_TG_WDT_INT_MAP_TG_WDT_INT_MAP_Pos = 0x0 + // Bit mask of TG_WDT_INT_MAP field. + INTERRUPT_CORE0_TG_WDT_INT_MAP_TG_WDT_INT_MAP_Msk = 0x1f + + // TG1_T0_INT_MAP: tg1 to intr map register + // Position of TG1_T0_INT_MAP field. + INTERRUPT_CORE0_TG1_T0_INT_MAP_TG1_T0_INT_MAP_Pos = 0x0 + // Bit mask of TG1_T0_INT_MAP field. + INTERRUPT_CORE0_TG1_T0_INT_MAP_TG1_T0_INT_MAP_Msk = 0x1f + + // TG1_WDT_INT_MAP: tg1 wdt intr map register + // Position of TG1_WDT_INT_MAP field. + INTERRUPT_CORE0_TG1_WDT_INT_MAP_TG1_WDT_INT_MAP_Pos = 0x0 + // Bit mask of TG1_WDT_INT_MAP field. + INTERRUPT_CORE0_TG1_WDT_INT_MAP_TG1_WDT_INT_MAP_Msk = 0x1f + + // CACHE_IA_INT_MAP: cache ia intr map register + // Position of CACHE_IA_INT_MAP field. + INTERRUPT_CORE0_CACHE_IA_INT_MAP_CACHE_IA_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_IA_INT_MAP field. + INTERRUPT_CORE0_CACHE_IA_INT_MAP_CACHE_IA_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET0_INT_MAP: systimer intr map register + // Position of SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_SYSTIMER_TARGET0_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_SYSTIMER_TARGET0_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET1_INT_MAP: systimer target1 intr map register + // Position of SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_SYSTIMER_TARGET1_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_SYSTIMER_TARGET1_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET2_INT_MAP: systimer target2 intr map register + // Position of SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_SYSTIMER_TARGET2_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_SYSTIMER_TARGET2_INT_MAP_Msk = 0x1f + + // SPI_MEM_REJECT_INTR_MAP: spi mem reject intr map register + // Position of SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_SPI_MEM_REJECT_INTR_MAP_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_SPI_MEM_REJECT_INTR_MAP_Msk = 0x1f + + // ICACHE_PRELOAD_INT_MAP: icache perload intr map register + // Position of ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_ICACHE_PRELOAD_INT_MAP_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_ICACHE_PRELOAD_INT_MAP_Msk = 0x1f + + // ICACHE_SYNC_INT_MAP: icache sync intr map register + // Position of ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_ICACHE_SYNC_INT_MAP_Pos = 0x0 + // Bit mask of ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_ICACHE_SYNC_INT_MAP_Msk = 0x1f + + // APB_ADC_INT_MAP: adc intr map register + // Position of APB_ADC_INT_MAP field. + INTERRUPT_CORE0_APB_ADC_INT_MAP_APB_ADC_INT_MAP_Pos = 0x0 + // Bit mask of APB_ADC_INT_MAP field. + INTERRUPT_CORE0_APB_ADC_INT_MAP_APB_ADC_INT_MAP_Msk = 0x1f + + // DMA_CH0_INT_MAP: dma ch0 intr map register + // Position of DMA_CH0_INT_MAP field. + INTERRUPT_CORE0_DMA_CH0_INT_MAP_DMA_CH0_INT_MAP_Pos = 0x0 + // Bit mask of DMA_CH0_INT_MAP field. + INTERRUPT_CORE0_DMA_CH0_INT_MAP_DMA_CH0_INT_MAP_Msk = 0x1f + + // DMA_CH1_INT_MAP: dma ch1 intr map register + // Position of DMA_CH1_INT_MAP field. + INTERRUPT_CORE0_DMA_CH1_INT_MAP_DMA_CH1_INT_MAP_Pos = 0x0 + // Bit mask of DMA_CH1_INT_MAP field. + INTERRUPT_CORE0_DMA_CH1_INT_MAP_DMA_CH1_INT_MAP_Msk = 0x1f + + // DMA_CH2_INT_MAP: dma ch2 intr map register + // Position of DMA_CH2_INT_MAP field. + INTERRUPT_CORE0_DMA_CH2_INT_MAP_DMA_CH2_INT_MAP_Pos = 0x0 + // Bit mask of DMA_CH2_INT_MAP field. + INTERRUPT_CORE0_DMA_CH2_INT_MAP_DMA_CH2_INT_MAP_Msk = 0x1f + + // RSA_INT_MAP: rsa intr map register + // Position of RSA_INT_MAP field. + INTERRUPT_CORE0_RSA_INT_MAP_RSA_INT_MAP_Pos = 0x0 + // Bit mask of RSA_INT_MAP field. + INTERRUPT_CORE0_RSA_INT_MAP_RSA_INT_MAP_Msk = 0x1f + + // AES_INT_MAP: aes intr map register + // Position of AES_INT_MAP field. + INTERRUPT_CORE0_AES_INT_MAP_AES_INT_MAP_Pos = 0x0 + // Bit mask of AES_INT_MAP field. + INTERRUPT_CORE0_AES_INT_MAP_AES_INT_MAP_Msk = 0x1f + + // SHA_INT_MAP: sha intr map register + // Position of SHA_INT_MAP field. + INTERRUPT_CORE0_SHA_INT_MAP_SHA_INT_MAP_Pos = 0x0 + // Bit mask of SHA_INT_MAP field. + INTERRUPT_CORE0_SHA_INT_MAP_SHA_INT_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_0_MAP: cpu from cpu 0 intr map register + // Position of CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_1_MAP: cpu from cpu 0 intr map register + // Position of CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_2_MAP: cpu from cpu 1 intr map register + // Position of CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_3_MAP: cpu from cpu 3 intr map register + // Position of CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Msk = 0x1f + + // ASSIST_DEBUG_INTR_MAP: assist debug intr map register + // Position of ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Pos = 0x0 + // Bit mask of ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Msk = 0x1f + + // DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: dma pms violatile intr map register + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: iram0 pms violatile intr map register + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mac intr map register + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: mac intr map register + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: mac intr map register + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Msk = 0x1f + + // BACKUP_PMS_VIOLATE_INTR_MAP: mac intr map register + // Position of BACKUP_PMS_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_BACKUP_PMS_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of BACKUP_PMS_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_BACKUP_PMS_VIOLATE_INTR_MAP_Msk = 0x1f + + // CACHE_CORE0_ACS_INT_MAP: mac intr map register + // Position of CACHE_CORE0_ACS_INT_MAP field. + INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_CACHE_CORE0_ACS_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_CORE0_ACS_INT_MAP field. + INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_CACHE_CORE0_ACS_INT_MAP_Msk = 0x1f + + // INTR_STATUS_REG_0: mac intr map register + // Position of INTR_STATUS_0 field. + INTERRUPT_CORE0_INTR_STATUS_REG_0_INTR_STATUS_0_Pos = 0x0 + // Bit mask of INTR_STATUS_0 field. + INTERRUPT_CORE0_INTR_STATUS_REG_0_INTR_STATUS_0_Msk = 0xffffffff + + // INTR_STATUS_REG_1: mac intr map register + // Position of INTR_STATUS_1 field. + INTERRUPT_CORE0_INTR_STATUS_REG_1_INTR_STATUS_1_Pos = 0x0 + // Bit mask of INTR_STATUS_1 field. + INTERRUPT_CORE0_INTR_STATUS_REG_1_INTR_STATUS_1_Msk = 0xffffffff + + // CLOCK_GATE: mac intr map register + // Position of REG_CLK_EN field. + INTERRUPT_CORE0_CLOCK_GATE_REG_CLK_EN_Pos = 0x0 + // Bit mask of REG_CLK_EN field. + INTERRUPT_CORE0_CLOCK_GATE_REG_CLK_EN_Msk = 0x1 + // Bit REG_CLK_EN. + INTERRUPT_CORE0_CLOCK_GATE_REG_CLK_EN = 0x1 + + // CPU_INT_ENABLE: mac intr map register + // Position of CPU_INT_ENABLE field. + INTERRUPT_CORE0_CPU_INT_ENABLE_CPU_INT_ENABLE_Pos = 0x0 + // Bit mask of CPU_INT_ENABLE field. + INTERRUPT_CORE0_CPU_INT_ENABLE_CPU_INT_ENABLE_Msk = 0xffffffff + + // CPU_INT_TYPE: mac intr map register + // Position of CPU_INT_TYPE field. + INTERRUPT_CORE0_CPU_INT_TYPE_CPU_INT_TYPE_Pos = 0x0 + // Bit mask of CPU_INT_TYPE field. + INTERRUPT_CORE0_CPU_INT_TYPE_CPU_INT_TYPE_Msk = 0xffffffff + + // CPU_INT_CLEAR: mac intr map register + // Position of CPU_INT_CLEAR field. + INTERRUPT_CORE0_CPU_INT_CLEAR_CPU_INT_CLEAR_Pos = 0x0 + // Bit mask of CPU_INT_CLEAR field. + INTERRUPT_CORE0_CPU_INT_CLEAR_CPU_INT_CLEAR_Msk = 0xffffffff + + // CPU_INT_EIP_STATUS: mac intr map register + // Position of CPU_INT_EIP_STATUS field. + INTERRUPT_CORE0_CPU_INT_EIP_STATUS_CPU_INT_EIP_STATUS_Pos = 0x0 + // Bit mask of CPU_INT_EIP_STATUS field. + INTERRUPT_CORE0_CPU_INT_EIP_STATUS_CPU_INT_EIP_STATUS_Msk = 0xffffffff + + // CPU_INT_PRI_0: mac intr map register + // Position of CPU_PRI_0_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_0_CPU_PRI_0_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_0_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_0_CPU_PRI_0_MAP_Msk = 0xf + + // CPU_INT_PRI_1: mac intr map register + // Position of CPU_PRI_1_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_1_CPU_PRI_1_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_1_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_1_CPU_PRI_1_MAP_Msk = 0xf + + // CPU_INT_PRI_2: mac intr map register + // Position of CPU_PRI_2_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_2_CPU_PRI_2_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_2_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_2_CPU_PRI_2_MAP_Msk = 0xf + + // CPU_INT_PRI_3: mac intr map register + // Position of CPU_PRI_3_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_3_CPU_PRI_3_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_3_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_3_CPU_PRI_3_MAP_Msk = 0xf + + // CPU_INT_PRI_4: mac intr map register + // Position of CPU_PRI_4_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_4_CPU_PRI_4_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_4_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_4_CPU_PRI_4_MAP_Msk = 0xf + + // CPU_INT_PRI_5: mac intr map register + // Position of CPU_PRI_5_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_5_CPU_PRI_5_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_5_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_5_CPU_PRI_5_MAP_Msk = 0xf + + // CPU_INT_PRI_6: mac intr map register + // Position of CPU_PRI_6_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_6_CPU_PRI_6_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_6_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_6_CPU_PRI_6_MAP_Msk = 0xf + + // CPU_INT_PRI_7: mac intr map register + // Position of CPU_PRI_7_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_7_CPU_PRI_7_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_7_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_7_CPU_PRI_7_MAP_Msk = 0xf + + // CPU_INT_PRI_8: mac intr map register + // Position of CPU_PRI_8_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_8_CPU_PRI_8_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_8_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_8_CPU_PRI_8_MAP_Msk = 0xf + + // CPU_INT_PRI_9: mac intr map register + // Position of CPU_PRI_9_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_9_CPU_PRI_9_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_9_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_9_CPU_PRI_9_MAP_Msk = 0xf + + // CPU_INT_PRI_10: mac intr map register + // Position of CPU_PRI_10_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_10_CPU_PRI_10_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_10_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_10_CPU_PRI_10_MAP_Msk = 0xf + + // CPU_INT_PRI_11: mac intr map register + // Position of CPU_PRI_11_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_11_CPU_PRI_11_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_11_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_11_CPU_PRI_11_MAP_Msk = 0xf + + // CPU_INT_PRI_12: mac intr map register + // Position of CPU_PRI_12_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_12_CPU_PRI_12_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_12_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_12_CPU_PRI_12_MAP_Msk = 0xf + + // CPU_INT_PRI_13: mac intr map register + // Position of CPU_PRI_13_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_13_CPU_PRI_13_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_13_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_13_CPU_PRI_13_MAP_Msk = 0xf + + // CPU_INT_PRI_14: mac intr map register + // Position of CPU_PRI_14_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_14_CPU_PRI_14_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_14_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_14_CPU_PRI_14_MAP_Msk = 0xf + + // CPU_INT_PRI_15: mac intr map register + // Position of CPU_PRI_15_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_15_CPU_PRI_15_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_15_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_15_CPU_PRI_15_MAP_Msk = 0xf + + // CPU_INT_PRI_16: mac intr map register + // Position of CPU_PRI_16_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_16_CPU_PRI_16_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_16_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_16_CPU_PRI_16_MAP_Msk = 0xf + + // CPU_INT_PRI_17: mac intr map register + // Position of CPU_PRI_17_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_17_CPU_PRI_17_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_17_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_17_CPU_PRI_17_MAP_Msk = 0xf + + // CPU_INT_PRI_18: mac intr map register + // Position of CPU_PRI_18_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_18_CPU_PRI_18_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_18_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_18_CPU_PRI_18_MAP_Msk = 0xf + + // CPU_INT_PRI_19: mac intr map register + // Position of CPU_PRI_19_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_19_CPU_PRI_19_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_19_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_19_CPU_PRI_19_MAP_Msk = 0xf + + // CPU_INT_PRI_20: mac intr map register + // Position of CPU_PRI_20_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_20_CPU_PRI_20_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_20_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_20_CPU_PRI_20_MAP_Msk = 0xf + + // CPU_INT_PRI_21: mac intr map register + // Position of CPU_PRI_21_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_21_CPU_PRI_21_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_21_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_21_CPU_PRI_21_MAP_Msk = 0xf + + // CPU_INT_PRI_22: mac intr map register + // Position of CPU_PRI_22_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_22_CPU_PRI_22_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_22_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_22_CPU_PRI_22_MAP_Msk = 0xf + + // CPU_INT_PRI_23: mac intr map register + // Position of CPU_PRI_23_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_23_CPU_PRI_23_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_23_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_23_CPU_PRI_23_MAP_Msk = 0xf + + // CPU_INT_PRI_24: mac intr map register + // Position of CPU_PRI_24_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_24_CPU_PRI_24_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_24_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_24_CPU_PRI_24_MAP_Msk = 0xf + + // CPU_INT_PRI_25: mac intr map register + // Position of CPU_PRI_25_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_25_CPU_PRI_25_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_25_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_25_CPU_PRI_25_MAP_Msk = 0xf + + // CPU_INT_PRI_26: mac intr map register + // Position of CPU_PRI_26_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_26_CPU_PRI_26_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_26_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_26_CPU_PRI_26_MAP_Msk = 0xf + + // CPU_INT_PRI_27: mac intr map register + // Position of CPU_PRI_27_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_27_CPU_PRI_27_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_27_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_27_CPU_PRI_27_MAP_Msk = 0xf + + // CPU_INT_PRI_28: mac intr map register + // Position of CPU_PRI_28_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_28_CPU_PRI_28_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_28_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_28_CPU_PRI_28_MAP_Msk = 0xf + + // CPU_INT_PRI_29: mac intr map register + // Position of CPU_PRI_29_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_29_CPU_PRI_29_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_29_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_29_CPU_PRI_29_MAP_Msk = 0xf + + // CPU_INT_PRI_30: mac intr map register + // Position of CPU_PRI_30_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_30_CPU_PRI_30_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_30_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_30_CPU_PRI_30_MAP_Msk = 0xf + + // CPU_INT_PRI_31: mac intr map register + // Position of CPU_PRI_31_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_31_CPU_PRI_31_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_31_MAP field. + INTERRUPT_CORE0_CPU_INT_PRI_31_CPU_PRI_31_MAP_Msk = 0xf + + // CPU_INT_THRESH: mac intr map register + // Position of CPU_INT_THRESH field. + INTERRUPT_CORE0_CPU_INT_THRESH_CPU_INT_THRESH_Pos = 0x0 + // Bit mask of CPU_INT_THRESH field. + INTERRUPT_CORE0_CPU_INT_THRESH_CPU_INT_THRESH_Msk = 0xf + + // INTERRUPT_REG_DATE: mac intr map register + // Position of INTERRUPT_REG_DATE field. + INTERRUPT_CORE0_INTERRUPT_REG_DATE_INTERRUPT_REG_DATE_Pos = 0x0 + // Bit mask of INTERRUPT_REG_DATE field. + INTERRUPT_CORE0_INTERRUPT_REG_DATE_INTERRUPT_REG_DATE_Msk = 0xfffffff +) + +// Constants for IO_MUX: Input/Output Multiplexer +const ( + // PIN_CTRL: Clock Output Configuration Register + // Position of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Pos = 0x0 + // Bit mask of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Msk = 0xf + // Position of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Pos = 0x4 + // Bit mask of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Msk = 0xf0 + // Position of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Pos = 0x8 + // Bit mask of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Msk = 0xf00 + + // GPIO0: IO MUX Configure Register for pad XTAL_32K_P + // Position of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO_FILTER_EN = 0x8000 + + // DATE: IO MUX Version Control Register + // Position of REG_DATE field. + IO_MUX_DATE_REG_DATE_Pos = 0x0 + // Bit mask of REG_DATE field. + IO_MUX_DATE_REG_DATE_Msk = 0xfffffff +) + +// Constants for LEDC: LED Control PWM (Pulse Width Modulation) +const ( + // CH0_CONF0: LEDC_LSCH%s_CONF%s. + // Position of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Pos = 0x0 + // Bit mask of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Msk = 0x3 + // Position of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Pos = 0x2 + // Bit mask of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Msk = 0x4 + // Bit SIG_OUT_EN. + LEDC_CH_CONF0_SIG_OUT_EN = 0x4 + // Position of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Pos = 0x3 + // Bit mask of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Msk = 0x8 + // Bit IDLE_LV. + LEDC_CH_CONF0_IDLE_LV = 0x8 + // Position of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Pos = 0x4 + // Bit mask of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Msk = 0x10 + // Bit PARA_UP. + LEDC_CH_CONF0_PARA_UP = 0x10 + // Position of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Pos = 0x5 + // Bit mask of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Msk = 0x7fe0 + // Position of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Pos = 0xf + // Bit mask of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Msk = 0x8000 + // Bit OVF_CNT_EN. + LEDC_CH_CONF0_OVF_CNT_EN = 0x8000 + // Position of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Pos = 0x10 + // Bit mask of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Msk = 0x10000 + // Bit OVF_CNT_RESET. + LEDC_CH_CONF0_OVF_CNT_RESET = 0x10000 + + // CH0_HPOINT: LEDC_LSCH%s_HPOINT. + // Position of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Pos = 0x0 + // Bit mask of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Msk = 0x3fff + + // CH0_DUTY: LEDC_LSCH%s_DUTY. + // Position of DUTY field. + LEDC_CH_DUTY_DUTY_Pos = 0x0 + // Bit mask of DUTY field. + LEDC_CH_DUTY_DUTY_Msk = 0x7ffff + + // CH0_CONF1: LEDC_LSCH%s_CONF1. + // Position of DUTY_SCALE field. + LEDC_CH_CONF1_DUTY_SCALE_Pos = 0x0 + // Bit mask of DUTY_SCALE field. + LEDC_CH_CONF1_DUTY_SCALE_Msk = 0x3ff + // Position of DUTY_CYCLE field. + LEDC_CH_CONF1_DUTY_CYCLE_Pos = 0xa + // Bit mask of DUTY_CYCLE field. + LEDC_CH_CONF1_DUTY_CYCLE_Msk = 0xffc00 + // Position of DUTY_NUM field. + LEDC_CH_CONF1_DUTY_NUM_Pos = 0x14 + // Bit mask of DUTY_NUM field. + LEDC_CH_CONF1_DUTY_NUM_Msk = 0x3ff00000 + // Position of DUTY_INC field. + LEDC_CH_CONF1_DUTY_INC_Pos = 0x1e + // Bit mask of DUTY_INC field. + LEDC_CH_CONF1_DUTY_INC_Msk = 0x40000000 + // Bit DUTY_INC. + LEDC_CH_CONF1_DUTY_INC = 0x40000000 + // Position of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Pos = 0x1f + // Bit mask of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Msk = 0x80000000 + // Bit DUTY_START. + LEDC_CH_CONF1_DUTY_START = 0x80000000 + + // CH0_DUTY_R: LEDC_LSCH%s_DUTY_R. + // Position of DUTY_R field. + LEDC_CH_DUTY_R_DUTY_R_Pos = 0x0 + // Bit mask of DUTY_R field. + LEDC_CH_DUTY_R_DUTY_R_Msk = 0x7ffff + + // TIMER0_CONF: LEDC_LSTIMER%s_CONF. + // Position of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Pos = 0x0 + // Bit mask of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Msk = 0xf + // Position of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Pos = 0x4 + // Bit mask of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Msk = 0x3ffff0 + // Position of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Pos = 0x16 + // Bit mask of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Msk = 0x400000 + // Bit PAUSE. + LEDC_TIMER_CONF_PAUSE = 0x400000 + // Position of RST field. + LEDC_TIMER_CONF_RST_Pos = 0x17 + // Bit mask of RST field. + LEDC_TIMER_CONF_RST_Msk = 0x800000 + // Bit RST. + LEDC_TIMER_CONF_RST = 0x800000 + // Position of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Pos = 0x18 + // Bit mask of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Msk = 0x1000000 + // Bit TICK_SEL. + LEDC_TIMER_CONF_TICK_SEL = 0x1000000 + // Position of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Pos = 0x19 + // Bit mask of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Msk = 0x2000000 + // Bit PARA_UP. + LEDC_TIMER_CONF_PARA_UP = 0x2000000 + + // TIMER0_VALUE: LEDC_LSTIMER%s_VALUE. + // Position of CNT field. + LEDC_TIMER_VALUE_CNT_Pos = 0x0 + // Bit mask of CNT field. + LEDC_TIMER_VALUE_CNT_Msk = 0x3fff + + // INT_RAW: LEDC_INT_RAW. + // Position of LSTIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER0_OVF_INT_RAW_Pos = 0x0 + // Bit mask of LSTIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER0_OVF_INT_RAW_Msk = 0x1 + // Bit LSTIMER0_OVF_INT_RAW. + LEDC_INT_RAW_LSTIMER0_OVF_INT_RAW = 0x1 + // Position of LSTIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER1_OVF_INT_RAW_Pos = 0x1 + // Bit mask of LSTIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER1_OVF_INT_RAW_Msk = 0x2 + // Bit LSTIMER1_OVF_INT_RAW. + LEDC_INT_RAW_LSTIMER1_OVF_INT_RAW = 0x2 + // Position of LSTIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER2_OVF_INT_RAW_Pos = 0x2 + // Bit mask of LSTIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER2_OVF_INT_RAW_Msk = 0x4 + // Bit LSTIMER2_OVF_INT_RAW. + LEDC_INT_RAW_LSTIMER2_OVF_INT_RAW = 0x4 + // Position of LSTIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER3_OVF_INT_RAW_Pos = 0x3 + // Bit mask of LSTIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_LSTIMER3_OVF_INT_RAW_Msk = 0x8 + // Bit LSTIMER3_OVF_INT_RAW. + LEDC_INT_RAW_LSTIMER3_OVF_INT_RAW = 0x8 + // Position of DUTY_CHNG_END_LSCH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_LSCH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW_Msk = 0x10 + // Bit DUTY_CHNG_END_LSCH0_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH0_INT_RAW = 0x10 + // Position of DUTY_CHNG_END_LSCH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_LSCH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW_Msk = 0x20 + // Bit DUTY_CHNG_END_LSCH1_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH1_INT_RAW = 0x20 + // Position of DUTY_CHNG_END_LSCH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_LSCH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW_Msk = 0x40 + // Bit DUTY_CHNG_END_LSCH2_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH2_INT_RAW = 0x40 + // Position of DUTY_CHNG_END_LSCH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_LSCH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW_Msk = 0x80 + // Bit DUTY_CHNG_END_LSCH3_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH3_INT_RAW = 0x80 + // Position of DUTY_CHNG_END_LSCH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_LSCH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW_Msk = 0x100 + // Bit DUTY_CHNG_END_LSCH4_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH4_INT_RAW = 0x100 + // Position of DUTY_CHNG_END_LSCH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_LSCH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW_Msk = 0x200 + // Bit DUTY_CHNG_END_LSCH5_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_LSCH5_INT_RAW = 0x200 + // Position of OVF_CNT_LSCH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH0_INT_RAW_Pos = 0xa + // Bit mask of OVF_CNT_LSCH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH0_INT_RAW_Msk = 0x400 + // Bit OVF_CNT_LSCH0_INT_RAW. + LEDC_INT_RAW_OVF_CNT_LSCH0_INT_RAW = 0x400 + // Position of OVF_CNT_LSCH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH1_INT_RAW_Pos = 0xb + // Bit mask of OVF_CNT_LSCH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH1_INT_RAW_Msk = 0x800 + // Bit OVF_CNT_LSCH1_INT_RAW. + LEDC_INT_RAW_OVF_CNT_LSCH1_INT_RAW = 0x800 + // Position of OVF_CNT_LSCH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH2_INT_RAW_Pos = 0xc + // Bit mask of OVF_CNT_LSCH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH2_INT_RAW_Msk = 0x1000 + // Bit OVF_CNT_LSCH2_INT_RAW. + LEDC_INT_RAW_OVF_CNT_LSCH2_INT_RAW = 0x1000 + // Position of OVF_CNT_LSCH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH3_INT_RAW_Pos = 0xd + // Bit mask of OVF_CNT_LSCH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH3_INT_RAW_Msk = 0x2000 + // Bit OVF_CNT_LSCH3_INT_RAW. + LEDC_INT_RAW_OVF_CNT_LSCH3_INT_RAW = 0x2000 + // Position of OVF_CNT_LSCH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH4_INT_RAW_Pos = 0xe + // Bit mask of OVF_CNT_LSCH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH4_INT_RAW_Msk = 0x4000 + // Bit OVF_CNT_LSCH4_INT_RAW. + LEDC_INT_RAW_OVF_CNT_LSCH4_INT_RAW = 0x4000 + // Position of OVF_CNT_LSCH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH5_INT_RAW_Pos = 0xf + // Bit mask of OVF_CNT_LSCH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_LSCH5_INT_RAW_Msk = 0x8000 + // Bit OVF_CNT_LSCH5_INT_RAW. + LEDC_INT_RAW_OVF_CNT_LSCH5_INT_RAW = 0x8000 + + // INT_ST: LEDC_INT_ST. + // Position of LSTIMER0_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER0_OVF_INT_ST_Pos = 0x0 + // Bit mask of LSTIMER0_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER0_OVF_INT_ST_Msk = 0x1 + // Bit LSTIMER0_OVF_INT_ST. + LEDC_INT_ST_LSTIMER0_OVF_INT_ST = 0x1 + // Position of LSTIMER1_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER1_OVF_INT_ST_Pos = 0x1 + // Bit mask of LSTIMER1_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER1_OVF_INT_ST_Msk = 0x2 + // Bit LSTIMER1_OVF_INT_ST. + LEDC_INT_ST_LSTIMER1_OVF_INT_ST = 0x2 + // Position of LSTIMER2_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER2_OVF_INT_ST_Pos = 0x2 + // Bit mask of LSTIMER2_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER2_OVF_INT_ST_Msk = 0x4 + // Bit LSTIMER2_OVF_INT_ST. + LEDC_INT_ST_LSTIMER2_OVF_INT_ST = 0x4 + // Position of LSTIMER3_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER3_OVF_INT_ST_Pos = 0x3 + // Bit mask of LSTIMER3_OVF_INT_ST field. + LEDC_INT_ST_LSTIMER3_OVF_INT_ST_Msk = 0x8 + // Bit LSTIMER3_OVF_INT_ST. + LEDC_INT_ST_LSTIMER3_OVF_INT_ST = 0x8 + // Position of DUTY_CHNG_END_LSCH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH0_INT_ST_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_LSCH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH0_INT_ST_Msk = 0x10 + // Bit DUTY_CHNG_END_LSCH0_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH0_INT_ST = 0x10 + // Position of DUTY_CHNG_END_LSCH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH1_INT_ST_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_LSCH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH1_INT_ST_Msk = 0x20 + // Bit DUTY_CHNG_END_LSCH1_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH1_INT_ST = 0x20 + // Position of DUTY_CHNG_END_LSCH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH2_INT_ST_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_LSCH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH2_INT_ST_Msk = 0x40 + // Bit DUTY_CHNG_END_LSCH2_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH2_INT_ST = 0x40 + // Position of DUTY_CHNG_END_LSCH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH3_INT_ST_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_LSCH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH3_INT_ST_Msk = 0x80 + // Bit DUTY_CHNG_END_LSCH3_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH3_INT_ST = 0x80 + // Position of DUTY_CHNG_END_LSCH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH4_INT_ST_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_LSCH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH4_INT_ST_Msk = 0x100 + // Bit DUTY_CHNG_END_LSCH4_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH4_INT_ST = 0x100 + // Position of DUTY_CHNG_END_LSCH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH5_INT_ST_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_LSCH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_LSCH5_INT_ST_Msk = 0x200 + // Bit DUTY_CHNG_END_LSCH5_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_LSCH5_INT_ST = 0x200 + // Position of OVF_CNT_LSCH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH0_INT_ST_Pos = 0xa + // Bit mask of OVF_CNT_LSCH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH0_INT_ST_Msk = 0x400 + // Bit OVF_CNT_LSCH0_INT_ST. + LEDC_INT_ST_OVF_CNT_LSCH0_INT_ST = 0x400 + // Position of OVF_CNT_LSCH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH1_INT_ST_Pos = 0xb + // Bit mask of OVF_CNT_LSCH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH1_INT_ST_Msk = 0x800 + // Bit OVF_CNT_LSCH1_INT_ST. + LEDC_INT_ST_OVF_CNT_LSCH1_INT_ST = 0x800 + // Position of OVF_CNT_LSCH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH2_INT_ST_Pos = 0xc + // Bit mask of OVF_CNT_LSCH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH2_INT_ST_Msk = 0x1000 + // Bit OVF_CNT_LSCH2_INT_ST. + LEDC_INT_ST_OVF_CNT_LSCH2_INT_ST = 0x1000 + // Position of OVF_CNT_LSCH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH3_INT_ST_Pos = 0xd + // Bit mask of OVF_CNT_LSCH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH3_INT_ST_Msk = 0x2000 + // Bit OVF_CNT_LSCH3_INT_ST. + LEDC_INT_ST_OVF_CNT_LSCH3_INT_ST = 0x2000 + // Position of OVF_CNT_LSCH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH4_INT_ST_Pos = 0xe + // Bit mask of OVF_CNT_LSCH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH4_INT_ST_Msk = 0x4000 + // Bit OVF_CNT_LSCH4_INT_ST. + LEDC_INT_ST_OVF_CNT_LSCH4_INT_ST = 0x4000 + // Position of OVF_CNT_LSCH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH5_INT_ST_Pos = 0xf + // Bit mask of OVF_CNT_LSCH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_LSCH5_INT_ST_Msk = 0x8000 + // Bit OVF_CNT_LSCH5_INT_ST. + LEDC_INT_ST_OVF_CNT_LSCH5_INT_ST = 0x8000 + + // INT_ENA: LEDC_INT_ENA. + // Position of LSTIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER0_OVF_INT_ENA_Pos = 0x0 + // Bit mask of LSTIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER0_OVF_INT_ENA_Msk = 0x1 + // Bit LSTIMER0_OVF_INT_ENA. + LEDC_INT_ENA_LSTIMER0_OVF_INT_ENA = 0x1 + // Position of LSTIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER1_OVF_INT_ENA_Pos = 0x1 + // Bit mask of LSTIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER1_OVF_INT_ENA_Msk = 0x2 + // Bit LSTIMER1_OVF_INT_ENA. + LEDC_INT_ENA_LSTIMER1_OVF_INT_ENA = 0x2 + // Position of LSTIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER2_OVF_INT_ENA_Pos = 0x2 + // Bit mask of LSTIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER2_OVF_INT_ENA_Msk = 0x4 + // Bit LSTIMER2_OVF_INT_ENA. + LEDC_INT_ENA_LSTIMER2_OVF_INT_ENA = 0x4 + // Position of LSTIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER3_OVF_INT_ENA_Pos = 0x3 + // Bit mask of LSTIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_LSTIMER3_OVF_INT_ENA_Msk = 0x8 + // Bit LSTIMER3_OVF_INT_ENA. + LEDC_INT_ENA_LSTIMER3_OVF_INT_ENA = 0x8 + // Position of DUTY_CHNG_END_LSCH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_LSCH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA_Msk = 0x10 + // Bit DUTY_CHNG_END_LSCH0_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH0_INT_ENA = 0x10 + // Position of DUTY_CHNG_END_LSCH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_LSCH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA_Msk = 0x20 + // Bit DUTY_CHNG_END_LSCH1_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH1_INT_ENA = 0x20 + // Position of DUTY_CHNG_END_LSCH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_LSCH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA_Msk = 0x40 + // Bit DUTY_CHNG_END_LSCH2_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH2_INT_ENA = 0x40 + // Position of DUTY_CHNG_END_LSCH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_LSCH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA_Msk = 0x80 + // Bit DUTY_CHNG_END_LSCH3_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH3_INT_ENA = 0x80 + // Position of DUTY_CHNG_END_LSCH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_LSCH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA_Msk = 0x100 + // Bit DUTY_CHNG_END_LSCH4_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH4_INT_ENA = 0x100 + // Position of DUTY_CHNG_END_LSCH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_LSCH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA_Msk = 0x200 + // Bit DUTY_CHNG_END_LSCH5_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_LSCH5_INT_ENA = 0x200 + // Position of OVF_CNT_LSCH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH0_INT_ENA_Pos = 0xa + // Bit mask of OVF_CNT_LSCH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH0_INT_ENA_Msk = 0x400 + // Bit OVF_CNT_LSCH0_INT_ENA. + LEDC_INT_ENA_OVF_CNT_LSCH0_INT_ENA = 0x400 + // Position of OVF_CNT_LSCH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH1_INT_ENA_Pos = 0xb + // Bit mask of OVF_CNT_LSCH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH1_INT_ENA_Msk = 0x800 + // Bit OVF_CNT_LSCH1_INT_ENA. + LEDC_INT_ENA_OVF_CNT_LSCH1_INT_ENA = 0x800 + // Position of OVF_CNT_LSCH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH2_INT_ENA_Pos = 0xc + // Bit mask of OVF_CNT_LSCH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH2_INT_ENA_Msk = 0x1000 + // Bit OVF_CNT_LSCH2_INT_ENA. + LEDC_INT_ENA_OVF_CNT_LSCH2_INT_ENA = 0x1000 + // Position of OVF_CNT_LSCH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH3_INT_ENA_Pos = 0xd + // Bit mask of OVF_CNT_LSCH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH3_INT_ENA_Msk = 0x2000 + // Bit OVF_CNT_LSCH3_INT_ENA. + LEDC_INT_ENA_OVF_CNT_LSCH3_INT_ENA = 0x2000 + // Position of OVF_CNT_LSCH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH4_INT_ENA_Pos = 0xe + // Bit mask of OVF_CNT_LSCH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH4_INT_ENA_Msk = 0x4000 + // Bit OVF_CNT_LSCH4_INT_ENA. + LEDC_INT_ENA_OVF_CNT_LSCH4_INT_ENA = 0x4000 + // Position of OVF_CNT_LSCH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH5_INT_ENA_Pos = 0xf + // Bit mask of OVF_CNT_LSCH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_LSCH5_INT_ENA_Msk = 0x8000 + // Bit OVF_CNT_LSCH5_INT_ENA. + LEDC_INT_ENA_OVF_CNT_LSCH5_INT_ENA = 0x8000 + + // INT_CLR: LEDC_INT_CLR. + // Position of LSTIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER0_OVF_INT_CLR_Pos = 0x0 + // Bit mask of LSTIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER0_OVF_INT_CLR_Msk = 0x1 + // Bit LSTIMER0_OVF_INT_CLR. + LEDC_INT_CLR_LSTIMER0_OVF_INT_CLR = 0x1 + // Position of LSTIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER1_OVF_INT_CLR_Pos = 0x1 + // Bit mask of LSTIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER1_OVF_INT_CLR_Msk = 0x2 + // Bit LSTIMER1_OVF_INT_CLR. + LEDC_INT_CLR_LSTIMER1_OVF_INT_CLR = 0x2 + // Position of LSTIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER2_OVF_INT_CLR_Pos = 0x2 + // Bit mask of LSTIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER2_OVF_INT_CLR_Msk = 0x4 + // Bit LSTIMER2_OVF_INT_CLR. + LEDC_INT_CLR_LSTIMER2_OVF_INT_CLR = 0x4 + // Position of LSTIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER3_OVF_INT_CLR_Pos = 0x3 + // Bit mask of LSTIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_LSTIMER3_OVF_INT_CLR_Msk = 0x8 + // Bit LSTIMER3_OVF_INT_CLR. + LEDC_INT_CLR_LSTIMER3_OVF_INT_CLR = 0x8 + // Position of DUTY_CHNG_END_LSCH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_LSCH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR_Msk = 0x10 + // Bit DUTY_CHNG_END_LSCH0_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH0_INT_CLR = 0x10 + // Position of DUTY_CHNG_END_LSCH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_LSCH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR_Msk = 0x20 + // Bit DUTY_CHNG_END_LSCH1_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH1_INT_CLR = 0x20 + // Position of DUTY_CHNG_END_LSCH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_LSCH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR_Msk = 0x40 + // Bit DUTY_CHNG_END_LSCH2_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH2_INT_CLR = 0x40 + // Position of DUTY_CHNG_END_LSCH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_LSCH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR_Msk = 0x80 + // Bit DUTY_CHNG_END_LSCH3_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH3_INT_CLR = 0x80 + // Position of DUTY_CHNG_END_LSCH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_LSCH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR_Msk = 0x100 + // Bit DUTY_CHNG_END_LSCH4_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH4_INT_CLR = 0x100 + // Position of DUTY_CHNG_END_LSCH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_LSCH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR_Msk = 0x200 + // Bit DUTY_CHNG_END_LSCH5_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_LSCH5_INT_CLR = 0x200 + // Position of OVF_CNT_LSCH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH0_INT_CLR_Pos = 0xa + // Bit mask of OVF_CNT_LSCH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH0_INT_CLR_Msk = 0x400 + // Bit OVF_CNT_LSCH0_INT_CLR. + LEDC_INT_CLR_OVF_CNT_LSCH0_INT_CLR = 0x400 + // Position of OVF_CNT_LSCH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH1_INT_CLR_Pos = 0xb + // Bit mask of OVF_CNT_LSCH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH1_INT_CLR_Msk = 0x800 + // Bit OVF_CNT_LSCH1_INT_CLR. + LEDC_INT_CLR_OVF_CNT_LSCH1_INT_CLR = 0x800 + // Position of OVF_CNT_LSCH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH2_INT_CLR_Pos = 0xc + // Bit mask of OVF_CNT_LSCH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH2_INT_CLR_Msk = 0x1000 + // Bit OVF_CNT_LSCH2_INT_CLR. + LEDC_INT_CLR_OVF_CNT_LSCH2_INT_CLR = 0x1000 + // Position of OVF_CNT_LSCH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH3_INT_CLR_Pos = 0xd + // Bit mask of OVF_CNT_LSCH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH3_INT_CLR_Msk = 0x2000 + // Bit OVF_CNT_LSCH3_INT_CLR. + LEDC_INT_CLR_OVF_CNT_LSCH3_INT_CLR = 0x2000 + // Position of OVF_CNT_LSCH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH4_INT_CLR_Pos = 0xe + // Bit mask of OVF_CNT_LSCH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH4_INT_CLR_Msk = 0x4000 + // Bit OVF_CNT_LSCH4_INT_CLR. + LEDC_INT_CLR_OVF_CNT_LSCH4_INT_CLR = 0x4000 + // Position of OVF_CNT_LSCH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH5_INT_CLR_Pos = 0xf + // Bit mask of OVF_CNT_LSCH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_LSCH5_INT_CLR_Msk = 0x8000 + // Bit OVF_CNT_LSCH5_INT_CLR. + LEDC_INT_CLR_OVF_CNT_LSCH5_INT_CLR = 0x8000 + + // CONF: LEDC_CONF. + // Position of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Pos = 0x0 + // Bit mask of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Msk = 0x3 + // Position of CLK_EN field. + LEDC_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LEDC_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LEDC_CONF_CLK_EN = 0x80000000 + + // DATE: LEDC_DATE. + // Position of LEDC_DATE field. + LEDC_DATE_LEDC_DATE_Pos = 0x0 + // Bit mask of LEDC_DATE field. + LEDC_DATE_LEDC_DATE_Msk = 0xffffffff +) + +// Constants for RMT: Remote Control +const ( + // CH0DATA: RMT_CH%sDATA_REG. + // Position of DATA field. + RMT_CHDATA_DATA_Pos = 0x0 + // Bit mask of DATA field. + RMT_CHDATA_DATA_Msk = 0xffffffff + + // CH0_TX_CONF0: RMT_CH%sCONF%s_REG. + // Position of TX_START field. + RMT_CH_TX_CONF0_TX_START_Pos = 0x0 + // Bit mask of TX_START field. + RMT_CH_TX_CONF0_TX_START_Msk = 0x1 + // Bit TX_START. + RMT_CH_TX_CONF0_TX_START = 0x1 + // Position of MEM_RD_RST field. + RMT_CH_TX_CONF0_MEM_RD_RST_Pos = 0x1 + // Bit mask of MEM_RD_RST field. + RMT_CH_TX_CONF0_MEM_RD_RST_Msk = 0x2 + // Bit MEM_RD_RST. + RMT_CH_TX_CONF0_MEM_RD_RST = 0x2 + // Position of APB_MEM_RST field. + RMT_CH_TX_CONF0_APB_MEM_RST_Pos = 0x2 + // Bit mask of APB_MEM_RST field. + RMT_CH_TX_CONF0_APB_MEM_RST_Msk = 0x4 + // Bit APB_MEM_RST. + RMT_CH_TX_CONF0_APB_MEM_RST = 0x4 + // Position of TX_CONTI_MODE field. + RMT_CH_TX_CONF0_TX_CONTI_MODE_Pos = 0x3 + // Bit mask of TX_CONTI_MODE field. + RMT_CH_TX_CONF0_TX_CONTI_MODE_Msk = 0x8 + // Bit TX_CONTI_MODE. + RMT_CH_TX_CONF0_TX_CONTI_MODE = 0x8 + // Position of MEM_TX_WRAP_EN field. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN_Pos = 0x4 + // Bit mask of MEM_TX_WRAP_EN field. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN_Msk = 0x10 + // Bit MEM_TX_WRAP_EN. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN = 0x10 + // Position of IDLE_OUT_LV field. + RMT_CH_TX_CONF0_IDLE_OUT_LV_Pos = 0x5 + // Bit mask of IDLE_OUT_LV field. + RMT_CH_TX_CONF0_IDLE_OUT_LV_Msk = 0x20 + // Bit IDLE_OUT_LV. + RMT_CH_TX_CONF0_IDLE_OUT_LV = 0x20 + // Position of IDLE_OUT_EN field. + RMT_CH_TX_CONF0_IDLE_OUT_EN_Pos = 0x6 + // Bit mask of IDLE_OUT_EN field. + RMT_CH_TX_CONF0_IDLE_OUT_EN_Msk = 0x40 + // Bit IDLE_OUT_EN. + RMT_CH_TX_CONF0_IDLE_OUT_EN = 0x40 + // Position of TX_STOP field. + RMT_CH_TX_CONF0_TX_STOP_Pos = 0x7 + // Bit mask of TX_STOP field. + RMT_CH_TX_CONF0_TX_STOP_Msk = 0x80 + // Bit TX_STOP. + RMT_CH_TX_CONF0_TX_STOP = 0x80 + // Position of DIV_CNT field. + RMT_CH_TX_CONF0_DIV_CNT_Pos = 0x8 + // Bit mask of DIV_CNT field. + RMT_CH_TX_CONF0_DIV_CNT_Msk = 0xff00 + // Position of MEM_SIZE field. + RMT_CH_TX_CONF0_MEM_SIZE_Pos = 0x10 + // Bit mask of MEM_SIZE field. + RMT_CH_TX_CONF0_MEM_SIZE_Msk = 0x70000 + // Position of CARRIER_EFF_EN field. + RMT_CH_TX_CONF0_CARRIER_EFF_EN_Pos = 0x14 + // Bit mask of CARRIER_EFF_EN field. + RMT_CH_TX_CONF0_CARRIER_EFF_EN_Msk = 0x100000 + // Bit CARRIER_EFF_EN. + RMT_CH_TX_CONF0_CARRIER_EFF_EN = 0x100000 + // Position of CARRIER_EN field. + RMT_CH_TX_CONF0_CARRIER_EN_Pos = 0x15 + // Bit mask of CARRIER_EN field. + RMT_CH_TX_CONF0_CARRIER_EN_Msk = 0x200000 + // Bit CARRIER_EN. + RMT_CH_TX_CONF0_CARRIER_EN = 0x200000 + // Position of CARRIER_OUT_LV field. + RMT_CH_TX_CONF0_CARRIER_OUT_LV_Pos = 0x16 + // Bit mask of CARRIER_OUT_LV field. + RMT_CH_TX_CONF0_CARRIER_OUT_LV_Msk = 0x400000 + // Bit CARRIER_OUT_LV. + RMT_CH_TX_CONF0_CARRIER_OUT_LV = 0x400000 + // Position of AFIFO_RST field. + RMT_CH_TX_CONF0_AFIFO_RST_Pos = 0x17 + // Bit mask of AFIFO_RST field. + RMT_CH_TX_CONF0_AFIFO_RST_Msk = 0x800000 + // Bit AFIFO_RST. + RMT_CH_TX_CONF0_AFIFO_RST = 0x800000 + // Position of CONF_UPDATE field. + RMT_CH_TX_CONF0_CONF_UPDATE_Pos = 0x18 + // Bit mask of CONF_UPDATE field. + RMT_CH_TX_CONF0_CONF_UPDATE_Msk = 0x1000000 + // Bit CONF_UPDATE. + RMT_CH_TX_CONF0_CONF_UPDATE = 0x1000000 + + // CH2_RX_CONF0: RMT_CH2CONF0_REG. + // Position of DIV_CNT field. + RMT_CH_RX_CONF0_DIV_CNT_Pos = 0x0 + // Bit mask of DIV_CNT field. + RMT_CH_RX_CONF0_DIV_CNT_Msk = 0xff + // Position of IDLE_THRES field. + RMT_CH_RX_CONF0_IDLE_THRES_Pos = 0x8 + // Bit mask of IDLE_THRES field. + RMT_CH_RX_CONF0_IDLE_THRES_Msk = 0x7fff00 + // Position of MEM_SIZE field. + RMT_CH_RX_CONF0_MEM_SIZE_Pos = 0x17 + // Bit mask of MEM_SIZE field. + RMT_CH_RX_CONF0_MEM_SIZE_Msk = 0x3800000 + // Position of CARRIER_EN field. + RMT_CH_RX_CONF0_CARRIER_EN_Pos = 0x1c + // Bit mask of CARRIER_EN field. + RMT_CH_RX_CONF0_CARRIER_EN_Msk = 0x10000000 + // Bit CARRIER_EN. + RMT_CH_RX_CONF0_CARRIER_EN = 0x10000000 + // Position of CARRIER_OUT_LV field. + RMT_CH_RX_CONF0_CARRIER_OUT_LV_Pos = 0x1d + // Bit mask of CARRIER_OUT_LV field. + RMT_CH_RX_CONF0_CARRIER_OUT_LV_Msk = 0x20000000 + // Bit CARRIER_OUT_LV. + RMT_CH_RX_CONF0_CARRIER_OUT_LV = 0x20000000 + + // CH2_RX_CONF1: RMT_CH2CONF1_REG. + // Position of RX_EN field. + RMT_CH_RX_CONF1_RX_EN_Pos = 0x0 + // Bit mask of RX_EN field. + RMT_CH_RX_CONF1_RX_EN_Msk = 0x1 + // Bit RX_EN. + RMT_CH_RX_CONF1_RX_EN = 0x1 + // Position of MEM_WR_RST field. + RMT_CH_RX_CONF1_MEM_WR_RST_Pos = 0x1 + // Bit mask of MEM_WR_RST field. + RMT_CH_RX_CONF1_MEM_WR_RST_Msk = 0x2 + // Bit MEM_WR_RST. + RMT_CH_RX_CONF1_MEM_WR_RST = 0x2 + // Position of APB_MEM_RST field. + RMT_CH_RX_CONF1_APB_MEM_RST_Pos = 0x2 + // Bit mask of APB_MEM_RST field. + RMT_CH_RX_CONF1_APB_MEM_RST_Msk = 0x4 + // Bit APB_MEM_RST. + RMT_CH_RX_CONF1_APB_MEM_RST = 0x4 + // Position of MEM_OWNER field. + RMT_CH_RX_CONF1_MEM_OWNER_Pos = 0x3 + // Bit mask of MEM_OWNER field. + RMT_CH_RX_CONF1_MEM_OWNER_Msk = 0x8 + // Bit MEM_OWNER. + RMT_CH_RX_CONF1_MEM_OWNER = 0x8 + // Position of RX_FILTER_EN field. + RMT_CH_RX_CONF1_RX_FILTER_EN_Pos = 0x4 + // Bit mask of RX_FILTER_EN field. + RMT_CH_RX_CONF1_RX_FILTER_EN_Msk = 0x10 + // Bit RX_FILTER_EN. + RMT_CH_RX_CONF1_RX_FILTER_EN = 0x10 + // Position of RX_FILTER_THRES field. + RMT_CH_RX_CONF1_RX_FILTER_THRES_Pos = 0x5 + // Bit mask of RX_FILTER_THRES field. + RMT_CH_RX_CONF1_RX_FILTER_THRES_Msk = 0x1fe0 + // Position of MEM_RX_WRAP_EN field. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN_Pos = 0xd + // Bit mask of MEM_RX_WRAP_EN field. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN_Msk = 0x2000 + // Bit MEM_RX_WRAP_EN. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN = 0x2000 + // Position of AFIFO_RST field. + RMT_CH_RX_CONF1_AFIFO_RST_Pos = 0xe + // Bit mask of AFIFO_RST field. + RMT_CH_RX_CONF1_AFIFO_RST_Msk = 0x4000 + // Bit AFIFO_RST. + RMT_CH_RX_CONF1_AFIFO_RST = 0x4000 + // Position of CONF_UPDATE field. + RMT_CH_RX_CONF1_CONF_UPDATE_Pos = 0xf + // Bit mask of CONF_UPDATE field. + RMT_CH_RX_CONF1_CONF_UPDATE_Msk = 0x8000 + // Bit CONF_UPDATE. + RMT_CH_RX_CONF1_CONF_UPDATE = 0x8000 + + // CH0_TX_STATUS: RMT_CH%sSTATUS_REG. + // Position of MEM_RADDR_EX field. + RMT_CH_TX_STATUS_MEM_RADDR_EX_Pos = 0x0 + // Bit mask of MEM_RADDR_EX field. + RMT_CH_TX_STATUS_MEM_RADDR_EX_Msk = 0x1ff + // Position of STATE field. + RMT_CH_TX_STATUS_STATE_Pos = 0x9 + // Bit mask of STATE field. + RMT_CH_TX_STATUS_STATE_Msk = 0xe00 + // Position of APB_MEM_WADDR field. + RMT_CH_TX_STATUS_APB_MEM_WADDR_Pos = 0xc + // Bit mask of APB_MEM_WADDR field. + RMT_CH_TX_STATUS_APB_MEM_WADDR_Msk = 0x1ff000 + // Position of APB_MEM_RD_ERR field. + RMT_CH_TX_STATUS_APB_MEM_RD_ERR_Pos = 0x15 + // Bit mask of APB_MEM_RD_ERR field. + RMT_CH_TX_STATUS_APB_MEM_RD_ERR_Msk = 0x200000 + // Bit APB_MEM_RD_ERR. + RMT_CH_TX_STATUS_APB_MEM_RD_ERR = 0x200000 + // Position of MEM_EMPTY field. + RMT_CH_TX_STATUS_MEM_EMPTY_Pos = 0x16 + // Bit mask of MEM_EMPTY field. + RMT_CH_TX_STATUS_MEM_EMPTY_Msk = 0x400000 + // Bit MEM_EMPTY. + RMT_CH_TX_STATUS_MEM_EMPTY = 0x400000 + // Position of APB_MEM_WR_ERR field. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR_Pos = 0x17 + // Bit mask of APB_MEM_WR_ERR field. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR_Msk = 0x800000 + // Bit APB_MEM_WR_ERR. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR = 0x800000 + // Position of APB_MEM_RADDR field. + RMT_CH_TX_STATUS_APB_MEM_RADDR_Pos = 0x18 + // Bit mask of APB_MEM_RADDR field. + RMT_CH_TX_STATUS_APB_MEM_RADDR_Msk = 0xff000000 + + // CH2_RX_STATUS: RMT_CH2STATUS_REG. + // Position of MEM_WADDR_EX field. + RMT_CH_RX_STATUS_MEM_WADDR_EX_Pos = 0x0 + // Bit mask of MEM_WADDR_EX field. + RMT_CH_RX_STATUS_MEM_WADDR_EX_Msk = 0x1ff + // Position of APB_MEM_RADDR field. + RMT_CH_RX_STATUS_APB_MEM_RADDR_Pos = 0xc + // Bit mask of APB_MEM_RADDR field. + RMT_CH_RX_STATUS_APB_MEM_RADDR_Msk = 0x1ff000 + // Position of STATE field. + RMT_CH_RX_STATUS_STATE_Pos = 0x16 + // Bit mask of STATE field. + RMT_CH_RX_STATUS_STATE_Msk = 0x1c00000 + // Position of MEM_OWNER_ERR field. + RMT_CH_RX_STATUS_MEM_OWNER_ERR_Pos = 0x19 + // Bit mask of MEM_OWNER_ERR field. + RMT_CH_RX_STATUS_MEM_OWNER_ERR_Msk = 0x2000000 + // Bit MEM_OWNER_ERR. + RMT_CH_RX_STATUS_MEM_OWNER_ERR = 0x2000000 + // Position of MEM_FULL field. + RMT_CH_RX_STATUS_MEM_FULL_Pos = 0x1a + // Bit mask of MEM_FULL field. + RMT_CH_RX_STATUS_MEM_FULL_Msk = 0x4000000 + // Bit MEM_FULL. + RMT_CH_RX_STATUS_MEM_FULL = 0x4000000 + // Position of APB_MEM_RD_ERR field. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR_Pos = 0x1b + // Bit mask of APB_MEM_RD_ERR field. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR_Msk = 0x8000000 + // Bit APB_MEM_RD_ERR. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR = 0x8000000 + + // INT_RAW: RMT_INT_RAW_REG. + // Position of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_RAW_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_RAW_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_RAW_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_RAW_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_RAW_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_RAW_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_RAW_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_RAW_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_RAW_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_RAW_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_RAW_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_RAW_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_RAW_CH_s_TX_LOOP = 0x1000 + + // INT_ST: RMT_INT_ST_REG. + // Position of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ST_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_ST_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_ST_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_ST_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_ST_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_ST_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_ST_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_ST_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ST_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_ST_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_ST_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_ST_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_TX_LOOP field. + RMT_INT_ST_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_ST_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_ST_CH_s_TX_LOOP = 0x1000 + + // INT_ENA: RMT_INT_ENA_REG. + // Position of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ENA_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_ENA_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_ENA_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_ENA_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_ENA_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_ENA_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_ENA_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_ENA_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ENA_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_ENA_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_ENA_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_ENA_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_TX_LOOP field. + RMT_INT_ENA_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_ENA_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_ENA_CH_s_TX_LOOP = 0x1000 + + // INT_CLR: RMT_INT_CLR_REG. + // Position of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_CLR_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_CLR_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_CLR_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_CLR_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_CLR_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_CLR_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_CLR_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_CLR_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_CLR_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_CLR_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_CLR_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_CLR_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_CLR_CH_s_TX_LOOP = 0x1000 + + // CH0CARRIER_DUTY: RMT_CH%sCARRIER_DUTY_REG. + // Position of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Pos = 0x0 + // Bit mask of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Msk = 0xffff + // Position of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Pos = 0x10 + // Bit mask of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Msk = 0xffff0000 + + // CH2_RX_CARRIER_RM: RMT_CH2_RX_CARRIER_RM_REG. + // Position of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Pos = 0x0 + // Bit mask of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Msk = 0xffff + // Position of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Pos = 0x10 + // Bit mask of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Msk = 0xffff0000 + + // CH0_TX_LIM: RMT_CH%s_TX_LIM_REG. + // Position of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Pos = 0x0 + // Bit mask of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Msk = 0x1ff + // Position of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Pos = 0x9 + // Bit mask of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Msk = 0x7fe00 + // Position of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Pos = 0x13 + // Bit mask of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Msk = 0x80000 + // Bit TX_LOOP_CNT_EN. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN = 0x80000 + // Position of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Pos = 0x14 + // Bit mask of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Msk = 0x100000 + // Bit LOOP_COUNT_RESET. + RMT_CH_TX_LIM_LOOP_COUNT_RESET = 0x100000 + + // CH2_RX_LIM: RMT_CH2_RX_LIM_REG. + // Position of RX_LIM field. + RMT_CH_RX_LIM_RX_LIM_Pos = 0x0 + // Bit mask of RX_LIM field. + RMT_CH_RX_LIM_RX_LIM_Msk = 0x1ff + + // SYS_CONF: RMT_SYS_CONF_REG. + // Position of APB_FIFO_MASK field. + RMT_SYS_CONF_APB_FIFO_MASK_Pos = 0x0 + // Bit mask of APB_FIFO_MASK field. + RMT_SYS_CONF_APB_FIFO_MASK_Msk = 0x1 + // Bit APB_FIFO_MASK. + RMT_SYS_CONF_APB_FIFO_MASK = 0x1 + // Position of MEM_CLK_FORCE_ON field. + RMT_SYS_CONF_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + RMT_SYS_CONF_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + RMT_SYS_CONF_MEM_CLK_FORCE_ON = 0x2 + // Position of MEM_FORCE_PD field. + RMT_SYS_CONF_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of MEM_FORCE_PD field. + RMT_SYS_CONF_MEM_FORCE_PD_Msk = 0x4 + // Bit MEM_FORCE_PD. + RMT_SYS_CONF_MEM_FORCE_PD = 0x4 + // Position of MEM_FORCE_PU field. + RMT_SYS_CONF_MEM_FORCE_PU_Pos = 0x3 + // Bit mask of MEM_FORCE_PU field. + RMT_SYS_CONF_MEM_FORCE_PU_Msk = 0x8 + // Bit MEM_FORCE_PU. + RMT_SYS_CONF_MEM_FORCE_PU = 0x8 + // Position of SCLK_DIV_NUM field. + RMT_SYS_CONF_SCLK_DIV_NUM_Pos = 0x4 + // Bit mask of SCLK_DIV_NUM field. + RMT_SYS_CONF_SCLK_DIV_NUM_Msk = 0xff0 + // Position of SCLK_DIV_A field. + RMT_SYS_CONF_SCLK_DIV_A_Pos = 0xc + // Bit mask of SCLK_DIV_A field. + RMT_SYS_CONF_SCLK_DIV_A_Msk = 0x3f000 + // Position of SCLK_DIV_B field. + RMT_SYS_CONF_SCLK_DIV_B_Pos = 0x12 + // Bit mask of SCLK_DIV_B field. + RMT_SYS_CONF_SCLK_DIV_B_Msk = 0xfc0000 + // Position of SCLK_SEL field. + RMT_SYS_CONF_SCLK_SEL_Pos = 0x18 + // Bit mask of SCLK_SEL field. + RMT_SYS_CONF_SCLK_SEL_Msk = 0x3000000 + // Position of SCLK_ACTIVE field. + RMT_SYS_CONF_SCLK_ACTIVE_Pos = 0x1a + // Bit mask of SCLK_ACTIVE field. + RMT_SYS_CONF_SCLK_ACTIVE_Msk = 0x4000000 + // Bit SCLK_ACTIVE. + RMT_SYS_CONF_SCLK_ACTIVE = 0x4000000 + // Position of CLK_EN field. + RMT_SYS_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + RMT_SYS_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + RMT_SYS_CONF_CLK_EN = 0x80000000 + + // TX_SIM: RMT_TX_SIM_REG. + // Position of TX_SIM_CH0 field. + RMT_TX_SIM_TX_SIM_CH0_Pos = 0x0 + // Bit mask of TX_SIM_CH0 field. + RMT_TX_SIM_TX_SIM_CH0_Msk = 0x1 + // Bit TX_SIM_CH0. + RMT_TX_SIM_TX_SIM_CH0 = 0x1 + // Position of TX_SIM_CH1 field. + RMT_TX_SIM_TX_SIM_CH1_Pos = 0x1 + // Bit mask of TX_SIM_CH1 field. + RMT_TX_SIM_TX_SIM_CH1_Msk = 0x2 + // Bit TX_SIM_CH1. + RMT_TX_SIM_TX_SIM_CH1 = 0x2 + // Position of TX_SIM_EN field. + RMT_TX_SIM_TX_SIM_EN_Pos = 0x2 + // Bit mask of TX_SIM_EN field. + RMT_TX_SIM_TX_SIM_EN_Msk = 0x4 + // Bit TX_SIM_EN. + RMT_TX_SIM_TX_SIM_EN = 0x4 + + // REF_CNT_RST: RMT_REF_CNT_RST_REG. + // Position of CH0 field. + RMT_REF_CNT_RST_CH0_Pos = 0x0 + // Bit mask of CH0 field. + RMT_REF_CNT_RST_CH0_Msk = 0x1 + // Bit CH0. + RMT_REF_CNT_RST_CH0 = 0x1 + // Position of CH1 field. + RMT_REF_CNT_RST_CH1_Pos = 0x1 + // Bit mask of CH1 field. + RMT_REF_CNT_RST_CH1_Msk = 0x2 + // Bit CH1. + RMT_REF_CNT_RST_CH1 = 0x2 + // Position of CH2 field. + RMT_REF_CNT_RST_CH2_Pos = 0x2 + // Bit mask of CH2 field. + RMT_REF_CNT_RST_CH2_Msk = 0x4 + // Bit CH2. + RMT_REF_CNT_RST_CH2 = 0x4 + // Position of CH3 field. + RMT_REF_CNT_RST_CH3_Pos = 0x3 + // Bit mask of CH3 field. + RMT_REF_CNT_RST_CH3_Msk = 0x8 + // Bit CH3. + RMT_REF_CNT_RST_CH3 = 0x8 + + // DATE: RMT_DATE_REG. + // Position of DATE field. + RMT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RMT_DATE_DATE_Msk = 0xfffffff +) + +// Constants for RNG: Hardware Random Number Generator +const () + +// Constants for RSA: RSA (Rivest Shamir Adleman) Accelerator +const ( + // M_PRIME: RSA M_prime register + // Position of M_PRIME field. + RSA_M_PRIME_M_PRIME_Pos = 0x0 + // Bit mask of M_PRIME field. + RSA_M_PRIME_M_PRIME_Msk = 0xffffffff + + // MODE: RSA mode register + // Position of MODE field. + RSA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + RSA_MODE_MODE_Msk = 0x7f + + // QUERY_CLEAN: RSA query clean register + // Position of QUERY_CLEAN field. + RSA_QUERY_CLEAN_QUERY_CLEAN_Pos = 0x0 + // Bit mask of QUERY_CLEAN field. + RSA_QUERY_CLEAN_QUERY_CLEAN_Msk = 0x1 + // Bit QUERY_CLEAN. + RSA_QUERY_CLEAN_QUERY_CLEAN = 0x1 + + // SET_START_MODEXP: RSA modular exponentiation trigger register. + // Position of SET_START_MODEXP field. + RSA_SET_START_MODEXP_SET_START_MODEXP_Pos = 0x0 + // Bit mask of SET_START_MODEXP field. + RSA_SET_START_MODEXP_SET_START_MODEXP_Msk = 0x1 + // Bit SET_START_MODEXP. + RSA_SET_START_MODEXP_SET_START_MODEXP = 0x1 + + // SET_START_MODMULT: RSA modular multiplication trigger register. + // Position of SET_START_MODMULT field. + RSA_SET_START_MODMULT_SET_START_MODMULT_Pos = 0x0 + // Bit mask of SET_START_MODMULT field. + RSA_SET_START_MODMULT_SET_START_MODMULT_Msk = 0x1 + // Bit SET_START_MODMULT. + RSA_SET_START_MODMULT_SET_START_MODMULT = 0x1 + + // SET_START_MULT: RSA normal multiplication trigger register. + // Position of SET_START_MULT field. + RSA_SET_START_MULT_SET_START_MULT_Pos = 0x0 + // Bit mask of SET_START_MULT field. + RSA_SET_START_MULT_SET_START_MULT_Msk = 0x1 + // Bit SET_START_MULT. + RSA_SET_START_MULT_SET_START_MULT = 0x1 + + // QUERY_IDLE: RSA query idle register + // Position of QUERY_IDLE field. + RSA_QUERY_IDLE_QUERY_IDLE_Pos = 0x0 + // Bit mask of QUERY_IDLE field. + RSA_QUERY_IDLE_QUERY_IDLE_Msk = 0x1 + // Bit QUERY_IDLE. + RSA_QUERY_IDLE_QUERY_IDLE = 0x1 + + // INT_CLR: RSA interrupt clear register + // Position of CLEAR_INTERRUPT field. + RSA_INT_CLR_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + RSA_INT_CLR_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + RSA_INT_CLR_CLEAR_INTERRUPT = 0x1 + + // CONSTANT_TIME: RSA constant time option register + // Position of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Pos = 0x0 + // Bit mask of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Msk = 0x1 + // Bit CONSTANT_TIME. + RSA_CONSTANT_TIME_CONSTANT_TIME = 0x1 + + // SEARCH_ENABLE: RSA search option + // Position of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Pos = 0x0 + // Bit mask of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Msk = 0x1 + // Bit SEARCH_ENABLE. + RSA_SEARCH_ENABLE_SEARCH_ENABLE = 0x1 + + // SEARCH_POS: RSA search position configure register + // Position of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Pos = 0x0 + // Bit mask of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Msk = 0xfff + + // INT_ENA: RSA interrupt enable register + // Position of INT_ENA field. + RSA_INT_ENA_INT_ENA_Pos = 0x0 + // Bit mask of INT_ENA field. + RSA_INT_ENA_INT_ENA_Msk = 0x1 + // Bit INT_ENA. + RSA_INT_ENA_INT_ENA = 0x1 + + // DATE: RSA version control register + // Position of DATE field. + RSA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RSA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for RTC_CNTL: Real-Time Clock Control +const ( + // OPTIONS0: rtc configure register + // Position of SW_STALL_APPCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_APPCPU_C0_Pos = 0x0 + // Bit mask of SW_STALL_APPCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_APPCPU_C0_Msk = 0x3 + // Position of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Pos = 0x2 + // Bit mask of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Msk = 0xc + // Position of SW_APPCPU_RST field. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST_Pos = 0x4 + // Bit mask of SW_APPCPU_RST field. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST_Msk = 0x10 + // Bit SW_APPCPU_RST. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST = 0x10 + // Position of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Pos = 0x5 + // Bit mask of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Msk = 0x20 + // Bit SW_PROCPU_RST. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST = 0x20 + // Position of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Pos = 0x6 + // Bit mask of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Msk = 0x40 + // Bit BB_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD = 0x40 + // Position of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Pos = 0x7 + // Bit mask of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Msk = 0x80 + // Bit BB_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU = 0x80 + // Position of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Pos = 0x8 + // Bit mask of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Msk = 0x100 + // Bit BBPLL_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD = 0x100 + // Position of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Pos = 0x9 + // Bit mask of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Msk = 0x200 + // Bit BBPLL_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU = 0x200 + // Position of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Pos = 0xa + // Bit mask of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Msk = 0x400 + // Bit BBPLL_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD = 0x400 + // Position of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Pos = 0xb + // Bit mask of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Msk = 0x800 + // Bit BBPLL_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU = 0x800 + // Position of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Pos = 0xc + // Bit mask of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Msk = 0x1000 + // Bit XTL_FORCE_PD. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD = 0x1000 + // Position of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Pos = 0xd + // Bit mask of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Msk = 0x2000 + // Bit XTL_FORCE_PU. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU = 0x2000 + // Position of XTL_EN_WAIT field. + RTC_CNTL_OPTIONS0_XTL_EN_WAIT_Pos = 0xe + // Bit mask of XTL_EN_WAIT field. + RTC_CNTL_OPTIONS0_XTL_EN_WAIT_Msk = 0x3c000 + // Position of XTL_EXT_CTR_SEL field. + RTC_CNTL_OPTIONS0_XTL_EXT_CTR_SEL_Pos = 0x14 + // Bit mask of XTL_EXT_CTR_SEL field. + RTC_CNTL_OPTIONS0_XTL_EXT_CTR_SEL_Msk = 0x700000 + // Position of XTL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO_Pos = 0x17 + // Bit mask of XTL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO_Msk = 0x800000 + // Bit XTL_FORCE_ISO. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO = 0x800000 + // Position of PLL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO_Pos = 0x18 + // Bit mask of PLL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO_Msk = 0x1000000 + // Bit PLL_FORCE_ISO. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO = 0x1000000 + // Position of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Pos = 0x19 + // Bit mask of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Msk = 0x2000000 + // Bit ANALOG_FORCE_ISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO = 0x2000000 + // Position of XTL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO_Pos = 0x1a + // Bit mask of XTL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO_Msk = 0x4000000 + // Bit XTL_FORCE_NOISO. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO = 0x4000000 + // Position of PLL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO_Pos = 0x1b + // Bit mask of PLL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO_Msk = 0x8000000 + // Bit PLL_FORCE_NOISO. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO = 0x8000000 + // Position of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Pos = 0x1c + // Bit mask of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Msk = 0x10000000 + // Bit ANALOG_FORCE_NOISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO = 0x10000000 + // Position of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Pos = 0x1d + // Bit mask of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Msk = 0x20000000 + // Bit DG_WRAP_FORCE_RST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST = 0x20000000 + // Position of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_NORST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST = 0x40000000 + // Position of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Pos = 0x1f + // Bit mask of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Msk = 0x80000000 + // Bit SW_SYS_RST. + RTC_CNTL_OPTIONS0_SW_SYS_RST = 0x80000000 + + // SLP_TIMER0: rtc configure register + // Position of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Pos = 0x0 + // Bit mask of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Msk = 0xffffffff + + // SLP_TIMER1: rtc configure register + // Position of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Pos = 0x0 + // Bit mask of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Msk = 0xffff + // Position of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Pos = 0x10 + // Bit mask of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Msk = 0x10000 + // Bit MAIN_TIMER_ALARM_EN. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN = 0x10000 + + // TIME_UPDATE: rtc configure register + // Position of TIMER_SYS_STALL field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL_Pos = 0x1b + // Bit mask of TIMER_SYS_STALL field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL_Msk = 0x8000000 + // Bit TIMER_SYS_STALL. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL = 0x8000000 + // Position of TIMER_XTL_OFF field. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF_Pos = 0x1c + // Bit mask of TIMER_XTL_OFF field. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF_Msk = 0x10000000 + // Bit TIMER_XTL_OFF. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF = 0x10000000 + // Position of TIMER_SYS_RST field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST_Pos = 0x1d + // Bit mask of TIMER_SYS_RST field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST_Msk = 0x20000000 + // Bit TIMER_SYS_RST. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST = 0x20000000 + // Position of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Pos = 0x1f + // Bit mask of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Msk = 0x80000000 + // Bit TIME_UPDATE. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE = 0x80000000 + + // TIME_LOW0: rtc configure register + // Position of TIMER_VALUE0_LOW field. + RTC_CNTL_TIME_LOW0_TIMER_VALUE0_LOW_Pos = 0x0 + // Bit mask of TIMER_VALUE0_LOW field. + RTC_CNTL_TIME_LOW0_TIMER_VALUE0_LOW_Msk = 0xffffffff + + // TIME_HIGH0: rtc configure register + // Position of TIMER_VALUE0_HIGH field. + RTC_CNTL_TIME_HIGH0_TIMER_VALUE0_HIGH_Pos = 0x0 + // Bit mask of TIMER_VALUE0_HIGH field. + RTC_CNTL_TIME_HIGH0_TIMER_VALUE0_HIGH_Msk = 0xffff + + // STATE0: rtc configure register + // Position of SW_CPU_INT field. + RTC_CNTL_STATE0_SW_CPU_INT_Pos = 0x0 + // Bit mask of SW_CPU_INT field. + RTC_CNTL_STATE0_SW_CPU_INT_Msk = 0x1 + // Bit SW_CPU_INT. + RTC_CNTL_STATE0_SW_CPU_INT = 0x1 + // Position of SLP_REJECT_CAUSE_CLR field. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR_Pos = 0x1 + // Bit mask of SLP_REJECT_CAUSE_CLR field. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR_Msk = 0x2 + // Bit SLP_REJECT_CAUSE_CLR. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR = 0x2 + // Position of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Pos = 0x16 + // Bit mask of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Msk = 0x400000 + // Bit APB2RTC_BRIDGE_SEL. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL = 0x400000 + // Position of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Pos = 0x1c + // Bit mask of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Msk = 0x10000000 + // Bit SDIO_ACTIVE_IND. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND = 0x10000000 + // Position of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Pos = 0x1d + // Bit mask of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Msk = 0x20000000 + // Bit SLP_WAKEUP. + RTC_CNTL_STATE0_SLP_WAKEUP = 0x20000000 + // Position of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Pos = 0x1e + // Bit mask of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Msk = 0x40000000 + // Bit SLP_REJECT. + RTC_CNTL_STATE0_SLP_REJECT = 0x40000000 + // Position of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Pos = 0x1f + // Bit mask of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Msk = 0x80000000 + // Bit SLEEP_EN. + RTC_CNTL_STATE0_SLEEP_EN = 0x80000000 + + // TIMER1: rtc configure register + // Position of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Pos = 0x0 + // Bit mask of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Msk = 0x1 + // Bit CPU_STALL_EN. + RTC_CNTL_TIMER1_CPU_STALL_EN = 0x1 + // Position of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Pos = 0x1 + // Bit mask of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Msk = 0x3e + // Position of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Pos = 0x6 + // Bit mask of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Msk = 0x3fc0 + // Position of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Pos = 0xe + // Bit mask of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Msk = 0xffc000 + // Position of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Pos = 0x18 + // Bit mask of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Msk = 0xff000000 + + // TIMER2: rtc configure register + // Position of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Pos = 0x18 + // Bit mask of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Msk = 0xff000000 + + // TIMER3: rtc configure register + // Position of WIFI_WAIT_TIMER field. + RTC_CNTL_TIMER3_WIFI_WAIT_TIMER_Pos = 0x0 + // Bit mask of WIFI_WAIT_TIMER field. + RTC_CNTL_TIMER3_WIFI_WAIT_TIMER_Msk = 0x1ff + // Position of WIFI_POWERUP_TIMER field. + RTC_CNTL_TIMER3_WIFI_POWERUP_TIMER_Pos = 0x9 + // Bit mask of WIFI_POWERUP_TIMER field. + RTC_CNTL_TIMER3_WIFI_POWERUP_TIMER_Msk = 0xfe00 + // Position of BT_WAIT_TIMER field. + RTC_CNTL_TIMER3_BT_WAIT_TIMER_Pos = 0x10 + // Bit mask of BT_WAIT_TIMER field. + RTC_CNTL_TIMER3_BT_WAIT_TIMER_Msk = 0x1ff0000 + // Position of BT_POWERUP_TIMER field. + RTC_CNTL_TIMER3_BT_POWERUP_TIMER_Pos = 0x19 + // Bit mask of BT_POWERUP_TIMER field. + RTC_CNTL_TIMER3_BT_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER4: rtc configure register + // Position of CPU_TOP_WAIT_TIMER field. + RTC_CNTL_TIMER4_CPU_TOP_WAIT_TIMER_Pos = 0x0 + // Bit mask of CPU_TOP_WAIT_TIMER field. + RTC_CNTL_TIMER4_CPU_TOP_WAIT_TIMER_Msk = 0x1ff + // Position of CPU_TOP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_CPU_TOP_POWERUP_TIMER_Pos = 0x9 + // Bit mask of CPU_TOP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_CPU_TOP_POWERUP_TIMER_Msk = 0xfe00 + // Position of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Pos = 0x10 + // Bit mask of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Msk = 0x1ff0000 + // Position of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Pos = 0x19 + // Bit mask of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER5: rtc configure register + // Position of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Pos = 0x8 + // Bit mask of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Msk = 0xff00 + + // TIMER6: rtc configure register + // Position of DG_PERI_WAIT_TIMER field. + RTC_CNTL_TIMER6_DG_PERI_WAIT_TIMER_Pos = 0x10 + // Bit mask of DG_PERI_WAIT_TIMER field. + RTC_CNTL_TIMER6_DG_PERI_WAIT_TIMER_Msk = 0x1ff0000 + // Position of DG_PERI_POWERUP_TIMER field. + RTC_CNTL_TIMER6_DG_PERI_POWERUP_TIMER_Pos = 0x19 + // Bit mask of DG_PERI_POWERUP_TIMER field. + RTC_CNTL_TIMER6_DG_PERI_POWERUP_TIMER_Msk = 0xfe000000 + + // ANA_CONF: rtc configure register + // Position of RESET_POR_FORCE_PD field. + RTC_CNTL_ANA_CONF_RESET_POR_FORCE_PD_Pos = 0x12 + // Bit mask of RESET_POR_FORCE_PD field. + RTC_CNTL_ANA_CONF_RESET_POR_FORCE_PD_Msk = 0x40000 + // Bit RESET_POR_FORCE_PD. + RTC_CNTL_ANA_CONF_RESET_POR_FORCE_PD = 0x40000 + // Position of RESET_POR_FORCE_PU field. + RTC_CNTL_ANA_CONF_RESET_POR_FORCE_PU_Pos = 0x13 + // Bit mask of RESET_POR_FORCE_PU field. + RTC_CNTL_ANA_CONF_RESET_POR_FORCE_PU_Msk = 0x80000 + // Bit RESET_POR_FORCE_PU. + RTC_CNTL_ANA_CONF_RESET_POR_FORCE_PU = 0x80000 + // Position of GLITCH_RST_EN field. + RTC_CNTL_ANA_CONF_GLITCH_RST_EN_Pos = 0x14 + // Bit mask of GLITCH_RST_EN field. + RTC_CNTL_ANA_CONF_GLITCH_RST_EN_Msk = 0x100000 + // Bit GLITCH_RST_EN. + RTC_CNTL_ANA_CONF_GLITCH_RST_EN = 0x100000 + // Position of SAR_I2C_PU field. + RTC_CNTL_ANA_CONF_SAR_I2C_PU_Pos = 0x16 + // Bit mask of SAR_I2C_PU field. + RTC_CNTL_ANA_CONF_SAR_I2C_PU_Msk = 0x400000 + // Bit SAR_I2C_PU. + RTC_CNTL_ANA_CONF_SAR_I2C_PU = 0x400000 + // Position of PLLA_FORCE_PD field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD_Pos = 0x17 + // Bit mask of PLLA_FORCE_PD field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD_Msk = 0x800000 + // Bit PLLA_FORCE_PD. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD = 0x800000 + // Position of PLLA_FORCE_PU field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU_Pos = 0x18 + // Bit mask of PLLA_FORCE_PU field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU_Msk = 0x1000000 + // Bit PLLA_FORCE_PU. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU = 0x1000000 + // Position of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Pos = 0x19 + // Bit mask of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Msk = 0x2000000 + // Bit BBPLL_CAL_SLP_START. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START = 0x2000000 + // Position of PVTMON_PU field. + RTC_CNTL_ANA_CONF_PVTMON_PU_Pos = 0x1a + // Bit mask of PVTMON_PU field. + RTC_CNTL_ANA_CONF_PVTMON_PU_Msk = 0x4000000 + // Bit PVTMON_PU. + RTC_CNTL_ANA_CONF_PVTMON_PU = 0x4000000 + // Position of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Pos = 0x1b + // Bit mask of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Msk = 0x8000000 + // Bit TXRF_I2C_PU. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU = 0x8000000 + // Position of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Pos = 0x1c + // Bit mask of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Msk = 0x10000000 + // Bit RFRX_PBUS_PU. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU = 0x10000000 + // Position of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Pos = 0x1e + // Bit mask of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Msk = 0x40000000 + // Bit CKGEN_I2C_PU. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU = 0x40000000 + // Position of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Pos = 0x1f + // Bit mask of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Msk = 0x80000000 + // Bit PLL_I2C_PU. + RTC_CNTL_ANA_CONF_PLL_I2C_PU = 0x80000000 + + // RESET_STATE: rtc configure register + // Position of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Pos = 0x0 + // Bit mask of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Msk = 0x3f + // Position of RESET_CAUSE_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_APPCPU_Pos = 0x6 + // Bit mask of RESET_CAUSE_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_APPCPU_Msk = 0xfc0 + // Position of STAT_VECTOR_SEL_APPCPU field. + RTC_CNTL_RESET_STATE_STAT_VECTOR_SEL_APPCPU_Pos = 0xc + // Bit mask of STAT_VECTOR_SEL_APPCPU field. + RTC_CNTL_RESET_STATE_STAT_VECTOR_SEL_APPCPU_Msk = 0x1000 + // Bit STAT_VECTOR_SEL_APPCPU. + RTC_CNTL_RESET_STATE_STAT_VECTOR_SEL_APPCPU = 0x1000 + // Position of STAT_VECTOR_SEL_PROCPU field. + RTC_CNTL_RESET_STATE_STAT_VECTOR_SEL_PROCPU_Pos = 0xd + // Bit mask of STAT_VECTOR_SEL_PROCPU field. + RTC_CNTL_RESET_STATE_STAT_VECTOR_SEL_PROCPU_Msk = 0x2000 + // Bit STAT_VECTOR_SEL_PROCPU. + RTC_CNTL_RESET_STATE_STAT_VECTOR_SEL_PROCPU = 0x2000 + // Position of ALL_RESET_FLAG_PROCPU field. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_PROCPU_Pos = 0xe + // Bit mask of ALL_RESET_FLAG_PROCPU field. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_PROCPU_Msk = 0x4000 + // Bit ALL_RESET_FLAG_PROCPU. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_PROCPU = 0x4000 + // Position of ALL_RESET_FLAG_APPCPU field. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_APPCPU_Pos = 0xf + // Bit mask of ALL_RESET_FLAG_APPCPU field. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_APPCPU_Msk = 0x8000 + // Bit ALL_RESET_FLAG_APPCPU. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_APPCPU = 0x8000 + // Position of ALL_RESET_FLAG_CLR_PROCPU field. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_CLR_PROCPU_Pos = 0x10 + // Bit mask of ALL_RESET_FLAG_CLR_PROCPU field. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_CLR_PROCPU_Msk = 0x10000 + // Bit ALL_RESET_FLAG_CLR_PROCPU. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_CLR_PROCPU = 0x10000 + // Position of ALL_RESET_FLAG_CLR_APPCPU field. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_CLR_APPCPU_Pos = 0x11 + // Bit mask of ALL_RESET_FLAG_CLR_APPCPU field. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_CLR_APPCPU_Msk = 0x20000 + // Bit ALL_RESET_FLAG_CLR_APPCPU. + RTC_CNTL_RESET_STATE_ALL_RESET_FLAG_CLR_APPCPU = 0x20000 + // Position of OCD_HALT_ON_RESET_APPCPU field. + RTC_CNTL_RESET_STATE_OCD_HALT_ON_RESET_APPCPU_Pos = 0x12 + // Bit mask of OCD_HALT_ON_RESET_APPCPU field. + RTC_CNTL_RESET_STATE_OCD_HALT_ON_RESET_APPCPU_Msk = 0x40000 + // Bit OCD_HALT_ON_RESET_APPCPU. + RTC_CNTL_RESET_STATE_OCD_HALT_ON_RESET_APPCPU = 0x40000 + // Position of OCD_HALT_ON_RESET_PROCPU field. + RTC_CNTL_RESET_STATE_OCD_HALT_ON_RESET_PROCPU_Pos = 0x13 + // Bit mask of OCD_HALT_ON_RESET_PROCPU field. + RTC_CNTL_RESET_STATE_OCD_HALT_ON_RESET_PROCPU_Msk = 0x80000 + // Bit OCD_HALT_ON_RESET_PROCPU. + RTC_CNTL_RESET_STATE_OCD_HALT_ON_RESET_PROCPU = 0x80000 + // Position of JTAG_RESET_FLAG_PROCPU field. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_PROCPU_Pos = 0x14 + // Bit mask of JTAG_RESET_FLAG_PROCPU field. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_PROCPU_Msk = 0x100000 + // Bit JTAG_RESET_FLAG_PROCPU. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_PROCPU = 0x100000 + // Position of JTAG_RESET_FLAG_APPCPU field. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_APPCPU_Pos = 0x15 + // Bit mask of JTAG_RESET_FLAG_APPCPU field. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_APPCPU_Msk = 0x200000 + // Bit JTAG_RESET_FLAG_APPCPU. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_APPCPU = 0x200000 + // Position of JTAG_RESET_FLAG_CLR_PROCPU field. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_CLR_PROCPU_Pos = 0x16 + // Bit mask of JTAG_RESET_FLAG_CLR_PROCPU field. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_CLR_PROCPU_Msk = 0x400000 + // Bit JTAG_RESET_FLAG_CLR_PROCPU. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_CLR_PROCPU = 0x400000 + // Position of JTAG_RESET_FLAG_CLR_APPCPU field. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_CLR_APPCPU_Pos = 0x17 + // Bit mask of JTAG_RESET_FLAG_CLR_APPCPU field. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_CLR_APPCPU_Msk = 0x800000 + // Bit JTAG_RESET_FLAG_CLR_APPCPU. + RTC_CNTL_RESET_STATE_JTAG_RESET_FLAG_CLR_APPCPU = 0x800000 + // Position of DRESET_MASK_APPCPU field. + RTC_CNTL_RESET_STATE_DRESET_MASK_APPCPU_Pos = 0x18 + // Bit mask of DRESET_MASK_APPCPU field. + RTC_CNTL_RESET_STATE_DRESET_MASK_APPCPU_Msk = 0x1000000 + // Bit DRESET_MASK_APPCPU. + RTC_CNTL_RESET_STATE_DRESET_MASK_APPCPU = 0x1000000 + // Position of DRESET_MASK_PROCPU field. + RTC_CNTL_RESET_STATE_DRESET_MASK_PROCPU_Pos = 0x19 + // Bit mask of DRESET_MASK_PROCPU field. + RTC_CNTL_RESET_STATE_DRESET_MASK_PROCPU_Msk = 0x2000000 + // Bit DRESET_MASK_PROCPU. + RTC_CNTL_RESET_STATE_DRESET_MASK_PROCPU = 0x2000000 + + // WAKEUP_STATE: rtc configure register + // Position of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Pos = 0xf + // Bit mask of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Msk = 0xffff8000 + + // INT_ENA_RTC: rtc configure register + // Position of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA = 0x1 + // Position of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA = 0x2 + // Position of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA_Pos = 0x3 + // Bit mask of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA_Msk = 0x8 + // Bit WDT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA = 0x8 + // Position of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA = 0x200 + // Position of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA = 0x400 + // Position of SWD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA_Pos = 0xf + // Bit mask of SWD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA_Msk = 0x8000 + // Bit SWD_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA = 0x8000 + // Position of XTAL32K_DEAD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_XTAL32K_DEAD_INT_ENA_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_XTAL32K_DEAD_INT_ENA_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ENA. + RTC_CNTL_INT_ENA_RTC_XTAL32K_DEAD_INT_ENA = 0x10000 + // Position of GLITCH_DET_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_GLITCH_DET_INT_ENA_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_GLITCH_DET_INT_ENA_Msk = 0x80000 + // Bit GLITCH_DET_INT_ENA. + RTC_CNTL_INT_ENA_RTC_GLITCH_DET_INT_ENA = 0x80000 + // Position of BBPLL_CAL_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BBPLL_CAL_INT_ENA_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BBPLL_CAL_INT_ENA_Msk = 0x100000 + // Bit BBPLL_CAL_INT_ENA. + RTC_CNTL_INT_ENA_RTC_BBPLL_CAL_INT_ENA = 0x100000 + + // INT_RAW_RTC: rtc configure register + // Position of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW_Msk = 0x1 + // Bit SLP_WAKEUP_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW = 0x1 + // Position of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW_Msk = 0x2 + // Bit SLP_REJECT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW = 0x2 + // Position of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW_Pos = 0x3 + // Bit mask of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW_Msk = 0x8 + // Bit WDT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW = 0x8 + // Position of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW_Msk = 0x200 + // Bit BROWN_OUT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW = 0x200 + // Position of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW_Msk = 0x400 + // Bit MAIN_TIMER_INT_RAW. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW = 0x400 + // Position of SWD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW_Pos = 0xf + // Bit mask of SWD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW_Msk = 0x8000 + // Bit SWD_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW = 0x8000 + // Position of XTAL32K_DEAD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_XTAL32K_DEAD_INT_RAW_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_XTAL32K_DEAD_INT_RAW_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_RAW. + RTC_CNTL_INT_RAW_RTC_XTAL32K_DEAD_INT_RAW = 0x10000 + // Position of GLITCH_DET_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_GLITCH_DET_INT_RAW_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_GLITCH_DET_INT_RAW_Msk = 0x80000 + // Bit GLITCH_DET_INT_RAW. + RTC_CNTL_INT_RAW_RTC_GLITCH_DET_INT_RAW = 0x80000 + // Position of BBPLL_CAL_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BBPLL_CAL_INT_RAW_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BBPLL_CAL_INT_RAW_Msk = 0x100000 + // Bit BBPLL_CAL_INT_RAW. + RTC_CNTL_INT_RAW_RTC_BBPLL_CAL_INT_RAW = 0x100000 + + // INT_ST_RTC: rtc configure register + // Position of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ST. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST = 0x1 + // Position of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST_Msk = 0x2 + // Bit SLP_REJECT_INT_ST. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST = 0x2 + // Position of WDT_INT_ST field. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST_Pos = 0x3 + // Bit mask of WDT_INT_ST field. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST_Msk = 0x8 + // Bit WDT_INT_ST. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST = 0x8 + // Position of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST_Msk = 0x200 + // Bit BROWN_OUT_INT_ST. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST = 0x200 + // Position of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST_Msk = 0x400 + // Bit MAIN_TIMER_INT_ST. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST = 0x400 + // Position of SWD_INT_ST field. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST_Pos = 0xf + // Bit mask of SWD_INT_ST field. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST_Msk = 0x8000 + // Bit SWD_INT_ST. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST = 0x8000 + // Position of XTAL32K_DEAD_INT_ST field. + RTC_CNTL_INT_ST_RTC_XTAL32K_DEAD_INT_ST_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ST field. + RTC_CNTL_INT_ST_RTC_XTAL32K_DEAD_INT_ST_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ST. + RTC_CNTL_INT_ST_RTC_XTAL32K_DEAD_INT_ST = 0x10000 + // Position of GLITCH_DET_INT_ST field. + RTC_CNTL_INT_ST_RTC_GLITCH_DET_INT_ST_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ST field. + RTC_CNTL_INT_ST_RTC_GLITCH_DET_INT_ST_Msk = 0x80000 + // Bit GLITCH_DET_INT_ST. + RTC_CNTL_INT_ST_RTC_GLITCH_DET_INT_ST = 0x80000 + // Position of BBPLL_CAL_INT_ST field. + RTC_CNTL_INT_ST_RTC_BBPLL_CAL_INT_ST_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_ST field. + RTC_CNTL_INT_ST_RTC_BBPLL_CAL_INT_ST_Msk = 0x100000 + // Bit BBPLL_CAL_INT_ST. + RTC_CNTL_INT_ST_RTC_BBPLL_CAL_INT_ST = 0x100000 + + // INT_CLR_RTC: rtc configure register + // Position of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR_Msk = 0x1 + // Bit SLP_WAKEUP_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR = 0x1 + // Position of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR_Msk = 0x2 + // Bit SLP_REJECT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR = 0x2 + // Position of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR_Pos = 0x3 + // Bit mask of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR_Msk = 0x8 + // Bit WDT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR = 0x8 + // Position of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR_Msk = 0x200 + // Bit BROWN_OUT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR = 0x200 + // Position of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR_Msk = 0x400 + // Bit MAIN_TIMER_INT_CLR. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR = 0x400 + // Position of SWD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR_Pos = 0xf + // Bit mask of SWD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR_Msk = 0x8000 + // Bit SWD_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR = 0x8000 + // Position of XTAL32K_DEAD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_XTAL32K_DEAD_INT_CLR_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_XTAL32K_DEAD_INT_CLR_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_CLR. + RTC_CNTL_INT_CLR_RTC_XTAL32K_DEAD_INT_CLR = 0x10000 + // Position of GLITCH_DET_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_GLITCH_DET_INT_CLR_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_GLITCH_DET_INT_CLR_Msk = 0x80000 + // Bit GLITCH_DET_INT_CLR. + RTC_CNTL_INT_CLR_RTC_GLITCH_DET_INT_CLR = 0x80000 + // Position of BBPLL_CAL_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BBPLL_CAL_INT_CLR_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BBPLL_CAL_INT_CLR_Msk = 0x100000 + // Bit BBPLL_CAL_INT_CLR. + RTC_CNTL_INT_CLR_RTC_BBPLL_CAL_INT_CLR = 0x100000 + + // STORE0: rtc configure register + // Position of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Pos = 0x0 + // Bit mask of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Msk = 0xffffffff + + // STORE1: rtc configure register + // Position of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Pos = 0x0 + // Bit mask of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Msk = 0xffffffff + + // STORE2: rtc configure register + // Position of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Pos = 0x0 + // Bit mask of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Msk = 0xffffffff + + // STORE3: rtc configure register + // Position of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Pos = 0x0 + // Bit mask of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Msk = 0xffffffff + + // EXT_XTL_CONF: rtc configure register + // Position of XTAL32K_WDT_EN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_EN_Pos = 0x0 + // Bit mask of XTAL32K_WDT_EN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_EN_Msk = 0x1 + // Bit XTAL32K_WDT_EN. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_EN = 0x1 + // Position of XTAL32K_WDT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_CLK_FO_Pos = 0x1 + // Bit mask of XTAL32K_WDT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_CLK_FO_Msk = 0x2 + // Bit XTAL32K_WDT_CLK_FO. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_CLK_FO = 0x2 + // Position of XTAL32K_WDT_RESET field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_RESET_Pos = 0x2 + // Bit mask of XTAL32K_WDT_RESET field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_RESET_Msk = 0x4 + // Bit XTAL32K_WDT_RESET. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_RESET = 0x4 + // Position of XTAL32K_EXT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_EXT_CLK_FO_Pos = 0x3 + // Bit mask of XTAL32K_EXT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_EXT_CLK_FO_Msk = 0x8 + // Bit XTAL32K_EXT_CLK_FO. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_EXT_CLK_FO = 0x8 + // Position of XTAL32K_AUTO_BACKUP field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_BACKUP_Pos = 0x4 + // Bit mask of XTAL32K_AUTO_BACKUP field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_BACKUP_Msk = 0x10 + // Bit XTAL32K_AUTO_BACKUP. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_BACKUP = 0x10 + // Position of XTAL32K_AUTO_RESTART field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RESTART_Pos = 0x5 + // Bit mask of XTAL32K_AUTO_RESTART field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RESTART_Msk = 0x20 + // Bit XTAL32K_AUTO_RESTART. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RESTART = 0x20 + // Position of XTAL32K_AUTO_RETURN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RETURN_Pos = 0x6 + // Bit mask of XTAL32K_AUTO_RETURN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RETURN_Msk = 0x40 + // Bit XTAL32K_AUTO_RETURN. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RETURN = 0x40 + // Position of XTAL32K_XPD_FORCE field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_XPD_FORCE_Pos = 0x7 + // Bit mask of XTAL32K_XPD_FORCE field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_XPD_FORCE_Msk = 0x80 + // Bit XTAL32K_XPD_FORCE. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_XPD_FORCE = 0x80 + // Position of ENCKINIT_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_ENCKINIT_XTAL_32K_Pos = 0x8 + // Bit mask of ENCKINIT_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_ENCKINIT_XTAL_32K_Msk = 0x100 + // Bit ENCKINIT_XTAL_32K. + RTC_CNTL_EXT_XTL_CONF_ENCKINIT_XTAL_32K = 0x100 + // Position of DBUF_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DBUF_XTAL_32K_Pos = 0x9 + // Bit mask of DBUF_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DBUF_XTAL_32K_Msk = 0x200 + // Bit DBUF_XTAL_32K. + RTC_CNTL_EXT_XTL_CONF_DBUF_XTAL_32K = 0x200 + // Position of DGM_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DGM_XTAL_32K_Pos = 0xa + // Bit mask of DGM_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DGM_XTAL_32K_Msk = 0x1c00 + // Position of DRES_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DRES_XTAL_32K_Pos = 0xd + // Bit mask of DRES_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DRES_XTAL_32K_Msk = 0xe000 + // Position of XPD_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_XPD_XTAL_32K_Pos = 0x10 + // Bit mask of XPD_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_XPD_XTAL_32K_Msk = 0x10000 + // Bit XPD_XTAL_32K. + RTC_CNTL_EXT_XTL_CONF_XPD_XTAL_32K = 0x10000 + // Position of DAC_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DAC_XTAL_32K_Pos = 0x11 + // Bit mask of DAC_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DAC_XTAL_32K_Msk = 0xe0000 + // Position of WDT_STATE field. + RTC_CNTL_EXT_XTL_CONF_WDT_STATE_Pos = 0x14 + // Bit mask of WDT_STATE field. + RTC_CNTL_EXT_XTL_CONF_WDT_STATE_Msk = 0x700000 + // Position of XTAL32K_GPIO_SEL field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_GPIO_SEL_Pos = 0x17 + // Bit mask of XTAL32K_GPIO_SEL field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_GPIO_SEL_Msk = 0x800000 + // Bit XTAL32K_GPIO_SEL. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_GPIO_SEL = 0x800000 + // Position of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Pos = 0x1e + // Bit mask of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Msk = 0x40000000 + // Bit XTL_EXT_CTR_LV. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV = 0x40000000 + // Position of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Pos = 0x1f + // Bit mask of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Msk = 0x80000000 + // Bit XTL_EXT_CTR_EN. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN = 0x80000000 + + // EXT_WAKEUP_CONF: rtc configure register + // Position of GPIO_WAKEUP_FILTER field. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER_Pos = 0x1f + // Bit mask of GPIO_WAKEUP_FILTER field. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER_Msk = 0x80000000 + // Bit GPIO_WAKEUP_FILTER. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER = 0x80000000 + + // SLP_REJECT_CONF: rtc configure register + // Position of SLEEP_REJECT_ENA field. + RTC_CNTL_SLP_REJECT_CONF_SLEEP_REJECT_ENA_Pos = 0xc + // Bit mask of SLEEP_REJECT_ENA field. + RTC_CNTL_SLP_REJECT_CONF_SLEEP_REJECT_ENA_Msk = 0x3ffff000 + // Position of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Pos = 0x1e + // Bit mask of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Msk = 0x40000000 + // Bit LIGHT_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN = 0x40000000 + // Position of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Pos = 0x1f + // Bit mask of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Msk = 0x80000000 + // Bit DEEP_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN = 0x80000000 + + // CPU_PERIOD_CONF: rtc configure register + // Position of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Pos = 0x1d + // Bit mask of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Msk = 0x20000000 + // Bit CPUSEL_CONF. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF = 0x20000000 + // Position of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Pos = 0x1e + // Bit mask of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Msk = 0xc0000000 + + // CLK_CONF: rtc configure register + // Position of EFUSE_CLK_FORCE_GATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_GATING_Pos = 0x1 + // Bit mask of EFUSE_CLK_FORCE_GATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_GATING_Msk = 0x2 + // Bit EFUSE_CLK_FORCE_GATING. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_GATING = 0x2 + // Position of EFUSE_CLK_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_NOGATING_Pos = 0x2 + // Bit mask of EFUSE_CLK_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_NOGATING_Msk = 0x4 + // Bit EFUSE_CLK_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_NOGATING = 0x4 + // Position of CK8M_DIV_SEL_VLD field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD_Pos = 0x3 + // Bit mask of CK8M_DIV_SEL_VLD field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD_Msk = 0x8 + // Bit CK8M_DIV_SEL_VLD. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD = 0x8 + // Position of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Pos = 0x4 + // Bit mask of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Msk = 0x30 + // Position of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Pos = 0x6 + // Bit mask of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Msk = 0x40 + // Bit ENB_CK8M. + RTC_CNTL_CLK_CONF_ENB_CK8M = 0x40 + // Position of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Pos = 0x7 + // Bit mask of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Msk = 0x80 + // Bit ENB_CK8M_DIV. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV = 0x80 + // Position of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Pos = 0x8 + // Bit mask of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Msk = 0x100 + // Bit DIG_XTAL32K_EN. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN = 0x100 + // Position of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Pos = 0x9 + // Bit mask of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Msk = 0x200 + // Bit DIG_CLK8M_D256_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN = 0x200 + // Position of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Pos = 0xa + // Bit mask of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Msk = 0x400 + // Bit DIG_CLK8M_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN = 0x400 + // Position of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Pos = 0xc + // Bit mask of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Msk = 0x7000 + // Position of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Pos = 0xf + // Bit mask of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Msk = 0x8000 + // Bit XTAL_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING = 0x8000 + // Position of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Pos = 0x10 + // Bit mask of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Msk = 0x10000 + // Bit CK8M_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING = 0x10000 + // Position of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Pos = 0x11 + // Bit mask of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Msk = 0x1fe0000 + // Position of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Pos = 0x19 + // Bit mask of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Msk = 0x2000000 + // Bit CK8M_FORCE_PD. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD = 0x2000000 + // Position of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Pos = 0x1a + // Bit mask of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Msk = 0x4000000 + // Bit CK8M_FORCE_PU. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU = 0x4000000 + // Position of XTAL_GLOBAL_FORCE_GATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_GATING_Pos = 0x1b + // Bit mask of XTAL_GLOBAL_FORCE_GATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_GATING_Msk = 0x8000000 + // Bit XTAL_GLOBAL_FORCE_GATING. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_GATING = 0x8000000 + // Position of XTAL_GLOBAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_NOGATING_Pos = 0x1c + // Bit mask of XTAL_GLOBAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_NOGATING_Msk = 0x10000000 + // Bit XTAL_GLOBAL_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_NOGATING = 0x10000000 + // Position of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Pos = 0x1d + // Bit mask of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Msk = 0x20000000 + // Bit FAST_CLK_RTC_SEL. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL = 0x20000000 + // Position of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Pos = 0x1e + // Bit mask of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Msk = 0xc0000000 + + // SLOW_CLK_CONF: rtc configure register + // Position of ANA_CLK_DIV_VLD field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD_Pos = 0x16 + // Bit mask of ANA_CLK_DIV_VLD field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD_Msk = 0x400000 + // Bit ANA_CLK_DIV_VLD. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD = 0x400000 + // Position of ANA_CLK_DIV field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_Pos = 0x17 + // Bit mask of ANA_CLK_DIV field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_Msk = 0x7f800000 + // Position of SLOW_CLK_NEXT_EDGE field. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE_Pos = 0x1f + // Bit mask of SLOW_CLK_NEXT_EDGE field. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE_Msk = 0x80000000 + // Bit SLOW_CLK_NEXT_EDGE. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE = 0x80000000 + + // SDIO_CONF: rtc configure register + // Position of SDIO_TIMER_TARGET field. + RTC_CNTL_SDIO_CONF_SDIO_TIMER_TARGET_Pos = 0x0 + // Bit mask of SDIO_TIMER_TARGET field. + RTC_CNTL_SDIO_CONF_SDIO_TIMER_TARGET_Msk = 0xff + // Position of SDIO_DTHDRV field. + RTC_CNTL_SDIO_CONF_SDIO_DTHDRV_Pos = 0x9 + // Bit mask of SDIO_DTHDRV field. + RTC_CNTL_SDIO_CONF_SDIO_DTHDRV_Msk = 0x600 + // Position of SDIO_DCAP field. + RTC_CNTL_SDIO_CONF_SDIO_DCAP_Pos = 0xb + // Bit mask of SDIO_DCAP field. + RTC_CNTL_SDIO_CONF_SDIO_DCAP_Msk = 0x1800 + // Position of SDIO_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_INITI_Pos = 0xd + // Bit mask of SDIO_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_INITI_Msk = 0x6000 + // Position of SDIO_EN_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_EN_INITI_Pos = 0xf + // Bit mask of SDIO_EN_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_EN_INITI_Msk = 0x8000 + // Bit SDIO_EN_INITI. + RTC_CNTL_SDIO_CONF_SDIO_EN_INITI = 0x8000 + // Position of SDIO_DCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_DCURLIM_Pos = 0x10 + // Bit mask of SDIO_DCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_DCURLIM_Msk = 0x70000 + // Position of SDIO_MODECURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_MODECURLIM_Pos = 0x13 + // Bit mask of SDIO_MODECURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_MODECURLIM_Msk = 0x80000 + // Bit SDIO_MODECURLIM. + RTC_CNTL_SDIO_CONF_SDIO_MODECURLIM = 0x80000 + // Position of SDIO_ENCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_ENCURLIM_Pos = 0x14 + // Bit mask of SDIO_ENCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_ENCURLIM_Msk = 0x100000 + // Bit SDIO_ENCURLIM. + RTC_CNTL_SDIO_CONF_SDIO_ENCURLIM = 0x100000 + // Position of SDIO_REG_PD_EN field. + RTC_CNTL_SDIO_CONF_SDIO_REG_PD_EN_Pos = 0x15 + // Bit mask of SDIO_REG_PD_EN field. + RTC_CNTL_SDIO_CONF_SDIO_REG_PD_EN_Msk = 0x200000 + // Bit SDIO_REG_PD_EN. + RTC_CNTL_SDIO_CONF_SDIO_REG_PD_EN = 0x200000 + // Position of SDIO_FORCE field. + RTC_CNTL_SDIO_CONF_SDIO_FORCE_Pos = 0x16 + // Bit mask of SDIO_FORCE field. + RTC_CNTL_SDIO_CONF_SDIO_FORCE_Msk = 0x400000 + // Bit SDIO_FORCE. + RTC_CNTL_SDIO_CONF_SDIO_FORCE = 0x400000 + // Position of SDIO_TIEH field. + RTC_CNTL_SDIO_CONF_SDIO_TIEH_Pos = 0x17 + // Bit mask of SDIO_TIEH field. + RTC_CNTL_SDIO_CONF_SDIO_TIEH_Msk = 0x800000 + // Bit SDIO_TIEH. + RTC_CNTL_SDIO_CONF_SDIO_TIEH = 0x800000 + // Position of _1P8_READY field. + RTC_CNTL_SDIO_CONF__1P8_READY_Pos = 0x18 + // Bit mask of _1P8_READY field. + RTC_CNTL_SDIO_CONF__1P8_READY_Msk = 0x1000000 + // Bit _1P8_READY. + RTC_CNTL_SDIO_CONF__1P8_READY = 0x1000000 + // Position of DREFL_SDIO field. + RTC_CNTL_SDIO_CONF_DREFL_SDIO_Pos = 0x19 + // Bit mask of DREFL_SDIO field. + RTC_CNTL_SDIO_CONF_DREFL_SDIO_Msk = 0x6000000 + // Position of DREFM_SDIO field. + RTC_CNTL_SDIO_CONF_DREFM_SDIO_Pos = 0x1b + // Bit mask of DREFM_SDIO field. + RTC_CNTL_SDIO_CONF_DREFM_SDIO_Msk = 0x18000000 + // Position of DREFH_SDIO field. + RTC_CNTL_SDIO_CONF_DREFH_SDIO_Pos = 0x1d + // Bit mask of DREFH_SDIO field. + RTC_CNTL_SDIO_CONF_DREFH_SDIO_Msk = 0x60000000 + // Position of XPD_SDIO field. + RTC_CNTL_SDIO_CONF_XPD_SDIO_Pos = 0x1f + // Bit mask of XPD_SDIO field. + RTC_CNTL_SDIO_CONF_XPD_SDIO_Msk = 0x80000000 + // Bit XPD_SDIO. + RTC_CNTL_SDIO_CONF_XPD_SDIO = 0x80000000 + + // BIAS_CONF: rtc configure register + // Position of DG_VDD_DRV_B_SLP field. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_Pos = 0x0 + // Bit mask of DG_VDD_DRV_B_SLP field. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_Msk = 0xff + // Position of DG_VDD_DRV_B_SLP_EN field. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_EN_Pos = 0x8 + // Bit mask of DG_VDD_DRV_B_SLP_EN field. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_EN_Msk = 0x100 + // Bit DG_VDD_DRV_B_SLP_EN. + RTC_CNTL_BIAS_CONF_DG_VDD_DRV_B_SLP_EN = 0x100 + // Position of BIAS_BUF_IDLE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE_Pos = 0xa + // Bit mask of BIAS_BUF_IDLE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE_Msk = 0x400 + // Bit BIAS_BUF_IDLE. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE = 0x400 + // Position of BIAS_BUF_WAKE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE_Pos = 0xb + // Bit mask of BIAS_BUF_WAKE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE_Msk = 0x800 + // Bit BIAS_BUF_WAKE. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE = 0x800 + // Position of BIAS_BUF_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP_Pos = 0xc + // Bit mask of BIAS_BUF_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP_Msk = 0x1000 + // Bit BIAS_BUF_DEEP_SLP. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP = 0x1000 + // Position of BIAS_BUF_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR_Pos = 0xd + // Bit mask of BIAS_BUF_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR_Msk = 0x2000 + // Bit BIAS_BUF_MONITOR. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR = 0x2000 + // Position of PD_CUR_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP_Pos = 0xe + // Bit mask of PD_CUR_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP_Msk = 0x4000 + // Bit PD_CUR_DEEP_SLP. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP = 0x4000 + // Position of PD_CUR_MONITOR field. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR_Pos = 0xf + // Bit mask of PD_CUR_MONITOR field. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR_Msk = 0x8000 + // Bit PD_CUR_MONITOR. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR = 0x8000 + // Position of BIAS_SLEEP_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP_Pos = 0x10 + // Bit mask of BIAS_SLEEP_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP_Msk = 0x10000 + // Bit BIAS_SLEEP_DEEP_SLP. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP = 0x10000 + // Position of BIAS_SLEEP_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR_Pos = 0x11 + // Bit mask of BIAS_SLEEP_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR_Msk = 0x20000 + // Bit BIAS_SLEEP_MONITOR. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR = 0x20000 + // Position of DBG_ATTEN_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_DEEP_SLP_Pos = 0x12 + // Bit mask of DBG_ATTEN_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_DEEP_SLP_Msk = 0x3c0000 + // Position of DBG_ATTEN_MONITOR field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_MONITOR_Pos = 0x16 + // Bit mask of DBG_ATTEN_MONITOR field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_MONITOR_Msk = 0x3c00000 + + // RTC_CNTL: rtc configure register + // Position of DIG_REG_CAL_EN field. + RTC_CNTL_RTC_CNTL_DIG_REG_CAL_EN_Pos = 0x7 + // Bit mask of DIG_REG_CAL_EN field. + RTC_CNTL_RTC_CNTL_DIG_REG_CAL_EN_Msk = 0x80 + // Bit DIG_REG_CAL_EN. + RTC_CNTL_RTC_CNTL_DIG_REG_CAL_EN = 0x80 + // Position of SCK_DCAP field. + RTC_CNTL_RTC_CNTL_SCK_DCAP_Pos = 0xe + // Bit mask of SCK_DCAP field. + RTC_CNTL_RTC_CNTL_SCK_DCAP_Msk = 0x3fc000 + // Position of DBOOST_FORCE_PD field. + RTC_CNTL_RTC_CNTL_DBOOST_FORCE_PD_Pos = 0x1c + // Bit mask of DBOOST_FORCE_PD field. + RTC_CNTL_RTC_CNTL_DBOOST_FORCE_PD_Msk = 0x10000000 + // Bit DBOOST_FORCE_PD. + RTC_CNTL_RTC_CNTL_DBOOST_FORCE_PD = 0x10000000 + // Position of DBOOST_FORCE_PU field. + RTC_CNTL_RTC_CNTL_DBOOST_FORCE_PU_Pos = 0x1d + // Bit mask of DBOOST_FORCE_PU field. + RTC_CNTL_RTC_CNTL_DBOOST_FORCE_PU_Msk = 0x20000000 + // Bit DBOOST_FORCE_PU. + RTC_CNTL_RTC_CNTL_DBOOST_FORCE_PU = 0x20000000 + // Position of REGULATOR_FORCE_PD field. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PD_Pos = 0x1e + // Bit mask of REGULATOR_FORCE_PD field. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PD_Msk = 0x40000000 + // Bit REGULATOR_FORCE_PD. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PD = 0x40000000 + // Position of REGULATOR_FORCE_PU field. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PU_Pos = 0x1f + // Bit mask of REGULATOR_FORCE_PU field. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PU_Msk = 0x80000000 + // Bit REGULATOR_FORCE_PU. + RTC_CNTL_RTC_CNTL_REGULATOR_FORCE_PU = 0x80000000 + + // PWC: rtc configure register + // Position of PAD_FORCE_HOLD field. + RTC_CNTL_PWC_PAD_FORCE_HOLD_Pos = 0x15 + // Bit mask of PAD_FORCE_HOLD field. + RTC_CNTL_PWC_PAD_FORCE_HOLD_Msk = 0x200000 + // Bit PAD_FORCE_HOLD. + RTC_CNTL_PWC_PAD_FORCE_HOLD = 0x200000 + + // DIG_PWC: rtc configure register + // Position of VDD_SPI_PWR_DRV field. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_DRV_Pos = 0x0 + // Bit mask of VDD_SPI_PWR_DRV field. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_DRV_Msk = 0x3 + // Position of VDD_SPI_PWR_FORCE field. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_FORCE_Pos = 0x2 + // Bit mask of VDD_SPI_PWR_FORCE field. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_FORCE_Msk = 0x4 + // Bit VDD_SPI_PWR_FORCE. + RTC_CNTL_DIG_PWC_VDD_SPI_PWR_FORCE = 0x4 + // Position of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Msk = 0x8 + // Bit LSLP_MEM_FORCE_PD. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD = 0x8 + // Position of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Msk = 0x10 + // Bit LSLP_MEM_FORCE_PU. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU = 0x10 + // Position of BT_FORCE_PD field. + RTC_CNTL_DIG_PWC_BT_FORCE_PD_Pos = 0xb + // Bit mask of BT_FORCE_PD field. + RTC_CNTL_DIG_PWC_BT_FORCE_PD_Msk = 0x800 + // Bit BT_FORCE_PD. + RTC_CNTL_DIG_PWC_BT_FORCE_PD = 0x800 + // Position of BT_FORCE_PU field. + RTC_CNTL_DIG_PWC_BT_FORCE_PU_Pos = 0xc + // Bit mask of BT_FORCE_PU field. + RTC_CNTL_DIG_PWC_BT_FORCE_PU_Msk = 0x1000 + // Bit BT_FORCE_PU. + RTC_CNTL_DIG_PWC_BT_FORCE_PU = 0x1000 + // Position of DG_PERI_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PD_Pos = 0xd + // Bit mask of DG_PERI_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PD_Msk = 0x2000 + // Bit DG_PERI_FORCE_PD. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PD = 0x2000 + // Position of DG_PERI_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PU_Pos = 0xe + // Bit mask of DG_PERI_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PU_Msk = 0x4000 + // Bit DG_PERI_FORCE_PU. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PU = 0x4000 + // Position of FASTMEM_FORCE_LPD field. + RTC_CNTL_DIG_PWC_FASTMEM_FORCE_LPD_Pos = 0xf + // Bit mask of FASTMEM_FORCE_LPD field. + RTC_CNTL_DIG_PWC_FASTMEM_FORCE_LPD_Msk = 0x8000 + // Bit FASTMEM_FORCE_LPD. + RTC_CNTL_DIG_PWC_FASTMEM_FORCE_LPD = 0x8000 + // Position of FASTMEM_FORCE_LPU field. + RTC_CNTL_DIG_PWC_FASTMEM_FORCE_LPU_Pos = 0x10 + // Bit mask of FASTMEM_FORCE_LPU field. + RTC_CNTL_DIG_PWC_FASTMEM_FORCE_LPU_Msk = 0x10000 + // Bit FASTMEM_FORCE_LPU. + RTC_CNTL_DIG_PWC_FASTMEM_FORCE_LPU = 0x10000 + // Position of WIFI_FORCE_PD field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD_Pos = 0x11 + // Bit mask of WIFI_FORCE_PD field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD_Msk = 0x20000 + // Bit WIFI_FORCE_PD. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD = 0x20000 + // Position of WIFI_FORCE_PU field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU_Pos = 0x12 + // Bit mask of WIFI_FORCE_PU field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU_Msk = 0x40000 + // Bit WIFI_FORCE_PU. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU = 0x40000 + // Position of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Pos = 0x13 + // Bit mask of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Msk = 0x80000 + // Bit DG_WRAP_FORCE_PD. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD = 0x80000 + // Position of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Pos = 0x14 + // Bit mask of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Msk = 0x100000 + // Bit DG_WRAP_FORCE_PU. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU = 0x100000 + // Position of CPU_TOP_FORCE_PD field. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PD_Pos = 0x15 + // Bit mask of CPU_TOP_FORCE_PD field. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PD_Msk = 0x200000 + // Bit CPU_TOP_FORCE_PD. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PD = 0x200000 + // Position of CPU_TOP_FORCE_PU field. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PU_Pos = 0x16 + // Bit mask of CPU_TOP_FORCE_PU field. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PU_Msk = 0x400000 + // Bit CPU_TOP_FORCE_PU. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PU = 0x400000 + // Position of BT_PD_EN field. + RTC_CNTL_DIG_PWC_BT_PD_EN_Pos = 0x1b + // Bit mask of BT_PD_EN field. + RTC_CNTL_DIG_PWC_BT_PD_EN_Msk = 0x8000000 + // Bit BT_PD_EN. + RTC_CNTL_DIG_PWC_BT_PD_EN = 0x8000000 + // Position of DG_PERI_PD_EN field. + RTC_CNTL_DIG_PWC_DG_PERI_PD_EN_Pos = 0x1c + // Bit mask of DG_PERI_PD_EN field. + RTC_CNTL_DIG_PWC_DG_PERI_PD_EN_Msk = 0x10000000 + // Bit DG_PERI_PD_EN. + RTC_CNTL_DIG_PWC_DG_PERI_PD_EN = 0x10000000 + // Position of CPU_TOP_PD_EN field. + RTC_CNTL_DIG_PWC_CPU_TOP_PD_EN_Pos = 0x1d + // Bit mask of CPU_TOP_PD_EN field. + RTC_CNTL_DIG_PWC_CPU_TOP_PD_EN_Msk = 0x20000000 + // Bit CPU_TOP_PD_EN. + RTC_CNTL_DIG_PWC_CPU_TOP_PD_EN = 0x20000000 + // Position of WIFI_PD_EN field. + RTC_CNTL_DIG_PWC_WIFI_PD_EN_Pos = 0x1e + // Bit mask of WIFI_PD_EN field. + RTC_CNTL_DIG_PWC_WIFI_PD_EN_Msk = 0x40000000 + // Bit WIFI_PD_EN. + RTC_CNTL_DIG_PWC_WIFI_PD_EN = 0x40000000 + // Position of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Pos = 0x1f + // Bit mask of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Msk = 0x80000000 + // Bit DG_WRAP_PD_EN. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN = 0x80000000 + + // DIG_ISO: rtc configure register + // Position of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Pos = 0x7 + // Bit mask of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Msk = 0x80 + // Bit FORCE_OFF. + RTC_CNTL_DIG_ISO_FORCE_OFF = 0x80 + // Position of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Pos = 0x8 + // Bit mask of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Msk = 0x100 + // Bit FORCE_ON. + RTC_CNTL_DIG_ISO_FORCE_ON = 0x100 + // Position of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Pos = 0x9 + // Bit mask of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Msk = 0x200 + // Bit DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD = 0x200 + // Position of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Pos = 0xa + // Bit mask of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Msk = 0x400 + // Bit CLR_DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD = 0x400 + // Position of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Pos = 0xb + // Bit mask of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Msk = 0x800 + // Bit DG_PAD_AUTOHOLD_EN. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN = 0x800 + // Position of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Pos = 0xc + // Bit mask of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Msk = 0x1000 + // Bit DG_PAD_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO = 0x1000 + // Position of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Pos = 0xd + // Bit mask of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Msk = 0x2000 + // Bit DG_PAD_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO = 0x2000 + // Position of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Pos = 0xe + // Bit mask of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Msk = 0x4000 + // Bit DG_PAD_FORCE_UNHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD = 0x4000 + // Position of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Pos = 0xf + // Bit mask of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Msk = 0x8000 + // Bit DG_PAD_FORCE_HOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD = 0x8000 + // Position of BT_FORCE_ISO field. + RTC_CNTL_DIG_ISO_BT_FORCE_ISO_Pos = 0x16 + // Bit mask of BT_FORCE_ISO field. + RTC_CNTL_DIG_ISO_BT_FORCE_ISO_Msk = 0x400000 + // Bit BT_FORCE_ISO. + RTC_CNTL_DIG_ISO_BT_FORCE_ISO = 0x400000 + // Position of BT_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_BT_FORCE_NOISO_Pos = 0x17 + // Bit mask of BT_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_BT_FORCE_NOISO_Msk = 0x800000 + // Bit BT_FORCE_NOISO. + RTC_CNTL_DIG_ISO_BT_FORCE_NOISO = 0x800000 + // Position of DG_PERI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_ISO_Pos = 0x18 + // Bit mask of DG_PERI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_ISO_Msk = 0x1000000 + // Bit DG_PERI_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_ISO = 0x1000000 + // Position of DG_PERI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_NOISO_Pos = 0x19 + // Bit mask of DG_PERI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_NOISO_Msk = 0x2000000 + // Bit DG_PERI_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_NOISO = 0x2000000 + // Position of CPU_TOP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_ISO_Pos = 0x1a + // Bit mask of CPU_TOP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_ISO_Msk = 0x4000000 + // Bit CPU_TOP_FORCE_ISO. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_ISO = 0x4000000 + // Position of CPU_TOP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_NOISO_Pos = 0x1b + // Bit mask of CPU_TOP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_NOISO_Msk = 0x8000000 + // Bit CPU_TOP_FORCE_NOISO. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_NOISO = 0x8000000 + // Position of WIFI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO_Pos = 0x1c + // Bit mask of WIFI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO_Msk = 0x10000000 + // Bit WIFI_FORCE_ISO. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO = 0x10000000 + // Position of WIFI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO_Pos = 0x1d + // Bit mask of WIFI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO_Msk = 0x20000000 + // Bit WIFI_FORCE_NOISO. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO = 0x20000000 + // Position of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO = 0x40000000 + // Position of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Pos = 0x1f + // Bit mask of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Msk = 0x80000000 + // Bit DG_WRAP_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO = 0x80000000 + + // WDTCONFIG0: rtc configure register + // Position of WDT_CHIP_RESET_WIDTH field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Pos = 0x0 + // Bit mask of WDT_CHIP_RESET_WIDTH field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Msk = 0xff + // Position of WDT_CHIP_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN_Pos = 0x8 + // Bit mask of WDT_CHIP_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN_Msk = 0x100 + // Bit WDT_CHIP_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN = 0x100 + // Position of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Pos = 0x9 + // Bit mask of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Msk = 0x200 + // Bit WDT_PAUSE_IN_SLP. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP = 0x200 + // Position of WDT_APPCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xa + // Bit mask of WDT_APPCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x400 + // Bit WDT_APPCPU_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x400 + // Position of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xb + // Bit mask of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x800 + // Bit WDT_PROCPU_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x800 + // Position of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xc + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x1000 + // Bit WDT_FLASHBOOT_MOD_EN. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x1000 + // Position of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xd + // Bit mask of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0xe000 + // Position of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x10 + // Bit mask of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x70000 + // Position of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Pos = 0x13 + // Bit mask of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Msk = 0x380000 + // Position of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Pos = 0x16 + // Bit mask of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Msk = 0x1c00000 + // Position of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Pos = 0x19 + // Bit mask of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Msk = 0xe000000 + // Position of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Pos = 0x1c + // Bit mask of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Msk = 0x70000000 + // Position of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + RTC_CNTL_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: rtc configure register + // Position of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG2: rtc configure register + // Position of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: rtc configure register + // Position of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: rtc configure register + // Position of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: rtc configure register + // Position of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Pos = 0x1f + // Bit mask of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Msk = 0x80000000 + // Bit WDT_FEED. + RTC_CNTL_WDTFEED_WDT_FEED = 0x80000000 + + // WDTWPROTECT: rtc configure register + // Position of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // SWD_CONF: rtc configure register + // Position of SWD_RESET_FLAG field. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG_Pos = 0x0 + // Bit mask of SWD_RESET_FLAG field. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG_Msk = 0x1 + // Bit SWD_RESET_FLAG. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG = 0x1 + // Position of SWD_FEED_INT field. + RTC_CNTL_SWD_CONF_SWD_FEED_INT_Pos = 0x1 + // Bit mask of SWD_FEED_INT field. + RTC_CNTL_SWD_CONF_SWD_FEED_INT_Msk = 0x2 + // Bit SWD_FEED_INT. + RTC_CNTL_SWD_CONF_SWD_FEED_INT = 0x2 + // Position of SWD_BYPASS_RST field. + RTC_CNTL_SWD_CONF_SWD_BYPASS_RST_Pos = 0x11 + // Bit mask of SWD_BYPASS_RST field. + RTC_CNTL_SWD_CONF_SWD_BYPASS_RST_Msk = 0x20000 + // Bit SWD_BYPASS_RST. + RTC_CNTL_SWD_CONF_SWD_BYPASS_RST = 0x20000 + // Position of SWD_SIGNAL_WIDTH field. + RTC_CNTL_SWD_CONF_SWD_SIGNAL_WIDTH_Pos = 0x12 + // Bit mask of SWD_SIGNAL_WIDTH field. + RTC_CNTL_SWD_CONF_SWD_SIGNAL_WIDTH_Msk = 0xffc0000 + // Position of SWD_RST_FLAG_CLR field. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR_Pos = 0x1c + // Bit mask of SWD_RST_FLAG_CLR field. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR_Msk = 0x10000000 + // Bit SWD_RST_FLAG_CLR. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR = 0x10000000 + // Position of SWD_FEED field. + RTC_CNTL_SWD_CONF_SWD_FEED_Pos = 0x1d + // Bit mask of SWD_FEED field. + RTC_CNTL_SWD_CONF_SWD_FEED_Msk = 0x20000000 + // Bit SWD_FEED. + RTC_CNTL_SWD_CONF_SWD_FEED = 0x20000000 + // Position of SWD_DISABLE field. + RTC_CNTL_SWD_CONF_SWD_DISABLE_Pos = 0x1e + // Bit mask of SWD_DISABLE field. + RTC_CNTL_SWD_CONF_SWD_DISABLE_Msk = 0x40000000 + // Bit SWD_DISABLE. + RTC_CNTL_SWD_CONF_SWD_DISABLE = 0x40000000 + // Position of SWD_AUTO_FEED_EN field. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN_Pos = 0x1f + // Bit mask of SWD_AUTO_FEED_EN field. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN_Msk = 0x80000000 + // Bit SWD_AUTO_FEED_EN. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN = 0x80000000 + + // SWD_WPROTECT: rtc configure register + // Position of SWD_WKEY field. + RTC_CNTL_SWD_WPROTECT_SWD_WKEY_Pos = 0x0 + // Bit mask of SWD_WKEY field. + RTC_CNTL_SWD_WPROTECT_SWD_WKEY_Msk = 0xffffffff + + // SW_CPU_STALL: rtc configure register + // Position of SW_STALL_APPCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_APPCPU_C1_Pos = 0x14 + // Bit mask of SW_STALL_APPCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_APPCPU_C1_Msk = 0x3f00000 + // Position of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Pos = 0x1a + // Bit mask of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Msk = 0xfc000000 + + // STORE4: rtc configure register + // Position of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Pos = 0x0 + // Bit mask of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Msk = 0xffffffff + + // STORE5: rtc configure register + // Position of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Pos = 0x0 + // Bit mask of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Msk = 0xffffffff + + // STORE6: rtc configure register + // Position of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Pos = 0x0 + // Bit mask of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Msk = 0xffffffff + + // STORE7: rtc configure register + // Position of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Pos = 0x0 + // Bit mask of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Msk = 0xffffffff + + // LOW_POWER_ST: rtc configure register + // Position of XPD_ROM0 field. + RTC_CNTL_LOW_POWER_ST_XPD_ROM0_Pos = 0x0 + // Bit mask of XPD_ROM0 field. + RTC_CNTL_LOW_POWER_ST_XPD_ROM0_Msk = 0x1 + // Bit XPD_ROM0. + RTC_CNTL_LOW_POWER_ST_XPD_ROM0 = 0x1 + // Position of XPD_DIG_DCDC field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_DCDC_Pos = 0x2 + // Bit mask of XPD_DIG_DCDC field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_DCDC_Msk = 0x4 + // Bit XPD_DIG_DCDC. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_DCDC = 0x4 + // Position of PERI_ISO field. + RTC_CNTL_LOW_POWER_ST_PERI_ISO_Pos = 0x3 + // Bit mask of PERI_ISO field. + RTC_CNTL_LOW_POWER_ST_PERI_ISO_Msk = 0x8 + // Bit PERI_ISO. + RTC_CNTL_LOW_POWER_ST_PERI_ISO = 0x8 + // Position of XPD_RTC_PERI field. + RTC_CNTL_LOW_POWER_ST_XPD_RTC_PERI_Pos = 0x4 + // Bit mask of XPD_RTC_PERI field. + RTC_CNTL_LOW_POWER_ST_XPD_RTC_PERI_Msk = 0x10 + // Bit XPD_RTC_PERI. + RTC_CNTL_LOW_POWER_ST_XPD_RTC_PERI = 0x10 + // Position of WIFI_ISO field. + RTC_CNTL_LOW_POWER_ST_WIFI_ISO_Pos = 0x5 + // Bit mask of WIFI_ISO field. + RTC_CNTL_LOW_POWER_ST_WIFI_ISO_Msk = 0x20 + // Bit WIFI_ISO. + RTC_CNTL_LOW_POWER_ST_WIFI_ISO = 0x20 + // Position of XPD_WIFI field. + RTC_CNTL_LOW_POWER_ST_XPD_WIFI_Pos = 0x6 + // Bit mask of XPD_WIFI field. + RTC_CNTL_LOW_POWER_ST_XPD_WIFI_Msk = 0x40 + // Bit XPD_WIFI. + RTC_CNTL_LOW_POWER_ST_XPD_WIFI = 0x40 + // Position of DIG_ISO field. + RTC_CNTL_LOW_POWER_ST_DIG_ISO_Pos = 0x7 + // Bit mask of DIG_ISO field. + RTC_CNTL_LOW_POWER_ST_DIG_ISO_Msk = 0x80 + // Bit DIG_ISO. + RTC_CNTL_LOW_POWER_ST_DIG_ISO = 0x80 + // Position of XPD_DIG field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_Pos = 0x8 + // Bit mask of XPD_DIG field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_Msk = 0x100 + // Bit XPD_DIG. + RTC_CNTL_LOW_POWER_ST_XPD_DIG = 0x100 + // Position of TOUCH_STATE_START field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START_Pos = 0x9 + // Bit mask of TOUCH_STATE_START field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START_Msk = 0x200 + // Bit TOUCH_STATE_START. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START = 0x200 + // Position of TOUCH_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH_Pos = 0xa + // Bit mask of TOUCH_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH_Msk = 0x400 + // Bit TOUCH_STATE_SWITCH. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH = 0x400 + // Position of TOUCH_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP_Pos = 0xb + // Bit mask of TOUCH_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP_Msk = 0x800 + // Bit TOUCH_STATE_SLP. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP = 0x800 + // Position of TOUCH_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE_Pos = 0xc + // Bit mask of TOUCH_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE_Msk = 0x1000 + // Bit TOUCH_STATE_DONE. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE = 0x1000 + // Position of COCPU_STATE_START field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START_Pos = 0xd + // Bit mask of COCPU_STATE_START field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START_Msk = 0x2000 + // Bit COCPU_STATE_START. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START = 0x2000 + // Position of COCPU_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH_Pos = 0xe + // Bit mask of COCPU_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH_Msk = 0x4000 + // Bit COCPU_STATE_SWITCH. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH = 0x4000 + // Position of COCPU_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP_Pos = 0xf + // Bit mask of COCPU_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP_Msk = 0x8000 + // Bit COCPU_STATE_SLP. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP = 0x8000 + // Position of COCPU_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE_Pos = 0x10 + // Bit mask of COCPU_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE_Msk = 0x10000 + // Bit COCPU_STATE_DONE. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE = 0x10000 + // Position of MAIN_STATE_XTAL_ISO field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO_Pos = 0x11 + // Bit mask of MAIN_STATE_XTAL_ISO field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO_Msk = 0x20000 + // Bit MAIN_STATE_XTAL_ISO. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO = 0x20000 + // Position of MAIN_STATE_PLL_ON field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON_Pos = 0x12 + // Bit mask of MAIN_STATE_PLL_ON field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON_Msk = 0x40000 + // Bit MAIN_STATE_PLL_ON. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON = 0x40000 + // Position of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Pos = 0x13 + // Bit mask of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Msk = 0x80000 + // Bit RDY_FOR_WAKEUP. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP = 0x80000 + // Position of MAIN_STATE_WAIT_END field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END_Pos = 0x14 + // Bit mask of MAIN_STATE_WAIT_END field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END_Msk = 0x100000 + // Bit MAIN_STATE_WAIT_END. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END = 0x100000 + // Position of IN_WAKEUP_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE_Pos = 0x15 + // Bit mask of IN_WAKEUP_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE_Msk = 0x200000 + // Bit IN_WAKEUP_STATE. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE = 0x200000 + // Position of IN_LOW_POWER_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE_Pos = 0x16 + // Bit mask of IN_LOW_POWER_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE_Msk = 0x400000 + // Bit IN_LOW_POWER_STATE. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE = 0x400000 + // Position of MAIN_STATE_IN_WAIT_8M field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M_Pos = 0x17 + // Bit mask of MAIN_STATE_IN_WAIT_8M field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M_Msk = 0x800000 + // Bit MAIN_STATE_IN_WAIT_8M. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M = 0x800000 + // Position of MAIN_STATE_IN_WAIT_PLL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL_Pos = 0x18 + // Bit mask of MAIN_STATE_IN_WAIT_PLL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL_Msk = 0x1000000 + // Bit MAIN_STATE_IN_WAIT_PLL. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL = 0x1000000 + // Position of MAIN_STATE_IN_WAIT_XTL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL_Pos = 0x19 + // Bit mask of MAIN_STATE_IN_WAIT_XTL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL_Msk = 0x2000000 + // Bit MAIN_STATE_IN_WAIT_XTL. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL = 0x2000000 + // Position of MAIN_STATE_IN_SLP field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP_Pos = 0x1a + // Bit mask of MAIN_STATE_IN_SLP field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP_Msk = 0x4000000 + // Bit MAIN_STATE_IN_SLP. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP = 0x4000000 + // Position of MAIN_STATE_IN_IDLE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE_Pos = 0x1b + // Bit mask of MAIN_STATE_IN_IDLE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE_Msk = 0x8000000 + // Bit MAIN_STATE_IN_IDLE. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE = 0x8000000 + // Position of MAIN_STATE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_Pos = 0x1c + // Bit mask of MAIN_STATE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_Msk = 0xf0000000 + + // DIAG0: rtc configure register + // Position of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG0_LOW_POWER_DIAG1_Pos = 0x0 + // Bit mask of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG0_LOW_POWER_DIAG1_Msk = 0xffffffff + + // PAD_HOLD: rtc configure register + // Position of GPIO_PIN0_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN0_HOLD_Pos = 0x0 + // Bit mask of GPIO_PIN0_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN0_HOLD_Msk = 0x1 + // Bit GPIO_PIN0_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN0_HOLD = 0x1 + // Position of GPIO_PIN1_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN1_HOLD_Pos = 0x1 + // Bit mask of GPIO_PIN1_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN1_HOLD_Msk = 0x2 + // Bit GPIO_PIN1_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN1_HOLD = 0x2 + // Position of GPIO_PIN2_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN2_HOLD_Pos = 0x2 + // Bit mask of GPIO_PIN2_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN2_HOLD_Msk = 0x4 + // Bit GPIO_PIN2_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN2_HOLD = 0x4 + // Position of GPIO_PIN3_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN3_HOLD_Pos = 0x3 + // Bit mask of GPIO_PIN3_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN3_HOLD_Msk = 0x8 + // Bit GPIO_PIN3_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN3_HOLD = 0x8 + // Position of GPIO_PIN4_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN4_HOLD_Pos = 0x4 + // Bit mask of GPIO_PIN4_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN4_HOLD_Msk = 0x10 + // Bit GPIO_PIN4_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN4_HOLD = 0x10 + // Position of GPIO_PIN5_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN5_HOLD_Pos = 0x5 + // Bit mask of GPIO_PIN5_HOLD field. + RTC_CNTL_PAD_HOLD_GPIO_PIN5_HOLD_Msk = 0x20 + // Bit GPIO_PIN5_HOLD. + RTC_CNTL_PAD_HOLD_GPIO_PIN5_HOLD = 0x20 + + // DIG_PAD_HOLD: rtc configure register + // Position of DIG_PAD_HOLD field. + RTC_CNTL_DIG_PAD_HOLD_DIG_PAD_HOLD_Pos = 0x0 + // Bit mask of DIG_PAD_HOLD field. + RTC_CNTL_DIG_PAD_HOLD_DIG_PAD_HOLD_Msk = 0xffffffff + + // BROWN_OUT: rtc configure register + // Position of BROWN_OUT_INT_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_INT_WAIT_Pos = 0x4 + // Bit mask of BROWN_OUT_INT_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_INT_WAIT_Msk = 0x3ff0 + // Position of BROWN_OUT_CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA_Pos = 0xe + // Bit mask of BROWN_OUT_CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA_Msk = 0x4000 + // Bit BROWN_OUT_CLOSE_FLASH_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA = 0x4000 + // Position of BROWN_OUT_PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_PD_RF_ENA_Pos = 0xf + // Bit mask of BROWN_OUT_PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_PD_RF_ENA_Msk = 0x8000 + // Bit BROWN_OUT_PD_RF_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_PD_RF_ENA = 0x8000 + // Position of BROWN_OUT_RST_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_WAIT_Pos = 0x10 + // Bit mask of BROWN_OUT_RST_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_WAIT_Msk = 0x3ff0000 + // Position of BROWN_OUT_RST_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_ENA_Pos = 0x1a + // Bit mask of BROWN_OUT_RST_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_ENA_Msk = 0x4000000 + // Bit BROWN_OUT_RST_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_ENA = 0x4000000 + // Position of BROWN_OUT_RST_SEL field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_SEL_Pos = 0x1b + // Bit mask of BROWN_OUT_RST_SEL field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_SEL_Msk = 0x8000000 + // Bit BROWN_OUT_RST_SEL. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_SEL = 0x8000000 + // Position of BROWN_OUT_ANA_RST_EN field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ANA_RST_EN_Pos = 0x1c + // Bit mask of BROWN_OUT_ANA_RST_EN field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ANA_RST_EN_Msk = 0x10000000 + // Bit BROWN_OUT_ANA_RST_EN. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ANA_RST_EN = 0x10000000 + // Position of BROWN_OUT_CNT_CLR field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CNT_CLR_Pos = 0x1d + // Bit mask of BROWN_OUT_CNT_CLR field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CNT_CLR_Msk = 0x20000000 + // Bit BROWN_OUT_CNT_CLR. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CNT_CLR = 0x20000000 + // Position of BROWN_OUT_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ENA_Pos = 0x1e + // Bit mask of BROWN_OUT_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ENA_Msk = 0x40000000 + // Bit BROWN_OUT_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ENA = 0x40000000 + // Position of DET field. + RTC_CNTL_BROWN_OUT_DET_Pos = 0x1f + // Bit mask of DET field. + RTC_CNTL_BROWN_OUT_DET_Msk = 0x80000000 + // Bit DET. + RTC_CNTL_BROWN_OUT_DET = 0x80000000 + + // TIME_LOW1: rtc configure register + // Position of TIMER_VALUE1_LOW field. + RTC_CNTL_TIME_LOW1_TIMER_VALUE1_LOW_Pos = 0x0 + // Bit mask of TIMER_VALUE1_LOW field. + RTC_CNTL_TIME_LOW1_TIMER_VALUE1_LOW_Msk = 0xffffffff + + // TIME_HIGH1: rtc configure register + // Position of TIMER_VALUE1_HIGH field. + RTC_CNTL_TIME_HIGH1_TIMER_VALUE1_HIGH_Pos = 0x0 + // Bit mask of TIMER_VALUE1_HIGH field. + RTC_CNTL_TIME_HIGH1_TIMER_VALUE1_HIGH_Msk = 0xffff + + // XTAL32K_CLK_FACTOR: rtc configure register + // Position of XTAL32K_CLK_FACTOR field. + RTC_CNTL_XTAL32K_CLK_FACTOR_XTAL32K_CLK_FACTOR_Pos = 0x0 + // Bit mask of XTAL32K_CLK_FACTOR field. + RTC_CNTL_XTAL32K_CLK_FACTOR_XTAL32K_CLK_FACTOR_Msk = 0xffffffff + + // XTAL32K_CONF: rtc configure register + // Position of XTAL32K_RETURN_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RETURN_WAIT_Pos = 0x0 + // Bit mask of XTAL32K_RETURN_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RETURN_WAIT_Msk = 0xf + // Position of XTAL32K_RESTART_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RESTART_WAIT_Pos = 0x4 + // Bit mask of XTAL32K_RESTART_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RESTART_WAIT_Msk = 0xffff0 + // Position of XTAL32K_WDT_TIMEOUT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_WDT_TIMEOUT_Pos = 0x14 + // Bit mask of XTAL32K_WDT_TIMEOUT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_WDT_TIMEOUT_Msk = 0xff00000 + // Position of XTAL32K_STABLE_THRES field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_STABLE_THRES_Pos = 0x1c + // Bit mask of XTAL32K_STABLE_THRES field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_STABLE_THRES_Msk = 0xf0000000 + + // USB_CONF: rtc configure register + // Position of IO_MUX_RESET_DISABLE field. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE_Pos = 0x12 + // Bit mask of IO_MUX_RESET_DISABLE field. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE_Msk = 0x40000 + // Bit IO_MUX_RESET_DISABLE. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE = 0x40000 + + // SLP_REJECT_CAUSE: RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG + // Position of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CAUSE_REJECT_CAUSE_Pos = 0x0 + // Bit mask of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CAUSE_REJECT_CAUSE_Msk = 0x3ffff + + // OPTION1: rtc configure register + // Position of FORCE_DOWNLOAD_BOOT field. + RTC_CNTL_OPTION1_FORCE_DOWNLOAD_BOOT_Pos = 0x0 + // Bit mask of FORCE_DOWNLOAD_BOOT field. + RTC_CNTL_OPTION1_FORCE_DOWNLOAD_BOOT_Msk = 0x1 + // Bit FORCE_DOWNLOAD_BOOT. + RTC_CNTL_OPTION1_FORCE_DOWNLOAD_BOOT = 0x1 + + // SLP_WAKEUP_CAUSE: RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG + // Position of WAKEUP_CAUSE field. + RTC_CNTL_SLP_WAKEUP_CAUSE_WAKEUP_CAUSE_Pos = 0x0 + // Bit mask of WAKEUP_CAUSE field. + RTC_CNTL_SLP_WAKEUP_CAUSE_WAKEUP_CAUSE_Msk = 0x1ffff + + // ULP_CP_TIMER_1: rtc configure register + // Position of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Pos = 0x8 + // Bit mask of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Msk = 0xffffff00 + + // INT_ENA_RTC_W1TS: rtc configure register + // Position of SLP_WAKEUP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS = 0x1 + // Position of SLP_REJECT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS = 0x2 + // Position of WDT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS_Pos = 0x3 + // Bit mask of WDT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS_Msk = 0x8 + // Bit WDT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS = 0x8 + // Position of BROWN_OUT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS = 0x200 + // Position of MAIN_TIMER_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS = 0x400 + // Position of SWD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS_Pos = 0xf + // Bit mask of SWD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS_Msk = 0x8000 + // Bit SWD_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS = 0x8000 + // Position of XTAL32K_DEAD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS = 0x10000 + // Position of GLITCH_DET_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS_Msk = 0x80000 + // Bit GLITCH_DET_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS = 0x80000 + // Position of BBPLL_CAL_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS_Msk = 0x100000 + // Bit BBPLL_CAL_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_BBPLL_CAL_INT_ENA_W1TS = 0x100000 + + // INT_ENA_RTC_W1TC: rtc configure register + // Position of SLP_WAKEUP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC = 0x1 + // Position of SLP_REJECT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC = 0x2 + // Position of WDT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC_Pos = 0x3 + // Bit mask of WDT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC_Msk = 0x8 + // Bit WDT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC = 0x8 + // Position of BROWN_OUT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC = 0x200 + // Position of MAIN_TIMER_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC = 0x400 + // Position of SWD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC_Pos = 0xf + // Bit mask of SWD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC_Msk = 0x8000 + // Bit SWD_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC = 0x8000 + // Position of XTAL32K_DEAD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC = 0x10000 + // Position of GLITCH_DET_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC_Msk = 0x80000 + // Bit GLITCH_DET_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC = 0x80000 + // Position of BBPLL_CAL_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC_Pos = 0x14 + // Bit mask of BBPLL_CAL_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC_Msk = 0x100000 + // Bit BBPLL_CAL_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_BBPLL_CAL_INT_ENA_W1TC = 0x100000 + + // RETENTION_CTRL: rtc configure register + // Position of RETENTION_CLK_SEL field. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLK_SEL_Pos = 0x12 + // Bit mask of RETENTION_CLK_SEL field. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLK_SEL_Msk = 0x40000 + // Bit RETENTION_CLK_SEL. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLK_SEL = 0x40000 + // Position of RETENTION_DONE_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_DONE_WAIT_Pos = 0x13 + // Bit mask of RETENTION_DONE_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_DONE_WAIT_Msk = 0x380000 + // Position of RETENTION_CLKOFF_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLKOFF_WAIT_Pos = 0x16 + // Bit mask of RETENTION_CLKOFF_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLKOFF_WAIT_Msk = 0x3c00000 + // Position of RETENTION_EN field. + RTC_CNTL_RETENTION_CTRL_RETENTION_EN_Pos = 0x1a + // Bit mask of RETENTION_EN field. + RTC_CNTL_RETENTION_CTRL_RETENTION_EN_Msk = 0x4000000 + // Bit RETENTION_EN. + RTC_CNTL_RETENTION_CTRL_RETENTION_EN = 0x4000000 + // Position of RETENTION_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_WAIT_Pos = 0x1b + // Bit mask of RETENTION_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_WAIT_Msk = 0xf8000000 + + // FIB_SEL: rtc configure register + // Position of FIB_SEL field. + RTC_CNTL_FIB_SEL_FIB_SEL_Pos = 0x0 + // Bit mask of FIB_SEL field. + RTC_CNTL_FIB_SEL_FIB_SEL_Msk = 0x7 + + // GPIO_WAKEUP: rtc configure register + // Position of GPIO_WAKEUP_STATUS field. + RTC_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_Pos = 0x0 + // Bit mask of GPIO_WAKEUP_STATUS field. + RTC_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_Msk = 0x3f + // Position of GPIO_WAKEUP_STATUS_CLR field. + RTC_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR_Pos = 0x6 + // Bit mask of GPIO_WAKEUP_STATUS_CLR field. + RTC_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR_Msk = 0x40 + // Bit GPIO_WAKEUP_STATUS_CLR. + RTC_CNTL_GPIO_WAKEUP_GPIO_WAKEUP_STATUS_CLR = 0x40 + // Position of GPIO_PIN_CLK_GATE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN_CLK_GATE_Pos = 0x7 + // Bit mask of GPIO_PIN_CLK_GATE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN_CLK_GATE_Msk = 0x80 + // Bit GPIO_PIN_CLK_GATE. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN_CLK_GATE = 0x80 + // Position of GPIO_PIN5_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN5_INT_TYPE_Pos = 0x8 + // Bit mask of GPIO_PIN5_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN5_INT_TYPE_Msk = 0x700 + // Position of GPIO_PIN4_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN4_INT_TYPE_Pos = 0xb + // Bit mask of GPIO_PIN4_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN4_INT_TYPE_Msk = 0x3800 + // Position of GPIO_PIN3_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN3_INT_TYPE_Pos = 0xe + // Bit mask of GPIO_PIN3_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN3_INT_TYPE_Msk = 0x1c000 + // Position of GPIO_PIN2_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN2_INT_TYPE_Pos = 0x11 + // Bit mask of GPIO_PIN2_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN2_INT_TYPE_Msk = 0xe0000 + // Position of GPIO_PIN1_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN1_INT_TYPE_Pos = 0x14 + // Bit mask of GPIO_PIN1_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN1_INT_TYPE_Msk = 0x700000 + // Position of GPIO_PIN0_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN0_INT_TYPE_Pos = 0x17 + // Bit mask of GPIO_PIN0_INT_TYPE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN0_INT_TYPE_Msk = 0x3800000 + // Position of GPIO_PIN5_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE_Pos = 0x1a + // Bit mask of GPIO_PIN5_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE_Msk = 0x4000000 + // Bit GPIO_PIN5_WAKEUP_ENABLE. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN5_WAKEUP_ENABLE = 0x4000000 + // Position of GPIO_PIN4_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE_Pos = 0x1b + // Bit mask of GPIO_PIN4_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE_Msk = 0x8000000 + // Bit GPIO_PIN4_WAKEUP_ENABLE. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN4_WAKEUP_ENABLE = 0x8000000 + // Position of GPIO_PIN3_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE_Pos = 0x1c + // Bit mask of GPIO_PIN3_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE_Msk = 0x10000000 + // Bit GPIO_PIN3_WAKEUP_ENABLE. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN3_WAKEUP_ENABLE = 0x10000000 + // Position of GPIO_PIN2_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE_Pos = 0x1d + // Bit mask of GPIO_PIN2_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE_Msk = 0x20000000 + // Bit GPIO_PIN2_WAKEUP_ENABLE. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN2_WAKEUP_ENABLE = 0x20000000 + // Position of GPIO_PIN1_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE_Pos = 0x1e + // Bit mask of GPIO_PIN1_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE_Msk = 0x40000000 + // Bit GPIO_PIN1_WAKEUP_ENABLE. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN1_WAKEUP_ENABLE = 0x40000000 + // Position of GPIO_PIN0_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE_Pos = 0x1f + // Bit mask of GPIO_PIN0_WAKEUP_ENABLE field. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE_Msk = 0x80000000 + // Bit GPIO_PIN0_WAKEUP_ENABLE. + RTC_CNTL_GPIO_WAKEUP_GPIO_PIN0_WAKEUP_ENABLE = 0x80000000 + + // DBG_SEL: rtc configure register + // Position of DEBUG_12M_NO_GATING field. + RTC_CNTL_DBG_SEL_DEBUG_12M_NO_GATING_Pos = 0x1 + // Bit mask of DEBUG_12M_NO_GATING field. + RTC_CNTL_DBG_SEL_DEBUG_12M_NO_GATING_Msk = 0x2 + // Bit DEBUG_12M_NO_GATING. + RTC_CNTL_DBG_SEL_DEBUG_12M_NO_GATING = 0x2 + // Position of DEBUG_BIT_SEL field. + RTC_CNTL_DBG_SEL_DEBUG_BIT_SEL_Pos = 0x2 + // Bit mask of DEBUG_BIT_SEL field. + RTC_CNTL_DBG_SEL_DEBUG_BIT_SEL_Msk = 0x7c + // Position of DEBUG_SEL0 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL0_Pos = 0x7 + // Bit mask of DEBUG_SEL0 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL0_Msk = 0xf80 + // Position of DEBUG_SEL1 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL1_Pos = 0xc + // Bit mask of DEBUG_SEL1 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL1_Msk = 0x1f000 + // Position of DEBUG_SEL2 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL2_Pos = 0x11 + // Bit mask of DEBUG_SEL2 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL2_Msk = 0x3e0000 + // Position of DEBUG_SEL3 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL3_Pos = 0x16 + // Bit mask of DEBUG_SEL3 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL3_Msk = 0x7c00000 + // Position of DEBUG_SEL4 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL4_Pos = 0x1b + // Bit mask of DEBUG_SEL4 field. + RTC_CNTL_DBG_SEL_DEBUG_SEL4_Msk = 0xf8000000 + + // DBG_MAP: rtc configure register + // Position of GPIO_PIN5_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN5_MUX_SEL_Pos = 0x2 + // Bit mask of GPIO_PIN5_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN5_MUX_SEL_Msk = 0x4 + // Bit GPIO_PIN5_MUX_SEL. + RTC_CNTL_DBG_MAP_GPIO_PIN5_MUX_SEL = 0x4 + // Position of GPIO_PIN4_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN4_MUX_SEL_Pos = 0x3 + // Bit mask of GPIO_PIN4_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN4_MUX_SEL_Msk = 0x8 + // Bit GPIO_PIN4_MUX_SEL. + RTC_CNTL_DBG_MAP_GPIO_PIN4_MUX_SEL = 0x8 + // Position of GPIO_PIN3_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN3_MUX_SEL_Pos = 0x4 + // Bit mask of GPIO_PIN3_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN3_MUX_SEL_Msk = 0x10 + // Bit GPIO_PIN3_MUX_SEL. + RTC_CNTL_DBG_MAP_GPIO_PIN3_MUX_SEL = 0x10 + // Position of GPIO_PIN2_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN2_MUX_SEL_Pos = 0x5 + // Bit mask of GPIO_PIN2_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN2_MUX_SEL_Msk = 0x20 + // Bit GPIO_PIN2_MUX_SEL. + RTC_CNTL_DBG_MAP_GPIO_PIN2_MUX_SEL = 0x20 + // Position of GPIO_PIN1_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN1_MUX_SEL_Pos = 0x6 + // Bit mask of GPIO_PIN1_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN1_MUX_SEL_Msk = 0x40 + // Bit GPIO_PIN1_MUX_SEL. + RTC_CNTL_DBG_MAP_GPIO_PIN1_MUX_SEL = 0x40 + // Position of GPIO_PIN0_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN0_MUX_SEL_Pos = 0x7 + // Bit mask of GPIO_PIN0_MUX_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN0_MUX_SEL_Msk = 0x80 + // Bit GPIO_PIN0_MUX_SEL. + RTC_CNTL_DBG_MAP_GPIO_PIN0_MUX_SEL = 0x80 + // Position of GPIO_PIN5_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN5_FUN_SEL_Pos = 0x8 + // Bit mask of GPIO_PIN5_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN5_FUN_SEL_Msk = 0xf00 + // Position of GPIO_PIN4_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN4_FUN_SEL_Pos = 0xc + // Bit mask of GPIO_PIN4_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN4_FUN_SEL_Msk = 0xf000 + // Position of GPIO_PIN3_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN3_FUN_SEL_Pos = 0x10 + // Bit mask of GPIO_PIN3_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN3_FUN_SEL_Msk = 0xf0000 + // Position of GPIO_PIN2_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN2_FUN_SEL_Pos = 0x14 + // Bit mask of GPIO_PIN2_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN2_FUN_SEL_Msk = 0xf00000 + // Position of GPIO_PIN1_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN1_FUN_SEL_Pos = 0x18 + // Bit mask of GPIO_PIN1_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN1_FUN_SEL_Msk = 0xf000000 + // Position of GPIO_PIN0_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN0_FUN_SEL_Pos = 0x1c + // Bit mask of GPIO_PIN0_FUN_SEL field. + RTC_CNTL_DBG_MAP_GPIO_PIN0_FUN_SEL_Msk = 0xf0000000 + + // SENSOR_CTRL: rtc configure register + // Position of SAR2_PWDET_CCT field. + RTC_CNTL_SENSOR_CTRL_SAR2_PWDET_CCT_Pos = 0x1b + // Bit mask of SAR2_PWDET_CCT field. + RTC_CNTL_SENSOR_CTRL_SAR2_PWDET_CCT_Msk = 0x38000000 + // Position of FORCE_XPD_SAR field. + RTC_CNTL_SENSOR_CTRL_FORCE_XPD_SAR_Pos = 0x1e + // Bit mask of FORCE_XPD_SAR field. + RTC_CNTL_SENSOR_CTRL_FORCE_XPD_SAR_Msk = 0xc0000000 + + // DBG_SAR_SEL: rtc configure register + // Position of SAR_DEBUG_SEL field. + RTC_CNTL_DBG_SAR_SEL_SAR_DEBUG_SEL_Pos = 0x1b + // Bit mask of SAR_DEBUG_SEL field. + RTC_CNTL_DBG_SAR_SEL_SAR_DEBUG_SEL_Msk = 0xf8000000 + + // PG_CTRL: rtc configure register + // Position of POWER_GLITCH_DSENSE field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_DSENSE_Pos = 0x1a + // Bit mask of POWER_GLITCH_DSENSE field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_DSENSE_Msk = 0xc000000 + // Position of POWER_GLITCH_FORCE_PD field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PD_Pos = 0x1c + // Bit mask of POWER_GLITCH_FORCE_PD field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PD_Msk = 0x10000000 + // Bit POWER_GLITCH_FORCE_PD. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PD = 0x10000000 + // Position of POWER_GLITCH_FORCE_PU field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PU_Pos = 0x1d + // Bit mask of POWER_GLITCH_FORCE_PU field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PU_Msk = 0x20000000 + // Bit POWER_GLITCH_FORCE_PU. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PU = 0x20000000 + // Position of POWER_GLITCH_EFUSE_SEL field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EFUSE_SEL_Pos = 0x1e + // Bit mask of POWER_GLITCH_EFUSE_SEL field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EFUSE_SEL_Msk = 0x40000000 + // Bit POWER_GLITCH_EFUSE_SEL. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EFUSE_SEL = 0x40000000 + // Position of POWER_GLITCH_EN field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EN_Pos = 0x1f + // Bit mask of POWER_GLITCH_EN field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EN_Msk = 0x80000000 + // Bit POWER_GLITCH_EN. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EN = 0x80000000 + + // DATE: rtc configure register + // Position of DATE field. + RTC_CNTL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RTC_CNTL_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SENSITIVE: SENSITIVE Peripheral +const ( + // ROM_TABLE_LOCK: SENSITIVE_ROM_TABLE_LOCK_REG + // Position of ROM_TABLE_LOCK field. + SENSITIVE_ROM_TABLE_LOCK_ROM_TABLE_LOCK_Pos = 0x0 + // Bit mask of ROM_TABLE_LOCK field. + SENSITIVE_ROM_TABLE_LOCK_ROM_TABLE_LOCK_Msk = 0x1 + // Bit ROM_TABLE_LOCK. + SENSITIVE_ROM_TABLE_LOCK_ROM_TABLE_LOCK = 0x1 + + // ROM_TABLE: SENSITIVE_ROM_TABLE_REG + // Position of ROM_TABLE field. + SENSITIVE_ROM_TABLE_ROM_TABLE_Pos = 0x0 + // Bit mask of ROM_TABLE field. + SENSITIVE_ROM_TABLE_ROM_TABLE_Msk = 0xffffffff + + // PRIVILEGE_MODE_SEL_LOCK: SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG + // Position of PRIVILEGE_MODE_SEL_LOCK field. + SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_PRIVILEGE_MODE_SEL_LOCK_Pos = 0x0 + // Bit mask of PRIVILEGE_MODE_SEL_LOCK field. + SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_PRIVILEGE_MODE_SEL_LOCK_Msk = 0x1 + // Bit PRIVILEGE_MODE_SEL_LOCK. + SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_PRIVILEGE_MODE_SEL_LOCK = 0x1 + + // PRIVILEGE_MODE_SEL: SENSITIVE_PRIVILEGE_MODE_SEL_REG + // Position of PRIVILEGE_MODE_SEL field. + SENSITIVE_PRIVILEGE_MODE_SEL_PRIVILEGE_MODE_SEL_Pos = 0x0 + // Bit mask of PRIVILEGE_MODE_SEL field. + SENSITIVE_PRIVILEGE_MODE_SEL_PRIVILEGE_MODE_SEL_Msk = 0x1 + // Bit PRIVILEGE_MODE_SEL. + SENSITIVE_PRIVILEGE_MODE_SEL_PRIVILEGE_MODE_SEL = 0x1 + + // APB_PERIPHERAL_ACCESS_0: SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG + // Position of APB_PERIPHERAL_ACCESS_LOCK field. + SENSITIVE_APB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK_Pos = 0x0 + // Bit mask of APB_PERIPHERAL_ACCESS_LOCK field. + SENSITIVE_APB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK_Msk = 0x1 + // Bit APB_PERIPHERAL_ACCESS_LOCK. + SENSITIVE_APB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK = 0x1 + + // APB_PERIPHERAL_ACCESS_1: SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG + // Position of APB_PERIPHERAL_ACCESS_SPLIT_BURST field. + SENSITIVE_APB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST_Pos = 0x0 + // Bit mask of APB_PERIPHERAL_ACCESS_SPLIT_BURST field. + SENSITIVE_APB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST_Msk = 0x1 + // Bit APB_PERIPHERAL_ACCESS_SPLIT_BURST. + SENSITIVE_APB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST = 0x1 + + // INTERNAL_SRAM_USAGE_0: SENSITIVE_INTERNAL_SRAM_USAGE_0_REG + // Position of INTERNAL_SRAM_USAGE_LOCK field. + SENSITIVE_INTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_USAGE_LOCK field. + SENSITIVE_INTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK_Msk = 0x1 + // Bit INTERNAL_SRAM_USAGE_LOCK. + SENSITIVE_INTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK = 0x1 + + // INTERNAL_SRAM_USAGE_1: SENSITIVE_INTERNAL_SRAM_USAGE_1_REG + // Position of INTERNAL_SRAM_USAGE_CPU_CACHE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_USAGE_CPU_CACHE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE_Msk = 0x1 + // Bit INTERNAL_SRAM_USAGE_CPU_CACHE. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_CACHE = 0x1 + // Position of INTERNAL_SRAM_USAGE_CPU_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_SRAM_Pos = 0x1 + // Bit mask of INTERNAL_SRAM_USAGE_CPU_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_USAGE_CPU_SRAM_Msk = 0xe + + // INTERNAL_SRAM_USAGE_3: SENSITIVE_INTERNAL_SRAM_USAGE_3_REG + // Position of INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_Msk = 0x7 + // Position of INTERNAL_SRAM_ALLOC_MAC_DUMP field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP_Pos = 0x3 + // Bit mask of INTERNAL_SRAM_ALLOC_MAC_DUMP field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP_Msk = 0x8 + // Bit INTERNAL_SRAM_ALLOC_MAC_DUMP. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_ALLOC_MAC_DUMP = 0x8 + + // INTERNAL_SRAM_USAGE_4: SENSITIVE_INTERNAL_SRAM_USAGE_4_REG + // Position of INTERNAL_SRAM_USAGE_LOG_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_4_INTERNAL_SRAM_USAGE_LOG_SRAM_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_USAGE_LOG_SRAM field. + SENSITIVE_INTERNAL_SRAM_USAGE_4_INTERNAL_SRAM_USAGE_LOG_SRAM_Msk = 0x1 + // Bit INTERNAL_SRAM_USAGE_LOG_SRAM. + SENSITIVE_INTERNAL_SRAM_USAGE_4_INTERNAL_SRAM_USAGE_LOG_SRAM = 0x1 + + // CACHE_TAG_ACCESS_0: SENSITIVE_CACHE_TAG_ACCESS_0_REG + // Position of CACHE_TAG_ACCESS_LOCK field. + SENSITIVE_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK_Pos = 0x0 + // Bit mask of CACHE_TAG_ACCESS_LOCK field. + SENSITIVE_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK_Msk = 0x1 + // Bit CACHE_TAG_ACCESS_LOCK. + SENSITIVE_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK = 0x1 + + // CACHE_TAG_ACCESS_1: SENSITIVE_CACHE_TAG_ACCESS_1_REG + // Position of PRO_I_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS_Pos = 0x0 + // Bit mask of PRO_I_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS_Msk = 0x1 + // Bit PRO_I_TAG_RD_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS = 0x1 + // Position of PRO_I_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS_Pos = 0x1 + // Bit mask of PRO_I_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS_Msk = 0x2 + // Bit PRO_I_TAG_WR_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS = 0x2 + // Position of PRO_D_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS_Pos = 0x2 + // Bit mask of PRO_D_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS_Msk = 0x4 + // Bit PRO_D_TAG_RD_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS = 0x4 + // Position of PRO_D_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS_Pos = 0x3 + // Bit mask of PRO_D_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS_Msk = 0x8 + // Bit PRO_D_TAG_WR_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS = 0x8 + + // CACHE_MMU_ACCESS_0: SENSITIVE_CACHE_MMU_ACCESS_0_REG + // Position of CACHE_MMU_ACCESS_LOCK field. + SENSITIVE_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK_Pos = 0x0 + // Bit mask of CACHE_MMU_ACCESS_LOCK field. + SENSITIVE_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK_Msk = 0x1 + // Bit CACHE_MMU_ACCESS_LOCK. + SENSITIVE_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK = 0x1 + + // CACHE_MMU_ACCESS_1: SENSITIVE_CACHE_MMU_ACCESS_1_REG + // Position of PRO_MMU_RD_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS_Pos = 0x0 + // Bit mask of PRO_MMU_RD_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS_Msk = 0x1 + // Bit PRO_MMU_RD_ACS. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS = 0x1 + // Position of PRO_MMU_WR_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS_Pos = 0x1 + // Bit mask of PRO_MMU_WR_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS_Msk = 0x2 + // Bit PRO_MMU_WR_ACS. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS = 0x2 + + // DMA_APBPERI_SPI2_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_SPI2_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + + // DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG + // Position of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG + // Position of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + + // DMA_APBPERI_I2S0_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_I2S0_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + + // DMA_APBPERI_MAC_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_MAC_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + + // DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + + // DMA_APBPERI_LC_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_LC_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + + // DMA_APBPERI_AES_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_AES_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + + // DMA_APBPERI_SHA_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_SHA_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + + // DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0: SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1: SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + + // DMA_APBPERI_PMS_MONITOR_0: SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG + // Position of DMA_APBPERI_PMS_MONITOR_LOCK field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_LOCK field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_PMS_MONITOR_LOCK. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK = 0x1 + + // DMA_APBPERI_PMS_MONITOR_1: SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit DMA_APBPERI_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN = 0x2 + + // DMA_APBPERI_PMS_MONITOR_2: SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_Pos = 0x1 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_Msk = 0x6 + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_Pos = 0x3 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_Msk = 0x7fffff8 + + // DMA_APBPERI_PMS_MONITOR_3: SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_Msk = 0x1 + // Bit DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR = 0x1 + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Pos = 0x1 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Msk = 0x1e + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG + // Position of CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK = 0x1 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_Msk = 0xc + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_Msk = 0xc + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_Msk = 0xc + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_Msk = 0xc + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_Msk = 0xc + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_PMS_CONSTRAIN_0: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_X_IRAM0_PMS_CONSTRAIN_LOCK. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK = 0x1 + + // CORE_X_IRAM0_PMS_CONSTRAIN_1: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x7 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0x3 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0x38 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x6 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x1c0 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x9 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xe00 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_Pos = 0xc + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_Msk = 0x7000 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_Pos = 0x12 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_Msk = 0x1c0000 + + // CORE_X_IRAM0_PMS_CONSTRAIN_2: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x7 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x3 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0x38 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x6 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x1c0 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x9 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xe00 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_Pos = 0xc + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_Msk = 0x7000 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_Pos = 0x12 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_Msk = 0x1c0000 + + // CORE_0_IRAM0_PMS_MONITOR_0: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG + // Position of CORE_0_IRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit CORE_0_IRAM0_PMS_MONITOR_LOCK. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK = 0x1 + + // CORE_0_IRAM0_PMS_MONITOR_1: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN = 0x2 + + // CORE_0_IRAM0_PMS_MONITOR_2: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Pos = 0x1 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Msk = 0x2 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR = 0x2 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_Pos = 0x2 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_Msk = 0x4 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE = 0x4 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Pos = 0x3 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Msk = 0x18 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Pos = 0x5 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Msk = 0x1fffffe0 + + // CORE_X_DRAM0_PMS_CONSTRAIN_0: SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_X_DRAM0_PMS_CONSTRAIN_LOCK. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK = 0x1 + + // CORE_X_DRAM0_PMS_CONSTRAIN_1: SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_Pos = 0x18 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_Msk = 0x3000000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_Pos = 0x1a + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_Msk = 0xc000000 + + // CORE_0_DRAM0_PMS_MONITOR_0: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG + // Position of CORE_0_DRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit CORE_0_DRAM0_PMS_MONITOR_LOCK. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK = 0x1 + + // CORE_0_DRAM0_PMS_MONITOR_1: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN = 0x2 + + // CORE_0_DRAM0_PMS_MONITOR_2: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_Pos = 0x1 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_Msk = 0x2 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK = 0x2 + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Pos = 0x2 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Msk = 0xc + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Pos = 0x4 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Msk = 0xffffff0 + + // CORE_0_DRAM0_PMS_MONITOR_3: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Msk = 0x1 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR = 0x1 + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Pos = 0x1 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Msk = 0x1e + + // CORE_0_PIF_PMS_CONSTRAIN_0: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_0_PIF_PMS_CONSTRAIN_LOCK. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK = 0x1 + + // CORE_0_PIF_PMS_CONSTRAIN_1: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_Pos = 0x12 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_Msk = 0xc0000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_2: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_3: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_Msk = 0x30000000 + + // CORE_0_PIF_PMS_CONSTRAIN_4: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_Pos = 0x12 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_Msk = 0xc0000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_Pos = 0x14 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_Msk = 0x300000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_5: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_Pos = 0x12 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_Msk = 0xc0000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_6: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_7: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_Msk = 0x30000000 + + // CORE_0_PIF_PMS_CONSTRAIN_8: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_Pos = 0x12 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_Msk = 0xc0000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_Pos = 0x14 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_Msk = 0x300000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_9: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_Msk = 0x7ff + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_Pos = 0xb + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_Msk = 0x3ff800 + + // CORE_0_PIF_PMS_CONSTRAIN_10: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_Msk = 0x7 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_Pos = 0x3 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_Msk = 0x38 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_Msk = 0x1c0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_Pos = 0x9 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_Msk = 0xe00 + + // REGION_PMS_CONSTRAIN_0: SENSITIVE_REGION_PMS_CONSTRAIN_0_REG + // Position of REGION_PMS_CONSTRAIN_LOCK field. + SENSITIVE_REGION_PMS_CONSTRAIN_0_REGION_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_LOCK field. + SENSITIVE_REGION_PMS_CONSTRAIN_0_REGION_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit REGION_PMS_CONSTRAIN_LOCK. + SENSITIVE_REGION_PMS_CONSTRAIN_0_REGION_PMS_CONSTRAIN_LOCK = 0x1 + + // REGION_PMS_CONSTRAIN_1: SENSITIVE_REGION_PMS_CONSTRAIN_1_REG + // Position of REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_Msk = 0x3 + // Position of REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_Pos = 0x2 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_Msk = 0xc + // Position of REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_Pos = 0x4 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_Msk = 0x30 + // Position of REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_Pos = 0x6 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_Msk = 0xc0 + // Position of REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_Pos = 0x8 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_Msk = 0x300 + // Position of REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_Pos = 0xa + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_Msk = 0xc00 + // Position of REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_Pos = 0xc + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 field. + SENSITIVE_REGION_PMS_CONSTRAIN_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_Msk = 0x3000 + + // REGION_PMS_CONSTRAIN_2: SENSITIVE_REGION_PMS_CONSTRAIN_2_REG + // Position of REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_Msk = 0x3 + // Position of REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_Pos = 0x2 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_Msk = 0xc + // Position of REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_Pos = 0x4 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_Msk = 0x30 + // Position of REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_Pos = 0x6 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_Msk = 0xc0 + // Position of REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_Pos = 0x8 + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_Msk = 0x300 + // Position of REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_Pos = 0xa + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_Msk = 0xc00 + // Position of REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_Pos = 0xc + // Bit mask of REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 field. + SENSITIVE_REGION_PMS_CONSTRAIN_2_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_Msk = 0x3000 + + // REGION_PMS_CONSTRAIN_3: SENSITIVE_REGION_PMS_CONSTRAIN_3_REG + // Position of REGION_PMS_CONSTRAIN_ADDR_0 field. + SENSITIVE_REGION_PMS_CONSTRAIN_3_REGION_PMS_CONSTRAIN_ADDR_0_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_ADDR_0 field. + SENSITIVE_REGION_PMS_CONSTRAIN_3_REGION_PMS_CONSTRAIN_ADDR_0_Msk = 0x3fffffff + + // REGION_PMS_CONSTRAIN_4: SENSITIVE_REGION_PMS_CONSTRAIN_4_REG + // Position of REGION_PMS_CONSTRAIN_ADDR_1 field. + SENSITIVE_REGION_PMS_CONSTRAIN_4_REGION_PMS_CONSTRAIN_ADDR_1_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_ADDR_1 field. + SENSITIVE_REGION_PMS_CONSTRAIN_4_REGION_PMS_CONSTRAIN_ADDR_1_Msk = 0x3fffffff + + // REGION_PMS_CONSTRAIN_5: SENSITIVE_REGION_PMS_CONSTRAIN_5_REG + // Position of REGION_PMS_CONSTRAIN_ADDR_2 field. + SENSITIVE_REGION_PMS_CONSTRAIN_5_REGION_PMS_CONSTRAIN_ADDR_2_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_ADDR_2 field. + SENSITIVE_REGION_PMS_CONSTRAIN_5_REGION_PMS_CONSTRAIN_ADDR_2_Msk = 0x3fffffff + + // REGION_PMS_CONSTRAIN_6: SENSITIVE_REGION_PMS_CONSTRAIN_6_REG + // Position of REGION_PMS_CONSTRAIN_ADDR_3 field. + SENSITIVE_REGION_PMS_CONSTRAIN_6_REGION_PMS_CONSTRAIN_ADDR_3_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_ADDR_3 field. + SENSITIVE_REGION_PMS_CONSTRAIN_6_REGION_PMS_CONSTRAIN_ADDR_3_Msk = 0x3fffffff + + // REGION_PMS_CONSTRAIN_7: SENSITIVE_REGION_PMS_CONSTRAIN_7_REG + // Position of REGION_PMS_CONSTRAIN_ADDR_4 field. + SENSITIVE_REGION_PMS_CONSTRAIN_7_REGION_PMS_CONSTRAIN_ADDR_4_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_ADDR_4 field. + SENSITIVE_REGION_PMS_CONSTRAIN_7_REGION_PMS_CONSTRAIN_ADDR_4_Msk = 0x3fffffff + + // REGION_PMS_CONSTRAIN_8: SENSITIVE_REGION_PMS_CONSTRAIN_8_REG + // Position of REGION_PMS_CONSTRAIN_ADDR_5 field. + SENSITIVE_REGION_PMS_CONSTRAIN_8_REGION_PMS_CONSTRAIN_ADDR_5_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_ADDR_5 field. + SENSITIVE_REGION_PMS_CONSTRAIN_8_REGION_PMS_CONSTRAIN_ADDR_5_Msk = 0x3fffffff + + // REGION_PMS_CONSTRAIN_9: SENSITIVE_REGION_PMS_CONSTRAIN_9_REG + // Position of REGION_PMS_CONSTRAIN_ADDR_6 field. + SENSITIVE_REGION_PMS_CONSTRAIN_9_REGION_PMS_CONSTRAIN_ADDR_6_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_ADDR_6 field. + SENSITIVE_REGION_PMS_CONSTRAIN_9_REGION_PMS_CONSTRAIN_ADDR_6_Msk = 0x3fffffff + + // REGION_PMS_CONSTRAIN_10: SENSITIVE_REGION_PMS_CONSTRAIN_10_REG + // Position of REGION_PMS_CONSTRAIN_ADDR_7 field. + SENSITIVE_REGION_PMS_CONSTRAIN_10_REGION_PMS_CONSTRAIN_ADDR_7_Pos = 0x0 + // Bit mask of REGION_PMS_CONSTRAIN_ADDR_7 field. + SENSITIVE_REGION_PMS_CONSTRAIN_10_REGION_PMS_CONSTRAIN_ADDR_7_Msk = 0x3fffffff + + // CORE_0_PIF_PMS_MONITOR_0: SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG + // Position of CORE_0_PIF_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_LOCK. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK = 0x1 + + // CORE_0_PIF_PMS_MONITOR_1: SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN = 0x2 + + // CORE_0_PIF_PMS_MONITOR_2: SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_Pos = 0x1 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_Msk = 0x2 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 = 0x2 + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Msk = 0x1c + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Pos = 0x5 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Msk = 0x20 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE = 0x20 + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_Msk = 0xc0 + + // CORE_0_PIF_PMS_MONITOR_3: SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_Msk = 0xffffffff + + // CORE_0_PIF_PMS_MONITOR_4: SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR = 0x1 + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_Msk = 0x2 + // Bit CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN = 0x2 + + // CORE_0_PIF_PMS_MONITOR_5: SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR = 0x1 + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_Pos = 0x1 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_Msk = 0x6 + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_Pos = 0x3 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_Msk = 0x18 + + // CORE_0_PIF_PMS_MONITOR_6: SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_Msk = 0xffffffff + + // BACKUP_BUS_PMS_CONSTRAIN_0: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG + // Position of BACKUP_BUS_PMS_CONSTRAIN_LOCK field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_LOCK field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit BACKUP_BUS_PMS_CONSTRAIN_LOCK. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK = 0x1 + + // BACKUP_BUS_PMS_CONSTRAIN_1: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG + // Position of BACKUP_BUS_PMS_CONSTRAIN_UART field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_UART field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART_Msk = 0x3 + // Position of BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_Pos = 0x2 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_Msk = 0xc + // Position of BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_Pos = 0x4 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_Msk = 0x30 + // Position of BACKUP_BUS_PMS_CONSTRAIN_GPIO field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_GPIO_Pos = 0x6 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_GPIO field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_GPIO_Msk = 0xc0 + // Position of BACKUP_BUS_PMS_CONSTRAIN_FE2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE2_Pos = 0x8 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_FE2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE2_Msk = 0x300 + // Position of BACKUP_BUS_PMS_CONSTRAIN_FE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE_Pos = 0xa + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_FE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE_Msk = 0xc00 + // Position of BACKUP_BUS_PMS_CONSTRAIN_TIMER field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_TIMER_Pos = 0xc + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_TIMER field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_TIMER_Msk = 0x3000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_RTC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_RTC_Pos = 0xe + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_RTC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_RTC_Msk = 0xc000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_IO_MUX field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_Pos = 0x10 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_IO_MUX field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_Msk = 0x30000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_WDG field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_WDG_Pos = 0x12 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_WDG field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_WDG_Msk = 0xc0000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_MISC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_MISC_Pos = 0x18 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_MISC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_MISC_Msk = 0x3000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_I2C field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2C_Pos = 0x1a + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_I2C field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2C_Msk = 0xc000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_UART1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART1_Pos = 0x1e + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_UART1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART1_Msk = 0xc0000000 + + // BACKUP_BUS_PMS_CONSTRAIN_2: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG + // Position of BACKUP_BUS_PMS_CONSTRAIN_BT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BT_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_BT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BT_Msk = 0x3 + // Position of BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_Pos = 0x4 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_Msk = 0x30 + // Position of BACKUP_BUS_PMS_CONSTRAIN_UHCI0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_Pos = 0x6 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_UHCI0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_Msk = 0xc0 + // Position of BACKUP_BUS_PMS_CONSTRAIN_RMT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_RMT_Pos = 0xa + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_RMT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_RMT_Msk = 0xc00 + // Position of BACKUP_BUS_PMS_CONSTRAIN_LEDC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_LEDC_Pos = 0x10 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_LEDC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_LEDC_Msk = 0x30000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_BB field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BB_Pos = 0x16 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_BB field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BB_Msk = 0xc00000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_Pos = 0x1a + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_Msk = 0xc000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_Pos = 0x1c + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_Msk = 0x30000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_Pos = 0x1e + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_Msk = 0xc0000000 + + // BACKUP_BUS_PMS_CONSTRAIN_3: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG + // Position of BACKUP_BUS_PMS_CONSTRAIN_SPI_2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SPI_2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_Msk = 0x3 + // Position of BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_Pos = 0x4 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_Msk = 0x30 + // Position of BACKUP_BUS_PMS_CONSTRAIN_CAN field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_CAN_Pos = 0xa + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_CAN field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_CAN_Msk = 0xc00 + // Position of BACKUP_BUS_PMS_CONSTRAIN_I2S1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2S1_Pos = 0xe + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_I2S1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2S1_Msk = 0xc000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_RWBT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_RWBT_Pos = 0x16 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_RWBT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_RWBT_Msk = 0xc00000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_Pos = 0x1a + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_Msk = 0xc000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_PWR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWR_Pos = 0x1c + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_PWR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWR_Msk = 0x30000000 + + // BACKUP_BUS_PMS_CONSTRAIN_4: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG + // Position of BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_Pos = 0x2 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_Msk = 0xc + // Position of BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_Pos = 0x4 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_Msk = 0x30 + // Position of BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_Pos = 0x6 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_Msk = 0xc0 + // Position of BACKUP_BUS_PMS_CONSTRAIN_APB_ADC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_Pos = 0x8 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_APB_ADC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_Msk = 0x300 + // Position of BACKUP_BUS_PMS_CONSTRAIN_BT_PWR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_Pos = 0xc + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_BT_PWR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_Msk = 0x3000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_Pos = 0xe + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_Msk = 0xc000 + + // BACKUP_BUS_PMS_MONITOR_0: SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG + // Position of BACKUP_BUS_PMS_MONITOR_LOCK field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_MONITOR_LOCK field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit BACKUP_BUS_PMS_MONITOR_LOCK. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK = 0x1 + + // BACKUP_BUS_PMS_MONITOR_1: SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit BACKUP_BUS_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN = 0x2 + + // BACKUP_BUS_PMS_MONITOR_2: SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_Pos = 0x1 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_Msk = 0x6 + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Pos = 0x3 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Msk = 0x38 + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Pos = 0x6 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Msk = 0x40 + // Bit BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE = 0x40 + + // BACKUP_BUS_PMS_MONITOR_3: SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_Msk = 0xffffffff + + // CLOCK_GATE: SENSITIVE_CLOCK_GATE_REG_REG + // Position of CLK_EN field. + SENSITIVE_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SENSITIVE_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SENSITIVE_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: SENSITIVE_DATE_REG + // Position of DATE field. + SENSITIVE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SENSITIVE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SHA: SHA (Secure Hash Algorithm) Accelerator +const ( + // MODE: Initial configuration register. + // Position of MODE field. + SHA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + SHA_MODE_MODE_Msk = 0x7 + + // T_STRING: SHA 512/t configuration register 0. + // Position of T_STRING field. + SHA_T_STRING_T_STRING_Pos = 0x0 + // Bit mask of T_STRING field. + SHA_T_STRING_T_STRING_Msk = 0xffffffff + + // T_LENGTH: SHA 512/t configuration register 1. + // Position of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Pos = 0x0 + // Bit mask of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Msk = 0x3f + + // DMA_BLOCK_NUM: DMA configuration register 0. + // Position of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Pos = 0x0 + // Bit mask of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Msk = 0x3f + + // START: Typical SHA configuration register 0. + // Position of START field. + SHA_START_START_Pos = 0x1 + // Bit mask of START field. + SHA_START_START_Msk = 0xfffffffe + + // CONTINUE: Typical SHA configuration register 1. + // Position of CONTINUE field. + SHA_CONTINUE_CONTINUE_Pos = 0x1 + // Bit mask of CONTINUE field. + SHA_CONTINUE_CONTINUE_Msk = 0xfffffffe + + // BUSY: Busy register. + // Position of STATE field. + SHA_BUSY_STATE_Pos = 0x0 + // Bit mask of STATE field. + SHA_BUSY_STATE_Msk = 0x1 + // Bit STATE. + SHA_BUSY_STATE = 0x1 + + // DMA_START: DMA configuration register 1. + // Position of DMA_START field. + SHA_DMA_START_DMA_START_Pos = 0x0 + // Bit mask of DMA_START field. + SHA_DMA_START_DMA_START_Msk = 0x1 + // Bit DMA_START. + SHA_DMA_START_DMA_START = 0x1 + + // DMA_CONTINUE: DMA configuration register 2. + // Position of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Pos = 0x0 + // Bit mask of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Msk = 0x1 + // Bit DMA_CONTINUE. + SHA_DMA_CONTINUE_DMA_CONTINUE = 0x1 + + // CLEAR_IRQ: Interrupt clear register. + // Position of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT = 0x1 + + // IRQ_ENA: Interrupt enable register. + // Position of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Pos = 0x0 + // Bit mask of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Msk = 0x1 + // Bit INTERRUPT_ENA. + SHA_IRQ_ENA_INTERRUPT_ENA = 0x1 + + // DATE: Date register. + // Position of DATE field. + SHA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SHA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for SPI0: SPI (Serial Peripheral Interface) Controller 0 +const ( + // CTRL: SPI0 control register. + // Position of FDUMMY_OUT field. + SPI0_CTRL_FDUMMY_OUT_Pos = 0x3 + // Bit mask of FDUMMY_OUT field. + SPI0_CTRL_FDUMMY_OUT_Msk = 0x8 + // Bit FDUMMY_OUT. + SPI0_CTRL_FDUMMY_OUT = 0x8 + // Position of FCMD_DUAL field. + SPI0_CTRL_FCMD_DUAL_Pos = 0x7 + // Bit mask of FCMD_DUAL field. + SPI0_CTRL_FCMD_DUAL_Msk = 0x80 + // Bit FCMD_DUAL. + SPI0_CTRL_FCMD_DUAL = 0x80 + // Position of FCMD_QUAD field. + SPI0_CTRL_FCMD_QUAD_Pos = 0x8 + // Bit mask of FCMD_QUAD field. + SPI0_CTRL_FCMD_QUAD_Msk = 0x100 + // Bit FCMD_QUAD. + SPI0_CTRL_FCMD_QUAD = 0x100 + // Position of FASTRD_MODE field. + SPI0_CTRL_FASTRD_MODE_Pos = 0xd + // Bit mask of FASTRD_MODE field. + SPI0_CTRL_FASTRD_MODE_Msk = 0x2000 + // Bit FASTRD_MODE. + SPI0_CTRL_FASTRD_MODE = 0x2000 + // Position of FREAD_DUAL field. + SPI0_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI0_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI0_CTRL_FREAD_DUAL = 0x4000 + // Position of Q_POL field. + SPI0_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI0_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI0_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI0_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI0_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI0_CTRL_D_POL = 0x80000 + // Position of FREAD_QUAD field. + SPI0_CTRL_FREAD_QUAD_Pos = 0x14 + // Bit mask of FREAD_QUAD field. + SPI0_CTRL_FREAD_QUAD_Msk = 0x100000 + // Bit FREAD_QUAD. + SPI0_CTRL_FREAD_QUAD = 0x100000 + // Position of WP field. + SPI0_CTRL_WP_Pos = 0x15 + // Bit mask of WP field. + SPI0_CTRL_WP_Msk = 0x200000 + // Bit WP. + SPI0_CTRL_WP = 0x200000 + // Position of FREAD_DIO field. + SPI0_CTRL_FREAD_DIO_Pos = 0x17 + // Bit mask of FREAD_DIO field. + SPI0_CTRL_FREAD_DIO_Msk = 0x800000 + // Bit FREAD_DIO. + SPI0_CTRL_FREAD_DIO = 0x800000 + // Position of FREAD_QIO field. + SPI0_CTRL_FREAD_QIO_Pos = 0x18 + // Bit mask of FREAD_QIO field. + SPI0_CTRL_FREAD_QIO_Msk = 0x1000000 + // Bit FREAD_QIO. + SPI0_CTRL_FREAD_QIO = 0x1000000 + + // CTRL1: SPI0 control1 register. + // Position of CLK_MODE field. + SPI0_CTRL1_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI0_CTRL1_CLK_MODE_Msk = 0x3 + // Position of RXFIFO_RST field. + SPI0_CTRL1_RXFIFO_RST_Pos = 0x1e + // Bit mask of RXFIFO_RST field. + SPI0_CTRL1_RXFIFO_RST_Msk = 0x40000000 + // Bit RXFIFO_RST. + SPI0_CTRL1_RXFIFO_RST = 0x40000000 + + // CTRL2: SPI0 control2 register. + // Position of CS_SETUP_TIME field. + SPI0_CTRL2_CS_SETUP_TIME_Pos = 0x0 + // Bit mask of CS_SETUP_TIME field. + SPI0_CTRL2_CS_SETUP_TIME_Msk = 0x1f + // Position of CS_HOLD_TIME field. + SPI0_CTRL2_CS_HOLD_TIME_Pos = 0x5 + // Bit mask of CS_HOLD_TIME field. + SPI0_CTRL2_CS_HOLD_TIME_Msk = 0x3e0 + // Position of CS_HOLD_DELAY field. + SPI0_CTRL2_CS_HOLD_DELAY_Pos = 0x19 + // Bit mask of CS_HOLD_DELAY field. + SPI0_CTRL2_CS_HOLD_DELAY_Msk = 0x7e000000 + // Position of SYNC_RESET field. + SPI0_CTRL2_SYNC_RESET_Pos = 0x1f + // Bit mask of SYNC_RESET field. + SPI0_CTRL2_SYNC_RESET_Msk = 0x80000000 + // Bit SYNC_RESET. + SPI0_CTRL2_SYNC_RESET = 0x80000000 + + // CLOCK: SPI clock division control register. + // Position of CLKCNT_L field. + SPI0_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI0_CLOCK_CLKCNT_L_Msk = 0xff + // Position of CLKCNT_H field. + SPI0_CLOCK_CLKCNT_H_Pos = 0x8 + // Bit mask of CLKCNT_H field. + SPI0_CLOCK_CLKCNT_H_Msk = 0xff00 + // Position of CLKCNT_N field. + SPI0_CLOCK_CLKCNT_N_Pos = 0x10 + // Bit mask of CLKCNT_N field. + SPI0_CLOCK_CLKCNT_N_Msk = 0xff0000 + // Position of CLK_EQU_SYSCLK field. + SPI0_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI0_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI0_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI0 user register. + // Position of CS_HOLD field. + SPI0_USER_CS_HOLD_Pos = 0x6 + // Bit mask of CS_HOLD field. + SPI0_USER_CS_HOLD_Msk = 0x40 + // Bit CS_HOLD. + SPI0_USER_CS_HOLD = 0x40 + // Position of CS_SETUP field. + SPI0_USER_CS_SETUP_Pos = 0x7 + // Bit mask of CS_SETUP field. + SPI0_USER_CS_SETUP_Msk = 0x80 + // Bit CS_SETUP. + SPI0_USER_CS_SETUP = 0x80 + // Position of CK_OUT_EDGE field. + SPI0_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI0_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI0_USER_CK_OUT_EDGE = 0x200 + // Position of USR_DUMMY_IDLE field. + SPI0_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI0_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI0_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_DUMMY field. + SPI0_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI0_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI0_USER_USR_DUMMY = 0x20000000 + + // USER1: SPI0 user1 register. + // Position of USR_DUMMY_CYCLELEN field. + SPI0_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI0_USER1_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of USR_ADDR_BITLEN field. + SPI0_USER1_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of USR_ADDR_BITLEN field. + SPI0_USER1_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // USER2: SPI0 user2 register. + // Position of USR_COMMAND_VALUE field. + SPI0_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI0_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of USR_COMMAND_BITLEN field. + SPI0_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI0_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // RD_STATUS: SPI0 read control register. + // Position of WB_MODE field. + SPI0_RD_STATUS_WB_MODE_Pos = 0x10 + // Bit mask of WB_MODE field. + SPI0_RD_STATUS_WB_MODE_Msk = 0xff0000 + + // MISC: SPI0 misc register + // Position of TRANS_END field. + SPI0_MISC_TRANS_END_Pos = 0x3 + // Bit mask of TRANS_END field. + SPI0_MISC_TRANS_END_Msk = 0x8 + // Bit TRANS_END. + SPI0_MISC_TRANS_END = 0x8 + // Position of TRANS_END_INT_ENA field. + SPI0_MISC_TRANS_END_INT_ENA_Pos = 0x4 + // Bit mask of TRANS_END_INT_ENA field. + SPI0_MISC_TRANS_END_INT_ENA_Msk = 0x10 + // Bit TRANS_END_INT_ENA. + SPI0_MISC_TRANS_END_INT_ENA = 0x10 + // Position of CSPI_ST_TRANS_END field. + SPI0_MISC_CSPI_ST_TRANS_END_Pos = 0x5 + // Bit mask of CSPI_ST_TRANS_END field. + SPI0_MISC_CSPI_ST_TRANS_END_Msk = 0x20 + // Bit CSPI_ST_TRANS_END. + SPI0_MISC_CSPI_ST_TRANS_END = 0x20 + // Position of CSPI_ST_TRANS_END_INT_ENA field. + SPI0_MISC_CSPI_ST_TRANS_END_INT_ENA_Pos = 0x6 + // Bit mask of CSPI_ST_TRANS_END_INT_ENA field. + SPI0_MISC_CSPI_ST_TRANS_END_INT_ENA_Msk = 0x40 + // Bit CSPI_ST_TRANS_END_INT_ENA. + SPI0_MISC_CSPI_ST_TRANS_END_INT_ENA = 0x40 + // Position of CK_IDLE_EDGE field. + SPI0_MISC_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of CK_IDLE_EDGE field. + SPI0_MISC_CK_IDLE_EDGE_Msk = 0x200 + // Bit CK_IDLE_EDGE. + SPI0_MISC_CK_IDLE_EDGE = 0x200 + // Position of CS_KEEP_ACTIVE field. + SPI0_MISC_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of CS_KEEP_ACTIVE field. + SPI0_MISC_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit CS_KEEP_ACTIVE. + SPI0_MISC_CS_KEEP_ACTIVE = 0x400 + + // CACHE_FCTRL: SPI0 bit mode control register. + // Position of CACHE_REQ_EN field. + SPI0_CACHE_FCTRL_CACHE_REQ_EN_Pos = 0x0 + // Bit mask of CACHE_REQ_EN field. + SPI0_CACHE_FCTRL_CACHE_REQ_EN_Msk = 0x1 + // Bit CACHE_REQ_EN. + SPI0_CACHE_FCTRL_CACHE_REQ_EN = 0x1 + // Position of CACHE_USR_ADDR_4BYTE field. + SPI0_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE_Pos = 0x1 + // Bit mask of CACHE_USR_ADDR_4BYTE field. + SPI0_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE_Msk = 0x2 + // Bit CACHE_USR_ADDR_4BYTE. + SPI0_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE = 0x2 + // Position of CACHE_FLASH_USR_CMD field. + SPI0_CACHE_FCTRL_CACHE_FLASH_USR_CMD_Pos = 0x2 + // Bit mask of CACHE_FLASH_USR_CMD field. + SPI0_CACHE_FCTRL_CACHE_FLASH_USR_CMD_Msk = 0x4 + // Bit CACHE_FLASH_USR_CMD. + SPI0_CACHE_FCTRL_CACHE_FLASH_USR_CMD = 0x4 + // Position of FDIN_DUAL field. + SPI0_CACHE_FCTRL_FDIN_DUAL_Pos = 0x3 + // Bit mask of FDIN_DUAL field. + SPI0_CACHE_FCTRL_FDIN_DUAL_Msk = 0x8 + // Bit FDIN_DUAL. + SPI0_CACHE_FCTRL_FDIN_DUAL = 0x8 + // Position of FDOUT_DUAL field. + SPI0_CACHE_FCTRL_FDOUT_DUAL_Pos = 0x4 + // Bit mask of FDOUT_DUAL field. + SPI0_CACHE_FCTRL_FDOUT_DUAL_Msk = 0x10 + // Bit FDOUT_DUAL. + SPI0_CACHE_FCTRL_FDOUT_DUAL = 0x10 + // Position of FADDR_DUAL field. + SPI0_CACHE_FCTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI0_CACHE_FCTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI0_CACHE_FCTRL_FADDR_DUAL = 0x20 + // Position of FDIN_QUAD field. + SPI0_CACHE_FCTRL_FDIN_QUAD_Pos = 0x6 + // Bit mask of FDIN_QUAD field. + SPI0_CACHE_FCTRL_FDIN_QUAD_Msk = 0x40 + // Bit FDIN_QUAD. + SPI0_CACHE_FCTRL_FDIN_QUAD = 0x40 + // Position of FDOUT_QUAD field. + SPI0_CACHE_FCTRL_FDOUT_QUAD_Pos = 0x7 + // Bit mask of FDOUT_QUAD field. + SPI0_CACHE_FCTRL_FDOUT_QUAD_Msk = 0x80 + // Bit FDOUT_QUAD. + SPI0_CACHE_FCTRL_FDOUT_QUAD = 0x80 + // Position of FADDR_QUAD field. + SPI0_CACHE_FCTRL_FADDR_QUAD_Pos = 0x8 + // Bit mask of FADDR_QUAD field. + SPI0_CACHE_FCTRL_FADDR_QUAD_Msk = 0x100 + // Bit FADDR_QUAD. + SPI0_CACHE_FCTRL_FADDR_QUAD = 0x100 + + // FSM: SPI0 FSM status register + // Position of CSPI_ST field. + SPI0_FSM_CSPI_ST_Pos = 0x0 + // Bit mask of CSPI_ST field. + SPI0_FSM_CSPI_ST_Msk = 0xf + // Position of EM_ST field. + SPI0_FSM_EM_ST_Pos = 0x4 + // Bit mask of EM_ST field. + SPI0_FSM_EM_ST_Msk = 0x70 + // Position of CSPI_LOCK_DELAY_TIME field. + SPI0_FSM_CSPI_LOCK_DELAY_TIME_Pos = 0x7 + // Bit mask of CSPI_LOCK_DELAY_TIME field. + SPI0_FSM_CSPI_LOCK_DELAY_TIME_Msk = 0xf80 + + // TIMING_CALI: SPI0 timing calibration register + // Position of TIMING_CLK_ENA field. + SPI0_TIMING_CALI_TIMING_CLK_ENA_Pos = 0x0 + // Bit mask of TIMING_CLK_ENA field. + SPI0_TIMING_CALI_TIMING_CLK_ENA_Msk = 0x1 + // Bit TIMING_CLK_ENA. + SPI0_TIMING_CALI_TIMING_CLK_ENA = 0x1 + // Position of TIMING_CALI field. + SPI0_TIMING_CALI_TIMING_CALI_Pos = 0x1 + // Bit mask of TIMING_CALI field. + SPI0_TIMING_CALI_TIMING_CALI_Msk = 0x2 + // Bit TIMING_CALI. + SPI0_TIMING_CALI_TIMING_CALI = 0x2 + // Position of EXTRA_DUMMY_CYCLELEN field. + SPI0_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of EXTRA_DUMMY_CYCLELEN field. + SPI0_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + + // DIN_MODE: SPI0 input delay mode control register + // Position of DIN0_MODE field. + SPI0_DIN_MODE_DIN0_MODE_Pos = 0x0 + // Bit mask of DIN0_MODE field. + SPI0_DIN_MODE_DIN0_MODE_Msk = 0x3 + // Position of DIN1_MODE field. + SPI0_DIN_MODE_DIN1_MODE_Pos = 0x2 + // Bit mask of DIN1_MODE field. + SPI0_DIN_MODE_DIN1_MODE_Msk = 0xc + // Position of DIN2_MODE field. + SPI0_DIN_MODE_DIN2_MODE_Pos = 0x4 + // Bit mask of DIN2_MODE field. + SPI0_DIN_MODE_DIN2_MODE_Msk = 0x30 + // Position of DIN3_MODE field. + SPI0_DIN_MODE_DIN3_MODE_Pos = 0x6 + // Bit mask of DIN3_MODE field. + SPI0_DIN_MODE_DIN3_MODE_Msk = 0xc0 + + // DIN_NUM: SPI0 input delay number control register + // Position of DIN0_NUM field. + SPI0_DIN_NUM_DIN0_NUM_Pos = 0x0 + // Bit mask of DIN0_NUM field. + SPI0_DIN_NUM_DIN0_NUM_Msk = 0x3 + // Position of DIN1_NUM field. + SPI0_DIN_NUM_DIN1_NUM_Pos = 0x2 + // Bit mask of DIN1_NUM field. + SPI0_DIN_NUM_DIN1_NUM_Msk = 0xc + // Position of DIN2_NUM field. + SPI0_DIN_NUM_DIN2_NUM_Pos = 0x4 + // Bit mask of DIN2_NUM field. + SPI0_DIN_NUM_DIN2_NUM_Msk = 0x30 + // Position of DIN3_NUM field. + SPI0_DIN_NUM_DIN3_NUM_Pos = 0x6 + // Bit mask of DIN3_NUM field. + SPI0_DIN_NUM_DIN3_NUM_Msk = 0xc0 + + // DOUT_MODE: SPI0 output delay mode control register + // Position of DOUT0_MODE field. + SPI0_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + SPI0_DOUT_MODE_DOUT0_MODE_Msk = 0x1 + // Bit DOUT0_MODE. + SPI0_DOUT_MODE_DOUT0_MODE = 0x1 + // Position of DOUT1_MODE field. + SPI0_DOUT_MODE_DOUT1_MODE_Pos = 0x1 + // Bit mask of DOUT1_MODE field. + SPI0_DOUT_MODE_DOUT1_MODE_Msk = 0x2 + // Bit DOUT1_MODE. + SPI0_DOUT_MODE_DOUT1_MODE = 0x2 + // Position of DOUT2_MODE field. + SPI0_DOUT_MODE_DOUT2_MODE_Pos = 0x2 + // Bit mask of DOUT2_MODE field. + SPI0_DOUT_MODE_DOUT2_MODE_Msk = 0x4 + // Bit DOUT2_MODE. + SPI0_DOUT_MODE_DOUT2_MODE = 0x4 + // Position of DOUT3_MODE field. + SPI0_DOUT_MODE_DOUT3_MODE_Pos = 0x3 + // Bit mask of DOUT3_MODE field. + SPI0_DOUT_MODE_DOUT3_MODE_Msk = 0x8 + // Bit DOUT3_MODE. + SPI0_DOUT_MODE_DOUT3_MODE = 0x8 + + // CLOCK_GATE: SPI0 clk_gate register + // Position of CLK_EN field. + SPI0_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI0_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI0_CLOCK_GATE_CLK_EN = 0x1 + + // CORE_CLK_SEL: SPI0 module clock select register + // Position of SPI01_CLK_SEL field. + SPI0_CORE_CLK_SEL_SPI01_CLK_SEL_Pos = 0x0 + // Bit mask of SPI01_CLK_SEL field. + SPI0_CORE_CLK_SEL_SPI01_CLK_SEL_Msk = 0x3 + + // DATE: Version control register + // Position of DATE field. + SPI0_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI0_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SPI1: SPI (Serial Peripheral Interface) Controller 1 +const ( + // CMD: SPI1 memory command register + // Position of SPI1_MST_ST field. + SPI1_CMD_SPI1_MST_ST_Pos = 0x0 + // Bit mask of SPI1_MST_ST field. + SPI1_CMD_SPI1_MST_ST_Msk = 0xf + // Position of MSPI_ST field. + SPI1_CMD_MSPI_ST_Pos = 0x4 + // Bit mask of MSPI_ST field. + SPI1_CMD_MSPI_ST_Msk = 0xf0 + // Position of FLASH_PE field. + SPI1_CMD_FLASH_PE_Pos = 0x11 + // Bit mask of FLASH_PE field. + SPI1_CMD_FLASH_PE_Msk = 0x20000 + // Bit FLASH_PE. + SPI1_CMD_FLASH_PE = 0x20000 + // Position of USR field. + SPI1_CMD_USR_Pos = 0x12 + // Bit mask of USR field. + SPI1_CMD_USR_Msk = 0x40000 + // Bit USR. + SPI1_CMD_USR = 0x40000 + // Position of FLASH_HPM field. + SPI1_CMD_FLASH_HPM_Pos = 0x13 + // Bit mask of FLASH_HPM field. + SPI1_CMD_FLASH_HPM_Msk = 0x80000 + // Bit FLASH_HPM. + SPI1_CMD_FLASH_HPM = 0x80000 + // Position of FLASH_RES field. + SPI1_CMD_FLASH_RES_Pos = 0x14 + // Bit mask of FLASH_RES field. + SPI1_CMD_FLASH_RES_Msk = 0x100000 + // Bit FLASH_RES. + SPI1_CMD_FLASH_RES = 0x100000 + // Position of FLASH_DP field. + SPI1_CMD_FLASH_DP_Pos = 0x15 + // Bit mask of FLASH_DP field. + SPI1_CMD_FLASH_DP_Msk = 0x200000 + // Bit FLASH_DP. + SPI1_CMD_FLASH_DP = 0x200000 + // Position of FLASH_CE field. + SPI1_CMD_FLASH_CE_Pos = 0x16 + // Bit mask of FLASH_CE field. + SPI1_CMD_FLASH_CE_Msk = 0x400000 + // Bit FLASH_CE. + SPI1_CMD_FLASH_CE = 0x400000 + // Position of FLASH_BE field. + SPI1_CMD_FLASH_BE_Pos = 0x17 + // Bit mask of FLASH_BE field. + SPI1_CMD_FLASH_BE_Msk = 0x800000 + // Bit FLASH_BE. + SPI1_CMD_FLASH_BE = 0x800000 + // Position of FLASH_SE field. + SPI1_CMD_FLASH_SE_Pos = 0x18 + // Bit mask of FLASH_SE field. + SPI1_CMD_FLASH_SE_Msk = 0x1000000 + // Bit FLASH_SE. + SPI1_CMD_FLASH_SE = 0x1000000 + // Position of FLASH_PP field. + SPI1_CMD_FLASH_PP_Pos = 0x19 + // Bit mask of FLASH_PP field. + SPI1_CMD_FLASH_PP_Msk = 0x2000000 + // Bit FLASH_PP. + SPI1_CMD_FLASH_PP = 0x2000000 + // Position of FLASH_WRSR field. + SPI1_CMD_FLASH_WRSR_Pos = 0x1a + // Bit mask of FLASH_WRSR field. + SPI1_CMD_FLASH_WRSR_Msk = 0x4000000 + // Bit FLASH_WRSR. + SPI1_CMD_FLASH_WRSR = 0x4000000 + // Position of FLASH_RDSR field. + SPI1_CMD_FLASH_RDSR_Pos = 0x1b + // Bit mask of FLASH_RDSR field. + SPI1_CMD_FLASH_RDSR_Msk = 0x8000000 + // Bit FLASH_RDSR. + SPI1_CMD_FLASH_RDSR = 0x8000000 + // Position of FLASH_RDID field. + SPI1_CMD_FLASH_RDID_Pos = 0x1c + // Bit mask of FLASH_RDID field. + SPI1_CMD_FLASH_RDID_Msk = 0x10000000 + // Bit FLASH_RDID. + SPI1_CMD_FLASH_RDID = 0x10000000 + // Position of FLASH_WRDI field. + SPI1_CMD_FLASH_WRDI_Pos = 0x1d + // Bit mask of FLASH_WRDI field. + SPI1_CMD_FLASH_WRDI_Msk = 0x20000000 + // Bit FLASH_WRDI. + SPI1_CMD_FLASH_WRDI = 0x20000000 + // Position of FLASH_WREN field. + SPI1_CMD_FLASH_WREN_Pos = 0x1e + // Bit mask of FLASH_WREN field. + SPI1_CMD_FLASH_WREN_Msk = 0x40000000 + // Bit FLASH_WREN. + SPI1_CMD_FLASH_WREN = 0x40000000 + // Position of FLASH_READ field. + SPI1_CMD_FLASH_READ_Pos = 0x1f + // Bit mask of FLASH_READ field. + SPI1_CMD_FLASH_READ_Msk = 0x80000000 + // Bit FLASH_READ. + SPI1_CMD_FLASH_READ = 0x80000000 + + // ADDR: SPI1 address register + // Position of USR_ADDR_VALUE field. + SPI1_ADDR_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of USR_ADDR_VALUE field. + SPI1_ADDR_USR_ADDR_VALUE_Msk = 0xffffffff + + // CTRL: SPI1 control register. + // Position of FDUMMY_OUT field. + SPI1_CTRL_FDUMMY_OUT_Pos = 0x3 + // Bit mask of FDUMMY_OUT field. + SPI1_CTRL_FDUMMY_OUT_Msk = 0x8 + // Bit FDUMMY_OUT. + SPI1_CTRL_FDUMMY_OUT = 0x8 + // Position of FCMD_DUAL field. + SPI1_CTRL_FCMD_DUAL_Pos = 0x7 + // Bit mask of FCMD_DUAL field. + SPI1_CTRL_FCMD_DUAL_Msk = 0x80 + // Bit FCMD_DUAL. + SPI1_CTRL_FCMD_DUAL = 0x80 + // Position of FCMD_QUAD field. + SPI1_CTRL_FCMD_QUAD_Pos = 0x8 + // Bit mask of FCMD_QUAD field. + SPI1_CTRL_FCMD_QUAD_Msk = 0x100 + // Bit FCMD_QUAD. + SPI1_CTRL_FCMD_QUAD = 0x100 + // Position of FCS_CRC_EN field. + SPI1_CTRL_FCS_CRC_EN_Pos = 0xa + // Bit mask of FCS_CRC_EN field. + SPI1_CTRL_FCS_CRC_EN_Msk = 0x400 + // Bit FCS_CRC_EN. + SPI1_CTRL_FCS_CRC_EN = 0x400 + // Position of TX_CRC_EN field. + SPI1_CTRL_TX_CRC_EN_Pos = 0xb + // Bit mask of TX_CRC_EN field. + SPI1_CTRL_TX_CRC_EN_Msk = 0x800 + // Bit TX_CRC_EN. + SPI1_CTRL_TX_CRC_EN = 0x800 + // Position of FASTRD_MODE field. + SPI1_CTRL_FASTRD_MODE_Pos = 0xd + // Bit mask of FASTRD_MODE field. + SPI1_CTRL_FASTRD_MODE_Msk = 0x2000 + // Bit FASTRD_MODE. + SPI1_CTRL_FASTRD_MODE = 0x2000 + // Position of FREAD_DUAL field. + SPI1_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI1_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI1_CTRL_FREAD_DUAL = 0x4000 + // Position of RESANDRES field. + SPI1_CTRL_RESANDRES_Pos = 0xf + // Bit mask of RESANDRES field. + SPI1_CTRL_RESANDRES_Msk = 0x8000 + // Bit RESANDRES. + SPI1_CTRL_RESANDRES = 0x8000 + // Position of Q_POL field. + SPI1_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI1_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI1_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI1_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI1_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI1_CTRL_D_POL = 0x80000 + // Position of FREAD_QUAD field. + SPI1_CTRL_FREAD_QUAD_Pos = 0x14 + // Bit mask of FREAD_QUAD field. + SPI1_CTRL_FREAD_QUAD_Msk = 0x100000 + // Bit FREAD_QUAD. + SPI1_CTRL_FREAD_QUAD = 0x100000 + // Position of WP field. + SPI1_CTRL_WP_Pos = 0x15 + // Bit mask of WP field. + SPI1_CTRL_WP_Msk = 0x200000 + // Bit WP. + SPI1_CTRL_WP = 0x200000 + // Position of WRSR_2B field. + SPI1_CTRL_WRSR_2B_Pos = 0x16 + // Bit mask of WRSR_2B field. + SPI1_CTRL_WRSR_2B_Msk = 0x400000 + // Bit WRSR_2B. + SPI1_CTRL_WRSR_2B = 0x400000 + // Position of FREAD_DIO field. + SPI1_CTRL_FREAD_DIO_Pos = 0x17 + // Bit mask of FREAD_DIO field. + SPI1_CTRL_FREAD_DIO_Msk = 0x800000 + // Bit FREAD_DIO. + SPI1_CTRL_FREAD_DIO = 0x800000 + // Position of FREAD_QIO field. + SPI1_CTRL_FREAD_QIO_Pos = 0x18 + // Bit mask of FREAD_QIO field. + SPI1_CTRL_FREAD_QIO_Msk = 0x1000000 + // Bit FREAD_QIO. + SPI1_CTRL_FREAD_QIO = 0x1000000 + + // CTRL1: SPI1 control1 register. + // Position of CLK_MODE field. + SPI1_CTRL1_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI1_CTRL1_CLK_MODE_Msk = 0x3 + // Position of CS_HOLD_DLY_RES field. + SPI1_CTRL1_CS_HOLD_DLY_RES_Pos = 0x2 + // Bit mask of CS_HOLD_DLY_RES field. + SPI1_CTRL1_CS_HOLD_DLY_RES_Msk = 0xffc + + // CTRL2: SPI1 control2 register. + // Position of SYNC_RESET field. + SPI1_CTRL2_SYNC_RESET_Pos = 0x1f + // Bit mask of SYNC_RESET field. + SPI1_CTRL2_SYNC_RESET_Msk = 0x80000000 + // Bit SYNC_RESET. + SPI1_CTRL2_SYNC_RESET = 0x80000000 + + // CLOCK: SPI1 clock division control register. + // Position of CLKCNT_L field. + SPI1_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI1_CLOCK_CLKCNT_L_Msk = 0xff + // Position of CLKCNT_H field. + SPI1_CLOCK_CLKCNT_H_Pos = 0x8 + // Bit mask of CLKCNT_H field. + SPI1_CLOCK_CLKCNT_H_Msk = 0xff00 + // Position of CLKCNT_N field. + SPI1_CLOCK_CLKCNT_N_Pos = 0x10 + // Bit mask of CLKCNT_N field. + SPI1_CLOCK_CLKCNT_N_Msk = 0xff0000 + // Position of CLK_EQU_SYSCLK field. + SPI1_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI1_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI1_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI1 user register. + // Position of CK_OUT_EDGE field. + SPI1_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI1_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI1_USER_CK_OUT_EDGE = 0x200 + // Position of FWRITE_DUAL field. + SPI1_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI1_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI1_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI1_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI1_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI1_USER_FWRITE_QUAD = 0x2000 + // Position of FWRITE_DIO field. + SPI1_USER_FWRITE_DIO_Pos = 0xe + // Bit mask of FWRITE_DIO field. + SPI1_USER_FWRITE_DIO_Msk = 0x4000 + // Bit FWRITE_DIO. + SPI1_USER_FWRITE_DIO = 0x4000 + // Position of FWRITE_QIO field. + SPI1_USER_FWRITE_QIO_Pos = 0xf + // Bit mask of FWRITE_QIO field. + SPI1_USER_FWRITE_QIO_Msk = 0x8000 + // Bit FWRITE_QIO. + SPI1_USER_FWRITE_QIO = 0x8000 + // Position of USR_MISO_HIGHPART field. + SPI1_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI1_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI1_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI1_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI1_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI1_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI1_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI1_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI1_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI1_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI1_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI1_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI1_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI1_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI1_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI1_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI1_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI1_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI1_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI1_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI1_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI1_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI1_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI1_USER_USR_COMMAND = 0x80000000 + + // USER1: SPI1 user1 register. + // Position of USR_DUMMY_CYCLELEN field. + SPI1_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI1_USER1_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of USR_ADDR_BITLEN field. + SPI1_USER1_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of USR_ADDR_BITLEN field. + SPI1_USER1_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // USER2: SPI1 user2 register. + // Position of USR_COMMAND_VALUE field. + SPI1_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI1_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of USR_COMMAND_BITLEN field. + SPI1_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI1_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MOSI_DLEN: SPI1 send data bit length control register. + // Position of USR_MOSI_DBITLEN field. + SPI1_MOSI_DLEN_USR_MOSI_DBITLEN_Pos = 0x0 + // Bit mask of USR_MOSI_DBITLEN field. + SPI1_MOSI_DLEN_USR_MOSI_DBITLEN_Msk = 0x3ff + + // MISO_DLEN: SPI1 receive data bit length control register. + // Position of USR_MISO_DBITLEN field. + SPI1_MISO_DLEN_USR_MISO_DBITLEN_Pos = 0x0 + // Bit mask of USR_MISO_DBITLEN field. + SPI1_MISO_DLEN_USR_MISO_DBITLEN_Msk = 0x3ff + + // RD_STATUS: SPI1 status register. + // Position of STATUS field. + SPI1_RD_STATUS_STATUS_Pos = 0x0 + // Bit mask of STATUS field. + SPI1_RD_STATUS_STATUS_Msk = 0xffff + // Position of WB_MODE field. + SPI1_RD_STATUS_WB_MODE_Pos = 0x10 + // Bit mask of WB_MODE field. + SPI1_RD_STATUS_WB_MODE_Msk = 0xff0000 + + // MISC: SPI1 misc register + // Position of CS0_DIS field. + SPI1_MISC_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI1_MISC_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI1_MISC_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI1_MISC_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI1_MISC_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI1_MISC_CS1_DIS = 0x2 + // Position of CK_IDLE_EDGE field. + SPI1_MISC_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of CK_IDLE_EDGE field. + SPI1_MISC_CK_IDLE_EDGE_Msk = 0x200 + // Bit CK_IDLE_EDGE. + SPI1_MISC_CK_IDLE_EDGE = 0x200 + // Position of CS_KEEP_ACTIVE field. + SPI1_MISC_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of CS_KEEP_ACTIVE field. + SPI1_MISC_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit CS_KEEP_ACTIVE. + SPI1_MISC_CS_KEEP_ACTIVE = 0x400 + + // TX_CRC: SPI1 TX CRC data register. + // Position of DATA field. + SPI1_TX_CRC_DATA_Pos = 0x0 + // Bit mask of DATA field. + SPI1_TX_CRC_DATA_Msk = 0xffffffff + + // CACHE_FCTRL: SPI1 bit mode control register. + // Position of CACHE_USR_ADDR_4BYTE field. + SPI1_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE_Pos = 0x1 + // Bit mask of CACHE_USR_ADDR_4BYTE field. + SPI1_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE_Msk = 0x2 + // Bit CACHE_USR_ADDR_4BYTE. + SPI1_CACHE_FCTRL_CACHE_USR_ADDR_4BYTE = 0x2 + // Position of FDIN_DUAL field. + SPI1_CACHE_FCTRL_FDIN_DUAL_Pos = 0x3 + // Bit mask of FDIN_DUAL field. + SPI1_CACHE_FCTRL_FDIN_DUAL_Msk = 0x8 + // Bit FDIN_DUAL. + SPI1_CACHE_FCTRL_FDIN_DUAL = 0x8 + // Position of FDOUT_DUAL field. + SPI1_CACHE_FCTRL_FDOUT_DUAL_Pos = 0x4 + // Bit mask of FDOUT_DUAL field. + SPI1_CACHE_FCTRL_FDOUT_DUAL_Msk = 0x10 + // Bit FDOUT_DUAL. + SPI1_CACHE_FCTRL_FDOUT_DUAL = 0x10 + // Position of FADDR_DUAL field. + SPI1_CACHE_FCTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI1_CACHE_FCTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI1_CACHE_FCTRL_FADDR_DUAL = 0x20 + // Position of FDIN_QUAD field. + SPI1_CACHE_FCTRL_FDIN_QUAD_Pos = 0x6 + // Bit mask of FDIN_QUAD field. + SPI1_CACHE_FCTRL_FDIN_QUAD_Msk = 0x40 + // Bit FDIN_QUAD. + SPI1_CACHE_FCTRL_FDIN_QUAD = 0x40 + // Position of FDOUT_QUAD field. + SPI1_CACHE_FCTRL_FDOUT_QUAD_Pos = 0x7 + // Bit mask of FDOUT_QUAD field. + SPI1_CACHE_FCTRL_FDOUT_QUAD_Msk = 0x80 + // Bit FDOUT_QUAD. + SPI1_CACHE_FCTRL_FDOUT_QUAD = 0x80 + // Position of FADDR_QUAD field. + SPI1_CACHE_FCTRL_FADDR_QUAD_Pos = 0x8 + // Bit mask of FADDR_QUAD field. + SPI1_CACHE_FCTRL_FADDR_QUAD_Msk = 0x100 + // Bit FADDR_QUAD. + SPI1_CACHE_FCTRL_FADDR_QUAD = 0x100 + + // W0: SPI1 memory data buffer0 + // Position of BUF0 field. + SPI1_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI1_W0_BUF0_Msk = 0xffffffff + + // W1: SPI1 memory data buffer1 + // Position of BUF1 field. + SPI1_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI1_W1_BUF1_Msk = 0xffffffff + + // W2: SPI1 memory data buffer2 + // Position of BUF2 field. + SPI1_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI1_W2_BUF2_Msk = 0xffffffff + + // W3: SPI1 memory data buffer3 + // Position of BUF3 field. + SPI1_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI1_W3_BUF3_Msk = 0xffffffff + + // W4: SPI1 memory data buffer4 + // Position of BUF4 field. + SPI1_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI1_W4_BUF4_Msk = 0xffffffff + + // W5: SPI1 memory data buffer5 + // Position of BUF5 field. + SPI1_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI1_W5_BUF5_Msk = 0xffffffff + + // W6: SPI1 memory data buffer6 + // Position of BUF6 field. + SPI1_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI1_W6_BUF6_Msk = 0xffffffff + + // W7: SPI1 memory data buffer7 + // Position of BUF7 field. + SPI1_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI1_W7_BUF7_Msk = 0xffffffff + + // W8: SPI1 memory data buffer8 + // Position of BUF8 field. + SPI1_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI1_W8_BUF8_Msk = 0xffffffff + + // W9: SPI1 memory data buffer9 + // Position of BUF9 field. + SPI1_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI1_W9_BUF9_Msk = 0xffffffff + + // W10: SPI1 memory data buffer10 + // Position of BUF10 field. + SPI1_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI1_W10_BUF10_Msk = 0xffffffff + + // W11: SPI1 memory data buffer11 + // Position of BUF11 field. + SPI1_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI1_W11_BUF11_Msk = 0xffffffff + + // W12: SPI1 memory data buffer12 + // Position of BUF12 field. + SPI1_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI1_W12_BUF12_Msk = 0xffffffff + + // W13: SPI1 memory data buffer13 + // Position of BUF13 field. + SPI1_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI1_W13_BUF13_Msk = 0xffffffff + + // W14: SPI1 memory data buffer14 + // Position of BUF14 field. + SPI1_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI1_W14_BUF14_Msk = 0xffffffff + + // W15: SPI1 memory data buffer15 + // Position of BUF15 field. + SPI1_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI1_W15_BUF15_Msk = 0xffffffff + + // FLASH_WAITI_CTRL: SPI1 wait idle control register + // Position of WAITI_DUMMY field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_Pos = 0x1 + // Bit mask of WAITI_DUMMY field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_Msk = 0x2 + // Bit WAITI_DUMMY. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY = 0x2 + // Position of WAITI_CMD field. + SPI1_FLASH_WAITI_CTRL_WAITI_CMD_Pos = 0x2 + // Bit mask of WAITI_CMD field. + SPI1_FLASH_WAITI_CTRL_WAITI_CMD_Msk = 0x3fc + // Position of WAITI_DUMMY_CYCLELEN field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN_Pos = 0xa + // Bit mask of WAITI_DUMMY_CYCLELEN field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN_Msk = 0xfc00 + + // FLASH_SUS_CTRL: SPI1 flash suspend control register + // Position of FLASH_PER field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_Pos = 0x0 + // Bit mask of FLASH_PER field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_Msk = 0x1 + // Bit FLASH_PER. + SPI1_FLASH_SUS_CTRL_FLASH_PER = 0x1 + // Position of FLASH_PES field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_Pos = 0x1 + // Bit mask of FLASH_PES field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_Msk = 0x2 + // Bit FLASH_PES. + SPI1_FLASH_SUS_CTRL_FLASH_PES = 0x2 + // Position of FLASH_PER_WAIT_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_WAIT_EN_Pos = 0x2 + // Bit mask of FLASH_PER_WAIT_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_WAIT_EN_Msk = 0x4 + // Bit FLASH_PER_WAIT_EN. + SPI1_FLASH_SUS_CTRL_FLASH_PER_WAIT_EN = 0x4 + // Position of FLASH_PES_WAIT_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_WAIT_EN_Pos = 0x3 + // Bit mask of FLASH_PES_WAIT_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_WAIT_EN_Msk = 0x8 + // Bit FLASH_PES_WAIT_EN. + SPI1_FLASH_SUS_CTRL_FLASH_PES_WAIT_EN = 0x8 + // Position of PES_PER_EN field. + SPI1_FLASH_SUS_CTRL_PES_PER_EN_Pos = 0x4 + // Bit mask of PES_PER_EN field. + SPI1_FLASH_SUS_CTRL_PES_PER_EN_Msk = 0x10 + // Bit PES_PER_EN. + SPI1_FLASH_SUS_CTRL_PES_PER_EN = 0x10 + // Position of FLASH_PES_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_EN_Pos = 0x5 + // Bit mask of FLASH_PES_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_EN_Msk = 0x20 + // Bit FLASH_PES_EN. + SPI1_FLASH_SUS_CTRL_FLASH_PES_EN = 0x20 + // Position of PESR_END_MSK field. + SPI1_FLASH_SUS_CTRL_PESR_END_MSK_Pos = 0x6 + // Bit mask of PESR_END_MSK field. + SPI1_FLASH_SUS_CTRL_PESR_END_MSK_Msk = 0x3fffc0 + // Position of RD_SUS_2B field. + SPI1_FLASH_SUS_CTRL_RD_SUS_2B_Pos = 0x16 + // Bit mask of RD_SUS_2B field. + SPI1_FLASH_SUS_CTRL_RD_SUS_2B_Msk = 0x400000 + // Bit RD_SUS_2B. + SPI1_FLASH_SUS_CTRL_RD_SUS_2B = 0x400000 + // Position of PER_END_EN field. + SPI1_FLASH_SUS_CTRL_PER_END_EN_Pos = 0x17 + // Bit mask of PER_END_EN field. + SPI1_FLASH_SUS_CTRL_PER_END_EN_Msk = 0x800000 + // Bit PER_END_EN. + SPI1_FLASH_SUS_CTRL_PER_END_EN = 0x800000 + // Position of PES_END_EN field. + SPI1_FLASH_SUS_CTRL_PES_END_EN_Pos = 0x18 + // Bit mask of PES_END_EN field. + SPI1_FLASH_SUS_CTRL_PES_END_EN_Msk = 0x1000000 + // Bit PES_END_EN. + SPI1_FLASH_SUS_CTRL_PES_END_EN = 0x1000000 + // Position of SUS_TIMEOUT_CNT field. + SPI1_FLASH_SUS_CTRL_SUS_TIMEOUT_CNT_Pos = 0x19 + // Bit mask of SUS_TIMEOUT_CNT field. + SPI1_FLASH_SUS_CTRL_SUS_TIMEOUT_CNT_Msk = 0xfe000000 + + // FLASH_SUS_CMD: SPI1 flash suspend command register + // Position of FLASH_PER_COMMAND field. + SPI1_FLASH_SUS_CMD_FLASH_PER_COMMAND_Pos = 0x0 + // Bit mask of FLASH_PER_COMMAND field. + SPI1_FLASH_SUS_CMD_FLASH_PER_COMMAND_Msk = 0xff + // Position of FLASH_PES_COMMAND field. + SPI1_FLASH_SUS_CMD_FLASH_PES_COMMAND_Pos = 0x8 + // Bit mask of FLASH_PES_COMMAND field. + SPI1_FLASH_SUS_CMD_FLASH_PES_COMMAND_Msk = 0xff00 + // Position of WAIT_PESR_COMMAND field. + SPI1_FLASH_SUS_CMD_WAIT_PESR_COMMAND_Pos = 0x10 + // Bit mask of WAIT_PESR_COMMAND field. + SPI1_FLASH_SUS_CMD_WAIT_PESR_COMMAND_Msk = 0xffff0000 + + // SUS_STATUS: SPI1 flash suspend status register + // Position of FLASH_SUS field. + SPI1_SUS_STATUS_FLASH_SUS_Pos = 0x0 + // Bit mask of FLASH_SUS field. + SPI1_SUS_STATUS_FLASH_SUS_Msk = 0x1 + // Bit FLASH_SUS. + SPI1_SUS_STATUS_FLASH_SUS = 0x1 + // Position of WAIT_PESR_CMD_2B field. + SPI1_SUS_STATUS_WAIT_PESR_CMD_2B_Pos = 0x1 + // Bit mask of WAIT_PESR_CMD_2B field. + SPI1_SUS_STATUS_WAIT_PESR_CMD_2B_Msk = 0x2 + // Bit WAIT_PESR_CMD_2B. + SPI1_SUS_STATUS_WAIT_PESR_CMD_2B = 0x2 + // Position of FLASH_HPM_DLY_128 field. + SPI1_SUS_STATUS_FLASH_HPM_DLY_128_Pos = 0x2 + // Bit mask of FLASH_HPM_DLY_128 field. + SPI1_SUS_STATUS_FLASH_HPM_DLY_128_Msk = 0x4 + // Bit FLASH_HPM_DLY_128. + SPI1_SUS_STATUS_FLASH_HPM_DLY_128 = 0x4 + // Position of FLASH_RES_DLY_128 field. + SPI1_SUS_STATUS_FLASH_RES_DLY_128_Pos = 0x3 + // Bit mask of FLASH_RES_DLY_128 field. + SPI1_SUS_STATUS_FLASH_RES_DLY_128_Msk = 0x8 + // Bit FLASH_RES_DLY_128. + SPI1_SUS_STATUS_FLASH_RES_DLY_128 = 0x8 + // Position of FLASH_DP_DLY_128 field. + SPI1_SUS_STATUS_FLASH_DP_DLY_128_Pos = 0x4 + // Bit mask of FLASH_DP_DLY_128 field. + SPI1_SUS_STATUS_FLASH_DP_DLY_128_Msk = 0x10 + // Bit FLASH_DP_DLY_128. + SPI1_SUS_STATUS_FLASH_DP_DLY_128 = 0x10 + // Position of FLASH_PER_DLY_128 field. + SPI1_SUS_STATUS_FLASH_PER_DLY_128_Pos = 0x5 + // Bit mask of FLASH_PER_DLY_128 field. + SPI1_SUS_STATUS_FLASH_PER_DLY_128_Msk = 0x20 + // Bit FLASH_PER_DLY_128. + SPI1_SUS_STATUS_FLASH_PER_DLY_128 = 0x20 + // Position of FLASH_PES_DLY_128 field. + SPI1_SUS_STATUS_FLASH_PES_DLY_128_Pos = 0x6 + // Bit mask of FLASH_PES_DLY_128 field. + SPI1_SUS_STATUS_FLASH_PES_DLY_128_Msk = 0x40 + // Bit FLASH_PES_DLY_128. + SPI1_SUS_STATUS_FLASH_PES_DLY_128 = 0x40 + // Position of SPI0_LOCK_EN field. + SPI1_SUS_STATUS_SPI0_LOCK_EN_Pos = 0x7 + // Bit mask of SPI0_LOCK_EN field. + SPI1_SUS_STATUS_SPI0_LOCK_EN_Msk = 0x80 + // Bit SPI0_LOCK_EN. + SPI1_SUS_STATUS_SPI0_LOCK_EN = 0x80 + + // TIMING_CALI: SPI1 timing control register + // Position of TIMING_CALI field. + SPI1_TIMING_CALI_TIMING_CALI_Pos = 0x1 + // Bit mask of TIMING_CALI field. + SPI1_TIMING_CALI_TIMING_CALI_Msk = 0x2 + // Bit TIMING_CALI. + SPI1_TIMING_CALI_TIMING_CALI = 0x2 + // Position of EXTRA_DUMMY_CYCLELEN field. + SPI1_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of EXTRA_DUMMY_CYCLELEN field. + SPI1_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + + // INT_ENA: SPI1 interrupt enable register + // Position of PER_END_INT_ENA field. + SPI1_INT_ENA_PER_END_INT_ENA_Pos = 0x0 + // Bit mask of PER_END_INT_ENA field. + SPI1_INT_ENA_PER_END_INT_ENA_Msk = 0x1 + // Bit PER_END_INT_ENA. + SPI1_INT_ENA_PER_END_INT_ENA = 0x1 + // Position of PES_END_INT_ENA field. + SPI1_INT_ENA_PES_END_INT_ENA_Pos = 0x1 + // Bit mask of PES_END_INT_ENA field. + SPI1_INT_ENA_PES_END_INT_ENA_Msk = 0x2 + // Bit PES_END_INT_ENA. + SPI1_INT_ENA_PES_END_INT_ENA = 0x2 + // Position of WPE_END_INT_ENA field. + SPI1_INT_ENA_WPE_END_INT_ENA_Pos = 0x2 + // Bit mask of WPE_END_INT_ENA field. + SPI1_INT_ENA_WPE_END_INT_ENA_Msk = 0x4 + // Bit WPE_END_INT_ENA. + SPI1_INT_ENA_WPE_END_INT_ENA = 0x4 + // Position of SLV_ST_END_INT_ENA field. + SPI1_INT_ENA_SLV_ST_END_INT_ENA_Pos = 0x3 + // Bit mask of SLV_ST_END_INT_ENA field. + SPI1_INT_ENA_SLV_ST_END_INT_ENA_Msk = 0x8 + // Bit SLV_ST_END_INT_ENA. + SPI1_INT_ENA_SLV_ST_END_INT_ENA = 0x8 + // Position of MST_ST_END_INT_ENA field. + SPI1_INT_ENA_MST_ST_END_INT_ENA_Pos = 0x4 + // Bit mask of MST_ST_END_INT_ENA field. + SPI1_INT_ENA_MST_ST_END_INT_ENA_Msk = 0x10 + // Bit MST_ST_END_INT_ENA. + SPI1_INT_ENA_MST_ST_END_INT_ENA = 0x10 + + // INT_CLR: SPI1 interrupt clear register + // Position of PER_END_INT_CLR field. + SPI1_INT_CLR_PER_END_INT_CLR_Pos = 0x0 + // Bit mask of PER_END_INT_CLR field. + SPI1_INT_CLR_PER_END_INT_CLR_Msk = 0x1 + // Bit PER_END_INT_CLR. + SPI1_INT_CLR_PER_END_INT_CLR = 0x1 + // Position of PES_END_INT_CLR field. + SPI1_INT_CLR_PES_END_INT_CLR_Pos = 0x1 + // Bit mask of PES_END_INT_CLR field. + SPI1_INT_CLR_PES_END_INT_CLR_Msk = 0x2 + // Bit PES_END_INT_CLR. + SPI1_INT_CLR_PES_END_INT_CLR = 0x2 + // Position of WPE_END_INT_CLR field. + SPI1_INT_CLR_WPE_END_INT_CLR_Pos = 0x2 + // Bit mask of WPE_END_INT_CLR field. + SPI1_INT_CLR_WPE_END_INT_CLR_Msk = 0x4 + // Bit WPE_END_INT_CLR. + SPI1_INT_CLR_WPE_END_INT_CLR = 0x4 + // Position of SLV_ST_END_INT_CLR field. + SPI1_INT_CLR_SLV_ST_END_INT_CLR_Pos = 0x3 + // Bit mask of SLV_ST_END_INT_CLR field. + SPI1_INT_CLR_SLV_ST_END_INT_CLR_Msk = 0x8 + // Bit SLV_ST_END_INT_CLR. + SPI1_INT_CLR_SLV_ST_END_INT_CLR = 0x8 + // Position of MST_ST_END_INT_CLR field. + SPI1_INT_CLR_MST_ST_END_INT_CLR_Pos = 0x4 + // Bit mask of MST_ST_END_INT_CLR field. + SPI1_INT_CLR_MST_ST_END_INT_CLR_Msk = 0x10 + // Bit MST_ST_END_INT_CLR. + SPI1_INT_CLR_MST_ST_END_INT_CLR = 0x10 + + // INT_RAW: SPI1 interrupt raw register + // Position of PER_END_INT_RAW field. + SPI1_INT_RAW_PER_END_INT_RAW_Pos = 0x0 + // Bit mask of PER_END_INT_RAW field. + SPI1_INT_RAW_PER_END_INT_RAW_Msk = 0x1 + // Bit PER_END_INT_RAW. + SPI1_INT_RAW_PER_END_INT_RAW = 0x1 + // Position of PES_END_INT_RAW field. + SPI1_INT_RAW_PES_END_INT_RAW_Pos = 0x1 + // Bit mask of PES_END_INT_RAW field. + SPI1_INT_RAW_PES_END_INT_RAW_Msk = 0x2 + // Bit PES_END_INT_RAW. + SPI1_INT_RAW_PES_END_INT_RAW = 0x2 + // Position of WPE_END_INT_RAW field. + SPI1_INT_RAW_WPE_END_INT_RAW_Pos = 0x2 + // Bit mask of WPE_END_INT_RAW field. + SPI1_INT_RAW_WPE_END_INT_RAW_Msk = 0x4 + // Bit WPE_END_INT_RAW. + SPI1_INT_RAW_WPE_END_INT_RAW = 0x4 + // Position of SLV_ST_END_INT_RAW field. + SPI1_INT_RAW_SLV_ST_END_INT_RAW_Pos = 0x3 + // Bit mask of SLV_ST_END_INT_RAW field. + SPI1_INT_RAW_SLV_ST_END_INT_RAW_Msk = 0x8 + // Bit SLV_ST_END_INT_RAW. + SPI1_INT_RAW_SLV_ST_END_INT_RAW = 0x8 + // Position of MST_ST_END_INT_RAW field. + SPI1_INT_RAW_MST_ST_END_INT_RAW_Pos = 0x4 + // Bit mask of MST_ST_END_INT_RAW field. + SPI1_INT_RAW_MST_ST_END_INT_RAW_Msk = 0x10 + // Bit MST_ST_END_INT_RAW. + SPI1_INT_RAW_MST_ST_END_INT_RAW = 0x10 + + // INT_ST: SPI1 interrupt status register + // Position of PER_END_INT_ST field. + SPI1_INT_ST_PER_END_INT_ST_Pos = 0x0 + // Bit mask of PER_END_INT_ST field. + SPI1_INT_ST_PER_END_INT_ST_Msk = 0x1 + // Bit PER_END_INT_ST. + SPI1_INT_ST_PER_END_INT_ST = 0x1 + // Position of PES_END_INT_ST field. + SPI1_INT_ST_PES_END_INT_ST_Pos = 0x1 + // Bit mask of PES_END_INT_ST field. + SPI1_INT_ST_PES_END_INT_ST_Msk = 0x2 + // Bit PES_END_INT_ST. + SPI1_INT_ST_PES_END_INT_ST = 0x2 + // Position of WPE_END_INT_ST field. + SPI1_INT_ST_WPE_END_INT_ST_Pos = 0x2 + // Bit mask of WPE_END_INT_ST field. + SPI1_INT_ST_WPE_END_INT_ST_Msk = 0x4 + // Bit WPE_END_INT_ST. + SPI1_INT_ST_WPE_END_INT_ST = 0x4 + // Position of SLV_ST_END_INT_ST field. + SPI1_INT_ST_SLV_ST_END_INT_ST_Pos = 0x3 + // Bit mask of SLV_ST_END_INT_ST field. + SPI1_INT_ST_SLV_ST_END_INT_ST_Msk = 0x8 + // Bit SLV_ST_END_INT_ST. + SPI1_INT_ST_SLV_ST_END_INT_ST = 0x8 + // Position of MST_ST_END_INT_ST field. + SPI1_INT_ST_MST_ST_END_INT_ST_Pos = 0x4 + // Bit mask of MST_ST_END_INT_ST field. + SPI1_INT_ST_MST_ST_END_INT_ST_Msk = 0x10 + // Bit MST_ST_END_INT_ST. + SPI1_INT_ST_MST_ST_END_INT_ST = 0x10 + + // CLOCK_GATE: SPI1 clk_gate register + // Position of CLK_EN field. + SPI1_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI1_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI1_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version control register + // Position of DATE field. + SPI1_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI1_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SPI2: SPI (Serial Peripheral Interface) Controller 2 +const ( + // CMD: Command control register + // Position of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Pos = 0x0 + // Bit mask of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Msk = 0x3ffff + // Position of UPDATE field. + SPI2_CMD_UPDATE_Pos = 0x17 + // Bit mask of UPDATE field. + SPI2_CMD_UPDATE_Msk = 0x800000 + // Bit UPDATE. + SPI2_CMD_UPDATE = 0x800000 + // Position of USR field. + SPI2_CMD_USR_Pos = 0x18 + // Bit mask of USR field. + SPI2_CMD_USR_Msk = 0x1000000 + // Bit USR. + SPI2_CMD_USR = 0x1000000 + + // ADDR: Address value register + // Position of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Msk = 0xffffffff + + // CTRL: SPI control register + // Position of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Pos = 0x3 + // Bit mask of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Msk = 0x8 + // Bit DUMMY_OUT. + SPI2_CTRL_DUMMY_OUT = 0x8 + // Position of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI2_CTRL_FADDR_DUAL = 0x20 + // Position of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Pos = 0x6 + // Bit mask of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Msk = 0x40 + // Bit FADDR_QUAD. + SPI2_CTRL_FADDR_QUAD = 0x40 + // Position of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Pos = 0x8 + // Bit mask of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Msk = 0x100 + // Bit FCMD_DUAL. + SPI2_CTRL_FCMD_DUAL = 0x100 + // Position of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Pos = 0x9 + // Bit mask of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Msk = 0x200 + // Bit FCMD_QUAD. + SPI2_CTRL_FCMD_QUAD = 0x200 + // Position of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI2_CTRL_FREAD_DUAL = 0x4000 + // Position of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Pos = 0xf + // Bit mask of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Msk = 0x8000 + // Bit FREAD_QUAD. + SPI2_CTRL_FREAD_QUAD = 0x8000 + // Position of Q_POL field. + SPI2_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI2_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI2_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI2_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI2_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI2_CTRL_D_POL = 0x80000 + // Position of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Pos = 0x14 + // Bit mask of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Msk = 0x100000 + // Bit HOLD_POL. + SPI2_CTRL_HOLD_POL = 0x100000 + // Position of WP_POL field. + SPI2_CTRL_WP_POL_Pos = 0x15 + // Bit mask of WP_POL field. + SPI2_CTRL_WP_POL_Msk = 0x200000 + // Bit WP_POL. + SPI2_CTRL_WP_POL = 0x200000 + // Position of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Pos = 0x19 + // Bit mask of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Msk = 0x2000000 + // Bit RD_BIT_ORDER. + SPI2_CTRL_RD_BIT_ORDER = 0x2000000 + // Position of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Pos = 0x1a + // Bit mask of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Msk = 0x4000000 + // Bit WR_BIT_ORDER. + SPI2_CTRL_WR_BIT_ORDER = 0x4000000 + + // CLOCK: SPI clock control register + // Position of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Msk = 0x3f + // Position of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Pos = 0x6 + // Bit mask of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Msk = 0xfc0 + // Position of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Pos = 0xc + // Bit mask of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Msk = 0x3f000 + // Position of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Pos = 0x12 + // Bit mask of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Msk = 0x3c0000 + // Position of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI2_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI USER control register + // Position of DOUTDIN field. + SPI2_USER_DOUTDIN_Pos = 0x0 + // Bit mask of DOUTDIN field. + SPI2_USER_DOUTDIN_Msk = 0x1 + // Bit DOUTDIN. + SPI2_USER_DOUTDIN = 0x1 + // Position of QPI_MODE field. + SPI2_USER_QPI_MODE_Pos = 0x3 + // Bit mask of QPI_MODE field. + SPI2_USER_QPI_MODE_Msk = 0x8 + // Bit QPI_MODE. + SPI2_USER_QPI_MODE = 0x8 + // Position of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Pos = 0x5 + // Bit mask of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Msk = 0x20 + // Bit TSCK_I_EDGE. + SPI2_USER_TSCK_I_EDGE = 0x20 + // Position of CS_HOLD field. + SPI2_USER_CS_HOLD_Pos = 0x6 + // Bit mask of CS_HOLD field. + SPI2_USER_CS_HOLD_Msk = 0x40 + // Bit CS_HOLD. + SPI2_USER_CS_HOLD = 0x40 + // Position of CS_SETUP field. + SPI2_USER_CS_SETUP_Pos = 0x7 + // Bit mask of CS_SETUP field. + SPI2_USER_CS_SETUP_Msk = 0x80 + // Bit CS_SETUP. + SPI2_USER_CS_SETUP = 0x80 + // Position of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Pos = 0x8 + // Bit mask of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Msk = 0x100 + // Bit RSCK_I_EDGE. + SPI2_USER_RSCK_I_EDGE = 0x100 + // Position of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI2_USER_CK_OUT_EDGE = 0x200 + // Position of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI2_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI2_USER_FWRITE_QUAD = 0x2000 + // Position of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Pos = 0xf + // Bit mask of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Msk = 0x8000 + // Bit USR_CONF_NXT. + SPI2_USER_USR_CONF_NXT = 0x8000 + // Position of SIO field. + SPI2_USER_SIO_Pos = 0x11 + // Bit mask of SIO field. + SPI2_USER_SIO_Msk = 0x20000 + // Bit SIO. + SPI2_USER_SIO = 0x20000 + // Position of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI2_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI2_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI2_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI2_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI2_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI2_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI2_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI2_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI2_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI2_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI2_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI2_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI2_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI2_USER_USR_COMMAND = 0x80000000 + + // USER1: SPI USER control register 1 + // Position of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Msk = 0xff + // Position of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Pos = 0x10 + // Bit mask of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Msk = 0x10000 + // Bit MST_WFULL_ERR_END_EN. + SPI2_USER1_MST_WFULL_ERR_END_EN = 0x10000 + // Position of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Pos = 0x11 + // Bit mask of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Msk = 0x3e0000 + // Position of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Pos = 0x16 + // Bit mask of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Msk = 0x7c00000 + // Position of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Pos = 0x1b + // Bit mask of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Msk = 0xf8000000 + + // USER2: SPI USER control register 2 + // Position of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Pos = 0x1b + // Bit mask of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Msk = 0x8000000 + // Bit MST_REMPTY_ERR_END_EN. + SPI2_USER2_MST_REMPTY_ERR_END_EN = 0x8000000 + // Position of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MS_DLEN: SPI data bit length control register + // Position of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Pos = 0x0 + // Bit mask of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Msk = 0x3ffff + + // MISC: SPI misc register + // Position of CS0_DIS field. + SPI2_MISC_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI2_MISC_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI2_MISC_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI2_MISC_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI2_MISC_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI2_MISC_CS1_DIS = 0x2 + // Position of CS2_DIS field. + SPI2_MISC_CS2_DIS_Pos = 0x2 + // Bit mask of CS2_DIS field. + SPI2_MISC_CS2_DIS_Msk = 0x4 + // Bit CS2_DIS. + SPI2_MISC_CS2_DIS = 0x4 + // Position of CS3_DIS field. + SPI2_MISC_CS3_DIS_Pos = 0x3 + // Bit mask of CS3_DIS field. + SPI2_MISC_CS3_DIS_Msk = 0x8 + // Bit CS3_DIS. + SPI2_MISC_CS3_DIS = 0x8 + // Position of CS4_DIS field. + SPI2_MISC_CS4_DIS_Pos = 0x4 + // Bit mask of CS4_DIS field. + SPI2_MISC_CS4_DIS_Msk = 0x10 + // Bit CS4_DIS. + SPI2_MISC_CS4_DIS = 0x10 + // Position of CS5_DIS field. + SPI2_MISC_CS5_DIS_Pos = 0x5 + // Bit mask of CS5_DIS field. + SPI2_MISC_CS5_DIS_Msk = 0x20 + // Bit CS5_DIS. + SPI2_MISC_CS5_DIS = 0x20 + // Position of CK_DIS field. + SPI2_MISC_CK_DIS_Pos = 0x6 + // Bit mask of CK_DIS field. + SPI2_MISC_CK_DIS_Msk = 0x40 + // Bit CK_DIS. + SPI2_MISC_CK_DIS = 0x40 + // Position of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Pos = 0x7 + // Bit mask of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Msk = 0x1f80 + // Position of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Pos = 0x17 + // Bit mask of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Msk = 0x800000 + // Bit SLAVE_CS_POL. + SPI2_MISC_SLAVE_CS_POL = 0x800000 + // Position of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Pos = 0x1d + // Bit mask of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Msk = 0x20000000 + // Bit CK_IDLE_EDGE. + SPI2_MISC_CK_IDLE_EDGE = 0x20000000 + // Position of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Pos = 0x1e + // Bit mask of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Msk = 0x40000000 + // Bit CS_KEEP_ACTIVE. + SPI2_MISC_CS_KEEP_ACTIVE = 0x40000000 + // Position of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Pos = 0x1f + // Bit mask of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Msk = 0x80000000 + // Bit QUAD_DIN_PIN_SWAP. + SPI2_MISC_QUAD_DIN_PIN_SWAP = 0x80000000 + + // DIN_MODE: SPI input delay mode configuration + // Position of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Pos = 0x0 + // Bit mask of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Msk = 0x3 + // Position of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Pos = 0x2 + // Bit mask of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Msk = 0xc + // Position of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Pos = 0x4 + // Bit mask of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Msk = 0x30 + // Position of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Pos = 0x6 + // Bit mask of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Msk = 0xc0 + // Position of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Pos = 0x10 + // Bit mask of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Msk = 0x10000 + // Bit TIMING_HCLK_ACTIVE. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE = 0x10000 + + // DIN_NUM: SPI input delay number configuration + // Position of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Pos = 0x0 + // Bit mask of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Msk = 0x3 + // Position of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Pos = 0x2 + // Bit mask of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Msk = 0xc + // Position of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Pos = 0x4 + // Bit mask of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Msk = 0x30 + // Position of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Pos = 0x6 + // Bit mask of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Msk = 0xc0 + + // DOUT_MODE: SPI output delay mode configuration + // Position of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Msk = 0x1 + // Bit DOUT0_MODE. + SPI2_DOUT_MODE_DOUT0_MODE = 0x1 + // Position of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Pos = 0x1 + // Bit mask of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Msk = 0x2 + // Bit DOUT1_MODE. + SPI2_DOUT_MODE_DOUT1_MODE = 0x2 + // Position of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Pos = 0x2 + // Bit mask of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Msk = 0x4 + // Bit DOUT2_MODE. + SPI2_DOUT_MODE_DOUT2_MODE = 0x4 + // Position of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Pos = 0x3 + // Bit mask of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Msk = 0x8 + // Bit DOUT3_MODE. + SPI2_DOUT_MODE_DOUT3_MODE = 0x8 + + // DMA_CONF: SPI DMA control register + // Position of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Pos = 0x12 + // Bit mask of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Msk = 0x40000 + // Bit DMA_SLV_SEG_TRANS_EN. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN = 0x40000 + // Position of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Pos = 0x13 + // Bit mask of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Msk = 0x80000 + // Bit SLV_RX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN = 0x80000 + // Position of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Pos = 0x14 + // Bit mask of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Msk = 0x100000 + // Bit SLV_TX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN = 0x100000 + // Position of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Pos = 0x15 + // Bit mask of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Msk = 0x200000 + // Bit RX_EOF_EN. + SPI2_DMA_CONF_RX_EOF_EN = 0x200000 + // Position of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Pos = 0x1b + // Bit mask of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Msk = 0x8000000 + // Bit DMA_RX_ENA. + SPI2_DMA_CONF_DMA_RX_ENA = 0x8000000 + // Position of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Pos = 0x1c + // Bit mask of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Msk = 0x10000000 + // Bit DMA_TX_ENA. + SPI2_DMA_CONF_DMA_TX_ENA = 0x10000000 + // Position of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Pos = 0x1d + // Bit mask of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Msk = 0x20000000 + // Bit RX_AFIFO_RST. + SPI2_DMA_CONF_RX_AFIFO_RST = 0x20000000 + // Position of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Pos = 0x1e + // Bit mask of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Msk = 0x40000000 + // Bit BUF_AFIFO_RST. + SPI2_DMA_CONF_BUF_AFIFO_RST = 0x40000000 + // Position of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Pos = 0x1f + // Bit mask of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Msk = 0x80000000 + // Bit DMA_AFIFO_RST. + SPI2_DMA_CONF_DMA_AFIFO_RST = 0x80000000 + + // DMA_INT_ENA: SPI DMA interrupt enable register + // Position of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA = 0x2 + // Position of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA = 0x4 + // Position of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA = 0x8 + // Position of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Msk = 0x10 + // Bit SLV_CMD7_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA = 0x10 + // Position of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Msk = 0x20 + // Bit SLV_CMD8_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA = 0x20 + // Position of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Msk = 0x40 + // Bit SLV_CMD9_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA = 0x40 + // Position of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Msk = 0x80 + // Bit SLV_CMDA_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA = 0x800 + // Position of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Msk = 0x1000 + // Bit TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA = 0x8000 + // Position of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA = 0x40000 + // Position of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Pos = 0x13 + // Bit mask of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Msk = 0x80000 + // Bit APP2_INT_ENA. + SPI2_DMA_INT_ENA_APP2_INT_ENA = 0x80000 + // Position of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Pos = 0x14 + // Bit mask of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Msk = 0x100000 + // Bit APP1_INT_ENA. + SPI2_DMA_INT_ENA_APP1_INT_ENA = 0x100000 + + // DMA_INT_CLR: SPI DMA interrupt clear register + // Position of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR = 0x2 + // Position of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Msk = 0x4 + // Bit SLV_EX_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR = 0x4 + // Position of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Msk = 0x8 + // Bit SLV_EN_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR = 0x8 + // Position of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Msk = 0x10 + // Bit SLV_CMD7_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR = 0x10 + // Position of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Msk = 0x20 + // Bit SLV_CMD8_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR = 0x20 + // Position of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Msk = 0x40 + // Bit SLV_CMD9_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR = 0x40 + // Position of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Msk = 0x80 + // Bit SLV_CMDA_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR = 0x80 + // Position of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR = 0x100 + // Position of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR = 0x200 + // Position of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR = 0x400 + // Position of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR = 0x800 + // Position of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Pos = 0xc + // Bit mask of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Msk = 0x1000 + // Bit TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR = 0x2000 + // Position of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR = 0x8000 + // Position of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR = 0x40000 + // Position of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Pos = 0x13 + // Bit mask of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Msk = 0x80000 + // Bit APP2_INT_CLR. + SPI2_DMA_INT_CLR_APP2_INT_CLR = 0x80000 + // Position of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Pos = 0x14 + // Bit mask of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Msk = 0x100000 + // Bit APP1_INT_CLR. + SPI2_DMA_INT_CLR_APP1_INT_CLR = 0x100000 + + // DMA_INT_RAW: SPI DMA interrupt raw register + // Position of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW = 0x2 + // Position of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Msk = 0x4 + // Bit SLV_EX_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW = 0x4 + // Position of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Msk = 0x8 + // Bit SLV_EN_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW = 0x8 + // Position of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Msk = 0x10 + // Bit SLV_CMD7_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW = 0x10 + // Position of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Msk = 0x20 + // Bit SLV_CMD8_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW = 0x20 + // Position of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Msk = 0x40 + // Bit SLV_CMD9_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW = 0x40 + // Position of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Msk = 0x80 + // Bit SLV_CMDA_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW = 0x80 + // Position of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW = 0x100 + // Position of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW = 0x200 + // Position of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW = 0x400 + // Position of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW = 0x800 + // Position of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Pos = 0xc + // Bit mask of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Msk = 0x1000 + // Bit TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW = 0x2000 + // Position of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW = 0x8000 + // Position of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW = 0x40000 + // Position of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Pos = 0x13 + // Bit mask of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Msk = 0x80000 + // Bit APP2_INT_RAW. + SPI2_DMA_INT_RAW_APP2_INT_RAW = 0x80000 + // Position of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Pos = 0x14 + // Bit mask of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Msk = 0x100000 + // Bit APP1_INT_RAW. + SPI2_DMA_INT_RAW_APP1_INT_RAW = 0x100000 + + // DMA_INT_ST: SPI DMA interrupt status register + // Position of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST = 0x2 + // Position of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST = 0x4 + // Position of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST = 0x8 + // Position of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Msk = 0x10 + // Bit SLV_CMD7_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST = 0x10 + // Position of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Msk = 0x20 + // Bit SLV_CMD8_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST = 0x20 + // Position of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Msk = 0x40 + // Bit SLV_CMD9_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST = 0x40 + // Position of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Msk = 0x80 + // Bit SLV_CMDA_INT_ST. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST = 0x800 + // Position of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Msk = 0x1000 + // Bit TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ST. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST = 0x8000 + // Position of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST = 0x40000 + // Position of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Pos = 0x13 + // Bit mask of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Msk = 0x80000 + // Bit APP2_INT_ST. + SPI2_DMA_INT_ST_APP2_INT_ST = 0x80000 + // Position of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Pos = 0x14 + // Bit mask of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Msk = 0x100000 + // Bit APP1_INT_ST. + SPI2_DMA_INT_ST_APP1_INT_ST = 0x100000 + + // W0: SPI CPU-controlled buffer0 + // Position of BUF0 field. + SPI2_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI2_W0_BUF0_Msk = 0xffffffff + + // W1: SPI CPU-controlled buffer1 + // Position of BUF1 field. + SPI2_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI2_W1_BUF1_Msk = 0xffffffff + + // W2: SPI CPU-controlled buffer2 + // Position of BUF2 field. + SPI2_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI2_W2_BUF2_Msk = 0xffffffff + + // W3: SPI CPU-controlled buffer3 + // Position of BUF3 field. + SPI2_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI2_W3_BUF3_Msk = 0xffffffff + + // W4: SPI CPU-controlled buffer4 + // Position of BUF4 field. + SPI2_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI2_W4_BUF4_Msk = 0xffffffff + + // W5: SPI CPU-controlled buffer5 + // Position of BUF5 field. + SPI2_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI2_W5_BUF5_Msk = 0xffffffff + + // W6: SPI CPU-controlled buffer6 + // Position of BUF6 field. + SPI2_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI2_W6_BUF6_Msk = 0xffffffff + + // W7: SPI CPU-controlled buffer7 + // Position of BUF7 field. + SPI2_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI2_W7_BUF7_Msk = 0xffffffff + + // W8: SPI CPU-controlled buffer8 + // Position of BUF8 field. + SPI2_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI2_W8_BUF8_Msk = 0xffffffff + + // W9: SPI CPU-controlled buffer9 + // Position of BUF9 field. + SPI2_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI2_W9_BUF9_Msk = 0xffffffff + + // W10: SPI CPU-controlled buffer10 + // Position of BUF10 field. + SPI2_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI2_W10_BUF10_Msk = 0xffffffff + + // W11: SPI CPU-controlled buffer11 + // Position of BUF11 field. + SPI2_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI2_W11_BUF11_Msk = 0xffffffff + + // W12: SPI CPU-controlled buffer12 + // Position of BUF12 field. + SPI2_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI2_W12_BUF12_Msk = 0xffffffff + + // W13: SPI CPU-controlled buffer13 + // Position of BUF13 field. + SPI2_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI2_W13_BUF13_Msk = 0xffffffff + + // W14: SPI CPU-controlled buffer14 + // Position of BUF14 field. + SPI2_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI2_W14_BUF14_Msk = 0xffffffff + + // W15: SPI CPU-controlled buffer15 + // Position of BUF15 field. + SPI2_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI2_W15_BUF15_Msk = 0xffffffff + + // SLAVE: SPI slave control register + // Position of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Msk = 0x3 + // Position of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Pos = 0x2 + // Bit mask of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Msk = 0x4 + // Bit CLK_MODE_13. + SPI2_SLAVE_CLK_MODE_13 = 0x4 + // Position of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Pos = 0x3 + // Bit mask of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Msk = 0x8 + // Bit RSCK_DATA_OUT. + SPI2_SLAVE_RSCK_DATA_OUT = 0x8 + // Position of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Pos = 0x8 + // Bit mask of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Msk = 0x100 + // Bit SLV_RDDMA_BITLEN_EN. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN = 0x100 + // Position of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Pos = 0x9 + // Bit mask of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Msk = 0x200 + // Bit SLV_WRDMA_BITLEN_EN. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN = 0x200 + // Position of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Pos = 0xa + // Bit mask of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Msk = 0x400 + // Bit SLV_RDBUF_BITLEN_EN. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN = 0x400 + // Position of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Pos = 0xb + // Bit mask of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Msk = 0x800 + // Bit SLV_WRBUF_BITLEN_EN. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN = 0x800 + // Position of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Pos = 0x16 + // Bit mask of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Msk = 0x3c00000 + // Position of MODE field. + SPI2_SLAVE_MODE_Pos = 0x1a + // Bit mask of MODE field. + SPI2_SLAVE_MODE_Msk = 0x4000000 + // Bit MODE. + SPI2_SLAVE_MODE = 0x4000000 + // Position of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Pos = 0x1b + // Bit mask of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Msk = 0x8000000 + // Bit SOFT_RESET. + SPI2_SLAVE_SOFT_RESET = 0x8000000 + // Position of USR_CONF field. + SPI2_SLAVE_USR_CONF_Pos = 0x1c + // Bit mask of USR_CONF field. + SPI2_SLAVE_USR_CONF_Msk = 0x10000000 + // Bit USR_CONF. + SPI2_SLAVE_USR_CONF = 0x10000000 + + // SLAVE1: SPI slave control register 1 + // Position of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Pos = 0x0 + // Bit mask of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Msk = 0x3ffff + // Position of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Pos = 0x12 + // Bit mask of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Msk = 0x3fc0000 + // Position of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Pos = 0x1a + // Bit mask of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Msk = 0xfc000000 + + // CLK_GATE: SPI module clock and register clock control + // Position of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI2_CLK_GATE_CLK_EN = 0x1 + // Position of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Pos = 0x1 + // Bit mask of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Msk = 0x2 + // Bit MST_CLK_ACTIVE. + SPI2_CLK_GATE_MST_CLK_ACTIVE = 0x2 + // Position of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Pos = 0x2 + // Bit mask of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Msk = 0x4 + // Bit MST_CLK_SEL. + SPI2_CLK_GATE_MST_CLK_SEL = 0x4 + + // DATE: Version control + // Position of DATE field. + SPI2_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI2_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SYSTEM: System Configuration Registers +const ( + // CPU_PERI_CLK_EN: cpu_peripheral clock gating register + // Position of CLK_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG_Pos = 0x6 + // Bit mask of CLK_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG_Msk = 0x40 + // Bit CLK_EN_ASSIST_DEBUG. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG = 0x40 + // Position of CLK_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO_Pos = 0x7 + // Bit mask of CLK_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO_Msk = 0x80 + // Bit CLK_EN_DEDICATED_GPIO. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO = 0x80 + + // CPU_PERI_RST_EN: cpu_peripheral reset register + // Position of RST_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG_Pos = 0x6 + // Bit mask of RST_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG_Msk = 0x40 + // Bit RST_EN_ASSIST_DEBUG. + SYSTEM_CPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG = 0x40 + // Position of RST_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO_Pos = 0x7 + // Bit mask of RST_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO_Msk = 0x80 + // Bit RST_EN_DEDICATED_GPIO. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO = 0x80 + + // CPU_PER_CONF: cpu clock config register + // Position of CPUPERIOD_SEL field. + SYSTEM_CPU_PER_CONF_CPUPERIOD_SEL_Pos = 0x0 + // Bit mask of CPUPERIOD_SEL field. + SYSTEM_CPU_PER_CONF_CPUPERIOD_SEL_Msk = 0x3 + // Position of PLL_FREQ_SEL field. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL_Pos = 0x2 + // Bit mask of PLL_FREQ_SEL field. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL_Msk = 0x4 + // Bit PLL_FREQ_SEL. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL = 0x4 + // Position of CPU_WAIT_MODE_FORCE_ON field. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON_Pos = 0x3 + // Bit mask of CPU_WAIT_MODE_FORCE_ON field. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON_Msk = 0x8 + // Bit CPU_WAIT_MODE_FORCE_ON. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON = 0x8 + // Position of CPU_WAITI_DELAY_NUM field. + SYSTEM_CPU_PER_CONF_CPU_WAITI_DELAY_NUM_Pos = 0x4 + // Bit mask of CPU_WAITI_DELAY_NUM field. + SYSTEM_CPU_PER_CONF_CPU_WAITI_DELAY_NUM_Msk = 0xf0 + + // MEM_PD_MASK: memory power down mask register + // Position of LSLP_MEM_PD_MASK field. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK_Pos = 0x0 + // Bit mask of LSLP_MEM_PD_MASK field. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK_Msk = 0x1 + // Bit LSLP_MEM_PD_MASK. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK = 0x1 + + // PERIP_CLK_EN0: peripheral clock gating register + // Position of TIMERS_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERS_CLK_EN_Pos = 0x0 + // Bit mask of TIMERS_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERS_CLK_EN_Msk = 0x1 + // Bit TIMERS_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERS_CLK_EN = 0x1 + // Position of SPI01_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN_Pos = 0x1 + // Bit mask of SPI01_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN_Msk = 0x2 + // Bit SPI01_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN = 0x2 + // Position of UART_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN_Pos = 0x2 + // Bit mask of UART_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN_Msk = 0x4 + // Bit UART_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN = 0x4 + // Position of WDG_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_WDG_CLK_EN_Pos = 0x3 + // Bit mask of WDG_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_WDG_CLK_EN_Msk = 0x8 + // Bit WDG_CLK_EN. + SYSTEM_PERIP_CLK_EN0_WDG_CLK_EN = 0x8 + // Position of I2S0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S0_CLK_EN_Pos = 0x4 + // Bit mask of I2S0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S0_CLK_EN_Msk = 0x10 + // Bit I2S0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2S0_CLK_EN = 0x10 + // Position of UART1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN_Pos = 0x5 + // Bit mask of UART1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN_Msk = 0x20 + // Bit UART1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN = 0x20 + // Position of SPI2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN_Pos = 0x6 + // Bit mask of SPI2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN_Msk = 0x40 + // Bit SPI2_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN = 0x40 + // Position of I2C_EXT0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN_Pos = 0x7 + // Bit mask of I2C_EXT0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN_Msk = 0x80 + // Bit I2C_EXT0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN = 0x80 + // Position of UHCI0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI0_CLK_EN_Pos = 0x8 + // Bit mask of UHCI0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI0_CLK_EN_Msk = 0x100 + // Bit UHCI0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UHCI0_CLK_EN = 0x100 + // Position of RMT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_RMT_CLK_EN_Pos = 0x9 + // Bit mask of RMT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_RMT_CLK_EN_Msk = 0x200 + // Bit RMT_CLK_EN. + SYSTEM_PERIP_CLK_EN0_RMT_CLK_EN = 0x200 + // Position of PCNT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PCNT_CLK_EN_Pos = 0xa + // Bit mask of PCNT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PCNT_CLK_EN_Msk = 0x400 + // Bit PCNT_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PCNT_CLK_EN = 0x400 + // Position of LEDC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN_Pos = 0xb + // Bit mask of LEDC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN_Msk = 0x800 + // Bit LEDC_CLK_EN. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN = 0x800 + // Position of UHCI1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI1_CLK_EN_Pos = 0xc + // Bit mask of UHCI1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI1_CLK_EN_Msk = 0x1000 + // Bit UHCI1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UHCI1_CLK_EN = 0x1000 + // Position of TIMERGROUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN_Pos = 0xd + // Bit mask of TIMERGROUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN_Msk = 0x2000 + // Bit TIMERGROUP_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN = 0x2000 + // Position of EFUSE_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_EFUSE_CLK_EN_Pos = 0xe + // Bit mask of EFUSE_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_EFUSE_CLK_EN_Msk = 0x4000 + // Bit EFUSE_CLK_EN. + SYSTEM_PERIP_CLK_EN0_EFUSE_CLK_EN = 0x4000 + // Position of TIMERGROUP1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP1_CLK_EN_Pos = 0xf + // Bit mask of TIMERGROUP1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP1_CLK_EN_Msk = 0x8000 + // Bit TIMERGROUP1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP1_CLK_EN = 0x8000 + // Position of SPI3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_CLK_EN_Pos = 0x10 + // Bit mask of SPI3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_CLK_EN_Msk = 0x10000 + // Bit SPI3_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI3_CLK_EN = 0x10000 + // Position of PWM0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM0_CLK_EN_Pos = 0x11 + // Bit mask of PWM0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM0_CLK_EN_Msk = 0x20000 + // Bit PWM0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM0_CLK_EN = 0x20000 + // Position of EXT1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_EXT1_CLK_EN_Pos = 0x12 + // Bit mask of EXT1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_EXT1_CLK_EN_Msk = 0x40000 + // Bit EXT1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_EXT1_CLK_EN = 0x40000 + // Position of TWAI_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TWAI_CLK_EN_Pos = 0x13 + // Bit mask of TWAI_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TWAI_CLK_EN_Msk = 0x80000 + // Bit TWAI_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TWAI_CLK_EN = 0x80000 + // Position of PWM1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM1_CLK_EN_Pos = 0x14 + // Bit mask of PWM1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM1_CLK_EN_Msk = 0x100000 + // Bit PWM1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM1_CLK_EN = 0x100000 + // Position of I2S1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S1_CLK_EN_Pos = 0x15 + // Bit mask of I2S1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S1_CLK_EN_Msk = 0x200000 + // Bit I2S1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2S1_CLK_EN = 0x200000 + // Position of SPI2_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_DMA_CLK_EN_Pos = 0x16 + // Bit mask of SPI2_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_DMA_CLK_EN_Msk = 0x400000 + // Bit SPI2_DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI2_DMA_CLK_EN = 0x400000 + // Position of USB_DEVICE_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_USB_DEVICE_CLK_EN_Pos = 0x17 + // Bit mask of USB_DEVICE_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_USB_DEVICE_CLK_EN_Msk = 0x800000 + // Bit USB_DEVICE_CLK_EN. + SYSTEM_PERIP_CLK_EN0_USB_DEVICE_CLK_EN = 0x800000 + // Position of UART_MEM_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN_Pos = 0x18 + // Bit mask of UART_MEM_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN_Msk = 0x1000000 + // Bit UART_MEM_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN = 0x1000000 + // Position of PWM2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM2_CLK_EN_Pos = 0x19 + // Bit mask of PWM2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM2_CLK_EN_Msk = 0x2000000 + // Bit PWM2_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM2_CLK_EN = 0x2000000 + // Position of PWM3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM3_CLK_EN_Pos = 0x1a + // Bit mask of PWM3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM3_CLK_EN_Msk = 0x4000000 + // Bit PWM3_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM3_CLK_EN = 0x4000000 + // Position of SPI3_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_DMA_CLK_EN_Pos = 0x1b + // Bit mask of SPI3_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_DMA_CLK_EN_Msk = 0x8000000 + // Bit SPI3_DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI3_DMA_CLK_EN = 0x8000000 + // Position of APB_SARADC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN_Pos = 0x1c + // Bit mask of APB_SARADC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN_Msk = 0x10000000 + // Bit APB_SARADC_CLK_EN. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN = 0x10000000 + // Position of SYSTIMER_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN_Pos = 0x1d + // Bit mask of SYSTIMER_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN_Msk = 0x20000000 + // Bit SYSTIMER_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN = 0x20000000 + // Position of ADC2_ARB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN_Pos = 0x1e + // Bit mask of ADC2_ARB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN_Msk = 0x40000000 + // Bit ADC2_ARB_CLK_EN. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN = 0x40000000 + // Position of SPI4_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI4_CLK_EN_Pos = 0x1f + // Bit mask of SPI4_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI4_CLK_EN_Msk = 0x80000000 + // Bit SPI4_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI4_CLK_EN = 0x80000000 + + // PERIP_CLK_EN1: peripheral clock gating register + // Position of CRYPTO_AES_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_AES_CLK_EN_Pos = 0x1 + // Bit mask of CRYPTO_AES_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_AES_CLK_EN_Msk = 0x2 + // Bit CRYPTO_AES_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_AES_CLK_EN = 0x2 + // Position of CRYPTO_SHA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN_Pos = 0x2 + // Bit mask of CRYPTO_SHA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN_Msk = 0x4 + // Bit CRYPTO_SHA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN = 0x4 + // Position of CRYPTO_RSA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_RSA_CLK_EN_Pos = 0x3 + // Bit mask of CRYPTO_RSA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_RSA_CLK_EN_Msk = 0x8 + // Bit CRYPTO_RSA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_RSA_CLK_EN = 0x8 + // Position of CRYPTO_DS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DS_CLK_EN_Pos = 0x4 + // Bit mask of CRYPTO_DS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DS_CLK_EN_Msk = 0x10 + // Bit CRYPTO_DS_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DS_CLK_EN = 0x10 + // Position of CRYPTO_HMAC_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN_Pos = 0x5 + // Bit mask of CRYPTO_HMAC_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN_Msk = 0x20 + // Bit CRYPTO_HMAC_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN = 0x20 + // Position of DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_DMA_CLK_EN_Pos = 0x6 + // Bit mask of DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_DMA_CLK_EN_Msk = 0x40 + // Bit DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_DMA_CLK_EN = 0x40 + // Position of SDIO_HOST_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_SDIO_HOST_CLK_EN_Pos = 0x7 + // Bit mask of SDIO_HOST_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_SDIO_HOST_CLK_EN_Msk = 0x80 + // Bit SDIO_HOST_CLK_EN. + SYSTEM_PERIP_CLK_EN1_SDIO_HOST_CLK_EN = 0x80 + // Position of LCD_CAM_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_LCD_CAM_CLK_EN_Pos = 0x8 + // Bit mask of LCD_CAM_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_LCD_CAM_CLK_EN_Msk = 0x100 + // Bit LCD_CAM_CLK_EN. + SYSTEM_PERIP_CLK_EN1_LCD_CAM_CLK_EN = 0x100 + // Position of UART2_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_UART2_CLK_EN_Pos = 0x9 + // Bit mask of UART2_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_UART2_CLK_EN_Msk = 0x200 + // Bit UART2_CLK_EN. + SYSTEM_PERIP_CLK_EN1_UART2_CLK_EN = 0x200 + // Position of TSENS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_TSENS_CLK_EN_Pos = 0xa + // Bit mask of TSENS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_TSENS_CLK_EN_Msk = 0x400 + // Bit TSENS_CLK_EN. + SYSTEM_PERIP_CLK_EN1_TSENS_CLK_EN = 0x400 + + // PERIP_RST_EN0: reserved + // Position of TIMERS_RST field. + SYSTEM_PERIP_RST_EN0_TIMERS_RST_Pos = 0x0 + // Bit mask of TIMERS_RST field. + SYSTEM_PERIP_RST_EN0_TIMERS_RST_Msk = 0x1 + // Bit TIMERS_RST. + SYSTEM_PERIP_RST_EN0_TIMERS_RST = 0x1 + // Position of SPI01_RST field. + SYSTEM_PERIP_RST_EN0_SPI01_RST_Pos = 0x1 + // Bit mask of SPI01_RST field. + SYSTEM_PERIP_RST_EN0_SPI01_RST_Msk = 0x2 + // Bit SPI01_RST. + SYSTEM_PERIP_RST_EN0_SPI01_RST = 0x2 + // Position of UART_RST field. + SYSTEM_PERIP_RST_EN0_UART_RST_Pos = 0x2 + // Bit mask of UART_RST field. + SYSTEM_PERIP_RST_EN0_UART_RST_Msk = 0x4 + // Bit UART_RST. + SYSTEM_PERIP_RST_EN0_UART_RST = 0x4 + // Position of WDG_RST field. + SYSTEM_PERIP_RST_EN0_WDG_RST_Pos = 0x3 + // Bit mask of WDG_RST field. + SYSTEM_PERIP_RST_EN0_WDG_RST_Msk = 0x8 + // Bit WDG_RST. + SYSTEM_PERIP_RST_EN0_WDG_RST = 0x8 + // Position of I2S0_RST field. + SYSTEM_PERIP_RST_EN0_I2S0_RST_Pos = 0x4 + // Bit mask of I2S0_RST field. + SYSTEM_PERIP_RST_EN0_I2S0_RST_Msk = 0x10 + // Bit I2S0_RST. + SYSTEM_PERIP_RST_EN0_I2S0_RST = 0x10 + // Position of UART1_RST field. + SYSTEM_PERIP_RST_EN0_UART1_RST_Pos = 0x5 + // Bit mask of UART1_RST field. + SYSTEM_PERIP_RST_EN0_UART1_RST_Msk = 0x20 + // Bit UART1_RST. + SYSTEM_PERIP_RST_EN0_UART1_RST = 0x20 + // Position of SPI2_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_RST_Pos = 0x6 + // Bit mask of SPI2_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_RST_Msk = 0x40 + // Bit SPI2_RST. + SYSTEM_PERIP_RST_EN0_SPI2_RST = 0x40 + // Position of I2C_EXT0_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST_Pos = 0x7 + // Bit mask of I2C_EXT0_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST_Msk = 0x80 + // Bit I2C_EXT0_RST. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST = 0x80 + // Position of UHCI0_RST field. + SYSTEM_PERIP_RST_EN0_UHCI0_RST_Pos = 0x8 + // Bit mask of UHCI0_RST field. + SYSTEM_PERIP_RST_EN0_UHCI0_RST_Msk = 0x100 + // Bit UHCI0_RST. + SYSTEM_PERIP_RST_EN0_UHCI0_RST = 0x100 + // Position of RMT_RST field. + SYSTEM_PERIP_RST_EN0_RMT_RST_Pos = 0x9 + // Bit mask of RMT_RST field. + SYSTEM_PERIP_RST_EN0_RMT_RST_Msk = 0x200 + // Bit RMT_RST. + SYSTEM_PERIP_RST_EN0_RMT_RST = 0x200 + // Position of PCNT_RST field. + SYSTEM_PERIP_RST_EN0_PCNT_RST_Pos = 0xa + // Bit mask of PCNT_RST field. + SYSTEM_PERIP_RST_EN0_PCNT_RST_Msk = 0x400 + // Bit PCNT_RST. + SYSTEM_PERIP_RST_EN0_PCNT_RST = 0x400 + // Position of LEDC_RST field. + SYSTEM_PERIP_RST_EN0_LEDC_RST_Pos = 0xb + // Bit mask of LEDC_RST field. + SYSTEM_PERIP_RST_EN0_LEDC_RST_Msk = 0x800 + // Bit LEDC_RST. + SYSTEM_PERIP_RST_EN0_LEDC_RST = 0x800 + // Position of UHCI1_RST field. + SYSTEM_PERIP_RST_EN0_UHCI1_RST_Pos = 0xc + // Bit mask of UHCI1_RST field. + SYSTEM_PERIP_RST_EN0_UHCI1_RST_Msk = 0x1000 + // Bit UHCI1_RST. + SYSTEM_PERIP_RST_EN0_UHCI1_RST = 0x1000 + // Position of TIMERGROUP_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST_Pos = 0xd + // Bit mask of TIMERGROUP_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST_Msk = 0x2000 + // Bit TIMERGROUP_RST. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST = 0x2000 + // Position of EFUSE_RST field. + SYSTEM_PERIP_RST_EN0_EFUSE_RST_Pos = 0xe + // Bit mask of EFUSE_RST field. + SYSTEM_PERIP_RST_EN0_EFUSE_RST_Msk = 0x4000 + // Bit EFUSE_RST. + SYSTEM_PERIP_RST_EN0_EFUSE_RST = 0x4000 + // Position of TIMERGROUP1_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP1_RST_Pos = 0xf + // Bit mask of TIMERGROUP1_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP1_RST_Msk = 0x8000 + // Bit TIMERGROUP1_RST. + SYSTEM_PERIP_RST_EN0_TIMERGROUP1_RST = 0x8000 + // Position of SPI3_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_RST_Pos = 0x10 + // Bit mask of SPI3_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_RST_Msk = 0x10000 + // Bit SPI3_RST. + SYSTEM_PERIP_RST_EN0_SPI3_RST = 0x10000 + // Position of PWM0_RST field. + SYSTEM_PERIP_RST_EN0_PWM0_RST_Pos = 0x11 + // Bit mask of PWM0_RST field. + SYSTEM_PERIP_RST_EN0_PWM0_RST_Msk = 0x20000 + // Bit PWM0_RST. + SYSTEM_PERIP_RST_EN0_PWM0_RST = 0x20000 + // Position of EXT1_RST field. + SYSTEM_PERIP_RST_EN0_EXT1_RST_Pos = 0x12 + // Bit mask of EXT1_RST field. + SYSTEM_PERIP_RST_EN0_EXT1_RST_Msk = 0x40000 + // Bit EXT1_RST. + SYSTEM_PERIP_RST_EN0_EXT1_RST = 0x40000 + // Position of TWAI_RST field. + SYSTEM_PERIP_RST_EN0_TWAI_RST_Pos = 0x13 + // Bit mask of TWAI_RST field. + SYSTEM_PERIP_RST_EN0_TWAI_RST_Msk = 0x80000 + // Bit TWAI_RST. + SYSTEM_PERIP_RST_EN0_TWAI_RST = 0x80000 + // Position of PWM1_RST field. + SYSTEM_PERIP_RST_EN0_PWM1_RST_Pos = 0x14 + // Bit mask of PWM1_RST field. + SYSTEM_PERIP_RST_EN0_PWM1_RST_Msk = 0x100000 + // Bit PWM1_RST. + SYSTEM_PERIP_RST_EN0_PWM1_RST = 0x100000 + // Position of I2S1_RST field. + SYSTEM_PERIP_RST_EN0_I2S1_RST_Pos = 0x15 + // Bit mask of I2S1_RST field. + SYSTEM_PERIP_RST_EN0_I2S1_RST_Msk = 0x200000 + // Bit I2S1_RST. + SYSTEM_PERIP_RST_EN0_I2S1_RST = 0x200000 + // Position of SPI2_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_DMA_RST_Pos = 0x16 + // Bit mask of SPI2_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_DMA_RST_Msk = 0x400000 + // Bit SPI2_DMA_RST. + SYSTEM_PERIP_RST_EN0_SPI2_DMA_RST = 0x400000 + // Position of USB_DEVICE_RST field. + SYSTEM_PERIP_RST_EN0_USB_DEVICE_RST_Pos = 0x17 + // Bit mask of USB_DEVICE_RST field. + SYSTEM_PERIP_RST_EN0_USB_DEVICE_RST_Msk = 0x800000 + // Bit USB_DEVICE_RST. + SYSTEM_PERIP_RST_EN0_USB_DEVICE_RST = 0x800000 + // Position of UART_MEM_RST field. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST_Pos = 0x18 + // Bit mask of UART_MEM_RST field. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST_Msk = 0x1000000 + // Bit UART_MEM_RST. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST = 0x1000000 + // Position of PWM2_RST field. + SYSTEM_PERIP_RST_EN0_PWM2_RST_Pos = 0x19 + // Bit mask of PWM2_RST field. + SYSTEM_PERIP_RST_EN0_PWM2_RST_Msk = 0x2000000 + // Bit PWM2_RST. + SYSTEM_PERIP_RST_EN0_PWM2_RST = 0x2000000 + // Position of PWM3_RST field. + SYSTEM_PERIP_RST_EN0_PWM3_RST_Pos = 0x1a + // Bit mask of PWM3_RST field. + SYSTEM_PERIP_RST_EN0_PWM3_RST_Msk = 0x4000000 + // Bit PWM3_RST. + SYSTEM_PERIP_RST_EN0_PWM3_RST = 0x4000000 + // Position of SPI3_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_DMA_RST_Pos = 0x1b + // Bit mask of SPI3_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_DMA_RST_Msk = 0x8000000 + // Bit SPI3_DMA_RST. + SYSTEM_PERIP_RST_EN0_SPI3_DMA_RST = 0x8000000 + // Position of APB_SARADC_RST field. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST_Pos = 0x1c + // Bit mask of APB_SARADC_RST field. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST_Msk = 0x10000000 + // Bit APB_SARADC_RST. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST = 0x10000000 + // Position of SYSTIMER_RST field. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST_Pos = 0x1d + // Bit mask of SYSTIMER_RST field. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST_Msk = 0x20000000 + // Bit SYSTIMER_RST. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST = 0x20000000 + // Position of ADC2_ARB_RST field. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST_Pos = 0x1e + // Bit mask of ADC2_ARB_RST field. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST_Msk = 0x40000000 + // Bit ADC2_ARB_RST. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST = 0x40000000 + // Position of SPI4_RST field. + SYSTEM_PERIP_RST_EN0_SPI4_RST_Pos = 0x1f + // Bit mask of SPI4_RST field. + SYSTEM_PERIP_RST_EN0_SPI4_RST_Msk = 0x80000000 + // Bit SPI4_RST. + SYSTEM_PERIP_RST_EN0_SPI4_RST = 0x80000000 + + // PERIP_RST_EN1: peripheral reset register + // Position of CRYPTO_AES_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_AES_RST_Pos = 0x1 + // Bit mask of CRYPTO_AES_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_AES_RST_Msk = 0x2 + // Bit CRYPTO_AES_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_AES_RST = 0x2 + // Position of CRYPTO_SHA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST_Pos = 0x2 + // Bit mask of CRYPTO_SHA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST_Msk = 0x4 + // Bit CRYPTO_SHA_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST = 0x4 + // Position of CRYPTO_RSA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_RSA_RST_Pos = 0x3 + // Bit mask of CRYPTO_RSA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_RSA_RST_Msk = 0x8 + // Bit CRYPTO_RSA_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_RSA_RST = 0x8 + // Position of CRYPTO_DS_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_DS_RST_Pos = 0x4 + // Bit mask of CRYPTO_DS_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_DS_RST_Msk = 0x10 + // Bit CRYPTO_DS_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_DS_RST = 0x10 + // Position of CRYPTO_HMAC_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_HMAC_RST_Pos = 0x5 + // Bit mask of CRYPTO_HMAC_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_HMAC_RST_Msk = 0x20 + // Bit CRYPTO_HMAC_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_HMAC_RST = 0x20 + // Position of DMA_RST field. + SYSTEM_PERIP_RST_EN1_DMA_RST_Pos = 0x6 + // Bit mask of DMA_RST field. + SYSTEM_PERIP_RST_EN1_DMA_RST_Msk = 0x40 + // Bit DMA_RST. + SYSTEM_PERIP_RST_EN1_DMA_RST = 0x40 + // Position of SDIO_HOST_RST field. + SYSTEM_PERIP_RST_EN1_SDIO_HOST_RST_Pos = 0x7 + // Bit mask of SDIO_HOST_RST field. + SYSTEM_PERIP_RST_EN1_SDIO_HOST_RST_Msk = 0x80 + // Bit SDIO_HOST_RST. + SYSTEM_PERIP_RST_EN1_SDIO_HOST_RST = 0x80 + // Position of LCD_CAM_RST field. + SYSTEM_PERIP_RST_EN1_LCD_CAM_RST_Pos = 0x8 + // Bit mask of LCD_CAM_RST field. + SYSTEM_PERIP_RST_EN1_LCD_CAM_RST_Msk = 0x100 + // Bit LCD_CAM_RST. + SYSTEM_PERIP_RST_EN1_LCD_CAM_RST = 0x100 + // Position of UART2_RST field. + SYSTEM_PERIP_RST_EN1_UART2_RST_Pos = 0x9 + // Bit mask of UART2_RST field. + SYSTEM_PERIP_RST_EN1_UART2_RST_Msk = 0x200 + // Bit UART2_RST. + SYSTEM_PERIP_RST_EN1_UART2_RST = 0x200 + // Position of TSENS_RST field. + SYSTEM_PERIP_RST_EN1_TSENS_RST_Pos = 0xa + // Bit mask of TSENS_RST field. + SYSTEM_PERIP_RST_EN1_TSENS_RST_Msk = 0x400 + // Bit TSENS_RST. + SYSTEM_PERIP_RST_EN1_TSENS_RST = 0x400 + + // BT_LPCK_DIV_INT: clock config register + // Position of BT_LPCK_DIV_NUM field. + SYSTEM_BT_LPCK_DIV_INT_BT_LPCK_DIV_NUM_Pos = 0x0 + // Bit mask of BT_LPCK_DIV_NUM field. + SYSTEM_BT_LPCK_DIV_INT_BT_LPCK_DIV_NUM_Msk = 0xfff + + // BT_LPCK_DIV_FRAC: clock config register + // Position of BT_LPCK_DIV_B field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_B_Pos = 0x0 + // Bit mask of BT_LPCK_DIV_B field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_B_Msk = 0xfff + // Position of BT_LPCK_DIV_A field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_A_Pos = 0xc + // Bit mask of BT_LPCK_DIV_A field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_A_Msk = 0xfff000 + // Position of LPCLK_SEL_RTC_SLOW field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Pos = 0x18 + // Bit mask of LPCLK_SEL_RTC_SLOW field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Msk = 0x1000000 + // Bit LPCLK_SEL_RTC_SLOW. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW = 0x1000000 + // Position of LPCLK_SEL_8M field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Pos = 0x19 + // Bit mask of LPCLK_SEL_8M field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Msk = 0x2000000 + // Bit LPCLK_SEL_8M. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M = 0x2000000 + // Position of LPCLK_SEL_XTAL field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Pos = 0x1a + // Bit mask of LPCLK_SEL_XTAL field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Msk = 0x4000000 + // Bit LPCLK_SEL_XTAL. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL = 0x4000000 + // Position of LPCLK_SEL_XTAL32K field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Pos = 0x1b + // Bit mask of LPCLK_SEL_XTAL32K field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Msk = 0x8000000 + // Bit LPCLK_SEL_XTAL32K. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K = 0x8000000 + // Position of LPCLK_RTC_EN field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN_Pos = 0x1c + // Bit mask of LPCLK_RTC_EN field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN_Msk = 0x10000000 + // Bit LPCLK_RTC_EN. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN = 0x10000000 + + // CPU_INTR_FROM_CPU_0: interrupt generate register + // Position of CPU_INTR_FROM_CPU_0 field. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0 field. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_0. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0 = 0x1 + + // CPU_INTR_FROM_CPU_1: interrupt generate register + // Position of CPU_INTR_FROM_CPU_1 field. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1 field. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_1. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1 = 0x1 + + // CPU_INTR_FROM_CPU_2: interrupt generate register + // Position of CPU_INTR_FROM_CPU_2 field. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2 field. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_2. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2 = 0x1 + + // CPU_INTR_FROM_CPU_3: interrupt generate register + // Position of CPU_INTR_FROM_CPU_3 field. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3 field. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_3. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3 = 0x1 + + // RSA_PD_CTRL: rsa memory power control register + // Position of RSA_MEM_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD_Pos = 0x0 + // Bit mask of RSA_MEM_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD_Msk = 0x1 + // Bit RSA_MEM_PD. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD = 0x1 + // Position of RSA_MEM_FORCE_PU field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of RSA_MEM_FORCE_PU field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Msk = 0x2 + // Bit RSA_MEM_FORCE_PU. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU = 0x2 + // Position of RSA_MEM_FORCE_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of RSA_MEM_FORCE_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Msk = 0x4 + // Bit RSA_MEM_FORCE_PD. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD = 0x4 + + // EDMA_CTRL: EDMA clock and reset register + // Position of EDMA_CLK_ON field. + SYSTEM_EDMA_CTRL_EDMA_CLK_ON_Pos = 0x0 + // Bit mask of EDMA_CLK_ON field. + SYSTEM_EDMA_CTRL_EDMA_CLK_ON_Msk = 0x1 + // Bit EDMA_CLK_ON. + SYSTEM_EDMA_CTRL_EDMA_CLK_ON = 0x1 + // Position of EDMA_RESET field. + SYSTEM_EDMA_CTRL_EDMA_RESET_Pos = 0x1 + // Bit mask of EDMA_RESET field. + SYSTEM_EDMA_CTRL_EDMA_RESET_Msk = 0x2 + // Bit EDMA_RESET. + SYSTEM_EDMA_CTRL_EDMA_RESET = 0x2 + + // CACHE_CONTROL: cache control register + // Position of ICACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_ICACHE_CLK_ON_Pos = 0x0 + // Bit mask of ICACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_ICACHE_CLK_ON_Msk = 0x1 + // Bit ICACHE_CLK_ON. + SYSTEM_CACHE_CONTROL_ICACHE_CLK_ON = 0x1 + // Position of ICACHE_RESET field. + SYSTEM_CACHE_CONTROL_ICACHE_RESET_Pos = 0x1 + // Bit mask of ICACHE_RESET field. + SYSTEM_CACHE_CONTROL_ICACHE_RESET_Msk = 0x2 + // Bit ICACHE_RESET. + SYSTEM_CACHE_CONTROL_ICACHE_RESET = 0x2 + // Position of DCACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_DCACHE_CLK_ON_Pos = 0x2 + // Bit mask of DCACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_DCACHE_CLK_ON_Msk = 0x4 + // Bit DCACHE_CLK_ON. + SYSTEM_CACHE_CONTROL_DCACHE_CLK_ON = 0x4 + // Position of DCACHE_RESET field. + SYSTEM_CACHE_CONTROL_DCACHE_RESET_Pos = 0x3 + // Bit mask of DCACHE_RESET field. + SYSTEM_CACHE_CONTROL_DCACHE_RESET_Msk = 0x8 + // Bit DCACHE_RESET. + SYSTEM_CACHE_CONTROL_DCACHE_RESET = 0x8 + + // EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG + // Position of ENABLE_SPI_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Pos = 0x0 + // Bit mask of ENABLE_SPI_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Msk = 0x1 + // Bit ENABLE_SPI_MANUAL_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT = 0x1 + // Position of ENABLE_DOWNLOAD_DB_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Pos = 0x1 + // Bit mask of ENABLE_DOWNLOAD_DB_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Msk = 0x2 + // Bit ENABLE_DOWNLOAD_DB_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT = 0x2 + // Position of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Pos = 0x2 + // Bit mask of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Msk = 0x4 + // Bit ENABLE_DOWNLOAD_G0CB_DECRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT = 0x4 + // Position of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x3 + // Bit mask of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x8 + // Bit ENABLE_DOWNLOAD_MANUAL_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT = 0x8 + + // RTC_FASTMEM_CONFIG: fast memory config register + // Position of RTC_MEM_CRC_START field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START_Pos = 0x8 + // Bit mask of RTC_MEM_CRC_START field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START_Msk = 0x100 + // Bit RTC_MEM_CRC_START. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START = 0x100 + // Position of RTC_MEM_CRC_ADDR field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR_Pos = 0x9 + // Bit mask of RTC_MEM_CRC_ADDR field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR_Msk = 0xffe00 + // Position of RTC_MEM_CRC_LEN field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN_Pos = 0x14 + // Bit mask of RTC_MEM_CRC_LEN field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN_Msk = 0x7ff00000 + // Position of RTC_MEM_CRC_FINISH field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH_Pos = 0x1f + // Bit mask of RTC_MEM_CRC_FINISH field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH_Msk = 0x80000000 + // Bit RTC_MEM_CRC_FINISH. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH = 0x80000000 + + // RTC_FASTMEM_CRC: reserved + // Position of RTC_MEM_CRC_RES field. + SYSTEM_RTC_FASTMEM_CRC_RTC_MEM_CRC_RES_Pos = 0x0 + // Bit mask of RTC_MEM_CRC_RES field. + SYSTEM_RTC_FASTMEM_CRC_RTC_MEM_CRC_RES_Msk = 0xffffffff + + // REDUNDANT_ECO_CTRL: eco register + // Position of REDUNDANT_ECO_DRIVE field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE_Pos = 0x0 + // Bit mask of REDUNDANT_ECO_DRIVE field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE_Msk = 0x1 + // Bit REDUNDANT_ECO_DRIVE. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE = 0x1 + // Position of REDUNDANT_ECO_RESULT field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT_Pos = 0x1 + // Bit mask of REDUNDANT_ECO_RESULT field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT_Msk = 0x2 + // Bit REDUNDANT_ECO_RESULT. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT = 0x2 + + // CLOCK_GATE: clock gating register + // Position of CLK_EN field. + SYSTEM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SYSTEM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SYSTEM_CLOCK_GATE_CLK_EN = 0x1 + + // SYSCLK_CONF: system clock config register + // Position of PRE_DIV_CNT field. + SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_Pos = 0x0 + // Bit mask of PRE_DIV_CNT field. + SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_Msk = 0x3ff + // Position of SOC_CLK_SEL field. + SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_Pos = 0xa + // Bit mask of SOC_CLK_SEL field. + SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_Msk = 0xc00 + // Position of CLK_XTAL_FREQ field. + SYSTEM_SYSCLK_CONF_CLK_XTAL_FREQ_Pos = 0xc + // Bit mask of CLK_XTAL_FREQ field. + SYSTEM_SYSCLK_CONF_CLK_XTAL_FREQ_Msk = 0x7f000 + // Position of CLK_DIV_EN field. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN_Pos = 0x13 + // Bit mask of CLK_DIV_EN field. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN_Msk = 0x80000 + // Bit CLK_DIV_EN. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN = 0x80000 + + // MEM_PVT: mem pvt register + // Position of MEM_PATH_LEN field. + SYSTEM_MEM_PVT_MEM_PATH_LEN_Pos = 0x0 + // Bit mask of MEM_PATH_LEN field. + SYSTEM_MEM_PVT_MEM_PATH_LEN_Msk = 0xf + // Position of MEM_ERR_CNT_CLR field. + SYSTEM_MEM_PVT_MEM_ERR_CNT_CLR_Pos = 0x4 + // Bit mask of MEM_ERR_CNT_CLR field. + SYSTEM_MEM_PVT_MEM_ERR_CNT_CLR_Msk = 0x10 + // Bit MEM_ERR_CNT_CLR. + SYSTEM_MEM_PVT_MEM_ERR_CNT_CLR = 0x10 + // Position of MONITOR_EN field. + SYSTEM_MEM_PVT_MONITOR_EN_Pos = 0x5 + // Bit mask of MONITOR_EN field. + SYSTEM_MEM_PVT_MONITOR_EN_Msk = 0x20 + // Bit MONITOR_EN. + SYSTEM_MEM_PVT_MONITOR_EN = 0x20 + // Position of MEM_TIMING_ERR_CNT field. + SYSTEM_MEM_PVT_MEM_TIMING_ERR_CNT_Pos = 0x6 + // Bit mask of MEM_TIMING_ERR_CNT field. + SYSTEM_MEM_PVT_MEM_TIMING_ERR_CNT_Msk = 0x3fffc0 + // Position of MEM_VT_SEL field. + SYSTEM_MEM_PVT_MEM_VT_SEL_Pos = 0x16 + // Bit mask of MEM_VT_SEL field. + SYSTEM_MEM_PVT_MEM_VT_SEL_Msk = 0xc00000 + + // COMB_PVT_LVT_CONF: mem pvt register + // Position of COMB_PATH_LEN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT_Pos = 0x0 + // Bit mask of COMB_PATH_LEN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT_Msk = 0x1f + // Position of COMB_ERR_CNT_CLR_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT_Pos = 0x5 + // Bit mask of COMB_ERR_CNT_CLR_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT_Msk = 0x20 + // Bit COMB_ERR_CNT_CLR_LVT. + SYSTEM_COMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT = 0x20 + // Position of COMB_PVT_MONITOR_EN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT_Pos = 0x6 + // Bit mask of COMB_PVT_MONITOR_EN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT_Msk = 0x40 + // Bit COMB_PVT_MONITOR_EN_LVT. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT = 0x40 + + // COMB_PVT_NVT_CONF: mem pvt register + // Position of COMB_PATH_LEN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT_Pos = 0x0 + // Bit mask of COMB_PATH_LEN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT_Msk = 0x1f + // Position of COMB_ERR_CNT_CLR_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT_Pos = 0x5 + // Bit mask of COMB_ERR_CNT_CLR_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT_Msk = 0x20 + // Bit COMB_ERR_CNT_CLR_NVT. + SYSTEM_COMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT = 0x20 + // Position of COMB_PVT_MONITOR_EN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT_Pos = 0x6 + // Bit mask of COMB_PVT_MONITOR_EN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT_Msk = 0x40 + // Bit COMB_PVT_MONITOR_EN_NVT. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT = 0x40 + + // COMB_PVT_HVT_CONF: mem pvt register + // Position of COMB_PATH_LEN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT_Pos = 0x0 + // Bit mask of COMB_PATH_LEN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT_Msk = 0x1f + // Position of COMB_ERR_CNT_CLR_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT_Pos = 0x5 + // Bit mask of COMB_ERR_CNT_CLR_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT_Msk = 0x20 + // Bit COMB_ERR_CNT_CLR_HVT. + SYSTEM_COMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT = 0x20 + // Position of COMB_PVT_MONITOR_EN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT_Pos = 0x6 + // Bit mask of COMB_PVT_MONITOR_EN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT_Msk = 0x40 + // Bit COMB_PVT_MONITOR_EN_HVT. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT = 0x40 + + // COMB_PVT_ERR_LVT_SITE0: mem pvt register + // Position of COMB_TIMING_ERR_CNT_LVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE0: mem pvt register + // Position of COMB_TIMING_ERR_CNT_NVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE0: mem pvt register + // Position of COMB_TIMING_ERR_CNT_HVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0_Msk = 0xffff + + // COMB_PVT_ERR_LVT_SITE1: mem pvt register + // Position of COMB_TIMING_ERR_CNT_LVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE1: mem pvt register + // Position of COMB_TIMING_ERR_CNT_NVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE1: mem pvt register + // Position of COMB_TIMING_ERR_CNT_HVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1_Msk = 0xffff + + // COMB_PVT_ERR_LVT_SITE2: mem pvt register + // Position of COMB_TIMING_ERR_CNT_LVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE2: mem pvt register + // Position of COMB_TIMING_ERR_CNT_NVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE2: mem pvt register + // Position of COMB_TIMING_ERR_CNT_HVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2_Msk = 0xffff + + // COMB_PVT_ERR_LVT_SITE3: mem pvt register + // Position of COMB_TIMING_ERR_CNT_LVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE3: mem pvt register + // Position of COMB_TIMING_ERR_CNT_NVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE3: mem pvt register + // Position of COMB_TIMING_ERR_CNT_HVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3_Msk = 0xffff + + // SYSTEM_REG_DATE: Version register + // Position of SYSTEM_REG_DATE field. + SYSTEM_SYSTEM_REG_DATE_SYSTEM_REG_DATE_Pos = 0x0 + // Bit mask of SYSTEM_REG_DATE field. + SYSTEM_SYSTEM_REG_DATE_SYSTEM_REG_DATE_Msk = 0xfffffff +) + +// Constants for SYSTIMER: System Timer +const ( + // CONF: SYSTIMER_CONF. + // Position of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Pos = 0x0 + // Bit mask of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Msk = 0x1 + // Bit SYSTIMER_CLK_FO. + SYSTIMER_CONF_SYSTIMER_CLK_FO = 0x1 + // Position of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Pos = 0x16 + // Bit mask of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Msk = 0x400000 + // Bit TARGET2_WORK_EN. + SYSTIMER_CONF_TARGET2_WORK_EN = 0x400000 + // Position of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Pos = 0x17 + // Bit mask of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Msk = 0x800000 + // Bit TARGET1_WORK_EN. + SYSTIMER_CONF_TARGET1_WORK_EN = 0x800000 + // Position of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Pos = 0x18 + // Bit mask of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Msk = 0x1000000 + // Bit TARGET0_WORK_EN. + SYSTIMER_CONF_TARGET0_WORK_EN = 0x1000000 + // Position of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Pos = 0x19 + // Bit mask of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Msk = 0x2000000 + // Bit TIMER_UNIT1_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN = 0x2000000 + // Position of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Pos = 0x1a + // Bit mask of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Msk = 0x4000000 + // Bit TIMER_UNIT1_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN = 0x4000000 + // Position of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Pos = 0x1b + // Bit mask of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Msk = 0x8000000 + // Bit TIMER_UNIT0_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN = 0x8000000 + // Position of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Pos = 0x1c + // Bit mask of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Msk = 0x10000000 + // Bit TIMER_UNIT0_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN = 0x10000000 + // Position of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Pos = 0x1d + // Bit mask of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Msk = 0x20000000 + // Bit TIMER_UNIT1_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN = 0x20000000 + // Position of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Pos = 0x1e + // Bit mask of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Msk = 0x40000000 + // Bit TIMER_UNIT0_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN = 0x40000000 + // Position of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + SYSTIMER_CONF_CLK_EN = 0x80000000 + + // UNIT0_OP: SYSTIMER_UNIT0_OP. + // Position of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT0_VALUE_VALID. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT0_UPDATE. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE = 0x40000000 + + // UNIT1_OP: SYSTIMER_UNIT1_OP. + // Position of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT1_VALUE_VALID. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT1_UPDATE. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE = 0x40000000 + + // UNIT0_LOAD_HI: SYSTIMER_UNIT0_LOAD_HI. + // Position of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Msk = 0xfffff + + // UNIT0_LOAD_LO: SYSTIMER_UNIT0_LOAD_LO. + // Position of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Msk = 0xffffffff + + // UNIT1_LOAD_HI: SYSTIMER_UNIT1_LOAD_HI. + // Position of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Msk = 0xfffff + + // UNIT1_LOAD_LO: SYSTIMER_UNIT1_LOAD_LO. + // Position of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Msk = 0xffffffff + + // TARGET0_HI: SYSTIMER_TARGET0_HI. + // Position of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Msk = 0xfffff + + // TARGET0_LO: SYSTIMER_TARGET0_LO. + // Position of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Msk = 0xffffffff + + // TARGET1_HI: SYSTIMER_TARGET1_HI. + // Position of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Msk = 0xfffff + + // TARGET1_LO: SYSTIMER_TARGET1_LO. + // Position of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Msk = 0xffffffff + + // TARGET2_HI: SYSTIMER_TARGET2_HI. + // Position of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Msk = 0xfffff + + // TARGET2_LO: SYSTIMER_TARGET2_LO. + // Position of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Msk = 0xffffffff + + // TARGET0_CONF: SYSTIMER_TARGET0_CONF. + // Position of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Pos = 0x0 + // Bit mask of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Msk = 0x3ffffff + // Position of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET0_PERIOD_MODE. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE = 0x40000000 + // Position of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET0_TIMER_UNIT_SEL. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL = 0x80000000 + + // TARGET1_CONF: SYSTIMER_TARGET1_CONF. + // Position of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Pos = 0x0 + // Bit mask of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Msk = 0x3ffffff + // Position of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET1_PERIOD_MODE. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE = 0x40000000 + // Position of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET1_TIMER_UNIT_SEL. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL = 0x80000000 + + // TARGET2_CONF: SYSTIMER_TARGET2_CONF. + // Position of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Pos = 0x0 + // Bit mask of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Msk = 0x3ffffff + // Position of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET2_PERIOD_MODE. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE = 0x40000000 + // Position of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET2_TIMER_UNIT_SEL. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL = 0x80000000 + + // UNIT0_VALUE_HI: SYSTIMER_UNIT0_VALUE_HI. + // Position of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Msk = 0xfffff + + // UNIT0_VALUE_LO: SYSTIMER_UNIT0_VALUE_LO. + // Position of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Msk = 0xffffffff + + // UNIT1_VALUE_HI: SYSTIMER_UNIT1_VALUE_HI. + // Position of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Msk = 0xfffff + + // UNIT1_VALUE_LO: SYSTIMER_UNIT1_VALUE_LO. + // Position of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Msk = 0xffffffff + + // COMP0_LOAD: SYSTIMER_COMP0_LOAD. + // Position of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Msk = 0x1 + // Bit TIMER_COMP0_LOAD. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD = 0x1 + + // COMP1_LOAD: SYSTIMER_COMP1_LOAD. + // Position of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Msk = 0x1 + // Bit TIMER_COMP1_LOAD. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD = 0x1 + + // COMP2_LOAD: SYSTIMER_COMP2_LOAD. + // Position of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Msk = 0x1 + // Bit TIMER_COMP2_LOAD. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD = 0x1 + + // UNIT0_LOAD: SYSTIMER_UNIT0_LOAD. + // Position of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Msk = 0x1 + // Bit TIMER_UNIT0_LOAD. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD = 0x1 + + // UNIT1_LOAD: SYSTIMER_UNIT1_LOAD. + // Position of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Msk = 0x1 + // Bit TIMER_UNIT1_LOAD. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD = 0x1 + + // INT_ENA: SYSTIMER_INT_ENA. + // Position of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Pos = 0x0 + // Bit mask of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Msk = 0x1 + // Bit TARGET0_INT_ENA. + SYSTIMER_INT_ENA_TARGET0_INT_ENA = 0x1 + // Position of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Pos = 0x1 + // Bit mask of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Msk = 0x2 + // Bit TARGET1_INT_ENA. + SYSTIMER_INT_ENA_TARGET1_INT_ENA = 0x2 + // Position of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Pos = 0x2 + // Bit mask of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Msk = 0x4 + // Bit TARGET2_INT_ENA. + SYSTIMER_INT_ENA_TARGET2_INT_ENA = 0x4 + + // INT_RAW: SYSTIMER_INT_RAW. + // Position of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Pos = 0x0 + // Bit mask of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Msk = 0x1 + // Bit TARGET0_INT_RAW. + SYSTIMER_INT_RAW_TARGET0_INT_RAW = 0x1 + // Position of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Pos = 0x1 + // Bit mask of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Msk = 0x2 + // Bit TARGET1_INT_RAW. + SYSTIMER_INT_RAW_TARGET1_INT_RAW = 0x2 + // Position of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Pos = 0x2 + // Bit mask of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Msk = 0x4 + // Bit TARGET2_INT_RAW. + SYSTIMER_INT_RAW_TARGET2_INT_RAW = 0x4 + + // INT_CLR: SYSTIMER_INT_CLR. + // Position of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Pos = 0x0 + // Bit mask of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Msk = 0x1 + // Bit TARGET0_INT_CLR. + SYSTIMER_INT_CLR_TARGET0_INT_CLR = 0x1 + // Position of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Pos = 0x1 + // Bit mask of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Msk = 0x2 + // Bit TARGET1_INT_CLR. + SYSTIMER_INT_CLR_TARGET1_INT_CLR = 0x2 + // Position of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Pos = 0x2 + // Bit mask of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Msk = 0x4 + // Bit TARGET2_INT_CLR. + SYSTIMER_INT_CLR_TARGET2_INT_CLR = 0x4 + + // INT_ST: SYSTIMER_INT_ST. + // Position of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Pos = 0x0 + // Bit mask of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Msk = 0x1 + // Bit TARGET0_INT_ST. + SYSTIMER_INT_ST_TARGET0_INT_ST = 0x1 + // Position of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Pos = 0x1 + // Bit mask of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Msk = 0x2 + // Bit TARGET1_INT_ST. + SYSTIMER_INT_ST_TARGET1_INT_ST = 0x2 + // Position of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Pos = 0x2 + // Bit mask of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Msk = 0x4 + // Bit TARGET2_INT_ST. + SYSTIMER_INT_ST_TARGET2_INT_ST = 0x4 + + // DATE: SYSTIMER_DATE. + // Position of DATE field. + SYSTIMER_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SYSTIMER_DATE_DATE_Msk = 0xffffffff +) + +// Constants for TIMG0: Timer Group 0 +const ( + // T0CONFIG: TIMG_T0CONFIG_REG. + // Position of USE_XTAL field. + TIMG_T0CONFIG_USE_XTAL_Pos = 0x9 + // Bit mask of USE_XTAL field. + TIMG_T0CONFIG_USE_XTAL_Msk = 0x200 + // Bit USE_XTAL. + TIMG_T0CONFIG_USE_XTAL = 0x200 + // Position of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Pos = 0xa + // Bit mask of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Msk = 0x400 + // Bit ALARM_EN. + TIMG_T0CONFIG_ALARM_EN = 0x400 + // Position of DIVCNT_RST field. + TIMG_T0CONFIG_DIVCNT_RST_Pos = 0xc + // Bit mask of DIVCNT_RST field. + TIMG_T0CONFIG_DIVCNT_RST_Msk = 0x1000 + // Bit DIVCNT_RST. + TIMG_T0CONFIG_DIVCNT_RST = 0x1000 + // Position of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Pos = 0xd + // Bit mask of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Msk = 0x1fffe000 + // Position of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Pos = 0x1d + // Bit mask of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Msk = 0x20000000 + // Bit AUTORELOAD. + TIMG_T0CONFIG_AUTORELOAD = 0x20000000 + // Position of INCREASE field. + TIMG_T0CONFIG_INCREASE_Pos = 0x1e + // Bit mask of INCREASE field. + TIMG_T0CONFIG_INCREASE_Msk = 0x40000000 + // Bit INCREASE. + TIMG_T0CONFIG_INCREASE = 0x40000000 + // Position of EN field. + TIMG_T0CONFIG_EN_Pos = 0x1f + // Bit mask of EN field. + TIMG_T0CONFIG_EN_Msk = 0x80000000 + // Bit EN. + TIMG_T0CONFIG_EN = 0x80000000 + + // T0LO: TIMG_T0LO_REG. + // Position of LO field. + TIMG_T0LO_LO_Pos = 0x0 + // Bit mask of LO field. + TIMG_T0LO_LO_Msk = 0xffffffff + + // T0HI: TIMG_T0HI_REG. + // Position of HI field. + TIMG_T0HI_HI_Pos = 0x0 + // Bit mask of HI field. + TIMG_T0HI_HI_Msk = 0x3fffff + + // T0UPDATE: TIMG_T0UPDATE_REG. + // Position of UPDATE field. + TIMG_T0UPDATE_UPDATE_Pos = 0x1f + // Bit mask of UPDATE field. + TIMG_T0UPDATE_UPDATE_Msk = 0x80000000 + // Bit UPDATE. + TIMG_T0UPDATE_UPDATE = 0x80000000 + + // T0ALARMLO: TIMG_T0ALARMLO_REG. + // Position of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Pos = 0x0 + // Bit mask of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Msk = 0xffffffff + + // T0ALARMHI: TIMG_T0ALARMHI_REG. + // Position of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Pos = 0x0 + // Bit mask of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Msk = 0x3fffff + + // T0LOADLO: TIMG_T0LOADLO_REG. + // Position of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Pos = 0x0 + // Bit mask of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Msk = 0xffffffff + + // T0LOADHI: TIMG_T0LOADHI_REG. + // Position of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Pos = 0x0 + // Bit mask of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Msk = 0x3fffff + + // T0LOAD: TIMG_T0LOAD_REG. + // Position of LOAD field. + TIMG_T0LOAD_LOAD_Pos = 0x0 + // Bit mask of LOAD field. + TIMG_T0LOAD_LOAD_Msk = 0xffffffff + + // WDTCONFIG0: TIMG_WDTCONFIG0_REG. + // Position of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xc + // Bit mask of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x1000 + // Bit WDT_APPCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x1000 + // Position of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xd + // Bit mask of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x2000 + // Bit WDT_PROCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x2000 + // Position of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xe + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x4000 + // Bit WDT_FLASHBOOT_MOD_EN. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x4000 + // Position of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xf + // Bit mask of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0x38000 + // Position of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x12 + // Bit mask of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x1c0000 + // Position of WDT_USE_XTAL field. + TIMG_WDTCONFIG0_WDT_USE_XTAL_Pos = 0x15 + // Bit mask of WDT_USE_XTAL field. + TIMG_WDTCONFIG0_WDT_USE_XTAL_Msk = 0x200000 + // Bit WDT_USE_XTAL. + TIMG_WDTCONFIG0_WDT_USE_XTAL = 0x200000 + // Position of WDT_CONF_UPDATE_EN field. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Pos = 0x16 + // Bit mask of WDT_CONF_UPDATE_EN field. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Msk = 0x400000 + // Bit WDT_CONF_UPDATE_EN. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN = 0x400000 + // Position of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Pos = 0x17 + // Bit mask of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Msk = 0x1800000 + // Position of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Pos = 0x19 + // Bit mask of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Msk = 0x6000000 + // Position of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Pos = 0x1b + // Bit mask of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Msk = 0x18000000 + // Position of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Pos = 0x1d + // Bit mask of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Msk = 0x60000000 + // Position of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + TIMG_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: TIMG_WDTCONFIG1_REG. + // Position of WDT_DIVCNT_RST field. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Pos = 0x0 + // Bit mask of WDT_DIVCNT_RST field. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Msk = 0x1 + // Bit WDT_DIVCNT_RST. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST = 0x1 + // Position of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Pos = 0x10 + // Bit mask of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Msk = 0xffff0000 + + // WDTCONFIG2: TIMG_WDTCONFIG2_REG. + // Position of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: TIMG_WDTCONFIG3_REG. + // Position of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: TIMG_WDTCONFIG4_REG. + // Position of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG5: TIMG_WDTCONFIG5_REG. + // Position of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: TIMG_WDTFEED_REG. + // Position of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Pos = 0x0 + // Bit mask of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Msk = 0xffffffff + + // WDTWPROTECT: TIMG_WDTWPROTECT_REG. + // Position of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // RTCCALICFG: TIMG_RTCCALICFG_REG. + // Position of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Pos = 0xc + // Bit mask of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Msk = 0x1000 + // Bit RTC_CALI_START_CYCLING. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING = 0x1000 + // Position of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Pos = 0xd + // Bit mask of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Msk = 0x6000 + // Position of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Pos = 0xf + // Bit mask of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Msk = 0x8000 + // Bit RTC_CALI_RDY. + TIMG_RTCCALICFG_RTC_CALI_RDY = 0x8000 + // Position of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Pos = 0x10 + // Bit mask of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Msk = 0x7fff0000 + // Position of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Pos = 0x1f + // Bit mask of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Msk = 0x80000000 + // Bit RTC_CALI_START. + TIMG_RTCCALICFG_RTC_CALI_START = 0x80000000 + + // RTCCALICFG1: TIMG_RTCCALICFG1_REG. + // Position of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Pos = 0x0 + // Bit mask of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Msk = 0x1 + // Bit RTC_CALI_CYCLING_DATA_VLD. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD = 0x1 + // Position of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Pos = 0x7 + // Bit mask of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Msk = 0xffffff80 + + // INT_ENA_TIMERS: INT_ENA_TIMG_REG + // Position of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Pos = 0x0 + // Bit mask of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Msk = 0x1 + // Bit T0_INT_ENA. + TIMG_INT_ENA_TIMERS_T0_INT_ENA = 0x1 + // Position of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Pos = 0x1 + // Bit mask of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Msk = 0x2 + // Bit WDT_INT_ENA. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA = 0x2 + + // INT_RAW_TIMERS: INT_RAW_TIMG_REG + // Position of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Pos = 0x0 + // Bit mask of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Msk = 0x1 + // Bit T0_INT_RAW. + TIMG_INT_RAW_TIMERS_T0_INT_RAW = 0x1 + // Position of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Pos = 0x1 + // Bit mask of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Msk = 0x2 + // Bit WDT_INT_RAW. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW = 0x2 + + // INT_ST_TIMERS: INT_ST_TIMG_REG + // Position of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Pos = 0x0 + // Bit mask of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Msk = 0x1 + // Bit T0_INT_ST. + TIMG_INT_ST_TIMERS_T0_INT_ST = 0x1 + // Position of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Pos = 0x1 + // Bit mask of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Msk = 0x2 + // Bit WDT_INT_ST. + TIMG_INT_ST_TIMERS_WDT_INT_ST = 0x2 + + // INT_CLR_TIMERS: INT_CLR_TIMG_REG + // Position of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Pos = 0x0 + // Bit mask of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Msk = 0x1 + // Bit T0_INT_CLR. + TIMG_INT_CLR_TIMERS_T0_INT_CLR = 0x1 + // Position of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Pos = 0x1 + // Bit mask of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Msk = 0x2 + // Bit WDT_INT_CLR. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR = 0x2 + + // RTCCALICFG2: TIMG_RTCCALICFG2_REG. + // Position of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Pos = 0x0 + // Bit mask of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Msk = 0x1 + // Bit RTC_CALI_TIMEOUT. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT = 0x1 + // Position of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Pos = 0x3 + // Bit mask of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Msk = 0x78 + // Position of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Pos = 0x7 + // Bit mask of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Msk = 0xffffff80 + + // NTIMG_DATE: TIMG_NTIMG_DATE_REG. + // Position of NTIMGS_DATE field. + TIMG_NTIMG_DATE_NTIMGS_DATE_Pos = 0x0 + // Bit mask of NTIMGS_DATE field. + TIMG_NTIMG_DATE_NTIMGS_DATE_Msk = 0xfffffff + + // REGCLK: TIMG_REGCLK_REG. + // Position of WDT_CLK_IS_ACTIVE field. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Pos = 0x1d + // Bit mask of WDT_CLK_IS_ACTIVE field. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Msk = 0x20000000 + // Bit WDT_CLK_IS_ACTIVE. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE = 0x20000000 + // Position of TIMER_CLK_IS_ACTIVE field. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Pos = 0x1e + // Bit mask of TIMER_CLK_IS_ACTIVE field. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Msk = 0x40000000 + // Bit TIMER_CLK_IS_ACTIVE. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE = 0x40000000 + // Position of CLK_EN field. + TIMG_REGCLK_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + TIMG_REGCLK_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + TIMG_REGCLK_CLK_EN = 0x80000000 +) + +// Constants for TWAI0: Two-Wire Automotive Interface +const ( + // MODE: Mode Register + // Position of RESET_MODE field. + TWAI_MODE_RESET_MODE_Pos = 0x0 + // Bit mask of RESET_MODE field. + TWAI_MODE_RESET_MODE_Msk = 0x1 + // Bit RESET_MODE. + TWAI_MODE_RESET_MODE = 0x1 + // Position of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Pos = 0x1 + // Bit mask of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Msk = 0x2 + // Bit LISTEN_ONLY_MODE. + TWAI_MODE_LISTEN_ONLY_MODE = 0x2 + // Position of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Pos = 0x2 + // Bit mask of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Msk = 0x4 + // Bit SELF_TEST_MODE. + TWAI_MODE_SELF_TEST_MODE = 0x4 + // Position of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Pos = 0x3 + // Bit mask of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Msk = 0x8 + // Bit RX_FILTER_MODE. + TWAI_MODE_RX_FILTER_MODE = 0x8 + + // CMD: Command Register + // Position of TX_REQ field. + TWAI_CMD_TX_REQ_Pos = 0x0 + // Bit mask of TX_REQ field. + TWAI_CMD_TX_REQ_Msk = 0x1 + // Bit TX_REQ. + TWAI_CMD_TX_REQ = 0x1 + // Position of ABORT_TX field. + TWAI_CMD_ABORT_TX_Pos = 0x1 + // Bit mask of ABORT_TX field. + TWAI_CMD_ABORT_TX_Msk = 0x2 + // Bit ABORT_TX. + TWAI_CMD_ABORT_TX = 0x2 + // Position of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Pos = 0x2 + // Bit mask of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Msk = 0x4 + // Bit RELEASE_BUF. + TWAI_CMD_RELEASE_BUF = 0x4 + // Position of CLR_OVERRUN field. + TWAI_CMD_CLR_OVERRUN_Pos = 0x3 + // Bit mask of CLR_OVERRUN field. + TWAI_CMD_CLR_OVERRUN_Msk = 0x8 + // Bit CLR_OVERRUN. + TWAI_CMD_CLR_OVERRUN = 0x8 + // Position of SELF_RX_REQ field. + TWAI_CMD_SELF_RX_REQ_Pos = 0x4 + // Bit mask of SELF_RX_REQ field. + TWAI_CMD_SELF_RX_REQ_Msk = 0x10 + // Bit SELF_RX_REQ. + TWAI_CMD_SELF_RX_REQ = 0x10 + + // STATUS: Status register + // Position of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Pos = 0x0 + // Bit mask of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Msk = 0x1 + // Bit RX_BUF_ST. + TWAI_STATUS_RX_BUF_ST = 0x1 + // Position of OVERRUN_ST field. + TWAI_STATUS_OVERRUN_ST_Pos = 0x1 + // Bit mask of OVERRUN_ST field. + TWAI_STATUS_OVERRUN_ST_Msk = 0x2 + // Bit OVERRUN_ST. + TWAI_STATUS_OVERRUN_ST = 0x2 + // Position of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Pos = 0x2 + // Bit mask of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Msk = 0x4 + // Bit TX_BUF_ST. + TWAI_STATUS_TX_BUF_ST = 0x4 + // Position of TX_COMPLETE field. + TWAI_STATUS_TX_COMPLETE_Pos = 0x3 + // Bit mask of TX_COMPLETE field. + TWAI_STATUS_TX_COMPLETE_Msk = 0x8 + // Bit TX_COMPLETE. + TWAI_STATUS_TX_COMPLETE = 0x8 + // Position of RX_ST field. + TWAI_STATUS_RX_ST_Pos = 0x4 + // Bit mask of RX_ST field. + TWAI_STATUS_RX_ST_Msk = 0x10 + // Bit RX_ST. + TWAI_STATUS_RX_ST = 0x10 + // Position of TX_ST field. + TWAI_STATUS_TX_ST_Pos = 0x5 + // Bit mask of TX_ST field. + TWAI_STATUS_TX_ST_Msk = 0x20 + // Bit TX_ST. + TWAI_STATUS_TX_ST = 0x20 + // Position of ERR_ST field. + TWAI_STATUS_ERR_ST_Pos = 0x6 + // Bit mask of ERR_ST field. + TWAI_STATUS_ERR_ST_Msk = 0x40 + // Bit ERR_ST. + TWAI_STATUS_ERR_ST = 0x40 + // Position of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Pos = 0x7 + // Bit mask of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Msk = 0x80 + // Bit BUS_OFF_ST. + TWAI_STATUS_BUS_OFF_ST = 0x80 + // Position of MISS_ST field. + TWAI_STATUS_MISS_ST_Pos = 0x8 + // Bit mask of MISS_ST field. + TWAI_STATUS_MISS_ST_Msk = 0x100 + // Bit MISS_ST. + TWAI_STATUS_MISS_ST = 0x100 + + // INT_RAW: Interrupt Register + // Position of RX_INT_ST field. + TWAI_INT_RAW_RX_INT_ST_Pos = 0x0 + // Bit mask of RX_INT_ST field. + TWAI_INT_RAW_RX_INT_ST_Msk = 0x1 + // Bit RX_INT_ST. + TWAI_INT_RAW_RX_INT_ST = 0x1 + // Position of TX_INT_ST field. + TWAI_INT_RAW_TX_INT_ST_Pos = 0x1 + // Bit mask of TX_INT_ST field. + TWAI_INT_RAW_TX_INT_ST_Msk = 0x2 + // Bit TX_INT_ST. + TWAI_INT_RAW_TX_INT_ST = 0x2 + // Position of ERR_WARN_INT_ST field. + TWAI_INT_RAW_ERR_WARN_INT_ST_Pos = 0x2 + // Bit mask of ERR_WARN_INT_ST field. + TWAI_INT_RAW_ERR_WARN_INT_ST_Msk = 0x4 + // Bit ERR_WARN_INT_ST. + TWAI_INT_RAW_ERR_WARN_INT_ST = 0x4 + // Position of OVERRUN_INT_ST field. + TWAI_INT_RAW_OVERRUN_INT_ST_Pos = 0x3 + // Bit mask of OVERRUN_INT_ST field. + TWAI_INT_RAW_OVERRUN_INT_ST_Msk = 0x8 + // Bit OVERRUN_INT_ST. + TWAI_INT_RAW_OVERRUN_INT_ST = 0x8 + // Position of ERR_PASSIVE_INT_ST field. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ST field. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ST. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST = 0x20 + // Position of ARB_LOST_INT_ST field. + TWAI_INT_RAW_ARB_LOST_INT_ST_Pos = 0x6 + // Bit mask of ARB_LOST_INT_ST field. + TWAI_INT_RAW_ARB_LOST_INT_ST_Msk = 0x40 + // Bit ARB_LOST_INT_ST. + TWAI_INT_RAW_ARB_LOST_INT_ST = 0x40 + // Position of BUS_ERR_INT_ST field. + TWAI_INT_RAW_BUS_ERR_INT_ST_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ST field. + TWAI_INT_RAW_BUS_ERR_INT_ST_Msk = 0x80 + // Bit BUS_ERR_INT_ST. + TWAI_INT_RAW_BUS_ERR_INT_ST = 0x80 + + // INT_ENA: Interrupt Enable Register + // Position of RX_INT_ENA field. + TWAI_INT_ENA_RX_INT_ENA_Pos = 0x0 + // Bit mask of RX_INT_ENA field. + TWAI_INT_ENA_RX_INT_ENA_Msk = 0x1 + // Bit RX_INT_ENA. + TWAI_INT_ENA_RX_INT_ENA = 0x1 + // Position of TX_INT_ENA field. + TWAI_INT_ENA_TX_INT_ENA_Pos = 0x1 + // Bit mask of TX_INT_ENA field. + TWAI_INT_ENA_TX_INT_ENA_Msk = 0x2 + // Bit TX_INT_ENA. + TWAI_INT_ENA_TX_INT_ENA = 0x2 + // Position of ERR_WARN_INT_ENA field. + TWAI_INT_ENA_ERR_WARN_INT_ENA_Pos = 0x2 + // Bit mask of ERR_WARN_INT_ENA field. + TWAI_INT_ENA_ERR_WARN_INT_ENA_Msk = 0x4 + // Bit ERR_WARN_INT_ENA. + TWAI_INT_ENA_ERR_WARN_INT_ENA = 0x4 + // Position of OVERRUN_INT_ENA field. + TWAI_INT_ENA_OVERRUN_INT_ENA_Pos = 0x3 + // Bit mask of OVERRUN_INT_ENA field. + TWAI_INT_ENA_OVERRUN_INT_ENA_Msk = 0x8 + // Bit OVERRUN_INT_ENA. + TWAI_INT_ENA_OVERRUN_INT_ENA = 0x8 + // Position of ERR_PASSIVE_INT_ENA field. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ENA field. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ENA. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA = 0x20 + // Position of ARB_LOST_INT_ENA field. + TWAI_INT_ENA_ARB_LOST_INT_ENA_Pos = 0x6 + // Bit mask of ARB_LOST_INT_ENA field. + TWAI_INT_ENA_ARB_LOST_INT_ENA_Msk = 0x40 + // Bit ARB_LOST_INT_ENA. + TWAI_INT_ENA_ARB_LOST_INT_ENA = 0x40 + // Position of BUS_ERR_INT_ENA field. + TWAI_INT_ENA_BUS_ERR_INT_ENA_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ENA field. + TWAI_INT_ENA_BUS_ERR_INT_ENA_Msk = 0x80 + // Bit BUS_ERR_INT_ENA. + TWAI_INT_ENA_BUS_ERR_INT_ENA = 0x80 + + // BUS_TIMING_0: Bus Timing Register 0 + // Position of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Pos = 0x0 + // Bit mask of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Msk = 0x3fff + // Position of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Pos = 0xe + // Bit mask of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Msk = 0xc000 + + // BUS_TIMING_1: Bus Timing Register 1 + // Position of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Pos = 0x0 + // Bit mask of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Msk = 0xf + // Position of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Pos = 0x4 + // Bit mask of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Msk = 0x70 + // Position of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Pos = 0x7 + // Bit mask of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Msk = 0x80 + // Bit TIME_SAMP. + TWAI_BUS_TIMING_1_TIME_SAMP = 0x80 + + // ARB_LOST_CAP: Arbitration Lost Capture Register + // Position of ARB_LOST_CAP field. + TWAI_ARB_LOST_CAP_ARB_LOST_CAP_Pos = 0x0 + // Bit mask of ARB_LOST_CAP field. + TWAI_ARB_LOST_CAP_ARB_LOST_CAP_Msk = 0x1f + + // ERR_CODE_CAP: Error Code Capture Register + // Position of ECC_SEGMENT field. + TWAI_ERR_CODE_CAP_ECC_SEGMENT_Pos = 0x0 + // Bit mask of ECC_SEGMENT field. + TWAI_ERR_CODE_CAP_ECC_SEGMENT_Msk = 0x1f + // Position of ECC_DIRECTION field. + TWAI_ERR_CODE_CAP_ECC_DIRECTION_Pos = 0x5 + // Bit mask of ECC_DIRECTION field. + TWAI_ERR_CODE_CAP_ECC_DIRECTION_Msk = 0x20 + // Bit ECC_DIRECTION. + TWAI_ERR_CODE_CAP_ECC_DIRECTION = 0x20 + // Position of ECC_TYPE field. + TWAI_ERR_CODE_CAP_ECC_TYPE_Pos = 0x6 + // Bit mask of ECC_TYPE field. + TWAI_ERR_CODE_CAP_ECC_TYPE_Msk = 0xc0 + + // ERR_WARNING_LIMIT: Error Warning Limit Register + // Position of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Pos = 0x0 + // Bit mask of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Msk = 0xff + + // RX_ERR_CNT: Receive Error Counter Register + // Position of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Pos = 0x0 + // Bit mask of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Msk = 0xff + + // TX_ERR_CNT: Transmit Error Counter Register + // Position of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Pos = 0x0 + // Bit mask of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Msk = 0xff + + // DATA_0: Data register 0 + // Position of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Pos = 0x0 + // Bit mask of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Msk = 0xff + + // DATA_1: Data register 1 + // Position of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Pos = 0x0 + // Bit mask of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Msk = 0xff + + // DATA_2: Data register 2 + // Position of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Pos = 0x0 + // Bit mask of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Msk = 0xff + + // DATA_3: Data register 3 + // Position of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Pos = 0x0 + // Bit mask of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Msk = 0xff + + // DATA_4: Data register 4 + // Position of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Pos = 0x0 + // Bit mask of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Msk = 0xff + + // DATA_5: Data register 5 + // Position of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Pos = 0x0 + // Bit mask of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Msk = 0xff + + // DATA_6: Data register 6 + // Position of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Pos = 0x0 + // Bit mask of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Msk = 0xff + + // DATA_7: Data register 7 + // Position of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Pos = 0x0 + // Bit mask of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Msk = 0xff + + // DATA_8: Data register 8 + // Position of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Pos = 0x0 + // Bit mask of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Msk = 0xff + + // DATA_9: Data register 9 + // Position of TX_BYTE_9 field. + TWAI_DATA_9_TX_BYTE_9_Pos = 0x0 + // Bit mask of TX_BYTE_9 field. + TWAI_DATA_9_TX_BYTE_9_Msk = 0xff + + // DATA_10: Data register 10 + // Position of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Pos = 0x0 + // Bit mask of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Msk = 0xff + + // DATA_11: Data register 11 + // Position of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Pos = 0x0 + // Bit mask of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Msk = 0xff + + // DATA_12: Data register 12 + // Position of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Pos = 0x0 + // Bit mask of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Msk = 0xff + + // RX_MESSAGE_CNT: Receive Message Counter Register + // Position of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Pos = 0x0 + // Bit mask of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Msk = 0x7f + + // CLOCK_DIVIDER: Clock Divider register + // Position of CD field. + TWAI_CLOCK_DIVIDER_CD_Pos = 0x0 + // Bit mask of CD field. + TWAI_CLOCK_DIVIDER_CD_Msk = 0xff + // Position of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Pos = 0x8 + // Bit mask of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Msk = 0x100 + // Bit CLOCK_OFF. + TWAI_CLOCK_DIVIDER_CLOCK_OFF = 0x100 +) + +// Constants for UART0: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +const ( + // FIFO: FIFO data register + // Position of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9 + // Bit mask of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200 + // Bit SW_XON_INT_RAW. + UART_INT_RAW_SW_XON_INT_RAW = 0x200 + // Position of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa + // Bit mask of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400 + // Bit SW_XOFF_INT_RAW. + UART_INT_RAW_SW_XOFF_INT_RAW = 0x400 + // Position of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb + // Bit mask of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800 + // Bit GLITCH_DET_INT_RAW. + UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800 + // Position of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000 + // Position of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit TX_DONE_INT_RAW. + UART_INT_RAW_TX_DONE_INT_RAW = 0x4000 + // Position of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_RAW. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW = 0x8000 + // Position of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_RAW. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW = 0x10000 + // Position of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Msk = 0x20000 + // Bit RS485_CLASH_INT_RAW. + UART_INT_RAW_RS485_CLASH_INT_RAW = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_RAW. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000 + // Position of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13 + // Bit mask of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000 + // Bit WAKEUP_INT_RAW. + UART_INT_RAW_WAKEUP_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Pos = 0x9 + // Bit mask of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Msk = 0x200 + // Bit SW_XON_INT_ST. + UART_INT_ST_SW_XON_INT_ST = 0x200 + // Position of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa + // Bit mask of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400 + // Bit SW_XOFF_INT_ST. + UART_INT_ST_SW_XOFF_INT_ST = 0x400 + // Position of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800 + // Bit GLITCH_DET_INT_ST. + UART_INT_ST_GLITCH_DET_INT_ST = 0x800 + // Position of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ST. + UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ST. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000 + // Position of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000 + // Bit TX_DONE_INT_ST. + UART_INT_ST_TX_DONE_INT_ST = 0x4000 + // Position of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ST. + UART_INT_ST_RS485_PARITY_ERR_INT_ST = 0x8000 + // Position of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ST. + UART_INT_ST_RS485_FRM_ERR_INT_ST = 0x10000 + // Position of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Msk = 0x20000 + // Bit RS485_CLASH_INT_ST. + UART_INT_ST_RS485_CLASH_INT_ST = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ST. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000 + // Position of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13 + // Bit mask of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000 + // Bit WAKEUP_INT_ST. + UART_INT_ST_WAKEUP_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9 + // Bit mask of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200 + // Bit SW_XON_INT_ENA. + UART_INT_ENA_SW_XON_INT_ENA = 0x200 + // Position of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa + // Bit mask of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400 + // Bit SW_XOFF_INT_ENA. + UART_INT_ENA_SW_XOFF_INT_ENA = 0x400 + // Position of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800 + // Bit GLITCH_DET_INT_ENA. + UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800 + // Position of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000 + // Position of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit TX_DONE_INT_ENA. + UART_INT_ENA_TX_DONE_INT_ENA = 0x4000 + // Position of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ENA. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA = 0x8000 + // Position of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ENA. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA = 0x10000 + // Position of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Msk = 0x20000 + // Bit RS485_CLASH_INT_ENA. + UART_INT_ENA_RS485_CLASH_INT_ENA = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ENA. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000 + // Position of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13 + // Bit mask of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000 + // Bit WAKEUP_INT_ENA. + UART_INT_ENA_WAKEUP_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9 + // Bit mask of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200 + // Bit SW_XON_INT_CLR. + UART_INT_CLR_SW_XON_INT_CLR = 0x200 + // Position of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa + // Bit mask of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400 + // Bit SW_XOFF_INT_CLR. + UART_INT_CLR_SW_XOFF_INT_CLR = 0x400 + // Position of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb + // Bit mask of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800 + // Bit GLITCH_DET_INT_CLR. + UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800 + // Position of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000 + // Position of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit TX_DONE_INT_CLR. + UART_INT_CLR_TX_DONE_INT_CLR = 0x4000 + // Position of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_CLR. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR = 0x8000 + // Position of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_CLR. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR = 0x10000 + // Position of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Msk = 0x20000 + // Bit RS485_CLASH_INT_CLR. + UART_INT_CLR_RS485_CLASH_INT_CLR = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_CLR. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000 + // Position of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13 + // Bit mask of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000 + // Bit WAKEUP_INT_CLR. + UART_INT_CLR_WAKEUP_INT_CLR = 0x80000 + + // CLKDIV: Clock divider configuration + // Position of CLKDIV field. + UART_CLKDIV_CLKDIV_Pos = 0x0 + // Bit mask of CLKDIV field. + UART_CLKDIV_CLKDIV_Msk = 0xfff + // Position of FRAG field. + UART_CLKDIV_FRAG_Pos = 0x14 + // Bit mask of FRAG field. + UART_CLKDIV_FRAG_Msk = 0xf00000 + + // RX_FILT: Rx Filter configuration + // Position of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Pos = 0x0 + // Bit mask of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Msk = 0xff + // Position of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Pos = 0x8 + // Bit mask of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Msk = 0x100 + // Bit GLITCH_FILT_EN. + UART_RX_FILT_GLITCH_FILT_EN = 0x100 + + // STATUS: UART status register + // Position of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Pos = 0x0 + // Bit mask of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Msk = 0x3ff + // Position of DSRN field. + UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + UART_STATUS_DSRN = 0x2000 + // Position of CTSN field. + UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + UART_STATUS_CTSN = 0x4000 + // Position of RXD field. + UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + UART_STATUS_RXD = 0x8000 + // Position of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Pos = 0x10 + // Bit mask of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Msk = 0x3ff0000 + // Position of DTRN field. + UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + UART_STATUS_DTRN = 0x20000000 + // Position of RTSN field. + UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + UART_STATUS_RTSN = 0x40000000 + // Position of TXD field. + UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + UART_STATUS_TXD = 0x80000000 + + // CONF0: a + // Position of PARITY field. + UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + UART_CONF0_PARITY = 0x1 + // Position of PARITY_EN field. + UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + UART_CONF0_PARITY_EN = 0x2 + // Position of BIT_NUM field. + UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + UART_CONF0_BIT_NUM_Msk = 0xc + // Position of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of SW_RTS field. + UART_CONF0_SW_RTS_Pos = 0x6 + // Bit mask of SW_RTS field. + UART_CONF0_SW_RTS_Msk = 0x40 + // Bit SW_RTS. + UART_CONF0_SW_RTS = 0x40 + // Position of SW_DTR field. + UART_CONF0_SW_DTR_Pos = 0x7 + // Bit mask of SW_DTR field. + UART_CONF0_SW_DTR_Msk = 0x80 + // Bit SW_DTR. + UART_CONF0_SW_DTR = 0x80 + // Position of TXD_BRK field. + UART_CONF0_TXD_BRK_Pos = 0x8 + // Bit mask of TXD_BRK field. + UART_CONF0_TXD_BRK_Msk = 0x100 + // Bit TXD_BRK. + UART_CONF0_TXD_BRK = 0x100 + // Position of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Pos = 0x9 + // Bit mask of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Msk = 0x200 + // Bit IRDA_DPLX. + UART_CONF0_IRDA_DPLX = 0x200 + // Position of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Pos = 0xa + // Bit mask of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Msk = 0x400 + // Bit IRDA_TX_EN. + UART_CONF0_IRDA_TX_EN = 0x400 + // Position of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Pos = 0xb + // Bit mask of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Msk = 0x800 + // Bit IRDA_WCTL. + UART_CONF0_IRDA_WCTL = 0x800 + // Position of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Pos = 0xc + // Bit mask of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Msk = 0x1000 + // Bit IRDA_TX_INV. + UART_CONF0_IRDA_TX_INV = 0x1000 + // Position of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Pos = 0xd + // Bit mask of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Msk = 0x2000 + // Bit IRDA_RX_INV. + UART_CONF0_IRDA_RX_INV = 0x2000 + // Position of LOOPBACK field. + UART_CONF0_LOOPBACK_Pos = 0xe + // Bit mask of LOOPBACK field. + UART_CONF0_LOOPBACK_Msk = 0x4000 + // Bit LOOPBACK. + UART_CONF0_LOOPBACK = 0x4000 + // Position of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Pos = 0xf + // Bit mask of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Msk = 0x8000 + // Bit TX_FLOW_EN. + UART_CONF0_TX_FLOW_EN = 0x8000 + // Position of IRDA_EN field. + UART_CONF0_IRDA_EN_Pos = 0x10 + // Bit mask of IRDA_EN field. + UART_CONF0_IRDA_EN_Msk = 0x10000 + // Bit IRDA_EN. + UART_CONF0_IRDA_EN = 0x10000 + // Position of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Pos = 0x11 + // Bit mask of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Msk = 0x20000 + // Bit RXFIFO_RST. + UART_CONF0_RXFIFO_RST = 0x20000 + // Position of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Pos = 0x12 + // Bit mask of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Msk = 0x40000 + // Bit TXFIFO_RST. + UART_CONF0_TXFIFO_RST = 0x40000 + // Position of RXD_INV field. + UART_CONF0_RXD_INV_Pos = 0x13 + // Bit mask of RXD_INV field. + UART_CONF0_RXD_INV_Msk = 0x80000 + // Bit RXD_INV. + UART_CONF0_RXD_INV = 0x80000 + // Position of CTS_INV field. + UART_CONF0_CTS_INV_Pos = 0x14 + // Bit mask of CTS_INV field. + UART_CONF0_CTS_INV_Msk = 0x100000 + // Bit CTS_INV. + UART_CONF0_CTS_INV = 0x100000 + // Position of DSR_INV field. + UART_CONF0_DSR_INV_Pos = 0x15 + // Bit mask of DSR_INV field. + UART_CONF0_DSR_INV_Msk = 0x200000 + // Bit DSR_INV. + UART_CONF0_DSR_INV = 0x200000 + // Position of TXD_INV field. + UART_CONF0_TXD_INV_Pos = 0x16 + // Bit mask of TXD_INV field. + UART_CONF0_TXD_INV_Msk = 0x400000 + // Bit TXD_INV. + UART_CONF0_TXD_INV = 0x400000 + // Position of RTS_INV field. + UART_CONF0_RTS_INV_Pos = 0x17 + // Bit mask of RTS_INV field. + UART_CONF0_RTS_INV_Msk = 0x800000 + // Bit RTS_INV. + UART_CONF0_RTS_INV = 0x800000 + // Position of DTR_INV field. + UART_CONF0_DTR_INV_Pos = 0x18 + // Bit mask of DTR_INV field. + UART_CONF0_DTR_INV_Msk = 0x1000000 + // Bit DTR_INV. + UART_CONF0_DTR_INV = 0x1000000 + // Position of CLK_EN field. + UART_CONF0_CLK_EN_Pos = 0x19 + // Bit mask of CLK_EN field. + UART_CONF0_CLK_EN_Msk = 0x2000000 + // Bit CLK_EN. + UART_CONF0_CLK_EN = 0x2000000 + // Position of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Pos = 0x1a + // Bit mask of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Msk = 0x4000000 + // Bit ERR_WR_MASK. + UART_CONF0_ERR_WR_MASK = 0x4000000 + // Position of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Pos = 0x1b + // Bit mask of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Msk = 0x8000000 + // Bit AUTOBAUD_EN. + UART_CONF0_AUTOBAUD_EN = 0x8000000 + // Position of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Pos = 0x1c + // Bit mask of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Msk = 0x10000000 + // Bit MEM_CLK_EN. + UART_CONF0_MEM_CLK_EN = 0x10000000 + + // CONF1: Configuration register 1 + // Position of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0x1ff + // Position of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0x9 + // Bit mask of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0x3fe00 + // Position of DIS_RX_DAT_OVF field. + UART_CONF1_DIS_RX_DAT_OVF_Pos = 0x12 + // Bit mask of DIS_RX_DAT_OVF field. + UART_CONF1_DIS_RX_DAT_OVF_Msk = 0x40000 + // Bit DIS_RX_DAT_OVF. + UART_CONF1_DIS_RX_DAT_OVF = 0x40000 + // Position of RX_TOUT_FLOW_DIS field. + UART_CONF1_RX_TOUT_FLOW_DIS_Pos = 0x13 + // Bit mask of RX_TOUT_FLOW_DIS field. + UART_CONF1_RX_TOUT_FLOW_DIS_Msk = 0x80000 + // Bit RX_TOUT_FLOW_DIS. + UART_CONF1_RX_TOUT_FLOW_DIS = 0x80000 + // Position of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Pos = 0x14 + // Bit mask of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Msk = 0x100000 + // Bit RX_FLOW_EN. + UART_CONF1_RX_FLOW_EN = 0x100000 + // Position of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Pos = 0x15 + // Bit mask of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Msk = 0x200000 + // Bit RX_TOUT_EN. + UART_CONF1_RX_TOUT_EN = 0x200000 + + // LOWPULSE: Autobaud minimum low pulse duration register + // Position of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Msk = 0xfff + + // HIGHPULSE: Autobaud minimum high pulse duration register + // Position of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Msk = 0xfff + + // RXD_CNT: Autobaud edge change count register + // Position of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0 + // Bit mask of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff + + // FLOW_CONF: Software flow-control configuration + // Position of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Pos = 0x0 + // Bit mask of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Msk = 0x1 + // Bit SW_FLOW_CON_EN. + UART_FLOW_CONF_SW_FLOW_CON_EN = 0x1 + // Position of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Pos = 0x1 + // Bit mask of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Msk = 0x2 + // Bit XONOFF_DEL. + UART_FLOW_CONF_XONOFF_DEL = 0x2 + // Position of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Pos = 0x2 + // Bit mask of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Msk = 0x4 + // Bit FORCE_XON. + UART_FLOW_CONF_FORCE_XON = 0x4 + // Position of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Pos = 0x3 + // Bit mask of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Msk = 0x8 + // Bit FORCE_XOFF. + UART_FLOW_CONF_FORCE_XOFF = 0x8 + // Position of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Pos = 0x4 + // Bit mask of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Msk = 0x10 + // Bit SEND_XON. + UART_FLOW_CONF_SEND_XON = 0x10 + // Position of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Pos = 0x5 + // Bit mask of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Msk = 0x20 + // Bit SEND_XOFF. + UART_FLOW_CONF_SEND_XOFF = 0x20 + + // SLEEP_CONF: Sleep-mode configuration + // Position of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Pos = 0x0 + // Bit mask of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Msk = 0x3ff + + // SWFC_CONF0: Software flow-control character configuration + // Position of XOFF_THRESHOLD field. + UART_SWFC_CONF0_XOFF_THRESHOLD_Pos = 0x0 + // Bit mask of XOFF_THRESHOLD field. + UART_SWFC_CONF0_XOFF_THRESHOLD_Msk = 0x1ff + // Position of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Pos = 0x9 + // Bit mask of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Msk = 0x1fe00 + + // SWFC_CONF1: Software flow-control character configuration + // Position of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x0 + // Bit mask of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0x1ff + // Position of XON_CHAR field. + UART_SWFC_CONF1_XON_CHAR_Pos = 0x9 + // Bit mask of XON_CHAR field. + UART_SWFC_CONF1_XON_CHAR_Msk = 0x1fe00 + + // TXBRK_CONF: Tx Break character configuration + // Position of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Pos = 0x0 + // Bit mask of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Msk = 0xff + + // IDLE_CONF: Frame-end idle configuration + // Position of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Pos = 0x0 + // Bit mask of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Msk = 0x3ff + // Position of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Pos = 0xa + // Bit mask of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Msk = 0xffc00 + + // RS485_CONF: RS485 mode configuration + // Position of RS485_EN field. + UART_RS485_CONF_RS485_EN_Pos = 0x0 + // Bit mask of RS485_EN field. + UART_RS485_CONF_RS485_EN_Msk = 0x1 + // Bit RS485_EN. + UART_RS485_CONF_RS485_EN = 0x1 + // Position of DL0_EN field. + UART_RS485_CONF_DL0_EN_Pos = 0x1 + // Bit mask of DL0_EN field. + UART_RS485_CONF_DL0_EN_Msk = 0x2 + // Bit DL0_EN. + UART_RS485_CONF_DL0_EN = 0x2 + // Position of DL1_EN field. + UART_RS485_CONF_DL1_EN_Pos = 0x2 + // Bit mask of DL1_EN field. + UART_RS485_CONF_DL1_EN_Msk = 0x4 + // Bit DL1_EN. + UART_RS485_CONF_DL1_EN = 0x4 + // Position of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Pos = 0x3 + // Bit mask of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Msk = 0x8 + // Bit RS485TX_RX_EN. + UART_RS485_CONF_RS485TX_RX_EN = 0x8 + // Position of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Pos = 0x4 + // Bit mask of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Msk = 0x10 + // Bit RS485RXBY_TX_EN. + UART_RS485_CONF_RS485RXBY_TX_EN = 0x10 + // Position of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Pos = 0x5 + // Bit mask of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Msk = 0x20 + // Bit RS485_RX_DLY_NUM. + UART_RS485_CONF_RS485_RX_DLY_NUM = 0x20 + // Position of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Pos = 0x6 + // Bit mask of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Msk = 0x3c0 + + // AT_CMD_PRECNT: Pre-sequence timing configuration + // Position of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Pos = 0x0 + // Bit mask of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Msk = 0xffff + + // AT_CMD_POSTCNT: Post-sequence timing configuration + // Position of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Pos = 0x0 + // Bit mask of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Msk = 0xffff + + // AT_CMD_GAPTOUT: Timeout configuration + // Position of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Pos = 0x0 + // Bit mask of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Msk = 0xffff + + // AT_CMD_CHAR: AT escape sequence detection configuration + // Position of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Pos = 0x0 + // Bit mask of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Msk = 0xff + // Position of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Pos = 0x8 + // Bit mask of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Msk = 0xff00 + + // MEM_CONF: UART threshold and allocation configuration + // Position of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Pos = 0x1 + // Bit mask of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Msk = 0xe + // Position of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Pos = 0x4 + // Bit mask of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Msk = 0x70 + // Position of RX_FLOW_THRHD field. + UART_MEM_CONF_RX_FLOW_THRHD_Pos = 0x7 + // Bit mask of RX_FLOW_THRHD field. + UART_MEM_CONF_RX_FLOW_THRHD_Msk = 0xff80 + // Position of RX_TOUT_THRHD field. + UART_MEM_CONF_RX_TOUT_THRHD_Pos = 0x10 + // Bit mask of RX_TOUT_THRHD field. + UART_MEM_CONF_RX_TOUT_THRHD_Msk = 0x3ff0000 + // Position of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x1a + // Bit mask of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x4000000 + // Bit MEM_FORCE_PD. + UART_MEM_CONF_MEM_FORCE_PD = 0x4000000 + // Position of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1b + // Bit mask of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x8000000 + // Bit MEM_FORCE_PU. + UART_MEM_CONF_MEM_FORCE_PU = 0x8000000 + + // MEM_TX_STATUS: Tx-FIFO write and read offset address. + // Position of APB_TX_WADDR field. + UART_MEM_TX_STATUS_APB_TX_WADDR_Pos = 0x0 + // Bit mask of APB_TX_WADDR field. + UART_MEM_TX_STATUS_APB_TX_WADDR_Msk = 0x3ff + // Position of TX_RADDR field. + UART_MEM_TX_STATUS_TX_RADDR_Pos = 0xb + // Bit mask of TX_RADDR field. + UART_MEM_TX_STATUS_TX_RADDR_Msk = 0x1ff800 + + // MEM_RX_STATUS: Rx-FIFO write and read offset address. + // Position of APB_RX_RADDR field. + UART_MEM_RX_STATUS_APB_RX_RADDR_Pos = 0x0 + // Bit mask of APB_RX_RADDR field. + UART_MEM_RX_STATUS_APB_RX_RADDR_Msk = 0x3ff + // Position of RX_WADDR field. + UART_MEM_RX_STATUS_RX_WADDR_Pos = 0xb + // Bit mask of RX_WADDR field. + UART_MEM_RX_STATUS_RX_WADDR_Msk = 0x1ff800 + + // FSM_STATUS: UART transmit and receive status. + // Position of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0 + // Bit mask of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf + // Position of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4 + // Bit mask of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0 + + // POSPULSE: Autobaud high pulse register + // Position of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Msk = 0xfff + + // NEGPULSE: Autobaud low pulse register + // Position of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Msk = 0xfff + + // CLK_CONF: UART core clock configuration + // Position of SCLK_DIV_B field. + UART_CLK_CONF_SCLK_DIV_B_Pos = 0x0 + // Bit mask of SCLK_DIV_B field. + UART_CLK_CONF_SCLK_DIV_B_Msk = 0x3f + // Position of SCLK_DIV_A field. + UART_CLK_CONF_SCLK_DIV_A_Pos = 0x6 + // Bit mask of SCLK_DIV_A field. + UART_CLK_CONF_SCLK_DIV_A_Msk = 0xfc0 + // Position of SCLK_DIV_NUM field. + UART_CLK_CONF_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of SCLK_DIV_NUM field. + UART_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff000 + // Position of SCLK_SEL field. + UART_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + UART_CLK_CONF_SCLK_SEL_Msk = 0x300000 + // Position of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Pos = 0x16 + // Bit mask of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Msk = 0x400000 + // Bit SCLK_EN. + UART_CLK_CONF_SCLK_EN = 0x400000 + // Position of RST_CORE field. + UART_CLK_CONF_RST_CORE_Pos = 0x17 + // Bit mask of RST_CORE field. + UART_CLK_CONF_RST_CORE_Msk = 0x800000 + // Bit RST_CORE. + UART_CLK_CONF_RST_CORE = 0x800000 + // Position of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Pos = 0x18 + // Bit mask of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Msk = 0x1000000 + // Bit TX_SCLK_EN. + UART_CLK_CONF_TX_SCLK_EN = 0x1000000 + // Position of RX_SCLK_EN field. + UART_CLK_CONF_RX_SCLK_EN_Pos = 0x19 + // Bit mask of RX_SCLK_EN field. + UART_CLK_CONF_RX_SCLK_EN_Msk = 0x2000000 + // Bit RX_SCLK_EN. + UART_CLK_CONF_RX_SCLK_EN = 0x2000000 + // Position of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Pos = 0x1a + // Bit mask of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Msk = 0x4000000 + // Bit TX_RST_CORE. + UART_CLK_CONF_TX_RST_CORE = 0x4000000 + // Position of RX_RST_CORE field. + UART_CLK_CONF_RX_RST_CORE_Pos = 0x1b + // Bit mask of RX_RST_CORE field. + UART_CLK_CONF_RX_RST_CORE_Msk = 0x8000000 + // Bit RX_RST_CORE. + UART_CLK_CONF_RX_RST_CORE = 0x8000000 + + // DATE: UART Version register + // Position of DATE field. + UART_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UART_DATE_DATE_Msk = 0xffffffff + + // ID: UART ID register + // Position of ID field. + UART_ID_ID_Pos = 0x0 + // Bit mask of ID field. + UART_ID_ID_Msk = 0x3fffffff + // Position of HIGH_SPEED field. + UART_ID_HIGH_SPEED_Pos = 0x1e + // Bit mask of HIGH_SPEED field. + UART_ID_HIGH_SPEED_Msk = 0x40000000 + // Bit HIGH_SPEED. + UART_ID_HIGH_SPEED = 0x40000000 + // Position of REG_UPDATE field. + UART_ID_REG_UPDATE_Pos = 0x1f + // Bit mask of REG_UPDATE field. + UART_ID_REG_UPDATE_Msk = 0x80000000 + // Bit REG_UPDATE. + UART_ID_REG_UPDATE = 0x80000000 +) + +// Constants for UHCI0: Universal Host Controller Interface 0 +const ( + // CONF0: a + // Position of TX_RST field. + UHCI_CONF0_TX_RST_Pos = 0x0 + // Bit mask of TX_RST field. + UHCI_CONF0_TX_RST_Msk = 0x1 + // Bit TX_RST. + UHCI_CONF0_TX_RST = 0x1 + // Position of RX_RST field. + UHCI_CONF0_RX_RST_Pos = 0x1 + // Bit mask of RX_RST field. + UHCI_CONF0_RX_RST_Msk = 0x2 + // Bit RX_RST. + UHCI_CONF0_RX_RST = 0x2 + // Position of UART0_CE field. + UHCI_CONF0_UART0_CE_Pos = 0x2 + // Bit mask of UART0_CE field. + UHCI_CONF0_UART0_CE_Msk = 0x4 + // Bit UART0_CE. + UHCI_CONF0_UART0_CE = 0x4 + // Position of UART1_CE field. + UHCI_CONF0_UART1_CE_Pos = 0x3 + // Bit mask of UART1_CE field. + UHCI_CONF0_UART1_CE_Msk = 0x8 + // Bit UART1_CE. + UHCI_CONF0_UART1_CE = 0x8 + // Position of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Pos = 0x5 + // Bit mask of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Msk = 0x20 + // Bit SEPER_EN. + UHCI_CONF0_SEPER_EN = 0x20 + // Position of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Pos = 0x6 + // Bit mask of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Msk = 0x40 + // Bit HEAD_EN. + UHCI_CONF0_HEAD_EN = 0x40 + // Position of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Pos = 0x7 + // Bit mask of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Msk = 0x80 + // Bit CRC_REC_EN. + UHCI_CONF0_CRC_REC_EN = 0x80 + // Position of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Pos = 0x8 + // Bit mask of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Msk = 0x100 + // Bit UART_IDLE_EOF_EN. + UHCI_CONF0_UART_IDLE_EOF_EN = 0x100 + // Position of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Pos = 0x9 + // Bit mask of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Msk = 0x200 + // Bit LEN_EOF_EN. + UHCI_CONF0_LEN_EOF_EN = 0x200 + // Position of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Pos = 0xa + // Bit mask of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Msk = 0x400 + // Bit ENCODE_CRC_EN. + UHCI_CONF0_ENCODE_CRC_EN = 0x400 + // Position of CLK_EN field. + UHCI_CONF0_CLK_EN_Pos = 0xb + // Bit mask of CLK_EN field. + UHCI_CONF0_CLK_EN_Msk = 0x800 + // Bit CLK_EN. + UHCI_CONF0_CLK_EN = 0x800 + // Position of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Pos = 0xc + // Bit mask of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Msk = 0x1000 + // Bit UART_RX_BRK_EOF_EN. + UHCI_CONF0_UART_RX_BRK_EOF_EN = 0x1000 + + // INT_RAW: a + // Position of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Pos = 0x0 + // Bit mask of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Msk = 0x1 + // Bit RX_START_INT_RAW. + UHCI_INT_RAW_RX_START_INT_RAW = 0x1 + // Position of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Pos = 0x1 + // Bit mask of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Msk = 0x2 + // Bit TX_START_INT_RAW. + UHCI_INT_RAW_TX_START_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + UHCI_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + UHCI_INT_RAW_TX_HUNG_INT_RAW = 0x8 + // Position of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW = 0x10 + // Position of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW = 0x20 + // Position of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x6 + // Bit mask of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x40 + // Bit OUT_EOF_INT_RAW. + UHCI_INT_RAW_OUT_EOF_INT_RAW = 0x40 + // Position of APP_CTRL0_INT_RAW field. + UHCI_INT_RAW_APP_CTRL0_INT_RAW_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_RAW field. + UHCI_INT_RAW_APP_CTRL0_INT_RAW_Msk = 0x80 + // Bit APP_CTRL0_INT_RAW. + UHCI_INT_RAW_APP_CTRL0_INT_RAW = 0x80 + // Position of APP_CTRL1_INT_RAW field. + UHCI_INT_RAW_APP_CTRL1_INT_RAW_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_RAW field. + UHCI_INT_RAW_APP_CTRL1_INT_RAW_Msk = 0x100 + // Bit APP_CTRL1_INT_RAW. + UHCI_INT_RAW_APP_CTRL1_INT_RAW = 0x100 + + // INT_ST: a + // Position of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Pos = 0x0 + // Bit mask of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Msk = 0x1 + // Bit RX_START_INT_ST. + UHCI_INT_ST_RX_START_INT_ST = 0x1 + // Position of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Pos = 0x1 + // Bit mask of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Msk = 0x2 + // Bit TX_START_INT_ST. + UHCI_INT_ST_TX_START_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + UHCI_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + UHCI_INT_ST_TX_HUNG_INT_ST = 0x8 + // Position of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_ST. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST = 0x10 + // Position of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_ST. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST = 0x20 + // Position of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_ST. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST = 0x40 + // Position of APP_CTRL0_INT_ST field. + UHCI_INT_ST_APP_CTRL0_INT_ST_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_ST field. + UHCI_INT_ST_APP_CTRL0_INT_ST_Msk = 0x80 + // Bit APP_CTRL0_INT_ST. + UHCI_INT_ST_APP_CTRL0_INT_ST = 0x80 + // Position of APP_CTRL1_INT_ST field. + UHCI_INT_ST_APP_CTRL1_INT_ST_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_ST field. + UHCI_INT_ST_APP_CTRL1_INT_ST_Msk = 0x100 + // Bit APP_CTRL1_INT_ST. + UHCI_INT_ST_APP_CTRL1_INT_ST = 0x100 + + // INT_ENA: a + // Position of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Pos = 0x0 + // Bit mask of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Msk = 0x1 + // Bit RX_START_INT_ENA. + UHCI_INT_ENA_RX_START_INT_ENA = 0x1 + // Position of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Pos = 0x1 + // Bit mask of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Msk = 0x2 + // Bit TX_START_INT_ENA. + UHCI_INT_ENA_TX_START_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + UHCI_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + UHCI_INT_ENA_TX_HUNG_INT_ENA = 0x8 + // Position of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA = 0x10 + // Position of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA = 0x20 + // Position of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_ENA. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA = 0x40 + // Position of APP_CTRL0_INT_ENA field. + UHCI_INT_ENA_APP_CTRL0_INT_ENA_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_ENA field. + UHCI_INT_ENA_APP_CTRL0_INT_ENA_Msk = 0x80 + // Bit APP_CTRL0_INT_ENA. + UHCI_INT_ENA_APP_CTRL0_INT_ENA = 0x80 + // Position of APP_CTRL1_INT_ENA field. + UHCI_INT_ENA_APP_CTRL1_INT_ENA_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_ENA field. + UHCI_INT_ENA_APP_CTRL1_INT_ENA_Msk = 0x100 + // Bit APP_CTRL1_INT_ENA. + UHCI_INT_ENA_APP_CTRL1_INT_ENA = 0x100 + + // INT_CLR: a + // Position of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Pos = 0x0 + // Bit mask of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Msk = 0x1 + // Bit RX_START_INT_CLR. + UHCI_INT_CLR_RX_START_INT_CLR = 0x1 + // Position of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Pos = 0x1 + // Bit mask of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Msk = 0x2 + // Bit TX_START_INT_CLR. + UHCI_INT_CLR_TX_START_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + UHCI_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + UHCI_INT_CLR_TX_HUNG_INT_CLR = 0x8 + // Position of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR = 0x10 + // Position of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR = 0x20 + // Position of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_CLR. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR = 0x40 + // Position of APP_CTRL0_INT_CLR field. + UHCI_INT_CLR_APP_CTRL0_INT_CLR_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_CLR field. + UHCI_INT_CLR_APP_CTRL0_INT_CLR_Msk = 0x80 + // Bit APP_CTRL0_INT_CLR. + UHCI_INT_CLR_APP_CTRL0_INT_CLR = 0x80 + // Position of APP_CTRL1_INT_CLR field. + UHCI_INT_CLR_APP_CTRL1_INT_CLR_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_CLR field. + UHCI_INT_CLR_APP_CTRL1_INT_CLR_Msk = 0x100 + // Bit APP_CTRL1_INT_CLR. + UHCI_INT_CLR_APP_CTRL1_INT_CLR = 0x100 + + // CONF1: a + // Position of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Pos = 0x0 + // Bit mask of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Msk = 0x1 + // Bit CHECK_SUM_EN. + UHCI_CONF1_CHECK_SUM_EN = 0x1 + // Position of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Pos = 0x1 + // Bit mask of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Msk = 0x2 + // Bit CHECK_SEQ_EN. + UHCI_CONF1_CHECK_SEQ_EN = 0x2 + // Position of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Pos = 0x2 + // Bit mask of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Msk = 0x4 + // Bit CRC_DISABLE. + UHCI_CONF1_CRC_DISABLE = 0x4 + // Position of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Pos = 0x3 + // Bit mask of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Msk = 0x8 + // Bit SAVE_HEAD. + UHCI_CONF1_SAVE_HEAD = 0x8 + // Position of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Pos = 0x4 + // Bit mask of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Msk = 0x10 + // Bit TX_CHECK_SUM_RE. + UHCI_CONF1_TX_CHECK_SUM_RE = 0x10 + // Position of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Pos = 0x5 + // Bit mask of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Msk = 0x20 + // Bit TX_ACK_NUM_RE. + UHCI_CONF1_TX_ACK_NUM_RE = 0x20 + // Position of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Pos = 0x7 + // Bit mask of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Msk = 0x80 + // Bit WAIT_SW_START. + UHCI_CONF1_WAIT_SW_START = 0x80 + // Position of SW_START field. + UHCI_CONF1_SW_START_Pos = 0x8 + // Bit mask of SW_START field. + UHCI_CONF1_SW_START_Msk = 0x100 + // Bit SW_START. + UHCI_CONF1_SW_START = 0x100 + + // STATE0: a + // Position of RX_ERR_CAUSE field. + UHCI_STATE0_RX_ERR_CAUSE_Pos = 0x0 + // Bit mask of RX_ERR_CAUSE field. + UHCI_STATE0_RX_ERR_CAUSE_Msk = 0x7 + // Position of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Pos = 0x3 + // Bit mask of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Msk = 0x38 + + // STATE1: a + // Position of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Pos = 0x0 + // Bit mask of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Msk = 0x7 + + // ESCAPE_CONF: a + // Position of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Pos = 0x0 + // Bit mask of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Msk = 0x1 + // Bit TX_C0_ESC_EN. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN = 0x1 + // Position of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Pos = 0x1 + // Bit mask of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Msk = 0x2 + // Bit TX_DB_ESC_EN. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN = 0x2 + // Position of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Pos = 0x2 + // Bit mask of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Msk = 0x4 + // Bit TX_11_ESC_EN. + UHCI_ESCAPE_CONF_TX_11_ESC_EN = 0x4 + // Position of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Pos = 0x3 + // Bit mask of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Msk = 0x8 + // Bit TX_13_ESC_EN. + UHCI_ESCAPE_CONF_TX_13_ESC_EN = 0x8 + // Position of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Pos = 0x4 + // Bit mask of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Msk = 0x10 + // Bit RX_C0_ESC_EN. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN = 0x10 + // Position of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Pos = 0x5 + // Bit mask of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Msk = 0x20 + // Bit RX_DB_ESC_EN. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN = 0x20 + // Position of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Pos = 0x6 + // Bit mask of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Msk = 0x40 + // Bit RX_11_ESC_EN. + UHCI_ESCAPE_CONF_RX_11_ESC_EN = 0x40 + // Position of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Pos = 0x7 + // Bit mask of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Msk = 0x80 + // Bit RX_13_ESC_EN. + UHCI_ESCAPE_CONF_RX_13_ESC_EN = 0x80 + + // HUNG_CONF: a + // Position of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Pos = 0x0 + // Bit mask of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Msk = 0xff + // Position of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit TXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA = 0x800 + // Position of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Pos = 0xc + // Bit mask of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Msk = 0xff000 + // Position of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Pos = 0x14 + // Bit mask of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Msk = 0x700000 + // Position of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Pos = 0x17 + // Bit mask of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Msk = 0x800000 + // Bit RXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA = 0x800000 + + // ACK_NUM: a + // Position of ACK_NUM field. + UHCI_ACK_NUM_ACK_NUM_Pos = 0x0 + // Bit mask of ACK_NUM field. + UHCI_ACK_NUM_ACK_NUM_Msk = 0x7 + // Position of LOAD field. + UHCI_ACK_NUM_LOAD_Pos = 0x3 + // Bit mask of LOAD field. + UHCI_ACK_NUM_LOAD_Msk = 0x8 + // Bit LOAD. + UHCI_ACK_NUM_LOAD = 0x8 + + // RX_HEAD: a + // Position of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Pos = 0x0 + // Bit mask of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Msk = 0xffffffff + + // QUICK_SENT: a + // Position of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Pos = 0x0 + // Bit mask of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Msk = 0x7 + // Position of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Pos = 0x3 + // Bit mask of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Msk = 0x8 + // Bit SINGLE_SEND_EN. + UHCI_QUICK_SENT_SINGLE_SEND_EN = 0x8 + // Position of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Pos = 0x4 + // Bit mask of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Msk = 0x70 + // Position of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Pos = 0x7 + // Bit mask of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Msk = 0x80 + // Bit ALWAYS_SEND_EN. + UHCI_QUICK_SENT_ALWAYS_SEND_EN = 0x80 + + // REG_Q0_WORD0: a + // Position of SEND_Q0_WORD0 field. + UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Pos = 0x0 + // Bit mask of SEND_Q0_WORD0 field. + UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Msk = 0xffffffff + + // REG_Q0_WORD1: a + // Position of SEND_Q0_WORD1 field. + UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Pos = 0x0 + // Bit mask of SEND_Q0_WORD1 field. + UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Msk = 0xffffffff + + // REG_Q1_WORD0: a + // Position of SEND_Q1_WORD0 field. + UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Pos = 0x0 + // Bit mask of SEND_Q1_WORD0 field. + UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Msk = 0xffffffff + + // REG_Q1_WORD1: a + // Position of SEND_Q1_WORD1 field. + UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Pos = 0x0 + // Bit mask of SEND_Q1_WORD1 field. + UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Msk = 0xffffffff + + // REG_Q2_WORD0: a + // Position of SEND_Q2_WORD0 field. + UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Pos = 0x0 + // Bit mask of SEND_Q2_WORD0 field. + UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Msk = 0xffffffff + + // REG_Q2_WORD1: a + // Position of SEND_Q2_WORD1 field. + UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Pos = 0x0 + // Bit mask of SEND_Q2_WORD1 field. + UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Msk = 0xffffffff + + // REG_Q3_WORD0: a + // Position of SEND_Q3_WORD0 field. + UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Pos = 0x0 + // Bit mask of SEND_Q3_WORD0 field. + UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Msk = 0xffffffff + + // REG_Q3_WORD1: a + // Position of SEND_Q3_WORD1 field. + UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Pos = 0x0 + // Bit mask of SEND_Q3_WORD1 field. + UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Msk = 0xffffffff + + // REG_Q4_WORD0: a + // Position of SEND_Q4_WORD0 field. + UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Pos = 0x0 + // Bit mask of SEND_Q4_WORD0 field. + UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Msk = 0xffffffff + + // REG_Q4_WORD1: a + // Position of SEND_Q4_WORD1 field. + UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Pos = 0x0 + // Bit mask of SEND_Q4_WORD1 field. + UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Msk = 0xffffffff + + // REG_Q5_WORD0: a + // Position of SEND_Q5_WORD0 field. + UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Pos = 0x0 + // Bit mask of SEND_Q5_WORD0 field. + UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Msk = 0xffffffff + + // REG_Q5_WORD1: a + // Position of SEND_Q5_WORD1 field. + UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Pos = 0x0 + // Bit mask of SEND_Q5_WORD1 field. + UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Msk = 0xffffffff + + // REG_Q6_WORD0: a + // Position of SEND_Q6_WORD0 field. + UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Pos = 0x0 + // Bit mask of SEND_Q6_WORD0 field. + UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Msk = 0xffffffff + + // REG_Q6_WORD1: a + // Position of SEND_Q6_WORD1 field. + UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Pos = 0x0 + // Bit mask of SEND_Q6_WORD1 field. + UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Msk = 0xffffffff + + // ESC_CONF0: a + // Position of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Pos = 0x0 + // Bit mask of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Msk = 0xff + // Position of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Pos = 0x8 + // Bit mask of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Msk = 0xff00 + // Position of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Pos = 0x10 + // Bit mask of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Msk = 0xff0000 + + // ESC_CONF1: a + // Position of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Pos = 0x0 + // Bit mask of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Msk = 0xff + // Position of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Msk = 0xff0000 + + // ESC_CONF2: a + // Position of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Pos = 0x0 + // Bit mask of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Msk = 0xff + // Position of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Msk = 0xff0000 + + // ESC_CONF3: a + // Position of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Pos = 0x0 + // Bit mask of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Msk = 0xff + // Position of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Msk = 0xff0000 + + // PKT_THRES: a + // Position of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Pos = 0x0 + // Bit mask of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Msk = 0x1fff + + // DATE: a + // Position of DATE field. + UHCI_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UHCI_DATE_DATE_Msk = 0xffffffff +) + +// Constants for USB_DEVICE: Full-speed USB Serial/JTAG Controller +const ( + // EP1: USB_DEVICE_EP1_REG. + // Position of RDWR_BYTE field. + USB_DEVICE_EP1_RDWR_BYTE_Pos = 0x0 + // Bit mask of RDWR_BYTE field. + USB_DEVICE_EP1_RDWR_BYTE_Msk = 0xff + + // EP1_CONF: USB_DEVICE_EP1_CONF_REG. + // Position of WR_DONE field. + USB_DEVICE_EP1_CONF_WR_DONE_Pos = 0x0 + // Bit mask of WR_DONE field. + USB_DEVICE_EP1_CONF_WR_DONE_Msk = 0x1 + // Bit WR_DONE. + USB_DEVICE_EP1_CONF_WR_DONE = 0x1 + // Position of SERIAL_IN_EP_DATA_FREE field. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE_Pos = 0x1 + // Bit mask of SERIAL_IN_EP_DATA_FREE field. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE_Msk = 0x2 + // Bit SERIAL_IN_EP_DATA_FREE. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE = 0x2 + // Position of SERIAL_OUT_EP_DATA_AVAIL field. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL_Pos = 0x2 + // Bit mask of SERIAL_OUT_EP_DATA_AVAIL field. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL_Msk = 0x4 + // Bit SERIAL_OUT_EP_DATA_AVAIL. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL = 0x4 + + // INT_RAW: USB_DEVICE_INT_RAW_REG. + // Position of JTAG_IN_FLUSH_INT_RAW field. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_RAW field. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_RAW. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW = 0x1 + // Position of SOF_INT_RAW field. + USB_DEVICE_INT_RAW_SOF_INT_RAW_Pos = 0x1 + // Bit mask of SOF_INT_RAW field. + USB_DEVICE_INT_RAW_SOF_INT_RAW_Msk = 0x2 + // Bit SOF_INT_RAW. + USB_DEVICE_INT_RAW_SOF_INT_RAW = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_RAW. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW = 0x4 + // Position of SERIAL_IN_EMPTY_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_RAW. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW = 0x8 + // Position of PID_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW_Pos = 0x4 + // Bit mask of PID_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW_Msk = 0x10 + // Bit PID_ERR_INT_RAW. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW = 0x10 + // Position of CRC5_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW_Msk = 0x20 + // Bit CRC5_ERR_INT_RAW. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW = 0x20 + // Position of CRC16_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW_Msk = 0x40 + // Bit CRC16_ERR_INT_RAW. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW = 0x40 + // Position of STUFF_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW_Msk = 0x80 + // Bit STUFF_ERR_INT_RAW. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_RAW field. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_RAW field. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_RAW. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW = 0x100 + // Position of USB_BUS_RESET_INT_RAW field. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_RAW field. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW_Msk = 0x200 + // Bit USB_BUS_RESET_INT_RAW. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_RAW. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_RAW. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW = 0x800 + + // INT_ST: USB_DEVICE_INT_ST_REG. + // Position of JTAG_IN_FLUSH_INT_ST field. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_ST field. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_ST. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST = 0x1 + // Position of SOF_INT_ST field. + USB_DEVICE_INT_ST_SOF_INT_ST_Pos = 0x1 + // Bit mask of SOF_INT_ST field. + USB_DEVICE_INT_ST_SOF_INT_ST_Msk = 0x2 + // Bit SOF_INT_ST. + USB_DEVICE_INT_ST_SOF_INT_ST = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_ST. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST = 0x4 + // Position of SERIAL_IN_EMPTY_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_ST. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST = 0x8 + // Position of PID_ERR_INT_ST field. + USB_DEVICE_INT_ST_PID_ERR_INT_ST_Pos = 0x4 + // Bit mask of PID_ERR_INT_ST field. + USB_DEVICE_INT_ST_PID_ERR_INT_ST_Msk = 0x10 + // Bit PID_ERR_INT_ST. + USB_DEVICE_INT_ST_PID_ERR_INT_ST = 0x10 + // Position of CRC5_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST_Msk = 0x20 + // Bit CRC5_ERR_INT_ST. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST = 0x20 + // Position of CRC16_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST_Msk = 0x40 + // Bit CRC16_ERR_INT_ST. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST = 0x40 + // Position of STUFF_ERR_INT_ST field. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_ST field. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST_Msk = 0x80 + // Bit STUFF_ERR_INT_ST. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_ST field. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_ST field. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_ST. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST = 0x100 + // Position of USB_BUS_RESET_INT_ST field. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_ST field. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST_Msk = 0x200 + // Bit USB_BUS_RESET_INT_ST. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_ST. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_ST. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST = 0x800 + + // INT_ENA: USB_DEVICE_INT_ENA_REG. + // Position of JTAG_IN_FLUSH_INT_ENA field. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_ENA field. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_ENA. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA = 0x1 + // Position of SOF_INT_ENA field. + USB_DEVICE_INT_ENA_SOF_INT_ENA_Pos = 0x1 + // Bit mask of SOF_INT_ENA field. + USB_DEVICE_INT_ENA_SOF_INT_ENA_Msk = 0x2 + // Bit SOF_INT_ENA. + USB_DEVICE_INT_ENA_SOF_INT_ENA = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_ENA. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA = 0x4 + // Position of SERIAL_IN_EMPTY_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_ENA. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA = 0x8 + // Position of PID_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA_Pos = 0x4 + // Bit mask of PID_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA_Msk = 0x10 + // Bit PID_ERR_INT_ENA. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA = 0x10 + // Position of CRC5_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA_Msk = 0x20 + // Bit CRC5_ERR_INT_ENA. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA = 0x20 + // Position of CRC16_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA_Msk = 0x40 + // Bit CRC16_ERR_INT_ENA. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA = 0x40 + // Position of STUFF_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA_Msk = 0x80 + // Bit STUFF_ERR_INT_ENA. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_ENA field. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_ENA field. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_ENA. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA = 0x100 + // Position of USB_BUS_RESET_INT_ENA field. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_ENA field. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA_Msk = 0x200 + // Bit USB_BUS_RESET_INT_ENA. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_ENA. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_ENA. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA = 0x800 + + // INT_CLR: USB_DEVICE_INT_CLR_REG. + // Position of JTAG_IN_FLUSH_INT_CLR field. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_CLR field. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_CLR. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR = 0x1 + // Position of SOF_INT_CLR field. + USB_DEVICE_INT_CLR_SOF_INT_CLR_Pos = 0x1 + // Bit mask of SOF_INT_CLR field. + USB_DEVICE_INT_CLR_SOF_INT_CLR_Msk = 0x2 + // Bit SOF_INT_CLR. + USB_DEVICE_INT_CLR_SOF_INT_CLR = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_CLR. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR = 0x4 + // Position of SERIAL_IN_EMPTY_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_CLR. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR = 0x8 + // Position of PID_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR_Pos = 0x4 + // Bit mask of PID_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR_Msk = 0x10 + // Bit PID_ERR_INT_CLR. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR = 0x10 + // Position of CRC5_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR_Msk = 0x20 + // Bit CRC5_ERR_INT_CLR. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR = 0x20 + // Position of CRC16_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR_Msk = 0x40 + // Bit CRC16_ERR_INT_CLR. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR = 0x40 + // Position of STUFF_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR_Msk = 0x80 + // Bit STUFF_ERR_INT_CLR. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_CLR field. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_CLR field. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_CLR. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR = 0x100 + // Position of USB_BUS_RESET_INT_CLR field. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_CLR field. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR_Msk = 0x200 + // Bit USB_BUS_RESET_INT_CLR. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_CLR. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_CLR. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR = 0x800 + + // CONF0: USB_DEVICE_CONF0_REG. + // Position of PHY_SEL field. + USB_DEVICE_CONF0_PHY_SEL_Pos = 0x0 + // Bit mask of PHY_SEL field. + USB_DEVICE_CONF0_PHY_SEL_Msk = 0x1 + // Bit PHY_SEL. + USB_DEVICE_CONF0_PHY_SEL = 0x1 + // Position of EXCHG_PINS_OVERRIDE field. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE_Pos = 0x1 + // Bit mask of EXCHG_PINS_OVERRIDE field. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE_Msk = 0x2 + // Bit EXCHG_PINS_OVERRIDE. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE = 0x2 + // Position of EXCHG_PINS field. + USB_DEVICE_CONF0_EXCHG_PINS_Pos = 0x2 + // Bit mask of EXCHG_PINS field. + USB_DEVICE_CONF0_EXCHG_PINS_Msk = 0x4 + // Bit EXCHG_PINS. + USB_DEVICE_CONF0_EXCHG_PINS = 0x4 + // Position of VREFH field. + USB_DEVICE_CONF0_VREFH_Pos = 0x3 + // Bit mask of VREFH field. + USB_DEVICE_CONF0_VREFH_Msk = 0x18 + // Position of VREFL field. + USB_DEVICE_CONF0_VREFL_Pos = 0x5 + // Bit mask of VREFL field. + USB_DEVICE_CONF0_VREFL_Msk = 0x60 + // Position of VREF_OVERRIDE field. + USB_DEVICE_CONF0_VREF_OVERRIDE_Pos = 0x7 + // Bit mask of VREF_OVERRIDE field. + USB_DEVICE_CONF0_VREF_OVERRIDE_Msk = 0x80 + // Bit VREF_OVERRIDE. + USB_DEVICE_CONF0_VREF_OVERRIDE = 0x80 + // Position of PAD_PULL_OVERRIDE field. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE_Pos = 0x8 + // Bit mask of PAD_PULL_OVERRIDE field. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE_Msk = 0x100 + // Bit PAD_PULL_OVERRIDE. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE = 0x100 + // Position of DP_PULLUP field. + USB_DEVICE_CONF0_DP_PULLUP_Pos = 0x9 + // Bit mask of DP_PULLUP field. + USB_DEVICE_CONF0_DP_PULLUP_Msk = 0x200 + // Bit DP_PULLUP. + USB_DEVICE_CONF0_DP_PULLUP = 0x200 + // Position of DP_PULLDOWN field. + USB_DEVICE_CONF0_DP_PULLDOWN_Pos = 0xa + // Bit mask of DP_PULLDOWN field. + USB_DEVICE_CONF0_DP_PULLDOWN_Msk = 0x400 + // Bit DP_PULLDOWN. + USB_DEVICE_CONF0_DP_PULLDOWN = 0x400 + // Position of DM_PULLUP field. + USB_DEVICE_CONF0_DM_PULLUP_Pos = 0xb + // Bit mask of DM_PULLUP field. + USB_DEVICE_CONF0_DM_PULLUP_Msk = 0x800 + // Bit DM_PULLUP. + USB_DEVICE_CONF0_DM_PULLUP = 0x800 + // Position of DM_PULLDOWN field. + USB_DEVICE_CONF0_DM_PULLDOWN_Pos = 0xc + // Bit mask of DM_PULLDOWN field. + USB_DEVICE_CONF0_DM_PULLDOWN_Msk = 0x1000 + // Bit DM_PULLDOWN. + USB_DEVICE_CONF0_DM_PULLDOWN = 0x1000 + // Position of PULLUP_VALUE field. + USB_DEVICE_CONF0_PULLUP_VALUE_Pos = 0xd + // Bit mask of PULLUP_VALUE field. + USB_DEVICE_CONF0_PULLUP_VALUE_Msk = 0x2000 + // Bit PULLUP_VALUE. + USB_DEVICE_CONF0_PULLUP_VALUE = 0x2000 + // Position of USB_PAD_ENABLE field. + USB_DEVICE_CONF0_USB_PAD_ENABLE_Pos = 0xe + // Bit mask of USB_PAD_ENABLE field. + USB_DEVICE_CONF0_USB_PAD_ENABLE_Msk = 0x4000 + // Bit USB_PAD_ENABLE. + USB_DEVICE_CONF0_USB_PAD_ENABLE = 0x4000 + + // TEST: USB_DEVICE_TEST_REG. + // Position of ENABLE field. + USB_DEVICE_TEST_ENABLE_Pos = 0x0 + // Bit mask of ENABLE field. + USB_DEVICE_TEST_ENABLE_Msk = 0x1 + // Bit ENABLE. + USB_DEVICE_TEST_ENABLE = 0x1 + // Position of USB_OE field. + USB_DEVICE_TEST_USB_OE_Pos = 0x1 + // Bit mask of USB_OE field. + USB_DEVICE_TEST_USB_OE_Msk = 0x2 + // Bit USB_OE. + USB_DEVICE_TEST_USB_OE = 0x2 + // Position of TX_DP field. + USB_DEVICE_TEST_TX_DP_Pos = 0x2 + // Bit mask of TX_DP field. + USB_DEVICE_TEST_TX_DP_Msk = 0x4 + // Bit TX_DP. + USB_DEVICE_TEST_TX_DP = 0x4 + // Position of TX_DM field. + USB_DEVICE_TEST_TX_DM_Pos = 0x3 + // Bit mask of TX_DM field. + USB_DEVICE_TEST_TX_DM_Msk = 0x8 + // Bit TX_DM. + USB_DEVICE_TEST_TX_DM = 0x8 + + // JFIFO_ST: USB_DEVICE_JFIFO_ST_REG. + // Position of IN_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_IN_FIFO_CNT_Pos = 0x0 + // Bit mask of IN_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_IN_FIFO_CNT_Msk = 0x3 + // Position of IN_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY_Pos = 0x2 + // Bit mask of IN_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY_Msk = 0x4 + // Bit IN_FIFO_EMPTY. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY = 0x4 + // Position of IN_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL_Pos = 0x3 + // Bit mask of IN_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL_Msk = 0x8 + // Bit IN_FIFO_FULL. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL = 0x8 + // Position of OUT_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_CNT_Pos = 0x4 + // Bit mask of OUT_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_CNT_Msk = 0x30 + // Position of OUT_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY_Pos = 0x6 + // Bit mask of OUT_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY_Msk = 0x40 + // Bit OUT_FIFO_EMPTY. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY = 0x40 + // Position of OUT_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL_Pos = 0x7 + // Bit mask of OUT_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL_Msk = 0x80 + // Bit OUT_FIFO_FULL. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL = 0x80 + // Position of IN_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET_Pos = 0x8 + // Bit mask of IN_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET_Msk = 0x100 + // Bit IN_FIFO_RESET. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET = 0x100 + // Position of OUT_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET_Pos = 0x9 + // Bit mask of OUT_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET_Msk = 0x200 + // Bit OUT_FIFO_RESET. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET = 0x200 + + // FRAM_NUM: USB_DEVICE_FRAM_NUM_REG. + // Position of SOF_FRAME_INDEX field. + USB_DEVICE_FRAM_NUM_SOF_FRAME_INDEX_Pos = 0x0 + // Bit mask of SOF_FRAME_INDEX field. + USB_DEVICE_FRAM_NUM_SOF_FRAME_INDEX_Msk = 0x7ff + + // IN_EP0_ST: USB_DEVICE_IN_EP0_ST_REG. + // Position of IN_EP0_STATE field. + USB_DEVICE_IN_EP0_ST_IN_EP0_STATE_Pos = 0x0 + // Bit mask of IN_EP0_STATE field. + USB_DEVICE_IN_EP0_ST_IN_EP0_STATE_Msk = 0x3 + // Position of IN_EP0_WR_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP0_WR_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_WR_ADDR_Msk = 0x1fc + // Position of IN_EP0_RD_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP0_RD_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_RD_ADDR_Msk = 0xfe00 + + // IN_EP1_ST: USB_DEVICE_IN_EP1_ST_REG. + // Position of IN_EP1_STATE field. + USB_DEVICE_IN_EP1_ST_IN_EP1_STATE_Pos = 0x0 + // Bit mask of IN_EP1_STATE field. + USB_DEVICE_IN_EP1_ST_IN_EP1_STATE_Msk = 0x3 + // Position of IN_EP1_WR_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP1_WR_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_WR_ADDR_Msk = 0x1fc + // Position of IN_EP1_RD_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP1_RD_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_RD_ADDR_Msk = 0xfe00 + + // IN_EP2_ST: USB_DEVICE_IN_EP2_ST_REG. + // Position of IN_EP2_STATE field. + USB_DEVICE_IN_EP2_ST_IN_EP2_STATE_Pos = 0x0 + // Bit mask of IN_EP2_STATE field. + USB_DEVICE_IN_EP2_ST_IN_EP2_STATE_Msk = 0x3 + // Position of IN_EP2_WR_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP2_WR_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_WR_ADDR_Msk = 0x1fc + // Position of IN_EP2_RD_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP2_RD_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_RD_ADDR_Msk = 0xfe00 + + // IN_EP3_ST: USB_DEVICE_IN_EP3_ST_REG. + // Position of IN_EP3_STATE field. + USB_DEVICE_IN_EP3_ST_IN_EP3_STATE_Pos = 0x0 + // Bit mask of IN_EP3_STATE field. + USB_DEVICE_IN_EP3_ST_IN_EP3_STATE_Msk = 0x3 + // Position of IN_EP3_WR_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP3_WR_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_WR_ADDR_Msk = 0x1fc + // Position of IN_EP3_RD_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP3_RD_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_RD_ADDR_Msk = 0xfe00 + + // OUT_EP0_ST: USB_DEVICE_OUT_EP0_ST_REG. + // Position of OUT_EP0_STATE field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_STATE_Pos = 0x0 + // Bit mask of OUT_EP0_STATE field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_STATE_Msk = 0x3 + // Position of OUT_EP0_WR_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP0_WR_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP0_RD_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP0_RD_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_RD_ADDR_Msk = 0xfe00 + + // OUT_EP1_ST: USB_DEVICE_OUT_EP1_ST_REG. + // Position of OUT_EP1_STATE field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_STATE_Pos = 0x0 + // Bit mask of OUT_EP1_STATE field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_STATE_Msk = 0x3 + // Position of OUT_EP1_WR_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP1_WR_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP1_RD_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP1_RD_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_RD_ADDR_Msk = 0xfe00 + // Position of OUT_EP1_REC_DATA_CNT field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_REC_DATA_CNT_Pos = 0x10 + // Bit mask of OUT_EP1_REC_DATA_CNT field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_REC_DATA_CNT_Msk = 0x7f0000 + + // OUT_EP2_ST: USB_DEVICE_OUT_EP2_ST_REG. + // Position of OUT_EP2_STATE field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_STATE_Pos = 0x0 + // Bit mask of OUT_EP2_STATE field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_STATE_Msk = 0x3 + // Position of OUT_EP2_WR_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP2_WR_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP2_RD_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP2_RD_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_RD_ADDR_Msk = 0xfe00 + + // MISC_CONF: USB_DEVICE_MISC_CONF_REG. + // Position of CLK_EN field. + USB_DEVICE_MISC_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + USB_DEVICE_MISC_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + USB_DEVICE_MISC_CONF_CLK_EN = 0x1 + + // MEM_CONF: USB_DEVICE_MEM_CONF_REG. + // Position of USB_MEM_PD field. + USB_DEVICE_MEM_CONF_USB_MEM_PD_Pos = 0x0 + // Bit mask of USB_MEM_PD field. + USB_DEVICE_MEM_CONF_USB_MEM_PD_Msk = 0x1 + // Bit USB_MEM_PD. + USB_DEVICE_MEM_CONF_USB_MEM_PD = 0x1 + // Position of USB_MEM_CLK_EN field. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN_Pos = 0x1 + // Bit mask of USB_MEM_CLK_EN field. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN_Msk = 0x2 + // Bit USB_MEM_CLK_EN. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN = 0x2 + + // DATE: USB_DEVICE_DATE_REG. + // Position of DATE field. + USB_DEVICE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + USB_DEVICE_DATE_DATE_Msk = 0xffffffff +) + +// Constants for XTS_AES: XTS-AES-128 Flash Encryption +const ( + // LINESIZE: XTS-AES line-size register + // Position of LINESIZE field. + XTS_AES_LINESIZE_LINESIZE_Pos = 0x0 + // Bit mask of LINESIZE field. + XTS_AES_LINESIZE_LINESIZE_Msk = 0x1 + // Bit LINESIZE. + XTS_AES_LINESIZE_LINESIZE = 0x1 + + // DESTINATION: XTS-AES destination register + // Position of DESTINATION field. + XTS_AES_DESTINATION_DESTINATION_Pos = 0x0 + // Bit mask of DESTINATION field. + XTS_AES_DESTINATION_DESTINATION_Msk = 0x1 + // Bit DESTINATION. + XTS_AES_DESTINATION_DESTINATION = 0x1 + + // PHYSICAL_ADDRESS: XTS-AES physical address register + // Position of PHYSICAL_ADDRESS field. + XTS_AES_PHYSICAL_ADDRESS_PHYSICAL_ADDRESS_Pos = 0x0 + // Bit mask of PHYSICAL_ADDRESS field. + XTS_AES_PHYSICAL_ADDRESS_PHYSICAL_ADDRESS_Msk = 0x3fffffff + + // TRIGGER: XTS-AES trigger register + // Position of TRIGGER field. + XTS_AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + XTS_AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + XTS_AES_TRIGGER_TRIGGER = 0x1 + + // RELEASE: XTS-AES release register + // Position of RELEASE field. + XTS_AES_RELEASE_RELEASE_Pos = 0x0 + // Bit mask of RELEASE field. + XTS_AES_RELEASE_RELEASE_Msk = 0x1 + // Bit RELEASE. + XTS_AES_RELEASE_RELEASE = 0x1 + + // DESTROY: XTS-AES destroy register + // Position of DESTROY field. + XTS_AES_DESTROY_DESTROY_Pos = 0x0 + // Bit mask of DESTROY field. + XTS_AES_DESTROY_DESTROY_Msk = 0x1 + // Bit DESTROY. + XTS_AES_DESTROY_DESTROY = 0x1 + + // STATE: XTS-AES status register + // Position of STATE field. + XTS_AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + XTS_AES_STATE_STATE_Msk = 0x3 + + // DATE: XTS-AES version control register + // Position of DATE field. + XTS_AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + XTS_AES_DATE_DATE_Msk = 0x3fffffff +) diff --git a/emb/device/esp/esp32c6.go b/emb/device/esp/esp32c6.go new file mode 100644 index 0000000..0542017 --- /dev/null +++ b/emb/device/esp/esp32c6.go @@ -0,0 +1,103000 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32c6.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32c6 + +/* +// 32-bit RISC-V MCU & 2.4 GHz Wi-Fi 6 & Bluetooth 5 (LE) & IEEE 802.15.4 +*/ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32-C6" + CPU = "RV32IMAC" + FPUPresent = false + NVICPrioBits = 0 +) + +// Interrupt numbers. +const ( + // Interrupt Controller (Core 0) + IRQ_WIFI_MAC = 0 + + // Interrupt Controller (Core 0) + IRQ_WIFI_MAC_NMI = 1 + + // Interrupt Controller (Core 0) + IRQ_WIFI_PWR = 2 + + // Interrupt Controller (Core 0) + IRQ_WIFI_BB = 3 + + // Interrupt Controller (Core 0) + IRQ_BT_MAC = 4 + + // Interrupt Controller (Core 0) + IRQ_BT_BB = 5 + + // Interrupt Controller (Core 0) + IRQ_BT_BB_NMI = 6 + + // Interrupt Controller (Core 0) + IRQ_LP_TIMER = 7 + + // Interrupt Controller (Core 0) + IRQ_COEX = 8 + + // Interrupt Controller (Core 0) + IRQ_BLE_TIMER = 9 + + // Interrupt Controller (Core 0) + IRQ_BLE_SEC = 10 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_MASTER = 11 + + // Interrupt Controller (Core 0) + IRQ_ZB_MAC = 12 + + // PMU Peripheral + IRQ_PMU = 13 + + // eFuse Controller + IRQ_EFUSE = 14 + + // Low-power Timer + IRQ_LP_RTC_TIMER = 15 + + // Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + IRQ_LP_UART = 16 + + // Low-power I2C (Inter-Integrated Circuit) Controller 0 + IRQ_LP_I2C = 17 + + // Low-power Watchdog Timer + IRQ_LP_WDT = 18 + + // LP_PERI Peripheral + IRQ_LP_PERI_TIMEOUT = 19 + + // Low-power Access Permission Management Controller + IRQ_LP_APM_M0 = 20 + + // Low-power Access Permission Management Controller + IRQ_LP_APM_M1 = 21 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR0 = 22 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR1 = 23 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR2 = 24 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR3 = 25 + + // Debug Assist + IRQ_ASSIST_DEBUG = 26 + + // RISC-V Trace Encoder + IRQ_TRACE = 27 + + // Interrupt Controller (Core 0) + IRQ_CACHE = 28 + + // Interrupt Controller (Core 0) + IRQ_CPU_PERI_TIMEOUT = 29 + + // General Purpose Input/Output + IRQ_GPIO = 30 + + // General Purpose Input/Output + IRQ_GPIO_NMI = 31 + + // PAU Peripheral + IRQ_PAU = 32 + + // High-Power System + IRQ_HP_PERI_TIMEOUT = 33 + + // High-Power System + IRQ_MODEM_PERI_TIMEOUT = 34 + + // HP_APM Peripheral + IRQ_HP_APM_M0 = 35 + + // HP_APM Peripheral + IRQ_HP_APM_M1 = 36 + + // HP_APM Peripheral + IRQ_HP_APM_M2 = 37 + + // HP_APM Peripheral + IRQ_HP_APM_M3 = 38 + + // Low-power Access Permission Management Controller + IRQ_LP_APM0 = 39 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_MSPI = 40 + + // I2S (Inter-IC Sound) Controller 0 + IRQ_I2S1 = 41 + + // Universal Host Controller Interface 0 + IRQ_UHCI0 = 42 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + IRQ_UART0 = 43 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + IRQ_UART1 = 44 + + // LED Control PWM (Pulse Width Modulation) + IRQ_LEDC = 45 + + // Two-Wire Automotive Interface + IRQ_TWAI0 = 46 + + // Two-Wire Automotive Interface + IRQ_TWAI1 = 47 + + // Full-speed USB Serial/JTAG Controller + IRQ_USB_DEVICE = 48 + + // Remote Control + IRQ_RMT = 49 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_EXT0 = 50 + + // Timer Group 0 + IRQ_TG0_T0_LEVEL = 51 + + // Timer Group 0 + IRQ_TG0_T1_LEVEL = 52 + + // Timer Group 0 + IRQ_TG0_WDT_LEVEL = 53 + + // Timer Group 1 + IRQ_TG1_T0_LEVEL = 54 + + // Timer Group 1 + IRQ_TG1_T1_LEVEL = 55 + + // Timer Group 1 + IRQ_TG1_WDT_LEVEL = 56 + + // System Timer + IRQ_SYSTIMER_TARGET0 = 57 + + // System Timer + IRQ_SYSTIMER_TARGET1 = 58 + + // System Timer + IRQ_SYSTIMER_TARGET2 = 59 + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + IRQ_APB_SARADC = 60 + + // Motor Control Pulse-Width Modulation 0 + IRQ_MCPWM0 = 61 + + // Pulse Count Controller + IRQ_PCNT = 62 + + // Parallel IO Controller + IRQ_PARL_IO = 63 + + // SLCHOST Peripheral + IRQ_SLC0 = 64 + + // SLCHOST Peripheral + IRQ_SLC1 = 65 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH0 = 66 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH1 = 67 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH2 = 68 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH0 = 69 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH1 = 70 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH2 = 71 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_SPI2 = 72 + + // AES (Advanced Encryption Standard) Accelerator + IRQ_AES = 73 + + // SHA (Secure Hash Algorithm) Accelerator + IRQ_SHA = 74 + + // RSA (Rivest Shamir Adleman) Accelerator + IRQ_RSA = 75 + + // ECC (ECC Hardware Accelerator) + IRQ_ECC = 76 + + // Highest interrupt number on this device. + IRQ_max = 76 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_WIFI_MAC: + callHandlers(IRQ_WIFI_MAC) + case IRQ_WIFI_MAC_NMI: + callHandlers(IRQ_WIFI_MAC_NMI) + case IRQ_WIFI_PWR: + callHandlers(IRQ_WIFI_PWR) + case IRQ_WIFI_BB: + callHandlers(IRQ_WIFI_BB) + case IRQ_BT_MAC: + callHandlers(IRQ_BT_MAC) + case IRQ_BT_BB: + callHandlers(IRQ_BT_BB) + case IRQ_BT_BB_NMI: + callHandlers(IRQ_BT_BB_NMI) + case IRQ_LP_TIMER: + callHandlers(IRQ_LP_TIMER) + case IRQ_COEX: + callHandlers(IRQ_COEX) + case IRQ_BLE_TIMER: + callHandlers(IRQ_BLE_TIMER) + case IRQ_BLE_SEC: + callHandlers(IRQ_BLE_SEC) + case IRQ_I2C_MASTER: + callHandlers(IRQ_I2C_MASTER) + case IRQ_ZB_MAC: + callHandlers(IRQ_ZB_MAC) + case IRQ_PMU: + callHandlers(IRQ_PMU) + case IRQ_EFUSE: + callHandlers(IRQ_EFUSE) + case IRQ_LP_RTC_TIMER: + callHandlers(IRQ_LP_RTC_TIMER) + case IRQ_LP_UART: + callHandlers(IRQ_LP_UART) + case IRQ_LP_I2C: + callHandlers(IRQ_LP_I2C) + case IRQ_LP_WDT: + callHandlers(IRQ_LP_WDT) + case IRQ_LP_PERI_TIMEOUT: + callHandlers(IRQ_LP_PERI_TIMEOUT) + case IRQ_LP_APM_M0: + callHandlers(IRQ_LP_APM_M0) + case IRQ_LP_APM_M1: + callHandlers(IRQ_LP_APM_M1) + case IRQ_FROM_CPU_INTR0: + callHandlers(IRQ_FROM_CPU_INTR0) + case IRQ_FROM_CPU_INTR1: + callHandlers(IRQ_FROM_CPU_INTR1) + case IRQ_FROM_CPU_INTR2: + callHandlers(IRQ_FROM_CPU_INTR2) + case IRQ_FROM_CPU_INTR3: + callHandlers(IRQ_FROM_CPU_INTR3) + case IRQ_ASSIST_DEBUG: + callHandlers(IRQ_ASSIST_DEBUG) + case IRQ_TRACE: + callHandlers(IRQ_TRACE) + case IRQ_CACHE: + callHandlers(IRQ_CACHE) + case IRQ_CPU_PERI_TIMEOUT: + callHandlers(IRQ_CPU_PERI_TIMEOUT) + case IRQ_GPIO: + callHandlers(IRQ_GPIO) + case IRQ_GPIO_NMI: + callHandlers(IRQ_GPIO_NMI) + case IRQ_PAU: + callHandlers(IRQ_PAU) + case IRQ_HP_PERI_TIMEOUT: + callHandlers(IRQ_HP_PERI_TIMEOUT) + case IRQ_MODEM_PERI_TIMEOUT: + callHandlers(IRQ_MODEM_PERI_TIMEOUT) + case IRQ_HP_APM_M0: + callHandlers(IRQ_HP_APM_M0) + case IRQ_HP_APM_M1: + callHandlers(IRQ_HP_APM_M1) + case IRQ_HP_APM_M2: + callHandlers(IRQ_HP_APM_M2) + case IRQ_HP_APM_M3: + callHandlers(IRQ_HP_APM_M3) + case IRQ_LP_APM0: + callHandlers(IRQ_LP_APM0) + case IRQ_MSPI: + callHandlers(IRQ_MSPI) + case IRQ_I2S1: + callHandlers(IRQ_I2S1) + case IRQ_UHCI0: + callHandlers(IRQ_UHCI0) + case IRQ_UART0: + callHandlers(IRQ_UART0) + case IRQ_UART1: + callHandlers(IRQ_UART1) + case IRQ_LEDC: + callHandlers(IRQ_LEDC) + case IRQ_TWAI0: + callHandlers(IRQ_TWAI0) + case IRQ_TWAI1: + callHandlers(IRQ_TWAI1) + case IRQ_USB_DEVICE: + callHandlers(IRQ_USB_DEVICE) + case IRQ_RMT: + callHandlers(IRQ_RMT) + case IRQ_I2C_EXT0: + callHandlers(IRQ_I2C_EXT0) + case IRQ_TG0_T0_LEVEL: + callHandlers(IRQ_TG0_T0_LEVEL) + case IRQ_TG0_T1_LEVEL: + callHandlers(IRQ_TG0_T1_LEVEL) + case IRQ_TG0_WDT_LEVEL: + callHandlers(IRQ_TG0_WDT_LEVEL) + case IRQ_TG1_T0_LEVEL: + callHandlers(IRQ_TG1_T0_LEVEL) + case IRQ_TG1_T1_LEVEL: + callHandlers(IRQ_TG1_T1_LEVEL) + case IRQ_TG1_WDT_LEVEL: + callHandlers(IRQ_TG1_WDT_LEVEL) + case IRQ_SYSTIMER_TARGET0: + callHandlers(IRQ_SYSTIMER_TARGET0) + case IRQ_SYSTIMER_TARGET1: + callHandlers(IRQ_SYSTIMER_TARGET1) + case IRQ_SYSTIMER_TARGET2: + callHandlers(IRQ_SYSTIMER_TARGET2) + case IRQ_APB_SARADC: + callHandlers(IRQ_APB_SARADC) + case IRQ_MCPWM0: + callHandlers(IRQ_MCPWM0) + case IRQ_PCNT: + callHandlers(IRQ_PCNT) + case IRQ_PARL_IO: + callHandlers(IRQ_PARL_IO) + case IRQ_SLC0: + callHandlers(IRQ_SLC0) + case IRQ_SLC1: + callHandlers(IRQ_SLC1) + case IRQ_DMA_IN_CH0: + callHandlers(IRQ_DMA_IN_CH0) + case IRQ_DMA_IN_CH1: + callHandlers(IRQ_DMA_IN_CH1) + case IRQ_DMA_IN_CH2: + callHandlers(IRQ_DMA_IN_CH2) + case IRQ_DMA_OUT_CH0: + callHandlers(IRQ_DMA_OUT_CH0) + case IRQ_DMA_OUT_CH1: + callHandlers(IRQ_DMA_OUT_CH1) + case IRQ_DMA_OUT_CH2: + callHandlers(IRQ_DMA_OUT_CH2) + case IRQ_SPI2: + callHandlers(IRQ_SPI2) + case IRQ_AES: + callHandlers(IRQ_AES) + case IRQ_SHA: + callHandlers(IRQ_SHA) + case IRQ_RSA: + callHandlers(IRQ_RSA) + case IRQ_ECC: + callHandlers(IRQ_ECC) + } +} + +// Peripherals. +var ( + // AES (Advanced Encryption Standard) Accelerator + AES = (*AES_Type)(unsafe.Pointer(uintptr(0x60088000))) + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + APB_SARADC = (*APB_SARADC_Type)(unsafe.Pointer(uintptr(0x6000e000))) + + // Debug Assist + ASSIST_DEBUG = (*ASSIST_DEBUG_Type)(unsafe.Pointer(uintptr(0x600c2000))) + + // Atomic Locker + ATOMIC = (*ATOMIC_Type)(unsafe.Pointer(uintptr(0x60011000))) + + // DMA (Direct Memory Access) Controller + DMA = (*DMA_Type)(unsafe.Pointer(uintptr(0x60080000))) + + // Digital Signature + DS = (*DS_Type)(unsafe.Pointer(uintptr(0x6008c000))) + + // ECC (ECC Hardware Accelerator) + ECC = (*ECC_Type)(unsafe.Pointer(uintptr(0x6008b000))) + + // eFuse Controller + EFUSE = (*EFUSE_Type)(unsafe.Pointer(uintptr(0x600b0800))) + + // External Memory + EXTMEM = (*EXTMEM_Type)(unsafe.Pointer(uintptr(0x600c8000))) + + // General Purpose Input/Output + GPIO = (*GPIO_Type)(unsafe.Pointer(uintptr(0x60091000))) + + // Sigma-Delta Modulation + GPIO_SD = (*GPIOSD_Type)(unsafe.Pointer(uintptr(0x60091f00))) + + // HINF Peripheral + HINF = (*HINF_Type)(unsafe.Pointer(uintptr(0x60016000))) + + // HMAC (Hash-based Message Authentication Code) Accelerator + HMAC = (*HMAC_Type)(unsafe.Pointer(uintptr(0x6008d000))) + + // HP_APM Peripheral + HP_APM = (*HP_APM_Type)(unsafe.Pointer(uintptr(0x60099000))) + + // High-Power System + HP_SYS = (*HP_SYS_Type)(unsafe.Pointer(uintptr(0x60095000))) + + // I2C (Inter-Integrated Circuit) Controller 0 + I2C0 = (*I2C_Type)(unsafe.Pointer(uintptr(0x60004000))) + + // I2S (Inter-IC Sound) Controller 0 + I2S0 = (*I2S_Type)(unsafe.Pointer(uintptr(0x6000c000))) + + // Interrupt Controller (Core 0) + INTERRUPT_CORE0 = (*INTMTX_CORE0_Type)(unsafe.Pointer(uintptr(0x60010000))) + + // INTPRI Peripheral + INTPRI = (*INTPRI_Type)(unsafe.Pointer(uintptr(0x600c5000))) + + // Input/Output Multiplexer + IO_MUX = (*IO_MUX_Type)(unsafe.Pointer(uintptr(0x60090000))) + + // LED Control PWM (Pulse Width Modulation) + LEDC = (*LEDC_Type)(unsafe.Pointer(uintptr(0x60007000))) + + // LP_PERI Peripheral + LP_PERI = (*LPPERI_Type)(unsafe.Pointer(uintptr(0x600b2800))) + + // LP_ANA Peripheral + LP_ANA = (*LP_ANA_Type)(unsafe.Pointer(uintptr(0x600b2c00))) + + // LP_AON Peripheral + LP_AON = (*LP_AON_Type)(unsafe.Pointer(uintptr(0x600b1000))) + + // Low-power Access Permission Management Controller + LP_APM = (*LP_APM_Type)(unsafe.Pointer(uintptr(0x600b3800))) + + // LP_APM0 Peripheral + LP_APM0 = (*LP_APM0_Type)(unsafe.Pointer(uintptr(0x60099800))) + + // LP_CLKRST Peripheral + LP_CLKRST = (*LP_CLKRST_Type)(unsafe.Pointer(uintptr(0x600b0400))) + + // Low-power I2C (Inter-Integrated Circuit) Controller 0 + LP_I2C0 = (*LP_I2C0_Type)(unsafe.Pointer(uintptr(0x600b1800))) + + // LP_I2C_ANA_MST Peripheral + LP_I2C_ANA_MST = (*LP_I2C_ANA_MST_Type)(unsafe.Pointer(uintptr(0x600b2400))) + + // LP_IO Peripheral + LP_IO = (*LP_IO_Type)(unsafe.Pointer(uintptr(0x600b2000))) + + // Low-power Trusted Execution Environment + LP_TEE = (*LP_TEE_Type)(unsafe.Pointer(uintptr(0x600b3400))) + + // Low-power Timer + LP_TIMER = (*LP_TIMER_Type)(unsafe.Pointer(uintptr(0x600b0c00))) + + // Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + LP_UART = (*LP_UART_Type)(unsafe.Pointer(uintptr(0x600b1400))) + + // Low-power Watchdog Timer + LP_WDT = (*LP_WDT_Type)(unsafe.Pointer(uintptr(0x600b1c00))) + + // Motor Control Pulse-Width Modulation 0 + MCPWM0 = (*MCPWM_Type)(unsafe.Pointer(uintptr(0x60014000))) + + // MEM_MONITOR Peripheral + MEM_MONITOR = (*MEM_MONITOR_Type)(unsafe.Pointer(uintptr(0x60092000))) + + // MODEM_LPCON Peripheral + MODEM_LPCON = (*MODEM_LPCON_Type)(unsafe.Pointer(uintptr(0x600af000))) + + // MODEM_SYSCON Peripheral + MODEM_SYSCON = (*MODEM_SYSCON_Type)(unsafe.Pointer(uintptr(0x600a9800))) + + // OTP_DEBUG Peripheral + OTP_DEBUG = (*OTP_DEBUG_Type)(unsafe.Pointer(uintptr(0x600b3c00))) + + // Parallel IO Controller + PARL_IO = (*PARL_IO_Type)(unsafe.Pointer(uintptr(0x60015000))) + + // PAU Peripheral + PAU = (*PAU_Type)(unsafe.Pointer(uintptr(0x60093000))) + + // Pulse Count Controller + PCNT = (*PCNT_Type)(unsafe.Pointer(uintptr(0x60012000))) + + // PCR Peripheral + PCR = (*PCR_Type)(unsafe.Pointer(uintptr(0x60096000))) + + // PMU Peripheral + PMU = (*PMU_Type)(unsafe.Pointer(uintptr(0x600b0000))) + + // Remote Control + RMT = (*RMT_Type)(unsafe.Pointer(uintptr(0x60006000))) + + // Hardware Random Number Generator + RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x600b2800))) + + // RSA (Rivest Shamir Adleman) Accelerator + RSA = (*RSA_Type)(unsafe.Pointer(uintptr(0x6008a000))) + + // SHA (Secure Hash Algorithm) Accelerator + SHA = (*SHA_Type)(unsafe.Pointer(uintptr(0x60089000))) + + // SLCHOST Peripheral + SLCHOST = (*SLCHOST_Type)(unsafe.Pointer(uintptr(0x60017000))) + + // Event Task Matrix + SOC_ETM = (*SOC_ETM_Type)(unsafe.Pointer(uintptr(0x60013000))) + + // SPI (Serial Peripheral Interface) Controller 0 + SPI0 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x60002000))) + + // SPI (Serial Peripheral Interface) Controller 1 + SPI1 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x60003000))) + + // SPI (Serial Peripheral Interface) Controller 2 + SPI2 = (*SPI2_Type)(unsafe.Pointer(uintptr(0x60081000))) + + // System Timer + SYSTIMER = (*SYSTIMER_Type)(unsafe.Pointer(uintptr(0x6000a000))) + + // TEE Peripheral + TEE = (*TEE_Type)(unsafe.Pointer(uintptr(0x60098000))) + + // Timer Group 0 + TIMG0 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x60008000))) + + // RISC-V Trace Encoder + TRACE = (*TRACE_Type)(unsafe.Pointer(uintptr(0x600c0000))) + + // Two-Wire Automotive Interface + TWAI0 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x6000b000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART0 = (*UART_Type)(unsafe.Pointer(uintptr(0x60000000))) + + // Universal Host Controller Interface 0 + UHCI0 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x60005000))) + + // Full-speed USB Serial/JTAG Controller + USB_DEVICE = (*USB_DEVICE_Type)(unsafe.Pointer(uintptr(0x6000f000))) + + // Timer Group 1 + TIMG1 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x60009000))) + + // Two-Wire Automotive Interface + TWAI1 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x6000d000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + UART1 = (*UART_Type)(unsafe.Pointer(uintptr(0x60001000))) +) + +// AES (Advanced Encryption Standard) Accelerator +type AES_Type struct { + KEY_0 volatile.Register32 // 0x0 + KEY_1 volatile.Register32 // 0x4 + KEY_2 volatile.Register32 // 0x8 + KEY_3 volatile.Register32 // 0xC + KEY_4 volatile.Register32 // 0x10 + KEY_5 volatile.Register32 // 0x14 + KEY_6 volatile.Register32 // 0x18 + KEY_7 volatile.Register32 // 0x1C + TEXT_IN_0 volatile.Register32 // 0x20 + TEXT_IN_1 volatile.Register32 // 0x24 + TEXT_IN_2 volatile.Register32 // 0x28 + TEXT_IN_3 volatile.Register32 // 0x2C + TEXT_OUT_0 volatile.Register32 // 0x30 + TEXT_OUT_1 volatile.Register32 // 0x34 + TEXT_OUT_2 volatile.Register32 // 0x38 + TEXT_OUT_3 volatile.Register32 // 0x3C + MODE volatile.Register32 // 0x40 + ENDIAN volatile.Register32 // 0x44 + TRIGGER volatile.Register32 // 0x48 + STATE volatile.Register32 // 0x4C + IV_MEM [16]volatile.Register8 // 0x50 + H_MEM [16]volatile.Register8 // 0x60 + J0_MEM [16]volatile.Register8 // 0x70 + T0_MEM [16]volatile.Register8 // 0x80 + DMA_ENABLE volatile.Register32 // 0x90 + BLOCK_MODE volatile.Register32 // 0x94 + BLOCK_NUM volatile.Register32 // 0x98 + INC_SEL volatile.Register32 // 0x9C + AAD_BLOCK_NUM volatile.Register32 // 0xA0 + REMAINDER_BIT_NUM volatile.Register32 // 0xA4 + CONTINUE volatile.Register32 // 0xA8 + INT_CLEAR volatile.Register32 // 0xAC + INT_ENA volatile.Register32 // 0xB0 + DATE volatile.Register32 // 0xB4 + DMA_EXIT volatile.Register32 // 0xB8 +} + +// AES.KEY_0: Key material key_0 configure register +func (o *AES_Type) SetKEY_0(value uint32) { + volatile.StoreUint32(&o.KEY_0.Reg, value) +} +func (o *AES_Type) GetKEY_0() uint32 { + return volatile.LoadUint32(&o.KEY_0.Reg) +} + +// AES.KEY_1: Key material key_1 configure register +func (o *AES_Type) SetKEY_1(value uint32) { + volatile.StoreUint32(&o.KEY_1.Reg, value) +} +func (o *AES_Type) GetKEY_1() uint32 { + return volatile.LoadUint32(&o.KEY_1.Reg) +} + +// AES.KEY_2: Key material key_2 configure register +func (o *AES_Type) SetKEY_2(value uint32) { + volatile.StoreUint32(&o.KEY_2.Reg, value) +} +func (o *AES_Type) GetKEY_2() uint32 { + return volatile.LoadUint32(&o.KEY_2.Reg) +} + +// AES.KEY_3: Key material key_3 configure register +func (o *AES_Type) SetKEY_3(value uint32) { + volatile.StoreUint32(&o.KEY_3.Reg, value) +} +func (o *AES_Type) GetKEY_3() uint32 { + return volatile.LoadUint32(&o.KEY_3.Reg) +} + +// AES.KEY_4: Key material key_4 configure register +func (o *AES_Type) SetKEY_4(value uint32) { + volatile.StoreUint32(&o.KEY_4.Reg, value) +} +func (o *AES_Type) GetKEY_4() uint32 { + return volatile.LoadUint32(&o.KEY_4.Reg) +} + +// AES.KEY_5: Key material key_5 configure register +func (o *AES_Type) SetKEY_5(value uint32) { + volatile.StoreUint32(&o.KEY_5.Reg, value) +} +func (o *AES_Type) GetKEY_5() uint32 { + return volatile.LoadUint32(&o.KEY_5.Reg) +} + +// AES.KEY_6: Key material key_6 configure register +func (o *AES_Type) SetKEY_6(value uint32) { + volatile.StoreUint32(&o.KEY_6.Reg, value) +} +func (o *AES_Type) GetKEY_6() uint32 { + return volatile.LoadUint32(&o.KEY_6.Reg) +} + +// AES.KEY_7: Key material key_7 configure register +func (o *AES_Type) SetKEY_7(value uint32) { + volatile.StoreUint32(&o.KEY_7.Reg, value) +} +func (o *AES_Type) GetKEY_7() uint32 { + return volatile.LoadUint32(&o.KEY_7.Reg) +} + +// AES.TEXT_IN_0: source text material text_in_0 configure register +func (o *AES_Type) SetTEXT_IN_0(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_0.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_0() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_0.Reg) +} + +// AES.TEXT_IN_1: source text material text_in_1 configure register +func (o *AES_Type) SetTEXT_IN_1(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_1.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_1() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_1.Reg) +} + +// AES.TEXT_IN_2: source text material text_in_2 configure register +func (o *AES_Type) SetTEXT_IN_2(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_2.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_2() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_2.Reg) +} + +// AES.TEXT_IN_3: source text material text_in_3 configure register +func (o *AES_Type) SetTEXT_IN_3(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_3.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_3() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_3.Reg) +} + +// AES.TEXT_OUT_0: result text material text_out_0 configure register +func (o *AES_Type) SetTEXT_OUT_0(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_0.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_0() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_0.Reg) +} + +// AES.TEXT_OUT_1: result text material text_out_1 configure register +func (o *AES_Type) SetTEXT_OUT_1(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_1.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_1() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_1.Reg) +} + +// AES.TEXT_OUT_2: result text material text_out_2 configure register +func (o *AES_Type) SetTEXT_OUT_2(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_2.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_2() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_2.Reg) +} + +// AES.TEXT_OUT_3: result text material text_out_3 configure register +func (o *AES_Type) SetTEXT_OUT_3(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_3.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_3() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_3.Reg) +} + +// AES.MODE: AES Mode register +func (o *AES_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// AES.ENDIAN: AES Endian configure register +func (o *AES_Type) SetENDIAN(value uint32) { + volatile.StoreUint32(&o.ENDIAN.Reg, volatile.LoadUint32(&o.ENDIAN.Reg)&^(0x3f)|value) +} +func (o *AES_Type) GetENDIAN() uint32 { + return volatile.LoadUint32(&o.ENDIAN.Reg) & 0x3f +} + +// AES.TRIGGER: AES trigger register +func (o *AES_Type) SetTRIGGER(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetTRIGGER() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} + +// AES.STATE: AES state register +func (o *AES_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *AES_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// AES.DMA_ENABLE: DMA-AES working mode register +func (o *AES_Type) SetDMA_ENABLE(value uint32) { + volatile.StoreUint32(&o.DMA_ENABLE.Reg, volatile.LoadUint32(&o.DMA_ENABLE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_ENABLE() uint32 { + return volatile.LoadUint32(&o.DMA_ENABLE.Reg) & 0x1 +} + +// AES.BLOCK_MODE: AES cipher block mode register +func (o *AES_Type) SetBLOCK_MODE(value uint32) { + volatile.StoreUint32(&o.BLOCK_MODE.Reg, volatile.LoadUint32(&o.BLOCK_MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetBLOCK_MODE() uint32 { + return volatile.LoadUint32(&o.BLOCK_MODE.Reg) & 0x7 +} + +// AES.BLOCK_NUM: AES block number register +func (o *AES_Type) SetBLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetBLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.BLOCK_NUM.Reg) +} + +// AES.INC_SEL: Standard incrementing function configure register +func (o *AES_Type) SetINC_SEL(value uint32) { + volatile.StoreUint32(&o.INC_SEL.Reg, volatile.LoadUint32(&o.INC_SEL.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINC_SEL() uint32 { + return volatile.LoadUint32(&o.INC_SEL.Reg) & 0x1 +} + +// AES.AAD_BLOCK_NUM: Additional Authential Data block number register +func (o *AES_Type) SetAAD_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.AAD_BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetAAD_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.AAD_BLOCK_NUM.Reg) +} + +// AES.REMAINDER_BIT_NUM: AES remainder bit number register +func (o *AES_Type) SetREMAINDER_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.REMAINDER_BIT_NUM.Reg, volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg)&^(0x7f)|value) +} +func (o *AES_Type) GetREMAINDER_BIT_NUM() uint32 { + return volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg) & 0x7f +} + +// AES.CONTINUE: AES continue register +func (o *AES_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetCONTINUE() uint32 { + return volatile.LoadUint32(&o.CONTINUE.Reg) & 0x1 +} + +// AES.INT_CLEAR: AES Interrupt clear register +func (o *AES_Type) SetINT_CLEAR(value uint32) { + volatile.StoreUint32(&o.INT_CLEAR.Reg, volatile.LoadUint32(&o.INT_CLEAR.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_CLEAR() uint32 { + return volatile.LoadUint32(&o.INT_CLEAR.Reg) & 0x1 +} + +// AES.INT_ENA: AES Interrupt enable register +func (o *AES_Type) SetINT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// AES.DATE: AES version control register +func (o *AES_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *AES_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// AES.DMA_EXIT: AES-DMA exit config +func (o *AES_Type) SetDMA_EXIT(value uint32) { + volatile.StoreUint32(&o.DMA_EXIT.Reg, volatile.LoadUint32(&o.DMA_EXIT.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_EXIT() uint32 { + return volatile.LoadUint32(&o.DMA_EXIT.Reg) & 0x1 +} + +// SAR (Successive Approximation Register) Analog-to-Digital Converter +type APB_SARADC_Type struct { + CTRL volatile.Register32 // 0x0 + CTRL2 volatile.Register32 // 0x4 + FILTER_CTRL1 volatile.Register32 // 0x8 + FSM_WAIT volatile.Register32 // 0xC + SAR1_STATUS volatile.Register32 // 0x10 + SAR2_STATUS volatile.Register32 // 0x14 + SAR_PATT_TAB1 volatile.Register32 // 0x18 + SAR_PATT_TAB2 volatile.Register32 // 0x1C + ONETIME_SAMPLE volatile.Register32 // 0x20 + ARB_CTRL volatile.Register32 // 0x24 + FILTER_CTRL0 volatile.Register32 // 0x28 + SAR1DATA_STATUS volatile.Register32 // 0x2C + SAR2DATA_STATUS volatile.Register32 // 0x30 + THRES0_CTRL volatile.Register32 // 0x34 + THRES1_CTRL volatile.Register32 // 0x38 + THRES_CTRL volatile.Register32 // 0x3C + INT_ENA volatile.Register32 // 0x40 + INT_RAW volatile.Register32 // 0x44 + INT_ST volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + DMA_CONF volatile.Register32 // 0x50 + CLKM_CONF volatile.Register32 // 0x54 + APB_TSENS_CTRL volatile.Register32 // 0x58 + TSENS_CTRL2 volatile.Register32 // 0x5C + CALI volatile.Register32 // 0x60 + APB_TSENS_WAKE volatile.Register32 // 0x64 + APB_TSENS_SAMPLE volatile.Register32 // 0x68 + _ [912]byte + CTRL_DATE volatile.Register32 // 0x3FC +} + +// APB_SARADC.CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetCTRL_SARADC_START_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START_FORCE() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x7f80)|value<<7) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x7f80) >> 7 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x38000)|value<<15) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x38000) >> 15 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_XPD_SAR_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x18000000)|value<<27) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_XPD_SAR_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x18000000) >> 27 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC2_PWDET_DRV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC2_PWDET_DRV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc0000000) >> 30 +} + +// APB_SARADC.CTRL2: digital saradc configure register +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MEAS_NUM_LIMIT(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MEAS_NUM_LIMIT() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MAX_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1fe)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MAX_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1fe) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR1_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR1_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x200) >> 9 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR2_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR2_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x400) >> 10 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff000)|value<<12) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_TARGET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff000) >> 12 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1000000) >> 24 +} + +// APB_SARADC.FILTER_CTRL1: digital saradc configure register +func (o *APB_SARADC_Type) SetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0x1c000000)|value<<26) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0x1c000000) >> 26 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0xe0000000)|value<<29) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0xe0000000) >> 29 +} + +// APB_SARADC.FSM_WAIT: digital saradc configure register +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff00)|value<<8) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff00) >> 8 +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff0000)|value<<16) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff0000) >> 16 +} + +// APB_SARADC.SAR1_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR1_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR1_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR1_STATUS.Reg) +} + +// APB_SARADC.SAR2_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR2_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR2_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR2_STATUS.Reg) +} + +// APB_SARADC.SAR_PATT_TAB1: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR_PATT_TAB1_SARADC_SAR_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR_PATT_TAB1.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR_PATT_TAB1_SARADC_SAR_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR_PATT_TAB1.Reg) & 0xffffff +} + +// APB_SARADC.SAR_PATT_TAB2: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR_PATT_TAB2_SARADC_SAR_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR_PATT_TAB2.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR_PATT_TAB2_SARADC_SAR_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR_PATT_TAB2.Reg) & 0xffffff +} + +// APB_SARADC.ONETIME_SAMPLE: digital saradc configure register +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_ATTEN(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x1800000)|value<<23) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_ATTEN() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x1800000) >> 23 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x1e000000)|value<<25) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x1e000000) >> 25 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_START(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_START() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.ARB_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x4) >> 2 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x8) >> 3 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x10) >> 4 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_GRANT_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_GRANT_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x20) >> 5 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc0)|value<<6) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc0) >> 6 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x300)|value<<8) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x300) >> 8 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc00)|value<<10) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc00) >> 10 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_FIX_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_FIX_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x1000) >> 12 +} + +// APB_SARADC.FILTER_CTRL0: digital saradc configure register +func (o *APB_SARADC_Type) SetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x3c0000)|value<<18) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x3c0000) >> 18 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x3c00000) >> 22 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_APB_SARADC_FILTER_RESET(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_APB_SARADC_FILTER_RESET() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.SAR1DATA_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR1DATA_STATUS_APB_SARADC1_DATA(value uint32) { + volatile.StoreUint32(&o.SAR1DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR1DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetSAR1DATA_STATUS_APB_SARADC1_DATA() uint32 { + return volatile.LoadUint32(&o.SAR1DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.SAR2DATA_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR2DATA_STATUS_APB_SARADC2_DATA(value uint32) { + volatile.StoreUint32(&o.SAR2DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR2DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetSAR2DATA_STATUS_APB_SARADC2_DATA() uint32 { + return volatile.LoadUint32(&o.SAR2DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.THRES0_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetTHRES0_CTRL_APB_SARADC_THRES0_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0xf)|value) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_APB_SARADC_THRES0_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0xf +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_APB_SARADC_THRES0_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_APB_SARADC_THRES0_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_APB_SARADC_THRES0_LOW(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_APB_SARADC_THRES0_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES1_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetTHRES1_CTRL_APB_SARADC_THRES1_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0xf)|value) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_APB_SARADC_THRES1_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0xf +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_APB_SARADC_THRES1_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_APB_SARADC_THRES1_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_APB_SARADC_THRES1_LOW(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_APB_SARADC_THRES1_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetTHRES_CTRL_APB_SARADC_THRES_ALL_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_APB_SARADC_THRES_ALL_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_APB_SARADC_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_APB_SARADC_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_APB_SARADC_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_APB_SARADC_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ENA: digital saradc int register +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_TSENS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_TSENS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES1_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES1_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES0_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES0_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC2_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC2_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC1_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC1_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_RAW: digital saradc int register +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_TSENS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_TSENS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES1_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES1_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES0_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES0_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC2_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC2_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC1_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC1_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ST: digital saradc int register +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_TSENS_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_TSENS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES1_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES1_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES0_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES0_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES1_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES1_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES0_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES0_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC2_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC2_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC1_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC1_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_CLR: digital saradc int register +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_TSENS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_TSENS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES1_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES1_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES0_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES0_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC2_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC2_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC1_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC1_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.DMA_CONF: digital saradc configure register +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0xffff)|value) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0xffff +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_RESET_FSM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_RESET_FSM() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_TRANS(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_TRANS() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.CLKM_CONF: digital saradc configure register +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x3f00) >> 8 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xfc000) >> 14 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x100000) >> 20 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x600000)|value<<21) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x600000) >> 21 +} + +// APB_SARADC.APB_TSENS_CTRL: digital tsens configure register +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_OUT(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_OUT() uint32 { + return volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_IN_INV(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_IN_INV() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x2000) >> 13 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_PU(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_PU() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x400000) >> 22 +} + +// APB_SARADC.TSENS_CTRL2: digital tsens configure register +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0xfff)|value) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0xfff +} +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0x3000)|value<<12) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0x3000) >> 12 +} +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_CLK_INV(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0x8000)|value<<15) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0x8000) >> 15 +} + +// APB_SARADC.CALI: digital saradc configure register +func (o *APB_SARADC_Type) SetCALI_APB_SARADC_CALI_CFG(value uint32) { + volatile.StoreUint32(&o.CALI.Reg, volatile.LoadUint32(&o.CALI.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetCALI_APB_SARADC_CALI_CFG() uint32 { + return volatile.LoadUint32(&o.CALI.Reg) & 0x1ffff +} + +// APB_SARADC.APB_TSENS_WAKE: digital tsens configure register +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_TH_LOW(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_TH_LOW() uint32 { + return volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_TH_HIGH(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0xff00)|value<<8) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_TH_HIGH() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0xff00) >> 8 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0x10000)|value<<16) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0x10000) >> 16 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_MODE(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0x20000)|value<<17) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_MODE() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0x20000) >> 17 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0x40000)|value<<18) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0x40000) >> 18 +} + +// APB_SARADC.APB_TSENS_SAMPLE: digital tsens configure register +func (o *APB_SARADC_Type) SetAPB_TSENS_SAMPLE_TSENS_SAMPLE_RATE(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_SAMPLE.Reg, volatile.LoadUint32(&o.APB_TSENS_SAMPLE.Reg)&^(0xffff)|value) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_SAMPLE_TSENS_SAMPLE_RATE() uint32 { + return volatile.LoadUint32(&o.APB_TSENS_SAMPLE.Reg) & 0xffff +} +func (o *APB_SARADC_Type) SetAPB_TSENS_SAMPLE_TSENS_SAMPLE_EN(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_SAMPLE.Reg, volatile.LoadUint32(&o.APB_TSENS_SAMPLE.Reg)&^(0x10000)|value<<16) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_SAMPLE_TSENS_SAMPLE_EN() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_SAMPLE.Reg) & 0x10000) >> 16 +} + +// APB_SARADC.CTRL_DATE: version +func (o *APB_SARADC_Type) SetCTRL_DATE(value uint32) { + volatile.StoreUint32(&o.CTRL_DATE.Reg, value) +} +func (o *APB_SARADC_Type) GetCTRL_DATE() uint32 { + return volatile.LoadUint32(&o.CTRL_DATE.Reg) +} + +// Debug Assist +type ASSIST_DEBUG_Type struct { + CORE_0_MONTR_ENA volatile.Register32 // 0x0 + CORE_0_INTR_RAW volatile.Register32 // 0x4 + CORE_0_INTR_ENA volatile.Register32 // 0x8 + CORE_0_INTR_CLR volatile.Register32 // 0xC + CORE_0_AREA_DRAM0_0_MIN volatile.Register32 // 0x10 + CORE_0_AREA_DRAM0_0_MAX volatile.Register32 // 0x14 + CORE_0_AREA_DRAM0_1_MIN volatile.Register32 // 0x18 + CORE_0_AREA_DRAM0_1_MAX volatile.Register32 // 0x1C + CORE_0_AREA_PIF_0_MIN volatile.Register32 // 0x20 + CORE_0_AREA_PIF_0_MAX volatile.Register32 // 0x24 + CORE_0_AREA_PIF_1_MIN volatile.Register32 // 0x28 + CORE_0_AREA_PIF_1_MAX volatile.Register32 // 0x2C + CORE_0_AREA_PC volatile.Register32 // 0x30 + CORE_0_AREA_SP volatile.Register32 // 0x34 + CORE_0_SP_MIN volatile.Register32 // 0x38 + CORE_0_SP_MAX volatile.Register32 // 0x3C + CORE_0_SP_PC volatile.Register32 // 0x40 + CORE_0_RCD_EN volatile.Register32 // 0x44 + CORE_0_RCD_PDEBUGPC volatile.Register32 // 0x48 + CORE_0_RCD_PDEBUGSP volatile.Register32 // 0x4C + CORE_0_IRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x50 + CORE_0_IRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x54 + CORE_0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x58 + CORE_0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x5C + CORE_0_DRAM0_EXCEPTION_MONITOR_2 volatile.Register32 // 0x60 + CORE_0_DRAM0_EXCEPTION_MONITOR_3 volatile.Register32 // 0x64 + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x68 + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x6C + C0RE_0_LASTPC_BEFORE_EXCEPTION volatile.Register32 // 0x70 + C0RE_0_DEBUG_MODE volatile.Register32 // 0x74 + CLOCK_GATE volatile.Register32 // 0x78 + _ [896]byte + DATE volatile.Register32 // 0x3FC +} + +// ASSIST_DEBUG.CORE_0_MONTR_ENA: core0 monitor enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_RAW: core0 monitor interrupt status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_ENA: core0 monitor interrupt enable register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_CLR: core0 monitor interrupt clr register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MIN: core0 dram0 region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MAX: core0 dram0 region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MIN: core0 dram0 region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MAX: core0 dram0 region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MIN: core0 PIF region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MAX: core0 PIF region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MIN: core0 PIF region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MAX: core0 PIF region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PC: core0 area pc status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PC.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_SP: core0 area sp status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_SP(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_SP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_SP() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_SP.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_MIN: stack min value +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_MAX: stack max value +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_PC: stack monitor pc status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_PC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_EN: record enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGPC: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGPC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGPC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGSP: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGSP(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGSP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGSP() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGSP.Reg) +} + +// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0 +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1 +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1e000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1e000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg) +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)&^(0x1e000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) & 0x1e000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_3() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg) +} + +// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register6 +func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xfffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0xfffff +} + +// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register7 +func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xfffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xfffff +} + +// ASSIST_DEBUG.C0RE_0_LASTPC_BEFORE_EXCEPTION: cpu status register +func (o *ASSIST_DEBUG_Type) SetC0RE_0_LASTPC_BEFORE_EXCEPTION(value uint32) { + volatile.StoreUint32(&o.C0RE_0_LASTPC_BEFORE_EXCEPTION.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetC0RE_0_LASTPC_BEFORE_EXCEPTION() uint32 { + return volatile.LoadUint32(&o.C0RE_0_LASTPC_BEFORE_EXCEPTION.Reg) +} + +// ASSIST_DEBUG.C0RE_0_DEBUG_MODE: cpu status register +func (o *ASSIST_DEBUG_Type) SetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE(value uint32) { + volatile.StoreUint32(&o.C0RE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE() uint32 { + return volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE(value uint32) { + volatile.StoreUint32(&o.C0RE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CLOCK_GATE: clock register +func (o *ASSIST_DEBUG_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// ASSIST_DEBUG.DATE: version register +func (o *ASSIST_DEBUG_Type) SetDATE_ASSIST_DEBUG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetDATE_ASSIST_DEBUG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Atomic Locker +type ATOMIC_Type struct { + ADDR_LOCK volatile.Register32 // 0x0 + LR_ADDR volatile.Register32 // 0x4 + LR_VALUE volatile.Register32 // 0x8 + LOCK_STATUS volatile.Register32 // 0xC + COUNTER volatile.Register32 // 0x10 +} + +// ATOMIC.ADDR_LOCK: hardware lock regsiter +func (o *ATOMIC_Type) SetADDR_LOCK_LOCK(value uint32) { + volatile.StoreUint32(&o.ADDR_LOCK.Reg, volatile.LoadUint32(&o.ADDR_LOCK.Reg)&^(0x3)|value) +} +func (o *ATOMIC_Type) GetADDR_LOCK_LOCK() uint32 { + return volatile.LoadUint32(&o.ADDR_LOCK.Reg) & 0x3 +} + +// ATOMIC.LR_ADDR: gloable lr address regsiter +func (o *ATOMIC_Type) SetLR_ADDR(value uint32) { + volatile.StoreUint32(&o.LR_ADDR.Reg, value) +} +func (o *ATOMIC_Type) GetLR_ADDR() uint32 { + return volatile.LoadUint32(&o.LR_ADDR.Reg) +} + +// ATOMIC.LR_VALUE: gloable lr value regsiter +func (o *ATOMIC_Type) SetLR_VALUE(value uint32) { + volatile.StoreUint32(&o.LR_VALUE.Reg, value) +} +func (o *ATOMIC_Type) GetLR_VALUE() uint32 { + return volatile.LoadUint32(&o.LR_VALUE.Reg) +} + +// ATOMIC.LOCK_STATUS: lock status regsiter +func (o *ATOMIC_Type) SetLOCK_STATUS(value uint32) { + volatile.StoreUint32(&o.LOCK_STATUS.Reg, volatile.LoadUint32(&o.LOCK_STATUS.Reg)&^(0x3)|value) +} +func (o *ATOMIC_Type) GetLOCK_STATUS() uint32 { + return volatile.LoadUint32(&o.LOCK_STATUS.Reg) & 0x3 +} + +// ATOMIC.COUNTER: wait counter register +func (o *ATOMIC_Type) SetCOUNTER_WAIT_COUNTER(value uint32) { + volatile.StoreUint32(&o.COUNTER.Reg, volatile.LoadUint32(&o.COUNTER.Reg)&^(0xffff)|value) +} +func (o *ATOMIC_Type) GetCOUNTER_WAIT_COUNTER() uint32 { + return volatile.LoadUint32(&o.COUNTER.Reg) & 0xffff +} + +// DMA (Direct Memory Access) Controller +type DMA_Type struct { + IN_INT_RAW_CH0 volatile.Register32 // 0x0 + IN_INT_ST_CH0 volatile.Register32 // 0x4 + IN_INT_ENA_CH0 volatile.Register32 // 0x8 + IN_INT_CLR_CH0 volatile.Register32 // 0xC + IN_INT_RAW_CH1 volatile.Register32 // 0x10 + IN_INT_ST_CH1 volatile.Register32 // 0x14 + IN_INT_ENA_CH1 volatile.Register32 // 0x18 + IN_INT_CLR_CH1 volatile.Register32 // 0x1C + IN_INT_RAW_CH2 volatile.Register32 // 0x20 + IN_INT_ST_CH2 volatile.Register32 // 0x24 + IN_INT_ENA_CH2 volatile.Register32 // 0x28 + IN_INT_CLR_CH2 volatile.Register32 // 0x2C + OUT_INT_RAW_CH0 volatile.Register32 // 0x30 + OUT_INT_ST_CH0 volatile.Register32 // 0x34 + OUT_INT_ENA_CH0 volatile.Register32 // 0x38 + OUT_INT_CLR_CH0 volatile.Register32 // 0x3C + OUT_INT_RAW_CH1 volatile.Register32 // 0x40 + OUT_INT_ST_CH1 volatile.Register32 // 0x44 + OUT_INT_ENA_CH1 volatile.Register32 // 0x48 + OUT_INT_CLR_CH1 volatile.Register32 // 0x4C + OUT_INT_RAW_CH2 volatile.Register32 // 0x50 + OUT_INT_ST_CH2 volatile.Register32 // 0x54 + OUT_INT_ENA_CH2 volatile.Register32 // 0x58 + OUT_INT_CLR_CH2 volatile.Register32 // 0x5C + AHB_TEST volatile.Register32 // 0x60 + MISC_CONF volatile.Register32 // 0x64 + DATE volatile.Register32 // 0x68 + _ [4]byte + IN_CONF0_CH0 volatile.Register32 // 0x70 + IN_CONF1_CH0 volatile.Register32 // 0x74 + INFIFO_STATUS_CH0 volatile.Register32 // 0x78 + IN_POP_CH0 volatile.Register32 // 0x7C + IN_LINK_CH0 volatile.Register32 // 0x80 + IN_STATE_CH0 volatile.Register32 // 0x84 + IN_SUC_EOF_DES_ADDR_CH0 volatile.Register32 // 0x88 + IN_ERR_EOF_DES_ADDR_CH0 volatile.Register32 // 0x8C + IN_DSCR_CH0 volatile.Register32 // 0x90 + IN_DSCR_BF0_CH0 volatile.Register32 // 0x94 + IN_DSCR_BF1_CH0 volatile.Register32 // 0x98 + IN_PRI_CH0 volatile.Register32 // 0x9C + IN_PERI_SEL_CH0 volatile.Register32 // 0xA0 + _ [48]byte + OUT_CONF1_CH0 volatile.Register32 // 0xD4 + OUTFIFO_STATUS_CH0 volatile.Register32 // 0xD8 + OUT_PUSH_CH0 volatile.Register32 // 0xDC + OUT_LINK_CH0 volatile.Register32 // 0xE0 + OUT_STATE_CH0 volatile.Register32 // 0xE4 + OUT_EOF_DES_ADDR_CH0 volatile.Register32 // 0xE8 + OUT_EOF_BFR_DES_ADDR_CH0 volatile.Register32 // 0xEC + OUT_DSCR_CH0 volatile.Register32 // 0xF0 + OUT_DSCR_BF0_CH0 volatile.Register32 // 0xF4 + OUT_DSCR_BF1_CH0 volatile.Register32 // 0xF8 + OUT_PRI_CH0 volatile.Register32 // 0xFC + OUT_PERI_SEL_CH0 volatile.Register32 // 0x100 + _ [44]byte + IN_CONF0_CH1 volatile.Register32 // 0x130 + IN_CONF1_CH1 volatile.Register32 // 0x134 + INFIFO_STATUS_CH1 volatile.Register32 // 0x138 + IN_POP_CH1 volatile.Register32 // 0x13C + IN_LINK_CH1 volatile.Register32 // 0x140 + IN_STATE_CH1 volatile.Register32 // 0x144 + IN_SUC_EOF_DES_ADDR_CH1 volatile.Register32 // 0x148 + IN_ERR_EOF_DES_ADDR_CH1 volatile.Register32 // 0x14C + IN_DSCR_CH1 volatile.Register32 // 0x150 + IN_DSCR_BF0_CH1 volatile.Register32 // 0x154 + IN_DSCR_BF1_CH1 volatile.Register32 // 0x158 + IN_PRI_CH1 volatile.Register32 // 0x15C + IN_PERI_SEL_CH1 volatile.Register32 // 0x160 + _ [44]byte + OUT_CONF0_CH0 volatile.Register32 // 0x190 + OUT_CONF1_CH1 volatile.Register32 // 0x194 + OUTFIFO_STATUS_CH1 volatile.Register32 // 0x198 + OUT_PUSH_CH1 volatile.Register32 // 0x19C + OUT_LINK_CH1 volatile.Register32 // 0x1A0 + OUT_STATE_CH1 volatile.Register32 // 0x1A4 + OUT_EOF_DES_ADDR_CH1 volatile.Register32 // 0x1A8 + OUT_EOF_BFR_DES_ADDR_CH1 volatile.Register32 // 0x1AC + OUT_DSCR_CH1 volatile.Register32 // 0x1B0 + OUT_DSCR_BF0_CH1 volatile.Register32 // 0x1B4 + OUT_DSCR_BF1_CH1 volatile.Register32 // 0x1B8 + OUT_PRI_CH1 volatile.Register32 // 0x1BC + OUT_PERI_SEL_CH1 volatile.Register32 // 0x1C0 + _ [44]byte + IN_CONF0_CH2 volatile.Register32 // 0x1F0 + IN_CONF1_CH2 volatile.Register32 // 0x1F4 + INFIFO_STATUS_CH2 volatile.Register32 // 0x1F8 + IN_POP_CH2 volatile.Register32 // 0x1FC + IN_LINK_CH2 volatile.Register32 // 0x200 + IN_STATE_CH2 volatile.Register32 // 0x204 + IN_SUC_EOF_DES_ADDR_CH2 volatile.Register32 // 0x208 + IN_ERR_EOF_DES_ADDR_CH2 volatile.Register32 // 0x20C + IN_DSCR_CH2 volatile.Register32 // 0x210 + IN_DSCR_BF0_CH2 volatile.Register32 // 0x214 + IN_DSCR_BF1_CH2 volatile.Register32 // 0x218 + IN_PRI_CH2 volatile.Register32 // 0x21C + IN_PERI_SEL_CH2 volatile.Register32 // 0x220 + _ [44]byte + OUT_CONF0_CH1 volatile.Register32 // 0x250 + OUT_CONF1_CH2 volatile.Register32 // 0x254 + OUTFIFO_STATUS_CH2 volatile.Register32 // 0x258 + OUT_PUSH_CH2 volatile.Register32 // 0x25C + OUT_LINK_CH2 volatile.Register32 // 0x260 + OUT_STATE_CH2 volatile.Register32 // 0x264 + OUT_EOF_DES_ADDR_CH2 volatile.Register32 // 0x268 + OUT_EOF_BFR_DES_ADDR_CH2 volatile.Register32 // 0x26C + OUT_DSCR_CH2 volatile.Register32 // 0x270 + OUT_DSCR_BF0_CH2 volatile.Register32 // 0x274 + OUT_DSCR_BF1_CH2 volatile.Register32 // 0x278 + OUT_PRI_CH2 volatile.Register32 // 0x27C + OUT_PERI_SEL_CH2 volatile.Register32 // 0x280 + _ [140]byte + OUT_CONF0_CH2 volatile.Register32 // 0x310 +} + +// DMA.IN_INT_RAW_CH0: Raw status interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ST_CH0: Masked interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ENA_CH0: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_CLR_CH0: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_RAW_CH1: Raw status interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ST_CH1: Masked interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ENA_CH1: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_CLR_CH1: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_RAW_CH2: Raw status interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ST_CH2: Masked interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ENA_CH2: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_CLR_CH2: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x40) >> 6 +} + +// DMA.OUT_INT_RAW_CH0: Raw status interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ST_CH0: Masked interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ENA_CH0: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_CLR_CH0: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_RAW_CH1: Raw status interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ST_CH1: Masked interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ENA_CH1: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_CLR_CH1: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_RAW_CH2: Raw status interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ST_CH2: Masked interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ENA_CH2: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_CLR_CH2: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x20) >> 5 +} + +// DMA.AHB_TEST: reserved +func (o *DMA_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *DMA_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// DMA.MISC_CONF: MISC register +func (o *DMA_Type) SetMISC_CONF_AHBM_RST_INTER(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetMISC_CONF_AHBM_RST_INTER() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} +func (o *DMA_Type) SetMISC_CONF_ARB_PRI_DIS(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetMISC_CONF_ARB_PRI_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetMISC_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x8) >> 3 +} + +// DMA.DATE: Version control register +func (o *DMA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *DMA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// DMA.IN_CONF0_CH0: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH0_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH0_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH0_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_ETM_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x20) >> 5 +} + +// DMA.IN_CONF1_CH0: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH0_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH0_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH0: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH0: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg) +} + +// DMA.IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg) +} + +// DMA.IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg) +} + +// DMA.IN_PRI_CH0: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH0_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH0_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH0_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH0_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg) & 0x3f +} + +// DMA.OUT_CONF1_CH0: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH0_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH0_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH0: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH0: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg) +} + +// DMA.OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg) +} + +// DMA.OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg) +} + +// DMA.OUT_PRI_CH0: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH0_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH0_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH0_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH0_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH1: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH1_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH1_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH1_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_ETM_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x20) >> 5 +} + +// DMA.IN_CONF1_CH1: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH1_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH1_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH1: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH1: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH1_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH1_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH1_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH1_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH1: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH1: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH1_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH1_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH1: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH1: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.IN_DSCR_CH1: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg) +} + +// DMA.IN_DSCR_BF0_CH1: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg) +} + +// DMA.IN_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg) +} + +// DMA.IN_PRI_CH1: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH1_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH1_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH1: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH1_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH1_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH0: Configure 0 register of Tx channel 1 +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_ETM_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x40) >> 6 +} + +// DMA.OUT_CONF1_CH1: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH1_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH1_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH1: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH1: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH1: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH1: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH1_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH1: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH1: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg) +} + +// DMA.OUT_DSCR_CH1: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg) +} + +// DMA.OUT_DSCR_BF0_CH1: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg) +} + +// DMA.OUT_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg) +} + +// DMA.OUT_PRI_CH1: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH1_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH1_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH1: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH1_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH1_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH2: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH2_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH2_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH2_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_ETM_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x20) >> 5 +} + +// DMA.IN_CONF1_CH2: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH2_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH2_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH2: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH2: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH2_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH2_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH2_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH2_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH2: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH2: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH2_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH2_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH2: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH2: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.IN_DSCR_CH2: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg) +} + +// DMA.IN_DSCR_BF0_CH2: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg) +} + +// DMA.IN_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg) +} + +// DMA.IN_PRI_CH2: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH2_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH2_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH2: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH2_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH2_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH1: Configure 0 register of Tx channel 1 +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_ETM_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x40) >> 6 +} + +// DMA.OUT_CONF1_CH2: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH2_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH2_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH2: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH2: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH2: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH2: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH2_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH2: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH2: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg) +} + +// DMA.OUT_DSCR_CH2: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg) +} + +// DMA.OUT_DSCR_BF0_CH2: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg) +} + +// DMA.OUT_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg) +} + +// DMA.OUT_PRI_CH2: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH2_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH2_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH2: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH2_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH2_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH2: Configure 0 register of Tx channel 1 +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_ETM_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x40) >> 6 +} + +// Digital Signature +type DS_Type struct { + Y_MEM [512]volatile.Register8 // 0x0 + M_MEM [512]volatile.Register8 // 0x200 + RB_MEM [512]volatile.Register8 // 0x400 + BOX_MEM [48]volatile.Register8 // 0x600 + IV_MEM [16]volatile.Register8 // 0x630 + _ [448]byte + X_MEM [512]volatile.Register8 // 0x800 + Z_MEM [512]volatile.Register8 // 0xA00 + _ [512]byte + SET_START volatile.Register32 // 0xE00 + SET_CONTINUE volatile.Register32 // 0xE04 + SET_FINISH volatile.Register32 // 0xE08 + QUERY_BUSY volatile.Register32 // 0xE0C + QUERY_KEY_WRONG volatile.Register32 // 0xE10 + QUERY_CHECK volatile.Register32 // 0xE14 + _ [8]byte + DATE volatile.Register32 // 0xE20 +} + +// DS.SET_START: DS start control register +func (o *DS_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// DS.SET_CONTINUE: DS continue control register +func (o *DS_Type) SetSET_CONTINUE(value uint32) { + volatile.StoreUint32(&o.SET_CONTINUE.Reg, volatile.LoadUint32(&o.SET_CONTINUE.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_CONTINUE() uint32 { + return volatile.LoadUint32(&o.SET_CONTINUE.Reg) & 0x1 +} + +// DS.SET_FINISH: DS finish control register +func (o *DS_Type) SetSET_FINISH(value uint32) { + volatile.StoreUint32(&o.SET_FINISH.Reg, volatile.LoadUint32(&o.SET_FINISH.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_FINISH() uint32 { + return volatile.LoadUint32(&o.SET_FINISH.Reg) & 0x1 +} + +// DS.QUERY_BUSY: DS query busy register +func (o *DS_Type) SetQUERY_BUSY(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_BUSY() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// DS.QUERY_KEY_WRONG: DS query key-wrong counter register +func (o *DS_Type) SetQUERY_KEY_WRONG(value uint32) { + volatile.StoreUint32(&o.QUERY_KEY_WRONG.Reg, volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg)&^(0xf)|value) +} +func (o *DS_Type) GetQUERY_KEY_WRONG() uint32 { + return volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg) & 0xf +} + +// DS.QUERY_CHECK: DS query check result register +func (o *DS_Type) SetQUERY_CHECK_MD_ERROR(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_CHECK_MD_ERROR() uint32 { + return volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x1 +} +func (o *DS_Type) SetQUERY_CHECK_PADDING_BAD(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x2)|value<<1) +} +func (o *DS_Type) GetQUERY_CHECK_PADDING_BAD() uint32 { + return (volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x2) >> 1 +} + +// DS.DATE: DS version control register +func (o *DS_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *DS_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// ECC (ECC Hardware Accelerator) +type ECC_Type struct { + _ [12]byte + MULT_INT_RAW volatile.Register32 // 0xC + MULT_INT_ST volatile.Register32 // 0x10 + MULT_INT_ENA volatile.Register32 // 0x14 + MULT_INT_CLR volatile.Register32 // 0x18 + MULT_CONF volatile.Register32 // 0x1C + _ [220]byte + MULT_DATE volatile.Register32 // 0xFC + K_MEM [32]volatile.Register8 // 0x100 + PX_MEM [32]volatile.Register8 // 0x120 + PY_MEM [32]volatile.Register8 // 0x140 +} + +// ECC.MULT_INT_RAW: ECC interrupt raw register, valid in level. +func (o *ECC_Type) SetMULT_INT_RAW_CALC_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.MULT_INT_RAW.Reg, volatile.LoadUint32(&o.MULT_INT_RAW.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_RAW_CALC_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.MULT_INT_RAW.Reg) & 0x1 +} + +// ECC.MULT_INT_ST: ECC interrupt status register. +func (o *ECC_Type) SetMULT_INT_ST_CALC_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.MULT_INT_ST.Reg, volatile.LoadUint32(&o.MULT_INT_ST.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_ST_CALC_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.MULT_INT_ST.Reg) & 0x1 +} + +// ECC.MULT_INT_ENA: ECC interrupt enable register. +func (o *ECC_Type) SetMULT_INT_ENA_CALC_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.MULT_INT_ENA.Reg, volatile.LoadUint32(&o.MULT_INT_ENA.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_ENA_CALC_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.MULT_INT_ENA.Reg) & 0x1 +} + +// ECC.MULT_INT_CLR: ECC interrupt clear register. +func (o *ECC_Type) SetMULT_INT_CLR_CALC_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.MULT_INT_CLR.Reg, volatile.LoadUint32(&o.MULT_INT_CLR.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_CLR_CALC_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.MULT_INT_CLR.Reg) & 0x1 +} + +// ECC.MULT_CONF: ECC configure register +func (o *ECC_Type) SetMULT_CONF_START(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_CONF_START() uint32 { + return volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x1 +} +func (o *ECC_Type) SetMULT_CONF_RESET(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *ECC_Type) GetMULT_CONF_RESET() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x2) >> 1 +} +func (o *ECC_Type) SetMULT_CONF_KEY_LENGTH(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x4)|value<<2) +} +func (o *ECC_Type) GetMULT_CONF_KEY_LENGTH() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x4) >> 2 +} +func (o *ECC_Type) SetMULT_CONF_SECURITY_MODE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x8)|value<<3) +} +func (o *ECC_Type) GetMULT_CONF_SECURITY_MODE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x8) >> 3 +} +func (o *ECC_Type) SetMULT_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x10)|value<<4) +} +func (o *ECC_Type) GetMULT_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x10) >> 4 +} +func (o *ECC_Type) SetMULT_CONF_WORK_MODE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0xe0)|value<<5) +} +func (o *ECC_Type) GetMULT_CONF_WORK_MODE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0xe0) >> 5 +} +func (o *ECC_Type) SetMULT_CONF_VERIFICATION_RESULT(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x100)|value<<8) +} +func (o *ECC_Type) GetMULT_CONF_VERIFICATION_RESULT() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x100) >> 8 +} +func (o *ECC_Type) SetMULT_CONF_MEM_CLOCK_GATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *ECC_Type) GetMULT_CONF_MEM_CLOCK_GATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x80000000) >> 31 +} + +// ECC.MULT_DATE: Version control register +func (o *ECC_Type) SetMULT_DATE_DATE(value uint32) { + volatile.StoreUint32(&o.MULT_DATE.Reg, volatile.LoadUint32(&o.MULT_DATE.Reg)&^(0xfffffff)|value) +} +func (o *ECC_Type) GetMULT_DATE_DATE() uint32 { + return volatile.LoadUint32(&o.MULT_DATE.Reg) & 0xfffffff +} + +// eFuse Controller +type EFUSE_Type struct { + PGM_DATA0 volatile.Register32 // 0x0 + PGM_DATA1 volatile.Register32 // 0x4 + PGM_DATA2 volatile.Register32 // 0x8 + PGM_DATA3 volatile.Register32 // 0xC + PGM_DATA4 volatile.Register32 // 0x10 + PGM_DATA5 volatile.Register32 // 0x14 + PGM_DATA6 volatile.Register32 // 0x18 + PGM_DATA7 volatile.Register32 // 0x1C + PGM_CHECK_VALUE0 volatile.Register32 // 0x20 + PGM_CHECK_VALUE1 volatile.Register32 // 0x24 + PGM_CHECK_VALUE2 volatile.Register32 // 0x28 + RD_WR_DIS volatile.Register32 // 0x2C + RD_REPEAT_DATA0 volatile.Register32 // 0x30 + RD_REPEAT_DATA1 volatile.Register32 // 0x34 + RD_REPEAT_DATA2 volatile.Register32 // 0x38 + RD_REPEAT_DATA3 volatile.Register32 // 0x3C + RD_REPEAT_DATA4 volatile.Register32 // 0x40 + RD_MAC_SPI_SYS_0 volatile.Register32 // 0x44 + RD_MAC_SPI_SYS_1 volatile.Register32 // 0x48 + RD_MAC_SPI_SYS_2 volatile.Register32 // 0x4C + RD_MAC_SPI_SYS_3 volatile.Register32 // 0x50 + RD_MAC_SPI_SYS_4 volatile.Register32 // 0x54 + RD_MAC_SPI_SYS_5 volatile.Register32 // 0x58 + RD_SYS_PART1_DATA0 volatile.Register32 // 0x5C + RD_SYS_PART1_DATA1 volatile.Register32 // 0x60 + RD_SYS_PART1_DATA2 volatile.Register32 // 0x64 + RD_SYS_PART1_DATA3 volatile.Register32 // 0x68 + RD_SYS_PART1_DATA4 volatile.Register32 // 0x6C + RD_SYS_PART1_DATA5 volatile.Register32 // 0x70 + RD_SYS_PART1_DATA6 volatile.Register32 // 0x74 + RD_SYS_PART1_DATA7 volatile.Register32 // 0x78 + RD_USR_DATA0 volatile.Register32 // 0x7C + RD_USR_DATA1 volatile.Register32 // 0x80 + RD_USR_DATA2 volatile.Register32 // 0x84 + RD_USR_DATA3 volatile.Register32 // 0x88 + RD_USR_DATA4 volatile.Register32 // 0x8C + RD_USR_DATA5 volatile.Register32 // 0x90 + RD_USR_DATA6 volatile.Register32 // 0x94 + RD_USR_DATA7 volatile.Register32 // 0x98 + RD_KEY0_DATA0 volatile.Register32 // 0x9C + RD_KEY0_DATA1 volatile.Register32 // 0xA0 + RD_KEY0_DATA2 volatile.Register32 // 0xA4 + RD_KEY0_DATA3 volatile.Register32 // 0xA8 + RD_KEY0_DATA4 volatile.Register32 // 0xAC + RD_KEY0_DATA5 volatile.Register32 // 0xB0 + RD_KEY0_DATA6 volatile.Register32 // 0xB4 + RD_KEY0_DATA7 volatile.Register32 // 0xB8 + RD_KEY1_DATA0 volatile.Register32 // 0xBC + RD_KEY1_DATA1 volatile.Register32 // 0xC0 + RD_KEY1_DATA2 volatile.Register32 // 0xC4 + RD_KEY1_DATA3 volatile.Register32 // 0xC8 + RD_KEY1_DATA4 volatile.Register32 // 0xCC + RD_KEY1_DATA5 volatile.Register32 // 0xD0 + RD_KEY1_DATA6 volatile.Register32 // 0xD4 + RD_KEY1_DATA7 volatile.Register32 // 0xD8 + RD_KEY2_DATA0 volatile.Register32 // 0xDC + RD_KEY2_DATA1 volatile.Register32 // 0xE0 + RD_KEY2_DATA2 volatile.Register32 // 0xE4 + RD_KEY2_DATA3 volatile.Register32 // 0xE8 + RD_KEY2_DATA4 volatile.Register32 // 0xEC + RD_KEY2_DATA5 volatile.Register32 // 0xF0 + RD_KEY2_DATA6 volatile.Register32 // 0xF4 + RD_KEY2_DATA7 volatile.Register32 // 0xF8 + RD_KEY3_DATA0 volatile.Register32 // 0xFC + RD_KEY3_DATA1 volatile.Register32 // 0x100 + RD_KEY3_DATA2 volatile.Register32 // 0x104 + RD_KEY3_DATA3 volatile.Register32 // 0x108 + RD_KEY3_DATA4 volatile.Register32 // 0x10C + RD_KEY3_DATA5 volatile.Register32 // 0x110 + RD_KEY3_DATA6 volatile.Register32 // 0x114 + RD_KEY3_DATA7 volatile.Register32 // 0x118 + RD_KEY4_DATA0 volatile.Register32 // 0x11C + RD_KEY4_DATA1 volatile.Register32 // 0x120 + RD_KEY4_DATA2 volatile.Register32 // 0x124 + RD_KEY4_DATA3 volatile.Register32 // 0x128 + RD_KEY4_DATA4 volatile.Register32 // 0x12C + RD_KEY4_DATA5 volatile.Register32 // 0x130 + RD_KEY4_DATA6 volatile.Register32 // 0x134 + RD_KEY4_DATA7 volatile.Register32 // 0x138 + RD_KEY5_DATA0 volatile.Register32 // 0x13C + RD_KEY5_DATA1 volatile.Register32 // 0x140 + RD_KEY5_DATA2 volatile.Register32 // 0x144 + RD_KEY5_DATA3 volatile.Register32 // 0x148 + RD_KEY5_DATA4 volatile.Register32 // 0x14C + RD_KEY5_DATA5 volatile.Register32 // 0x150 + RD_KEY5_DATA6 volatile.Register32 // 0x154 + RD_KEY5_DATA7 volatile.Register32 // 0x158 + RD_SYS_PART2_DATA0 volatile.Register32 // 0x15C + RD_SYS_PART2_DATA1 volatile.Register32 // 0x160 + RD_SYS_PART2_DATA2 volatile.Register32 // 0x164 + RD_SYS_PART2_DATA3 volatile.Register32 // 0x168 + RD_SYS_PART2_DATA4 volatile.Register32 // 0x16C + RD_SYS_PART2_DATA5 volatile.Register32 // 0x170 + RD_SYS_PART2_DATA6 volatile.Register32 // 0x174 + RD_SYS_PART2_DATA7 volatile.Register32 // 0x178 + RD_REPEAT_ERR0 volatile.Register32 // 0x17C + RD_REPEAT_ERR1 volatile.Register32 // 0x180 + RD_REPEAT_ERR2 volatile.Register32 // 0x184 + RD_REPEAT_ERR3 volatile.Register32 // 0x188 + _ [4]byte + RD_REPEAT_ERR4 volatile.Register32 // 0x190 + _ [44]byte + RD_RS_ERR0 volatile.Register32 // 0x1C0 + RD_RS_ERR1 volatile.Register32 // 0x1C4 + CLK volatile.Register32 // 0x1C8 + CONF volatile.Register32 // 0x1CC + STATUS volatile.Register32 // 0x1D0 + CMD volatile.Register32 // 0x1D4 + INT_RAW volatile.Register32 // 0x1D8 + INT_ST volatile.Register32 // 0x1DC + INT_ENA volatile.Register32 // 0x1E0 + INT_CLR volatile.Register32 // 0x1E4 + DAC_CONF volatile.Register32 // 0x1E8 + RD_TIM_CONF volatile.Register32 // 0x1EC + WR_TIM_CONF1 volatile.Register32 // 0x1F0 + WR_TIM_CONF2 volatile.Register32 // 0x1F4 + WR_TIM_CONF0_RS_BYPASS volatile.Register32 // 0x1F8 + DATE volatile.Register32 // 0x1FC +} + +// EFUSE.PGM_DATA0: Register 0 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA0(value uint32) { + volatile.StoreUint32(&o.PGM_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA0() uint32 { + return volatile.LoadUint32(&o.PGM_DATA0.Reg) +} + +// EFUSE.PGM_DATA1: Register 1 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA1(value uint32) { + volatile.StoreUint32(&o.PGM_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA1() uint32 { + return volatile.LoadUint32(&o.PGM_DATA1.Reg) +} + +// EFUSE.PGM_DATA2: Register 2 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA2(value uint32) { + volatile.StoreUint32(&o.PGM_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA2() uint32 { + return volatile.LoadUint32(&o.PGM_DATA2.Reg) +} + +// EFUSE.PGM_DATA3: Register 3 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA3(value uint32) { + volatile.StoreUint32(&o.PGM_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA3() uint32 { + return volatile.LoadUint32(&o.PGM_DATA3.Reg) +} + +// EFUSE.PGM_DATA4: Register 4 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA4(value uint32) { + volatile.StoreUint32(&o.PGM_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA4() uint32 { + return volatile.LoadUint32(&o.PGM_DATA4.Reg) +} + +// EFUSE.PGM_DATA5: Register 5 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA5(value uint32) { + volatile.StoreUint32(&o.PGM_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA5() uint32 { + return volatile.LoadUint32(&o.PGM_DATA5.Reg) +} + +// EFUSE.PGM_DATA6: Register 6 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA6(value uint32) { + volatile.StoreUint32(&o.PGM_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA6() uint32 { + return volatile.LoadUint32(&o.PGM_DATA6.Reg) +} + +// EFUSE.PGM_DATA7: Register 7 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA7(value uint32) { + volatile.StoreUint32(&o.PGM_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA7() uint32 { + return volatile.LoadUint32(&o.PGM_DATA7.Reg) +} + +// EFUSE.PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE0(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE0() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE0.Reg) +} + +// EFUSE.PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE1(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE1() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE1.Reg) +} + +// EFUSE.PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE2(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE2() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE2.Reg) +} + +// EFUSE.RD_WR_DIS: BLOCK0 data register 0. +func (o *EFUSE_Type) SetRD_WR_DIS(value uint32) { + volatile.StoreUint32(&o.RD_WR_DIS.Reg, value) +} +func (o *EFUSE_Type) GetRD_WR_DIS() uint32 { + return volatile.LoadUint32(&o.RD_WR_DIS.Reg) +} + +// EFUSE.RD_REPEAT_DATA0: BLOCK0 data register 1. +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RD_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RD_DIS() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SWAP_UART_SDIO_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SWAP_UART_SDIO_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_CAN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_CAN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_JTAG_SEL_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_JTAG_SEL_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SOFT_DIS_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SOFT_DIS_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_PAD_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_PAD_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_VDD_SPI_AS_GPIO(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_VDD_SPI_AS_GPIO() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED0_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED0_2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED0_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED0_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED0_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED0_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_DATA1: BLOCK0 data register 2. +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_RPT4_RESERVED1_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_RPT4_RESERVED1_0() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_WDT_DELAY_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_WDT_DELAY_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA2: BLOCK0 data register 3. +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_2() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_DPA_SEC_LEVEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_DPA_SEC_LEVEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_RPT4_RESERVED2_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_RPT4_RESERVED2_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_CRYPT_DPA_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_CRYPT_DPA_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_RPT4_RESERVED2_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xfc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_RPT4_RESERVED2_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xfc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_TPUW(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_TPUW() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA3: BLOCK0 data register 4. +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DIRECT_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DIRECT_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_PRINT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_PRINT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED3_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED3_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CONTROL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CONTROL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED3_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED3_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED3_3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED3_3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED3_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc00)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED3_2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc00) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED3_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED3_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FORCE_SEND_RESUME(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FORCE_SEND_RESUME() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_VERSION(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x3fffc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_VERSION() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x3fffc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x40000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x40000000) >> 30 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED3_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x80000000)|value<<31) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED3_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x80000000) >> 31 +} + +// EFUSE.RD_REPEAT_DATA4: BLOCK0 data register 5. +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_RPT4_RESERVED4_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_RPT4_RESERVED4_1() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xffffff +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_RPT4_RESERVED4_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_RPT4_RESERVED4_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xff000000) >> 24 +} + +// EFUSE.RD_MAC_SPI_SYS_0: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_0.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_0() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_0.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_1: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_1_MAC_1(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_1_MAC_1() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_1_MAC_EXT(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_1_MAC_EXT() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.RD_MAC_SPI_SYS_2: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_2_MAC_SPI_RESERVED(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_2.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_2.Reg)&^(0x3fff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_2_MAC_SPI_RESERVED() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_2.Reg) & 0x3fff +} +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_2_SPI_PAD_CONF_1(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_2.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_2.Reg)&^(0xffffc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_2_SPI_PAD_CONF_1() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SPI_SYS_2.Reg) & 0xffffc000) >> 14 +} + +// EFUSE.RD_MAC_SPI_SYS_3: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_3_SPI_PAD_CONF_2(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg)&^(0x3ffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_3_SPI_PAD_CONF_2() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg) & 0x3ffff +} +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_3_SYS_DATA_PART0_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg)&^(0xfffc0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_3_SYS_DATA_PART0_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg) & 0xfffc0000) >> 18 +} + +// EFUSE.RD_MAC_SPI_SYS_4: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_4(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_4.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_4() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_4.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_5: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_5(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_5.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_5() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA0: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA1: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA2: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA3: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA4: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA5: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA6: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA7: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA7.Reg) +} + +// EFUSE.RD_USR_DATA0: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA0.Reg) +} + +// EFUSE.RD_USR_DATA1: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA1.Reg) +} + +// EFUSE.RD_USR_DATA2: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA2.Reg) +} + +// EFUSE.RD_USR_DATA3: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA3.Reg) +} + +// EFUSE.RD_USR_DATA4: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA4.Reg) +} + +// EFUSE.RD_USR_DATA5: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA5.Reg) +} + +// EFUSE.RD_USR_DATA6: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA6.Reg) +} + +// EFUSE.RD_USR_DATA7: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA7.Reg) +} + +// EFUSE.RD_KEY0_DATA0: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA0.Reg) +} + +// EFUSE.RD_KEY0_DATA1: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA1.Reg) +} + +// EFUSE.RD_KEY0_DATA2: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA2.Reg) +} + +// EFUSE.RD_KEY0_DATA3: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA3.Reg) +} + +// EFUSE.RD_KEY0_DATA4: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA4.Reg) +} + +// EFUSE.RD_KEY0_DATA5: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA5.Reg) +} + +// EFUSE.RD_KEY0_DATA6: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA6.Reg) +} + +// EFUSE.RD_KEY0_DATA7: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA7.Reg) +} + +// EFUSE.RD_KEY1_DATA0: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA0.Reg) +} + +// EFUSE.RD_KEY1_DATA1: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA1.Reg) +} + +// EFUSE.RD_KEY1_DATA2: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA2.Reg) +} + +// EFUSE.RD_KEY1_DATA3: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA3.Reg) +} + +// EFUSE.RD_KEY1_DATA4: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA4.Reg) +} + +// EFUSE.RD_KEY1_DATA5: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA5.Reg) +} + +// EFUSE.RD_KEY1_DATA6: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA6.Reg) +} + +// EFUSE.RD_KEY1_DATA7: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA7.Reg) +} + +// EFUSE.RD_KEY2_DATA0: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA0.Reg) +} + +// EFUSE.RD_KEY2_DATA1: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA1.Reg) +} + +// EFUSE.RD_KEY2_DATA2: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA2.Reg) +} + +// EFUSE.RD_KEY2_DATA3: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA3.Reg) +} + +// EFUSE.RD_KEY2_DATA4: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA4.Reg) +} + +// EFUSE.RD_KEY2_DATA5: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA5.Reg) +} + +// EFUSE.RD_KEY2_DATA6: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA6.Reg) +} + +// EFUSE.RD_KEY2_DATA7: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA7.Reg) +} + +// EFUSE.RD_KEY3_DATA0: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA0.Reg) +} + +// EFUSE.RD_KEY3_DATA1: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA1.Reg) +} + +// EFUSE.RD_KEY3_DATA2: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA2.Reg) +} + +// EFUSE.RD_KEY3_DATA3: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA3.Reg) +} + +// EFUSE.RD_KEY3_DATA4: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA4.Reg) +} + +// EFUSE.RD_KEY3_DATA5: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA5.Reg) +} + +// EFUSE.RD_KEY3_DATA6: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA6.Reg) +} + +// EFUSE.RD_KEY3_DATA7: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA7.Reg) +} + +// EFUSE.RD_KEY4_DATA0: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA0.Reg) +} + +// EFUSE.RD_KEY4_DATA1: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA1.Reg) +} + +// EFUSE.RD_KEY4_DATA2: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA2.Reg) +} + +// EFUSE.RD_KEY4_DATA3: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA3.Reg) +} + +// EFUSE.RD_KEY4_DATA4: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA4.Reg) +} + +// EFUSE.RD_KEY4_DATA5: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA5.Reg) +} + +// EFUSE.RD_KEY4_DATA6: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA6.Reg) +} + +// EFUSE.RD_KEY4_DATA7: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA7.Reg) +} + +// EFUSE.RD_KEY5_DATA0: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA0.Reg) +} + +// EFUSE.RD_KEY5_DATA1: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA1.Reg) +} + +// EFUSE.RD_KEY5_DATA2: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA2.Reg) +} + +// EFUSE.RD_KEY5_DATA3: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA3.Reg) +} + +// EFUSE.RD_KEY5_DATA4: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA4.Reg) +} + +// EFUSE.RD_KEY5_DATA5: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA5.Reg) +} + +// EFUSE.RD_KEY5_DATA6: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA6.Reg) +} + +// EFUSE.RD_KEY5_DATA7: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA7.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA0: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA1: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA2: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA3: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA4: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA5: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA6: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA7: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA7.Reg) +} + +// EFUSE.RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RD_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RD_DIS_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SWAP_UART_SDIO_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SWAP_UART_SDIO_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_TWAI_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_TWAI_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_RPT4_RESERVED1_ERR_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_RPT4_RESERVED1_ERR_0() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_RPT4_RESERVED2_ERR_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xfc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_RPT4_RESERVED2_ERR_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xfc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_TPUW_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_TPUW_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_USB_PRINT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_USB_PRINT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc00)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc00) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_VERSION_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x3fffc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_VERSION_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x3fffc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR_1() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xffffff +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xff000000) >> 24 +} + +// EFUSE.RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700)|value<<8) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700) >> 8 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000)|value<<12) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000) >> 12 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700000)|value<<20) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700000) >> 20 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000000) >> 24 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000000) >> 27 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000000) >> 28 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000000)|value<<31) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000000) >> 31 +} + +// EFUSE.RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x80) >> 7 +} + +// EFUSE.CLK: eFuse clcok configuration register. +func (o *EFUSE_Type) SetCLK_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCLK_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCLK_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCLK_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCLK_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetCLK_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x10000) >> 16 +} + +// EFUSE.CONF: eFuse operation mode configuraiton register +func (o *EFUSE_Type) SetCONF_OP_CODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetCONF_OP_CODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0xffff +} + +// EFUSE.STATUS: eFuse status register. +func (o *EFUSE_Type) SetSTATUS_STATE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetSTATUS_STATE() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xf +} +func (o *EFUSE_Type) SetSTATUS_OTP_LOAD_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetSTATUS_OTP_LOAD_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_C_SYNC2(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_C_SYNC2() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetSTATUS_OTP_STROBE_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetSTATUS_OTP_STROBE_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetSTATUS_OTP_CSB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetSTATUS_OTP_CSB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetSTATUS_OTP_PGENB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetSTATUS_OTP_PGENB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_IS_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_IS_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetSTATUS_BLK0_VALID_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xffc00)|value<<10) +} +func (o *EFUSE_Type) GetSTATUS_BLK0_VALID_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xffc00) >> 10 +} + +// EFUSE.CMD: eFuse command register. +func (o *EFUSE_Type) SetCMD_READ_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCMD_READ_CMD() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCMD_PGM_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCMD_PGM_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCMD_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3c)|value<<2) +} +func (o *EFUSE_Type) GetCMD_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x3c) >> 2 +} + +// EFUSE.INT_RAW: eFuse raw interrupt register. +func (o *EFUSE_Type) SetINT_RAW_READ_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_RAW_READ_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_RAW_PGM_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_RAW_PGM_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ST: eFuse interrupt status register. +func (o *EFUSE_Type) SetINT_ST_READ_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ST_READ_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ST_PGM_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ST_PGM_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ENA: eFuse interrupt enable register. +func (o *EFUSE_Type) SetINT_ENA_READ_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ENA_READ_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ENA_PGM_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ENA_PGM_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_CLR: eFuse interrupt clear register. +func (o *EFUSE_Type) SetINT_CLR_READ_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_CLR_READ_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_CLR_PGM_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_CLR_PGM_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// EFUSE.DAC_CONF: Controls the eFuse programming voltage. +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.DAC_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_PAD_SEL(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_PAD_SEL() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_NUM(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x1fe00)|value<<9) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_NUM() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x1fe00) >> 9 +} +func (o *EFUSE_Type) SetDAC_CONF_OE_CLR(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EFUSE_Type) GetDAC_CONF_OE_CLR() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x20000) >> 17 +} + +// EFUSE.RD_TIM_CONF: Configures read timing parameters. +func (o *EFUSE_Type) SetRD_TIM_CONF_THR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_THR_A() uint32 { + return volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TRD(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TRD() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff00) >> 8 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TSUR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TSUR_A() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff0000) >> 16 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_READ_INIT_NUM(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_READ_INIT_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF1_TSUP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_TSUP_A() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff +} +func (o *EFUSE_Type) SetWR_TIM_CONF1_PWR_ON_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xffff00)|value<<8) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_PWR_ON_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xffff00) >> 8 +} +func (o *EFUSE_Type) SetWR_TIM_CONF1_THP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_THP_A() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF2_PWR_OFF_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_PWR_OFF_NUM() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff +} +func (o *EFUSE_Type) SetWR_TIM_CONF2_TPGM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_TPGM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.WR_TIM_CONF0_RS_BYPASS: Configurarion register0 of eFuse programming time parameters and rs bypass operation. +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0xffe)|value<<1) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0xffe) >> 1 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_UPDATE(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_UPDATE() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1fe000)|value<<13) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1fe000) >> 13 +} + +// EFUSE.DATE: eFuse version register. +func (o *EFUSE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *EFUSE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// External Memory +type EXTMEM_Type struct { + L1_ICACHE_CTRL volatile.Register32 // 0x0 + L1_CACHE_CTRL volatile.Register32 // 0x4 + L1_BYPASS_CACHE_CONF volatile.Register32 // 0x8 + L1_CACHE_ATOMIC_CONF volatile.Register32 // 0xC + L1_ICACHE_CACHESIZE_CONF volatile.Register32 // 0x10 + L1_ICACHE_BLOCKSIZE_CONF volatile.Register32 // 0x14 + L1_CACHE_CACHESIZE_CONF volatile.Register32 // 0x18 + L1_CACHE_BLOCKSIZE_CONF volatile.Register32 // 0x1C + L1_CACHE_WRAP_AROUND_CTRL volatile.Register32 // 0x20 + L1_CACHE_TAG_MEM_POWER_CTRL volatile.Register32 // 0x24 + L1_CACHE_DATA_MEM_POWER_CTRL volatile.Register32 // 0x28 + L1_CACHE_FREEZE_CTRL volatile.Register32 // 0x2C + L1_CACHE_DATA_MEM_ACS_CONF volatile.Register32 // 0x30 + L1_CACHE_TAG_MEM_ACS_CONF volatile.Register32 // 0x34 + L1_ICACHE0_PRELOCK_CONF volatile.Register32 // 0x38 + L1_ICACHE0_PRELOCK_SCT0_ADDR volatile.Register32 // 0x3C + L1_ICACHE0_PRELOCK_SCT1_ADDR volatile.Register32 // 0x40 + L1_ICACHE0_PRELOCK_SCT_SIZE volatile.Register32 // 0x44 + L1_ICACHE1_PRELOCK_CONF volatile.Register32 // 0x48 + L1_ICACHE1_PRELOCK_SCT0_ADDR volatile.Register32 // 0x4C + L1_ICACHE1_PRELOCK_SCT1_ADDR volatile.Register32 // 0x50 + L1_ICACHE1_PRELOCK_SCT_SIZE volatile.Register32 // 0x54 + L1_ICACHE2_PRELOCK_CONF volatile.Register32 // 0x58 + L1_ICACHE2_PRELOCK_SCT0_ADDR volatile.Register32 // 0x5C + L1_ICACHE2_PRELOCK_SCT1_ADDR volatile.Register32 // 0x60 + L1_ICACHE2_PRELOCK_SCT_SIZE volatile.Register32 // 0x64 + L1_ICACHE3_PRELOCK_CONF volatile.Register32 // 0x68 + L1_ICACHE3_PRELOCK_SCT0_ADDR volatile.Register32 // 0x6C + L1_ICACHE3_PRELOCK_SCT1_ADDR volatile.Register32 // 0x70 + L1_ICACHE3_PRELOCK_SCT_SIZE volatile.Register32 // 0x74 + L1_CACHE_PRELOCK_CONF volatile.Register32 // 0x78 + L1_CACHE_PRELOCK_SCT0_ADDR volatile.Register32 // 0x7C + L1_DCACHE_PRELOCK_SCT1_ADDR volatile.Register32 // 0x80 + L1_DCACHE_PRELOCK_SCT_SIZE volatile.Register32 // 0x84 + CACHE_LOCK_CTRL volatile.Register32 // 0x88 + CACHE_LOCK_MAP volatile.Register32 // 0x8C + CACHE_LOCK_ADDR volatile.Register32 // 0x90 + CACHE_LOCK_SIZE volatile.Register32 // 0x94 + CACHE_SYNC_CTRL volatile.Register32 // 0x98 + CACHE_SYNC_MAP volatile.Register32 // 0x9C + CACHE_SYNC_ADDR volatile.Register32 // 0xA0 + CACHE_SYNC_SIZE volatile.Register32 // 0xA4 + L1_ICACHE0_PRELOAD_CTRL volatile.Register32 // 0xA8 + L1_ICACHE0_PRELOAD_ADDR volatile.Register32 // 0xAC + L1_ICACHE0_PRELOAD_SIZE volatile.Register32 // 0xB0 + L1_ICACHE1_PRELOAD_CTRL volatile.Register32 // 0xB4 + L1_ICACHE1_PRELOAD_ADDR volatile.Register32 // 0xB8 + L1_ICACHE1_PRELOAD_SIZE volatile.Register32 // 0xBC + L1_ICACHE2_PRELOAD_CTRL volatile.Register32 // 0xC0 + L1_ICACHE2_PRELOAD_ADDR volatile.Register32 // 0xC4 + L1_ICACHE2_PRELOAD_SIZE volatile.Register32 // 0xC8 + L1_ICACHE3_PRELOAD_CTRL volatile.Register32 // 0xCC + L1_ICACHE3_PRELOAD_ADDR volatile.Register32 // 0xD0 + L1_ICACHE3_PRELOAD_SIZE volatile.Register32 // 0xD4 + L1_CACHE_PRELOAD_CTRL volatile.Register32 // 0xD8 + L1_DCACHE_PRELOAD_ADDR volatile.Register32 // 0xDC + L1_DCACHE_PRELOAD_SIZE volatile.Register32 // 0xE0 + L1_ICACHE0_AUTOLOAD_CTRL volatile.Register32 // 0xE4 + L1_ICACHE0_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0xE8 + L1_ICACHE0_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0xEC + L1_ICACHE0_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0xF0 + L1_ICACHE0_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0xF4 + L1_ICACHE1_AUTOLOAD_CTRL volatile.Register32 // 0xF8 + L1_ICACHE1_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0xFC + L1_ICACHE1_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x100 + L1_ICACHE1_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x104 + L1_ICACHE1_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x108 + L1_ICACHE2_AUTOLOAD_CTRL volatile.Register32 // 0x10C + L1_ICACHE2_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x110 + L1_ICACHE2_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x114 + L1_ICACHE2_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x118 + L1_ICACHE2_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x11C + L1_ICACHE3_AUTOLOAD_CTRL volatile.Register32 // 0x120 + L1_ICACHE3_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x124 + L1_ICACHE3_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x128 + L1_ICACHE3_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x12C + L1_ICACHE3_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x130 + L1_CACHE_AUTOLOAD_CTRL volatile.Register32 // 0x134 + L1_CACHE_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x138 + L1_CACHE_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x13C + L1_CACHE_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x140 + L1_CACHE_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x144 + L1_CACHE_AUTOLOAD_SCT2_ADDR volatile.Register32 // 0x148 + L1_CACHE_AUTOLOAD_SCT2_SIZE volatile.Register32 // 0x14C + L1_CACHE_AUTOLOAD_SCT3_ADDR volatile.Register32 // 0x150 + L1_CACHE_AUTOLOAD_SCT3_SIZE volatile.Register32 // 0x154 + L1_CACHE_ACS_CNT_INT_ENA volatile.Register32 // 0x158 + L1_CACHE_ACS_CNT_INT_CLR volatile.Register32 // 0x15C + L1_CACHE_ACS_CNT_INT_RAW volatile.Register32 // 0x160 + L1_CACHE_ACS_CNT_INT_ST volatile.Register32 // 0x164 + L1_CACHE_ACS_FAIL_INT_ENA volatile.Register32 // 0x168 + L1_CACHE_ACS_FAIL_INT_CLR volatile.Register32 // 0x16C + L1_CACHE_ACS_FAIL_INT_RAW volatile.Register32 // 0x170 + L1_CACHE_ACS_FAIL_INT_ST volatile.Register32 // 0x174 + L1_CACHE_ACS_CNT_CTRL volatile.Register32 // 0x178 + L1_IBUS0_ACS_HIT_CNT volatile.Register32 // 0x17C + L1_IBUS0_ACS_MISS_CNT volatile.Register32 // 0x180 + L1_IBUS0_ACS_CONFLICT_CNT volatile.Register32 // 0x184 + L1_IBUS0_ACS_NXTLVL_CNT volatile.Register32 // 0x188 + L1_IBUS1_ACS_HIT_CNT volatile.Register32 // 0x18C + L1_IBUS1_ACS_MISS_CNT volatile.Register32 // 0x190 + L1_IBUS1_ACS_CONFLICT_CNT volatile.Register32 // 0x194 + L1_IBUS1_ACS_NXTLVL_CNT volatile.Register32 // 0x198 + L1_IBUS2_ACS_HIT_CNT volatile.Register32 // 0x19C + L1_IBUS2_ACS_MISS_CNT volatile.Register32 // 0x1A0 + L1_IBUS2_ACS_CONFLICT_CNT volatile.Register32 // 0x1A4 + L1_IBUS2_ACS_NXTLVL_CNT volatile.Register32 // 0x1A8 + L1_IBUS3_ACS_HIT_CNT volatile.Register32 // 0x1AC + L1_IBUS3_ACS_MISS_CNT volatile.Register32 // 0x1B0 + L1_IBUS3_ACS_CONFLICT_CNT volatile.Register32 // 0x1B4 + L1_IBUS3_ACS_NXTLVL_CNT volatile.Register32 // 0x1B8 + L1_BUS0_ACS_HIT_CNT volatile.Register32 // 0x1BC + L1_BUS0_ACS_MISS_CNT volatile.Register32 // 0x1C0 + L1_BUS0_ACS_CONFLICT_CNT volatile.Register32 // 0x1C4 + L1_BUS0_ACS_NXTLVL_CNT volatile.Register32 // 0x1C8 + L1_BUS1_ACS_HIT_CNT volatile.Register32 // 0x1CC + L1_BUS1_ACS_MISS_CNT volatile.Register32 // 0x1D0 + L1_BUS1_ACS_CONFLICT_CNT volatile.Register32 // 0x1D4 + L1_BUS1_ACS_NXTLVL_CNT volatile.Register32 // 0x1D8 + L1_DBUS2_ACS_HIT_CNT volatile.Register32 // 0x1DC + L1_DBUS2_ACS_MISS_CNT volatile.Register32 // 0x1E0 + L1_DBUS2_ACS_CONFLICT_CNT volatile.Register32 // 0x1E4 + L1_DBUS2_ACS_NXTLVL_CNT volatile.Register32 // 0x1E8 + L1_DBUS3_ACS_HIT_CNT volatile.Register32 // 0x1EC + L1_DBUS3_ACS_MISS_CNT volatile.Register32 // 0x1F0 + L1_DBUS3_ACS_CONFLICT_CNT volatile.Register32 // 0x1F4 + L1_DBUS3_ACS_NXTLVL_CNT volatile.Register32 // 0x1F8 + L1_ICACHE0_ACS_FAIL_ID_ATTR volatile.Register32 // 0x1FC + L1_ICACHE0_ACS_FAIL_ADDR volatile.Register32 // 0x200 + L1_ICACHE1_ACS_FAIL_ID_ATTR volatile.Register32 // 0x204 + L1_ICACHE1_ACS_FAIL_ADDR volatile.Register32 // 0x208 + L1_ICACHE2_ACS_FAIL_ID_ATTR volatile.Register32 // 0x20C + L1_ICACHE2_ACS_FAIL_ADDR volatile.Register32 // 0x210 + L1_ICACHE3_ACS_FAIL_ID_ATTR volatile.Register32 // 0x214 + L1_ICACHE3_ACS_FAIL_ADDR volatile.Register32 // 0x218 + L1_CACHE_ACS_FAIL_ID_ATTR volatile.Register32 // 0x21C + L1_DCACHE_ACS_FAIL_ADDR volatile.Register32 // 0x220 + L1_CACHE_SYNC_PRELOAD_INT_ENA volatile.Register32 // 0x224 + L1_CACHE_SYNC_PRELOAD_INT_CLR volatile.Register32 // 0x228 + L1_CACHE_SYNC_PRELOAD_INT_RAW volatile.Register32 // 0x22C + L1_CACHE_SYNC_PRELOAD_INT_ST volatile.Register32 // 0x230 + L1_CACHE_SYNC_PRELOAD_EXCEPTION volatile.Register32 // 0x234 + L1_CACHE_SYNC_RST_CTRL volatile.Register32 // 0x238 + L1_CACHE_PRELOAD_RST_CTRL volatile.Register32 // 0x23C + L1_CACHE_AUTOLOAD_BUF_CLR_CTRL volatile.Register32 // 0x240 + L1_UNALLOCATE_BUFFER_CLEAR volatile.Register32 // 0x244 + L1_CACHE_OBJECT_CTRL volatile.Register32 // 0x248 + L1_CACHE_WAY_OBJECT volatile.Register32 // 0x24C + L1_CACHE_VADDR volatile.Register32 // 0x250 + L1_CACHE_DEBUG_BUS volatile.Register32 // 0x254 + LEVEL_SPLIT0 volatile.Register32 // 0x258 + L2_CACHE_CTRL volatile.Register32 // 0x25C + L2_BYPASS_CACHE_CONF volatile.Register32 // 0x260 + L2_CACHE_CACHESIZE_CONF volatile.Register32 // 0x264 + L2_CACHE_BLOCKSIZE_CONF volatile.Register32 // 0x268 + L2_CACHE_WRAP_AROUND_CTRL volatile.Register32 // 0x26C + L2_CACHE_TAG_MEM_POWER_CTRL volatile.Register32 // 0x270 + L2_CACHE_DATA_MEM_POWER_CTRL volatile.Register32 // 0x274 + L2_CACHE_FREEZE_CTRL volatile.Register32 // 0x278 + L2_CACHE_DATA_MEM_ACS_CONF volatile.Register32 // 0x27C + L2_CACHE_TAG_MEM_ACS_CONF volatile.Register32 // 0x280 + L2_CACHE_PRELOCK_CONF volatile.Register32 // 0x284 + L2_CACHE_PRELOCK_SCT0_ADDR volatile.Register32 // 0x288 + L2_CACHE_PRELOCK_SCT1_ADDR volatile.Register32 // 0x28C + L2_CACHE_PRELOCK_SCT_SIZE volatile.Register32 // 0x290 + L2_CACHE_PRELOAD_CTRL volatile.Register32 // 0x294 + L2_CACHE_PRELOAD_ADDR volatile.Register32 // 0x298 + L2_CACHE_PRELOAD_SIZE volatile.Register32 // 0x29C + L2_CACHE_AUTOLOAD_CTRL volatile.Register32 // 0x2A0 + L2_CACHE_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x2A4 + L2_CACHE_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x2A8 + L2_CACHE_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x2AC + L2_CACHE_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x2B0 + L2_CACHE_AUTOLOAD_SCT2_ADDR volatile.Register32 // 0x2B4 + L2_CACHE_AUTOLOAD_SCT2_SIZE volatile.Register32 // 0x2B8 + L2_CACHE_AUTOLOAD_SCT3_ADDR volatile.Register32 // 0x2BC + L2_CACHE_AUTOLOAD_SCT3_SIZE volatile.Register32 // 0x2C0 + L2_CACHE_ACS_CNT_INT_ENA volatile.Register32 // 0x2C4 + L2_CACHE_ACS_CNT_INT_CLR volatile.Register32 // 0x2C8 + L2_CACHE_ACS_CNT_INT_RAW volatile.Register32 // 0x2CC + L2_CACHE_ACS_CNT_INT_ST volatile.Register32 // 0x2D0 + L2_CACHE_ACS_FAIL_INT_ENA volatile.Register32 // 0x2D4 + L2_CACHE_ACS_FAIL_INT_CLR volatile.Register32 // 0x2D8 + L2_CACHE_ACS_FAIL_INT_RAW volatile.Register32 // 0x2DC + L2_CACHE_ACS_FAIL_INT_ST volatile.Register32 // 0x2E0 + L2_CACHE_ACS_CNT_CTRL volatile.Register32 // 0x2E4 + L2_IBUS0_ACS_HIT_CNT volatile.Register32 // 0x2E8 + L2_IBUS0_ACS_MISS_CNT volatile.Register32 // 0x2EC + L2_IBUS0_ACS_CONFLICT_CNT volatile.Register32 // 0x2F0 + L2_IBUS0_ACS_NXTLVL_CNT volatile.Register32 // 0x2F4 + L2_IBUS1_ACS_HIT_CNT volatile.Register32 // 0x2F8 + L2_IBUS1_ACS_MISS_CNT volatile.Register32 // 0x2FC + L2_IBUS1_ACS_CONFLICT_CNT volatile.Register32 // 0x300 + L2_IBUS1_ACS_NXTLVL_CNT volatile.Register32 // 0x304 + L2_IBUS2_ACS_HIT_CNT volatile.Register32 // 0x308 + L2_IBUS2_ACS_MISS_CNT volatile.Register32 // 0x30C + L2_IBUS2_ACS_CONFLICT_CNT volatile.Register32 // 0x310 + L2_IBUS2_ACS_NXTLVL_CNT volatile.Register32 // 0x314 + L2_IBUS3_ACS_HIT_CNT volatile.Register32 // 0x318 + L2_IBUS3_ACS_MISS_CNT volatile.Register32 // 0x31C + L2_IBUS3_ACS_CONFLICT_CNT volatile.Register32 // 0x320 + L2_IBUS3_ACS_NXTLVL_CNT volatile.Register32 // 0x324 + L2_DBUS0_ACS_HIT_CNT volatile.Register32 // 0x328 + L2_DBUS0_ACS_MISS_CNT volatile.Register32 // 0x32C + L2_DBUS0_ACS_CONFLICT_CNT volatile.Register32 // 0x330 + L2_DBUS0_ACS_NXTLVL_CNT volatile.Register32 // 0x334 + L2_DBUS1_ACS_HIT_CNT volatile.Register32 // 0x338 + L2_DBUS1_ACS_MISS_CNT volatile.Register32 // 0x33C + L2_DBUS1_ACS_CONFLICT_CNT volatile.Register32 // 0x340 + L2_DBUS1_ACS_NXTLVL_CNT volatile.Register32 // 0x344 + L2_DBUS2_ACS_HIT_CNT volatile.Register32 // 0x348 + L2_DBUS2_ACS_MISS_CNT volatile.Register32 // 0x34C + L2_DBUS2_ACS_CONFLICT_CNT volatile.Register32 // 0x350 + L2_DBUS2_ACS_NXTLVL_CNT volatile.Register32 // 0x354 + L2_DBUS3_ACS_HIT_CNT volatile.Register32 // 0x358 + L2_DBUS3_ACS_MISS_CNT volatile.Register32 // 0x35C + L2_DBUS3_ACS_CONFLICT_CNT volatile.Register32 // 0x360 + L2_DBUS3_ACS_NXTLVL_CNT volatile.Register32 // 0x364 + L2_CACHE_ACS_FAIL_ID_ATTR volatile.Register32 // 0x368 + L2_CACHE_ACS_FAIL_ADDR volatile.Register32 // 0x36C + L2_CACHE_SYNC_PRELOAD_INT_ENA volatile.Register32 // 0x370 + L2_CACHE_SYNC_PRELOAD_INT_CLR volatile.Register32 // 0x374 + L2_CACHE_SYNC_PRELOAD_INT_RAW volatile.Register32 // 0x378 + L2_CACHE_SYNC_PRELOAD_INT_ST volatile.Register32 // 0x37C + L2_CACHE_SYNC_PRELOAD_EXCEPTION volatile.Register32 // 0x380 + L2_CACHE_SYNC_RST_CTRL volatile.Register32 // 0x384 + L2_CACHE_PRELOAD_RST_CTRL volatile.Register32 // 0x388 + L2_CACHE_AUTOLOAD_BUF_CLR_CTRL volatile.Register32 // 0x38C + L2_UNALLOCATE_BUFFER_CLEAR volatile.Register32 // 0x390 + L2_CACHE_ACCESS_ATTR_CTRL volatile.Register32 // 0x394 + L2_CACHE_OBJECT_CTRL volatile.Register32 // 0x398 + L2_CACHE_WAY_OBJECT volatile.Register32 // 0x39C + L2_CACHE_VADDR volatile.Register32 // 0x3A0 + L2_CACHE_DEBUG_BUS volatile.Register32 // 0x3A4 + LEVEL_SPLIT1 volatile.Register32 // 0x3A8 + CLOCK_GATE volatile.Register32 // 0x3AC + REDUNDANCY_SIG0 volatile.Register32 // 0x3B0 + REDUNDANCY_SIG1 volatile.Register32 // 0x3B4 + REDUNDANCY_SIG2 volatile.Register32 // 0x3B8 + REDUNDANCY_SIG3 volatile.Register32 // 0x3BC + REDUNDANCY_SIG4 volatile.Register32 // 0x3C0 + _ [56]byte + DATE volatile.Register32 // 0x3FC +} + +// EXTMEM.L1_ICACHE_CTRL: L1 instruction Cache(L1-ICache) control register +func (o *EXTMEM_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0xf0)|value<<4) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0xf0) >> 4 +} + +// EXTMEM.L1_CACHE_CTRL: L1 data Cache(L1-Cache) control register +func (o *EXTMEM_Type) SetL1_CACHE_CTRL_L1_CACHE_SHUT_BUS0(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_CTRL_L1_CACHE_SHUT_BUS0() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_CTRL_L1_CACHE_SHUT_BUS1(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_CTRL_L1_CACHE_SHUT_BUS1() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_CTRL_L1_CACHE_SHUT_DBUS2(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_CTRL_L1_CACHE_SHUT_DBUS2() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_CTRL_L1_CACHE_SHUT_DBUS3(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_CTRL_L1_CACHE_SHUT_DBUS3() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_CTRL_L1_CACHE_SHUT_DMA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_CTRL_L1_CACHE_SHUT_DMA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_CTRL_L1_CACHE_UNDEF_OP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg)&^(0xf00)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_CTRL_L1_CACHE_UNDEF_OP() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CTRL.Reg) & 0xf00) >> 8 +} + +// EXTMEM.L1_BYPASS_CACHE_CONF: Bypass Cache configure register +func (o *EXTMEM_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN() uint32 { + return volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN() uint32 { + return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN() uint32 { + return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_CACHE_ATOMIC_CONF: L1 Cache atomic feature configure register +func (o *EXTMEM_Type) SetL1_CACHE_ATOMIC_CONF_L1_CACHE_ATOMIC_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ATOMIC_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_ATOMIC_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ATOMIC_CONF_L1_CACHE_ATOMIC_EN() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ATOMIC_CONF.Reg) & 0x1 +} + +// EXTMEM.L1_ICACHE_CACHESIZE_CONF: L1 instruction Cache CacheSize mode configure register +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2048K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2048K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4096K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4096K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x1000) >> 12 +} + +// EXTMEM.L1_ICACHE_BLOCKSIZE_CONF: L1 instruction Cache BlockSize mode configure register +func (o *EXTMEM_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x20) >> 5 +} + +// EXTMEM.L1_CACHE_CACHESIZE_CONF: L1 data Cache CacheSize mode configure register +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1K() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_8K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_8K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_16K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_16K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_32K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_32K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_64K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_64K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_128K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_128K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_256K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_256K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_512K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_512K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1024K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1024K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2048K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2048K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4096K(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4096K() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_CACHESIZE_CONF.Reg) & 0x1000) >> 12 +} + +// EXTMEM.L1_CACHE_BLOCKSIZE_CONF: L1 data Cache BlockSize mode configure register +func (o *EXTMEM_Type) SetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_8(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_8() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_16(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_16() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_32(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_32() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_64(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_64() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_128(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_128() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_256(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_256() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_BLOCKSIZE_CONF.Reg) & 0x20) >> 5 +} + +// EXTMEM.L1_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register +func (o *EXTMEM_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_CACHE_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_CACHE_WRAP() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x10000) >> 16 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x20000) >> 17 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x40000) >> 18 +} + +// EXTMEM.L1_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x10000) >> 16 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x20000) >> 17 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x40000) >> 18 +} + +// EXTMEM.L1_CACHE_FREEZE_CTRL: Cache Freeze control register +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x10000) >> 16 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x20000) >> 17 +} +func (o *EXTMEM_Type) SetL1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *EXTMEM_Type) GetL1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x40000) >> 18 +} + +// EXTMEM.L1_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x10000) >> 16 +} +func (o *EXTMEM_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EXTMEM_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x20000) >> 17 +} + +// EXTMEM.L1_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x10000) >> 16 +} +func (o *EXTMEM_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EXTMEM_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x20000) >> 17 +} + +// EXTMEM.L1_ICACHE0_PRELOCK_CONF: L1 instruction Cache 0 prelock configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// EXTMEM.L1_ICACHE0_PRELOCK_SCT0_ADDR: L1 instruction Cache 0 prelock section0 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE0_PRELOCK_SCT1_ADDR: L1 instruction Cache 0 prelock section1 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE0_PRELOCK_SCT_SIZE: L1 instruction Cache 0 prelock section size configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// EXTMEM.L1_ICACHE1_PRELOCK_CONF: L1 instruction Cache 1 prelock configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// EXTMEM.L1_ICACHE1_PRELOCK_SCT0_ADDR: L1 instruction Cache 1 prelock section0 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE1_PRELOCK_SCT1_ADDR: L1 instruction Cache 1 prelock section1 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE1_PRELOCK_SCT_SIZE: L1 instruction Cache 1 prelock section size configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// EXTMEM.L1_ICACHE2_PRELOCK_CONF: L1 instruction Cache 2 prelock configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// EXTMEM.L1_ICACHE2_PRELOCK_SCT0_ADDR: L1 instruction Cache 2 prelock section0 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE2_PRELOCK_SCT1_ADDR: L1 instruction Cache 2 prelock section1 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE2_PRELOCK_SCT_SIZE: L1 instruction Cache 2 prelock section size configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// EXTMEM.L1_ICACHE3_PRELOCK_CONF: L1 instruction Cache 3 prelock configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// EXTMEM.L1_ICACHE3_PRELOCK_SCT0_ADDR: L1 instruction Cache 3 prelock section0 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE3_PRELOCK_SCT1_ADDR: L1 instruction Cache 3 prelock section1 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE3_PRELOCK_SCT_SIZE: L1 instruction Cache 3 prelock section size configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// EXTMEM.L1_CACHE_PRELOCK_CONF: L1 Cache prelock configure register +func (o *EXTMEM_Type) SetL1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_PRELOCK_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// EXTMEM.L1_CACHE_PRELOCK_SCT0_ADDR: L1 Cache prelock section0 address configure register +func (o *EXTMEM_Type) SetL1_CACHE_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_PRELOCK_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_DCACHE_PRELOCK_SCT1_ADDR: L1 Cache prelock section1 address configure register +func (o *EXTMEM_Type) SetL1_DCACHE_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DCACHE_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_DCACHE_PRELOCK_SCT_SIZE: L1 Cache prelock section size configure register +func (o *EXTMEM_Type) SetL1_DCACHE_PRELOCK_SCT_SIZE_L1_CACHE_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_DCACHE_PRELOCK_SCT_SIZE_L1_CACHE_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *EXTMEM_Type) SetL1_DCACHE_PRELOCK_SCT_SIZE_L1_CACHE_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_DCACHE_PRELOCK_SCT_SIZE_L1_CACHE_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// EXTMEM.CACHE_LOCK_CTRL: Lock-class (manual lock) operation control register +func (o *EXTMEM_Type) SetCACHE_LOCK_CTRL_CACHE_LOCK_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.CACHE_LOCK_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_LOCK_CTRL_CACHE_LOCK_ENA() uint32 { + return volatile.LoadUint32(&o.CACHE_LOCK_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_LOCK_CTRL_CACHE_UNLOCK_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.CACHE_LOCK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_LOCK_CTRL_CACHE_UNLOCK_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_LOCK_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_LOCK_CTRL_CACHE_LOCK_DONE(value uint32) { + volatile.StoreUint32(&o.CACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.CACHE_LOCK_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_LOCK_CTRL_CACHE_LOCK_DONE() uint32 { + return (volatile.LoadUint32(&o.CACHE_LOCK_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_LOCK_CTRL_CACHE_LOCK_RGID(value uint32) { + volatile.StoreUint32(&o.CACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.CACHE_LOCK_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_LOCK_CTRL_CACHE_LOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.CACHE_LOCK_CTRL.Reg) & 0x78) >> 3 +} + +// EXTMEM.CACHE_LOCK_MAP: Lock (manual lock) map configure register +func (o *EXTMEM_Type) SetCACHE_LOCK_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_LOCK_MAP.Reg, volatile.LoadUint32(&o.CACHE_LOCK_MAP.Reg)&^(0x3f)|value) +} +func (o *EXTMEM_Type) GetCACHE_LOCK_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_LOCK_MAP.Reg) & 0x3f +} + +// EXTMEM.CACHE_LOCK_ADDR: Lock (manual lock) address configure register +func (o *EXTMEM_Type) SetCACHE_LOCK_ADDR(value uint32) { + volatile.StoreUint32(&o.CACHE_LOCK_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCACHE_LOCK_ADDR() uint32 { + return volatile.LoadUint32(&o.CACHE_LOCK_ADDR.Reg) +} + +// EXTMEM.CACHE_LOCK_SIZE: Lock (manual lock) size configure register +func (o *EXTMEM_Type) SetCACHE_LOCK_SIZE(value uint32) { + volatile.StoreUint32(&o.CACHE_LOCK_SIZE.Reg, volatile.LoadUint32(&o.CACHE_LOCK_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetCACHE_LOCK_SIZE() uint32 { + return volatile.LoadUint32(&o.CACHE_LOCK_SIZE.Reg) & 0xffff +} + +// EXTMEM.CACHE_SYNC_CTRL: Sync-class operation control register +func (o *EXTMEM_Type) SetCACHE_SYNC_CTRL_CACHE_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_CTRL_CACHE_INVALIDATE_ENA() uint32 { + return volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_CTRL_CACHE_CLEAN_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_CTRL_CACHE_CLEAN_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_CTRL_CACHE_WRITEBACK_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_CTRL_CACHE_WRITEBACK_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_CTRL_CACHE_WRITEBACK_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_CTRL_CACHE_WRITEBACK_INVALIDATE_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_CTRL_CACHE_SYNC_DONE(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_CTRL_CACHE_SYNC_DONE() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_CTRL_CACHE_SYNC_RGID(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg)&^(0x1e0)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_CTRL_CACHE_SYNC_RGID() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_CTRL.Reg) & 0x1e0) >> 5 +} + +// EXTMEM.CACHE_SYNC_MAP: Sync map configure register +func (o *EXTMEM_Type) SetCACHE_SYNC_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_MAP.Reg, volatile.LoadUint32(&o.CACHE_SYNC_MAP.Reg)&^(0x3f)|value) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_SYNC_MAP.Reg) & 0x3f +} + +// EXTMEM.CACHE_SYNC_ADDR: Sync address configure register +func (o *EXTMEM_Type) SetCACHE_SYNC_ADDR(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_ADDR() uint32 { + return volatile.LoadUint32(&o.CACHE_SYNC_ADDR.Reg) +} + +// EXTMEM.CACHE_SYNC_SIZE: Sync size configure register +func (o *EXTMEM_Type) SetCACHE_SYNC_SIZE(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_SIZE.Reg, volatile.LoadUint32(&o.CACHE_SYNC_SIZE.Reg)&^(0xffffff)|value) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_SIZE() uint32 { + return volatile.LoadUint32(&o.CACHE_SYNC_SIZE.Reg) & 0xffffff +} + +// EXTMEM.L1_ICACHE0_PRELOAD_CTRL: L1 instruction Cache 0 preload-operation control register +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// EXTMEM.L1_ICACHE0_PRELOAD_ADDR: L1 instruction Cache 0 preload address configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE0_PRELOAD_SIZE: L1 instruction Cache 0 preload size configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_SIZE.Reg) & 0x3fff +} + +// EXTMEM.L1_ICACHE1_PRELOAD_CTRL: L1 instruction Cache 1 preload-operation control register +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// EXTMEM.L1_ICACHE1_PRELOAD_ADDR: L1 instruction Cache 1 preload address configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE1_PRELOAD_SIZE: L1 instruction Cache 1 preload size configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_SIZE.Reg) & 0x3fff +} + +// EXTMEM.L1_ICACHE2_PRELOAD_CTRL: L1 instruction Cache 2 preload-operation control register +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// EXTMEM.L1_ICACHE2_PRELOAD_ADDR: L1 instruction Cache 2 preload address configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE2_PRELOAD_SIZE: L1 instruction Cache 2 preload size configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_SIZE.Reg) & 0x3fff +} + +// EXTMEM.L1_ICACHE3_PRELOAD_CTRL: L1 instruction Cache 3 preload-operation control register +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// EXTMEM.L1_ICACHE3_PRELOAD_ADDR: L1 instruction Cache 3 preload address configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE3_PRELOAD_SIZE: L1 instruction Cache 3 preload size configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_SIZE.Reg) & 0x3fff +} + +// EXTMEM.L1_CACHE_PRELOAD_CTRL: L1 Cache preload-operation control register +func (o *EXTMEM_Type) SetL1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// EXTMEM.L1_DCACHE_PRELOAD_ADDR: L1 Cache preload address configure register +func (o *EXTMEM_Type) SetL1_DCACHE_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DCACHE_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_ADDR.Reg) +} + +// EXTMEM.L1_DCACHE_PRELOAD_SIZE: L1 Cache preload size configure register +func (o *EXTMEM_Type) SetL1_DCACHE_PRELOAD_SIZE_L1_CACHE_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *EXTMEM_Type) GetL1_DCACHE_PRELOAD_SIZE_L1_CACHE_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_SIZE.Reg) & 0x3fff +} + +// EXTMEM.L1_ICACHE0_AUTOLOAD_CTRL: L1 instruction Cache 0 autoload-operation control register +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10 +} + +// EXTMEM.L1_ICACHE0_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 0 autoload section 0 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE0_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 0 autoload section 0 size configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_ICACHE0_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 0 autoload section 1 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE0_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 0 autoload section 1 size configure register +func (o *EXTMEM_Type) SetL1_ICACHE0_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_ICACHE1_AUTOLOAD_CTRL: L1 instruction Cache 1 autoload-operation control register +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10 +} + +// EXTMEM.L1_ICACHE1_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 1 autoload section 0 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE1_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 1 autoload section 0 size configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_ICACHE1_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 1 autoload section 1 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE1_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 1 autoload section 1 size configure register +func (o *EXTMEM_Type) SetL1_ICACHE1_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_ICACHE2_AUTOLOAD_CTRL: L1 instruction Cache 2 autoload-operation control register +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10 +} + +// EXTMEM.L1_ICACHE2_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 2 autoload section 0 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE2_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 2 autoload section 0 size configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_ICACHE2_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 2 autoload section 1 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE2_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 2 autoload section 1 size configure register +func (o *EXTMEM_Type) SetL1_ICACHE2_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_ICACHE3_AUTOLOAD_CTRL: L1 instruction Cache 3 autoload-operation control register +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10 +} + +// EXTMEM.L1_ICACHE3_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 3 autoload section 0 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE3_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 3 autoload section 0 size configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_ICACHE3_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 3 autoload section 1 address configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE3_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 3 autoload section 1 size configure register +func (o *EXTMEM_Type) SetL1_ICACHE3_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_CACHE_AUTOLOAD_CTRL: L1 Cache autoload-operation control register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT2_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT2_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT3_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT3_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg)&^(0xf000)|value<<12) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_CTRL.Reg) & 0xf000) >> 12 +} + +// EXTMEM.L1_CACHE_AUTOLOAD_SCT0_ADDR: L1 Cache autoload section 0 address configure register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT0_ADDR.Reg) +} + +// EXTMEM.L1_CACHE_AUTOLOAD_SCT0_SIZE: L1 Cache autoload section 0 size configure register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_CACHE_AUTOLOAD_SCT1_ADDR: L1 Cache autoload section 1 address configure register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT1_ADDR.Reg) +} + +// EXTMEM.L1_CACHE_AUTOLOAD_SCT1_SIZE: L1 Cache autoload section 1 size configure register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_CACHE_AUTOLOAD_SCT2_ADDR: L1 Cache autoload section 2 address configure register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_SCT2_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_SCT2_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_SCT2_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT2_ADDR.Reg) +} + +// EXTMEM.L1_CACHE_AUTOLOAD_SCT2_SIZE: L1 Cache autoload section 2 size configure register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_SCT2_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_SCT2_SIZE.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT2_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_SCT2_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT2_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_CACHE_AUTOLOAD_SCT3_ADDR: L1 Cache autoload section 1 address configure register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_SCT3_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_SCT3_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_SCT3_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT3_ADDR.Reg) +} + +// EXTMEM.L1_CACHE_AUTOLOAD_SCT3_SIZE: L1 Cache autoload section 1 size configure register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_SCT3_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_SCT3_SIZE.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT3_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_SCT3_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_SCT3_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L1_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_BUS0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_BUS0_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_BUS1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_BUS1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x80) >> 7 +} + +// EXTMEM.L1_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_BUS0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_BUS0_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_BUS1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_BUS1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x80) >> 7 +} + +// EXTMEM.L1_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_BUS0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_BUS0_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_BUS1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_BUS1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x80) >> 7 +} + +// EXTMEM.L1_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_BUS0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_BUS0_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_BUS1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_BUS1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x80) >> 7 +} + +// EXTMEM.L1_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_CACHE_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_CACHE_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_CACHE_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_CACHE_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_CACHE_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_CACHE_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_CACHE_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_CACHE_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x10000) >> 16 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x20000) >> 17 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x40000) >> 18 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x80000) >> 19 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x200000) >> 21 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x400000) >> 22 +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x800000) >> 23 +} + +// EXTMEM.L1_IBUS0_ACS_HIT_CNT: L1-ICache bus0 Hit-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS0_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS0_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS0_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS0_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L1_IBUS0_ACS_MISS_CNT: L1-ICache bus0 Miss-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS0_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS0_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L1_IBUS0_ACS_CONFLICT_CNT: L1-ICache bus0 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS0_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS0_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS0_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS0_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L1_IBUS0_ACS_NXTLVL_CNT: L1-ICache bus0 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS0_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS0_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS0_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS0_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L1_IBUS1_ACS_HIT_CNT: L1-ICache bus1 Hit-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS1_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS1_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS1_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS1_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L1_IBUS1_ACS_MISS_CNT: L1-ICache bus1 Miss-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS1_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS1_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L1_IBUS1_ACS_CONFLICT_CNT: L1-ICache bus1 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS1_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS1_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS1_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS1_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L1_IBUS1_ACS_NXTLVL_CNT: L1-ICache bus1 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS1_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS1_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS1_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS1_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L1_IBUS2_ACS_HIT_CNT: L1-ICache bus2 Hit-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS2_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS2_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS2_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS2_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L1_IBUS2_ACS_MISS_CNT: L1-ICache bus2 Miss-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS2_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L1_IBUS2_ACS_CONFLICT_CNT: L1-ICache bus2 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS2_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS2_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS2_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS2_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L1_IBUS2_ACS_NXTLVL_CNT: L1-ICache bus2 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS2_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS2_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS2_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS2_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L1_IBUS3_ACS_HIT_CNT: L1-ICache bus3 Hit-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS3_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS3_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS3_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS3_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L1_IBUS3_ACS_MISS_CNT: L1-ICache bus3 Miss-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS3_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS3_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS3_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS3_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L1_IBUS3_ACS_CONFLICT_CNT: L1-ICache bus3 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS3_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS3_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS3_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS3_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L1_IBUS3_ACS_NXTLVL_CNT: L1-ICache bus3 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL1_IBUS3_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS3_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_IBUS3_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS3_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L1_BUS0_ACS_HIT_CNT: L1-Cache bus0 Hit-Access Counter register +func (o *EXTMEM_Type) SetL1_BUS0_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_BUS0_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_BUS0_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_BUS0_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L1_BUS0_ACS_MISS_CNT: L1-Cache bus0 Miss-Access Counter register +func (o *EXTMEM_Type) SetL1_BUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_BUS0_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_BUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_BUS0_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L1_BUS0_ACS_CONFLICT_CNT: L1-Cache bus0 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL1_BUS0_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_BUS0_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_BUS0_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_BUS0_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L1_BUS0_ACS_NXTLVL_CNT: L1-Cache bus0 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL1_BUS0_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L1_BUS0_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_BUS0_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L1_BUS0_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L1_BUS1_ACS_HIT_CNT: L1-Cache bus1 Hit-Access Counter register +func (o *EXTMEM_Type) SetL1_BUS1_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_BUS1_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_BUS1_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_BUS1_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L1_BUS1_ACS_MISS_CNT: L1-Cache bus1 Miss-Access Counter register +func (o *EXTMEM_Type) SetL1_BUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_BUS1_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_BUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_BUS1_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L1_BUS1_ACS_CONFLICT_CNT: L1-Cache bus1 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL1_BUS1_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_BUS1_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_BUS1_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_BUS1_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L1_BUS1_ACS_NXTLVL_CNT: L1-Cache bus1 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL1_BUS1_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L1_BUS1_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_BUS1_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L1_BUS1_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L1_DBUS2_ACS_HIT_CNT: L1-DCache bus2 Hit-Access Counter register +func (o *EXTMEM_Type) SetL1_DBUS2_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS2_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DBUS2_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS2_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L1_DBUS2_ACS_MISS_CNT: L1-DCache bus2 Miss-Access Counter register +func (o *EXTMEM_Type) SetL1_DBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS2_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L1_DBUS2_ACS_CONFLICT_CNT: L1-DCache bus2 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL1_DBUS2_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS2_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DBUS2_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS2_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L1_DBUS2_ACS_NXTLVL_CNT: L1-DCache bus2 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL1_DBUS2_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS2_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DBUS2_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS2_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L1_DBUS3_ACS_HIT_CNT: L1-DCache bus3 Hit-Access Counter register +func (o *EXTMEM_Type) SetL1_DBUS3_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS3_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DBUS3_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS3_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L1_DBUS3_ACS_MISS_CNT: L1-DCache bus3 Miss-Access Counter register +func (o *EXTMEM_Type) SetL1_DBUS3_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS3_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DBUS3_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS3_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L1_DBUS3_ACS_CONFLICT_CNT: L1-DCache bus3 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL1_DBUS3_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS3_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DBUS3_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS3_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L1_DBUS3_ACS_NXTLVL_CNT: L1-DCache bus3 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL1_DBUS3_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS3_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DBUS3_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS3_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L1_ICACHE0_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register +func (o *EXTMEM_Type) SetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.L1_ICACHE0_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register +func (o *EXTMEM_Type) SetL1_ICACHE0_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_ACS_FAIL_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE0_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE1_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register +func (o *EXTMEM_Type) SetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.L1_ICACHE1_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register +func (o *EXTMEM_Type) SetL1_ICACHE1_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_ACS_FAIL_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE1_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE2_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register +func (o *EXTMEM_Type) SetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.L1_ICACHE2_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register +func (o *EXTMEM_Type) SetL1_ICACHE2_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_ACS_FAIL_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE2_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ADDR.Reg) +} + +// EXTMEM.L1_ICACHE3_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register +func (o *EXTMEM_Type) SetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.L1_ICACHE3_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register +func (o *EXTMEM_Type) SetL1_ICACHE3_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_ACS_FAIL_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_ICACHE3_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ADDR.Reg) +} + +// EXTMEM.L1_CACHE_ACS_FAIL_ID_ATTR: L1-Cache Access Fail ID/attribution information register +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_ID_ATTR_L1_CACHE_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_ID_ATTR_L1_CACHE_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetL1_CACHE_ACS_FAIL_ID_ATTR_L1_CACHE_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL1_CACHE_ACS_FAIL_ID_ATTR_L1_CACHE_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.L1_DCACHE_ACS_FAIL_ADDR: L1-Cache Access Fail Address information register +func (o *EXTMEM_Type) SetL1_DCACHE_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_ACS_FAIL_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_DCACHE_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ADDR.Reg) +} + +// EXTMEM.L1_CACHE_SYNC_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x2000) >> 13 +} + +// EXTMEM.L1_CACHE_SYNC_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x2000) >> 13 +} + +// EXTMEM.L1_CACHE_SYNC_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x2000) >> 13 +} + +// EXTMEM.L1_CACHE_SYNC_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x2000) >> 13 +} + +// EXTMEM.L1_CACHE_SYNC_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg)&^(0x3)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg) & 0x3 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg)&^(0xc)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg) & 0xc) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg)&^(0x30)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg) & 0x30) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg)&^(0xc0)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg) & 0xc0) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_CACHE_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg)&^(0x300)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_CACHE_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg) & 0x300) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_PRELOAD_EXCEPTION_CACHE_SYNC_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg)&^(0x3000)|value<<12) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_PRELOAD_EXCEPTION_CACHE_SYNC_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_PRELOAD_EXCEPTION.Reg) & 0x3000) >> 12 +} + +// EXTMEM.L1_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_CACHE_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_CACHE_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register +func (o *EXTMEM_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_CACHE_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_CACHE_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_CACHE_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_CACHE_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers +func (o *EXTMEM_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR() uint32 { + return volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_CACHE_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_CACHE_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x10) >> 4 +} + +// EXTMEM.L1_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_CACHE_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_CACHE_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL1_CACHE_OBJECT_CTRL_L1_CACHE_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL1_CACHE_OBJECT_CTRL_L1_CACHE_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x400) >> 10 +} + +// EXTMEM.L1_CACHE_WAY_OBJECT: Cache Tag and Data memory way register +func (o *EXTMEM_Type) SetL1_CACHE_WAY_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WAY_OBJECT.Reg, volatile.LoadUint32(&o.L1_CACHE_WAY_OBJECT.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetL1_CACHE_WAY_OBJECT() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_WAY_OBJECT.Reg) & 0x7 +} + +// EXTMEM.L1_CACHE_VADDR: Cache Vaddr register +func (o *EXTMEM_Type) SetL1_CACHE_VADDR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL1_CACHE_VADDR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_VADDR.Reg) +} + +// EXTMEM.L1_CACHE_DEBUG_BUS: Cache Tag/data memory content register +func (o *EXTMEM_Type) SetL1_CACHE_DEBUG_BUS(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DEBUG_BUS.Reg, value) +} +func (o *EXTMEM_Type) GetL1_CACHE_DEBUG_BUS() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_DEBUG_BUS.Reg) +} + +// EXTMEM.LEVEL_SPLIT0: USED TO SPLIT L1 CACHE AND L2 CACHE +func (o *EXTMEM_Type) SetLEVEL_SPLIT0(value uint32) { + volatile.StoreUint32(&o.LEVEL_SPLIT0.Reg, value) +} +func (o *EXTMEM_Type) GetLEVEL_SPLIT0() uint32 { + return volatile.LoadUint32(&o.LEVEL_SPLIT0.Reg) +} + +// EXTMEM.L2_CACHE_CTRL: L2 Cache(L2-Cache) control register +func (o *EXTMEM_Type) SetL2_CACHE_CTRL_L2_CACHE_SHUT_DMA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL2_CACHE_CTRL_L2_CACHE_SHUT_DMA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL2_CACHE_CTRL_L2_CACHE_UNDEF_OP(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg)&^(0x1e0)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_CTRL_L2_CACHE_UNDEF_OP() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg) & 0x1e0) >> 5 +} + +// EXTMEM.L2_BYPASS_CACHE_CONF: Bypass Cache configure register +func (o *EXTMEM_Type) SetL2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN(value uint32) { + volatile.StoreUint32(&o.L2_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L2_BYPASS_CACHE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN() uint32 { + return (volatile.LoadUint32(&o.L2_BYPASS_CACHE_CONF.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_CACHESIZE_CONF: L2 Cache CacheSize mode configure register +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2048K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2048K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4096K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4096K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x1000) >> 12 +} + +// EXTMEM.L2_CACHE_BLOCKSIZE_CONF: L2 Cache BlockSize mode configure register +func (o *EXTMEM_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register +func (o *EXTMEM_Type) SetL2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_WRAP_AROUND_CTRL.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register +func (o *EXTMEM_Type) SetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x200000) >> 21 +} +func (o *EXTMEM_Type) SetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *EXTMEM_Type) GetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x400000) >> 22 +} + +// EXTMEM.L2_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register +func (o *EXTMEM_Type) SetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x200000) >> 21 +} +func (o *EXTMEM_Type) SetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *EXTMEM_Type) GetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x400000) >> 22 +} + +// EXTMEM.L2_CACHE_FREEZE_CTRL: Cache Freeze control register +func (o *EXTMEM_Type) SetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg) & 0x200000) >> 21 +} +func (o *EXTMEM_Type) SetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *EXTMEM_Type) GetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg) & 0x400000) >> 22 +} + +// EXTMEM.L2_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register +func (o *EXTMEM_Type) SetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x200000) >> 21 +} + +// EXTMEM.L2_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register +func (o *EXTMEM_Type) SetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x200000) >> 21 +} + +// EXTMEM.L2_CACHE_PRELOCK_CONF: L2 Cache prelock configure register +func (o *EXTMEM_Type) SetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// EXTMEM.L2_CACHE_PRELOCK_SCT0_ADDR: L2 Cache prelock section0 address configure register +func (o *EXTMEM_Type) SetL2_CACHE_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT0_ADDR.Reg) +} + +// EXTMEM.L2_CACHE_PRELOCK_SCT1_ADDR: L2 Cache prelock section1 address configure register +func (o *EXTMEM_Type) SetL2_CACHE_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT1_ADDR.Reg) +} + +// EXTMEM.L2_CACHE_PRELOCK_SCT_SIZE: L2 Cache prelock section size configure register +func (o *EXTMEM_Type) SetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.L2_CACHE_PRELOAD_CTRL: L2 Cache preload-operation control register +func (o *EXTMEM_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// EXTMEM.L2_CACHE_PRELOAD_ADDR: L2 Cache preload address configure register +func (o *EXTMEM_Type) SetL2_CACHE_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOAD_ADDR.Reg) +} + +// EXTMEM.L2_CACHE_PRELOAD_SIZE: L2 Cache preload size configure register +func (o *EXTMEM_Type) SetL2_CACHE_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOAD_SIZE.Reg) & 0xffff +} + +// EXTMEM.L2_CACHE_AUTOLOAD_CTRL: L2 Cache autoload-operation control register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0xf000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0xf000) >> 12 +} + +// EXTMEM.L2_CACHE_AUTOLOAD_SCT0_ADDR: L2 Cache autoload section 0 address configure register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT0_ADDR.Reg) +} + +// EXTMEM.L2_CACHE_AUTOLOAD_SCT0_SIZE: L2 Cache autoload section 0 size configure register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L2_CACHE_AUTOLOAD_SCT1_ADDR: L2 Cache autoload section 1 address configure register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT1_ADDR.Reg) +} + +// EXTMEM.L2_CACHE_AUTOLOAD_SCT1_SIZE: L2 Cache autoload section 1 size configure register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L2_CACHE_AUTOLOAD_SCT2_ADDR: L2 Cache autoload section 2 address configure register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_SCT2_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT2_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_SCT2_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT2_ADDR.Reg) +} + +// EXTMEM.L2_CACHE_AUTOLOAD_SCT2_SIZE: L2 Cache autoload section 2 size configure register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_SCT2_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT2_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT2_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_SCT2_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT2_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L2_CACHE_AUTOLOAD_SCT3_ADDR: L2 Cache autoload section 3 address configure register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_SCT3_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT3_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_SCT3_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT3_ADDR.Reg) +} + +// EXTMEM.L2_CACHE_AUTOLOAD_SCT3_SIZE: L2 Cache autoload section 3 size configure register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_SCT3_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT3_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT3_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_SCT3_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT3_SIZE.Reg) & 0xfffffff +} + +// EXTMEM.L2_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x8000) >> 15 +} + +// EXTMEM.L2_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x8000) >> 15 +} + +// EXTMEM.L2_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x8000) >> 15 +} + +// EXTMEM.L2_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x8000) >> 15 +} + +// EXTMEM.L2_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ST.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x8000) >> 15 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x80000000) >> 31 +} + +// EXTMEM.L2_IBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS0_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS0_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS0_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS0_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L2_IBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS0_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS0_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L2_IBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS0_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS0_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS0_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS0_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L2_IBUS0_ACS_NXTLVL_CNT: L2-Cache bus0 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS0_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS0_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS0_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS0_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L2_IBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS1_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS1_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS1_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS1_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L2_IBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS1_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS1_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L2_IBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS1_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS1_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS1_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS1_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L2_IBUS1_ACS_NXTLVL_CNT: L2-Cache bus1 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS1_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS1_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS1_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS1_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L2_IBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS2_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS2_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS2_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS2_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L2_IBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS2_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L2_IBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS2_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS2_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS2_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS2_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L2_IBUS2_ACS_NXTLVL_CNT: L2-Cache bus2 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS2_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS2_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS2_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS2_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L2_IBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS3_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS3_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS3_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS3_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L2_IBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS3_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS3_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS3_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS3_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L2_IBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS3_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS3_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS3_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS3_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L2_IBUS3_ACS_NXTLVL_CNT: L2-Cache bus3 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL2_IBUS3_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS3_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_IBUS3_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS3_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L2_DBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS0_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS0_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS0_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS0_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L2_DBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS0_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS0_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L2_DBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS0_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS0_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS0_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS0_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L2_DBUS0_ACS_NXTLVL_CNT: L2-Cache bus0 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS0_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS0_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS0_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS0_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L2_DBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS1_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS1_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS1_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS1_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L2_DBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS1_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS1_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L2_DBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS1_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS1_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS1_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS1_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L2_DBUS1_ACS_NXTLVL_CNT: L2-Cache bus1 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS1_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS1_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS1_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS1_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L2_DBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS2_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS2_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS2_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS2_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L2_DBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS2_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L2_DBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS2_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS2_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS2_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS2_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L2_DBUS2_ACS_NXTLVL_CNT: L2-Cache bus2 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS2_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS2_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS2_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS2_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L2_DBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS3_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS3_ACS_HIT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS3_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS3_ACS_HIT_CNT.Reg) +} + +// EXTMEM.L2_DBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS3_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS3_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS3_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS3_ACS_MISS_CNT.Reg) +} + +// EXTMEM.L2_DBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS3_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS3_ACS_CONFLICT_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS3_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS3_ACS_CONFLICT_CNT.Reg) +} + +// EXTMEM.L2_DBUS3_ACS_NXTLVL_CNT: L2-Cache bus3 Next-Level-Access Counter register +func (o *EXTMEM_Type) SetL2_DBUS3_ACS_NXTLVL_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS3_ACS_NXTLVL_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetL2_DBUS3_ACS_NXTLVL_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS3_ACS_NXTLVL_CNT.Reg) +} + +// EXTMEM.L2_CACHE_ACS_FAIL_ID_ATTR: L2-Cache Access Fail ID/attribution information register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.L2_CACHE_ACS_FAIL_ADDR: L2-Cache Access Fail Address information register +func (o *EXTMEM_Type) SetL2_CACHE_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ADDR.Reg) +} + +// EXTMEM.L2_CACHE_SYNC_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x1000) >> 12 +} + +// EXTMEM.L2_CACHE_SYNC_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x1000) >> 12 +} + +// EXTMEM.L2_CACHE_SYNC_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x1000) >> 12 +} + +// EXTMEM.L2_CACHE_SYNC_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x1000) >> 12 +} + +// EXTMEM.L2_CACHE_SYNC_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_EXCEPTION.Reg)&^(0xc00)|value<<10) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_EXCEPTION.Reg) & 0xc00) >> 10 +} + +// EXTMEM.L2_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register +func (o *EXTMEM_Type) SetL2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_RST_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_RST_CTRL.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register +func (o *EXTMEM_Type) SetL2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_RST_CTRL.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register +func (o *EXTMEM_Type) SetL2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers +func (o *EXTMEM_Type) SetL2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L2_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L2_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x20) >> 5 +} + +// EXTMEM.L2_CACHE_ACCESS_ATTR_CTRL: L1 Cache access Attribute propagation control register +func (o *EXTMEM_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x8) >> 3 +} + +// EXTMEM.L2_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register +func (o *EXTMEM_Type) SetL2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetL2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetL2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetL2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg) & 0x800) >> 11 +} + +// EXTMEM.L2_CACHE_WAY_OBJECT: Cache Tag and Data memory way register +func (o *EXTMEM_Type) SetL2_CACHE_WAY_OBJECT(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_WAY_OBJECT.Reg, volatile.LoadUint32(&o.L2_CACHE_WAY_OBJECT.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetL2_CACHE_WAY_OBJECT() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_WAY_OBJECT.Reg) & 0x7 +} + +// EXTMEM.L2_CACHE_VADDR: Cache Vaddr register +func (o *EXTMEM_Type) SetL2_CACHE_VADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_VADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_VADDR.Reg) +} + +// EXTMEM.L2_CACHE_DEBUG_BUS: Cache Tag/data memory content register +func (o *EXTMEM_Type) SetL2_CACHE_DEBUG_BUS(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DEBUG_BUS.Reg, value) +} +func (o *EXTMEM_Type) GetL2_CACHE_DEBUG_BUS() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_DEBUG_BUS.Reg) +} + +// EXTMEM.LEVEL_SPLIT1: USED TO SPLIT L1 CACHE AND L2 CACHE +func (o *EXTMEM_Type) SetLEVEL_SPLIT1(value uint32) { + volatile.StoreUint32(&o.LEVEL_SPLIT1.Reg, value) +} +func (o *EXTMEM_Type) GetLEVEL_SPLIT1() uint32 { + return volatile.LoadUint32(&o.LEVEL_SPLIT1.Reg) +} + +// EXTMEM.CLOCK_GATE: Clock gate control register +func (o *EXTMEM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// EXTMEM.REDUNDANCY_SIG0: Cache redundancy signal 0 register +func (o *EXTMEM_Type) SetREDUNDANCY_SIG0(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG0.Reg, value) +} +func (o *EXTMEM_Type) GetREDUNDANCY_SIG0() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG0.Reg) +} + +// EXTMEM.REDUNDANCY_SIG1: Cache redundancy signal 1 register +func (o *EXTMEM_Type) SetREDUNDANCY_SIG1(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG1.Reg, value) +} +func (o *EXTMEM_Type) GetREDUNDANCY_SIG1() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG1.Reg) +} + +// EXTMEM.REDUNDANCY_SIG2: Cache redundancy signal 2 register +func (o *EXTMEM_Type) SetREDUNDANCY_SIG2(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG2.Reg, value) +} +func (o *EXTMEM_Type) GetREDUNDANCY_SIG2() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG2.Reg) +} + +// EXTMEM.REDUNDANCY_SIG3: Cache redundancy signal 3 register +func (o *EXTMEM_Type) SetREDUNDANCY_SIG3(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG3.Reg, value) +} +func (o *EXTMEM_Type) GetREDUNDANCY_SIG3() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG3.Reg) +} + +// EXTMEM.REDUNDANCY_SIG4: Cache redundancy signal 0 register +func (o *EXTMEM_Type) SetREDUNDANCY_SIG4_CACHE_REDCY_SIG4(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG4.Reg, volatile.LoadUint32(&o.REDUNDANCY_SIG4.Reg)&^(0xf)|value) +} +func (o *EXTMEM_Type) GetREDUNDANCY_SIG4_CACHE_REDCY_SIG4() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG4.Reg) & 0xf +} + +// EXTMEM.DATE: Version control register +func (o *EXTMEM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// General Purpose Input/Output +type GPIO_Type struct { + BT_SELECT volatile.Register32 // 0x0 + OUT volatile.Register32 // 0x4 + OUT_W1TS volatile.Register32 // 0x8 + OUT_W1TC volatile.Register32 // 0xC + OUT1 volatile.Register32 // 0x10 + OUT1_W1TS volatile.Register32 // 0x14 + OUT1_W1TC volatile.Register32 // 0x18 + SDIO_SELECT volatile.Register32 // 0x1C + ENABLE volatile.Register32 // 0x20 + ENABLE_W1TS volatile.Register32 // 0x24 + ENABLE_W1TC volatile.Register32 // 0x28 + ENABLE1 volatile.Register32 // 0x2C + ENABLE1_W1TS volatile.Register32 // 0x30 + ENABLE1_W1TC volatile.Register32 // 0x34 + STRAP volatile.Register32 // 0x38 + IN volatile.Register32 // 0x3C + IN1 volatile.Register32 // 0x40 + STATUS volatile.Register32 // 0x44 + STATUS_W1TS volatile.Register32 // 0x48 + STATUS_W1TC volatile.Register32 // 0x4C + STATUS1 volatile.Register32 // 0x50 + STATUS1_W1TS volatile.Register32 // 0x54 + STATUS1_W1TC volatile.Register32 // 0x58 + PCPU_INT volatile.Register32 // 0x5C + PCPU_NMI_INT volatile.Register32 // 0x60 + CPUSDIO_INT volatile.Register32 // 0x64 + PCPU_INT1 volatile.Register32 // 0x68 + PCPU_NMI_INT1 volatile.Register32 // 0x6C + CPUSDIO_INT1 volatile.Register32 // 0x70 + PIN0 volatile.Register32 // 0x74 + PIN1 volatile.Register32 // 0x78 + PIN2 volatile.Register32 // 0x7C + PIN3 volatile.Register32 // 0x80 + PIN4 volatile.Register32 // 0x84 + PIN5 volatile.Register32 // 0x88 + PIN6 volatile.Register32 // 0x8C + PIN7 volatile.Register32 // 0x90 + PIN8 volatile.Register32 // 0x94 + PIN9 volatile.Register32 // 0x98 + PIN10 volatile.Register32 // 0x9C + PIN11 volatile.Register32 // 0xA0 + PIN12 volatile.Register32 // 0xA4 + PIN13 volatile.Register32 // 0xA8 + PIN14 volatile.Register32 // 0xAC + PIN15 volatile.Register32 // 0xB0 + PIN16 volatile.Register32 // 0xB4 + PIN17 volatile.Register32 // 0xB8 + PIN18 volatile.Register32 // 0xBC + PIN19 volatile.Register32 // 0xC0 + PIN20 volatile.Register32 // 0xC4 + PIN21 volatile.Register32 // 0xC8 + PIN22 volatile.Register32 // 0xCC + PIN23 volatile.Register32 // 0xD0 + PIN24 volatile.Register32 // 0xD4 + PIN25 volatile.Register32 // 0xD8 + PIN26 volatile.Register32 // 0xDC + PIN27 volatile.Register32 // 0xE0 + PIN28 volatile.Register32 // 0xE4 + PIN29 volatile.Register32 // 0xE8 + PIN30 volatile.Register32 // 0xEC + PIN31 volatile.Register32 // 0xF0 + PIN32 volatile.Register32 // 0xF4 + PIN33 volatile.Register32 // 0xF8 + PIN34 volatile.Register32 // 0xFC + _ [76]byte + STATUS_NEXT volatile.Register32 // 0x14C + STATUS_NEXT1 volatile.Register32 // 0x150 + FUNC0_IN_SEL_CFG volatile.Register32 // 0x154 + FUNC1_IN_SEL_CFG volatile.Register32 // 0x158 + FUNC2_IN_SEL_CFG volatile.Register32 // 0x15C + FUNC3_IN_SEL_CFG volatile.Register32 // 0x160 + FUNC4_IN_SEL_CFG volatile.Register32 // 0x164 + FUNC5_IN_SEL_CFG volatile.Register32 // 0x168 + FUNC6_IN_SEL_CFG volatile.Register32 // 0x16C + FUNC7_IN_SEL_CFG volatile.Register32 // 0x170 + FUNC8_IN_SEL_CFG volatile.Register32 // 0x174 + FUNC9_IN_SEL_CFG volatile.Register32 // 0x178 + FUNC10_IN_SEL_CFG volatile.Register32 // 0x17C + FUNC11_IN_SEL_CFG volatile.Register32 // 0x180 + FUNC12_IN_SEL_CFG volatile.Register32 // 0x184 + FUNC13_IN_SEL_CFG volatile.Register32 // 0x188 + FUNC14_IN_SEL_CFG volatile.Register32 // 0x18C + FUNC15_IN_SEL_CFG volatile.Register32 // 0x190 + FUNC16_IN_SEL_CFG volatile.Register32 // 0x194 + FUNC17_IN_SEL_CFG volatile.Register32 // 0x198 + FUNC18_IN_SEL_CFG volatile.Register32 // 0x19C + FUNC19_IN_SEL_CFG volatile.Register32 // 0x1A0 + FUNC20_IN_SEL_CFG volatile.Register32 // 0x1A4 + FUNC21_IN_SEL_CFG volatile.Register32 // 0x1A8 + FUNC22_IN_SEL_CFG volatile.Register32 // 0x1AC + FUNC23_IN_SEL_CFG volatile.Register32 // 0x1B0 + FUNC24_IN_SEL_CFG volatile.Register32 // 0x1B4 + FUNC25_IN_SEL_CFG volatile.Register32 // 0x1B8 + FUNC26_IN_SEL_CFG volatile.Register32 // 0x1BC + FUNC27_IN_SEL_CFG volatile.Register32 // 0x1C0 + FUNC28_IN_SEL_CFG volatile.Register32 // 0x1C4 + FUNC29_IN_SEL_CFG volatile.Register32 // 0x1C8 + FUNC30_IN_SEL_CFG volatile.Register32 // 0x1CC + FUNC31_IN_SEL_CFG volatile.Register32 // 0x1D0 + FUNC32_IN_SEL_CFG volatile.Register32 // 0x1D4 + FUNC33_IN_SEL_CFG volatile.Register32 // 0x1D8 + FUNC34_IN_SEL_CFG volatile.Register32 // 0x1DC + FUNC35_IN_SEL_CFG volatile.Register32 // 0x1E0 + FUNC36_IN_SEL_CFG volatile.Register32 // 0x1E4 + FUNC37_IN_SEL_CFG volatile.Register32 // 0x1E8 + FUNC38_IN_SEL_CFG volatile.Register32 // 0x1EC + FUNC39_IN_SEL_CFG volatile.Register32 // 0x1F0 + FUNC40_IN_SEL_CFG volatile.Register32 // 0x1F4 + FUNC41_IN_SEL_CFG volatile.Register32 // 0x1F8 + FUNC42_IN_SEL_CFG volatile.Register32 // 0x1FC + FUNC43_IN_SEL_CFG volatile.Register32 // 0x200 + FUNC44_IN_SEL_CFG volatile.Register32 // 0x204 + FUNC45_IN_SEL_CFG volatile.Register32 // 0x208 + FUNC46_IN_SEL_CFG volatile.Register32 // 0x20C + FUNC47_IN_SEL_CFG volatile.Register32 // 0x210 + FUNC48_IN_SEL_CFG volatile.Register32 // 0x214 + FUNC49_IN_SEL_CFG volatile.Register32 // 0x218 + FUNC50_IN_SEL_CFG volatile.Register32 // 0x21C + FUNC51_IN_SEL_CFG volatile.Register32 // 0x220 + FUNC52_IN_SEL_CFG volatile.Register32 // 0x224 + FUNC53_IN_SEL_CFG volatile.Register32 // 0x228 + FUNC54_IN_SEL_CFG volatile.Register32 // 0x22C + FUNC55_IN_SEL_CFG volatile.Register32 // 0x230 + FUNC56_IN_SEL_CFG volatile.Register32 // 0x234 + FUNC57_IN_SEL_CFG volatile.Register32 // 0x238 + FUNC58_IN_SEL_CFG volatile.Register32 // 0x23C + FUNC59_IN_SEL_CFG volatile.Register32 // 0x240 + FUNC60_IN_SEL_CFG volatile.Register32 // 0x244 + FUNC61_IN_SEL_CFG volatile.Register32 // 0x248 + FUNC62_IN_SEL_CFG volatile.Register32 // 0x24C + FUNC63_IN_SEL_CFG volatile.Register32 // 0x250 + FUNC64_IN_SEL_CFG volatile.Register32 // 0x254 + FUNC65_IN_SEL_CFG volatile.Register32 // 0x258 + FUNC66_IN_SEL_CFG volatile.Register32 // 0x25C + FUNC67_IN_SEL_CFG volatile.Register32 // 0x260 + FUNC68_IN_SEL_CFG volatile.Register32 // 0x264 + FUNC69_IN_SEL_CFG volatile.Register32 // 0x268 + FUNC70_IN_SEL_CFG volatile.Register32 // 0x26C + FUNC71_IN_SEL_CFG volatile.Register32 // 0x270 + FUNC72_IN_SEL_CFG volatile.Register32 // 0x274 + FUNC73_IN_SEL_CFG volatile.Register32 // 0x278 + FUNC74_IN_SEL_CFG volatile.Register32 // 0x27C + FUNC75_IN_SEL_CFG volatile.Register32 // 0x280 + FUNC76_IN_SEL_CFG volatile.Register32 // 0x284 + FUNC77_IN_SEL_CFG volatile.Register32 // 0x288 + FUNC78_IN_SEL_CFG volatile.Register32 // 0x28C + FUNC79_IN_SEL_CFG volatile.Register32 // 0x290 + FUNC80_IN_SEL_CFG volatile.Register32 // 0x294 + FUNC81_IN_SEL_CFG volatile.Register32 // 0x298 + FUNC82_IN_SEL_CFG volatile.Register32 // 0x29C + FUNC83_IN_SEL_CFG volatile.Register32 // 0x2A0 + FUNC84_IN_SEL_CFG volatile.Register32 // 0x2A4 + FUNC85_IN_SEL_CFG volatile.Register32 // 0x2A8 + FUNC86_IN_SEL_CFG volatile.Register32 // 0x2AC + FUNC87_IN_SEL_CFG volatile.Register32 // 0x2B0 + FUNC88_IN_SEL_CFG volatile.Register32 // 0x2B4 + FUNC89_IN_SEL_CFG volatile.Register32 // 0x2B8 + FUNC90_IN_SEL_CFG volatile.Register32 // 0x2BC + FUNC91_IN_SEL_CFG volatile.Register32 // 0x2C0 + FUNC92_IN_SEL_CFG volatile.Register32 // 0x2C4 + FUNC93_IN_SEL_CFG volatile.Register32 // 0x2C8 + FUNC94_IN_SEL_CFG volatile.Register32 // 0x2CC + FUNC95_IN_SEL_CFG volatile.Register32 // 0x2D0 + FUNC96_IN_SEL_CFG volatile.Register32 // 0x2D4 + FUNC97_IN_SEL_CFG volatile.Register32 // 0x2D8 + FUNC98_IN_SEL_CFG volatile.Register32 // 0x2DC + FUNC99_IN_SEL_CFG volatile.Register32 // 0x2E0 + FUNC100_IN_SEL_CFG volatile.Register32 // 0x2E4 + FUNC101_IN_SEL_CFG volatile.Register32 // 0x2E8 + FUNC102_IN_SEL_CFG volatile.Register32 // 0x2EC + FUNC103_IN_SEL_CFG volatile.Register32 // 0x2F0 + FUNC104_IN_SEL_CFG volatile.Register32 // 0x2F4 + FUNC105_IN_SEL_CFG volatile.Register32 // 0x2F8 + FUNC106_IN_SEL_CFG volatile.Register32 // 0x2FC + FUNC107_IN_SEL_CFG volatile.Register32 // 0x300 + FUNC108_IN_SEL_CFG volatile.Register32 // 0x304 + FUNC109_IN_SEL_CFG volatile.Register32 // 0x308 + FUNC110_IN_SEL_CFG volatile.Register32 // 0x30C + FUNC111_IN_SEL_CFG volatile.Register32 // 0x310 + FUNC112_IN_SEL_CFG volatile.Register32 // 0x314 + FUNC113_IN_SEL_CFG volatile.Register32 // 0x318 + FUNC114_IN_SEL_CFG volatile.Register32 // 0x31C + FUNC115_IN_SEL_CFG volatile.Register32 // 0x320 + FUNC116_IN_SEL_CFG volatile.Register32 // 0x324 + FUNC117_IN_SEL_CFG volatile.Register32 // 0x328 + FUNC118_IN_SEL_CFG volatile.Register32 // 0x32C + FUNC119_IN_SEL_CFG volatile.Register32 // 0x330 + FUNC120_IN_SEL_CFG volatile.Register32 // 0x334 + FUNC121_IN_SEL_CFG volatile.Register32 // 0x338 + FUNC122_IN_SEL_CFG volatile.Register32 // 0x33C + FUNC123_IN_SEL_CFG volatile.Register32 // 0x340 + FUNC124_IN_SEL_CFG volatile.Register32 // 0x344 + FUNC125_IN_SEL_CFG volatile.Register32 // 0x348 + FUNC126_IN_SEL_CFG volatile.Register32 // 0x34C + FUNC127_IN_SEL_CFG volatile.Register32 // 0x350 + _ [512]byte + FUNC0_OUT_SEL_CFG volatile.Register32 // 0x554 + FUNC1_OUT_SEL_CFG volatile.Register32 // 0x558 + FUNC2_OUT_SEL_CFG volatile.Register32 // 0x55C + FUNC3_OUT_SEL_CFG volatile.Register32 // 0x560 + FUNC4_OUT_SEL_CFG volatile.Register32 // 0x564 + FUNC5_OUT_SEL_CFG volatile.Register32 // 0x568 + FUNC6_OUT_SEL_CFG volatile.Register32 // 0x56C + FUNC7_OUT_SEL_CFG volatile.Register32 // 0x570 + FUNC8_OUT_SEL_CFG volatile.Register32 // 0x574 + FUNC9_OUT_SEL_CFG volatile.Register32 // 0x578 + FUNC10_OUT_SEL_CFG volatile.Register32 // 0x57C + FUNC11_OUT_SEL_CFG volatile.Register32 // 0x580 + FUNC12_OUT_SEL_CFG volatile.Register32 // 0x584 + FUNC13_OUT_SEL_CFG volatile.Register32 // 0x588 + FUNC14_OUT_SEL_CFG volatile.Register32 // 0x58C + FUNC15_OUT_SEL_CFG volatile.Register32 // 0x590 + FUNC16_OUT_SEL_CFG volatile.Register32 // 0x594 + FUNC17_OUT_SEL_CFG volatile.Register32 // 0x598 + FUNC18_OUT_SEL_CFG volatile.Register32 // 0x59C + FUNC19_OUT_SEL_CFG volatile.Register32 // 0x5A0 + FUNC20_OUT_SEL_CFG volatile.Register32 // 0x5A4 + FUNC21_OUT_SEL_CFG volatile.Register32 // 0x5A8 + FUNC22_OUT_SEL_CFG volatile.Register32 // 0x5AC + FUNC23_OUT_SEL_CFG volatile.Register32 // 0x5B0 + FUNC24_OUT_SEL_CFG volatile.Register32 // 0x5B4 + FUNC25_OUT_SEL_CFG volatile.Register32 // 0x5B8 + FUNC26_OUT_SEL_CFG volatile.Register32 // 0x5BC + FUNC27_OUT_SEL_CFG volatile.Register32 // 0x5C0 + FUNC28_OUT_SEL_CFG volatile.Register32 // 0x5C4 + FUNC29_OUT_SEL_CFG volatile.Register32 // 0x5C8 + _ [96]byte + CLOCK_GATE volatile.Register32 // 0x62C + _ [204]byte + DATE volatile.Register32 // 0x6FC +} + +// GPIO.BT_SELECT: GPIO bit select register +func (o *GPIO_Type) SetBT_SELECT(value uint32) { + volatile.StoreUint32(&o.BT_SELECT.Reg, value) +} +func (o *GPIO_Type) GetBT_SELECT() uint32 { + return volatile.LoadUint32(&o.BT_SELECT.Reg) +} + +// GPIO.OUT: GPIO output register for GPIO0-31 +func (o *GPIO_Type) SetOUT(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, value) +} +func (o *GPIO_Type) GetOUT() uint32 { + return volatile.LoadUint32(&o.OUT.Reg) +} + +// GPIO.OUT_W1TS: GPIO output set register for GPIO0-31 +func (o *GPIO_Type) SetOUT_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_W1TS.Reg) +} + +// GPIO.OUT_W1TC: GPIO output clear register for GPIO0-31 +func (o *GPIO_Type) SetOUT_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_W1TC.Reg) +} + +// GPIO.OUT1: GPIO output register for GPIO32-34 +func (o *GPIO_Type) SetOUT1_DATA_ORIG(value uint32) { + volatile.StoreUint32(&o.OUT1.Reg, volatile.LoadUint32(&o.OUT1.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetOUT1_DATA_ORIG() uint32 { + return volatile.LoadUint32(&o.OUT1.Reg) & 0x7 +} + +// GPIO.OUT1_W1TS: GPIO output set register for GPIO32-34 +func (o *GPIO_Type) SetOUT1_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TS.Reg, volatile.LoadUint32(&o.OUT1_W1TS.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetOUT1_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TS.Reg) & 0x7 +} + +// GPIO.OUT1_W1TC: GPIO output clear register for GPIO32-34 +func (o *GPIO_Type) SetOUT1_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TC.Reg, volatile.LoadUint32(&o.OUT1_W1TC.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetOUT1_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TC.Reg) & 0x7 +} + +// GPIO.SDIO_SELECT: GPIO sdio select register +func (o *GPIO_Type) SetSDIO_SELECT_SDIO_SEL(value uint32) { + volatile.StoreUint32(&o.SDIO_SELECT.Reg, volatile.LoadUint32(&o.SDIO_SELECT.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSDIO_SELECT_SDIO_SEL() uint32 { + return volatile.LoadUint32(&o.SDIO_SELECT.Reg) & 0xff +} + +// GPIO.ENABLE: GPIO output enable register for GPIO0-31 +func (o *GPIO_Type) SetENABLE(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, value) +} +func (o *GPIO_Type) GetENABLE() uint32 { + return volatile.LoadUint32(&o.ENABLE.Reg) +} + +// GPIO.ENABLE_W1TS: GPIO output enable set register for GPIO0-31 +func (o *GPIO_Type) SetENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) +} + +// GPIO.ENABLE_W1TC: GPIO output enable clear register for GPIO0-31 +func (o *GPIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) +} + +// GPIO.ENABLE1: GPIO output enable register for GPIO32-34 +func (o *GPIO_Type) SetENABLE1_DATA(value uint32) { + volatile.StoreUint32(&o.ENABLE1.Reg, volatile.LoadUint32(&o.ENABLE1.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetENABLE1_DATA() uint32 { + return volatile.LoadUint32(&o.ENABLE1.Reg) & 0x7 +} + +// GPIO.ENABLE1_W1TS: GPIO output enable set register for GPIO32-34 +func (o *GPIO_Type) SetENABLE1_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TS.Reg, volatile.LoadUint32(&o.ENABLE1_W1TS.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TS.Reg) & 0x7 +} + +// GPIO.ENABLE1_W1TC: GPIO output enable clear register for GPIO32-34 +func (o *GPIO_Type) SetENABLE1_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TC.Reg, volatile.LoadUint32(&o.ENABLE1_W1TC.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TC.Reg) & 0x7 +} + +// GPIO.STRAP: pad strapping register +func (o *GPIO_Type) SetSTRAP_STRAPPING(value uint32) { + volatile.StoreUint32(&o.STRAP.Reg, volatile.LoadUint32(&o.STRAP.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetSTRAP_STRAPPING() uint32 { + return volatile.LoadUint32(&o.STRAP.Reg) & 0xffff +} + +// GPIO.IN: GPIO input register for GPIO0-31 +func (o *GPIO_Type) SetIN(value uint32) { + volatile.StoreUint32(&o.IN.Reg, value) +} +func (o *GPIO_Type) GetIN() uint32 { + return volatile.LoadUint32(&o.IN.Reg) +} + +// GPIO.IN1: GPIO input register for GPIO32-34 +func (o *GPIO_Type) SetIN1_DATA_NEXT(value uint32) { + volatile.StoreUint32(&o.IN1.Reg, volatile.LoadUint32(&o.IN1.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetIN1_DATA_NEXT() uint32 { + return volatile.LoadUint32(&o.IN1.Reg) & 0x7 +} + +// GPIO.STATUS: GPIO interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) +} + +// GPIO.STATUS_W1TS: GPIO interrupt status set register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) +} + +// GPIO.STATUS_W1TC: GPIO interrupt status clear register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) +} + +// GPIO.STATUS1: GPIO interrupt status register for GPIO32-34 +func (o *GPIO_Type) SetSTATUS1_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.STATUS1.Reg, volatile.LoadUint32(&o.STATUS1.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetSTATUS1_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.STATUS1.Reg) & 0x7 +} + +// GPIO.STATUS1_W1TS: GPIO interrupt status set register for GPIO32-34 +func (o *GPIO_Type) SetSTATUS1_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TS.Reg, volatile.LoadUint32(&o.STATUS1_W1TS.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TS.Reg) & 0x7 +} + +// GPIO.STATUS1_W1TC: GPIO interrupt status clear register for GPIO32-34 +func (o *GPIO_Type) SetSTATUS1_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TC.Reg, volatile.LoadUint32(&o.STATUS1_W1TC.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TC.Reg) & 0x7 +} + +// GPIO.PCPU_INT: GPIO PRO_CPU interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetPCPU_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_INT.Reg) +} + +// GPIO.PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetPCPU_NMI_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT.Reg) +} + +// GPIO.CPUSDIO_INT: GPIO CPUSDIO interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetCPUSDIO_INT(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT.Reg, value) +} +func (o *GPIO_Type) GetCPUSDIO_INT() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT.Reg) +} + +// GPIO.PCPU_INT1: GPIO PRO_CPU interrupt status register for GPIO32-34 +func (o *GPIO_Type) SetPCPU_INT1_PROCPU_INT1(value uint32) { + volatile.StoreUint32(&o.PCPU_INT1.Reg, volatile.LoadUint32(&o.PCPU_INT1.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetPCPU_INT1_PROCPU_INT1() uint32 { + return volatile.LoadUint32(&o.PCPU_INT1.Reg) & 0x7 +} + +// GPIO.PCPU_NMI_INT1: GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 +func (o *GPIO_Type) SetPCPU_NMI_INT1_PROCPU_NMI_INT1(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT1.Reg, volatile.LoadUint32(&o.PCPU_NMI_INT1.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT1_PROCPU_NMI_INT1() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT1.Reg) & 0x7 +} + +// GPIO.CPUSDIO_INT1: GPIO CPUSDIO interrupt status register for GPIO32-34 +func (o *GPIO_Type) SetCPUSDIO_INT1_SDIO_INT1(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT1.Reg, volatile.LoadUint32(&o.CPUSDIO_INT1.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetCPUSDIO_INT1_SDIO_INT1() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT1.Reg) & 0x7 +} + +// GPIO.PIN0: GPIO pin configuration register +func (o *GPIO_Type) SetPIN0_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN0_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN0_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN0_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN0_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN0_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN1: GPIO pin configuration register +func (o *GPIO_Type) SetPIN1_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN1_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN1_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN1_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN1_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN1_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN2: GPIO pin configuration register +func (o *GPIO_Type) SetPIN2_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN2_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN2_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN2_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN2_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN2_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN3: GPIO pin configuration register +func (o *GPIO_Type) SetPIN3_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN3_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN3_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN3_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN3_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN3_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN4: GPIO pin configuration register +func (o *GPIO_Type) SetPIN4_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN4_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN4_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN4_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN4_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN4_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN5: GPIO pin configuration register +func (o *GPIO_Type) SetPIN5_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN5_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN5_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN5_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN5_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN5_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN6: GPIO pin configuration register +func (o *GPIO_Type) SetPIN6_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN6_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN6_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN6_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN6_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN6_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN7: GPIO pin configuration register +func (o *GPIO_Type) SetPIN7_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN7_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN7_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN7_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN7_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN7_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN8: GPIO pin configuration register +func (o *GPIO_Type) SetPIN8_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN8_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN8.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN8_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN8_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN8_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN8_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN9: GPIO pin configuration register +func (o *GPIO_Type) SetPIN9_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN9_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN9.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN9_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN9_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN9_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN9_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN10: GPIO pin configuration register +func (o *GPIO_Type) SetPIN10_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN10_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN10.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN10_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN10_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN10_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN10_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN10_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN10_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN11: GPIO pin configuration register +func (o *GPIO_Type) SetPIN11_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN11_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN11.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN11_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN11_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN11_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN11_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN11_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN11_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN12: GPIO pin configuration register +func (o *GPIO_Type) SetPIN12_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN12_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN12.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN12_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN12_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN12_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN12_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN12_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN12_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN13: GPIO pin configuration register +func (o *GPIO_Type) SetPIN13_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN13_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN13.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN13_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN13_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN13_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN13_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN13_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN13_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN14: GPIO pin configuration register +func (o *GPIO_Type) SetPIN14_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN14_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN14.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN14_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN14_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN14_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN14_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN14_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN14_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN15: GPIO pin configuration register +func (o *GPIO_Type) SetPIN15_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN15_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN15.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN15_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN15_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN15_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN15_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN15_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN15_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN16: GPIO pin configuration register +func (o *GPIO_Type) SetPIN16_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN16_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN16.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN16_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN16_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN16_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN16_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN16_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN16_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN17: GPIO pin configuration register +func (o *GPIO_Type) SetPIN17_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN17_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN17.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN17_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN17_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN17_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN17_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN17_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN17_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN18: GPIO pin configuration register +func (o *GPIO_Type) SetPIN18_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN18_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN18.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN18_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN18_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN18_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN18_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN18_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN18_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN19: GPIO pin configuration register +func (o *GPIO_Type) SetPIN19_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN19_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN19.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN19_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN19_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN19_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN19_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN19_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN19_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN20: GPIO pin configuration register +func (o *GPIO_Type) SetPIN20_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN20_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN20.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN20_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN20_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN20_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN20_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN20_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN20_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN21: GPIO pin configuration register +func (o *GPIO_Type) SetPIN21_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN21_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN21.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN21_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN21_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN21_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN21_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN21_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN21_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN22: GPIO pin configuration register +func (o *GPIO_Type) SetPIN22_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN22_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN22.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN22_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN22_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN22_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN22_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN22_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN22_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN22_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN22_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN22_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN22_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN22_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN22_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN23: GPIO pin configuration register +func (o *GPIO_Type) SetPIN23_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN23_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN23.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN23_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN23_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN23_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN23_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN23_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN23_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN23_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN23_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN23_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN23_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN23_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN23_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN24: GPIO pin configuration register +func (o *GPIO_Type) SetPIN24_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN24_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN24.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN24_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN24_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN24_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN24_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN24_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN24_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN24_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN24_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN24_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN24_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN24_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN24_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN25: GPIO pin configuration register +func (o *GPIO_Type) SetPIN25_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN25_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN25.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN25_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN25_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN25_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN25_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN25_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN25_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN25_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN25_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN25_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN25_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN25_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN25_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN26: GPIO pin configuration register +func (o *GPIO_Type) SetPIN26_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN26_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN26.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN26_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN26_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN26_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN26_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN26_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN26_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN26_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN26_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN26_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN26_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN26_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN26_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN27: GPIO pin configuration register +func (o *GPIO_Type) SetPIN27_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN27_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN27.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN27_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN27_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN27_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN27_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN27_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN27_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN27_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN27_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN27_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN27_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN27_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN27_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN28: GPIO pin configuration register +func (o *GPIO_Type) SetPIN28_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN28_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN28.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN28_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN28_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN28_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN28_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN28_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN28_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN28_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN28_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN28_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN28_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN28_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN28_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN29: GPIO pin configuration register +func (o *GPIO_Type) SetPIN29_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN29_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN29.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN29_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN29_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN29_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN29_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN29_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN29_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN29_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN29_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN29_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN29_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN29_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN29_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN30: GPIO pin configuration register +func (o *GPIO_Type) SetPIN30_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN30_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN30.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN30_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN30_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN30_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN30_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN30_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN30_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN30_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN30_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN30_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN30_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN30_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN30_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN31: GPIO pin configuration register +func (o *GPIO_Type) SetPIN31_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN31_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN31.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN31_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN31_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN31_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN31_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN31_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN31_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN31_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN31_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN31_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN31_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN31_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN31_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN32: GPIO pin configuration register +func (o *GPIO_Type) SetPIN32_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN32_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN32.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN32_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN32_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN32_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN32_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN32_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN32_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN32_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN32_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN32_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN32_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN32_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN32_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN33: GPIO pin configuration register +func (o *GPIO_Type) SetPIN33_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN33_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN33.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN33_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN33_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN33_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN33_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN33_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN33_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN33_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN33_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN33_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN33_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN33_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN33_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN34: GPIO pin configuration register +func (o *GPIO_Type) SetPIN34_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN34_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN34.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN34_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN34_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN34_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN34_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN34_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN34_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN34_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN34_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN34_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN34_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN34_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN34_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x3e000) >> 13 +} + +// GPIO.STATUS_NEXT: GPIO interrupt source register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT.Reg) +} + +// GPIO.STATUS_NEXT1: GPIO interrupt source register for GPIO32-34 +func (o *GPIO_Type) SetSTATUS_NEXT1_STATUS_INTERRUPT_NEXT1(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT1.Reg, volatile.LoadUint32(&o.STATUS_NEXT1.Reg)&^(0x7)|value) +} +func (o *GPIO_Type) GetSTATUS_NEXT1_STATUS_INTERRUPT_NEXT1() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT1.Reg) & 0x7 +} + +// GPIO.FUNC0_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC1_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC2_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC3_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC4_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC5_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC6_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC7_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC8_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC9_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC10_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC11_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC12_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC13_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC14_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC15_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC16_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC17_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC18_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC19_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC20_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC21_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC22_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC23_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC24_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC25_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC26_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC27_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC28_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC29_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC30_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC31_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC32_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC33_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC34_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC35_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC36_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC37_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC38_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC39_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC40_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC41_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC42_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC43_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC44_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC45_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC46_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC47_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC48_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC49_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC50_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC51_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC52_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC53_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC54_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC55_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC56_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC57_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC58_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC59_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC60_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC61_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC62_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC63_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC64_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC65_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC66_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC67_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC68_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC69_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC70_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC71_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC72_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC73_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC74_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC75_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC76_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC77_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC78_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC79_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC80_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC81_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC82_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC83_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC84_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC85_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC86_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC87_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC88_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC89_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC90_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC91_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC92_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC93_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC94_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC95_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC96_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC97_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC98_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC99_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC100_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC101_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC102_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC103_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC104_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC105_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC106_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC107_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC108_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC109_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC110_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC111_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC112_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC113_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC114_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC115_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC116_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC117_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC118_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC119_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC120_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC121_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC122_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC123_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC124_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC125_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC126_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC127_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC0_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC1_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC2_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC3_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC4_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC5_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC6_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC7_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC8_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC9_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC10_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC11_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC12_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC13_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC14_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC15_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC16_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC17_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC18_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC19_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC20_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC21_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC22_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC23_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC24_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC25_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC26_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC27_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC28_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC29_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.CLOCK_GATE: GPIO clock gate register +func (o *GPIO_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIO.DATE: GPIO version register +func (o *GPIO_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *GPIO_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Sigma-Delta Modulation +type GPIOSD_Type struct { + SIGMADELTA0 volatile.Register32 // 0x0 + SIGMADELTA1 volatile.Register32 // 0x4 + SIGMADELTA2 volatile.Register32 // 0x8 + SIGMADELTA3 volatile.Register32 // 0xC + _ [16]byte + CLOCK_GATE volatile.Register32 // 0x20 + SIGMADELTA_MISC volatile.Register32 // 0x24 + _ [8]byte + GLITCH_FILTER_CH0 volatile.Register32 // 0x30 + GLITCH_FILTER_CH1 volatile.Register32 // 0x34 + GLITCH_FILTER_CH2 volatile.Register32 // 0x38 + GLITCH_FILTER_CH3 volatile.Register32 // 0x3C + GLITCH_FILTER_CH4 volatile.Register32 // 0x40 + GLITCH_FILTER_CH5 volatile.Register32 // 0x44 + GLITCH_FILTER_CH6 volatile.Register32 // 0x48 + GLITCH_FILTER_CH7 volatile.Register32 // 0x4C + _ [16]byte + ETM_EVENT_CH0_CFG volatile.Register32 // 0x60 + ETM_EVENT_CH1_CFG volatile.Register32 // 0x64 + ETM_EVENT_CH2_CFG volatile.Register32 // 0x68 + ETM_EVENT_CH3_CFG volatile.Register32 // 0x6C + ETM_EVENT_CH4_CFG volatile.Register32 // 0x70 + ETM_EVENT_CH5_CFG volatile.Register32 // 0x74 + ETM_EVENT_CH6_CFG volatile.Register32 // 0x78 + ETM_EVENT_CH7_CFG volatile.Register32 // 0x7C + _ [32]byte + ETM_TASK_P0_CFG volatile.Register32 // 0xA0 + ETM_TASK_P1_CFG volatile.Register32 // 0xA4 + ETM_TASK_P2_CFG volatile.Register32 // 0xA8 + ETM_TASK_P3_CFG volatile.Register32 // 0xAC + ETM_TASK_P4_CFG volatile.Register32 // 0xB0 + ETM_TASK_P5_CFG volatile.Register32 // 0xB4 + ETM_TASK_P6_CFG volatile.Register32 // 0xB8 + ETM_TASK_P7_CFG volatile.Register32 // 0xBC + _ [60]byte + VERSION volatile.Register32 // 0xFC +} + +// GPIOSD.SIGMADELTA0: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA0_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA0_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA1: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA1_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA1_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA2: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA2_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA2_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA3: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA3_SD0_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD0_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA3_SD0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff00) >> 8 +} + +// GPIOSD.CLOCK_GATE: Clock Gating Configure Register +func (o *GPIOSD_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIOSD.SIGMADELTA_MISC: MISC Register +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_FUNCTION_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_FUNCTION_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x40000000) >> 30 +} +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_SPI_SWAP(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_SPI_SWAP() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x80000000) >> 31 +} + +// GPIOSD.GLITCH_FILTER_CH0: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH1: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH2: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH3: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH4: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH5: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH6: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH7: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.ETM_EVENT_CH0_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH0_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH0_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH1_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH1_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH1_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH2_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH2_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH2_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH3_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH3_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH3_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH4_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH4_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH4_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH5_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH5_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH5_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH6_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH6_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH6_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH7_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH7_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH7_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_TASK_P0_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P1_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P2_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P3_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P4_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P5_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P6_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P7_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe0000) >> 17 +} + +// GPIOSD.VERSION: Version Control Register +func (o *GPIOSD_Type) SetVERSION_GPIO_SD_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *GPIOSD_Type) GetVERSION_GPIO_SD_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// HINF Peripheral +type HINF_Type struct { + CFG_DATA0 volatile.Register32 // 0x0 + CFG_DATA1 volatile.Register32 // 0x4 + CFG_TIMING volatile.Register32 // 0x8 + CFG_UPDATE volatile.Register32 // 0xC + _ [12]byte + CFG_DATA7 volatile.Register32 // 0x1C + CIS_CONF_W0 volatile.Register32 // 0x20 + CIS_CONF_W1 volatile.Register32 // 0x24 + CIS_CONF_W2 volatile.Register32 // 0x28 + CIS_CONF_W3 volatile.Register32 // 0x2C + CIS_CONF_W4 volatile.Register32 // 0x30 + CIS_CONF_W5 volatile.Register32 // 0x34 + CIS_CONF_W6 volatile.Register32 // 0x38 + CIS_CONF_W7 volatile.Register32 // 0x3C + CFG_DATA16 volatile.Register32 // 0x40 + CFG_UHS1_INT_MODE volatile.Register32 // 0x44 + _ [12]byte + CONF_STATUS volatile.Register32 // 0x54 + _ [76]byte + SDIO_SLAVE_ECO_LOW volatile.Register32 // 0xA4 + SDIO_SLAVE_ECO_HIGH volatile.Register32 // 0xA8 + SDIO_SLAVE_ECO_CONF volatile.Register32 // 0xAC + SDIO_SLAVE_LDO_CONF volatile.Register32 // 0xB0 + _ [72]byte + SDIO_DATE volatile.Register32 // 0xFC +} + +// HINF.CFG_DATA0: Configure sdio cis content +func (o *HINF_Type) SetCFG_DATA0_DEVICE_ID_FN1(value uint32) { + volatile.StoreUint32(&o.CFG_DATA0.Reg, volatile.LoadUint32(&o.CFG_DATA0.Reg)&^(0xffff)|value) +} +func (o *HINF_Type) GetCFG_DATA0_DEVICE_ID_FN1() uint32 { + return volatile.LoadUint32(&o.CFG_DATA0.Reg) & 0xffff +} +func (o *HINF_Type) SetCFG_DATA0_USER_ID_FN1(value uint32) { + volatile.StoreUint32(&o.CFG_DATA0.Reg, volatile.LoadUint32(&o.CFG_DATA0.Reg)&^(0xffff0000)|value<<16) +} +func (o *HINF_Type) GetCFG_DATA0_USER_ID_FN1() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA0.Reg) & 0xffff0000) >> 16 +} + +// HINF.CFG_DATA1: SDIO configuration register +func (o *HINF_Type) SetCFG_DATA1_SDIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x1)|value) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_ENABLE() uint32 { + return volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x1 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_IOREADY1(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x2)|value<<1) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_IOREADY1() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x2) >> 1 +} +func (o *HINF_Type) SetCFG_DATA1_HIGHSPEED_ENABLE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x4)|value<<2) +} +func (o *HINF_Type) GetCFG_DATA1_HIGHSPEED_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x4) >> 2 +} +func (o *HINF_Type) SetCFG_DATA1_HIGHSPEED_MODE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x8)|value<<3) +} +func (o *HINF_Type) GetCFG_DATA1_HIGHSPEED_MODE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x8) >> 3 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_CD_ENABLE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x10)|value<<4) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_CD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x10) >> 4 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_IOREADY2(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x20)|value<<5) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_IOREADY2() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x20) >> 5 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_INT_MASK(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x40)|value<<6) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_INT_MASK() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x40) >> 6 +} +func (o *HINF_Type) SetCFG_DATA1_IOENABLE2(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x80)|value<<7) +} +func (o *HINF_Type) GetCFG_DATA1_IOENABLE2() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x80) >> 7 +} +func (o *HINF_Type) SetCFG_DATA1_CD_DISABLE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x100)|value<<8) +} +func (o *HINF_Type) GetCFG_DATA1_CD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x100) >> 8 +} +func (o *HINF_Type) SetCFG_DATA1_FUNC1_EPS(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x200)|value<<9) +} +func (o *HINF_Type) GetCFG_DATA1_FUNC1_EPS() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x200) >> 9 +} +func (o *HINF_Type) SetCFG_DATA1_EMP(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x400)|value<<10) +} +func (o *HINF_Type) GetCFG_DATA1_EMP() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x400) >> 10 +} +func (o *HINF_Type) SetCFG_DATA1_IOENABLE1(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x800)|value<<11) +} +func (o *HINF_Type) GetCFG_DATA1_IOENABLE1() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x800) >> 11 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO_VER(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0xfff000)|value<<12) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO_VER() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0xfff000) >> 12 +} +func (o *HINF_Type) SetCFG_DATA1_FUNC2_EPS(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0x1000000)|value<<24) +} +func (o *HINF_Type) GetCFG_DATA1_FUNC2_EPS() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0x1000000) >> 24 +} +func (o *HINF_Type) SetCFG_DATA1_SDIO20_CONF(value uint32) { + volatile.StoreUint32(&o.CFG_DATA1.Reg, volatile.LoadUint32(&o.CFG_DATA1.Reg)&^(0xfe000000)|value<<25) +} +func (o *HINF_Type) GetCFG_DATA1_SDIO20_CONF() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA1.Reg) & 0xfe000000) >> 25 +} + +// HINF.CFG_TIMING: Timing configuration registers +func (o *HINF_Type) SetCFG_TIMING_NCRC(value uint32) { + volatile.StoreUint32(&o.CFG_TIMING.Reg, volatile.LoadUint32(&o.CFG_TIMING.Reg)&^(0x7)|value) +} +func (o *HINF_Type) GetCFG_TIMING_NCRC() uint32 { + return volatile.LoadUint32(&o.CFG_TIMING.Reg) & 0x7 +} +func (o *HINF_Type) SetCFG_TIMING_PST_END_CMD_LOW_VALUE(value uint32) { + volatile.StoreUint32(&o.CFG_TIMING.Reg, volatile.LoadUint32(&o.CFG_TIMING.Reg)&^(0x3f8)|value<<3) +} +func (o *HINF_Type) GetCFG_TIMING_PST_END_CMD_LOW_VALUE() uint32 { + return (volatile.LoadUint32(&o.CFG_TIMING.Reg) & 0x3f8) >> 3 +} +func (o *HINF_Type) SetCFG_TIMING_PST_END_DATA_LOW_VALUE(value uint32) { + volatile.StoreUint32(&o.CFG_TIMING.Reg, volatile.LoadUint32(&o.CFG_TIMING.Reg)&^(0xfc00)|value<<10) +} +func (o *HINF_Type) GetCFG_TIMING_PST_END_DATA_LOW_VALUE() uint32 { + return (volatile.LoadUint32(&o.CFG_TIMING.Reg) & 0xfc00) >> 10 +} +func (o *HINF_Type) SetCFG_TIMING_SDCLK_STOP_THRES(value uint32) { + volatile.StoreUint32(&o.CFG_TIMING.Reg, volatile.LoadUint32(&o.CFG_TIMING.Reg)&^(0x7ff0000)|value<<16) +} +func (o *HINF_Type) GetCFG_TIMING_SDCLK_STOP_THRES() uint32 { + return (volatile.LoadUint32(&o.CFG_TIMING.Reg) & 0x7ff0000) >> 16 +} +func (o *HINF_Type) SetCFG_TIMING_SAMPLE_CLK_DIVIDER(value uint32) { + volatile.StoreUint32(&o.CFG_TIMING.Reg, volatile.LoadUint32(&o.CFG_TIMING.Reg)&^(0xf0000000)|value<<28) +} +func (o *HINF_Type) GetCFG_TIMING_SAMPLE_CLK_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.CFG_TIMING.Reg) & 0xf0000000) >> 28 +} + +// HINF.CFG_UPDATE: update sdio configurations +func (o *HINF_Type) SetCFG_UPDATE_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CFG_UPDATE.Reg, volatile.LoadUint32(&o.CFG_UPDATE.Reg)&^(0x1)|value) +} +func (o *HINF_Type) GetCFG_UPDATE_CONF_UPDATE() uint32 { + return volatile.LoadUint32(&o.CFG_UPDATE.Reg) & 0x1 +} + +// HINF.CFG_DATA7: SDIO configuration register +func (o *HINF_Type) SetCFG_DATA7_PIN_STATE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0xff)|value) +} +func (o *HINF_Type) GetCFG_DATA7_PIN_STATE() uint32 { + return volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0xff +} +func (o *HINF_Type) SetCFG_DATA7_CHIP_STATE(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0xff00)|value<<8) +} +func (o *HINF_Type) GetCFG_DATA7_CHIP_STATE() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0xff00) >> 8 +} +func (o *HINF_Type) SetCFG_DATA7_SDIO_RST(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x10000)|value<<16) +} +func (o *HINF_Type) GetCFG_DATA7_SDIO_RST() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x10000) >> 16 +} +func (o *HINF_Type) SetCFG_DATA7_SDIO_IOREADY0(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x20000)|value<<17) +} +func (o *HINF_Type) GetCFG_DATA7_SDIO_IOREADY0() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x20000) >> 17 +} +func (o *HINF_Type) SetCFG_DATA7_SDIO_MEM_PD(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x40000)|value<<18) +} +func (o *HINF_Type) GetCFG_DATA7_SDIO_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x40000) >> 18 +} +func (o *HINF_Type) SetCFG_DATA7_ESDIO_DATA1_INT_EN(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x80000)|value<<19) +} +func (o *HINF_Type) GetCFG_DATA7_ESDIO_DATA1_INT_EN() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x80000) >> 19 +} +func (o *HINF_Type) SetCFG_DATA7_SDIO_SWITCH_VOLT_SW(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x100000)|value<<20) +} +func (o *HINF_Type) GetCFG_DATA7_SDIO_SWITCH_VOLT_SW() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x100000) >> 20 +} +func (o *HINF_Type) SetCFG_DATA7_DDR50_BLK_LEN_FIX_EN(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x200000)|value<<21) +} +func (o *HINF_Type) GetCFG_DATA7_DDR50_BLK_LEN_FIX_EN() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x200000) >> 21 +} +func (o *HINF_Type) SetCFG_DATA7_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x400000)|value<<22) +} +func (o *HINF_Type) GetCFG_DATA7_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x400000) >> 22 +} +func (o *HINF_Type) SetCFG_DATA7_SDDR50(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x800000)|value<<23) +} +func (o *HINF_Type) GetCFG_DATA7_SDDR50() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x800000) >> 23 +} +func (o *HINF_Type) SetCFG_DATA7_SSDR104(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x1000000)|value<<24) +} +func (o *HINF_Type) GetCFG_DATA7_SSDR104() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x1000000) >> 24 +} +func (o *HINF_Type) SetCFG_DATA7_SSDR50(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x2000000)|value<<25) +} +func (o *HINF_Type) GetCFG_DATA7_SSDR50() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x2000000) >> 25 +} +func (o *HINF_Type) SetCFG_DATA7_SDTD(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x4000000)|value<<26) +} +func (o *HINF_Type) GetCFG_DATA7_SDTD() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x4000000) >> 26 +} +func (o *HINF_Type) SetCFG_DATA7_SDTA(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x8000000)|value<<27) +} +func (o *HINF_Type) GetCFG_DATA7_SDTA() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x8000000) >> 27 +} +func (o *HINF_Type) SetCFG_DATA7_SDTC(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x10000000)|value<<28) +} +func (o *HINF_Type) GetCFG_DATA7_SDTC() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x10000000) >> 28 +} +func (o *HINF_Type) SetCFG_DATA7_SAI(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x20000000)|value<<29) +} +func (o *HINF_Type) GetCFG_DATA7_SAI() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x20000000) >> 29 +} +func (o *HINF_Type) SetCFG_DATA7_SDIO_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.CFG_DATA7.Reg, volatile.LoadUint32(&o.CFG_DATA7.Reg)&^(0x40000000)|value<<30) +} +func (o *HINF_Type) GetCFG_DATA7_SDIO_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA7.Reg) & 0x40000000) >> 30 +} + +// HINF.CIS_CONF_W0: SDIO cis configuration register +func (o *HINF_Type) SetCIS_CONF_W0(value uint32) { + volatile.StoreUint32(&o.CIS_CONF_W0.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF_W0() uint32 { + return volatile.LoadUint32(&o.CIS_CONF_W0.Reg) +} + +// HINF.CIS_CONF_W1: SDIO cis configuration register +func (o *HINF_Type) SetCIS_CONF_W1(value uint32) { + volatile.StoreUint32(&o.CIS_CONF_W1.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF_W1() uint32 { + return volatile.LoadUint32(&o.CIS_CONF_W1.Reg) +} + +// HINF.CIS_CONF_W2: SDIO cis configuration register +func (o *HINF_Type) SetCIS_CONF_W2(value uint32) { + volatile.StoreUint32(&o.CIS_CONF_W2.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF_W2() uint32 { + return volatile.LoadUint32(&o.CIS_CONF_W2.Reg) +} + +// HINF.CIS_CONF_W3: SDIO cis configuration register +func (o *HINF_Type) SetCIS_CONF_W3(value uint32) { + volatile.StoreUint32(&o.CIS_CONF_W3.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF_W3() uint32 { + return volatile.LoadUint32(&o.CIS_CONF_W3.Reg) +} + +// HINF.CIS_CONF_W4: SDIO cis configuration register +func (o *HINF_Type) SetCIS_CONF_W4(value uint32) { + volatile.StoreUint32(&o.CIS_CONF_W4.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF_W4() uint32 { + return volatile.LoadUint32(&o.CIS_CONF_W4.Reg) +} + +// HINF.CIS_CONF_W5: SDIO cis configuration register +func (o *HINF_Type) SetCIS_CONF_W5(value uint32) { + volatile.StoreUint32(&o.CIS_CONF_W5.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF_W5() uint32 { + return volatile.LoadUint32(&o.CIS_CONF_W5.Reg) +} + +// HINF.CIS_CONF_W6: SDIO cis configuration register +func (o *HINF_Type) SetCIS_CONF_W6(value uint32) { + volatile.StoreUint32(&o.CIS_CONF_W6.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF_W6() uint32 { + return volatile.LoadUint32(&o.CIS_CONF_W6.Reg) +} + +// HINF.CIS_CONF_W7: SDIO cis configuration register +func (o *HINF_Type) SetCIS_CONF_W7(value uint32) { + volatile.StoreUint32(&o.CIS_CONF_W7.Reg, value) +} +func (o *HINF_Type) GetCIS_CONF_W7() uint32 { + return volatile.LoadUint32(&o.CIS_CONF_W7.Reg) +} + +// HINF.CFG_DATA16: SDIO cis configuration register +func (o *HINF_Type) SetCFG_DATA16_DEVICE_ID_FN2(value uint32) { + volatile.StoreUint32(&o.CFG_DATA16.Reg, volatile.LoadUint32(&o.CFG_DATA16.Reg)&^(0xffff)|value) +} +func (o *HINF_Type) GetCFG_DATA16_DEVICE_ID_FN2() uint32 { + return volatile.LoadUint32(&o.CFG_DATA16.Reg) & 0xffff +} +func (o *HINF_Type) SetCFG_DATA16_USER_ID_FN2(value uint32) { + volatile.StoreUint32(&o.CFG_DATA16.Reg, volatile.LoadUint32(&o.CFG_DATA16.Reg)&^(0xffff0000)|value<<16) +} +func (o *HINF_Type) GetCFG_DATA16_USER_ID_FN2() uint32 { + return (volatile.LoadUint32(&o.CFG_DATA16.Reg) & 0xffff0000) >> 16 +} + +// HINF.CFG_UHS1_INT_MODE: configure int to start and end ahead of time in uhs1 mode +func (o *HINF_Type) SetCFG_UHS1_INT_MODE_INTOE_END_AHEAD_MODE(value uint32) { + volatile.StoreUint32(&o.CFG_UHS1_INT_MODE.Reg, volatile.LoadUint32(&o.CFG_UHS1_INT_MODE.Reg)&^(0x3)|value) +} +func (o *HINF_Type) GetCFG_UHS1_INT_MODE_INTOE_END_AHEAD_MODE() uint32 { + return volatile.LoadUint32(&o.CFG_UHS1_INT_MODE.Reg) & 0x3 +} +func (o *HINF_Type) SetCFG_UHS1_INT_MODE_INT_END_AHEAD_MODE(value uint32) { + volatile.StoreUint32(&o.CFG_UHS1_INT_MODE.Reg, volatile.LoadUint32(&o.CFG_UHS1_INT_MODE.Reg)&^(0xc)|value<<2) +} +func (o *HINF_Type) GetCFG_UHS1_INT_MODE_INT_END_AHEAD_MODE() uint32 { + return (volatile.LoadUint32(&o.CFG_UHS1_INT_MODE.Reg) & 0xc) >> 2 +} +func (o *HINF_Type) SetCFG_UHS1_INT_MODE_INTOE_ST_AHEAD_MODE(value uint32) { + volatile.StoreUint32(&o.CFG_UHS1_INT_MODE.Reg, volatile.LoadUint32(&o.CFG_UHS1_INT_MODE.Reg)&^(0x30)|value<<4) +} +func (o *HINF_Type) GetCFG_UHS1_INT_MODE_INTOE_ST_AHEAD_MODE() uint32 { + return (volatile.LoadUint32(&o.CFG_UHS1_INT_MODE.Reg) & 0x30) >> 4 +} +func (o *HINF_Type) SetCFG_UHS1_INT_MODE_INT_ST_AHEAD_MODE(value uint32) { + volatile.StoreUint32(&o.CFG_UHS1_INT_MODE.Reg, volatile.LoadUint32(&o.CFG_UHS1_INT_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *HINF_Type) GetCFG_UHS1_INT_MODE_INT_ST_AHEAD_MODE() uint32 { + return (volatile.LoadUint32(&o.CFG_UHS1_INT_MODE.Reg) & 0xc0) >> 6 +} + +// HINF.CONF_STATUS: func0 config0 status +func (o *HINF_Type) SetCONF_STATUS_FUNC0_CONFIG0(value uint32) { + volatile.StoreUint32(&o.CONF_STATUS.Reg, volatile.LoadUint32(&o.CONF_STATUS.Reg)&^(0xff)|value) +} +func (o *HINF_Type) GetCONF_STATUS_FUNC0_CONFIG0() uint32 { + return volatile.LoadUint32(&o.CONF_STATUS.Reg) & 0xff +} +func (o *HINF_Type) SetCONF_STATUS_SDR25_ST(value uint32) { + volatile.StoreUint32(&o.CONF_STATUS.Reg, volatile.LoadUint32(&o.CONF_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *HINF_Type) GetCONF_STATUS_SDR25_ST() uint32 { + return (volatile.LoadUint32(&o.CONF_STATUS.Reg) & 0x100) >> 8 +} +func (o *HINF_Type) SetCONF_STATUS_SDR50_ST(value uint32) { + volatile.StoreUint32(&o.CONF_STATUS.Reg, volatile.LoadUint32(&o.CONF_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *HINF_Type) GetCONF_STATUS_SDR50_ST() uint32 { + return (volatile.LoadUint32(&o.CONF_STATUS.Reg) & 0x200) >> 9 +} +func (o *HINF_Type) SetCONF_STATUS_SDR104_ST(value uint32) { + volatile.StoreUint32(&o.CONF_STATUS.Reg, volatile.LoadUint32(&o.CONF_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *HINF_Type) GetCONF_STATUS_SDR104_ST() uint32 { + return (volatile.LoadUint32(&o.CONF_STATUS.Reg) & 0x400) >> 10 +} +func (o *HINF_Type) SetCONF_STATUS_DDR50_ST(value uint32) { + volatile.StoreUint32(&o.CONF_STATUS.Reg, volatile.LoadUint32(&o.CONF_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *HINF_Type) GetCONF_STATUS_DDR50_ST() uint32 { + return (volatile.LoadUint32(&o.CONF_STATUS.Reg) & 0x800) >> 11 +} +func (o *HINF_Type) SetCONF_STATUS_TUNE_ST(value uint32) { + volatile.StoreUint32(&o.CONF_STATUS.Reg, volatile.LoadUint32(&o.CONF_STATUS.Reg)&^(0x7000)|value<<12) +} +func (o *HINF_Type) GetCONF_STATUS_TUNE_ST() uint32 { + return (volatile.LoadUint32(&o.CONF_STATUS.Reg) & 0x7000) >> 12 +} +func (o *HINF_Type) SetCONF_STATUS_SDIO_SWITCH_VOLT_ST(value uint32) { + volatile.StoreUint32(&o.CONF_STATUS.Reg, volatile.LoadUint32(&o.CONF_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *HINF_Type) GetCONF_STATUS_SDIO_SWITCH_VOLT_ST() uint32 { + return (volatile.LoadUint32(&o.CONF_STATUS.Reg) & 0x8000) >> 15 +} +func (o *HINF_Type) SetCONF_STATUS_SDIO_SWITCH_END(value uint32) { + volatile.StoreUint32(&o.CONF_STATUS.Reg, volatile.LoadUint32(&o.CONF_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *HINF_Type) GetCONF_STATUS_SDIO_SWITCH_END() uint32 { + return (volatile.LoadUint32(&o.CONF_STATUS.Reg) & 0x10000) >> 16 +} + +// HINF.SDIO_SLAVE_ECO_LOW: sdio_slave redundant control registers +func (o *HINF_Type) SetSDIO_SLAVE_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_ECO_LOW.Reg, value) +} +func (o *HINF_Type) GetSDIO_SLAVE_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.SDIO_SLAVE_ECO_LOW.Reg) +} + +// HINF.SDIO_SLAVE_ECO_HIGH: sdio_slave redundant control registers +func (o *HINF_Type) SetSDIO_SLAVE_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_ECO_HIGH.Reg, value) +} +func (o *HINF_Type) GetSDIO_SLAVE_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.SDIO_SLAVE_ECO_HIGH.Reg) +} + +// HINF.SDIO_SLAVE_ECO_CONF: sdio_slave redundant control registers +func (o *HINF_Type) SetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_ECO_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg)&^(0x1)|value) +} +func (o *HINF_Type) GetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_RESULT() uint32 { + return volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg) & 0x1 +} +func (o *HINF_Type) SetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_ECO_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg)&^(0x2)|value<<1) +} +func (o *HINF_Type) GetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_ENA() uint32 { + return (volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg) & 0x2) >> 1 +} +func (o *HINF_Type) SetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_ECO_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg)&^(0x4)|value<<2) +} +func (o *HINF_Type) GetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg) & 0x4) >> 2 +} +func (o *HINF_Type) SetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_ECO_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg)&^(0x8)|value<<3) +} +func (o *HINF_Type) GetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_ENA() uint32 { + return (volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg) & 0x8) >> 3 +} +func (o *HINF_Type) SetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_ECO_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg)&^(0x10)|value<<4) +} +func (o *HINF_Type) GetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg) & 0x10) >> 4 +} +func (o *HINF_Type) SetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_ECO_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg)&^(0x20)|value<<5) +} +func (o *HINF_Type) GetSDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA() uint32 { + return (volatile.LoadUint32(&o.SDIO_SLAVE_ECO_CONF.Reg) & 0x20) >> 5 +} + +// HINF.SDIO_SLAVE_LDO_CONF: sdio slave ldo control register +func (o *HINF_Type) SetSDIO_SLAVE_LDO_CONF_LDO_READY_CTL_IN_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_LDO_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_LDO_CONF.Reg)&^(0x1)|value) +} +func (o *HINF_Type) GetSDIO_SLAVE_LDO_CONF_LDO_READY_CTL_IN_EN() uint32 { + return volatile.LoadUint32(&o.SDIO_SLAVE_LDO_CONF.Reg) & 0x1 +} +func (o *HINF_Type) SetSDIO_SLAVE_LDO_CONF_LDO_READY_THRES(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_LDO_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_LDO_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *HINF_Type) GetSDIO_SLAVE_LDO_CONF_LDO_READY_THRES() uint32 { + return (volatile.LoadUint32(&o.SDIO_SLAVE_LDO_CONF.Reg) & 0x3e) >> 1 +} +func (o *HINF_Type) SetSDIO_SLAVE_LDO_CONF_LDO_READY_IGNORE_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_LDO_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_LDO_CONF.Reg)&^(0x40)|value<<6) +} +func (o *HINF_Type) GetSDIO_SLAVE_LDO_CONF_LDO_READY_IGNORE_EN() uint32 { + return (volatile.LoadUint32(&o.SDIO_SLAVE_LDO_CONF.Reg) & 0x40) >> 6 +} + +// HINF.SDIO_DATE: ******* Description *********** +func (o *HINF_Type) SetSDIO_DATE(value uint32) { + volatile.StoreUint32(&o.SDIO_DATE.Reg, value) +} +func (o *HINF_Type) GetSDIO_DATE() uint32 { + return volatile.LoadUint32(&o.SDIO_DATE.Reg) +} + +// HMAC (Hash-based Message Authentication Code) Accelerator +type HMAC_Type struct { + _ [64]byte + SET_START volatile.Register32 // 0x40 + SET_PARA_PURPOSE volatile.Register32 // 0x44 + SET_PARA_KEY volatile.Register32 // 0x48 + SET_PARA_FINISH volatile.Register32 // 0x4C + SET_MESSAGE_ONE volatile.Register32 // 0x50 + SET_MESSAGE_ING volatile.Register32 // 0x54 + SET_MESSAGE_END volatile.Register32 // 0x58 + SET_RESULT_FINISH volatile.Register32 // 0x5C + SET_INVALIDATE_JTAG volatile.Register32 // 0x60 + SET_INVALIDATE_DS volatile.Register32 // 0x64 + QUERY_ERROR volatile.Register32 // 0x68 + QUERY_BUSY volatile.Register32 // 0x6C + _ [16]byte + WR_MESSAGE_MEM [64]volatile.Register8 // 0x80 + RD_RESULT_MEM [32]volatile.Register8 // 0xC0 + _ [16]byte + SET_MESSAGE_PAD volatile.Register32 // 0xF0 + ONE_BLOCK volatile.Register32 // 0xF4 + SOFT_JTAG_CTRL volatile.Register32 // 0xF8 + WR_JTAG volatile.Register32 // 0xFC + _ [252]byte + DATE volatile.Register32 // 0x1FC +} + +// HMAC.SET_START: Process control register 0. +func (o *HMAC_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// HMAC.SET_PARA_PURPOSE: Configure purpose. +func (o *HMAC_Type) SetSET_PARA_PURPOSE_PURPOSE_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_PURPOSE.Reg, volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg)&^(0xf)|value) +} +func (o *HMAC_Type) GetSET_PARA_PURPOSE_PURPOSE_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg) & 0xf +} + +// HMAC.SET_PARA_KEY: Configure key. +func (o *HMAC_Type) SetSET_PARA_KEY_KEY_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_KEY.Reg, volatile.LoadUint32(&o.SET_PARA_KEY.Reg)&^(0x7)|value) +} +func (o *HMAC_Type) GetSET_PARA_KEY_KEY_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_KEY.Reg) & 0x7 +} + +// HMAC.SET_PARA_FINISH: Finish initial configuration. +func (o *HMAC_Type) SetSET_PARA_FINISH_SET_PARA_END(value uint32) { + volatile.StoreUint32(&o.SET_PARA_FINISH.Reg, volatile.LoadUint32(&o.SET_PARA_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_PARA_FINISH_SET_PARA_END() uint32 { + return volatile.LoadUint32(&o.SET_PARA_FINISH.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ONE: Process control register 1. +func (o *HMAC_Type) SetSET_MESSAGE_ONE_SET_TEXT_ONE(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ONE.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ONE_SET_TEXT_ONE() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ING: Process control register 2. +func (o *HMAC_Type) SetSET_MESSAGE_ING_SET_TEXT_ING(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ING.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ING_SET_TEXT_ING() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_END: Process control register 3. +func (o *HMAC_Type) SetSET_MESSAGE_END_SET_TEXT_END(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_END.Reg, volatile.LoadUint32(&o.SET_MESSAGE_END.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_END_SET_TEXT_END() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_END.Reg) & 0x1 +} + +// HMAC.SET_RESULT_FINISH: Process control register 4. +func (o *HMAC_Type) SetSET_RESULT_FINISH_SET_RESULT_END(value uint32) { + volatile.StoreUint32(&o.SET_RESULT_FINISH.Reg, volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_RESULT_FINISH_SET_RESULT_END() uint32 { + return volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_JTAG: Invalidate register 0. +func (o *HMAC_Type) SetSET_INVALIDATE_JTAG(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_JTAG.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_JTAG() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_DS: Invalidate register 1. +func (o *HMAC_Type) SetSET_INVALIDATE_DS(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_DS.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_DS() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg) & 0x1 +} + +// HMAC.QUERY_ERROR: Error register. +func (o *HMAC_Type) SetQUERY_ERROR_QUERY_CHECK(value uint32) { + volatile.StoreUint32(&o.QUERY_ERROR.Reg, volatile.LoadUint32(&o.QUERY_ERROR.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_ERROR_QUERY_CHECK() uint32 { + return volatile.LoadUint32(&o.QUERY_ERROR.Reg) & 0x1 +} + +// HMAC.QUERY_BUSY: Busy register. +func (o *HMAC_Type) SetQUERY_BUSY_BUSY_STATE(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_BUSY_BUSY_STATE() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_PAD: Process control register 5. +func (o *HMAC_Type) SetSET_MESSAGE_PAD_SET_TEXT_PAD(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_PAD.Reg, volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_PAD_SET_TEXT_PAD() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg) & 0x1 +} + +// HMAC.ONE_BLOCK: Process control register 6. +func (o *HMAC_Type) SetONE_BLOCK_SET_ONE_BLOCK(value uint32) { + volatile.StoreUint32(&o.ONE_BLOCK.Reg, volatile.LoadUint32(&o.ONE_BLOCK.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetONE_BLOCK_SET_ONE_BLOCK() uint32 { + return volatile.LoadUint32(&o.ONE_BLOCK.Reg) & 0x1 +} + +// HMAC.SOFT_JTAG_CTRL: Jtag register 0. +func (o *HMAC_Type) SetSOFT_JTAG_CTRL(value uint32) { + volatile.StoreUint32(&o.SOFT_JTAG_CTRL.Reg, volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSOFT_JTAG_CTRL() uint32 { + return volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg) & 0x1 +} + +// HMAC.WR_JTAG: Jtag register 1. +func (o *HMAC_Type) SetWR_JTAG(value uint32) { + volatile.StoreUint32(&o.WR_JTAG.Reg, value) +} +func (o *HMAC_Type) GetWR_JTAG() uint32 { + return volatile.LoadUint32(&o.WR_JTAG.Reg) +} + +// HMAC.DATE: Date register. +func (o *HMAC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *HMAC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// HP_APM Peripheral +type HP_APM_Type struct { + REGION_FILTER_EN volatile.Register32 // 0x0 + REGION0_ADDR_START volatile.Register32 // 0x4 + REGION0_ADDR_END volatile.Register32 // 0x8 + REGION0_PMS_ATTR volatile.Register32 // 0xC + REGION1_ADDR_START volatile.Register32 // 0x10 + REGION1_ADDR_END volatile.Register32 // 0x14 + REGION1_PMS_ATTR volatile.Register32 // 0x18 + REGION2_ADDR_START volatile.Register32 // 0x1C + REGION2_ADDR_END volatile.Register32 // 0x20 + REGION2_PMS_ATTR volatile.Register32 // 0x24 + REGION3_ADDR_START volatile.Register32 // 0x28 + REGION3_ADDR_END volatile.Register32 // 0x2C + REGION3_PMS_ATTR volatile.Register32 // 0x30 + REGION4_ADDR_START volatile.Register32 // 0x34 + REGION4_ADDR_END volatile.Register32 // 0x38 + REGION4_PMS_ATTR volatile.Register32 // 0x3C + REGION5_ADDR_START volatile.Register32 // 0x40 + REGION5_ADDR_END volatile.Register32 // 0x44 + REGION5_PMS_ATTR volatile.Register32 // 0x48 + REGION6_ADDR_START volatile.Register32 // 0x4C + REGION6_ADDR_END volatile.Register32 // 0x50 + REGION6_PMS_ATTR volatile.Register32 // 0x54 + REGION7_ADDR_START volatile.Register32 // 0x58 + REGION7_ADDR_END volatile.Register32 // 0x5C + REGION7_PMS_ATTR volatile.Register32 // 0x60 + REGION8_ADDR_START volatile.Register32 // 0x64 + REGION8_ADDR_END volatile.Register32 // 0x68 + REGION8_PMS_ATTR volatile.Register32 // 0x6C + REGION9_ADDR_START volatile.Register32 // 0x70 + REGION9_ADDR_END volatile.Register32 // 0x74 + REGION9_PMS_ATTR volatile.Register32 // 0x78 + REGION10_ADDR_START volatile.Register32 // 0x7C + REGION10_ADDR_END volatile.Register32 // 0x80 + REGION10_PMS_ATTR volatile.Register32 // 0x84 + REGION11_ADDR_START volatile.Register32 // 0x88 + REGION11_ADDR_END volatile.Register32 // 0x8C + REGION11_PMS_ATTR volatile.Register32 // 0x90 + REGION12_ADDR_START volatile.Register32 // 0x94 + REGION12_ADDR_END volatile.Register32 // 0x98 + REGION12_PMS_ATTR volatile.Register32 // 0x9C + REGION13_ADDR_START volatile.Register32 // 0xA0 + REGION13_ADDR_END volatile.Register32 // 0xA4 + REGION13_PMS_ATTR volatile.Register32 // 0xA8 + REGION14_ADDR_START volatile.Register32 // 0xAC + REGION14_ADDR_END volatile.Register32 // 0xB0 + REGION14_PMS_ATTR volatile.Register32 // 0xB4 + REGION15_ADDR_START volatile.Register32 // 0xB8 + REGION15_ADDR_END volatile.Register32 // 0xBC + REGION15_PMS_ATTR volatile.Register32 // 0xC0 + FUNC_CTRL volatile.Register32 // 0xC4 + M0_STATUS volatile.Register32 // 0xC8 + M0_STATUS_CLR volatile.Register32 // 0xCC + M0_EXCEPTION_INFO0 volatile.Register32 // 0xD0 + M0_EXCEPTION_INFO1 volatile.Register32 // 0xD4 + M1_STATUS volatile.Register32 // 0xD8 + M1_STATUS_CLR volatile.Register32 // 0xDC + M1_EXCEPTION_INFO0 volatile.Register32 // 0xE0 + M1_EXCEPTION_INFO1 volatile.Register32 // 0xE4 + M2_STATUS volatile.Register32 // 0xE8 + M2_STATUS_CLR volatile.Register32 // 0xEC + M2_EXCEPTION_INFO0 volatile.Register32 // 0xF0 + M2_EXCEPTION_INFO1 volatile.Register32 // 0xF4 + M3_STATUS volatile.Register32 // 0xF8 + M3_STATUS_CLR volatile.Register32 // 0xFC + M3_EXCEPTION_INFO0 volatile.Register32 // 0x100 + M3_EXCEPTION_INFO1 volatile.Register32 // 0x104 + INT_EN volatile.Register32 // 0x108 + CLOCK_GATE volatile.Register32 // 0x10C + _ [1772]byte + DATE volatile.Register32 // 0x7FC +} + +// HP_APM.REGION_FILTER_EN: Region filter enable register +func (o *HP_APM_Type) SetREGION_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.REGION_FILTER_EN.Reg, volatile.LoadUint32(&o.REGION_FILTER_EN.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetREGION_FILTER_EN() uint32 { + return volatile.LoadUint32(&o.REGION_FILTER_EN.Reg) & 0xffff +} + +// HP_APM.REGION0_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION0_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION0_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_START.Reg) +} + +// HP_APM.REGION0_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION0_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION0_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_END.Reg) +} + +// HP_APM.REGION0_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION1_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION1_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION1_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_START.Reg) +} + +// HP_APM.REGION1_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION1_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION1_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_END.Reg) +} + +// HP_APM.REGION1_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION2_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION2_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION2_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_START.Reg) +} + +// HP_APM.REGION2_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION2_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION2_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_END.Reg) +} + +// HP_APM.REGION2_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION3_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION3_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION3_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_START.Reg) +} + +// HP_APM.REGION3_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION3_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION3_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_END.Reg) +} + +// HP_APM.REGION3_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION4_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION4_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION4_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION4_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION4_ADDR_START.Reg) +} + +// HP_APM.REGION4_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION4_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION4_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION4_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION4_ADDR_END.Reg) +} + +// HP_APM.REGION4_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION5_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION5_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION5_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION5_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION5_ADDR_START.Reg) +} + +// HP_APM.REGION5_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION5_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION5_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION5_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION5_ADDR_END.Reg) +} + +// HP_APM.REGION5_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION6_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION6_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION6_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION6_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION6_ADDR_START.Reg) +} + +// HP_APM.REGION6_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION6_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION6_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION6_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION6_ADDR_END.Reg) +} + +// HP_APM.REGION6_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION7_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION7_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION7_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION7_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION7_ADDR_START.Reg) +} + +// HP_APM.REGION7_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION7_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION7_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION7_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION7_ADDR_END.Reg) +} + +// HP_APM.REGION7_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION8_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION8_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION8_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION8_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION8_ADDR_START.Reg) +} + +// HP_APM.REGION8_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION8_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION8_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION8_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION8_ADDR_END.Reg) +} + +// HP_APM.REGION8_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION9_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION9_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION9_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION9_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION9_ADDR_START.Reg) +} + +// HP_APM.REGION9_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION9_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION9_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION9_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION9_ADDR_END.Reg) +} + +// HP_APM.REGION9_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION10_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION10_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION10_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION10_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION10_ADDR_START.Reg) +} + +// HP_APM.REGION10_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION10_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION10_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION10_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION10_ADDR_END.Reg) +} + +// HP_APM.REGION10_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION11_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION11_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION11_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION11_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION11_ADDR_START.Reg) +} + +// HP_APM.REGION11_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION11_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION11_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION11_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION11_ADDR_END.Reg) +} + +// HP_APM.REGION11_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION12_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION12_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION12_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION12_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION12_ADDR_START.Reg) +} + +// HP_APM.REGION12_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION12_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION12_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION12_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION12_ADDR_END.Reg) +} + +// HP_APM.REGION12_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION13_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION13_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION13_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION13_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION13_ADDR_START.Reg) +} + +// HP_APM.REGION13_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION13_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION13_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION13_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION13_ADDR_END.Reg) +} + +// HP_APM.REGION13_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION14_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION14_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION14_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION14_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION14_ADDR_START.Reg) +} + +// HP_APM.REGION14_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION14_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION14_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION14_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION14_ADDR_END.Reg) +} + +// HP_APM.REGION14_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION15_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION15_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION15_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION15_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION15_ADDR_START.Reg) +} + +// HP_APM.REGION15_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION15_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION15_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION15_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION15_ADDR_END.Reg) +} + +// HP_APM.REGION15_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.FUNC_CTRL: PMS function control register +func (o *HP_APM_Type) SetFUNC_CTRL_M0_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetFUNC_CTRL_M0_PMS_FUNC_EN() uint32 { + return volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x1 +} +func (o *HP_APM_Type) SetFUNC_CTRL_M1_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetFUNC_CTRL_M1_PMS_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetFUNC_CTRL_M2_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetFUNC_CTRL_M2_PMS_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetFUNC_CTRL_M3_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *HP_APM_Type) GetFUNC_CTRL_M3_PMS_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x8) >> 3 +} + +// HP_APM.M0_STATUS: M0 status register +func (o *HP_APM_Type) SetM0_STATUS_M0_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M0_STATUS.Reg, volatile.LoadUint32(&o.M0_STATUS.Reg)&^(0x3)|value) +} +func (o *HP_APM_Type) GetM0_STATUS_M0_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M0_STATUS.Reg) & 0x3 +} + +// HP_APM.M0_STATUS_CLR: M0 status clear register +func (o *HP_APM_Type) SetM0_STATUS_CLR_M0_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M0_STATUS_CLR.Reg, volatile.LoadUint32(&o.M0_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetM0_STATUS_CLR_M0_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M0_STATUS_CLR.Reg) & 0x1 +} + +// HP_APM.M0_EXCEPTION_INFO0: M0 exception_info0 register +func (o *HP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0xffff +} +func (o *HP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *HP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *HP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *HP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// HP_APM.M0_EXCEPTION_INFO1: M0 exception_info1 register +func (o *HP_APM_Type) SetM0_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO1.Reg, value) +} +func (o *HP_APM_Type) GetM0_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO1.Reg) +} + +// HP_APM.M1_STATUS: M1 status register +func (o *HP_APM_Type) SetM1_STATUS_M1_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M1_STATUS.Reg, volatile.LoadUint32(&o.M1_STATUS.Reg)&^(0x3)|value) +} +func (o *HP_APM_Type) GetM1_STATUS_M1_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M1_STATUS.Reg) & 0x3 +} + +// HP_APM.M1_STATUS_CLR: M1 status clear register +func (o *HP_APM_Type) SetM1_STATUS_CLR_M1_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M1_STATUS_CLR.Reg, volatile.LoadUint32(&o.M1_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetM1_STATUS_CLR_M1_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M1_STATUS_CLR.Reg) & 0x1 +} + +// HP_APM.M1_EXCEPTION_INFO0: M1 exception_info0 register +func (o *HP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0xffff +} +func (o *HP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *HP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *HP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *HP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// HP_APM.M1_EXCEPTION_INFO1: M1 exception_info1 register +func (o *HP_APM_Type) SetM1_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO1.Reg, value) +} +func (o *HP_APM_Type) GetM1_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M1_EXCEPTION_INFO1.Reg) +} + +// HP_APM.M2_STATUS: M2 status register +func (o *HP_APM_Type) SetM2_STATUS_M2_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M2_STATUS.Reg, volatile.LoadUint32(&o.M2_STATUS.Reg)&^(0x3)|value) +} +func (o *HP_APM_Type) GetM2_STATUS_M2_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M2_STATUS.Reg) & 0x3 +} + +// HP_APM.M2_STATUS_CLR: M2 status clear register +func (o *HP_APM_Type) SetM2_STATUS_CLR_M2_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M2_STATUS_CLR.Reg, volatile.LoadUint32(&o.M2_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetM2_STATUS_CLR_M2_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M2_STATUS_CLR.Reg) & 0x1 +} + +// HP_APM.M2_EXCEPTION_INFO0: M2 exception_info0 register +func (o *HP_APM_Type) SetM2_EXCEPTION_INFO0_M2_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M2_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetM2_EXCEPTION_INFO0_M2_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg) & 0xffff +} +func (o *HP_APM_Type) SetM2_EXCEPTION_INFO0_M2_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M2_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *HP_APM_Type) GetM2_EXCEPTION_INFO0_M2_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *HP_APM_Type) SetM2_EXCEPTION_INFO0_M2_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M2_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *HP_APM_Type) GetM2_EXCEPTION_INFO0_M2_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// HP_APM.M2_EXCEPTION_INFO1: M2 exception_info1 register +func (o *HP_APM_Type) SetM2_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M2_EXCEPTION_INFO1.Reg, value) +} +func (o *HP_APM_Type) GetM2_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M2_EXCEPTION_INFO1.Reg) +} + +// HP_APM.M3_STATUS: M3 status register +func (o *HP_APM_Type) SetM3_STATUS_M3_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M3_STATUS.Reg, volatile.LoadUint32(&o.M3_STATUS.Reg)&^(0x3)|value) +} +func (o *HP_APM_Type) GetM3_STATUS_M3_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M3_STATUS.Reg) & 0x3 +} + +// HP_APM.M3_STATUS_CLR: M3 status clear register +func (o *HP_APM_Type) SetM3_STATUS_CLR_M3_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M3_STATUS_CLR.Reg, volatile.LoadUint32(&o.M3_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetM3_STATUS_CLR_M3_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M3_STATUS_CLR.Reg) & 0x1 +} + +// HP_APM.M3_EXCEPTION_INFO0: M3 exception_info0 register +func (o *HP_APM_Type) SetM3_EXCEPTION_INFO0_M3_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M3_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetM3_EXCEPTION_INFO0_M3_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg) & 0xffff +} +func (o *HP_APM_Type) SetM3_EXCEPTION_INFO0_M3_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M3_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *HP_APM_Type) GetM3_EXCEPTION_INFO0_M3_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *HP_APM_Type) SetM3_EXCEPTION_INFO0_M3_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M3_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *HP_APM_Type) GetM3_EXCEPTION_INFO0_M3_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// HP_APM.M3_EXCEPTION_INFO1: M3 exception_info1 register +func (o *HP_APM_Type) SetM3_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M3_EXCEPTION_INFO1.Reg, value) +} +func (o *HP_APM_Type) GetM3_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M3_EXCEPTION_INFO1.Reg) +} + +// HP_APM.INT_EN: APM interrupt enable register +func (o *HP_APM_Type) SetINT_EN_M0_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetINT_EN_M0_APM_INT_EN() uint32 { + return volatile.LoadUint32(&o.INT_EN.Reg) & 0x1 +} +func (o *HP_APM_Type) SetINT_EN_M1_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetINT_EN_M1_APM_INT_EN() uint32 { + return (volatile.LoadUint32(&o.INT_EN.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetINT_EN_M2_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetINT_EN_M2_APM_INT_EN() uint32 { + return (volatile.LoadUint32(&o.INT_EN.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetINT_EN_M3_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x8)|value<<3) +} +func (o *HP_APM_Type) GetINT_EN_M3_APM_INT_EN() uint32 { + return (volatile.LoadUint32(&o.INT_EN.Reg) & 0x8) >> 3 +} + +// HP_APM.CLOCK_GATE: clock gating register +func (o *HP_APM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// HP_APM.DATE: Version register +func (o *HP_APM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *HP_APM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// High-Power System +type HP_SYS_Type struct { + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL volatile.Register32 // 0x0 + SRAM_USAGE_CONF volatile.Register32 // 0x4 + SEC_DPA_CONF volatile.Register32 // 0x8 + CPU_PERI_TIMEOUT_CONF volatile.Register32 // 0xC + CPU_PERI_TIMEOUT_ADDR volatile.Register32 // 0x10 + CPU_PERI_TIMEOUT_UID volatile.Register32 // 0x14 + HP_PERI_TIMEOUT_CONF volatile.Register32 // 0x18 + HP_PERI_TIMEOUT_ADDR volatile.Register32 // 0x1C + HP_PERI_TIMEOUT_UID volatile.Register32 // 0x20 + MODEM_PERI_TIMEOUT_CONF volatile.Register32 // 0x24 + MODEM_PERI_TIMEOUT_ADDR volatile.Register32 // 0x28 + MODEM_PERI_TIMEOUT_UID volatile.Register32 // 0x2C + SDIO_CTRL volatile.Register32 // 0x30 + RETENTION_CONF volatile.Register32 // 0x34 + ROM_TABLE_LOCK volatile.Register32 // 0x38 + ROM_TABLE volatile.Register32 // 0x3C + CORE_DEBUG_RUNSTALL_CONF volatile.Register32 // 0x40 + MEM_TEST_CONF volatile.Register32 // 0x44 + _ [920]byte + RND_ECO volatile.Register32 // 0x3E0 + RND_ECO_LOW volatile.Register32 // 0x3E4 + RND_ECO_HIGH volatile.Register32 // 0x3E8 + _ [12]byte + CLOCK_GATE volatile.Register32 // 0x3F8 + DATE volatile.Register32 // 0x3FC +} + +// HP_SYS.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register +func (o *HP_SYS_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x8) >> 3 +} + +// HP_SYS.SRAM_USAGE_CONF: HP memory usage configuration register +func (o *HP_SYS_Type) SetSRAM_USAGE_CONF_CACHE_USAGE(value uint32) { + volatile.StoreUint32(&o.SRAM_USAGE_CONF.Reg, volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetSRAM_USAGE_CONF_CACHE_USAGE() uint32 { + return volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetSRAM_USAGE_CONF_SRAM_USAGE(value uint32) { + volatile.StoreUint32(&o.SRAM_USAGE_CONF.Reg, volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg)&^(0xf00)|value<<8) +} +func (o *HP_SYS_Type) GetSRAM_USAGE_CONF_SRAM_USAGE() uint32 { + return (volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg) & 0xf00) >> 8 +} +func (o *HP_SYS_Type) SetSRAM_USAGE_CONF_MAC_DUMP_ALLOC(value uint32) { + volatile.StoreUint32(&o.SRAM_USAGE_CONF.Reg, volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_Type) GetSRAM_USAGE_CONF_MAC_DUMP_ALLOC() uint32 { + return (volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg) & 0x10000) >> 16 +} + +// HP_SYS.SEC_DPA_CONF: HP anti-DPA security configuration register +func (o *HP_SYS_Type) SetSEC_DPA_CONF_SEC_DPA_LEVEL(value uint32) { + volatile.StoreUint32(&o.SEC_DPA_CONF.Reg, volatile.LoadUint32(&o.SEC_DPA_CONF.Reg)&^(0x3)|value) +} +func (o *HP_SYS_Type) GetSEC_DPA_CONF_SEC_DPA_LEVEL() uint32 { + return volatile.LoadUint32(&o.SEC_DPA_CONF.Reg) & 0x3 +} +func (o *HP_SYS_Type) SetSEC_DPA_CONF_SEC_DPA_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.SEC_DPA_CONF.Reg, volatile.LoadUint32(&o.SEC_DPA_CONF.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetSEC_DPA_CONF_SEC_DPA_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.SEC_DPA_CONF.Reg) & 0x4) >> 2 +} + +// HP_SYS.CPU_PERI_TIMEOUT_CONF: CPU_PERI_TIMEOUT configuration register +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg)&^(0xffff)|value) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_THRES() uint32 { + return volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg) & 0xffff +} +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg) & 0x20000) >> 17 +} + +// HP_SYS.CPU_PERI_TIMEOUT_ADDR: CPU_PERI_TIMEOUT_ADDR register +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_ADDR(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_ADDR.Reg, value) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_ADDR() uint32 { + return volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_ADDR.Reg) +} + +// HP_SYS.CPU_PERI_TIMEOUT_UID: CPU_PERI_TIMEOUT_UID register +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_UID(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_UID.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_UID.Reg)&^(0x7f)|value) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_UID() uint32 { + return volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_UID.Reg) & 0x7f +} + +// HP_SYS.HP_PERI_TIMEOUT_CONF: HP_PERI_TIMEOUT configuration register +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg)&^(0xffff)|value) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_THRES() uint32 { + return volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg) & 0xffff +} +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR() uint32 { + return (volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN() uint32 { + return (volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg) & 0x20000) >> 17 +} + +// HP_SYS.HP_PERI_TIMEOUT_ADDR: HP_PERI_TIMEOUT_ADDR register +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_ADDR(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_ADDR.Reg, value) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_ADDR() uint32 { + return volatile.LoadUint32(&o.HP_PERI_TIMEOUT_ADDR.Reg) +} + +// HP_SYS.HP_PERI_TIMEOUT_UID: HP_PERI_TIMEOUT_UID register +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_UID(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_UID.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_UID.Reg)&^(0x7f)|value) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_UID() uint32 { + return volatile.LoadUint32(&o.HP_PERI_TIMEOUT_UID.Reg) & 0x7f +} + +// HP_SYS.MODEM_PERI_TIMEOUT_CONF: MODEM_PERI_TIMEOUT configuration register +func (o *HP_SYS_Type) SetMODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.MODEM_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_CONF.Reg)&^(0xffff)|value) +} +func (o *HP_SYS_Type) GetMODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_THRES() uint32 { + return volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_CONF.Reg) & 0xffff +} +func (o *HP_SYS_Type) SetMODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.MODEM_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_Type) GetMODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_INT_CLEAR() uint32 { + return (volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_CONF.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_Type) SetMODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_PROTECT_EN(value uint32) { + volatile.StoreUint32(&o.MODEM_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_Type) GetMODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_PROTECT_EN() uint32 { + return (volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_CONF.Reg) & 0x20000) >> 17 +} + +// HP_SYS.MODEM_PERI_TIMEOUT_ADDR: MODEM_PERI_TIMEOUT_ADDR register +func (o *HP_SYS_Type) SetMODEM_PERI_TIMEOUT_ADDR(value uint32) { + volatile.StoreUint32(&o.MODEM_PERI_TIMEOUT_ADDR.Reg, value) +} +func (o *HP_SYS_Type) GetMODEM_PERI_TIMEOUT_ADDR() uint32 { + return volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_ADDR.Reg) +} + +// HP_SYS.MODEM_PERI_TIMEOUT_UID: MODEM_PERI_TIMEOUT_UID register +func (o *HP_SYS_Type) SetMODEM_PERI_TIMEOUT_UID(value uint32) { + volatile.StoreUint32(&o.MODEM_PERI_TIMEOUT_UID.Reg, volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_UID.Reg)&^(0x7f)|value) +} +func (o *HP_SYS_Type) GetMODEM_PERI_TIMEOUT_UID() uint32 { + return volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_UID.Reg) & 0x7f +} + +// HP_SYS.SDIO_CTRL: SDIO Control configuration register +func (o *HP_SYS_Type) SetSDIO_CTRL_DIS_SDIO_PROB(value uint32) { + volatile.StoreUint32(&o.SDIO_CTRL.Reg, volatile.LoadUint32(&o.SDIO_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetSDIO_CTRL_DIS_SDIO_PROB() uint32 { + return volatile.LoadUint32(&o.SDIO_CTRL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetSDIO_CTRL_SDIO_WIN_ACCESS_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_CTRL.Reg, volatile.LoadUint32(&o.SDIO_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetSDIO_CTRL_SDIO_WIN_ACCESS_EN() uint32 { + return (volatile.LoadUint32(&o.SDIO_CTRL.Reg) & 0x2) >> 1 +} + +// HP_SYS.RETENTION_CONF: Retention configuration register +func (o *HP_SYS_Type) SetRETENTION_CONF_RETENTION_DISABLE(value uint32) { + volatile.StoreUint32(&o.RETENTION_CONF.Reg, volatile.LoadUint32(&o.RETENTION_CONF.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetRETENTION_CONF_RETENTION_DISABLE() uint32 { + return volatile.LoadUint32(&o.RETENTION_CONF.Reg) & 0x1 +} + +// HP_SYS.ROM_TABLE_LOCK: Rom-Table lock register +func (o *HP_SYS_Type) SetROM_TABLE_LOCK(value uint32) { + volatile.StoreUint32(&o.ROM_TABLE_LOCK.Reg, volatile.LoadUint32(&o.ROM_TABLE_LOCK.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetROM_TABLE_LOCK() uint32 { + return volatile.LoadUint32(&o.ROM_TABLE_LOCK.Reg) & 0x1 +} + +// HP_SYS.ROM_TABLE: Rom-Table register +func (o *HP_SYS_Type) SetROM_TABLE(value uint32) { + volatile.StoreUint32(&o.ROM_TABLE.Reg, value) +} +func (o *HP_SYS_Type) GetROM_TABLE() uint32 { + return volatile.LoadUint32(&o.ROM_TABLE.Reg) +} + +// HP_SYS.CORE_DEBUG_RUNSTALL_CONF: Core Debug runstall configure register +func (o *HP_SYS_Type) SetCORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE(value uint32) { + volatile.StoreUint32(&o.CORE_DEBUG_RUNSTALL_CONF.Reg, volatile.LoadUint32(&o.CORE_DEBUG_RUNSTALL_CONF.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE() uint32 { + return volatile.LoadUint32(&o.CORE_DEBUG_RUNSTALL_CONF.Reg) & 0x1 +} + +// HP_SYS.MEM_TEST_CONF: MEM_TEST configuration register +func (o *HP_SYS_Type) SetMEM_TEST_CONF_HP_MEM_WPULSE(value uint32) { + volatile.StoreUint32(&o.MEM_TEST_CONF.Reg, volatile.LoadUint32(&o.MEM_TEST_CONF.Reg)&^(0x7)|value) +} +func (o *HP_SYS_Type) GetMEM_TEST_CONF_HP_MEM_WPULSE() uint32 { + return volatile.LoadUint32(&o.MEM_TEST_CONF.Reg) & 0x7 +} +func (o *HP_SYS_Type) SetMEM_TEST_CONF_HP_MEM_WA(value uint32) { + volatile.StoreUint32(&o.MEM_TEST_CONF.Reg, volatile.LoadUint32(&o.MEM_TEST_CONF.Reg)&^(0x38)|value<<3) +} +func (o *HP_SYS_Type) GetMEM_TEST_CONF_HP_MEM_WA() uint32 { + return (volatile.LoadUint32(&o.MEM_TEST_CONF.Reg) & 0x38) >> 3 +} +func (o *HP_SYS_Type) SetMEM_TEST_CONF_HP_MEM_RA(value uint32) { + volatile.StoreUint32(&o.MEM_TEST_CONF.Reg, volatile.LoadUint32(&o.MEM_TEST_CONF.Reg)&^(0xc0)|value<<6) +} +func (o *HP_SYS_Type) GetMEM_TEST_CONF_HP_MEM_RA() uint32 { + return (volatile.LoadUint32(&o.MEM_TEST_CONF.Reg) & 0xc0) >> 6 +} + +// HP_SYS.RND_ECO: redcy eco register. +func (o *HP_SYS_Type) SetRND_ECO_REDCY_ENA(value uint32) { + volatile.StoreUint32(&o.RND_ECO.Reg, volatile.LoadUint32(&o.RND_ECO.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetRND_ECO_REDCY_ENA() uint32 { + return volatile.LoadUint32(&o.RND_ECO.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetRND_ECO_REDCY_RESULT(value uint32) { + volatile.StoreUint32(&o.RND_ECO.Reg, volatile.LoadUint32(&o.RND_ECO.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetRND_ECO_REDCY_RESULT() uint32 { + return (volatile.LoadUint32(&o.RND_ECO.Reg) & 0x2) >> 1 +} + +// HP_SYS.RND_ECO_LOW: redcy eco low register. +func (o *HP_SYS_Type) SetRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value) +} +func (o *HP_SYS_Type) GetRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RND_ECO_LOW.Reg) +} + +// HP_SYS.RND_ECO_HIGH: redcy eco high register. +func (o *HP_SYS_Type) SetRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value) +} +func (o *HP_SYS_Type) GetRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg) +} + +// HP_SYS.CLOCK_GATE: HP-SYSTEM clock gating configure register +func (o *HP_SYS_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// HP_SYS.DATE: Date register. +func (o *HP_SYS_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *HP_SYS_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// I2C (Inter-Integrated Circuit) Controller 0 +type I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + FILTER_CFG volatile.Register32 // 0x50 + CLK_CONF volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + SCL_ST_TIME_OUT volatile.Register32 // 0x78 + SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C + SCL_SP_CONF volatile.Register32 // 0x80 + SCL_STRETCH_CONF volatile.Register32 // 0x84 + _ [112]byte + DATE volatile.Register32 // 0xF8 + _ [4]byte + TXFIFO_START_ADDR volatile.Register32 // 0x100 + _ [124]byte + RXFIFO_START_ADDR volatile.Register32 // 0x180 +} + +// I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL Clock +func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff +} + +// I2C.CTR: Transmission setting +func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetCTR_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetCTR_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetCTR_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetCTR_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetCTR_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetCTR_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetCTR_CONF_UPGATE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetCTR_CONF_UPGATE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetCTR_SLV_TX_AUTO_START_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetCTR_SLV_TX_AUTO_START_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetCTR_ADDR_10BIT_RW_CHECK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetCTR_ADDR_10BIT_RW_CHECK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetCTR_ADDR_BROADCASTING_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetCTR_ADDR_BROADCASTING_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4000) >> 14 +} + +// I2C.SR: Describe I2C work status. +func (o *I2C_Type) SetSR_RESP_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSR_RESP_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *I2C_Type) SetSR_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetSR_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetSR_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetSR_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetSR_STRETCH_CAUSE(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xc000)|value<<14) +} +func (o *I2C_Type) GetSR_STRETCH_CAUSE() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xc000) >> 14 +} +func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xfc0000) >> 18 +} +func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// I2C.TO: Setting time out control for receiving data. +func (o *I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetTO_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0x1f +} +func (o *I2C_Type) SetTO_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetTO_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5 +} + +// I2C.SLAVE_ADDR: Local slave address setting +func (o *I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// I2C.FIFO_ST: FIFO status register. +func (o *I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 { + return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x7c00)|value<<10) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x7c00) >> 10 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf8000)|value<<15) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf8000) >> 15 +} +func (o *I2C_Type) SetFIFO_ST_SLAVE_RW_POINT(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3fc00000)|value<<22) +} +func (o *I2C_Type) GetFIFO_ST_SLAVE_RW_POINT() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3fc00000) >> 22 +} + +// I2C.FIFO_CONF: FIFO configuration register. +func (o *I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_ADDR_CFG_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_ADDR_CFG_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14 +} + +// I2C.DATA: Rx FIFO read data. +func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// I2C.INT_RAW: Raw interrupt status +func (o *I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_STRETCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_STRETCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_RAW_GENERAL_CALL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_RAW_GENERAL_CALL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} + +// I2C.INT_CLR: Interrupt clear bits +func (o *I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_STRETCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_STRETCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_CLR_GENERAL_CALL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_CLR_GENERAL_CALL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} + +// I2C.INT_ENA: Interrupt enable bits +func (o *I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_STRETCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_STRETCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_ENA_GENERAL_CALL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_ENA_GENERAL_CALL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} + +// I2C.INT_STATUS: Status of captured I2C communication events +func (o *I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_STRETCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_STRETCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_STATUS_GENERAL_CALL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_STATUS_GENERAL_CALL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40000) >> 18 +} + +// I2C.SDA_HOLD: Configures the hold time after a negative SCL edge. +func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff +} + +// I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge. +func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff +} + +// I2C.SCL_HIGH_PERIOD: Configures the high level width of SCL +func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff +} +func (o *I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9 +} + +// I2C.SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition +func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA +func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff +} + +// I2C.FILTER_CFG: SCL and SDA filter configuration register +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4 +} +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9 +} + +// I2C.CLK_CONF: I2C CLK configuration register +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} + +// I2C.COMD0: I2C command register %s +func (o *I2C_Type) SetCOMD0_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD0_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD0_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD0_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD1: I2C command register %s +func (o *I2C_Type) SetCOMD1_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD1_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD1_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD1_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD2: I2C command register %s +func (o *I2C_Type) SetCOMD2_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD2_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD2_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD2_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD3: I2C command register %s +func (o *I2C_Type) SetCOMD3_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD3_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD3_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD3_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD4: I2C command register %s +func (o *I2C_Type) SetCOMD4_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD4_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD4_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD4_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD5: I2C command register %s +func (o *I2C_Type) SetCOMD5_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD5_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD5_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD5_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD6: I2C command register %s +func (o *I2C_Type) SetCOMD6_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD6_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD6_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD6_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD7: I2C command register %s +func (o *I2C_Type) SetCOMD7_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD7_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD7_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD7_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// I2C.SCL_ST_TIME_OUT: SCL status time out register +func (o *I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register +func (o *I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_SP_CONF: Power configuration register +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// I2C.SCL_STRETCH_CONF: Set SCL stretch of I2C slave +func (o *I2C_Type) SetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM() uint32 { + return volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x3ff +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x2000) >> 13 +} + +// I2C.DATE: Version register +func (o *I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2C.TXFIFO_START_ADDR: I2C TXFIFO base address register +func (o *I2C_Type) SetTXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetTXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg) +} + +// I2C.RXFIFO_START_ADDR: I2C RXFIFO base address register +func (o *I2C_Type) SetRXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetRXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg) +} + +// I2S (Inter-IC Sound) Controller 0 +type I2S_Type struct { + _ [12]byte + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + _ [4]byte + RX_CONF volatile.Register32 // 0x20 + TX_CONF volatile.Register32 // 0x24 + RX_CONF1 volatile.Register32 // 0x28 + TX_CONF1 volatile.Register32 // 0x2C + RX_CLKM_CONF volatile.Register32 // 0x30 + TX_CLKM_CONF volatile.Register32 // 0x34 + RX_CLKM_DIV_CONF volatile.Register32 // 0x38 + TX_CLKM_DIV_CONF volatile.Register32 // 0x3C + TX_PCM2PDM_CONF volatile.Register32 // 0x40 + TX_PCM2PDM_CONF1 volatile.Register32 // 0x44 + _ [8]byte + RX_TDM_CTRL volatile.Register32 // 0x50 + TX_TDM_CTRL volatile.Register32 // 0x54 + RX_TIMING volatile.Register32 // 0x58 + TX_TIMING volatile.Register32 // 0x5C + LC_HUNG_CONF volatile.Register32 // 0x60 + RXEOF_NUM volatile.Register32 // 0x64 + CONF_SIGLE_DATA volatile.Register32 // 0x68 + STATE volatile.Register32 // 0x6C + ETM_CONF volatile.Register32 // 0x70 + _ [12]byte + DATE volatile.Register32 // 0x80 +} + +// I2S.INT_RAW: I2S interrupt raw register, valid in level. +func (o *I2S_Type) SetINT_RAW_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_RAW_RX_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// I2S.INT_ST: I2S interrupt status register. +func (o *I2S_Type) SetINT_ST_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ST_RX_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// I2S.INT_ENA: I2S interrupt enable register. +func (o *I2S_Type) SetINT_ENA_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ENA_RX_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// I2S.INT_CLR: I2S interrupt clear register. +func (o *I2S_Type) SetINT_CLR_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_CLR_RX_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// I2S.RX_CONF: I2S RX configure register +func (o *I2S_Type) SetRX_CONF_RX_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_CONF_RX_RESET() uint32 { + return volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_CONF_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_CONF_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_CONF_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_CONF_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_CONF_RX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_CONF_RX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetRX_CONF_RX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_CONF_RX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_CONF_RX_UPDATE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_CONF_RX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_CONF_RX_STOP_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *I2S_Type) GetRX_CONF_RX_STOP_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x6000) >> 13 +} +func (o *I2S_Type) SetRX_CONF_RX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_CONF_RX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_CONF_RX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetRX_CONF_RX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetRX_CONF_RX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetRX_CONF_RX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetRX_CONF_RX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetRX_CONF_RX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetRX_CONF_RX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetRX_CONF_RX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetRX_CONF_RX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetRX_CONF_RX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100000) >> 20 +} + +// I2S.TX_CONF: I2S TX configure register +func (o *I2S_Type) SetTX_CONF_TX_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_CONF_TX_RESET() uint32 { + return volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_CONF_TX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_CONF_TX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_CONF_TX_START(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_CONF_TX_START() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_CONF_TX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_CONF_TX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_EQUAL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_EQUAL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_CONF_TX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_CONF_TX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_CONF_TX_UPDATE(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_CONF_TX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_CONF_TX_STOP_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_CONF_TX_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_CONF_TX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_CONF_TX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_CONF_TX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetTX_CONF_TX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetTX_CONF_TX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetTX_CONF_TX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetTX_CONF_TX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetTX_CONF_TX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetTX_CONF_TX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetTX_CONF_TX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetTX_CONF_TX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_CONF_TX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x7000000)|value<<24) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x7000000) >> 24 +} +func (o *I2S_Type) SetTX_CONF_SIG_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetTX_CONF_SIG_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.RX_CONF1: I2S RX configure register 1 +func (o *I2S_Type) SetRX_CONF1_RX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7f)|value) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7f +} +func (o *I2S_Type) SetRX_CONF1_RX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *I2S_Type) GetRX_CONF1_RX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *I2S_Type) SetRX_CONF1_RX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x3e000)|value<<13) +} +func (o *I2S_Type) GetRX_CONF1_RX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x3e000) >> 13 +} +func (o *I2S_Type) SetRX_CONF1_RX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S_Type) GetRX_CONF1_RX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0xfc0000) >> 18 +} +func (o *I2S_Type) SetRX_CONF1_RX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f000000)|value<<24) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f000000) >> 24 +} +func (o *I2S_Type) SetRX_CONF1_RX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetRX_CONF1_RX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x20000000) >> 29 +} + +// I2S.TX_CONF1: I2S TX configure register 1 +func (o *I2S_Type) SetTX_CONF1_TX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7f)|value) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7f +} +func (o *I2S_Type) SetTX_CONF1_TX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *I2S_Type) GetTX_CONF1_TX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *I2S_Type) SetTX_CONF1_TX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x3e000)|value<<13) +} +func (o *I2S_Type) GetTX_CONF1_TX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x3e000) >> 13 +} +func (o *I2S_Type) SetTX_CONF1_TX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S_Type) GetTX_CONF1_TX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0xfc0000) >> 18 +} +func (o *I2S_Type) SetTX_CONF1_TX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1f000000)|value<<24) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1f000000) >> 24 +} +func (o *I2S_Type) SetTX_CONF1_TX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetTX_CONF1_TX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x20000000) >> 29 +} +func (o *I2S_Type) SetTX_CONF1_TX_BCK_NO_DLY(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetTX_CONF1_TX_BCK_NO_DLY() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x40000000) >> 30 +} + +// I2S.RX_CLKM_CONF: I2S RX clock configure register +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S_Type) SetRX_CLKM_CONF_MCLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetRX_CLKM_CONF_MCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S.TX_CLKM_CONF: I2S TX clock configure register +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S_Type) SetTX_CLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetTX_CLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S.RX_CLKM_DIV_CONF: I2S RX module clock divider configure register +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.TX_CLKM_DIV_CONF: I2S TX module clock divider configure register +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1e)|value<<1) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1e) >> 1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1fe0)|value<<5) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1fe0) >> 5 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x6000) >> 13 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x18000)|value<<15) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x18000) >> 15 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x60000)|value<<17) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x60000) >> 17 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x180000)|value<<19) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x180000) >> 19 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x400000) >> 22 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x800000) >> 23 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1000000) >> 24 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x2000000) >> 25 +} + +// I2S.TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FP(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3ff)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FP() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3ff +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FS() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x700000)|value<<20) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x700000) >> 20 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3800000) >> 23 +} + +// I2S.RX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} + +// I2S.TX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100000) >> 20 +} + +// I2S.RX_TIMING: I2S RX timing control register +func (o *I2S_Type) SetRX_TIMING_RX_SD_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD_IN_DM() uint32 { + return volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.TX_TIMING: I2S TX timing control register +func (o *I2S_Type) SetTX_TIMING_TX_SD_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD_OUT_DM() uint32 { + return volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetTX_TIMING_TX_SD1_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD1_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.LC_HUNG_CONF: I2S HUNG configure register. +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11 +} + +// I2S.RXEOF_NUM: I2S RX data number control register. +func (o *I2S_Type) SetRXEOF_NUM_RX_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.RXEOF_NUM.Reg, volatile.LoadUint32(&o.RXEOF_NUM.Reg)&^(0xfff)|value) +} +func (o *I2S_Type) GetRXEOF_NUM_RX_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.RXEOF_NUM.Reg) & 0xfff +} + +// I2S.CONF_SIGLE_DATA: I2S signal data register +func (o *I2S_Type) SetCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value) +} +func (o *I2S_Type) GetCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg) +} + +// I2S.STATE: I2S TX status register +func (o *I2S_Type) SetSTATE_TX_IDLE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetSTATE_TX_IDLE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x1 +} + +// I2S.ETM_CONF: I2S ETM configure register +func (o *I2S_Type) SetETM_CONF_ETM_TX_SEND_WORD_NUM(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2S_Type) GetETM_CONF_ETM_TX_SEND_WORD_NUM() uint32 { + return volatile.LoadUint32(&o.ETM_CONF.Reg) & 0x3ff +} +func (o *I2S_Type) SetETM_CONF_ETM_RX_RECEIVE_WORD_NUM(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *I2S_Type) GetETM_CONF_ETM_RX_RECEIVE_WORD_NUM() uint32 { + return (volatile.LoadUint32(&o.ETM_CONF.Reg) & 0xffc00) >> 10 +} + +// I2S.DATE: Version control register +func (o *I2S_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *I2S_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Interrupt Controller (Core 0) +type INTMTX_CORE0_Type struct { + WIFI_MAC_INTR_MAP volatile.Register32 // 0x0 + WIFI_MAC_NMI_MAP volatile.Register32 // 0x4 + WIFI_PWR_INTR_MAP volatile.Register32 // 0x8 + WIFI_BB_INTR_MAP volatile.Register32 // 0xC + BT_MAC_INTR_MAP volatile.Register32 // 0x10 + BT_BB_INTR_MAP volatile.Register32 // 0x14 + BT_BB_NMI_MAP volatile.Register32 // 0x18 + LP_TIMER_INTR_MAP volatile.Register32 // 0x1C + COEX_INTR_MAP volatile.Register32 // 0x20 + BLE_TIMER_INTR_MAP volatile.Register32 // 0x24 + BLE_SEC_INTR_MAP volatile.Register32 // 0x28 + I2C_MST_INTR_MAP volatile.Register32 // 0x2C + ZB_MAC_INTR_MAP volatile.Register32 // 0x30 + PMU_INTR_MAP volatile.Register32 // 0x34 + EFUSE_INTR_MAP volatile.Register32 // 0x38 + LP_RTC_TIMER_INTR_MAP volatile.Register32 // 0x3C + LP_UART_INTR_MAP volatile.Register32 // 0x40 + LP_I2C_INTR_MAP volatile.Register32 // 0x44 + LP_WDT_INTR_MAP volatile.Register32 // 0x48 + LP_PERI_TIMEOUT_INTR_MAP volatile.Register32 // 0x4C + LP_APM_M0_INTR_MAP volatile.Register32 // 0x50 + LP_APM_M1_INTR_MAP volatile.Register32 // 0x54 + CPU_INTR_FROM_CPU_0_MAP volatile.Register32 // 0x58 + CPU_INTR_FROM_CPU_1_MAP volatile.Register32 // 0x5C + CPU_INTR_FROM_CPU_2_MAP volatile.Register32 // 0x60 + CPU_INTR_FROM_CPU_3_MAP volatile.Register32 // 0x64 + ASSIST_DEBUG_INTR_MAP volatile.Register32 // 0x68 + TRACE_INTR_MAP volatile.Register32 // 0x6C + CACHE_INTR_MAP volatile.Register32 // 0x70 + CPU_PERI_TIMEOUT_INTR_MAP volatile.Register32 // 0x74 + GPIO_INTERRUPT_PRO_MAP volatile.Register32 // 0x78 + GPIO_INTERRUPT_PRO_NMI_MAP volatile.Register32 // 0x7C + PAU_INTR_MAP volatile.Register32 // 0x80 + HP_PERI_TIMEOUT_INTR_MAP volatile.Register32 // 0x84 + MODEM_PERI_TIMEOUT_INTR_MAP volatile.Register32 // 0x88 + HP_APM_M0_INTR_MAP volatile.Register32 // 0x8C + HP_APM_M1_INTR_MAP volatile.Register32 // 0x90 + HP_APM_M2_INTR_MAP volatile.Register32 // 0x94 + HP_APM_M3_INTR_MAP volatile.Register32 // 0x98 + LP_APM0_INTR_MAP volatile.Register32 // 0x9C + MSPI_INTR_MAP volatile.Register32 // 0xA0 + I2S1_INTR_MAP volatile.Register32 // 0xA4 + UHCI0_INTR_MAP volatile.Register32 // 0xA8 + UART0_INTR_MAP volatile.Register32 // 0xAC + UART1_INTR_MAP volatile.Register32 // 0xB0 + LEDC_INTR_MAP volatile.Register32 // 0xB4 + CAN0_INTR_MAP volatile.Register32 // 0xB8 + CAN1_INTR_MAP volatile.Register32 // 0xBC + USB_INTR_MAP volatile.Register32 // 0xC0 + RMT_INTR_MAP volatile.Register32 // 0xC4 + I2C_EXT0_INTR_MAP volatile.Register32 // 0xC8 + TG0_T0_INTR_MAP volatile.Register32 // 0xCC + TG0_T1_INTR_MAP volatile.Register32 // 0xD0 + TG0_WDT_INTR_MAP volatile.Register32 // 0xD4 + TG1_T0_INTR_MAP volatile.Register32 // 0xD8 + TG1_T1_INTR_MAP volatile.Register32 // 0xDC + TG1_WDT_INTR_MAP volatile.Register32 // 0xE0 + SYSTIMER_TARGET0_INTR_MAP volatile.Register32 // 0xE4 + SYSTIMER_TARGET1_INTR_MAP volatile.Register32 // 0xE8 + SYSTIMER_TARGET2_INTR_MAP volatile.Register32 // 0xEC + APB_ADC_INTR_MAP volatile.Register32 // 0xF0 + PWM_INTR_MAP volatile.Register32 // 0xF4 + PCNT_INTR_MAP volatile.Register32 // 0xF8 + PARL_IO_INTR_MAP volatile.Register32 // 0xFC + SLC0_INTR_MAP volatile.Register32 // 0x100 + SLC1_INTR_MAP volatile.Register32 // 0x104 + DMA_IN_CH0_INTR_MAP volatile.Register32 // 0x108 + DMA_IN_CH1_INTR_MAP volatile.Register32 // 0x10C + DMA_IN_CH2_INTR_MAP volatile.Register32 // 0x110 + DMA_OUT_CH0_INTR_MAP volatile.Register32 // 0x114 + DMA_OUT_CH1_INTR_MAP volatile.Register32 // 0x118 + DMA_OUT_CH2_INTR_MAP volatile.Register32 // 0x11C + GPSPI2_INTR_MAP volatile.Register32 // 0x120 + AES_INTR_MAP volatile.Register32 // 0x124 + SHA_INTR_MAP volatile.Register32 // 0x128 + RSA_INTR_MAP volatile.Register32 // 0x12C + ECC_INTR_MAP volatile.Register32 // 0x130 + INTR_STATUS_REG_0 volatile.Register32 // 0x134 + INTR_STATUS_REG_1 volatile.Register32 // 0x138 + INT_STATUS_REG_2 volatile.Register32 // 0x13C + CLOCK_GATE volatile.Register32 // 0x140 + _ [1720]byte + INTERRUPT_REG_DATE volatile.Register32 // 0x7FC +} + +// INTMTX_CORE0.WIFI_MAC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetWIFI_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.WIFI_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.WIFI_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetWIFI_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.WIFI_MAC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.WIFI_MAC_NMI_MAP: register description +func (o *INTMTX_CORE0_Type) SetWIFI_MAC_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.WIFI_MAC_NMI_MAP.Reg, volatile.LoadUint32(&o.WIFI_MAC_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetWIFI_MAC_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.WIFI_MAC_NMI_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.WIFI_PWR_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetWIFI_PWR_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.WIFI_PWR_INTR_MAP.Reg, volatile.LoadUint32(&o.WIFI_PWR_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetWIFI_PWR_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.WIFI_PWR_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.WIFI_BB_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetWIFI_BB_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_INTR_MAP.Reg, volatile.LoadUint32(&o.WIFI_BB_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetWIFI_BB_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BT_MAC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetBT_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BT_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.BT_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBT_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BT_MAC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BT_BB_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetBT_BB_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_INTR_MAP.Reg, volatile.LoadUint32(&o.BT_BB_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBT_BB_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BT_BB_NMI_MAP: register description +func (o *INTMTX_CORE0_Type) SetBT_BB_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_NMI_MAP.Reg, volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBT_BB_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_TIMER_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_TIMER_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_TIMER_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TIMER_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.COEX_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetCOEX_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.COEX_INTR_MAP.Reg, volatile.LoadUint32(&o.COEX_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCOEX_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.COEX_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BLE_TIMER_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetBLE_TIMER_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BLE_TIMER_INTR_MAP.Reg, volatile.LoadUint32(&o.BLE_TIMER_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBLE_TIMER_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BLE_TIMER_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BLE_SEC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetBLE_SEC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BLE_SEC_INTR_MAP.Reg, volatile.LoadUint32(&o.BLE_SEC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBLE_SEC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BLE_SEC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.I2C_MST_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetI2C_MST_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_MST_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_MST_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetI2C_MST_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_MST_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.ZB_MAC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetZB_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ZB_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.ZB_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetZB_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ZB_MAC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PMU_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPMU_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PMU_INTR_MAP.Reg, volatile.LoadUint32(&o.PMU_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPMU_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PMU_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.EFUSE_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetEFUSE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.EFUSE_INTR_MAP.Reg, volatile.LoadUint32(&o.EFUSE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetEFUSE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.EFUSE_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_RTC_TIMER_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_RTC_TIMER_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_RTC_TIMER_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_RTC_TIMER_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_RTC_TIMER_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_RTC_TIMER_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_UART_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_UART_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_UART_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_UART_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_UART_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_UART_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_I2C_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_I2C_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_I2C_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_I2C_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_I2C_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_I2C_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_WDT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_WDT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_WDT_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_WDT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_WDT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_WDT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_PERI_TIMEOUT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_PERI_TIMEOUT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_PERI_TIMEOUT_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_PERI_TIMEOUT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_PERI_TIMEOUT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_PERI_TIMEOUT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_APM_M0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_APM_M0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_APM_M0_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_APM_M0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_APM_M0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_APM_M0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_APM_M1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_APM_M1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_APM_M1_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_APM_M1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_APM_M1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_APM_M1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_INTR_FROM_CPU_0_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_INTR_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_INTR_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_INTR_FROM_CPU_1_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_INTR_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_INTR_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_INTR_FROM_CPU_2_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_INTR_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_INTR_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_INTR_FROM_CPU_3_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_INTR_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_INTR_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.ASSIST_DEBUG_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetASSIST_DEBUG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetASSIST_DEBUG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TRACE_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTRACE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TRACE_INTR_MAP.Reg, volatile.LoadUint32(&o.TRACE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTRACE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TRACE_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CACHE_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetCACHE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_INTR_MAP.Reg, volatile.LoadUint32(&o.CACHE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCACHE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_PERI_TIMEOUT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_PERI_TIMEOUT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_INTR_MAP.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_PERI_TIMEOUT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.GPIO_INTERRUPT_PRO_MAP: register description +func (o *INTMTX_CORE0_Type) SetGPIO_INTERRUPT_PRO_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetGPIO_INTERRUPT_PRO_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.GPIO_INTERRUPT_PRO_NMI_MAP: register description +func (o *INTMTX_CORE0_Type) SetGPIO_INTERRUPT_PRO_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetGPIO_INTERRUPT_PRO_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PAU_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPAU_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PAU_INTR_MAP.Reg, volatile.LoadUint32(&o.PAU_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPAU_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PAU_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_PERI_TIMEOUT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_PERI_TIMEOUT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_PERI_TIMEOUT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_PERI_TIMEOUT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.MODEM_PERI_TIMEOUT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetMODEM_PERI_TIMEOUT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.MODEM_PERI_TIMEOUT_INTR_MAP.Reg, volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetMODEM_PERI_TIMEOUT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.MODEM_PERI_TIMEOUT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_APM_M0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_APM_M0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_APM_M0_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_APM_M0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_APM_M0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_APM_M0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_APM_M1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_APM_M1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_APM_M1_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_APM_M1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_APM_M1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_APM_M1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_APM_M2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_APM_M2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_APM_M2_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_APM_M2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_APM_M2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_APM_M2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_APM_M3_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_APM_M3_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_APM_M3_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_APM_M3_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_APM_M3_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_APM_M3_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_APM0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_APM0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_APM0_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_APM0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_APM0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_APM0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.MSPI_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetMSPI_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.MSPI_INTR_MAP.Reg, volatile.LoadUint32(&o.MSPI_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetMSPI_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.MSPI_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.I2S1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetI2S1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2S1_INTR_MAP.Reg, volatile.LoadUint32(&o.I2S1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetI2S1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2S1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.UHCI0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetUHCI0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UHCI0_INTR_MAP.Reg, volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetUHCI0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.UART0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetUART0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART0_INTR_MAP.Reg, volatile.LoadUint32(&o.UART0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetUART0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.UART1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetUART1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART1_INTR_MAP.Reg, volatile.LoadUint32(&o.UART1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetUART1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LEDC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLEDC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LEDC_INTR_MAP.Reg, volatile.LoadUint32(&o.LEDC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLEDC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LEDC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CAN0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetCAN0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CAN0_INTR_MAP.Reg, volatile.LoadUint32(&o.CAN0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCAN0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CAN0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CAN1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetCAN1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CAN1_INTR_MAP.Reg, volatile.LoadUint32(&o.CAN1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCAN1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CAN1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.USB_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetUSB_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.USB_INTR_MAP.Reg, volatile.LoadUint32(&o.USB_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetUSB_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.USB_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.RMT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetRMT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RMT_INTR_MAP.Reg, volatile.LoadUint32(&o.RMT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetRMT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RMT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.I2C_EXT0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetI2C_EXT0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_EXT0_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetI2C_EXT0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG0_T0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG0_T0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG0_T0_INTR_MAP.Reg, volatile.LoadUint32(&o.TG0_T0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG0_T0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG0_T0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG0_T1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG0_T1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG0_T1_INTR_MAP.Reg, volatile.LoadUint32(&o.TG0_T1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG0_T1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG0_T1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG0_WDT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG0_WDT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG0_WDT_INTR_MAP.Reg, volatile.LoadUint32(&o.TG0_WDT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG0_WDT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG0_WDT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG1_T0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG1_T0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_T0_INTR_MAP.Reg, volatile.LoadUint32(&o.TG1_T0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG1_T0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_T0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG1_T1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG1_T1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_T1_INTR_MAP.Reg, volatile.LoadUint32(&o.TG1_T1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG1_T1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_T1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG1_WDT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG1_WDT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_WDT_INTR_MAP.Reg, volatile.LoadUint32(&o.TG1_WDT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG1_WDT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_WDT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SYSTIMER_TARGET0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSYSTIMER_TARGET0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET0_INTR_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSYSTIMER_TARGET0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SYSTIMER_TARGET1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSYSTIMER_TARGET1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET1_INTR_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSYSTIMER_TARGET1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SYSTIMER_TARGET2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSYSTIMER_TARGET2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET2_INTR_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSYSTIMER_TARGET2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.APB_ADC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetAPB_ADC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APB_ADC_INTR_MAP.Reg, volatile.LoadUint32(&o.APB_ADC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetAPB_ADC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APB_ADC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PWM_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPWM_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPWM_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PCNT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPCNT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PCNT_INTR_MAP.Reg, volatile.LoadUint32(&o.PCNT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPCNT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PCNT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PARL_IO_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPARL_IO_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PARL_IO_INTR_MAP.Reg, volatile.LoadUint32(&o.PARL_IO_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPARL_IO_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PARL_IO_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SLC0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSLC0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SLC0_INTR_MAP.Reg, volatile.LoadUint32(&o.SLC0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSLC0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SLC0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SLC1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSLC1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SLC1_INTR_MAP.Reg, volatile.LoadUint32(&o.SLC1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSLC1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SLC1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_IN_CH0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_IN_CH0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH0_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_IN_CH0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_IN_CH1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_IN_CH1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH1_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_IN_CH1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_IN_CH2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_IN_CH2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH2_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_IN_CH2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_OUT_CH0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_OUT_CH0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH0_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_OUT_CH0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_OUT_CH1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_OUT_CH1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH1_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_OUT_CH1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_OUT_CH2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_OUT_CH2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH2_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_OUT_CH2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.GPSPI2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetGPSPI2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.GPSPI2_INTR_MAP.Reg, volatile.LoadUint32(&o.GPSPI2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetGPSPI2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.GPSPI2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.AES_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetAES_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.AES_INTR_MAP.Reg, volatile.LoadUint32(&o.AES_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetAES_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.AES_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SHA_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSHA_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SHA_INTR_MAP.Reg, volatile.LoadUint32(&o.SHA_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSHA_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SHA_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.RSA_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetRSA_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RSA_INTR_MAP.Reg, volatile.LoadUint32(&o.RSA_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetRSA_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RSA_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.ECC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetECC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ECC_INTR_MAP.Reg, volatile.LoadUint32(&o.ECC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetECC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ECC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.INTR_STATUS_REG_0: register description +func (o *INTMTX_CORE0_Type) SetINTR_STATUS_REG_0(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_0.Reg, value) +} +func (o *INTMTX_CORE0_Type) GetINTR_STATUS_REG_0() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_0.Reg) +} + +// INTMTX_CORE0.INTR_STATUS_REG_1: register description +func (o *INTMTX_CORE0_Type) SetINTR_STATUS_REG_1(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_1.Reg, value) +} +func (o *INTMTX_CORE0_Type) GetINTR_STATUS_REG_1() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_1.Reg) +} + +// INTMTX_CORE0.INT_STATUS_REG_2: register description +func (o *INTMTX_CORE0_Type) SetINT_STATUS_REG_2(value uint32) { + volatile.StoreUint32(&o.INT_STATUS_REG_2.Reg, value) +} +func (o *INTMTX_CORE0_Type) GetINT_STATUS_REG_2() uint32 { + return volatile.LoadUint32(&o.INT_STATUS_REG_2.Reg) +} + +// INTMTX_CORE0.CLOCK_GATE: register description +func (o *INTMTX_CORE0_Type) SetCLOCK_GATE_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *INTMTX_CORE0_Type) GetCLOCK_GATE_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// INTMTX_CORE0.INTERRUPT_REG_DATE: register description +func (o *INTMTX_CORE0_Type) SetINTERRUPT_REG_DATE(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_REG_DATE.Reg, volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *INTMTX_CORE0_Type) GetINTERRUPT_REG_DATE() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg) & 0xfffffff +} + +// INTPRI Peripheral +type INTPRI_Type struct { + CPU_INT_ENABLE volatile.Register32 // 0x0 + CPU_INT_TYPE volatile.Register32 // 0x4 + CPU_INT_EIP_STATUS volatile.Register32 // 0x8 + CPU_INT_PRI_0 volatile.Register32 // 0xC + CPU_INT_PRI_1 volatile.Register32 // 0x10 + CPU_INT_PRI_2 volatile.Register32 // 0x14 + CPU_INT_PRI_3 volatile.Register32 // 0x18 + CPU_INT_PRI_4 volatile.Register32 // 0x1C + CPU_INT_PRI_5 volatile.Register32 // 0x20 + CPU_INT_PRI_6 volatile.Register32 // 0x24 + CPU_INT_PRI_7 volatile.Register32 // 0x28 + CPU_INT_PRI_8 volatile.Register32 // 0x2C + CPU_INT_PRI_9 volatile.Register32 // 0x30 + CPU_INT_PRI_10 volatile.Register32 // 0x34 + CPU_INT_PRI_11 volatile.Register32 // 0x38 + CPU_INT_PRI_12 volatile.Register32 // 0x3C + CPU_INT_PRI_13 volatile.Register32 // 0x40 + CPU_INT_PRI_14 volatile.Register32 // 0x44 + CPU_INT_PRI_15 volatile.Register32 // 0x48 + CPU_INT_PRI_16 volatile.Register32 // 0x4C + CPU_INT_PRI_17 volatile.Register32 // 0x50 + CPU_INT_PRI_18 volatile.Register32 // 0x54 + CPU_INT_PRI_19 volatile.Register32 // 0x58 + CPU_INT_PRI_20 volatile.Register32 // 0x5C + CPU_INT_PRI_21 volatile.Register32 // 0x60 + CPU_INT_PRI_22 volatile.Register32 // 0x64 + CPU_INT_PRI_23 volatile.Register32 // 0x68 + CPU_INT_PRI_24 volatile.Register32 // 0x6C + CPU_INT_PRI_25 volatile.Register32 // 0x70 + CPU_INT_PRI_26 volatile.Register32 // 0x74 + CPU_INT_PRI_27 volatile.Register32 // 0x78 + CPU_INT_PRI_28 volatile.Register32 // 0x7C + CPU_INT_PRI_29 volatile.Register32 // 0x80 + CPU_INT_PRI_30 volatile.Register32 // 0x84 + CPU_INT_PRI_31 volatile.Register32 // 0x88 + CPU_INT_THRESH volatile.Register32 // 0x8C + CPU_INTR_FROM_CPU_0 volatile.Register32 // 0x90 + CPU_INTR_FROM_CPU_1 volatile.Register32 // 0x94 + CPU_INTR_FROM_CPU_2 volatile.Register32 // 0x98 + CPU_INTR_FROM_CPU_3 volatile.Register32 // 0x9C + DATE volatile.Register32 // 0xA0 + CLOCK_GATE volatile.Register32 // 0xA4 + CPU_INT_CLEAR volatile.Register32 // 0xA8 + RND_ECO volatile.Register32 // 0xAC + RND_ECO_LOW volatile.Register32 // 0xB0 + _ [840]byte + RND_ECO_HIGH volatile.Register32 // 0x3FC +} + +// INTPRI.CPU_INT_ENABLE: register description +func (o *INTPRI_Type) SetCPU_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.CPU_INT_ENABLE.Reg, value) +} +func (o *INTPRI_Type) GetCPU_INT_ENABLE() uint32 { + return volatile.LoadUint32(&o.CPU_INT_ENABLE.Reg) +} + +// INTPRI.CPU_INT_TYPE: register description +func (o *INTPRI_Type) SetCPU_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CPU_INT_TYPE.Reg, value) +} +func (o *INTPRI_Type) GetCPU_INT_TYPE() uint32 { + return volatile.LoadUint32(&o.CPU_INT_TYPE.Reg) +} + +// INTPRI.CPU_INT_EIP_STATUS: register description +func (o *INTPRI_Type) SetCPU_INT_EIP_STATUS(value uint32) { + volatile.StoreUint32(&o.CPU_INT_EIP_STATUS.Reg, value) +} +func (o *INTPRI_Type) GetCPU_INT_EIP_STATUS() uint32 { + return volatile.LoadUint32(&o.CPU_INT_EIP_STATUS.Reg) +} + +// INTPRI.CPU_INT_PRI_0: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_0_CPU_PRI_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_0.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_0.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_0_CPU_PRI_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_0.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_1: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_1_CPU_PRI_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_1.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_1.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_1_CPU_PRI_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_1.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_2: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_2_CPU_PRI_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_2.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_2.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_2_CPU_PRI_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_2.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_3: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_3_CPU_PRI_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_3.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_3.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_3_CPU_PRI_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_3.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_4: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_4_CPU_PRI_4_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_4.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_4.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_4_CPU_PRI_4_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_4.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_5: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_5_CPU_PRI_5_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_5.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_5.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_5_CPU_PRI_5_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_5.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_6: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_6_CPU_PRI_6_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_6.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_6.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_6_CPU_PRI_6_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_6.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_7: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_7_CPU_PRI_7_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_7.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_7.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_7_CPU_PRI_7_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_7.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_8: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_8_CPU_PRI_8_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_8.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_8.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_8_CPU_PRI_8_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_8.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_9: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_9_CPU_PRI_9_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_9.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_9.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_9_CPU_PRI_9_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_9.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_10: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_10_CPU_PRI_10_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_10.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_10.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_10_CPU_PRI_10_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_10.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_11: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_11_CPU_PRI_11_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_11.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_11.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_11_CPU_PRI_11_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_11.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_12: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_12_CPU_PRI_12_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_12.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_12.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_12_CPU_PRI_12_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_12.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_13: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_13_CPU_PRI_13_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_13.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_13.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_13_CPU_PRI_13_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_13.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_14: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_14_CPU_PRI_14_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_14.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_14.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_14_CPU_PRI_14_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_14.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_15: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_15_CPU_PRI_15_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_15.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_15.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_15_CPU_PRI_15_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_15.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_16: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_16_CPU_PRI_16_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_16.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_16.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_16_CPU_PRI_16_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_16.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_17: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_17_CPU_PRI_17_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_17.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_17.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_17_CPU_PRI_17_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_17.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_18: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_18_CPU_PRI_18_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_18.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_18.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_18_CPU_PRI_18_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_18.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_19: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_19_CPU_PRI_19_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_19.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_19.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_19_CPU_PRI_19_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_19.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_20: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_20_CPU_PRI_20_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_20.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_20.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_20_CPU_PRI_20_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_20.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_21: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_21_CPU_PRI_21_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_21.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_21.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_21_CPU_PRI_21_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_21.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_22: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_22_CPU_PRI_22_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_22.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_22.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_22_CPU_PRI_22_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_22.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_23: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_23_CPU_PRI_23_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_23.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_23.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_23_CPU_PRI_23_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_23.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_24: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_24_CPU_PRI_24_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_24.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_24.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_24_CPU_PRI_24_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_24.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_25: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_25_CPU_PRI_25_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_25.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_25.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_25_CPU_PRI_25_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_25.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_26: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_26_CPU_PRI_26_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_26.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_26.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_26_CPU_PRI_26_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_26.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_27: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_27_CPU_PRI_27_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_27.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_27.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_27_CPU_PRI_27_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_27.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_28: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_28_CPU_PRI_28_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_28.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_28.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_28_CPU_PRI_28_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_28.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_29: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_29_CPU_PRI_29_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_29.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_29.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_29_CPU_PRI_29_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_29.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_30: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_30_CPU_PRI_30_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_30.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_30.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_30_CPU_PRI_30_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_30.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_31: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_31_CPU_PRI_31_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_31.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_31.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_31_CPU_PRI_31_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_31.Reg) & 0xf +} + +// INTPRI.CPU_INT_THRESH: register description +func (o *INTPRI_Type) SetCPU_INT_THRESH(value uint32) { + volatile.StoreUint32(&o.CPU_INT_THRESH.Reg, volatile.LoadUint32(&o.CPU_INT_THRESH.Reg)&^(0xff)|value) +} +func (o *INTPRI_Type) GetCPU_INT_THRESH() uint32 { + return volatile.LoadUint32(&o.CPU_INT_THRESH.Reg) & 0xff +} + +// INTPRI.CPU_INTR_FROM_CPU_0: register description +func (o *INTPRI_Type) SetCPU_INTR_FROM_CPU_0(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCPU_INTR_FROM_CPU_0() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg) & 0x1 +} + +// INTPRI.CPU_INTR_FROM_CPU_1: register description +func (o *INTPRI_Type) SetCPU_INTR_FROM_CPU_1(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCPU_INTR_FROM_CPU_1() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg) & 0x1 +} + +// INTPRI.CPU_INTR_FROM_CPU_2: register description +func (o *INTPRI_Type) SetCPU_INTR_FROM_CPU_2(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCPU_INTR_FROM_CPU_2() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg) & 0x1 +} + +// INTPRI.CPU_INTR_FROM_CPU_3: register description +func (o *INTPRI_Type) SetCPU_INTR_FROM_CPU_3(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCPU_INTR_FROM_CPU_3() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg) & 0x1 +} + +// INTPRI.DATE: register description +func (o *INTPRI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *INTPRI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// INTPRI.CLOCK_GATE: register description +func (o *INTPRI_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// INTPRI.CPU_INT_CLEAR: register description +func (o *INTPRI_Type) SetCPU_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.CPU_INT_CLEAR.Reg, value) +} +func (o *INTPRI_Type) GetCPU_INT_CLEAR() uint32 { + return volatile.LoadUint32(&o.CPU_INT_CLEAR.Reg) +} + +// INTPRI.RND_ECO: redcy eco register. +func (o *INTPRI_Type) SetRND_ECO_REDCY_ENA(value uint32) { + volatile.StoreUint32(&o.RND_ECO.Reg, volatile.LoadUint32(&o.RND_ECO.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetRND_ECO_REDCY_ENA() uint32 { + return volatile.LoadUint32(&o.RND_ECO.Reg) & 0x1 +} +func (o *INTPRI_Type) SetRND_ECO_REDCY_RESULT(value uint32) { + volatile.StoreUint32(&o.RND_ECO.Reg, volatile.LoadUint32(&o.RND_ECO.Reg)&^(0x2)|value<<1) +} +func (o *INTPRI_Type) GetRND_ECO_REDCY_RESULT() uint32 { + return (volatile.LoadUint32(&o.RND_ECO.Reg) & 0x2) >> 1 +} + +// INTPRI.RND_ECO_LOW: redcy eco low register. +func (o *INTPRI_Type) SetRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value) +} +func (o *INTPRI_Type) GetRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RND_ECO_LOW.Reg) +} + +// INTPRI.RND_ECO_HIGH: redcy eco high register. +func (o *INTPRI_Type) SetRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value) +} +func (o *INTPRI_Type) GetRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg) +} + +// Input/Output Multiplexer +type IO_MUX_Type struct { + PIN_CTRL volatile.Register32 // 0x0 + GPIO0 volatile.Register32 // 0x4 + GPIO1 volatile.Register32 // 0x8 + GPIO2 volatile.Register32 // 0xC + GPIO3 volatile.Register32 // 0x10 + GPIO4 volatile.Register32 // 0x14 + GPIO5 volatile.Register32 // 0x18 + GPIO6 volatile.Register32 // 0x1C + GPIO7 volatile.Register32 // 0x20 + GPIO8 volatile.Register32 // 0x24 + GPIO9 volatile.Register32 // 0x28 + GPIO10 volatile.Register32 // 0x2C + GPIO11 volatile.Register32 // 0x30 + GPIO12 volatile.Register32 // 0x34 + GPIO13 volatile.Register32 // 0x38 + GPIO14 volatile.Register32 // 0x3C + GPIO15 volatile.Register32 // 0x40 + GPIO16 volatile.Register32 // 0x44 + GPIO17 volatile.Register32 // 0x48 + GPIO18 volatile.Register32 // 0x4C + GPIO19 volatile.Register32 // 0x50 + GPIO20 volatile.Register32 // 0x54 + GPIO21 volatile.Register32 // 0x58 + GPIO22 volatile.Register32 // 0x5C + GPIO23 volatile.Register32 // 0x60 + GPIO24 volatile.Register32 // 0x64 + GPIO25 volatile.Register32 // 0x68 + GPIO26 volatile.Register32 // 0x6C + GPIO27 volatile.Register32 // 0x70 + GPIO28 volatile.Register32 // 0x74 + GPIO29 volatile.Register32 // 0x78 + GPIO30 volatile.Register32 // 0x7C + _ [60]byte + MODEM_DIAG_EN volatile.Register32 // 0xBC + _ [60]byte + DATE volatile.Register32 // 0xFC +} + +// IO_MUX.PIN_CTRL: Clock Output Configuration Register +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT1(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0x1f)|value) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT1() uint32 { + return volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0x1f +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT2(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0x3e0)|value<<5) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT2() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0x3e0) >> 5 +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT3(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0x7c00)|value<<10) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT3() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0x7c00) >> 10 +} + +// IO_MUX.GPIO0: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO1: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO2: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO3: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO4: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO5: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO6: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO7: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO8: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO8_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO8.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO8_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO8_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO9: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO9_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO9.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO9_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO9_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO10: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO10_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO10.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO10_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO10_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO11: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO11_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO11.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO11_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO11_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO12: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO12_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO12.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO12_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO12_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO13: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO13_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO13.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO13_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO13_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO14: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO14_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO14.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO14_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO14_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO15: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO15_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO15.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO15_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO15_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO15_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO15_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO16: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO16_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO16.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO16_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO16_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO16_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO16_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO17: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO17_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO17.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO17_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO17_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO17_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO17_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO18: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO18_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO18.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO18_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO18_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO18_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO18_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO19: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO19_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO19.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO19_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO19_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO20: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO20_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO20.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO20_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO20_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO21: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO21_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO21.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO21_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO21_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO22: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO22_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO22.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO22_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO22_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO22_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO22_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO23: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO23_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO23.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO23_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO23_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO23_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO23_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO24: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO24_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO24.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO24_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO24_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO24_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO24_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO25: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO25_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO25.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO25_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO25_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO25_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO25_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO26: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO26_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO26.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO26_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO26_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO26_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO26_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO27: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO27_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO27.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO27_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO27_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO27_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO27_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO28: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO28_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO28.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO28_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO28_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO28_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO28_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO29: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO29_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO29.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO29_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO29_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO29_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO29_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO30: IO MUX Configure Register for pad XTAL_32K_P +func (o *IO_MUX_Type) SetGPIO30_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO30.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO30_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO30_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO30_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO30_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8000) >> 15 +} + +// IO_MUX.MODEM_DIAG_EN: GPIO MATRIX Configure Register for modem diag +func (o *IO_MUX_Type) SetMODEM_DIAG_EN(value uint32) { + volatile.StoreUint32(&o.MODEM_DIAG_EN.Reg, value) +} +func (o *IO_MUX_Type) GetMODEM_DIAG_EN() uint32 { + return volatile.LoadUint32(&o.MODEM_DIAG_EN.Reg) +} + +// IO_MUX.DATE: IO MUX Version Control Register +func (o *IO_MUX_Type) SetDATE_REG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *IO_MUX_Type) GetDATE_REG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LED Control PWM (Pulse Width Modulation) +type LEDC_Type struct { + CH0_CONF0 volatile.Register32 // 0x0 + CH0_HPOINT volatile.Register32 // 0x4 + CH0_DUTY volatile.Register32 // 0x8 + CH0_CONF1 volatile.Register32 // 0xC + CH0_DUTY_R volatile.Register32 // 0x10 + CH1_CONF0 volatile.Register32 // 0x14 + CH1_HPOINT volatile.Register32 // 0x18 + CH1_DUTY volatile.Register32 // 0x1C + CH1_CONF1 volatile.Register32 // 0x20 + CH1_DUTY_R volatile.Register32 // 0x24 + CH2_CONF0 volatile.Register32 // 0x28 + CH2_HPOINT volatile.Register32 // 0x2C + CH2_DUTY volatile.Register32 // 0x30 + CH2_CONF1 volatile.Register32 // 0x34 + CH2_DUTY_R volatile.Register32 // 0x38 + CH3_CONF0 volatile.Register32 // 0x3C + CH3_HPOINT volatile.Register32 // 0x40 + CH3_DUTY volatile.Register32 // 0x44 + CH3_CONF1 volatile.Register32 // 0x48 + CH3_DUTY_R volatile.Register32 // 0x4C + CH4_CONF0 volatile.Register32 // 0x50 + CH4_HPOINT volatile.Register32 // 0x54 + CH4_DUTY volatile.Register32 // 0x58 + CH4_CONF1 volatile.Register32 // 0x5C + CH4_DUTY_R volatile.Register32 // 0x60 + CH5_CONF0 volatile.Register32 // 0x64 + CH5_HPOINT volatile.Register32 // 0x68 + CH5_DUTY volatile.Register32 // 0x6C + CH5_CONF1 volatile.Register32 // 0x70 + CH5_DUTY_R volatile.Register32 // 0x74 + _ [40]byte + TIMER0_CONF volatile.Register32 // 0xA0 + TIMER0_VALUE volatile.Register32 // 0xA4 + TIMER1_CONF volatile.Register32 // 0xA8 + TIMER1_VALUE volatile.Register32 // 0xAC + TIMER2_CONF volatile.Register32 // 0xB0 + TIMER2_VALUE volatile.Register32 // 0xB4 + TIMER3_CONF volatile.Register32 // 0xB8 + TIMER3_VALUE volatile.Register32 // 0xBC + INT_RAW volatile.Register32 // 0xC0 + INT_ST volatile.Register32 // 0xC4 + INT_ENA volatile.Register32 // 0xC8 + INT_CLR volatile.Register32 // 0xCC + _ [48]byte + CH0_GAMMA_WR volatile.Register32 // 0x100 + CH0_GAMMA_WR_ADDR volatile.Register32 // 0x104 + CH0_GAMMA_RD_ADDR volatile.Register32 // 0x108 + CH0_GAMMA_RD_DATA volatile.Register32 // 0x10C + CH1_GAMMA_WR volatile.Register32 // 0x110 + CH1_GAMMA_WR_ADDR volatile.Register32 // 0x114 + CH1_GAMMA_RD_ADDR volatile.Register32 // 0x118 + CH1_GAMMA_RD_DATA volatile.Register32 // 0x11C + CH2_GAMMA_WR volatile.Register32 // 0x120 + CH2_GAMMA_WR_ADDR volatile.Register32 // 0x124 + CH2_GAMMA_RD_ADDR volatile.Register32 // 0x128 + CH2_GAMMA_RD_DATA volatile.Register32 // 0x12C + CH3_GAMMA_WR volatile.Register32 // 0x130 + CH3_GAMMA_WR_ADDR volatile.Register32 // 0x134 + CH3_GAMMA_RD_ADDR volatile.Register32 // 0x138 + CH3_GAMMA_RD_DATA volatile.Register32 // 0x13C + CH4_GAMMA_WR volatile.Register32 // 0x140 + CH4_GAMMA_WR_ADDR volatile.Register32 // 0x144 + CH4_GAMMA_RD_ADDR volatile.Register32 // 0x148 + CH4_GAMMA_RD_DATA volatile.Register32 // 0x14C + CH5_GAMMA_WR volatile.Register32 // 0x150 + CH5_GAMMA_WR_ADDR volatile.Register32 // 0x154 + CH5_GAMMA_RD_ADDR volatile.Register32 // 0x158 + CH5_GAMMA_RD_DATA volatile.Register32 // 0x15C + _ [32]byte + CH0_GAMMA_CONF volatile.Register32 // 0x180 + CH1_GAMMA_CONF volatile.Register32 // 0x184 + CH2_GAMMA_CONF volatile.Register32 // 0x188 + CH3_GAMMA_CONF volatile.Register32 // 0x18C + CH4_GAMMA_CONF volatile.Register32 // 0x190 + CH5_GAMMA_CONF volatile.Register32 // 0x194 + _ [8]byte + EVT_TASK_EN0 volatile.Register32 // 0x1A0 + EVT_TASK_EN1 volatile.Register32 // 0x1A4 + EVT_TASK_EN2 volatile.Register32 // 0x1A8 + _ [4]byte + TIMER0_CMP volatile.Register32 // 0x1B0 + TIMER1_CMP volatile.Register32 // 0x1B4 + TIMER2_CMP volatile.Register32 // 0x1B8 + TIMER3_CMP volatile.Register32 // 0x1BC + TIMER0_CNT_CAP volatile.Register32 // 0x1C0 + TIMER1_CNT_CAP volatile.Register32 // 0x1C4 + TIMER2_CNT_CAP volatile.Register32 // 0x1C8 + TIMER3_CNT_CAP volatile.Register32 // 0x1CC + _ [32]byte + CONF volatile.Register32 // 0x1F0 + _ [8]byte + DATE volatile.Register32 // 0x1FC +} + +// LEDC.CH0_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH0_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH0_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH0_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH0_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH0_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH0_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH0_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH0_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH0_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH0_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH0_HPOINT.Reg, volatile.LoadUint32(&o.CH0_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH0_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH0_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH0_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY.Reg, volatile.LoadUint32(&o.CH0_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH0_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH0_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH0_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY_R.Reg, volatile.LoadUint32(&o.CH0_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH1_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH1_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH1_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH1_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH1_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH1_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH1_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH1_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH1_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH1_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH1_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH1_HPOINT.Reg, volatile.LoadUint32(&o.CH1_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH1_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH1_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH1_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY.Reg, volatile.LoadUint32(&o.CH1_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH1_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH1_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH1_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY_R.Reg, volatile.LoadUint32(&o.CH1_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH2_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH2_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH2_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH2_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH2_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH2_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH2_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH2_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH2_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH2_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH2_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH2_HPOINT.Reg, volatile.LoadUint32(&o.CH2_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH2_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH2_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH2_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY.Reg, volatile.LoadUint32(&o.CH2_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH2_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH2_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH2_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY_R.Reg, volatile.LoadUint32(&o.CH2_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH3_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH3_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH3_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH3_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH3_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH3_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH3_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH3_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH3_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH3_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH3_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH3_HPOINT.Reg, volatile.LoadUint32(&o.CH3_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH3_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH3_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH3_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY.Reg, volatile.LoadUint32(&o.CH3_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH3_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH3_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH3_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY_R.Reg, volatile.LoadUint32(&o.CH3_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH4_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH4_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH4_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH4_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH4_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH4_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH4_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH4_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH4_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH4_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH4_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH4_HPOINT.Reg, volatile.LoadUint32(&o.CH4_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH4_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH4_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH4_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY.Reg, volatile.LoadUint32(&o.CH4_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH4_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH4_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH4_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY_R.Reg, volatile.LoadUint32(&o.CH4_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH5_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH5_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH5_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH5_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH5_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH5_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH5_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH5_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH5_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH5_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH5_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH5_HPOINT.Reg, volatile.LoadUint32(&o.CH5_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH5_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH5_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH5_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY.Reg, volatile.LoadUint32(&o.CH5_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH5_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH5_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH5_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY_R.Reg, volatile.LoadUint32(&o.CH5_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.TIMER0_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER0_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER0_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER0_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER0_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER0_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER0_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER0_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER0_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER0_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER0_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER0_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER0_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER0_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER0_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER0_VALUE.Reg, volatile.LoadUint32(&o.TIMER0_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER0_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER0_VALUE.Reg) & 0xfffff +} + +// LEDC.TIMER1_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER1_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER1_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER1_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER1_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER1_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER1_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER1_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER1_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER1_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER1_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER1_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER1_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER1_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER1_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER1_VALUE.Reg, volatile.LoadUint32(&o.TIMER1_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER1_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER1_VALUE.Reg) & 0xfffff +} + +// LEDC.TIMER2_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER2_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER2_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER2_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER2_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER2_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER2_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER2_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER2_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER2_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER2_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER2_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER2_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER2_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER2_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER2_VALUE.Reg, volatile.LoadUint32(&o.TIMER2_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER2_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER2_VALUE.Reg) & 0xfffff +} + +// LEDC.TIMER3_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER3_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER3_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER3_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER3_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER3_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER3_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER3_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER3_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER3_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER3_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER3_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER3_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER3_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER3_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER3_VALUE.Reg, volatile.LoadUint32(&o.TIMER3_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER3_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER3_VALUE.Reg) & 0xfffff +} + +// LEDC.INT_RAW: Raw interrupt status +func (o *LEDC_Type) SetINT_RAW_TIMER0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_RAW_TIMER0_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_RAW_TIMER1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_RAW_TIMER2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_RAW_TIMER3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_RAW_TIMER3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} + +// LEDC.INT_ST: Masked interrupt status +func (o *LEDC_Type) SetINT_ST_TIMER0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ST_TIMER0_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ST_TIMER1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ST_TIMER1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ST_TIMER2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ST_TIMER2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ST_TIMER3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ST_TIMER3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} + +// LEDC.INT_ENA: Interrupt enable bits +func (o *LEDC_Type) SetINT_ENA_TIMER0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ENA_TIMER0_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ENA_TIMER1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ENA_TIMER2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ENA_TIMER3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ENA_TIMER3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} + +// LEDC.INT_CLR: Interrupt clear bits +func (o *LEDC_Type) SetINT_CLR_TIMER0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_CLR_TIMER0_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_CLR_TIMER1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_CLR_TIMER2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_CLR_TIMER3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_CLR_TIMER3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} + +// LEDC.CH0_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH0_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH0_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH0_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH0_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH0_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH0_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH0_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH0_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH0_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH0_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH0_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH1_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH1_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH1_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH1_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH1_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH1_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH1_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH1_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH1_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH1_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH1_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH1_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH2_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH2_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH2_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH2_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH2_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH2_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH2_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH2_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH2_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH2_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH2_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH2_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH3_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH3_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH3_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH3_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH3_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH3_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH3_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH3_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH3_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH3_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH3_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH3_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH4_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH4_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH4_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH4_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH4_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH4_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH4_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH4_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH4_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH4_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH4_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH4_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH5_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH5_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH5_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH5_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH5_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH5_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH5_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH5_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH5_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH5_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH5_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH5_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH0_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH1_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH2_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH3_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH4_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH5_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.EVT_TASK_EN0: Ledc event task enable bit register0. +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN() uint32 { + return volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME0_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME0_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME1_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME1_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME2_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME2_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME3_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME3_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4000000) >> 26 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8000000) >> 27 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10000000) >> 28 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20000000) >> 29 +} + +// LEDC.EVT_TASK_EN1: Ledc event task enable bit register1. +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN() uint32 { + return volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4000000) >> 26 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8000000)|value<<27) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8000000) >> 27 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10000000)|value<<28) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10000000) >> 28 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20000000)|value<<29) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20000000) >> 29 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80000000) >> 31 +} + +// LEDC.EVT_TASK_EN2: Ledc event task enable bit register2. +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN() uint32 { + return volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x1 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x200000) >> 21 +} + +// LEDC.TIMER0_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER0_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CMP.Reg, volatile.LoadUint32(&o.TIMER0_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER0_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER0_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER1_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER1_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CMP.Reg, volatile.LoadUint32(&o.TIMER1_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER1_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER1_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER2_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER2_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CMP.Reg, volatile.LoadUint32(&o.TIMER2_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER2_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER2_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER3_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER3_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CMP.Reg, volatile.LoadUint32(&o.TIMER3_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER3_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER3_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER0_CNT_CAP: Ledc timer%s count value capture register. +func (o *LEDC_Type) SetTIMER0_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER0_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER0_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER0_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.TIMER1_CNT_CAP: Ledc timer%s count value capture register. +func (o *LEDC_Type) SetTIMER1_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER1_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER1_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER1_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.TIMER2_CNT_CAP: Ledc timer%s count value capture register. +func (o *LEDC_Type) SetTIMER2_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER2_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER2_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER2_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.TIMER3_CNT_CAP: Ledc timer%s count value capture register. +func (o *LEDC_Type) SetTIMER3_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER3_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER3_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER3_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.CONF: Global ledc configuration register +func (o *LEDC_Type) SetCONF_APB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCONF_APB_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x3 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH0(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH1(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH2(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH3(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH4(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH5(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH5() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// LEDC.DATE: Version control register +func (o *LEDC_Type) SetDATE_LEDC_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LEDC_Type) GetDATE_LEDC_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LP_PERI Peripheral +type LPPERI_Type struct { + CLK_EN volatile.Register32 // 0x0 + RESET_EN volatile.Register32 // 0x4 + RNG_DATA volatile.Register32 // 0x8 + CPU volatile.Register32 // 0xC + BUS_TIMEOUT volatile.Register32 // 0x10 + BUS_TIMEOUT_ADDR volatile.Register32 // 0x14 + BUS_TIMEOUT_UID volatile.Register32 // 0x18 + MEM_CTRL volatile.Register32 // 0x1C + INTERRUPT_SOURCE volatile.Register32 // 0x20 + _ [984]byte + DATE volatile.Register32 // 0x3FC +} + +// LPPERI.CLK_EN: need_des +func (o *LPPERI_Type) SetCLK_EN_LP_TOUCH_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x800000)|value<<23) +} +func (o *LPPERI_Type) GetCLK_EN_LP_TOUCH_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x800000) >> 23 +} +func (o *LPPERI_Type) SetCLK_EN_RNG_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *LPPERI_Type) GetCLK_EN_RNG_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1000000) >> 24 +} +func (o *LPPERI_Type) SetCLK_EN_OTP_DBG_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *LPPERI_Type) GetCLK_EN_OTP_DBG_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x2000000) >> 25 +} +func (o *LPPERI_Type) SetCLK_EN_LP_UART_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LPPERI_Type) GetCLK_EN_LP_UART_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x4000000) >> 26 +} +func (o *LPPERI_Type) SetCLK_EN_LP_IO_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LPPERI_Type) GetCLK_EN_LP_IO_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x8000000) >> 27 +} +func (o *LPPERI_Type) SetCLK_EN_LP_EXT_I2C_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LPPERI_Type) GetCLK_EN_LP_EXT_I2C_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10000000) >> 28 +} +func (o *LPPERI_Type) SetCLK_EN_LP_ANA_I2C_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetCLK_EN_LP_ANA_I2C_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetCLK_EN_EFUSE_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetCLK_EN_EFUSE_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetCLK_EN_LP_CPU_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetCLK_EN_LP_CPU_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x80000000) >> 31 +} + +// LPPERI.RESET_EN: need_des +func (o *LPPERI_Type) SetRESET_EN_BUS_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x800000)|value<<23) +} +func (o *LPPERI_Type) GetRESET_EN_BUS_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x800000) >> 23 +} +func (o *LPPERI_Type) SetRESET_EN_LP_TOUCH_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *LPPERI_Type) GetRESET_EN_LP_TOUCH_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x1000000) >> 24 +} +func (o *LPPERI_Type) SetRESET_EN_OTP_DBG_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *LPPERI_Type) GetRESET_EN_OTP_DBG_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x2000000) >> 25 +} +func (o *LPPERI_Type) SetRESET_EN_LP_UART_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LPPERI_Type) GetRESET_EN_LP_UART_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x4000000) >> 26 +} +func (o *LPPERI_Type) SetRESET_EN_LP_IO_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LPPERI_Type) GetRESET_EN_LP_IO_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x8000000) >> 27 +} +func (o *LPPERI_Type) SetRESET_EN_LP_EXT_I2C_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LPPERI_Type) GetRESET_EN_LP_EXT_I2C_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x10000000) >> 28 +} +func (o *LPPERI_Type) SetRESET_EN_LP_ANA_I2C_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetRESET_EN_LP_ANA_I2C_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetRESET_EN_EFUSE_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetRESET_EN_EFUSE_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetRESET_EN_LP_CPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetRESET_EN_LP_CPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x80000000) >> 31 +} + +// LPPERI.RNG_DATA: need_des +func (o *LPPERI_Type) SetRNG_DATA(value uint32) { + volatile.StoreUint32(&o.RNG_DATA.Reg, value) +} +func (o *LPPERI_Type) GetRNG_DATA() uint32 { + return volatile.LoadUint32(&o.RNG_DATA.Reg) +} + +// LPPERI.CPU: need_des +func (o *LPPERI_Type) SetCPU_LPCORE_DBGM_UNAVALIABLE(value uint32) { + volatile.StoreUint32(&o.CPU.Reg, volatile.LoadUint32(&o.CPU.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetCPU_LPCORE_DBGM_UNAVALIABLE() uint32 { + return (volatile.LoadUint32(&o.CPU.Reg) & 0x80000000) >> 31 +} + +// LPPERI.BUS_TIMEOUT: need_des +func (o *LPPERI_Type) SetBUS_TIMEOUT_LP_PERI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT.Reg)&^(0x3fffc000)|value<<14) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_LP_PERI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMEOUT.Reg) & 0x3fffc000) >> 14 +} +func (o *LPPERI_Type) SetBUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMEOUT.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetBUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMEOUT.Reg) & 0x80000000) >> 31 +} + +// LPPERI.BUS_TIMEOUT_ADDR: need_des +func (o *LPPERI_Type) SetBUS_TIMEOUT_ADDR(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT_ADDR.Reg, value) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_ADDR() uint32 { + return volatile.LoadUint32(&o.BUS_TIMEOUT_ADDR.Reg) +} + +// LPPERI.BUS_TIMEOUT_UID: need_des +func (o *LPPERI_Type) SetBUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT_UID.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT_UID.Reg)&^(0x7f)|value) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID() uint32 { + return volatile.LoadUint32(&o.BUS_TIMEOUT_UID.Reg) & 0x7f +} + +// LPPERI.MEM_CTRL: need_des +func (o *LPPERI_Type) SetMEM_CTRL_UART_WAKEUP_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x1)|value) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_WAKEUP_FLAG_CLR() uint32 { + return volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x1 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_WAKEUP_FLAG(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_WAKEUP_FLAG() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x2) >> 1 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x80000000) >> 31 +} + +// LPPERI.INTERRUPT_SOURCE: need_des +func (o *LPPERI_Type) SetINTERRUPT_SOURCE_LP_INTERRUPT_SOURCE(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_SOURCE.Reg, volatile.LoadUint32(&o.INTERRUPT_SOURCE.Reg)&^(0x3f)|value) +} +func (o *LPPERI_Type) GetINTERRUPT_SOURCE_LP_INTERRUPT_SOURCE() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_SOURCE.Reg) & 0x3f +} + +// LPPERI.DATE: need_des +func (o *LPPERI_Type) SetDATE_LPPERI_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LPPERI_Type) GetDATE_LPPERI_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LPPERI_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_ANA Peripheral +type LP_ANA_Type struct { + BOD_MODE0_CNTL volatile.Register32 // 0x0 + BOD_MODE1_CNTL volatile.Register32 // 0x4 + CK_GLITCH_CNTL volatile.Register32 // 0x8 + FIB_ENABLE volatile.Register32 // 0xC + INT_RAW volatile.Register32 // 0x10 + INT_ST volatile.Register32 // 0x14 + INT_ENA volatile.Register32 // 0x18 + INT_CLR volatile.Register32 // 0x1C + LP_INT_RAW volatile.Register32 // 0x20 + LP_INT_ST volatile.Register32 // 0x24 + LP_INT_ENA volatile.Register32 // 0x28 + LP_INT_CLR volatile.Register32 // 0x2C + _ [972]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_ANA.BOD_MODE0_CNTL: need_des +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x40)|value<<6) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x40) >> 6 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x80)|value<<7) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x80) >> 7 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x3ff00)|value<<8) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x3ff00) >> 8 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0xffc0000)|value<<18) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0xffc0000) >> 18 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_RESET_SEL(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_RESET_SEL() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.BOD_MODE1_CNTL: need_des +func (o *LP_ANA_Type) SetBOD_MODE1_CNTL_BOD_MODE1_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE1_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE1_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetBOD_MODE1_CNTL_BOD_MODE1_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE1_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.CK_GLITCH_CNTL: need_des +func (o *LP_ANA_Type) SetCK_GLITCH_CNTL_CK_GLITCH_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.CK_GLITCH_CNTL.Reg, volatile.LoadUint32(&o.CK_GLITCH_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetCK_GLITCH_CNTL_CK_GLITCH_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.CK_GLITCH_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.FIB_ENABLE: need_des +func (o *LP_ANA_Type) SetFIB_ENABLE(value uint32) { + volatile.StoreUint32(&o.FIB_ENABLE.Reg, value) +} +func (o *LP_ANA_Type) GetFIB_ENABLE() uint32 { + return volatile.LoadUint32(&o.FIB_ENABLE.Reg) +} + +// LP_ANA.INT_RAW: need_des +func (o *LP_ANA_Type) SetINT_RAW_BOD_MODE0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_RAW_BOD_MODE0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.INT_ST: need_des +func (o *LP_ANA_Type) SetINT_ST_BOD_MODE0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_ST_BOD_MODE0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.INT_ENA: need_des +func (o *LP_ANA_Type) SetINT_ENA_BOD_MODE0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_ENA_BOD_MODE0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.INT_CLR: need_des +func (o *LP_ANA_Type) SetINT_CLR_BOD_MODE0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_CLR_BOD_MODE0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_RAW: need_des +func (o *LP_ANA_Type) SetLP_INT_RAW_BOD_MODE0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_RAW_BOD_MODE0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_ST: need_des +func (o *LP_ANA_Type) SetLP_INT_ST_BOD_MODE0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_ST_BOD_MODE0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_ENA: need_des +func (o *LP_ANA_Type) SetLP_INT_ENA_BOD_MODE0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_ENA_BOD_MODE0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_CLR: need_des +func (o *LP_ANA_Type) SetLP_INT_CLR_BOD_MODE0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_CLR_BOD_MODE0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.DATE: need_des +func (o *LP_ANA_Type) SetDATE_LP_ANA_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_ANA_Type) GetDATE_LP_ANA_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_ANA_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_AON Peripheral +type LP_AON_Type struct { + STORE0 volatile.Register32 // 0x0 + STORE1 volatile.Register32 // 0x4 + STORE2 volatile.Register32 // 0x8 + STORE3 volatile.Register32 // 0xC + STORE4 volatile.Register32 // 0x10 + STORE5 volatile.Register32 // 0x14 + STORE6 volatile.Register32 // 0x18 + STORE7 volatile.Register32 // 0x1C + STORE8 volatile.Register32 // 0x20 + STORE9 volatile.Register32 // 0x24 + GPIO_MUX volatile.Register32 // 0x28 + GPIO_HOLD0 volatile.Register32 // 0x2C + GPIO_HOLD1 volatile.Register32 // 0x30 + SYS_CFG volatile.Register32 // 0x34 + CPUCORE0_CFG volatile.Register32 // 0x38 + IO_MUX volatile.Register32 // 0x3C + EXT_WAKEUP_CNTL volatile.Register32 // 0x40 + USB volatile.Register32 // 0x44 + LPBUS volatile.Register32 // 0x48 + SDIO_ACTIVE volatile.Register32 // 0x4C + LPCORE volatile.Register32 // 0x50 + SAR_CCT volatile.Register32 // 0x54 + _ [932]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_AON.STORE0: need_des +func (o *LP_AON_Type) SetSTORE0(value uint32) { + volatile.StoreUint32(&o.STORE0.Reg, value) +} +func (o *LP_AON_Type) GetSTORE0() uint32 { + return volatile.LoadUint32(&o.STORE0.Reg) +} + +// LP_AON.STORE1: need_des +func (o *LP_AON_Type) SetSTORE1(value uint32) { + volatile.StoreUint32(&o.STORE1.Reg, value) +} +func (o *LP_AON_Type) GetSTORE1() uint32 { + return volatile.LoadUint32(&o.STORE1.Reg) +} + +// LP_AON.STORE2: need_des +func (o *LP_AON_Type) SetSTORE2(value uint32) { + volatile.StoreUint32(&o.STORE2.Reg, value) +} +func (o *LP_AON_Type) GetSTORE2() uint32 { + return volatile.LoadUint32(&o.STORE2.Reg) +} + +// LP_AON.STORE3: need_des +func (o *LP_AON_Type) SetSTORE3(value uint32) { + volatile.StoreUint32(&o.STORE3.Reg, value) +} +func (o *LP_AON_Type) GetSTORE3() uint32 { + return volatile.LoadUint32(&o.STORE3.Reg) +} + +// LP_AON.STORE4: need_des +func (o *LP_AON_Type) SetSTORE4(value uint32) { + volatile.StoreUint32(&o.STORE4.Reg, value) +} +func (o *LP_AON_Type) GetSTORE4() uint32 { + return volatile.LoadUint32(&o.STORE4.Reg) +} + +// LP_AON.STORE5: need_des +func (o *LP_AON_Type) SetSTORE5(value uint32) { + volatile.StoreUint32(&o.STORE5.Reg, value) +} +func (o *LP_AON_Type) GetSTORE5() uint32 { + return volatile.LoadUint32(&o.STORE5.Reg) +} + +// LP_AON.STORE6: need_des +func (o *LP_AON_Type) SetSTORE6(value uint32) { + volatile.StoreUint32(&o.STORE6.Reg, value) +} +func (o *LP_AON_Type) GetSTORE6() uint32 { + return volatile.LoadUint32(&o.STORE6.Reg) +} + +// LP_AON.STORE7: need_des +func (o *LP_AON_Type) SetSTORE7(value uint32) { + volatile.StoreUint32(&o.STORE7.Reg, value) +} +func (o *LP_AON_Type) GetSTORE7() uint32 { + return volatile.LoadUint32(&o.STORE7.Reg) +} + +// LP_AON.STORE8: need_des +func (o *LP_AON_Type) SetSTORE8(value uint32) { + volatile.StoreUint32(&o.STORE8.Reg, value) +} +func (o *LP_AON_Type) GetSTORE8() uint32 { + return volatile.LoadUint32(&o.STORE8.Reg) +} + +// LP_AON.STORE9: need_des +func (o *LP_AON_Type) SetSTORE9(value uint32) { + volatile.StoreUint32(&o.STORE9.Reg, value) +} +func (o *LP_AON_Type) GetSTORE9() uint32 { + return volatile.LoadUint32(&o.STORE9.Reg) +} + +// LP_AON.GPIO_MUX: need_des +func (o *LP_AON_Type) SetGPIO_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO_MUX.Reg, volatile.LoadUint32(&o.GPIO_MUX.Reg)&^(0xff)|value) +} +func (o *LP_AON_Type) GetGPIO_MUX_SEL() uint32 { + return volatile.LoadUint32(&o.GPIO_MUX.Reg) & 0xff +} + +// LP_AON.GPIO_HOLD0: need_des +func (o *LP_AON_Type) SetGPIO_HOLD0(value uint32) { + volatile.StoreUint32(&o.GPIO_HOLD0.Reg, value) +} +func (o *LP_AON_Type) GetGPIO_HOLD0() uint32 { + return volatile.LoadUint32(&o.GPIO_HOLD0.Reg) +} + +// LP_AON.GPIO_HOLD1: need_des +func (o *LP_AON_Type) SetGPIO_HOLD1(value uint32) { + volatile.StoreUint32(&o.GPIO_HOLD1.Reg, value) +} +func (o *LP_AON_Type) GetGPIO_HOLD1() uint32 { + return volatile.LoadUint32(&o.GPIO_HOLD1.Reg) +} + +// LP_AON.SYS_CFG: need_des +func (o *LP_AON_Type) SetSYS_CFG_FORCE_DOWNLOAD_BOOT(value uint32) { + volatile.StoreUint32(&o.SYS_CFG.Reg, volatile.LoadUint32(&o.SYS_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_Type) GetSYS_CFG_FORCE_DOWNLOAD_BOOT() uint32 { + return (volatile.LoadUint32(&o.SYS_CFG.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_Type) SetSYS_CFG_HPSYS_SW_RESET(value uint32) { + volatile.StoreUint32(&o.SYS_CFG.Reg, volatile.LoadUint32(&o.SYS_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetSYS_CFG_HPSYS_SW_RESET() uint32 { + return (volatile.LoadUint32(&o.SYS_CFG.Reg) & 0x80000000) >> 31 +} + +// LP_AON.CPUCORE0_CFG: need_des +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_SW_STALL(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0xff)|value) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_SW_STALL() uint32 { + return volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0xff +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_SW_RESET(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_SW_RESET() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_DRESET_MASK(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_DRESET_MASK() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x80000000) >> 31 +} + +// LP_AON.IO_MUX: need_des +func (o *LP_AON_Type) SetIO_MUX_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX.Reg, volatile.LoadUint32(&o.IO_MUX.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetIO_MUX_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.IO_MUX.Reg) & 0x80000000) >> 31 +} + +// LP_AON.EXT_WAKEUP_CNTL: need_des +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0xff)|value) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0xff +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x4000)|value<<14) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x4000) >> 14 +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x7f8000)|value<<15) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x7f8000) >> 15 +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x7f800000)|value<<23) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x7f800000) >> 23 +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_AON.USB: need_des +func (o *LP_AON_Type) SetUSB_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.USB.Reg, volatile.LoadUint32(&o.USB.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetUSB_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.USB.Reg) & 0x80000000) >> 31 +} + +// LP_AON.LPBUS: need_des +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_WPULSE(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x70000)|value<<16) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_WPULSE() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x70000) >> 16 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_WA(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x380000)|value<<19) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_WA() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x380000) >> 19 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_RA(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0xc00000)|value<<22) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_RA() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0xc00000) >> 22 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_SEL_STATUS(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_SEL_STATUS() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_SEL_UPDATE(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_SEL_UPDATE() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x80000000) >> 31 +} + +// LP_AON.SDIO_ACTIVE: need_des +func (o *LP_AON_Type) SetSDIO_ACTIVE_SDIO_ACT_DNUM(value uint32) { + volatile.StoreUint32(&o.SDIO_ACTIVE.Reg, volatile.LoadUint32(&o.SDIO_ACTIVE.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_AON_Type) GetSDIO_ACTIVE_SDIO_ACT_DNUM() uint32 { + return (volatile.LoadUint32(&o.SDIO_ACTIVE.Reg) & 0xffc00000) >> 22 +} + +// LP_AON.LPCORE: need_des +func (o *LP_AON_Type) SetLPCORE_ETM_WAKEUP_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.LPCORE.Reg, volatile.LoadUint32(&o.LPCORE.Reg)&^(0x1)|value) +} +func (o *LP_AON_Type) GetLPCORE_ETM_WAKEUP_FLAG_CLR() uint32 { + return volatile.LoadUint32(&o.LPCORE.Reg) & 0x1 +} +func (o *LP_AON_Type) SetLPCORE_ETM_WAKEUP_FLAG(value uint32) { + volatile.StoreUint32(&o.LPCORE.Reg, volatile.LoadUint32(&o.LPCORE.Reg)&^(0x2)|value<<1) +} +func (o *LP_AON_Type) GetLPCORE_ETM_WAKEUP_FLAG() uint32 { + return (volatile.LoadUint32(&o.LPCORE.Reg) & 0x2) >> 1 +} +func (o *LP_AON_Type) SetLPCORE_DISABLE(value uint32) { + volatile.StoreUint32(&o.LPCORE.Reg, volatile.LoadUint32(&o.LPCORE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetLPCORE_DISABLE() uint32 { + return (volatile.LoadUint32(&o.LPCORE.Reg) & 0x80000000) >> 31 +} + +// LP_AON.SAR_CCT: need_des +func (o *LP_AON_Type) SetSAR_CCT_SAR2_PWDET_CCT(value uint32) { + volatile.StoreUint32(&o.SAR_CCT.Reg, volatile.LoadUint32(&o.SAR_CCT.Reg)&^(0xe0000000)|value<<29) +} +func (o *LP_AON_Type) GetSAR_CCT_SAR2_PWDET_CCT() uint32 { + return (volatile.LoadUint32(&o.SAR_CCT.Reg) & 0xe0000000) >> 29 +} + +// LP_AON.DATE: need_des +func (o *LP_AON_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_AON_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_AON_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power Access Permission Management Controller +type LP_APM_Type struct { + REGION_FILTER_EN volatile.Register32 // 0x0 + REGION0_ADDR_START volatile.Register32 // 0x4 + REGION0_ADDR_END volatile.Register32 // 0x8 + REGION0_PMS_ATTR volatile.Register32 // 0xC + REGION1_ADDR_START volatile.Register32 // 0x10 + REGION1_ADDR_END volatile.Register32 // 0x14 + REGION1_PMS_ATTR volatile.Register32 // 0x18 + REGION2_ADDR_START volatile.Register32 // 0x1C + REGION2_ADDR_END volatile.Register32 // 0x20 + REGION2_PMS_ATTR volatile.Register32 // 0x24 + REGION3_ADDR_START volatile.Register32 // 0x28 + REGION3_ADDR_END volatile.Register32 // 0x2C + REGION3_PMS_ATTR volatile.Register32 // 0x30 + _ [144]byte + FUNC_CTRL volatile.Register32 // 0xC4 + M0_STATUS volatile.Register32 // 0xC8 + M0_STATUS_CLR volatile.Register32 // 0xCC + M0_EXCEPTION_INFO0 volatile.Register32 // 0xD0 + M0_EXCEPTION_INFO1 volatile.Register32 // 0xD4 + M1_STATUS volatile.Register32 // 0xD8 + M1_STATUS_CLR volatile.Register32 // 0xDC + M1_EXCEPTION_INFO0 volatile.Register32 // 0xE0 + M1_EXCEPTION_INFO1 volatile.Register32 // 0xE4 + INT_EN volatile.Register32 // 0xE8 + CLOCK_GATE volatile.Register32 // 0xEC + _ [12]byte + DATE volatile.Register32 // 0xFC +} + +// LP_APM.REGION_FILTER_EN: Region filter enable register +func (o *LP_APM_Type) SetREGION_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.REGION_FILTER_EN.Reg, volatile.LoadUint32(&o.REGION_FILTER_EN.Reg)&^(0xf)|value) +} +func (o *LP_APM_Type) GetREGION_FILTER_EN() uint32 { + return volatile.LoadUint32(&o.REGION_FILTER_EN.Reg) & 0xf +} + +// LP_APM.REGION0_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION0_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION0_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_START.Reg) +} + +// LP_APM.REGION0_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION0_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION0_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_END.Reg) +} + +// LP_APM.REGION0_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.REGION1_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION1_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION1_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_START.Reg) +} + +// LP_APM.REGION1_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION1_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION1_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_END.Reg) +} + +// LP_APM.REGION1_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.REGION2_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION2_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION2_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_START.Reg) +} + +// LP_APM.REGION2_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION2_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION2_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_END.Reg) +} + +// LP_APM.REGION2_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.REGION3_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION3_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION3_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_START.Reg) +} + +// LP_APM.REGION3_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION3_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION3_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_END.Reg) +} + +// LP_APM.REGION3_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.FUNC_CTRL: PMS function control register +func (o *LP_APM_Type) SetFUNC_CTRL_M0_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetFUNC_CTRL_M0_PMS_FUNC_EN() uint32 { + return volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x1 +} +func (o *LP_APM_Type) SetFUNC_CTRL_M1_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetFUNC_CTRL_M1_PMS_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x2) >> 1 +} + +// LP_APM.M0_STATUS: M0 status register +func (o *LP_APM_Type) SetM0_STATUS_M0_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M0_STATUS.Reg, volatile.LoadUint32(&o.M0_STATUS.Reg)&^(0x3)|value) +} +func (o *LP_APM_Type) GetM0_STATUS_M0_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M0_STATUS.Reg) & 0x3 +} + +// LP_APM.M0_STATUS_CLR: M0 status clear register +func (o *LP_APM_Type) SetM0_STATUS_CLR_M0_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M0_STATUS_CLR.Reg, volatile.LoadUint32(&o.M0_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetM0_STATUS_CLR_M0_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M0_STATUS_CLR.Reg) & 0x1 +} + +// LP_APM.M0_EXCEPTION_INFO0: M0 exception_info0 register +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0xf)|value) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0xf +} +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// LP_APM.M0_EXCEPTION_INFO1: M0 exception_info1 register +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO1.Reg, value) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO1.Reg) +} + +// LP_APM.M1_STATUS: M1 status register +func (o *LP_APM_Type) SetM1_STATUS_M1_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M1_STATUS.Reg, volatile.LoadUint32(&o.M1_STATUS.Reg)&^(0x3)|value) +} +func (o *LP_APM_Type) GetM1_STATUS_M1_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M1_STATUS.Reg) & 0x3 +} + +// LP_APM.M1_STATUS_CLR: M1 status clear register +func (o *LP_APM_Type) SetM1_STATUS_CLR_M1_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M1_STATUS_CLR.Reg, volatile.LoadUint32(&o.M1_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetM1_STATUS_CLR_M1_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M1_STATUS_CLR.Reg) & 0x1 +} + +// LP_APM.M1_EXCEPTION_INFO0: M1 exception_info0 register +func (o *LP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0xf)|value) +} +func (o *LP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0xf +} +func (o *LP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *LP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *LP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// LP_APM.M1_EXCEPTION_INFO1: M1 exception_info1 register +func (o *LP_APM_Type) SetM1_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO1.Reg, value) +} +func (o *LP_APM_Type) GetM1_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M1_EXCEPTION_INFO1.Reg) +} + +// LP_APM.INT_EN: APM interrupt enable register +func (o *LP_APM_Type) SetINT_EN_M0_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetINT_EN_M0_APM_INT_EN() uint32 { + return volatile.LoadUint32(&o.INT_EN.Reg) & 0x1 +} +func (o *LP_APM_Type) SetINT_EN_M1_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetINT_EN_M1_APM_INT_EN() uint32 { + return (volatile.LoadUint32(&o.INT_EN.Reg) & 0x2) >> 1 +} + +// LP_APM.CLOCK_GATE: clock gating register +func (o *LP_APM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// LP_APM.DATE: Version register +func (o *LP_APM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_APM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LP_APM0 Peripheral +type LP_APM0_Type struct { + REGION_FILTER_EN volatile.Register32 // 0x0 + REGION0_ADDR_START volatile.Register32 // 0x4 + REGION0_ADDR_END volatile.Register32 // 0x8 + REGION0_PMS_ATTR volatile.Register32 // 0xC + REGION1_ADDR_START volatile.Register32 // 0x10 + REGION1_ADDR_END volatile.Register32 // 0x14 + REGION1_PMS_ATTR volatile.Register32 // 0x18 + REGION2_ADDR_START volatile.Register32 // 0x1C + REGION2_ADDR_END volatile.Register32 // 0x20 + REGION2_PMS_ATTR volatile.Register32 // 0x24 + REGION3_ADDR_START volatile.Register32 // 0x28 + REGION3_ADDR_END volatile.Register32 // 0x2C + REGION3_PMS_ATTR volatile.Register32 // 0x30 + _ [144]byte + FUNC_CTRL volatile.Register32 // 0xC4 + M0_STATUS volatile.Register32 // 0xC8 + M0_STATUS_CLR volatile.Register32 // 0xCC + M0_EXCEPTION_INFO0 volatile.Register32 // 0xD0 + M0_EXCEPTION_INFO1 volatile.Register32 // 0xD4 + INT_EN volatile.Register32 // 0xD8 + CLOCK_GATE volatile.Register32 // 0xDC + _ [1820]byte + DATE volatile.Register32 // 0x7FC +} + +// LP_APM0.REGION_FILTER_EN: Region filter enable register +func (o *LP_APM0_Type) SetREGION_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.REGION_FILTER_EN.Reg, volatile.LoadUint32(&o.REGION_FILTER_EN.Reg)&^(0xf)|value) +} +func (o *LP_APM0_Type) GetREGION_FILTER_EN() uint32 { + return volatile.LoadUint32(&o.REGION_FILTER_EN.Reg) & 0xf +} + +// LP_APM0.REGION0_ADDR_START: Region address register +func (o *LP_APM0_Type) SetREGION0_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_START.Reg, value) +} +func (o *LP_APM0_Type) GetREGION0_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_START.Reg) +} + +// LP_APM0.REGION0_ADDR_END: Region address register +func (o *LP_APM0_Type) SetREGION0_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_END.Reg, value) +} +func (o *LP_APM0_Type) GetREGION0_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_END.Reg) +} + +// LP_APM0.REGION0_PMS_ATTR: Region access authority attribute register +func (o *LP_APM0_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM0_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM0_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM0_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM0_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM0_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM0_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM0_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM0_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM0_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM0_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM0_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM0_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM0_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM0_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM0_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM0_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM0_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM0.REGION1_ADDR_START: Region address register +func (o *LP_APM0_Type) SetREGION1_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_START.Reg, value) +} +func (o *LP_APM0_Type) GetREGION1_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_START.Reg) +} + +// LP_APM0.REGION1_ADDR_END: Region address register +func (o *LP_APM0_Type) SetREGION1_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_END.Reg, value) +} +func (o *LP_APM0_Type) GetREGION1_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_END.Reg) +} + +// LP_APM0.REGION1_PMS_ATTR: Region access authority attribute register +func (o *LP_APM0_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM0_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM0_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM0_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM0_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM0_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM0_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM0_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM0_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM0_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM0_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM0_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM0_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM0_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM0_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM0_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM0_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM0_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM0.REGION2_ADDR_START: Region address register +func (o *LP_APM0_Type) SetREGION2_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_START.Reg, value) +} +func (o *LP_APM0_Type) GetREGION2_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_START.Reg) +} + +// LP_APM0.REGION2_ADDR_END: Region address register +func (o *LP_APM0_Type) SetREGION2_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_END.Reg, value) +} +func (o *LP_APM0_Type) GetREGION2_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_END.Reg) +} + +// LP_APM0.REGION2_PMS_ATTR: Region access authority attribute register +func (o *LP_APM0_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM0_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM0_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM0_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM0_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM0_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM0_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM0_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM0_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM0_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM0_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM0_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM0_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM0_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM0_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM0_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM0_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM0_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM0.REGION3_ADDR_START: Region address register +func (o *LP_APM0_Type) SetREGION3_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_START.Reg, value) +} +func (o *LP_APM0_Type) GetREGION3_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_START.Reg) +} + +// LP_APM0.REGION3_ADDR_END: Region address register +func (o *LP_APM0_Type) SetREGION3_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_END.Reg, value) +} +func (o *LP_APM0_Type) GetREGION3_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_END.Reg) +} + +// LP_APM0.REGION3_PMS_ATTR: Region access authority attribute register +func (o *LP_APM0_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM0_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM0_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM0_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM0_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM0_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM0_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM0_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM0_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM0_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM0_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM0_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM0_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM0_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM0_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM0_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM0_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM0_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM0.FUNC_CTRL: PMS function control register +func (o *LP_APM0_Type) SetFUNC_CTRL_M0_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x1)|value) +} +func (o *LP_APM0_Type) GetFUNC_CTRL_M0_PMS_FUNC_EN() uint32 { + return volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x1 +} + +// LP_APM0.M0_STATUS: M0 status register +func (o *LP_APM0_Type) SetM0_STATUS_M0_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M0_STATUS.Reg, volatile.LoadUint32(&o.M0_STATUS.Reg)&^(0x3)|value) +} +func (o *LP_APM0_Type) GetM0_STATUS_M0_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M0_STATUS.Reg) & 0x3 +} + +// LP_APM0.M0_STATUS_CLR: M0 status clear register +func (o *LP_APM0_Type) SetM0_STATUS_CLR_M0_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M0_STATUS_CLR.Reg, volatile.LoadUint32(&o.M0_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *LP_APM0_Type) GetM0_STATUS_CLR_M0_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M0_STATUS_CLR.Reg) & 0x1 +} + +// LP_APM0.M0_EXCEPTION_INFO0: M0 exception_info0 register +func (o *LP_APM0_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0xf)|value) +} +func (o *LP_APM0_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0xf +} +func (o *LP_APM0_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *LP_APM0_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *LP_APM0_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_APM0_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// LP_APM0.M0_EXCEPTION_INFO1: M0 exception_info1 register +func (o *LP_APM0_Type) SetM0_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO1.Reg, value) +} +func (o *LP_APM0_Type) GetM0_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO1.Reg) +} + +// LP_APM0.INT_EN: APM interrupt enable register +func (o *LP_APM0_Type) SetINT_EN_M0_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x1)|value) +} +func (o *LP_APM0_Type) GetINT_EN_M0_APM_INT_EN() uint32 { + return volatile.LoadUint32(&o.INT_EN.Reg) & 0x1 +} + +// LP_APM0.CLOCK_GATE: clock gating register +func (o *LP_APM0_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *LP_APM0_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// LP_APM0.DATE: Version register +func (o *LP_APM0_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_APM0_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LP_CLKRST Peripheral +type LP_CLKRST_Type struct { + LP_CLK_CONF volatile.Register32 // 0x0 + LP_CLK_PO_EN volatile.Register32 // 0x4 + LP_CLK_EN volatile.Register32 // 0x8 + LP_RST_EN volatile.Register32 // 0xC + RESET_CAUSE volatile.Register32 // 0x10 + CPU_RESET volatile.Register32 // 0x14 + FOSC_CNTL volatile.Register32 // 0x18 + RC32K_CNTL volatile.Register32 // 0x1C + CLK_TO_HP volatile.Register32 // 0x20 + LPMEM_FORCE volatile.Register32 // 0x24 + LPPERI volatile.Register32 // 0x28 + XTAL32K volatile.Register32 // 0x2C + _ [972]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_CLKRST.LP_CLK_CONF: need_des +func (o *LP_CLKRST_Type) SetLP_CLK_CONF_SLOW_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_CLK_CONF.Reg)&^(0x3)|value) +} +func (o *LP_CLKRST_Type) GetLP_CLK_CONF_SLOW_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.LP_CLK_CONF.Reg) & 0x3 +} +func (o *LP_CLKRST_Type) SetLP_CLK_CONF_FAST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *LP_CLKRST_Type) GetLP_CLK_CONF_FAST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *LP_CLKRST_Type) SetLP_CLK_CONF_LP_PERI_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_CLK_CONF.Reg)&^(0x7f8)|value<<3) +} +func (o *LP_CLKRST_Type) GetLP_CLK_CONF_LP_PERI_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_CONF.Reg) & 0x7f8) >> 3 +} + +// LP_CLKRST.LP_CLK_PO_EN: need_des +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_AON_SLOW_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x1)|value) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_AON_SLOW_OEN() uint32 { + return volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x1 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_AON_FAST_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x2)|value<<1) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_AON_FAST_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x2) >> 1 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_SOSC_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x4)|value<<2) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_SOSC_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x4) >> 2 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_FOSC_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x8)|value<<3) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_FOSC_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x8) >> 3 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_OSC32K_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x10)|value<<4) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_OSC32K_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x10) >> 4 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_XTAL32K_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x20)|value<<5) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_XTAL32K_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x20) >> 5 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_CORE_EFUSE_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x40)|value<<6) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_CORE_EFUSE_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x40) >> 6 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_SLOW_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x80)|value<<7) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_SLOW_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x80) >> 7 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_FAST_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x100)|value<<8) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_FAST_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x100) >> 8 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_RNG_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x200)|value<<9) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_RNG_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x200) >> 9 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_LPBUS_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x400)|value<<10) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_LPBUS_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x400) >> 10 +} + +// LP_CLKRST.LP_CLK_EN: need_des +func (o *LP_CLKRST_Type) SetLP_CLK_EN_FAST_ORI_GATE(value uint32) { + volatile.StoreUint32(&o.LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_CLK_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLP_CLK_EN_FAST_ORI_GATE() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_EN.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.LP_RST_EN: need_des +func (o *LP_CLKRST_Type) SetLP_RST_EN_AON_EFUSE_CORE_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_AON_EFUSE_CORE_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetLP_RST_EN_LP_TIMER_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_LP_TIMER_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetLP_RST_EN_WDT_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_WDT_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetLP_RST_EN_ANA_PERI_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_ANA_PERI_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.RESET_CAUSE: need_des +func (o *LP_CLKRST_Type) SetRESET_CAUSE(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x1f)|value) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE() uint32 { + return volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x1f +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x20)|value<<5) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_FLAG() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x20) >> 5 +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_FLAG_SET(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_FLAG_SET() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.CPU_RESET: need_des +func (o *LP_CLKRST_Type) SetCPU_RESET_RTC_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_RTC_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x1c00000) >> 22 +} +func (o *LP_CLKRST_Type) SetCPU_RESET_RTC_WDT_CPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_RTC_WDT_CPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x2000000) >> 25 +} +func (o *LP_CLKRST_Type) SetCPU_RESET_CPU_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x7c000000)|value<<26) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_CPU_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x7c000000) >> 26 +} +func (o *LP_CLKRST_Type) SetCPU_RESET_CPU_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_CPU_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.FOSC_CNTL: need_des +func (o *LP_CLKRST_Type) SetFOSC_CNTL_FOSC_DFREQ(value uint32) { + volatile.StoreUint32(&o.FOSC_CNTL.Reg, volatile.LoadUint32(&o.FOSC_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetFOSC_CNTL_FOSC_DFREQ() uint32 { + return (volatile.LoadUint32(&o.FOSC_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_CLKRST.RC32K_CNTL: need_des +func (o *LP_CLKRST_Type) SetRC32K_CNTL_RC32K_DFREQ(value uint32) { + volatile.StoreUint32(&o.RC32K_CNTL.Reg, volatile.LoadUint32(&o.RC32K_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetRC32K_CNTL_RC32K_DFREQ() uint32 { + return (volatile.LoadUint32(&o.RC32K_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_CLKRST.CLK_TO_HP: need_des +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_XTAL32K(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_SOSC(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_SOSC() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_OSC32K(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_OSC32K() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_FOSC(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_FOSC() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.LPMEM_FORCE: need_des +func (o *LP_CLKRST_Type) SetLPMEM_FORCE_LPMEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LPMEM_FORCE.Reg, volatile.LoadUint32(&o.LPMEM_FORCE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLPMEM_FORCE_LPMEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LPMEM_FORCE.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.LPPERI: need_des +func (o *LP_CLKRST_Type) SetLPPERI_LP_I2C_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_I2C_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetLPPERI_LP_UART_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_UART_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.XTAL32K: need_des +func (o *LP_CLKRST_Type) SetXTAL32K_DRES_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DRES_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0x1c00000) >> 22 +} +func (o *LP_CLKRST_Type) SetXTAL32K_DGM_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0xe000000)|value<<25) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DGM_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0xe000000) >> 25 +} +func (o *LP_CLKRST_Type) SetXTAL32K_DBUF_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DBUF_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetXTAL32K_DAC_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0xe0000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DAC_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0xe0000000) >> 29 +} + +// LP_CLKRST.DATE: need_des +func (o *LP_CLKRST_Type) SetDATE_CLKRST_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_CLKRST_Type) GetDATE_CLKRST_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_CLKRST_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power I2C (Inter-Integrated Circuit) Controller 0 +type LP_I2C0_Type struct { + I2C_SCL_LOW_PERIOD volatile.Register32 // 0x0 + I2C_CTR volatile.Register32 // 0x4 + I2C_SR volatile.Register32 // 0x8 + I2C_TO volatile.Register32 // 0xC + _ [4]byte + I2C_FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + I2C_DATA volatile.Register32 // 0x1C + I2C_INT_RAW volatile.Register32 // 0x20 + I2C_INT_CLR volatile.Register32 // 0x24 + I2C_INT_ENA volatile.Register32 // 0x28 + I2C_INT_STATUS volatile.Register32 // 0x2C + I2C_SDA_HOLD volatile.Register32 // 0x30 + I2C_SDA_SAMPLE volatile.Register32 // 0x34 + I2C_SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + I2C_SCL_START_HOLD volatile.Register32 // 0x40 + I2C_SCL_RSTART_SETUP volatile.Register32 // 0x44 + I2C_SCL_STOP_HOLD volatile.Register32 // 0x48 + I2C_SCL_STOP_SETUP volatile.Register32 // 0x4C + I2C_FILTER_CFG volatile.Register32 // 0x50 + I2C_CLK_CONF volatile.Register32 // 0x54 + I2C_COMD0 volatile.Register32 // 0x58 + I2C_COMD1 volatile.Register32 // 0x5C + I2C_COMD2 volatile.Register32 // 0x60 + I2C_COMD3 volatile.Register32 // 0x64 + I2C_COMD4 volatile.Register32 // 0x68 + I2C_COMD5 volatile.Register32 // 0x6C + I2C_COMD6 volatile.Register32 // 0x70 + I2C_COMD7 volatile.Register32 // 0x74 + I2C_SCL_ST_TIME_OUT volatile.Register32 // 0x78 + I2C_SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C + I2C_SCL_SP_CONF volatile.Register32 // 0x80 + _ [116]byte + I2C_DATE volatile.Register32 // 0xF8 + _ [4]byte + I2C_TXFIFO_START_ADDR volatile.Register32 // 0x100 + _ [124]byte + I2C_RXFIFO_START_ADDR volatile.Register32 // 0x180 +} + +// LP_I2C0.I2C_SCL_LOW_PERIOD: Configures the low level width of the SCL Clock +func (o *LP_I2C0_Type) SetI2C_SCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.I2C_SCL_LOW_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C0_Type) GetI2C_SCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.I2C_SCL_LOW_PERIOD.Reg) & 0x1ff +} + +// LP_I2C0.I2C_CTR: Transmission setting +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x1)|value) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x1 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x2) >> 1 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x4) >> 2 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x8) >> 3 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_TRANS_START(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x20) >> 5 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x40) >> 6 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x80) >> 7 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_CLK_EN(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x100) >> 8 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x200) >> 9 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_FSM_RST(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x400) >> 10 +} +func (o *LP_I2C0_Type) SetI2C_CTR_I2C_CONF_UPGATE(value uint32) { + volatile.StoreUint32(&o.I2C_CTR.Reg, volatile.LoadUint32(&o.I2C_CTR.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C0_Type) GetI2C_CTR_I2C_CONF_UPGATE() uint32 { + return (volatile.LoadUint32(&o.I2C_CTR.Reg) & 0x800) >> 11 +} + +// LP_I2C0.I2C_SR: Describe I2C work status. +func (o *LP_I2C0_Type) SetI2C_SR_I2C_RESP_REC(value uint32) { + volatile.StoreUint32(&o.I2C_SR.Reg, volatile.LoadUint32(&o.I2C_SR.Reg)&^(0x1)|value) +} +func (o *LP_I2C0_Type) GetI2C_SR_I2C_RESP_REC() uint32 { + return volatile.LoadUint32(&o.I2C_SR.Reg) & 0x1 +} +func (o *LP_I2C0_Type) SetI2C_SR_I2C_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.I2C_SR.Reg, volatile.LoadUint32(&o.I2C_SR.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C0_Type) GetI2C_SR_I2C_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.I2C_SR.Reg) & 0x8) >> 3 +} +func (o *LP_I2C0_Type) SetI2C_SR_I2C_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.I2C_SR.Reg, volatile.LoadUint32(&o.I2C_SR.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C0_Type) GetI2C_SR_I2C_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.I2C_SR.Reg) & 0x10) >> 4 +} +func (o *LP_I2C0_Type) SetI2C_SR_I2C_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.I2C_SR.Reg, volatile.LoadUint32(&o.I2C_SR.Reg)&^(0x1f00)|value<<8) +} +func (o *LP_I2C0_Type) GetI2C_SR_I2C_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.I2C_SR.Reg) & 0x1f00) >> 8 +} +func (o *LP_I2C0_Type) SetI2C_SR_I2C_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.I2C_SR.Reg, volatile.LoadUint32(&o.I2C_SR.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_I2C0_Type) GetI2C_SR_I2C_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.I2C_SR.Reg) & 0x7c0000) >> 18 +} +func (o *LP_I2C0_Type) SetI2C_SR_I2C_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.I2C_SR.Reg, volatile.LoadUint32(&o.I2C_SR.Reg)&^(0x7000000)|value<<24) +} +func (o *LP_I2C0_Type) GetI2C_SR_I2C_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.I2C_SR.Reg) & 0x7000000) >> 24 +} +func (o *LP_I2C0_Type) SetI2C_SR_I2C_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.I2C_SR.Reg, volatile.LoadUint32(&o.I2C_SR.Reg)&^(0x70000000)|value<<28) +} +func (o *LP_I2C0_Type) GetI2C_SR_I2C_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.I2C_SR.Reg) & 0x70000000) >> 28 +} + +// LP_I2C0.I2C_TO: Setting time out control for receiving data. +func (o *LP_I2C0_Type) SetI2C_TO_I2C_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.I2C_TO.Reg, volatile.LoadUint32(&o.I2C_TO.Reg)&^(0x1f)|value) +} +func (o *LP_I2C0_Type) GetI2C_TO_I2C_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.I2C_TO.Reg) & 0x1f +} +func (o *LP_I2C0_Type) SetI2C_TO_I2C_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.I2C_TO.Reg, volatile.LoadUint32(&o.I2C_TO.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C0_Type) GetI2C_TO_I2C_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.I2C_TO.Reg) & 0x20) >> 5 +} + +// LP_I2C0.I2C_FIFO_ST: FIFO status register. +func (o *LP_I2C0_Type) SetI2C_FIFO_ST_I2C_RXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.I2C_FIFO_ST.Reg, volatile.LoadUint32(&o.I2C_FIFO_ST.Reg)&^(0xf)|value) +} +func (o *LP_I2C0_Type) GetI2C_FIFO_ST_I2C_RXFIFO_RADDR() uint32 { + return volatile.LoadUint32(&o.I2C_FIFO_ST.Reg) & 0xf +} +func (o *LP_I2C0_Type) SetI2C_FIFO_ST_I2C_RXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.I2C_FIFO_ST.Reg, volatile.LoadUint32(&o.I2C_FIFO_ST.Reg)&^(0x1e0)|value<<5) +} +func (o *LP_I2C0_Type) GetI2C_FIFO_ST_I2C_RXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.I2C_FIFO_ST.Reg) & 0x1e0) >> 5 +} +func (o *LP_I2C0_Type) SetI2C_FIFO_ST_I2C_TXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.I2C_FIFO_ST.Reg, volatile.LoadUint32(&o.I2C_FIFO_ST.Reg)&^(0x3c00)|value<<10) +} +func (o *LP_I2C0_Type) GetI2C_FIFO_ST_I2C_TXFIFO_RADDR() uint32 { + return (volatile.LoadUint32(&o.I2C_FIFO_ST.Reg) & 0x3c00) >> 10 +} +func (o *LP_I2C0_Type) SetI2C_FIFO_ST_I2C_TXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.I2C_FIFO_ST.Reg, volatile.LoadUint32(&o.I2C_FIFO_ST.Reg)&^(0x78000)|value<<15) +} +func (o *LP_I2C0_Type) GetI2C_FIFO_ST_I2C_TXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.I2C_FIFO_ST.Reg) & 0x78000) >> 15 +} + +// LP_I2C0.FIFO_CONF: FIFO configuration register. +func (o *LP_I2C0_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xf)|value) +} +func (o *LP_I2C0_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xf +} +func (o *LP_I2C0_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1e0)|value<<5) +} +func (o *LP_I2C0_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1e0) >> 5 +} +func (o *LP_I2C0_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C0_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *LP_I2C0_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C0_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C0_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C0_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C0_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C0_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14 +} + +// LP_I2C0.I2C_DATA: Rx FIFO read data. +func (o *LP_I2C0_Type) SetI2C_DATA_I2C_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.I2C_DATA.Reg, volatile.LoadUint32(&o.I2C_DATA.Reg)&^(0xff)|value) +} +func (o *LP_I2C0_Type) GetI2C_DATA_I2C_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.I2C_DATA.Reg) & 0xff +} + +// LP_I2C0.I2C_INT_RAW: Raw interrupt status +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x1)|value) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x1 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LP_I2C0_Type) SetI2C_INT_RAW_I2C_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2C_INT_RAW.Reg, volatile.LoadUint32(&o.I2C_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LP_I2C0_Type) GetI2C_INT_RAW_I2C_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_RAW.Reg) & 0x8000) >> 15 +} + +// LP_I2C0.I2C_INT_CLR: Interrupt clear bits +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x1)|value) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x1 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LP_I2C0_Type) SetI2C_INT_CLR_I2C_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2C_INT_CLR.Reg, volatile.LoadUint32(&o.I2C_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LP_I2C0_Type) GetI2C_INT_CLR_I2C_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_CLR.Reg) & 0x8000) >> 15 +} + +// LP_I2C0.I2C_INT_ENA: Interrupt enable bits +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x1)|value) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x1 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LP_I2C0_Type) SetI2C_INT_ENA_I2C_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2C_INT_ENA.Reg, volatile.LoadUint32(&o.I2C_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LP_I2C0_Type) GetI2C_INT_ENA_I2C_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_ENA.Reg) & 0x8000) >> 15 +} + +// LP_I2C0.I2C_INT_STATUS: Status of captured I2C communication events +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x1)|value) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x1 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *LP_I2C0_Type) SetI2C_INT_STATUS_I2C_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2C_INT_STATUS.Reg, volatile.LoadUint32(&o.I2C_INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *LP_I2C0_Type) GetI2C_INT_STATUS_I2C_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2C_INT_STATUS.Reg) & 0x8000) >> 15 +} + +// LP_I2C0.I2C_SDA_HOLD: Configures the hold time after a negative SCL edge. +func (o *LP_I2C0_Type) SetI2C_SDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.I2C_SDA_HOLD.Reg, volatile.LoadUint32(&o.I2C_SDA_HOLD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C0_Type) GetI2C_SDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.I2C_SDA_HOLD.Reg) & 0x1ff +} + +// LP_I2C0.I2C_SDA_SAMPLE: Configures the sample time after a positive SCL edge. +func (o *LP_I2C0_Type) SetI2C_SDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.I2C_SDA_SAMPLE.Reg, volatile.LoadUint32(&o.I2C_SDA_SAMPLE.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C0_Type) GetI2C_SDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.I2C_SDA_SAMPLE.Reg) & 0x1ff +} + +// LP_I2C0.I2C_SCL_HIGH_PERIOD: Configures the high level width of SCL +func (o *LP_I2C0_Type) SetI2C_SCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.I2C_SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C0_Type) GetI2C_SCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.I2C_SCL_HIGH_PERIOD.Reg) & 0x1ff +} +func (o *LP_I2C0_Type) SetI2C_SCL_HIGH_PERIOD_I2C_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.I2C_SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9) +} +func (o *LP_I2C0_Type) GetI2C_SCL_HIGH_PERIOD_I2C_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.I2C_SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9 +} + +// LP_I2C0.I2C_SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition +func (o *LP_I2C0_Type) SetI2C_SCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_START_HOLD.Reg, volatile.LoadUint32(&o.I2C_SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C0_Type) GetI2C_SCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.I2C_SCL_START_HOLD.Reg) & 0x1ff +} + +// LP_I2C0.I2C_SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA +func (o *LP_I2C0_Type) SetI2C_SCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.I2C_SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C0_Type) GetI2C_SCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.I2C_SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// LP_I2C0.I2C_SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition +func (o *LP_I2C0_Type) SetI2C_SCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.I2C_SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C0_Type) GetI2C_SCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.I2C_SCL_STOP_HOLD.Reg) & 0x1ff +} + +// LP_I2C0.I2C_SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition +func (o *LP_I2C0_Type) SetI2C_SCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.I2C_SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C0_Type) GetI2C_SCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.I2C_SCL_STOP_SETUP.Reg) & 0x1ff +} + +// LP_I2C0.I2C_FILTER_CFG: SCL and SDA filter configuration register +func (o *LP_I2C0_Type) SetI2C_FILTER_CFG_I2C_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.I2C_FILTER_CFG.Reg, volatile.LoadUint32(&o.I2C_FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *LP_I2C0_Type) GetI2C_FILTER_CFG_I2C_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.I2C_FILTER_CFG.Reg) & 0xf +} +func (o *LP_I2C0_Type) SetI2C_FILTER_CFG_I2C_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.I2C_FILTER_CFG.Reg, volatile.LoadUint32(&o.I2C_FILTER_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *LP_I2C0_Type) GetI2C_FILTER_CFG_I2C_SDA_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.I2C_FILTER_CFG.Reg) & 0xf0) >> 4 +} +func (o *LP_I2C0_Type) SetI2C_FILTER_CFG_I2C_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.I2C_FILTER_CFG.Reg, volatile.LoadUint32(&o.I2C_FILTER_CFG.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C0_Type) GetI2C_FILTER_CFG_I2C_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.I2C_FILTER_CFG.Reg) & 0x100) >> 8 +} +func (o *LP_I2C0_Type) SetI2C_FILTER_CFG_I2C_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.I2C_FILTER_CFG.Reg, volatile.LoadUint32(&o.I2C_FILTER_CFG.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C0_Type) GetI2C_FILTER_CFG_I2C_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.I2C_FILTER_CFG.Reg) & 0x200) >> 9 +} + +// LP_I2C0.I2C_CLK_CONF: I2C CLK configuration register +func (o *LP_I2C0_Type) SetI2C_CLK_CONF_I2C_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2C_CLK_CONF.Reg, volatile.LoadUint32(&o.I2C_CLK_CONF.Reg)&^(0xff)|value) +} +func (o *LP_I2C0_Type) GetI2C_CLK_CONF_I2C_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.I2C_CLK_CONF.Reg) & 0xff +} +func (o *LP_I2C0_Type) SetI2C_CLK_CONF_I2C_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.I2C_CLK_CONF.Reg, volatile.LoadUint32(&o.I2C_CLK_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *LP_I2C0_Type) GetI2C_CLK_CONF_I2C_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.I2C_CLK_CONF.Reg) & 0x3f00) >> 8 +} +func (o *LP_I2C0_Type) SetI2C_CLK_CONF_I2C_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.I2C_CLK_CONF.Reg, volatile.LoadUint32(&o.I2C_CLK_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *LP_I2C0_Type) GetI2C_CLK_CONF_I2C_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.I2C_CLK_CONF.Reg) & 0xfc000) >> 14 +} +func (o *LP_I2C0_Type) SetI2C_CLK_CONF_I2C_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.I2C_CLK_CONF.Reg, volatile.LoadUint32(&o.I2C_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *LP_I2C0_Type) GetI2C_CLK_CONF_I2C_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.I2C_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *LP_I2C0_Type) SetI2C_CLK_CONF_I2C_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.I2C_CLK_CONF.Reg, volatile.LoadUint32(&o.I2C_CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *LP_I2C0_Type) GetI2C_CLK_CONF_I2C_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.I2C_CLK_CONF.Reg) & 0x200000) >> 21 +} + +// LP_I2C0.I2C_COMD0: I2C command register 0 +func (o *LP_I2C0_Type) SetI2C_COMD0_I2C_COMMAND0(value uint32) { + volatile.StoreUint32(&o.I2C_COMD0.Reg, volatile.LoadUint32(&o.I2C_COMD0.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C0_Type) GetI2C_COMD0_I2C_COMMAND0() uint32 { + return volatile.LoadUint32(&o.I2C_COMD0.Reg) & 0x3fff +} +func (o *LP_I2C0_Type) SetI2C_COMD0_I2C_COMMAND0_DONE(value uint32) { + volatile.StoreUint32(&o.I2C_COMD0.Reg, volatile.LoadUint32(&o.I2C_COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C0_Type) GetI2C_COMD0_I2C_COMMAND0_DONE() uint32 { + return (volatile.LoadUint32(&o.I2C_COMD0.Reg) & 0x80000000) >> 31 +} + +// LP_I2C0.I2C_COMD1: I2C command register 1 +func (o *LP_I2C0_Type) SetI2C_COMD1_I2C_COMMAND1(value uint32) { + volatile.StoreUint32(&o.I2C_COMD1.Reg, volatile.LoadUint32(&o.I2C_COMD1.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C0_Type) GetI2C_COMD1_I2C_COMMAND1() uint32 { + return volatile.LoadUint32(&o.I2C_COMD1.Reg) & 0x3fff +} +func (o *LP_I2C0_Type) SetI2C_COMD1_I2C_COMMAND1_DONE(value uint32) { + volatile.StoreUint32(&o.I2C_COMD1.Reg, volatile.LoadUint32(&o.I2C_COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C0_Type) GetI2C_COMD1_I2C_COMMAND1_DONE() uint32 { + return (volatile.LoadUint32(&o.I2C_COMD1.Reg) & 0x80000000) >> 31 +} + +// LP_I2C0.I2C_COMD2: I2C command register 2 +func (o *LP_I2C0_Type) SetI2C_COMD2_I2C_COMMAND2(value uint32) { + volatile.StoreUint32(&o.I2C_COMD2.Reg, volatile.LoadUint32(&o.I2C_COMD2.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C0_Type) GetI2C_COMD2_I2C_COMMAND2() uint32 { + return volatile.LoadUint32(&o.I2C_COMD2.Reg) & 0x3fff +} +func (o *LP_I2C0_Type) SetI2C_COMD2_I2C_COMMAND2_DONE(value uint32) { + volatile.StoreUint32(&o.I2C_COMD2.Reg, volatile.LoadUint32(&o.I2C_COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C0_Type) GetI2C_COMD2_I2C_COMMAND2_DONE() uint32 { + return (volatile.LoadUint32(&o.I2C_COMD2.Reg) & 0x80000000) >> 31 +} + +// LP_I2C0.I2C_COMD3: I2C command register 3 +func (o *LP_I2C0_Type) SetI2C_COMD3_I2C_COMMAND3(value uint32) { + volatile.StoreUint32(&o.I2C_COMD3.Reg, volatile.LoadUint32(&o.I2C_COMD3.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C0_Type) GetI2C_COMD3_I2C_COMMAND3() uint32 { + return volatile.LoadUint32(&o.I2C_COMD3.Reg) & 0x3fff +} +func (o *LP_I2C0_Type) SetI2C_COMD3_I2C_COMMAND3_DONE(value uint32) { + volatile.StoreUint32(&o.I2C_COMD3.Reg, volatile.LoadUint32(&o.I2C_COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C0_Type) GetI2C_COMD3_I2C_COMMAND3_DONE() uint32 { + return (volatile.LoadUint32(&o.I2C_COMD3.Reg) & 0x80000000) >> 31 +} + +// LP_I2C0.I2C_COMD4: I2C command register 4 +func (o *LP_I2C0_Type) SetI2C_COMD4_I2C_COMMAND4(value uint32) { + volatile.StoreUint32(&o.I2C_COMD4.Reg, volatile.LoadUint32(&o.I2C_COMD4.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C0_Type) GetI2C_COMD4_I2C_COMMAND4() uint32 { + return volatile.LoadUint32(&o.I2C_COMD4.Reg) & 0x3fff +} +func (o *LP_I2C0_Type) SetI2C_COMD4_I2C_COMMAND4_DONE(value uint32) { + volatile.StoreUint32(&o.I2C_COMD4.Reg, volatile.LoadUint32(&o.I2C_COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C0_Type) GetI2C_COMD4_I2C_COMMAND4_DONE() uint32 { + return (volatile.LoadUint32(&o.I2C_COMD4.Reg) & 0x80000000) >> 31 +} + +// LP_I2C0.I2C_COMD5: I2C command register 5 +func (o *LP_I2C0_Type) SetI2C_COMD5_I2C_COMMAND5(value uint32) { + volatile.StoreUint32(&o.I2C_COMD5.Reg, volatile.LoadUint32(&o.I2C_COMD5.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C0_Type) GetI2C_COMD5_I2C_COMMAND5() uint32 { + return volatile.LoadUint32(&o.I2C_COMD5.Reg) & 0x3fff +} +func (o *LP_I2C0_Type) SetI2C_COMD5_I2C_COMMAND5_DONE(value uint32) { + volatile.StoreUint32(&o.I2C_COMD5.Reg, volatile.LoadUint32(&o.I2C_COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C0_Type) GetI2C_COMD5_I2C_COMMAND5_DONE() uint32 { + return (volatile.LoadUint32(&o.I2C_COMD5.Reg) & 0x80000000) >> 31 +} + +// LP_I2C0.I2C_COMD6: I2C command register 6 +func (o *LP_I2C0_Type) SetI2C_COMD6_I2C_COMMAND6(value uint32) { + volatile.StoreUint32(&o.I2C_COMD6.Reg, volatile.LoadUint32(&o.I2C_COMD6.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C0_Type) GetI2C_COMD6_I2C_COMMAND6() uint32 { + return volatile.LoadUint32(&o.I2C_COMD6.Reg) & 0x3fff +} +func (o *LP_I2C0_Type) SetI2C_COMD6_I2C_COMMAND6_DONE(value uint32) { + volatile.StoreUint32(&o.I2C_COMD6.Reg, volatile.LoadUint32(&o.I2C_COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C0_Type) GetI2C_COMD6_I2C_COMMAND6_DONE() uint32 { + return (volatile.LoadUint32(&o.I2C_COMD6.Reg) & 0x80000000) >> 31 +} + +// LP_I2C0.I2C_COMD7: I2C command register 7 +func (o *LP_I2C0_Type) SetI2C_COMD7_I2C_COMMAND7(value uint32) { + volatile.StoreUint32(&o.I2C_COMD7.Reg, volatile.LoadUint32(&o.I2C_COMD7.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C0_Type) GetI2C_COMD7_I2C_COMMAND7() uint32 { + return volatile.LoadUint32(&o.I2C_COMD7.Reg) & 0x3fff +} +func (o *LP_I2C0_Type) SetI2C_COMD7_I2C_COMMAND7_DONE(value uint32) { + volatile.StoreUint32(&o.I2C_COMD7.Reg, volatile.LoadUint32(&o.I2C_COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C0_Type) GetI2C_COMD7_I2C_COMMAND7_DONE() uint32 { + return (volatile.LoadUint32(&o.I2C_COMD7.Reg) & 0x80000000) >> 31 +} + +// LP_I2C0.I2C_SCL_ST_TIME_OUT: SCL status time out register +func (o *LP_I2C0_Type) SetI2C_SCL_ST_TIME_OUT_I2C_SCL_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.I2C_SCL_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *LP_I2C0_Type) GetI2C_SCL_ST_TIME_OUT_I2C_SCL_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.I2C_SCL_ST_TIME_OUT.Reg) & 0x1f +} + +// LP_I2C0.I2C_SCL_MAIN_ST_TIME_OUT: SCL main status time out register +func (o *LP_I2C0_Type) SetI2C_SCL_MAIN_ST_TIME_OUT_I2C_SCL_MAIN_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.I2C_SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *LP_I2C0_Type) GetI2C_SCL_MAIN_ST_TIME_OUT_I2C_SCL_MAIN_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.I2C_SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f +} + +// LP_I2C0.I2C_SCL_SP_CONF: Power configuration register +func (o *LP_I2C0_Type) SetI2C_SCL_SP_CONF_I2C_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_SP_CONF.Reg, volatile.LoadUint32(&o.I2C_SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *LP_I2C0_Type) GetI2C_SCL_SP_CONF_I2C_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.I2C_SCL_SP_CONF.Reg) & 0x1 +} +func (o *LP_I2C0_Type) SetI2C_SCL_SP_CONF_I2C_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_SP_CONF.Reg, volatile.LoadUint32(&o.I2C_SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *LP_I2C0_Type) GetI2C_SCL_SP_CONF_I2C_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2C_SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *LP_I2C0_Type) SetI2C_SCL_SP_CONF_I2C_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_SP_CONF.Reg, volatile.LoadUint32(&o.I2C_SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C0_Type) GetI2C_SCL_SP_CONF_I2C_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.I2C_SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *LP_I2C0_Type) SetI2C_SCL_SP_CONF_I2C_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.I2C_SCL_SP_CONF.Reg, volatile.LoadUint32(&o.I2C_SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C0_Type) GetI2C_SCL_SP_CONF_I2C_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.I2C_SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// LP_I2C0.I2C_DATE: Version register +func (o *LP_I2C0_Type) SetI2C_DATE(value uint32) { + volatile.StoreUint32(&o.I2C_DATE.Reg, value) +} +func (o *LP_I2C0_Type) GetI2C_DATE() uint32 { + return volatile.LoadUint32(&o.I2C_DATE.Reg) +} + +// LP_I2C0.I2C_TXFIFO_START_ADDR: I2C TXFIFO base address register +func (o *LP_I2C0_Type) SetI2C_TXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.I2C_TXFIFO_START_ADDR.Reg, value) +} +func (o *LP_I2C0_Type) GetI2C_TXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.I2C_TXFIFO_START_ADDR.Reg) +} + +// LP_I2C0.I2C_RXFIFO_START_ADDR: I2C RXFIFO base address register +func (o *LP_I2C0_Type) SetI2C_RXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.I2C_RXFIFO_START_ADDR.Reg, value) +} +func (o *LP_I2C0_Type) GetI2C_RXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.I2C_RXFIFO_START_ADDR.Reg) +} + +// LP_I2C_ANA_MST Peripheral +type LP_I2C_ANA_MST_Type struct { + I2C0_CTRL volatile.Register32 // 0x0 + I2C0_CONF volatile.Register32 // 0x4 + I2C0_DATA volatile.Register32 // 0x8 + ANA_CONF1 volatile.Register32 // 0xC + NOUSE volatile.Register32 // 0x10 + DEVICE_EN volatile.Register32 // 0x14 + _ [996]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_I2C_ANA_MST.I2C0_CTRL: need_des +func (o *LP_I2C_ANA_MST_Type) SetI2C0_CTRL_LP_I2C_ANA_MAST_I2C0_CTRL(value uint32) { + volatile.StoreUint32(&o.I2C0_CTRL.Reg, volatile.LoadUint32(&o.I2C0_CTRL.Reg)&^(0x1ffffff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_CTRL_LP_I2C_ANA_MAST_I2C0_CTRL() uint32 { + return volatile.LoadUint32(&o.I2C0_CTRL.Reg) & 0x1ffffff +} +func (o *LP_I2C_ANA_MST_Type) SetI2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY(value uint32) { + volatile.StoreUint32(&o.I2C0_CTRL.Reg, volatile.LoadUint32(&o.I2C0_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY() uint32 { + return (volatile.LoadUint32(&o.I2C0_CTRL.Reg) & 0x2000000) >> 25 +} + +// LP_I2C_ANA_MST.I2C0_CONF: need_des +func (o *LP_I2C_ANA_MST_Type) SetI2C0_CONF_LP_I2C_ANA_MAST_I2C0_CONF(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0xffffff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_CONF_LP_I2C_ANA_MAST_I2C0_CONF() uint32 { + return volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0xffffff +} +func (o *LP_I2C_ANA_MST_Type) SetI2C0_CONF_LP_I2C_ANA_MAST_I2C0_STATUS(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_CONF_LP_I2C_ANA_MAST_I2C0_STATUS() uint32 { + return (volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0xff000000) >> 24 +} + +// LP_I2C_ANA_MST.I2C0_DATA: need_des +func (o *LP_I2C_ANA_MST_Type) SetI2C0_DATA_LP_I2C_ANA_MAST_I2C0_RDATA(value uint32) { + volatile.StoreUint32(&o.I2C0_DATA.Reg, volatile.LoadUint32(&o.I2C0_DATA.Reg)&^(0xff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_DATA_LP_I2C_ANA_MAST_I2C0_RDATA() uint32 { + return volatile.LoadUint32(&o.I2C0_DATA.Reg) & 0xff +} +func (o *LP_I2C_ANA_MST_Type) SetI2C0_DATA_LP_I2C_ANA_MAST_I2C0_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.I2C0_DATA.Reg, volatile.LoadUint32(&o.I2C0_DATA.Reg)&^(0x700)|value<<8) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_DATA_LP_I2C_ANA_MAST_I2C0_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.I2C0_DATA.Reg) & 0x700) >> 8 +} +func (o *LP_I2C_ANA_MST_Type) SetI2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL(value uint32) { + volatile.StoreUint32(&o.I2C0_DATA.Reg, volatile.LoadUint32(&o.I2C0_DATA.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL() uint32 { + return (volatile.LoadUint32(&o.I2C0_DATA.Reg) & 0x800) >> 11 +} + +// LP_I2C_ANA_MST.ANA_CONF1: need_des +func (o *LP_I2C_ANA_MST_Type) SetANA_CONF1_LP_I2C_ANA_MAST_ANA_CONF1(value uint32) { + volatile.StoreUint32(&o.ANA_CONF1.Reg, volatile.LoadUint32(&o.ANA_CONF1.Reg)&^(0xffffff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetANA_CONF1_LP_I2C_ANA_MAST_ANA_CONF1() uint32 { + return volatile.LoadUint32(&o.ANA_CONF1.Reg) & 0xffffff +} + +// LP_I2C_ANA_MST.NOUSE: need_des +func (o *LP_I2C_ANA_MST_Type) SetNOUSE(value uint32) { + volatile.StoreUint32(&o.NOUSE.Reg, value) +} +func (o *LP_I2C_ANA_MST_Type) GetNOUSE() uint32 { + return volatile.LoadUint32(&o.NOUSE.Reg) +} + +// LP_I2C_ANA_MST.DEVICE_EN: need_des +func (o *LP_I2C_ANA_MST_Type) SetDEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_EN.Reg, volatile.LoadUint32(&o.DEVICE_EN.Reg)&^(0xfff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetDEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN() uint32 { + return volatile.LoadUint32(&o.DEVICE_EN.Reg) & 0xfff +} + +// LP_I2C_ANA_MST.DATE: need_des +func (o *LP_I2C_ANA_MST_Type) SetDATE_LP_I2C_ANA_MAST_I2C_MAT_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetDATE_LP_I2C_ANA_MAST_I2C_MAT_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} +func (o *LP_I2C_ANA_MST_Type) SetDATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_I2C_ANA_MST_Type) GetDATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x10000000) >> 28 +} + +// LP_IO Peripheral +type LP_IO_Type struct { + OUT_DATA volatile.Register32 // 0x0 + OUT_DATA_W1TS volatile.Register32 // 0x4 + OUT_DATA_W1TC volatile.Register32 // 0x8 + OUT_ENABLE volatile.Register32 // 0xC + OUT_ENABLE_W1TS volatile.Register32 // 0x10 + OUT_ENABLE_W1TC volatile.Register32 // 0x14 + STATUS volatile.Register32 // 0x18 + STATUS_W1TS volatile.Register32 // 0x1C + STATUS_W1TC volatile.Register32 // 0x20 + IN volatile.Register32 // 0x24 + PIN0 volatile.Register32 // 0x28 + PIN1 volatile.Register32 // 0x2C + PIN2 volatile.Register32 // 0x30 + PIN3 volatile.Register32 // 0x34 + PIN4 volatile.Register32 // 0x38 + PIN5 volatile.Register32 // 0x3C + PIN6 volatile.Register32 // 0x40 + PIN7 volatile.Register32 // 0x44 + GPIO0 volatile.Register32 // 0x48 + GPIO1 volatile.Register32 // 0x4C + GPIO2 volatile.Register32 // 0x50 + GPIO3 volatile.Register32 // 0x54 + GPIO4 volatile.Register32 // 0x58 + GPIO5 volatile.Register32 // 0x5C + GPIO6 volatile.Register32 // 0x60 + GPIO7 volatile.Register32 // 0x64 + STATUS_INTERRUPT volatile.Register32 // 0x68 + DEBUG_SEL0 volatile.Register32 // 0x6C + DEBUG_SEL1 volatile.Register32 // 0x70 + LPI2C volatile.Register32 // 0x74 + _ [900]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_IO.OUT_DATA: need des +func (o *LP_IO_Type) SetOUT_DATA_LP_GPIO_OUT_DATA(value uint32) { + volatile.StoreUint32(&o.OUT_DATA.Reg, volatile.LoadUint32(&o.OUT_DATA.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_DATA_LP_GPIO_OUT_DATA() uint32 { + return volatile.LoadUint32(&o.OUT_DATA.Reg) & 0xff +} + +// LP_IO.OUT_DATA_W1TS: need des +func (o *LP_IO_Type) SetOUT_DATA_W1TS_LP_GPIO_OUT_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_DATA_W1TS.Reg, volatile.LoadUint32(&o.OUT_DATA_W1TS.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_DATA_W1TS_LP_GPIO_OUT_DATA_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_DATA_W1TS.Reg) & 0xff +} + +// LP_IO.OUT_DATA_W1TC: need des +func (o *LP_IO_Type) SetOUT_DATA_W1TC_LP_GPIO_OUT_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_DATA_W1TC.Reg, volatile.LoadUint32(&o.OUT_DATA_W1TC.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_DATA_W1TC_LP_GPIO_OUT_DATA_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_DATA_W1TC.Reg) & 0xff +} + +// LP_IO.OUT_ENABLE: need des +func (o *LP_IO_Type) SetOUT_ENABLE_LP_GPIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.OUT_ENABLE.Reg, volatile.LoadUint32(&o.OUT_ENABLE.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_ENABLE_LP_GPIO_ENABLE() uint32 { + return volatile.LoadUint32(&o.OUT_ENABLE.Reg) & 0xff +} + +// LP_IO.OUT_ENABLE_W1TS: need des +func (o *LP_IO_Type) SetOUT_ENABLE_W1TS_LP_GPIO_ENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_ENABLE_W1TS.Reg, volatile.LoadUint32(&o.OUT_ENABLE_W1TS.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_ENABLE_W1TS_LP_GPIO_ENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_ENABLE_W1TS.Reg) & 0xff +} + +// LP_IO.OUT_ENABLE_W1TC: need des +func (o *LP_IO_Type) SetOUT_ENABLE_W1TC_LP_GPIO_ENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_ENABLE_W1TC.Reg, volatile.LoadUint32(&o.OUT_ENABLE_W1TC.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_ENABLE_W1TC_LP_GPIO_ENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_ENABLE_W1TC.Reg) & 0xff +} + +// LP_IO.STATUS: need des +func (o *LP_IO_Type) SetSTATUS_LP_GPIO_STATUS_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetSTATUS_LP_GPIO_STATUS_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xff +} + +// LP_IO.STATUS_W1TS: need des +func (o *LP_IO_Type) SetSTATUS_W1TS_LP_GPIO_STATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, volatile.LoadUint32(&o.STATUS_W1TS.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetSTATUS_W1TS_LP_GPIO_STATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) & 0xff +} + +// LP_IO.STATUS_W1TC: need des +func (o *LP_IO_Type) SetSTATUS_W1TC_LP_GPIO_STATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, volatile.LoadUint32(&o.STATUS_W1TC.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetSTATUS_W1TC_LP_GPIO_STATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) & 0xff +} + +// LP_IO.IN: need des +func (o *LP_IO_Type) SetIN_LP_GPIO_IN_DATA_NEXT(value uint32) { + volatile.StoreUint32(&o.IN.Reg, volatile.LoadUint32(&o.IN.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetIN_LP_GPIO_IN_DATA_NEXT() uint32 { + return volatile.LoadUint32(&o.IN.Reg) & 0xff +} + +// LP_IO.PIN0: need des +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN1: need des +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN2: need des +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN3: need des +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN4: need des +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN5: need des +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN6: need des +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN7: need des +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x800) >> 11 +} + +// LP_IO.GPIO0: need des +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO1: need des +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO2: need des +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO3: need des +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO4: need des +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO5: need des +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO6: need des +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO7: need des +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} + +// LP_IO.STATUS_INTERRUPT: need des +func (o *LP_IO_Type) SetSTATUS_INTERRUPT_LP_GPIO_STATUS_INTERRUPT_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_INTERRUPT.Reg, volatile.LoadUint32(&o.STATUS_INTERRUPT.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetSTATUS_INTERRUPT_LP_GPIO_STATUS_INTERRUPT_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_INTERRUPT.Reg) & 0xff +} + +// LP_IO.DEBUG_SEL0: need des +func (o *LP_IO_Type) SetDEBUG_SEL0_LP_DEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0x7f)|value) +} +func (o *LP_IO_Type) GetDEBUG_SEL0_LP_DEBUG_SEL0() uint32 { + return volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0x7f +} +func (o *LP_IO_Type) SetDEBUG_SEL0_LP_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0x3f80)|value<<7) +} +func (o *LP_IO_Type) GetDEBUG_SEL0_LP_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0x3f80) >> 7 +} +func (o *LP_IO_Type) SetDEBUG_SEL0_LP_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0x1fc000)|value<<14) +} +func (o *LP_IO_Type) GetDEBUG_SEL0_LP_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0x1fc000) >> 14 +} +func (o *LP_IO_Type) SetDEBUG_SEL0_LP_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0xfe00000)|value<<21) +} +func (o *LP_IO_Type) GetDEBUG_SEL0_LP_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0xfe00000) >> 21 +} + +// LP_IO.DEBUG_SEL1: need des +func (o *LP_IO_Type) SetDEBUG_SEL1_LP_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL1.Reg, volatile.LoadUint32(&o.DEBUG_SEL1.Reg)&^(0x7f)|value) +} +func (o *LP_IO_Type) GetDEBUG_SEL1_LP_DEBUG_SEL4() uint32 { + return volatile.LoadUint32(&o.DEBUG_SEL1.Reg) & 0x7f +} + +// LP_IO.LPI2C: need des +func (o *LP_IO_Type) SetLPI2C_LP_I2C_SDA_IE(value uint32) { + volatile.StoreUint32(&o.LPI2C.Reg, volatile.LoadUint32(&o.LPI2C.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_IO_Type) GetLPI2C_LP_I2C_SDA_IE() uint32 { + return (volatile.LoadUint32(&o.LPI2C.Reg) & 0x40000000) >> 30 +} +func (o *LP_IO_Type) SetLPI2C_LP_I2C_SCL_IE(value uint32) { + volatile.StoreUint32(&o.LPI2C.Reg, volatile.LoadUint32(&o.LPI2C.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_IO_Type) GetLPI2C_LP_I2C_SCL_IE() uint32 { + return (volatile.LoadUint32(&o.LPI2C.Reg) & 0x80000000) >> 31 +} + +// LP_IO.DATE: need des +func (o *LP_IO_Type) SetDATE_LP_IO_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_IO_Type) GetDATE_LP_IO_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_IO_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_IO_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power Trusted Execution Environment +type LP_TEE_Type struct { + M0_MODE_CTRL volatile.Register32 // 0x0 + CLOCK_GATE volatile.Register32 // 0x4 + _ [136]byte + FORCE_ACC_HP volatile.Register32 // 0x90 + _ [104]byte + DATE volatile.Register32 // 0xFC +} + +// LP_TEE.M0_MODE_CTRL: Tee mode control register +func (o *LP_TEE_Type) SetM0_MODE_CTRL_M0_MODE(value uint32) { + volatile.StoreUint32(&o.M0_MODE_CTRL.Reg, volatile.LoadUint32(&o.M0_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *LP_TEE_Type) GetM0_MODE_CTRL_M0_MODE() uint32 { + return volatile.LoadUint32(&o.M0_MODE_CTRL.Reg) & 0x3 +} + +// LP_TEE.CLOCK_GATE: Clock gating register +func (o *LP_TEE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *LP_TEE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// LP_TEE.FORCE_ACC_HP: need_des +func (o *LP_TEE_Type) SetFORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN(value uint32) { + volatile.StoreUint32(&o.FORCE_ACC_HP.Reg, volatile.LoadUint32(&o.FORCE_ACC_HP.Reg)&^(0x1)|value) +} +func (o *LP_TEE_Type) GetFORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN() uint32 { + return volatile.LoadUint32(&o.FORCE_ACC_HP.Reg) & 0x1 +} + +// LP_TEE.DATE: Version register +func (o *LP_TEE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_TEE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power Timer +type LP_TIMER_Type struct { + TAR0_LOW volatile.Register32 // 0x0 + TAR0_HIGH volatile.Register32 // 0x4 + TAR1_LOW volatile.Register32 // 0x8 + TAR1_HIGH volatile.Register32 // 0xC + UPDATE volatile.Register32 // 0x10 + MAIN_BUF0_LOW volatile.Register32 // 0x14 + MAIN_BUF0_HIGH volatile.Register32 // 0x18 + MAIN_BUF1_LOW volatile.Register32 // 0x1C + MAIN_BUF1_HIGH volatile.Register32 // 0x20 + MAIN_OVERFLOW volatile.Register32 // 0x24 + INT_RAW volatile.Register32 // 0x28 + INT_ST volatile.Register32 // 0x2C + INT_ENA volatile.Register32 // 0x30 + INT_CLR volatile.Register32 // 0x34 + LP_INT_RAW volatile.Register32 // 0x38 + LP_INT_ST volatile.Register32 // 0x3C + LP_INT_ENA volatile.Register32 // 0x40 + LP_INT_CLR volatile.Register32 // 0x44 + _ [948]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_TIMER.TAR0_LOW: need_des +func (o *LP_TIMER_Type) SetTAR0_LOW(value uint32) { + volatile.StoreUint32(&o.TAR0_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetTAR0_LOW() uint32 { + return volatile.LoadUint32(&o.TAR0_LOW.Reg) +} + +// LP_TIMER.TAR0_HIGH: need_des +func (o *LP_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0(value uint32) { + volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0() uint32 { + return volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0xffff +} +func (o *LP_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_EN0(value uint32) { + volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_EN0() uint32 { + return (volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.TAR1_LOW: need_des +func (o *LP_TIMER_Type) SetTAR1_LOW(value uint32) { + volatile.StoreUint32(&o.TAR1_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetTAR1_LOW() uint32 { + return volatile.LoadUint32(&o.TAR1_LOW.Reg) +} + +// LP_TIMER.TAR1_HIGH: need_des +func (o *LP_TIMER_Type) SetTAR1_HIGH_MAIN_TIMER_TAR_HIGH1(value uint32) { + volatile.StoreUint32(&o.TAR1_HIGH.Reg, volatile.LoadUint32(&o.TAR1_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetTAR1_HIGH_MAIN_TIMER_TAR_HIGH1() uint32 { + return volatile.LoadUint32(&o.TAR1_HIGH.Reg) & 0xffff +} +func (o *LP_TIMER_Type) SetTAR1_HIGH_MAIN_TIMER_TAR_EN1(value uint32) { + volatile.StoreUint32(&o.TAR1_HIGH.Reg, volatile.LoadUint32(&o.TAR1_HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetTAR1_HIGH_MAIN_TIMER_TAR_EN1() uint32 { + return (volatile.LoadUint32(&o.TAR1_HIGH.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.UPDATE: need_des +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_UPDATE(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x10000000) >> 28 +} +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_XTAL_OFF(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_XTAL_OFF() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x20000000) >> 29 +} +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_STALL(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_STALL() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_RST(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.MAIN_BUF0_LOW: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF0_LOW(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF0_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF0_LOW() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF0_LOW.Reg) +} + +// LP_TIMER.MAIN_BUF0_HIGH: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF0_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg) & 0xffff +} + +// LP_TIMER.MAIN_BUF1_LOW: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF1_LOW(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF1_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF1_LOW() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF1_LOW.Reg) +} + +// LP_TIMER.MAIN_BUF1_HIGH: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF1_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg) & 0xffff +} + +// LP_TIMER.MAIN_OVERFLOW: need_des +func (o *LP_TIMER_Type) SetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD(value uint32) { + volatile.StoreUint32(&o.MAIN_OVERFLOW.Reg, volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD() uint32 { + return (volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_RAW: need_des +func (o *LP_TIMER_Type) SetINT_RAW_OVERFLOW_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_RAW_OVERFLOW_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_RAW_SOC_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_RAW_SOC_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_ST: need_des +func (o *LP_TIMER_Type) SetINT_ST_OVERFLOW_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_ST_OVERFLOW_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_ST_SOC_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_ST_SOC_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_ENA: need_des +func (o *LP_TIMER_Type) SetINT_ENA_OVERFLOW_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_ENA_OVERFLOW_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_ENA_SOC_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_ENA_SOC_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_CLR: need_des +func (o *LP_TIMER_Type) SetINT_CLR_OVERFLOW_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_CLR_OVERFLOW_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_CLR_SOC_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_CLR_SOC_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.LP_INT_RAW: need_des +func (o *LP_TIMER_Type) SetLP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetLP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetLP_INT_RAW_MAIN_TIMER_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetLP_INT_RAW_MAIN_TIMER_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.LP_INT_ST: need_des +func (o *LP_TIMER_Type) SetLP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetLP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetLP_INT_ST_MAIN_TIMER_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetLP_INT_ST_MAIN_TIMER_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.LP_INT_ENA: need_des +func (o *LP_TIMER_Type) SetLP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetLP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetLP_INT_ENA_MAIN_TIMER_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetLP_INT_ENA_MAIN_TIMER_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.LP_INT_CLR: need_des +func (o *LP_TIMER_Type) SetLP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetLP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetLP_INT_CLR_MAIN_TIMER_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetLP_INT_CLR_MAIN_TIMER_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.DATE: need_des +func (o *LP_TIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_TIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_TIMER_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller +type LP_UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV volatile.Register32 // 0x14 + RX_FILT volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0 volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + _ [4]byte + HWFC_CONF volatile.Register32 // 0x2C + SLEEP_CONF0 volatile.Register32 // 0x30 + SLEEP_CONF1 volatile.Register32 // 0x34 + SLEEP_CONF2 volatile.Register32 // 0x38 + SWFC_CONF0 volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + TXBRK_CONF volatile.Register32 // 0x44 + IDLE_CONF volatile.Register32 // 0x48 + RS485_CONF volatile.Register32 // 0x4C + AT_CMD_PRECNT volatile.Register32 // 0x50 + AT_CMD_POSTCNT volatile.Register32 // 0x54 + AT_CMD_GAPTOUT volatile.Register32 // 0x58 + AT_CMD_CHAR volatile.Register32 // 0x5C + MEM_CONF volatile.Register32 // 0x60 + TOUT_CONF volatile.Register32 // 0x64 + MEM_TX_STATUS volatile.Register32 // 0x68 + MEM_RX_STATUS volatile.Register32 // 0x6C + FSM_STATUS volatile.Register32 // 0x70 + _ [20]byte + CLK_CONF volatile.Register32 // 0x88 + DATE volatile.Register32 // 0x8C + AFIFO_STATUS volatile.Register32 // 0x90 + _ [4]byte + REG_UPDATE volatile.Register32 // 0x98 + ID volatile.Register32 // 0x9C +} + +// LP_UART.FIFO: FIFO data register +func (o *LP_UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// LP_UART.INT_RAW: Raw interrupt status +func (o *LP_UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// LP_UART.INT_ST: Masked interrupt status +func (o *LP_UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// LP_UART.INT_ENA: Interrupt enable bits +func (o *LP_UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// LP_UART.INT_CLR: Interrupt clear bits +func (o *LP_UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// LP_UART.CLKDIV: Clock divider configuration +func (o *LP_UART_Type) SetCLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xfff)|value) +} +func (o *LP_UART_Type) GetCLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xfff +} +func (o *LP_UART_Type) SetCLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xf00000)|value<<20) +} +func (o *LP_UART_Type) GetCLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xf00000) >> 20 +} + +// LP_UART.RX_FILT: Rx Filter configuration +func (o *LP_UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetRX_FILT_GLITCH_FILT() uint32 { + return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff +} +func (o *LP_UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8 +} + +// LP_UART.STATUS: UART status register +func (o *LP_UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *LP_UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *LP_UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf80000)|value<<19) +} +func (o *LP_UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf80000) >> 19 +} +func (o *LP_UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *LP_UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *LP_UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// LP_UART.CONF0: Configuration register 0 +func (o *LP_UART_Type) SetCONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetCONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *LP_UART_Type) SetCONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetCONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetCONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0xc)|value<<2) +} +func (o *LP_UART_Type) GetCONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0xc) >> 2 +} +func (o *LP_UART_Type) SetCONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x30)|value<<4) +} +func (o *LP_UART_Type) GetCONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x30) >> 4 +} +func (o *LP_UART_Type) SetCONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetCONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetCONF0_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetCONF0_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetCONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetCONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetCONF0_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LP_UART_Type) GetCONF0_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *LP_UART_Type) SetCONF0_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LP_UART_Type) GetCONF0_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *LP_UART_Type) SetCONF0_DIS_RX_DAT_OVF(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LP_UART_Type) GetCONF0_DIS_RX_DAT_OVF() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *LP_UART_Type) SetCONF0_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetCONF0_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetCONF0_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *LP_UART_Type) GetCONF0_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *LP_UART_Type) SetCONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *LP_UART_Type) GetCONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *LP_UART_Type) SetCONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *LP_UART_Type) GetCONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *LP_UART_Type) SetCONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *LP_UART_Type) GetCONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} + +// LP_UART.CONF1: Configuration register 1 +func (o *LP_UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xf800)|value<<11) +} +func (o *LP_UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xf800) >> 11 +} +func (o *LP_UART_Type) SetCONF1_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *LP_UART_Type) GetCONF1_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10000) >> 16 +} +func (o *LP_UART_Type) SetCONF1_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *LP_UART_Type) GetCONF1_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000) >> 17 +} +func (o *LP_UART_Type) SetCONF1_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetCONF1_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetCONF1_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetCONF1_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19 +} +func (o *LP_UART_Type) SetCONF1_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *LP_UART_Type) GetCONF1_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *LP_UART_Type) SetCONF1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *LP_UART_Type) GetCONF1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} + +// LP_UART.HWFC_CONF: Hardware flow-control configuration +func (o *LP_UART_Type) SetHWFC_CONF_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF.Reg, volatile.LoadUint32(&o.HWFC_CONF.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetHWFC_CONF_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.HWFC_CONF.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetHWFC_CONF_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF.Reg, volatile.LoadUint32(&o.HWFC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetHWFC_CONF_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.HWFC_CONF.Reg) & 0x100) >> 8 +} + +// LP_UART.SLEEP_CONF0: UART sleep configure register 0 +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR1(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR1() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff +} +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR2(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR2() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff00) >> 8 +} +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR3(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR3() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff0000) >> 16 +} +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR4(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff000000)|value<<24) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR4() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff000000) >> 24 +} + +// LP_UART.SLEEP_CONF1: UART sleep configure register 1 +func (o *LP_UART_Type) SetSLEEP_CONF1_WK_CHAR0(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF1.Reg, volatile.LoadUint32(&o.SLEEP_CONF1.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetSLEEP_CONF1_WK_CHAR0() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF1.Reg) & 0xff +} + +// LP_UART.SLEEP_CONF2: UART sleep configure register 2 +func (o *LP_UART_Type) SetSLEEP_CONF2_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3ff)|value) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3ff +} +func (o *LP_UART_Type) SetSLEEP_CONF2_RX_WAKE_UP_THRHD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e000)|value<<13) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_RX_WAKE_UP_THRHD() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e000) >> 13 +} +func (o *LP_UART_Type) SetSLEEP_CONF2_WK_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x1c0000)|value<<18) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_WK_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x1c0000) >> 18 +} +func (o *LP_UART_Type) SetSLEEP_CONF2_WK_CHAR_MASK(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e00000)|value<<21) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_WK_CHAR_MASK() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e00000) >> 21 +} +func (o *LP_UART_Type) SetSLEEP_CONF2_WK_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0xc000000)|value<<26) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_WK_MODE_SEL() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0xc000000) >> 26 +} + +// LP_UART.SWFC_CONF0: Software flow-control character configuration +func (o *LP_UART_Type) SetSWFC_CONF0_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetSWFC_CONF0_XON_CHAR() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0xff +} +func (o *LP_UART_Type) SetSWFC_CONF0_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *LP_UART_Type) GetSWFC_CONF0_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *LP_UART_Type) SetSWFC_CONF0_XON_XOFF_STILL_SEND(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LP_UART_Type) GetSWFC_CONF0_XON_XOFF_STILL_SEND() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SW_FLOW_CON_EN() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x20000) >> 17 +} +func (o *LP_UART_Type) SetSWFC_CONF0_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetSWFC_CONF0_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetSWFC_CONF0_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetSWFC_CONF0_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x80000) >> 19 +} +func (o *LP_UART_Type) SetSWFC_CONF0_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *LP_UART_Type) GetSWFC_CONF0_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x100000) >> 20 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SEND_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x200000) >> 21 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x400000) >> 22 +} + +// LP_UART.SWFC_CONF1: Software flow-control character configuration +func (o *LP_UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetSWFC_CONF1_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xf800)|value<<11) +} +func (o *LP_UART_Type) GetSWFC_CONF1_XOFF_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xf800) >> 11 +} + +// LP_UART.TXBRK_CONF: Tx Break character configuration +func (o *LP_UART_Type) SetTXBRK_CONF_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.TXBRK_CONF.Reg, volatile.LoadUint32(&o.TXBRK_CONF.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetTXBRK_CONF_TX_BRK_NUM() uint32 { + return volatile.LoadUint32(&o.TXBRK_CONF.Reg) & 0xff +} + +// LP_UART.IDLE_CONF: Frame-end idle configuration +func (o *LP_UART_Type) SetIDLE_CONF_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0x3ff)|value) +} +func (o *LP_UART_Type) GetIDLE_CONF_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0x3ff +} +func (o *LP_UART_Type) SetIDLE_CONF_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *LP_UART_Type) GetIDLE_CONF_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xffc00) >> 10 +} + +// LP_UART.RS485_CONF: RS485 mode configuration +func (o *LP_UART_Type) SetRS485_CONF_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetRS485_CONF_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetRS485_CONF_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetRS485_CONF_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x4) >> 2 +} + +// LP_UART.AT_CMD_PRECNT: Pre-sequence timing configuration +func (o *LP_UART_Type) SetAT_CMD_PRECNT_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg)&^(0xffff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_PRECNT_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg) & 0xffff +} + +// LP_UART.AT_CMD_POSTCNT: Post-sequence timing configuration +func (o *LP_UART_Type) SetAT_CMD_POSTCNT_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg)&^(0xffff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_POSTCNT_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg) & 0xffff +} + +// LP_UART.AT_CMD_GAPTOUT: Timeout configuration +func (o *LP_UART_Type) SetAT_CMD_GAPTOUT_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg)&^(0xffff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_GAPTOUT_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg) & 0xffff +} + +// LP_UART.AT_CMD_CHAR: AT escape sequence detection configuration +func (o *LP_UART_Type) SetAT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff +} +func (o *LP_UART_Type) SetAT_CMD_CHAR_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff00)|value<<8) +} +func (o *LP_UART_Type) GetAT_CMD_CHAR_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff00) >> 8 +} + +// LP_UART.MEM_CONF: UART memory power configuration +func (o *LP_UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LP_UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26 +} + +// LP_UART.TOUT_CONF: UART threshold and allocation configuration +func (o *LP_UART_Type) SetTOUT_CONF_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF.Reg, volatile.LoadUint32(&o.TOUT_CONF.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetTOUT_CONF_RX_TOUT_EN() uint32 { + return volatile.LoadUint32(&o.TOUT_CONF.Reg) & 0x1 +} +func (o *LP_UART_Type) SetTOUT_CONF_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF.Reg, volatile.LoadUint32(&o.TOUT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetTOUT_CONF_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetTOUT_CONF_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF.Reg, volatile.LoadUint32(&o.TOUT_CONF.Reg)&^(0xffc)|value<<2) +} +func (o *LP_UART_Type) GetTOUT_CONF_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF.Reg) & 0xffc) >> 2 +} + +// LP_UART.MEM_TX_STATUS: Tx-SRAM write and read offset address. +func (o *LP_UART_Type) SetMEM_TX_STATUS_TX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetMEM_TX_STATUS_TX_SRAM_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetMEM_TX_STATUS_TX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1f000)|value<<12) +} +func (o *LP_UART_Type) GetMEM_TX_STATUS_TX_SRAM_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1f000) >> 12 +} + +// LP_UART.MEM_RX_STATUS: Rx-SRAM write and read offset address. +func (o *LP_UART_Type) SetMEM_RX_STATUS_RX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetMEM_RX_STATUS_RX_SRAM_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetMEM_RX_STATUS_RX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1f000)|value<<12) +} +func (o *LP_UART_Type) GetMEM_RX_STATUS_RX_SRAM_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1f000) >> 12 +} + +// LP_UART.FSM_STATUS: UART transmit and receive status. +func (o *LP_UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *LP_UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *LP_UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *LP_UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// LP_UART.CLK_CONF: UART core clock configuration +func (o *LP_UART_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f)|value) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f +} +func (o *LP_UART_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *LP_UART_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *LP_UART_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *LP_UART_Type) SetCLK_CONF_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *LP_UART_Type) SetCLK_CONF_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LP_UART_Type) GetCLK_CONF_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x800000) >> 23 +} +func (o *LP_UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LP_UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LP_UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LP_UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *LP_UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} + +// LP_UART.DATE: UART Version register +func (o *LP_UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *LP_UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// LP_UART.AFIFO_STATUS: UART AFIFO Status +func (o *LP_UART_Type) SetAFIFO_STATUS_TX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_TX_AFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x1 +} +func (o *LP_UART_Type) SetAFIFO_STATUS_TX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_TX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetAFIFO_STATUS_RX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_RX_AFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetAFIFO_STATUS_RX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_RX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x8) >> 3 +} + +// LP_UART.REG_UPDATE: UART Registers Configuration Update register +func (o *LP_UART_Type) SetREG_UPDATE(value uint32) { + volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetREG_UPDATE() uint32 { + return volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x1 +} + +// LP_UART.ID: UART ID register +func (o *LP_UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, value) +} +func (o *LP_UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) +} + +// Low-power Watchdog Timer +type LP_WDT_Type struct { + WDTCONFIG0 volatile.Register32 // 0x0 + CONFIG1 volatile.Register32 // 0x4 + CONFIG2 volatile.Register32 // 0x8 + CONFIG3 volatile.Register32 // 0xC + CONFIG4 volatile.Register32 // 0x10 + WDTFEED volatile.Register32 // 0x14 + WDTWPROTECT volatile.Register32 // 0x18 + SWD_CONF volatile.Register32 // 0x1C + SWD_WPROTECT volatile.Register32 // 0x20 + INT_RAW volatile.Register32 // 0x24 + INT_ST_RTC volatile.Register32 // 0x28 + INT_ENA_RTC volatile.Register32 // 0x2C + INT_CLR_RTC volatile.Register32 // 0x30 + _ [968]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_WDT.WDTCONFIG0: need_des +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_CHIP_RESET_WIDTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xff)|value) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_CHIP_RESET_WIDTH() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xff +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_CHIP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x100)|value<<8) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_CHIP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x100) >> 8 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_PAUSE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200)|value<<9) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_PAUSE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200) >> 9 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400)|value<<10) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400) >> 10 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x800)|value<<11) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x800) >> 11 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000)|value<<13) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000) >> 13 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000)|value<<16) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000) >> 16 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x380000)|value<<19) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x380000) >> 19 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c00000) >> 22 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000000)|value<<25) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000000) >> 25 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000000)|value<<28) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000000) >> 28 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.CONFIG1: need_des +func (o *LP_WDT_Type) SetCONFIG1(value uint32) { + volatile.StoreUint32(&o.CONFIG1.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG1() uint32 { + return volatile.LoadUint32(&o.CONFIG1.Reg) +} + +// LP_WDT.CONFIG2: need_des +func (o *LP_WDT_Type) SetCONFIG2(value uint32) { + volatile.StoreUint32(&o.CONFIG2.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG2() uint32 { + return volatile.LoadUint32(&o.CONFIG2.Reg) +} + +// LP_WDT.CONFIG3: need_des +func (o *LP_WDT_Type) SetCONFIG3(value uint32) { + volatile.StoreUint32(&o.CONFIG3.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG3() uint32 { + return volatile.LoadUint32(&o.CONFIG3.Reg) +} + +// LP_WDT.CONFIG4: need_des +func (o *LP_WDT_Type) SetCONFIG4(value uint32) { + volatile.StoreUint32(&o.CONFIG4.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG4() uint32 { + return volatile.LoadUint32(&o.CONFIG4.Reg) +} + +// LP_WDT.WDTFEED: need_des +func (o *LP_WDT_Type) SetWDTFEED_RTC_WDT_FEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, volatile.LoadUint32(&o.WDTFEED.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetWDTFEED_RTC_WDT_FEED() uint32 { + return (volatile.LoadUint32(&o.WDTFEED.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.WDTWPROTECT: need_des +func (o *LP_WDT_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *LP_WDT_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// LP_WDT.SWD_CONF: need_des +func (o *LP_WDT_Type) SetSWD_CONF_SWD_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x1)|value) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_RESET_FLAG() uint32 { + return volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x1 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_AUTO_FEED_EN(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_AUTO_FEED_EN() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x40000) >> 18 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_RST_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_RST_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x80000) >> 19 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_SIGNAL_WIDTH(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_SIGNAL_WIDTH() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x3ff00000) >> 20 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_DISABLE(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_FEED(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_FEED() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.SWD_WPROTECT: need_des +func (o *LP_WDT_Type) SetSWD_WPROTECT(value uint32) { + volatile.StoreUint32(&o.SWD_WPROTECT.Reg, value) +} +func (o *LP_WDT_Type) GetSWD_WPROTECT() uint32 { + return volatile.LoadUint32(&o.SWD_WPROTECT.Reg) +} + +// LP_WDT.INT_RAW: need_des +func (o *LP_WDT_Type) SetINT_RAW_SUPER_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_RAW_SUPER_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_RAW_LP_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_RAW_LP_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.INT_ST_RTC: need_des +func (o *LP_WDT_Type) SetINT_ST_RTC_SUPER_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_ST_RTC_SUPER_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_ST_RTC_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_ST_RTC_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.INT_ENA_RTC: need_des +func (o *LP_WDT_Type) SetINT_ENA_RTC_SUPER_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_ENA_RTC_SUPER_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_ENA_RTC_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_ENA_RTC_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.INT_CLR_RTC: need_des +func (o *LP_WDT_Type) SetINT_CLR_RTC_SUPER_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_CLR_RTC_SUPER_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_CLR_RTC_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_CLR_RTC_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.DATE: need_des +func (o *LP_WDT_Type) SetDATE_LP_WDT_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_WDT_Type) GetDATE_LP_WDT_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_WDT_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Motor Control Pulse-Width Modulation 0 +type MCPWM_Type struct { + CLK_CFG volatile.Register32 // 0x0 + TIMER0_CFG0 volatile.Register32 // 0x4 + TIMER0_CFG1 volatile.Register32 // 0x8 + TIMER0_SYNC volatile.Register32 // 0xC + TIMER0_STATUS volatile.Register32 // 0x10 + TIMER1_CFG0 volatile.Register32 // 0x14 + TIMER1_CFG1 volatile.Register32 // 0x18 + TIMER1_SYNC volatile.Register32 // 0x1C + TIMER1_STATUS volatile.Register32 // 0x20 + TIMER2_CFG0 volatile.Register32 // 0x24 + TIMER2_CFG1 volatile.Register32 // 0x28 + TIMER2_SYNC volatile.Register32 // 0x2C + TIMER2_STATUS volatile.Register32 // 0x30 + TIMER_SYNCI_CFG volatile.Register32 // 0x34 + OPERATOR_TIMERSEL volatile.Register32 // 0x38 + GEN0_STMP_CFG volatile.Register32 // 0x3C + GEN0_TSTMP_A volatile.Register32 // 0x40 + GEN0_TSTMP_B volatile.Register32 // 0x44 + GEN0_CFG0 volatile.Register32 // 0x48 + GEN0_FORCE volatile.Register32 // 0x4C + GEN0_A volatile.Register32 // 0x50 + GEN0_B volatile.Register32 // 0x54 + DT0_CFG volatile.Register32 // 0x58 + DT0_FED_CFG volatile.Register32 // 0x5C + DT0_RED_CFG volatile.Register32 // 0x60 + CARRIER0_CFG volatile.Register32 // 0x64 + FH0_CFG0 volatile.Register32 // 0x68 + FH0_CFG1 volatile.Register32 // 0x6C + FH0_STATUS volatile.Register32 // 0x70 + GEN1_STMP_CFG volatile.Register32 // 0x74 + GEN1_TSTMP_A volatile.Register32 // 0x78 + GEN1_TSTMP_B volatile.Register32 // 0x7C + GEN1_CFG0 volatile.Register32 // 0x80 + GEN1_FORCE volatile.Register32 // 0x84 + GEN1_A volatile.Register32 // 0x88 + GEN1_B volatile.Register32 // 0x8C + DT1_CFG volatile.Register32 // 0x90 + DT1_FED_CFG volatile.Register32 // 0x94 + DT1_RED_CFG volatile.Register32 // 0x98 + CARRIER1_CFG volatile.Register32 // 0x9C + FH1_CFG0 volatile.Register32 // 0xA0 + FH1_CFG1 volatile.Register32 // 0xA4 + FH1_STATUS volatile.Register32 // 0xA8 + GEN2_STMP_CFG volatile.Register32 // 0xAC + GEN2_TSTMP_A volatile.Register32 // 0xB0 + GEN2_TSTMP_B volatile.Register32 // 0xB4 + GEN2_CFG0 volatile.Register32 // 0xB8 + GEN2_FORCE volatile.Register32 // 0xBC + GEN2_A volatile.Register32 // 0xC0 + GEN2_B volatile.Register32 // 0xC4 + DT2_CFG volatile.Register32 // 0xC8 + DT2_FED_CFG volatile.Register32 // 0xCC + DT2_RED_CFG volatile.Register32 // 0xD0 + CARRIER2_CFG volatile.Register32 // 0xD4 + FH2_CFG0 volatile.Register32 // 0xD8 + FH2_CFG1 volatile.Register32 // 0xDC + FH2_STATUS volatile.Register32 // 0xE0 + FAULT_DETECT volatile.Register32 // 0xE4 + CAP_TIMER_CFG volatile.Register32 // 0xE8 + CAP_TIMER_PHASE volatile.Register32 // 0xEC + CAP_CH0_CFG volatile.Register32 // 0xF0 + CAP_CH1_CFG volatile.Register32 // 0xF4 + CAP_CH2_CFG volatile.Register32 // 0xF8 + CAP_CH0 volatile.Register32 // 0xFC + CAP_CH1 volatile.Register32 // 0x100 + CAP_CH2 volatile.Register32 // 0x104 + CAP_STATUS volatile.Register32 // 0x108 + UPDATE_CFG volatile.Register32 // 0x10C + INT_ENA volatile.Register32 // 0x110 + INT_RAW volatile.Register32 // 0x114 + INT_ST volatile.Register32 // 0x118 + INT_CLR volatile.Register32 // 0x11C + EVT_EN volatile.Register32 // 0x120 + TASK_EN volatile.Register32 // 0x124 + CLK volatile.Register32 // 0x128 + VERSION volatile.Register32 // 0x12C +} + +// MCPWM.CLK_CFG: PWM clock prescaler register. +func (o *MCPWM_Type) SetCLK_CFG_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetCLK_CFG_CLK_PRESCALE() uint32 { + return volatile.LoadUint32(&o.CLK_CFG.Reg) & 0xff +} + +// MCPWM.TIMER0_CFG0: PWM timer0 period and update method configuration register. +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER0_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER0_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER0_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER0_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER0_CFG1: PWM timer0 working mode and start/stop control configuration register. +func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER0_START(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER0_START() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER0_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER0_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER0_SYNC: PWM timer0 sync function configuration register. +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER0_STATUS: PWM timer0 status register. +func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER0_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER0_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER0_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER0_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER1_CFG0: PWM timer1 period and update method configuration register. +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER1_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER1_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER1_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER1_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER1_CFG1: PWM timer1 working mode and start/stop control configuration register. +func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER1_START(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER1_START() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER1_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER1_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER1_SYNC: PWM timer1 sync function configuration register. +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER1_STATUS: PWM timer1 status register. +func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER1_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER1_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER1_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER1_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER2_CFG0: PWM timer2 period and update method configuration register. +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER2_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER2_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER2_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER2_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER2_CFG1: PWM timer2 working mode and start/stop control configuration register. +func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER2_START(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER2_START() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER2_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER2_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER2_SYNC: PWM timer2 sync function configuration register. +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER2_STATUS: PWM timer2 status register. +func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER2_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER2_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER2_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER2_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER_SYNCI_CFG: Synchronization input selection for three PWM timers. +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER0_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER0_SYNCISEL() uint32 { + return volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER1_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x38)|value<<3) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER1_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x38) >> 3 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER2_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x1c0)|value<<6) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER2_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x1c0) >> 6 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x800) >> 11 +} + +// MCPWM.OPERATOR_TIMERSEL: Select specific timer for PWM operators. +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL() uint32 { + return volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x3 +} +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x30) >> 4 +} + +// MCPWM.GEN0_STMP_CFG: Transfer status and update method for time stamp registers A and B +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR0_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR0_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR0_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR0_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR0_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR0_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR0_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR0_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN0_TSTMP_A: Shadow register for register A. +func (o *MCPWM_Type) SetGEN0_TSTMP_A_CMPR0_A(value uint32) { + volatile.StoreUint32(&o.GEN0_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN0_TSTMP_A_CMPR0_A() uint32 { + return volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN0_TSTMP_B: Shadow register for register B. +func (o *MCPWM_Type) SetGEN0_TSTMP_B_CMPR0_B(value uint32) { + volatile.StoreUint32(&o.GEN0_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN0_TSTMP_B_CMPR0_B() uint32 { + return volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN0_CFG0: Fault event T0 and T1 handling +func (o *MCPWM_Type) SetGEN0_CFG0_GEN0_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN0_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN0_CFG0_GEN0_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN0_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN0_CFG0_GEN0_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN0_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN0_FORCE: Permissives to force PWM0A and PWM0B outputs by software +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN0_A: Actions triggered by events on PWM0A +func (o *MCPWM_Type) SetGEN0_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN0_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN0_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN0_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN0_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN0_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN0_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN0_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN0_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN0_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN0_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN0_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN0_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN0_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN0_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN0_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN0_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN0_B: Actions triggered by events on PWM0B +func (o *MCPWM_Type) SetGEN0_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN0_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN0_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN0_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN0_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN0_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN0_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN0_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN0_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN0_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN0_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN0_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN0_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN0_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN0_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN0_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN0_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT0_CFG: dead time type selection and configuration +func (o *MCPWM_Type) SetDT0_CFG_DB0_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT0_FED_CFG: Shadow register for falling edge delay (FED). +func (o *MCPWM_Type) SetDT0_FED_CFG_DB0_FED(value uint32) { + volatile.StoreUint32(&o.DT0_FED_CFG.Reg, volatile.LoadUint32(&o.DT0_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT0_FED_CFG_DB0_FED() uint32 { + return volatile.LoadUint32(&o.DT0_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT0_RED_CFG: Shadow register for rising edge delay (RED). +func (o *MCPWM_Type) SetDT0_RED_CFG_DB0_RED(value uint32) { + volatile.StoreUint32(&o.DT0_RED_CFG.Reg, volatile.LoadUint32(&o.DT0_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT0_RED_CFG_DB0_RED() uint32 { + return volatile.LoadUint32(&o.DT0_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER0_CFG: Carrier enable and configuratoin +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH0_CFG0: Actions on PWM0A and PWM0B trip events +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH0_CFG1: Software triggers for fault handler actions +func (o *MCPWM_Type) SetFH0_CFG1_TZ0_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ0_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_CFG1_TZ0_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ0_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH0_CFG1_TZ0_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ0_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH0_CFG1_TZ0_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ0_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH0_STATUS: Status of fault events. +func (o *MCPWM_Type) SetFH0_STATUS_TZ0_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_STATUS_TZ0_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_STATUS_TZ0_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH0_STATUS_TZ0_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.GEN1_STMP_CFG: Transfer status and update method for time stamp registers A and B +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR1_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR1_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR1_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR1_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR1_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR1_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR1_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR1_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN1_TSTMP_A: Shadow register for register A. +func (o *MCPWM_Type) SetGEN1_TSTMP_A_CMPR1_A(value uint32) { + volatile.StoreUint32(&o.GEN1_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN1_TSTMP_A_CMPR1_A() uint32 { + return volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN1_TSTMP_B: Shadow register for register B. +func (o *MCPWM_Type) SetGEN1_TSTMP_B_CMPR1_B(value uint32) { + volatile.StoreUint32(&o.GEN1_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN1_TSTMP_B_CMPR1_B() uint32 { + return volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN1_CFG0: Fault event T0 and T1 handling +func (o *MCPWM_Type) SetGEN1_CFG0_GEN1_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN1_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN1_CFG0_GEN1_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN1_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN1_CFG0_GEN1_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN1_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN1_FORCE: Permissives to force PWM1A and PWM1B outputs by software +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN1_A: Actions triggered by events on PWM1A +func (o *MCPWM_Type) SetGEN1_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN1_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN1_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN1_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN1_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN1_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN1_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN1_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN1_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN1_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN1_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN1_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN1_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN1_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN1_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN1_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN1_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN1_B: Actions triggered by events on PWM1B +func (o *MCPWM_Type) SetGEN1_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN1_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN1_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN1_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN1_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN1_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN1_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN1_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN1_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN1_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN1_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN1_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN1_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN1_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN1_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN1_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN1_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT1_CFG: dead time type selection and configuration +func (o *MCPWM_Type) SetDT1_CFG_DB1_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT1_FED_CFG: Shadow register for falling edge delay (FED). +func (o *MCPWM_Type) SetDT1_FED_CFG_DB1_FED(value uint32) { + volatile.StoreUint32(&o.DT1_FED_CFG.Reg, volatile.LoadUint32(&o.DT1_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT1_FED_CFG_DB1_FED() uint32 { + return volatile.LoadUint32(&o.DT1_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT1_RED_CFG: Shadow register for rising edge delay (RED). +func (o *MCPWM_Type) SetDT1_RED_CFG_DB1_RED(value uint32) { + volatile.StoreUint32(&o.DT1_RED_CFG.Reg, volatile.LoadUint32(&o.DT1_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT1_RED_CFG_DB1_RED() uint32 { + return volatile.LoadUint32(&o.DT1_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER1_CFG: Carrier enable and configuratoin +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH1_CFG0: Actions on PWM1A and PWM1B trip events +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH1_CFG1: Software triggers for fault handler actions +func (o *MCPWM_Type) SetFH1_CFG1_TZ1_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ1_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_CFG1_TZ1_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ1_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH1_CFG1_TZ1_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ1_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH1_CFG1_TZ1_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ1_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH1_STATUS: Status of fault events. +func (o *MCPWM_Type) SetFH1_STATUS_TZ1_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_STATUS_TZ1_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_STATUS_TZ1_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH1_STATUS_TZ1_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.GEN2_STMP_CFG: Transfer status and update method for time stamp registers A and B +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR2_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR2_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR2_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR2_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR2_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR2_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR2_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR2_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN2_TSTMP_A: Shadow register for register A. +func (o *MCPWM_Type) SetGEN2_TSTMP_A_CMPR2_A(value uint32) { + volatile.StoreUint32(&o.GEN2_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN2_TSTMP_A_CMPR2_A() uint32 { + return volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN2_TSTMP_B: Shadow register for register B. +func (o *MCPWM_Type) SetGEN2_TSTMP_B_CMPR2_B(value uint32) { + volatile.StoreUint32(&o.GEN2_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN2_TSTMP_B_CMPR2_B() uint32 { + return volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN2_CFG0: Fault event T0 and T1 handling +func (o *MCPWM_Type) SetGEN2_CFG0_GEN2_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN2_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN2_CFG0_GEN2_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN2_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN2_CFG0_GEN2_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN2_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN2_FORCE: Permissives to force PWM2A and PWM2B outputs by software +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN2_A: Actions triggered by events on PWM2A +func (o *MCPWM_Type) SetGEN2_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN2_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN2_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN2_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN2_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN2_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN2_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN2_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN2_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN2_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN2_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN2_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN2_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN2_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN2_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN2_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN2_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN2_B: Actions triggered by events on PWM2B +func (o *MCPWM_Type) SetGEN2_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN2_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN2_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN2_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN2_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN2_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN2_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN2_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN2_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN2_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN2_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN2_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN2_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN2_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN2_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN2_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN2_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT2_CFG: dead time type selection and configuration +func (o *MCPWM_Type) SetDT2_CFG_DB2_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT2_FED_CFG: Shadow register for falling edge delay (FED). +func (o *MCPWM_Type) SetDT2_FED_CFG_DB2_FED(value uint32) { + volatile.StoreUint32(&o.DT2_FED_CFG.Reg, volatile.LoadUint32(&o.DT2_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT2_FED_CFG_DB2_FED() uint32 { + return volatile.LoadUint32(&o.DT2_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT2_RED_CFG: Shadow register for rising edge delay (RED). +func (o *MCPWM_Type) SetDT2_RED_CFG_DB2_RED(value uint32) { + volatile.StoreUint32(&o.DT2_RED_CFG.Reg, volatile.LoadUint32(&o.DT2_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT2_RED_CFG_DB2_RED() uint32 { + return volatile.LoadUint32(&o.DT2_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER2_CFG: Carrier enable and configuratoin +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH2_CFG0: Actions on PWM2A and PWM2B trip events +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH2_CFG1: Software triggers for fault handler actions +func (o *MCPWM_Type) SetFH2_CFG1_TZ2_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ2_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_CFG1_TZ2_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ2_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH2_CFG1_TZ2_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ2_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH2_CFG1_TZ2_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ2_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH2_STATUS: Status of fault events. +func (o *MCPWM_Type) SetFH2_STATUS_TZ2_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_STATUS_TZ2_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_STATUS_TZ2_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH2_STATUS_TZ2_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.FAULT_DETECT: Fault detection configuration and status +func (o *MCPWM_Type) SetFAULT_DETECT_F0_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F0_EN() uint32 { + return volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F1_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F1_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F2_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F2_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F0_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F0_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F1_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F1_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F2_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F2_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F0(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F0() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F1(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F1() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F2(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F2() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x100) >> 8 +} + +// MCPWM.CAP_TIMER_CFG: Configure capture timer +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_TIMER_EN() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_EN() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_SEL(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1c)|value<<2) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_SEL() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1c) >> 2 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x20) >> 5 +} + +// MCPWM.CAP_TIMER_PHASE: Phase for capture timer sync +func (o *MCPWM_Type) SetCAP_TIMER_PHASE(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_PHASE.Reg, value) +} +func (o *MCPWM_Type) GetCAP_TIMER_PHASE() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_PHASE.Reg) +} + +// MCPWM.CAP_CH0_CFG: Capture channel 0 configuration and enable +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH1_CFG: Capture channel 1 configuration and enable +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH2_CFG: Capture channel 2 configuration and enable +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH0: ch0 capture value status register +func (o *MCPWM_Type) SetCAP_CH0(value uint32) { + volatile.StoreUint32(&o.CAP_CH0.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH0() uint32 { + return volatile.LoadUint32(&o.CAP_CH0.Reg) +} + +// MCPWM.CAP_CH1: ch1 capture value status register +func (o *MCPWM_Type) SetCAP_CH1(value uint32) { + volatile.StoreUint32(&o.CAP_CH1.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH1() uint32 { + return volatile.LoadUint32(&o.CAP_CH1.Reg) +} + +// MCPWM.CAP_CH2: ch2 capture value status register +func (o *MCPWM_Type) SetCAP_CH2(value uint32) { + volatile.StoreUint32(&o.CAP_CH2.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH2() uint32 { + return volatile.LoadUint32(&o.CAP_CH2.Reg) +} + +// MCPWM.CAP_STATUS: Edge of last capture trigger +func (o *MCPWM_Type) SetCAP_STATUS_CAP0_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP0_EDGE() uint32 { + return volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_STATUS_CAP1_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP1_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetCAP_STATUS_CAP2_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP2_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x4) >> 2 +} + +// MCPWM.UPDATE_CFG: Enable update. +func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_UP_EN() uint32 { + return volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP0_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP0_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP0_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP0_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP1_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP1_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP1_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP1_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP2_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP2_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP2_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP2_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x80) >> 7 +} + +// MCPWM.INT_ENA: Interrupt enable bits +func (o *MCPWM_Type) SetINT_ENA_TIMER0_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_STOP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT0_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT0_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT1_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT1_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT2_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT2_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR0_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR0_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR1_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR1_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR2_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR2_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR0_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR0_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR1_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR1_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR2_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR2_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_ENA_TZ0_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_ENA_TZ0_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_ENA_TZ1_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_ENA_TZ1_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_ENA_TZ2_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_ENA_TZ2_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_ENA_TZ0_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_ENA_TZ0_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_ENA_TZ1_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_ENA_TZ1_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_ENA_TZ2_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_ENA_TZ2_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_ENA_CAP0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_ENA_CAP0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_ENA_CAP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_ENA_CAP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_ENA_CAP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_ENA_CAP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_RAW: Raw interrupt status +func (o *MCPWM_Type) SetINT_RAW_TIMER0_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_STOP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT0_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT0_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT1_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT1_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT2_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT2_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR0_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR0_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR1_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR1_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR2_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR2_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR0_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR0_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR1_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR1_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR2_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR2_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_RAW_TZ0_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_RAW_TZ0_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_RAW_TZ1_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_RAW_TZ1_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_RAW_TZ2_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_RAW_TZ2_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_RAW_TZ0_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_RAW_TZ0_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_RAW_TZ1_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_RAW_TZ1_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_RAW_TZ2_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_RAW_TZ2_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_RAW_CAP0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_RAW_CAP0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_RAW_CAP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_RAW_CAP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_RAW_CAP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_RAW_CAP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_ST: Masked interrupt status +func (o *MCPWM_Type) SetINT_ST_TIMER0_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_STOP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_ST_TIMER0_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_ST_TIMER0_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_ST_FAULT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_ST_FAULT0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_ST_FAULT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_ST_FAULT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_ST_FAULT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_ST_FAULT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_ST_FAULT0_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_ST_FAULT0_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_ST_FAULT1_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_ST_FAULT1_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_ST_FAULT2_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_ST_FAULT2_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_ST_CMPR0_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_ST_CMPR0_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_ST_CMPR1_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_ST_CMPR1_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_ST_CMPR2_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_ST_CMPR2_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_ST_CMPR0_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_ST_CMPR0_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_ST_CMPR1_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_ST_CMPR1_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_ST_CMPR2_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_ST_CMPR2_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_ST_TZ0_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_ST_TZ0_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_ST_TZ1_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_ST_TZ1_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_ST_TZ2_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_ST_TZ2_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_ST_TZ0_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_ST_TZ0_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_ST_TZ1_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_ST_TZ1_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_ST_TZ2_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_ST_TZ2_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_ST_CAP0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_ST_CAP0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_ST_CAP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_ST_CAP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_ST_CAP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_ST_CAP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_CLR: Interrupt clear bits +func (o *MCPWM_Type) SetINT_CLR_TIMER0_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_STOP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT0_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT0_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT1_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT1_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT2_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT2_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR0_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR0_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR1_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR1_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR2_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR2_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR0_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR0_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR1_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR1_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR2_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR2_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_CLR_TZ0_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_CLR_TZ0_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_CLR_TZ1_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_CLR_TZ1_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_CLR_TZ2_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_CLR_TZ2_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_CLR_TZ0_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_CLR_TZ0_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_CLR_TZ1_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_CLR_TZ1_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_CLR_TZ2_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_CLR_TZ2_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_CLR_CAP0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_CLR_CAP0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_CLR_CAP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_CLR_CAP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_CLR_CAP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_CLR_CAP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} + +// MCPWM.EVT_EN: MCPWM event enable register +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_STOP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_STOP_EN() uint32 { + return volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_STOP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_STOP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_TEZ_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_TEZ_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_TEZ_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_TEZ_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_TEZ_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_TEZ_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_TEP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_TEP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_TEP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_TEP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_TEP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_TEP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP0_TEA_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP0_TEA_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP1_TEA_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP1_TEA_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP2_TEA_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP2_TEA_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP0_TEB_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP0_TEB_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP1_TEB_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP1_TEB_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP2_TEB_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP2_TEB_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F0_CLR_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F0_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F1_CLR_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F1_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F2_CLR_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F2_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ0_CBC_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ0_CBC_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ1_CBC_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ1_CBC_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ2_CBC_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ2_CBC_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ0_OST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ0_OST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ1_OST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ1_OST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ2_OST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ2_OST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_CAP0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_CAP1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_CAP2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20000000) >> 29 +} + +// MCPWM.TASK_EN: MCPWM task enable register +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR0_A_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR0_A_UP_EN() uint32 { + return volatile.LoadUint32(&o.TASK_EN.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR1_A_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR1_A_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR2_A_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR2_A_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR0_B_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR0_B_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR1_B_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR1_B_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR2_B_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR2_B_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_GEN_STOP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_GEN_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER0_SYNC_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER0_SYNC_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER1_SYNC_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER1_SYNC_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER2_SYNC_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER2_SYNC_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER0_PERIOD_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER0_PERIOD_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER1_PERIOD_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER1_PERIOD_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER2_PERIOD_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER2_PERIOD_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TZ0_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TZ0_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TZ1_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TZ1_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TZ2_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TZ2_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CLR0_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CLR0_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CLR1_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CLR1_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CLR2_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CLR2_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CAP0_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CAP1_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CAP2_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x200000) >> 21 +} + +// MCPWM.CLK: MCPWM APB configuration register +func (o *MCPWM_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} + +// MCPWM.VERSION: Version register. +func (o *MCPWM_Type) SetVERSION_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *MCPWM_Type) GetVERSION_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// MEM_MONITOR Peripheral +type MEM_MONITOR_Type struct { + LOG_SETTING volatile.Register32 // 0x0 + LOG_CHECK_DATA volatile.Register32 // 0x4 + LOG_DATA_MASK volatile.Register32 // 0x8 + LOG_MIN volatile.Register32 // 0xC + LOG_MAX volatile.Register32 // 0x10 + LOG_MEM_START volatile.Register32 // 0x14 + LOG_MEM_END volatile.Register32 // 0x18 + LOG_MEM_CURRENT_ADDR volatile.Register32 // 0x1C + LOG_MEM_ADDR_UPDATE volatile.Register32 // 0x20 + LOG_MEM_FULL_FLAG volatile.Register32 // 0x24 + CLOCK_GATE volatile.Register32 // 0x28 + _ [976]byte + DATE volatile.Register32 // 0x3FC +} + +// MEM_MONITOR.LOG_SETTING: log config regsiter +func (o *MEM_MONITOR_Type) SetLOG_SETTING_LOG_ENA(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x7)|value) +} +func (o *MEM_MONITOR_Type) GetLOG_SETTING_LOG_ENA() uint32 { + return volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x7 +} +func (o *MEM_MONITOR_Type) SetLOG_SETTING_LOG_MODE(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x78)|value<<3) +} +func (o *MEM_MONITOR_Type) GetLOG_SETTING_LOG_MODE() uint32 { + return (volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x78) >> 3 +} +func (o *MEM_MONITOR_Type) SetLOG_SETTING_LOG_MEM_LOOP_ENABLE(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x80)|value<<7) +} +func (o *MEM_MONITOR_Type) GetLOG_SETTING_LOG_MEM_LOOP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x80) >> 7 +} + +// MEM_MONITOR.LOG_CHECK_DATA: check data regsiter +func (o *MEM_MONITOR_Type) SetLOG_CHECK_DATA(value uint32) { + volatile.StoreUint32(&o.LOG_CHECK_DATA.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_CHECK_DATA() uint32 { + return volatile.LoadUint32(&o.LOG_CHECK_DATA.Reg) +} + +// MEM_MONITOR.LOG_DATA_MASK: check data mask register +func (o *MEM_MONITOR_Type) SetLOG_DATA_MASK(value uint32) { + volatile.StoreUint32(&o.LOG_DATA_MASK.Reg, volatile.LoadUint32(&o.LOG_DATA_MASK.Reg)&^(0xf)|value) +} +func (o *MEM_MONITOR_Type) GetLOG_DATA_MASK() uint32 { + return volatile.LoadUint32(&o.LOG_DATA_MASK.Reg) & 0xf +} + +// MEM_MONITOR.LOG_MIN: log boundary regsiter +func (o *MEM_MONITOR_Type) SetLOG_MIN(value uint32) { + volatile.StoreUint32(&o.LOG_MIN.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MIN() uint32 { + return volatile.LoadUint32(&o.LOG_MIN.Reg) +} + +// MEM_MONITOR.LOG_MAX: log boundary regsiter +func (o *MEM_MONITOR_Type) SetLOG_MAX(value uint32) { + volatile.StoreUint32(&o.LOG_MAX.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MAX() uint32 { + return volatile.LoadUint32(&o.LOG_MAX.Reg) +} + +// MEM_MONITOR.LOG_MEM_START: log message store range register +func (o *MEM_MONITOR_Type) SetLOG_MEM_START(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_START.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_START() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_START.Reg) +} + +// MEM_MONITOR.LOG_MEM_END: log message store range register +func (o *MEM_MONITOR_Type) SetLOG_MEM_END(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_END.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_END() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_END.Reg) +} + +// MEM_MONITOR.LOG_MEM_CURRENT_ADDR: current writing address. +func (o *MEM_MONITOR_Type) SetLOG_MEM_CURRENT_ADDR(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_CURRENT_ADDR.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_CURRENT_ADDR() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_CURRENT_ADDR.Reg) +} + +// MEM_MONITOR.LOG_MEM_ADDR_UPDATE: writing address update +func (o *MEM_MONITOR_Type) SetLOG_MEM_ADDR_UPDATE(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_ADDR_UPDATE.Reg, volatile.LoadUint32(&o.LOG_MEM_ADDR_UPDATE.Reg)&^(0x1)|value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_ADDR_UPDATE() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_ADDR_UPDATE.Reg) & 0x1 +} + +// MEM_MONITOR.LOG_MEM_FULL_FLAG: full flag status register +func (o *MEM_MONITOR_Type) SetLOG_MEM_FULL_FLAG(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_FULL_FLAG.Reg, volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg)&^(0x1)|value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_FULL_FLAG() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg) & 0x1 +} +func (o *MEM_MONITOR_Type) SetLOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_FULL_FLAG.Reg, volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg)&^(0x2)|value<<1) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG() uint32 { + return (volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg) & 0x2) >> 1 +} + +// MEM_MONITOR.CLOCK_GATE: clock gate force on register +func (o *MEM_MONITOR_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *MEM_MONITOR_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// MEM_MONITOR.DATE: version register +func (o *MEM_MONITOR_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *MEM_MONITOR_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// MODEM_LPCON Peripheral +type MODEM_LPCON_Type struct { + TEST_CONF volatile.Register32 // 0x0 + LP_TIMER_CONF volatile.Register32 // 0x4 + COEX_LP_CLK_CONF volatile.Register32 // 0x8 + WIFI_LP_CLK_CONF volatile.Register32 // 0xC + I2C_MST_CLK_CONF volatile.Register32 // 0x10 + MODEM_32K_CLK_CONF volatile.Register32 // 0x14 + CLK_CONF volatile.Register32 // 0x18 + CLK_CONF_FORCE_ON volatile.Register32 // 0x1C + CLK_CONF_POWER_ST volatile.Register32 // 0x20 + RST_CONF volatile.Register32 // 0x24 + MEM_CONF volatile.Register32 // 0x28 + DATE volatile.Register32 // 0x2C +} + +// MODEM_LPCON.TEST_CONF +func (o *MODEM_LPCON_Type) SetTEST_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetTEST_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x1 +} +func (o *MODEM_LPCON_Type) SetTEST_CONF_CLK_DEBUG_ENA(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetTEST_CONF_CLK_DEBUG_ENA() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x2) >> 1 +} + +// MODEM_LPCON.LP_TIMER_CONF +func (o *MODEM_LPCON_Type) SetLP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_SLOW(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.LP_TIMER_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetLP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_SLOW() uint32 { + return volatile.LoadUint32(&o.LP_TIMER_CONF.Reg) & 0x1 +} +func (o *MODEM_LPCON_Type) SetLP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_FAST(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.LP_TIMER_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetLP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_FAST() uint32 { + return (volatile.LoadUint32(&o.LP_TIMER_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetLP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.LP_TIMER_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetLP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.LP_TIMER_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetLP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.LP_TIMER_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_LPCON_Type) GetLP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LP_TIMER_CONF.Reg) & 0x8) >> 3 +} +func (o *MODEM_LPCON_Type) SetLP_TIMER_CONF_CLK_LP_TIMER_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_CONF.Reg, volatile.LoadUint32(&o.LP_TIMER_CONF.Reg)&^(0xfff0)|value<<4) +} +func (o *MODEM_LPCON_Type) GetLP_TIMER_CONF_CLK_LP_TIMER_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_TIMER_CONF.Reg) & 0xfff0) >> 4 +} + +// MODEM_LPCON.COEX_LP_CLK_CONF +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW() uint32 { + return volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x1 +} +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x8) >> 3 +} +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0xfff0)|value<<4) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0xfff0) >> 4 +} + +// MODEM_LPCON.WIFI_LP_CLK_CONF +func (o *MODEM_LPCON_Type) SetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_SLOW(value uint32) { + volatile.StoreUint32(&o.WIFI_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_SLOW() uint32 { + return volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg) & 0x1 +} +func (o *MODEM_LPCON_Type) SetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_FAST(value uint32) { + volatile.StoreUint32(&o.WIFI_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_FAST() uint32 { + return (volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.WIFI_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.WIFI_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_LPCON_Type) GetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg) & 0x8) >> 3 +} +func (o *MODEM_LPCON_Type) SetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.WIFI_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg)&^(0xfff0)|value<<4) +} +func (o *MODEM_LPCON_Type) GetWIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.WIFI_LP_CLK_CONF.Reg) & 0xfff0) >> 4 +} + +// MODEM_LPCON.I2C_MST_CLK_CONF +func (o *MODEM_LPCON_Type) SetI2C_MST_CLK_CONF_CLK_I2C_MST_SEL_160M(value uint32) { + volatile.StoreUint32(&o.I2C_MST_CLK_CONF.Reg, volatile.LoadUint32(&o.I2C_MST_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetI2C_MST_CLK_CONF_CLK_I2C_MST_SEL_160M() uint32 { + return volatile.LoadUint32(&o.I2C_MST_CLK_CONF.Reg) & 0x1 +} + +// MODEM_LPCON.MODEM_32K_CLK_CONF +func (o *MODEM_LPCON_Type) SetMODEM_32K_CLK_CONF_CLK_MODEM_32K_SEL(value uint32) { + volatile.StoreUint32(&o.MODEM_32K_CLK_CONF.Reg, volatile.LoadUint32(&o.MODEM_32K_CLK_CONF.Reg)&^(0x3)|value) +} +func (o *MODEM_LPCON_Type) GetMODEM_32K_CLK_CONF_CLK_MODEM_32K_SEL() uint32 { + return volatile.LoadUint32(&o.MODEM_32K_CLK_CONF.Reg) & 0x3 +} + +// MODEM_LPCON.CLK_CONF +func (o *MODEM_LPCON_Type) SetCLK_CONF_CLK_WIFIPWR_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_CLK_WIFIPWR_EN() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_CLK_COEX_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_CLK_COEX_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_CLK_I2C_MST_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_CLK_I2C_MST_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_CLK_LP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_CLK_LP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8) >> 3 +} + +// MODEM_LPCON.CLK_CONF_FORCE_ON +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_WIFIPWR_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_WIFIPWR_FO() uint32 { + return volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x1 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_COEX_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_COEX_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_I2C_MST_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_I2C_MST_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_LP_TIMER_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_LP_TIMER_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x8) >> 3 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_BCMEM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x10)|value<<4) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_BCMEM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x10) >> 4 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_I2C_MST_MEM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x20)|value<<5) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_I2C_MST_MEM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x20) >> 5 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_CHAN_FREQ_MEM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x40)|value<<6) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_CHAN_FREQ_MEM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x40) >> 6 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_PBUS_MEM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x80)|value<<7) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_PBUS_MEM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x80) >> 7 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_AGC_MEM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x100)|value<<8) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_AGC_MEM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x100) >> 8 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_DC_MEM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x200)|value<<9) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_DC_MEM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x200) >> 9 +} + +// MODEM_LPCON.CLK_CONF_POWER_ST +func (o *MODEM_LPCON_Type) SetCLK_CONF_POWER_ST_CLK_WIFIPWR_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf0000)|value<<16) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_POWER_ST_CLK_WIFIPWR_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf0000) >> 16 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_POWER_ST_CLK_COEX_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf00000)|value<<20) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_POWER_ST_CLK_COEX_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf00000) >> 20 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_POWER_ST_CLK_I2C_MST_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf000000)|value<<24) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_POWER_ST_CLK_I2C_MST_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf000000) >> 24 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_POWER_ST_CLK_LP_APB_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf0000000)|value<<28) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_POWER_ST_CLK_LP_APB_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf0000000) >> 28 +} + +// MODEM_LPCON.RST_CONF +func (o *MODEM_LPCON_Type) SetRST_CONF_RST_WIFIPWR(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetRST_CONF_RST_WIFIPWR() uint32 { + return volatile.LoadUint32(&o.RST_CONF.Reg) & 0x1 +} +func (o *MODEM_LPCON_Type) SetRST_CONF_RST_COEX(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetRST_CONF_RST_COEX() uint32 { + return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetRST_CONF_RST_I2C_MST(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetRST_CONF_RST_I2C_MST() uint32 { + return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetRST_CONF_RST_LP_TIMER(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_LPCON_Type) GetRST_CONF_RST_LP_TIMER() uint32 { + return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x8) >> 3 +} + +// MODEM_LPCON.MEM_CONF +func (o *MODEM_LPCON_Type) SetMEM_CONF_DC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_DC_MEM_FORCE_PU() uint32 { + return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_DC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_DC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_AGC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_AGC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_AGC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_AGC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x8) >> 3 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_PBUS_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x10)|value<<4) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_PBUS_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x10) >> 4 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_PBUS_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x20)|value<<5) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_PBUS_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x20) >> 5 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_BC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x40)|value<<6) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_BC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x40) >> 6 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_BC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x80)|value<<7) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_BC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x80) >> 7 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_I2C_MST_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x100)|value<<8) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_I2C_MST_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x100) >> 8 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_I2C_MST_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x200)|value<<9) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_I2C_MST_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x200) >> 9 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_CHAN_FREQ_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x400)|value<<10) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_CHAN_FREQ_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x400) >> 10 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_CHAN_FREQ_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x800)|value<<11) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_CHAN_FREQ_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x800) >> 11 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_MODEM_PWR_MEM_WP(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x7000)|value<<12) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_MODEM_PWR_MEM_WP() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x7000) >> 12 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_MODEM_PWR_MEM_WA(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x38000)|value<<15) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_MODEM_PWR_MEM_WA() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x38000) >> 15 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_MODEM_PWR_MEM_RA(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xc0000)|value<<18) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_MODEM_PWR_MEM_RA() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xc0000) >> 18 +} + +// MODEM_LPCON.DATE +func (o *MODEM_LPCON_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *MODEM_LPCON_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// MODEM_SYSCON Peripheral +type MODEM_SYSCON_Type struct { + TEST_CONF volatile.Register32 // 0x0 + CLK_CONF volatile.Register32 // 0x4 + CLK_CONF_FORCE_ON volatile.Register32 // 0x8 + CLK_CONF_POWER_ST volatile.Register32 // 0xC + MODEM_RST_CONF volatile.Register32 // 0x10 + CLK_CONF1 volatile.Register32 // 0x14 + CLK_CONF1_FORCE_ON volatile.Register32 // 0x18 + WIFI_BB_CFG volatile.Register32 // 0x1C + MEM_CONF volatile.Register32 // 0x20 + DATE volatile.Register32 // 0x24 +} + +// MODEM_SYSCON.TEST_CONF +func (o *MODEM_SYSCON_Type) SetTEST_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_SYSCON_Type) GetTEST_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x1 +} + +// MODEM_SYSCON.CLK_CONF +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_DATA_DUMP_MUX(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_DATA_DUMP_MUX() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_ETM_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_ZB_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_ZB_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x800000) >> 23 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_ZB_MAC_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_ZB_MAC_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_ECB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_ECB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_CCM_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_CCM_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_BAH_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_BAH_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000000) >> 28 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x20000000) >> 29 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_BLE_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_BLE_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x40000000) >> 30 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_DATA_DUMP_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_DATA_DUMP_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x80000000) >> 31 +} + +// MODEM_SYSCON.CLK_CONF_FORCE_ON +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_ETM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x400000)|value<<22) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_ETM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x400000) >> 22 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_ZB_APB_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x800000)|value<<23) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_ZB_APB_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x800000) >> 23 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_ZB_MAC_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x1000000)|value<<24) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_ZB_MAC_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x1000000) >> 24 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_ECB_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x2000000)|value<<25) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_ECB_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x2000000) >> 25 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_CCM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x4000000)|value<<26) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_CCM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x4000000) >> 26 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_BAH_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x8000000)|value<<27) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_BAH_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x8000000) >> 27 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_APB_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x10000000)|value<<28) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_APB_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x10000000) >> 28 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x20000000)|value<<29) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x20000000) >> 29 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x40000000)|value<<30) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x40000000) >> 30 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x80000000)|value<<31) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x80000000) >> 31 +} + +// MODEM_SYSCON.CLK_CONF_POWER_ST +func (o *MODEM_SYSCON_Type) SetCLK_CONF_POWER_ST_CLK_ZB_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf00)|value<<8) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_POWER_ST_CLK_ZB_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf00) >> 8 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_POWER_ST_CLK_FE_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf000)|value<<12) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_POWER_ST_CLK_FE_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf000) >> 12 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_POWER_ST_CLK_BT_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf0000)|value<<16) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_POWER_ST_CLK_BT_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf0000) >> 16 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_POWER_ST_CLK_WIFI_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf00000)|value<<20) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_POWER_ST_CLK_WIFI_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf00000) >> 20 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_POWER_ST_CLK_MODEM_PERI_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf000000)|value<<24) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_POWER_ST_CLK_MODEM_PERI_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf000000) >> 24 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_POWER_ST_CLK_MODEM_APB_ST_MAP(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_POWER_ST.Reg, volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg)&^(0xf0000000)|value<<28) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_POWER_ST_CLK_MODEM_APB_ST_MAP() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_POWER_ST.Reg) & 0xf0000000) >> 28 +} + +// MODEM_SYSCON.MODEM_RST_CONF +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_WIFIBB(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x100)|value<<8) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_WIFIBB() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x100) >> 8 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_WIFIMAC(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x400)|value<<10) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_WIFIMAC() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x400) >> 10 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_FE(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_FE() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x4000) >> 14 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BTMAC_APB(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BTMAC_APB() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x8000) >> 15 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BTMAC(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BTMAC() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x10000) >> 16 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BTBB_APB(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BTBB_APB() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x20000) >> 17 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BTBB(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BTBB() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x40000) >> 18 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_ETM(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_ETM() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x400000) >> 22 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_ZBMAC(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_ZBMAC() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x1000000) >> 24 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_MODEM_ECB(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_MODEM_ECB() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x2000000) >> 25 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_MODEM_CCM(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_MODEM_CCM() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x4000000) >> 26 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_MODEM_BAH(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_MODEM_BAH() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x8000000) >> 27 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_MODEM_SEC(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_MODEM_SEC() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x20000000) >> 29 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BLE_TIMER(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BLE_TIMER() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x40000000) >> 30 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_DATA_DUMP(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_DATA_DUMP() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x80000000) >> 31 +} + +// MODEM_SYSCON.CLK_CONF1 +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_22M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x1)|value) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_22M_EN() uint32 { + return volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x1 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_40M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_40M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x2) >> 1 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_44M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_44M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x4) >> 2 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_80M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_80M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x8) >> 3 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_40X_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_40X_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x10) >> 4 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_80X_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x20)|value<<5) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_80X_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x20) >> 5 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_40X1_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x40)|value<<6) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_40X1_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x40) >> 6 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_80X1_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x80)|value<<7) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_80X1_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x80) >> 7 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_160X1_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x100)|value<<8) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_160X1_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x100) >> 8 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIMAC_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x200)|value<<9) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIMAC_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x200) >> 9 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFI_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x400)|value<<10) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFI_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x400) >> 10 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_20M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x800)|value<<11) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_20M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x800) >> 11 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_40M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x1000)|value<<12) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_40M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x1000) >> 12 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_80M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_80M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x2000) >> 13 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_160M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_160M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x4000) >> 14 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_CAL_160M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_CAL_160M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x8000) >> 15 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x10000) >> 16 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_BT_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_BT_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x20000) >> 17 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_BT_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_BT_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x40000) >> 18 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_WIFIBB_480M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_WIFIBB_480M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x80000) >> 19 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_480M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_480M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x100000) >> 20 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_ANAMODE_40M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_ANAMODE_40M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x200000) >> 21 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_ANAMODE_80M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x400000)|value<<22) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_ANAMODE_80M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x400000) >> 22 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_ANAMODE_160M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x800000)|value<<23) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_ANAMODE_160M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x800000) >> 23 +} + +// MODEM_SYSCON.CLK_CONF1_FORCE_ON +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_22M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x1)|value) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_22M_FO() uint32 { + return volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x1 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_40M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_40M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x2) >> 1 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_44M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_44M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x4) >> 2 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_80M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_80M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x8) >> 3 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_40X_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x10)|value<<4) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_40X_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x10) >> 4 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_80X_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x20)|value<<5) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_80X_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x20) >> 5 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_40X1_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x40)|value<<6) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_40X1_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x40) >> 6 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_80X1_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x80)|value<<7) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_80X1_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x80) >> 7 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_160X1_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x100)|value<<8) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_160X1_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x100) >> 8 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIMAC_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x200)|value<<9) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIMAC_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x200) >> 9 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFI_APB_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x400)|value<<10) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFI_APB_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x400) >> 10 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_20M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x800)|value<<11) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_20M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x800) >> 11 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_40M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x1000)|value<<12) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_40M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x1000) >> 12 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_80M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x2000)|value<<13) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_80M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x2000) >> 13 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_160M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x4000)|value<<14) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_160M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x4000) >> 14 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_CAL_160M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x8000)|value<<15) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_CAL_160M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x8000) >> 15 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_APB_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x10000)|value<<16) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_APB_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x10000) >> 16 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_BT_APB_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x20000)|value<<17) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_BT_APB_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x20000) >> 17 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_BT_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x40000)|value<<18) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_BT_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x40000) >> 18 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_WIFIBB_480M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x80000)|value<<19) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_WIFIBB_480M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x80000) >> 19 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_480M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x100000)|value<<20) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_480M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x100000) >> 20 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_40M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x200000)|value<<21) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_40M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x200000) >> 21 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_80M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x400000)|value<<22) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_80M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x400000) >> 22 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_160M_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x800000)|value<<23) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_160M_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x800000) >> 23 +} + +// MODEM_SYSCON.WIFI_BB_CFG +func (o *MODEM_SYSCON_Type) SetWIFI_BB_CFG(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG.Reg, value) +} +func (o *MODEM_SYSCON_Type) GetWIFI_BB_CFG() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG.Reg) +} + +// MODEM_SYSCON.MEM_CONF +func (o *MODEM_SYSCON_Type) SetMEM_CONF_MODEM_MEM_WP(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x7)|value) +} +func (o *MODEM_SYSCON_Type) GetMEM_CONF_MODEM_MEM_WP() uint32 { + return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x7 +} +func (o *MODEM_SYSCON_Type) SetMEM_CONF_MODEM_MEM_WA(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x38)|value<<3) +} +func (o *MODEM_SYSCON_Type) GetMEM_CONF_MODEM_MEM_WA() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x38) >> 3 +} +func (o *MODEM_SYSCON_Type) SetMEM_CONF_MODEM_MEM_RA(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xc0)|value<<6) +} +func (o *MODEM_SYSCON_Type) GetMEM_CONF_MODEM_MEM_RA() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xc0) >> 6 +} + +// MODEM_SYSCON.DATE +func (o *MODEM_SYSCON_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *MODEM_SYSCON_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// OTP_DEBUG Peripheral +type OTP_DEBUG_Type struct { + WR_DIS volatile.Register32 // 0x0 + BLK0_BACKUP1_W1 volatile.Register32 // 0x4 + BLK0_BACKUP1_W2 volatile.Register32 // 0x8 + BLK0_BACKUP1_W3 volatile.Register32 // 0xC + BLK0_BACKUP1_W4 volatile.Register32 // 0x10 + BLK0_BACKUP1_W5 volatile.Register32 // 0x14 + BLK0_BACKUP2_W1 volatile.Register32 // 0x18 + BLK0_BACKUP2_W2 volatile.Register32 // 0x1C + BLK0_BACKUP2_W3 volatile.Register32 // 0x20 + BLK0_BACKUP2_W4 volatile.Register32 // 0x24 + BLK0_BACKUP2_W5 volatile.Register32 // 0x28 + BLK0_BACKUP3_W1 volatile.Register32 // 0x2C + BLK0_BACKUP3_W2 volatile.Register32 // 0x30 + BLK0_BACKUP3_W3 volatile.Register32 // 0x34 + BLK0_BACKUP3_W4 volatile.Register32 // 0x38 + BLK0_BACKUP3_W5 volatile.Register32 // 0x3C + BLK0_BACKUP4_W1 volatile.Register32 // 0x40 + BLK0_BACKUP4_W2 volatile.Register32 // 0x44 + BLK0_BACKUP4_W3 volatile.Register32 // 0x48 + BLK0_BACKUP4_W4 volatile.Register32 // 0x4C + BLK0_BACKUP4_W5 volatile.Register32 // 0x50 + BLK1_W1 volatile.Register32 // 0x54 + BLK1_W2 volatile.Register32 // 0x58 + BLK1_W3 volatile.Register32 // 0x5C + BLK1_W4 volatile.Register32 // 0x60 + BLK1_W5 volatile.Register32 // 0x64 + BLK1_W6 volatile.Register32 // 0x68 + BLK1_W7 volatile.Register32 // 0x6C + BLK1_W8 volatile.Register32 // 0x70 + BLK1_W9 volatile.Register32 // 0x74 + BLK2_W1 volatile.Register32 // 0x78 + BLK2_W2 volatile.Register32 // 0x7C + BLK2_W3 volatile.Register32 // 0x80 + BLK2_W4 volatile.Register32 // 0x84 + BLK2_W5 volatile.Register32 // 0x88 + BLK2_W6 volatile.Register32 // 0x8C + BLK2_W7 volatile.Register32 // 0x90 + BLK2_W8 volatile.Register32 // 0x94 + BLK2_W9 volatile.Register32 // 0x98 + BLK2_W10 volatile.Register32 // 0x9C + BLK2_W11 volatile.Register32 // 0xA0 + BLK3_W1 volatile.Register32 // 0xA4 + BLK3_W2 volatile.Register32 // 0xA8 + BLK3_W3 volatile.Register32 // 0xAC + BLK3_W4 volatile.Register32 // 0xB0 + BLK3_W5 volatile.Register32 // 0xB4 + BLK3_W6 volatile.Register32 // 0xB8 + BLK3_W7 volatile.Register32 // 0xBC + BLK3_W8 volatile.Register32 // 0xC0 + BLK3_W9 volatile.Register32 // 0xC4 + BLK3_W10 volatile.Register32 // 0xC8 + BLK3_W11 volatile.Register32 // 0xCC + BLK4_W1 volatile.Register32 // 0xD0 + BLK4_W2 volatile.Register32 // 0xD4 + BLK4_W3 volatile.Register32 // 0xD8 + BLK4_W4 volatile.Register32 // 0xDC + BLK4_W5 volatile.Register32 // 0xE0 + BLK4_W6 volatile.Register32 // 0xE4 + BLK4_W7 volatile.Register32 // 0xE8 + BLK4_W8 volatile.Register32 // 0xEC + BLK4_W9 volatile.Register32 // 0xF0 + BLK4_W10 volatile.Register32 // 0xF4 + BLK4_W11 volatile.Register32 // 0xF8 + BLK5_W1 volatile.Register32 // 0xFC + BLK5_W2 volatile.Register32 // 0x100 + BLK5_W3 volatile.Register32 // 0x104 + BLK5_W4 volatile.Register32 // 0x108 + BLK5_W5 volatile.Register32 // 0x10C + BLK5_W6 volatile.Register32 // 0x110 + BLK5_W7 volatile.Register32 // 0x114 + BLK5_W8 volatile.Register32 // 0x118 + BLK5_W9 volatile.Register32 // 0x11C + BLK5_W10 volatile.Register32 // 0x120 + BLK5_W11 volatile.Register32 // 0x124 + BLK6_W1 volatile.Register32 // 0x128 + BLK6_W2 volatile.Register32 // 0x12C + BLK6_W3 volatile.Register32 // 0x130 + BLK6_W4 volatile.Register32 // 0x134 + BLK6_W5 volatile.Register32 // 0x138 + BLK6_W6 volatile.Register32 // 0x13C + BLK6_W7 volatile.Register32 // 0x140 + BLK6_W8 volatile.Register32 // 0x144 + BLK6_W9 volatile.Register32 // 0x148 + BLK6_W10 volatile.Register32 // 0x14C + BLK6_W11 volatile.Register32 // 0x150 + BLK7_W1 volatile.Register32 // 0x154 + BLK7_W2 volatile.Register32 // 0x158 + BLK7_W3 volatile.Register32 // 0x15C + BLK7_W4 volatile.Register32 // 0x160 + BLK7_W5 volatile.Register32 // 0x164 + BLK7_W6 volatile.Register32 // 0x168 + BLK7_W7 volatile.Register32 // 0x16C + BLK7_W8 volatile.Register32 // 0x170 + BLK7_W9 volatile.Register32 // 0x174 + BLK7_W10 volatile.Register32 // 0x178 + BLK7_W11 volatile.Register32 // 0x17C + BLK8_W1 volatile.Register32 // 0x180 + BLK8_W2 volatile.Register32 // 0x184 + BLK8_W3 volatile.Register32 // 0x188 + BLK8_W4 volatile.Register32 // 0x18C + BLK8_W5 volatile.Register32 // 0x190 + BLK8_W6 volatile.Register32 // 0x194 + BLK8_W7 volatile.Register32 // 0x198 + BLK8_W8 volatile.Register32 // 0x19C + BLK8_W9 volatile.Register32 // 0x1A0 + BLK8_W10 volatile.Register32 // 0x1A4 + BLK8_W11 volatile.Register32 // 0x1A8 + BLK9_W1 volatile.Register32 // 0x1AC + BLK9_W2 volatile.Register32 // 0x1B0 + BLK9_W3 volatile.Register32 // 0x1B4 + BLK9_W4 volatile.Register32 // 0x1B8 + BLK9_W5 volatile.Register32 // 0x1BC + BLK9_W6 volatile.Register32 // 0x1C0 + BLK9_W7 volatile.Register32 // 0x1C4 + BLK9_W8 volatile.Register32 // 0x1C8 + BLK9_W9 volatile.Register32 // 0x1CC + BLK9_W10 volatile.Register32 // 0x1D0 + BLK9_W11 volatile.Register32 // 0x1D4 + BLK10_W1 volatile.Register32 // 0x1D8 + BLK10_W2 volatile.Register32 // 0x1DC + BLK10_W3 volatile.Register32 // 0x1E0 + BLK10_W4 volatile.Register32 // 0x1E4 + BLK10_W5 volatile.Register32 // 0x1E8 + BLK10_W6 volatile.Register32 // 0x1EC + BLK10_W7 volatile.Register32 // 0x1F0 + BLK10_W8 volatile.Register32 // 0x1F4 + BLK10_W9 volatile.Register32 // 0x1F8 + BLK10_W10 volatile.Register32 // 0x1FC + BLK10_W11 volatile.Register32 // 0x200 + CLK volatile.Register32 // 0x204 + APB2OTP_EN volatile.Register32 // 0x208 + DATE volatile.Register32 // 0x20C +} + +// OTP_DEBUG.WR_DIS: Otp debuger block0 data register1. +func (o *OTP_DEBUG_Type) SetWR_DIS(value uint32) { + volatile.StoreUint32(&o.WR_DIS.Reg, value) +} +func (o *OTP_DEBUG_Type) GetWR_DIS() uint32 { + return volatile.LoadUint32(&o.WR_DIS.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W1: Otp debuger block0 data register2. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W1(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W1() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W1.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W2: Otp debuger block0 data register3. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W2(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W2() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W2.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W3: Otp debuger block0 data register4. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W3(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W3() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W3.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W4: Otp debuger block0 data register5. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W4(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W4() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W4.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W5: Otp debuger block0 data register6. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W5(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W5() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W5.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W1: Otp debuger block0 data register7. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W1(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W1() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W1.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W2: Otp debuger block0 data register8. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W2(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W2() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W2.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W3: Otp debuger block0 data register9. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W3(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W3() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W3.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W4: Otp debuger block0 data register10. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W4(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W4() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W4.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W5: Otp debuger block0 data register11. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W5(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W5() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W5.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W1: Otp debuger block0 data register12. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W1(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W1() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W1.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W2: Otp debuger block0 data register13. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W2(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W2() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W2.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W3: Otp debuger block0 data register14. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W3(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W3() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W3.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W4: Otp debuger block0 data register15. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W4(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W4() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W4.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W5: Otp debuger block0 data register16. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W5(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W5() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W5.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W1: Otp debuger block0 data register17. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W1(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W1() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W1.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W2: Otp debuger block0 data register18. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W2(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W2() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W2.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W3: Otp debuger block0 data register19. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W3(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W3() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W3.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W4: Otp debuger block0 data register20. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W4(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W4() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W4.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W5: Otp debuger block0 data register21. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W5(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W5() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W5.Reg) +} + +// OTP_DEBUG.BLK1_W1: Otp debuger block1 data register1. +func (o *OTP_DEBUG_Type) SetBLK1_W1(value uint32) { + volatile.StoreUint32(&o.BLK1_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W1() uint32 { + return volatile.LoadUint32(&o.BLK1_W1.Reg) +} + +// OTP_DEBUG.BLK1_W2: Otp debuger block1 data register2. +func (o *OTP_DEBUG_Type) SetBLK1_W2(value uint32) { + volatile.StoreUint32(&o.BLK1_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W2() uint32 { + return volatile.LoadUint32(&o.BLK1_W2.Reg) +} + +// OTP_DEBUG.BLK1_W3: Otp debuger block1 data register3. +func (o *OTP_DEBUG_Type) SetBLK1_W3(value uint32) { + volatile.StoreUint32(&o.BLK1_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W3() uint32 { + return volatile.LoadUint32(&o.BLK1_W3.Reg) +} + +// OTP_DEBUG.BLK1_W4: Otp debuger block1 data register4. +func (o *OTP_DEBUG_Type) SetBLK1_W4(value uint32) { + volatile.StoreUint32(&o.BLK1_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W4() uint32 { + return volatile.LoadUint32(&o.BLK1_W4.Reg) +} + +// OTP_DEBUG.BLK1_W5: Otp debuger block1 data register5. +func (o *OTP_DEBUG_Type) SetBLK1_W5(value uint32) { + volatile.StoreUint32(&o.BLK1_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W5() uint32 { + return volatile.LoadUint32(&o.BLK1_W5.Reg) +} + +// OTP_DEBUG.BLK1_W6: Otp debuger block1 data register6. +func (o *OTP_DEBUG_Type) SetBLK1_W6(value uint32) { + volatile.StoreUint32(&o.BLK1_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W6() uint32 { + return volatile.LoadUint32(&o.BLK1_W6.Reg) +} + +// OTP_DEBUG.BLK1_W7: Otp debuger block1 data register7. +func (o *OTP_DEBUG_Type) SetBLK1_W7(value uint32) { + volatile.StoreUint32(&o.BLK1_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W7() uint32 { + return volatile.LoadUint32(&o.BLK1_W7.Reg) +} + +// OTP_DEBUG.BLK1_W8: Otp debuger block1 data register8. +func (o *OTP_DEBUG_Type) SetBLK1_W8(value uint32) { + volatile.StoreUint32(&o.BLK1_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W8() uint32 { + return volatile.LoadUint32(&o.BLK1_W8.Reg) +} + +// OTP_DEBUG.BLK1_W9: Otp debuger block1 data register9. +func (o *OTP_DEBUG_Type) SetBLK1_W9(value uint32) { + volatile.StoreUint32(&o.BLK1_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W9() uint32 { + return volatile.LoadUint32(&o.BLK1_W9.Reg) +} + +// OTP_DEBUG.BLK2_W1: Otp debuger block2 data register1. +func (o *OTP_DEBUG_Type) SetBLK2_W1(value uint32) { + volatile.StoreUint32(&o.BLK2_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W1() uint32 { + return volatile.LoadUint32(&o.BLK2_W1.Reg) +} + +// OTP_DEBUG.BLK2_W2: Otp debuger block2 data register2. +func (o *OTP_DEBUG_Type) SetBLK2_W2(value uint32) { + volatile.StoreUint32(&o.BLK2_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W2() uint32 { + return volatile.LoadUint32(&o.BLK2_W2.Reg) +} + +// OTP_DEBUG.BLK2_W3: Otp debuger block2 data register3. +func (o *OTP_DEBUG_Type) SetBLK2_W3(value uint32) { + volatile.StoreUint32(&o.BLK2_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W3() uint32 { + return volatile.LoadUint32(&o.BLK2_W3.Reg) +} + +// OTP_DEBUG.BLK2_W4: Otp debuger block2 data register4. +func (o *OTP_DEBUG_Type) SetBLK2_W4(value uint32) { + volatile.StoreUint32(&o.BLK2_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W4() uint32 { + return volatile.LoadUint32(&o.BLK2_W4.Reg) +} + +// OTP_DEBUG.BLK2_W5: Otp debuger block2 data register5. +func (o *OTP_DEBUG_Type) SetBLK2_W5(value uint32) { + volatile.StoreUint32(&o.BLK2_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W5() uint32 { + return volatile.LoadUint32(&o.BLK2_W5.Reg) +} + +// OTP_DEBUG.BLK2_W6: Otp debuger block2 data register6. +func (o *OTP_DEBUG_Type) SetBLK2_W6(value uint32) { + volatile.StoreUint32(&o.BLK2_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W6() uint32 { + return volatile.LoadUint32(&o.BLK2_W6.Reg) +} + +// OTP_DEBUG.BLK2_W7: Otp debuger block2 data register7. +func (o *OTP_DEBUG_Type) SetBLK2_W7(value uint32) { + volatile.StoreUint32(&o.BLK2_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W7() uint32 { + return volatile.LoadUint32(&o.BLK2_W7.Reg) +} + +// OTP_DEBUG.BLK2_W8: Otp debuger block2 data register8. +func (o *OTP_DEBUG_Type) SetBLK2_W8(value uint32) { + volatile.StoreUint32(&o.BLK2_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W8() uint32 { + return volatile.LoadUint32(&o.BLK2_W8.Reg) +} + +// OTP_DEBUG.BLK2_W9: Otp debuger block2 data register9. +func (o *OTP_DEBUG_Type) SetBLK2_W9(value uint32) { + volatile.StoreUint32(&o.BLK2_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W9() uint32 { + return volatile.LoadUint32(&o.BLK2_W9.Reg) +} + +// OTP_DEBUG.BLK2_W10: Otp debuger block2 data register10. +func (o *OTP_DEBUG_Type) SetBLK2_W10(value uint32) { + volatile.StoreUint32(&o.BLK2_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W10() uint32 { + return volatile.LoadUint32(&o.BLK2_W10.Reg) +} + +// OTP_DEBUG.BLK2_W11: Otp debuger block2 data register11. +func (o *OTP_DEBUG_Type) SetBLK2_W11(value uint32) { + volatile.StoreUint32(&o.BLK2_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W11() uint32 { + return volatile.LoadUint32(&o.BLK2_W11.Reg) +} + +// OTP_DEBUG.BLK3_W1: Otp debuger block3 data register1. +func (o *OTP_DEBUG_Type) SetBLK3_W1(value uint32) { + volatile.StoreUint32(&o.BLK3_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W1() uint32 { + return volatile.LoadUint32(&o.BLK3_W1.Reg) +} + +// OTP_DEBUG.BLK3_W2: Otp debuger block3 data register2. +func (o *OTP_DEBUG_Type) SetBLK3_W2(value uint32) { + volatile.StoreUint32(&o.BLK3_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W2() uint32 { + return volatile.LoadUint32(&o.BLK3_W2.Reg) +} + +// OTP_DEBUG.BLK3_W3: Otp debuger block3 data register3. +func (o *OTP_DEBUG_Type) SetBLK3_W3(value uint32) { + volatile.StoreUint32(&o.BLK3_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W3() uint32 { + return volatile.LoadUint32(&o.BLK3_W3.Reg) +} + +// OTP_DEBUG.BLK3_W4: Otp debuger block3 data register4. +func (o *OTP_DEBUG_Type) SetBLK3_W4(value uint32) { + volatile.StoreUint32(&o.BLK3_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W4() uint32 { + return volatile.LoadUint32(&o.BLK3_W4.Reg) +} + +// OTP_DEBUG.BLK3_W5: Otp debuger block3 data register5. +func (o *OTP_DEBUG_Type) SetBLK3_W5(value uint32) { + volatile.StoreUint32(&o.BLK3_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W5() uint32 { + return volatile.LoadUint32(&o.BLK3_W5.Reg) +} + +// OTP_DEBUG.BLK3_W6: Otp debuger block3 data register6. +func (o *OTP_DEBUG_Type) SetBLK3_W6(value uint32) { + volatile.StoreUint32(&o.BLK3_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W6() uint32 { + return volatile.LoadUint32(&o.BLK3_W6.Reg) +} + +// OTP_DEBUG.BLK3_W7: Otp debuger block3 data register7. +func (o *OTP_DEBUG_Type) SetBLK3_W7(value uint32) { + volatile.StoreUint32(&o.BLK3_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W7() uint32 { + return volatile.LoadUint32(&o.BLK3_W7.Reg) +} + +// OTP_DEBUG.BLK3_W8: Otp debuger block3 data register8. +func (o *OTP_DEBUG_Type) SetBLK3_W8(value uint32) { + volatile.StoreUint32(&o.BLK3_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W8() uint32 { + return volatile.LoadUint32(&o.BLK3_W8.Reg) +} + +// OTP_DEBUG.BLK3_W9: Otp debuger block3 data register9. +func (o *OTP_DEBUG_Type) SetBLK3_W9(value uint32) { + volatile.StoreUint32(&o.BLK3_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W9() uint32 { + return volatile.LoadUint32(&o.BLK3_W9.Reg) +} + +// OTP_DEBUG.BLK3_W10: Otp debuger block3 data register10. +func (o *OTP_DEBUG_Type) SetBLK3_W10(value uint32) { + volatile.StoreUint32(&o.BLK3_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W10() uint32 { + return volatile.LoadUint32(&o.BLK3_W10.Reg) +} + +// OTP_DEBUG.BLK3_W11: Otp debuger block3 data register11. +func (o *OTP_DEBUG_Type) SetBLK3_W11(value uint32) { + volatile.StoreUint32(&o.BLK3_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W11() uint32 { + return volatile.LoadUint32(&o.BLK3_W11.Reg) +} + +// OTP_DEBUG.BLK4_W1: Otp debuger block4 data register1. +func (o *OTP_DEBUG_Type) SetBLK4_W1(value uint32) { + volatile.StoreUint32(&o.BLK4_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W1() uint32 { + return volatile.LoadUint32(&o.BLK4_W1.Reg) +} + +// OTP_DEBUG.BLK4_W2: Otp debuger block4 data register2. +func (o *OTP_DEBUG_Type) SetBLK4_W2(value uint32) { + volatile.StoreUint32(&o.BLK4_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W2() uint32 { + return volatile.LoadUint32(&o.BLK4_W2.Reg) +} + +// OTP_DEBUG.BLK4_W3: Otp debuger block4 data register3. +func (o *OTP_DEBUG_Type) SetBLK4_W3(value uint32) { + volatile.StoreUint32(&o.BLK4_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W3() uint32 { + return volatile.LoadUint32(&o.BLK4_W3.Reg) +} + +// OTP_DEBUG.BLK4_W4: Otp debuger block4 data register4. +func (o *OTP_DEBUG_Type) SetBLK4_W4(value uint32) { + volatile.StoreUint32(&o.BLK4_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W4() uint32 { + return volatile.LoadUint32(&o.BLK4_W4.Reg) +} + +// OTP_DEBUG.BLK4_W5: Otp debuger block4 data register5. +func (o *OTP_DEBUG_Type) SetBLK4_W5(value uint32) { + volatile.StoreUint32(&o.BLK4_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W5() uint32 { + return volatile.LoadUint32(&o.BLK4_W5.Reg) +} + +// OTP_DEBUG.BLK4_W6: Otp debuger block4 data register6. +func (o *OTP_DEBUG_Type) SetBLK4_W6(value uint32) { + volatile.StoreUint32(&o.BLK4_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W6() uint32 { + return volatile.LoadUint32(&o.BLK4_W6.Reg) +} + +// OTP_DEBUG.BLK4_W7: Otp debuger block4 data register7. +func (o *OTP_DEBUG_Type) SetBLK4_W7(value uint32) { + volatile.StoreUint32(&o.BLK4_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W7() uint32 { + return volatile.LoadUint32(&o.BLK4_W7.Reg) +} + +// OTP_DEBUG.BLK4_W8: Otp debuger block4 data register8. +func (o *OTP_DEBUG_Type) SetBLK4_W8(value uint32) { + volatile.StoreUint32(&o.BLK4_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W8() uint32 { + return volatile.LoadUint32(&o.BLK4_W8.Reg) +} + +// OTP_DEBUG.BLK4_W9: Otp debuger block4 data register9. +func (o *OTP_DEBUG_Type) SetBLK4_W9(value uint32) { + volatile.StoreUint32(&o.BLK4_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W9() uint32 { + return volatile.LoadUint32(&o.BLK4_W9.Reg) +} + +// OTP_DEBUG.BLK4_W10: Otp debuger block4 data registe10. +func (o *OTP_DEBUG_Type) SetBLK4_W10(value uint32) { + volatile.StoreUint32(&o.BLK4_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W10() uint32 { + return volatile.LoadUint32(&o.BLK4_W10.Reg) +} + +// OTP_DEBUG.BLK4_W11: Otp debuger block4 data register11. +func (o *OTP_DEBUG_Type) SetBLK4_W11(value uint32) { + volatile.StoreUint32(&o.BLK4_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W11() uint32 { + return volatile.LoadUint32(&o.BLK4_W11.Reg) +} + +// OTP_DEBUG.BLK5_W1: Otp debuger block5 data register1. +func (o *OTP_DEBUG_Type) SetBLK5_W1(value uint32) { + volatile.StoreUint32(&o.BLK5_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W1() uint32 { + return volatile.LoadUint32(&o.BLK5_W1.Reg) +} + +// OTP_DEBUG.BLK5_W2: Otp debuger block5 data register2. +func (o *OTP_DEBUG_Type) SetBLK5_W2(value uint32) { + volatile.StoreUint32(&o.BLK5_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W2() uint32 { + return volatile.LoadUint32(&o.BLK5_W2.Reg) +} + +// OTP_DEBUG.BLK5_W3: Otp debuger block5 data register3. +func (o *OTP_DEBUG_Type) SetBLK5_W3(value uint32) { + volatile.StoreUint32(&o.BLK5_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W3() uint32 { + return volatile.LoadUint32(&o.BLK5_W3.Reg) +} + +// OTP_DEBUG.BLK5_W4: Otp debuger block5 data register4. +func (o *OTP_DEBUG_Type) SetBLK5_W4(value uint32) { + volatile.StoreUint32(&o.BLK5_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W4() uint32 { + return volatile.LoadUint32(&o.BLK5_W4.Reg) +} + +// OTP_DEBUG.BLK5_W5: Otp debuger block5 data register5. +func (o *OTP_DEBUG_Type) SetBLK5_W5(value uint32) { + volatile.StoreUint32(&o.BLK5_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W5() uint32 { + return volatile.LoadUint32(&o.BLK5_W5.Reg) +} + +// OTP_DEBUG.BLK5_W6: Otp debuger block5 data register6. +func (o *OTP_DEBUG_Type) SetBLK5_W6(value uint32) { + volatile.StoreUint32(&o.BLK5_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W6() uint32 { + return volatile.LoadUint32(&o.BLK5_W6.Reg) +} + +// OTP_DEBUG.BLK5_W7: Otp debuger block5 data register7. +func (o *OTP_DEBUG_Type) SetBLK5_W7(value uint32) { + volatile.StoreUint32(&o.BLK5_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W7() uint32 { + return volatile.LoadUint32(&o.BLK5_W7.Reg) +} + +// OTP_DEBUG.BLK5_W8: Otp debuger block5 data register8. +func (o *OTP_DEBUG_Type) SetBLK5_W8(value uint32) { + volatile.StoreUint32(&o.BLK5_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W8() uint32 { + return volatile.LoadUint32(&o.BLK5_W8.Reg) +} + +// OTP_DEBUG.BLK5_W9: Otp debuger block5 data register9. +func (o *OTP_DEBUG_Type) SetBLK5_W9(value uint32) { + volatile.StoreUint32(&o.BLK5_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W9() uint32 { + return volatile.LoadUint32(&o.BLK5_W9.Reg) +} + +// OTP_DEBUG.BLK5_W10: Otp debuger block5 data register10. +func (o *OTP_DEBUG_Type) SetBLK5_W10(value uint32) { + volatile.StoreUint32(&o.BLK5_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W10() uint32 { + return volatile.LoadUint32(&o.BLK5_W10.Reg) +} + +// OTP_DEBUG.BLK5_W11: Otp debuger block5 data register11. +func (o *OTP_DEBUG_Type) SetBLK5_W11(value uint32) { + volatile.StoreUint32(&o.BLK5_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W11() uint32 { + return volatile.LoadUint32(&o.BLK5_W11.Reg) +} + +// OTP_DEBUG.BLK6_W1: Otp debuger block6 data register1. +func (o *OTP_DEBUG_Type) SetBLK6_W1(value uint32) { + volatile.StoreUint32(&o.BLK6_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W1() uint32 { + return volatile.LoadUint32(&o.BLK6_W1.Reg) +} + +// OTP_DEBUG.BLK6_W2: Otp debuger block6 data register2. +func (o *OTP_DEBUG_Type) SetBLK6_W2(value uint32) { + volatile.StoreUint32(&o.BLK6_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W2() uint32 { + return volatile.LoadUint32(&o.BLK6_W2.Reg) +} + +// OTP_DEBUG.BLK6_W3: Otp debuger block6 data register3. +func (o *OTP_DEBUG_Type) SetBLK6_W3(value uint32) { + volatile.StoreUint32(&o.BLK6_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W3() uint32 { + return volatile.LoadUint32(&o.BLK6_W3.Reg) +} + +// OTP_DEBUG.BLK6_W4: Otp debuger block6 data register4. +func (o *OTP_DEBUG_Type) SetBLK6_W4(value uint32) { + volatile.StoreUint32(&o.BLK6_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W4() uint32 { + return volatile.LoadUint32(&o.BLK6_W4.Reg) +} + +// OTP_DEBUG.BLK6_W5: Otp debuger block6 data register5. +func (o *OTP_DEBUG_Type) SetBLK6_W5(value uint32) { + volatile.StoreUint32(&o.BLK6_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W5() uint32 { + return volatile.LoadUint32(&o.BLK6_W5.Reg) +} + +// OTP_DEBUG.BLK6_W6: Otp debuger block6 data register6. +func (o *OTP_DEBUG_Type) SetBLK6_W6(value uint32) { + volatile.StoreUint32(&o.BLK6_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W6() uint32 { + return volatile.LoadUint32(&o.BLK6_W6.Reg) +} + +// OTP_DEBUG.BLK6_W7: Otp debuger block6 data register7. +func (o *OTP_DEBUG_Type) SetBLK6_W7(value uint32) { + volatile.StoreUint32(&o.BLK6_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W7() uint32 { + return volatile.LoadUint32(&o.BLK6_W7.Reg) +} + +// OTP_DEBUG.BLK6_W8: Otp debuger block6 data register8. +func (o *OTP_DEBUG_Type) SetBLK6_W8(value uint32) { + volatile.StoreUint32(&o.BLK6_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W8() uint32 { + return volatile.LoadUint32(&o.BLK6_W8.Reg) +} + +// OTP_DEBUG.BLK6_W9: Otp debuger block6 data register9. +func (o *OTP_DEBUG_Type) SetBLK6_W9(value uint32) { + volatile.StoreUint32(&o.BLK6_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W9() uint32 { + return volatile.LoadUint32(&o.BLK6_W9.Reg) +} + +// OTP_DEBUG.BLK6_W10: Otp debuger block6 data register10. +func (o *OTP_DEBUG_Type) SetBLK6_W10(value uint32) { + volatile.StoreUint32(&o.BLK6_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W10() uint32 { + return volatile.LoadUint32(&o.BLK6_W10.Reg) +} + +// OTP_DEBUG.BLK6_W11: Otp debuger block6 data register11. +func (o *OTP_DEBUG_Type) SetBLK6_W11(value uint32) { + volatile.StoreUint32(&o.BLK6_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W11() uint32 { + return volatile.LoadUint32(&o.BLK6_W11.Reg) +} + +// OTP_DEBUG.BLK7_W1: Otp debuger block7 data register1. +func (o *OTP_DEBUG_Type) SetBLK7_W1(value uint32) { + volatile.StoreUint32(&o.BLK7_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W1() uint32 { + return volatile.LoadUint32(&o.BLK7_W1.Reg) +} + +// OTP_DEBUG.BLK7_W2: Otp debuger block7 data register2. +func (o *OTP_DEBUG_Type) SetBLK7_W2(value uint32) { + volatile.StoreUint32(&o.BLK7_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W2() uint32 { + return volatile.LoadUint32(&o.BLK7_W2.Reg) +} + +// OTP_DEBUG.BLK7_W3: Otp debuger block7 data register3. +func (o *OTP_DEBUG_Type) SetBLK7_W3(value uint32) { + volatile.StoreUint32(&o.BLK7_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W3() uint32 { + return volatile.LoadUint32(&o.BLK7_W3.Reg) +} + +// OTP_DEBUG.BLK7_W4: Otp debuger block7 data register4. +func (o *OTP_DEBUG_Type) SetBLK7_W4(value uint32) { + volatile.StoreUint32(&o.BLK7_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W4() uint32 { + return volatile.LoadUint32(&o.BLK7_W4.Reg) +} + +// OTP_DEBUG.BLK7_W5: Otp debuger block7 data register5. +func (o *OTP_DEBUG_Type) SetBLK7_W5(value uint32) { + volatile.StoreUint32(&o.BLK7_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W5() uint32 { + return volatile.LoadUint32(&o.BLK7_W5.Reg) +} + +// OTP_DEBUG.BLK7_W6: Otp debuger block7 data register6. +func (o *OTP_DEBUG_Type) SetBLK7_W6(value uint32) { + volatile.StoreUint32(&o.BLK7_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W6() uint32 { + return volatile.LoadUint32(&o.BLK7_W6.Reg) +} + +// OTP_DEBUG.BLK7_W7: Otp debuger block7 data register7. +func (o *OTP_DEBUG_Type) SetBLK7_W7(value uint32) { + volatile.StoreUint32(&o.BLK7_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W7() uint32 { + return volatile.LoadUint32(&o.BLK7_W7.Reg) +} + +// OTP_DEBUG.BLK7_W8: Otp debuger block7 data register8. +func (o *OTP_DEBUG_Type) SetBLK7_W8(value uint32) { + volatile.StoreUint32(&o.BLK7_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W8() uint32 { + return volatile.LoadUint32(&o.BLK7_W8.Reg) +} + +// OTP_DEBUG.BLK7_W9: Otp debuger block7 data register9. +func (o *OTP_DEBUG_Type) SetBLK7_W9(value uint32) { + volatile.StoreUint32(&o.BLK7_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W9() uint32 { + return volatile.LoadUint32(&o.BLK7_W9.Reg) +} + +// OTP_DEBUG.BLK7_W10: Otp debuger block7 data register10. +func (o *OTP_DEBUG_Type) SetBLK7_W10(value uint32) { + volatile.StoreUint32(&o.BLK7_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W10() uint32 { + return volatile.LoadUint32(&o.BLK7_W10.Reg) +} + +// OTP_DEBUG.BLK7_W11: Otp debuger block7 data register11. +func (o *OTP_DEBUG_Type) SetBLK7_W11(value uint32) { + volatile.StoreUint32(&o.BLK7_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W11() uint32 { + return volatile.LoadUint32(&o.BLK7_W11.Reg) +} + +// OTP_DEBUG.BLK8_W1: Otp debuger block8 data register1. +func (o *OTP_DEBUG_Type) SetBLK8_W1(value uint32) { + volatile.StoreUint32(&o.BLK8_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W1() uint32 { + return volatile.LoadUint32(&o.BLK8_W1.Reg) +} + +// OTP_DEBUG.BLK8_W2: Otp debuger block8 data register2. +func (o *OTP_DEBUG_Type) SetBLK8_W2(value uint32) { + volatile.StoreUint32(&o.BLK8_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W2() uint32 { + return volatile.LoadUint32(&o.BLK8_W2.Reg) +} + +// OTP_DEBUG.BLK8_W3: Otp debuger block8 data register3. +func (o *OTP_DEBUG_Type) SetBLK8_W3(value uint32) { + volatile.StoreUint32(&o.BLK8_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W3() uint32 { + return volatile.LoadUint32(&o.BLK8_W3.Reg) +} + +// OTP_DEBUG.BLK8_W4: Otp debuger block8 data register4. +func (o *OTP_DEBUG_Type) SetBLK8_W4(value uint32) { + volatile.StoreUint32(&o.BLK8_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W4() uint32 { + return volatile.LoadUint32(&o.BLK8_W4.Reg) +} + +// OTP_DEBUG.BLK8_W5: Otp debuger block8 data register5. +func (o *OTP_DEBUG_Type) SetBLK8_W5(value uint32) { + volatile.StoreUint32(&o.BLK8_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W5() uint32 { + return volatile.LoadUint32(&o.BLK8_W5.Reg) +} + +// OTP_DEBUG.BLK8_W6: Otp debuger block8 data register6. +func (o *OTP_DEBUG_Type) SetBLK8_W6(value uint32) { + volatile.StoreUint32(&o.BLK8_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W6() uint32 { + return volatile.LoadUint32(&o.BLK8_W6.Reg) +} + +// OTP_DEBUG.BLK8_W7: Otp debuger block8 data register7. +func (o *OTP_DEBUG_Type) SetBLK8_W7(value uint32) { + volatile.StoreUint32(&o.BLK8_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W7() uint32 { + return volatile.LoadUint32(&o.BLK8_W7.Reg) +} + +// OTP_DEBUG.BLK8_W8: Otp debuger block8 data register8. +func (o *OTP_DEBUG_Type) SetBLK8_W8(value uint32) { + volatile.StoreUint32(&o.BLK8_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W8() uint32 { + return volatile.LoadUint32(&o.BLK8_W8.Reg) +} + +// OTP_DEBUG.BLK8_W9: Otp debuger block8 data register9. +func (o *OTP_DEBUG_Type) SetBLK8_W9(value uint32) { + volatile.StoreUint32(&o.BLK8_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W9() uint32 { + return volatile.LoadUint32(&o.BLK8_W9.Reg) +} + +// OTP_DEBUG.BLK8_W10: Otp debuger block8 data register10. +func (o *OTP_DEBUG_Type) SetBLK8_W10(value uint32) { + volatile.StoreUint32(&o.BLK8_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W10() uint32 { + return volatile.LoadUint32(&o.BLK8_W10.Reg) +} + +// OTP_DEBUG.BLK8_W11: Otp debuger block8 data register11. +func (o *OTP_DEBUG_Type) SetBLK8_W11(value uint32) { + volatile.StoreUint32(&o.BLK8_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W11() uint32 { + return volatile.LoadUint32(&o.BLK8_W11.Reg) +} + +// OTP_DEBUG.BLK9_W1: Otp debuger block9 data register1. +func (o *OTP_DEBUG_Type) SetBLK9_W1(value uint32) { + volatile.StoreUint32(&o.BLK9_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W1() uint32 { + return volatile.LoadUint32(&o.BLK9_W1.Reg) +} + +// OTP_DEBUG.BLK9_W2: Otp debuger block9 data register2. +func (o *OTP_DEBUG_Type) SetBLK9_W2(value uint32) { + volatile.StoreUint32(&o.BLK9_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W2() uint32 { + return volatile.LoadUint32(&o.BLK9_W2.Reg) +} + +// OTP_DEBUG.BLK9_W3: Otp debuger block9 data register3. +func (o *OTP_DEBUG_Type) SetBLK9_W3(value uint32) { + volatile.StoreUint32(&o.BLK9_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W3() uint32 { + return volatile.LoadUint32(&o.BLK9_W3.Reg) +} + +// OTP_DEBUG.BLK9_W4: Otp debuger block9 data register4. +func (o *OTP_DEBUG_Type) SetBLK9_W4(value uint32) { + volatile.StoreUint32(&o.BLK9_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W4() uint32 { + return volatile.LoadUint32(&o.BLK9_W4.Reg) +} + +// OTP_DEBUG.BLK9_W5: Otp debuger block9 data register5. +func (o *OTP_DEBUG_Type) SetBLK9_W5(value uint32) { + volatile.StoreUint32(&o.BLK9_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W5() uint32 { + return volatile.LoadUint32(&o.BLK9_W5.Reg) +} + +// OTP_DEBUG.BLK9_W6: Otp debuger block9 data register6. +func (o *OTP_DEBUG_Type) SetBLK9_W6(value uint32) { + volatile.StoreUint32(&o.BLK9_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W6() uint32 { + return volatile.LoadUint32(&o.BLK9_W6.Reg) +} + +// OTP_DEBUG.BLK9_W7: Otp debuger block9 data register7. +func (o *OTP_DEBUG_Type) SetBLK9_W7(value uint32) { + volatile.StoreUint32(&o.BLK9_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W7() uint32 { + return volatile.LoadUint32(&o.BLK9_W7.Reg) +} + +// OTP_DEBUG.BLK9_W8: Otp debuger block9 data register8. +func (o *OTP_DEBUG_Type) SetBLK9_W8(value uint32) { + volatile.StoreUint32(&o.BLK9_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W8() uint32 { + return volatile.LoadUint32(&o.BLK9_W8.Reg) +} + +// OTP_DEBUG.BLK9_W9: Otp debuger block9 data register9. +func (o *OTP_DEBUG_Type) SetBLK9_W9(value uint32) { + volatile.StoreUint32(&o.BLK9_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W9() uint32 { + return volatile.LoadUint32(&o.BLK9_W9.Reg) +} + +// OTP_DEBUG.BLK9_W10: Otp debuger block9 data register10. +func (o *OTP_DEBUG_Type) SetBLK9_W10(value uint32) { + volatile.StoreUint32(&o.BLK9_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W10() uint32 { + return volatile.LoadUint32(&o.BLK9_W10.Reg) +} + +// OTP_DEBUG.BLK9_W11: Otp debuger block9 data register11. +func (o *OTP_DEBUG_Type) SetBLK9_W11(value uint32) { + volatile.StoreUint32(&o.BLK9_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W11() uint32 { + return volatile.LoadUint32(&o.BLK9_W11.Reg) +} + +// OTP_DEBUG.BLK10_W1: Otp debuger block10 data register1. +func (o *OTP_DEBUG_Type) SetBLK10_W1(value uint32) { + volatile.StoreUint32(&o.BLK10_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W1() uint32 { + return volatile.LoadUint32(&o.BLK10_W1.Reg) +} + +// OTP_DEBUG.BLK10_W2: Otp debuger block10 data register2. +func (o *OTP_DEBUG_Type) SetBLK10_W2(value uint32) { + volatile.StoreUint32(&o.BLK10_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W2() uint32 { + return volatile.LoadUint32(&o.BLK10_W2.Reg) +} + +// OTP_DEBUG.BLK10_W3: Otp debuger block10 data register3. +func (o *OTP_DEBUG_Type) SetBLK10_W3(value uint32) { + volatile.StoreUint32(&o.BLK10_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W3() uint32 { + return volatile.LoadUint32(&o.BLK10_W3.Reg) +} + +// OTP_DEBUG.BLK10_W4: Otp debuger block10 data register4. +func (o *OTP_DEBUG_Type) SetBLK10_W4(value uint32) { + volatile.StoreUint32(&o.BLK10_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W4() uint32 { + return volatile.LoadUint32(&o.BLK10_W4.Reg) +} + +// OTP_DEBUG.BLK10_W5: Otp debuger block10 data register5. +func (o *OTP_DEBUG_Type) SetBLK10_W5(value uint32) { + volatile.StoreUint32(&o.BLK10_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W5() uint32 { + return volatile.LoadUint32(&o.BLK10_W5.Reg) +} + +// OTP_DEBUG.BLK10_W6: Otp debuger block10 data register6. +func (o *OTP_DEBUG_Type) SetBLK10_W6(value uint32) { + volatile.StoreUint32(&o.BLK10_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W6() uint32 { + return volatile.LoadUint32(&o.BLK10_W6.Reg) +} + +// OTP_DEBUG.BLK10_W7: Otp debuger block10 data register7. +func (o *OTP_DEBUG_Type) SetBLK10_W7(value uint32) { + volatile.StoreUint32(&o.BLK10_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W7() uint32 { + return volatile.LoadUint32(&o.BLK10_W7.Reg) +} + +// OTP_DEBUG.BLK10_W8: Otp debuger block10 data register8. +func (o *OTP_DEBUG_Type) SetBLK10_W8(value uint32) { + volatile.StoreUint32(&o.BLK10_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W8() uint32 { + return volatile.LoadUint32(&o.BLK10_W8.Reg) +} + +// OTP_DEBUG.BLK10_W9: Otp debuger block10 data register9. +func (o *OTP_DEBUG_Type) SetBLK10_W9(value uint32) { + volatile.StoreUint32(&o.BLK10_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W9() uint32 { + return volatile.LoadUint32(&o.BLK10_W9.Reg) +} + +// OTP_DEBUG.BLK10_W10: Otp debuger block10 data register10. +func (o *OTP_DEBUG_Type) SetBLK10_W10(value uint32) { + volatile.StoreUint32(&o.BLK10_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W10() uint32 { + return volatile.LoadUint32(&o.BLK10_W10.Reg) +} + +// OTP_DEBUG.BLK10_W11: Otp debuger block10 data register11. +func (o *OTP_DEBUG_Type) SetBLK10_W11(value uint32) { + volatile.StoreUint32(&o.BLK10_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W11() uint32 { + return volatile.LoadUint32(&o.BLK10_W11.Reg) +} + +// OTP_DEBUG.CLK: Otp debuger clk_en configuration register. +func (o *OTP_DEBUG_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *OTP_DEBUG_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} + +// OTP_DEBUG.APB2OTP_EN: Otp_debuger apb2otp enable configuration register. +func (o *OTP_DEBUG_Type) SetAPB2OTP_EN(value uint32) { + volatile.StoreUint32(&o.APB2OTP_EN.Reg, volatile.LoadUint32(&o.APB2OTP_EN.Reg)&^(0x1)|value) +} +func (o *OTP_DEBUG_Type) GetAPB2OTP_EN() uint32 { + return volatile.LoadUint32(&o.APB2OTP_EN.Reg) & 0x1 +} + +// OTP_DEBUG.DATE: eFuse version register. +func (o *OTP_DEBUG_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *OTP_DEBUG_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Parallel IO Controller +type PARL_IO_Type struct { + RX_CFG0 volatile.Register32 // 0x0 + RX_CFG1 volatile.Register32 // 0x4 + TX_CFG0 volatile.Register32 // 0x8 + TX_CFG1 volatile.Register32 // 0xC + ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_RAW volatile.Register32 // 0x18 + INT_ST volatile.Register32 // 0x1C + INT_CLR volatile.Register32 // 0x20 + _ [252]byte + CLK volatile.Register32 // 0x120 + _ [728]byte + VERSION volatile.Register32 // 0x3FC +} + +// PARL_IO.RX_CFG0: Parallel RX module configuration register0. +func (o *PARL_IO_Type) SetRX_CFG0_RX_EOF_GEN_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_EOF_GEN_SEL() uint32 { + return volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_DATA_BYTELEN(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x3fffc)|value<<2) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_DATA_BYTELEN() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x3fffc) >> 2 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_SW_EN(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x40000)|value<<18) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_SW_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x40000) >> 18 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_PULSE_SUBMODE_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x780000)|value<<19) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_PULSE_SUBMODE_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x780000) >> 19 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_LEVEL_SUBMODE_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x800000)|value<<23) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_LEVEL_SUBMODE_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x800000) >> 23 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_SMP_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_SMP_MODE_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x3000000) >> 24 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_CLK_EDGE_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x4000000)|value<<26) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_CLK_EDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x4000000) >> 26 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_BIT_PACK_ORDER(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x8000000)|value<<27) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_BIT_PACK_ORDER() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x8000000) >> 27 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_BUS_WID_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x70000000)|value<<28) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_BUS_WID_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x70000000) >> 28 +} +func (o *PARL_IO_Type) SetRX_CFG0_RX_FIFO_SRST(value uint32) { + volatile.StoreUint32(&o.RX_CFG0.Reg, volatile.LoadUint32(&o.RX_CFG0.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetRX_CFG0_RX_FIFO_SRST() uint32 { + return (volatile.LoadUint32(&o.RX_CFG0.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.RX_CFG1: Parallel RX module configuration register1. +func (o *PARL_IO_Type) SetRX_CFG1_RX_REG_UPDATE(value uint32) { + volatile.StoreUint32(&o.RX_CFG1.Reg, volatile.LoadUint32(&o.RX_CFG1.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetRX_CFG1_RX_REG_UPDATE() uint32 { + return (volatile.LoadUint32(&o.RX_CFG1.Reg) & 0x4) >> 2 +} +func (o *PARL_IO_Type) SetRX_CFG1_RX_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.RX_CFG1.Reg, volatile.LoadUint32(&o.RX_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *PARL_IO_Type) GetRX_CFG1_RX_TIMEOUT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CFG1.Reg) & 0x8) >> 3 +} +func (o *PARL_IO_Type) SetRX_CFG1_RX_EXT_EN_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CFG1.Reg, volatile.LoadUint32(&o.RX_CFG1.Reg)&^(0xf000)|value<<12) +} +func (o *PARL_IO_Type) GetRX_CFG1_RX_EXT_EN_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CFG1.Reg) & 0xf000) >> 12 +} +func (o *PARL_IO_Type) SetRX_CFG1_RX_TIMEOUT_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.RX_CFG1.Reg, volatile.LoadUint32(&o.RX_CFG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PARL_IO_Type) GetRX_CFG1_RX_TIMEOUT_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.RX_CFG1.Reg) & 0xffff0000) >> 16 +} + +// PARL_IO.TX_CFG0: Parallel TX module configuration register0. +func (o *PARL_IO_Type) SetTX_CFG0_TX_BYTELEN(value uint32) { + volatile.StoreUint32(&o.TX_CFG0.Reg, volatile.LoadUint32(&o.TX_CFG0.Reg)&^(0x3fffc)|value<<2) +} +func (o *PARL_IO_Type) GetTX_CFG0_TX_BYTELEN() uint32 { + return (volatile.LoadUint32(&o.TX_CFG0.Reg) & 0x3fffc) >> 2 +} +func (o *PARL_IO_Type) SetTX_CFG0_TX_GATING_EN(value uint32) { + volatile.StoreUint32(&o.TX_CFG0.Reg, volatile.LoadUint32(&o.TX_CFG0.Reg)&^(0x40000)|value<<18) +} +func (o *PARL_IO_Type) GetTX_CFG0_TX_GATING_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CFG0.Reg) & 0x40000) >> 18 +} +func (o *PARL_IO_Type) SetTX_CFG0_TX_START(value uint32) { + volatile.StoreUint32(&o.TX_CFG0.Reg, volatile.LoadUint32(&o.TX_CFG0.Reg)&^(0x80000)|value<<19) +} +func (o *PARL_IO_Type) GetTX_CFG0_TX_START() uint32 { + return (volatile.LoadUint32(&o.TX_CFG0.Reg) & 0x80000) >> 19 +} +func (o *PARL_IO_Type) SetTX_CFG0_TX_HW_VALID_EN(value uint32) { + volatile.StoreUint32(&o.TX_CFG0.Reg, volatile.LoadUint32(&o.TX_CFG0.Reg)&^(0x100000)|value<<20) +} +func (o *PARL_IO_Type) GetTX_CFG0_TX_HW_VALID_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CFG0.Reg) & 0x100000) >> 20 +} +func (o *PARL_IO_Type) SetTX_CFG0_TX_SMP_EDGE_SEL(value uint32) { + volatile.StoreUint32(&o.TX_CFG0.Reg, volatile.LoadUint32(&o.TX_CFG0.Reg)&^(0x2000000)|value<<25) +} +func (o *PARL_IO_Type) GetTX_CFG0_TX_SMP_EDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_CFG0.Reg) & 0x2000000) >> 25 +} +func (o *PARL_IO_Type) SetTX_CFG0_TX_BIT_UNPACK_ORDER(value uint32) { + volatile.StoreUint32(&o.TX_CFG0.Reg, volatile.LoadUint32(&o.TX_CFG0.Reg)&^(0x4000000)|value<<26) +} +func (o *PARL_IO_Type) GetTX_CFG0_TX_BIT_UNPACK_ORDER() uint32 { + return (volatile.LoadUint32(&o.TX_CFG0.Reg) & 0x4000000) >> 26 +} +func (o *PARL_IO_Type) SetTX_CFG0_TX_BUS_WID_SEL(value uint32) { + volatile.StoreUint32(&o.TX_CFG0.Reg, volatile.LoadUint32(&o.TX_CFG0.Reg)&^(0x38000000)|value<<27) +} +func (o *PARL_IO_Type) GetTX_CFG0_TX_BUS_WID_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_CFG0.Reg) & 0x38000000) >> 27 +} +func (o *PARL_IO_Type) SetTX_CFG0_TX_FIFO_SRST(value uint32) { + volatile.StoreUint32(&o.TX_CFG0.Reg, volatile.LoadUint32(&o.TX_CFG0.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetTX_CFG0_TX_FIFO_SRST() uint32 { + return (volatile.LoadUint32(&o.TX_CFG0.Reg) & 0x40000000) >> 30 +} + +// PARL_IO.TX_CFG1: Parallel TX module configuration register1. +func (o *PARL_IO_Type) SetTX_CFG1_TX_IDLE_VALUE(value uint32) { + volatile.StoreUint32(&o.TX_CFG1.Reg, volatile.LoadUint32(&o.TX_CFG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PARL_IO_Type) GetTX_CFG1_TX_IDLE_VALUE() uint32 { + return (volatile.LoadUint32(&o.TX_CFG1.Reg) & 0xffff0000) >> 16 +} + +// PARL_IO.ST: Parallel IO module status register0. +func (o *PARL_IO_Type) SetST_TX_READY(value uint32) { + volatile.StoreUint32(&o.ST.Reg, volatile.LoadUint32(&o.ST.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetST_TX_READY() uint32 { + return (volatile.LoadUint32(&o.ST.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.INT_ENA: Parallel IO interrupt enable singal configuration register. +func (o *PARL_IO_Type) SetINT_ENA_TX_FIFO_REMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_ENA_TX_FIFO_REMPTY_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_ENA_RX_FIFO_WFULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_ENA_RX_FIFO_WFULL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_ENA_TX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_ENA_TX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// PARL_IO.INT_RAW: Parallel IO interrupt raw singal status register. +func (o *PARL_IO_Type) SetINT_RAW_TX_FIFO_REMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_RAW_TX_FIFO_REMPTY_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_RAW_RX_FIFO_WFULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_RAW_RX_FIFO_WFULL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_RAW_TX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_RAW_TX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// PARL_IO.INT_ST: Parallel IO interrupt singal status register. +func (o *PARL_IO_Type) SetINT_ST_TX_FIFO_REMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_ST_TX_FIFO_REMPTY_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_ST_RX_FIFO_WFULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_ST_RX_FIFO_WFULL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_ST_TX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_ST_TX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// PARL_IO.INT_CLR: Parallel IO interrupt clear singal configuration register. +func (o *PARL_IO_Type) SetINT_CLR_TX_FIFO_REMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_CLR_TX_FIFO_REMPTY_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_CLR_RX_FIFO_WFULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_CLR_RX_FIFO_WFULL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_CLR_TX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_CLR_TX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// PARL_IO.CLK: Parallel IO clk configuration register +func (o *PARL_IO_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} + +// PARL_IO.VERSION: Version register. +func (o *PARL_IO_Type) SetVERSION_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *PARL_IO_Type) GetVERSION_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// PAU Peripheral +type PAU_Type struct { + REGDMA_CONF volatile.Register32 // 0x0 + REGDMA_CLK_CONF volatile.Register32 // 0x4 + REGDMA_ETM_CTRL volatile.Register32 // 0x8 + REGDMA_LINK_0_ADDR volatile.Register32 // 0xC + REGDMA_LINK_1_ADDR volatile.Register32 // 0x10 + REGDMA_LINK_2_ADDR volatile.Register32 // 0x14 + REGDMA_LINK_3_ADDR volatile.Register32 // 0x18 + REGDMA_LINK_MAC_ADDR volatile.Register32 // 0x1C + REGDMA_CURRENT_LINK_ADDR volatile.Register32 // 0x20 + REGDMA_BACKUP_ADDR volatile.Register32 // 0x24 + REGDMA_MEM_ADDR volatile.Register32 // 0x28 + REGDMA_BKP_CONF volatile.Register32 // 0x2C + RETENTION_LINK_BASE volatile.Register32 // 0x30 + RETENTION_CFG volatile.Register32 // 0x34 + INT_ENA volatile.Register32 // 0x38 + INT_RAW volatile.Register32 // 0x3C + INT_CLR volatile.Register32 // 0x40 + INT_ST volatile.Register32 // 0x44 + _ [948]byte + DATE volatile.Register32 // 0x3FC +} + +// PAU.REGDMA_CONF: Peri backup control register +func (o *PAU_Type) SetREGDMA_CONF_FLOW_ERR(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x7)|value) +} +func (o *PAU_Type) GetREGDMA_CONF_FLOW_ERR() uint32 { + return volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x7 +} +func (o *PAU_Type) SetREGDMA_CONF_START(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PAU_Type) GetREGDMA_CONF_START() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x8) >> 3 +} +func (o *PAU_Type) SetREGDMA_CONF_TO_MEM(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x10)|value<<4) +} +func (o *PAU_Type) GetREGDMA_CONF_TO_MEM() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x10) >> 4 +} +func (o *PAU_Type) SetREGDMA_CONF_LINK_SEL(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x60)|value<<5) +} +func (o *PAU_Type) GetREGDMA_CONF_LINK_SEL() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x60) >> 5 +} +func (o *PAU_Type) SetREGDMA_CONF_START_MAC(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x80)|value<<7) +} +func (o *PAU_Type) GetREGDMA_CONF_START_MAC() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x80) >> 7 +} +func (o *PAU_Type) SetREGDMA_CONF_TO_MEM_MAC(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x100)|value<<8) +} +func (o *PAU_Type) GetREGDMA_CONF_TO_MEM_MAC() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x100) >> 8 +} +func (o *PAU_Type) SetREGDMA_CONF_SEL_MAC(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x200)|value<<9) +} +func (o *PAU_Type) GetREGDMA_CONF_SEL_MAC() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x200) >> 9 +} + +// PAU.REGDMA_CLK_CONF: Clock control register +func (o *PAU_Type) SetREGDMA_CLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGDMA_CLK_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetREGDMA_CLK_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.REGDMA_CLK_CONF.Reg) & 0x1 +} + +// PAU.REGDMA_ETM_CTRL: ETM start ctrl reg +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_0(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_0() uint32 { + return volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x1 +} +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_1(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_1() uint32 { + return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x2) >> 1 +} +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_2(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_2() uint32 { + return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x4) >> 2 +} +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_3(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_3() uint32 { + return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x8) >> 3 +} + +// PAU.REGDMA_LINK_0_ADDR: link_0_addr +func (o *PAU_Type) SetREGDMA_LINK_0_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_0_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_0_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_0_ADDR.Reg) +} + +// PAU.REGDMA_LINK_1_ADDR: Link_1_addr +func (o *PAU_Type) SetREGDMA_LINK_1_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_1_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_1_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_1_ADDR.Reg) +} + +// PAU.REGDMA_LINK_2_ADDR: Link_2_addr +func (o *PAU_Type) SetREGDMA_LINK_2_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_2_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_2_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_2_ADDR.Reg) +} + +// PAU.REGDMA_LINK_3_ADDR: Link_3_addr +func (o *PAU_Type) SetREGDMA_LINK_3_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_3_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_3_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_3_ADDR.Reg) +} + +// PAU.REGDMA_LINK_MAC_ADDR: Link_mac_addr +func (o *PAU_Type) SetREGDMA_LINK_MAC_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_MAC_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_MAC_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_MAC_ADDR.Reg) +} + +// PAU.REGDMA_CURRENT_LINK_ADDR: current link addr +func (o *PAU_Type) SetREGDMA_CURRENT_LINK_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_CURRENT_LINK_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_CURRENT_LINK_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_CURRENT_LINK_ADDR.Reg) +} + +// PAU.REGDMA_BACKUP_ADDR: Backup addr +func (o *PAU_Type) SetREGDMA_BACKUP_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_BACKUP_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_BACKUP_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_BACKUP_ADDR.Reg) +} + +// PAU.REGDMA_MEM_ADDR: mem addr +func (o *PAU_Type) SetREGDMA_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_MEM_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_MEM_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_MEM_ADDR.Reg) +} + +// PAU.REGDMA_BKP_CONF: backup config +func (o *PAU_Type) SetREGDMA_BKP_CONF_READ_INTERVAL(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x7f)|value) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_READ_INTERVAL() uint32 { + return volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x7f +} +func (o *PAU_Type) SetREGDMA_BKP_CONF_LINK_TOUT_THRES(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x1ff80)|value<<7) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_LINK_TOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x1ff80) >> 7 +} +func (o *PAU_Type) SetREGDMA_BKP_CONF_BURST_LIMIT(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x3e0000)|value<<17) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_BURST_LIMIT() uint32 { + return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x3e0000) >> 17 +} +func (o *PAU_Type) SetREGDMA_BKP_CONF_BACKUP_TOUT_THRES(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0xffc00000)|value<<22) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_BACKUP_TOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0xffc00000) >> 22 +} + +// PAU.RETENTION_LINK_BASE: retention dma link base +func (o *PAU_Type) SetRETENTION_LINK_BASE_LINK_BASE_ADDR(value uint32) { + volatile.StoreUint32(&o.RETENTION_LINK_BASE.Reg, volatile.LoadUint32(&o.RETENTION_LINK_BASE.Reg)&^(0x7ffffff)|value) +} +func (o *PAU_Type) GetRETENTION_LINK_BASE_LINK_BASE_ADDR() uint32 { + return volatile.LoadUint32(&o.RETENTION_LINK_BASE.Reg) & 0x7ffffff +} + +// PAU.RETENTION_CFG: retention_cfg +func (o *PAU_Type) SetRETENTION_CFG(value uint32) { + volatile.StoreUint32(&o.RETENTION_CFG.Reg, value) +} +func (o *PAU_Type) GetRETENTION_CFG() uint32 { + return volatile.LoadUint32(&o.RETENTION_CFG.Reg) +} + +// PAU.INT_ENA: Read only register for error and done +func (o *PAU_Type) SetINT_ENA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_ENA_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_ENA_ERROR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_ENA_ERROR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// PAU.INT_RAW: Read only register for error and done +func (o *PAU_Type) SetINT_RAW_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_RAW_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_RAW_ERROR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_RAW_ERROR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// PAU.INT_CLR: Read only register for error and done +func (o *PAU_Type) SetINT_CLR_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_CLR_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_CLR_ERROR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_CLR_ERROR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// PAU.INT_ST: Read only register for error and done +func (o *PAU_Type) SetINT_ST_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_ST_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_ST_ERROR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_ST_ERROR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// PAU.DATE: Date register. +func (o *PAU_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *PAU_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Pulse Count Controller +type PCNT_Type struct { + U0_CONF0 volatile.Register32 // 0x0 + U0_CONF1 volatile.Register32 // 0x4 + U0_CONF2 volatile.Register32 // 0x8 + U1_CONF0 volatile.Register32 // 0xC + U1_CONF1 volatile.Register32 // 0x10 + U1_CONF2 volatile.Register32 // 0x14 + U2_CONF0 volatile.Register32 // 0x18 + U2_CONF1 volatile.Register32 // 0x1C + U2_CONF2 volatile.Register32 // 0x20 + U3_CONF0 volatile.Register32 // 0x24 + U3_CONF1 volatile.Register32 // 0x28 + U3_CONF2 volatile.Register32 // 0x2C + U0_CNT volatile.Register32 // 0x30 + U1_CNT volatile.Register32 // 0x34 + U2_CNT volatile.Register32 // 0x38 + U3_CNT volatile.Register32 // 0x3C + INT_RAW volatile.Register32 // 0x40 + INT_ST volatile.Register32 // 0x44 + INT_ENA volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + U0_STATUS volatile.Register32 // 0x50 + U1_STATUS volatile.Register32 // 0x54 + U2_STATUS volatile.Register32 // 0x58 + U3_STATUS volatile.Register32 // 0x5C + CTRL volatile.Register32 // 0x60 + _ [152]byte + DATE volatile.Register32 // 0xFC +} + +// PCNT.U0_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU0_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU0_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU0_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU0_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU0_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU0_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU0_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU0_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U0_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU0_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU1_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU1_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU1_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU1_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU1_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU1_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU1_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU1_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U1_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU1_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU2_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU2_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU2_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU2_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU2_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU2_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU2_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU2_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U2_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU2_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU3_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU3_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU3_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU3_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU3_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU3_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU3_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU3_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U3_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU3_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU0_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U0_CNT.Reg, volatile.LoadUint32(&o.U0_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U0_CNT.Reg) & 0xffff +} + +// PCNT.U1_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU1_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U1_CNT.Reg, volatile.LoadUint32(&o.U1_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U1_CNT.Reg) & 0xffff +} + +// PCNT.U2_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU2_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U2_CNT.Reg, volatile.LoadUint32(&o.U2_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U2_CNT.Reg) & 0xffff +} + +// PCNT.U3_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU3_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U3_CNT.Reg, volatile.LoadUint32(&o.U3_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U3_CNT.Reg) & 0xffff +} + +// PCNT.INT_RAW: Interrupt raw status register +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ST: Interrupt status register +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ENA: Interrupt enable register +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// PCNT.INT_CLR: Interrupt clear register +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// PCNT.U0_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU0_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU0_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU0_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU0_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU0_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU0_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU0_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU0_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU0_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU0_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U1_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU1_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU1_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU1_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU1_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU1_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU1_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU1_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU1_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU1_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU1_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U2_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU2_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU2_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU2_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU2_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU2_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU2_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU2_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU2_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU2_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU2_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U3_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU3_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU3_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU3_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU3_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU3_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU3_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU3_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU3_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU3_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU3_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.CTRL: Control register for all counters +func (o *PCNT_Type) SetCTRL_CNT_RST_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U0() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U0() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *PCNT_Type) SetCTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *PCNT_Type) GetCTRL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} + +// PCNT.DATE: PCNT version control register +func (o *PCNT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *PCNT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// PCR Peripheral +type PCR_Type struct { + UART0_CONF volatile.Register32 // 0x0 + UART0_SCLK_CONF volatile.Register32 // 0x4 + UART0_PD_CTRL volatile.Register32 // 0x8 + UART1_CONF volatile.Register32 // 0xC + UART1_SCLK_CONF volatile.Register32 // 0x10 + UART1_PD_CTRL volatile.Register32 // 0x14 + MSPI_CONF volatile.Register32 // 0x18 + MSPI_CLK_CONF volatile.Register32 // 0x1C + I2C0_CONF volatile.Register32 // 0x20 + I2C_SCLK_CONF volatile.Register32 // 0x24 + UHCI_CONF volatile.Register32 // 0x28 + RMT_CONF volatile.Register32 // 0x2C + RMT_SCLK_CONF volatile.Register32 // 0x30 + LEDC_CONF volatile.Register32 // 0x34 + LEDC_SCLK_CONF volatile.Register32 // 0x38 + TIMERGROUP0_CONF volatile.Register32 // 0x3C + TIMERGROUP0_TIMER_CLK_CONF volatile.Register32 // 0x40 + TIMERGROUP0_WDT_CLK_CONF volatile.Register32 // 0x44 + TIMERGROUP1_CONF volatile.Register32 // 0x48 + TIMERGROUP1_TIMER_CLK_CONF volatile.Register32 // 0x4C + TIMERGROUP1_WDT_CLK_CONF volatile.Register32 // 0x50 + SYSTIMER_CONF volatile.Register32 // 0x54 + SYSTIMER_FUNC_CLK_CONF volatile.Register32 // 0x58 + TWAI0_CONF volatile.Register32 // 0x5C + TWAI0_FUNC_CLK_CONF volatile.Register32 // 0x60 + TWAI1_CONF volatile.Register32 // 0x64 + TWAI1_FUNC_CLK_CONF volatile.Register32 // 0x68 + I2S_CONF volatile.Register32 // 0x6C + I2S_TX_CLKM_CONF volatile.Register32 // 0x70 + I2S_TX_CLKM_DIV_CONF volatile.Register32 // 0x74 + I2S_RX_CLKM_CONF volatile.Register32 // 0x78 + I2S_RX_CLKM_DIV_CONF volatile.Register32 // 0x7C + SARADC_CONF volatile.Register32 // 0x80 + SARADC_CLKM_CONF volatile.Register32 // 0x84 + TSENS_CLK_CONF volatile.Register32 // 0x88 + USB_DEVICE_CONF volatile.Register32 // 0x8C + INTMTX_CONF volatile.Register32 // 0x90 + PCNT_CONF volatile.Register32 // 0x94 + ETM_CONF volatile.Register32 // 0x98 + PWM_CONF volatile.Register32 // 0x9C + PWM_CLK_CONF volatile.Register32 // 0xA0 + PARL_IO_CONF volatile.Register32 // 0xA4 + PARL_CLK_RX_CONF volatile.Register32 // 0xA8 + PARL_CLK_TX_CONF volatile.Register32 // 0xAC + SDIO_SLAVE_CONF volatile.Register32 // 0xB0 + PVT_MONITOR_CONF volatile.Register32 // 0xB4 + PVT_MONITOR_FUNC_CLK_CONF volatile.Register32 // 0xB8 + GDMA_CONF volatile.Register32 // 0xBC + SPI2_CONF volatile.Register32 // 0xC0 + SPI2_CLKM_CONF volatile.Register32 // 0xC4 + AES_CONF volatile.Register32 // 0xC8 + SHA_CONF volatile.Register32 // 0xCC + RSA_CONF volatile.Register32 // 0xD0 + RSA_PD_CTRL volatile.Register32 // 0xD4 + ECC_CONF volatile.Register32 // 0xD8 + ECC_PD_CTRL volatile.Register32 // 0xDC + DS_CONF volatile.Register32 // 0xE0 + HMAC_CONF volatile.Register32 // 0xE4 + IOMUX_CONF volatile.Register32 // 0xE8 + IOMUX_CLK_CONF volatile.Register32 // 0xEC + MEM_MONITOR_CONF volatile.Register32 // 0xF0 + REGDMA_CONF volatile.Register32 // 0xF4 + RETENTION_CONF volatile.Register32 // 0xF8 + TRACE_CONF volatile.Register32 // 0xFC + ASSIST_CONF volatile.Register32 // 0x100 + CACHE_CONF volatile.Register32 // 0x104 + MODEM_APB_CONF volatile.Register32 // 0x108 + TIMEOUT_CONF volatile.Register32 // 0x10C + SYSCLK_CONF volatile.Register32 // 0x110 + CPU_WAITI_CONF volatile.Register32 // 0x114 + CPU_FREQ_CONF volatile.Register32 // 0x118 + AHB_FREQ_CONF volatile.Register32 // 0x11C + APB_FREQ_CONF volatile.Register32 // 0x120 + SYSCLK_FREQ_QUERY_0 volatile.Register32 // 0x124 + PLL_DIV_CLK_EN volatile.Register32 // 0x128 + CTRL_CLK_OUT_EN volatile.Register32 // 0x12C + CTRL_TICK_CONF volatile.Register32 // 0x130 + CTRL_32K_CONF volatile.Register32 // 0x134 + SRAM_POWER_CONF volatile.Register32 // 0x138 + _ [3764]byte + RESET_EVENT_BYPASS volatile.Register32 // 0xFF0 + FPGA_DEBUG volatile.Register32 // 0xFF4 + CLOCK_GATE volatile.Register32 // 0xFF8 + DATE volatile.Register32 // 0xFFC +} + +// PCR.UART0_CONF: UART0 configuration register +func (o *PCR_Type) SetUART0_CONF_UART0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.UART0_CONF.Reg, volatile.LoadUint32(&o.UART0_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetUART0_CONF_UART0_CLK_EN() uint32 { + return volatile.LoadUint32(&o.UART0_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetUART0_CONF_UART0_RST_EN(value uint32) { + volatile.StoreUint32(&o.UART0_CONF.Reg, volatile.LoadUint32(&o.UART0_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUART0_CONF_UART0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.UART0_CONF.Reg) & 0x2) >> 1 +} + +// PCR.UART0_SCLK_CONF: UART0_SCLK configuration register +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_DIV_A() uint32 { + return volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.UART0_PD_CTRL: UART0 power control register +func (o *PCR_Type) SetUART0_PD_CTRL_UART0_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.UART0_PD_CTRL.Reg, volatile.LoadUint32(&o.UART0_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUART0_PD_CTRL_UART0_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.UART0_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetUART0_PD_CTRL_UART0_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.UART0_PD_CTRL.Reg, volatile.LoadUint32(&o.UART0_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetUART0_PD_CTRL_UART0_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.UART0_PD_CTRL.Reg) & 0x4) >> 2 +} + +// PCR.UART1_CONF: UART1 configuration register +func (o *PCR_Type) SetUART1_CONF_UART1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.UART1_CONF.Reg, volatile.LoadUint32(&o.UART1_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetUART1_CONF_UART1_CLK_EN() uint32 { + return volatile.LoadUint32(&o.UART1_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetUART1_CONF_UART1_RST_EN(value uint32) { + volatile.StoreUint32(&o.UART1_CONF.Reg, volatile.LoadUint32(&o.UART1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUART1_CONF_UART1_RST_EN() uint32 { + return (volatile.LoadUint32(&o.UART1_CONF.Reg) & 0x2) >> 1 +} + +// PCR.UART1_SCLK_CONF: UART1_SCLK configuration register +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_DIV_A() uint32 { + return volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.UART1_PD_CTRL: UART1 power control register +func (o *PCR_Type) SetUART1_PD_CTRL_UART1_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.UART1_PD_CTRL.Reg, volatile.LoadUint32(&o.UART1_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUART1_PD_CTRL_UART1_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.UART1_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetUART1_PD_CTRL_UART1_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.UART1_PD_CTRL.Reg, volatile.LoadUint32(&o.UART1_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetUART1_PD_CTRL_UART1_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.UART1_PD_CTRL.Reg) & 0x4) >> 2 +} + +// PCR.MSPI_CONF: MSPI configuration register +func (o *PCR_Type) SetMSPI_CONF_MSPI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MSPI_CONF.Reg, volatile.LoadUint32(&o.MSPI_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetMSPI_CONF_MSPI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MSPI_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetMSPI_CONF_MSPI_RST_EN(value uint32) { + volatile.StoreUint32(&o.MSPI_CONF.Reg, volatile.LoadUint32(&o.MSPI_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetMSPI_CONF_MSPI_RST_EN() uint32 { + return (volatile.LoadUint32(&o.MSPI_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetMSPI_CONF_MSPI_PLL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MSPI_CONF.Reg, volatile.LoadUint32(&o.MSPI_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetMSPI_CONF_MSPI_PLL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MSPI_CONF.Reg) & 0x4) >> 2 +} + +// PCR.MSPI_CLK_CONF: MSPI_CLK configuration register +func (o *PCR_Type) SetMSPI_CLK_CONF_MSPI_FAST_LS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.MSPI_CLK_CONF.Reg, volatile.LoadUint32(&o.MSPI_CLK_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetMSPI_CLK_CONF_MSPI_FAST_LS_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.MSPI_CLK_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetMSPI_CLK_CONF_MSPI_FAST_HS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.MSPI_CLK_CONF.Reg, volatile.LoadUint32(&o.MSPI_CLK_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetMSPI_CLK_CONF_MSPI_FAST_HS_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.MSPI_CLK_CONF.Reg) & 0xff00) >> 8 +} + +// PCR.I2C0_CONF: I2C configuration register +func (o *PCR_Type) SetI2C0_CONF_I2C0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetI2C0_CONF_I2C0_CLK_EN() uint32 { + return volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetI2C0_CONF_I2C0_RST_EN(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetI2C0_CONF_I2C0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0x2) >> 1 +} + +// PCR.I2C_SCLK_CONF: I2C_SCLK configuration register +func (o *PCR_Type) SetI2C_SCLK_CONF_I2C_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.I2C_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetI2C_SCLK_CONF_I2C_SCLK_DIV_A() uint32 { + return volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetI2C_SCLK_CONF_I2C_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.I2C_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetI2C_SCLK_CONF_I2C_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetI2C_SCLK_CONF_I2C_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2C_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetI2C_SCLK_CONF_I2C_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetI2C_SCLK_CONF_I2C_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.I2C_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetI2C_SCLK_CONF_I2C_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetI2C_SCLK_CONF_I2C_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.I2C_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetI2C_SCLK_CONF_I2C_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.I2C_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.UHCI_CONF: UHCI configuration register +func (o *PCR_Type) SetUHCI_CONF_UHCI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.UHCI_CONF.Reg, volatile.LoadUint32(&o.UHCI_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetUHCI_CONF_UHCI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.UHCI_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetUHCI_CONF_UHCI_RST_EN(value uint32) { + volatile.StoreUint32(&o.UHCI_CONF.Reg, volatile.LoadUint32(&o.UHCI_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUHCI_CONF_UHCI_RST_EN() uint32 { + return (volatile.LoadUint32(&o.UHCI_CONF.Reg) & 0x2) >> 1 +} + +// PCR.RMT_CONF: RMT configuration register +func (o *PCR_Type) SetRMT_CONF_RMT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.RMT_CONF.Reg, volatile.LoadUint32(&o.RMT_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetRMT_CONF_RMT_CLK_EN() uint32 { + return volatile.LoadUint32(&o.RMT_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetRMT_CONF_RMT_RST_EN(value uint32) { + volatile.StoreUint32(&o.RMT_CONF.Reg, volatile.LoadUint32(&o.RMT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetRMT_CONF_RMT_RST_EN() uint32 { + return (volatile.LoadUint32(&o.RMT_CONF.Reg) & 0x2) >> 1 +} + +// PCR.RMT_SCLK_CONF: RMT_SCLK configuration register +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_DIV_A() uint32 { + return volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.LEDC_CONF: LEDC configuration register +func (o *PCR_Type) SetLEDC_CONF_LEDC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LEDC_CONF.Reg, volatile.LoadUint32(&o.LEDC_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetLEDC_CONF_LEDC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.LEDC_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetLEDC_CONF_LEDC_RST_EN(value uint32) { + volatile.StoreUint32(&o.LEDC_CONF.Reg, volatile.LoadUint32(&o.LEDC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetLEDC_CONF_LEDC_RST_EN() uint32 { + return (volatile.LoadUint32(&o.LEDC_CONF.Reg) & 0x2) >> 1 +} + +// PCR.LEDC_SCLK_CONF: LEDC_SCLK configuration register +func (o *PCR_Type) SetLEDC_SCLK_CONF_LEDC_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.LEDC_SCLK_CONF.Reg, volatile.LoadUint32(&o.LEDC_SCLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetLEDC_SCLK_CONF_LEDC_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LEDC_SCLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetLEDC_SCLK_CONF_LEDC_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.LEDC_SCLK_CONF.Reg, volatile.LoadUint32(&o.LEDC_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetLEDC_SCLK_CONF_LEDC_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.LEDC_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TIMERGROUP0_CONF: TIMERGROUP0 configuration register +func (o *PCR_Type) SetTIMERGROUP0_CONF_TG0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetTIMERGROUP0_CONF_TG0_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetTIMERGROUP0_CONF_TG0_RST_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTIMERGROUP0_CONF_TG0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg) & 0x2) >> 1 +} + +// PCR.TIMERGROUP0_TIMER_CLK_CONF: TIMERGROUP0_TIMER_CLK configuration register +func (o *PCR_Type) SetTIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetTIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetTIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TIMERGROUP0_WDT_CLK_CONF: TIMERGROUP0_WDT_CLK configuration register +func (o *PCR_Type) SetTIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetTIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetTIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TIMERGROUP1_CONF: TIMERGROUP1 configuration register +func (o *PCR_Type) SetTIMERGROUP1_CONF_TG1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetTIMERGROUP1_CONF_TG1_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetTIMERGROUP1_CONF_TG1_RST_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTIMERGROUP1_CONF_TG1_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg) & 0x2) >> 1 +} + +// PCR.TIMERGROUP1_TIMER_CLK_CONF: TIMERGROUP1_TIMER_CLK configuration register +func (o *PCR_Type) SetTIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetTIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetTIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TIMERGROUP1_WDT_CLK_CONF: TIMERGROUP1_WDT_CLK configuration register +func (o *PCR_Type) SetTIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetTIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetTIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.SYSTIMER_CONF: SYSTIMER configuration register +func (o *PCR_Type) SetSYSTIMER_CONF_SYSTIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_CONF.Reg, volatile.LoadUint32(&o.SYSTIMER_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSYSTIMER_CONF_SYSTIMER_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSYSTIMER_CONF_SYSTIMER_RST_EN(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_CONF.Reg, volatile.LoadUint32(&o.SYSTIMER_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetSYSTIMER_CONF_SYSTIMER_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SYSTIMER_CONF.Reg) & 0x2) >> 1 +} + +// PCR.SYSTIMER_FUNC_CLK_CONF: SYSTIMER_FUNC_CLK configuration register +func (o *PCR_Type) SetSYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetSYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetSYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetSYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TWAI0_CONF: TWAI0 configuration register +func (o *PCR_Type) SetTWAI0_CONF_TWAI0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TWAI0_CONF.Reg, volatile.LoadUint32(&o.TWAI0_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetTWAI0_CONF_TWAI0_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TWAI0_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetTWAI0_CONF_TWAI0_RST_EN(value uint32) { + volatile.StoreUint32(&o.TWAI0_CONF.Reg, volatile.LoadUint32(&o.TWAI0_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTWAI0_CONF_TWAI0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TWAI0_CONF.Reg) & 0x2) >> 1 +} + +// PCR.TWAI0_FUNC_CLK_CONF: TWAI0_FUNC_CLK configuration register +func (o *PCR_Type) SetTWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TWAI0_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.TWAI0_FUNC_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetTWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TWAI0_FUNC_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetTWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TWAI0_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.TWAI0_FUNC_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TWAI0_FUNC_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TWAI1_CONF: TWAI1 configuration register +func (o *PCR_Type) SetTWAI1_CONF_TWAI1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TWAI1_CONF.Reg, volatile.LoadUint32(&o.TWAI1_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetTWAI1_CONF_TWAI1_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TWAI1_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetTWAI1_CONF_TWAI1_RST_EN(value uint32) { + volatile.StoreUint32(&o.TWAI1_CONF.Reg, volatile.LoadUint32(&o.TWAI1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTWAI1_CONF_TWAI1_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TWAI1_CONF.Reg) & 0x2) >> 1 +} + +// PCR.TWAI1_FUNC_CLK_CONF: TWAI1_FUNC_CLK configuration register +func (o *PCR_Type) SetTWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TWAI1_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.TWAI1_FUNC_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetTWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TWAI1_FUNC_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetTWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TWAI1_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.TWAI1_FUNC_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TWAI1_FUNC_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.I2S_CONF: I2S configuration register +func (o *PCR_Type) SetI2S_CONF_I2S_CLK_EN(value uint32) { + volatile.StoreUint32(&o.I2S_CONF.Reg, volatile.LoadUint32(&o.I2S_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetI2S_CONF_I2S_CLK_EN() uint32 { + return volatile.LoadUint32(&o.I2S_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetI2S_CONF_I2S_RST_EN(value uint32) { + volatile.StoreUint32(&o.I2S_CONF.Reg, volatile.LoadUint32(&o.I2S_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetI2S_CONF_I2S_RST_EN() uint32 { + return (volatile.LoadUint32(&o.I2S_CONF.Reg) & 0x2) >> 1 +} + +// PCR.I2S_TX_CLKM_CONF: I2S_TX_CLKM configuration register +func (o *PCR_Type) SetI2S_TX_CLKM_CONF_I2S_TX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetI2S_TX_CLKM_CONF_I2S_TX_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetI2S_TX_CLKM_CONF_I2S_TX_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetI2S_TX_CLKM_CONF_I2S_TX_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetI2S_TX_CLKM_CONF_I2S_TX_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetI2S_TX_CLKM_CONF_I2S_TX_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.I2S_TX_CLKM_DIV_CONF: I2S_TX_CLKM_DIV configuration register +func (o *PCR_Type) SetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *PCR_Type) GetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *PCR_Type) SetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *PCR_Type) GetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *PCR_Type) SetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *PCR_Type) GetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *PCR_Type) SetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *PCR_Type) GetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// PCR.I2S_RX_CLKM_CONF: I2S_RX_CLKM configuration register +func (o *PCR_Type) SetI2S_RX_CLKM_CONF_I2S_RX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetI2S_RX_CLKM_CONF_I2S_RX_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetI2S_RX_CLKM_CONF_I2S_RX_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetI2S_RX_CLKM_CONF_I2S_RX_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetI2S_RX_CLKM_CONF_I2S_RX_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetI2S_RX_CLKM_CONF_I2S_RX_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg) & 0x400000) >> 22 +} +func (o *PCR_Type) SetI2S_RX_CLKM_CONF_I2S_MCLK_SEL(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *PCR_Type) GetI2S_RX_CLKM_CONF_I2S_MCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg) & 0x800000) >> 23 +} + +// PCR.I2S_RX_CLKM_DIV_CONF: I2S_RX_CLKM_DIV configuration register +func (o *PCR_Type) SetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *PCR_Type) GetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *PCR_Type) SetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *PCR_Type) GetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *PCR_Type) SetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *PCR_Type) GetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *PCR_Type) SetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *PCR_Type) GetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// PCR.SARADC_CONF: SARADC configuration register +func (o *PCR_Type) SetSARADC_CONF_SARADC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CONF.Reg, volatile.LoadUint32(&o.SARADC_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSARADC_CONF_SARADC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SARADC_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSARADC_CONF_SARADC_RST_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CONF.Reg, volatile.LoadUint32(&o.SARADC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetSARADC_CONF_SARADC_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SARADC_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetSARADC_CONF_SARADC_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CONF.Reg, volatile.LoadUint32(&o.SARADC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetSARADC_CONF_SARADC_REG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SARADC_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetSARADC_CONF_SARADC_REG_RST_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CONF.Reg, volatile.LoadUint32(&o.SARADC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetSARADC_CONF_SARADC_REG_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SARADC_CONF.Reg) & 0x8) >> 3 +} + +// PCR.SARADC_CLKM_CONF: SARADC_CLKM configuration register +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_DIV_A() uint32 { + return volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TSENS_CLK_CONF: TSENS_CLK configuration register +func (o *PCR_Type) SetTSENS_CLK_CONF_TSENS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TSENS_CLK_CONF.Reg, volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetTSENS_CLK_CONF_TSENS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetTSENS_CLK_CONF_TSENS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TSENS_CLK_CONF.Reg, volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTSENS_CLK_CONF_TSENS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *PCR_Type) SetTSENS_CLK_CONF_TSENS_RST_EN(value uint32) { + volatile.StoreUint32(&o.TSENS_CLK_CONF.Reg, volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *PCR_Type) GetTSENS_CLK_CONF_TSENS_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg) & 0x800000) >> 23 +} + +// PCR.USB_DEVICE_CONF: USB_DEVICE configuration register +func (o *PCR_Type) SetUSB_DEVICE_CONF_USB_DEVICE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.USB_DEVICE_CONF.Reg, volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetUSB_DEVICE_CONF_USB_DEVICE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetUSB_DEVICE_CONF_USB_DEVICE_RST_EN(value uint32) { + volatile.StoreUint32(&o.USB_DEVICE_CONF.Reg, volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUSB_DEVICE_CONF_USB_DEVICE_RST_EN() uint32 { + return (volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg) & 0x2) >> 1 +} + +// PCR.INTMTX_CONF: INTMTX configuration register +func (o *PCR_Type) SetINTMTX_CONF_INTMTX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.INTMTX_CONF.Reg, volatile.LoadUint32(&o.INTMTX_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetINTMTX_CONF_INTMTX_CLK_EN() uint32 { + return volatile.LoadUint32(&o.INTMTX_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetINTMTX_CONF_INTMTX_RST_EN(value uint32) { + volatile.StoreUint32(&o.INTMTX_CONF.Reg, volatile.LoadUint32(&o.INTMTX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetINTMTX_CONF_INTMTX_RST_EN() uint32 { + return (volatile.LoadUint32(&o.INTMTX_CONF.Reg) & 0x2) >> 1 +} + +// PCR.PCNT_CONF: PCNT configuration register +func (o *PCR_Type) SetPCNT_CONF_PCNT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PCNT_CONF.Reg, volatile.LoadUint32(&o.PCNT_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPCNT_CONF_PCNT_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PCNT_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetPCNT_CONF_PCNT_RST_EN(value uint32) { + volatile.StoreUint32(&o.PCNT_CONF.Reg, volatile.LoadUint32(&o.PCNT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPCNT_CONF_PCNT_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PCNT_CONF.Reg) & 0x2) >> 1 +} + +// PCR.ETM_CONF: ETM configuration register +func (o *PCR_Type) SetETM_CONF_ETM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetETM_CONF_ETM_CLK_EN() uint32 { + return volatile.LoadUint32(&o.ETM_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetETM_CONF_ETM_RST_EN(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetETM_CONF_ETM_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_CONF.Reg) & 0x2) >> 1 +} + +// PCR.PWM_CONF: PWM configuration register +func (o *PCR_Type) SetPWM_CONF_PWM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PWM_CONF.Reg, volatile.LoadUint32(&o.PWM_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPWM_CONF_PWM_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PWM_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetPWM_CONF_PWM_RST_EN(value uint32) { + volatile.StoreUint32(&o.PWM_CONF.Reg, volatile.LoadUint32(&o.PWM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPWM_CONF_PWM_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PWM_CONF.Reg) & 0x2) >> 1 +} + +// PCR.PWM_CLK_CONF: PWM_CLK configuration register +func (o *PCR_Type) SetPWM_CLK_CONF_PWM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PWM_CLK_CONF.Reg, volatile.LoadUint32(&o.PWM_CLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetPWM_CLK_CONF_PWM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PWM_CLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetPWM_CLK_CONF_PWM_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.PWM_CLK_CONF.Reg, volatile.LoadUint32(&o.PWM_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetPWM_CLK_CONF_PWM_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.PWM_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetPWM_CLK_CONF_PWM_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.PWM_CLK_CONF.Reg, volatile.LoadUint32(&o.PWM_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetPWM_CLK_CONF_PWM_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.PWM_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.PARL_IO_CONF: PARL_IO configuration register +func (o *PCR_Type) SetPARL_IO_CONF_PARL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PARL_IO_CONF.Reg, volatile.LoadUint32(&o.PARL_IO_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPARL_IO_CONF_PARL_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PARL_IO_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetPARL_IO_CONF_PARL_RST_EN(value uint32) { + volatile.StoreUint32(&o.PARL_IO_CONF.Reg, volatile.LoadUint32(&o.PARL_IO_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPARL_IO_CONF_PARL_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_IO_CONF.Reg) & 0x2) >> 1 +} + +// PCR.PARL_CLK_RX_CONF: PARL_CLK_RX configuration register +func (o *PCR_Type) SetPARL_CLK_RX_CONF_PARL_CLK_RX_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_RX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg)&^(0xffff)|value) +} +func (o *PCR_Type) GetPARL_CLK_RX_CONF_PARL_CLK_RX_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg) & 0xffff +} +func (o *PCR_Type) SetPARL_CLK_RX_CONF_PARL_CLK_RX_SEL(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_RX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg)&^(0x30000)|value<<16) +} +func (o *PCR_Type) GetPARL_CLK_RX_CONF_PARL_CLK_RX_SEL() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg) & 0x30000) >> 16 +} +func (o *PCR_Type) SetPARL_CLK_RX_CONF_PARL_CLK_RX_EN(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_RX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *PCR_Type) GetPARL_CLK_RX_CONF_PARL_CLK_RX_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg) & 0x40000) >> 18 +} +func (o *PCR_Type) SetPARL_CLK_RX_CONF_PARL_RX_RST_EN(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_RX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *PCR_Type) GetPARL_CLK_RX_CONF_PARL_RX_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg) & 0x80000) >> 19 +} + +// PCR.PARL_CLK_TX_CONF: PARL_CLK_TX configuration register +func (o *PCR_Type) SetPARL_CLK_TX_CONF_PARL_CLK_TX_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_TX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg)&^(0xffff)|value) +} +func (o *PCR_Type) GetPARL_CLK_TX_CONF_PARL_CLK_TX_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg) & 0xffff +} +func (o *PCR_Type) SetPARL_CLK_TX_CONF_PARL_CLK_TX_SEL(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_TX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg)&^(0x30000)|value<<16) +} +func (o *PCR_Type) GetPARL_CLK_TX_CONF_PARL_CLK_TX_SEL() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg) & 0x30000) >> 16 +} +func (o *PCR_Type) SetPARL_CLK_TX_CONF_PARL_CLK_TX_EN(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_TX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *PCR_Type) GetPARL_CLK_TX_CONF_PARL_CLK_TX_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg) & 0x40000) >> 18 +} +func (o *PCR_Type) SetPARL_CLK_TX_CONF_PARL_TX_RST_EN(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_TX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *PCR_Type) GetPARL_CLK_TX_CONF_PARL_TX_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg) & 0x80000) >> 19 +} + +// PCR.SDIO_SLAVE_CONF: SDIO_SLAVE configuration register +func (o *PCR_Type) SetSDIO_SLAVE_CONF_SDIO_SLAVE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSDIO_SLAVE_CONF_SDIO_SLAVE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SDIO_SLAVE_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSDIO_SLAVE_CONF_SDIO_SLAVE_RST_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_SLAVE_CONF.Reg, volatile.LoadUint32(&o.SDIO_SLAVE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetSDIO_SLAVE_CONF_SDIO_SLAVE_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SDIO_SLAVE_CONF.Reg) & 0x2) >> 1 +} + +// PCR.PVT_MONITOR_CONF: PVT_MONITOR configuration register +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_RST_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x10)|value<<4) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x10) >> 4 +} + +// PCR.PVT_MONITOR_FUNC_CLK_CONF: PVT_MONITOR function clock configuration register +func (o *PCR_Type) SetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg)&^(0xf)|value) +} +func (o *PCR_Type) GetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg) & 0xf +} +func (o *PCR_Type) SetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.GDMA_CONF: GDMA configuration register +func (o *PCR_Type) SetGDMA_CONF_GDMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.GDMA_CONF.Reg, volatile.LoadUint32(&o.GDMA_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetGDMA_CONF_GDMA_CLK_EN() uint32 { + return volatile.LoadUint32(&o.GDMA_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetGDMA_CONF_GDMA_RST_EN(value uint32) { + volatile.StoreUint32(&o.GDMA_CONF.Reg, volatile.LoadUint32(&o.GDMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetGDMA_CONF_GDMA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.GDMA_CONF.Reg) & 0x2) >> 1 +} + +// PCR.SPI2_CONF: SPI2 configuration register +func (o *PCR_Type) SetSPI2_CONF_SPI2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI2_CONF.Reg, volatile.LoadUint32(&o.SPI2_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSPI2_CONF_SPI2_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI2_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSPI2_CONF_SPI2_RST_EN(value uint32) { + volatile.StoreUint32(&o.SPI2_CONF.Reg, volatile.LoadUint32(&o.SPI2_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetSPI2_CONF_SPI2_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SPI2_CONF.Reg) & 0x2) >> 1 +} + +// PCR.SPI2_CLKM_CONF: SPI2_CLKM configuration register +func (o *PCR_Type) SetSPI2_CLKM_CONF_SPI2_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.SPI2_CLKM_CONF.Reg, volatile.LoadUint32(&o.SPI2_CLKM_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetSPI2_CLKM_CONF_SPI2_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.SPI2_CLKM_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetSPI2_CLKM_CONF_SPI2_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.SPI2_CLKM_CONF.Reg, volatile.LoadUint32(&o.SPI2_CLKM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetSPI2_CLKM_CONF_SPI2_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.SPI2_CLKM_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.AES_CONF: AES configuration register +func (o *PCR_Type) SetAES_CONF_AES_CLK_EN(value uint32) { + volatile.StoreUint32(&o.AES_CONF.Reg, volatile.LoadUint32(&o.AES_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetAES_CONF_AES_CLK_EN() uint32 { + return volatile.LoadUint32(&o.AES_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetAES_CONF_AES_RST_EN(value uint32) { + volatile.StoreUint32(&o.AES_CONF.Reg, volatile.LoadUint32(&o.AES_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetAES_CONF_AES_RST_EN() uint32 { + return (volatile.LoadUint32(&o.AES_CONF.Reg) & 0x2) >> 1 +} + +// PCR.SHA_CONF: SHA configuration register +func (o *PCR_Type) SetSHA_CONF_SHA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SHA_CONF.Reg, volatile.LoadUint32(&o.SHA_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSHA_CONF_SHA_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SHA_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSHA_CONF_SHA_RST_EN(value uint32) { + volatile.StoreUint32(&o.SHA_CONF.Reg, volatile.LoadUint32(&o.SHA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetSHA_CONF_SHA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SHA_CONF.Reg) & 0x2) >> 1 +} + +// PCR.RSA_CONF: RSA configuration register +func (o *PCR_Type) SetRSA_CONF_RSA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.RSA_CONF.Reg, volatile.LoadUint32(&o.RSA_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetRSA_CONF_RSA_CLK_EN() uint32 { + return volatile.LoadUint32(&o.RSA_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetRSA_CONF_RSA_RST_EN(value uint32) { + volatile.StoreUint32(&o.RSA_CONF.Reg, volatile.LoadUint32(&o.RSA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetRSA_CONF_RSA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.RSA_CONF.Reg) & 0x2) >> 1 +} + +// PCR.RSA_PD_CTRL: RSA power control register +func (o *PCR_Type) SetRSA_PD_CTRL_RSA_MEM_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetRSA_PD_CTRL_RSA_MEM_PD() uint32 { + return volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x1 +} +func (o *PCR_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x4) >> 2 +} + +// PCR.ECC_CONF: ECC configuration register +func (o *PCR_Type) SetECC_CONF_ECC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.ECC_CONF.Reg, volatile.LoadUint32(&o.ECC_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetECC_CONF_ECC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.ECC_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetECC_CONF_ECC_RST_EN(value uint32) { + volatile.StoreUint32(&o.ECC_CONF.Reg, volatile.LoadUint32(&o.ECC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetECC_CONF_ECC_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ECC_CONF.Reg) & 0x2) >> 1 +} + +// PCR.ECC_PD_CTRL: ECC power control register +func (o *PCR_Type) SetECC_PD_CTRL_ECC_MEM_PD(value uint32) { + volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetECC_PD_CTRL_ECC_MEM_PD() uint32 { + return volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x1 +} +func (o *PCR_Type) SetECC_PD_CTRL_ECC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetECC_PD_CTRL_ECC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetECC_PD_CTRL_ECC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetECC_PD_CTRL_ECC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x4) >> 2 +} + +// PCR.DS_CONF: DS configuration register +func (o *PCR_Type) SetDS_CONF_DS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DS_CONF.Reg, volatile.LoadUint32(&o.DS_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetDS_CONF_DS_CLK_EN() uint32 { + return volatile.LoadUint32(&o.DS_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetDS_CONF_DS_RST_EN(value uint32) { + volatile.StoreUint32(&o.DS_CONF.Reg, volatile.LoadUint32(&o.DS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetDS_CONF_DS_RST_EN() uint32 { + return (volatile.LoadUint32(&o.DS_CONF.Reg) & 0x2) >> 1 +} + +// PCR.HMAC_CONF: HMAC configuration register +func (o *PCR_Type) SetHMAC_CONF_HMAC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.HMAC_CONF.Reg, volatile.LoadUint32(&o.HMAC_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetHMAC_CONF_HMAC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.HMAC_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetHMAC_CONF_HMAC_RST_EN(value uint32) { + volatile.StoreUint32(&o.HMAC_CONF.Reg, volatile.LoadUint32(&o.HMAC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetHMAC_CONF_HMAC_RST_EN() uint32 { + return (volatile.LoadUint32(&o.HMAC_CONF.Reg) & 0x2) >> 1 +} + +// PCR.IOMUX_CONF: IOMUX configuration register +func (o *PCR_Type) SetIOMUX_CONF_IOMUX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.IOMUX_CONF.Reg, volatile.LoadUint32(&o.IOMUX_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetIOMUX_CONF_IOMUX_CLK_EN() uint32 { + return volatile.LoadUint32(&o.IOMUX_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetIOMUX_CONF_IOMUX_RST_EN(value uint32) { + volatile.StoreUint32(&o.IOMUX_CONF.Reg, volatile.LoadUint32(&o.IOMUX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetIOMUX_CONF_IOMUX_RST_EN() uint32 { + return (volatile.LoadUint32(&o.IOMUX_CONF.Reg) & 0x2) >> 1 +} + +// PCR.IOMUX_CLK_CONF: IOMUX_CLK configuration register +func (o *PCR_Type) SetIOMUX_CLK_CONF_IOMUX_FUNC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.IOMUX_CLK_CONF.Reg, volatile.LoadUint32(&o.IOMUX_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetIOMUX_CLK_CONF_IOMUX_FUNC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IOMUX_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetIOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.IOMUX_CLK_CONF.Reg, volatile.LoadUint32(&o.IOMUX_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetIOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.IOMUX_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.MEM_MONITOR_CONF: MEM_MONITOR configuration register +func (o *PCR_Type) SetMEM_MONITOR_CONF_MEM_MONITOR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MEM_MONITOR_CONF.Reg, volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetMEM_MONITOR_CONF_MEM_MONITOR_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetMEM_MONITOR_CONF_MEM_MONITOR_RST_EN(value uint32) { + volatile.StoreUint32(&o.MEM_MONITOR_CONF.Reg, volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetMEM_MONITOR_CONF_MEM_MONITOR_RST_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg) & 0x2) >> 1 +} + +// PCR.REGDMA_CONF: REGDMA configuration register +func (o *PCR_Type) SetREGDMA_CONF_REGDMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetREGDMA_CONF_REGDMA_CLK_EN() uint32 { + return volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetREGDMA_CONF_REGDMA_RST_EN(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetREGDMA_CONF_REGDMA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x2) >> 1 +} + +// PCR.RETENTION_CONF: retention configuration register +func (o *PCR_Type) SetRETENTION_CONF_RETENTION_CLK_EN(value uint32) { + volatile.StoreUint32(&o.RETENTION_CONF.Reg, volatile.LoadUint32(&o.RETENTION_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetRETENTION_CONF_RETENTION_CLK_EN() uint32 { + return volatile.LoadUint32(&o.RETENTION_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetRETENTION_CONF_RETENTION_RST_EN(value uint32) { + volatile.StoreUint32(&o.RETENTION_CONF.Reg, volatile.LoadUint32(&o.RETENTION_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetRETENTION_CONF_RETENTION_RST_EN() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CONF.Reg) & 0x2) >> 1 +} + +// PCR.TRACE_CONF: TRACE configuration register +func (o *PCR_Type) SetTRACE_CONF_TRACE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TRACE_CONF.Reg, volatile.LoadUint32(&o.TRACE_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetTRACE_CONF_TRACE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TRACE_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetTRACE_CONF_TRACE_RST_EN(value uint32) { + volatile.StoreUint32(&o.TRACE_CONF.Reg, volatile.LoadUint32(&o.TRACE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTRACE_CONF_TRACE_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TRACE_CONF.Reg) & 0x2) >> 1 +} + +// PCR.ASSIST_CONF: ASSIST configuration register +func (o *PCR_Type) SetASSIST_CONF_ASSIST_CLK_EN(value uint32) { + volatile.StoreUint32(&o.ASSIST_CONF.Reg, volatile.LoadUint32(&o.ASSIST_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetASSIST_CONF_ASSIST_CLK_EN() uint32 { + return volatile.LoadUint32(&o.ASSIST_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetASSIST_CONF_ASSIST_RST_EN(value uint32) { + volatile.StoreUint32(&o.ASSIST_CONF.Reg, volatile.LoadUint32(&o.ASSIST_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetASSIST_CONF_ASSIST_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ASSIST_CONF.Reg) & 0x2) >> 1 +} + +// PCR.CACHE_CONF: CACHE configuration register +func (o *PCR_Type) SetCACHE_CONF_CACHE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF.Reg, volatile.LoadUint32(&o.CACHE_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetCACHE_CONF_CACHE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CACHE_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetCACHE_CONF_CACHE_RST_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF.Reg, volatile.LoadUint32(&o.CACHE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetCACHE_CONF_CACHE_RST_EN() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF.Reg) & 0x2) >> 1 +} + +// PCR.MODEM_APB_CONF: MODEM_APB configuration register +func (o *PCR_Type) SetMODEM_APB_CONF_MODEM_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MODEM_APB_CONF.Reg, volatile.LoadUint32(&o.MODEM_APB_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetMODEM_APB_CONF_MODEM_APB_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MODEM_APB_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetMODEM_APB_CONF_MODEM_RST_EN(value uint32) { + volatile.StoreUint32(&o.MODEM_APB_CONF.Reg, volatile.LoadUint32(&o.MODEM_APB_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetMODEM_APB_CONF_MODEM_RST_EN() uint32 { + return (volatile.LoadUint32(&o.MODEM_APB_CONF.Reg) & 0x2) >> 1 +} + +// PCR.TIMEOUT_CONF: TIMEOUT configuration register +func (o *PCR_Type) SetTIMEOUT_CONF_CPU_TIMEOUT_RST_EN(value uint32) { + volatile.StoreUint32(&o.TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.TIMEOUT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTIMEOUT_CONF_CPU_TIMEOUT_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TIMEOUT_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetTIMEOUT_CONF_HP_TIMEOUT_RST_EN(value uint32) { + volatile.StoreUint32(&o.TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.TIMEOUT_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetTIMEOUT_CONF_HP_TIMEOUT_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TIMEOUT_CONF.Reg) & 0x4) >> 2 +} + +// PCR.SYSCLK_CONF: SYSCLK configuration register +func (o *PCR_Type) SetSYSCLK_CONF_LS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetSYSCLK_CONF_LS_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetSYSCLK_CONF_HS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetSYSCLK_CONF_HS_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0xff00) >> 8 +} +func (o *PCR_Type) SetSYSCLK_CONF_SOC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x30000)|value<<16) +} +func (o *PCR_Type) GetSYSCLK_CONF_SOC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x30000) >> 16 +} +func (o *PCR_Type) SetSYSCLK_CONF_CLK_XTAL_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x7f000000)|value<<24) +} +func (o *PCR_Type) GetSYSCLK_CONF_CLK_XTAL_FREQ() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x7f000000) >> 24 +} + +// PCR.CPU_WAITI_CONF: CPU_WAITI configuration register +func (o *PCR_Type) SetCPU_WAITI_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x3)|value) +} +func (o *PCR_Type) GetCPU_WAITI_CONF_CPUPERIOD_SEL() uint32 { + return volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x3 +} +func (o *PCR_Type) SetCPU_WAITI_CONF_PLL_FREQ_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetCPU_WAITI_CONF_PLL_FREQ_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetCPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetCPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetCPU_WAITI_CONF_CPU_WAITI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *PCR_Type) GetCPU_WAITI_CONF_CPU_WAITI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0xf0) >> 4 +} + +// PCR.CPU_FREQ_CONF: CPU_FREQ configuration register +func (o *PCR_Type) SetCPU_FREQ_CONF_CPU_LS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_FREQ_CONF.Reg, volatile.LoadUint32(&o.CPU_FREQ_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetCPU_FREQ_CONF_CPU_LS_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CPU_FREQ_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetCPU_FREQ_CONF_CPU_HS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_FREQ_CONF.Reg, volatile.LoadUint32(&o.CPU_FREQ_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetCPU_FREQ_CONF_CPU_HS_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.CPU_FREQ_CONF.Reg) & 0xff00) >> 8 +} +func (o *PCR_Type) SetCPU_FREQ_CONF_CPU_HS_120M_FORCE(value uint32) { + volatile.StoreUint32(&o.CPU_FREQ_CONF.Reg, volatile.LoadUint32(&o.CPU_FREQ_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *PCR_Type) GetCPU_FREQ_CONF_CPU_HS_120M_FORCE() uint32 { + return (volatile.LoadUint32(&o.CPU_FREQ_CONF.Reg) & 0x10000) >> 16 +} + +// PCR.AHB_FREQ_CONF: AHB_FREQ configuration register +func (o *PCR_Type) SetAHB_FREQ_CONF_AHB_LS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.AHB_FREQ_CONF.Reg, volatile.LoadUint32(&o.AHB_FREQ_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetAHB_FREQ_CONF_AHB_LS_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.AHB_FREQ_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetAHB_FREQ_CONF_AHB_HS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.AHB_FREQ_CONF.Reg, volatile.LoadUint32(&o.AHB_FREQ_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetAHB_FREQ_CONF_AHB_HS_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.AHB_FREQ_CONF.Reg) & 0xff00) >> 8 +} + +// PCR.APB_FREQ_CONF: APB_FREQ configuration register +func (o *PCR_Type) SetAPB_FREQ_CONF_APB_DECREASE_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.APB_FREQ_CONF.Reg, volatile.LoadUint32(&o.APB_FREQ_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetAPB_FREQ_CONF_APB_DECREASE_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.APB_FREQ_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetAPB_FREQ_CONF_APB_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.APB_FREQ_CONF.Reg, volatile.LoadUint32(&o.APB_FREQ_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetAPB_FREQ_CONF_APB_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.APB_FREQ_CONF.Reg) & 0xff00) >> 8 +} + +// PCR.SYSCLK_FREQ_QUERY_0: SYSCLK frequency query 0 register +func (o *PCR_Type) SetSYSCLK_FREQ_QUERY_0_FOSC_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_FREQ_QUERY_0.Reg, volatile.LoadUint32(&o.SYSCLK_FREQ_QUERY_0.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetSYSCLK_FREQ_QUERY_0_FOSC_FREQ() uint32 { + return volatile.LoadUint32(&o.SYSCLK_FREQ_QUERY_0.Reg) & 0xff +} +func (o *PCR_Type) SetSYSCLK_FREQ_QUERY_0_PLL_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_FREQ_QUERY_0.Reg, volatile.LoadUint32(&o.SYSCLK_FREQ_QUERY_0.Reg)&^(0x3ff00)|value<<8) +} +func (o *PCR_Type) GetSYSCLK_FREQ_QUERY_0_PLL_FREQ() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_FREQ_QUERY_0.Reg) & 0x3ff00) >> 8 +} + +// PCR.PLL_DIV_CLK_EN: SPLL DIV clock-gating configuration register +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_240M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_240M_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x1 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_160M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_160M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_120M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_120M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_80M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_80M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_48M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x10)|value<<4) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_48M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x10) >> 4 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_40M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x20)|value<<5) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_40M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x20) >> 5 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_20M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x40)|value<<6) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_20M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x40) >> 6 +} + +// PCR.CTRL_CLK_OUT_EN: CLK_OUT_EN configuration register +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK20_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK20_OEN() uint32 { + return volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x1 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK22_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK22_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK44_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK44_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK80_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x10)|value<<4) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK80_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x10) >> 4 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK160_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x20)|value<<5) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK160_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x20) >> 5 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK_320M_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x40)|value<<6) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK_320M_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x40) >> 6 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK_ADC_INF_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x80)|value<<7) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK_ADC_INF_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x80) >> 7 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x100)|value<<8) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x100) >> 8 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK40X_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x200)|value<<9) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK40X_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x200) >> 9 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK_XTAL_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x400)|value<<10) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK_XTAL_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x400) >> 10 +} + +// PCR.CTRL_TICK_CONF: TICK configuration register +func (o *PCR_Type) SetCTRL_TICK_CONF_XTAL_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL_TICK_CONF.Reg, volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetCTRL_TICK_CONF_XTAL_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetCTRL_TICK_CONF_FOSC_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL_TICK_CONF.Reg, volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetCTRL_TICK_CONF_FOSC_TICK_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg) & 0xff00) >> 8 +} +func (o *PCR_Type) SetCTRL_TICK_CONF_TICK_ENABLE(value uint32) { + volatile.StoreUint32(&o.CTRL_TICK_CONF.Reg, volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *PCR_Type) GetCTRL_TICK_CONF_TICK_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg) & 0x10000) >> 16 +} +func (o *PCR_Type) SetCTRL_TICK_CONF_RST_TICK_CNT(value uint32) { + volatile.StoreUint32(&o.CTRL_TICK_CONF.Reg, volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *PCR_Type) GetCTRL_TICK_CONF_RST_TICK_CNT() uint32 { + return (volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg) & 0x20000) >> 17 +} + +// PCR.CTRL_32K_CONF: 32KHz clock configuration register +func (o *PCR_Type) SetCTRL_32K_CONF_CLK_32K_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL_32K_CONF.Reg, volatile.LoadUint32(&o.CTRL_32K_CONF.Reg)&^(0x3)|value) +} +func (o *PCR_Type) GetCTRL_32K_CONF_CLK_32K_SEL() uint32 { + return volatile.LoadUint32(&o.CTRL_32K_CONF.Reg) & 0x3 +} + +// PCR.SRAM_POWER_CONF: HP SRAM/ROM configuration register +func (o *PCR_Type) SetSRAM_POWER_CONF_SRAM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg)&^(0xf)|value) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_SRAM_FORCE_PU() uint32 { + return volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg) & 0xf +} +func (o *PCR_Type) SetSRAM_POWER_CONF_SRAM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_SRAM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg) & 0xf0) >> 4 +} +func (o *PCR_Type) SetSRAM_POWER_CONF_SRAM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg)&^(0xf00)|value<<8) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_SRAM_CLKGATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg) & 0xf00) >> 8 +} +func (o *PCR_Type) SetSRAM_POWER_CONF_ROM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg)&^(0x7000)|value<<12) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_ROM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg) & 0x7000) >> 12 +} +func (o *PCR_Type) SetSRAM_POWER_CONF_ROM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg)&^(0x38000)|value<<15) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_ROM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg) & 0x38000) >> 15 +} +func (o *PCR_Type) SetSRAM_POWER_CONF_ROM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg)&^(0x1c0000)|value<<18) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_ROM_CLKGATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF.Reg) & 0x1c0000) >> 18 +} + +// PCR.RESET_EVENT_BYPASS: reset event bypass backdoor configuration register +func (o *PCR_Type) SetRESET_EVENT_BYPASS_APM(value uint32) { + volatile.StoreUint32(&o.RESET_EVENT_BYPASS.Reg, volatile.LoadUint32(&o.RESET_EVENT_BYPASS.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetRESET_EVENT_BYPASS_APM() uint32 { + return volatile.LoadUint32(&o.RESET_EVENT_BYPASS.Reg) & 0x1 +} +func (o *PCR_Type) SetRESET_EVENT_BYPASS(value uint32) { + volatile.StoreUint32(&o.RESET_EVENT_BYPASS.Reg, volatile.LoadUint32(&o.RESET_EVENT_BYPASS.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetRESET_EVENT_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RESET_EVENT_BYPASS.Reg) & 0x2) >> 1 +} + +// PCR.FPGA_DEBUG: fpga debug register +func (o *PCR_Type) SetFPGA_DEBUG(value uint32) { + volatile.StoreUint32(&o.FPGA_DEBUG.Reg, value) +} +func (o *PCR_Type) GetFPGA_DEBUG() uint32 { + return volatile.LoadUint32(&o.FPGA_DEBUG.Reg) +} + +// PCR.CLOCK_GATE: PCR clock gating configure register +func (o *PCR_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// PCR.DATE: Date register. +func (o *PCR_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *PCR_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// PMU Peripheral +type PMU_Type struct { + HP_ACTIVE_DIG_POWER volatile.Register32 // 0x0 + HP_ACTIVE_ICG_HP_FUNC volatile.Register32 // 0x4 + HP_ACTIVE_ICG_HP_APB volatile.Register32 // 0x8 + HP_ACTIVE_ICG_MODEM volatile.Register32 // 0xC + HP_ACTIVE_HP_SYS_CNTL volatile.Register32 // 0x10 + HP_ACTIVE_HP_CK_POWER volatile.Register32 // 0x14 + HP_ACTIVE_BIAS volatile.Register32 // 0x18 + HP_ACTIVE_BACKUP volatile.Register32 // 0x1C + HP_ACTIVE_BACKUP_CLK volatile.Register32 // 0x20 + HP_ACTIVE_SYSCLK volatile.Register32 // 0x24 + HP_ACTIVE_HP_REGULATOR0 volatile.Register32 // 0x28 + HP_ACTIVE_HP_REGULATOR1 volatile.Register32 // 0x2C + HP_ACTIVE_XTAL volatile.Register32 // 0x30 + HP_MODEM_DIG_POWER volatile.Register32 // 0x34 + HP_MODEM_ICG_HP_FUNC volatile.Register32 // 0x38 + HP_MODEM_ICG_HP_APB volatile.Register32 // 0x3C + HP_MODEM_ICG_MODEM volatile.Register32 // 0x40 + HP_MODEM_HP_SYS_CNTL volatile.Register32 // 0x44 + HP_MODEM_HP_CK_POWER volatile.Register32 // 0x48 + HP_MODEM_BIAS volatile.Register32 // 0x4C + HP_MODEM_BACKUP volatile.Register32 // 0x50 + HP_MODEM_BACKUP_CLK volatile.Register32 // 0x54 + HP_MODEM_SYSCLK volatile.Register32 // 0x58 + HP_MODEM_HP_REGULATOR0 volatile.Register32 // 0x5C + HP_MODEM_HP_REGULATOR1 volatile.Register32 // 0x60 + HP_MODEM_XTAL volatile.Register32 // 0x64 + HP_SLEEP_DIG_POWER volatile.Register32 // 0x68 + HP_SLEEP_ICG_HP_FUNC volatile.Register32 // 0x6C + HP_SLEEP_ICG_HP_APB volatile.Register32 // 0x70 + HP_SLEEP_ICG_MODEM volatile.Register32 // 0x74 + HP_SLEEP_HP_SYS_CNTL volatile.Register32 // 0x78 + HP_SLEEP_HP_CK_POWER volatile.Register32 // 0x7C + HP_SLEEP_BIAS volatile.Register32 // 0x80 + HP_SLEEP_BACKUP volatile.Register32 // 0x84 + HP_SLEEP_BACKUP_CLK volatile.Register32 // 0x88 + HP_SLEEP_SYSCLK volatile.Register32 // 0x8C + HP_SLEEP_HP_REGULATOR0 volatile.Register32 // 0x90 + HP_SLEEP_HP_REGULATOR1 volatile.Register32 // 0x94 + HP_SLEEP_XTAL volatile.Register32 // 0x98 + HP_SLEEP_LP_REGULATOR0 volatile.Register32 // 0x9C + HP_SLEEP_LP_REGULATOR1 volatile.Register32 // 0xA0 + HP_SLEEP_LP_DCDC_RESERVE volatile.Register32 // 0xA4 + HP_SLEEP_LP_DIG_POWER volatile.Register32 // 0xA8 + HP_SLEEP_LP_CK_POWER volatile.Register32 // 0xAC + LP_SLEEP_LP_BIAS_RESERVE volatile.Register32 // 0xB0 + LP_SLEEP_LP_REGULATOR0 volatile.Register32 // 0xB4 + LP_SLEEP_LP_REGULATOR1 volatile.Register32 // 0xB8 + LP_SLEEP_XTAL volatile.Register32 // 0xBC + LP_SLEEP_LP_DIG_POWER volatile.Register32 // 0xC0 + LP_SLEEP_LP_CK_POWER volatile.Register32 // 0xC4 + LP_SLEEP_BIAS volatile.Register32 // 0xC8 + IMM_HP_CK_POWER volatile.Register32 // 0xCC + IMM_SLEEP_SYSCLK volatile.Register32 // 0xD0 + IMM_HP_FUNC_ICG volatile.Register32 // 0xD4 + IMM_HP_APB_ICG volatile.Register32 // 0xD8 + IMM_MODEM_ICG volatile.Register32 // 0xDC + IMM_LP_ICG volatile.Register32 // 0xE0 + IMM_PAD_HOLD_ALL volatile.Register32 // 0xE4 + IMM_I2C_ISO volatile.Register32 // 0xE8 + POWER_WAIT_TIMER0 volatile.Register32 // 0xEC + POWER_WAIT_TIMER1 volatile.Register32 // 0xF0 + POWER_PD_TOP_CNTL volatile.Register32 // 0xF4 + POWER_PD_HPAON_CNTL volatile.Register32 // 0xF8 + POWER_PD_HPCPU_CNTL volatile.Register32 // 0xFC + POWER_PD_HPPERI_RESERVE volatile.Register32 // 0x100 + POWER_PD_HPWIFI_CNTL volatile.Register32 // 0x104 + POWER_PD_LPPERI_CNTL volatile.Register32 // 0x108 + POWER_PD_MEM_CNTL volatile.Register32 // 0x10C + POWER_PD_MEM_MASK volatile.Register32 // 0x110 + POWER_HP_PAD volatile.Register32 // 0x114 + POWER_VDD_SPI_CNTL volatile.Register32 // 0x118 + POWER_CK_WAIT_CNTL volatile.Register32 // 0x11C + SLP_WAKEUP_CNTL0 volatile.Register32 // 0x120 + SLP_WAKEUP_CNTL1 volatile.Register32 // 0x124 + SLP_WAKEUP_CNTL2 volatile.Register32 // 0x128 + SLP_WAKEUP_CNTL3 volatile.Register32 // 0x12C + SLP_WAKEUP_CNTL4 volatile.Register32 // 0x130 + SLP_WAKEUP_CNTL5 volatile.Register32 // 0x134 + SLP_WAKEUP_CNTL6 volatile.Register32 // 0x138 + SLP_WAKEUP_CNTL7 volatile.Register32 // 0x13C + SLP_WAKEUP_STATUS0 volatile.Register32 // 0x140 + SLP_WAKEUP_STATUS1 volatile.Register32 // 0x144 + HP_CK_POWERON volatile.Register32 // 0x148 + HP_CK_CNTL volatile.Register32 // 0x14C + POR_STATUS volatile.Register32 // 0x150 + RF_PWC volatile.Register32 // 0x154 + BACKUP_CFG volatile.Register32 // 0x158 + INT_RAW volatile.Register32 // 0x15C + HP_INT_ST volatile.Register32 // 0x160 + HP_INT_ENA volatile.Register32 // 0x164 + HP_INT_CLR volatile.Register32 // 0x168 + LP_INT_RAW volatile.Register32 // 0x16C + LP_INT_ST volatile.Register32 // 0x170 + LP_INT_ENA volatile.Register32 // 0x174 + LP_INT_CLR volatile.Register32 // 0x178 + LP_CPU_PWR0 volatile.Register32 // 0x17C + LP_CPU_PWR1 volatile.Register32 // 0x180 + HP_LP_CPU_COMM volatile.Register32 // 0x184 + HP_REGULATOR_CFG volatile.Register32 // 0x188 + MAIN_STATE volatile.Register32 // 0x18C + PWR_STATE volatile.Register32 // 0x190 + CLK_STATE0 volatile.Register32 // 0x194 + CLK_STATE1 volatile.Register32 // 0x198 + CLK_STATE2 volatile.Register32 // 0x19C + VDD_SPI_STATUS volatile.Register32 // 0x1A0 + _ [600]byte + DATE volatile.Register32 // 0x3FC +} + +// PMU.HP_ACTIVE_DIG_POWER: need_des +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_ACTIVE_ICG_HP_FUNC: need_des +func (o *PMU_Type) SetHP_ACTIVE_ICG_HP_FUNC(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_ICG_HP_FUNC.Reg, value) +} +func (o *PMU_Type) GetHP_ACTIVE_ICG_HP_FUNC() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_ICG_HP_FUNC.Reg) +} + +// PMU.HP_ACTIVE_ICG_HP_APB: need_des +func (o *PMU_Type) SetHP_ACTIVE_ICG_HP_APB(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_ICG_HP_APB.Reg, value) +} +func (o *PMU_Type) GetHP_ACTIVE_ICG_HP_APB() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_ICG_HP_APB.Reg) +} + +// PMU.HP_ACTIVE_ICG_MODEM: need_des +func (o *PMU_Type) SetHP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_ACTIVE_ICG_MODEM.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_ICG_MODEM.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_ACTIVE_HP_SYS_CNTL: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_ACTIVE_HP_CK_POWER: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x40000000) >> 30 +} + +// PMU.HP_ACTIVE_BIAS: need_des +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x3c000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x3c000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_ACTIVE_BACKUP: need_des +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x30)|value<<4) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x30) >> 4 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0xc0)|value<<6) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0xc0) >> 6 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x800)|value<<11) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x800) >> 11 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0xc000)|value<<14) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0xc000) >> 14 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x30000) >> 16 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x700000)|value<<20) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x700000) >> 20 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x40000000) >> 30 +} + +// PMU.HP_ACTIVE_BACKUP_CLK: need_des +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_CLK(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP_CLK.Reg, value) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_CLK() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_BACKUP_CLK.Reg) +} + +// PMU.HP_ACTIVE_SYSCLK: need_des +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_ACTIVE_HP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x1f0)|value<<4) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x1f0) >> 4 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x3e00)|value<<9) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x3e00) >> 9 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x780000)|value<<19) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x780000) >> 19 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_ACTIVE_HP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg)&^(0xffffff00)|value<<8) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg) & 0xffffff00) >> 8 +} + +// PMU.HP_ACTIVE_XTAL: need_des +func (o *PMU_Type) SetHP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_XTAL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_MODEM_DIG_POWER: need_des +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_MODEM_ICG_HP_FUNC: need_des +func (o *PMU_Type) SetHP_MODEM_ICG_HP_FUNC(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_ICG_HP_FUNC.Reg, value) +} +func (o *PMU_Type) GetHP_MODEM_ICG_HP_FUNC() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_ICG_HP_FUNC.Reg) +} + +// PMU.HP_MODEM_ICG_HP_APB: need_des +func (o *PMU_Type) SetHP_MODEM_ICG_HP_APB(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_ICG_HP_APB.Reg, value) +} +func (o *PMU_Type) GetHP_MODEM_ICG_HP_APB() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_ICG_HP_APB.Reg) +} + +// PMU.HP_MODEM_ICG_MODEM: need_des +func (o *PMU_Type) SetHP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_MODEM_ICG_MODEM.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_ICG_MODEM.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_MODEM_HP_SYS_CNTL: need_des +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_MODEM_HP_CK_POWER: need_des +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x40000000) >> 30 +} + +// PMU.HP_MODEM_BIAS: need_des +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_DBG_ATTEN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x3c000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_DBG_ATTEN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x3c000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_PD_CUR(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_MODEM_BACKUP: need_des +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x30)|value<<4) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x30) >> 4 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x800)|value<<11) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x800) >> 11 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0xc000)|value<<14) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0xc000) >> 14 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x700000)|value<<20) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x700000) >> 20 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_MODEM_BACKUP_CLK: need_des +func (o *PMU_Type) SetHP_MODEM_BACKUP_CLK(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP_CLK.Reg, value) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_CLK() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_BACKUP_CLK.Reg) +} + +// PMU.HP_MODEM_SYSCLK: need_des +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_MODEM_HP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x780000)|value<<19) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x780000) >> 19 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_MODEM_HP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR1.Reg)&^(0xffffff00)|value<<8) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR1.Reg) & 0xffffff00) >> 8 +} + +// PMU.HP_MODEM_XTAL: need_des +func (o *PMU_Type) SetHP_MODEM_XTAL_HP_MODEM_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_XTAL.Reg, volatile.LoadUint32(&o.HP_MODEM_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_MODEM_XTAL_HP_MODEM_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_DIG_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_ICG_HP_FUNC: need_des +func (o *PMU_Type) SetHP_SLEEP_ICG_HP_FUNC(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_ICG_HP_FUNC.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_ICG_HP_FUNC() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_ICG_HP_FUNC.Reg) +} + +// PMU.HP_SLEEP_ICG_HP_APB: need_des +func (o *PMU_Type) SetHP_SLEEP_ICG_HP_APB(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_ICG_HP_APB.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_ICG_HP_APB() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_ICG_HP_APB.Reg) +} + +// PMU.HP_SLEEP_ICG_MODEM: need_des +func (o *PMU_Type) SetHP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_SLEEP_ICG_MODEM.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_ICG_MODEM.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_SLEEP_HP_SYS_CNTL: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_SLEEP_HP_CK_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x40000000) >> 30 +} + +// PMU.HP_SLEEP_BIAS: need_des +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x3c000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x3c000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_PD_CUR(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_BACKUP: need_des +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0xc0)|value<<6) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0xc0) >> 6 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x300)|value<<8) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x300) >> 8 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x30000) >> 16 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0xc0000)|value<<18) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0xc0000) >> 18 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x1c000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x1c000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_BACKUP_CLK: need_des +func (o *PMU_Type) SetHP_SLEEP_BACKUP_CLK(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP_CLK.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_CLK() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_BACKUP_CLK.Reg) +} + +// PMU.HP_SLEEP_SYSCLK: need_des +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_SLEEP_HP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x780000)|value<<19) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x780000) >> 19 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_SLEEP_HP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg)&^(0xffffff00)|value<<8) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg) & 0xffffff00) >> 8 +} + +// PMU.HP_SLEEP_XTAL: need_des +func (o *PMU_Type) SetHP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_XTAL.Reg, volatile.LoadUint32(&o.HP_SLEEP_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_LP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_SLEEP_LP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg) & 0xf0000000) >> 28 +} + +// PMU.HP_SLEEP_LP_DCDC_RESERVE: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_DCDC_RESERVE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DCDC_RESERVE.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DCDC_RESERVE() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_LP_DCDC_RESERVE.Reg) +} + +// PMU.HP_SLEEP_LP_DIG_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_LP_CK_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_LP_BIAS_RESERVE: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_BIAS_RESERVE(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_BIAS_RESERVE.Reg, value) +} +func (o *PMU_Type) GetLP_SLEEP_LP_BIAS_RESERVE() uint32 { + return volatile.LoadUint32(&o.LP_SLEEP_LP_BIAS_RESERVE.Reg) +} + +// PMU.LP_SLEEP_LP_REGULATOR0: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.LP_SLEEP_LP_REGULATOR1: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg) & 0xf0000000) >> 28 +} + +// PMU.LP_SLEEP_XTAL: need_des +func (o *PMU_Type) SetLP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_XTAL.Reg, volatile.LoadUint32(&o.LP_SLEEP_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_LP_DIG_POWER: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_LP_CK_POWER: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_BIAS: need_des +func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x3c000000)|value<<26) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x3c000000) >> 26 +} +func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_PD_CUR(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_SLEEP_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_HP_CK_POWER: need_des +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG() uint32 { + return volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x1 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x40)|value<<6) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x40) >> 6 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_SLEEP_SYSCLK: need_des +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_HP_FUNC_ICG: need_des +func (o *PMU_Type) SetIMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.IMM_HP_FUNC_ICG.Reg, volatile.LoadUint32(&o.IMM_HP_FUNC_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_FUNC_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_HP_APB_ICG: need_des +func (o *PMU_Type) SetIMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN(value uint32) { + volatile.StoreUint32(&o.IMM_HP_APB_ICG.Reg, volatile.LoadUint32(&o.IMM_HP_APB_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_APB_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_MODEM_ICG: need_des +func (o *PMU_Type) SetIMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN(value uint32) { + volatile.StoreUint32(&o.IMM_MODEM_ICG.Reg, volatile.LoadUint32(&o.IMM_MODEM_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_MODEM_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_LP_ICG: need_des +func (o *PMU_Type) SetIMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_LP_ICG.Reg, volatile.LoadUint32(&o.IMM_LP_ICG.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_LP_ICG.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_LP_ICG.Reg, volatile.LoadUint32(&o.IMM_LP_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_LP_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_PAD_HOLD_ALL: need_des +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_I2C_ISO: need_des +func (o *PMU_Type) SetIMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.IMM_I2C_ISO.Reg, volatile.LoadUint32(&o.IMM_I2C_ISO.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_I2C_ISO.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_I2C_ISO_TIE_LOW_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.IMM_I2C_ISO.Reg, volatile.LoadUint32(&o.IMM_I2C_ISO.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_I2C_ISO_TIE_LOW_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_I2C_ISO.Reg) & 0x80000000) >> 31 +} + +// PMU.POWER_WAIT_TIMER0: need_des +func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0x3fe0)|value<<5) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0x3fe0) >> 5 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0x7fc000)|value<<14) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0x7fc000) >> 14 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0xff800000)|value<<23) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0xff800000) >> 23 +} + +// PMU.POWER_WAIT_TIMER1: need_des +func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0xfe00)|value<<9) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0xfe00) >> 9 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0x7f0000)|value<<16) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0x7f0000) >> 16 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0xff800000)|value<<23) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0xff800000) >> 23 +} + +// PMU.POWER_PD_TOP_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_PD_TOP_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x7c0)|value<<6) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_PD_TOP_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x7c0) >> 6 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_PD_TOP_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_PD_TOP_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_HPAON_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_PD_HP_AON_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x7c0)|value<<6) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_PD_HP_AON_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x7c0) >> 6 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_PD_HP_AON_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_PD_HP_AON_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_HPCPU_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_PD_HP_CPU_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x7c0)|value<<6) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_PD_HP_CPU_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x7c0) >> 6 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_PD_HP_CPU_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_PD_HP_CPU_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_HPPERI_RESERVE: need_des +func (o *PMU_Type) SetPOWER_PD_HPPERI_RESERVE(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPPERI_RESERVE.Reg, value) +} +func (o *PMU_Type) GetPOWER_PD_HPPERI_RESERVE() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPPERI_RESERVE.Reg) +} + +// PMU.POWER_PD_HPWIFI_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_PD_HP_WIFI_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x7c0)|value<<6) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_PD_HP_WIFI_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x7c0) >> 6 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_PD_HP_WIFI_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_PD_HP_WIFI_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_LPPERI_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x20) >> 5 +} + +// PMU.POWER_PD_MEM_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg)&^(0xf)|value) +} +func (o *PMU_Type) GetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_ISO() uint32 { + return volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg) & 0xf +} +func (o *PMU_Type) SetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg)&^(0xf0)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg) & 0xf0) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg)&^(0xf000000)|value<<24) +} +func (o *PMU_Type) GetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg) & 0xf000000) >> 24 +} +func (o *PMU_Type) SetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg) & 0xf0000000) >> 28 +} + +// PMU.POWER_PD_MEM_MASK: need_des +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM2_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x1f)|value) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM2_PD_MASK() uint32 { + return volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x1f +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM1_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x3e0)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM1_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x3e0) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM0_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x7c00)|value<<10) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM0_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x7c00) >> 10 +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM2_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x3e0000)|value<<17) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM2_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x3e0000) >> 17 +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM1_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x7c00000)|value<<22) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM1_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x7c00000) >> 22 +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM0_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM0_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_HP_PAD: need_des +func (o *PMU_Type) SetPOWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL(value uint32) { + volatile.StoreUint32(&o.POWER_HP_PAD.Reg, volatile.LoadUint32(&o.POWER_HP_PAD.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL() uint32 { + return volatile.LoadUint32(&o.POWER_HP_PAD.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_HP_PAD_FORCE_HP_PAD_ISO_ALL(value uint32) { + volatile.StoreUint32(&o.POWER_HP_PAD.Reg, volatile.LoadUint32(&o.POWER_HP_PAD.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_HP_PAD_FORCE_HP_PAD_ISO_ALL() uint32 { + return (volatile.LoadUint32(&o.POWER_HP_PAD.Reg) & 0x2) >> 1 +} + +// PMU.POWER_VDD_SPI_CNTL: need_des +func (o *PMU_Type) SetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_WAIT(value uint32) { + volatile.StoreUint32(&o.POWER_VDD_SPI_CNTL.Reg, volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg)&^(0x1ffc0000)|value<<18) +} +func (o *PMU_Type) GetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_WAIT() uint32 { + return (volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg) & 0x1ffc0000) >> 18 +} +func (o *PMU_Type) SetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_SW(value uint32) { + volatile.StoreUint32(&o.POWER_VDD_SPI_CNTL.Reg, volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg)&^(0x60000000)|value<<29) +} +func (o *PMU_Type) GetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_SW() uint32 { + return (volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg) & 0x60000000) >> 29 +} +func (o *PMU_Type) SetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW(value uint32) { + volatile.StoreUint32(&o.POWER_VDD_SPI_CNTL.Reg, volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW() uint32 { + return (volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg) & 0x80000000) >> 31 +} + +// PMU.POWER_CK_WAIT_CNTL: need_des +func (o *PMU_Type) SetPOWER_CK_WAIT_CNTL_WAIT_XTL_STABLE(value uint32) { + volatile.StoreUint32(&o.POWER_CK_WAIT_CNTL.Reg, volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg)&^(0xffff)|value) +} +func (o *PMU_Type) GetPOWER_CK_WAIT_CNTL_WAIT_XTL_STABLE() uint32 { + return volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg) & 0xffff +} +func (o *PMU_Type) SetPOWER_CK_WAIT_CNTL_WAIT_PLL_STABLE(value uint32) { + volatile.StoreUint32(&o.POWER_CK_WAIT_CNTL.Reg, volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg)&^(0xffff0000)|value<<16) +} +func (o *PMU_Type) GetPOWER_CK_WAIT_CNTL_WAIT_PLL_STABLE() uint32 { + return (volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg) & 0xffff0000) >> 16 +} + +// PMU.SLP_WAKEUP_CNTL0: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL0_SLEEP_REQ(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL0.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL0.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL0_SLEEP_REQ() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL0.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_CNTL1: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg) & 0x7fffffff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL1_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL1_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_CNTL2: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL2(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL2.Reg, value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL2() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL2.Reg) +} + +// PMU.SLP_WAKEUP_CNTL3: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0xff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0xff00)|value<<8) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0xff00) >> 8 +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_SLEEP_PRT_SEL(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_SLEEP_PRT_SEL() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0x30000) >> 16 +} + +// PMU.SLP_WAKEUP_CNTL4: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL4.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL4.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL4.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_CNTL5: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL5.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg)&^(0xfffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg) & 0xfffff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL5.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg)&^(0xff000000)|value<<24) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg) & 0xff000000) >> 24 +} + +// PMU.SLP_WAKEUP_CNTL6: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL6.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg)&^(0xfffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg) & 0xfffff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL6.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg) & 0xc0000000) >> 30 +} + +// PMU.SLP_WAKEUP_CNTL7: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL7_ANA_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL7.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL7.Reg)&^(0xffff0000)|value<<16) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL7_ANA_WAIT_TARGET() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL7.Reg) & 0xffff0000) >> 16 +} + +// PMU.SLP_WAKEUP_STATUS0: need_des +func (o *PMU_Type) SetSLP_WAKEUP_STATUS0(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_STATUS0.Reg, value) +} +func (o *PMU_Type) GetSLP_WAKEUP_STATUS0() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_STATUS0.Reg) +} + +// PMU.SLP_WAKEUP_STATUS1: need_des +func (o *PMU_Type) SetSLP_WAKEUP_STATUS1(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_STATUS1.Reg, value) +} +func (o *PMU_Type) GetSLP_WAKEUP_STATUS1() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_STATUS1.Reg) +} + +// PMU.HP_CK_POWERON: need_des +func (o *PMU_Type) SetHP_CK_POWERON_I2C_POR_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.HP_CK_POWERON.Reg, volatile.LoadUint32(&o.HP_CK_POWERON.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetHP_CK_POWERON_I2C_POR_WAIT_TARGET() uint32 { + return volatile.LoadUint32(&o.HP_CK_POWERON.Reg) & 0xff +} + +// PMU.HP_CK_CNTL: need_des +func (o *PMU_Type) SetHP_CK_CNTL_MODIFY_ICG_CNTL_WAIT(value uint32) { + volatile.StoreUint32(&o.HP_CK_CNTL.Reg, volatile.LoadUint32(&o.HP_CK_CNTL.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetHP_CK_CNTL_MODIFY_ICG_CNTL_WAIT() uint32 { + return volatile.LoadUint32(&o.HP_CK_CNTL.Reg) & 0xff +} +func (o *PMU_Type) SetHP_CK_CNTL_SWITCH_ICG_CNTL_WAIT(value uint32) { + volatile.StoreUint32(&o.HP_CK_CNTL.Reg, volatile.LoadUint32(&o.HP_CK_CNTL.Reg)&^(0xff00)|value<<8) +} +func (o *PMU_Type) GetHP_CK_CNTL_SWITCH_ICG_CNTL_WAIT() uint32 { + return (volatile.LoadUint32(&o.HP_CK_CNTL.Reg) & 0xff00) >> 8 +} + +// PMU.POR_STATUS: need_des +func (o *PMU_Type) SetPOR_STATUS_POR_DONE(value uint32) { + volatile.StoreUint32(&o.POR_STATUS.Reg, volatile.LoadUint32(&o.POR_STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetPOR_STATUS_POR_DONE() uint32 { + return (volatile.LoadUint32(&o.POR_STATUS.Reg) & 0x80000000) >> 31 +} + +// PMU.RF_PWC: need_des +func (o *PMU_Type) SetRF_PWC_PERIF_I2C_RSTB(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetRF_PWC_PERIF_I2C_RSTB() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetRF_PWC_XPD_PERIF_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetRF_PWC_XPD_PERIF_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetRF_PWC_XPD_TXRF_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetRF_PWC_XPD_TXRF_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetRF_PWC_XPD_RFRX_PBUS(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetRF_PWC_XPD_RFRX_PBUS() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetRF_PWC_XPD_CKGEN_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetRF_PWC_XPD_CKGEN_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetRF_PWC_XPD_PLL_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetRF_PWC_XPD_PLL_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x80000000) >> 31 +} + +// PMU.BACKUP_CFG: need_des +func (o *PMU_Type) SetBACKUP_CFG_BACKUP_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.BACKUP_CFG.Reg, volatile.LoadUint32(&o.BACKUP_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetBACKUP_CFG_BACKUP_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.BACKUP_CFG.Reg) & 0x80000000) >> 31 +} + +// PMU.INT_RAW: need_des +func (o *PMU_Type) SetINT_RAW_LP_CPU_EXC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetINT_RAW_LP_CPU_EXC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetINT_RAW_SDIO_IDLE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetINT_RAW_SDIO_IDLE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetINT_RAW_SW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetINT_RAW_SW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetINT_RAW_SOC_SLEEP_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetINT_RAW_SOC_SLEEP_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetINT_RAW_SOC_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetINT_RAW_SOC_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_INT_ST: need_des +func (o *PMU_Type) SetHP_INT_ST_LP_CPU_EXC_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_INT_ST_LP_CPU_EXC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_INT_ST_SDIO_IDLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_INT_ST_SDIO_IDLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_INT_ST_SW_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_INT_ST_SW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_INT_ST_SOC_SLEEP_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_INT_ST_SOC_SLEEP_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_INT_ST_SOC_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_INT_ST_SOC_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_INT_ENA: need_des +func (o *PMU_Type) SetHP_INT_ENA_LP_CPU_EXC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_INT_ENA_LP_CPU_EXC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_INT_ENA_SDIO_IDLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_INT_ENA_SDIO_IDLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_INT_ENA_SW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_INT_ENA_SW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_INT_ENA_SOC_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_INT_ENA_SOC_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_INT_CLR: need_des +func (o *PMU_Type) SetHP_INT_CLR_LP_CPU_EXC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_INT_CLR_LP_CPU_EXC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_INT_CLR_SDIO_IDLE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_INT_CLR_SDIO_IDLE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_INT_CLR_SW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_INT_CLR_SW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_INT_CLR_SOC_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_INT_CLR_SOC_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_RAW: need_des +func (o *PMU_Type) SetLP_INT_RAW_LP_CPU_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_RAW_LP_CPU_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_RAW_HP_SW_TRIGGER_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_RAW_HP_SW_TRIGGER_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_ST: need_des +func (o *PMU_Type) SetLP_INT_ST_LP_CPU_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_ST_LP_CPU_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_ST_HP_SW_TRIGGER_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_ST_HP_SW_TRIGGER_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_ENA: need_des +func (o *PMU_Type) SetLP_INT_ENA_LP_CPU_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_ENA_LP_CPU_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_ENA_HP_SW_TRIGGER_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_ENA_HP_SW_TRIGGER_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_CLR: need_des +func (o *PMU_Type) SetLP_INT_CLR_LP_CPU_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_CLR_LP_CPU_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_CLR_HP_SW_TRIGGER_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_CLR_HP_SW_TRIGGER_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_CPU_PWR0: need_des +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_WAITI_RDY(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_WAITI_RDY() uint32 { + return volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x1 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_STALL_RDY(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_STALL_RDY() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_FORCE_STALL(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_FORCE_STALL() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x1fe00000)|value<<21) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x1fe00000) >> 21 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_CPU_PWR1: need_des +func (o *PMU_Type) SetLP_CPU_PWR1_LP_CPU_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR1.Reg, volatile.LoadUint32(&o.LP_CPU_PWR1.Reg)&^(0xffff)|value) +} +func (o *PMU_Type) GetLP_CPU_PWR1_LP_CPU_WAKEUP_EN() uint32 { + return volatile.LoadUint32(&o.LP_CPU_PWR1.Reg) & 0xffff +} +func (o *PMU_Type) SetLP_CPU_PWR1_LP_CPU_SLEEP_REQ(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR1.Reg, volatile.LoadUint32(&o.LP_CPU_PWR1.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_CPU_PWR1_LP_CPU_SLEEP_REQ() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR1.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_LP_CPU_COMM: need_des +func (o *PMU_Type) SetHP_LP_CPU_COMM_LP_TRIGGER_HP(value uint32) { + volatile.StoreUint32(&o.HP_LP_CPU_COMM.Reg, volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_LP_CPU_COMM_LP_TRIGGER_HP() uint32 { + return (volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_LP_CPU_COMM_HP_TRIGGER_LP(value uint32) { + volatile.StoreUint32(&o.HP_LP_CPU_COMM.Reg, volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_LP_CPU_COMM_HP_TRIGGER_LP() uint32 { + return (volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_REGULATOR_CFG: need_des +func (o *PMU_Type) SetHP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL(value uint32) { + volatile.StoreUint32(&o.HP_REGULATOR_CFG.Reg, volatile.LoadUint32(&o.HP_REGULATOR_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL() uint32 { + return (volatile.LoadUint32(&o.HP_REGULATOR_CFG.Reg) & 0x80000000) >> 31 +} + +// PMU.MAIN_STATE: need_des +func (o *PMU_Type) SetMAIN_STATE_MAIN_LAST_ST_STATE(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x3f800)|value<<11) +} +func (o *PMU_Type) GetMAIN_STATE_MAIN_LAST_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x3f800) >> 11 +} +func (o *PMU_Type) SetMAIN_STATE_MAIN_TAR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x1fc0000)|value<<18) +} +func (o *PMU_Type) GetMAIN_STATE_MAIN_TAR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x1fc0000) >> 18 +} +func (o *PMU_Type) SetMAIN_STATE_MAIN_CUR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0xfe000000)|value<<25) +} +func (o *PMU_Type) GetMAIN_STATE_MAIN_CUR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0xfe000000) >> 25 +} + +// PMU.PWR_STATE: need_des +func (o *PMU_Type) SetPWR_STATE_BACKUP_ST_STATE(value uint32) { + volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0x3e000)|value<<13) +} +func (o *PMU_Type) GetPWR_STATE_BACKUP_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0x3e000) >> 13 +} +func (o *PMU_Type) SetPWR_STATE_LP_PWR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0x7c0000)|value<<18) +} +func (o *PMU_Type) GetPWR_STATE_LP_PWR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0x7c0000) >> 18 +} +func (o *PMU_Type) SetPWR_STATE_HP_PWR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0xff800000)|value<<23) +} +func (o *PMU_Type) GetPWR_STATE_HP_PWR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0xff800000) >> 23 +} + +// PMU.CLK_STATE0: need_des +func (o *PMU_Type) SetCLK_STATE0_STABLE_XPD_BBPLL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetCLK_STATE0_STABLE_XPD_BBPLL_STATE() uint32 { + return volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x1 +} +func (o *PMU_Type) SetCLK_STATE0_STABLE_XPD_XTAL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetCLK_STATE0_STABLE_XPD_XTAL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetCLK_STATE0_SYS_CLK_SLP_SEL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetCLK_STATE0_SYS_CLK_SLP_SEL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetCLK_STATE0_SYS_CLK_SEL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetCLK_STATE0_SYS_CLK_SEL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x30000) >> 16 +} +func (o *PMU_Type) SetCLK_STATE0_SYS_CLK_NO_DIV_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetCLK_STATE0_SYS_CLK_NO_DIV_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_SYS_CLK_EN_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_SYS_CLK_EN_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_MODEM_SWITCH_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_MODEM_SWITCH_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_MODEM_CODE_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x600000)|value<<21) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_MODEM_CODE_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x600000) >> 21 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_SLP_SEL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_SLP_SEL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_GLOBAL_XTAL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_GLOBAL_XTAL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_GLOBAL_PLL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_GLOBAL_PLL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_I2C_ISO_EN_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_I2C_ISO_EN_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_I2C_RETENTION_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_I2C_RETENTION_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_XPD_BB_I2C_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_XPD_BB_I2C_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_XPD_BBPLL_I2C_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_XPD_BBPLL_I2C_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_XPD_BBPLL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_XPD_BBPLL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_XPD_XTAL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_XPD_XTAL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x80000000) >> 31 +} + +// PMU.CLK_STATE1: need_des +func (o *PMU_Type) SetCLK_STATE1(value uint32) { + volatile.StoreUint32(&o.CLK_STATE1.Reg, value) +} +func (o *PMU_Type) GetCLK_STATE1() uint32 { + return volatile.LoadUint32(&o.CLK_STATE1.Reg) +} + +// PMU.CLK_STATE2: need_des +func (o *PMU_Type) SetCLK_STATE2(value uint32) { + volatile.StoreUint32(&o.CLK_STATE2.Reg, value) +} +func (o *PMU_Type) GetCLK_STATE2() uint32 { + return volatile.LoadUint32(&o.CLK_STATE2.Reg) +} + +// PMU.VDD_SPI_STATUS: need_des +func (o *PMU_Type) SetVDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV(value uint32) { + volatile.StoreUint32(&o.VDD_SPI_STATUS.Reg, volatile.LoadUint32(&o.VDD_SPI_STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetVDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV() uint32 { + return (volatile.LoadUint32(&o.VDD_SPI_STATUS.Reg) & 0x80000000) >> 31 +} + +// PMU.DATE: need_des +func (o *PMU_Type) SetDATE_PMU_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetDATE_PMU_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *PMU_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Remote Control +type RMT_Type struct { + CH0DATA volatile.Register32 // 0x0 + CH1DATA volatile.Register32 // 0x4 + CH2DATA volatile.Register32 // 0x8 + CH3DATA volatile.Register32 // 0xC + CH0_TX_CONF0 volatile.Register32 // 0x10 + CH1_TX_CONF0 volatile.Register32 // 0x14 + CH2_RX_CONF0 volatile.Register32 // 0x18 + CH2_RX_CONF1 volatile.Register32 // 0x1C + CH3_RX_CONF0 volatile.Register32 // 0x20 + CH3_RX_CONF1 volatile.Register32 // 0x24 + CH0_TX_STATUS volatile.Register32 // 0x28 + CH1_TX_STATUS volatile.Register32 // 0x2C + CH0_RX_STATUS volatile.Register32 // 0x30 + CH1_RX_STATUS volatile.Register32 // 0x34 + INT_RAW volatile.Register32 // 0x38 + INT_ST volatile.Register32 // 0x3C + INT_ENA volatile.Register32 // 0x40 + INT_CLR volatile.Register32 // 0x44 + CH0CARRIER_DUTY volatile.Register32 // 0x48 + CH1CARRIER_DUTY volatile.Register32 // 0x4C + CH0_RX_CARRIER_RM volatile.Register32 // 0x50 + CH1_RX_CARRIER_RM volatile.Register32 // 0x54 + CH0_TX_LIM volatile.Register32 // 0x58 + CH1_TX_LIM volatile.Register32 // 0x5C + CH0_RX_LIM volatile.Register32 // 0x60 + CH1_RX_LIM volatile.Register32 // 0x64 + SYS_CONF volatile.Register32 // 0x68 + TX_SIM volatile.Register32 // 0x6C + REF_CNT_RST volatile.Register32 // 0x70 + _ [88]byte + DATE volatile.Register32 // 0xCC +} + +// RMT.CH0DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH0DATA(value uint32) { + volatile.StoreUint32(&o.CH0DATA.Reg, value) +} +func (o *RMT_Type) GetCH0DATA() uint32 { + return volatile.LoadUint32(&o.CH0DATA.Reg) +} + +// RMT.CH1DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH1DATA(value uint32) { + volatile.StoreUint32(&o.CH1DATA.Reg, value) +} +func (o *RMT_Type) GetCH1DATA() uint32 { + return volatile.LoadUint32(&o.CH1DATA.Reg) +} + +// RMT.CH2DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH2DATA(value uint32) { + volatile.StoreUint32(&o.CH2DATA.Reg, value) +} +func (o *RMT_Type) GetCH2DATA() uint32 { + return volatile.LoadUint32(&o.CH2DATA.Reg) +} + +// RMT.CH3DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH3DATA(value uint32) { + volatile.StoreUint32(&o.CH3DATA.Reg, value) +} +func (o *RMT_Type) GetCH3DATA() uint32 { + return volatile.LoadUint32(&o.CH3DATA.Reg) +} + +// RMT.CH0_TX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH0_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH0_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH0_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH0_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH0_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH0_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH0_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH0_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH0_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH0_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH0_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x70000)|value<<16) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x70000) >> 16 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH0_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH0_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH1_TX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH1_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH1_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH1_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH1_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH1_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH1_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH1_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH1_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH1_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH1_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH1_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x70000)|value<<16) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x70000) >> 16 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH1_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH1_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH2_RX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH2_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH2_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH2_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH2_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH2_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x3800000)|value<<23) +} +func (o *RMT_Type) GetCH2_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x3800000) >> 23 +} +func (o *RMT_Type) SetCH2_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH2_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH2_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH2_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH2_RX_CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH2_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH2_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH2_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH2_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH2_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH2_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH2_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH2_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH2_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH2_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH2_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH2_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH2_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH2_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH2_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH2_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH2_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH2_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH3_RX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH3_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH3_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH3_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH3_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH3_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x3800000)|value<<23) +} +func (o *RMT_Type) GetCH3_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x3800000) >> 23 +} +func (o *RMT_Type) SetCH3_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH3_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH3_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH3_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH3_RX_CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH3_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH3_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH3_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH3_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH3_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH3_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH3_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH3_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH3_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH3_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH3_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH3_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH3_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH3_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH3_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH3_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH3_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH3_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH0_TX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH0_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0xe00)|value<<9) +} +func (o *RMT_Type) GetCH0_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0xe00) >> 9 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH0_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH0_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0xff000000)|value<<24) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0xff000000) >> 24 +} + +// RMT.CH1_TX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH1_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0xe00)|value<<9) +} +func (o *RMT_Type) GetCH1_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0xe00) >> 9 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH1_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH1_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0xff000000)|value<<24) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0xff000000) >> 24 +} + +// RMT.CH0_RX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH0_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH0_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH0_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH0_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH0_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH0_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH0_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH0_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH0_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH0_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH1_RX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH1_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH1_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH1_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH1_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH1_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH1_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH1_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH1_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH1_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH1_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.INT_RAW: Raw interrupt status +func (o *RMT_Type) SetINT_RAW_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} + +// RMT.INT_ST: Masked interrupt status +func (o *RMT_Type) SetINT_ST_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_ST_CH_s_X_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ST_CH_s_X_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} + +// RMT.INT_ENA: Interrupt enable bits +func (o *RMT_Type) SetINT_ENA_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_ENA_CH_s_X_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ENA_CH_s_X_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} + +// RMT.INT_CLR: Interrupt clear bits +func (o *RMT_Type) SetINT_CLR_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} + +// RMT.CH0CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH0_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH1_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH1_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH0_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH0_RX_LIM_RMT_RX_LIM(value uint32) { + volatile.StoreUint32(&o.CH0_RX_LIM.Reg, volatile.LoadUint32(&o.CH0_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_RX_LIM_RMT_RX_LIM() uint32 { + return volatile.LoadUint32(&o.CH0_RX_LIM.Reg) & 0x1ff +} + +// RMT.CH1_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH1_RX_LIM_RMT_RX_LIM(value uint32) { + volatile.StoreUint32(&o.CH1_RX_LIM.Reg, volatile.LoadUint32(&o.CH1_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_RX_LIM_RMT_RX_LIM() uint32 { + return volatile.LoadUint32(&o.CH1_RX_LIM.Reg) & 0x1ff +} + +// RMT.SYS_CONF: RMT apb configuration register +func (o *RMT_Type) SetSYS_CONF_APB_FIFO_MASK(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetSYS_CONF_APB_FIFO_MASK() uint32 { + return volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetSYS_CONF_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xff0)|value<<4) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xff0) >> 4 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3f000)|value<<12) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3f000) >> 12 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xfc0000)|value<<18) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xfc0000) >> 18 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3000000)|value<<24) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3000000) >> 24 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetSYS_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetSYS_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x80000000) >> 31 +} + +// RMT.TX_SIM: RMT TX synchronous register +func (o *RMT_Type) SetTX_SIM_CH0(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_SIM_CH0() uint32 { + return volatile.LoadUint32(&o.TX_SIM.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_SIM_CH1(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_SIM_CH1() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_SIM_EN(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_SIM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x4) >> 2 +} + +// RMT.REF_CNT_RST: RMT clock divider reset register +func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST() uint32 { + return volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x1 +} +func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH1(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH1() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH2(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH2() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH3(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH3() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x8) >> 3 +} + +// RMT.DATE: RMT version register +func (o *RMT_Type) SetDATE_RMT_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RMT_Type) GetDATE_RMT_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Hardware Random Number Generator +type RNG_Type struct { + _ [8]byte + DATA volatile.Register32 // 0x8 +} + +// RSA (Rivest Shamir Adleman) Accelerator +type RSA_Type struct { + M_MEM [384]volatile.Register8 // 0x0 + _ [128]byte + Z_MEM [384]volatile.Register8 // 0x200 + _ [128]byte + Y_MEM [384]volatile.Register8 // 0x400 + _ [128]byte + X_MEM [384]volatile.Register8 // 0x600 + _ [128]byte + M_PRIME volatile.Register32 // 0x800 + MODE volatile.Register32 // 0x804 + QUERY_CLEAN volatile.Register32 // 0x808 + SET_START_MODEXP volatile.Register32 // 0x80C + SET_START_MODMULT volatile.Register32 // 0x810 + SET_START_MULT volatile.Register32 // 0x814 + QUERY_IDLE volatile.Register32 // 0x818 + INT_CLR volatile.Register32 // 0x81C + CONSTANT_TIME volatile.Register32 // 0x820 + SEARCH_ENABLE volatile.Register32 // 0x824 + SEARCH_POS volatile.Register32 // 0x828 + INT_ENA volatile.Register32 // 0x82C + DATE volatile.Register32 // 0x830 +} + +// RSA.M_PRIME: RSA M_prime register +func (o *RSA_Type) SetM_PRIME(value uint32) { + volatile.StoreUint32(&o.M_PRIME.Reg, value) +} +func (o *RSA_Type) GetM_PRIME() uint32 { + return volatile.LoadUint32(&o.M_PRIME.Reg) +} + +// RSA.MODE: RSA mode register +func (o *RSA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7f)|value) +} +func (o *RSA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7f +} + +// RSA.QUERY_CLEAN: RSA query clean register +func (o *RSA_Type) SetQUERY_CLEAN(value uint32) { + volatile.StoreUint32(&o.QUERY_CLEAN.Reg, volatile.LoadUint32(&o.QUERY_CLEAN.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetQUERY_CLEAN() uint32 { + return volatile.LoadUint32(&o.QUERY_CLEAN.Reg) & 0x1 +} + +// RSA.SET_START_MODEXP: RSA modular exponentiation trigger register. +func (o *RSA_Type) SetSET_START_MODEXP(value uint32) { + volatile.StoreUint32(&o.SET_START_MODEXP.Reg, volatile.LoadUint32(&o.SET_START_MODEXP.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MODEXP() uint32 { + return volatile.LoadUint32(&o.SET_START_MODEXP.Reg) & 0x1 +} + +// RSA.SET_START_MODMULT: RSA modular multiplication trigger register. +func (o *RSA_Type) SetSET_START_MODMULT(value uint32) { + volatile.StoreUint32(&o.SET_START_MODMULT.Reg, volatile.LoadUint32(&o.SET_START_MODMULT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MODMULT() uint32 { + return volatile.LoadUint32(&o.SET_START_MODMULT.Reg) & 0x1 +} + +// RSA.SET_START_MULT: RSA normal multiplication trigger register. +func (o *RSA_Type) SetSET_START_MULT(value uint32) { + volatile.StoreUint32(&o.SET_START_MULT.Reg, volatile.LoadUint32(&o.SET_START_MULT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MULT() uint32 { + return volatile.LoadUint32(&o.SET_START_MULT.Reg) & 0x1 +} + +// RSA.QUERY_IDLE: RSA query idle register +func (o *RSA_Type) SetQUERY_IDLE(value uint32) { + volatile.StoreUint32(&o.QUERY_IDLE.Reg, volatile.LoadUint32(&o.QUERY_IDLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetQUERY_IDLE() uint32 { + return volatile.LoadUint32(&o.QUERY_IDLE.Reg) & 0x1 +} + +// RSA.INT_CLR: RSA interrupt clear register +func (o *RSA_Type) SetINT_CLR_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINT_CLR_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} + +// RSA.CONSTANT_TIME: RSA constant time option register +func (o *RSA_Type) SetCONSTANT_TIME(value uint32) { + volatile.StoreUint32(&o.CONSTANT_TIME.Reg, volatile.LoadUint32(&o.CONSTANT_TIME.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCONSTANT_TIME() uint32 { + return volatile.LoadUint32(&o.CONSTANT_TIME.Reg) & 0x1 +} + +// RSA.SEARCH_ENABLE: RSA search option +func (o *RSA_Type) SetSEARCH_ENABLE(value uint32) { + volatile.StoreUint32(&o.SEARCH_ENABLE.Reg, volatile.LoadUint32(&o.SEARCH_ENABLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSEARCH_ENABLE() uint32 { + return volatile.LoadUint32(&o.SEARCH_ENABLE.Reg) & 0x1 +} + +// RSA.SEARCH_POS: RSA search position configure register +func (o *RSA_Type) SetSEARCH_POS(value uint32) { + volatile.StoreUint32(&o.SEARCH_POS.Reg, volatile.LoadUint32(&o.SEARCH_POS.Reg)&^(0xfff)|value) +} +func (o *RSA_Type) GetSEARCH_POS() uint32 { + return volatile.LoadUint32(&o.SEARCH_POS.Reg) & 0xfff +} + +// RSA.INT_ENA: RSA interrupt enable register +func (o *RSA_Type) SetINT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// RSA.DATE: RSA version control register +func (o *RSA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *RSA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// SHA (Secure Hash Algorithm) Accelerator +type SHA_Type struct { + MODE volatile.Register32 // 0x0 + T_STRING volatile.Register32 // 0x4 + T_LENGTH volatile.Register32 // 0x8 + DMA_BLOCK_NUM volatile.Register32 // 0xC + START volatile.Register32 // 0x10 + CONTINUE volatile.Register32 // 0x14 + BUSY volatile.Register32 // 0x18 + DMA_START volatile.Register32 // 0x1C + DMA_CONTINUE volatile.Register32 // 0x20 + CLEAR_IRQ volatile.Register32 // 0x24 + IRQ_ENA volatile.Register32 // 0x28 + DATE volatile.Register32 // 0x2C + _ [16]byte + H_MEM [64]volatile.Register8 // 0x40 + M_MEM [64]volatile.Register8 // 0x80 +} + +// SHA.MODE: Initial configuration register. +func (o *SHA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *SHA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// SHA.T_STRING: SHA 512/t configuration register 0. +func (o *SHA_Type) SetT_STRING(value uint32) { + volatile.StoreUint32(&o.T_STRING.Reg, value) +} +func (o *SHA_Type) GetT_STRING() uint32 { + return volatile.LoadUint32(&o.T_STRING.Reg) +} + +// SHA.T_LENGTH: SHA 512/t configuration register 1. +func (o *SHA_Type) SetT_LENGTH(value uint32) { + volatile.StoreUint32(&o.T_LENGTH.Reg, volatile.LoadUint32(&o.T_LENGTH.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetT_LENGTH() uint32 { + return volatile.LoadUint32(&o.T_LENGTH.Reg) & 0x3f +} + +// SHA.DMA_BLOCK_NUM: DMA configuration register 0. +func (o *SHA_Type) SetDMA_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_NUM.Reg, volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetDMA_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg) & 0x3f +} + +// SHA.START: Typical SHA configuration register 0. +func (o *SHA_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetSTART() uint32 { + return (volatile.LoadUint32(&o.START.Reg) & 0xfffffffe) >> 1 +} + +// SHA.CONTINUE: Typical SHA configuration register 1. +func (o *SHA_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetCONTINUE() uint32 { + return (volatile.LoadUint32(&o.CONTINUE.Reg) & 0xfffffffe) >> 1 +} + +// SHA.BUSY: Busy register. +func (o *SHA_Type) SetBUSY_STATE(value uint32) { + volatile.StoreUint32(&o.BUSY.Reg, volatile.LoadUint32(&o.BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetBUSY_STATE() uint32 { + return volatile.LoadUint32(&o.BUSY.Reg) & 0x1 +} + +// SHA.DMA_START: DMA configuration register 1. +func (o *SHA_Type) SetDMA_START(value uint32) { + volatile.StoreUint32(&o.DMA_START.Reg, volatile.LoadUint32(&o.DMA_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_START() uint32 { + return volatile.LoadUint32(&o.DMA_START.Reg) & 0x1 +} + +// SHA.DMA_CONTINUE: DMA configuration register 2. +func (o *SHA_Type) SetDMA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.DMA_CONTINUE.Reg, volatile.LoadUint32(&o.DMA_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_CONTINUE() uint32 { + return volatile.LoadUint32(&o.DMA_CONTINUE.Reg) & 0x1 +} + +// SHA.CLEAR_IRQ: Interrupt clear register. +func (o *SHA_Type) SetCLEAR_IRQ_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CLEAR_IRQ.Reg, volatile.LoadUint32(&o.CLEAR_IRQ.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetCLEAR_IRQ_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.CLEAR_IRQ.Reg) & 0x1 +} + +// SHA.IRQ_ENA: Interrupt enable register. +func (o *SHA_Type) SetIRQ_ENA_INTERRUPT_ENA(value uint32) { + volatile.StoreUint32(&o.IRQ_ENA.Reg, volatile.LoadUint32(&o.IRQ_ENA.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetIRQ_ENA_INTERRUPT_ENA() uint32 { + return volatile.LoadUint32(&o.IRQ_ENA.Reg) & 0x1 +} + +// SHA.DATE: Date register. +func (o *SHA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SHA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// SLCHOST Peripheral +type SLCHOST_Type struct { + _ [16]byte + FUNC2_0 volatile.Register32 // 0x10 + FUNC2_1 volatile.Register32 // 0x14 + _ [8]byte + FUNC2_2 volatile.Register32 // 0x20 + _ [16]byte + GPIO_STATUS0 volatile.Register32 // 0x34 + GPIO_STATUS1 volatile.Register32 // 0x38 + GPIO_IN0 volatile.Register32 // 0x3C + GPIO_IN1 volatile.Register32 // 0x40 + SLC0HOST_TOKEN_RDATA volatile.Register32 // 0x44 + SLC0_HOST_PF volatile.Register32 // 0x48 + SLC1_HOST_PF volatile.Register32 // 0x4C + SLC0HOST_INT_RAW volatile.Register32 // 0x50 + SLC1HOST_INT_RAW volatile.Register32 // 0x54 + SLC0HOST_INT_ST volatile.Register32 // 0x58 + SLC1HOST_INT_ST volatile.Register32 // 0x5C + PKT_LEN volatile.Register32 // 0x60 + STATE_W0 volatile.Register32 // 0x64 + STATE_W1 volatile.Register32 // 0x68 + CONF_W0 volatile.Register32 // 0x6C + CONF_W1 volatile.Register32 // 0x70 + CONF_W2 volatile.Register32 // 0x74 + CONF_W3 volatile.Register32 // 0x78 + CONF_W4 volatile.Register32 // 0x7C + CONF_W5 volatile.Register32 // 0x80 + WIN_CMD volatile.Register32 // 0x84 + CONF_W6 volatile.Register32 // 0x88 + CONF_W7 volatile.Register32 // 0x8C + PKT_LEN0 volatile.Register32 // 0x90 + PKT_LEN1 volatile.Register32 // 0x94 + PKT_LEN2 volatile.Register32 // 0x98 + CONF_W8 volatile.Register32 // 0x9C + CONF_W9 volatile.Register32 // 0xA0 + CONF_W10 volatile.Register32 // 0xA4 + CONF_W11 volatile.Register32 // 0xA8 + CONF_W12 volatile.Register32 // 0xAC + CONF_W13 volatile.Register32 // 0xB0 + CONF_W14 volatile.Register32 // 0xB4 + CONF_W15 volatile.Register32 // 0xB8 + CHECK_SUM0 volatile.Register32 // 0xBC + CHECK_SUM1 volatile.Register32 // 0xC0 + SLC1HOST_TOKEN_RDATA volatile.Register32 // 0xC4 + SLC0HOST_TOKEN_WDATA volatile.Register32 // 0xC8 + SLC1HOST_TOKEN_WDATA volatile.Register32 // 0xCC + TOKEN_CON volatile.Register32 // 0xD0 + SLC0HOST_INT_CLR volatile.Register32 // 0xD4 + SLC1HOST_INT_CLR volatile.Register32 // 0xD8 + SLC0HOST_FUNC1_INT_ENA volatile.Register32 // 0xDC + SLC1HOST_FUNC1_INT_ENA volatile.Register32 // 0xE0 + SLC0HOST_FUNC2_INT_ENA volatile.Register32 // 0xE4 + SLC1HOST_FUNC2_INT_ENA volatile.Register32 // 0xE8 + SLC0HOST_INT_ENA volatile.Register32 // 0xEC + SLC1HOST_INT_ENA volatile.Register32 // 0xF0 + SLC0HOST_RX_INFOR volatile.Register32 // 0xF4 + SLC1HOST_RX_INFOR volatile.Register32 // 0xF8 + SLC0HOST_LEN_WD volatile.Register32 // 0xFC + SLC_APBWIN_WDATA volatile.Register32 // 0x100 + SLC_APBWIN_CONF volatile.Register32 // 0x104 + SLC_APBWIN_RDATA volatile.Register32 // 0x108 + RDCLR0 volatile.Register32 // 0x10C + RDCLR1 volatile.Register32 // 0x110 + SLC0HOST_INT_ENA1 volatile.Register32 // 0x114 + SLC1HOST_INT_ENA1 volatile.Register32 // 0x118 + _ [92]byte + SLCHOSTDATE volatile.Register32 // 0x178 + SLCHOSTID volatile.Register32 // 0x17C + _ [112]byte + CONF volatile.Register32 // 0x1F0 + INF_ST volatile.Register32 // 0x1F4 +} + +// SLCHOST.FUNC2_0: *******Description*********** +func (o *SLCHOST_Type) SetFUNC2_0_SLC_FUNC2_INT(value uint32) { + volatile.StoreUint32(&o.FUNC2_0.Reg, volatile.LoadUint32(&o.FUNC2_0.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetFUNC2_0_SLC_FUNC2_INT() uint32 { + return (volatile.LoadUint32(&o.FUNC2_0.Reg) & 0x1000000) >> 24 +} + +// SLCHOST.FUNC2_1: *******Description*********** +func (o *SLCHOST_Type) SetFUNC2_1_SLC_FUNC2_INT_EN(value uint32) { + volatile.StoreUint32(&o.FUNC2_1.Reg, volatile.LoadUint32(&o.FUNC2_1.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetFUNC2_1_SLC_FUNC2_INT_EN() uint32 { + return volatile.LoadUint32(&o.FUNC2_1.Reg) & 0x1 +} + +// SLCHOST.FUNC2_2: *******Description*********** +func (o *SLCHOST_Type) SetFUNC2_2_SLC_FUNC1_MDSTAT(value uint32) { + volatile.StoreUint32(&o.FUNC2_2.Reg, volatile.LoadUint32(&o.FUNC2_2.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetFUNC2_2_SLC_FUNC1_MDSTAT() uint32 { + return volatile.LoadUint32(&o.FUNC2_2.Reg) & 0x1 +} + +// SLCHOST.GPIO_STATUS0: *******Description*********** +func (o *SLCHOST_Type) SetGPIO_STATUS0(value uint32) { + volatile.StoreUint32(&o.GPIO_STATUS0.Reg, value) +} +func (o *SLCHOST_Type) GetGPIO_STATUS0() uint32 { + return volatile.LoadUint32(&o.GPIO_STATUS0.Reg) +} + +// SLCHOST.GPIO_STATUS1: *******Description*********** +func (o *SLCHOST_Type) SetGPIO_STATUS1(value uint32) { + volatile.StoreUint32(&o.GPIO_STATUS1.Reg, value) +} +func (o *SLCHOST_Type) GetGPIO_STATUS1() uint32 { + return volatile.LoadUint32(&o.GPIO_STATUS1.Reg) +} + +// SLCHOST.GPIO_IN0: *******Description*********** +func (o *SLCHOST_Type) SetGPIO_IN0(value uint32) { + volatile.StoreUint32(&o.GPIO_IN0.Reg, value) +} +func (o *SLCHOST_Type) GetGPIO_IN0() uint32 { + return volatile.LoadUint32(&o.GPIO_IN0.Reg) +} + +// SLCHOST.GPIO_IN1: *******Description*********** +func (o *SLCHOST_Type) SetGPIO_IN1(value uint32) { + volatile.StoreUint32(&o.GPIO_IN1.Reg, value) +} +func (o *SLCHOST_Type) GetGPIO_IN1() uint32 { + return volatile.LoadUint32(&o.GPIO_IN1.Reg) +} + +// SLCHOST.SLC0HOST_TOKEN_RDATA: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_TOKEN_RDATA_SLC0_TOKEN0(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.SLC0HOST_TOKEN_RDATA.Reg)&^(0xfff)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_TOKEN_RDATA_SLC0_TOKEN0() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_TOKEN_RDATA.Reg) & 0xfff +} +func (o *SLCHOST_Type) SetSLC0HOST_TOKEN_RDATA_SLC0_RX_PF_VALID(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.SLC0HOST_TOKEN_RDATA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC0HOST_TOKEN_RDATA_SLC0_RX_PF_VALID() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_TOKEN_RDATA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC0HOST_TOKEN_RDATA_HOSTSLCHOST_SLC0_TOKEN1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.SLC0HOST_TOKEN_RDATA.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC0HOST_TOKEN_RDATA_HOSTSLCHOST_SLC0_TOKEN1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_TOKEN_RDATA.Reg) & 0xfff0000) >> 16 +} +func (o *SLCHOST_Type) SetSLC0HOST_TOKEN_RDATA_SLC0_RX_PF_EOF(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.SLC0HOST_TOKEN_RDATA.Reg)&^(0xf0000000)|value<<28) +} +func (o *SLCHOST_Type) GetSLC0HOST_TOKEN_RDATA_SLC0_RX_PF_EOF() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_TOKEN_RDATA.Reg) & 0xf0000000) >> 28 +} + +// SLCHOST.SLC0_HOST_PF: *******Description*********** +func (o *SLCHOST_Type) SetSLC0_HOST_PF(value uint32) { + volatile.StoreUint32(&o.SLC0_HOST_PF.Reg, value) +} +func (o *SLCHOST_Type) GetSLC0_HOST_PF() uint32 { + return volatile.LoadUint32(&o.SLC0_HOST_PF.Reg) +} + +// SLCHOST.SLC1_HOST_PF: *******Description*********** +func (o *SLCHOST_Type) SetSLC1_HOST_PF(value uint32) { + volatile.StoreUint32(&o.SLC1_HOST_PF.Reg, value) +} +func (o *SLCHOST_Type) GetSLC1_HOST_PF() uint32 { + return volatile.LoadUint32(&o.SLC1_HOST_PF.Reg) +} + +// SLCHOST.SLC0HOST_INT_RAW: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOHOST_BIT7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOKEN0_0TO1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOKEN0_0TO1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TOKEN1_0TO1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TOKEN1_0TO1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0HOST_RX_SOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0HOST_RX_SOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0HOST_RX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0HOST_RX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0HOST_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0HOST_RX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0HOST_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0HOST_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_RX_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_RX_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_TX_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_TX_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_RX_PF_VALID_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_RX_PF_VALID_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_EXT_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_EXT_BIT0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_EXT_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_EXT_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_EXT_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_EXT_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_EXT_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_EXT_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_RX_NEW_PACKET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_RX_NEW_PACKET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_SLC0_HOST_RD_RETRY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_SLC0_HOST_RD_RETRY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_RAW_GPIO_SDIO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_RAW_GPIO_SDIO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_RAW.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC1HOST_INT_RAW: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOHOST_BIT7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOKEN0_0TO1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOKEN0_0TO1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TOKEN1_0TO1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TOKEN1_0TO1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1HOST_RX_SOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1HOST_RX_SOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1HOST_RX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1HOST_RX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1HOST_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1HOST_RX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1HOST_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1HOST_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_RX_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_RX_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_TX_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_TX_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_RX_PF_VALID_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_RX_PF_VALID_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_EXT_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_EXT_BIT0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_EXT_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_EXT_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_EXT_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_EXT_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_EXT_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_EXT_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_WIFI_RX_NEW_PACKET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_WIFI_RX_NEW_PACKET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_HOST_RD_RETRY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_HOST_RD_RETRY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_RAW_SLC1_BT_RX_NEW_PACKET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_RAW.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_RAW_SLC1_BT_RX_NEW_PACKET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_RAW.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC0HOST_INT_ST: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOHOST_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOHOST_BIT0_INT_ST() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOHOST_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOHOST_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOHOST_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOHOST_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOHOST_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOHOST_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOHOST_BIT4_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOHOST_BIT4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOHOST_BIT5_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOHOST_BIT5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOHOST_BIT6_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOHOST_BIT6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOHOST_BIT7_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOHOST_BIT7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOKEN0_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOKEN0_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOKEN1_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOKEN1_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOKEN0_0TO1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOKEN0_0TO1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TOKEN1_0TO1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TOKEN1_0TO1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0HOST_RX_SOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0HOST_RX_SOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0HOST_RX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0HOST_RX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0HOST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0HOST_RX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0HOST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0HOST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_RX_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_RX_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_TX_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_TX_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_RX_PF_VALID_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_RX_PF_VALID_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_EXT_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_EXT_BIT0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_EXT_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_EXT_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_EXT_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_EXT_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_EXT_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_EXT_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_RX_NEW_PACKET_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_RX_NEW_PACKET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_SLC0_HOST_RD_RETRY_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_SLC0_HOST_RD_RETRY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ST_GPIO_SDIO_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ST_GPIO_SDIO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ST.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC1HOST_INT_ST: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOHOST_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOHOST_BIT0_INT_ST() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOHOST_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOHOST_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOHOST_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOHOST_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOHOST_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOHOST_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOHOST_BIT4_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOHOST_BIT4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOHOST_BIT5_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOHOST_BIT5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOHOST_BIT6_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOHOST_BIT6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOHOST_BIT7_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOHOST_BIT7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOKEN0_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOKEN0_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOKEN1_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOKEN1_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOKEN0_0TO1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOKEN0_0TO1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TOKEN1_0TO1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TOKEN1_0TO1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1HOST_RX_SOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1HOST_RX_SOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1HOST_RX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1HOST_RX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1HOST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1HOST_RX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1HOST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1HOST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_RX_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_RX_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_TX_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_TX_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_RX_PF_VALID_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_RX_PF_VALID_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_EXT_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_EXT_BIT0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_EXT_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_EXT_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_EXT_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_EXT_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_EXT_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_EXT_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_WIFI_RX_NEW_PACKET_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_WIFI_RX_NEW_PACKET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_HOST_RD_RETRY_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_HOST_RD_RETRY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ST_SLC1_BT_RX_NEW_PACKET_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ST.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ST_SLC1_BT_RX_NEW_PACKET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ST.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.PKT_LEN: *******Description*********** +func (o *SLCHOST_Type) SetPKT_LEN_HOSTSLCHOST_SLC0_LEN(value uint32) { + volatile.StoreUint32(&o.PKT_LEN.Reg, volatile.LoadUint32(&o.PKT_LEN.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetPKT_LEN_HOSTSLCHOST_SLC0_LEN() uint32 { + return volatile.LoadUint32(&o.PKT_LEN.Reg) & 0xfffff +} +func (o *SLCHOST_Type) SetPKT_LEN_HOSTSLCHOST_SLC0_LEN_CHECK(value uint32) { + volatile.StoreUint32(&o.PKT_LEN.Reg, volatile.LoadUint32(&o.PKT_LEN.Reg)&^(0xfff00000)|value<<20) +} +func (o *SLCHOST_Type) GetPKT_LEN_HOSTSLCHOST_SLC0_LEN_CHECK() uint32 { + return (volatile.LoadUint32(&o.PKT_LEN.Reg) & 0xfff00000) >> 20 +} + +// SLCHOST.STATE_W0: *******Description*********** +func (o *SLCHOST_Type) SetSTATE_W0_SLCHOST_STATE0(value uint32) { + volatile.StoreUint32(&o.STATE_W0.Reg, volatile.LoadUint32(&o.STATE_W0.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetSTATE_W0_SLCHOST_STATE0() uint32 { + return volatile.LoadUint32(&o.STATE_W0.Reg) & 0xff +} +func (o *SLCHOST_Type) SetSTATE_W0_SLCHOST_STATE1(value uint32) { + volatile.StoreUint32(&o.STATE_W0.Reg, volatile.LoadUint32(&o.STATE_W0.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetSTATE_W0_SLCHOST_STATE1() uint32 { + return (volatile.LoadUint32(&o.STATE_W0.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetSTATE_W0_SLCHOST_STATE2(value uint32) { + volatile.StoreUint32(&o.STATE_W0.Reg, volatile.LoadUint32(&o.STATE_W0.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetSTATE_W0_SLCHOST_STATE2() uint32 { + return (volatile.LoadUint32(&o.STATE_W0.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetSTATE_W0_SLCHOST_STATE3(value uint32) { + volatile.StoreUint32(&o.STATE_W0.Reg, volatile.LoadUint32(&o.STATE_W0.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetSTATE_W0_SLCHOST_STATE3() uint32 { + return (volatile.LoadUint32(&o.STATE_W0.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.STATE_W1: *******Description*********** +func (o *SLCHOST_Type) SetSTATE_W1_SLCHOST_STATE4(value uint32) { + volatile.StoreUint32(&o.STATE_W1.Reg, volatile.LoadUint32(&o.STATE_W1.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetSTATE_W1_SLCHOST_STATE4() uint32 { + return volatile.LoadUint32(&o.STATE_W1.Reg) & 0xff +} +func (o *SLCHOST_Type) SetSTATE_W1_SLCHOST_STATE5(value uint32) { + volatile.StoreUint32(&o.STATE_W1.Reg, volatile.LoadUint32(&o.STATE_W1.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetSTATE_W1_SLCHOST_STATE5() uint32 { + return (volatile.LoadUint32(&o.STATE_W1.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetSTATE_W1_SLCHOST_STATE6(value uint32) { + volatile.StoreUint32(&o.STATE_W1.Reg, volatile.LoadUint32(&o.STATE_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetSTATE_W1_SLCHOST_STATE6() uint32 { + return (volatile.LoadUint32(&o.STATE_W1.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetSTATE_W1_SLCHOST_STATE7(value uint32) { + volatile.StoreUint32(&o.STATE_W1.Reg, volatile.LoadUint32(&o.STATE_W1.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetSTATE_W1_SLCHOST_STATE7() uint32 { + return (volatile.LoadUint32(&o.STATE_W1.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W0: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W0_SLCHOST_CONF0(value uint32) { + volatile.StoreUint32(&o.CONF_W0.Reg, volatile.LoadUint32(&o.CONF_W0.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W0_SLCHOST_CONF0() uint32 { + return volatile.LoadUint32(&o.CONF_W0.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W0_SLCHOST_CONF1(value uint32) { + volatile.StoreUint32(&o.CONF_W0.Reg, volatile.LoadUint32(&o.CONF_W0.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W0_SLCHOST_CONF1() uint32 { + return (volatile.LoadUint32(&o.CONF_W0.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W0_SLCHOST_CONF2(value uint32) { + volatile.StoreUint32(&o.CONF_W0.Reg, volatile.LoadUint32(&o.CONF_W0.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W0_SLCHOST_CONF2() uint32 { + return (volatile.LoadUint32(&o.CONF_W0.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W0_SLCHOST_CONF3(value uint32) { + volatile.StoreUint32(&o.CONF_W0.Reg, volatile.LoadUint32(&o.CONF_W0.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W0_SLCHOST_CONF3() uint32 { + return (volatile.LoadUint32(&o.CONF_W0.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W1: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W1_SLCHOST_CONF4(value uint32) { + volatile.StoreUint32(&o.CONF_W1.Reg, volatile.LoadUint32(&o.CONF_W1.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W1_SLCHOST_CONF4() uint32 { + return volatile.LoadUint32(&o.CONF_W1.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W1_SLCHOST_CONF5(value uint32) { + volatile.StoreUint32(&o.CONF_W1.Reg, volatile.LoadUint32(&o.CONF_W1.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W1_SLCHOST_CONF5() uint32 { + return (volatile.LoadUint32(&o.CONF_W1.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W1_SLCHOST_CONF6(value uint32) { + volatile.StoreUint32(&o.CONF_W1.Reg, volatile.LoadUint32(&o.CONF_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W1_SLCHOST_CONF6() uint32 { + return (volatile.LoadUint32(&o.CONF_W1.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W1_SLCHOST_CONF7(value uint32) { + volatile.StoreUint32(&o.CONF_W1.Reg, volatile.LoadUint32(&o.CONF_W1.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W1_SLCHOST_CONF7() uint32 { + return (volatile.LoadUint32(&o.CONF_W1.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W2: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W2_SLCHOST_CONF8(value uint32) { + volatile.StoreUint32(&o.CONF_W2.Reg, volatile.LoadUint32(&o.CONF_W2.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W2_SLCHOST_CONF8() uint32 { + return volatile.LoadUint32(&o.CONF_W2.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W2_SLCHOST_CONF9(value uint32) { + volatile.StoreUint32(&o.CONF_W2.Reg, volatile.LoadUint32(&o.CONF_W2.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W2_SLCHOST_CONF9() uint32 { + return (volatile.LoadUint32(&o.CONF_W2.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W2_SLCHOST_CONF10(value uint32) { + volatile.StoreUint32(&o.CONF_W2.Reg, volatile.LoadUint32(&o.CONF_W2.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W2_SLCHOST_CONF10() uint32 { + return (volatile.LoadUint32(&o.CONF_W2.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W2_SLCHOST_CONF11(value uint32) { + volatile.StoreUint32(&o.CONF_W2.Reg, volatile.LoadUint32(&o.CONF_W2.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W2_SLCHOST_CONF11() uint32 { + return (volatile.LoadUint32(&o.CONF_W2.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W3: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W3_SLCHOST_CONF12(value uint32) { + volatile.StoreUint32(&o.CONF_W3.Reg, volatile.LoadUint32(&o.CONF_W3.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W3_SLCHOST_CONF12() uint32 { + return volatile.LoadUint32(&o.CONF_W3.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W3_SLCHOST_CONF13(value uint32) { + volatile.StoreUint32(&o.CONF_W3.Reg, volatile.LoadUint32(&o.CONF_W3.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W3_SLCHOST_CONF13() uint32 { + return (volatile.LoadUint32(&o.CONF_W3.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W3_SLCHOST_CONF14(value uint32) { + volatile.StoreUint32(&o.CONF_W3.Reg, volatile.LoadUint32(&o.CONF_W3.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W3_SLCHOST_CONF14() uint32 { + return (volatile.LoadUint32(&o.CONF_W3.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W3_SLCHOST_CONF15(value uint32) { + volatile.StoreUint32(&o.CONF_W3.Reg, volatile.LoadUint32(&o.CONF_W3.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W3_SLCHOST_CONF15() uint32 { + return (volatile.LoadUint32(&o.CONF_W3.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W4: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W4_SLCHOST_CONF16(value uint32) { + volatile.StoreUint32(&o.CONF_W4.Reg, volatile.LoadUint32(&o.CONF_W4.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W4_SLCHOST_CONF16() uint32 { + return volatile.LoadUint32(&o.CONF_W4.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W4_SLCHOST_CONF17(value uint32) { + volatile.StoreUint32(&o.CONF_W4.Reg, volatile.LoadUint32(&o.CONF_W4.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W4_SLCHOST_CONF17() uint32 { + return (volatile.LoadUint32(&o.CONF_W4.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W4_SLCHOST_CONF18(value uint32) { + volatile.StoreUint32(&o.CONF_W4.Reg, volatile.LoadUint32(&o.CONF_W4.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W4_SLCHOST_CONF18() uint32 { + return (volatile.LoadUint32(&o.CONF_W4.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W4_SLCHOST_CONF19(value uint32) { + volatile.StoreUint32(&o.CONF_W4.Reg, volatile.LoadUint32(&o.CONF_W4.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W4_SLCHOST_CONF19() uint32 { + return (volatile.LoadUint32(&o.CONF_W4.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W5: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W5_SLCHOST_CONF20(value uint32) { + volatile.StoreUint32(&o.CONF_W5.Reg, volatile.LoadUint32(&o.CONF_W5.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W5_SLCHOST_CONF20() uint32 { + return volatile.LoadUint32(&o.CONF_W5.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W5_SLCHOST_CONF21(value uint32) { + volatile.StoreUint32(&o.CONF_W5.Reg, volatile.LoadUint32(&o.CONF_W5.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W5_SLCHOST_CONF21() uint32 { + return (volatile.LoadUint32(&o.CONF_W5.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W5_SLCHOST_CONF22(value uint32) { + volatile.StoreUint32(&o.CONF_W5.Reg, volatile.LoadUint32(&o.CONF_W5.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W5_SLCHOST_CONF22() uint32 { + return (volatile.LoadUint32(&o.CONF_W5.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W5_SLCHOST_CONF23(value uint32) { + volatile.StoreUint32(&o.CONF_W5.Reg, volatile.LoadUint32(&o.CONF_W5.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W5_SLCHOST_CONF23() uint32 { + return (volatile.LoadUint32(&o.CONF_W5.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.WIN_CMD: *******Description*********** +func (o *SLCHOST_Type) SetWIN_CMD_SLCHOST_WIN_CMD(value uint32) { + volatile.StoreUint32(&o.WIN_CMD.Reg, volatile.LoadUint32(&o.WIN_CMD.Reg)&^(0xffff)|value) +} +func (o *SLCHOST_Type) GetWIN_CMD_SLCHOST_WIN_CMD() uint32 { + return volatile.LoadUint32(&o.WIN_CMD.Reg) & 0xffff +} + +// SLCHOST.CONF_W6: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W6_SLCHOST_CONF24(value uint32) { + volatile.StoreUint32(&o.CONF_W6.Reg, volatile.LoadUint32(&o.CONF_W6.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W6_SLCHOST_CONF24() uint32 { + return volatile.LoadUint32(&o.CONF_W6.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W6_SLCHOST_CONF25(value uint32) { + volatile.StoreUint32(&o.CONF_W6.Reg, volatile.LoadUint32(&o.CONF_W6.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W6_SLCHOST_CONF25() uint32 { + return (volatile.LoadUint32(&o.CONF_W6.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W6_SLCHOST_CONF26(value uint32) { + volatile.StoreUint32(&o.CONF_W6.Reg, volatile.LoadUint32(&o.CONF_W6.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W6_SLCHOST_CONF26() uint32 { + return (volatile.LoadUint32(&o.CONF_W6.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W6_SLCHOST_CONF27(value uint32) { + volatile.StoreUint32(&o.CONF_W6.Reg, volatile.LoadUint32(&o.CONF_W6.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W6_SLCHOST_CONF27() uint32 { + return (volatile.LoadUint32(&o.CONF_W6.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W7: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W7_SLCHOST_CONF28(value uint32) { + volatile.StoreUint32(&o.CONF_W7.Reg, volatile.LoadUint32(&o.CONF_W7.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W7_SLCHOST_CONF28() uint32 { + return volatile.LoadUint32(&o.CONF_W7.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W7_SLCHOST_CONF29(value uint32) { + volatile.StoreUint32(&o.CONF_W7.Reg, volatile.LoadUint32(&o.CONF_W7.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W7_SLCHOST_CONF29() uint32 { + return (volatile.LoadUint32(&o.CONF_W7.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W7_SLCHOST_CONF30(value uint32) { + volatile.StoreUint32(&o.CONF_W7.Reg, volatile.LoadUint32(&o.CONF_W7.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W7_SLCHOST_CONF30() uint32 { + return (volatile.LoadUint32(&o.CONF_W7.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W7_SLCHOST_CONF31(value uint32) { + volatile.StoreUint32(&o.CONF_W7.Reg, volatile.LoadUint32(&o.CONF_W7.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W7_SLCHOST_CONF31() uint32 { + return (volatile.LoadUint32(&o.CONF_W7.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.PKT_LEN0: *******Description*********** +func (o *SLCHOST_Type) SetPKT_LEN0_HOSTSLCHOST_SLC0_LEN0(value uint32) { + volatile.StoreUint32(&o.PKT_LEN0.Reg, volatile.LoadUint32(&o.PKT_LEN0.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetPKT_LEN0_HOSTSLCHOST_SLC0_LEN0() uint32 { + return volatile.LoadUint32(&o.PKT_LEN0.Reg) & 0xfffff +} +func (o *SLCHOST_Type) SetPKT_LEN0_HOSTSLCHOST_SLC0_LEN0_CHECK(value uint32) { + volatile.StoreUint32(&o.PKT_LEN0.Reg, volatile.LoadUint32(&o.PKT_LEN0.Reg)&^(0xfff00000)|value<<20) +} +func (o *SLCHOST_Type) GetPKT_LEN0_HOSTSLCHOST_SLC0_LEN0_CHECK() uint32 { + return (volatile.LoadUint32(&o.PKT_LEN0.Reg) & 0xfff00000) >> 20 +} + +// SLCHOST.PKT_LEN1: *******Description*********** +func (o *SLCHOST_Type) SetPKT_LEN1_HOSTSLCHOST_SLC0_LEN1(value uint32) { + volatile.StoreUint32(&o.PKT_LEN1.Reg, volatile.LoadUint32(&o.PKT_LEN1.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetPKT_LEN1_HOSTSLCHOST_SLC0_LEN1() uint32 { + return volatile.LoadUint32(&o.PKT_LEN1.Reg) & 0xfffff +} +func (o *SLCHOST_Type) SetPKT_LEN1_HOSTSLCHOST_SLC0_LEN1_CHECK(value uint32) { + volatile.StoreUint32(&o.PKT_LEN1.Reg, volatile.LoadUint32(&o.PKT_LEN1.Reg)&^(0xfff00000)|value<<20) +} +func (o *SLCHOST_Type) GetPKT_LEN1_HOSTSLCHOST_SLC0_LEN1_CHECK() uint32 { + return (volatile.LoadUint32(&o.PKT_LEN1.Reg) & 0xfff00000) >> 20 +} + +// SLCHOST.PKT_LEN2: *******Description*********** +func (o *SLCHOST_Type) SetPKT_LEN2_HOSTSLCHOST_SLC0_LEN2(value uint32) { + volatile.StoreUint32(&o.PKT_LEN2.Reg, volatile.LoadUint32(&o.PKT_LEN2.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetPKT_LEN2_HOSTSLCHOST_SLC0_LEN2() uint32 { + return volatile.LoadUint32(&o.PKT_LEN2.Reg) & 0xfffff +} +func (o *SLCHOST_Type) SetPKT_LEN2_HOSTSLCHOST_SLC0_LEN2_CHECK(value uint32) { + volatile.StoreUint32(&o.PKT_LEN2.Reg, volatile.LoadUint32(&o.PKT_LEN2.Reg)&^(0xfff00000)|value<<20) +} +func (o *SLCHOST_Type) GetPKT_LEN2_HOSTSLCHOST_SLC0_LEN2_CHECK() uint32 { + return (volatile.LoadUint32(&o.PKT_LEN2.Reg) & 0xfff00000) >> 20 +} + +// SLCHOST.CONF_W8: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W8_SLCHOST_CONF32(value uint32) { + volatile.StoreUint32(&o.CONF_W8.Reg, volatile.LoadUint32(&o.CONF_W8.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W8_SLCHOST_CONF32() uint32 { + return volatile.LoadUint32(&o.CONF_W8.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W8_SLCHOST_CONF33(value uint32) { + volatile.StoreUint32(&o.CONF_W8.Reg, volatile.LoadUint32(&o.CONF_W8.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W8_SLCHOST_CONF33() uint32 { + return (volatile.LoadUint32(&o.CONF_W8.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W8_SLCHOST_CONF34(value uint32) { + volatile.StoreUint32(&o.CONF_W8.Reg, volatile.LoadUint32(&o.CONF_W8.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W8_SLCHOST_CONF34() uint32 { + return (volatile.LoadUint32(&o.CONF_W8.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W8_SLCHOST_CONF35(value uint32) { + volatile.StoreUint32(&o.CONF_W8.Reg, volatile.LoadUint32(&o.CONF_W8.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W8_SLCHOST_CONF35() uint32 { + return (volatile.LoadUint32(&o.CONF_W8.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W9: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W9_SLCHOST_CONF36(value uint32) { + volatile.StoreUint32(&o.CONF_W9.Reg, volatile.LoadUint32(&o.CONF_W9.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W9_SLCHOST_CONF36() uint32 { + return volatile.LoadUint32(&o.CONF_W9.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W9_SLCHOST_CONF37(value uint32) { + volatile.StoreUint32(&o.CONF_W9.Reg, volatile.LoadUint32(&o.CONF_W9.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W9_SLCHOST_CONF37() uint32 { + return (volatile.LoadUint32(&o.CONF_W9.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W9_SLCHOST_CONF38(value uint32) { + volatile.StoreUint32(&o.CONF_W9.Reg, volatile.LoadUint32(&o.CONF_W9.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W9_SLCHOST_CONF38() uint32 { + return (volatile.LoadUint32(&o.CONF_W9.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W9_SLCHOST_CONF39(value uint32) { + volatile.StoreUint32(&o.CONF_W9.Reg, volatile.LoadUint32(&o.CONF_W9.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W9_SLCHOST_CONF39() uint32 { + return (volatile.LoadUint32(&o.CONF_W9.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W10: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W10_SLCHOST_CONF40(value uint32) { + volatile.StoreUint32(&o.CONF_W10.Reg, volatile.LoadUint32(&o.CONF_W10.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W10_SLCHOST_CONF40() uint32 { + return volatile.LoadUint32(&o.CONF_W10.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W10_SLCHOST_CONF41(value uint32) { + volatile.StoreUint32(&o.CONF_W10.Reg, volatile.LoadUint32(&o.CONF_W10.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W10_SLCHOST_CONF41() uint32 { + return (volatile.LoadUint32(&o.CONF_W10.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W10_SLCHOST_CONF42(value uint32) { + volatile.StoreUint32(&o.CONF_W10.Reg, volatile.LoadUint32(&o.CONF_W10.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W10_SLCHOST_CONF42() uint32 { + return (volatile.LoadUint32(&o.CONF_W10.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W10_SLCHOST_CONF43(value uint32) { + volatile.StoreUint32(&o.CONF_W10.Reg, volatile.LoadUint32(&o.CONF_W10.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W10_SLCHOST_CONF43() uint32 { + return (volatile.LoadUint32(&o.CONF_W10.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W11: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W11_SLCHOST_CONF44(value uint32) { + volatile.StoreUint32(&o.CONF_W11.Reg, volatile.LoadUint32(&o.CONF_W11.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W11_SLCHOST_CONF44() uint32 { + return volatile.LoadUint32(&o.CONF_W11.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W11_SLCHOST_CONF45(value uint32) { + volatile.StoreUint32(&o.CONF_W11.Reg, volatile.LoadUint32(&o.CONF_W11.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W11_SLCHOST_CONF45() uint32 { + return (volatile.LoadUint32(&o.CONF_W11.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W11_SLCHOST_CONF46(value uint32) { + volatile.StoreUint32(&o.CONF_W11.Reg, volatile.LoadUint32(&o.CONF_W11.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W11_SLCHOST_CONF46() uint32 { + return (volatile.LoadUint32(&o.CONF_W11.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W11_SLCHOST_CONF47(value uint32) { + volatile.StoreUint32(&o.CONF_W11.Reg, volatile.LoadUint32(&o.CONF_W11.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W11_SLCHOST_CONF47() uint32 { + return (volatile.LoadUint32(&o.CONF_W11.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W12: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W12_SLCHOST_CONF48(value uint32) { + volatile.StoreUint32(&o.CONF_W12.Reg, volatile.LoadUint32(&o.CONF_W12.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W12_SLCHOST_CONF48() uint32 { + return volatile.LoadUint32(&o.CONF_W12.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W12_SLCHOST_CONF49(value uint32) { + volatile.StoreUint32(&o.CONF_W12.Reg, volatile.LoadUint32(&o.CONF_W12.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W12_SLCHOST_CONF49() uint32 { + return (volatile.LoadUint32(&o.CONF_W12.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W12_SLCHOST_CONF50(value uint32) { + volatile.StoreUint32(&o.CONF_W12.Reg, volatile.LoadUint32(&o.CONF_W12.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W12_SLCHOST_CONF50() uint32 { + return (volatile.LoadUint32(&o.CONF_W12.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W12_SLCHOST_CONF51(value uint32) { + volatile.StoreUint32(&o.CONF_W12.Reg, volatile.LoadUint32(&o.CONF_W12.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W12_SLCHOST_CONF51() uint32 { + return (volatile.LoadUint32(&o.CONF_W12.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W13: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W13_SLCHOST_CONF52(value uint32) { + volatile.StoreUint32(&o.CONF_W13.Reg, volatile.LoadUint32(&o.CONF_W13.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W13_SLCHOST_CONF52() uint32 { + return volatile.LoadUint32(&o.CONF_W13.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W13_SLCHOST_CONF53(value uint32) { + volatile.StoreUint32(&o.CONF_W13.Reg, volatile.LoadUint32(&o.CONF_W13.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W13_SLCHOST_CONF53() uint32 { + return (volatile.LoadUint32(&o.CONF_W13.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W13_SLCHOST_CONF54(value uint32) { + volatile.StoreUint32(&o.CONF_W13.Reg, volatile.LoadUint32(&o.CONF_W13.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W13_SLCHOST_CONF54() uint32 { + return (volatile.LoadUint32(&o.CONF_W13.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W13_SLCHOST_CONF55(value uint32) { + volatile.StoreUint32(&o.CONF_W13.Reg, volatile.LoadUint32(&o.CONF_W13.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W13_SLCHOST_CONF55() uint32 { + return (volatile.LoadUint32(&o.CONF_W13.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W14: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W14_SLCHOST_CONF56(value uint32) { + volatile.StoreUint32(&o.CONF_W14.Reg, volatile.LoadUint32(&o.CONF_W14.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W14_SLCHOST_CONF56() uint32 { + return volatile.LoadUint32(&o.CONF_W14.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W14_SLCHOST_CONF57(value uint32) { + volatile.StoreUint32(&o.CONF_W14.Reg, volatile.LoadUint32(&o.CONF_W14.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W14_SLCHOST_CONF57() uint32 { + return (volatile.LoadUint32(&o.CONF_W14.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W14_SLCHOST_CONF58(value uint32) { + volatile.StoreUint32(&o.CONF_W14.Reg, volatile.LoadUint32(&o.CONF_W14.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W14_SLCHOST_CONF58() uint32 { + return (volatile.LoadUint32(&o.CONF_W14.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W14_SLCHOST_CONF59(value uint32) { + volatile.StoreUint32(&o.CONF_W14.Reg, volatile.LoadUint32(&o.CONF_W14.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W14_SLCHOST_CONF59() uint32 { + return (volatile.LoadUint32(&o.CONF_W14.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CONF_W15: *******Description*********** +func (o *SLCHOST_Type) SetCONF_W15_SLCHOST_CONF60(value uint32) { + volatile.StoreUint32(&o.CONF_W15.Reg, volatile.LoadUint32(&o.CONF_W15.Reg)&^(0xff)|value) +} +func (o *SLCHOST_Type) GetCONF_W15_SLCHOST_CONF60() uint32 { + return volatile.LoadUint32(&o.CONF_W15.Reg) & 0xff +} +func (o *SLCHOST_Type) SetCONF_W15_SLCHOST_CONF61(value uint32) { + volatile.StoreUint32(&o.CONF_W15.Reg, volatile.LoadUint32(&o.CONF_W15.Reg)&^(0xff00)|value<<8) +} +func (o *SLCHOST_Type) GetCONF_W15_SLCHOST_CONF61() uint32 { + return (volatile.LoadUint32(&o.CONF_W15.Reg) & 0xff00) >> 8 +} +func (o *SLCHOST_Type) SetCONF_W15_SLCHOST_CONF62(value uint32) { + volatile.StoreUint32(&o.CONF_W15.Reg, volatile.LoadUint32(&o.CONF_W15.Reg)&^(0xff0000)|value<<16) +} +func (o *SLCHOST_Type) GetCONF_W15_SLCHOST_CONF62() uint32 { + return (volatile.LoadUint32(&o.CONF_W15.Reg) & 0xff0000) >> 16 +} +func (o *SLCHOST_Type) SetCONF_W15_SLCHOST_CONF63(value uint32) { + volatile.StoreUint32(&o.CONF_W15.Reg, volatile.LoadUint32(&o.CONF_W15.Reg)&^(0xff000000)|value<<24) +} +func (o *SLCHOST_Type) GetCONF_W15_SLCHOST_CONF63() uint32 { + return (volatile.LoadUint32(&o.CONF_W15.Reg) & 0xff000000) >> 24 +} + +// SLCHOST.CHECK_SUM0: *******Description*********** +func (o *SLCHOST_Type) SetCHECK_SUM0(value uint32) { + volatile.StoreUint32(&o.CHECK_SUM0.Reg, value) +} +func (o *SLCHOST_Type) GetCHECK_SUM0() uint32 { + return volatile.LoadUint32(&o.CHECK_SUM0.Reg) +} + +// SLCHOST.CHECK_SUM1: *******Description*********** +func (o *SLCHOST_Type) SetCHECK_SUM1(value uint32) { + volatile.StoreUint32(&o.CHECK_SUM1.Reg, value) +} +func (o *SLCHOST_Type) GetCHECK_SUM1() uint32 { + return volatile.LoadUint32(&o.CHECK_SUM1.Reg) +} + +// SLCHOST.SLC1HOST_TOKEN_RDATA: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_TOKEN_RDATA_SLC1_TOKEN0(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.SLC1HOST_TOKEN_RDATA.Reg)&^(0xfff)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_TOKEN_RDATA_SLC1_TOKEN0() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_TOKEN_RDATA.Reg) & 0xfff +} +func (o *SLCHOST_Type) SetSLC1HOST_TOKEN_RDATA_SLC1_RX_PF_VALID(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.SLC1HOST_TOKEN_RDATA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC1HOST_TOKEN_RDATA_SLC1_RX_PF_VALID() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_TOKEN_RDATA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC1HOST_TOKEN_RDATA_HOSTSLCHOST_SLC1_TOKEN1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.SLC1HOST_TOKEN_RDATA.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC1HOST_TOKEN_RDATA_HOSTSLCHOST_SLC1_TOKEN1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_TOKEN_RDATA.Reg) & 0xfff0000) >> 16 +} +func (o *SLCHOST_Type) SetSLC1HOST_TOKEN_RDATA_SLC1_RX_PF_EOF(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_TOKEN_RDATA.Reg, volatile.LoadUint32(&o.SLC1HOST_TOKEN_RDATA.Reg)&^(0xf0000000)|value<<28) +} +func (o *SLCHOST_Type) GetSLC1HOST_TOKEN_RDATA_SLC1_RX_PF_EOF() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_TOKEN_RDATA.Reg) & 0xf0000000) >> 28 +} + +// SLCHOST.SLC0HOST_TOKEN_WDATA: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_TOKEN_WDATA_SLC0HOST_TOKEN0_WD(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_TOKEN_WDATA.Reg, volatile.LoadUint32(&o.SLC0HOST_TOKEN_WDATA.Reg)&^(0xfff)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_TOKEN_WDATA_SLC0HOST_TOKEN0_WD() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_TOKEN_WDATA.Reg) & 0xfff +} +func (o *SLCHOST_Type) SetSLC0HOST_TOKEN_WDATA_SLC0HOST_TOKEN1_WD(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_TOKEN_WDATA.Reg, volatile.LoadUint32(&o.SLC0HOST_TOKEN_WDATA.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC0HOST_TOKEN_WDATA_SLC0HOST_TOKEN1_WD() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_TOKEN_WDATA.Reg) & 0xfff0000) >> 16 +} + +// SLCHOST.SLC1HOST_TOKEN_WDATA: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_TOKEN_WDATA_SLC1HOST_TOKEN0_WD(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_TOKEN_WDATA.Reg, volatile.LoadUint32(&o.SLC1HOST_TOKEN_WDATA.Reg)&^(0xfff)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_TOKEN_WDATA_SLC1HOST_TOKEN0_WD() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_TOKEN_WDATA.Reg) & 0xfff +} +func (o *SLCHOST_Type) SetSLC1HOST_TOKEN_WDATA_SLC1HOST_TOKEN1_WD(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_TOKEN_WDATA.Reg, volatile.LoadUint32(&o.SLC1HOST_TOKEN_WDATA.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC1HOST_TOKEN_WDATA_SLC1HOST_TOKEN1_WD() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_TOKEN_WDATA.Reg) & 0xfff0000) >> 16 +} + +// SLCHOST.TOKEN_CON: *******Description*********** +func (o *SLCHOST_Type) SetTOKEN_CON_SLC0HOST_TOKEN0_DEC(value uint32) { + volatile.StoreUint32(&o.TOKEN_CON.Reg, volatile.LoadUint32(&o.TOKEN_CON.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetTOKEN_CON_SLC0HOST_TOKEN0_DEC() uint32 { + return volatile.LoadUint32(&o.TOKEN_CON.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetTOKEN_CON_SLC0HOST_TOKEN1_DEC(value uint32) { + volatile.StoreUint32(&o.TOKEN_CON.Reg, volatile.LoadUint32(&o.TOKEN_CON.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetTOKEN_CON_SLC0HOST_TOKEN1_DEC() uint32 { + return (volatile.LoadUint32(&o.TOKEN_CON.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetTOKEN_CON_SLC0HOST_TOKEN0_WR(value uint32) { + volatile.StoreUint32(&o.TOKEN_CON.Reg, volatile.LoadUint32(&o.TOKEN_CON.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetTOKEN_CON_SLC0HOST_TOKEN0_WR() uint32 { + return (volatile.LoadUint32(&o.TOKEN_CON.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetTOKEN_CON_SLC0HOST_TOKEN1_WR(value uint32) { + volatile.StoreUint32(&o.TOKEN_CON.Reg, volatile.LoadUint32(&o.TOKEN_CON.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetTOKEN_CON_SLC0HOST_TOKEN1_WR() uint32 { + return (volatile.LoadUint32(&o.TOKEN_CON.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetTOKEN_CON_SLC1HOST_TOKEN0_DEC(value uint32) { + volatile.StoreUint32(&o.TOKEN_CON.Reg, volatile.LoadUint32(&o.TOKEN_CON.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetTOKEN_CON_SLC1HOST_TOKEN0_DEC() uint32 { + return (volatile.LoadUint32(&o.TOKEN_CON.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetTOKEN_CON_SLC1HOST_TOKEN1_DEC(value uint32) { + volatile.StoreUint32(&o.TOKEN_CON.Reg, volatile.LoadUint32(&o.TOKEN_CON.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetTOKEN_CON_SLC1HOST_TOKEN1_DEC() uint32 { + return (volatile.LoadUint32(&o.TOKEN_CON.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetTOKEN_CON_SLC1HOST_TOKEN0_WR(value uint32) { + volatile.StoreUint32(&o.TOKEN_CON.Reg, volatile.LoadUint32(&o.TOKEN_CON.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetTOKEN_CON_SLC1HOST_TOKEN0_WR() uint32 { + return (volatile.LoadUint32(&o.TOKEN_CON.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetTOKEN_CON_SLC1HOST_TOKEN1_WR(value uint32) { + volatile.StoreUint32(&o.TOKEN_CON.Reg, volatile.LoadUint32(&o.TOKEN_CON.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetTOKEN_CON_SLC1HOST_TOKEN1_WR() uint32 { + return (volatile.LoadUint32(&o.TOKEN_CON.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetTOKEN_CON_SLC0HOST_LEN_WR(value uint32) { + volatile.StoreUint32(&o.TOKEN_CON.Reg, volatile.LoadUint32(&o.TOKEN_CON.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetTOKEN_CON_SLC0HOST_LEN_WR() uint32 { + return (volatile.LoadUint32(&o.TOKEN_CON.Reg) & 0x100) >> 8 +} + +// SLCHOST.SLC0HOST_INT_CLR: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOHOST_BIT7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOKEN0_0TO1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOKEN0_0TO1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TOKEN1_0TO1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TOKEN1_0TO1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0HOST_RX_SOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0HOST_RX_SOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0HOST_RX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0HOST_RX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0HOST_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0HOST_RX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0HOST_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0HOST_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_RX_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_RX_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_TX_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_TX_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_RX_PF_VALID_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_RX_PF_VALID_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_EXT_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_EXT_BIT0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_EXT_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_EXT_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_EXT_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_EXT_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_EXT_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_EXT_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_RX_NEW_PACKET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_RX_NEW_PACKET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_SLC0_HOST_RD_RETRY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_SLC0_HOST_RD_RETRY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_CLR_GPIO_SDIO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_CLR_GPIO_SDIO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_CLR.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC1HOST_INT_CLR: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOHOST_BIT7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOKEN0_0TO1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOKEN0_0TO1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TOKEN1_0TO1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TOKEN1_0TO1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1HOST_RX_SOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1HOST_RX_SOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1HOST_RX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1HOST_RX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1HOST_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1HOST_RX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1HOST_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1HOST_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_RX_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_RX_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_TX_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_TX_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_RX_PF_VALID_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_RX_PF_VALID_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_EXT_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_EXT_BIT0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_EXT_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_EXT_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_EXT_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_EXT_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_EXT_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_EXT_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_WIFI_RX_NEW_PACKET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_WIFI_RX_NEW_PACKET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_HOST_RD_RETRY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_HOST_RD_RETRY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_CLR_SLC1_BT_RX_NEW_PACKET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_CLR.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_CLR_SLC1_BT_RX_NEW_PACKET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_CLR.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC0HOST_FUNC1_INT_ENA: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_SLC0_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC1_INT_ENA_FN1_GPIO_SDIO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC1_INT_ENA_FN1_GPIO_SDIO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC1_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC1HOST_FUNC1_INT_ENA: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC1_INT_ENA_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC1_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC0HOST_FUNC2_INT_ENA: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_SLC0_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC0HOST_FUNC2_INT_ENA_FN2_GPIO_SDIO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC0HOST_FUNC2_INT_ENA_FN2_GPIO_SDIO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_FUNC2_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC1HOST_FUNC2_INT_ENA: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC1HOST_FUNC2_INT_ENA_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_FUNC2_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC0HOST_INT_ENA: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_SLC0_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_SLC0_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA_GPIO_SDIO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA_GPIO_SDIO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC1HOST_INT_ENA: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOKEN0_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOKEN0_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TOKEN1_0TO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TOKEN1_0TO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1HOST_RX_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1HOST_RX_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1HOST_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1HOST_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1HOST_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1HOST_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1HOST_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1HOST_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_RX_PF_VALID_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_RX_PF_VALID_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_EXT_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_EXT_BIT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_EXT_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_EXT_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_EXT_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_EXT_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_EXT_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_EXT_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_WIFI_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_WIFI_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_HOST_RD_RETRY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_HOST_RD_RETRY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA_SLC1_BT_RX_NEW_PACKET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA_SLC1_BT_RX_NEW_PACKET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC0HOST_RX_INFOR: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_RX_INFOR(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_RX_INFOR.Reg, volatile.LoadUint32(&o.SLC0HOST_RX_INFOR.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_RX_INFOR() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_RX_INFOR.Reg) & 0xfffff +} + +// SLCHOST.SLC1HOST_RX_INFOR: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_RX_INFOR(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_RX_INFOR.Reg, volatile.LoadUint32(&o.SLC1HOST_RX_INFOR.Reg)&^(0xfffff)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_RX_INFOR() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_RX_INFOR.Reg) & 0xfffff +} + +// SLCHOST.SLC0HOST_LEN_WD: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_LEN_WD(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_LEN_WD.Reg, value) +} +func (o *SLCHOST_Type) GetSLC0HOST_LEN_WD() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_LEN_WD.Reg) +} + +// SLCHOST.SLC_APBWIN_WDATA: *******Description*********** +func (o *SLCHOST_Type) SetSLC_APBWIN_WDATA(value uint32) { + volatile.StoreUint32(&o.SLC_APBWIN_WDATA.Reg, value) +} +func (o *SLCHOST_Type) GetSLC_APBWIN_WDATA() uint32 { + return volatile.LoadUint32(&o.SLC_APBWIN_WDATA.Reg) +} + +// SLCHOST.SLC_APBWIN_CONF: *******Description*********** +func (o *SLCHOST_Type) SetSLC_APBWIN_CONF_SLC_APBWIN_ADDR(value uint32) { + volatile.StoreUint32(&o.SLC_APBWIN_CONF.Reg, volatile.LoadUint32(&o.SLC_APBWIN_CONF.Reg)&^(0xfffffff)|value) +} +func (o *SLCHOST_Type) GetSLC_APBWIN_CONF_SLC_APBWIN_ADDR() uint32 { + return volatile.LoadUint32(&o.SLC_APBWIN_CONF.Reg) & 0xfffffff +} +func (o *SLCHOST_Type) SetSLC_APBWIN_CONF_SLC_APBWIN_WR(value uint32) { + volatile.StoreUint32(&o.SLC_APBWIN_CONF.Reg, volatile.LoadUint32(&o.SLC_APBWIN_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SLCHOST_Type) GetSLC_APBWIN_CONF_SLC_APBWIN_WR() uint32 { + return (volatile.LoadUint32(&o.SLC_APBWIN_CONF.Reg) & 0x10000000) >> 28 +} +func (o *SLCHOST_Type) SetSLC_APBWIN_CONF_SLC_APBWIN_START(value uint32) { + volatile.StoreUint32(&o.SLC_APBWIN_CONF.Reg, volatile.LoadUint32(&o.SLC_APBWIN_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SLCHOST_Type) GetSLC_APBWIN_CONF_SLC_APBWIN_START() uint32 { + return (volatile.LoadUint32(&o.SLC_APBWIN_CONF.Reg) & 0x20000000) >> 29 +} + +// SLCHOST.SLC_APBWIN_RDATA: *******Description*********** +func (o *SLCHOST_Type) SetSLC_APBWIN_RDATA(value uint32) { + volatile.StoreUint32(&o.SLC_APBWIN_RDATA.Reg, value) +} +func (o *SLCHOST_Type) GetSLC_APBWIN_RDATA() uint32 { + return volatile.LoadUint32(&o.SLC_APBWIN_RDATA.Reg) +} + +// SLCHOST.RDCLR0: *******Description*********** +func (o *SLCHOST_Type) SetRDCLR0_SLCHOST_SLC0_BIT7_CLRADDR(value uint32) { + volatile.StoreUint32(&o.RDCLR0.Reg, volatile.LoadUint32(&o.RDCLR0.Reg)&^(0x1ff)|value) +} +func (o *SLCHOST_Type) GetRDCLR0_SLCHOST_SLC0_BIT7_CLRADDR() uint32 { + return volatile.LoadUint32(&o.RDCLR0.Reg) & 0x1ff +} +func (o *SLCHOST_Type) SetRDCLR0_SLCHOST_SLC0_BIT6_CLRADDR(value uint32) { + volatile.StoreUint32(&o.RDCLR0.Reg, volatile.LoadUint32(&o.RDCLR0.Reg)&^(0x3fe00)|value<<9) +} +func (o *SLCHOST_Type) GetRDCLR0_SLCHOST_SLC0_BIT6_CLRADDR() uint32 { + return (volatile.LoadUint32(&o.RDCLR0.Reg) & 0x3fe00) >> 9 +} + +// SLCHOST.RDCLR1: *******Description*********** +func (o *SLCHOST_Type) SetRDCLR1_SLCHOST_SLC1_BIT7_CLRADDR(value uint32) { + volatile.StoreUint32(&o.RDCLR1.Reg, volatile.LoadUint32(&o.RDCLR1.Reg)&^(0x1ff)|value) +} +func (o *SLCHOST_Type) GetRDCLR1_SLCHOST_SLC1_BIT7_CLRADDR() uint32 { + return volatile.LoadUint32(&o.RDCLR1.Reg) & 0x1ff +} +func (o *SLCHOST_Type) SetRDCLR1_SLCHOST_SLC1_BIT6_CLRADDR(value uint32) { + volatile.StoreUint32(&o.RDCLR1.Reg, volatile.LoadUint32(&o.RDCLR1.Reg)&^(0x3fe00)|value<<9) +} +func (o *SLCHOST_Type) GetRDCLR1_SLCHOST_SLC1_BIT6_CLRADDR() uint32 { + return (volatile.LoadUint32(&o.RDCLR1.Reg) & 0x3fe00) >> 9 +} + +// SLCHOST.SLC0HOST_INT_ENA1: *******Description*********** +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT0_INT_ENA1() uint32 { + return volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT2_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT2_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT3_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT3_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT4_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT4_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT5_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT5_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT6_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT6_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT7_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOHOST_BIT7_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOKEN0_0TO1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOKEN0_0TO1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TOKEN1_0TO1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TOKEN1_0TO1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0HOST_RX_SOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0HOST_RX_SOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0HOST_RX_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0HOST_RX_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0HOST_RX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0HOST_RX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0HOST_TX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0HOST_TX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_RX_UDF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_RX_UDF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_TX_OVF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_TX_OVF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_RX_PF_VALID_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_RX_PF_VALID_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_EXT_BIT0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_EXT_BIT0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_EXT_BIT1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_EXT_BIT1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_EXT_BIT2_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_EXT_BIT2_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_EXT_BIT3_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_EXT_BIT3_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_RX_NEW_PACKET_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_RX_NEW_PACKET_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_SLC0_HOST_RD_RETRY_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_SLC0_HOST_RD_RETRY_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC0HOST_INT_ENA1_GPIO_SDIO_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC0HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC0HOST_INT_ENA1_GPIO_SDIO_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC0HOST_INT_ENA1.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLC1HOST_INT_ENA1: *******Description*********** +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x1)|value) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT0_INT_ENA1() uint32 { + return volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x2)|value<<1) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x2) >> 1 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT2_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x4)|value<<2) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT2_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x4) >> 2 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT3_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x8)|value<<3) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT3_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x8) >> 3 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT4_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x10)|value<<4) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT4_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x10) >> 4 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT5_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x20)|value<<5) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT5_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x20) >> 5 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT6_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x40)|value<<6) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT6_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x40) >> 6 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT7_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x80)|value<<7) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOHOST_BIT7_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x80) >> 7 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x100)|value<<8) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x100) >> 8 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x200)|value<<9) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x200) >> 9 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOKEN0_0TO1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x400)|value<<10) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOKEN0_0TO1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x400) >> 10 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TOKEN1_0TO1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x800)|value<<11) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TOKEN1_0TO1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x800) >> 11 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1HOST_RX_SOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x1000)|value<<12) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1HOST_RX_SOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x1000) >> 12 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1HOST_RX_EOF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x2000)|value<<13) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1HOST_RX_EOF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x2000) >> 13 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1HOST_RX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x4000)|value<<14) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1HOST_RX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x4000) >> 14 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1HOST_TX_START_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1HOST_TX_START_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_RX_UDF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_RX_UDF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_TX_OVF_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_TX_OVF_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_RX_PF_VALID_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x40000)|value<<18) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_RX_PF_VALID_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x40000) >> 18 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_EXT_BIT0_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x80000)|value<<19) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_EXT_BIT0_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x80000) >> 19 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_EXT_BIT1_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x100000)|value<<20) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_EXT_BIT1_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x100000) >> 20 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_EXT_BIT2_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x200000)|value<<21) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_EXT_BIT2_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x200000) >> 21 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_EXT_BIT3_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x400000)|value<<22) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_EXT_BIT3_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x400000) >> 22 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x800000)|value<<23) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x800000) >> 23 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_HOST_RD_RETRY_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x1000000)|value<<24) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_HOST_RD_RETRY_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x1000000) >> 24 +} +func (o *SLCHOST_Type) SetSLC1HOST_INT_ENA1_SLC1_BT_RX_NEW_PACKET_INT_ENA1(value uint32) { + volatile.StoreUint32(&o.SLC1HOST_INT_ENA1.Reg, volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetSLC1HOST_INT_ENA1_SLC1_BT_RX_NEW_PACKET_INT_ENA1() uint32 { + return (volatile.LoadUint32(&o.SLC1HOST_INT_ENA1.Reg) & 0x2000000) >> 25 +} + +// SLCHOST.SLCHOSTDATE: *******Description*********** +func (o *SLCHOST_Type) SetSLCHOSTDATE(value uint32) { + volatile.StoreUint32(&o.SLCHOSTDATE.Reg, value) +} +func (o *SLCHOST_Type) GetSLCHOSTDATE() uint32 { + return volatile.LoadUint32(&o.SLCHOSTDATE.Reg) +} + +// SLCHOST.SLCHOSTID: *******Description*********** +func (o *SLCHOST_Type) SetSLCHOSTID(value uint32) { + volatile.StoreUint32(&o.SLCHOSTID.Reg, value) +} +func (o *SLCHOST_Type) GetSLCHOSTID() uint32 { + return volatile.LoadUint32(&o.SLCHOSTID.Reg) +} + +// SLCHOST.CONF: *******Description*********** +func (o *SLCHOST_Type) SetCONF_FRC_SDIO11(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1f)|value) +} +func (o *SLCHOST_Type) GetCONF_FRC_SDIO11() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1f +} +func (o *SLCHOST_Type) SetCONF_FRC_SDIO20(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3e0)|value<<5) +} +func (o *SLCHOST_Type) GetCONF_FRC_SDIO20() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x3e0) >> 5 +} +func (o *SLCHOST_Type) SetCONF_FRC_NEG_SAMP(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x7c00)|value<<10) +} +func (o *SLCHOST_Type) GetCONF_FRC_NEG_SAMP() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x7c00) >> 10 +} +func (o *SLCHOST_Type) SetCONF_FRC_POS_SAMP(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xf8000)|value<<15) +} +func (o *SLCHOST_Type) GetCONF_FRC_POS_SAMP() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0xf8000) >> 15 +} +func (o *SLCHOST_Type) SetCONF_FRC_QUICK_IN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1f00000)|value<<20) +} +func (o *SLCHOST_Type) GetCONF_FRC_QUICK_IN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1f00000) >> 20 +} +func (o *SLCHOST_Type) SetCONF_SDIO20_INT_DELAY(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SLCHOST_Type) GetCONF_SDIO20_INT_DELAY() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25 +} +func (o *SLCHOST_Type) SetCONF_SDIO_PAD_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *SLCHOST_Type) GetCONF_SDIO_PAD_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000000) >> 26 +} +func (o *SLCHOST_Type) SetCONF_HSPEED_CON_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SLCHOST_Type) GetCONF_HSPEED_CON_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000000) >> 27 +} + +// SLCHOST.INF_ST: *******Description*********** +func (o *SLCHOST_Type) SetINF_ST_SDIO20_MODE(value uint32) { + volatile.StoreUint32(&o.INF_ST.Reg, volatile.LoadUint32(&o.INF_ST.Reg)&^(0x1f)|value) +} +func (o *SLCHOST_Type) GetINF_ST_SDIO20_MODE() uint32 { + return volatile.LoadUint32(&o.INF_ST.Reg) & 0x1f +} +func (o *SLCHOST_Type) SetINF_ST_SDIO_NEG_SAMP(value uint32) { + volatile.StoreUint32(&o.INF_ST.Reg, volatile.LoadUint32(&o.INF_ST.Reg)&^(0x3e0)|value<<5) +} +func (o *SLCHOST_Type) GetINF_ST_SDIO_NEG_SAMP() uint32 { + return (volatile.LoadUint32(&o.INF_ST.Reg) & 0x3e0) >> 5 +} +func (o *SLCHOST_Type) SetINF_ST_SDIO_QUICK_IN(value uint32) { + volatile.StoreUint32(&o.INF_ST.Reg, volatile.LoadUint32(&o.INF_ST.Reg)&^(0x7c00)|value<<10) +} +func (o *SLCHOST_Type) GetINF_ST_SDIO_QUICK_IN() uint32 { + return (volatile.LoadUint32(&o.INF_ST.Reg) & 0x7c00) >> 10 +} +func (o *SLCHOST_Type) SetINF_ST_DLL_ON_SW(value uint32) { + volatile.StoreUint32(&o.INF_ST.Reg, volatile.LoadUint32(&o.INF_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SLCHOST_Type) GetINF_ST_DLL_ON_SW() uint32 { + return (volatile.LoadUint32(&o.INF_ST.Reg) & 0x8000) >> 15 +} +func (o *SLCHOST_Type) SetINF_ST_DLL_ON(value uint32) { + volatile.StoreUint32(&o.INF_ST.Reg, volatile.LoadUint32(&o.INF_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SLCHOST_Type) GetINF_ST_DLL_ON() uint32 { + return (volatile.LoadUint32(&o.INF_ST.Reg) & 0x10000) >> 16 +} +func (o *SLCHOST_Type) SetINF_ST_CLK_MODE_SW(value uint32) { + volatile.StoreUint32(&o.INF_ST.Reg, volatile.LoadUint32(&o.INF_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SLCHOST_Type) GetINF_ST_CLK_MODE_SW() uint32 { + return (volatile.LoadUint32(&o.INF_ST.Reg) & 0x20000) >> 17 +} +func (o *SLCHOST_Type) SetINF_ST_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.INF_ST.Reg, volatile.LoadUint32(&o.INF_ST.Reg)&^(0xc0000)|value<<18) +} +func (o *SLCHOST_Type) GetINF_ST_CLK_MODE() uint32 { + return (volatile.LoadUint32(&o.INF_ST.Reg) & 0xc0000) >> 18 +} + +// Event Task Matrix +type SOC_ETM_Type struct { + CH_ENA_AD0 volatile.Register32 // 0x0 + CH_ENA_AD0_SET volatile.Register32 // 0x4 + CH_ENA_AD0_CLR volatile.Register32 // 0x8 + CH_ENA_AD1 volatile.Register32 // 0xC + CH_ENA_AD1_SET volatile.Register32 // 0x10 + CH_ENA_AD1_CLR volatile.Register32 // 0x14 + CH0_EVT_ID volatile.Register32 // 0x18 + CH0_TASK_ID volatile.Register32 // 0x1C + CH1_EVT_ID volatile.Register32 // 0x20 + CH1_TASK_ID volatile.Register32 // 0x24 + CH2_EVT_ID volatile.Register32 // 0x28 + CH2_TASK_ID volatile.Register32 // 0x2C + CH3_EVT_ID volatile.Register32 // 0x30 + CH3_TASK_ID volatile.Register32 // 0x34 + CH4_EVT_ID volatile.Register32 // 0x38 + CH4_TASK_ID volatile.Register32 // 0x3C + CH5_EVT_ID volatile.Register32 // 0x40 + CH5_TASK_ID volatile.Register32 // 0x44 + CH6_EVT_ID volatile.Register32 // 0x48 + CH6_TASK_ID volatile.Register32 // 0x4C + CH7_EVT_ID volatile.Register32 // 0x50 + CH7_TASK_ID volatile.Register32 // 0x54 + CH8_EVT_ID volatile.Register32 // 0x58 + CH8_TASK_ID volatile.Register32 // 0x5C + CH9_EVT_ID volatile.Register32 // 0x60 + CH9_TASK_ID volatile.Register32 // 0x64 + CH10_EVT_ID volatile.Register32 // 0x68 + CH10_TASK_ID volatile.Register32 // 0x6C + CH11_EVT_ID volatile.Register32 // 0x70 + CH11_TASK_ID volatile.Register32 // 0x74 + CH12_EVT_ID volatile.Register32 // 0x78 + CH12_TASK_ID volatile.Register32 // 0x7C + CH13_EVT_ID volatile.Register32 // 0x80 + CH13_TASK_ID volatile.Register32 // 0x84 + CH14_EVT_ID volatile.Register32 // 0x88 + CH14_TASK_ID volatile.Register32 // 0x8C + CH15_EVT_ID volatile.Register32 // 0x90 + CH15_TASK_ID volatile.Register32 // 0x94 + CH16_EVT_ID volatile.Register32 // 0x98 + CH16_TASK_ID volatile.Register32 // 0x9C + CH17_EVT_ID volatile.Register32 // 0xA0 + CH17_TASK_ID volatile.Register32 // 0xA4 + CH18_EVT_ID volatile.Register32 // 0xA8 + CH18_TASK_ID volatile.Register32 // 0xAC + CH19_EVT_ID volatile.Register32 // 0xB0 + CH19_TASK_ID volatile.Register32 // 0xB4 + CH20_EVT_ID volatile.Register32 // 0xB8 + CH20_TASK_ID volatile.Register32 // 0xBC + CH21_EVT_ID volatile.Register32 // 0xC0 + CH21_TASK_ID volatile.Register32 // 0xC4 + CH22_EVT_ID volatile.Register32 // 0xC8 + CH22_TASK_ID volatile.Register32 // 0xCC + CH23_EVT_ID volatile.Register32 // 0xD0 + CH23_TASK_ID volatile.Register32 // 0xD4 + CH24_EVT_ID volatile.Register32 // 0xD8 + CH24_TASK_ID volatile.Register32 // 0xDC + CH25_EVT_ID volatile.Register32 // 0xE0 + CH25_TASK_ID volatile.Register32 // 0xE4 + CH26_EVT_ID volatile.Register32 // 0xE8 + CH26_TASK_ID volatile.Register32 // 0xEC + CH27_EVT_ID volatile.Register32 // 0xF0 + CH27_TASK_ID volatile.Register32 // 0xF4 + CH28_EVT_ID volatile.Register32 // 0xF8 + CH28_TASK_ID volatile.Register32 // 0xFC + CH29_EVT_ID volatile.Register32 // 0x100 + CH29_TASK_ID volatile.Register32 // 0x104 + CH30_EVT_ID volatile.Register32 // 0x108 + CH30_TASK_ID volatile.Register32 // 0x10C + CH31_EVT_ID volatile.Register32 // 0x110 + CH31_TASK_ID volatile.Register32 // 0x114 + CH32_EVT_ID volatile.Register32 // 0x118 + CH32_TASK_ID volatile.Register32 // 0x11C + CH33_EVT_ID volatile.Register32 // 0x120 + CH33_TASK_ID volatile.Register32 // 0x124 + CH34_EVT_ID volatile.Register32 // 0x128 + CH34_TASK_ID volatile.Register32 // 0x12C + CH35_EVT_ID volatile.Register32 // 0x130 + CH35_TASK_ID volatile.Register32 // 0x134 + CH36_EVT_ID volatile.Register32 // 0x138 + CH36_TASK_ID volatile.Register32 // 0x13C + CH37_EVT_ID volatile.Register32 // 0x140 + CH37_TASK_ID volatile.Register32 // 0x144 + CH38_EVT_ID volatile.Register32 // 0x148 + CH38_TASK_ID volatile.Register32 // 0x14C + CH39_EVT_ID volatile.Register32 // 0x150 + CH39_TASK_ID volatile.Register32 // 0x154 + CH40_EVT_ID volatile.Register32 // 0x158 + CH40_TASK_ID volatile.Register32 // 0x15C + CH41_EVT_ID volatile.Register32 // 0x160 + CH41_TASK_ID volatile.Register32 // 0x164 + CH42_EVT_ID volatile.Register32 // 0x168 + CH42_TASK_ID volatile.Register32 // 0x16C + CH43_EVT_ID volatile.Register32 // 0x170 + CH43_TASK_ID volatile.Register32 // 0x174 + CH44_EVT_ID volatile.Register32 // 0x178 + CH44_TASK_ID volatile.Register32 // 0x17C + CH45_EVT_ID volatile.Register32 // 0x180 + CH45_TASK_ID volatile.Register32 // 0x184 + CH46_EVT_ID volatile.Register32 // 0x188 + CH46_TASK_ID volatile.Register32 // 0x18C + CH47_EVT_ID volatile.Register32 // 0x190 + CH47_TASK_ID volatile.Register32 // 0x194 + CH48_EVT_ID volatile.Register32 // 0x198 + CH48_TASK_ID volatile.Register32 // 0x19C + CH49_EVT_ID volatile.Register32 // 0x1A0 + CH49_TASK_ID volatile.Register32 // 0x1A4 + CLK_EN volatile.Register32 // 0x1A8 + DATE volatile.Register32 // 0x1AC +} + +// SOC_ETM.CH_ENA_AD0: channel enable register +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA0(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA0() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA1(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA1() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA2(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA2() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA3(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA3() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA4(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA4() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA5(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA5() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA6(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA6() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA7(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA7() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA8(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA8() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA9(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA9() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA10(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA10() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA11(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA11() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA12(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA12() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA13(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA13() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA14(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA14() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA15(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA15() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA16(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA16() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA17(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA17() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA18(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA18() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA19(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA19() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA20(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA20() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA21(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA21() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA22(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA22() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA23(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA23() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA24(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA24() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA25(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA25() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA26(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA26() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA27(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA27() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA28(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA28() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA29(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA29() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA30(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA30() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA31(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA31() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.CH_ENA_AD0_SET: channel enable set register +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET0(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET0() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET1(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET1() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET2(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET2() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET3(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET3() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET4(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET4() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET5(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET5() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET6(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET6() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET7(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET7() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET8(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET8() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET9(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET9() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET10(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET10() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET11(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET11() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET12(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET12() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET13(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET13() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET14(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET14() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET15(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET15() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET16(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET16() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET17(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET17() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET18(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET18() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET19(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET19() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET20(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET20() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET21(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET21() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET22(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET22() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET23(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET23() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET24(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET24() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET25(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET25() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET26(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET26() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET27(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET27() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET28(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET28() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET29(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET29() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET30(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET30() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET31(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET31() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.CH_ENA_AD0_CLR: channel enable clear register +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR0(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR0() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR1(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR1() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR2(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR2() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR3(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR3() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR4(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR4() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR5(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR5() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR6(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR6() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR7(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR7() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR8(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR8() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR9(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR9() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR10(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR10() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR11(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR11() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR12(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR12() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR13(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR13() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR14(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR14() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR15(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR15() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR16(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR16() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR17(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR17() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR18(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR18() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR19(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR19() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR20(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR20() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR21(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR21() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR22(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR22() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR23(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR23() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR24(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR24() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR25(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR25() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR26(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR26() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR27(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR27() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR28(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR28() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR29(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR29() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR30(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR30() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR31(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR31() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.CH_ENA_AD1: channel enable register +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA32(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA32() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA33(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA33() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA34(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA34() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA35(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA35() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA36(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA36() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA37(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA37() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA38(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA38() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA39(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA39() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA40(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA40() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA41(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA41() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA42(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA42() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA43(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA43() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA44(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA44() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA45(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA45() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA46(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA46() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA47(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA47() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA48(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA48() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA49(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA49() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x20000) >> 17 +} + +// SOC_ETM.CH_ENA_AD1_SET: channel enable set register +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET32(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET32() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET33(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET33() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET34(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET34() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET35(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET35() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET36(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET36() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET37(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET37() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET38(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET38() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET39(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET39() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET40(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET40() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET41(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET41() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET42(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET42() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET43(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET43() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET44(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET44() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET45(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET45() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET46(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET46() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET47(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET47() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET48(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET48() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET49(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET49() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x20000) >> 17 +} + +// SOC_ETM.CH_ENA_AD1_CLR: channel enable clear register +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR32(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR32() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR33(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR33() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR34(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR34() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR35(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR35() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR36(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR36() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR37(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR37() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR38(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR38() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR39(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR39() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR40(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR40() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR41(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR41() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR42(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR42() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR43(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR43() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR44(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR44() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR45(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR45() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR46(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR46() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR47(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR47() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR48(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR48() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR49(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR49() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x20000) >> 17 +} + +// SOC_ETM.CH0_EVT_ID: channel0 event id register +func (o *SOC_ETM_Type) SetCH0_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH0_EVT_ID.Reg, volatile.LoadUint32(&o.CH0_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH0_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH0_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH0_TASK_ID: channel0 task id register +func (o *SOC_ETM_Type) SetCH0_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH0_TASK_ID.Reg, volatile.LoadUint32(&o.CH0_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH0_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH0_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH1_EVT_ID: channel1 event id register +func (o *SOC_ETM_Type) SetCH1_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH1_EVT_ID.Reg, volatile.LoadUint32(&o.CH1_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH1_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH1_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH1_TASK_ID: channel1 task id register +func (o *SOC_ETM_Type) SetCH1_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH1_TASK_ID.Reg, volatile.LoadUint32(&o.CH1_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH1_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH1_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH2_EVT_ID: channel2 event id register +func (o *SOC_ETM_Type) SetCH2_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH2_EVT_ID.Reg, volatile.LoadUint32(&o.CH2_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH2_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH2_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH2_TASK_ID: channel2 task id register +func (o *SOC_ETM_Type) SetCH2_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH2_TASK_ID.Reg, volatile.LoadUint32(&o.CH2_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH2_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH2_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH3_EVT_ID: channel3 event id register +func (o *SOC_ETM_Type) SetCH3_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH3_EVT_ID.Reg, volatile.LoadUint32(&o.CH3_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH3_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH3_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH3_TASK_ID: channel3 task id register +func (o *SOC_ETM_Type) SetCH3_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH3_TASK_ID.Reg, volatile.LoadUint32(&o.CH3_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH3_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH3_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH4_EVT_ID: channel4 event id register +func (o *SOC_ETM_Type) SetCH4_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH4_EVT_ID.Reg, volatile.LoadUint32(&o.CH4_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH4_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH4_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH4_TASK_ID: channel4 task id register +func (o *SOC_ETM_Type) SetCH4_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH4_TASK_ID.Reg, volatile.LoadUint32(&o.CH4_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH4_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH4_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH5_EVT_ID: channel5 event id register +func (o *SOC_ETM_Type) SetCH5_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH5_EVT_ID.Reg, volatile.LoadUint32(&o.CH5_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH5_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH5_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH5_TASK_ID: channel5 task id register +func (o *SOC_ETM_Type) SetCH5_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH5_TASK_ID.Reg, volatile.LoadUint32(&o.CH5_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH5_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH5_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH6_EVT_ID: channel6 event id register +func (o *SOC_ETM_Type) SetCH6_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH6_EVT_ID.Reg, volatile.LoadUint32(&o.CH6_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH6_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH6_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH6_TASK_ID: channel6 task id register +func (o *SOC_ETM_Type) SetCH6_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH6_TASK_ID.Reg, volatile.LoadUint32(&o.CH6_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH6_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH6_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH7_EVT_ID: channel7 event id register +func (o *SOC_ETM_Type) SetCH7_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH7_EVT_ID.Reg, volatile.LoadUint32(&o.CH7_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH7_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH7_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH7_TASK_ID: channel7 task id register +func (o *SOC_ETM_Type) SetCH7_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH7_TASK_ID.Reg, volatile.LoadUint32(&o.CH7_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH7_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH7_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH8_EVT_ID: channel8 event id register +func (o *SOC_ETM_Type) SetCH8_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH8_EVT_ID.Reg, volatile.LoadUint32(&o.CH8_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH8_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH8_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH8_TASK_ID: channel8 task id register +func (o *SOC_ETM_Type) SetCH8_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH8_TASK_ID.Reg, volatile.LoadUint32(&o.CH8_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH8_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH8_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH9_EVT_ID: channel9 event id register +func (o *SOC_ETM_Type) SetCH9_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH9_EVT_ID.Reg, volatile.LoadUint32(&o.CH9_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH9_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH9_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH9_TASK_ID: channel9 task id register +func (o *SOC_ETM_Type) SetCH9_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH9_TASK_ID.Reg, volatile.LoadUint32(&o.CH9_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH9_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH9_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH10_EVT_ID: channel10 event id register +func (o *SOC_ETM_Type) SetCH10_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH10_EVT_ID.Reg, volatile.LoadUint32(&o.CH10_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH10_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH10_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH10_TASK_ID: channel10 task id register +func (o *SOC_ETM_Type) SetCH10_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH10_TASK_ID.Reg, volatile.LoadUint32(&o.CH10_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH10_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH10_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH11_EVT_ID: channel11 event id register +func (o *SOC_ETM_Type) SetCH11_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH11_EVT_ID.Reg, volatile.LoadUint32(&o.CH11_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH11_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH11_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH11_TASK_ID: channel11 task id register +func (o *SOC_ETM_Type) SetCH11_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH11_TASK_ID.Reg, volatile.LoadUint32(&o.CH11_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH11_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH11_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH12_EVT_ID: channel12 event id register +func (o *SOC_ETM_Type) SetCH12_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH12_EVT_ID.Reg, volatile.LoadUint32(&o.CH12_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH12_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH12_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH12_TASK_ID: channel12 task id register +func (o *SOC_ETM_Type) SetCH12_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH12_TASK_ID.Reg, volatile.LoadUint32(&o.CH12_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH12_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH12_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH13_EVT_ID: channel13 event id register +func (o *SOC_ETM_Type) SetCH13_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH13_EVT_ID.Reg, volatile.LoadUint32(&o.CH13_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH13_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH13_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH13_TASK_ID: channel13 task id register +func (o *SOC_ETM_Type) SetCH13_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH13_TASK_ID.Reg, volatile.LoadUint32(&o.CH13_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH13_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH13_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH14_EVT_ID: channel14 event id register +func (o *SOC_ETM_Type) SetCH14_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH14_EVT_ID.Reg, volatile.LoadUint32(&o.CH14_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH14_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH14_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH14_TASK_ID: channel14 task id register +func (o *SOC_ETM_Type) SetCH14_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH14_TASK_ID.Reg, volatile.LoadUint32(&o.CH14_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH14_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH14_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH15_EVT_ID: channel15 event id register +func (o *SOC_ETM_Type) SetCH15_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH15_EVT_ID.Reg, volatile.LoadUint32(&o.CH15_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH15_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH15_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH15_TASK_ID: channel15 task id register +func (o *SOC_ETM_Type) SetCH15_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH15_TASK_ID.Reg, volatile.LoadUint32(&o.CH15_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH15_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH15_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH16_EVT_ID: channel16 event id register +func (o *SOC_ETM_Type) SetCH16_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH16_EVT_ID.Reg, volatile.LoadUint32(&o.CH16_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH16_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH16_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH16_TASK_ID: channel16 task id register +func (o *SOC_ETM_Type) SetCH16_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH16_TASK_ID.Reg, volatile.LoadUint32(&o.CH16_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH16_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH16_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH17_EVT_ID: channel17 event id register +func (o *SOC_ETM_Type) SetCH17_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH17_EVT_ID.Reg, volatile.LoadUint32(&o.CH17_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH17_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH17_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH17_TASK_ID: channel17 task id register +func (o *SOC_ETM_Type) SetCH17_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH17_TASK_ID.Reg, volatile.LoadUint32(&o.CH17_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH17_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH17_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH18_EVT_ID: channel18 event id register +func (o *SOC_ETM_Type) SetCH18_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH18_EVT_ID.Reg, volatile.LoadUint32(&o.CH18_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH18_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH18_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH18_TASK_ID: channel18 task id register +func (o *SOC_ETM_Type) SetCH18_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH18_TASK_ID.Reg, volatile.LoadUint32(&o.CH18_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH18_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH18_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH19_EVT_ID: channel19 event id register +func (o *SOC_ETM_Type) SetCH19_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH19_EVT_ID.Reg, volatile.LoadUint32(&o.CH19_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH19_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH19_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH19_TASK_ID: channel19 task id register +func (o *SOC_ETM_Type) SetCH19_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH19_TASK_ID.Reg, volatile.LoadUint32(&o.CH19_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH19_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH19_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH20_EVT_ID: channel20 event id register +func (o *SOC_ETM_Type) SetCH20_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH20_EVT_ID.Reg, volatile.LoadUint32(&o.CH20_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH20_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH20_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH20_TASK_ID: channel20 task id register +func (o *SOC_ETM_Type) SetCH20_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH20_TASK_ID.Reg, volatile.LoadUint32(&o.CH20_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH20_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH20_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH21_EVT_ID: channel21 event id register +func (o *SOC_ETM_Type) SetCH21_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH21_EVT_ID.Reg, volatile.LoadUint32(&o.CH21_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH21_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH21_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH21_TASK_ID: channel21 task id register +func (o *SOC_ETM_Type) SetCH21_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH21_TASK_ID.Reg, volatile.LoadUint32(&o.CH21_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH21_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH21_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH22_EVT_ID: channel22 event id register +func (o *SOC_ETM_Type) SetCH22_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH22_EVT_ID.Reg, volatile.LoadUint32(&o.CH22_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH22_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH22_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH22_TASK_ID: channel22 task id register +func (o *SOC_ETM_Type) SetCH22_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH22_TASK_ID.Reg, volatile.LoadUint32(&o.CH22_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH22_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH22_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH23_EVT_ID: channel23 event id register +func (o *SOC_ETM_Type) SetCH23_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH23_EVT_ID.Reg, volatile.LoadUint32(&o.CH23_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH23_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH23_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH23_TASK_ID: channel23 task id register +func (o *SOC_ETM_Type) SetCH23_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH23_TASK_ID.Reg, volatile.LoadUint32(&o.CH23_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH23_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH23_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH24_EVT_ID: channel24 event id register +func (o *SOC_ETM_Type) SetCH24_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH24_EVT_ID.Reg, volatile.LoadUint32(&o.CH24_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH24_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH24_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH24_TASK_ID: channel24 task id register +func (o *SOC_ETM_Type) SetCH24_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH24_TASK_ID.Reg, volatile.LoadUint32(&o.CH24_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH24_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH24_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH25_EVT_ID: channel25 event id register +func (o *SOC_ETM_Type) SetCH25_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH25_EVT_ID.Reg, volatile.LoadUint32(&o.CH25_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH25_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH25_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH25_TASK_ID: channel25 task id register +func (o *SOC_ETM_Type) SetCH25_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH25_TASK_ID.Reg, volatile.LoadUint32(&o.CH25_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH25_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH25_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH26_EVT_ID: channel26 event id register +func (o *SOC_ETM_Type) SetCH26_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH26_EVT_ID.Reg, volatile.LoadUint32(&o.CH26_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH26_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH26_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH26_TASK_ID: channel26 task id register +func (o *SOC_ETM_Type) SetCH26_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH26_TASK_ID.Reg, volatile.LoadUint32(&o.CH26_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH26_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH26_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH27_EVT_ID: channel27 event id register +func (o *SOC_ETM_Type) SetCH27_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH27_EVT_ID.Reg, volatile.LoadUint32(&o.CH27_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH27_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH27_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH27_TASK_ID: channel27 task id register +func (o *SOC_ETM_Type) SetCH27_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH27_TASK_ID.Reg, volatile.LoadUint32(&o.CH27_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH27_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH27_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH28_EVT_ID: channel28 event id register +func (o *SOC_ETM_Type) SetCH28_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH28_EVT_ID.Reg, volatile.LoadUint32(&o.CH28_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH28_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH28_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH28_TASK_ID: channel28 task id register +func (o *SOC_ETM_Type) SetCH28_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH28_TASK_ID.Reg, volatile.LoadUint32(&o.CH28_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH28_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH28_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH29_EVT_ID: channel29 event id register +func (o *SOC_ETM_Type) SetCH29_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH29_EVT_ID.Reg, volatile.LoadUint32(&o.CH29_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH29_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH29_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH29_TASK_ID: channel29 task id register +func (o *SOC_ETM_Type) SetCH29_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH29_TASK_ID.Reg, volatile.LoadUint32(&o.CH29_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH29_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH29_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH30_EVT_ID: channel30 event id register +func (o *SOC_ETM_Type) SetCH30_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH30_EVT_ID.Reg, volatile.LoadUint32(&o.CH30_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH30_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH30_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH30_TASK_ID: channel30 task id register +func (o *SOC_ETM_Type) SetCH30_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH30_TASK_ID.Reg, volatile.LoadUint32(&o.CH30_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH30_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH30_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH31_EVT_ID: channel31 event id register +func (o *SOC_ETM_Type) SetCH31_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH31_EVT_ID.Reg, volatile.LoadUint32(&o.CH31_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH31_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH31_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH31_TASK_ID: channel31 task id register +func (o *SOC_ETM_Type) SetCH31_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH31_TASK_ID.Reg, volatile.LoadUint32(&o.CH31_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH31_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH31_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH32_EVT_ID: channel32 event id register +func (o *SOC_ETM_Type) SetCH32_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH32_EVT_ID.Reg, volatile.LoadUint32(&o.CH32_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH32_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH32_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH32_TASK_ID: channel32 task id register +func (o *SOC_ETM_Type) SetCH32_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH32_TASK_ID.Reg, volatile.LoadUint32(&o.CH32_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH32_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH32_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH33_EVT_ID: channel33 event id register +func (o *SOC_ETM_Type) SetCH33_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH33_EVT_ID.Reg, volatile.LoadUint32(&o.CH33_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH33_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH33_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH33_TASK_ID: channel33 task id register +func (o *SOC_ETM_Type) SetCH33_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH33_TASK_ID.Reg, volatile.LoadUint32(&o.CH33_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH33_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH33_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH34_EVT_ID: channel34 event id register +func (o *SOC_ETM_Type) SetCH34_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH34_EVT_ID.Reg, volatile.LoadUint32(&o.CH34_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH34_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH34_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH34_TASK_ID: channel34 task id register +func (o *SOC_ETM_Type) SetCH34_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH34_TASK_ID.Reg, volatile.LoadUint32(&o.CH34_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH34_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH34_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH35_EVT_ID: channel35 event id register +func (o *SOC_ETM_Type) SetCH35_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH35_EVT_ID.Reg, volatile.LoadUint32(&o.CH35_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH35_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH35_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH35_TASK_ID: channel35 task id register +func (o *SOC_ETM_Type) SetCH35_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH35_TASK_ID.Reg, volatile.LoadUint32(&o.CH35_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH35_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH35_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH36_EVT_ID: channel36 event id register +func (o *SOC_ETM_Type) SetCH36_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH36_EVT_ID.Reg, volatile.LoadUint32(&o.CH36_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH36_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH36_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH36_TASK_ID: channel36 task id register +func (o *SOC_ETM_Type) SetCH36_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH36_TASK_ID.Reg, volatile.LoadUint32(&o.CH36_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH36_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH36_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH37_EVT_ID: channel37 event id register +func (o *SOC_ETM_Type) SetCH37_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH37_EVT_ID.Reg, volatile.LoadUint32(&o.CH37_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH37_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH37_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH37_TASK_ID: channel37 task id register +func (o *SOC_ETM_Type) SetCH37_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH37_TASK_ID.Reg, volatile.LoadUint32(&o.CH37_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH37_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH37_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH38_EVT_ID: channel38 event id register +func (o *SOC_ETM_Type) SetCH38_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH38_EVT_ID.Reg, volatile.LoadUint32(&o.CH38_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH38_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH38_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH38_TASK_ID: channel38 task id register +func (o *SOC_ETM_Type) SetCH38_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH38_TASK_ID.Reg, volatile.LoadUint32(&o.CH38_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH38_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH38_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH39_EVT_ID: channel39 event id register +func (o *SOC_ETM_Type) SetCH39_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH39_EVT_ID.Reg, volatile.LoadUint32(&o.CH39_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH39_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH39_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH39_TASK_ID: channel39 task id register +func (o *SOC_ETM_Type) SetCH39_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH39_TASK_ID.Reg, volatile.LoadUint32(&o.CH39_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH39_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH39_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH40_EVT_ID: channel40 event id register +func (o *SOC_ETM_Type) SetCH40_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH40_EVT_ID.Reg, volatile.LoadUint32(&o.CH40_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH40_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH40_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH40_TASK_ID: channel40 task id register +func (o *SOC_ETM_Type) SetCH40_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH40_TASK_ID.Reg, volatile.LoadUint32(&o.CH40_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH40_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH40_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH41_EVT_ID: channel41 event id register +func (o *SOC_ETM_Type) SetCH41_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH41_EVT_ID.Reg, volatile.LoadUint32(&o.CH41_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH41_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH41_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH41_TASK_ID: channel41 task id register +func (o *SOC_ETM_Type) SetCH41_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH41_TASK_ID.Reg, volatile.LoadUint32(&o.CH41_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH41_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH41_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH42_EVT_ID: channel42 event id register +func (o *SOC_ETM_Type) SetCH42_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH42_EVT_ID.Reg, volatile.LoadUint32(&o.CH42_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH42_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH42_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH42_TASK_ID: channel42 task id register +func (o *SOC_ETM_Type) SetCH42_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH42_TASK_ID.Reg, volatile.LoadUint32(&o.CH42_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH42_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH42_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH43_EVT_ID: channel43 event id register +func (o *SOC_ETM_Type) SetCH43_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH43_EVT_ID.Reg, volatile.LoadUint32(&o.CH43_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH43_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH43_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH43_TASK_ID: channel43 task id register +func (o *SOC_ETM_Type) SetCH43_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH43_TASK_ID.Reg, volatile.LoadUint32(&o.CH43_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH43_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH43_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH44_EVT_ID: channel44 event id register +func (o *SOC_ETM_Type) SetCH44_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH44_EVT_ID.Reg, volatile.LoadUint32(&o.CH44_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH44_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH44_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH44_TASK_ID: channel44 task id register +func (o *SOC_ETM_Type) SetCH44_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH44_TASK_ID.Reg, volatile.LoadUint32(&o.CH44_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH44_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH44_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH45_EVT_ID: channel45 event id register +func (o *SOC_ETM_Type) SetCH45_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH45_EVT_ID.Reg, volatile.LoadUint32(&o.CH45_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH45_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH45_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH45_TASK_ID: channel45 task id register +func (o *SOC_ETM_Type) SetCH45_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH45_TASK_ID.Reg, volatile.LoadUint32(&o.CH45_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH45_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH45_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH46_EVT_ID: channel46 event id register +func (o *SOC_ETM_Type) SetCH46_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH46_EVT_ID.Reg, volatile.LoadUint32(&o.CH46_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH46_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH46_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH46_TASK_ID: channel46 task id register +func (o *SOC_ETM_Type) SetCH46_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH46_TASK_ID.Reg, volatile.LoadUint32(&o.CH46_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH46_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH46_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH47_EVT_ID: channel47 event id register +func (o *SOC_ETM_Type) SetCH47_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH47_EVT_ID.Reg, volatile.LoadUint32(&o.CH47_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH47_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH47_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH47_TASK_ID: channel47 task id register +func (o *SOC_ETM_Type) SetCH47_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH47_TASK_ID.Reg, volatile.LoadUint32(&o.CH47_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH47_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH47_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH48_EVT_ID: channel48 event id register +func (o *SOC_ETM_Type) SetCH48_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH48_EVT_ID.Reg, volatile.LoadUint32(&o.CH48_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH48_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH48_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH48_TASK_ID: channel48 task id register +func (o *SOC_ETM_Type) SetCH48_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH48_TASK_ID.Reg, volatile.LoadUint32(&o.CH48_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH48_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH48_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH49_EVT_ID: channel49 event id register +func (o *SOC_ETM_Type) SetCH49_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH49_EVT_ID.Reg, volatile.LoadUint32(&o.CH49_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH49_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH49_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH49_TASK_ID: channel49 task id register +func (o *SOC_ETM_Type) SetCH49_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH49_TASK_ID.Reg, volatile.LoadUint32(&o.CH49_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH49_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH49_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CLK_EN: etm clock enable register +func (o *SOC_ETM_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1 +} + +// SOC_ETM.DATE: etm date register +func (o *SOC_ETM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SOC_ETM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 0 +type SPI0_Type struct { + SPI_MEM_CMD volatile.Register32 // 0x0 + _ [4]byte + SPI_MEM_CTRL volatile.Register32 // 0x8 + SPI_MEM_CTRL1 volatile.Register32 // 0xC + SPI_MEM_CTRL2 volatile.Register32 // 0x10 + SPI_MEM_CLOCK volatile.Register32 // 0x14 + SPI_MEM_USER volatile.Register32 // 0x18 + SPI_MEM_USER1 volatile.Register32 // 0x1C + SPI_MEM_USER2 volatile.Register32 // 0x20 + _ [8]byte + SPI_MEM_RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + SPI_MEM_MISC volatile.Register32 // 0x34 + _ [4]byte + SPI_MEM_CACHE_FCTRL volatile.Register32 // 0x3C + SPI_MEM_CACHE_SCTRL volatile.Register32 // 0x40 + SPI_MEM_SRAM_CMD volatile.Register32 // 0x44 + SPI_MEM_SRAM_DRD_CMD volatile.Register32 // 0x48 + SPI_MEM_SRAM_DWR_CMD volatile.Register32 // 0x4C + SPI_MEM_SRAM_CLK volatile.Register32 // 0x50 + SPI_MEM_FSM volatile.Register32 // 0x54 + _ [104]byte + SPI_MEM_INT_ENA volatile.Register32 // 0xC0 + SPI_MEM_INT_CLR volatile.Register32 // 0xC4 + SPI_MEM_INT_RAW volatile.Register32 // 0xC8 + SPI_MEM_INT_ST volatile.Register32 // 0xCC + _ [4]byte + SPI_MEM_DDR volatile.Register32 // 0xD4 + SPI_SMEM_DDR volatile.Register32 // 0xD8 + _ [36]byte + SPI_FMEM_PMS0_ATTR volatile.Register32 // 0x100 + SPI_FMEM_PMS1_ATTR volatile.Register32 // 0x104 + SPI_FMEM_PMS2_ATTR volatile.Register32 // 0x108 + SPI_FMEM_PMS3_ATTR volatile.Register32 // 0x10C + SPI_FMEM_PMS0_ADDR volatile.Register32 // 0x110 + SPI_FMEM_PMS1_ADDR volatile.Register32 // 0x114 + SPI_FMEM_PMS2_ADDR volatile.Register32 // 0x118 + SPI_FMEM_PMS3_ADDR volatile.Register32 // 0x11C + SPI_FMEM_PMS0_SIZE volatile.Register32 // 0x120 + SPI_FMEM_PMS1_SIZE volatile.Register32 // 0x124 + SPI_FMEM_PMS2_SIZE volatile.Register32 // 0x128 + SPI_FMEM_PMS3_SIZE volatile.Register32 // 0x12C + SPI_SMEM_PMS0_ATTR volatile.Register32 // 0x130 + SPI_SMEM_PMS1_ATTR volatile.Register32 // 0x134 + SPI_SMEM_PMS2_ATTR volatile.Register32 // 0x138 + SPI_SMEM_PMS3_ATTR volatile.Register32 // 0x13C + SPI_SMEM_PMS0_ADDR volatile.Register32 // 0x140 + SPI_SMEM_PMS1_ADDR volatile.Register32 // 0x144 + SPI_SMEM_PMS2_ADDR volatile.Register32 // 0x148 + SPI_SMEM_PMS3_ADDR volatile.Register32 // 0x14C + SPI_SMEM_PMS0_SIZE volatile.Register32 // 0x150 + SPI_SMEM_PMS1_SIZE volatile.Register32 // 0x154 + SPI_SMEM_PMS2_SIZE volatile.Register32 // 0x158 + SPI_SMEM_PMS3_SIZE volatile.Register32 // 0x15C + _ [4]byte + SPI_MEM_PMS_REJECT volatile.Register32 // 0x164 + SPI_MEM_ECC_CTRL volatile.Register32 // 0x168 + SPI_MEM_ECC_ERR_ADDR volatile.Register32 // 0x16C + SPI_MEM_AXI_ERR_ADDR volatile.Register32 // 0x170 + SPI_SMEM_ECC_CTRL volatile.Register32 // 0x174 + _ [8]byte + SPI_MEM_TIMING_CALI volatile.Register32 // 0x180 + SPI_MEM_DIN_MODE volatile.Register32 // 0x184 + SPI_MEM_DIN_NUM volatile.Register32 // 0x188 + SPI_MEM_DOUT_MODE volatile.Register32 // 0x18C + SPI_SMEM_TIMING_CALI volatile.Register32 // 0x190 + SPI_SMEM_DIN_MODE volatile.Register32 // 0x194 + SPI_SMEM_DIN_NUM volatile.Register32 // 0x198 + SPI_SMEM_DOUT_MODE volatile.Register32 // 0x19C + SPI_SMEM_AC volatile.Register32 // 0x1A0 + _ [92]byte + SPI_MEM_CLOCK_GATE volatile.Register32 // 0x200 + _ [252]byte + SPI_MEM_XTS_PLAIN_BASE volatile.Register32 // 0x300 + _ [60]byte + SPI_MEM_XTS_LINESIZE volatile.Register32 // 0x340 + SPI_MEM_XTS_DESTINATION volatile.Register32 // 0x344 + SPI_MEM_XTS_PHYSICAL_ADDRESS volatile.Register32 // 0x348 + SPI_MEM_XTS_TRIGGER volatile.Register32 // 0x34C + SPI_MEM_XTS_RELEASE volatile.Register32 // 0x350 + SPI_MEM_XTS_DESTROY volatile.Register32 // 0x354 + SPI_MEM_XTS_STATE volatile.Register32 // 0x358 + SPI_MEM_XTS_DATE volatile.Register32 // 0x35C + _ [28]byte + SPI_MEM_MMU_ITEM_CONTENT volatile.Register32 // 0x37C + SPI_MEM_MMU_ITEM_INDEX volatile.Register32 // 0x380 + SPI_MEM_MMU_POWER_CTRL volatile.Register32 // 0x384 + SPI_MEM_DPA_CTRL volatile.Register32 // 0x388 + _ [100]byte + SPI_MEM_REGISTERRND_ECO_HIGH volatile.Register32 // 0x3F0 + SPI_MEM_REGISTERRND_ECO_LOW volatile.Register32 // 0x3F4 + _ [4]byte + SPI_MEM_DATE volatile.Register32 // 0x3FC +} + +// SPI0.SPI_MEM_CMD: SPI0 FSM status register +func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_MST_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_MST_ST() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf +} +func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_SLV_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf0)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_SLV_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf0) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_USR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000) >> 18 +} + +// SPI0.SPI_MEM_CTRL: SPI0 control register. +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_Q_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_Q_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_D_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_D_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CTRL1: SPI0 control1 register. +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x400000) >> 22 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RAM0_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RAM0_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CTRL2: SPI0 control2 register. +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1f)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1f +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x3e0)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x3e0) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1c00)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1c00) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x7e000000) >> 25 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CLOCK: SPI clock division control register. +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff +} +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_USER: SPI0 user register. +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x20000000) >> 29 +} + +// SPI0.SPI_MEM_USER1: SPI0 user1 register. +func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x3f)|value) +} +func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x3f +} +func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI0.SPI_MEM_USER2: SPI0 user2 register. +func (o *SPI0_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SPI_MEM_RD_STATUS: SPI0 read control register. +func (o *SPI0_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI0.SPI_MEM_MISC: SPI0 misc register +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_FSUB_PIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_FSUB_PIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_SSUB_PIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_SSUB_PIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x400) >> 10 +} + +// SPI0.SPI_MEM_CACHE_FCTRL: SPI0 bit mode control register. +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CACHE_SCTRL: SPI0 external RAM control register +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc00000)|value<<22) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc00000) >> 22 +} + +// SPI0.SPI_MEM_SRAM_CMD: SPI0 external RAM mode control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x3fc)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x3fc) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x400) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x800)|value<<11) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x800) >> 11 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x8000)|value<<15) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x8000) >> 15 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_SRAM_DRD_CMD: SPI0 external RAM DDR read command control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SPI_MEM_SRAM_DWR_CMD: SPI0 external RAM DDR write command control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SPI_MEM_SRAM_CLK: SPI0 external RAM clock control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_FSM: SPI0 FSM status register +func (o *SPI0_Type) SetSPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FSM.Reg, volatile.LoadUint32(&o.SPI_MEM_FSM.Reg)&^(0xf80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FSM.Reg) & 0xf80) >> 7 +} + +// SPI0.SPI_MEM_INT_ENA: SPI0 interrupt enable register +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x200) >> 9 +} + +// SPI0.SPI_MEM_INT_CLR: SPI0 interrupt clear register +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x200) >> 9 +} + +// SPI0.SPI_MEM_INT_RAW: SPI0 interrupt raw register +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x200) >> 9 +} + +// SPI0.SPI_MEM_INT_ST: SPI0 interrupt status register +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x200) >> 9 +} + +// SPI0.SPI_MEM_DDR: SPI0 flash DDR mode control register +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI0.SPI_SMEM_DDR: SPI0 external RAM DDR mode control register +func (o *SPI0_Type) SetSPI_SMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI0.SPI_FMEM_PMS0_ATTR: MSPI flash ACE section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS1_ATTR: MSPI flash ACE section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS2_ATTR: MSPI flash ACE section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS3_ATTR: MSPI flash ACE section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS0_ADDR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS0_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_FMEM_PMS1_ADDR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS1_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_FMEM_PMS2_ADDR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS2_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_FMEM_PMS3_ADDR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS3_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_FMEM_PMS0_SIZE: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS0_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS0_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_FMEM_PMS1_SIZE: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS1_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS1_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_FMEM_PMS2_SIZE: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS2_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS2_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_FMEM_PMS3_SIZE: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS3_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS3_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_SMEM_PMS0_ATTR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS1_ATTR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS2_ATTR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS3_ATTR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS0_ADDR: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS0_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_SMEM_PMS1_ADDR: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS1_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_SMEM_PMS2_ADDR: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS2_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_SMEM_PMS3_ADDR: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS3_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_SMEM_PMS0_SIZE: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS0_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS0_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_SMEM_PMS1_SIZE: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS1_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS1_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_SMEM_PMS2_SIZE: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS2_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS2_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_SMEM_PMS3_SIZE: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS3_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS3_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_MEM_PMS_REJECT: SPI1 access reject register +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x3ffffff +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PM_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PM_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_ECC_CTRL: MSPI ECC control register +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x1f800)|value<<11) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x1f800) >> 11 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0xc0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0xc0000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0xfe000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0xfe000000) >> 25 +} + +// SPI0.SPI_MEM_ECC_ERR_ADDR: MSPI ECC error address register +func (o *SPI0_Type) SetSPI_MEM_ECC_ERR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_ERR_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg) & 0x3ffffff +} +func (o *SPI0_Type) SetSPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg) & 0xfc000000) >> 26 +} + +// SPI0.SPI_MEM_AXI_ERR_ADDR: SPI0 AXI request error address. +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x3ffffff +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_SMEM_ECC_CTRL: MSPI ECC control register +func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0xc0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0xc0000) >> 18 +} +func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0x100000) >> 20 +} + +// SPI0.SPI_MEM_TIMING_CALI: SPI0 flash timing calibration register +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_UPDATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_UPDATE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x40) >> 6 +} + +// SPI0.SPI_MEM_DIN_MODE: MSPI flash input timing delay mode control register +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7000000) >> 24 +} + +// SPI0.SPI_MEM_DIN_NUM: MSPI flash input timing delay number control register +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x30000) >> 16 +} + +// SPI0.SPI_MEM_DOUT_MODE: MSPI flash output timing adjustment control register +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI0.SPI_SMEM_TIMING_CALI: MSPI external RAM timing calibration register +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x20) >> 5 +} + +// SPI0.SPI_SMEM_DIN_MODE: MSPI external RAM input timing delay mode control register +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000000) >> 24 +} + +// SPI0.SPI_SMEM_DIN_NUM: MSPI external RAM input timing delay number control register +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc000) >> 14 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30000) >> 16 +} + +// SPI0.SPI_SMEM_DOUT_MODE: MSPI external RAM output timing adjustment control register +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI0.SPI_SMEM_AC: MSPI external RAM ECC and SPI CS timing control register +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7c)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7c) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0xf80)|value<<7) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0xf80) >> 7 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x8000)|value<<15) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x8000) >> 15 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7e000000) >> 25 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CLOCK_GATE: SPI0 clock gate register +func (o *SPI0_Type) SetSPI_MEM_CLOCK_GATE_SPI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK_GATE.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_GATE_SPI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_PLAIN_BASE: The base address of the memory that stores plaintext in Manual Encryption +func (o *SPI0_Type) SetSPI_MEM_XTS_PLAIN_BASE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_PLAIN_BASE.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_PLAIN_BASE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_PLAIN_BASE.Reg) +} + +// SPI0.SPI_MEM_XTS_LINESIZE: Manual Encryption Line-Size register +func (o *SPI0_Type) SetSPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_LINESIZE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_LINESIZE.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_LINESIZE.Reg) & 0x3 +} + +// SPI0.SPI_MEM_XTS_DESTINATION: Manual Encryption destination register +func (o *SPI0_Type) SetSPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_DESTINATION.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DESTINATION.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_DESTINATION.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_PHYSICAL_ADDRESS: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg) & 0x3ffffff +} + +// SPI0.SPI_MEM_XTS_TRIGGER: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_TRIGGER.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_TRIGGER.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_TRIGGER.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_RELEASE: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_RELEASE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_RELEASE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_RELEASE.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_DESTROY: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_DESTROY.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DESTROY.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_DESTROY.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_STATE: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_STATE_SPI_XTS_STATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_STATE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_STATE.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_STATE_SPI_XTS_STATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_STATE.Reg) & 0x3 +} + +// SPI0.SPI_MEM_XTS_DATE: Manual Encryption version register +func (o *SPI0_Type) SetSPI_MEM_XTS_DATE_SPI_XTS_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_DATE_SPI_XTS_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_DATE.Reg) & 0x3fffffff +} + +// SPI0.SPI_MEM_MMU_ITEM_CONTENT: MSPI-MMU item content register +func (o *SPI0_Type) SetSPI_MEM_MMU_ITEM_CONTENT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_ITEM_CONTENT.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_ITEM_CONTENT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MMU_ITEM_CONTENT.Reg) +} + +// SPI0.SPI_MEM_MMU_ITEM_INDEX: MSPI-MMU item index register +func (o *SPI0_Type) SetSPI_MEM_MMU_ITEM_INDEX(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_ITEM_INDEX.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_ITEM_INDEX() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MMU_ITEM_INDEX.Reg) +} + +// SPI0.SPI_MEM_MMU_POWER_CTRL: MSPI MMU power control register +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x18) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x3fff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x3fff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_DPA_CTRL: SPI memory cryption DPA register +func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x10) >> 4 +} + +// SPI0.SPI_MEM_REGISTERRND_ECO_HIGH: MSPI ECO high register +func (o *SPI0_Type) SetSPI_MEM_REGISTERRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REGISTERRND_ECO_HIGH.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_REGISTERRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REGISTERRND_ECO_HIGH.Reg) +} + +// SPI0.SPI_MEM_REGISTERRND_ECO_LOW: MSPI ECO low register +func (o *SPI0_Type) SetSPI_MEM_REGISTERRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REGISTERRND_ECO_LOW.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_REGISTERRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REGISTERRND_ECO_LOW.Reg) +} + +// SPI0.SPI_MEM_DATE: SPI0 version control register +func (o *SPI0_Type) SetSPI_MEM_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 1 +type SPI1_Type struct { + SPI_MEM_CMD volatile.Register32 // 0x0 + SPI_MEM_ADDR volatile.Register32 // 0x4 + SPI_MEM_CTRL volatile.Register32 // 0x8 + SPI_MEM_CTRL1 volatile.Register32 // 0xC + SPI_MEM_CTRL2 volatile.Register32 // 0x10 + SPI_MEM_CLOCK volatile.Register32 // 0x14 + SPI_MEM_USER volatile.Register32 // 0x18 + SPI_MEM_USER1 volatile.Register32 // 0x1C + SPI_MEM_USER2 volatile.Register32 // 0x20 + SPI_MEM_MOSI_DLEN volatile.Register32 // 0x24 + SPI_MEM_MISO_DLEN volatile.Register32 // 0x28 + SPI_MEM_RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + SPI_MEM_MISC volatile.Register32 // 0x34 + SPI_MEM_TX_CRC volatile.Register32 // 0x38 + SPI_MEM_CACHE_FCTRL volatile.Register32 // 0x3C + _ [24]byte + SPI_MEM_W0 volatile.Register32 // 0x58 + SPI_MEM_W1 volatile.Register32 // 0x5C + SPI_MEM_W2 volatile.Register32 // 0x60 + SPI_MEM_W3 volatile.Register32 // 0x64 + SPI_MEM_W4 volatile.Register32 // 0x68 + SPI_MEM_W5 volatile.Register32 // 0x6C + SPI_MEM_W6 volatile.Register32 // 0x70 + SPI_MEM_W7 volatile.Register32 // 0x74 + SPI_MEM_W8 volatile.Register32 // 0x78 + SPI_MEM_W9 volatile.Register32 // 0x7C + SPI_MEM_W10 volatile.Register32 // 0x80 + SPI_MEM_W11 volatile.Register32 // 0x84 + SPI_MEM_W12 volatile.Register32 // 0x88 + SPI_MEM_W13 volatile.Register32 // 0x8C + SPI_MEM_W14 volatile.Register32 // 0x90 + SPI_MEM_W15 volatile.Register32 // 0x94 + SPI_MEM_FLASH_WAITI_CTRL volatile.Register32 // 0x98 + SPI_MEM_FLASH_SUS_CTRL volatile.Register32 // 0x9C + SPI_MEM_FLASH_SUS_CMD volatile.Register32 // 0xA0 + SPI_MEM_SUS_STATUS volatile.Register32 // 0xA4 + _ [24]byte + SPI_MEM_INT_ENA volatile.Register32 // 0xC0 + SPI_MEM_INT_CLR volatile.Register32 // 0xC4 + SPI_MEM_INT_RAW volatile.Register32 // 0xC8 + SPI_MEM_INT_ST volatile.Register32 // 0xCC + _ [4]byte + SPI_MEM_DDR volatile.Register32 // 0xD4 + _ [168]byte + SPI_MEM_TIMING_CALI volatile.Register32 // 0x180 + _ [124]byte + SPI_MEM_CLOCK_GATE volatile.Register32 // 0x200 + _ [504]byte + SPI_MEM_DATE volatile.Register32 // 0x3FC +} + +// SPI1.SPI_MEM_CMD: SPI1 memory command register +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_MST_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_MST_ST() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_SLV_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf0)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_SLV_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf0) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_PE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_PE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_USR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_HPM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_HPM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_DP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_DP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_CE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_CE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_BE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_BE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_SE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_SE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_PP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_PP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WRSR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WRSR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RDSR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RDSR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RDID(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RDID() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WRDI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WRDI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WREN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WREN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_READ(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_READ() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_ADDR: SPI1 address register +func (o *SPI1_Type) SetSPI_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ADDR.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_ADDR.Reg) +} + +// SPI1.SPI_MEM_CTRL: SPI1 control register. +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_TX_CRC_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_TX_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800) >> 11 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_RESANDRES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_RESANDRES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_Q_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_Q_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_D_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_D_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_WP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_WP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_WRSR_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_WRSR_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1000000) >> 24 +} + +// SPI1.SPI_MEM_CTRL1: SPI1 control1 register. +func (o *SPI1_Type) SetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x3 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0xffc)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0xffc) >> 2 +} + +// SPI1.SPI_MEM_CTRL2: SPI1 control2 register. +func (o *SPI1_Type) SetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_CLOCK: SPI1 clock division control register. +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff +} +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_USER: SPI1 user register. +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x1000) >> 12 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MISO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_USER1: SPI1 user1 register. +func (o *SPI1_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x3f)|value) +} +func (o *SPI1_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x3f +} +func (o *SPI1_Type) SetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI1.SPI_MEM_USER2: SPI1 user2 register. +func (o *SPI1_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI1.SPI_MEM_MOSI_DLEN: SPI1 send data bit length control register. +func (o *SPI1_Type) SetSPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MOSI_DLEN.Reg, volatile.LoadUint32(&o.SPI_MEM_MOSI_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MOSI_DLEN.Reg) & 0x3ff +} + +// SPI1.SPI_MEM_MISO_DLEN: SPI1 receive data bit length control register. +func (o *SPI1_Type) SetSPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISO_DLEN.Reg, volatile.LoadUint32(&o.SPI_MEM_MISO_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MISO_DLEN.Reg) & 0x3ff +} + +// SPI1.SPI_MEM_RD_STATUS: SPI1 status register. +func (o *SPI1_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_STATUS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_STATUS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI1.SPI_MEM_MISC: SPI1 misc register +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_TX_CRC: SPI1 TX CRC data register. +func (o *SPI1_Type) SetSPI_MEM_TX_CRC(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TX_CRC.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_TX_CRC() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_TX_CRC.Reg) +} + +// SPI1.SPI_MEM_CACHE_FCTRL: SPI1 bit mode control register. +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x100) >> 8 +} + +// SPI1.SPI_MEM_W0: SPI1 memory data buffer0 +func (o *SPI1_Type) SetSPI_MEM_W0(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W0.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W0() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W0.Reg) +} + +// SPI1.SPI_MEM_W1: SPI1 memory data buffer1 +func (o *SPI1_Type) SetSPI_MEM_W1(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W1.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W1() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W1.Reg) +} + +// SPI1.SPI_MEM_W2: SPI1 memory data buffer2 +func (o *SPI1_Type) SetSPI_MEM_W2(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W2.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W2() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W2.Reg) +} + +// SPI1.SPI_MEM_W3: SPI1 memory data buffer3 +func (o *SPI1_Type) SetSPI_MEM_W3(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W3.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W3() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W3.Reg) +} + +// SPI1.SPI_MEM_W4: SPI1 memory data buffer4 +func (o *SPI1_Type) SetSPI_MEM_W4(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W4.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W4() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W4.Reg) +} + +// SPI1.SPI_MEM_W5: SPI1 memory data buffer5 +func (o *SPI1_Type) SetSPI_MEM_W5(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W5.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W5() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W5.Reg) +} + +// SPI1.SPI_MEM_W6: SPI1 memory data buffer6 +func (o *SPI1_Type) SetSPI_MEM_W6(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W6.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W6() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W6.Reg) +} + +// SPI1.SPI_MEM_W7: SPI1 memory data buffer7 +func (o *SPI1_Type) SetSPI_MEM_W7(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W7.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W7() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W7.Reg) +} + +// SPI1.SPI_MEM_W8: SPI1 memory data buffer8 +func (o *SPI1_Type) SetSPI_MEM_W8(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W8.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W8() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W8.Reg) +} + +// SPI1.SPI_MEM_W9: SPI1 memory data buffer9 +func (o *SPI1_Type) SetSPI_MEM_W9(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W9.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W9() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W9.Reg) +} + +// SPI1.SPI_MEM_W10: SPI1 memory data buffer10 +func (o *SPI1_Type) SetSPI_MEM_W10(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W10.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W10() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W10.Reg) +} + +// SPI1.SPI_MEM_W11: SPI1 memory data buffer11 +func (o *SPI1_Type) SetSPI_MEM_W11(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W11.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W11() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W11.Reg) +} + +// SPI1.SPI_MEM_W12: SPI1 memory data buffer12 +func (o *SPI1_Type) SetSPI_MEM_W12(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W12.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W12() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W12.Reg) +} + +// SPI1.SPI_MEM_W13: SPI1 memory data buffer13 +func (o *SPI1_Type) SetSPI_MEM_W13(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W13.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W13() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W13.Reg) +} + +// SPI1.SPI_MEM_W14: SPI1 memory data buffer14 +func (o *SPI1_Type) SetSPI_MEM_W14(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W14.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W14() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W14.Reg) +} + +// SPI1.SPI_MEM_W15: SPI1 memory data buffer15 +func (o *SPI1_Type) SetSPI_MEM_W15(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W15.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W15() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W15.Reg) +} + +// SPI1.SPI_MEM_FLASH_WAITI_CTRL: SPI1 wait idle control register +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x18) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0xfc00)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0xfc00) >> 10 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SPI_MEM_FLASH_SUS_CTRL: SPI1 flash suspend control register +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x3fffc0)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x3fffc0) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0xfe000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0xfe000000) >> 25 +} + +// SPI1.SPI_MEM_FLASH_SUS_CMD: SPI1 flash suspend command register +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SPI_MEM_SUS_STATUS: SPI1 flash suspend status register +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SPI_MEM_INT_ENA: SPI1 interrupt enable register +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_INT_CLR: SPI1 interrupt clear register +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_INT_RAW: SPI1 interrupt raw register +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_INT_ST: SPI1 interrupt status register +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_DDR: SPI1 DDR control register +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI1.SPI_MEM_TIMING_CALI: SPI1 timing control register +func (o *SPI1_Type) SetSPI_MEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI1.SPI_MEM_CLOCK_GATE: SPI1 clk_gate register +func (o *SPI1_Type) SetSPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK_GATE.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg) & 0x1 +} + +// SPI1.SPI_MEM_DATE: Version control register +func (o *SPI1_Type) SetSPI_MEM_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 2 +type SPI2_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CLOCK volatile.Register32 // 0xC + USER volatile.Register32 // 0x10 + USER1 volatile.Register32 // 0x14 + USER2 volatile.Register32 // 0x18 + MS_DLEN volatile.Register32 // 0x1C + MISC volatile.Register32 // 0x20 + DIN_MODE volatile.Register32 // 0x24 + DIN_NUM volatile.Register32 // 0x28 + DOUT_MODE volatile.Register32 // 0x2C + DMA_CONF volatile.Register32 // 0x30 + DMA_INT_ENA volatile.Register32 // 0x34 + DMA_INT_CLR volatile.Register32 // 0x38 + DMA_INT_RAW volatile.Register32 // 0x3C + DMA_INT_ST volatile.Register32 // 0x40 + DMA_INT_SET volatile.Register32 // 0x44 + _ [80]byte + W0 volatile.Register32 // 0x98 + W1 volatile.Register32 // 0x9C + W2 volatile.Register32 // 0xA0 + W3 volatile.Register32 // 0xA4 + W4 volatile.Register32 // 0xA8 + W5 volatile.Register32 // 0xAC + W6 volatile.Register32 // 0xB0 + W7 volatile.Register32 // 0xB4 + W8 volatile.Register32 // 0xB8 + W9 volatile.Register32 // 0xBC + W10 volatile.Register32 // 0xC0 + W11 volatile.Register32 // 0xC4 + W12 volatile.Register32 // 0xC8 + W13 volatile.Register32 // 0xCC + W14 volatile.Register32 // 0xD0 + W15 volatile.Register32 // 0xD4 + _ [8]byte + SLAVE volatile.Register32 // 0xE0 + SLAVE1 volatile.Register32 // 0xE4 + CLK_GATE volatile.Register32 // 0xE8 + _ [4]byte + DATE volatile.Register32 // 0xF0 +} + +// SPI2.CMD: Command control register +func (o *SPI2_Type) SetCMD_CONF_BITLEN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetCMD_CONF_BITLEN() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetCMD_UPDATE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetCMD_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} + +// SPI2.ADDR: Address value register +func (o *SPI2_Type) SetADDR(value uint32) { + volatile.StoreUint32(&o.ADDR.Reg, value) +} +func (o *SPI2_Type) GetADDR() uint32 { + return volatile.LoadUint32(&o.ADDR.Reg) +} + +// SPI2.CTRL: SPI control register +func (o *SPI2_Type) SetCTRL_DUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetCTRL_DUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetCTRL_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetCTRL_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetCTRL_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetCTRL_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetCTRL_FREAD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetCTRL_FREAD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetCTRL_HOLD_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetCTRL_HOLD_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetCTRL_WP_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetCTRL_WP_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetCTRL_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1800000)|value<<23) +} +func (o *SPI2_Type) GetCTRL_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1800000) >> 23 +} +func (o *SPI2_Type) SetCTRL_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x6000000)|value<<25) +} +func (o *SPI2_Type) GetCTRL_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x6000000) >> 25 +} + +// SPI2.CLOCK: SPI clock control register +func (o *SPI2_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI2_Type) SetCLOCK_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3c0000)|value<<18) +} +func (o *SPI2_Type) GetCLOCK_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3c0000) >> 18 +} +func (o *SPI2_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER: SPI USER control register +func (o *SPI2_Type) SetUSER_DOUTDIN(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetUSER_DOUTDIN() uint32 { + return volatile.LoadUint32(&o.USER.Reg) & 0x1 +} +func (o *SPI2_Type) SetUSER_QPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetUSER_QPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetUSER_OPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetUSER_OPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetUSER_TSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetUSER_TSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetUSER_RSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetUSER_RSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetUSER_FWRITE_OCT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetUSER_FWRITE_OCT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetUSER_USR_CONF_NXT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetUSER_USR_CONF_NXT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetUSER_SIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetUSER_SIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI2_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER1: SPI USER control register 1 +func (o *SPI2_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xff)|value) +} +func (o *SPI2_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0xff +} +func (o *SPI2_Type) SetUSER1_MST_WFULL_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetUSER1_MST_WFULL_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetUSER1_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3e0000)|value<<17) +} +func (o *SPI2_Type) GetUSER1_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x3e0000) >> 17 +} +func (o *SPI2_Type) SetUSER1_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x7c00000)|value<<22) +} +func (o *SPI2_Type) GetUSER1_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x7c00000) >> 22 +} +func (o *SPI2_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xf8000000) >> 27 +} + +// SPI2.USER2: SPI USER control register 2 +func (o *SPI2_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI2_Type) SetUSER2_MST_REMPTY_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER2_MST_REMPTY_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI2.MS_DLEN: SPI data bit length control register +func (o *SPI2_Type) SetMS_DLEN_MS_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.MS_DLEN.Reg, volatile.LoadUint32(&o.MS_DLEN.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetMS_DLEN_MS_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.MS_DLEN.Reg) & 0x3ffff +} + +// SPI2.MISC: SPI misc register +func (o *SPI2_Type) SetMISC_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetMISC_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.MISC.Reg) & 0x1 +} +func (o *SPI2_Type) SetMISC_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetMISC_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetMISC_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetMISC_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetMISC_CS3_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetMISC_CS3_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetMISC_CS4_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetMISC_CS4_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetMISC_CS5_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetMISC_CS5_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetMISC_CK_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetMISC_CK_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetMISC_MASTER_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1f80)|value<<7) +} +func (o *SPI2_Type) GetMISC_MASTER_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1f80) >> 7 +} +func (o *SPI2_Type) SetMISC_CLK_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetMISC_CLK_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetMISC_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetMISC_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetMISC_ADDR_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetMISC_ADDR_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetMISC_CMD_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetMISC_CMD_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetMISC_SLAVE_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetMISC_SLAVE_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetMISC_DQS_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetMISC_DQS_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetMISC_QUAD_DIN_PIN_SWAP(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetMISC_QUAD_DIN_PIN_SWAP() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000000) >> 31 +} + +// SPI2.DIN_MODE: SPI input delay mode configuration +func (o *SPI2_Type) SetDIN_MODE_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_MODE_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_MODE_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_MODE_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_MODE_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_MODE_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_MODE_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_MODE_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetDIN_MODE_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetDIN_MODE_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetDIN_MODE_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetDIN_MODE_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetDIN_MODE_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetDIN_MODE_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetDIN_MODE_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetDIN_MODE_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc000) >> 14 +} +func (o *SPI2_Type) SetDIN_MODE_TIMING_HCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDIN_MODE_TIMING_HCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x10000) >> 16 +} + +// SPI2.DIN_NUM: SPI input delay number configuration +func (o *SPI2_Type) SetDIN_NUM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_NUM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_NUM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_NUM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_NUM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_NUM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_NUM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_NUM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetDIN_NUM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetDIN_NUM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetDIN_NUM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetDIN_NUM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetDIN_NUM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetDIN_NUM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetDIN_NUM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetDIN_NUM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc000) >> 14 +} + +// SPI2.DOUT_MODE: SPI output delay mode configuration +func (o *SPI2_Type) SetDOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDOUT_MODE_D_DQS_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDOUT_MODE_D_DQS_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI2.DMA_CONF: SPI DMA control register +func (o *SPI2_Type) SetDMA_CONF_DMA_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_OUTFIFO_EMPTY() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_INFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_SLV_SEG_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_SLV_SEG_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetDMA_CONF_RX_EOF_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetDMA_CONF_RX_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_RX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_RX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_TX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_TX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetDMA_CONF_RX_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetDMA_CONF_RX_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetDMA_CONF_BUF_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetDMA_CONF_BUF_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// SPI2.DMA_INT_ENA: SPI interrupt enable register +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EX_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EX_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EN_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EN_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMDA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMDA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ENA_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ENA_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_CLR: SPI interrupt clear register +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EX_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EX_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EN_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EN_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD8_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD8_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD9_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD9_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMDA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMDA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_CLR_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_CLR_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_RAW: SPI interrupt raw register +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EX_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EX_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EN_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EN_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD8_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD8_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD9_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD9_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMDA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMDA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_RAW_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_RAW_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_ST: SPI interrupt status register +func (o *SPI2_Type) SetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EX_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EX_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EN_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EN_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD7_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD8_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD8_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD9_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD9_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMDA_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMDA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ST_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ST_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_SET: SPI interrupt software set register +func (o *SPI2_Type) SetDMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET() uint32 { + return volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_EX_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_EX_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_EN_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_EN_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD7_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD7_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD8_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD8_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD9_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD9_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMDA_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMDA_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_RD_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_RD_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_WR_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_WR_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_RD_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_RD_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_WR_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_WR_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_SET_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_SET_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_SET_SEG_MAGIC_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_SET_SEG_MAGIC_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_SET_APP2_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_SET_APP2_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_SET_APP1_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_SET_APP1_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x100000) >> 20 +} + +// SPI2.W0: SPI CPU-controlled buffer0 +func (o *SPI2_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI2_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI2.W1: SPI CPU-controlled buffer1 +func (o *SPI2_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI2_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI2.W2: SPI CPU-controlled buffer2 +func (o *SPI2_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI2_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI2.W3: SPI CPU-controlled buffer3 +func (o *SPI2_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI2_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI2.W4: SPI CPU-controlled buffer4 +func (o *SPI2_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI2_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI2.W5: SPI CPU-controlled buffer5 +func (o *SPI2_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI2_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI2.W6: SPI CPU-controlled buffer6 +func (o *SPI2_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI2_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI2.W7: SPI CPU-controlled buffer7 +func (o *SPI2_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI2_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI2.W8: SPI CPU-controlled buffer8 +func (o *SPI2_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI2_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI2.W9: SPI CPU-controlled buffer9 +func (o *SPI2_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI2_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI2.W10: SPI CPU-controlled buffer10 +func (o *SPI2_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI2_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI2.W11: SPI CPU-controlled buffer11 +func (o *SPI2_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI2_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI2.W12: SPI CPU-controlled buffer12 +func (o *SPI2_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI2_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI2.W13: SPI CPU-controlled buffer13 +func (o *SPI2_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI2_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI2.W14: SPI CPU-controlled buffer14 +func (o *SPI2_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI2_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI2.W15: SPI CPU-controlled buffer15 +func (o *SPI2_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI2_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI2.SLAVE: SPI slave control register +func (o *SPI2_Type) SetSLAVE_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SLAVE.Reg) & 0x3 +} +func (o *SPI2_Type) SetSLAVE_CLK_MODE_13(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE_13() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSLAVE_RSCK_DATA_OUT(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSLAVE_RSCK_DATA_OUT() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSLAVE_DMA_SEG_MAGIC_VALUE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3c00000)|value<<22) +} +func (o *SPI2_Type) GetSLAVE_DMA_SEG_MAGIC_VALUE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x3c00000) >> 22 +} +func (o *SPI2_Type) SetSLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetSLAVE_SOFT_RESET(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetSLAVE_SOFT_RESET() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetSLAVE_USR_CONF(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetSLAVE_USR_CONF() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetSLAVE_MST_FD_WAIT_DMA_TX_DATA(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetSLAVE_MST_FD_WAIT_DMA_TX_DATA() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x20000000) >> 29 +} + +// SPI2.SLAVE1: SPI slave control register 1 +func (o *SPI2_Type) SetSLAVE1_SLV_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetSLAVE1_SLV_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_COMMAND(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3fc0000)|value<<18) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3fc0000) >> 18 +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_ADDR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0xfc000000) >> 26 +} + +// SPI2.CLK_GATE: SPI module clock and register clock control +func (o *SPI2_Type) SetCLK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetCLK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x4) >> 2 +} + +// SPI2.DATE: Version control +func (o *SPI2_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI2_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// System Timer +type SYSTIMER_Type struct { + CONF volatile.Register32 // 0x0 + UNIT0_OP volatile.Register32 // 0x4 + UNIT1_OP volatile.Register32 // 0x8 + UNIT0_LOAD_HI volatile.Register32 // 0xC + UNIT0_LOAD_LO volatile.Register32 // 0x10 + UNIT1_LOAD_HI volatile.Register32 // 0x14 + UNIT1_LOAD_LO volatile.Register32 // 0x18 + TARGET0_HI volatile.Register32 // 0x1C + TARGET0_LO volatile.Register32 // 0x20 + TARGET1_HI volatile.Register32 // 0x24 + TARGET1_LO volatile.Register32 // 0x28 + TARGET2_HI volatile.Register32 // 0x2C + TARGET2_LO volatile.Register32 // 0x30 + TARGET0_CONF volatile.Register32 // 0x34 + TARGET1_CONF volatile.Register32 // 0x38 + TARGET2_CONF volatile.Register32 // 0x3C + UNIT0_VALUE_HI volatile.Register32 // 0x40 + UNIT0_VALUE_LO volatile.Register32 // 0x44 + UNIT1_VALUE_HI volatile.Register32 // 0x48 + UNIT1_VALUE_LO volatile.Register32 // 0x4C + COMP0_LOAD volatile.Register32 // 0x50 + COMP1_LOAD volatile.Register32 // 0x54 + COMP2_LOAD volatile.Register32 // 0x58 + UNIT0_LOAD volatile.Register32 // 0x5C + UNIT1_LOAD volatile.Register32 // 0x60 + INT_ENA volatile.Register32 // 0x64 + INT_RAW volatile.Register32 // 0x68 + INT_CLR volatile.Register32 // 0x6C + INT_ST volatile.Register32 // 0x70 + REAL_TARGET0_LO volatile.Register32 // 0x74 + REAL_TARGET0_HI volatile.Register32 // 0x78 + REAL_TARGET1_LO volatile.Register32 // 0x7C + REAL_TARGET1_HI volatile.Register32 // 0x80 + REAL_TARGET2_LO volatile.Register32 // 0x84 + REAL_TARGET2_HI volatile.Register32 // 0x88 + _ [112]byte + DATE volatile.Register32 // 0xFC +} + +// SYSTIMER.CONF: Configure system timer clock +func (o *SYSTIMER_Type) SetCONF_SYSTIMER_CLK_FO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCONF_SYSTIMER_CLK_FO() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetCONF_ETM_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetCONF_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetCONF_TARGET2_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTIMER_Type) GetCONF_TARGET2_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22 +} +func (o *SYSTIMER_Type) SetCONF_TARGET1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTIMER_Type) GetCONF_TARGET1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23 +} +func (o *SYSTIMER_Type) SetCONF_TARGET0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTIMER_Type) GetCONF_TARGET0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000000) >> 26 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000000) >> 27 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000000) >> 28 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_OP: system timer unit0 value update register +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT1_OP: system timer unit1 value update register +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT0_LOAD_HI: system timer unit0 value high load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_LOAD_LO: system timer unit0 value low load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_LO.Reg) +} + +// SYSTIMER.UNIT1_LOAD_HI: system timer unit1 value high load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_LOAD_LO: system timer unit1 value low load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_LO.Reg) +} + +// SYSTIMER.TARGET0_HI: system timer comp0 value high register +func (o *SYSTIMER_Type) SetTARGET0_HI_TIMER_TARGET0_HI(value uint32) { + volatile.StoreUint32(&o.TARGET0_HI.Reg, volatile.LoadUint32(&o.TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_HI_TIMER_TARGET0_HI() uint32 { + return volatile.LoadUint32(&o.TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET0_LO: system timer comp0 value low register +func (o *SYSTIMER_Type) SetTARGET0_LO(value uint32) { + volatile.StoreUint32(&o.TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET0_LO() uint32 { + return volatile.LoadUint32(&o.TARGET0_LO.Reg) +} + +// SYSTIMER.TARGET1_HI: system timer comp1 value high register +func (o *SYSTIMER_Type) SetTARGET1_HI_TIMER_TARGET1_HI(value uint32) { + volatile.StoreUint32(&o.TARGET1_HI.Reg, volatile.LoadUint32(&o.TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_HI_TIMER_TARGET1_HI() uint32 { + return volatile.LoadUint32(&o.TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET1_LO: system timer comp1 value low register +func (o *SYSTIMER_Type) SetTARGET1_LO(value uint32) { + volatile.StoreUint32(&o.TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET1_LO() uint32 { + return volatile.LoadUint32(&o.TARGET1_LO.Reg) +} + +// SYSTIMER.TARGET2_HI: system timer comp2 value high register +func (o *SYSTIMER_Type) SetTARGET2_HI_TIMER_TARGET2_HI(value uint32) { + volatile.StoreUint32(&o.TARGET2_HI.Reg, volatile.LoadUint32(&o.TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_HI_TIMER_TARGET2_HI() uint32 { + return volatile.LoadUint32(&o.TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET2_LO: system timer comp2 value low register +func (o *SYSTIMER_Type) SetTARGET2_LO(value uint32) { + volatile.StoreUint32(&o.TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET2_LO() uint32 { + return volatile.LoadUint32(&o.TARGET2_LO.Reg) +} + +// SYSTIMER.TARGET0_CONF: system timer comp0 target mode register +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET1_CONF: system timer comp1 target mode register +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET2_CONF: system timer comp2 target mode register +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_VALUE_HI: system timer unit0 value high register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_VALUE_LO: system timer unit0 value low register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_LO.Reg) +} + +// SYSTIMER.UNIT1_VALUE_HI: system timer unit1 value high register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_VALUE_LO: system timer unit1 value low register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_LO.Reg) +} + +// SYSTIMER.COMP0_LOAD: system timer comp0 conf sync register +func (o *SYSTIMER_Type) SetCOMP0_LOAD_TIMER_COMP0_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP0_LOAD.Reg, volatile.LoadUint32(&o.COMP0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP0_LOAD_TIMER_COMP0_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP1_LOAD: system timer comp1 conf sync register +func (o *SYSTIMER_Type) SetCOMP1_LOAD_TIMER_COMP1_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP1_LOAD.Reg, volatile.LoadUint32(&o.COMP1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP1_LOAD_TIMER_COMP1_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP2_LOAD: system timer comp2 conf sync register +func (o *SYSTIMER_Type) SetCOMP2_LOAD_TIMER_COMP2_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP2_LOAD.Reg, volatile.LoadUint32(&o.COMP2_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP2_LOAD_TIMER_COMP2_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP2_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT0_LOAD: system timer unit0 conf sync register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_TIMER_UNIT0_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD.Reg, volatile.LoadUint32(&o.UNIT0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_TIMER_UNIT0_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT1_LOAD: system timer unit1 conf sync register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_TIMER_UNIT1_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD.Reg, volatile.LoadUint32(&o.UNIT1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_TIMER_UNIT1_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.INT_ENA: systimer interrupt enable register +func (o *SYSTIMER_Type) SetINT_ENA_TARGET0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_RAW: systimer interrupt raw register +func (o *SYSTIMER_Type) SetINT_RAW_TARGET0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_CLR: systimer interrupt clear register +func (o *SYSTIMER_Type) SetINT_CLR_TARGET0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_ST: systimer interrupt status register +func (o *SYSTIMER_Type) SetINT_ST_TARGET0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// SYSTIMER.REAL_TARGET0_LO: system timer comp0 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET0_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET0_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET0_LO.Reg) +} + +// SYSTIMER.REAL_TARGET0_HI: system timer comp0 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET0_HI_TARGET0_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET0_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET0_HI_TARGET0_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.REAL_TARGET1_LO: system timer comp1 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET1_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET1_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET1_LO.Reg) +} + +// SYSTIMER.REAL_TARGET1_HI: system timer comp1 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET1_HI_TARGET1_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET1_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET1_HI_TARGET1_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.REAL_TARGET2_LO: system timer comp2 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET2_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET2_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET2_LO.Reg) +} + +// SYSTIMER.REAL_TARGET2_HI: system timer comp2 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET2_HI_TARGET2_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET2_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET2_HI_TARGET2_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.DATE: system timer version control register +func (o *SYSTIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *SYSTIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// TEE Peripheral +type TEE_Type struct { + M0_MODE_CTRL volatile.Register32 // 0x0 + M1_MODE_CTRL volatile.Register32 // 0x4 + M2_MODE_CTRL volatile.Register32 // 0x8 + M3_MODE_CTRL volatile.Register32 // 0xC + M4_MODE_CTRL volatile.Register32 // 0x10 + M5_MODE_CTRL volatile.Register32 // 0x14 + M6_MODE_CTRL volatile.Register32 // 0x18 + M7_MODE_CTRL volatile.Register32 // 0x1C + M8_MODE_CTRL volatile.Register32 // 0x20 + M9_MODE_CTRL volatile.Register32 // 0x24 + M10_MODE_CTRL volatile.Register32 // 0x28 + M11_MODE_CTRL volatile.Register32 // 0x2C + M12_MODE_CTRL volatile.Register32 // 0x30 + M13_MODE_CTRL volatile.Register32 // 0x34 + M14_MODE_CTRL volatile.Register32 // 0x38 + M15_MODE_CTRL volatile.Register32 // 0x3C + M16_MODE_CTRL volatile.Register32 // 0x40 + M17_MODE_CTRL volatile.Register32 // 0x44 + M18_MODE_CTRL volatile.Register32 // 0x48 + M19_MODE_CTRL volatile.Register32 // 0x4C + M20_MODE_CTRL volatile.Register32 // 0x50 + M21_MODE_CTRL volatile.Register32 // 0x54 + M22_MODE_CTRL volatile.Register32 // 0x58 + M23_MODE_CTRL volatile.Register32 // 0x5C + M24_MODE_CTRL volatile.Register32 // 0x60 + M25_MODE_CTRL volatile.Register32 // 0x64 + M26_MODE_CTRL volatile.Register32 // 0x68 + M27_MODE_CTRL volatile.Register32 // 0x6C + M28_MODE_CTRL volatile.Register32 // 0x70 + M29_MODE_CTRL volatile.Register32 // 0x74 + M30_MODE_CTRL volatile.Register32 // 0x78 + M31_MODE_CTRL volatile.Register32 // 0x7C + CLOCK_GATE volatile.Register32 // 0x80 + _ [3960]byte + DATE volatile.Register32 // 0xFFC +} + +// TEE.M0_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM0_MODE_CTRL_M0_MODE(value uint32) { + volatile.StoreUint32(&o.M0_MODE_CTRL.Reg, volatile.LoadUint32(&o.M0_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM0_MODE_CTRL_M0_MODE() uint32 { + return volatile.LoadUint32(&o.M0_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M1_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM1_MODE_CTRL_M1_MODE(value uint32) { + volatile.StoreUint32(&o.M1_MODE_CTRL.Reg, volatile.LoadUint32(&o.M1_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM1_MODE_CTRL_M1_MODE() uint32 { + return volatile.LoadUint32(&o.M1_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M2_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM2_MODE_CTRL_M2_MODE(value uint32) { + volatile.StoreUint32(&o.M2_MODE_CTRL.Reg, volatile.LoadUint32(&o.M2_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM2_MODE_CTRL_M2_MODE() uint32 { + return volatile.LoadUint32(&o.M2_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M3_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM3_MODE_CTRL_M3_MODE(value uint32) { + volatile.StoreUint32(&o.M3_MODE_CTRL.Reg, volatile.LoadUint32(&o.M3_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM3_MODE_CTRL_M3_MODE() uint32 { + return volatile.LoadUint32(&o.M3_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M4_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM4_MODE_CTRL_M4_MODE(value uint32) { + volatile.StoreUint32(&o.M4_MODE_CTRL.Reg, volatile.LoadUint32(&o.M4_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM4_MODE_CTRL_M4_MODE() uint32 { + return volatile.LoadUint32(&o.M4_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M5_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM5_MODE_CTRL_M5_MODE(value uint32) { + volatile.StoreUint32(&o.M5_MODE_CTRL.Reg, volatile.LoadUint32(&o.M5_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM5_MODE_CTRL_M5_MODE() uint32 { + return volatile.LoadUint32(&o.M5_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M6_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM6_MODE_CTRL_M6_MODE(value uint32) { + volatile.StoreUint32(&o.M6_MODE_CTRL.Reg, volatile.LoadUint32(&o.M6_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM6_MODE_CTRL_M6_MODE() uint32 { + return volatile.LoadUint32(&o.M6_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M7_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM7_MODE_CTRL_M7_MODE(value uint32) { + volatile.StoreUint32(&o.M7_MODE_CTRL.Reg, volatile.LoadUint32(&o.M7_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM7_MODE_CTRL_M7_MODE() uint32 { + return volatile.LoadUint32(&o.M7_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M8_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM8_MODE_CTRL_M8_MODE(value uint32) { + volatile.StoreUint32(&o.M8_MODE_CTRL.Reg, volatile.LoadUint32(&o.M8_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM8_MODE_CTRL_M8_MODE() uint32 { + return volatile.LoadUint32(&o.M8_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M9_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM9_MODE_CTRL_M9_MODE(value uint32) { + volatile.StoreUint32(&o.M9_MODE_CTRL.Reg, volatile.LoadUint32(&o.M9_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM9_MODE_CTRL_M9_MODE() uint32 { + return volatile.LoadUint32(&o.M9_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M10_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM10_MODE_CTRL_M10_MODE(value uint32) { + volatile.StoreUint32(&o.M10_MODE_CTRL.Reg, volatile.LoadUint32(&o.M10_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM10_MODE_CTRL_M10_MODE() uint32 { + return volatile.LoadUint32(&o.M10_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M11_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM11_MODE_CTRL_M11_MODE(value uint32) { + volatile.StoreUint32(&o.M11_MODE_CTRL.Reg, volatile.LoadUint32(&o.M11_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM11_MODE_CTRL_M11_MODE() uint32 { + return volatile.LoadUint32(&o.M11_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M12_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM12_MODE_CTRL_M12_MODE(value uint32) { + volatile.StoreUint32(&o.M12_MODE_CTRL.Reg, volatile.LoadUint32(&o.M12_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM12_MODE_CTRL_M12_MODE() uint32 { + return volatile.LoadUint32(&o.M12_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M13_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM13_MODE_CTRL_M13_MODE(value uint32) { + volatile.StoreUint32(&o.M13_MODE_CTRL.Reg, volatile.LoadUint32(&o.M13_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM13_MODE_CTRL_M13_MODE() uint32 { + return volatile.LoadUint32(&o.M13_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M14_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM14_MODE_CTRL_M14_MODE(value uint32) { + volatile.StoreUint32(&o.M14_MODE_CTRL.Reg, volatile.LoadUint32(&o.M14_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM14_MODE_CTRL_M14_MODE() uint32 { + return volatile.LoadUint32(&o.M14_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M15_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM15_MODE_CTRL_M15_MODE(value uint32) { + volatile.StoreUint32(&o.M15_MODE_CTRL.Reg, volatile.LoadUint32(&o.M15_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM15_MODE_CTRL_M15_MODE() uint32 { + return volatile.LoadUint32(&o.M15_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M16_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM16_MODE_CTRL_M16_MODE(value uint32) { + volatile.StoreUint32(&o.M16_MODE_CTRL.Reg, volatile.LoadUint32(&o.M16_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM16_MODE_CTRL_M16_MODE() uint32 { + return volatile.LoadUint32(&o.M16_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M17_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM17_MODE_CTRL_M17_MODE(value uint32) { + volatile.StoreUint32(&o.M17_MODE_CTRL.Reg, volatile.LoadUint32(&o.M17_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM17_MODE_CTRL_M17_MODE() uint32 { + return volatile.LoadUint32(&o.M17_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M18_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM18_MODE_CTRL_M18_MODE(value uint32) { + volatile.StoreUint32(&o.M18_MODE_CTRL.Reg, volatile.LoadUint32(&o.M18_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM18_MODE_CTRL_M18_MODE() uint32 { + return volatile.LoadUint32(&o.M18_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M19_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM19_MODE_CTRL_M19_MODE(value uint32) { + volatile.StoreUint32(&o.M19_MODE_CTRL.Reg, volatile.LoadUint32(&o.M19_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM19_MODE_CTRL_M19_MODE() uint32 { + return volatile.LoadUint32(&o.M19_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M20_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM20_MODE_CTRL_M20_MODE(value uint32) { + volatile.StoreUint32(&o.M20_MODE_CTRL.Reg, volatile.LoadUint32(&o.M20_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM20_MODE_CTRL_M20_MODE() uint32 { + return volatile.LoadUint32(&o.M20_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M21_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM21_MODE_CTRL_M21_MODE(value uint32) { + volatile.StoreUint32(&o.M21_MODE_CTRL.Reg, volatile.LoadUint32(&o.M21_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM21_MODE_CTRL_M21_MODE() uint32 { + return volatile.LoadUint32(&o.M21_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M22_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM22_MODE_CTRL_M22_MODE(value uint32) { + volatile.StoreUint32(&o.M22_MODE_CTRL.Reg, volatile.LoadUint32(&o.M22_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM22_MODE_CTRL_M22_MODE() uint32 { + return volatile.LoadUint32(&o.M22_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M23_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM23_MODE_CTRL_M23_MODE(value uint32) { + volatile.StoreUint32(&o.M23_MODE_CTRL.Reg, volatile.LoadUint32(&o.M23_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM23_MODE_CTRL_M23_MODE() uint32 { + return volatile.LoadUint32(&o.M23_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M24_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM24_MODE_CTRL_M24_MODE(value uint32) { + volatile.StoreUint32(&o.M24_MODE_CTRL.Reg, volatile.LoadUint32(&o.M24_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM24_MODE_CTRL_M24_MODE() uint32 { + return volatile.LoadUint32(&o.M24_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M25_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM25_MODE_CTRL_M25_MODE(value uint32) { + volatile.StoreUint32(&o.M25_MODE_CTRL.Reg, volatile.LoadUint32(&o.M25_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM25_MODE_CTRL_M25_MODE() uint32 { + return volatile.LoadUint32(&o.M25_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M26_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM26_MODE_CTRL_M26_MODE(value uint32) { + volatile.StoreUint32(&o.M26_MODE_CTRL.Reg, volatile.LoadUint32(&o.M26_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM26_MODE_CTRL_M26_MODE() uint32 { + return volatile.LoadUint32(&o.M26_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M27_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM27_MODE_CTRL_M27_MODE(value uint32) { + volatile.StoreUint32(&o.M27_MODE_CTRL.Reg, volatile.LoadUint32(&o.M27_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM27_MODE_CTRL_M27_MODE() uint32 { + return volatile.LoadUint32(&o.M27_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M28_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM28_MODE_CTRL_M28_MODE(value uint32) { + volatile.StoreUint32(&o.M28_MODE_CTRL.Reg, volatile.LoadUint32(&o.M28_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM28_MODE_CTRL_M28_MODE() uint32 { + return volatile.LoadUint32(&o.M28_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M29_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM29_MODE_CTRL_M29_MODE(value uint32) { + volatile.StoreUint32(&o.M29_MODE_CTRL.Reg, volatile.LoadUint32(&o.M29_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM29_MODE_CTRL_M29_MODE() uint32 { + return volatile.LoadUint32(&o.M29_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M30_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM30_MODE_CTRL_M30_MODE(value uint32) { + volatile.StoreUint32(&o.M30_MODE_CTRL.Reg, volatile.LoadUint32(&o.M30_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM30_MODE_CTRL_M30_MODE() uint32 { + return volatile.LoadUint32(&o.M30_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M31_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM31_MODE_CTRL_M31_MODE(value uint32) { + volatile.StoreUint32(&o.M31_MODE_CTRL.Reg, volatile.LoadUint32(&o.M31_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM31_MODE_CTRL_M31_MODE() uint32 { + return volatile.LoadUint32(&o.M31_MODE_CTRL.Reg) & 0x3 +} + +// TEE.CLOCK_GATE: Clock gating register +func (o *TEE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *TEE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// TEE.DATE: Version register +func (o *TEE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *TEE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Timer Group 0 +type TIMG_Type struct { + T0CONFIG volatile.Register32 // 0x0 + T0LO volatile.Register32 // 0x4 + T0HI volatile.Register32 // 0x8 + T0UPDATE volatile.Register32 // 0xC + T0ALARMLO volatile.Register32 // 0x10 + T0ALARMHI volatile.Register32 // 0x14 + T0LOADLO volatile.Register32 // 0x18 + T0LOADHI volatile.Register32 // 0x1C + T0LOAD volatile.Register32 // 0x20 + _ [36]byte + WDTCONFIG0 volatile.Register32 // 0x48 + WDTCONFIG1 volatile.Register32 // 0x4C + WDTCONFIG2 volatile.Register32 // 0x50 + WDTCONFIG3 volatile.Register32 // 0x54 + WDTCONFIG4 volatile.Register32 // 0x58 + WDTCONFIG5 volatile.Register32 // 0x5C + WDTFEED volatile.Register32 // 0x60 + WDTWPROTECT volatile.Register32 // 0x64 + RTCCALICFG volatile.Register32 // 0x68 + RTCCALICFG1 volatile.Register32 // 0x6C + INT_ENA_TIMERS volatile.Register32 // 0x70 + INT_RAW_TIMERS volatile.Register32 // 0x74 + INT_ST_TIMERS volatile.Register32 // 0x78 + INT_CLR_TIMERS volatile.Register32 // 0x7C + RTCCALICFG2 volatile.Register32 // 0x80 + _ [116]byte + NTIMERS_DATE volatile.Register32 // 0xF8 + REGCLK volatile.Register32 // 0xFC +} + +// TIMG.T0CONFIG: Timer %s configuration register +func (o *TIMG_Type) SetT0CONFIG_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetT0CONFIG_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetT0CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT0CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT0CONFIG_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetT0CONFIG_DIVCNT_RST() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetT0CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT0CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT0CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT0CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT0CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT0CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT0CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0LO: Timer %s current value, low 32 bits +func (o *TIMG_Type) SetT0LO(value uint32) { + volatile.StoreUint32(&o.T0LO.Reg, value) +} +func (o *TIMG_Type) GetT0LO() uint32 { + return volatile.LoadUint32(&o.T0LO.Reg) +} + +// TIMG.T0HI: Timer %s current value, high 22 bits +func (o *TIMG_Type) SetT0HI_HI(value uint32) { + volatile.StoreUint32(&o.T0HI.Reg, volatile.LoadUint32(&o.T0HI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0HI_HI() uint32 { + return volatile.LoadUint32(&o.T0HI.Reg) & 0x3fffff +} + +// TIMG.T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG +func (o *TIMG_Type) SetT0UPDATE_UPDATE(value uint32) { + volatile.StoreUint32(&o.T0UPDATE.Reg, volatile.LoadUint32(&o.T0UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0UPDATE_UPDATE() uint32 { + return (volatile.LoadUint32(&o.T0UPDATE.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0ALARMLO: Timer %s alarm value, low 32 bits +func (o *TIMG_Type) SetT0ALARMLO(value uint32) { + volatile.StoreUint32(&o.T0ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMLO() uint32 { + return volatile.LoadUint32(&o.T0ALARMLO.Reg) +} + +// TIMG.T0ALARMHI: Timer %s alarm value, high bits +func (o *TIMG_Type) SetT0ALARMHI_ALARM_HI(value uint32) { + volatile.StoreUint32(&o.T0ALARMHI.Reg, volatile.LoadUint32(&o.T0ALARMHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0ALARMHI_ALARM_HI() uint32 { + return volatile.LoadUint32(&o.T0ALARMHI.Reg) & 0x3fffff +} + +// TIMG.T0LOADLO: Timer %s reload value, low 32 bits +func (o *TIMG_Type) SetT0LOADLO(value uint32) { + volatile.StoreUint32(&o.T0LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT0LOADLO() uint32 { + return volatile.LoadUint32(&o.T0LOADLO.Reg) +} + +// TIMG.T0LOADHI: Timer %s reload value, high 22 bits +func (o *TIMG_Type) SetT0LOADHI_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.T0LOADHI.Reg, volatile.LoadUint32(&o.T0LOADHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0LOADHI_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.T0LOADHI.Reg) & 0x3fffff +} + +// TIMG.T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG +func (o *TIMG_Type) SetT0LOAD(value uint32) { + volatile.StoreUint32(&o.T0LOAD.Reg, value) +} +func (o *TIMG_Type) GetT0LOAD() uint32 { + return volatile.LoadUint32(&o.T0LOAD.Reg) +} + +// TIMG.WDTCONFIG0: Watchdog timer configuration register +func (o *TIMG_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x2000)|value<<13) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x2000) >> 13 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x4000)|value<<14) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x4000) >> 14 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x38000)|value<<15) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x38000) >> 15 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c0000)|value<<18) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c0000) >> 18 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200000)|value<<21) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200000) >> 21 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CONF_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400000)|value<<22) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CONF_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400000) >> 22 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1800000)|value<<23) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1800000) >> 23 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x6000000)|value<<25) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x6000000) >> 25 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x18000000)|value<<27) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x18000000) >> 27 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x60000000)|value<<29) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x60000000) >> 29 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// TIMG.WDTCONFIG1: Watchdog timer prescaler register +func (o *TIMG_Type) SetWDTCONFIG1_WDT_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_DIVCNT_RST() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetWDTCONFIG1_WDT_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_CLK_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0xffff0000) >> 16 +} + +// TIMG.WDTCONFIG2: Watchdog timer stage 0 timeout value +func (o *TIMG_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// TIMG.WDTCONFIG3: Watchdog timer stage 1 timeout value +func (o *TIMG_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// TIMG.WDTCONFIG4: Watchdog timer stage 2 timeout value +func (o *TIMG_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// TIMG.WDTCONFIG5: Watchdog timer stage 3 timeout value +func (o *TIMG_Type) SetWDTCONFIG5(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG5.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG5() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG5.Reg) +} + +// TIMG.WDTFEED: Write to feed the watchdog timer +func (o *TIMG_Type) SetWDTFEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, value) +} +func (o *TIMG_Type) GetWDTFEED() uint32 { + return volatile.LoadUint32(&o.WDTFEED.Reg) +} + +// TIMG.WDTWPROTECT: Watchdog write protect register +func (o *TIMG_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *TIMG_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// TIMG.RTCCALICFG: RTC calibration configure register +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START_CYCLING(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START_CYCLING() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x6000)|value<<13) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x6000) >> 13 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_RDY(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x8000)|value<<15) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_RDY() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x8000) >> 15 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_MAX(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x7fff0000)|value<<16) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_MAX() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x7fff0000) >> 16 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x80000000) >> 31 +} + +// TIMG.RTCCALICFG1: RTC calibration configure1 register +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_VALUE(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_VALUE() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0xffffff80) >> 7 +} + +// TIMG.INT_ENA_TIMERS: Interrupt enable bits +func (o *TIMG_Type) SetINT_ENA_TIMERS_T0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_RAW_TIMERS: Raw interrupt status +func (o *TIMG_Type) SetINT_RAW_TIMERS_T0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_ST_TIMERS: Masked interrupt status +func (o *TIMG_Type) SetINT_ST_TIMERS_T0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_CLR_TIMERS: Interrupt clear bits +func (o *TIMG_Type) SetINT_CLR_TIMERS_T0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.RTCCALICFG2: Timer group calibration register +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x78)|value<<3) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x78) >> 3 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0xffffff80) >> 7 +} + +// TIMG.NTIMERS_DATE: Timer version control register +func (o *TIMG_Type) SetNTIMERS_DATE_NTIMGS_DATE(value uint32) { + volatile.StoreUint32(&o.NTIMERS_DATE.Reg, volatile.LoadUint32(&o.NTIMERS_DATE.Reg)&^(0xfffffff)|value) +} +func (o *TIMG_Type) GetNTIMERS_DATE_NTIMGS_DATE() uint32 { + return volatile.LoadUint32(&o.NTIMERS_DATE.Reg) & 0xfffffff +} + +// TIMG.REGCLK: Timer group clock gate register +func (o *TIMG_Type) SetREGCLK_ETM_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *TIMG_Type) GetREGCLK_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x10000000) >> 28 +} +func (o *TIMG_Type) SetREGCLK_WDT_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetREGCLK_WDT_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetREGCLK_TIMER_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetREGCLK_TIMER_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetREGCLK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetREGCLK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x80000000) >> 31 +} + +// RISC-V Trace Encoder +type TRACE_Type struct { + MEM_START_ADDR volatile.Register32 // 0x0 + MEM_END_ADDR volatile.Register32 // 0x4 + MEM_CURRENT_ADDR volatile.Register32 // 0x8 + MEM_ADDR_UPDATE volatile.Register32 // 0xC + FIFO_STATUS volatile.Register32 // 0x10 + INTR_ENA volatile.Register32 // 0x14 + INTR_RAW volatile.Register32 // 0x18 + INTR_CLR volatile.Register32 // 0x1C + TRIGGER volatile.Register32 // 0x20 + RESYNC_PROLONGED volatile.Register32 // 0x24 + CLOCK_GATE volatile.Register32 // 0x28 + _ [976]byte + DATE volatile.Register32 // 0x3FC +} + +// TRACE.MEM_START_ADDR: mem start addr +func (o *TRACE_Type) SetMEM_START_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_START_ADDR.Reg, value) +} +func (o *TRACE_Type) GetMEM_START_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_START_ADDR.Reg) +} + +// TRACE.MEM_END_ADDR: mem end addr +func (o *TRACE_Type) SetMEM_END_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_END_ADDR.Reg, value) +} +func (o *TRACE_Type) GetMEM_END_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_END_ADDR.Reg) +} + +// TRACE.MEM_CURRENT_ADDR: mem current addr +func (o *TRACE_Type) SetMEM_CURRENT_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_CURRENT_ADDR.Reg, value) +} +func (o *TRACE_Type) GetMEM_CURRENT_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_CURRENT_ADDR.Reg) +} + +// TRACE.MEM_ADDR_UPDATE: mem addr update +func (o *TRACE_Type) SetMEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE(value uint32) { + volatile.StoreUint32(&o.MEM_ADDR_UPDATE.Reg, volatile.LoadUint32(&o.MEM_ADDR_UPDATE.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetMEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE() uint32 { + return volatile.LoadUint32(&o.MEM_ADDR_UPDATE.Reg) & 0x1 +} + +// TRACE.FIFO_STATUS: fifo status register +func (o *TRACE_Type) SetFIFO_STATUS_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.FIFO_STATUS.Reg, volatile.LoadUint32(&o.FIFO_STATUS.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetFIFO_STATUS_FIFO_EMPTY() uint32 { + return volatile.LoadUint32(&o.FIFO_STATUS.Reg) & 0x1 +} +func (o *TRACE_Type) SetFIFO_STATUS_WORK_STATUS(value uint32) { + volatile.StoreUint32(&o.FIFO_STATUS.Reg, volatile.LoadUint32(&o.FIFO_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetFIFO_STATUS_WORK_STATUS() uint32 { + return (volatile.LoadUint32(&o.FIFO_STATUS.Reg) & 0x2) >> 1 +} + +// TRACE.INTR_ENA: interrupt enable register +func (o *TRACE_Type) SetINTR_ENA_FIFO_OVERFLOW_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_ENA.Reg, volatile.LoadUint32(&o.INTR_ENA.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetINTR_ENA_FIFO_OVERFLOW_INTR_ENA() uint32 { + return volatile.LoadUint32(&o.INTR_ENA.Reg) & 0x1 +} +func (o *TRACE_Type) SetINTR_ENA_MEM_FULL_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_ENA.Reg, volatile.LoadUint32(&o.INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetINTR_ENA_MEM_FULL_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_ENA.Reg) & 0x2) >> 1 +} + +// TRACE.INTR_RAW: interrupt status register +func (o *TRACE_Type) SetINTR_RAW_FIFO_OVERFLOW_INTR_RAW(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetINTR_RAW_FIFO_OVERFLOW_INTR_RAW() uint32 { + return volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x1 +} +func (o *TRACE_Type) SetINTR_RAW_MEM_FULL_INTR_RAW(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetINTR_RAW_MEM_FULL_INTR_RAW() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x2) >> 1 +} + +// TRACE.INTR_CLR: interrupt clear register +func (o *TRACE_Type) SetINTR_CLR_FIFO_OVERFLOW_INTR_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetINTR_CLR_FIFO_OVERFLOW_INTR_CLR() uint32 { + return volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x1 +} +func (o *TRACE_Type) SetINTR_CLR_MEM_FULL_INTR_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetINTR_CLR_MEM_FULL_INTR_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x2) >> 1 +} + +// TRACE.TRIGGER: trigger register +func (o *TRACE_Type) SetTRIGGER_ON(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetTRIGGER_ON() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} +func (o *TRACE_Type) SetTRIGGER_OFF(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetTRIGGER_OFF() uint32 { + return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x2) >> 1 +} +func (o *TRACE_Type) SetTRIGGER_MEM_LOOP(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x4)|value<<2) +} +func (o *TRACE_Type) GetTRIGGER_MEM_LOOP() uint32 { + return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x4) >> 2 +} +func (o *TRACE_Type) SetTRIGGER_RESTART_ENA(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x8)|value<<3) +} +func (o *TRACE_Type) GetTRIGGER_RESTART_ENA() uint32 { + return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x8) >> 3 +} + +// TRACE.RESYNC_PROLONGED: resync configuration register +func (o *TRACE_Type) SetRESYNC_PROLONGED(value uint32) { + volatile.StoreUint32(&o.RESYNC_PROLONGED.Reg, volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg)&^(0xffffff)|value) +} +func (o *TRACE_Type) GetRESYNC_PROLONGED() uint32 { + return volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg) & 0xffffff +} +func (o *TRACE_Type) SetRESYNC_PROLONGED_RESYNC_MODE(value uint32) { + volatile.StoreUint32(&o.RESYNC_PROLONGED.Reg, volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg)&^(0x1000000)|value<<24) +} +func (o *TRACE_Type) GetRESYNC_PROLONGED_RESYNC_MODE() uint32 { + return (volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg) & 0x1000000) >> 24 +} + +// TRACE.CLOCK_GATE: Clock gate control register +func (o *TRACE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// TRACE.DATE: Version control register +func (o *TRACE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *TRACE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Two-Wire Automotive Interface +type TWAI_Type struct { + MODE volatile.Register32 // 0x0 + CMD volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + INTERRUPT volatile.Register32 // 0xC + INTERRUPT_ENABLE volatile.Register32 // 0x10 + _ [4]byte + BUS_TIMING_0 volatile.Register32 // 0x18 + BUS_TIMING_1 volatile.Register32 // 0x1C + _ [12]byte + ARB_LOST_CAP volatile.Register32 // 0x2C + ERR_CODE_CAP volatile.Register32 // 0x30 + ERR_WARNING_LIMIT volatile.Register32 // 0x34 + RX_ERR_CNT volatile.Register32 // 0x38 + TX_ERR_CNT volatile.Register32 // 0x3C + DATA_0 volatile.Register32 // 0x40 + DATA_1 volatile.Register32 // 0x44 + DATA_2 volatile.Register32 // 0x48 + DATA_3 volatile.Register32 // 0x4C + DATA_4 volatile.Register32 // 0x50 + DATA_5 volatile.Register32 // 0x54 + DATA_6 volatile.Register32 // 0x58 + DATA_7 volatile.Register32 // 0x5C + DATA_8 volatile.Register32 // 0x60 + DATA_9 volatile.Register32 // 0x64 + DATA_10 volatile.Register32 // 0x68 + DATA_11 volatile.Register32 // 0x6C + DATA_12 volatile.Register32 // 0x70 + RX_MESSAGE_CNT volatile.Register32 // 0x74 + _ [4]byte + CLOCK_DIVIDER volatile.Register32 // 0x7C + SW_STANDBY_CFG volatile.Register32 // 0x80 + HW_CFG volatile.Register32 // 0x84 + HW_STANDBY_CNT volatile.Register32 // 0x88 + IDLE_INTR_CNT volatile.Register32 // 0x8C + ECO_CFG volatile.Register32 // 0x90 +} + +// TWAI.MODE: TWAI mode register. +func (o *TWAI_Type) SetMODE_RESET_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetMODE_RESET_MODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x1 +} +func (o *TWAI_Type) SetMODE_LISTEN_ONLY_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetMODE_LISTEN_ONLY_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetMODE_SELF_TEST_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetMODE_SELF_TEST_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetMODE_RX_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetMODE_RX_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x8) >> 3 +} + +// TWAI.CMD: TWAI command register. +func (o *TWAI_Type) SetCMD_TX_REQ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetCMD_TX_REQ() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *TWAI_Type) SetCMD_ABORT_TX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetCMD_ABORT_TX() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetCMD_RELEASE_BUF(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetCMD_RELEASE_BUF() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetCMD_CLEAR_DATA_OVERRUN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetCMD_CLEAR_DATA_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetCMD_SELF_RX_REQUEST(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetCMD_SELF_RX_REQUEST() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10) >> 4 +} + +// TWAI.STATUS: TWAI status register. +func (o *TWAI_Type) SetSTATUS_RX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSTATUS_RX_BUF_ST() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *TWAI_Type) SetSTATUS_OVERRUN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSTATUS_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetSTATUS_TX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetSTATUS_TX_BUF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetSTATUS_TRANSMISSION_COMPLETE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetSTATUS_TRANSMISSION_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetSTATUS_RECEIVE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetSTATUS_RECEIVE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *TWAI_Type) SetSTATUS_TRANSMIT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetSTATUS_TRANSMIT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetSTATUS_ERR(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetSTATUS_ERR() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetSTATUS_BUS_OFF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetSTATUS_BUS_OFF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetSTATUS_MISS_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetSTATUS_MISS_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} + +// TWAI.INTERRUPT: Interrupt signals' register. +func (o *TWAI_Type) SetINTERRUPT_RECEIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINTERRUPT_RECEIVE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x1 +} +func (o *TWAI_Type) SetINTERRUPT_TRANSMIT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINTERRUPT_TRANSMIT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINTERRUPT_ERR_WARNING_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINTERRUPT_ERR_WARNING_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINTERRUPT_DATA_OVERRUN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINTERRUPT_DATA_OVERRUN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINTERRUPT_ERR_PASSIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINTERRUPT_ERR_PASSIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINTERRUPT_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINTERRUPT_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINTERRUPT_BUS_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINTERRUPT_BUS_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetINTERRUPT_IDLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetINTERRUPT_IDLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x100) >> 8 +} + +// TWAI.INTERRUPT_ENABLE: Interrupt enable register. +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x1 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_BUS_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_BUS_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_IDLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_IDLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x100) >> 8 +} + +// TWAI.BUS_TIMING_0: Bit timing configuration register 0. +func (o *TWAI_Type) SetBUS_TIMING_0_BAUD_PRESC(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0x3fff)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_0_BAUD_PRESC() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0x3fff +} +func (o *TWAI_Type) SetBUS_TIMING_0_SYNC_JUMP_WIDTH(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0xc000)|value<<14) +} +func (o *TWAI_Type) GetBUS_TIMING_0_SYNC_JUMP_WIDTH() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0xc000) >> 14 +} + +// TWAI.BUS_TIMING_1: Bit timing configuration register 1. +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG1(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0xf)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG1() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0xf +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG2(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x70)|value<<4) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG2() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x70) >> 4 +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SAMP(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SAMP() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x80) >> 7 +} + +// TWAI.ARB_LOST_CAP: TWAI arbiter lost capture register. +func (o *TWAI_Type) SetARB_LOST_CAP_ARBITRATION_LOST_CAPTURE(value uint32) { + volatile.StoreUint32(&o.ARB_LOST_CAP.Reg, volatile.LoadUint32(&o.ARB_LOST_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetARB_LOST_CAP_ARBITRATION_LOST_CAPTURE() uint32 { + return volatile.LoadUint32(&o.ARB_LOST_CAP.Reg) & 0x1f +} + +// TWAI.ERR_CODE_CAP: TWAI error info capture register. +func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT() uint32 { + return volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x1f +} +func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0xc0)|value<<6) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0xc0) >> 6 +} + +// TWAI.ERR_WARNING_LIMIT: TWAI error threshold configuration register. +func (o *TWAI_Type) SetERR_WARNING_LIMIT(value uint32) { + volatile.StoreUint32(&o.ERR_WARNING_LIMIT.Reg, volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetERR_WARNING_LIMIT() uint32 { + return volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg) & 0xff +} + +// TWAI.RX_ERR_CNT: Rx error counter register. +func (o *TWAI_Type) SetRX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ERR_CNT.Reg, volatile.LoadUint32(&o.RX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetRX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.RX_ERR_CNT.Reg) & 0xff +} + +// TWAI.TX_ERR_CNT: Tx error counter register. +func (o *TWAI_Type) SetTX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ERR_CNT.Reg, volatile.LoadUint32(&o.TX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetTX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.TX_ERR_CNT.Reg) & 0xff +} + +// TWAI.DATA_0: Data register 0. +func (o *TWAI_Type) SetDATA_0_TX_BYTE_0(value uint32) { + volatile.StoreUint32(&o.DATA_0.Reg, volatile.LoadUint32(&o.DATA_0.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_0_TX_BYTE_0() uint32 { + return volatile.LoadUint32(&o.DATA_0.Reg) & 0xff +} + +// TWAI.DATA_1: Data register 1. +func (o *TWAI_Type) SetDATA_1_TX_BYTE_1(value uint32) { + volatile.StoreUint32(&o.DATA_1.Reg, volatile.LoadUint32(&o.DATA_1.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_1_TX_BYTE_1() uint32 { + return volatile.LoadUint32(&o.DATA_1.Reg) & 0xff +} + +// TWAI.DATA_2: Data register 2. +func (o *TWAI_Type) SetDATA_2_TX_BYTE_2(value uint32) { + volatile.StoreUint32(&o.DATA_2.Reg, volatile.LoadUint32(&o.DATA_2.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_2_TX_BYTE_2() uint32 { + return volatile.LoadUint32(&o.DATA_2.Reg) & 0xff +} + +// TWAI.DATA_3: Data register 3. +func (o *TWAI_Type) SetDATA_3_TX_BYTE_3(value uint32) { + volatile.StoreUint32(&o.DATA_3.Reg, volatile.LoadUint32(&o.DATA_3.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_3_TX_BYTE_3() uint32 { + return volatile.LoadUint32(&o.DATA_3.Reg) & 0xff +} + +// TWAI.DATA_4: Data register 4. +func (o *TWAI_Type) SetDATA_4_TX_BYTE_4(value uint32) { + volatile.StoreUint32(&o.DATA_4.Reg, volatile.LoadUint32(&o.DATA_4.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_4_TX_BYTE_4() uint32 { + return volatile.LoadUint32(&o.DATA_4.Reg) & 0xff +} + +// TWAI.DATA_5: Data register 5. +func (o *TWAI_Type) SetDATA_5_TX_BYTE_5(value uint32) { + volatile.StoreUint32(&o.DATA_5.Reg, volatile.LoadUint32(&o.DATA_5.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_5_TX_BYTE_5() uint32 { + return volatile.LoadUint32(&o.DATA_5.Reg) & 0xff +} + +// TWAI.DATA_6: Data register 6. +func (o *TWAI_Type) SetDATA_6_TX_BYTE_6(value uint32) { + volatile.StoreUint32(&o.DATA_6.Reg, volatile.LoadUint32(&o.DATA_6.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_6_TX_BYTE_6() uint32 { + return volatile.LoadUint32(&o.DATA_6.Reg) & 0xff +} + +// TWAI.DATA_7: Data register 7. +func (o *TWAI_Type) SetDATA_7_TX_BYTE_7(value uint32) { + volatile.StoreUint32(&o.DATA_7.Reg, volatile.LoadUint32(&o.DATA_7.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_7_TX_BYTE_7() uint32 { + return volatile.LoadUint32(&o.DATA_7.Reg) & 0xff +} + +// TWAI.DATA_8: Data register 8. +func (o *TWAI_Type) SetDATA_8_TX_BYTE_8(value uint32) { + volatile.StoreUint32(&o.DATA_8.Reg, volatile.LoadUint32(&o.DATA_8.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_8_TX_BYTE_8() uint32 { + return volatile.LoadUint32(&o.DATA_8.Reg) & 0xff +} + +// TWAI.DATA_9: Data register 9. +func (o *TWAI_Type) SetDATA_9(value uint32) { + volatile.StoreUint32(&o.DATA_9.Reg, volatile.LoadUint32(&o.DATA_9.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_9() uint32 { + return volatile.LoadUint32(&o.DATA_9.Reg) & 0xff +} + +// TWAI.DATA_10: Data register 10. +func (o *TWAI_Type) SetDATA_10_TX_BYTE_10(value uint32) { + volatile.StoreUint32(&o.DATA_10.Reg, volatile.LoadUint32(&o.DATA_10.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_10_TX_BYTE_10() uint32 { + return volatile.LoadUint32(&o.DATA_10.Reg) & 0xff +} + +// TWAI.DATA_11: Data register 11. +func (o *TWAI_Type) SetDATA_11_TX_BYTE_11(value uint32) { + volatile.StoreUint32(&o.DATA_11.Reg, volatile.LoadUint32(&o.DATA_11.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_11_TX_BYTE_11() uint32 { + return volatile.LoadUint32(&o.DATA_11.Reg) & 0xff +} + +// TWAI.DATA_12: Data register 12. +func (o *TWAI_Type) SetDATA_12_TX_BYTE_12(value uint32) { + volatile.StoreUint32(&o.DATA_12.Reg, volatile.LoadUint32(&o.DATA_12.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_12_TX_BYTE_12() uint32 { + return volatile.LoadUint32(&o.DATA_12.Reg) & 0xff +} + +// TWAI.RX_MESSAGE_CNT: Received message counter register. +func (o *TWAI_Type) SetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER(value uint32) { + volatile.StoreUint32(&o.RX_MESSAGE_CNT.Reg, volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg)&^(0x7f)|value) +} +func (o *TWAI_Type) GetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER() uint32 { + return volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg) & 0x7f +} + +// TWAI.CLOCK_DIVIDER: Clock divider register. +func (o *TWAI_Type) SetCLOCK_DIVIDER_CD(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CD() uint32 { + return volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0xff +} +func (o *TWAI_Type) SetCLOCK_DIVIDER_CLOCK_OFF(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CLOCK_OFF() uint32 { + return (volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0x100) >> 8 +} + +// TWAI.SW_STANDBY_CFG: Software configure standby pin directly. +func (o *TWAI_Type) SetSW_STANDBY_CFG_SW_STANDBY_EN(value uint32) { + volatile.StoreUint32(&o.SW_STANDBY_CFG.Reg, volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSW_STANDBY_CFG_SW_STANDBY_EN() uint32 { + return volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg) & 0x1 +} +func (o *TWAI_Type) SetSW_STANDBY_CFG_SW_STANDBY_CLR(value uint32) { + volatile.StoreUint32(&o.SW_STANDBY_CFG.Reg, volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSW_STANDBY_CFG_SW_STANDBY_CLR() uint32 { + return (volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg) & 0x2) >> 1 +} + +// TWAI.HW_CFG: Hardware configure standby pin. +func (o *TWAI_Type) SetHW_CFG_HW_STANDBY_EN(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetHW_CFG_HW_STANDBY_EN() uint32 { + return volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1 +} + +// TWAI.HW_STANDBY_CNT: Configure standby counter. +func (o *TWAI_Type) SetHW_STANDBY_CNT(value uint32) { + volatile.StoreUint32(&o.HW_STANDBY_CNT.Reg, value) +} +func (o *TWAI_Type) GetHW_STANDBY_CNT() uint32 { + return volatile.LoadUint32(&o.HW_STANDBY_CNT.Reg) +} + +// TWAI.IDLE_INTR_CNT: Configure idle interrupt counter. +func (o *TWAI_Type) SetIDLE_INTR_CNT(value uint32) { + volatile.StoreUint32(&o.IDLE_INTR_CNT.Reg, value) +} +func (o *TWAI_Type) GetIDLE_INTR_CNT() uint32 { + return volatile.LoadUint32(&o.IDLE_INTR_CNT.Reg) +} + +// TWAI.ECO_CFG: ECO configuration register. +func (o *TWAI_Type) SetECO_CFG_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.ECO_CFG.Reg, volatile.LoadUint32(&o.ECO_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetECO_CFG_RDN_ENA() uint32 { + return volatile.LoadUint32(&o.ECO_CFG.Reg) & 0x1 +} +func (o *TWAI_Type) SetECO_CFG_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.ECO_CFG.Reg, volatile.LoadUint32(&o.ECO_CFG.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetECO_CFG_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.ECO_CFG.Reg) & 0x2) >> 1 +} + +// UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +type UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV volatile.Register32 // 0x14 + RX_FILT volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0 volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + _ [4]byte + HWFC_CONF volatile.Register32 // 0x2C + SLEEP_CONF0 volatile.Register32 // 0x30 + SLEEP_CONF1 volatile.Register32 // 0x34 + SLEEP_CONF2 volatile.Register32 // 0x38 + SWFC_CONF0 volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + TXBRK_CONF volatile.Register32 // 0x44 + IDLE_CONF volatile.Register32 // 0x48 + RS485_CONF volatile.Register32 // 0x4C + AT_CMD_PRECNT volatile.Register32 // 0x50 + AT_CMD_POSTCNT volatile.Register32 // 0x54 + AT_CMD_GAPTOUT volatile.Register32 // 0x58 + AT_CMD_CHAR volatile.Register32 // 0x5C + MEM_CONF volatile.Register32 // 0x60 + TOUT_CONF volatile.Register32 // 0x64 + MEM_TX_STATUS volatile.Register32 // 0x68 + MEM_RX_STATUS volatile.Register32 // 0x6C + FSM_STATUS volatile.Register32 // 0x70 + POSPULSE volatile.Register32 // 0x74 + NEGPULSE volatile.Register32 // 0x78 + LOWPULSE volatile.Register32 // 0x7C + HIGHPULSE volatile.Register32 // 0x80 + RXD_CNT volatile.Register32 // 0x84 + CLK_CONF volatile.Register32 // 0x88 + DATE volatile.Register32 // 0x8C + AFIFO_STATUS volatile.Register32 // 0x90 + _ [4]byte + REG_UPDATE volatile.Register32 // 0x98 + ID volatile.Register32 // 0x9C +} + +// UART.FIFO: FIFO data register +func (o *UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// UART.INT_RAW: Raw interrupt status +func (o *UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_RAW_RS485_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_RAW_RS485_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_RAW_RS485_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_RAW_RS485_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_RAW_RS485_CLASH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_RAW_RS485_CLASH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// UART.INT_ST: Masked interrupt status +func (o *UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ST_RS485_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ST_RS485_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ST_RS485_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ST_RS485_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ST_RS485_CLASH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ST_RS485_CLASH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// UART.INT_ENA: Interrupt enable bits +func (o *UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ENA_RS485_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ENA_RS485_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ENA_RS485_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ENA_RS485_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ENA_RS485_CLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ENA_RS485_CLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// UART.INT_CLR: Interrupt clear bits +func (o *UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_CLR_RS485_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_CLR_RS485_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_CLR_RS485_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_CLR_RS485_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_CLR_RS485_CLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_CLR_RS485_CLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// UART.CLKDIV: Clock divider configuration +func (o *UART_Type) SetCLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetCLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xfff +} +func (o *UART_Type) SetCLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xf00000)|value<<20) +} +func (o *UART_Type) GetCLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xf00000) >> 20 +} + +// UART.RX_FILT: Rx Filter configuration +func (o *UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT() uint32 { + return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff +} +func (o *UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8 +} + +// UART.STATUS: UART status register +func (o *UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xff +} +func (o *UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xff0000) >> 16 +} +func (o *UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// UART.CONF0: a +func (o *UART_Type) SetCONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetCONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UART_Type) SetCONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetCONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetCONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0xc)|value<<2) +} +func (o *UART_Type) GetCONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0xc) >> 2 +} +func (o *UART_Type) SetCONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x30)|value<<4) +} +func (o *UART_Type) GetCONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x30) >> 4 +} +func (o *UART_Type) SetCONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetCONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetCONF0_IRDA_DPLX(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetCONF0_IRDA_DPLX() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetCONF0_IRDA_TX_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetCONF0_IRDA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetCONF0_IRDA_WCTL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetCONF0_IRDA_WCTL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetCONF0_IRDA_TX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetCONF0_IRDA_TX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetCONF0_IRDA_RX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetCONF0_IRDA_RX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetCONF0_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetCONF0_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetCONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetCONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetCONF0_IRDA_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetCONF0_IRDA_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetCONF0_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetCONF0_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetCONF0_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF0_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF0_DIS_RX_DAT_OVF(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF0_DIS_RX_DAT_OVF() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF0_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF0_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF0_AUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF0_AUTOBAUD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF0_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF0_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetCONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} + +// UART.CONF1: Configuration register 1 +func (o *UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0xff +} +func (o *UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetCONF1_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF1_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF1_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF1_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF1_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF1_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF1_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF1_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF1_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF1_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} + +// UART.HWFC_CONF: Hardware flow-control configuration +func (o *UART_Type) SetHWFC_CONF_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF.Reg, volatile.LoadUint32(&o.HWFC_CONF.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetHWFC_CONF_RX_FLOW_THRHD() uint32 { + return volatile.LoadUint32(&o.HWFC_CONF.Reg) & 0xff +} +func (o *UART_Type) SetHWFC_CONF_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF.Reg, volatile.LoadUint32(&o.HWFC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetHWFC_CONF_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.HWFC_CONF.Reg) & 0x100) >> 8 +} + +// UART.SLEEP_CONF0: UART sleep configure register 0 +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR1(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR1() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff +} +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR2(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR2() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR3(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR3() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff0000) >> 16 +} +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR4(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff000000)|value<<24) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR4() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff000000) >> 24 +} + +// UART.SLEEP_CONF1: UART sleep configure register 1 +func (o *UART_Type) SetSLEEP_CONF1_WK_CHAR0(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF1.Reg, volatile.LoadUint32(&o.SLEEP_CONF1.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSLEEP_CONF1_WK_CHAR0() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF1.Reg) & 0xff +} + +// UART.SLEEP_CONF2: UART sleep configure register 2 +func (o *UART_Type) SetSLEEP_CONF2_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSLEEP_CONF2_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3ff +} +func (o *UART_Type) SetSLEEP_CONF2_RX_WAKE_UP_THRHD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3fc00)|value<<10) +} +func (o *UART_Type) GetSLEEP_CONF2_RX_WAKE_UP_THRHD() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3fc00) >> 10 +} +func (o *UART_Type) SetSLEEP_CONF2_WK_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x1c0000)|value<<18) +} +func (o *UART_Type) GetSLEEP_CONF2_WK_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x1c0000) >> 18 +} +func (o *UART_Type) SetSLEEP_CONF2_WK_CHAR_MASK(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e00000)|value<<21) +} +func (o *UART_Type) GetSLEEP_CONF2_WK_CHAR_MASK() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e00000) >> 21 +} +func (o *UART_Type) SetSLEEP_CONF2_WK_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0xc000000)|value<<26) +} +func (o *UART_Type) GetSLEEP_CONF2_WK_MODE_SEL() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0xc000000) >> 26 +} + +// UART.SWFC_CONF0: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF0_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSWFC_CONF0_XON_CHAR() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0xff +} +func (o *UART_Type) SetSWFC_CONF0_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetSWFC_CONF0_XON_XOFF_STILL_SEND(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetSWFC_CONF0_XON_XOFF_STILL_SEND() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetSWFC_CONF0_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetSWFC_CONF0_SW_FLOW_CON_EN() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetSWFC_CONF0_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetSWFC_CONF0_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetSWFC_CONF0_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetSWFC_CONF0_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetSWFC_CONF0_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetSWFC_CONF0_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetSWFC_CONF0_SEND_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetSWFC_CONF0_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetSWFC_CONF0_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetSWFC_CONF0_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x400000) >> 22 +} + +// UART.SWFC_CONF1: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xff +} +func (o *UART_Type) SetSWFC_CONF1_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSWFC_CONF1_XOFF_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xff00) >> 8 +} + +// UART.TXBRK_CONF: Tx Break character configuration +func (o *UART_Type) SetTXBRK_CONF_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.TXBRK_CONF.Reg, volatile.LoadUint32(&o.TXBRK_CONF.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetTXBRK_CONF_TX_BRK_NUM() uint32 { + return volatile.LoadUint32(&o.TXBRK_CONF.Reg) & 0xff +} + +// UART.IDLE_CONF: Frame-end idle configuration +func (o *UART_Type) SetIDLE_CONF_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetIDLE_CONF_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0x3ff +} +func (o *UART_Type) SetIDLE_CONF_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *UART_Type) GetIDLE_CONF_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xffc00) >> 10 +} + +// UART.RS485_CONF: RS485 mode configuration +func (o *UART_Type) SetRS485_CONF_RS485_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetRS485_CONF_RS485_EN() uint32 { + return volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetRS485_CONF_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetRS485_CONF_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetRS485_CONF_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetRS485_CONF_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetRS485_CONF_RS485TX_RX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetRS485_CONF_RS485TX_RX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetRS485_CONF_RS485RXBY_TX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetRS485_CONF_RS485RXBY_TX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetRS485_CONF_RS485_RX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetRS485_CONF_RS485_RX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetRS485_CONF_RS485_TX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x3c0)|value<<6) +} +func (o *UART_Type) GetRS485_CONF_RS485_TX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x3c0) >> 6 +} + +// UART.AT_CMD_PRECNT: Pre-sequence timing configuration +func (o *UART_Type) SetAT_CMD_PRECNT_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_PRECNT_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg) & 0xffff +} + +// UART.AT_CMD_POSTCNT: Post-sequence timing configuration +func (o *UART_Type) SetAT_CMD_POSTCNT_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_POSTCNT_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg) & 0xffff +} + +// UART.AT_CMD_GAPTOUT: Timeout configuration +func (o *UART_Type) SetAT_CMD_GAPTOUT_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_GAPTOUT_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg) & 0xffff +} + +// UART.AT_CMD_CHAR: AT escape sequence detection configuration +func (o *UART_Type) SetAT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetAT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff +} +func (o *UART_Type) SetAT_CMD_CHAR_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAT_CMD_CHAR_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff00) >> 8 +} + +// UART.MEM_CONF: UART memory power configuration +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26 +} + +// UART.TOUT_CONF: UART threshold and allocation configuration +func (o *UART_Type) SetTOUT_CONF_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF.Reg, volatile.LoadUint32(&o.TOUT_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetTOUT_CONF_RX_TOUT_EN() uint32 { + return volatile.LoadUint32(&o.TOUT_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetTOUT_CONF_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF.Reg, volatile.LoadUint32(&o.TOUT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetTOUT_CONF_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetTOUT_CONF_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF.Reg, volatile.LoadUint32(&o.TOUT_CONF.Reg)&^(0xffc)|value<<2) +} +func (o *UART_Type) GetTOUT_CONF_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF.Reg) & 0xffc) >> 2 +} + +// UART.MEM_TX_STATUS: Tx-SRAM write and read offset address. +func (o *UART_Type) SetMEM_TX_STATUS_TX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_SRAM_WADDR() uint32 { + return volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0xff +} +func (o *UART_Type) SetMEM_TX_STATUS_TX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_SRAM_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1fe00) >> 9 +} + +// UART.MEM_RX_STATUS: Rx-SRAM write and read offset address. +func (o *UART_Type) SetMEM_RX_STATUS_RX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_SRAM_RADDR() uint32 { + return volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xff +} +func (o *UART_Type) SetMEM_RX_STATUS_RX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_SRAM_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1fe00) >> 9 +} + +// UART.FSM_STATUS: UART transmit and receive status. +func (o *UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// UART.POSPULSE: Autobaud high pulse register +func (o *UART_Type) SetPOSPULSE_POSEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.POSPULSE.Reg, volatile.LoadUint32(&o.POSPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetPOSPULSE_POSEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.POSPULSE.Reg) & 0xfff +} + +// UART.NEGPULSE: Autobaud low pulse register +func (o *UART_Type) SetNEGPULSE_NEGEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.NEGPULSE.Reg, volatile.LoadUint32(&o.NEGPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetNEGPULSE_NEGEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.NEGPULSE.Reg) & 0xfff +} + +// UART.LOWPULSE: Autobaud minimum low pulse duration register +func (o *UART_Type) SetLOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.LOWPULSE.Reg, volatile.LoadUint32(&o.LOWPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetLOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.LOWPULSE.Reg) & 0xfff +} + +// UART.HIGHPULSE: Autobaud minimum high pulse duration register +func (o *UART_Type) SetHIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.HIGHPULSE.Reg, volatile.LoadUint32(&o.HIGHPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetHIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.HIGHPULSE.Reg) & 0xfff +} + +// UART.RXD_CNT: Autobaud edge change count register +func (o *UART_Type) SetRXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.RXD_CNT.Reg, volatile.LoadUint32(&o.RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetRXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.RXD_CNT.Reg) & 0x3ff +} + +// UART.CLK_CONF: UART core clock configuration +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f)|value) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f +} +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *UART_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *UART_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *UART_Type) SetCLK_CONF_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCLK_CONF_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCLK_CONF_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCLK_CONF_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} + +// UART.DATE: UART Version register +func (o *UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// UART.AFIFO_STATUS: UART AFIFO Status +func (o *UART_Type) SetAFIFO_STATUS_TX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetAFIFO_STATUS_TX_AFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x1 +} +func (o *UART_Type) SetAFIFO_STATUS_TX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetAFIFO_STATUS_TX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetAFIFO_STATUS_RX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetAFIFO_STATUS_RX_AFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetAFIFO_STATUS_RX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetAFIFO_STATUS_RX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x8) >> 3 +} + +// UART.REG_UPDATE: UART Registers Configuration Update register +func (o *UART_Type) SetREG_UPDATE(value uint32) { + volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetREG_UPDATE() uint32 { + return volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x1 +} + +// UART.ID: UART ID register +func (o *UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, value) +} +func (o *UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) +} + +// Universal Host Controller Interface 0 +type UHCI_Type struct { + CONF0 volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CONF1 volatile.Register32 // 0x14 + STATE0 volatile.Register32 // 0x18 + STATE1 volatile.Register32 // 0x1C + ESCAPE_CONF volatile.Register32 // 0x20 + HUNG_CONF volatile.Register32 // 0x24 + ACK_NUM volatile.Register32 // 0x28 + RX_HEAD volatile.Register32 // 0x2C + QUICK_SENT volatile.Register32 // 0x30 + REG_Q0_WORD0 volatile.Register32 // 0x34 + REG_Q0_WORD1 volatile.Register32 // 0x38 + REG_Q1_WORD0 volatile.Register32 // 0x3C + REG_Q1_WORD1 volatile.Register32 // 0x40 + REG_Q2_WORD0 volatile.Register32 // 0x44 + REG_Q2_WORD1 volatile.Register32 // 0x48 + REG_Q3_WORD0 volatile.Register32 // 0x4C + REG_Q3_WORD1 volatile.Register32 // 0x50 + REG_Q4_WORD0 volatile.Register32 // 0x54 + REG_Q4_WORD1 volatile.Register32 // 0x58 + REG_Q5_WORD0 volatile.Register32 // 0x5C + REG_Q5_WORD1 volatile.Register32 // 0x60 + REG_Q6_WORD0 volatile.Register32 // 0x64 + REG_Q6_WORD1 volatile.Register32 // 0x68 + ESC_CONF0 volatile.Register32 // 0x6C + ESC_CONF1 volatile.Register32 // 0x70 + ESC_CONF2 volatile.Register32 // 0x74 + ESC_CONF3 volatile.Register32 // 0x78 + PKT_THRES volatile.Register32 // 0x7C + DATE volatile.Register32 // 0x80 +} + +// UHCI.CONF0: UHCI Configuration Register0 +func (o *UHCI_Type) SetCONF0_TX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF0_TX_RST() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF0_RX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF0_RX_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF0_UART0_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF0_UART0_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF0_UART1_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF0_UART1_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF0_SEPER_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF0_SEPER_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF0_HEAD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetCONF0_HEAD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetCONF0_CRC_REC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF0_CRC_REC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF0_UART_IDLE_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF0_UART_IDLE_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetCONF0_LEN_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetCONF0_LEN_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetCONF0_ENCODE_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetCONF0_ENCODE_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetCONF0_UART_RX_BRK_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetCONF0_UART_RX_BRK_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} + +// UHCI.INT_RAW: UHCI Interrupt Raw Register +func (o *UHCI_Type) SetINT_RAW_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_RAW_RX_START_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_RAW_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_RAW_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_RAW_SEND_S_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_RAW_SEND_S_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_RAW_SEND_A_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_RAW_SEND_A_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ST: UHCI Interrupt Status Register +func (o *UHCI_Type) SetINT_ST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ST_RX_START_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ST_SEND_S_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ST_SEND_S_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ST_SEND_A_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ST_SEND_A_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ST_OUTLINK_EOF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ST_OUTLINK_EOF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ENA: UHCI Interrupt Enable Register +func (o *UHCI_Type) SetINT_ENA_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ENA_RX_START_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ENA_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ENA_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ENA_SEND_S_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ENA_SEND_S_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ENA_SEND_A_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ENA_SEND_A_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ENA_OUTLINK_EOF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ENA_OUTLINK_EOF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// UHCI.INT_CLR: UHCI Interrupt Clear Register +func (o *UHCI_Type) SetINT_CLR_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_CLR_RX_START_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_CLR_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_CLR_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_CLR_SEND_S_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_CLR_SEND_S_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_CLR_SEND_A_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_CLR_SEND_A_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_CLR_OUTLINK_EOF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_CLR_OUTLINK_EOF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// UHCI.CONF1: UHCI Configuration Register1 +func (o *UHCI_Type) SetCONF1_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF1_CHECK_SUM_EN() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF1_CHECK_SEQ_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF1_CHECK_SEQ_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF1_CRC_DISABLE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF1_CRC_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF1_SAVE_HEAD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF1_SAVE_HEAD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF1_TX_CHECK_SUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF1_TX_CHECK_SUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF1_TX_ACK_NUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF1_TX_ACK_NUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF1_WAIT_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF1_WAIT_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF1_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF1_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8 +} + +// UHCI.STATE0: UHCI Receive Status Register +func (o *UHCI_Type) SetSTATE0_RX_ERR_CAUSE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE0_RX_ERR_CAUSE() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x7 +} +func (o *UHCI_Type) SetSTATE0_DECODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x38)|value<<3) +} +func (o *UHCI_Type) GetSTATE0_DECODE_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x38) >> 3 +} + +// UHCI.STATE1: UHCI Transmit Status Register +func (o *UHCI_Type) SetSTATE1_ENCODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE1_ENCODE_STATE() uint32 { + return volatile.LoadUint32(&o.STATE1.Reg) & 0x7 +} + +// UHCI.ESCAPE_CONF: UHCI Escapes Configuration Register0 +func (o *UHCI_Type) SetESCAPE_CONF_TX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_C0_ESC_EN() uint32 { + return volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_C0_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x80) >> 7 +} + +// UHCI.HUNG_CONF: UHCI Hung Configuration Register0 +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff000) >> 12 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700000) >> 20 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800000) >> 23 +} + +// UHCI.ACK_NUM: UHCI Ack Value Configuration Register0 +func (o *UHCI_Type) SetACK_NUM(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetACK_NUM() uint32 { + return volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x7 +} +func (o *UHCI_Type) SetACK_NUM_LOAD(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetACK_NUM_LOAD() uint32 { + return (volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x8) >> 3 +} + +// UHCI.RX_HEAD: UHCI Head Register +func (o *UHCI_Type) SetRX_HEAD(value uint32) { + volatile.StoreUint32(&o.RX_HEAD.Reg, value) +} +func (o *UHCI_Type) GetRX_HEAD() uint32 { + return volatile.LoadUint32(&o.RX_HEAD.Reg) +} + +// UHCI.QUICK_SENT: UCHI Quick send Register +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_NUM() uint32 { + return volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x7 +} +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x70)|value<<4) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_NUM() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x70) >> 4 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x80) >> 7 +} + +// UHCI.REG_Q0_WORD0: UHCI Q0_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q0_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD0.Reg) +} + +// UHCI.REG_Q0_WORD1: UHCI Q0_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q0_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD1.Reg) +} + +// UHCI.REG_Q1_WORD0: UHCI Q1_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q1_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD0.Reg) +} + +// UHCI.REG_Q1_WORD1: UHCI Q1_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q1_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD1.Reg) +} + +// UHCI.REG_Q2_WORD0: UHCI Q2_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q2_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD0.Reg) +} + +// UHCI.REG_Q2_WORD1: UHCI Q2_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q2_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD1.Reg) +} + +// UHCI.REG_Q3_WORD0: UHCI Q3_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q3_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD0.Reg) +} + +// UHCI.REG_Q3_WORD1: UHCI Q3_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q3_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD1.Reg) +} + +// UHCI.REG_Q4_WORD0: UHCI Q4_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q4_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD0.Reg) +} + +// UHCI.REG_Q4_WORD1: UHCI Q4_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q4_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD1.Reg) +} + +// UHCI.REG_Q5_WORD0: UHCI Q5_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q5_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD0.Reg) +} + +// UHCI.REG_Q5_WORD1: UHCI Q5_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q5_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD1.Reg) +} + +// UHCI.REG_Q6_WORD0: UHCI Q6_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q6_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD0.Reg) +} + +// UHCI.REG_Q6_WORD1: UHCI Q6_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q6_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD1.Reg) +} + +// UHCI.ESC_CONF0: UHCI Escapes Sequence Configuration Register0 +func (o *UHCI_Type) SetESC_CONF0_SEPER_CHAR(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_CHAR() uint32 { + return volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF1: UHCI Escapes Sequence Configuration Register1 +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0() uint32 { + return volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF2: UHCI Escapes Sequence Configuration Register2 +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1() uint32 { + return volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF3: UHCI Escapes Sequence Configuration Register3 +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2() uint32 { + return volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff0000) >> 16 +} + +// UHCI.PKT_THRES: UCHI Packet Length Configuration Register +func (o *UHCI_Type) SetPKT_THRES_PKT_THRS(value uint32) { + volatile.StoreUint32(&o.PKT_THRES.Reg, volatile.LoadUint32(&o.PKT_THRES.Reg)&^(0x1fff)|value) +} +func (o *UHCI_Type) GetPKT_THRES_PKT_THRS() uint32 { + return volatile.LoadUint32(&o.PKT_THRES.Reg) & 0x1fff +} + +// UHCI.DATE: UHCI Version Register +func (o *UHCI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UHCI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Full-speed USB Serial/JTAG Controller +type USB_DEVICE_Type struct { + EP1 volatile.Register32 // 0x0 + EP1_CONF volatile.Register32 // 0x4 + INT_RAW volatile.Register32 // 0x8 + INT_ST volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + INT_CLR volatile.Register32 // 0x14 + CONF0 volatile.Register32 // 0x18 + TEST volatile.Register32 // 0x1C + JFIFO_ST volatile.Register32 // 0x20 + FRAM_NUM volatile.Register32 // 0x24 + IN_EP0_ST volatile.Register32 // 0x28 + IN_EP1_ST volatile.Register32 // 0x2C + IN_EP2_ST volatile.Register32 // 0x30 + IN_EP3_ST volatile.Register32 // 0x34 + OUT_EP0_ST volatile.Register32 // 0x38 + OUT_EP1_ST volatile.Register32 // 0x3C + OUT_EP2_ST volatile.Register32 // 0x40 + MISC_CONF volatile.Register32 // 0x44 + MEM_CONF volatile.Register32 // 0x48 + CHIP_RST volatile.Register32 // 0x4C + SET_LINE_CODE_W0 volatile.Register32 // 0x50 + SET_LINE_CODE_W1 volatile.Register32 // 0x54 + GET_LINE_CODE_W0 volatile.Register32 // 0x58 + GET_LINE_CODE_W1 volatile.Register32 // 0x5C + CONFIG_UPDATE volatile.Register32 // 0x60 + SER_AFIFO_CONFIG volatile.Register32 // 0x64 + BUS_RESET_ST volatile.Register32 // 0x68 + _ [20]byte + DATE volatile.Register32 // 0x80 +} + +// USB_DEVICE.EP1: FIFO access for the CDC-ACM data IN and OUT endpoints. +func (o *USB_DEVICE_Type) SetEP1_RDWR_BYTE(value uint32) { + volatile.StoreUint32(&o.EP1.Reg, volatile.LoadUint32(&o.EP1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetEP1_RDWR_BYTE() uint32 { + return volatile.LoadUint32(&o.EP1.Reg) & 0xff +} + +// USB_DEVICE.EP1_CONF: Configuration and control registers for the CDC-ACM FIFOs. +func (o *USB_DEVICE_Type) SetEP1_CONF_WR_DONE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_WR_DONE() uint32 { + return volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_SERIAL_IN_EP_DATA_FREE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_SERIAL_IN_EP_DATA_FREE() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_SERIAL_OUT_EP_DATA_AVAIL(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_SERIAL_OUT_EP_DATA_AVAIL() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x4) >> 2 +} + +// USB_DEVICE.INT_RAW: Interrupt raw status register. +func (o *USB_DEVICE_Type) SetINT_RAW_JTAG_IN_FLUSH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_RAW_JTAG_IN_FLUSH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SERIAL_IN_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SERIAL_IN_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_RAW_PID_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_RAW_PID_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_RAW_CRC5_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_RAW_CRC5_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_RAW_CRC16_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_RAW_CRC16_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_RAW_STUFF_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_RAW_STUFF_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_BUS_RESET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_BUS_RESET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_RAW_RTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_RAW_RTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_RAW_DTR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_RAW_DTR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_RAW_GET_LINE_CODE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_RAW_GET_LINE_CODE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SET_LINE_CODE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SET_LINE_CODE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.INT_ST: Interrupt status register. +func (o *USB_DEVICE_Type) SetINT_ST_JTAG_IN_FLUSH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ST_JTAG_IN_FLUSH_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ST_SOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ST_SOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ST_SERIAL_OUT_RECV_PKT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ST_SERIAL_OUT_RECV_PKT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ST_SERIAL_IN_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ST_SERIAL_IN_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ST_PID_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ST_PID_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ST_CRC5_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ST_CRC5_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ST_CRC16_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ST_CRC16_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ST_STUFF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ST_STUFF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ST_IN_TOKEN_REC_IN_EP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ST_IN_TOKEN_REC_IN_EP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_BUS_RESET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_BUS_RESET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_ST_RTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_ST_RTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_ST_DTR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_ST_DTR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_ST_GET_LINE_CODE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_ST_GET_LINE_CODE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_ST_SET_LINE_CODE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_ST_SET_LINE_CODE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.INT_ENA: Interrupt enable status register. +func (o *USB_DEVICE_Type) SetINT_ENA_JTAG_IN_FLUSH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ENA_JTAG_IN_FLUSH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SERIAL_IN_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SERIAL_IN_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ENA_PID_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ENA_PID_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ENA_CRC5_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ENA_CRC5_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ENA_CRC16_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ENA_CRC16_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ENA_STUFF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ENA_STUFF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_BUS_RESET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_BUS_RESET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_ENA_RTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_ENA_RTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_ENA_DTR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_ENA_DTR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_ENA_GET_LINE_CODE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_ENA_GET_LINE_CODE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SET_LINE_CODE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SET_LINE_CODE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.INT_CLR: Interrupt clear status register. +func (o *USB_DEVICE_Type) SetINT_CLR_JTAG_IN_FLUSH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_CLR_JTAG_IN_FLUSH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SERIAL_IN_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SERIAL_IN_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_CLR_PID_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_CLR_PID_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_CLR_CRC5_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_CLR_CRC5_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_CLR_CRC16_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_CLR_CRC16_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_CLR_STUFF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_CLR_STUFF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_BUS_RESET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_BUS_RESET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_CLR_RTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_CLR_RTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_CLR_DTR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_CLR_DTR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_CLR_GET_LINE_CODE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_CLR_GET_LINE_CODE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SET_LINE_CODE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SET_LINE_CODE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.CONF0: PHY hardware configuration. +func (o *USB_DEVICE_Type) SetCONF0_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCONF0_PHY_SEL() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetCONF0_EXCHG_PINS_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetCONF0_EXCHG_PINS_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetCONF0_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetCONF0_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetCONF0_VREFH(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x18)|value<<3) +} +func (o *USB_DEVICE_Type) GetCONF0_VREFH() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x18) >> 3 +} +func (o *USB_DEVICE_Type) SetCONF0_VREFL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x60)|value<<5) +} +func (o *USB_DEVICE_Type) GetCONF0_VREFL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x60) >> 5 +} +func (o *USB_DEVICE_Type) SetCONF0_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetCONF0_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetCONF0_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetCONF0_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetCONF0_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetCONF0_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetCONF0_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetCONF0_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetCONF0_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetCONF0_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetCONF0_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetCONF0_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetCONF0_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetCONF0_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_JTAG_BRIDGE_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_JTAG_BRIDGE_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.TEST: Registers used for debugging the PHY. +func (o *USB_DEVICE_Type) SetTEST_TEST_ENABLE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_ENABLE() uint32 { + return volatile.LoadUint32(&o.TEST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_USB_OE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_USB_OE() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_TX_DP(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_TX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_TX_DM(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_TX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_RX_RCV(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_RX_RCV() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_RX_DP(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_RX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_RX_DM(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_RX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x40) >> 6 +} + +// USB_DEVICE.JFIFO_ST: JTAG FIFO status and control registers. +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_CNT() uint32 { + return volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x30)|value<<4) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x30) >> 4 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x200) >> 9 +} + +// USB_DEVICE.FRAM_NUM: Last received SOF frame index register. +func (o *USB_DEVICE_Type) SetFRAM_NUM_SOF_FRAME_INDEX(value uint32) { + volatile.StoreUint32(&o.FRAM_NUM.Reg, volatile.LoadUint32(&o.FRAM_NUM.Reg)&^(0x7ff)|value) +} +func (o *USB_DEVICE_Type) GetFRAM_NUM_SOF_FRAME_INDEX() uint32 { + return volatile.LoadUint32(&o.FRAM_NUM.Reg) & 0x7ff +} + +// USB_DEVICE.IN_EP0_ST: Control IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP1_ST: CDC-ACM IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP2_ST: CDC-ACM interrupt IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP3_ST: JTAG IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP0_ST: Control OUT endpoint status information. +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP1_ST: CDC-ACM OUT endpoint status information. +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0xfe00) >> 9 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_REC_DATA_CNT(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x7f0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_REC_DATA_CNT() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x7f0000) >> 16 +} + +// USB_DEVICE.OUT_EP2_ST: JTAG OUT endpoint status information. +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.MISC_CONF: Clock enable control +func (o *USB_DEVICE_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMISC_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} + +// USB_DEVICE.MEM_CONF: Memory power control +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_MEM_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_MEM_PD() uint32 { + return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2) >> 1 +} + +// USB_DEVICE.CHIP_RST: CDC-ACM chip reset control. +func (o *USB_DEVICE_Type) SetCHIP_RST_RTS(value uint32) { + volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCHIP_RST_RTS() uint32 { + return volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetCHIP_RST_DTR(value uint32) { + volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetCHIP_RST_DTR() uint32 { + return (volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetCHIP_RST_USB_UART_CHIP_RST_DIS(value uint32) { + volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetCHIP_RST_USB_UART_CHIP_RST_DIS() uint32 { + return (volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x4) >> 2 +} + +// USB_DEVICE.SET_LINE_CODE_W0: W0 of SET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W0(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W0.Reg, value) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W0() uint32 { + return volatile.LoadUint32(&o.SET_LINE_CODE_W0.Reg) +} + +// USB_DEVICE.SET_LINE_CODE_W1: W1 of SET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_BCHAR_FORMAT(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_BCHAR_FORMAT() uint32 { + return volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff +} +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_BPARITY_TYPE(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff00)|value<<8) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_BPARITY_TYPE() uint32 { + return (volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff00) >> 8 +} +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_BDATA_BITS(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_BDATA_BITS() uint32 { + return (volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff0000) >> 16 +} + +// USB_DEVICE.GET_LINE_CODE_W0: W0 of GET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W0(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W0.Reg, value) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W0() uint32 { + return volatile.LoadUint32(&o.GET_LINE_CODE_W0.Reg) +} + +// USB_DEVICE.GET_LINE_CODE_W1: W1 of GET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_GET_BDATA_BITS(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_GET_BDATA_BITS() uint32 { + return volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff +} +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_GET_BPARITY_TYPE(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff00)|value<<8) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_GET_BPARITY_TYPE() uint32 { + return (volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff00) >> 8 +} +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_GET_BCHAR_FORMAT(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_GET_BCHAR_FORMAT() uint32 { + return (volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff0000) >> 16 +} + +// USB_DEVICE.CONFIG_UPDATE: Configuration registers' value update +func (o *USB_DEVICE_Type) SetCONFIG_UPDATE(value uint32) { + volatile.StoreUint32(&o.CONFIG_UPDATE.Reg, volatile.LoadUint32(&o.CONFIG_UPDATE.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCONFIG_UPDATE() uint32 { + return volatile.LoadUint32(&o.CONFIG_UPDATE.Reg) & 0x1 +} + +// USB_DEVICE.SER_AFIFO_CONFIG: Serial AFIFO configure register +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR() uint32 { + return volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x20) >> 5 +} + +// USB_DEVICE.BUS_RESET_ST: USB Bus reset status register +func (o *USB_DEVICE_Type) SetBUS_RESET_ST_USB_BUS_RESET_ST(value uint32) { + volatile.StoreUint32(&o.BUS_RESET_ST.Reg, volatile.LoadUint32(&o.BUS_RESET_ST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetBUS_RESET_ST_USB_BUS_RESET_ST() uint32 { + return volatile.LoadUint32(&o.BUS_RESET_ST.Reg) & 0x1 +} + +// USB_DEVICE.DATE: Date register +func (o *USB_DEVICE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *USB_DEVICE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Constants for AES: AES (Advanced Encryption Standard) Accelerator +const ( + // KEY_0: Key material key_0 configure register + // Position of KEY_0 field. + AES_KEY_0_KEY_0_Pos = 0x0 + // Bit mask of KEY_0 field. + AES_KEY_0_KEY_0_Msk = 0xffffffff + + // KEY_1: Key material key_1 configure register + // Position of KEY_1 field. + AES_KEY_1_KEY_1_Pos = 0x0 + // Bit mask of KEY_1 field. + AES_KEY_1_KEY_1_Msk = 0xffffffff + + // KEY_2: Key material key_2 configure register + // Position of KEY_2 field. + AES_KEY_2_KEY_2_Pos = 0x0 + // Bit mask of KEY_2 field. + AES_KEY_2_KEY_2_Msk = 0xffffffff + + // KEY_3: Key material key_3 configure register + // Position of KEY_3 field. + AES_KEY_3_KEY_3_Pos = 0x0 + // Bit mask of KEY_3 field. + AES_KEY_3_KEY_3_Msk = 0xffffffff + + // KEY_4: Key material key_4 configure register + // Position of KEY_4 field. + AES_KEY_4_KEY_4_Pos = 0x0 + // Bit mask of KEY_4 field. + AES_KEY_4_KEY_4_Msk = 0xffffffff + + // KEY_5: Key material key_5 configure register + // Position of KEY_5 field. + AES_KEY_5_KEY_5_Pos = 0x0 + // Bit mask of KEY_5 field. + AES_KEY_5_KEY_5_Msk = 0xffffffff + + // KEY_6: Key material key_6 configure register + // Position of KEY_6 field. + AES_KEY_6_KEY_6_Pos = 0x0 + // Bit mask of KEY_6 field. + AES_KEY_6_KEY_6_Msk = 0xffffffff + + // KEY_7: Key material key_7 configure register + // Position of KEY_7 field. + AES_KEY_7_KEY_7_Pos = 0x0 + // Bit mask of KEY_7 field. + AES_KEY_7_KEY_7_Msk = 0xffffffff + + // TEXT_IN_0: source text material text_in_0 configure register + // Position of TEXT_IN_0 field. + AES_TEXT_IN_0_TEXT_IN_0_Pos = 0x0 + // Bit mask of TEXT_IN_0 field. + AES_TEXT_IN_0_TEXT_IN_0_Msk = 0xffffffff + + // TEXT_IN_1: source text material text_in_1 configure register + // Position of TEXT_IN_1 field. + AES_TEXT_IN_1_TEXT_IN_1_Pos = 0x0 + // Bit mask of TEXT_IN_1 field. + AES_TEXT_IN_1_TEXT_IN_1_Msk = 0xffffffff + + // TEXT_IN_2: source text material text_in_2 configure register + // Position of TEXT_IN_2 field. + AES_TEXT_IN_2_TEXT_IN_2_Pos = 0x0 + // Bit mask of TEXT_IN_2 field. + AES_TEXT_IN_2_TEXT_IN_2_Msk = 0xffffffff + + // TEXT_IN_3: source text material text_in_3 configure register + // Position of TEXT_IN_3 field. + AES_TEXT_IN_3_TEXT_IN_3_Pos = 0x0 + // Bit mask of TEXT_IN_3 field. + AES_TEXT_IN_3_TEXT_IN_3_Msk = 0xffffffff + + // TEXT_OUT_0: result text material text_out_0 configure register + // Position of TEXT_OUT_0 field. + AES_TEXT_OUT_0_TEXT_OUT_0_Pos = 0x0 + // Bit mask of TEXT_OUT_0 field. + AES_TEXT_OUT_0_TEXT_OUT_0_Msk = 0xffffffff + + // TEXT_OUT_1: result text material text_out_1 configure register + // Position of TEXT_OUT_1 field. + AES_TEXT_OUT_1_TEXT_OUT_1_Pos = 0x0 + // Bit mask of TEXT_OUT_1 field. + AES_TEXT_OUT_1_TEXT_OUT_1_Msk = 0xffffffff + + // TEXT_OUT_2: result text material text_out_2 configure register + // Position of TEXT_OUT_2 field. + AES_TEXT_OUT_2_TEXT_OUT_2_Pos = 0x0 + // Bit mask of TEXT_OUT_2 field. + AES_TEXT_OUT_2_TEXT_OUT_2_Msk = 0xffffffff + + // TEXT_OUT_3: result text material text_out_3 configure register + // Position of TEXT_OUT_3 field. + AES_TEXT_OUT_3_TEXT_OUT_3_Pos = 0x0 + // Bit mask of TEXT_OUT_3 field. + AES_TEXT_OUT_3_TEXT_OUT_3_Msk = 0xffffffff + + // MODE: AES Mode register + // Position of MODE field. + AES_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + AES_MODE_MODE_Msk = 0x7 + + // ENDIAN: AES Endian configure register + // Position of ENDIAN field. + AES_ENDIAN_ENDIAN_Pos = 0x0 + // Bit mask of ENDIAN field. + AES_ENDIAN_ENDIAN_Msk = 0x3f + + // TRIGGER: AES trigger register + // Position of TRIGGER field. + AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + AES_TRIGGER_TRIGGER = 0x1 + + // STATE: AES state register + // Position of STATE field. + AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + AES_STATE_STATE_Msk = 0x3 + + // DMA_ENABLE: DMA-AES working mode register + // Position of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Pos = 0x0 + // Bit mask of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Msk = 0x1 + // Bit DMA_ENABLE. + AES_DMA_ENABLE_DMA_ENABLE = 0x1 + + // BLOCK_MODE: AES cipher block mode register + // Position of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Pos = 0x0 + // Bit mask of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Msk = 0x7 + + // BLOCK_NUM: AES block number register + // Position of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Pos = 0x0 + // Bit mask of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Msk = 0xffffffff + + // INC_SEL: Standard incrementing function configure register + // Position of INC_SEL field. + AES_INC_SEL_INC_SEL_Pos = 0x0 + // Bit mask of INC_SEL field. + AES_INC_SEL_INC_SEL_Msk = 0x1 + // Bit INC_SEL. + AES_INC_SEL_INC_SEL = 0x1 + + // AAD_BLOCK_NUM: Additional Authential Data block number register + // Position of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Pos = 0x0 + // Bit mask of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Msk = 0xffffffff + + // REMAINDER_BIT_NUM: AES remainder bit number register + // Position of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Pos = 0x0 + // Bit mask of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Msk = 0x7f + + // CONTINUE: AES continue register + // Position of CONTINUE field. + AES_CONTINUE_CONTINUE_Pos = 0x0 + // Bit mask of CONTINUE field. + AES_CONTINUE_CONTINUE_Msk = 0x1 + // Bit CONTINUE. + AES_CONTINUE_CONTINUE = 0x1 + + // INT_CLEAR: AES Interrupt clear register + // Position of INT_CLEAR field. + AES_INT_CLEAR_INT_CLEAR_Pos = 0x0 + // Bit mask of INT_CLEAR field. + AES_INT_CLEAR_INT_CLEAR_Msk = 0x1 + // Bit INT_CLEAR. + AES_INT_CLEAR_INT_CLEAR = 0x1 + + // INT_ENA: AES Interrupt enable register + // Position of INT_ENA field. + AES_INT_ENA_INT_ENA_Pos = 0x0 + // Bit mask of INT_ENA field. + AES_INT_ENA_INT_ENA_Msk = 0x1 + // Bit INT_ENA. + AES_INT_ENA_INT_ENA = 0x1 + + // DATE: AES version control register + // Position of DATE field. + AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + AES_DATE_DATE_Msk = 0x3fffffff + + // DMA_EXIT: AES-DMA exit config + // Position of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Pos = 0x0 + // Bit mask of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Msk = 0x1 + // Bit DMA_EXIT. + AES_DMA_EXIT_DMA_EXIT = 0x1 +) + +// Constants for APB_SARADC: SAR (Successive Approximation Register) Analog-to-Digital Converter +const ( + // CTRL: digital saradc configure register + // Position of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Pos = 0x0 + // Bit mask of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Msk = 0x1 + // Bit SARADC_START_FORCE. + APB_SARADC_CTRL_SARADC_START_FORCE = 0x1 + // Position of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Pos = 0x1 + // Bit mask of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Msk = 0x2 + // Bit SARADC_START. + APB_SARADC_CTRL_SARADC_START = 0x2 + // Position of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Pos = 0x6 + // Bit mask of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Msk = 0x40 + // Bit SARADC_SAR_CLK_GATED. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED = 0x40 + // Position of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Pos = 0x7 + // Bit mask of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Msk = 0x7f80 + // Position of SARADC_SAR_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR_PATT_LEN_Pos = 0xf + // Bit mask of SARADC_SAR_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR_PATT_LEN_Msk = 0x38000 + // Position of SARADC_SAR_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR_Pos = 0x17 + // Bit mask of SARADC_SAR_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR_Msk = 0x800000 + // Bit SARADC_SAR_PATT_P_CLEAR. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR = 0x800000 + // Position of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Pos = 0x1b + // Bit mask of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Msk = 0x18000000 + // Position of SARADC2_PWDET_DRV field. + APB_SARADC_CTRL_SARADC2_PWDET_DRV_Pos = 0x1d + // Bit mask of SARADC2_PWDET_DRV field. + APB_SARADC_CTRL_SARADC2_PWDET_DRV_Msk = 0x20000000 + // Bit SARADC2_PWDET_DRV. + APB_SARADC_CTRL_SARADC2_PWDET_DRV = 0x20000000 + // Position of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Pos = 0x1e + // Bit mask of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Msk = 0xc0000000 + + // CTRL2: digital saradc configure register + // Position of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Pos = 0x0 + // Bit mask of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Msk = 0x1 + // Bit SARADC_MEAS_NUM_LIMIT. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT = 0x1 + // Position of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Pos = 0x1 + // Bit mask of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Msk = 0x1fe + // Position of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Pos = 0x9 + // Bit mask of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Msk = 0x200 + // Bit SARADC_SAR1_INV. + APB_SARADC_CTRL2_SARADC_SAR1_INV = 0x200 + // Position of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Pos = 0xa + // Bit mask of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Msk = 0x400 + // Bit SARADC_SAR2_INV. + APB_SARADC_CTRL2_SARADC_SAR2_INV = 0x400 + // Position of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Pos = 0xc + // Bit mask of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Msk = 0xfff000 + // Position of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Pos = 0x18 + // Bit mask of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Msk = 0x1000000 + // Bit SARADC_TIMER_EN. + APB_SARADC_CTRL2_SARADC_TIMER_EN = 0x1000000 + + // FILTER_CTRL1: digital saradc configure register + // Position of APB_SARADC_FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR1_Pos = 0x1a + // Bit mask of APB_SARADC_FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR1_Msk = 0x1c000000 + // Position of APB_SARADC_FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR0_Pos = 0x1d + // Bit mask of APB_SARADC_FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR0_Msk = 0xe0000000 + + // FSM_WAIT: digital saradc configure register + // Position of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Pos = 0x0 + // Bit mask of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Msk = 0xff + // Position of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Pos = 0x8 + // Bit mask of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Msk = 0xff00 + // Position of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Pos = 0x10 + // Bit mask of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Msk = 0xff0000 + + // SAR1_STATUS: digital saradc configure register + // Position of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Msk = 0xffffffff + + // SAR2_STATUS: digital saradc configure register + // Position of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Msk = 0xffffffff + + // SAR_PATT_TAB1: digital saradc configure register + // Position of SARADC_SAR_PATT_TAB1 field. + APB_SARADC_SAR_PATT_TAB1_SARADC_SAR_PATT_TAB1_Pos = 0x0 + // Bit mask of SARADC_SAR_PATT_TAB1 field. + APB_SARADC_SAR_PATT_TAB1_SARADC_SAR_PATT_TAB1_Msk = 0xffffff + + // SAR_PATT_TAB2: digital saradc configure register + // Position of SARADC_SAR_PATT_TAB2 field. + APB_SARADC_SAR_PATT_TAB2_SARADC_SAR_PATT_TAB2_Pos = 0x0 + // Bit mask of SARADC_SAR_PATT_TAB2 field. + APB_SARADC_SAR_PATT_TAB2_SARADC_SAR_PATT_TAB2_Msk = 0xffffff + + // ONETIME_SAMPLE: digital saradc configure register + // Position of SARADC_ONETIME_ATTEN field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_ATTEN_Pos = 0x17 + // Bit mask of SARADC_ONETIME_ATTEN field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_ATTEN_Msk = 0x1800000 + // Position of SARADC_ONETIME_CHANNEL field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_CHANNEL_Pos = 0x19 + // Bit mask of SARADC_ONETIME_CHANNEL field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_CHANNEL_Msk = 0x1e000000 + // Position of SARADC_ONETIME_START field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START_Pos = 0x1d + // Bit mask of SARADC_ONETIME_START field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START_Msk = 0x20000000 + // Bit SARADC_ONETIME_START. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START = 0x20000000 + // Position of SARADC2_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE_Pos = 0x1e + // Bit mask of SARADC2_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE_Msk = 0x40000000 + // Bit SARADC2_ONETIME_SAMPLE. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE = 0x40000000 + // Position of SARADC1_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE_Pos = 0x1f + // Bit mask of SARADC1_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE_Msk = 0x80000000 + // Bit SARADC1_ONETIME_SAMPLE. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE = 0x80000000 + + // ARB_CTRL: digital saradc configure register + // Position of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Pos = 0x2 + // Bit mask of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Msk = 0x4 + // Bit ADC_ARB_APB_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE = 0x4 + // Position of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Pos = 0x3 + // Bit mask of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Msk = 0x8 + // Bit ADC_ARB_RTC_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE = 0x8 + // Position of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Pos = 0x4 + // Bit mask of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Msk = 0x10 + // Bit ADC_ARB_WIFI_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE = 0x10 + // Position of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Pos = 0x5 + // Bit mask of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Msk = 0x20 + // Bit ADC_ARB_GRANT_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE = 0x20 + // Position of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Pos = 0x6 + // Bit mask of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Msk = 0xc0 + // Position of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Pos = 0x8 + // Bit mask of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Msk = 0x300 + // Position of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Pos = 0xa + // Bit mask of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Msk = 0xc00 + // Position of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Pos = 0xc + // Bit mask of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Msk = 0x1000 + // Bit ADC_ARB_FIX_PRIORITY. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY = 0x1000 + + // FILTER_CTRL0: digital saradc configure register + // Position of APB_SARADC_FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1_Pos = 0x12 + // Bit mask of APB_SARADC_FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1_Msk = 0x3c0000 + // Position of APB_SARADC_FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0_Pos = 0x16 + // Bit mask of APB_SARADC_FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0_Msk = 0x3c00000 + // Position of APB_SARADC_FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_RESET_Pos = 0x1f + // Bit mask of APB_SARADC_FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_RESET_Msk = 0x80000000 + // Bit APB_SARADC_FILTER_RESET. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_RESET = 0x80000000 + + // SAR1DATA_STATUS: digital saradc configure register + // Position of APB_SARADC1_DATA field. + APB_SARADC_SAR1DATA_STATUS_APB_SARADC1_DATA_Pos = 0x0 + // Bit mask of APB_SARADC1_DATA field. + APB_SARADC_SAR1DATA_STATUS_APB_SARADC1_DATA_Msk = 0x1ffff + + // SAR2DATA_STATUS: digital saradc configure register + // Position of APB_SARADC2_DATA field. + APB_SARADC_SAR2DATA_STATUS_APB_SARADC2_DATA_Pos = 0x0 + // Bit mask of APB_SARADC2_DATA field. + APB_SARADC_SAR2DATA_STATUS_APB_SARADC2_DATA_Msk = 0x1ffff + + // THRES0_CTRL: digital saradc configure register + // Position of APB_SARADC_THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_CHANNEL_Pos = 0x0 + // Bit mask of APB_SARADC_THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_CHANNEL_Msk = 0xf + // Position of APB_SARADC_THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_HIGH_Pos = 0x5 + // Bit mask of APB_SARADC_THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_HIGH_Msk = 0x3ffe0 + // Position of APB_SARADC_THRES0_LOW field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_LOW_Pos = 0x12 + // Bit mask of APB_SARADC_THRES0_LOW field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_LOW_Msk = 0x7ffc0000 + + // THRES1_CTRL: digital saradc configure register + // Position of APB_SARADC_THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_CHANNEL_Pos = 0x0 + // Bit mask of APB_SARADC_THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_CHANNEL_Msk = 0xf + // Position of APB_SARADC_THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_HIGH_Pos = 0x5 + // Bit mask of APB_SARADC_THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_HIGH_Msk = 0x3ffe0 + // Position of APB_SARADC_THRES1_LOW field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_LOW_Pos = 0x12 + // Bit mask of APB_SARADC_THRES1_LOW field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_LOW_Msk = 0x7ffc0000 + + // THRES_CTRL: digital saradc configure register + // Position of APB_SARADC_THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES_ALL_EN_Pos = 0x1b + // Bit mask of APB_SARADC_THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES_ALL_EN_Msk = 0x8000000 + // Bit APB_SARADC_THRES_ALL_EN. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES_ALL_EN = 0x8000000 + // Position of APB_SARADC_THRES1_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES1_EN_Pos = 0x1e + // Bit mask of APB_SARADC_THRES1_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES1_EN_Msk = 0x40000000 + // Bit APB_SARADC_THRES1_EN. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES1_EN = 0x40000000 + // Position of APB_SARADC_THRES0_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES0_EN_Pos = 0x1f + // Bit mask of APB_SARADC_THRES0_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES0_EN_Msk = 0x80000000 + // Bit APB_SARADC_THRES0_EN. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES0_EN = 0x80000000 + + // INT_ENA: digital saradc int register + // Position of APB_SARADC_TSENS_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_TSENS_INT_ENA_Pos = 0x19 + // Bit mask of APB_SARADC_TSENS_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_TSENS_INT_ENA_Msk = 0x2000000 + // Bit APB_SARADC_TSENS_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_TSENS_INT_ENA = 0x2000000 + // Position of APB_SARADC_THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_LOW_INT_ENA_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_LOW_INT_ENA_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_LOW_INT_ENA = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_LOW_INT_ENA_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_LOW_INT_ENA_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_LOW_INT_ENA = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA = 0x80000000 + + // INT_RAW: digital saradc int register + // Position of APB_SARADC_TSENS_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_TSENS_INT_RAW_Pos = 0x19 + // Bit mask of APB_SARADC_TSENS_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_TSENS_INT_RAW_Msk = 0x2000000 + // Bit APB_SARADC_TSENS_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_TSENS_INT_RAW = 0x2000000 + // Position of APB_SARADC_THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_LOW_INT_RAW_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_LOW_INT_RAW_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_LOW_INT_RAW = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_LOW_INT_RAW_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_LOW_INT_RAW_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_LOW_INT_RAW = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW = 0x20000000 + // Position of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW = 0x40000000 + // Position of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW = 0x80000000 + + // INT_ST: digital saradc int register + // Position of APB_SARADC_TSENS_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_TSENS_INT_ST_Pos = 0x19 + // Bit mask of APB_SARADC_TSENS_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_TSENS_INT_ST_Msk = 0x2000000 + // Bit APB_SARADC_TSENS_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_TSENS_INT_ST = 0x2000000 + // Position of APB_SARADC_THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_LOW_INT_ST_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_LOW_INT_ST_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES1_LOW_INT_ST = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_LOW_INT_ST_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_LOW_INT_ST_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES0_LOW_INT_ST = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_HIGH_INT_ST_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_HIGH_INT_ST_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES1_HIGH_INT_ST = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_HIGH_INT_ST_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_HIGH_INT_ST_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES0_HIGH_INT_ST = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST = 0x80000000 + + // INT_CLR: digital saradc int register + // Position of APB_SARADC_TSENS_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_TSENS_INT_CLR_Pos = 0x19 + // Bit mask of APB_SARADC_TSENS_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_TSENS_INT_CLR_Msk = 0x2000000 + // Bit APB_SARADC_TSENS_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_TSENS_INT_CLR = 0x2000000 + // Position of APB_SARADC_THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_LOW_INT_CLR_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_LOW_INT_CLR_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_LOW_INT_CLR = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_LOW_INT_CLR_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_LOW_INT_CLR_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_LOW_INT_CLR = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR = 0x20000000 + // Position of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR = 0x40000000 + // Position of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR = 0x80000000 + + // DMA_CONF: digital saradc configure register + // Position of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Pos = 0x0 + // Bit mask of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Msk = 0xffff + // Position of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Pos = 0x1e + // Bit mask of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Msk = 0x40000000 + // Bit APB_ADC_RESET_FSM. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM = 0x40000000 + // Position of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Pos = 0x1f + // Bit mask of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Msk = 0x80000000 + // Bit APB_ADC_TRANS. + APB_SARADC_DMA_CONF_APB_ADC_TRANS = 0x80000000 + + // CLKM_CONF: digital saradc configure register + // Position of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Msk = 0xff + // Position of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Pos = 0x8 + // Bit mask of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Msk = 0x3f00 + // Position of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Pos = 0xe + // Bit mask of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Msk = 0xfc000 + // Position of CLK_EN field. + APB_SARADC_CLKM_CONF_CLK_EN_Pos = 0x14 + // Bit mask of CLK_EN field. + APB_SARADC_CLKM_CONF_CLK_EN_Msk = 0x100000 + // Bit CLK_EN. + APB_SARADC_CLKM_CONF_CLK_EN = 0x100000 + // Position of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Pos = 0x15 + // Bit mask of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Msk = 0x600000 + + // APB_TSENS_CTRL: digital tsens configure register + // Position of TSENS_OUT field. + APB_SARADC_APB_TSENS_CTRL_TSENS_OUT_Pos = 0x0 + // Bit mask of TSENS_OUT field. + APB_SARADC_APB_TSENS_CTRL_TSENS_OUT_Msk = 0xff + // Position of TSENS_IN_INV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_IN_INV_Pos = 0xd + // Bit mask of TSENS_IN_INV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_IN_INV_Msk = 0x2000 + // Bit TSENS_IN_INV. + APB_SARADC_APB_TSENS_CTRL_TSENS_IN_INV = 0x2000 + // Position of TSENS_CLK_DIV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_CLK_DIV_Pos = 0xe + // Bit mask of TSENS_CLK_DIV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_CLK_DIV_Msk = 0x3fc000 + // Position of TSENS_PU field. + APB_SARADC_APB_TSENS_CTRL_TSENS_PU_Pos = 0x16 + // Bit mask of TSENS_PU field. + APB_SARADC_APB_TSENS_CTRL_TSENS_PU_Msk = 0x400000 + // Bit TSENS_PU. + APB_SARADC_APB_TSENS_CTRL_TSENS_PU = 0x400000 + + // TSENS_CTRL2: digital tsens configure register + // Position of TSENS_XPD_WAIT field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_WAIT_Pos = 0x0 + // Bit mask of TSENS_XPD_WAIT field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_WAIT_Msk = 0xfff + // Position of TSENS_XPD_FORCE field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_FORCE_Pos = 0xc + // Bit mask of TSENS_XPD_FORCE field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_FORCE_Msk = 0x3000 + // Position of TSENS_CLK_INV field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_INV_Pos = 0xe + // Bit mask of TSENS_CLK_INV field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_INV_Msk = 0x4000 + // Bit TSENS_CLK_INV. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_INV = 0x4000 + // Position of TSENS_CLK_SEL field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_SEL_Pos = 0xf + // Bit mask of TSENS_CLK_SEL field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_SEL_Msk = 0x8000 + // Bit TSENS_CLK_SEL. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_SEL = 0x8000 + + // CALI: digital saradc configure register + // Position of APB_SARADC_CALI_CFG field. + APB_SARADC_CALI_APB_SARADC_CALI_CFG_Pos = 0x0 + // Bit mask of APB_SARADC_CALI_CFG field. + APB_SARADC_CALI_APB_SARADC_CALI_CFG_Msk = 0x1ffff + + // APB_TSENS_WAKE: digital tsens configure register + // Position of WAKEUP_TH_LOW field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_TH_LOW_Pos = 0x0 + // Bit mask of WAKEUP_TH_LOW field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_TH_LOW_Msk = 0xff + // Position of WAKEUP_TH_HIGH field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_TH_HIGH_Pos = 0x8 + // Bit mask of WAKEUP_TH_HIGH field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_TH_HIGH_Msk = 0xff00 + // Position of WAKEUP_OVER_UPPER_TH field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH_Pos = 0x10 + // Bit mask of WAKEUP_OVER_UPPER_TH field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH_Msk = 0x10000 + // Bit WAKEUP_OVER_UPPER_TH. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH = 0x10000 + // Position of WAKEUP_MODE field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_MODE_Pos = 0x11 + // Bit mask of WAKEUP_MODE field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_MODE_Msk = 0x20000 + // Bit WAKEUP_MODE. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_MODE = 0x20000 + // Position of WAKEUP_EN field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_EN_Pos = 0x12 + // Bit mask of WAKEUP_EN field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_EN_Msk = 0x40000 + // Bit WAKEUP_EN. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_EN = 0x40000 + + // APB_TSENS_SAMPLE: digital tsens configure register + // Position of TSENS_SAMPLE_RATE field. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_RATE_Pos = 0x0 + // Bit mask of TSENS_SAMPLE_RATE field. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_RATE_Msk = 0xffff + // Position of TSENS_SAMPLE_EN field. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_EN_Pos = 0x10 + // Bit mask of TSENS_SAMPLE_EN field. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_EN_Msk = 0x10000 + // Bit TSENS_SAMPLE_EN. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_EN = 0x10000 + + // CTRL_DATE: version + // Position of DATE field. + APB_SARADC_CTRL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + APB_SARADC_CTRL_DATE_DATE_Msk = 0xffffffff +) + +// Constants for ASSIST_DEBUG: Debug Assist +const ( + // CORE_0_MONTR_ENA: core0 monitor enable configuration register + // Position of CORE_0_AREA_DRAM0_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA = 0x80 + // Position of CORE_0_SP_SPILL_MIN_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA = 0x100 + // Position of CORE_0_SP_SPILL_MAX_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA = 0x800 + + // CORE_0_INTR_RAW: core0 monitor interrupt status register + // Position of CORE_0_AREA_DRAM0_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW = 0x80 + // Position of CORE_0_SP_SPILL_MIN_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW = 0x100 + // Position of CORE_0_SP_SPILL_MAX_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW = 0x800 + + // CORE_0_INTR_ENA: core0 monitor interrupt enable register + // Position of CORE_0_AREA_DRAM0_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA = 0x80 + // Position of CORE_0_SP_SPILL_MIN_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA = 0x100 + // Position of CORE_0_SP_SPILL_MAX_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA = 0x800 + + // CORE_0_INTR_CLR: core0 monitor interrupt clr register + // Position of CORE_0_AREA_DRAM0_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR = 0x80 + // Position of CORE_0_SP_SPILL_MIN_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR = 0x100 + // Position of CORE_0_SP_SPILL_MAX_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR = 0x800 + + // CORE_0_AREA_DRAM0_0_MIN: core0 dram0 region0 addr configuration register + // Position of CORE_0_AREA_DRAM0_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_0_MAX: core0 dram0 region0 addr configuration register + // Position of CORE_0_AREA_DRAM0_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_1_MIN: core0 dram0 region1 addr configuration register + // Position of CORE_0_AREA_DRAM0_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_1_MAX: core0 dram0 region1 addr configuration register + // Position of CORE_0_AREA_DRAM0_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PIF_0_MIN: core0 PIF region0 addr configuration register + // Position of CORE_0_AREA_PIF_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Msk = 0xffffffff + + // CORE_0_AREA_PIF_0_MAX: core0 PIF region0 addr configuration register + // Position of CORE_0_AREA_PIF_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PIF_1_MIN: core0 PIF region1 addr configuration register + // Position of CORE_0_AREA_PIF_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Msk = 0xffffffff + + // CORE_0_AREA_PIF_1_MAX: core0 PIF region1 addr configuration register + // Position of CORE_0_AREA_PIF_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PC: core0 area pc status register + // Position of CORE_0_AREA_PC field. + ASSIST_DEBUG_CORE_0_AREA_PC_CORE_0_AREA_PC_Pos = 0x0 + // Bit mask of CORE_0_AREA_PC field. + ASSIST_DEBUG_CORE_0_AREA_PC_CORE_0_AREA_PC_Msk = 0xffffffff + + // CORE_0_AREA_SP: core0 area sp status register + // Position of CORE_0_AREA_SP field. + ASSIST_DEBUG_CORE_0_AREA_SP_CORE_0_AREA_SP_Pos = 0x0 + // Bit mask of CORE_0_AREA_SP field. + ASSIST_DEBUG_CORE_0_AREA_SP_CORE_0_AREA_SP_Msk = 0xffffffff + + // CORE_0_SP_MIN: stack min value + // Position of CORE_0_SP_MIN field. + ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Pos = 0x0 + // Bit mask of CORE_0_SP_MIN field. + ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Msk = 0xffffffff + + // CORE_0_SP_MAX: stack max value + // Position of CORE_0_SP_MAX field. + ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Pos = 0x0 + // Bit mask of CORE_0_SP_MAX field. + ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Msk = 0xffffffff + + // CORE_0_SP_PC: stack monitor pc status register + // Position of CORE_0_SP_PC field. + ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Pos = 0x0 + // Bit mask of CORE_0_SP_PC field. + ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Msk = 0xffffffff + + // CORE_0_RCD_EN: record enable configuration register + // Position of CORE_0_RCD_RECORDEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Pos = 0x0 + // Bit mask of CORE_0_RCD_RECORDEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Msk = 0x1 + // Bit CORE_0_RCD_RECORDEN. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN = 0x1 + // Position of CORE_0_RCD_PDEBUGEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Pos = 0x1 + // Bit mask of CORE_0_RCD_PDEBUGEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Msk = 0x2 + // Bit CORE_0_RCD_PDEBUGEN. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN = 0x2 + + // CORE_0_RCD_PDEBUGPC: record status regsiter + // Position of CORE_0_RCD_PDEBUGPC field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGPC field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGSP: record status regsiter + // Position of CORE_0_RCD_PDEBUGSP field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGSP field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Msk = 0xffffffff + + // CORE_0_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0 + // Position of CORE_0_IRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Msk = 0xffffff + // Position of CORE_0_IRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Pos = 0x18 + // Bit mask of CORE_0_IRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Msk = 0x1000000 + // Bit CORE_0_IRAM0_RECORDING_WR_0. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0 = 0x1000000 + // Position of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Pos = 0x19 + // Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Msk = 0x2000000 + // Bit CORE_0_IRAM0_RECORDING_LOADSTORE_0. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0 = 0x2000000 + + // CORE_0_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1 + // Position of CORE_0_IRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Msk = 0xffffff + // Position of CORE_0_IRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Pos = 0x18 + // Bit mask of CORE_0_IRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Msk = 0x1000000 + // Bit CORE_0_IRAM0_RECORDING_WR_1. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1 = 0x1000000 + // Position of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Pos = 0x19 + // Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Msk = 0x2000000 + // Bit CORE_0_IRAM0_RECORDING_LOADSTORE_1. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1 = 0x2000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2 + // Position of CORE_0_DRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0_Msk = 0xffffff + // Position of CORE_0_DRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Pos = 0x18 + // Bit mask of CORE_0_DRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Msk = 0x1000000 + // Bit CORE_0_DRAM0_RECORDING_WR_0. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0 = 0x1000000 + // Position of CORE_0_DRAM0_RECORDING_BYTEEN_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0_Pos = 0x19 + // Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0_Msk = 0x1e000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3 + // Position of CORE_0_DRAM0_RECORDING_PC_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_PC_0_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_PC_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_PC_0_Msk = 0xffffffff + + // CORE_0_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4 + // Position of CORE_0_DRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1_Msk = 0xffffff + // Position of CORE_0_DRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1_Pos = 0x18 + // Bit mask of CORE_0_DRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1_Msk = 0x1000000 + // Bit CORE_0_DRAM0_RECORDING_WR_1. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1 = 0x1000000 + // Position of CORE_0_DRAM0_RECORDING_BYTEEN_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1_Pos = 0x19 + // Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1_Msk = 0x1e000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5 + // Position of CORE_0_DRAM0_RECORDING_PC_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_PC_1_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_PC_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_PC_1_Msk = 0xffffffff + + // CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register6 + // Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Msk = 0xfffff + + // CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register7 + // Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Msk = 0xfffff + + // C0RE_0_LASTPC_BEFORE_EXCEPTION: cpu status register + // Position of CORE_0_LASTPC_BEFORE_EXC field. + ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Pos = 0x0 + // Bit mask of CORE_0_LASTPC_BEFORE_EXC field. + ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Msk = 0xffffffff + + // C0RE_0_DEBUG_MODE: cpu status register + // Position of CORE_0_DEBUG_MODE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Pos = 0x0 + // Bit mask of CORE_0_DEBUG_MODE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Msk = 0x1 + // Bit CORE_0_DEBUG_MODE. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE = 0x1 + // Position of CORE_0_DEBUG_MODULE_ACTIVE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Pos = 0x1 + // Bit mask of CORE_0_DEBUG_MODULE_ACTIVE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Msk = 0x2 + // Bit CORE_0_DEBUG_MODULE_ACTIVE. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE = 0x2 + + // CLOCK_GATE: clock register + // Position of CLK_EN field. + ASSIST_DEBUG_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + ASSIST_DEBUG_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + ASSIST_DEBUG_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: version register + // Position of ASSIST_DEBUG_DATE field. + ASSIST_DEBUG_DATE_ASSIST_DEBUG_DATE_Pos = 0x0 + // Bit mask of ASSIST_DEBUG_DATE field. + ASSIST_DEBUG_DATE_ASSIST_DEBUG_DATE_Msk = 0xfffffff +) + +// Constants for ATOMIC: Atomic Locker +const ( + // ADDR_LOCK: hardware lock regsiter + // Position of LOCK field. + ATOMIC_ADDR_LOCK_LOCK_Pos = 0x0 + // Bit mask of LOCK field. + ATOMIC_ADDR_LOCK_LOCK_Msk = 0x3 + + // LR_ADDR: gloable lr address regsiter + // Position of GLOABLE_LR_ADDR field. + ATOMIC_LR_ADDR_GLOABLE_LR_ADDR_Pos = 0x0 + // Bit mask of GLOABLE_LR_ADDR field. + ATOMIC_LR_ADDR_GLOABLE_LR_ADDR_Msk = 0xffffffff + + // LR_VALUE: gloable lr value regsiter + // Position of GLOABLE_LR_VALUE field. + ATOMIC_LR_VALUE_GLOABLE_LR_VALUE_Pos = 0x0 + // Bit mask of GLOABLE_LR_VALUE field. + ATOMIC_LR_VALUE_GLOABLE_LR_VALUE_Msk = 0xffffffff + + // LOCK_STATUS: lock status regsiter + // Position of LOCK_STATUS field. + ATOMIC_LOCK_STATUS_LOCK_STATUS_Pos = 0x0 + // Bit mask of LOCK_STATUS field. + ATOMIC_LOCK_STATUS_LOCK_STATUS_Msk = 0x3 + + // COUNTER: wait counter register + // Position of WAIT_COUNTER field. + ATOMIC_COUNTER_WAIT_COUNTER_Pos = 0x0 + // Bit mask of WAIT_COUNTER field. + ATOMIC_COUNTER_WAIT_COUNTER_Msk = 0xffff +) + +// Constants for DMA: DMA (Direct Memory Access) Controller +const ( + // IN_INT_RAW_CH0: Raw status interrupt of channel 0 + // Position of IN_DONE field. + DMA_IN_INT_RAW_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_RAW_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_RAW_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_RAW_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_RAW_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_RAW_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_RAW_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_RAW_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_RAW_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_RAW_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_RAW_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_RAW_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_OVF field. + DMA_IN_INT_RAW_CH_INFIFO_OVF_Pos = 0x5 + // Bit mask of INFIFO_OVF field. + DMA_IN_INT_RAW_CH_INFIFO_OVF_Msk = 0x20 + // Bit INFIFO_OVF. + DMA_IN_INT_RAW_CH_INFIFO_OVF = 0x20 + // Position of INFIFO_UDF field. + DMA_IN_INT_RAW_CH_INFIFO_UDF_Pos = 0x6 + // Bit mask of INFIFO_UDF field. + DMA_IN_INT_RAW_CH_INFIFO_UDF_Msk = 0x40 + // Bit INFIFO_UDF. + DMA_IN_INT_RAW_CH_INFIFO_UDF = 0x40 + + // IN_INT_ST_CH0: Masked interrupt of channel 0 + // Position of IN_DONE field. + DMA_IN_INT_ST_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_ST_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_ST_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_ST_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_ST_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_ST_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_ST_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_ST_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_ST_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_ST_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_ST_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_ST_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_ST_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_OVF field. + DMA_IN_INT_ST_CH_INFIFO_OVF_Pos = 0x5 + // Bit mask of INFIFO_OVF field. + DMA_IN_INT_ST_CH_INFIFO_OVF_Msk = 0x20 + // Bit INFIFO_OVF. + DMA_IN_INT_ST_CH_INFIFO_OVF = 0x20 + // Position of INFIFO_UDF field. + DMA_IN_INT_ST_CH_INFIFO_UDF_Pos = 0x6 + // Bit mask of INFIFO_UDF field. + DMA_IN_INT_ST_CH_INFIFO_UDF_Msk = 0x40 + // Bit INFIFO_UDF. + DMA_IN_INT_ST_CH_INFIFO_UDF = 0x40 + + // IN_INT_ENA_CH0: Interrupt enable bits of channel 0 + // Position of IN_DONE field. + DMA_IN_INT_ENA_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_ENA_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_ENA_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_ENA_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_ENA_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_ENA_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_ENA_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_ENA_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_ENA_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_ENA_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_ENA_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_ENA_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_OVF field. + DMA_IN_INT_ENA_CH_INFIFO_OVF_Pos = 0x5 + // Bit mask of INFIFO_OVF field. + DMA_IN_INT_ENA_CH_INFIFO_OVF_Msk = 0x20 + // Bit INFIFO_OVF. + DMA_IN_INT_ENA_CH_INFIFO_OVF = 0x20 + // Position of INFIFO_UDF field. + DMA_IN_INT_ENA_CH_INFIFO_UDF_Pos = 0x6 + // Bit mask of INFIFO_UDF field. + DMA_IN_INT_ENA_CH_INFIFO_UDF_Msk = 0x40 + // Bit INFIFO_UDF. + DMA_IN_INT_ENA_CH_INFIFO_UDF = 0x40 + + // IN_INT_CLR_CH0: Interrupt clear bits of channel 0 + // Position of IN_DONE field. + DMA_IN_INT_CLR_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_CLR_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_CLR_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_CLR_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_CLR_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_CLR_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_CLR_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_CLR_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_CLR_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_CLR_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_CLR_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_CLR_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_OVF field. + DMA_IN_INT_CLR_CH_INFIFO_OVF_Pos = 0x5 + // Bit mask of INFIFO_OVF field. + DMA_IN_INT_CLR_CH_INFIFO_OVF_Msk = 0x20 + // Bit INFIFO_OVF. + DMA_IN_INT_CLR_CH_INFIFO_OVF = 0x20 + // Position of INFIFO_UDF field. + DMA_IN_INT_CLR_CH_INFIFO_UDF_Pos = 0x6 + // Bit mask of INFIFO_UDF field. + DMA_IN_INT_CLR_CH_INFIFO_UDF_Msk = 0x40 + // Bit INFIFO_UDF. + DMA_IN_INT_CLR_CH_INFIFO_UDF = 0x40 + + // OUT_INT_RAW_CH0: Raw status interrupt of channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_RAW_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_RAW_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_RAW_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_RAW_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_RAW_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_RAW_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF field. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_Pos = 0x4 + // Bit mask of OUTFIFO_OVF field. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_Msk = 0x10 + // Bit OUTFIFO_OVF. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF = 0x10 + // Position of OUTFIFO_UDF field. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_Pos = 0x5 + // Bit mask of OUTFIFO_UDF field. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_Msk = 0x20 + // Bit OUTFIFO_UDF. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF = 0x20 + + // OUT_INT_ST_CH0: Masked interrupt of channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_ST_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_ST_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_ST_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_ST_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_ST_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_ST_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_ST_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF field. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_Pos = 0x4 + // Bit mask of OUTFIFO_OVF field. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_Msk = 0x10 + // Bit OUTFIFO_OVF. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF = 0x10 + // Position of OUTFIFO_UDF field. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_Pos = 0x5 + // Bit mask of OUTFIFO_UDF field. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_Msk = 0x20 + // Bit OUTFIFO_UDF. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF = 0x20 + + // OUT_INT_ENA_CH0: Interrupt enable bits of channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_ENA_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_ENA_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_ENA_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_ENA_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_ENA_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_ENA_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF field. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_Pos = 0x4 + // Bit mask of OUTFIFO_OVF field. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_Msk = 0x10 + // Bit OUTFIFO_OVF. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF = 0x10 + // Position of OUTFIFO_UDF field. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_Pos = 0x5 + // Bit mask of OUTFIFO_UDF field. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_Msk = 0x20 + // Bit OUTFIFO_UDF. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF = 0x20 + + // OUT_INT_CLR_CH0: Interrupt clear bits of channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_CLR_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_CLR_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_CLR_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_CLR_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_CLR_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_CLR_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF field. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_Pos = 0x4 + // Bit mask of OUTFIFO_OVF field. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_Msk = 0x10 + // Bit OUTFIFO_OVF. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF = 0x10 + // Position of OUTFIFO_UDF field. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_Pos = 0x5 + // Bit mask of OUTFIFO_UDF field. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_Msk = 0x20 + // Bit OUTFIFO_UDF. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF = 0x20 + + // AHB_TEST: reserved + // Position of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // MISC_CONF: MISC register + // Position of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Pos = 0x0 + // Bit mask of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Msk = 0x1 + // Bit AHBM_RST_INTER. + DMA_MISC_CONF_AHBM_RST_INTER = 0x1 + // Position of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Pos = 0x2 + // Bit mask of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Msk = 0x4 + // Bit ARB_PRI_DIS. + DMA_MISC_CONF_ARB_PRI_DIS = 0x4 + // Position of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Pos = 0x3 + // Bit mask of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Msk = 0x8 + // Bit CLK_EN. + DMA_MISC_CONF_CLK_EN = 0x8 + + // DATE: Version control register + // Position of DATE field. + DMA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DMA_DATE_DATE_Msk = 0xffffffff + + // IN_CONF0_CH0: Configure 0 register of Rx channel 0 + // Position of IN_RST field. + DMA_IN_CONF0_CH_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + DMA_IN_CONF0_CH_IN_RST_Msk = 0x1 + // Bit IN_RST. + DMA_IN_CONF0_CH_IN_RST = 0x1 + // Position of IN_LOOP_TEST field. + DMA_IN_CONF0_CH_IN_LOOP_TEST_Pos = 0x1 + // Bit mask of IN_LOOP_TEST field. + DMA_IN_CONF0_CH_IN_LOOP_TEST_Msk = 0x2 + // Bit IN_LOOP_TEST. + DMA_IN_CONF0_CH_IN_LOOP_TEST = 0x2 + // Position of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH_INDSCR_BURST_EN_Pos = 0x2 + // Bit mask of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH_INDSCR_BURST_EN_Msk = 0x4 + // Bit INDSCR_BURST_EN. + DMA_IN_CONF0_CH_INDSCR_BURST_EN = 0x4 + // Position of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH_IN_DATA_BURST_EN_Pos = 0x3 + // Bit mask of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH_IN_DATA_BURST_EN_Msk = 0x8 + // Bit IN_DATA_BURST_EN. + DMA_IN_CONF0_CH_IN_DATA_BURST_EN = 0x8 + // Position of MEM_TRANS_EN field. + DMA_IN_CONF0_CH_MEM_TRANS_EN_Pos = 0x4 + // Bit mask of MEM_TRANS_EN field. + DMA_IN_CONF0_CH_MEM_TRANS_EN_Msk = 0x10 + // Bit MEM_TRANS_EN. + DMA_IN_CONF0_CH_MEM_TRANS_EN = 0x10 + // Position of IN_ETM_EN field. + DMA_IN_CONF0_CH_IN_ETM_EN_Pos = 0x5 + // Bit mask of IN_ETM_EN field. + DMA_IN_CONF0_CH_IN_ETM_EN_Msk = 0x20 + // Bit IN_ETM_EN. + DMA_IN_CONF0_CH_IN_ETM_EN = 0x20 + + // IN_CONF1_CH0: Configure 1 register of Rx channel 0 + // Position of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH_IN_CHECK_OWNER_Pos = 0xc + // Bit mask of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH_IN_CHECK_OWNER_Msk = 0x1000 + // Bit IN_CHECK_OWNER. + DMA_IN_CONF1_CH_IN_CHECK_OWNER = 0x1000 + + // INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0 + // Position of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_Pos = 0x0 + // Bit mask of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_Msk = 0x1 + // Bit INFIFO_FULL. + DMA_INFIFO_STATUS_CH_INFIFO_FULL = 0x1 + // Position of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_Pos = 0x1 + // Bit mask of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_Msk = 0x2 + // Bit INFIFO_EMPTY. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY = 0x2 + // Position of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_Pos = 0x2 + // Bit mask of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_Msk = 0xfc + // Position of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit IN_REMAIN_UNDER_1B. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B = 0x800000 + // Position of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit IN_REMAIN_UNDER_2B. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B = 0x1000000 + // Position of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit IN_REMAIN_UNDER_3B. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B = 0x2000000 + // Position of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit IN_REMAIN_UNDER_4B. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B = 0x4000000 + // Position of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_Pos = 0x1b + // Bit mask of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_Msk = 0x8000000 + // Bit IN_BUF_HUNGRY. + DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY = 0x8000000 + + // IN_POP_CH0: Pop control register of Rx channel 0 + // Position of INFIFO_RDATA field. + DMA_IN_POP_CH_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + DMA_IN_POP_CH_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + DMA_IN_POP_CH_INFIFO_POP_Pos = 0xc + // Bit mask of INFIFO_POP field. + DMA_IN_POP_CH_INFIFO_POP_Msk = 0x1000 + // Bit INFIFO_POP. + DMA_IN_POP_CH_INFIFO_POP = 0x1000 + + // IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0 + // Position of INLINK_ADDR field. + DMA_IN_LINK_CH_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + DMA_IN_LINK_CH_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + DMA_IN_LINK_CH_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + DMA_IN_LINK_CH_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + DMA_IN_LINK_CH_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + DMA_IN_LINK_CH_INLINK_STOP_Pos = 0x15 + // Bit mask of INLINK_STOP field. + DMA_IN_LINK_CH_INLINK_STOP_Msk = 0x200000 + // Bit INLINK_STOP. + DMA_IN_LINK_CH_INLINK_STOP = 0x200000 + // Position of INLINK_START field. + DMA_IN_LINK_CH_INLINK_START_Pos = 0x16 + // Bit mask of INLINK_START field. + DMA_IN_LINK_CH_INLINK_START_Msk = 0x400000 + // Bit INLINK_START. + DMA_IN_LINK_CH_INLINK_START = 0x400000 + // Position of INLINK_RESTART field. + DMA_IN_LINK_CH_INLINK_RESTART_Pos = 0x17 + // Bit mask of INLINK_RESTART field. + DMA_IN_LINK_CH_INLINK_RESTART_Msk = 0x800000 + // Bit INLINK_RESTART. + DMA_IN_LINK_CH_INLINK_RESTART = 0x800000 + // Position of INLINK_PARK field. + DMA_IN_LINK_CH_INLINK_PARK_Pos = 0x18 + // Bit mask of INLINK_PARK field. + DMA_IN_LINK_CH_INLINK_PARK_Msk = 0x1000000 + // Bit INLINK_PARK. + DMA_IN_LINK_CH_INLINK_PARK = 0x1000000 + + // IN_STATE_CH0: Receive status of Rx channel 0 + // Position of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH_INLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH_INLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of IN_DSCR_STATE field. + DMA_IN_STATE_CH_IN_DSCR_STATE_Pos = 0x12 + // Bit mask of IN_DSCR_STATE field. + DMA_IN_STATE_CH_IN_DSCR_STATE_Msk = 0xc0000 + // Position of IN_STATE field. + DMA_IN_STATE_CH_IN_STATE_Pos = 0x14 + // Bit mask of IN_STATE field. + DMA_IN_STATE_CH_IN_STATE_Msk = 0x700000 + + // IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0 + // Position of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0 + // Position of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR field. + DMA_IN_DSCR_CH_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + DMA_IN_DSCR_CH_INLINK_DSCR_Msk = 0xffffffff + + // IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_Msk = 0xffffffff + + // IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_Msk = 0xffffffff + + // IN_PRI_CH0: Priority register of Rx channel 0 + // Position of RX_PRI field. + DMA_IN_PRI_CH_RX_PRI_Pos = 0x0 + // Bit mask of RX_PRI field. + DMA_IN_PRI_CH_RX_PRI_Msk = 0xf + + // IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0 + // Position of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH_PERI_IN_SEL_Pos = 0x0 + // Bit mask of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH_PERI_IN_SEL_Msk = 0x3f + + // OUT_CONF1_CH0: Configure 1 register of Tx channel 0 + // Position of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_Pos = 0xc + // Bit mask of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_Msk = 0x1000 + // Bit OUT_CHECK_OWNER. + DMA_OUT_CONF1_CH_OUT_CHECK_OWNER = 0x1000 + + // OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0 + // Position of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_Pos = 0x0 + // Bit mask of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_Msk = 0x1 + // Bit OUTFIFO_FULL. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL = 0x1 + // Position of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_Pos = 0x1 + // Bit mask of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_Msk = 0x2 + // Bit OUTFIFO_EMPTY. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY = 0x2 + // Position of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_Pos = 0x2 + // Bit mask of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_Msk = 0xfc + // Position of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit OUT_REMAIN_UNDER_1B. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B = 0x800000 + // Position of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit OUT_REMAIN_UNDER_2B. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B = 0x1000000 + // Position of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit OUT_REMAIN_UNDER_3B. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B = 0x2000000 + // Position of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit OUT_REMAIN_UNDER_4B. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B = 0x4000000 + + // OUT_PUSH_CH0: Push control register of Rx channel 0 + // Position of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH_OUTFIFO_PUSH_Pos = 0x9 + // Bit mask of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH_OUTFIFO_PUSH_Msk = 0x200 + // Bit OUTFIFO_PUSH. + DMA_OUT_PUSH_CH_OUTFIFO_PUSH = 0x200 + + // OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0 + // Position of OUTLINK_ADDR field. + DMA_OUT_LINK_CH_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + DMA_OUT_LINK_CH_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + DMA_OUT_LINK_CH_OUTLINK_STOP_Pos = 0x14 + // Bit mask of OUTLINK_STOP field. + DMA_OUT_LINK_CH_OUTLINK_STOP_Msk = 0x100000 + // Bit OUTLINK_STOP. + DMA_OUT_LINK_CH_OUTLINK_STOP = 0x100000 + // Position of OUTLINK_START field. + DMA_OUT_LINK_CH_OUTLINK_START_Pos = 0x15 + // Bit mask of OUTLINK_START field. + DMA_OUT_LINK_CH_OUTLINK_START_Msk = 0x200000 + // Bit OUTLINK_START. + DMA_OUT_LINK_CH_OUTLINK_START = 0x200000 + // Position of OUTLINK_RESTART field. + DMA_OUT_LINK_CH_OUTLINK_RESTART_Pos = 0x16 + // Bit mask of OUTLINK_RESTART field. + DMA_OUT_LINK_CH_OUTLINK_RESTART_Msk = 0x400000 + // Bit OUTLINK_RESTART. + DMA_OUT_LINK_CH_OUTLINK_RESTART = 0x400000 + // Position of OUTLINK_PARK field. + DMA_OUT_LINK_CH_OUTLINK_PARK_Pos = 0x17 + // Bit mask of OUTLINK_PARK field. + DMA_OUT_LINK_CH_OUTLINK_PARK_Msk = 0x800000 + // Bit OUTLINK_PARK. + DMA_OUT_LINK_CH_OUTLINK_PARK = 0x800000 + + // OUT_STATE_CH0: Transmit status of Tx channel 0 + // Position of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH_OUT_DSCR_STATE_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH_OUT_DSCR_STATE_Msk = 0xc0000 + // Position of OUT_STATE field. + DMA_OUT_STATE_CH_OUT_STATE_Pos = 0x14 + // Bit mask of OUT_STATE field. + DMA_OUT_STATE_CH_OUT_STATE_Msk = 0x700000 + + // OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0 + // Position of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0 + // Position of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH_OUTLINK_DSCR_Msk = 0xffffffff + + // OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // OUT_PRI_CH0: Priority register of Tx channel 0. + // Position of TX_PRI field. + DMA_OUT_PRI_CH_TX_PRI_Pos = 0x0 + // Bit mask of TX_PRI field. + DMA_OUT_PRI_CH_TX_PRI_Msk = 0xf + + // OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0 + // Position of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_Pos = 0x0 + // Bit mask of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_Msk = 0x3f + + // OUT_CONF0_CH0: Configure 0 register of Tx channel 1 + // Position of OUT_RST field. + DMA_OUT_CONF0_CH_OUT_RST_Pos = 0x0 + // Bit mask of OUT_RST field. + DMA_OUT_CONF0_CH_OUT_RST_Msk = 0x1 + // Bit OUT_RST. + DMA_OUT_CONF0_CH_OUT_RST = 0x1 + // Position of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH_OUT_LOOP_TEST_Pos = 0x1 + // Bit mask of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH_OUT_LOOP_TEST_Msk = 0x2 + // Bit OUT_LOOP_TEST. + DMA_OUT_CONF0_CH_OUT_LOOP_TEST = 0x2 + // Position of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_Pos = 0x2 + // Bit mask of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_Msk = 0x4 + // Bit OUT_AUTO_WRBACK. + DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK = 0x4 + // Position of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH_OUT_EOF_MODE_Pos = 0x3 + // Bit mask of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH_OUT_EOF_MODE_Msk = 0x8 + // Bit OUT_EOF_MODE. + DMA_OUT_CONF0_CH_OUT_EOF_MODE = 0x8 + // Position of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_Pos = 0x4 + // Bit mask of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_Msk = 0x10 + // Bit OUTDSCR_BURST_EN. + DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN = 0x10 + // Position of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_Pos = 0x5 + // Bit mask of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_Msk = 0x20 + // Bit OUT_DATA_BURST_EN. + DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN = 0x20 + // Position of OUT_ETM_EN field. + DMA_OUT_CONF0_CH_OUT_ETM_EN_Pos = 0x6 + // Bit mask of OUT_ETM_EN field. + DMA_OUT_CONF0_CH_OUT_ETM_EN_Msk = 0x40 + // Bit OUT_ETM_EN. + DMA_OUT_CONF0_CH_OUT_ETM_EN = 0x40 +) + +// Constants for DS: Digital Signature +const ( + // SET_START: DS start control register + // Position of SET_START field. + DS_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + DS_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + DS_SET_START_SET_START = 0x1 + + // SET_CONTINUE: DS continue control register + // Position of SET_CONTINUE field. + DS_SET_CONTINUE_SET_CONTINUE_Pos = 0x0 + // Bit mask of SET_CONTINUE field. + DS_SET_CONTINUE_SET_CONTINUE_Msk = 0x1 + // Bit SET_CONTINUE. + DS_SET_CONTINUE_SET_CONTINUE = 0x1 + + // SET_FINISH: DS finish control register + // Position of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Pos = 0x0 + // Bit mask of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Msk = 0x1 + // Bit SET_FINISH. + DS_SET_FINISH_SET_FINISH = 0x1 + + // QUERY_BUSY: DS query busy register + // Position of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Pos = 0x0 + // Bit mask of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Msk = 0x1 + // Bit QUERY_BUSY. + DS_QUERY_BUSY_QUERY_BUSY = 0x1 + + // QUERY_KEY_WRONG: DS query key-wrong counter register + // Position of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Pos = 0x0 + // Bit mask of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Msk = 0xf + + // QUERY_CHECK: DS query check result register + // Position of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Pos = 0x0 + // Bit mask of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Msk = 0x1 + // Bit MD_ERROR. + DS_QUERY_CHECK_MD_ERROR = 0x1 + // Position of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Pos = 0x1 + // Bit mask of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Msk = 0x2 + // Bit PADDING_BAD. + DS_QUERY_CHECK_PADDING_BAD = 0x2 + + // DATE: DS version control register + // Position of DATE field. + DS_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DS_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for ECC: ECC (ECC Hardware Accelerator) +const ( + // MULT_INT_RAW: ECC interrupt raw register, valid in level. + // Position of CALC_DONE_INT_RAW field. + ECC_MULT_INT_RAW_CALC_DONE_INT_RAW_Pos = 0x0 + // Bit mask of CALC_DONE_INT_RAW field. + ECC_MULT_INT_RAW_CALC_DONE_INT_RAW_Msk = 0x1 + // Bit CALC_DONE_INT_RAW. + ECC_MULT_INT_RAW_CALC_DONE_INT_RAW = 0x1 + + // MULT_INT_ST: ECC interrupt status register. + // Position of CALC_DONE_INT_ST field. + ECC_MULT_INT_ST_CALC_DONE_INT_ST_Pos = 0x0 + // Bit mask of CALC_DONE_INT_ST field. + ECC_MULT_INT_ST_CALC_DONE_INT_ST_Msk = 0x1 + // Bit CALC_DONE_INT_ST. + ECC_MULT_INT_ST_CALC_DONE_INT_ST = 0x1 + + // MULT_INT_ENA: ECC interrupt enable register. + // Position of CALC_DONE_INT_ENA field. + ECC_MULT_INT_ENA_CALC_DONE_INT_ENA_Pos = 0x0 + // Bit mask of CALC_DONE_INT_ENA field. + ECC_MULT_INT_ENA_CALC_DONE_INT_ENA_Msk = 0x1 + // Bit CALC_DONE_INT_ENA. + ECC_MULT_INT_ENA_CALC_DONE_INT_ENA = 0x1 + + // MULT_INT_CLR: ECC interrupt clear register. + // Position of CALC_DONE_INT_CLR field. + ECC_MULT_INT_CLR_CALC_DONE_INT_CLR_Pos = 0x0 + // Bit mask of CALC_DONE_INT_CLR field. + ECC_MULT_INT_CLR_CALC_DONE_INT_CLR_Msk = 0x1 + // Bit CALC_DONE_INT_CLR. + ECC_MULT_INT_CLR_CALC_DONE_INT_CLR = 0x1 + + // MULT_CONF: ECC configure register + // Position of START field. + ECC_MULT_CONF_START_Pos = 0x0 + // Bit mask of START field. + ECC_MULT_CONF_START_Msk = 0x1 + // Bit START. + ECC_MULT_CONF_START = 0x1 + // Position of RESET field. + ECC_MULT_CONF_RESET_Pos = 0x1 + // Bit mask of RESET field. + ECC_MULT_CONF_RESET_Msk = 0x2 + // Bit RESET. + ECC_MULT_CONF_RESET = 0x2 + // Position of KEY_LENGTH field. + ECC_MULT_CONF_KEY_LENGTH_Pos = 0x2 + // Bit mask of KEY_LENGTH field. + ECC_MULT_CONF_KEY_LENGTH_Msk = 0x4 + // Bit KEY_LENGTH. + ECC_MULT_CONF_KEY_LENGTH = 0x4 + // Position of SECURITY_MODE field. + ECC_MULT_CONF_SECURITY_MODE_Pos = 0x3 + // Bit mask of SECURITY_MODE field. + ECC_MULT_CONF_SECURITY_MODE_Msk = 0x8 + // Bit SECURITY_MODE. + ECC_MULT_CONF_SECURITY_MODE = 0x8 + // Position of CLK_EN field. + ECC_MULT_CONF_CLK_EN_Pos = 0x4 + // Bit mask of CLK_EN field. + ECC_MULT_CONF_CLK_EN_Msk = 0x10 + // Bit CLK_EN. + ECC_MULT_CONF_CLK_EN = 0x10 + // Position of WORK_MODE field. + ECC_MULT_CONF_WORK_MODE_Pos = 0x5 + // Bit mask of WORK_MODE field. + ECC_MULT_CONF_WORK_MODE_Msk = 0xe0 + // Position of VERIFICATION_RESULT field. + ECC_MULT_CONF_VERIFICATION_RESULT_Pos = 0x8 + // Bit mask of VERIFICATION_RESULT field. + ECC_MULT_CONF_VERIFICATION_RESULT_Msk = 0x100 + // Bit VERIFICATION_RESULT. + ECC_MULT_CONF_VERIFICATION_RESULT = 0x100 + // Position of MEM_CLOCK_GATE_FORCE_ON field. + ECC_MULT_CONF_MEM_CLOCK_GATE_FORCE_ON_Pos = 0x1f + // Bit mask of MEM_CLOCK_GATE_FORCE_ON field. + ECC_MULT_CONF_MEM_CLOCK_GATE_FORCE_ON_Msk = 0x80000000 + // Bit MEM_CLOCK_GATE_FORCE_ON. + ECC_MULT_CONF_MEM_CLOCK_GATE_FORCE_ON = 0x80000000 + + // MULT_DATE: Version control register + // Position of DATE field. + ECC_MULT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + ECC_MULT_DATE_DATE_Msk = 0xfffffff +) + +// Constants for EFUSE: eFuse Controller +const ( + // PGM_DATA0: Register 0 that stores data to be programmed. + // Position of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Pos = 0x0 + // Bit mask of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Msk = 0xffffffff + + // PGM_DATA1: Register 1 that stores data to be programmed. + // Position of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Pos = 0x0 + // Bit mask of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Msk = 0xffffffff + + // PGM_DATA2: Register 2 that stores data to be programmed. + // Position of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Pos = 0x0 + // Bit mask of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Msk = 0xffffffff + + // PGM_DATA3: Register 3 that stores data to be programmed. + // Position of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Pos = 0x0 + // Bit mask of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Msk = 0xffffffff + + // PGM_DATA4: Register 4 that stores data to be programmed. + // Position of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Pos = 0x0 + // Bit mask of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Msk = 0xffffffff + + // PGM_DATA5: Register 5 that stores data to be programmed. + // Position of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Pos = 0x0 + // Bit mask of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Msk = 0xffffffff + + // PGM_DATA6: Register 6 that stores data to be programmed. + // Position of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Pos = 0x0 + // Bit mask of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Msk = 0xffffffff + + // PGM_DATA7: Register 7 that stores data to be programmed. + // Position of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Pos = 0x0 + // Bit mask of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Msk = 0xffffffff + + // PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Pos = 0x0 + // Bit mask of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Msk = 0xffffffff + + // PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Pos = 0x0 + // Bit mask of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Msk = 0xffffffff + + // PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Pos = 0x0 + // Bit mask of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Msk = 0xffffffff + + // RD_WR_DIS: BLOCK0 data register 0. + // Position of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Pos = 0x0 + // Bit mask of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Msk = 0xffffffff + + // RD_REPEAT_DATA0: BLOCK0 data register 1. + // Position of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Pos = 0x0 + // Bit mask of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Msk = 0x7f + // Position of SWAP_UART_SDIO_EN field. + EFUSE_RD_REPEAT_DATA0_SWAP_UART_SDIO_EN_Pos = 0x7 + // Bit mask of SWAP_UART_SDIO_EN field. + EFUSE_RD_REPEAT_DATA0_SWAP_UART_SDIO_EN_Msk = 0x80 + // Bit SWAP_UART_SDIO_EN. + EFUSE_RD_REPEAT_DATA0_SWAP_UART_SDIO_EN = 0x80 + // Position of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Pos = 0x8 + // Bit mask of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Msk = 0x100 + // Bit DIS_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE = 0x100 + // Position of DIS_USB_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG_Pos = 0x9 + // Bit mask of DIS_USB_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG_Msk = 0x200 + // Bit DIS_USB_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG = 0x200 + // Position of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Pos = 0xa + // Bit mask of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Msk = 0x400 + // Bit DIS_DOWNLOAD_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE = 0x400 + // Position of DIS_USB_SERIAL_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG_Pos = 0xb + // Bit mask of DIS_USB_SERIAL_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG_Msk = 0x800 + // Bit DIS_USB_SERIAL_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG = 0x800 + // Position of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD = 0x1000 + // Position of SPI_DOWNLOAD_MSPI_DIS field. + EFUSE_RD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS_Pos = 0xd + // Bit mask of SPI_DOWNLOAD_MSPI_DIS field. + EFUSE_RD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS_Msk = 0x2000 + // Bit SPI_DOWNLOAD_MSPI_DIS. + EFUSE_RD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS = 0x2000 + // Position of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Pos = 0xe + // Bit mask of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Msk = 0x4000 + // Bit DIS_CAN. + EFUSE_RD_REPEAT_DATA0_DIS_CAN = 0x4000 + // Position of JTAG_SEL_ENABLE field. + EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE_Pos = 0xf + // Bit mask of JTAG_SEL_ENABLE field. + EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE_Msk = 0x8000 + // Bit JTAG_SEL_ENABLE. + EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE = 0x8000 + // Position of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Pos = 0x10 + // Bit mask of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Msk = 0x70000 + // Position of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Pos = 0x13 + // Bit mask of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Msk = 0x80000 + // Bit DIS_PAD_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG = 0x80000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x14 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x100000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT = 0x100000 + // Position of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Pos = 0x15 + // Bit mask of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Msk = 0x600000 + // Position of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Pos = 0x17 + // Bit mask of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Msk = 0x1800000 + // Position of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Pos = 0x19 + // Bit mask of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Msk = 0x2000000 + // Bit USB_EXCHG_PINS. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS = 0x2000000 + // Position of VDD_SPI_AS_GPIO field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_AS_GPIO_Pos = 0x1a + // Bit mask of VDD_SPI_AS_GPIO field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_AS_GPIO_Msk = 0x4000000 + // Bit VDD_SPI_AS_GPIO. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_AS_GPIO = 0x4000000 + // Position of RPT4_RESERVED0_2 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_2_Pos = 0x1b + // Bit mask of RPT4_RESERVED0_2 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_2_Msk = 0x18000000 + // Position of RPT4_RESERVED0_1 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_1_Pos = 0x1d + // Bit mask of RPT4_RESERVED0_1 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_1_Msk = 0x20000000 + // Bit RPT4_RESERVED0_1. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_1 = 0x20000000 + // Position of RPT4_RESERVED0_0 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_0_Pos = 0x1e + // Bit mask of RPT4_RESERVED0_0 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_0_Msk = 0xc0000000 + + // RD_REPEAT_DATA1: BLOCK0 data register 2. + // Position of RPT4_RESERVED1_0 field. + EFUSE_RD_REPEAT_DATA1_RPT4_RESERVED1_0_Pos = 0x0 + // Bit mask of RPT4_RESERVED1_0 field. + EFUSE_RD_REPEAT_DATA1_RPT4_RESERVED1_0_Msk = 0xffff + // Position of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0 = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1 = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2 = 0x800000 + // Position of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Msk = 0xf000000 + // Position of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Msk = 0xf0000000 + + // RD_REPEAT_DATA2: BLOCK0 data register 3. + // Position of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Msk = 0xf + // Position of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Msk = 0xf0 + // Position of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Msk = 0xf00 + // Position of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Pos = 0xc + // Bit mask of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Msk = 0xf000 + // Position of DPA_SEC_LEVEL field. + EFUSE_RD_REPEAT_DATA2_DPA_SEC_LEVEL_Pos = 0x10 + // Bit mask of DPA_SEC_LEVEL field. + EFUSE_RD_REPEAT_DATA2_DPA_SEC_LEVEL_Msk = 0x30000 + // Position of RPT4_RESERVED2_1 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED2_1_Pos = 0x12 + // Bit mask of RPT4_RESERVED2_1 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED2_1_Msk = 0x40000 + // Bit RPT4_RESERVED2_1. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED2_1 = 0x40000 + // Position of CRYPT_DPA_ENABLE field. + EFUSE_RD_REPEAT_DATA2_CRYPT_DPA_ENABLE_Pos = 0x13 + // Bit mask of CRYPT_DPA_ENABLE field. + EFUSE_RD_REPEAT_DATA2_CRYPT_DPA_ENABLE_Msk = 0x80000 + // Bit CRYPT_DPA_ENABLE. + EFUSE_RD_REPEAT_DATA2_CRYPT_DPA_ENABLE = 0x80000 + // Position of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Msk = 0x100000 + // Bit SECURE_BOOT_EN. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE = 0x200000 + // Position of RPT4_RESERVED2_0 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED2_0_Pos = 0x16 + // Bit mask of RPT4_RESERVED2_0 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED2_0_Msk = 0xfc00000 + // Position of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Pos = 0x1c + // Bit mask of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Msk = 0xf0000000 + + // RD_REPEAT_DATA3: BLOCK0 data register 4. + // Position of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE = 0x1 + // Position of DIS_DIRECT_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_DIRECT_BOOT_Pos = 0x1 + // Bit mask of DIS_DIRECT_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_DIRECT_BOOT_Msk = 0x2 + // Bit DIS_DIRECT_BOOT. + EFUSE_RD_REPEAT_DATA3_DIS_DIRECT_BOOT = 0x2 + // Position of DIS_USB_PRINT field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_PRINT_Pos = 0x2 + // Bit mask of DIS_USB_PRINT field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_PRINT_Msk = 0x4 + // Bit DIS_USB_PRINT. + EFUSE_RD_REPEAT_DATA3_DIS_USB_PRINT = 0x4 + // Position of RPT4_RESERVED3_5 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_5_Pos = 0x3 + // Bit mask of RPT4_RESERVED3_5 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_5_Msk = 0x8 + // Bit RPT4_RESERVED3_5. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_5 = 0x8 + // Position of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_Pos = 0x4 + // Bit mask of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_Msk = 0x10 + // Bit DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD = 0x20 + // Position of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Msk = 0xc0 + // Position of RPT4_RESERVED3_4 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_4_Pos = 0x8 + // Bit mask of RPT4_RESERVED3_4 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_4_Msk = 0x100 + // Bit RPT4_RESERVED3_4. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_4 = 0x100 + // Position of RPT4_RESERVED3_3 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_3_Pos = 0x9 + // Bit mask of RPT4_RESERVED3_3 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_3_Msk = 0x200 + // Bit RPT4_RESERVED3_3. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_3 = 0x200 + // Position of RPT4_RESERVED3_2 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_2_Pos = 0xa + // Bit mask of RPT4_RESERVED3_2 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_2_Msk = 0xc00 + // Position of RPT4_RESERVED3_1 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_1_Pos = 0xc + // Bit mask of RPT4_RESERVED3_1 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_1_Msk = 0x1000 + // Bit RPT4_RESERVED3_1. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_1 = 0x1000 + // Position of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Pos = 0xd + // Bit mask of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Msk = 0x2000 + // Bit FORCE_SEND_RESUME. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME = 0x2000 + // Position of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Pos = 0xe + // Bit mask of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Msk = 0x3fffc000 + // Position of SECURE_BOOT_DISABLE_FAST_WAKE field. + EFUSE_RD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE_Pos = 0x1e + // Bit mask of SECURE_BOOT_DISABLE_FAST_WAKE field. + EFUSE_RD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE_Msk = 0x40000000 + // Bit SECURE_BOOT_DISABLE_FAST_WAKE. + EFUSE_RD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE = 0x40000000 + // Position of RPT4_RESERVED3_0 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_0_Pos = 0x1f + // Bit mask of RPT4_RESERVED3_0 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_0_Msk = 0x80000000 + // Bit RPT4_RESERVED3_0. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_0 = 0x80000000 + + // RD_REPEAT_DATA4: BLOCK0 data register 5. + // Position of RPT4_RESERVED4_1 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_1_Pos = 0x0 + // Bit mask of RPT4_RESERVED4_1 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_1_Msk = 0xffffff + // Position of RPT4_RESERVED4_0 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_0_Pos = 0x18 + // Bit mask of RPT4_RESERVED4_0 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_0_Msk = 0xff000000 + + // RD_MAC_SPI_SYS_0: BLOCK1 data register $n. + // Position of MAC_0 field. + EFUSE_RD_MAC_SPI_SYS_0_MAC_0_Pos = 0x0 + // Bit mask of MAC_0 field. + EFUSE_RD_MAC_SPI_SYS_0_MAC_0_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_1: BLOCK1 data register $n. + // Position of MAC_1 field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_1_Pos = 0x0 + // Bit mask of MAC_1 field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_1_Msk = 0xffff + // Position of MAC_EXT field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_EXT_Pos = 0x10 + // Bit mask of MAC_EXT field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_EXT_Msk = 0xffff0000 + + // RD_MAC_SPI_SYS_2: BLOCK1 data register $n. + // Position of MAC_SPI_RESERVED field. + EFUSE_RD_MAC_SPI_SYS_2_MAC_SPI_RESERVED_Pos = 0x0 + // Bit mask of MAC_SPI_RESERVED field. + EFUSE_RD_MAC_SPI_SYS_2_MAC_SPI_RESERVED_Msk = 0x3fff + // Position of SPI_PAD_CONF_1 field. + EFUSE_RD_MAC_SPI_SYS_2_SPI_PAD_CONF_1_Pos = 0xe + // Bit mask of SPI_PAD_CONF_1 field. + EFUSE_RD_MAC_SPI_SYS_2_SPI_PAD_CONF_1_Msk = 0xffffc000 + + // RD_MAC_SPI_SYS_3: BLOCK1 data register $n. + // Position of SPI_PAD_CONF_2 field. + EFUSE_RD_MAC_SPI_SYS_3_SPI_PAD_CONF_2_Pos = 0x0 + // Bit mask of SPI_PAD_CONF_2 field. + EFUSE_RD_MAC_SPI_SYS_3_SPI_PAD_CONF_2_Msk = 0x3ffff + // Position of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SPI_SYS_3_SYS_DATA_PART0_0_Pos = 0x12 + // Bit mask of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SPI_SYS_3_SYS_DATA_PART0_0_Msk = 0xfffc0000 + + // RD_MAC_SPI_SYS_4: BLOCK1 data register $n. + // Position of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SPI_SYS_4_SYS_DATA_PART0_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SPI_SYS_4_SYS_DATA_PART0_1_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_5: BLOCK1 data register $n. + // Position of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SPI_SYS_5_SYS_DATA_PART0_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SPI_SYS_5_SYS_DATA_PART0_2_Msk = 0xffffffff + + // RD_SYS_PART1_DATA0: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_0 field. + EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_0 field. + EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Msk = 0xffffffff + + // RD_SYS_PART1_DATA1: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_1 field. + EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_1 field. + EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Msk = 0xffffffff + + // RD_SYS_PART1_DATA2: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_2 field. + EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_2 field. + EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Msk = 0xffffffff + + // RD_SYS_PART1_DATA3: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_3 field. + EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_3 field. + EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Msk = 0xffffffff + + // RD_SYS_PART1_DATA4: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_4 field. + EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_4 field. + EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Msk = 0xffffffff + + // RD_SYS_PART1_DATA5: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_5 field. + EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_5 field. + EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Msk = 0xffffffff + + // RD_SYS_PART1_DATA6: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_6 field. + EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_6 field. + EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Msk = 0xffffffff + + // RD_SYS_PART1_DATA7: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_7 field. + EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_7 field. + EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Msk = 0xffffffff + + // RD_USR_DATA0: Register $n of BLOCK3 (user). + // Position of USR_DATA0 field. + EFUSE_RD_USR_DATA0_USR_DATA0_Pos = 0x0 + // Bit mask of USR_DATA0 field. + EFUSE_RD_USR_DATA0_USR_DATA0_Msk = 0xffffffff + + // RD_USR_DATA1: Register $n of BLOCK3 (user). + // Position of USR_DATA1 field. + EFUSE_RD_USR_DATA1_USR_DATA1_Pos = 0x0 + // Bit mask of USR_DATA1 field. + EFUSE_RD_USR_DATA1_USR_DATA1_Msk = 0xffffffff + + // RD_USR_DATA2: Register $n of BLOCK3 (user). + // Position of USR_DATA2 field. + EFUSE_RD_USR_DATA2_USR_DATA2_Pos = 0x0 + // Bit mask of USR_DATA2 field. + EFUSE_RD_USR_DATA2_USR_DATA2_Msk = 0xffffffff + + // RD_USR_DATA3: Register $n of BLOCK3 (user). + // Position of USR_DATA3 field. + EFUSE_RD_USR_DATA3_USR_DATA3_Pos = 0x0 + // Bit mask of USR_DATA3 field. + EFUSE_RD_USR_DATA3_USR_DATA3_Msk = 0xffffffff + + // RD_USR_DATA4: Register $n of BLOCK3 (user). + // Position of USR_DATA4 field. + EFUSE_RD_USR_DATA4_USR_DATA4_Pos = 0x0 + // Bit mask of USR_DATA4 field. + EFUSE_RD_USR_DATA4_USR_DATA4_Msk = 0xffffffff + + // RD_USR_DATA5: Register $n of BLOCK3 (user). + // Position of USR_DATA5 field. + EFUSE_RD_USR_DATA5_USR_DATA5_Pos = 0x0 + // Bit mask of USR_DATA5 field. + EFUSE_RD_USR_DATA5_USR_DATA5_Msk = 0xffffffff + + // RD_USR_DATA6: Register $n of BLOCK3 (user). + // Position of USR_DATA6 field. + EFUSE_RD_USR_DATA6_USR_DATA6_Pos = 0x0 + // Bit mask of USR_DATA6 field. + EFUSE_RD_USR_DATA6_USR_DATA6_Msk = 0xffffffff + + // RD_USR_DATA7: Register $n of BLOCK3 (user). + // Position of USR_DATA7 field. + EFUSE_RD_USR_DATA7_USR_DATA7_Pos = 0x0 + // Bit mask of USR_DATA7 field. + EFUSE_RD_USR_DATA7_USR_DATA7_Msk = 0xffffffff + + // RD_KEY0_DATA0: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA0 field. + EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Pos = 0x0 + // Bit mask of KEY0_DATA0 field. + EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Msk = 0xffffffff + + // RD_KEY0_DATA1: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA1 field. + EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Pos = 0x0 + // Bit mask of KEY0_DATA1 field. + EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Msk = 0xffffffff + + // RD_KEY0_DATA2: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA2 field. + EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Pos = 0x0 + // Bit mask of KEY0_DATA2 field. + EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Msk = 0xffffffff + + // RD_KEY0_DATA3: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA3 field. + EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Pos = 0x0 + // Bit mask of KEY0_DATA3 field. + EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Msk = 0xffffffff + + // RD_KEY0_DATA4: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA4 field. + EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Pos = 0x0 + // Bit mask of KEY0_DATA4 field. + EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Msk = 0xffffffff + + // RD_KEY0_DATA5: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA5 field. + EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Pos = 0x0 + // Bit mask of KEY0_DATA5 field. + EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Msk = 0xffffffff + + // RD_KEY0_DATA6: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA6 field. + EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Pos = 0x0 + // Bit mask of KEY0_DATA6 field. + EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Msk = 0xffffffff + + // RD_KEY0_DATA7: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA7 field. + EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Pos = 0x0 + // Bit mask of KEY0_DATA7 field. + EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Msk = 0xffffffff + + // RD_KEY1_DATA0: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA0 field. + EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Pos = 0x0 + // Bit mask of KEY1_DATA0 field. + EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Msk = 0xffffffff + + // RD_KEY1_DATA1: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA1 field. + EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Pos = 0x0 + // Bit mask of KEY1_DATA1 field. + EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Msk = 0xffffffff + + // RD_KEY1_DATA2: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA2 field. + EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Pos = 0x0 + // Bit mask of KEY1_DATA2 field. + EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Msk = 0xffffffff + + // RD_KEY1_DATA3: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA3 field. + EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Pos = 0x0 + // Bit mask of KEY1_DATA3 field. + EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Msk = 0xffffffff + + // RD_KEY1_DATA4: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA4 field. + EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Pos = 0x0 + // Bit mask of KEY1_DATA4 field. + EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Msk = 0xffffffff + + // RD_KEY1_DATA5: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA5 field. + EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Pos = 0x0 + // Bit mask of KEY1_DATA5 field. + EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Msk = 0xffffffff + + // RD_KEY1_DATA6: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA6 field. + EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Pos = 0x0 + // Bit mask of KEY1_DATA6 field. + EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Msk = 0xffffffff + + // RD_KEY1_DATA7: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA7 field. + EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Pos = 0x0 + // Bit mask of KEY1_DATA7 field. + EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Msk = 0xffffffff + + // RD_KEY2_DATA0: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA0 field. + EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Pos = 0x0 + // Bit mask of KEY2_DATA0 field. + EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Msk = 0xffffffff + + // RD_KEY2_DATA1: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA1 field. + EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Pos = 0x0 + // Bit mask of KEY2_DATA1 field. + EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Msk = 0xffffffff + + // RD_KEY2_DATA2: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA2 field. + EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Pos = 0x0 + // Bit mask of KEY2_DATA2 field. + EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Msk = 0xffffffff + + // RD_KEY2_DATA3: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA3 field. + EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Pos = 0x0 + // Bit mask of KEY2_DATA3 field. + EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Msk = 0xffffffff + + // RD_KEY2_DATA4: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA4 field. + EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Pos = 0x0 + // Bit mask of KEY2_DATA4 field. + EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Msk = 0xffffffff + + // RD_KEY2_DATA5: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA5 field. + EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Pos = 0x0 + // Bit mask of KEY2_DATA5 field. + EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Msk = 0xffffffff + + // RD_KEY2_DATA6: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA6 field. + EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Pos = 0x0 + // Bit mask of KEY2_DATA6 field. + EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Msk = 0xffffffff + + // RD_KEY2_DATA7: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA7 field. + EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Pos = 0x0 + // Bit mask of KEY2_DATA7 field. + EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Msk = 0xffffffff + + // RD_KEY3_DATA0: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA0 field. + EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Pos = 0x0 + // Bit mask of KEY3_DATA0 field. + EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Msk = 0xffffffff + + // RD_KEY3_DATA1: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA1 field. + EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Pos = 0x0 + // Bit mask of KEY3_DATA1 field. + EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Msk = 0xffffffff + + // RD_KEY3_DATA2: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA2 field. + EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Pos = 0x0 + // Bit mask of KEY3_DATA2 field. + EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Msk = 0xffffffff + + // RD_KEY3_DATA3: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA3 field. + EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Pos = 0x0 + // Bit mask of KEY3_DATA3 field. + EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Msk = 0xffffffff + + // RD_KEY3_DATA4: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA4 field. + EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Pos = 0x0 + // Bit mask of KEY3_DATA4 field. + EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Msk = 0xffffffff + + // RD_KEY3_DATA5: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA5 field. + EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Pos = 0x0 + // Bit mask of KEY3_DATA5 field. + EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Msk = 0xffffffff + + // RD_KEY3_DATA6: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA6 field. + EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Pos = 0x0 + // Bit mask of KEY3_DATA6 field. + EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Msk = 0xffffffff + + // RD_KEY3_DATA7: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA7 field. + EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Pos = 0x0 + // Bit mask of KEY3_DATA7 field. + EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Msk = 0xffffffff + + // RD_KEY4_DATA0: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA0 field. + EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Pos = 0x0 + // Bit mask of KEY4_DATA0 field. + EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Msk = 0xffffffff + + // RD_KEY4_DATA1: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA1 field. + EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Pos = 0x0 + // Bit mask of KEY4_DATA1 field. + EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Msk = 0xffffffff + + // RD_KEY4_DATA2: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA2 field. + EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Pos = 0x0 + // Bit mask of KEY4_DATA2 field. + EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Msk = 0xffffffff + + // RD_KEY4_DATA3: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA3 field. + EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Pos = 0x0 + // Bit mask of KEY4_DATA3 field. + EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Msk = 0xffffffff + + // RD_KEY4_DATA4: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA4 field. + EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Pos = 0x0 + // Bit mask of KEY4_DATA4 field. + EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Msk = 0xffffffff + + // RD_KEY4_DATA5: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA5 field. + EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Pos = 0x0 + // Bit mask of KEY4_DATA5 field. + EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Msk = 0xffffffff + + // RD_KEY4_DATA6: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA6 field. + EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Pos = 0x0 + // Bit mask of KEY4_DATA6 field. + EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Msk = 0xffffffff + + // RD_KEY4_DATA7: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA7 field. + EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Pos = 0x0 + // Bit mask of KEY4_DATA7 field. + EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Msk = 0xffffffff + + // RD_KEY5_DATA0: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA0 field. + EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Pos = 0x0 + // Bit mask of KEY5_DATA0 field. + EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Msk = 0xffffffff + + // RD_KEY5_DATA1: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA1 field. + EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Pos = 0x0 + // Bit mask of KEY5_DATA1 field. + EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Msk = 0xffffffff + + // RD_KEY5_DATA2: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA2 field. + EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Pos = 0x0 + // Bit mask of KEY5_DATA2 field. + EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Msk = 0xffffffff + + // RD_KEY5_DATA3: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA3 field. + EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Pos = 0x0 + // Bit mask of KEY5_DATA3 field. + EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Msk = 0xffffffff + + // RD_KEY5_DATA4: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA4 field. + EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Pos = 0x0 + // Bit mask of KEY5_DATA4 field. + EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Msk = 0xffffffff + + // RD_KEY5_DATA5: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA5 field. + EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Pos = 0x0 + // Bit mask of KEY5_DATA5 field. + EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Msk = 0xffffffff + + // RD_KEY5_DATA6: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA6 field. + EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Pos = 0x0 + // Bit mask of KEY5_DATA6 field. + EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Msk = 0xffffffff + + // RD_KEY5_DATA7: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA7 field. + EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Pos = 0x0 + // Bit mask of KEY5_DATA7 field. + EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Msk = 0xffffffff + + // RD_SYS_PART2_DATA0: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_0 field. + EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_0 field. + EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Msk = 0xffffffff + + // RD_SYS_PART2_DATA1: Register $n of BLOCK9 (KEY5). + // Position of SYS_DATA_PART2_1 field. + EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_1 field. + EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Msk = 0xffffffff + + // RD_SYS_PART2_DATA2: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_2 field. + EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_2 field. + EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Msk = 0xffffffff + + // RD_SYS_PART2_DATA3: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_3 field. + EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_3 field. + EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Msk = 0xffffffff + + // RD_SYS_PART2_DATA4: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_4 field. + EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_4 field. + EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Msk = 0xffffffff + + // RD_SYS_PART2_DATA5: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_5 field. + EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_5 field. + EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Msk = 0xffffffff + + // RD_SYS_PART2_DATA6: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_6 field. + EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_6 field. + EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Msk = 0xffffffff + + // RD_SYS_PART2_DATA7: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_7 field. + EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_7 field. + EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Msk = 0xffffffff + + // RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. + // Position of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Pos = 0x0 + // Bit mask of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Msk = 0x7f + // Position of SWAP_UART_SDIO_EN_ERR field. + EFUSE_RD_REPEAT_ERR0_SWAP_UART_SDIO_EN_ERR_Pos = 0x7 + // Bit mask of SWAP_UART_SDIO_EN_ERR field. + EFUSE_RD_REPEAT_ERR0_SWAP_UART_SDIO_EN_ERR_Msk = 0x80 + // Bit SWAP_UART_SDIO_EN_ERR. + EFUSE_RD_REPEAT_ERR0_SWAP_UART_SDIO_EN_ERR = 0x80 + // Position of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Pos = 0x8 + // Bit mask of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Msk = 0x100 + // Bit DIS_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR = 0x100 + // Position of DIS_USB_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR_Pos = 0x9 + // Bit mask of DIS_USB_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR_Msk = 0x200 + // Bit DIS_USB_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR = 0x200 + // Position of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR_Pos = 0xa + // Bit mask of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR_Msk = 0x400 + // Bit DIS_DOWNLOAD_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR = 0x400 + // Position of DIS_USB_SERIAL_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR_Pos = 0xb + // Bit mask of DIS_USB_SERIAL_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR_Msk = 0x800 + // Bit DIS_USB_SERIAL_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR = 0x800 + // Position of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR = 0x1000 + // Position of SPI_DOWNLOAD_MSPI_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR_Pos = 0xd + // Bit mask of SPI_DOWNLOAD_MSPI_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR_Msk = 0x2000 + // Bit SPI_DOWNLOAD_MSPI_DIS_ERR. + EFUSE_RD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR = 0x2000 + // Position of DIS_TWAI_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_TWAI_ERR_Pos = 0xe + // Bit mask of DIS_TWAI_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_TWAI_ERR_Msk = 0x4000 + // Bit DIS_TWAI_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_TWAI_ERR = 0x4000 + // Position of JTAG_SEL_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR_Pos = 0xf + // Bit mask of JTAG_SEL_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR_Msk = 0x8000 + // Bit JTAG_SEL_ENABLE_ERR. + EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR = 0x8000 + // Position of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Pos = 0x10 + // Bit mask of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Msk = 0x70000 + // Position of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Pos = 0x13 + // Bit mask of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Msk = 0x80000 + // Bit DIS_PAD_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR = 0x80000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Pos = 0x14 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Msk = 0x100000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR = 0x100000 + // Position of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Pos = 0x15 + // Bit mask of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Msk = 0x600000 + // Position of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Pos = 0x17 + // Bit mask of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Msk = 0x1800000 + // Position of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Pos = 0x19 + // Bit mask of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Msk = 0x2000000 + // Bit USB_EXCHG_PINS_ERR. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR = 0x2000000 + // Position of VDD_SPI_AS_GPIO_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR_Pos = 0x1a + // Bit mask of VDD_SPI_AS_GPIO_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR_Msk = 0x4000000 + // Bit VDD_SPI_AS_GPIO_ERR. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR = 0x4000000 + // Position of RPT4_RESERVED0_ERR_2 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_2_Pos = 0x1b + // Bit mask of RPT4_RESERVED0_ERR_2 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_2_Msk = 0x18000000 + // Position of RPT4_RESERVED0_ERR_1 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1_Pos = 0x1d + // Bit mask of RPT4_RESERVED0_ERR_1 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1_Msk = 0x20000000 + // Bit RPT4_RESERVED0_ERR_1. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1 = 0x20000000 + // Position of RPT4_RESERVED0_ERR_0 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_0_Pos = 0x1e + // Bit mask of RPT4_RESERVED0_ERR_0 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_0_Msk = 0xc0000000 + + // RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. + // Position of RPT4_RESERVED1_ERR_0 field. + EFUSE_RD_REPEAT_ERR1_RPT4_RESERVED1_ERR_0_Pos = 0x0 + // Bit mask of RPT4_RESERVED1_ERR_0 field. + EFUSE_RD_REPEAT_ERR1_RPT4_RESERVED1_ERR_0_Msk = 0xffff + // Position of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR = 0x800000 + // Position of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Msk = 0xf000000 + // Position of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. + // Position of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Msk = 0xf + // Position of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Msk = 0xf0 + // Position of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Msk = 0xf00 + // Position of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Pos = 0xc + // Bit mask of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Msk = 0xf000 + // Position of SEC_DPA_LEVEL_ERR field. + EFUSE_RD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR_Pos = 0x10 + // Bit mask of SEC_DPA_LEVEL_ERR field. + EFUSE_RD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR_Msk = 0x30000 + // Position of RPT4_RESERVED2_ERR_1 field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1_Pos = 0x12 + // Bit mask of RPT4_RESERVED2_ERR_1 field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1_Msk = 0x40000 + // Bit RPT4_RESERVED2_ERR_1. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1 = 0x40000 + // Position of CRYPT_DPA_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR_Pos = 0x13 + // Bit mask of CRYPT_DPA_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR_Msk = 0x80000 + // Bit CRYPT_DPA_ENABLE_ERR. + EFUSE_RD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR = 0x80000 + // Position of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Msk = 0x100000 + // Bit SECURE_BOOT_EN_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR = 0x200000 + // Position of RPT4_RESERVED2_ERR_0 field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_0_Pos = 0x16 + // Bit mask of RPT4_RESERVED2_ERR_0 field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_0_Msk = 0xfc00000 + // Position of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Pos = 0x1c + // Bit mask of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. + // Position of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR = 0x1 + // Position of DIS_DIRECT_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR_Pos = 0x1 + // Bit mask of DIS_DIRECT_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR_Msk = 0x2 + // Bit DIS_DIRECT_BOOT_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR = 0x2 + // Position of USB_PRINT_ERR field. + EFUSE_RD_REPEAT_ERR3_USB_PRINT_ERR_Pos = 0x2 + // Bit mask of USB_PRINT_ERR field. + EFUSE_RD_REPEAT_ERR3_USB_PRINT_ERR_Msk = 0x4 + // Bit USB_PRINT_ERR. + EFUSE_RD_REPEAT_ERR3_USB_PRINT_ERR = 0x4 + // Position of RPT4_RESERVED3_ERR_5 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5_Pos = 0x3 + // Bit mask of RPT4_RESERVED3_ERR_5 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5_Msk = 0x8 + // Bit RPT4_RESERVED3_ERR_5. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5 = 0x8 + // Position of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_Pos = 0x4 + // Bit mask of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_Msk = 0x10 + // Bit DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR = 0x20 + // Position of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Msk = 0xc0 + // Position of RPT4_RESERVED3_ERR_4 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_4_Pos = 0x8 + // Bit mask of RPT4_RESERVED3_ERR_4 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_4_Msk = 0x100 + // Bit RPT4_RESERVED3_ERR_4. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_4 = 0x100 + // Position of RPT4_RESERVED3_ERR_3 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_3_Pos = 0x9 + // Bit mask of RPT4_RESERVED3_ERR_3 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_3_Msk = 0x200 + // Bit RPT4_RESERVED3_ERR_3. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_3 = 0x200 + // Position of RPT4_RESERVED3_ERR_2 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_2_Pos = 0xa + // Bit mask of RPT4_RESERVED3_ERR_2 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_2_Msk = 0xc00 + // Position of RPT4_RESERVED3_ERR_1 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_1_Pos = 0xc + // Bit mask of RPT4_RESERVED3_ERR_1 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_1_Msk = 0x1000 + // Bit RPT4_RESERVED3_ERR_1. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_1 = 0x1000 + // Position of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Pos = 0xd + // Bit mask of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Msk = 0x2000 + // Bit FORCE_SEND_RESUME_ERR. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR = 0x2000 + // Position of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Pos = 0xe + // Bit mask of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Msk = 0x3fffc000 + // Position of RPT4_RESERVED3_ERR_0 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_0_Pos = 0x1e + // Bit mask of RPT4_RESERVED3_ERR_0 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_0_Msk = 0xc0000000 + + // RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. + // Position of RPT4_RESERVED4_ERR_1 field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_1_Pos = 0x0 + // Bit mask of RPT4_RESERVED4_ERR_1 field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_1_Msk = 0xffffff + // Position of RPT4_RESERVED4_ERR_0 field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_0_Pos = 0x18 + // Bit mask of RPT4_RESERVED4_ERR_0 field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_0_Msk = 0xff000000 + + // RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. + // Position of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Pos = 0x0 + // Bit mask of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Msk = 0x7 + // Position of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Pos = 0x3 + // Bit mask of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Msk = 0x8 + // Bit MAC_SPI_8M_FAIL. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL = 0x8 + // Position of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Pos = 0x4 + // Bit mask of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Msk = 0x70 + // Position of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Pos = 0x7 + // Bit mask of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Msk = 0x80 + // Bit SYS_PART1_FAIL. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL = 0x80 + // Position of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Pos = 0x8 + // Bit mask of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Msk = 0x700 + // Position of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Pos = 0xb + // Bit mask of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Msk = 0x800 + // Bit USR_DATA_FAIL. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL = 0x800 + // Position of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Pos = 0xc + // Bit mask of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Msk = 0x7000 + // Position of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Pos = 0xf + // Bit mask of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Msk = 0x8000 + // Bit KEY0_FAIL. + EFUSE_RD_RS_ERR0_KEY0_FAIL = 0x8000 + // Position of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Pos = 0x10 + // Bit mask of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Msk = 0x70000 + // Position of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Pos = 0x13 + // Bit mask of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Msk = 0x80000 + // Bit KEY1_FAIL. + EFUSE_RD_RS_ERR0_KEY1_FAIL = 0x80000 + // Position of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Pos = 0x14 + // Bit mask of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Msk = 0x700000 + // Position of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Pos = 0x17 + // Bit mask of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Msk = 0x800000 + // Bit KEY2_FAIL. + EFUSE_RD_RS_ERR0_KEY2_FAIL = 0x800000 + // Position of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Pos = 0x18 + // Bit mask of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Msk = 0x7000000 + // Position of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Pos = 0x1b + // Bit mask of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Msk = 0x8000000 + // Bit KEY3_FAIL. + EFUSE_RD_RS_ERR0_KEY3_FAIL = 0x8000000 + // Position of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Pos = 0x1c + // Bit mask of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Msk = 0x70000000 + // Position of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Pos = 0x1f + // Bit mask of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Msk = 0x80000000 + // Bit KEY4_FAIL. + EFUSE_RD_RS_ERR0_KEY4_FAIL = 0x80000000 + + // RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. + // Position of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Pos = 0x0 + // Bit mask of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Msk = 0x7 + // Position of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Pos = 0x3 + // Bit mask of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Msk = 0x8 + // Bit KEY5_FAIL. + EFUSE_RD_RS_ERR1_KEY5_FAIL = 0x8 + // Position of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Pos = 0x4 + // Bit mask of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Msk = 0x70 + // Position of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Pos = 0x7 + // Bit mask of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Msk = 0x80 + // Bit SYS_PART2_FAIL. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL = 0x80 + + // CLK: eFuse clcok configuration register. + // Position of MEM_FORCE_PD field. + EFUSE_CLK_MEM_FORCE_PD_Pos = 0x0 + // Bit mask of MEM_FORCE_PD field. + EFUSE_CLK_MEM_FORCE_PD_Msk = 0x1 + // Bit MEM_FORCE_PD. + EFUSE_CLK_MEM_FORCE_PD = 0x1 + // Position of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + EFUSE_CLK_MEM_CLK_FORCE_ON = 0x2 + // Position of MEM_FORCE_PU field. + EFUSE_CLK_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of MEM_FORCE_PU field. + EFUSE_CLK_MEM_FORCE_PU_Msk = 0x4 + // Bit MEM_FORCE_PU. + EFUSE_CLK_MEM_FORCE_PU = 0x4 + // Position of EN field. + EFUSE_CLK_EN_Pos = 0x10 + // Bit mask of EN field. + EFUSE_CLK_EN_Msk = 0x10000 + // Bit EN. + EFUSE_CLK_EN = 0x10000 + + // CONF: eFuse operation mode configuraiton register + // Position of OP_CODE field. + EFUSE_CONF_OP_CODE_Pos = 0x0 + // Bit mask of OP_CODE field. + EFUSE_CONF_OP_CODE_Msk = 0xffff + + // STATUS: eFuse status register. + // Position of STATE field. + EFUSE_STATUS_STATE_Pos = 0x0 + // Bit mask of STATE field. + EFUSE_STATUS_STATE_Msk = 0xf + // Position of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Pos = 0x4 + // Bit mask of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Msk = 0x10 + // Bit OTP_LOAD_SW. + EFUSE_STATUS_OTP_LOAD_SW = 0x10 + // Position of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Pos = 0x5 + // Bit mask of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Msk = 0x20 + // Bit OTP_VDDQ_C_SYNC2. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2 = 0x20 + // Position of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Pos = 0x6 + // Bit mask of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Msk = 0x40 + // Bit OTP_STROBE_SW. + EFUSE_STATUS_OTP_STROBE_SW = 0x40 + // Position of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Pos = 0x7 + // Bit mask of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Msk = 0x80 + // Bit OTP_CSB_SW. + EFUSE_STATUS_OTP_CSB_SW = 0x80 + // Position of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Pos = 0x8 + // Bit mask of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Msk = 0x100 + // Bit OTP_PGENB_SW. + EFUSE_STATUS_OTP_PGENB_SW = 0x100 + // Position of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Pos = 0x9 + // Bit mask of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Msk = 0x200 + // Bit OTP_VDDQ_IS_SW. + EFUSE_STATUS_OTP_VDDQ_IS_SW = 0x200 + // Position of BLK0_VALID_BIT_CNT field. + EFUSE_STATUS_BLK0_VALID_BIT_CNT_Pos = 0xa + // Bit mask of BLK0_VALID_BIT_CNT field. + EFUSE_STATUS_BLK0_VALID_BIT_CNT_Msk = 0xffc00 + + // CMD: eFuse command register. + // Position of READ_CMD field. + EFUSE_CMD_READ_CMD_Pos = 0x0 + // Bit mask of READ_CMD field. + EFUSE_CMD_READ_CMD_Msk = 0x1 + // Bit READ_CMD. + EFUSE_CMD_READ_CMD = 0x1 + // Position of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Pos = 0x1 + // Bit mask of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Msk = 0x2 + // Bit PGM_CMD. + EFUSE_CMD_PGM_CMD = 0x2 + // Position of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Pos = 0x2 + // Bit mask of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Msk = 0x3c + + // INT_RAW: eFuse raw interrupt register. + // Position of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Pos = 0x0 + // Bit mask of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Msk = 0x1 + // Bit READ_DONE_INT_RAW. + EFUSE_INT_RAW_READ_DONE_INT_RAW = 0x1 + // Position of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Pos = 0x1 + // Bit mask of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Msk = 0x2 + // Bit PGM_DONE_INT_RAW. + EFUSE_INT_RAW_PGM_DONE_INT_RAW = 0x2 + + // INT_ST: eFuse interrupt status register. + // Position of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Pos = 0x0 + // Bit mask of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Msk = 0x1 + // Bit READ_DONE_INT_ST. + EFUSE_INT_ST_READ_DONE_INT_ST = 0x1 + // Position of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Msk = 0x2 + // Bit PGM_DONE_INT_ST. + EFUSE_INT_ST_PGM_DONE_INT_ST = 0x2 + + // INT_ENA: eFuse interrupt enable register. + // Position of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Pos = 0x0 + // Bit mask of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Msk = 0x1 + // Bit READ_DONE_INT_ENA. + EFUSE_INT_ENA_READ_DONE_INT_ENA = 0x1 + // Position of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Msk = 0x2 + // Bit PGM_DONE_INT_ENA. + EFUSE_INT_ENA_PGM_DONE_INT_ENA = 0x2 + + // INT_CLR: eFuse interrupt clear register. + // Position of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Pos = 0x0 + // Bit mask of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Msk = 0x1 + // Bit READ_DONE_INT_CLR. + EFUSE_INT_CLR_READ_DONE_INT_CLR = 0x1 + // Position of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Pos = 0x1 + // Bit mask of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Msk = 0x2 + // Bit PGM_DONE_INT_CLR. + EFUSE_INT_CLR_PGM_DONE_INT_CLR = 0x2 + + // DAC_CONF: Controls the eFuse programming voltage. + // Position of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Pos = 0x0 + // Bit mask of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Msk = 0xff + // Position of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Pos = 0x8 + // Bit mask of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Msk = 0x100 + // Bit DAC_CLK_PAD_SEL. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL = 0x100 + // Position of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Pos = 0x9 + // Bit mask of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Msk = 0x1fe00 + // Position of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Pos = 0x11 + // Bit mask of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Msk = 0x20000 + // Bit OE_CLR. + EFUSE_DAC_CONF_OE_CLR = 0x20000 + + // RD_TIM_CONF: Configures read timing parameters. + // Position of THR_A field. + EFUSE_RD_TIM_CONF_THR_A_Pos = 0x0 + // Bit mask of THR_A field. + EFUSE_RD_TIM_CONF_THR_A_Msk = 0xff + // Position of TRD field. + EFUSE_RD_TIM_CONF_TRD_Pos = 0x8 + // Bit mask of TRD field. + EFUSE_RD_TIM_CONF_TRD_Msk = 0xff00 + // Position of TSUR_A field. + EFUSE_RD_TIM_CONF_TSUR_A_Pos = 0x10 + // Bit mask of TSUR_A field. + EFUSE_RD_TIM_CONF_TSUR_A_Msk = 0xff0000 + // Position of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Pos = 0x18 + // Bit mask of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Msk = 0xff000000 + + // WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters. + // Position of TSUP_A field. + EFUSE_WR_TIM_CONF1_TSUP_A_Pos = 0x0 + // Bit mask of TSUP_A field. + EFUSE_WR_TIM_CONF1_TSUP_A_Msk = 0xff + // Position of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Pos = 0x8 + // Bit mask of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Msk = 0xffff00 + // Position of THP_A field. + EFUSE_WR_TIM_CONF1_THP_A_Pos = 0x18 + // Bit mask of THP_A field. + EFUSE_WR_TIM_CONF1_THP_A_Msk = 0xff000000 + + // WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters. + // Position of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Pos = 0x0 + // Bit mask of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Msk = 0xffff + // Position of TPGM field. + EFUSE_WR_TIM_CONF2_TPGM_Pos = 0x10 + // Bit mask of TPGM field. + EFUSE_WR_TIM_CONF2_TPGM_Msk = 0xffff0000 + + // WR_TIM_CONF0_RS_BYPASS: Configurarion register0 of eFuse programming time parameters and rs bypass operation. + // Position of BYPASS_RS_CORRECTION field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION_Pos = 0x0 + // Bit mask of BYPASS_RS_CORRECTION field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION_Msk = 0x1 + // Bit BYPASS_RS_CORRECTION. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION = 0x1 + // Position of BYPASS_RS_BLK_NUM field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM_Pos = 0x1 + // Bit mask of BYPASS_RS_BLK_NUM field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM_Msk = 0xffe + // Position of UPDATE field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_UPDATE_Pos = 0xc + // Bit mask of UPDATE field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_UPDATE_Msk = 0x1000 + // Bit UPDATE. + EFUSE_WR_TIM_CONF0_RS_BYPASS_UPDATE = 0x1000 + // Position of TPGM_INACTIVE field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE_Pos = 0xd + // Bit mask of TPGM_INACTIVE field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE_Msk = 0x1fe000 + + // DATE: eFuse version register. + // Position of DATE field. + EFUSE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EFUSE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for EXTMEM: External Memory +const ( + // L1_ICACHE_CTRL: L1 instruction Cache(L1-ICache) control register + // Position of L1_ICACHE_SHUT_IBUS0 field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0_Pos = 0x0 + // Bit mask of L1_ICACHE_SHUT_IBUS0 field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0_Msk = 0x1 + // Bit L1_ICACHE_SHUT_IBUS0. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0 = 0x1 + // Position of L1_ICACHE_SHUT_IBUS1 field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1_Pos = 0x1 + // Bit mask of L1_ICACHE_SHUT_IBUS1 field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1_Msk = 0x2 + // Bit L1_ICACHE_SHUT_IBUS1. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1 = 0x2 + // Position of L1_ICACHE_SHUT_IBUS2 field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2_Pos = 0x2 + // Bit mask of L1_ICACHE_SHUT_IBUS2 field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2_Msk = 0x4 + // Bit L1_ICACHE_SHUT_IBUS2. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2 = 0x4 + // Position of L1_ICACHE_SHUT_IBUS3 field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3_Pos = 0x3 + // Bit mask of L1_ICACHE_SHUT_IBUS3 field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3_Msk = 0x8 + // Bit L1_ICACHE_SHUT_IBUS3. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3 = 0x8 + // Position of L1_ICACHE_UNDEF_OP field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP_Pos = 0x4 + // Bit mask of L1_ICACHE_UNDEF_OP field. + EXTMEM_L1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP_Msk = 0xf0 + + // L1_CACHE_CTRL: L1 data Cache(L1-Cache) control register + // Position of L1_CACHE_SHUT_BUS0 field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_BUS0_Pos = 0x0 + // Bit mask of L1_CACHE_SHUT_BUS0 field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_BUS0_Msk = 0x1 + // Bit L1_CACHE_SHUT_BUS0. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_BUS0 = 0x1 + // Position of L1_CACHE_SHUT_BUS1 field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_BUS1_Pos = 0x1 + // Bit mask of L1_CACHE_SHUT_BUS1 field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_BUS1_Msk = 0x2 + // Bit L1_CACHE_SHUT_BUS1. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_BUS1 = 0x2 + // Position of L1_CACHE_SHUT_DBUS2 field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_DBUS2_Pos = 0x2 + // Bit mask of L1_CACHE_SHUT_DBUS2 field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_DBUS2_Msk = 0x4 + // Bit L1_CACHE_SHUT_DBUS2. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_DBUS2 = 0x4 + // Position of L1_CACHE_SHUT_DBUS3 field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_DBUS3_Pos = 0x3 + // Bit mask of L1_CACHE_SHUT_DBUS3 field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_DBUS3_Msk = 0x8 + // Bit L1_CACHE_SHUT_DBUS3. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_DBUS3 = 0x8 + // Position of L1_CACHE_SHUT_DMA field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_DMA_Pos = 0x4 + // Bit mask of L1_CACHE_SHUT_DMA field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_DMA_Msk = 0x10 + // Bit L1_CACHE_SHUT_DMA. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_SHUT_DMA = 0x10 + // Position of L1_CACHE_UNDEF_OP field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_UNDEF_OP_Pos = 0x8 + // Bit mask of L1_CACHE_UNDEF_OP field. + EXTMEM_L1_CACHE_CTRL_L1_CACHE_UNDEF_OP_Msk = 0xf00 + + // L1_BYPASS_CACHE_CONF: Bypass Cache configure register + // Position of BYPASS_L1_ICACHE0_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN_Pos = 0x0 + // Bit mask of BYPASS_L1_ICACHE0_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN_Msk = 0x1 + // Bit BYPASS_L1_ICACHE0_EN. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN = 0x1 + // Position of BYPASS_L1_ICACHE1_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN_Pos = 0x1 + // Bit mask of BYPASS_L1_ICACHE1_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN_Msk = 0x2 + // Bit BYPASS_L1_ICACHE1_EN. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN = 0x2 + // Position of BYPASS_L1_ICACHE2_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN_Pos = 0x2 + // Bit mask of BYPASS_L1_ICACHE2_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN_Msk = 0x4 + // Bit BYPASS_L1_ICACHE2_EN. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN = 0x4 + // Position of BYPASS_L1_ICACHE3_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN_Pos = 0x3 + // Bit mask of BYPASS_L1_ICACHE3_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN_Msk = 0x8 + // Bit BYPASS_L1_ICACHE3_EN. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN = 0x8 + // Position of BYPASS_L1_DCACHE_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN_Pos = 0x4 + // Bit mask of BYPASS_L1_DCACHE_EN field. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN_Msk = 0x10 + // Bit BYPASS_L1_DCACHE_EN. + EXTMEM_L1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN = 0x10 + + // L1_CACHE_ATOMIC_CONF: L1 Cache atomic feature configure register + // Position of L1_CACHE_ATOMIC_EN field. + EXTMEM_L1_CACHE_ATOMIC_CONF_L1_CACHE_ATOMIC_EN_Pos = 0x0 + // Bit mask of L1_CACHE_ATOMIC_EN field. + EXTMEM_L1_CACHE_ATOMIC_CONF_L1_CACHE_ATOMIC_EN_Msk = 0x1 + // Bit L1_CACHE_ATOMIC_EN. + EXTMEM_L1_CACHE_ATOMIC_CONF_L1_CACHE_ATOMIC_EN = 0x1 + + // L1_ICACHE_CACHESIZE_CONF: L1 instruction Cache CacheSize mode configure register + // Position of L1_ICACHE_CACHESIZE_1K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K_Pos = 0x0 + // Bit mask of L1_ICACHE_CACHESIZE_1K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K_Msk = 0x1 + // Bit L1_ICACHE_CACHESIZE_1K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K = 0x1 + // Position of L1_ICACHE_CACHESIZE_2K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K_Pos = 0x1 + // Bit mask of L1_ICACHE_CACHESIZE_2K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K_Msk = 0x2 + // Bit L1_ICACHE_CACHESIZE_2K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K = 0x2 + // Position of L1_ICACHE_CACHESIZE_4K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K_Pos = 0x2 + // Bit mask of L1_ICACHE_CACHESIZE_4K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K_Msk = 0x4 + // Bit L1_ICACHE_CACHESIZE_4K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K = 0x4 + // Position of L1_ICACHE_CACHESIZE_8K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K_Pos = 0x3 + // Bit mask of L1_ICACHE_CACHESIZE_8K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K_Msk = 0x8 + // Bit L1_ICACHE_CACHESIZE_8K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K = 0x8 + // Position of L1_ICACHE_CACHESIZE_16K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K_Pos = 0x4 + // Bit mask of L1_ICACHE_CACHESIZE_16K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K_Msk = 0x10 + // Bit L1_ICACHE_CACHESIZE_16K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K = 0x10 + // Position of L1_ICACHE_CACHESIZE_32K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K_Pos = 0x5 + // Bit mask of L1_ICACHE_CACHESIZE_32K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K_Msk = 0x20 + // Bit L1_ICACHE_CACHESIZE_32K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K = 0x20 + // Position of L1_ICACHE_CACHESIZE_64K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K_Pos = 0x6 + // Bit mask of L1_ICACHE_CACHESIZE_64K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K_Msk = 0x40 + // Bit L1_ICACHE_CACHESIZE_64K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K = 0x40 + // Position of L1_ICACHE_CACHESIZE_128K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K_Pos = 0x7 + // Bit mask of L1_ICACHE_CACHESIZE_128K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K_Msk = 0x80 + // Bit L1_ICACHE_CACHESIZE_128K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K = 0x80 + // Position of L1_ICACHE_CACHESIZE_256K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K_Pos = 0x8 + // Bit mask of L1_ICACHE_CACHESIZE_256K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K_Msk = 0x100 + // Bit L1_ICACHE_CACHESIZE_256K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K = 0x100 + // Position of L1_ICACHE_CACHESIZE_512K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K_Pos = 0x9 + // Bit mask of L1_ICACHE_CACHESIZE_512K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K_Msk = 0x200 + // Bit L1_ICACHE_CACHESIZE_512K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K = 0x200 + // Position of L1_ICACHE_CACHESIZE_1024K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K_Pos = 0xa + // Bit mask of L1_ICACHE_CACHESIZE_1024K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K_Msk = 0x400 + // Bit L1_ICACHE_CACHESIZE_1024K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K = 0x400 + // Position of L1_ICACHE_CACHESIZE_2048K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2048K_Pos = 0xb + // Bit mask of L1_ICACHE_CACHESIZE_2048K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2048K_Msk = 0x800 + // Bit L1_ICACHE_CACHESIZE_2048K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2048K = 0x800 + // Position of L1_ICACHE_CACHESIZE_4096K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4096K_Pos = 0xc + // Bit mask of L1_ICACHE_CACHESIZE_4096K field. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4096K_Msk = 0x1000 + // Bit L1_ICACHE_CACHESIZE_4096K. + EXTMEM_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4096K = 0x1000 + + // L1_ICACHE_BLOCKSIZE_CONF: L1 instruction Cache BlockSize mode configure register + // Position of L1_ICACHE_BLOCKSIZE_8 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8_Pos = 0x0 + // Bit mask of L1_ICACHE_BLOCKSIZE_8 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8_Msk = 0x1 + // Bit L1_ICACHE_BLOCKSIZE_8. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8 = 0x1 + // Position of L1_ICACHE_BLOCKSIZE_16 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16_Pos = 0x1 + // Bit mask of L1_ICACHE_BLOCKSIZE_16 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16_Msk = 0x2 + // Bit L1_ICACHE_BLOCKSIZE_16. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16 = 0x2 + // Position of L1_ICACHE_BLOCKSIZE_32 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32_Pos = 0x2 + // Bit mask of L1_ICACHE_BLOCKSIZE_32 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32_Msk = 0x4 + // Bit L1_ICACHE_BLOCKSIZE_32. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32 = 0x4 + // Position of L1_ICACHE_BLOCKSIZE_64 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64_Pos = 0x3 + // Bit mask of L1_ICACHE_BLOCKSIZE_64 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64_Msk = 0x8 + // Bit L1_ICACHE_BLOCKSIZE_64. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64 = 0x8 + // Position of L1_ICACHE_BLOCKSIZE_128 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128_Pos = 0x4 + // Bit mask of L1_ICACHE_BLOCKSIZE_128 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128_Msk = 0x10 + // Bit L1_ICACHE_BLOCKSIZE_128. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128 = 0x10 + // Position of L1_ICACHE_BLOCKSIZE_256 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256_Pos = 0x5 + // Bit mask of L1_ICACHE_BLOCKSIZE_256 field. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256_Msk = 0x20 + // Bit L1_ICACHE_BLOCKSIZE_256. + EXTMEM_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256 = 0x20 + + // L1_CACHE_CACHESIZE_CONF: L1 data Cache CacheSize mode configure register + // Position of L1_CACHE_CACHESIZE_1K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1K_Pos = 0x0 + // Bit mask of L1_CACHE_CACHESIZE_1K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1K_Msk = 0x1 + // Bit L1_CACHE_CACHESIZE_1K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1K = 0x1 + // Position of L1_CACHE_CACHESIZE_2K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2K_Pos = 0x1 + // Bit mask of L1_CACHE_CACHESIZE_2K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2K_Msk = 0x2 + // Bit L1_CACHE_CACHESIZE_2K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2K = 0x2 + // Position of L1_CACHE_CACHESIZE_4K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4K_Pos = 0x2 + // Bit mask of L1_CACHE_CACHESIZE_4K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4K_Msk = 0x4 + // Bit L1_CACHE_CACHESIZE_4K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4K = 0x4 + // Position of L1_CACHE_CACHESIZE_8K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_8K_Pos = 0x3 + // Bit mask of L1_CACHE_CACHESIZE_8K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_8K_Msk = 0x8 + // Bit L1_CACHE_CACHESIZE_8K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_8K = 0x8 + // Position of L1_CACHE_CACHESIZE_16K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_16K_Pos = 0x4 + // Bit mask of L1_CACHE_CACHESIZE_16K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_16K_Msk = 0x10 + // Bit L1_CACHE_CACHESIZE_16K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_16K = 0x10 + // Position of L1_CACHE_CACHESIZE_32K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_32K_Pos = 0x5 + // Bit mask of L1_CACHE_CACHESIZE_32K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_32K_Msk = 0x20 + // Bit L1_CACHE_CACHESIZE_32K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_32K = 0x20 + // Position of L1_CACHE_CACHESIZE_64K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_64K_Pos = 0x6 + // Bit mask of L1_CACHE_CACHESIZE_64K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_64K_Msk = 0x40 + // Bit L1_CACHE_CACHESIZE_64K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_64K = 0x40 + // Position of L1_CACHE_CACHESIZE_128K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_128K_Pos = 0x7 + // Bit mask of L1_CACHE_CACHESIZE_128K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_128K_Msk = 0x80 + // Bit L1_CACHE_CACHESIZE_128K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_128K = 0x80 + // Position of L1_CACHE_CACHESIZE_256K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_256K_Pos = 0x8 + // Bit mask of L1_CACHE_CACHESIZE_256K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_256K_Msk = 0x100 + // Bit L1_CACHE_CACHESIZE_256K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_256K = 0x100 + // Position of L1_CACHE_CACHESIZE_512K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_512K_Pos = 0x9 + // Bit mask of L1_CACHE_CACHESIZE_512K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_512K_Msk = 0x200 + // Bit L1_CACHE_CACHESIZE_512K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_512K = 0x200 + // Position of L1_CACHE_CACHESIZE_1024K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1024K_Pos = 0xa + // Bit mask of L1_CACHE_CACHESIZE_1024K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1024K_Msk = 0x400 + // Bit L1_CACHE_CACHESIZE_1024K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_1024K = 0x400 + // Position of L1_CACHE_CACHESIZE_2048K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2048K_Pos = 0xb + // Bit mask of L1_CACHE_CACHESIZE_2048K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2048K_Msk = 0x800 + // Bit L1_CACHE_CACHESIZE_2048K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_2048K = 0x800 + // Position of L1_CACHE_CACHESIZE_4096K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4096K_Pos = 0xc + // Bit mask of L1_CACHE_CACHESIZE_4096K field. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4096K_Msk = 0x1000 + // Bit L1_CACHE_CACHESIZE_4096K. + EXTMEM_L1_CACHE_CACHESIZE_CONF_L1_CACHE_CACHESIZE_4096K = 0x1000 + + // L1_CACHE_BLOCKSIZE_CONF: L1 data Cache BlockSize mode configure register + // Position of L1_CACHE_BLOCKSIZE_8 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_8_Pos = 0x0 + // Bit mask of L1_CACHE_BLOCKSIZE_8 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_8_Msk = 0x1 + // Bit L1_CACHE_BLOCKSIZE_8. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_8 = 0x1 + // Position of L1_CACHE_BLOCKSIZE_16 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_16_Pos = 0x1 + // Bit mask of L1_CACHE_BLOCKSIZE_16 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_16_Msk = 0x2 + // Bit L1_CACHE_BLOCKSIZE_16. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_16 = 0x2 + // Position of L1_CACHE_BLOCKSIZE_32 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_32_Pos = 0x2 + // Bit mask of L1_CACHE_BLOCKSIZE_32 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_32_Msk = 0x4 + // Bit L1_CACHE_BLOCKSIZE_32. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_32 = 0x4 + // Position of L1_CACHE_BLOCKSIZE_64 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_64_Pos = 0x3 + // Bit mask of L1_CACHE_BLOCKSIZE_64 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_64_Msk = 0x8 + // Bit L1_CACHE_BLOCKSIZE_64. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_64 = 0x8 + // Position of L1_CACHE_BLOCKSIZE_128 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_128_Pos = 0x4 + // Bit mask of L1_CACHE_BLOCKSIZE_128 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_128_Msk = 0x10 + // Bit L1_CACHE_BLOCKSIZE_128. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_128 = 0x10 + // Position of L1_CACHE_BLOCKSIZE_256 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_256_Pos = 0x5 + // Bit mask of L1_CACHE_BLOCKSIZE_256 field. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_256_Msk = 0x20 + // Bit L1_CACHE_BLOCKSIZE_256. + EXTMEM_L1_CACHE_BLOCKSIZE_CONF_L1_CACHE_BLOCKSIZE_256 = 0x20 + + // L1_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register + // Position of L1_ICACHE0_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP_Pos = 0x0 + // Bit mask of L1_ICACHE0_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP_Msk = 0x1 + // Bit L1_ICACHE0_WRAP. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP = 0x1 + // Position of L1_ICACHE1_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP_Pos = 0x1 + // Bit mask of L1_ICACHE1_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP_Msk = 0x2 + // Bit L1_ICACHE1_WRAP. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP = 0x2 + // Position of L1_ICACHE2_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP_Pos = 0x2 + // Bit mask of L1_ICACHE2_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP_Msk = 0x4 + // Bit L1_ICACHE2_WRAP. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP = 0x4 + // Position of L1_ICACHE3_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP_Pos = 0x3 + // Bit mask of L1_ICACHE3_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP_Msk = 0x8 + // Bit L1_ICACHE3_WRAP. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP = 0x8 + // Position of L1_CACHE_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_CACHE_WRAP_Pos = 0x4 + // Bit mask of L1_CACHE_WRAP field. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_CACHE_WRAP_Msk = 0x10 + // Bit L1_CACHE_WRAP. + EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_L1_CACHE_WRAP = 0x10 + + // L1_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register + // Position of L1_ICACHE0_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of L1_ICACHE0_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON_Msk = 0x1 + // Bit L1_ICACHE0_TAG_MEM_FORCE_ON. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON = 0x1 + // Position of L1_ICACHE0_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of L1_ICACHE0_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD_Msk = 0x2 + // Bit L1_ICACHE0_TAG_MEM_FORCE_PD. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD = 0x2 + // Position of L1_ICACHE0_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of L1_ICACHE0_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU_Msk = 0x4 + // Bit L1_ICACHE0_TAG_MEM_FORCE_PU. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU = 0x4 + // Position of L1_ICACHE1_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON_Pos = 0x4 + // Bit mask of L1_ICACHE1_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON_Msk = 0x10 + // Bit L1_ICACHE1_TAG_MEM_FORCE_ON. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON = 0x10 + // Position of L1_ICACHE1_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD_Pos = 0x5 + // Bit mask of L1_ICACHE1_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD_Msk = 0x20 + // Bit L1_ICACHE1_TAG_MEM_FORCE_PD. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD = 0x20 + // Position of L1_ICACHE1_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU_Pos = 0x6 + // Bit mask of L1_ICACHE1_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU_Msk = 0x40 + // Bit L1_ICACHE1_TAG_MEM_FORCE_PU. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU = 0x40 + // Position of L1_ICACHE2_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON_Pos = 0x8 + // Bit mask of L1_ICACHE2_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON_Msk = 0x100 + // Bit L1_ICACHE2_TAG_MEM_FORCE_ON. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON = 0x100 + // Position of L1_ICACHE2_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD_Pos = 0x9 + // Bit mask of L1_ICACHE2_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD_Msk = 0x200 + // Bit L1_ICACHE2_TAG_MEM_FORCE_PD. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD = 0x200 + // Position of L1_ICACHE2_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU_Pos = 0xa + // Bit mask of L1_ICACHE2_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU_Msk = 0x400 + // Bit L1_ICACHE2_TAG_MEM_FORCE_PU. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU = 0x400 + // Position of L1_ICACHE3_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON_Pos = 0xc + // Bit mask of L1_ICACHE3_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON_Msk = 0x1000 + // Bit L1_ICACHE3_TAG_MEM_FORCE_ON. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON = 0x1000 + // Position of L1_ICACHE3_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD_Pos = 0xd + // Bit mask of L1_ICACHE3_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD_Msk = 0x2000 + // Bit L1_ICACHE3_TAG_MEM_FORCE_PD. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD = 0x2000 + // Position of L1_ICACHE3_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU_Pos = 0xe + // Bit mask of L1_ICACHE3_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU_Msk = 0x4000 + // Bit L1_ICACHE3_TAG_MEM_FORCE_PU. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU = 0x4000 + // Position of L1_CACHE_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_ON_Pos = 0x10 + // Bit mask of L1_CACHE_TAG_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_ON_Msk = 0x10000 + // Bit L1_CACHE_TAG_MEM_FORCE_ON. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_ON = 0x10000 + // Position of L1_CACHE_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PD_Pos = 0x11 + // Bit mask of L1_CACHE_TAG_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PD_Msk = 0x20000 + // Bit L1_CACHE_TAG_MEM_FORCE_PD. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PD = 0x20000 + // Position of L1_CACHE_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PU_Pos = 0x12 + // Bit mask of L1_CACHE_TAG_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PU_Msk = 0x40000 + // Bit L1_CACHE_TAG_MEM_FORCE_PU. + EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_L1_CACHE_TAG_MEM_FORCE_PU = 0x40000 + + // L1_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register + // Position of L1_ICACHE0_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of L1_ICACHE0_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON_Msk = 0x1 + // Bit L1_ICACHE0_DATA_MEM_FORCE_ON. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON = 0x1 + // Position of L1_ICACHE0_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of L1_ICACHE0_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD_Msk = 0x2 + // Bit L1_ICACHE0_DATA_MEM_FORCE_PD. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD = 0x2 + // Position of L1_ICACHE0_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of L1_ICACHE0_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU_Msk = 0x4 + // Bit L1_ICACHE0_DATA_MEM_FORCE_PU. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU = 0x4 + // Position of L1_ICACHE1_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON_Pos = 0x4 + // Bit mask of L1_ICACHE1_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON_Msk = 0x10 + // Bit L1_ICACHE1_DATA_MEM_FORCE_ON. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON = 0x10 + // Position of L1_ICACHE1_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD_Pos = 0x5 + // Bit mask of L1_ICACHE1_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD_Msk = 0x20 + // Bit L1_ICACHE1_DATA_MEM_FORCE_PD. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD = 0x20 + // Position of L1_ICACHE1_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU_Pos = 0x6 + // Bit mask of L1_ICACHE1_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU_Msk = 0x40 + // Bit L1_ICACHE1_DATA_MEM_FORCE_PU. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU = 0x40 + // Position of L1_ICACHE2_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON_Pos = 0x8 + // Bit mask of L1_ICACHE2_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON_Msk = 0x100 + // Bit L1_ICACHE2_DATA_MEM_FORCE_ON. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON = 0x100 + // Position of L1_ICACHE2_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD_Pos = 0x9 + // Bit mask of L1_ICACHE2_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD_Msk = 0x200 + // Bit L1_ICACHE2_DATA_MEM_FORCE_PD. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD = 0x200 + // Position of L1_ICACHE2_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU_Pos = 0xa + // Bit mask of L1_ICACHE2_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU_Msk = 0x400 + // Bit L1_ICACHE2_DATA_MEM_FORCE_PU. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU = 0x400 + // Position of L1_ICACHE3_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON_Pos = 0xc + // Bit mask of L1_ICACHE3_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON_Msk = 0x1000 + // Bit L1_ICACHE3_DATA_MEM_FORCE_ON. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON = 0x1000 + // Position of L1_ICACHE3_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD_Pos = 0xd + // Bit mask of L1_ICACHE3_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD_Msk = 0x2000 + // Bit L1_ICACHE3_DATA_MEM_FORCE_PD. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD = 0x2000 + // Position of L1_ICACHE3_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU_Pos = 0xe + // Bit mask of L1_ICACHE3_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU_Msk = 0x4000 + // Bit L1_ICACHE3_DATA_MEM_FORCE_PU. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU = 0x4000 + // Position of L1_CACHE_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_ON_Pos = 0x10 + // Bit mask of L1_CACHE_DATA_MEM_FORCE_ON field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_ON_Msk = 0x10000 + // Bit L1_CACHE_DATA_MEM_FORCE_ON. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_ON = 0x10000 + // Position of L1_CACHE_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PD_Pos = 0x11 + // Bit mask of L1_CACHE_DATA_MEM_FORCE_PD field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PD_Msk = 0x20000 + // Bit L1_CACHE_DATA_MEM_FORCE_PD. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PD = 0x20000 + // Position of L1_CACHE_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PU_Pos = 0x12 + // Bit mask of L1_CACHE_DATA_MEM_FORCE_PU field. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PU_Msk = 0x40000 + // Bit L1_CACHE_DATA_MEM_FORCE_PU. + EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_L1_CACHE_DATA_MEM_FORCE_PU = 0x40000 + + // L1_CACHE_FREEZE_CTRL: Cache Freeze control register + // Position of L1_ICACHE0_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN_Pos = 0x0 + // Bit mask of L1_ICACHE0_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN_Msk = 0x1 + // Bit L1_ICACHE0_FREEZE_EN. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN = 0x1 + // Position of L1_ICACHE0_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE_Pos = 0x1 + // Bit mask of L1_ICACHE0_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE_Msk = 0x2 + // Bit L1_ICACHE0_FREEZE_MODE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE = 0x2 + // Position of L1_ICACHE0_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE_Pos = 0x2 + // Bit mask of L1_ICACHE0_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE_Msk = 0x4 + // Bit L1_ICACHE0_FREEZE_DONE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE = 0x4 + // Position of L1_ICACHE1_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN_Pos = 0x4 + // Bit mask of L1_ICACHE1_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN_Msk = 0x10 + // Bit L1_ICACHE1_FREEZE_EN. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN = 0x10 + // Position of L1_ICACHE1_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE_Pos = 0x5 + // Bit mask of L1_ICACHE1_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE_Msk = 0x20 + // Bit L1_ICACHE1_FREEZE_MODE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE = 0x20 + // Position of L1_ICACHE1_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE_Pos = 0x6 + // Bit mask of L1_ICACHE1_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE_Msk = 0x40 + // Bit L1_ICACHE1_FREEZE_DONE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE = 0x40 + // Position of L1_ICACHE2_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN_Pos = 0x8 + // Bit mask of L1_ICACHE2_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN_Msk = 0x100 + // Bit L1_ICACHE2_FREEZE_EN. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN = 0x100 + // Position of L1_ICACHE2_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE_Pos = 0x9 + // Bit mask of L1_ICACHE2_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE_Msk = 0x200 + // Bit L1_ICACHE2_FREEZE_MODE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE = 0x200 + // Position of L1_ICACHE2_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE_Pos = 0xa + // Bit mask of L1_ICACHE2_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE_Msk = 0x400 + // Bit L1_ICACHE2_FREEZE_DONE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE = 0x400 + // Position of L1_ICACHE3_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN_Pos = 0xc + // Bit mask of L1_ICACHE3_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN_Msk = 0x1000 + // Bit L1_ICACHE3_FREEZE_EN. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN = 0x1000 + // Position of L1_ICACHE3_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE_Pos = 0xd + // Bit mask of L1_ICACHE3_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE_Msk = 0x2000 + // Bit L1_ICACHE3_FREEZE_MODE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE = 0x2000 + // Position of L1_ICACHE3_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE_Pos = 0xe + // Bit mask of L1_ICACHE3_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE_Msk = 0x4000 + // Bit L1_ICACHE3_FREEZE_DONE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE = 0x4000 + // Position of L1_CACHE_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_EN_Pos = 0x10 + // Bit mask of L1_CACHE_FREEZE_EN field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_EN_Msk = 0x10000 + // Bit L1_CACHE_FREEZE_EN. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_EN = 0x10000 + // Position of L1_CACHE_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_MODE_Pos = 0x11 + // Bit mask of L1_CACHE_FREEZE_MODE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_MODE_Msk = 0x20000 + // Bit L1_CACHE_FREEZE_MODE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_MODE = 0x20000 + // Position of L1_CACHE_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_DONE_Pos = 0x12 + // Bit mask of L1_CACHE_FREEZE_DONE field. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_DONE_Msk = 0x40000 + // Bit L1_CACHE_FREEZE_DONE. + EXTMEM_L1_CACHE_FREEZE_CTRL_L1_CACHE_FREEZE_DONE = 0x40000 + + // L1_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register + // Position of L1_ICACHE0_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN_Pos = 0x0 + // Bit mask of L1_ICACHE0_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN_Msk = 0x1 + // Bit L1_ICACHE0_DATA_MEM_RD_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN = 0x1 + // Position of L1_ICACHE0_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN_Pos = 0x1 + // Bit mask of L1_ICACHE0_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN_Msk = 0x2 + // Bit L1_ICACHE0_DATA_MEM_WR_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN = 0x2 + // Position of L1_ICACHE1_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN_Pos = 0x4 + // Bit mask of L1_ICACHE1_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN_Msk = 0x10 + // Bit L1_ICACHE1_DATA_MEM_RD_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN = 0x10 + // Position of L1_ICACHE1_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN_Pos = 0x5 + // Bit mask of L1_ICACHE1_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN_Msk = 0x20 + // Bit L1_ICACHE1_DATA_MEM_WR_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN = 0x20 + // Position of L1_ICACHE2_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN_Pos = 0x8 + // Bit mask of L1_ICACHE2_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN_Msk = 0x100 + // Bit L1_ICACHE2_DATA_MEM_RD_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN = 0x100 + // Position of L1_ICACHE2_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN_Pos = 0x9 + // Bit mask of L1_ICACHE2_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN_Msk = 0x200 + // Bit L1_ICACHE2_DATA_MEM_WR_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN = 0x200 + // Position of L1_ICACHE3_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN_Pos = 0xc + // Bit mask of L1_ICACHE3_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN_Msk = 0x1000 + // Bit L1_ICACHE3_DATA_MEM_RD_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN = 0x1000 + // Position of L1_ICACHE3_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN_Pos = 0xd + // Bit mask of L1_ICACHE3_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN_Msk = 0x2000 + // Bit L1_ICACHE3_DATA_MEM_WR_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN = 0x2000 + // Position of L1_CACHE_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_RD_EN_Pos = 0x10 + // Bit mask of L1_CACHE_DATA_MEM_RD_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_RD_EN_Msk = 0x10000 + // Bit L1_CACHE_DATA_MEM_RD_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_RD_EN = 0x10000 + // Position of L1_CACHE_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_WR_EN_Pos = 0x11 + // Bit mask of L1_CACHE_DATA_MEM_WR_EN field. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_WR_EN_Msk = 0x20000 + // Bit L1_CACHE_DATA_MEM_WR_EN. + EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_L1_CACHE_DATA_MEM_WR_EN = 0x20000 + + // L1_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register + // Position of L1_ICACHE0_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN_Pos = 0x0 + // Bit mask of L1_ICACHE0_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN_Msk = 0x1 + // Bit L1_ICACHE0_TAG_MEM_RD_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN = 0x1 + // Position of L1_ICACHE0_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN_Pos = 0x1 + // Bit mask of L1_ICACHE0_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN_Msk = 0x2 + // Bit L1_ICACHE0_TAG_MEM_WR_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN = 0x2 + // Position of L1_ICACHE1_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN_Pos = 0x4 + // Bit mask of L1_ICACHE1_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN_Msk = 0x10 + // Bit L1_ICACHE1_TAG_MEM_RD_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN = 0x10 + // Position of L1_ICACHE1_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN_Pos = 0x5 + // Bit mask of L1_ICACHE1_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN_Msk = 0x20 + // Bit L1_ICACHE1_TAG_MEM_WR_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN = 0x20 + // Position of L1_ICACHE2_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN_Pos = 0x8 + // Bit mask of L1_ICACHE2_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN_Msk = 0x100 + // Bit L1_ICACHE2_TAG_MEM_RD_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN = 0x100 + // Position of L1_ICACHE2_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN_Pos = 0x9 + // Bit mask of L1_ICACHE2_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN_Msk = 0x200 + // Bit L1_ICACHE2_TAG_MEM_WR_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN = 0x200 + // Position of L1_ICACHE3_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN_Pos = 0xc + // Bit mask of L1_ICACHE3_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN_Msk = 0x1000 + // Bit L1_ICACHE3_TAG_MEM_RD_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN = 0x1000 + // Position of L1_ICACHE3_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN_Pos = 0xd + // Bit mask of L1_ICACHE3_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN_Msk = 0x2000 + // Bit L1_ICACHE3_TAG_MEM_WR_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN = 0x2000 + // Position of L1_CACHE_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_RD_EN_Pos = 0x10 + // Bit mask of L1_CACHE_TAG_MEM_RD_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_RD_EN_Msk = 0x10000 + // Bit L1_CACHE_TAG_MEM_RD_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_RD_EN = 0x10000 + // Position of L1_CACHE_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_WR_EN_Pos = 0x11 + // Bit mask of L1_CACHE_TAG_MEM_WR_EN field. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_WR_EN_Msk = 0x20000 + // Bit L1_CACHE_TAG_MEM_WR_EN. + EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_L1_CACHE_TAG_MEM_WR_EN = 0x20000 + + // L1_ICACHE0_PRELOCK_CONF: L1 instruction Cache 0 prelock configure register + // Position of L1_ICACHE0_PRELOCK_SCT0_EN field. + EXTMEM_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN_Pos = 0x0 + // Bit mask of L1_ICACHE0_PRELOCK_SCT0_EN field. + EXTMEM_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN_Msk = 0x1 + // Bit L1_ICACHE0_PRELOCK_SCT0_EN. + EXTMEM_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN = 0x1 + // Position of L1_ICACHE0_PRELOCK_SCT1_EN field. + EXTMEM_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN_Pos = 0x1 + // Bit mask of L1_ICACHE0_PRELOCK_SCT1_EN field. + EXTMEM_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN_Msk = 0x2 + // Bit L1_ICACHE0_PRELOCK_SCT1_EN. + EXTMEM_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN = 0x2 + // Position of L1_ICACHE0_PRELOCK_RGID field. + EXTMEM_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID_Pos = 0x2 + // Bit mask of L1_ICACHE0_PRELOCK_RGID field. + EXTMEM_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID_Msk = 0x3c + + // L1_ICACHE0_PRELOCK_SCT0_ADDR: L1 instruction Cache 0 prelock section0 address configure register + // Position of L1_ICACHE0_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_ICACHE0_PRELOCK_SCT0_ADDR_L1_ICACHE0_PRELOCK_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE0_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_ICACHE0_PRELOCK_SCT0_ADDR_L1_ICACHE0_PRELOCK_SCT0_ADDR_Msk = 0xffffffff + + // L1_ICACHE0_PRELOCK_SCT1_ADDR: L1 instruction Cache 0 prelock section1 address configure register + // Position of L1_ICACHE0_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_ICACHE0_PRELOCK_SCT1_ADDR_L1_ICACHE0_PRELOCK_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE0_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_ICACHE0_PRELOCK_SCT1_ADDR_L1_ICACHE0_PRELOCK_SCT1_ADDR_Msk = 0xffffffff + + // L1_ICACHE0_PRELOCK_SCT_SIZE: L1 instruction Cache 0 prelock section size configure register + // Position of L1_ICACHE0_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE0_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE_Msk = 0x3fff + // Position of L1_ICACHE0_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE_Pos = 0x10 + // Bit mask of L1_ICACHE0_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000 + + // L1_ICACHE1_PRELOCK_CONF: L1 instruction Cache 1 prelock configure register + // Position of L1_ICACHE1_PRELOCK_SCT0_EN field. + EXTMEM_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN_Pos = 0x0 + // Bit mask of L1_ICACHE1_PRELOCK_SCT0_EN field. + EXTMEM_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN_Msk = 0x1 + // Bit L1_ICACHE1_PRELOCK_SCT0_EN. + EXTMEM_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN = 0x1 + // Position of L1_ICACHE1_PRELOCK_SCT1_EN field. + EXTMEM_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN_Pos = 0x1 + // Bit mask of L1_ICACHE1_PRELOCK_SCT1_EN field. + EXTMEM_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN_Msk = 0x2 + // Bit L1_ICACHE1_PRELOCK_SCT1_EN. + EXTMEM_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN = 0x2 + // Position of L1_ICACHE1_PRELOCK_RGID field. + EXTMEM_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID_Pos = 0x2 + // Bit mask of L1_ICACHE1_PRELOCK_RGID field. + EXTMEM_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID_Msk = 0x3c + + // L1_ICACHE1_PRELOCK_SCT0_ADDR: L1 instruction Cache 1 prelock section0 address configure register + // Position of L1_ICACHE1_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_ICACHE1_PRELOCK_SCT0_ADDR_L1_ICACHE1_PRELOCK_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE1_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_ICACHE1_PRELOCK_SCT0_ADDR_L1_ICACHE1_PRELOCK_SCT0_ADDR_Msk = 0xffffffff + + // L1_ICACHE1_PRELOCK_SCT1_ADDR: L1 instruction Cache 1 prelock section1 address configure register + // Position of L1_ICACHE1_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_ICACHE1_PRELOCK_SCT1_ADDR_L1_ICACHE1_PRELOCK_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE1_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_ICACHE1_PRELOCK_SCT1_ADDR_L1_ICACHE1_PRELOCK_SCT1_ADDR_Msk = 0xffffffff + + // L1_ICACHE1_PRELOCK_SCT_SIZE: L1 instruction Cache 1 prelock section size configure register + // Position of L1_ICACHE1_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE1_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE_Msk = 0x3fff + // Position of L1_ICACHE1_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE_Pos = 0x10 + // Bit mask of L1_ICACHE1_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000 + + // L1_ICACHE2_PRELOCK_CONF: L1 instruction Cache 2 prelock configure register + // Position of L1_ICACHE2_PRELOCK_SCT0_EN field. + EXTMEM_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN_Pos = 0x0 + // Bit mask of L1_ICACHE2_PRELOCK_SCT0_EN field. + EXTMEM_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN_Msk = 0x1 + // Bit L1_ICACHE2_PRELOCK_SCT0_EN. + EXTMEM_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN = 0x1 + // Position of L1_ICACHE2_PRELOCK_SCT1_EN field. + EXTMEM_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN_Pos = 0x1 + // Bit mask of L1_ICACHE2_PRELOCK_SCT1_EN field. + EXTMEM_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN_Msk = 0x2 + // Bit L1_ICACHE2_PRELOCK_SCT1_EN. + EXTMEM_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN = 0x2 + // Position of L1_ICACHE2_PRELOCK_RGID field. + EXTMEM_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID_Pos = 0x2 + // Bit mask of L1_ICACHE2_PRELOCK_RGID field. + EXTMEM_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID_Msk = 0x3c + + // L1_ICACHE2_PRELOCK_SCT0_ADDR: L1 instruction Cache 2 prelock section0 address configure register + // Position of L1_ICACHE2_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_ICACHE2_PRELOCK_SCT0_ADDR_L1_ICACHE2_PRELOCK_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE2_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_ICACHE2_PRELOCK_SCT0_ADDR_L1_ICACHE2_PRELOCK_SCT0_ADDR_Msk = 0xffffffff + + // L1_ICACHE2_PRELOCK_SCT1_ADDR: L1 instruction Cache 2 prelock section1 address configure register + // Position of L1_ICACHE2_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_ICACHE2_PRELOCK_SCT1_ADDR_L1_ICACHE2_PRELOCK_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE2_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_ICACHE2_PRELOCK_SCT1_ADDR_L1_ICACHE2_PRELOCK_SCT1_ADDR_Msk = 0xffffffff + + // L1_ICACHE2_PRELOCK_SCT_SIZE: L1 instruction Cache 2 prelock section size configure register + // Position of L1_ICACHE2_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE2_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE_Msk = 0x3fff + // Position of L1_ICACHE2_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE_Pos = 0x10 + // Bit mask of L1_ICACHE2_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000 + + // L1_ICACHE3_PRELOCK_CONF: L1 instruction Cache 3 prelock configure register + // Position of L1_ICACHE3_PRELOCK_SCT0_EN field. + EXTMEM_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN_Pos = 0x0 + // Bit mask of L1_ICACHE3_PRELOCK_SCT0_EN field. + EXTMEM_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN_Msk = 0x1 + // Bit L1_ICACHE3_PRELOCK_SCT0_EN. + EXTMEM_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN = 0x1 + // Position of L1_ICACHE3_PRELOCK_SCT1_EN field. + EXTMEM_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN_Pos = 0x1 + // Bit mask of L1_ICACHE3_PRELOCK_SCT1_EN field. + EXTMEM_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN_Msk = 0x2 + // Bit L1_ICACHE3_PRELOCK_SCT1_EN. + EXTMEM_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN = 0x2 + // Position of L1_ICACHE3_PRELOCK_RGID field. + EXTMEM_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID_Pos = 0x2 + // Bit mask of L1_ICACHE3_PRELOCK_RGID field. + EXTMEM_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID_Msk = 0x3c + + // L1_ICACHE3_PRELOCK_SCT0_ADDR: L1 instruction Cache 3 prelock section0 address configure register + // Position of L1_ICACHE3_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_ICACHE3_PRELOCK_SCT0_ADDR_L1_ICACHE3_PRELOCK_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE3_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_ICACHE3_PRELOCK_SCT0_ADDR_L1_ICACHE3_PRELOCK_SCT0_ADDR_Msk = 0xffffffff + + // L1_ICACHE3_PRELOCK_SCT1_ADDR: L1 instruction Cache 3 prelock section1 address configure register + // Position of L1_ICACHE3_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_ICACHE3_PRELOCK_SCT1_ADDR_L1_ICACHE3_PRELOCK_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE3_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_ICACHE3_PRELOCK_SCT1_ADDR_L1_ICACHE3_PRELOCK_SCT1_ADDR_Msk = 0xffffffff + + // L1_ICACHE3_PRELOCK_SCT_SIZE: L1 instruction Cache 3 prelock section size configure register + // Position of L1_ICACHE3_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE3_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE_Msk = 0x3fff + // Position of L1_ICACHE3_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE_Pos = 0x10 + // Bit mask of L1_ICACHE3_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000 + + // L1_CACHE_PRELOCK_CONF: L1 Cache prelock configure register + // Position of L1_CACHE_PRELOCK_SCT0_EN field. + EXTMEM_L1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT0_EN_Pos = 0x0 + // Bit mask of L1_CACHE_PRELOCK_SCT0_EN field. + EXTMEM_L1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT0_EN_Msk = 0x1 + // Bit L1_CACHE_PRELOCK_SCT0_EN. + EXTMEM_L1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT0_EN = 0x1 + // Position of L1_CACHE_PRELOCK_SCT1_EN field. + EXTMEM_L1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT1_EN_Pos = 0x1 + // Bit mask of L1_CACHE_PRELOCK_SCT1_EN field. + EXTMEM_L1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT1_EN_Msk = 0x2 + // Bit L1_CACHE_PRELOCK_SCT1_EN. + EXTMEM_L1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_SCT1_EN = 0x2 + // Position of L1_CACHE_PRELOCK_RGID field. + EXTMEM_L1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_RGID_Pos = 0x2 + // Bit mask of L1_CACHE_PRELOCK_RGID field. + EXTMEM_L1_CACHE_PRELOCK_CONF_L1_CACHE_PRELOCK_RGID_Msk = 0x3c + + // L1_CACHE_PRELOCK_SCT0_ADDR: L1 Cache prelock section0 address configure register + // Position of L1_CACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_L1_CACHE_PRELOCK_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_CACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_L1_CACHE_PRELOCK_SCT0_ADDR_Msk = 0xffffffff + + // L1_DCACHE_PRELOCK_SCT1_ADDR: L1 Cache prelock section1 address configure register + // Position of L1_CACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_DCACHE_PRELOCK_SCT1_ADDR_L1_CACHE_PRELOCK_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_CACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_L1_DCACHE_PRELOCK_SCT1_ADDR_L1_CACHE_PRELOCK_SCT1_ADDR_Msk = 0xffffffff + + // L1_DCACHE_PRELOCK_SCT_SIZE: L1 Cache prelock section size configure register + // Position of L1_CACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_DCACHE_PRELOCK_SCT_SIZE_L1_CACHE_PRELOCK_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_CACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_L1_DCACHE_PRELOCK_SCT_SIZE_L1_CACHE_PRELOCK_SCT0_SIZE_Msk = 0x3fff + // Position of L1_CACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_DCACHE_PRELOCK_SCT_SIZE_L1_CACHE_PRELOCK_SCT1_SIZE_Pos = 0x10 + // Bit mask of L1_CACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_L1_DCACHE_PRELOCK_SCT_SIZE_L1_CACHE_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000 + + // CACHE_LOCK_CTRL: Lock-class (manual lock) operation control register + // Position of CACHE_LOCK_ENA field. + EXTMEM_CACHE_LOCK_CTRL_CACHE_LOCK_ENA_Pos = 0x0 + // Bit mask of CACHE_LOCK_ENA field. + EXTMEM_CACHE_LOCK_CTRL_CACHE_LOCK_ENA_Msk = 0x1 + // Bit CACHE_LOCK_ENA. + EXTMEM_CACHE_LOCK_CTRL_CACHE_LOCK_ENA = 0x1 + // Position of CACHE_UNLOCK_ENA field. + EXTMEM_CACHE_LOCK_CTRL_CACHE_UNLOCK_ENA_Pos = 0x1 + // Bit mask of CACHE_UNLOCK_ENA field. + EXTMEM_CACHE_LOCK_CTRL_CACHE_UNLOCK_ENA_Msk = 0x2 + // Bit CACHE_UNLOCK_ENA. + EXTMEM_CACHE_LOCK_CTRL_CACHE_UNLOCK_ENA = 0x2 + // Position of CACHE_LOCK_DONE field. + EXTMEM_CACHE_LOCK_CTRL_CACHE_LOCK_DONE_Pos = 0x2 + // Bit mask of CACHE_LOCK_DONE field. + EXTMEM_CACHE_LOCK_CTRL_CACHE_LOCK_DONE_Msk = 0x4 + // Bit CACHE_LOCK_DONE. + EXTMEM_CACHE_LOCK_CTRL_CACHE_LOCK_DONE = 0x4 + // Position of CACHE_LOCK_RGID field. + EXTMEM_CACHE_LOCK_CTRL_CACHE_LOCK_RGID_Pos = 0x3 + // Bit mask of CACHE_LOCK_RGID field. + EXTMEM_CACHE_LOCK_CTRL_CACHE_LOCK_RGID_Msk = 0x78 + + // CACHE_LOCK_MAP: Lock (manual lock) map configure register + // Position of CACHE_LOCK_MAP field. + EXTMEM_CACHE_LOCK_MAP_CACHE_LOCK_MAP_Pos = 0x0 + // Bit mask of CACHE_LOCK_MAP field. + EXTMEM_CACHE_LOCK_MAP_CACHE_LOCK_MAP_Msk = 0x3f + + // CACHE_LOCK_ADDR: Lock (manual lock) address configure register + // Position of CACHE_LOCK_ADDR field. + EXTMEM_CACHE_LOCK_ADDR_CACHE_LOCK_ADDR_Pos = 0x0 + // Bit mask of CACHE_LOCK_ADDR field. + EXTMEM_CACHE_LOCK_ADDR_CACHE_LOCK_ADDR_Msk = 0xffffffff + + // CACHE_LOCK_SIZE: Lock (manual lock) size configure register + // Position of CACHE_LOCK_SIZE field. + EXTMEM_CACHE_LOCK_SIZE_CACHE_LOCK_SIZE_Pos = 0x0 + // Bit mask of CACHE_LOCK_SIZE field. + EXTMEM_CACHE_LOCK_SIZE_CACHE_LOCK_SIZE_Msk = 0xffff + + // CACHE_SYNC_CTRL: Sync-class operation control register + // Position of CACHE_INVALIDATE_ENA field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_INVALIDATE_ENA_Pos = 0x0 + // Bit mask of CACHE_INVALIDATE_ENA field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_INVALIDATE_ENA_Msk = 0x1 + // Bit CACHE_INVALIDATE_ENA. + EXTMEM_CACHE_SYNC_CTRL_CACHE_INVALIDATE_ENA = 0x1 + // Position of CACHE_CLEAN_ENA field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_CLEAN_ENA_Pos = 0x1 + // Bit mask of CACHE_CLEAN_ENA field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_CLEAN_ENA_Msk = 0x2 + // Bit CACHE_CLEAN_ENA. + EXTMEM_CACHE_SYNC_CTRL_CACHE_CLEAN_ENA = 0x2 + // Position of CACHE_WRITEBACK_ENA field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_WRITEBACK_ENA_Pos = 0x2 + // Bit mask of CACHE_WRITEBACK_ENA field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_WRITEBACK_ENA_Msk = 0x4 + // Bit CACHE_WRITEBACK_ENA. + EXTMEM_CACHE_SYNC_CTRL_CACHE_WRITEBACK_ENA = 0x4 + // Position of CACHE_WRITEBACK_INVALIDATE_ENA field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_WRITEBACK_INVALIDATE_ENA_Pos = 0x3 + // Bit mask of CACHE_WRITEBACK_INVALIDATE_ENA field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_WRITEBACK_INVALIDATE_ENA_Msk = 0x8 + // Bit CACHE_WRITEBACK_INVALIDATE_ENA. + EXTMEM_CACHE_SYNC_CTRL_CACHE_WRITEBACK_INVALIDATE_ENA = 0x8 + // Position of CACHE_SYNC_DONE field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_SYNC_DONE_Pos = 0x4 + // Bit mask of CACHE_SYNC_DONE field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_SYNC_DONE_Msk = 0x10 + // Bit CACHE_SYNC_DONE. + EXTMEM_CACHE_SYNC_CTRL_CACHE_SYNC_DONE = 0x10 + // Position of CACHE_SYNC_RGID field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_SYNC_RGID_Pos = 0x5 + // Bit mask of CACHE_SYNC_RGID field. + EXTMEM_CACHE_SYNC_CTRL_CACHE_SYNC_RGID_Msk = 0x1e0 + + // CACHE_SYNC_MAP: Sync map configure register + // Position of CACHE_SYNC_MAP field. + EXTMEM_CACHE_SYNC_MAP_CACHE_SYNC_MAP_Pos = 0x0 + // Bit mask of CACHE_SYNC_MAP field. + EXTMEM_CACHE_SYNC_MAP_CACHE_SYNC_MAP_Msk = 0x3f + + // CACHE_SYNC_ADDR: Sync address configure register + // Position of CACHE_SYNC_ADDR field. + EXTMEM_CACHE_SYNC_ADDR_CACHE_SYNC_ADDR_Pos = 0x0 + // Bit mask of CACHE_SYNC_ADDR field. + EXTMEM_CACHE_SYNC_ADDR_CACHE_SYNC_ADDR_Msk = 0xffffffff + + // CACHE_SYNC_SIZE: Sync size configure register + // Position of CACHE_SYNC_SIZE field. + EXTMEM_CACHE_SYNC_SIZE_CACHE_SYNC_SIZE_Pos = 0x0 + // Bit mask of CACHE_SYNC_SIZE field. + EXTMEM_CACHE_SYNC_SIZE_CACHE_SYNC_SIZE_Msk = 0xffffff + + // L1_ICACHE0_PRELOAD_CTRL: L1 instruction Cache 0 preload-operation control register + // Position of L1_ICACHE0_PRELOAD_ENA field. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE0_PRELOAD_ENA field. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA_Msk = 0x1 + // Bit L1_ICACHE0_PRELOAD_ENA. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA = 0x1 + // Position of L1_ICACHE0_PRELOAD_DONE field. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE_Pos = 0x1 + // Bit mask of L1_ICACHE0_PRELOAD_DONE field. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE_Msk = 0x2 + // Bit L1_ICACHE0_PRELOAD_DONE. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE = 0x2 + // Position of L1_ICACHE0_PRELOAD_ORDER field. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER_Pos = 0x2 + // Bit mask of L1_ICACHE0_PRELOAD_ORDER field. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER_Msk = 0x4 + // Bit L1_ICACHE0_PRELOAD_ORDER. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER = 0x4 + // Position of L1_ICACHE0_PRELOAD_RGID field. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID_Pos = 0x3 + // Bit mask of L1_ICACHE0_PRELOAD_RGID field. + EXTMEM_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID_Msk = 0x78 + + // L1_ICACHE0_PRELOAD_ADDR: L1 instruction Cache 0 preload address configure register + // Position of L1_ICACHE0_PRELOAD_ADDR field. + EXTMEM_L1_ICACHE0_PRELOAD_ADDR_L1_ICACHE0_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE0_PRELOAD_ADDR field. + EXTMEM_L1_ICACHE0_PRELOAD_ADDR_L1_ICACHE0_PRELOAD_ADDR_Msk = 0xffffffff + + // L1_ICACHE0_PRELOAD_SIZE: L1 instruction Cache 0 preload size configure register + // Position of L1_ICACHE0_PRELOAD_SIZE field. + EXTMEM_L1_ICACHE0_PRELOAD_SIZE_L1_ICACHE0_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE0_PRELOAD_SIZE field. + EXTMEM_L1_ICACHE0_PRELOAD_SIZE_L1_ICACHE0_PRELOAD_SIZE_Msk = 0x3fff + + // L1_ICACHE1_PRELOAD_CTRL: L1 instruction Cache 1 preload-operation control register + // Position of L1_ICACHE1_PRELOAD_ENA field. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE1_PRELOAD_ENA field. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA_Msk = 0x1 + // Bit L1_ICACHE1_PRELOAD_ENA. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA = 0x1 + // Position of L1_ICACHE1_PRELOAD_DONE field. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE_Pos = 0x1 + // Bit mask of L1_ICACHE1_PRELOAD_DONE field. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE_Msk = 0x2 + // Bit L1_ICACHE1_PRELOAD_DONE. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE = 0x2 + // Position of L1_ICACHE1_PRELOAD_ORDER field. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER_Pos = 0x2 + // Bit mask of L1_ICACHE1_PRELOAD_ORDER field. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER_Msk = 0x4 + // Bit L1_ICACHE1_PRELOAD_ORDER. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER = 0x4 + // Position of L1_ICACHE1_PRELOAD_RGID field. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID_Pos = 0x3 + // Bit mask of L1_ICACHE1_PRELOAD_RGID field. + EXTMEM_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID_Msk = 0x78 + + // L1_ICACHE1_PRELOAD_ADDR: L1 instruction Cache 1 preload address configure register + // Position of L1_ICACHE1_PRELOAD_ADDR field. + EXTMEM_L1_ICACHE1_PRELOAD_ADDR_L1_ICACHE1_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE1_PRELOAD_ADDR field. + EXTMEM_L1_ICACHE1_PRELOAD_ADDR_L1_ICACHE1_PRELOAD_ADDR_Msk = 0xffffffff + + // L1_ICACHE1_PRELOAD_SIZE: L1 instruction Cache 1 preload size configure register + // Position of L1_ICACHE1_PRELOAD_SIZE field. + EXTMEM_L1_ICACHE1_PRELOAD_SIZE_L1_ICACHE1_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE1_PRELOAD_SIZE field. + EXTMEM_L1_ICACHE1_PRELOAD_SIZE_L1_ICACHE1_PRELOAD_SIZE_Msk = 0x3fff + + // L1_ICACHE2_PRELOAD_CTRL: L1 instruction Cache 2 preload-operation control register + // Position of L1_ICACHE2_PRELOAD_ENA field. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE2_PRELOAD_ENA field. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA_Msk = 0x1 + // Bit L1_ICACHE2_PRELOAD_ENA. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA = 0x1 + // Position of L1_ICACHE2_PRELOAD_DONE field. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE_Pos = 0x1 + // Bit mask of L1_ICACHE2_PRELOAD_DONE field. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE_Msk = 0x2 + // Bit L1_ICACHE2_PRELOAD_DONE. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE = 0x2 + // Position of L1_ICACHE2_PRELOAD_ORDER field. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER_Pos = 0x2 + // Bit mask of L1_ICACHE2_PRELOAD_ORDER field. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER_Msk = 0x4 + // Bit L1_ICACHE2_PRELOAD_ORDER. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER = 0x4 + // Position of L1_ICACHE2_PRELOAD_RGID field. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID_Pos = 0x3 + // Bit mask of L1_ICACHE2_PRELOAD_RGID field. + EXTMEM_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID_Msk = 0x78 + + // L1_ICACHE2_PRELOAD_ADDR: L1 instruction Cache 2 preload address configure register + // Position of L1_ICACHE2_PRELOAD_ADDR field. + EXTMEM_L1_ICACHE2_PRELOAD_ADDR_L1_ICACHE2_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE2_PRELOAD_ADDR field. + EXTMEM_L1_ICACHE2_PRELOAD_ADDR_L1_ICACHE2_PRELOAD_ADDR_Msk = 0xffffffff + + // L1_ICACHE2_PRELOAD_SIZE: L1 instruction Cache 2 preload size configure register + // Position of L1_ICACHE2_PRELOAD_SIZE field. + EXTMEM_L1_ICACHE2_PRELOAD_SIZE_L1_ICACHE2_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE2_PRELOAD_SIZE field. + EXTMEM_L1_ICACHE2_PRELOAD_SIZE_L1_ICACHE2_PRELOAD_SIZE_Msk = 0x3fff + + // L1_ICACHE3_PRELOAD_CTRL: L1 instruction Cache 3 preload-operation control register + // Position of L1_ICACHE3_PRELOAD_ENA field. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE3_PRELOAD_ENA field. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA_Msk = 0x1 + // Bit L1_ICACHE3_PRELOAD_ENA. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA = 0x1 + // Position of L1_ICACHE3_PRELOAD_DONE field. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE_Pos = 0x1 + // Bit mask of L1_ICACHE3_PRELOAD_DONE field. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE_Msk = 0x2 + // Bit L1_ICACHE3_PRELOAD_DONE. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE = 0x2 + // Position of L1_ICACHE3_PRELOAD_ORDER field. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER_Pos = 0x2 + // Bit mask of L1_ICACHE3_PRELOAD_ORDER field. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER_Msk = 0x4 + // Bit L1_ICACHE3_PRELOAD_ORDER. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER = 0x4 + // Position of L1_ICACHE3_PRELOAD_RGID field. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID_Pos = 0x3 + // Bit mask of L1_ICACHE3_PRELOAD_RGID field. + EXTMEM_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID_Msk = 0x78 + + // L1_ICACHE3_PRELOAD_ADDR: L1 instruction Cache 3 preload address configure register + // Position of L1_ICACHE3_PRELOAD_ADDR field. + EXTMEM_L1_ICACHE3_PRELOAD_ADDR_L1_ICACHE3_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE3_PRELOAD_ADDR field. + EXTMEM_L1_ICACHE3_PRELOAD_ADDR_L1_ICACHE3_PRELOAD_ADDR_Msk = 0xffffffff + + // L1_ICACHE3_PRELOAD_SIZE: L1 instruction Cache 3 preload size configure register + // Position of L1_ICACHE3_PRELOAD_SIZE field. + EXTMEM_L1_ICACHE3_PRELOAD_SIZE_L1_ICACHE3_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE3_PRELOAD_SIZE field. + EXTMEM_L1_ICACHE3_PRELOAD_SIZE_L1_ICACHE3_PRELOAD_SIZE_Msk = 0x3fff + + // L1_CACHE_PRELOAD_CTRL: L1 Cache preload-operation control register + // Position of L1_CACHE_PRELOAD_ENA field. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ENA_Pos = 0x0 + // Bit mask of L1_CACHE_PRELOAD_ENA field. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ENA_Msk = 0x1 + // Bit L1_CACHE_PRELOAD_ENA. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ENA = 0x1 + // Position of L1_CACHE_PRELOAD_DONE field. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_DONE_Pos = 0x1 + // Bit mask of L1_CACHE_PRELOAD_DONE field. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_DONE_Msk = 0x2 + // Bit L1_CACHE_PRELOAD_DONE. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_DONE = 0x2 + // Position of L1_CACHE_PRELOAD_ORDER field. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ORDER_Pos = 0x2 + // Bit mask of L1_CACHE_PRELOAD_ORDER field. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ORDER_Msk = 0x4 + // Bit L1_CACHE_PRELOAD_ORDER. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_ORDER = 0x4 + // Position of L1_CACHE_PRELOAD_RGID field. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_RGID_Pos = 0x3 + // Bit mask of L1_CACHE_PRELOAD_RGID field. + EXTMEM_L1_CACHE_PRELOAD_CTRL_L1_CACHE_PRELOAD_RGID_Msk = 0x78 + + // L1_DCACHE_PRELOAD_ADDR: L1 Cache preload address configure register + // Position of L1_CACHE_PRELOAD_ADDR field. + EXTMEM_L1_DCACHE_PRELOAD_ADDR_L1_CACHE_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of L1_CACHE_PRELOAD_ADDR field. + EXTMEM_L1_DCACHE_PRELOAD_ADDR_L1_CACHE_PRELOAD_ADDR_Msk = 0xffffffff + + // L1_DCACHE_PRELOAD_SIZE: L1 Cache preload size configure register + // Position of L1_CACHE_PRELOAD_SIZE field. + EXTMEM_L1_DCACHE_PRELOAD_SIZE_L1_CACHE_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of L1_CACHE_PRELOAD_SIZE field. + EXTMEM_L1_DCACHE_PRELOAD_SIZE_L1_CACHE_PRELOAD_SIZE_Msk = 0x3fff + + // L1_ICACHE0_AUTOLOAD_CTRL: L1 instruction Cache 0 autoload-operation control register + // Position of L1_ICACHE0_AUTOLOAD_ENA field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE0_AUTOLOAD_ENA field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA_Msk = 0x1 + // Bit L1_ICACHE0_AUTOLOAD_ENA. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA = 0x1 + // Position of L1_ICACHE0_AUTOLOAD_DONE field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE_Pos = 0x1 + // Bit mask of L1_ICACHE0_AUTOLOAD_DONE field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE_Msk = 0x2 + // Bit L1_ICACHE0_AUTOLOAD_DONE. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE = 0x2 + // Position of L1_ICACHE0_AUTOLOAD_ORDER field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER_Pos = 0x2 + // Bit mask of L1_ICACHE0_AUTOLOAD_ORDER field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER_Msk = 0x4 + // Bit L1_ICACHE0_AUTOLOAD_ORDER. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER = 0x4 + // Position of L1_ICACHE0_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_Pos = 0x3 + // Bit mask of L1_ICACHE0_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_Msk = 0x18 + // Position of L1_ICACHE0_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA_Pos = 0x8 + // Bit mask of L1_ICACHE0_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA_Msk = 0x100 + // Bit L1_ICACHE0_AUTOLOAD_SCT0_ENA. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA = 0x100 + // Position of L1_ICACHE0_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA_Pos = 0x9 + // Bit mask of L1_ICACHE0_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA_Msk = 0x200 + // Bit L1_ICACHE0_AUTOLOAD_SCT1_ENA. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA = 0x200 + // Position of L1_ICACHE0_AUTOLOAD_RGID field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID_Pos = 0xa + // Bit mask of L1_ICACHE0_AUTOLOAD_RGID field. + EXTMEM_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID_Msk = 0x3c00 + + // L1_ICACHE0_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 0 autoload section 0 address configure register + // Position of L1_ICACHE0_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE0_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // L1_ICACHE0_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 0 autoload section 0 size configure register + // Position of L1_ICACHE0_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE0_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff + + // L1_ICACHE0_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 0 autoload section 1 address configure register + // Position of L1_ICACHE0_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE0_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // L1_ICACHE0_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 0 autoload section 1 size configure register + // Position of L1_ICACHE0_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE0_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff + + // L1_ICACHE1_AUTOLOAD_CTRL: L1 instruction Cache 1 autoload-operation control register + // Position of L1_ICACHE1_AUTOLOAD_ENA field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE1_AUTOLOAD_ENA field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA_Msk = 0x1 + // Bit L1_ICACHE1_AUTOLOAD_ENA. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA = 0x1 + // Position of L1_ICACHE1_AUTOLOAD_DONE field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE_Pos = 0x1 + // Bit mask of L1_ICACHE1_AUTOLOAD_DONE field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE_Msk = 0x2 + // Bit L1_ICACHE1_AUTOLOAD_DONE. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE = 0x2 + // Position of L1_ICACHE1_AUTOLOAD_ORDER field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER_Pos = 0x2 + // Bit mask of L1_ICACHE1_AUTOLOAD_ORDER field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER_Msk = 0x4 + // Bit L1_ICACHE1_AUTOLOAD_ORDER. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER = 0x4 + // Position of L1_ICACHE1_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_Pos = 0x3 + // Bit mask of L1_ICACHE1_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_Msk = 0x18 + // Position of L1_ICACHE1_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA_Pos = 0x8 + // Bit mask of L1_ICACHE1_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA_Msk = 0x100 + // Bit L1_ICACHE1_AUTOLOAD_SCT0_ENA. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA = 0x100 + // Position of L1_ICACHE1_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA_Pos = 0x9 + // Bit mask of L1_ICACHE1_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA_Msk = 0x200 + // Bit L1_ICACHE1_AUTOLOAD_SCT1_ENA. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA = 0x200 + // Position of L1_ICACHE1_AUTOLOAD_RGID field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID_Pos = 0xa + // Bit mask of L1_ICACHE1_AUTOLOAD_RGID field. + EXTMEM_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID_Msk = 0x3c00 + + // L1_ICACHE1_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 1 autoload section 0 address configure register + // Position of L1_ICACHE1_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE1_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // L1_ICACHE1_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 1 autoload section 0 size configure register + // Position of L1_ICACHE1_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE1_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff + + // L1_ICACHE1_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 1 autoload section 1 address configure register + // Position of L1_ICACHE1_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE1_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // L1_ICACHE1_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 1 autoload section 1 size configure register + // Position of L1_ICACHE1_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE1_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff + + // L1_ICACHE2_AUTOLOAD_CTRL: L1 instruction Cache 2 autoload-operation control register + // Position of L1_ICACHE2_AUTOLOAD_ENA field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE2_AUTOLOAD_ENA field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA_Msk = 0x1 + // Bit L1_ICACHE2_AUTOLOAD_ENA. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA = 0x1 + // Position of L1_ICACHE2_AUTOLOAD_DONE field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE_Pos = 0x1 + // Bit mask of L1_ICACHE2_AUTOLOAD_DONE field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE_Msk = 0x2 + // Bit L1_ICACHE2_AUTOLOAD_DONE. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE = 0x2 + // Position of L1_ICACHE2_AUTOLOAD_ORDER field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER_Pos = 0x2 + // Bit mask of L1_ICACHE2_AUTOLOAD_ORDER field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER_Msk = 0x4 + // Bit L1_ICACHE2_AUTOLOAD_ORDER. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER = 0x4 + // Position of L1_ICACHE2_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_Pos = 0x3 + // Bit mask of L1_ICACHE2_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_Msk = 0x18 + // Position of L1_ICACHE2_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA_Pos = 0x8 + // Bit mask of L1_ICACHE2_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA_Msk = 0x100 + // Bit L1_ICACHE2_AUTOLOAD_SCT0_ENA. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA = 0x100 + // Position of L1_ICACHE2_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA_Pos = 0x9 + // Bit mask of L1_ICACHE2_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA_Msk = 0x200 + // Bit L1_ICACHE2_AUTOLOAD_SCT1_ENA. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA = 0x200 + // Position of L1_ICACHE2_AUTOLOAD_RGID field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID_Pos = 0xa + // Bit mask of L1_ICACHE2_AUTOLOAD_RGID field. + EXTMEM_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID_Msk = 0x3c00 + + // L1_ICACHE2_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 2 autoload section 0 address configure register + // Position of L1_ICACHE2_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE2_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // L1_ICACHE2_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 2 autoload section 0 size configure register + // Position of L1_ICACHE2_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE2_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff + + // L1_ICACHE2_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 2 autoload section 1 address configure register + // Position of L1_ICACHE2_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE2_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // L1_ICACHE2_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 2 autoload section 1 size configure register + // Position of L1_ICACHE2_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE2_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff + + // L1_ICACHE3_AUTOLOAD_CTRL: L1 instruction Cache 3 autoload-operation control register + // Position of L1_ICACHE3_AUTOLOAD_ENA field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE3_AUTOLOAD_ENA field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA_Msk = 0x1 + // Bit L1_ICACHE3_AUTOLOAD_ENA. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA = 0x1 + // Position of L1_ICACHE3_AUTOLOAD_DONE field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE_Pos = 0x1 + // Bit mask of L1_ICACHE3_AUTOLOAD_DONE field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE_Msk = 0x2 + // Bit L1_ICACHE3_AUTOLOAD_DONE. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE = 0x2 + // Position of L1_ICACHE3_AUTOLOAD_ORDER field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER_Pos = 0x2 + // Bit mask of L1_ICACHE3_AUTOLOAD_ORDER field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER_Msk = 0x4 + // Bit L1_ICACHE3_AUTOLOAD_ORDER. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER = 0x4 + // Position of L1_ICACHE3_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_Pos = 0x3 + // Bit mask of L1_ICACHE3_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_Msk = 0x18 + // Position of L1_ICACHE3_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA_Pos = 0x8 + // Bit mask of L1_ICACHE3_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA_Msk = 0x100 + // Bit L1_ICACHE3_AUTOLOAD_SCT0_ENA. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA = 0x100 + // Position of L1_ICACHE3_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA_Pos = 0x9 + // Bit mask of L1_ICACHE3_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA_Msk = 0x200 + // Bit L1_ICACHE3_AUTOLOAD_SCT1_ENA. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA = 0x200 + // Position of L1_ICACHE3_AUTOLOAD_RGID field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID_Pos = 0xa + // Bit mask of L1_ICACHE3_AUTOLOAD_RGID field. + EXTMEM_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID_Msk = 0x3c00 + + // L1_ICACHE3_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 3 autoload section 0 address configure register + // Position of L1_ICACHE3_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE3_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // L1_ICACHE3_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 3 autoload section 0 size configure register + // Position of L1_ICACHE3_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE3_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff + + // L1_ICACHE3_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 3 autoload section 1 address configure register + // Position of L1_ICACHE3_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE3_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // L1_ICACHE3_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 3 autoload section 1 size configure register + // Position of L1_ICACHE3_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of L1_ICACHE3_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff + + // L1_CACHE_AUTOLOAD_CTRL: L1 Cache autoload-operation control register + // Position of L1_CACHE_AUTOLOAD_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ENA_Pos = 0x0 + // Bit mask of L1_CACHE_AUTOLOAD_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ENA_Msk = 0x1 + // Bit L1_CACHE_AUTOLOAD_ENA. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ENA = 0x1 + // Position of L1_CACHE_AUTOLOAD_DONE field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_DONE_Pos = 0x1 + // Bit mask of L1_CACHE_AUTOLOAD_DONE field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_DONE_Msk = 0x2 + // Bit L1_CACHE_AUTOLOAD_DONE. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_DONE = 0x2 + // Position of L1_CACHE_AUTOLOAD_ORDER field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ORDER_Pos = 0x2 + // Bit mask of L1_CACHE_AUTOLOAD_ORDER field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ORDER_Msk = 0x4 + // Bit L1_CACHE_AUTOLOAD_ORDER. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_ORDER = 0x4 + // Position of L1_CACHE_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_TRIGGER_MODE_Pos = 0x3 + // Bit mask of L1_CACHE_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_TRIGGER_MODE_Msk = 0x18 + // Position of L1_CACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT0_ENA_Pos = 0x8 + // Bit mask of L1_CACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT0_ENA_Msk = 0x100 + // Bit L1_CACHE_AUTOLOAD_SCT0_ENA. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT0_ENA = 0x100 + // Position of L1_CACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT1_ENA_Pos = 0x9 + // Bit mask of L1_CACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT1_ENA_Msk = 0x200 + // Bit L1_CACHE_AUTOLOAD_SCT1_ENA. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT1_ENA = 0x200 + // Position of L1_CACHE_AUTOLOAD_SCT2_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT2_ENA_Pos = 0xa + // Bit mask of L1_CACHE_AUTOLOAD_SCT2_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT2_ENA_Msk = 0x400 + // Bit L1_CACHE_AUTOLOAD_SCT2_ENA. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT2_ENA = 0x400 + // Position of L1_CACHE_AUTOLOAD_SCT3_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT3_ENA_Pos = 0xb + // Bit mask of L1_CACHE_AUTOLOAD_SCT3_ENA field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT3_ENA_Msk = 0x800 + // Bit L1_CACHE_AUTOLOAD_SCT3_ENA. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_SCT3_ENA = 0x800 + // Position of L1_CACHE_AUTOLOAD_RGID field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_RGID_Pos = 0xc + // Bit mask of L1_CACHE_AUTOLOAD_RGID field. + EXTMEM_L1_CACHE_AUTOLOAD_CTRL_L1_CACHE_AUTOLOAD_RGID_Msk = 0xf000 + + // L1_CACHE_AUTOLOAD_SCT0_ADDR: L1 Cache autoload section 0 address configure register + // Position of L1_CACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_L1_CACHE_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of L1_CACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_L1_CACHE_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // L1_CACHE_AUTOLOAD_SCT0_SIZE: L1 Cache autoload section 0 size configure register + // Position of L1_CACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_L1_CACHE_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of L1_CACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_L1_CACHE_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff + + // L1_CACHE_AUTOLOAD_SCT1_ADDR: L1 Cache autoload section 1 address configure register + // Position of L1_CACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_L1_CACHE_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of L1_CACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_L1_CACHE_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // L1_CACHE_AUTOLOAD_SCT1_SIZE: L1 Cache autoload section 1 size configure register + // Position of L1_CACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_L1_CACHE_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of L1_CACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_L1_CACHE_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff + + // L1_CACHE_AUTOLOAD_SCT2_ADDR: L1 Cache autoload section 2 address configure register + // Position of L1_CACHE_AUTOLOAD_SCT2_ADDR field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT2_ADDR_L1_CACHE_AUTOLOAD_SCT2_ADDR_Pos = 0x0 + // Bit mask of L1_CACHE_AUTOLOAD_SCT2_ADDR field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT2_ADDR_L1_CACHE_AUTOLOAD_SCT2_ADDR_Msk = 0xffffffff + + // L1_CACHE_AUTOLOAD_SCT2_SIZE: L1 Cache autoload section 2 size configure register + // Position of L1_CACHE_AUTOLOAD_SCT2_SIZE field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT2_SIZE_L1_CACHE_AUTOLOAD_SCT2_SIZE_Pos = 0x0 + // Bit mask of L1_CACHE_AUTOLOAD_SCT2_SIZE field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT2_SIZE_L1_CACHE_AUTOLOAD_SCT2_SIZE_Msk = 0xfffffff + + // L1_CACHE_AUTOLOAD_SCT3_ADDR: L1 Cache autoload section 1 address configure register + // Position of L1_CACHE_AUTOLOAD_SCT3_ADDR field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT3_ADDR_L1_CACHE_AUTOLOAD_SCT3_ADDR_Pos = 0x0 + // Bit mask of L1_CACHE_AUTOLOAD_SCT3_ADDR field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT3_ADDR_L1_CACHE_AUTOLOAD_SCT3_ADDR_Msk = 0xffffffff + + // L1_CACHE_AUTOLOAD_SCT3_SIZE: L1 Cache autoload section 1 size configure register + // Position of L1_CACHE_AUTOLOAD_SCT3_SIZE field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT3_SIZE_L1_CACHE_AUTOLOAD_SCT3_SIZE_Pos = 0x0 + // Bit mask of L1_CACHE_AUTOLOAD_SCT3_SIZE field. + EXTMEM_L1_CACHE_AUTOLOAD_SCT3_SIZE_L1_CACHE_AUTOLOAD_SCT3_SIZE_Msk = 0xfffffff + + // L1_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register + // Position of L1_IBUS0_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA_Pos = 0x0 + // Bit mask of L1_IBUS0_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA_Msk = 0x1 + // Bit L1_IBUS0_OVF_INT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA = 0x1 + // Position of L1_IBUS1_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA_Pos = 0x1 + // Bit mask of L1_IBUS1_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA_Msk = 0x2 + // Bit L1_IBUS1_OVF_INT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA = 0x2 + // Position of L1_IBUS2_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA_Pos = 0x2 + // Bit mask of L1_IBUS2_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA_Msk = 0x4 + // Bit L1_IBUS2_OVF_INT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA = 0x4 + // Position of L1_IBUS3_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA_Pos = 0x3 + // Bit mask of L1_IBUS3_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA_Msk = 0x8 + // Bit L1_IBUS3_OVF_INT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA = 0x8 + // Position of L1_BUS0_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_BUS0_OVF_INT_ENA_Pos = 0x4 + // Bit mask of L1_BUS0_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_BUS0_OVF_INT_ENA_Msk = 0x10 + // Bit L1_BUS0_OVF_INT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_BUS0_OVF_INT_ENA = 0x10 + // Position of L1_BUS1_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_BUS1_OVF_INT_ENA_Pos = 0x5 + // Bit mask of L1_BUS1_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_BUS1_OVF_INT_ENA_Msk = 0x20 + // Bit L1_BUS1_OVF_INT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_BUS1_OVF_INT_ENA = 0x20 + // Position of L1_DBUS2_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA_Pos = 0x6 + // Bit mask of L1_DBUS2_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA_Msk = 0x40 + // Bit L1_DBUS2_OVF_INT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA = 0x40 + // Position of L1_DBUS3_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA_Pos = 0x7 + // Bit mask of L1_DBUS3_OVF_INT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA_Msk = 0x80 + // Bit L1_DBUS3_OVF_INT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA = 0x80 + + // L1_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register + // Position of L1_IBUS0_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR_Pos = 0x0 + // Bit mask of L1_IBUS0_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR_Msk = 0x1 + // Bit L1_IBUS0_OVF_INT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR = 0x1 + // Position of L1_IBUS1_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR_Pos = 0x1 + // Bit mask of L1_IBUS1_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR_Msk = 0x2 + // Bit L1_IBUS1_OVF_INT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR = 0x2 + // Position of L1_IBUS2_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR_Pos = 0x2 + // Bit mask of L1_IBUS2_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR_Msk = 0x4 + // Bit L1_IBUS2_OVF_INT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR = 0x4 + // Position of L1_IBUS3_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR_Pos = 0x3 + // Bit mask of L1_IBUS3_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR_Msk = 0x8 + // Bit L1_IBUS3_OVF_INT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR = 0x8 + // Position of L1_BUS0_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_BUS0_OVF_INT_CLR_Pos = 0x4 + // Bit mask of L1_BUS0_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_BUS0_OVF_INT_CLR_Msk = 0x10 + // Bit L1_BUS0_OVF_INT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_BUS0_OVF_INT_CLR = 0x10 + // Position of L1_BUS1_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_BUS1_OVF_INT_CLR_Pos = 0x5 + // Bit mask of L1_BUS1_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_BUS1_OVF_INT_CLR_Msk = 0x20 + // Bit L1_BUS1_OVF_INT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_BUS1_OVF_INT_CLR = 0x20 + // Position of L1_DBUS2_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR_Pos = 0x6 + // Bit mask of L1_DBUS2_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR_Msk = 0x40 + // Bit L1_DBUS2_OVF_INT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR = 0x40 + // Position of L1_DBUS3_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR_Pos = 0x7 + // Bit mask of L1_DBUS3_OVF_INT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR_Msk = 0x80 + // Bit L1_DBUS3_OVF_INT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR = 0x80 + + // L1_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register + // Position of L1_IBUS0_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW_Pos = 0x0 + // Bit mask of L1_IBUS0_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW_Msk = 0x1 + // Bit L1_IBUS0_OVF_INT_RAW. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW = 0x1 + // Position of L1_IBUS1_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW_Pos = 0x1 + // Bit mask of L1_IBUS1_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW_Msk = 0x2 + // Bit L1_IBUS1_OVF_INT_RAW. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW = 0x2 + // Position of L1_IBUS2_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW_Pos = 0x2 + // Bit mask of L1_IBUS2_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW_Msk = 0x4 + // Bit L1_IBUS2_OVF_INT_RAW. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW = 0x4 + // Position of L1_IBUS3_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW_Pos = 0x3 + // Bit mask of L1_IBUS3_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW_Msk = 0x8 + // Bit L1_IBUS3_OVF_INT_RAW. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW = 0x8 + // Position of L1_BUS0_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_BUS0_OVF_INT_RAW_Pos = 0x4 + // Bit mask of L1_BUS0_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_BUS0_OVF_INT_RAW_Msk = 0x10 + // Bit L1_BUS0_OVF_INT_RAW. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_BUS0_OVF_INT_RAW = 0x10 + // Position of L1_BUS1_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_BUS1_OVF_INT_RAW_Pos = 0x5 + // Bit mask of L1_BUS1_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_BUS1_OVF_INT_RAW_Msk = 0x20 + // Bit L1_BUS1_OVF_INT_RAW. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_BUS1_OVF_INT_RAW = 0x20 + // Position of L1_DBUS2_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW_Pos = 0x6 + // Bit mask of L1_DBUS2_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW_Msk = 0x40 + // Bit L1_DBUS2_OVF_INT_RAW. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW = 0x40 + // Position of L1_DBUS3_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW_Pos = 0x7 + // Bit mask of L1_DBUS3_OVF_INT_RAW field. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW_Msk = 0x80 + // Bit L1_DBUS3_OVF_INT_RAW. + EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW = 0x80 + + // L1_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register + // Position of L1_IBUS0_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST_Pos = 0x0 + // Bit mask of L1_IBUS0_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST_Msk = 0x1 + // Bit L1_IBUS0_OVF_INT_ST. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST = 0x1 + // Position of L1_IBUS1_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST_Pos = 0x1 + // Bit mask of L1_IBUS1_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST_Msk = 0x2 + // Bit L1_IBUS1_OVF_INT_ST. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST = 0x2 + // Position of L1_IBUS2_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST_Pos = 0x2 + // Bit mask of L1_IBUS2_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST_Msk = 0x4 + // Bit L1_IBUS2_OVF_INT_ST. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST = 0x4 + // Position of L1_IBUS3_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST_Pos = 0x3 + // Bit mask of L1_IBUS3_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST_Msk = 0x8 + // Bit L1_IBUS3_OVF_INT_ST. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST = 0x8 + // Position of L1_BUS0_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_BUS0_OVF_INT_ST_Pos = 0x4 + // Bit mask of L1_BUS0_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_BUS0_OVF_INT_ST_Msk = 0x10 + // Bit L1_BUS0_OVF_INT_ST. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_BUS0_OVF_INT_ST = 0x10 + // Position of L1_BUS1_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_BUS1_OVF_INT_ST_Pos = 0x5 + // Bit mask of L1_BUS1_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_BUS1_OVF_INT_ST_Msk = 0x20 + // Bit L1_BUS1_OVF_INT_ST. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_BUS1_OVF_INT_ST = 0x20 + // Position of L1_DBUS2_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST_Pos = 0x6 + // Bit mask of L1_DBUS2_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST_Msk = 0x40 + // Bit L1_DBUS2_OVF_INT_ST. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST = 0x40 + // Position of L1_DBUS3_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST_Pos = 0x7 + // Bit mask of L1_DBUS3_OVF_INT_ST field. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST_Msk = 0x80 + // Bit L1_DBUS3_OVF_INT_ST. + EXTMEM_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST = 0x80 + + // L1_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register + // Position of L1_ICACHE0_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE0_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA_Msk = 0x1 + // Bit L1_ICACHE0_FAIL_INT_ENA. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA = 0x1 + // Position of L1_ICACHE1_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA_Pos = 0x1 + // Bit mask of L1_ICACHE1_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA_Msk = 0x2 + // Bit L1_ICACHE1_FAIL_INT_ENA. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA = 0x2 + // Position of L1_ICACHE2_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA_Pos = 0x2 + // Bit mask of L1_ICACHE2_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA_Msk = 0x4 + // Bit L1_ICACHE2_FAIL_INT_ENA. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA = 0x4 + // Position of L1_ICACHE3_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA_Pos = 0x3 + // Bit mask of L1_ICACHE3_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA_Msk = 0x8 + // Bit L1_ICACHE3_FAIL_INT_ENA. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA = 0x8 + // Position of L1_CACHE_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_CACHE_FAIL_INT_ENA_Pos = 0x4 + // Bit mask of L1_CACHE_FAIL_INT_ENA field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_CACHE_FAIL_INT_ENA_Msk = 0x10 + // Bit L1_CACHE_FAIL_INT_ENA. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_L1_CACHE_FAIL_INT_ENA = 0x10 + + // L1_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register + // Position of L1_ICACHE0_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR_Pos = 0x0 + // Bit mask of L1_ICACHE0_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR_Msk = 0x1 + // Bit L1_ICACHE0_FAIL_INT_CLR. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR = 0x1 + // Position of L1_ICACHE1_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR_Pos = 0x1 + // Bit mask of L1_ICACHE1_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR_Msk = 0x2 + // Bit L1_ICACHE1_FAIL_INT_CLR. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR = 0x2 + // Position of L1_ICACHE2_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR_Pos = 0x2 + // Bit mask of L1_ICACHE2_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR_Msk = 0x4 + // Bit L1_ICACHE2_FAIL_INT_CLR. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR = 0x4 + // Position of L1_ICACHE3_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR_Pos = 0x3 + // Bit mask of L1_ICACHE3_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR_Msk = 0x8 + // Bit L1_ICACHE3_FAIL_INT_CLR. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR = 0x8 + // Position of L1_CACHE_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_CACHE_FAIL_INT_CLR_Pos = 0x4 + // Bit mask of L1_CACHE_FAIL_INT_CLR field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_CACHE_FAIL_INT_CLR_Msk = 0x10 + // Bit L1_CACHE_FAIL_INT_CLR. + EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_L1_CACHE_FAIL_INT_CLR = 0x10 + + // L1_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register + // Position of L1_ICACHE0_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW_Pos = 0x0 + // Bit mask of L1_ICACHE0_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW_Msk = 0x1 + // Bit L1_ICACHE0_FAIL_INT_RAW. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW = 0x1 + // Position of L1_ICACHE1_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW_Pos = 0x1 + // Bit mask of L1_ICACHE1_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW_Msk = 0x2 + // Bit L1_ICACHE1_FAIL_INT_RAW. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW = 0x2 + // Position of L1_ICACHE2_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW_Pos = 0x2 + // Bit mask of L1_ICACHE2_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW_Msk = 0x4 + // Bit L1_ICACHE2_FAIL_INT_RAW. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW = 0x4 + // Position of L1_ICACHE3_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW_Pos = 0x3 + // Bit mask of L1_ICACHE3_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW_Msk = 0x8 + // Bit L1_ICACHE3_FAIL_INT_RAW. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW = 0x8 + // Position of L1_CACHE_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_CACHE_FAIL_INT_RAW_Pos = 0x4 + // Bit mask of L1_CACHE_FAIL_INT_RAW field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_CACHE_FAIL_INT_RAW_Msk = 0x10 + // Bit L1_CACHE_FAIL_INT_RAW. + EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_L1_CACHE_FAIL_INT_RAW = 0x10 + + // L1_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register + // Position of L1_ICACHE0_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST_Pos = 0x0 + // Bit mask of L1_ICACHE0_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST_Msk = 0x1 + // Bit L1_ICACHE0_FAIL_INT_ST. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST = 0x1 + // Position of L1_ICACHE1_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST_Pos = 0x1 + // Bit mask of L1_ICACHE1_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST_Msk = 0x2 + // Bit L1_ICACHE1_FAIL_INT_ST. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST = 0x2 + // Position of L1_ICACHE2_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST_Pos = 0x2 + // Bit mask of L1_ICACHE2_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST_Msk = 0x4 + // Bit L1_ICACHE2_FAIL_INT_ST. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST = 0x4 + // Position of L1_ICACHE3_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST_Pos = 0x3 + // Bit mask of L1_ICACHE3_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST_Msk = 0x8 + // Bit L1_ICACHE3_FAIL_INT_ST. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST = 0x8 + // Position of L1_CACHE_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_CACHE_FAIL_INT_ST_Pos = 0x4 + // Bit mask of L1_CACHE_FAIL_INT_ST field. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_CACHE_FAIL_INT_ST_Msk = 0x10 + // Bit L1_CACHE_FAIL_INT_ST. + EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_L1_CACHE_FAIL_INT_ST = 0x10 + + // L1_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register + // Position of L1_IBUS0_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA_Pos = 0x0 + // Bit mask of L1_IBUS0_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA_Msk = 0x1 + // Bit L1_IBUS0_CNT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA = 0x1 + // Position of L1_IBUS1_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA_Pos = 0x1 + // Bit mask of L1_IBUS1_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA_Msk = 0x2 + // Bit L1_IBUS1_CNT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA = 0x2 + // Position of L1_IBUS2_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA_Pos = 0x2 + // Bit mask of L1_IBUS2_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA_Msk = 0x4 + // Bit L1_IBUS2_CNT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA = 0x4 + // Position of L1_IBUS3_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA_Pos = 0x3 + // Bit mask of L1_IBUS3_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA_Msk = 0x8 + // Bit L1_IBUS3_CNT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA = 0x8 + // Position of L1_BUS0_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_ENA_Pos = 0x4 + // Bit mask of L1_BUS0_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_ENA_Msk = 0x10 + // Bit L1_BUS0_CNT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_ENA = 0x10 + // Position of L1_BUS1_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_ENA_Pos = 0x5 + // Bit mask of L1_BUS1_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_ENA_Msk = 0x20 + // Bit L1_BUS1_CNT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_ENA = 0x20 + // Position of L1_DBUS2_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA_Pos = 0x6 + // Bit mask of L1_DBUS2_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA_Msk = 0x40 + // Bit L1_DBUS2_CNT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA = 0x40 + // Position of L1_DBUS3_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA_Pos = 0x7 + // Bit mask of L1_DBUS3_CNT_ENA field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA_Msk = 0x80 + // Bit L1_DBUS3_CNT_ENA. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA = 0x80 + // Position of L1_IBUS0_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR_Pos = 0x10 + // Bit mask of L1_IBUS0_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR_Msk = 0x10000 + // Bit L1_IBUS0_CNT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR = 0x10000 + // Position of L1_IBUS1_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR_Pos = 0x11 + // Bit mask of L1_IBUS1_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR_Msk = 0x20000 + // Bit L1_IBUS1_CNT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR = 0x20000 + // Position of L1_IBUS2_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR_Pos = 0x12 + // Bit mask of L1_IBUS2_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR_Msk = 0x40000 + // Bit L1_IBUS2_CNT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR = 0x40000 + // Position of L1_IBUS3_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR_Pos = 0x13 + // Bit mask of L1_IBUS3_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR_Msk = 0x80000 + // Bit L1_IBUS3_CNT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR = 0x80000 + // Position of L1_BUS0_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_CLR_Pos = 0x14 + // Bit mask of L1_BUS0_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_CLR_Msk = 0x100000 + // Bit L1_BUS0_CNT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS0_CNT_CLR = 0x100000 + // Position of L1_BUS1_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_CLR_Pos = 0x15 + // Bit mask of L1_BUS1_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_CLR_Msk = 0x200000 + // Bit L1_BUS1_CNT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_BUS1_CNT_CLR = 0x200000 + // Position of L1_DBUS2_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR_Pos = 0x16 + // Bit mask of L1_DBUS2_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR_Msk = 0x400000 + // Bit L1_DBUS2_CNT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR = 0x400000 + // Position of L1_DBUS3_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR_Pos = 0x17 + // Bit mask of L1_DBUS3_CNT_CLR field. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR_Msk = 0x800000 + // Bit L1_DBUS3_CNT_CLR. + EXTMEM_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR = 0x800000 + + // L1_IBUS0_ACS_HIT_CNT: L1-ICache bus0 Hit-Access Counter register + // Position of L1_IBUS0_HIT_CNT field. + EXTMEM_L1_IBUS0_ACS_HIT_CNT_L1_IBUS0_HIT_CNT_Pos = 0x0 + // Bit mask of L1_IBUS0_HIT_CNT field. + EXTMEM_L1_IBUS0_ACS_HIT_CNT_L1_IBUS0_HIT_CNT_Msk = 0xffffffff + + // L1_IBUS0_ACS_MISS_CNT: L1-ICache bus0 Miss-Access Counter register + // Position of L1_IBUS0_MISS_CNT field. + EXTMEM_L1_IBUS0_ACS_MISS_CNT_L1_IBUS0_MISS_CNT_Pos = 0x0 + // Bit mask of L1_IBUS0_MISS_CNT field. + EXTMEM_L1_IBUS0_ACS_MISS_CNT_L1_IBUS0_MISS_CNT_Msk = 0xffffffff + + // L1_IBUS0_ACS_CONFLICT_CNT: L1-ICache bus0 Conflict-Access Counter register + // Position of L1_IBUS0_CONFLICT_CNT field. + EXTMEM_L1_IBUS0_ACS_CONFLICT_CNT_L1_IBUS0_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L1_IBUS0_CONFLICT_CNT field. + EXTMEM_L1_IBUS0_ACS_CONFLICT_CNT_L1_IBUS0_CONFLICT_CNT_Msk = 0xffffffff + + // L1_IBUS0_ACS_NXTLVL_CNT: L1-ICache bus0 Next-Level-Access Counter register + // Position of L1_IBUS0_NXTLVL_CNT field. + EXTMEM_L1_IBUS0_ACS_NXTLVL_CNT_L1_IBUS0_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L1_IBUS0_NXTLVL_CNT field. + EXTMEM_L1_IBUS0_ACS_NXTLVL_CNT_L1_IBUS0_NXTLVL_CNT_Msk = 0xffffffff + + // L1_IBUS1_ACS_HIT_CNT: L1-ICache bus1 Hit-Access Counter register + // Position of L1_IBUS1_HIT_CNT field. + EXTMEM_L1_IBUS1_ACS_HIT_CNT_L1_IBUS1_HIT_CNT_Pos = 0x0 + // Bit mask of L1_IBUS1_HIT_CNT field. + EXTMEM_L1_IBUS1_ACS_HIT_CNT_L1_IBUS1_HIT_CNT_Msk = 0xffffffff + + // L1_IBUS1_ACS_MISS_CNT: L1-ICache bus1 Miss-Access Counter register + // Position of L1_IBUS1_MISS_CNT field. + EXTMEM_L1_IBUS1_ACS_MISS_CNT_L1_IBUS1_MISS_CNT_Pos = 0x0 + // Bit mask of L1_IBUS1_MISS_CNT field. + EXTMEM_L1_IBUS1_ACS_MISS_CNT_L1_IBUS1_MISS_CNT_Msk = 0xffffffff + + // L1_IBUS1_ACS_CONFLICT_CNT: L1-ICache bus1 Conflict-Access Counter register + // Position of L1_IBUS1_CONFLICT_CNT field. + EXTMEM_L1_IBUS1_ACS_CONFLICT_CNT_L1_IBUS1_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L1_IBUS1_CONFLICT_CNT field. + EXTMEM_L1_IBUS1_ACS_CONFLICT_CNT_L1_IBUS1_CONFLICT_CNT_Msk = 0xffffffff + + // L1_IBUS1_ACS_NXTLVL_CNT: L1-ICache bus1 Next-Level-Access Counter register + // Position of L1_IBUS1_NXTLVL_CNT field. + EXTMEM_L1_IBUS1_ACS_NXTLVL_CNT_L1_IBUS1_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L1_IBUS1_NXTLVL_CNT field. + EXTMEM_L1_IBUS1_ACS_NXTLVL_CNT_L1_IBUS1_NXTLVL_CNT_Msk = 0xffffffff + + // L1_IBUS2_ACS_HIT_CNT: L1-ICache bus2 Hit-Access Counter register + // Position of L1_IBUS2_HIT_CNT field. + EXTMEM_L1_IBUS2_ACS_HIT_CNT_L1_IBUS2_HIT_CNT_Pos = 0x0 + // Bit mask of L1_IBUS2_HIT_CNT field. + EXTMEM_L1_IBUS2_ACS_HIT_CNT_L1_IBUS2_HIT_CNT_Msk = 0xffffffff + + // L1_IBUS2_ACS_MISS_CNT: L1-ICache bus2 Miss-Access Counter register + // Position of L1_IBUS2_MISS_CNT field. + EXTMEM_L1_IBUS2_ACS_MISS_CNT_L1_IBUS2_MISS_CNT_Pos = 0x0 + // Bit mask of L1_IBUS2_MISS_CNT field. + EXTMEM_L1_IBUS2_ACS_MISS_CNT_L1_IBUS2_MISS_CNT_Msk = 0xffffffff + + // L1_IBUS2_ACS_CONFLICT_CNT: L1-ICache bus2 Conflict-Access Counter register + // Position of L1_IBUS2_CONFLICT_CNT field. + EXTMEM_L1_IBUS2_ACS_CONFLICT_CNT_L1_IBUS2_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L1_IBUS2_CONFLICT_CNT field. + EXTMEM_L1_IBUS2_ACS_CONFLICT_CNT_L1_IBUS2_CONFLICT_CNT_Msk = 0xffffffff + + // L1_IBUS2_ACS_NXTLVL_CNT: L1-ICache bus2 Next-Level-Access Counter register + // Position of L1_IBUS2_NXTLVL_CNT field. + EXTMEM_L1_IBUS2_ACS_NXTLVL_CNT_L1_IBUS2_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L1_IBUS2_NXTLVL_CNT field. + EXTMEM_L1_IBUS2_ACS_NXTLVL_CNT_L1_IBUS2_NXTLVL_CNT_Msk = 0xffffffff + + // L1_IBUS3_ACS_HIT_CNT: L1-ICache bus3 Hit-Access Counter register + // Position of L1_IBUS3_HIT_CNT field. + EXTMEM_L1_IBUS3_ACS_HIT_CNT_L1_IBUS3_HIT_CNT_Pos = 0x0 + // Bit mask of L1_IBUS3_HIT_CNT field. + EXTMEM_L1_IBUS3_ACS_HIT_CNT_L1_IBUS3_HIT_CNT_Msk = 0xffffffff + + // L1_IBUS3_ACS_MISS_CNT: L1-ICache bus3 Miss-Access Counter register + // Position of L1_IBUS3_MISS_CNT field. + EXTMEM_L1_IBUS3_ACS_MISS_CNT_L1_IBUS3_MISS_CNT_Pos = 0x0 + // Bit mask of L1_IBUS3_MISS_CNT field. + EXTMEM_L1_IBUS3_ACS_MISS_CNT_L1_IBUS3_MISS_CNT_Msk = 0xffffffff + + // L1_IBUS3_ACS_CONFLICT_CNT: L1-ICache bus3 Conflict-Access Counter register + // Position of L1_IBUS3_CONFLICT_CNT field. + EXTMEM_L1_IBUS3_ACS_CONFLICT_CNT_L1_IBUS3_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L1_IBUS3_CONFLICT_CNT field. + EXTMEM_L1_IBUS3_ACS_CONFLICT_CNT_L1_IBUS3_CONFLICT_CNT_Msk = 0xffffffff + + // L1_IBUS3_ACS_NXTLVL_CNT: L1-ICache bus3 Next-Level-Access Counter register + // Position of L1_IBUS3_NXTLVL_CNT field. + EXTMEM_L1_IBUS3_ACS_NXTLVL_CNT_L1_IBUS3_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L1_IBUS3_NXTLVL_CNT field. + EXTMEM_L1_IBUS3_ACS_NXTLVL_CNT_L1_IBUS3_NXTLVL_CNT_Msk = 0xffffffff + + // L1_BUS0_ACS_HIT_CNT: L1-Cache bus0 Hit-Access Counter register + // Position of L1_BUS0_HIT_CNT field. + EXTMEM_L1_BUS0_ACS_HIT_CNT_L1_BUS0_HIT_CNT_Pos = 0x0 + // Bit mask of L1_BUS0_HIT_CNT field. + EXTMEM_L1_BUS0_ACS_HIT_CNT_L1_BUS0_HIT_CNT_Msk = 0xffffffff + + // L1_BUS0_ACS_MISS_CNT: L1-Cache bus0 Miss-Access Counter register + // Position of L1_BUS0_MISS_CNT field. + EXTMEM_L1_BUS0_ACS_MISS_CNT_L1_BUS0_MISS_CNT_Pos = 0x0 + // Bit mask of L1_BUS0_MISS_CNT field. + EXTMEM_L1_BUS0_ACS_MISS_CNT_L1_BUS0_MISS_CNT_Msk = 0xffffffff + + // L1_BUS0_ACS_CONFLICT_CNT: L1-Cache bus0 Conflict-Access Counter register + // Position of L1_BUS0_CONFLICT_CNT field. + EXTMEM_L1_BUS0_ACS_CONFLICT_CNT_L1_BUS0_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L1_BUS0_CONFLICT_CNT field. + EXTMEM_L1_BUS0_ACS_CONFLICT_CNT_L1_BUS0_CONFLICT_CNT_Msk = 0xffffffff + + // L1_BUS0_ACS_NXTLVL_CNT: L1-Cache bus0 Next-Level-Access Counter register + // Position of L1_BUS0_NXTLVL_CNT field. + EXTMEM_L1_BUS0_ACS_NXTLVL_CNT_L1_BUS0_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L1_BUS0_NXTLVL_CNT field. + EXTMEM_L1_BUS0_ACS_NXTLVL_CNT_L1_BUS0_NXTLVL_CNT_Msk = 0xffffffff + + // L1_BUS1_ACS_HIT_CNT: L1-Cache bus1 Hit-Access Counter register + // Position of L1_BUS1_HIT_CNT field. + EXTMEM_L1_BUS1_ACS_HIT_CNT_L1_BUS1_HIT_CNT_Pos = 0x0 + // Bit mask of L1_BUS1_HIT_CNT field. + EXTMEM_L1_BUS1_ACS_HIT_CNT_L1_BUS1_HIT_CNT_Msk = 0xffffffff + + // L1_BUS1_ACS_MISS_CNT: L1-Cache bus1 Miss-Access Counter register + // Position of L1_BUS1_MISS_CNT field. + EXTMEM_L1_BUS1_ACS_MISS_CNT_L1_BUS1_MISS_CNT_Pos = 0x0 + // Bit mask of L1_BUS1_MISS_CNT field. + EXTMEM_L1_BUS1_ACS_MISS_CNT_L1_BUS1_MISS_CNT_Msk = 0xffffffff + + // L1_BUS1_ACS_CONFLICT_CNT: L1-Cache bus1 Conflict-Access Counter register + // Position of L1_BUS1_CONFLICT_CNT field. + EXTMEM_L1_BUS1_ACS_CONFLICT_CNT_L1_BUS1_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L1_BUS1_CONFLICT_CNT field. + EXTMEM_L1_BUS1_ACS_CONFLICT_CNT_L1_BUS1_CONFLICT_CNT_Msk = 0xffffffff + + // L1_BUS1_ACS_NXTLVL_CNT: L1-Cache bus1 Next-Level-Access Counter register + // Position of L1_BUS1_NXTLVL_CNT field. + EXTMEM_L1_BUS1_ACS_NXTLVL_CNT_L1_BUS1_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L1_BUS1_NXTLVL_CNT field. + EXTMEM_L1_BUS1_ACS_NXTLVL_CNT_L1_BUS1_NXTLVL_CNT_Msk = 0xffffffff + + // L1_DBUS2_ACS_HIT_CNT: L1-DCache bus2 Hit-Access Counter register + // Position of L1_DBUS2_HIT_CNT field. + EXTMEM_L1_DBUS2_ACS_HIT_CNT_L1_DBUS2_HIT_CNT_Pos = 0x0 + // Bit mask of L1_DBUS2_HIT_CNT field. + EXTMEM_L1_DBUS2_ACS_HIT_CNT_L1_DBUS2_HIT_CNT_Msk = 0xffffffff + + // L1_DBUS2_ACS_MISS_CNT: L1-DCache bus2 Miss-Access Counter register + // Position of L1_DBUS2_MISS_CNT field. + EXTMEM_L1_DBUS2_ACS_MISS_CNT_L1_DBUS2_MISS_CNT_Pos = 0x0 + // Bit mask of L1_DBUS2_MISS_CNT field. + EXTMEM_L1_DBUS2_ACS_MISS_CNT_L1_DBUS2_MISS_CNT_Msk = 0xffffffff + + // L1_DBUS2_ACS_CONFLICT_CNT: L1-DCache bus2 Conflict-Access Counter register + // Position of L1_DBUS2_CONFLICT_CNT field. + EXTMEM_L1_DBUS2_ACS_CONFLICT_CNT_L1_DBUS2_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L1_DBUS2_CONFLICT_CNT field. + EXTMEM_L1_DBUS2_ACS_CONFLICT_CNT_L1_DBUS2_CONFLICT_CNT_Msk = 0xffffffff + + // L1_DBUS2_ACS_NXTLVL_CNT: L1-DCache bus2 Next-Level-Access Counter register + // Position of L1_DBUS2_NXTLVL_CNT field. + EXTMEM_L1_DBUS2_ACS_NXTLVL_CNT_L1_DBUS2_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L1_DBUS2_NXTLVL_CNT field. + EXTMEM_L1_DBUS2_ACS_NXTLVL_CNT_L1_DBUS2_NXTLVL_CNT_Msk = 0xffffffff + + // L1_DBUS3_ACS_HIT_CNT: L1-DCache bus3 Hit-Access Counter register + // Position of L1_DBUS3_HIT_CNT field. + EXTMEM_L1_DBUS3_ACS_HIT_CNT_L1_DBUS3_HIT_CNT_Pos = 0x0 + // Bit mask of L1_DBUS3_HIT_CNT field. + EXTMEM_L1_DBUS3_ACS_HIT_CNT_L1_DBUS3_HIT_CNT_Msk = 0xffffffff + + // L1_DBUS3_ACS_MISS_CNT: L1-DCache bus3 Miss-Access Counter register + // Position of L1_DBUS3_MISS_CNT field. + EXTMEM_L1_DBUS3_ACS_MISS_CNT_L1_DBUS3_MISS_CNT_Pos = 0x0 + // Bit mask of L1_DBUS3_MISS_CNT field. + EXTMEM_L1_DBUS3_ACS_MISS_CNT_L1_DBUS3_MISS_CNT_Msk = 0xffffffff + + // L1_DBUS3_ACS_CONFLICT_CNT: L1-DCache bus3 Conflict-Access Counter register + // Position of L1_DBUS3_CONFLICT_CNT field. + EXTMEM_L1_DBUS3_ACS_CONFLICT_CNT_L1_DBUS3_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L1_DBUS3_CONFLICT_CNT field. + EXTMEM_L1_DBUS3_ACS_CONFLICT_CNT_L1_DBUS3_CONFLICT_CNT_Msk = 0xffffffff + + // L1_DBUS3_ACS_NXTLVL_CNT: L1-DCache bus3 Next-Level-Access Counter register + // Position of L1_DBUS3_NXTLVL_CNT field. + EXTMEM_L1_DBUS3_ACS_NXTLVL_CNT_L1_DBUS3_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L1_DBUS3_NXTLVL_CNT field. + EXTMEM_L1_DBUS3_ACS_NXTLVL_CNT_L1_DBUS3_NXTLVL_CNT_Msk = 0xffffffff + + // L1_ICACHE0_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register + // Position of L1_ICACHE0_FAIL_ID field. + EXTMEM_L1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID_Pos = 0x0 + // Bit mask of L1_ICACHE0_FAIL_ID field. + EXTMEM_L1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID_Msk = 0xffff + // Position of L1_ICACHE0_FAIL_ATTR field. + EXTMEM_L1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR_Pos = 0x10 + // Bit mask of L1_ICACHE0_FAIL_ATTR field. + EXTMEM_L1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR_Msk = 0xffff0000 + + // L1_ICACHE0_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register + // Position of L1_ICACHE0_FAIL_ADDR field. + EXTMEM_L1_ICACHE0_ACS_FAIL_ADDR_L1_ICACHE0_FAIL_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE0_FAIL_ADDR field. + EXTMEM_L1_ICACHE0_ACS_FAIL_ADDR_L1_ICACHE0_FAIL_ADDR_Msk = 0xffffffff + + // L1_ICACHE1_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register + // Position of L1_ICACHE1_FAIL_ID field. + EXTMEM_L1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID_Pos = 0x0 + // Bit mask of L1_ICACHE1_FAIL_ID field. + EXTMEM_L1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID_Msk = 0xffff + // Position of L1_ICACHE1_FAIL_ATTR field. + EXTMEM_L1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR_Pos = 0x10 + // Bit mask of L1_ICACHE1_FAIL_ATTR field. + EXTMEM_L1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR_Msk = 0xffff0000 + + // L1_ICACHE1_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register + // Position of L1_ICACHE1_FAIL_ADDR field. + EXTMEM_L1_ICACHE1_ACS_FAIL_ADDR_L1_ICACHE1_FAIL_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE1_FAIL_ADDR field. + EXTMEM_L1_ICACHE1_ACS_FAIL_ADDR_L1_ICACHE1_FAIL_ADDR_Msk = 0xffffffff + + // L1_ICACHE2_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register + // Position of L1_ICACHE2_FAIL_ID field. + EXTMEM_L1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID_Pos = 0x0 + // Bit mask of L1_ICACHE2_FAIL_ID field. + EXTMEM_L1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID_Msk = 0xffff + // Position of L1_ICACHE2_FAIL_ATTR field. + EXTMEM_L1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR_Pos = 0x10 + // Bit mask of L1_ICACHE2_FAIL_ATTR field. + EXTMEM_L1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR_Msk = 0xffff0000 + + // L1_ICACHE2_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register + // Position of L1_ICACHE2_FAIL_ADDR field. + EXTMEM_L1_ICACHE2_ACS_FAIL_ADDR_L1_ICACHE2_FAIL_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE2_FAIL_ADDR field. + EXTMEM_L1_ICACHE2_ACS_FAIL_ADDR_L1_ICACHE2_FAIL_ADDR_Msk = 0xffffffff + + // L1_ICACHE3_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register + // Position of L1_ICACHE3_FAIL_ID field. + EXTMEM_L1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID_Pos = 0x0 + // Bit mask of L1_ICACHE3_FAIL_ID field. + EXTMEM_L1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID_Msk = 0xffff + // Position of L1_ICACHE3_FAIL_ATTR field. + EXTMEM_L1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR_Pos = 0x10 + // Bit mask of L1_ICACHE3_FAIL_ATTR field. + EXTMEM_L1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR_Msk = 0xffff0000 + + // L1_ICACHE3_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register + // Position of L1_ICACHE3_FAIL_ADDR field. + EXTMEM_L1_ICACHE3_ACS_FAIL_ADDR_L1_ICACHE3_FAIL_ADDR_Pos = 0x0 + // Bit mask of L1_ICACHE3_FAIL_ADDR field. + EXTMEM_L1_ICACHE3_ACS_FAIL_ADDR_L1_ICACHE3_FAIL_ADDR_Msk = 0xffffffff + + // L1_CACHE_ACS_FAIL_ID_ATTR: L1-Cache Access Fail ID/attribution information register + // Position of L1_CACHE_FAIL_ID field. + EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_L1_CACHE_FAIL_ID_Pos = 0x0 + // Bit mask of L1_CACHE_FAIL_ID field. + EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_L1_CACHE_FAIL_ID_Msk = 0xffff + // Position of L1_CACHE_FAIL_ATTR field. + EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_L1_CACHE_FAIL_ATTR_Pos = 0x10 + // Bit mask of L1_CACHE_FAIL_ATTR field. + EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_L1_CACHE_FAIL_ATTR_Msk = 0xffff0000 + + // L1_DCACHE_ACS_FAIL_ADDR: L1-Cache Access Fail Address information register + // Position of L1_CACHE_FAIL_ADDR field. + EXTMEM_L1_DCACHE_ACS_FAIL_ADDR_L1_CACHE_FAIL_ADDR_Pos = 0x0 + // Bit mask of L1_CACHE_FAIL_ADDR field. + EXTMEM_L1_DCACHE_ACS_FAIL_ADDR_L1_CACHE_FAIL_ADDR_Msk = 0xffffffff + + // L1_CACHE_SYNC_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register + // Position of L1_ICACHE0_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA_Pos = 0x0 + // Bit mask of L1_ICACHE0_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA_Msk = 0x1 + // Bit L1_ICACHE0_PLD_DONE_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA = 0x1 + // Position of L1_ICACHE1_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA_Pos = 0x1 + // Bit mask of L1_ICACHE1_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA_Msk = 0x2 + // Bit L1_ICACHE1_PLD_DONE_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA = 0x2 + // Position of L1_ICACHE2_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA_Pos = 0x2 + // Bit mask of L1_ICACHE2_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA_Msk = 0x4 + // Bit L1_ICACHE2_PLD_DONE_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA = 0x4 + // Position of L1_ICACHE3_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA_Pos = 0x3 + // Bit mask of L1_ICACHE3_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA_Msk = 0x8 + // Bit L1_ICACHE3_PLD_DONE_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA = 0x8 + // Position of L1_CACHE_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_DONE_INT_ENA_Pos = 0x4 + // Bit mask of L1_CACHE_PLD_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_DONE_INT_ENA_Msk = 0x10 + // Bit L1_CACHE_PLD_DONE_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_DONE_INT_ENA = 0x10 + // Position of CACHE_SYNC_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_DONE_INT_ENA_Pos = 0x6 + // Bit mask of CACHE_SYNC_DONE_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_DONE_INT_ENA_Msk = 0x40 + // Bit CACHE_SYNC_DONE_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_DONE_INT_ENA = 0x40 + // Position of L1_ICACHE0_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA_Pos = 0x7 + // Bit mask of L1_ICACHE0_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA_Msk = 0x80 + // Bit L1_ICACHE0_PLD_ERR_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA = 0x80 + // Position of L1_ICACHE1_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA_Pos = 0x8 + // Bit mask of L1_ICACHE1_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA_Msk = 0x100 + // Bit L1_ICACHE1_PLD_ERR_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA = 0x100 + // Position of L1_ICACHE2_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA_Pos = 0x9 + // Bit mask of L1_ICACHE2_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA_Msk = 0x200 + // Bit L1_ICACHE2_PLD_ERR_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA = 0x200 + // Position of L1_ICACHE3_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA_Pos = 0xa + // Bit mask of L1_ICACHE3_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA_Msk = 0x400 + // Bit L1_ICACHE3_PLD_ERR_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA = 0x400 + // Position of L1_CACHE_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_ERR_INT_ENA_Pos = 0xb + // Bit mask of L1_CACHE_PLD_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_ERR_INT_ENA_Msk = 0x800 + // Bit L1_CACHE_PLD_ERR_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_L1_CACHE_PLD_ERR_INT_ENA = 0x800 + // Position of CACHE_SYNC_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_ERR_INT_ENA_Pos = 0xd + // Bit mask of CACHE_SYNC_ERR_INT_ENA field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_ERR_INT_ENA_Msk = 0x2000 + // Bit CACHE_SYNC_ERR_INT_ENA. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_CACHE_SYNC_ERR_INT_ENA = 0x2000 + + // L1_CACHE_SYNC_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register + // Position of L1_ICACHE0_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR_Pos = 0x0 + // Bit mask of L1_ICACHE0_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR_Msk = 0x1 + // Bit L1_ICACHE0_PLD_DONE_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR = 0x1 + // Position of L1_ICACHE1_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR_Pos = 0x1 + // Bit mask of L1_ICACHE1_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR_Msk = 0x2 + // Bit L1_ICACHE1_PLD_DONE_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR = 0x2 + // Position of L1_ICACHE2_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR_Pos = 0x2 + // Bit mask of L1_ICACHE2_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR_Msk = 0x4 + // Bit L1_ICACHE2_PLD_DONE_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR = 0x4 + // Position of L1_ICACHE3_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR_Pos = 0x3 + // Bit mask of L1_ICACHE3_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR_Msk = 0x8 + // Bit L1_ICACHE3_PLD_DONE_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR = 0x8 + // Position of L1_CACHE_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_DONE_INT_CLR_Pos = 0x4 + // Bit mask of L1_CACHE_PLD_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_DONE_INT_CLR_Msk = 0x10 + // Bit L1_CACHE_PLD_DONE_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_DONE_INT_CLR = 0x10 + // Position of CACHE_SYNC_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_DONE_INT_CLR_Pos = 0x6 + // Bit mask of CACHE_SYNC_DONE_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_DONE_INT_CLR_Msk = 0x40 + // Bit CACHE_SYNC_DONE_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_DONE_INT_CLR = 0x40 + // Position of L1_ICACHE0_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR_Pos = 0x7 + // Bit mask of L1_ICACHE0_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR_Msk = 0x80 + // Bit L1_ICACHE0_PLD_ERR_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR = 0x80 + // Position of L1_ICACHE1_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR_Pos = 0x8 + // Bit mask of L1_ICACHE1_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR_Msk = 0x100 + // Bit L1_ICACHE1_PLD_ERR_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR = 0x100 + // Position of L1_ICACHE2_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR_Pos = 0x9 + // Bit mask of L1_ICACHE2_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR_Msk = 0x200 + // Bit L1_ICACHE2_PLD_ERR_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR = 0x200 + // Position of L1_ICACHE3_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR_Pos = 0xa + // Bit mask of L1_ICACHE3_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR_Msk = 0x400 + // Bit L1_ICACHE3_PLD_ERR_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR = 0x400 + // Position of L1_CACHE_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_ERR_INT_CLR_Pos = 0xb + // Bit mask of L1_CACHE_PLD_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_ERR_INT_CLR_Msk = 0x800 + // Bit L1_CACHE_PLD_ERR_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_L1_CACHE_PLD_ERR_INT_CLR = 0x800 + // Position of CACHE_SYNC_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_ERR_INT_CLR_Pos = 0xd + // Bit mask of CACHE_SYNC_ERR_INT_CLR field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_ERR_INT_CLR_Msk = 0x2000 + // Bit CACHE_SYNC_ERR_INT_CLR. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_CACHE_SYNC_ERR_INT_CLR = 0x2000 + + // L1_CACHE_SYNC_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register + // Position of L1_ICACHE0_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW_Pos = 0x0 + // Bit mask of L1_ICACHE0_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW_Msk = 0x1 + // Bit L1_ICACHE0_PLD_DONE_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW = 0x1 + // Position of L1_ICACHE1_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW_Pos = 0x1 + // Bit mask of L1_ICACHE1_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW_Msk = 0x2 + // Bit L1_ICACHE1_PLD_DONE_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW = 0x2 + // Position of L1_ICACHE2_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW_Pos = 0x2 + // Bit mask of L1_ICACHE2_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW_Msk = 0x4 + // Bit L1_ICACHE2_PLD_DONE_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW = 0x4 + // Position of L1_ICACHE3_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW_Pos = 0x3 + // Bit mask of L1_ICACHE3_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW_Msk = 0x8 + // Bit L1_ICACHE3_PLD_DONE_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW = 0x8 + // Position of L1_CACHE_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_DONE_INT_RAW_Pos = 0x4 + // Bit mask of L1_CACHE_PLD_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_DONE_INT_RAW_Msk = 0x10 + // Bit L1_CACHE_PLD_DONE_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_DONE_INT_RAW = 0x10 + // Position of CACHE_SYNC_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_DONE_INT_RAW_Pos = 0x6 + // Bit mask of CACHE_SYNC_DONE_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_DONE_INT_RAW_Msk = 0x40 + // Bit CACHE_SYNC_DONE_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_DONE_INT_RAW = 0x40 + // Position of L1_ICACHE0_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW_Pos = 0x7 + // Bit mask of L1_ICACHE0_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW_Msk = 0x80 + // Bit L1_ICACHE0_PLD_ERR_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW = 0x80 + // Position of L1_ICACHE1_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW_Pos = 0x8 + // Bit mask of L1_ICACHE1_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW_Msk = 0x100 + // Bit L1_ICACHE1_PLD_ERR_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW = 0x100 + // Position of L1_ICACHE2_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW_Pos = 0x9 + // Bit mask of L1_ICACHE2_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW_Msk = 0x200 + // Bit L1_ICACHE2_PLD_ERR_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW = 0x200 + // Position of L1_ICACHE3_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW_Pos = 0xa + // Bit mask of L1_ICACHE3_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW_Msk = 0x400 + // Bit L1_ICACHE3_PLD_ERR_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW = 0x400 + // Position of L1_CACHE_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_ERR_INT_RAW_Pos = 0xb + // Bit mask of L1_CACHE_PLD_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_ERR_INT_RAW_Msk = 0x800 + // Bit L1_CACHE_PLD_ERR_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_L1_CACHE_PLD_ERR_INT_RAW = 0x800 + // Position of CACHE_SYNC_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_ERR_INT_RAW_Pos = 0xd + // Bit mask of CACHE_SYNC_ERR_INT_RAW field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_ERR_INT_RAW_Msk = 0x2000 + // Bit CACHE_SYNC_ERR_INT_RAW. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_CACHE_SYNC_ERR_INT_RAW = 0x2000 + + // L1_CACHE_SYNC_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register + // Position of L1_ICACHE0_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST_Pos = 0x0 + // Bit mask of L1_ICACHE0_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST_Msk = 0x1 + // Bit L1_ICACHE0_PLD_DONE_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST = 0x1 + // Position of L1_ICACHE1_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST_Pos = 0x1 + // Bit mask of L1_ICACHE1_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST_Msk = 0x2 + // Bit L1_ICACHE1_PLD_DONE_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST = 0x2 + // Position of L1_ICACHE2_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST_Pos = 0x2 + // Bit mask of L1_ICACHE2_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST_Msk = 0x4 + // Bit L1_ICACHE2_PLD_DONE_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST = 0x4 + // Position of L1_ICACHE3_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST_Pos = 0x3 + // Bit mask of L1_ICACHE3_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST_Msk = 0x8 + // Bit L1_ICACHE3_PLD_DONE_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST = 0x8 + // Position of L1_CACHE_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_DONE_INT_ST_Pos = 0x4 + // Bit mask of L1_CACHE_PLD_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_DONE_INT_ST_Msk = 0x10 + // Bit L1_CACHE_PLD_DONE_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_DONE_INT_ST = 0x10 + // Position of CACHE_SYNC_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_DONE_INT_ST_Pos = 0x6 + // Bit mask of CACHE_SYNC_DONE_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_DONE_INT_ST_Msk = 0x40 + // Bit CACHE_SYNC_DONE_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_DONE_INT_ST = 0x40 + // Position of L1_ICACHE0_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST_Pos = 0x7 + // Bit mask of L1_ICACHE0_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST_Msk = 0x80 + // Bit L1_ICACHE0_PLD_ERR_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST = 0x80 + // Position of L1_ICACHE1_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST_Pos = 0x8 + // Bit mask of L1_ICACHE1_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST_Msk = 0x100 + // Bit L1_ICACHE1_PLD_ERR_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST = 0x100 + // Position of L1_ICACHE2_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST_Pos = 0x9 + // Bit mask of L1_ICACHE2_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST_Msk = 0x200 + // Bit L1_ICACHE2_PLD_ERR_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST = 0x200 + // Position of L1_ICACHE3_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST_Pos = 0xa + // Bit mask of L1_ICACHE3_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST_Msk = 0x400 + // Bit L1_ICACHE3_PLD_ERR_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST = 0x400 + // Position of L1_CACHE_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_ERR_INT_ST_Pos = 0xb + // Bit mask of L1_CACHE_PLD_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_ERR_INT_ST_Msk = 0x800 + // Bit L1_CACHE_PLD_ERR_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_L1_CACHE_PLD_ERR_INT_ST = 0x800 + // Position of CACHE_SYNC_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_ERR_INT_ST_Pos = 0xd + // Bit mask of CACHE_SYNC_ERR_INT_ST field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_ERR_INT_ST_Msk = 0x2000 + // Bit CACHE_SYNC_ERR_INT_ST. + EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_CACHE_SYNC_ERR_INT_ST = 0x2000 + + // L1_CACHE_SYNC_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register + // Position of L1_ICACHE0_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE_Pos = 0x0 + // Bit mask of L1_ICACHE0_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE_Msk = 0x3 + // Position of L1_ICACHE1_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE_Pos = 0x2 + // Bit mask of L1_ICACHE1_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE_Msk = 0xc + // Position of L1_ICACHE2_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE_Pos = 0x4 + // Bit mask of L1_ICACHE2_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE_Msk = 0x30 + // Position of L1_ICACHE3_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE_Pos = 0x6 + // Bit mask of L1_ICACHE3_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE_Msk = 0xc0 + // Position of L1_CACHE_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_CACHE_PLD_ERR_CODE_Pos = 0x8 + // Bit mask of L1_CACHE_PLD_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_L1_CACHE_PLD_ERR_CODE_Msk = 0x300 + // Position of CACHE_SYNC_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_CACHE_SYNC_ERR_CODE_Pos = 0xc + // Bit mask of CACHE_SYNC_ERR_CODE field. + EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_CACHE_SYNC_ERR_CODE_Msk = 0x3000 + + // L1_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register + // Position of L1_ICACHE0_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST_Pos = 0x0 + // Bit mask of L1_ICACHE0_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST_Msk = 0x1 + // Bit L1_ICACHE0_SYNC_RST. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST = 0x1 + // Position of L1_ICACHE1_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST_Pos = 0x1 + // Bit mask of L1_ICACHE1_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST_Msk = 0x2 + // Bit L1_ICACHE1_SYNC_RST. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST = 0x2 + // Position of L1_ICACHE2_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST_Pos = 0x2 + // Bit mask of L1_ICACHE2_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST_Msk = 0x4 + // Bit L1_ICACHE2_SYNC_RST. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST = 0x4 + // Position of L1_ICACHE3_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST_Pos = 0x3 + // Bit mask of L1_ICACHE3_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST_Msk = 0x8 + // Bit L1_ICACHE3_SYNC_RST. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST = 0x8 + // Position of L1_CACHE_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_CACHE_SYNC_RST_Pos = 0x4 + // Bit mask of L1_CACHE_SYNC_RST field. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_CACHE_SYNC_RST_Msk = 0x10 + // Bit L1_CACHE_SYNC_RST. + EXTMEM_L1_CACHE_SYNC_RST_CTRL_L1_CACHE_SYNC_RST = 0x10 + + // L1_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register + // Position of L1_ICACHE0_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST_Pos = 0x0 + // Bit mask of L1_ICACHE0_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST_Msk = 0x1 + // Bit L1_ICACHE0_PLD_RST. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST = 0x1 + // Position of L1_ICACHE1_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST_Pos = 0x1 + // Bit mask of L1_ICACHE1_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST_Msk = 0x2 + // Bit L1_ICACHE1_PLD_RST. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST = 0x2 + // Position of L1_ICACHE2_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST_Pos = 0x2 + // Bit mask of L1_ICACHE2_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST_Msk = 0x4 + // Bit L1_ICACHE2_PLD_RST. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST = 0x4 + // Position of L1_ICACHE3_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST_Pos = 0x3 + // Bit mask of L1_ICACHE3_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST_Msk = 0x8 + // Bit L1_ICACHE3_PLD_RST. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST = 0x8 + // Position of L1_CACHE_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_CACHE_PLD_RST_Pos = 0x4 + // Bit mask of L1_CACHE_PLD_RST field. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_CACHE_PLD_RST_Msk = 0x10 + // Bit L1_CACHE_PLD_RST. + EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_L1_CACHE_PLD_RST = 0x10 + + // L1_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register + // Position of L1_ICACHE0_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR_Pos = 0x0 + // Bit mask of L1_ICACHE0_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR_Msk = 0x1 + // Bit L1_ICACHE0_ALD_BUF_CLR. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR = 0x1 + // Position of L1_ICACHE1_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR_Pos = 0x1 + // Bit mask of L1_ICACHE1_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR_Msk = 0x2 + // Bit L1_ICACHE1_ALD_BUF_CLR. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR = 0x2 + // Position of L1_ICACHE2_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR_Pos = 0x2 + // Bit mask of L1_ICACHE2_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR_Msk = 0x4 + // Bit L1_ICACHE2_ALD_BUF_CLR. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR = 0x4 + // Position of L1_ICACHE3_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR_Pos = 0x3 + // Bit mask of L1_ICACHE3_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR_Msk = 0x8 + // Bit L1_ICACHE3_ALD_BUF_CLR. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR = 0x8 + // Position of L1_CACHE_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_CACHE_ALD_BUF_CLR_Pos = 0x4 + // Bit mask of L1_CACHE_ALD_BUF_CLR field. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_CACHE_ALD_BUF_CLR_Msk = 0x10 + // Bit L1_CACHE_ALD_BUF_CLR. + EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_CACHE_ALD_BUF_CLR = 0x10 + + // L1_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers + // Position of L1_ICACHE0_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR_Pos = 0x0 + // Bit mask of L1_ICACHE0_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR_Msk = 0x1 + // Bit L1_ICACHE0_UNALLOC_CLR. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR = 0x1 + // Position of L1_ICACHE1_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR_Pos = 0x1 + // Bit mask of L1_ICACHE1_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR_Msk = 0x2 + // Bit L1_ICACHE1_UNALLOC_CLR. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR = 0x2 + // Position of L1_ICACHE2_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR_Pos = 0x2 + // Bit mask of L1_ICACHE2_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR_Msk = 0x4 + // Bit L1_ICACHE2_UNALLOC_CLR. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR = 0x4 + // Position of L1_ICACHE3_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR_Pos = 0x3 + // Bit mask of L1_ICACHE3_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR_Msk = 0x8 + // Bit L1_ICACHE3_UNALLOC_CLR. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR = 0x8 + // Position of L1_CACHE_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_CACHE_UNALLOC_CLR_Pos = 0x4 + // Bit mask of L1_CACHE_UNALLOC_CLR field. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_CACHE_UNALLOC_CLR_Msk = 0x10 + // Bit L1_CACHE_UNALLOC_CLR. + EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_L1_CACHE_UNALLOC_CLR = 0x10 + + // L1_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register + // Position of L1_ICACHE0_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT_Pos = 0x0 + // Bit mask of L1_ICACHE0_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT_Msk = 0x1 + // Bit L1_ICACHE0_TAG_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT = 0x1 + // Position of L1_ICACHE1_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT_Pos = 0x1 + // Bit mask of L1_ICACHE1_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT_Msk = 0x2 + // Bit L1_ICACHE1_TAG_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT = 0x2 + // Position of L1_ICACHE2_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT_Pos = 0x2 + // Bit mask of L1_ICACHE2_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT_Msk = 0x4 + // Bit L1_ICACHE2_TAG_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT = 0x4 + // Position of L1_ICACHE3_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT_Pos = 0x3 + // Bit mask of L1_ICACHE3_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT_Msk = 0x8 + // Bit L1_ICACHE3_TAG_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT = 0x8 + // Position of L1_CACHE_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_CACHE_TAG_OBJECT_Pos = 0x4 + // Bit mask of L1_CACHE_TAG_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_CACHE_TAG_OBJECT_Msk = 0x10 + // Bit L1_CACHE_TAG_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_CACHE_TAG_OBJECT = 0x10 + // Position of L1_ICACHE0_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT_Pos = 0x6 + // Bit mask of L1_ICACHE0_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT_Msk = 0x40 + // Bit L1_ICACHE0_MEM_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT = 0x40 + // Position of L1_ICACHE1_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT_Pos = 0x7 + // Bit mask of L1_ICACHE1_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT_Msk = 0x80 + // Bit L1_ICACHE1_MEM_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT = 0x80 + // Position of L1_ICACHE2_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT_Pos = 0x8 + // Bit mask of L1_ICACHE2_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT_Msk = 0x100 + // Bit L1_ICACHE2_MEM_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT = 0x100 + // Position of L1_ICACHE3_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT_Pos = 0x9 + // Bit mask of L1_ICACHE3_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT_Msk = 0x200 + // Bit L1_ICACHE3_MEM_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT = 0x200 + // Position of L1_CACHE_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_CACHE_MEM_OBJECT_Pos = 0xa + // Bit mask of L1_CACHE_MEM_OBJECT field. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_CACHE_MEM_OBJECT_Msk = 0x400 + // Bit L1_CACHE_MEM_OBJECT. + EXTMEM_L1_CACHE_OBJECT_CTRL_L1_CACHE_MEM_OBJECT = 0x400 + + // L1_CACHE_WAY_OBJECT: Cache Tag and Data memory way register + // Position of L1_CACHE_WAY_OBJECT field. + EXTMEM_L1_CACHE_WAY_OBJECT_L1_CACHE_WAY_OBJECT_Pos = 0x0 + // Bit mask of L1_CACHE_WAY_OBJECT field. + EXTMEM_L1_CACHE_WAY_OBJECT_L1_CACHE_WAY_OBJECT_Msk = 0x7 + + // L1_CACHE_VADDR: Cache Vaddr register + // Position of L1_CACHE_VADDR field. + EXTMEM_L1_CACHE_VADDR_L1_CACHE_VADDR_Pos = 0x0 + // Bit mask of L1_CACHE_VADDR field. + EXTMEM_L1_CACHE_VADDR_L1_CACHE_VADDR_Msk = 0xffffffff + + // L1_CACHE_DEBUG_BUS: Cache Tag/data memory content register + // Position of L1_CACHE_DEBUG_BUS field. + EXTMEM_L1_CACHE_DEBUG_BUS_L1_CACHE_DEBUG_BUS_Pos = 0x0 + // Bit mask of L1_CACHE_DEBUG_BUS field. + EXTMEM_L1_CACHE_DEBUG_BUS_L1_CACHE_DEBUG_BUS_Msk = 0xffffffff + + // LEVEL_SPLIT0: USED TO SPLIT L1 CACHE AND L2 CACHE + // Position of LEVEL_SPLIT0 field. + EXTMEM_LEVEL_SPLIT0_LEVEL_SPLIT0_Pos = 0x0 + // Bit mask of LEVEL_SPLIT0 field. + EXTMEM_LEVEL_SPLIT0_LEVEL_SPLIT0_Msk = 0xffffffff + + // L2_CACHE_CTRL: L2 Cache(L2-Cache) control register + // Position of L2_CACHE_SHUT_DMA field. + EXTMEM_L2_CACHE_CTRL_L2_CACHE_SHUT_DMA_Pos = 0x4 + // Bit mask of L2_CACHE_SHUT_DMA field. + EXTMEM_L2_CACHE_CTRL_L2_CACHE_SHUT_DMA_Msk = 0x10 + // Bit L2_CACHE_SHUT_DMA. + EXTMEM_L2_CACHE_CTRL_L2_CACHE_SHUT_DMA = 0x10 + // Position of L2_CACHE_UNDEF_OP field. + EXTMEM_L2_CACHE_CTRL_L2_CACHE_UNDEF_OP_Pos = 0x5 + // Bit mask of L2_CACHE_UNDEF_OP field. + EXTMEM_L2_CACHE_CTRL_L2_CACHE_UNDEF_OP_Msk = 0x1e0 + + // L2_BYPASS_CACHE_CONF: Bypass Cache configure register + // Position of BYPASS_L2_CACHE_EN field. + EXTMEM_L2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN_Pos = 0x5 + // Bit mask of BYPASS_L2_CACHE_EN field. + EXTMEM_L2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN_Msk = 0x20 + // Bit BYPASS_L2_CACHE_EN. + EXTMEM_L2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN = 0x20 + + // L2_CACHE_CACHESIZE_CONF: L2 Cache CacheSize mode configure register + // Position of L2_CACHE_CACHESIZE_1K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K_Pos = 0x0 + // Bit mask of L2_CACHE_CACHESIZE_1K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K_Msk = 0x1 + // Bit L2_CACHE_CACHESIZE_1K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K = 0x1 + // Position of L2_CACHE_CACHESIZE_2K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K_Pos = 0x1 + // Bit mask of L2_CACHE_CACHESIZE_2K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K_Msk = 0x2 + // Bit L2_CACHE_CACHESIZE_2K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K = 0x2 + // Position of L2_CACHE_CACHESIZE_4K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K_Pos = 0x2 + // Bit mask of L2_CACHE_CACHESIZE_4K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K_Msk = 0x4 + // Bit L2_CACHE_CACHESIZE_4K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K = 0x4 + // Position of L2_CACHE_CACHESIZE_8K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K_Pos = 0x3 + // Bit mask of L2_CACHE_CACHESIZE_8K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K_Msk = 0x8 + // Bit L2_CACHE_CACHESIZE_8K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K = 0x8 + // Position of L2_CACHE_CACHESIZE_16K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K_Pos = 0x4 + // Bit mask of L2_CACHE_CACHESIZE_16K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K_Msk = 0x10 + // Bit L2_CACHE_CACHESIZE_16K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K = 0x10 + // Position of L2_CACHE_CACHESIZE_32K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K_Pos = 0x5 + // Bit mask of L2_CACHE_CACHESIZE_32K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K_Msk = 0x20 + // Bit L2_CACHE_CACHESIZE_32K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K = 0x20 + // Position of L2_CACHE_CACHESIZE_64K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K_Pos = 0x6 + // Bit mask of L2_CACHE_CACHESIZE_64K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K_Msk = 0x40 + // Bit L2_CACHE_CACHESIZE_64K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K = 0x40 + // Position of L2_CACHE_CACHESIZE_128K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K_Pos = 0x7 + // Bit mask of L2_CACHE_CACHESIZE_128K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K_Msk = 0x80 + // Bit L2_CACHE_CACHESIZE_128K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K = 0x80 + // Position of L2_CACHE_CACHESIZE_256K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K_Pos = 0x8 + // Bit mask of L2_CACHE_CACHESIZE_256K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K_Msk = 0x100 + // Bit L2_CACHE_CACHESIZE_256K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K = 0x100 + // Position of L2_CACHE_CACHESIZE_512K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K_Pos = 0x9 + // Bit mask of L2_CACHE_CACHESIZE_512K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K_Msk = 0x200 + // Bit L2_CACHE_CACHESIZE_512K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K = 0x200 + // Position of L2_CACHE_CACHESIZE_1024K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K_Pos = 0xa + // Bit mask of L2_CACHE_CACHESIZE_1024K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K_Msk = 0x400 + // Bit L2_CACHE_CACHESIZE_1024K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K = 0x400 + // Position of L2_CACHE_CACHESIZE_2048K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2048K_Pos = 0xb + // Bit mask of L2_CACHE_CACHESIZE_2048K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2048K_Msk = 0x800 + // Bit L2_CACHE_CACHESIZE_2048K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2048K = 0x800 + // Position of L2_CACHE_CACHESIZE_4096K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4096K_Pos = 0xc + // Bit mask of L2_CACHE_CACHESIZE_4096K field. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4096K_Msk = 0x1000 + // Bit L2_CACHE_CACHESIZE_4096K. + EXTMEM_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4096K = 0x1000 + + // L2_CACHE_BLOCKSIZE_CONF: L2 Cache BlockSize mode configure register + // Position of L2_CACHE_BLOCKSIZE_8 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8_Pos = 0x0 + // Bit mask of L2_CACHE_BLOCKSIZE_8 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8_Msk = 0x1 + // Bit L2_CACHE_BLOCKSIZE_8. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8 = 0x1 + // Position of L2_CACHE_BLOCKSIZE_16 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16_Pos = 0x1 + // Bit mask of L2_CACHE_BLOCKSIZE_16 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16_Msk = 0x2 + // Bit L2_CACHE_BLOCKSIZE_16. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16 = 0x2 + // Position of L2_CACHE_BLOCKSIZE_32 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32_Pos = 0x2 + // Bit mask of L2_CACHE_BLOCKSIZE_32 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32_Msk = 0x4 + // Bit L2_CACHE_BLOCKSIZE_32. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32 = 0x4 + // Position of L2_CACHE_BLOCKSIZE_64 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64_Pos = 0x3 + // Bit mask of L2_CACHE_BLOCKSIZE_64 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64_Msk = 0x8 + // Bit L2_CACHE_BLOCKSIZE_64. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64 = 0x8 + // Position of L2_CACHE_BLOCKSIZE_128 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128_Pos = 0x4 + // Bit mask of L2_CACHE_BLOCKSIZE_128 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128_Msk = 0x10 + // Bit L2_CACHE_BLOCKSIZE_128. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128 = 0x10 + // Position of L2_CACHE_BLOCKSIZE_256 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256_Pos = 0x5 + // Bit mask of L2_CACHE_BLOCKSIZE_256 field. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256_Msk = 0x20 + // Bit L2_CACHE_BLOCKSIZE_256. + EXTMEM_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256 = 0x20 + + // L2_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register + // Position of L2_CACHE_WRAP field. + EXTMEM_L2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP_Pos = 0x5 + // Bit mask of L2_CACHE_WRAP field. + EXTMEM_L2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP_Msk = 0x20 + // Bit L2_CACHE_WRAP. + EXTMEM_L2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP = 0x20 + + // L2_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register + // Position of L2_CACHE_TAG_MEM_FORCE_ON field. + EXTMEM_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON_Pos = 0x14 + // Bit mask of L2_CACHE_TAG_MEM_FORCE_ON field. + EXTMEM_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON_Msk = 0x100000 + // Bit L2_CACHE_TAG_MEM_FORCE_ON. + EXTMEM_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON = 0x100000 + // Position of L2_CACHE_TAG_MEM_FORCE_PD field. + EXTMEM_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD_Pos = 0x15 + // Bit mask of L2_CACHE_TAG_MEM_FORCE_PD field. + EXTMEM_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD_Msk = 0x200000 + // Bit L2_CACHE_TAG_MEM_FORCE_PD. + EXTMEM_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD = 0x200000 + // Position of L2_CACHE_TAG_MEM_FORCE_PU field. + EXTMEM_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU_Pos = 0x16 + // Bit mask of L2_CACHE_TAG_MEM_FORCE_PU field. + EXTMEM_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU_Msk = 0x400000 + // Bit L2_CACHE_TAG_MEM_FORCE_PU. + EXTMEM_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU = 0x400000 + + // L2_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register + // Position of L2_CACHE_DATA_MEM_FORCE_ON field. + EXTMEM_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON_Pos = 0x14 + // Bit mask of L2_CACHE_DATA_MEM_FORCE_ON field. + EXTMEM_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON_Msk = 0x100000 + // Bit L2_CACHE_DATA_MEM_FORCE_ON. + EXTMEM_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON = 0x100000 + // Position of L2_CACHE_DATA_MEM_FORCE_PD field. + EXTMEM_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD_Pos = 0x15 + // Bit mask of L2_CACHE_DATA_MEM_FORCE_PD field. + EXTMEM_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD_Msk = 0x200000 + // Bit L2_CACHE_DATA_MEM_FORCE_PD. + EXTMEM_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD = 0x200000 + // Position of L2_CACHE_DATA_MEM_FORCE_PU field. + EXTMEM_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU_Pos = 0x16 + // Bit mask of L2_CACHE_DATA_MEM_FORCE_PU field. + EXTMEM_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU_Msk = 0x400000 + // Bit L2_CACHE_DATA_MEM_FORCE_PU. + EXTMEM_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU = 0x400000 + + // L2_CACHE_FREEZE_CTRL: Cache Freeze control register + // Position of L2_CACHE_FREEZE_EN field. + EXTMEM_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN_Pos = 0x14 + // Bit mask of L2_CACHE_FREEZE_EN field. + EXTMEM_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN_Msk = 0x100000 + // Bit L2_CACHE_FREEZE_EN. + EXTMEM_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN = 0x100000 + // Position of L2_CACHE_FREEZE_MODE field. + EXTMEM_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE_Pos = 0x15 + // Bit mask of L2_CACHE_FREEZE_MODE field. + EXTMEM_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE_Msk = 0x200000 + // Bit L2_CACHE_FREEZE_MODE. + EXTMEM_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE = 0x200000 + // Position of L2_CACHE_FREEZE_DONE field. + EXTMEM_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE_Pos = 0x16 + // Bit mask of L2_CACHE_FREEZE_DONE field. + EXTMEM_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE_Msk = 0x400000 + // Bit L2_CACHE_FREEZE_DONE. + EXTMEM_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE = 0x400000 + + // L2_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register + // Position of L2_CACHE_DATA_MEM_RD_EN field. + EXTMEM_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN_Pos = 0x14 + // Bit mask of L2_CACHE_DATA_MEM_RD_EN field. + EXTMEM_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN_Msk = 0x100000 + // Bit L2_CACHE_DATA_MEM_RD_EN. + EXTMEM_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN = 0x100000 + // Position of L2_CACHE_DATA_MEM_WR_EN field. + EXTMEM_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN_Pos = 0x15 + // Bit mask of L2_CACHE_DATA_MEM_WR_EN field. + EXTMEM_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN_Msk = 0x200000 + // Bit L2_CACHE_DATA_MEM_WR_EN. + EXTMEM_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN = 0x200000 + + // L2_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register + // Position of L2_CACHE_TAG_MEM_RD_EN field. + EXTMEM_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN_Pos = 0x14 + // Bit mask of L2_CACHE_TAG_MEM_RD_EN field. + EXTMEM_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN_Msk = 0x100000 + // Bit L2_CACHE_TAG_MEM_RD_EN. + EXTMEM_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN = 0x100000 + // Position of L2_CACHE_TAG_MEM_WR_EN field. + EXTMEM_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN_Pos = 0x15 + // Bit mask of L2_CACHE_TAG_MEM_WR_EN field. + EXTMEM_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN_Msk = 0x200000 + // Bit L2_CACHE_TAG_MEM_WR_EN. + EXTMEM_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN = 0x200000 + + // L2_CACHE_PRELOCK_CONF: L2 Cache prelock configure register + // Position of L2_CACHE_PRELOCK_SCT0_EN field. + EXTMEM_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN_Pos = 0x0 + // Bit mask of L2_CACHE_PRELOCK_SCT0_EN field. + EXTMEM_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN_Msk = 0x1 + // Bit L2_CACHE_PRELOCK_SCT0_EN. + EXTMEM_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN = 0x1 + // Position of L2_CACHE_PRELOCK_SCT1_EN field. + EXTMEM_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN_Pos = 0x1 + // Bit mask of L2_CACHE_PRELOCK_SCT1_EN field. + EXTMEM_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN_Msk = 0x2 + // Bit L2_CACHE_PRELOCK_SCT1_EN. + EXTMEM_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN = 0x2 + // Position of L2_CACHE_PRELOCK_RGID field. + EXTMEM_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID_Pos = 0x2 + // Bit mask of L2_CACHE_PRELOCK_RGID field. + EXTMEM_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID_Msk = 0x3c + + // L2_CACHE_PRELOCK_SCT0_ADDR: L2 Cache prelock section0 address configure register + // Position of L2_CACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_L2_CACHE_PRELOCK_SCT0_ADDR_L2_CACHE_PRELOCK_SCT0_ADDR_Pos = 0x0 + // Bit mask of L2_CACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_L2_CACHE_PRELOCK_SCT0_ADDR_L2_CACHE_PRELOCK_SCT0_ADDR_Msk = 0xffffffff + + // L2_CACHE_PRELOCK_SCT1_ADDR: L2 Cache prelock section1 address configure register + // Position of L2_CACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_L2_CACHE_PRELOCK_SCT1_ADDR_L2_CACHE_PRELOCK_SCT1_ADDR_Pos = 0x0 + // Bit mask of L2_CACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_L2_CACHE_PRELOCK_SCT1_ADDR_L2_CACHE_PRELOCK_SCT1_ADDR_Msk = 0xffffffff + + // L2_CACHE_PRELOCK_SCT_SIZE: L2 Cache prelock section size configure register + // Position of L2_CACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_L2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE_Pos = 0x0 + // Bit mask of L2_CACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_L2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE_Msk = 0xffff + // Position of L2_CACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_L2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE_Pos = 0x10 + // Bit mask of L2_CACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_L2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE_Msk = 0xffff0000 + + // L2_CACHE_PRELOAD_CTRL: L2 Cache preload-operation control register + // Position of L2_CACHE_PRELOAD_ENA field. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA_Pos = 0x0 + // Bit mask of L2_CACHE_PRELOAD_ENA field. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA_Msk = 0x1 + // Bit L2_CACHE_PRELOAD_ENA. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA = 0x1 + // Position of L2_CACHE_PRELOAD_DONE field. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE_Pos = 0x1 + // Bit mask of L2_CACHE_PRELOAD_DONE field. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE_Msk = 0x2 + // Bit L2_CACHE_PRELOAD_DONE. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE = 0x2 + // Position of L2_CACHE_PRELOAD_ORDER field. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER_Pos = 0x2 + // Bit mask of L2_CACHE_PRELOAD_ORDER field. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER_Msk = 0x4 + // Bit L2_CACHE_PRELOAD_ORDER. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER = 0x4 + // Position of L2_CACHE_PRELOAD_RGID field. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID_Pos = 0x3 + // Bit mask of L2_CACHE_PRELOAD_RGID field. + EXTMEM_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID_Msk = 0x78 + + // L2_CACHE_PRELOAD_ADDR: L2 Cache preload address configure register + // Position of L2_CACHE_PRELOAD_ADDR field. + EXTMEM_L2_CACHE_PRELOAD_ADDR_L2_CACHE_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of L2_CACHE_PRELOAD_ADDR field. + EXTMEM_L2_CACHE_PRELOAD_ADDR_L2_CACHE_PRELOAD_ADDR_Msk = 0xffffffff + + // L2_CACHE_PRELOAD_SIZE: L2 Cache preload size configure register + // Position of L2_CACHE_PRELOAD_SIZE field. + EXTMEM_L2_CACHE_PRELOAD_SIZE_L2_CACHE_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of L2_CACHE_PRELOAD_SIZE field. + EXTMEM_L2_CACHE_PRELOAD_SIZE_L2_CACHE_PRELOAD_SIZE_Msk = 0xffff + + // L2_CACHE_AUTOLOAD_CTRL: L2 Cache autoload-operation control register + // Position of L2_CACHE_AUTOLOAD_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA_Pos = 0x0 + // Bit mask of L2_CACHE_AUTOLOAD_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA_Msk = 0x1 + // Bit L2_CACHE_AUTOLOAD_ENA. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA = 0x1 + // Position of L2_CACHE_AUTOLOAD_DONE field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE_Pos = 0x1 + // Bit mask of L2_CACHE_AUTOLOAD_DONE field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE_Msk = 0x2 + // Bit L2_CACHE_AUTOLOAD_DONE. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE = 0x2 + // Position of L2_CACHE_AUTOLOAD_ORDER field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER_Pos = 0x2 + // Bit mask of L2_CACHE_AUTOLOAD_ORDER field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER_Msk = 0x4 + // Bit L2_CACHE_AUTOLOAD_ORDER. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER = 0x4 + // Position of L2_CACHE_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE_Pos = 0x3 + // Bit mask of L2_CACHE_AUTOLOAD_TRIGGER_MODE field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE_Msk = 0x18 + // Position of L2_CACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA_Pos = 0x8 + // Bit mask of L2_CACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA_Msk = 0x100 + // Bit L2_CACHE_AUTOLOAD_SCT0_ENA. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA = 0x100 + // Position of L2_CACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA_Pos = 0x9 + // Bit mask of L2_CACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA_Msk = 0x200 + // Bit L2_CACHE_AUTOLOAD_SCT1_ENA. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA = 0x200 + // Position of L2_CACHE_AUTOLOAD_SCT2_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA_Pos = 0xa + // Bit mask of L2_CACHE_AUTOLOAD_SCT2_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA_Msk = 0x400 + // Bit L2_CACHE_AUTOLOAD_SCT2_ENA. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA = 0x400 + // Position of L2_CACHE_AUTOLOAD_SCT3_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA_Pos = 0xb + // Bit mask of L2_CACHE_AUTOLOAD_SCT3_ENA field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA_Msk = 0x800 + // Bit L2_CACHE_AUTOLOAD_SCT3_ENA. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA = 0x800 + // Position of L2_CACHE_AUTOLOAD_RGID field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID_Pos = 0xc + // Bit mask of L2_CACHE_AUTOLOAD_RGID field. + EXTMEM_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID_Msk = 0xf000 + + // L2_CACHE_AUTOLOAD_SCT0_ADDR: L2 Cache autoload section 0 address configure register + // Position of L2_CACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT0_ADDR_L2_CACHE_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of L2_CACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT0_ADDR_L2_CACHE_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // L2_CACHE_AUTOLOAD_SCT0_SIZE: L2 Cache autoload section 0 size configure register + // Position of L2_CACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT0_SIZE_L2_CACHE_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of L2_CACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT0_SIZE_L2_CACHE_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff + + // L2_CACHE_AUTOLOAD_SCT1_ADDR: L2 Cache autoload section 1 address configure register + // Position of L2_CACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT1_ADDR_L2_CACHE_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of L2_CACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT1_ADDR_L2_CACHE_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // L2_CACHE_AUTOLOAD_SCT1_SIZE: L2 Cache autoload section 1 size configure register + // Position of L2_CACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT1_SIZE_L2_CACHE_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of L2_CACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT1_SIZE_L2_CACHE_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff + + // L2_CACHE_AUTOLOAD_SCT2_ADDR: L2 Cache autoload section 2 address configure register + // Position of L2_CACHE_AUTOLOAD_SCT2_ADDR field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT2_ADDR_L2_CACHE_AUTOLOAD_SCT2_ADDR_Pos = 0x0 + // Bit mask of L2_CACHE_AUTOLOAD_SCT2_ADDR field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT2_ADDR_L2_CACHE_AUTOLOAD_SCT2_ADDR_Msk = 0xffffffff + + // L2_CACHE_AUTOLOAD_SCT2_SIZE: L2 Cache autoload section 2 size configure register + // Position of L2_CACHE_AUTOLOAD_SCT2_SIZE field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT2_SIZE_L2_CACHE_AUTOLOAD_SCT2_SIZE_Pos = 0x0 + // Bit mask of L2_CACHE_AUTOLOAD_SCT2_SIZE field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT2_SIZE_L2_CACHE_AUTOLOAD_SCT2_SIZE_Msk = 0xfffffff + + // L2_CACHE_AUTOLOAD_SCT3_ADDR: L2 Cache autoload section 3 address configure register + // Position of L2_CACHE_AUTOLOAD_SCT3_ADDR field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT3_ADDR_L2_CACHE_AUTOLOAD_SCT3_ADDR_Pos = 0x0 + // Bit mask of L2_CACHE_AUTOLOAD_SCT3_ADDR field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT3_ADDR_L2_CACHE_AUTOLOAD_SCT3_ADDR_Msk = 0xffffffff + + // L2_CACHE_AUTOLOAD_SCT3_SIZE: L2 Cache autoload section 3 size configure register + // Position of L2_CACHE_AUTOLOAD_SCT3_SIZE field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT3_SIZE_L2_CACHE_AUTOLOAD_SCT3_SIZE_Pos = 0x0 + // Bit mask of L2_CACHE_AUTOLOAD_SCT3_SIZE field. + EXTMEM_L2_CACHE_AUTOLOAD_SCT3_SIZE_L2_CACHE_AUTOLOAD_SCT3_SIZE_Msk = 0xfffffff + + // L2_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register + // Position of L2_IBUS0_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA_Pos = 0x8 + // Bit mask of L2_IBUS0_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA_Msk = 0x100 + // Bit L2_IBUS0_OVF_INT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA = 0x100 + // Position of L2_IBUS1_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA_Pos = 0x9 + // Bit mask of L2_IBUS1_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA_Msk = 0x200 + // Bit L2_IBUS1_OVF_INT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA = 0x200 + // Position of L2_IBUS2_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA_Pos = 0xa + // Bit mask of L2_IBUS2_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA_Msk = 0x400 + // Bit L2_IBUS2_OVF_INT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA = 0x400 + // Position of L2_IBUS3_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA_Pos = 0xb + // Bit mask of L2_IBUS3_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA_Msk = 0x800 + // Bit L2_IBUS3_OVF_INT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA = 0x800 + // Position of L2_DBUS0_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA_Pos = 0xc + // Bit mask of L2_DBUS0_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA_Msk = 0x1000 + // Bit L2_DBUS0_OVF_INT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA = 0x1000 + // Position of L2_DBUS1_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA_Pos = 0xd + // Bit mask of L2_DBUS1_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA_Msk = 0x2000 + // Bit L2_DBUS1_OVF_INT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA = 0x2000 + // Position of L2_DBUS2_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA_Pos = 0xe + // Bit mask of L2_DBUS2_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA_Msk = 0x4000 + // Bit L2_DBUS2_OVF_INT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA = 0x4000 + // Position of L2_DBUS3_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA_Pos = 0xf + // Bit mask of L2_DBUS3_OVF_INT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA_Msk = 0x8000 + // Bit L2_DBUS3_OVF_INT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA = 0x8000 + + // L2_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register + // Position of L2_IBUS0_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR_Pos = 0x8 + // Bit mask of L2_IBUS0_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR_Msk = 0x100 + // Bit L2_IBUS0_OVF_INT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR = 0x100 + // Position of L2_IBUS1_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR_Pos = 0x9 + // Bit mask of L2_IBUS1_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR_Msk = 0x200 + // Bit L2_IBUS1_OVF_INT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR = 0x200 + // Position of L2_IBUS2_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR_Pos = 0xa + // Bit mask of L2_IBUS2_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR_Msk = 0x400 + // Bit L2_IBUS2_OVF_INT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR = 0x400 + // Position of L2_IBUS3_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR_Pos = 0xb + // Bit mask of L2_IBUS3_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR_Msk = 0x800 + // Bit L2_IBUS3_OVF_INT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR = 0x800 + // Position of L2_DBUS0_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR_Pos = 0xc + // Bit mask of L2_DBUS0_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR_Msk = 0x1000 + // Bit L2_DBUS0_OVF_INT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR = 0x1000 + // Position of L2_DBUS1_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR_Pos = 0xd + // Bit mask of L2_DBUS1_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR_Msk = 0x2000 + // Bit L2_DBUS1_OVF_INT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR = 0x2000 + // Position of L2_DBUS2_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR_Pos = 0xe + // Bit mask of L2_DBUS2_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR_Msk = 0x4000 + // Bit L2_DBUS2_OVF_INT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR = 0x4000 + // Position of L2_DBUS3_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR_Pos = 0xf + // Bit mask of L2_DBUS3_OVF_INT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR_Msk = 0x8000 + // Bit L2_DBUS3_OVF_INT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR = 0x8000 + + // L2_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register + // Position of L2_IBUS0_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW_Pos = 0x8 + // Bit mask of L2_IBUS0_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW_Msk = 0x100 + // Bit L2_IBUS0_OVF_INT_RAW. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW = 0x100 + // Position of L2_IBUS1_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW_Pos = 0x9 + // Bit mask of L2_IBUS1_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW_Msk = 0x200 + // Bit L2_IBUS1_OVF_INT_RAW. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW = 0x200 + // Position of L2_IBUS2_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW_Pos = 0xa + // Bit mask of L2_IBUS2_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW_Msk = 0x400 + // Bit L2_IBUS2_OVF_INT_RAW. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW = 0x400 + // Position of L2_IBUS3_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW_Pos = 0xb + // Bit mask of L2_IBUS3_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW_Msk = 0x800 + // Bit L2_IBUS3_OVF_INT_RAW. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW = 0x800 + // Position of L2_DBUS0_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW_Pos = 0xc + // Bit mask of L2_DBUS0_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW_Msk = 0x1000 + // Bit L2_DBUS0_OVF_INT_RAW. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW = 0x1000 + // Position of L2_DBUS1_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW_Pos = 0xd + // Bit mask of L2_DBUS1_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW_Msk = 0x2000 + // Bit L2_DBUS1_OVF_INT_RAW. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW = 0x2000 + // Position of L2_DBUS2_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW_Pos = 0xe + // Bit mask of L2_DBUS2_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW_Msk = 0x4000 + // Bit L2_DBUS2_OVF_INT_RAW. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW = 0x4000 + // Position of L2_DBUS3_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW_Pos = 0xf + // Bit mask of L2_DBUS3_OVF_INT_RAW field. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW_Msk = 0x8000 + // Bit L2_DBUS3_OVF_INT_RAW. + EXTMEM_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW = 0x8000 + + // L2_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register + // Position of L2_IBUS0_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST_Pos = 0x8 + // Bit mask of L2_IBUS0_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST_Msk = 0x100 + // Bit L2_IBUS0_OVF_INT_ST. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST = 0x100 + // Position of L2_IBUS1_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST_Pos = 0x9 + // Bit mask of L2_IBUS1_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST_Msk = 0x200 + // Bit L2_IBUS1_OVF_INT_ST. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST = 0x200 + // Position of L2_IBUS2_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST_Pos = 0xa + // Bit mask of L2_IBUS2_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST_Msk = 0x400 + // Bit L2_IBUS2_OVF_INT_ST. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST = 0x400 + // Position of L2_IBUS3_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST_Pos = 0xb + // Bit mask of L2_IBUS3_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST_Msk = 0x800 + // Bit L2_IBUS3_OVF_INT_ST. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST = 0x800 + // Position of L2_DBUS0_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST_Pos = 0xc + // Bit mask of L2_DBUS0_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST_Msk = 0x1000 + // Bit L2_DBUS0_OVF_INT_ST. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST = 0x1000 + // Position of L2_DBUS1_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST_Pos = 0xd + // Bit mask of L2_DBUS1_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST_Msk = 0x2000 + // Bit L2_DBUS1_OVF_INT_ST. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST = 0x2000 + // Position of L2_DBUS2_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST_Pos = 0xe + // Bit mask of L2_DBUS2_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST_Msk = 0x4000 + // Bit L2_DBUS2_OVF_INT_ST. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST = 0x4000 + // Position of L2_DBUS3_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST_Pos = 0xf + // Bit mask of L2_DBUS3_OVF_INT_ST field. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST_Msk = 0x8000 + // Bit L2_DBUS3_OVF_INT_ST. + EXTMEM_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST = 0x8000 + + // L2_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register + // Position of L2_CACHE_FAIL_INT_ENA field. + EXTMEM_L2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA_Pos = 0x5 + // Bit mask of L2_CACHE_FAIL_INT_ENA field. + EXTMEM_L2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA_Msk = 0x20 + // Bit L2_CACHE_FAIL_INT_ENA. + EXTMEM_L2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA = 0x20 + + // L2_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register + // Position of L2_CACHE_FAIL_INT_CLR field. + EXTMEM_L2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR_Pos = 0x5 + // Bit mask of L2_CACHE_FAIL_INT_CLR field. + EXTMEM_L2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR_Msk = 0x20 + // Bit L2_CACHE_FAIL_INT_CLR. + EXTMEM_L2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR = 0x20 + + // L2_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register + // Position of L2_CACHE_FAIL_INT_RAW field. + EXTMEM_L2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW_Pos = 0x5 + // Bit mask of L2_CACHE_FAIL_INT_RAW field. + EXTMEM_L2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW_Msk = 0x20 + // Bit L2_CACHE_FAIL_INT_RAW. + EXTMEM_L2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW = 0x20 + + // L2_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register + // Position of L2_CACHE_FAIL_INT_ST field. + EXTMEM_L2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST_Pos = 0x5 + // Bit mask of L2_CACHE_FAIL_INT_ST field. + EXTMEM_L2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST_Msk = 0x20 + // Bit L2_CACHE_FAIL_INT_ST. + EXTMEM_L2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST = 0x20 + + // L2_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register + // Position of L2_IBUS0_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA_Pos = 0x8 + // Bit mask of L2_IBUS0_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA_Msk = 0x100 + // Bit L2_IBUS0_CNT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA = 0x100 + // Position of L2_IBUS1_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA_Pos = 0x9 + // Bit mask of L2_IBUS1_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA_Msk = 0x200 + // Bit L2_IBUS1_CNT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA = 0x200 + // Position of L2_IBUS2_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA_Pos = 0xa + // Bit mask of L2_IBUS2_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA_Msk = 0x400 + // Bit L2_IBUS2_CNT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA = 0x400 + // Position of L2_IBUS3_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA_Pos = 0xb + // Bit mask of L2_IBUS3_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA_Msk = 0x800 + // Bit L2_IBUS3_CNT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA = 0x800 + // Position of L2_DBUS0_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA_Pos = 0xc + // Bit mask of L2_DBUS0_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA_Msk = 0x1000 + // Bit L2_DBUS0_CNT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA = 0x1000 + // Position of L2_DBUS1_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA_Pos = 0xd + // Bit mask of L2_DBUS1_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA_Msk = 0x2000 + // Bit L2_DBUS1_CNT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA = 0x2000 + // Position of L2_DBUS2_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA_Pos = 0xe + // Bit mask of L2_DBUS2_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA_Msk = 0x4000 + // Bit L2_DBUS2_CNT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA = 0x4000 + // Position of L2_DBUS3_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA_Pos = 0xf + // Bit mask of L2_DBUS3_CNT_ENA field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA_Msk = 0x8000 + // Bit L2_DBUS3_CNT_ENA. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA = 0x8000 + // Position of L2_IBUS0_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR_Pos = 0x18 + // Bit mask of L2_IBUS0_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR_Msk = 0x1000000 + // Bit L2_IBUS0_CNT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR = 0x1000000 + // Position of L2_IBUS1_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR_Pos = 0x19 + // Bit mask of L2_IBUS1_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR_Msk = 0x2000000 + // Bit L2_IBUS1_CNT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR = 0x2000000 + // Position of L2_IBUS2_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR_Pos = 0x1a + // Bit mask of L2_IBUS2_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR_Msk = 0x4000000 + // Bit L2_IBUS2_CNT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR = 0x4000000 + // Position of L2_IBUS3_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR_Pos = 0x1b + // Bit mask of L2_IBUS3_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR_Msk = 0x8000000 + // Bit L2_IBUS3_CNT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR = 0x8000000 + // Position of L2_DBUS0_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR_Pos = 0x1c + // Bit mask of L2_DBUS0_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR_Msk = 0x10000000 + // Bit L2_DBUS0_CNT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR = 0x10000000 + // Position of L2_DBUS1_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR_Pos = 0x1d + // Bit mask of L2_DBUS1_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR_Msk = 0x20000000 + // Bit L2_DBUS1_CNT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR = 0x20000000 + // Position of L2_DBUS2_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR_Pos = 0x1e + // Bit mask of L2_DBUS2_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR_Msk = 0x40000000 + // Bit L2_DBUS2_CNT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR = 0x40000000 + // Position of L2_DBUS3_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR_Pos = 0x1f + // Bit mask of L2_DBUS3_CNT_CLR field. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR_Msk = 0x80000000 + // Bit L2_DBUS3_CNT_CLR. + EXTMEM_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR = 0x80000000 + + // L2_IBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register + // Position of L2_IBUS0_HIT_CNT field. + EXTMEM_L2_IBUS0_ACS_HIT_CNT_L2_IBUS0_HIT_CNT_Pos = 0x0 + // Bit mask of L2_IBUS0_HIT_CNT field. + EXTMEM_L2_IBUS0_ACS_HIT_CNT_L2_IBUS0_HIT_CNT_Msk = 0xffffffff + + // L2_IBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register + // Position of L2_IBUS0_MISS_CNT field. + EXTMEM_L2_IBUS0_ACS_MISS_CNT_L2_IBUS0_MISS_CNT_Pos = 0x0 + // Bit mask of L2_IBUS0_MISS_CNT field. + EXTMEM_L2_IBUS0_ACS_MISS_CNT_L2_IBUS0_MISS_CNT_Msk = 0xffffffff + + // L2_IBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register + // Position of L2_IBUS0_CONFLICT_CNT field. + EXTMEM_L2_IBUS0_ACS_CONFLICT_CNT_L2_IBUS0_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L2_IBUS0_CONFLICT_CNT field. + EXTMEM_L2_IBUS0_ACS_CONFLICT_CNT_L2_IBUS0_CONFLICT_CNT_Msk = 0xffffffff + + // L2_IBUS0_ACS_NXTLVL_CNT: L2-Cache bus0 Next-Level-Access Counter register + // Position of L2_IBUS0_NXTLVL_CNT field. + EXTMEM_L2_IBUS0_ACS_NXTLVL_CNT_L2_IBUS0_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L2_IBUS0_NXTLVL_CNT field. + EXTMEM_L2_IBUS0_ACS_NXTLVL_CNT_L2_IBUS0_NXTLVL_CNT_Msk = 0xffffffff + + // L2_IBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register + // Position of L2_IBUS1_HIT_CNT field. + EXTMEM_L2_IBUS1_ACS_HIT_CNT_L2_IBUS1_HIT_CNT_Pos = 0x0 + // Bit mask of L2_IBUS1_HIT_CNT field. + EXTMEM_L2_IBUS1_ACS_HIT_CNT_L2_IBUS1_HIT_CNT_Msk = 0xffffffff + + // L2_IBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register + // Position of L2_IBUS1_MISS_CNT field. + EXTMEM_L2_IBUS1_ACS_MISS_CNT_L2_IBUS1_MISS_CNT_Pos = 0x0 + // Bit mask of L2_IBUS1_MISS_CNT field. + EXTMEM_L2_IBUS1_ACS_MISS_CNT_L2_IBUS1_MISS_CNT_Msk = 0xffffffff + + // L2_IBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register + // Position of L2_IBUS1_CONFLICT_CNT field. + EXTMEM_L2_IBUS1_ACS_CONFLICT_CNT_L2_IBUS1_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L2_IBUS1_CONFLICT_CNT field. + EXTMEM_L2_IBUS1_ACS_CONFLICT_CNT_L2_IBUS1_CONFLICT_CNT_Msk = 0xffffffff + + // L2_IBUS1_ACS_NXTLVL_CNT: L2-Cache bus1 Next-Level-Access Counter register + // Position of L2_IBUS1_NXTLVL_CNT field. + EXTMEM_L2_IBUS1_ACS_NXTLVL_CNT_L2_IBUS1_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L2_IBUS1_NXTLVL_CNT field. + EXTMEM_L2_IBUS1_ACS_NXTLVL_CNT_L2_IBUS1_NXTLVL_CNT_Msk = 0xffffffff + + // L2_IBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register + // Position of L2_IBUS2_HIT_CNT field. + EXTMEM_L2_IBUS2_ACS_HIT_CNT_L2_IBUS2_HIT_CNT_Pos = 0x0 + // Bit mask of L2_IBUS2_HIT_CNT field. + EXTMEM_L2_IBUS2_ACS_HIT_CNT_L2_IBUS2_HIT_CNT_Msk = 0xffffffff + + // L2_IBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register + // Position of L2_IBUS2_MISS_CNT field. + EXTMEM_L2_IBUS2_ACS_MISS_CNT_L2_IBUS2_MISS_CNT_Pos = 0x0 + // Bit mask of L2_IBUS2_MISS_CNT field. + EXTMEM_L2_IBUS2_ACS_MISS_CNT_L2_IBUS2_MISS_CNT_Msk = 0xffffffff + + // L2_IBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register + // Position of L2_IBUS2_CONFLICT_CNT field. + EXTMEM_L2_IBUS2_ACS_CONFLICT_CNT_L2_IBUS2_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L2_IBUS2_CONFLICT_CNT field. + EXTMEM_L2_IBUS2_ACS_CONFLICT_CNT_L2_IBUS2_CONFLICT_CNT_Msk = 0xffffffff + + // L2_IBUS2_ACS_NXTLVL_CNT: L2-Cache bus2 Next-Level-Access Counter register + // Position of L2_IBUS2_NXTLVL_CNT field. + EXTMEM_L2_IBUS2_ACS_NXTLVL_CNT_L2_IBUS2_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L2_IBUS2_NXTLVL_CNT field. + EXTMEM_L2_IBUS2_ACS_NXTLVL_CNT_L2_IBUS2_NXTLVL_CNT_Msk = 0xffffffff + + // L2_IBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register + // Position of L2_IBUS3_HIT_CNT field. + EXTMEM_L2_IBUS3_ACS_HIT_CNT_L2_IBUS3_HIT_CNT_Pos = 0x0 + // Bit mask of L2_IBUS3_HIT_CNT field. + EXTMEM_L2_IBUS3_ACS_HIT_CNT_L2_IBUS3_HIT_CNT_Msk = 0xffffffff + + // L2_IBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register + // Position of L2_IBUS3_MISS_CNT field. + EXTMEM_L2_IBUS3_ACS_MISS_CNT_L2_IBUS3_MISS_CNT_Pos = 0x0 + // Bit mask of L2_IBUS3_MISS_CNT field. + EXTMEM_L2_IBUS3_ACS_MISS_CNT_L2_IBUS3_MISS_CNT_Msk = 0xffffffff + + // L2_IBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register + // Position of L2_IBUS3_CONFLICT_CNT field. + EXTMEM_L2_IBUS3_ACS_CONFLICT_CNT_L2_IBUS3_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L2_IBUS3_CONFLICT_CNT field. + EXTMEM_L2_IBUS3_ACS_CONFLICT_CNT_L2_IBUS3_CONFLICT_CNT_Msk = 0xffffffff + + // L2_IBUS3_ACS_NXTLVL_CNT: L2-Cache bus3 Next-Level-Access Counter register + // Position of L2_IBUS3_NXTLVL_CNT field. + EXTMEM_L2_IBUS3_ACS_NXTLVL_CNT_L2_IBUS3_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L2_IBUS3_NXTLVL_CNT field. + EXTMEM_L2_IBUS3_ACS_NXTLVL_CNT_L2_IBUS3_NXTLVL_CNT_Msk = 0xffffffff + + // L2_DBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register + // Position of L2_DBUS0_HIT_CNT field. + EXTMEM_L2_DBUS0_ACS_HIT_CNT_L2_DBUS0_HIT_CNT_Pos = 0x0 + // Bit mask of L2_DBUS0_HIT_CNT field. + EXTMEM_L2_DBUS0_ACS_HIT_CNT_L2_DBUS0_HIT_CNT_Msk = 0xffffffff + + // L2_DBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register + // Position of L2_DBUS0_MISS_CNT field. + EXTMEM_L2_DBUS0_ACS_MISS_CNT_L2_DBUS0_MISS_CNT_Pos = 0x0 + // Bit mask of L2_DBUS0_MISS_CNT field. + EXTMEM_L2_DBUS0_ACS_MISS_CNT_L2_DBUS0_MISS_CNT_Msk = 0xffffffff + + // L2_DBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register + // Position of L2_DBUS0_CONFLICT_CNT field. + EXTMEM_L2_DBUS0_ACS_CONFLICT_CNT_L2_DBUS0_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L2_DBUS0_CONFLICT_CNT field. + EXTMEM_L2_DBUS0_ACS_CONFLICT_CNT_L2_DBUS0_CONFLICT_CNT_Msk = 0xffffffff + + // L2_DBUS0_ACS_NXTLVL_CNT: L2-Cache bus0 Next-Level-Access Counter register + // Position of L2_DBUS0_NXTLVL_CNT field. + EXTMEM_L2_DBUS0_ACS_NXTLVL_CNT_L2_DBUS0_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L2_DBUS0_NXTLVL_CNT field. + EXTMEM_L2_DBUS0_ACS_NXTLVL_CNT_L2_DBUS0_NXTLVL_CNT_Msk = 0xffffffff + + // L2_DBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register + // Position of L2_DBUS1_HIT_CNT field. + EXTMEM_L2_DBUS1_ACS_HIT_CNT_L2_DBUS1_HIT_CNT_Pos = 0x0 + // Bit mask of L2_DBUS1_HIT_CNT field. + EXTMEM_L2_DBUS1_ACS_HIT_CNT_L2_DBUS1_HIT_CNT_Msk = 0xffffffff + + // L2_DBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register + // Position of L2_DBUS1_MISS_CNT field. + EXTMEM_L2_DBUS1_ACS_MISS_CNT_L2_DBUS1_MISS_CNT_Pos = 0x0 + // Bit mask of L2_DBUS1_MISS_CNT field. + EXTMEM_L2_DBUS1_ACS_MISS_CNT_L2_DBUS1_MISS_CNT_Msk = 0xffffffff + + // L2_DBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register + // Position of L2_DBUS1_CONFLICT_CNT field. + EXTMEM_L2_DBUS1_ACS_CONFLICT_CNT_L2_DBUS1_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L2_DBUS1_CONFLICT_CNT field. + EXTMEM_L2_DBUS1_ACS_CONFLICT_CNT_L2_DBUS1_CONFLICT_CNT_Msk = 0xffffffff + + // L2_DBUS1_ACS_NXTLVL_CNT: L2-Cache bus1 Next-Level-Access Counter register + // Position of L2_DBUS1_NXTLVL_CNT field. + EXTMEM_L2_DBUS1_ACS_NXTLVL_CNT_L2_DBUS1_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L2_DBUS1_NXTLVL_CNT field. + EXTMEM_L2_DBUS1_ACS_NXTLVL_CNT_L2_DBUS1_NXTLVL_CNT_Msk = 0xffffffff + + // L2_DBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register + // Position of L2_DBUS2_HIT_CNT field. + EXTMEM_L2_DBUS2_ACS_HIT_CNT_L2_DBUS2_HIT_CNT_Pos = 0x0 + // Bit mask of L2_DBUS2_HIT_CNT field. + EXTMEM_L2_DBUS2_ACS_HIT_CNT_L2_DBUS2_HIT_CNT_Msk = 0xffffffff + + // L2_DBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register + // Position of L2_DBUS2_MISS_CNT field. + EXTMEM_L2_DBUS2_ACS_MISS_CNT_L2_DBUS2_MISS_CNT_Pos = 0x0 + // Bit mask of L2_DBUS2_MISS_CNT field. + EXTMEM_L2_DBUS2_ACS_MISS_CNT_L2_DBUS2_MISS_CNT_Msk = 0xffffffff + + // L2_DBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register + // Position of L2_DBUS2_CONFLICT_CNT field. + EXTMEM_L2_DBUS2_ACS_CONFLICT_CNT_L2_DBUS2_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L2_DBUS2_CONFLICT_CNT field. + EXTMEM_L2_DBUS2_ACS_CONFLICT_CNT_L2_DBUS2_CONFLICT_CNT_Msk = 0xffffffff + + // L2_DBUS2_ACS_NXTLVL_CNT: L2-Cache bus2 Next-Level-Access Counter register + // Position of L2_DBUS2_NXTLVL_CNT field. + EXTMEM_L2_DBUS2_ACS_NXTLVL_CNT_L2_DBUS2_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L2_DBUS2_NXTLVL_CNT field. + EXTMEM_L2_DBUS2_ACS_NXTLVL_CNT_L2_DBUS2_NXTLVL_CNT_Msk = 0xffffffff + + // L2_DBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register + // Position of L2_DBUS3_HIT_CNT field. + EXTMEM_L2_DBUS3_ACS_HIT_CNT_L2_DBUS3_HIT_CNT_Pos = 0x0 + // Bit mask of L2_DBUS3_HIT_CNT field. + EXTMEM_L2_DBUS3_ACS_HIT_CNT_L2_DBUS3_HIT_CNT_Msk = 0xffffffff + + // L2_DBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register + // Position of L2_DBUS3_MISS_CNT field. + EXTMEM_L2_DBUS3_ACS_MISS_CNT_L2_DBUS3_MISS_CNT_Pos = 0x0 + // Bit mask of L2_DBUS3_MISS_CNT field. + EXTMEM_L2_DBUS3_ACS_MISS_CNT_L2_DBUS3_MISS_CNT_Msk = 0xffffffff + + // L2_DBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register + // Position of L2_DBUS3_CONFLICT_CNT field. + EXTMEM_L2_DBUS3_ACS_CONFLICT_CNT_L2_DBUS3_CONFLICT_CNT_Pos = 0x0 + // Bit mask of L2_DBUS3_CONFLICT_CNT field. + EXTMEM_L2_DBUS3_ACS_CONFLICT_CNT_L2_DBUS3_CONFLICT_CNT_Msk = 0xffffffff + + // L2_DBUS3_ACS_NXTLVL_CNT: L2-Cache bus3 Next-Level-Access Counter register + // Position of L2_DBUS3_NXTLVL_CNT field. + EXTMEM_L2_DBUS3_ACS_NXTLVL_CNT_L2_DBUS3_NXTLVL_CNT_Pos = 0x0 + // Bit mask of L2_DBUS3_NXTLVL_CNT field. + EXTMEM_L2_DBUS3_ACS_NXTLVL_CNT_L2_DBUS3_NXTLVL_CNT_Msk = 0xffffffff + + // L2_CACHE_ACS_FAIL_ID_ATTR: L2-Cache Access Fail ID/attribution information register + // Position of L2_CACHE_FAIL_ID field. + EXTMEM_L2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID_Pos = 0x0 + // Bit mask of L2_CACHE_FAIL_ID field. + EXTMEM_L2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID_Msk = 0xffff + // Position of L2_CACHE_FAIL_ATTR field. + EXTMEM_L2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR_Pos = 0x10 + // Bit mask of L2_CACHE_FAIL_ATTR field. + EXTMEM_L2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR_Msk = 0xffff0000 + + // L2_CACHE_ACS_FAIL_ADDR: L2-Cache Access Fail Address information register + // Position of L2_CACHE_FAIL_ADDR field. + EXTMEM_L2_CACHE_ACS_FAIL_ADDR_L2_CACHE_FAIL_ADDR_Pos = 0x0 + // Bit mask of L2_CACHE_FAIL_ADDR field. + EXTMEM_L2_CACHE_ACS_FAIL_ADDR_L2_CACHE_FAIL_ADDR_Msk = 0xffffffff + + // L2_CACHE_SYNC_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register + // Position of L2_CACHE_PLD_DONE_INT_ENA field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA_Pos = 0x5 + // Bit mask of L2_CACHE_PLD_DONE_INT_ENA field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA_Msk = 0x20 + // Bit L2_CACHE_PLD_DONE_INT_ENA. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA = 0x20 + // Position of L2_CACHE_PLD_ERR_INT_ENA field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA_Pos = 0xc + // Bit mask of L2_CACHE_PLD_ERR_INT_ENA field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA_Msk = 0x1000 + // Bit L2_CACHE_PLD_ERR_INT_ENA. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA = 0x1000 + + // L2_CACHE_SYNC_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register + // Position of L2_CACHE_PLD_DONE_INT_CLR field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR_Pos = 0x5 + // Bit mask of L2_CACHE_PLD_DONE_INT_CLR field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR_Msk = 0x20 + // Bit L2_CACHE_PLD_DONE_INT_CLR. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR = 0x20 + // Position of L2_CACHE_PLD_ERR_INT_CLR field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR_Pos = 0xc + // Bit mask of L2_CACHE_PLD_ERR_INT_CLR field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR_Msk = 0x1000 + // Bit L2_CACHE_PLD_ERR_INT_CLR. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR = 0x1000 + + // L2_CACHE_SYNC_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register + // Position of L2_CACHE_PLD_DONE_INT_RAW field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW_Pos = 0x5 + // Bit mask of L2_CACHE_PLD_DONE_INT_RAW field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW_Msk = 0x20 + // Bit L2_CACHE_PLD_DONE_INT_RAW. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW = 0x20 + // Position of L2_CACHE_PLD_ERR_INT_RAW field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW_Pos = 0xc + // Bit mask of L2_CACHE_PLD_ERR_INT_RAW field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW_Msk = 0x1000 + // Bit L2_CACHE_PLD_ERR_INT_RAW. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW = 0x1000 + + // L2_CACHE_SYNC_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register + // Position of L2_CACHE_PLD_DONE_INT_ST field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST_Pos = 0x5 + // Bit mask of L2_CACHE_PLD_DONE_INT_ST field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST_Msk = 0x20 + // Bit L2_CACHE_PLD_DONE_INT_ST. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST = 0x20 + // Position of L2_CACHE_PLD_ERR_INT_ST field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST_Pos = 0xc + // Bit mask of L2_CACHE_PLD_ERR_INT_ST field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST_Msk = 0x1000 + // Bit L2_CACHE_PLD_ERR_INT_ST. + EXTMEM_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST = 0x1000 + + // L2_CACHE_SYNC_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register + // Position of L2_CACHE_PLD_ERR_CODE field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE_Pos = 0xa + // Bit mask of L2_CACHE_PLD_ERR_CODE field. + EXTMEM_L2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE_Msk = 0xc00 + + // L2_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register + // Position of L2_CACHE_SYNC_RST field. + EXTMEM_L2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST_Pos = 0x5 + // Bit mask of L2_CACHE_SYNC_RST field. + EXTMEM_L2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST_Msk = 0x20 + // Bit L2_CACHE_SYNC_RST. + EXTMEM_L2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST = 0x20 + + // L2_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register + // Position of L2_CACHE_PLD_RST field. + EXTMEM_L2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST_Pos = 0x5 + // Bit mask of L2_CACHE_PLD_RST field. + EXTMEM_L2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST_Msk = 0x20 + // Bit L2_CACHE_PLD_RST. + EXTMEM_L2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST = 0x20 + + // L2_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register + // Position of L2_CACHE_ALD_BUF_CLR field. + EXTMEM_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR_Pos = 0x5 + // Bit mask of L2_CACHE_ALD_BUF_CLR field. + EXTMEM_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR_Msk = 0x20 + // Bit L2_CACHE_ALD_BUF_CLR. + EXTMEM_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR = 0x20 + + // L2_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers + // Position of L2_CACHE_UNALLOC_CLR field. + EXTMEM_L2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR_Pos = 0x5 + // Bit mask of L2_CACHE_UNALLOC_CLR field. + EXTMEM_L2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR_Msk = 0x20 + // Bit L2_CACHE_UNALLOC_CLR. + EXTMEM_L2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR = 0x20 + + // L2_CACHE_ACCESS_ATTR_CTRL: L1 Cache access Attribute propagation control register + // Position of L2_CACHE_ACCESS_FORCE_CC field. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC_Pos = 0x0 + // Bit mask of L2_CACHE_ACCESS_FORCE_CC field. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC_Msk = 0x1 + // Bit L2_CACHE_ACCESS_FORCE_CC. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC = 0x1 + // Position of L2_CACHE_ACCESS_FORCE_WB field. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB_Pos = 0x1 + // Bit mask of L2_CACHE_ACCESS_FORCE_WB field. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB_Msk = 0x2 + // Bit L2_CACHE_ACCESS_FORCE_WB. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB = 0x2 + // Position of L2_CACHE_ACCESS_FORCE_WMA field. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA_Pos = 0x2 + // Bit mask of L2_CACHE_ACCESS_FORCE_WMA field. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA_Msk = 0x4 + // Bit L2_CACHE_ACCESS_FORCE_WMA. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA = 0x4 + // Position of L2_CACHE_ACCESS_FORCE_RMA field. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA_Pos = 0x3 + // Bit mask of L2_CACHE_ACCESS_FORCE_RMA field. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA_Msk = 0x8 + // Bit L2_CACHE_ACCESS_FORCE_RMA. + EXTMEM_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA = 0x8 + + // L2_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register + // Position of L2_CACHE_TAG_OBJECT field. + EXTMEM_L2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT_Pos = 0x5 + // Bit mask of L2_CACHE_TAG_OBJECT field. + EXTMEM_L2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT_Msk = 0x20 + // Bit L2_CACHE_TAG_OBJECT. + EXTMEM_L2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT = 0x20 + // Position of L2_CACHE_MEM_OBJECT field. + EXTMEM_L2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT_Pos = 0xb + // Bit mask of L2_CACHE_MEM_OBJECT field. + EXTMEM_L2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT_Msk = 0x800 + // Bit L2_CACHE_MEM_OBJECT. + EXTMEM_L2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT = 0x800 + + // L2_CACHE_WAY_OBJECT: Cache Tag and Data memory way register + // Position of L2_CACHE_WAY_OBJECT field. + EXTMEM_L2_CACHE_WAY_OBJECT_L2_CACHE_WAY_OBJECT_Pos = 0x0 + // Bit mask of L2_CACHE_WAY_OBJECT field. + EXTMEM_L2_CACHE_WAY_OBJECT_L2_CACHE_WAY_OBJECT_Msk = 0x7 + + // L2_CACHE_VADDR: Cache Vaddr register + // Position of L2_CACHE_VADDR field. + EXTMEM_L2_CACHE_VADDR_L2_CACHE_VADDR_Pos = 0x0 + // Bit mask of L2_CACHE_VADDR field. + EXTMEM_L2_CACHE_VADDR_L2_CACHE_VADDR_Msk = 0xffffffff + + // L2_CACHE_DEBUG_BUS: Cache Tag/data memory content register + // Position of L2_CACHE_DEBUG_BUS field. + EXTMEM_L2_CACHE_DEBUG_BUS_L2_CACHE_DEBUG_BUS_Pos = 0x0 + // Bit mask of L2_CACHE_DEBUG_BUS field. + EXTMEM_L2_CACHE_DEBUG_BUS_L2_CACHE_DEBUG_BUS_Msk = 0xffffffff + + // LEVEL_SPLIT1: USED TO SPLIT L1 CACHE AND L2 CACHE + // Position of LEVEL_SPLIT1 field. + EXTMEM_LEVEL_SPLIT1_LEVEL_SPLIT1_Pos = 0x0 + // Bit mask of LEVEL_SPLIT1 field. + EXTMEM_LEVEL_SPLIT1_LEVEL_SPLIT1_Msk = 0xffffffff + + // CLOCK_GATE: Clock gate control register + // Position of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + EXTMEM_CLOCK_GATE_CLK_EN = 0x1 + + // REDUNDANCY_SIG0: Cache redundancy signal 0 register + // Position of CACHE_REDCY_SIG0 field. + EXTMEM_REDUNDANCY_SIG0_CACHE_REDCY_SIG0_Pos = 0x0 + // Bit mask of CACHE_REDCY_SIG0 field. + EXTMEM_REDUNDANCY_SIG0_CACHE_REDCY_SIG0_Msk = 0xffffffff + + // REDUNDANCY_SIG1: Cache redundancy signal 1 register + // Position of CACHE_REDCY_SIG1 field. + EXTMEM_REDUNDANCY_SIG1_CACHE_REDCY_SIG1_Pos = 0x0 + // Bit mask of CACHE_REDCY_SIG1 field. + EXTMEM_REDUNDANCY_SIG1_CACHE_REDCY_SIG1_Msk = 0xffffffff + + // REDUNDANCY_SIG2: Cache redundancy signal 2 register + // Position of CACHE_REDCY_SIG2 field. + EXTMEM_REDUNDANCY_SIG2_CACHE_REDCY_SIG2_Pos = 0x0 + // Bit mask of CACHE_REDCY_SIG2 field. + EXTMEM_REDUNDANCY_SIG2_CACHE_REDCY_SIG2_Msk = 0xffffffff + + // REDUNDANCY_SIG3: Cache redundancy signal 3 register + // Position of CACHE_REDCY_SIG3 field. + EXTMEM_REDUNDANCY_SIG3_CACHE_REDCY_SIG3_Pos = 0x0 + // Bit mask of CACHE_REDCY_SIG3 field. + EXTMEM_REDUNDANCY_SIG3_CACHE_REDCY_SIG3_Msk = 0xffffffff + + // REDUNDANCY_SIG4: Cache redundancy signal 0 register + // Position of CACHE_REDCY_SIG4 field. + EXTMEM_REDUNDANCY_SIG4_CACHE_REDCY_SIG4_Pos = 0x0 + // Bit mask of CACHE_REDCY_SIG4 field. + EXTMEM_REDUNDANCY_SIG4_CACHE_REDCY_SIG4_Msk = 0xf + + // DATE: Version control register + // Position of DATE field. + EXTMEM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EXTMEM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for GPIO: General Purpose Input/Output +const ( + // BT_SELECT: GPIO bit select register + // Position of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Pos = 0x0 + // Bit mask of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Msk = 0xffffffff + + // OUT: GPIO output register for GPIO0-31 + // Position of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Pos = 0x0 + // Bit mask of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Msk = 0xffffffff + + // OUT_W1TS: GPIO output set register for GPIO0-31 + // Position of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Pos = 0x0 + // Bit mask of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Msk = 0xffffffff + + // OUT_W1TC: GPIO output clear register for GPIO0-31 + // Position of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Pos = 0x0 + // Bit mask of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Msk = 0xffffffff + + // OUT1: GPIO output register for GPIO32-34 + // Position of DATA_ORIG field. + GPIO_OUT1_DATA_ORIG_Pos = 0x0 + // Bit mask of DATA_ORIG field. + GPIO_OUT1_DATA_ORIG_Msk = 0x7 + + // OUT1_W1TS: GPIO output set register for GPIO32-34 + // Position of OUT1_W1TS field. + GPIO_OUT1_W1TS_OUT1_W1TS_Pos = 0x0 + // Bit mask of OUT1_W1TS field. + GPIO_OUT1_W1TS_OUT1_W1TS_Msk = 0x7 + + // OUT1_W1TC: GPIO output clear register for GPIO32-34 + // Position of OUT1_W1TC field. + GPIO_OUT1_W1TC_OUT1_W1TC_Pos = 0x0 + // Bit mask of OUT1_W1TC field. + GPIO_OUT1_W1TC_OUT1_W1TC_Msk = 0x7 + + // SDIO_SELECT: GPIO sdio select register + // Position of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Pos = 0x0 + // Bit mask of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Msk = 0xff + + // ENABLE: GPIO output enable register for GPIO0-31 + // Position of DATA field. + GPIO_ENABLE_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE_DATA_Msk = 0xffffffff + + // ENABLE_W1TS: GPIO output enable set register for GPIO0-31 + // Position of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Pos = 0x0 + // Bit mask of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Msk = 0xffffffff + + // ENABLE_W1TC: GPIO output enable clear register for GPIO0-31 + // Position of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0x0 + // Bit mask of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0xffffffff + + // ENABLE1: GPIO output enable register for GPIO32-34 + // Position of DATA field. + GPIO_ENABLE1_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE1_DATA_Msk = 0x7 + + // ENABLE1_W1TS: GPIO output enable set register for GPIO32-34 + // Position of ENABLE1_W1TS field. + GPIO_ENABLE1_W1TS_ENABLE1_W1TS_Pos = 0x0 + // Bit mask of ENABLE1_W1TS field. + GPIO_ENABLE1_W1TS_ENABLE1_W1TS_Msk = 0x7 + + // ENABLE1_W1TC: GPIO output enable clear register for GPIO32-34 + // Position of ENABLE1_W1TC field. + GPIO_ENABLE1_W1TC_ENABLE1_W1TC_Pos = 0x0 + // Bit mask of ENABLE1_W1TC field. + GPIO_ENABLE1_W1TC_ENABLE1_W1TC_Msk = 0x7 + + // STRAP: pad strapping register + // Position of STRAPPING field. + GPIO_STRAP_STRAPPING_Pos = 0x0 + // Bit mask of STRAPPING field. + GPIO_STRAP_STRAPPING_Msk = 0xffff + + // IN: GPIO input register for GPIO0-31 + // Position of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Msk = 0xffffffff + + // IN1: GPIO input register for GPIO32-34 + // Position of DATA_NEXT field. + GPIO_IN1_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN1_DATA_NEXT_Msk = 0x7 + + // STATUS: GPIO interrupt status register for GPIO0-31 + // Position of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Msk = 0xffffffff + + // STATUS_W1TS: GPIO interrupt status set register for GPIO0-31 + // Position of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Pos = 0x0 + // Bit mask of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Msk = 0xffffffff + + // STATUS_W1TC: GPIO interrupt status clear register for GPIO0-31 + // Position of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Pos = 0x0 + // Bit mask of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Msk = 0xffffffff + + // STATUS1: GPIO interrupt status register for GPIO32-34 + // Position of INTERRUPT field. + GPIO_STATUS1_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + GPIO_STATUS1_INTERRUPT_Msk = 0x7 + + // STATUS1_W1TS: GPIO interrupt status set register for GPIO32-34 + // Position of STATUS1_W1TS field. + GPIO_STATUS1_W1TS_STATUS1_W1TS_Pos = 0x0 + // Bit mask of STATUS1_W1TS field. + GPIO_STATUS1_W1TS_STATUS1_W1TS_Msk = 0x7 + + // STATUS1_W1TC: GPIO interrupt status clear register for GPIO32-34 + // Position of STATUS1_W1TC field. + GPIO_STATUS1_W1TC_STATUS1_W1TC_Pos = 0x0 + // Bit mask of STATUS1_W1TC field. + GPIO_STATUS1_W1TC_STATUS1_W1TC_Msk = 0x7 + + // PCPU_INT: GPIO PRO_CPU interrupt status register for GPIO0-31 + // Position of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Pos = 0x0 + // Bit mask of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Msk = 0xffffffff + + // PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + // Position of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Msk = 0xffffffff + + // CPUSDIO_INT: GPIO CPUSDIO interrupt status register for GPIO0-31 + // Position of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Pos = 0x0 + // Bit mask of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Msk = 0xffffffff + + // PCPU_INT1: GPIO PRO_CPU interrupt status register for GPIO32-34 + // Position of PROCPU_INT1 field. + GPIO_PCPU_INT1_PROCPU_INT1_Pos = 0x0 + // Bit mask of PROCPU_INT1 field. + GPIO_PCPU_INT1_PROCPU_INT1_Msk = 0x7 + + // PCPU_NMI_INT1: GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + // Position of PROCPU_NMI_INT1 field. + GPIO_PCPU_NMI_INT1_PROCPU_NMI_INT1_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT1 field. + GPIO_PCPU_NMI_INT1_PROCPU_NMI_INT1_Msk = 0x7 + + // CPUSDIO_INT1: GPIO CPUSDIO interrupt status register for GPIO32-34 + // Position of SDIO_INT1 field. + GPIO_CPUSDIO_INT1_SDIO_INT1_Pos = 0x0 + // Bit mask of SDIO_INT1 field. + GPIO_CPUSDIO_INT1_SDIO_INT1_Msk = 0x7 + + // PIN0: GPIO pin configuration register + // Position of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Pos = 0x0 + // Bit mask of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Msk = 0x3 + // Position of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + GPIO_PIN_PAD_DRIVER = 0x4 + // Position of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Pos = 0x3 + // Bit mask of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Msk = 0x18 + // Position of INT_TYPE field. + GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + GPIO_PIN_WAKEUP_ENABLE = 0x400 + // Position of CONFIG field. + GPIO_PIN_CONFIG_Pos = 0xb + // Bit mask of CONFIG field. + GPIO_PIN_CONFIG_Msk = 0x1800 + // Position of INT_ENA field. + GPIO_PIN_INT_ENA_Pos = 0xd + // Bit mask of INT_ENA field. + GPIO_PIN_INT_ENA_Msk = 0x3e000 + + // STATUS_NEXT: GPIO interrupt source register for GPIO0-31 + // Position of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Pos = 0x0 + // Bit mask of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Msk = 0xffffffff + + // STATUS_NEXT1: GPIO interrupt source register for GPIO32-34 + // Position of STATUS_INTERRUPT_NEXT1 field. + GPIO_STATUS_NEXT1_STATUS_INTERRUPT_NEXT1_Pos = 0x0 + // Bit mask of STATUS_INTERRUPT_NEXT1 field. + GPIO_STATUS_NEXT1_STATUS_INTERRUPT_NEXT1_Msk = 0x7 + + // FUNC0_IN_SEL_CFG: GPIO input function configuration register + // Position of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Pos = 0x0 + // Bit mask of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Msk = 0x3f + // Position of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Pos = 0x6 + // Bit mask of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Msk = 0x40 + // Bit IN_INV_SEL. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL = 0x40 + // Position of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Pos = 0x7 + // Bit mask of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Msk = 0x80 + // Bit SEL. + GPIO_FUNC_IN_SEL_CFG_SEL = 0x80 + + // FUNC0_OUT_SEL_CFG: GPIO output function select register + // Position of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Pos = 0x0 + // Bit mask of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Msk = 0xff + // Position of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Pos = 0x8 + // Bit mask of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Msk = 0x100 + // Bit INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL = 0x100 + // Position of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Pos = 0x9 + // Bit mask of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Msk = 0x200 + // Bit OEN_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL = 0x200 + // Position of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Pos = 0xa + // Bit mask of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Msk = 0x400 + // Bit OEN_INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL = 0x400 + + // CLOCK_GATE: GPIO clock gate register + // Position of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + GPIO_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: GPIO version register + // Position of DATE field. + GPIO_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + GPIO_DATE_DATE_Msk = 0xfffffff +) + +// Constants for GPIO_SD: Sigma-Delta Modulation +const ( + // SIGMADELTA0: Duty Cycle Configure Register of SDM%s + // Position of SD0_IN field. + GPIOSD_SIGMADELTA_SD0_IN_Pos = 0x0 + // Bit mask of SD0_IN field. + GPIOSD_SIGMADELTA_SD0_IN_Msk = 0xff + // Position of SD0_PRESCALE field. + GPIOSD_SIGMADELTA_SD0_PRESCALE_Pos = 0x8 + // Bit mask of SD0_PRESCALE field. + GPIOSD_SIGMADELTA_SD0_PRESCALE_Msk = 0xff00 + + // CLOCK_GATE: Clock Gating Configure Register + // Position of CLK_EN field. + GPIOSD_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + GPIOSD_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + GPIOSD_CLOCK_GATE_CLK_EN = 0x1 + + // SIGMADELTA_MISC: MISC Register + // Position of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Pos = 0x1e + // Bit mask of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Msk = 0x40000000 + // Bit FUNCTION_CLK_EN. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN = 0x40000000 + // Position of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Pos = 0x1f + // Bit mask of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Msk = 0x80000000 + // Bit SPI_SWAP. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP = 0x80000000 + + // GLITCH_FILTER_CH0: Glitch Filter Configure Register of Channel%s + // Position of FILTER_CH0_EN field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_EN_Pos = 0x0 + // Bit mask of FILTER_CH0_EN field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_EN_Msk = 0x1 + // Bit FILTER_CH0_EN. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_EN = 0x1 + // Position of FILTER_CH0_INPUT_IO_NUM field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_INPUT_IO_NUM_Pos = 0x1 + // Bit mask of FILTER_CH0_INPUT_IO_NUM field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_INPUT_IO_NUM_Msk = 0x7e + // Position of FILTER_CH0_WINDOW_THRES field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_THRES_Pos = 0x7 + // Bit mask of FILTER_CH0_WINDOW_THRES field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_THRES_Msk = 0x1f80 + // Position of FILTER_CH0_WINDOW_WIDTH field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_WIDTH_Pos = 0xd + // Bit mask of FILTER_CH0_WINDOW_WIDTH field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_WIDTH_Msk = 0x7e000 + + // ETM_EVENT_CH0_CFG: Etm Config register of Channel%s + // Position of ETM_CH0_EVENT_SEL field. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_SEL_Pos = 0x0 + // Bit mask of ETM_CH0_EVENT_SEL field. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_SEL_Msk = 0x1f + // Position of ETM_CH0_EVENT_EN field. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_EN_Pos = 0x7 + // Bit mask of ETM_CH0_EVENT_EN field. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_EN_Msk = 0x80 + // Bit ETM_CH0_EVENT_EN. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_EN = 0x80 + + // ETM_TASK_P0_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO0_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO0_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO0_EN. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN = 0x1 + // Position of ETM_TASK_GPIO0_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO0_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO1_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO1_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO1_EN. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN = 0x100 + // Position of ETM_TASK_GPIO1_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO1_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO2_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO2_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO2_EN. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN = 0x10000 + // Position of ETM_TASK_GPIO2_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO2_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO3_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO3_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO3_EN. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN = 0x1000000 + // Position of ETM_TASK_GPIO3_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO3_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL_Msk = 0xe000000 + + // ETM_TASK_P1_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO4_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO4_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO4_EN. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN = 0x1 + // Position of ETM_TASK_GPIO4_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO4_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO5_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO5_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO5_EN. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN = 0x100 + // Position of ETM_TASK_GPIO5_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO5_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO6_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO6_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO6_EN. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN = 0x10000 + // Position of ETM_TASK_GPIO6_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO6_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO7_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO7_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO7_EN. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN = 0x1000000 + // Position of ETM_TASK_GPIO7_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO7_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL_Msk = 0xe000000 + + // ETM_TASK_P2_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO8_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO8_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO8_EN. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN = 0x1 + // Position of ETM_TASK_GPIO8_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO8_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO9_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO9_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO9_EN. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN = 0x100 + // Position of ETM_TASK_GPIO9_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO9_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO10_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO10_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO10_EN. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN = 0x10000 + // Position of ETM_TASK_GPIO10_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO10_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO11_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO11_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO11_EN. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN = 0x1000000 + // Position of ETM_TASK_GPIO11_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO11_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL_Msk = 0xe000000 + + // ETM_TASK_P3_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO12_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO12_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO12_EN. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN = 0x1 + // Position of ETM_TASK_GPIO12_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO12_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO13_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO13_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO13_EN. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN = 0x100 + // Position of ETM_TASK_GPIO13_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO13_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO14_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO14_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO14_EN. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN = 0x10000 + // Position of ETM_TASK_GPIO14_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO14_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO15_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO15_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO15_EN. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN = 0x1000000 + // Position of ETM_TASK_GPIO15_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO15_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL_Msk = 0xe000000 + + // ETM_TASK_P4_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO16_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO16_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO16_EN. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN = 0x1 + // Position of ETM_TASK_GPIO16_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO16_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO17_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO17_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO17_EN. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN = 0x100 + // Position of ETM_TASK_GPIO17_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO17_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO18_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO18_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO18_EN. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN = 0x10000 + // Position of ETM_TASK_GPIO18_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO18_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO19_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO19_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO19_EN. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN = 0x1000000 + // Position of ETM_TASK_GPIO19_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO19_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL_Msk = 0xe000000 + + // ETM_TASK_P5_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO20_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO20_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO20_EN. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN = 0x1 + // Position of ETM_TASK_GPIO20_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO20_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO21_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO21_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO21_EN. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN = 0x100 + // Position of ETM_TASK_GPIO21_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO21_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO22_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO22_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO22_EN. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN = 0x10000 + // Position of ETM_TASK_GPIO22_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO22_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO23_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO23_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO23_EN. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN = 0x1000000 + // Position of ETM_TASK_GPIO23_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO23_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL_Msk = 0xe000000 + + // ETM_TASK_P6_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO24_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO24_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO24_EN. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN = 0x1 + // Position of ETM_TASK_GPIO24_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO24_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO25_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO25_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO25_EN. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN = 0x100 + // Position of ETM_TASK_GPIO25_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO25_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO26_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO26_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO26_EN. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN = 0x10000 + // Position of ETM_TASK_GPIO26_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO26_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO27_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO27_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO27_EN. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN = 0x1000000 + // Position of ETM_TASK_GPIO27_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO27_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL_Msk = 0xe000000 + + // ETM_TASK_P7_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO28_EN field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO28_EN field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO28_EN. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN = 0x1 + // Position of ETM_TASK_GPIO28_SEL field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO28_SEL field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO29_EN field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO29_EN field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO29_EN. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN = 0x100 + // Position of ETM_TASK_GPIO29_SEL field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO29_SEL field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO30_EN field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO30_EN field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO30_EN. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN = 0x10000 + // Position of ETM_TASK_GPIO30_SEL field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO30_SEL field. + GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL_Msk = 0xe0000 + + // VERSION: Version Control Register + // Position of GPIO_SD_DATE field. + GPIOSD_VERSION_GPIO_SD_DATE_Pos = 0x0 + // Bit mask of GPIO_SD_DATE field. + GPIOSD_VERSION_GPIO_SD_DATE_Msk = 0xfffffff +) + +// Constants for HINF: HINF Peripheral +const ( + // CFG_DATA0: Configure sdio cis content + // Position of DEVICE_ID_FN1 field. + HINF_CFG_DATA0_DEVICE_ID_FN1_Pos = 0x0 + // Bit mask of DEVICE_ID_FN1 field. + HINF_CFG_DATA0_DEVICE_ID_FN1_Msk = 0xffff + // Position of USER_ID_FN1 field. + HINF_CFG_DATA0_USER_ID_FN1_Pos = 0x10 + // Bit mask of USER_ID_FN1 field. + HINF_CFG_DATA0_USER_ID_FN1_Msk = 0xffff0000 + + // CFG_DATA1: SDIO configuration register + // Position of SDIO_ENABLE field. + HINF_CFG_DATA1_SDIO_ENABLE_Pos = 0x0 + // Bit mask of SDIO_ENABLE field. + HINF_CFG_DATA1_SDIO_ENABLE_Msk = 0x1 + // Bit SDIO_ENABLE. + HINF_CFG_DATA1_SDIO_ENABLE = 0x1 + // Position of SDIO_IOREADY1 field. + HINF_CFG_DATA1_SDIO_IOREADY1_Pos = 0x1 + // Bit mask of SDIO_IOREADY1 field. + HINF_CFG_DATA1_SDIO_IOREADY1_Msk = 0x2 + // Bit SDIO_IOREADY1. + HINF_CFG_DATA1_SDIO_IOREADY1 = 0x2 + // Position of HIGHSPEED_ENABLE field. + HINF_CFG_DATA1_HIGHSPEED_ENABLE_Pos = 0x2 + // Bit mask of HIGHSPEED_ENABLE field. + HINF_CFG_DATA1_HIGHSPEED_ENABLE_Msk = 0x4 + // Bit HIGHSPEED_ENABLE. + HINF_CFG_DATA1_HIGHSPEED_ENABLE = 0x4 + // Position of HIGHSPEED_MODE field. + HINF_CFG_DATA1_HIGHSPEED_MODE_Pos = 0x3 + // Bit mask of HIGHSPEED_MODE field. + HINF_CFG_DATA1_HIGHSPEED_MODE_Msk = 0x8 + // Bit HIGHSPEED_MODE. + HINF_CFG_DATA1_HIGHSPEED_MODE = 0x8 + // Position of SDIO_CD_ENABLE field. + HINF_CFG_DATA1_SDIO_CD_ENABLE_Pos = 0x4 + // Bit mask of SDIO_CD_ENABLE field. + HINF_CFG_DATA1_SDIO_CD_ENABLE_Msk = 0x10 + // Bit SDIO_CD_ENABLE. + HINF_CFG_DATA1_SDIO_CD_ENABLE = 0x10 + // Position of SDIO_IOREADY2 field. + HINF_CFG_DATA1_SDIO_IOREADY2_Pos = 0x5 + // Bit mask of SDIO_IOREADY2 field. + HINF_CFG_DATA1_SDIO_IOREADY2_Msk = 0x20 + // Bit SDIO_IOREADY2. + HINF_CFG_DATA1_SDIO_IOREADY2 = 0x20 + // Position of SDIO_INT_MASK field. + HINF_CFG_DATA1_SDIO_INT_MASK_Pos = 0x6 + // Bit mask of SDIO_INT_MASK field. + HINF_CFG_DATA1_SDIO_INT_MASK_Msk = 0x40 + // Bit SDIO_INT_MASK. + HINF_CFG_DATA1_SDIO_INT_MASK = 0x40 + // Position of IOENABLE2 field. + HINF_CFG_DATA1_IOENABLE2_Pos = 0x7 + // Bit mask of IOENABLE2 field. + HINF_CFG_DATA1_IOENABLE2_Msk = 0x80 + // Bit IOENABLE2. + HINF_CFG_DATA1_IOENABLE2 = 0x80 + // Position of CD_DISABLE field. + HINF_CFG_DATA1_CD_DISABLE_Pos = 0x8 + // Bit mask of CD_DISABLE field. + HINF_CFG_DATA1_CD_DISABLE_Msk = 0x100 + // Bit CD_DISABLE. + HINF_CFG_DATA1_CD_DISABLE = 0x100 + // Position of FUNC1_EPS field. + HINF_CFG_DATA1_FUNC1_EPS_Pos = 0x9 + // Bit mask of FUNC1_EPS field. + HINF_CFG_DATA1_FUNC1_EPS_Msk = 0x200 + // Bit FUNC1_EPS. + HINF_CFG_DATA1_FUNC1_EPS = 0x200 + // Position of EMP field. + HINF_CFG_DATA1_EMP_Pos = 0xa + // Bit mask of EMP field. + HINF_CFG_DATA1_EMP_Msk = 0x400 + // Bit EMP. + HINF_CFG_DATA1_EMP = 0x400 + // Position of IOENABLE1 field. + HINF_CFG_DATA1_IOENABLE1_Pos = 0xb + // Bit mask of IOENABLE1 field. + HINF_CFG_DATA1_IOENABLE1_Msk = 0x800 + // Bit IOENABLE1. + HINF_CFG_DATA1_IOENABLE1 = 0x800 + // Position of SDIO_VER field. + HINF_CFG_DATA1_SDIO_VER_Pos = 0xc + // Bit mask of SDIO_VER field. + HINF_CFG_DATA1_SDIO_VER_Msk = 0xfff000 + // Position of FUNC2_EPS field. + HINF_CFG_DATA1_FUNC2_EPS_Pos = 0x18 + // Bit mask of FUNC2_EPS field. + HINF_CFG_DATA1_FUNC2_EPS_Msk = 0x1000000 + // Bit FUNC2_EPS. + HINF_CFG_DATA1_FUNC2_EPS = 0x1000000 + // Position of SDIO20_CONF field. + HINF_CFG_DATA1_SDIO20_CONF_Pos = 0x19 + // Bit mask of SDIO20_CONF field. + HINF_CFG_DATA1_SDIO20_CONF_Msk = 0xfe000000 + + // CFG_TIMING: Timing configuration registers + // Position of NCRC field. + HINF_CFG_TIMING_NCRC_Pos = 0x0 + // Bit mask of NCRC field. + HINF_CFG_TIMING_NCRC_Msk = 0x7 + // Position of PST_END_CMD_LOW_VALUE field. + HINF_CFG_TIMING_PST_END_CMD_LOW_VALUE_Pos = 0x3 + // Bit mask of PST_END_CMD_LOW_VALUE field. + HINF_CFG_TIMING_PST_END_CMD_LOW_VALUE_Msk = 0x3f8 + // Position of PST_END_DATA_LOW_VALUE field. + HINF_CFG_TIMING_PST_END_DATA_LOW_VALUE_Pos = 0xa + // Bit mask of PST_END_DATA_LOW_VALUE field. + HINF_CFG_TIMING_PST_END_DATA_LOW_VALUE_Msk = 0xfc00 + // Position of SDCLK_STOP_THRES field. + HINF_CFG_TIMING_SDCLK_STOP_THRES_Pos = 0x10 + // Bit mask of SDCLK_STOP_THRES field. + HINF_CFG_TIMING_SDCLK_STOP_THRES_Msk = 0x7ff0000 + // Position of SAMPLE_CLK_DIVIDER field. + HINF_CFG_TIMING_SAMPLE_CLK_DIVIDER_Pos = 0x1c + // Bit mask of SAMPLE_CLK_DIVIDER field. + HINF_CFG_TIMING_SAMPLE_CLK_DIVIDER_Msk = 0xf0000000 + + // CFG_UPDATE: update sdio configurations + // Position of CONF_UPDATE field. + HINF_CFG_UPDATE_CONF_UPDATE_Pos = 0x0 + // Bit mask of CONF_UPDATE field. + HINF_CFG_UPDATE_CONF_UPDATE_Msk = 0x1 + // Bit CONF_UPDATE. + HINF_CFG_UPDATE_CONF_UPDATE = 0x1 + + // CFG_DATA7: SDIO configuration register + // Position of PIN_STATE field. + HINF_CFG_DATA7_PIN_STATE_Pos = 0x0 + // Bit mask of PIN_STATE field. + HINF_CFG_DATA7_PIN_STATE_Msk = 0xff + // Position of CHIP_STATE field. + HINF_CFG_DATA7_CHIP_STATE_Pos = 0x8 + // Bit mask of CHIP_STATE field. + HINF_CFG_DATA7_CHIP_STATE_Msk = 0xff00 + // Position of SDIO_RST field. + HINF_CFG_DATA7_SDIO_RST_Pos = 0x10 + // Bit mask of SDIO_RST field. + HINF_CFG_DATA7_SDIO_RST_Msk = 0x10000 + // Bit SDIO_RST. + HINF_CFG_DATA7_SDIO_RST = 0x10000 + // Position of SDIO_IOREADY0 field. + HINF_CFG_DATA7_SDIO_IOREADY0_Pos = 0x11 + // Bit mask of SDIO_IOREADY0 field. + HINF_CFG_DATA7_SDIO_IOREADY0_Msk = 0x20000 + // Bit SDIO_IOREADY0. + HINF_CFG_DATA7_SDIO_IOREADY0 = 0x20000 + // Position of SDIO_MEM_PD field. + HINF_CFG_DATA7_SDIO_MEM_PD_Pos = 0x12 + // Bit mask of SDIO_MEM_PD field. + HINF_CFG_DATA7_SDIO_MEM_PD_Msk = 0x40000 + // Bit SDIO_MEM_PD. + HINF_CFG_DATA7_SDIO_MEM_PD = 0x40000 + // Position of ESDIO_DATA1_INT_EN field. + HINF_CFG_DATA7_ESDIO_DATA1_INT_EN_Pos = 0x13 + // Bit mask of ESDIO_DATA1_INT_EN field. + HINF_CFG_DATA7_ESDIO_DATA1_INT_EN_Msk = 0x80000 + // Bit ESDIO_DATA1_INT_EN. + HINF_CFG_DATA7_ESDIO_DATA1_INT_EN = 0x80000 + // Position of SDIO_SWITCH_VOLT_SW field. + HINF_CFG_DATA7_SDIO_SWITCH_VOLT_SW_Pos = 0x14 + // Bit mask of SDIO_SWITCH_VOLT_SW field. + HINF_CFG_DATA7_SDIO_SWITCH_VOLT_SW_Msk = 0x100000 + // Bit SDIO_SWITCH_VOLT_SW. + HINF_CFG_DATA7_SDIO_SWITCH_VOLT_SW = 0x100000 + // Position of DDR50_BLK_LEN_FIX_EN field. + HINF_CFG_DATA7_DDR50_BLK_LEN_FIX_EN_Pos = 0x15 + // Bit mask of DDR50_BLK_LEN_FIX_EN field. + HINF_CFG_DATA7_DDR50_BLK_LEN_FIX_EN_Msk = 0x200000 + // Bit DDR50_BLK_LEN_FIX_EN. + HINF_CFG_DATA7_DDR50_BLK_LEN_FIX_EN = 0x200000 + // Position of CLK_EN field. + HINF_CFG_DATA7_CLK_EN_Pos = 0x16 + // Bit mask of CLK_EN field. + HINF_CFG_DATA7_CLK_EN_Msk = 0x400000 + // Bit CLK_EN. + HINF_CFG_DATA7_CLK_EN = 0x400000 + // Position of SDDR50 field. + HINF_CFG_DATA7_SDDR50_Pos = 0x17 + // Bit mask of SDDR50 field. + HINF_CFG_DATA7_SDDR50_Msk = 0x800000 + // Bit SDDR50. + HINF_CFG_DATA7_SDDR50 = 0x800000 + // Position of SSDR104 field. + HINF_CFG_DATA7_SSDR104_Pos = 0x18 + // Bit mask of SSDR104 field. + HINF_CFG_DATA7_SSDR104_Msk = 0x1000000 + // Bit SSDR104. + HINF_CFG_DATA7_SSDR104 = 0x1000000 + // Position of SSDR50 field. + HINF_CFG_DATA7_SSDR50_Pos = 0x19 + // Bit mask of SSDR50 field. + HINF_CFG_DATA7_SSDR50_Msk = 0x2000000 + // Bit SSDR50. + HINF_CFG_DATA7_SSDR50 = 0x2000000 + // Position of SDTD field. + HINF_CFG_DATA7_SDTD_Pos = 0x1a + // Bit mask of SDTD field. + HINF_CFG_DATA7_SDTD_Msk = 0x4000000 + // Bit SDTD. + HINF_CFG_DATA7_SDTD = 0x4000000 + // Position of SDTA field. + HINF_CFG_DATA7_SDTA_Pos = 0x1b + // Bit mask of SDTA field. + HINF_CFG_DATA7_SDTA_Msk = 0x8000000 + // Bit SDTA. + HINF_CFG_DATA7_SDTA = 0x8000000 + // Position of SDTC field. + HINF_CFG_DATA7_SDTC_Pos = 0x1c + // Bit mask of SDTC field. + HINF_CFG_DATA7_SDTC_Msk = 0x10000000 + // Bit SDTC. + HINF_CFG_DATA7_SDTC = 0x10000000 + // Position of SAI field. + HINF_CFG_DATA7_SAI_Pos = 0x1d + // Bit mask of SAI field. + HINF_CFG_DATA7_SAI_Msk = 0x20000000 + // Bit SAI. + HINF_CFG_DATA7_SAI = 0x20000000 + // Position of SDIO_WAKEUP_CLR field. + HINF_CFG_DATA7_SDIO_WAKEUP_CLR_Pos = 0x1e + // Bit mask of SDIO_WAKEUP_CLR field. + HINF_CFG_DATA7_SDIO_WAKEUP_CLR_Msk = 0x40000000 + // Bit SDIO_WAKEUP_CLR. + HINF_CFG_DATA7_SDIO_WAKEUP_CLR = 0x40000000 + + // CIS_CONF_W0: SDIO cis configuration register + // Position of CIS_CONF_W0 field. + HINF_CIS_CONF_W0_CIS_CONF_W0_Pos = 0x0 + // Bit mask of CIS_CONF_W0 field. + HINF_CIS_CONF_W0_CIS_CONF_W0_Msk = 0xffffffff + + // CIS_CONF_W1: SDIO cis configuration register + // Position of CIS_CONF_W1 field. + HINF_CIS_CONF_W1_CIS_CONF_W1_Pos = 0x0 + // Bit mask of CIS_CONF_W1 field. + HINF_CIS_CONF_W1_CIS_CONF_W1_Msk = 0xffffffff + + // CIS_CONF_W2: SDIO cis configuration register + // Position of CIS_CONF_W2 field. + HINF_CIS_CONF_W2_CIS_CONF_W2_Pos = 0x0 + // Bit mask of CIS_CONF_W2 field. + HINF_CIS_CONF_W2_CIS_CONF_W2_Msk = 0xffffffff + + // CIS_CONF_W3: SDIO cis configuration register + // Position of CIS_CONF_W3 field. + HINF_CIS_CONF_W3_CIS_CONF_W3_Pos = 0x0 + // Bit mask of CIS_CONF_W3 field. + HINF_CIS_CONF_W3_CIS_CONF_W3_Msk = 0xffffffff + + // CIS_CONF_W4: SDIO cis configuration register + // Position of CIS_CONF_W4 field. + HINF_CIS_CONF_W4_CIS_CONF_W4_Pos = 0x0 + // Bit mask of CIS_CONF_W4 field. + HINF_CIS_CONF_W4_CIS_CONF_W4_Msk = 0xffffffff + + // CIS_CONF_W5: SDIO cis configuration register + // Position of CIS_CONF_W5 field. + HINF_CIS_CONF_W5_CIS_CONF_W5_Pos = 0x0 + // Bit mask of CIS_CONF_W5 field. + HINF_CIS_CONF_W5_CIS_CONF_W5_Msk = 0xffffffff + + // CIS_CONF_W6: SDIO cis configuration register + // Position of CIS_CONF_W6 field. + HINF_CIS_CONF_W6_CIS_CONF_W6_Pos = 0x0 + // Bit mask of CIS_CONF_W6 field. + HINF_CIS_CONF_W6_CIS_CONF_W6_Msk = 0xffffffff + + // CIS_CONF_W7: SDIO cis configuration register + // Position of CIS_CONF_W7 field. + HINF_CIS_CONF_W7_CIS_CONF_W7_Pos = 0x0 + // Bit mask of CIS_CONF_W7 field. + HINF_CIS_CONF_W7_CIS_CONF_W7_Msk = 0xffffffff + + // CFG_DATA16: SDIO cis configuration register + // Position of DEVICE_ID_FN2 field. + HINF_CFG_DATA16_DEVICE_ID_FN2_Pos = 0x0 + // Bit mask of DEVICE_ID_FN2 field. + HINF_CFG_DATA16_DEVICE_ID_FN2_Msk = 0xffff + // Position of USER_ID_FN2 field. + HINF_CFG_DATA16_USER_ID_FN2_Pos = 0x10 + // Bit mask of USER_ID_FN2 field. + HINF_CFG_DATA16_USER_ID_FN2_Msk = 0xffff0000 + + // CFG_UHS1_INT_MODE: configure int to start and end ahead of time in uhs1 mode + // Position of INTOE_END_AHEAD_MODE field. + HINF_CFG_UHS1_INT_MODE_INTOE_END_AHEAD_MODE_Pos = 0x0 + // Bit mask of INTOE_END_AHEAD_MODE field. + HINF_CFG_UHS1_INT_MODE_INTOE_END_AHEAD_MODE_Msk = 0x3 + // Position of INT_END_AHEAD_MODE field. + HINF_CFG_UHS1_INT_MODE_INT_END_AHEAD_MODE_Pos = 0x2 + // Bit mask of INT_END_AHEAD_MODE field. + HINF_CFG_UHS1_INT_MODE_INT_END_AHEAD_MODE_Msk = 0xc + // Position of INTOE_ST_AHEAD_MODE field. + HINF_CFG_UHS1_INT_MODE_INTOE_ST_AHEAD_MODE_Pos = 0x4 + // Bit mask of INTOE_ST_AHEAD_MODE field. + HINF_CFG_UHS1_INT_MODE_INTOE_ST_AHEAD_MODE_Msk = 0x30 + // Position of INT_ST_AHEAD_MODE field. + HINF_CFG_UHS1_INT_MODE_INT_ST_AHEAD_MODE_Pos = 0x6 + // Bit mask of INT_ST_AHEAD_MODE field. + HINF_CFG_UHS1_INT_MODE_INT_ST_AHEAD_MODE_Msk = 0xc0 + + // CONF_STATUS: func0 config0 status + // Position of FUNC0_CONFIG0 field. + HINF_CONF_STATUS_FUNC0_CONFIG0_Pos = 0x0 + // Bit mask of FUNC0_CONFIG0 field. + HINF_CONF_STATUS_FUNC0_CONFIG0_Msk = 0xff + // Position of SDR25_ST field. + HINF_CONF_STATUS_SDR25_ST_Pos = 0x8 + // Bit mask of SDR25_ST field. + HINF_CONF_STATUS_SDR25_ST_Msk = 0x100 + // Bit SDR25_ST. + HINF_CONF_STATUS_SDR25_ST = 0x100 + // Position of SDR50_ST field. + HINF_CONF_STATUS_SDR50_ST_Pos = 0x9 + // Bit mask of SDR50_ST field. + HINF_CONF_STATUS_SDR50_ST_Msk = 0x200 + // Bit SDR50_ST. + HINF_CONF_STATUS_SDR50_ST = 0x200 + // Position of SDR104_ST field. + HINF_CONF_STATUS_SDR104_ST_Pos = 0xa + // Bit mask of SDR104_ST field. + HINF_CONF_STATUS_SDR104_ST_Msk = 0x400 + // Bit SDR104_ST. + HINF_CONF_STATUS_SDR104_ST = 0x400 + // Position of DDR50_ST field. + HINF_CONF_STATUS_DDR50_ST_Pos = 0xb + // Bit mask of DDR50_ST field. + HINF_CONF_STATUS_DDR50_ST_Msk = 0x800 + // Bit DDR50_ST. + HINF_CONF_STATUS_DDR50_ST = 0x800 + // Position of TUNE_ST field. + HINF_CONF_STATUS_TUNE_ST_Pos = 0xc + // Bit mask of TUNE_ST field. + HINF_CONF_STATUS_TUNE_ST_Msk = 0x7000 + // Position of SDIO_SWITCH_VOLT_ST field. + HINF_CONF_STATUS_SDIO_SWITCH_VOLT_ST_Pos = 0xf + // Bit mask of SDIO_SWITCH_VOLT_ST field. + HINF_CONF_STATUS_SDIO_SWITCH_VOLT_ST_Msk = 0x8000 + // Bit SDIO_SWITCH_VOLT_ST. + HINF_CONF_STATUS_SDIO_SWITCH_VOLT_ST = 0x8000 + // Position of SDIO_SWITCH_END field. + HINF_CONF_STATUS_SDIO_SWITCH_END_Pos = 0x10 + // Bit mask of SDIO_SWITCH_END field. + HINF_CONF_STATUS_SDIO_SWITCH_END_Msk = 0x10000 + // Bit SDIO_SWITCH_END. + HINF_CONF_STATUS_SDIO_SWITCH_END = 0x10000 + + // SDIO_SLAVE_ECO_LOW: sdio_slave redundant control registers + // Position of RDN_ECO_LOW field. + HINF_SDIO_SLAVE_ECO_LOW_RDN_ECO_LOW_Pos = 0x0 + // Bit mask of RDN_ECO_LOW field. + HINF_SDIO_SLAVE_ECO_LOW_RDN_ECO_LOW_Msk = 0xffffffff + + // SDIO_SLAVE_ECO_HIGH: sdio_slave redundant control registers + // Position of RDN_ECO_HIGH field. + HINF_SDIO_SLAVE_ECO_HIGH_RDN_ECO_HIGH_Pos = 0x0 + // Bit mask of RDN_ECO_HIGH field. + HINF_SDIO_SLAVE_ECO_HIGH_RDN_ECO_HIGH_Msk = 0xffffffff + + // SDIO_SLAVE_ECO_CONF: sdio_slave redundant control registers + // Position of SDIO_SLAVE_RDN_RESULT field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_RESULT_Pos = 0x0 + // Bit mask of SDIO_SLAVE_RDN_RESULT field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_RESULT_Msk = 0x1 + // Bit SDIO_SLAVE_RDN_RESULT. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_RESULT = 0x1 + // Position of SDIO_SLAVE_RDN_ENA field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_ENA_Pos = 0x1 + // Bit mask of SDIO_SLAVE_RDN_ENA field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_ENA_Msk = 0x2 + // Bit SDIO_SLAVE_RDN_ENA. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_RDN_ENA = 0x2 + // Position of SDIO_SLAVE_SDIO_CLK_RDN_RESULT field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_Pos = 0x2 + // Bit mask of SDIO_SLAVE_SDIO_CLK_RDN_RESULT field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_Msk = 0x4 + // Bit SDIO_SLAVE_SDIO_CLK_RDN_RESULT. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT = 0x4 + // Position of SDIO_SLAVE_SDIO_CLK_RDN_ENA field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_Pos = 0x3 + // Bit mask of SDIO_SLAVE_SDIO_CLK_RDN_ENA field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_Msk = 0x8 + // Bit SDIO_SLAVE_SDIO_CLK_RDN_ENA. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDIO_CLK_RDN_ENA = 0x8 + // Position of SDIO_SLAVE_SDCLK_PAD_RDN_RESULT field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_Pos = 0x4 + // Bit mask of SDIO_SLAVE_SDCLK_PAD_RDN_RESULT field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_Msk = 0x10 + // Bit SDIO_SLAVE_SDCLK_PAD_RDN_RESULT. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT = 0x10 + // Position of SDIO_SLAVE_SDCLK_PAD_RDN_ENA field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_Pos = 0x5 + // Bit mask of SDIO_SLAVE_SDCLK_PAD_RDN_ENA field. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_Msk = 0x20 + // Bit SDIO_SLAVE_SDCLK_PAD_RDN_ENA. + HINF_SDIO_SLAVE_ECO_CONF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA = 0x20 + + // SDIO_SLAVE_LDO_CONF: sdio slave ldo control register + // Position of LDO_READY_CTL_IN_EN field. + HINF_SDIO_SLAVE_LDO_CONF_LDO_READY_CTL_IN_EN_Pos = 0x0 + // Bit mask of LDO_READY_CTL_IN_EN field. + HINF_SDIO_SLAVE_LDO_CONF_LDO_READY_CTL_IN_EN_Msk = 0x1 + // Bit LDO_READY_CTL_IN_EN. + HINF_SDIO_SLAVE_LDO_CONF_LDO_READY_CTL_IN_EN = 0x1 + // Position of LDO_READY_THRES field. + HINF_SDIO_SLAVE_LDO_CONF_LDO_READY_THRES_Pos = 0x1 + // Bit mask of LDO_READY_THRES field. + HINF_SDIO_SLAVE_LDO_CONF_LDO_READY_THRES_Msk = 0x3e + // Position of LDO_READY_IGNORE_EN field. + HINF_SDIO_SLAVE_LDO_CONF_LDO_READY_IGNORE_EN_Pos = 0x6 + // Bit mask of LDO_READY_IGNORE_EN field. + HINF_SDIO_SLAVE_LDO_CONF_LDO_READY_IGNORE_EN_Msk = 0x40 + // Bit LDO_READY_IGNORE_EN. + HINF_SDIO_SLAVE_LDO_CONF_LDO_READY_IGNORE_EN = 0x40 + + // SDIO_DATE: ******* Description *********** + // Position of SDIO_DATE field. + HINF_SDIO_DATE_SDIO_DATE_Pos = 0x0 + // Bit mask of SDIO_DATE field. + HINF_SDIO_DATE_SDIO_DATE_Msk = 0xffffffff +) + +// Constants for HMAC: HMAC (Hash-based Message Authentication Code) Accelerator +const ( + // SET_START: Process control register 0. + // Position of SET_START field. + HMAC_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + HMAC_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + HMAC_SET_START_SET_START = 0x1 + + // SET_PARA_PURPOSE: Configure purpose. + // Position of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Pos = 0x0 + // Bit mask of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Msk = 0xf + + // SET_PARA_KEY: Configure key. + // Position of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Pos = 0x0 + // Bit mask of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Msk = 0x7 + + // SET_PARA_FINISH: Finish initial configuration. + // Position of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Pos = 0x0 + // Bit mask of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Msk = 0x1 + // Bit SET_PARA_END. + HMAC_SET_PARA_FINISH_SET_PARA_END = 0x1 + + // SET_MESSAGE_ONE: Process control register 1. + // Position of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Pos = 0x0 + // Bit mask of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Msk = 0x1 + // Bit SET_TEXT_ONE. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE = 0x1 + + // SET_MESSAGE_ING: Process control register 2. + // Position of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Pos = 0x0 + // Bit mask of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Msk = 0x1 + // Bit SET_TEXT_ING. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING = 0x1 + + // SET_MESSAGE_END: Process control register 3. + // Position of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Pos = 0x0 + // Bit mask of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Msk = 0x1 + // Bit SET_TEXT_END. + HMAC_SET_MESSAGE_END_SET_TEXT_END = 0x1 + + // SET_RESULT_FINISH: Process control register 4. + // Position of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Pos = 0x0 + // Bit mask of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Msk = 0x1 + // Bit SET_RESULT_END. + HMAC_SET_RESULT_FINISH_SET_RESULT_END = 0x1 + + // SET_INVALIDATE_JTAG: Invalidate register 0. + // Position of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Pos = 0x0 + // Bit mask of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Msk = 0x1 + // Bit SET_INVALIDATE_JTAG. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG = 0x1 + + // SET_INVALIDATE_DS: Invalidate register 1. + // Position of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Pos = 0x0 + // Bit mask of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Msk = 0x1 + // Bit SET_INVALIDATE_DS. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS = 0x1 + + // QUERY_ERROR: Error register. + // Position of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Pos = 0x0 + // Bit mask of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Msk = 0x1 + // Bit QUERY_CHECK. + HMAC_QUERY_ERROR_QUERY_CHECK = 0x1 + + // QUERY_BUSY: Busy register. + // Position of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Pos = 0x0 + // Bit mask of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Msk = 0x1 + // Bit BUSY_STATE. + HMAC_QUERY_BUSY_BUSY_STATE = 0x1 + + // SET_MESSAGE_PAD: Process control register 5. + // Position of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Pos = 0x0 + // Bit mask of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Msk = 0x1 + // Bit SET_TEXT_PAD. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD = 0x1 + + // ONE_BLOCK: Process control register 6. + // Position of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Pos = 0x0 + // Bit mask of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Msk = 0x1 + // Bit SET_ONE_BLOCK. + HMAC_ONE_BLOCK_SET_ONE_BLOCK = 0x1 + + // SOFT_JTAG_CTRL: Jtag register 0. + // Position of SOFT_JTAG_CTRL field. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Pos = 0x0 + // Bit mask of SOFT_JTAG_CTRL field. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Msk = 0x1 + // Bit SOFT_JTAG_CTRL. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL = 0x1 + + // WR_JTAG: Jtag register 1. + // Position of WR_JTAG field. + HMAC_WR_JTAG_WR_JTAG_Pos = 0x0 + // Bit mask of WR_JTAG field. + HMAC_WR_JTAG_WR_JTAG_Msk = 0xffffffff + + // DATE: Date register. + // Position of DATE field. + HMAC_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + HMAC_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for HP_APM: HP_APM Peripheral +const ( + // REGION_FILTER_EN: Region filter enable register + // Position of REGION_FILTER_EN field. + HP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Pos = 0x0 + // Bit mask of REGION_FILTER_EN field. + HP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Msk = 0xffff + + // REGION0_ADDR_START: Region address register + // Position of REGION0_ADDR_START field. + HP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Pos = 0x0 + // Bit mask of REGION0_ADDR_START field. + HP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Msk = 0xffffffff + + // REGION0_ADDR_END: Region address register + // Position of REGION0_ADDR_END field. + HP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Pos = 0x0 + // Bit mask of REGION0_ADDR_END field. + HP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Msk = 0xffffffff + + // REGION0_PMS_ATTR: Region access authority attribute register + // Position of REGION0_R0_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION0_R0_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Msk = 0x1 + // Bit REGION0_R0_PMS_X. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X = 0x1 + // Position of REGION0_R0_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION0_R0_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Msk = 0x2 + // Bit REGION0_R0_PMS_W. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W = 0x2 + // Position of REGION0_R0_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION0_R0_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Msk = 0x4 + // Bit REGION0_R0_PMS_R. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R = 0x4 + // Position of REGION0_R1_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION0_R1_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Msk = 0x10 + // Bit REGION0_R1_PMS_X. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X = 0x10 + // Position of REGION0_R1_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION0_R1_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Msk = 0x20 + // Bit REGION0_R1_PMS_W. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W = 0x20 + // Position of REGION0_R1_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION0_R1_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Msk = 0x40 + // Bit REGION0_R1_PMS_R. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R = 0x40 + // Position of REGION0_R2_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION0_R2_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Msk = 0x100 + // Bit REGION0_R2_PMS_X. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X = 0x100 + // Position of REGION0_R2_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION0_R2_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Msk = 0x200 + // Bit REGION0_R2_PMS_W. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W = 0x200 + // Position of REGION0_R2_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Pos = 0xa + // Bit mask of REGION0_R2_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Msk = 0x400 + // Bit REGION0_R2_PMS_R. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R = 0x400 + + // REGION1_ADDR_START: Region address register + // Position of REGION1_ADDR_START field. + HP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Pos = 0x0 + // Bit mask of REGION1_ADDR_START field. + HP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Msk = 0xffffffff + + // REGION1_ADDR_END: Region address register + // Position of REGION1_ADDR_END field. + HP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Pos = 0x0 + // Bit mask of REGION1_ADDR_END field. + HP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Msk = 0xffffffff + + // REGION1_PMS_ATTR: Region access authority attribute register + // Position of REGION1_R0_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION1_R0_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Msk = 0x1 + // Bit REGION1_R0_PMS_X. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X = 0x1 + // Position of REGION1_R0_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION1_R0_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Msk = 0x2 + // Bit REGION1_R0_PMS_W. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W = 0x2 + // Position of REGION1_R0_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION1_R0_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Msk = 0x4 + // Bit REGION1_R0_PMS_R. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R = 0x4 + // Position of REGION1_R1_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION1_R1_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Msk = 0x10 + // Bit REGION1_R1_PMS_X. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X = 0x10 + // Position of REGION1_R1_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION1_R1_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Msk = 0x20 + // Bit REGION1_R1_PMS_W. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W = 0x20 + // Position of REGION1_R1_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION1_R1_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Msk = 0x40 + // Bit REGION1_R1_PMS_R. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R = 0x40 + // Position of REGION1_R2_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION1_R2_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Msk = 0x100 + // Bit REGION1_R2_PMS_X. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X = 0x100 + // Position of REGION1_R2_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION1_R2_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Msk = 0x200 + // Bit REGION1_R2_PMS_W. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W = 0x200 + // Position of REGION1_R2_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Pos = 0xa + // Bit mask of REGION1_R2_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Msk = 0x400 + // Bit REGION1_R2_PMS_R. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R = 0x400 + + // REGION2_ADDR_START: Region address register + // Position of REGION2_ADDR_START field. + HP_APM_REGION2_ADDR_START_REGION2_ADDR_START_Pos = 0x0 + // Bit mask of REGION2_ADDR_START field. + HP_APM_REGION2_ADDR_START_REGION2_ADDR_START_Msk = 0xffffffff + + // REGION2_ADDR_END: Region address register + // Position of REGION2_ADDR_END field. + HP_APM_REGION2_ADDR_END_REGION2_ADDR_END_Pos = 0x0 + // Bit mask of REGION2_ADDR_END field. + HP_APM_REGION2_ADDR_END_REGION2_ADDR_END_Msk = 0xffffffff + + // REGION2_PMS_ATTR: Region access authority attribute register + // Position of REGION2_R0_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION2_R0_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Msk = 0x1 + // Bit REGION2_R0_PMS_X. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X = 0x1 + // Position of REGION2_R0_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION2_R0_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Msk = 0x2 + // Bit REGION2_R0_PMS_W. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W = 0x2 + // Position of REGION2_R0_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION2_R0_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Msk = 0x4 + // Bit REGION2_R0_PMS_R. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R = 0x4 + // Position of REGION2_R1_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION2_R1_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Msk = 0x10 + // Bit REGION2_R1_PMS_X. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X = 0x10 + // Position of REGION2_R1_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION2_R1_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Msk = 0x20 + // Bit REGION2_R1_PMS_W. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W = 0x20 + // Position of REGION2_R1_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION2_R1_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Msk = 0x40 + // Bit REGION2_R1_PMS_R. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R = 0x40 + // Position of REGION2_R2_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION2_R2_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Msk = 0x100 + // Bit REGION2_R2_PMS_X. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X = 0x100 + // Position of REGION2_R2_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION2_R2_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Msk = 0x200 + // Bit REGION2_R2_PMS_W. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W = 0x200 + // Position of REGION2_R2_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Pos = 0xa + // Bit mask of REGION2_R2_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Msk = 0x400 + // Bit REGION2_R2_PMS_R. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R = 0x400 + + // REGION3_ADDR_START: Region address register + // Position of REGION3_ADDR_START field. + HP_APM_REGION3_ADDR_START_REGION3_ADDR_START_Pos = 0x0 + // Bit mask of REGION3_ADDR_START field. + HP_APM_REGION3_ADDR_START_REGION3_ADDR_START_Msk = 0xffffffff + + // REGION3_ADDR_END: Region address register + // Position of REGION3_ADDR_END field. + HP_APM_REGION3_ADDR_END_REGION3_ADDR_END_Pos = 0x0 + // Bit mask of REGION3_ADDR_END field. + HP_APM_REGION3_ADDR_END_REGION3_ADDR_END_Msk = 0xffffffff + + // REGION3_PMS_ATTR: Region access authority attribute register + // Position of REGION3_R0_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION3_R0_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Msk = 0x1 + // Bit REGION3_R0_PMS_X. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X = 0x1 + // Position of REGION3_R0_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION3_R0_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Msk = 0x2 + // Bit REGION3_R0_PMS_W. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W = 0x2 + // Position of REGION3_R0_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION3_R0_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Msk = 0x4 + // Bit REGION3_R0_PMS_R. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R = 0x4 + // Position of REGION3_R1_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION3_R1_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Msk = 0x10 + // Bit REGION3_R1_PMS_X. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X = 0x10 + // Position of REGION3_R1_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION3_R1_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Msk = 0x20 + // Bit REGION3_R1_PMS_W. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W = 0x20 + // Position of REGION3_R1_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION3_R1_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Msk = 0x40 + // Bit REGION3_R1_PMS_R. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R = 0x40 + // Position of REGION3_R2_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION3_R2_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Msk = 0x100 + // Bit REGION3_R2_PMS_X. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X = 0x100 + // Position of REGION3_R2_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION3_R2_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Msk = 0x200 + // Bit REGION3_R2_PMS_W. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W = 0x200 + // Position of REGION3_R2_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Pos = 0xa + // Bit mask of REGION3_R2_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Msk = 0x400 + // Bit REGION3_R2_PMS_R. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R = 0x400 + + // REGION4_ADDR_START: Region address register + // Position of REGION4_ADDR_START field. + HP_APM_REGION4_ADDR_START_REGION4_ADDR_START_Pos = 0x0 + // Bit mask of REGION4_ADDR_START field. + HP_APM_REGION4_ADDR_START_REGION4_ADDR_START_Msk = 0xffffffff + + // REGION4_ADDR_END: Region address register + // Position of REGION4_ADDR_END field. + HP_APM_REGION4_ADDR_END_REGION4_ADDR_END_Pos = 0x0 + // Bit mask of REGION4_ADDR_END field. + HP_APM_REGION4_ADDR_END_REGION4_ADDR_END_Msk = 0xffffffff + + // REGION4_PMS_ATTR: Region access authority attribute register + // Position of REGION4_R0_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION4_R0_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_X_Msk = 0x1 + // Bit REGION4_R0_PMS_X. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_X = 0x1 + // Position of REGION4_R0_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION4_R0_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_W_Msk = 0x2 + // Bit REGION4_R0_PMS_W. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_W = 0x2 + // Position of REGION4_R0_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION4_R0_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_R_Msk = 0x4 + // Bit REGION4_R0_PMS_R. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_R = 0x4 + // Position of REGION4_R1_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION4_R1_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_X_Msk = 0x10 + // Bit REGION4_R1_PMS_X. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_X = 0x10 + // Position of REGION4_R1_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION4_R1_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_W_Msk = 0x20 + // Bit REGION4_R1_PMS_W. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_W = 0x20 + // Position of REGION4_R1_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION4_R1_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_R_Msk = 0x40 + // Bit REGION4_R1_PMS_R. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_R = 0x40 + // Position of REGION4_R2_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION4_R2_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_X_Msk = 0x100 + // Bit REGION4_R2_PMS_X. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_X = 0x100 + // Position of REGION4_R2_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION4_R2_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_W_Msk = 0x200 + // Bit REGION4_R2_PMS_W. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_W = 0x200 + // Position of REGION4_R2_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_R_Pos = 0xa + // Bit mask of REGION4_R2_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_R_Msk = 0x400 + // Bit REGION4_R2_PMS_R. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_R = 0x400 + + // REGION5_ADDR_START: Region address register + // Position of REGION5_ADDR_START field. + HP_APM_REGION5_ADDR_START_REGION5_ADDR_START_Pos = 0x0 + // Bit mask of REGION5_ADDR_START field. + HP_APM_REGION5_ADDR_START_REGION5_ADDR_START_Msk = 0xffffffff + + // REGION5_ADDR_END: Region address register + // Position of REGION5_ADDR_END field. + HP_APM_REGION5_ADDR_END_REGION5_ADDR_END_Pos = 0x0 + // Bit mask of REGION5_ADDR_END field. + HP_APM_REGION5_ADDR_END_REGION5_ADDR_END_Msk = 0xffffffff + + // REGION5_PMS_ATTR: Region access authority attribute register + // Position of REGION5_R0_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION5_R0_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_X_Msk = 0x1 + // Bit REGION5_R0_PMS_X. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_X = 0x1 + // Position of REGION5_R0_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION5_R0_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_W_Msk = 0x2 + // Bit REGION5_R0_PMS_W. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_W = 0x2 + // Position of REGION5_R0_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION5_R0_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_R_Msk = 0x4 + // Bit REGION5_R0_PMS_R. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_R = 0x4 + // Position of REGION5_R1_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION5_R1_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_X_Msk = 0x10 + // Bit REGION5_R1_PMS_X. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_X = 0x10 + // Position of REGION5_R1_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION5_R1_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_W_Msk = 0x20 + // Bit REGION5_R1_PMS_W. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_W = 0x20 + // Position of REGION5_R1_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION5_R1_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_R_Msk = 0x40 + // Bit REGION5_R1_PMS_R. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_R = 0x40 + // Position of REGION5_R2_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION5_R2_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_X_Msk = 0x100 + // Bit REGION5_R2_PMS_X. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_X = 0x100 + // Position of REGION5_R2_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION5_R2_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_W_Msk = 0x200 + // Bit REGION5_R2_PMS_W. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_W = 0x200 + // Position of REGION5_R2_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_R_Pos = 0xa + // Bit mask of REGION5_R2_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_R_Msk = 0x400 + // Bit REGION5_R2_PMS_R. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_R = 0x400 + + // REGION6_ADDR_START: Region address register + // Position of REGION6_ADDR_START field. + HP_APM_REGION6_ADDR_START_REGION6_ADDR_START_Pos = 0x0 + // Bit mask of REGION6_ADDR_START field. + HP_APM_REGION6_ADDR_START_REGION6_ADDR_START_Msk = 0xffffffff + + // REGION6_ADDR_END: Region address register + // Position of REGION6_ADDR_END field. + HP_APM_REGION6_ADDR_END_REGION6_ADDR_END_Pos = 0x0 + // Bit mask of REGION6_ADDR_END field. + HP_APM_REGION6_ADDR_END_REGION6_ADDR_END_Msk = 0xffffffff + + // REGION6_PMS_ATTR: Region access authority attribute register + // Position of REGION6_R0_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION6_R0_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_X_Msk = 0x1 + // Bit REGION6_R0_PMS_X. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_X = 0x1 + // Position of REGION6_R0_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION6_R0_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_W_Msk = 0x2 + // Bit REGION6_R0_PMS_W. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_W = 0x2 + // Position of REGION6_R0_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION6_R0_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_R_Msk = 0x4 + // Bit REGION6_R0_PMS_R. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_R = 0x4 + // Position of REGION6_R1_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION6_R1_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_X_Msk = 0x10 + // Bit REGION6_R1_PMS_X. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_X = 0x10 + // Position of REGION6_R1_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION6_R1_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_W_Msk = 0x20 + // Bit REGION6_R1_PMS_W. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_W = 0x20 + // Position of REGION6_R1_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION6_R1_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_R_Msk = 0x40 + // Bit REGION6_R1_PMS_R. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_R = 0x40 + // Position of REGION6_R2_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION6_R2_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_X_Msk = 0x100 + // Bit REGION6_R2_PMS_X. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_X = 0x100 + // Position of REGION6_R2_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION6_R2_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_W_Msk = 0x200 + // Bit REGION6_R2_PMS_W. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_W = 0x200 + // Position of REGION6_R2_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_R_Pos = 0xa + // Bit mask of REGION6_R2_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_R_Msk = 0x400 + // Bit REGION6_R2_PMS_R. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_R = 0x400 + + // REGION7_ADDR_START: Region address register + // Position of REGION7_ADDR_START field. + HP_APM_REGION7_ADDR_START_REGION7_ADDR_START_Pos = 0x0 + // Bit mask of REGION7_ADDR_START field. + HP_APM_REGION7_ADDR_START_REGION7_ADDR_START_Msk = 0xffffffff + + // REGION7_ADDR_END: Region address register + // Position of REGION7_ADDR_END field. + HP_APM_REGION7_ADDR_END_REGION7_ADDR_END_Pos = 0x0 + // Bit mask of REGION7_ADDR_END field. + HP_APM_REGION7_ADDR_END_REGION7_ADDR_END_Msk = 0xffffffff + + // REGION7_PMS_ATTR: Region access authority attribute register + // Position of REGION7_R0_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION7_R0_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_X_Msk = 0x1 + // Bit REGION7_R0_PMS_X. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_X = 0x1 + // Position of REGION7_R0_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION7_R0_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_W_Msk = 0x2 + // Bit REGION7_R0_PMS_W. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_W = 0x2 + // Position of REGION7_R0_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION7_R0_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_R_Msk = 0x4 + // Bit REGION7_R0_PMS_R. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_R = 0x4 + // Position of REGION7_R1_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION7_R1_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_X_Msk = 0x10 + // Bit REGION7_R1_PMS_X. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_X = 0x10 + // Position of REGION7_R1_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION7_R1_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_W_Msk = 0x20 + // Bit REGION7_R1_PMS_W. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_W = 0x20 + // Position of REGION7_R1_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION7_R1_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_R_Msk = 0x40 + // Bit REGION7_R1_PMS_R. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_R = 0x40 + // Position of REGION7_R2_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION7_R2_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_X_Msk = 0x100 + // Bit REGION7_R2_PMS_X. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_X = 0x100 + // Position of REGION7_R2_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION7_R2_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_W_Msk = 0x200 + // Bit REGION7_R2_PMS_W. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_W = 0x200 + // Position of REGION7_R2_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_R_Pos = 0xa + // Bit mask of REGION7_R2_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_R_Msk = 0x400 + // Bit REGION7_R2_PMS_R. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_R = 0x400 + + // REGION8_ADDR_START: Region address register + // Position of REGION8_ADDR_START field. + HP_APM_REGION8_ADDR_START_REGION8_ADDR_START_Pos = 0x0 + // Bit mask of REGION8_ADDR_START field. + HP_APM_REGION8_ADDR_START_REGION8_ADDR_START_Msk = 0xffffffff + + // REGION8_ADDR_END: Region address register + // Position of REGION8_ADDR_END field. + HP_APM_REGION8_ADDR_END_REGION8_ADDR_END_Pos = 0x0 + // Bit mask of REGION8_ADDR_END field. + HP_APM_REGION8_ADDR_END_REGION8_ADDR_END_Msk = 0xffffffff + + // REGION8_PMS_ATTR: Region access authority attribute register + // Position of REGION8_R0_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION8_R0_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_X_Msk = 0x1 + // Bit REGION8_R0_PMS_X. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_X = 0x1 + // Position of REGION8_R0_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION8_R0_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_W_Msk = 0x2 + // Bit REGION8_R0_PMS_W. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_W = 0x2 + // Position of REGION8_R0_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION8_R0_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_R_Msk = 0x4 + // Bit REGION8_R0_PMS_R. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_R = 0x4 + // Position of REGION8_R1_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION8_R1_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_X_Msk = 0x10 + // Bit REGION8_R1_PMS_X. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_X = 0x10 + // Position of REGION8_R1_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION8_R1_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_W_Msk = 0x20 + // Bit REGION8_R1_PMS_W. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_W = 0x20 + // Position of REGION8_R1_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION8_R1_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_R_Msk = 0x40 + // Bit REGION8_R1_PMS_R. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_R = 0x40 + // Position of REGION8_R2_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION8_R2_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_X_Msk = 0x100 + // Bit REGION8_R2_PMS_X. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_X = 0x100 + // Position of REGION8_R2_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION8_R2_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_W_Msk = 0x200 + // Bit REGION8_R2_PMS_W. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_W = 0x200 + // Position of REGION8_R2_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_R_Pos = 0xa + // Bit mask of REGION8_R2_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_R_Msk = 0x400 + // Bit REGION8_R2_PMS_R. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_R = 0x400 + + // REGION9_ADDR_START: Region address register + // Position of REGION9_ADDR_START field. + HP_APM_REGION9_ADDR_START_REGION9_ADDR_START_Pos = 0x0 + // Bit mask of REGION9_ADDR_START field. + HP_APM_REGION9_ADDR_START_REGION9_ADDR_START_Msk = 0xffffffff + + // REGION9_ADDR_END: Region address register + // Position of REGION9_ADDR_END field. + HP_APM_REGION9_ADDR_END_REGION9_ADDR_END_Pos = 0x0 + // Bit mask of REGION9_ADDR_END field. + HP_APM_REGION9_ADDR_END_REGION9_ADDR_END_Msk = 0xffffffff + + // REGION9_PMS_ATTR: Region access authority attribute register + // Position of REGION9_R0_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION9_R0_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_X_Msk = 0x1 + // Bit REGION9_R0_PMS_X. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_X = 0x1 + // Position of REGION9_R0_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION9_R0_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_W_Msk = 0x2 + // Bit REGION9_R0_PMS_W. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_W = 0x2 + // Position of REGION9_R0_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION9_R0_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_R_Msk = 0x4 + // Bit REGION9_R0_PMS_R. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_R = 0x4 + // Position of REGION9_R1_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION9_R1_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_X_Msk = 0x10 + // Bit REGION9_R1_PMS_X. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_X = 0x10 + // Position of REGION9_R1_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION9_R1_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_W_Msk = 0x20 + // Bit REGION9_R1_PMS_W. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_W = 0x20 + // Position of REGION9_R1_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION9_R1_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_R_Msk = 0x40 + // Bit REGION9_R1_PMS_R. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_R = 0x40 + // Position of REGION9_R2_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION9_R2_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_X_Msk = 0x100 + // Bit REGION9_R2_PMS_X. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_X = 0x100 + // Position of REGION9_R2_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION9_R2_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_W_Msk = 0x200 + // Bit REGION9_R2_PMS_W. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_W = 0x200 + // Position of REGION9_R2_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_R_Pos = 0xa + // Bit mask of REGION9_R2_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_R_Msk = 0x400 + // Bit REGION9_R2_PMS_R. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_R = 0x400 + + // REGION10_ADDR_START: Region address register + // Position of REGION10_ADDR_START field. + HP_APM_REGION10_ADDR_START_REGION10_ADDR_START_Pos = 0x0 + // Bit mask of REGION10_ADDR_START field. + HP_APM_REGION10_ADDR_START_REGION10_ADDR_START_Msk = 0xffffffff + + // REGION10_ADDR_END: Region address register + // Position of REGION10_ADDR_END field. + HP_APM_REGION10_ADDR_END_REGION10_ADDR_END_Pos = 0x0 + // Bit mask of REGION10_ADDR_END field. + HP_APM_REGION10_ADDR_END_REGION10_ADDR_END_Msk = 0xffffffff + + // REGION10_PMS_ATTR: Region access authority attribute register + // Position of REGION10_R0_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION10_R0_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_X_Msk = 0x1 + // Bit REGION10_R0_PMS_X. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_X = 0x1 + // Position of REGION10_R0_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION10_R0_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_W_Msk = 0x2 + // Bit REGION10_R0_PMS_W. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_W = 0x2 + // Position of REGION10_R0_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION10_R0_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_R_Msk = 0x4 + // Bit REGION10_R0_PMS_R. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_R = 0x4 + // Position of REGION10_R1_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION10_R1_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_X_Msk = 0x10 + // Bit REGION10_R1_PMS_X. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_X = 0x10 + // Position of REGION10_R1_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION10_R1_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_W_Msk = 0x20 + // Bit REGION10_R1_PMS_W. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_W = 0x20 + // Position of REGION10_R1_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION10_R1_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_R_Msk = 0x40 + // Bit REGION10_R1_PMS_R. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_R = 0x40 + // Position of REGION10_R2_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION10_R2_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_X_Msk = 0x100 + // Bit REGION10_R2_PMS_X. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_X = 0x100 + // Position of REGION10_R2_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION10_R2_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_W_Msk = 0x200 + // Bit REGION10_R2_PMS_W. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_W = 0x200 + // Position of REGION10_R2_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_R_Pos = 0xa + // Bit mask of REGION10_R2_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_R_Msk = 0x400 + // Bit REGION10_R2_PMS_R. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_R = 0x400 + + // REGION11_ADDR_START: Region address register + // Position of REGION11_ADDR_START field. + HP_APM_REGION11_ADDR_START_REGION11_ADDR_START_Pos = 0x0 + // Bit mask of REGION11_ADDR_START field. + HP_APM_REGION11_ADDR_START_REGION11_ADDR_START_Msk = 0xffffffff + + // REGION11_ADDR_END: Region address register + // Position of REGION11_ADDR_END field. + HP_APM_REGION11_ADDR_END_REGION11_ADDR_END_Pos = 0x0 + // Bit mask of REGION11_ADDR_END field. + HP_APM_REGION11_ADDR_END_REGION11_ADDR_END_Msk = 0xffffffff + + // REGION11_PMS_ATTR: Region access authority attribute register + // Position of REGION11_R0_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION11_R0_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_X_Msk = 0x1 + // Bit REGION11_R0_PMS_X. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_X = 0x1 + // Position of REGION11_R0_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION11_R0_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_W_Msk = 0x2 + // Bit REGION11_R0_PMS_W. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_W = 0x2 + // Position of REGION11_R0_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION11_R0_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_R_Msk = 0x4 + // Bit REGION11_R0_PMS_R. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_R = 0x4 + // Position of REGION11_R1_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION11_R1_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_X_Msk = 0x10 + // Bit REGION11_R1_PMS_X. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_X = 0x10 + // Position of REGION11_R1_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION11_R1_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_W_Msk = 0x20 + // Bit REGION11_R1_PMS_W. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_W = 0x20 + // Position of REGION11_R1_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION11_R1_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_R_Msk = 0x40 + // Bit REGION11_R1_PMS_R. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_R = 0x40 + // Position of REGION11_R2_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION11_R2_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_X_Msk = 0x100 + // Bit REGION11_R2_PMS_X. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_X = 0x100 + // Position of REGION11_R2_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION11_R2_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_W_Msk = 0x200 + // Bit REGION11_R2_PMS_W. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_W = 0x200 + // Position of REGION11_R2_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_R_Pos = 0xa + // Bit mask of REGION11_R2_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_R_Msk = 0x400 + // Bit REGION11_R2_PMS_R. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_R = 0x400 + + // REGION12_ADDR_START: Region address register + // Position of REGION12_ADDR_START field. + HP_APM_REGION12_ADDR_START_REGION12_ADDR_START_Pos = 0x0 + // Bit mask of REGION12_ADDR_START field. + HP_APM_REGION12_ADDR_START_REGION12_ADDR_START_Msk = 0xffffffff + + // REGION12_ADDR_END: Region address register + // Position of REGION12_ADDR_END field. + HP_APM_REGION12_ADDR_END_REGION12_ADDR_END_Pos = 0x0 + // Bit mask of REGION12_ADDR_END field. + HP_APM_REGION12_ADDR_END_REGION12_ADDR_END_Msk = 0xffffffff + + // REGION12_PMS_ATTR: Region access authority attribute register + // Position of REGION12_R0_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION12_R0_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_X_Msk = 0x1 + // Bit REGION12_R0_PMS_X. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_X = 0x1 + // Position of REGION12_R0_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION12_R0_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_W_Msk = 0x2 + // Bit REGION12_R0_PMS_W. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_W = 0x2 + // Position of REGION12_R0_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION12_R0_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_R_Msk = 0x4 + // Bit REGION12_R0_PMS_R. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_R = 0x4 + // Position of REGION12_R1_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION12_R1_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_X_Msk = 0x10 + // Bit REGION12_R1_PMS_X. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_X = 0x10 + // Position of REGION12_R1_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION12_R1_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_W_Msk = 0x20 + // Bit REGION12_R1_PMS_W. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_W = 0x20 + // Position of REGION12_R1_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION12_R1_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_R_Msk = 0x40 + // Bit REGION12_R1_PMS_R. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_R = 0x40 + // Position of REGION12_R2_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION12_R2_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_X_Msk = 0x100 + // Bit REGION12_R2_PMS_X. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_X = 0x100 + // Position of REGION12_R2_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION12_R2_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_W_Msk = 0x200 + // Bit REGION12_R2_PMS_W. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_W = 0x200 + // Position of REGION12_R2_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_R_Pos = 0xa + // Bit mask of REGION12_R2_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_R_Msk = 0x400 + // Bit REGION12_R2_PMS_R. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_R = 0x400 + + // REGION13_ADDR_START: Region address register + // Position of REGION13_ADDR_START field. + HP_APM_REGION13_ADDR_START_REGION13_ADDR_START_Pos = 0x0 + // Bit mask of REGION13_ADDR_START field. + HP_APM_REGION13_ADDR_START_REGION13_ADDR_START_Msk = 0xffffffff + + // REGION13_ADDR_END: Region address register + // Position of REGION13_ADDR_END field. + HP_APM_REGION13_ADDR_END_REGION13_ADDR_END_Pos = 0x0 + // Bit mask of REGION13_ADDR_END field. + HP_APM_REGION13_ADDR_END_REGION13_ADDR_END_Msk = 0xffffffff + + // REGION13_PMS_ATTR: Region access authority attribute register + // Position of REGION13_R0_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION13_R0_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_X_Msk = 0x1 + // Bit REGION13_R0_PMS_X. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_X = 0x1 + // Position of REGION13_R0_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION13_R0_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_W_Msk = 0x2 + // Bit REGION13_R0_PMS_W. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_W = 0x2 + // Position of REGION13_R0_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION13_R0_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_R_Msk = 0x4 + // Bit REGION13_R0_PMS_R. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_R = 0x4 + // Position of REGION13_R1_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION13_R1_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_X_Msk = 0x10 + // Bit REGION13_R1_PMS_X. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_X = 0x10 + // Position of REGION13_R1_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION13_R1_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_W_Msk = 0x20 + // Bit REGION13_R1_PMS_W. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_W = 0x20 + // Position of REGION13_R1_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION13_R1_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_R_Msk = 0x40 + // Bit REGION13_R1_PMS_R. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_R = 0x40 + // Position of REGION13_R2_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION13_R2_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_X_Msk = 0x100 + // Bit REGION13_R2_PMS_X. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_X = 0x100 + // Position of REGION13_R2_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION13_R2_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_W_Msk = 0x200 + // Bit REGION13_R2_PMS_W. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_W = 0x200 + // Position of REGION13_R2_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_R_Pos = 0xa + // Bit mask of REGION13_R2_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_R_Msk = 0x400 + // Bit REGION13_R2_PMS_R. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_R = 0x400 + + // REGION14_ADDR_START: Region address register + // Position of REGION14_ADDR_START field. + HP_APM_REGION14_ADDR_START_REGION14_ADDR_START_Pos = 0x0 + // Bit mask of REGION14_ADDR_START field. + HP_APM_REGION14_ADDR_START_REGION14_ADDR_START_Msk = 0xffffffff + + // REGION14_ADDR_END: Region address register + // Position of REGION14_ADDR_END field. + HP_APM_REGION14_ADDR_END_REGION14_ADDR_END_Pos = 0x0 + // Bit mask of REGION14_ADDR_END field. + HP_APM_REGION14_ADDR_END_REGION14_ADDR_END_Msk = 0xffffffff + + // REGION14_PMS_ATTR: Region access authority attribute register + // Position of REGION14_R0_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION14_R0_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_X_Msk = 0x1 + // Bit REGION14_R0_PMS_X. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_X = 0x1 + // Position of REGION14_R0_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION14_R0_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_W_Msk = 0x2 + // Bit REGION14_R0_PMS_W. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_W = 0x2 + // Position of REGION14_R0_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION14_R0_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_R_Msk = 0x4 + // Bit REGION14_R0_PMS_R. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_R = 0x4 + // Position of REGION14_R1_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION14_R1_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_X_Msk = 0x10 + // Bit REGION14_R1_PMS_X. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_X = 0x10 + // Position of REGION14_R1_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION14_R1_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_W_Msk = 0x20 + // Bit REGION14_R1_PMS_W. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_W = 0x20 + // Position of REGION14_R1_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION14_R1_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_R_Msk = 0x40 + // Bit REGION14_R1_PMS_R. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_R = 0x40 + // Position of REGION14_R2_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION14_R2_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_X_Msk = 0x100 + // Bit REGION14_R2_PMS_X. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_X = 0x100 + // Position of REGION14_R2_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION14_R2_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_W_Msk = 0x200 + // Bit REGION14_R2_PMS_W. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_W = 0x200 + // Position of REGION14_R2_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_R_Pos = 0xa + // Bit mask of REGION14_R2_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_R_Msk = 0x400 + // Bit REGION14_R2_PMS_R. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_R = 0x400 + + // REGION15_ADDR_START: Region address register + // Position of REGION15_ADDR_START field. + HP_APM_REGION15_ADDR_START_REGION15_ADDR_START_Pos = 0x0 + // Bit mask of REGION15_ADDR_START field. + HP_APM_REGION15_ADDR_START_REGION15_ADDR_START_Msk = 0xffffffff + + // REGION15_ADDR_END: Region address register + // Position of REGION15_ADDR_END field. + HP_APM_REGION15_ADDR_END_REGION15_ADDR_END_Pos = 0x0 + // Bit mask of REGION15_ADDR_END field. + HP_APM_REGION15_ADDR_END_REGION15_ADDR_END_Msk = 0xffffffff + + // REGION15_PMS_ATTR: Region access authority attribute register + // Position of REGION15_R0_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION15_R0_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_X_Msk = 0x1 + // Bit REGION15_R0_PMS_X. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_X = 0x1 + // Position of REGION15_R0_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION15_R0_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_W_Msk = 0x2 + // Bit REGION15_R0_PMS_W. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_W = 0x2 + // Position of REGION15_R0_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION15_R0_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_R_Msk = 0x4 + // Bit REGION15_R0_PMS_R. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_R = 0x4 + // Position of REGION15_R1_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION15_R1_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_X_Msk = 0x10 + // Bit REGION15_R1_PMS_X. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_X = 0x10 + // Position of REGION15_R1_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION15_R1_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_W_Msk = 0x20 + // Bit REGION15_R1_PMS_W. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_W = 0x20 + // Position of REGION15_R1_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION15_R1_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_R_Msk = 0x40 + // Bit REGION15_R1_PMS_R. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_R = 0x40 + // Position of REGION15_R2_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION15_R2_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_X_Msk = 0x100 + // Bit REGION15_R2_PMS_X. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_X = 0x100 + // Position of REGION15_R2_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION15_R2_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_W_Msk = 0x200 + // Bit REGION15_R2_PMS_W. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_W = 0x200 + // Position of REGION15_R2_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_R_Pos = 0xa + // Bit mask of REGION15_R2_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_R_Msk = 0x400 + // Bit REGION15_R2_PMS_R. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_R = 0x400 + + // FUNC_CTRL: PMS function control register + // Position of M0_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Pos = 0x0 + // Bit mask of M0_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Msk = 0x1 + // Bit M0_PMS_FUNC_EN. + HP_APM_FUNC_CTRL_M0_PMS_FUNC_EN = 0x1 + // Position of M1_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M1_PMS_FUNC_EN_Pos = 0x1 + // Bit mask of M1_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M1_PMS_FUNC_EN_Msk = 0x2 + // Bit M1_PMS_FUNC_EN. + HP_APM_FUNC_CTRL_M1_PMS_FUNC_EN = 0x2 + // Position of M2_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M2_PMS_FUNC_EN_Pos = 0x2 + // Bit mask of M2_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M2_PMS_FUNC_EN_Msk = 0x4 + // Bit M2_PMS_FUNC_EN. + HP_APM_FUNC_CTRL_M2_PMS_FUNC_EN = 0x4 + // Position of M3_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M3_PMS_FUNC_EN_Pos = 0x3 + // Bit mask of M3_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M3_PMS_FUNC_EN_Msk = 0x8 + // Bit M3_PMS_FUNC_EN. + HP_APM_FUNC_CTRL_M3_PMS_FUNC_EN = 0x8 + + // M0_STATUS: M0 status register + // Position of M0_EXCEPTION_STATUS field. + HP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M0_EXCEPTION_STATUS field. + HP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Msk = 0x3 + + // M0_STATUS_CLR: M0 status clear register + // Position of M0_REGION_STATUS_CLR field. + HP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M0_REGION_STATUS_CLR field. + HP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Msk = 0x1 + // Bit M0_REGION_STATUS_CLR. + HP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR = 0x1 + + // M0_EXCEPTION_INFO0: M0 exception_info0 register + // Position of M0_EXCEPTION_REGION field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M0_EXCEPTION_REGION field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Msk = 0xffff + // Position of M0_EXCEPTION_MODE field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M0_EXCEPTION_MODE field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Msk = 0x30000 + // Position of M0_EXCEPTION_ID field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M0_EXCEPTION_ID field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Msk = 0x7c0000 + + // M0_EXCEPTION_INFO1: M0 exception_info1 register + // Position of M0_EXCEPTION_ADDR field. + HP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M0_EXCEPTION_ADDR field. + HP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Msk = 0xffffffff + + // M1_STATUS: M1 status register + // Position of M1_EXCEPTION_STATUS field. + HP_APM_M1_STATUS_M1_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M1_EXCEPTION_STATUS field. + HP_APM_M1_STATUS_M1_EXCEPTION_STATUS_Msk = 0x3 + + // M1_STATUS_CLR: M1 status clear register + // Position of M1_REGION_STATUS_CLR field. + HP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M1_REGION_STATUS_CLR field. + HP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR_Msk = 0x1 + // Bit M1_REGION_STATUS_CLR. + HP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR = 0x1 + + // M1_EXCEPTION_INFO0: M1 exception_info0 register + // Position of M1_EXCEPTION_REGION field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M1_EXCEPTION_REGION field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_REGION_Msk = 0xffff + // Position of M1_EXCEPTION_MODE field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M1_EXCEPTION_MODE field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_MODE_Msk = 0x30000 + // Position of M1_EXCEPTION_ID field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M1_EXCEPTION_ID field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_ID_Msk = 0x7c0000 + + // M1_EXCEPTION_INFO1: M1 exception_info1 register + // Position of M1_EXCEPTION_ADDR field. + HP_APM_M1_EXCEPTION_INFO1_M1_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M1_EXCEPTION_ADDR field. + HP_APM_M1_EXCEPTION_INFO1_M1_EXCEPTION_ADDR_Msk = 0xffffffff + + // M2_STATUS: M2 status register + // Position of M2_EXCEPTION_STATUS field. + HP_APM_M2_STATUS_M2_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M2_EXCEPTION_STATUS field. + HP_APM_M2_STATUS_M2_EXCEPTION_STATUS_Msk = 0x3 + + // M2_STATUS_CLR: M2 status clear register + // Position of M2_REGION_STATUS_CLR field. + HP_APM_M2_STATUS_CLR_M2_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M2_REGION_STATUS_CLR field. + HP_APM_M2_STATUS_CLR_M2_REGION_STATUS_CLR_Msk = 0x1 + // Bit M2_REGION_STATUS_CLR. + HP_APM_M2_STATUS_CLR_M2_REGION_STATUS_CLR = 0x1 + + // M2_EXCEPTION_INFO0: M2 exception_info0 register + // Position of M2_EXCEPTION_REGION field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M2_EXCEPTION_REGION field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_REGION_Msk = 0xffff + // Position of M2_EXCEPTION_MODE field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M2_EXCEPTION_MODE field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_MODE_Msk = 0x30000 + // Position of M2_EXCEPTION_ID field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M2_EXCEPTION_ID field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_ID_Msk = 0x7c0000 + + // M2_EXCEPTION_INFO1: M2 exception_info1 register + // Position of M2_EXCEPTION_ADDR field. + HP_APM_M2_EXCEPTION_INFO1_M2_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M2_EXCEPTION_ADDR field. + HP_APM_M2_EXCEPTION_INFO1_M2_EXCEPTION_ADDR_Msk = 0xffffffff + + // M3_STATUS: M3 status register + // Position of M3_EXCEPTION_STATUS field. + HP_APM_M3_STATUS_M3_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M3_EXCEPTION_STATUS field. + HP_APM_M3_STATUS_M3_EXCEPTION_STATUS_Msk = 0x3 + + // M3_STATUS_CLR: M3 status clear register + // Position of M3_REGION_STATUS_CLR field. + HP_APM_M3_STATUS_CLR_M3_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M3_REGION_STATUS_CLR field. + HP_APM_M3_STATUS_CLR_M3_REGION_STATUS_CLR_Msk = 0x1 + // Bit M3_REGION_STATUS_CLR. + HP_APM_M3_STATUS_CLR_M3_REGION_STATUS_CLR = 0x1 + + // M3_EXCEPTION_INFO0: M3 exception_info0 register + // Position of M3_EXCEPTION_REGION field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M3_EXCEPTION_REGION field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_REGION_Msk = 0xffff + // Position of M3_EXCEPTION_MODE field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M3_EXCEPTION_MODE field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_MODE_Msk = 0x30000 + // Position of M3_EXCEPTION_ID field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M3_EXCEPTION_ID field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_ID_Msk = 0x7c0000 + + // M3_EXCEPTION_INFO1: M3 exception_info1 register + // Position of M3_EXCEPTION_ADDR field. + HP_APM_M3_EXCEPTION_INFO1_M3_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M3_EXCEPTION_ADDR field. + HP_APM_M3_EXCEPTION_INFO1_M3_EXCEPTION_ADDR_Msk = 0xffffffff + + // INT_EN: APM interrupt enable register + // Position of M0_APM_INT_EN field. + HP_APM_INT_EN_M0_APM_INT_EN_Pos = 0x0 + // Bit mask of M0_APM_INT_EN field. + HP_APM_INT_EN_M0_APM_INT_EN_Msk = 0x1 + // Bit M0_APM_INT_EN. + HP_APM_INT_EN_M0_APM_INT_EN = 0x1 + // Position of M1_APM_INT_EN field. + HP_APM_INT_EN_M1_APM_INT_EN_Pos = 0x1 + // Bit mask of M1_APM_INT_EN field. + HP_APM_INT_EN_M1_APM_INT_EN_Msk = 0x2 + // Bit M1_APM_INT_EN. + HP_APM_INT_EN_M1_APM_INT_EN = 0x2 + // Position of M2_APM_INT_EN field. + HP_APM_INT_EN_M2_APM_INT_EN_Pos = 0x2 + // Bit mask of M2_APM_INT_EN field. + HP_APM_INT_EN_M2_APM_INT_EN_Msk = 0x4 + // Bit M2_APM_INT_EN. + HP_APM_INT_EN_M2_APM_INT_EN = 0x4 + // Position of M3_APM_INT_EN field. + HP_APM_INT_EN_M3_APM_INT_EN_Pos = 0x3 + // Bit mask of M3_APM_INT_EN field. + HP_APM_INT_EN_M3_APM_INT_EN_Msk = 0x8 + // Bit M3_APM_INT_EN. + HP_APM_INT_EN_M3_APM_INT_EN = 0x8 + + // CLOCK_GATE: clock gating register + // Position of CLK_EN field. + HP_APM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + HP_APM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + HP_APM_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + HP_APM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + HP_APM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for HP_SYS: High-Power System +const ( + // EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + // Position of ENABLE_SPI_MANUAL_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Pos = 0x0 + // Bit mask of ENABLE_SPI_MANUAL_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Msk = 0x1 + // Bit ENABLE_SPI_MANUAL_ENCRYPT. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT = 0x1 + // Position of ENABLE_DOWNLOAD_DB_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Pos = 0x1 + // Bit mask of ENABLE_DOWNLOAD_DB_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Msk = 0x2 + // Bit ENABLE_DOWNLOAD_DB_ENCRYPT. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT = 0x2 + // Position of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Pos = 0x2 + // Bit mask of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Msk = 0x4 + // Bit ENABLE_DOWNLOAD_G0CB_DECRYPT. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT = 0x4 + // Position of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x3 + // Bit mask of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x8 + // Bit ENABLE_DOWNLOAD_MANUAL_ENCRYPT. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT = 0x8 + + // SRAM_USAGE_CONF: HP memory usage configuration register + // Position of CACHE_USAGE field. + HP_SYS_SRAM_USAGE_CONF_CACHE_USAGE_Pos = 0x0 + // Bit mask of CACHE_USAGE field. + HP_SYS_SRAM_USAGE_CONF_CACHE_USAGE_Msk = 0x1 + // Bit CACHE_USAGE. + HP_SYS_SRAM_USAGE_CONF_CACHE_USAGE = 0x1 + // Position of SRAM_USAGE field. + HP_SYS_SRAM_USAGE_CONF_SRAM_USAGE_Pos = 0x8 + // Bit mask of SRAM_USAGE field. + HP_SYS_SRAM_USAGE_CONF_SRAM_USAGE_Msk = 0xf00 + // Position of MAC_DUMP_ALLOC field. + HP_SYS_SRAM_USAGE_CONF_MAC_DUMP_ALLOC_Pos = 0x10 + // Bit mask of MAC_DUMP_ALLOC field. + HP_SYS_SRAM_USAGE_CONF_MAC_DUMP_ALLOC_Msk = 0x10000 + // Bit MAC_DUMP_ALLOC. + HP_SYS_SRAM_USAGE_CONF_MAC_DUMP_ALLOC = 0x10000 + + // SEC_DPA_CONF: HP anti-DPA security configuration register + // Position of SEC_DPA_LEVEL field. + HP_SYS_SEC_DPA_CONF_SEC_DPA_LEVEL_Pos = 0x0 + // Bit mask of SEC_DPA_LEVEL field. + HP_SYS_SEC_DPA_CONF_SEC_DPA_LEVEL_Msk = 0x3 + // Position of SEC_DPA_CFG_SEL field. + HP_SYS_SEC_DPA_CONF_SEC_DPA_CFG_SEL_Pos = 0x2 + // Bit mask of SEC_DPA_CFG_SEL field. + HP_SYS_SEC_DPA_CONF_SEC_DPA_CFG_SEL_Msk = 0x4 + // Bit SEC_DPA_CFG_SEL. + HP_SYS_SEC_DPA_CONF_SEC_DPA_CFG_SEL = 0x4 + + // CPU_PERI_TIMEOUT_CONF: CPU_PERI_TIMEOUT configuration register + // Position of CPU_PERI_TIMEOUT_THRES field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_THRES_Pos = 0x0 + // Bit mask of CPU_PERI_TIMEOUT_THRES field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_THRES_Msk = 0xffff + // Position of CPU_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR_Pos = 0x10 + // Bit mask of CPU_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR_Msk = 0x10000 + // Bit CPU_PERI_TIMEOUT_INT_CLEAR. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR = 0x10000 + // Position of CPU_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN_Pos = 0x11 + // Bit mask of CPU_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN_Msk = 0x20000 + // Bit CPU_PERI_TIMEOUT_PROTECT_EN. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN = 0x20000 + + // CPU_PERI_TIMEOUT_ADDR: CPU_PERI_TIMEOUT_ADDR register + // Position of CPU_PERI_TIMEOUT_ADDR field. + HP_SYS_CPU_PERI_TIMEOUT_ADDR_CPU_PERI_TIMEOUT_ADDR_Pos = 0x0 + // Bit mask of CPU_PERI_TIMEOUT_ADDR field. + HP_SYS_CPU_PERI_TIMEOUT_ADDR_CPU_PERI_TIMEOUT_ADDR_Msk = 0xffffffff + + // CPU_PERI_TIMEOUT_UID: CPU_PERI_TIMEOUT_UID register + // Position of CPU_PERI_TIMEOUT_UID field. + HP_SYS_CPU_PERI_TIMEOUT_UID_CPU_PERI_TIMEOUT_UID_Pos = 0x0 + // Bit mask of CPU_PERI_TIMEOUT_UID field. + HP_SYS_CPU_PERI_TIMEOUT_UID_CPU_PERI_TIMEOUT_UID_Msk = 0x7f + + // HP_PERI_TIMEOUT_CONF: HP_PERI_TIMEOUT configuration register + // Position of HP_PERI_TIMEOUT_THRES field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_THRES_Pos = 0x0 + // Bit mask of HP_PERI_TIMEOUT_THRES field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_THRES_Msk = 0xffff + // Position of HP_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR_Pos = 0x10 + // Bit mask of HP_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR_Msk = 0x10000 + // Bit HP_PERI_TIMEOUT_INT_CLEAR. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR = 0x10000 + // Position of HP_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN_Pos = 0x11 + // Bit mask of HP_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN_Msk = 0x20000 + // Bit HP_PERI_TIMEOUT_PROTECT_EN. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN = 0x20000 + + // HP_PERI_TIMEOUT_ADDR: HP_PERI_TIMEOUT_ADDR register + // Position of HP_PERI_TIMEOUT_ADDR field. + HP_SYS_HP_PERI_TIMEOUT_ADDR_HP_PERI_TIMEOUT_ADDR_Pos = 0x0 + // Bit mask of HP_PERI_TIMEOUT_ADDR field. + HP_SYS_HP_PERI_TIMEOUT_ADDR_HP_PERI_TIMEOUT_ADDR_Msk = 0xffffffff + + // HP_PERI_TIMEOUT_UID: HP_PERI_TIMEOUT_UID register + // Position of HP_PERI_TIMEOUT_UID field. + HP_SYS_HP_PERI_TIMEOUT_UID_HP_PERI_TIMEOUT_UID_Pos = 0x0 + // Bit mask of HP_PERI_TIMEOUT_UID field. + HP_SYS_HP_PERI_TIMEOUT_UID_HP_PERI_TIMEOUT_UID_Msk = 0x7f + + // MODEM_PERI_TIMEOUT_CONF: MODEM_PERI_TIMEOUT configuration register + // Position of MODEM_PERI_TIMEOUT_THRES field. + HP_SYS_MODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_THRES_Pos = 0x0 + // Bit mask of MODEM_PERI_TIMEOUT_THRES field. + HP_SYS_MODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_THRES_Msk = 0xffff + // Position of MODEM_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_MODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_INT_CLEAR_Pos = 0x10 + // Bit mask of MODEM_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_MODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_INT_CLEAR_Msk = 0x10000 + // Bit MODEM_PERI_TIMEOUT_INT_CLEAR. + HP_SYS_MODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_INT_CLEAR = 0x10000 + // Position of MODEM_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_MODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_PROTECT_EN_Pos = 0x11 + // Bit mask of MODEM_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_MODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_PROTECT_EN_Msk = 0x20000 + // Bit MODEM_PERI_TIMEOUT_PROTECT_EN. + HP_SYS_MODEM_PERI_TIMEOUT_CONF_MODEM_PERI_TIMEOUT_PROTECT_EN = 0x20000 + + // MODEM_PERI_TIMEOUT_ADDR: MODEM_PERI_TIMEOUT_ADDR register + // Position of MODEM_PERI_TIMEOUT_ADDR field. + HP_SYS_MODEM_PERI_TIMEOUT_ADDR_MODEM_PERI_TIMEOUT_ADDR_Pos = 0x0 + // Bit mask of MODEM_PERI_TIMEOUT_ADDR field. + HP_SYS_MODEM_PERI_TIMEOUT_ADDR_MODEM_PERI_TIMEOUT_ADDR_Msk = 0xffffffff + + // MODEM_PERI_TIMEOUT_UID: MODEM_PERI_TIMEOUT_UID register + // Position of MODEM_PERI_TIMEOUT_UID field. + HP_SYS_MODEM_PERI_TIMEOUT_UID_MODEM_PERI_TIMEOUT_UID_Pos = 0x0 + // Bit mask of MODEM_PERI_TIMEOUT_UID field. + HP_SYS_MODEM_PERI_TIMEOUT_UID_MODEM_PERI_TIMEOUT_UID_Msk = 0x7f + + // SDIO_CTRL: SDIO Control configuration register + // Position of DIS_SDIO_PROB field. + HP_SYS_SDIO_CTRL_DIS_SDIO_PROB_Pos = 0x0 + // Bit mask of DIS_SDIO_PROB field. + HP_SYS_SDIO_CTRL_DIS_SDIO_PROB_Msk = 0x1 + // Bit DIS_SDIO_PROB. + HP_SYS_SDIO_CTRL_DIS_SDIO_PROB = 0x1 + // Position of SDIO_WIN_ACCESS_EN field. + HP_SYS_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Pos = 0x1 + // Bit mask of SDIO_WIN_ACCESS_EN field. + HP_SYS_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Msk = 0x2 + // Bit SDIO_WIN_ACCESS_EN. + HP_SYS_SDIO_CTRL_SDIO_WIN_ACCESS_EN = 0x2 + + // RETENTION_CONF: Retention configuration register + // Position of RETENTION_DISABLE field. + HP_SYS_RETENTION_CONF_RETENTION_DISABLE_Pos = 0x0 + // Bit mask of RETENTION_DISABLE field. + HP_SYS_RETENTION_CONF_RETENTION_DISABLE_Msk = 0x1 + // Bit RETENTION_DISABLE. + HP_SYS_RETENTION_CONF_RETENTION_DISABLE = 0x1 + + // ROM_TABLE_LOCK: Rom-Table lock register + // Position of ROM_TABLE_LOCK field. + HP_SYS_ROM_TABLE_LOCK_ROM_TABLE_LOCK_Pos = 0x0 + // Bit mask of ROM_TABLE_LOCK field. + HP_SYS_ROM_TABLE_LOCK_ROM_TABLE_LOCK_Msk = 0x1 + // Bit ROM_TABLE_LOCK. + HP_SYS_ROM_TABLE_LOCK_ROM_TABLE_LOCK = 0x1 + + // ROM_TABLE: Rom-Table register + // Position of ROM_TABLE field. + HP_SYS_ROM_TABLE_ROM_TABLE_Pos = 0x0 + // Bit mask of ROM_TABLE field. + HP_SYS_ROM_TABLE_ROM_TABLE_Msk = 0xffffffff + + // CORE_DEBUG_RUNSTALL_CONF: Core Debug runstall configure register + // Position of CORE_DEBUG_RUNSTALL_ENABLE field. + HP_SYS_CORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE_Pos = 0x0 + // Bit mask of CORE_DEBUG_RUNSTALL_ENABLE field. + HP_SYS_CORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE_Msk = 0x1 + // Bit CORE_DEBUG_RUNSTALL_ENABLE. + HP_SYS_CORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE = 0x1 + + // MEM_TEST_CONF: MEM_TEST configuration register + // Position of HP_MEM_WPULSE field. + HP_SYS_MEM_TEST_CONF_HP_MEM_WPULSE_Pos = 0x0 + // Bit mask of HP_MEM_WPULSE field. + HP_SYS_MEM_TEST_CONF_HP_MEM_WPULSE_Msk = 0x7 + // Position of HP_MEM_WA field. + HP_SYS_MEM_TEST_CONF_HP_MEM_WA_Pos = 0x3 + // Bit mask of HP_MEM_WA field. + HP_SYS_MEM_TEST_CONF_HP_MEM_WA_Msk = 0x38 + // Position of HP_MEM_RA field. + HP_SYS_MEM_TEST_CONF_HP_MEM_RA_Pos = 0x6 + // Bit mask of HP_MEM_RA field. + HP_SYS_MEM_TEST_CONF_HP_MEM_RA_Msk = 0xc0 + + // RND_ECO: redcy eco register. + // Position of REDCY_ENA field. + HP_SYS_RND_ECO_REDCY_ENA_Pos = 0x0 + // Bit mask of REDCY_ENA field. + HP_SYS_RND_ECO_REDCY_ENA_Msk = 0x1 + // Bit REDCY_ENA. + HP_SYS_RND_ECO_REDCY_ENA = 0x1 + // Position of REDCY_RESULT field. + HP_SYS_RND_ECO_REDCY_RESULT_Pos = 0x1 + // Bit mask of REDCY_RESULT field. + HP_SYS_RND_ECO_REDCY_RESULT_Msk = 0x2 + // Bit REDCY_RESULT. + HP_SYS_RND_ECO_REDCY_RESULT = 0x2 + + // RND_ECO_LOW: redcy eco low register. + // Position of REDCY_LOW field. + HP_SYS_RND_ECO_LOW_REDCY_LOW_Pos = 0x0 + // Bit mask of REDCY_LOW field. + HP_SYS_RND_ECO_LOW_REDCY_LOW_Msk = 0xffffffff + + // RND_ECO_HIGH: redcy eco high register. + // Position of REDCY_HIGH field. + HP_SYS_RND_ECO_HIGH_REDCY_HIGH_Pos = 0x0 + // Bit mask of REDCY_HIGH field. + HP_SYS_RND_ECO_HIGH_REDCY_HIGH_Msk = 0xffffffff + + // CLOCK_GATE: HP-SYSTEM clock gating configure register + // Position of CLK_EN field. + HP_SYS_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + HP_SYS_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + HP_SYS_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Date register. + // Position of DATE field. + HP_SYS_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + HP_SYS_DATE_DATE_Msk = 0xfffffff +) + +// Constants for I2C0: I2C (Inter-Integrated Circuit) Controller 0 +const ( + // SCL_LOW_PERIOD: Configures the low level width of the SCL Clock + // Position of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x1ff + + // CTR: Transmission setting + // Position of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + I2C_CTR_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + I2C_CTR_SCL_FORCE_OUT = 0x2 + // Position of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2 + // Bit mask of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4 + // Bit SAMPLE_SCL_LEVEL. + I2C_CTR_SAMPLE_SCL_LEVEL = 0x4 + // Position of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Pos = 0x3 + // Bit mask of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Msk = 0x8 + // Bit RX_FULL_ACK_LEVEL. + I2C_CTR_RX_FULL_ACK_LEVEL = 0x8 + // Position of MS_MODE field. + I2C_CTR_MS_MODE_Pos = 0x4 + // Bit mask of MS_MODE field. + I2C_CTR_MS_MODE_Msk = 0x10 + // Bit MS_MODE. + I2C_CTR_MS_MODE = 0x10 + // Position of TRANS_START field. + I2C_CTR_TRANS_START_Pos = 0x5 + // Bit mask of TRANS_START field. + I2C_CTR_TRANS_START_Msk = 0x20 + // Bit TRANS_START. + I2C_CTR_TRANS_START = 0x20 + // Position of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Msk = 0x40 + // Bit TX_LSB_FIRST. + I2C_CTR_TX_LSB_FIRST = 0x40 + // Position of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Msk = 0x80 + // Bit RX_LSB_FIRST. + I2C_CTR_RX_LSB_FIRST = 0x80 + // Position of CLK_EN field. + I2C_CTR_CLK_EN_Pos = 0x8 + // Bit mask of CLK_EN field. + I2C_CTR_CLK_EN_Msk = 0x100 + // Bit CLK_EN. + I2C_CTR_CLK_EN = 0x100 + // Position of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Pos = 0x9 + // Bit mask of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Msk = 0x200 + // Bit ARBITRATION_EN. + I2C_CTR_ARBITRATION_EN = 0x200 + // Position of FSM_RST field. + I2C_CTR_FSM_RST_Pos = 0xa + // Bit mask of FSM_RST field. + I2C_CTR_FSM_RST_Msk = 0x400 + // Bit FSM_RST. + I2C_CTR_FSM_RST = 0x400 + // Position of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Pos = 0xb + // Bit mask of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Msk = 0x800 + // Bit CONF_UPGATE. + I2C_CTR_CONF_UPGATE = 0x800 + // Position of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Pos = 0xc + // Bit mask of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Msk = 0x1000 + // Bit SLV_TX_AUTO_START_EN. + I2C_CTR_SLV_TX_AUTO_START_EN = 0x1000 + // Position of ADDR_10BIT_RW_CHECK_EN field. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Pos = 0xd + // Bit mask of ADDR_10BIT_RW_CHECK_EN field. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Msk = 0x2000 + // Bit ADDR_10BIT_RW_CHECK_EN. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN = 0x2000 + // Position of ADDR_BROADCASTING_EN field. + I2C_CTR_ADDR_BROADCASTING_EN_Pos = 0xe + // Bit mask of ADDR_BROADCASTING_EN field. + I2C_CTR_ADDR_BROADCASTING_EN_Msk = 0x4000 + // Bit ADDR_BROADCASTING_EN. + I2C_CTR_ADDR_BROADCASTING_EN = 0x4000 + + // SR: Describe I2C work status. + // Position of RESP_REC field. + I2C_SR_RESP_REC_Pos = 0x0 + // Bit mask of RESP_REC field. + I2C_SR_RESP_REC_Msk = 0x1 + // Bit RESP_REC. + I2C_SR_RESP_REC = 0x1 + // Position of SLAVE_RW field. + I2C_SR_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + I2C_SR_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + I2C_SR_SLAVE_RW = 0x2 + // Position of ARB_LOST field. + I2C_SR_ARB_LOST_Pos = 0x3 + // Bit mask of ARB_LOST field. + I2C_SR_ARB_LOST_Msk = 0x8 + // Bit ARB_LOST. + I2C_SR_ARB_LOST = 0x8 + // Position of BUS_BUSY field. + I2C_SR_BUS_BUSY_Pos = 0x4 + // Bit mask of BUS_BUSY field. + I2C_SR_BUS_BUSY_Msk = 0x10 + // Bit BUS_BUSY. + I2C_SR_BUS_BUSY = 0x10 + // Position of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Pos = 0x5 + // Bit mask of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Msk = 0x20 + // Bit SLAVE_ADDRESSED. + I2C_SR_SLAVE_ADDRESSED = 0x20 + // Position of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Pos = 0x8 + // Bit mask of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Msk = 0x3f00 + // Position of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Pos = 0xe + // Bit mask of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Msk = 0xc000 + // Position of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Pos = 0x12 + // Bit mask of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Msk = 0xfc0000 + // Position of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: Setting time out control for receiving data. + // Position of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Pos = 0x0 + // Bit mask of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Msk = 0x1f + // Position of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Pos = 0x5 + // Bit mask of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Msk = 0x20 + // Bit TIME_OUT_EN. + I2C_TO_TIME_OUT_EN = 0x20 + + // SLAVE_ADDR: Local slave address setting + // Position of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // FIFO_ST: FIFO status register. + // Position of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Pos = 0x0 + // Bit mask of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Msk = 0x1f + // Position of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Pos = 0x5 + // Bit mask of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Msk = 0x3e0 + // Position of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Pos = 0xa + // Bit mask of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Msk = 0x7c00 + // Position of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Pos = 0xf + // Bit mask of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Msk = 0xf8000 + // Position of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Pos = 0x16 + // Bit mask of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Msk = 0x3fc00000 + + // FIFO_CONF: FIFO configuration register. + // Position of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0x1f + // Position of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5 + // Bit mask of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x3e0 + // Position of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa + // Bit mask of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400 + // Bit NONFIFO_EN. + I2C_FIFO_CONF_NONFIFO_EN = 0x400 + // Position of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Pos = 0xb + // Bit mask of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Msk = 0x800 + // Bit FIFO_ADDR_CFG_EN. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN = 0x800 + // Position of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc + // Bit mask of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000 + // Bit RX_FIFO_RST. + I2C_FIFO_CONF_RX_FIFO_RST = 0x1000 + // Position of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd + // Bit mask of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000 + // Bit TX_FIFO_RST. + I2C_FIFO_CONF_TX_FIFO_RST = 0x2000 + // Position of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Pos = 0xe + // Bit mask of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000 + // Bit FIFO_PRT_EN. + I2C_FIFO_CONF_FIFO_PRT_EN = 0x4000 + + // DATA: Rx FIFO read data. + // Position of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Pos = 0x0 + // Bit mask of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Msk = 0x1 + // Bit RXFIFO_WM_INT_RAW. + I2C_INT_RAW_RXFIFO_WM_INT_RAW = 0x1 + // Position of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Msk = 0x2 + // Bit TXFIFO_WM_INT_RAW. + I2C_INT_RAW_TXFIFO_WM_INT_RAW = 0x2 + // Position of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4 + // Bit RXFIFO_OVF_INT_RAW. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4 + // Position of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3 + // Bit mask of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8 + // Bit END_DETECT_INT_RAW. + I2C_INT_RAW_END_DETECT_INT_RAW = 0x8 + // Position of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_RAW. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW = 0x10 + // Position of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_RAW. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20 + // Position of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_RAW. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW = 0x40 + // Position of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_RAW. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80 + // Position of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8 + // Bit mask of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100 + // Bit TIME_OUT_INT_RAW. + I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100 + // Position of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9 + // Bit mask of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200 + // Bit TRANS_START_INT_RAW. + I2C_INT_RAW_TRANS_START_INT_RAW = 0x200 + // Position of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Pos = 0xa + // Bit mask of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Msk = 0x400 + // Bit NACK_INT_RAW. + I2C_INT_RAW_NACK_INT_RAW = 0x400 + // Position of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Msk = 0x800 + // Bit TXFIFO_OVF_INT_RAW. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW = 0x800 + // Position of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_RAW. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW = 0x1000 + // Position of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Msk = 0x2000 + // Bit SCL_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_ST_TO_INT_RAW = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW = 0x4000 + // Position of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Pos = 0xf + // Bit mask of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Msk = 0x8000 + // Bit DET_START_INT_RAW. + I2C_INT_RAW_DET_START_INT_RAW = 0x8000 + // Position of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_RAW. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW = 0x10000 + // Position of GENERAL_CALL_INT_RAW field. + I2C_INT_RAW_GENERAL_CALL_INT_RAW_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_RAW field. + I2C_INT_RAW_GENERAL_CALL_INT_RAW_Msk = 0x20000 + // Bit GENERAL_CALL_INT_RAW. + I2C_INT_RAW_GENERAL_CALL_INT_RAW = 0x20000 + // Position of SLAVE_ADDR_UNMATCH_INT_RAW field. + I2C_INT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW_Pos = 0x12 + // Bit mask of SLAVE_ADDR_UNMATCH_INT_RAW field. + I2C_INT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW_Msk = 0x40000 + // Bit SLAVE_ADDR_UNMATCH_INT_RAW. + I2C_INT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW = 0x40000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Msk = 0x1 + // Bit RXFIFO_WM_INT_CLR. + I2C_INT_CLR_RXFIFO_WM_INT_CLR = 0x1 + // Position of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Msk = 0x2 + // Bit TXFIFO_WM_INT_CLR. + I2C_INT_CLR_TXFIFO_WM_INT_CLR = 0x2 + // Position of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4 + // Bit RXFIFO_OVF_INT_CLR. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4 + // Position of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3 + // Bit mask of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8 + // Bit END_DETECT_INT_CLR. + I2C_INT_CLR_END_DETECT_INT_CLR = 0x8 + // Position of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_CLR. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR = 0x10 + // Position of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_CLR. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_CLR. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR = 0x40 + // Position of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_CLR. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit TIME_OUT_INT_CLR. + I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100 + // Position of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9 + // Bit mask of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200 + // Bit TRANS_START_INT_CLR. + I2C_INT_CLR_TRANS_START_INT_CLR = 0x200 + // Position of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Pos = 0xa + // Bit mask of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Msk = 0x400 + // Bit NACK_INT_CLR. + I2C_INT_CLR_NACK_INT_CLR = 0x400 + // Position of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Msk = 0x800 + // Bit TXFIFO_OVF_INT_CLR. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR = 0x800 + // Position of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_CLR. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR = 0x1000 + // Position of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Msk = 0x2000 + // Bit SCL_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_ST_TO_INT_CLR = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR = 0x4000 + // Position of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Pos = 0xf + // Bit mask of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Msk = 0x8000 + // Bit DET_START_INT_CLR. + I2C_INT_CLR_DET_START_INT_CLR = 0x8000 + // Position of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_CLR. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR = 0x10000 + // Position of GENERAL_CALL_INT_CLR field. + I2C_INT_CLR_GENERAL_CALL_INT_CLR_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_CLR field. + I2C_INT_CLR_GENERAL_CALL_INT_CLR_Msk = 0x20000 + // Bit GENERAL_CALL_INT_CLR. + I2C_INT_CLR_GENERAL_CALL_INT_CLR = 0x20000 + // Position of SLAVE_ADDR_UNMATCH_INT_CLR field. + I2C_INT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR_Pos = 0x12 + // Bit mask of SLAVE_ADDR_UNMATCH_INT_CLR field. + I2C_INT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR_Msk = 0x40000 + // Bit SLAVE_ADDR_UNMATCH_INT_CLR. + I2C_INT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR = 0x40000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Msk = 0x1 + // Bit RXFIFO_WM_INT_ENA. + I2C_INT_ENA_RXFIFO_WM_INT_ENA = 0x1 + // Position of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Msk = 0x2 + // Bit TXFIFO_WM_INT_ENA. + I2C_INT_ENA_TXFIFO_WM_INT_ENA = 0x2 + // Position of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ENA. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4 + // Position of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3 + // Bit mask of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8 + // Bit END_DETECT_INT_ENA. + I2C_INT_ENA_END_DETECT_INT_ENA = 0x8 + // Position of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ENA. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA = 0x10 + // Position of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ENA. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20 + // Position of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ENA. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA = 0x40 + // Position of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ENA. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80 + // Position of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100 + // Bit TIME_OUT_INT_ENA. + I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100 + // Position of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9 + // Bit mask of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200 + // Bit TRANS_START_INT_ENA. + I2C_INT_ENA_TRANS_START_INT_ENA = 0x200 + // Position of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Pos = 0xa + // Bit mask of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Msk = 0x400 + // Bit NACK_INT_ENA. + I2C_INT_ENA_NACK_INT_ENA = 0x400 + // Position of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ENA. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA = 0x800 + // Position of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ENA. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA = 0x1000 + // Position of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_ST_TO_INT_ENA = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA = 0x4000 + // Position of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Pos = 0xf + // Bit mask of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Msk = 0x8000 + // Bit DET_START_INT_ENA. + I2C_INT_ENA_DET_START_INT_ENA = 0x8000 + // Position of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ENA. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA = 0x10000 + // Position of GENERAL_CALL_INT_ENA field. + I2C_INT_ENA_GENERAL_CALL_INT_ENA_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_ENA field. + I2C_INT_ENA_GENERAL_CALL_INT_ENA_Msk = 0x20000 + // Bit GENERAL_CALL_INT_ENA. + I2C_INT_ENA_GENERAL_CALL_INT_ENA = 0x20000 + // Position of SLAVE_ADDR_UNMATCH_INT_ENA field. + I2C_INT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA_Pos = 0x12 + // Bit mask of SLAVE_ADDR_UNMATCH_INT_ENA field. + I2C_INT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA_Msk = 0x40000 + // Bit SLAVE_ADDR_UNMATCH_INT_ENA. + I2C_INT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA = 0x40000 + + // INT_STATUS: Status of captured I2C communication events + // Position of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Msk = 0x1 + // Bit RXFIFO_WM_INT_ST. + I2C_INT_STATUS_RXFIFO_WM_INT_ST = 0x1 + // Position of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Msk = 0x2 + // Bit TXFIFO_WM_INT_ST. + I2C_INT_STATUS_TXFIFO_WM_INT_ST = 0x2 + // Position of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ST. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4 + // Position of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3 + // Bit mask of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8 + // Bit END_DETECT_INT_ST. + I2C_INT_STATUS_END_DETECT_INT_ST = 0x8 + // Position of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ST. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST = 0x10 + // Position of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ST. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20 + // Position of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ST. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST = 0x40 + // Position of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ST. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80 + // Position of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100 + // Bit TIME_OUT_INT_ST. + I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100 + // Position of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9 + // Bit mask of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200 + // Bit TRANS_START_INT_ST. + I2C_INT_STATUS_TRANS_START_INT_ST = 0x200 + // Position of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Pos = 0xa + // Bit mask of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Msk = 0x400 + // Bit NACK_INT_ST. + I2C_INT_STATUS_NACK_INT_ST = 0x400 + // Position of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ST. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST = 0x800 + // Position of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ST. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST = 0x1000 + // Position of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_ST_TO_INT_ST = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST = 0x4000 + // Position of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Pos = 0xf + // Bit mask of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Msk = 0x8000 + // Bit DET_START_INT_ST. + I2C_INT_STATUS_DET_START_INT_ST = 0x8000 + // Position of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ST. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST = 0x10000 + // Position of GENERAL_CALL_INT_ST field. + I2C_INT_STATUS_GENERAL_CALL_INT_ST_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_ST field. + I2C_INT_STATUS_GENERAL_CALL_INT_ST_Msk = 0x20000 + // Bit GENERAL_CALL_INT_ST. + I2C_INT_STATUS_GENERAL_CALL_INT_ST = 0x20000 + // Position of SLAVE_ADDR_UNMATCH_INT_ST field. + I2C_INT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST_Pos = 0x12 + // Bit mask of SLAVE_ADDR_UNMATCH_INT_ST field. + I2C_INT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST_Msk = 0x40000 + // Bit SLAVE_ADDR_UNMATCH_INT_ST. + I2C_INT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST = 0x40000 + + // SDA_HOLD: Configures the hold time after a negative SCL edge. + // Position of TIME field. + I2C_SDA_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_HOLD_TIME_Msk = 0x1ff + + // SDA_SAMPLE: Configures the sample time after a positive SCL edge. + // Position of TIME field. + I2C_SDA_SAMPLE_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_SAMPLE_TIME_Msk = 0x1ff + + // SCL_HIGH_PERIOD: Configures the high level width of SCL + // Position of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x1ff + // Position of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Pos = 0x9 + // Bit mask of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Msk = 0xfe00 + + // SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition + // Position of TIME field. + I2C_SCL_START_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_START_HOLD_TIME_Msk = 0x1ff + + // SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA + // Position of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Msk = 0x1ff + + // SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_HOLD_TIME_Msk = 0x1ff + + // SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_SETUP_TIME_Msk = 0x1ff + + // FILTER_CFG: SCL and SDA filter configuration register + // Position of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0 + // Bit mask of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Msk = 0xf + // Position of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x4 + // Bit mask of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Msk = 0xf0 + // Position of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Pos = 0x8 + // Bit mask of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Msk = 0x100 + // Bit SCL_FILTER_EN. + I2C_FILTER_CFG_SCL_FILTER_EN = 0x100 + // Position of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Pos = 0x9 + // Bit mask of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Msk = 0x200 + // Bit SDA_FILTER_EN. + I2C_FILTER_CFG_SDA_FILTER_EN = 0x200 + + // CLK_CONF: I2C CLK configuration register + // Position of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Pos = 0x0 + // Bit mask of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff + // Position of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Pos = 0x8 + // Bit mask of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Msk = 0x3f00 + // Position of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Pos = 0xe + // Bit mask of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Msk = 0xfc000 + // Position of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Msk = 0x100000 + // Bit SCLK_SEL. + I2C_CLK_CONF_SCLK_SEL = 0x100000 + // Position of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Pos = 0x15 + // Bit mask of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Msk = 0x200000 + // Bit SCLK_ACTIVE. + I2C_CLK_CONF_SCLK_ACTIVE = 0x200000 + + // COMD0: I2C command register %s + // Position of COMMAND field. + I2C_COMD_COMMAND_Pos = 0x0 + // Bit mask of COMMAND field. + I2C_COMD_COMMAND_Msk = 0x3fff + // Position of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Pos = 0x1f + // Bit mask of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Msk = 0x80000000 + // Bit COMMAND_DONE. + I2C_COMD_COMMAND_DONE = 0x80000000 + + // SCL_ST_TIME_OUT: SCL status time out register + // Position of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Msk = 0x1f + + // SCL_MAIN_ST_TIME_OUT: SCL main status time out register + // Position of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Msk = 0x1f + + // SCL_SP_CONF: Power configuration register + // Position of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Pos = 0x0 + // Bit mask of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Msk = 0x1 + // Bit SCL_RST_SLV_EN. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN = 0x1 + // Position of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Pos = 0x1 + // Bit mask of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Msk = 0x3e + // Position of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Pos = 0x6 + // Bit mask of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Msk = 0x40 + // Bit SCL_PD_EN. + I2C_SCL_SP_CONF_SCL_PD_EN = 0x40 + // Position of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Pos = 0x7 + // Bit mask of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Msk = 0x80 + // Bit SDA_PD_EN. + I2C_SCL_SP_CONF_SDA_PD_EN = 0x80 + + // SCL_STRETCH_CONF: Set SCL stretch of I2C slave + // Position of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Pos = 0x0 + // Bit mask of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Msk = 0x3ff + // Position of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Pos = 0xa + // Bit mask of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Msk = 0x400 + // Bit SLAVE_SCL_STRETCH_EN. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN = 0x400 + // Position of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Pos = 0xb + // Bit mask of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Msk = 0x800 + // Bit SLAVE_SCL_STRETCH_CLR. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR = 0x800 + // Position of SLAVE_BYTE_ACK_CTL_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Pos = 0xc + // Bit mask of SLAVE_BYTE_ACK_CTL_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Msk = 0x1000 + // Bit SLAVE_BYTE_ACK_CTL_EN. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN = 0x1000 + // Position of SLAVE_BYTE_ACK_LVL field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Pos = 0xd + // Bit mask of SLAVE_BYTE_ACK_LVL field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Msk = 0x2000 + // Bit SLAVE_BYTE_ACK_LVL. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL = 0x2000 + + // DATE: Version register + // Position of DATE field. + I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2C_DATE_DATE_Msk = 0xffffffff + + // TXFIFO_START_ADDR: I2C TXFIFO base address register + // Position of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Msk = 0xffffffff + + // RXFIFO_START_ADDR: I2C RXFIFO base address register + // Position of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Msk = 0xffffffff +) + +// Constants for I2S0: I2S (Inter-IC Sound) Controller 0 +const ( + // INT_RAW: I2S interrupt raw register, valid in level. + // Position of RX_DONE_INT_RAW field. + I2S_INT_RAW_RX_DONE_INT_RAW_Pos = 0x0 + // Bit mask of RX_DONE_INT_RAW field. + I2S_INT_RAW_RX_DONE_INT_RAW_Msk = 0x1 + // Bit RX_DONE_INT_RAW. + I2S_INT_RAW_RX_DONE_INT_RAW = 0x1 + // Position of TX_DONE_INT_RAW field. + I2S_INT_RAW_TX_DONE_INT_RAW_Pos = 0x1 + // Bit mask of TX_DONE_INT_RAW field. + I2S_INT_RAW_TX_DONE_INT_RAW_Msk = 0x2 + // Bit TX_DONE_INT_RAW. + I2S_INT_RAW_TX_DONE_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + I2S_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + I2S_INT_RAW_TX_HUNG_INT_RAW = 0x8 + + // INT_ST: I2S interrupt status register. + // Position of RX_DONE_INT_ST field. + I2S_INT_ST_RX_DONE_INT_ST_Pos = 0x0 + // Bit mask of RX_DONE_INT_ST field. + I2S_INT_ST_RX_DONE_INT_ST_Msk = 0x1 + // Bit RX_DONE_INT_ST. + I2S_INT_ST_RX_DONE_INT_ST = 0x1 + // Position of TX_DONE_INT_ST field. + I2S_INT_ST_TX_DONE_INT_ST_Pos = 0x1 + // Bit mask of TX_DONE_INT_ST field. + I2S_INT_ST_TX_DONE_INT_ST_Msk = 0x2 + // Bit TX_DONE_INT_ST. + I2S_INT_ST_TX_DONE_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + I2S_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + I2S_INT_ST_TX_HUNG_INT_ST = 0x8 + + // INT_ENA: I2S interrupt enable register. + // Position of RX_DONE_INT_ENA field. + I2S_INT_ENA_RX_DONE_INT_ENA_Pos = 0x0 + // Bit mask of RX_DONE_INT_ENA field. + I2S_INT_ENA_RX_DONE_INT_ENA_Msk = 0x1 + // Bit RX_DONE_INT_ENA. + I2S_INT_ENA_RX_DONE_INT_ENA = 0x1 + // Position of TX_DONE_INT_ENA field. + I2S_INT_ENA_TX_DONE_INT_ENA_Pos = 0x1 + // Bit mask of TX_DONE_INT_ENA field. + I2S_INT_ENA_TX_DONE_INT_ENA_Msk = 0x2 + // Bit TX_DONE_INT_ENA. + I2S_INT_ENA_TX_DONE_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + I2S_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + I2S_INT_ENA_TX_HUNG_INT_ENA = 0x8 + + // INT_CLR: I2S interrupt clear register. + // Position of RX_DONE_INT_CLR field. + I2S_INT_CLR_RX_DONE_INT_CLR_Pos = 0x0 + // Bit mask of RX_DONE_INT_CLR field. + I2S_INT_CLR_RX_DONE_INT_CLR_Msk = 0x1 + // Bit RX_DONE_INT_CLR. + I2S_INT_CLR_RX_DONE_INT_CLR = 0x1 + // Position of TX_DONE_INT_CLR field. + I2S_INT_CLR_TX_DONE_INT_CLR_Pos = 0x1 + // Bit mask of TX_DONE_INT_CLR field. + I2S_INT_CLR_TX_DONE_INT_CLR_Msk = 0x2 + // Bit TX_DONE_INT_CLR. + I2S_INT_CLR_TX_DONE_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + I2S_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + I2S_INT_CLR_TX_HUNG_INT_CLR = 0x8 + + // RX_CONF: I2S RX configure register + // Position of RX_RESET field. + I2S_RX_CONF_RX_RESET_Pos = 0x0 + // Bit mask of RX_RESET field. + I2S_RX_CONF_RX_RESET_Msk = 0x1 + // Bit RX_RESET. + I2S_RX_CONF_RX_RESET = 0x1 + // Position of RX_FIFO_RESET field. + I2S_RX_CONF_RX_FIFO_RESET_Pos = 0x1 + // Bit mask of RX_FIFO_RESET field. + I2S_RX_CONF_RX_FIFO_RESET_Msk = 0x2 + // Bit RX_FIFO_RESET. + I2S_RX_CONF_RX_FIFO_RESET = 0x2 + // Position of RX_START field. + I2S_RX_CONF_RX_START_Pos = 0x2 + // Bit mask of RX_START field. + I2S_RX_CONF_RX_START_Msk = 0x4 + // Bit RX_START. + I2S_RX_CONF_RX_START = 0x4 + // Position of RX_SLAVE_MOD field. + I2S_RX_CONF_RX_SLAVE_MOD_Pos = 0x3 + // Bit mask of RX_SLAVE_MOD field. + I2S_RX_CONF_RX_SLAVE_MOD_Msk = 0x8 + // Bit RX_SLAVE_MOD. + I2S_RX_CONF_RX_SLAVE_MOD = 0x8 + // Position of RX_MONO field. + I2S_RX_CONF_RX_MONO_Pos = 0x5 + // Bit mask of RX_MONO field. + I2S_RX_CONF_RX_MONO_Msk = 0x20 + // Bit RX_MONO. + I2S_RX_CONF_RX_MONO = 0x20 + // Position of RX_BIG_ENDIAN field. + I2S_RX_CONF_RX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of RX_BIG_ENDIAN field. + I2S_RX_CONF_RX_BIG_ENDIAN_Msk = 0x80 + // Bit RX_BIG_ENDIAN. + I2S_RX_CONF_RX_BIG_ENDIAN = 0x80 + // Position of RX_UPDATE field. + I2S_RX_CONF_RX_UPDATE_Pos = 0x8 + // Bit mask of RX_UPDATE field. + I2S_RX_CONF_RX_UPDATE_Msk = 0x100 + // Bit RX_UPDATE. + I2S_RX_CONF_RX_UPDATE = 0x100 + // Position of RX_MONO_FST_VLD field. + I2S_RX_CONF_RX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of RX_MONO_FST_VLD field. + I2S_RX_CONF_RX_MONO_FST_VLD_Msk = 0x200 + // Bit RX_MONO_FST_VLD. + I2S_RX_CONF_RX_MONO_FST_VLD = 0x200 + // Position of RX_PCM_CONF field. + I2S_RX_CONF_RX_PCM_CONF_Pos = 0xa + // Bit mask of RX_PCM_CONF field. + I2S_RX_CONF_RX_PCM_CONF_Msk = 0xc00 + // Position of RX_PCM_BYPASS field. + I2S_RX_CONF_RX_PCM_BYPASS_Pos = 0xc + // Bit mask of RX_PCM_BYPASS field. + I2S_RX_CONF_RX_PCM_BYPASS_Msk = 0x1000 + // Bit RX_PCM_BYPASS. + I2S_RX_CONF_RX_PCM_BYPASS = 0x1000 + // Position of RX_STOP_MODE field. + I2S_RX_CONF_RX_STOP_MODE_Pos = 0xd + // Bit mask of RX_STOP_MODE field. + I2S_RX_CONF_RX_STOP_MODE_Msk = 0x6000 + // Position of RX_LEFT_ALIGN field. + I2S_RX_CONF_RX_LEFT_ALIGN_Pos = 0xf + // Bit mask of RX_LEFT_ALIGN field. + I2S_RX_CONF_RX_LEFT_ALIGN_Msk = 0x8000 + // Bit RX_LEFT_ALIGN. + I2S_RX_CONF_RX_LEFT_ALIGN = 0x8000 + // Position of RX_24_FILL_EN field. + I2S_RX_CONF_RX_24_FILL_EN_Pos = 0x10 + // Bit mask of RX_24_FILL_EN field. + I2S_RX_CONF_RX_24_FILL_EN_Msk = 0x10000 + // Bit RX_24_FILL_EN. + I2S_RX_CONF_RX_24_FILL_EN = 0x10000 + // Position of RX_WS_IDLE_POL field. + I2S_RX_CONF_RX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of RX_WS_IDLE_POL field. + I2S_RX_CONF_RX_WS_IDLE_POL_Msk = 0x20000 + // Bit RX_WS_IDLE_POL. + I2S_RX_CONF_RX_WS_IDLE_POL = 0x20000 + // Position of RX_BIT_ORDER field. + I2S_RX_CONF_RX_BIT_ORDER_Pos = 0x12 + // Bit mask of RX_BIT_ORDER field. + I2S_RX_CONF_RX_BIT_ORDER_Msk = 0x40000 + // Bit RX_BIT_ORDER. + I2S_RX_CONF_RX_BIT_ORDER = 0x40000 + // Position of RX_TDM_EN field. + I2S_RX_CONF_RX_TDM_EN_Pos = 0x13 + // Bit mask of RX_TDM_EN field. + I2S_RX_CONF_RX_TDM_EN_Msk = 0x80000 + // Bit RX_TDM_EN. + I2S_RX_CONF_RX_TDM_EN = 0x80000 + // Position of RX_PDM_EN field. + I2S_RX_CONF_RX_PDM_EN_Pos = 0x14 + // Bit mask of RX_PDM_EN field. + I2S_RX_CONF_RX_PDM_EN_Msk = 0x100000 + // Bit RX_PDM_EN. + I2S_RX_CONF_RX_PDM_EN = 0x100000 + + // TX_CONF: I2S TX configure register + // Position of TX_RESET field. + I2S_TX_CONF_TX_RESET_Pos = 0x0 + // Bit mask of TX_RESET field. + I2S_TX_CONF_TX_RESET_Msk = 0x1 + // Bit TX_RESET. + I2S_TX_CONF_TX_RESET = 0x1 + // Position of TX_FIFO_RESET field. + I2S_TX_CONF_TX_FIFO_RESET_Pos = 0x1 + // Bit mask of TX_FIFO_RESET field. + I2S_TX_CONF_TX_FIFO_RESET_Msk = 0x2 + // Bit TX_FIFO_RESET. + I2S_TX_CONF_TX_FIFO_RESET = 0x2 + // Position of TX_START field. + I2S_TX_CONF_TX_START_Pos = 0x2 + // Bit mask of TX_START field. + I2S_TX_CONF_TX_START_Msk = 0x4 + // Bit TX_START. + I2S_TX_CONF_TX_START = 0x4 + // Position of TX_SLAVE_MOD field. + I2S_TX_CONF_TX_SLAVE_MOD_Pos = 0x3 + // Bit mask of TX_SLAVE_MOD field. + I2S_TX_CONF_TX_SLAVE_MOD_Msk = 0x8 + // Bit TX_SLAVE_MOD. + I2S_TX_CONF_TX_SLAVE_MOD = 0x8 + // Position of TX_MONO field. + I2S_TX_CONF_TX_MONO_Pos = 0x5 + // Bit mask of TX_MONO field. + I2S_TX_CONF_TX_MONO_Msk = 0x20 + // Bit TX_MONO. + I2S_TX_CONF_TX_MONO = 0x20 + // Position of TX_CHAN_EQUAL field. + I2S_TX_CONF_TX_CHAN_EQUAL_Pos = 0x6 + // Bit mask of TX_CHAN_EQUAL field. + I2S_TX_CONF_TX_CHAN_EQUAL_Msk = 0x40 + // Bit TX_CHAN_EQUAL. + I2S_TX_CONF_TX_CHAN_EQUAL = 0x40 + // Position of TX_BIG_ENDIAN field. + I2S_TX_CONF_TX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of TX_BIG_ENDIAN field. + I2S_TX_CONF_TX_BIG_ENDIAN_Msk = 0x80 + // Bit TX_BIG_ENDIAN. + I2S_TX_CONF_TX_BIG_ENDIAN = 0x80 + // Position of TX_UPDATE field. + I2S_TX_CONF_TX_UPDATE_Pos = 0x8 + // Bit mask of TX_UPDATE field. + I2S_TX_CONF_TX_UPDATE_Msk = 0x100 + // Bit TX_UPDATE. + I2S_TX_CONF_TX_UPDATE = 0x100 + // Position of TX_MONO_FST_VLD field. + I2S_TX_CONF_TX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of TX_MONO_FST_VLD field. + I2S_TX_CONF_TX_MONO_FST_VLD_Msk = 0x200 + // Bit TX_MONO_FST_VLD. + I2S_TX_CONF_TX_MONO_FST_VLD = 0x200 + // Position of TX_PCM_CONF field. + I2S_TX_CONF_TX_PCM_CONF_Pos = 0xa + // Bit mask of TX_PCM_CONF field. + I2S_TX_CONF_TX_PCM_CONF_Msk = 0xc00 + // Position of TX_PCM_BYPASS field. + I2S_TX_CONF_TX_PCM_BYPASS_Pos = 0xc + // Bit mask of TX_PCM_BYPASS field. + I2S_TX_CONF_TX_PCM_BYPASS_Msk = 0x1000 + // Bit TX_PCM_BYPASS. + I2S_TX_CONF_TX_PCM_BYPASS = 0x1000 + // Position of TX_STOP_EN field. + I2S_TX_CONF_TX_STOP_EN_Pos = 0xd + // Bit mask of TX_STOP_EN field. + I2S_TX_CONF_TX_STOP_EN_Msk = 0x2000 + // Bit TX_STOP_EN. + I2S_TX_CONF_TX_STOP_EN = 0x2000 + // Position of TX_LEFT_ALIGN field. + I2S_TX_CONF_TX_LEFT_ALIGN_Pos = 0xf + // Bit mask of TX_LEFT_ALIGN field. + I2S_TX_CONF_TX_LEFT_ALIGN_Msk = 0x8000 + // Bit TX_LEFT_ALIGN. + I2S_TX_CONF_TX_LEFT_ALIGN = 0x8000 + // Position of TX_24_FILL_EN field. + I2S_TX_CONF_TX_24_FILL_EN_Pos = 0x10 + // Bit mask of TX_24_FILL_EN field. + I2S_TX_CONF_TX_24_FILL_EN_Msk = 0x10000 + // Bit TX_24_FILL_EN. + I2S_TX_CONF_TX_24_FILL_EN = 0x10000 + // Position of TX_WS_IDLE_POL field. + I2S_TX_CONF_TX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of TX_WS_IDLE_POL field. + I2S_TX_CONF_TX_WS_IDLE_POL_Msk = 0x20000 + // Bit TX_WS_IDLE_POL. + I2S_TX_CONF_TX_WS_IDLE_POL = 0x20000 + // Position of TX_BIT_ORDER field. + I2S_TX_CONF_TX_BIT_ORDER_Pos = 0x12 + // Bit mask of TX_BIT_ORDER field. + I2S_TX_CONF_TX_BIT_ORDER_Msk = 0x40000 + // Bit TX_BIT_ORDER. + I2S_TX_CONF_TX_BIT_ORDER = 0x40000 + // Position of TX_TDM_EN field. + I2S_TX_CONF_TX_TDM_EN_Pos = 0x13 + // Bit mask of TX_TDM_EN field. + I2S_TX_CONF_TX_TDM_EN_Msk = 0x80000 + // Bit TX_TDM_EN. + I2S_TX_CONF_TX_TDM_EN = 0x80000 + // Position of TX_PDM_EN field. + I2S_TX_CONF_TX_PDM_EN_Pos = 0x14 + // Bit mask of TX_PDM_EN field. + I2S_TX_CONF_TX_PDM_EN_Msk = 0x100000 + // Bit TX_PDM_EN. + I2S_TX_CONF_TX_PDM_EN = 0x100000 + // Position of TX_CHAN_MOD field. + I2S_TX_CONF_TX_CHAN_MOD_Pos = 0x18 + // Bit mask of TX_CHAN_MOD field. + I2S_TX_CONF_TX_CHAN_MOD_Msk = 0x7000000 + // Position of SIG_LOOPBACK field. + I2S_TX_CONF_SIG_LOOPBACK_Pos = 0x1b + // Bit mask of SIG_LOOPBACK field. + I2S_TX_CONF_SIG_LOOPBACK_Msk = 0x8000000 + // Bit SIG_LOOPBACK. + I2S_TX_CONF_SIG_LOOPBACK = 0x8000000 + + // RX_CONF1: I2S RX configure register 1 + // Position of RX_TDM_WS_WIDTH field. + I2S_RX_CONF1_RX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of RX_TDM_WS_WIDTH field. + I2S_RX_CONF1_RX_TDM_WS_WIDTH_Msk = 0x7f + // Position of RX_BCK_DIV_NUM field. + I2S_RX_CONF1_RX_BCK_DIV_NUM_Pos = 0x7 + // Bit mask of RX_BCK_DIV_NUM field. + I2S_RX_CONF1_RX_BCK_DIV_NUM_Msk = 0x1f80 + // Position of RX_BITS_MOD field. + I2S_RX_CONF1_RX_BITS_MOD_Pos = 0xd + // Bit mask of RX_BITS_MOD field. + I2S_RX_CONF1_RX_BITS_MOD_Msk = 0x3e000 + // Position of RX_HALF_SAMPLE_BITS field. + I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Pos = 0x12 + // Bit mask of RX_HALF_SAMPLE_BITS field. + I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Msk = 0xfc0000 + // Position of RX_TDM_CHAN_BITS field. + I2S_RX_CONF1_RX_TDM_CHAN_BITS_Pos = 0x18 + // Bit mask of RX_TDM_CHAN_BITS field. + I2S_RX_CONF1_RX_TDM_CHAN_BITS_Msk = 0x1f000000 + // Position of RX_MSB_SHIFT field. + I2S_RX_CONF1_RX_MSB_SHIFT_Pos = 0x1d + // Bit mask of RX_MSB_SHIFT field. + I2S_RX_CONF1_RX_MSB_SHIFT_Msk = 0x20000000 + // Bit RX_MSB_SHIFT. + I2S_RX_CONF1_RX_MSB_SHIFT = 0x20000000 + + // TX_CONF1: I2S TX configure register 1 + // Position of TX_TDM_WS_WIDTH field. + I2S_TX_CONF1_TX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of TX_TDM_WS_WIDTH field. + I2S_TX_CONF1_TX_TDM_WS_WIDTH_Msk = 0x7f + // Position of TX_BCK_DIV_NUM field. + I2S_TX_CONF1_TX_BCK_DIV_NUM_Pos = 0x7 + // Bit mask of TX_BCK_DIV_NUM field. + I2S_TX_CONF1_TX_BCK_DIV_NUM_Msk = 0x1f80 + // Position of TX_BITS_MOD field. + I2S_TX_CONF1_TX_BITS_MOD_Pos = 0xd + // Bit mask of TX_BITS_MOD field. + I2S_TX_CONF1_TX_BITS_MOD_Msk = 0x3e000 + // Position of TX_HALF_SAMPLE_BITS field. + I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Pos = 0x12 + // Bit mask of TX_HALF_SAMPLE_BITS field. + I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Msk = 0xfc0000 + // Position of TX_TDM_CHAN_BITS field. + I2S_TX_CONF1_TX_TDM_CHAN_BITS_Pos = 0x18 + // Bit mask of TX_TDM_CHAN_BITS field. + I2S_TX_CONF1_TX_TDM_CHAN_BITS_Msk = 0x1f000000 + // Position of TX_MSB_SHIFT field. + I2S_TX_CONF1_TX_MSB_SHIFT_Pos = 0x1d + // Bit mask of TX_MSB_SHIFT field. + I2S_TX_CONF1_TX_MSB_SHIFT_Msk = 0x20000000 + // Bit TX_MSB_SHIFT. + I2S_TX_CONF1_TX_MSB_SHIFT = 0x20000000 + // Position of TX_BCK_NO_DLY field. + I2S_TX_CONF1_TX_BCK_NO_DLY_Pos = 0x1e + // Bit mask of TX_BCK_NO_DLY field. + I2S_TX_CONF1_TX_BCK_NO_DLY_Msk = 0x40000000 + // Bit TX_BCK_NO_DLY. + I2S_TX_CONF1_TX_BCK_NO_DLY = 0x40000000 + + // RX_CLKM_CONF: I2S RX clock configure register + // Position of RX_CLKM_DIV_NUM field. + I2S_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_NUM field. + I2S_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Msk = 0xff + // Position of RX_CLK_ACTIVE field. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of RX_CLK_ACTIVE field. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE_Msk = 0x4000000 + // Bit RX_CLK_ACTIVE. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE = 0x4000000 + // Position of RX_CLK_SEL field. + I2S_RX_CLKM_CONF_RX_CLK_SEL_Pos = 0x1b + // Bit mask of RX_CLK_SEL field. + I2S_RX_CLKM_CONF_RX_CLK_SEL_Msk = 0x18000000 + // Position of MCLK_SEL field. + I2S_RX_CLKM_CONF_MCLK_SEL_Pos = 0x1d + // Bit mask of MCLK_SEL field. + I2S_RX_CLKM_CONF_MCLK_SEL_Msk = 0x20000000 + // Bit MCLK_SEL. + I2S_RX_CLKM_CONF_MCLK_SEL = 0x20000000 + + // TX_CLKM_CONF: I2S TX clock configure register + // Position of TX_CLKM_DIV_NUM field. + I2S_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_NUM field. + I2S_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Msk = 0xff + // Position of TX_CLK_ACTIVE field. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of TX_CLK_ACTIVE field. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE_Msk = 0x4000000 + // Bit TX_CLK_ACTIVE. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE = 0x4000000 + // Position of TX_CLK_SEL field. + I2S_TX_CLKM_CONF_TX_CLK_SEL_Pos = 0x1b + // Bit mask of TX_CLK_SEL field. + I2S_TX_CLKM_CONF_TX_CLK_SEL_Msk = 0x18000000 + // Position of CLK_EN field. + I2S_TX_CLKM_CONF_CLK_EN_Pos = 0x1d + // Bit mask of CLK_EN field. + I2S_TX_CLKM_CONF_CLK_EN_Msk = 0x20000000 + // Bit CLK_EN. + I2S_TX_CLKM_CONF_CLK_EN = 0x20000000 + + // RX_CLKM_DIV_CONF: I2S RX module clock divider configure register + // Position of RX_CLKM_DIV_Z field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_Z field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Msk = 0x1ff + // Position of RX_CLKM_DIV_Y field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of RX_CLKM_DIV_Y field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of RX_CLKM_DIV_X field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of RX_CLKM_DIV_X field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of RX_CLKM_DIV_YN1 field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of RX_CLKM_DIV_YN1 field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit RX_CLKM_DIV_YN1. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1 = 0x8000000 + + // TX_CLKM_DIV_CONF: I2S TX module clock divider configure register + // Position of TX_CLKM_DIV_Z field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_Z field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Msk = 0x1ff + // Position of TX_CLKM_DIV_Y field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of TX_CLKM_DIV_Y field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of TX_CLKM_DIV_X field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of TX_CLKM_DIV_X field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of TX_CLKM_DIV_YN1 field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of TX_CLKM_DIV_YN1 field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit TX_CLKM_DIV_YN1. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1 = 0x8000000 + + // TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register + // Position of TX_PDM_HP_BYPASS field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Pos = 0x0 + // Bit mask of TX_PDM_HP_BYPASS field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Msk = 0x1 + // Bit TX_PDM_HP_BYPASS. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS = 0x1 + // Position of TX_PDM_SINC_OSR2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Pos = 0x1 + // Bit mask of TX_PDM_SINC_OSR2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Msk = 0x1e + // Position of TX_PDM_PRESCALE field. + I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Pos = 0x5 + // Bit mask of TX_PDM_PRESCALE field. + I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Msk = 0x1fe0 + // Position of TX_PDM_HP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Pos = 0xd + // Bit mask of TX_PDM_HP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Msk = 0x6000 + // Position of TX_PDM_LP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Pos = 0xf + // Bit mask of TX_PDM_LP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Msk = 0x18000 + // Position of TX_PDM_SINC_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Pos = 0x11 + // Bit mask of TX_PDM_SINC_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Msk = 0x60000 + // Position of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Pos = 0x13 + // Bit mask of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Msk = 0x180000 + // Position of TX_PDM_SIGMADELTA_DITHER2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Pos = 0x15 + // Bit mask of TX_PDM_SIGMADELTA_DITHER2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Msk = 0x200000 + // Bit TX_PDM_SIGMADELTA_DITHER2. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2 = 0x200000 + // Position of TX_PDM_SIGMADELTA_DITHER field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Pos = 0x16 + // Bit mask of TX_PDM_SIGMADELTA_DITHER field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Msk = 0x400000 + // Bit TX_PDM_SIGMADELTA_DITHER. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER = 0x400000 + // Position of TX_PDM_DAC_2OUT_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Pos = 0x17 + // Bit mask of TX_PDM_DAC_2OUT_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Msk = 0x800000 + // Bit TX_PDM_DAC_2OUT_EN. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN = 0x800000 + // Position of TX_PDM_DAC_MODE_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Pos = 0x18 + // Bit mask of TX_PDM_DAC_MODE_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Msk = 0x1000000 + // Bit TX_PDM_DAC_MODE_EN. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN = 0x1000000 + // Position of PCM2PDM_CONV_EN field. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Pos = 0x19 + // Bit mask of PCM2PDM_CONV_EN field. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Msk = 0x2000000 + // Bit PCM2PDM_CONV_EN. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN = 0x2000000 + + // TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register + // Position of TX_PDM_FP field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Pos = 0x0 + // Bit mask of TX_PDM_FP field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Msk = 0x3ff + // Position of TX_PDM_FS field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Pos = 0xa + // Bit mask of TX_PDM_FS field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Msk = 0xffc00 + // Position of TX_IIR_HP_MULT12_5 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Pos = 0x14 + // Bit mask of TX_IIR_HP_MULT12_5 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Msk = 0x700000 + // Position of TX_IIR_HP_MULT12_0 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Pos = 0x17 + // Bit mask of TX_IIR_HP_MULT12_0 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Msk = 0x3800000 + + // RX_TDM_CTRL: I2S TX TDM mode control register + // Position of RX_TDM_PDM_CHAN0_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Pos = 0x0 + // Bit mask of RX_TDM_PDM_CHAN0_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Msk = 0x1 + // Bit RX_TDM_PDM_CHAN0_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN = 0x1 + // Position of RX_TDM_PDM_CHAN1_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Pos = 0x1 + // Bit mask of RX_TDM_PDM_CHAN1_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Msk = 0x2 + // Bit RX_TDM_PDM_CHAN1_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN = 0x2 + // Position of RX_TDM_PDM_CHAN2_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Pos = 0x2 + // Bit mask of RX_TDM_PDM_CHAN2_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Msk = 0x4 + // Bit RX_TDM_PDM_CHAN2_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN = 0x4 + // Position of RX_TDM_PDM_CHAN3_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Pos = 0x3 + // Bit mask of RX_TDM_PDM_CHAN3_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Msk = 0x8 + // Bit RX_TDM_PDM_CHAN3_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN = 0x8 + // Position of RX_TDM_PDM_CHAN4_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Pos = 0x4 + // Bit mask of RX_TDM_PDM_CHAN4_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Msk = 0x10 + // Bit RX_TDM_PDM_CHAN4_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN = 0x10 + // Position of RX_TDM_PDM_CHAN5_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Pos = 0x5 + // Bit mask of RX_TDM_PDM_CHAN5_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Msk = 0x20 + // Bit RX_TDM_PDM_CHAN5_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN = 0x20 + // Position of RX_TDM_PDM_CHAN6_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Pos = 0x6 + // Bit mask of RX_TDM_PDM_CHAN6_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Msk = 0x40 + // Bit RX_TDM_PDM_CHAN6_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN = 0x40 + // Position of RX_TDM_PDM_CHAN7_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Pos = 0x7 + // Bit mask of RX_TDM_PDM_CHAN7_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Msk = 0x80 + // Bit RX_TDM_PDM_CHAN7_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN = 0x80 + // Position of RX_TDM_CHAN8_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of RX_TDM_CHAN8_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Msk = 0x100 + // Bit RX_TDM_CHAN8_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN = 0x100 + // Position of RX_TDM_CHAN9_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of RX_TDM_CHAN9_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Msk = 0x200 + // Bit RX_TDM_CHAN9_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN = 0x200 + // Position of RX_TDM_CHAN10_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of RX_TDM_CHAN10_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Msk = 0x400 + // Bit RX_TDM_CHAN10_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN = 0x400 + // Position of RX_TDM_CHAN11_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of RX_TDM_CHAN11_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Msk = 0x800 + // Bit RX_TDM_CHAN11_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN = 0x800 + // Position of RX_TDM_CHAN12_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of RX_TDM_CHAN12_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit RX_TDM_CHAN12_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN = 0x1000 + // Position of RX_TDM_CHAN13_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of RX_TDM_CHAN13_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit RX_TDM_CHAN13_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN = 0x2000 + // Position of RX_TDM_CHAN14_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of RX_TDM_CHAN14_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit RX_TDM_CHAN14_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN = 0x4000 + // Position of RX_TDM_CHAN15_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of RX_TDM_CHAN15_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit RX_TDM_CHAN15_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN = 0x8000 + // Position of RX_TDM_TOT_CHAN_NUM field. + I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of RX_TDM_TOT_CHAN_NUM field. + I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + + // TX_TDM_CTRL: I2S TX TDM mode control register + // Position of TX_TDM_CHAN0_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Pos = 0x0 + // Bit mask of TX_TDM_CHAN0_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Msk = 0x1 + // Bit TX_TDM_CHAN0_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN = 0x1 + // Position of TX_TDM_CHAN1_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Pos = 0x1 + // Bit mask of TX_TDM_CHAN1_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Msk = 0x2 + // Bit TX_TDM_CHAN1_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN = 0x2 + // Position of TX_TDM_CHAN2_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Pos = 0x2 + // Bit mask of TX_TDM_CHAN2_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Msk = 0x4 + // Bit TX_TDM_CHAN2_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN = 0x4 + // Position of TX_TDM_CHAN3_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Pos = 0x3 + // Bit mask of TX_TDM_CHAN3_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Msk = 0x8 + // Bit TX_TDM_CHAN3_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN = 0x8 + // Position of TX_TDM_CHAN4_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Pos = 0x4 + // Bit mask of TX_TDM_CHAN4_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Msk = 0x10 + // Bit TX_TDM_CHAN4_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN = 0x10 + // Position of TX_TDM_CHAN5_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Pos = 0x5 + // Bit mask of TX_TDM_CHAN5_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Msk = 0x20 + // Bit TX_TDM_CHAN5_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN = 0x20 + // Position of TX_TDM_CHAN6_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Pos = 0x6 + // Bit mask of TX_TDM_CHAN6_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Msk = 0x40 + // Bit TX_TDM_CHAN6_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN = 0x40 + // Position of TX_TDM_CHAN7_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Pos = 0x7 + // Bit mask of TX_TDM_CHAN7_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Msk = 0x80 + // Bit TX_TDM_CHAN7_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN = 0x80 + // Position of TX_TDM_CHAN8_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of TX_TDM_CHAN8_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Msk = 0x100 + // Bit TX_TDM_CHAN8_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN = 0x100 + // Position of TX_TDM_CHAN9_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of TX_TDM_CHAN9_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Msk = 0x200 + // Bit TX_TDM_CHAN9_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN = 0x200 + // Position of TX_TDM_CHAN10_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of TX_TDM_CHAN10_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Msk = 0x400 + // Bit TX_TDM_CHAN10_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN = 0x400 + // Position of TX_TDM_CHAN11_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of TX_TDM_CHAN11_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Msk = 0x800 + // Bit TX_TDM_CHAN11_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN = 0x800 + // Position of TX_TDM_CHAN12_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of TX_TDM_CHAN12_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit TX_TDM_CHAN12_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN = 0x1000 + // Position of TX_TDM_CHAN13_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of TX_TDM_CHAN13_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit TX_TDM_CHAN13_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN = 0x2000 + // Position of TX_TDM_CHAN14_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of TX_TDM_CHAN14_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit TX_TDM_CHAN14_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN = 0x4000 + // Position of TX_TDM_CHAN15_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of TX_TDM_CHAN15_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit TX_TDM_CHAN15_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN = 0x8000 + // Position of TX_TDM_TOT_CHAN_NUM field. + I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of TX_TDM_TOT_CHAN_NUM field. + I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + // Position of TX_TDM_SKIP_MSK_EN field. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Pos = 0x14 + // Bit mask of TX_TDM_SKIP_MSK_EN field. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Msk = 0x100000 + // Bit TX_TDM_SKIP_MSK_EN. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN = 0x100000 + + // RX_TIMING: I2S RX timing control register + // Position of RX_SD_IN_DM field. + I2S_RX_TIMING_RX_SD_IN_DM_Pos = 0x0 + // Bit mask of RX_SD_IN_DM field. + I2S_RX_TIMING_RX_SD_IN_DM_Msk = 0x3 + // Position of RX_WS_OUT_DM field. + I2S_RX_TIMING_RX_WS_OUT_DM_Pos = 0x10 + // Bit mask of RX_WS_OUT_DM field. + I2S_RX_TIMING_RX_WS_OUT_DM_Msk = 0x30000 + // Position of RX_BCK_OUT_DM field. + I2S_RX_TIMING_RX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of RX_BCK_OUT_DM field. + I2S_RX_TIMING_RX_BCK_OUT_DM_Msk = 0x300000 + // Position of RX_WS_IN_DM field. + I2S_RX_TIMING_RX_WS_IN_DM_Pos = 0x18 + // Bit mask of RX_WS_IN_DM field. + I2S_RX_TIMING_RX_WS_IN_DM_Msk = 0x3000000 + // Position of RX_BCK_IN_DM field. + I2S_RX_TIMING_RX_BCK_IN_DM_Pos = 0x1c + // Bit mask of RX_BCK_IN_DM field. + I2S_RX_TIMING_RX_BCK_IN_DM_Msk = 0x30000000 + + // TX_TIMING: I2S TX timing control register + // Position of TX_SD_OUT_DM field. + I2S_TX_TIMING_TX_SD_OUT_DM_Pos = 0x0 + // Bit mask of TX_SD_OUT_DM field. + I2S_TX_TIMING_TX_SD_OUT_DM_Msk = 0x3 + // Position of TX_SD1_OUT_DM field. + I2S_TX_TIMING_TX_SD1_OUT_DM_Pos = 0x4 + // Bit mask of TX_SD1_OUT_DM field. + I2S_TX_TIMING_TX_SD1_OUT_DM_Msk = 0x30 + // Position of TX_WS_OUT_DM field. + I2S_TX_TIMING_TX_WS_OUT_DM_Pos = 0x10 + // Bit mask of TX_WS_OUT_DM field. + I2S_TX_TIMING_TX_WS_OUT_DM_Msk = 0x30000 + // Position of TX_BCK_OUT_DM field. + I2S_TX_TIMING_TX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of TX_BCK_OUT_DM field. + I2S_TX_TIMING_TX_BCK_OUT_DM_Msk = 0x300000 + // Position of TX_WS_IN_DM field. + I2S_TX_TIMING_TX_WS_IN_DM_Pos = 0x18 + // Bit mask of TX_WS_IN_DM field. + I2S_TX_TIMING_TX_WS_IN_DM_Msk = 0x3000000 + // Position of TX_BCK_IN_DM field. + I2S_TX_TIMING_TX_BCK_IN_DM_Pos = 0x1c + // Bit mask of TX_BCK_IN_DM field. + I2S_TX_TIMING_TX_BCK_IN_DM_Msk = 0x30000000 + + // LC_HUNG_CONF: I2S HUNG configure register. + // Position of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Pos = 0x0 + // Bit mask of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Msk = 0xff + // Position of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit LC_FIFO_TIMEOUT_ENA. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA = 0x800 + + // RXEOF_NUM: I2S RX data number control register. + // Position of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Pos = 0x0 + // Bit mask of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Msk = 0xfff + + // CONF_SIGLE_DATA: I2S signal data register + // Position of SINGLE_DATA field. + I2S_CONF_SIGLE_DATA_SINGLE_DATA_Pos = 0x0 + // Bit mask of SINGLE_DATA field. + I2S_CONF_SIGLE_DATA_SINGLE_DATA_Msk = 0xffffffff + + // STATE: I2S TX status register + // Position of TX_IDLE field. + I2S_STATE_TX_IDLE_Pos = 0x0 + // Bit mask of TX_IDLE field. + I2S_STATE_TX_IDLE_Msk = 0x1 + // Bit TX_IDLE. + I2S_STATE_TX_IDLE = 0x1 + + // ETM_CONF: I2S ETM configure register + // Position of ETM_TX_SEND_WORD_NUM field. + I2S_ETM_CONF_ETM_TX_SEND_WORD_NUM_Pos = 0x0 + // Bit mask of ETM_TX_SEND_WORD_NUM field. + I2S_ETM_CONF_ETM_TX_SEND_WORD_NUM_Msk = 0x3ff + // Position of ETM_RX_RECEIVE_WORD_NUM field. + I2S_ETM_CONF_ETM_RX_RECEIVE_WORD_NUM_Pos = 0xa + // Bit mask of ETM_RX_RECEIVE_WORD_NUM field. + I2S_ETM_CONF_ETM_RX_RECEIVE_WORD_NUM_Msk = 0xffc00 + + // DATE: Version control register + // Position of DATE field. + I2S_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2S_DATE_DATE_Msk = 0xfffffff +) + +// Constants for INTERRUPT_CORE0: Interrupt Controller (Core 0) +const ( + // WIFI_MAC_INTR_MAP: register description + // Position of WIFI_MAC_INTR_MAP field. + INTMTX_CORE0_WIFI_MAC_INTR_MAP_WIFI_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of WIFI_MAC_INTR_MAP field. + INTMTX_CORE0_WIFI_MAC_INTR_MAP_WIFI_MAC_INTR_MAP_Msk = 0x1f + + // WIFI_MAC_NMI_MAP: register description + // Position of WIFI_MAC_NMI_MAP field. + INTMTX_CORE0_WIFI_MAC_NMI_MAP_WIFI_MAC_NMI_MAP_Pos = 0x0 + // Bit mask of WIFI_MAC_NMI_MAP field. + INTMTX_CORE0_WIFI_MAC_NMI_MAP_WIFI_MAC_NMI_MAP_Msk = 0x1f + + // WIFI_PWR_INTR_MAP: register description + // Position of WIFI_PWR_INTR_MAP field. + INTMTX_CORE0_WIFI_PWR_INTR_MAP_WIFI_PWR_INTR_MAP_Pos = 0x0 + // Bit mask of WIFI_PWR_INTR_MAP field. + INTMTX_CORE0_WIFI_PWR_INTR_MAP_WIFI_PWR_INTR_MAP_Msk = 0x1f + + // WIFI_BB_INTR_MAP: register description + // Position of WIFI_BB_INTR_MAP field. + INTMTX_CORE0_WIFI_BB_INTR_MAP_WIFI_BB_INTR_MAP_Pos = 0x0 + // Bit mask of WIFI_BB_INTR_MAP field. + INTMTX_CORE0_WIFI_BB_INTR_MAP_WIFI_BB_INTR_MAP_Msk = 0x1f + + // BT_MAC_INTR_MAP: register description + // Position of BT_MAC_INTR_MAP field. + INTMTX_CORE0_BT_MAC_INTR_MAP_BT_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of BT_MAC_INTR_MAP field. + INTMTX_CORE0_BT_MAC_INTR_MAP_BT_MAC_INTR_MAP_Msk = 0x1f + + // BT_BB_INTR_MAP: register description + // Position of BT_BB_INTR_MAP field. + INTMTX_CORE0_BT_BB_INTR_MAP_BT_BB_INTR_MAP_Pos = 0x0 + // Bit mask of BT_BB_INTR_MAP field. + INTMTX_CORE0_BT_BB_INTR_MAP_BT_BB_INTR_MAP_Msk = 0x1f + + // BT_BB_NMI_MAP: register description + // Position of BT_BB_NMI_MAP field. + INTMTX_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Pos = 0x0 + // Bit mask of BT_BB_NMI_MAP field. + INTMTX_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Msk = 0x1f + + // LP_TIMER_INTR_MAP: register description + // Position of LP_TIMER_INTR_MAP field. + INTMTX_CORE0_LP_TIMER_INTR_MAP_LP_TIMER_INTR_MAP_Pos = 0x0 + // Bit mask of LP_TIMER_INTR_MAP field. + INTMTX_CORE0_LP_TIMER_INTR_MAP_LP_TIMER_INTR_MAP_Msk = 0x1f + + // COEX_INTR_MAP: register description + // Position of COEX_INTR_MAP field. + INTMTX_CORE0_COEX_INTR_MAP_COEX_INTR_MAP_Pos = 0x0 + // Bit mask of COEX_INTR_MAP field. + INTMTX_CORE0_COEX_INTR_MAP_COEX_INTR_MAP_Msk = 0x1f + + // BLE_TIMER_INTR_MAP: register description + // Position of BLE_TIMER_INTR_MAP field. + INTMTX_CORE0_BLE_TIMER_INTR_MAP_BLE_TIMER_INTR_MAP_Pos = 0x0 + // Bit mask of BLE_TIMER_INTR_MAP field. + INTMTX_CORE0_BLE_TIMER_INTR_MAP_BLE_TIMER_INTR_MAP_Msk = 0x1f + + // BLE_SEC_INTR_MAP: register description + // Position of BLE_SEC_INTR_MAP field. + INTMTX_CORE0_BLE_SEC_INTR_MAP_BLE_SEC_INTR_MAP_Pos = 0x0 + // Bit mask of BLE_SEC_INTR_MAP field. + INTMTX_CORE0_BLE_SEC_INTR_MAP_BLE_SEC_INTR_MAP_Msk = 0x1f + + // I2C_MST_INTR_MAP: register description + // Position of I2C_MST_INTR_MAP field. + INTMTX_CORE0_I2C_MST_INTR_MAP_I2C_MST_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_MST_INTR_MAP field. + INTMTX_CORE0_I2C_MST_INTR_MAP_I2C_MST_INTR_MAP_Msk = 0x1f + + // ZB_MAC_INTR_MAP: register description + // Position of ZB_MAC_INTR_MAP field. + INTMTX_CORE0_ZB_MAC_INTR_MAP_ZB_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of ZB_MAC_INTR_MAP field. + INTMTX_CORE0_ZB_MAC_INTR_MAP_ZB_MAC_INTR_MAP_Msk = 0x1f + + // PMU_INTR_MAP: register description + // Position of PMU_INTR_MAP field. + INTMTX_CORE0_PMU_INTR_MAP_PMU_INTR_MAP_Pos = 0x0 + // Bit mask of PMU_INTR_MAP field. + INTMTX_CORE0_PMU_INTR_MAP_PMU_INTR_MAP_Msk = 0x1f + + // EFUSE_INTR_MAP: register description + // Position of EFUSE_INTR_MAP field. + INTMTX_CORE0_EFUSE_INTR_MAP_EFUSE_INTR_MAP_Pos = 0x0 + // Bit mask of EFUSE_INTR_MAP field. + INTMTX_CORE0_EFUSE_INTR_MAP_EFUSE_INTR_MAP_Msk = 0x1f + + // LP_RTC_TIMER_INTR_MAP: register description + // Position of LP_RTC_TIMER_INTR_MAP field. + INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_LP_RTC_TIMER_INTR_MAP_Pos = 0x0 + // Bit mask of LP_RTC_TIMER_INTR_MAP field. + INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_LP_RTC_TIMER_INTR_MAP_Msk = 0x1f + + // LP_UART_INTR_MAP: register description + // Position of LP_UART_INTR_MAP field. + INTMTX_CORE0_LP_UART_INTR_MAP_LP_UART_INTR_MAP_Pos = 0x0 + // Bit mask of LP_UART_INTR_MAP field. + INTMTX_CORE0_LP_UART_INTR_MAP_LP_UART_INTR_MAP_Msk = 0x1f + + // LP_I2C_INTR_MAP: register description + // Position of LP_I2C_INTR_MAP field. + INTMTX_CORE0_LP_I2C_INTR_MAP_LP_I2C_INTR_MAP_Pos = 0x0 + // Bit mask of LP_I2C_INTR_MAP field. + INTMTX_CORE0_LP_I2C_INTR_MAP_LP_I2C_INTR_MAP_Msk = 0x1f + + // LP_WDT_INTR_MAP: register description + // Position of LP_WDT_INTR_MAP field. + INTMTX_CORE0_LP_WDT_INTR_MAP_LP_WDT_INTR_MAP_Pos = 0x0 + // Bit mask of LP_WDT_INTR_MAP field. + INTMTX_CORE0_LP_WDT_INTR_MAP_LP_WDT_INTR_MAP_Msk = 0x1f + + // LP_PERI_TIMEOUT_INTR_MAP: register description + // Position of LP_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_LP_PERI_TIMEOUT_INTR_MAP_Pos = 0x0 + // Bit mask of LP_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_LP_PERI_TIMEOUT_INTR_MAP_Msk = 0x1f + + // LP_APM_M0_INTR_MAP: register description + // Position of LP_APM_M0_INTR_MAP field. + INTMTX_CORE0_LP_APM_M0_INTR_MAP_LP_APM_M0_INTR_MAP_Pos = 0x0 + // Bit mask of LP_APM_M0_INTR_MAP field. + INTMTX_CORE0_LP_APM_M0_INTR_MAP_LP_APM_M0_INTR_MAP_Msk = 0x1f + + // LP_APM_M1_INTR_MAP: register description + // Position of LP_APM_M1_INTR_MAP field. + INTMTX_CORE0_LP_APM_M1_INTR_MAP_LP_APM_M1_INTR_MAP_Pos = 0x0 + // Bit mask of LP_APM_M1_INTR_MAP field. + INTMTX_CORE0_LP_APM_M1_INTR_MAP_LP_APM_M1_INTR_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_0_MAP: register description + // Position of CPU_INTR_FROM_CPU_0_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_1_MAP: register description + // Position of CPU_INTR_FROM_CPU_1_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_2_MAP: register description + // Position of CPU_INTR_FROM_CPU_2_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_3_MAP: register description + // Position of CPU_INTR_FROM_CPU_3_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Msk = 0x1f + + // ASSIST_DEBUG_INTR_MAP: register description + // Position of ASSIST_DEBUG_INTR_MAP field. + INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Pos = 0x0 + // Bit mask of ASSIST_DEBUG_INTR_MAP field. + INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Msk = 0x1f + + // TRACE_INTR_MAP: register description + // Position of TRACE_INTR_MAP field. + INTMTX_CORE0_TRACE_INTR_MAP_TRACE_INTR_MAP_Pos = 0x0 + // Bit mask of TRACE_INTR_MAP field. + INTMTX_CORE0_TRACE_INTR_MAP_TRACE_INTR_MAP_Msk = 0x1f + + // CACHE_INTR_MAP: register description + // Position of CACHE_INTR_MAP field. + INTMTX_CORE0_CACHE_INTR_MAP_CACHE_INTR_MAP_Pos = 0x0 + // Bit mask of CACHE_INTR_MAP field. + INTMTX_CORE0_CACHE_INTR_MAP_CACHE_INTR_MAP_Msk = 0x1f + + // CPU_PERI_TIMEOUT_INTR_MAP: register description + // Position of CPU_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_CPU_PERI_TIMEOUT_INTR_MAP_Pos = 0x0 + // Bit mask of CPU_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_CPU_PERI_TIMEOUT_INTR_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_MAP: register description + // Position of GPIO_INTERRUPT_PRO_MAP field. + INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_MAP field. + INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_NMI_MAP: register description + // Position of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Msk = 0x1f + + // PAU_INTR_MAP: register description + // Position of PAU_INTR_MAP field. + INTMTX_CORE0_PAU_INTR_MAP_PAU_INTR_MAP_Pos = 0x0 + // Bit mask of PAU_INTR_MAP field. + INTMTX_CORE0_PAU_INTR_MAP_PAU_INTR_MAP_Msk = 0x1f + + // HP_PERI_TIMEOUT_INTR_MAP: register description + // Position of HP_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_HP_PERI_TIMEOUT_INTR_MAP_Pos = 0x0 + // Bit mask of HP_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_HP_PERI_TIMEOUT_INTR_MAP_Msk = 0x1f + + // MODEM_PERI_TIMEOUT_INTR_MAP: register description + // Position of MODEM_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_MODEM_PERI_TIMEOUT_INTR_MAP_Pos = 0x0 + // Bit mask of MODEM_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_MODEM_PERI_TIMEOUT_INTR_MAP_Msk = 0x1f + + // HP_APM_M0_INTR_MAP: register description + // Position of HP_APM_M0_INTR_MAP field. + INTMTX_CORE0_HP_APM_M0_INTR_MAP_HP_APM_M0_INTR_MAP_Pos = 0x0 + // Bit mask of HP_APM_M0_INTR_MAP field. + INTMTX_CORE0_HP_APM_M0_INTR_MAP_HP_APM_M0_INTR_MAP_Msk = 0x1f + + // HP_APM_M1_INTR_MAP: register description + // Position of HP_APM_M1_INTR_MAP field. + INTMTX_CORE0_HP_APM_M1_INTR_MAP_HP_APM_M1_INTR_MAP_Pos = 0x0 + // Bit mask of HP_APM_M1_INTR_MAP field. + INTMTX_CORE0_HP_APM_M1_INTR_MAP_HP_APM_M1_INTR_MAP_Msk = 0x1f + + // HP_APM_M2_INTR_MAP: register description + // Position of HP_APM_M2_INTR_MAP field. + INTMTX_CORE0_HP_APM_M2_INTR_MAP_HP_APM_M2_INTR_MAP_Pos = 0x0 + // Bit mask of HP_APM_M2_INTR_MAP field. + INTMTX_CORE0_HP_APM_M2_INTR_MAP_HP_APM_M2_INTR_MAP_Msk = 0x1f + + // HP_APM_M3_INTR_MAP: register description + // Position of HP_APM_M3_INTR_MAP field. + INTMTX_CORE0_HP_APM_M3_INTR_MAP_HP_APM_M3_INTR_MAP_Pos = 0x0 + // Bit mask of HP_APM_M3_INTR_MAP field. + INTMTX_CORE0_HP_APM_M3_INTR_MAP_HP_APM_M3_INTR_MAP_Msk = 0x1f + + // LP_APM0_INTR_MAP: register description + // Position of LP_APM0_INTR_MAP field. + INTMTX_CORE0_LP_APM0_INTR_MAP_LP_APM0_INTR_MAP_Pos = 0x0 + // Bit mask of LP_APM0_INTR_MAP field. + INTMTX_CORE0_LP_APM0_INTR_MAP_LP_APM0_INTR_MAP_Msk = 0x1f + + // MSPI_INTR_MAP: register description + // Position of MSPI_INTR_MAP field. + INTMTX_CORE0_MSPI_INTR_MAP_MSPI_INTR_MAP_Pos = 0x0 + // Bit mask of MSPI_INTR_MAP field. + INTMTX_CORE0_MSPI_INTR_MAP_MSPI_INTR_MAP_Msk = 0x1f + + // I2S1_INTR_MAP: register description + // Position of I2S1_INTR_MAP field. + INTMTX_CORE0_I2S1_INTR_MAP_I2S1_INTR_MAP_Pos = 0x0 + // Bit mask of I2S1_INTR_MAP field. + INTMTX_CORE0_I2S1_INTR_MAP_I2S1_INTR_MAP_Msk = 0x1f + + // UHCI0_INTR_MAP: register description + // Position of UHCI0_INTR_MAP field. + INTMTX_CORE0_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Pos = 0x0 + // Bit mask of UHCI0_INTR_MAP field. + INTMTX_CORE0_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Msk = 0x1f + + // UART0_INTR_MAP: register description + // Position of UART0_INTR_MAP field. + INTMTX_CORE0_UART0_INTR_MAP_UART0_INTR_MAP_Pos = 0x0 + // Bit mask of UART0_INTR_MAP field. + INTMTX_CORE0_UART0_INTR_MAP_UART0_INTR_MAP_Msk = 0x1f + + // UART1_INTR_MAP: register description + // Position of UART1_INTR_MAP field. + INTMTX_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Pos = 0x0 + // Bit mask of UART1_INTR_MAP field. + INTMTX_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Msk = 0x1f + + // LEDC_INTR_MAP: register description + // Position of LEDC_INTR_MAP field. + INTMTX_CORE0_LEDC_INTR_MAP_LEDC_INTR_MAP_Pos = 0x0 + // Bit mask of LEDC_INTR_MAP field. + INTMTX_CORE0_LEDC_INTR_MAP_LEDC_INTR_MAP_Msk = 0x1f + + // CAN0_INTR_MAP: register description + // Position of CAN0_INTR_MAP field. + INTMTX_CORE0_CAN0_INTR_MAP_CAN0_INTR_MAP_Pos = 0x0 + // Bit mask of CAN0_INTR_MAP field. + INTMTX_CORE0_CAN0_INTR_MAP_CAN0_INTR_MAP_Msk = 0x1f + + // CAN1_INTR_MAP: register description + // Position of CAN1_INTR_MAP field. + INTMTX_CORE0_CAN1_INTR_MAP_CAN1_INTR_MAP_Pos = 0x0 + // Bit mask of CAN1_INTR_MAP field. + INTMTX_CORE0_CAN1_INTR_MAP_CAN1_INTR_MAP_Msk = 0x1f + + // USB_INTR_MAP: register description + // Position of USB_INTR_MAP field. + INTMTX_CORE0_USB_INTR_MAP_USB_INTR_MAP_Pos = 0x0 + // Bit mask of USB_INTR_MAP field. + INTMTX_CORE0_USB_INTR_MAP_USB_INTR_MAP_Msk = 0x1f + + // RMT_INTR_MAP: register description + // Position of RMT_INTR_MAP field. + INTMTX_CORE0_RMT_INTR_MAP_RMT_INTR_MAP_Pos = 0x0 + // Bit mask of RMT_INTR_MAP field. + INTMTX_CORE0_RMT_INTR_MAP_RMT_INTR_MAP_Msk = 0x1f + + // I2C_EXT0_INTR_MAP: register description + // Position of I2C_EXT0_INTR_MAP field. + INTMTX_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_EXT0_INTR_MAP field. + INTMTX_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Msk = 0x1f + + // TG0_T0_INTR_MAP: register description + // Position of TG0_T0_INTR_MAP field. + INTMTX_CORE0_TG0_T0_INTR_MAP_TG0_T0_INTR_MAP_Pos = 0x0 + // Bit mask of TG0_T0_INTR_MAP field. + INTMTX_CORE0_TG0_T0_INTR_MAP_TG0_T0_INTR_MAP_Msk = 0x1f + + // TG0_T1_INTR_MAP: register description + // Position of TG0_T1_INTR_MAP field. + INTMTX_CORE0_TG0_T1_INTR_MAP_TG0_T1_INTR_MAP_Pos = 0x0 + // Bit mask of TG0_T1_INTR_MAP field. + INTMTX_CORE0_TG0_T1_INTR_MAP_TG0_T1_INTR_MAP_Msk = 0x1f + + // TG0_WDT_INTR_MAP: register description + // Position of TG0_WDT_INTR_MAP field. + INTMTX_CORE0_TG0_WDT_INTR_MAP_TG0_WDT_INTR_MAP_Pos = 0x0 + // Bit mask of TG0_WDT_INTR_MAP field. + INTMTX_CORE0_TG0_WDT_INTR_MAP_TG0_WDT_INTR_MAP_Msk = 0x1f + + // TG1_T0_INTR_MAP: register description + // Position of TG1_T0_INTR_MAP field. + INTMTX_CORE0_TG1_T0_INTR_MAP_TG1_T0_INTR_MAP_Pos = 0x0 + // Bit mask of TG1_T0_INTR_MAP field. + INTMTX_CORE0_TG1_T0_INTR_MAP_TG1_T0_INTR_MAP_Msk = 0x1f + + // TG1_T1_INTR_MAP: register description + // Position of TG1_T1_INTR_MAP field. + INTMTX_CORE0_TG1_T1_INTR_MAP_TG1_T1_INTR_MAP_Pos = 0x0 + // Bit mask of TG1_T1_INTR_MAP field. + INTMTX_CORE0_TG1_T1_INTR_MAP_TG1_T1_INTR_MAP_Msk = 0x1f + + // TG1_WDT_INTR_MAP: register description + // Position of TG1_WDT_INTR_MAP field. + INTMTX_CORE0_TG1_WDT_INTR_MAP_TG1_WDT_INTR_MAP_Pos = 0x0 + // Bit mask of TG1_WDT_INTR_MAP field. + INTMTX_CORE0_TG1_WDT_INTR_MAP_TG1_WDT_INTR_MAP_Msk = 0x1f + + // SYSTIMER_TARGET0_INTR_MAP: register description + // Position of SYSTIMER_TARGET0_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_SYSTIMER_TARGET0_INTR_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET0_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_SYSTIMER_TARGET0_INTR_MAP_Msk = 0x1f + + // SYSTIMER_TARGET1_INTR_MAP: register description + // Position of SYSTIMER_TARGET1_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_SYSTIMER_TARGET1_INTR_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET1_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_SYSTIMER_TARGET1_INTR_MAP_Msk = 0x1f + + // SYSTIMER_TARGET2_INTR_MAP: register description + // Position of SYSTIMER_TARGET2_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_SYSTIMER_TARGET2_INTR_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET2_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_SYSTIMER_TARGET2_INTR_MAP_Msk = 0x1f + + // APB_ADC_INTR_MAP: register description + // Position of APB_ADC_INTR_MAP field. + INTMTX_CORE0_APB_ADC_INTR_MAP_APB_ADC_INTR_MAP_Pos = 0x0 + // Bit mask of APB_ADC_INTR_MAP field. + INTMTX_CORE0_APB_ADC_INTR_MAP_APB_ADC_INTR_MAP_Msk = 0x1f + + // PWM_INTR_MAP: register description + // Position of PWM_INTR_MAP field. + INTMTX_CORE0_PWM_INTR_MAP_PWM_INTR_MAP_Pos = 0x0 + // Bit mask of PWM_INTR_MAP field. + INTMTX_CORE0_PWM_INTR_MAP_PWM_INTR_MAP_Msk = 0x1f + + // PCNT_INTR_MAP: register description + // Position of PCNT_INTR_MAP field. + INTMTX_CORE0_PCNT_INTR_MAP_PCNT_INTR_MAP_Pos = 0x0 + // Bit mask of PCNT_INTR_MAP field. + INTMTX_CORE0_PCNT_INTR_MAP_PCNT_INTR_MAP_Msk = 0x1f + + // PARL_IO_INTR_MAP: register description + // Position of PARL_IO_INTR_MAP field. + INTMTX_CORE0_PARL_IO_INTR_MAP_PARL_IO_INTR_MAP_Pos = 0x0 + // Bit mask of PARL_IO_INTR_MAP field. + INTMTX_CORE0_PARL_IO_INTR_MAP_PARL_IO_INTR_MAP_Msk = 0x1f + + // SLC0_INTR_MAP: register description + // Position of SLC0_INTR_MAP field. + INTMTX_CORE0_SLC0_INTR_MAP_SLC0_INTR_MAP_Pos = 0x0 + // Bit mask of SLC0_INTR_MAP field. + INTMTX_CORE0_SLC0_INTR_MAP_SLC0_INTR_MAP_Msk = 0x1f + + // SLC1_INTR_MAP: register description + // Position of SLC1_INTR_MAP field. + INTMTX_CORE0_SLC1_INTR_MAP_SLC1_INTR_MAP_Pos = 0x0 + // Bit mask of SLC1_INTR_MAP field. + INTMTX_CORE0_SLC1_INTR_MAP_SLC1_INTR_MAP_Msk = 0x1f + + // DMA_IN_CH0_INTR_MAP: register description + // Position of DMA_IN_CH0_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_DMA_IN_CH0_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH0_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_DMA_IN_CH0_INTR_MAP_Msk = 0x1f + + // DMA_IN_CH1_INTR_MAP: register description + // Position of DMA_IN_CH1_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_DMA_IN_CH1_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH1_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_DMA_IN_CH1_INTR_MAP_Msk = 0x1f + + // DMA_IN_CH2_INTR_MAP: register description + // Position of DMA_IN_CH2_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_DMA_IN_CH2_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH2_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_DMA_IN_CH2_INTR_MAP_Msk = 0x1f + + // DMA_OUT_CH0_INTR_MAP: register description + // Position of DMA_OUT_CH0_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_DMA_OUT_CH0_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH0_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_DMA_OUT_CH0_INTR_MAP_Msk = 0x1f + + // DMA_OUT_CH1_INTR_MAP: register description + // Position of DMA_OUT_CH1_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_DMA_OUT_CH1_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH1_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_DMA_OUT_CH1_INTR_MAP_Msk = 0x1f + + // DMA_OUT_CH2_INTR_MAP: register description + // Position of DMA_OUT_CH2_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_DMA_OUT_CH2_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH2_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_DMA_OUT_CH2_INTR_MAP_Msk = 0x1f + + // GPSPI2_INTR_MAP: register description + // Position of GPSPI2_INTR_MAP field. + INTMTX_CORE0_GPSPI2_INTR_MAP_GPSPI2_INTR_MAP_Pos = 0x0 + // Bit mask of GPSPI2_INTR_MAP field. + INTMTX_CORE0_GPSPI2_INTR_MAP_GPSPI2_INTR_MAP_Msk = 0x1f + + // AES_INTR_MAP: register description + // Position of AES_INTR_MAP field. + INTMTX_CORE0_AES_INTR_MAP_AES_INTR_MAP_Pos = 0x0 + // Bit mask of AES_INTR_MAP field. + INTMTX_CORE0_AES_INTR_MAP_AES_INTR_MAP_Msk = 0x1f + + // SHA_INTR_MAP: register description + // Position of SHA_INTR_MAP field. + INTMTX_CORE0_SHA_INTR_MAP_SHA_INTR_MAP_Pos = 0x0 + // Bit mask of SHA_INTR_MAP field. + INTMTX_CORE0_SHA_INTR_MAP_SHA_INTR_MAP_Msk = 0x1f + + // RSA_INTR_MAP: register description + // Position of RSA_INTR_MAP field. + INTMTX_CORE0_RSA_INTR_MAP_RSA_INTR_MAP_Pos = 0x0 + // Bit mask of RSA_INTR_MAP field. + INTMTX_CORE0_RSA_INTR_MAP_RSA_INTR_MAP_Msk = 0x1f + + // ECC_INTR_MAP: register description + // Position of ECC_INTR_MAP field. + INTMTX_CORE0_ECC_INTR_MAP_ECC_INTR_MAP_Pos = 0x0 + // Bit mask of ECC_INTR_MAP field. + INTMTX_CORE0_ECC_INTR_MAP_ECC_INTR_MAP_Msk = 0x1f + + // INTR_STATUS_REG_0: register description + // Position of INTR_STATUS_0 field. + INTMTX_CORE0_INTR_STATUS_REG_0_INTR_STATUS_0_Pos = 0x0 + // Bit mask of INTR_STATUS_0 field. + INTMTX_CORE0_INTR_STATUS_REG_0_INTR_STATUS_0_Msk = 0xffffffff + + // INTR_STATUS_REG_1: register description + // Position of INTR_STATUS_1 field. + INTMTX_CORE0_INTR_STATUS_REG_1_INTR_STATUS_1_Pos = 0x0 + // Bit mask of INTR_STATUS_1 field. + INTMTX_CORE0_INTR_STATUS_REG_1_INTR_STATUS_1_Msk = 0xffffffff + + // INT_STATUS_REG_2: register description + // Position of INT_STATUS_2 field. + INTMTX_CORE0_INT_STATUS_REG_2_INT_STATUS_2_Pos = 0x0 + // Bit mask of INT_STATUS_2 field. + INTMTX_CORE0_INT_STATUS_REG_2_INT_STATUS_2_Msk = 0xffffffff + + // CLOCK_GATE: register description + // Position of REG_CLK_EN field. + INTMTX_CORE0_CLOCK_GATE_REG_CLK_EN_Pos = 0x0 + // Bit mask of REG_CLK_EN field. + INTMTX_CORE0_CLOCK_GATE_REG_CLK_EN_Msk = 0x1 + // Bit REG_CLK_EN. + INTMTX_CORE0_CLOCK_GATE_REG_CLK_EN = 0x1 + + // INTERRUPT_REG_DATE: register description + // Position of INTERRUPT_REG_DATE field. + INTMTX_CORE0_INTERRUPT_REG_DATE_INTERRUPT_REG_DATE_Pos = 0x0 + // Bit mask of INTERRUPT_REG_DATE field. + INTMTX_CORE0_INTERRUPT_REG_DATE_INTERRUPT_REG_DATE_Msk = 0xfffffff +) + +// Constants for INTPRI: INTPRI Peripheral +const ( + // CPU_INT_ENABLE: register description + // Position of CPU_INT_ENABLE field. + INTPRI_CPU_INT_ENABLE_CPU_INT_ENABLE_Pos = 0x0 + // Bit mask of CPU_INT_ENABLE field. + INTPRI_CPU_INT_ENABLE_CPU_INT_ENABLE_Msk = 0xffffffff + + // CPU_INT_TYPE: register description + // Position of CPU_INT_TYPE field. + INTPRI_CPU_INT_TYPE_CPU_INT_TYPE_Pos = 0x0 + // Bit mask of CPU_INT_TYPE field. + INTPRI_CPU_INT_TYPE_CPU_INT_TYPE_Msk = 0xffffffff + + // CPU_INT_EIP_STATUS: register description + // Position of CPU_INT_EIP_STATUS field. + INTPRI_CPU_INT_EIP_STATUS_CPU_INT_EIP_STATUS_Pos = 0x0 + // Bit mask of CPU_INT_EIP_STATUS field. + INTPRI_CPU_INT_EIP_STATUS_CPU_INT_EIP_STATUS_Msk = 0xffffffff + + // CPU_INT_PRI_0: register description + // Position of CPU_PRI_0_MAP field. + INTPRI_CPU_INT_PRI_0_CPU_PRI_0_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_0_MAP field. + INTPRI_CPU_INT_PRI_0_CPU_PRI_0_MAP_Msk = 0xf + + // CPU_INT_PRI_1: register description + // Position of CPU_PRI_1_MAP field. + INTPRI_CPU_INT_PRI_1_CPU_PRI_1_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_1_MAP field. + INTPRI_CPU_INT_PRI_1_CPU_PRI_1_MAP_Msk = 0xf + + // CPU_INT_PRI_2: register description + // Position of CPU_PRI_2_MAP field. + INTPRI_CPU_INT_PRI_2_CPU_PRI_2_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_2_MAP field. + INTPRI_CPU_INT_PRI_2_CPU_PRI_2_MAP_Msk = 0xf + + // CPU_INT_PRI_3: register description + // Position of CPU_PRI_3_MAP field. + INTPRI_CPU_INT_PRI_3_CPU_PRI_3_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_3_MAP field. + INTPRI_CPU_INT_PRI_3_CPU_PRI_3_MAP_Msk = 0xf + + // CPU_INT_PRI_4: register description + // Position of CPU_PRI_4_MAP field. + INTPRI_CPU_INT_PRI_4_CPU_PRI_4_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_4_MAP field. + INTPRI_CPU_INT_PRI_4_CPU_PRI_4_MAP_Msk = 0xf + + // CPU_INT_PRI_5: register description + // Position of CPU_PRI_5_MAP field. + INTPRI_CPU_INT_PRI_5_CPU_PRI_5_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_5_MAP field. + INTPRI_CPU_INT_PRI_5_CPU_PRI_5_MAP_Msk = 0xf + + // CPU_INT_PRI_6: register description + // Position of CPU_PRI_6_MAP field. + INTPRI_CPU_INT_PRI_6_CPU_PRI_6_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_6_MAP field. + INTPRI_CPU_INT_PRI_6_CPU_PRI_6_MAP_Msk = 0xf + + // CPU_INT_PRI_7: register description + // Position of CPU_PRI_7_MAP field. + INTPRI_CPU_INT_PRI_7_CPU_PRI_7_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_7_MAP field. + INTPRI_CPU_INT_PRI_7_CPU_PRI_7_MAP_Msk = 0xf + + // CPU_INT_PRI_8: register description + // Position of CPU_PRI_8_MAP field. + INTPRI_CPU_INT_PRI_8_CPU_PRI_8_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_8_MAP field. + INTPRI_CPU_INT_PRI_8_CPU_PRI_8_MAP_Msk = 0xf + + // CPU_INT_PRI_9: register description + // Position of CPU_PRI_9_MAP field. + INTPRI_CPU_INT_PRI_9_CPU_PRI_9_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_9_MAP field. + INTPRI_CPU_INT_PRI_9_CPU_PRI_9_MAP_Msk = 0xf + + // CPU_INT_PRI_10: register description + // Position of CPU_PRI_10_MAP field. + INTPRI_CPU_INT_PRI_10_CPU_PRI_10_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_10_MAP field. + INTPRI_CPU_INT_PRI_10_CPU_PRI_10_MAP_Msk = 0xf + + // CPU_INT_PRI_11: register description + // Position of CPU_PRI_11_MAP field. + INTPRI_CPU_INT_PRI_11_CPU_PRI_11_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_11_MAP field. + INTPRI_CPU_INT_PRI_11_CPU_PRI_11_MAP_Msk = 0xf + + // CPU_INT_PRI_12: register description + // Position of CPU_PRI_12_MAP field. + INTPRI_CPU_INT_PRI_12_CPU_PRI_12_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_12_MAP field. + INTPRI_CPU_INT_PRI_12_CPU_PRI_12_MAP_Msk = 0xf + + // CPU_INT_PRI_13: register description + // Position of CPU_PRI_13_MAP field. + INTPRI_CPU_INT_PRI_13_CPU_PRI_13_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_13_MAP field. + INTPRI_CPU_INT_PRI_13_CPU_PRI_13_MAP_Msk = 0xf + + // CPU_INT_PRI_14: register description + // Position of CPU_PRI_14_MAP field. + INTPRI_CPU_INT_PRI_14_CPU_PRI_14_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_14_MAP field. + INTPRI_CPU_INT_PRI_14_CPU_PRI_14_MAP_Msk = 0xf + + // CPU_INT_PRI_15: register description + // Position of CPU_PRI_15_MAP field. + INTPRI_CPU_INT_PRI_15_CPU_PRI_15_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_15_MAP field. + INTPRI_CPU_INT_PRI_15_CPU_PRI_15_MAP_Msk = 0xf + + // CPU_INT_PRI_16: register description + // Position of CPU_PRI_16_MAP field. + INTPRI_CPU_INT_PRI_16_CPU_PRI_16_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_16_MAP field. + INTPRI_CPU_INT_PRI_16_CPU_PRI_16_MAP_Msk = 0xf + + // CPU_INT_PRI_17: register description + // Position of CPU_PRI_17_MAP field. + INTPRI_CPU_INT_PRI_17_CPU_PRI_17_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_17_MAP field. + INTPRI_CPU_INT_PRI_17_CPU_PRI_17_MAP_Msk = 0xf + + // CPU_INT_PRI_18: register description + // Position of CPU_PRI_18_MAP field. + INTPRI_CPU_INT_PRI_18_CPU_PRI_18_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_18_MAP field. + INTPRI_CPU_INT_PRI_18_CPU_PRI_18_MAP_Msk = 0xf + + // CPU_INT_PRI_19: register description + // Position of CPU_PRI_19_MAP field. + INTPRI_CPU_INT_PRI_19_CPU_PRI_19_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_19_MAP field. + INTPRI_CPU_INT_PRI_19_CPU_PRI_19_MAP_Msk = 0xf + + // CPU_INT_PRI_20: register description + // Position of CPU_PRI_20_MAP field. + INTPRI_CPU_INT_PRI_20_CPU_PRI_20_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_20_MAP field. + INTPRI_CPU_INT_PRI_20_CPU_PRI_20_MAP_Msk = 0xf + + // CPU_INT_PRI_21: register description + // Position of CPU_PRI_21_MAP field. + INTPRI_CPU_INT_PRI_21_CPU_PRI_21_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_21_MAP field. + INTPRI_CPU_INT_PRI_21_CPU_PRI_21_MAP_Msk = 0xf + + // CPU_INT_PRI_22: register description + // Position of CPU_PRI_22_MAP field. + INTPRI_CPU_INT_PRI_22_CPU_PRI_22_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_22_MAP field. + INTPRI_CPU_INT_PRI_22_CPU_PRI_22_MAP_Msk = 0xf + + // CPU_INT_PRI_23: register description + // Position of CPU_PRI_23_MAP field. + INTPRI_CPU_INT_PRI_23_CPU_PRI_23_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_23_MAP field. + INTPRI_CPU_INT_PRI_23_CPU_PRI_23_MAP_Msk = 0xf + + // CPU_INT_PRI_24: register description + // Position of CPU_PRI_24_MAP field. + INTPRI_CPU_INT_PRI_24_CPU_PRI_24_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_24_MAP field. + INTPRI_CPU_INT_PRI_24_CPU_PRI_24_MAP_Msk = 0xf + + // CPU_INT_PRI_25: register description + // Position of CPU_PRI_25_MAP field. + INTPRI_CPU_INT_PRI_25_CPU_PRI_25_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_25_MAP field. + INTPRI_CPU_INT_PRI_25_CPU_PRI_25_MAP_Msk = 0xf + + // CPU_INT_PRI_26: register description + // Position of CPU_PRI_26_MAP field. + INTPRI_CPU_INT_PRI_26_CPU_PRI_26_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_26_MAP field. + INTPRI_CPU_INT_PRI_26_CPU_PRI_26_MAP_Msk = 0xf + + // CPU_INT_PRI_27: register description + // Position of CPU_PRI_27_MAP field. + INTPRI_CPU_INT_PRI_27_CPU_PRI_27_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_27_MAP field. + INTPRI_CPU_INT_PRI_27_CPU_PRI_27_MAP_Msk = 0xf + + // CPU_INT_PRI_28: register description + // Position of CPU_PRI_28_MAP field. + INTPRI_CPU_INT_PRI_28_CPU_PRI_28_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_28_MAP field. + INTPRI_CPU_INT_PRI_28_CPU_PRI_28_MAP_Msk = 0xf + + // CPU_INT_PRI_29: register description + // Position of CPU_PRI_29_MAP field. + INTPRI_CPU_INT_PRI_29_CPU_PRI_29_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_29_MAP field. + INTPRI_CPU_INT_PRI_29_CPU_PRI_29_MAP_Msk = 0xf + + // CPU_INT_PRI_30: register description + // Position of CPU_PRI_30_MAP field. + INTPRI_CPU_INT_PRI_30_CPU_PRI_30_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_30_MAP field. + INTPRI_CPU_INT_PRI_30_CPU_PRI_30_MAP_Msk = 0xf + + // CPU_INT_PRI_31: register description + // Position of CPU_PRI_31_MAP field. + INTPRI_CPU_INT_PRI_31_CPU_PRI_31_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_31_MAP field. + INTPRI_CPU_INT_PRI_31_CPU_PRI_31_MAP_Msk = 0xf + + // CPU_INT_THRESH: register description + // Position of CPU_INT_THRESH field. + INTPRI_CPU_INT_THRESH_CPU_INT_THRESH_Pos = 0x0 + // Bit mask of CPU_INT_THRESH field. + INTPRI_CPU_INT_THRESH_CPU_INT_THRESH_Msk = 0xff + + // CPU_INTR_FROM_CPU_0: register description + // Position of CPU_INTR_FROM_CPU_0 field. + INTPRI_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0 field. + INTPRI_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_0. + INTPRI_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0 = 0x1 + + // CPU_INTR_FROM_CPU_1: register description + // Position of CPU_INTR_FROM_CPU_1 field. + INTPRI_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1 field. + INTPRI_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_1. + INTPRI_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1 = 0x1 + + // CPU_INTR_FROM_CPU_2: register description + // Position of CPU_INTR_FROM_CPU_2 field. + INTPRI_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2 field. + INTPRI_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_2. + INTPRI_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2 = 0x1 + + // CPU_INTR_FROM_CPU_3: register description + // Position of CPU_INTR_FROM_CPU_3 field. + INTPRI_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3 field. + INTPRI_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_3. + INTPRI_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3 = 0x1 + + // DATE: register description + // Position of DATE field. + INTPRI_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + INTPRI_DATE_DATE_Msk = 0xfffffff + + // CLOCK_GATE: register description + // Position of CLK_EN field. + INTPRI_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + INTPRI_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + INTPRI_CLOCK_GATE_CLK_EN = 0x1 + + // CPU_INT_CLEAR: register description + // Position of CPU_INT_CLEAR field. + INTPRI_CPU_INT_CLEAR_CPU_INT_CLEAR_Pos = 0x0 + // Bit mask of CPU_INT_CLEAR field. + INTPRI_CPU_INT_CLEAR_CPU_INT_CLEAR_Msk = 0xffffffff + + // RND_ECO: redcy eco register. + // Position of REDCY_ENA field. + INTPRI_RND_ECO_REDCY_ENA_Pos = 0x0 + // Bit mask of REDCY_ENA field. + INTPRI_RND_ECO_REDCY_ENA_Msk = 0x1 + // Bit REDCY_ENA. + INTPRI_RND_ECO_REDCY_ENA = 0x1 + // Position of REDCY_RESULT field. + INTPRI_RND_ECO_REDCY_RESULT_Pos = 0x1 + // Bit mask of REDCY_RESULT field. + INTPRI_RND_ECO_REDCY_RESULT_Msk = 0x2 + // Bit REDCY_RESULT. + INTPRI_RND_ECO_REDCY_RESULT = 0x2 + + // RND_ECO_LOW: redcy eco low register. + // Position of REDCY_LOW field. + INTPRI_RND_ECO_LOW_REDCY_LOW_Pos = 0x0 + // Bit mask of REDCY_LOW field. + INTPRI_RND_ECO_LOW_REDCY_LOW_Msk = 0xffffffff + + // RND_ECO_HIGH: redcy eco high register. + // Position of REDCY_HIGH field. + INTPRI_RND_ECO_HIGH_REDCY_HIGH_Pos = 0x0 + // Bit mask of REDCY_HIGH field. + INTPRI_RND_ECO_HIGH_REDCY_HIGH_Msk = 0xffffffff +) + +// Constants for IO_MUX: Input/Output Multiplexer +const ( + // PIN_CTRL: Clock Output Configuration Register + // Position of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Pos = 0x0 + // Bit mask of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Msk = 0x1f + // Position of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Pos = 0x5 + // Bit mask of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Msk = 0x3e0 + // Position of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Pos = 0xa + // Bit mask of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Msk = 0x7c00 + + // GPIO0: IO MUX Configure Register for pad XTAL_32K_P + // Position of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO_FILTER_EN = 0x8000 + + // MODEM_DIAG_EN: GPIO MATRIX Configure Register for modem diag + // Position of MODEM_DIAG_EN field. + IO_MUX_MODEM_DIAG_EN_MODEM_DIAG_EN_Pos = 0x0 + // Bit mask of MODEM_DIAG_EN field. + IO_MUX_MODEM_DIAG_EN_MODEM_DIAG_EN_Msk = 0xffffffff + + // DATE: IO MUX Version Control Register + // Position of REG_DATE field. + IO_MUX_DATE_REG_DATE_Pos = 0x0 + // Bit mask of REG_DATE field. + IO_MUX_DATE_REG_DATE_Msk = 0xfffffff +) + +// Constants for LEDC: LED Control PWM (Pulse Width Modulation) +const ( + // CH0_CONF0: Configuration register 0 for channel %s + // Position of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Pos = 0x0 + // Bit mask of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Msk = 0x3 + // Position of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Pos = 0x2 + // Bit mask of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Msk = 0x4 + // Bit SIG_OUT_EN. + LEDC_CH_CONF0_SIG_OUT_EN = 0x4 + // Position of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Pos = 0x3 + // Bit mask of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Msk = 0x8 + // Bit IDLE_LV. + LEDC_CH_CONF0_IDLE_LV = 0x8 + // Position of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Pos = 0x4 + // Bit mask of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Msk = 0x10 + // Bit PARA_UP. + LEDC_CH_CONF0_PARA_UP = 0x10 + // Position of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Pos = 0x5 + // Bit mask of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Msk = 0x7fe0 + // Position of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Pos = 0xf + // Bit mask of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Msk = 0x8000 + // Bit OVF_CNT_EN. + LEDC_CH_CONF0_OVF_CNT_EN = 0x8000 + // Position of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Pos = 0x10 + // Bit mask of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Msk = 0x10000 + // Bit OVF_CNT_RESET. + LEDC_CH_CONF0_OVF_CNT_RESET = 0x10000 + + // CH0_HPOINT: High point register for channel %s + // Position of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Pos = 0x0 + // Bit mask of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Msk = 0xfffff + + // CH0_DUTY: Initial duty cycle for channel %s + // Position of DUTY field. + LEDC_CH_DUTY_DUTY_Pos = 0x0 + // Bit mask of DUTY field. + LEDC_CH_DUTY_DUTY_Msk = 0x1ffffff + + // CH0_CONF1: Configuration register 1 for channel %s + // Position of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Pos = 0x1f + // Bit mask of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Msk = 0x80000000 + // Bit DUTY_START. + LEDC_CH_CONF1_DUTY_START = 0x80000000 + + // CH0_DUTY_R: Current duty cycle for channel %s + // Position of DUTY_CH_R field. + LEDC_CH_DUTY_R_DUTY_CH_R_Pos = 0x0 + // Bit mask of DUTY_CH_R field. + LEDC_CH_DUTY_R_DUTY_CH_R_Msk = 0x1ffffff + + // TIMER0_CONF: Timer %s configuration + // Position of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Pos = 0x0 + // Bit mask of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Msk = 0x1f + // Position of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Pos = 0x5 + // Bit mask of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Msk = 0x7fffe0 + // Position of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Pos = 0x17 + // Bit mask of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Msk = 0x800000 + // Bit PAUSE. + LEDC_TIMER_CONF_PAUSE = 0x800000 + // Position of RST field. + LEDC_TIMER_CONF_RST_Pos = 0x18 + // Bit mask of RST field. + LEDC_TIMER_CONF_RST_Msk = 0x1000000 + // Bit RST. + LEDC_TIMER_CONF_RST = 0x1000000 + // Position of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Pos = 0x19 + // Bit mask of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Msk = 0x2000000 + // Bit TICK_SEL. + LEDC_TIMER_CONF_TICK_SEL = 0x2000000 + // Position of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Pos = 0x1a + // Bit mask of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Msk = 0x4000000 + // Bit PARA_UP. + LEDC_TIMER_CONF_PARA_UP = 0x4000000 + + // TIMER0_VALUE: Timer %s current counter value + // Position of TIMER_CNT field. + LEDC_TIMER_VALUE_TIMER_CNT_Pos = 0x0 + // Bit mask of TIMER_CNT field. + LEDC_TIMER_VALUE_TIMER_CNT_Msk = 0xfffff + + // INT_RAW: Raw interrupt status + // Position of TIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Msk = 0x1 + // Bit TIMER0_OVF_INT_RAW. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW = 0x1 + // Position of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Msk = 0x2 + // Bit TIMER1_OVF_INT_RAW. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW = 0x2 + // Position of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Msk = 0x4 + // Bit TIMER2_OVF_INT_RAW. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW = 0x4 + // Position of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Msk = 0x8 + // Bit TIMER3_OVF_INT_RAW. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW = 0x200 + // Position of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW = 0x1000 + // Position of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW = 0x2000 + // Position of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW = 0x4000 + // Position of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW = 0x8000 + // Position of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW = 0x10000 + // Position of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW = 0x20000 + + // INT_ST: Masked interrupt status + // Position of TIMER0_OVF_INT_ST field. + LEDC_INT_ST_TIMER0_OVF_INT_ST_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_ST field. + LEDC_INT_ST_TIMER0_OVF_INT_ST_Msk = 0x1 + // Bit TIMER0_OVF_INT_ST. + LEDC_INT_ST_TIMER0_OVF_INT_ST = 0x1 + // Position of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Msk = 0x2 + // Bit TIMER1_OVF_INT_ST. + LEDC_INT_ST_TIMER1_OVF_INT_ST = 0x2 + // Position of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Msk = 0x4 + // Bit TIMER2_OVF_INT_ST. + LEDC_INT_ST_TIMER2_OVF_INT_ST = 0x4 + // Position of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Msk = 0x8 + // Bit TIMER3_OVF_INT_ST. + LEDC_INT_ST_TIMER3_OVF_INT_ST = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST = 0x200 + // Position of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_ST. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST = 0x1000 + // Position of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_ST. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST = 0x2000 + // Position of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_ST. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST = 0x4000 + // Position of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_ST. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST = 0x8000 + // Position of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_ST. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST = 0x10000 + // Position of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_ST. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST = 0x20000 + + // INT_ENA: Interrupt enable bits + // Position of TIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Msk = 0x1 + // Bit TIMER0_OVF_INT_ENA. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA = 0x1 + // Position of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Msk = 0x2 + // Bit TIMER1_OVF_INT_ENA. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA = 0x2 + // Position of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Msk = 0x4 + // Bit TIMER2_OVF_INT_ENA. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA = 0x4 + // Position of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Msk = 0x8 + // Bit TIMER3_OVF_INT_ENA. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA = 0x200 + // Position of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA = 0x1000 + // Position of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA = 0x2000 + // Position of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA = 0x4000 + // Position of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA = 0x8000 + // Position of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA = 0x10000 + // Position of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA = 0x20000 + + // INT_CLR: Interrupt clear bits + // Position of TIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Msk = 0x1 + // Bit TIMER0_OVF_INT_CLR. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR = 0x1 + // Position of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Msk = 0x2 + // Bit TIMER1_OVF_INT_CLR. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR = 0x2 + // Position of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Msk = 0x4 + // Bit TIMER2_OVF_INT_CLR. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR = 0x4 + // Position of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Msk = 0x8 + // Bit TIMER3_OVF_INT_CLR. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR = 0x200 + // Position of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR = 0x1000 + // Position of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR = 0x2000 + // Position of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR = 0x4000 + // Position of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR = 0x8000 + // Position of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR = 0x10000 + // Position of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR = 0x20000 + + // CH0_GAMMA_WR: Ledc ch%s gamma ram write register. + // Position of CH_GAMMA_DUTY_INC field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_INC_Pos = 0x0 + // Bit mask of CH_GAMMA_DUTY_INC field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_INC_Msk = 0x1 + // Bit CH_GAMMA_DUTY_INC. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_INC = 0x1 + // Position of CH_GAMMA_DUTY_CYCLE field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_CYCLE_Pos = 0x1 + // Bit mask of CH_GAMMA_DUTY_CYCLE field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_CYCLE_Msk = 0x7fe + // Position of CH_GAMMA_SCALE field. + LEDC_CH_GAMMA_WR_CH_GAMMA_SCALE_Pos = 0xb + // Bit mask of CH_GAMMA_SCALE field. + LEDC_CH_GAMMA_WR_CH_GAMMA_SCALE_Msk = 0x1ff800 + // Position of CH_GAMMA_DUTY_NUM field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_NUM_Pos = 0x15 + // Bit mask of CH_GAMMA_DUTY_NUM field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_NUM_Msk = 0x7fe00000 + + // CH0_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. + // Position of CH_GAMMA_WR_ADDR field. + LEDC_CH_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR_Pos = 0x0 + // Bit mask of CH_GAMMA_WR_ADDR field. + LEDC_CH_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR_Msk = 0xf + + // CH0_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. + // Position of CH_GAMMA_RD_ADDR field. + LEDC_CH_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR_Pos = 0x0 + // Bit mask of CH_GAMMA_RD_ADDR field. + LEDC_CH_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR_Msk = 0xf + + // CH0_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. + // Position of CH_GAMMA_RD_DATA field. + LEDC_CH_GAMMA_RD_DATA_CH_GAMMA_RD_DATA_Pos = 0x0 + // Bit mask of CH_GAMMA_RD_DATA field. + LEDC_CH_GAMMA_RD_DATA_CH_GAMMA_RD_DATA_Msk = 0x7fffffff + + // CH0_GAMMA_CONF: Ledc ch%s gamma config register. + // Position of CH_GAMMA_ENTRY_NUM field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_ENTRY_NUM_Pos = 0x0 + // Bit mask of CH_GAMMA_ENTRY_NUM field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_ENTRY_NUM_Msk = 0x1f + // Position of CH_GAMMA_PAUSE field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_PAUSE_Pos = 0x5 + // Bit mask of CH_GAMMA_PAUSE field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_PAUSE_Msk = 0x20 + // Bit CH_GAMMA_PAUSE. + LEDC_CH_GAMMA_CONF_CH_GAMMA_PAUSE = 0x20 + // Position of CH_GAMMA_RESUME field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_RESUME_Pos = 0x6 + // Bit mask of CH_GAMMA_RESUME field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_RESUME_Msk = 0x40 + // Bit CH_GAMMA_RESUME. + LEDC_CH_GAMMA_CONF_CH_GAMMA_RESUME = 0x40 + + // EVT_TASK_EN0: Ledc event task enable bit register0. + // Position of EVT_DUTY_CHNG_END_CH0_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN_Pos = 0x0 + // Bit mask of EVT_DUTY_CHNG_END_CH0_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN_Msk = 0x1 + // Bit EVT_DUTY_CHNG_END_CH0_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN = 0x1 + // Position of EVT_DUTY_CHNG_END_CH1_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN_Pos = 0x1 + // Bit mask of EVT_DUTY_CHNG_END_CH1_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN_Msk = 0x2 + // Bit EVT_DUTY_CHNG_END_CH1_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN = 0x2 + // Position of EVT_DUTY_CHNG_END_CH2_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN_Pos = 0x2 + // Bit mask of EVT_DUTY_CHNG_END_CH2_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN_Msk = 0x4 + // Bit EVT_DUTY_CHNG_END_CH2_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN = 0x4 + // Position of EVT_DUTY_CHNG_END_CH3_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN_Pos = 0x3 + // Bit mask of EVT_DUTY_CHNG_END_CH3_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN_Msk = 0x8 + // Bit EVT_DUTY_CHNG_END_CH3_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN = 0x8 + // Position of EVT_DUTY_CHNG_END_CH4_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN_Pos = 0x4 + // Bit mask of EVT_DUTY_CHNG_END_CH4_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN_Msk = 0x10 + // Bit EVT_DUTY_CHNG_END_CH4_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN = 0x10 + // Position of EVT_DUTY_CHNG_END_CH5_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN_Pos = 0x5 + // Bit mask of EVT_DUTY_CHNG_END_CH5_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN_Msk = 0x20 + // Bit EVT_DUTY_CHNG_END_CH5_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN = 0x20 + // Position of EVT_OVF_CNT_PLS_CH0_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN_Pos = 0x8 + // Bit mask of EVT_OVF_CNT_PLS_CH0_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN_Msk = 0x100 + // Bit EVT_OVF_CNT_PLS_CH0_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN = 0x100 + // Position of EVT_OVF_CNT_PLS_CH1_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN_Pos = 0x9 + // Bit mask of EVT_OVF_CNT_PLS_CH1_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN_Msk = 0x200 + // Bit EVT_OVF_CNT_PLS_CH1_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN = 0x200 + // Position of EVT_OVF_CNT_PLS_CH2_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN_Pos = 0xa + // Bit mask of EVT_OVF_CNT_PLS_CH2_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN_Msk = 0x400 + // Bit EVT_OVF_CNT_PLS_CH2_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN = 0x400 + // Position of EVT_OVF_CNT_PLS_CH3_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN_Pos = 0xb + // Bit mask of EVT_OVF_CNT_PLS_CH3_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN_Msk = 0x800 + // Bit EVT_OVF_CNT_PLS_CH3_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN = 0x800 + // Position of EVT_OVF_CNT_PLS_CH4_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN_Pos = 0xc + // Bit mask of EVT_OVF_CNT_PLS_CH4_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN_Msk = 0x1000 + // Bit EVT_OVF_CNT_PLS_CH4_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN = 0x1000 + // Position of EVT_OVF_CNT_PLS_CH5_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN_Pos = 0xd + // Bit mask of EVT_OVF_CNT_PLS_CH5_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN_Msk = 0x2000 + // Bit EVT_OVF_CNT_PLS_CH5_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN = 0x2000 + // Position of EVT_TIME_OVF_TIMER0_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN_Pos = 0x10 + // Bit mask of EVT_TIME_OVF_TIMER0_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN_Msk = 0x10000 + // Bit EVT_TIME_OVF_TIMER0_EN. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN = 0x10000 + // Position of EVT_TIME_OVF_TIMER1_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN_Pos = 0x11 + // Bit mask of EVT_TIME_OVF_TIMER1_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN_Msk = 0x20000 + // Bit EVT_TIME_OVF_TIMER1_EN. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN = 0x20000 + // Position of EVT_TIME_OVF_TIMER2_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN_Pos = 0x12 + // Bit mask of EVT_TIME_OVF_TIMER2_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN_Msk = 0x40000 + // Bit EVT_TIME_OVF_TIMER2_EN. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN = 0x40000 + // Position of EVT_TIME_OVF_TIMER3_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN_Pos = 0x13 + // Bit mask of EVT_TIME_OVF_TIMER3_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN_Msk = 0x80000 + // Bit EVT_TIME_OVF_TIMER3_EN. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN = 0x80000 + // Position of EVT_TIME0_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME0_CMP_EN_Pos = 0x14 + // Bit mask of EVT_TIME0_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME0_CMP_EN_Msk = 0x100000 + // Bit EVT_TIME0_CMP_EN. + LEDC_EVT_TASK_EN0_EVT_TIME0_CMP_EN = 0x100000 + // Position of EVT_TIME1_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME1_CMP_EN_Pos = 0x15 + // Bit mask of EVT_TIME1_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME1_CMP_EN_Msk = 0x200000 + // Bit EVT_TIME1_CMP_EN. + LEDC_EVT_TASK_EN0_EVT_TIME1_CMP_EN = 0x200000 + // Position of EVT_TIME2_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME2_CMP_EN_Pos = 0x16 + // Bit mask of EVT_TIME2_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME2_CMP_EN_Msk = 0x400000 + // Bit EVT_TIME2_CMP_EN. + LEDC_EVT_TASK_EN0_EVT_TIME2_CMP_EN = 0x400000 + // Position of EVT_TIME3_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME3_CMP_EN_Pos = 0x17 + // Bit mask of EVT_TIME3_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME3_CMP_EN_Msk = 0x800000 + // Bit EVT_TIME3_CMP_EN. + LEDC_EVT_TASK_EN0_EVT_TIME3_CMP_EN = 0x800000 + // Position of TASK_DUTY_SCALE_UPDATE_CH0_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN_Pos = 0x18 + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH0_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN_Msk = 0x1000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH0_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN = 0x1000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH1_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN_Pos = 0x19 + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH1_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN_Msk = 0x2000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH1_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN = 0x2000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH2_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN_Pos = 0x1a + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH2_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN_Msk = 0x4000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH2_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN = 0x4000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH3_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN_Pos = 0x1b + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH3_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN_Msk = 0x8000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH3_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN = 0x8000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH4_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN_Pos = 0x1c + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH4_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN_Msk = 0x10000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH4_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN = 0x10000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH5_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN_Pos = 0x1d + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH5_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN_Msk = 0x20000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH5_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN = 0x20000000 + + // EVT_TASK_EN1: Ledc event task enable bit register1. + // Position of TASK_TIMER0_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN_Pos = 0x0 + // Bit mask of TASK_TIMER0_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN_Msk = 0x1 + // Bit TASK_TIMER0_RES_UPDATE_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN = 0x1 + // Position of TASK_TIMER1_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN_Pos = 0x1 + // Bit mask of TASK_TIMER1_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN_Msk = 0x2 + // Bit TASK_TIMER1_RES_UPDATE_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN = 0x2 + // Position of TASK_TIMER2_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN_Pos = 0x2 + // Bit mask of TASK_TIMER2_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN_Msk = 0x4 + // Bit TASK_TIMER2_RES_UPDATE_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN = 0x4 + // Position of TASK_TIMER3_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN_Pos = 0x3 + // Bit mask of TASK_TIMER3_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN_Msk = 0x8 + // Bit TASK_TIMER3_RES_UPDATE_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN = 0x8 + // Position of TASK_TIMER0_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_CAP_EN_Pos = 0x4 + // Bit mask of TASK_TIMER0_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_CAP_EN_Msk = 0x10 + // Bit TASK_TIMER0_CAP_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER0_CAP_EN = 0x10 + // Position of TASK_TIMER1_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_CAP_EN_Pos = 0x5 + // Bit mask of TASK_TIMER1_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_CAP_EN_Msk = 0x20 + // Bit TASK_TIMER1_CAP_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER1_CAP_EN = 0x20 + // Position of TASK_TIMER2_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_CAP_EN_Pos = 0x6 + // Bit mask of TASK_TIMER2_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_CAP_EN_Msk = 0x40 + // Bit TASK_TIMER2_CAP_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER2_CAP_EN = 0x40 + // Position of TASK_TIMER3_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_CAP_EN_Pos = 0x7 + // Bit mask of TASK_TIMER3_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_CAP_EN_Msk = 0x80 + // Bit TASK_TIMER3_CAP_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER3_CAP_EN = 0x80 + // Position of TASK_SIG_OUT_DIS_CH0_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN_Pos = 0x8 + // Bit mask of TASK_SIG_OUT_DIS_CH0_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN_Msk = 0x100 + // Bit TASK_SIG_OUT_DIS_CH0_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN = 0x100 + // Position of TASK_SIG_OUT_DIS_CH1_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN_Pos = 0x9 + // Bit mask of TASK_SIG_OUT_DIS_CH1_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN_Msk = 0x200 + // Bit TASK_SIG_OUT_DIS_CH1_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN = 0x200 + // Position of TASK_SIG_OUT_DIS_CH2_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN_Pos = 0xa + // Bit mask of TASK_SIG_OUT_DIS_CH2_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN_Msk = 0x400 + // Bit TASK_SIG_OUT_DIS_CH2_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN = 0x400 + // Position of TASK_SIG_OUT_DIS_CH3_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN_Pos = 0xb + // Bit mask of TASK_SIG_OUT_DIS_CH3_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN_Msk = 0x800 + // Bit TASK_SIG_OUT_DIS_CH3_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN = 0x800 + // Position of TASK_SIG_OUT_DIS_CH4_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN_Pos = 0xc + // Bit mask of TASK_SIG_OUT_DIS_CH4_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN_Msk = 0x1000 + // Bit TASK_SIG_OUT_DIS_CH4_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN = 0x1000 + // Position of TASK_SIG_OUT_DIS_CH5_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN_Pos = 0xd + // Bit mask of TASK_SIG_OUT_DIS_CH5_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN_Msk = 0x2000 + // Bit TASK_SIG_OUT_DIS_CH5_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN = 0x2000 + // Position of TASK_OVF_CNT_RST_CH0_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN_Pos = 0x10 + // Bit mask of TASK_OVF_CNT_RST_CH0_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN_Msk = 0x10000 + // Bit TASK_OVF_CNT_RST_CH0_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN = 0x10000 + // Position of TASK_OVF_CNT_RST_CH1_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN_Pos = 0x11 + // Bit mask of TASK_OVF_CNT_RST_CH1_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN_Msk = 0x20000 + // Bit TASK_OVF_CNT_RST_CH1_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN = 0x20000 + // Position of TASK_OVF_CNT_RST_CH2_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN_Pos = 0x12 + // Bit mask of TASK_OVF_CNT_RST_CH2_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN_Msk = 0x40000 + // Bit TASK_OVF_CNT_RST_CH2_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN = 0x40000 + // Position of TASK_OVF_CNT_RST_CH3_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN_Pos = 0x13 + // Bit mask of TASK_OVF_CNT_RST_CH3_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN_Msk = 0x80000 + // Bit TASK_OVF_CNT_RST_CH3_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN = 0x80000 + // Position of TASK_OVF_CNT_RST_CH4_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN_Pos = 0x14 + // Bit mask of TASK_OVF_CNT_RST_CH4_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN_Msk = 0x100000 + // Bit TASK_OVF_CNT_RST_CH4_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN = 0x100000 + // Position of TASK_OVF_CNT_RST_CH5_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN_Pos = 0x15 + // Bit mask of TASK_OVF_CNT_RST_CH5_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN_Msk = 0x200000 + // Bit TASK_OVF_CNT_RST_CH5_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN = 0x200000 + // Position of TASK_TIMER0_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RST_EN_Pos = 0x18 + // Bit mask of TASK_TIMER0_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RST_EN_Msk = 0x1000000 + // Bit TASK_TIMER0_RST_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RST_EN = 0x1000000 + // Position of TASK_TIMER1_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RST_EN_Pos = 0x19 + // Bit mask of TASK_TIMER1_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RST_EN_Msk = 0x2000000 + // Bit TASK_TIMER1_RST_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RST_EN = 0x2000000 + // Position of TASK_TIMER2_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RST_EN_Pos = 0x1a + // Bit mask of TASK_TIMER2_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RST_EN_Msk = 0x4000000 + // Bit TASK_TIMER2_RST_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RST_EN = 0x4000000 + // Position of TASK_TIMER3_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RST_EN_Pos = 0x1b + // Bit mask of TASK_TIMER3_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RST_EN_Msk = 0x8000000 + // Bit TASK_TIMER3_RST_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RST_EN = 0x8000000 + // Position of TASK_TIMER0_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN_Pos = 0x1c + // Bit mask of TASK_TIMER0_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN_Msk = 0x10000000 + // Bit TASK_TIMER0_PAUSE_RESUME_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN = 0x10000000 + // Position of TASK_TIMER1_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN_Pos = 0x1d + // Bit mask of TASK_TIMER1_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN_Msk = 0x20000000 + // Bit TASK_TIMER1_PAUSE_RESUME_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN = 0x20000000 + // Position of TASK_TIMER2_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN_Pos = 0x1e + // Bit mask of TASK_TIMER2_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN_Msk = 0x40000000 + // Bit TASK_TIMER2_PAUSE_RESUME_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN = 0x40000000 + // Position of TASK_TIMER3_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN_Pos = 0x1f + // Bit mask of TASK_TIMER3_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN_Msk = 0x80000000 + // Bit TASK_TIMER3_PAUSE_RESUME_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN = 0x80000000 + + // EVT_TASK_EN2: Ledc event task enable bit register2. + // Position of TASK_GAMMA_RESTART_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN_Pos = 0x0 + // Bit mask of TASK_GAMMA_RESTART_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN_Msk = 0x1 + // Bit TASK_GAMMA_RESTART_CH0_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN = 0x1 + // Position of TASK_GAMMA_RESTART_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN_Pos = 0x1 + // Bit mask of TASK_GAMMA_RESTART_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN_Msk = 0x2 + // Bit TASK_GAMMA_RESTART_CH1_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN = 0x2 + // Position of TASK_GAMMA_RESTART_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN_Pos = 0x2 + // Bit mask of TASK_GAMMA_RESTART_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN_Msk = 0x4 + // Bit TASK_GAMMA_RESTART_CH2_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN = 0x4 + // Position of TASK_GAMMA_RESTART_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN_Pos = 0x3 + // Bit mask of TASK_GAMMA_RESTART_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN_Msk = 0x8 + // Bit TASK_GAMMA_RESTART_CH3_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN = 0x8 + // Position of TASK_GAMMA_RESTART_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN_Pos = 0x4 + // Bit mask of TASK_GAMMA_RESTART_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN_Msk = 0x10 + // Bit TASK_GAMMA_RESTART_CH4_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN = 0x10 + // Position of TASK_GAMMA_RESTART_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN_Pos = 0x5 + // Bit mask of TASK_GAMMA_RESTART_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN_Msk = 0x20 + // Bit TASK_GAMMA_RESTART_CH5_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN = 0x20 + // Position of TASK_GAMMA_PAUSE_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN_Pos = 0x8 + // Bit mask of TASK_GAMMA_PAUSE_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN_Msk = 0x100 + // Bit TASK_GAMMA_PAUSE_CH0_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN = 0x100 + // Position of TASK_GAMMA_PAUSE_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN_Pos = 0x9 + // Bit mask of TASK_GAMMA_PAUSE_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN_Msk = 0x200 + // Bit TASK_GAMMA_PAUSE_CH1_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN = 0x200 + // Position of TASK_GAMMA_PAUSE_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN_Pos = 0xa + // Bit mask of TASK_GAMMA_PAUSE_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN_Msk = 0x400 + // Bit TASK_GAMMA_PAUSE_CH2_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN = 0x400 + // Position of TASK_GAMMA_PAUSE_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN_Pos = 0xb + // Bit mask of TASK_GAMMA_PAUSE_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN_Msk = 0x800 + // Bit TASK_GAMMA_PAUSE_CH3_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN = 0x800 + // Position of TASK_GAMMA_PAUSE_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN_Pos = 0xc + // Bit mask of TASK_GAMMA_PAUSE_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN_Msk = 0x1000 + // Bit TASK_GAMMA_PAUSE_CH4_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN = 0x1000 + // Position of TASK_GAMMA_PAUSE_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN_Pos = 0xd + // Bit mask of TASK_GAMMA_PAUSE_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN_Msk = 0x2000 + // Bit TASK_GAMMA_PAUSE_CH5_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN = 0x2000 + // Position of TASK_GAMMA_RESUME_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN_Pos = 0x10 + // Bit mask of TASK_GAMMA_RESUME_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN_Msk = 0x10000 + // Bit TASK_GAMMA_RESUME_CH0_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN = 0x10000 + // Position of TASK_GAMMA_RESUME_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN_Pos = 0x11 + // Bit mask of TASK_GAMMA_RESUME_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN_Msk = 0x20000 + // Bit TASK_GAMMA_RESUME_CH1_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN = 0x20000 + // Position of TASK_GAMMA_RESUME_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN_Pos = 0x12 + // Bit mask of TASK_GAMMA_RESUME_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN_Msk = 0x40000 + // Bit TASK_GAMMA_RESUME_CH2_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN = 0x40000 + // Position of TASK_GAMMA_RESUME_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN_Pos = 0x13 + // Bit mask of TASK_GAMMA_RESUME_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN_Msk = 0x80000 + // Bit TASK_GAMMA_RESUME_CH3_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN = 0x80000 + // Position of TASK_GAMMA_RESUME_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN_Pos = 0x14 + // Bit mask of TASK_GAMMA_RESUME_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN_Msk = 0x100000 + // Bit TASK_GAMMA_RESUME_CH4_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN = 0x100000 + // Position of TASK_GAMMA_RESUME_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN_Pos = 0x15 + // Bit mask of TASK_GAMMA_RESUME_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN_Msk = 0x200000 + // Bit TASK_GAMMA_RESUME_CH5_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN = 0x200000 + + // TIMER0_CMP: Ledc timer%s compare value register. + // Position of TIMER_CMP field. + LEDC_TIMER_CMP_TIMER_CMP_Pos = 0x0 + // Bit mask of TIMER_CMP field. + LEDC_TIMER_CMP_TIMER_CMP_Msk = 0xfffff + + // TIMER0_CNT_CAP: Ledc timer%s count value capture register. + // Position of TIMER_CNT_CAP field. + LEDC_TIMER_CNT_CAP_TIMER_CNT_CAP_Pos = 0x0 + // Bit mask of TIMER_CNT_CAP field. + LEDC_TIMER_CNT_CAP_TIMER_CNT_CAP_Msk = 0xfffff + + // CONF: Global ledc configuration register + // Position of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Pos = 0x0 + // Bit mask of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Msk = 0x3 + // Position of GAMMA_RAM_CLK_EN_CH0 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH0_Pos = 0x2 + // Bit mask of GAMMA_RAM_CLK_EN_CH0 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH0_Msk = 0x4 + // Bit GAMMA_RAM_CLK_EN_CH0. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH0 = 0x4 + // Position of GAMMA_RAM_CLK_EN_CH1 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH1_Pos = 0x3 + // Bit mask of GAMMA_RAM_CLK_EN_CH1 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH1_Msk = 0x8 + // Bit GAMMA_RAM_CLK_EN_CH1. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH1 = 0x8 + // Position of GAMMA_RAM_CLK_EN_CH2 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH2_Pos = 0x4 + // Bit mask of GAMMA_RAM_CLK_EN_CH2 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH2_Msk = 0x10 + // Bit GAMMA_RAM_CLK_EN_CH2. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH2 = 0x10 + // Position of GAMMA_RAM_CLK_EN_CH3 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH3_Pos = 0x5 + // Bit mask of GAMMA_RAM_CLK_EN_CH3 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH3_Msk = 0x20 + // Bit GAMMA_RAM_CLK_EN_CH3. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH3 = 0x20 + // Position of GAMMA_RAM_CLK_EN_CH4 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH4_Pos = 0x6 + // Bit mask of GAMMA_RAM_CLK_EN_CH4 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH4_Msk = 0x40 + // Bit GAMMA_RAM_CLK_EN_CH4. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH4 = 0x40 + // Position of GAMMA_RAM_CLK_EN_CH5 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH5_Pos = 0x7 + // Bit mask of GAMMA_RAM_CLK_EN_CH5 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH5_Msk = 0x80 + // Bit GAMMA_RAM_CLK_EN_CH5. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH5 = 0x80 + // Position of CLK_EN field. + LEDC_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LEDC_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LEDC_CONF_CLK_EN = 0x80000000 + + // DATE: Version control register + // Position of LEDC_DATE field. + LEDC_DATE_LEDC_DATE_Pos = 0x0 + // Bit mask of LEDC_DATE field. + LEDC_DATE_LEDC_DATE_Msk = 0xfffffff +) + +// Constants for LP_PERI: LP_PERI Peripheral +const ( + // CLK_EN: need_des + // Position of LP_TOUCH_CK_EN field. + LPPERI_CLK_EN_LP_TOUCH_CK_EN_Pos = 0x17 + // Bit mask of LP_TOUCH_CK_EN field. + LPPERI_CLK_EN_LP_TOUCH_CK_EN_Msk = 0x800000 + // Bit LP_TOUCH_CK_EN. + LPPERI_CLK_EN_LP_TOUCH_CK_EN = 0x800000 + // Position of RNG_CK_EN field. + LPPERI_CLK_EN_RNG_CK_EN_Pos = 0x18 + // Bit mask of RNG_CK_EN field. + LPPERI_CLK_EN_RNG_CK_EN_Msk = 0x1000000 + // Bit RNG_CK_EN. + LPPERI_CLK_EN_RNG_CK_EN = 0x1000000 + // Position of OTP_DBG_CK_EN field. + LPPERI_CLK_EN_OTP_DBG_CK_EN_Pos = 0x19 + // Bit mask of OTP_DBG_CK_EN field. + LPPERI_CLK_EN_OTP_DBG_CK_EN_Msk = 0x2000000 + // Bit OTP_DBG_CK_EN. + LPPERI_CLK_EN_OTP_DBG_CK_EN = 0x2000000 + // Position of LP_UART_CK_EN field. + LPPERI_CLK_EN_LP_UART_CK_EN_Pos = 0x1a + // Bit mask of LP_UART_CK_EN field. + LPPERI_CLK_EN_LP_UART_CK_EN_Msk = 0x4000000 + // Bit LP_UART_CK_EN. + LPPERI_CLK_EN_LP_UART_CK_EN = 0x4000000 + // Position of LP_IO_CK_EN field. + LPPERI_CLK_EN_LP_IO_CK_EN_Pos = 0x1b + // Bit mask of LP_IO_CK_EN field. + LPPERI_CLK_EN_LP_IO_CK_EN_Msk = 0x8000000 + // Bit LP_IO_CK_EN. + LPPERI_CLK_EN_LP_IO_CK_EN = 0x8000000 + // Position of LP_EXT_I2C_CK_EN field. + LPPERI_CLK_EN_LP_EXT_I2C_CK_EN_Pos = 0x1c + // Bit mask of LP_EXT_I2C_CK_EN field. + LPPERI_CLK_EN_LP_EXT_I2C_CK_EN_Msk = 0x10000000 + // Bit LP_EXT_I2C_CK_EN. + LPPERI_CLK_EN_LP_EXT_I2C_CK_EN = 0x10000000 + // Position of LP_ANA_I2C_CK_EN field. + LPPERI_CLK_EN_LP_ANA_I2C_CK_EN_Pos = 0x1d + // Bit mask of LP_ANA_I2C_CK_EN field. + LPPERI_CLK_EN_LP_ANA_I2C_CK_EN_Msk = 0x20000000 + // Bit LP_ANA_I2C_CK_EN. + LPPERI_CLK_EN_LP_ANA_I2C_CK_EN = 0x20000000 + // Position of EFUSE_CK_EN field. + LPPERI_CLK_EN_EFUSE_CK_EN_Pos = 0x1e + // Bit mask of EFUSE_CK_EN field. + LPPERI_CLK_EN_EFUSE_CK_EN_Msk = 0x40000000 + // Bit EFUSE_CK_EN. + LPPERI_CLK_EN_EFUSE_CK_EN = 0x40000000 + // Position of LP_CPU_CK_EN field. + LPPERI_CLK_EN_LP_CPU_CK_EN_Pos = 0x1f + // Bit mask of LP_CPU_CK_EN field. + LPPERI_CLK_EN_LP_CPU_CK_EN_Msk = 0x80000000 + // Bit LP_CPU_CK_EN. + LPPERI_CLK_EN_LP_CPU_CK_EN = 0x80000000 + + // RESET_EN: need_des + // Position of BUS_RESET_EN field. + LPPERI_RESET_EN_BUS_RESET_EN_Pos = 0x17 + // Bit mask of BUS_RESET_EN field. + LPPERI_RESET_EN_BUS_RESET_EN_Msk = 0x800000 + // Bit BUS_RESET_EN. + LPPERI_RESET_EN_BUS_RESET_EN = 0x800000 + // Position of LP_TOUCH_RESET_EN field. + LPPERI_RESET_EN_LP_TOUCH_RESET_EN_Pos = 0x18 + // Bit mask of LP_TOUCH_RESET_EN field. + LPPERI_RESET_EN_LP_TOUCH_RESET_EN_Msk = 0x1000000 + // Bit LP_TOUCH_RESET_EN. + LPPERI_RESET_EN_LP_TOUCH_RESET_EN = 0x1000000 + // Position of OTP_DBG_RESET_EN field. + LPPERI_RESET_EN_OTP_DBG_RESET_EN_Pos = 0x19 + // Bit mask of OTP_DBG_RESET_EN field. + LPPERI_RESET_EN_OTP_DBG_RESET_EN_Msk = 0x2000000 + // Bit OTP_DBG_RESET_EN. + LPPERI_RESET_EN_OTP_DBG_RESET_EN = 0x2000000 + // Position of LP_UART_RESET_EN field. + LPPERI_RESET_EN_LP_UART_RESET_EN_Pos = 0x1a + // Bit mask of LP_UART_RESET_EN field. + LPPERI_RESET_EN_LP_UART_RESET_EN_Msk = 0x4000000 + // Bit LP_UART_RESET_EN. + LPPERI_RESET_EN_LP_UART_RESET_EN = 0x4000000 + // Position of LP_IO_RESET_EN field. + LPPERI_RESET_EN_LP_IO_RESET_EN_Pos = 0x1b + // Bit mask of LP_IO_RESET_EN field. + LPPERI_RESET_EN_LP_IO_RESET_EN_Msk = 0x8000000 + // Bit LP_IO_RESET_EN. + LPPERI_RESET_EN_LP_IO_RESET_EN = 0x8000000 + // Position of LP_EXT_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_EXT_I2C_RESET_EN_Pos = 0x1c + // Bit mask of LP_EXT_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_EXT_I2C_RESET_EN_Msk = 0x10000000 + // Bit LP_EXT_I2C_RESET_EN. + LPPERI_RESET_EN_LP_EXT_I2C_RESET_EN = 0x10000000 + // Position of LP_ANA_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_ANA_I2C_RESET_EN_Pos = 0x1d + // Bit mask of LP_ANA_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_ANA_I2C_RESET_EN_Msk = 0x20000000 + // Bit LP_ANA_I2C_RESET_EN. + LPPERI_RESET_EN_LP_ANA_I2C_RESET_EN = 0x20000000 + // Position of EFUSE_RESET_EN field. + LPPERI_RESET_EN_EFUSE_RESET_EN_Pos = 0x1e + // Bit mask of EFUSE_RESET_EN field. + LPPERI_RESET_EN_EFUSE_RESET_EN_Msk = 0x40000000 + // Bit EFUSE_RESET_EN. + LPPERI_RESET_EN_EFUSE_RESET_EN = 0x40000000 + // Position of LP_CPU_RESET_EN field. + LPPERI_RESET_EN_LP_CPU_RESET_EN_Pos = 0x1f + // Bit mask of LP_CPU_RESET_EN field. + LPPERI_RESET_EN_LP_CPU_RESET_EN_Msk = 0x80000000 + // Bit LP_CPU_RESET_EN. + LPPERI_RESET_EN_LP_CPU_RESET_EN = 0x80000000 + + // RNG_DATA: need_des + // Position of RND_DATA field. + LPPERI_RNG_DATA_RND_DATA_Pos = 0x0 + // Bit mask of RND_DATA field. + LPPERI_RNG_DATA_RND_DATA_Msk = 0xffffffff + + // CPU: need_des + // Position of LPCORE_DBGM_UNAVALIABLE field. + LPPERI_CPU_LPCORE_DBGM_UNAVALIABLE_Pos = 0x1f + // Bit mask of LPCORE_DBGM_UNAVALIABLE field. + LPPERI_CPU_LPCORE_DBGM_UNAVALIABLE_Msk = 0x80000000 + // Bit LPCORE_DBGM_UNAVALIABLE. + LPPERI_CPU_LPCORE_DBGM_UNAVALIABLE = 0x80000000 + + // BUS_TIMEOUT: need_des + // Position of LP_PERI_TIMEOUT_THRES field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_THRES_Pos = 0xe + // Bit mask of LP_PERI_TIMEOUT_THRES field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_THRES_Msk = 0x3fffc000 + // Position of LP_PERI_TIMEOUT_INT_CLEAR field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR_Pos = 0x1e + // Bit mask of LP_PERI_TIMEOUT_INT_CLEAR field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR_Msk = 0x40000000 + // Bit LP_PERI_TIMEOUT_INT_CLEAR. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR = 0x40000000 + // Position of LP_PERI_TIMEOUT_PROTECT_EN field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN_Pos = 0x1f + // Bit mask of LP_PERI_TIMEOUT_PROTECT_EN field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN_Msk = 0x80000000 + // Bit LP_PERI_TIMEOUT_PROTECT_EN. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN = 0x80000000 + + // BUS_TIMEOUT_ADDR: need_des + // Position of LP_PERI_TIMEOUT_ADDR field. + LPPERI_BUS_TIMEOUT_ADDR_LP_PERI_TIMEOUT_ADDR_Pos = 0x0 + // Bit mask of LP_PERI_TIMEOUT_ADDR field. + LPPERI_BUS_TIMEOUT_ADDR_LP_PERI_TIMEOUT_ADDR_Msk = 0xffffffff + + // BUS_TIMEOUT_UID: need_des + // Position of LP_PERI_TIMEOUT_UID field. + LPPERI_BUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID_Pos = 0x0 + // Bit mask of LP_PERI_TIMEOUT_UID field. + LPPERI_BUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID_Msk = 0x7f + + // MEM_CTRL: need_des + // Position of UART_WAKEUP_FLAG_CLR field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_CLR_Pos = 0x0 + // Bit mask of UART_WAKEUP_FLAG_CLR field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_CLR_Msk = 0x1 + // Bit UART_WAKEUP_FLAG_CLR. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_CLR = 0x1 + // Position of UART_WAKEUP_FLAG field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_Pos = 0x1 + // Bit mask of UART_WAKEUP_FLAG field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_Msk = 0x2 + // Bit UART_WAKEUP_FLAG. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG = 0x2 + // Position of UART_WAKEUP_EN field. + LPPERI_MEM_CTRL_UART_WAKEUP_EN_Pos = 0x1d + // Bit mask of UART_WAKEUP_EN field. + LPPERI_MEM_CTRL_UART_WAKEUP_EN_Msk = 0x20000000 + // Bit UART_WAKEUP_EN. + LPPERI_MEM_CTRL_UART_WAKEUP_EN = 0x20000000 + // Position of UART_MEM_FORCE_PD field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PD_Pos = 0x1e + // Bit mask of UART_MEM_FORCE_PD field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PD_Msk = 0x40000000 + // Bit UART_MEM_FORCE_PD. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PD = 0x40000000 + // Position of UART_MEM_FORCE_PU field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PU_Pos = 0x1f + // Bit mask of UART_MEM_FORCE_PU field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PU_Msk = 0x80000000 + // Bit UART_MEM_FORCE_PU. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PU = 0x80000000 + + // INTERRUPT_SOURCE: need_des + // Position of LP_INTERRUPT_SOURCE field. + LPPERI_INTERRUPT_SOURCE_LP_INTERRUPT_SOURCE_Pos = 0x0 + // Bit mask of LP_INTERRUPT_SOURCE field. + LPPERI_INTERRUPT_SOURCE_LP_INTERRUPT_SOURCE_Msk = 0x3f + + // DATE: need_des + // Position of LPPERI_DATE field. + LPPERI_DATE_LPPERI_DATE_Pos = 0x0 + // Bit mask of LPPERI_DATE field. + LPPERI_DATE_LPPERI_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LPPERI_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LPPERI_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LPPERI_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_ANA: LP_ANA Peripheral +const ( + // BOD_MODE0_CNTL: need_des + // Position of BOD_MODE0_CLOSE_FLASH_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA_Pos = 0x6 + // Bit mask of BOD_MODE0_CLOSE_FLASH_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA_Msk = 0x40 + // Bit BOD_MODE0_CLOSE_FLASH_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA = 0x40 + // Position of BOD_MODE0_PD_RF_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA_Pos = 0x7 + // Bit mask of BOD_MODE0_PD_RF_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA_Msk = 0x80 + // Bit BOD_MODE0_PD_RF_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA = 0x80 + // Position of BOD_MODE0_INTR_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT_Pos = 0x8 + // Bit mask of BOD_MODE0_INTR_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT_Msk = 0x3ff00 + // Position of BOD_MODE0_RESET_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT_Pos = 0x12 + // Bit mask of BOD_MODE0_RESET_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT_Msk = 0xffc0000 + // Position of BOD_MODE0_CNT_CLR field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CNT_CLR_Pos = 0x1c + // Bit mask of BOD_MODE0_CNT_CLR field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CNT_CLR_Msk = 0x10000000 + // Bit BOD_MODE0_CNT_CLR. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CNT_CLR = 0x10000000 + // Position of BOD_MODE0_INTR_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_ENA_Pos = 0x1d + // Bit mask of BOD_MODE0_INTR_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_ENA_Msk = 0x20000000 + // Bit BOD_MODE0_INTR_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_ENA = 0x20000000 + // Position of BOD_MODE0_RESET_SEL field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_SEL_Pos = 0x1e + // Bit mask of BOD_MODE0_RESET_SEL field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_SEL_Msk = 0x40000000 + // Bit BOD_MODE0_RESET_SEL. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_SEL = 0x40000000 + // Position of BOD_MODE0_RESET_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_ENA_Pos = 0x1f + // Bit mask of BOD_MODE0_RESET_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_ENA_Msk = 0x80000000 + // Bit BOD_MODE0_RESET_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_ENA = 0x80000000 + + // BOD_MODE1_CNTL: need_des + // Position of BOD_MODE1_RESET_ENA field. + LP_ANA_BOD_MODE1_CNTL_BOD_MODE1_RESET_ENA_Pos = 0x1f + // Bit mask of BOD_MODE1_RESET_ENA field. + LP_ANA_BOD_MODE1_CNTL_BOD_MODE1_RESET_ENA_Msk = 0x80000000 + // Bit BOD_MODE1_RESET_ENA. + LP_ANA_BOD_MODE1_CNTL_BOD_MODE1_RESET_ENA = 0x80000000 + + // CK_GLITCH_CNTL: need_des + // Position of CK_GLITCH_RESET_ENA field. + LP_ANA_CK_GLITCH_CNTL_CK_GLITCH_RESET_ENA_Pos = 0x1f + // Bit mask of CK_GLITCH_RESET_ENA field. + LP_ANA_CK_GLITCH_CNTL_CK_GLITCH_RESET_ENA_Msk = 0x80000000 + // Bit CK_GLITCH_RESET_ENA. + LP_ANA_CK_GLITCH_CNTL_CK_GLITCH_RESET_ENA = 0x80000000 + + // FIB_ENABLE: need_des + // Position of ANA_FIB_ENA field. + LP_ANA_FIB_ENABLE_ANA_FIB_ENA_Pos = 0x0 + // Bit mask of ANA_FIB_ENA field. + LP_ANA_FIB_ENABLE_ANA_FIB_ENA_Msk = 0xffffffff + + // INT_RAW: need_des + // Position of BOD_MODE0_INT_RAW field. + LP_ANA_INT_RAW_BOD_MODE0_INT_RAW_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_RAW field. + LP_ANA_INT_RAW_BOD_MODE0_INT_RAW_Msk = 0x80000000 + // Bit BOD_MODE0_INT_RAW. + LP_ANA_INT_RAW_BOD_MODE0_INT_RAW = 0x80000000 + + // INT_ST: need_des + // Position of BOD_MODE0_INT_ST field. + LP_ANA_INT_ST_BOD_MODE0_INT_ST_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_ST field. + LP_ANA_INT_ST_BOD_MODE0_INT_ST_Msk = 0x80000000 + // Bit BOD_MODE0_INT_ST. + LP_ANA_INT_ST_BOD_MODE0_INT_ST = 0x80000000 + + // INT_ENA: need_des + // Position of BOD_MODE0_INT_ENA field. + LP_ANA_INT_ENA_BOD_MODE0_INT_ENA_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_ENA field. + LP_ANA_INT_ENA_BOD_MODE0_INT_ENA_Msk = 0x80000000 + // Bit BOD_MODE0_INT_ENA. + LP_ANA_INT_ENA_BOD_MODE0_INT_ENA = 0x80000000 + + // INT_CLR: need_des + // Position of BOD_MODE0_INT_CLR field. + LP_ANA_INT_CLR_BOD_MODE0_INT_CLR_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_CLR field. + LP_ANA_INT_CLR_BOD_MODE0_INT_CLR_Msk = 0x80000000 + // Bit BOD_MODE0_INT_CLR. + LP_ANA_INT_CLR_BOD_MODE0_INT_CLR = 0x80000000 + + // LP_INT_RAW: need_des + // Position of BOD_MODE0_LP_INT_RAW field. + LP_ANA_LP_INT_RAW_BOD_MODE0_LP_INT_RAW_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_RAW field. + LP_ANA_LP_INT_RAW_BOD_MODE0_LP_INT_RAW_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_RAW. + LP_ANA_LP_INT_RAW_BOD_MODE0_LP_INT_RAW = 0x80000000 + + // LP_INT_ST: need_des + // Position of BOD_MODE0_LP_INT_ST field. + LP_ANA_LP_INT_ST_BOD_MODE0_LP_INT_ST_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_ST field. + LP_ANA_LP_INT_ST_BOD_MODE0_LP_INT_ST_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_ST. + LP_ANA_LP_INT_ST_BOD_MODE0_LP_INT_ST = 0x80000000 + + // LP_INT_ENA: need_des + // Position of BOD_MODE0_LP_INT_ENA field. + LP_ANA_LP_INT_ENA_BOD_MODE0_LP_INT_ENA_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_ENA field. + LP_ANA_LP_INT_ENA_BOD_MODE0_LP_INT_ENA_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_ENA. + LP_ANA_LP_INT_ENA_BOD_MODE0_LP_INT_ENA = 0x80000000 + + // LP_INT_CLR: need_des + // Position of BOD_MODE0_LP_INT_CLR field. + LP_ANA_LP_INT_CLR_BOD_MODE0_LP_INT_CLR_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_CLR field. + LP_ANA_LP_INT_CLR_BOD_MODE0_LP_INT_CLR_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_CLR. + LP_ANA_LP_INT_CLR_BOD_MODE0_LP_INT_CLR = 0x80000000 + + // DATE: need_des + // Position of LP_ANA_DATE field. + LP_ANA_DATE_LP_ANA_DATE_Pos = 0x0 + // Bit mask of LP_ANA_DATE field. + LP_ANA_DATE_LP_ANA_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_ANA_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_ANA_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_ANA_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_AON: LP_AON Peripheral +const ( + // STORE0: need_des + // Position of LP_AON_STORE0 field. + LP_AON_STORE0_LP_AON_STORE0_Pos = 0x0 + // Bit mask of LP_AON_STORE0 field. + LP_AON_STORE0_LP_AON_STORE0_Msk = 0xffffffff + + // STORE1: need_des + // Position of LP_AON_STORE1 field. + LP_AON_STORE1_LP_AON_STORE1_Pos = 0x0 + // Bit mask of LP_AON_STORE1 field. + LP_AON_STORE1_LP_AON_STORE1_Msk = 0xffffffff + + // STORE2: need_des + // Position of LP_AON_STORE2 field. + LP_AON_STORE2_LP_AON_STORE2_Pos = 0x0 + // Bit mask of LP_AON_STORE2 field. + LP_AON_STORE2_LP_AON_STORE2_Msk = 0xffffffff + + // STORE3: need_des + // Position of LP_AON_STORE3 field. + LP_AON_STORE3_LP_AON_STORE3_Pos = 0x0 + // Bit mask of LP_AON_STORE3 field. + LP_AON_STORE3_LP_AON_STORE3_Msk = 0xffffffff + + // STORE4: need_des + // Position of LP_AON_STORE4 field. + LP_AON_STORE4_LP_AON_STORE4_Pos = 0x0 + // Bit mask of LP_AON_STORE4 field. + LP_AON_STORE4_LP_AON_STORE4_Msk = 0xffffffff + + // STORE5: need_des + // Position of LP_AON_STORE5 field. + LP_AON_STORE5_LP_AON_STORE5_Pos = 0x0 + // Bit mask of LP_AON_STORE5 field. + LP_AON_STORE5_LP_AON_STORE5_Msk = 0xffffffff + + // STORE6: need_des + // Position of LP_AON_STORE6 field. + LP_AON_STORE6_LP_AON_STORE6_Pos = 0x0 + // Bit mask of LP_AON_STORE6 field. + LP_AON_STORE6_LP_AON_STORE6_Msk = 0xffffffff + + // STORE7: need_des + // Position of LP_AON_STORE7 field. + LP_AON_STORE7_LP_AON_STORE7_Pos = 0x0 + // Bit mask of LP_AON_STORE7 field. + LP_AON_STORE7_LP_AON_STORE7_Msk = 0xffffffff + + // STORE8: need_des + // Position of LP_AON_STORE8 field. + LP_AON_STORE8_LP_AON_STORE8_Pos = 0x0 + // Bit mask of LP_AON_STORE8 field. + LP_AON_STORE8_LP_AON_STORE8_Msk = 0xffffffff + + // STORE9: need_des + // Position of LP_AON_STORE9 field. + LP_AON_STORE9_LP_AON_STORE9_Pos = 0x0 + // Bit mask of LP_AON_STORE9 field. + LP_AON_STORE9_LP_AON_STORE9_Msk = 0xffffffff + + // GPIO_MUX: need_des + // Position of SEL field. + LP_AON_GPIO_MUX_SEL_Pos = 0x0 + // Bit mask of SEL field. + LP_AON_GPIO_MUX_SEL_Msk = 0xff + + // GPIO_HOLD0: need_des + // Position of GPIO_HOLD0 field. + LP_AON_GPIO_HOLD0_GPIO_HOLD0_Pos = 0x0 + // Bit mask of GPIO_HOLD0 field. + LP_AON_GPIO_HOLD0_GPIO_HOLD0_Msk = 0xffffffff + + // GPIO_HOLD1: need_des + // Position of GPIO_HOLD1 field. + LP_AON_GPIO_HOLD1_GPIO_HOLD1_Pos = 0x0 + // Bit mask of GPIO_HOLD1 field. + LP_AON_GPIO_HOLD1_GPIO_HOLD1_Msk = 0xffffffff + + // SYS_CFG: need_des + // Position of FORCE_DOWNLOAD_BOOT field. + LP_AON_SYS_CFG_FORCE_DOWNLOAD_BOOT_Pos = 0x1e + // Bit mask of FORCE_DOWNLOAD_BOOT field. + LP_AON_SYS_CFG_FORCE_DOWNLOAD_BOOT_Msk = 0x40000000 + // Bit FORCE_DOWNLOAD_BOOT. + LP_AON_SYS_CFG_FORCE_DOWNLOAD_BOOT = 0x40000000 + // Position of HPSYS_SW_RESET field. + LP_AON_SYS_CFG_HPSYS_SW_RESET_Pos = 0x1f + // Bit mask of HPSYS_SW_RESET field. + LP_AON_SYS_CFG_HPSYS_SW_RESET_Msk = 0x80000000 + // Bit HPSYS_SW_RESET. + LP_AON_SYS_CFG_HPSYS_SW_RESET = 0x80000000 + + // CPUCORE0_CFG: need_des + // Position of CPU_CORE0_SW_STALL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_STALL_Pos = 0x0 + // Bit mask of CPU_CORE0_SW_STALL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_STALL_Msk = 0xff + // Position of CPU_CORE0_SW_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_RESET_Pos = 0x1c + // Bit mask of CPU_CORE0_SW_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_RESET_Msk = 0x10000000 + // Bit CPU_CORE0_SW_RESET. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_RESET = 0x10000000 + // Position of CPU_CORE0_OCD_HALT_ON_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET_Pos = 0x1d + // Bit mask of CPU_CORE0_OCD_HALT_ON_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET_Msk = 0x20000000 + // Bit CPU_CORE0_OCD_HALT_ON_RESET. + LP_AON_CPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET = 0x20000000 + // Position of CPU_CORE0_STAT_VECTOR_SEL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL_Pos = 0x1e + // Bit mask of CPU_CORE0_STAT_VECTOR_SEL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL_Msk = 0x40000000 + // Bit CPU_CORE0_STAT_VECTOR_SEL. + LP_AON_CPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL = 0x40000000 + // Position of CPU_CORE0_DRESET_MASK field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_DRESET_MASK_Pos = 0x1f + // Bit mask of CPU_CORE0_DRESET_MASK field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_DRESET_MASK_Msk = 0x80000000 + // Bit CPU_CORE0_DRESET_MASK. + LP_AON_CPUCORE0_CFG_CPU_CORE0_DRESET_MASK = 0x80000000 + + // IO_MUX: need_des + // Position of RESET_DISABLE field. + LP_AON_IO_MUX_RESET_DISABLE_Pos = 0x1f + // Bit mask of RESET_DISABLE field. + LP_AON_IO_MUX_RESET_DISABLE_Msk = 0x80000000 + // Bit RESET_DISABLE. + LP_AON_IO_MUX_RESET_DISABLE = 0x80000000 + + // EXT_WAKEUP_CNTL: need_des + // Position of EXT_WAKEUP_STATUS field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_Pos = 0x0 + // Bit mask of EXT_WAKEUP_STATUS field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_Msk = 0xff + // Position of EXT_WAKEUP_STATUS_CLR field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR_Pos = 0xe + // Bit mask of EXT_WAKEUP_STATUS_CLR field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR_Msk = 0x4000 + // Bit EXT_WAKEUP_STATUS_CLR. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR = 0x4000 + // Position of EXT_WAKEUP_SEL field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_SEL_Pos = 0xf + // Bit mask of EXT_WAKEUP_SEL field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_SEL_Msk = 0x7f8000 + // Position of EXT_WAKEUP_LV field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_LV_Pos = 0x17 + // Bit mask of EXT_WAKEUP_LV field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_LV_Msk = 0x7f800000 + // Position of EXT_WAKEUP_FILTER field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER_Pos = 0x1f + // Bit mask of EXT_WAKEUP_FILTER field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER_Msk = 0x80000000 + // Bit EXT_WAKEUP_FILTER. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER = 0x80000000 + + // USB: need_des + // Position of RESET_DISABLE field. + LP_AON_USB_RESET_DISABLE_Pos = 0x1f + // Bit mask of RESET_DISABLE field. + LP_AON_USB_RESET_DISABLE_Msk = 0x80000000 + // Bit RESET_DISABLE. + LP_AON_USB_RESET_DISABLE = 0x80000000 + + // LPBUS: need_des + // Position of FAST_MEM_WPULSE field. + LP_AON_LPBUS_FAST_MEM_WPULSE_Pos = 0x10 + // Bit mask of FAST_MEM_WPULSE field. + LP_AON_LPBUS_FAST_MEM_WPULSE_Msk = 0x70000 + // Position of FAST_MEM_WA field. + LP_AON_LPBUS_FAST_MEM_WA_Pos = 0x13 + // Bit mask of FAST_MEM_WA field. + LP_AON_LPBUS_FAST_MEM_WA_Msk = 0x380000 + // Position of FAST_MEM_RA field. + LP_AON_LPBUS_FAST_MEM_RA_Pos = 0x16 + // Bit mask of FAST_MEM_RA field. + LP_AON_LPBUS_FAST_MEM_RA_Msk = 0xc00000 + // Position of FAST_MEM_MUX_FSM_IDLE field. + LP_AON_LPBUS_FAST_MEM_MUX_FSM_IDLE_Pos = 0x1c + // Bit mask of FAST_MEM_MUX_FSM_IDLE field. + LP_AON_LPBUS_FAST_MEM_MUX_FSM_IDLE_Msk = 0x10000000 + // Bit FAST_MEM_MUX_FSM_IDLE. + LP_AON_LPBUS_FAST_MEM_MUX_FSM_IDLE = 0x10000000 + // Position of FAST_MEM_MUX_SEL_STATUS field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_STATUS_Pos = 0x1d + // Bit mask of FAST_MEM_MUX_SEL_STATUS field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_STATUS_Msk = 0x20000000 + // Bit FAST_MEM_MUX_SEL_STATUS. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_STATUS = 0x20000000 + // Position of FAST_MEM_MUX_SEL_UPDATE field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_UPDATE_Pos = 0x1e + // Bit mask of FAST_MEM_MUX_SEL_UPDATE field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_UPDATE_Msk = 0x40000000 + // Bit FAST_MEM_MUX_SEL_UPDATE. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_UPDATE = 0x40000000 + // Position of FAST_MEM_MUX_SEL field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_Pos = 0x1f + // Bit mask of FAST_MEM_MUX_SEL field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_Msk = 0x80000000 + // Bit FAST_MEM_MUX_SEL. + LP_AON_LPBUS_FAST_MEM_MUX_SEL = 0x80000000 + + // SDIO_ACTIVE: need_des + // Position of SDIO_ACT_DNUM field. + LP_AON_SDIO_ACTIVE_SDIO_ACT_DNUM_Pos = 0x16 + // Bit mask of SDIO_ACT_DNUM field. + LP_AON_SDIO_ACTIVE_SDIO_ACT_DNUM_Msk = 0xffc00000 + + // LPCORE: need_des + // Position of ETM_WAKEUP_FLAG_CLR field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_Pos = 0x0 + // Bit mask of ETM_WAKEUP_FLAG_CLR field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_Msk = 0x1 + // Bit ETM_WAKEUP_FLAG_CLR. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR = 0x1 + // Position of ETM_WAKEUP_FLAG field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_Pos = 0x1 + // Bit mask of ETM_WAKEUP_FLAG field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_Msk = 0x2 + // Bit ETM_WAKEUP_FLAG. + LP_AON_LPCORE_ETM_WAKEUP_FLAG = 0x2 + // Position of DISABLE field. + LP_AON_LPCORE_DISABLE_Pos = 0x1f + // Bit mask of DISABLE field. + LP_AON_LPCORE_DISABLE_Msk = 0x80000000 + // Bit DISABLE. + LP_AON_LPCORE_DISABLE = 0x80000000 + + // SAR_CCT: need_des + // Position of SAR2_PWDET_CCT field. + LP_AON_SAR_CCT_SAR2_PWDET_CCT_Pos = 0x1d + // Bit mask of SAR2_PWDET_CCT field. + LP_AON_SAR_CCT_SAR2_PWDET_CCT_Msk = 0xe0000000 + + // DATE: need_des + // Position of DATE field. + LP_AON_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_AON_DATE_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_AON_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_AON_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_AON_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_APM: Low-power Access Permission Management Controller +const ( + // REGION_FILTER_EN: Region filter enable register + // Position of REGION_FILTER_EN field. + LP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Pos = 0x0 + // Bit mask of REGION_FILTER_EN field. + LP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Msk = 0xf + + // REGION0_ADDR_START: Region address register + // Position of REGION0_ADDR_START field. + LP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Pos = 0x0 + // Bit mask of REGION0_ADDR_START field. + LP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Msk = 0xffffffff + + // REGION0_ADDR_END: Region address register + // Position of REGION0_ADDR_END field. + LP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Pos = 0x0 + // Bit mask of REGION0_ADDR_END field. + LP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Msk = 0xffffffff + + // REGION0_PMS_ATTR: Region access authority attribute register + // Position of REGION0_R0_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION0_R0_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Msk = 0x1 + // Bit REGION0_R0_PMS_X. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X = 0x1 + // Position of REGION0_R0_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION0_R0_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Msk = 0x2 + // Bit REGION0_R0_PMS_W. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W = 0x2 + // Position of REGION0_R0_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION0_R0_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Msk = 0x4 + // Bit REGION0_R0_PMS_R. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R = 0x4 + // Position of REGION0_R1_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION0_R1_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Msk = 0x10 + // Bit REGION0_R1_PMS_X. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X = 0x10 + // Position of REGION0_R1_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION0_R1_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Msk = 0x20 + // Bit REGION0_R1_PMS_W. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W = 0x20 + // Position of REGION0_R1_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION0_R1_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Msk = 0x40 + // Bit REGION0_R1_PMS_R. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R = 0x40 + // Position of REGION0_R2_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION0_R2_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Msk = 0x100 + // Bit REGION0_R2_PMS_X. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X = 0x100 + // Position of REGION0_R2_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION0_R2_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Msk = 0x200 + // Bit REGION0_R2_PMS_W. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W = 0x200 + // Position of REGION0_R2_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Pos = 0xa + // Bit mask of REGION0_R2_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Msk = 0x400 + // Bit REGION0_R2_PMS_R. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R = 0x400 + + // REGION1_ADDR_START: Region address register + // Position of REGION1_ADDR_START field. + LP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Pos = 0x0 + // Bit mask of REGION1_ADDR_START field. + LP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Msk = 0xffffffff + + // REGION1_ADDR_END: Region address register + // Position of REGION1_ADDR_END field. + LP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Pos = 0x0 + // Bit mask of REGION1_ADDR_END field. + LP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Msk = 0xffffffff + + // REGION1_PMS_ATTR: Region access authority attribute register + // Position of REGION1_R0_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION1_R0_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Msk = 0x1 + // Bit REGION1_R0_PMS_X. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X = 0x1 + // Position of REGION1_R0_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION1_R0_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Msk = 0x2 + // Bit REGION1_R0_PMS_W. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W = 0x2 + // Position of REGION1_R0_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION1_R0_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Msk = 0x4 + // Bit REGION1_R0_PMS_R. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R = 0x4 + // Position of REGION1_R1_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION1_R1_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Msk = 0x10 + // Bit REGION1_R1_PMS_X. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X = 0x10 + // Position of REGION1_R1_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION1_R1_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Msk = 0x20 + // Bit REGION1_R1_PMS_W. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W = 0x20 + // Position of REGION1_R1_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION1_R1_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Msk = 0x40 + // Bit REGION1_R1_PMS_R. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R = 0x40 + // Position of REGION1_R2_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION1_R2_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Msk = 0x100 + // Bit REGION1_R2_PMS_X. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X = 0x100 + // Position of REGION1_R2_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION1_R2_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Msk = 0x200 + // Bit REGION1_R2_PMS_W. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W = 0x200 + // Position of REGION1_R2_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Pos = 0xa + // Bit mask of REGION1_R2_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Msk = 0x400 + // Bit REGION1_R2_PMS_R. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R = 0x400 + + // REGION2_ADDR_START: Region address register + // Position of REGION2_ADDR_START field. + LP_APM_REGION2_ADDR_START_REGION2_ADDR_START_Pos = 0x0 + // Bit mask of REGION2_ADDR_START field. + LP_APM_REGION2_ADDR_START_REGION2_ADDR_START_Msk = 0xffffffff + + // REGION2_ADDR_END: Region address register + // Position of REGION2_ADDR_END field. + LP_APM_REGION2_ADDR_END_REGION2_ADDR_END_Pos = 0x0 + // Bit mask of REGION2_ADDR_END field. + LP_APM_REGION2_ADDR_END_REGION2_ADDR_END_Msk = 0xffffffff + + // REGION2_PMS_ATTR: Region access authority attribute register + // Position of REGION2_R0_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION2_R0_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Msk = 0x1 + // Bit REGION2_R0_PMS_X. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X = 0x1 + // Position of REGION2_R0_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION2_R0_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Msk = 0x2 + // Bit REGION2_R0_PMS_W. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W = 0x2 + // Position of REGION2_R0_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION2_R0_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Msk = 0x4 + // Bit REGION2_R0_PMS_R. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R = 0x4 + // Position of REGION2_R1_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION2_R1_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Msk = 0x10 + // Bit REGION2_R1_PMS_X. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X = 0x10 + // Position of REGION2_R1_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION2_R1_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Msk = 0x20 + // Bit REGION2_R1_PMS_W. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W = 0x20 + // Position of REGION2_R1_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION2_R1_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Msk = 0x40 + // Bit REGION2_R1_PMS_R. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R = 0x40 + // Position of REGION2_R2_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION2_R2_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Msk = 0x100 + // Bit REGION2_R2_PMS_X. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X = 0x100 + // Position of REGION2_R2_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION2_R2_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Msk = 0x200 + // Bit REGION2_R2_PMS_W. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W = 0x200 + // Position of REGION2_R2_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Pos = 0xa + // Bit mask of REGION2_R2_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Msk = 0x400 + // Bit REGION2_R2_PMS_R. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R = 0x400 + + // REGION3_ADDR_START: Region address register + // Position of REGION3_ADDR_START field. + LP_APM_REGION3_ADDR_START_REGION3_ADDR_START_Pos = 0x0 + // Bit mask of REGION3_ADDR_START field. + LP_APM_REGION3_ADDR_START_REGION3_ADDR_START_Msk = 0xffffffff + + // REGION3_ADDR_END: Region address register + // Position of REGION3_ADDR_END field. + LP_APM_REGION3_ADDR_END_REGION3_ADDR_END_Pos = 0x0 + // Bit mask of REGION3_ADDR_END field. + LP_APM_REGION3_ADDR_END_REGION3_ADDR_END_Msk = 0xffffffff + + // REGION3_PMS_ATTR: Region access authority attribute register + // Position of REGION3_R0_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION3_R0_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Msk = 0x1 + // Bit REGION3_R0_PMS_X. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X = 0x1 + // Position of REGION3_R0_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION3_R0_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Msk = 0x2 + // Bit REGION3_R0_PMS_W. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W = 0x2 + // Position of REGION3_R0_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION3_R0_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Msk = 0x4 + // Bit REGION3_R0_PMS_R. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R = 0x4 + // Position of REGION3_R1_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION3_R1_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Msk = 0x10 + // Bit REGION3_R1_PMS_X. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X = 0x10 + // Position of REGION3_R1_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION3_R1_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Msk = 0x20 + // Bit REGION3_R1_PMS_W. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W = 0x20 + // Position of REGION3_R1_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION3_R1_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Msk = 0x40 + // Bit REGION3_R1_PMS_R. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R = 0x40 + // Position of REGION3_R2_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION3_R2_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Msk = 0x100 + // Bit REGION3_R2_PMS_X. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X = 0x100 + // Position of REGION3_R2_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION3_R2_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Msk = 0x200 + // Bit REGION3_R2_PMS_W. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W = 0x200 + // Position of REGION3_R2_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Pos = 0xa + // Bit mask of REGION3_R2_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Msk = 0x400 + // Bit REGION3_R2_PMS_R. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R = 0x400 + + // FUNC_CTRL: PMS function control register + // Position of M0_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Pos = 0x0 + // Bit mask of M0_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Msk = 0x1 + // Bit M0_PMS_FUNC_EN. + LP_APM_FUNC_CTRL_M0_PMS_FUNC_EN = 0x1 + // Position of M1_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M1_PMS_FUNC_EN_Pos = 0x1 + // Bit mask of M1_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M1_PMS_FUNC_EN_Msk = 0x2 + // Bit M1_PMS_FUNC_EN. + LP_APM_FUNC_CTRL_M1_PMS_FUNC_EN = 0x2 + + // M0_STATUS: M0 status register + // Position of M0_EXCEPTION_STATUS field. + LP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M0_EXCEPTION_STATUS field. + LP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Msk = 0x3 + + // M0_STATUS_CLR: M0 status clear register + // Position of M0_REGION_STATUS_CLR field. + LP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M0_REGION_STATUS_CLR field. + LP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Msk = 0x1 + // Bit M0_REGION_STATUS_CLR. + LP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR = 0x1 + + // M0_EXCEPTION_INFO0: M0 exception_info0 register + // Position of M0_EXCEPTION_REGION field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M0_EXCEPTION_REGION field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Msk = 0xf + // Position of M0_EXCEPTION_MODE field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M0_EXCEPTION_MODE field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Msk = 0x30000 + // Position of M0_EXCEPTION_ID field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M0_EXCEPTION_ID field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Msk = 0x7c0000 + + // M0_EXCEPTION_INFO1: M0 exception_info1 register + // Position of M0_EXCEPTION_ADDR field. + LP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M0_EXCEPTION_ADDR field. + LP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Msk = 0xffffffff + + // M1_STATUS: M1 status register + // Position of M1_EXCEPTION_STATUS field. + LP_APM_M1_STATUS_M1_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M1_EXCEPTION_STATUS field. + LP_APM_M1_STATUS_M1_EXCEPTION_STATUS_Msk = 0x3 + + // M1_STATUS_CLR: M1 status clear register + // Position of M1_REGION_STATUS_CLR field. + LP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M1_REGION_STATUS_CLR field. + LP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR_Msk = 0x1 + // Bit M1_REGION_STATUS_CLR. + LP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR = 0x1 + + // M1_EXCEPTION_INFO0: M1 exception_info0 register + // Position of M1_EXCEPTION_REGION field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M1_EXCEPTION_REGION field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_REGION_Msk = 0xf + // Position of M1_EXCEPTION_MODE field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M1_EXCEPTION_MODE field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_MODE_Msk = 0x30000 + // Position of M1_EXCEPTION_ID field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M1_EXCEPTION_ID field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_ID_Msk = 0x7c0000 + + // M1_EXCEPTION_INFO1: M1 exception_info1 register + // Position of M1_EXCEPTION_ADDR field. + LP_APM_M1_EXCEPTION_INFO1_M1_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M1_EXCEPTION_ADDR field. + LP_APM_M1_EXCEPTION_INFO1_M1_EXCEPTION_ADDR_Msk = 0xffffffff + + // INT_EN: APM interrupt enable register + // Position of M0_APM_INT_EN field. + LP_APM_INT_EN_M0_APM_INT_EN_Pos = 0x0 + // Bit mask of M0_APM_INT_EN field. + LP_APM_INT_EN_M0_APM_INT_EN_Msk = 0x1 + // Bit M0_APM_INT_EN. + LP_APM_INT_EN_M0_APM_INT_EN = 0x1 + // Position of M1_APM_INT_EN field. + LP_APM_INT_EN_M1_APM_INT_EN_Pos = 0x1 + // Bit mask of M1_APM_INT_EN field. + LP_APM_INT_EN_M1_APM_INT_EN_Msk = 0x2 + // Bit M1_APM_INT_EN. + LP_APM_INT_EN_M1_APM_INT_EN = 0x2 + + // CLOCK_GATE: clock gating register + // Position of CLK_EN field. + LP_APM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + LP_APM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + LP_APM_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + LP_APM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_APM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for LP_APM0: LP_APM0 Peripheral +const ( + // REGION_FILTER_EN: Region filter enable register + // Position of REGION_FILTER_EN field. + LP_APM0_REGION_FILTER_EN_REGION_FILTER_EN_Pos = 0x0 + // Bit mask of REGION_FILTER_EN field. + LP_APM0_REGION_FILTER_EN_REGION_FILTER_EN_Msk = 0xf + + // REGION0_ADDR_START: Region address register + // Position of REGION0_ADDR_START field. + LP_APM0_REGION0_ADDR_START_REGION0_ADDR_START_Pos = 0x0 + // Bit mask of REGION0_ADDR_START field. + LP_APM0_REGION0_ADDR_START_REGION0_ADDR_START_Msk = 0xffffffff + + // REGION0_ADDR_END: Region address register + // Position of REGION0_ADDR_END field. + LP_APM0_REGION0_ADDR_END_REGION0_ADDR_END_Pos = 0x0 + // Bit mask of REGION0_ADDR_END field. + LP_APM0_REGION0_ADDR_END_REGION0_ADDR_END_Msk = 0xffffffff + + // REGION0_PMS_ATTR: Region access authority attribute register + // Position of REGION0_R0_PMS_X field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION0_R0_PMS_X field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Msk = 0x1 + // Bit REGION0_R0_PMS_X. + LP_APM0_REGION0_PMS_ATTR_REGION0_R0_PMS_X = 0x1 + // Position of REGION0_R0_PMS_W field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION0_R0_PMS_W field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Msk = 0x2 + // Bit REGION0_R0_PMS_W. + LP_APM0_REGION0_PMS_ATTR_REGION0_R0_PMS_W = 0x2 + // Position of REGION0_R0_PMS_R field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION0_R0_PMS_R field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Msk = 0x4 + // Bit REGION0_R0_PMS_R. + LP_APM0_REGION0_PMS_ATTR_REGION0_R0_PMS_R = 0x4 + // Position of REGION0_R1_PMS_X field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION0_R1_PMS_X field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Msk = 0x10 + // Bit REGION0_R1_PMS_X. + LP_APM0_REGION0_PMS_ATTR_REGION0_R1_PMS_X = 0x10 + // Position of REGION0_R1_PMS_W field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION0_R1_PMS_W field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Msk = 0x20 + // Bit REGION0_R1_PMS_W. + LP_APM0_REGION0_PMS_ATTR_REGION0_R1_PMS_W = 0x20 + // Position of REGION0_R1_PMS_R field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION0_R1_PMS_R field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Msk = 0x40 + // Bit REGION0_R1_PMS_R. + LP_APM0_REGION0_PMS_ATTR_REGION0_R1_PMS_R = 0x40 + // Position of REGION0_R2_PMS_X field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION0_R2_PMS_X field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Msk = 0x100 + // Bit REGION0_R2_PMS_X. + LP_APM0_REGION0_PMS_ATTR_REGION0_R2_PMS_X = 0x100 + // Position of REGION0_R2_PMS_W field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION0_R2_PMS_W field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Msk = 0x200 + // Bit REGION0_R2_PMS_W. + LP_APM0_REGION0_PMS_ATTR_REGION0_R2_PMS_W = 0x200 + // Position of REGION0_R2_PMS_R field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Pos = 0xa + // Bit mask of REGION0_R2_PMS_R field. + LP_APM0_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Msk = 0x400 + // Bit REGION0_R2_PMS_R. + LP_APM0_REGION0_PMS_ATTR_REGION0_R2_PMS_R = 0x400 + + // REGION1_ADDR_START: Region address register + // Position of REGION1_ADDR_START field. + LP_APM0_REGION1_ADDR_START_REGION1_ADDR_START_Pos = 0x0 + // Bit mask of REGION1_ADDR_START field. + LP_APM0_REGION1_ADDR_START_REGION1_ADDR_START_Msk = 0xffffffff + + // REGION1_ADDR_END: Region address register + // Position of REGION1_ADDR_END field. + LP_APM0_REGION1_ADDR_END_REGION1_ADDR_END_Pos = 0x0 + // Bit mask of REGION1_ADDR_END field. + LP_APM0_REGION1_ADDR_END_REGION1_ADDR_END_Msk = 0xffffffff + + // REGION1_PMS_ATTR: Region access authority attribute register + // Position of REGION1_R0_PMS_X field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION1_R0_PMS_X field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Msk = 0x1 + // Bit REGION1_R0_PMS_X. + LP_APM0_REGION1_PMS_ATTR_REGION1_R0_PMS_X = 0x1 + // Position of REGION1_R0_PMS_W field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION1_R0_PMS_W field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Msk = 0x2 + // Bit REGION1_R0_PMS_W. + LP_APM0_REGION1_PMS_ATTR_REGION1_R0_PMS_W = 0x2 + // Position of REGION1_R0_PMS_R field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION1_R0_PMS_R field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Msk = 0x4 + // Bit REGION1_R0_PMS_R. + LP_APM0_REGION1_PMS_ATTR_REGION1_R0_PMS_R = 0x4 + // Position of REGION1_R1_PMS_X field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION1_R1_PMS_X field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Msk = 0x10 + // Bit REGION1_R1_PMS_X. + LP_APM0_REGION1_PMS_ATTR_REGION1_R1_PMS_X = 0x10 + // Position of REGION1_R1_PMS_W field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION1_R1_PMS_W field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Msk = 0x20 + // Bit REGION1_R1_PMS_W. + LP_APM0_REGION1_PMS_ATTR_REGION1_R1_PMS_W = 0x20 + // Position of REGION1_R1_PMS_R field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION1_R1_PMS_R field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Msk = 0x40 + // Bit REGION1_R1_PMS_R. + LP_APM0_REGION1_PMS_ATTR_REGION1_R1_PMS_R = 0x40 + // Position of REGION1_R2_PMS_X field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION1_R2_PMS_X field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Msk = 0x100 + // Bit REGION1_R2_PMS_X. + LP_APM0_REGION1_PMS_ATTR_REGION1_R2_PMS_X = 0x100 + // Position of REGION1_R2_PMS_W field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION1_R2_PMS_W field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Msk = 0x200 + // Bit REGION1_R2_PMS_W. + LP_APM0_REGION1_PMS_ATTR_REGION1_R2_PMS_W = 0x200 + // Position of REGION1_R2_PMS_R field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Pos = 0xa + // Bit mask of REGION1_R2_PMS_R field. + LP_APM0_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Msk = 0x400 + // Bit REGION1_R2_PMS_R. + LP_APM0_REGION1_PMS_ATTR_REGION1_R2_PMS_R = 0x400 + + // REGION2_ADDR_START: Region address register + // Position of REGION2_ADDR_START field. + LP_APM0_REGION2_ADDR_START_REGION2_ADDR_START_Pos = 0x0 + // Bit mask of REGION2_ADDR_START field. + LP_APM0_REGION2_ADDR_START_REGION2_ADDR_START_Msk = 0xffffffff + + // REGION2_ADDR_END: Region address register + // Position of REGION2_ADDR_END field. + LP_APM0_REGION2_ADDR_END_REGION2_ADDR_END_Pos = 0x0 + // Bit mask of REGION2_ADDR_END field. + LP_APM0_REGION2_ADDR_END_REGION2_ADDR_END_Msk = 0xffffffff + + // REGION2_PMS_ATTR: Region access authority attribute register + // Position of REGION2_R0_PMS_X field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION2_R0_PMS_X field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Msk = 0x1 + // Bit REGION2_R0_PMS_X. + LP_APM0_REGION2_PMS_ATTR_REGION2_R0_PMS_X = 0x1 + // Position of REGION2_R0_PMS_W field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION2_R0_PMS_W field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Msk = 0x2 + // Bit REGION2_R0_PMS_W. + LP_APM0_REGION2_PMS_ATTR_REGION2_R0_PMS_W = 0x2 + // Position of REGION2_R0_PMS_R field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION2_R0_PMS_R field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Msk = 0x4 + // Bit REGION2_R0_PMS_R. + LP_APM0_REGION2_PMS_ATTR_REGION2_R0_PMS_R = 0x4 + // Position of REGION2_R1_PMS_X field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION2_R1_PMS_X field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Msk = 0x10 + // Bit REGION2_R1_PMS_X. + LP_APM0_REGION2_PMS_ATTR_REGION2_R1_PMS_X = 0x10 + // Position of REGION2_R1_PMS_W field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION2_R1_PMS_W field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Msk = 0x20 + // Bit REGION2_R1_PMS_W. + LP_APM0_REGION2_PMS_ATTR_REGION2_R1_PMS_W = 0x20 + // Position of REGION2_R1_PMS_R field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION2_R1_PMS_R field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Msk = 0x40 + // Bit REGION2_R1_PMS_R. + LP_APM0_REGION2_PMS_ATTR_REGION2_R1_PMS_R = 0x40 + // Position of REGION2_R2_PMS_X field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION2_R2_PMS_X field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Msk = 0x100 + // Bit REGION2_R2_PMS_X. + LP_APM0_REGION2_PMS_ATTR_REGION2_R2_PMS_X = 0x100 + // Position of REGION2_R2_PMS_W field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION2_R2_PMS_W field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Msk = 0x200 + // Bit REGION2_R2_PMS_W. + LP_APM0_REGION2_PMS_ATTR_REGION2_R2_PMS_W = 0x200 + // Position of REGION2_R2_PMS_R field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Pos = 0xa + // Bit mask of REGION2_R2_PMS_R field. + LP_APM0_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Msk = 0x400 + // Bit REGION2_R2_PMS_R. + LP_APM0_REGION2_PMS_ATTR_REGION2_R2_PMS_R = 0x400 + + // REGION3_ADDR_START: Region address register + // Position of REGION3_ADDR_START field. + LP_APM0_REGION3_ADDR_START_REGION3_ADDR_START_Pos = 0x0 + // Bit mask of REGION3_ADDR_START field. + LP_APM0_REGION3_ADDR_START_REGION3_ADDR_START_Msk = 0xffffffff + + // REGION3_ADDR_END: Region address register + // Position of REGION3_ADDR_END field. + LP_APM0_REGION3_ADDR_END_REGION3_ADDR_END_Pos = 0x0 + // Bit mask of REGION3_ADDR_END field. + LP_APM0_REGION3_ADDR_END_REGION3_ADDR_END_Msk = 0xffffffff + + // REGION3_PMS_ATTR: Region access authority attribute register + // Position of REGION3_R0_PMS_X field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION3_R0_PMS_X field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Msk = 0x1 + // Bit REGION3_R0_PMS_X. + LP_APM0_REGION3_PMS_ATTR_REGION3_R0_PMS_X = 0x1 + // Position of REGION3_R0_PMS_W field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION3_R0_PMS_W field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Msk = 0x2 + // Bit REGION3_R0_PMS_W. + LP_APM0_REGION3_PMS_ATTR_REGION3_R0_PMS_W = 0x2 + // Position of REGION3_R0_PMS_R field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION3_R0_PMS_R field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Msk = 0x4 + // Bit REGION3_R0_PMS_R. + LP_APM0_REGION3_PMS_ATTR_REGION3_R0_PMS_R = 0x4 + // Position of REGION3_R1_PMS_X field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION3_R1_PMS_X field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Msk = 0x10 + // Bit REGION3_R1_PMS_X. + LP_APM0_REGION3_PMS_ATTR_REGION3_R1_PMS_X = 0x10 + // Position of REGION3_R1_PMS_W field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION3_R1_PMS_W field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Msk = 0x20 + // Bit REGION3_R1_PMS_W. + LP_APM0_REGION3_PMS_ATTR_REGION3_R1_PMS_W = 0x20 + // Position of REGION3_R1_PMS_R field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION3_R1_PMS_R field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Msk = 0x40 + // Bit REGION3_R1_PMS_R. + LP_APM0_REGION3_PMS_ATTR_REGION3_R1_PMS_R = 0x40 + // Position of REGION3_R2_PMS_X field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION3_R2_PMS_X field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Msk = 0x100 + // Bit REGION3_R2_PMS_X. + LP_APM0_REGION3_PMS_ATTR_REGION3_R2_PMS_X = 0x100 + // Position of REGION3_R2_PMS_W field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION3_R2_PMS_W field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Msk = 0x200 + // Bit REGION3_R2_PMS_W. + LP_APM0_REGION3_PMS_ATTR_REGION3_R2_PMS_W = 0x200 + // Position of REGION3_R2_PMS_R field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Pos = 0xa + // Bit mask of REGION3_R2_PMS_R field. + LP_APM0_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Msk = 0x400 + // Bit REGION3_R2_PMS_R. + LP_APM0_REGION3_PMS_ATTR_REGION3_R2_PMS_R = 0x400 + + // FUNC_CTRL: PMS function control register + // Position of M0_PMS_FUNC_EN field. + LP_APM0_FUNC_CTRL_M0_PMS_FUNC_EN_Pos = 0x0 + // Bit mask of M0_PMS_FUNC_EN field. + LP_APM0_FUNC_CTRL_M0_PMS_FUNC_EN_Msk = 0x1 + // Bit M0_PMS_FUNC_EN. + LP_APM0_FUNC_CTRL_M0_PMS_FUNC_EN = 0x1 + + // M0_STATUS: M0 status register + // Position of M0_EXCEPTION_STATUS field. + LP_APM0_M0_STATUS_M0_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M0_EXCEPTION_STATUS field. + LP_APM0_M0_STATUS_M0_EXCEPTION_STATUS_Msk = 0x3 + + // M0_STATUS_CLR: M0 status clear register + // Position of M0_REGION_STATUS_CLR field. + LP_APM0_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M0_REGION_STATUS_CLR field. + LP_APM0_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Msk = 0x1 + // Bit M0_REGION_STATUS_CLR. + LP_APM0_M0_STATUS_CLR_M0_REGION_STATUS_CLR = 0x1 + + // M0_EXCEPTION_INFO0: M0 exception_info0 register + // Position of M0_EXCEPTION_REGION field. + LP_APM0_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M0_EXCEPTION_REGION field. + LP_APM0_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Msk = 0xf + // Position of M0_EXCEPTION_MODE field. + LP_APM0_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M0_EXCEPTION_MODE field. + LP_APM0_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Msk = 0x30000 + // Position of M0_EXCEPTION_ID field. + LP_APM0_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M0_EXCEPTION_ID field. + LP_APM0_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Msk = 0x7c0000 + + // M0_EXCEPTION_INFO1: M0 exception_info1 register + // Position of M0_EXCEPTION_ADDR field. + LP_APM0_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M0_EXCEPTION_ADDR field. + LP_APM0_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Msk = 0xffffffff + + // INT_EN: APM interrupt enable register + // Position of M0_APM_INT_EN field. + LP_APM0_INT_EN_M0_APM_INT_EN_Pos = 0x0 + // Bit mask of M0_APM_INT_EN field. + LP_APM0_INT_EN_M0_APM_INT_EN_Msk = 0x1 + // Bit M0_APM_INT_EN. + LP_APM0_INT_EN_M0_APM_INT_EN = 0x1 + + // CLOCK_GATE: clock gating register + // Position of CLK_EN field. + LP_APM0_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + LP_APM0_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + LP_APM0_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + LP_APM0_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_APM0_DATE_DATE_Msk = 0xfffffff +) + +// Constants for LP_CLKRST: LP_CLKRST Peripheral +const ( + // LP_CLK_CONF: need_des + // Position of SLOW_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_SLOW_CLK_SEL_Pos = 0x0 + // Bit mask of SLOW_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_SLOW_CLK_SEL_Msk = 0x3 + // Position of FAST_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_FAST_CLK_SEL_Pos = 0x2 + // Bit mask of FAST_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_FAST_CLK_SEL_Msk = 0x4 + // Bit FAST_CLK_SEL. + LP_CLKRST_LP_CLK_CONF_FAST_CLK_SEL = 0x4 + // Position of LP_PERI_DIV_NUM field. + LP_CLKRST_LP_CLK_CONF_LP_PERI_DIV_NUM_Pos = 0x3 + // Bit mask of LP_PERI_DIV_NUM field. + LP_CLKRST_LP_CLK_CONF_LP_PERI_DIV_NUM_Msk = 0x7f8 + + // LP_CLK_PO_EN: need_des + // Position of AON_SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_SLOW_OEN_Pos = 0x0 + // Bit mask of AON_SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_SLOW_OEN_Msk = 0x1 + // Bit AON_SLOW_OEN. + LP_CLKRST_LP_CLK_PO_EN_AON_SLOW_OEN = 0x1 + // Position of AON_FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_FAST_OEN_Pos = 0x1 + // Bit mask of AON_FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_FAST_OEN_Msk = 0x2 + // Bit AON_FAST_OEN. + LP_CLKRST_LP_CLK_PO_EN_AON_FAST_OEN = 0x2 + // Position of SOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SOSC_OEN_Pos = 0x2 + // Bit mask of SOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SOSC_OEN_Msk = 0x4 + // Bit SOSC_OEN. + LP_CLKRST_LP_CLK_PO_EN_SOSC_OEN = 0x4 + // Position of FOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FOSC_OEN_Pos = 0x3 + // Bit mask of FOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FOSC_OEN_Msk = 0x8 + // Bit FOSC_OEN. + LP_CLKRST_LP_CLK_PO_EN_FOSC_OEN = 0x8 + // Position of OSC32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_OSC32K_OEN_Pos = 0x4 + // Bit mask of OSC32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_OSC32K_OEN_Msk = 0x10 + // Bit OSC32K_OEN. + LP_CLKRST_LP_CLK_PO_EN_OSC32K_OEN = 0x10 + // Position of XTAL32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_XTAL32K_OEN_Pos = 0x5 + // Bit mask of XTAL32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_XTAL32K_OEN_Msk = 0x20 + // Bit XTAL32K_OEN. + LP_CLKRST_LP_CLK_PO_EN_XTAL32K_OEN = 0x20 + // Position of CORE_EFUSE_OEN field. + LP_CLKRST_LP_CLK_PO_EN_CORE_EFUSE_OEN_Pos = 0x6 + // Bit mask of CORE_EFUSE_OEN field. + LP_CLKRST_LP_CLK_PO_EN_CORE_EFUSE_OEN_Msk = 0x40 + // Bit CORE_EFUSE_OEN. + LP_CLKRST_LP_CLK_PO_EN_CORE_EFUSE_OEN = 0x40 + // Position of SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SLOW_OEN_Pos = 0x7 + // Bit mask of SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SLOW_OEN_Msk = 0x80 + // Bit SLOW_OEN. + LP_CLKRST_LP_CLK_PO_EN_SLOW_OEN = 0x80 + // Position of FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FAST_OEN_Pos = 0x8 + // Bit mask of FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FAST_OEN_Msk = 0x100 + // Bit FAST_OEN. + LP_CLKRST_LP_CLK_PO_EN_FAST_OEN = 0x100 + // Position of RNG_OEN field. + LP_CLKRST_LP_CLK_PO_EN_RNG_OEN_Pos = 0x9 + // Bit mask of RNG_OEN field. + LP_CLKRST_LP_CLK_PO_EN_RNG_OEN_Msk = 0x200 + // Bit RNG_OEN. + LP_CLKRST_LP_CLK_PO_EN_RNG_OEN = 0x200 + // Position of LPBUS_OEN field. + LP_CLKRST_LP_CLK_PO_EN_LPBUS_OEN_Pos = 0xa + // Bit mask of LPBUS_OEN field. + LP_CLKRST_LP_CLK_PO_EN_LPBUS_OEN_Msk = 0x400 + // Bit LPBUS_OEN. + LP_CLKRST_LP_CLK_PO_EN_LPBUS_OEN = 0x400 + + // LP_CLK_EN: need_des + // Position of FAST_ORI_GATE field. + LP_CLKRST_LP_CLK_EN_FAST_ORI_GATE_Pos = 0x1f + // Bit mask of FAST_ORI_GATE field. + LP_CLKRST_LP_CLK_EN_FAST_ORI_GATE_Msk = 0x80000000 + // Bit FAST_ORI_GATE. + LP_CLKRST_LP_CLK_EN_FAST_ORI_GATE = 0x80000000 + + // LP_RST_EN: need_des + // Position of AON_EFUSE_CORE_RESET_EN field. + LP_CLKRST_LP_RST_EN_AON_EFUSE_CORE_RESET_EN_Pos = 0x1c + // Bit mask of AON_EFUSE_CORE_RESET_EN field. + LP_CLKRST_LP_RST_EN_AON_EFUSE_CORE_RESET_EN_Msk = 0x10000000 + // Bit AON_EFUSE_CORE_RESET_EN. + LP_CLKRST_LP_RST_EN_AON_EFUSE_CORE_RESET_EN = 0x10000000 + // Position of LP_TIMER_RESET_EN field. + LP_CLKRST_LP_RST_EN_LP_TIMER_RESET_EN_Pos = 0x1d + // Bit mask of LP_TIMER_RESET_EN field. + LP_CLKRST_LP_RST_EN_LP_TIMER_RESET_EN_Msk = 0x20000000 + // Bit LP_TIMER_RESET_EN. + LP_CLKRST_LP_RST_EN_LP_TIMER_RESET_EN = 0x20000000 + // Position of WDT_RESET_EN field. + LP_CLKRST_LP_RST_EN_WDT_RESET_EN_Pos = 0x1e + // Bit mask of WDT_RESET_EN field. + LP_CLKRST_LP_RST_EN_WDT_RESET_EN_Msk = 0x40000000 + // Bit WDT_RESET_EN. + LP_CLKRST_LP_RST_EN_WDT_RESET_EN = 0x40000000 + // Position of ANA_PERI_RESET_EN field. + LP_CLKRST_LP_RST_EN_ANA_PERI_RESET_EN_Pos = 0x1f + // Bit mask of ANA_PERI_RESET_EN field. + LP_CLKRST_LP_RST_EN_ANA_PERI_RESET_EN_Msk = 0x80000000 + // Bit ANA_PERI_RESET_EN. + LP_CLKRST_LP_RST_EN_ANA_PERI_RESET_EN = 0x80000000 + + // RESET_CAUSE: need_des + // Position of RESET_CAUSE field. + LP_CLKRST_RESET_CAUSE_RESET_CAUSE_Pos = 0x0 + // Bit mask of RESET_CAUSE field. + LP_CLKRST_RESET_CAUSE_RESET_CAUSE_Msk = 0x1f + // Position of CORE0_RESET_FLAG field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_Pos = 0x5 + // Bit mask of CORE0_RESET_FLAG field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_Msk = 0x20 + // Bit CORE0_RESET_FLAG. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG = 0x20 + // Position of CORE0_RESET_CAUSE_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_CAUSE_CLR_Pos = 0x1d + // Bit mask of CORE0_RESET_CAUSE_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_CAUSE_CLR_Msk = 0x20000000 + // Bit CORE0_RESET_CAUSE_CLR. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_CAUSE_CLR = 0x20000000 + // Position of CORE0_RESET_FLAG_SET field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_SET_Pos = 0x1e + // Bit mask of CORE0_RESET_FLAG_SET field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_SET_Msk = 0x40000000 + // Bit CORE0_RESET_FLAG_SET. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_SET = 0x40000000 + // Position of CORE0_RESET_FLAG_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_CLR_Pos = 0x1f + // Bit mask of CORE0_RESET_FLAG_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_CLR_Msk = 0x80000000 + // Bit CORE0_RESET_FLAG_CLR. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_CLR = 0x80000000 + + // CPU_RESET: need_des + // Position of RTC_WDT_CPU_RESET_LENGTH field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_LENGTH_Pos = 0x16 + // Bit mask of RTC_WDT_CPU_RESET_LENGTH field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_LENGTH_Msk = 0x1c00000 + // Position of RTC_WDT_CPU_RESET_EN field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_EN_Pos = 0x19 + // Bit mask of RTC_WDT_CPU_RESET_EN field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_EN_Msk = 0x2000000 + // Bit RTC_WDT_CPU_RESET_EN. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_EN = 0x2000000 + // Position of CPU_STALL_WAIT field. + LP_CLKRST_CPU_RESET_CPU_STALL_WAIT_Pos = 0x1a + // Bit mask of CPU_STALL_WAIT field. + LP_CLKRST_CPU_RESET_CPU_STALL_WAIT_Msk = 0x7c000000 + // Position of CPU_STALL_EN field. + LP_CLKRST_CPU_RESET_CPU_STALL_EN_Pos = 0x1f + // Bit mask of CPU_STALL_EN field. + LP_CLKRST_CPU_RESET_CPU_STALL_EN_Msk = 0x80000000 + // Bit CPU_STALL_EN. + LP_CLKRST_CPU_RESET_CPU_STALL_EN = 0x80000000 + + // FOSC_CNTL: need_des + // Position of FOSC_DFREQ field. + LP_CLKRST_FOSC_CNTL_FOSC_DFREQ_Pos = 0x16 + // Bit mask of FOSC_DFREQ field. + LP_CLKRST_FOSC_CNTL_FOSC_DFREQ_Msk = 0xffc00000 + + // RC32K_CNTL: need_des + // Position of RC32K_DFREQ field. + LP_CLKRST_RC32K_CNTL_RC32K_DFREQ_Pos = 0x16 + // Bit mask of RC32K_DFREQ field. + LP_CLKRST_RC32K_CNTL_RC32K_DFREQ_Msk = 0xffc00000 + + // CLK_TO_HP: need_des + // Position of ICG_HP_XTAL32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_XTAL32K_Pos = 0x1c + // Bit mask of ICG_HP_XTAL32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_XTAL32K_Msk = 0x10000000 + // Bit ICG_HP_XTAL32K. + LP_CLKRST_CLK_TO_HP_ICG_HP_XTAL32K = 0x10000000 + // Position of ICG_HP_SOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_SOSC_Pos = 0x1d + // Bit mask of ICG_HP_SOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_SOSC_Msk = 0x20000000 + // Bit ICG_HP_SOSC. + LP_CLKRST_CLK_TO_HP_ICG_HP_SOSC = 0x20000000 + // Position of ICG_HP_OSC32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_OSC32K_Pos = 0x1e + // Bit mask of ICG_HP_OSC32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_OSC32K_Msk = 0x40000000 + // Bit ICG_HP_OSC32K. + LP_CLKRST_CLK_TO_HP_ICG_HP_OSC32K = 0x40000000 + // Position of ICG_HP_FOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_FOSC_Pos = 0x1f + // Bit mask of ICG_HP_FOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_FOSC_Msk = 0x80000000 + // Bit ICG_HP_FOSC. + LP_CLKRST_CLK_TO_HP_ICG_HP_FOSC = 0x80000000 + + // LPMEM_FORCE: need_des + // Position of LPMEM_CLK_FORCE_ON field. + LP_CLKRST_LPMEM_FORCE_LPMEM_CLK_FORCE_ON_Pos = 0x1f + // Bit mask of LPMEM_CLK_FORCE_ON field. + LP_CLKRST_LPMEM_FORCE_LPMEM_CLK_FORCE_ON_Msk = 0x80000000 + // Bit LPMEM_CLK_FORCE_ON. + LP_CLKRST_LPMEM_FORCE_LPMEM_CLK_FORCE_ON = 0x80000000 + + // LPPERI: need_des + // Position of LP_I2C_CLK_SEL field. + LP_CLKRST_LPPERI_LP_I2C_CLK_SEL_Pos = 0x1e + // Bit mask of LP_I2C_CLK_SEL field. + LP_CLKRST_LPPERI_LP_I2C_CLK_SEL_Msk = 0x40000000 + // Bit LP_I2C_CLK_SEL. + LP_CLKRST_LPPERI_LP_I2C_CLK_SEL = 0x40000000 + // Position of LP_UART_CLK_SEL field. + LP_CLKRST_LPPERI_LP_UART_CLK_SEL_Pos = 0x1f + // Bit mask of LP_UART_CLK_SEL field. + LP_CLKRST_LPPERI_LP_UART_CLK_SEL_Msk = 0x80000000 + // Bit LP_UART_CLK_SEL. + LP_CLKRST_LPPERI_LP_UART_CLK_SEL = 0x80000000 + + // XTAL32K: need_des + // Position of DRES_XTAL32K field. + LP_CLKRST_XTAL32K_DRES_XTAL32K_Pos = 0x16 + // Bit mask of DRES_XTAL32K field. + LP_CLKRST_XTAL32K_DRES_XTAL32K_Msk = 0x1c00000 + // Position of DGM_XTAL32K field. + LP_CLKRST_XTAL32K_DGM_XTAL32K_Pos = 0x19 + // Bit mask of DGM_XTAL32K field. + LP_CLKRST_XTAL32K_DGM_XTAL32K_Msk = 0xe000000 + // Position of DBUF_XTAL32K field. + LP_CLKRST_XTAL32K_DBUF_XTAL32K_Pos = 0x1c + // Bit mask of DBUF_XTAL32K field. + LP_CLKRST_XTAL32K_DBUF_XTAL32K_Msk = 0x10000000 + // Bit DBUF_XTAL32K. + LP_CLKRST_XTAL32K_DBUF_XTAL32K = 0x10000000 + // Position of DAC_XTAL32K field. + LP_CLKRST_XTAL32K_DAC_XTAL32K_Pos = 0x1d + // Bit mask of DAC_XTAL32K field. + LP_CLKRST_XTAL32K_DAC_XTAL32K_Msk = 0xe0000000 + + // DATE: need_des + // Position of CLKRST_DATE field. + LP_CLKRST_DATE_CLKRST_DATE_Pos = 0x0 + // Bit mask of CLKRST_DATE field. + LP_CLKRST_DATE_CLKRST_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_CLKRST_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_CLKRST_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_CLKRST_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_I2C0: Low-power I2C (Inter-Integrated Circuit) Controller 0 +const ( + // I2C_SCL_LOW_PERIOD: Configures the low level width of the SCL Clock + // Position of I2C_SCL_LOW_PERIOD field. + LP_I2C0_I2C_SCL_LOW_PERIOD_I2C_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of I2C_SCL_LOW_PERIOD field. + LP_I2C0_I2C_SCL_LOW_PERIOD_I2C_SCL_LOW_PERIOD_Msk = 0x1ff + + // I2C_CTR: Transmission setting + // Position of I2C_SDA_FORCE_OUT field. + LP_I2C0_I2C_CTR_I2C_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of I2C_SDA_FORCE_OUT field. + LP_I2C0_I2C_CTR_I2C_SDA_FORCE_OUT_Msk = 0x1 + // Bit I2C_SDA_FORCE_OUT. + LP_I2C0_I2C_CTR_I2C_SDA_FORCE_OUT = 0x1 + // Position of I2C_SCL_FORCE_OUT field. + LP_I2C0_I2C_CTR_I2C_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of I2C_SCL_FORCE_OUT field. + LP_I2C0_I2C_CTR_I2C_SCL_FORCE_OUT_Msk = 0x2 + // Bit I2C_SCL_FORCE_OUT. + LP_I2C0_I2C_CTR_I2C_SCL_FORCE_OUT = 0x2 + // Position of I2C_SAMPLE_SCL_LEVEL field. + LP_I2C0_I2C_CTR_I2C_SAMPLE_SCL_LEVEL_Pos = 0x2 + // Bit mask of I2C_SAMPLE_SCL_LEVEL field. + LP_I2C0_I2C_CTR_I2C_SAMPLE_SCL_LEVEL_Msk = 0x4 + // Bit I2C_SAMPLE_SCL_LEVEL. + LP_I2C0_I2C_CTR_I2C_SAMPLE_SCL_LEVEL = 0x4 + // Position of I2C_RX_FULL_ACK_LEVEL field. + LP_I2C0_I2C_CTR_I2C_RX_FULL_ACK_LEVEL_Pos = 0x3 + // Bit mask of I2C_RX_FULL_ACK_LEVEL field. + LP_I2C0_I2C_CTR_I2C_RX_FULL_ACK_LEVEL_Msk = 0x8 + // Bit I2C_RX_FULL_ACK_LEVEL. + LP_I2C0_I2C_CTR_I2C_RX_FULL_ACK_LEVEL = 0x8 + // Position of I2C_TRANS_START field. + LP_I2C0_I2C_CTR_I2C_TRANS_START_Pos = 0x5 + // Bit mask of I2C_TRANS_START field. + LP_I2C0_I2C_CTR_I2C_TRANS_START_Msk = 0x20 + // Bit I2C_TRANS_START. + LP_I2C0_I2C_CTR_I2C_TRANS_START = 0x20 + // Position of I2C_TX_LSB_FIRST field. + LP_I2C0_I2C_CTR_I2C_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of I2C_TX_LSB_FIRST field. + LP_I2C0_I2C_CTR_I2C_TX_LSB_FIRST_Msk = 0x40 + // Bit I2C_TX_LSB_FIRST. + LP_I2C0_I2C_CTR_I2C_TX_LSB_FIRST = 0x40 + // Position of I2C_RX_LSB_FIRST field. + LP_I2C0_I2C_CTR_I2C_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of I2C_RX_LSB_FIRST field. + LP_I2C0_I2C_CTR_I2C_RX_LSB_FIRST_Msk = 0x80 + // Bit I2C_RX_LSB_FIRST. + LP_I2C0_I2C_CTR_I2C_RX_LSB_FIRST = 0x80 + // Position of I2C_CLK_EN field. + LP_I2C0_I2C_CTR_I2C_CLK_EN_Pos = 0x8 + // Bit mask of I2C_CLK_EN field. + LP_I2C0_I2C_CTR_I2C_CLK_EN_Msk = 0x100 + // Bit I2C_CLK_EN. + LP_I2C0_I2C_CTR_I2C_CLK_EN = 0x100 + // Position of I2C_ARBITRATION_EN field. + LP_I2C0_I2C_CTR_I2C_ARBITRATION_EN_Pos = 0x9 + // Bit mask of I2C_ARBITRATION_EN field. + LP_I2C0_I2C_CTR_I2C_ARBITRATION_EN_Msk = 0x200 + // Bit I2C_ARBITRATION_EN. + LP_I2C0_I2C_CTR_I2C_ARBITRATION_EN = 0x200 + // Position of I2C_FSM_RST field. + LP_I2C0_I2C_CTR_I2C_FSM_RST_Pos = 0xa + // Bit mask of I2C_FSM_RST field. + LP_I2C0_I2C_CTR_I2C_FSM_RST_Msk = 0x400 + // Bit I2C_FSM_RST. + LP_I2C0_I2C_CTR_I2C_FSM_RST = 0x400 + // Position of I2C_CONF_UPGATE field. + LP_I2C0_I2C_CTR_I2C_CONF_UPGATE_Pos = 0xb + // Bit mask of I2C_CONF_UPGATE field. + LP_I2C0_I2C_CTR_I2C_CONF_UPGATE_Msk = 0x800 + // Bit I2C_CONF_UPGATE. + LP_I2C0_I2C_CTR_I2C_CONF_UPGATE = 0x800 + + // I2C_SR: Describe I2C work status. + // Position of I2C_RESP_REC field. + LP_I2C0_I2C_SR_I2C_RESP_REC_Pos = 0x0 + // Bit mask of I2C_RESP_REC field. + LP_I2C0_I2C_SR_I2C_RESP_REC_Msk = 0x1 + // Bit I2C_RESP_REC. + LP_I2C0_I2C_SR_I2C_RESP_REC = 0x1 + // Position of I2C_ARB_LOST field. + LP_I2C0_I2C_SR_I2C_ARB_LOST_Pos = 0x3 + // Bit mask of I2C_ARB_LOST field. + LP_I2C0_I2C_SR_I2C_ARB_LOST_Msk = 0x8 + // Bit I2C_ARB_LOST. + LP_I2C0_I2C_SR_I2C_ARB_LOST = 0x8 + // Position of I2C_BUS_BUSY field. + LP_I2C0_I2C_SR_I2C_BUS_BUSY_Pos = 0x4 + // Bit mask of I2C_BUS_BUSY field. + LP_I2C0_I2C_SR_I2C_BUS_BUSY_Msk = 0x10 + // Bit I2C_BUS_BUSY. + LP_I2C0_I2C_SR_I2C_BUS_BUSY = 0x10 + // Position of I2C_RXFIFO_CNT field. + LP_I2C0_I2C_SR_I2C_RXFIFO_CNT_Pos = 0x8 + // Bit mask of I2C_RXFIFO_CNT field. + LP_I2C0_I2C_SR_I2C_RXFIFO_CNT_Msk = 0x1f00 + // Position of I2C_TXFIFO_CNT field. + LP_I2C0_I2C_SR_I2C_TXFIFO_CNT_Pos = 0x12 + // Bit mask of I2C_TXFIFO_CNT field. + LP_I2C0_I2C_SR_I2C_TXFIFO_CNT_Msk = 0x7c0000 + // Position of I2C_SCL_MAIN_STATE_LAST field. + LP_I2C0_I2C_SR_I2C_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of I2C_SCL_MAIN_STATE_LAST field. + LP_I2C0_I2C_SR_I2C_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of I2C_SCL_STATE_LAST field. + LP_I2C0_I2C_SR_I2C_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of I2C_SCL_STATE_LAST field. + LP_I2C0_I2C_SR_I2C_SCL_STATE_LAST_Msk = 0x70000000 + + // I2C_TO: Setting time out control for receiving data. + // Position of I2C_TIME_OUT_VALUE field. + LP_I2C0_I2C_TO_I2C_TIME_OUT_VALUE_Pos = 0x0 + // Bit mask of I2C_TIME_OUT_VALUE field. + LP_I2C0_I2C_TO_I2C_TIME_OUT_VALUE_Msk = 0x1f + // Position of I2C_TIME_OUT_EN field. + LP_I2C0_I2C_TO_I2C_TIME_OUT_EN_Pos = 0x5 + // Bit mask of I2C_TIME_OUT_EN field. + LP_I2C0_I2C_TO_I2C_TIME_OUT_EN_Msk = 0x20 + // Bit I2C_TIME_OUT_EN. + LP_I2C0_I2C_TO_I2C_TIME_OUT_EN = 0x20 + + // I2C_FIFO_ST: FIFO status register. + // Position of I2C_RXFIFO_RADDR field. + LP_I2C0_I2C_FIFO_ST_I2C_RXFIFO_RADDR_Pos = 0x0 + // Bit mask of I2C_RXFIFO_RADDR field. + LP_I2C0_I2C_FIFO_ST_I2C_RXFIFO_RADDR_Msk = 0xf + // Position of I2C_RXFIFO_WADDR field. + LP_I2C0_I2C_FIFO_ST_I2C_RXFIFO_WADDR_Pos = 0x5 + // Bit mask of I2C_RXFIFO_WADDR field. + LP_I2C0_I2C_FIFO_ST_I2C_RXFIFO_WADDR_Msk = 0x1e0 + // Position of I2C_TXFIFO_RADDR field. + LP_I2C0_I2C_FIFO_ST_I2C_TXFIFO_RADDR_Pos = 0xa + // Bit mask of I2C_TXFIFO_RADDR field. + LP_I2C0_I2C_FIFO_ST_I2C_TXFIFO_RADDR_Msk = 0x3c00 + // Position of I2C_TXFIFO_WADDR field. + LP_I2C0_I2C_FIFO_ST_I2C_TXFIFO_WADDR_Pos = 0xf + // Bit mask of I2C_TXFIFO_WADDR field. + LP_I2C0_I2C_FIFO_ST_I2C_TXFIFO_WADDR_Msk = 0x78000 + + // FIFO_CONF: FIFO configuration register. + // Position of RXFIFO_WM_THRHD field. + LP_I2C0_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_WM_THRHD field. + LP_I2C0_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0xf + // Position of TXFIFO_WM_THRHD field. + LP_I2C0_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5 + // Bit mask of TXFIFO_WM_THRHD field. + LP_I2C0_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x1e0 + // Position of NONFIFO_EN field. + LP_I2C0_FIFO_CONF_NONFIFO_EN_Pos = 0xa + // Bit mask of NONFIFO_EN field. + LP_I2C0_FIFO_CONF_NONFIFO_EN_Msk = 0x400 + // Bit NONFIFO_EN. + LP_I2C0_FIFO_CONF_NONFIFO_EN = 0x400 + // Position of RX_FIFO_RST field. + LP_I2C0_FIFO_CONF_RX_FIFO_RST_Pos = 0xc + // Bit mask of RX_FIFO_RST field. + LP_I2C0_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000 + // Bit RX_FIFO_RST. + LP_I2C0_FIFO_CONF_RX_FIFO_RST = 0x1000 + // Position of TX_FIFO_RST field. + LP_I2C0_FIFO_CONF_TX_FIFO_RST_Pos = 0xd + // Bit mask of TX_FIFO_RST field. + LP_I2C0_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000 + // Bit TX_FIFO_RST. + LP_I2C0_FIFO_CONF_TX_FIFO_RST = 0x2000 + // Position of FIFO_PRT_EN field. + LP_I2C0_FIFO_CONF_FIFO_PRT_EN_Pos = 0xe + // Bit mask of FIFO_PRT_EN field. + LP_I2C0_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000 + // Bit FIFO_PRT_EN. + LP_I2C0_FIFO_CONF_FIFO_PRT_EN = 0x4000 + + // I2C_DATA: Rx FIFO read data. + // Position of I2C_FIFO_RDATA field. + LP_I2C0_I2C_DATA_I2C_FIFO_RDATA_Pos = 0x0 + // Bit mask of I2C_FIFO_RDATA field. + LP_I2C0_I2C_DATA_I2C_FIFO_RDATA_Msk = 0xff + + // I2C_INT_RAW: Raw interrupt status + // Position of I2C_RXFIFO_WM_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_RXFIFO_WM_INT_RAW_Pos = 0x0 + // Bit mask of I2C_RXFIFO_WM_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_RXFIFO_WM_INT_RAW_Msk = 0x1 + // Bit I2C_RXFIFO_WM_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_RXFIFO_WM_INT_RAW = 0x1 + // Position of I2C_TXFIFO_WM_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TXFIFO_WM_INT_RAW_Pos = 0x1 + // Bit mask of I2C_TXFIFO_WM_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TXFIFO_WM_INT_RAW_Msk = 0x2 + // Bit I2C_TXFIFO_WM_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_TXFIFO_WM_INT_RAW = 0x2 + // Position of I2C_RXFIFO_OVF_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_RXFIFO_OVF_INT_RAW_Pos = 0x2 + // Bit mask of I2C_RXFIFO_OVF_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_RXFIFO_OVF_INT_RAW_Msk = 0x4 + // Bit I2C_RXFIFO_OVF_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_RXFIFO_OVF_INT_RAW = 0x4 + // Position of I2C_END_DETECT_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_END_DETECT_INT_RAW_Pos = 0x3 + // Bit mask of I2C_END_DETECT_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_END_DETECT_INT_RAW_Msk = 0x8 + // Bit I2C_END_DETECT_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_END_DETECT_INT_RAW = 0x8 + // Position of I2C_BYTE_TRANS_DONE_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4 + // Bit mask of I2C_BYTE_TRANS_DONE_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10 + // Bit I2C_BYTE_TRANS_DONE_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_BYTE_TRANS_DONE_INT_RAW = 0x10 + // Position of I2C_ARBITRATION_LOST_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_ARBITRATION_LOST_INT_RAW_Pos = 0x5 + // Bit mask of I2C_ARBITRATION_LOST_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_ARBITRATION_LOST_INT_RAW_Msk = 0x20 + // Bit I2C_ARBITRATION_LOST_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_ARBITRATION_LOST_INT_RAW = 0x20 + // Position of I2C_MST_TXFIFO_UDF_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6 + // Bit mask of I2C_MST_TXFIFO_UDF_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40 + // Bit I2C_MST_TXFIFO_UDF_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_MST_TXFIFO_UDF_INT_RAW = 0x40 + // Position of I2C_TRANS_COMPLETE_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TRANS_COMPLETE_INT_RAW_Pos = 0x7 + // Bit mask of I2C_TRANS_COMPLETE_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TRANS_COMPLETE_INT_RAW_Msk = 0x80 + // Bit I2C_TRANS_COMPLETE_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_TRANS_COMPLETE_INT_RAW = 0x80 + // Position of I2C_TIME_OUT_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TIME_OUT_INT_RAW_Pos = 0x8 + // Bit mask of I2C_TIME_OUT_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TIME_OUT_INT_RAW_Msk = 0x100 + // Bit I2C_TIME_OUT_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_TIME_OUT_INT_RAW = 0x100 + // Position of I2C_TRANS_START_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TRANS_START_INT_RAW_Pos = 0x9 + // Bit mask of I2C_TRANS_START_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TRANS_START_INT_RAW_Msk = 0x200 + // Bit I2C_TRANS_START_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_TRANS_START_INT_RAW = 0x200 + // Position of I2C_NACK_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_NACK_INT_RAW_Pos = 0xa + // Bit mask of I2C_NACK_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_NACK_INT_RAW_Msk = 0x400 + // Bit I2C_NACK_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_NACK_INT_RAW = 0x400 + // Position of I2C_TXFIFO_OVF_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TXFIFO_OVF_INT_RAW_Pos = 0xb + // Bit mask of I2C_TXFIFO_OVF_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_TXFIFO_OVF_INT_RAW_Msk = 0x800 + // Bit I2C_TXFIFO_OVF_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_TXFIFO_OVF_INT_RAW = 0x800 + // Position of I2C_RXFIFO_UDF_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_RXFIFO_UDF_INT_RAW_Pos = 0xc + // Bit mask of I2C_RXFIFO_UDF_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_RXFIFO_UDF_INT_RAW_Msk = 0x1000 + // Bit I2C_RXFIFO_UDF_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_RXFIFO_UDF_INT_RAW = 0x1000 + // Position of I2C_SCL_ST_TO_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_SCL_ST_TO_INT_RAW_Pos = 0xd + // Bit mask of I2C_SCL_ST_TO_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_SCL_ST_TO_INT_RAW_Msk = 0x2000 + // Bit I2C_SCL_ST_TO_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_SCL_ST_TO_INT_RAW = 0x2000 + // Position of I2C_SCL_MAIN_ST_TO_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe + // Bit mask of I2C_SCL_MAIN_ST_TO_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000 + // Bit I2C_SCL_MAIN_ST_TO_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_SCL_MAIN_ST_TO_INT_RAW = 0x4000 + // Position of I2C_DET_START_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_DET_START_INT_RAW_Pos = 0xf + // Bit mask of I2C_DET_START_INT_RAW field. + LP_I2C0_I2C_INT_RAW_I2C_DET_START_INT_RAW_Msk = 0x8000 + // Bit I2C_DET_START_INT_RAW. + LP_I2C0_I2C_INT_RAW_I2C_DET_START_INT_RAW = 0x8000 + + // I2C_INT_CLR: Interrupt clear bits + // Position of I2C_RXFIFO_WM_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_RXFIFO_WM_INT_CLR_Pos = 0x0 + // Bit mask of I2C_RXFIFO_WM_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_RXFIFO_WM_INT_CLR_Msk = 0x1 + // Bit I2C_RXFIFO_WM_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_RXFIFO_WM_INT_CLR = 0x1 + // Position of I2C_TXFIFO_WM_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TXFIFO_WM_INT_CLR_Pos = 0x1 + // Bit mask of I2C_TXFIFO_WM_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TXFIFO_WM_INT_CLR_Msk = 0x2 + // Bit I2C_TXFIFO_WM_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_TXFIFO_WM_INT_CLR = 0x2 + // Position of I2C_RXFIFO_OVF_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_RXFIFO_OVF_INT_CLR_Pos = 0x2 + // Bit mask of I2C_RXFIFO_OVF_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_RXFIFO_OVF_INT_CLR_Msk = 0x4 + // Bit I2C_RXFIFO_OVF_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_RXFIFO_OVF_INT_CLR = 0x4 + // Position of I2C_END_DETECT_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_END_DETECT_INT_CLR_Pos = 0x3 + // Bit mask of I2C_END_DETECT_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_END_DETECT_INT_CLR_Msk = 0x8 + // Bit I2C_END_DETECT_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_END_DETECT_INT_CLR = 0x8 + // Position of I2C_BYTE_TRANS_DONE_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4 + // Bit mask of I2C_BYTE_TRANS_DONE_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10 + // Bit I2C_BYTE_TRANS_DONE_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_BYTE_TRANS_DONE_INT_CLR = 0x10 + // Position of I2C_ARBITRATION_LOST_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of I2C_ARBITRATION_LOST_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit I2C_ARBITRATION_LOST_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of I2C_MST_TXFIFO_UDF_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6 + // Bit mask of I2C_MST_TXFIFO_UDF_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40 + // Bit I2C_MST_TXFIFO_UDF_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_MST_TXFIFO_UDF_INT_CLR = 0x40 + // Position of I2C_TRANS_COMPLETE_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of I2C_TRANS_COMPLETE_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit I2C_TRANS_COMPLETE_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of I2C_TIME_OUT_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of I2C_TIME_OUT_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit I2C_TIME_OUT_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_TIME_OUT_INT_CLR = 0x100 + // Position of I2C_TRANS_START_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TRANS_START_INT_CLR_Pos = 0x9 + // Bit mask of I2C_TRANS_START_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TRANS_START_INT_CLR_Msk = 0x200 + // Bit I2C_TRANS_START_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_TRANS_START_INT_CLR = 0x200 + // Position of I2C_NACK_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_NACK_INT_CLR_Pos = 0xa + // Bit mask of I2C_NACK_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_NACK_INT_CLR_Msk = 0x400 + // Bit I2C_NACK_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_NACK_INT_CLR = 0x400 + // Position of I2C_TXFIFO_OVF_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TXFIFO_OVF_INT_CLR_Pos = 0xb + // Bit mask of I2C_TXFIFO_OVF_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_TXFIFO_OVF_INT_CLR_Msk = 0x800 + // Bit I2C_TXFIFO_OVF_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_TXFIFO_OVF_INT_CLR = 0x800 + // Position of I2C_RXFIFO_UDF_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_RXFIFO_UDF_INT_CLR_Pos = 0xc + // Bit mask of I2C_RXFIFO_UDF_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_RXFIFO_UDF_INT_CLR_Msk = 0x1000 + // Bit I2C_RXFIFO_UDF_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_RXFIFO_UDF_INT_CLR = 0x1000 + // Position of I2C_SCL_ST_TO_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_SCL_ST_TO_INT_CLR_Pos = 0xd + // Bit mask of I2C_SCL_ST_TO_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_SCL_ST_TO_INT_CLR_Msk = 0x2000 + // Bit I2C_SCL_ST_TO_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_SCL_ST_TO_INT_CLR = 0x2000 + // Position of I2C_SCL_MAIN_ST_TO_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe + // Bit mask of I2C_SCL_MAIN_ST_TO_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000 + // Bit I2C_SCL_MAIN_ST_TO_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_SCL_MAIN_ST_TO_INT_CLR = 0x4000 + // Position of I2C_DET_START_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_DET_START_INT_CLR_Pos = 0xf + // Bit mask of I2C_DET_START_INT_CLR field. + LP_I2C0_I2C_INT_CLR_I2C_DET_START_INT_CLR_Msk = 0x8000 + // Bit I2C_DET_START_INT_CLR. + LP_I2C0_I2C_INT_CLR_I2C_DET_START_INT_CLR = 0x8000 + + // I2C_INT_ENA: Interrupt enable bits + // Position of I2C_RXFIFO_WM_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_RXFIFO_WM_INT_ENA_Pos = 0x0 + // Bit mask of I2C_RXFIFO_WM_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_RXFIFO_WM_INT_ENA_Msk = 0x1 + // Bit I2C_RXFIFO_WM_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_RXFIFO_WM_INT_ENA = 0x1 + // Position of I2C_TXFIFO_WM_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TXFIFO_WM_INT_ENA_Pos = 0x1 + // Bit mask of I2C_TXFIFO_WM_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TXFIFO_WM_INT_ENA_Msk = 0x2 + // Bit I2C_TXFIFO_WM_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_TXFIFO_WM_INT_ENA = 0x2 + // Position of I2C_RXFIFO_OVF_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_RXFIFO_OVF_INT_ENA_Pos = 0x2 + // Bit mask of I2C_RXFIFO_OVF_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_RXFIFO_OVF_INT_ENA_Msk = 0x4 + // Bit I2C_RXFIFO_OVF_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_RXFIFO_OVF_INT_ENA = 0x4 + // Position of I2C_END_DETECT_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_END_DETECT_INT_ENA_Pos = 0x3 + // Bit mask of I2C_END_DETECT_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_END_DETECT_INT_ENA_Msk = 0x8 + // Bit I2C_END_DETECT_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_END_DETECT_INT_ENA = 0x8 + // Position of I2C_BYTE_TRANS_DONE_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4 + // Bit mask of I2C_BYTE_TRANS_DONE_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10 + // Bit I2C_BYTE_TRANS_DONE_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_BYTE_TRANS_DONE_INT_ENA = 0x10 + // Position of I2C_ARBITRATION_LOST_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_ARBITRATION_LOST_INT_ENA_Pos = 0x5 + // Bit mask of I2C_ARBITRATION_LOST_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_ARBITRATION_LOST_INT_ENA_Msk = 0x20 + // Bit I2C_ARBITRATION_LOST_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_ARBITRATION_LOST_INT_ENA = 0x20 + // Position of I2C_MST_TXFIFO_UDF_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6 + // Bit mask of I2C_MST_TXFIFO_UDF_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40 + // Bit I2C_MST_TXFIFO_UDF_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_MST_TXFIFO_UDF_INT_ENA = 0x40 + // Position of I2C_TRANS_COMPLETE_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TRANS_COMPLETE_INT_ENA_Pos = 0x7 + // Bit mask of I2C_TRANS_COMPLETE_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TRANS_COMPLETE_INT_ENA_Msk = 0x80 + // Bit I2C_TRANS_COMPLETE_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_TRANS_COMPLETE_INT_ENA = 0x80 + // Position of I2C_TIME_OUT_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TIME_OUT_INT_ENA_Pos = 0x8 + // Bit mask of I2C_TIME_OUT_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TIME_OUT_INT_ENA_Msk = 0x100 + // Bit I2C_TIME_OUT_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_TIME_OUT_INT_ENA = 0x100 + // Position of I2C_TRANS_START_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TRANS_START_INT_ENA_Pos = 0x9 + // Bit mask of I2C_TRANS_START_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TRANS_START_INT_ENA_Msk = 0x200 + // Bit I2C_TRANS_START_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_TRANS_START_INT_ENA = 0x200 + // Position of I2C_NACK_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_NACK_INT_ENA_Pos = 0xa + // Bit mask of I2C_NACK_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_NACK_INT_ENA_Msk = 0x400 + // Bit I2C_NACK_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_NACK_INT_ENA = 0x400 + // Position of I2C_TXFIFO_OVF_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TXFIFO_OVF_INT_ENA_Pos = 0xb + // Bit mask of I2C_TXFIFO_OVF_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_TXFIFO_OVF_INT_ENA_Msk = 0x800 + // Bit I2C_TXFIFO_OVF_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_TXFIFO_OVF_INT_ENA = 0x800 + // Position of I2C_RXFIFO_UDF_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_RXFIFO_UDF_INT_ENA_Pos = 0xc + // Bit mask of I2C_RXFIFO_UDF_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_RXFIFO_UDF_INT_ENA_Msk = 0x1000 + // Bit I2C_RXFIFO_UDF_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_RXFIFO_UDF_INT_ENA = 0x1000 + // Position of I2C_SCL_ST_TO_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_SCL_ST_TO_INT_ENA_Pos = 0xd + // Bit mask of I2C_SCL_ST_TO_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_SCL_ST_TO_INT_ENA_Msk = 0x2000 + // Bit I2C_SCL_ST_TO_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_SCL_ST_TO_INT_ENA = 0x2000 + // Position of I2C_SCL_MAIN_ST_TO_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe + // Bit mask of I2C_SCL_MAIN_ST_TO_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000 + // Bit I2C_SCL_MAIN_ST_TO_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_SCL_MAIN_ST_TO_INT_ENA = 0x4000 + // Position of I2C_DET_START_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_DET_START_INT_ENA_Pos = 0xf + // Bit mask of I2C_DET_START_INT_ENA field. + LP_I2C0_I2C_INT_ENA_I2C_DET_START_INT_ENA_Msk = 0x8000 + // Bit I2C_DET_START_INT_ENA. + LP_I2C0_I2C_INT_ENA_I2C_DET_START_INT_ENA = 0x8000 + + // I2C_INT_STATUS: Status of captured I2C communication events + // Position of I2C_RXFIFO_WM_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_RXFIFO_WM_INT_ST_Pos = 0x0 + // Bit mask of I2C_RXFIFO_WM_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_RXFIFO_WM_INT_ST_Msk = 0x1 + // Bit I2C_RXFIFO_WM_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_RXFIFO_WM_INT_ST = 0x1 + // Position of I2C_TXFIFO_WM_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TXFIFO_WM_INT_ST_Pos = 0x1 + // Bit mask of I2C_TXFIFO_WM_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TXFIFO_WM_INT_ST_Msk = 0x2 + // Bit I2C_TXFIFO_WM_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_TXFIFO_WM_INT_ST = 0x2 + // Position of I2C_RXFIFO_OVF_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_RXFIFO_OVF_INT_ST_Pos = 0x2 + // Bit mask of I2C_RXFIFO_OVF_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_RXFIFO_OVF_INT_ST_Msk = 0x4 + // Bit I2C_RXFIFO_OVF_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_RXFIFO_OVF_INT_ST = 0x4 + // Position of I2C_END_DETECT_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_END_DETECT_INT_ST_Pos = 0x3 + // Bit mask of I2C_END_DETECT_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_END_DETECT_INT_ST_Msk = 0x8 + // Bit I2C_END_DETECT_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_END_DETECT_INT_ST = 0x8 + // Position of I2C_BYTE_TRANS_DONE_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_BYTE_TRANS_DONE_INT_ST_Pos = 0x4 + // Bit mask of I2C_BYTE_TRANS_DONE_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_BYTE_TRANS_DONE_INT_ST_Msk = 0x10 + // Bit I2C_BYTE_TRANS_DONE_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_BYTE_TRANS_DONE_INT_ST = 0x10 + // Position of I2C_ARBITRATION_LOST_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_ARBITRATION_LOST_INT_ST_Pos = 0x5 + // Bit mask of I2C_ARBITRATION_LOST_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_ARBITRATION_LOST_INT_ST_Msk = 0x20 + // Bit I2C_ARBITRATION_LOST_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_ARBITRATION_LOST_INT_ST = 0x20 + // Position of I2C_MST_TXFIFO_UDF_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_MST_TXFIFO_UDF_INT_ST_Pos = 0x6 + // Bit mask of I2C_MST_TXFIFO_UDF_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_MST_TXFIFO_UDF_INT_ST_Msk = 0x40 + // Bit I2C_MST_TXFIFO_UDF_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_MST_TXFIFO_UDF_INT_ST = 0x40 + // Position of I2C_TRANS_COMPLETE_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TRANS_COMPLETE_INT_ST_Pos = 0x7 + // Bit mask of I2C_TRANS_COMPLETE_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TRANS_COMPLETE_INT_ST_Msk = 0x80 + // Bit I2C_TRANS_COMPLETE_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_TRANS_COMPLETE_INT_ST = 0x80 + // Position of I2C_TIME_OUT_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TIME_OUT_INT_ST_Pos = 0x8 + // Bit mask of I2C_TIME_OUT_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TIME_OUT_INT_ST_Msk = 0x100 + // Bit I2C_TIME_OUT_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_TIME_OUT_INT_ST = 0x100 + // Position of I2C_TRANS_START_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TRANS_START_INT_ST_Pos = 0x9 + // Bit mask of I2C_TRANS_START_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TRANS_START_INT_ST_Msk = 0x200 + // Bit I2C_TRANS_START_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_TRANS_START_INT_ST = 0x200 + // Position of I2C_NACK_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_NACK_INT_ST_Pos = 0xa + // Bit mask of I2C_NACK_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_NACK_INT_ST_Msk = 0x400 + // Bit I2C_NACK_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_NACK_INT_ST = 0x400 + // Position of I2C_TXFIFO_OVF_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TXFIFO_OVF_INT_ST_Pos = 0xb + // Bit mask of I2C_TXFIFO_OVF_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_TXFIFO_OVF_INT_ST_Msk = 0x800 + // Bit I2C_TXFIFO_OVF_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_TXFIFO_OVF_INT_ST = 0x800 + // Position of I2C_RXFIFO_UDF_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_RXFIFO_UDF_INT_ST_Pos = 0xc + // Bit mask of I2C_RXFIFO_UDF_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_RXFIFO_UDF_INT_ST_Msk = 0x1000 + // Bit I2C_RXFIFO_UDF_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_RXFIFO_UDF_INT_ST = 0x1000 + // Position of I2C_SCL_ST_TO_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_SCL_ST_TO_INT_ST_Pos = 0xd + // Bit mask of I2C_SCL_ST_TO_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_SCL_ST_TO_INT_ST_Msk = 0x2000 + // Bit I2C_SCL_ST_TO_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_SCL_ST_TO_INT_ST = 0x2000 + // Position of I2C_SCL_MAIN_ST_TO_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe + // Bit mask of I2C_SCL_MAIN_ST_TO_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000 + // Bit I2C_SCL_MAIN_ST_TO_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_SCL_MAIN_ST_TO_INT_ST = 0x4000 + // Position of I2C_DET_START_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_DET_START_INT_ST_Pos = 0xf + // Bit mask of I2C_DET_START_INT_ST field. + LP_I2C0_I2C_INT_STATUS_I2C_DET_START_INT_ST_Msk = 0x8000 + // Bit I2C_DET_START_INT_ST. + LP_I2C0_I2C_INT_STATUS_I2C_DET_START_INT_ST = 0x8000 + + // I2C_SDA_HOLD: Configures the hold time after a negative SCL edge. + // Position of TIME field. + LP_I2C0_I2C_SDA_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + LP_I2C0_I2C_SDA_HOLD_TIME_Msk = 0x1ff + + // I2C_SDA_SAMPLE: Configures the sample time after a positive SCL edge. + // Position of TIME field. + LP_I2C0_I2C_SDA_SAMPLE_TIME_Pos = 0x0 + // Bit mask of TIME field. + LP_I2C0_I2C_SDA_SAMPLE_TIME_Msk = 0x1ff + + // I2C_SCL_HIGH_PERIOD: Configures the high level width of SCL + // Position of I2C_SCL_HIGH_PERIOD field. + LP_I2C0_I2C_SCL_HIGH_PERIOD_I2C_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of I2C_SCL_HIGH_PERIOD field. + LP_I2C0_I2C_SCL_HIGH_PERIOD_I2C_SCL_HIGH_PERIOD_Msk = 0x1ff + // Position of I2C_SCL_WAIT_HIGH_PERIOD field. + LP_I2C0_I2C_SCL_HIGH_PERIOD_I2C_SCL_WAIT_HIGH_PERIOD_Pos = 0x9 + // Bit mask of I2C_SCL_WAIT_HIGH_PERIOD field. + LP_I2C0_I2C_SCL_HIGH_PERIOD_I2C_SCL_WAIT_HIGH_PERIOD_Msk = 0xfe00 + + // I2C_SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition + // Position of TIME field. + LP_I2C0_I2C_SCL_START_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + LP_I2C0_I2C_SCL_START_HOLD_TIME_Msk = 0x1ff + + // I2C_SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA + // Position of TIME field. + LP_I2C0_I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + LP_I2C0_I2C_SCL_RSTART_SETUP_TIME_Msk = 0x1ff + + // I2C_SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition + // Position of TIME field. + LP_I2C0_I2C_SCL_STOP_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + LP_I2C0_I2C_SCL_STOP_HOLD_TIME_Msk = 0x1ff + + // I2C_SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition + // Position of TIME field. + LP_I2C0_I2C_SCL_STOP_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + LP_I2C0_I2C_SCL_STOP_SETUP_TIME_Msk = 0x1ff + + // I2C_FILTER_CFG: SCL and SDA filter configuration register + // Position of I2C_SCL_FILTER_THRES field. + LP_I2C0_I2C_FILTER_CFG_I2C_SCL_FILTER_THRES_Pos = 0x0 + // Bit mask of I2C_SCL_FILTER_THRES field. + LP_I2C0_I2C_FILTER_CFG_I2C_SCL_FILTER_THRES_Msk = 0xf + // Position of I2C_SDA_FILTER_THRES field. + LP_I2C0_I2C_FILTER_CFG_I2C_SDA_FILTER_THRES_Pos = 0x4 + // Bit mask of I2C_SDA_FILTER_THRES field. + LP_I2C0_I2C_FILTER_CFG_I2C_SDA_FILTER_THRES_Msk = 0xf0 + // Position of I2C_SCL_FILTER_EN field. + LP_I2C0_I2C_FILTER_CFG_I2C_SCL_FILTER_EN_Pos = 0x8 + // Bit mask of I2C_SCL_FILTER_EN field. + LP_I2C0_I2C_FILTER_CFG_I2C_SCL_FILTER_EN_Msk = 0x100 + // Bit I2C_SCL_FILTER_EN. + LP_I2C0_I2C_FILTER_CFG_I2C_SCL_FILTER_EN = 0x100 + // Position of I2C_SDA_FILTER_EN field. + LP_I2C0_I2C_FILTER_CFG_I2C_SDA_FILTER_EN_Pos = 0x9 + // Bit mask of I2C_SDA_FILTER_EN field. + LP_I2C0_I2C_FILTER_CFG_I2C_SDA_FILTER_EN_Msk = 0x200 + // Bit I2C_SDA_FILTER_EN. + LP_I2C0_I2C_FILTER_CFG_I2C_SDA_FILTER_EN = 0x200 + + // I2C_CLK_CONF: I2C CLK configuration register + // Position of I2C_SCLK_DIV_NUM field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_DIV_NUM_Pos = 0x0 + // Bit mask of I2C_SCLK_DIV_NUM field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_DIV_NUM_Msk = 0xff + // Position of I2C_SCLK_DIV_A field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_DIV_A_Pos = 0x8 + // Bit mask of I2C_SCLK_DIV_A field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_DIV_A_Msk = 0x3f00 + // Position of I2C_SCLK_DIV_B field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_DIV_B_Pos = 0xe + // Bit mask of I2C_SCLK_DIV_B field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_DIV_B_Msk = 0xfc000 + // Position of I2C_SCLK_SEL field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_SEL_Pos = 0x14 + // Bit mask of I2C_SCLK_SEL field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_SEL_Msk = 0x100000 + // Bit I2C_SCLK_SEL. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_SEL = 0x100000 + // Position of I2C_SCLK_ACTIVE field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_ACTIVE_Pos = 0x15 + // Bit mask of I2C_SCLK_ACTIVE field. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_ACTIVE_Msk = 0x200000 + // Bit I2C_SCLK_ACTIVE. + LP_I2C0_I2C_CLK_CONF_I2C_SCLK_ACTIVE = 0x200000 + + // I2C_COMD0: I2C command register 0 + // Position of I2C_COMMAND0 field. + LP_I2C0_I2C_COMD0_I2C_COMMAND0_Pos = 0x0 + // Bit mask of I2C_COMMAND0 field. + LP_I2C0_I2C_COMD0_I2C_COMMAND0_Msk = 0x3fff + // Position of I2C_COMMAND0_DONE field. + LP_I2C0_I2C_COMD0_I2C_COMMAND0_DONE_Pos = 0x1f + // Bit mask of I2C_COMMAND0_DONE field. + LP_I2C0_I2C_COMD0_I2C_COMMAND0_DONE_Msk = 0x80000000 + // Bit I2C_COMMAND0_DONE. + LP_I2C0_I2C_COMD0_I2C_COMMAND0_DONE = 0x80000000 + + // I2C_COMD1: I2C command register 1 + // Position of I2C_COMMAND1 field. + LP_I2C0_I2C_COMD1_I2C_COMMAND1_Pos = 0x0 + // Bit mask of I2C_COMMAND1 field. + LP_I2C0_I2C_COMD1_I2C_COMMAND1_Msk = 0x3fff + // Position of I2C_COMMAND1_DONE field. + LP_I2C0_I2C_COMD1_I2C_COMMAND1_DONE_Pos = 0x1f + // Bit mask of I2C_COMMAND1_DONE field. + LP_I2C0_I2C_COMD1_I2C_COMMAND1_DONE_Msk = 0x80000000 + // Bit I2C_COMMAND1_DONE. + LP_I2C0_I2C_COMD1_I2C_COMMAND1_DONE = 0x80000000 + + // I2C_COMD2: I2C command register 2 + // Position of I2C_COMMAND2 field. + LP_I2C0_I2C_COMD2_I2C_COMMAND2_Pos = 0x0 + // Bit mask of I2C_COMMAND2 field. + LP_I2C0_I2C_COMD2_I2C_COMMAND2_Msk = 0x3fff + // Position of I2C_COMMAND2_DONE field. + LP_I2C0_I2C_COMD2_I2C_COMMAND2_DONE_Pos = 0x1f + // Bit mask of I2C_COMMAND2_DONE field. + LP_I2C0_I2C_COMD2_I2C_COMMAND2_DONE_Msk = 0x80000000 + // Bit I2C_COMMAND2_DONE. + LP_I2C0_I2C_COMD2_I2C_COMMAND2_DONE = 0x80000000 + + // I2C_COMD3: I2C command register 3 + // Position of I2C_COMMAND3 field. + LP_I2C0_I2C_COMD3_I2C_COMMAND3_Pos = 0x0 + // Bit mask of I2C_COMMAND3 field. + LP_I2C0_I2C_COMD3_I2C_COMMAND3_Msk = 0x3fff + // Position of I2C_COMMAND3_DONE field. + LP_I2C0_I2C_COMD3_I2C_COMMAND3_DONE_Pos = 0x1f + // Bit mask of I2C_COMMAND3_DONE field. + LP_I2C0_I2C_COMD3_I2C_COMMAND3_DONE_Msk = 0x80000000 + // Bit I2C_COMMAND3_DONE. + LP_I2C0_I2C_COMD3_I2C_COMMAND3_DONE = 0x80000000 + + // I2C_COMD4: I2C command register 4 + // Position of I2C_COMMAND4 field. + LP_I2C0_I2C_COMD4_I2C_COMMAND4_Pos = 0x0 + // Bit mask of I2C_COMMAND4 field. + LP_I2C0_I2C_COMD4_I2C_COMMAND4_Msk = 0x3fff + // Position of I2C_COMMAND4_DONE field. + LP_I2C0_I2C_COMD4_I2C_COMMAND4_DONE_Pos = 0x1f + // Bit mask of I2C_COMMAND4_DONE field. + LP_I2C0_I2C_COMD4_I2C_COMMAND4_DONE_Msk = 0x80000000 + // Bit I2C_COMMAND4_DONE. + LP_I2C0_I2C_COMD4_I2C_COMMAND4_DONE = 0x80000000 + + // I2C_COMD5: I2C command register 5 + // Position of I2C_COMMAND5 field. + LP_I2C0_I2C_COMD5_I2C_COMMAND5_Pos = 0x0 + // Bit mask of I2C_COMMAND5 field. + LP_I2C0_I2C_COMD5_I2C_COMMAND5_Msk = 0x3fff + // Position of I2C_COMMAND5_DONE field. + LP_I2C0_I2C_COMD5_I2C_COMMAND5_DONE_Pos = 0x1f + // Bit mask of I2C_COMMAND5_DONE field. + LP_I2C0_I2C_COMD5_I2C_COMMAND5_DONE_Msk = 0x80000000 + // Bit I2C_COMMAND5_DONE. + LP_I2C0_I2C_COMD5_I2C_COMMAND5_DONE = 0x80000000 + + // I2C_COMD6: I2C command register 6 + // Position of I2C_COMMAND6 field. + LP_I2C0_I2C_COMD6_I2C_COMMAND6_Pos = 0x0 + // Bit mask of I2C_COMMAND6 field. + LP_I2C0_I2C_COMD6_I2C_COMMAND6_Msk = 0x3fff + // Position of I2C_COMMAND6_DONE field. + LP_I2C0_I2C_COMD6_I2C_COMMAND6_DONE_Pos = 0x1f + // Bit mask of I2C_COMMAND6_DONE field. + LP_I2C0_I2C_COMD6_I2C_COMMAND6_DONE_Msk = 0x80000000 + // Bit I2C_COMMAND6_DONE. + LP_I2C0_I2C_COMD6_I2C_COMMAND6_DONE = 0x80000000 + + // I2C_COMD7: I2C command register 7 + // Position of I2C_COMMAND7 field. + LP_I2C0_I2C_COMD7_I2C_COMMAND7_Pos = 0x0 + // Bit mask of I2C_COMMAND7 field. + LP_I2C0_I2C_COMD7_I2C_COMMAND7_Msk = 0x3fff + // Position of I2C_COMMAND7_DONE field. + LP_I2C0_I2C_COMD7_I2C_COMMAND7_DONE_Pos = 0x1f + // Bit mask of I2C_COMMAND7_DONE field. + LP_I2C0_I2C_COMD7_I2C_COMMAND7_DONE_Msk = 0x80000000 + // Bit I2C_COMMAND7_DONE. + LP_I2C0_I2C_COMD7_I2C_COMMAND7_DONE = 0x80000000 + + // I2C_SCL_ST_TIME_OUT: SCL status time out register + // Position of I2C_SCL_ST_TO_I2C field. + LP_I2C0_I2C_SCL_ST_TIME_OUT_I2C_SCL_ST_TO_I2C_Pos = 0x0 + // Bit mask of I2C_SCL_ST_TO_I2C field. + LP_I2C0_I2C_SCL_ST_TIME_OUT_I2C_SCL_ST_TO_I2C_Msk = 0x1f + + // I2C_SCL_MAIN_ST_TIME_OUT: SCL main status time out register + // Position of I2C_SCL_MAIN_ST_TO_I2C field. + LP_I2C0_I2C_SCL_MAIN_ST_TIME_OUT_I2C_SCL_MAIN_ST_TO_I2C_Pos = 0x0 + // Bit mask of I2C_SCL_MAIN_ST_TO_I2C field. + LP_I2C0_I2C_SCL_MAIN_ST_TIME_OUT_I2C_SCL_MAIN_ST_TO_I2C_Msk = 0x1f + + // I2C_SCL_SP_CONF: Power configuration register + // Position of I2C_SCL_RST_SLV_EN field. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SCL_RST_SLV_EN_Pos = 0x0 + // Bit mask of I2C_SCL_RST_SLV_EN field. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SCL_RST_SLV_EN_Msk = 0x1 + // Bit I2C_SCL_RST_SLV_EN. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SCL_RST_SLV_EN = 0x1 + // Position of I2C_SCL_RST_SLV_NUM field. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SCL_RST_SLV_NUM_Pos = 0x1 + // Bit mask of I2C_SCL_RST_SLV_NUM field. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SCL_RST_SLV_NUM_Msk = 0x3e + // Position of I2C_SCL_PD_EN field. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SCL_PD_EN_Pos = 0x6 + // Bit mask of I2C_SCL_PD_EN field. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SCL_PD_EN_Msk = 0x40 + // Bit I2C_SCL_PD_EN. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SCL_PD_EN = 0x40 + // Position of I2C_SDA_PD_EN field. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SDA_PD_EN_Pos = 0x7 + // Bit mask of I2C_SDA_PD_EN field. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SDA_PD_EN_Msk = 0x80 + // Bit I2C_SDA_PD_EN. + LP_I2C0_I2C_SCL_SP_CONF_I2C_SDA_PD_EN = 0x80 + + // I2C_DATE: Version register + // Position of I2C_DATE field. + LP_I2C0_I2C_DATE_I2C_DATE_Pos = 0x0 + // Bit mask of I2C_DATE field. + LP_I2C0_I2C_DATE_I2C_DATE_Msk = 0xffffffff + + // I2C_TXFIFO_START_ADDR: I2C TXFIFO base address register + // Position of I2C_TXFIFO_START_ADDR field. + LP_I2C0_I2C_TXFIFO_START_ADDR_I2C_TXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of I2C_TXFIFO_START_ADDR field. + LP_I2C0_I2C_TXFIFO_START_ADDR_I2C_TXFIFO_START_ADDR_Msk = 0xffffffff + + // I2C_RXFIFO_START_ADDR: I2C RXFIFO base address register + // Position of I2C_RXFIFO_START_ADDR field. + LP_I2C0_I2C_RXFIFO_START_ADDR_I2C_RXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of I2C_RXFIFO_START_ADDR field. + LP_I2C0_I2C_RXFIFO_START_ADDR_I2C_RXFIFO_START_ADDR_Msk = 0xffffffff +) + +// Constants for LP_I2C_ANA_MST: LP_I2C_ANA_MST Peripheral +const ( + // I2C0_CTRL: need_des + // Position of LP_I2C_ANA_MAST_I2C0_CTRL field. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_CTRL_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C0_CTRL field. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_CTRL_Msk = 0x1ffffff + // Position of LP_I2C_ANA_MAST_I2C0_BUSY field. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY_Pos = 0x19 + // Bit mask of LP_I2C_ANA_MAST_I2C0_BUSY field. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY_Msk = 0x2000000 + // Bit LP_I2C_ANA_MAST_I2C0_BUSY. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY = 0x2000000 + + // I2C0_CONF: need_des + // Position of LP_I2C_ANA_MAST_I2C0_CONF field. + LP_I2C_ANA_MST_I2C0_CONF_LP_I2C_ANA_MAST_I2C0_CONF_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C0_CONF field. + LP_I2C_ANA_MST_I2C0_CONF_LP_I2C_ANA_MAST_I2C0_CONF_Msk = 0xffffff + // Position of LP_I2C_ANA_MAST_I2C0_STATUS field. + LP_I2C_ANA_MST_I2C0_CONF_LP_I2C_ANA_MAST_I2C0_STATUS_Pos = 0x18 + // Bit mask of LP_I2C_ANA_MAST_I2C0_STATUS field. + LP_I2C_ANA_MST_I2C0_CONF_LP_I2C_ANA_MAST_I2C0_STATUS_Msk = 0xff000000 + + // I2C0_DATA: need_des + // Position of LP_I2C_ANA_MAST_I2C0_RDATA field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C0_RDATA_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C0_RDATA field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C0_RDATA_Msk = 0xff + // Position of LP_I2C_ANA_MAST_I2C0_CLK_SEL field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C0_CLK_SEL_Pos = 0x8 + // Bit mask of LP_I2C_ANA_MAST_I2C0_CLK_SEL field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C0_CLK_SEL_Msk = 0x700 + // Position of LP_I2C_ANA_MAST_I2C_MST_SEL field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL_Pos = 0xb + // Bit mask of LP_I2C_ANA_MAST_I2C_MST_SEL field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL_Msk = 0x800 + // Bit LP_I2C_ANA_MAST_I2C_MST_SEL. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL = 0x800 + + // ANA_CONF1: need_des + // Position of LP_I2C_ANA_MAST_ANA_CONF1 field. + LP_I2C_ANA_MST_ANA_CONF1_LP_I2C_ANA_MAST_ANA_CONF1_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_ANA_CONF1 field. + LP_I2C_ANA_MST_ANA_CONF1_LP_I2C_ANA_MAST_ANA_CONF1_Msk = 0xffffff + + // NOUSE: need_des + // Position of LP_I2C_ANA_MAST_I2C_MST_NOUSE field. + LP_I2C_ANA_MST_NOUSE_LP_I2C_ANA_MAST_I2C_MST_NOUSE_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C_MST_NOUSE field. + LP_I2C_ANA_MST_NOUSE_LP_I2C_ANA_MAST_I2C_MST_NOUSE_Msk = 0xffffffff + + // DEVICE_EN: need_des + // Position of LP_I2C_ANA_MAST_I2C_DEVICE_EN field. + LP_I2C_ANA_MST_DEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C_DEVICE_EN field. + LP_I2C_ANA_MST_DEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN_Msk = 0xfff + + // DATE: need_des + // Position of LP_I2C_ANA_MAST_I2C_MAT_DATE field. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_DATE_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C_MAT_DATE field. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_DATE_Msk = 0xfffffff + // Position of LP_I2C_ANA_MAST_I2C_MAT_CLK_EN field. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN_Pos = 0x1c + // Bit mask of LP_I2C_ANA_MAST_I2C_MAT_CLK_EN field. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN_Msk = 0x10000000 + // Bit LP_I2C_ANA_MAST_I2C_MAT_CLK_EN. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN = 0x10000000 +) + +// Constants for LP_IO: LP_IO Peripheral +const ( + // OUT_DATA: need des + // Position of LP_GPIO_OUT_DATA field. + LP_IO_OUT_DATA_LP_GPIO_OUT_DATA_Pos = 0x0 + // Bit mask of LP_GPIO_OUT_DATA field. + LP_IO_OUT_DATA_LP_GPIO_OUT_DATA_Msk = 0xff + + // OUT_DATA_W1TS: need des + // Position of LP_GPIO_OUT_DATA_W1TS field. + LP_IO_OUT_DATA_W1TS_LP_GPIO_OUT_DATA_W1TS_Pos = 0x0 + // Bit mask of LP_GPIO_OUT_DATA_W1TS field. + LP_IO_OUT_DATA_W1TS_LP_GPIO_OUT_DATA_W1TS_Msk = 0xff + + // OUT_DATA_W1TC: need des + // Position of LP_GPIO_OUT_DATA_W1TC field. + LP_IO_OUT_DATA_W1TC_LP_GPIO_OUT_DATA_W1TC_Pos = 0x0 + // Bit mask of LP_GPIO_OUT_DATA_W1TC field. + LP_IO_OUT_DATA_W1TC_LP_GPIO_OUT_DATA_W1TC_Msk = 0xff + + // OUT_ENABLE: need des + // Position of LP_GPIO_ENABLE field. + LP_IO_OUT_ENABLE_LP_GPIO_ENABLE_Pos = 0x0 + // Bit mask of LP_GPIO_ENABLE field. + LP_IO_OUT_ENABLE_LP_GPIO_ENABLE_Msk = 0xff + + // OUT_ENABLE_W1TS: need des + // Position of LP_GPIO_ENABLE_W1TS field. + LP_IO_OUT_ENABLE_W1TS_LP_GPIO_ENABLE_W1TS_Pos = 0x0 + // Bit mask of LP_GPIO_ENABLE_W1TS field. + LP_IO_OUT_ENABLE_W1TS_LP_GPIO_ENABLE_W1TS_Msk = 0xff + + // OUT_ENABLE_W1TC: need des + // Position of LP_GPIO_ENABLE_W1TC field. + LP_IO_OUT_ENABLE_W1TC_LP_GPIO_ENABLE_W1TC_Pos = 0x0 + // Bit mask of LP_GPIO_ENABLE_W1TC field. + LP_IO_OUT_ENABLE_W1TC_LP_GPIO_ENABLE_W1TC_Msk = 0xff + + // STATUS: need des + // Position of LP_GPIO_STATUS_INTERRUPT field. + LP_IO_STATUS_LP_GPIO_STATUS_INTERRUPT_Pos = 0x0 + // Bit mask of LP_GPIO_STATUS_INTERRUPT field. + LP_IO_STATUS_LP_GPIO_STATUS_INTERRUPT_Msk = 0xff + + // STATUS_W1TS: need des + // Position of LP_GPIO_STATUS_W1TS field. + LP_IO_STATUS_W1TS_LP_GPIO_STATUS_W1TS_Pos = 0x0 + // Bit mask of LP_GPIO_STATUS_W1TS field. + LP_IO_STATUS_W1TS_LP_GPIO_STATUS_W1TS_Msk = 0xff + + // STATUS_W1TC: need des + // Position of LP_GPIO_STATUS_W1TC field. + LP_IO_STATUS_W1TC_LP_GPIO_STATUS_W1TC_Pos = 0x0 + // Bit mask of LP_GPIO_STATUS_W1TC field. + LP_IO_STATUS_W1TC_LP_GPIO_STATUS_W1TC_Msk = 0xff + + // IN: need des + // Position of LP_GPIO_IN_DATA_NEXT field. + LP_IO_IN_LP_GPIO_IN_DATA_NEXT_Pos = 0x0 + // Bit mask of LP_GPIO_IN_DATA_NEXT field. + LP_IO_IN_LP_GPIO_IN_DATA_NEXT_Msk = 0xff + + // PIN0: need des + // Position of LP_GPIO0_SYNC_BYPASS field. + LP_IO_PIN0_LP_GPIO0_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO0_SYNC_BYPASS field. + LP_IO_PIN0_LP_GPIO0_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO0_PAD_DRIVER field. + LP_IO_PIN0_LP_GPIO0_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO0_PAD_DRIVER field. + LP_IO_PIN0_LP_GPIO0_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO0_PAD_DRIVER. + LP_IO_PIN0_LP_GPIO0_PAD_DRIVER = 0x4 + // Position of LP_GPIO0_EDGE_WAKEUP_CLR field. + LP_IO_PIN0_LP_GPIO0_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO0_EDGE_WAKEUP_CLR field. + LP_IO_PIN0_LP_GPIO0_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO0_EDGE_WAKEUP_CLR. + LP_IO_PIN0_LP_GPIO0_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO0_INT_TYPE field. + LP_IO_PIN0_LP_GPIO0_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO0_INT_TYPE field. + LP_IO_PIN0_LP_GPIO0_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO0_WAKEUP_ENABLE field. + LP_IO_PIN0_LP_GPIO0_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO0_WAKEUP_ENABLE field. + LP_IO_PIN0_LP_GPIO0_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO0_WAKEUP_ENABLE. + LP_IO_PIN0_LP_GPIO0_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO0_FILTER_EN field. + LP_IO_PIN0_LP_GPIO0_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO0_FILTER_EN field. + LP_IO_PIN0_LP_GPIO0_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO0_FILTER_EN. + LP_IO_PIN0_LP_GPIO0_FILTER_EN = 0x800 + + // PIN1: need des + // Position of LP_GPIO1_SYNC_BYPASS field. + LP_IO_PIN1_LP_GPIO1_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO1_SYNC_BYPASS field. + LP_IO_PIN1_LP_GPIO1_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO1_PAD_DRIVER field. + LP_IO_PIN1_LP_GPIO1_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO1_PAD_DRIVER field. + LP_IO_PIN1_LP_GPIO1_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO1_PAD_DRIVER. + LP_IO_PIN1_LP_GPIO1_PAD_DRIVER = 0x4 + // Position of LP_GPIO1_EDGE_WAKEUP_CLR field. + LP_IO_PIN1_LP_GPIO1_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO1_EDGE_WAKEUP_CLR field. + LP_IO_PIN1_LP_GPIO1_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO1_EDGE_WAKEUP_CLR. + LP_IO_PIN1_LP_GPIO1_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO1_INT_TYPE field. + LP_IO_PIN1_LP_GPIO1_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO1_INT_TYPE field. + LP_IO_PIN1_LP_GPIO1_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO1_WAKEUP_ENABLE field. + LP_IO_PIN1_LP_GPIO1_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO1_WAKEUP_ENABLE field. + LP_IO_PIN1_LP_GPIO1_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO1_WAKEUP_ENABLE. + LP_IO_PIN1_LP_GPIO1_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO1_FILTER_EN field. + LP_IO_PIN1_LP_GPIO1_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO1_FILTER_EN field. + LP_IO_PIN1_LP_GPIO1_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO1_FILTER_EN. + LP_IO_PIN1_LP_GPIO1_FILTER_EN = 0x800 + + // PIN2: need des + // Position of LP_GPIO2_SYNC_BYPASS field. + LP_IO_PIN2_LP_GPIO2_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO2_SYNC_BYPASS field. + LP_IO_PIN2_LP_GPIO2_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO2_PAD_DRIVER field. + LP_IO_PIN2_LP_GPIO2_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO2_PAD_DRIVER field. + LP_IO_PIN2_LP_GPIO2_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO2_PAD_DRIVER. + LP_IO_PIN2_LP_GPIO2_PAD_DRIVER = 0x4 + // Position of LP_GPIO2_EDGE_WAKEUP_CLR field. + LP_IO_PIN2_LP_GPIO2_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO2_EDGE_WAKEUP_CLR field. + LP_IO_PIN2_LP_GPIO2_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO2_EDGE_WAKEUP_CLR. + LP_IO_PIN2_LP_GPIO2_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO2_INT_TYPE field. + LP_IO_PIN2_LP_GPIO2_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO2_INT_TYPE field. + LP_IO_PIN2_LP_GPIO2_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO2_WAKEUP_ENABLE field. + LP_IO_PIN2_LP_GPIO2_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO2_WAKEUP_ENABLE field. + LP_IO_PIN2_LP_GPIO2_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO2_WAKEUP_ENABLE. + LP_IO_PIN2_LP_GPIO2_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO2_FILTER_EN field. + LP_IO_PIN2_LP_GPIO2_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO2_FILTER_EN field. + LP_IO_PIN2_LP_GPIO2_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO2_FILTER_EN. + LP_IO_PIN2_LP_GPIO2_FILTER_EN = 0x800 + + // PIN3: need des + // Position of LP_GPIO3_SYNC_BYPASS field. + LP_IO_PIN3_LP_GPIO3_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO3_SYNC_BYPASS field. + LP_IO_PIN3_LP_GPIO3_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO3_PAD_DRIVER field. + LP_IO_PIN3_LP_GPIO3_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO3_PAD_DRIVER field. + LP_IO_PIN3_LP_GPIO3_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO3_PAD_DRIVER. + LP_IO_PIN3_LP_GPIO3_PAD_DRIVER = 0x4 + // Position of LP_GPIO3_EDGE_WAKEUP_CLR field. + LP_IO_PIN3_LP_GPIO3_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO3_EDGE_WAKEUP_CLR field. + LP_IO_PIN3_LP_GPIO3_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO3_EDGE_WAKEUP_CLR. + LP_IO_PIN3_LP_GPIO3_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO3_INT_TYPE field. + LP_IO_PIN3_LP_GPIO3_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO3_INT_TYPE field. + LP_IO_PIN3_LP_GPIO3_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO3_WAKEUP_ENABLE field. + LP_IO_PIN3_LP_GPIO3_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO3_WAKEUP_ENABLE field. + LP_IO_PIN3_LP_GPIO3_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO3_WAKEUP_ENABLE. + LP_IO_PIN3_LP_GPIO3_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO3_FILTER_EN field. + LP_IO_PIN3_LP_GPIO3_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO3_FILTER_EN field. + LP_IO_PIN3_LP_GPIO3_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO3_FILTER_EN. + LP_IO_PIN3_LP_GPIO3_FILTER_EN = 0x800 + + // PIN4: need des + // Position of LP_GPIO4_SYNC_BYPASS field. + LP_IO_PIN4_LP_GPIO4_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO4_SYNC_BYPASS field. + LP_IO_PIN4_LP_GPIO4_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO4_PAD_DRIVER field. + LP_IO_PIN4_LP_GPIO4_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO4_PAD_DRIVER field. + LP_IO_PIN4_LP_GPIO4_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO4_PAD_DRIVER. + LP_IO_PIN4_LP_GPIO4_PAD_DRIVER = 0x4 + // Position of LP_GPIO4_EDGE_WAKEUP_CLR field. + LP_IO_PIN4_LP_GPIO4_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO4_EDGE_WAKEUP_CLR field. + LP_IO_PIN4_LP_GPIO4_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO4_EDGE_WAKEUP_CLR. + LP_IO_PIN4_LP_GPIO4_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO4_INT_TYPE field. + LP_IO_PIN4_LP_GPIO4_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO4_INT_TYPE field. + LP_IO_PIN4_LP_GPIO4_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO4_WAKEUP_ENABLE field. + LP_IO_PIN4_LP_GPIO4_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO4_WAKEUP_ENABLE field. + LP_IO_PIN4_LP_GPIO4_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO4_WAKEUP_ENABLE. + LP_IO_PIN4_LP_GPIO4_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO4_FILTER_EN field. + LP_IO_PIN4_LP_GPIO4_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO4_FILTER_EN field. + LP_IO_PIN4_LP_GPIO4_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO4_FILTER_EN. + LP_IO_PIN4_LP_GPIO4_FILTER_EN = 0x800 + + // PIN5: need des + // Position of LP_GPIO5_SYNC_BYPASS field. + LP_IO_PIN5_LP_GPIO5_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO5_SYNC_BYPASS field. + LP_IO_PIN5_LP_GPIO5_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO5_PAD_DRIVER field. + LP_IO_PIN5_LP_GPIO5_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO5_PAD_DRIVER field. + LP_IO_PIN5_LP_GPIO5_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO5_PAD_DRIVER. + LP_IO_PIN5_LP_GPIO5_PAD_DRIVER = 0x4 + // Position of LP_GPIO5_EDGE_WAKEUP_CLR field. + LP_IO_PIN5_LP_GPIO5_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO5_EDGE_WAKEUP_CLR field. + LP_IO_PIN5_LP_GPIO5_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO5_EDGE_WAKEUP_CLR. + LP_IO_PIN5_LP_GPIO5_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO5_INT_TYPE field. + LP_IO_PIN5_LP_GPIO5_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO5_INT_TYPE field. + LP_IO_PIN5_LP_GPIO5_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO5_WAKEUP_ENABLE field. + LP_IO_PIN5_LP_GPIO5_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO5_WAKEUP_ENABLE field. + LP_IO_PIN5_LP_GPIO5_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO5_WAKEUP_ENABLE. + LP_IO_PIN5_LP_GPIO5_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO5_FILTER_EN field. + LP_IO_PIN5_LP_GPIO5_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO5_FILTER_EN field. + LP_IO_PIN5_LP_GPIO5_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO5_FILTER_EN. + LP_IO_PIN5_LP_GPIO5_FILTER_EN = 0x800 + + // PIN6: need des + // Position of LP_GPIO6_SYNC_BYPASS field. + LP_IO_PIN6_LP_GPIO6_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO6_SYNC_BYPASS field. + LP_IO_PIN6_LP_GPIO6_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO6_PAD_DRIVER field. + LP_IO_PIN6_LP_GPIO6_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO6_PAD_DRIVER field. + LP_IO_PIN6_LP_GPIO6_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO6_PAD_DRIVER. + LP_IO_PIN6_LP_GPIO6_PAD_DRIVER = 0x4 + // Position of LP_GPIO6_EDGE_WAKEUP_CLR field. + LP_IO_PIN6_LP_GPIO6_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO6_EDGE_WAKEUP_CLR field. + LP_IO_PIN6_LP_GPIO6_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO6_EDGE_WAKEUP_CLR. + LP_IO_PIN6_LP_GPIO6_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO6_INT_TYPE field. + LP_IO_PIN6_LP_GPIO6_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO6_INT_TYPE field. + LP_IO_PIN6_LP_GPIO6_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO6_WAKEUP_ENABLE field. + LP_IO_PIN6_LP_GPIO6_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO6_WAKEUP_ENABLE field. + LP_IO_PIN6_LP_GPIO6_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO6_WAKEUP_ENABLE. + LP_IO_PIN6_LP_GPIO6_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO6_FILTER_EN field. + LP_IO_PIN6_LP_GPIO6_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO6_FILTER_EN field. + LP_IO_PIN6_LP_GPIO6_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO6_FILTER_EN. + LP_IO_PIN6_LP_GPIO6_FILTER_EN = 0x800 + + // PIN7: need des + // Position of LP_GPIO7_SYNC_BYPASS field. + LP_IO_PIN7_LP_GPIO7_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO7_SYNC_BYPASS field. + LP_IO_PIN7_LP_GPIO7_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO7_PAD_DRIVER field. + LP_IO_PIN7_LP_GPIO7_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO7_PAD_DRIVER field. + LP_IO_PIN7_LP_GPIO7_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO7_PAD_DRIVER. + LP_IO_PIN7_LP_GPIO7_PAD_DRIVER = 0x4 + // Position of LP_GPIO7_EDGE_WAKEUP_CLR field. + LP_IO_PIN7_LP_GPIO7_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO7_EDGE_WAKEUP_CLR field. + LP_IO_PIN7_LP_GPIO7_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO7_EDGE_WAKEUP_CLR. + LP_IO_PIN7_LP_GPIO7_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO7_INT_TYPE field. + LP_IO_PIN7_LP_GPIO7_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO7_INT_TYPE field. + LP_IO_PIN7_LP_GPIO7_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO7_WAKEUP_ENABLE field. + LP_IO_PIN7_LP_GPIO7_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO7_WAKEUP_ENABLE field. + LP_IO_PIN7_LP_GPIO7_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO7_WAKEUP_ENABLE. + LP_IO_PIN7_LP_GPIO7_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO7_FILTER_EN field. + LP_IO_PIN7_LP_GPIO7_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO7_FILTER_EN field. + LP_IO_PIN7_LP_GPIO7_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO7_FILTER_EN. + LP_IO_PIN7_LP_GPIO7_FILTER_EN = 0x800 + + // GPIO0: need des + // Position of LP_GPIO0_MCU_OE field. + LP_IO_GPIO0_LP_GPIO0_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO0_MCU_OE field. + LP_IO_GPIO0_LP_GPIO0_MCU_OE_Msk = 0x1 + // Bit LP_GPIO0_MCU_OE. + LP_IO_GPIO0_LP_GPIO0_MCU_OE = 0x1 + // Position of LP_GPIO0_SLP_SEL field. + LP_IO_GPIO0_LP_GPIO0_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO0_SLP_SEL field. + LP_IO_GPIO0_LP_GPIO0_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO0_SLP_SEL. + LP_IO_GPIO0_LP_GPIO0_SLP_SEL = 0x2 + // Position of LP_GPIO0_MCU_WPD field. + LP_IO_GPIO0_LP_GPIO0_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO0_MCU_WPD field. + LP_IO_GPIO0_LP_GPIO0_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO0_MCU_WPD. + LP_IO_GPIO0_LP_GPIO0_MCU_WPD = 0x4 + // Position of LP_GPIO0_MCU_WPU field. + LP_IO_GPIO0_LP_GPIO0_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO0_MCU_WPU field. + LP_IO_GPIO0_LP_GPIO0_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO0_MCU_WPU. + LP_IO_GPIO0_LP_GPIO0_MCU_WPU = 0x8 + // Position of LP_GPIO0_MCU_IE field. + LP_IO_GPIO0_LP_GPIO0_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO0_MCU_IE field. + LP_IO_GPIO0_LP_GPIO0_MCU_IE_Msk = 0x10 + // Bit LP_GPIO0_MCU_IE. + LP_IO_GPIO0_LP_GPIO0_MCU_IE = 0x10 + // Position of LP_GPIO0_MCU_DRV field. + LP_IO_GPIO0_LP_GPIO0_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO0_MCU_DRV field. + LP_IO_GPIO0_LP_GPIO0_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO0_FUN_WPD field. + LP_IO_GPIO0_LP_GPIO0_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO0_FUN_WPD field. + LP_IO_GPIO0_LP_GPIO0_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO0_FUN_WPD. + LP_IO_GPIO0_LP_GPIO0_FUN_WPD = 0x80 + // Position of LP_GPIO0_FUN_WPU field. + LP_IO_GPIO0_LP_GPIO0_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO0_FUN_WPU field. + LP_IO_GPIO0_LP_GPIO0_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO0_FUN_WPU. + LP_IO_GPIO0_LP_GPIO0_FUN_WPU = 0x100 + // Position of LP_GPIO0_FUN_IE field. + LP_IO_GPIO0_LP_GPIO0_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO0_FUN_IE field. + LP_IO_GPIO0_LP_GPIO0_FUN_IE_Msk = 0x200 + // Bit LP_GPIO0_FUN_IE. + LP_IO_GPIO0_LP_GPIO0_FUN_IE = 0x200 + // Position of LP_GPIO0_FUN_DRV field. + LP_IO_GPIO0_LP_GPIO0_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO0_FUN_DRV field. + LP_IO_GPIO0_LP_GPIO0_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO0_MCU_SEL field. + LP_IO_GPIO0_LP_GPIO0_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO0_MCU_SEL field. + LP_IO_GPIO0_LP_GPIO0_MCU_SEL_Msk = 0x7000 + + // GPIO1: need des + // Position of LP_GPIO1_MCU_OE field. + LP_IO_GPIO1_LP_GPIO1_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO1_MCU_OE field. + LP_IO_GPIO1_LP_GPIO1_MCU_OE_Msk = 0x1 + // Bit LP_GPIO1_MCU_OE. + LP_IO_GPIO1_LP_GPIO1_MCU_OE = 0x1 + // Position of LP_GPIO1_SLP_SEL field. + LP_IO_GPIO1_LP_GPIO1_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO1_SLP_SEL field. + LP_IO_GPIO1_LP_GPIO1_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO1_SLP_SEL. + LP_IO_GPIO1_LP_GPIO1_SLP_SEL = 0x2 + // Position of LP_GPIO1_MCU_WPD field. + LP_IO_GPIO1_LP_GPIO1_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO1_MCU_WPD field. + LP_IO_GPIO1_LP_GPIO1_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO1_MCU_WPD. + LP_IO_GPIO1_LP_GPIO1_MCU_WPD = 0x4 + // Position of LP_GPIO1_MCU_WPU field. + LP_IO_GPIO1_LP_GPIO1_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO1_MCU_WPU field. + LP_IO_GPIO1_LP_GPIO1_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO1_MCU_WPU. + LP_IO_GPIO1_LP_GPIO1_MCU_WPU = 0x8 + // Position of LP_GPIO1_MCU_IE field. + LP_IO_GPIO1_LP_GPIO1_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO1_MCU_IE field. + LP_IO_GPIO1_LP_GPIO1_MCU_IE_Msk = 0x10 + // Bit LP_GPIO1_MCU_IE. + LP_IO_GPIO1_LP_GPIO1_MCU_IE = 0x10 + // Position of LP_GPIO1_MCU_DRV field. + LP_IO_GPIO1_LP_GPIO1_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO1_MCU_DRV field. + LP_IO_GPIO1_LP_GPIO1_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO1_FUN_WPD field. + LP_IO_GPIO1_LP_GPIO1_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO1_FUN_WPD field. + LP_IO_GPIO1_LP_GPIO1_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO1_FUN_WPD. + LP_IO_GPIO1_LP_GPIO1_FUN_WPD = 0x80 + // Position of LP_GPIO1_FUN_WPU field. + LP_IO_GPIO1_LP_GPIO1_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO1_FUN_WPU field. + LP_IO_GPIO1_LP_GPIO1_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO1_FUN_WPU. + LP_IO_GPIO1_LP_GPIO1_FUN_WPU = 0x100 + // Position of LP_GPIO1_FUN_IE field. + LP_IO_GPIO1_LP_GPIO1_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO1_FUN_IE field. + LP_IO_GPIO1_LP_GPIO1_FUN_IE_Msk = 0x200 + // Bit LP_GPIO1_FUN_IE. + LP_IO_GPIO1_LP_GPIO1_FUN_IE = 0x200 + // Position of LP_GPIO1_FUN_DRV field. + LP_IO_GPIO1_LP_GPIO1_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO1_FUN_DRV field. + LP_IO_GPIO1_LP_GPIO1_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO1_MCU_SEL field. + LP_IO_GPIO1_LP_GPIO1_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO1_MCU_SEL field. + LP_IO_GPIO1_LP_GPIO1_MCU_SEL_Msk = 0x7000 + + // GPIO2: need des + // Position of LP_GPIO2_MCU_OE field. + LP_IO_GPIO2_LP_GPIO2_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO2_MCU_OE field. + LP_IO_GPIO2_LP_GPIO2_MCU_OE_Msk = 0x1 + // Bit LP_GPIO2_MCU_OE. + LP_IO_GPIO2_LP_GPIO2_MCU_OE = 0x1 + // Position of LP_GPIO2_SLP_SEL field. + LP_IO_GPIO2_LP_GPIO2_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO2_SLP_SEL field. + LP_IO_GPIO2_LP_GPIO2_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO2_SLP_SEL. + LP_IO_GPIO2_LP_GPIO2_SLP_SEL = 0x2 + // Position of LP_GPIO2_MCU_WPD field. + LP_IO_GPIO2_LP_GPIO2_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO2_MCU_WPD field. + LP_IO_GPIO2_LP_GPIO2_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO2_MCU_WPD. + LP_IO_GPIO2_LP_GPIO2_MCU_WPD = 0x4 + // Position of LP_GPIO2_MCU_WPU field. + LP_IO_GPIO2_LP_GPIO2_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO2_MCU_WPU field. + LP_IO_GPIO2_LP_GPIO2_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO2_MCU_WPU. + LP_IO_GPIO2_LP_GPIO2_MCU_WPU = 0x8 + // Position of LP_GPIO2_MCU_IE field. + LP_IO_GPIO2_LP_GPIO2_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO2_MCU_IE field. + LP_IO_GPIO2_LP_GPIO2_MCU_IE_Msk = 0x10 + // Bit LP_GPIO2_MCU_IE. + LP_IO_GPIO2_LP_GPIO2_MCU_IE = 0x10 + // Position of LP_GPIO2_MCU_DRV field. + LP_IO_GPIO2_LP_GPIO2_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO2_MCU_DRV field. + LP_IO_GPIO2_LP_GPIO2_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO2_FUN_WPD field. + LP_IO_GPIO2_LP_GPIO2_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO2_FUN_WPD field. + LP_IO_GPIO2_LP_GPIO2_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO2_FUN_WPD. + LP_IO_GPIO2_LP_GPIO2_FUN_WPD = 0x80 + // Position of LP_GPIO2_FUN_WPU field. + LP_IO_GPIO2_LP_GPIO2_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO2_FUN_WPU field. + LP_IO_GPIO2_LP_GPIO2_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO2_FUN_WPU. + LP_IO_GPIO2_LP_GPIO2_FUN_WPU = 0x100 + // Position of LP_GPIO2_FUN_IE field. + LP_IO_GPIO2_LP_GPIO2_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO2_FUN_IE field. + LP_IO_GPIO2_LP_GPIO2_FUN_IE_Msk = 0x200 + // Bit LP_GPIO2_FUN_IE. + LP_IO_GPIO2_LP_GPIO2_FUN_IE = 0x200 + // Position of LP_GPIO2_FUN_DRV field. + LP_IO_GPIO2_LP_GPIO2_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO2_FUN_DRV field. + LP_IO_GPIO2_LP_GPIO2_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO2_MCU_SEL field. + LP_IO_GPIO2_LP_GPIO2_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO2_MCU_SEL field. + LP_IO_GPIO2_LP_GPIO2_MCU_SEL_Msk = 0x7000 + + // GPIO3: need des + // Position of LP_GPIO3_MCU_OE field. + LP_IO_GPIO3_LP_GPIO3_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO3_MCU_OE field. + LP_IO_GPIO3_LP_GPIO3_MCU_OE_Msk = 0x1 + // Bit LP_GPIO3_MCU_OE. + LP_IO_GPIO3_LP_GPIO3_MCU_OE = 0x1 + // Position of LP_GPIO3_SLP_SEL field. + LP_IO_GPIO3_LP_GPIO3_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO3_SLP_SEL field. + LP_IO_GPIO3_LP_GPIO3_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO3_SLP_SEL. + LP_IO_GPIO3_LP_GPIO3_SLP_SEL = 0x2 + // Position of LP_GPIO3_MCU_WPD field. + LP_IO_GPIO3_LP_GPIO3_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO3_MCU_WPD field. + LP_IO_GPIO3_LP_GPIO3_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO3_MCU_WPD. + LP_IO_GPIO3_LP_GPIO3_MCU_WPD = 0x4 + // Position of LP_GPIO3_MCU_WPU field. + LP_IO_GPIO3_LP_GPIO3_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO3_MCU_WPU field. + LP_IO_GPIO3_LP_GPIO3_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO3_MCU_WPU. + LP_IO_GPIO3_LP_GPIO3_MCU_WPU = 0x8 + // Position of LP_GPIO3_MCU_IE field. + LP_IO_GPIO3_LP_GPIO3_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO3_MCU_IE field. + LP_IO_GPIO3_LP_GPIO3_MCU_IE_Msk = 0x10 + // Bit LP_GPIO3_MCU_IE. + LP_IO_GPIO3_LP_GPIO3_MCU_IE = 0x10 + // Position of LP_GPIO3_MCU_DRV field. + LP_IO_GPIO3_LP_GPIO3_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO3_MCU_DRV field. + LP_IO_GPIO3_LP_GPIO3_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO3_FUN_WPD field. + LP_IO_GPIO3_LP_GPIO3_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO3_FUN_WPD field. + LP_IO_GPIO3_LP_GPIO3_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO3_FUN_WPD. + LP_IO_GPIO3_LP_GPIO3_FUN_WPD = 0x80 + // Position of LP_GPIO3_FUN_WPU field. + LP_IO_GPIO3_LP_GPIO3_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO3_FUN_WPU field. + LP_IO_GPIO3_LP_GPIO3_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO3_FUN_WPU. + LP_IO_GPIO3_LP_GPIO3_FUN_WPU = 0x100 + // Position of LP_GPIO3_FUN_IE field. + LP_IO_GPIO3_LP_GPIO3_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO3_FUN_IE field. + LP_IO_GPIO3_LP_GPIO3_FUN_IE_Msk = 0x200 + // Bit LP_GPIO3_FUN_IE. + LP_IO_GPIO3_LP_GPIO3_FUN_IE = 0x200 + // Position of LP_GPIO3_FUN_DRV field. + LP_IO_GPIO3_LP_GPIO3_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO3_FUN_DRV field. + LP_IO_GPIO3_LP_GPIO3_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO3_MCU_SEL field. + LP_IO_GPIO3_LP_GPIO3_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO3_MCU_SEL field. + LP_IO_GPIO3_LP_GPIO3_MCU_SEL_Msk = 0x7000 + + // GPIO4: need des + // Position of LP_GPIO4_MCU_OE field. + LP_IO_GPIO4_LP_GPIO4_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO4_MCU_OE field. + LP_IO_GPIO4_LP_GPIO4_MCU_OE_Msk = 0x1 + // Bit LP_GPIO4_MCU_OE. + LP_IO_GPIO4_LP_GPIO4_MCU_OE = 0x1 + // Position of LP_GPIO4_SLP_SEL field. + LP_IO_GPIO4_LP_GPIO4_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO4_SLP_SEL field. + LP_IO_GPIO4_LP_GPIO4_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO4_SLP_SEL. + LP_IO_GPIO4_LP_GPIO4_SLP_SEL = 0x2 + // Position of LP_GPIO4_MCU_WPD field. + LP_IO_GPIO4_LP_GPIO4_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO4_MCU_WPD field. + LP_IO_GPIO4_LP_GPIO4_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO4_MCU_WPD. + LP_IO_GPIO4_LP_GPIO4_MCU_WPD = 0x4 + // Position of LP_GPIO4_MCU_WPU field. + LP_IO_GPIO4_LP_GPIO4_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO4_MCU_WPU field. + LP_IO_GPIO4_LP_GPIO4_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO4_MCU_WPU. + LP_IO_GPIO4_LP_GPIO4_MCU_WPU = 0x8 + // Position of LP_GPIO4_MCU_IE field. + LP_IO_GPIO4_LP_GPIO4_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO4_MCU_IE field. + LP_IO_GPIO4_LP_GPIO4_MCU_IE_Msk = 0x10 + // Bit LP_GPIO4_MCU_IE. + LP_IO_GPIO4_LP_GPIO4_MCU_IE = 0x10 + // Position of LP_GPIO4_MCU_DRV field. + LP_IO_GPIO4_LP_GPIO4_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO4_MCU_DRV field. + LP_IO_GPIO4_LP_GPIO4_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO4_FUN_WPD field. + LP_IO_GPIO4_LP_GPIO4_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO4_FUN_WPD field. + LP_IO_GPIO4_LP_GPIO4_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO4_FUN_WPD. + LP_IO_GPIO4_LP_GPIO4_FUN_WPD = 0x80 + // Position of LP_GPIO4_FUN_WPU field. + LP_IO_GPIO4_LP_GPIO4_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO4_FUN_WPU field. + LP_IO_GPIO4_LP_GPIO4_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO4_FUN_WPU. + LP_IO_GPIO4_LP_GPIO4_FUN_WPU = 0x100 + // Position of LP_GPIO4_FUN_IE field. + LP_IO_GPIO4_LP_GPIO4_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO4_FUN_IE field. + LP_IO_GPIO4_LP_GPIO4_FUN_IE_Msk = 0x200 + // Bit LP_GPIO4_FUN_IE. + LP_IO_GPIO4_LP_GPIO4_FUN_IE = 0x200 + // Position of LP_GPIO4_FUN_DRV field. + LP_IO_GPIO4_LP_GPIO4_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO4_FUN_DRV field. + LP_IO_GPIO4_LP_GPIO4_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO4_MCU_SEL field. + LP_IO_GPIO4_LP_GPIO4_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO4_MCU_SEL field. + LP_IO_GPIO4_LP_GPIO4_MCU_SEL_Msk = 0x7000 + + // GPIO5: need des + // Position of LP_GPIO5_MCU_OE field. + LP_IO_GPIO5_LP_GPIO5_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO5_MCU_OE field. + LP_IO_GPIO5_LP_GPIO5_MCU_OE_Msk = 0x1 + // Bit LP_GPIO5_MCU_OE. + LP_IO_GPIO5_LP_GPIO5_MCU_OE = 0x1 + // Position of LP_GPIO5_SLP_SEL field. + LP_IO_GPIO5_LP_GPIO5_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO5_SLP_SEL field. + LP_IO_GPIO5_LP_GPIO5_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO5_SLP_SEL. + LP_IO_GPIO5_LP_GPIO5_SLP_SEL = 0x2 + // Position of LP_GPIO5_MCU_WPD field. + LP_IO_GPIO5_LP_GPIO5_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO5_MCU_WPD field. + LP_IO_GPIO5_LP_GPIO5_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO5_MCU_WPD. + LP_IO_GPIO5_LP_GPIO5_MCU_WPD = 0x4 + // Position of LP_GPIO5_MCU_WPU field. + LP_IO_GPIO5_LP_GPIO5_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO5_MCU_WPU field. + LP_IO_GPIO5_LP_GPIO5_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO5_MCU_WPU. + LP_IO_GPIO5_LP_GPIO5_MCU_WPU = 0x8 + // Position of LP_GPIO5_MCU_IE field. + LP_IO_GPIO5_LP_GPIO5_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO5_MCU_IE field. + LP_IO_GPIO5_LP_GPIO5_MCU_IE_Msk = 0x10 + // Bit LP_GPIO5_MCU_IE. + LP_IO_GPIO5_LP_GPIO5_MCU_IE = 0x10 + // Position of LP_GPIO5_MCU_DRV field. + LP_IO_GPIO5_LP_GPIO5_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO5_MCU_DRV field. + LP_IO_GPIO5_LP_GPIO5_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO5_FUN_WPD field. + LP_IO_GPIO5_LP_GPIO5_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO5_FUN_WPD field. + LP_IO_GPIO5_LP_GPIO5_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO5_FUN_WPD. + LP_IO_GPIO5_LP_GPIO5_FUN_WPD = 0x80 + // Position of LP_GPIO5_FUN_WPU field. + LP_IO_GPIO5_LP_GPIO5_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO5_FUN_WPU field. + LP_IO_GPIO5_LP_GPIO5_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO5_FUN_WPU. + LP_IO_GPIO5_LP_GPIO5_FUN_WPU = 0x100 + // Position of LP_GPIO5_FUN_IE field. + LP_IO_GPIO5_LP_GPIO5_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO5_FUN_IE field. + LP_IO_GPIO5_LP_GPIO5_FUN_IE_Msk = 0x200 + // Bit LP_GPIO5_FUN_IE. + LP_IO_GPIO5_LP_GPIO5_FUN_IE = 0x200 + // Position of LP_GPIO5_FUN_DRV field. + LP_IO_GPIO5_LP_GPIO5_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO5_FUN_DRV field. + LP_IO_GPIO5_LP_GPIO5_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO5_MCU_SEL field. + LP_IO_GPIO5_LP_GPIO5_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO5_MCU_SEL field. + LP_IO_GPIO5_LP_GPIO5_MCU_SEL_Msk = 0x7000 + + // GPIO6: need des + // Position of LP_GPIO6_MCU_OE field. + LP_IO_GPIO6_LP_GPIO6_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO6_MCU_OE field. + LP_IO_GPIO6_LP_GPIO6_MCU_OE_Msk = 0x1 + // Bit LP_GPIO6_MCU_OE. + LP_IO_GPIO6_LP_GPIO6_MCU_OE = 0x1 + // Position of LP_GPIO6_SLP_SEL field. + LP_IO_GPIO6_LP_GPIO6_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO6_SLP_SEL field. + LP_IO_GPIO6_LP_GPIO6_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO6_SLP_SEL. + LP_IO_GPIO6_LP_GPIO6_SLP_SEL = 0x2 + // Position of LP_GPIO6_MCU_WPD field. + LP_IO_GPIO6_LP_GPIO6_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO6_MCU_WPD field. + LP_IO_GPIO6_LP_GPIO6_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO6_MCU_WPD. + LP_IO_GPIO6_LP_GPIO6_MCU_WPD = 0x4 + // Position of LP_GPIO6_MCU_WPU field. + LP_IO_GPIO6_LP_GPIO6_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO6_MCU_WPU field. + LP_IO_GPIO6_LP_GPIO6_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO6_MCU_WPU. + LP_IO_GPIO6_LP_GPIO6_MCU_WPU = 0x8 + // Position of LP_GPIO6_MCU_IE field. + LP_IO_GPIO6_LP_GPIO6_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO6_MCU_IE field. + LP_IO_GPIO6_LP_GPIO6_MCU_IE_Msk = 0x10 + // Bit LP_GPIO6_MCU_IE. + LP_IO_GPIO6_LP_GPIO6_MCU_IE = 0x10 + // Position of LP_GPIO6_MCU_DRV field. + LP_IO_GPIO6_LP_GPIO6_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO6_MCU_DRV field. + LP_IO_GPIO6_LP_GPIO6_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO6_FUN_WPD field. + LP_IO_GPIO6_LP_GPIO6_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO6_FUN_WPD field. + LP_IO_GPIO6_LP_GPIO6_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO6_FUN_WPD. + LP_IO_GPIO6_LP_GPIO6_FUN_WPD = 0x80 + // Position of LP_GPIO6_FUN_WPU field. + LP_IO_GPIO6_LP_GPIO6_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO6_FUN_WPU field. + LP_IO_GPIO6_LP_GPIO6_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO6_FUN_WPU. + LP_IO_GPIO6_LP_GPIO6_FUN_WPU = 0x100 + // Position of LP_GPIO6_FUN_IE field. + LP_IO_GPIO6_LP_GPIO6_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO6_FUN_IE field. + LP_IO_GPIO6_LP_GPIO6_FUN_IE_Msk = 0x200 + // Bit LP_GPIO6_FUN_IE. + LP_IO_GPIO6_LP_GPIO6_FUN_IE = 0x200 + // Position of LP_GPIO6_FUN_DRV field. + LP_IO_GPIO6_LP_GPIO6_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO6_FUN_DRV field. + LP_IO_GPIO6_LP_GPIO6_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO6_MCU_SEL field. + LP_IO_GPIO6_LP_GPIO6_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO6_MCU_SEL field. + LP_IO_GPIO6_LP_GPIO6_MCU_SEL_Msk = 0x7000 + + // GPIO7: need des + // Position of LP_GPIO7_MCU_OE field. + LP_IO_GPIO7_LP_GPIO7_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO7_MCU_OE field. + LP_IO_GPIO7_LP_GPIO7_MCU_OE_Msk = 0x1 + // Bit LP_GPIO7_MCU_OE. + LP_IO_GPIO7_LP_GPIO7_MCU_OE = 0x1 + // Position of LP_GPIO7_SLP_SEL field. + LP_IO_GPIO7_LP_GPIO7_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO7_SLP_SEL field. + LP_IO_GPIO7_LP_GPIO7_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO7_SLP_SEL. + LP_IO_GPIO7_LP_GPIO7_SLP_SEL = 0x2 + // Position of LP_GPIO7_MCU_WPD field. + LP_IO_GPIO7_LP_GPIO7_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO7_MCU_WPD field. + LP_IO_GPIO7_LP_GPIO7_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO7_MCU_WPD. + LP_IO_GPIO7_LP_GPIO7_MCU_WPD = 0x4 + // Position of LP_GPIO7_MCU_WPU field. + LP_IO_GPIO7_LP_GPIO7_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO7_MCU_WPU field. + LP_IO_GPIO7_LP_GPIO7_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO7_MCU_WPU. + LP_IO_GPIO7_LP_GPIO7_MCU_WPU = 0x8 + // Position of LP_GPIO7_MCU_IE field. + LP_IO_GPIO7_LP_GPIO7_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO7_MCU_IE field. + LP_IO_GPIO7_LP_GPIO7_MCU_IE_Msk = 0x10 + // Bit LP_GPIO7_MCU_IE. + LP_IO_GPIO7_LP_GPIO7_MCU_IE = 0x10 + // Position of LP_GPIO7_MCU_DRV field. + LP_IO_GPIO7_LP_GPIO7_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO7_MCU_DRV field. + LP_IO_GPIO7_LP_GPIO7_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO7_FUN_WPD field. + LP_IO_GPIO7_LP_GPIO7_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO7_FUN_WPD field. + LP_IO_GPIO7_LP_GPIO7_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO7_FUN_WPD. + LP_IO_GPIO7_LP_GPIO7_FUN_WPD = 0x80 + // Position of LP_GPIO7_FUN_WPU field. + LP_IO_GPIO7_LP_GPIO7_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO7_FUN_WPU field. + LP_IO_GPIO7_LP_GPIO7_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO7_FUN_WPU. + LP_IO_GPIO7_LP_GPIO7_FUN_WPU = 0x100 + // Position of LP_GPIO7_FUN_IE field. + LP_IO_GPIO7_LP_GPIO7_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO7_FUN_IE field. + LP_IO_GPIO7_LP_GPIO7_FUN_IE_Msk = 0x200 + // Bit LP_GPIO7_FUN_IE. + LP_IO_GPIO7_LP_GPIO7_FUN_IE = 0x200 + // Position of LP_GPIO7_FUN_DRV field. + LP_IO_GPIO7_LP_GPIO7_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO7_FUN_DRV field. + LP_IO_GPIO7_LP_GPIO7_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO7_MCU_SEL field. + LP_IO_GPIO7_LP_GPIO7_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO7_MCU_SEL field. + LP_IO_GPIO7_LP_GPIO7_MCU_SEL_Msk = 0x7000 + + // STATUS_INTERRUPT: need des + // Position of LP_GPIO_STATUS_INTERRUPT_NEXT field. + LP_IO_STATUS_INTERRUPT_LP_GPIO_STATUS_INTERRUPT_NEXT_Pos = 0x0 + // Bit mask of LP_GPIO_STATUS_INTERRUPT_NEXT field. + LP_IO_STATUS_INTERRUPT_LP_GPIO_STATUS_INTERRUPT_NEXT_Msk = 0xff + + // DEBUG_SEL0: need des + // Position of LP_DEBUG_SEL0 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL0_Pos = 0x0 + // Bit mask of LP_DEBUG_SEL0 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL0_Msk = 0x7f + // Position of LP_DEBUG_SEL1 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL1_Pos = 0x7 + // Bit mask of LP_DEBUG_SEL1 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL1_Msk = 0x3f80 + // Position of LP_DEBUG_SEL2 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL2_Pos = 0xe + // Bit mask of LP_DEBUG_SEL2 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL2_Msk = 0x1fc000 + // Position of LP_DEBUG_SEL3 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL3_Pos = 0x15 + // Bit mask of LP_DEBUG_SEL3 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL3_Msk = 0xfe00000 + + // DEBUG_SEL1: need des + // Position of LP_DEBUG_SEL4 field. + LP_IO_DEBUG_SEL1_LP_DEBUG_SEL4_Pos = 0x0 + // Bit mask of LP_DEBUG_SEL4 field. + LP_IO_DEBUG_SEL1_LP_DEBUG_SEL4_Msk = 0x7f + + // LPI2C: need des + // Position of LP_I2C_SDA_IE field. + LP_IO_LPI2C_LP_I2C_SDA_IE_Pos = 0x1e + // Bit mask of LP_I2C_SDA_IE field. + LP_IO_LPI2C_LP_I2C_SDA_IE_Msk = 0x40000000 + // Bit LP_I2C_SDA_IE. + LP_IO_LPI2C_LP_I2C_SDA_IE = 0x40000000 + // Position of LP_I2C_SCL_IE field. + LP_IO_LPI2C_LP_I2C_SCL_IE_Pos = 0x1f + // Bit mask of LP_I2C_SCL_IE field. + LP_IO_LPI2C_LP_I2C_SCL_IE_Msk = 0x80000000 + // Bit LP_I2C_SCL_IE. + LP_IO_LPI2C_LP_I2C_SCL_IE = 0x80000000 + + // DATE: need des + // Position of LP_IO_DATE field. + LP_IO_DATE_LP_IO_DATE_Pos = 0x0 + // Bit mask of LP_IO_DATE field. + LP_IO_DATE_LP_IO_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_IO_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_IO_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_IO_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_TEE: Low-power Trusted Execution Environment +const ( + // M0_MODE_CTRL: Tee mode control register + // Position of M0_MODE field. + LP_TEE_M0_MODE_CTRL_M0_MODE_Pos = 0x0 + // Bit mask of M0_MODE field. + LP_TEE_M0_MODE_CTRL_M0_MODE_Msk = 0x3 + + // CLOCK_GATE: Clock gating register + // Position of CLK_EN field. + LP_TEE_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + LP_TEE_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + LP_TEE_CLOCK_GATE_CLK_EN = 0x1 + + // FORCE_ACC_HP: need_des + // Position of LP_AON_FORCE_ACC_HPMEM_EN field. + LP_TEE_FORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN_Pos = 0x0 + // Bit mask of LP_AON_FORCE_ACC_HPMEM_EN field. + LP_TEE_FORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN_Msk = 0x1 + // Bit LP_AON_FORCE_ACC_HPMEM_EN. + LP_TEE_FORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + LP_TEE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_TEE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for LP_TIMER: Low-power Timer +const ( + // TAR0_LOW: need_des + // Position of MAIN_TIMER_TAR_LOW0 field. + LP_TIMER_TAR0_LOW_MAIN_TIMER_TAR_LOW0_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_LOW0 field. + LP_TIMER_TAR0_LOW_MAIN_TIMER_TAR_LOW0_Msk = 0xffffffff + + // TAR0_HIGH: need_des + // Position of MAIN_TIMER_TAR_HIGH0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_HIGH0_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_HIGH0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_HIGH0_Msk = 0xffff + // Position of MAIN_TIMER_TAR_EN0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0_Pos = 0x1f + // Bit mask of MAIN_TIMER_TAR_EN0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0_Msk = 0x80000000 + // Bit MAIN_TIMER_TAR_EN0. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0 = 0x80000000 + + // TAR1_LOW: need_des + // Position of MAIN_TIMER_TAR_LOW1 field. + LP_TIMER_TAR1_LOW_MAIN_TIMER_TAR_LOW1_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_LOW1 field. + LP_TIMER_TAR1_LOW_MAIN_TIMER_TAR_LOW1_Msk = 0xffffffff + + // TAR1_HIGH: need_des + // Position of MAIN_TIMER_TAR_HIGH1 field. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_HIGH1_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_HIGH1 field. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_HIGH1_Msk = 0xffff + // Position of MAIN_TIMER_TAR_EN1 field. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_EN1_Pos = 0x1f + // Bit mask of MAIN_TIMER_TAR_EN1 field. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_EN1_Msk = 0x80000000 + // Bit MAIN_TIMER_TAR_EN1. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_EN1 = 0x80000000 + + // UPDATE: need_des + // Position of MAIN_TIMER_UPDATE field. + LP_TIMER_UPDATE_MAIN_TIMER_UPDATE_Pos = 0x1c + // Bit mask of MAIN_TIMER_UPDATE field. + LP_TIMER_UPDATE_MAIN_TIMER_UPDATE_Msk = 0x10000000 + // Bit MAIN_TIMER_UPDATE. + LP_TIMER_UPDATE_MAIN_TIMER_UPDATE = 0x10000000 + // Position of MAIN_TIMER_XTAL_OFF field. + LP_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF_Pos = 0x1d + // Bit mask of MAIN_TIMER_XTAL_OFF field. + LP_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF_Msk = 0x20000000 + // Bit MAIN_TIMER_XTAL_OFF. + LP_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF = 0x20000000 + // Position of MAIN_TIMER_SYS_STALL field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_STALL_Pos = 0x1e + // Bit mask of MAIN_TIMER_SYS_STALL field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_STALL_Msk = 0x40000000 + // Bit MAIN_TIMER_SYS_STALL. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_STALL = 0x40000000 + // Position of MAIN_TIMER_SYS_RST field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_RST_Pos = 0x1f + // Bit mask of MAIN_TIMER_SYS_RST field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_RST_Msk = 0x80000000 + // Bit MAIN_TIMER_SYS_RST. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_RST = 0x80000000 + + // MAIN_BUF0_LOW: need_des + // Position of MAIN_TIMER_BUF0_LOW field. + LP_TIMER_MAIN_BUF0_LOW_MAIN_TIMER_BUF0_LOW_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF0_LOW field. + LP_TIMER_MAIN_BUF0_LOW_MAIN_TIMER_BUF0_LOW_Msk = 0xffffffff + + // MAIN_BUF0_HIGH: need_des + // Position of MAIN_TIMER_BUF0_HIGH field. + LP_TIMER_MAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF0_HIGH field. + LP_TIMER_MAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH_Msk = 0xffff + + // MAIN_BUF1_LOW: need_des + // Position of MAIN_TIMER_BUF1_LOW field. + LP_TIMER_MAIN_BUF1_LOW_MAIN_TIMER_BUF1_LOW_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF1_LOW field. + LP_TIMER_MAIN_BUF1_LOW_MAIN_TIMER_BUF1_LOW_Msk = 0xffffffff + + // MAIN_BUF1_HIGH: need_des + // Position of MAIN_TIMER_BUF1_HIGH field. + LP_TIMER_MAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF1_HIGH field. + LP_TIMER_MAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH_Msk = 0xffff + + // MAIN_OVERFLOW: need_des + // Position of MAIN_TIMER_ALARM_LOAD field. + LP_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD_Pos = 0x1f + // Bit mask of MAIN_TIMER_ALARM_LOAD field. + LP_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD_Msk = 0x80000000 + // Bit MAIN_TIMER_ALARM_LOAD. + LP_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD = 0x80000000 + + // INT_RAW: need_des + // Position of OVERFLOW_RAW field. + LP_TIMER_INT_RAW_OVERFLOW_RAW_Pos = 0x1e + // Bit mask of OVERFLOW_RAW field. + LP_TIMER_INT_RAW_OVERFLOW_RAW_Msk = 0x40000000 + // Bit OVERFLOW_RAW. + LP_TIMER_INT_RAW_OVERFLOW_RAW = 0x40000000 + // Position of SOC_WAKEUP_INT_RAW field. + LP_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_RAW field. + LP_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_RAW. + LP_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW = 0x80000000 + + // INT_ST: need_des + // Position of OVERFLOW_ST field. + LP_TIMER_INT_ST_OVERFLOW_ST_Pos = 0x1e + // Bit mask of OVERFLOW_ST field. + LP_TIMER_INT_ST_OVERFLOW_ST_Msk = 0x40000000 + // Bit OVERFLOW_ST. + LP_TIMER_INT_ST_OVERFLOW_ST = 0x40000000 + // Position of SOC_WAKEUP_INT_ST field. + LP_TIMER_INT_ST_SOC_WAKEUP_INT_ST_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ST field. + LP_TIMER_INT_ST_SOC_WAKEUP_INT_ST_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ST. + LP_TIMER_INT_ST_SOC_WAKEUP_INT_ST = 0x80000000 + + // INT_ENA: need_des + // Position of OVERFLOW_ENA field. + LP_TIMER_INT_ENA_OVERFLOW_ENA_Pos = 0x1e + // Bit mask of OVERFLOW_ENA field. + LP_TIMER_INT_ENA_OVERFLOW_ENA_Msk = 0x40000000 + // Bit OVERFLOW_ENA. + LP_TIMER_INT_ENA_OVERFLOW_ENA = 0x40000000 + // Position of SOC_WAKEUP_INT_ENA field. + LP_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ENA field. + LP_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ENA. + LP_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA = 0x80000000 + + // INT_CLR: need_des + // Position of OVERFLOW_CLR field. + LP_TIMER_INT_CLR_OVERFLOW_CLR_Pos = 0x1e + // Bit mask of OVERFLOW_CLR field. + LP_TIMER_INT_CLR_OVERFLOW_CLR_Msk = 0x40000000 + // Bit OVERFLOW_CLR. + LP_TIMER_INT_CLR_OVERFLOW_CLR = 0x40000000 + // Position of SOC_WAKEUP_INT_CLR field. + LP_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_CLR field. + LP_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_CLR. + LP_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR = 0x80000000 + + // LP_INT_RAW: need_des + // Position of MAIN_TIMER_OVERFLOW_LP_INT_RAW field. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW_Pos = 0x1e + // Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_RAW field. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW_Msk = 0x40000000 + // Bit MAIN_TIMER_OVERFLOW_LP_INT_RAW. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW = 0x40000000 + // Position of MAIN_TIMER_LP_INT_RAW field. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_LP_INT_RAW_Pos = 0x1f + // Bit mask of MAIN_TIMER_LP_INT_RAW field. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_LP_INT_RAW_Msk = 0x80000000 + // Bit MAIN_TIMER_LP_INT_RAW. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_LP_INT_RAW = 0x80000000 + + // LP_INT_ST: need_des + // Position of MAIN_TIMER_OVERFLOW_LP_INT_ST field. + LP_TIMER_LP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST_Pos = 0x1e + // Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_ST field. + LP_TIMER_LP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST_Msk = 0x40000000 + // Bit MAIN_TIMER_OVERFLOW_LP_INT_ST. + LP_TIMER_LP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST = 0x40000000 + // Position of MAIN_TIMER_LP_INT_ST field. + LP_TIMER_LP_INT_ST_MAIN_TIMER_LP_INT_ST_Pos = 0x1f + // Bit mask of MAIN_TIMER_LP_INT_ST field. + LP_TIMER_LP_INT_ST_MAIN_TIMER_LP_INT_ST_Msk = 0x80000000 + // Bit MAIN_TIMER_LP_INT_ST. + LP_TIMER_LP_INT_ST_MAIN_TIMER_LP_INT_ST = 0x80000000 + + // LP_INT_ENA: need_des + // Position of MAIN_TIMER_OVERFLOW_LP_INT_ENA field. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA_Pos = 0x1e + // Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_ENA field. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA_Msk = 0x40000000 + // Bit MAIN_TIMER_OVERFLOW_LP_INT_ENA. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA = 0x40000000 + // Position of MAIN_TIMER_LP_INT_ENA field. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_LP_INT_ENA_Pos = 0x1f + // Bit mask of MAIN_TIMER_LP_INT_ENA field. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_LP_INT_ENA_Msk = 0x80000000 + // Bit MAIN_TIMER_LP_INT_ENA. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_LP_INT_ENA = 0x80000000 + + // LP_INT_CLR: need_des + // Position of MAIN_TIMER_OVERFLOW_LP_INT_CLR field. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR_Pos = 0x1e + // Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_CLR field. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR_Msk = 0x40000000 + // Bit MAIN_TIMER_OVERFLOW_LP_INT_CLR. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR = 0x40000000 + // Position of MAIN_TIMER_LP_INT_CLR field. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_LP_INT_CLR_Pos = 0x1f + // Bit mask of MAIN_TIMER_LP_INT_CLR field. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_LP_INT_CLR_Msk = 0x80000000 + // Bit MAIN_TIMER_LP_INT_CLR. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_LP_INT_CLR = 0x80000000 + + // DATE: need_des + // Position of DATE field. + LP_TIMER_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_TIMER_DATE_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_TIMER_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_TIMER_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_TIMER_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_UART: Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller +const ( + // FIFO: FIFO data register + // Position of RXFIFO_RD_BYTE field. + LP_UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + LP_UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_FULL_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + LP_UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + LP_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + LP_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + LP_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of PARITY_ERR_INT_RAW field. + LP_UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + LP_UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + LP_UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of FRM_ERR_INT_RAW field. + LP_UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + LP_UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + LP_UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of RXFIFO_OVF_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + LP_UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of DSR_CHG_INT_RAW field. + LP_UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + LP_UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + LP_UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of CTS_CHG_INT_RAW field. + LP_UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + LP_UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + LP_UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of BRK_DET_INT_RAW field. + LP_UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + LP_UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + LP_UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of RXFIFO_TOUT_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + LP_UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of SW_XON_INT_RAW field. + LP_UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9 + // Bit mask of SW_XON_INT_RAW field. + LP_UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200 + // Bit SW_XON_INT_RAW. + LP_UART_INT_RAW_SW_XON_INT_RAW = 0x200 + // Position of SW_XOFF_INT_RAW field. + LP_UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa + // Bit mask of SW_XOFF_INT_RAW field. + LP_UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400 + // Bit SW_XOFF_INT_RAW. + LP_UART_INT_RAW_SW_XOFF_INT_RAW = 0x400 + // Position of GLITCH_DET_INT_RAW field. + LP_UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb + // Bit mask of GLITCH_DET_INT_RAW field. + LP_UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800 + // Bit GLITCH_DET_INT_RAW. + LP_UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800 + // Position of TX_BRK_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_RAW. + LP_UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_RAW. + LP_UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000 + // Position of TX_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of TX_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit TX_DONE_INT_RAW. + LP_UART_INT_RAW_TX_DONE_INT_RAW = 0x4000 + // Position of AT_CMD_CHAR_DET_INT_RAW field. + LP_UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_RAW field. + LP_UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_RAW. + LP_UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000 + // Position of WAKEUP_INT_RAW field. + LP_UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13 + // Bit mask of WAKEUP_INT_RAW field. + LP_UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000 + // Bit WAKEUP_INT_RAW. + LP_UART_INT_RAW_WAKEUP_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of RXFIFO_FULL_INT_ST field. + LP_UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + LP_UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + LP_UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + LP_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + LP_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + LP_UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of PARITY_ERR_INT_ST field. + LP_UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + LP_UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + LP_UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of FRM_ERR_INT_ST field. + LP_UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + LP_UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + LP_UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of RXFIFO_OVF_INT_ST field. + LP_UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + LP_UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + LP_UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of DSR_CHG_INT_ST field. + LP_UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + LP_UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + LP_UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of CTS_CHG_INT_ST field. + LP_UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + LP_UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + LP_UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of BRK_DET_INT_ST field. + LP_UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + LP_UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + LP_UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of RXFIFO_TOUT_INT_ST field. + LP_UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + LP_UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + LP_UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of SW_XON_INT_ST field. + LP_UART_INT_ST_SW_XON_INT_ST_Pos = 0x9 + // Bit mask of SW_XON_INT_ST field. + LP_UART_INT_ST_SW_XON_INT_ST_Msk = 0x200 + // Bit SW_XON_INT_ST. + LP_UART_INT_ST_SW_XON_INT_ST = 0x200 + // Position of SW_XOFF_INT_ST field. + LP_UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa + // Bit mask of SW_XOFF_INT_ST field. + LP_UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400 + // Bit SW_XOFF_INT_ST. + LP_UART_INT_ST_SW_XOFF_INT_ST = 0x400 + // Position of GLITCH_DET_INT_ST field. + LP_UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ST field. + LP_UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800 + // Bit GLITCH_DET_INT_ST. + LP_UART_INT_ST_GLITCH_DET_INT_ST = 0x800 + // Position of TX_BRK_DONE_INT_ST field. + LP_UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ST field. + LP_UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ST. + LP_UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ST field. + LP_UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ST field. + LP_UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ST. + LP_UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000 + // Position of TX_DONE_INT_ST field. + LP_UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of TX_DONE_INT_ST field. + LP_UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000 + // Bit TX_DONE_INT_ST. + LP_UART_INT_ST_TX_DONE_INT_ST = 0x4000 + // Position of AT_CMD_CHAR_DET_INT_ST field. + LP_UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ST field. + LP_UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ST. + LP_UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000 + // Position of WAKEUP_INT_ST field. + LP_UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13 + // Bit mask of WAKEUP_INT_ST field. + LP_UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000 + // Bit WAKEUP_INT_ST. + LP_UART_INT_ST_WAKEUP_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_FULL_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + LP_UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + LP_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + LP_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + LP_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of PARITY_ERR_INT_ENA field. + LP_UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + LP_UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + LP_UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of FRM_ERR_INT_ENA field. + LP_UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + LP_UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + LP_UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of RXFIFO_OVF_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + LP_UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of DSR_CHG_INT_ENA field. + LP_UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + LP_UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + LP_UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of CTS_CHG_INT_ENA field. + LP_UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + LP_UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + LP_UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of BRK_DET_INT_ENA field. + LP_UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + LP_UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + LP_UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of RXFIFO_TOUT_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + LP_UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of SW_XON_INT_ENA field. + LP_UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9 + // Bit mask of SW_XON_INT_ENA field. + LP_UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200 + // Bit SW_XON_INT_ENA. + LP_UART_INT_ENA_SW_XON_INT_ENA = 0x200 + // Position of SW_XOFF_INT_ENA field. + LP_UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa + // Bit mask of SW_XOFF_INT_ENA field. + LP_UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400 + // Bit SW_XOFF_INT_ENA. + LP_UART_INT_ENA_SW_XOFF_INT_ENA = 0x400 + // Position of GLITCH_DET_INT_ENA field. + LP_UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ENA field. + LP_UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800 + // Bit GLITCH_DET_INT_ENA. + LP_UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800 + // Position of TX_BRK_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ENA. + LP_UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ENA. + LP_UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000 + // Position of TX_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of TX_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit TX_DONE_INT_ENA. + LP_UART_INT_ENA_TX_DONE_INT_ENA = 0x4000 + // Position of AT_CMD_CHAR_DET_INT_ENA field. + LP_UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ENA field. + LP_UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ENA. + LP_UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000 + // Position of WAKEUP_INT_ENA field. + LP_UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13 + // Bit mask of WAKEUP_INT_ENA field. + LP_UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000 + // Bit WAKEUP_INT_ENA. + LP_UART_INT_ENA_WAKEUP_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_FULL_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + LP_UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + LP_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + LP_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + LP_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of PARITY_ERR_INT_CLR field. + LP_UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + LP_UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + LP_UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of FRM_ERR_INT_CLR field. + LP_UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + LP_UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + LP_UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of RXFIFO_OVF_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + LP_UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of DSR_CHG_INT_CLR field. + LP_UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + LP_UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + LP_UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of CTS_CHG_INT_CLR field. + LP_UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + LP_UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + LP_UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of BRK_DET_INT_CLR field. + LP_UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + LP_UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + LP_UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of RXFIFO_TOUT_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + LP_UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of SW_XON_INT_CLR field. + LP_UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9 + // Bit mask of SW_XON_INT_CLR field. + LP_UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200 + // Bit SW_XON_INT_CLR. + LP_UART_INT_CLR_SW_XON_INT_CLR = 0x200 + // Position of SW_XOFF_INT_CLR field. + LP_UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa + // Bit mask of SW_XOFF_INT_CLR field. + LP_UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400 + // Bit SW_XOFF_INT_CLR. + LP_UART_INT_CLR_SW_XOFF_INT_CLR = 0x400 + // Position of GLITCH_DET_INT_CLR field. + LP_UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb + // Bit mask of GLITCH_DET_INT_CLR field. + LP_UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800 + // Bit GLITCH_DET_INT_CLR. + LP_UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800 + // Position of TX_BRK_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_CLR. + LP_UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_CLR. + LP_UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000 + // Position of TX_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of TX_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit TX_DONE_INT_CLR. + LP_UART_INT_CLR_TX_DONE_INT_CLR = 0x4000 + // Position of AT_CMD_CHAR_DET_INT_CLR field. + LP_UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_CLR field. + LP_UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_CLR. + LP_UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000 + // Position of WAKEUP_INT_CLR field. + LP_UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13 + // Bit mask of WAKEUP_INT_CLR field. + LP_UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000 + // Bit WAKEUP_INT_CLR. + LP_UART_INT_CLR_WAKEUP_INT_CLR = 0x80000 + + // CLKDIV: Clock divider configuration + // Position of CLKDIV field. + LP_UART_CLKDIV_CLKDIV_Pos = 0x0 + // Bit mask of CLKDIV field. + LP_UART_CLKDIV_CLKDIV_Msk = 0xfff + // Position of FRAG field. + LP_UART_CLKDIV_FRAG_Pos = 0x14 + // Bit mask of FRAG field. + LP_UART_CLKDIV_FRAG_Msk = 0xf00000 + + // RX_FILT: Rx Filter configuration + // Position of GLITCH_FILT field. + LP_UART_RX_FILT_GLITCH_FILT_Pos = 0x0 + // Bit mask of GLITCH_FILT field. + LP_UART_RX_FILT_GLITCH_FILT_Msk = 0xff + // Position of GLITCH_FILT_EN field. + LP_UART_RX_FILT_GLITCH_FILT_EN_Pos = 0x8 + // Bit mask of GLITCH_FILT_EN field. + LP_UART_RX_FILT_GLITCH_FILT_EN_Msk = 0x100 + // Bit GLITCH_FILT_EN. + LP_UART_RX_FILT_GLITCH_FILT_EN = 0x100 + + // STATUS: UART status register + // Position of RXFIFO_CNT field. + LP_UART_STATUS_RXFIFO_CNT_Pos = 0x3 + // Bit mask of RXFIFO_CNT field. + LP_UART_STATUS_RXFIFO_CNT_Msk = 0xf8 + // Position of DSRN field. + LP_UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + LP_UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + LP_UART_STATUS_DSRN = 0x2000 + // Position of CTSN field. + LP_UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + LP_UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + LP_UART_STATUS_CTSN = 0x4000 + // Position of RXD field. + LP_UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + LP_UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + LP_UART_STATUS_RXD = 0x8000 + // Position of TXFIFO_CNT field. + LP_UART_STATUS_TXFIFO_CNT_Pos = 0x13 + // Bit mask of TXFIFO_CNT field. + LP_UART_STATUS_TXFIFO_CNT_Msk = 0xf80000 + // Position of DTRN field. + LP_UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + LP_UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + LP_UART_STATUS_DTRN = 0x20000000 + // Position of RTSN field. + LP_UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + LP_UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + LP_UART_STATUS_RTSN = 0x40000000 + // Position of TXD field. + LP_UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + LP_UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + LP_UART_STATUS_TXD = 0x80000000 + + // CONF0: Configuration register 0 + // Position of PARITY field. + LP_UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + LP_UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + LP_UART_CONF0_PARITY = 0x1 + // Position of PARITY_EN field. + LP_UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + LP_UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + LP_UART_CONF0_PARITY_EN = 0x2 + // Position of BIT_NUM field. + LP_UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + LP_UART_CONF0_BIT_NUM_Msk = 0xc + // Position of STOP_BIT_NUM field. + LP_UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + LP_UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of TXD_BRK field. + LP_UART_CONF0_TXD_BRK_Pos = 0x6 + // Bit mask of TXD_BRK field. + LP_UART_CONF0_TXD_BRK_Msk = 0x40 + // Bit TXD_BRK. + LP_UART_CONF0_TXD_BRK = 0x40 + // Position of LOOPBACK field. + LP_UART_CONF0_LOOPBACK_Pos = 0xc + // Bit mask of LOOPBACK field. + LP_UART_CONF0_LOOPBACK_Msk = 0x1000 + // Bit LOOPBACK. + LP_UART_CONF0_LOOPBACK = 0x1000 + // Position of TX_FLOW_EN field. + LP_UART_CONF0_TX_FLOW_EN_Pos = 0xd + // Bit mask of TX_FLOW_EN field. + LP_UART_CONF0_TX_FLOW_EN_Msk = 0x2000 + // Bit TX_FLOW_EN. + LP_UART_CONF0_TX_FLOW_EN = 0x2000 + // Position of RXD_INV field. + LP_UART_CONF0_RXD_INV_Pos = 0xf + // Bit mask of RXD_INV field. + LP_UART_CONF0_RXD_INV_Msk = 0x8000 + // Bit RXD_INV. + LP_UART_CONF0_RXD_INV = 0x8000 + // Position of TXD_INV field. + LP_UART_CONF0_TXD_INV_Pos = 0x10 + // Bit mask of TXD_INV field. + LP_UART_CONF0_TXD_INV_Msk = 0x10000 + // Bit TXD_INV. + LP_UART_CONF0_TXD_INV = 0x10000 + // Position of DIS_RX_DAT_OVF field. + LP_UART_CONF0_DIS_RX_DAT_OVF_Pos = 0x11 + // Bit mask of DIS_RX_DAT_OVF field. + LP_UART_CONF0_DIS_RX_DAT_OVF_Msk = 0x20000 + // Bit DIS_RX_DAT_OVF. + LP_UART_CONF0_DIS_RX_DAT_OVF = 0x20000 + // Position of ERR_WR_MASK field. + LP_UART_CONF0_ERR_WR_MASK_Pos = 0x12 + // Bit mask of ERR_WR_MASK field. + LP_UART_CONF0_ERR_WR_MASK_Msk = 0x40000 + // Bit ERR_WR_MASK. + LP_UART_CONF0_ERR_WR_MASK = 0x40000 + // Position of MEM_CLK_EN field. + LP_UART_CONF0_MEM_CLK_EN_Pos = 0x14 + // Bit mask of MEM_CLK_EN field. + LP_UART_CONF0_MEM_CLK_EN_Msk = 0x100000 + // Bit MEM_CLK_EN. + LP_UART_CONF0_MEM_CLK_EN = 0x100000 + // Position of SW_RTS field. + LP_UART_CONF0_SW_RTS_Pos = 0x15 + // Bit mask of SW_RTS field. + LP_UART_CONF0_SW_RTS_Msk = 0x200000 + // Bit SW_RTS. + LP_UART_CONF0_SW_RTS = 0x200000 + // Position of RXFIFO_RST field. + LP_UART_CONF0_RXFIFO_RST_Pos = 0x16 + // Bit mask of RXFIFO_RST field. + LP_UART_CONF0_RXFIFO_RST_Msk = 0x400000 + // Bit RXFIFO_RST. + LP_UART_CONF0_RXFIFO_RST = 0x400000 + // Position of TXFIFO_RST field. + LP_UART_CONF0_TXFIFO_RST_Pos = 0x17 + // Bit mask of TXFIFO_RST field. + LP_UART_CONF0_TXFIFO_RST_Msk = 0x800000 + // Bit TXFIFO_RST. + LP_UART_CONF0_TXFIFO_RST = 0x800000 + + // CONF1: Configuration register 1 + // Position of RXFIFO_FULL_THRHD field. + LP_UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x3 + // Bit mask of RXFIFO_FULL_THRHD field. + LP_UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0xf8 + // Position of TXFIFO_EMPTY_THRHD field. + LP_UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0xb + // Bit mask of TXFIFO_EMPTY_THRHD field. + LP_UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0xf800 + // Position of CTS_INV field. + LP_UART_CONF1_CTS_INV_Pos = 0x10 + // Bit mask of CTS_INV field. + LP_UART_CONF1_CTS_INV_Msk = 0x10000 + // Bit CTS_INV. + LP_UART_CONF1_CTS_INV = 0x10000 + // Position of DSR_INV field. + LP_UART_CONF1_DSR_INV_Pos = 0x11 + // Bit mask of DSR_INV field. + LP_UART_CONF1_DSR_INV_Msk = 0x20000 + // Bit DSR_INV. + LP_UART_CONF1_DSR_INV = 0x20000 + // Position of RTS_INV field. + LP_UART_CONF1_RTS_INV_Pos = 0x12 + // Bit mask of RTS_INV field. + LP_UART_CONF1_RTS_INV_Msk = 0x40000 + // Bit RTS_INV. + LP_UART_CONF1_RTS_INV = 0x40000 + // Position of DTR_INV field. + LP_UART_CONF1_DTR_INV_Pos = 0x13 + // Bit mask of DTR_INV field. + LP_UART_CONF1_DTR_INV_Msk = 0x80000 + // Bit DTR_INV. + LP_UART_CONF1_DTR_INV = 0x80000 + // Position of SW_DTR field. + LP_UART_CONF1_SW_DTR_Pos = 0x14 + // Bit mask of SW_DTR field. + LP_UART_CONF1_SW_DTR_Msk = 0x100000 + // Bit SW_DTR. + LP_UART_CONF1_SW_DTR = 0x100000 + // Position of CLK_EN field. + LP_UART_CONF1_CLK_EN_Pos = 0x15 + // Bit mask of CLK_EN field. + LP_UART_CONF1_CLK_EN_Msk = 0x200000 + // Bit CLK_EN. + LP_UART_CONF1_CLK_EN = 0x200000 + + // HWFC_CONF: Hardware flow-control configuration + // Position of RX_FLOW_THRHD field. + LP_UART_HWFC_CONF_RX_FLOW_THRHD_Pos = 0x3 + // Bit mask of RX_FLOW_THRHD field. + LP_UART_HWFC_CONF_RX_FLOW_THRHD_Msk = 0xf8 + // Position of RX_FLOW_EN field. + LP_UART_HWFC_CONF_RX_FLOW_EN_Pos = 0x8 + // Bit mask of RX_FLOW_EN field. + LP_UART_HWFC_CONF_RX_FLOW_EN_Msk = 0x100 + // Bit RX_FLOW_EN. + LP_UART_HWFC_CONF_RX_FLOW_EN = 0x100 + + // SLEEP_CONF0: UART sleep configure register 0 + // Position of WK_CHAR1 field. + LP_UART_SLEEP_CONF0_WK_CHAR1_Pos = 0x0 + // Bit mask of WK_CHAR1 field. + LP_UART_SLEEP_CONF0_WK_CHAR1_Msk = 0xff + // Position of WK_CHAR2 field. + LP_UART_SLEEP_CONF0_WK_CHAR2_Pos = 0x8 + // Bit mask of WK_CHAR2 field. + LP_UART_SLEEP_CONF0_WK_CHAR2_Msk = 0xff00 + // Position of WK_CHAR3 field. + LP_UART_SLEEP_CONF0_WK_CHAR3_Pos = 0x10 + // Bit mask of WK_CHAR3 field. + LP_UART_SLEEP_CONF0_WK_CHAR3_Msk = 0xff0000 + // Position of WK_CHAR4 field. + LP_UART_SLEEP_CONF0_WK_CHAR4_Pos = 0x18 + // Bit mask of WK_CHAR4 field. + LP_UART_SLEEP_CONF0_WK_CHAR4_Msk = 0xff000000 + + // SLEEP_CONF1: UART sleep configure register 1 + // Position of WK_CHAR0 field. + LP_UART_SLEEP_CONF1_WK_CHAR0_Pos = 0x0 + // Bit mask of WK_CHAR0 field. + LP_UART_SLEEP_CONF1_WK_CHAR0_Msk = 0xff + + // SLEEP_CONF2: UART sleep configure register 2 + // Position of ACTIVE_THRESHOLD field. + LP_UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Pos = 0x0 + // Bit mask of ACTIVE_THRESHOLD field. + LP_UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Msk = 0x3ff + // Position of RX_WAKE_UP_THRHD field. + LP_UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Pos = 0xd + // Bit mask of RX_WAKE_UP_THRHD field. + LP_UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Msk = 0x3e000 + // Position of WK_CHAR_NUM field. + LP_UART_SLEEP_CONF2_WK_CHAR_NUM_Pos = 0x12 + // Bit mask of WK_CHAR_NUM field. + LP_UART_SLEEP_CONF2_WK_CHAR_NUM_Msk = 0x1c0000 + // Position of WK_CHAR_MASK field. + LP_UART_SLEEP_CONF2_WK_CHAR_MASK_Pos = 0x15 + // Bit mask of WK_CHAR_MASK field. + LP_UART_SLEEP_CONF2_WK_CHAR_MASK_Msk = 0x3e00000 + // Position of WK_MODE_SEL field. + LP_UART_SLEEP_CONF2_WK_MODE_SEL_Pos = 0x1a + // Bit mask of WK_MODE_SEL field. + LP_UART_SLEEP_CONF2_WK_MODE_SEL_Msk = 0xc000000 + + // SWFC_CONF0: Software flow-control character configuration + // Position of XON_CHAR field. + LP_UART_SWFC_CONF0_XON_CHAR_Pos = 0x0 + // Bit mask of XON_CHAR field. + LP_UART_SWFC_CONF0_XON_CHAR_Msk = 0xff + // Position of XOFF_CHAR field. + LP_UART_SWFC_CONF0_XOFF_CHAR_Pos = 0x8 + // Bit mask of XOFF_CHAR field. + LP_UART_SWFC_CONF0_XOFF_CHAR_Msk = 0xff00 + // Position of XON_XOFF_STILL_SEND field. + LP_UART_SWFC_CONF0_XON_XOFF_STILL_SEND_Pos = 0x10 + // Bit mask of XON_XOFF_STILL_SEND field. + LP_UART_SWFC_CONF0_XON_XOFF_STILL_SEND_Msk = 0x10000 + // Bit XON_XOFF_STILL_SEND. + LP_UART_SWFC_CONF0_XON_XOFF_STILL_SEND = 0x10000 + // Position of SW_FLOW_CON_EN field. + LP_UART_SWFC_CONF0_SW_FLOW_CON_EN_Pos = 0x11 + // Bit mask of SW_FLOW_CON_EN field. + LP_UART_SWFC_CONF0_SW_FLOW_CON_EN_Msk = 0x20000 + // Bit SW_FLOW_CON_EN. + LP_UART_SWFC_CONF0_SW_FLOW_CON_EN = 0x20000 + // Position of XONOFF_DEL field. + LP_UART_SWFC_CONF0_XONOFF_DEL_Pos = 0x12 + // Bit mask of XONOFF_DEL field. + LP_UART_SWFC_CONF0_XONOFF_DEL_Msk = 0x40000 + // Bit XONOFF_DEL. + LP_UART_SWFC_CONF0_XONOFF_DEL = 0x40000 + // Position of FORCE_XON field. + LP_UART_SWFC_CONF0_FORCE_XON_Pos = 0x13 + // Bit mask of FORCE_XON field. + LP_UART_SWFC_CONF0_FORCE_XON_Msk = 0x80000 + // Bit FORCE_XON. + LP_UART_SWFC_CONF0_FORCE_XON = 0x80000 + // Position of FORCE_XOFF field. + LP_UART_SWFC_CONF0_FORCE_XOFF_Pos = 0x14 + // Bit mask of FORCE_XOFF field. + LP_UART_SWFC_CONF0_FORCE_XOFF_Msk = 0x100000 + // Bit FORCE_XOFF. + LP_UART_SWFC_CONF0_FORCE_XOFF = 0x100000 + // Position of SEND_XON field. + LP_UART_SWFC_CONF0_SEND_XON_Pos = 0x15 + // Bit mask of SEND_XON field. + LP_UART_SWFC_CONF0_SEND_XON_Msk = 0x200000 + // Bit SEND_XON. + LP_UART_SWFC_CONF0_SEND_XON = 0x200000 + // Position of SEND_XOFF field. + LP_UART_SWFC_CONF0_SEND_XOFF_Pos = 0x16 + // Bit mask of SEND_XOFF field. + LP_UART_SWFC_CONF0_SEND_XOFF_Msk = 0x400000 + // Bit SEND_XOFF. + LP_UART_SWFC_CONF0_SEND_XOFF = 0x400000 + + // SWFC_CONF1: Software flow-control character configuration + // Position of XON_THRESHOLD field. + LP_UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x3 + // Bit mask of XON_THRESHOLD field. + LP_UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0xf8 + // Position of XOFF_THRESHOLD field. + LP_UART_SWFC_CONF1_XOFF_THRESHOLD_Pos = 0xb + // Bit mask of XOFF_THRESHOLD field. + LP_UART_SWFC_CONF1_XOFF_THRESHOLD_Msk = 0xf800 + + // TXBRK_CONF: Tx Break character configuration + // Position of TX_BRK_NUM field. + LP_UART_TXBRK_CONF_TX_BRK_NUM_Pos = 0x0 + // Bit mask of TX_BRK_NUM field. + LP_UART_TXBRK_CONF_TX_BRK_NUM_Msk = 0xff + + // IDLE_CONF: Frame-end idle configuration + // Position of RX_IDLE_THRHD field. + LP_UART_IDLE_CONF_RX_IDLE_THRHD_Pos = 0x0 + // Bit mask of RX_IDLE_THRHD field. + LP_UART_IDLE_CONF_RX_IDLE_THRHD_Msk = 0x3ff + // Position of TX_IDLE_NUM field. + LP_UART_IDLE_CONF_TX_IDLE_NUM_Pos = 0xa + // Bit mask of TX_IDLE_NUM field. + LP_UART_IDLE_CONF_TX_IDLE_NUM_Msk = 0xffc00 + + // RS485_CONF: RS485 mode configuration + // Position of DL0_EN field. + LP_UART_RS485_CONF_DL0_EN_Pos = 0x1 + // Bit mask of DL0_EN field. + LP_UART_RS485_CONF_DL0_EN_Msk = 0x2 + // Bit DL0_EN. + LP_UART_RS485_CONF_DL0_EN = 0x2 + // Position of DL1_EN field. + LP_UART_RS485_CONF_DL1_EN_Pos = 0x2 + // Bit mask of DL1_EN field. + LP_UART_RS485_CONF_DL1_EN_Msk = 0x4 + // Bit DL1_EN. + LP_UART_RS485_CONF_DL1_EN = 0x4 + + // AT_CMD_PRECNT: Pre-sequence timing configuration + // Position of PRE_IDLE_NUM field. + LP_UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Pos = 0x0 + // Bit mask of PRE_IDLE_NUM field. + LP_UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Msk = 0xffff + + // AT_CMD_POSTCNT: Post-sequence timing configuration + // Position of POST_IDLE_NUM field. + LP_UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Pos = 0x0 + // Bit mask of POST_IDLE_NUM field. + LP_UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Msk = 0xffff + + // AT_CMD_GAPTOUT: Timeout configuration + // Position of RX_GAP_TOUT field. + LP_UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Pos = 0x0 + // Bit mask of RX_GAP_TOUT field. + LP_UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Msk = 0xffff + + // AT_CMD_CHAR: AT escape sequence detection configuration + // Position of AT_CMD_CHAR field. + LP_UART_AT_CMD_CHAR_AT_CMD_CHAR_Pos = 0x0 + // Bit mask of AT_CMD_CHAR field. + LP_UART_AT_CMD_CHAR_AT_CMD_CHAR_Msk = 0xff + // Position of CHAR_NUM field. + LP_UART_AT_CMD_CHAR_CHAR_NUM_Pos = 0x8 + // Bit mask of CHAR_NUM field. + LP_UART_AT_CMD_CHAR_CHAR_NUM_Msk = 0xff00 + + // MEM_CONF: UART memory power configuration + // Position of MEM_FORCE_PD field. + LP_UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x19 + // Bit mask of MEM_FORCE_PD field. + LP_UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x2000000 + // Bit MEM_FORCE_PD. + LP_UART_MEM_CONF_MEM_FORCE_PD = 0x2000000 + // Position of MEM_FORCE_PU field. + LP_UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1a + // Bit mask of MEM_FORCE_PU field. + LP_UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x4000000 + // Bit MEM_FORCE_PU. + LP_UART_MEM_CONF_MEM_FORCE_PU = 0x4000000 + + // TOUT_CONF: UART threshold and allocation configuration + // Position of RX_TOUT_EN field. + LP_UART_TOUT_CONF_RX_TOUT_EN_Pos = 0x0 + // Bit mask of RX_TOUT_EN field. + LP_UART_TOUT_CONF_RX_TOUT_EN_Msk = 0x1 + // Bit RX_TOUT_EN. + LP_UART_TOUT_CONF_RX_TOUT_EN = 0x1 + // Position of RX_TOUT_FLOW_DIS field. + LP_UART_TOUT_CONF_RX_TOUT_FLOW_DIS_Pos = 0x1 + // Bit mask of RX_TOUT_FLOW_DIS field. + LP_UART_TOUT_CONF_RX_TOUT_FLOW_DIS_Msk = 0x2 + // Bit RX_TOUT_FLOW_DIS. + LP_UART_TOUT_CONF_RX_TOUT_FLOW_DIS = 0x2 + // Position of RX_TOUT_THRHD field. + LP_UART_TOUT_CONF_RX_TOUT_THRHD_Pos = 0x2 + // Bit mask of RX_TOUT_THRHD field. + LP_UART_TOUT_CONF_RX_TOUT_THRHD_Msk = 0xffc + + // MEM_TX_STATUS: Tx-SRAM write and read offset address. + // Position of TX_SRAM_WADDR field. + LP_UART_MEM_TX_STATUS_TX_SRAM_WADDR_Pos = 0x3 + // Bit mask of TX_SRAM_WADDR field. + LP_UART_MEM_TX_STATUS_TX_SRAM_WADDR_Msk = 0xf8 + // Position of TX_SRAM_RADDR field. + LP_UART_MEM_TX_STATUS_TX_SRAM_RADDR_Pos = 0xc + // Bit mask of TX_SRAM_RADDR field. + LP_UART_MEM_TX_STATUS_TX_SRAM_RADDR_Msk = 0x1f000 + + // MEM_RX_STATUS: Rx-SRAM write and read offset address. + // Position of RX_SRAM_RADDR field. + LP_UART_MEM_RX_STATUS_RX_SRAM_RADDR_Pos = 0x3 + // Bit mask of RX_SRAM_RADDR field. + LP_UART_MEM_RX_STATUS_RX_SRAM_RADDR_Msk = 0xf8 + // Position of RX_SRAM_WADDR field. + LP_UART_MEM_RX_STATUS_RX_SRAM_WADDR_Pos = 0xc + // Bit mask of RX_SRAM_WADDR field. + LP_UART_MEM_RX_STATUS_RX_SRAM_WADDR_Msk = 0x1f000 + + // FSM_STATUS: UART transmit and receive status. + // Position of ST_URX_OUT field. + LP_UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0 + // Bit mask of ST_URX_OUT field. + LP_UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf + // Position of ST_UTX_OUT field. + LP_UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4 + // Bit mask of ST_UTX_OUT field. + LP_UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0 + + // CLK_CONF: UART core clock configuration + // Position of SCLK_DIV_B field. + LP_UART_CLK_CONF_SCLK_DIV_B_Pos = 0x0 + // Bit mask of SCLK_DIV_B field. + LP_UART_CLK_CONF_SCLK_DIV_B_Msk = 0x3f + // Position of SCLK_DIV_A field. + LP_UART_CLK_CONF_SCLK_DIV_A_Pos = 0x6 + // Bit mask of SCLK_DIV_A field. + LP_UART_CLK_CONF_SCLK_DIV_A_Msk = 0xfc0 + // Position of SCLK_DIV_NUM field. + LP_UART_CLK_CONF_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of SCLK_DIV_NUM field. + LP_UART_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff000 + // Position of SCLK_SEL field. + LP_UART_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + LP_UART_CLK_CONF_SCLK_SEL_Msk = 0x300000 + // Position of SCLK_EN field. + LP_UART_CLK_CONF_SCLK_EN_Pos = 0x16 + // Bit mask of SCLK_EN field. + LP_UART_CLK_CONF_SCLK_EN_Msk = 0x400000 + // Bit SCLK_EN. + LP_UART_CLK_CONF_SCLK_EN = 0x400000 + // Position of RST_CORE field. + LP_UART_CLK_CONF_RST_CORE_Pos = 0x17 + // Bit mask of RST_CORE field. + LP_UART_CLK_CONF_RST_CORE_Msk = 0x800000 + // Bit RST_CORE. + LP_UART_CLK_CONF_RST_CORE = 0x800000 + // Position of TX_SCLK_EN field. + LP_UART_CLK_CONF_TX_SCLK_EN_Pos = 0x18 + // Bit mask of TX_SCLK_EN field. + LP_UART_CLK_CONF_TX_SCLK_EN_Msk = 0x1000000 + // Bit TX_SCLK_EN. + LP_UART_CLK_CONF_TX_SCLK_EN = 0x1000000 + // Position of RX_SCLK_EN field. + LP_UART_CLK_CONF_RX_SCLK_EN_Pos = 0x19 + // Bit mask of RX_SCLK_EN field. + LP_UART_CLK_CONF_RX_SCLK_EN_Msk = 0x2000000 + // Bit RX_SCLK_EN. + LP_UART_CLK_CONF_RX_SCLK_EN = 0x2000000 + // Position of TX_RST_CORE field. + LP_UART_CLK_CONF_TX_RST_CORE_Pos = 0x1a + // Bit mask of TX_RST_CORE field. + LP_UART_CLK_CONF_TX_RST_CORE_Msk = 0x4000000 + // Bit TX_RST_CORE. + LP_UART_CLK_CONF_TX_RST_CORE = 0x4000000 + // Position of RX_RST_CORE field. + LP_UART_CLK_CONF_RX_RST_CORE_Pos = 0x1b + // Bit mask of RX_RST_CORE field. + LP_UART_CLK_CONF_RX_RST_CORE_Msk = 0x8000000 + // Bit RX_RST_CORE. + LP_UART_CLK_CONF_RX_RST_CORE = 0x8000000 + + // DATE: UART Version register + // Position of DATE field. + LP_UART_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_UART_DATE_DATE_Msk = 0xffffffff + + // AFIFO_STATUS: UART AFIFO Status + // Position of TX_AFIFO_FULL field. + LP_UART_AFIFO_STATUS_TX_AFIFO_FULL_Pos = 0x0 + // Bit mask of TX_AFIFO_FULL field. + LP_UART_AFIFO_STATUS_TX_AFIFO_FULL_Msk = 0x1 + // Bit TX_AFIFO_FULL. + LP_UART_AFIFO_STATUS_TX_AFIFO_FULL = 0x1 + // Position of TX_AFIFO_EMPTY field. + LP_UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Pos = 0x1 + // Bit mask of TX_AFIFO_EMPTY field. + LP_UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Msk = 0x2 + // Bit TX_AFIFO_EMPTY. + LP_UART_AFIFO_STATUS_TX_AFIFO_EMPTY = 0x2 + // Position of RX_AFIFO_FULL field. + LP_UART_AFIFO_STATUS_RX_AFIFO_FULL_Pos = 0x2 + // Bit mask of RX_AFIFO_FULL field. + LP_UART_AFIFO_STATUS_RX_AFIFO_FULL_Msk = 0x4 + // Bit RX_AFIFO_FULL. + LP_UART_AFIFO_STATUS_RX_AFIFO_FULL = 0x4 + // Position of RX_AFIFO_EMPTY field. + LP_UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Pos = 0x3 + // Bit mask of RX_AFIFO_EMPTY field. + LP_UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Msk = 0x8 + // Bit RX_AFIFO_EMPTY. + LP_UART_AFIFO_STATUS_RX_AFIFO_EMPTY = 0x8 + + // REG_UPDATE: UART Registers Configuration Update register + // Position of REG_UPDATE field. + LP_UART_REG_UPDATE_REG_UPDATE_Pos = 0x0 + // Bit mask of REG_UPDATE field. + LP_UART_REG_UPDATE_REG_UPDATE_Msk = 0x1 + // Bit REG_UPDATE. + LP_UART_REG_UPDATE_REG_UPDATE = 0x1 + + // ID: UART ID register + // Position of ID field. + LP_UART_ID_ID_Pos = 0x0 + // Bit mask of ID field. + LP_UART_ID_ID_Msk = 0xffffffff +) + +// Constants for LP_WDT: Low-power Watchdog Timer +const ( + // WDTCONFIG0: need_des + // Position of WDT_CHIP_RESET_WIDTH field. + LP_WDT_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Pos = 0x0 + // Bit mask of WDT_CHIP_RESET_WIDTH field. + LP_WDT_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Msk = 0xff + // Position of WDT_CHIP_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_CHIP_RESET_EN_Pos = 0x8 + // Bit mask of WDT_CHIP_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_CHIP_RESET_EN_Msk = 0x100 + // Bit WDT_CHIP_RESET_EN. + LP_WDT_WDTCONFIG0_WDT_CHIP_RESET_EN = 0x100 + // Position of WDT_PAUSE_IN_SLP field. + LP_WDT_WDTCONFIG0_WDT_PAUSE_IN_SLP_Pos = 0x9 + // Bit mask of WDT_PAUSE_IN_SLP field. + LP_WDT_WDTCONFIG0_WDT_PAUSE_IN_SLP_Msk = 0x200 + // Bit WDT_PAUSE_IN_SLP. + LP_WDT_WDTCONFIG0_WDT_PAUSE_IN_SLP = 0x200 + // Position of WDT_APPCPU_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xa + // Bit mask of WDT_APPCPU_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x400 + // Bit WDT_APPCPU_RESET_EN. + LP_WDT_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x400 + // Position of WDT_PROCPU_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xb + // Bit mask of WDT_PROCPU_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x800 + // Bit WDT_PROCPU_RESET_EN. + LP_WDT_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x800 + // Position of WDT_FLASHBOOT_MOD_EN field. + LP_WDT_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xc + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + LP_WDT_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x1000 + // Bit WDT_FLASHBOOT_MOD_EN. + LP_WDT_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x1000 + // Position of WDT_SYS_RESET_LENGTH field. + LP_WDT_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xd + // Bit mask of WDT_SYS_RESET_LENGTH field. + LP_WDT_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0xe000 + // Position of WDT_CPU_RESET_LENGTH field. + LP_WDT_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x10 + // Bit mask of WDT_CPU_RESET_LENGTH field. + LP_WDT_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x70000 + // Position of WDT_STG3 field. + LP_WDT_WDTCONFIG0_WDT_STG3_Pos = 0x13 + // Bit mask of WDT_STG3 field. + LP_WDT_WDTCONFIG0_WDT_STG3_Msk = 0x380000 + // Position of WDT_STG2 field. + LP_WDT_WDTCONFIG0_WDT_STG2_Pos = 0x16 + // Bit mask of WDT_STG2 field. + LP_WDT_WDTCONFIG0_WDT_STG2_Msk = 0x1c00000 + // Position of WDT_STG1 field. + LP_WDT_WDTCONFIG0_WDT_STG1_Pos = 0x19 + // Bit mask of WDT_STG1 field. + LP_WDT_WDTCONFIG0_WDT_STG1_Msk = 0xe000000 + // Position of WDT_STG0 field. + LP_WDT_WDTCONFIG0_WDT_STG0_Pos = 0x1c + // Bit mask of WDT_STG0 field. + LP_WDT_WDTCONFIG0_WDT_STG0_Msk = 0x70000000 + // Position of WDT_EN field. + LP_WDT_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + LP_WDT_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + LP_WDT_WDTCONFIG0_WDT_EN = 0x80000000 + + // CONFIG1: need_des + // Position of WDT_STG0_HOLD field. + LP_WDT_CONFIG1_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + LP_WDT_CONFIG1_WDT_STG0_HOLD_Msk = 0xffffffff + + // CONFIG2: need_des + // Position of WDT_STG1_HOLD field. + LP_WDT_CONFIG2_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + LP_WDT_CONFIG2_WDT_STG1_HOLD_Msk = 0xffffffff + + // CONFIG3: need_des + // Position of WDT_STG2_HOLD field. + LP_WDT_CONFIG3_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + LP_WDT_CONFIG3_WDT_STG2_HOLD_Msk = 0xffffffff + + // CONFIG4: need_des + // Position of WDT_STG3_HOLD field. + LP_WDT_CONFIG4_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + LP_WDT_CONFIG4_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: need_des + // Position of RTC_WDT_FEED field. + LP_WDT_WDTFEED_RTC_WDT_FEED_Pos = 0x1f + // Bit mask of RTC_WDT_FEED field. + LP_WDT_WDTFEED_RTC_WDT_FEED_Msk = 0x80000000 + // Bit RTC_WDT_FEED. + LP_WDT_WDTFEED_RTC_WDT_FEED = 0x80000000 + + // WDTWPROTECT: need_des + // Position of WDT_WKEY field. + LP_WDT_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + LP_WDT_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // SWD_CONF: need_des + // Position of SWD_RESET_FLAG field. + LP_WDT_SWD_CONF_SWD_RESET_FLAG_Pos = 0x0 + // Bit mask of SWD_RESET_FLAG field. + LP_WDT_SWD_CONF_SWD_RESET_FLAG_Msk = 0x1 + // Bit SWD_RESET_FLAG. + LP_WDT_SWD_CONF_SWD_RESET_FLAG = 0x1 + // Position of SWD_AUTO_FEED_EN field. + LP_WDT_SWD_CONF_SWD_AUTO_FEED_EN_Pos = 0x12 + // Bit mask of SWD_AUTO_FEED_EN field. + LP_WDT_SWD_CONF_SWD_AUTO_FEED_EN_Msk = 0x40000 + // Bit SWD_AUTO_FEED_EN. + LP_WDT_SWD_CONF_SWD_AUTO_FEED_EN = 0x40000 + // Position of SWD_RST_FLAG_CLR field. + LP_WDT_SWD_CONF_SWD_RST_FLAG_CLR_Pos = 0x13 + // Bit mask of SWD_RST_FLAG_CLR field. + LP_WDT_SWD_CONF_SWD_RST_FLAG_CLR_Msk = 0x80000 + // Bit SWD_RST_FLAG_CLR. + LP_WDT_SWD_CONF_SWD_RST_FLAG_CLR = 0x80000 + // Position of SWD_SIGNAL_WIDTH field. + LP_WDT_SWD_CONF_SWD_SIGNAL_WIDTH_Pos = 0x14 + // Bit mask of SWD_SIGNAL_WIDTH field. + LP_WDT_SWD_CONF_SWD_SIGNAL_WIDTH_Msk = 0x3ff00000 + // Position of SWD_DISABLE field. + LP_WDT_SWD_CONF_SWD_DISABLE_Pos = 0x1e + // Bit mask of SWD_DISABLE field. + LP_WDT_SWD_CONF_SWD_DISABLE_Msk = 0x40000000 + // Bit SWD_DISABLE. + LP_WDT_SWD_CONF_SWD_DISABLE = 0x40000000 + // Position of SWD_FEED field. + LP_WDT_SWD_CONF_SWD_FEED_Pos = 0x1f + // Bit mask of SWD_FEED field. + LP_WDT_SWD_CONF_SWD_FEED_Msk = 0x80000000 + // Bit SWD_FEED. + LP_WDT_SWD_CONF_SWD_FEED = 0x80000000 + + // SWD_WPROTECT: need_des + // Position of SWD_WKEY field. + LP_WDT_SWD_WPROTECT_SWD_WKEY_Pos = 0x0 + // Bit mask of SWD_WKEY field. + LP_WDT_SWD_WPROTECT_SWD_WKEY_Msk = 0xffffffff + + // INT_RAW: need_des + // Position of SUPER_WDT_INT_RAW field. + LP_WDT_INT_RAW_SUPER_WDT_INT_RAW_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_RAW field. + LP_WDT_INT_RAW_SUPER_WDT_INT_RAW_Msk = 0x40000000 + // Bit SUPER_WDT_INT_RAW. + LP_WDT_INT_RAW_SUPER_WDT_INT_RAW = 0x40000000 + // Position of LP_WDT_INT_RAW field. + LP_WDT_INT_RAW_LP_WDT_INT_RAW_Pos = 0x1f + // Bit mask of LP_WDT_INT_RAW field. + LP_WDT_INT_RAW_LP_WDT_INT_RAW_Msk = 0x80000000 + // Bit LP_WDT_INT_RAW. + LP_WDT_INT_RAW_LP_WDT_INT_RAW = 0x80000000 + + // INT_ST_RTC: need_des + // Position of SUPER_WDT_INT_ST field. + LP_WDT_INT_ST_RTC_SUPER_WDT_INT_ST_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_ST field. + LP_WDT_INT_ST_RTC_SUPER_WDT_INT_ST_Msk = 0x40000000 + // Bit SUPER_WDT_INT_ST. + LP_WDT_INT_ST_RTC_SUPER_WDT_INT_ST = 0x40000000 + // Position of WDT_INT_ST field. + LP_WDT_INT_ST_RTC_WDT_INT_ST_Pos = 0x1f + // Bit mask of WDT_INT_ST field. + LP_WDT_INT_ST_RTC_WDT_INT_ST_Msk = 0x80000000 + // Bit WDT_INT_ST. + LP_WDT_INT_ST_RTC_WDT_INT_ST = 0x80000000 + + // INT_ENA_RTC: need_des + // Position of SUPER_WDT_INT_ENA field. + LP_WDT_INT_ENA_RTC_SUPER_WDT_INT_ENA_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_ENA field. + LP_WDT_INT_ENA_RTC_SUPER_WDT_INT_ENA_Msk = 0x40000000 + // Bit SUPER_WDT_INT_ENA. + LP_WDT_INT_ENA_RTC_SUPER_WDT_INT_ENA = 0x40000000 + // Position of WDT_INT_ENA field. + LP_WDT_INT_ENA_RTC_WDT_INT_ENA_Pos = 0x1f + // Bit mask of WDT_INT_ENA field. + LP_WDT_INT_ENA_RTC_WDT_INT_ENA_Msk = 0x80000000 + // Bit WDT_INT_ENA. + LP_WDT_INT_ENA_RTC_WDT_INT_ENA = 0x80000000 + + // INT_CLR_RTC: need_des + // Position of SUPER_WDT_INT_CLR field. + LP_WDT_INT_CLR_RTC_SUPER_WDT_INT_CLR_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_CLR field. + LP_WDT_INT_CLR_RTC_SUPER_WDT_INT_CLR_Msk = 0x40000000 + // Bit SUPER_WDT_INT_CLR. + LP_WDT_INT_CLR_RTC_SUPER_WDT_INT_CLR = 0x40000000 + // Position of WDT_INT_CLR field. + LP_WDT_INT_CLR_RTC_WDT_INT_CLR_Pos = 0x1f + // Bit mask of WDT_INT_CLR field. + LP_WDT_INT_CLR_RTC_WDT_INT_CLR_Msk = 0x80000000 + // Bit WDT_INT_CLR. + LP_WDT_INT_CLR_RTC_WDT_INT_CLR = 0x80000000 + + // DATE: need_des + // Position of LP_WDT_DATE field. + LP_WDT_DATE_LP_WDT_DATE_Pos = 0x0 + // Bit mask of LP_WDT_DATE field. + LP_WDT_DATE_LP_WDT_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_WDT_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_WDT_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_WDT_DATE_CLK_EN = 0x80000000 +) + +// Constants for MCPWM0: Motor Control Pulse-Width Modulation 0 +const ( + // CLK_CFG: PWM clock prescaler register. + // Position of CLK_PRESCALE field. + MCPWM_CLK_CFG_CLK_PRESCALE_Pos = 0x0 + // Bit mask of CLK_PRESCALE field. + MCPWM_CLK_CFG_CLK_PRESCALE_Msk = 0xff + + // TIMER0_CFG0: PWM timer0 period and update method configuration register. + // Position of TIMER0_PRESCALE field. + MCPWM_TIMER0_CFG0_TIMER0_PRESCALE_Pos = 0x0 + // Bit mask of TIMER0_PRESCALE field. + MCPWM_TIMER0_CFG0_TIMER0_PRESCALE_Msk = 0xff + // Position of TIMER0_PERIOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_Pos = 0x8 + // Bit mask of TIMER0_PERIOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_Msk = 0xffff00 + // Position of TIMER0_PERIOD_UPMETHOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER0_PERIOD_UPMETHOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER0_CFG1: PWM timer0 working mode and start/stop control configuration register. + // Position of TIMER0_START field. + MCPWM_TIMER0_CFG1_TIMER0_START_Pos = 0x0 + // Bit mask of TIMER0_START field. + MCPWM_TIMER0_CFG1_TIMER0_START_Msk = 0x7 + // Position of TIMER0_MOD field. + MCPWM_TIMER0_CFG1_TIMER0_MOD_Pos = 0x3 + // Bit mask of TIMER0_MOD field. + MCPWM_TIMER0_CFG1_TIMER0_MOD_Msk = 0x18 + + // TIMER0_SYNC: PWM timer0 sync function configuration register. + // Position of TIMER0_SYNCI_EN field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER0_SYNCI_EN field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCI_EN_Msk = 0x1 + // Bit TIMER0_SYNCI_EN. + MCPWM_TIMER0_SYNC_TIMER0_SYNCI_EN = 0x1 + // Position of SW field. + MCPWM_TIMER0_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + MCPWM_TIMER0_SYNC_SW_Msk = 0x2 + // Bit SW. + MCPWM_TIMER0_SYNC_SW = 0x2 + // Position of TIMER0_SYNCO_SEL field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER0_SYNCO_SEL field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCO_SEL_Msk = 0xc + // Position of TIMER0_PHASE field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_Pos = 0x4 + // Bit mask of TIMER0_PHASE field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_Msk = 0xffff0 + // Position of TIMER0_PHASE_DIRECTION field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER0_PHASE_DIRECTION field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER0_PHASE_DIRECTION. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION = 0x100000 + + // TIMER0_STATUS: PWM timer0 status register. + // Position of TIMER0_VALUE field. + MCPWM_TIMER0_STATUS_TIMER0_VALUE_Pos = 0x0 + // Bit mask of TIMER0_VALUE field. + MCPWM_TIMER0_STATUS_TIMER0_VALUE_Msk = 0xffff + // Position of TIMER0_DIRECTION field. + MCPWM_TIMER0_STATUS_TIMER0_DIRECTION_Pos = 0x10 + // Bit mask of TIMER0_DIRECTION field. + MCPWM_TIMER0_STATUS_TIMER0_DIRECTION_Msk = 0x10000 + // Bit TIMER0_DIRECTION. + MCPWM_TIMER0_STATUS_TIMER0_DIRECTION = 0x10000 + + // TIMER1_CFG0: PWM timer1 period and update method configuration register. + // Position of TIMER1_PRESCALE field. + MCPWM_TIMER1_CFG0_TIMER1_PRESCALE_Pos = 0x0 + // Bit mask of TIMER1_PRESCALE field. + MCPWM_TIMER1_CFG0_TIMER1_PRESCALE_Msk = 0xff + // Position of TIMER1_PERIOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_Pos = 0x8 + // Bit mask of TIMER1_PERIOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_Msk = 0xffff00 + // Position of TIMER1_PERIOD_UPMETHOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER1_PERIOD_UPMETHOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER1_CFG1: PWM timer1 working mode and start/stop control configuration register. + // Position of TIMER1_START field. + MCPWM_TIMER1_CFG1_TIMER1_START_Pos = 0x0 + // Bit mask of TIMER1_START field. + MCPWM_TIMER1_CFG1_TIMER1_START_Msk = 0x7 + // Position of TIMER1_MOD field. + MCPWM_TIMER1_CFG1_TIMER1_MOD_Pos = 0x3 + // Bit mask of TIMER1_MOD field. + MCPWM_TIMER1_CFG1_TIMER1_MOD_Msk = 0x18 + + // TIMER1_SYNC: PWM timer1 sync function configuration register. + // Position of TIMER1_SYNCI_EN field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER1_SYNCI_EN field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCI_EN_Msk = 0x1 + // Bit TIMER1_SYNCI_EN. + MCPWM_TIMER1_SYNC_TIMER1_SYNCI_EN = 0x1 + // Position of SW field. + MCPWM_TIMER1_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + MCPWM_TIMER1_SYNC_SW_Msk = 0x2 + // Bit SW. + MCPWM_TIMER1_SYNC_SW = 0x2 + // Position of TIMER1_SYNCO_SEL field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER1_SYNCO_SEL field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCO_SEL_Msk = 0xc + // Position of TIMER1_PHASE field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_Pos = 0x4 + // Bit mask of TIMER1_PHASE field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_Msk = 0xffff0 + // Position of TIMER1_PHASE_DIRECTION field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER1_PHASE_DIRECTION field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER1_PHASE_DIRECTION. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION = 0x100000 + + // TIMER1_STATUS: PWM timer1 status register. + // Position of TIMER1_VALUE field. + MCPWM_TIMER1_STATUS_TIMER1_VALUE_Pos = 0x0 + // Bit mask of TIMER1_VALUE field. + MCPWM_TIMER1_STATUS_TIMER1_VALUE_Msk = 0xffff + // Position of TIMER1_DIRECTION field. + MCPWM_TIMER1_STATUS_TIMER1_DIRECTION_Pos = 0x10 + // Bit mask of TIMER1_DIRECTION field. + MCPWM_TIMER1_STATUS_TIMER1_DIRECTION_Msk = 0x10000 + // Bit TIMER1_DIRECTION. + MCPWM_TIMER1_STATUS_TIMER1_DIRECTION = 0x10000 + + // TIMER2_CFG0: PWM timer2 period and update method configuration register. + // Position of TIMER2_PRESCALE field. + MCPWM_TIMER2_CFG0_TIMER2_PRESCALE_Pos = 0x0 + // Bit mask of TIMER2_PRESCALE field. + MCPWM_TIMER2_CFG0_TIMER2_PRESCALE_Msk = 0xff + // Position of TIMER2_PERIOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_Pos = 0x8 + // Bit mask of TIMER2_PERIOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_Msk = 0xffff00 + // Position of TIMER2_PERIOD_UPMETHOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER2_PERIOD_UPMETHOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER2_CFG1: PWM timer2 working mode and start/stop control configuration register. + // Position of TIMER2_START field. + MCPWM_TIMER2_CFG1_TIMER2_START_Pos = 0x0 + // Bit mask of TIMER2_START field. + MCPWM_TIMER2_CFG1_TIMER2_START_Msk = 0x7 + // Position of TIMER2_MOD field. + MCPWM_TIMER2_CFG1_TIMER2_MOD_Pos = 0x3 + // Bit mask of TIMER2_MOD field. + MCPWM_TIMER2_CFG1_TIMER2_MOD_Msk = 0x18 + + // TIMER2_SYNC: PWM timer2 sync function configuration register. + // Position of TIMER2_SYNCI_EN field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER2_SYNCI_EN field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCI_EN_Msk = 0x1 + // Bit TIMER2_SYNCI_EN. + MCPWM_TIMER2_SYNC_TIMER2_SYNCI_EN = 0x1 + // Position of SW field. + MCPWM_TIMER2_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + MCPWM_TIMER2_SYNC_SW_Msk = 0x2 + // Bit SW. + MCPWM_TIMER2_SYNC_SW = 0x2 + // Position of TIMER2_SYNCO_SEL field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER2_SYNCO_SEL field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCO_SEL_Msk = 0xc + // Position of TIMER2_PHASE field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_Pos = 0x4 + // Bit mask of TIMER2_PHASE field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_Msk = 0xffff0 + // Position of TIMER2_PHASE_DIRECTION field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER2_PHASE_DIRECTION field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER2_PHASE_DIRECTION. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION = 0x100000 + + // TIMER2_STATUS: PWM timer2 status register. + // Position of TIMER2_VALUE field. + MCPWM_TIMER2_STATUS_TIMER2_VALUE_Pos = 0x0 + // Bit mask of TIMER2_VALUE field. + MCPWM_TIMER2_STATUS_TIMER2_VALUE_Msk = 0xffff + // Position of TIMER2_DIRECTION field. + MCPWM_TIMER2_STATUS_TIMER2_DIRECTION_Pos = 0x10 + // Bit mask of TIMER2_DIRECTION field. + MCPWM_TIMER2_STATUS_TIMER2_DIRECTION_Msk = 0x10000 + // Bit TIMER2_DIRECTION. + MCPWM_TIMER2_STATUS_TIMER2_DIRECTION = 0x10000 + + // TIMER_SYNCI_CFG: Synchronization input selection for three PWM timers. + // Position of TIMER0_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Pos = 0x0 + // Bit mask of TIMER0_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Msk = 0x7 + // Position of TIMER1_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Pos = 0x3 + // Bit mask of TIMER1_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Msk = 0x38 + // Position of TIMER2_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Pos = 0x6 + // Bit mask of TIMER2_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Msk = 0x1c0 + // Position of EXTERNAL_SYNCI0_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Pos = 0x9 + // Bit mask of EXTERNAL_SYNCI0_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Msk = 0x200 + // Bit EXTERNAL_SYNCI0_INVERT. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT = 0x200 + // Position of EXTERNAL_SYNCI1_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Pos = 0xa + // Bit mask of EXTERNAL_SYNCI1_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Msk = 0x400 + // Bit EXTERNAL_SYNCI1_INVERT. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT = 0x400 + // Position of EXTERNAL_SYNCI2_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Pos = 0xb + // Bit mask of EXTERNAL_SYNCI2_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Msk = 0x800 + // Bit EXTERNAL_SYNCI2_INVERT. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT = 0x800 + + // OPERATOR_TIMERSEL: Select specific timer for PWM operators. + // Position of OPERATOR0_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Pos = 0x0 + // Bit mask of OPERATOR0_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Msk = 0x3 + // Position of OPERATOR1_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Pos = 0x2 + // Bit mask of OPERATOR1_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Msk = 0xc + // Position of OPERATOR2_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Pos = 0x4 + // Bit mask of OPERATOR2_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Msk = 0x30 + + // GEN0_STMP_CFG: Transfer status and update method for time stamp registers A and B + // Position of CMPR0_A_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_CMPR0_A_UPMETHOD_Pos = 0x0 + // Bit mask of CMPR0_A_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_CMPR0_A_UPMETHOD_Msk = 0xf + // Position of CMPR0_B_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_CMPR0_B_UPMETHOD_Pos = 0x4 + // Bit mask of CMPR0_B_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_CMPR0_B_UPMETHOD_Msk = 0xf0 + // Position of CMPR0_A_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_CMPR0_A_SHDW_FULL_Pos = 0x8 + // Bit mask of CMPR0_A_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_CMPR0_A_SHDW_FULL_Msk = 0x100 + // Bit CMPR0_A_SHDW_FULL. + MCPWM_GEN0_STMP_CFG_CMPR0_A_SHDW_FULL = 0x100 + // Position of CMPR0_B_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_CMPR0_B_SHDW_FULL_Pos = 0x9 + // Bit mask of CMPR0_B_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_CMPR0_B_SHDW_FULL_Msk = 0x200 + // Bit CMPR0_B_SHDW_FULL. + MCPWM_GEN0_STMP_CFG_CMPR0_B_SHDW_FULL = 0x200 + + // GEN0_TSTMP_A: Shadow register for register A. + // Position of CMPR0_A field. + MCPWM_GEN0_TSTMP_A_CMPR0_A_Pos = 0x0 + // Bit mask of CMPR0_A field. + MCPWM_GEN0_TSTMP_A_CMPR0_A_Msk = 0xffff + + // GEN0_TSTMP_B: Shadow register for register B. + // Position of CMPR0_B field. + MCPWM_GEN0_TSTMP_B_CMPR0_B_Pos = 0x0 + // Bit mask of CMPR0_B field. + MCPWM_GEN0_TSTMP_B_CMPR0_B_Msk = 0xffff + + // GEN0_CFG0: Fault event T0 and T1 handling + // Position of GEN0_CFG_UPMETHOD field. + MCPWM_GEN0_CFG0_GEN0_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN0_CFG_UPMETHOD field. + MCPWM_GEN0_CFG0_GEN0_CFG_UPMETHOD_Msk = 0xf + // Position of GEN0_T0_SEL field. + MCPWM_GEN0_CFG0_GEN0_T0_SEL_Pos = 0x4 + // Bit mask of GEN0_T0_SEL field. + MCPWM_GEN0_CFG0_GEN0_T0_SEL_Msk = 0x70 + // Position of GEN0_T1_SEL field. + MCPWM_GEN0_CFG0_GEN0_T1_SEL_Pos = 0x7 + // Bit mask of GEN0_T1_SEL field. + MCPWM_GEN0_CFG0_GEN0_T1_SEL_Msk = 0x380 + + // GEN0_FORCE: Permissives to force PWM0A and PWM0B outputs by software + // Position of GEN0_CNTUFORCE_UPMETHOD field. + MCPWM_GEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN0_CNTUFORCE_UPMETHOD field. + MCPWM_GEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN0_A_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN0_A_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN0_B_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN0_B_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN0_A_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN0_A_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_Msk = 0x400 + // Bit GEN0_A_NCIFORCE. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE = 0x400 + // Position of GEN0_A_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN0_A_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN0_B_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN0_B_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_Msk = 0x2000 + // Bit GEN0_B_NCIFORCE. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE = 0x2000 + // Position of GEN0_B_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN0_B_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN0_A: Actions triggered by events on PWM0A + // Position of UTEZ field. + MCPWM_GEN0_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN0_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN0_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN0_A_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN0_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN0_A_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN0_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN0_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN0_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN0_A_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN0_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN0_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN0_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN0_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN0_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN0_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN0_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN0_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN0_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN0_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN0_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN0_A_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN0_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN0_A_DT1_Msk = 0xc00000 + + // GEN0_B: Actions triggered by events on PWM0B + // Position of UTEZ field. + MCPWM_GEN0_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN0_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN0_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN0_B_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN0_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN0_B_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN0_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN0_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN0_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN0_B_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN0_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN0_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN0_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN0_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN0_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN0_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN0_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN0_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN0_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN0_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN0_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN0_B_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN0_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN0_B_DT1_Msk = 0xc00000 + + // DT0_CFG: dead time type selection and configuration + // Position of DB0_FED_UPMETHOD field. + MCPWM_DT0_CFG_DB0_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DB0_FED_UPMETHOD field. + MCPWM_DT0_CFG_DB0_FED_UPMETHOD_Msk = 0xf + // Position of DB0_RED_UPMETHOD field. + MCPWM_DT0_CFG_DB0_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DB0_RED_UPMETHOD field. + MCPWM_DT0_CFG_DB0_RED_UPMETHOD_Msk = 0xf0 + // Position of DB0_DEB_MODE field. + MCPWM_DT0_CFG_DB0_DEB_MODE_Pos = 0x8 + // Bit mask of DB0_DEB_MODE field. + MCPWM_DT0_CFG_DB0_DEB_MODE_Msk = 0x100 + // Bit DB0_DEB_MODE. + MCPWM_DT0_CFG_DB0_DEB_MODE = 0x100 + // Position of DB0_A_OUTSWAP field. + MCPWM_DT0_CFG_DB0_A_OUTSWAP_Pos = 0x9 + // Bit mask of DB0_A_OUTSWAP field. + MCPWM_DT0_CFG_DB0_A_OUTSWAP_Msk = 0x200 + // Bit DB0_A_OUTSWAP. + MCPWM_DT0_CFG_DB0_A_OUTSWAP = 0x200 + // Position of DB0_B_OUTSWAP field. + MCPWM_DT0_CFG_DB0_B_OUTSWAP_Pos = 0xa + // Bit mask of DB0_B_OUTSWAP field. + MCPWM_DT0_CFG_DB0_B_OUTSWAP_Msk = 0x400 + // Bit DB0_B_OUTSWAP. + MCPWM_DT0_CFG_DB0_B_OUTSWAP = 0x400 + // Position of DB0_RED_INSEL field. + MCPWM_DT0_CFG_DB0_RED_INSEL_Pos = 0xb + // Bit mask of DB0_RED_INSEL field. + MCPWM_DT0_CFG_DB0_RED_INSEL_Msk = 0x800 + // Bit DB0_RED_INSEL. + MCPWM_DT0_CFG_DB0_RED_INSEL = 0x800 + // Position of DB0_FED_INSEL field. + MCPWM_DT0_CFG_DB0_FED_INSEL_Pos = 0xc + // Bit mask of DB0_FED_INSEL field. + MCPWM_DT0_CFG_DB0_FED_INSEL_Msk = 0x1000 + // Bit DB0_FED_INSEL. + MCPWM_DT0_CFG_DB0_FED_INSEL = 0x1000 + // Position of DB0_RED_OUTINVERT field. + MCPWM_DT0_CFG_DB0_RED_OUTINVERT_Pos = 0xd + // Bit mask of DB0_RED_OUTINVERT field. + MCPWM_DT0_CFG_DB0_RED_OUTINVERT_Msk = 0x2000 + // Bit DB0_RED_OUTINVERT. + MCPWM_DT0_CFG_DB0_RED_OUTINVERT = 0x2000 + // Position of DB0_FED_OUTINVERT field. + MCPWM_DT0_CFG_DB0_FED_OUTINVERT_Pos = 0xe + // Bit mask of DB0_FED_OUTINVERT field. + MCPWM_DT0_CFG_DB0_FED_OUTINVERT_Msk = 0x4000 + // Bit DB0_FED_OUTINVERT. + MCPWM_DT0_CFG_DB0_FED_OUTINVERT = 0x4000 + // Position of DB0_A_OUTBYPASS field. + MCPWM_DT0_CFG_DB0_A_OUTBYPASS_Pos = 0xf + // Bit mask of DB0_A_OUTBYPASS field. + MCPWM_DT0_CFG_DB0_A_OUTBYPASS_Msk = 0x8000 + // Bit DB0_A_OUTBYPASS. + MCPWM_DT0_CFG_DB0_A_OUTBYPASS = 0x8000 + // Position of DB0_B_OUTBYPASS field. + MCPWM_DT0_CFG_DB0_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DB0_B_OUTBYPASS field. + MCPWM_DT0_CFG_DB0_B_OUTBYPASS_Msk = 0x10000 + // Bit DB0_B_OUTBYPASS. + MCPWM_DT0_CFG_DB0_B_OUTBYPASS = 0x10000 + // Position of DB0_CLK_SEL field. + MCPWM_DT0_CFG_DB0_CLK_SEL_Pos = 0x11 + // Bit mask of DB0_CLK_SEL field. + MCPWM_DT0_CFG_DB0_CLK_SEL_Msk = 0x20000 + // Bit DB0_CLK_SEL. + MCPWM_DT0_CFG_DB0_CLK_SEL = 0x20000 + + // DT0_FED_CFG: Shadow register for falling edge delay (FED). + // Position of DB0_FED field. + MCPWM_DT0_FED_CFG_DB0_FED_Pos = 0x0 + // Bit mask of DB0_FED field. + MCPWM_DT0_FED_CFG_DB0_FED_Msk = 0xffff + + // DT0_RED_CFG: Shadow register for rising edge delay (RED). + // Position of DB0_RED field. + MCPWM_DT0_RED_CFG_DB0_RED_Pos = 0x0 + // Bit mask of DB0_RED field. + MCPWM_DT0_RED_CFG_DB0_RED_Msk = 0xffff + + // CARRIER0_CFG: Carrier enable and configuratoin + // Position of CHOPPER0_EN field. + MCPWM_CARRIER0_CFG_CHOPPER0_EN_Pos = 0x0 + // Bit mask of CHOPPER0_EN field. + MCPWM_CARRIER0_CFG_CHOPPER0_EN_Msk = 0x1 + // Bit CHOPPER0_EN. + MCPWM_CARRIER0_CFG_CHOPPER0_EN = 0x1 + // Position of CHOPPER0_PRESCALE field. + MCPWM_CARRIER0_CFG_CHOPPER0_PRESCALE_Pos = 0x1 + // Bit mask of CHOPPER0_PRESCALE field. + MCPWM_CARRIER0_CFG_CHOPPER0_PRESCALE_Msk = 0x1e + // Position of CHOPPER0_DUTY field. + MCPWM_CARRIER0_CFG_CHOPPER0_DUTY_Pos = 0x5 + // Bit mask of CHOPPER0_DUTY field. + MCPWM_CARRIER0_CFG_CHOPPER0_DUTY_Msk = 0xe0 + // Position of CHOPPER0_OSHTWTH field. + MCPWM_CARRIER0_CFG_CHOPPER0_OSHTWTH_Pos = 0x8 + // Bit mask of CHOPPER0_OSHTWTH field. + MCPWM_CARRIER0_CFG_CHOPPER0_OSHTWTH_Msk = 0xf00 + // Position of CHOPPER0_OUT_INVERT field. + MCPWM_CARRIER0_CFG_CHOPPER0_OUT_INVERT_Pos = 0xc + // Bit mask of CHOPPER0_OUT_INVERT field. + MCPWM_CARRIER0_CFG_CHOPPER0_OUT_INVERT_Msk = 0x1000 + // Bit CHOPPER0_OUT_INVERT. + MCPWM_CARRIER0_CFG_CHOPPER0_OUT_INVERT = 0x1000 + // Position of CHOPPER0_IN_INVERT field. + MCPWM_CARRIER0_CFG_CHOPPER0_IN_INVERT_Pos = 0xd + // Bit mask of CHOPPER0_IN_INVERT field. + MCPWM_CARRIER0_CFG_CHOPPER0_IN_INVERT_Msk = 0x2000 + // Bit CHOPPER0_IN_INVERT. + MCPWM_CARRIER0_CFG_CHOPPER0_IN_INVERT = 0x2000 + + // FH0_CFG0: Actions on PWM0A and PWM0B trip events + // Position of TZ0_SW_CBC field. + MCPWM_FH0_CFG0_TZ0_SW_CBC_Pos = 0x0 + // Bit mask of TZ0_SW_CBC field. + MCPWM_FH0_CFG0_TZ0_SW_CBC_Msk = 0x1 + // Bit TZ0_SW_CBC. + MCPWM_FH0_CFG0_TZ0_SW_CBC = 0x1 + // Position of TZ0_F2_CBC field. + MCPWM_FH0_CFG0_TZ0_F2_CBC_Pos = 0x1 + // Bit mask of TZ0_F2_CBC field. + MCPWM_FH0_CFG0_TZ0_F2_CBC_Msk = 0x2 + // Bit TZ0_F2_CBC. + MCPWM_FH0_CFG0_TZ0_F2_CBC = 0x2 + // Position of TZ0_F1_CBC field. + MCPWM_FH0_CFG0_TZ0_F1_CBC_Pos = 0x2 + // Bit mask of TZ0_F1_CBC field. + MCPWM_FH0_CFG0_TZ0_F1_CBC_Msk = 0x4 + // Bit TZ0_F1_CBC. + MCPWM_FH0_CFG0_TZ0_F1_CBC = 0x4 + // Position of TZ0_F0_CBC field. + MCPWM_FH0_CFG0_TZ0_F0_CBC_Pos = 0x3 + // Bit mask of TZ0_F0_CBC field. + MCPWM_FH0_CFG0_TZ0_F0_CBC_Msk = 0x8 + // Bit TZ0_F0_CBC. + MCPWM_FH0_CFG0_TZ0_F0_CBC = 0x8 + // Position of TZ0_SW_OST field. + MCPWM_FH0_CFG0_TZ0_SW_OST_Pos = 0x4 + // Bit mask of TZ0_SW_OST field. + MCPWM_FH0_CFG0_TZ0_SW_OST_Msk = 0x10 + // Bit TZ0_SW_OST. + MCPWM_FH0_CFG0_TZ0_SW_OST = 0x10 + // Position of TZ0_F2_OST field. + MCPWM_FH0_CFG0_TZ0_F2_OST_Pos = 0x5 + // Bit mask of TZ0_F2_OST field. + MCPWM_FH0_CFG0_TZ0_F2_OST_Msk = 0x20 + // Bit TZ0_F2_OST. + MCPWM_FH0_CFG0_TZ0_F2_OST = 0x20 + // Position of TZ0_F1_OST field. + MCPWM_FH0_CFG0_TZ0_F1_OST_Pos = 0x6 + // Bit mask of TZ0_F1_OST field. + MCPWM_FH0_CFG0_TZ0_F1_OST_Msk = 0x40 + // Bit TZ0_F1_OST. + MCPWM_FH0_CFG0_TZ0_F1_OST = 0x40 + // Position of TZ0_F0_OST field. + MCPWM_FH0_CFG0_TZ0_F0_OST_Pos = 0x7 + // Bit mask of TZ0_F0_OST field. + MCPWM_FH0_CFG0_TZ0_F0_OST_Msk = 0x80 + // Bit TZ0_F0_OST. + MCPWM_FH0_CFG0_TZ0_F0_OST = 0x80 + // Position of TZ0_A_CBC_D field. + MCPWM_FH0_CFG0_TZ0_A_CBC_D_Pos = 0x8 + // Bit mask of TZ0_A_CBC_D field. + MCPWM_FH0_CFG0_TZ0_A_CBC_D_Msk = 0x300 + // Position of TZ0_A_CBC_U field. + MCPWM_FH0_CFG0_TZ0_A_CBC_U_Pos = 0xa + // Bit mask of TZ0_A_CBC_U field. + MCPWM_FH0_CFG0_TZ0_A_CBC_U_Msk = 0xc00 + // Position of TZ0_A_OST_D field. + MCPWM_FH0_CFG0_TZ0_A_OST_D_Pos = 0xc + // Bit mask of TZ0_A_OST_D field. + MCPWM_FH0_CFG0_TZ0_A_OST_D_Msk = 0x3000 + // Position of TZ0_A_OST_U field. + MCPWM_FH0_CFG0_TZ0_A_OST_U_Pos = 0xe + // Bit mask of TZ0_A_OST_U field. + MCPWM_FH0_CFG0_TZ0_A_OST_U_Msk = 0xc000 + // Position of TZ0_B_CBC_D field. + MCPWM_FH0_CFG0_TZ0_B_CBC_D_Pos = 0x10 + // Bit mask of TZ0_B_CBC_D field. + MCPWM_FH0_CFG0_TZ0_B_CBC_D_Msk = 0x30000 + // Position of TZ0_B_CBC_U field. + MCPWM_FH0_CFG0_TZ0_B_CBC_U_Pos = 0x12 + // Bit mask of TZ0_B_CBC_U field. + MCPWM_FH0_CFG0_TZ0_B_CBC_U_Msk = 0xc0000 + // Position of TZ0_B_OST_D field. + MCPWM_FH0_CFG0_TZ0_B_OST_D_Pos = 0x14 + // Bit mask of TZ0_B_OST_D field. + MCPWM_FH0_CFG0_TZ0_B_OST_D_Msk = 0x300000 + // Position of TZ0_B_OST_U field. + MCPWM_FH0_CFG0_TZ0_B_OST_U_Pos = 0x16 + // Bit mask of TZ0_B_OST_U field. + MCPWM_FH0_CFG0_TZ0_B_OST_U_Msk = 0xc00000 + + // FH0_CFG1: Software triggers for fault handler actions + // Position of TZ0_CLR_OST field. + MCPWM_FH0_CFG1_TZ0_CLR_OST_Pos = 0x0 + // Bit mask of TZ0_CLR_OST field. + MCPWM_FH0_CFG1_TZ0_CLR_OST_Msk = 0x1 + // Bit TZ0_CLR_OST. + MCPWM_FH0_CFG1_TZ0_CLR_OST = 0x1 + // Position of TZ0_CBCPULSE field. + MCPWM_FH0_CFG1_TZ0_CBCPULSE_Pos = 0x1 + // Bit mask of TZ0_CBCPULSE field. + MCPWM_FH0_CFG1_TZ0_CBCPULSE_Msk = 0x6 + // Position of TZ0_FORCE_CBC field. + MCPWM_FH0_CFG1_TZ0_FORCE_CBC_Pos = 0x3 + // Bit mask of TZ0_FORCE_CBC field. + MCPWM_FH0_CFG1_TZ0_FORCE_CBC_Msk = 0x8 + // Bit TZ0_FORCE_CBC. + MCPWM_FH0_CFG1_TZ0_FORCE_CBC = 0x8 + // Position of TZ0_FORCE_OST field. + MCPWM_FH0_CFG1_TZ0_FORCE_OST_Pos = 0x4 + // Bit mask of TZ0_FORCE_OST field. + MCPWM_FH0_CFG1_TZ0_FORCE_OST_Msk = 0x10 + // Bit TZ0_FORCE_OST. + MCPWM_FH0_CFG1_TZ0_FORCE_OST = 0x10 + + // FH0_STATUS: Status of fault events. + // Position of TZ0_CBC_ON field. + MCPWM_FH0_STATUS_TZ0_CBC_ON_Pos = 0x0 + // Bit mask of TZ0_CBC_ON field. + MCPWM_FH0_STATUS_TZ0_CBC_ON_Msk = 0x1 + // Bit TZ0_CBC_ON. + MCPWM_FH0_STATUS_TZ0_CBC_ON = 0x1 + // Position of TZ0_OST_ON field. + MCPWM_FH0_STATUS_TZ0_OST_ON_Pos = 0x1 + // Bit mask of TZ0_OST_ON field. + MCPWM_FH0_STATUS_TZ0_OST_ON_Msk = 0x2 + // Bit TZ0_OST_ON. + MCPWM_FH0_STATUS_TZ0_OST_ON = 0x2 + + // GEN1_STMP_CFG: Transfer status and update method for time stamp registers A and B + // Position of CMPR1_A_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_CMPR1_A_UPMETHOD_Pos = 0x0 + // Bit mask of CMPR1_A_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_CMPR1_A_UPMETHOD_Msk = 0xf + // Position of CMPR1_B_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_CMPR1_B_UPMETHOD_Pos = 0x4 + // Bit mask of CMPR1_B_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_CMPR1_B_UPMETHOD_Msk = 0xf0 + // Position of CMPR1_A_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_CMPR1_A_SHDW_FULL_Pos = 0x8 + // Bit mask of CMPR1_A_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_CMPR1_A_SHDW_FULL_Msk = 0x100 + // Bit CMPR1_A_SHDW_FULL. + MCPWM_GEN1_STMP_CFG_CMPR1_A_SHDW_FULL = 0x100 + // Position of CMPR1_B_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_CMPR1_B_SHDW_FULL_Pos = 0x9 + // Bit mask of CMPR1_B_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_CMPR1_B_SHDW_FULL_Msk = 0x200 + // Bit CMPR1_B_SHDW_FULL. + MCPWM_GEN1_STMP_CFG_CMPR1_B_SHDW_FULL = 0x200 + + // GEN1_TSTMP_A: Shadow register for register A. + // Position of CMPR1_A field. + MCPWM_GEN1_TSTMP_A_CMPR1_A_Pos = 0x0 + // Bit mask of CMPR1_A field. + MCPWM_GEN1_TSTMP_A_CMPR1_A_Msk = 0xffff + + // GEN1_TSTMP_B: Shadow register for register B. + // Position of CMPR1_B field. + MCPWM_GEN1_TSTMP_B_CMPR1_B_Pos = 0x0 + // Bit mask of CMPR1_B field. + MCPWM_GEN1_TSTMP_B_CMPR1_B_Msk = 0xffff + + // GEN1_CFG0: Fault event T0 and T1 handling + // Position of GEN1_CFG_UPMETHOD field. + MCPWM_GEN1_CFG0_GEN1_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN1_CFG_UPMETHOD field. + MCPWM_GEN1_CFG0_GEN1_CFG_UPMETHOD_Msk = 0xf + // Position of GEN1_T0_SEL field. + MCPWM_GEN1_CFG0_GEN1_T0_SEL_Pos = 0x4 + // Bit mask of GEN1_T0_SEL field. + MCPWM_GEN1_CFG0_GEN1_T0_SEL_Msk = 0x70 + // Position of GEN1_T1_SEL field. + MCPWM_GEN1_CFG0_GEN1_T1_SEL_Pos = 0x7 + // Bit mask of GEN1_T1_SEL field. + MCPWM_GEN1_CFG0_GEN1_T1_SEL_Msk = 0x380 + + // GEN1_FORCE: Permissives to force PWM1A and PWM1B outputs by software + // Position of GEN1_CNTUFORCE_UPMETHOD field. + MCPWM_GEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN1_CNTUFORCE_UPMETHOD field. + MCPWM_GEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN1_A_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN1_A_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN1_B_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN1_B_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN1_A_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN1_A_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_Msk = 0x400 + // Bit GEN1_A_NCIFORCE. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE = 0x400 + // Position of GEN1_A_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN1_A_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN1_B_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN1_B_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_Msk = 0x2000 + // Bit GEN1_B_NCIFORCE. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE = 0x2000 + // Position of GEN1_B_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN1_B_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN1_A: Actions triggered by events on PWM1A + // Position of UTEZ field. + MCPWM_GEN1_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN1_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN1_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN1_A_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN1_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN1_A_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN1_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN1_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN1_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN1_A_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN1_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN1_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN1_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN1_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN1_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN1_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN1_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN1_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN1_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN1_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN1_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN1_A_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN1_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN1_A_DT1_Msk = 0xc00000 + + // GEN1_B: Actions triggered by events on PWM1B + // Position of UTEZ field. + MCPWM_GEN1_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN1_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN1_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN1_B_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN1_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN1_B_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN1_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN1_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN1_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN1_B_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN1_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN1_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN1_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN1_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN1_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN1_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN1_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN1_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN1_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN1_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN1_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN1_B_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN1_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN1_B_DT1_Msk = 0xc00000 + + // DT1_CFG: dead time type selection and configuration + // Position of DB1_FED_UPMETHOD field. + MCPWM_DT1_CFG_DB1_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DB1_FED_UPMETHOD field. + MCPWM_DT1_CFG_DB1_FED_UPMETHOD_Msk = 0xf + // Position of DB1_RED_UPMETHOD field. + MCPWM_DT1_CFG_DB1_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DB1_RED_UPMETHOD field. + MCPWM_DT1_CFG_DB1_RED_UPMETHOD_Msk = 0xf0 + // Position of DB1_DEB_MODE field. + MCPWM_DT1_CFG_DB1_DEB_MODE_Pos = 0x8 + // Bit mask of DB1_DEB_MODE field. + MCPWM_DT1_CFG_DB1_DEB_MODE_Msk = 0x100 + // Bit DB1_DEB_MODE. + MCPWM_DT1_CFG_DB1_DEB_MODE = 0x100 + // Position of DB1_A_OUTSWAP field. + MCPWM_DT1_CFG_DB1_A_OUTSWAP_Pos = 0x9 + // Bit mask of DB1_A_OUTSWAP field. + MCPWM_DT1_CFG_DB1_A_OUTSWAP_Msk = 0x200 + // Bit DB1_A_OUTSWAP. + MCPWM_DT1_CFG_DB1_A_OUTSWAP = 0x200 + // Position of DB1_B_OUTSWAP field. + MCPWM_DT1_CFG_DB1_B_OUTSWAP_Pos = 0xa + // Bit mask of DB1_B_OUTSWAP field. + MCPWM_DT1_CFG_DB1_B_OUTSWAP_Msk = 0x400 + // Bit DB1_B_OUTSWAP. + MCPWM_DT1_CFG_DB1_B_OUTSWAP = 0x400 + // Position of DB1_RED_INSEL field. + MCPWM_DT1_CFG_DB1_RED_INSEL_Pos = 0xb + // Bit mask of DB1_RED_INSEL field. + MCPWM_DT1_CFG_DB1_RED_INSEL_Msk = 0x800 + // Bit DB1_RED_INSEL. + MCPWM_DT1_CFG_DB1_RED_INSEL = 0x800 + // Position of DB1_FED_INSEL field. + MCPWM_DT1_CFG_DB1_FED_INSEL_Pos = 0xc + // Bit mask of DB1_FED_INSEL field. + MCPWM_DT1_CFG_DB1_FED_INSEL_Msk = 0x1000 + // Bit DB1_FED_INSEL. + MCPWM_DT1_CFG_DB1_FED_INSEL = 0x1000 + // Position of DB1_RED_OUTINVERT field. + MCPWM_DT1_CFG_DB1_RED_OUTINVERT_Pos = 0xd + // Bit mask of DB1_RED_OUTINVERT field. + MCPWM_DT1_CFG_DB1_RED_OUTINVERT_Msk = 0x2000 + // Bit DB1_RED_OUTINVERT. + MCPWM_DT1_CFG_DB1_RED_OUTINVERT = 0x2000 + // Position of DB1_FED_OUTINVERT field. + MCPWM_DT1_CFG_DB1_FED_OUTINVERT_Pos = 0xe + // Bit mask of DB1_FED_OUTINVERT field. + MCPWM_DT1_CFG_DB1_FED_OUTINVERT_Msk = 0x4000 + // Bit DB1_FED_OUTINVERT. + MCPWM_DT1_CFG_DB1_FED_OUTINVERT = 0x4000 + // Position of DB1_A_OUTBYPASS field. + MCPWM_DT1_CFG_DB1_A_OUTBYPASS_Pos = 0xf + // Bit mask of DB1_A_OUTBYPASS field. + MCPWM_DT1_CFG_DB1_A_OUTBYPASS_Msk = 0x8000 + // Bit DB1_A_OUTBYPASS. + MCPWM_DT1_CFG_DB1_A_OUTBYPASS = 0x8000 + // Position of DB1_B_OUTBYPASS field. + MCPWM_DT1_CFG_DB1_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DB1_B_OUTBYPASS field. + MCPWM_DT1_CFG_DB1_B_OUTBYPASS_Msk = 0x10000 + // Bit DB1_B_OUTBYPASS. + MCPWM_DT1_CFG_DB1_B_OUTBYPASS = 0x10000 + // Position of DB1_CLK_SEL field. + MCPWM_DT1_CFG_DB1_CLK_SEL_Pos = 0x11 + // Bit mask of DB1_CLK_SEL field. + MCPWM_DT1_CFG_DB1_CLK_SEL_Msk = 0x20000 + // Bit DB1_CLK_SEL. + MCPWM_DT1_CFG_DB1_CLK_SEL = 0x20000 + + // DT1_FED_CFG: Shadow register for falling edge delay (FED). + // Position of DB1_FED field. + MCPWM_DT1_FED_CFG_DB1_FED_Pos = 0x0 + // Bit mask of DB1_FED field. + MCPWM_DT1_FED_CFG_DB1_FED_Msk = 0xffff + + // DT1_RED_CFG: Shadow register for rising edge delay (RED). + // Position of DB1_RED field. + MCPWM_DT1_RED_CFG_DB1_RED_Pos = 0x0 + // Bit mask of DB1_RED field. + MCPWM_DT1_RED_CFG_DB1_RED_Msk = 0xffff + + // CARRIER1_CFG: Carrier enable and configuratoin + // Position of CHOPPER1_EN field. + MCPWM_CARRIER1_CFG_CHOPPER1_EN_Pos = 0x0 + // Bit mask of CHOPPER1_EN field. + MCPWM_CARRIER1_CFG_CHOPPER1_EN_Msk = 0x1 + // Bit CHOPPER1_EN. + MCPWM_CARRIER1_CFG_CHOPPER1_EN = 0x1 + // Position of CHOPPER1_PRESCALE field. + MCPWM_CARRIER1_CFG_CHOPPER1_PRESCALE_Pos = 0x1 + // Bit mask of CHOPPER1_PRESCALE field. + MCPWM_CARRIER1_CFG_CHOPPER1_PRESCALE_Msk = 0x1e + // Position of CHOPPER1_DUTY field. + MCPWM_CARRIER1_CFG_CHOPPER1_DUTY_Pos = 0x5 + // Bit mask of CHOPPER1_DUTY field. + MCPWM_CARRIER1_CFG_CHOPPER1_DUTY_Msk = 0xe0 + // Position of CHOPPER1_OSHTWTH field. + MCPWM_CARRIER1_CFG_CHOPPER1_OSHTWTH_Pos = 0x8 + // Bit mask of CHOPPER1_OSHTWTH field. + MCPWM_CARRIER1_CFG_CHOPPER1_OSHTWTH_Msk = 0xf00 + // Position of CHOPPER1_OUT_INVERT field. + MCPWM_CARRIER1_CFG_CHOPPER1_OUT_INVERT_Pos = 0xc + // Bit mask of CHOPPER1_OUT_INVERT field. + MCPWM_CARRIER1_CFG_CHOPPER1_OUT_INVERT_Msk = 0x1000 + // Bit CHOPPER1_OUT_INVERT. + MCPWM_CARRIER1_CFG_CHOPPER1_OUT_INVERT = 0x1000 + // Position of CHOPPER1_IN_INVERT field. + MCPWM_CARRIER1_CFG_CHOPPER1_IN_INVERT_Pos = 0xd + // Bit mask of CHOPPER1_IN_INVERT field. + MCPWM_CARRIER1_CFG_CHOPPER1_IN_INVERT_Msk = 0x2000 + // Bit CHOPPER1_IN_INVERT. + MCPWM_CARRIER1_CFG_CHOPPER1_IN_INVERT = 0x2000 + + // FH1_CFG0: Actions on PWM1A and PWM1B trip events + // Position of TZ1_SW_CBC field. + MCPWM_FH1_CFG0_TZ1_SW_CBC_Pos = 0x0 + // Bit mask of TZ1_SW_CBC field. + MCPWM_FH1_CFG0_TZ1_SW_CBC_Msk = 0x1 + // Bit TZ1_SW_CBC. + MCPWM_FH1_CFG0_TZ1_SW_CBC = 0x1 + // Position of TZ1_F2_CBC field. + MCPWM_FH1_CFG0_TZ1_F2_CBC_Pos = 0x1 + // Bit mask of TZ1_F2_CBC field. + MCPWM_FH1_CFG0_TZ1_F2_CBC_Msk = 0x2 + // Bit TZ1_F2_CBC. + MCPWM_FH1_CFG0_TZ1_F2_CBC = 0x2 + // Position of TZ1_F1_CBC field. + MCPWM_FH1_CFG0_TZ1_F1_CBC_Pos = 0x2 + // Bit mask of TZ1_F1_CBC field. + MCPWM_FH1_CFG0_TZ1_F1_CBC_Msk = 0x4 + // Bit TZ1_F1_CBC. + MCPWM_FH1_CFG0_TZ1_F1_CBC = 0x4 + // Position of TZ1_F0_CBC field. + MCPWM_FH1_CFG0_TZ1_F0_CBC_Pos = 0x3 + // Bit mask of TZ1_F0_CBC field. + MCPWM_FH1_CFG0_TZ1_F0_CBC_Msk = 0x8 + // Bit TZ1_F0_CBC. + MCPWM_FH1_CFG0_TZ1_F0_CBC = 0x8 + // Position of TZ1_SW_OST field. + MCPWM_FH1_CFG0_TZ1_SW_OST_Pos = 0x4 + // Bit mask of TZ1_SW_OST field. + MCPWM_FH1_CFG0_TZ1_SW_OST_Msk = 0x10 + // Bit TZ1_SW_OST. + MCPWM_FH1_CFG0_TZ1_SW_OST = 0x10 + // Position of TZ1_F2_OST field. + MCPWM_FH1_CFG0_TZ1_F2_OST_Pos = 0x5 + // Bit mask of TZ1_F2_OST field. + MCPWM_FH1_CFG0_TZ1_F2_OST_Msk = 0x20 + // Bit TZ1_F2_OST. + MCPWM_FH1_CFG0_TZ1_F2_OST = 0x20 + // Position of TZ1_F1_OST field. + MCPWM_FH1_CFG0_TZ1_F1_OST_Pos = 0x6 + // Bit mask of TZ1_F1_OST field. + MCPWM_FH1_CFG0_TZ1_F1_OST_Msk = 0x40 + // Bit TZ1_F1_OST. + MCPWM_FH1_CFG0_TZ1_F1_OST = 0x40 + // Position of TZ1_F0_OST field. + MCPWM_FH1_CFG0_TZ1_F0_OST_Pos = 0x7 + // Bit mask of TZ1_F0_OST field. + MCPWM_FH1_CFG0_TZ1_F0_OST_Msk = 0x80 + // Bit TZ1_F0_OST. + MCPWM_FH1_CFG0_TZ1_F0_OST = 0x80 + // Position of TZ1_A_CBC_D field. + MCPWM_FH1_CFG0_TZ1_A_CBC_D_Pos = 0x8 + // Bit mask of TZ1_A_CBC_D field. + MCPWM_FH1_CFG0_TZ1_A_CBC_D_Msk = 0x300 + // Position of TZ1_A_CBC_U field. + MCPWM_FH1_CFG0_TZ1_A_CBC_U_Pos = 0xa + // Bit mask of TZ1_A_CBC_U field. + MCPWM_FH1_CFG0_TZ1_A_CBC_U_Msk = 0xc00 + // Position of TZ1_A_OST_D field. + MCPWM_FH1_CFG0_TZ1_A_OST_D_Pos = 0xc + // Bit mask of TZ1_A_OST_D field. + MCPWM_FH1_CFG0_TZ1_A_OST_D_Msk = 0x3000 + // Position of TZ1_A_OST_U field. + MCPWM_FH1_CFG0_TZ1_A_OST_U_Pos = 0xe + // Bit mask of TZ1_A_OST_U field. + MCPWM_FH1_CFG0_TZ1_A_OST_U_Msk = 0xc000 + // Position of TZ1_B_CBC_D field. + MCPWM_FH1_CFG0_TZ1_B_CBC_D_Pos = 0x10 + // Bit mask of TZ1_B_CBC_D field. + MCPWM_FH1_CFG0_TZ1_B_CBC_D_Msk = 0x30000 + // Position of TZ1_B_CBC_U field. + MCPWM_FH1_CFG0_TZ1_B_CBC_U_Pos = 0x12 + // Bit mask of TZ1_B_CBC_U field. + MCPWM_FH1_CFG0_TZ1_B_CBC_U_Msk = 0xc0000 + // Position of TZ1_B_OST_D field. + MCPWM_FH1_CFG0_TZ1_B_OST_D_Pos = 0x14 + // Bit mask of TZ1_B_OST_D field. + MCPWM_FH1_CFG0_TZ1_B_OST_D_Msk = 0x300000 + // Position of TZ1_B_OST_U field. + MCPWM_FH1_CFG0_TZ1_B_OST_U_Pos = 0x16 + // Bit mask of TZ1_B_OST_U field. + MCPWM_FH1_CFG0_TZ1_B_OST_U_Msk = 0xc00000 + + // FH1_CFG1: Software triggers for fault handler actions + // Position of TZ1_CLR_OST field. + MCPWM_FH1_CFG1_TZ1_CLR_OST_Pos = 0x0 + // Bit mask of TZ1_CLR_OST field. + MCPWM_FH1_CFG1_TZ1_CLR_OST_Msk = 0x1 + // Bit TZ1_CLR_OST. + MCPWM_FH1_CFG1_TZ1_CLR_OST = 0x1 + // Position of TZ1_CBCPULSE field. + MCPWM_FH1_CFG1_TZ1_CBCPULSE_Pos = 0x1 + // Bit mask of TZ1_CBCPULSE field. + MCPWM_FH1_CFG1_TZ1_CBCPULSE_Msk = 0x6 + // Position of TZ1_FORCE_CBC field. + MCPWM_FH1_CFG1_TZ1_FORCE_CBC_Pos = 0x3 + // Bit mask of TZ1_FORCE_CBC field. + MCPWM_FH1_CFG1_TZ1_FORCE_CBC_Msk = 0x8 + // Bit TZ1_FORCE_CBC. + MCPWM_FH1_CFG1_TZ1_FORCE_CBC = 0x8 + // Position of TZ1_FORCE_OST field. + MCPWM_FH1_CFG1_TZ1_FORCE_OST_Pos = 0x4 + // Bit mask of TZ1_FORCE_OST field. + MCPWM_FH1_CFG1_TZ1_FORCE_OST_Msk = 0x10 + // Bit TZ1_FORCE_OST. + MCPWM_FH1_CFG1_TZ1_FORCE_OST = 0x10 + + // FH1_STATUS: Status of fault events. + // Position of TZ1_CBC_ON field. + MCPWM_FH1_STATUS_TZ1_CBC_ON_Pos = 0x0 + // Bit mask of TZ1_CBC_ON field. + MCPWM_FH1_STATUS_TZ1_CBC_ON_Msk = 0x1 + // Bit TZ1_CBC_ON. + MCPWM_FH1_STATUS_TZ1_CBC_ON = 0x1 + // Position of TZ1_OST_ON field. + MCPWM_FH1_STATUS_TZ1_OST_ON_Pos = 0x1 + // Bit mask of TZ1_OST_ON field. + MCPWM_FH1_STATUS_TZ1_OST_ON_Msk = 0x2 + // Bit TZ1_OST_ON. + MCPWM_FH1_STATUS_TZ1_OST_ON = 0x2 + + // GEN2_STMP_CFG: Transfer status and update method for time stamp registers A and B + // Position of CMPR2_A_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_CMPR2_A_UPMETHOD_Pos = 0x0 + // Bit mask of CMPR2_A_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_CMPR2_A_UPMETHOD_Msk = 0xf + // Position of CMPR2_B_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_CMPR2_B_UPMETHOD_Pos = 0x4 + // Bit mask of CMPR2_B_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_CMPR2_B_UPMETHOD_Msk = 0xf0 + // Position of CMPR2_A_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_CMPR2_A_SHDW_FULL_Pos = 0x8 + // Bit mask of CMPR2_A_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_CMPR2_A_SHDW_FULL_Msk = 0x100 + // Bit CMPR2_A_SHDW_FULL. + MCPWM_GEN2_STMP_CFG_CMPR2_A_SHDW_FULL = 0x100 + // Position of CMPR2_B_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_CMPR2_B_SHDW_FULL_Pos = 0x9 + // Bit mask of CMPR2_B_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_CMPR2_B_SHDW_FULL_Msk = 0x200 + // Bit CMPR2_B_SHDW_FULL. + MCPWM_GEN2_STMP_CFG_CMPR2_B_SHDW_FULL = 0x200 + + // GEN2_TSTMP_A: Shadow register for register A. + // Position of CMPR2_A field. + MCPWM_GEN2_TSTMP_A_CMPR2_A_Pos = 0x0 + // Bit mask of CMPR2_A field. + MCPWM_GEN2_TSTMP_A_CMPR2_A_Msk = 0xffff + + // GEN2_TSTMP_B: Shadow register for register B. + // Position of CMPR2_B field. + MCPWM_GEN2_TSTMP_B_CMPR2_B_Pos = 0x0 + // Bit mask of CMPR2_B field. + MCPWM_GEN2_TSTMP_B_CMPR2_B_Msk = 0xffff + + // GEN2_CFG0: Fault event T0 and T1 handling + // Position of GEN2_CFG_UPMETHOD field. + MCPWM_GEN2_CFG0_GEN2_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN2_CFG_UPMETHOD field. + MCPWM_GEN2_CFG0_GEN2_CFG_UPMETHOD_Msk = 0xf + // Position of GEN2_T0_SEL field. + MCPWM_GEN2_CFG0_GEN2_T0_SEL_Pos = 0x4 + // Bit mask of GEN2_T0_SEL field. + MCPWM_GEN2_CFG0_GEN2_T0_SEL_Msk = 0x70 + // Position of GEN2_T1_SEL field. + MCPWM_GEN2_CFG0_GEN2_T1_SEL_Pos = 0x7 + // Bit mask of GEN2_T1_SEL field. + MCPWM_GEN2_CFG0_GEN2_T1_SEL_Msk = 0x380 + + // GEN2_FORCE: Permissives to force PWM2A and PWM2B outputs by software + // Position of GEN2_CNTUFORCE_UPMETHOD field. + MCPWM_GEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN2_CNTUFORCE_UPMETHOD field. + MCPWM_GEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN2_A_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN2_A_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN2_B_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN2_B_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN2_A_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN2_A_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_Msk = 0x400 + // Bit GEN2_A_NCIFORCE. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE = 0x400 + // Position of GEN2_A_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN2_A_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN2_B_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN2_B_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_Msk = 0x2000 + // Bit GEN2_B_NCIFORCE. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE = 0x2000 + // Position of GEN2_B_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN2_B_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN2_A: Actions triggered by events on PWM2A + // Position of UTEZ field. + MCPWM_GEN2_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN2_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN2_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN2_A_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN2_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN2_A_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN2_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN2_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN2_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN2_A_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN2_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN2_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN2_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN2_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN2_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN2_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN2_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN2_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN2_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN2_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN2_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN2_A_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN2_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN2_A_DT1_Msk = 0xc00000 + + // GEN2_B: Actions triggered by events on PWM2B + // Position of UTEZ field. + MCPWM_GEN2_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN2_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN2_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN2_B_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN2_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN2_B_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN2_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN2_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN2_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN2_B_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN2_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN2_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN2_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN2_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN2_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN2_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN2_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN2_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN2_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN2_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN2_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN2_B_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN2_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN2_B_DT1_Msk = 0xc00000 + + // DT2_CFG: dead time type selection and configuration + // Position of DB2_FED_UPMETHOD field. + MCPWM_DT2_CFG_DB2_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DB2_FED_UPMETHOD field. + MCPWM_DT2_CFG_DB2_FED_UPMETHOD_Msk = 0xf + // Position of DB2_RED_UPMETHOD field. + MCPWM_DT2_CFG_DB2_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DB2_RED_UPMETHOD field. + MCPWM_DT2_CFG_DB2_RED_UPMETHOD_Msk = 0xf0 + // Position of DB2_DEB_MODE field. + MCPWM_DT2_CFG_DB2_DEB_MODE_Pos = 0x8 + // Bit mask of DB2_DEB_MODE field. + MCPWM_DT2_CFG_DB2_DEB_MODE_Msk = 0x100 + // Bit DB2_DEB_MODE. + MCPWM_DT2_CFG_DB2_DEB_MODE = 0x100 + // Position of DB2_A_OUTSWAP field. + MCPWM_DT2_CFG_DB2_A_OUTSWAP_Pos = 0x9 + // Bit mask of DB2_A_OUTSWAP field. + MCPWM_DT2_CFG_DB2_A_OUTSWAP_Msk = 0x200 + // Bit DB2_A_OUTSWAP. + MCPWM_DT2_CFG_DB2_A_OUTSWAP = 0x200 + // Position of DB2_B_OUTSWAP field. + MCPWM_DT2_CFG_DB2_B_OUTSWAP_Pos = 0xa + // Bit mask of DB2_B_OUTSWAP field. + MCPWM_DT2_CFG_DB2_B_OUTSWAP_Msk = 0x400 + // Bit DB2_B_OUTSWAP. + MCPWM_DT2_CFG_DB2_B_OUTSWAP = 0x400 + // Position of DB2_RED_INSEL field. + MCPWM_DT2_CFG_DB2_RED_INSEL_Pos = 0xb + // Bit mask of DB2_RED_INSEL field. + MCPWM_DT2_CFG_DB2_RED_INSEL_Msk = 0x800 + // Bit DB2_RED_INSEL. + MCPWM_DT2_CFG_DB2_RED_INSEL = 0x800 + // Position of DB2_FED_INSEL field. + MCPWM_DT2_CFG_DB2_FED_INSEL_Pos = 0xc + // Bit mask of DB2_FED_INSEL field. + MCPWM_DT2_CFG_DB2_FED_INSEL_Msk = 0x1000 + // Bit DB2_FED_INSEL. + MCPWM_DT2_CFG_DB2_FED_INSEL = 0x1000 + // Position of DB2_RED_OUTINVERT field. + MCPWM_DT2_CFG_DB2_RED_OUTINVERT_Pos = 0xd + // Bit mask of DB2_RED_OUTINVERT field. + MCPWM_DT2_CFG_DB2_RED_OUTINVERT_Msk = 0x2000 + // Bit DB2_RED_OUTINVERT. + MCPWM_DT2_CFG_DB2_RED_OUTINVERT = 0x2000 + // Position of DB2_FED_OUTINVERT field. + MCPWM_DT2_CFG_DB2_FED_OUTINVERT_Pos = 0xe + // Bit mask of DB2_FED_OUTINVERT field. + MCPWM_DT2_CFG_DB2_FED_OUTINVERT_Msk = 0x4000 + // Bit DB2_FED_OUTINVERT. + MCPWM_DT2_CFG_DB2_FED_OUTINVERT = 0x4000 + // Position of DB2_A_OUTBYPASS field. + MCPWM_DT2_CFG_DB2_A_OUTBYPASS_Pos = 0xf + // Bit mask of DB2_A_OUTBYPASS field. + MCPWM_DT2_CFG_DB2_A_OUTBYPASS_Msk = 0x8000 + // Bit DB2_A_OUTBYPASS. + MCPWM_DT2_CFG_DB2_A_OUTBYPASS = 0x8000 + // Position of DB2_B_OUTBYPASS field. + MCPWM_DT2_CFG_DB2_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DB2_B_OUTBYPASS field. + MCPWM_DT2_CFG_DB2_B_OUTBYPASS_Msk = 0x10000 + // Bit DB2_B_OUTBYPASS. + MCPWM_DT2_CFG_DB2_B_OUTBYPASS = 0x10000 + // Position of DB2_CLK_SEL field. + MCPWM_DT2_CFG_DB2_CLK_SEL_Pos = 0x11 + // Bit mask of DB2_CLK_SEL field. + MCPWM_DT2_CFG_DB2_CLK_SEL_Msk = 0x20000 + // Bit DB2_CLK_SEL. + MCPWM_DT2_CFG_DB2_CLK_SEL = 0x20000 + + // DT2_FED_CFG: Shadow register for falling edge delay (FED). + // Position of DB2_FED field. + MCPWM_DT2_FED_CFG_DB2_FED_Pos = 0x0 + // Bit mask of DB2_FED field. + MCPWM_DT2_FED_CFG_DB2_FED_Msk = 0xffff + + // DT2_RED_CFG: Shadow register for rising edge delay (RED). + // Position of DB2_RED field. + MCPWM_DT2_RED_CFG_DB2_RED_Pos = 0x0 + // Bit mask of DB2_RED field. + MCPWM_DT2_RED_CFG_DB2_RED_Msk = 0xffff + + // CARRIER2_CFG: Carrier enable and configuratoin + // Position of CHOPPER2_EN field. + MCPWM_CARRIER2_CFG_CHOPPER2_EN_Pos = 0x0 + // Bit mask of CHOPPER2_EN field. + MCPWM_CARRIER2_CFG_CHOPPER2_EN_Msk = 0x1 + // Bit CHOPPER2_EN. + MCPWM_CARRIER2_CFG_CHOPPER2_EN = 0x1 + // Position of CHOPPER2_PRESCALE field. + MCPWM_CARRIER2_CFG_CHOPPER2_PRESCALE_Pos = 0x1 + // Bit mask of CHOPPER2_PRESCALE field. + MCPWM_CARRIER2_CFG_CHOPPER2_PRESCALE_Msk = 0x1e + // Position of CHOPPER2_DUTY field. + MCPWM_CARRIER2_CFG_CHOPPER2_DUTY_Pos = 0x5 + // Bit mask of CHOPPER2_DUTY field. + MCPWM_CARRIER2_CFG_CHOPPER2_DUTY_Msk = 0xe0 + // Position of CHOPPER2_OSHTWTH field. + MCPWM_CARRIER2_CFG_CHOPPER2_OSHTWTH_Pos = 0x8 + // Bit mask of CHOPPER2_OSHTWTH field. + MCPWM_CARRIER2_CFG_CHOPPER2_OSHTWTH_Msk = 0xf00 + // Position of CHOPPER2_OUT_INVERT field. + MCPWM_CARRIER2_CFG_CHOPPER2_OUT_INVERT_Pos = 0xc + // Bit mask of CHOPPER2_OUT_INVERT field. + MCPWM_CARRIER2_CFG_CHOPPER2_OUT_INVERT_Msk = 0x1000 + // Bit CHOPPER2_OUT_INVERT. + MCPWM_CARRIER2_CFG_CHOPPER2_OUT_INVERT = 0x1000 + // Position of CHOPPER2_IN_INVERT field. + MCPWM_CARRIER2_CFG_CHOPPER2_IN_INVERT_Pos = 0xd + // Bit mask of CHOPPER2_IN_INVERT field. + MCPWM_CARRIER2_CFG_CHOPPER2_IN_INVERT_Msk = 0x2000 + // Bit CHOPPER2_IN_INVERT. + MCPWM_CARRIER2_CFG_CHOPPER2_IN_INVERT = 0x2000 + + // FH2_CFG0: Actions on PWM2A and PWM2B trip events + // Position of TZ2_SW_CBC field. + MCPWM_FH2_CFG0_TZ2_SW_CBC_Pos = 0x0 + // Bit mask of TZ2_SW_CBC field. + MCPWM_FH2_CFG0_TZ2_SW_CBC_Msk = 0x1 + // Bit TZ2_SW_CBC. + MCPWM_FH2_CFG0_TZ2_SW_CBC = 0x1 + // Position of TZ2_F2_CBC field. + MCPWM_FH2_CFG0_TZ2_F2_CBC_Pos = 0x1 + // Bit mask of TZ2_F2_CBC field. + MCPWM_FH2_CFG0_TZ2_F2_CBC_Msk = 0x2 + // Bit TZ2_F2_CBC. + MCPWM_FH2_CFG0_TZ2_F2_CBC = 0x2 + // Position of TZ2_F1_CBC field. + MCPWM_FH2_CFG0_TZ2_F1_CBC_Pos = 0x2 + // Bit mask of TZ2_F1_CBC field. + MCPWM_FH2_CFG0_TZ2_F1_CBC_Msk = 0x4 + // Bit TZ2_F1_CBC. + MCPWM_FH2_CFG0_TZ2_F1_CBC = 0x4 + // Position of TZ2_F0_CBC field. + MCPWM_FH2_CFG0_TZ2_F0_CBC_Pos = 0x3 + // Bit mask of TZ2_F0_CBC field. + MCPWM_FH2_CFG0_TZ2_F0_CBC_Msk = 0x8 + // Bit TZ2_F0_CBC. + MCPWM_FH2_CFG0_TZ2_F0_CBC = 0x8 + // Position of TZ2_SW_OST field. + MCPWM_FH2_CFG0_TZ2_SW_OST_Pos = 0x4 + // Bit mask of TZ2_SW_OST field. + MCPWM_FH2_CFG0_TZ2_SW_OST_Msk = 0x10 + // Bit TZ2_SW_OST. + MCPWM_FH2_CFG0_TZ2_SW_OST = 0x10 + // Position of TZ2_F2_OST field. + MCPWM_FH2_CFG0_TZ2_F2_OST_Pos = 0x5 + // Bit mask of TZ2_F2_OST field. + MCPWM_FH2_CFG0_TZ2_F2_OST_Msk = 0x20 + // Bit TZ2_F2_OST. + MCPWM_FH2_CFG0_TZ2_F2_OST = 0x20 + // Position of TZ2_F1_OST field. + MCPWM_FH2_CFG0_TZ2_F1_OST_Pos = 0x6 + // Bit mask of TZ2_F1_OST field. + MCPWM_FH2_CFG0_TZ2_F1_OST_Msk = 0x40 + // Bit TZ2_F1_OST. + MCPWM_FH2_CFG0_TZ2_F1_OST = 0x40 + // Position of TZ2_F0_OST field. + MCPWM_FH2_CFG0_TZ2_F0_OST_Pos = 0x7 + // Bit mask of TZ2_F0_OST field. + MCPWM_FH2_CFG0_TZ2_F0_OST_Msk = 0x80 + // Bit TZ2_F0_OST. + MCPWM_FH2_CFG0_TZ2_F0_OST = 0x80 + // Position of TZ2_A_CBC_D field. + MCPWM_FH2_CFG0_TZ2_A_CBC_D_Pos = 0x8 + // Bit mask of TZ2_A_CBC_D field. + MCPWM_FH2_CFG0_TZ2_A_CBC_D_Msk = 0x300 + // Position of TZ2_A_CBC_U field. + MCPWM_FH2_CFG0_TZ2_A_CBC_U_Pos = 0xa + // Bit mask of TZ2_A_CBC_U field. + MCPWM_FH2_CFG0_TZ2_A_CBC_U_Msk = 0xc00 + // Position of TZ2_A_OST_D field. + MCPWM_FH2_CFG0_TZ2_A_OST_D_Pos = 0xc + // Bit mask of TZ2_A_OST_D field. + MCPWM_FH2_CFG0_TZ2_A_OST_D_Msk = 0x3000 + // Position of TZ2_A_OST_U field. + MCPWM_FH2_CFG0_TZ2_A_OST_U_Pos = 0xe + // Bit mask of TZ2_A_OST_U field. + MCPWM_FH2_CFG0_TZ2_A_OST_U_Msk = 0xc000 + // Position of TZ2_B_CBC_D field. + MCPWM_FH2_CFG0_TZ2_B_CBC_D_Pos = 0x10 + // Bit mask of TZ2_B_CBC_D field. + MCPWM_FH2_CFG0_TZ2_B_CBC_D_Msk = 0x30000 + // Position of TZ2_B_CBC_U field. + MCPWM_FH2_CFG0_TZ2_B_CBC_U_Pos = 0x12 + // Bit mask of TZ2_B_CBC_U field. + MCPWM_FH2_CFG0_TZ2_B_CBC_U_Msk = 0xc0000 + // Position of TZ2_B_OST_D field. + MCPWM_FH2_CFG0_TZ2_B_OST_D_Pos = 0x14 + // Bit mask of TZ2_B_OST_D field. + MCPWM_FH2_CFG0_TZ2_B_OST_D_Msk = 0x300000 + // Position of TZ2_B_OST_U field. + MCPWM_FH2_CFG0_TZ2_B_OST_U_Pos = 0x16 + // Bit mask of TZ2_B_OST_U field. + MCPWM_FH2_CFG0_TZ2_B_OST_U_Msk = 0xc00000 + + // FH2_CFG1: Software triggers for fault handler actions + // Position of TZ2_CLR_OST field. + MCPWM_FH2_CFG1_TZ2_CLR_OST_Pos = 0x0 + // Bit mask of TZ2_CLR_OST field. + MCPWM_FH2_CFG1_TZ2_CLR_OST_Msk = 0x1 + // Bit TZ2_CLR_OST. + MCPWM_FH2_CFG1_TZ2_CLR_OST = 0x1 + // Position of TZ2_CBCPULSE field. + MCPWM_FH2_CFG1_TZ2_CBCPULSE_Pos = 0x1 + // Bit mask of TZ2_CBCPULSE field. + MCPWM_FH2_CFG1_TZ2_CBCPULSE_Msk = 0x6 + // Position of TZ2_FORCE_CBC field. + MCPWM_FH2_CFG1_TZ2_FORCE_CBC_Pos = 0x3 + // Bit mask of TZ2_FORCE_CBC field. + MCPWM_FH2_CFG1_TZ2_FORCE_CBC_Msk = 0x8 + // Bit TZ2_FORCE_CBC. + MCPWM_FH2_CFG1_TZ2_FORCE_CBC = 0x8 + // Position of TZ2_FORCE_OST field. + MCPWM_FH2_CFG1_TZ2_FORCE_OST_Pos = 0x4 + // Bit mask of TZ2_FORCE_OST field. + MCPWM_FH2_CFG1_TZ2_FORCE_OST_Msk = 0x10 + // Bit TZ2_FORCE_OST. + MCPWM_FH2_CFG1_TZ2_FORCE_OST = 0x10 + + // FH2_STATUS: Status of fault events. + // Position of TZ2_CBC_ON field. + MCPWM_FH2_STATUS_TZ2_CBC_ON_Pos = 0x0 + // Bit mask of TZ2_CBC_ON field. + MCPWM_FH2_STATUS_TZ2_CBC_ON_Msk = 0x1 + // Bit TZ2_CBC_ON. + MCPWM_FH2_STATUS_TZ2_CBC_ON = 0x1 + // Position of TZ2_OST_ON field. + MCPWM_FH2_STATUS_TZ2_OST_ON_Pos = 0x1 + // Bit mask of TZ2_OST_ON field. + MCPWM_FH2_STATUS_TZ2_OST_ON_Msk = 0x2 + // Bit TZ2_OST_ON. + MCPWM_FH2_STATUS_TZ2_OST_ON = 0x2 + + // FAULT_DETECT: Fault detection configuration and status + // Position of F0_EN field. + MCPWM_FAULT_DETECT_F0_EN_Pos = 0x0 + // Bit mask of F0_EN field. + MCPWM_FAULT_DETECT_F0_EN_Msk = 0x1 + // Bit F0_EN. + MCPWM_FAULT_DETECT_F0_EN = 0x1 + // Position of F1_EN field. + MCPWM_FAULT_DETECT_F1_EN_Pos = 0x1 + // Bit mask of F1_EN field. + MCPWM_FAULT_DETECT_F1_EN_Msk = 0x2 + // Bit F1_EN. + MCPWM_FAULT_DETECT_F1_EN = 0x2 + // Position of F2_EN field. + MCPWM_FAULT_DETECT_F2_EN_Pos = 0x2 + // Bit mask of F2_EN field. + MCPWM_FAULT_DETECT_F2_EN_Msk = 0x4 + // Bit F2_EN. + MCPWM_FAULT_DETECT_F2_EN = 0x4 + // Position of F0_POLE field. + MCPWM_FAULT_DETECT_F0_POLE_Pos = 0x3 + // Bit mask of F0_POLE field. + MCPWM_FAULT_DETECT_F0_POLE_Msk = 0x8 + // Bit F0_POLE. + MCPWM_FAULT_DETECT_F0_POLE = 0x8 + // Position of F1_POLE field. + MCPWM_FAULT_DETECT_F1_POLE_Pos = 0x4 + // Bit mask of F1_POLE field. + MCPWM_FAULT_DETECT_F1_POLE_Msk = 0x10 + // Bit F1_POLE. + MCPWM_FAULT_DETECT_F1_POLE = 0x10 + // Position of F2_POLE field. + MCPWM_FAULT_DETECT_F2_POLE_Pos = 0x5 + // Bit mask of F2_POLE field. + MCPWM_FAULT_DETECT_F2_POLE_Msk = 0x20 + // Bit F2_POLE. + MCPWM_FAULT_DETECT_F2_POLE = 0x20 + // Position of EVENT_F0 field. + MCPWM_FAULT_DETECT_EVENT_F0_Pos = 0x6 + // Bit mask of EVENT_F0 field. + MCPWM_FAULT_DETECT_EVENT_F0_Msk = 0x40 + // Bit EVENT_F0. + MCPWM_FAULT_DETECT_EVENT_F0 = 0x40 + // Position of EVENT_F1 field. + MCPWM_FAULT_DETECT_EVENT_F1_Pos = 0x7 + // Bit mask of EVENT_F1 field. + MCPWM_FAULT_DETECT_EVENT_F1_Msk = 0x80 + // Bit EVENT_F1. + MCPWM_FAULT_DETECT_EVENT_F1 = 0x80 + // Position of EVENT_F2 field. + MCPWM_FAULT_DETECT_EVENT_F2_Pos = 0x8 + // Bit mask of EVENT_F2 field. + MCPWM_FAULT_DETECT_EVENT_F2_Msk = 0x100 + // Bit EVENT_F2. + MCPWM_FAULT_DETECT_EVENT_F2 = 0x100 + + // CAP_TIMER_CFG: Configure capture timer + // Position of CAP_TIMER_EN field. + MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN_Pos = 0x0 + // Bit mask of CAP_TIMER_EN field. + MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN_Msk = 0x1 + // Bit CAP_TIMER_EN. + MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN = 0x1 + // Position of CAP_SYNCI_EN field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Pos = 0x1 + // Bit mask of CAP_SYNCI_EN field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Msk = 0x2 + // Bit CAP_SYNCI_EN. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN = 0x2 + // Position of CAP_SYNCI_SEL field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Pos = 0x2 + // Bit mask of CAP_SYNCI_SEL field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Msk = 0x1c + // Position of CAP_SYNC_SW field. + MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW_Pos = 0x5 + // Bit mask of CAP_SYNC_SW field. + MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW_Msk = 0x20 + // Bit CAP_SYNC_SW. + MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW = 0x20 + + // CAP_TIMER_PHASE: Phase for capture timer sync + // Position of CAP_PHASE field. + MCPWM_CAP_TIMER_PHASE_CAP_PHASE_Pos = 0x0 + // Bit mask of CAP_PHASE field. + MCPWM_CAP_TIMER_PHASE_CAP_PHASE_Msk = 0xffffffff + + // CAP_CH0_CFG: Capture channel 0 configuration and enable + // Position of CAP0_EN field. + MCPWM_CAP_CH0_CFG_CAP0_EN_Pos = 0x0 + // Bit mask of CAP0_EN field. + MCPWM_CAP_CH0_CFG_CAP0_EN_Msk = 0x1 + // Bit CAP0_EN. + MCPWM_CAP_CH0_CFG_CAP0_EN = 0x1 + // Position of CAP0_MODE field. + MCPWM_CAP_CH0_CFG_CAP0_MODE_Pos = 0x1 + // Bit mask of CAP0_MODE field. + MCPWM_CAP_CH0_CFG_CAP0_MODE_Msk = 0x6 + // Position of CAP0_PRESCALE field. + MCPWM_CAP_CH0_CFG_CAP0_PRESCALE_Pos = 0x3 + // Bit mask of CAP0_PRESCALE field. + MCPWM_CAP_CH0_CFG_CAP0_PRESCALE_Msk = 0x7f8 + // Position of CAP0_IN_INVERT field. + MCPWM_CAP_CH0_CFG_CAP0_IN_INVERT_Pos = 0xb + // Bit mask of CAP0_IN_INVERT field. + MCPWM_CAP_CH0_CFG_CAP0_IN_INVERT_Msk = 0x800 + // Bit CAP0_IN_INVERT. + MCPWM_CAP_CH0_CFG_CAP0_IN_INVERT = 0x800 + // Position of CAP0_SW field. + MCPWM_CAP_CH0_CFG_CAP0_SW_Pos = 0xc + // Bit mask of CAP0_SW field. + MCPWM_CAP_CH0_CFG_CAP0_SW_Msk = 0x1000 + // Bit CAP0_SW. + MCPWM_CAP_CH0_CFG_CAP0_SW = 0x1000 + + // CAP_CH1_CFG: Capture channel 1 configuration and enable + // Position of CAP1_EN field. + MCPWM_CAP_CH1_CFG_CAP1_EN_Pos = 0x0 + // Bit mask of CAP1_EN field. + MCPWM_CAP_CH1_CFG_CAP1_EN_Msk = 0x1 + // Bit CAP1_EN. + MCPWM_CAP_CH1_CFG_CAP1_EN = 0x1 + // Position of CAP1_MODE field. + MCPWM_CAP_CH1_CFG_CAP1_MODE_Pos = 0x1 + // Bit mask of CAP1_MODE field. + MCPWM_CAP_CH1_CFG_CAP1_MODE_Msk = 0x6 + // Position of CAP1_PRESCALE field. + MCPWM_CAP_CH1_CFG_CAP1_PRESCALE_Pos = 0x3 + // Bit mask of CAP1_PRESCALE field. + MCPWM_CAP_CH1_CFG_CAP1_PRESCALE_Msk = 0x7f8 + // Position of CAP1_IN_INVERT field. + MCPWM_CAP_CH1_CFG_CAP1_IN_INVERT_Pos = 0xb + // Bit mask of CAP1_IN_INVERT field. + MCPWM_CAP_CH1_CFG_CAP1_IN_INVERT_Msk = 0x800 + // Bit CAP1_IN_INVERT. + MCPWM_CAP_CH1_CFG_CAP1_IN_INVERT = 0x800 + // Position of CAP1_SW field. + MCPWM_CAP_CH1_CFG_CAP1_SW_Pos = 0xc + // Bit mask of CAP1_SW field. + MCPWM_CAP_CH1_CFG_CAP1_SW_Msk = 0x1000 + // Bit CAP1_SW. + MCPWM_CAP_CH1_CFG_CAP1_SW = 0x1000 + + // CAP_CH2_CFG: Capture channel 2 configuration and enable + // Position of CAP2_EN field. + MCPWM_CAP_CH2_CFG_CAP2_EN_Pos = 0x0 + // Bit mask of CAP2_EN field. + MCPWM_CAP_CH2_CFG_CAP2_EN_Msk = 0x1 + // Bit CAP2_EN. + MCPWM_CAP_CH2_CFG_CAP2_EN = 0x1 + // Position of CAP2_MODE field. + MCPWM_CAP_CH2_CFG_CAP2_MODE_Pos = 0x1 + // Bit mask of CAP2_MODE field. + MCPWM_CAP_CH2_CFG_CAP2_MODE_Msk = 0x6 + // Position of CAP2_PRESCALE field. + MCPWM_CAP_CH2_CFG_CAP2_PRESCALE_Pos = 0x3 + // Bit mask of CAP2_PRESCALE field. + MCPWM_CAP_CH2_CFG_CAP2_PRESCALE_Msk = 0x7f8 + // Position of CAP2_IN_INVERT field. + MCPWM_CAP_CH2_CFG_CAP2_IN_INVERT_Pos = 0xb + // Bit mask of CAP2_IN_INVERT field. + MCPWM_CAP_CH2_CFG_CAP2_IN_INVERT_Msk = 0x800 + // Bit CAP2_IN_INVERT. + MCPWM_CAP_CH2_CFG_CAP2_IN_INVERT = 0x800 + // Position of CAP2_SW field. + MCPWM_CAP_CH2_CFG_CAP2_SW_Pos = 0xc + // Bit mask of CAP2_SW field. + MCPWM_CAP_CH2_CFG_CAP2_SW_Msk = 0x1000 + // Bit CAP2_SW. + MCPWM_CAP_CH2_CFG_CAP2_SW = 0x1000 + + // CAP_CH0: ch0 capture value status register + // Position of CAP0_VALUE field. + MCPWM_CAP_CH0_CAP0_VALUE_Pos = 0x0 + // Bit mask of CAP0_VALUE field. + MCPWM_CAP_CH0_CAP0_VALUE_Msk = 0xffffffff + + // CAP_CH1: ch1 capture value status register + // Position of CAP1_VALUE field. + MCPWM_CAP_CH1_CAP1_VALUE_Pos = 0x0 + // Bit mask of CAP1_VALUE field. + MCPWM_CAP_CH1_CAP1_VALUE_Msk = 0xffffffff + + // CAP_CH2: ch2 capture value status register + // Position of CAP2_VALUE field. + MCPWM_CAP_CH2_CAP2_VALUE_Pos = 0x0 + // Bit mask of CAP2_VALUE field. + MCPWM_CAP_CH2_CAP2_VALUE_Msk = 0xffffffff + + // CAP_STATUS: Edge of last capture trigger + // Position of CAP0_EDGE field. + MCPWM_CAP_STATUS_CAP0_EDGE_Pos = 0x0 + // Bit mask of CAP0_EDGE field. + MCPWM_CAP_STATUS_CAP0_EDGE_Msk = 0x1 + // Bit CAP0_EDGE. + MCPWM_CAP_STATUS_CAP0_EDGE = 0x1 + // Position of CAP1_EDGE field. + MCPWM_CAP_STATUS_CAP1_EDGE_Pos = 0x1 + // Bit mask of CAP1_EDGE field. + MCPWM_CAP_STATUS_CAP1_EDGE_Msk = 0x2 + // Bit CAP1_EDGE. + MCPWM_CAP_STATUS_CAP1_EDGE = 0x2 + // Position of CAP2_EDGE field. + MCPWM_CAP_STATUS_CAP2_EDGE_Pos = 0x2 + // Bit mask of CAP2_EDGE field. + MCPWM_CAP_STATUS_CAP2_EDGE_Msk = 0x4 + // Bit CAP2_EDGE. + MCPWM_CAP_STATUS_CAP2_EDGE = 0x4 + + // UPDATE_CFG: Enable update. + // Position of GLOBAL_UP_EN field. + MCPWM_UPDATE_CFG_GLOBAL_UP_EN_Pos = 0x0 + // Bit mask of GLOBAL_UP_EN field. + MCPWM_UPDATE_CFG_GLOBAL_UP_EN_Msk = 0x1 + // Bit GLOBAL_UP_EN. + MCPWM_UPDATE_CFG_GLOBAL_UP_EN = 0x1 + // Position of GLOBAL_FORCE_UP field. + MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP_Pos = 0x1 + // Bit mask of GLOBAL_FORCE_UP field. + MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP_Msk = 0x2 + // Bit GLOBAL_FORCE_UP. + MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP = 0x2 + // Position of OP0_UP_EN field. + MCPWM_UPDATE_CFG_OP0_UP_EN_Pos = 0x2 + // Bit mask of OP0_UP_EN field. + MCPWM_UPDATE_CFG_OP0_UP_EN_Msk = 0x4 + // Bit OP0_UP_EN. + MCPWM_UPDATE_CFG_OP0_UP_EN = 0x4 + // Position of OP0_FORCE_UP field. + MCPWM_UPDATE_CFG_OP0_FORCE_UP_Pos = 0x3 + // Bit mask of OP0_FORCE_UP field. + MCPWM_UPDATE_CFG_OP0_FORCE_UP_Msk = 0x8 + // Bit OP0_FORCE_UP. + MCPWM_UPDATE_CFG_OP0_FORCE_UP = 0x8 + // Position of OP1_UP_EN field. + MCPWM_UPDATE_CFG_OP1_UP_EN_Pos = 0x4 + // Bit mask of OP1_UP_EN field. + MCPWM_UPDATE_CFG_OP1_UP_EN_Msk = 0x10 + // Bit OP1_UP_EN. + MCPWM_UPDATE_CFG_OP1_UP_EN = 0x10 + // Position of OP1_FORCE_UP field. + MCPWM_UPDATE_CFG_OP1_FORCE_UP_Pos = 0x5 + // Bit mask of OP1_FORCE_UP field. + MCPWM_UPDATE_CFG_OP1_FORCE_UP_Msk = 0x20 + // Bit OP1_FORCE_UP. + MCPWM_UPDATE_CFG_OP1_FORCE_UP = 0x20 + // Position of OP2_UP_EN field. + MCPWM_UPDATE_CFG_OP2_UP_EN_Pos = 0x6 + // Bit mask of OP2_UP_EN field. + MCPWM_UPDATE_CFG_OP2_UP_EN_Msk = 0x40 + // Bit OP2_UP_EN. + MCPWM_UPDATE_CFG_OP2_UP_EN = 0x40 + // Position of OP2_FORCE_UP field. + MCPWM_UPDATE_CFG_OP2_FORCE_UP_Pos = 0x7 + // Bit mask of OP2_FORCE_UP field. + MCPWM_UPDATE_CFG_OP2_FORCE_UP_Msk = 0x80 + // Bit OP2_FORCE_UP. + MCPWM_UPDATE_CFG_OP2_FORCE_UP = 0x80 + + // INT_ENA: Interrupt enable bits + // Position of TIMER0_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_STOP_INT_ENA_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_STOP_INT_ENA_Msk = 0x1 + // Bit TIMER0_STOP_INT_ENA. + MCPWM_INT_ENA_TIMER0_STOP_INT_ENA = 0x1 + // Position of TIMER1_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_STOP_INT_ENA_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_STOP_INT_ENA_Msk = 0x2 + // Bit TIMER1_STOP_INT_ENA. + MCPWM_INT_ENA_TIMER1_STOP_INT_ENA = 0x2 + // Position of TIMER2_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_STOP_INT_ENA_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_STOP_INT_ENA_Msk = 0x4 + // Bit TIMER2_STOP_INT_ENA. + MCPWM_INT_ENA_TIMER2_STOP_INT_ENA = 0x4 + // Position of TIMER0_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA_Msk = 0x8 + // Bit TIMER0_TEZ_INT_ENA. + MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA = 0x8 + // Position of TIMER1_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA_Msk = 0x10 + // Bit TIMER1_TEZ_INT_ENA. + MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA = 0x10 + // Position of TIMER2_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA_Msk = 0x20 + // Bit TIMER2_TEZ_INT_ENA. + MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA = 0x20 + // Position of TIMER0_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEP_INT_ENA_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEP_INT_ENA_Msk = 0x40 + // Bit TIMER0_TEP_INT_ENA. + MCPWM_INT_ENA_TIMER0_TEP_INT_ENA = 0x40 + // Position of TIMER1_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEP_INT_ENA_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEP_INT_ENA_Msk = 0x80 + // Bit TIMER1_TEP_INT_ENA. + MCPWM_INT_ENA_TIMER1_TEP_INT_ENA = 0x80 + // Position of TIMER2_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEP_INT_ENA_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEP_INT_ENA_Msk = 0x100 + // Bit TIMER2_TEP_INT_ENA. + MCPWM_INT_ENA_TIMER2_TEP_INT_ENA = 0x100 + // Position of FAULT0_INT_ENA field. + MCPWM_INT_ENA_FAULT0_INT_ENA_Pos = 0x9 + // Bit mask of FAULT0_INT_ENA field. + MCPWM_INT_ENA_FAULT0_INT_ENA_Msk = 0x200 + // Bit FAULT0_INT_ENA. + MCPWM_INT_ENA_FAULT0_INT_ENA = 0x200 + // Position of FAULT1_INT_ENA field. + MCPWM_INT_ENA_FAULT1_INT_ENA_Pos = 0xa + // Bit mask of FAULT1_INT_ENA field. + MCPWM_INT_ENA_FAULT1_INT_ENA_Msk = 0x400 + // Bit FAULT1_INT_ENA. + MCPWM_INT_ENA_FAULT1_INT_ENA = 0x400 + // Position of FAULT2_INT_ENA field. + MCPWM_INT_ENA_FAULT2_INT_ENA_Pos = 0xb + // Bit mask of FAULT2_INT_ENA field. + MCPWM_INT_ENA_FAULT2_INT_ENA_Msk = 0x800 + // Bit FAULT2_INT_ENA. + MCPWM_INT_ENA_FAULT2_INT_ENA = 0x800 + // Position of FAULT0_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT0_CLR_INT_ENA_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT0_CLR_INT_ENA_Msk = 0x1000 + // Bit FAULT0_CLR_INT_ENA. + MCPWM_INT_ENA_FAULT0_CLR_INT_ENA = 0x1000 + // Position of FAULT1_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT1_CLR_INT_ENA_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT1_CLR_INT_ENA_Msk = 0x2000 + // Bit FAULT1_CLR_INT_ENA. + MCPWM_INT_ENA_FAULT1_CLR_INT_ENA = 0x2000 + // Position of FAULT2_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT2_CLR_INT_ENA_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT2_CLR_INT_ENA_Msk = 0x4000 + // Bit FAULT2_CLR_INT_ENA. + MCPWM_INT_ENA_FAULT2_CLR_INT_ENA = 0x4000 + // Position of CMPR0_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR0_TEA_INT_ENA_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR0_TEA_INT_ENA_Msk = 0x8000 + // Bit CMPR0_TEA_INT_ENA. + MCPWM_INT_ENA_CMPR0_TEA_INT_ENA = 0x8000 + // Position of CMPR1_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR1_TEA_INT_ENA_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR1_TEA_INT_ENA_Msk = 0x10000 + // Bit CMPR1_TEA_INT_ENA. + MCPWM_INT_ENA_CMPR1_TEA_INT_ENA = 0x10000 + // Position of CMPR2_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR2_TEA_INT_ENA_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR2_TEA_INT_ENA_Msk = 0x20000 + // Bit CMPR2_TEA_INT_ENA. + MCPWM_INT_ENA_CMPR2_TEA_INT_ENA = 0x20000 + // Position of CMPR0_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR0_TEB_INT_ENA_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR0_TEB_INT_ENA_Msk = 0x40000 + // Bit CMPR0_TEB_INT_ENA. + MCPWM_INT_ENA_CMPR0_TEB_INT_ENA = 0x40000 + // Position of CMPR1_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR1_TEB_INT_ENA_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR1_TEB_INT_ENA_Msk = 0x80000 + // Bit CMPR1_TEB_INT_ENA. + MCPWM_INT_ENA_CMPR1_TEB_INT_ENA = 0x80000 + // Position of CMPR2_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR2_TEB_INT_ENA_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR2_TEB_INT_ENA_Msk = 0x100000 + // Bit CMPR2_TEB_INT_ENA. + MCPWM_INT_ENA_CMPR2_TEB_INT_ENA = 0x100000 + // Position of TZ0_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ0_CBC_INT_ENA_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ0_CBC_INT_ENA_Msk = 0x200000 + // Bit TZ0_CBC_INT_ENA. + MCPWM_INT_ENA_TZ0_CBC_INT_ENA = 0x200000 + // Position of TZ1_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ1_CBC_INT_ENA_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ1_CBC_INT_ENA_Msk = 0x400000 + // Bit TZ1_CBC_INT_ENA. + MCPWM_INT_ENA_TZ1_CBC_INT_ENA = 0x400000 + // Position of TZ2_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ2_CBC_INT_ENA_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ2_CBC_INT_ENA_Msk = 0x800000 + // Bit TZ2_CBC_INT_ENA. + MCPWM_INT_ENA_TZ2_CBC_INT_ENA = 0x800000 + // Position of TZ0_OST_INT_ENA field. + MCPWM_INT_ENA_TZ0_OST_INT_ENA_Pos = 0x18 + // Bit mask of TZ0_OST_INT_ENA field. + MCPWM_INT_ENA_TZ0_OST_INT_ENA_Msk = 0x1000000 + // Bit TZ0_OST_INT_ENA. + MCPWM_INT_ENA_TZ0_OST_INT_ENA = 0x1000000 + // Position of TZ1_OST_INT_ENA field. + MCPWM_INT_ENA_TZ1_OST_INT_ENA_Pos = 0x19 + // Bit mask of TZ1_OST_INT_ENA field. + MCPWM_INT_ENA_TZ1_OST_INT_ENA_Msk = 0x2000000 + // Bit TZ1_OST_INT_ENA. + MCPWM_INT_ENA_TZ1_OST_INT_ENA = 0x2000000 + // Position of TZ2_OST_INT_ENA field. + MCPWM_INT_ENA_TZ2_OST_INT_ENA_Pos = 0x1a + // Bit mask of TZ2_OST_INT_ENA field. + MCPWM_INT_ENA_TZ2_OST_INT_ENA_Msk = 0x4000000 + // Bit TZ2_OST_INT_ENA. + MCPWM_INT_ENA_TZ2_OST_INT_ENA = 0x4000000 + // Position of CAP0_INT_ENA field. + MCPWM_INT_ENA_CAP0_INT_ENA_Pos = 0x1b + // Bit mask of CAP0_INT_ENA field. + MCPWM_INT_ENA_CAP0_INT_ENA_Msk = 0x8000000 + // Bit CAP0_INT_ENA. + MCPWM_INT_ENA_CAP0_INT_ENA = 0x8000000 + // Position of CAP1_INT_ENA field. + MCPWM_INT_ENA_CAP1_INT_ENA_Pos = 0x1c + // Bit mask of CAP1_INT_ENA field. + MCPWM_INT_ENA_CAP1_INT_ENA_Msk = 0x10000000 + // Bit CAP1_INT_ENA. + MCPWM_INT_ENA_CAP1_INT_ENA = 0x10000000 + // Position of CAP2_INT_ENA field. + MCPWM_INT_ENA_CAP2_INT_ENA_Pos = 0x1d + // Bit mask of CAP2_INT_ENA field. + MCPWM_INT_ENA_CAP2_INT_ENA_Msk = 0x20000000 + // Bit CAP2_INT_ENA. + MCPWM_INT_ENA_CAP2_INT_ENA = 0x20000000 + + // INT_RAW: Raw interrupt status + // Position of TIMER0_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_STOP_INT_RAW_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_STOP_INT_RAW_Msk = 0x1 + // Bit TIMER0_STOP_INT_RAW. + MCPWM_INT_RAW_TIMER0_STOP_INT_RAW = 0x1 + // Position of TIMER1_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_STOP_INT_RAW_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_STOP_INT_RAW_Msk = 0x2 + // Bit TIMER1_STOP_INT_RAW. + MCPWM_INT_RAW_TIMER1_STOP_INT_RAW = 0x2 + // Position of TIMER2_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_STOP_INT_RAW_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_STOP_INT_RAW_Msk = 0x4 + // Bit TIMER2_STOP_INT_RAW. + MCPWM_INT_RAW_TIMER2_STOP_INT_RAW = 0x4 + // Position of TIMER0_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW_Msk = 0x8 + // Bit TIMER0_TEZ_INT_RAW. + MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW = 0x8 + // Position of TIMER1_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW_Msk = 0x10 + // Bit TIMER1_TEZ_INT_RAW. + MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW = 0x10 + // Position of TIMER2_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW_Msk = 0x20 + // Bit TIMER2_TEZ_INT_RAW. + MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW = 0x20 + // Position of TIMER0_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEP_INT_RAW_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEP_INT_RAW_Msk = 0x40 + // Bit TIMER0_TEP_INT_RAW. + MCPWM_INT_RAW_TIMER0_TEP_INT_RAW = 0x40 + // Position of TIMER1_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEP_INT_RAW_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEP_INT_RAW_Msk = 0x80 + // Bit TIMER1_TEP_INT_RAW. + MCPWM_INT_RAW_TIMER1_TEP_INT_RAW = 0x80 + // Position of TIMER2_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEP_INT_RAW_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEP_INT_RAW_Msk = 0x100 + // Bit TIMER2_TEP_INT_RAW. + MCPWM_INT_RAW_TIMER2_TEP_INT_RAW = 0x100 + // Position of FAULT0_INT_RAW field. + MCPWM_INT_RAW_FAULT0_INT_RAW_Pos = 0x9 + // Bit mask of FAULT0_INT_RAW field. + MCPWM_INT_RAW_FAULT0_INT_RAW_Msk = 0x200 + // Bit FAULT0_INT_RAW. + MCPWM_INT_RAW_FAULT0_INT_RAW = 0x200 + // Position of FAULT1_INT_RAW field. + MCPWM_INT_RAW_FAULT1_INT_RAW_Pos = 0xa + // Bit mask of FAULT1_INT_RAW field. + MCPWM_INT_RAW_FAULT1_INT_RAW_Msk = 0x400 + // Bit FAULT1_INT_RAW. + MCPWM_INT_RAW_FAULT1_INT_RAW = 0x400 + // Position of FAULT2_INT_RAW field. + MCPWM_INT_RAW_FAULT2_INT_RAW_Pos = 0xb + // Bit mask of FAULT2_INT_RAW field. + MCPWM_INT_RAW_FAULT2_INT_RAW_Msk = 0x800 + // Bit FAULT2_INT_RAW. + MCPWM_INT_RAW_FAULT2_INT_RAW = 0x800 + // Position of FAULT0_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT0_CLR_INT_RAW_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT0_CLR_INT_RAW_Msk = 0x1000 + // Bit FAULT0_CLR_INT_RAW. + MCPWM_INT_RAW_FAULT0_CLR_INT_RAW = 0x1000 + // Position of FAULT1_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT1_CLR_INT_RAW_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT1_CLR_INT_RAW_Msk = 0x2000 + // Bit FAULT1_CLR_INT_RAW. + MCPWM_INT_RAW_FAULT1_CLR_INT_RAW = 0x2000 + // Position of FAULT2_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT2_CLR_INT_RAW_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT2_CLR_INT_RAW_Msk = 0x4000 + // Bit FAULT2_CLR_INT_RAW. + MCPWM_INT_RAW_FAULT2_CLR_INT_RAW = 0x4000 + // Position of CMPR0_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR0_TEA_INT_RAW_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR0_TEA_INT_RAW_Msk = 0x8000 + // Bit CMPR0_TEA_INT_RAW. + MCPWM_INT_RAW_CMPR0_TEA_INT_RAW = 0x8000 + // Position of CMPR1_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR1_TEA_INT_RAW_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR1_TEA_INT_RAW_Msk = 0x10000 + // Bit CMPR1_TEA_INT_RAW. + MCPWM_INT_RAW_CMPR1_TEA_INT_RAW = 0x10000 + // Position of CMPR2_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR2_TEA_INT_RAW_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR2_TEA_INT_RAW_Msk = 0x20000 + // Bit CMPR2_TEA_INT_RAW. + MCPWM_INT_RAW_CMPR2_TEA_INT_RAW = 0x20000 + // Position of CMPR0_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR0_TEB_INT_RAW_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR0_TEB_INT_RAW_Msk = 0x40000 + // Bit CMPR0_TEB_INT_RAW. + MCPWM_INT_RAW_CMPR0_TEB_INT_RAW = 0x40000 + // Position of CMPR1_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR1_TEB_INT_RAW_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR1_TEB_INT_RAW_Msk = 0x80000 + // Bit CMPR1_TEB_INT_RAW. + MCPWM_INT_RAW_CMPR1_TEB_INT_RAW = 0x80000 + // Position of CMPR2_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR2_TEB_INT_RAW_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR2_TEB_INT_RAW_Msk = 0x100000 + // Bit CMPR2_TEB_INT_RAW. + MCPWM_INT_RAW_CMPR2_TEB_INT_RAW = 0x100000 + // Position of TZ0_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ0_CBC_INT_RAW_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ0_CBC_INT_RAW_Msk = 0x200000 + // Bit TZ0_CBC_INT_RAW. + MCPWM_INT_RAW_TZ0_CBC_INT_RAW = 0x200000 + // Position of TZ1_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ1_CBC_INT_RAW_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ1_CBC_INT_RAW_Msk = 0x400000 + // Bit TZ1_CBC_INT_RAW. + MCPWM_INT_RAW_TZ1_CBC_INT_RAW = 0x400000 + // Position of TZ2_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ2_CBC_INT_RAW_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ2_CBC_INT_RAW_Msk = 0x800000 + // Bit TZ2_CBC_INT_RAW. + MCPWM_INT_RAW_TZ2_CBC_INT_RAW = 0x800000 + // Position of TZ0_OST_INT_RAW field. + MCPWM_INT_RAW_TZ0_OST_INT_RAW_Pos = 0x18 + // Bit mask of TZ0_OST_INT_RAW field. + MCPWM_INT_RAW_TZ0_OST_INT_RAW_Msk = 0x1000000 + // Bit TZ0_OST_INT_RAW. + MCPWM_INT_RAW_TZ0_OST_INT_RAW = 0x1000000 + // Position of TZ1_OST_INT_RAW field. + MCPWM_INT_RAW_TZ1_OST_INT_RAW_Pos = 0x19 + // Bit mask of TZ1_OST_INT_RAW field. + MCPWM_INT_RAW_TZ1_OST_INT_RAW_Msk = 0x2000000 + // Bit TZ1_OST_INT_RAW. + MCPWM_INT_RAW_TZ1_OST_INT_RAW = 0x2000000 + // Position of TZ2_OST_INT_RAW field. + MCPWM_INT_RAW_TZ2_OST_INT_RAW_Pos = 0x1a + // Bit mask of TZ2_OST_INT_RAW field. + MCPWM_INT_RAW_TZ2_OST_INT_RAW_Msk = 0x4000000 + // Bit TZ2_OST_INT_RAW. + MCPWM_INT_RAW_TZ2_OST_INT_RAW = 0x4000000 + // Position of CAP0_INT_RAW field. + MCPWM_INT_RAW_CAP0_INT_RAW_Pos = 0x1b + // Bit mask of CAP0_INT_RAW field. + MCPWM_INT_RAW_CAP0_INT_RAW_Msk = 0x8000000 + // Bit CAP0_INT_RAW. + MCPWM_INT_RAW_CAP0_INT_RAW = 0x8000000 + // Position of CAP1_INT_RAW field. + MCPWM_INT_RAW_CAP1_INT_RAW_Pos = 0x1c + // Bit mask of CAP1_INT_RAW field. + MCPWM_INT_RAW_CAP1_INT_RAW_Msk = 0x10000000 + // Bit CAP1_INT_RAW. + MCPWM_INT_RAW_CAP1_INT_RAW = 0x10000000 + // Position of CAP2_INT_RAW field. + MCPWM_INT_RAW_CAP2_INT_RAW_Pos = 0x1d + // Bit mask of CAP2_INT_RAW field. + MCPWM_INT_RAW_CAP2_INT_RAW_Msk = 0x20000000 + // Bit CAP2_INT_RAW. + MCPWM_INT_RAW_CAP2_INT_RAW = 0x20000000 + + // INT_ST: Masked interrupt status + // Position of TIMER0_STOP_INT_ST field. + MCPWM_INT_ST_TIMER0_STOP_INT_ST_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_ST field. + MCPWM_INT_ST_TIMER0_STOP_INT_ST_Msk = 0x1 + // Bit TIMER0_STOP_INT_ST. + MCPWM_INT_ST_TIMER0_STOP_INT_ST = 0x1 + // Position of TIMER1_STOP_INT_ST field. + MCPWM_INT_ST_TIMER1_STOP_INT_ST_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_ST field. + MCPWM_INT_ST_TIMER1_STOP_INT_ST_Msk = 0x2 + // Bit TIMER1_STOP_INT_ST. + MCPWM_INT_ST_TIMER1_STOP_INT_ST = 0x2 + // Position of TIMER2_STOP_INT_ST field. + MCPWM_INT_ST_TIMER2_STOP_INT_ST_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_ST field. + MCPWM_INT_ST_TIMER2_STOP_INT_ST_Msk = 0x4 + // Bit TIMER2_STOP_INT_ST. + MCPWM_INT_ST_TIMER2_STOP_INT_ST = 0x4 + // Position of TIMER0_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER0_TEZ_INT_ST_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER0_TEZ_INT_ST_Msk = 0x8 + // Bit TIMER0_TEZ_INT_ST. + MCPWM_INT_ST_TIMER0_TEZ_INT_ST = 0x8 + // Position of TIMER1_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER1_TEZ_INT_ST_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER1_TEZ_INT_ST_Msk = 0x10 + // Bit TIMER1_TEZ_INT_ST. + MCPWM_INT_ST_TIMER1_TEZ_INT_ST = 0x10 + // Position of TIMER2_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER2_TEZ_INT_ST_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER2_TEZ_INT_ST_Msk = 0x20 + // Bit TIMER2_TEZ_INT_ST. + MCPWM_INT_ST_TIMER2_TEZ_INT_ST = 0x20 + // Position of TIMER0_TEP_INT_ST field. + MCPWM_INT_ST_TIMER0_TEP_INT_ST_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_ST field. + MCPWM_INT_ST_TIMER0_TEP_INT_ST_Msk = 0x40 + // Bit TIMER0_TEP_INT_ST. + MCPWM_INT_ST_TIMER0_TEP_INT_ST = 0x40 + // Position of TIMER1_TEP_INT_ST field. + MCPWM_INT_ST_TIMER1_TEP_INT_ST_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_ST field. + MCPWM_INT_ST_TIMER1_TEP_INT_ST_Msk = 0x80 + // Bit TIMER1_TEP_INT_ST. + MCPWM_INT_ST_TIMER1_TEP_INT_ST = 0x80 + // Position of TIMER2_TEP_INT_ST field. + MCPWM_INT_ST_TIMER2_TEP_INT_ST_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_ST field. + MCPWM_INT_ST_TIMER2_TEP_INT_ST_Msk = 0x100 + // Bit TIMER2_TEP_INT_ST. + MCPWM_INT_ST_TIMER2_TEP_INT_ST = 0x100 + // Position of FAULT0_INT_ST field. + MCPWM_INT_ST_FAULT0_INT_ST_Pos = 0x9 + // Bit mask of FAULT0_INT_ST field. + MCPWM_INT_ST_FAULT0_INT_ST_Msk = 0x200 + // Bit FAULT0_INT_ST. + MCPWM_INT_ST_FAULT0_INT_ST = 0x200 + // Position of FAULT1_INT_ST field. + MCPWM_INT_ST_FAULT1_INT_ST_Pos = 0xa + // Bit mask of FAULT1_INT_ST field. + MCPWM_INT_ST_FAULT1_INT_ST_Msk = 0x400 + // Bit FAULT1_INT_ST. + MCPWM_INT_ST_FAULT1_INT_ST = 0x400 + // Position of FAULT2_INT_ST field. + MCPWM_INT_ST_FAULT2_INT_ST_Pos = 0xb + // Bit mask of FAULT2_INT_ST field. + MCPWM_INT_ST_FAULT2_INT_ST_Msk = 0x800 + // Bit FAULT2_INT_ST. + MCPWM_INT_ST_FAULT2_INT_ST = 0x800 + // Position of FAULT0_CLR_INT_ST field. + MCPWM_INT_ST_FAULT0_CLR_INT_ST_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_ST field. + MCPWM_INT_ST_FAULT0_CLR_INT_ST_Msk = 0x1000 + // Bit FAULT0_CLR_INT_ST. + MCPWM_INT_ST_FAULT0_CLR_INT_ST = 0x1000 + // Position of FAULT1_CLR_INT_ST field. + MCPWM_INT_ST_FAULT1_CLR_INT_ST_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_ST field. + MCPWM_INT_ST_FAULT1_CLR_INT_ST_Msk = 0x2000 + // Bit FAULT1_CLR_INT_ST. + MCPWM_INT_ST_FAULT1_CLR_INT_ST = 0x2000 + // Position of FAULT2_CLR_INT_ST field. + MCPWM_INT_ST_FAULT2_CLR_INT_ST_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_ST field. + MCPWM_INT_ST_FAULT2_CLR_INT_ST_Msk = 0x4000 + // Bit FAULT2_CLR_INT_ST. + MCPWM_INT_ST_FAULT2_CLR_INT_ST = 0x4000 + // Position of CMPR0_TEA_INT_ST field. + MCPWM_INT_ST_CMPR0_TEA_INT_ST_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_ST field. + MCPWM_INT_ST_CMPR0_TEA_INT_ST_Msk = 0x8000 + // Bit CMPR0_TEA_INT_ST. + MCPWM_INT_ST_CMPR0_TEA_INT_ST = 0x8000 + // Position of CMPR1_TEA_INT_ST field. + MCPWM_INT_ST_CMPR1_TEA_INT_ST_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_ST field. + MCPWM_INT_ST_CMPR1_TEA_INT_ST_Msk = 0x10000 + // Bit CMPR1_TEA_INT_ST. + MCPWM_INT_ST_CMPR1_TEA_INT_ST = 0x10000 + // Position of CMPR2_TEA_INT_ST field. + MCPWM_INT_ST_CMPR2_TEA_INT_ST_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_ST field. + MCPWM_INT_ST_CMPR2_TEA_INT_ST_Msk = 0x20000 + // Bit CMPR2_TEA_INT_ST. + MCPWM_INT_ST_CMPR2_TEA_INT_ST = 0x20000 + // Position of CMPR0_TEB_INT_ST field. + MCPWM_INT_ST_CMPR0_TEB_INT_ST_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_ST field. + MCPWM_INT_ST_CMPR0_TEB_INT_ST_Msk = 0x40000 + // Bit CMPR0_TEB_INT_ST. + MCPWM_INT_ST_CMPR0_TEB_INT_ST = 0x40000 + // Position of CMPR1_TEB_INT_ST field. + MCPWM_INT_ST_CMPR1_TEB_INT_ST_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_ST field. + MCPWM_INT_ST_CMPR1_TEB_INT_ST_Msk = 0x80000 + // Bit CMPR1_TEB_INT_ST. + MCPWM_INT_ST_CMPR1_TEB_INT_ST = 0x80000 + // Position of CMPR2_TEB_INT_ST field. + MCPWM_INT_ST_CMPR2_TEB_INT_ST_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_ST field. + MCPWM_INT_ST_CMPR2_TEB_INT_ST_Msk = 0x100000 + // Bit CMPR2_TEB_INT_ST. + MCPWM_INT_ST_CMPR2_TEB_INT_ST = 0x100000 + // Position of TZ0_CBC_INT_ST field. + MCPWM_INT_ST_TZ0_CBC_INT_ST_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_ST field. + MCPWM_INT_ST_TZ0_CBC_INT_ST_Msk = 0x200000 + // Bit TZ0_CBC_INT_ST. + MCPWM_INT_ST_TZ0_CBC_INT_ST = 0x200000 + // Position of TZ1_CBC_INT_ST field. + MCPWM_INT_ST_TZ1_CBC_INT_ST_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_ST field. + MCPWM_INT_ST_TZ1_CBC_INT_ST_Msk = 0x400000 + // Bit TZ1_CBC_INT_ST. + MCPWM_INT_ST_TZ1_CBC_INT_ST = 0x400000 + // Position of TZ2_CBC_INT_ST field. + MCPWM_INT_ST_TZ2_CBC_INT_ST_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_ST field. + MCPWM_INT_ST_TZ2_CBC_INT_ST_Msk = 0x800000 + // Bit TZ2_CBC_INT_ST. + MCPWM_INT_ST_TZ2_CBC_INT_ST = 0x800000 + // Position of TZ0_OST_INT_ST field. + MCPWM_INT_ST_TZ0_OST_INT_ST_Pos = 0x18 + // Bit mask of TZ0_OST_INT_ST field. + MCPWM_INT_ST_TZ0_OST_INT_ST_Msk = 0x1000000 + // Bit TZ0_OST_INT_ST. + MCPWM_INT_ST_TZ0_OST_INT_ST = 0x1000000 + // Position of TZ1_OST_INT_ST field. + MCPWM_INT_ST_TZ1_OST_INT_ST_Pos = 0x19 + // Bit mask of TZ1_OST_INT_ST field. + MCPWM_INT_ST_TZ1_OST_INT_ST_Msk = 0x2000000 + // Bit TZ1_OST_INT_ST. + MCPWM_INT_ST_TZ1_OST_INT_ST = 0x2000000 + // Position of TZ2_OST_INT_ST field. + MCPWM_INT_ST_TZ2_OST_INT_ST_Pos = 0x1a + // Bit mask of TZ2_OST_INT_ST field. + MCPWM_INT_ST_TZ2_OST_INT_ST_Msk = 0x4000000 + // Bit TZ2_OST_INT_ST. + MCPWM_INT_ST_TZ2_OST_INT_ST = 0x4000000 + // Position of CAP0_INT_ST field. + MCPWM_INT_ST_CAP0_INT_ST_Pos = 0x1b + // Bit mask of CAP0_INT_ST field. + MCPWM_INT_ST_CAP0_INT_ST_Msk = 0x8000000 + // Bit CAP0_INT_ST. + MCPWM_INT_ST_CAP0_INT_ST = 0x8000000 + // Position of CAP1_INT_ST field. + MCPWM_INT_ST_CAP1_INT_ST_Pos = 0x1c + // Bit mask of CAP1_INT_ST field. + MCPWM_INT_ST_CAP1_INT_ST_Msk = 0x10000000 + // Bit CAP1_INT_ST. + MCPWM_INT_ST_CAP1_INT_ST = 0x10000000 + // Position of CAP2_INT_ST field. + MCPWM_INT_ST_CAP2_INT_ST_Pos = 0x1d + // Bit mask of CAP2_INT_ST field. + MCPWM_INT_ST_CAP2_INT_ST_Msk = 0x20000000 + // Bit CAP2_INT_ST. + MCPWM_INT_ST_CAP2_INT_ST = 0x20000000 + + // INT_CLR: Interrupt clear bits + // Position of TIMER0_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_STOP_INT_CLR_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_STOP_INT_CLR_Msk = 0x1 + // Bit TIMER0_STOP_INT_CLR. + MCPWM_INT_CLR_TIMER0_STOP_INT_CLR = 0x1 + // Position of TIMER1_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_STOP_INT_CLR_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_STOP_INT_CLR_Msk = 0x2 + // Bit TIMER1_STOP_INT_CLR. + MCPWM_INT_CLR_TIMER1_STOP_INT_CLR = 0x2 + // Position of TIMER2_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_STOP_INT_CLR_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_STOP_INT_CLR_Msk = 0x4 + // Bit TIMER2_STOP_INT_CLR. + MCPWM_INT_CLR_TIMER2_STOP_INT_CLR = 0x4 + // Position of TIMER0_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR_Msk = 0x8 + // Bit TIMER0_TEZ_INT_CLR. + MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR = 0x8 + // Position of TIMER1_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR_Msk = 0x10 + // Bit TIMER1_TEZ_INT_CLR. + MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR = 0x10 + // Position of TIMER2_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR_Msk = 0x20 + // Bit TIMER2_TEZ_INT_CLR. + MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR = 0x20 + // Position of TIMER0_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEP_INT_CLR_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEP_INT_CLR_Msk = 0x40 + // Bit TIMER0_TEP_INT_CLR. + MCPWM_INT_CLR_TIMER0_TEP_INT_CLR = 0x40 + // Position of TIMER1_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEP_INT_CLR_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEP_INT_CLR_Msk = 0x80 + // Bit TIMER1_TEP_INT_CLR. + MCPWM_INT_CLR_TIMER1_TEP_INT_CLR = 0x80 + // Position of TIMER2_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEP_INT_CLR_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEP_INT_CLR_Msk = 0x100 + // Bit TIMER2_TEP_INT_CLR. + MCPWM_INT_CLR_TIMER2_TEP_INT_CLR = 0x100 + // Position of FAULT0_INT_CLR field. + MCPWM_INT_CLR_FAULT0_INT_CLR_Pos = 0x9 + // Bit mask of FAULT0_INT_CLR field. + MCPWM_INT_CLR_FAULT0_INT_CLR_Msk = 0x200 + // Bit FAULT0_INT_CLR. + MCPWM_INT_CLR_FAULT0_INT_CLR = 0x200 + // Position of FAULT1_INT_CLR field. + MCPWM_INT_CLR_FAULT1_INT_CLR_Pos = 0xa + // Bit mask of FAULT1_INT_CLR field. + MCPWM_INT_CLR_FAULT1_INT_CLR_Msk = 0x400 + // Bit FAULT1_INT_CLR. + MCPWM_INT_CLR_FAULT1_INT_CLR = 0x400 + // Position of FAULT2_INT_CLR field. + MCPWM_INT_CLR_FAULT2_INT_CLR_Pos = 0xb + // Bit mask of FAULT2_INT_CLR field. + MCPWM_INT_CLR_FAULT2_INT_CLR_Msk = 0x800 + // Bit FAULT2_INT_CLR. + MCPWM_INT_CLR_FAULT2_INT_CLR = 0x800 + // Position of FAULT0_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT0_CLR_INT_CLR_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT0_CLR_INT_CLR_Msk = 0x1000 + // Bit FAULT0_CLR_INT_CLR. + MCPWM_INT_CLR_FAULT0_CLR_INT_CLR = 0x1000 + // Position of FAULT1_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT1_CLR_INT_CLR_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT1_CLR_INT_CLR_Msk = 0x2000 + // Bit FAULT1_CLR_INT_CLR. + MCPWM_INT_CLR_FAULT1_CLR_INT_CLR = 0x2000 + // Position of FAULT2_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT2_CLR_INT_CLR_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT2_CLR_INT_CLR_Msk = 0x4000 + // Bit FAULT2_CLR_INT_CLR. + MCPWM_INT_CLR_FAULT2_CLR_INT_CLR = 0x4000 + // Position of CMPR0_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR0_TEA_INT_CLR_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR0_TEA_INT_CLR_Msk = 0x8000 + // Bit CMPR0_TEA_INT_CLR. + MCPWM_INT_CLR_CMPR0_TEA_INT_CLR = 0x8000 + // Position of CMPR1_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR1_TEA_INT_CLR_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR1_TEA_INT_CLR_Msk = 0x10000 + // Bit CMPR1_TEA_INT_CLR. + MCPWM_INT_CLR_CMPR1_TEA_INT_CLR = 0x10000 + // Position of CMPR2_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR2_TEA_INT_CLR_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR2_TEA_INT_CLR_Msk = 0x20000 + // Bit CMPR2_TEA_INT_CLR. + MCPWM_INT_CLR_CMPR2_TEA_INT_CLR = 0x20000 + // Position of CMPR0_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR0_TEB_INT_CLR_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR0_TEB_INT_CLR_Msk = 0x40000 + // Bit CMPR0_TEB_INT_CLR. + MCPWM_INT_CLR_CMPR0_TEB_INT_CLR = 0x40000 + // Position of CMPR1_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR1_TEB_INT_CLR_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR1_TEB_INT_CLR_Msk = 0x80000 + // Bit CMPR1_TEB_INT_CLR. + MCPWM_INT_CLR_CMPR1_TEB_INT_CLR = 0x80000 + // Position of CMPR2_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR2_TEB_INT_CLR_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR2_TEB_INT_CLR_Msk = 0x100000 + // Bit CMPR2_TEB_INT_CLR. + MCPWM_INT_CLR_CMPR2_TEB_INT_CLR = 0x100000 + // Position of TZ0_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ0_CBC_INT_CLR_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ0_CBC_INT_CLR_Msk = 0x200000 + // Bit TZ0_CBC_INT_CLR. + MCPWM_INT_CLR_TZ0_CBC_INT_CLR = 0x200000 + // Position of TZ1_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ1_CBC_INT_CLR_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ1_CBC_INT_CLR_Msk = 0x400000 + // Bit TZ1_CBC_INT_CLR. + MCPWM_INT_CLR_TZ1_CBC_INT_CLR = 0x400000 + // Position of TZ2_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ2_CBC_INT_CLR_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ2_CBC_INT_CLR_Msk = 0x800000 + // Bit TZ2_CBC_INT_CLR. + MCPWM_INT_CLR_TZ2_CBC_INT_CLR = 0x800000 + // Position of TZ0_OST_INT_CLR field. + MCPWM_INT_CLR_TZ0_OST_INT_CLR_Pos = 0x18 + // Bit mask of TZ0_OST_INT_CLR field. + MCPWM_INT_CLR_TZ0_OST_INT_CLR_Msk = 0x1000000 + // Bit TZ0_OST_INT_CLR. + MCPWM_INT_CLR_TZ0_OST_INT_CLR = 0x1000000 + // Position of TZ1_OST_INT_CLR field. + MCPWM_INT_CLR_TZ1_OST_INT_CLR_Pos = 0x19 + // Bit mask of TZ1_OST_INT_CLR field. + MCPWM_INT_CLR_TZ1_OST_INT_CLR_Msk = 0x2000000 + // Bit TZ1_OST_INT_CLR. + MCPWM_INT_CLR_TZ1_OST_INT_CLR = 0x2000000 + // Position of TZ2_OST_INT_CLR field. + MCPWM_INT_CLR_TZ2_OST_INT_CLR_Pos = 0x1a + // Bit mask of TZ2_OST_INT_CLR field. + MCPWM_INT_CLR_TZ2_OST_INT_CLR_Msk = 0x4000000 + // Bit TZ2_OST_INT_CLR. + MCPWM_INT_CLR_TZ2_OST_INT_CLR = 0x4000000 + // Position of CAP0_INT_CLR field. + MCPWM_INT_CLR_CAP0_INT_CLR_Pos = 0x1b + // Bit mask of CAP0_INT_CLR field. + MCPWM_INT_CLR_CAP0_INT_CLR_Msk = 0x8000000 + // Bit CAP0_INT_CLR. + MCPWM_INT_CLR_CAP0_INT_CLR = 0x8000000 + // Position of CAP1_INT_CLR field. + MCPWM_INT_CLR_CAP1_INT_CLR_Pos = 0x1c + // Bit mask of CAP1_INT_CLR field. + MCPWM_INT_CLR_CAP1_INT_CLR_Msk = 0x10000000 + // Bit CAP1_INT_CLR. + MCPWM_INT_CLR_CAP1_INT_CLR = 0x10000000 + // Position of CAP2_INT_CLR field. + MCPWM_INT_CLR_CAP2_INT_CLR_Pos = 0x1d + // Bit mask of CAP2_INT_CLR field. + MCPWM_INT_CLR_CAP2_INT_CLR_Msk = 0x20000000 + // Bit CAP2_INT_CLR. + MCPWM_INT_CLR_CAP2_INT_CLR = 0x20000000 + + // EVT_EN: MCPWM event enable register + // Position of EVT_TIMER0_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER0_STOP_EN_Pos = 0x0 + // Bit mask of EVT_TIMER0_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER0_STOP_EN_Msk = 0x1 + // Bit EVT_TIMER0_STOP_EN. + MCPWM_EVT_EN_EVT_TIMER0_STOP_EN = 0x1 + // Position of EVT_TIMER1_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER1_STOP_EN_Pos = 0x1 + // Bit mask of EVT_TIMER1_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER1_STOP_EN_Msk = 0x2 + // Bit EVT_TIMER1_STOP_EN. + MCPWM_EVT_EN_EVT_TIMER1_STOP_EN = 0x2 + // Position of EVT_TIMER2_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER2_STOP_EN_Pos = 0x2 + // Bit mask of EVT_TIMER2_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER2_STOP_EN_Msk = 0x4 + // Bit EVT_TIMER2_STOP_EN. + MCPWM_EVT_EN_EVT_TIMER2_STOP_EN = 0x4 + // Position of EVT_TIMER0_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER0_TEZ_EN_Pos = 0x3 + // Bit mask of EVT_TIMER0_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER0_TEZ_EN_Msk = 0x8 + // Bit EVT_TIMER0_TEZ_EN. + MCPWM_EVT_EN_EVT_TIMER0_TEZ_EN = 0x8 + // Position of EVT_TIMER1_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER1_TEZ_EN_Pos = 0x4 + // Bit mask of EVT_TIMER1_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER1_TEZ_EN_Msk = 0x10 + // Bit EVT_TIMER1_TEZ_EN. + MCPWM_EVT_EN_EVT_TIMER1_TEZ_EN = 0x10 + // Position of EVT_TIMER2_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER2_TEZ_EN_Pos = 0x5 + // Bit mask of EVT_TIMER2_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER2_TEZ_EN_Msk = 0x20 + // Bit EVT_TIMER2_TEZ_EN. + MCPWM_EVT_EN_EVT_TIMER2_TEZ_EN = 0x20 + // Position of EVT_TIMER0_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER0_TEP_EN_Pos = 0x6 + // Bit mask of EVT_TIMER0_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER0_TEP_EN_Msk = 0x40 + // Bit EVT_TIMER0_TEP_EN. + MCPWM_EVT_EN_EVT_TIMER0_TEP_EN = 0x40 + // Position of EVT_TIMER1_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER1_TEP_EN_Pos = 0x7 + // Bit mask of EVT_TIMER1_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER1_TEP_EN_Msk = 0x80 + // Bit EVT_TIMER1_TEP_EN. + MCPWM_EVT_EN_EVT_TIMER1_TEP_EN = 0x80 + // Position of EVT_TIMER2_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER2_TEP_EN_Pos = 0x8 + // Bit mask of EVT_TIMER2_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER2_TEP_EN_Msk = 0x100 + // Bit EVT_TIMER2_TEP_EN. + MCPWM_EVT_EN_EVT_TIMER2_TEP_EN = 0x100 + // Position of EVT_OP0_TEA_EN field. + MCPWM_EVT_EN_EVT_OP0_TEA_EN_Pos = 0x9 + // Bit mask of EVT_OP0_TEA_EN field. + MCPWM_EVT_EN_EVT_OP0_TEA_EN_Msk = 0x200 + // Bit EVT_OP0_TEA_EN. + MCPWM_EVT_EN_EVT_OP0_TEA_EN = 0x200 + // Position of EVT_OP1_TEA_EN field. + MCPWM_EVT_EN_EVT_OP1_TEA_EN_Pos = 0xa + // Bit mask of EVT_OP1_TEA_EN field. + MCPWM_EVT_EN_EVT_OP1_TEA_EN_Msk = 0x400 + // Bit EVT_OP1_TEA_EN. + MCPWM_EVT_EN_EVT_OP1_TEA_EN = 0x400 + // Position of EVT_OP2_TEA_EN field. + MCPWM_EVT_EN_EVT_OP2_TEA_EN_Pos = 0xb + // Bit mask of EVT_OP2_TEA_EN field. + MCPWM_EVT_EN_EVT_OP2_TEA_EN_Msk = 0x800 + // Bit EVT_OP2_TEA_EN. + MCPWM_EVT_EN_EVT_OP2_TEA_EN = 0x800 + // Position of EVT_OP0_TEB_EN field. + MCPWM_EVT_EN_EVT_OP0_TEB_EN_Pos = 0xc + // Bit mask of EVT_OP0_TEB_EN field. + MCPWM_EVT_EN_EVT_OP0_TEB_EN_Msk = 0x1000 + // Bit EVT_OP0_TEB_EN. + MCPWM_EVT_EN_EVT_OP0_TEB_EN = 0x1000 + // Position of EVT_OP1_TEB_EN field. + MCPWM_EVT_EN_EVT_OP1_TEB_EN_Pos = 0xd + // Bit mask of EVT_OP1_TEB_EN field. + MCPWM_EVT_EN_EVT_OP1_TEB_EN_Msk = 0x2000 + // Bit EVT_OP1_TEB_EN. + MCPWM_EVT_EN_EVT_OP1_TEB_EN = 0x2000 + // Position of EVT_OP2_TEB_EN field. + MCPWM_EVT_EN_EVT_OP2_TEB_EN_Pos = 0xe + // Bit mask of EVT_OP2_TEB_EN field. + MCPWM_EVT_EN_EVT_OP2_TEB_EN_Msk = 0x4000 + // Bit EVT_OP2_TEB_EN. + MCPWM_EVT_EN_EVT_OP2_TEB_EN = 0x4000 + // Position of EVT_F0_EN field. + MCPWM_EVT_EN_EVT_F0_EN_Pos = 0xf + // Bit mask of EVT_F0_EN field. + MCPWM_EVT_EN_EVT_F0_EN_Msk = 0x8000 + // Bit EVT_F0_EN. + MCPWM_EVT_EN_EVT_F0_EN = 0x8000 + // Position of EVT_F1_EN field. + MCPWM_EVT_EN_EVT_F1_EN_Pos = 0x10 + // Bit mask of EVT_F1_EN field. + MCPWM_EVT_EN_EVT_F1_EN_Msk = 0x10000 + // Bit EVT_F1_EN. + MCPWM_EVT_EN_EVT_F1_EN = 0x10000 + // Position of EVT_F2_EN field. + MCPWM_EVT_EN_EVT_F2_EN_Pos = 0x11 + // Bit mask of EVT_F2_EN field. + MCPWM_EVT_EN_EVT_F2_EN_Msk = 0x20000 + // Bit EVT_F2_EN. + MCPWM_EVT_EN_EVT_F2_EN = 0x20000 + // Position of EVT_F0_CLR_EN field. + MCPWM_EVT_EN_EVT_F0_CLR_EN_Pos = 0x12 + // Bit mask of EVT_F0_CLR_EN field. + MCPWM_EVT_EN_EVT_F0_CLR_EN_Msk = 0x40000 + // Bit EVT_F0_CLR_EN. + MCPWM_EVT_EN_EVT_F0_CLR_EN = 0x40000 + // Position of EVT_F1_CLR_EN field. + MCPWM_EVT_EN_EVT_F1_CLR_EN_Pos = 0x13 + // Bit mask of EVT_F1_CLR_EN field. + MCPWM_EVT_EN_EVT_F1_CLR_EN_Msk = 0x80000 + // Bit EVT_F1_CLR_EN. + MCPWM_EVT_EN_EVT_F1_CLR_EN = 0x80000 + // Position of EVT_F2_CLR_EN field. + MCPWM_EVT_EN_EVT_F2_CLR_EN_Pos = 0x14 + // Bit mask of EVT_F2_CLR_EN field. + MCPWM_EVT_EN_EVT_F2_CLR_EN_Msk = 0x100000 + // Bit EVT_F2_CLR_EN. + MCPWM_EVT_EN_EVT_F2_CLR_EN = 0x100000 + // Position of EVT_TZ0_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ0_CBC_EN_Pos = 0x15 + // Bit mask of EVT_TZ0_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ0_CBC_EN_Msk = 0x200000 + // Bit EVT_TZ0_CBC_EN. + MCPWM_EVT_EN_EVT_TZ0_CBC_EN = 0x200000 + // Position of EVT_TZ1_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ1_CBC_EN_Pos = 0x16 + // Bit mask of EVT_TZ1_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ1_CBC_EN_Msk = 0x400000 + // Bit EVT_TZ1_CBC_EN. + MCPWM_EVT_EN_EVT_TZ1_CBC_EN = 0x400000 + // Position of EVT_TZ2_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ2_CBC_EN_Pos = 0x17 + // Bit mask of EVT_TZ2_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ2_CBC_EN_Msk = 0x800000 + // Bit EVT_TZ2_CBC_EN. + MCPWM_EVT_EN_EVT_TZ2_CBC_EN = 0x800000 + // Position of EVT_TZ0_OST_EN field. + MCPWM_EVT_EN_EVT_TZ0_OST_EN_Pos = 0x18 + // Bit mask of EVT_TZ0_OST_EN field. + MCPWM_EVT_EN_EVT_TZ0_OST_EN_Msk = 0x1000000 + // Bit EVT_TZ0_OST_EN. + MCPWM_EVT_EN_EVT_TZ0_OST_EN = 0x1000000 + // Position of EVT_TZ1_OST_EN field. + MCPWM_EVT_EN_EVT_TZ1_OST_EN_Pos = 0x19 + // Bit mask of EVT_TZ1_OST_EN field. + MCPWM_EVT_EN_EVT_TZ1_OST_EN_Msk = 0x2000000 + // Bit EVT_TZ1_OST_EN. + MCPWM_EVT_EN_EVT_TZ1_OST_EN = 0x2000000 + // Position of EVT_TZ2_OST_EN field. + MCPWM_EVT_EN_EVT_TZ2_OST_EN_Pos = 0x1a + // Bit mask of EVT_TZ2_OST_EN field. + MCPWM_EVT_EN_EVT_TZ2_OST_EN_Msk = 0x4000000 + // Bit EVT_TZ2_OST_EN. + MCPWM_EVT_EN_EVT_TZ2_OST_EN = 0x4000000 + // Position of EVT_CAP0_EN field. + MCPWM_EVT_EN_EVT_CAP0_EN_Pos = 0x1b + // Bit mask of EVT_CAP0_EN field. + MCPWM_EVT_EN_EVT_CAP0_EN_Msk = 0x8000000 + // Bit EVT_CAP0_EN. + MCPWM_EVT_EN_EVT_CAP0_EN = 0x8000000 + // Position of EVT_CAP1_EN field. + MCPWM_EVT_EN_EVT_CAP1_EN_Pos = 0x1c + // Bit mask of EVT_CAP1_EN field. + MCPWM_EVT_EN_EVT_CAP1_EN_Msk = 0x10000000 + // Bit EVT_CAP1_EN. + MCPWM_EVT_EN_EVT_CAP1_EN = 0x10000000 + // Position of EVT_CAP2_EN field. + MCPWM_EVT_EN_EVT_CAP2_EN_Pos = 0x1d + // Bit mask of EVT_CAP2_EN field. + MCPWM_EVT_EN_EVT_CAP2_EN_Msk = 0x20000000 + // Bit EVT_CAP2_EN. + MCPWM_EVT_EN_EVT_CAP2_EN = 0x20000000 + + // TASK_EN: MCPWM task enable register + // Position of TASK_CMPR0_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR0_A_UP_EN_Pos = 0x0 + // Bit mask of TASK_CMPR0_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR0_A_UP_EN_Msk = 0x1 + // Bit TASK_CMPR0_A_UP_EN. + MCPWM_TASK_EN_TASK_CMPR0_A_UP_EN = 0x1 + // Position of TASK_CMPR1_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR1_A_UP_EN_Pos = 0x1 + // Bit mask of TASK_CMPR1_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR1_A_UP_EN_Msk = 0x2 + // Bit TASK_CMPR1_A_UP_EN. + MCPWM_TASK_EN_TASK_CMPR1_A_UP_EN = 0x2 + // Position of TASK_CMPR2_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR2_A_UP_EN_Pos = 0x2 + // Bit mask of TASK_CMPR2_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR2_A_UP_EN_Msk = 0x4 + // Bit TASK_CMPR2_A_UP_EN. + MCPWM_TASK_EN_TASK_CMPR2_A_UP_EN = 0x4 + // Position of TASK_CMPR0_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR0_B_UP_EN_Pos = 0x3 + // Bit mask of TASK_CMPR0_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR0_B_UP_EN_Msk = 0x8 + // Bit TASK_CMPR0_B_UP_EN. + MCPWM_TASK_EN_TASK_CMPR0_B_UP_EN = 0x8 + // Position of TASK_CMPR1_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR1_B_UP_EN_Pos = 0x4 + // Bit mask of TASK_CMPR1_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR1_B_UP_EN_Msk = 0x10 + // Bit TASK_CMPR1_B_UP_EN. + MCPWM_TASK_EN_TASK_CMPR1_B_UP_EN = 0x10 + // Position of TASK_CMPR2_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR2_B_UP_EN_Pos = 0x5 + // Bit mask of TASK_CMPR2_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR2_B_UP_EN_Msk = 0x20 + // Bit TASK_CMPR2_B_UP_EN. + MCPWM_TASK_EN_TASK_CMPR2_B_UP_EN = 0x20 + // Position of TASK_GEN_STOP_EN field. + MCPWM_TASK_EN_TASK_GEN_STOP_EN_Pos = 0x6 + // Bit mask of TASK_GEN_STOP_EN field. + MCPWM_TASK_EN_TASK_GEN_STOP_EN_Msk = 0x40 + // Bit TASK_GEN_STOP_EN. + MCPWM_TASK_EN_TASK_GEN_STOP_EN = 0x40 + // Position of TASK_TIMER0_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER0_SYNC_EN_Pos = 0x7 + // Bit mask of TASK_TIMER0_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER0_SYNC_EN_Msk = 0x80 + // Bit TASK_TIMER0_SYNC_EN. + MCPWM_TASK_EN_TASK_TIMER0_SYNC_EN = 0x80 + // Position of TASK_TIMER1_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER1_SYNC_EN_Pos = 0x8 + // Bit mask of TASK_TIMER1_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER1_SYNC_EN_Msk = 0x100 + // Bit TASK_TIMER1_SYNC_EN. + MCPWM_TASK_EN_TASK_TIMER1_SYNC_EN = 0x100 + // Position of TASK_TIMER2_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER2_SYNC_EN_Pos = 0x9 + // Bit mask of TASK_TIMER2_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER2_SYNC_EN_Msk = 0x200 + // Bit TASK_TIMER2_SYNC_EN. + MCPWM_TASK_EN_TASK_TIMER2_SYNC_EN = 0x200 + // Position of TASK_TIMER0_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER0_PERIOD_UP_EN_Pos = 0xa + // Bit mask of TASK_TIMER0_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER0_PERIOD_UP_EN_Msk = 0x400 + // Bit TASK_TIMER0_PERIOD_UP_EN. + MCPWM_TASK_EN_TASK_TIMER0_PERIOD_UP_EN = 0x400 + // Position of TASK_TIMER1_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER1_PERIOD_UP_EN_Pos = 0xb + // Bit mask of TASK_TIMER1_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER1_PERIOD_UP_EN_Msk = 0x800 + // Bit TASK_TIMER1_PERIOD_UP_EN. + MCPWM_TASK_EN_TASK_TIMER1_PERIOD_UP_EN = 0x800 + // Position of TASK_TIMER2_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER2_PERIOD_UP_EN_Pos = 0xc + // Bit mask of TASK_TIMER2_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER2_PERIOD_UP_EN_Msk = 0x1000 + // Bit TASK_TIMER2_PERIOD_UP_EN. + MCPWM_TASK_EN_TASK_TIMER2_PERIOD_UP_EN = 0x1000 + // Position of TASK_TZ0_OST_EN field. + MCPWM_TASK_EN_TASK_TZ0_OST_EN_Pos = 0xd + // Bit mask of TASK_TZ0_OST_EN field. + MCPWM_TASK_EN_TASK_TZ0_OST_EN_Msk = 0x2000 + // Bit TASK_TZ0_OST_EN. + MCPWM_TASK_EN_TASK_TZ0_OST_EN = 0x2000 + // Position of TASK_TZ1_OST_EN field. + MCPWM_TASK_EN_TASK_TZ1_OST_EN_Pos = 0xe + // Bit mask of TASK_TZ1_OST_EN field. + MCPWM_TASK_EN_TASK_TZ1_OST_EN_Msk = 0x4000 + // Bit TASK_TZ1_OST_EN. + MCPWM_TASK_EN_TASK_TZ1_OST_EN = 0x4000 + // Position of TASK_TZ2_OST_EN field. + MCPWM_TASK_EN_TASK_TZ2_OST_EN_Pos = 0xf + // Bit mask of TASK_TZ2_OST_EN field. + MCPWM_TASK_EN_TASK_TZ2_OST_EN_Msk = 0x8000 + // Bit TASK_TZ2_OST_EN. + MCPWM_TASK_EN_TASK_TZ2_OST_EN = 0x8000 + // Position of TASK_CLR0_OST_EN field. + MCPWM_TASK_EN_TASK_CLR0_OST_EN_Pos = 0x10 + // Bit mask of TASK_CLR0_OST_EN field. + MCPWM_TASK_EN_TASK_CLR0_OST_EN_Msk = 0x10000 + // Bit TASK_CLR0_OST_EN. + MCPWM_TASK_EN_TASK_CLR0_OST_EN = 0x10000 + // Position of TASK_CLR1_OST_EN field. + MCPWM_TASK_EN_TASK_CLR1_OST_EN_Pos = 0x11 + // Bit mask of TASK_CLR1_OST_EN field. + MCPWM_TASK_EN_TASK_CLR1_OST_EN_Msk = 0x20000 + // Bit TASK_CLR1_OST_EN. + MCPWM_TASK_EN_TASK_CLR1_OST_EN = 0x20000 + // Position of TASK_CLR2_OST_EN field. + MCPWM_TASK_EN_TASK_CLR2_OST_EN_Pos = 0x12 + // Bit mask of TASK_CLR2_OST_EN field. + MCPWM_TASK_EN_TASK_CLR2_OST_EN_Msk = 0x40000 + // Bit TASK_CLR2_OST_EN. + MCPWM_TASK_EN_TASK_CLR2_OST_EN = 0x40000 + // Position of TASK_CAP0_EN field. + MCPWM_TASK_EN_TASK_CAP0_EN_Pos = 0x13 + // Bit mask of TASK_CAP0_EN field. + MCPWM_TASK_EN_TASK_CAP0_EN_Msk = 0x80000 + // Bit TASK_CAP0_EN. + MCPWM_TASK_EN_TASK_CAP0_EN = 0x80000 + // Position of TASK_CAP1_EN field. + MCPWM_TASK_EN_TASK_CAP1_EN_Pos = 0x14 + // Bit mask of TASK_CAP1_EN field. + MCPWM_TASK_EN_TASK_CAP1_EN_Msk = 0x100000 + // Bit TASK_CAP1_EN. + MCPWM_TASK_EN_TASK_CAP1_EN = 0x100000 + // Position of TASK_CAP2_EN field. + MCPWM_TASK_EN_TASK_CAP2_EN_Pos = 0x15 + // Bit mask of TASK_CAP2_EN field. + MCPWM_TASK_EN_TASK_CAP2_EN_Msk = 0x200000 + // Bit TASK_CAP2_EN. + MCPWM_TASK_EN_TASK_CAP2_EN = 0x200000 + + // CLK: MCPWM APB configuration register + // Position of EN field. + MCPWM_CLK_EN_Pos = 0x0 + // Bit mask of EN field. + MCPWM_CLK_EN_Msk = 0x1 + // Bit EN. + MCPWM_CLK_EN = 0x1 + + // VERSION: Version register. + // Position of DATE field. + MCPWM_VERSION_DATE_Pos = 0x0 + // Bit mask of DATE field. + MCPWM_VERSION_DATE_Msk = 0xfffffff +) + +// Constants for MEM_MONITOR: MEM_MONITOR Peripheral +const ( + // LOG_SETTING: log config regsiter + // Position of LOG_ENA field. + MEM_MONITOR_LOG_SETTING_LOG_ENA_Pos = 0x0 + // Bit mask of LOG_ENA field. + MEM_MONITOR_LOG_SETTING_LOG_ENA_Msk = 0x7 + // Position of LOG_MODE field. + MEM_MONITOR_LOG_SETTING_LOG_MODE_Pos = 0x3 + // Bit mask of LOG_MODE field. + MEM_MONITOR_LOG_SETTING_LOG_MODE_Msk = 0x78 + // Position of LOG_MEM_LOOP_ENABLE field. + MEM_MONITOR_LOG_SETTING_LOG_MEM_LOOP_ENABLE_Pos = 0x7 + // Bit mask of LOG_MEM_LOOP_ENABLE field. + MEM_MONITOR_LOG_SETTING_LOG_MEM_LOOP_ENABLE_Msk = 0x80 + // Bit LOG_MEM_LOOP_ENABLE. + MEM_MONITOR_LOG_SETTING_LOG_MEM_LOOP_ENABLE = 0x80 + + // LOG_CHECK_DATA: check data regsiter + // Position of LOG_CHECK_DATA field. + MEM_MONITOR_LOG_CHECK_DATA_LOG_CHECK_DATA_Pos = 0x0 + // Bit mask of LOG_CHECK_DATA field. + MEM_MONITOR_LOG_CHECK_DATA_LOG_CHECK_DATA_Msk = 0xffffffff + + // LOG_DATA_MASK: check data mask register + // Position of LOG_DATA_MASK field. + MEM_MONITOR_LOG_DATA_MASK_LOG_DATA_MASK_Pos = 0x0 + // Bit mask of LOG_DATA_MASK field. + MEM_MONITOR_LOG_DATA_MASK_LOG_DATA_MASK_Msk = 0xf + + // LOG_MIN: log boundary regsiter + // Position of LOG_MIN field. + MEM_MONITOR_LOG_MIN_LOG_MIN_Pos = 0x0 + // Bit mask of LOG_MIN field. + MEM_MONITOR_LOG_MIN_LOG_MIN_Msk = 0xffffffff + + // LOG_MAX: log boundary regsiter + // Position of LOG_MAX field. + MEM_MONITOR_LOG_MAX_LOG_MAX_Pos = 0x0 + // Bit mask of LOG_MAX field. + MEM_MONITOR_LOG_MAX_LOG_MAX_Msk = 0xffffffff + + // LOG_MEM_START: log message store range register + // Position of LOG_MEM_START field. + MEM_MONITOR_LOG_MEM_START_LOG_MEM_START_Pos = 0x0 + // Bit mask of LOG_MEM_START field. + MEM_MONITOR_LOG_MEM_START_LOG_MEM_START_Msk = 0xffffffff + + // LOG_MEM_END: log message store range register + // Position of LOG_MEM_END field. + MEM_MONITOR_LOG_MEM_END_LOG_MEM_END_Pos = 0x0 + // Bit mask of LOG_MEM_END field. + MEM_MONITOR_LOG_MEM_END_LOG_MEM_END_Msk = 0xffffffff + + // LOG_MEM_CURRENT_ADDR: current writing address. + // Position of LOG_MEM_CURRENT_ADDR field. + MEM_MONITOR_LOG_MEM_CURRENT_ADDR_LOG_MEM_CURRENT_ADDR_Pos = 0x0 + // Bit mask of LOG_MEM_CURRENT_ADDR field. + MEM_MONITOR_LOG_MEM_CURRENT_ADDR_LOG_MEM_CURRENT_ADDR_Msk = 0xffffffff + + // LOG_MEM_ADDR_UPDATE: writing address update + // Position of LOG_MEM_ADDR_UPDATE field. + MEM_MONITOR_LOG_MEM_ADDR_UPDATE_LOG_MEM_ADDR_UPDATE_Pos = 0x0 + // Bit mask of LOG_MEM_ADDR_UPDATE field. + MEM_MONITOR_LOG_MEM_ADDR_UPDATE_LOG_MEM_ADDR_UPDATE_Msk = 0x1 + // Bit LOG_MEM_ADDR_UPDATE. + MEM_MONITOR_LOG_MEM_ADDR_UPDATE_LOG_MEM_ADDR_UPDATE = 0x1 + + // LOG_MEM_FULL_FLAG: full flag status register + // Position of LOG_MEM_FULL_FLAG field. + MEM_MONITOR_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG_Pos = 0x0 + // Bit mask of LOG_MEM_FULL_FLAG field. + MEM_MONITOR_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG_Msk = 0x1 + // Bit LOG_MEM_FULL_FLAG. + MEM_MONITOR_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG = 0x1 + // Position of CLR_LOG_MEM_FULL_FLAG field. + MEM_MONITOR_LOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG_Pos = 0x1 + // Bit mask of CLR_LOG_MEM_FULL_FLAG field. + MEM_MONITOR_LOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG_Msk = 0x2 + // Bit CLR_LOG_MEM_FULL_FLAG. + MEM_MONITOR_LOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG = 0x2 + + // CLOCK_GATE: clock gate force on register + // Position of CLK_EN field. + MEM_MONITOR_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + MEM_MONITOR_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + MEM_MONITOR_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: version register + // Position of DATE field. + MEM_MONITOR_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + MEM_MONITOR_DATE_DATE_Msk = 0xfffffff +) + +// Constants for MODEM_LPCON: MODEM_LPCON Peripheral +const ( + // TEST_CONF + // Position of CLK_EN field. + MODEM_LPCON_TEST_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + MODEM_LPCON_TEST_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + MODEM_LPCON_TEST_CONF_CLK_EN = 0x1 + // Position of CLK_DEBUG_ENA field. + MODEM_LPCON_TEST_CONF_CLK_DEBUG_ENA_Pos = 0x1 + // Bit mask of CLK_DEBUG_ENA field. + MODEM_LPCON_TEST_CONF_CLK_DEBUG_ENA_Msk = 0x2 + // Bit CLK_DEBUG_ENA. + MODEM_LPCON_TEST_CONF_CLK_DEBUG_ENA = 0x2 + + // LP_TIMER_CONF + // Position of CLK_LP_TIMER_SEL_OSC_SLOW field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_SLOW_Pos = 0x0 + // Bit mask of CLK_LP_TIMER_SEL_OSC_SLOW field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_SLOW_Msk = 0x1 + // Bit CLK_LP_TIMER_SEL_OSC_SLOW. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_SLOW = 0x1 + // Position of CLK_LP_TIMER_SEL_OSC_FAST field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_FAST_Pos = 0x1 + // Bit mask of CLK_LP_TIMER_SEL_OSC_FAST field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_FAST_Msk = 0x2 + // Bit CLK_LP_TIMER_SEL_OSC_FAST. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_OSC_FAST = 0x2 + // Position of CLK_LP_TIMER_SEL_XTAL field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL_Pos = 0x2 + // Bit mask of CLK_LP_TIMER_SEL_XTAL field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL_Msk = 0x4 + // Bit CLK_LP_TIMER_SEL_XTAL. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL = 0x4 + // Position of CLK_LP_TIMER_SEL_XTAL32K field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL32K_Pos = 0x3 + // Bit mask of CLK_LP_TIMER_SEL_XTAL32K field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL32K_Msk = 0x8 + // Bit CLK_LP_TIMER_SEL_XTAL32K. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_SEL_XTAL32K = 0x8 + // Position of CLK_LP_TIMER_DIV_NUM field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_DIV_NUM_Pos = 0x4 + // Bit mask of CLK_LP_TIMER_DIV_NUM field. + MODEM_LPCON_LP_TIMER_CONF_CLK_LP_TIMER_DIV_NUM_Msk = 0xfff0 + + // COEX_LP_CLK_CONF + // Position of CLK_COEX_LP_SEL_OSC_SLOW field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW_Pos = 0x0 + // Bit mask of CLK_COEX_LP_SEL_OSC_SLOW field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW_Msk = 0x1 + // Bit CLK_COEX_LP_SEL_OSC_SLOW. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW = 0x1 + // Position of CLK_COEX_LP_SEL_OSC_FAST field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST_Pos = 0x1 + // Bit mask of CLK_COEX_LP_SEL_OSC_FAST field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST_Msk = 0x2 + // Bit CLK_COEX_LP_SEL_OSC_FAST. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST = 0x2 + // Position of CLK_COEX_LP_SEL_XTAL field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL_Pos = 0x2 + // Bit mask of CLK_COEX_LP_SEL_XTAL field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL_Msk = 0x4 + // Bit CLK_COEX_LP_SEL_XTAL. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL = 0x4 + // Position of CLK_COEX_LP_SEL_XTAL32K field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K_Pos = 0x3 + // Bit mask of CLK_COEX_LP_SEL_XTAL32K field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K_Msk = 0x8 + // Bit CLK_COEX_LP_SEL_XTAL32K. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K = 0x8 + // Position of CLK_COEX_LP_DIV_NUM field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_DIV_NUM_Pos = 0x4 + // Bit mask of CLK_COEX_LP_DIV_NUM field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_DIV_NUM_Msk = 0xfff0 + + // WIFI_LP_CLK_CONF + // Position of CLK_WIFIPWR_LP_SEL_OSC_SLOW field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_SLOW_Pos = 0x0 + // Bit mask of CLK_WIFIPWR_LP_SEL_OSC_SLOW field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_SLOW_Msk = 0x1 + // Bit CLK_WIFIPWR_LP_SEL_OSC_SLOW. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_SLOW = 0x1 + // Position of CLK_WIFIPWR_LP_SEL_OSC_FAST field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_FAST_Pos = 0x1 + // Bit mask of CLK_WIFIPWR_LP_SEL_OSC_FAST field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_FAST_Msk = 0x2 + // Bit CLK_WIFIPWR_LP_SEL_OSC_FAST. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_OSC_FAST = 0x2 + // Position of CLK_WIFIPWR_LP_SEL_XTAL field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL_Pos = 0x2 + // Bit mask of CLK_WIFIPWR_LP_SEL_XTAL field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL_Msk = 0x4 + // Bit CLK_WIFIPWR_LP_SEL_XTAL. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL = 0x4 + // Position of CLK_WIFIPWR_LP_SEL_XTAL32K field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL32K_Pos = 0x3 + // Bit mask of CLK_WIFIPWR_LP_SEL_XTAL32K field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL32K_Msk = 0x8 + // Bit CLK_WIFIPWR_LP_SEL_XTAL32K. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_SEL_XTAL32K = 0x8 + // Position of CLK_WIFIPWR_LP_DIV_NUM field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_DIV_NUM_Pos = 0x4 + // Bit mask of CLK_WIFIPWR_LP_DIV_NUM field. + MODEM_LPCON_WIFI_LP_CLK_CONF_CLK_WIFIPWR_LP_DIV_NUM_Msk = 0xfff0 + + // I2C_MST_CLK_CONF + // Position of CLK_I2C_MST_SEL_160M field. + MODEM_LPCON_I2C_MST_CLK_CONF_CLK_I2C_MST_SEL_160M_Pos = 0x0 + // Bit mask of CLK_I2C_MST_SEL_160M field. + MODEM_LPCON_I2C_MST_CLK_CONF_CLK_I2C_MST_SEL_160M_Msk = 0x1 + // Bit CLK_I2C_MST_SEL_160M. + MODEM_LPCON_I2C_MST_CLK_CONF_CLK_I2C_MST_SEL_160M = 0x1 + + // MODEM_32K_CLK_CONF + // Position of CLK_MODEM_32K_SEL field. + MODEM_LPCON_MODEM_32K_CLK_CONF_CLK_MODEM_32K_SEL_Pos = 0x0 + // Bit mask of CLK_MODEM_32K_SEL field. + MODEM_LPCON_MODEM_32K_CLK_CONF_CLK_MODEM_32K_SEL_Msk = 0x3 + + // CLK_CONF + // Position of CLK_WIFIPWR_EN field. + MODEM_LPCON_CLK_CONF_CLK_WIFIPWR_EN_Pos = 0x0 + // Bit mask of CLK_WIFIPWR_EN field. + MODEM_LPCON_CLK_CONF_CLK_WIFIPWR_EN_Msk = 0x1 + // Bit CLK_WIFIPWR_EN. + MODEM_LPCON_CLK_CONF_CLK_WIFIPWR_EN = 0x1 + // Position of CLK_COEX_EN field. + MODEM_LPCON_CLK_CONF_CLK_COEX_EN_Pos = 0x1 + // Bit mask of CLK_COEX_EN field. + MODEM_LPCON_CLK_CONF_CLK_COEX_EN_Msk = 0x2 + // Bit CLK_COEX_EN. + MODEM_LPCON_CLK_CONF_CLK_COEX_EN = 0x2 + // Position of CLK_I2C_MST_EN field. + MODEM_LPCON_CLK_CONF_CLK_I2C_MST_EN_Pos = 0x2 + // Bit mask of CLK_I2C_MST_EN field. + MODEM_LPCON_CLK_CONF_CLK_I2C_MST_EN_Msk = 0x4 + // Bit CLK_I2C_MST_EN. + MODEM_LPCON_CLK_CONF_CLK_I2C_MST_EN = 0x4 + // Position of CLK_LP_TIMER_EN field. + MODEM_LPCON_CLK_CONF_CLK_LP_TIMER_EN_Pos = 0x3 + // Bit mask of CLK_LP_TIMER_EN field. + MODEM_LPCON_CLK_CONF_CLK_LP_TIMER_EN_Msk = 0x8 + // Bit CLK_LP_TIMER_EN. + MODEM_LPCON_CLK_CONF_CLK_LP_TIMER_EN = 0x8 + + // CLK_CONF_FORCE_ON + // Position of CLK_WIFIPWR_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_WIFIPWR_FO_Pos = 0x0 + // Bit mask of CLK_WIFIPWR_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_WIFIPWR_FO_Msk = 0x1 + // Bit CLK_WIFIPWR_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_WIFIPWR_FO = 0x1 + // Position of CLK_COEX_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_COEX_FO_Pos = 0x1 + // Bit mask of CLK_COEX_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_COEX_FO_Msk = 0x2 + // Bit CLK_COEX_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_COEX_FO = 0x2 + // Position of CLK_I2C_MST_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_I2C_MST_FO_Pos = 0x2 + // Bit mask of CLK_I2C_MST_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_I2C_MST_FO_Msk = 0x4 + // Bit CLK_I2C_MST_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_I2C_MST_FO = 0x4 + // Position of CLK_LP_TIMER_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_LP_TIMER_FO_Pos = 0x3 + // Bit mask of CLK_LP_TIMER_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_LP_TIMER_FO_Msk = 0x8 + // Bit CLK_LP_TIMER_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_LP_TIMER_FO = 0x8 + // Position of CLK_BCMEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_BCMEM_FO_Pos = 0x4 + // Bit mask of CLK_BCMEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_BCMEM_FO_Msk = 0x10 + // Bit CLK_BCMEM_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_BCMEM_FO = 0x10 + // Position of CLK_I2C_MST_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_I2C_MST_MEM_FO_Pos = 0x5 + // Bit mask of CLK_I2C_MST_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_I2C_MST_MEM_FO_Msk = 0x20 + // Bit CLK_I2C_MST_MEM_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_I2C_MST_MEM_FO = 0x20 + // Position of CLK_CHAN_FREQ_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_CHAN_FREQ_MEM_FO_Pos = 0x6 + // Bit mask of CLK_CHAN_FREQ_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_CHAN_FREQ_MEM_FO_Msk = 0x40 + // Bit CLK_CHAN_FREQ_MEM_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_CHAN_FREQ_MEM_FO = 0x40 + // Position of CLK_PBUS_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_PBUS_MEM_FO_Pos = 0x7 + // Bit mask of CLK_PBUS_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_PBUS_MEM_FO_Msk = 0x80 + // Bit CLK_PBUS_MEM_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_PBUS_MEM_FO = 0x80 + // Position of CLK_AGC_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_AGC_MEM_FO_Pos = 0x8 + // Bit mask of CLK_AGC_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_AGC_MEM_FO_Msk = 0x100 + // Bit CLK_AGC_MEM_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_AGC_MEM_FO = 0x100 + // Position of CLK_DC_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_DC_MEM_FO_Pos = 0x9 + // Bit mask of CLK_DC_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_DC_MEM_FO_Msk = 0x200 + // Bit CLK_DC_MEM_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_DC_MEM_FO = 0x200 + + // CLK_CONF_POWER_ST + // Position of CLK_WIFIPWR_ST_MAP field. + MODEM_LPCON_CLK_CONF_POWER_ST_CLK_WIFIPWR_ST_MAP_Pos = 0x10 + // Bit mask of CLK_WIFIPWR_ST_MAP field. + MODEM_LPCON_CLK_CONF_POWER_ST_CLK_WIFIPWR_ST_MAP_Msk = 0xf0000 + // Position of CLK_COEX_ST_MAP field. + MODEM_LPCON_CLK_CONF_POWER_ST_CLK_COEX_ST_MAP_Pos = 0x14 + // Bit mask of CLK_COEX_ST_MAP field. + MODEM_LPCON_CLK_CONF_POWER_ST_CLK_COEX_ST_MAP_Msk = 0xf00000 + // Position of CLK_I2C_MST_ST_MAP field. + MODEM_LPCON_CLK_CONF_POWER_ST_CLK_I2C_MST_ST_MAP_Pos = 0x18 + // Bit mask of CLK_I2C_MST_ST_MAP field. + MODEM_LPCON_CLK_CONF_POWER_ST_CLK_I2C_MST_ST_MAP_Msk = 0xf000000 + // Position of CLK_LP_APB_ST_MAP field. + MODEM_LPCON_CLK_CONF_POWER_ST_CLK_LP_APB_ST_MAP_Pos = 0x1c + // Bit mask of CLK_LP_APB_ST_MAP field. + MODEM_LPCON_CLK_CONF_POWER_ST_CLK_LP_APB_ST_MAP_Msk = 0xf0000000 + + // RST_CONF + // Position of RST_WIFIPWR field. + MODEM_LPCON_RST_CONF_RST_WIFIPWR_Pos = 0x0 + // Bit mask of RST_WIFIPWR field. + MODEM_LPCON_RST_CONF_RST_WIFIPWR_Msk = 0x1 + // Bit RST_WIFIPWR. + MODEM_LPCON_RST_CONF_RST_WIFIPWR = 0x1 + // Position of RST_COEX field. + MODEM_LPCON_RST_CONF_RST_COEX_Pos = 0x1 + // Bit mask of RST_COEX field. + MODEM_LPCON_RST_CONF_RST_COEX_Msk = 0x2 + // Bit RST_COEX. + MODEM_LPCON_RST_CONF_RST_COEX = 0x2 + // Position of RST_I2C_MST field. + MODEM_LPCON_RST_CONF_RST_I2C_MST_Pos = 0x2 + // Bit mask of RST_I2C_MST field. + MODEM_LPCON_RST_CONF_RST_I2C_MST_Msk = 0x4 + // Bit RST_I2C_MST. + MODEM_LPCON_RST_CONF_RST_I2C_MST = 0x4 + // Position of RST_LP_TIMER field. + MODEM_LPCON_RST_CONF_RST_LP_TIMER_Pos = 0x3 + // Bit mask of RST_LP_TIMER field. + MODEM_LPCON_RST_CONF_RST_LP_TIMER_Msk = 0x8 + // Bit RST_LP_TIMER. + MODEM_LPCON_RST_CONF_RST_LP_TIMER = 0x8 + + // MEM_CONF + // Position of DC_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_DC_MEM_FORCE_PU_Pos = 0x0 + // Bit mask of DC_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_DC_MEM_FORCE_PU_Msk = 0x1 + // Bit DC_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_DC_MEM_FORCE_PU = 0x1 + // Position of DC_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_DC_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of DC_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_DC_MEM_FORCE_PD_Msk = 0x2 + // Bit DC_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_DC_MEM_FORCE_PD = 0x2 + // Position of AGC_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of AGC_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PU_Msk = 0x4 + // Bit AGC_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PU = 0x4 + // Position of AGC_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of AGC_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PD_Msk = 0x8 + // Bit AGC_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PD = 0x8 + // Position of PBUS_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of PBUS_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PU_Msk = 0x10 + // Bit PBUS_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PU = 0x10 + // Position of PBUS_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PD_Pos = 0x5 + // Bit mask of PBUS_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PD_Msk = 0x20 + // Bit PBUS_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PD = 0x20 + // Position of BC_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_BC_MEM_FORCE_PU_Pos = 0x6 + // Bit mask of BC_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_BC_MEM_FORCE_PU_Msk = 0x40 + // Bit BC_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_BC_MEM_FORCE_PU = 0x40 + // Position of BC_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_BC_MEM_FORCE_PD_Pos = 0x7 + // Bit mask of BC_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_BC_MEM_FORCE_PD_Msk = 0x80 + // Bit BC_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_BC_MEM_FORCE_PD = 0x80 + // Position of I2C_MST_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PU_Pos = 0x8 + // Bit mask of I2C_MST_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PU_Msk = 0x100 + // Bit I2C_MST_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PU = 0x100 + // Position of I2C_MST_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PD_Pos = 0x9 + // Bit mask of I2C_MST_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PD_Msk = 0x200 + // Bit I2C_MST_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PD = 0x200 + // Position of CHAN_FREQ_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PU_Pos = 0xa + // Bit mask of CHAN_FREQ_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PU_Msk = 0x400 + // Bit CHAN_FREQ_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PU = 0x400 + // Position of CHAN_FREQ_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PD_Pos = 0xb + // Bit mask of CHAN_FREQ_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PD_Msk = 0x800 + // Bit CHAN_FREQ_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PD = 0x800 + // Position of MODEM_PWR_MEM_WP field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_WP_Pos = 0xc + // Bit mask of MODEM_PWR_MEM_WP field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_WP_Msk = 0x7000 + // Position of MODEM_PWR_MEM_WA field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_WA_Pos = 0xf + // Bit mask of MODEM_PWR_MEM_WA field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_WA_Msk = 0x38000 + // Position of MODEM_PWR_MEM_RA field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_RA_Pos = 0x12 + // Bit mask of MODEM_PWR_MEM_RA field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_RA_Msk = 0xc0000 + + // DATE + // Position of DATE field. + MODEM_LPCON_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + MODEM_LPCON_DATE_DATE_Msk = 0xfffffff +) + +// Constants for MODEM_SYSCON: MODEM_SYSCON Peripheral +const ( + // TEST_CONF + // Position of CLK_EN field. + MODEM_SYSCON_TEST_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + MODEM_SYSCON_TEST_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + MODEM_SYSCON_TEST_CONF_CLK_EN = 0x1 + + // CLK_CONF + // Position of CLK_DATA_DUMP_MUX field. + MODEM_SYSCON_CLK_CONF_CLK_DATA_DUMP_MUX_Pos = 0x15 + // Bit mask of CLK_DATA_DUMP_MUX field. + MODEM_SYSCON_CLK_CONF_CLK_DATA_DUMP_MUX_Msk = 0x200000 + // Bit CLK_DATA_DUMP_MUX. + MODEM_SYSCON_CLK_CONF_CLK_DATA_DUMP_MUX = 0x200000 + // Position of CLK_ETM_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ETM_EN_Pos = 0x16 + // Bit mask of CLK_ETM_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ETM_EN_Msk = 0x400000 + // Bit CLK_ETM_EN. + MODEM_SYSCON_CLK_CONF_CLK_ETM_EN = 0x400000 + // Position of CLK_ZB_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ZB_APB_EN_Pos = 0x17 + // Bit mask of CLK_ZB_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ZB_APB_EN_Msk = 0x800000 + // Bit CLK_ZB_APB_EN. + MODEM_SYSCON_CLK_CONF_CLK_ZB_APB_EN = 0x800000 + // Position of CLK_ZB_MAC_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ZB_MAC_EN_Pos = 0x18 + // Bit mask of CLK_ZB_MAC_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ZB_MAC_EN_Msk = 0x1000000 + // Bit CLK_ZB_MAC_EN. + MODEM_SYSCON_CLK_CONF_CLK_ZB_MAC_EN = 0x1000000 + // Position of CLK_MODEM_SEC_ECB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_ECB_EN_Pos = 0x19 + // Bit mask of CLK_MODEM_SEC_ECB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_ECB_EN_Msk = 0x2000000 + // Bit CLK_MODEM_SEC_ECB_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_ECB_EN = 0x2000000 + // Position of CLK_MODEM_SEC_CCM_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_CCM_EN_Pos = 0x1a + // Bit mask of CLK_MODEM_SEC_CCM_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_CCM_EN_Msk = 0x4000000 + // Bit CLK_MODEM_SEC_CCM_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_CCM_EN = 0x4000000 + // Position of CLK_MODEM_SEC_BAH_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_BAH_EN_Pos = 0x1b + // Bit mask of CLK_MODEM_SEC_BAH_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_BAH_EN_Msk = 0x8000000 + // Bit CLK_MODEM_SEC_BAH_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_BAH_EN = 0x8000000 + // Position of CLK_MODEM_SEC_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_APB_EN_Pos = 0x1c + // Bit mask of CLK_MODEM_SEC_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_APB_EN_Msk = 0x10000000 + // Bit CLK_MODEM_SEC_APB_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_APB_EN = 0x10000000 + // Position of CLK_MODEM_SEC_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_EN_Pos = 0x1d + // Bit mask of CLK_MODEM_SEC_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_EN_Msk = 0x20000000 + // Bit CLK_MODEM_SEC_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_EN = 0x20000000 + // Position of CLK_BLE_TIMER_EN field. + MODEM_SYSCON_CLK_CONF_CLK_BLE_TIMER_EN_Pos = 0x1e + // Bit mask of CLK_BLE_TIMER_EN field. + MODEM_SYSCON_CLK_CONF_CLK_BLE_TIMER_EN_Msk = 0x40000000 + // Bit CLK_BLE_TIMER_EN. + MODEM_SYSCON_CLK_CONF_CLK_BLE_TIMER_EN = 0x40000000 + // Position of CLK_DATA_DUMP_EN field. + MODEM_SYSCON_CLK_CONF_CLK_DATA_DUMP_EN_Pos = 0x1f + // Bit mask of CLK_DATA_DUMP_EN field. + MODEM_SYSCON_CLK_CONF_CLK_DATA_DUMP_EN_Msk = 0x80000000 + // Bit CLK_DATA_DUMP_EN. + MODEM_SYSCON_CLK_CONF_CLK_DATA_DUMP_EN = 0x80000000 + + // CLK_CONF_FORCE_ON + // Position of CLK_ETM_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ETM_FO_Pos = 0x16 + // Bit mask of CLK_ETM_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ETM_FO_Msk = 0x400000 + // Bit CLK_ETM_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ETM_FO = 0x400000 + // Position of CLK_ZB_APB_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ZB_APB_FO_Pos = 0x17 + // Bit mask of CLK_ZB_APB_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ZB_APB_FO_Msk = 0x800000 + // Bit CLK_ZB_APB_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ZB_APB_FO = 0x800000 + // Position of CLK_ZB_MAC_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ZB_MAC_FO_Pos = 0x18 + // Bit mask of CLK_ZB_MAC_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ZB_MAC_FO_Msk = 0x1000000 + // Bit CLK_ZB_MAC_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ZB_MAC_FO = 0x1000000 + // Position of CLK_MODEM_SEC_ECB_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_ECB_FO_Pos = 0x19 + // Bit mask of CLK_MODEM_SEC_ECB_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_ECB_FO_Msk = 0x2000000 + // Bit CLK_MODEM_SEC_ECB_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_ECB_FO = 0x2000000 + // Position of CLK_MODEM_SEC_CCM_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_CCM_FO_Pos = 0x1a + // Bit mask of CLK_MODEM_SEC_CCM_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_CCM_FO_Msk = 0x4000000 + // Bit CLK_MODEM_SEC_CCM_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_CCM_FO = 0x4000000 + // Position of CLK_MODEM_SEC_BAH_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_BAH_FO_Pos = 0x1b + // Bit mask of CLK_MODEM_SEC_BAH_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_BAH_FO_Msk = 0x8000000 + // Bit CLK_MODEM_SEC_BAH_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_BAH_FO = 0x8000000 + // Position of CLK_MODEM_SEC_APB_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_APB_FO_Pos = 0x1c + // Bit mask of CLK_MODEM_SEC_APB_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_APB_FO_Msk = 0x10000000 + // Bit CLK_MODEM_SEC_APB_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_APB_FO = 0x10000000 + // Position of CLK_MODEM_SEC_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO_Pos = 0x1d + // Bit mask of CLK_MODEM_SEC_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO_Msk = 0x20000000 + // Bit CLK_MODEM_SEC_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO = 0x20000000 + // Position of CLK_BLE_TIMER_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO_Pos = 0x1e + // Bit mask of CLK_BLE_TIMER_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO_Msk = 0x40000000 + // Bit CLK_BLE_TIMER_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO = 0x40000000 + // Position of CLK_DATA_DUMP_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO_Pos = 0x1f + // Bit mask of CLK_DATA_DUMP_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO_Msk = 0x80000000 + // Bit CLK_DATA_DUMP_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO = 0x80000000 + + // CLK_CONF_POWER_ST + // Position of CLK_ZB_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_ZB_ST_MAP_Pos = 0x8 + // Bit mask of CLK_ZB_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_ZB_ST_MAP_Msk = 0xf00 + // Position of CLK_FE_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_FE_ST_MAP_Pos = 0xc + // Bit mask of CLK_FE_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_FE_ST_MAP_Msk = 0xf000 + // Position of CLK_BT_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_BT_ST_MAP_Pos = 0x10 + // Bit mask of CLK_BT_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_BT_ST_MAP_Msk = 0xf0000 + // Position of CLK_WIFI_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_WIFI_ST_MAP_Pos = 0x14 + // Bit mask of CLK_WIFI_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_WIFI_ST_MAP_Msk = 0xf00000 + // Position of CLK_MODEM_PERI_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_MODEM_PERI_ST_MAP_Pos = 0x18 + // Bit mask of CLK_MODEM_PERI_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_MODEM_PERI_ST_MAP_Msk = 0xf000000 + // Position of CLK_MODEM_APB_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_MODEM_APB_ST_MAP_Pos = 0x1c + // Bit mask of CLK_MODEM_APB_ST_MAP field. + MODEM_SYSCON_CLK_CONF_POWER_ST_CLK_MODEM_APB_ST_MAP_Msk = 0xf0000000 + + // MODEM_RST_CONF + // Position of RST_WIFIBB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_WIFIBB_Pos = 0x8 + // Bit mask of RST_WIFIBB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_WIFIBB_Msk = 0x100 + // Bit RST_WIFIBB. + MODEM_SYSCON_MODEM_RST_CONF_RST_WIFIBB = 0x100 + // Position of RST_WIFIMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_WIFIMAC_Pos = 0xa + // Bit mask of RST_WIFIMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_WIFIMAC_Msk = 0x400 + // Bit RST_WIFIMAC. + MODEM_SYSCON_MODEM_RST_CONF_RST_WIFIMAC = 0x400 + // Position of RST_FE field. + MODEM_SYSCON_MODEM_RST_CONF_RST_FE_Pos = 0xe + // Bit mask of RST_FE field. + MODEM_SYSCON_MODEM_RST_CONF_RST_FE_Msk = 0x4000 + // Bit RST_FE. + MODEM_SYSCON_MODEM_RST_CONF_RST_FE = 0x4000 + // Position of RST_BTMAC_APB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_APB_Pos = 0xf + // Bit mask of RST_BTMAC_APB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_APB_Msk = 0x8000 + // Bit RST_BTMAC_APB. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_APB = 0x8000 + // Position of RST_BTMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_Pos = 0x10 + // Bit mask of RST_BTMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_Msk = 0x10000 + // Bit RST_BTMAC. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC = 0x10000 + // Position of RST_BTBB_APB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_APB_Pos = 0x11 + // Bit mask of RST_BTBB_APB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_APB_Msk = 0x20000 + // Bit RST_BTBB_APB. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_APB = 0x20000 + // Position of RST_BTBB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_Pos = 0x12 + // Bit mask of RST_BTBB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_Msk = 0x40000 + // Bit RST_BTBB. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB = 0x40000 + // Position of RST_ETM field. + MODEM_SYSCON_MODEM_RST_CONF_RST_ETM_Pos = 0x16 + // Bit mask of RST_ETM field. + MODEM_SYSCON_MODEM_RST_CONF_RST_ETM_Msk = 0x400000 + // Bit RST_ETM. + MODEM_SYSCON_MODEM_RST_CONF_RST_ETM = 0x400000 + // Position of RST_ZBMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_ZBMAC_Pos = 0x18 + // Bit mask of RST_ZBMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_ZBMAC_Msk = 0x1000000 + // Bit RST_ZBMAC. + MODEM_SYSCON_MODEM_RST_CONF_RST_ZBMAC = 0x1000000 + // Position of RST_MODEM_ECB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_ECB_Pos = 0x19 + // Bit mask of RST_MODEM_ECB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_ECB_Msk = 0x2000000 + // Bit RST_MODEM_ECB. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_ECB = 0x2000000 + // Position of RST_MODEM_CCM field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_CCM_Pos = 0x1a + // Bit mask of RST_MODEM_CCM field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_CCM_Msk = 0x4000000 + // Bit RST_MODEM_CCM. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_CCM = 0x4000000 + // Position of RST_MODEM_BAH field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_BAH_Pos = 0x1b + // Bit mask of RST_MODEM_BAH field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_BAH_Msk = 0x8000000 + // Bit RST_MODEM_BAH. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_BAH = 0x8000000 + // Position of RST_MODEM_SEC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_SEC_Pos = 0x1d + // Bit mask of RST_MODEM_SEC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_SEC_Msk = 0x20000000 + // Bit RST_MODEM_SEC. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_SEC = 0x20000000 + // Position of RST_BLE_TIMER field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BLE_TIMER_Pos = 0x1e + // Bit mask of RST_BLE_TIMER field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BLE_TIMER_Msk = 0x40000000 + // Bit RST_BLE_TIMER. + MODEM_SYSCON_MODEM_RST_CONF_RST_BLE_TIMER = 0x40000000 + // Position of RST_DATA_DUMP field. + MODEM_SYSCON_MODEM_RST_CONF_RST_DATA_DUMP_Pos = 0x1f + // Bit mask of RST_DATA_DUMP field. + MODEM_SYSCON_MODEM_RST_CONF_RST_DATA_DUMP_Msk = 0x80000000 + // Bit RST_DATA_DUMP. + MODEM_SYSCON_MODEM_RST_CONF_RST_DATA_DUMP = 0x80000000 + + // CLK_CONF1 + // Position of CLK_WIFIBB_22M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_22M_EN_Pos = 0x0 + // Bit mask of CLK_WIFIBB_22M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_22M_EN_Msk = 0x1 + // Bit CLK_WIFIBB_22M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_22M_EN = 0x1 + // Position of CLK_WIFIBB_40M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_40M_EN_Pos = 0x1 + // Bit mask of CLK_WIFIBB_40M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_40M_EN_Msk = 0x2 + // Bit CLK_WIFIBB_40M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_40M_EN = 0x2 + // Position of CLK_WIFIBB_44M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_44M_EN_Pos = 0x2 + // Bit mask of CLK_WIFIBB_44M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_44M_EN_Msk = 0x4 + // Bit CLK_WIFIBB_44M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_44M_EN = 0x4 + // Position of CLK_WIFIBB_80M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_80M_EN_Pos = 0x3 + // Bit mask of CLK_WIFIBB_80M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_80M_EN_Msk = 0x8 + // Bit CLK_WIFIBB_80M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_80M_EN = 0x8 + // Position of CLK_WIFIBB_40X_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_40X_EN_Pos = 0x4 + // Bit mask of CLK_WIFIBB_40X_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_40X_EN_Msk = 0x10 + // Bit CLK_WIFIBB_40X_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_40X_EN = 0x10 + // Position of CLK_WIFIBB_80X_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_80X_EN_Pos = 0x5 + // Bit mask of CLK_WIFIBB_80X_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_80X_EN_Msk = 0x20 + // Bit CLK_WIFIBB_80X_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_80X_EN = 0x20 + // Position of CLK_WIFIBB_40X1_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_40X1_EN_Pos = 0x6 + // Bit mask of CLK_WIFIBB_40X1_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_40X1_EN_Msk = 0x40 + // Bit CLK_WIFIBB_40X1_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_40X1_EN = 0x40 + // Position of CLK_WIFIBB_80X1_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_80X1_EN_Pos = 0x7 + // Bit mask of CLK_WIFIBB_80X1_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_80X1_EN_Msk = 0x80 + // Bit CLK_WIFIBB_80X1_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_80X1_EN = 0x80 + // Position of CLK_WIFIBB_160X1_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_160X1_EN_Pos = 0x8 + // Bit mask of CLK_WIFIBB_160X1_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_160X1_EN_Msk = 0x100 + // Bit CLK_WIFIBB_160X1_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_160X1_EN = 0x100 + // Position of CLK_WIFIMAC_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIMAC_EN_Pos = 0x9 + // Bit mask of CLK_WIFIMAC_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIMAC_EN_Msk = 0x200 + // Bit CLK_WIFIMAC_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIMAC_EN = 0x200 + // Position of CLK_WIFI_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFI_APB_EN_Pos = 0xa + // Bit mask of CLK_WIFI_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFI_APB_EN_Msk = 0x400 + // Bit CLK_WIFI_APB_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFI_APB_EN = 0x400 + // Position of CLK_FE_20M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_20M_EN_Pos = 0xb + // Bit mask of CLK_FE_20M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_20M_EN_Msk = 0x800 + // Bit CLK_FE_20M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_20M_EN = 0x800 + // Position of CLK_FE_40M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_40M_EN_Pos = 0xc + // Bit mask of CLK_FE_40M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_40M_EN_Msk = 0x1000 + // Bit CLK_FE_40M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_40M_EN = 0x1000 + // Position of CLK_FE_80M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_80M_EN_Pos = 0xd + // Bit mask of CLK_FE_80M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_80M_EN_Msk = 0x2000 + // Bit CLK_FE_80M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_80M_EN = 0x2000 + // Position of CLK_FE_160M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_160M_EN_Pos = 0xe + // Bit mask of CLK_FE_160M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_160M_EN_Msk = 0x4000 + // Bit CLK_FE_160M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_160M_EN = 0x4000 + // Position of CLK_FE_CAL_160M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_CAL_160M_EN_Pos = 0xf + // Bit mask of CLK_FE_CAL_160M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_CAL_160M_EN_Msk = 0x8000 + // Bit CLK_FE_CAL_160M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_CAL_160M_EN = 0x8000 + // Position of CLK_FE_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_APB_EN_Pos = 0x10 + // Bit mask of CLK_FE_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_APB_EN_Msk = 0x10000 + // Bit CLK_FE_APB_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_APB_EN = 0x10000 + // Position of CLK_BT_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_BT_APB_EN_Pos = 0x11 + // Bit mask of CLK_BT_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_BT_APB_EN_Msk = 0x20000 + // Bit CLK_BT_APB_EN. + MODEM_SYSCON_CLK_CONF1_CLK_BT_APB_EN = 0x20000 + // Position of CLK_BT_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_BT_EN_Pos = 0x12 + // Bit mask of CLK_BT_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_BT_EN_Msk = 0x40000 + // Bit CLK_BT_EN. + MODEM_SYSCON_CLK_CONF1_CLK_BT_EN = 0x40000 + // Position of CLK_WIFIBB_480M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_480M_EN_Pos = 0x13 + // Bit mask of CLK_WIFIBB_480M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_480M_EN_Msk = 0x80000 + // Bit CLK_WIFIBB_480M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_WIFIBB_480M_EN = 0x80000 + // Position of CLK_FE_480M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_480M_EN_Pos = 0x14 + // Bit mask of CLK_FE_480M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_480M_EN_Msk = 0x100000 + // Bit CLK_FE_480M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_480M_EN = 0x100000 + // Position of CLK_FE_ANAMODE_40M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ANAMODE_40M_EN_Pos = 0x15 + // Bit mask of CLK_FE_ANAMODE_40M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ANAMODE_40M_EN_Msk = 0x200000 + // Bit CLK_FE_ANAMODE_40M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ANAMODE_40M_EN = 0x200000 + // Position of CLK_FE_ANAMODE_80M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ANAMODE_80M_EN_Pos = 0x16 + // Bit mask of CLK_FE_ANAMODE_80M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ANAMODE_80M_EN_Msk = 0x400000 + // Bit CLK_FE_ANAMODE_80M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ANAMODE_80M_EN = 0x400000 + // Position of CLK_FE_ANAMODE_160M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ANAMODE_160M_EN_Pos = 0x17 + // Bit mask of CLK_FE_ANAMODE_160M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ANAMODE_160M_EN_Msk = 0x800000 + // Bit CLK_FE_ANAMODE_160M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ANAMODE_160M_EN = 0x800000 + + // CLK_CONF1_FORCE_ON + // Position of CLK_WIFIBB_22M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_22M_FO_Pos = 0x0 + // Bit mask of CLK_WIFIBB_22M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_22M_FO_Msk = 0x1 + // Bit CLK_WIFIBB_22M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_22M_FO = 0x1 + // Position of CLK_WIFIBB_40M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_40M_FO_Pos = 0x1 + // Bit mask of CLK_WIFIBB_40M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_40M_FO_Msk = 0x2 + // Bit CLK_WIFIBB_40M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_40M_FO = 0x2 + // Position of CLK_WIFIBB_44M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_44M_FO_Pos = 0x2 + // Bit mask of CLK_WIFIBB_44M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_44M_FO_Msk = 0x4 + // Bit CLK_WIFIBB_44M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_44M_FO = 0x4 + // Position of CLK_WIFIBB_80M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_80M_FO_Pos = 0x3 + // Bit mask of CLK_WIFIBB_80M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_80M_FO_Msk = 0x8 + // Bit CLK_WIFIBB_80M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_80M_FO = 0x8 + // Position of CLK_WIFIBB_40X_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_40X_FO_Pos = 0x4 + // Bit mask of CLK_WIFIBB_40X_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_40X_FO_Msk = 0x10 + // Bit CLK_WIFIBB_40X_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_40X_FO = 0x10 + // Position of CLK_WIFIBB_80X_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_80X_FO_Pos = 0x5 + // Bit mask of CLK_WIFIBB_80X_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_80X_FO_Msk = 0x20 + // Bit CLK_WIFIBB_80X_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_80X_FO = 0x20 + // Position of CLK_WIFIBB_40X1_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_40X1_FO_Pos = 0x6 + // Bit mask of CLK_WIFIBB_40X1_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_40X1_FO_Msk = 0x40 + // Bit CLK_WIFIBB_40X1_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_40X1_FO = 0x40 + // Position of CLK_WIFIBB_80X1_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_80X1_FO_Pos = 0x7 + // Bit mask of CLK_WIFIBB_80X1_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_80X1_FO_Msk = 0x80 + // Bit CLK_WIFIBB_80X1_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_80X1_FO = 0x80 + // Position of CLK_WIFIBB_160X1_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_160X1_FO_Pos = 0x8 + // Bit mask of CLK_WIFIBB_160X1_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_160X1_FO_Msk = 0x100 + // Bit CLK_WIFIBB_160X1_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_160X1_FO = 0x100 + // Position of CLK_WIFIMAC_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIMAC_FO_Pos = 0x9 + // Bit mask of CLK_WIFIMAC_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIMAC_FO_Msk = 0x200 + // Bit CLK_WIFIMAC_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIMAC_FO = 0x200 + // Position of CLK_WIFI_APB_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFI_APB_FO_Pos = 0xa + // Bit mask of CLK_WIFI_APB_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFI_APB_FO_Msk = 0x400 + // Bit CLK_WIFI_APB_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFI_APB_FO = 0x400 + // Position of CLK_FE_20M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_20M_FO_Pos = 0xb + // Bit mask of CLK_FE_20M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_20M_FO_Msk = 0x800 + // Bit CLK_FE_20M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_20M_FO = 0x800 + // Position of CLK_FE_40M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_40M_FO_Pos = 0xc + // Bit mask of CLK_FE_40M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_40M_FO_Msk = 0x1000 + // Bit CLK_FE_40M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_40M_FO = 0x1000 + // Position of CLK_FE_80M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_80M_FO_Pos = 0xd + // Bit mask of CLK_FE_80M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_80M_FO_Msk = 0x2000 + // Bit CLK_FE_80M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_80M_FO = 0x2000 + // Position of CLK_FE_160M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_160M_FO_Pos = 0xe + // Bit mask of CLK_FE_160M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_160M_FO_Msk = 0x4000 + // Bit CLK_FE_160M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_160M_FO = 0x4000 + // Position of CLK_FE_CAL_160M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_CAL_160M_FO_Pos = 0xf + // Bit mask of CLK_FE_CAL_160M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_CAL_160M_FO_Msk = 0x8000 + // Bit CLK_FE_CAL_160M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_CAL_160M_FO = 0x8000 + // Position of CLK_FE_APB_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_APB_FO_Pos = 0x10 + // Bit mask of CLK_FE_APB_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_APB_FO_Msk = 0x10000 + // Bit CLK_FE_APB_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_APB_FO = 0x10000 + // Position of CLK_BT_APB_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_BT_APB_FO_Pos = 0x11 + // Bit mask of CLK_BT_APB_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_BT_APB_FO_Msk = 0x20000 + // Bit CLK_BT_APB_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_BT_APB_FO = 0x20000 + // Position of CLK_BT_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_BT_FO_Pos = 0x12 + // Bit mask of CLK_BT_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_BT_FO_Msk = 0x40000 + // Bit CLK_BT_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_BT_FO = 0x40000 + // Position of CLK_WIFIBB_480M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_480M_FO_Pos = 0x13 + // Bit mask of CLK_WIFIBB_480M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_480M_FO_Msk = 0x80000 + // Bit CLK_WIFIBB_480M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_WIFIBB_480M_FO = 0x80000 + // Position of CLK_FE_480M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_480M_FO_Pos = 0x14 + // Bit mask of CLK_FE_480M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_480M_FO_Msk = 0x100000 + // Bit CLK_FE_480M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_480M_FO = 0x100000 + // Position of CLK_FE_ANAMODE_40M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_40M_FO_Pos = 0x15 + // Bit mask of CLK_FE_ANAMODE_40M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_40M_FO_Msk = 0x200000 + // Bit CLK_FE_ANAMODE_40M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_40M_FO = 0x200000 + // Position of CLK_FE_ANAMODE_80M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_80M_FO_Pos = 0x16 + // Bit mask of CLK_FE_ANAMODE_80M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_80M_FO_Msk = 0x400000 + // Bit CLK_FE_ANAMODE_80M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_80M_FO = 0x400000 + // Position of CLK_FE_ANAMODE_160M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_160M_FO_Pos = 0x17 + // Bit mask of CLK_FE_ANAMODE_160M_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_160M_FO_Msk = 0x800000 + // Bit CLK_FE_ANAMODE_160M_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_ANAMODE_160M_FO = 0x800000 + + // WIFI_BB_CFG + // Position of WIFI_BB_CFG field. + MODEM_SYSCON_WIFI_BB_CFG_WIFI_BB_CFG_Pos = 0x0 + // Bit mask of WIFI_BB_CFG field. + MODEM_SYSCON_WIFI_BB_CFG_WIFI_BB_CFG_Msk = 0xffffffff + + // MEM_CONF + // Position of MODEM_MEM_WP field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_WP_Pos = 0x0 + // Bit mask of MODEM_MEM_WP field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_WP_Msk = 0x7 + // Position of MODEM_MEM_WA field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_WA_Pos = 0x3 + // Bit mask of MODEM_MEM_WA field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_WA_Msk = 0x38 + // Position of MODEM_MEM_RA field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_RA_Pos = 0x6 + // Bit mask of MODEM_MEM_RA field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_RA_Msk = 0xc0 + + // DATE + // Position of DATE field. + MODEM_SYSCON_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + MODEM_SYSCON_DATE_DATE_Msk = 0xfffffff +) + +// Constants for OTP_DEBUG: OTP_DEBUG Peripheral +const ( + // WR_DIS: Otp debuger block0 data register1. + // Position of BLOCK0_WR_DIS field. + OTP_DEBUG_WR_DIS_BLOCK0_WR_DIS_Pos = 0x0 + // Bit mask of BLOCK0_WR_DIS field. + OTP_DEBUG_WR_DIS_BLOCK0_WR_DIS_Msk = 0xffffffff + + // BLK0_BACKUP1_W1: Otp debuger block0 data register2. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W1 field. + OTP_DEBUG_BLK0_BACKUP1_W1_OTP_BEBUG_BLOCK0_BACKUP1_W1_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W1 field. + OTP_DEBUG_BLK0_BACKUP1_W1_OTP_BEBUG_BLOCK0_BACKUP1_W1_Msk = 0xffffffff + + // BLK0_BACKUP1_W2: Otp debuger block0 data register3. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W2 field. + OTP_DEBUG_BLK0_BACKUP1_W2_OTP_BEBUG_BLOCK0_BACKUP1_W2_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W2 field. + OTP_DEBUG_BLK0_BACKUP1_W2_OTP_BEBUG_BLOCK0_BACKUP1_W2_Msk = 0xffffffff + + // BLK0_BACKUP1_W3: Otp debuger block0 data register4. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W3 field. + OTP_DEBUG_BLK0_BACKUP1_W3_OTP_BEBUG_BLOCK0_BACKUP1_W3_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W3 field. + OTP_DEBUG_BLK0_BACKUP1_W3_OTP_BEBUG_BLOCK0_BACKUP1_W3_Msk = 0xffffffff + + // BLK0_BACKUP1_W4: Otp debuger block0 data register5. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W4 field. + OTP_DEBUG_BLK0_BACKUP1_W4_OTP_BEBUG_BLOCK0_BACKUP1_W4_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W4 field. + OTP_DEBUG_BLK0_BACKUP1_W4_OTP_BEBUG_BLOCK0_BACKUP1_W4_Msk = 0xffffffff + + // BLK0_BACKUP1_W5: Otp debuger block0 data register6. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W5 field. + OTP_DEBUG_BLK0_BACKUP1_W5_OTP_BEBUG_BLOCK0_BACKUP1_W5_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W5 field. + OTP_DEBUG_BLK0_BACKUP1_W5_OTP_BEBUG_BLOCK0_BACKUP1_W5_Msk = 0xffffffff + + // BLK0_BACKUP2_W1: Otp debuger block0 data register7. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W1 field. + OTP_DEBUG_BLK0_BACKUP2_W1_OTP_BEBUG_BLOCK0_BACKUP2_W1_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W1 field. + OTP_DEBUG_BLK0_BACKUP2_W1_OTP_BEBUG_BLOCK0_BACKUP2_W1_Msk = 0xffffffff + + // BLK0_BACKUP2_W2: Otp debuger block0 data register8. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W2 field. + OTP_DEBUG_BLK0_BACKUP2_W2_OTP_BEBUG_BLOCK0_BACKUP2_W2_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W2 field. + OTP_DEBUG_BLK0_BACKUP2_W2_OTP_BEBUG_BLOCK0_BACKUP2_W2_Msk = 0xffffffff + + // BLK0_BACKUP2_W3: Otp debuger block0 data register9. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W3 field. + OTP_DEBUG_BLK0_BACKUP2_W3_OTP_BEBUG_BLOCK0_BACKUP2_W3_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W3 field. + OTP_DEBUG_BLK0_BACKUP2_W3_OTP_BEBUG_BLOCK0_BACKUP2_W3_Msk = 0xffffffff + + // BLK0_BACKUP2_W4: Otp debuger block0 data register10. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W4 field. + OTP_DEBUG_BLK0_BACKUP2_W4_OTP_BEBUG_BLOCK0_BACKUP2_W4_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W4 field. + OTP_DEBUG_BLK0_BACKUP2_W4_OTP_BEBUG_BLOCK0_BACKUP2_W4_Msk = 0xffffffff + + // BLK0_BACKUP2_W5: Otp debuger block0 data register11. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W5 field. + OTP_DEBUG_BLK0_BACKUP2_W5_OTP_BEBUG_BLOCK0_BACKUP2_W5_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W5 field. + OTP_DEBUG_BLK0_BACKUP2_W5_OTP_BEBUG_BLOCK0_BACKUP2_W5_Msk = 0xffffffff + + // BLK0_BACKUP3_W1: Otp debuger block0 data register12. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W1 field. + OTP_DEBUG_BLK0_BACKUP3_W1_OTP_BEBUG_BLOCK0_BACKUP3_W1_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W1 field. + OTP_DEBUG_BLK0_BACKUP3_W1_OTP_BEBUG_BLOCK0_BACKUP3_W1_Msk = 0xffffffff + + // BLK0_BACKUP3_W2: Otp debuger block0 data register13. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W2 field. + OTP_DEBUG_BLK0_BACKUP3_W2_OTP_BEBUG_BLOCK0_BACKUP3_W2_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W2 field. + OTP_DEBUG_BLK0_BACKUP3_W2_OTP_BEBUG_BLOCK0_BACKUP3_W2_Msk = 0xffffffff + + // BLK0_BACKUP3_W3: Otp debuger block0 data register14. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W3 field. + OTP_DEBUG_BLK0_BACKUP3_W3_OTP_BEBUG_BLOCK0_BACKUP3_W3_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W3 field. + OTP_DEBUG_BLK0_BACKUP3_W3_OTP_BEBUG_BLOCK0_BACKUP3_W3_Msk = 0xffffffff + + // BLK0_BACKUP3_W4: Otp debuger block0 data register15. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W4 field. + OTP_DEBUG_BLK0_BACKUP3_W4_OTP_BEBUG_BLOCK0_BACKUP3_W4_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W4 field. + OTP_DEBUG_BLK0_BACKUP3_W4_OTP_BEBUG_BLOCK0_BACKUP3_W4_Msk = 0xffffffff + + // BLK0_BACKUP3_W5: Otp debuger block0 data register16. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W5 field. + OTP_DEBUG_BLK0_BACKUP3_W5_OTP_BEBUG_BLOCK0_BACKUP3_W5_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W5 field. + OTP_DEBUG_BLK0_BACKUP3_W5_OTP_BEBUG_BLOCK0_BACKUP3_W5_Msk = 0xffffffff + + // BLK0_BACKUP4_W1: Otp debuger block0 data register17. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W1 field. + OTP_DEBUG_BLK0_BACKUP4_W1_OTP_BEBUG_BLOCK0_BACKUP4_W1_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W1 field. + OTP_DEBUG_BLK0_BACKUP4_W1_OTP_BEBUG_BLOCK0_BACKUP4_W1_Msk = 0xffffffff + + // BLK0_BACKUP4_W2: Otp debuger block0 data register18. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W2 field. + OTP_DEBUG_BLK0_BACKUP4_W2_OTP_BEBUG_BLOCK0_BACKUP4_W2_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W2 field. + OTP_DEBUG_BLK0_BACKUP4_W2_OTP_BEBUG_BLOCK0_BACKUP4_W2_Msk = 0xffffffff + + // BLK0_BACKUP4_W3: Otp debuger block0 data register19. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W3 field. + OTP_DEBUG_BLK0_BACKUP4_W3_OTP_BEBUG_BLOCK0_BACKUP4_W3_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W3 field. + OTP_DEBUG_BLK0_BACKUP4_W3_OTP_BEBUG_BLOCK0_BACKUP4_W3_Msk = 0xffffffff + + // BLK0_BACKUP4_W4: Otp debuger block0 data register20. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W4 field. + OTP_DEBUG_BLK0_BACKUP4_W4_OTP_BEBUG_BLOCK0_BACKUP4_W4_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W4 field. + OTP_DEBUG_BLK0_BACKUP4_W4_OTP_BEBUG_BLOCK0_BACKUP4_W4_Msk = 0xffffffff + + // BLK0_BACKUP4_W5: Otp debuger block0 data register21. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W5 field. + OTP_DEBUG_BLK0_BACKUP4_W5_OTP_BEBUG_BLOCK0_BACKUP4_W5_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W5 field. + OTP_DEBUG_BLK0_BACKUP4_W5_OTP_BEBUG_BLOCK0_BACKUP4_W5_Msk = 0xffffffff + + // BLK1_W1: Otp debuger block1 data register1. + // Position of BLOCK1_W1 field. + OTP_DEBUG_BLK1_W1_BLOCK1_W1_Pos = 0x0 + // Bit mask of BLOCK1_W1 field. + OTP_DEBUG_BLK1_W1_BLOCK1_W1_Msk = 0xffffffff + + // BLK1_W2: Otp debuger block1 data register2. + // Position of BLOCK1_W2 field. + OTP_DEBUG_BLK1_W2_BLOCK1_W2_Pos = 0x0 + // Bit mask of BLOCK1_W2 field. + OTP_DEBUG_BLK1_W2_BLOCK1_W2_Msk = 0xffffffff + + // BLK1_W3: Otp debuger block1 data register3. + // Position of BLOCK1_W3 field. + OTP_DEBUG_BLK1_W3_BLOCK1_W3_Pos = 0x0 + // Bit mask of BLOCK1_W3 field. + OTP_DEBUG_BLK1_W3_BLOCK1_W3_Msk = 0xffffffff + + // BLK1_W4: Otp debuger block1 data register4. + // Position of BLOCK1_W4 field. + OTP_DEBUG_BLK1_W4_BLOCK1_W4_Pos = 0x0 + // Bit mask of BLOCK1_W4 field. + OTP_DEBUG_BLK1_W4_BLOCK1_W4_Msk = 0xffffffff + + // BLK1_W5: Otp debuger block1 data register5. + // Position of BLOCK1_W5 field. + OTP_DEBUG_BLK1_W5_BLOCK1_W5_Pos = 0x0 + // Bit mask of BLOCK1_W5 field. + OTP_DEBUG_BLK1_W5_BLOCK1_W5_Msk = 0xffffffff + + // BLK1_W6: Otp debuger block1 data register6. + // Position of BLOCK1_W6 field. + OTP_DEBUG_BLK1_W6_BLOCK1_W6_Pos = 0x0 + // Bit mask of BLOCK1_W6 field. + OTP_DEBUG_BLK1_W6_BLOCK1_W6_Msk = 0xffffffff + + // BLK1_W7: Otp debuger block1 data register7. + // Position of BLOCK1_W7 field. + OTP_DEBUG_BLK1_W7_BLOCK1_W7_Pos = 0x0 + // Bit mask of BLOCK1_W7 field. + OTP_DEBUG_BLK1_W7_BLOCK1_W7_Msk = 0xffffffff + + // BLK1_W8: Otp debuger block1 data register8. + // Position of BLOCK1_W8 field. + OTP_DEBUG_BLK1_W8_BLOCK1_W8_Pos = 0x0 + // Bit mask of BLOCK1_W8 field. + OTP_DEBUG_BLK1_W8_BLOCK1_W8_Msk = 0xffffffff + + // BLK1_W9: Otp debuger block1 data register9. + // Position of BLOCK1_W9 field. + OTP_DEBUG_BLK1_W9_BLOCK1_W9_Pos = 0x0 + // Bit mask of BLOCK1_W9 field. + OTP_DEBUG_BLK1_W9_BLOCK1_W9_Msk = 0xffffffff + + // BLK2_W1: Otp debuger block2 data register1. + // Position of BLOCK2_W1 field. + OTP_DEBUG_BLK2_W1_BLOCK2_W1_Pos = 0x0 + // Bit mask of BLOCK2_W1 field. + OTP_DEBUG_BLK2_W1_BLOCK2_W1_Msk = 0xffffffff + + // BLK2_W2: Otp debuger block2 data register2. + // Position of BLOCK2_W2 field. + OTP_DEBUG_BLK2_W2_BLOCK2_W2_Pos = 0x0 + // Bit mask of BLOCK2_W2 field. + OTP_DEBUG_BLK2_W2_BLOCK2_W2_Msk = 0xffffffff + + // BLK2_W3: Otp debuger block2 data register3. + // Position of BLOCK2_W3 field. + OTP_DEBUG_BLK2_W3_BLOCK2_W3_Pos = 0x0 + // Bit mask of BLOCK2_W3 field. + OTP_DEBUG_BLK2_W3_BLOCK2_W3_Msk = 0xffffffff + + // BLK2_W4: Otp debuger block2 data register4. + // Position of BLOCK2_W4 field. + OTP_DEBUG_BLK2_W4_BLOCK2_W4_Pos = 0x0 + // Bit mask of BLOCK2_W4 field. + OTP_DEBUG_BLK2_W4_BLOCK2_W4_Msk = 0xffffffff + + // BLK2_W5: Otp debuger block2 data register5. + // Position of BLOCK2_W5 field. + OTP_DEBUG_BLK2_W5_BLOCK2_W5_Pos = 0x0 + // Bit mask of BLOCK2_W5 field. + OTP_DEBUG_BLK2_W5_BLOCK2_W5_Msk = 0xffffffff + + // BLK2_W6: Otp debuger block2 data register6. + // Position of BLOCK2_W6 field. + OTP_DEBUG_BLK2_W6_BLOCK2_W6_Pos = 0x0 + // Bit mask of BLOCK2_W6 field. + OTP_DEBUG_BLK2_W6_BLOCK2_W6_Msk = 0xffffffff + + // BLK2_W7: Otp debuger block2 data register7. + // Position of BLOCK2_W7 field. + OTP_DEBUG_BLK2_W7_BLOCK2_W7_Pos = 0x0 + // Bit mask of BLOCK2_W7 field. + OTP_DEBUG_BLK2_W7_BLOCK2_W7_Msk = 0xffffffff + + // BLK2_W8: Otp debuger block2 data register8. + // Position of BLOCK2_W8 field. + OTP_DEBUG_BLK2_W8_BLOCK2_W8_Pos = 0x0 + // Bit mask of BLOCK2_W8 field. + OTP_DEBUG_BLK2_W8_BLOCK2_W8_Msk = 0xffffffff + + // BLK2_W9: Otp debuger block2 data register9. + // Position of BLOCK2_W9 field. + OTP_DEBUG_BLK2_W9_BLOCK2_W9_Pos = 0x0 + // Bit mask of BLOCK2_W9 field. + OTP_DEBUG_BLK2_W9_BLOCK2_W9_Msk = 0xffffffff + + // BLK2_W10: Otp debuger block2 data register10. + // Position of BLOCK2_W10 field. + OTP_DEBUG_BLK2_W10_BLOCK2_W10_Pos = 0x0 + // Bit mask of BLOCK2_W10 field. + OTP_DEBUG_BLK2_W10_BLOCK2_W10_Msk = 0xffffffff + + // BLK2_W11: Otp debuger block2 data register11. + // Position of BLOCK2_W11 field. + OTP_DEBUG_BLK2_W11_BLOCK2_W11_Pos = 0x0 + // Bit mask of BLOCK2_W11 field. + OTP_DEBUG_BLK2_W11_BLOCK2_W11_Msk = 0xffffffff + + // BLK3_W1: Otp debuger block3 data register1. + // Position of BLOCK3_W1 field. + OTP_DEBUG_BLK3_W1_BLOCK3_W1_Pos = 0x0 + // Bit mask of BLOCK3_W1 field. + OTP_DEBUG_BLK3_W1_BLOCK3_W1_Msk = 0xffffffff + + // BLK3_W2: Otp debuger block3 data register2. + // Position of BLOCK3_W2 field. + OTP_DEBUG_BLK3_W2_BLOCK3_W2_Pos = 0x0 + // Bit mask of BLOCK3_W2 field. + OTP_DEBUG_BLK3_W2_BLOCK3_W2_Msk = 0xffffffff + + // BLK3_W3: Otp debuger block3 data register3. + // Position of BLOCK3_W3 field. + OTP_DEBUG_BLK3_W3_BLOCK3_W3_Pos = 0x0 + // Bit mask of BLOCK3_W3 field. + OTP_DEBUG_BLK3_W3_BLOCK3_W3_Msk = 0xffffffff + + // BLK3_W4: Otp debuger block3 data register4. + // Position of BLOCK3_W4 field. + OTP_DEBUG_BLK3_W4_BLOCK3_W4_Pos = 0x0 + // Bit mask of BLOCK3_W4 field. + OTP_DEBUG_BLK3_W4_BLOCK3_W4_Msk = 0xffffffff + + // BLK3_W5: Otp debuger block3 data register5. + // Position of BLOCK3_W5 field. + OTP_DEBUG_BLK3_W5_BLOCK3_W5_Pos = 0x0 + // Bit mask of BLOCK3_W5 field. + OTP_DEBUG_BLK3_W5_BLOCK3_W5_Msk = 0xffffffff + + // BLK3_W6: Otp debuger block3 data register6. + // Position of BLOCK3_W6 field. + OTP_DEBUG_BLK3_W6_BLOCK3_W6_Pos = 0x0 + // Bit mask of BLOCK3_W6 field. + OTP_DEBUG_BLK3_W6_BLOCK3_W6_Msk = 0xffffffff + + // BLK3_W7: Otp debuger block3 data register7. + // Position of BLOCK3_W7 field. + OTP_DEBUG_BLK3_W7_BLOCK3_W7_Pos = 0x0 + // Bit mask of BLOCK3_W7 field. + OTP_DEBUG_BLK3_W7_BLOCK3_W7_Msk = 0xffffffff + + // BLK3_W8: Otp debuger block3 data register8. + // Position of BLOCK3_W8 field. + OTP_DEBUG_BLK3_W8_BLOCK3_W8_Pos = 0x0 + // Bit mask of BLOCK3_W8 field. + OTP_DEBUG_BLK3_W8_BLOCK3_W8_Msk = 0xffffffff + + // BLK3_W9: Otp debuger block3 data register9. + // Position of BLOCK3_W9 field. + OTP_DEBUG_BLK3_W9_BLOCK3_W9_Pos = 0x0 + // Bit mask of BLOCK3_W9 field. + OTP_DEBUG_BLK3_W9_BLOCK3_W9_Msk = 0xffffffff + + // BLK3_W10: Otp debuger block3 data register10. + // Position of BLOCK3_W10 field. + OTP_DEBUG_BLK3_W10_BLOCK3_W10_Pos = 0x0 + // Bit mask of BLOCK3_W10 field. + OTP_DEBUG_BLK3_W10_BLOCK3_W10_Msk = 0xffffffff + + // BLK3_W11: Otp debuger block3 data register11. + // Position of BLOCK3_W11 field. + OTP_DEBUG_BLK3_W11_BLOCK3_W11_Pos = 0x0 + // Bit mask of BLOCK3_W11 field. + OTP_DEBUG_BLK3_W11_BLOCK3_W11_Msk = 0xffffffff + + // BLK4_W1: Otp debuger block4 data register1. + // Position of BLOCK4_W1 field. + OTP_DEBUG_BLK4_W1_BLOCK4_W1_Pos = 0x0 + // Bit mask of BLOCK4_W1 field. + OTP_DEBUG_BLK4_W1_BLOCK4_W1_Msk = 0xffffffff + + // BLK4_W2: Otp debuger block4 data register2. + // Position of BLOCK4_W2 field. + OTP_DEBUG_BLK4_W2_BLOCK4_W2_Pos = 0x0 + // Bit mask of BLOCK4_W2 field. + OTP_DEBUG_BLK4_W2_BLOCK4_W2_Msk = 0xffffffff + + // BLK4_W3: Otp debuger block4 data register3. + // Position of BLOCK4_W3 field. + OTP_DEBUG_BLK4_W3_BLOCK4_W3_Pos = 0x0 + // Bit mask of BLOCK4_W3 field. + OTP_DEBUG_BLK4_W3_BLOCK4_W3_Msk = 0xffffffff + + // BLK4_W4: Otp debuger block4 data register4. + // Position of BLOCK4_W4 field. + OTP_DEBUG_BLK4_W4_BLOCK4_W4_Pos = 0x0 + // Bit mask of BLOCK4_W4 field. + OTP_DEBUG_BLK4_W4_BLOCK4_W4_Msk = 0xffffffff + + // BLK4_W5: Otp debuger block4 data register5. + // Position of BLOCK4_W5 field. + OTP_DEBUG_BLK4_W5_BLOCK4_W5_Pos = 0x0 + // Bit mask of BLOCK4_W5 field. + OTP_DEBUG_BLK4_W5_BLOCK4_W5_Msk = 0xffffffff + + // BLK4_W6: Otp debuger block4 data register6. + // Position of BLOCK4_W6 field. + OTP_DEBUG_BLK4_W6_BLOCK4_W6_Pos = 0x0 + // Bit mask of BLOCK4_W6 field. + OTP_DEBUG_BLK4_W6_BLOCK4_W6_Msk = 0xffffffff + + // BLK4_W7: Otp debuger block4 data register7. + // Position of BLOCK4_W7 field. + OTP_DEBUG_BLK4_W7_BLOCK4_W7_Pos = 0x0 + // Bit mask of BLOCK4_W7 field. + OTP_DEBUG_BLK4_W7_BLOCK4_W7_Msk = 0xffffffff + + // BLK4_W8: Otp debuger block4 data register8. + // Position of BLOCK4_W8 field. + OTP_DEBUG_BLK4_W8_BLOCK4_W8_Pos = 0x0 + // Bit mask of BLOCK4_W8 field. + OTP_DEBUG_BLK4_W8_BLOCK4_W8_Msk = 0xffffffff + + // BLK4_W9: Otp debuger block4 data register9. + // Position of BLOCK4_W9 field. + OTP_DEBUG_BLK4_W9_BLOCK4_W9_Pos = 0x0 + // Bit mask of BLOCK4_W9 field. + OTP_DEBUG_BLK4_W9_BLOCK4_W9_Msk = 0xffffffff + + // BLK4_W10: Otp debuger block4 data registe10. + // Position of BLOCK4_W10 field. + OTP_DEBUG_BLK4_W10_BLOCK4_W10_Pos = 0x0 + // Bit mask of BLOCK4_W10 field. + OTP_DEBUG_BLK4_W10_BLOCK4_W10_Msk = 0xffffffff + + // BLK4_W11: Otp debuger block4 data register11. + // Position of BLOCK4_W11 field. + OTP_DEBUG_BLK4_W11_BLOCK4_W11_Pos = 0x0 + // Bit mask of BLOCK4_W11 field. + OTP_DEBUG_BLK4_W11_BLOCK4_W11_Msk = 0xffffffff + + // BLK5_W1: Otp debuger block5 data register1. + // Position of BLOCK5_W1 field. + OTP_DEBUG_BLK5_W1_BLOCK5_W1_Pos = 0x0 + // Bit mask of BLOCK5_W1 field. + OTP_DEBUG_BLK5_W1_BLOCK5_W1_Msk = 0xffffffff + + // BLK5_W2: Otp debuger block5 data register2. + // Position of BLOCK5_W2 field. + OTP_DEBUG_BLK5_W2_BLOCK5_W2_Pos = 0x0 + // Bit mask of BLOCK5_W2 field. + OTP_DEBUG_BLK5_W2_BLOCK5_W2_Msk = 0xffffffff + + // BLK5_W3: Otp debuger block5 data register3. + // Position of BLOCK5_W3 field. + OTP_DEBUG_BLK5_W3_BLOCK5_W3_Pos = 0x0 + // Bit mask of BLOCK5_W3 field. + OTP_DEBUG_BLK5_W3_BLOCK5_W3_Msk = 0xffffffff + + // BLK5_W4: Otp debuger block5 data register4. + // Position of BLOCK5_W4 field. + OTP_DEBUG_BLK5_W4_BLOCK5_W4_Pos = 0x0 + // Bit mask of BLOCK5_W4 field. + OTP_DEBUG_BLK5_W4_BLOCK5_W4_Msk = 0xffffffff + + // BLK5_W5: Otp debuger block5 data register5. + // Position of BLOCK5_W5 field. + OTP_DEBUG_BLK5_W5_BLOCK5_W5_Pos = 0x0 + // Bit mask of BLOCK5_W5 field. + OTP_DEBUG_BLK5_W5_BLOCK5_W5_Msk = 0xffffffff + + // BLK5_W6: Otp debuger block5 data register6. + // Position of BLOCK5_W6 field. + OTP_DEBUG_BLK5_W6_BLOCK5_W6_Pos = 0x0 + // Bit mask of BLOCK5_W6 field. + OTP_DEBUG_BLK5_W6_BLOCK5_W6_Msk = 0xffffffff + + // BLK5_W7: Otp debuger block5 data register7. + // Position of BLOCK5_W7 field. + OTP_DEBUG_BLK5_W7_BLOCK5_W7_Pos = 0x0 + // Bit mask of BLOCK5_W7 field. + OTP_DEBUG_BLK5_W7_BLOCK5_W7_Msk = 0xffffffff + + // BLK5_W8: Otp debuger block5 data register8. + // Position of BLOCK5_W8 field. + OTP_DEBUG_BLK5_W8_BLOCK5_W8_Pos = 0x0 + // Bit mask of BLOCK5_W8 field. + OTP_DEBUG_BLK5_W8_BLOCK5_W8_Msk = 0xffffffff + + // BLK5_W9: Otp debuger block5 data register9. + // Position of BLOCK5_W9 field. + OTP_DEBUG_BLK5_W9_BLOCK5_W9_Pos = 0x0 + // Bit mask of BLOCK5_W9 field. + OTP_DEBUG_BLK5_W9_BLOCK5_W9_Msk = 0xffffffff + + // BLK5_W10: Otp debuger block5 data register10. + // Position of BLOCK5_W10 field. + OTP_DEBUG_BLK5_W10_BLOCK5_W10_Pos = 0x0 + // Bit mask of BLOCK5_W10 field. + OTP_DEBUG_BLK5_W10_BLOCK5_W10_Msk = 0xffffffff + + // BLK5_W11: Otp debuger block5 data register11. + // Position of BLOCK5_W11 field. + OTP_DEBUG_BLK5_W11_BLOCK5_W11_Pos = 0x0 + // Bit mask of BLOCK5_W11 field. + OTP_DEBUG_BLK5_W11_BLOCK5_W11_Msk = 0xffffffff + + // BLK6_W1: Otp debuger block6 data register1. + // Position of BLOCK6_W1 field. + OTP_DEBUG_BLK6_W1_BLOCK6_W1_Pos = 0x0 + // Bit mask of BLOCK6_W1 field. + OTP_DEBUG_BLK6_W1_BLOCK6_W1_Msk = 0xffffffff + + // BLK6_W2: Otp debuger block6 data register2. + // Position of BLOCK6_W2 field. + OTP_DEBUG_BLK6_W2_BLOCK6_W2_Pos = 0x0 + // Bit mask of BLOCK6_W2 field. + OTP_DEBUG_BLK6_W2_BLOCK6_W2_Msk = 0xffffffff + + // BLK6_W3: Otp debuger block6 data register3. + // Position of BLOCK6_W3 field. + OTP_DEBUG_BLK6_W3_BLOCK6_W3_Pos = 0x0 + // Bit mask of BLOCK6_W3 field. + OTP_DEBUG_BLK6_W3_BLOCK6_W3_Msk = 0xffffffff + + // BLK6_W4: Otp debuger block6 data register4. + // Position of BLOCK6_W4 field. + OTP_DEBUG_BLK6_W4_BLOCK6_W4_Pos = 0x0 + // Bit mask of BLOCK6_W4 field. + OTP_DEBUG_BLK6_W4_BLOCK6_W4_Msk = 0xffffffff + + // BLK6_W5: Otp debuger block6 data register5. + // Position of BLOCK6_W5 field. + OTP_DEBUG_BLK6_W5_BLOCK6_W5_Pos = 0x0 + // Bit mask of BLOCK6_W5 field. + OTP_DEBUG_BLK6_W5_BLOCK6_W5_Msk = 0xffffffff + + // BLK6_W6: Otp debuger block6 data register6. + // Position of BLOCK6_W6 field. + OTP_DEBUG_BLK6_W6_BLOCK6_W6_Pos = 0x0 + // Bit mask of BLOCK6_W6 field. + OTP_DEBUG_BLK6_W6_BLOCK6_W6_Msk = 0xffffffff + + // BLK6_W7: Otp debuger block6 data register7. + // Position of BLOCK6_W7 field. + OTP_DEBUG_BLK6_W7_BLOCK6_W7_Pos = 0x0 + // Bit mask of BLOCK6_W7 field. + OTP_DEBUG_BLK6_W7_BLOCK6_W7_Msk = 0xffffffff + + // BLK6_W8: Otp debuger block6 data register8. + // Position of BLOCK6_W8 field. + OTP_DEBUG_BLK6_W8_BLOCK6_W8_Pos = 0x0 + // Bit mask of BLOCK6_W8 field. + OTP_DEBUG_BLK6_W8_BLOCK6_W8_Msk = 0xffffffff + + // BLK6_W9: Otp debuger block6 data register9. + // Position of BLOCK6_W9 field. + OTP_DEBUG_BLK6_W9_BLOCK6_W9_Pos = 0x0 + // Bit mask of BLOCK6_W9 field. + OTP_DEBUG_BLK6_W9_BLOCK6_W9_Msk = 0xffffffff + + // BLK6_W10: Otp debuger block6 data register10. + // Position of BLOCK6_W10 field. + OTP_DEBUG_BLK6_W10_BLOCK6_W10_Pos = 0x0 + // Bit mask of BLOCK6_W10 field. + OTP_DEBUG_BLK6_W10_BLOCK6_W10_Msk = 0xffffffff + + // BLK6_W11: Otp debuger block6 data register11. + // Position of BLOCK6_W11 field. + OTP_DEBUG_BLK6_W11_BLOCK6_W11_Pos = 0x0 + // Bit mask of BLOCK6_W11 field. + OTP_DEBUG_BLK6_W11_BLOCK6_W11_Msk = 0xffffffff + + // BLK7_W1: Otp debuger block7 data register1. + // Position of BLOCK7_W1 field. + OTP_DEBUG_BLK7_W1_BLOCK7_W1_Pos = 0x0 + // Bit mask of BLOCK7_W1 field. + OTP_DEBUG_BLK7_W1_BLOCK7_W1_Msk = 0xffffffff + + // BLK7_W2: Otp debuger block7 data register2. + // Position of BLOCK7_W2 field. + OTP_DEBUG_BLK7_W2_BLOCK7_W2_Pos = 0x0 + // Bit mask of BLOCK7_W2 field. + OTP_DEBUG_BLK7_W2_BLOCK7_W2_Msk = 0xffffffff + + // BLK7_W3: Otp debuger block7 data register3. + // Position of BLOCK7_W3 field. + OTP_DEBUG_BLK7_W3_BLOCK7_W3_Pos = 0x0 + // Bit mask of BLOCK7_W3 field. + OTP_DEBUG_BLK7_W3_BLOCK7_W3_Msk = 0xffffffff + + // BLK7_W4: Otp debuger block7 data register4. + // Position of BLOCK7_W4 field. + OTP_DEBUG_BLK7_W4_BLOCK7_W4_Pos = 0x0 + // Bit mask of BLOCK7_W4 field. + OTP_DEBUG_BLK7_W4_BLOCK7_W4_Msk = 0xffffffff + + // BLK7_W5: Otp debuger block7 data register5. + // Position of BLOCK7_W5 field. + OTP_DEBUG_BLK7_W5_BLOCK7_W5_Pos = 0x0 + // Bit mask of BLOCK7_W5 field. + OTP_DEBUG_BLK7_W5_BLOCK7_W5_Msk = 0xffffffff + + // BLK7_W6: Otp debuger block7 data register6. + // Position of BLOCK7_W6 field. + OTP_DEBUG_BLK7_W6_BLOCK7_W6_Pos = 0x0 + // Bit mask of BLOCK7_W6 field. + OTP_DEBUG_BLK7_W6_BLOCK7_W6_Msk = 0xffffffff + + // BLK7_W7: Otp debuger block7 data register7. + // Position of BLOCK7_W7 field. + OTP_DEBUG_BLK7_W7_BLOCK7_W7_Pos = 0x0 + // Bit mask of BLOCK7_W7 field. + OTP_DEBUG_BLK7_W7_BLOCK7_W7_Msk = 0xffffffff + + // BLK7_W8: Otp debuger block7 data register8. + // Position of BLOCK7_W8 field. + OTP_DEBUG_BLK7_W8_BLOCK7_W8_Pos = 0x0 + // Bit mask of BLOCK7_W8 field. + OTP_DEBUG_BLK7_W8_BLOCK7_W8_Msk = 0xffffffff + + // BLK7_W9: Otp debuger block7 data register9. + // Position of BLOCK7_W9 field. + OTP_DEBUG_BLK7_W9_BLOCK7_W9_Pos = 0x0 + // Bit mask of BLOCK7_W9 field. + OTP_DEBUG_BLK7_W9_BLOCK7_W9_Msk = 0xffffffff + + // BLK7_W10: Otp debuger block7 data register10. + // Position of BLOCK7_W10 field. + OTP_DEBUG_BLK7_W10_BLOCK7_W10_Pos = 0x0 + // Bit mask of BLOCK7_W10 field. + OTP_DEBUG_BLK7_W10_BLOCK7_W10_Msk = 0xffffffff + + // BLK7_W11: Otp debuger block7 data register11. + // Position of BLOCK7_W11 field. + OTP_DEBUG_BLK7_W11_BLOCK7_W11_Pos = 0x0 + // Bit mask of BLOCK7_W11 field. + OTP_DEBUG_BLK7_W11_BLOCK7_W11_Msk = 0xffffffff + + // BLK8_W1: Otp debuger block8 data register1. + // Position of BLOCK8_W1 field. + OTP_DEBUG_BLK8_W1_BLOCK8_W1_Pos = 0x0 + // Bit mask of BLOCK8_W1 field. + OTP_DEBUG_BLK8_W1_BLOCK8_W1_Msk = 0xffffffff + + // BLK8_W2: Otp debuger block8 data register2. + // Position of BLOCK8_W2 field. + OTP_DEBUG_BLK8_W2_BLOCK8_W2_Pos = 0x0 + // Bit mask of BLOCK8_W2 field. + OTP_DEBUG_BLK8_W2_BLOCK8_W2_Msk = 0xffffffff + + // BLK8_W3: Otp debuger block8 data register3. + // Position of BLOCK8_W3 field. + OTP_DEBUG_BLK8_W3_BLOCK8_W3_Pos = 0x0 + // Bit mask of BLOCK8_W3 field. + OTP_DEBUG_BLK8_W3_BLOCK8_W3_Msk = 0xffffffff + + // BLK8_W4: Otp debuger block8 data register4. + // Position of BLOCK8_W4 field. + OTP_DEBUG_BLK8_W4_BLOCK8_W4_Pos = 0x0 + // Bit mask of BLOCK8_W4 field. + OTP_DEBUG_BLK8_W4_BLOCK8_W4_Msk = 0xffffffff + + // BLK8_W5: Otp debuger block8 data register5. + // Position of BLOCK8_W5 field. + OTP_DEBUG_BLK8_W5_BLOCK8_W5_Pos = 0x0 + // Bit mask of BLOCK8_W5 field. + OTP_DEBUG_BLK8_W5_BLOCK8_W5_Msk = 0xffffffff + + // BLK8_W6: Otp debuger block8 data register6. + // Position of BLOCK8_W6 field. + OTP_DEBUG_BLK8_W6_BLOCK8_W6_Pos = 0x0 + // Bit mask of BLOCK8_W6 field. + OTP_DEBUG_BLK8_W6_BLOCK8_W6_Msk = 0xffffffff + + // BLK8_W7: Otp debuger block8 data register7. + // Position of BLOCK8_W7 field. + OTP_DEBUG_BLK8_W7_BLOCK8_W7_Pos = 0x0 + // Bit mask of BLOCK8_W7 field. + OTP_DEBUG_BLK8_W7_BLOCK8_W7_Msk = 0xffffffff + + // BLK8_W8: Otp debuger block8 data register8. + // Position of BLOCK8_W8 field. + OTP_DEBUG_BLK8_W8_BLOCK8_W8_Pos = 0x0 + // Bit mask of BLOCK8_W8 field. + OTP_DEBUG_BLK8_W8_BLOCK8_W8_Msk = 0xffffffff + + // BLK8_W9: Otp debuger block8 data register9. + // Position of BLOCK8_W9 field. + OTP_DEBUG_BLK8_W9_BLOCK8_W9_Pos = 0x0 + // Bit mask of BLOCK8_W9 field. + OTP_DEBUG_BLK8_W9_BLOCK8_W9_Msk = 0xffffffff + + // BLK8_W10: Otp debuger block8 data register10. + // Position of BLOCK8_W10 field. + OTP_DEBUG_BLK8_W10_BLOCK8_W10_Pos = 0x0 + // Bit mask of BLOCK8_W10 field. + OTP_DEBUG_BLK8_W10_BLOCK8_W10_Msk = 0xffffffff + + // BLK8_W11: Otp debuger block8 data register11. + // Position of BLOCK8_W11 field. + OTP_DEBUG_BLK8_W11_BLOCK8_W11_Pos = 0x0 + // Bit mask of BLOCK8_W11 field. + OTP_DEBUG_BLK8_W11_BLOCK8_W11_Msk = 0xffffffff + + // BLK9_W1: Otp debuger block9 data register1. + // Position of BLOCK9_W1 field. + OTP_DEBUG_BLK9_W1_BLOCK9_W1_Pos = 0x0 + // Bit mask of BLOCK9_W1 field. + OTP_DEBUG_BLK9_W1_BLOCK9_W1_Msk = 0xffffffff + + // BLK9_W2: Otp debuger block9 data register2. + // Position of BLOCK9_W2 field. + OTP_DEBUG_BLK9_W2_BLOCK9_W2_Pos = 0x0 + // Bit mask of BLOCK9_W2 field. + OTP_DEBUG_BLK9_W2_BLOCK9_W2_Msk = 0xffffffff + + // BLK9_W3: Otp debuger block9 data register3. + // Position of BLOCK9_W3 field. + OTP_DEBUG_BLK9_W3_BLOCK9_W3_Pos = 0x0 + // Bit mask of BLOCK9_W3 field. + OTP_DEBUG_BLK9_W3_BLOCK9_W3_Msk = 0xffffffff + + // BLK9_W4: Otp debuger block9 data register4. + // Position of BLOCK9_W4 field. + OTP_DEBUG_BLK9_W4_BLOCK9_W4_Pos = 0x0 + // Bit mask of BLOCK9_W4 field. + OTP_DEBUG_BLK9_W4_BLOCK9_W4_Msk = 0xffffffff + + // BLK9_W5: Otp debuger block9 data register5. + // Position of BLOCK9_W5 field. + OTP_DEBUG_BLK9_W5_BLOCK9_W5_Pos = 0x0 + // Bit mask of BLOCK9_W5 field. + OTP_DEBUG_BLK9_W5_BLOCK9_W5_Msk = 0xffffffff + + // BLK9_W6: Otp debuger block9 data register6. + // Position of BLOCK9_W6 field. + OTP_DEBUG_BLK9_W6_BLOCK9_W6_Pos = 0x0 + // Bit mask of BLOCK9_W6 field. + OTP_DEBUG_BLK9_W6_BLOCK9_W6_Msk = 0xffffffff + + // BLK9_W7: Otp debuger block9 data register7. + // Position of BLOCK9_W7 field. + OTP_DEBUG_BLK9_W7_BLOCK9_W7_Pos = 0x0 + // Bit mask of BLOCK9_W7 field. + OTP_DEBUG_BLK9_W7_BLOCK9_W7_Msk = 0xffffffff + + // BLK9_W8: Otp debuger block9 data register8. + // Position of BLOCK9_W8 field. + OTP_DEBUG_BLK9_W8_BLOCK9_W8_Pos = 0x0 + // Bit mask of BLOCK9_W8 field. + OTP_DEBUG_BLK9_W8_BLOCK9_W8_Msk = 0xffffffff + + // BLK9_W9: Otp debuger block9 data register9. + // Position of BLOCK9_W9 field. + OTP_DEBUG_BLK9_W9_BLOCK9_W9_Pos = 0x0 + // Bit mask of BLOCK9_W9 field. + OTP_DEBUG_BLK9_W9_BLOCK9_W9_Msk = 0xffffffff + + // BLK9_W10: Otp debuger block9 data register10. + // Position of BLOCK9_W10 field. + OTP_DEBUG_BLK9_W10_BLOCK9_W10_Pos = 0x0 + // Bit mask of BLOCK9_W10 field. + OTP_DEBUG_BLK9_W10_BLOCK9_W10_Msk = 0xffffffff + + // BLK9_W11: Otp debuger block9 data register11. + // Position of BLOCK9_W11 field. + OTP_DEBUG_BLK9_W11_BLOCK9_W11_Pos = 0x0 + // Bit mask of BLOCK9_W11 field. + OTP_DEBUG_BLK9_W11_BLOCK9_W11_Msk = 0xffffffff + + // BLK10_W1: Otp debuger block10 data register1. + // Position of BLOCK10_W1 field. + OTP_DEBUG_BLK10_W1_BLOCK10_W1_Pos = 0x0 + // Bit mask of BLOCK10_W1 field. + OTP_DEBUG_BLK10_W1_BLOCK10_W1_Msk = 0xffffffff + + // BLK10_W2: Otp debuger block10 data register2. + // Position of BLOCK10_W2 field. + OTP_DEBUG_BLK10_W2_BLOCK10_W2_Pos = 0x0 + // Bit mask of BLOCK10_W2 field. + OTP_DEBUG_BLK10_W2_BLOCK10_W2_Msk = 0xffffffff + + // BLK10_W3: Otp debuger block10 data register3. + // Position of BLOCK10_W3 field. + OTP_DEBUG_BLK10_W3_BLOCK10_W3_Pos = 0x0 + // Bit mask of BLOCK10_W3 field. + OTP_DEBUG_BLK10_W3_BLOCK10_W3_Msk = 0xffffffff + + // BLK10_W4: Otp debuger block10 data register4. + // Position of BLOCK10_W4 field. + OTP_DEBUG_BLK10_W4_BLOCK10_W4_Pos = 0x0 + // Bit mask of BLOCK10_W4 field. + OTP_DEBUG_BLK10_W4_BLOCK10_W4_Msk = 0xffffffff + + // BLK10_W5: Otp debuger block10 data register5. + // Position of BLOCK10_W5 field. + OTP_DEBUG_BLK10_W5_BLOCK10_W5_Pos = 0x0 + // Bit mask of BLOCK10_W5 field. + OTP_DEBUG_BLK10_W5_BLOCK10_W5_Msk = 0xffffffff + + // BLK10_W6: Otp debuger block10 data register6. + // Position of BLOCK10_W6 field. + OTP_DEBUG_BLK10_W6_BLOCK10_W6_Pos = 0x0 + // Bit mask of BLOCK10_W6 field. + OTP_DEBUG_BLK10_W6_BLOCK10_W6_Msk = 0xffffffff + + // BLK10_W7: Otp debuger block10 data register7. + // Position of BLOCK10_W7 field. + OTP_DEBUG_BLK10_W7_BLOCK10_W7_Pos = 0x0 + // Bit mask of BLOCK10_W7 field. + OTP_DEBUG_BLK10_W7_BLOCK10_W7_Msk = 0xffffffff + + // BLK10_W8: Otp debuger block10 data register8. + // Position of BLOCK10_W8 field. + OTP_DEBUG_BLK10_W8_BLOCK10_W8_Pos = 0x0 + // Bit mask of BLOCK10_W8 field. + OTP_DEBUG_BLK10_W8_BLOCK10_W8_Msk = 0xffffffff + + // BLK10_W9: Otp debuger block10 data register9. + // Position of BLOCK10_W9 field. + OTP_DEBUG_BLK10_W9_BLOCK10_W9_Pos = 0x0 + // Bit mask of BLOCK10_W9 field. + OTP_DEBUG_BLK10_W9_BLOCK10_W9_Msk = 0xffffffff + + // BLK10_W10: Otp debuger block10 data register10. + // Position of BLOCK19_W10 field. + OTP_DEBUG_BLK10_W10_BLOCK19_W10_Pos = 0x0 + // Bit mask of BLOCK19_W10 field. + OTP_DEBUG_BLK10_W10_BLOCK19_W10_Msk = 0xffffffff + + // BLK10_W11: Otp debuger block10 data register11. + // Position of BLOCK10_W11 field. + OTP_DEBUG_BLK10_W11_BLOCK10_W11_Pos = 0x0 + // Bit mask of BLOCK10_W11 field. + OTP_DEBUG_BLK10_W11_BLOCK10_W11_Msk = 0xffffffff + + // CLK: Otp debuger clk_en configuration register. + // Position of EN field. + OTP_DEBUG_CLK_EN_Pos = 0x0 + // Bit mask of EN field. + OTP_DEBUG_CLK_EN_Msk = 0x1 + // Bit EN. + OTP_DEBUG_CLK_EN = 0x1 + + // APB2OTP_EN: Otp_debuger apb2otp enable configuration register. + // Position of APB2OTP_EN field. + OTP_DEBUG_APB2OTP_EN_APB2OTP_EN_Pos = 0x0 + // Bit mask of APB2OTP_EN field. + OTP_DEBUG_APB2OTP_EN_APB2OTP_EN_Msk = 0x1 + // Bit APB2OTP_EN. + OTP_DEBUG_APB2OTP_EN_APB2OTP_EN = 0x1 + + // DATE: eFuse version register. + // Position of DATE field. + OTP_DEBUG_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + OTP_DEBUG_DATE_DATE_Msk = 0xfffffff +) + +// Constants for PARL_IO: Parallel IO Controller +const ( + // RX_CFG0: Parallel RX module configuration register0. + // Position of RX_EOF_GEN_SEL field. + PARL_IO_RX_CFG0_RX_EOF_GEN_SEL_Pos = 0x0 + // Bit mask of RX_EOF_GEN_SEL field. + PARL_IO_RX_CFG0_RX_EOF_GEN_SEL_Msk = 0x1 + // Bit RX_EOF_GEN_SEL. + PARL_IO_RX_CFG0_RX_EOF_GEN_SEL = 0x1 + // Position of RX_START field. + PARL_IO_RX_CFG0_RX_START_Pos = 0x1 + // Bit mask of RX_START field. + PARL_IO_RX_CFG0_RX_START_Msk = 0x2 + // Bit RX_START. + PARL_IO_RX_CFG0_RX_START = 0x2 + // Position of RX_DATA_BYTELEN field. + PARL_IO_RX_CFG0_RX_DATA_BYTELEN_Pos = 0x2 + // Bit mask of RX_DATA_BYTELEN field. + PARL_IO_RX_CFG0_RX_DATA_BYTELEN_Msk = 0x3fffc + // Position of RX_SW_EN field. + PARL_IO_RX_CFG0_RX_SW_EN_Pos = 0x12 + // Bit mask of RX_SW_EN field. + PARL_IO_RX_CFG0_RX_SW_EN_Msk = 0x40000 + // Bit RX_SW_EN. + PARL_IO_RX_CFG0_RX_SW_EN = 0x40000 + // Position of RX_PULSE_SUBMODE_SEL field. + PARL_IO_RX_CFG0_RX_PULSE_SUBMODE_SEL_Pos = 0x13 + // Bit mask of RX_PULSE_SUBMODE_SEL field. + PARL_IO_RX_CFG0_RX_PULSE_SUBMODE_SEL_Msk = 0x780000 + // Position of RX_LEVEL_SUBMODE_SEL field. + PARL_IO_RX_CFG0_RX_LEVEL_SUBMODE_SEL_Pos = 0x17 + // Bit mask of RX_LEVEL_SUBMODE_SEL field. + PARL_IO_RX_CFG0_RX_LEVEL_SUBMODE_SEL_Msk = 0x800000 + // Bit RX_LEVEL_SUBMODE_SEL. + PARL_IO_RX_CFG0_RX_LEVEL_SUBMODE_SEL = 0x800000 + // Position of RX_SMP_MODE_SEL field. + PARL_IO_RX_CFG0_RX_SMP_MODE_SEL_Pos = 0x18 + // Bit mask of RX_SMP_MODE_SEL field. + PARL_IO_RX_CFG0_RX_SMP_MODE_SEL_Msk = 0x3000000 + // Position of RX_CLK_EDGE_SEL field. + PARL_IO_RX_CFG0_RX_CLK_EDGE_SEL_Pos = 0x1a + // Bit mask of RX_CLK_EDGE_SEL field. + PARL_IO_RX_CFG0_RX_CLK_EDGE_SEL_Msk = 0x4000000 + // Bit RX_CLK_EDGE_SEL. + PARL_IO_RX_CFG0_RX_CLK_EDGE_SEL = 0x4000000 + // Position of RX_BIT_PACK_ORDER field. + PARL_IO_RX_CFG0_RX_BIT_PACK_ORDER_Pos = 0x1b + // Bit mask of RX_BIT_PACK_ORDER field. + PARL_IO_RX_CFG0_RX_BIT_PACK_ORDER_Msk = 0x8000000 + // Bit RX_BIT_PACK_ORDER. + PARL_IO_RX_CFG0_RX_BIT_PACK_ORDER = 0x8000000 + // Position of RX_BUS_WID_SEL field. + PARL_IO_RX_CFG0_RX_BUS_WID_SEL_Pos = 0x1c + // Bit mask of RX_BUS_WID_SEL field. + PARL_IO_RX_CFG0_RX_BUS_WID_SEL_Msk = 0x70000000 + // Position of RX_FIFO_SRST field. + PARL_IO_RX_CFG0_RX_FIFO_SRST_Pos = 0x1f + // Bit mask of RX_FIFO_SRST field. + PARL_IO_RX_CFG0_RX_FIFO_SRST_Msk = 0x80000000 + // Bit RX_FIFO_SRST. + PARL_IO_RX_CFG0_RX_FIFO_SRST = 0x80000000 + + // RX_CFG1: Parallel RX module configuration register1. + // Position of RX_REG_UPDATE field. + PARL_IO_RX_CFG1_RX_REG_UPDATE_Pos = 0x2 + // Bit mask of RX_REG_UPDATE field. + PARL_IO_RX_CFG1_RX_REG_UPDATE_Msk = 0x4 + // Bit RX_REG_UPDATE. + PARL_IO_RX_CFG1_RX_REG_UPDATE = 0x4 + // Position of RX_TIMEOUT_EN field. + PARL_IO_RX_CFG1_RX_TIMEOUT_EN_Pos = 0x3 + // Bit mask of RX_TIMEOUT_EN field. + PARL_IO_RX_CFG1_RX_TIMEOUT_EN_Msk = 0x8 + // Bit RX_TIMEOUT_EN. + PARL_IO_RX_CFG1_RX_TIMEOUT_EN = 0x8 + // Position of RX_EXT_EN_SEL field. + PARL_IO_RX_CFG1_RX_EXT_EN_SEL_Pos = 0xc + // Bit mask of RX_EXT_EN_SEL field. + PARL_IO_RX_CFG1_RX_EXT_EN_SEL_Msk = 0xf000 + // Position of RX_TIMEOUT_THRESHOLD field. + PARL_IO_RX_CFG1_RX_TIMEOUT_THRESHOLD_Pos = 0x10 + // Bit mask of RX_TIMEOUT_THRESHOLD field. + PARL_IO_RX_CFG1_RX_TIMEOUT_THRESHOLD_Msk = 0xffff0000 + + // TX_CFG0: Parallel TX module configuration register0. + // Position of TX_BYTELEN field. + PARL_IO_TX_CFG0_TX_BYTELEN_Pos = 0x2 + // Bit mask of TX_BYTELEN field. + PARL_IO_TX_CFG0_TX_BYTELEN_Msk = 0x3fffc + // Position of TX_GATING_EN field. + PARL_IO_TX_CFG0_TX_GATING_EN_Pos = 0x12 + // Bit mask of TX_GATING_EN field. + PARL_IO_TX_CFG0_TX_GATING_EN_Msk = 0x40000 + // Bit TX_GATING_EN. + PARL_IO_TX_CFG0_TX_GATING_EN = 0x40000 + // Position of TX_START field. + PARL_IO_TX_CFG0_TX_START_Pos = 0x13 + // Bit mask of TX_START field. + PARL_IO_TX_CFG0_TX_START_Msk = 0x80000 + // Bit TX_START. + PARL_IO_TX_CFG0_TX_START = 0x80000 + // Position of TX_HW_VALID_EN field. + PARL_IO_TX_CFG0_TX_HW_VALID_EN_Pos = 0x14 + // Bit mask of TX_HW_VALID_EN field. + PARL_IO_TX_CFG0_TX_HW_VALID_EN_Msk = 0x100000 + // Bit TX_HW_VALID_EN. + PARL_IO_TX_CFG0_TX_HW_VALID_EN = 0x100000 + // Position of TX_SMP_EDGE_SEL field. + PARL_IO_TX_CFG0_TX_SMP_EDGE_SEL_Pos = 0x19 + // Bit mask of TX_SMP_EDGE_SEL field. + PARL_IO_TX_CFG0_TX_SMP_EDGE_SEL_Msk = 0x2000000 + // Bit TX_SMP_EDGE_SEL. + PARL_IO_TX_CFG0_TX_SMP_EDGE_SEL = 0x2000000 + // Position of TX_BIT_UNPACK_ORDER field. + PARL_IO_TX_CFG0_TX_BIT_UNPACK_ORDER_Pos = 0x1a + // Bit mask of TX_BIT_UNPACK_ORDER field. + PARL_IO_TX_CFG0_TX_BIT_UNPACK_ORDER_Msk = 0x4000000 + // Bit TX_BIT_UNPACK_ORDER. + PARL_IO_TX_CFG0_TX_BIT_UNPACK_ORDER = 0x4000000 + // Position of TX_BUS_WID_SEL field. + PARL_IO_TX_CFG0_TX_BUS_WID_SEL_Pos = 0x1b + // Bit mask of TX_BUS_WID_SEL field. + PARL_IO_TX_CFG0_TX_BUS_WID_SEL_Msk = 0x38000000 + // Position of TX_FIFO_SRST field. + PARL_IO_TX_CFG0_TX_FIFO_SRST_Pos = 0x1e + // Bit mask of TX_FIFO_SRST field. + PARL_IO_TX_CFG0_TX_FIFO_SRST_Msk = 0x40000000 + // Bit TX_FIFO_SRST. + PARL_IO_TX_CFG0_TX_FIFO_SRST = 0x40000000 + + // TX_CFG1: Parallel TX module configuration register1. + // Position of TX_IDLE_VALUE field. + PARL_IO_TX_CFG1_TX_IDLE_VALUE_Pos = 0x10 + // Bit mask of TX_IDLE_VALUE field. + PARL_IO_TX_CFG1_TX_IDLE_VALUE_Msk = 0xffff0000 + + // ST: Parallel IO module status register0. + // Position of TX_READY field. + PARL_IO_ST_TX_READY_Pos = 0x1f + // Bit mask of TX_READY field. + PARL_IO_ST_TX_READY_Msk = 0x80000000 + // Bit TX_READY. + PARL_IO_ST_TX_READY = 0x80000000 + + // INT_ENA: Parallel IO interrupt enable singal configuration register. + // Position of TX_FIFO_REMPTY_INT_ENA field. + PARL_IO_INT_ENA_TX_FIFO_REMPTY_INT_ENA_Pos = 0x0 + // Bit mask of TX_FIFO_REMPTY_INT_ENA field. + PARL_IO_INT_ENA_TX_FIFO_REMPTY_INT_ENA_Msk = 0x1 + // Bit TX_FIFO_REMPTY_INT_ENA. + PARL_IO_INT_ENA_TX_FIFO_REMPTY_INT_ENA = 0x1 + // Position of RX_FIFO_WFULL_INT_ENA field. + PARL_IO_INT_ENA_RX_FIFO_WFULL_INT_ENA_Pos = 0x1 + // Bit mask of RX_FIFO_WFULL_INT_ENA field. + PARL_IO_INT_ENA_RX_FIFO_WFULL_INT_ENA_Msk = 0x2 + // Bit RX_FIFO_WFULL_INT_ENA. + PARL_IO_INT_ENA_RX_FIFO_WFULL_INT_ENA = 0x2 + // Position of TX_EOF_INT_ENA field. + PARL_IO_INT_ENA_TX_EOF_INT_ENA_Pos = 0x2 + // Bit mask of TX_EOF_INT_ENA field. + PARL_IO_INT_ENA_TX_EOF_INT_ENA_Msk = 0x4 + // Bit TX_EOF_INT_ENA. + PARL_IO_INT_ENA_TX_EOF_INT_ENA = 0x4 + + // INT_RAW: Parallel IO interrupt raw singal status register. + // Position of TX_FIFO_REMPTY_INT_RAW field. + PARL_IO_INT_RAW_TX_FIFO_REMPTY_INT_RAW_Pos = 0x0 + // Bit mask of TX_FIFO_REMPTY_INT_RAW field. + PARL_IO_INT_RAW_TX_FIFO_REMPTY_INT_RAW_Msk = 0x1 + // Bit TX_FIFO_REMPTY_INT_RAW. + PARL_IO_INT_RAW_TX_FIFO_REMPTY_INT_RAW = 0x1 + // Position of RX_FIFO_WFULL_INT_RAW field. + PARL_IO_INT_RAW_RX_FIFO_WFULL_INT_RAW_Pos = 0x1 + // Bit mask of RX_FIFO_WFULL_INT_RAW field. + PARL_IO_INT_RAW_RX_FIFO_WFULL_INT_RAW_Msk = 0x2 + // Bit RX_FIFO_WFULL_INT_RAW. + PARL_IO_INT_RAW_RX_FIFO_WFULL_INT_RAW = 0x2 + // Position of TX_EOF_INT_RAW field. + PARL_IO_INT_RAW_TX_EOF_INT_RAW_Pos = 0x2 + // Bit mask of TX_EOF_INT_RAW field. + PARL_IO_INT_RAW_TX_EOF_INT_RAW_Msk = 0x4 + // Bit TX_EOF_INT_RAW. + PARL_IO_INT_RAW_TX_EOF_INT_RAW = 0x4 + + // INT_ST: Parallel IO interrupt singal status register. + // Position of TX_FIFO_REMPTY_INT_ST field. + PARL_IO_INT_ST_TX_FIFO_REMPTY_INT_ST_Pos = 0x0 + // Bit mask of TX_FIFO_REMPTY_INT_ST field. + PARL_IO_INT_ST_TX_FIFO_REMPTY_INT_ST_Msk = 0x1 + // Bit TX_FIFO_REMPTY_INT_ST. + PARL_IO_INT_ST_TX_FIFO_REMPTY_INT_ST = 0x1 + // Position of RX_FIFO_WFULL_INT_ST field. + PARL_IO_INT_ST_RX_FIFO_WFULL_INT_ST_Pos = 0x1 + // Bit mask of RX_FIFO_WFULL_INT_ST field. + PARL_IO_INT_ST_RX_FIFO_WFULL_INT_ST_Msk = 0x2 + // Bit RX_FIFO_WFULL_INT_ST. + PARL_IO_INT_ST_RX_FIFO_WFULL_INT_ST = 0x2 + // Position of TX_EOF_INT_ST field. + PARL_IO_INT_ST_TX_EOF_INT_ST_Pos = 0x2 + // Bit mask of TX_EOF_INT_ST field. + PARL_IO_INT_ST_TX_EOF_INT_ST_Msk = 0x4 + // Bit TX_EOF_INT_ST. + PARL_IO_INT_ST_TX_EOF_INT_ST = 0x4 + + // INT_CLR: Parallel IO interrupt clear singal configuration register. + // Position of TX_FIFO_REMPTY_INT_CLR field. + PARL_IO_INT_CLR_TX_FIFO_REMPTY_INT_CLR_Pos = 0x0 + // Bit mask of TX_FIFO_REMPTY_INT_CLR field. + PARL_IO_INT_CLR_TX_FIFO_REMPTY_INT_CLR_Msk = 0x1 + // Bit TX_FIFO_REMPTY_INT_CLR. + PARL_IO_INT_CLR_TX_FIFO_REMPTY_INT_CLR = 0x1 + // Position of RX_FIFO_WFULL_INT_CLR field. + PARL_IO_INT_CLR_RX_FIFO_WFULL_INT_CLR_Pos = 0x1 + // Bit mask of RX_FIFO_WFULL_INT_CLR field. + PARL_IO_INT_CLR_RX_FIFO_WFULL_INT_CLR_Msk = 0x2 + // Bit RX_FIFO_WFULL_INT_CLR. + PARL_IO_INT_CLR_RX_FIFO_WFULL_INT_CLR = 0x2 + // Position of TX_EOF_INT_CLR field. + PARL_IO_INT_CLR_TX_EOF_INT_CLR_Pos = 0x2 + // Bit mask of TX_EOF_INT_CLR field. + PARL_IO_INT_CLR_TX_EOF_INT_CLR_Msk = 0x4 + // Bit TX_EOF_INT_CLR. + PARL_IO_INT_CLR_TX_EOF_INT_CLR = 0x4 + + // CLK: Parallel IO clk configuration register + // Position of EN field. + PARL_IO_CLK_EN_Pos = 0x0 + // Bit mask of EN field. + PARL_IO_CLK_EN_Msk = 0x1 + // Bit EN. + PARL_IO_CLK_EN = 0x1 + + // VERSION: Version register. + // Position of DATE field. + PARL_IO_VERSION_DATE_Pos = 0x0 + // Bit mask of DATE field. + PARL_IO_VERSION_DATE_Msk = 0xfffffff +) + +// Constants for PAU: PAU Peripheral +const ( + // REGDMA_CONF: Peri backup control register + // Position of FLOW_ERR field. + PAU_REGDMA_CONF_FLOW_ERR_Pos = 0x0 + // Bit mask of FLOW_ERR field. + PAU_REGDMA_CONF_FLOW_ERR_Msk = 0x7 + // Position of START field. + PAU_REGDMA_CONF_START_Pos = 0x3 + // Bit mask of START field. + PAU_REGDMA_CONF_START_Msk = 0x8 + // Bit START. + PAU_REGDMA_CONF_START = 0x8 + // Position of TO_MEM field. + PAU_REGDMA_CONF_TO_MEM_Pos = 0x4 + // Bit mask of TO_MEM field. + PAU_REGDMA_CONF_TO_MEM_Msk = 0x10 + // Bit TO_MEM. + PAU_REGDMA_CONF_TO_MEM = 0x10 + // Position of LINK_SEL field. + PAU_REGDMA_CONF_LINK_SEL_Pos = 0x5 + // Bit mask of LINK_SEL field. + PAU_REGDMA_CONF_LINK_SEL_Msk = 0x60 + // Position of START_MAC field. + PAU_REGDMA_CONF_START_MAC_Pos = 0x7 + // Bit mask of START_MAC field. + PAU_REGDMA_CONF_START_MAC_Msk = 0x80 + // Bit START_MAC. + PAU_REGDMA_CONF_START_MAC = 0x80 + // Position of TO_MEM_MAC field. + PAU_REGDMA_CONF_TO_MEM_MAC_Pos = 0x8 + // Bit mask of TO_MEM_MAC field. + PAU_REGDMA_CONF_TO_MEM_MAC_Msk = 0x100 + // Bit TO_MEM_MAC. + PAU_REGDMA_CONF_TO_MEM_MAC = 0x100 + // Position of SEL_MAC field. + PAU_REGDMA_CONF_SEL_MAC_Pos = 0x9 + // Bit mask of SEL_MAC field. + PAU_REGDMA_CONF_SEL_MAC_Msk = 0x200 + // Bit SEL_MAC. + PAU_REGDMA_CONF_SEL_MAC = 0x200 + + // REGDMA_CLK_CONF: Clock control register + // Position of CLK_EN field. + PAU_REGDMA_CLK_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + PAU_REGDMA_CLK_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + PAU_REGDMA_CLK_CONF_CLK_EN = 0x1 + + // REGDMA_ETM_CTRL: ETM start ctrl reg + // Position of ETM_START_0 field. + PAU_REGDMA_ETM_CTRL_ETM_START_0_Pos = 0x0 + // Bit mask of ETM_START_0 field. + PAU_REGDMA_ETM_CTRL_ETM_START_0_Msk = 0x1 + // Bit ETM_START_0. + PAU_REGDMA_ETM_CTRL_ETM_START_0 = 0x1 + // Position of ETM_START_1 field. + PAU_REGDMA_ETM_CTRL_ETM_START_1_Pos = 0x1 + // Bit mask of ETM_START_1 field. + PAU_REGDMA_ETM_CTRL_ETM_START_1_Msk = 0x2 + // Bit ETM_START_1. + PAU_REGDMA_ETM_CTRL_ETM_START_1 = 0x2 + // Position of ETM_START_2 field. + PAU_REGDMA_ETM_CTRL_ETM_START_2_Pos = 0x2 + // Bit mask of ETM_START_2 field. + PAU_REGDMA_ETM_CTRL_ETM_START_2_Msk = 0x4 + // Bit ETM_START_2. + PAU_REGDMA_ETM_CTRL_ETM_START_2 = 0x4 + // Position of ETM_START_3 field. + PAU_REGDMA_ETM_CTRL_ETM_START_3_Pos = 0x3 + // Bit mask of ETM_START_3 field. + PAU_REGDMA_ETM_CTRL_ETM_START_3_Msk = 0x8 + // Bit ETM_START_3. + PAU_REGDMA_ETM_CTRL_ETM_START_3 = 0x8 + + // REGDMA_LINK_0_ADDR: link_0_addr + // Position of LINK_ADDR_0 field. + PAU_REGDMA_LINK_0_ADDR_LINK_ADDR_0_Pos = 0x0 + // Bit mask of LINK_ADDR_0 field. + PAU_REGDMA_LINK_0_ADDR_LINK_ADDR_0_Msk = 0xffffffff + + // REGDMA_LINK_1_ADDR: Link_1_addr + // Position of LINK_ADDR_1 field. + PAU_REGDMA_LINK_1_ADDR_LINK_ADDR_1_Pos = 0x0 + // Bit mask of LINK_ADDR_1 field. + PAU_REGDMA_LINK_1_ADDR_LINK_ADDR_1_Msk = 0xffffffff + + // REGDMA_LINK_2_ADDR: Link_2_addr + // Position of LINK_ADDR_2 field. + PAU_REGDMA_LINK_2_ADDR_LINK_ADDR_2_Pos = 0x0 + // Bit mask of LINK_ADDR_2 field. + PAU_REGDMA_LINK_2_ADDR_LINK_ADDR_2_Msk = 0xffffffff + + // REGDMA_LINK_3_ADDR: Link_3_addr + // Position of LINK_ADDR_3 field. + PAU_REGDMA_LINK_3_ADDR_LINK_ADDR_3_Pos = 0x0 + // Bit mask of LINK_ADDR_3 field. + PAU_REGDMA_LINK_3_ADDR_LINK_ADDR_3_Msk = 0xffffffff + + // REGDMA_LINK_MAC_ADDR: Link_mac_addr + // Position of LINK_ADDR_MAC field. + PAU_REGDMA_LINK_MAC_ADDR_LINK_ADDR_MAC_Pos = 0x0 + // Bit mask of LINK_ADDR_MAC field. + PAU_REGDMA_LINK_MAC_ADDR_LINK_ADDR_MAC_Msk = 0xffffffff + + // REGDMA_CURRENT_LINK_ADDR: current link addr + // Position of CURRENT_LINK_ADDR field. + PAU_REGDMA_CURRENT_LINK_ADDR_CURRENT_LINK_ADDR_Pos = 0x0 + // Bit mask of CURRENT_LINK_ADDR field. + PAU_REGDMA_CURRENT_LINK_ADDR_CURRENT_LINK_ADDR_Msk = 0xffffffff + + // REGDMA_BACKUP_ADDR: Backup addr + // Position of BACKUP_ADDR field. + PAU_REGDMA_BACKUP_ADDR_BACKUP_ADDR_Pos = 0x0 + // Bit mask of BACKUP_ADDR field. + PAU_REGDMA_BACKUP_ADDR_BACKUP_ADDR_Msk = 0xffffffff + + // REGDMA_MEM_ADDR: mem addr + // Position of MEM_ADDR field. + PAU_REGDMA_MEM_ADDR_MEM_ADDR_Pos = 0x0 + // Bit mask of MEM_ADDR field. + PAU_REGDMA_MEM_ADDR_MEM_ADDR_Msk = 0xffffffff + + // REGDMA_BKP_CONF: backup config + // Position of READ_INTERVAL field. + PAU_REGDMA_BKP_CONF_READ_INTERVAL_Pos = 0x0 + // Bit mask of READ_INTERVAL field. + PAU_REGDMA_BKP_CONF_READ_INTERVAL_Msk = 0x7f + // Position of LINK_TOUT_THRES field. + PAU_REGDMA_BKP_CONF_LINK_TOUT_THRES_Pos = 0x7 + // Bit mask of LINK_TOUT_THRES field. + PAU_REGDMA_BKP_CONF_LINK_TOUT_THRES_Msk = 0x1ff80 + // Position of BURST_LIMIT field. + PAU_REGDMA_BKP_CONF_BURST_LIMIT_Pos = 0x11 + // Bit mask of BURST_LIMIT field. + PAU_REGDMA_BKP_CONF_BURST_LIMIT_Msk = 0x3e0000 + // Position of BACKUP_TOUT_THRES field. + PAU_REGDMA_BKP_CONF_BACKUP_TOUT_THRES_Pos = 0x16 + // Bit mask of BACKUP_TOUT_THRES field. + PAU_REGDMA_BKP_CONF_BACKUP_TOUT_THRES_Msk = 0xffc00000 + + // RETENTION_LINK_BASE: retention dma link base + // Position of LINK_BASE_ADDR field. + PAU_RETENTION_LINK_BASE_LINK_BASE_ADDR_Pos = 0x0 + // Bit mask of LINK_BASE_ADDR field. + PAU_RETENTION_LINK_BASE_LINK_BASE_ADDR_Msk = 0x7ffffff + + // RETENTION_CFG: retention_cfg + // Position of RET_INV_CFG field. + PAU_RETENTION_CFG_RET_INV_CFG_Pos = 0x0 + // Bit mask of RET_INV_CFG field. + PAU_RETENTION_CFG_RET_INV_CFG_Msk = 0xffffffff + + // INT_ENA: Read only register for error and done + // Position of DONE_INT_ENA field. + PAU_INT_ENA_DONE_INT_ENA_Pos = 0x0 + // Bit mask of DONE_INT_ENA field. + PAU_INT_ENA_DONE_INT_ENA_Msk = 0x1 + // Bit DONE_INT_ENA. + PAU_INT_ENA_DONE_INT_ENA = 0x1 + // Position of ERROR_INT_ENA field. + PAU_INT_ENA_ERROR_INT_ENA_Pos = 0x1 + // Bit mask of ERROR_INT_ENA field. + PAU_INT_ENA_ERROR_INT_ENA_Msk = 0x2 + // Bit ERROR_INT_ENA. + PAU_INT_ENA_ERROR_INT_ENA = 0x2 + + // INT_RAW: Read only register for error and done + // Position of DONE_INT_RAW field. + PAU_INT_RAW_DONE_INT_RAW_Pos = 0x0 + // Bit mask of DONE_INT_RAW field. + PAU_INT_RAW_DONE_INT_RAW_Msk = 0x1 + // Bit DONE_INT_RAW. + PAU_INT_RAW_DONE_INT_RAW = 0x1 + // Position of ERROR_INT_RAW field. + PAU_INT_RAW_ERROR_INT_RAW_Pos = 0x1 + // Bit mask of ERROR_INT_RAW field. + PAU_INT_RAW_ERROR_INT_RAW_Msk = 0x2 + // Bit ERROR_INT_RAW. + PAU_INT_RAW_ERROR_INT_RAW = 0x2 + + // INT_CLR: Read only register for error and done + // Position of DONE_INT_CLR field. + PAU_INT_CLR_DONE_INT_CLR_Pos = 0x0 + // Bit mask of DONE_INT_CLR field. + PAU_INT_CLR_DONE_INT_CLR_Msk = 0x1 + // Bit DONE_INT_CLR. + PAU_INT_CLR_DONE_INT_CLR = 0x1 + // Position of ERROR_INT_CLR field. + PAU_INT_CLR_ERROR_INT_CLR_Pos = 0x1 + // Bit mask of ERROR_INT_CLR field. + PAU_INT_CLR_ERROR_INT_CLR_Msk = 0x2 + // Bit ERROR_INT_CLR. + PAU_INT_CLR_ERROR_INT_CLR = 0x2 + + // INT_ST: Read only register for error and done + // Position of DONE_INT_ST field. + PAU_INT_ST_DONE_INT_ST_Pos = 0x0 + // Bit mask of DONE_INT_ST field. + PAU_INT_ST_DONE_INT_ST_Msk = 0x1 + // Bit DONE_INT_ST. + PAU_INT_ST_DONE_INT_ST = 0x1 + // Position of ERROR_INT_ST field. + PAU_INT_ST_ERROR_INT_ST_Pos = 0x1 + // Bit mask of ERROR_INT_ST field. + PAU_INT_ST_ERROR_INT_ST_Msk = 0x2 + // Bit ERROR_INT_ST. + PAU_INT_ST_ERROR_INT_ST = 0x2 + + // DATE: Date register. + // Position of DATE field. + PAU_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PAU_DATE_DATE_Msk = 0xfffffff +) + +// Constants for PCNT: Pulse Count Controller +const ( + // U0_CONF0: Configuration register 0 for unit %s + // Position of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Pos = 0x0 + // Bit mask of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Msk = 0x3ff + // Position of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Pos = 0xa + // Bit mask of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Msk = 0x400 + // Bit FILTER_EN. + PCNT_U_CONF0_FILTER_EN = 0x400 + // Position of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Pos = 0xb + // Bit mask of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Msk = 0x800 + // Bit THR_ZERO_EN. + PCNT_U_CONF0_THR_ZERO_EN = 0x800 + // Position of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Pos = 0xc + // Bit mask of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Msk = 0x1000 + // Bit THR_H_LIM_EN. + PCNT_U_CONF0_THR_H_LIM_EN = 0x1000 + // Position of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Pos = 0xd + // Bit mask of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Msk = 0x2000 + // Bit THR_L_LIM_EN. + PCNT_U_CONF0_THR_L_LIM_EN = 0x2000 + // Position of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Pos = 0xe + // Bit mask of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Msk = 0x4000 + // Bit THR_THRES0_EN. + PCNT_U_CONF0_THR_THRES0_EN = 0x4000 + // Position of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Pos = 0xf + // Bit mask of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Msk = 0x8000 + // Bit THR_THRES1_EN. + PCNT_U_CONF0_THR_THRES1_EN = 0x8000 + // Position of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Pos = 0x10 + // Bit mask of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Msk = 0x30000 + // Position of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Pos = 0x12 + // Bit mask of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Msk = 0xc0000 + // Position of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Pos = 0x14 + // Bit mask of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Msk = 0x300000 + // Position of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Pos = 0x16 + // Bit mask of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Msk = 0xc00000 + // Position of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Pos = 0x18 + // Bit mask of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Msk = 0x3000000 + // Position of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Pos = 0x1a + // Bit mask of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Msk = 0xc000000 + // Position of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Pos = 0x1c + // Bit mask of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Msk = 0x30000000 + // Position of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Pos = 0x1e + // Bit mask of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Msk = 0xc0000000 + + // U0_CONF1: Configuration register 1 for unit %s + // Position of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Pos = 0x0 + // Bit mask of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Msk = 0xffff + // Position of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Pos = 0x10 + // Bit mask of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Msk = 0xffff0000 + + // U0_CONF2: Configuration register 2 for unit %s + // Position of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Pos = 0x0 + // Bit mask of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Msk = 0xffff + // Position of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Pos = 0x10 + // Bit mask of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Msk = 0xffff0000 + + // U0_CNT: Counter value for unit %s + // Position of CNT field. + PCNT_U_CNT_CNT_Pos = 0x0 + // Bit mask of CNT field. + PCNT_U_CNT_CNT_Msk = 0xffff + + // INT_RAW: Interrupt raw status register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_RAW_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_RAW_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_RAW_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_RAW_CNT_THR_EVENT_U3 = 0x8 + + // INT_ST: Interrupt status register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ST_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ST_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ST_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ST_CNT_THR_EVENT_U3 = 0x8 + + // INT_ENA: Interrupt enable register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ENA_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ENA_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ENA_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ENA_CNT_THR_EVENT_U3 = 0x8 + + // INT_CLR: Interrupt clear register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_CLR_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_CLR_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_CLR_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_CLR_CNT_THR_EVENT_U3 = 0x8 + + // U0_STATUS: PNCT UNIT%s status register + // Position of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Pos = 0x0 + // Bit mask of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Msk = 0x3 + // Position of THRES1 field. + PCNT_U_STATUS_THRES1_Pos = 0x2 + // Bit mask of THRES1 field. + PCNT_U_STATUS_THRES1_Msk = 0x4 + // Bit THRES1. + PCNT_U_STATUS_THRES1 = 0x4 + // Position of THRES0 field. + PCNT_U_STATUS_THRES0_Pos = 0x3 + // Bit mask of THRES0 field. + PCNT_U_STATUS_THRES0_Msk = 0x8 + // Bit THRES0. + PCNT_U_STATUS_THRES0 = 0x8 + // Position of L_LIM field. + PCNT_U_STATUS_L_LIM_Pos = 0x4 + // Bit mask of L_LIM field. + PCNT_U_STATUS_L_LIM_Msk = 0x10 + // Bit L_LIM. + PCNT_U_STATUS_L_LIM = 0x10 + // Position of H_LIM field. + PCNT_U_STATUS_H_LIM_Pos = 0x5 + // Bit mask of H_LIM field. + PCNT_U_STATUS_H_LIM_Msk = 0x20 + // Bit H_LIM. + PCNT_U_STATUS_H_LIM = 0x20 + // Position of ZERO field. + PCNT_U_STATUS_ZERO_Pos = 0x6 + // Bit mask of ZERO field. + PCNT_U_STATUS_ZERO_Msk = 0x40 + // Bit ZERO. + PCNT_U_STATUS_ZERO = 0x40 + + // CTRL: Control register for all counters + // Position of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Pos = 0x0 + // Bit mask of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Msk = 0x1 + // Bit CNT_RST_U0. + PCNT_CTRL_CNT_RST_U0 = 0x1 + // Position of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Pos = 0x1 + // Bit mask of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Msk = 0x2 + // Bit CNT_PAUSE_U0. + PCNT_CTRL_CNT_PAUSE_U0 = 0x2 + // Position of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Pos = 0x2 + // Bit mask of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Msk = 0x4 + // Bit CNT_RST_U1. + PCNT_CTRL_CNT_RST_U1 = 0x4 + // Position of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Pos = 0x3 + // Bit mask of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Msk = 0x8 + // Bit CNT_PAUSE_U1. + PCNT_CTRL_CNT_PAUSE_U1 = 0x8 + // Position of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Pos = 0x4 + // Bit mask of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Msk = 0x10 + // Bit CNT_RST_U2. + PCNT_CTRL_CNT_RST_U2 = 0x10 + // Position of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Pos = 0x5 + // Bit mask of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Msk = 0x20 + // Bit CNT_PAUSE_U2. + PCNT_CTRL_CNT_PAUSE_U2 = 0x20 + // Position of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Pos = 0x6 + // Bit mask of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Msk = 0x40 + // Bit CNT_RST_U3. + PCNT_CTRL_CNT_RST_U3 = 0x40 + // Position of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Pos = 0x7 + // Bit mask of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Msk = 0x80 + // Bit CNT_PAUSE_U3. + PCNT_CTRL_CNT_PAUSE_U3 = 0x80 + // Position of CLK_EN field. + PCNT_CTRL_CLK_EN_Pos = 0x10 + // Bit mask of CLK_EN field. + PCNT_CTRL_CLK_EN_Msk = 0x10000 + // Bit CLK_EN. + PCNT_CTRL_CLK_EN = 0x10000 + + // DATE: PCNT version control register + // Position of DATE field. + PCNT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PCNT_DATE_DATE_Msk = 0xffffffff +) + +// Constants for PCR: PCR Peripheral +const ( + // UART0_CONF: UART0 configuration register + // Position of UART0_CLK_EN field. + PCR_UART0_CONF_UART0_CLK_EN_Pos = 0x0 + // Bit mask of UART0_CLK_EN field. + PCR_UART0_CONF_UART0_CLK_EN_Msk = 0x1 + // Bit UART0_CLK_EN. + PCR_UART0_CONF_UART0_CLK_EN = 0x1 + // Position of UART0_RST_EN field. + PCR_UART0_CONF_UART0_RST_EN_Pos = 0x1 + // Bit mask of UART0_RST_EN field. + PCR_UART0_CONF_UART0_RST_EN_Msk = 0x2 + // Bit UART0_RST_EN. + PCR_UART0_CONF_UART0_RST_EN = 0x2 + + // UART0_SCLK_CONF: UART0_SCLK configuration register + // Position of UART0_SCLK_DIV_A field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_A_Pos = 0x0 + // Bit mask of UART0_SCLK_DIV_A field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_A_Msk = 0x3f + // Position of UART0_SCLK_DIV_B field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_B_Pos = 0x6 + // Bit mask of UART0_SCLK_DIV_B field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_B_Msk = 0xfc0 + // Position of UART0_SCLK_DIV_NUM field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of UART0_SCLK_DIV_NUM field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_NUM_Msk = 0xff000 + // Position of UART0_SCLK_SEL field. + PCR_UART0_SCLK_CONF_UART0_SCLK_SEL_Pos = 0x14 + // Bit mask of UART0_SCLK_SEL field. + PCR_UART0_SCLK_CONF_UART0_SCLK_SEL_Msk = 0x300000 + // Position of UART0_SCLK_EN field. + PCR_UART0_SCLK_CONF_UART0_SCLK_EN_Pos = 0x16 + // Bit mask of UART0_SCLK_EN field. + PCR_UART0_SCLK_CONF_UART0_SCLK_EN_Msk = 0x400000 + // Bit UART0_SCLK_EN. + PCR_UART0_SCLK_CONF_UART0_SCLK_EN = 0x400000 + + // UART0_PD_CTRL: UART0 power control register + // Position of UART0_MEM_FORCE_PU field. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of UART0_MEM_FORCE_PU field. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PU_Msk = 0x2 + // Bit UART0_MEM_FORCE_PU. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PU = 0x2 + // Position of UART0_MEM_FORCE_PD field. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of UART0_MEM_FORCE_PD field. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PD_Msk = 0x4 + // Bit UART0_MEM_FORCE_PD. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PD = 0x4 + + // UART1_CONF: UART1 configuration register + // Position of UART1_CLK_EN field. + PCR_UART1_CONF_UART1_CLK_EN_Pos = 0x0 + // Bit mask of UART1_CLK_EN field. + PCR_UART1_CONF_UART1_CLK_EN_Msk = 0x1 + // Bit UART1_CLK_EN. + PCR_UART1_CONF_UART1_CLK_EN = 0x1 + // Position of UART1_RST_EN field. + PCR_UART1_CONF_UART1_RST_EN_Pos = 0x1 + // Bit mask of UART1_RST_EN field. + PCR_UART1_CONF_UART1_RST_EN_Msk = 0x2 + // Bit UART1_RST_EN. + PCR_UART1_CONF_UART1_RST_EN = 0x2 + + // UART1_SCLK_CONF: UART1_SCLK configuration register + // Position of UART1_SCLK_DIV_A field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_A_Pos = 0x0 + // Bit mask of UART1_SCLK_DIV_A field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_A_Msk = 0x3f + // Position of UART1_SCLK_DIV_B field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_B_Pos = 0x6 + // Bit mask of UART1_SCLK_DIV_B field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_B_Msk = 0xfc0 + // Position of UART1_SCLK_DIV_NUM field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of UART1_SCLK_DIV_NUM field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_NUM_Msk = 0xff000 + // Position of UART1_SCLK_SEL field. + PCR_UART1_SCLK_CONF_UART1_SCLK_SEL_Pos = 0x14 + // Bit mask of UART1_SCLK_SEL field. + PCR_UART1_SCLK_CONF_UART1_SCLK_SEL_Msk = 0x300000 + // Position of UART1_SCLK_EN field. + PCR_UART1_SCLK_CONF_UART1_SCLK_EN_Pos = 0x16 + // Bit mask of UART1_SCLK_EN field. + PCR_UART1_SCLK_CONF_UART1_SCLK_EN_Msk = 0x400000 + // Bit UART1_SCLK_EN. + PCR_UART1_SCLK_CONF_UART1_SCLK_EN = 0x400000 + + // UART1_PD_CTRL: UART1 power control register + // Position of UART1_MEM_FORCE_PU field. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of UART1_MEM_FORCE_PU field. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PU_Msk = 0x2 + // Bit UART1_MEM_FORCE_PU. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PU = 0x2 + // Position of UART1_MEM_FORCE_PD field. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of UART1_MEM_FORCE_PD field. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PD_Msk = 0x4 + // Bit UART1_MEM_FORCE_PD. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PD = 0x4 + + // MSPI_CONF: MSPI configuration register + // Position of MSPI_CLK_EN field. + PCR_MSPI_CONF_MSPI_CLK_EN_Pos = 0x0 + // Bit mask of MSPI_CLK_EN field. + PCR_MSPI_CONF_MSPI_CLK_EN_Msk = 0x1 + // Bit MSPI_CLK_EN. + PCR_MSPI_CONF_MSPI_CLK_EN = 0x1 + // Position of MSPI_RST_EN field. + PCR_MSPI_CONF_MSPI_RST_EN_Pos = 0x1 + // Bit mask of MSPI_RST_EN field. + PCR_MSPI_CONF_MSPI_RST_EN_Msk = 0x2 + // Bit MSPI_RST_EN. + PCR_MSPI_CONF_MSPI_RST_EN = 0x2 + // Position of MSPI_PLL_CLK_EN field. + PCR_MSPI_CONF_MSPI_PLL_CLK_EN_Pos = 0x2 + // Bit mask of MSPI_PLL_CLK_EN field. + PCR_MSPI_CONF_MSPI_PLL_CLK_EN_Msk = 0x4 + // Bit MSPI_PLL_CLK_EN. + PCR_MSPI_CONF_MSPI_PLL_CLK_EN = 0x4 + + // MSPI_CLK_CONF: MSPI_CLK configuration register + // Position of MSPI_FAST_LS_DIV_NUM field. + PCR_MSPI_CLK_CONF_MSPI_FAST_LS_DIV_NUM_Pos = 0x0 + // Bit mask of MSPI_FAST_LS_DIV_NUM field. + PCR_MSPI_CLK_CONF_MSPI_FAST_LS_DIV_NUM_Msk = 0xff + // Position of MSPI_FAST_HS_DIV_NUM field. + PCR_MSPI_CLK_CONF_MSPI_FAST_HS_DIV_NUM_Pos = 0x8 + // Bit mask of MSPI_FAST_HS_DIV_NUM field. + PCR_MSPI_CLK_CONF_MSPI_FAST_HS_DIV_NUM_Msk = 0xff00 + + // I2C0_CONF: I2C configuration register + // Position of I2C0_CLK_EN field. + PCR_I2C0_CONF_I2C0_CLK_EN_Pos = 0x0 + // Bit mask of I2C0_CLK_EN field. + PCR_I2C0_CONF_I2C0_CLK_EN_Msk = 0x1 + // Bit I2C0_CLK_EN. + PCR_I2C0_CONF_I2C0_CLK_EN = 0x1 + // Position of I2C0_RST_EN field. + PCR_I2C0_CONF_I2C0_RST_EN_Pos = 0x1 + // Bit mask of I2C0_RST_EN field. + PCR_I2C0_CONF_I2C0_RST_EN_Msk = 0x2 + // Bit I2C0_RST_EN. + PCR_I2C0_CONF_I2C0_RST_EN = 0x2 + + // I2C_SCLK_CONF: I2C_SCLK configuration register + // Position of I2C_SCLK_DIV_A field. + PCR_I2C_SCLK_CONF_I2C_SCLK_DIV_A_Pos = 0x0 + // Bit mask of I2C_SCLK_DIV_A field. + PCR_I2C_SCLK_CONF_I2C_SCLK_DIV_A_Msk = 0x3f + // Position of I2C_SCLK_DIV_B field. + PCR_I2C_SCLK_CONF_I2C_SCLK_DIV_B_Pos = 0x6 + // Bit mask of I2C_SCLK_DIV_B field. + PCR_I2C_SCLK_CONF_I2C_SCLK_DIV_B_Msk = 0xfc0 + // Position of I2C_SCLK_DIV_NUM field. + PCR_I2C_SCLK_CONF_I2C_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of I2C_SCLK_DIV_NUM field. + PCR_I2C_SCLK_CONF_I2C_SCLK_DIV_NUM_Msk = 0xff000 + // Position of I2C_SCLK_SEL field. + PCR_I2C_SCLK_CONF_I2C_SCLK_SEL_Pos = 0x14 + // Bit mask of I2C_SCLK_SEL field. + PCR_I2C_SCLK_CONF_I2C_SCLK_SEL_Msk = 0x100000 + // Bit I2C_SCLK_SEL. + PCR_I2C_SCLK_CONF_I2C_SCLK_SEL = 0x100000 + // Position of I2C_SCLK_EN field. + PCR_I2C_SCLK_CONF_I2C_SCLK_EN_Pos = 0x16 + // Bit mask of I2C_SCLK_EN field. + PCR_I2C_SCLK_CONF_I2C_SCLK_EN_Msk = 0x400000 + // Bit I2C_SCLK_EN. + PCR_I2C_SCLK_CONF_I2C_SCLK_EN = 0x400000 + + // UHCI_CONF: UHCI configuration register + // Position of UHCI_CLK_EN field. + PCR_UHCI_CONF_UHCI_CLK_EN_Pos = 0x0 + // Bit mask of UHCI_CLK_EN field. + PCR_UHCI_CONF_UHCI_CLK_EN_Msk = 0x1 + // Bit UHCI_CLK_EN. + PCR_UHCI_CONF_UHCI_CLK_EN = 0x1 + // Position of UHCI_RST_EN field. + PCR_UHCI_CONF_UHCI_RST_EN_Pos = 0x1 + // Bit mask of UHCI_RST_EN field. + PCR_UHCI_CONF_UHCI_RST_EN_Msk = 0x2 + // Bit UHCI_RST_EN. + PCR_UHCI_CONF_UHCI_RST_EN = 0x2 + + // RMT_CONF: RMT configuration register + // Position of RMT_CLK_EN field. + PCR_RMT_CONF_RMT_CLK_EN_Pos = 0x0 + // Bit mask of RMT_CLK_EN field. + PCR_RMT_CONF_RMT_CLK_EN_Msk = 0x1 + // Bit RMT_CLK_EN. + PCR_RMT_CONF_RMT_CLK_EN = 0x1 + // Position of RMT_RST_EN field. + PCR_RMT_CONF_RMT_RST_EN_Pos = 0x1 + // Bit mask of RMT_RST_EN field. + PCR_RMT_CONF_RMT_RST_EN_Msk = 0x2 + // Bit RMT_RST_EN. + PCR_RMT_CONF_RMT_RST_EN = 0x2 + + // RMT_SCLK_CONF: RMT_SCLK configuration register + // Position of SCLK_DIV_A field. + PCR_RMT_SCLK_CONF_SCLK_DIV_A_Pos = 0x0 + // Bit mask of SCLK_DIV_A field. + PCR_RMT_SCLK_CONF_SCLK_DIV_A_Msk = 0x3f + // Position of SCLK_DIV_B field. + PCR_RMT_SCLK_CONF_SCLK_DIV_B_Pos = 0x6 + // Bit mask of SCLK_DIV_B field. + PCR_RMT_SCLK_CONF_SCLK_DIV_B_Msk = 0xfc0 + // Position of SCLK_DIV_NUM field. + PCR_RMT_SCLK_CONF_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of SCLK_DIV_NUM field. + PCR_RMT_SCLK_CONF_SCLK_DIV_NUM_Msk = 0xff000 + // Position of SCLK_SEL field. + PCR_RMT_SCLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + PCR_RMT_SCLK_CONF_SCLK_SEL_Msk = 0x300000 + // Position of SCLK_EN field. + PCR_RMT_SCLK_CONF_SCLK_EN_Pos = 0x16 + // Bit mask of SCLK_EN field. + PCR_RMT_SCLK_CONF_SCLK_EN_Msk = 0x400000 + // Bit SCLK_EN. + PCR_RMT_SCLK_CONF_SCLK_EN = 0x400000 + + // LEDC_CONF: LEDC configuration register + // Position of LEDC_CLK_EN field. + PCR_LEDC_CONF_LEDC_CLK_EN_Pos = 0x0 + // Bit mask of LEDC_CLK_EN field. + PCR_LEDC_CONF_LEDC_CLK_EN_Msk = 0x1 + // Bit LEDC_CLK_EN. + PCR_LEDC_CONF_LEDC_CLK_EN = 0x1 + // Position of LEDC_RST_EN field. + PCR_LEDC_CONF_LEDC_RST_EN_Pos = 0x1 + // Bit mask of LEDC_RST_EN field. + PCR_LEDC_CONF_LEDC_RST_EN_Msk = 0x2 + // Bit LEDC_RST_EN. + PCR_LEDC_CONF_LEDC_RST_EN = 0x2 + + // LEDC_SCLK_CONF: LEDC_SCLK configuration register + // Position of LEDC_SCLK_SEL field. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_SEL_Pos = 0x14 + // Bit mask of LEDC_SCLK_SEL field. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_SEL_Msk = 0x300000 + // Position of LEDC_SCLK_EN field. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_EN_Pos = 0x16 + // Bit mask of LEDC_SCLK_EN field. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_EN_Msk = 0x400000 + // Bit LEDC_SCLK_EN. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_EN = 0x400000 + + // TIMERGROUP0_CONF: TIMERGROUP0 configuration register + // Position of TG0_CLK_EN field. + PCR_TIMERGROUP0_CONF_TG0_CLK_EN_Pos = 0x0 + // Bit mask of TG0_CLK_EN field. + PCR_TIMERGROUP0_CONF_TG0_CLK_EN_Msk = 0x1 + // Bit TG0_CLK_EN. + PCR_TIMERGROUP0_CONF_TG0_CLK_EN = 0x1 + // Position of TG0_RST_EN field. + PCR_TIMERGROUP0_CONF_TG0_RST_EN_Pos = 0x1 + // Bit mask of TG0_RST_EN field. + PCR_TIMERGROUP0_CONF_TG0_RST_EN_Msk = 0x2 + // Bit TG0_RST_EN. + PCR_TIMERGROUP0_CONF_TG0_RST_EN = 0x2 + + // TIMERGROUP0_TIMER_CLK_CONF: TIMERGROUP0_TIMER_CLK configuration register + // Position of TG0_TIMER_CLK_SEL field. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_SEL_Pos = 0x14 + // Bit mask of TG0_TIMER_CLK_SEL field. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_SEL_Msk = 0x300000 + // Position of TG0_TIMER_CLK_EN field. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN_Pos = 0x16 + // Bit mask of TG0_TIMER_CLK_EN field. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN_Msk = 0x400000 + // Bit TG0_TIMER_CLK_EN. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN = 0x400000 + + // TIMERGROUP0_WDT_CLK_CONF: TIMERGROUP0_WDT_CLK configuration register + // Position of TG0_WDT_CLK_SEL field. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_SEL_Pos = 0x14 + // Bit mask of TG0_WDT_CLK_SEL field. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_SEL_Msk = 0x300000 + // Position of TG0_WDT_CLK_EN field. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN_Pos = 0x16 + // Bit mask of TG0_WDT_CLK_EN field. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN_Msk = 0x400000 + // Bit TG0_WDT_CLK_EN. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN = 0x400000 + + // TIMERGROUP1_CONF: TIMERGROUP1 configuration register + // Position of TG1_CLK_EN field. + PCR_TIMERGROUP1_CONF_TG1_CLK_EN_Pos = 0x0 + // Bit mask of TG1_CLK_EN field. + PCR_TIMERGROUP1_CONF_TG1_CLK_EN_Msk = 0x1 + // Bit TG1_CLK_EN. + PCR_TIMERGROUP1_CONF_TG1_CLK_EN = 0x1 + // Position of TG1_RST_EN field. + PCR_TIMERGROUP1_CONF_TG1_RST_EN_Pos = 0x1 + // Bit mask of TG1_RST_EN field. + PCR_TIMERGROUP1_CONF_TG1_RST_EN_Msk = 0x2 + // Bit TG1_RST_EN. + PCR_TIMERGROUP1_CONF_TG1_RST_EN = 0x2 + + // TIMERGROUP1_TIMER_CLK_CONF: TIMERGROUP1_TIMER_CLK configuration register + // Position of TG1_TIMER_CLK_SEL field. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_SEL_Pos = 0x14 + // Bit mask of TG1_TIMER_CLK_SEL field. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_SEL_Msk = 0x300000 + // Position of TG1_TIMER_CLK_EN field. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN_Pos = 0x16 + // Bit mask of TG1_TIMER_CLK_EN field. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN_Msk = 0x400000 + // Bit TG1_TIMER_CLK_EN. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN = 0x400000 + + // TIMERGROUP1_WDT_CLK_CONF: TIMERGROUP1_WDT_CLK configuration register + // Position of TG1_WDT_CLK_SEL field. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_SEL_Pos = 0x14 + // Bit mask of TG1_WDT_CLK_SEL field. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_SEL_Msk = 0x300000 + // Position of TG1_WDT_CLK_EN field. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN_Pos = 0x16 + // Bit mask of TG1_WDT_CLK_EN field. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN_Msk = 0x400000 + // Bit TG1_WDT_CLK_EN. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN = 0x400000 + + // SYSTIMER_CONF: SYSTIMER configuration register + // Position of SYSTIMER_CLK_EN field. + PCR_SYSTIMER_CONF_SYSTIMER_CLK_EN_Pos = 0x0 + // Bit mask of SYSTIMER_CLK_EN field. + PCR_SYSTIMER_CONF_SYSTIMER_CLK_EN_Msk = 0x1 + // Bit SYSTIMER_CLK_EN. + PCR_SYSTIMER_CONF_SYSTIMER_CLK_EN = 0x1 + // Position of SYSTIMER_RST_EN field. + PCR_SYSTIMER_CONF_SYSTIMER_RST_EN_Pos = 0x1 + // Bit mask of SYSTIMER_RST_EN field. + PCR_SYSTIMER_CONF_SYSTIMER_RST_EN_Msk = 0x2 + // Bit SYSTIMER_RST_EN. + PCR_SYSTIMER_CONF_SYSTIMER_RST_EN = 0x2 + + // SYSTIMER_FUNC_CLK_CONF: SYSTIMER_FUNC_CLK configuration register + // Position of SYSTIMER_FUNC_CLK_SEL field. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL_Pos = 0x14 + // Bit mask of SYSTIMER_FUNC_CLK_SEL field. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL_Msk = 0x100000 + // Bit SYSTIMER_FUNC_CLK_SEL. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL = 0x100000 + // Position of SYSTIMER_FUNC_CLK_EN field. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN_Pos = 0x16 + // Bit mask of SYSTIMER_FUNC_CLK_EN field. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN_Msk = 0x400000 + // Bit SYSTIMER_FUNC_CLK_EN. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN = 0x400000 + + // TWAI0_CONF: TWAI0 configuration register + // Position of TWAI0_CLK_EN field. + PCR_TWAI0_CONF_TWAI0_CLK_EN_Pos = 0x0 + // Bit mask of TWAI0_CLK_EN field. + PCR_TWAI0_CONF_TWAI0_CLK_EN_Msk = 0x1 + // Bit TWAI0_CLK_EN. + PCR_TWAI0_CONF_TWAI0_CLK_EN = 0x1 + // Position of TWAI0_RST_EN field. + PCR_TWAI0_CONF_TWAI0_RST_EN_Pos = 0x1 + // Bit mask of TWAI0_RST_EN field. + PCR_TWAI0_CONF_TWAI0_RST_EN_Msk = 0x2 + // Bit TWAI0_RST_EN. + PCR_TWAI0_CONF_TWAI0_RST_EN = 0x2 + + // TWAI0_FUNC_CLK_CONF: TWAI0_FUNC_CLK configuration register + // Position of TWAI0_FUNC_CLK_SEL field. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL_Pos = 0x14 + // Bit mask of TWAI0_FUNC_CLK_SEL field. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL_Msk = 0x100000 + // Bit TWAI0_FUNC_CLK_SEL. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL = 0x100000 + // Position of TWAI0_FUNC_CLK_EN field. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN_Pos = 0x16 + // Bit mask of TWAI0_FUNC_CLK_EN field. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN_Msk = 0x400000 + // Bit TWAI0_FUNC_CLK_EN. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN = 0x400000 + + // TWAI1_CONF: TWAI1 configuration register + // Position of TWAI1_CLK_EN field. + PCR_TWAI1_CONF_TWAI1_CLK_EN_Pos = 0x0 + // Bit mask of TWAI1_CLK_EN field. + PCR_TWAI1_CONF_TWAI1_CLK_EN_Msk = 0x1 + // Bit TWAI1_CLK_EN. + PCR_TWAI1_CONF_TWAI1_CLK_EN = 0x1 + // Position of TWAI1_RST_EN field. + PCR_TWAI1_CONF_TWAI1_RST_EN_Pos = 0x1 + // Bit mask of TWAI1_RST_EN field. + PCR_TWAI1_CONF_TWAI1_RST_EN_Msk = 0x2 + // Bit TWAI1_RST_EN. + PCR_TWAI1_CONF_TWAI1_RST_EN = 0x2 + + // TWAI1_FUNC_CLK_CONF: TWAI1_FUNC_CLK configuration register + // Position of TWAI1_FUNC_CLK_SEL field. + PCR_TWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_SEL_Pos = 0x14 + // Bit mask of TWAI1_FUNC_CLK_SEL field. + PCR_TWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_SEL_Msk = 0x100000 + // Bit TWAI1_FUNC_CLK_SEL. + PCR_TWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_SEL = 0x100000 + // Position of TWAI1_FUNC_CLK_EN field. + PCR_TWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_EN_Pos = 0x16 + // Bit mask of TWAI1_FUNC_CLK_EN field. + PCR_TWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_EN_Msk = 0x400000 + // Bit TWAI1_FUNC_CLK_EN. + PCR_TWAI1_FUNC_CLK_CONF_TWAI1_FUNC_CLK_EN = 0x400000 + + // I2S_CONF: I2S configuration register + // Position of I2S_CLK_EN field. + PCR_I2S_CONF_I2S_CLK_EN_Pos = 0x0 + // Bit mask of I2S_CLK_EN field. + PCR_I2S_CONF_I2S_CLK_EN_Msk = 0x1 + // Bit I2S_CLK_EN. + PCR_I2S_CONF_I2S_CLK_EN = 0x1 + // Position of I2S_RST_EN field. + PCR_I2S_CONF_I2S_RST_EN_Pos = 0x1 + // Bit mask of I2S_RST_EN field. + PCR_I2S_CONF_I2S_RST_EN_Msk = 0x2 + // Bit I2S_RST_EN. + PCR_I2S_CONF_I2S_RST_EN = 0x2 + + // I2S_TX_CLKM_CONF: I2S_TX_CLKM configuration register + // Position of I2S_TX_CLKM_DIV_NUM field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_DIV_NUM_Pos = 0xc + // Bit mask of I2S_TX_CLKM_DIV_NUM field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_DIV_NUM_Msk = 0xff000 + // Position of I2S_TX_CLKM_SEL field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_SEL_Pos = 0x14 + // Bit mask of I2S_TX_CLKM_SEL field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_SEL_Msk = 0x300000 + // Position of I2S_TX_CLKM_EN field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_EN_Pos = 0x16 + // Bit mask of I2S_TX_CLKM_EN field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_EN_Msk = 0x400000 + // Bit I2S_TX_CLKM_EN. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_EN = 0x400000 + + // I2S_TX_CLKM_DIV_CONF: I2S_TX_CLKM_DIV configuration register + // Position of I2S_TX_CLKM_DIV_Z field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of I2S_TX_CLKM_DIV_Z field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Z_Msk = 0x1ff + // Position of I2S_TX_CLKM_DIV_Y field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of I2S_TX_CLKM_DIV_Y field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of I2S_TX_CLKM_DIV_X field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of I2S_TX_CLKM_DIV_X field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of I2S_TX_CLKM_DIV_YN1 field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of I2S_TX_CLKM_DIV_YN1 field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit I2S_TX_CLKM_DIV_YN1. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1 = 0x8000000 + + // I2S_RX_CLKM_CONF: I2S_RX_CLKM configuration register + // Position of I2S_RX_CLKM_DIV_NUM field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_DIV_NUM_Pos = 0xc + // Bit mask of I2S_RX_CLKM_DIV_NUM field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_DIV_NUM_Msk = 0xff000 + // Position of I2S_RX_CLKM_SEL field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_SEL_Pos = 0x14 + // Bit mask of I2S_RX_CLKM_SEL field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_SEL_Msk = 0x300000 + // Position of I2S_RX_CLKM_EN field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_EN_Pos = 0x16 + // Bit mask of I2S_RX_CLKM_EN field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_EN_Msk = 0x400000 + // Bit I2S_RX_CLKM_EN. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_EN = 0x400000 + // Position of I2S_MCLK_SEL field. + PCR_I2S_RX_CLKM_CONF_I2S_MCLK_SEL_Pos = 0x17 + // Bit mask of I2S_MCLK_SEL field. + PCR_I2S_RX_CLKM_CONF_I2S_MCLK_SEL_Msk = 0x800000 + // Bit I2S_MCLK_SEL. + PCR_I2S_RX_CLKM_CONF_I2S_MCLK_SEL = 0x800000 + + // I2S_RX_CLKM_DIV_CONF: I2S_RX_CLKM_DIV configuration register + // Position of I2S_RX_CLKM_DIV_Z field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of I2S_RX_CLKM_DIV_Z field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Z_Msk = 0x1ff + // Position of I2S_RX_CLKM_DIV_Y field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of I2S_RX_CLKM_DIV_Y field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of I2S_RX_CLKM_DIV_X field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of I2S_RX_CLKM_DIV_X field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of I2S_RX_CLKM_DIV_YN1 field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of I2S_RX_CLKM_DIV_YN1 field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit I2S_RX_CLKM_DIV_YN1. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1 = 0x8000000 + + // SARADC_CONF: SARADC configuration register + // Position of SARADC_CLK_EN field. + PCR_SARADC_CONF_SARADC_CLK_EN_Pos = 0x0 + // Bit mask of SARADC_CLK_EN field. + PCR_SARADC_CONF_SARADC_CLK_EN_Msk = 0x1 + // Bit SARADC_CLK_EN. + PCR_SARADC_CONF_SARADC_CLK_EN = 0x1 + // Position of SARADC_RST_EN field. + PCR_SARADC_CONF_SARADC_RST_EN_Pos = 0x1 + // Bit mask of SARADC_RST_EN field. + PCR_SARADC_CONF_SARADC_RST_EN_Msk = 0x2 + // Bit SARADC_RST_EN. + PCR_SARADC_CONF_SARADC_RST_EN = 0x2 + // Position of SARADC_REG_CLK_EN field. + PCR_SARADC_CONF_SARADC_REG_CLK_EN_Pos = 0x2 + // Bit mask of SARADC_REG_CLK_EN field. + PCR_SARADC_CONF_SARADC_REG_CLK_EN_Msk = 0x4 + // Bit SARADC_REG_CLK_EN. + PCR_SARADC_CONF_SARADC_REG_CLK_EN = 0x4 + // Position of SARADC_REG_RST_EN field. + PCR_SARADC_CONF_SARADC_REG_RST_EN_Pos = 0x3 + // Bit mask of SARADC_REG_RST_EN field. + PCR_SARADC_CONF_SARADC_REG_RST_EN_Msk = 0x8 + // Bit SARADC_REG_RST_EN. + PCR_SARADC_CONF_SARADC_REG_RST_EN = 0x8 + + // SARADC_CLKM_CONF: SARADC_CLKM configuration register + // Position of SARADC_CLKM_DIV_A field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_A_Pos = 0x0 + // Bit mask of SARADC_CLKM_DIV_A field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_A_Msk = 0x3f + // Position of SARADC_CLKM_DIV_B field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_B_Pos = 0x6 + // Bit mask of SARADC_CLKM_DIV_B field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_B_Msk = 0xfc0 + // Position of SARADC_CLKM_DIV_NUM field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_NUM_Pos = 0xc + // Bit mask of SARADC_CLKM_DIV_NUM field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_NUM_Msk = 0xff000 + // Position of SARADC_CLKM_SEL field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_SEL_Pos = 0x14 + // Bit mask of SARADC_CLKM_SEL field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_SEL_Msk = 0x300000 + // Position of SARADC_CLKM_EN field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_EN_Pos = 0x16 + // Bit mask of SARADC_CLKM_EN field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_EN_Msk = 0x400000 + // Bit SARADC_CLKM_EN. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_EN = 0x400000 + + // TSENS_CLK_CONF: TSENS_CLK configuration register + // Position of TSENS_CLK_SEL field. + PCR_TSENS_CLK_CONF_TSENS_CLK_SEL_Pos = 0x14 + // Bit mask of TSENS_CLK_SEL field. + PCR_TSENS_CLK_CONF_TSENS_CLK_SEL_Msk = 0x100000 + // Bit TSENS_CLK_SEL. + PCR_TSENS_CLK_CONF_TSENS_CLK_SEL = 0x100000 + // Position of TSENS_CLK_EN field. + PCR_TSENS_CLK_CONF_TSENS_CLK_EN_Pos = 0x16 + // Bit mask of TSENS_CLK_EN field. + PCR_TSENS_CLK_CONF_TSENS_CLK_EN_Msk = 0x400000 + // Bit TSENS_CLK_EN. + PCR_TSENS_CLK_CONF_TSENS_CLK_EN = 0x400000 + // Position of TSENS_RST_EN field. + PCR_TSENS_CLK_CONF_TSENS_RST_EN_Pos = 0x17 + // Bit mask of TSENS_RST_EN field. + PCR_TSENS_CLK_CONF_TSENS_RST_EN_Msk = 0x800000 + // Bit TSENS_RST_EN. + PCR_TSENS_CLK_CONF_TSENS_RST_EN = 0x800000 + + // USB_DEVICE_CONF: USB_DEVICE configuration register + // Position of USB_DEVICE_CLK_EN field. + PCR_USB_DEVICE_CONF_USB_DEVICE_CLK_EN_Pos = 0x0 + // Bit mask of USB_DEVICE_CLK_EN field. + PCR_USB_DEVICE_CONF_USB_DEVICE_CLK_EN_Msk = 0x1 + // Bit USB_DEVICE_CLK_EN. + PCR_USB_DEVICE_CONF_USB_DEVICE_CLK_EN = 0x1 + // Position of USB_DEVICE_RST_EN field. + PCR_USB_DEVICE_CONF_USB_DEVICE_RST_EN_Pos = 0x1 + // Bit mask of USB_DEVICE_RST_EN field. + PCR_USB_DEVICE_CONF_USB_DEVICE_RST_EN_Msk = 0x2 + // Bit USB_DEVICE_RST_EN. + PCR_USB_DEVICE_CONF_USB_DEVICE_RST_EN = 0x2 + + // INTMTX_CONF: INTMTX configuration register + // Position of INTMTX_CLK_EN field. + PCR_INTMTX_CONF_INTMTX_CLK_EN_Pos = 0x0 + // Bit mask of INTMTX_CLK_EN field. + PCR_INTMTX_CONF_INTMTX_CLK_EN_Msk = 0x1 + // Bit INTMTX_CLK_EN. + PCR_INTMTX_CONF_INTMTX_CLK_EN = 0x1 + // Position of INTMTX_RST_EN field. + PCR_INTMTX_CONF_INTMTX_RST_EN_Pos = 0x1 + // Bit mask of INTMTX_RST_EN field. + PCR_INTMTX_CONF_INTMTX_RST_EN_Msk = 0x2 + // Bit INTMTX_RST_EN. + PCR_INTMTX_CONF_INTMTX_RST_EN = 0x2 + + // PCNT_CONF: PCNT configuration register + // Position of PCNT_CLK_EN field. + PCR_PCNT_CONF_PCNT_CLK_EN_Pos = 0x0 + // Bit mask of PCNT_CLK_EN field. + PCR_PCNT_CONF_PCNT_CLK_EN_Msk = 0x1 + // Bit PCNT_CLK_EN. + PCR_PCNT_CONF_PCNT_CLK_EN = 0x1 + // Position of PCNT_RST_EN field. + PCR_PCNT_CONF_PCNT_RST_EN_Pos = 0x1 + // Bit mask of PCNT_RST_EN field. + PCR_PCNT_CONF_PCNT_RST_EN_Msk = 0x2 + // Bit PCNT_RST_EN. + PCR_PCNT_CONF_PCNT_RST_EN = 0x2 + + // ETM_CONF: ETM configuration register + // Position of ETM_CLK_EN field. + PCR_ETM_CONF_ETM_CLK_EN_Pos = 0x0 + // Bit mask of ETM_CLK_EN field. + PCR_ETM_CONF_ETM_CLK_EN_Msk = 0x1 + // Bit ETM_CLK_EN. + PCR_ETM_CONF_ETM_CLK_EN = 0x1 + // Position of ETM_RST_EN field. + PCR_ETM_CONF_ETM_RST_EN_Pos = 0x1 + // Bit mask of ETM_RST_EN field. + PCR_ETM_CONF_ETM_RST_EN_Msk = 0x2 + // Bit ETM_RST_EN. + PCR_ETM_CONF_ETM_RST_EN = 0x2 + + // PWM_CONF: PWM configuration register + // Position of PWM_CLK_EN field. + PCR_PWM_CONF_PWM_CLK_EN_Pos = 0x0 + // Bit mask of PWM_CLK_EN field. + PCR_PWM_CONF_PWM_CLK_EN_Msk = 0x1 + // Bit PWM_CLK_EN. + PCR_PWM_CONF_PWM_CLK_EN = 0x1 + // Position of PWM_RST_EN field. + PCR_PWM_CONF_PWM_RST_EN_Pos = 0x1 + // Bit mask of PWM_RST_EN field. + PCR_PWM_CONF_PWM_RST_EN_Msk = 0x2 + // Bit PWM_RST_EN. + PCR_PWM_CONF_PWM_RST_EN = 0x2 + + // PWM_CLK_CONF: PWM_CLK configuration register + // Position of PWM_DIV_NUM field. + PCR_PWM_CLK_CONF_PWM_DIV_NUM_Pos = 0xc + // Bit mask of PWM_DIV_NUM field. + PCR_PWM_CLK_CONF_PWM_DIV_NUM_Msk = 0xff000 + // Position of PWM_CLKM_SEL field. + PCR_PWM_CLK_CONF_PWM_CLKM_SEL_Pos = 0x14 + // Bit mask of PWM_CLKM_SEL field. + PCR_PWM_CLK_CONF_PWM_CLKM_SEL_Msk = 0x300000 + // Position of PWM_CLKM_EN field. + PCR_PWM_CLK_CONF_PWM_CLKM_EN_Pos = 0x16 + // Bit mask of PWM_CLKM_EN field. + PCR_PWM_CLK_CONF_PWM_CLKM_EN_Msk = 0x400000 + // Bit PWM_CLKM_EN. + PCR_PWM_CLK_CONF_PWM_CLKM_EN = 0x400000 + + // PARL_IO_CONF: PARL_IO configuration register + // Position of PARL_CLK_EN field. + PCR_PARL_IO_CONF_PARL_CLK_EN_Pos = 0x0 + // Bit mask of PARL_CLK_EN field. + PCR_PARL_IO_CONF_PARL_CLK_EN_Msk = 0x1 + // Bit PARL_CLK_EN. + PCR_PARL_IO_CONF_PARL_CLK_EN = 0x1 + // Position of PARL_RST_EN field. + PCR_PARL_IO_CONF_PARL_RST_EN_Pos = 0x1 + // Bit mask of PARL_RST_EN field. + PCR_PARL_IO_CONF_PARL_RST_EN_Msk = 0x2 + // Bit PARL_RST_EN. + PCR_PARL_IO_CONF_PARL_RST_EN = 0x2 + + // PARL_CLK_RX_CONF: PARL_CLK_RX configuration register + // Position of PARL_CLK_RX_DIV_NUM field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_DIV_NUM_Pos = 0x0 + // Bit mask of PARL_CLK_RX_DIV_NUM field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_DIV_NUM_Msk = 0xffff + // Position of PARL_CLK_RX_SEL field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_SEL_Pos = 0x10 + // Bit mask of PARL_CLK_RX_SEL field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_SEL_Msk = 0x30000 + // Position of PARL_CLK_RX_EN field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_EN_Pos = 0x12 + // Bit mask of PARL_CLK_RX_EN field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_EN_Msk = 0x40000 + // Bit PARL_CLK_RX_EN. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_EN = 0x40000 + // Position of PARL_RX_RST_EN field. + PCR_PARL_CLK_RX_CONF_PARL_RX_RST_EN_Pos = 0x13 + // Bit mask of PARL_RX_RST_EN field. + PCR_PARL_CLK_RX_CONF_PARL_RX_RST_EN_Msk = 0x80000 + // Bit PARL_RX_RST_EN. + PCR_PARL_CLK_RX_CONF_PARL_RX_RST_EN = 0x80000 + + // PARL_CLK_TX_CONF: PARL_CLK_TX configuration register + // Position of PARL_CLK_TX_DIV_NUM field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_DIV_NUM_Pos = 0x0 + // Bit mask of PARL_CLK_TX_DIV_NUM field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_DIV_NUM_Msk = 0xffff + // Position of PARL_CLK_TX_SEL field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_SEL_Pos = 0x10 + // Bit mask of PARL_CLK_TX_SEL field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_SEL_Msk = 0x30000 + // Position of PARL_CLK_TX_EN field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_EN_Pos = 0x12 + // Bit mask of PARL_CLK_TX_EN field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_EN_Msk = 0x40000 + // Bit PARL_CLK_TX_EN. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_EN = 0x40000 + // Position of PARL_TX_RST_EN field. + PCR_PARL_CLK_TX_CONF_PARL_TX_RST_EN_Pos = 0x13 + // Bit mask of PARL_TX_RST_EN field. + PCR_PARL_CLK_TX_CONF_PARL_TX_RST_EN_Msk = 0x80000 + // Bit PARL_TX_RST_EN. + PCR_PARL_CLK_TX_CONF_PARL_TX_RST_EN = 0x80000 + + // SDIO_SLAVE_CONF: SDIO_SLAVE configuration register + // Position of SDIO_SLAVE_CLK_EN field. + PCR_SDIO_SLAVE_CONF_SDIO_SLAVE_CLK_EN_Pos = 0x0 + // Bit mask of SDIO_SLAVE_CLK_EN field. + PCR_SDIO_SLAVE_CONF_SDIO_SLAVE_CLK_EN_Msk = 0x1 + // Bit SDIO_SLAVE_CLK_EN. + PCR_SDIO_SLAVE_CONF_SDIO_SLAVE_CLK_EN = 0x1 + // Position of SDIO_SLAVE_RST_EN field. + PCR_SDIO_SLAVE_CONF_SDIO_SLAVE_RST_EN_Pos = 0x1 + // Bit mask of SDIO_SLAVE_RST_EN field. + PCR_SDIO_SLAVE_CONF_SDIO_SLAVE_RST_EN_Msk = 0x2 + // Bit SDIO_SLAVE_RST_EN. + PCR_SDIO_SLAVE_CONF_SDIO_SLAVE_RST_EN = 0x2 + + // PVT_MONITOR_CONF: PVT_MONITOR configuration register + // Position of PVT_MONITOR_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_CLK_EN_Pos = 0x0 + // Bit mask of PVT_MONITOR_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_CLK_EN_Msk = 0x1 + // Bit PVT_MONITOR_CLK_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_CLK_EN = 0x1 + // Position of PVT_MONITOR_RST_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_RST_EN_Pos = 0x1 + // Bit mask of PVT_MONITOR_RST_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_RST_EN_Msk = 0x2 + // Bit PVT_MONITOR_RST_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_RST_EN = 0x2 + // Position of PVT_MONITOR_SITE1_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN_Pos = 0x2 + // Bit mask of PVT_MONITOR_SITE1_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN_Msk = 0x4 + // Bit PVT_MONITOR_SITE1_CLK_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN = 0x4 + // Position of PVT_MONITOR_SITE2_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN_Pos = 0x3 + // Bit mask of PVT_MONITOR_SITE2_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN_Msk = 0x8 + // Bit PVT_MONITOR_SITE2_CLK_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN = 0x8 + // Position of PVT_MONITOR_SITE3_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN_Pos = 0x4 + // Bit mask of PVT_MONITOR_SITE3_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN_Msk = 0x10 + // Bit PVT_MONITOR_SITE3_CLK_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN = 0x10 + + // PVT_MONITOR_FUNC_CLK_CONF: PVT_MONITOR function clock configuration register + // Position of PVT_MONITOR_FUNC_CLK_DIV_NUM field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_DIV_NUM_Pos = 0x0 + // Bit mask of PVT_MONITOR_FUNC_CLK_DIV_NUM field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_DIV_NUM_Msk = 0xf + // Position of PVT_MONITOR_FUNC_CLK_SEL field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL_Pos = 0x14 + // Bit mask of PVT_MONITOR_FUNC_CLK_SEL field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL_Msk = 0x100000 + // Bit PVT_MONITOR_FUNC_CLK_SEL. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL = 0x100000 + // Position of PVT_MONITOR_FUNC_CLK_EN field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN_Pos = 0x16 + // Bit mask of PVT_MONITOR_FUNC_CLK_EN field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN_Msk = 0x400000 + // Bit PVT_MONITOR_FUNC_CLK_EN. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN = 0x400000 + + // GDMA_CONF: GDMA configuration register + // Position of GDMA_CLK_EN field. + PCR_GDMA_CONF_GDMA_CLK_EN_Pos = 0x0 + // Bit mask of GDMA_CLK_EN field. + PCR_GDMA_CONF_GDMA_CLK_EN_Msk = 0x1 + // Bit GDMA_CLK_EN. + PCR_GDMA_CONF_GDMA_CLK_EN = 0x1 + // Position of GDMA_RST_EN field. + PCR_GDMA_CONF_GDMA_RST_EN_Pos = 0x1 + // Bit mask of GDMA_RST_EN field. + PCR_GDMA_CONF_GDMA_RST_EN_Msk = 0x2 + // Bit GDMA_RST_EN. + PCR_GDMA_CONF_GDMA_RST_EN = 0x2 + + // SPI2_CONF: SPI2 configuration register + // Position of SPI2_CLK_EN field. + PCR_SPI2_CONF_SPI2_CLK_EN_Pos = 0x0 + // Bit mask of SPI2_CLK_EN field. + PCR_SPI2_CONF_SPI2_CLK_EN_Msk = 0x1 + // Bit SPI2_CLK_EN. + PCR_SPI2_CONF_SPI2_CLK_EN = 0x1 + // Position of SPI2_RST_EN field. + PCR_SPI2_CONF_SPI2_RST_EN_Pos = 0x1 + // Bit mask of SPI2_RST_EN field. + PCR_SPI2_CONF_SPI2_RST_EN_Msk = 0x2 + // Bit SPI2_RST_EN. + PCR_SPI2_CONF_SPI2_RST_EN = 0x2 + + // SPI2_CLKM_CONF: SPI2_CLKM configuration register + // Position of SPI2_CLKM_SEL field. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_SEL_Pos = 0x14 + // Bit mask of SPI2_CLKM_SEL field. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_SEL_Msk = 0x300000 + // Position of SPI2_CLKM_EN field. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_EN_Pos = 0x16 + // Bit mask of SPI2_CLKM_EN field. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_EN_Msk = 0x400000 + // Bit SPI2_CLKM_EN. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_EN = 0x400000 + + // AES_CONF: AES configuration register + // Position of AES_CLK_EN field. + PCR_AES_CONF_AES_CLK_EN_Pos = 0x0 + // Bit mask of AES_CLK_EN field. + PCR_AES_CONF_AES_CLK_EN_Msk = 0x1 + // Bit AES_CLK_EN. + PCR_AES_CONF_AES_CLK_EN = 0x1 + // Position of AES_RST_EN field. + PCR_AES_CONF_AES_RST_EN_Pos = 0x1 + // Bit mask of AES_RST_EN field. + PCR_AES_CONF_AES_RST_EN_Msk = 0x2 + // Bit AES_RST_EN. + PCR_AES_CONF_AES_RST_EN = 0x2 + + // SHA_CONF: SHA configuration register + // Position of SHA_CLK_EN field. + PCR_SHA_CONF_SHA_CLK_EN_Pos = 0x0 + // Bit mask of SHA_CLK_EN field. + PCR_SHA_CONF_SHA_CLK_EN_Msk = 0x1 + // Bit SHA_CLK_EN. + PCR_SHA_CONF_SHA_CLK_EN = 0x1 + // Position of SHA_RST_EN field. + PCR_SHA_CONF_SHA_RST_EN_Pos = 0x1 + // Bit mask of SHA_RST_EN field. + PCR_SHA_CONF_SHA_RST_EN_Msk = 0x2 + // Bit SHA_RST_EN. + PCR_SHA_CONF_SHA_RST_EN = 0x2 + + // RSA_CONF: RSA configuration register + // Position of RSA_CLK_EN field. + PCR_RSA_CONF_RSA_CLK_EN_Pos = 0x0 + // Bit mask of RSA_CLK_EN field. + PCR_RSA_CONF_RSA_CLK_EN_Msk = 0x1 + // Bit RSA_CLK_EN. + PCR_RSA_CONF_RSA_CLK_EN = 0x1 + // Position of RSA_RST_EN field. + PCR_RSA_CONF_RSA_RST_EN_Pos = 0x1 + // Bit mask of RSA_RST_EN field. + PCR_RSA_CONF_RSA_RST_EN_Msk = 0x2 + // Bit RSA_RST_EN. + PCR_RSA_CONF_RSA_RST_EN = 0x2 + + // RSA_PD_CTRL: RSA power control register + // Position of RSA_MEM_PD field. + PCR_RSA_PD_CTRL_RSA_MEM_PD_Pos = 0x0 + // Bit mask of RSA_MEM_PD field. + PCR_RSA_PD_CTRL_RSA_MEM_PD_Msk = 0x1 + // Bit RSA_MEM_PD. + PCR_RSA_PD_CTRL_RSA_MEM_PD = 0x1 + // Position of RSA_MEM_FORCE_PU field. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of RSA_MEM_FORCE_PU field. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Msk = 0x2 + // Bit RSA_MEM_FORCE_PU. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PU = 0x2 + // Position of RSA_MEM_FORCE_PD field. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of RSA_MEM_FORCE_PD field. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Msk = 0x4 + // Bit RSA_MEM_FORCE_PD. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PD = 0x4 + + // ECC_CONF: ECC configuration register + // Position of ECC_CLK_EN field. + PCR_ECC_CONF_ECC_CLK_EN_Pos = 0x0 + // Bit mask of ECC_CLK_EN field. + PCR_ECC_CONF_ECC_CLK_EN_Msk = 0x1 + // Bit ECC_CLK_EN. + PCR_ECC_CONF_ECC_CLK_EN = 0x1 + // Position of ECC_RST_EN field. + PCR_ECC_CONF_ECC_RST_EN_Pos = 0x1 + // Bit mask of ECC_RST_EN field. + PCR_ECC_CONF_ECC_RST_EN_Msk = 0x2 + // Bit ECC_RST_EN. + PCR_ECC_CONF_ECC_RST_EN = 0x2 + + // ECC_PD_CTRL: ECC power control register + // Position of ECC_MEM_PD field. + PCR_ECC_PD_CTRL_ECC_MEM_PD_Pos = 0x0 + // Bit mask of ECC_MEM_PD field. + PCR_ECC_PD_CTRL_ECC_MEM_PD_Msk = 0x1 + // Bit ECC_MEM_PD. + PCR_ECC_PD_CTRL_ECC_MEM_PD = 0x1 + // Position of ECC_MEM_FORCE_PU field. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of ECC_MEM_FORCE_PU field. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PU_Msk = 0x2 + // Bit ECC_MEM_FORCE_PU. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PU = 0x2 + // Position of ECC_MEM_FORCE_PD field. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of ECC_MEM_FORCE_PD field. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PD_Msk = 0x4 + // Bit ECC_MEM_FORCE_PD. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PD = 0x4 + + // DS_CONF: DS configuration register + // Position of DS_CLK_EN field. + PCR_DS_CONF_DS_CLK_EN_Pos = 0x0 + // Bit mask of DS_CLK_EN field. + PCR_DS_CONF_DS_CLK_EN_Msk = 0x1 + // Bit DS_CLK_EN. + PCR_DS_CONF_DS_CLK_EN = 0x1 + // Position of DS_RST_EN field. + PCR_DS_CONF_DS_RST_EN_Pos = 0x1 + // Bit mask of DS_RST_EN field. + PCR_DS_CONF_DS_RST_EN_Msk = 0x2 + // Bit DS_RST_EN. + PCR_DS_CONF_DS_RST_EN = 0x2 + + // HMAC_CONF: HMAC configuration register + // Position of HMAC_CLK_EN field. + PCR_HMAC_CONF_HMAC_CLK_EN_Pos = 0x0 + // Bit mask of HMAC_CLK_EN field. + PCR_HMAC_CONF_HMAC_CLK_EN_Msk = 0x1 + // Bit HMAC_CLK_EN. + PCR_HMAC_CONF_HMAC_CLK_EN = 0x1 + // Position of HMAC_RST_EN field. + PCR_HMAC_CONF_HMAC_RST_EN_Pos = 0x1 + // Bit mask of HMAC_RST_EN field. + PCR_HMAC_CONF_HMAC_RST_EN_Msk = 0x2 + // Bit HMAC_RST_EN. + PCR_HMAC_CONF_HMAC_RST_EN = 0x2 + + // IOMUX_CONF: IOMUX configuration register + // Position of IOMUX_CLK_EN field. + PCR_IOMUX_CONF_IOMUX_CLK_EN_Pos = 0x0 + // Bit mask of IOMUX_CLK_EN field. + PCR_IOMUX_CONF_IOMUX_CLK_EN_Msk = 0x1 + // Bit IOMUX_CLK_EN. + PCR_IOMUX_CONF_IOMUX_CLK_EN = 0x1 + // Position of IOMUX_RST_EN field. + PCR_IOMUX_CONF_IOMUX_RST_EN_Pos = 0x1 + // Bit mask of IOMUX_RST_EN field. + PCR_IOMUX_CONF_IOMUX_RST_EN_Msk = 0x2 + // Bit IOMUX_RST_EN. + PCR_IOMUX_CONF_IOMUX_RST_EN = 0x2 + + // IOMUX_CLK_CONF: IOMUX_CLK configuration register + // Position of IOMUX_FUNC_CLK_SEL field. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_SEL_Pos = 0x14 + // Bit mask of IOMUX_FUNC_CLK_SEL field. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_SEL_Msk = 0x300000 + // Position of IOMUX_FUNC_CLK_EN field. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN_Pos = 0x16 + // Bit mask of IOMUX_FUNC_CLK_EN field. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN_Msk = 0x400000 + // Bit IOMUX_FUNC_CLK_EN. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN = 0x400000 + + // MEM_MONITOR_CONF: MEM_MONITOR configuration register + // Position of MEM_MONITOR_CLK_EN field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_CLK_EN_Pos = 0x0 + // Bit mask of MEM_MONITOR_CLK_EN field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_CLK_EN_Msk = 0x1 + // Bit MEM_MONITOR_CLK_EN. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_CLK_EN = 0x1 + // Position of MEM_MONITOR_RST_EN field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_RST_EN_Pos = 0x1 + // Bit mask of MEM_MONITOR_RST_EN field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_RST_EN_Msk = 0x2 + // Bit MEM_MONITOR_RST_EN. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_RST_EN = 0x2 + + // REGDMA_CONF: REGDMA configuration register + // Position of REGDMA_CLK_EN field. + PCR_REGDMA_CONF_REGDMA_CLK_EN_Pos = 0x0 + // Bit mask of REGDMA_CLK_EN field. + PCR_REGDMA_CONF_REGDMA_CLK_EN_Msk = 0x1 + // Bit REGDMA_CLK_EN. + PCR_REGDMA_CONF_REGDMA_CLK_EN = 0x1 + // Position of REGDMA_RST_EN field. + PCR_REGDMA_CONF_REGDMA_RST_EN_Pos = 0x1 + // Bit mask of REGDMA_RST_EN field. + PCR_REGDMA_CONF_REGDMA_RST_EN_Msk = 0x2 + // Bit REGDMA_RST_EN. + PCR_REGDMA_CONF_REGDMA_RST_EN = 0x2 + + // RETENTION_CONF: retention configuration register + // Position of RETENTION_CLK_EN field. + PCR_RETENTION_CONF_RETENTION_CLK_EN_Pos = 0x0 + // Bit mask of RETENTION_CLK_EN field. + PCR_RETENTION_CONF_RETENTION_CLK_EN_Msk = 0x1 + // Bit RETENTION_CLK_EN. + PCR_RETENTION_CONF_RETENTION_CLK_EN = 0x1 + // Position of RETENTION_RST_EN field. + PCR_RETENTION_CONF_RETENTION_RST_EN_Pos = 0x1 + // Bit mask of RETENTION_RST_EN field. + PCR_RETENTION_CONF_RETENTION_RST_EN_Msk = 0x2 + // Bit RETENTION_RST_EN. + PCR_RETENTION_CONF_RETENTION_RST_EN = 0x2 + + // TRACE_CONF: TRACE configuration register + // Position of TRACE_CLK_EN field. + PCR_TRACE_CONF_TRACE_CLK_EN_Pos = 0x0 + // Bit mask of TRACE_CLK_EN field. + PCR_TRACE_CONF_TRACE_CLK_EN_Msk = 0x1 + // Bit TRACE_CLK_EN. + PCR_TRACE_CONF_TRACE_CLK_EN = 0x1 + // Position of TRACE_RST_EN field. + PCR_TRACE_CONF_TRACE_RST_EN_Pos = 0x1 + // Bit mask of TRACE_RST_EN field. + PCR_TRACE_CONF_TRACE_RST_EN_Msk = 0x2 + // Bit TRACE_RST_EN. + PCR_TRACE_CONF_TRACE_RST_EN = 0x2 + + // ASSIST_CONF: ASSIST configuration register + // Position of ASSIST_CLK_EN field. + PCR_ASSIST_CONF_ASSIST_CLK_EN_Pos = 0x0 + // Bit mask of ASSIST_CLK_EN field. + PCR_ASSIST_CONF_ASSIST_CLK_EN_Msk = 0x1 + // Bit ASSIST_CLK_EN. + PCR_ASSIST_CONF_ASSIST_CLK_EN = 0x1 + // Position of ASSIST_RST_EN field. + PCR_ASSIST_CONF_ASSIST_RST_EN_Pos = 0x1 + // Bit mask of ASSIST_RST_EN field. + PCR_ASSIST_CONF_ASSIST_RST_EN_Msk = 0x2 + // Bit ASSIST_RST_EN. + PCR_ASSIST_CONF_ASSIST_RST_EN = 0x2 + + // CACHE_CONF: CACHE configuration register + // Position of CACHE_CLK_EN field. + PCR_CACHE_CONF_CACHE_CLK_EN_Pos = 0x0 + // Bit mask of CACHE_CLK_EN field. + PCR_CACHE_CONF_CACHE_CLK_EN_Msk = 0x1 + // Bit CACHE_CLK_EN. + PCR_CACHE_CONF_CACHE_CLK_EN = 0x1 + // Position of CACHE_RST_EN field. + PCR_CACHE_CONF_CACHE_RST_EN_Pos = 0x1 + // Bit mask of CACHE_RST_EN field. + PCR_CACHE_CONF_CACHE_RST_EN_Msk = 0x2 + // Bit CACHE_RST_EN. + PCR_CACHE_CONF_CACHE_RST_EN = 0x2 + + // MODEM_APB_CONF: MODEM_APB configuration register + // Position of MODEM_APB_CLK_EN field. + PCR_MODEM_APB_CONF_MODEM_APB_CLK_EN_Pos = 0x0 + // Bit mask of MODEM_APB_CLK_EN field. + PCR_MODEM_APB_CONF_MODEM_APB_CLK_EN_Msk = 0x1 + // Bit MODEM_APB_CLK_EN. + PCR_MODEM_APB_CONF_MODEM_APB_CLK_EN = 0x1 + // Position of MODEM_RST_EN field. + PCR_MODEM_APB_CONF_MODEM_RST_EN_Pos = 0x1 + // Bit mask of MODEM_RST_EN field. + PCR_MODEM_APB_CONF_MODEM_RST_EN_Msk = 0x2 + // Bit MODEM_RST_EN. + PCR_MODEM_APB_CONF_MODEM_RST_EN = 0x2 + + // TIMEOUT_CONF: TIMEOUT configuration register + // Position of CPU_TIMEOUT_RST_EN field. + PCR_TIMEOUT_CONF_CPU_TIMEOUT_RST_EN_Pos = 0x1 + // Bit mask of CPU_TIMEOUT_RST_EN field. + PCR_TIMEOUT_CONF_CPU_TIMEOUT_RST_EN_Msk = 0x2 + // Bit CPU_TIMEOUT_RST_EN. + PCR_TIMEOUT_CONF_CPU_TIMEOUT_RST_EN = 0x2 + // Position of HP_TIMEOUT_RST_EN field. + PCR_TIMEOUT_CONF_HP_TIMEOUT_RST_EN_Pos = 0x2 + // Bit mask of HP_TIMEOUT_RST_EN field. + PCR_TIMEOUT_CONF_HP_TIMEOUT_RST_EN_Msk = 0x4 + // Bit HP_TIMEOUT_RST_EN. + PCR_TIMEOUT_CONF_HP_TIMEOUT_RST_EN = 0x4 + + // SYSCLK_CONF: SYSCLK configuration register + // Position of LS_DIV_NUM field. + PCR_SYSCLK_CONF_LS_DIV_NUM_Pos = 0x0 + // Bit mask of LS_DIV_NUM field. + PCR_SYSCLK_CONF_LS_DIV_NUM_Msk = 0xff + // Position of HS_DIV_NUM field. + PCR_SYSCLK_CONF_HS_DIV_NUM_Pos = 0x8 + // Bit mask of HS_DIV_NUM field. + PCR_SYSCLK_CONF_HS_DIV_NUM_Msk = 0xff00 + // Position of SOC_CLK_SEL field. + PCR_SYSCLK_CONF_SOC_CLK_SEL_Pos = 0x10 + // Bit mask of SOC_CLK_SEL field. + PCR_SYSCLK_CONF_SOC_CLK_SEL_Msk = 0x30000 + // Position of CLK_XTAL_FREQ field. + PCR_SYSCLK_CONF_CLK_XTAL_FREQ_Pos = 0x18 + // Bit mask of CLK_XTAL_FREQ field. + PCR_SYSCLK_CONF_CLK_XTAL_FREQ_Msk = 0x7f000000 + + // CPU_WAITI_CONF: CPU_WAITI configuration register + // Position of CPUPERIOD_SEL field. + PCR_CPU_WAITI_CONF_CPUPERIOD_SEL_Pos = 0x0 + // Bit mask of CPUPERIOD_SEL field. + PCR_CPU_WAITI_CONF_CPUPERIOD_SEL_Msk = 0x3 + // Position of PLL_FREQ_SEL field. + PCR_CPU_WAITI_CONF_PLL_FREQ_SEL_Pos = 0x2 + // Bit mask of PLL_FREQ_SEL field. + PCR_CPU_WAITI_CONF_PLL_FREQ_SEL_Msk = 0x4 + // Bit PLL_FREQ_SEL. + PCR_CPU_WAITI_CONF_PLL_FREQ_SEL = 0x4 + // Position of CPU_WAIT_MODE_FORCE_ON field. + PCR_CPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON_Pos = 0x3 + // Bit mask of CPU_WAIT_MODE_FORCE_ON field. + PCR_CPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON_Msk = 0x8 + // Bit CPU_WAIT_MODE_FORCE_ON. + PCR_CPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON = 0x8 + // Position of CPU_WAITI_DELAY_NUM field. + PCR_CPU_WAITI_CONF_CPU_WAITI_DELAY_NUM_Pos = 0x4 + // Bit mask of CPU_WAITI_DELAY_NUM field. + PCR_CPU_WAITI_CONF_CPU_WAITI_DELAY_NUM_Msk = 0xf0 + + // CPU_FREQ_CONF: CPU_FREQ configuration register + // Position of CPU_LS_DIV_NUM field. + PCR_CPU_FREQ_CONF_CPU_LS_DIV_NUM_Pos = 0x0 + // Bit mask of CPU_LS_DIV_NUM field. + PCR_CPU_FREQ_CONF_CPU_LS_DIV_NUM_Msk = 0xff + // Position of CPU_HS_DIV_NUM field. + PCR_CPU_FREQ_CONF_CPU_HS_DIV_NUM_Pos = 0x8 + // Bit mask of CPU_HS_DIV_NUM field. + PCR_CPU_FREQ_CONF_CPU_HS_DIV_NUM_Msk = 0xff00 + // Position of CPU_HS_120M_FORCE field. + PCR_CPU_FREQ_CONF_CPU_HS_120M_FORCE_Pos = 0x10 + // Bit mask of CPU_HS_120M_FORCE field. + PCR_CPU_FREQ_CONF_CPU_HS_120M_FORCE_Msk = 0x10000 + // Bit CPU_HS_120M_FORCE. + PCR_CPU_FREQ_CONF_CPU_HS_120M_FORCE = 0x10000 + + // AHB_FREQ_CONF: AHB_FREQ configuration register + // Position of AHB_LS_DIV_NUM field. + PCR_AHB_FREQ_CONF_AHB_LS_DIV_NUM_Pos = 0x0 + // Bit mask of AHB_LS_DIV_NUM field. + PCR_AHB_FREQ_CONF_AHB_LS_DIV_NUM_Msk = 0xff + // Position of AHB_HS_DIV_NUM field. + PCR_AHB_FREQ_CONF_AHB_HS_DIV_NUM_Pos = 0x8 + // Bit mask of AHB_HS_DIV_NUM field. + PCR_AHB_FREQ_CONF_AHB_HS_DIV_NUM_Msk = 0xff00 + + // APB_FREQ_CONF: APB_FREQ configuration register + // Position of APB_DECREASE_DIV_NUM field. + PCR_APB_FREQ_CONF_APB_DECREASE_DIV_NUM_Pos = 0x0 + // Bit mask of APB_DECREASE_DIV_NUM field. + PCR_APB_FREQ_CONF_APB_DECREASE_DIV_NUM_Msk = 0xff + // Position of APB_DIV_NUM field. + PCR_APB_FREQ_CONF_APB_DIV_NUM_Pos = 0x8 + // Bit mask of APB_DIV_NUM field. + PCR_APB_FREQ_CONF_APB_DIV_NUM_Msk = 0xff00 + + // SYSCLK_FREQ_QUERY_0: SYSCLK frequency query 0 register + // Position of FOSC_FREQ field. + PCR_SYSCLK_FREQ_QUERY_0_FOSC_FREQ_Pos = 0x0 + // Bit mask of FOSC_FREQ field. + PCR_SYSCLK_FREQ_QUERY_0_FOSC_FREQ_Msk = 0xff + // Position of PLL_FREQ field. + PCR_SYSCLK_FREQ_QUERY_0_PLL_FREQ_Pos = 0x8 + // Bit mask of PLL_FREQ field. + PCR_SYSCLK_FREQ_QUERY_0_PLL_FREQ_Msk = 0x3ff00 + + // PLL_DIV_CLK_EN: SPLL DIV clock-gating configuration register + // Position of PLL_240M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_240M_CLK_EN_Pos = 0x0 + // Bit mask of PLL_240M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_240M_CLK_EN_Msk = 0x1 + // Bit PLL_240M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_240M_CLK_EN = 0x1 + // Position of PLL_160M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_160M_CLK_EN_Pos = 0x1 + // Bit mask of PLL_160M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_160M_CLK_EN_Msk = 0x2 + // Bit PLL_160M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_160M_CLK_EN = 0x2 + // Position of PLL_120M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_120M_CLK_EN_Pos = 0x2 + // Bit mask of PLL_120M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_120M_CLK_EN_Msk = 0x4 + // Bit PLL_120M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_120M_CLK_EN = 0x4 + // Position of PLL_80M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_80M_CLK_EN_Pos = 0x3 + // Bit mask of PLL_80M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_80M_CLK_EN_Msk = 0x8 + // Bit PLL_80M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_80M_CLK_EN = 0x8 + // Position of PLL_48M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_48M_CLK_EN_Pos = 0x4 + // Bit mask of PLL_48M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_48M_CLK_EN_Msk = 0x10 + // Bit PLL_48M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_48M_CLK_EN = 0x10 + // Position of PLL_40M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_40M_CLK_EN_Pos = 0x5 + // Bit mask of PLL_40M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_40M_CLK_EN_Msk = 0x20 + // Bit PLL_40M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_40M_CLK_EN = 0x20 + // Position of PLL_20M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_20M_CLK_EN_Pos = 0x6 + // Bit mask of PLL_20M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_20M_CLK_EN_Msk = 0x40 + // Bit PLL_20M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_20M_CLK_EN = 0x40 + + // CTRL_CLK_OUT_EN: CLK_OUT_EN configuration register + // Position of CLK20_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK20_OEN_Pos = 0x0 + // Bit mask of CLK20_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK20_OEN_Msk = 0x1 + // Bit CLK20_OEN. + PCR_CTRL_CLK_OUT_EN_CLK20_OEN = 0x1 + // Position of CLK22_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK22_OEN_Pos = 0x1 + // Bit mask of CLK22_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK22_OEN_Msk = 0x2 + // Bit CLK22_OEN. + PCR_CTRL_CLK_OUT_EN_CLK22_OEN = 0x2 + // Position of CLK44_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK44_OEN_Pos = 0x2 + // Bit mask of CLK44_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK44_OEN_Msk = 0x4 + // Bit CLK44_OEN. + PCR_CTRL_CLK_OUT_EN_CLK44_OEN = 0x4 + // Position of CLK_BB_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_BB_OEN_Pos = 0x3 + // Bit mask of CLK_BB_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_BB_OEN_Msk = 0x8 + // Bit CLK_BB_OEN. + PCR_CTRL_CLK_OUT_EN_CLK_BB_OEN = 0x8 + // Position of CLK80_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK80_OEN_Pos = 0x4 + // Bit mask of CLK80_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK80_OEN_Msk = 0x10 + // Bit CLK80_OEN. + PCR_CTRL_CLK_OUT_EN_CLK80_OEN = 0x10 + // Position of CLK160_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK160_OEN_Pos = 0x5 + // Bit mask of CLK160_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK160_OEN_Msk = 0x20 + // Bit CLK160_OEN. + PCR_CTRL_CLK_OUT_EN_CLK160_OEN = 0x20 + // Position of CLK_320M_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_320M_OEN_Pos = 0x6 + // Bit mask of CLK_320M_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_320M_OEN_Msk = 0x40 + // Bit CLK_320M_OEN. + PCR_CTRL_CLK_OUT_EN_CLK_320M_OEN = 0x40 + // Position of CLK_ADC_INF_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Pos = 0x7 + // Bit mask of CLK_ADC_INF_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Msk = 0x80 + // Bit CLK_ADC_INF_OEN. + PCR_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN = 0x80 + // Position of CLK_DAC_CPU_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN_Pos = 0x8 + // Bit mask of CLK_DAC_CPU_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN_Msk = 0x100 + // Bit CLK_DAC_CPU_OEN. + PCR_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN = 0x100 + // Position of CLK40X_BB_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK40X_BB_OEN_Pos = 0x9 + // Bit mask of CLK40X_BB_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK40X_BB_OEN_Msk = 0x200 + // Bit CLK40X_BB_OEN. + PCR_CTRL_CLK_OUT_EN_CLK40X_BB_OEN = 0x200 + // Position of CLK_XTAL_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Pos = 0xa + // Bit mask of CLK_XTAL_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Msk = 0x400 + // Bit CLK_XTAL_OEN. + PCR_CTRL_CLK_OUT_EN_CLK_XTAL_OEN = 0x400 + + // CTRL_TICK_CONF: TICK configuration register + // Position of XTAL_TICK_NUM field. + PCR_CTRL_TICK_CONF_XTAL_TICK_NUM_Pos = 0x0 + // Bit mask of XTAL_TICK_NUM field. + PCR_CTRL_TICK_CONF_XTAL_TICK_NUM_Msk = 0xff + // Position of FOSC_TICK_NUM field. + PCR_CTRL_TICK_CONF_FOSC_TICK_NUM_Pos = 0x8 + // Bit mask of FOSC_TICK_NUM field. + PCR_CTRL_TICK_CONF_FOSC_TICK_NUM_Msk = 0xff00 + // Position of TICK_ENABLE field. + PCR_CTRL_TICK_CONF_TICK_ENABLE_Pos = 0x10 + // Bit mask of TICK_ENABLE field. + PCR_CTRL_TICK_CONF_TICK_ENABLE_Msk = 0x10000 + // Bit TICK_ENABLE. + PCR_CTRL_TICK_CONF_TICK_ENABLE = 0x10000 + // Position of RST_TICK_CNT field. + PCR_CTRL_TICK_CONF_RST_TICK_CNT_Pos = 0x11 + // Bit mask of RST_TICK_CNT field. + PCR_CTRL_TICK_CONF_RST_TICK_CNT_Msk = 0x20000 + // Bit RST_TICK_CNT. + PCR_CTRL_TICK_CONF_RST_TICK_CNT = 0x20000 + + // CTRL_32K_CONF: 32KHz clock configuration register + // Position of CLK_32K_SEL field. + PCR_CTRL_32K_CONF_CLK_32K_SEL_Pos = 0x0 + // Bit mask of CLK_32K_SEL field. + PCR_CTRL_32K_CONF_CLK_32K_SEL_Msk = 0x3 + + // SRAM_POWER_CONF: HP SRAM/ROM configuration register + // Position of SRAM_FORCE_PU field. + PCR_SRAM_POWER_CONF_SRAM_FORCE_PU_Pos = 0x0 + // Bit mask of SRAM_FORCE_PU field. + PCR_SRAM_POWER_CONF_SRAM_FORCE_PU_Msk = 0xf + // Position of SRAM_FORCE_PD field. + PCR_SRAM_POWER_CONF_SRAM_FORCE_PD_Pos = 0x4 + // Bit mask of SRAM_FORCE_PD field. + PCR_SRAM_POWER_CONF_SRAM_FORCE_PD_Msk = 0xf0 + // Position of SRAM_CLKGATE_FORCE_ON field. + PCR_SRAM_POWER_CONF_SRAM_CLKGATE_FORCE_ON_Pos = 0x8 + // Bit mask of SRAM_CLKGATE_FORCE_ON field. + PCR_SRAM_POWER_CONF_SRAM_CLKGATE_FORCE_ON_Msk = 0xf00 + // Position of ROM_FORCE_PU field. + PCR_SRAM_POWER_CONF_ROM_FORCE_PU_Pos = 0xc + // Bit mask of ROM_FORCE_PU field. + PCR_SRAM_POWER_CONF_ROM_FORCE_PU_Msk = 0x7000 + // Position of ROM_FORCE_PD field. + PCR_SRAM_POWER_CONF_ROM_FORCE_PD_Pos = 0xf + // Bit mask of ROM_FORCE_PD field. + PCR_SRAM_POWER_CONF_ROM_FORCE_PD_Msk = 0x38000 + // Position of ROM_CLKGATE_FORCE_ON field. + PCR_SRAM_POWER_CONF_ROM_CLKGATE_FORCE_ON_Pos = 0x12 + // Bit mask of ROM_CLKGATE_FORCE_ON field. + PCR_SRAM_POWER_CONF_ROM_CLKGATE_FORCE_ON_Msk = 0x1c0000 + + // RESET_EVENT_BYPASS: reset event bypass backdoor configuration register + // Position of APM field. + PCR_RESET_EVENT_BYPASS_APM_Pos = 0x0 + // Bit mask of APM field. + PCR_RESET_EVENT_BYPASS_APM_Msk = 0x1 + // Bit APM. + PCR_RESET_EVENT_BYPASS_APM = 0x1 + // Position of RESET_EVENT_BYPASS field. + PCR_RESET_EVENT_BYPASS_RESET_EVENT_BYPASS_Pos = 0x1 + // Bit mask of RESET_EVENT_BYPASS field. + PCR_RESET_EVENT_BYPASS_RESET_EVENT_BYPASS_Msk = 0x2 + // Bit RESET_EVENT_BYPASS. + PCR_RESET_EVENT_BYPASS_RESET_EVENT_BYPASS = 0x2 + + // FPGA_DEBUG: fpga debug register + // Position of FPGA_DEBUG field. + PCR_FPGA_DEBUG_FPGA_DEBUG_Pos = 0x0 + // Bit mask of FPGA_DEBUG field. + PCR_FPGA_DEBUG_FPGA_DEBUG_Msk = 0xffffffff + + // CLOCK_GATE: PCR clock gating configure register + // Position of CLK_EN field. + PCR_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + PCR_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + PCR_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Date register. + // Position of DATE field. + PCR_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PCR_DATE_DATE_Msk = 0xfffffff +) + +// Constants for PMU: PMU Peripheral +const ( + // HP_ACTIVE_DIG_POWER: need_des + // Position of HP_ACTIVE_VDD_SPI_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN_Pos = 0x15 + // Bit mask of HP_ACTIVE_VDD_SPI_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN_Msk = 0x200000 + // Bit HP_ACTIVE_VDD_SPI_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN = 0x200000 + // Position of HP_ACTIVE_HP_MEM_DSLP field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP_Pos = 0x16 + // Bit mask of HP_ACTIVE_HP_MEM_DSLP field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP_Msk = 0x400000 + // Bit HP_ACTIVE_HP_MEM_DSLP. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP = 0x400000 + // Position of HP_ACTIVE_PD_HP_MEM_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN_Pos = 0x17 + // Bit mask of HP_ACTIVE_PD_HP_MEM_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN_Msk = 0x7800000 + // Position of HP_ACTIVE_PD_HP_WIFI_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN_Pos = 0x1b + // Bit mask of HP_ACTIVE_PD_HP_WIFI_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN_Msk = 0x8000000 + // Bit HP_ACTIVE_PD_HP_WIFI_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN = 0x8000000 + // Position of HP_ACTIVE_PD_HP_CPU_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN_Pos = 0x1d + // Bit mask of HP_ACTIVE_PD_HP_CPU_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN_Msk = 0x20000000 + // Bit HP_ACTIVE_PD_HP_CPU_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN = 0x20000000 + // Position of HP_ACTIVE_PD_HP_AON_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN_Pos = 0x1e + // Bit mask of HP_ACTIVE_PD_HP_AON_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN_Msk = 0x40000000 + // Bit HP_ACTIVE_PD_HP_AON_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN = 0x40000000 + // Position of HP_ACTIVE_PD_TOP_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN_Pos = 0x1f + // Bit mask of HP_ACTIVE_PD_TOP_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN_Msk = 0x80000000 + // Bit HP_ACTIVE_PD_TOP_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN = 0x80000000 + + // HP_ACTIVE_ICG_HP_FUNC: need_des + // Position of HP_ACTIVE_DIG_ICG_FUNC_EN field. + PMU_HP_ACTIVE_ICG_HP_FUNC_HP_ACTIVE_DIG_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_ACTIVE_DIG_ICG_FUNC_EN field. + PMU_HP_ACTIVE_ICG_HP_FUNC_HP_ACTIVE_DIG_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_ACTIVE_ICG_HP_APB: need_des + // Position of HP_ACTIVE_DIG_ICG_APB_EN field. + PMU_HP_ACTIVE_ICG_HP_APB_HP_ACTIVE_DIG_ICG_APB_EN_Pos = 0x0 + // Bit mask of HP_ACTIVE_DIG_ICG_APB_EN field. + PMU_HP_ACTIVE_ICG_HP_APB_HP_ACTIVE_DIG_ICG_APB_EN_Msk = 0xffffffff + + // HP_ACTIVE_ICG_MODEM: need_des + // Position of HP_ACTIVE_DIG_ICG_MODEM_CODE field. + PMU_HP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE_Pos = 0x1e + // Bit mask of HP_ACTIVE_DIG_ICG_MODEM_CODE field. + PMU_HP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE_Msk = 0xc0000000 + + // HP_ACTIVE_HP_SYS_CNTL: need_des + // Position of HP_ACTIVE_UART_WAKEUP_EN field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN_Pos = 0x18 + // Bit mask of HP_ACTIVE_UART_WAKEUP_EN field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN_Msk = 0x1000000 + // Bit HP_ACTIVE_UART_WAKEUP_EN. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN = 0x1000000 + // Position of HP_ACTIVE_LP_PAD_HOLD_ALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL_Pos = 0x19 + // Bit mask of HP_ACTIVE_LP_PAD_HOLD_ALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL_Msk = 0x2000000 + // Bit HP_ACTIVE_LP_PAD_HOLD_ALL. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL = 0x2000000 + // Position of HP_ACTIVE_HP_PAD_HOLD_ALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL_Pos = 0x1a + // Bit mask of HP_ACTIVE_HP_PAD_HOLD_ALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL_Msk = 0x4000000 + // Bit HP_ACTIVE_HP_PAD_HOLD_ALL. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL = 0x4000000 + // Position of HP_ACTIVE_DIG_PAD_SLP_SEL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL_Pos = 0x1b + // Bit mask of HP_ACTIVE_DIG_PAD_SLP_SEL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL_Msk = 0x8000000 + // Bit HP_ACTIVE_DIG_PAD_SLP_SEL. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL = 0x8000000 + // Position of HP_ACTIVE_DIG_PAUSE_WDT field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT_Pos = 0x1c + // Bit mask of HP_ACTIVE_DIG_PAUSE_WDT field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT_Msk = 0x10000000 + // Bit HP_ACTIVE_DIG_PAUSE_WDT. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT = 0x10000000 + // Position of HP_ACTIVE_DIG_CPU_STALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL_Pos = 0x1d + // Bit mask of HP_ACTIVE_DIG_CPU_STALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL_Msk = 0x20000000 + // Bit HP_ACTIVE_DIG_CPU_STALL. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL = 0x20000000 + + // HP_ACTIVE_HP_CK_POWER: need_des + // Position of HP_ACTIVE_I2C_ISO_EN field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN_Pos = 0x1a + // Bit mask of HP_ACTIVE_I2C_ISO_EN field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN_Msk = 0x4000000 + // Bit HP_ACTIVE_I2C_ISO_EN. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN = 0x4000000 + // Position of HP_ACTIVE_I2C_RETENTION field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION_Pos = 0x1b + // Bit mask of HP_ACTIVE_I2C_RETENTION field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION_Msk = 0x8000000 + // Bit HP_ACTIVE_I2C_RETENTION. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION = 0x8000000 + // Position of HP_ACTIVE_XPD_BB_I2C field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C_Pos = 0x1c + // Bit mask of HP_ACTIVE_XPD_BB_I2C field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C_Msk = 0x10000000 + // Bit HP_ACTIVE_XPD_BB_I2C. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C = 0x10000000 + // Position of HP_ACTIVE_XPD_BBPLL_I2C field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C_Pos = 0x1d + // Bit mask of HP_ACTIVE_XPD_BBPLL_I2C field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C_Msk = 0x20000000 + // Bit HP_ACTIVE_XPD_BBPLL_I2C. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C = 0x20000000 + // Position of HP_ACTIVE_XPD_BBPLL field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_Pos = 0x1e + // Bit mask of HP_ACTIVE_XPD_BBPLL field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_Msk = 0x40000000 + // Bit HP_ACTIVE_XPD_BBPLL. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL = 0x40000000 + + // HP_ACTIVE_BIAS: need_des + // Position of HP_ACTIVE_XPD_BIAS field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS_Pos = 0x19 + // Bit mask of HP_ACTIVE_XPD_BIAS field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS_Msk = 0x2000000 + // Bit HP_ACTIVE_XPD_BIAS. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS = 0x2000000 + // Position of HP_ACTIVE_DBG_ATTEN field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN_Pos = 0x1a + // Bit mask of HP_ACTIVE_DBG_ATTEN field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN_Msk = 0x3c000000 + // Position of HP_ACTIVE_PD_CUR field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR_Pos = 0x1e + // Bit mask of HP_ACTIVE_PD_CUR field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR_Msk = 0x40000000 + // Bit HP_ACTIVE_PD_CUR. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR = 0x40000000 + // Position of SLEEP field. + PMU_HP_ACTIVE_BIAS_SLEEP_Pos = 0x1f + // Bit mask of SLEEP field. + PMU_HP_ACTIVE_BIAS_SLEEP_Msk = 0x80000000 + // Bit SLEEP. + PMU_HP_ACTIVE_BIAS_SLEEP = 0x80000000 + + // HP_ACTIVE_BACKUP: need_des + // Position of HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_Pos = 0x4 + // Bit mask of HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_Msk = 0x30 + // Position of HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_Pos = 0x6 + // Bit mask of HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_Msk = 0xc0 + // Position of HP_ACTIVE_RETENTION_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE_Pos = 0xa + // Bit mask of HP_ACTIVE_RETENTION_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE_Msk = 0x400 + // Bit HP_ACTIVE_RETENTION_MODE. + PMU_HP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE = 0x400 + // Position of HP_SLEEP2ACTIVE_RETENTION_EN field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN_Pos = 0xb + // Bit mask of HP_SLEEP2ACTIVE_RETENTION_EN field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN_Msk = 0x800 + // Bit HP_SLEEP2ACTIVE_RETENTION_EN. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN = 0x800 + // Position of HP_MODEM2ACTIVE_RETENTION_EN field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN_Pos = 0xc + // Bit mask of HP_MODEM2ACTIVE_RETENTION_EN field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN_Msk = 0x1000 + // Bit HP_MODEM2ACTIVE_RETENTION_EN. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN = 0x1000 + // Position of HP_SLEEP2ACTIVE_BACKUP_CLK_SEL field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_Pos = 0xe + // Bit mask of HP_SLEEP2ACTIVE_BACKUP_CLK_SEL field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_Msk = 0xc000 + // Position of HP_MODEM2ACTIVE_BACKUP_CLK_SEL field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_Pos = 0x10 + // Bit mask of HP_MODEM2ACTIVE_BACKUP_CLK_SEL field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_Msk = 0x30000 + // Position of HP_SLEEP2ACTIVE_BACKUP_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE_Pos = 0x14 + // Bit mask of HP_SLEEP2ACTIVE_BACKUP_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE_Msk = 0x700000 + // Position of HP_MODEM2ACTIVE_BACKUP_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE_Pos = 0x17 + // Bit mask of HP_MODEM2ACTIVE_BACKUP_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE_Msk = 0x3800000 + // Position of HP_SLEEP2ACTIVE_BACKUP_EN field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN_Pos = 0x1d + // Bit mask of HP_SLEEP2ACTIVE_BACKUP_EN field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN_Msk = 0x20000000 + // Bit HP_SLEEP2ACTIVE_BACKUP_EN. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN = 0x20000000 + // Position of HP_MODEM2ACTIVE_BACKUP_EN field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN_Pos = 0x1e + // Bit mask of HP_MODEM2ACTIVE_BACKUP_EN field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN_Msk = 0x40000000 + // Bit HP_MODEM2ACTIVE_BACKUP_EN. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN = 0x40000000 + + // HP_ACTIVE_BACKUP_CLK: need_des + // Position of HP_ACTIVE_BACKUP_ICG_FUNC_EN field. + PMU_HP_ACTIVE_BACKUP_CLK_HP_ACTIVE_BACKUP_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_ACTIVE_BACKUP_ICG_FUNC_EN field. + PMU_HP_ACTIVE_BACKUP_CLK_HP_ACTIVE_BACKUP_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_ACTIVE_SYSCLK: need_des + // Position of HP_ACTIVE_DIG_SYS_CLK_NO_DIV field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_Pos = 0x1a + // Bit mask of HP_ACTIVE_DIG_SYS_CLK_NO_DIV field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_Msk = 0x4000000 + // Bit HP_ACTIVE_DIG_SYS_CLK_NO_DIV. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV = 0x4000000 + // Position of HP_ACTIVE_ICG_SYS_CLOCK_EN field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN_Pos = 0x1b + // Bit mask of HP_ACTIVE_ICG_SYS_CLOCK_EN field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN_Msk = 0x8000000 + // Bit HP_ACTIVE_ICG_SYS_CLOCK_EN. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN = 0x8000000 + // Position of HP_ACTIVE_SYS_CLK_SLP_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL_Pos = 0x1c + // Bit mask of HP_ACTIVE_SYS_CLK_SLP_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL_Msk = 0x10000000 + // Bit HP_ACTIVE_SYS_CLK_SLP_SEL. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL = 0x10000000 + // Position of HP_ACTIVE_ICG_SLP_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL_Pos = 0x1d + // Bit mask of HP_ACTIVE_ICG_SLP_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL_Msk = 0x20000000 + // Bit HP_ACTIVE_ICG_SLP_SEL. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL = 0x20000000 + // Position of HP_ACTIVE_DIG_SYS_CLK_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL_Pos = 0x1e + // Bit mask of HP_ACTIVE_DIG_SYS_CLK_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL_Msk = 0xc0000000 + + // HP_ACTIVE_HP_REGULATOR0: need_des + // Position of LP_DBIAS_VOL field. + PMU_HP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL_Pos = 0x4 + // Bit mask of LP_DBIAS_VOL field. + PMU_HP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL_Msk = 0x1f0 + // Position of HP_DBIAS_VOL field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL_Pos = 0x9 + // Bit mask of HP_DBIAS_VOL field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL_Msk = 0x3e00 + // Position of DIG_REGULATOR0_DBIAS_SEL field. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL_Pos = 0xe + // Bit mask of DIG_REGULATOR0_DBIAS_SEL field. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL_Msk = 0x4000 + // Bit DIG_REGULATOR0_DBIAS_SEL. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL = 0x4000 + // Position of DIG_DBIAS_INIT field. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT_Pos = 0xf + // Bit mask of DIG_DBIAS_INIT field. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT_Msk = 0x8000 + // Bit DIG_DBIAS_INIT. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT = 0x8000 + // Position of HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_Pos = 0x10 + // Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_Msk = 0x10000 + // Bit HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD = 0x10000 + // Position of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_Pos = 0x11 + // Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_Msk = 0x20000 + // Bit HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD = 0x20000 + // Position of HP_ACTIVE_HP_REGULATOR_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD_Pos = 0x12 + // Bit mask of HP_ACTIVE_HP_REGULATOR_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD_Msk = 0x40000 + // Bit HP_ACTIVE_HP_REGULATOR_XPD. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD = 0x40000 + // Position of HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_Pos = 0x13 + // Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_Msk = 0x780000 + // Position of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_Pos = 0x17 + // Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_Msk = 0x7800000 + // Position of HP_ACTIVE_HP_REGULATOR_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of HP_ACTIVE_HP_REGULATOR_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // HP_ACTIVE_HP_REGULATOR1: need_des + // Position of HP_ACTIVE_HP_REGULATOR_DRV_B field. + PMU_HP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B_Pos = 0x8 + // Bit mask of HP_ACTIVE_HP_REGULATOR_DRV_B field. + PMU_HP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B_Msk = 0xffffff00 + + // HP_ACTIVE_XTAL: need_des + // Position of HP_ACTIVE_XPD_XTAL field. + PMU_HP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL_Pos = 0x1f + // Bit mask of HP_ACTIVE_XPD_XTAL field. + PMU_HP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL_Msk = 0x80000000 + // Bit HP_ACTIVE_XPD_XTAL. + PMU_HP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL = 0x80000000 + + // HP_MODEM_DIG_POWER: need_des + // Position of HP_MODEM_VDD_SPI_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN_Pos = 0x15 + // Bit mask of HP_MODEM_VDD_SPI_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN_Msk = 0x200000 + // Bit HP_MODEM_VDD_SPI_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN = 0x200000 + // Position of HP_MODEM_HP_MEM_DSLP field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP_Pos = 0x16 + // Bit mask of HP_MODEM_HP_MEM_DSLP field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP_Msk = 0x400000 + // Bit HP_MODEM_HP_MEM_DSLP. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP = 0x400000 + // Position of HP_MODEM_PD_HP_MEM_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN_Pos = 0x17 + // Bit mask of HP_MODEM_PD_HP_MEM_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN_Msk = 0x7800000 + // Position of HP_MODEM_PD_HP_WIFI_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN_Pos = 0x1b + // Bit mask of HP_MODEM_PD_HP_WIFI_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN_Msk = 0x8000000 + // Bit HP_MODEM_PD_HP_WIFI_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN = 0x8000000 + // Position of HP_MODEM_PD_HP_CPU_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN_Pos = 0x1d + // Bit mask of HP_MODEM_PD_HP_CPU_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN_Msk = 0x20000000 + // Bit HP_MODEM_PD_HP_CPU_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN = 0x20000000 + // Position of HP_MODEM_PD_HP_AON_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN_Pos = 0x1e + // Bit mask of HP_MODEM_PD_HP_AON_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN_Msk = 0x40000000 + // Bit HP_MODEM_PD_HP_AON_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN = 0x40000000 + // Position of HP_MODEM_PD_TOP_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN_Pos = 0x1f + // Bit mask of HP_MODEM_PD_TOP_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN_Msk = 0x80000000 + // Bit HP_MODEM_PD_TOP_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN = 0x80000000 + + // HP_MODEM_ICG_HP_FUNC: need_des + // Position of HP_MODEM_DIG_ICG_FUNC_EN field. + PMU_HP_MODEM_ICG_HP_FUNC_HP_MODEM_DIG_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_MODEM_DIG_ICG_FUNC_EN field. + PMU_HP_MODEM_ICG_HP_FUNC_HP_MODEM_DIG_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_MODEM_ICG_HP_APB: need_des + // Position of HP_MODEM_DIG_ICG_APB_EN field. + PMU_HP_MODEM_ICG_HP_APB_HP_MODEM_DIG_ICG_APB_EN_Pos = 0x0 + // Bit mask of HP_MODEM_DIG_ICG_APB_EN field. + PMU_HP_MODEM_ICG_HP_APB_HP_MODEM_DIG_ICG_APB_EN_Msk = 0xffffffff + + // HP_MODEM_ICG_MODEM: need_des + // Position of HP_MODEM_DIG_ICG_MODEM_CODE field. + PMU_HP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE_Pos = 0x1e + // Bit mask of HP_MODEM_DIG_ICG_MODEM_CODE field. + PMU_HP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE_Msk = 0xc0000000 + + // HP_MODEM_HP_SYS_CNTL: need_des + // Position of HP_MODEM_UART_WAKEUP_EN field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN_Pos = 0x18 + // Bit mask of HP_MODEM_UART_WAKEUP_EN field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN_Msk = 0x1000000 + // Bit HP_MODEM_UART_WAKEUP_EN. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN = 0x1000000 + // Position of HP_MODEM_LP_PAD_HOLD_ALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL_Pos = 0x19 + // Bit mask of HP_MODEM_LP_PAD_HOLD_ALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL_Msk = 0x2000000 + // Bit HP_MODEM_LP_PAD_HOLD_ALL. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL = 0x2000000 + // Position of HP_MODEM_HP_PAD_HOLD_ALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL_Pos = 0x1a + // Bit mask of HP_MODEM_HP_PAD_HOLD_ALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL_Msk = 0x4000000 + // Bit HP_MODEM_HP_PAD_HOLD_ALL. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL = 0x4000000 + // Position of HP_MODEM_DIG_PAD_SLP_SEL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL_Pos = 0x1b + // Bit mask of HP_MODEM_DIG_PAD_SLP_SEL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL_Msk = 0x8000000 + // Bit HP_MODEM_DIG_PAD_SLP_SEL. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL = 0x8000000 + // Position of HP_MODEM_DIG_PAUSE_WDT field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT_Pos = 0x1c + // Bit mask of HP_MODEM_DIG_PAUSE_WDT field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT_Msk = 0x10000000 + // Bit HP_MODEM_DIG_PAUSE_WDT. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT = 0x10000000 + // Position of HP_MODEM_DIG_CPU_STALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL_Pos = 0x1d + // Bit mask of HP_MODEM_DIG_CPU_STALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL_Msk = 0x20000000 + // Bit HP_MODEM_DIG_CPU_STALL. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL = 0x20000000 + + // HP_MODEM_HP_CK_POWER: need_des + // Position of HP_MODEM_I2C_ISO_EN field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN_Pos = 0x1a + // Bit mask of HP_MODEM_I2C_ISO_EN field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN_Msk = 0x4000000 + // Bit HP_MODEM_I2C_ISO_EN. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN = 0x4000000 + // Position of HP_MODEM_I2C_RETENTION field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION_Pos = 0x1b + // Bit mask of HP_MODEM_I2C_RETENTION field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION_Msk = 0x8000000 + // Bit HP_MODEM_I2C_RETENTION. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION = 0x8000000 + // Position of HP_MODEM_XPD_BB_I2C field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C_Pos = 0x1c + // Bit mask of HP_MODEM_XPD_BB_I2C field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C_Msk = 0x10000000 + // Bit HP_MODEM_XPD_BB_I2C. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C = 0x10000000 + // Position of HP_MODEM_XPD_BBPLL_I2C field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C_Pos = 0x1d + // Bit mask of HP_MODEM_XPD_BBPLL_I2C field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C_Msk = 0x20000000 + // Bit HP_MODEM_XPD_BBPLL_I2C. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C = 0x20000000 + // Position of HP_MODEM_XPD_BBPLL field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_Pos = 0x1e + // Bit mask of HP_MODEM_XPD_BBPLL field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_Msk = 0x40000000 + // Bit HP_MODEM_XPD_BBPLL. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL = 0x40000000 + + // HP_MODEM_BIAS: need_des + // Position of HP_MODEM_XPD_BIAS field. + PMU_HP_MODEM_BIAS_HP_MODEM_XPD_BIAS_Pos = 0x19 + // Bit mask of HP_MODEM_XPD_BIAS field. + PMU_HP_MODEM_BIAS_HP_MODEM_XPD_BIAS_Msk = 0x2000000 + // Bit HP_MODEM_XPD_BIAS. + PMU_HP_MODEM_BIAS_HP_MODEM_XPD_BIAS = 0x2000000 + // Position of HP_MODEM_DBG_ATTEN field. + PMU_HP_MODEM_BIAS_HP_MODEM_DBG_ATTEN_Pos = 0x1a + // Bit mask of HP_MODEM_DBG_ATTEN field. + PMU_HP_MODEM_BIAS_HP_MODEM_DBG_ATTEN_Msk = 0x3c000000 + // Position of HP_MODEM_PD_CUR field. + PMU_HP_MODEM_BIAS_HP_MODEM_PD_CUR_Pos = 0x1e + // Bit mask of HP_MODEM_PD_CUR field. + PMU_HP_MODEM_BIAS_HP_MODEM_PD_CUR_Msk = 0x40000000 + // Bit HP_MODEM_PD_CUR. + PMU_HP_MODEM_BIAS_HP_MODEM_PD_CUR = 0x40000000 + // Position of SLEEP field. + PMU_HP_MODEM_BIAS_SLEEP_Pos = 0x1f + // Bit mask of SLEEP field. + PMU_HP_MODEM_BIAS_SLEEP_Msk = 0x80000000 + // Bit SLEEP. + PMU_HP_MODEM_BIAS_SLEEP = 0x80000000 + + // HP_MODEM_BACKUP: need_des + // Position of HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_Pos = 0x4 + // Bit mask of HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_Msk = 0x30 + // Position of HP_MODEM_RETENTION_MODE field. + PMU_HP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE_Pos = 0xa + // Bit mask of HP_MODEM_RETENTION_MODE field. + PMU_HP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE_Msk = 0x400 + // Bit HP_MODEM_RETENTION_MODE. + PMU_HP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE = 0x400 + // Position of HP_SLEEP2MODEM_RETENTION_EN field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN_Pos = 0xb + // Bit mask of HP_SLEEP2MODEM_RETENTION_EN field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN_Msk = 0x800 + // Bit HP_SLEEP2MODEM_RETENTION_EN. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN = 0x800 + // Position of HP_SLEEP2MODEM_BACKUP_CLK_SEL field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL_Pos = 0xe + // Bit mask of HP_SLEEP2MODEM_BACKUP_CLK_SEL field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL_Msk = 0xc000 + // Position of HP_SLEEP2MODEM_BACKUP_MODE field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE_Pos = 0x14 + // Bit mask of HP_SLEEP2MODEM_BACKUP_MODE field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE_Msk = 0x700000 + // Position of HP_SLEEP2MODEM_BACKUP_EN field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN_Pos = 0x1d + // Bit mask of HP_SLEEP2MODEM_BACKUP_EN field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN_Msk = 0x20000000 + // Bit HP_SLEEP2MODEM_BACKUP_EN. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN = 0x20000000 + + // HP_MODEM_BACKUP_CLK: need_des + // Position of HP_MODEM_BACKUP_ICG_FUNC_EN field. + PMU_HP_MODEM_BACKUP_CLK_HP_MODEM_BACKUP_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_MODEM_BACKUP_ICG_FUNC_EN field. + PMU_HP_MODEM_BACKUP_CLK_HP_MODEM_BACKUP_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_MODEM_SYSCLK: need_des + // Position of HP_MODEM_DIG_SYS_CLK_NO_DIV field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV_Pos = 0x1a + // Bit mask of HP_MODEM_DIG_SYS_CLK_NO_DIV field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV_Msk = 0x4000000 + // Bit HP_MODEM_DIG_SYS_CLK_NO_DIV. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV = 0x4000000 + // Position of HP_MODEM_ICG_SYS_CLOCK_EN field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN_Pos = 0x1b + // Bit mask of HP_MODEM_ICG_SYS_CLOCK_EN field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN_Msk = 0x8000000 + // Bit HP_MODEM_ICG_SYS_CLOCK_EN. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN = 0x8000000 + // Position of HP_MODEM_SYS_CLK_SLP_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL_Pos = 0x1c + // Bit mask of HP_MODEM_SYS_CLK_SLP_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL_Msk = 0x10000000 + // Bit HP_MODEM_SYS_CLK_SLP_SEL. + PMU_HP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL = 0x10000000 + // Position of HP_MODEM_ICG_SLP_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL_Pos = 0x1d + // Bit mask of HP_MODEM_ICG_SLP_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL_Msk = 0x20000000 + // Bit HP_MODEM_ICG_SLP_SEL. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL = 0x20000000 + // Position of HP_MODEM_DIG_SYS_CLK_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL_Pos = 0x1e + // Bit mask of HP_MODEM_DIG_SYS_CLK_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL_Msk = 0xc0000000 + + // HP_MODEM_HP_REGULATOR0: need_des + // Position of HP_MODEM_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_Pos = 0x10 + // Bit mask of HP_MODEM_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_Msk = 0x10000 + // Bit HP_MODEM_HP_REGULATOR_SLP_MEM_XPD. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD = 0x10000 + // Position of HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_Pos = 0x11 + // Bit mask of HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_Msk = 0x20000 + // Bit HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD = 0x20000 + // Position of HP_MODEM_HP_REGULATOR_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD_Pos = 0x12 + // Bit mask of HP_MODEM_HP_REGULATOR_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD_Msk = 0x40000 + // Bit HP_MODEM_HP_REGULATOR_XPD. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD = 0x40000 + // Position of HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_Pos = 0x13 + // Bit mask of HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_Msk = 0x780000 + // Position of HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_Pos = 0x17 + // Bit mask of HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_Msk = 0x7800000 + // Position of HP_MODEM_HP_REGULATOR_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of HP_MODEM_HP_REGULATOR_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // HP_MODEM_HP_REGULATOR1: need_des + // Position of HP_MODEM_HP_REGULATOR_DRV_B field. + PMU_HP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B_Pos = 0x8 + // Bit mask of HP_MODEM_HP_REGULATOR_DRV_B field. + PMU_HP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B_Msk = 0xffffff00 + + // HP_MODEM_XTAL: need_des + // Position of HP_MODEM_XPD_XTAL field. + PMU_HP_MODEM_XTAL_HP_MODEM_XPD_XTAL_Pos = 0x1f + // Bit mask of HP_MODEM_XPD_XTAL field. + PMU_HP_MODEM_XTAL_HP_MODEM_XPD_XTAL_Msk = 0x80000000 + // Bit HP_MODEM_XPD_XTAL. + PMU_HP_MODEM_XTAL_HP_MODEM_XPD_XTAL = 0x80000000 + + // HP_SLEEP_DIG_POWER: need_des + // Position of HP_SLEEP_VDD_SPI_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN_Pos = 0x15 + // Bit mask of HP_SLEEP_VDD_SPI_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN_Msk = 0x200000 + // Bit HP_SLEEP_VDD_SPI_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN = 0x200000 + // Position of HP_SLEEP_HP_MEM_DSLP field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP_Pos = 0x16 + // Bit mask of HP_SLEEP_HP_MEM_DSLP field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP_Msk = 0x400000 + // Bit HP_SLEEP_HP_MEM_DSLP. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP = 0x400000 + // Position of HP_SLEEP_PD_HP_MEM_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN_Pos = 0x17 + // Bit mask of HP_SLEEP_PD_HP_MEM_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN_Msk = 0x7800000 + // Position of HP_SLEEP_PD_HP_WIFI_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN_Pos = 0x1b + // Bit mask of HP_SLEEP_PD_HP_WIFI_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN_Msk = 0x8000000 + // Bit HP_SLEEP_PD_HP_WIFI_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN = 0x8000000 + // Position of HP_SLEEP_PD_HP_CPU_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN_Pos = 0x1d + // Bit mask of HP_SLEEP_PD_HP_CPU_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN_Msk = 0x20000000 + // Bit HP_SLEEP_PD_HP_CPU_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN = 0x20000000 + // Position of HP_SLEEP_PD_HP_AON_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN_Pos = 0x1e + // Bit mask of HP_SLEEP_PD_HP_AON_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN_Msk = 0x40000000 + // Bit HP_SLEEP_PD_HP_AON_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN = 0x40000000 + // Position of HP_SLEEP_PD_TOP_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN_Pos = 0x1f + // Bit mask of HP_SLEEP_PD_TOP_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN_Msk = 0x80000000 + // Bit HP_SLEEP_PD_TOP_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN = 0x80000000 + + // HP_SLEEP_ICG_HP_FUNC: need_des + // Position of HP_SLEEP_DIG_ICG_FUNC_EN field. + PMU_HP_SLEEP_ICG_HP_FUNC_HP_SLEEP_DIG_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_SLEEP_DIG_ICG_FUNC_EN field. + PMU_HP_SLEEP_ICG_HP_FUNC_HP_SLEEP_DIG_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_SLEEP_ICG_HP_APB: need_des + // Position of HP_SLEEP_DIG_ICG_APB_EN field. + PMU_HP_SLEEP_ICG_HP_APB_HP_SLEEP_DIG_ICG_APB_EN_Pos = 0x0 + // Bit mask of HP_SLEEP_DIG_ICG_APB_EN field. + PMU_HP_SLEEP_ICG_HP_APB_HP_SLEEP_DIG_ICG_APB_EN_Msk = 0xffffffff + + // HP_SLEEP_ICG_MODEM: need_des + // Position of HP_SLEEP_DIG_ICG_MODEM_CODE field. + PMU_HP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE_Pos = 0x1e + // Bit mask of HP_SLEEP_DIG_ICG_MODEM_CODE field. + PMU_HP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE_Msk = 0xc0000000 + + // HP_SLEEP_HP_SYS_CNTL: need_des + // Position of HP_SLEEP_UART_WAKEUP_EN field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN_Pos = 0x18 + // Bit mask of HP_SLEEP_UART_WAKEUP_EN field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN_Msk = 0x1000000 + // Bit HP_SLEEP_UART_WAKEUP_EN. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN = 0x1000000 + // Position of HP_SLEEP_LP_PAD_HOLD_ALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL_Pos = 0x19 + // Bit mask of HP_SLEEP_LP_PAD_HOLD_ALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL_Msk = 0x2000000 + // Bit HP_SLEEP_LP_PAD_HOLD_ALL. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL = 0x2000000 + // Position of HP_SLEEP_HP_PAD_HOLD_ALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL_Pos = 0x1a + // Bit mask of HP_SLEEP_HP_PAD_HOLD_ALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL_Msk = 0x4000000 + // Bit HP_SLEEP_HP_PAD_HOLD_ALL. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL = 0x4000000 + // Position of HP_SLEEP_DIG_PAD_SLP_SEL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL_Pos = 0x1b + // Bit mask of HP_SLEEP_DIG_PAD_SLP_SEL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL_Msk = 0x8000000 + // Bit HP_SLEEP_DIG_PAD_SLP_SEL. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL = 0x8000000 + // Position of HP_SLEEP_DIG_PAUSE_WDT field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT_Pos = 0x1c + // Bit mask of HP_SLEEP_DIG_PAUSE_WDT field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT_Msk = 0x10000000 + // Bit HP_SLEEP_DIG_PAUSE_WDT. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT = 0x10000000 + // Position of HP_SLEEP_DIG_CPU_STALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL_Pos = 0x1d + // Bit mask of HP_SLEEP_DIG_CPU_STALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL_Msk = 0x20000000 + // Bit HP_SLEEP_DIG_CPU_STALL. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL = 0x20000000 + + // HP_SLEEP_HP_CK_POWER: need_des + // Position of HP_SLEEP_I2C_ISO_EN field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN_Pos = 0x1a + // Bit mask of HP_SLEEP_I2C_ISO_EN field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN_Msk = 0x4000000 + // Bit HP_SLEEP_I2C_ISO_EN. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN = 0x4000000 + // Position of HP_SLEEP_I2C_RETENTION field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION_Pos = 0x1b + // Bit mask of HP_SLEEP_I2C_RETENTION field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION_Msk = 0x8000000 + // Bit HP_SLEEP_I2C_RETENTION. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION = 0x8000000 + // Position of HP_SLEEP_XPD_BB_I2C field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C_Pos = 0x1c + // Bit mask of HP_SLEEP_XPD_BB_I2C field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C_Msk = 0x10000000 + // Bit HP_SLEEP_XPD_BB_I2C. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C = 0x10000000 + // Position of HP_SLEEP_XPD_BBPLL_I2C field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C_Pos = 0x1d + // Bit mask of HP_SLEEP_XPD_BBPLL_I2C field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C_Msk = 0x20000000 + // Bit HP_SLEEP_XPD_BBPLL_I2C. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C = 0x20000000 + // Position of HP_SLEEP_XPD_BBPLL field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_Pos = 0x1e + // Bit mask of HP_SLEEP_XPD_BBPLL field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_Msk = 0x40000000 + // Bit HP_SLEEP_XPD_BBPLL. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL = 0x40000000 + + // HP_SLEEP_BIAS: need_des + // Position of HP_SLEEP_XPD_BIAS field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS_Pos = 0x19 + // Bit mask of HP_SLEEP_XPD_BIAS field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS_Msk = 0x2000000 + // Bit HP_SLEEP_XPD_BIAS. + PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS = 0x2000000 + // Position of HP_SLEEP_DBG_ATTEN field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN_Pos = 0x1a + // Bit mask of HP_SLEEP_DBG_ATTEN field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN_Msk = 0x3c000000 + // Position of HP_SLEEP_PD_CUR field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_PD_CUR_Pos = 0x1e + // Bit mask of HP_SLEEP_PD_CUR field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_PD_CUR_Msk = 0x40000000 + // Bit HP_SLEEP_PD_CUR. + PMU_HP_SLEEP_BIAS_HP_SLEEP_PD_CUR = 0x40000000 + // Position of SLEEP field. + PMU_HP_SLEEP_BIAS_SLEEP_Pos = 0x1f + // Bit mask of SLEEP field. + PMU_HP_SLEEP_BIAS_SLEEP_Msk = 0x80000000 + // Bit SLEEP. + PMU_HP_SLEEP_BIAS_SLEEP = 0x80000000 + + // HP_SLEEP_BACKUP: need_des + // Position of HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_Pos = 0x6 + // Bit mask of HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_Msk = 0xc0 + // Position of HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_Pos = 0x8 + // Bit mask of HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_Msk = 0x300 + // Position of HP_SLEEP_RETENTION_MODE field. + PMU_HP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE_Pos = 0xa + // Bit mask of HP_SLEEP_RETENTION_MODE field. + PMU_HP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE_Msk = 0x400 + // Bit HP_SLEEP_RETENTION_MODE. + PMU_HP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE = 0x400 + // Position of HP_MODEM2SLEEP_RETENTION_EN field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN_Pos = 0xc + // Bit mask of HP_MODEM2SLEEP_RETENTION_EN field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN_Msk = 0x1000 + // Bit HP_MODEM2SLEEP_RETENTION_EN. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN = 0x1000 + // Position of HP_ACTIVE2SLEEP_RETENTION_EN field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN_Pos = 0xd + // Bit mask of HP_ACTIVE2SLEEP_RETENTION_EN field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN_Msk = 0x2000 + // Bit HP_ACTIVE2SLEEP_RETENTION_EN. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN = 0x2000 + // Position of HP_MODEM2SLEEP_BACKUP_CLK_SEL field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL_Pos = 0x10 + // Bit mask of HP_MODEM2SLEEP_BACKUP_CLK_SEL field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL_Msk = 0x30000 + // Position of HP_ACTIVE2SLEEP_BACKUP_CLK_SEL field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_Pos = 0x12 + // Bit mask of HP_ACTIVE2SLEEP_BACKUP_CLK_SEL field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_Msk = 0xc0000 + // Position of HP_MODEM2SLEEP_BACKUP_MODE field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE_Pos = 0x17 + // Bit mask of HP_MODEM2SLEEP_BACKUP_MODE field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE_Msk = 0x3800000 + // Position of HP_ACTIVE2SLEEP_BACKUP_MODE field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE_Pos = 0x1a + // Bit mask of HP_ACTIVE2SLEEP_BACKUP_MODE field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE_Msk = 0x1c000000 + // Position of HP_MODEM2SLEEP_BACKUP_EN field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN_Pos = 0x1e + // Bit mask of HP_MODEM2SLEEP_BACKUP_EN field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN_Msk = 0x40000000 + // Bit HP_MODEM2SLEEP_BACKUP_EN. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN = 0x40000000 + // Position of HP_ACTIVE2SLEEP_BACKUP_EN field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN_Pos = 0x1f + // Bit mask of HP_ACTIVE2SLEEP_BACKUP_EN field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN_Msk = 0x80000000 + // Bit HP_ACTIVE2SLEEP_BACKUP_EN. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN = 0x80000000 + + // HP_SLEEP_BACKUP_CLK: need_des + // Position of HP_SLEEP_BACKUP_ICG_FUNC_EN field. + PMU_HP_SLEEP_BACKUP_CLK_HP_SLEEP_BACKUP_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_SLEEP_BACKUP_ICG_FUNC_EN field. + PMU_HP_SLEEP_BACKUP_CLK_HP_SLEEP_BACKUP_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_SLEEP_SYSCLK: need_des + // Position of HP_SLEEP_DIG_SYS_CLK_NO_DIV field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV_Pos = 0x1a + // Bit mask of HP_SLEEP_DIG_SYS_CLK_NO_DIV field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV_Msk = 0x4000000 + // Bit HP_SLEEP_DIG_SYS_CLK_NO_DIV. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV = 0x4000000 + // Position of HP_SLEEP_ICG_SYS_CLOCK_EN field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN_Pos = 0x1b + // Bit mask of HP_SLEEP_ICG_SYS_CLOCK_EN field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN_Msk = 0x8000000 + // Bit HP_SLEEP_ICG_SYS_CLOCK_EN. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN = 0x8000000 + // Position of HP_SLEEP_SYS_CLK_SLP_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL_Pos = 0x1c + // Bit mask of HP_SLEEP_SYS_CLK_SLP_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL_Msk = 0x10000000 + // Bit HP_SLEEP_SYS_CLK_SLP_SEL. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL = 0x10000000 + // Position of HP_SLEEP_ICG_SLP_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL_Pos = 0x1d + // Bit mask of HP_SLEEP_ICG_SLP_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL_Msk = 0x20000000 + // Bit HP_SLEEP_ICG_SLP_SEL. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL = 0x20000000 + // Position of HP_SLEEP_DIG_SYS_CLK_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL_Pos = 0x1e + // Bit mask of HP_SLEEP_DIG_SYS_CLK_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL_Msk = 0xc0000000 + + // HP_SLEEP_HP_REGULATOR0: need_des + // Position of HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_Pos = 0x10 + // Bit mask of HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_Msk = 0x10000 + // Bit HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD = 0x10000 + // Position of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_Pos = 0x11 + // Bit mask of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_Msk = 0x20000 + // Bit HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD = 0x20000 + // Position of HP_SLEEP_HP_REGULATOR_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD_Pos = 0x12 + // Bit mask of HP_SLEEP_HP_REGULATOR_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD_Msk = 0x40000 + // Bit HP_SLEEP_HP_REGULATOR_XPD. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD = 0x40000 + // Position of HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_Pos = 0x13 + // Bit mask of HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_Msk = 0x780000 + // Position of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_Pos = 0x17 + // Bit mask of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_Msk = 0x7800000 + // Position of HP_SLEEP_HP_REGULATOR_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of HP_SLEEP_HP_REGULATOR_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // HP_SLEEP_HP_REGULATOR1: need_des + // Position of HP_SLEEP_HP_REGULATOR_DRV_B field. + PMU_HP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B_Pos = 0x8 + // Bit mask of HP_SLEEP_HP_REGULATOR_DRV_B field. + PMU_HP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B_Msk = 0xffffff00 + + // HP_SLEEP_XTAL: need_des + // Position of HP_SLEEP_XPD_XTAL field. + PMU_HP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL_Pos = 0x1f + // Bit mask of HP_SLEEP_XPD_XTAL field. + PMU_HP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL_Msk = 0x80000000 + // Bit HP_SLEEP_XPD_XTAL. + PMU_HP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL = 0x80000000 + + // HP_SLEEP_LP_REGULATOR0: need_des + // Position of HP_SLEEP_LP_REGULATOR_SLP_XPD field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD_Pos = 0x15 + // Bit mask of HP_SLEEP_LP_REGULATOR_SLP_XPD field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD_Msk = 0x200000 + // Bit HP_SLEEP_LP_REGULATOR_SLP_XPD. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD = 0x200000 + // Position of HP_SLEEP_LP_REGULATOR_XPD field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD_Pos = 0x16 + // Bit mask of HP_SLEEP_LP_REGULATOR_XPD field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD_Msk = 0x400000 + // Bit HP_SLEEP_LP_REGULATOR_XPD. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD = 0x400000 + // Position of HP_SLEEP_LP_REGULATOR_SLP_DBIAS field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_Pos = 0x17 + // Bit mask of HP_SLEEP_LP_REGULATOR_SLP_DBIAS field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_Msk = 0x7800000 + // Position of HP_SLEEP_LP_REGULATOR_DBIAS field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of HP_SLEEP_LP_REGULATOR_DBIAS field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // HP_SLEEP_LP_REGULATOR1: need_des + // Position of HP_SLEEP_LP_REGULATOR_DRV_B field. + PMU_HP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B_Pos = 0x1c + // Bit mask of HP_SLEEP_LP_REGULATOR_DRV_B field. + PMU_HP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B_Msk = 0xf0000000 + + // HP_SLEEP_LP_DCDC_RESERVE: need_des + // Position of HP_SLEEP_LP_DCDC_RESERVE field. + PMU_HP_SLEEP_LP_DCDC_RESERVE_HP_SLEEP_LP_DCDC_RESERVE_Pos = 0x0 + // Bit mask of HP_SLEEP_LP_DCDC_RESERVE field. + PMU_HP_SLEEP_LP_DCDC_RESERVE_HP_SLEEP_LP_DCDC_RESERVE_Msk = 0xffffffff + + // HP_SLEEP_LP_DIG_POWER: need_des + // Position of HP_SLEEP_LP_MEM_DSLP field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP_Pos = 0x1e + // Bit mask of HP_SLEEP_LP_MEM_DSLP field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP_Msk = 0x40000000 + // Bit HP_SLEEP_LP_MEM_DSLP. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP = 0x40000000 + // Position of HP_SLEEP_PD_LP_PERI_PD_EN field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN_Pos = 0x1f + // Bit mask of HP_SLEEP_PD_LP_PERI_PD_EN field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN_Msk = 0x80000000 + // Bit HP_SLEEP_PD_LP_PERI_PD_EN. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN = 0x80000000 + + // HP_SLEEP_LP_CK_POWER: need_des + // Position of HP_SLEEP_XPD_XTAL32K field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K_Pos = 0x1c + // Bit mask of HP_SLEEP_XPD_XTAL32K field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K_Msk = 0x10000000 + // Bit HP_SLEEP_XPD_XTAL32K. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K = 0x10000000 + // Position of HP_SLEEP_XPD_RC32K field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K_Pos = 0x1d + // Bit mask of HP_SLEEP_XPD_RC32K field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K_Msk = 0x20000000 + // Bit HP_SLEEP_XPD_RC32K. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K = 0x20000000 + // Position of HP_SLEEP_XPD_FOSC_CLK field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK_Pos = 0x1e + // Bit mask of HP_SLEEP_XPD_FOSC_CLK field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK_Msk = 0x40000000 + // Bit HP_SLEEP_XPD_FOSC_CLK. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK = 0x40000000 + // Position of HP_SLEEP_PD_OSC_CLK field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK_Pos = 0x1f + // Bit mask of HP_SLEEP_PD_OSC_CLK field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK_Msk = 0x80000000 + // Bit HP_SLEEP_PD_OSC_CLK. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK = 0x80000000 + + // LP_SLEEP_LP_BIAS_RESERVE: need_des + // Position of LP_SLEEP_LP_BIAS_RESERVE field. + PMU_LP_SLEEP_LP_BIAS_RESERVE_LP_SLEEP_LP_BIAS_RESERVE_Pos = 0x0 + // Bit mask of LP_SLEEP_LP_BIAS_RESERVE field. + PMU_LP_SLEEP_LP_BIAS_RESERVE_LP_SLEEP_LP_BIAS_RESERVE_Msk = 0xffffffff + + // LP_SLEEP_LP_REGULATOR0: need_des + // Position of LP_SLEEP_LP_REGULATOR_SLP_XPD field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD_Pos = 0x15 + // Bit mask of LP_SLEEP_LP_REGULATOR_SLP_XPD field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD_Msk = 0x200000 + // Bit LP_SLEEP_LP_REGULATOR_SLP_XPD. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD = 0x200000 + // Position of LP_SLEEP_LP_REGULATOR_XPD field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD_Pos = 0x16 + // Bit mask of LP_SLEEP_LP_REGULATOR_XPD field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD_Msk = 0x400000 + // Bit LP_SLEEP_LP_REGULATOR_XPD. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD = 0x400000 + // Position of LP_SLEEP_LP_REGULATOR_SLP_DBIAS field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_Pos = 0x17 + // Bit mask of LP_SLEEP_LP_REGULATOR_SLP_DBIAS field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_Msk = 0x7800000 + // Position of LP_SLEEP_LP_REGULATOR_DBIAS field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of LP_SLEEP_LP_REGULATOR_DBIAS field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // LP_SLEEP_LP_REGULATOR1: need_des + // Position of LP_SLEEP_LP_REGULATOR_DRV_B field. + PMU_LP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B_Pos = 0x1c + // Bit mask of LP_SLEEP_LP_REGULATOR_DRV_B field. + PMU_LP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B_Msk = 0xf0000000 + + // LP_SLEEP_XTAL: need_des + // Position of LP_SLEEP_XPD_XTAL field. + PMU_LP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL_Pos = 0x1f + // Bit mask of LP_SLEEP_XPD_XTAL field. + PMU_LP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL_Msk = 0x80000000 + // Bit LP_SLEEP_XPD_XTAL. + PMU_LP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL = 0x80000000 + + // LP_SLEEP_LP_DIG_POWER: need_des + // Position of LP_SLEEP_LP_MEM_DSLP field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP_Pos = 0x1e + // Bit mask of LP_SLEEP_LP_MEM_DSLP field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP_Msk = 0x40000000 + // Bit LP_SLEEP_LP_MEM_DSLP. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP = 0x40000000 + // Position of LP_SLEEP_PD_LP_PERI_PD_EN field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN_Pos = 0x1f + // Bit mask of LP_SLEEP_PD_LP_PERI_PD_EN field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN_Msk = 0x80000000 + // Bit LP_SLEEP_PD_LP_PERI_PD_EN. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN = 0x80000000 + + // LP_SLEEP_LP_CK_POWER: need_des + // Position of LP_SLEEP_XPD_XTAL32K field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K_Pos = 0x1c + // Bit mask of LP_SLEEP_XPD_XTAL32K field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K_Msk = 0x10000000 + // Bit LP_SLEEP_XPD_XTAL32K. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K = 0x10000000 + // Position of LP_SLEEP_XPD_RC32K field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K_Pos = 0x1d + // Bit mask of LP_SLEEP_XPD_RC32K field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K_Msk = 0x20000000 + // Bit LP_SLEEP_XPD_RC32K. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K = 0x20000000 + // Position of LP_SLEEP_XPD_FOSC_CLK field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK_Pos = 0x1e + // Bit mask of LP_SLEEP_XPD_FOSC_CLK field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK_Msk = 0x40000000 + // Bit LP_SLEEP_XPD_FOSC_CLK. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK = 0x40000000 + // Position of LP_SLEEP_PD_OSC_CLK field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK_Pos = 0x1f + // Bit mask of LP_SLEEP_PD_OSC_CLK field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK_Msk = 0x80000000 + // Bit LP_SLEEP_PD_OSC_CLK. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK = 0x80000000 + + // LP_SLEEP_BIAS: need_des + // Position of LP_SLEEP_XPD_BIAS field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS_Pos = 0x19 + // Bit mask of LP_SLEEP_XPD_BIAS field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS_Msk = 0x2000000 + // Bit LP_SLEEP_XPD_BIAS. + PMU_LP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS = 0x2000000 + // Position of LP_SLEEP_DBG_ATTEN field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN_Pos = 0x1a + // Bit mask of LP_SLEEP_DBG_ATTEN field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN_Msk = 0x3c000000 + // Position of LP_SLEEP_PD_CUR field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_PD_CUR_Pos = 0x1e + // Bit mask of LP_SLEEP_PD_CUR field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_PD_CUR_Msk = 0x40000000 + // Bit LP_SLEEP_PD_CUR. + PMU_LP_SLEEP_BIAS_LP_SLEEP_PD_CUR = 0x40000000 + // Position of SLEEP field. + PMU_LP_SLEEP_BIAS_SLEEP_Pos = 0x1f + // Bit mask of SLEEP field. + PMU_LP_SLEEP_BIAS_SLEEP_Msk = 0x80000000 + // Bit SLEEP. + PMU_LP_SLEEP_BIAS_SLEEP = 0x80000000 + + // IMM_HP_CK_POWER: need_des + // Position of TIE_LOW_GLOBAL_BBPLL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG_Pos = 0x0 + // Bit mask of TIE_LOW_GLOBAL_BBPLL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG_Msk = 0x1 + // Bit TIE_LOW_GLOBAL_BBPLL_ICG. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG = 0x1 + // Position of TIE_LOW_GLOBAL_XTAL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG_Pos = 0x1 + // Bit mask of TIE_LOW_GLOBAL_XTAL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG_Msk = 0x2 + // Bit TIE_LOW_GLOBAL_XTAL_ICG. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG = 0x2 + // Position of TIE_LOW_I2C_RETENTION field. + PMU_IMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION_Pos = 0x2 + // Bit mask of TIE_LOW_I2C_RETENTION field. + PMU_IMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION_Msk = 0x4 + // Bit TIE_LOW_I2C_RETENTION. + PMU_IMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION = 0x4 + // Position of TIE_LOW_XPD_BB_I2C field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C_Pos = 0x3 + // Bit mask of TIE_LOW_XPD_BB_I2C field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C_Msk = 0x8 + // Bit TIE_LOW_XPD_BB_I2C. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C = 0x8 + // Position of TIE_LOW_XPD_BBPLL_I2C field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C_Pos = 0x4 + // Bit mask of TIE_LOW_XPD_BBPLL_I2C field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C_Msk = 0x10 + // Bit TIE_LOW_XPD_BBPLL_I2C. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C = 0x10 + // Position of TIE_LOW_XPD_BBPLL field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_Pos = 0x5 + // Bit mask of TIE_LOW_XPD_BBPLL field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_Msk = 0x20 + // Bit TIE_LOW_XPD_BBPLL. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL = 0x20 + // Position of TIE_LOW_XPD_XTAL field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_XTAL_Pos = 0x6 + // Bit mask of TIE_LOW_XPD_XTAL field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_XTAL_Msk = 0x40 + // Bit TIE_LOW_XPD_XTAL. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_XTAL = 0x40 + // Position of TIE_HIGH_GLOBAL_BBPLL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG_Pos = 0x19 + // Bit mask of TIE_HIGH_GLOBAL_BBPLL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG_Msk = 0x2000000 + // Bit TIE_HIGH_GLOBAL_BBPLL_ICG. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG = 0x2000000 + // Position of TIE_HIGH_GLOBAL_XTAL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG_Pos = 0x1a + // Bit mask of TIE_HIGH_GLOBAL_XTAL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG_Msk = 0x4000000 + // Bit TIE_HIGH_GLOBAL_XTAL_ICG. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG = 0x4000000 + // Position of TIE_HIGH_I2C_RETENTION field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION_Pos = 0x1b + // Bit mask of TIE_HIGH_I2C_RETENTION field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION_Msk = 0x8000000 + // Bit TIE_HIGH_I2C_RETENTION. + PMU_IMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION = 0x8000000 + // Position of TIE_HIGH_XPD_BB_I2C field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C_Pos = 0x1c + // Bit mask of TIE_HIGH_XPD_BB_I2C field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C_Msk = 0x10000000 + // Bit TIE_HIGH_XPD_BB_I2C. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C = 0x10000000 + // Position of TIE_HIGH_XPD_BBPLL_I2C field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C_Pos = 0x1d + // Bit mask of TIE_HIGH_XPD_BBPLL_I2C field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C_Msk = 0x20000000 + // Bit TIE_HIGH_XPD_BBPLL_I2C. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C = 0x20000000 + // Position of TIE_HIGH_XPD_BBPLL field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_Pos = 0x1e + // Bit mask of TIE_HIGH_XPD_BBPLL field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_Msk = 0x40000000 + // Bit TIE_HIGH_XPD_BBPLL. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL = 0x40000000 + // Position of TIE_HIGH_XPD_XTAL field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL_Pos = 0x1f + // Bit mask of TIE_HIGH_XPD_XTAL field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL_Msk = 0x80000000 + // Bit TIE_HIGH_XPD_XTAL. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL = 0x80000000 + + // IMM_SLEEP_SYSCLK: need_des + // Position of UPDATE_DIG_ICG_SWITCH field. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH_Pos = 0x1c + // Bit mask of UPDATE_DIG_ICG_SWITCH field. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH_Msk = 0x10000000 + // Bit UPDATE_DIG_ICG_SWITCH. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH = 0x10000000 + // Position of TIE_LOW_ICG_SLP_SEL field. + PMU_IMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL_Pos = 0x1d + // Bit mask of TIE_LOW_ICG_SLP_SEL field. + PMU_IMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL_Msk = 0x20000000 + // Bit TIE_LOW_ICG_SLP_SEL. + PMU_IMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL = 0x20000000 + // Position of TIE_HIGH_ICG_SLP_SEL field. + PMU_IMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL_Pos = 0x1e + // Bit mask of TIE_HIGH_ICG_SLP_SEL field. + PMU_IMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL_Msk = 0x40000000 + // Bit TIE_HIGH_ICG_SLP_SEL. + PMU_IMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL = 0x40000000 + // Position of UPDATE_DIG_SYS_CLK_SEL field. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL_Pos = 0x1f + // Bit mask of UPDATE_DIG_SYS_CLK_SEL field. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL_Msk = 0x80000000 + // Bit UPDATE_DIG_SYS_CLK_SEL. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL = 0x80000000 + + // IMM_HP_FUNC_ICG: need_des + // Position of UPDATE_DIG_ICG_FUNC_EN field. + PMU_IMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN_Pos = 0x1f + // Bit mask of UPDATE_DIG_ICG_FUNC_EN field. + PMU_IMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN_Msk = 0x80000000 + // Bit UPDATE_DIG_ICG_FUNC_EN. + PMU_IMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN = 0x80000000 + + // IMM_HP_APB_ICG: need_des + // Position of UPDATE_DIG_ICG_APB_EN field. + PMU_IMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN_Pos = 0x1f + // Bit mask of UPDATE_DIG_ICG_APB_EN field. + PMU_IMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN_Msk = 0x80000000 + // Bit UPDATE_DIG_ICG_APB_EN. + PMU_IMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN = 0x80000000 + + // IMM_MODEM_ICG: need_des + // Position of UPDATE_DIG_ICG_MODEM_EN field. + PMU_IMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN_Pos = 0x1f + // Bit mask of UPDATE_DIG_ICG_MODEM_EN field. + PMU_IMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN_Msk = 0x80000000 + // Bit UPDATE_DIG_ICG_MODEM_EN. + PMU_IMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN = 0x80000000 + + // IMM_LP_ICG: need_des + // Position of TIE_LOW_LP_ROOTCLK_SEL field. + PMU_IMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL_Pos = 0x1e + // Bit mask of TIE_LOW_LP_ROOTCLK_SEL field. + PMU_IMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL_Msk = 0x40000000 + // Bit TIE_LOW_LP_ROOTCLK_SEL. + PMU_IMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL = 0x40000000 + // Position of TIE_HIGH_LP_ROOTCLK_SEL field. + PMU_IMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL_Pos = 0x1f + // Bit mask of TIE_HIGH_LP_ROOTCLK_SEL field. + PMU_IMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL_Msk = 0x80000000 + // Bit TIE_HIGH_LP_ROOTCLK_SEL. + PMU_IMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL = 0x80000000 + + // IMM_PAD_HOLD_ALL: need_des + // Position of TIE_HIGH_LP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL_Pos = 0x1c + // Bit mask of TIE_HIGH_LP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL_Msk = 0x10000000 + // Bit TIE_HIGH_LP_PAD_HOLD_ALL. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL = 0x10000000 + // Position of TIE_LOW_LP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL_Pos = 0x1d + // Bit mask of TIE_LOW_LP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL_Msk = 0x20000000 + // Bit TIE_LOW_LP_PAD_HOLD_ALL. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL = 0x20000000 + // Position of TIE_HIGH_HP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL_Pos = 0x1e + // Bit mask of TIE_HIGH_HP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL_Msk = 0x40000000 + // Bit TIE_HIGH_HP_PAD_HOLD_ALL. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL = 0x40000000 + // Position of TIE_LOW_HP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL_Pos = 0x1f + // Bit mask of TIE_LOW_HP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL_Msk = 0x80000000 + // Bit TIE_LOW_HP_PAD_HOLD_ALL. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL = 0x80000000 + + // IMM_I2C_ISO: need_des + // Position of TIE_HIGH_I2C_ISO_EN field. + PMU_IMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN_Pos = 0x1e + // Bit mask of TIE_HIGH_I2C_ISO_EN field. + PMU_IMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN_Msk = 0x40000000 + // Bit TIE_HIGH_I2C_ISO_EN. + PMU_IMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN = 0x40000000 + // Position of TIE_LOW_I2C_ISO_EN field. + PMU_IMM_I2C_ISO_TIE_LOW_I2C_ISO_EN_Pos = 0x1f + // Bit mask of TIE_LOW_I2C_ISO_EN field. + PMU_IMM_I2C_ISO_TIE_LOW_I2C_ISO_EN_Msk = 0x80000000 + // Bit TIE_LOW_I2C_ISO_EN. + PMU_IMM_I2C_ISO_TIE_LOW_I2C_ISO_EN = 0x80000000 + + // POWER_WAIT_TIMER0: need_des + // Position of DG_HP_POWERDOWN_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER_Pos = 0x5 + // Bit mask of DG_HP_POWERDOWN_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER_Msk = 0x3fe0 + // Position of DG_HP_POWERUP_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER_Pos = 0xe + // Bit mask of DG_HP_POWERUP_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER_Msk = 0x7fc000 + // Position of DG_HP_WAIT_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_WAIT_TIMER_Pos = 0x17 + // Bit mask of DG_HP_WAIT_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_WAIT_TIMER_Msk = 0xff800000 + + // POWER_WAIT_TIMER1: need_des + // Position of DG_LP_POWERDOWN_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER_Pos = 0x9 + // Bit mask of DG_LP_POWERDOWN_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER_Msk = 0xfe00 + // Position of DG_LP_POWERUP_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER_Pos = 0x10 + // Bit mask of DG_LP_POWERUP_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER_Msk = 0x7f0000 + // Position of DG_LP_WAIT_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_WAIT_TIMER_Pos = 0x17 + // Bit mask of DG_LP_WAIT_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_WAIT_TIMER_Msk = 0xff800000 + + // POWER_PD_TOP_CNTL: need_des + // Position of FORCE_TOP_RESET field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_RESET_Pos = 0x0 + // Bit mask of FORCE_TOP_RESET field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_RESET_Msk = 0x1 + // Bit FORCE_TOP_RESET. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_RESET = 0x1 + // Position of FORCE_TOP_ISO field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_ISO_Pos = 0x1 + // Bit mask of FORCE_TOP_ISO field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_ISO_Msk = 0x2 + // Bit FORCE_TOP_ISO. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_ISO = 0x2 + // Position of FORCE_TOP_PU field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PU_Pos = 0x2 + // Bit mask of FORCE_TOP_PU field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PU_Msk = 0x4 + // Bit FORCE_TOP_PU. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PU = 0x4 + // Position of FORCE_TOP_NO_RESET field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_TOP_NO_RESET field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET_Msk = 0x8 + // Bit FORCE_TOP_NO_RESET. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET = 0x8 + // Position of FORCE_TOP_NO_ISO field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_TOP_NO_ISO field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO_Msk = 0x10 + // Bit FORCE_TOP_NO_ISO. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO = 0x10 + // Position of FORCE_TOP_PD field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PD_Pos = 0x5 + // Bit mask of FORCE_TOP_PD field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PD_Msk = 0x20 + // Bit FORCE_TOP_PD. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PD = 0x20 + // Position of PD_TOP_MASK field. + PMU_POWER_PD_TOP_CNTL_PD_TOP_MASK_Pos = 0x6 + // Bit mask of PD_TOP_MASK field. + PMU_POWER_PD_TOP_CNTL_PD_TOP_MASK_Msk = 0x7c0 + // Position of PD_TOP_PD_MASK field. + PMU_POWER_PD_TOP_CNTL_PD_TOP_PD_MASK_Pos = 0x1b + // Bit mask of PD_TOP_PD_MASK field. + PMU_POWER_PD_TOP_CNTL_PD_TOP_PD_MASK_Msk = 0xf8000000 + + // POWER_PD_HPAON_CNTL: need_des + // Position of FORCE_HP_AON_RESET field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET_Pos = 0x0 + // Bit mask of FORCE_HP_AON_RESET field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET_Msk = 0x1 + // Bit FORCE_HP_AON_RESET. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET = 0x1 + // Position of FORCE_HP_AON_ISO field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO_Pos = 0x1 + // Bit mask of FORCE_HP_AON_ISO field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO_Msk = 0x2 + // Bit FORCE_HP_AON_ISO. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO = 0x2 + // Position of FORCE_HP_AON_PU field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PU_Pos = 0x2 + // Bit mask of FORCE_HP_AON_PU field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PU_Msk = 0x4 + // Bit FORCE_HP_AON_PU. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PU = 0x4 + // Position of FORCE_HP_AON_NO_RESET field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_HP_AON_NO_RESET field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET_Msk = 0x8 + // Bit FORCE_HP_AON_NO_RESET. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET = 0x8 + // Position of FORCE_HP_AON_NO_ISO field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_HP_AON_NO_ISO field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO_Msk = 0x10 + // Bit FORCE_HP_AON_NO_ISO. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO = 0x10 + // Position of FORCE_HP_AON_PD field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PD_Pos = 0x5 + // Bit mask of FORCE_HP_AON_PD field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PD_Msk = 0x20 + // Bit FORCE_HP_AON_PD. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PD = 0x20 + // Position of PD_HP_AON_MASK field. + PMU_POWER_PD_HPAON_CNTL_PD_HP_AON_MASK_Pos = 0x6 + // Bit mask of PD_HP_AON_MASK field. + PMU_POWER_PD_HPAON_CNTL_PD_HP_AON_MASK_Msk = 0x7c0 + // Position of PD_HP_AON_PD_MASK field. + PMU_POWER_PD_HPAON_CNTL_PD_HP_AON_PD_MASK_Pos = 0x1b + // Bit mask of PD_HP_AON_PD_MASK field. + PMU_POWER_PD_HPAON_CNTL_PD_HP_AON_PD_MASK_Msk = 0xf8000000 + + // POWER_PD_HPCPU_CNTL: need_des + // Position of FORCE_HP_CPU_RESET field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET_Pos = 0x0 + // Bit mask of FORCE_HP_CPU_RESET field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET_Msk = 0x1 + // Bit FORCE_HP_CPU_RESET. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET = 0x1 + // Position of FORCE_HP_CPU_ISO field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO_Pos = 0x1 + // Bit mask of FORCE_HP_CPU_ISO field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO_Msk = 0x2 + // Bit FORCE_HP_CPU_ISO. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO = 0x2 + // Position of FORCE_HP_CPU_PU field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU_Pos = 0x2 + // Bit mask of FORCE_HP_CPU_PU field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU_Msk = 0x4 + // Bit FORCE_HP_CPU_PU. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU = 0x4 + // Position of FORCE_HP_CPU_NO_RESET field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_HP_CPU_NO_RESET field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET_Msk = 0x8 + // Bit FORCE_HP_CPU_NO_RESET. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET = 0x8 + // Position of FORCE_HP_CPU_NO_ISO field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_HP_CPU_NO_ISO field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO_Msk = 0x10 + // Bit FORCE_HP_CPU_NO_ISO. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO = 0x10 + // Position of FORCE_HP_CPU_PD field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD_Pos = 0x5 + // Bit mask of FORCE_HP_CPU_PD field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD_Msk = 0x20 + // Bit FORCE_HP_CPU_PD. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD = 0x20 + // Position of PD_HP_CPU_MASK field. + PMU_POWER_PD_HPCPU_CNTL_PD_HP_CPU_MASK_Pos = 0x6 + // Bit mask of PD_HP_CPU_MASK field. + PMU_POWER_PD_HPCPU_CNTL_PD_HP_CPU_MASK_Msk = 0x7c0 + // Position of PD_HP_CPU_PD_MASK field. + PMU_POWER_PD_HPCPU_CNTL_PD_HP_CPU_PD_MASK_Pos = 0x1b + // Bit mask of PD_HP_CPU_PD_MASK field. + PMU_POWER_PD_HPCPU_CNTL_PD_HP_CPU_PD_MASK_Msk = 0xf8000000 + + // POWER_PD_HPPERI_RESERVE: need_des + // Position of HP_PERI_RESERVE field. + PMU_POWER_PD_HPPERI_RESERVE_HP_PERI_RESERVE_Pos = 0x0 + // Bit mask of HP_PERI_RESERVE field. + PMU_POWER_PD_HPPERI_RESERVE_HP_PERI_RESERVE_Msk = 0xffffffff + + // POWER_PD_HPWIFI_CNTL: need_des + // Position of FORCE_HP_WIFI_RESET field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET_Pos = 0x0 + // Bit mask of FORCE_HP_WIFI_RESET field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET_Msk = 0x1 + // Bit FORCE_HP_WIFI_RESET. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET = 0x1 + // Position of FORCE_HP_WIFI_ISO field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO_Pos = 0x1 + // Bit mask of FORCE_HP_WIFI_ISO field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO_Msk = 0x2 + // Bit FORCE_HP_WIFI_ISO. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO = 0x2 + // Position of FORCE_HP_WIFI_PU field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU_Pos = 0x2 + // Bit mask of FORCE_HP_WIFI_PU field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU_Msk = 0x4 + // Bit FORCE_HP_WIFI_PU. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU = 0x4 + // Position of FORCE_HP_WIFI_NO_RESET field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_HP_WIFI_NO_RESET field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET_Msk = 0x8 + // Bit FORCE_HP_WIFI_NO_RESET. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET = 0x8 + // Position of FORCE_HP_WIFI_NO_ISO field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_HP_WIFI_NO_ISO field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO_Msk = 0x10 + // Bit FORCE_HP_WIFI_NO_ISO. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO = 0x10 + // Position of FORCE_HP_WIFI_PD field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD_Pos = 0x5 + // Bit mask of FORCE_HP_WIFI_PD field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD_Msk = 0x20 + // Bit FORCE_HP_WIFI_PD. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD = 0x20 + // Position of PD_HP_WIFI_MASK field. + PMU_POWER_PD_HPWIFI_CNTL_PD_HP_WIFI_MASK_Pos = 0x6 + // Bit mask of PD_HP_WIFI_MASK field. + PMU_POWER_PD_HPWIFI_CNTL_PD_HP_WIFI_MASK_Msk = 0x7c0 + // Position of PD_HP_WIFI_PD_MASK field. + PMU_POWER_PD_HPWIFI_CNTL_PD_HP_WIFI_PD_MASK_Pos = 0x1b + // Bit mask of PD_HP_WIFI_PD_MASK field. + PMU_POWER_PD_HPWIFI_CNTL_PD_HP_WIFI_PD_MASK_Msk = 0xf8000000 + + // POWER_PD_LPPERI_CNTL: need_des + // Position of FORCE_LP_PERI_RESET field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET_Pos = 0x0 + // Bit mask of FORCE_LP_PERI_RESET field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET_Msk = 0x1 + // Bit FORCE_LP_PERI_RESET. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET = 0x1 + // Position of FORCE_LP_PERI_ISO field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO_Pos = 0x1 + // Bit mask of FORCE_LP_PERI_ISO field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO_Msk = 0x2 + // Bit FORCE_LP_PERI_ISO. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO = 0x2 + // Position of FORCE_LP_PERI_PU field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU_Pos = 0x2 + // Bit mask of FORCE_LP_PERI_PU field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU_Msk = 0x4 + // Bit FORCE_LP_PERI_PU. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU = 0x4 + // Position of FORCE_LP_PERI_NO_RESET field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_LP_PERI_NO_RESET field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET_Msk = 0x8 + // Bit FORCE_LP_PERI_NO_RESET. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET = 0x8 + // Position of FORCE_LP_PERI_NO_ISO field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_LP_PERI_NO_ISO field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO_Msk = 0x10 + // Bit FORCE_LP_PERI_NO_ISO. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO = 0x10 + // Position of FORCE_LP_PERI_PD field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD_Pos = 0x5 + // Bit mask of FORCE_LP_PERI_PD field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD_Msk = 0x20 + // Bit FORCE_LP_PERI_PD. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD = 0x20 + + // POWER_PD_MEM_CNTL: need_des + // Position of FORCE_HP_MEM_ISO field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_ISO_Pos = 0x0 + // Bit mask of FORCE_HP_MEM_ISO field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_ISO_Msk = 0xf + // Position of FORCE_HP_MEM_PD field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_PD_Pos = 0x4 + // Bit mask of FORCE_HP_MEM_PD field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_PD_Msk = 0xf0 + // Position of FORCE_HP_MEM_NO_ISO field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_NO_ISO_Pos = 0x18 + // Bit mask of FORCE_HP_MEM_NO_ISO field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_NO_ISO_Msk = 0xf000000 + // Position of FORCE_HP_MEM_PU field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_PU_Pos = 0x1c + // Bit mask of FORCE_HP_MEM_PU field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_PU_Msk = 0xf0000000 + + // POWER_PD_MEM_MASK: need_des + // Position of PD_HP_MEM2_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM2_PD_MASK_Pos = 0x0 + // Bit mask of PD_HP_MEM2_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM2_PD_MASK_Msk = 0x1f + // Position of PD_HP_MEM1_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM1_PD_MASK_Pos = 0x5 + // Bit mask of PD_HP_MEM1_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM1_PD_MASK_Msk = 0x3e0 + // Position of PD_HP_MEM0_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM0_PD_MASK_Pos = 0xa + // Bit mask of PD_HP_MEM0_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM0_PD_MASK_Msk = 0x7c00 + // Position of PD_HP_MEM2_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM2_MASK_Pos = 0x11 + // Bit mask of PD_HP_MEM2_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM2_MASK_Msk = 0x3e0000 + // Position of PD_HP_MEM1_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM1_MASK_Pos = 0x16 + // Bit mask of PD_HP_MEM1_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM1_MASK_Msk = 0x7c00000 + // Position of PD_HP_MEM0_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM0_MASK_Pos = 0x1b + // Bit mask of PD_HP_MEM0_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM0_MASK_Msk = 0xf8000000 + + // POWER_HP_PAD: need_des + // Position of FORCE_HP_PAD_NO_ISO_ALL field. + PMU_POWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL_Pos = 0x0 + // Bit mask of FORCE_HP_PAD_NO_ISO_ALL field. + PMU_POWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL_Msk = 0x1 + // Bit FORCE_HP_PAD_NO_ISO_ALL. + PMU_POWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL = 0x1 + // Position of FORCE_HP_PAD_ISO_ALL field. + PMU_POWER_HP_PAD_FORCE_HP_PAD_ISO_ALL_Pos = 0x1 + // Bit mask of FORCE_HP_PAD_ISO_ALL field. + PMU_POWER_HP_PAD_FORCE_HP_PAD_ISO_ALL_Msk = 0x2 + // Bit FORCE_HP_PAD_ISO_ALL. + PMU_POWER_HP_PAD_FORCE_HP_PAD_ISO_ALL = 0x2 + + // POWER_VDD_SPI_CNTL: need_des + // Position of VDD_SPI_PWR_WAIT field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_WAIT_Pos = 0x12 + // Bit mask of VDD_SPI_PWR_WAIT field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_WAIT_Msk = 0x1ffc0000 + // Position of VDD_SPI_PWR_SW field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SW_Pos = 0x1d + // Bit mask of VDD_SPI_PWR_SW field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SW_Msk = 0x60000000 + // Position of VDD_SPI_PWR_SEL_SW field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW_Pos = 0x1f + // Bit mask of VDD_SPI_PWR_SEL_SW field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW_Msk = 0x80000000 + // Bit VDD_SPI_PWR_SEL_SW. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW = 0x80000000 + + // POWER_CK_WAIT_CNTL: need_des + // Position of WAIT_XTL_STABLE field. + PMU_POWER_CK_WAIT_CNTL_WAIT_XTL_STABLE_Pos = 0x0 + // Bit mask of WAIT_XTL_STABLE field. + PMU_POWER_CK_WAIT_CNTL_WAIT_XTL_STABLE_Msk = 0xffff + // Position of WAIT_PLL_STABLE field. + PMU_POWER_CK_WAIT_CNTL_WAIT_PLL_STABLE_Pos = 0x10 + // Bit mask of WAIT_PLL_STABLE field. + PMU_POWER_CK_WAIT_CNTL_WAIT_PLL_STABLE_Msk = 0xffff0000 + + // SLP_WAKEUP_CNTL0: need_des + // Position of SLEEP_REQ field. + PMU_SLP_WAKEUP_CNTL0_SLEEP_REQ_Pos = 0x1f + // Bit mask of SLEEP_REQ field. + PMU_SLP_WAKEUP_CNTL0_SLEEP_REQ_Msk = 0x80000000 + // Bit SLEEP_REQ. + PMU_SLP_WAKEUP_CNTL0_SLEEP_REQ = 0x80000000 + + // SLP_WAKEUP_CNTL1: need_des + // Position of SLEEP_REJECT_ENA field. + PMU_SLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA_Pos = 0x0 + // Bit mask of SLEEP_REJECT_ENA field. + PMU_SLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA_Msk = 0x7fffffff + // Position of SLP_REJECT_EN field. + PMU_SLP_WAKEUP_CNTL1_SLP_REJECT_EN_Pos = 0x1f + // Bit mask of SLP_REJECT_EN field. + PMU_SLP_WAKEUP_CNTL1_SLP_REJECT_EN_Msk = 0x80000000 + // Bit SLP_REJECT_EN. + PMU_SLP_WAKEUP_CNTL1_SLP_REJECT_EN = 0x80000000 + + // SLP_WAKEUP_CNTL2: need_des + // Position of WAKEUP_ENA field. + PMU_SLP_WAKEUP_CNTL2_WAKEUP_ENA_Pos = 0x0 + // Bit mask of WAKEUP_ENA field. + PMU_SLP_WAKEUP_CNTL2_WAKEUP_ENA_Msk = 0xffffffff + + // SLP_WAKEUP_CNTL3: need_des + // Position of LP_MIN_SLP_VAL field. + PMU_SLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL_Pos = 0x0 + // Bit mask of LP_MIN_SLP_VAL field. + PMU_SLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL_Msk = 0xff + // Position of HP_MIN_SLP_VAL field. + PMU_SLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL_Pos = 0x8 + // Bit mask of HP_MIN_SLP_VAL field. + PMU_SLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL_Msk = 0xff00 + // Position of SLEEP_PRT_SEL field. + PMU_SLP_WAKEUP_CNTL3_SLEEP_PRT_SEL_Pos = 0x10 + // Bit mask of SLEEP_PRT_SEL field. + PMU_SLP_WAKEUP_CNTL3_SLEEP_PRT_SEL_Msk = 0x30000 + + // SLP_WAKEUP_CNTL4: need_des + // Position of SLP_REJECT_CAUSE_CLR field. + PMU_SLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR_Pos = 0x1f + // Bit mask of SLP_REJECT_CAUSE_CLR field. + PMU_SLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR_Msk = 0x80000000 + // Bit SLP_REJECT_CAUSE_CLR. + PMU_SLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR = 0x80000000 + + // SLP_WAKEUP_CNTL5: need_des + // Position of MODEM_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET_Pos = 0x0 + // Bit mask of MODEM_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET_Msk = 0xfffff + // Position of LP_ANA_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET_Pos = 0x18 + // Bit mask of LP_ANA_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET_Msk = 0xff000000 + + // SLP_WAKEUP_CNTL6: need_des + // Position of SOC_WAKEUP_WAIT field. + PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_Pos = 0x0 + // Bit mask of SOC_WAKEUP_WAIT field. + PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_Msk = 0xfffff + // Position of SOC_WAKEUP_WAIT_CFG field. + PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG_Pos = 0x1e + // Bit mask of SOC_WAKEUP_WAIT_CFG field. + PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG_Msk = 0xc0000000 + + // SLP_WAKEUP_CNTL7: need_des + // Position of ANA_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL7_ANA_WAIT_TARGET_Pos = 0x10 + // Bit mask of ANA_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL7_ANA_WAIT_TARGET_Msk = 0xffff0000 + + // SLP_WAKEUP_STATUS0: need_des + // Position of WAKEUP_CAUSE field. + PMU_SLP_WAKEUP_STATUS0_WAKEUP_CAUSE_Pos = 0x0 + // Bit mask of WAKEUP_CAUSE field. + PMU_SLP_WAKEUP_STATUS0_WAKEUP_CAUSE_Msk = 0xffffffff + + // SLP_WAKEUP_STATUS1: need_des + // Position of REJECT_CAUSE field. + PMU_SLP_WAKEUP_STATUS1_REJECT_CAUSE_Pos = 0x0 + // Bit mask of REJECT_CAUSE field. + PMU_SLP_WAKEUP_STATUS1_REJECT_CAUSE_Msk = 0xffffffff + + // HP_CK_POWERON: need_des + // Position of I2C_POR_WAIT_TARGET field. + PMU_HP_CK_POWERON_I2C_POR_WAIT_TARGET_Pos = 0x0 + // Bit mask of I2C_POR_WAIT_TARGET field. + PMU_HP_CK_POWERON_I2C_POR_WAIT_TARGET_Msk = 0xff + + // HP_CK_CNTL: need_des + // Position of MODIFY_ICG_CNTL_WAIT field. + PMU_HP_CK_CNTL_MODIFY_ICG_CNTL_WAIT_Pos = 0x0 + // Bit mask of MODIFY_ICG_CNTL_WAIT field. + PMU_HP_CK_CNTL_MODIFY_ICG_CNTL_WAIT_Msk = 0xff + // Position of SWITCH_ICG_CNTL_WAIT field. + PMU_HP_CK_CNTL_SWITCH_ICG_CNTL_WAIT_Pos = 0x8 + // Bit mask of SWITCH_ICG_CNTL_WAIT field. + PMU_HP_CK_CNTL_SWITCH_ICG_CNTL_WAIT_Msk = 0xff00 + + // POR_STATUS: need_des + // Position of POR_DONE field. + PMU_POR_STATUS_POR_DONE_Pos = 0x1f + // Bit mask of POR_DONE field. + PMU_POR_STATUS_POR_DONE_Msk = 0x80000000 + // Bit POR_DONE. + PMU_POR_STATUS_POR_DONE = 0x80000000 + + // RF_PWC: need_des + // Position of PERIF_I2C_RSTB field. + PMU_RF_PWC_PERIF_I2C_RSTB_Pos = 0x1a + // Bit mask of PERIF_I2C_RSTB field. + PMU_RF_PWC_PERIF_I2C_RSTB_Msk = 0x4000000 + // Bit PERIF_I2C_RSTB. + PMU_RF_PWC_PERIF_I2C_RSTB = 0x4000000 + // Position of XPD_PERIF_I2C field. + PMU_RF_PWC_XPD_PERIF_I2C_Pos = 0x1b + // Bit mask of XPD_PERIF_I2C field. + PMU_RF_PWC_XPD_PERIF_I2C_Msk = 0x8000000 + // Bit XPD_PERIF_I2C. + PMU_RF_PWC_XPD_PERIF_I2C = 0x8000000 + // Position of XPD_TXRF_I2C field. + PMU_RF_PWC_XPD_TXRF_I2C_Pos = 0x1c + // Bit mask of XPD_TXRF_I2C field. + PMU_RF_PWC_XPD_TXRF_I2C_Msk = 0x10000000 + // Bit XPD_TXRF_I2C. + PMU_RF_PWC_XPD_TXRF_I2C = 0x10000000 + // Position of XPD_RFRX_PBUS field. + PMU_RF_PWC_XPD_RFRX_PBUS_Pos = 0x1d + // Bit mask of XPD_RFRX_PBUS field. + PMU_RF_PWC_XPD_RFRX_PBUS_Msk = 0x20000000 + // Bit XPD_RFRX_PBUS. + PMU_RF_PWC_XPD_RFRX_PBUS = 0x20000000 + // Position of XPD_CKGEN_I2C field. + PMU_RF_PWC_XPD_CKGEN_I2C_Pos = 0x1e + // Bit mask of XPD_CKGEN_I2C field. + PMU_RF_PWC_XPD_CKGEN_I2C_Msk = 0x40000000 + // Bit XPD_CKGEN_I2C. + PMU_RF_PWC_XPD_CKGEN_I2C = 0x40000000 + // Position of XPD_PLL_I2C field. + PMU_RF_PWC_XPD_PLL_I2C_Pos = 0x1f + // Bit mask of XPD_PLL_I2C field. + PMU_RF_PWC_XPD_PLL_I2C_Msk = 0x80000000 + // Bit XPD_PLL_I2C. + PMU_RF_PWC_XPD_PLL_I2C = 0x80000000 + + // BACKUP_CFG: need_des + // Position of BACKUP_SYS_CLK_NO_DIV field. + PMU_BACKUP_CFG_BACKUP_SYS_CLK_NO_DIV_Pos = 0x1f + // Bit mask of BACKUP_SYS_CLK_NO_DIV field. + PMU_BACKUP_CFG_BACKUP_SYS_CLK_NO_DIV_Msk = 0x80000000 + // Bit BACKUP_SYS_CLK_NO_DIV. + PMU_BACKUP_CFG_BACKUP_SYS_CLK_NO_DIV = 0x80000000 + + // INT_RAW: need_des + // Position of LP_CPU_EXC_INT_RAW field. + PMU_INT_RAW_LP_CPU_EXC_INT_RAW_Pos = 0x1b + // Bit mask of LP_CPU_EXC_INT_RAW field. + PMU_INT_RAW_LP_CPU_EXC_INT_RAW_Msk = 0x8000000 + // Bit LP_CPU_EXC_INT_RAW. + PMU_INT_RAW_LP_CPU_EXC_INT_RAW = 0x8000000 + // Position of SDIO_IDLE_INT_RAW field. + PMU_INT_RAW_SDIO_IDLE_INT_RAW_Pos = 0x1c + // Bit mask of SDIO_IDLE_INT_RAW field. + PMU_INT_RAW_SDIO_IDLE_INT_RAW_Msk = 0x10000000 + // Bit SDIO_IDLE_INT_RAW. + PMU_INT_RAW_SDIO_IDLE_INT_RAW = 0x10000000 + // Position of SW_INT_RAW field. + PMU_INT_RAW_SW_INT_RAW_Pos = 0x1d + // Bit mask of SW_INT_RAW field. + PMU_INT_RAW_SW_INT_RAW_Msk = 0x20000000 + // Bit SW_INT_RAW. + PMU_INT_RAW_SW_INT_RAW = 0x20000000 + // Position of SOC_SLEEP_REJECT_INT_RAW field. + PMU_INT_RAW_SOC_SLEEP_REJECT_INT_RAW_Pos = 0x1e + // Bit mask of SOC_SLEEP_REJECT_INT_RAW field. + PMU_INT_RAW_SOC_SLEEP_REJECT_INT_RAW_Msk = 0x40000000 + // Bit SOC_SLEEP_REJECT_INT_RAW. + PMU_INT_RAW_SOC_SLEEP_REJECT_INT_RAW = 0x40000000 + // Position of SOC_WAKEUP_INT_RAW field. + PMU_INT_RAW_SOC_WAKEUP_INT_RAW_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_RAW field. + PMU_INT_RAW_SOC_WAKEUP_INT_RAW_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_RAW. + PMU_INT_RAW_SOC_WAKEUP_INT_RAW = 0x80000000 + + // HP_INT_ST: need_des + // Position of LP_CPU_EXC_INT_ST field. + PMU_HP_INT_ST_LP_CPU_EXC_INT_ST_Pos = 0x1b + // Bit mask of LP_CPU_EXC_INT_ST field. + PMU_HP_INT_ST_LP_CPU_EXC_INT_ST_Msk = 0x8000000 + // Bit LP_CPU_EXC_INT_ST. + PMU_HP_INT_ST_LP_CPU_EXC_INT_ST = 0x8000000 + // Position of SDIO_IDLE_INT_ST field. + PMU_HP_INT_ST_SDIO_IDLE_INT_ST_Pos = 0x1c + // Bit mask of SDIO_IDLE_INT_ST field. + PMU_HP_INT_ST_SDIO_IDLE_INT_ST_Msk = 0x10000000 + // Bit SDIO_IDLE_INT_ST. + PMU_HP_INT_ST_SDIO_IDLE_INT_ST = 0x10000000 + // Position of SW_INT_ST field. + PMU_HP_INT_ST_SW_INT_ST_Pos = 0x1d + // Bit mask of SW_INT_ST field. + PMU_HP_INT_ST_SW_INT_ST_Msk = 0x20000000 + // Bit SW_INT_ST. + PMU_HP_INT_ST_SW_INT_ST = 0x20000000 + // Position of SOC_SLEEP_REJECT_INT_ST field. + PMU_HP_INT_ST_SOC_SLEEP_REJECT_INT_ST_Pos = 0x1e + // Bit mask of SOC_SLEEP_REJECT_INT_ST field. + PMU_HP_INT_ST_SOC_SLEEP_REJECT_INT_ST_Msk = 0x40000000 + // Bit SOC_SLEEP_REJECT_INT_ST. + PMU_HP_INT_ST_SOC_SLEEP_REJECT_INT_ST = 0x40000000 + // Position of SOC_WAKEUP_INT_ST field. + PMU_HP_INT_ST_SOC_WAKEUP_INT_ST_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ST field. + PMU_HP_INT_ST_SOC_WAKEUP_INT_ST_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ST. + PMU_HP_INT_ST_SOC_WAKEUP_INT_ST = 0x80000000 + + // HP_INT_ENA: need_des + // Position of LP_CPU_EXC_INT_ENA field. + PMU_HP_INT_ENA_LP_CPU_EXC_INT_ENA_Pos = 0x1b + // Bit mask of LP_CPU_EXC_INT_ENA field. + PMU_HP_INT_ENA_LP_CPU_EXC_INT_ENA_Msk = 0x8000000 + // Bit LP_CPU_EXC_INT_ENA. + PMU_HP_INT_ENA_LP_CPU_EXC_INT_ENA = 0x8000000 + // Position of SDIO_IDLE_INT_ENA field. + PMU_HP_INT_ENA_SDIO_IDLE_INT_ENA_Pos = 0x1c + // Bit mask of SDIO_IDLE_INT_ENA field. + PMU_HP_INT_ENA_SDIO_IDLE_INT_ENA_Msk = 0x10000000 + // Bit SDIO_IDLE_INT_ENA. + PMU_HP_INT_ENA_SDIO_IDLE_INT_ENA = 0x10000000 + // Position of SW_INT_ENA field. + PMU_HP_INT_ENA_SW_INT_ENA_Pos = 0x1d + // Bit mask of SW_INT_ENA field. + PMU_HP_INT_ENA_SW_INT_ENA_Msk = 0x20000000 + // Bit SW_INT_ENA. + PMU_HP_INT_ENA_SW_INT_ENA = 0x20000000 + // Position of SOC_SLEEP_REJECT_INT_ENA field. + PMU_HP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA_Pos = 0x1e + // Bit mask of SOC_SLEEP_REJECT_INT_ENA field. + PMU_HP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA_Msk = 0x40000000 + // Bit SOC_SLEEP_REJECT_INT_ENA. + PMU_HP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA = 0x40000000 + // Position of SOC_WAKEUP_INT_ENA field. + PMU_HP_INT_ENA_SOC_WAKEUP_INT_ENA_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ENA field. + PMU_HP_INT_ENA_SOC_WAKEUP_INT_ENA_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ENA. + PMU_HP_INT_ENA_SOC_WAKEUP_INT_ENA = 0x80000000 + + // HP_INT_CLR: need_des + // Position of LP_CPU_EXC_INT_CLR field. + PMU_HP_INT_CLR_LP_CPU_EXC_INT_CLR_Pos = 0x1b + // Bit mask of LP_CPU_EXC_INT_CLR field. + PMU_HP_INT_CLR_LP_CPU_EXC_INT_CLR_Msk = 0x8000000 + // Bit LP_CPU_EXC_INT_CLR. + PMU_HP_INT_CLR_LP_CPU_EXC_INT_CLR = 0x8000000 + // Position of SDIO_IDLE_INT_CLR field. + PMU_HP_INT_CLR_SDIO_IDLE_INT_CLR_Pos = 0x1c + // Bit mask of SDIO_IDLE_INT_CLR field. + PMU_HP_INT_CLR_SDIO_IDLE_INT_CLR_Msk = 0x10000000 + // Bit SDIO_IDLE_INT_CLR. + PMU_HP_INT_CLR_SDIO_IDLE_INT_CLR = 0x10000000 + // Position of SW_INT_CLR field. + PMU_HP_INT_CLR_SW_INT_CLR_Pos = 0x1d + // Bit mask of SW_INT_CLR field. + PMU_HP_INT_CLR_SW_INT_CLR_Msk = 0x20000000 + // Bit SW_INT_CLR. + PMU_HP_INT_CLR_SW_INT_CLR = 0x20000000 + // Position of SOC_SLEEP_REJECT_INT_CLR field. + PMU_HP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR_Pos = 0x1e + // Bit mask of SOC_SLEEP_REJECT_INT_CLR field. + PMU_HP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR_Msk = 0x40000000 + // Bit SOC_SLEEP_REJECT_INT_CLR. + PMU_HP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR = 0x40000000 + // Position of SOC_WAKEUP_INT_CLR field. + PMU_HP_INT_CLR_SOC_WAKEUP_INT_CLR_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_CLR field. + PMU_HP_INT_CLR_SOC_WAKEUP_INT_CLR_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_CLR. + PMU_HP_INT_CLR_SOC_WAKEUP_INT_CLR = 0x80000000 + + // LP_INT_RAW: need_des + // Position of LP_CPU_WAKEUP_INT_RAW field. + PMU_LP_INT_RAW_LP_CPU_WAKEUP_INT_RAW_Pos = 0x14 + // Bit mask of LP_CPU_WAKEUP_INT_RAW field. + PMU_LP_INT_RAW_LP_CPU_WAKEUP_INT_RAW_Msk = 0x100000 + // Bit LP_CPU_WAKEUP_INT_RAW. + PMU_LP_INT_RAW_LP_CPU_WAKEUP_INT_RAW = 0x100000 + // Position of MODEM_SWITCH_ACTIVE_END_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW_Pos = 0x15 + // Bit mask of MODEM_SWITCH_ACTIVE_END_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW_Msk = 0x200000 + // Bit MODEM_SWITCH_ACTIVE_END_INT_RAW. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW = 0x200000 + // Position of SLEEP_SWITCH_ACTIVE_END_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW_Pos = 0x16 + // Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW_Msk = 0x400000 + // Bit SLEEP_SWITCH_ACTIVE_END_INT_RAW. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW = 0x400000 + // Position of SLEEP_SWITCH_MODEM_END_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW_Pos = 0x17 + // Bit mask of SLEEP_SWITCH_MODEM_END_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW_Msk = 0x800000 + // Bit SLEEP_SWITCH_MODEM_END_INT_RAW. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW = 0x800000 + // Position of MODEM_SWITCH_SLEEP_END_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW_Pos = 0x18 + // Bit mask of MODEM_SWITCH_SLEEP_END_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW_Msk = 0x1000000 + // Bit MODEM_SWITCH_SLEEP_END_INT_RAW. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW = 0x1000000 + // Position of ACTIVE_SWITCH_SLEEP_END_INT_RAW field. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW_Pos = 0x19 + // Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_RAW field. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW_Msk = 0x2000000 + // Bit ACTIVE_SWITCH_SLEEP_END_INT_RAW. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW = 0x2000000 + // Position of MODEM_SWITCH_ACTIVE_START_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW_Pos = 0x1a + // Bit mask of MODEM_SWITCH_ACTIVE_START_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW_Msk = 0x4000000 + // Bit MODEM_SWITCH_ACTIVE_START_INT_RAW. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW = 0x4000000 + // Position of SLEEP_SWITCH_ACTIVE_START_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW_Pos = 0x1b + // Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW_Msk = 0x8000000 + // Bit SLEEP_SWITCH_ACTIVE_START_INT_RAW. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW = 0x8000000 + // Position of SLEEP_SWITCH_MODEM_START_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW_Pos = 0x1c + // Bit mask of SLEEP_SWITCH_MODEM_START_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW_Msk = 0x10000000 + // Bit SLEEP_SWITCH_MODEM_START_INT_RAW. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW = 0x10000000 + // Position of MODEM_SWITCH_SLEEP_START_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW_Pos = 0x1d + // Bit mask of MODEM_SWITCH_SLEEP_START_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW_Msk = 0x20000000 + // Bit MODEM_SWITCH_SLEEP_START_INT_RAW. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW = 0x20000000 + // Position of ACTIVE_SWITCH_SLEEP_START_INT_RAW field. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW_Pos = 0x1e + // Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_RAW field. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW_Msk = 0x40000000 + // Bit ACTIVE_SWITCH_SLEEP_START_INT_RAW. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW = 0x40000000 + // Position of HP_SW_TRIGGER_INT_RAW field. + PMU_LP_INT_RAW_HP_SW_TRIGGER_INT_RAW_Pos = 0x1f + // Bit mask of HP_SW_TRIGGER_INT_RAW field. + PMU_LP_INT_RAW_HP_SW_TRIGGER_INT_RAW_Msk = 0x80000000 + // Bit HP_SW_TRIGGER_INT_RAW. + PMU_LP_INT_RAW_HP_SW_TRIGGER_INT_RAW = 0x80000000 + + // LP_INT_ST: need_des + // Position of LP_CPU_WAKEUP_INT_ST field. + PMU_LP_INT_ST_LP_CPU_WAKEUP_INT_ST_Pos = 0x14 + // Bit mask of LP_CPU_WAKEUP_INT_ST field. + PMU_LP_INT_ST_LP_CPU_WAKEUP_INT_ST_Msk = 0x100000 + // Bit LP_CPU_WAKEUP_INT_ST. + PMU_LP_INT_ST_LP_CPU_WAKEUP_INT_ST = 0x100000 + // Position of MODEM_SWITCH_ACTIVE_END_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST_Pos = 0x15 + // Bit mask of MODEM_SWITCH_ACTIVE_END_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST_Msk = 0x200000 + // Bit MODEM_SWITCH_ACTIVE_END_INT_ST. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST = 0x200000 + // Position of SLEEP_SWITCH_ACTIVE_END_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST_Pos = 0x16 + // Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST_Msk = 0x400000 + // Bit SLEEP_SWITCH_ACTIVE_END_INT_ST. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST = 0x400000 + // Position of SLEEP_SWITCH_MODEM_END_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST_Pos = 0x17 + // Bit mask of SLEEP_SWITCH_MODEM_END_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST_Msk = 0x800000 + // Bit SLEEP_SWITCH_MODEM_END_INT_ST. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST = 0x800000 + // Position of MODEM_SWITCH_SLEEP_END_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST_Pos = 0x18 + // Bit mask of MODEM_SWITCH_SLEEP_END_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST_Msk = 0x1000000 + // Bit MODEM_SWITCH_SLEEP_END_INT_ST. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST = 0x1000000 + // Position of ACTIVE_SWITCH_SLEEP_END_INT_ST field. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST_Pos = 0x19 + // Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_ST field. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST_Msk = 0x2000000 + // Bit ACTIVE_SWITCH_SLEEP_END_INT_ST. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST = 0x2000000 + // Position of MODEM_SWITCH_ACTIVE_START_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST_Pos = 0x1a + // Bit mask of MODEM_SWITCH_ACTIVE_START_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST_Msk = 0x4000000 + // Bit MODEM_SWITCH_ACTIVE_START_INT_ST. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST = 0x4000000 + // Position of SLEEP_SWITCH_ACTIVE_START_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST_Pos = 0x1b + // Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST_Msk = 0x8000000 + // Bit SLEEP_SWITCH_ACTIVE_START_INT_ST. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST = 0x8000000 + // Position of SLEEP_SWITCH_MODEM_START_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST_Pos = 0x1c + // Bit mask of SLEEP_SWITCH_MODEM_START_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST_Msk = 0x10000000 + // Bit SLEEP_SWITCH_MODEM_START_INT_ST. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST = 0x10000000 + // Position of MODEM_SWITCH_SLEEP_START_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST_Pos = 0x1d + // Bit mask of MODEM_SWITCH_SLEEP_START_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST_Msk = 0x20000000 + // Bit MODEM_SWITCH_SLEEP_START_INT_ST. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST = 0x20000000 + // Position of ACTIVE_SWITCH_SLEEP_START_INT_ST field. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST_Pos = 0x1e + // Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_ST field. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST_Msk = 0x40000000 + // Bit ACTIVE_SWITCH_SLEEP_START_INT_ST. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST = 0x40000000 + // Position of HP_SW_TRIGGER_INT_ST field. + PMU_LP_INT_ST_HP_SW_TRIGGER_INT_ST_Pos = 0x1f + // Bit mask of HP_SW_TRIGGER_INT_ST field. + PMU_LP_INT_ST_HP_SW_TRIGGER_INT_ST_Msk = 0x80000000 + // Bit HP_SW_TRIGGER_INT_ST. + PMU_LP_INT_ST_HP_SW_TRIGGER_INT_ST = 0x80000000 + + // LP_INT_ENA: need_des + // Position of LP_CPU_WAKEUP_INT_ENA field. + PMU_LP_INT_ENA_LP_CPU_WAKEUP_INT_ENA_Pos = 0x14 + // Bit mask of LP_CPU_WAKEUP_INT_ENA field. + PMU_LP_INT_ENA_LP_CPU_WAKEUP_INT_ENA_Msk = 0x100000 + // Bit LP_CPU_WAKEUP_INT_ENA. + PMU_LP_INT_ENA_LP_CPU_WAKEUP_INT_ENA = 0x100000 + // Position of MODEM_SWITCH_ACTIVE_END_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA_Pos = 0x15 + // Bit mask of MODEM_SWITCH_ACTIVE_END_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA_Msk = 0x200000 + // Bit MODEM_SWITCH_ACTIVE_END_INT_ENA. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA = 0x200000 + // Position of SLEEP_SWITCH_ACTIVE_END_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA_Pos = 0x16 + // Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA_Msk = 0x400000 + // Bit SLEEP_SWITCH_ACTIVE_END_INT_ENA. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA = 0x400000 + // Position of SLEEP_SWITCH_MODEM_END_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA_Pos = 0x17 + // Bit mask of SLEEP_SWITCH_MODEM_END_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA_Msk = 0x800000 + // Bit SLEEP_SWITCH_MODEM_END_INT_ENA. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA = 0x800000 + // Position of MODEM_SWITCH_SLEEP_END_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA_Pos = 0x18 + // Bit mask of MODEM_SWITCH_SLEEP_END_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA_Msk = 0x1000000 + // Bit MODEM_SWITCH_SLEEP_END_INT_ENA. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA = 0x1000000 + // Position of ACTIVE_SWITCH_SLEEP_END_INT_ENA field. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA_Pos = 0x19 + // Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_ENA field. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA_Msk = 0x2000000 + // Bit ACTIVE_SWITCH_SLEEP_END_INT_ENA. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA = 0x2000000 + // Position of MODEM_SWITCH_ACTIVE_START_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA_Pos = 0x1a + // Bit mask of MODEM_SWITCH_ACTIVE_START_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA_Msk = 0x4000000 + // Bit MODEM_SWITCH_ACTIVE_START_INT_ENA. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA = 0x4000000 + // Position of SLEEP_SWITCH_ACTIVE_START_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA_Pos = 0x1b + // Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA_Msk = 0x8000000 + // Bit SLEEP_SWITCH_ACTIVE_START_INT_ENA. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA = 0x8000000 + // Position of SLEEP_SWITCH_MODEM_START_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA_Pos = 0x1c + // Bit mask of SLEEP_SWITCH_MODEM_START_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA_Msk = 0x10000000 + // Bit SLEEP_SWITCH_MODEM_START_INT_ENA. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA = 0x10000000 + // Position of MODEM_SWITCH_SLEEP_START_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA_Pos = 0x1d + // Bit mask of MODEM_SWITCH_SLEEP_START_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA_Msk = 0x20000000 + // Bit MODEM_SWITCH_SLEEP_START_INT_ENA. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA = 0x20000000 + // Position of ACTIVE_SWITCH_SLEEP_START_INT_ENA field. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA_Pos = 0x1e + // Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_ENA field. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA_Msk = 0x40000000 + // Bit ACTIVE_SWITCH_SLEEP_START_INT_ENA. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA = 0x40000000 + // Position of HP_SW_TRIGGER_INT_ENA field. + PMU_LP_INT_ENA_HP_SW_TRIGGER_INT_ENA_Pos = 0x1f + // Bit mask of HP_SW_TRIGGER_INT_ENA field. + PMU_LP_INT_ENA_HP_SW_TRIGGER_INT_ENA_Msk = 0x80000000 + // Bit HP_SW_TRIGGER_INT_ENA. + PMU_LP_INT_ENA_HP_SW_TRIGGER_INT_ENA = 0x80000000 + + // LP_INT_CLR: need_des + // Position of LP_CPU_WAKEUP_INT_CLR field. + PMU_LP_INT_CLR_LP_CPU_WAKEUP_INT_CLR_Pos = 0x14 + // Bit mask of LP_CPU_WAKEUP_INT_CLR field. + PMU_LP_INT_CLR_LP_CPU_WAKEUP_INT_CLR_Msk = 0x100000 + // Bit LP_CPU_WAKEUP_INT_CLR. + PMU_LP_INT_CLR_LP_CPU_WAKEUP_INT_CLR = 0x100000 + // Position of MODEM_SWITCH_ACTIVE_END_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR_Pos = 0x15 + // Bit mask of MODEM_SWITCH_ACTIVE_END_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR_Msk = 0x200000 + // Bit MODEM_SWITCH_ACTIVE_END_INT_CLR. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR = 0x200000 + // Position of SLEEP_SWITCH_ACTIVE_END_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR_Pos = 0x16 + // Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR_Msk = 0x400000 + // Bit SLEEP_SWITCH_ACTIVE_END_INT_CLR. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR = 0x400000 + // Position of SLEEP_SWITCH_MODEM_END_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR_Pos = 0x17 + // Bit mask of SLEEP_SWITCH_MODEM_END_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR_Msk = 0x800000 + // Bit SLEEP_SWITCH_MODEM_END_INT_CLR. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR = 0x800000 + // Position of MODEM_SWITCH_SLEEP_END_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR_Pos = 0x18 + // Bit mask of MODEM_SWITCH_SLEEP_END_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR_Msk = 0x1000000 + // Bit MODEM_SWITCH_SLEEP_END_INT_CLR. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR = 0x1000000 + // Position of ACTIVE_SWITCH_SLEEP_END_INT_CLR field. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR_Pos = 0x19 + // Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_CLR field. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR_Msk = 0x2000000 + // Bit ACTIVE_SWITCH_SLEEP_END_INT_CLR. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR = 0x2000000 + // Position of MODEM_SWITCH_ACTIVE_START_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR_Pos = 0x1a + // Bit mask of MODEM_SWITCH_ACTIVE_START_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR_Msk = 0x4000000 + // Bit MODEM_SWITCH_ACTIVE_START_INT_CLR. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR = 0x4000000 + // Position of SLEEP_SWITCH_ACTIVE_START_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR_Pos = 0x1b + // Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR_Msk = 0x8000000 + // Bit SLEEP_SWITCH_ACTIVE_START_INT_CLR. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR = 0x8000000 + // Position of SLEEP_SWITCH_MODEM_START_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR_Pos = 0x1c + // Bit mask of SLEEP_SWITCH_MODEM_START_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR_Msk = 0x10000000 + // Bit SLEEP_SWITCH_MODEM_START_INT_CLR. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR = 0x10000000 + // Position of MODEM_SWITCH_SLEEP_START_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR_Pos = 0x1d + // Bit mask of MODEM_SWITCH_SLEEP_START_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR_Msk = 0x20000000 + // Bit MODEM_SWITCH_SLEEP_START_INT_CLR. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR = 0x20000000 + // Position of ACTIVE_SWITCH_SLEEP_START_INT_CLR field. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR_Pos = 0x1e + // Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_CLR field. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR_Msk = 0x40000000 + // Bit ACTIVE_SWITCH_SLEEP_START_INT_CLR. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR = 0x40000000 + // Position of HP_SW_TRIGGER_INT_CLR field. + PMU_LP_INT_CLR_HP_SW_TRIGGER_INT_CLR_Pos = 0x1f + // Bit mask of HP_SW_TRIGGER_INT_CLR field. + PMU_LP_INT_CLR_HP_SW_TRIGGER_INT_CLR_Msk = 0x80000000 + // Bit HP_SW_TRIGGER_INT_CLR. + PMU_LP_INT_CLR_HP_SW_TRIGGER_INT_CLR = 0x80000000 + + // LP_CPU_PWR0: need_des + // Position of LP_CPU_WAITI_RDY field. + PMU_LP_CPU_PWR0_LP_CPU_WAITI_RDY_Pos = 0x0 + // Bit mask of LP_CPU_WAITI_RDY field. + PMU_LP_CPU_PWR0_LP_CPU_WAITI_RDY_Msk = 0x1 + // Bit LP_CPU_WAITI_RDY. + PMU_LP_CPU_PWR0_LP_CPU_WAITI_RDY = 0x1 + // Position of LP_CPU_STALL_RDY field. + PMU_LP_CPU_PWR0_LP_CPU_STALL_RDY_Pos = 0x1 + // Bit mask of LP_CPU_STALL_RDY field. + PMU_LP_CPU_PWR0_LP_CPU_STALL_RDY_Msk = 0x2 + // Bit LP_CPU_STALL_RDY. + PMU_LP_CPU_PWR0_LP_CPU_STALL_RDY = 0x2 + // Position of LP_CPU_FORCE_STALL field. + PMU_LP_CPU_PWR0_LP_CPU_FORCE_STALL_Pos = 0x12 + // Bit mask of LP_CPU_FORCE_STALL field. + PMU_LP_CPU_PWR0_LP_CPU_FORCE_STALL_Msk = 0x40000 + // Bit LP_CPU_FORCE_STALL. + PMU_LP_CPU_PWR0_LP_CPU_FORCE_STALL = 0x40000 + // Position of LP_CPU_SLP_WAITI_FLAG_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN_Pos = 0x13 + // Bit mask of LP_CPU_SLP_WAITI_FLAG_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN_Msk = 0x80000 + // Bit LP_CPU_SLP_WAITI_FLAG_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN = 0x80000 + // Position of LP_CPU_SLP_STALL_FLAG_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN_Pos = 0x14 + // Bit mask of LP_CPU_SLP_STALL_FLAG_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN_Msk = 0x100000 + // Bit LP_CPU_SLP_STALL_FLAG_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN = 0x100000 + // Position of LP_CPU_SLP_STALL_WAIT field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT_Pos = 0x15 + // Bit mask of LP_CPU_SLP_STALL_WAIT field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT_Msk = 0x1fe00000 + // Position of LP_CPU_SLP_STALL_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_EN_Pos = 0x1d + // Bit mask of LP_CPU_SLP_STALL_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_EN_Msk = 0x20000000 + // Bit LP_CPU_SLP_STALL_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_EN = 0x20000000 + // Position of LP_CPU_SLP_RESET_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_RESET_EN_Pos = 0x1e + // Bit mask of LP_CPU_SLP_RESET_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_RESET_EN_Msk = 0x40000000 + // Bit LP_CPU_SLP_RESET_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_RESET_EN = 0x40000000 + // Position of LP_CPU_SLP_BYPASS_INTR_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN_Pos = 0x1f + // Bit mask of LP_CPU_SLP_BYPASS_INTR_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN_Msk = 0x80000000 + // Bit LP_CPU_SLP_BYPASS_INTR_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN = 0x80000000 + + // LP_CPU_PWR1: need_des + // Position of LP_CPU_WAKEUP_EN field. + PMU_LP_CPU_PWR1_LP_CPU_WAKEUP_EN_Pos = 0x0 + // Bit mask of LP_CPU_WAKEUP_EN field. + PMU_LP_CPU_PWR1_LP_CPU_WAKEUP_EN_Msk = 0xffff + // Position of LP_CPU_SLEEP_REQ field. + PMU_LP_CPU_PWR1_LP_CPU_SLEEP_REQ_Pos = 0x1f + // Bit mask of LP_CPU_SLEEP_REQ field. + PMU_LP_CPU_PWR1_LP_CPU_SLEEP_REQ_Msk = 0x80000000 + // Bit LP_CPU_SLEEP_REQ. + PMU_LP_CPU_PWR1_LP_CPU_SLEEP_REQ = 0x80000000 + + // HP_LP_CPU_COMM: need_des + // Position of LP_TRIGGER_HP field. + PMU_HP_LP_CPU_COMM_LP_TRIGGER_HP_Pos = 0x1e + // Bit mask of LP_TRIGGER_HP field. + PMU_HP_LP_CPU_COMM_LP_TRIGGER_HP_Msk = 0x40000000 + // Bit LP_TRIGGER_HP. + PMU_HP_LP_CPU_COMM_LP_TRIGGER_HP = 0x40000000 + // Position of HP_TRIGGER_LP field. + PMU_HP_LP_CPU_COMM_HP_TRIGGER_LP_Pos = 0x1f + // Bit mask of HP_TRIGGER_LP field. + PMU_HP_LP_CPU_COMM_HP_TRIGGER_LP_Msk = 0x80000000 + // Bit HP_TRIGGER_LP. + PMU_HP_LP_CPU_COMM_HP_TRIGGER_LP = 0x80000000 + + // HP_REGULATOR_CFG: need_des + // Position of DIG_REGULATOR_EN_CAL field. + PMU_HP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL_Pos = 0x1f + // Bit mask of DIG_REGULATOR_EN_CAL field. + PMU_HP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL_Msk = 0x80000000 + // Bit DIG_REGULATOR_EN_CAL. + PMU_HP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL = 0x80000000 + + // MAIN_STATE: need_des + // Position of MAIN_LAST_ST_STATE field. + PMU_MAIN_STATE_MAIN_LAST_ST_STATE_Pos = 0xb + // Bit mask of MAIN_LAST_ST_STATE field. + PMU_MAIN_STATE_MAIN_LAST_ST_STATE_Msk = 0x3f800 + // Position of MAIN_TAR_ST_STATE field. + PMU_MAIN_STATE_MAIN_TAR_ST_STATE_Pos = 0x12 + // Bit mask of MAIN_TAR_ST_STATE field. + PMU_MAIN_STATE_MAIN_TAR_ST_STATE_Msk = 0x1fc0000 + // Position of MAIN_CUR_ST_STATE field. + PMU_MAIN_STATE_MAIN_CUR_ST_STATE_Pos = 0x19 + // Bit mask of MAIN_CUR_ST_STATE field. + PMU_MAIN_STATE_MAIN_CUR_ST_STATE_Msk = 0xfe000000 + + // PWR_STATE: need_des + // Position of BACKUP_ST_STATE field. + PMU_PWR_STATE_BACKUP_ST_STATE_Pos = 0xd + // Bit mask of BACKUP_ST_STATE field. + PMU_PWR_STATE_BACKUP_ST_STATE_Msk = 0x3e000 + // Position of LP_PWR_ST_STATE field. + PMU_PWR_STATE_LP_PWR_ST_STATE_Pos = 0x12 + // Bit mask of LP_PWR_ST_STATE field. + PMU_PWR_STATE_LP_PWR_ST_STATE_Msk = 0x7c0000 + // Position of HP_PWR_ST_STATE field. + PMU_PWR_STATE_HP_PWR_ST_STATE_Pos = 0x17 + // Bit mask of HP_PWR_ST_STATE field. + PMU_PWR_STATE_HP_PWR_ST_STATE_Msk = 0xff800000 + + // CLK_STATE0: need_des + // Position of STABLE_XPD_BBPLL_STATE field. + PMU_CLK_STATE0_STABLE_XPD_BBPLL_STATE_Pos = 0x0 + // Bit mask of STABLE_XPD_BBPLL_STATE field. + PMU_CLK_STATE0_STABLE_XPD_BBPLL_STATE_Msk = 0x1 + // Bit STABLE_XPD_BBPLL_STATE. + PMU_CLK_STATE0_STABLE_XPD_BBPLL_STATE = 0x1 + // Position of STABLE_XPD_XTAL_STATE field. + PMU_CLK_STATE0_STABLE_XPD_XTAL_STATE_Pos = 0x1 + // Bit mask of STABLE_XPD_XTAL_STATE field. + PMU_CLK_STATE0_STABLE_XPD_XTAL_STATE_Msk = 0x2 + // Bit STABLE_XPD_XTAL_STATE. + PMU_CLK_STATE0_STABLE_XPD_XTAL_STATE = 0x2 + // Position of SYS_CLK_SLP_SEL_STATE field. + PMU_CLK_STATE0_SYS_CLK_SLP_SEL_STATE_Pos = 0xf + // Bit mask of SYS_CLK_SLP_SEL_STATE field. + PMU_CLK_STATE0_SYS_CLK_SLP_SEL_STATE_Msk = 0x8000 + // Bit SYS_CLK_SLP_SEL_STATE. + PMU_CLK_STATE0_SYS_CLK_SLP_SEL_STATE = 0x8000 + // Position of SYS_CLK_SEL_STATE field. + PMU_CLK_STATE0_SYS_CLK_SEL_STATE_Pos = 0x10 + // Bit mask of SYS_CLK_SEL_STATE field. + PMU_CLK_STATE0_SYS_CLK_SEL_STATE_Msk = 0x30000 + // Position of SYS_CLK_NO_DIV_STATE field. + PMU_CLK_STATE0_SYS_CLK_NO_DIV_STATE_Pos = 0x12 + // Bit mask of SYS_CLK_NO_DIV_STATE field. + PMU_CLK_STATE0_SYS_CLK_NO_DIV_STATE_Msk = 0x40000 + // Bit SYS_CLK_NO_DIV_STATE. + PMU_CLK_STATE0_SYS_CLK_NO_DIV_STATE = 0x40000 + // Position of ICG_SYS_CLK_EN_STATE field. + PMU_CLK_STATE0_ICG_SYS_CLK_EN_STATE_Pos = 0x13 + // Bit mask of ICG_SYS_CLK_EN_STATE field. + PMU_CLK_STATE0_ICG_SYS_CLK_EN_STATE_Msk = 0x80000 + // Bit ICG_SYS_CLK_EN_STATE. + PMU_CLK_STATE0_ICG_SYS_CLK_EN_STATE = 0x80000 + // Position of ICG_MODEM_SWITCH_STATE field. + PMU_CLK_STATE0_ICG_MODEM_SWITCH_STATE_Pos = 0x14 + // Bit mask of ICG_MODEM_SWITCH_STATE field. + PMU_CLK_STATE0_ICG_MODEM_SWITCH_STATE_Msk = 0x100000 + // Bit ICG_MODEM_SWITCH_STATE. + PMU_CLK_STATE0_ICG_MODEM_SWITCH_STATE = 0x100000 + // Position of ICG_MODEM_CODE_STATE field. + PMU_CLK_STATE0_ICG_MODEM_CODE_STATE_Pos = 0x15 + // Bit mask of ICG_MODEM_CODE_STATE field. + PMU_CLK_STATE0_ICG_MODEM_CODE_STATE_Msk = 0x600000 + // Position of ICG_SLP_SEL_STATE field. + PMU_CLK_STATE0_ICG_SLP_SEL_STATE_Pos = 0x17 + // Bit mask of ICG_SLP_SEL_STATE field. + PMU_CLK_STATE0_ICG_SLP_SEL_STATE_Msk = 0x800000 + // Bit ICG_SLP_SEL_STATE. + PMU_CLK_STATE0_ICG_SLP_SEL_STATE = 0x800000 + // Position of ICG_GLOBAL_XTAL_STATE field. + PMU_CLK_STATE0_ICG_GLOBAL_XTAL_STATE_Pos = 0x18 + // Bit mask of ICG_GLOBAL_XTAL_STATE field. + PMU_CLK_STATE0_ICG_GLOBAL_XTAL_STATE_Msk = 0x1000000 + // Bit ICG_GLOBAL_XTAL_STATE. + PMU_CLK_STATE0_ICG_GLOBAL_XTAL_STATE = 0x1000000 + // Position of ICG_GLOBAL_PLL_STATE field. + PMU_CLK_STATE0_ICG_GLOBAL_PLL_STATE_Pos = 0x19 + // Bit mask of ICG_GLOBAL_PLL_STATE field. + PMU_CLK_STATE0_ICG_GLOBAL_PLL_STATE_Msk = 0x2000000 + // Bit ICG_GLOBAL_PLL_STATE. + PMU_CLK_STATE0_ICG_GLOBAL_PLL_STATE = 0x2000000 + // Position of ANA_I2C_ISO_EN_STATE field. + PMU_CLK_STATE0_ANA_I2C_ISO_EN_STATE_Pos = 0x1a + // Bit mask of ANA_I2C_ISO_EN_STATE field. + PMU_CLK_STATE0_ANA_I2C_ISO_EN_STATE_Msk = 0x4000000 + // Bit ANA_I2C_ISO_EN_STATE. + PMU_CLK_STATE0_ANA_I2C_ISO_EN_STATE = 0x4000000 + // Position of ANA_I2C_RETENTION_STATE field. + PMU_CLK_STATE0_ANA_I2C_RETENTION_STATE_Pos = 0x1b + // Bit mask of ANA_I2C_RETENTION_STATE field. + PMU_CLK_STATE0_ANA_I2C_RETENTION_STATE_Msk = 0x8000000 + // Bit ANA_I2C_RETENTION_STATE. + PMU_CLK_STATE0_ANA_I2C_RETENTION_STATE = 0x8000000 + // Position of ANA_XPD_BB_I2C_STATE field. + PMU_CLK_STATE0_ANA_XPD_BB_I2C_STATE_Pos = 0x1c + // Bit mask of ANA_XPD_BB_I2C_STATE field. + PMU_CLK_STATE0_ANA_XPD_BB_I2C_STATE_Msk = 0x10000000 + // Bit ANA_XPD_BB_I2C_STATE. + PMU_CLK_STATE0_ANA_XPD_BB_I2C_STATE = 0x10000000 + // Position of ANA_XPD_BBPLL_I2C_STATE field. + PMU_CLK_STATE0_ANA_XPD_BBPLL_I2C_STATE_Pos = 0x1d + // Bit mask of ANA_XPD_BBPLL_I2C_STATE field. + PMU_CLK_STATE0_ANA_XPD_BBPLL_I2C_STATE_Msk = 0x20000000 + // Bit ANA_XPD_BBPLL_I2C_STATE. + PMU_CLK_STATE0_ANA_XPD_BBPLL_I2C_STATE = 0x20000000 + // Position of ANA_XPD_BBPLL_STATE field. + PMU_CLK_STATE0_ANA_XPD_BBPLL_STATE_Pos = 0x1e + // Bit mask of ANA_XPD_BBPLL_STATE field. + PMU_CLK_STATE0_ANA_XPD_BBPLL_STATE_Msk = 0x40000000 + // Bit ANA_XPD_BBPLL_STATE. + PMU_CLK_STATE0_ANA_XPD_BBPLL_STATE = 0x40000000 + // Position of ANA_XPD_XTAL_STATE field. + PMU_CLK_STATE0_ANA_XPD_XTAL_STATE_Pos = 0x1f + // Bit mask of ANA_XPD_XTAL_STATE field. + PMU_CLK_STATE0_ANA_XPD_XTAL_STATE_Msk = 0x80000000 + // Bit ANA_XPD_XTAL_STATE. + PMU_CLK_STATE0_ANA_XPD_XTAL_STATE = 0x80000000 + + // CLK_STATE1: need_des + // Position of ICG_FUNC_EN_STATE field. + PMU_CLK_STATE1_ICG_FUNC_EN_STATE_Pos = 0x0 + // Bit mask of ICG_FUNC_EN_STATE field. + PMU_CLK_STATE1_ICG_FUNC_EN_STATE_Msk = 0xffffffff + + // CLK_STATE2: need_des + // Position of ICG_APB_EN_STATE field. + PMU_CLK_STATE2_ICG_APB_EN_STATE_Pos = 0x0 + // Bit mask of ICG_APB_EN_STATE field. + PMU_CLK_STATE2_ICG_APB_EN_STATE_Msk = 0xffffffff + + // VDD_SPI_STATUS: need_des + // Position of STABLE_VDD_SPI_PWR_DRV field. + PMU_VDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV_Pos = 0x1f + // Bit mask of STABLE_VDD_SPI_PWR_DRV field. + PMU_VDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV_Msk = 0x80000000 + // Bit STABLE_VDD_SPI_PWR_DRV. + PMU_VDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV = 0x80000000 + + // DATE: need_des + // Position of PMU_DATE field. + PMU_DATE_PMU_DATE_Pos = 0x0 + // Bit mask of PMU_DATE field. + PMU_DATE_PMU_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + PMU_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + PMU_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + PMU_DATE_CLK_EN = 0x80000000 +) + +// Constants for RMT: Remote Control +const ( + // CH0DATA: The read and write data register for CHANNEL%s by apb fifo access. + // Position of DATA field. + RMT_CHDATA_DATA_Pos = 0x0 + // Bit mask of DATA field. + RMT_CHDATA_DATA_Msk = 0xffffffff + + // CH0_TX_CONF0: Channel %s configure register 0 + // Position of TX_START field. + RMT_CH_TX_CONF0_TX_START_Pos = 0x0 + // Bit mask of TX_START field. + RMT_CH_TX_CONF0_TX_START_Msk = 0x1 + // Bit TX_START. + RMT_CH_TX_CONF0_TX_START = 0x1 + // Position of MEM_RD_RST field. + RMT_CH_TX_CONF0_MEM_RD_RST_Pos = 0x1 + // Bit mask of MEM_RD_RST field. + RMT_CH_TX_CONF0_MEM_RD_RST_Msk = 0x2 + // Bit MEM_RD_RST. + RMT_CH_TX_CONF0_MEM_RD_RST = 0x2 + // Position of APB_MEM_RST field. + RMT_CH_TX_CONF0_APB_MEM_RST_Pos = 0x2 + // Bit mask of APB_MEM_RST field. + RMT_CH_TX_CONF0_APB_MEM_RST_Msk = 0x4 + // Bit APB_MEM_RST. + RMT_CH_TX_CONF0_APB_MEM_RST = 0x4 + // Position of TX_CONTI_MODE field. + RMT_CH_TX_CONF0_TX_CONTI_MODE_Pos = 0x3 + // Bit mask of TX_CONTI_MODE field. + RMT_CH_TX_CONF0_TX_CONTI_MODE_Msk = 0x8 + // Bit TX_CONTI_MODE. + RMT_CH_TX_CONF0_TX_CONTI_MODE = 0x8 + // Position of MEM_TX_WRAP_EN field. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN_Pos = 0x4 + // Bit mask of MEM_TX_WRAP_EN field. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN_Msk = 0x10 + // Bit MEM_TX_WRAP_EN. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN = 0x10 + // Position of IDLE_OUT_LV field. + RMT_CH_TX_CONF0_IDLE_OUT_LV_Pos = 0x5 + // Bit mask of IDLE_OUT_LV field. + RMT_CH_TX_CONF0_IDLE_OUT_LV_Msk = 0x20 + // Bit IDLE_OUT_LV. + RMT_CH_TX_CONF0_IDLE_OUT_LV = 0x20 + // Position of IDLE_OUT_EN field. + RMT_CH_TX_CONF0_IDLE_OUT_EN_Pos = 0x6 + // Bit mask of IDLE_OUT_EN field. + RMT_CH_TX_CONF0_IDLE_OUT_EN_Msk = 0x40 + // Bit IDLE_OUT_EN. + RMT_CH_TX_CONF0_IDLE_OUT_EN = 0x40 + // Position of TX_STOP field. + RMT_CH_TX_CONF0_TX_STOP_Pos = 0x7 + // Bit mask of TX_STOP field. + RMT_CH_TX_CONF0_TX_STOP_Msk = 0x80 + // Bit TX_STOP. + RMT_CH_TX_CONF0_TX_STOP = 0x80 + // Position of DIV_CNT field. + RMT_CH_TX_CONF0_DIV_CNT_Pos = 0x8 + // Bit mask of DIV_CNT field. + RMT_CH_TX_CONF0_DIV_CNT_Msk = 0xff00 + // Position of MEM_SIZE field. + RMT_CH_TX_CONF0_MEM_SIZE_Pos = 0x10 + // Bit mask of MEM_SIZE field. + RMT_CH_TX_CONF0_MEM_SIZE_Msk = 0x70000 + // Position of CARRIER_EFF_EN field. + RMT_CH_TX_CONF0_CARRIER_EFF_EN_Pos = 0x14 + // Bit mask of CARRIER_EFF_EN field. + RMT_CH_TX_CONF0_CARRIER_EFF_EN_Msk = 0x100000 + // Bit CARRIER_EFF_EN. + RMT_CH_TX_CONF0_CARRIER_EFF_EN = 0x100000 + // Position of CARRIER_EN field. + RMT_CH_TX_CONF0_CARRIER_EN_Pos = 0x15 + // Bit mask of CARRIER_EN field. + RMT_CH_TX_CONF0_CARRIER_EN_Msk = 0x200000 + // Bit CARRIER_EN. + RMT_CH_TX_CONF0_CARRIER_EN = 0x200000 + // Position of CARRIER_OUT_LV field. + RMT_CH_TX_CONF0_CARRIER_OUT_LV_Pos = 0x16 + // Bit mask of CARRIER_OUT_LV field. + RMT_CH_TX_CONF0_CARRIER_OUT_LV_Msk = 0x400000 + // Bit CARRIER_OUT_LV. + RMT_CH_TX_CONF0_CARRIER_OUT_LV = 0x400000 + // Position of AFIFO_RST field. + RMT_CH_TX_CONF0_AFIFO_RST_Pos = 0x17 + // Bit mask of AFIFO_RST field. + RMT_CH_TX_CONF0_AFIFO_RST_Msk = 0x800000 + // Bit AFIFO_RST. + RMT_CH_TX_CONF0_AFIFO_RST = 0x800000 + // Position of CONF_UPDATE field. + RMT_CH_TX_CONF0_CONF_UPDATE_Pos = 0x18 + // Bit mask of CONF_UPDATE field. + RMT_CH_TX_CONF0_CONF_UPDATE_Msk = 0x1000000 + // Bit CONF_UPDATE. + RMT_CH_TX_CONF0_CONF_UPDATE = 0x1000000 + + // CH2_RX_CONF0: Channel %s configure register 0 + // Position of DIV_CNT field. + RMT_CH_RX_CONF0_DIV_CNT_Pos = 0x0 + // Bit mask of DIV_CNT field. + RMT_CH_RX_CONF0_DIV_CNT_Msk = 0xff + // Position of IDLE_THRES field. + RMT_CH_RX_CONF0_IDLE_THRES_Pos = 0x8 + // Bit mask of IDLE_THRES field. + RMT_CH_RX_CONF0_IDLE_THRES_Msk = 0x7fff00 + // Position of MEM_SIZE field. + RMT_CH_RX_CONF0_MEM_SIZE_Pos = 0x17 + // Bit mask of MEM_SIZE field. + RMT_CH_RX_CONF0_MEM_SIZE_Msk = 0x3800000 + // Position of CARRIER_EN field. + RMT_CH_RX_CONF0_CARRIER_EN_Pos = 0x1c + // Bit mask of CARRIER_EN field. + RMT_CH_RX_CONF0_CARRIER_EN_Msk = 0x10000000 + // Bit CARRIER_EN. + RMT_CH_RX_CONF0_CARRIER_EN = 0x10000000 + // Position of CARRIER_OUT_LV field. + RMT_CH_RX_CONF0_CARRIER_OUT_LV_Pos = 0x1d + // Bit mask of CARRIER_OUT_LV field. + RMT_CH_RX_CONF0_CARRIER_OUT_LV_Msk = 0x20000000 + // Bit CARRIER_OUT_LV. + RMT_CH_RX_CONF0_CARRIER_OUT_LV = 0x20000000 + + // CH2_RX_CONF1: Channel %s configure register 1 + // Position of RX_EN field. + RMT_CH_RX_CONF1_RX_EN_Pos = 0x0 + // Bit mask of RX_EN field. + RMT_CH_RX_CONF1_RX_EN_Msk = 0x1 + // Bit RX_EN. + RMT_CH_RX_CONF1_RX_EN = 0x1 + // Position of MEM_WR_RST field. + RMT_CH_RX_CONF1_MEM_WR_RST_Pos = 0x1 + // Bit mask of MEM_WR_RST field. + RMT_CH_RX_CONF1_MEM_WR_RST_Msk = 0x2 + // Bit MEM_WR_RST. + RMT_CH_RX_CONF1_MEM_WR_RST = 0x2 + // Position of APB_MEM_RST field. + RMT_CH_RX_CONF1_APB_MEM_RST_Pos = 0x2 + // Bit mask of APB_MEM_RST field. + RMT_CH_RX_CONF1_APB_MEM_RST_Msk = 0x4 + // Bit APB_MEM_RST. + RMT_CH_RX_CONF1_APB_MEM_RST = 0x4 + // Position of MEM_OWNER field. + RMT_CH_RX_CONF1_MEM_OWNER_Pos = 0x3 + // Bit mask of MEM_OWNER field. + RMT_CH_RX_CONF1_MEM_OWNER_Msk = 0x8 + // Bit MEM_OWNER. + RMT_CH_RX_CONF1_MEM_OWNER = 0x8 + // Position of RX_FILTER_EN field. + RMT_CH_RX_CONF1_RX_FILTER_EN_Pos = 0x4 + // Bit mask of RX_FILTER_EN field. + RMT_CH_RX_CONF1_RX_FILTER_EN_Msk = 0x10 + // Bit RX_FILTER_EN. + RMT_CH_RX_CONF1_RX_FILTER_EN = 0x10 + // Position of RX_FILTER_THRES field. + RMT_CH_RX_CONF1_RX_FILTER_THRES_Pos = 0x5 + // Bit mask of RX_FILTER_THRES field. + RMT_CH_RX_CONF1_RX_FILTER_THRES_Msk = 0x1fe0 + // Position of MEM_RX_WRAP_EN field. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN_Pos = 0xd + // Bit mask of MEM_RX_WRAP_EN field. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN_Msk = 0x2000 + // Bit MEM_RX_WRAP_EN. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN = 0x2000 + // Position of AFIFO_RST field. + RMT_CH_RX_CONF1_AFIFO_RST_Pos = 0xe + // Bit mask of AFIFO_RST field. + RMT_CH_RX_CONF1_AFIFO_RST_Msk = 0x4000 + // Bit AFIFO_RST. + RMT_CH_RX_CONF1_AFIFO_RST = 0x4000 + // Position of CONF_UPDATE field. + RMT_CH_RX_CONF1_CONF_UPDATE_Pos = 0xf + // Bit mask of CONF_UPDATE field. + RMT_CH_RX_CONF1_CONF_UPDATE_Msk = 0x8000 + // Bit CONF_UPDATE. + RMT_CH_RX_CONF1_CONF_UPDATE = 0x8000 + + // CH0_TX_STATUS: Channel %s status register + // Position of MEM_RADDR_EX field. + RMT_CH_TX_STATUS_MEM_RADDR_EX_Pos = 0x0 + // Bit mask of MEM_RADDR_EX field. + RMT_CH_TX_STATUS_MEM_RADDR_EX_Msk = 0x1ff + // Position of STATE field. + RMT_CH_TX_STATUS_STATE_Pos = 0x9 + // Bit mask of STATE field. + RMT_CH_TX_STATUS_STATE_Msk = 0xe00 + // Position of APB_MEM_WADDR field. + RMT_CH_TX_STATUS_APB_MEM_WADDR_Pos = 0xc + // Bit mask of APB_MEM_WADDR field. + RMT_CH_TX_STATUS_APB_MEM_WADDR_Msk = 0x1ff000 + // Position of APB_MEM_RD_ERR field. + RMT_CH_TX_STATUS_APB_MEM_RD_ERR_Pos = 0x15 + // Bit mask of APB_MEM_RD_ERR field. + RMT_CH_TX_STATUS_APB_MEM_RD_ERR_Msk = 0x200000 + // Bit APB_MEM_RD_ERR. + RMT_CH_TX_STATUS_APB_MEM_RD_ERR = 0x200000 + // Position of MEM_EMPTY field. + RMT_CH_TX_STATUS_MEM_EMPTY_Pos = 0x16 + // Bit mask of MEM_EMPTY field. + RMT_CH_TX_STATUS_MEM_EMPTY_Msk = 0x400000 + // Bit MEM_EMPTY. + RMT_CH_TX_STATUS_MEM_EMPTY = 0x400000 + // Position of APB_MEM_WR_ERR field. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR_Pos = 0x17 + // Bit mask of APB_MEM_WR_ERR field. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR_Msk = 0x800000 + // Bit APB_MEM_WR_ERR. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR = 0x800000 + // Position of APB_MEM_RADDR field. + RMT_CH_TX_STATUS_APB_MEM_RADDR_Pos = 0x18 + // Bit mask of APB_MEM_RADDR field. + RMT_CH_TX_STATUS_APB_MEM_RADDR_Msk = 0xff000000 + + // CH0_RX_STATUS: Channel %s status register + // Position of MEM_WADDR_EX field. + RMT_CH_RX_STATUS_MEM_WADDR_EX_Pos = 0x0 + // Bit mask of MEM_WADDR_EX field. + RMT_CH_RX_STATUS_MEM_WADDR_EX_Msk = 0x1ff + // Position of APB_MEM_RADDR field. + RMT_CH_RX_STATUS_APB_MEM_RADDR_Pos = 0xc + // Bit mask of APB_MEM_RADDR field. + RMT_CH_RX_STATUS_APB_MEM_RADDR_Msk = 0x1ff000 + // Position of STATE field. + RMT_CH_RX_STATUS_STATE_Pos = 0x16 + // Bit mask of STATE field. + RMT_CH_RX_STATUS_STATE_Msk = 0x1c00000 + // Position of MEM_OWNER_ERR field. + RMT_CH_RX_STATUS_MEM_OWNER_ERR_Pos = 0x19 + // Bit mask of MEM_OWNER_ERR field. + RMT_CH_RX_STATUS_MEM_OWNER_ERR_Msk = 0x2000000 + // Bit MEM_OWNER_ERR. + RMT_CH_RX_STATUS_MEM_OWNER_ERR = 0x2000000 + // Position of MEM_FULL field. + RMT_CH_RX_STATUS_MEM_FULL_Pos = 0x1a + // Bit mask of MEM_FULL field. + RMT_CH_RX_STATUS_MEM_FULL_Msk = 0x4000000 + // Bit MEM_FULL. + RMT_CH_RX_STATUS_MEM_FULL = 0x4000000 + // Position of APB_MEM_RD_ERR field. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR_Pos = 0x1b + // Bit mask of APB_MEM_RD_ERR field. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR_Msk = 0x8000000 + // Bit APB_MEM_RD_ERR. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR = 0x8000000 + + // INT_RAW: Raw interrupt status + // Position of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_RAW_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_RAW_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_RAW_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_RAW_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_RAW_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_RAW_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_RAW_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_RAW_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_RAW_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_RAW_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_RAW_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_RAW_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_RAW_CH_s_TX_LOOP = 0x1000 + + // INT_ST: Masked interrupt status + // Position of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ST_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_ST_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_ST_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_ST_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_ST_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_ST_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_ST_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_ST_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ST_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_ST_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_ST_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_ST_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_X_LOOP field. + RMT_INT_ST_CH_s_X_LOOP_Pos = 0xc + // Bit mask of CH_s_X_LOOP field. + RMT_INT_ST_CH_s_X_LOOP_Msk = 0x1000 + // Bit CH_s_X_LOOP. + RMT_INT_ST_CH_s_X_LOOP = 0x1000 + + // INT_ENA: Interrupt enable bits + // Position of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ENA_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_ENA_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_ENA_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_ENA_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_ENA_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_ENA_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_ENA_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_ENA_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ENA_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_ENA_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_ENA_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_ENA_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_X_LOOP field. + RMT_INT_ENA_CH_s_X_LOOP_Pos = 0xc + // Bit mask of CH_s_X_LOOP field. + RMT_INT_ENA_CH_s_X_LOOP_Msk = 0x1000 + // Bit CH_s_X_LOOP. + RMT_INT_ENA_CH_s_X_LOOP = 0x1000 + + // INT_CLR: Interrupt clear bits + // Position of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_CLR_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_CLR_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_CLR_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_CLR_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_CLR_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_CLR_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_CLR_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_CLR_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_CLR_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_CLR_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_CLR_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_CLR_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_CLR_CH_s_TX_LOOP = 0x1000 + + // CH0CARRIER_DUTY: Channel %s duty cycle configuration register + // Position of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Pos = 0x0 + // Bit mask of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Msk = 0xffff + // Position of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Pos = 0x10 + // Bit mask of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Msk = 0xffff0000 + + // CH0_RX_CARRIER_RM: Channel %s carrier remove register + // Position of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Pos = 0x0 + // Bit mask of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Msk = 0xffff + // Position of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Pos = 0x10 + // Bit mask of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Msk = 0xffff0000 + + // CH0_TX_LIM: Channel %s Tx event configuration register + // Position of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Pos = 0x0 + // Bit mask of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Msk = 0x1ff + // Position of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Pos = 0x9 + // Bit mask of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Msk = 0x7fe00 + // Position of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Pos = 0x13 + // Bit mask of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Msk = 0x80000 + // Bit TX_LOOP_CNT_EN. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN = 0x80000 + // Position of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Pos = 0x14 + // Bit mask of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Msk = 0x100000 + // Bit LOOP_COUNT_RESET. + RMT_CH_TX_LIM_LOOP_COUNT_RESET = 0x100000 + // Position of LOOP_STOP_EN field. + RMT_CH_TX_LIM_LOOP_STOP_EN_Pos = 0x15 + // Bit mask of LOOP_STOP_EN field. + RMT_CH_TX_LIM_LOOP_STOP_EN_Msk = 0x200000 + // Bit LOOP_STOP_EN. + RMT_CH_TX_LIM_LOOP_STOP_EN = 0x200000 + + // CH0_RX_LIM: Channel %s Rx event configuration register + // Position of RMT_RX_LIM field. + RMT_CH_RX_LIM_RMT_RX_LIM_Pos = 0x0 + // Bit mask of RMT_RX_LIM field. + RMT_CH_RX_LIM_RMT_RX_LIM_Msk = 0x1ff + + // SYS_CONF: RMT apb configuration register + // Position of APB_FIFO_MASK field. + RMT_SYS_CONF_APB_FIFO_MASK_Pos = 0x0 + // Bit mask of APB_FIFO_MASK field. + RMT_SYS_CONF_APB_FIFO_MASK_Msk = 0x1 + // Bit APB_FIFO_MASK. + RMT_SYS_CONF_APB_FIFO_MASK = 0x1 + // Position of MEM_CLK_FORCE_ON field. + RMT_SYS_CONF_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + RMT_SYS_CONF_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + RMT_SYS_CONF_MEM_CLK_FORCE_ON = 0x2 + // Position of MEM_FORCE_PD field. + RMT_SYS_CONF_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of MEM_FORCE_PD field. + RMT_SYS_CONF_MEM_FORCE_PD_Msk = 0x4 + // Bit MEM_FORCE_PD. + RMT_SYS_CONF_MEM_FORCE_PD = 0x4 + // Position of MEM_FORCE_PU field. + RMT_SYS_CONF_MEM_FORCE_PU_Pos = 0x3 + // Bit mask of MEM_FORCE_PU field. + RMT_SYS_CONF_MEM_FORCE_PU_Msk = 0x8 + // Bit MEM_FORCE_PU. + RMT_SYS_CONF_MEM_FORCE_PU = 0x8 + // Position of SCLK_DIV_NUM field. + RMT_SYS_CONF_SCLK_DIV_NUM_Pos = 0x4 + // Bit mask of SCLK_DIV_NUM field. + RMT_SYS_CONF_SCLK_DIV_NUM_Msk = 0xff0 + // Position of SCLK_DIV_A field. + RMT_SYS_CONF_SCLK_DIV_A_Pos = 0xc + // Bit mask of SCLK_DIV_A field. + RMT_SYS_CONF_SCLK_DIV_A_Msk = 0x3f000 + // Position of SCLK_DIV_B field. + RMT_SYS_CONF_SCLK_DIV_B_Pos = 0x12 + // Bit mask of SCLK_DIV_B field. + RMT_SYS_CONF_SCLK_DIV_B_Msk = 0xfc0000 + // Position of SCLK_SEL field. + RMT_SYS_CONF_SCLK_SEL_Pos = 0x18 + // Bit mask of SCLK_SEL field. + RMT_SYS_CONF_SCLK_SEL_Msk = 0x3000000 + // Position of SCLK_ACTIVE field. + RMT_SYS_CONF_SCLK_ACTIVE_Pos = 0x1a + // Bit mask of SCLK_ACTIVE field. + RMT_SYS_CONF_SCLK_ACTIVE_Msk = 0x4000000 + // Bit SCLK_ACTIVE. + RMT_SYS_CONF_SCLK_ACTIVE = 0x4000000 + // Position of CLK_EN field. + RMT_SYS_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + RMT_SYS_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + RMT_SYS_CONF_CLK_EN = 0x80000000 + + // TX_SIM: RMT TX synchronous register + // Position of CH0 field. + RMT_TX_SIM_CH0_Pos = 0x0 + // Bit mask of CH0 field. + RMT_TX_SIM_CH0_Msk = 0x1 + // Bit CH0. + RMT_TX_SIM_CH0 = 0x1 + // Position of CH1 field. + RMT_TX_SIM_CH1_Pos = 0x1 + // Bit mask of CH1 field. + RMT_TX_SIM_CH1_Msk = 0x2 + // Bit CH1. + RMT_TX_SIM_CH1 = 0x2 + // Position of EN field. + RMT_TX_SIM_EN_Pos = 0x2 + // Bit mask of EN field. + RMT_TX_SIM_EN_Msk = 0x4 + // Bit EN. + RMT_TX_SIM_EN = 0x4 + + // REF_CNT_RST: RMT clock divider reset register + // Position of TX_REF_CNT_RST field. + RMT_REF_CNT_RST_TX_REF_CNT_RST_Pos = 0x0 + // Bit mask of TX_REF_CNT_RST field. + RMT_REF_CNT_RST_TX_REF_CNT_RST_Msk = 0x1 + // Bit TX_REF_CNT_RST. + RMT_REF_CNT_RST_TX_REF_CNT_RST = 0x1 + // Position of TX_REF_CNT_RST_CH1 field. + RMT_REF_CNT_RST_TX_REF_CNT_RST_CH1_Pos = 0x1 + // Bit mask of TX_REF_CNT_RST_CH1 field. + RMT_REF_CNT_RST_TX_REF_CNT_RST_CH1_Msk = 0x2 + // Bit TX_REF_CNT_RST_CH1. + RMT_REF_CNT_RST_TX_REF_CNT_RST_CH1 = 0x2 + // Position of RX_REF_CNT_RST_CH2 field. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH2_Pos = 0x2 + // Bit mask of RX_REF_CNT_RST_CH2 field. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH2_Msk = 0x4 + // Bit RX_REF_CNT_RST_CH2. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH2 = 0x4 + // Position of RX_REF_CNT_RST_CH3 field. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH3_Pos = 0x3 + // Bit mask of RX_REF_CNT_RST_CH3 field. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH3_Msk = 0x8 + // Bit RX_REF_CNT_RST_CH3. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH3 = 0x8 + + // DATE: RMT version register + // Position of RMT_DATE field. + RMT_DATE_RMT_DATE_Pos = 0x0 + // Bit mask of RMT_DATE field. + RMT_DATE_RMT_DATE_Msk = 0xfffffff +) + +// Constants for RNG: Hardware Random Number Generator +const () + +// Constants for RSA: RSA (Rivest Shamir Adleman) Accelerator +const ( + // M_PRIME: RSA M_prime register + // Position of M_PRIME field. + RSA_M_PRIME_M_PRIME_Pos = 0x0 + // Bit mask of M_PRIME field. + RSA_M_PRIME_M_PRIME_Msk = 0xffffffff + + // MODE: RSA mode register + // Position of MODE field. + RSA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + RSA_MODE_MODE_Msk = 0x7f + + // QUERY_CLEAN: RSA query clean register + // Position of QUERY_CLEAN field. + RSA_QUERY_CLEAN_QUERY_CLEAN_Pos = 0x0 + // Bit mask of QUERY_CLEAN field. + RSA_QUERY_CLEAN_QUERY_CLEAN_Msk = 0x1 + // Bit QUERY_CLEAN. + RSA_QUERY_CLEAN_QUERY_CLEAN = 0x1 + + // SET_START_MODEXP: RSA modular exponentiation trigger register. + // Position of SET_START_MODEXP field. + RSA_SET_START_MODEXP_SET_START_MODEXP_Pos = 0x0 + // Bit mask of SET_START_MODEXP field. + RSA_SET_START_MODEXP_SET_START_MODEXP_Msk = 0x1 + // Bit SET_START_MODEXP. + RSA_SET_START_MODEXP_SET_START_MODEXP = 0x1 + + // SET_START_MODMULT: RSA modular multiplication trigger register. + // Position of SET_START_MODMULT field. + RSA_SET_START_MODMULT_SET_START_MODMULT_Pos = 0x0 + // Bit mask of SET_START_MODMULT field. + RSA_SET_START_MODMULT_SET_START_MODMULT_Msk = 0x1 + // Bit SET_START_MODMULT. + RSA_SET_START_MODMULT_SET_START_MODMULT = 0x1 + + // SET_START_MULT: RSA normal multiplication trigger register. + // Position of SET_START_MULT field. + RSA_SET_START_MULT_SET_START_MULT_Pos = 0x0 + // Bit mask of SET_START_MULT field. + RSA_SET_START_MULT_SET_START_MULT_Msk = 0x1 + // Bit SET_START_MULT. + RSA_SET_START_MULT_SET_START_MULT = 0x1 + + // QUERY_IDLE: RSA query idle register + // Position of QUERY_IDLE field. + RSA_QUERY_IDLE_QUERY_IDLE_Pos = 0x0 + // Bit mask of QUERY_IDLE field. + RSA_QUERY_IDLE_QUERY_IDLE_Msk = 0x1 + // Bit QUERY_IDLE. + RSA_QUERY_IDLE_QUERY_IDLE = 0x1 + + // INT_CLR: RSA interrupt clear register + // Position of CLEAR_INTERRUPT field. + RSA_INT_CLR_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + RSA_INT_CLR_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + RSA_INT_CLR_CLEAR_INTERRUPT = 0x1 + + // CONSTANT_TIME: RSA constant time option register + // Position of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Pos = 0x0 + // Bit mask of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Msk = 0x1 + // Bit CONSTANT_TIME. + RSA_CONSTANT_TIME_CONSTANT_TIME = 0x1 + + // SEARCH_ENABLE: RSA search option + // Position of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Pos = 0x0 + // Bit mask of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Msk = 0x1 + // Bit SEARCH_ENABLE. + RSA_SEARCH_ENABLE_SEARCH_ENABLE = 0x1 + + // SEARCH_POS: RSA search position configure register + // Position of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Pos = 0x0 + // Bit mask of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Msk = 0xfff + + // INT_ENA: RSA interrupt enable register + // Position of INT_ENA field. + RSA_INT_ENA_INT_ENA_Pos = 0x0 + // Bit mask of INT_ENA field. + RSA_INT_ENA_INT_ENA_Msk = 0x1 + // Bit INT_ENA. + RSA_INT_ENA_INT_ENA = 0x1 + + // DATE: RSA version control register + // Position of DATE field. + RSA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RSA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for SHA: SHA (Secure Hash Algorithm) Accelerator +const ( + // MODE: Initial configuration register. + // Position of MODE field. + SHA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + SHA_MODE_MODE_Msk = 0x7 + + // T_STRING: SHA 512/t configuration register 0. + // Position of T_STRING field. + SHA_T_STRING_T_STRING_Pos = 0x0 + // Bit mask of T_STRING field. + SHA_T_STRING_T_STRING_Msk = 0xffffffff + + // T_LENGTH: SHA 512/t configuration register 1. + // Position of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Pos = 0x0 + // Bit mask of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Msk = 0x3f + + // DMA_BLOCK_NUM: DMA configuration register 0. + // Position of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Pos = 0x0 + // Bit mask of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Msk = 0x3f + + // START: Typical SHA configuration register 0. + // Position of START field. + SHA_START_START_Pos = 0x1 + // Bit mask of START field. + SHA_START_START_Msk = 0xfffffffe + + // CONTINUE: Typical SHA configuration register 1. + // Position of CONTINUE field. + SHA_CONTINUE_CONTINUE_Pos = 0x1 + // Bit mask of CONTINUE field. + SHA_CONTINUE_CONTINUE_Msk = 0xfffffffe + + // BUSY: Busy register. + // Position of STATE field. + SHA_BUSY_STATE_Pos = 0x0 + // Bit mask of STATE field. + SHA_BUSY_STATE_Msk = 0x1 + // Bit STATE. + SHA_BUSY_STATE = 0x1 + + // DMA_START: DMA configuration register 1. + // Position of DMA_START field. + SHA_DMA_START_DMA_START_Pos = 0x0 + // Bit mask of DMA_START field. + SHA_DMA_START_DMA_START_Msk = 0x1 + // Bit DMA_START. + SHA_DMA_START_DMA_START = 0x1 + + // DMA_CONTINUE: DMA configuration register 2. + // Position of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Pos = 0x0 + // Bit mask of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Msk = 0x1 + // Bit DMA_CONTINUE. + SHA_DMA_CONTINUE_DMA_CONTINUE = 0x1 + + // CLEAR_IRQ: Interrupt clear register. + // Position of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT = 0x1 + + // IRQ_ENA: Interrupt enable register. + // Position of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Pos = 0x0 + // Bit mask of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Msk = 0x1 + // Bit INTERRUPT_ENA. + SHA_IRQ_ENA_INTERRUPT_ENA = 0x1 + + // DATE: Date register. + // Position of DATE field. + SHA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SHA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for SLCHOST: SLCHOST Peripheral +const ( + // FUNC2_0: *******Description*********** + // Position of SLC_FUNC2_INT field. + SLCHOST_FUNC2_0_SLC_FUNC2_INT_Pos = 0x18 + // Bit mask of SLC_FUNC2_INT field. + SLCHOST_FUNC2_0_SLC_FUNC2_INT_Msk = 0x1000000 + // Bit SLC_FUNC2_INT. + SLCHOST_FUNC2_0_SLC_FUNC2_INT = 0x1000000 + + // FUNC2_1: *******Description*********** + // Position of SLC_FUNC2_INT_EN field. + SLCHOST_FUNC2_1_SLC_FUNC2_INT_EN_Pos = 0x0 + // Bit mask of SLC_FUNC2_INT_EN field. + SLCHOST_FUNC2_1_SLC_FUNC2_INT_EN_Msk = 0x1 + // Bit SLC_FUNC2_INT_EN. + SLCHOST_FUNC2_1_SLC_FUNC2_INT_EN = 0x1 + + // FUNC2_2: *******Description*********** + // Position of SLC_FUNC1_MDSTAT field. + SLCHOST_FUNC2_2_SLC_FUNC1_MDSTAT_Pos = 0x0 + // Bit mask of SLC_FUNC1_MDSTAT field. + SLCHOST_FUNC2_2_SLC_FUNC1_MDSTAT_Msk = 0x1 + // Bit SLC_FUNC1_MDSTAT. + SLCHOST_FUNC2_2_SLC_FUNC1_MDSTAT = 0x1 + + // GPIO_STATUS0: *******Description*********** + // Position of GPIO_SDIO_INT0 field. + SLCHOST_GPIO_STATUS0_GPIO_SDIO_INT0_Pos = 0x0 + // Bit mask of GPIO_SDIO_INT0 field. + SLCHOST_GPIO_STATUS0_GPIO_SDIO_INT0_Msk = 0xffffffff + + // GPIO_STATUS1: *******Description*********** + // Position of GPIO_SDIO_INT1 field. + SLCHOST_GPIO_STATUS1_GPIO_SDIO_INT1_Pos = 0x0 + // Bit mask of GPIO_SDIO_INT1 field. + SLCHOST_GPIO_STATUS1_GPIO_SDIO_INT1_Msk = 0xffffffff + + // GPIO_IN0: *******Description*********** + // Position of GPIO_SDIO_IN0 field. + SLCHOST_GPIO_IN0_GPIO_SDIO_IN0_Pos = 0x0 + // Bit mask of GPIO_SDIO_IN0 field. + SLCHOST_GPIO_IN0_GPIO_SDIO_IN0_Msk = 0xffffffff + + // GPIO_IN1: *******Description*********** + // Position of GPIO_SDIO_IN1 field. + SLCHOST_GPIO_IN1_GPIO_SDIO_IN1_Pos = 0x0 + // Bit mask of GPIO_SDIO_IN1 field. + SLCHOST_GPIO_IN1_GPIO_SDIO_IN1_Msk = 0xffffffff + + // SLC0HOST_TOKEN_RDATA: *******Description*********** + // Position of SLC0_TOKEN0 field. + SLCHOST_SLC0HOST_TOKEN_RDATA_SLC0_TOKEN0_Pos = 0x0 + // Bit mask of SLC0_TOKEN0 field. + SLCHOST_SLC0HOST_TOKEN_RDATA_SLC0_TOKEN0_Msk = 0xfff + // Position of SLC0_RX_PF_VALID field. + SLCHOST_SLC0HOST_TOKEN_RDATA_SLC0_RX_PF_VALID_Pos = 0xc + // Bit mask of SLC0_RX_PF_VALID field. + SLCHOST_SLC0HOST_TOKEN_RDATA_SLC0_RX_PF_VALID_Msk = 0x1000 + // Bit SLC0_RX_PF_VALID. + SLCHOST_SLC0HOST_TOKEN_RDATA_SLC0_RX_PF_VALID = 0x1000 + // Position of HOSTSLCHOST_SLC0_TOKEN1 field. + SLCHOST_SLC0HOST_TOKEN_RDATA_HOSTSLCHOST_SLC0_TOKEN1_Pos = 0x10 + // Bit mask of HOSTSLCHOST_SLC0_TOKEN1 field. + SLCHOST_SLC0HOST_TOKEN_RDATA_HOSTSLCHOST_SLC0_TOKEN1_Msk = 0xfff0000 + // Position of SLC0_RX_PF_EOF field. + SLCHOST_SLC0HOST_TOKEN_RDATA_SLC0_RX_PF_EOF_Pos = 0x1c + // Bit mask of SLC0_RX_PF_EOF field. + SLCHOST_SLC0HOST_TOKEN_RDATA_SLC0_RX_PF_EOF_Msk = 0xf0000000 + + // SLC0_HOST_PF: *******Description*********** + // Position of SLC0_PF_DATA field. + SLCHOST_SLC0_HOST_PF_SLC0_PF_DATA_Pos = 0x0 + // Bit mask of SLC0_PF_DATA field. + SLCHOST_SLC0_HOST_PF_SLC0_PF_DATA_Msk = 0xffffffff + + // SLC1_HOST_PF: *******Description*********** + // Position of SLC1_PF_DATA field. + SLCHOST_SLC1_HOST_PF_SLC1_PF_DATA_Pos = 0x0 + // Bit mask of SLC1_PF_DATA field. + SLCHOST_SLC1_HOST_PF_SLC1_PF_DATA_Msk = 0xffffffff + + // SLC0HOST_INT_RAW: *******Description*********** + // Position of SLC0_TOHOST_BIT0_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT0_INT_RAW_Pos = 0x0 + // Bit mask of SLC0_TOHOST_BIT0_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT0_INT_RAW_Msk = 0x1 + // Bit SLC0_TOHOST_BIT0_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT0_INT_RAW = 0x1 + // Position of SLC0_TOHOST_BIT1_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT1_INT_RAW_Pos = 0x1 + // Bit mask of SLC0_TOHOST_BIT1_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT1_INT_RAW_Msk = 0x2 + // Bit SLC0_TOHOST_BIT1_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT1_INT_RAW = 0x2 + // Position of SLC0_TOHOST_BIT2_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT2_INT_RAW_Pos = 0x2 + // Bit mask of SLC0_TOHOST_BIT2_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT2_INT_RAW_Msk = 0x4 + // Bit SLC0_TOHOST_BIT2_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT2_INT_RAW = 0x4 + // Position of SLC0_TOHOST_BIT3_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT3_INT_RAW_Pos = 0x3 + // Bit mask of SLC0_TOHOST_BIT3_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT3_INT_RAW_Msk = 0x8 + // Bit SLC0_TOHOST_BIT3_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT3_INT_RAW = 0x8 + // Position of SLC0_TOHOST_BIT4_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT4_INT_RAW_Pos = 0x4 + // Bit mask of SLC0_TOHOST_BIT4_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT4_INT_RAW_Msk = 0x10 + // Bit SLC0_TOHOST_BIT4_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT4_INT_RAW = 0x10 + // Position of SLC0_TOHOST_BIT5_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT5_INT_RAW_Pos = 0x5 + // Bit mask of SLC0_TOHOST_BIT5_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT5_INT_RAW_Msk = 0x20 + // Bit SLC0_TOHOST_BIT5_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT5_INT_RAW = 0x20 + // Position of SLC0_TOHOST_BIT6_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT6_INT_RAW_Pos = 0x6 + // Bit mask of SLC0_TOHOST_BIT6_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT6_INT_RAW_Msk = 0x40 + // Bit SLC0_TOHOST_BIT6_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT6_INT_RAW = 0x40 + // Position of SLC0_TOHOST_BIT7_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT7_INT_RAW_Pos = 0x7 + // Bit mask of SLC0_TOHOST_BIT7_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT7_INT_RAW_Msk = 0x80 + // Bit SLC0_TOHOST_BIT7_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOHOST_BIT7_INT_RAW = 0x80 + // Position of SLC0_TOKEN0_1TO0_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW_Pos = 0x8 + // Bit mask of SLC0_TOKEN0_1TO0_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW_Msk = 0x100 + // Bit SLC0_TOKEN0_1TO0_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN0_1TO0_INT_RAW = 0x100 + // Position of SLC0_TOKEN1_1TO0_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW_Pos = 0x9 + // Bit mask of SLC0_TOKEN1_1TO0_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW_Msk = 0x200 + // Bit SLC0_TOKEN1_1TO0_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN1_1TO0_INT_RAW = 0x200 + // Position of SLC0_TOKEN0_0TO1_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN0_0TO1_INT_RAW_Pos = 0xa + // Bit mask of SLC0_TOKEN0_0TO1_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN0_0TO1_INT_RAW_Msk = 0x400 + // Bit SLC0_TOKEN0_0TO1_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN0_0TO1_INT_RAW = 0x400 + // Position of SLC0_TOKEN1_0TO1_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN1_0TO1_INT_RAW_Pos = 0xb + // Bit mask of SLC0_TOKEN1_0TO1_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN1_0TO1_INT_RAW_Msk = 0x800 + // Bit SLC0_TOKEN1_0TO1_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TOKEN1_0TO1_INT_RAW = 0x800 + // Position of SLC0HOST_RX_SOF_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_RX_SOF_INT_RAW_Pos = 0xc + // Bit mask of SLC0HOST_RX_SOF_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_RX_SOF_INT_RAW_Msk = 0x1000 + // Bit SLC0HOST_RX_SOF_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_RX_SOF_INT_RAW = 0x1000 + // Position of SLC0HOST_RX_EOF_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_RX_EOF_INT_RAW_Pos = 0xd + // Bit mask of SLC0HOST_RX_EOF_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_RX_EOF_INT_RAW_Msk = 0x2000 + // Bit SLC0HOST_RX_EOF_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_RX_EOF_INT_RAW = 0x2000 + // Position of SLC0HOST_RX_START_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_RX_START_INT_RAW_Pos = 0xe + // Bit mask of SLC0HOST_RX_START_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_RX_START_INT_RAW_Msk = 0x4000 + // Bit SLC0HOST_RX_START_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_RX_START_INT_RAW = 0x4000 + // Position of SLC0HOST_TX_START_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_TX_START_INT_RAW_Pos = 0xf + // Bit mask of SLC0HOST_TX_START_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_TX_START_INT_RAW_Msk = 0x8000 + // Bit SLC0HOST_TX_START_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0HOST_TX_START_INT_RAW = 0x8000 + // Position of SLC0_RX_UDF_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_RX_UDF_INT_RAW_Pos = 0x10 + // Bit mask of SLC0_RX_UDF_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_RX_UDF_INT_RAW_Msk = 0x10000 + // Bit SLC0_RX_UDF_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_RX_UDF_INT_RAW = 0x10000 + // Position of SLC0_TX_OVF_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TX_OVF_INT_RAW_Pos = 0x11 + // Bit mask of SLC0_TX_OVF_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TX_OVF_INT_RAW_Msk = 0x20000 + // Bit SLC0_TX_OVF_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_TX_OVF_INT_RAW = 0x20000 + // Position of SLC0_RX_PF_VALID_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_RX_PF_VALID_INT_RAW_Pos = 0x12 + // Bit mask of SLC0_RX_PF_VALID_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_RX_PF_VALID_INT_RAW_Msk = 0x40000 + // Bit SLC0_RX_PF_VALID_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_RX_PF_VALID_INT_RAW = 0x40000 + // Position of SLC0_EXT_BIT0_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT0_INT_RAW_Pos = 0x13 + // Bit mask of SLC0_EXT_BIT0_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT0_INT_RAW_Msk = 0x80000 + // Bit SLC0_EXT_BIT0_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT0_INT_RAW = 0x80000 + // Position of SLC0_EXT_BIT1_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT1_INT_RAW_Pos = 0x14 + // Bit mask of SLC0_EXT_BIT1_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT1_INT_RAW_Msk = 0x100000 + // Bit SLC0_EXT_BIT1_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT1_INT_RAW = 0x100000 + // Position of SLC0_EXT_BIT2_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT2_INT_RAW_Pos = 0x15 + // Bit mask of SLC0_EXT_BIT2_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT2_INT_RAW_Msk = 0x200000 + // Bit SLC0_EXT_BIT2_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT2_INT_RAW = 0x200000 + // Position of SLC0_EXT_BIT3_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT3_INT_RAW_Pos = 0x16 + // Bit mask of SLC0_EXT_BIT3_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT3_INT_RAW_Msk = 0x400000 + // Bit SLC0_EXT_BIT3_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_EXT_BIT3_INT_RAW = 0x400000 + // Position of SLC0_RX_NEW_PACKET_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_RX_NEW_PACKET_INT_RAW_Pos = 0x17 + // Bit mask of SLC0_RX_NEW_PACKET_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_RX_NEW_PACKET_INT_RAW_Msk = 0x800000 + // Bit SLC0_RX_NEW_PACKET_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_RX_NEW_PACKET_INT_RAW = 0x800000 + // Position of SLC0_HOST_RD_RETRY_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_HOST_RD_RETRY_INT_RAW_Pos = 0x18 + // Bit mask of SLC0_HOST_RD_RETRY_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_SLC0_HOST_RD_RETRY_INT_RAW_Msk = 0x1000000 + // Bit SLC0_HOST_RD_RETRY_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_SLC0_HOST_RD_RETRY_INT_RAW = 0x1000000 + // Position of GPIO_SDIO_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_GPIO_SDIO_INT_RAW_Pos = 0x19 + // Bit mask of GPIO_SDIO_INT_RAW field. + SLCHOST_SLC0HOST_INT_RAW_GPIO_SDIO_INT_RAW_Msk = 0x2000000 + // Bit GPIO_SDIO_INT_RAW. + SLCHOST_SLC0HOST_INT_RAW_GPIO_SDIO_INT_RAW = 0x2000000 + + // SLC1HOST_INT_RAW: *******Description*********** + // Position of SLC1_TOHOST_BIT0_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT0_INT_RAW_Pos = 0x0 + // Bit mask of SLC1_TOHOST_BIT0_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT0_INT_RAW_Msk = 0x1 + // Bit SLC1_TOHOST_BIT0_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT0_INT_RAW = 0x1 + // Position of SLC1_TOHOST_BIT1_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT1_INT_RAW_Pos = 0x1 + // Bit mask of SLC1_TOHOST_BIT1_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT1_INT_RAW_Msk = 0x2 + // Bit SLC1_TOHOST_BIT1_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT1_INT_RAW = 0x2 + // Position of SLC1_TOHOST_BIT2_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT2_INT_RAW_Pos = 0x2 + // Bit mask of SLC1_TOHOST_BIT2_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT2_INT_RAW_Msk = 0x4 + // Bit SLC1_TOHOST_BIT2_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT2_INT_RAW = 0x4 + // Position of SLC1_TOHOST_BIT3_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT3_INT_RAW_Pos = 0x3 + // Bit mask of SLC1_TOHOST_BIT3_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT3_INT_RAW_Msk = 0x8 + // Bit SLC1_TOHOST_BIT3_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT3_INT_RAW = 0x8 + // Position of SLC1_TOHOST_BIT4_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT4_INT_RAW_Pos = 0x4 + // Bit mask of SLC1_TOHOST_BIT4_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT4_INT_RAW_Msk = 0x10 + // Bit SLC1_TOHOST_BIT4_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT4_INT_RAW = 0x10 + // Position of SLC1_TOHOST_BIT5_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT5_INT_RAW_Pos = 0x5 + // Bit mask of SLC1_TOHOST_BIT5_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT5_INT_RAW_Msk = 0x20 + // Bit SLC1_TOHOST_BIT5_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT5_INT_RAW = 0x20 + // Position of SLC1_TOHOST_BIT6_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT6_INT_RAW_Pos = 0x6 + // Bit mask of SLC1_TOHOST_BIT6_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT6_INT_RAW_Msk = 0x40 + // Bit SLC1_TOHOST_BIT6_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT6_INT_RAW = 0x40 + // Position of SLC1_TOHOST_BIT7_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT7_INT_RAW_Pos = 0x7 + // Bit mask of SLC1_TOHOST_BIT7_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT7_INT_RAW_Msk = 0x80 + // Bit SLC1_TOHOST_BIT7_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOHOST_BIT7_INT_RAW = 0x80 + // Position of SLC1_TOKEN0_1TO0_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW_Pos = 0x8 + // Bit mask of SLC1_TOKEN0_1TO0_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW_Msk = 0x100 + // Bit SLC1_TOKEN0_1TO0_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN0_1TO0_INT_RAW = 0x100 + // Position of SLC1_TOKEN1_1TO0_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW_Pos = 0x9 + // Bit mask of SLC1_TOKEN1_1TO0_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW_Msk = 0x200 + // Bit SLC1_TOKEN1_1TO0_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN1_1TO0_INT_RAW = 0x200 + // Position of SLC1_TOKEN0_0TO1_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN0_0TO1_INT_RAW_Pos = 0xa + // Bit mask of SLC1_TOKEN0_0TO1_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN0_0TO1_INT_RAW_Msk = 0x400 + // Bit SLC1_TOKEN0_0TO1_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN0_0TO1_INT_RAW = 0x400 + // Position of SLC1_TOKEN1_0TO1_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN1_0TO1_INT_RAW_Pos = 0xb + // Bit mask of SLC1_TOKEN1_0TO1_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN1_0TO1_INT_RAW_Msk = 0x800 + // Bit SLC1_TOKEN1_0TO1_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TOKEN1_0TO1_INT_RAW = 0x800 + // Position of SLC1HOST_RX_SOF_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_RX_SOF_INT_RAW_Pos = 0xc + // Bit mask of SLC1HOST_RX_SOF_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_RX_SOF_INT_RAW_Msk = 0x1000 + // Bit SLC1HOST_RX_SOF_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_RX_SOF_INT_RAW = 0x1000 + // Position of SLC1HOST_RX_EOF_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_RX_EOF_INT_RAW_Pos = 0xd + // Bit mask of SLC1HOST_RX_EOF_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_RX_EOF_INT_RAW_Msk = 0x2000 + // Bit SLC1HOST_RX_EOF_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_RX_EOF_INT_RAW = 0x2000 + // Position of SLC1HOST_RX_START_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_RX_START_INT_RAW_Pos = 0xe + // Bit mask of SLC1HOST_RX_START_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_RX_START_INT_RAW_Msk = 0x4000 + // Bit SLC1HOST_RX_START_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_RX_START_INT_RAW = 0x4000 + // Position of SLC1HOST_TX_START_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_TX_START_INT_RAW_Pos = 0xf + // Bit mask of SLC1HOST_TX_START_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_TX_START_INT_RAW_Msk = 0x8000 + // Bit SLC1HOST_TX_START_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1HOST_TX_START_INT_RAW = 0x8000 + // Position of SLC1_RX_UDF_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_RX_UDF_INT_RAW_Pos = 0x10 + // Bit mask of SLC1_RX_UDF_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_RX_UDF_INT_RAW_Msk = 0x10000 + // Bit SLC1_RX_UDF_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_RX_UDF_INT_RAW = 0x10000 + // Position of SLC1_TX_OVF_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TX_OVF_INT_RAW_Pos = 0x11 + // Bit mask of SLC1_TX_OVF_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TX_OVF_INT_RAW_Msk = 0x20000 + // Bit SLC1_TX_OVF_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_TX_OVF_INT_RAW = 0x20000 + // Position of SLC1_RX_PF_VALID_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_RX_PF_VALID_INT_RAW_Pos = 0x12 + // Bit mask of SLC1_RX_PF_VALID_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_RX_PF_VALID_INT_RAW_Msk = 0x40000 + // Bit SLC1_RX_PF_VALID_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_RX_PF_VALID_INT_RAW = 0x40000 + // Position of SLC1_EXT_BIT0_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT0_INT_RAW_Pos = 0x13 + // Bit mask of SLC1_EXT_BIT0_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT0_INT_RAW_Msk = 0x80000 + // Bit SLC1_EXT_BIT0_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT0_INT_RAW = 0x80000 + // Position of SLC1_EXT_BIT1_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT1_INT_RAW_Pos = 0x14 + // Bit mask of SLC1_EXT_BIT1_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT1_INT_RAW_Msk = 0x100000 + // Bit SLC1_EXT_BIT1_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT1_INT_RAW = 0x100000 + // Position of SLC1_EXT_BIT2_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT2_INT_RAW_Pos = 0x15 + // Bit mask of SLC1_EXT_BIT2_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT2_INT_RAW_Msk = 0x200000 + // Bit SLC1_EXT_BIT2_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT2_INT_RAW = 0x200000 + // Position of SLC1_EXT_BIT3_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT3_INT_RAW_Pos = 0x16 + // Bit mask of SLC1_EXT_BIT3_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT3_INT_RAW_Msk = 0x400000 + // Bit SLC1_EXT_BIT3_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_EXT_BIT3_INT_RAW = 0x400000 + // Position of SLC1_WIFI_RX_NEW_PACKET_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_Pos = 0x17 + // Bit mask of SLC1_WIFI_RX_NEW_PACKET_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_Msk = 0x800000 + // Bit SLC1_WIFI_RX_NEW_PACKET_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_WIFI_RX_NEW_PACKET_INT_RAW = 0x800000 + // Position of SLC1_HOST_RD_RETRY_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_HOST_RD_RETRY_INT_RAW_Pos = 0x18 + // Bit mask of SLC1_HOST_RD_RETRY_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_HOST_RD_RETRY_INT_RAW_Msk = 0x1000000 + // Bit SLC1_HOST_RD_RETRY_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_HOST_RD_RETRY_INT_RAW = 0x1000000 + // Position of SLC1_BT_RX_NEW_PACKET_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_BT_RX_NEW_PACKET_INT_RAW_Pos = 0x19 + // Bit mask of SLC1_BT_RX_NEW_PACKET_INT_RAW field. + SLCHOST_SLC1HOST_INT_RAW_SLC1_BT_RX_NEW_PACKET_INT_RAW_Msk = 0x2000000 + // Bit SLC1_BT_RX_NEW_PACKET_INT_RAW. + SLCHOST_SLC1HOST_INT_RAW_SLC1_BT_RX_NEW_PACKET_INT_RAW = 0x2000000 + + // SLC0HOST_INT_ST: *******Description*********** + // Position of SLC0_TOHOST_BIT0_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT0_INT_ST_Pos = 0x0 + // Bit mask of SLC0_TOHOST_BIT0_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT0_INT_ST_Msk = 0x1 + // Bit SLC0_TOHOST_BIT0_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT0_INT_ST = 0x1 + // Position of SLC0_TOHOST_BIT1_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT1_INT_ST_Pos = 0x1 + // Bit mask of SLC0_TOHOST_BIT1_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT1_INT_ST_Msk = 0x2 + // Bit SLC0_TOHOST_BIT1_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT1_INT_ST = 0x2 + // Position of SLC0_TOHOST_BIT2_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT2_INT_ST_Pos = 0x2 + // Bit mask of SLC0_TOHOST_BIT2_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT2_INT_ST_Msk = 0x4 + // Bit SLC0_TOHOST_BIT2_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT2_INT_ST = 0x4 + // Position of SLC0_TOHOST_BIT3_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT3_INT_ST_Pos = 0x3 + // Bit mask of SLC0_TOHOST_BIT3_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT3_INT_ST_Msk = 0x8 + // Bit SLC0_TOHOST_BIT3_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT3_INT_ST = 0x8 + // Position of SLC0_TOHOST_BIT4_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT4_INT_ST_Pos = 0x4 + // Bit mask of SLC0_TOHOST_BIT4_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT4_INT_ST_Msk = 0x10 + // Bit SLC0_TOHOST_BIT4_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT4_INT_ST = 0x10 + // Position of SLC0_TOHOST_BIT5_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT5_INT_ST_Pos = 0x5 + // Bit mask of SLC0_TOHOST_BIT5_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT5_INT_ST_Msk = 0x20 + // Bit SLC0_TOHOST_BIT5_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT5_INT_ST = 0x20 + // Position of SLC0_TOHOST_BIT6_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT6_INT_ST_Pos = 0x6 + // Bit mask of SLC0_TOHOST_BIT6_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT6_INT_ST_Msk = 0x40 + // Bit SLC0_TOHOST_BIT6_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT6_INT_ST = 0x40 + // Position of SLC0_TOHOST_BIT7_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT7_INT_ST_Pos = 0x7 + // Bit mask of SLC0_TOHOST_BIT7_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT7_INT_ST_Msk = 0x80 + // Bit SLC0_TOHOST_BIT7_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOHOST_BIT7_INT_ST = 0x80 + // Position of SLC0_TOKEN0_1TO0_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN0_1TO0_INT_ST_Pos = 0x8 + // Bit mask of SLC0_TOKEN0_1TO0_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN0_1TO0_INT_ST_Msk = 0x100 + // Bit SLC0_TOKEN0_1TO0_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN0_1TO0_INT_ST = 0x100 + // Position of SLC0_TOKEN1_1TO0_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN1_1TO0_INT_ST_Pos = 0x9 + // Bit mask of SLC0_TOKEN1_1TO0_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN1_1TO0_INT_ST_Msk = 0x200 + // Bit SLC0_TOKEN1_1TO0_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN1_1TO0_INT_ST = 0x200 + // Position of SLC0_TOKEN0_0TO1_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN0_0TO1_INT_ST_Pos = 0xa + // Bit mask of SLC0_TOKEN0_0TO1_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN0_0TO1_INT_ST_Msk = 0x400 + // Bit SLC0_TOKEN0_0TO1_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN0_0TO1_INT_ST = 0x400 + // Position of SLC0_TOKEN1_0TO1_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN1_0TO1_INT_ST_Pos = 0xb + // Bit mask of SLC0_TOKEN1_0TO1_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN1_0TO1_INT_ST_Msk = 0x800 + // Bit SLC0_TOKEN1_0TO1_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TOKEN1_0TO1_INT_ST = 0x800 + // Position of SLC0HOST_RX_SOF_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_RX_SOF_INT_ST_Pos = 0xc + // Bit mask of SLC0HOST_RX_SOF_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_RX_SOF_INT_ST_Msk = 0x1000 + // Bit SLC0HOST_RX_SOF_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_RX_SOF_INT_ST = 0x1000 + // Position of SLC0HOST_RX_EOF_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_RX_EOF_INT_ST_Pos = 0xd + // Bit mask of SLC0HOST_RX_EOF_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_RX_EOF_INT_ST_Msk = 0x2000 + // Bit SLC0HOST_RX_EOF_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_RX_EOF_INT_ST = 0x2000 + // Position of SLC0HOST_RX_START_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_RX_START_INT_ST_Pos = 0xe + // Bit mask of SLC0HOST_RX_START_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_RX_START_INT_ST_Msk = 0x4000 + // Bit SLC0HOST_RX_START_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_RX_START_INT_ST = 0x4000 + // Position of SLC0HOST_TX_START_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_TX_START_INT_ST_Pos = 0xf + // Bit mask of SLC0HOST_TX_START_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_TX_START_INT_ST_Msk = 0x8000 + // Bit SLC0HOST_TX_START_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0HOST_TX_START_INT_ST = 0x8000 + // Position of SLC0_RX_UDF_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_RX_UDF_INT_ST_Pos = 0x10 + // Bit mask of SLC0_RX_UDF_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_RX_UDF_INT_ST_Msk = 0x10000 + // Bit SLC0_RX_UDF_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_RX_UDF_INT_ST = 0x10000 + // Position of SLC0_TX_OVF_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TX_OVF_INT_ST_Pos = 0x11 + // Bit mask of SLC0_TX_OVF_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_TX_OVF_INT_ST_Msk = 0x20000 + // Bit SLC0_TX_OVF_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_TX_OVF_INT_ST = 0x20000 + // Position of SLC0_RX_PF_VALID_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_RX_PF_VALID_INT_ST_Pos = 0x12 + // Bit mask of SLC0_RX_PF_VALID_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_RX_PF_VALID_INT_ST_Msk = 0x40000 + // Bit SLC0_RX_PF_VALID_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_RX_PF_VALID_INT_ST = 0x40000 + // Position of SLC0_EXT_BIT0_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT0_INT_ST_Pos = 0x13 + // Bit mask of SLC0_EXT_BIT0_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT0_INT_ST_Msk = 0x80000 + // Bit SLC0_EXT_BIT0_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT0_INT_ST = 0x80000 + // Position of SLC0_EXT_BIT1_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT1_INT_ST_Pos = 0x14 + // Bit mask of SLC0_EXT_BIT1_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT1_INT_ST_Msk = 0x100000 + // Bit SLC0_EXT_BIT1_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT1_INT_ST = 0x100000 + // Position of SLC0_EXT_BIT2_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT2_INT_ST_Pos = 0x15 + // Bit mask of SLC0_EXT_BIT2_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT2_INT_ST_Msk = 0x200000 + // Bit SLC0_EXT_BIT2_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT2_INT_ST = 0x200000 + // Position of SLC0_EXT_BIT3_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT3_INT_ST_Pos = 0x16 + // Bit mask of SLC0_EXT_BIT3_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT3_INT_ST_Msk = 0x400000 + // Bit SLC0_EXT_BIT3_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_EXT_BIT3_INT_ST = 0x400000 + // Position of SLC0_RX_NEW_PACKET_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_RX_NEW_PACKET_INT_ST_Pos = 0x17 + // Bit mask of SLC0_RX_NEW_PACKET_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_RX_NEW_PACKET_INT_ST_Msk = 0x800000 + // Bit SLC0_RX_NEW_PACKET_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_RX_NEW_PACKET_INT_ST = 0x800000 + // Position of SLC0_HOST_RD_RETRY_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_HOST_RD_RETRY_INT_ST_Pos = 0x18 + // Bit mask of SLC0_HOST_RD_RETRY_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_SLC0_HOST_RD_RETRY_INT_ST_Msk = 0x1000000 + // Bit SLC0_HOST_RD_RETRY_INT_ST. + SLCHOST_SLC0HOST_INT_ST_SLC0_HOST_RD_RETRY_INT_ST = 0x1000000 + // Position of GPIO_SDIO_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_GPIO_SDIO_INT_ST_Pos = 0x19 + // Bit mask of GPIO_SDIO_INT_ST field. + SLCHOST_SLC0HOST_INT_ST_GPIO_SDIO_INT_ST_Msk = 0x2000000 + // Bit GPIO_SDIO_INT_ST. + SLCHOST_SLC0HOST_INT_ST_GPIO_SDIO_INT_ST = 0x2000000 + + // SLC1HOST_INT_ST: *******Description*********** + // Position of SLC1_TOHOST_BIT0_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT0_INT_ST_Pos = 0x0 + // Bit mask of SLC1_TOHOST_BIT0_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT0_INT_ST_Msk = 0x1 + // Bit SLC1_TOHOST_BIT0_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT0_INT_ST = 0x1 + // Position of SLC1_TOHOST_BIT1_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT1_INT_ST_Pos = 0x1 + // Bit mask of SLC1_TOHOST_BIT1_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT1_INT_ST_Msk = 0x2 + // Bit SLC1_TOHOST_BIT1_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT1_INT_ST = 0x2 + // Position of SLC1_TOHOST_BIT2_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT2_INT_ST_Pos = 0x2 + // Bit mask of SLC1_TOHOST_BIT2_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT2_INT_ST_Msk = 0x4 + // Bit SLC1_TOHOST_BIT2_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT2_INT_ST = 0x4 + // Position of SLC1_TOHOST_BIT3_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT3_INT_ST_Pos = 0x3 + // Bit mask of SLC1_TOHOST_BIT3_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT3_INT_ST_Msk = 0x8 + // Bit SLC1_TOHOST_BIT3_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT3_INT_ST = 0x8 + // Position of SLC1_TOHOST_BIT4_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT4_INT_ST_Pos = 0x4 + // Bit mask of SLC1_TOHOST_BIT4_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT4_INT_ST_Msk = 0x10 + // Bit SLC1_TOHOST_BIT4_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT4_INT_ST = 0x10 + // Position of SLC1_TOHOST_BIT5_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT5_INT_ST_Pos = 0x5 + // Bit mask of SLC1_TOHOST_BIT5_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT5_INT_ST_Msk = 0x20 + // Bit SLC1_TOHOST_BIT5_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT5_INT_ST = 0x20 + // Position of SLC1_TOHOST_BIT6_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT6_INT_ST_Pos = 0x6 + // Bit mask of SLC1_TOHOST_BIT6_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT6_INT_ST_Msk = 0x40 + // Bit SLC1_TOHOST_BIT6_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT6_INT_ST = 0x40 + // Position of SLC1_TOHOST_BIT7_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT7_INT_ST_Pos = 0x7 + // Bit mask of SLC1_TOHOST_BIT7_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT7_INT_ST_Msk = 0x80 + // Bit SLC1_TOHOST_BIT7_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOHOST_BIT7_INT_ST = 0x80 + // Position of SLC1_TOKEN0_1TO0_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN0_1TO0_INT_ST_Pos = 0x8 + // Bit mask of SLC1_TOKEN0_1TO0_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN0_1TO0_INT_ST_Msk = 0x100 + // Bit SLC1_TOKEN0_1TO0_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN0_1TO0_INT_ST = 0x100 + // Position of SLC1_TOKEN1_1TO0_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN1_1TO0_INT_ST_Pos = 0x9 + // Bit mask of SLC1_TOKEN1_1TO0_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN1_1TO0_INT_ST_Msk = 0x200 + // Bit SLC1_TOKEN1_1TO0_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN1_1TO0_INT_ST = 0x200 + // Position of SLC1_TOKEN0_0TO1_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN0_0TO1_INT_ST_Pos = 0xa + // Bit mask of SLC1_TOKEN0_0TO1_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN0_0TO1_INT_ST_Msk = 0x400 + // Bit SLC1_TOKEN0_0TO1_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN0_0TO1_INT_ST = 0x400 + // Position of SLC1_TOKEN1_0TO1_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN1_0TO1_INT_ST_Pos = 0xb + // Bit mask of SLC1_TOKEN1_0TO1_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN1_0TO1_INT_ST_Msk = 0x800 + // Bit SLC1_TOKEN1_0TO1_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TOKEN1_0TO1_INT_ST = 0x800 + // Position of SLC1HOST_RX_SOF_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_RX_SOF_INT_ST_Pos = 0xc + // Bit mask of SLC1HOST_RX_SOF_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_RX_SOF_INT_ST_Msk = 0x1000 + // Bit SLC1HOST_RX_SOF_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_RX_SOF_INT_ST = 0x1000 + // Position of SLC1HOST_RX_EOF_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_RX_EOF_INT_ST_Pos = 0xd + // Bit mask of SLC1HOST_RX_EOF_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_RX_EOF_INT_ST_Msk = 0x2000 + // Bit SLC1HOST_RX_EOF_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_RX_EOF_INT_ST = 0x2000 + // Position of SLC1HOST_RX_START_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_RX_START_INT_ST_Pos = 0xe + // Bit mask of SLC1HOST_RX_START_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_RX_START_INT_ST_Msk = 0x4000 + // Bit SLC1HOST_RX_START_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_RX_START_INT_ST = 0x4000 + // Position of SLC1HOST_TX_START_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_TX_START_INT_ST_Pos = 0xf + // Bit mask of SLC1HOST_TX_START_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_TX_START_INT_ST_Msk = 0x8000 + // Bit SLC1HOST_TX_START_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1HOST_TX_START_INT_ST = 0x8000 + // Position of SLC1_RX_UDF_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_RX_UDF_INT_ST_Pos = 0x10 + // Bit mask of SLC1_RX_UDF_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_RX_UDF_INT_ST_Msk = 0x10000 + // Bit SLC1_RX_UDF_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_RX_UDF_INT_ST = 0x10000 + // Position of SLC1_TX_OVF_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TX_OVF_INT_ST_Pos = 0x11 + // Bit mask of SLC1_TX_OVF_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_TX_OVF_INT_ST_Msk = 0x20000 + // Bit SLC1_TX_OVF_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_TX_OVF_INT_ST = 0x20000 + // Position of SLC1_RX_PF_VALID_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_RX_PF_VALID_INT_ST_Pos = 0x12 + // Bit mask of SLC1_RX_PF_VALID_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_RX_PF_VALID_INT_ST_Msk = 0x40000 + // Bit SLC1_RX_PF_VALID_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_RX_PF_VALID_INT_ST = 0x40000 + // Position of SLC1_EXT_BIT0_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT0_INT_ST_Pos = 0x13 + // Bit mask of SLC1_EXT_BIT0_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT0_INT_ST_Msk = 0x80000 + // Bit SLC1_EXT_BIT0_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT0_INT_ST = 0x80000 + // Position of SLC1_EXT_BIT1_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT1_INT_ST_Pos = 0x14 + // Bit mask of SLC1_EXT_BIT1_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT1_INT_ST_Msk = 0x100000 + // Bit SLC1_EXT_BIT1_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT1_INT_ST = 0x100000 + // Position of SLC1_EXT_BIT2_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT2_INT_ST_Pos = 0x15 + // Bit mask of SLC1_EXT_BIT2_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT2_INT_ST_Msk = 0x200000 + // Bit SLC1_EXT_BIT2_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT2_INT_ST = 0x200000 + // Position of SLC1_EXT_BIT3_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT3_INT_ST_Pos = 0x16 + // Bit mask of SLC1_EXT_BIT3_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT3_INT_ST_Msk = 0x400000 + // Bit SLC1_EXT_BIT3_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_EXT_BIT3_INT_ST = 0x400000 + // Position of SLC1_WIFI_RX_NEW_PACKET_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_Pos = 0x17 + // Bit mask of SLC1_WIFI_RX_NEW_PACKET_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_Msk = 0x800000 + // Bit SLC1_WIFI_RX_NEW_PACKET_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_WIFI_RX_NEW_PACKET_INT_ST = 0x800000 + // Position of SLC1_HOST_RD_RETRY_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_HOST_RD_RETRY_INT_ST_Pos = 0x18 + // Bit mask of SLC1_HOST_RD_RETRY_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_HOST_RD_RETRY_INT_ST_Msk = 0x1000000 + // Bit SLC1_HOST_RD_RETRY_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_HOST_RD_RETRY_INT_ST = 0x1000000 + // Position of SLC1_BT_RX_NEW_PACKET_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_BT_RX_NEW_PACKET_INT_ST_Pos = 0x19 + // Bit mask of SLC1_BT_RX_NEW_PACKET_INT_ST field. + SLCHOST_SLC1HOST_INT_ST_SLC1_BT_RX_NEW_PACKET_INT_ST_Msk = 0x2000000 + // Bit SLC1_BT_RX_NEW_PACKET_INT_ST. + SLCHOST_SLC1HOST_INT_ST_SLC1_BT_RX_NEW_PACKET_INT_ST = 0x2000000 + + // PKT_LEN: *******Description*********** + // Position of HOSTSLCHOST_SLC0_LEN field. + SLCHOST_PKT_LEN_HOSTSLCHOST_SLC0_LEN_Pos = 0x0 + // Bit mask of HOSTSLCHOST_SLC0_LEN field. + SLCHOST_PKT_LEN_HOSTSLCHOST_SLC0_LEN_Msk = 0xfffff + // Position of HOSTSLCHOST_SLC0_LEN_CHECK field. + SLCHOST_PKT_LEN_HOSTSLCHOST_SLC0_LEN_CHECK_Pos = 0x14 + // Bit mask of HOSTSLCHOST_SLC0_LEN_CHECK field. + SLCHOST_PKT_LEN_HOSTSLCHOST_SLC0_LEN_CHECK_Msk = 0xfff00000 + + // STATE_W0: *******Description*********** + // Position of SLCHOST_STATE0 field. + SLCHOST_STATE_W0_SLCHOST_STATE0_Pos = 0x0 + // Bit mask of SLCHOST_STATE0 field. + SLCHOST_STATE_W0_SLCHOST_STATE0_Msk = 0xff + // Position of SLCHOST_STATE1 field. + SLCHOST_STATE_W0_SLCHOST_STATE1_Pos = 0x8 + // Bit mask of SLCHOST_STATE1 field. + SLCHOST_STATE_W0_SLCHOST_STATE1_Msk = 0xff00 + // Position of SLCHOST_STATE2 field. + SLCHOST_STATE_W0_SLCHOST_STATE2_Pos = 0x10 + // Bit mask of SLCHOST_STATE2 field. + SLCHOST_STATE_W0_SLCHOST_STATE2_Msk = 0xff0000 + // Position of SLCHOST_STATE3 field. + SLCHOST_STATE_W0_SLCHOST_STATE3_Pos = 0x18 + // Bit mask of SLCHOST_STATE3 field. + SLCHOST_STATE_W0_SLCHOST_STATE3_Msk = 0xff000000 + + // STATE_W1: *******Description*********** + // Position of SLCHOST_STATE4 field. + SLCHOST_STATE_W1_SLCHOST_STATE4_Pos = 0x0 + // Bit mask of SLCHOST_STATE4 field. + SLCHOST_STATE_W1_SLCHOST_STATE4_Msk = 0xff + // Position of SLCHOST_STATE5 field. + SLCHOST_STATE_W1_SLCHOST_STATE5_Pos = 0x8 + // Bit mask of SLCHOST_STATE5 field. + SLCHOST_STATE_W1_SLCHOST_STATE5_Msk = 0xff00 + // Position of SLCHOST_STATE6 field. + SLCHOST_STATE_W1_SLCHOST_STATE6_Pos = 0x10 + // Bit mask of SLCHOST_STATE6 field. + SLCHOST_STATE_W1_SLCHOST_STATE6_Msk = 0xff0000 + // Position of SLCHOST_STATE7 field. + SLCHOST_STATE_W1_SLCHOST_STATE7_Pos = 0x18 + // Bit mask of SLCHOST_STATE7 field. + SLCHOST_STATE_W1_SLCHOST_STATE7_Msk = 0xff000000 + + // CONF_W0: *******Description*********** + // Position of SLCHOST_CONF0 field. + SLCHOST_CONF_W0_SLCHOST_CONF0_Pos = 0x0 + // Bit mask of SLCHOST_CONF0 field. + SLCHOST_CONF_W0_SLCHOST_CONF0_Msk = 0xff + // Position of SLCHOST_CONF1 field. + SLCHOST_CONF_W0_SLCHOST_CONF1_Pos = 0x8 + // Bit mask of SLCHOST_CONF1 field. + SLCHOST_CONF_W0_SLCHOST_CONF1_Msk = 0xff00 + // Position of SLCHOST_CONF2 field. + SLCHOST_CONF_W0_SLCHOST_CONF2_Pos = 0x10 + // Bit mask of SLCHOST_CONF2 field. + SLCHOST_CONF_W0_SLCHOST_CONF2_Msk = 0xff0000 + // Position of SLCHOST_CONF3 field. + SLCHOST_CONF_W0_SLCHOST_CONF3_Pos = 0x18 + // Bit mask of SLCHOST_CONF3 field. + SLCHOST_CONF_W0_SLCHOST_CONF3_Msk = 0xff000000 + + // CONF_W1: *******Description*********** + // Position of SLCHOST_CONF4 field. + SLCHOST_CONF_W1_SLCHOST_CONF4_Pos = 0x0 + // Bit mask of SLCHOST_CONF4 field. + SLCHOST_CONF_W1_SLCHOST_CONF4_Msk = 0xff + // Position of SLCHOST_CONF5 field. + SLCHOST_CONF_W1_SLCHOST_CONF5_Pos = 0x8 + // Bit mask of SLCHOST_CONF5 field. + SLCHOST_CONF_W1_SLCHOST_CONF5_Msk = 0xff00 + // Position of SLCHOST_CONF6 field. + SLCHOST_CONF_W1_SLCHOST_CONF6_Pos = 0x10 + // Bit mask of SLCHOST_CONF6 field. + SLCHOST_CONF_W1_SLCHOST_CONF6_Msk = 0xff0000 + // Position of SLCHOST_CONF7 field. + SLCHOST_CONF_W1_SLCHOST_CONF7_Pos = 0x18 + // Bit mask of SLCHOST_CONF7 field. + SLCHOST_CONF_W1_SLCHOST_CONF7_Msk = 0xff000000 + + // CONF_W2: *******Description*********** + // Position of SLCHOST_CONF8 field. + SLCHOST_CONF_W2_SLCHOST_CONF8_Pos = 0x0 + // Bit mask of SLCHOST_CONF8 field. + SLCHOST_CONF_W2_SLCHOST_CONF8_Msk = 0xff + // Position of SLCHOST_CONF9 field. + SLCHOST_CONF_W2_SLCHOST_CONF9_Pos = 0x8 + // Bit mask of SLCHOST_CONF9 field. + SLCHOST_CONF_W2_SLCHOST_CONF9_Msk = 0xff00 + // Position of SLCHOST_CONF10 field. + SLCHOST_CONF_W2_SLCHOST_CONF10_Pos = 0x10 + // Bit mask of SLCHOST_CONF10 field. + SLCHOST_CONF_W2_SLCHOST_CONF10_Msk = 0xff0000 + // Position of SLCHOST_CONF11 field. + SLCHOST_CONF_W2_SLCHOST_CONF11_Pos = 0x18 + // Bit mask of SLCHOST_CONF11 field. + SLCHOST_CONF_W2_SLCHOST_CONF11_Msk = 0xff000000 + + // CONF_W3: *******Description*********** + // Position of SLCHOST_CONF12 field. + SLCHOST_CONF_W3_SLCHOST_CONF12_Pos = 0x0 + // Bit mask of SLCHOST_CONF12 field. + SLCHOST_CONF_W3_SLCHOST_CONF12_Msk = 0xff + // Position of SLCHOST_CONF13 field. + SLCHOST_CONF_W3_SLCHOST_CONF13_Pos = 0x8 + // Bit mask of SLCHOST_CONF13 field. + SLCHOST_CONF_W3_SLCHOST_CONF13_Msk = 0xff00 + // Position of SLCHOST_CONF14 field. + SLCHOST_CONF_W3_SLCHOST_CONF14_Pos = 0x10 + // Bit mask of SLCHOST_CONF14 field. + SLCHOST_CONF_W3_SLCHOST_CONF14_Msk = 0xff0000 + // Position of SLCHOST_CONF15 field. + SLCHOST_CONF_W3_SLCHOST_CONF15_Pos = 0x18 + // Bit mask of SLCHOST_CONF15 field. + SLCHOST_CONF_W3_SLCHOST_CONF15_Msk = 0xff000000 + + // CONF_W4: *******Description*********** + // Position of SLCHOST_CONF16 field. + SLCHOST_CONF_W4_SLCHOST_CONF16_Pos = 0x0 + // Bit mask of SLCHOST_CONF16 field. + SLCHOST_CONF_W4_SLCHOST_CONF16_Msk = 0xff + // Position of SLCHOST_CONF17 field. + SLCHOST_CONF_W4_SLCHOST_CONF17_Pos = 0x8 + // Bit mask of SLCHOST_CONF17 field. + SLCHOST_CONF_W4_SLCHOST_CONF17_Msk = 0xff00 + // Position of SLCHOST_CONF18 field. + SLCHOST_CONF_W4_SLCHOST_CONF18_Pos = 0x10 + // Bit mask of SLCHOST_CONF18 field. + SLCHOST_CONF_W4_SLCHOST_CONF18_Msk = 0xff0000 + // Position of SLCHOST_CONF19 field. + SLCHOST_CONF_W4_SLCHOST_CONF19_Pos = 0x18 + // Bit mask of SLCHOST_CONF19 field. + SLCHOST_CONF_W4_SLCHOST_CONF19_Msk = 0xff000000 + + // CONF_W5: *******Description*********** + // Position of SLCHOST_CONF20 field. + SLCHOST_CONF_W5_SLCHOST_CONF20_Pos = 0x0 + // Bit mask of SLCHOST_CONF20 field. + SLCHOST_CONF_W5_SLCHOST_CONF20_Msk = 0xff + // Position of SLCHOST_CONF21 field. + SLCHOST_CONF_W5_SLCHOST_CONF21_Pos = 0x8 + // Bit mask of SLCHOST_CONF21 field. + SLCHOST_CONF_W5_SLCHOST_CONF21_Msk = 0xff00 + // Position of SLCHOST_CONF22 field. + SLCHOST_CONF_W5_SLCHOST_CONF22_Pos = 0x10 + // Bit mask of SLCHOST_CONF22 field. + SLCHOST_CONF_W5_SLCHOST_CONF22_Msk = 0xff0000 + // Position of SLCHOST_CONF23 field. + SLCHOST_CONF_W5_SLCHOST_CONF23_Pos = 0x18 + // Bit mask of SLCHOST_CONF23 field. + SLCHOST_CONF_W5_SLCHOST_CONF23_Msk = 0xff000000 + + // WIN_CMD: *******Description*********** + // Position of SLCHOST_WIN_CMD field. + SLCHOST_WIN_CMD_SLCHOST_WIN_CMD_Pos = 0x0 + // Bit mask of SLCHOST_WIN_CMD field. + SLCHOST_WIN_CMD_SLCHOST_WIN_CMD_Msk = 0xffff + + // CONF_W6: *******Description*********** + // Position of SLCHOST_CONF24 field. + SLCHOST_CONF_W6_SLCHOST_CONF24_Pos = 0x0 + // Bit mask of SLCHOST_CONF24 field. + SLCHOST_CONF_W6_SLCHOST_CONF24_Msk = 0xff + // Position of SLCHOST_CONF25 field. + SLCHOST_CONF_W6_SLCHOST_CONF25_Pos = 0x8 + // Bit mask of SLCHOST_CONF25 field. + SLCHOST_CONF_W6_SLCHOST_CONF25_Msk = 0xff00 + // Position of SLCHOST_CONF26 field. + SLCHOST_CONF_W6_SLCHOST_CONF26_Pos = 0x10 + // Bit mask of SLCHOST_CONF26 field. + SLCHOST_CONF_W6_SLCHOST_CONF26_Msk = 0xff0000 + // Position of SLCHOST_CONF27 field. + SLCHOST_CONF_W6_SLCHOST_CONF27_Pos = 0x18 + // Bit mask of SLCHOST_CONF27 field. + SLCHOST_CONF_W6_SLCHOST_CONF27_Msk = 0xff000000 + + // CONF_W7: *******Description*********** + // Position of SLCHOST_CONF28 field. + SLCHOST_CONF_W7_SLCHOST_CONF28_Pos = 0x0 + // Bit mask of SLCHOST_CONF28 field. + SLCHOST_CONF_W7_SLCHOST_CONF28_Msk = 0xff + // Position of SLCHOST_CONF29 field. + SLCHOST_CONF_W7_SLCHOST_CONF29_Pos = 0x8 + // Bit mask of SLCHOST_CONF29 field. + SLCHOST_CONF_W7_SLCHOST_CONF29_Msk = 0xff00 + // Position of SLCHOST_CONF30 field. + SLCHOST_CONF_W7_SLCHOST_CONF30_Pos = 0x10 + // Bit mask of SLCHOST_CONF30 field. + SLCHOST_CONF_W7_SLCHOST_CONF30_Msk = 0xff0000 + // Position of SLCHOST_CONF31 field. + SLCHOST_CONF_W7_SLCHOST_CONF31_Pos = 0x18 + // Bit mask of SLCHOST_CONF31 field. + SLCHOST_CONF_W7_SLCHOST_CONF31_Msk = 0xff000000 + + // PKT_LEN0: *******Description*********** + // Position of HOSTSLCHOST_SLC0_LEN0 field. + SLCHOST_PKT_LEN0_HOSTSLCHOST_SLC0_LEN0_Pos = 0x0 + // Bit mask of HOSTSLCHOST_SLC0_LEN0 field. + SLCHOST_PKT_LEN0_HOSTSLCHOST_SLC0_LEN0_Msk = 0xfffff + // Position of HOSTSLCHOST_SLC0_LEN0_CHECK field. + SLCHOST_PKT_LEN0_HOSTSLCHOST_SLC0_LEN0_CHECK_Pos = 0x14 + // Bit mask of HOSTSLCHOST_SLC0_LEN0_CHECK field. + SLCHOST_PKT_LEN0_HOSTSLCHOST_SLC0_LEN0_CHECK_Msk = 0xfff00000 + + // PKT_LEN1: *******Description*********** + // Position of HOSTSLCHOST_SLC0_LEN1 field. + SLCHOST_PKT_LEN1_HOSTSLCHOST_SLC0_LEN1_Pos = 0x0 + // Bit mask of HOSTSLCHOST_SLC0_LEN1 field. + SLCHOST_PKT_LEN1_HOSTSLCHOST_SLC0_LEN1_Msk = 0xfffff + // Position of HOSTSLCHOST_SLC0_LEN1_CHECK field. + SLCHOST_PKT_LEN1_HOSTSLCHOST_SLC0_LEN1_CHECK_Pos = 0x14 + // Bit mask of HOSTSLCHOST_SLC0_LEN1_CHECK field. + SLCHOST_PKT_LEN1_HOSTSLCHOST_SLC0_LEN1_CHECK_Msk = 0xfff00000 + + // PKT_LEN2: *******Description*********** + // Position of HOSTSLCHOST_SLC0_LEN2 field. + SLCHOST_PKT_LEN2_HOSTSLCHOST_SLC0_LEN2_Pos = 0x0 + // Bit mask of HOSTSLCHOST_SLC0_LEN2 field. + SLCHOST_PKT_LEN2_HOSTSLCHOST_SLC0_LEN2_Msk = 0xfffff + // Position of HOSTSLCHOST_SLC0_LEN2_CHECK field. + SLCHOST_PKT_LEN2_HOSTSLCHOST_SLC0_LEN2_CHECK_Pos = 0x14 + // Bit mask of HOSTSLCHOST_SLC0_LEN2_CHECK field. + SLCHOST_PKT_LEN2_HOSTSLCHOST_SLC0_LEN2_CHECK_Msk = 0xfff00000 + + // CONF_W8: *******Description*********** + // Position of SLCHOST_CONF32 field. + SLCHOST_CONF_W8_SLCHOST_CONF32_Pos = 0x0 + // Bit mask of SLCHOST_CONF32 field. + SLCHOST_CONF_W8_SLCHOST_CONF32_Msk = 0xff + // Position of SLCHOST_CONF33 field. + SLCHOST_CONF_W8_SLCHOST_CONF33_Pos = 0x8 + // Bit mask of SLCHOST_CONF33 field. + SLCHOST_CONF_W8_SLCHOST_CONF33_Msk = 0xff00 + // Position of SLCHOST_CONF34 field. + SLCHOST_CONF_W8_SLCHOST_CONF34_Pos = 0x10 + // Bit mask of SLCHOST_CONF34 field. + SLCHOST_CONF_W8_SLCHOST_CONF34_Msk = 0xff0000 + // Position of SLCHOST_CONF35 field. + SLCHOST_CONF_W8_SLCHOST_CONF35_Pos = 0x18 + // Bit mask of SLCHOST_CONF35 field. + SLCHOST_CONF_W8_SLCHOST_CONF35_Msk = 0xff000000 + + // CONF_W9: *******Description*********** + // Position of SLCHOST_CONF36 field. + SLCHOST_CONF_W9_SLCHOST_CONF36_Pos = 0x0 + // Bit mask of SLCHOST_CONF36 field. + SLCHOST_CONF_W9_SLCHOST_CONF36_Msk = 0xff + // Position of SLCHOST_CONF37 field. + SLCHOST_CONF_W9_SLCHOST_CONF37_Pos = 0x8 + // Bit mask of SLCHOST_CONF37 field. + SLCHOST_CONF_W9_SLCHOST_CONF37_Msk = 0xff00 + // Position of SLCHOST_CONF38 field. + SLCHOST_CONF_W9_SLCHOST_CONF38_Pos = 0x10 + // Bit mask of SLCHOST_CONF38 field. + SLCHOST_CONF_W9_SLCHOST_CONF38_Msk = 0xff0000 + // Position of SLCHOST_CONF39 field. + SLCHOST_CONF_W9_SLCHOST_CONF39_Pos = 0x18 + // Bit mask of SLCHOST_CONF39 field. + SLCHOST_CONF_W9_SLCHOST_CONF39_Msk = 0xff000000 + + // CONF_W10: *******Description*********** + // Position of SLCHOST_CONF40 field. + SLCHOST_CONF_W10_SLCHOST_CONF40_Pos = 0x0 + // Bit mask of SLCHOST_CONF40 field. + SLCHOST_CONF_W10_SLCHOST_CONF40_Msk = 0xff + // Position of SLCHOST_CONF41 field. + SLCHOST_CONF_W10_SLCHOST_CONF41_Pos = 0x8 + // Bit mask of SLCHOST_CONF41 field. + SLCHOST_CONF_W10_SLCHOST_CONF41_Msk = 0xff00 + // Position of SLCHOST_CONF42 field. + SLCHOST_CONF_W10_SLCHOST_CONF42_Pos = 0x10 + // Bit mask of SLCHOST_CONF42 field. + SLCHOST_CONF_W10_SLCHOST_CONF42_Msk = 0xff0000 + // Position of SLCHOST_CONF43 field. + SLCHOST_CONF_W10_SLCHOST_CONF43_Pos = 0x18 + // Bit mask of SLCHOST_CONF43 field. + SLCHOST_CONF_W10_SLCHOST_CONF43_Msk = 0xff000000 + + // CONF_W11: *******Description*********** + // Position of SLCHOST_CONF44 field. + SLCHOST_CONF_W11_SLCHOST_CONF44_Pos = 0x0 + // Bit mask of SLCHOST_CONF44 field. + SLCHOST_CONF_W11_SLCHOST_CONF44_Msk = 0xff + // Position of SLCHOST_CONF45 field. + SLCHOST_CONF_W11_SLCHOST_CONF45_Pos = 0x8 + // Bit mask of SLCHOST_CONF45 field. + SLCHOST_CONF_W11_SLCHOST_CONF45_Msk = 0xff00 + // Position of SLCHOST_CONF46 field. + SLCHOST_CONF_W11_SLCHOST_CONF46_Pos = 0x10 + // Bit mask of SLCHOST_CONF46 field. + SLCHOST_CONF_W11_SLCHOST_CONF46_Msk = 0xff0000 + // Position of SLCHOST_CONF47 field. + SLCHOST_CONF_W11_SLCHOST_CONF47_Pos = 0x18 + // Bit mask of SLCHOST_CONF47 field. + SLCHOST_CONF_W11_SLCHOST_CONF47_Msk = 0xff000000 + + // CONF_W12: *******Description*********** + // Position of SLCHOST_CONF48 field. + SLCHOST_CONF_W12_SLCHOST_CONF48_Pos = 0x0 + // Bit mask of SLCHOST_CONF48 field. + SLCHOST_CONF_W12_SLCHOST_CONF48_Msk = 0xff + // Position of SLCHOST_CONF49 field. + SLCHOST_CONF_W12_SLCHOST_CONF49_Pos = 0x8 + // Bit mask of SLCHOST_CONF49 field. + SLCHOST_CONF_W12_SLCHOST_CONF49_Msk = 0xff00 + // Position of SLCHOST_CONF50 field. + SLCHOST_CONF_W12_SLCHOST_CONF50_Pos = 0x10 + // Bit mask of SLCHOST_CONF50 field. + SLCHOST_CONF_W12_SLCHOST_CONF50_Msk = 0xff0000 + // Position of SLCHOST_CONF51 field. + SLCHOST_CONF_W12_SLCHOST_CONF51_Pos = 0x18 + // Bit mask of SLCHOST_CONF51 field. + SLCHOST_CONF_W12_SLCHOST_CONF51_Msk = 0xff000000 + + // CONF_W13: *******Description*********** + // Position of SLCHOST_CONF52 field. + SLCHOST_CONF_W13_SLCHOST_CONF52_Pos = 0x0 + // Bit mask of SLCHOST_CONF52 field. + SLCHOST_CONF_W13_SLCHOST_CONF52_Msk = 0xff + // Position of SLCHOST_CONF53 field. + SLCHOST_CONF_W13_SLCHOST_CONF53_Pos = 0x8 + // Bit mask of SLCHOST_CONF53 field. + SLCHOST_CONF_W13_SLCHOST_CONF53_Msk = 0xff00 + // Position of SLCHOST_CONF54 field. + SLCHOST_CONF_W13_SLCHOST_CONF54_Pos = 0x10 + // Bit mask of SLCHOST_CONF54 field. + SLCHOST_CONF_W13_SLCHOST_CONF54_Msk = 0xff0000 + // Position of SLCHOST_CONF55 field. + SLCHOST_CONF_W13_SLCHOST_CONF55_Pos = 0x18 + // Bit mask of SLCHOST_CONF55 field. + SLCHOST_CONF_W13_SLCHOST_CONF55_Msk = 0xff000000 + + // CONF_W14: *******Description*********** + // Position of SLCHOST_CONF56 field. + SLCHOST_CONF_W14_SLCHOST_CONF56_Pos = 0x0 + // Bit mask of SLCHOST_CONF56 field. + SLCHOST_CONF_W14_SLCHOST_CONF56_Msk = 0xff + // Position of SLCHOST_CONF57 field. + SLCHOST_CONF_W14_SLCHOST_CONF57_Pos = 0x8 + // Bit mask of SLCHOST_CONF57 field. + SLCHOST_CONF_W14_SLCHOST_CONF57_Msk = 0xff00 + // Position of SLCHOST_CONF58 field. + SLCHOST_CONF_W14_SLCHOST_CONF58_Pos = 0x10 + // Bit mask of SLCHOST_CONF58 field. + SLCHOST_CONF_W14_SLCHOST_CONF58_Msk = 0xff0000 + // Position of SLCHOST_CONF59 field. + SLCHOST_CONF_W14_SLCHOST_CONF59_Pos = 0x18 + // Bit mask of SLCHOST_CONF59 field. + SLCHOST_CONF_W14_SLCHOST_CONF59_Msk = 0xff000000 + + // CONF_W15: *******Description*********** + // Position of SLCHOST_CONF60 field. + SLCHOST_CONF_W15_SLCHOST_CONF60_Pos = 0x0 + // Bit mask of SLCHOST_CONF60 field. + SLCHOST_CONF_W15_SLCHOST_CONF60_Msk = 0xff + // Position of SLCHOST_CONF61 field. + SLCHOST_CONF_W15_SLCHOST_CONF61_Pos = 0x8 + // Bit mask of SLCHOST_CONF61 field. + SLCHOST_CONF_W15_SLCHOST_CONF61_Msk = 0xff00 + // Position of SLCHOST_CONF62 field. + SLCHOST_CONF_W15_SLCHOST_CONF62_Pos = 0x10 + // Bit mask of SLCHOST_CONF62 field. + SLCHOST_CONF_W15_SLCHOST_CONF62_Msk = 0xff0000 + // Position of SLCHOST_CONF63 field. + SLCHOST_CONF_W15_SLCHOST_CONF63_Pos = 0x18 + // Bit mask of SLCHOST_CONF63 field. + SLCHOST_CONF_W15_SLCHOST_CONF63_Msk = 0xff000000 + + // CHECK_SUM0: *******Description*********** + // Position of SLCHOST_CHECK_SUM0 field. + SLCHOST_CHECK_SUM0_SLCHOST_CHECK_SUM0_Pos = 0x0 + // Bit mask of SLCHOST_CHECK_SUM0 field. + SLCHOST_CHECK_SUM0_SLCHOST_CHECK_SUM0_Msk = 0xffffffff + + // CHECK_SUM1: *******Description*********** + // Position of SLCHOST_CHECK_SUM1 field. + SLCHOST_CHECK_SUM1_SLCHOST_CHECK_SUM1_Pos = 0x0 + // Bit mask of SLCHOST_CHECK_SUM1 field. + SLCHOST_CHECK_SUM1_SLCHOST_CHECK_SUM1_Msk = 0xffffffff + + // SLC1HOST_TOKEN_RDATA: *******Description*********** + // Position of SLC1_TOKEN0 field. + SLCHOST_SLC1HOST_TOKEN_RDATA_SLC1_TOKEN0_Pos = 0x0 + // Bit mask of SLC1_TOKEN0 field. + SLCHOST_SLC1HOST_TOKEN_RDATA_SLC1_TOKEN0_Msk = 0xfff + // Position of SLC1_RX_PF_VALID field. + SLCHOST_SLC1HOST_TOKEN_RDATA_SLC1_RX_PF_VALID_Pos = 0xc + // Bit mask of SLC1_RX_PF_VALID field. + SLCHOST_SLC1HOST_TOKEN_RDATA_SLC1_RX_PF_VALID_Msk = 0x1000 + // Bit SLC1_RX_PF_VALID. + SLCHOST_SLC1HOST_TOKEN_RDATA_SLC1_RX_PF_VALID = 0x1000 + // Position of HOSTSLCHOST_SLC1_TOKEN1 field. + SLCHOST_SLC1HOST_TOKEN_RDATA_HOSTSLCHOST_SLC1_TOKEN1_Pos = 0x10 + // Bit mask of HOSTSLCHOST_SLC1_TOKEN1 field. + SLCHOST_SLC1HOST_TOKEN_RDATA_HOSTSLCHOST_SLC1_TOKEN1_Msk = 0xfff0000 + // Position of SLC1_RX_PF_EOF field. + SLCHOST_SLC1HOST_TOKEN_RDATA_SLC1_RX_PF_EOF_Pos = 0x1c + // Bit mask of SLC1_RX_PF_EOF field. + SLCHOST_SLC1HOST_TOKEN_RDATA_SLC1_RX_PF_EOF_Msk = 0xf0000000 + + // SLC0HOST_TOKEN_WDATA: *******Description*********** + // Position of SLC0HOST_TOKEN0_WD field. + SLCHOST_SLC0HOST_TOKEN_WDATA_SLC0HOST_TOKEN0_WD_Pos = 0x0 + // Bit mask of SLC0HOST_TOKEN0_WD field. + SLCHOST_SLC0HOST_TOKEN_WDATA_SLC0HOST_TOKEN0_WD_Msk = 0xfff + // Position of SLC0HOST_TOKEN1_WD field. + SLCHOST_SLC0HOST_TOKEN_WDATA_SLC0HOST_TOKEN1_WD_Pos = 0x10 + // Bit mask of SLC0HOST_TOKEN1_WD field. + SLCHOST_SLC0HOST_TOKEN_WDATA_SLC0HOST_TOKEN1_WD_Msk = 0xfff0000 + + // SLC1HOST_TOKEN_WDATA: *******Description*********** + // Position of SLC1HOST_TOKEN0_WD field. + SLCHOST_SLC1HOST_TOKEN_WDATA_SLC1HOST_TOKEN0_WD_Pos = 0x0 + // Bit mask of SLC1HOST_TOKEN0_WD field. + SLCHOST_SLC1HOST_TOKEN_WDATA_SLC1HOST_TOKEN0_WD_Msk = 0xfff + // Position of SLC1HOST_TOKEN1_WD field. + SLCHOST_SLC1HOST_TOKEN_WDATA_SLC1HOST_TOKEN1_WD_Pos = 0x10 + // Bit mask of SLC1HOST_TOKEN1_WD field. + SLCHOST_SLC1HOST_TOKEN_WDATA_SLC1HOST_TOKEN1_WD_Msk = 0xfff0000 + + // TOKEN_CON: *******Description*********** + // Position of SLC0HOST_TOKEN0_DEC field. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN0_DEC_Pos = 0x0 + // Bit mask of SLC0HOST_TOKEN0_DEC field. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN0_DEC_Msk = 0x1 + // Bit SLC0HOST_TOKEN0_DEC. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN0_DEC = 0x1 + // Position of SLC0HOST_TOKEN1_DEC field. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN1_DEC_Pos = 0x1 + // Bit mask of SLC0HOST_TOKEN1_DEC field. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN1_DEC_Msk = 0x2 + // Bit SLC0HOST_TOKEN1_DEC. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN1_DEC = 0x2 + // Position of SLC0HOST_TOKEN0_WR field. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN0_WR_Pos = 0x2 + // Bit mask of SLC0HOST_TOKEN0_WR field. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN0_WR_Msk = 0x4 + // Bit SLC0HOST_TOKEN0_WR. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN0_WR = 0x4 + // Position of SLC0HOST_TOKEN1_WR field. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN1_WR_Pos = 0x3 + // Bit mask of SLC0HOST_TOKEN1_WR field. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN1_WR_Msk = 0x8 + // Bit SLC0HOST_TOKEN1_WR. + SLCHOST_TOKEN_CON_SLC0HOST_TOKEN1_WR = 0x8 + // Position of SLC1HOST_TOKEN0_DEC field. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN0_DEC_Pos = 0x4 + // Bit mask of SLC1HOST_TOKEN0_DEC field. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN0_DEC_Msk = 0x10 + // Bit SLC1HOST_TOKEN0_DEC. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN0_DEC = 0x10 + // Position of SLC1HOST_TOKEN1_DEC field. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN1_DEC_Pos = 0x5 + // Bit mask of SLC1HOST_TOKEN1_DEC field. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN1_DEC_Msk = 0x20 + // Bit SLC1HOST_TOKEN1_DEC. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN1_DEC = 0x20 + // Position of SLC1HOST_TOKEN0_WR field. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN0_WR_Pos = 0x6 + // Bit mask of SLC1HOST_TOKEN0_WR field. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN0_WR_Msk = 0x40 + // Bit SLC1HOST_TOKEN0_WR. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN0_WR = 0x40 + // Position of SLC1HOST_TOKEN1_WR field. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN1_WR_Pos = 0x7 + // Bit mask of SLC1HOST_TOKEN1_WR field. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN1_WR_Msk = 0x80 + // Bit SLC1HOST_TOKEN1_WR. + SLCHOST_TOKEN_CON_SLC1HOST_TOKEN1_WR = 0x80 + // Position of SLC0HOST_LEN_WR field. + SLCHOST_TOKEN_CON_SLC0HOST_LEN_WR_Pos = 0x8 + // Bit mask of SLC0HOST_LEN_WR field. + SLCHOST_TOKEN_CON_SLC0HOST_LEN_WR_Msk = 0x100 + // Bit SLC0HOST_LEN_WR. + SLCHOST_TOKEN_CON_SLC0HOST_LEN_WR = 0x100 + + // SLC0HOST_INT_CLR: *******Description*********** + // Position of SLC0_TOHOST_BIT0_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT0_INT_CLR_Pos = 0x0 + // Bit mask of SLC0_TOHOST_BIT0_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT0_INT_CLR_Msk = 0x1 + // Bit SLC0_TOHOST_BIT0_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT0_INT_CLR = 0x1 + // Position of SLC0_TOHOST_BIT1_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT1_INT_CLR_Pos = 0x1 + // Bit mask of SLC0_TOHOST_BIT1_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT1_INT_CLR_Msk = 0x2 + // Bit SLC0_TOHOST_BIT1_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT1_INT_CLR = 0x2 + // Position of SLC0_TOHOST_BIT2_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT2_INT_CLR_Pos = 0x2 + // Bit mask of SLC0_TOHOST_BIT2_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT2_INT_CLR_Msk = 0x4 + // Bit SLC0_TOHOST_BIT2_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT2_INT_CLR = 0x4 + // Position of SLC0_TOHOST_BIT3_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT3_INT_CLR_Pos = 0x3 + // Bit mask of SLC0_TOHOST_BIT3_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT3_INT_CLR_Msk = 0x8 + // Bit SLC0_TOHOST_BIT3_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT3_INT_CLR = 0x8 + // Position of SLC0_TOHOST_BIT4_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT4_INT_CLR_Pos = 0x4 + // Bit mask of SLC0_TOHOST_BIT4_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT4_INT_CLR_Msk = 0x10 + // Bit SLC0_TOHOST_BIT4_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT4_INT_CLR = 0x10 + // Position of SLC0_TOHOST_BIT5_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT5_INT_CLR_Pos = 0x5 + // Bit mask of SLC0_TOHOST_BIT5_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT5_INT_CLR_Msk = 0x20 + // Bit SLC0_TOHOST_BIT5_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT5_INT_CLR = 0x20 + // Position of SLC0_TOHOST_BIT6_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT6_INT_CLR_Pos = 0x6 + // Bit mask of SLC0_TOHOST_BIT6_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT6_INT_CLR_Msk = 0x40 + // Bit SLC0_TOHOST_BIT6_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT6_INT_CLR = 0x40 + // Position of SLC0_TOHOST_BIT7_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT7_INT_CLR_Pos = 0x7 + // Bit mask of SLC0_TOHOST_BIT7_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT7_INT_CLR_Msk = 0x80 + // Bit SLC0_TOHOST_BIT7_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOHOST_BIT7_INT_CLR = 0x80 + // Position of SLC0_TOKEN0_1TO0_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR_Pos = 0x8 + // Bit mask of SLC0_TOKEN0_1TO0_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR_Msk = 0x100 + // Bit SLC0_TOKEN0_1TO0_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN0_1TO0_INT_CLR = 0x100 + // Position of SLC0_TOKEN1_1TO0_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR_Pos = 0x9 + // Bit mask of SLC0_TOKEN1_1TO0_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR_Msk = 0x200 + // Bit SLC0_TOKEN1_1TO0_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN1_1TO0_INT_CLR = 0x200 + // Position of SLC0_TOKEN0_0TO1_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN0_0TO1_INT_CLR_Pos = 0xa + // Bit mask of SLC0_TOKEN0_0TO1_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN0_0TO1_INT_CLR_Msk = 0x400 + // Bit SLC0_TOKEN0_0TO1_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN0_0TO1_INT_CLR = 0x400 + // Position of SLC0_TOKEN1_0TO1_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN1_0TO1_INT_CLR_Pos = 0xb + // Bit mask of SLC0_TOKEN1_0TO1_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN1_0TO1_INT_CLR_Msk = 0x800 + // Bit SLC0_TOKEN1_0TO1_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TOKEN1_0TO1_INT_CLR = 0x800 + // Position of SLC0HOST_RX_SOF_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_RX_SOF_INT_CLR_Pos = 0xc + // Bit mask of SLC0HOST_RX_SOF_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_RX_SOF_INT_CLR_Msk = 0x1000 + // Bit SLC0HOST_RX_SOF_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_RX_SOF_INT_CLR = 0x1000 + // Position of SLC0HOST_RX_EOF_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_RX_EOF_INT_CLR_Pos = 0xd + // Bit mask of SLC0HOST_RX_EOF_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_RX_EOF_INT_CLR_Msk = 0x2000 + // Bit SLC0HOST_RX_EOF_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_RX_EOF_INT_CLR = 0x2000 + // Position of SLC0HOST_RX_START_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_RX_START_INT_CLR_Pos = 0xe + // Bit mask of SLC0HOST_RX_START_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_RX_START_INT_CLR_Msk = 0x4000 + // Bit SLC0HOST_RX_START_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_RX_START_INT_CLR = 0x4000 + // Position of SLC0HOST_TX_START_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_TX_START_INT_CLR_Pos = 0xf + // Bit mask of SLC0HOST_TX_START_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_TX_START_INT_CLR_Msk = 0x8000 + // Bit SLC0HOST_TX_START_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0HOST_TX_START_INT_CLR = 0x8000 + // Position of SLC0_RX_UDF_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_RX_UDF_INT_CLR_Pos = 0x10 + // Bit mask of SLC0_RX_UDF_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_RX_UDF_INT_CLR_Msk = 0x10000 + // Bit SLC0_RX_UDF_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_RX_UDF_INT_CLR = 0x10000 + // Position of SLC0_TX_OVF_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TX_OVF_INT_CLR_Pos = 0x11 + // Bit mask of SLC0_TX_OVF_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TX_OVF_INT_CLR_Msk = 0x20000 + // Bit SLC0_TX_OVF_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_TX_OVF_INT_CLR = 0x20000 + // Position of SLC0_RX_PF_VALID_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_RX_PF_VALID_INT_CLR_Pos = 0x12 + // Bit mask of SLC0_RX_PF_VALID_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_RX_PF_VALID_INT_CLR_Msk = 0x40000 + // Bit SLC0_RX_PF_VALID_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_RX_PF_VALID_INT_CLR = 0x40000 + // Position of SLC0_EXT_BIT0_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT0_INT_CLR_Pos = 0x13 + // Bit mask of SLC0_EXT_BIT0_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT0_INT_CLR_Msk = 0x80000 + // Bit SLC0_EXT_BIT0_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT0_INT_CLR = 0x80000 + // Position of SLC0_EXT_BIT1_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT1_INT_CLR_Pos = 0x14 + // Bit mask of SLC0_EXT_BIT1_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT1_INT_CLR_Msk = 0x100000 + // Bit SLC0_EXT_BIT1_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT1_INT_CLR = 0x100000 + // Position of SLC0_EXT_BIT2_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT2_INT_CLR_Pos = 0x15 + // Bit mask of SLC0_EXT_BIT2_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT2_INT_CLR_Msk = 0x200000 + // Bit SLC0_EXT_BIT2_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT2_INT_CLR = 0x200000 + // Position of SLC0_EXT_BIT3_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT3_INT_CLR_Pos = 0x16 + // Bit mask of SLC0_EXT_BIT3_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT3_INT_CLR_Msk = 0x400000 + // Bit SLC0_EXT_BIT3_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_EXT_BIT3_INT_CLR = 0x400000 + // Position of SLC0_RX_NEW_PACKET_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_RX_NEW_PACKET_INT_CLR_Pos = 0x17 + // Bit mask of SLC0_RX_NEW_PACKET_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_RX_NEW_PACKET_INT_CLR_Msk = 0x800000 + // Bit SLC0_RX_NEW_PACKET_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_RX_NEW_PACKET_INT_CLR = 0x800000 + // Position of SLC0_HOST_RD_RETRY_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_HOST_RD_RETRY_INT_CLR_Pos = 0x18 + // Bit mask of SLC0_HOST_RD_RETRY_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_SLC0_HOST_RD_RETRY_INT_CLR_Msk = 0x1000000 + // Bit SLC0_HOST_RD_RETRY_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_SLC0_HOST_RD_RETRY_INT_CLR = 0x1000000 + // Position of GPIO_SDIO_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_GPIO_SDIO_INT_CLR_Pos = 0x19 + // Bit mask of GPIO_SDIO_INT_CLR field. + SLCHOST_SLC0HOST_INT_CLR_GPIO_SDIO_INT_CLR_Msk = 0x2000000 + // Bit GPIO_SDIO_INT_CLR. + SLCHOST_SLC0HOST_INT_CLR_GPIO_SDIO_INT_CLR = 0x2000000 + + // SLC1HOST_INT_CLR: *******Description*********** + // Position of SLC1_TOHOST_BIT0_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT0_INT_CLR_Pos = 0x0 + // Bit mask of SLC1_TOHOST_BIT0_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT0_INT_CLR_Msk = 0x1 + // Bit SLC1_TOHOST_BIT0_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT0_INT_CLR = 0x1 + // Position of SLC1_TOHOST_BIT1_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT1_INT_CLR_Pos = 0x1 + // Bit mask of SLC1_TOHOST_BIT1_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT1_INT_CLR_Msk = 0x2 + // Bit SLC1_TOHOST_BIT1_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT1_INT_CLR = 0x2 + // Position of SLC1_TOHOST_BIT2_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT2_INT_CLR_Pos = 0x2 + // Bit mask of SLC1_TOHOST_BIT2_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT2_INT_CLR_Msk = 0x4 + // Bit SLC1_TOHOST_BIT2_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT2_INT_CLR = 0x4 + // Position of SLC1_TOHOST_BIT3_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT3_INT_CLR_Pos = 0x3 + // Bit mask of SLC1_TOHOST_BIT3_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT3_INT_CLR_Msk = 0x8 + // Bit SLC1_TOHOST_BIT3_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT3_INT_CLR = 0x8 + // Position of SLC1_TOHOST_BIT4_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT4_INT_CLR_Pos = 0x4 + // Bit mask of SLC1_TOHOST_BIT4_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT4_INT_CLR_Msk = 0x10 + // Bit SLC1_TOHOST_BIT4_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT4_INT_CLR = 0x10 + // Position of SLC1_TOHOST_BIT5_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT5_INT_CLR_Pos = 0x5 + // Bit mask of SLC1_TOHOST_BIT5_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT5_INT_CLR_Msk = 0x20 + // Bit SLC1_TOHOST_BIT5_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT5_INT_CLR = 0x20 + // Position of SLC1_TOHOST_BIT6_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT6_INT_CLR_Pos = 0x6 + // Bit mask of SLC1_TOHOST_BIT6_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT6_INT_CLR_Msk = 0x40 + // Bit SLC1_TOHOST_BIT6_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT6_INT_CLR = 0x40 + // Position of SLC1_TOHOST_BIT7_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT7_INT_CLR_Pos = 0x7 + // Bit mask of SLC1_TOHOST_BIT7_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT7_INT_CLR_Msk = 0x80 + // Bit SLC1_TOHOST_BIT7_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOHOST_BIT7_INT_CLR = 0x80 + // Position of SLC1_TOKEN0_1TO0_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR_Pos = 0x8 + // Bit mask of SLC1_TOKEN0_1TO0_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR_Msk = 0x100 + // Bit SLC1_TOKEN0_1TO0_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN0_1TO0_INT_CLR = 0x100 + // Position of SLC1_TOKEN1_1TO0_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR_Pos = 0x9 + // Bit mask of SLC1_TOKEN1_1TO0_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR_Msk = 0x200 + // Bit SLC1_TOKEN1_1TO0_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN1_1TO0_INT_CLR = 0x200 + // Position of SLC1_TOKEN0_0TO1_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN0_0TO1_INT_CLR_Pos = 0xa + // Bit mask of SLC1_TOKEN0_0TO1_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN0_0TO1_INT_CLR_Msk = 0x400 + // Bit SLC1_TOKEN0_0TO1_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN0_0TO1_INT_CLR = 0x400 + // Position of SLC1_TOKEN1_0TO1_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN1_0TO1_INT_CLR_Pos = 0xb + // Bit mask of SLC1_TOKEN1_0TO1_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN1_0TO1_INT_CLR_Msk = 0x800 + // Bit SLC1_TOKEN1_0TO1_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TOKEN1_0TO1_INT_CLR = 0x800 + // Position of SLC1HOST_RX_SOF_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_RX_SOF_INT_CLR_Pos = 0xc + // Bit mask of SLC1HOST_RX_SOF_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_RX_SOF_INT_CLR_Msk = 0x1000 + // Bit SLC1HOST_RX_SOF_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_RX_SOF_INT_CLR = 0x1000 + // Position of SLC1HOST_RX_EOF_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_RX_EOF_INT_CLR_Pos = 0xd + // Bit mask of SLC1HOST_RX_EOF_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_RX_EOF_INT_CLR_Msk = 0x2000 + // Bit SLC1HOST_RX_EOF_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_RX_EOF_INT_CLR = 0x2000 + // Position of SLC1HOST_RX_START_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_RX_START_INT_CLR_Pos = 0xe + // Bit mask of SLC1HOST_RX_START_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_RX_START_INT_CLR_Msk = 0x4000 + // Bit SLC1HOST_RX_START_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_RX_START_INT_CLR = 0x4000 + // Position of SLC1HOST_TX_START_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_TX_START_INT_CLR_Pos = 0xf + // Bit mask of SLC1HOST_TX_START_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_TX_START_INT_CLR_Msk = 0x8000 + // Bit SLC1HOST_TX_START_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1HOST_TX_START_INT_CLR = 0x8000 + // Position of SLC1_RX_UDF_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_RX_UDF_INT_CLR_Pos = 0x10 + // Bit mask of SLC1_RX_UDF_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_RX_UDF_INT_CLR_Msk = 0x10000 + // Bit SLC1_RX_UDF_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_RX_UDF_INT_CLR = 0x10000 + // Position of SLC1_TX_OVF_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TX_OVF_INT_CLR_Pos = 0x11 + // Bit mask of SLC1_TX_OVF_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TX_OVF_INT_CLR_Msk = 0x20000 + // Bit SLC1_TX_OVF_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_TX_OVF_INT_CLR = 0x20000 + // Position of SLC1_RX_PF_VALID_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_RX_PF_VALID_INT_CLR_Pos = 0x12 + // Bit mask of SLC1_RX_PF_VALID_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_RX_PF_VALID_INT_CLR_Msk = 0x40000 + // Bit SLC1_RX_PF_VALID_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_RX_PF_VALID_INT_CLR = 0x40000 + // Position of SLC1_EXT_BIT0_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT0_INT_CLR_Pos = 0x13 + // Bit mask of SLC1_EXT_BIT0_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT0_INT_CLR_Msk = 0x80000 + // Bit SLC1_EXT_BIT0_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT0_INT_CLR = 0x80000 + // Position of SLC1_EXT_BIT1_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT1_INT_CLR_Pos = 0x14 + // Bit mask of SLC1_EXT_BIT1_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT1_INT_CLR_Msk = 0x100000 + // Bit SLC1_EXT_BIT1_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT1_INT_CLR = 0x100000 + // Position of SLC1_EXT_BIT2_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT2_INT_CLR_Pos = 0x15 + // Bit mask of SLC1_EXT_BIT2_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT2_INT_CLR_Msk = 0x200000 + // Bit SLC1_EXT_BIT2_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT2_INT_CLR = 0x200000 + // Position of SLC1_EXT_BIT3_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT3_INT_CLR_Pos = 0x16 + // Bit mask of SLC1_EXT_BIT3_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT3_INT_CLR_Msk = 0x400000 + // Bit SLC1_EXT_BIT3_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_EXT_BIT3_INT_CLR = 0x400000 + // Position of SLC1_WIFI_RX_NEW_PACKET_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_Pos = 0x17 + // Bit mask of SLC1_WIFI_RX_NEW_PACKET_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_Msk = 0x800000 + // Bit SLC1_WIFI_RX_NEW_PACKET_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_WIFI_RX_NEW_PACKET_INT_CLR = 0x800000 + // Position of SLC1_HOST_RD_RETRY_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_HOST_RD_RETRY_INT_CLR_Pos = 0x18 + // Bit mask of SLC1_HOST_RD_RETRY_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_HOST_RD_RETRY_INT_CLR_Msk = 0x1000000 + // Bit SLC1_HOST_RD_RETRY_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_HOST_RD_RETRY_INT_CLR = 0x1000000 + // Position of SLC1_BT_RX_NEW_PACKET_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_BT_RX_NEW_PACKET_INT_CLR_Pos = 0x19 + // Bit mask of SLC1_BT_RX_NEW_PACKET_INT_CLR field. + SLCHOST_SLC1HOST_INT_CLR_SLC1_BT_RX_NEW_PACKET_INT_CLR_Msk = 0x2000000 + // Bit SLC1_BT_RX_NEW_PACKET_INT_CLR. + SLCHOST_SLC1HOST_INT_CLR_SLC1_BT_RX_NEW_PACKET_INT_CLR = 0x2000000 + + // SLC0HOST_FUNC1_INT_ENA: *******Description*********** + // Position of FN1_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of FN1_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit FN1_SLC0_TOHOST_BIT0_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT0_INT_ENA = 0x1 + // Position of FN1_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of FN1_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit FN1_SLC0_TOHOST_BIT1_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT1_INT_ENA = 0x2 + // Position of FN1_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of FN1_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit FN1_SLC0_TOHOST_BIT2_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT2_INT_ENA = 0x4 + // Position of FN1_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of FN1_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit FN1_SLC0_TOHOST_BIT3_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT3_INT_ENA = 0x8 + // Position of FN1_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of FN1_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit FN1_SLC0_TOHOST_BIT4_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT4_INT_ENA = 0x10 + // Position of FN1_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of FN1_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit FN1_SLC0_TOHOST_BIT5_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT5_INT_ENA = 0x20 + // Position of FN1_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of FN1_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit FN1_SLC0_TOHOST_BIT6_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT6_INT_ENA = 0x40 + // Position of FN1_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of FN1_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit FN1_SLC0_TOHOST_BIT7_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOHOST_BIT7_INT_ENA = 0x80 + // Position of FN1_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of FN1_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit FN1_SLC0_TOKEN0_1TO0_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of FN1_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of FN1_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit FN1_SLC0_TOKEN1_1TO0_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of FN1_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of FN1_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit FN1_SLC0_TOKEN0_0TO1_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of FN1_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of FN1_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit FN1_SLC0_TOKEN1_0TO1_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of FN1_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of FN1_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit FN1_SLC0HOST_RX_SOF_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_SOF_INT_ENA = 0x1000 + // Position of FN1_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of FN1_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit FN1_SLC0HOST_RX_EOF_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_EOF_INT_ENA = 0x2000 + // Position of FN1_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of FN1_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit FN1_SLC0HOST_RX_START_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_RX_START_INT_ENA = 0x4000 + // Position of FN1_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of FN1_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit FN1_SLC0HOST_TX_START_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0HOST_TX_START_INT_ENA = 0x8000 + // Position of FN1_SLC0_RX_UDF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of FN1_SLC0_RX_UDF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit FN1_SLC0_RX_UDF_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_UDF_INT_ENA = 0x10000 + // Position of FN1_SLC0_TX_OVF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of FN1_SLC0_TX_OVF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit FN1_SLC0_TX_OVF_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_TX_OVF_INT_ENA = 0x20000 + // Position of FN1_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of FN1_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit FN1_SLC0_RX_PF_VALID_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_PF_VALID_INT_ENA = 0x40000 + // Position of FN1_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of FN1_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit FN1_SLC0_EXT_BIT0_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT0_INT_ENA = 0x80000 + // Position of FN1_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of FN1_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit FN1_SLC0_EXT_BIT1_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT1_INT_ENA = 0x100000 + // Position of FN1_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of FN1_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit FN1_SLC0_EXT_BIT2_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT2_INT_ENA = 0x200000 + // Position of FN1_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of FN1_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit FN1_SLC0_EXT_BIT3_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_EXT_BIT3_INT_ENA = 0x400000 + // Position of FN1_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of FN1_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit FN1_SLC0_RX_NEW_PACKET_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of FN1_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of FN1_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit FN1_SLC0_HOST_RD_RETRY_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_SLC0_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of FN1_GPIO_SDIO_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_GPIO_SDIO_INT_ENA_Pos = 0x19 + // Bit mask of FN1_GPIO_SDIO_INT_ENA field. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_GPIO_SDIO_INT_ENA_Msk = 0x2000000 + // Bit FN1_GPIO_SDIO_INT_ENA. + SLCHOST_SLC0HOST_FUNC1_INT_ENA_FN1_GPIO_SDIO_INT_ENA = 0x2000000 + + // SLC1HOST_FUNC1_INT_ENA: *******Description*********** + // Position of FN1_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of FN1_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit FN1_SLC1_TOHOST_BIT0_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT0_INT_ENA = 0x1 + // Position of FN1_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of FN1_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit FN1_SLC1_TOHOST_BIT1_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT1_INT_ENA = 0x2 + // Position of FN1_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of FN1_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit FN1_SLC1_TOHOST_BIT2_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT2_INT_ENA = 0x4 + // Position of FN1_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of FN1_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit FN1_SLC1_TOHOST_BIT3_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT3_INT_ENA = 0x8 + // Position of FN1_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of FN1_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit FN1_SLC1_TOHOST_BIT4_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT4_INT_ENA = 0x10 + // Position of FN1_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of FN1_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit FN1_SLC1_TOHOST_BIT5_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT5_INT_ENA = 0x20 + // Position of FN1_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of FN1_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit FN1_SLC1_TOHOST_BIT6_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT6_INT_ENA = 0x40 + // Position of FN1_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of FN1_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit FN1_SLC1_TOHOST_BIT7_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOHOST_BIT7_INT_ENA = 0x80 + // Position of FN1_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of FN1_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit FN1_SLC1_TOKEN0_1TO0_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of FN1_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of FN1_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit FN1_SLC1_TOKEN1_1TO0_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of FN1_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of FN1_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit FN1_SLC1_TOKEN0_0TO1_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of FN1_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of FN1_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit FN1_SLC1_TOKEN1_0TO1_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of FN1_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of FN1_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit FN1_SLC1HOST_RX_SOF_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_SOF_INT_ENA = 0x1000 + // Position of FN1_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of FN1_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit FN1_SLC1HOST_RX_EOF_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_EOF_INT_ENA = 0x2000 + // Position of FN1_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of FN1_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit FN1_SLC1HOST_RX_START_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_RX_START_INT_ENA = 0x4000 + // Position of FN1_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of FN1_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit FN1_SLC1HOST_TX_START_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1HOST_TX_START_INT_ENA = 0x8000 + // Position of FN1_SLC1_RX_UDF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of FN1_SLC1_RX_UDF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit FN1_SLC1_RX_UDF_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_UDF_INT_ENA = 0x10000 + // Position of FN1_SLC1_TX_OVF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of FN1_SLC1_TX_OVF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit FN1_SLC1_TX_OVF_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_TX_OVF_INT_ENA = 0x20000 + // Position of FN1_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of FN1_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit FN1_SLC1_RX_PF_VALID_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_RX_PF_VALID_INT_ENA = 0x40000 + // Position of FN1_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of FN1_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit FN1_SLC1_EXT_BIT0_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT0_INT_ENA = 0x80000 + // Position of FN1_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of FN1_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit FN1_SLC1_EXT_BIT1_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT1_INT_ENA = 0x100000 + // Position of FN1_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of FN1_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit FN1_SLC1_EXT_BIT2_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT2_INT_ENA = 0x200000 + // Position of FN1_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of FN1_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit FN1_SLC1_EXT_BIT3_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_EXT_BIT3_INT_ENA = 0x400000 + // Position of FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of FN1_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of FN1_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit FN1_SLC1_HOST_RD_RETRY_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_Pos = 0x19 + // Bit mask of FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_Msk = 0x2000000 + // Bit FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA. + SLCHOST_SLC1HOST_FUNC1_INT_ENA_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA = 0x2000000 + + // SLC0HOST_FUNC2_INT_ENA: *******Description*********** + // Position of FN2_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of FN2_SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit FN2_SLC0_TOHOST_BIT0_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT0_INT_ENA = 0x1 + // Position of FN2_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of FN2_SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit FN2_SLC0_TOHOST_BIT1_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT1_INT_ENA = 0x2 + // Position of FN2_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of FN2_SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit FN2_SLC0_TOHOST_BIT2_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT2_INT_ENA = 0x4 + // Position of FN2_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of FN2_SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit FN2_SLC0_TOHOST_BIT3_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT3_INT_ENA = 0x8 + // Position of FN2_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of FN2_SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit FN2_SLC0_TOHOST_BIT4_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT4_INT_ENA = 0x10 + // Position of FN2_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of FN2_SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit FN2_SLC0_TOHOST_BIT5_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT5_INT_ENA = 0x20 + // Position of FN2_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of FN2_SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit FN2_SLC0_TOHOST_BIT6_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT6_INT_ENA = 0x40 + // Position of FN2_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of FN2_SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit FN2_SLC0_TOHOST_BIT7_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOHOST_BIT7_INT_ENA = 0x80 + // Position of FN2_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of FN2_SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit FN2_SLC0_TOKEN0_1TO0_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of FN2_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of FN2_SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit FN2_SLC0_TOKEN1_1TO0_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of FN2_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of FN2_SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit FN2_SLC0_TOKEN0_0TO1_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of FN2_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of FN2_SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit FN2_SLC0_TOKEN1_0TO1_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of FN2_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of FN2_SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit FN2_SLC0HOST_RX_SOF_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_SOF_INT_ENA = 0x1000 + // Position of FN2_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of FN2_SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit FN2_SLC0HOST_RX_EOF_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_EOF_INT_ENA = 0x2000 + // Position of FN2_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of FN2_SLC0HOST_RX_START_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit FN2_SLC0HOST_RX_START_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_RX_START_INT_ENA = 0x4000 + // Position of FN2_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of FN2_SLC0HOST_TX_START_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit FN2_SLC0HOST_TX_START_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0HOST_TX_START_INT_ENA = 0x8000 + // Position of FN2_SLC0_RX_UDF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of FN2_SLC0_RX_UDF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit FN2_SLC0_RX_UDF_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_UDF_INT_ENA = 0x10000 + // Position of FN2_SLC0_TX_OVF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of FN2_SLC0_TX_OVF_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit FN2_SLC0_TX_OVF_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_TX_OVF_INT_ENA = 0x20000 + // Position of FN2_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of FN2_SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit FN2_SLC0_RX_PF_VALID_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_PF_VALID_INT_ENA = 0x40000 + // Position of FN2_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of FN2_SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit FN2_SLC0_EXT_BIT0_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT0_INT_ENA = 0x80000 + // Position of FN2_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of FN2_SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit FN2_SLC0_EXT_BIT1_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT1_INT_ENA = 0x100000 + // Position of FN2_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of FN2_SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit FN2_SLC0_EXT_BIT2_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT2_INT_ENA = 0x200000 + // Position of FN2_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of FN2_SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit FN2_SLC0_EXT_BIT3_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_EXT_BIT3_INT_ENA = 0x400000 + // Position of FN2_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of FN2_SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit FN2_SLC0_RX_NEW_PACKET_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of FN2_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of FN2_SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit FN2_SLC0_HOST_RD_RETRY_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_SLC0_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of FN2_GPIO_SDIO_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_GPIO_SDIO_INT_ENA_Pos = 0x19 + // Bit mask of FN2_GPIO_SDIO_INT_ENA field. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_GPIO_SDIO_INT_ENA_Msk = 0x2000000 + // Bit FN2_GPIO_SDIO_INT_ENA. + SLCHOST_SLC0HOST_FUNC2_INT_ENA_FN2_GPIO_SDIO_INT_ENA = 0x2000000 + + // SLC1HOST_FUNC2_INT_ENA: *******Description*********** + // Position of FN2_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of FN2_SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit FN2_SLC1_TOHOST_BIT0_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT0_INT_ENA = 0x1 + // Position of FN2_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of FN2_SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit FN2_SLC1_TOHOST_BIT1_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT1_INT_ENA = 0x2 + // Position of FN2_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of FN2_SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit FN2_SLC1_TOHOST_BIT2_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT2_INT_ENA = 0x4 + // Position of FN2_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of FN2_SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit FN2_SLC1_TOHOST_BIT3_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT3_INT_ENA = 0x8 + // Position of FN2_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of FN2_SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit FN2_SLC1_TOHOST_BIT4_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT4_INT_ENA = 0x10 + // Position of FN2_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of FN2_SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit FN2_SLC1_TOHOST_BIT5_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT5_INT_ENA = 0x20 + // Position of FN2_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of FN2_SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit FN2_SLC1_TOHOST_BIT6_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT6_INT_ENA = 0x40 + // Position of FN2_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of FN2_SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit FN2_SLC1_TOHOST_BIT7_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOHOST_BIT7_INT_ENA = 0x80 + // Position of FN2_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of FN2_SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit FN2_SLC1_TOKEN0_1TO0_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of FN2_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of FN2_SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit FN2_SLC1_TOKEN1_1TO0_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of FN2_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of FN2_SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit FN2_SLC1_TOKEN0_0TO1_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of FN2_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of FN2_SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit FN2_SLC1_TOKEN1_0TO1_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of FN2_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of FN2_SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit FN2_SLC1HOST_RX_SOF_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_SOF_INT_ENA = 0x1000 + // Position of FN2_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of FN2_SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit FN2_SLC1HOST_RX_EOF_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_EOF_INT_ENA = 0x2000 + // Position of FN2_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of FN2_SLC1HOST_RX_START_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit FN2_SLC1HOST_RX_START_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_RX_START_INT_ENA = 0x4000 + // Position of FN2_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of FN2_SLC1HOST_TX_START_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit FN2_SLC1HOST_TX_START_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1HOST_TX_START_INT_ENA = 0x8000 + // Position of FN2_SLC1_RX_UDF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of FN2_SLC1_RX_UDF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit FN2_SLC1_RX_UDF_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_UDF_INT_ENA = 0x10000 + // Position of FN2_SLC1_TX_OVF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of FN2_SLC1_TX_OVF_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit FN2_SLC1_TX_OVF_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_TX_OVF_INT_ENA = 0x20000 + // Position of FN2_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of FN2_SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit FN2_SLC1_RX_PF_VALID_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_RX_PF_VALID_INT_ENA = 0x40000 + // Position of FN2_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of FN2_SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit FN2_SLC1_EXT_BIT0_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT0_INT_ENA = 0x80000 + // Position of FN2_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of FN2_SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit FN2_SLC1_EXT_BIT1_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT1_INT_ENA = 0x100000 + // Position of FN2_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of FN2_SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit FN2_SLC1_EXT_BIT2_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT2_INT_ENA = 0x200000 + // Position of FN2_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of FN2_SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit FN2_SLC1_EXT_BIT3_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_EXT_BIT3_INT_ENA = 0x400000 + // Position of FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of FN2_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of FN2_SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit FN2_SLC1_HOST_RD_RETRY_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_Pos = 0x19 + // Bit mask of FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_Msk = 0x2000000 + // Bit FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA. + SLCHOST_SLC1HOST_FUNC2_INT_ENA_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA = 0x2000000 + + // SLC0HOST_INT_ENA: *******Description*********** + // Position of SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of SLC0_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit SLC0_TOHOST_BIT0_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT0_INT_ENA = 0x1 + // Position of SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of SLC0_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit SLC0_TOHOST_BIT1_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT1_INT_ENA = 0x2 + // Position of SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of SLC0_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit SLC0_TOHOST_BIT2_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT2_INT_ENA = 0x4 + // Position of SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of SLC0_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit SLC0_TOHOST_BIT3_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT3_INT_ENA = 0x8 + // Position of SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of SLC0_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit SLC0_TOHOST_BIT4_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT4_INT_ENA = 0x10 + // Position of SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of SLC0_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit SLC0_TOHOST_BIT5_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT5_INT_ENA = 0x20 + // Position of SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of SLC0_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit SLC0_TOHOST_BIT6_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT6_INT_ENA = 0x40 + // Position of SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of SLC0_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit SLC0_TOHOST_BIT7_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOHOST_BIT7_INT_ENA = 0x80 + // Position of SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of SLC0_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit SLC0_TOKEN0_1TO0_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of SLC0_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit SLC0_TOKEN1_1TO0_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of SLC0_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit SLC0_TOKEN0_0TO1_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of SLC0_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit SLC0_TOKEN1_0TO1_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of SLC0HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit SLC0HOST_RX_SOF_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_RX_SOF_INT_ENA = 0x1000 + // Position of SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of SLC0HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit SLC0HOST_RX_EOF_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_RX_EOF_INT_ENA = 0x2000 + // Position of SLC0HOST_RX_START_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of SLC0HOST_RX_START_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit SLC0HOST_RX_START_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_RX_START_INT_ENA = 0x4000 + // Position of SLC0HOST_TX_START_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of SLC0HOST_TX_START_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit SLC0HOST_TX_START_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0HOST_TX_START_INT_ENA = 0x8000 + // Position of SLC0_RX_UDF_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of SLC0_RX_UDF_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit SLC0_RX_UDF_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_RX_UDF_INT_ENA = 0x10000 + // Position of SLC0_TX_OVF_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of SLC0_TX_OVF_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit SLC0_TX_OVF_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_TX_OVF_INT_ENA = 0x20000 + // Position of SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of SLC0_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit SLC0_RX_PF_VALID_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_RX_PF_VALID_INT_ENA = 0x40000 + // Position of SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of SLC0_EXT_BIT0_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit SLC0_EXT_BIT0_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT0_INT_ENA = 0x80000 + // Position of SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of SLC0_EXT_BIT1_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit SLC0_EXT_BIT1_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT1_INT_ENA = 0x100000 + // Position of SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of SLC0_EXT_BIT2_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit SLC0_EXT_BIT2_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT2_INT_ENA = 0x200000 + // Position of SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of SLC0_EXT_BIT3_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit SLC0_EXT_BIT3_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_EXT_BIT3_INT_ENA = 0x400000 + // Position of SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of SLC0_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit SLC0_RX_NEW_PACKET_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of SLC0_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_SLC0_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit SLC0_HOST_RD_RETRY_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_SLC0_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of GPIO_SDIO_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_GPIO_SDIO_INT_ENA_Pos = 0x19 + // Bit mask of GPIO_SDIO_INT_ENA field. + SLCHOST_SLC0HOST_INT_ENA_GPIO_SDIO_INT_ENA_Msk = 0x2000000 + // Bit GPIO_SDIO_INT_ENA. + SLCHOST_SLC0HOST_INT_ENA_GPIO_SDIO_INT_ENA = 0x2000000 + + // SLC1HOST_INT_ENA: *******Description*********** + // Position of SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of SLC1_TOHOST_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit SLC1_TOHOST_BIT0_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT0_INT_ENA = 0x1 + // Position of SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of SLC1_TOHOST_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit SLC1_TOHOST_BIT1_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT1_INT_ENA = 0x2 + // Position of SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of SLC1_TOHOST_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit SLC1_TOHOST_BIT2_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT2_INT_ENA = 0x4 + // Position of SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of SLC1_TOHOST_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit SLC1_TOHOST_BIT3_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT3_INT_ENA = 0x8 + // Position of SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of SLC1_TOHOST_BIT4_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit SLC1_TOHOST_BIT4_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT4_INT_ENA = 0x10 + // Position of SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of SLC1_TOHOST_BIT5_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit SLC1_TOHOST_BIT5_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT5_INT_ENA = 0x20 + // Position of SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of SLC1_TOHOST_BIT6_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit SLC1_TOHOST_BIT6_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT6_INT_ENA = 0x40 + // Position of SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of SLC1_TOHOST_BIT7_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit SLC1_TOHOST_BIT7_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOHOST_BIT7_INT_ENA = 0x80 + // Position of SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA_Pos = 0x8 + // Bit mask of SLC1_TOKEN0_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA_Msk = 0x100 + // Bit SLC1_TOKEN0_1TO0_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN0_1TO0_INT_ENA = 0x100 + // Position of SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA_Pos = 0x9 + // Bit mask of SLC1_TOKEN1_1TO0_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA_Msk = 0x200 + // Bit SLC1_TOKEN1_1TO0_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN1_1TO0_INT_ENA = 0x200 + // Position of SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN0_0TO1_INT_ENA_Pos = 0xa + // Bit mask of SLC1_TOKEN0_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN0_0TO1_INT_ENA_Msk = 0x400 + // Bit SLC1_TOKEN0_0TO1_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN0_0TO1_INT_ENA = 0x400 + // Position of SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN1_0TO1_INT_ENA_Pos = 0xb + // Bit mask of SLC1_TOKEN1_0TO1_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN1_0TO1_INT_ENA_Msk = 0x800 + // Bit SLC1_TOKEN1_0TO1_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TOKEN1_0TO1_INT_ENA = 0x800 + // Position of SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_RX_SOF_INT_ENA_Pos = 0xc + // Bit mask of SLC1HOST_RX_SOF_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_RX_SOF_INT_ENA_Msk = 0x1000 + // Bit SLC1HOST_RX_SOF_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_RX_SOF_INT_ENA = 0x1000 + // Position of SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_RX_EOF_INT_ENA_Pos = 0xd + // Bit mask of SLC1HOST_RX_EOF_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_RX_EOF_INT_ENA_Msk = 0x2000 + // Bit SLC1HOST_RX_EOF_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_RX_EOF_INT_ENA = 0x2000 + // Position of SLC1HOST_RX_START_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_RX_START_INT_ENA_Pos = 0xe + // Bit mask of SLC1HOST_RX_START_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_RX_START_INT_ENA_Msk = 0x4000 + // Bit SLC1HOST_RX_START_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_RX_START_INT_ENA = 0x4000 + // Position of SLC1HOST_TX_START_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_TX_START_INT_ENA_Pos = 0xf + // Bit mask of SLC1HOST_TX_START_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_TX_START_INT_ENA_Msk = 0x8000 + // Bit SLC1HOST_TX_START_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1HOST_TX_START_INT_ENA = 0x8000 + // Position of SLC1_RX_UDF_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_RX_UDF_INT_ENA_Pos = 0x10 + // Bit mask of SLC1_RX_UDF_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_RX_UDF_INT_ENA_Msk = 0x10000 + // Bit SLC1_RX_UDF_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_RX_UDF_INT_ENA = 0x10000 + // Position of SLC1_TX_OVF_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TX_OVF_INT_ENA_Pos = 0x11 + // Bit mask of SLC1_TX_OVF_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TX_OVF_INT_ENA_Msk = 0x20000 + // Bit SLC1_TX_OVF_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_TX_OVF_INT_ENA = 0x20000 + // Position of SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_RX_PF_VALID_INT_ENA_Pos = 0x12 + // Bit mask of SLC1_RX_PF_VALID_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_RX_PF_VALID_INT_ENA_Msk = 0x40000 + // Bit SLC1_RX_PF_VALID_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_RX_PF_VALID_INT_ENA = 0x40000 + // Position of SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT0_INT_ENA_Pos = 0x13 + // Bit mask of SLC1_EXT_BIT0_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT0_INT_ENA_Msk = 0x80000 + // Bit SLC1_EXT_BIT0_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT0_INT_ENA = 0x80000 + // Position of SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT1_INT_ENA_Pos = 0x14 + // Bit mask of SLC1_EXT_BIT1_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT1_INT_ENA_Msk = 0x100000 + // Bit SLC1_EXT_BIT1_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT1_INT_ENA = 0x100000 + // Position of SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT2_INT_ENA_Pos = 0x15 + // Bit mask of SLC1_EXT_BIT2_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT2_INT_ENA_Msk = 0x200000 + // Bit SLC1_EXT_BIT2_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT2_INT_ENA = 0x200000 + // Position of SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT3_INT_ENA_Pos = 0x16 + // Bit mask of SLC1_EXT_BIT3_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT3_INT_ENA_Msk = 0x400000 + // Bit SLC1_EXT_BIT3_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_EXT_BIT3_INT_ENA = 0x400000 + // Position of SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Pos = 0x17 + // Bit mask of SLC1_WIFI_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_Msk = 0x800000 + // Bit SLC1_WIFI_RX_NEW_PACKET_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_WIFI_RX_NEW_PACKET_INT_ENA = 0x800000 + // Position of SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_HOST_RD_RETRY_INT_ENA_Pos = 0x18 + // Bit mask of SLC1_HOST_RD_RETRY_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_HOST_RD_RETRY_INT_ENA_Msk = 0x1000000 + // Bit SLC1_HOST_RD_RETRY_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_HOST_RD_RETRY_INT_ENA = 0x1000000 + // Position of SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_BT_RX_NEW_PACKET_INT_ENA_Pos = 0x19 + // Bit mask of SLC1_BT_RX_NEW_PACKET_INT_ENA field. + SLCHOST_SLC1HOST_INT_ENA_SLC1_BT_RX_NEW_PACKET_INT_ENA_Msk = 0x2000000 + // Bit SLC1_BT_RX_NEW_PACKET_INT_ENA. + SLCHOST_SLC1HOST_INT_ENA_SLC1_BT_RX_NEW_PACKET_INT_ENA = 0x2000000 + + // SLC0HOST_RX_INFOR: *******Description*********** + // Position of SLC0HOST_RX_INFOR field. + SLCHOST_SLC0HOST_RX_INFOR_SLC0HOST_RX_INFOR_Pos = 0x0 + // Bit mask of SLC0HOST_RX_INFOR field. + SLCHOST_SLC0HOST_RX_INFOR_SLC0HOST_RX_INFOR_Msk = 0xfffff + + // SLC1HOST_RX_INFOR: *******Description*********** + // Position of SLC1HOST_RX_INFOR field. + SLCHOST_SLC1HOST_RX_INFOR_SLC1HOST_RX_INFOR_Pos = 0x0 + // Bit mask of SLC1HOST_RX_INFOR field. + SLCHOST_SLC1HOST_RX_INFOR_SLC1HOST_RX_INFOR_Msk = 0xfffff + + // SLC0HOST_LEN_WD: *******Description*********** + // Position of SLC0HOST_LEN_WD field. + SLCHOST_SLC0HOST_LEN_WD_SLC0HOST_LEN_WD_Pos = 0x0 + // Bit mask of SLC0HOST_LEN_WD field. + SLCHOST_SLC0HOST_LEN_WD_SLC0HOST_LEN_WD_Msk = 0xffffffff + + // SLC_APBWIN_WDATA: *******Description*********** + // Position of SLC_APBWIN_WDATA field. + SLCHOST_SLC_APBWIN_WDATA_SLC_APBWIN_WDATA_Pos = 0x0 + // Bit mask of SLC_APBWIN_WDATA field. + SLCHOST_SLC_APBWIN_WDATA_SLC_APBWIN_WDATA_Msk = 0xffffffff + + // SLC_APBWIN_CONF: *******Description*********** + // Position of SLC_APBWIN_ADDR field. + SLCHOST_SLC_APBWIN_CONF_SLC_APBWIN_ADDR_Pos = 0x0 + // Bit mask of SLC_APBWIN_ADDR field. + SLCHOST_SLC_APBWIN_CONF_SLC_APBWIN_ADDR_Msk = 0xfffffff + // Position of SLC_APBWIN_WR field. + SLCHOST_SLC_APBWIN_CONF_SLC_APBWIN_WR_Pos = 0x1c + // Bit mask of SLC_APBWIN_WR field. + SLCHOST_SLC_APBWIN_CONF_SLC_APBWIN_WR_Msk = 0x10000000 + // Bit SLC_APBWIN_WR. + SLCHOST_SLC_APBWIN_CONF_SLC_APBWIN_WR = 0x10000000 + // Position of SLC_APBWIN_START field. + SLCHOST_SLC_APBWIN_CONF_SLC_APBWIN_START_Pos = 0x1d + // Bit mask of SLC_APBWIN_START field. + SLCHOST_SLC_APBWIN_CONF_SLC_APBWIN_START_Msk = 0x20000000 + // Bit SLC_APBWIN_START. + SLCHOST_SLC_APBWIN_CONF_SLC_APBWIN_START = 0x20000000 + + // SLC_APBWIN_RDATA: *******Description*********** + // Position of SLC_APBWIN_RDATA field. + SLCHOST_SLC_APBWIN_RDATA_SLC_APBWIN_RDATA_Pos = 0x0 + // Bit mask of SLC_APBWIN_RDATA field. + SLCHOST_SLC_APBWIN_RDATA_SLC_APBWIN_RDATA_Msk = 0xffffffff + + // RDCLR0: *******Description*********** + // Position of SLCHOST_SLC0_BIT7_CLRADDR field. + SLCHOST_RDCLR0_SLCHOST_SLC0_BIT7_CLRADDR_Pos = 0x0 + // Bit mask of SLCHOST_SLC0_BIT7_CLRADDR field. + SLCHOST_RDCLR0_SLCHOST_SLC0_BIT7_CLRADDR_Msk = 0x1ff + // Position of SLCHOST_SLC0_BIT6_CLRADDR field. + SLCHOST_RDCLR0_SLCHOST_SLC0_BIT6_CLRADDR_Pos = 0x9 + // Bit mask of SLCHOST_SLC0_BIT6_CLRADDR field. + SLCHOST_RDCLR0_SLCHOST_SLC0_BIT6_CLRADDR_Msk = 0x3fe00 + + // RDCLR1: *******Description*********** + // Position of SLCHOST_SLC1_BIT7_CLRADDR field. + SLCHOST_RDCLR1_SLCHOST_SLC1_BIT7_CLRADDR_Pos = 0x0 + // Bit mask of SLCHOST_SLC1_BIT7_CLRADDR field. + SLCHOST_RDCLR1_SLCHOST_SLC1_BIT7_CLRADDR_Msk = 0x1ff + // Position of SLCHOST_SLC1_BIT6_CLRADDR field. + SLCHOST_RDCLR1_SLCHOST_SLC1_BIT6_CLRADDR_Pos = 0x9 + // Bit mask of SLCHOST_SLC1_BIT6_CLRADDR field. + SLCHOST_RDCLR1_SLCHOST_SLC1_BIT6_CLRADDR_Msk = 0x3fe00 + + // SLC0HOST_INT_ENA1: *******Description*********** + // Position of SLC0_TOHOST_BIT0_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT0_INT_ENA1_Pos = 0x0 + // Bit mask of SLC0_TOHOST_BIT0_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT0_INT_ENA1_Msk = 0x1 + // Bit SLC0_TOHOST_BIT0_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT0_INT_ENA1 = 0x1 + // Position of SLC0_TOHOST_BIT1_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT1_INT_ENA1_Pos = 0x1 + // Bit mask of SLC0_TOHOST_BIT1_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT1_INT_ENA1_Msk = 0x2 + // Bit SLC0_TOHOST_BIT1_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT1_INT_ENA1 = 0x2 + // Position of SLC0_TOHOST_BIT2_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT2_INT_ENA1_Pos = 0x2 + // Bit mask of SLC0_TOHOST_BIT2_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT2_INT_ENA1_Msk = 0x4 + // Bit SLC0_TOHOST_BIT2_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT2_INT_ENA1 = 0x4 + // Position of SLC0_TOHOST_BIT3_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT3_INT_ENA1_Pos = 0x3 + // Bit mask of SLC0_TOHOST_BIT3_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT3_INT_ENA1_Msk = 0x8 + // Bit SLC0_TOHOST_BIT3_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT3_INT_ENA1 = 0x8 + // Position of SLC0_TOHOST_BIT4_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT4_INT_ENA1_Pos = 0x4 + // Bit mask of SLC0_TOHOST_BIT4_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT4_INT_ENA1_Msk = 0x10 + // Bit SLC0_TOHOST_BIT4_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT4_INT_ENA1 = 0x10 + // Position of SLC0_TOHOST_BIT5_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT5_INT_ENA1_Pos = 0x5 + // Bit mask of SLC0_TOHOST_BIT5_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT5_INT_ENA1_Msk = 0x20 + // Bit SLC0_TOHOST_BIT5_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT5_INT_ENA1 = 0x20 + // Position of SLC0_TOHOST_BIT6_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT6_INT_ENA1_Pos = 0x6 + // Bit mask of SLC0_TOHOST_BIT6_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT6_INT_ENA1_Msk = 0x40 + // Bit SLC0_TOHOST_BIT6_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT6_INT_ENA1 = 0x40 + // Position of SLC0_TOHOST_BIT7_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT7_INT_ENA1_Pos = 0x7 + // Bit mask of SLC0_TOHOST_BIT7_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT7_INT_ENA1_Msk = 0x80 + // Bit SLC0_TOHOST_BIT7_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOHOST_BIT7_INT_ENA1 = 0x80 + // Position of SLC0_TOKEN0_1TO0_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1_Pos = 0x8 + // Bit mask of SLC0_TOKEN0_1TO0_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1_Msk = 0x100 + // Bit SLC0_TOKEN0_1TO0_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN0_1TO0_INT_ENA1 = 0x100 + // Position of SLC0_TOKEN1_1TO0_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1_Pos = 0x9 + // Bit mask of SLC0_TOKEN1_1TO0_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1_Msk = 0x200 + // Bit SLC0_TOKEN1_1TO0_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN1_1TO0_INT_ENA1 = 0x200 + // Position of SLC0_TOKEN0_0TO1_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN0_0TO1_INT_ENA1_Pos = 0xa + // Bit mask of SLC0_TOKEN0_0TO1_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN0_0TO1_INT_ENA1_Msk = 0x400 + // Bit SLC0_TOKEN0_0TO1_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN0_0TO1_INT_ENA1 = 0x400 + // Position of SLC0_TOKEN1_0TO1_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN1_0TO1_INT_ENA1_Pos = 0xb + // Bit mask of SLC0_TOKEN1_0TO1_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN1_0TO1_INT_ENA1_Msk = 0x800 + // Bit SLC0_TOKEN1_0TO1_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TOKEN1_0TO1_INT_ENA1 = 0x800 + // Position of SLC0HOST_RX_SOF_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_RX_SOF_INT_ENA1_Pos = 0xc + // Bit mask of SLC0HOST_RX_SOF_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_RX_SOF_INT_ENA1_Msk = 0x1000 + // Bit SLC0HOST_RX_SOF_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_RX_SOF_INT_ENA1 = 0x1000 + // Position of SLC0HOST_RX_EOF_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_RX_EOF_INT_ENA1_Pos = 0xd + // Bit mask of SLC0HOST_RX_EOF_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_RX_EOF_INT_ENA1_Msk = 0x2000 + // Bit SLC0HOST_RX_EOF_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_RX_EOF_INT_ENA1 = 0x2000 + // Position of SLC0HOST_RX_START_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_RX_START_INT_ENA1_Pos = 0xe + // Bit mask of SLC0HOST_RX_START_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_RX_START_INT_ENA1_Msk = 0x4000 + // Bit SLC0HOST_RX_START_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_RX_START_INT_ENA1 = 0x4000 + // Position of SLC0HOST_TX_START_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_TX_START_INT_ENA1_Pos = 0xf + // Bit mask of SLC0HOST_TX_START_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_TX_START_INT_ENA1_Msk = 0x8000 + // Bit SLC0HOST_TX_START_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0HOST_TX_START_INT_ENA1 = 0x8000 + // Position of SLC0_RX_UDF_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_RX_UDF_INT_ENA1_Pos = 0x10 + // Bit mask of SLC0_RX_UDF_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_RX_UDF_INT_ENA1_Msk = 0x10000 + // Bit SLC0_RX_UDF_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_RX_UDF_INT_ENA1 = 0x10000 + // Position of SLC0_TX_OVF_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TX_OVF_INT_ENA1_Pos = 0x11 + // Bit mask of SLC0_TX_OVF_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TX_OVF_INT_ENA1_Msk = 0x20000 + // Bit SLC0_TX_OVF_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_TX_OVF_INT_ENA1 = 0x20000 + // Position of SLC0_RX_PF_VALID_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_RX_PF_VALID_INT_ENA1_Pos = 0x12 + // Bit mask of SLC0_RX_PF_VALID_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_RX_PF_VALID_INT_ENA1_Msk = 0x40000 + // Bit SLC0_RX_PF_VALID_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_RX_PF_VALID_INT_ENA1 = 0x40000 + // Position of SLC0_EXT_BIT0_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT0_INT_ENA1_Pos = 0x13 + // Bit mask of SLC0_EXT_BIT0_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT0_INT_ENA1_Msk = 0x80000 + // Bit SLC0_EXT_BIT0_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT0_INT_ENA1 = 0x80000 + // Position of SLC0_EXT_BIT1_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT1_INT_ENA1_Pos = 0x14 + // Bit mask of SLC0_EXT_BIT1_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT1_INT_ENA1_Msk = 0x100000 + // Bit SLC0_EXT_BIT1_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT1_INT_ENA1 = 0x100000 + // Position of SLC0_EXT_BIT2_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT2_INT_ENA1_Pos = 0x15 + // Bit mask of SLC0_EXT_BIT2_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT2_INT_ENA1_Msk = 0x200000 + // Bit SLC0_EXT_BIT2_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT2_INT_ENA1 = 0x200000 + // Position of SLC0_EXT_BIT3_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT3_INT_ENA1_Pos = 0x16 + // Bit mask of SLC0_EXT_BIT3_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT3_INT_ENA1_Msk = 0x400000 + // Bit SLC0_EXT_BIT3_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_EXT_BIT3_INT_ENA1 = 0x400000 + // Position of SLC0_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_RX_NEW_PACKET_INT_ENA1_Pos = 0x17 + // Bit mask of SLC0_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_RX_NEW_PACKET_INT_ENA1_Msk = 0x800000 + // Bit SLC0_RX_NEW_PACKET_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_RX_NEW_PACKET_INT_ENA1 = 0x800000 + // Position of SLC0_HOST_RD_RETRY_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_HOST_RD_RETRY_INT_ENA1_Pos = 0x18 + // Bit mask of SLC0_HOST_RD_RETRY_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_HOST_RD_RETRY_INT_ENA1_Msk = 0x1000000 + // Bit SLC0_HOST_RD_RETRY_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_SLC0_HOST_RD_RETRY_INT_ENA1 = 0x1000000 + // Position of GPIO_SDIO_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_GPIO_SDIO_INT_ENA1_Pos = 0x19 + // Bit mask of GPIO_SDIO_INT_ENA1 field. + SLCHOST_SLC0HOST_INT_ENA1_GPIO_SDIO_INT_ENA1_Msk = 0x2000000 + // Bit GPIO_SDIO_INT_ENA1. + SLCHOST_SLC0HOST_INT_ENA1_GPIO_SDIO_INT_ENA1 = 0x2000000 + + // SLC1HOST_INT_ENA1: *******Description*********** + // Position of SLC1_TOHOST_BIT0_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT0_INT_ENA1_Pos = 0x0 + // Bit mask of SLC1_TOHOST_BIT0_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT0_INT_ENA1_Msk = 0x1 + // Bit SLC1_TOHOST_BIT0_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT0_INT_ENA1 = 0x1 + // Position of SLC1_TOHOST_BIT1_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT1_INT_ENA1_Pos = 0x1 + // Bit mask of SLC1_TOHOST_BIT1_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT1_INT_ENA1_Msk = 0x2 + // Bit SLC1_TOHOST_BIT1_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT1_INT_ENA1 = 0x2 + // Position of SLC1_TOHOST_BIT2_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT2_INT_ENA1_Pos = 0x2 + // Bit mask of SLC1_TOHOST_BIT2_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT2_INT_ENA1_Msk = 0x4 + // Bit SLC1_TOHOST_BIT2_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT2_INT_ENA1 = 0x4 + // Position of SLC1_TOHOST_BIT3_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT3_INT_ENA1_Pos = 0x3 + // Bit mask of SLC1_TOHOST_BIT3_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT3_INT_ENA1_Msk = 0x8 + // Bit SLC1_TOHOST_BIT3_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT3_INT_ENA1 = 0x8 + // Position of SLC1_TOHOST_BIT4_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT4_INT_ENA1_Pos = 0x4 + // Bit mask of SLC1_TOHOST_BIT4_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT4_INT_ENA1_Msk = 0x10 + // Bit SLC1_TOHOST_BIT4_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT4_INT_ENA1 = 0x10 + // Position of SLC1_TOHOST_BIT5_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT5_INT_ENA1_Pos = 0x5 + // Bit mask of SLC1_TOHOST_BIT5_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT5_INT_ENA1_Msk = 0x20 + // Bit SLC1_TOHOST_BIT5_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT5_INT_ENA1 = 0x20 + // Position of SLC1_TOHOST_BIT6_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT6_INT_ENA1_Pos = 0x6 + // Bit mask of SLC1_TOHOST_BIT6_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT6_INT_ENA1_Msk = 0x40 + // Bit SLC1_TOHOST_BIT6_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT6_INT_ENA1 = 0x40 + // Position of SLC1_TOHOST_BIT7_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT7_INT_ENA1_Pos = 0x7 + // Bit mask of SLC1_TOHOST_BIT7_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT7_INT_ENA1_Msk = 0x80 + // Bit SLC1_TOHOST_BIT7_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOHOST_BIT7_INT_ENA1 = 0x80 + // Position of SLC1_TOKEN0_1TO0_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1_Pos = 0x8 + // Bit mask of SLC1_TOKEN0_1TO0_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1_Msk = 0x100 + // Bit SLC1_TOKEN0_1TO0_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN0_1TO0_INT_ENA1 = 0x100 + // Position of SLC1_TOKEN1_1TO0_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1_Pos = 0x9 + // Bit mask of SLC1_TOKEN1_1TO0_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1_Msk = 0x200 + // Bit SLC1_TOKEN1_1TO0_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN1_1TO0_INT_ENA1 = 0x200 + // Position of SLC1_TOKEN0_0TO1_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN0_0TO1_INT_ENA1_Pos = 0xa + // Bit mask of SLC1_TOKEN0_0TO1_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN0_0TO1_INT_ENA1_Msk = 0x400 + // Bit SLC1_TOKEN0_0TO1_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN0_0TO1_INT_ENA1 = 0x400 + // Position of SLC1_TOKEN1_0TO1_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN1_0TO1_INT_ENA1_Pos = 0xb + // Bit mask of SLC1_TOKEN1_0TO1_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN1_0TO1_INT_ENA1_Msk = 0x800 + // Bit SLC1_TOKEN1_0TO1_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TOKEN1_0TO1_INT_ENA1 = 0x800 + // Position of SLC1HOST_RX_SOF_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_RX_SOF_INT_ENA1_Pos = 0xc + // Bit mask of SLC1HOST_RX_SOF_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_RX_SOF_INT_ENA1_Msk = 0x1000 + // Bit SLC1HOST_RX_SOF_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_RX_SOF_INT_ENA1 = 0x1000 + // Position of SLC1HOST_RX_EOF_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_RX_EOF_INT_ENA1_Pos = 0xd + // Bit mask of SLC1HOST_RX_EOF_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_RX_EOF_INT_ENA1_Msk = 0x2000 + // Bit SLC1HOST_RX_EOF_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_RX_EOF_INT_ENA1 = 0x2000 + // Position of SLC1HOST_RX_START_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_RX_START_INT_ENA1_Pos = 0xe + // Bit mask of SLC1HOST_RX_START_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_RX_START_INT_ENA1_Msk = 0x4000 + // Bit SLC1HOST_RX_START_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_RX_START_INT_ENA1 = 0x4000 + // Position of SLC1HOST_TX_START_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_TX_START_INT_ENA1_Pos = 0xf + // Bit mask of SLC1HOST_TX_START_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_TX_START_INT_ENA1_Msk = 0x8000 + // Bit SLC1HOST_TX_START_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1HOST_TX_START_INT_ENA1 = 0x8000 + // Position of SLC1_RX_UDF_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_RX_UDF_INT_ENA1_Pos = 0x10 + // Bit mask of SLC1_RX_UDF_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_RX_UDF_INT_ENA1_Msk = 0x10000 + // Bit SLC1_RX_UDF_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_RX_UDF_INT_ENA1 = 0x10000 + // Position of SLC1_TX_OVF_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TX_OVF_INT_ENA1_Pos = 0x11 + // Bit mask of SLC1_TX_OVF_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TX_OVF_INT_ENA1_Msk = 0x20000 + // Bit SLC1_TX_OVF_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_TX_OVF_INT_ENA1 = 0x20000 + // Position of SLC1_RX_PF_VALID_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_RX_PF_VALID_INT_ENA1_Pos = 0x12 + // Bit mask of SLC1_RX_PF_VALID_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_RX_PF_VALID_INT_ENA1_Msk = 0x40000 + // Bit SLC1_RX_PF_VALID_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_RX_PF_VALID_INT_ENA1 = 0x40000 + // Position of SLC1_EXT_BIT0_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT0_INT_ENA1_Pos = 0x13 + // Bit mask of SLC1_EXT_BIT0_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT0_INT_ENA1_Msk = 0x80000 + // Bit SLC1_EXT_BIT0_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT0_INT_ENA1 = 0x80000 + // Position of SLC1_EXT_BIT1_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT1_INT_ENA1_Pos = 0x14 + // Bit mask of SLC1_EXT_BIT1_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT1_INT_ENA1_Msk = 0x100000 + // Bit SLC1_EXT_BIT1_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT1_INT_ENA1 = 0x100000 + // Position of SLC1_EXT_BIT2_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT2_INT_ENA1_Pos = 0x15 + // Bit mask of SLC1_EXT_BIT2_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT2_INT_ENA1_Msk = 0x200000 + // Bit SLC1_EXT_BIT2_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT2_INT_ENA1 = 0x200000 + // Position of SLC1_EXT_BIT3_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT3_INT_ENA1_Pos = 0x16 + // Bit mask of SLC1_EXT_BIT3_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT3_INT_ENA1_Msk = 0x400000 + // Bit SLC1_EXT_BIT3_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_EXT_BIT3_INT_ENA1 = 0x400000 + // Position of SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_Pos = 0x17 + // Bit mask of SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_Msk = 0x800000 + // Bit SLC1_WIFI_RX_NEW_PACKET_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 = 0x800000 + // Position of SLC1_HOST_RD_RETRY_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_HOST_RD_RETRY_INT_ENA1_Pos = 0x18 + // Bit mask of SLC1_HOST_RD_RETRY_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_HOST_RD_RETRY_INT_ENA1_Msk = 0x1000000 + // Bit SLC1_HOST_RD_RETRY_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_HOST_RD_RETRY_INT_ENA1 = 0x1000000 + // Position of SLC1_BT_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_BT_RX_NEW_PACKET_INT_ENA1_Pos = 0x19 + // Bit mask of SLC1_BT_RX_NEW_PACKET_INT_ENA1 field. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_BT_RX_NEW_PACKET_INT_ENA1_Msk = 0x2000000 + // Bit SLC1_BT_RX_NEW_PACKET_INT_ENA1. + SLCHOST_SLC1HOST_INT_ENA1_SLC1_BT_RX_NEW_PACKET_INT_ENA1 = 0x2000000 + + // SLCHOSTDATE: *******Description*********** + // Position of SLCHOST_DATE field. + SLCHOST_SLCHOSTDATE_SLCHOST_DATE_Pos = 0x0 + // Bit mask of SLCHOST_DATE field. + SLCHOST_SLCHOSTDATE_SLCHOST_DATE_Msk = 0xffffffff + + // SLCHOSTID: *******Description*********** + // Position of SLCHOST_ID field. + SLCHOST_SLCHOSTID_SLCHOST_ID_Pos = 0x0 + // Bit mask of SLCHOST_ID field. + SLCHOST_SLCHOSTID_SLCHOST_ID_Msk = 0xffffffff + + // CONF: *******Description*********** + // Position of FRC_SDIO11 field. + SLCHOST_CONF_FRC_SDIO11_Pos = 0x0 + // Bit mask of FRC_SDIO11 field. + SLCHOST_CONF_FRC_SDIO11_Msk = 0x1f + // Position of FRC_SDIO20 field. + SLCHOST_CONF_FRC_SDIO20_Pos = 0x5 + // Bit mask of FRC_SDIO20 field. + SLCHOST_CONF_FRC_SDIO20_Msk = 0x3e0 + // Position of FRC_NEG_SAMP field. + SLCHOST_CONF_FRC_NEG_SAMP_Pos = 0xa + // Bit mask of FRC_NEG_SAMP field. + SLCHOST_CONF_FRC_NEG_SAMP_Msk = 0x7c00 + // Position of FRC_POS_SAMP field. + SLCHOST_CONF_FRC_POS_SAMP_Pos = 0xf + // Bit mask of FRC_POS_SAMP field. + SLCHOST_CONF_FRC_POS_SAMP_Msk = 0xf8000 + // Position of FRC_QUICK_IN field. + SLCHOST_CONF_FRC_QUICK_IN_Pos = 0x14 + // Bit mask of FRC_QUICK_IN field. + SLCHOST_CONF_FRC_QUICK_IN_Msk = 0x1f00000 + // Position of SDIO20_INT_DELAY field. + SLCHOST_CONF_SDIO20_INT_DELAY_Pos = 0x19 + // Bit mask of SDIO20_INT_DELAY field. + SLCHOST_CONF_SDIO20_INT_DELAY_Msk = 0x2000000 + // Bit SDIO20_INT_DELAY. + SLCHOST_CONF_SDIO20_INT_DELAY = 0x2000000 + // Position of SDIO_PAD_PULLUP field. + SLCHOST_CONF_SDIO_PAD_PULLUP_Pos = 0x1a + // Bit mask of SDIO_PAD_PULLUP field. + SLCHOST_CONF_SDIO_PAD_PULLUP_Msk = 0x4000000 + // Bit SDIO_PAD_PULLUP. + SLCHOST_CONF_SDIO_PAD_PULLUP = 0x4000000 + // Position of HSPEED_CON_EN field. + SLCHOST_CONF_HSPEED_CON_EN_Pos = 0x1b + // Bit mask of HSPEED_CON_EN field. + SLCHOST_CONF_HSPEED_CON_EN_Msk = 0x8000000 + // Bit HSPEED_CON_EN. + SLCHOST_CONF_HSPEED_CON_EN = 0x8000000 + + // INF_ST: *******Description*********** + // Position of SDIO20_MODE field. + SLCHOST_INF_ST_SDIO20_MODE_Pos = 0x0 + // Bit mask of SDIO20_MODE field. + SLCHOST_INF_ST_SDIO20_MODE_Msk = 0x1f + // Position of SDIO_NEG_SAMP field. + SLCHOST_INF_ST_SDIO_NEG_SAMP_Pos = 0x5 + // Bit mask of SDIO_NEG_SAMP field. + SLCHOST_INF_ST_SDIO_NEG_SAMP_Msk = 0x3e0 + // Position of SDIO_QUICK_IN field. + SLCHOST_INF_ST_SDIO_QUICK_IN_Pos = 0xa + // Bit mask of SDIO_QUICK_IN field. + SLCHOST_INF_ST_SDIO_QUICK_IN_Msk = 0x7c00 + // Position of DLL_ON_SW field. + SLCHOST_INF_ST_DLL_ON_SW_Pos = 0xf + // Bit mask of DLL_ON_SW field. + SLCHOST_INF_ST_DLL_ON_SW_Msk = 0x8000 + // Bit DLL_ON_SW. + SLCHOST_INF_ST_DLL_ON_SW = 0x8000 + // Position of DLL_ON field. + SLCHOST_INF_ST_DLL_ON_Pos = 0x10 + // Bit mask of DLL_ON field. + SLCHOST_INF_ST_DLL_ON_Msk = 0x10000 + // Bit DLL_ON. + SLCHOST_INF_ST_DLL_ON = 0x10000 + // Position of CLK_MODE_SW field. + SLCHOST_INF_ST_CLK_MODE_SW_Pos = 0x11 + // Bit mask of CLK_MODE_SW field. + SLCHOST_INF_ST_CLK_MODE_SW_Msk = 0x20000 + // Bit CLK_MODE_SW. + SLCHOST_INF_ST_CLK_MODE_SW = 0x20000 + // Position of CLK_MODE field. + SLCHOST_INF_ST_CLK_MODE_Pos = 0x12 + // Bit mask of CLK_MODE field. + SLCHOST_INF_ST_CLK_MODE_Msk = 0xc0000 +) + +// Constants for SOC_ETM: Event Task Matrix +const ( + // CH_ENA_AD0: channel enable register + // Position of CH_ENA0 field. + SOC_ETM_CH_ENA_AD0_CH_ENA0_Pos = 0x0 + // Bit mask of CH_ENA0 field. + SOC_ETM_CH_ENA_AD0_CH_ENA0_Msk = 0x1 + // Bit CH_ENA0. + SOC_ETM_CH_ENA_AD0_CH_ENA0 = 0x1 + // Position of CH_ENA1 field. + SOC_ETM_CH_ENA_AD0_CH_ENA1_Pos = 0x1 + // Bit mask of CH_ENA1 field. + SOC_ETM_CH_ENA_AD0_CH_ENA1_Msk = 0x2 + // Bit CH_ENA1. + SOC_ETM_CH_ENA_AD0_CH_ENA1 = 0x2 + // Position of CH_ENA2 field. + SOC_ETM_CH_ENA_AD0_CH_ENA2_Pos = 0x2 + // Bit mask of CH_ENA2 field. + SOC_ETM_CH_ENA_AD0_CH_ENA2_Msk = 0x4 + // Bit CH_ENA2. + SOC_ETM_CH_ENA_AD0_CH_ENA2 = 0x4 + // Position of CH_ENA3 field. + SOC_ETM_CH_ENA_AD0_CH_ENA3_Pos = 0x3 + // Bit mask of CH_ENA3 field. + SOC_ETM_CH_ENA_AD0_CH_ENA3_Msk = 0x8 + // Bit CH_ENA3. + SOC_ETM_CH_ENA_AD0_CH_ENA3 = 0x8 + // Position of CH_ENA4 field. + SOC_ETM_CH_ENA_AD0_CH_ENA4_Pos = 0x4 + // Bit mask of CH_ENA4 field. + SOC_ETM_CH_ENA_AD0_CH_ENA4_Msk = 0x10 + // Bit CH_ENA4. + SOC_ETM_CH_ENA_AD0_CH_ENA4 = 0x10 + // Position of CH_ENA5 field. + SOC_ETM_CH_ENA_AD0_CH_ENA5_Pos = 0x5 + // Bit mask of CH_ENA5 field. + SOC_ETM_CH_ENA_AD0_CH_ENA5_Msk = 0x20 + // Bit CH_ENA5. + SOC_ETM_CH_ENA_AD0_CH_ENA5 = 0x20 + // Position of CH_ENA6 field. + SOC_ETM_CH_ENA_AD0_CH_ENA6_Pos = 0x6 + // Bit mask of CH_ENA6 field. + SOC_ETM_CH_ENA_AD0_CH_ENA6_Msk = 0x40 + // Bit CH_ENA6. + SOC_ETM_CH_ENA_AD0_CH_ENA6 = 0x40 + // Position of CH_ENA7 field. + SOC_ETM_CH_ENA_AD0_CH_ENA7_Pos = 0x7 + // Bit mask of CH_ENA7 field. + SOC_ETM_CH_ENA_AD0_CH_ENA7_Msk = 0x80 + // Bit CH_ENA7. + SOC_ETM_CH_ENA_AD0_CH_ENA7 = 0x80 + // Position of CH_ENA8 field. + SOC_ETM_CH_ENA_AD0_CH_ENA8_Pos = 0x8 + // Bit mask of CH_ENA8 field. + SOC_ETM_CH_ENA_AD0_CH_ENA8_Msk = 0x100 + // Bit CH_ENA8. + SOC_ETM_CH_ENA_AD0_CH_ENA8 = 0x100 + // Position of CH_ENA9 field. + SOC_ETM_CH_ENA_AD0_CH_ENA9_Pos = 0x9 + // Bit mask of CH_ENA9 field. + SOC_ETM_CH_ENA_AD0_CH_ENA9_Msk = 0x200 + // Bit CH_ENA9. + SOC_ETM_CH_ENA_AD0_CH_ENA9 = 0x200 + // Position of CH_ENA10 field. + SOC_ETM_CH_ENA_AD0_CH_ENA10_Pos = 0xa + // Bit mask of CH_ENA10 field. + SOC_ETM_CH_ENA_AD0_CH_ENA10_Msk = 0x400 + // Bit CH_ENA10. + SOC_ETM_CH_ENA_AD0_CH_ENA10 = 0x400 + // Position of CH_ENA11 field. + SOC_ETM_CH_ENA_AD0_CH_ENA11_Pos = 0xb + // Bit mask of CH_ENA11 field. + SOC_ETM_CH_ENA_AD0_CH_ENA11_Msk = 0x800 + // Bit CH_ENA11. + SOC_ETM_CH_ENA_AD0_CH_ENA11 = 0x800 + // Position of CH_ENA12 field. + SOC_ETM_CH_ENA_AD0_CH_ENA12_Pos = 0xc + // Bit mask of CH_ENA12 field. + SOC_ETM_CH_ENA_AD0_CH_ENA12_Msk = 0x1000 + // Bit CH_ENA12. + SOC_ETM_CH_ENA_AD0_CH_ENA12 = 0x1000 + // Position of CH_ENA13 field. + SOC_ETM_CH_ENA_AD0_CH_ENA13_Pos = 0xd + // Bit mask of CH_ENA13 field. + SOC_ETM_CH_ENA_AD0_CH_ENA13_Msk = 0x2000 + // Bit CH_ENA13. + SOC_ETM_CH_ENA_AD0_CH_ENA13 = 0x2000 + // Position of CH_ENA14 field. + SOC_ETM_CH_ENA_AD0_CH_ENA14_Pos = 0xe + // Bit mask of CH_ENA14 field. + SOC_ETM_CH_ENA_AD0_CH_ENA14_Msk = 0x4000 + // Bit CH_ENA14. + SOC_ETM_CH_ENA_AD0_CH_ENA14 = 0x4000 + // Position of CH_ENA15 field. + SOC_ETM_CH_ENA_AD0_CH_ENA15_Pos = 0xf + // Bit mask of CH_ENA15 field. + SOC_ETM_CH_ENA_AD0_CH_ENA15_Msk = 0x8000 + // Bit CH_ENA15. + SOC_ETM_CH_ENA_AD0_CH_ENA15 = 0x8000 + // Position of CH_ENA16 field. + SOC_ETM_CH_ENA_AD0_CH_ENA16_Pos = 0x10 + // Bit mask of CH_ENA16 field. + SOC_ETM_CH_ENA_AD0_CH_ENA16_Msk = 0x10000 + // Bit CH_ENA16. + SOC_ETM_CH_ENA_AD0_CH_ENA16 = 0x10000 + // Position of CH_ENA17 field. + SOC_ETM_CH_ENA_AD0_CH_ENA17_Pos = 0x11 + // Bit mask of CH_ENA17 field. + SOC_ETM_CH_ENA_AD0_CH_ENA17_Msk = 0x20000 + // Bit CH_ENA17. + SOC_ETM_CH_ENA_AD0_CH_ENA17 = 0x20000 + // Position of CH_ENA18 field. + SOC_ETM_CH_ENA_AD0_CH_ENA18_Pos = 0x12 + // Bit mask of CH_ENA18 field. + SOC_ETM_CH_ENA_AD0_CH_ENA18_Msk = 0x40000 + // Bit CH_ENA18. + SOC_ETM_CH_ENA_AD0_CH_ENA18 = 0x40000 + // Position of CH_ENA19 field. + SOC_ETM_CH_ENA_AD0_CH_ENA19_Pos = 0x13 + // Bit mask of CH_ENA19 field. + SOC_ETM_CH_ENA_AD0_CH_ENA19_Msk = 0x80000 + // Bit CH_ENA19. + SOC_ETM_CH_ENA_AD0_CH_ENA19 = 0x80000 + // Position of CH_ENA20 field. + SOC_ETM_CH_ENA_AD0_CH_ENA20_Pos = 0x14 + // Bit mask of CH_ENA20 field. + SOC_ETM_CH_ENA_AD0_CH_ENA20_Msk = 0x100000 + // Bit CH_ENA20. + SOC_ETM_CH_ENA_AD0_CH_ENA20 = 0x100000 + // Position of CH_ENA21 field. + SOC_ETM_CH_ENA_AD0_CH_ENA21_Pos = 0x15 + // Bit mask of CH_ENA21 field. + SOC_ETM_CH_ENA_AD0_CH_ENA21_Msk = 0x200000 + // Bit CH_ENA21. + SOC_ETM_CH_ENA_AD0_CH_ENA21 = 0x200000 + // Position of CH_ENA22 field. + SOC_ETM_CH_ENA_AD0_CH_ENA22_Pos = 0x16 + // Bit mask of CH_ENA22 field. + SOC_ETM_CH_ENA_AD0_CH_ENA22_Msk = 0x400000 + // Bit CH_ENA22. + SOC_ETM_CH_ENA_AD0_CH_ENA22 = 0x400000 + // Position of CH_ENA23 field. + SOC_ETM_CH_ENA_AD0_CH_ENA23_Pos = 0x17 + // Bit mask of CH_ENA23 field. + SOC_ETM_CH_ENA_AD0_CH_ENA23_Msk = 0x800000 + // Bit CH_ENA23. + SOC_ETM_CH_ENA_AD0_CH_ENA23 = 0x800000 + // Position of CH_ENA24 field. + SOC_ETM_CH_ENA_AD0_CH_ENA24_Pos = 0x18 + // Bit mask of CH_ENA24 field. + SOC_ETM_CH_ENA_AD0_CH_ENA24_Msk = 0x1000000 + // Bit CH_ENA24. + SOC_ETM_CH_ENA_AD0_CH_ENA24 = 0x1000000 + // Position of CH_ENA25 field. + SOC_ETM_CH_ENA_AD0_CH_ENA25_Pos = 0x19 + // Bit mask of CH_ENA25 field. + SOC_ETM_CH_ENA_AD0_CH_ENA25_Msk = 0x2000000 + // Bit CH_ENA25. + SOC_ETM_CH_ENA_AD0_CH_ENA25 = 0x2000000 + // Position of CH_ENA26 field. + SOC_ETM_CH_ENA_AD0_CH_ENA26_Pos = 0x1a + // Bit mask of CH_ENA26 field. + SOC_ETM_CH_ENA_AD0_CH_ENA26_Msk = 0x4000000 + // Bit CH_ENA26. + SOC_ETM_CH_ENA_AD0_CH_ENA26 = 0x4000000 + // Position of CH_ENA27 field. + SOC_ETM_CH_ENA_AD0_CH_ENA27_Pos = 0x1b + // Bit mask of CH_ENA27 field. + SOC_ETM_CH_ENA_AD0_CH_ENA27_Msk = 0x8000000 + // Bit CH_ENA27. + SOC_ETM_CH_ENA_AD0_CH_ENA27 = 0x8000000 + // Position of CH_ENA28 field. + SOC_ETM_CH_ENA_AD0_CH_ENA28_Pos = 0x1c + // Bit mask of CH_ENA28 field. + SOC_ETM_CH_ENA_AD0_CH_ENA28_Msk = 0x10000000 + // Bit CH_ENA28. + SOC_ETM_CH_ENA_AD0_CH_ENA28 = 0x10000000 + // Position of CH_ENA29 field. + SOC_ETM_CH_ENA_AD0_CH_ENA29_Pos = 0x1d + // Bit mask of CH_ENA29 field. + SOC_ETM_CH_ENA_AD0_CH_ENA29_Msk = 0x20000000 + // Bit CH_ENA29. + SOC_ETM_CH_ENA_AD0_CH_ENA29 = 0x20000000 + // Position of CH_ENA30 field. + SOC_ETM_CH_ENA_AD0_CH_ENA30_Pos = 0x1e + // Bit mask of CH_ENA30 field. + SOC_ETM_CH_ENA_AD0_CH_ENA30_Msk = 0x40000000 + // Bit CH_ENA30. + SOC_ETM_CH_ENA_AD0_CH_ENA30 = 0x40000000 + // Position of CH_ENA31 field. + SOC_ETM_CH_ENA_AD0_CH_ENA31_Pos = 0x1f + // Bit mask of CH_ENA31 field. + SOC_ETM_CH_ENA_AD0_CH_ENA31_Msk = 0x80000000 + // Bit CH_ENA31. + SOC_ETM_CH_ENA_AD0_CH_ENA31 = 0x80000000 + + // CH_ENA_AD0_SET: channel enable set register + // Position of CH_SET0 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET0_Pos = 0x0 + // Bit mask of CH_SET0 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET0_Msk = 0x1 + // Bit CH_SET0. + SOC_ETM_CH_ENA_AD0_SET_CH_SET0 = 0x1 + // Position of CH_SET1 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET1_Pos = 0x1 + // Bit mask of CH_SET1 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET1_Msk = 0x2 + // Bit CH_SET1. + SOC_ETM_CH_ENA_AD0_SET_CH_SET1 = 0x2 + // Position of CH_SET2 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET2_Pos = 0x2 + // Bit mask of CH_SET2 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET2_Msk = 0x4 + // Bit CH_SET2. + SOC_ETM_CH_ENA_AD0_SET_CH_SET2 = 0x4 + // Position of CH_SET3 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET3_Pos = 0x3 + // Bit mask of CH_SET3 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET3_Msk = 0x8 + // Bit CH_SET3. + SOC_ETM_CH_ENA_AD0_SET_CH_SET3 = 0x8 + // Position of CH_SET4 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET4_Pos = 0x4 + // Bit mask of CH_SET4 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET4_Msk = 0x10 + // Bit CH_SET4. + SOC_ETM_CH_ENA_AD0_SET_CH_SET4 = 0x10 + // Position of CH_SET5 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET5_Pos = 0x5 + // Bit mask of CH_SET5 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET5_Msk = 0x20 + // Bit CH_SET5. + SOC_ETM_CH_ENA_AD0_SET_CH_SET5 = 0x20 + // Position of CH_SET6 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET6_Pos = 0x6 + // Bit mask of CH_SET6 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET6_Msk = 0x40 + // Bit CH_SET6. + SOC_ETM_CH_ENA_AD0_SET_CH_SET6 = 0x40 + // Position of CH_SET7 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET7_Pos = 0x7 + // Bit mask of CH_SET7 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET7_Msk = 0x80 + // Bit CH_SET7. + SOC_ETM_CH_ENA_AD0_SET_CH_SET7 = 0x80 + // Position of CH_SET8 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET8_Pos = 0x8 + // Bit mask of CH_SET8 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET8_Msk = 0x100 + // Bit CH_SET8. + SOC_ETM_CH_ENA_AD0_SET_CH_SET8 = 0x100 + // Position of CH_SET9 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET9_Pos = 0x9 + // Bit mask of CH_SET9 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET9_Msk = 0x200 + // Bit CH_SET9. + SOC_ETM_CH_ENA_AD0_SET_CH_SET9 = 0x200 + // Position of CH_SET10 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET10_Pos = 0xa + // Bit mask of CH_SET10 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET10_Msk = 0x400 + // Bit CH_SET10. + SOC_ETM_CH_ENA_AD0_SET_CH_SET10 = 0x400 + // Position of CH_SET11 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET11_Pos = 0xb + // Bit mask of CH_SET11 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET11_Msk = 0x800 + // Bit CH_SET11. + SOC_ETM_CH_ENA_AD0_SET_CH_SET11 = 0x800 + // Position of CH_SET12 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET12_Pos = 0xc + // Bit mask of CH_SET12 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET12_Msk = 0x1000 + // Bit CH_SET12. + SOC_ETM_CH_ENA_AD0_SET_CH_SET12 = 0x1000 + // Position of CH_SET13 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET13_Pos = 0xd + // Bit mask of CH_SET13 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET13_Msk = 0x2000 + // Bit CH_SET13. + SOC_ETM_CH_ENA_AD0_SET_CH_SET13 = 0x2000 + // Position of CH_SET14 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET14_Pos = 0xe + // Bit mask of CH_SET14 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET14_Msk = 0x4000 + // Bit CH_SET14. + SOC_ETM_CH_ENA_AD0_SET_CH_SET14 = 0x4000 + // Position of CH_SET15 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET15_Pos = 0xf + // Bit mask of CH_SET15 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET15_Msk = 0x8000 + // Bit CH_SET15. + SOC_ETM_CH_ENA_AD0_SET_CH_SET15 = 0x8000 + // Position of CH_SET16 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET16_Pos = 0x10 + // Bit mask of CH_SET16 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET16_Msk = 0x10000 + // Bit CH_SET16. + SOC_ETM_CH_ENA_AD0_SET_CH_SET16 = 0x10000 + // Position of CH_SET17 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET17_Pos = 0x11 + // Bit mask of CH_SET17 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET17_Msk = 0x20000 + // Bit CH_SET17. + SOC_ETM_CH_ENA_AD0_SET_CH_SET17 = 0x20000 + // Position of CH_SET18 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET18_Pos = 0x12 + // Bit mask of CH_SET18 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET18_Msk = 0x40000 + // Bit CH_SET18. + SOC_ETM_CH_ENA_AD0_SET_CH_SET18 = 0x40000 + // Position of CH_SET19 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET19_Pos = 0x13 + // Bit mask of CH_SET19 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET19_Msk = 0x80000 + // Bit CH_SET19. + SOC_ETM_CH_ENA_AD0_SET_CH_SET19 = 0x80000 + // Position of CH_SET20 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET20_Pos = 0x14 + // Bit mask of CH_SET20 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET20_Msk = 0x100000 + // Bit CH_SET20. + SOC_ETM_CH_ENA_AD0_SET_CH_SET20 = 0x100000 + // Position of CH_SET21 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET21_Pos = 0x15 + // Bit mask of CH_SET21 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET21_Msk = 0x200000 + // Bit CH_SET21. + SOC_ETM_CH_ENA_AD0_SET_CH_SET21 = 0x200000 + // Position of CH_SET22 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET22_Pos = 0x16 + // Bit mask of CH_SET22 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET22_Msk = 0x400000 + // Bit CH_SET22. + SOC_ETM_CH_ENA_AD0_SET_CH_SET22 = 0x400000 + // Position of CH_SET23 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET23_Pos = 0x17 + // Bit mask of CH_SET23 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET23_Msk = 0x800000 + // Bit CH_SET23. + SOC_ETM_CH_ENA_AD0_SET_CH_SET23 = 0x800000 + // Position of CH_SET24 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET24_Pos = 0x18 + // Bit mask of CH_SET24 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET24_Msk = 0x1000000 + // Bit CH_SET24. + SOC_ETM_CH_ENA_AD0_SET_CH_SET24 = 0x1000000 + // Position of CH_SET25 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET25_Pos = 0x19 + // Bit mask of CH_SET25 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET25_Msk = 0x2000000 + // Bit CH_SET25. + SOC_ETM_CH_ENA_AD0_SET_CH_SET25 = 0x2000000 + // Position of CH_SET26 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET26_Pos = 0x1a + // Bit mask of CH_SET26 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET26_Msk = 0x4000000 + // Bit CH_SET26. + SOC_ETM_CH_ENA_AD0_SET_CH_SET26 = 0x4000000 + // Position of CH_SET27 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET27_Pos = 0x1b + // Bit mask of CH_SET27 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET27_Msk = 0x8000000 + // Bit CH_SET27. + SOC_ETM_CH_ENA_AD0_SET_CH_SET27 = 0x8000000 + // Position of CH_SET28 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET28_Pos = 0x1c + // Bit mask of CH_SET28 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET28_Msk = 0x10000000 + // Bit CH_SET28. + SOC_ETM_CH_ENA_AD0_SET_CH_SET28 = 0x10000000 + // Position of CH_SET29 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET29_Pos = 0x1d + // Bit mask of CH_SET29 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET29_Msk = 0x20000000 + // Bit CH_SET29. + SOC_ETM_CH_ENA_AD0_SET_CH_SET29 = 0x20000000 + // Position of CH_SET30 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET30_Pos = 0x1e + // Bit mask of CH_SET30 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET30_Msk = 0x40000000 + // Bit CH_SET30. + SOC_ETM_CH_ENA_AD0_SET_CH_SET30 = 0x40000000 + // Position of CH_SET31 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET31_Pos = 0x1f + // Bit mask of CH_SET31 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET31_Msk = 0x80000000 + // Bit CH_SET31. + SOC_ETM_CH_ENA_AD0_SET_CH_SET31 = 0x80000000 + + // CH_ENA_AD0_CLR: channel enable clear register + // Position of CH_CLR0 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR0_Pos = 0x0 + // Bit mask of CH_CLR0 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR0_Msk = 0x1 + // Bit CH_CLR0. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR0 = 0x1 + // Position of CH_CLR1 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR1_Pos = 0x1 + // Bit mask of CH_CLR1 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR1_Msk = 0x2 + // Bit CH_CLR1. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR1 = 0x2 + // Position of CH_CLR2 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR2_Pos = 0x2 + // Bit mask of CH_CLR2 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR2_Msk = 0x4 + // Bit CH_CLR2. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR2 = 0x4 + // Position of CH_CLR3 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR3_Pos = 0x3 + // Bit mask of CH_CLR3 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR3_Msk = 0x8 + // Bit CH_CLR3. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR3 = 0x8 + // Position of CH_CLR4 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR4_Pos = 0x4 + // Bit mask of CH_CLR4 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR4_Msk = 0x10 + // Bit CH_CLR4. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR4 = 0x10 + // Position of CH_CLR5 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR5_Pos = 0x5 + // Bit mask of CH_CLR5 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR5_Msk = 0x20 + // Bit CH_CLR5. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR5 = 0x20 + // Position of CH_CLR6 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR6_Pos = 0x6 + // Bit mask of CH_CLR6 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR6_Msk = 0x40 + // Bit CH_CLR6. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR6 = 0x40 + // Position of CH_CLR7 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR7_Pos = 0x7 + // Bit mask of CH_CLR7 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR7_Msk = 0x80 + // Bit CH_CLR7. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR7 = 0x80 + // Position of CH_CLR8 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR8_Pos = 0x8 + // Bit mask of CH_CLR8 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR8_Msk = 0x100 + // Bit CH_CLR8. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR8 = 0x100 + // Position of CH_CLR9 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR9_Pos = 0x9 + // Bit mask of CH_CLR9 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR9_Msk = 0x200 + // Bit CH_CLR9. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR9 = 0x200 + // Position of CH_CLR10 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR10_Pos = 0xa + // Bit mask of CH_CLR10 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR10_Msk = 0x400 + // Bit CH_CLR10. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR10 = 0x400 + // Position of CH_CLR11 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR11_Pos = 0xb + // Bit mask of CH_CLR11 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR11_Msk = 0x800 + // Bit CH_CLR11. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR11 = 0x800 + // Position of CH_CLR12 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR12_Pos = 0xc + // Bit mask of CH_CLR12 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR12_Msk = 0x1000 + // Bit CH_CLR12. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR12 = 0x1000 + // Position of CH_CLR13 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR13_Pos = 0xd + // Bit mask of CH_CLR13 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR13_Msk = 0x2000 + // Bit CH_CLR13. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR13 = 0x2000 + // Position of CH_CLR14 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR14_Pos = 0xe + // Bit mask of CH_CLR14 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR14_Msk = 0x4000 + // Bit CH_CLR14. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR14 = 0x4000 + // Position of CH_CLR15 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR15_Pos = 0xf + // Bit mask of CH_CLR15 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR15_Msk = 0x8000 + // Bit CH_CLR15. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR15 = 0x8000 + // Position of CH_CLR16 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR16_Pos = 0x10 + // Bit mask of CH_CLR16 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR16_Msk = 0x10000 + // Bit CH_CLR16. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR16 = 0x10000 + // Position of CH_CLR17 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR17_Pos = 0x11 + // Bit mask of CH_CLR17 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR17_Msk = 0x20000 + // Bit CH_CLR17. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR17 = 0x20000 + // Position of CH_CLR18 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR18_Pos = 0x12 + // Bit mask of CH_CLR18 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR18_Msk = 0x40000 + // Bit CH_CLR18. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR18 = 0x40000 + // Position of CH_CLR19 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR19_Pos = 0x13 + // Bit mask of CH_CLR19 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR19_Msk = 0x80000 + // Bit CH_CLR19. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR19 = 0x80000 + // Position of CH_CLR20 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR20_Pos = 0x14 + // Bit mask of CH_CLR20 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR20_Msk = 0x100000 + // Bit CH_CLR20. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR20 = 0x100000 + // Position of CH_CLR21 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR21_Pos = 0x15 + // Bit mask of CH_CLR21 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR21_Msk = 0x200000 + // Bit CH_CLR21. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR21 = 0x200000 + // Position of CH_CLR22 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR22_Pos = 0x16 + // Bit mask of CH_CLR22 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR22_Msk = 0x400000 + // Bit CH_CLR22. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR22 = 0x400000 + // Position of CH_CLR23 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR23_Pos = 0x17 + // Bit mask of CH_CLR23 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR23_Msk = 0x800000 + // Bit CH_CLR23. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR23 = 0x800000 + // Position of CH_CLR24 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR24_Pos = 0x18 + // Bit mask of CH_CLR24 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR24_Msk = 0x1000000 + // Bit CH_CLR24. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR24 = 0x1000000 + // Position of CH_CLR25 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR25_Pos = 0x19 + // Bit mask of CH_CLR25 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR25_Msk = 0x2000000 + // Bit CH_CLR25. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR25 = 0x2000000 + // Position of CH_CLR26 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR26_Pos = 0x1a + // Bit mask of CH_CLR26 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR26_Msk = 0x4000000 + // Bit CH_CLR26. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR26 = 0x4000000 + // Position of CH_CLR27 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR27_Pos = 0x1b + // Bit mask of CH_CLR27 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR27_Msk = 0x8000000 + // Bit CH_CLR27. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR27 = 0x8000000 + // Position of CH_CLR28 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR28_Pos = 0x1c + // Bit mask of CH_CLR28 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR28_Msk = 0x10000000 + // Bit CH_CLR28. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR28 = 0x10000000 + // Position of CH_CLR29 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR29_Pos = 0x1d + // Bit mask of CH_CLR29 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR29_Msk = 0x20000000 + // Bit CH_CLR29. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR29 = 0x20000000 + // Position of CH_CLR30 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR30_Pos = 0x1e + // Bit mask of CH_CLR30 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR30_Msk = 0x40000000 + // Bit CH_CLR30. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR30 = 0x40000000 + // Position of CH_CLR31 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR31_Pos = 0x1f + // Bit mask of CH_CLR31 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR31_Msk = 0x80000000 + // Bit CH_CLR31. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR31 = 0x80000000 + + // CH_ENA_AD1: channel enable register + // Position of CH_ENA32 field. + SOC_ETM_CH_ENA_AD1_CH_ENA32_Pos = 0x0 + // Bit mask of CH_ENA32 field. + SOC_ETM_CH_ENA_AD1_CH_ENA32_Msk = 0x1 + // Bit CH_ENA32. + SOC_ETM_CH_ENA_AD1_CH_ENA32 = 0x1 + // Position of CH_ENA33 field. + SOC_ETM_CH_ENA_AD1_CH_ENA33_Pos = 0x1 + // Bit mask of CH_ENA33 field. + SOC_ETM_CH_ENA_AD1_CH_ENA33_Msk = 0x2 + // Bit CH_ENA33. + SOC_ETM_CH_ENA_AD1_CH_ENA33 = 0x2 + // Position of CH_ENA34 field. + SOC_ETM_CH_ENA_AD1_CH_ENA34_Pos = 0x2 + // Bit mask of CH_ENA34 field. + SOC_ETM_CH_ENA_AD1_CH_ENA34_Msk = 0x4 + // Bit CH_ENA34. + SOC_ETM_CH_ENA_AD1_CH_ENA34 = 0x4 + // Position of CH_ENA35 field. + SOC_ETM_CH_ENA_AD1_CH_ENA35_Pos = 0x3 + // Bit mask of CH_ENA35 field. + SOC_ETM_CH_ENA_AD1_CH_ENA35_Msk = 0x8 + // Bit CH_ENA35. + SOC_ETM_CH_ENA_AD1_CH_ENA35 = 0x8 + // Position of CH_ENA36 field. + SOC_ETM_CH_ENA_AD1_CH_ENA36_Pos = 0x4 + // Bit mask of CH_ENA36 field. + SOC_ETM_CH_ENA_AD1_CH_ENA36_Msk = 0x10 + // Bit CH_ENA36. + SOC_ETM_CH_ENA_AD1_CH_ENA36 = 0x10 + // Position of CH_ENA37 field. + SOC_ETM_CH_ENA_AD1_CH_ENA37_Pos = 0x5 + // Bit mask of CH_ENA37 field. + SOC_ETM_CH_ENA_AD1_CH_ENA37_Msk = 0x20 + // Bit CH_ENA37. + SOC_ETM_CH_ENA_AD1_CH_ENA37 = 0x20 + // Position of CH_ENA38 field. + SOC_ETM_CH_ENA_AD1_CH_ENA38_Pos = 0x6 + // Bit mask of CH_ENA38 field. + SOC_ETM_CH_ENA_AD1_CH_ENA38_Msk = 0x40 + // Bit CH_ENA38. + SOC_ETM_CH_ENA_AD1_CH_ENA38 = 0x40 + // Position of CH_ENA39 field. + SOC_ETM_CH_ENA_AD1_CH_ENA39_Pos = 0x7 + // Bit mask of CH_ENA39 field. + SOC_ETM_CH_ENA_AD1_CH_ENA39_Msk = 0x80 + // Bit CH_ENA39. + SOC_ETM_CH_ENA_AD1_CH_ENA39 = 0x80 + // Position of CH_ENA40 field. + SOC_ETM_CH_ENA_AD1_CH_ENA40_Pos = 0x8 + // Bit mask of CH_ENA40 field. + SOC_ETM_CH_ENA_AD1_CH_ENA40_Msk = 0x100 + // Bit CH_ENA40. + SOC_ETM_CH_ENA_AD1_CH_ENA40 = 0x100 + // Position of CH_ENA41 field. + SOC_ETM_CH_ENA_AD1_CH_ENA41_Pos = 0x9 + // Bit mask of CH_ENA41 field. + SOC_ETM_CH_ENA_AD1_CH_ENA41_Msk = 0x200 + // Bit CH_ENA41. + SOC_ETM_CH_ENA_AD1_CH_ENA41 = 0x200 + // Position of CH_ENA42 field. + SOC_ETM_CH_ENA_AD1_CH_ENA42_Pos = 0xa + // Bit mask of CH_ENA42 field. + SOC_ETM_CH_ENA_AD1_CH_ENA42_Msk = 0x400 + // Bit CH_ENA42. + SOC_ETM_CH_ENA_AD1_CH_ENA42 = 0x400 + // Position of CH_ENA43 field. + SOC_ETM_CH_ENA_AD1_CH_ENA43_Pos = 0xb + // Bit mask of CH_ENA43 field. + SOC_ETM_CH_ENA_AD1_CH_ENA43_Msk = 0x800 + // Bit CH_ENA43. + SOC_ETM_CH_ENA_AD1_CH_ENA43 = 0x800 + // Position of CH_ENA44 field. + SOC_ETM_CH_ENA_AD1_CH_ENA44_Pos = 0xc + // Bit mask of CH_ENA44 field. + SOC_ETM_CH_ENA_AD1_CH_ENA44_Msk = 0x1000 + // Bit CH_ENA44. + SOC_ETM_CH_ENA_AD1_CH_ENA44 = 0x1000 + // Position of CH_ENA45 field. + SOC_ETM_CH_ENA_AD1_CH_ENA45_Pos = 0xd + // Bit mask of CH_ENA45 field. + SOC_ETM_CH_ENA_AD1_CH_ENA45_Msk = 0x2000 + // Bit CH_ENA45. + SOC_ETM_CH_ENA_AD1_CH_ENA45 = 0x2000 + // Position of CH_ENA46 field. + SOC_ETM_CH_ENA_AD1_CH_ENA46_Pos = 0xe + // Bit mask of CH_ENA46 field. + SOC_ETM_CH_ENA_AD1_CH_ENA46_Msk = 0x4000 + // Bit CH_ENA46. + SOC_ETM_CH_ENA_AD1_CH_ENA46 = 0x4000 + // Position of CH_ENA47 field. + SOC_ETM_CH_ENA_AD1_CH_ENA47_Pos = 0xf + // Bit mask of CH_ENA47 field. + SOC_ETM_CH_ENA_AD1_CH_ENA47_Msk = 0x8000 + // Bit CH_ENA47. + SOC_ETM_CH_ENA_AD1_CH_ENA47 = 0x8000 + // Position of CH_ENA48 field. + SOC_ETM_CH_ENA_AD1_CH_ENA48_Pos = 0x10 + // Bit mask of CH_ENA48 field. + SOC_ETM_CH_ENA_AD1_CH_ENA48_Msk = 0x10000 + // Bit CH_ENA48. + SOC_ETM_CH_ENA_AD1_CH_ENA48 = 0x10000 + // Position of CH_ENA49 field. + SOC_ETM_CH_ENA_AD1_CH_ENA49_Pos = 0x11 + // Bit mask of CH_ENA49 field. + SOC_ETM_CH_ENA_AD1_CH_ENA49_Msk = 0x20000 + // Bit CH_ENA49. + SOC_ETM_CH_ENA_AD1_CH_ENA49 = 0x20000 + + // CH_ENA_AD1_SET: channel enable set register + // Position of CH_SET32 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET32_Pos = 0x0 + // Bit mask of CH_SET32 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET32_Msk = 0x1 + // Bit CH_SET32. + SOC_ETM_CH_ENA_AD1_SET_CH_SET32 = 0x1 + // Position of CH_SET33 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET33_Pos = 0x1 + // Bit mask of CH_SET33 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET33_Msk = 0x2 + // Bit CH_SET33. + SOC_ETM_CH_ENA_AD1_SET_CH_SET33 = 0x2 + // Position of CH_SET34 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET34_Pos = 0x2 + // Bit mask of CH_SET34 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET34_Msk = 0x4 + // Bit CH_SET34. + SOC_ETM_CH_ENA_AD1_SET_CH_SET34 = 0x4 + // Position of CH_SET35 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET35_Pos = 0x3 + // Bit mask of CH_SET35 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET35_Msk = 0x8 + // Bit CH_SET35. + SOC_ETM_CH_ENA_AD1_SET_CH_SET35 = 0x8 + // Position of CH_SET36 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET36_Pos = 0x4 + // Bit mask of CH_SET36 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET36_Msk = 0x10 + // Bit CH_SET36. + SOC_ETM_CH_ENA_AD1_SET_CH_SET36 = 0x10 + // Position of CH_SET37 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET37_Pos = 0x5 + // Bit mask of CH_SET37 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET37_Msk = 0x20 + // Bit CH_SET37. + SOC_ETM_CH_ENA_AD1_SET_CH_SET37 = 0x20 + // Position of CH_SET38 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET38_Pos = 0x6 + // Bit mask of CH_SET38 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET38_Msk = 0x40 + // Bit CH_SET38. + SOC_ETM_CH_ENA_AD1_SET_CH_SET38 = 0x40 + // Position of CH_SET39 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET39_Pos = 0x7 + // Bit mask of CH_SET39 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET39_Msk = 0x80 + // Bit CH_SET39. + SOC_ETM_CH_ENA_AD1_SET_CH_SET39 = 0x80 + // Position of CH_SET40 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET40_Pos = 0x8 + // Bit mask of CH_SET40 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET40_Msk = 0x100 + // Bit CH_SET40. + SOC_ETM_CH_ENA_AD1_SET_CH_SET40 = 0x100 + // Position of CH_SET41 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET41_Pos = 0x9 + // Bit mask of CH_SET41 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET41_Msk = 0x200 + // Bit CH_SET41. + SOC_ETM_CH_ENA_AD1_SET_CH_SET41 = 0x200 + // Position of CH_SET42 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET42_Pos = 0xa + // Bit mask of CH_SET42 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET42_Msk = 0x400 + // Bit CH_SET42. + SOC_ETM_CH_ENA_AD1_SET_CH_SET42 = 0x400 + // Position of CH_SET43 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET43_Pos = 0xb + // Bit mask of CH_SET43 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET43_Msk = 0x800 + // Bit CH_SET43. + SOC_ETM_CH_ENA_AD1_SET_CH_SET43 = 0x800 + // Position of CH_SET44 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET44_Pos = 0xc + // Bit mask of CH_SET44 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET44_Msk = 0x1000 + // Bit CH_SET44. + SOC_ETM_CH_ENA_AD1_SET_CH_SET44 = 0x1000 + // Position of CH_SET45 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET45_Pos = 0xd + // Bit mask of CH_SET45 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET45_Msk = 0x2000 + // Bit CH_SET45. + SOC_ETM_CH_ENA_AD1_SET_CH_SET45 = 0x2000 + // Position of CH_SET46 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET46_Pos = 0xe + // Bit mask of CH_SET46 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET46_Msk = 0x4000 + // Bit CH_SET46. + SOC_ETM_CH_ENA_AD1_SET_CH_SET46 = 0x4000 + // Position of CH_SET47 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET47_Pos = 0xf + // Bit mask of CH_SET47 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET47_Msk = 0x8000 + // Bit CH_SET47. + SOC_ETM_CH_ENA_AD1_SET_CH_SET47 = 0x8000 + // Position of CH_SET48 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET48_Pos = 0x10 + // Bit mask of CH_SET48 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET48_Msk = 0x10000 + // Bit CH_SET48. + SOC_ETM_CH_ENA_AD1_SET_CH_SET48 = 0x10000 + // Position of CH_SET49 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET49_Pos = 0x11 + // Bit mask of CH_SET49 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET49_Msk = 0x20000 + // Bit CH_SET49. + SOC_ETM_CH_ENA_AD1_SET_CH_SET49 = 0x20000 + + // CH_ENA_AD1_CLR: channel enable clear register + // Position of CH_CLR32 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR32_Pos = 0x0 + // Bit mask of CH_CLR32 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR32_Msk = 0x1 + // Bit CH_CLR32. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR32 = 0x1 + // Position of CH_CLR33 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR33_Pos = 0x1 + // Bit mask of CH_CLR33 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR33_Msk = 0x2 + // Bit CH_CLR33. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR33 = 0x2 + // Position of CH_CLR34 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR34_Pos = 0x2 + // Bit mask of CH_CLR34 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR34_Msk = 0x4 + // Bit CH_CLR34. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR34 = 0x4 + // Position of CH_CLR35 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR35_Pos = 0x3 + // Bit mask of CH_CLR35 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR35_Msk = 0x8 + // Bit CH_CLR35. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR35 = 0x8 + // Position of CH_CLR36 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR36_Pos = 0x4 + // Bit mask of CH_CLR36 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR36_Msk = 0x10 + // Bit CH_CLR36. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR36 = 0x10 + // Position of CH_CLR37 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR37_Pos = 0x5 + // Bit mask of CH_CLR37 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR37_Msk = 0x20 + // Bit CH_CLR37. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR37 = 0x20 + // Position of CH_CLR38 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR38_Pos = 0x6 + // Bit mask of CH_CLR38 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR38_Msk = 0x40 + // Bit CH_CLR38. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR38 = 0x40 + // Position of CH_CLR39 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR39_Pos = 0x7 + // Bit mask of CH_CLR39 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR39_Msk = 0x80 + // Bit CH_CLR39. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR39 = 0x80 + // Position of CH_CLR40 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR40_Pos = 0x8 + // Bit mask of CH_CLR40 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR40_Msk = 0x100 + // Bit CH_CLR40. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR40 = 0x100 + // Position of CH_CLR41 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR41_Pos = 0x9 + // Bit mask of CH_CLR41 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR41_Msk = 0x200 + // Bit CH_CLR41. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR41 = 0x200 + // Position of CH_CLR42 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR42_Pos = 0xa + // Bit mask of CH_CLR42 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR42_Msk = 0x400 + // Bit CH_CLR42. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR42 = 0x400 + // Position of CH_CLR43 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR43_Pos = 0xb + // Bit mask of CH_CLR43 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR43_Msk = 0x800 + // Bit CH_CLR43. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR43 = 0x800 + // Position of CH_CLR44 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR44_Pos = 0xc + // Bit mask of CH_CLR44 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR44_Msk = 0x1000 + // Bit CH_CLR44. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR44 = 0x1000 + // Position of CH_CLR45 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR45_Pos = 0xd + // Bit mask of CH_CLR45 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR45_Msk = 0x2000 + // Bit CH_CLR45. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR45 = 0x2000 + // Position of CH_CLR46 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR46_Pos = 0xe + // Bit mask of CH_CLR46 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR46_Msk = 0x4000 + // Bit CH_CLR46. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR46 = 0x4000 + // Position of CH_CLR47 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR47_Pos = 0xf + // Bit mask of CH_CLR47 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR47_Msk = 0x8000 + // Bit CH_CLR47. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR47 = 0x8000 + // Position of CH_CLR48 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR48_Pos = 0x10 + // Bit mask of CH_CLR48 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR48_Msk = 0x10000 + // Bit CH_CLR48. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR48 = 0x10000 + // Position of CH_CLR49 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR49_Pos = 0x11 + // Bit mask of CH_CLR49 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR49_Msk = 0x20000 + // Bit CH_CLR49. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR49 = 0x20000 + + // CH0_EVT_ID: channel0 event id register + // Position of CH0_EVT_ID field. + SOC_ETM_CH0_EVT_ID_CH0_EVT_ID_Pos = 0x0 + // Bit mask of CH0_EVT_ID field. + SOC_ETM_CH0_EVT_ID_CH0_EVT_ID_Msk = 0xff + + // CH0_TASK_ID: channel0 task id register + // Position of CH0_TASK_ID field. + SOC_ETM_CH0_TASK_ID_CH0_TASK_ID_Pos = 0x0 + // Bit mask of CH0_TASK_ID field. + SOC_ETM_CH0_TASK_ID_CH0_TASK_ID_Msk = 0xff + + // CH1_EVT_ID: channel1 event id register + // Position of CH1_EVT_ID field. + SOC_ETM_CH1_EVT_ID_CH1_EVT_ID_Pos = 0x0 + // Bit mask of CH1_EVT_ID field. + SOC_ETM_CH1_EVT_ID_CH1_EVT_ID_Msk = 0xff + + // CH1_TASK_ID: channel1 task id register + // Position of CH1_TASK_ID field. + SOC_ETM_CH1_TASK_ID_CH1_TASK_ID_Pos = 0x0 + // Bit mask of CH1_TASK_ID field. + SOC_ETM_CH1_TASK_ID_CH1_TASK_ID_Msk = 0xff + + // CH2_EVT_ID: channel2 event id register + // Position of CH2_EVT_ID field. + SOC_ETM_CH2_EVT_ID_CH2_EVT_ID_Pos = 0x0 + // Bit mask of CH2_EVT_ID field. + SOC_ETM_CH2_EVT_ID_CH2_EVT_ID_Msk = 0xff + + // CH2_TASK_ID: channel2 task id register + // Position of CH2_TASK_ID field. + SOC_ETM_CH2_TASK_ID_CH2_TASK_ID_Pos = 0x0 + // Bit mask of CH2_TASK_ID field. + SOC_ETM_CH2_TASK_ID_CH2_TASK_ID_Msk = 0xff + + // CH3_EVT_ID: channel3 event id register + // Position of CH3_EVT_ID field. + SOC_ETM_CH3_EVT_ID_CH3_EVT_ID_Pos = 0x0 + // Bit mask of CH3_EVT_ID field. + SOC_ETM_CH3_EVT_ID_CH3_EVT_ID_Msk = 0xff + + // CH3_TASK_ID: channel3 task id register + // Position of CH3_TASK_ID field. + SOC_ETM_CH3_TASK_ID_CH3_TASK_ID_Pos = 0x0 + // Bit mask of CH3_TASK_ID field. + SOC_ETM_CH3_TASK_ID_CH3_TASK_ID_Msk = 0xff + + // CH4_EVT_ID: channel4 event id register + // Position of CH4_EVT_ID field. + SOC_ETM_CH4_EVT_ID_CH4_EVT_ID_Pos = 0x0 + // Bit mask of CH4_EVT_ID field. + SOC_ETM_CH4_EVT_ID_CH4_EVT_ID_Msk = 0xff + + // CH4_TASK_ID: channel4 task id register + // Position of CH4_TASK_ID field. + SOC_ETM_CH4_TASK_ID_CH4_TASK_ID_Pos = 0x0 + // Bit mask of CH4_TASK_ID field. + SOC_ETM_CH4_TASK_ID_CH4_TASK_ID_Msk = 0xff + + // CH5_EVT_ID: channel5 event id register + // Position of CH5_EVT_ID field. + SOC_ETM_CH5_EVT_ID_CH5_EVT_ID_Pos = 0x0 + // Bit mask of CH5_EVT_ID field. + SOC_ETM_CH5_EVT_ID_CH5_EVT_ID_Msk = 0xff + + // CH5_TASK_ID: channel5 task id register + // Position of CH5_TASK_ID field. + SOC_ETM_CH5_TASK_ID_CH5_TASK_ID_Pos = 0x0 + // Bit mask of CH5_TASK_ID field. + SOC_ETM_CH5_TASK_ID_CH5_TASK_ID_Msk = 0xff + + // CH6_EVT_ID: channel6 event id register + // Position of CH6_EVT_ID field. + SOC_ETM_CH6_EVT_ID_CH6_EVT_ID_Pos = 0x0 + // Bit mask of CH6_EVT_ID field. + SOC_ETM_CH6_EVT_ID_CH6_EVT_ID_Msk = 0xff + + // CH6_TASK_ID: channel6 task id register + // Position of CH6_TASK_ID field. + SOC_ETM_CH6_TASK_ID_CH6_TASK_ID_Pos = 0x0 + // Bit mask of CH6_TASK_ID field. + SOC_ETM_CH6_TASK_ID_CH6_TASK_ID_Msk = 0xff + + // CH7_EVT_ID: channel7 event id register + // Position of CH7_EVT_ID field. + SOC_ETM_CH7_EVT_ID_CH7_EVT_ID_Pos = 0x0 + // Bit mask of CH7_EVT_ID field. + SOC_ETM_CH7_EVT_ID_CH7_EVT_ID_Msk = 0xff + + // CH7_TASK_ID: channel7 task id register + // Position of CH7_TASK_ID field. + SOC_ETM_CH7_TASK_ID_CH7_TASK_ID_Pos = 0x0 + // Bit mask of CH7_TASK_ID field. + SOC_ETM_CH7_TASK_ID_CH7_TASK_ID_Msk = 0xff + + // CH8_EVT_ID: channel8 event id register + // Position of CH8_EVT_ID field. + SOC_ETM_CH8_EVT_ID_CH8_EVT_ID_Pos = 0x0 + // Bit mask of CH8_EVT_ID field. + SOC_ETM_CH8_EVT_ID_CH8_EVT_ID_Msk = 0xff + + // CH8_TASK_ID: channel8 task id register + // Position of CH8_TASK_ID field. + SOC_ETM_CH8_TASK_ID_CH8_TASK_ID_Pos = 0x0 + // Bit mask of CH8_TASK_ID field. + SOC_ETM_CH8_TASK_ID_CH8_TASK_ID_Msk = 0xff + + // CH9_EVT_ID: channel9 event id register + // Position of CH9_EVT_ID field. + SOC_ETM_CH9_EVT_ID_CH9_EVT_ID_Pos = 0x0 + // Bit mask of CH9_EVT_ID field. + SOC_ETM_CH9_EVT_ID_CH9_EVT_ID_Msk = 0xff + + // CH9_TASK_ID: channel9 task id register + // Position of CH9_TASK_ID field. + SOC_ETM_CH9_TASK_ID_CH9_TASK_ID_Pos = 0x0 + // Bit mask of CH9_TASK_ID field. + SOC_ETM_CH9_TASK_ID_CH9_TASK_ID_Msk = 0xff + + // CH10_EVT_ID: channel10 event id register + // Position of CH10_EVT_ID field. + SOC_ETM_CH10_EVT_ID_CH10_EVT_ID_Pos = 0x0 + // Bit mask of CH10_EVT_ID field. + SOC_ETM_CH10_EVT_ID_CH10_EVT_ID_Msk = 0xff + + // CH10_TASK_ID: channel10 task id register + // Position of CH10_TASK_ID field. + SOC_ETM_CH10_TASK_ID_CH10_TASK_ID_Pos = 0x0 + // Bit mask of CH10_TASK_ID field. + SOC_ETM_CH10_TASK_ID_CH10_TASK_ID_Msk = 0xff + + // CH11_EVT_ID: channel11 event id register + // Position of CH11_EVT_ID field. + SOC_ETM_CH11_EVT_ID_CH11_EVT_ID_Pos = 0x0 + // Bit mask of CH11_EVT_ID field. + SOC_ETM_CH11_EVT_ID_CH11_EVT_ID_Msk = 0xff + + // CH11_TASK_ID: channel11 task id register + // Position of CH11_TASK_ID field. + SOC_ETM_CH11_TASK_ID_CH11_TASK_ID_Pos = 0x0 + // Bit mask of CH11_TASK_ID field. + SOC_ETM_CH11_TASK_ID_CH11_TASK_ID_Msk = 0xff + + // CH12_EVT_ID: channel12 event id register + // Position of CH12_EVT_ID field. + SOC_ETM_CH12_EVT_ID_CH12_EVT_ID_Pos = 0x0 + // Bit mask of CH12_EVT_ID field. + SOC_ETM_CH12_EVT_ID_CH12_EVT_ID_Msk = 0xff + + // CH12_TASK_ID: channel12 task id register + // Position of CH12_TASK_ID field. + SOC_ETM_CH12_TASK_ID_CH12_TASK_ID_Pos = 0x0 + // Bit mask of CH12_TASK_ID field. + SOC_ETM_CH12_TASK_ID_CH12_TASK_ID_Msk = 0xff + + // CH13_EVT_ID: channel13 event id register + // Position of CH13_EVT_ID field. + SOC_ETM_CH13_EVT_ID_CH13_EVT_ID_Pos = 0x0 + // Bit mask of CH13_EVT_ID field. + SOC_ETM_CH13_EVT_ID_CH13_EVT_ID_Msk = 0xff + + // CH13_TASK_ID: channel13 task id register + // Position of CH13_TASK_ID field. + SOC_ETM_CH13_TASK_ID_CH13_TASK_ID_Pos = 0x0 + // Bit mask of CH13_TASK_ID field. + SOC_ETM_CH13_TASK_ID_CH13_TASK_ID_Msk = 0xff + + // CH14_EVT_ID: channel14 event id register + // Position of CH14_EVT_ID field. + SOC_ETM_CH14_EVT_ID_CH14_EVT_ID_Pos = 0x0 + // Bit mask of CH14_EVT_ID field. + SOC_ETM_CH14_EVT_ID_CH14_EVT_ID_Msk = 0xff + + // CH14_TASK_ID: channel14 task id register + // Position of CH14_TASK_ID field. + SOC_ETM_CH14_TASK_ID_CH14_TASK_ID_Pos = 0x0 + // Bit mask of CH14_TASK_ID field. + SOC_ETM_CH14_TASK_ID_CH14_TASK_ID_Msk = 0xff + + // CH15_EVT_ID: channel15 event id register + // Position of CH15_EVT_ID field. + SOC_ETM_CH15_EVT_ID_CH15_EVT_ID_Pos = 0x0 + // Bit mask of CH15_EVT_ID field. + SOC_ETM_CH15_EVT_ID_CH15_EVT_ID_Msk = 0xff + + // CH15_TASK_ID: channel15 task id register + // Position of CH15_TASK_ID field. + SOC_ETM_CH15_TASK_ID_CH15_TASK_ID_Pos = 0x0 + // Bit mask of CH15_TASK_ID field. + SOC_ETM_CH15_TASK_ID_CH15_TASK_ID_Msk = 0xff + + // CH16_EVT_ID: channel16 event id register + // Position of CH16_EVT_ID field. + SOC_ETM_CH16_EVT_ID_CH16_EVT_ID_Pos = 0x0 + // Bit mask of CH16_EVT_ID field. + SOC_ETM_CH16_EVT_ID_CH16_EVT_ID_Msk = 0xff + + // CH16_TASK_ID: channel16 task id register + // Position of CH16_TASK_ID field. + SOC_ETM_CH16_TASK_ID_CH16_TASK_ID_Pos = 0x0 + // Bit mask of CH16_TASK_ID field. + SOC_ETM_CH16_TASK_ID_CH16_TASK_ID_Msk = 0xff + + // CH17_EVT_ID: channel17 event id register + // Position of CH17_EVT_ID field. + SOC_ETM_CH17_EVT_ID_CH17_EVT_ID_Pos = 0x0 + // Bit mask of CH17_EVT_ID field. + SOC_ETM_CH17_EVT_ID_CH17_EVT_ID_Msk = 0xff + + // CH17_TASK_ID: channel17 task id register + // Position of CH17_TASK_ID field. + SOC_ETM_CH17_TASK_ID_CH17_TASK_ID_Pos = 0x0 + // Bit mask of CH17_TASK_ID field. + SOC_ETM_CH17_TASK_ID_CH17_TASK_ID_Msk = 0xff + + // CH18_EVT_ID: channel18 event id register + // Position of CH18_EVT_ID field. + SOC_ETM_CH18_EVT_ID_CH18_EVT_ID_Pos = 0x0 + // Bit mask of CH18_EVT_ID field. + SOC_ETM_CH18_EVT_ID_CH18_EVT_ID_Msk = 0xff + + // CH18_TASK_ID: channel18 task id register + // Position of CH18_TASK_ID field. + SOC_ETM_CH18_TASK_ID_CH18_TASK_ID_Pos = 0x0 + // Bit mask of CH18_TASK_ID field. + SOC_ETM_CH18_TASK_ID_CH18_TASK_ID_Msk = 0xff + + // CH19_EVT_ID: channel19 event id register + // Position of CH19_EVT_ID field. + SOC_ETM_CH19_EVT_ID_CH19_EVT_ID_Pos = 0x0 + // Bit mask of CH19_EVT_ID field. + SOC_ETM_CH19_EVT_ID_CH19_EVT_ID_Msk = 0xff + + // CH19_TASK_ID: channel19 task id register + // Position of CH19_TASK_ID field. + SOC_ETM_CH19_TASK_ID_CH19_TASK_ID_Pos = 0x0 + // Bit mask of CH19_TASK_ID field. + SOC_ETM_CH19_TASK_ID_CH19_TASK_ID_Msk = 0xff + + // CH20_EVT_ID: channel20 event id register + // Position of CH20_EVT_ID field. + SOC_ETM_CH20_EVT_ID_CH20_EVT_ID_Pos = 0x0 + // Bit mask of CH20_EVT_ID field. + SOC_ETM_CH20_EVT_ID_CH20_EVT_ID_Msk = 0xff + + // CH20_TASK_ID: channel20 task id register + // Position of CH20_TASK_ID field. + SOC_ETM_CH20_TASK_ID_CH20_TASK_ID_Pos = 0x0 + // Bit mask of CH20_TASK_ID field. + SOC_ETM_CH20_TASK_ID_CH20_TASK_ID_Msk = 0xff + + // CH21_EVT_ID: channel21 event id register + // Position of CH21_EVT_ID field. + SOC_ETM_CH21_EVT_ID_CH21_EVT_ID_Pos = 0x0 + // Bit mask of CH21_EVT_ID field. + SOC_ETM_CH21_EVT_ID_CH21_EVT_ID_Msk = 0xff + + // CH21_TASK_ID: channel21 task id register + // Position of CH21_TASK_ID field. + SOC_ETM_CH21_TASK_ID_CH21_TASK_ID_Pos = 0x0 + // Bit mask of CH21_TASK_ID field. + SOC_ETM_CH21_TASK_ID_CH21_TASK_ID_Msk = 0xff + + // CH22_EVT_ID: channel22 event id register + // Position of CH22_EVT_ID field. + SOC_ETM_CH22_EVT_ID_CH22_EVT_ID_Pos = 0x0 + // Bit mask of CH22_EVT_ID field. + SOC_ETM_CH22_EVT_ID_CH22_EVT_ID_Msk = 0xff + + // CH22_TASK_ID: channel22 task id register + // Position of CH22_TASK_ID field. + SOC_ETM_CH22_TASK_ID_CH22_TASK_ID_Pos = 0x0 + // Bit mask of CH22_TASK_ID field. + SOC_ETM_CH22_TASK_ID_CH22_TASK_ID_Msk = 0xff + + // CH23_EVT_ID: channel23 event id register + // Position of CH23_EVT_ID field. + SOC_ETM_CH23_EVT_ID_CH23_EVT_ID_Pos = 0x0 + // Bit mask of CH23_EVT_ID field. + SOC_ETM_CH23_EVT_ID_CH23_EVT_ID_Msk = 0xff + + // CH23_TASK_ID: channel23 task id register + // Position of CH23_TASK_ID field. + SOC_ETM_CH23_TASK_ID_CH23_TASK_ID_Pos = 0x0 + // Bit mask of CH23_TASK_ID field. + SOC_ETM_CH23_TASK_ID_CH23_TASK_ID_Msk = 0xff + + // CH24_EVT_ID: channel24 event id register + // Position of CH24_EVT_ID field. + SOC_ETM_CH24_EVT_ID_CH24_EVT_ID_Pos = 0x0 + // Bit mask of CH24_EVT_ID field. + SOC_ETM_CH24_EVT_ID_CH24_EVT_ID_Msk = 0xff + + // CH24_TASK_ID: channel24 task id register + // Position of CH24_TASK_ID field. + SOC_ETM_CH24_TASK_ID_CH24_TASK_ID_Pos = 0x0 + // Bit mask of CH24_TASK_ID field. + SOC_ETM_CH24_TASK_ID_CH24_TASK_ID_Msk = 0xff + + // CH25_EVT_ID: channel25 event id register + // Position of CH25_EVT_ID field. + SOC_ETM_CH25_EVT_ID_CH25_EVT_ID_Pos = 0x0 + // Bit mask of CH25_EVT_ID field. + SOC_ETM_CH25_EVT_ID_CH25_EVT_ID_Msk = 0xff + + // CH25_TASK_ID: channel25 task id register + // Position of CH25_TASK_ID field. + SOC_ETM_CH25_TASK_ID_CH25_TASK_ID_Pos = 0x0 + // Bit mask of CH25_TASK_ID field. + SOC_ETM_CH25_TASK_ID_CH25_TASK_ID_Msk = 0xff + + // CH26_EVT_ID: channel26 event id register + // Position of CH26_EVT_ID field. + SOC_ETM_CH26_EVT_ID_CH26_EVT_ID_Pos = 0x0 + // Bit mask of CH26_EVT_ID field. + SOC_ETM_CH26_EVT_ID_CH26_EVT_ID_Msk = 0xff + + // CH26_TASK_ID: channel26 task id register + // Position of CH26_TASK_ID field. + SOC_ETM_CH26_TASK_ID_CH26_TASK_ID_Pos = 0x0 + // Bit mask of CH26_TASK_ID field. + SOC_ETM_CH26_TASK_ID_CH26_TASK_ID_Msk = 0xff + + // CH27_EVT_ID: channel27 event id register + // Position of CH27_EVT_ID field. + SOC_ETM_CH27_EVT_ID_CH27_EVT_ID_Pos = 0x0 + // Bit mask of CH27_EVT_ID field. + SOC_ETM_CH27_EVT_ID_CH27_EVT_ID_Msk = 0xff + + // CH27_TASK_ID: channel27 task id register + // Position of CH27_TASK_ID field. + SOC_ETM_CH27_TASK_ID_CH27_TASK_ID_Pos = 0x0 + // Bit mask of CH27_TASK_ID field. + SOC_ETM_CH27_TASK_ID_CH27_TASK_ID_Msk = 0xff + + // CH28_EVT_ID: channel28 event id register + // Position of CH28_EVT_ID field. + SOC_ETM_CH28_EVT_ID_CH28_EVT_ID_Pos = 0x0 + // Bit mask of CH28_EVT_ID field. + SOC_ETM_CH28_EVT_ID_CH28_EVT_ID_Msk = 0xff + + // CH28_TASK_ID: channel28 task id register + // Position of CH28_TASK_ID field. + SOC_ETM_CH28_TASK_ID_CH28_TASK_ID_Pos = 0x0 + // Bit mask of CH28_TASK_ID field. + SOC_ETM_CH28_TASK_ID_CH28_TASK_ID_Msk = 0xff + + // CH29_EVT_ID: channel29 event id register + // Position of CH29_EVT_ID field. + SOC_ETM_CH29_EVT_ID_CH29_EVT_ID_Pos = 0x0 + // Bit mask of CH29_EVT_ID field. + SOC_ETM_CH29_EVT_ID_CH29_EVT_ID_Msk = 0xff + + // CH29_TASK_ID: channel29 task id register + // Position of CH29_TASK_ID field. + SOC_ETM_CH29_TASK_ID_CH29_TASK_ID_Pos = 0x0 + // Bit mask of CH29_TASK_ID field. + SOC_ETM_CH29_TASK_ID_CH29_TASK_ID_Msk = 0xff + + // CH30_EVT_ID: channel30 event id register + // Position of CH30_EVT_ID field. + SOC_ETM_CH30_EVT_ID_CH30_EVT_ID_Pos = 0x0 + // Bit mask of CH30_EVT_ID field. + SOC_ETM_CH30_EVT_ID_CH30_EVT_ID_Msk = 0xff + + // CH30_TASK_ID: channel30 task id register + // Position of CH30_TASK_ID field. + SOC_ETM_CH30_TASK_ID_CH30_TASK_ID_Pos = 0x0 + // Bit mask of CH30_TASK_ID field. + SOC_ETM_CH30_TASK_ID_CH30_TASK_ID_Msk = 0xff + + // CH31_EVT_ID: channel31 event id register + // Position of CH31_EVT_ID field. + SOC_ETM_CH31_EVT_ID_CH31_EVT_ID_Pos = 0x0 + // Bit mask of CH31_EVT_ID field. + SOC_ETM_CH31_EVT_ID_CH31_EVT_ID_Msk = 0xff + + // CH31_TASK_ID: channel31 task id register + // Position of CH31_TASK_ID field. + SOC_ETM_CH31_TASK_ID_CH31_TASK_ID_Pos = 0x0 + // Bit mask of CH31_TASK_ID field. + SOC_ETM_CH31_TASK_ID_CH31_TASK_ID_Msk = 0xff + + // CH32_EVT_ID: channel32 event id register + // Position of CH32_EVT_ID field. + SOC_ETM_CH32_EVT_ID_CH32_EVT_ID_Pos = 0x0 + // Bit mask of CH32_EVT_ID field. + SOC_ETM_CH32_EVT_ID_CH32_EVT_ID_Msk = 0xff + + // CH32_TASK_ID: channel32 task id register + // Position of CH32_TASK_ID field. + SOC_ETM_CH32_TASK_ID_CH32_TASK_ID_Pos = 0x0 + // Bit mask of CH32_TASK_ID field. + SOC_ETM_CH32_TASK_ID_CH32_TASK_ID_Msk = 0xff + + // CH33_EVT_ID: channel33 event id register + // Position of CH33_EVT_ID field. + SOC_ETM_CH33_EVT_ID_CH33_EVT_ID_Pos = 0x0 + // Bit mask of CH33_EVT_ID field. + SOC_ETM_CH33_EVT_ID_CH33_EVT_ID_Msk = 0xff + + // CH33_TASK_ID: channel33 task id register + // Position of CH33_TASK_ID field. + SOC_ETM_CH33_TASK_ID_CH33_TASK_ID_Pos = 0x0 + // Bit mask of CH33_TASK_ID field. + SOC_ETM_CH33_TASK_ID_CH33_TASK_ID_Msk = 0xff + + // CH34_EVT_ID: channel34 event id register + // Position of CH34_EVT_ID field. + SOC_ETM_CH34_EVT_ID_CH34_EVT_ID_Pos = 0x0 + // Bit mask of CH34_EVT_ID field. + SOC_ETM_CH34_EVT_ID_CH34_EVT_ID_Msk = 0xff + + // CH34_TASK_ID: channel34 task id register + // Position of CH34_TASK_ID field. + SOC_ETM_CH34_TASK_ID_CH34_TASK_ID_Pos = 0x0 + // Bit mask of CH34_TASK_ID field. + SOC_ETM_CH34_TASK_ID_CH34_TASK_ID_Msk = 0xff + + // CH35_EVT_ID: channel35 event id register + // Position of CH35_EVT_ID field. + SOC_ETM_CH35_EVT_ID_CH35_EVT_ID_Pos = 0x0 + // Bit mask of CH35_EVT_ID field. + SOC_ETM_CH35_EVT_ID_CH35_EVT_ID_Msk = 0xff + + // CH35_TASK_ID: channel35 task id register + // Position of CH35_TASK_ID field. + SOC_ETM_CH35_TASK_ID_CH35_TASK_ID_Pos = 0x0 + // Bit mask of CH35_TASK_ID field. + SOC_ETM_CH35_TASK_ID_CH35_TASK_ID_Msk = 0xff + + // CH36_EVT_ID: channel36 event id register + // Position of CH36_EVT_ID field. + SOC_ETM_CH36_EVT_ID_CH36_EVT_ID_Pos = 0x0 + // Bit mask of CH36_EVT_ID field. + SOC_ETM_CH36_EVT_ID_CH36_EVT_ID_Msk = 0xff + + // CH36_TASK_ID: channel36 task id register + // Position of CH36_TASK_ID field. + SOC_ETM_CH36_TASK_ID_CH36_TASK_ID_Pos = 0x0 + // Bit mask of CH36_TASK_ID field. + SOC_ETM_CH36_TASK_ID_CH36_TASK_ID_Msk = 0xff + + // CH37_EVT_ID: channel37 event id register + // Position of CH37_EVT_ID field. + SOC_ETM_CH37_EVT_ID_CH37_EVT_ID_Pos = 0x0 + // Bit mask of CH37_EVT_ID field. + SOC_ETM_CH37_EVT_ID_CH37_EVT_ID_Msk = 0xff + + // CH37_TASK_ID: channel37 task id register + // Position of CH37_TASK_ID field. + SOC_ETM_CH37_TASK_ID_CH37_TASK_ID_Pos = 0x0 + // Bit mask of CH37_TASK_ID field. + SOC_ETM_CH37_TASK_ID_CH37_TASK_ID_Msk = 0xff + + // CH38_EVT_ID: channel38 event id register + // Position of CH38_EVT_ID field. + SOC_ETM_CH38_EVT_ID_CH38_EVT_ID_Pos = 0x0 + // Bit mask of CH38_EVT_ID field. + SOC_ETM_CH38_EVT_ID_CH38_EVT_ID_Msk = 0xff + + // CH38_TASK_ID: channel38 task id register + // Position of CH38_TASK_ID field. + SOC_ETM_CH38_TASK_ID_CH38_TASK_ID_Pos = 0x0 + // Bit mask of CH38_TASK_ID field. + SOC_ETM_CH38_TASK_ID_CH38_TASK_ID_Msk = 0xff + + // CH39_EVT_ID: channel39 event id register + // Position of CH39_EVT_ID field. + SOC_ETM_CH39_EVT_ID_CH39_EVT_ID_Pos = 0x0 + // Bit mask of CH39_EVT_ID field. + SOC_ETM_CH39_EVT_ID_CH39_EVT_ID_Msk = 0xff + + // CH39_TASK_ID: channel39 task id register + // Position of CH39_TASK_ID field. + SOC_ETM_CH39_TASK_ID_CH39_TASK_ID_Pos = 0x0 + // Bit mask of CH39_TASK_ID field. + SOC_ETM_CH39_TASK_ID_CH39_TASK_ID_Msk = 0xff + + // CH40_EVT_ID: channel40 event id register + // Position of CH40_EVT_ID field. + SOC_ETM_CH40_EVT_ID_CH40_EVT_ID_Pos = 0x0 + // Bit mask of CH40_EVT_ID field. + SOC_ETM_CH40_EVT_ID_CH40_EVT_ID_Msk = 0xff + + // CH40_TASK_ID: channel40 task id register + // Position of CH40_TASK_ID field. + SOC_ETM_CH40_TASK_ID_CH40_TASK_ID_Pos = 0x0 + // Bit mask of CH40_TASK_ID field. + SOC_ETM_CH40_TASK_ID_CH40_TASK_ID_Msk = 0xff + + // CH41_EVT_ID: channel41 event id register + // Position of CH41_EVT_ID field. + SOC_ETM_CH41_EVT_ID_CH41_EVT_ID_Pos = 0x0 + // Bit mask of CH41_EVT_ID field. + SOC_ETM_CH41_EVT_ID_CH41_EVT_ID_Msk = 0xff + + // CH41_TASK_ID: channel41 task id register + // Position of CH41_TASK_ID field. + SOC_ETM_CH41_TASK_ID_CH41_TASK_ID_Pos = 0x0 + // Bit mask of CH41_TASK_ID field. + SOC_ETM_CH41_TASK_ID_CH41_TASK_ID_Msk = 0xff + + // CH42_EVT_ID: channel42 event id register + // Position of CH42_EVT_ID field. + SOC_ETM_CH42_EVT_ID_CH42_EVT_ID_Pos = 0x0 + // Bit mask of CH42_EVT_ID field. + SOC_ETM_CH42_EVT_ID_CH42_EVT_ID_Msk = 0xff + + // CH42_TASK_ID: channel42 task id register + // Position of CH42_TASK_ID field. + SOC_ETM_CH42_TASK_ID_CH42_TASK_ID_Pos = 0x0 + // Bit mask of CH42_TASK_ID field. + SOC_ETM_CH42_TASK_ID_CH42_TASK_ID_Msk = 0xff + + // CH43_EVT_ID: channel43 event id register + // Position of CH43_EVT_ID field. + SOC_ETM_CH43_EVT_ID_CH43_EVT_ID_Pos = 0x0 + // Bit mask of CH43_EVT_ID field. + SOC_ETM_CH43_EVT_ID_CH43_EVT_ID_Msk = 0xff + + // CH43_TASK_ID: channel43 task id register + // Position of CH43_TASK_ID field. + SOC_ETM_CH43_TASK_ID_CH43_TASK_ID_Pos = 0x0 + // Bit mask of CH43_TASK_ID field. + SOC_ETM_CH43_TASK_ID_CH43_TASK_ID_Msk = 0xff + + // CH44_EVT_ID: channel44 event id register + // Position of CH44_EVT_ID field. + SOC_ETM_CH44_EVT_ID_CH44_EVT_ID_Pos = 0x0 + // Bit mask of CH44_EVT_ID field. + SOC_ETM_CH44_EVT_ID_CH44_EVT_ID_Msk = 0xff + + // CH44_TASK_ID: channel44 task id register + // Position of CH44_TASK_ID field. + SOC_ETM_CH44_TASK_ID_CH44_TASK_ID_Pos = 0x0 + // Bit mask of CH44_TASK_ID field. + SOC_ETM_CH44_TASK_ID_CH44_TASK_ID_Msk = 0xff + + // CH45_EVT_ID: channel45 event id register + // Position of CH45_EVT_ID field. + SOC_ETM_CH45_EVT_ID_CH45_EVT_ID_Pos = 0x0 + // Bit mask of CH45_EVT_ID field. + SOC_ETM_CH45_EVT_ID_CH45_EVT_ID_Msk = 0xff + + // CH45_TASK_ID: channel45 task id register + // Position of CH45_TASK_ID field. + SOC_ETM_CH45_TASK_ID_CH45_TASK_ID_Pos = 0x0 + // Bit mask of CH45_TASK_ID field. + SOC_ETM_CH45_TASK_ID_CH45_TASK_ID_Msk = 0xff + + // CH46_EVT_ID: channel46 event id register + // Position of CH46_EVT_ID field. + SOC_ETM_CH46_EVT_ID_CH46_EVT_ID_Pos = 0x0 + // Bit mask of CH46_EVT_ID field. + SOC_ETM_CH46_EVT_ID_CH46_EVT_ID_Msk = 0xff + + // CH46_TASK_ID: channel46 task id register + // Position of CH46_TASK_ID field. + SOC_ETM_CH46_TASK_ID_CH46_TASK_ID_Pos = 0x0 + // Bit mask of CH46_TASK_ID field. + SOC_ETM_CH46_TASK_ID_CH46_TASK_ID_Msk = 0xff + + // CH47_EVT_ID: channel47 event id register + // Position of CH47_EVT_ID field. + SOC_ETM_CH47_EVT_ID_CH47_EVT_ID_Pos = 0x0 + // Bit mask of CH47_EVT_ID field. + SOC_ETM_CH47_EVT_ID_CH47_EVT_ID_Msk = 0xff + + // CH47_TASK_ID: channel47 task id register + // Position of CH47_TASK_ID field. + SOC_ETM_CH47_TASK_ID_CH47_TASK_ID_Pos = 0x0 + // Bit mask of CH47_TASK_ID field. + SOC_ETM_CH47_TASK_ID_CH47_TASK_ID_Msk = 0xff + + // CH48_EVT_ID: channel48 event id register + // Position of CH48_EVT_ID field. + SOC_ETM_CH48_EVT_ID_CH48_EVT_ID_Pos = 0x0 + // Bit mask of CH48_EVT_ID field. + SOC_ETM_CH48_EVT_ID_CH48_EVT_ID_Msk = 0xff + + // CH48_TASK_ID: channel48 task id register + // Position of CH48_TASK_ID field. + SOC_ETM_CH48_TASK_ID_CH48_TASK_ID_Pos = 0x0 + // Bit mask of CH48_TASK_ID field. + SOC_ETM_CH48_TASK_ID_CH48_TASK_ID_Msk = 0xff + + // CH49_EVT_ID: channel49 event id register + // Position of CH49_EVT_ID field. + SOC_ETM_CH49_EVT_ID_CH49_EVT_ID_Pos = 0x0 + // Bit mask of CH49_EVT_ID field. + SOC_ETM_CH49_EVT_ID_CH49_EVT_ID_Msk = 0xff + + // CH49_TASK_ID: channel49 task id register + // Position of CH49_TASK_ID field. + SOC_ETM_CH49_TASK_ID_CH49_TASK_ID_Pos = 0x0 + // Bit mask of CH49_TASK_ID field. + SOC_ETM_CH49_TASK_ID_CH49_TASK_ID_Msk = 0xff + + // CLK_EN: etm clock enable register + // Position of CLK_EN field. + SOC_ETM_CLK_EN_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SOC_ETM_CLK_EN_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SOC_ETM_CLK_EN_CLK_EN = 0x1 + + // DATE: etm date register + // Position of DATE field. + SOC_ETM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SOC_ETM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SPI0: SPI (Serial Peripheral Interface) Controller 0 +const ( + // SPI_MEM_CMD: SPI0 FSM status register + // Position of SPI_MEM_MST_ST field. + SPI0_SPI_MEM_CMD_SPI_MEM_MST_ST_Pos = 0x0 + // Bit mask of SPI_MEM_MST_ST field. + SPI0_SPI_MEM_CMD_SPI_MEM_MST_ST_Msk = 0xf + // Position of SPI_MEM_SLV_ST field. + SPI0_SPI_MEM_CMD_SPI_MEM_SLV_ST_Pos = 0x4 + // Bit mask of SPI_MEM_SLV_ST field. + SPI0_SPI_MEM_CMD_SPI_MEM_SLV_ST_Msk = 0xf0 + // Position of SPI_MEM_USR field. + SPI0_SPI_MEM_CMD_SPI_MEM_USR_Pos = 0x12 + // Bit mask of SPI_MEM_USR field. + SPI0_SPI_MEM_CMD_SPI_MEM_USR_Msk = 0x40000 + // Bit SPI_MEM_USR. + SPI0_SPI_MEM_CMD_SPI_MEM_USR = 0x40000 + + // SPI_MEM_CTRL: SPI0 control register. + // Position of SPI_MEM_WDUMMY_DQS_ALWAYS_OUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_Pos = 0x0 + // Bit mask of SPI_MEM_WDUMMY_DQS_ALWAYS_OUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_Msk = 0x1 + // Bit SPI_MEM_WDUMMY_DQS_ALWAYS_OUT. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT = 0x1 + // Position of SPI_MEM_WDUMMY_ALWAYS_OUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT_Pos = 0x1 + // Bit mask of SPI_MEM_WDUMMY_ALWAYS_OUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT_Msk = 0x2 + // Bit SPI_MEM_WDUMMY_ALWAYS_OUT. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT = 0x2 + // Position of SPI_MEM_FDUMMY_RIN field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Pos = 0x2 + // Bit mask of SPI_MEM_FDUMMY_RIN field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Msk = 0x4 + // Bit SPI_MEM_FDUMMY_RIN. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN = 0x4 + // Position of SPI_MEM_FDUMMY_WOUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Pos = 0x3 + // Bit mask of SPI_MEM_FDUMMY_WOUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Msk = 0x8 + // Bit SPI_MEM_FDUMMY_WOUT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT = 0x8 + // Position of SPI_MEM_FDOUT_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Pos = 0x4 + // Bit mask of SPI_MEM_FDOUT_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Msk = 0x10 + // Bit SPI_MEM_FDOUT_OCT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT = 0x10 + // Position of SPI_MEM_FDIN_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Pos = 0x5 + // Bit mask of SPI_MEM_FDIN_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Msk = 0x20 + // Bit SPI_MEM_FDIN_OCT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT = 0x20 + // Position of SPI_MEM_FADDR_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Pos = 0x6 + // Bit mask of SPI_MEM_FADDR_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Msk = 0x40 + // Bit SPI_MEM_FADDR_OCT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT = 0x40 + // Position of SPI_MEM_FCMD_QUAD field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Pos = 0x8 + // Bit mask of SPI_MEM_FCMD_QUAD field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Msk = 0x100 + // Bit SPI_MEM_FCMD_QUAD. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD = 0x100 + // Position of SPI_MEM_FCMD_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Pos = 0x9 + // Bit mask of SPI_MEM_FCMD_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Msk = 0x200 + // Bit SPI_MEM_FCMD_OCT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT = 0x200 + // Position of SPI_MEM_FASTRD_MODE field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Pos = 0xd + // Bit mask of SPI_MEM_FASTRD_MODE field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Msk = 0x2000 + // Bit SPI_MEM_FASTRD_MODE. + SPI0_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE = 0x2000 + // Position of SPI_MEM_FREAD_DUAL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Pos = 0xe + // Bit mask of SPI_MEM_FREAD_DUAL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Msk = 0x4000 + // Bit SPI_MEM_FREAD_DUAL. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL = 0x4000 + // Position of SPI_MEM_Q_POL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_Q_POL_Pos = 0x12 + // Bit mask of SPI_MEM_Q_POL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_Q_POL_Msk = 0x40000 + // Bit SPI_MEM_Q_POL. + SPI0_SPI_MEM_CTRL_SPI_MEM_Q_POL = 0x40000 + // Position of SPI_MEM_D_POL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_D_POL_Pos = 0x13 + // Bit mask of SPI_MEM_D_POL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_D_POL_Msk = 0x80000 + // Bit SPI_MEM_D_POL. + SPI0_SPI_MEM_CTRL_SPI_MEM_D_POL = 0x80000 + // Position of SPI_MEM_FREAD_QUAD field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Pos = 0x14 + // Bit mask of SPI_MEM_FREAD_QUAD field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Msk = 0x100000 + // Bit SPI_MEM_FREAD_QUAD. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD = 0x100000 + // Position of SPI_MEM_WP field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WP_Pos = 0x15 + // Bit mask of SPI_MEM_WP field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WP_Msk = 0x200000 + // Bit SPI_MEM_WP. + SPI0_SPI_MEM_CTRL_SPI_MEM_WP = 0x200000 + // Position of SPI_MEM_FREAD_DIO field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Pos = 0x17 + // Bit mask of SPI_MEM_FREAD_DIO field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Msk = 0x800000 + // Bit SPI_MEM_FREAD_DIO. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO = 0x800000 + // Position of SPI_MEM_FREAD_QIO field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Pos = 0x18 + // Bit mask of SPI_MEM_FREAD_QIO field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Msk = 0x1000000 + // Bit SPI_MEM_FREAD_QIO. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO = 0x1000000 + // Position of SPI_MEM_DQS_IE_ALWAYS_ON field. + SPI0_SPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON_Pos = 0x1e + // Bit mask of SPI_MEM_DQS_IE_ALWAYS_ON field. + SPI0_SPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON_Msk = 0x40000000 + // Bit SPI_MEM_DQS_IE_ALWAYS_ON. + SPI0_SPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON = 0x40000000 + // Position of SPI_MEM_DATA_IE_ALWAYS_ON field. + SPI0_SPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON_Pos = 0x1f + // Bit mask of SPI_MEM_DATA_IE_ALWAYS_ON field. + SPI0_SPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON_Msk = 0x80000000 + // Bit SPI_MEM_DATA_IE_ALWAYS_ON. + SPI0_SPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON = 0x80000000 + + // SPI_MEM_CTRL1: SPI0 control1 register. + // Position of SPI_MEM_CLK_MODE field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_CLK_MODE field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Msk = 0x3 + // Position of SPI_AR_SIZE0_1_SUPPORT_EN field. + SPI0_SPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN_Pos = 0x15 + // Bit mask of SPI_AR_SIZE0_1_SUPPORT_EN field. + SPI0_SPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN_Msk = 0x200000 + // Bit SPI_AR_SIZE0_1_SUPPORT_EN. + SPI0_SPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN = 0x200000 + // Position of SPI_AW_SIZE0_1_SUPPORT_EN field. + SPI0_SPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN_Pos = 0x16 + // Bit mask of SPI_AW_SIZE0_1_SUPPORT_EN field. + SPI0_SPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN_Msk = 0x400000 + // Bit SPI_AW_SIZE0_1_SUPPORT_EN. + SPI0_SPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN = 0x400000 + // Position of SPI_AXI_RDATA_BACK_FAST field. + SPI0_SPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST_Pos = 0x17 + // Bit mask of SPI_AXI_RDATA_BACK_FAST field. + SPI0_SPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST_Msk = 0x800000 + // Bit SPI_AXI_RDATA_BACK_FAST. + SPI0_SPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST = 0x800000 + // Position of SPI_MEM_RRESP_ECC_ERR_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN_Pos = 0x18 + // Bit mask of SPI_MEM_RRESP_ECC_ERR_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN_Msk = 0x1000000 + // Bit SPI_MEM_RRESP_ECC_ERR_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN = 0x1000000 + // Position of SPI_MEM_AR_SPLICE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN_Pos = 0x19 + // Bit mask of SPI_MEM_AR_SPLICE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN_Msk = 0x2000000 + // Bit SPI_MEM_AR_SPLICE_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN = 0x2000000 + // Position of SPI_MEM_AW_SPLICE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN_Pos = 0x1a + // Bit mask of SPI_MEM_AW_SPLICE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN_Msk = 0x4000000 + // Bit SPI_MEM_AW_SPLICE_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN = 0x4000000 + // Position of SPI_MEM_RAM0_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RAM0_EN_Pos = 0x1b + // Bit mask of SPI_MEM_RAM0_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RAM0_EN_Msk = 0x8000000 + // Bit SPI_MEM_RAM0_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RAM0_EN = 0x8000000 + // Position of SPI_MEM_DUAL_RAM_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN_Pos = 0x1c + // Bit mask of SPI_MEM_DUAL_RAM_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN_Msk = 0x10000000 + // Bit SPI_MEM_DUAL_RAM_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN = 0x10000000 + // Position of SPI_MEM_FAST_WRITE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN_Pos = 0x1d + // Bit mask of SPI_MEM_FAST_WRITE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN_Msk = 0x20000000 + // Bit SPI_MEM_FAST_WRITE_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN = 0x20000000 + // Position of SPI_MEM_RXFIFO_RST field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST_Pos = 0x1e + // Bit mask of SPI_MEM_RXFIFO_RST field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST_Msk = 0x40000000 + // Bit SPI_MEM_RXFIFO_RST. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST = 0x40000000 + // Position of SPI_MEM_TXFIFO_RST field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST_Pos = 0x1f + // Bit mask of SPI_MEM_TXFIFO_RST field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST_Msk = 0x80000000 + // Bit SPI_MEM_TXFIFO_RST. + SPI0_SPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST = 0x80000000 + + // SPI_MEM_CTRL2: SPI0 control2 register. + // Position of SPI_MEM_CS_SETUP_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME_Pos = 0x0 + // Bit mask of SPI_MEM_CS_SETUP_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME_Msk = 0x1f + // Position of SPI_MEM_CS_HOLD_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME_Pos = 0x5 + // Bit mask of SPI_MEM_CS_HOLD_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME_Msk = 0x3e0 + // Position of SPI_MEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME_Pos = 0xa + // Bit mask of SPI_MEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME_Msk = 0x1c00 + // Position of SPI_MEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER_Pos = 0xd + // Bit mask of SPI_MEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER_Msk = 0x2000 + // Bit SPI_MEM_ECC_SKIP_PAGE_CORNER. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER = 0x2000 + // Position of SPI_MEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN_Pos = 0xe + // Bit mask of SPI_MEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN_Msk = 0x4000 + // Bit SPI_MEM_ECC_16TO18_BYTE_EN. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN = 0x4000 + // Position of SPI_MEM_SPLIT_TRANS_EN field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN_Pos = 0x18 + // Bit mask of SPI_MEM_SPLIT_TRANS_EN field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN_Msk = 0x1000000 + // Bit SPI_MEM_SPLIT_TRANS_EN. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN = 0x1000000 + // Position of SPI_MEM_CS_HOLD_DELAY field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY_Pos = 0x19 + // Bit mask of SPI_MEM_CS_HOLD_DELAY field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY_Msk = 0x7e000000 + // Position of SPI_MEM_SYNC_RESET field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Pos = 0x1f + // Bit mask of SPI_MEM_SYNC_RESET field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Msk = 0x80000000 + // Bit SPI_MEM_SYNC_RESET. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET = 0x80000000 + + // SPI_MEM_CLOCK: SPI clock division control register. + // Position of SPI_MEM_CLKCNT_L field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Pos = 0x0 + // Bit mask of SPI_MEM_CLKCNT_L field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Msk = 0xff + // Position of SPI_MEM_CLKCNT_H field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Pos = 0x8 + // Bit mask of SPI_MEM_CLKCNT_H field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Msk = 0xff00 + // Position of SPI_MEM_CLKCNT_N field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Pos = 0x10 + // Bit mask of SPI_MEM_CLKCNT_N field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Msk = 0xff0000 + // Position of SPI_MEM_CLK_EQU_SYSCLK field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of SPI_MEM_CLK_EQU_SYSCLK field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit SPI_MEM_CLK_EQU_SYSCLK. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK = 0x80000000 + + // SPI_MEM_USER: SPI0 user register. + // Position of SPI_MEM_CS_HOLD field. + SPI0_SPI_MEM_USER_SPI_MEM_CS_HOLD_Pos = 0x6 + // Bit mask of SPI_MEM_CS_HOLD field. + SPI0_SPI_MEM_USER_SPI_MEM_CS_HOLD_Msk = 0x40 + // Bit SPI_MEM_CS_HOLD. + SPI0_SPI_MEM_USER_SPI_MEM_CS_HOLD = 0x40 + // Position of SPI_MEM_CS_SETUP field. + SPI0_SPI_MEM_USER_SPI_MEM_CS_SETUP_Pos = 0x7 + // Bit mask of SPI_MEM_CS_SETUP field. + SPI0_SPI_MEM_USER_SPI_MEM_CS_SETUP_Msk = 0x80 + // Bit SPI_MEM_CS_SETUP. + SPI0_SPI_MEM_USER_SPI_MEM_CS_SETUP = 0x80 + // Position of SPI_MEM_CK_OUT_EDGE field. + SPI0_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of SPI_MEM_CK_OUT_EDGE field. + SPI0_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Msk = 0x200 + // Bit SPI_MEM_CK_OUT_EDGE. + SPI0_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE = 0x200 + // Position of SPI_MEM_USR_DUMMY_IDLE field. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of SPI_MEM_USR_DUMMY_IDLE field. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit SPI_MEM_USR_DUMMY_IDLE. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE = 0x4000000 + // Position of SPI_MEM_USR_DUMMY field. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Pos = 0x1d + // Bit mask of SPI_MEM_USR_DUMMY field. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Msk = 0x20000000 + // Bit SPI_MEM_USR_DUMMY. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY = 0x20000000 + + // SPI_MEM_USER1: SPI0 user1 register. + // Position of SPI_MEM_USR_DUMMY_CYCLELEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of SPI_MEM_USR_DUMMY_CYCLELEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of SPI_MEM_USR_DBYTELEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_DBYTELEN_Pos = 0x6 + // Bit mask of SPI_MEM_USR_DBYTELEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_DBYTELEN_Msk = 0x1c0 + // Position of SPI_MEM_USR_ADDR_BITLEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of SPI_MEM_USR_ADDR_BITLEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // SPI_MEM_USER2: SPI0 user2 register. + // Position of SPI_MEM_USR_COMMAND_VALUE field. + SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_USR_COMMAND_VALUE field. + SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Msk = 0xffff + // Position of SPI_MEM_USR_COMMAND_BITLEN field. + SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of SPI_MEM_USR_COMMAND_BITLEN field. + SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // SPI_MEM_RD_STATUS: SPI0 read control register. + // Position of SPI_MEM_WB_MODE field. + SPI0_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Pos = 0x10 + // Bit mask of SPI_MEM_WB_MODE field. + SPI0_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Msk = 0xff0000 + + // SPI_MEM_MISC: SPI0 misc register + // Position of SPI_MEM_FSUB_PIN field. + SPI0_SPI_MEM_MISC_SPI_MEM_FSUB_PIN_Pos = 0x7 + // Bit mask of SPI_MEM_FSUB_PIN field. + SPI0_SPI_MEM_MISC_SPI_MEM_FSUB_PIN_Msk = 0x80 + // Bit SPI_MEM_FSUB_PIN. + SPI0_SPI_MEM_MISC_SPI_MEM_FSUB_PIN = 0x80 + // Position of SPI_MEM_SSUB_PIN field. + SPI0_SPI_MEM_MISC_SPI_MEM_SSUB_PIN_Pos = 0x8 + // Bit mask of SPI_MEM_SSUB_PIN field. + SPI0_SPI_MEM_MISC_SPI_MEM_SSUB_PIN_Msk = 0x100 + // Bit SPI_MEM_SSUB_PIN. + SPI0_SPI_MEM_MISC_SPI_MEM_SSUB_PIN = 0x100 + // Position of SPI_MEM_CK_IDLE_EDGE field. + SPI0_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of SPI_MEM_CK_IDLE_EDGE field. + SPI0_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Msk = 0x200 + // Bit SPI_MEM_CK_IDLE_EDGE. + SPI0_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE = 0x200 + // Position of SPI_MEM_CS_KEEP_ACTIVE field. + SPI0_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of SPI_MEM_CS_KEEP_ACTIVE field. + SPI0_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit SPI_MEM_CS_KEEP_ACTIVE. + SPI0_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE = 0x400 + + // SPI_MEM_CACHE_FCTRL: SPI0 bit mode control register. + // Position of SPI_MEM_AXI_REQ_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN_Pos = 0x0 + // Bit mask of SPI_MEM_AXI_REQ_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN_Msk = 0x1 + // Bit SPI_MEM_AXI_REQ_EN. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN = 0x1 + // Position of SPI_MEM_CACHE_USR_ADDR_4BYTE field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Pos = 0x1 + // Bit mask of SPI_MEM_CACHE_USR_ADDR_4BYTE field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Msk = 0x2 + // Bit SPI_MEM_CACHE_USR_ADDR_4BYTE. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE = 0x2 + // Position of SPI_MEM_CACHE_FLASH_USR_CMD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD_Pos = 0x2 + // Bit mask of SPI_MEM_CACHE_FLASH_USR_CMD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD_Msk = 0x4 + // Bit SPI_MEM_CACHE_FLASH_USR_CMD. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD = 0x4 + // Position of SPI_MEM_FDIN_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Pos = 0x3 + // Bit mask of SPI_MEM_FDIN_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Msk = 0x8 + // Bit SPI_MEM_FDIN_DUAL. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL = 0x8 + // Position of SPI_MEM_FDOUT_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Pos = 0x4 + // Bit mask of SPI_MEM_FDOUT_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Msk = 0x10 + // Bit SPI_MEM_FDOUT_DUAL. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL = 0x10 + // Position of SPI_MEM_FADDR_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Pos = 0x5 + // Bit mask of SPI_MEM_FADDR_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Msk = 0x20 + // Bit SPI_MEM_FADDR_DUAL. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL = 0x20 + // Position of SPI_MEM_FDIN_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Pos = 0x6 + // Bit mask of SPI_MEM_FDIN_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Msk = 0x40 + // Bit SPI_MEM_FDIN_QUAD. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD = 0x40 + // Position of SPI_MEM_FDOUT_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Pos = 0x7 + // Bit mask of SPI_MEM_FDOUT_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Msk = 0x80 + // Bit SPI_MEM_FDOUT_QUAD. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD = 0x80 + // Position of SPI_MEM_FADDR_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Pos = 0x8 + // Bit mask of SPI_MEM_FADDR_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Msk = 0x100 + // Bit SPI_MEM_FADDR_QUAD. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD = 0x100 + // Position of SPI_SAME_AW_AR_ADDR_CHK_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN_Pos = 0x1e + // Bit mask of SPI_SAME_AW_AR_ADDR_CHK_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN_Msk = 0x40000000 + // Bit SPI_SAME_AW_AR_ADDR_CHK_EN. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN = 0x40000000 + // Position of SPI_CLOSE_AXI_INF_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN_Pos = 0x1f + // Bit mask of SPI_CLOSE_AXI_INF_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN_Msk = 0x80000000 + // Bit SPI_CLOSE_AXI_INF_EN. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN = 0x80000000 + + // SPI_MEM_CACHE_SCTRL: SPI0 external RAM control register + // Position of SPI_MEM_CACHE_USR_SADDR_4BYTE field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE_Pos = 0x0 + // Bit mask of SPI_MEM_CACHE_USR_SADDR_4BYTE field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE_Msk = 0x1 + // Bit SPI_MEM_CACHE_USR_SADDR_4BYTE. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE = 0x1 + // Position of SPI_MEM_USR_SRAM_DIO field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO_Pos = 0x1 + // Bit mask of SPI_MEM_USR_SRAM_DIO field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO_Msk = 0x2 + // Bit SPI_MEM_USR_SRAM_DIO. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO = 0x2 + // Position of SPI_MEM_USR_SRAM_QIO field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO_Pos = 0x2 + // Bit mask of SPI_MEM_USR_SRAM_QIO field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO_Msk = 0x4 + // Bit SPI_MEM_USR_SRAM_QIO. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO = 0x4 + // Position of SPI_MEM_USR_WR_SRAM_DUMMY field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY_Pos = 0x3 + // Bit mask of SPI_MEM_USR_WR_SRAM_DUMMY field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY_Msk = 0x8 + // Bit SPI_MEM_USR_WR_SRAM_DUMMY. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY = 0x8 + // Position of SPI_MEM_USR_RD_SRAM_DUMMY field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY_Pos = 0x4 + // Bit mask of SPI_MEM_USR_RD_SRAM_DUMMY field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY_Msk = 0x10 + // Bit SPI_MEM_USR_RD_SRAM_DUMMY. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY = 0x10 + // Position of SPI_MEM_CACHE_SRAM_USR_RCMD field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD_Pos = 0x5 + // Bit mask of SPI_MEM_CACHE_SRAM_USR_RCMD field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD_Msk = 0x20 + // Bit SPI_MEM_CACHE_SRAM_USR_RCMD. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD = 0x20 + // Position of SPI_MEM_SRAM_RDUMMY_CYCLELEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN_Pos = 0x6 + // Bit mask of SPI_MEM_SRAM_RDUMMY_CYCLELEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN_Msk = 0xfc0 + // Position of SPI_MEM_SRAM_ADDR_BITLEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN_Pos = 0xe + // Bit mask of SPI_MEM_SRAM_ADDR_BITLEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN_Msk = 0xfc000 + // Position of SPI_MEM_CACHE_SRAM_USR_WCMD field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD_Pos = 0x14 + // Bit mask of SPI_MEM_CACHE_SRAM_USR_WCMD field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD_Msk = 0x100000 + // Bit SPI_MEM_CACHE_SRAM_USR_WCMD. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD = 0x100000 + // Position of SPI_MEM_SRAM_OCT field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT_Pos = 0x15 + // Bit mask of SPI_MEM_SRAM_OCT field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT_Msk = 0x200000 + // Bit SPI_MEM_SRAM_OCT. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT = 0x200000 + // Position of SPI_MEM_SRAM_WDUMMY_CYCLELEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN_Pos = 0x16 + // Bit mask of SPI_MEM_SRAM_WDUMMY_CYCLELEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN_Msk = 0xfc00000 + + // SPI_MEM_SRAM_CMD: SPI0 external RAM mode control register + // Position of SPI_MEM_SCLK_MODE field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_SCLK_MODE field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE_Msk = 0x3 + // Position of SPI_MEM_SWB_MODE field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE_Pos = 0x2 + // Bit mask of SPI_MEM_SWB_MODE field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE_Msk = 0x3fc + // Position of SPI_MEM_SDIN_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL_Pos = 0xa + // Bit mask of SPI_MEM_SDIN_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL_Msk = 0x400 + // Bit SPI_MEM_SDIN_DUAL. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL = 0x400 + // Position of SPI_MEM_SDOUT_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL_Pos = 0xb + // Bit mask of SPI_MEM_SDOUT_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL_Msk = 0x800 + // Bit SPI_MEM_SDOUT_DUAL. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL = 0x800 + // Position of SPI_MEM_SADDR_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL_Pos = 0xc + // Bit mask of SPI_MEM_SADDR_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL_Msk = 0x1000 + // Bit SPI_MEM_SADDR_DUAL. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL = 0x1000 + // Position of SPI_MEM_SDIN_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD_Pos = 0xe + // Bit mask of SPI_MEM_SDIN_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD_Msk = 0x4000 + // Bit SPI_MEM_SDIN_QUAD. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD = 0x4000 + // Position of SPI_MEM_SDOUT_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD_Pos = 0xf + // Bit mask of SPI_MEM_SDOUT_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD_Msk = 0x8000 + // Bit SPI_MEM_SDOUT_QUAD. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD = 0x8000 + // Position of SPI_MEM_SADDR_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD_Pos = 0x10 + // Bit mask of SPI_MEM_SADDR_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD_Msk = 0x10000 + // Bit SPI_MEM_SADDR_QUAD. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD = 0x10000 + // Position of SPI_MEM_SCMD_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD_Pos = 0x11 + // Bit mask of SPI_MEM_SCMD_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD_Msk = 0x20000 + // Bit SPI_MEM_SCMD_QUAD. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD = 0x20000 + // Position of SPI_MEM_SDIN_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT_Pos = 0x12 + // Bit mask of SPI_MEM_SDIN_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT_Msk = 0x40000 + // Bit SPI_MEM_SDIN_OCT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT = 0x40000 + // Position of SPI_MEM_SDOUT_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT_Pos = 0x13 + // Bit mask of SPI_MEM_SDOUT_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT_Msk = 0x80000 + // Bit SPI_MEM_SDOUT_OCT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT = 0x80000 + // Position of SPI_MEM_SADDR_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT_Pos = 0x14 + // Bit mask of SPI_MEM_SADDR_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT_Msk = 0x100000 + // Bit SPI_MEM_SADDR_OCT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT = 0x100000 + // Position of SPI_MEM_SCMD_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT_Pos = 0x15 + // Bit mask of SPI_MEM_SCMD_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT_Msk = 0x200000 + // Bit SPI_MEM_SCMD_OCT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT = 0x200000 + // Position of SPI_MEM_SDUMMY_RIN field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN_Pos = 0x16 + // Bit mask of SPI_MEM_SDUMMY_RIN field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN_Msk = 0x400000 + // Bit SPI_MEM_SDUMMY_RIN. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN = 0x400000 + // Position of SPI_MEM_SDUMMY_WOUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT_Pos = 0x17 + // Bit mask of SPI_MEM_SDUMMY_WOUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT_Msk = 0x800000 + // Bit SPI_MEM_SDUMMY_WOUT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT = 0x800000 + // Position of SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_Pos = 0x18 + // Bit mask of SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_Msk = 0x1000000 + // Bit SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT = 0x1000000 + // Position of SPI_SMEM_WDUMMY_ALWAYS_OUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT_Pos = 0x19 + // Bit mask of SPI_SMEM_WDUMMY_ALWAYS_OUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT_Msk = 0x2000000 + // Bit SPI_SMEM_WDUMMY_ALWAYS_OUT. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT = 0x2000000 + // Position of SPI_SMEM_DQS_IE_ALWAYS_ON field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON_Pos = 0x1e + // Bit mask of SPI_SMEM_DQS_IE_ALWAYS_ON field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON_Msk = 0x40000000 + // Bit SPI_SMEM_DQS_IE_ALWAYS_ON. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON = 0x40000000 + // Position of SPI_SMEM_DATA_IE_ALWAYS_ON field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON_Pos = 0x1f + // Bit mask of SPI_SMEM_DATA_IE_ALWAYS_ON field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON_Msk = 0x80000000 + // Bit SPI_SMEM_DATA_IE_ALWAYS_ON. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON = 0x80000000 + + // SPI_MEM_SRAM_DRD_CMD: SPI0 external RAM DDR read command control register + // Position of SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE field. + SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE field. + SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_Msk = 0xffff + // Position of SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN field. + SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_Pos = 0x1c + // Bit mask of SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN field. + SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_Msk = 0xf0000000 + + // SPI_MEM_SRAM_DWR_CMD: SPI0 external RAM DDR write command control register + // Position of SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE field. + SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE field. + SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_Msk = 0xffff + // Position of SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN field. + SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_Pos = 0x1c + // Bit mask of SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN field. + SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_Msk = 0xf0000000 + + // SPI_MEM_SRAM_CLK: SPI0 external RAM clock control register + // Position of SPI_MEM_SCLKCNT_L field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L_Pos = 0x0 + // Bit mask of SPI_MEM_SCLKCNT_L field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L_Msk = 0xff + // Position of SPI_MEM_SCLKCNT_H field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H_Pos = 0x8 + // Bit mask of SPI_MEM_SCLKCNT_H field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H_Msk = 0xff00 + // Position of SPI_MEM_SCLKCNT_N field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N_Pos = 0x10 + // Bit mask of SPI_MEM_SCLKCNT_N field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N_Msk = 0xff0000 + // Position of SPI_MEM_SCLK_EQU_SYSCLK field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of SPI_MEM_SCLK_EQU_SYSCLK field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit SPI_MEM_SCLK_EQU_SYSCLK. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK = 0x80000000 + + // SPI_MEM_FSM: SPI0 FSM status register + // Position of SPI_MEM_LOCK_DELAY_TIME field. + SPI0_SPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME_Pos = 0x7 + // Bit mask of SPI_MEM_LOCK_DELAY_TIME field. + SPI0_SPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME_Msk = 0xf80 + + // SPI_MEM_INT_ENA: SPI0 interrupt enable register + // Position of SPI_MEM_SLV_ST_END_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA = 0x10 + // Position of SPI_MEM_ECC_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA_Pos = 0x5 + // Bit mask of SPI_MEM_ECC_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA_Msk = 0x20 + // Bit SPI_MEM_ECC_ERR_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA = 0x20 + // Position of SPI_MEM_PMS_REJECT_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA_Pos = 0x6 + // Bit mask of SPI_MEM_PMS_REJECT_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA_Msk = 0x40 + // Bit SPI_MEM_PMS_REJECT_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA = 0x40 + // Position of SPI_MEM_AXI_RADDR_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA_Pos = 0x7 + // Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA_Msk = 0x80 + // Bit SPI_MEM_AXI_RADDR_ERR_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA = 0x80 + // Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_Pos = 0x8 + // Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_Msk = 0x100 + // Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA = 0x100 + // Position of SPI_MEM_AXI_WADDR_ERR_INT__ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA_Pos = 0x9 + // Bit mask of SPI_MEM_AXI_WADDR_ERR_INT__ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA_Msk = 0x200 + // Bit SPI_MEM_AXI_WADDR_ERR_INT__ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA = 0x200 + + // SPI_MEM_INT_CLR: SPI0 interrupt clear register + // Position of SPI_MEM_SLV_ST_END_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR = 0x10 + // Position of SPI_MEM_ECC_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR_Pos = 0x5 + // Bit mask of SPI_MEM_ECC_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR_Msk = 0x20 + // Bit SPI_MEM_ECC_ERR_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR = 0x20 + // Position of SPI_MEM_PMS_REJECT_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR_Pos = 0x6 + // Bit mask of SPI_MEM_PMS_REJECT_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR_Msk = 0x40 + // Bit SPI_MEM_PMS_REJECT_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR = 0x40 + // Position of SPI_MEM_AXI_RADDR_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR_Pos = 0x7 + // Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR_Msk = 0x80 + // Bit SPI_MEM_AXI_RADDR_ERR_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR = 0x80 + // Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_Pos = 0x8 + // Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_Msk = 0x100 + // Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR = 0x100 + // Position of SPI_MEM_AXI_WADDR_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR_Pos = 0x9 + // Bit mask of SPI_MEM_AXI_WADDR_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR_Msk = 0x200 + // Bit SPI_MEM_AXI_WADDR_ERR_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR = 0x200 + + // SPI_MEM_INT_RAW: SPI0 interrupt raw register + // Position of SPI_MEM_SLV_ST_END_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW = 0x10 + // Position of SPI_MEM_ECC_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW_Pos = 0x5 + // Bit mask of SPI_MEM_ECC_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW_Msk = 0x20 + // Bit SPI_MEM_ECC_ERR_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW = 0x20 + // Position of SPI_MEM_PMS_REJECT_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW_Pos = 0x6 + // Bit mask of SPI_MEM_PMS_REJECT_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW_Msk = 0x40 + // Bit SPI_MEM_PMS_REJECT_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW = 0x40 + // Position of SPI_MEM_AXI_RADDR_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW_Pos = 0x7 + // Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW_Msk = 0x80 + // Bit SPI_MEM_AXI_RADDR_ERR_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW = 0x80 + // Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_Pos = 0x8 + // Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_Msk = 0x100 + // Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW = 0x100 + // Position of SPI_MEM_AXI_WADDR_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW_Pos = 0x9 + // Bit mask of SPI_MEM_AXI_WADDR_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW_Msk = 0x200 + // Bit SPI_MEM_AXI_WADDR_ERR_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW = 0x200 + + // SPI_MEM_INT_ST: SPI0 interrupt status register + // Position of SPI_MEM_SLV_ST_END_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST = 0x10 + // Position of SPI_MEM_ECC_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST_Pos = 0x5 + // Bit mask of SPI_MEM_ECC_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST_Msk = 0x20 + // Bit SPI_MEM_ECC_ERR_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST = 0x20 + // Position of SPI_MEM_PMS_REJECT_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST_Pos = 0x6 + // Bit mask of SPI_MEM_PMS_REJECT_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST_Msk = 0x40 + // Bit SPI_MEM_PMS_REJECT_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST = 0x40 + // Position of SPI_MEM_AXI_RADDR_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST_Pos = 0x7 + // Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST_Msk = 0x80 + // Bit SPI_MEM_AXI_RADDR_ERR_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST = 0x80 + // Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_Pos = 0x8 + // Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_Msk = 0x100 + // Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST = 0x100 + // Position of SPI_MEM_AXI_WADDR_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST_Pos = 0x9 + // Bit mask of SPI_MEM_AXI_WADDR_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST_Msk = 0x200 + // Bit SPI_MEM_AXI_WADDR_ERR_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST = 0x200 + + // SPI_MEM_DDR: SPI0 flash DDR mode control register + // Position of SPI_FMEM_DDR_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Pos = 0x0 + // Bit mask of SPI_FMEM_DDR_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Msk = 0x1 + // Bit SPI_FMEM_DDR_EN. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_EN = 0x1 + // Position of SPI_FMEM_VAR_DUMMY field. + SPI0_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Pos = 0x1 + // Bit mask of SPI_FMEM_VAR_DUMMY field. + SPI0_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Msk = 0x2 + // Bit SPI_FMEM_VAR_DUMMY. + SPI0_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY = 0x2 + // Position of SPI_FMEM_DDR_RDAT_SWP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Pos = 0x2 + // Bit mask of SPI_FMEM_DDR_RDAT_SWP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Msk = 0x4 + // Bit SPI_FMEM_DDR_RDAT_SWP. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP = 0x4 + // Position of SPI_FMEM_DDR_WDAT_SWP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Pos = 0x3 + // Bit mask of SPI_FMEM_DDR_WDAT_SWP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Msk = 0x8 + // Bit SPI_FMEM_DDR_WDAT_SWP. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP = 0x8 + // Position of SPI_FMEM_DDR_CMD_DIS field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Pos = 0x4 + // Bit mask of SPI_FMEM_DDR_CMD_DIS field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Msk = 0x10 + // Bit SPI_FMEM_DDR_CMD_DIS. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS = 0x10 + // Position of SPI_FMEM_OUTMINBYTELEN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Pos = 0x5 + // Bit mask of SPI_FMEM_OUTMINBYTELEN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Msk = 0xfe0 + // Position of SPI_FMEM_TX_DDR_MSK_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN_Pos = 0xc + // Bit mask of SPI_FMEM_TX_DDR_MSK_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN_Msk = 0x1000 + // Bit SPI_FMEM_TX_DDR_MSK_EN. + SPI0_SPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN = 0x1000 + // Position of SPI_FMEM_RX_DDR_MSK_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN_Pos = 0xd + // Bit mask of SPI_FMEM_RX_DDR_MSK_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN_Msk = 0x2000 + // Bit SPI_FMEM_RX_DDR_MSK_EN. + SPI0_SPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN = 0x2000 + // Position of SPI_FMEM_USR_DDR_DQS_THD field. + SPI0_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Pos = 0xe + // Bit mask of SPI_FMEM_USR_DDR_DQS_THD field. + SPI0_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Msk = 0x1fc000 + // Position of SPI_FMEM_DDR_DQS_LOOP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Pos = 0x15 + // Bit mask of SPI_FMEM_DDR_DQS_LOOP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Msk = 0x200000 + // Bit SPI_FMEM_DDR_DQS_LOOP. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP = 0x200000 + // Position of SPI_FMEM_CLK_DIFF_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Pos = 0x18 + // Bit mask of SPI_FMEM_CLK_DIFF_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Msk = 0x1000000 + // Bit SPI_FMEM_CLK_DIFF_EN. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN = 0x1000000 + // Position of SPI_FMEM_DQS_CA_IN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Pos = 0x1a + // Bit mask of SPI_FMEM_DQS_CA_IN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Msk = 0x4000000 + // Bit SPI_FMEM_DQS_CA_IN. + SPI0_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN = 0x4000000 + // Position of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b + // Bit mask of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000 + // Bit SPI_FMEM_HYPERBUS_DUMMY_2X. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X = 0x8000000 + // Position of SPI_FMEM_CLK_DIFF_INV field. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Pos = 0x1c + // Bit mask of SPI_FMEM_CLK_DIFF_INV field. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Msk = 0x10000000 + // Bit SPI_FMEM_CLK_DIFF_INV. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV = 0x10000000 + // Position of SPI_FMEM_OCTA_RAM_ADDR field. + SPI0_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Pos = 0x1d + // Bit mask of SPI_FMEM_OCTA_RAM_ADDR field. + SPI0_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Msk = 0x20000000 + // Bit SPI_FMEM_OCTA_RAM_ADDR. + SPI0_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR = 0x20000000 + // Position of SPI_FMEM_HYPERBUS_CA field. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Pos = 0x1e + // Bit mask of SPI_FMEM_HYPERBUS_CA field. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Msk = 0x40000000 + // Bit SPI_FMEM_HYPERBUS_CA. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA = 0x40000000 + + // SPI_SMEM_DDR: SPI0 external RAM DDR mode control register + // Position of EN field. + SPI0_SPI_SMEM_DDR_EN_Pos = 0x0 + // Bit mask of EN field. + SPI0_SPI_SMEM_DDR_EN_Msk = 0x1 + // Bit EN. + SPI0_SPI_SMEM_DDR_EN = 0x1 + // Position of SPI_SMEM_VAR_DUMMY field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY_Pos = 0x1 + // Bit mask of SPI_SMEM_VAR_DUMMY field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY_Msk = 0x2 + // Bit SPI_SMEM_VAR_DUMMY. + SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY = 0x2 + // Position of RDAT_SWP field. + SPI0_SPI_SMEM_DDR_RDAT_SWP_Pos = 0x2 + // Bit mask of RDAT_SWP field. + SPI0_SPI_SMEM_DDR_RDAT_SWP_Msk = 0x4 + // Bit RDAT_SWP. + SPI0_SPI_SMEM_DDR_RDAT_SWP = 0x4 + // Position of WDAT_SWP field. + SPI0_SPI_SMEM_DDR_WDAT_SWP_Pos = 0x3 + // Bit mask of WDAT_SWP field. + SPI0_SPI_SMEM_DDR_WDAT_SWP_Msk = 0x8 + // Bit WDAT_SWP. + SPI0_SPI_SMEM_DDR_WDAT_SWP = 0x8 + // Position of CMD_DIS field. + SPI0_SPI_SMEM_DDR_CMD_DIS_Pos = 0x4 + // Bit mask of CMD_DIS field. + SPI0_SPI_SMEM_DDR_CMD_DIS_Msk = 0x10 + // Bit CMD_DIS. + SPI0_SPI_SMEM_DDR_CMD_DIS = 0x10 + // Position of SPI_SMEM_OUTMINBYTELEN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN_Pos = 0x5 + // Bit mask of SPI_SMEM_OUTMINBYTELEN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN_Msk = 0xfe0 + // Position of SPI_SMEM_TX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN_Pos = 0xc + // Bit mask of SPI_SMEM_TX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN_Msk = 0x1000 + // Bit SPI_SMEM_TX_DDR_MSK_EN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN = 0x1000 + // Position of SPI_SMEM_RX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN_Pos = 0xd + // Bit mask of SPI_SMEM_RX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN_Msk = 0x2000 + // Bit SPI_SMEM_RX_DDR_MSK_EN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN = 0x2000 + // Position of SPI_SMEM_USR_DDR_DQS_THD field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD_Pos = 0xe + // Bit mask of SPI_SMEM_USR_DDR_DQS_THD field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD_Msk = 0x1fc000 + // Position of DQS_LOOP field. + SPI0_SPI_SMEM_DDR_DQS_LOOP_Pos = 0x15 + // Bit mask of DQS_LOOP field. + SPI0_SPI_SMEM_DDR_DQS_LOOP_Msk = 0x200000 + // Bit DQS_LOOP. + SPI0_SPI_SMEM_DDR_DQS_LOOP = 0x200000 + // Position of SPI_SMEM_CLK_DIFF_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN_Pos = 0x18 + // Bit mask of SPI_SMEM_CLK_DIFF_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN_Msk = 0x1000000 + // Bit SPI_SMEM_CLK_DIFF_EN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN = 0x1000000 + // Position of SPI_SMEM_DQS_CA_IN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN_Pos = 0x1a + // Bit mask of SPI_SMEM_DQS_CA_IN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN_Msk = 0x4000000 + // Bit SPI_SMEM_DQS_CA_IN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN = 0x4000000 + // Position of SPI_SMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b + // Bit mask of SPI_SMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000 + // Bit SPI_SMEM_HYPERBUS_DUMMY_2X. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X = 0x8000000 + // Position of SPI_SMEM_CLK_DIFF_INV field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV_Pos = 0x1c + // Bit mask of SPI_SMEM_CLK_DIFF_INV field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV_Msk = 0x10000000 + // Bit SPI_SMEM_CLK_DIFF_INV. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV = 0x10000000 + // Position of SPI_SMEM_OCTA_RAM_ADDR field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR_Pos = 0x1d + // Bit mask of SPI_SMEM_OCTA_RAM_ADDR field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR_Msk = 0x20000000 + // Bit SPI_SMEM_OCTA_RAM_ADDR. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR = 0x20000000 + // Position of SPI_SMEM_HYPERBUS_CA field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA_Pos = 0x1e + // Bit mask of SPI_SMEM_HYPERBUS_CA field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA_Msk = 0x40000000 + // Bit SPI_SMEM_HYPERBUS_CA. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA = 0x40000000 + + // SPI_FMEM_PMS0_ATTR: MSPI flash ACE section %s attribute register + // Position of SPI_FMEM_PMS_RD_ATTR field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_RD_ATTR_Pos = 0x0 + // Bit mask of SPI_FMEM_PMS_RD_ATTR field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_RD_ATTR_Msk = 0x1 + // Bit SPI_FMEM_PMS_RD_ATTR. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_RD_ATTR = 0x1 + // Position of SPI_FMEM_PMS_WR_ATTR field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_WR_ATTR_Pos = 0x1 + // Bit mask of SPI_FMEM_PMS_WR_ATTR field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_WR_ATTR_Msk = 0x2 + // Bit SPI_FMEM_PMS_WR_ATTR. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_WR_ATTR = 0x2 + // Position of SPI_FMEM_PMS_ECC field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_ECC_Pos = 0x2 + // Bit mask of SPI_FMEM_PMS_ECC field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_ECC_Msk = 0x4 + // Bit SPI_FMEM_PMS_ECC. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_ECC = 0x4 + + // SPI_FMEM_PMS0_ADDR: SPI1 flash ACE section %s start address register + // Position of S field. + SPI0_SPI_FMEM_PMS_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SPI0_SPI_FMEM_PMS_ADDR_S_Msk = 0x3ffffff + + // SPI_FMEM_PMS0_SIZE: SPI1 flash ACE section %s start address register + // Position of SPI_FMEM_PMS_SIZE field. + SPI0_SPI_FMEM_PMS_SIZE_SPI_FMEM_PMS_SIZE_Pos = 0x0 + // Bit mask of SPI_FMEM_PMS_SIZE field. + SPI0_SPI_FMEM_PMS_SIZE_SPI_FMEM_PMS_SIZE_Msk = 0x3fff + + // SPI_SMEM_PMS0_ATTR: SPI1 flash ACE section %s start address register + // Position of SPI_SMEM_PMS_RD_ATTR field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_RD_ATTR_Pos = 0x0 + // Bit mask of SPI_SMEM_PMS_RD_ATTR field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_RD_ATTR_Msk = 0x1 + // Bit SPI_SMEM_PMS_RD_ATTR. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_RD_ATTR = 0x1 + // Position of SPI_SMEM_PMS_WR_ATTR field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_WR_ATTR_Pos = 0x1 + // Bit mask of SPI_SMEM_PMS_WR_ATTR field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_WR_ATTR_Msk = 0x2 + // Bit SPI_SMEM_PMS_WR_ATTR. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_WR_ATTR = 0x2 + // Position of SPI_SMEM_PMS_ECC field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_ECC_Pos = 0x2 + // Bit mask of SPI_SMEM_PMS_ECC field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_ECC_Msk = 0x4 + // Bit SPI_SMEM_PMS_ECC. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_ECC = 0x4 + + // SPI_SMEM_PMS0_ADDR: SPI1 external RAM ACE section %s start address register + // Position of S field. + SPI0_SPI_SMEM_PMS_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SPI0_SPI_SMEM_PMS_ADDR_S_Msk = 0x3ffffff + + // SPI_SMEM_PMS0_SIZE: SPI1 external RAM ACE section %s start address register + // Position of SPI_SMEM_PMS_SIZE field. + SPI0_SPI_SMEM_PMS_SIZE_SPI_SMEM_PMS_SIZE_Pos = 0x0 + // Bit mask of SPI_SMEM_PMS_SIZE field. + SPI0_SPI_SMEM_PMS_SIZE_SPI_SMEM_PMS_SIZE_Msk = 0x3fff + + // SPI_MEM_PMS_REJECT: SPI1 access reject register + // Position of SPI_MEM_REJECT_ADDR field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_ADDR field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR_Msk = 0x3ffffff + // Position of SPI_MEM_PM_EN field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PM_EN_Pos = 0x1a + // Bit mask of SPI_MEM_PM_EN field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PM_EN_Msk = 0x4000000 + // Bit SPI_MEM_PM_EN. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PM_EN = 0x4000000 + // Position of SPI_MEM_PMS_LD field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD_Pos = 0x1c + // Bit mask of SPI_MEM_PMS_LD field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD_Msk = 0x10000000 + // Bit SPI_MEM_PMS_LD. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD = 0x10000000 + // Position of SPI_MEM_PMS_ST field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST_Pos = 0x1d + // Bit mask of SPI_MEM_PMS_ST field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST_Msk = 0x20000000 + // Bit SPI_MEM_PMS_ST. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST = 0x20000000 + // Position of SPI_MEM_PMS_MULTI_HIT field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT_Pos = 0x1e + // Bit mask of SPI_MEM_PMS_MULTI_HIT field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT_Msk = 0x40000000 + // Bit SPI_MEM_PMS_MULTI_HIT. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT = 0x40000000 + // Position of SPI_MEM_PMS_IVD field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD_Pos = 0x1f + // Bit mask of SPI_MEM_PMS_IVD field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD_Msk = 0x80000000 + // Bit SPI_MEM_PMS_IVD. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD = 0x80000000 + + // SPI_MEM_ECC_CTRL: MSPI ECC control register + // Position of SPI_FMEM_ECC_ERR_INT_NUM field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM_Pos = 0xb + // Bit mask of SPI_FMEM_ECC_ERR_INT_NUM field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM_Msk = 0x1f800 + // Position of SPI_FMEM_ECC_ERR_INT_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN_Pos = 0x11 + // Bit mask of SPI_FMEM_ECC_ERR_INT_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN_Msk = 0x20000 + // Bit SPI_FMEM_ECC_ERR_INT_EN. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN = 0x20000 + // Position of SPI_FMEM_PAGE_SIZE field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE_Pos = 0x12 + // Bit mask of SPI_FMEM_PAGE_SIZE field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE_Msk = 0xc0000 + // Position of SPI_FMEM_ECC_ADDR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN_Pos = 0x14 + // Bit mask of SPI_FMEM_ECC_ADDR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN_Msk = 0x100000 + // Bit SPI_FMEM_ECC_ADDR_EN. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN = 0x100000 + // Position of SPI_MEM_USR_ECC_ADDR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN_Pos = 0x15 + // Bit mask of SPI_MEM_USR_ECC_ADDR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN_Msk = 0x200000 + // Bit SPI_MEM_USR_ECC_ADDR_EN. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN = 0x200000 + // Position of SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_Pos = 0x18 + // Bit mask of SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_Msk = 0x1000000 + // Bit SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN = 0x1000000 + // Position of SPI_MEM_ECC_ERR_BITS field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS_Pos = 0x19 + // Bit mask of SPI_MEM_ECC_ERR_BITS field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS_Msk = 0xfe000000 + + // SPI_MEM_ECC_ERR_ADDR: MSPI ECC error address register + // Position of SPI_MEM_ECC_ERR_ADDR field. + SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_ECC_ERR_ADDR field. + SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_ADDR_Msk = 0x3ffffff + // Position of SPI_MEM_ECC_ERR_CNT field. + SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_CNT_Pos = 0x1a + // Bit mask of SPI_MEM_ECC_ERR_CNT field. + SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_CNT_Msk = 0xfc000000 + + // SPI_MEM_AXI_ERR_ADDR: SPI0 AXI request error address. + // Position of SPI_MEM_AXI_ERR_ADDR field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_AXI_ERR_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_AXI_ERR_ADDR field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_AXI_ERR_ADDR_Msk = 0x3ffffff + // Position of SPI_MEM_ALL_FIFO_EMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY_Pos = 0x1a + // Bit mask of SPI_MEM_ALL_FIFO_EMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY_Msk = 0x4000000 + // Bit SPI_MEM_ALL_FIFO_EMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY = 0x4000000 + // Position of SPI_RDATA_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY_Pos = 0x1b + // Bit mask of SPI_RDATA_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY_Msk = 0x8000000 + // Bit SPI_RDATA_AFIFO_REMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY = 0x8000000 + // Position of SPI_RADDR_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY_Pos = 0x1c + // Bit mask of SPI_RADDR_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY_Msk = 0x10000000 + // Bit SPI_RADDR_AFIFO_REMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY = 0x10000000 + // Position of SPI_WDATA_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY_Pos = 0x1d + // Bit mask of SPI_WDATA_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY_Msk = 0x20000000 + // Bit SPI_WDATA_AFIFO_REMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY = 0x20000000 + // Position of SPI_WBLEN_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY_Pos = 0x1e + // Bit mask of SPI_WBLEN_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY_Msk = 0x40000000 + // Bit SPI_WBLEN_AFIFO_REMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY = 0x40000000 + // Position of SPI_ALL_AXI_TRANS_AFIFO_EMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_Pos = 0x1f + // Bit mask of SPI_ALL_AXI_TRANS_AFIFO_EMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_Msk = 0x80000000 + // Bit SPI_ALL_AXI_TRANS_AFIFO_EMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY = 0x80000000 + + // SPI_SMEM_ECC_CTRL: MSPI ECC control register + // Position of SPI_SMEM_ECC_ERR_INT_EN field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN_Pos = 0x11 + // Bit mask of SPI_SMEM_ECC_ERR_INT_EN field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN_Msk = 0x20000 + // Bit SPI_SMEM_ECC_ERR_INT_EN. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN = 0x20000 + // Position of SPI_SMEM_PAGE_SIZE field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE_Pos = 0x12 + // Bit mask of SPI_SMEM_PAGE_SIZE field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE_Msk = 0xc0000 + // Position of SPI_SMEM_ECC_ADDR_EN field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN_Pos = 0x14 + // Bit mask of SPI_SMEM_ECC_ADDR_EN field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN_Msk = 0x100000 + // Bit SPI_SMEM_ECC_ADDR_EN. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN = 0x100000 + + // SPI_MEM_TIMING_CALI: SPI0 flash timing calibration register + // Position of SPI_MEM_TIMING_CLK_ENA field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA_Pos = 0x0 + // Bit mask of SPI_MEM_TIMING_CLK_ENA field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA_Msk = 0x1 + // Bit SPI_MEM_TIMING_CLK_ENA. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA = 0x1 + // Position of SPI_MEM_TIMING_CALI field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Pos = 0x1 + // Bit mask of SPI_MEM_TIMING_CALI field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Msk = 0x2 + // Bit SPI_MEM_TIMING_CALI. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI = 0x2 + // Position of SPI_MEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of SPI_MEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + // Position of SPI_MEM_DLL_TIMING_CALI field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI_Pos = 0x5 + // Bit mask of SPI_MEM_DLL_TIMING_CALI field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI_Msk = 0x20 + // Bit SPI_MEM_DLL_TIMING_CALI. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI = 0x20 + // Position of UPDATE field. + SPI0_SPI_MEM_TIMING_CALI_UPDATE_Pos = 0x6 + // Bit mask of UPDATE field. + SPI0_SPI_MEM_TIMING_CALI_UPDATE_Msk = 0x40 + // Bit UPDATE. + SPI0_SPI_MEM_TIMING_CALI_UPDATE = 0x40 + + // SPI_MEM_DIN_MODE: MSPI flash input timing delay mode control register + // Position of SPI_MEM_DIN0_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_DIN0_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE_Msk = 0x7 + // Position of SPI_MEM_DIN1_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE_Pos = 0x3 + // Bit mask of SPI_MEM_DIN1_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE_Msk = 0x38 + // Position of SPI_MEM_DIN2_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE_Pos = 0x6 + // Bit mask of SPI_MEM_DIN2_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE_Msk = 0x1c0 + // Position of SPI_MEM_DIN3_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE_Pos = 0x9 + // Bit mask of SPI_MEM_DIN3_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE_Msk = 0xe00 + // Position of SPI_MEM_DIN4_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE_Pos = 0xc + // Bit mask of SPI_MEM_DIN4_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE_Msk = 0x7000 + // Position of SPI_MEM_DIN5_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE_Pos = 0xf + // Bit mask of SPI_MEM_DIN5_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE_Msk = 0x38000 + // Position of SPI_MEM_DIN6_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE_Pos = 0x12 + // Bit mask of SPI_MEM_DIN6_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE_Msk = 0x1c0000 + // Position of SPI_MEM_DIN7_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE_Pos = 0x15 + // Bit mask of SPI_MEM_DIN7_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE_Msk = 0xe00000 + // Position of SPI_MEM_DINS_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE_Pos = 0x18 + // Bit mask of SPI_MEM_DINS_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE_Msk = 0x7000000 + + // SPI_MEM_DIN_NUM: MSPI flash input timing delay number control register + // Position of SPI_MEM_DIN0_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM_Pos = 0x0 + // Bit mask of SPI_MEM_DIN0_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM_Msk = 0x3 + // Position of SPI_MEM_DIN1_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM_Pos = 0x2 + // Bit mask of SPI_MEM_DIN1_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM_Msk = 0xc + // Position of SPI_MEM_DIN2_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM_Pos = 0x4 + // Bit mask of SPI_MEM_DIN2_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM_Msk = 0x30 + // Position of SPI_MEM_DIN3_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM_Pos = 0x6 + // Bit mask of SPI_MEM_DIN3_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM_Msk = 0xc0 + // Position of SPI_MEM_DIN4_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM_Pos = 0x8 + // Bit mask of SPI_MEM_DIN4_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM_Msk = 0x300 + // Position of SPI_MEM_DIN5_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM_Pos = 0xa + // Bit mask of SPI_MEM_DIN5_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM_Msk = 0xc00 + // Position of SPI_MEM_DIN6_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM_Pos = 0xc + // Bit mask of SPI_MEM_DIN6_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM_Msk = 0x3000 + // Position of SPI_MEM_DIN7_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM_Pos = 0xe + // Bit mask of SPI_MEM_DIN7_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM_Msk = 0xc000 + // Position of SPI_MEM_DINS_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM_Pos = 0x10 + // Bit mask of SPI_MEM_DINS_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM_Msk = 0x30000 + + // SPI_MEM_DOUT_MODE: MSPI flash output timing adjustment control register + // Position of SPI_MEM_DOUT0_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_DOUT0_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE_Msk = 0x1 + // Bit SPI_MEM_DOUT0_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE = 0x1 + // Position of SPI_MEM_DOUT1_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE_Pos = 0x1 + // Bit mask of SPI_MEM_DOUT1_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE_Msk = 0x2 + // Bit SPI_MEM_DOUT1_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE = 0x2 + // Position of SPI_MEM_DOUT2_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE_Pos = 0x2 + // Bit mask of SPI_MEM_DOUT2_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE_Msk = 0x4 + // Bit SPI_MEM_DOUT2_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE = 0x4 + // Position of SPI_MEM_DOUT3_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE_Pos = 0x3 + // Bit mask of SPI_MEM_DOUT3_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE_Msk = 0x8 + // Bit SPI_MEM_DOUT3_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE = 0x8 + // Position of SPI_MEM_DOUT4_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE_Pos = 0x4 + // Bit mask of SPI_MEM_DOUT4_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE_Msk = 0x10 + // Bit SPI_MEM_DOUT4_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE = 0x10 + // Position of SPI_MEM_DOUT5_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE_Pos = 0x5 + // Bit mask of SPI_MEM_DOUT5_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE_Msk = 0x20 + // Bit SPI_MEM_DOUT5_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE = 0x20 + // Position of SPI_MEM_DOUT6_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE_Pos = 0x6 + // Bit mask of SPI_MEM_DOUT6_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE_Msk = 0x40 + // Bit SPI_MEM_DOUT6_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE = 0x40 + // Position of SPI_MEM_DOUT7_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE_Pos = 0x7 + // Bit mask of SPI_MEM_DOUT7_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE_Msk = 0x80 + // Bit SPI_MEM_DOUT7_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE = 0x80 + // Position of SPI_MEM_DOUTS_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE_Pos = 0x8 + // Bit mask of SPI_MEM_DOUTS_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE_Msk = 0x100 + // Bit SPI_MEM_DOUTS_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE = 0x100 + + // SPI_SMEM_TIMING_CALI: MSPI external RAM timing calibration register + // Position of SPI_SMEM_TIMING_CLK_ENA field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA_Pos = 0x0 + // Bit mask of SPI_SMEM_TIMING_CLK_ENA field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA_Msk = 0x1 + // Bit SPI_SMEM_TIMING_CLK_ENA. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA = 0x1 + // Position of SPI_SMEM_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI_Pos = 0x1 + // Bit mask of SPI_SMEM_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI_Msk = 0x2 + // Bit SPI_SMEM_TIMING_CALI. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI = 0x2 + // Position of SPI_SMEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of SPI_SMEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + // Position of SPI_SMEM_DLL_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI_Pos = 0x5 + // Bit mask of SPI_SMEM_DLL_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI_Msk = 0x20 + // Bit SPI_SMEM_DLL_TIMING_CALI. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI = 0x20 + + // SPI_SMEM_DIN_MODE: MSPI external RAM input timing delay mode control register + // Position of SPI_SMEM_DIN0_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE_Pos = 0x0 + // Bit mask of SPI_SMEM_DIN0_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE_Msk = 0x7 + // Position of SPI_SMEM_DIN1_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE_Pos = 0x3 + // Bit mask of SPI_SMEM_DIN1_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE_Msk = 0x38 + // Position of SPI_SMEM_DIN2_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE_Pos = 0x6 + // Bit mask of SPI_SMEM_DIN2_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE_Msk = 0x1c0 + // Position of SPI_SMEM_DIN3_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE_Pos = 0x9 + // Bit mask of SPI_SMEM_DIN3_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE_Msk = 0xe00 + // Position of SPI_SMEM_DIN4_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE_Pos = 0xc + // Bit mask of SPI_SMEM_DIN4_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE_Msk = 0x7000 + // Position of SPI_SMEM_DIN5_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE_Pos = 0xf + // Bit mask of SPI_SMEM_DIN5_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE_Msk = 0x38000 + // Position of SPI_SMEM_DIN6_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE_Pos = 0x12 + // Bit mask of SPI_SMEM_DIN6_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE_Msk = 0x1c0000 + // Position of SPI_SMEM_DIN7_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE_Pos = 0x15 + // Bit mask of SPI_SMEM_DIN7_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE_Msk = 0xe00000 + // Position of SPI_SMEM_DINS_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE_Pos = 0x18 + // Bit mask of SPI_SMEM_DINS_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE_Msk = 0x7000000 + + // SPI_SMEM_DIN_NUM: MSPI external RAM input timing delay number control register + // Position of SPI_SMEM_DIN0_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM_Pos = 0x0 + // Bit mask of SPI_SMEM_DIN0_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM_Msk = 0x3 + // Position of SPI_SMEM_DIN1_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM_Pos = 0x2 + // Bit mask of SPI_SMEM_DIN1_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM_Msk = 0xc + // Position of SPI_SMEM_DIN2_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM_Pos = 0x4 + // Bit mask of SPI_SMEM_DIN2_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM_Msk = 0x30 + // Position of SPI_SMEM_DIN3_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM_Pos = 0x6 + // Bit mask of SPI_SMEM_DIN3_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM_Msk = 0xc0 + // Position of SPI_SMEM_DIN4_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM_Pos = 0x8 + // Bit mask of SPI_SMEM_DIN4_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM_Msk = 0x300 + // Position of SPI_SMEM_DIN5_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM_Pos = 0xa + // Bit mask of SPI_SMEM_DIN5_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM_Msk = 0xc00 + // Position of SPI_SMEM_DIN6_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM_Pos = 0xc + // Bit mask of SPI_SMEM_DIN6_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM_Msk = 0x3000 + // Position of SPI_SMEM_DIN7_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM_Pos = 0xe + // Bit mask of SPI_SMEM_DIN7_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM_Msk = 0xc000 + // Position of SPI_SMEM_DINS_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM_Pos = 0x10 + // Bit mask of SPI_SMEM_DINS_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM_Msk = 0x30000 + + // SPI_SMEM_DOUT_MODE: MSPI external RAM output timing adjustment control register + // Position of SPI_SMEM_DOUT0_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE_Pos = 0x0 + // Bit mask of SPI_SMEM_DOUT0_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE_Msk = 0x1 + // Bit SPI_SMEM_DOUT0_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE = 0x1 + // Position of SPI_SMEM_DOUT1_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE_Pos = 0x1 + // Bit mask of SPI_SMEM_DOUT1_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE_Msk = 0x2 + // Bit SPI_SMEM_DOUT1_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE = 0x2 + // Position of SPI_SMEM_DOUT2_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE_Pos = 0x2 + // Bit mask of SPI_SMEM_DOUT2_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE_Msk = 0x4 + // Bit SPI_SMEM_DOUT2_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE = 0x4 + // Position of SPI_SMEM_DOUT3_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE_Pos = 0x3 + // Bit mask of SPI_SMEM_DOUT3_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE_Msk = 0x8 + // Bit SPI_SMEM_DOUT3_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE = 0x8 + // Position of SPI_SMEM_DOUT4_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE_Pos = 0x4 + // Bit mask of SPI_SMEM_DOUT4_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE_Msk = 0x10 + // Bit SPI_SMEM_DOUT4_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE = 0x10 + // Position of SPI_SMEM_DOUT5_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE_Pos = 0x5 + // Bit mask of SPI_SMEM_DOUT5_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE_Msk = 0x20 + // Bit SPI_SMEM_DOUT5_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE = 0x20 + // Position of SPI_SMEM_DOUT6_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE_Pos = 0x6 + // Bit mask of SPI_SMEM_DOUT6_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE_Msk = 0x40 + // Bit SPI_SMEM_DOUT6_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE = 0x40 + // Position of SPI_SMEM_DOUT7_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE_Pos = 0x7 + // Bit mask of SPI_SMEM_DOUT7_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE_Msk = 0x80 + // Bit SPI_SMEM_DOUT7_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE = 0x80 + // Position of SPI_SMEM_DOUTS_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE_Pos = 0x8 + // Bit mask of SPI_SMEM_DOUTS_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE_Msk = 0x100 + // Bit SPI_SMEM_DOUTS_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE = 0x100 + + // SPI_SMEM_AC: MSPI external RAM ECC and SPI CS timing control register + // Position of SPI_SMEM_CS_SETUP field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_Pos = 0x0 + // Bit mask of SPI_SMEM_CS_SETUP field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_Msk = 0x1 + // Bit SPI_SMEM_CS_SETUP. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP = 0x1 + // Position of SPI_SMEM_CS_HOLD field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_Pos = 0x1 + // Bit mask of SPI_SMEM_CS_HOLD field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_Msk = 0x2 + // Bit SPI_SMEM_CS_HOLD. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD = 0x2 + // Position of SPI_SMEM_CS_SETUP_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME_Pos = 0x2 + // Bit mask of SPI_SMEM_CS_SETUP_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME_Msk = 0x7c + // Position of SPI_SMEM_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME_Pos = 0x7 + // Bit mask of SPI_SMEM_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME_Msk = 0xf80 + // Position of SPI_SMEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME_Pos = 0xc + // Bit mask of SPI_SMEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME_Msk = 0x7000 + // Position of SPI_SMEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER_Pos = 0xf + // Bit mask of SPI_SMEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER_Msk = 0x8000 + // Bit SPI_SMEM_ECC_SKIP_PAGE_CORNER. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER = 0x8000 + // Position of SPI_SMEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN_Pos = 0x10 + // Bit mask of SPI_SMEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN_Msk = 0x10000 + // Bit SPI_SMEM_ECC_16TO18_BYTE_EN. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN = 0x10000 + // Position of SPI_SMEM_CS_HOLD_DELAY field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY_Pos = 0x19 + // Bit mask of SPI_SMEM_CS_HOLD_DELAY field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY_Msk = 0x7e000000 + // Position of SPI_SMEM_SPLIT_TRANS_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN_Pos = 0x1f + // Bit mask of SPI_SMEM_SPLIT_TRANS_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN_Msk = 0x80000000 + // Bit SPI_SMEM_SPLIT_TRANS_EN. + SPI0_SPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN = 0x80000000 + + // SPI_MEM_CLOCK_GATE: SPI0 clock gate register + // Position of SPI_CLK_EN field. + SPI0_SPI_MEM_CLOCK_GATE_SPI_CLK_EN_Pos = 0x0 + // Bit mask of SPI_CLK_EN field. + SPI0_SPI_MEM_CLOCK_GATE_SPI_CLK_EN_Msk = 0x1 + // Bit SPI_CLK_EN. + SPI0_SPI_MEM_CLOCK_GATE_SPI_CLK_EN = 0x1 + + // SPI_MEM_XTS_PLAIN_BASE: The base address of the memory that stores plaintext in Manual Encryption + // Position of SPI_XTS_PLAIN field. + SPI0_SPI_MEM_XTS_PLAIN_BASE_SPI_XTS_PLAIN_Pos = 0x0 + // Bit mask of SPI_XTS_PLAIN field. + SPI0_SPI_MEM_XTS_PLAIN_BASE_SPI_XTS_PLAIN_Msk = 0xffffffff + + // SPI_MEM_XTS_LINESIZE: Manual Encryption Line-Size register + // Position of SPI_XTS_LINESIZE field. + SPI0_SPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE_Pos = 0x0 + // Bit mask of SPI_XTS_LINESIZE field. + SPI0_SPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE_Msk = 0x3 + + // SPI_MEM_XTS_DESTINATION: Manual Encryption destination register + // Position of SPI_XTS_DESTINATION field. + SPI0_SPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION_Pos = 0x0 + // Bit mask of SPI_XTS_DESTINATION field. + SPI0_SPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION_Msk = 0x1 + // Bit SPI_XTS_DESTINATION. + SPI0_SPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION = 0x1 + + // SPI_MEM_XTS_PHYSICAL_ADDRESS: Manual Encryption physical address register + // Position of SPI_XTS_PHYSICAL_ADDRESS field. + SPI0_SPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS_Pos = 0x0 + // Bit mask of SPI_XTS_PHYSICAL_ADDRESS field. + SPI0_SPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS_Msk = 0x3ffffff + + // SPI_MEM_XTS_TRIGGER: Manual Encryption physical address register + // Position of SPI_XTS_TRIGGER field. + SPI0_SPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER_Pos = 0x0 + // Bit mask of SPI_XTS_TRIGGER field. + SPI0_SPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER_Msk = 0x1 + // Bit SPI_XTS_TRIGGER. + SPI0_SPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER = 0x1 + + // SPI_MEM_XTS_RELEASE: Manual Encryption physical address register + // Position of SPI_XTS_RELEASE field. + SPI0_SPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE_Pos = 0x0 + // Bit mask of SPI_XTS_RELEASE field. + SPI0_SPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE_Msk = 0x1 + // Bit SPI_XTS_RELEASE. + SPI0_SPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE = 0x1 + + // SPI_MEM_XTS_DESTROY: Manual Encryption physical address register + // Position of SPI_XTS_DESTROY field. + SPI0_SPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY_Pos = 0x0 + // Bit mask of SPI_XTS_DESTROY field. + SPI0_SPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY_Msk = 0x1 + // Bit SPI_XTS_DESTROY. + SPI0_SPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY = 0x1 + + // SPI_MEM_XTS_STATE: Manual Encryption physical address register + // Position of SPI_XTS_STATE field. + SPI0_SPI_MEM_XTS_STATE_SPI_XTS_STATE_Pos = 0x0 + // Bit mask of SPI_XTS_STATE field. + SPI0_SPI_MEM_XTS_STATE_SPI_XTS_STATE_Msk = 0x3 + + // SPI_MEM_XTS_DATE: Manual Encryption version register + // Position of SPI_XTS_DATE field. + SPI0_SPI_MEM_XTS_DATE_SPI_XTS_DATE_Pos = 0x0 + // Bit mask of SPI_XTS_DATE field. + SPI0_SPI_MEM_XTS_DATE_SPI_XTS_DATE_Msk = 0x3fffffff + + // SPI_MEM_MMU_ITEM_CONTENT: MSPI-MMU item content register + // Position of SPI_MMU_ITEM_CONTENT field. + SPI0_SPI_MEM_MMU_ITEM_CONTENT_SPI_MMU_ITEM_CONTENT_Pos = 0x0 + // Bit mask of SPI_MMU_ITEM_CONTENT field. + SPI0_SPI_MEM_MMU_ITEM_CONTENT_SPI_MMU_ITEM_CONTENT_Msk = 0xffffffff + + // SPI_MEM_MMU_ITEM_INDEX: MSPI-MMU item index register + // Position of SPI_MMU_ITEM_INDEX field. + SPI0_SPI_MEM_MMU_ITEM_INDEX_SPI_MMU_ITEM_INDEX_Pos = 0x0 + // Bit mask of SPI_MMU_ITEM_INDEX field. + SPI0_SPI_MEM_MMU_ITEM_INDEX_SPI_MMU_ITEM_INDEX_Msk = 0xffffffff + + // SPI_MEM_MMU_POWER_CTRL: MSPI MMU power control register + // Position of SPI_MMU_MEM_FORCE_ON field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of SPI_MMU_MEM_FORCE_ON field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON_Msk = 0x1 + // Bit SPI_MMU_MEM_FORCE_ON. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON = 0x1 + // Position of SPI_MMU_MEM_FORCE_PD field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of SPI_MMU_MEM_FORCE_PD field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD_Msk = 0x2 + // Bit SPI_MMU_MEM_FORCE_PD. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD = 0x2 + // Position of SPI_MMU_MEM_FORCE_PU field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of SPI_MMU_MEM_FORCE_PU field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU_Msk = 0x4 + // Bit SPI_MMU_MEM_FORCE_PU. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU = 0x4 + // Position of SPI_MMU_PAGE_SIZE field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_PAGE_SIZE_Pos = 0x3 + // Bit mask of SPI_MMU_PAGE_SIZE field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_PAGE_SIZE_Msk = 0x18 + // Position of SPI_MEM_AUX_CTRL field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL_Pos = 0x10 + // Bit mask of SPI_MEM_AUX_CTRL field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL_Msk = 0x3fff0000 + // Position of SPI_MEM_RDN_ENA field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA_Pos = 0x1e + // Bit mask of SPI_MEM_RDN_ENA field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA_Msk = 0x40000000 + // Bit SPI_MEM_RDN_ENA. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA = 0x40000000 + // Position of SPI_MEM_RDN_RESULT field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT_Pos = 0x1f + // Bit mask of SPI_MEM_RDN_RESULT field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT_Msk = 0x80000000 + // Bit SPI_MEM_RDN_RESULT. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT = 0x80000000 + + // SPI_MEM_DPA_CTRL: SPI memory cryption DPA register + // Position of SPI_CRYPT_SECURITY_LEVEL field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL_Pos = 0x0 + // Bit mask of SPI_CRYPT_SECURITY_LEVEL field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL_Msk = 0x7 + // Position of SPI_CRYPT_CALC_D_DPA_EN field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN_Pos = 0x3 + // Bit mask of SPI_CRYPT_CALC_D_DPA_EN field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN_Msk = 0x8 + // Bit SPI_CRYPT_CALC_D_DPA_EN. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN = 0x8 + // Position of SPI_CRYPT_DPA_SELECT_REGISTER field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER_Pos = 0x4 + // Bit mask of SPI_CRYPT_DPA_SELECT_REGISTER field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER_Msk = 0x10 + // Bit SPI_CRYPT_DPA_SELECT_REGISTER. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER = 0x10 + + // SPI_MEM_REGISTERRND_ECO_HIGH: MSPI ECO high register + // Position of SPI_MEM_REGISTERRND_ECO_HIGH field. + SPI0_SPI_MEM_REGISTERRND_ECO_HIGH_SPI_MEM_REGISTERRND_ECO_HIGH_Pos = 0x0 + // Bit mask of SPI_MEM_REGISTERRND_ECO_HIGH field. + SPI0_SPI_MEM_REGISTERRND_ECO_HIGH_SPI_MEM_REGISTERRND_ECO_HIGH_Msk = 0xffffffff + + // SPI_MEM_REGISTERRND_ECO_LOW: MSPI ECO low register + // Position of SPI_MEM_REGISTERRND_ECO_LOW field. + SPI0_SPI_MEM_REGISTERRND_ECO_LOW_SPI_MEM_REGISTERRND_ECO_LOW_Pos = 0x0 + // Bit mask of SPI_MEM_REGISTERRND_ECO_LOW field. + SPI0_SPI_MEM_REGISTERRND_ECO_LOW_SPI_MEM_REGISTERRND_ECO_LOW_Msk = 0xffffffff + + // SPI_MEM_DATE: SPI0 version control register + // Position of SPI_MEM_DATE field. + SPI0_SPI_MEM_DATE_SPI_MEM_DATE_Pos = 0x0 + // Bit mask of SPI_MEM_DATE field. + SPI0_SPI_MEM_DATE_SPI_MEM_DATE_Msk = 0xfffffff +) + +// Constants for SPI1: SPI (Serial Peripheral Interface) Controller 1 +const ( + // SPI_MEM_CMD: SPI1 memory command register + // Position of SPI_MEM_MST_ST field. + SPI1_SPI_MEM_CMD_SPI_MEM_MST_ST_Pos = 0x0 + // Bit mask of SPI_MEM_MST_ST field. + SPI1_SPI_MEM_CMD_SPI_MEM_MST_ST_Msk = 0xf + // Position of SPI_MEM_SLV_ST field. + SPI1_SPI_MEM_CMD_SPI_MEM_SLV_ST_Pos = 0x4 + // Bit mask of SPI_MEM_SLV_ST field. + SPI1_SPI_MEM_CMD_SPI_MEM_SLV_ST_Msk = 0xf0 + // Position of SPI_MEM_FLASH_PE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PE_Pos = 0x11 + // Bit mask of SPI_MEM_FLASH_PE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PE_Msk = 0x20000 + // Bit SPI_MEM_FLASH_PE. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PE = 0x20000 + // Position of SPI_MEM_USR field. + SPI1_SPI_MEM_CMD_SPI_MEM_USR_Pos = 0x12 + // Bit mask of SPI_MEM_USR field. + SPI1_SPI_MEM_CMD_SPI_MEM_USR_Msk = 0x40000 + // Bit SPI_MEM_USR. + SPI1_SPI_MEM_CMD_SPI_MEM_USR = 0x40000 + // Position of SPI_MEM_FLASH_HPM field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_HPM_Pos = 0x13 + // Bit mask of SPI_MEM_FLASH_HPM field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_HPM_Msk = 0x80000 + // Bit SPI_MEM_FLASH_HPM. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_HPM = 0x80000 + // Position of SPI_MEM_FLASH_RES field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RES_Pos = 0x14 + // Bit mask of SPI_MEM_FLASH_RES field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RES_Msk = 0x100000 + // Bit SPI_MEM_FLASH_RES. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RES = 0x100000 + // Position of SPI_MEM_FLASH_DP field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_DP_Pos = 0x15 + // Bit mask of SPI_MEM_FLASH_DP field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_DP_Msk = 0x200000 + // Bit SPI_MEM_FLASH_DP. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_DP = 0x200000 + // Position of SPI_MEM_FLASH_CE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_CE_Pos = 0x16 + // Bit mask of SPI_MEM_FLASH_CE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_CE_Msk = 0x400000 + // Bit SPI_MEM_FLASH_CE. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_CE = 0x400000 + // Position of SPI_MEM_FLASH_BE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_BE_Pos = 0x17 + // Bit mask of SPI_MEM_FLASH_BE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_BE_Msk = 0x800000 + // Bit SPI_MEM_FLASH_BE. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_BE = 0x800000 + // Position of SPI_MEM_FLASH_SE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_SE_Pos = 0x18 + // Bit mask of SPI_MEM_FLASH_SE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_SE_Msk = 0x1000000 + // Bit SPI_MEM_FLASH_SE. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_SE = 0x1000000 + // Position of SPI_MEM_FLASH_PP field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PP_Pos = 0x19 + // Bit mask of SPI_MEM_FLASH_PP field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PP_Msk = 0x2000000 + // Bit SPI_MEM_FLASH_PP. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PP = 0x2000000 + // Position of SPI_MEM_FLASH_WRSR field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRSR_Pos = 0x1a + // Bit mask of SPI_MEM_FLASH_WRSR field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRSR_Msk = 0x4000000 + // Bit SPI_MEM_FLASH_WRSR. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRSR = 0x4000000 + // Position of SPI_MEM_FLASH_RDSR field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDSR_Pos = 0x1b + // Bit mask of SPI_MEM_FLASH_RDSR field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDSR_Msk = 0x8000000 + // Bit SPI_MEM_FLASH_RDSR. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDSR = 0x8000000 + // Position of SPI_MEM_FLASH_RDID field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDID_Pos = 0x1c + // Bit mask of SPI_MEM_FLASH_RDID field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDID_Msk = 0x10000000 + // Bit SPI_MEM_FLASH_RDID. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDID = 0x10000000 + // Position of SPI_MEM_FLASH_WRDI field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRDI_Pos = 0x1d + // Bit mask of SPI_MEM_FLASH_WRDI field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRDI_Msk = 0x20000000 + // Bit SPI_MEM_FLASH_WRDI. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRDI = 0x20000000 + // Position of SPI_MEM_FLASH_WREN field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WREN_Pos = 0x1e + // Bit mask of SPI_MEM_FLASH_WREN field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WREN_Msk = 0x40000000 + // Bit SPI_MEM_FLASH_WREN. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WREN = 0x40000000 + // Position of SPI_MEM_FLASH_READ field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_READ_Pos = 0x1f + // Bit mask of SPI_MEM_FLASH_READ field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_READ_Msk = 0x80000000 + // Bit SPI_MEM_FLASH_READ. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_READ = 0x80000000 + + // SPI_MEM_ADDR: SPI1 address register + // Position of SPI_MEM_USR_ADDR_VALUE field. + SPI1_SPI_MEM_ADDR_SPI_MEM_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_USR_ADDR_VALUE field. + SPI1_SPI_MEM_ADDR_SPI_MEM_USR_ADDR_VALUE_Msk = 0xffffffff + + // SPI_MEM_CTRL: SPI1 control register. + // Position of SPI_MEM_FDUMMY_RIN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Pos = 0x2 + // Bit mask of SPI_MEM_FDUMMY_RIN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Msk = 0x4 + // Bit SPI_MEM_FDUMMY_RIN. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN = 0x4 + // Position of SPI_MEM_FDUMMY_WOUT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Pos = 0x3 + // Bit mask of SPI_MEM_FDUMMY_WOUT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Msk = 0x8 + // Bit SPI_MEM_FDUMMY_WOUT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT = 0x8 + // Position of SPI_MEM_FDOUT_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Pos = 0x4 + // Bit mask of SPI_MEM_FDOUT_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Msk = 0x10 + // Bit SPI_MEM_FDOUT_OCT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT = 0x10 + // Position of SPI_MEM_FDIN_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Pos = 0x5 + // Bit mask of SPI_MEM_FDIN_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Msk = 0x20 + // Bit SPI_MEM_FDIN_OCT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT = 0x20 + // Position of SPI_MEM_FADDR_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Pos = 0x6 + // Bit mask of SPI_MEM_FADDR_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Msk = 0x40 + // Bit SPI_MEM_FADDR_OCT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT = 0x40 + // Position of SPI_MEM_FCMD_QUAD field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Pos = 0x8 + // Bit mask of SPI_MEM_FCMD_QUAD field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Msk = 0x100 + // Bit SPI_MEM_FCMD_QUAD. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD = 0x100 + // Position of SPI_MEM_FCMD_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Pos = 0x9 + // Bit mask of SPI_MEM_FCMD_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Msk = 0x200 + // Bit SPI_MEM_FCMD_OCT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT = 0x200 + // Position of SPI_MEM_FCS_CRC_EN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN_Pos = 0xa + // Bit mask of SPI_MEM_FCS_CRC_EN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN_Msk = 0x400 + // Bit SPI_MEM_FCS_CRC_EN. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN = 0x400 + // Position of SPI_MEM_TX_CRC_EN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_TX_CRC_EN_Pos = 0xb + // Bit mask of SPI_MEM_TX_CRC_EN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_TX_CRC_EN_Msk = 0x800 + // Bit SPI_MEM_TX_CRC_EN. + SPI1_SPI_MEM_CTRL_SPI_MEM_TX_CRC_EN = 0x800 + // Position of SPI_MEM_FASTRD_MODE field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Pos = 0xd + // Bit mask of SPI_MEM_FASTRD_MODE field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Msk = 0x2000 + // Bit SPI_MEM_FASTRD_MODE. + SPI1_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE = 0x2000 + // Position of SPI_MEM_FREAD_DUAL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Pos = 0xe + // Bit mask of SPI_MEM_FREAD_DUAL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Msk = 0x4000 + // Bit SPI_MEM_FREAD_DUAL. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL = 0x4000 + // Position of SPI_MEM_RESANDRES field. + SPI1_SPI_MEM_CTRL_SPI_MEM_RESANDRES_Pos = 0xf + // Bit mask of SPI_MEM_RESANDRES field. + SPI1_SPI_MEM_CTRL_SPI_MEM_RESANDRES_Msk = 0x8000 + // Bit SPI_MEM_RESANDRES. + SPI1_SPI_MEM_CTRL_SPI_MEM_RESANDRES = 0x8000 + // Position of SPI_MEM_Q_POL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_Q_POL_Pos = 0x12 + // Bit mask of SPI_MEM_Q_POL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_Q_POL_Msk = 0x40000 + // Bit SPI_MEM_Q_POL. + SPI1_SPI_MEM_CTRL_SPI_MEM_Q_POL = 0x40000 + // Position of SPI_MEM_D_POL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_D_POL_Pos = 0x13 + // Bit mask of SPI_MEM_D_POL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_D_POL_Msk = 0x80000 + // Bit SPI_MEM_D_POL. + SPI1_SPI_MEM_CTRL_SPI_MEM_D_POL = 0x80000 + // Position of SPI_MEM_FREAD_QUAD field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Pos = 0x14 + // Bit mask of SPI_MEM_FREAD_QUAD field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Msk = 0x100000 + // Bit SPI_MEM_FREAD_QUAD. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD = 0x100000 + // Position of SPI_MEM_WP field. + SPI1_SPI_MEM_CTRL_SPI_MEM_WP_Pos = 0x15 + // Bit mask of SPI_MEM_WP field. + SPI1_SPI_MEM_CTRL_SPI_MEM_WP_Msk = 0x200000 + // Bit SPI_MEM_WP. + SPI1_SPI_MEM_CTRL_SPI_MEM_WP = 0x200000 + // Position of SPI_MEM_WRSR_2B field. + SPI1_SPI_MEM_CTRL_SPI_MEM_WRSR_2B_Pos = 0x16 + // Bit mask of SPI_MEM_WRSR_2B field. + SPI1_SPI_MEM_CTRL_SPI_MEM_WRSR_2B_Msk = 0x400000 + // Bit SPI_MEM_WRSR_2B. + SPI1_SPI_MEM_CTRL_SPI_MEM_WRSR_2B = 0x400000 + // Position of SPI_MEM_FREAD_DIO field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Pos = 0x17 + // Bit mask of SPI_MEM_FREAD_DIO field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Msk = 0x800000 + // Bit SPI_MEM_FREAD_DIO. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO = 0x800000 + // Position of SPI_MEM_FREAD_QIO field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Pos = 0x18 + // Bit mask of SPI_MEM_FREAD_QIO field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Msk = 0x1000000 + // Bit SPI_MEM_FREAD_QIO. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO = 0x1000000 + + // SPI_MEM_CTRL1: SPI1 control1 register. + // Position of SPI_MEM_CLK_MODE field. + SPI1_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_CLK_MODE field. + SPI1_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Msk = 0x3 + // Position of SPI_MEM_CS_HOLD_DLY_RES field. + SPI1_SPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES_Pos = 0x2 + // Bit mask of SPI_MEM_CS_HOLD_DLY_RES field. + SPI1_SPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES_Msk = 0xffc + + // SPI_MEM_CTRL2: SPI1 control2 register. + // Position of SPI_MEM_SYNC_RESET field. + SPI1_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Pos = 0x1f + // Bit mask of SPI_MEM_SYNC_RESET field. + SPI1_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Msk = 0x80000000 + // Bit SPI_MEM_SYNC_RESET. + SPI1_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET = 0x80000000 + + // SPI_MEM_CLOCK: SPI1 clock division control register. + // Position of SPI_MEM_CLKCNT_L field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Pos = 0x0 + // Bit mask of SPI_MEM_CLKCNT_L field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Msk = 0xff + // Position of SPI_MEM_CLKCNT_H field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Pos = 0x8 + // Bit mask of SPI_MEM_CLKCNT_H field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Msk = 0xff00 + // Position of SPI_MEM_CLKCNT_N field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Pos = 0x10 + // Bit mask of SPI_MEM_CLKCNT_N field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Msk = 0xff0000 + // Position of SPI_MEM_CLK_EQU_SYSCLK field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of SPI_MEM_CLK_EQU_SYSCLK field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit SPI_MEM_CLK_EQU_SYSCLK. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK = 0x80000000 + + // SPI_MEM_USER: SPI1 user register. + // Position of SPI_MEM_CK_OUT_EDGE field. + SPI1_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of SPI_MEM_CK_OUT_EDGE field. + SPI1_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Msk = 0x200 + // Bit SPI_MEM_CK_OUT_EDGE. + SPI1_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE = 0x200 + // Position of SPI_MEM_FWRITE_DUAL field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DUAL_Pos = 0xc + // Bit mask of SPI_MEM_FWRITE_DUAL field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DUAL_Msk = 0x1000 + // Bit SPI_MEM_FWRITE_DUAL. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DUAL = 0x1000 + // Position of SPI_MEM_FWRITE_QUAD field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QUAD_Pos = 0xd + // Bit mask of SPI_MEM_FWRITE_QUAD field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QUAD_Msk = 0x2000 + // Bit SPI_MEM_FWRITE_QUAD. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QUAD = 0x2000 + // Position of SPI_MEM_FWRITE_DIO field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DIO_Pos = 0xe + // Bit mask of SPI_MEM_FWRITE_DIO field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DIO_Msk = 0x4000 + // Bit SPI_MEM_FWRITE_DIO. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DIO = 0x4000 + // Position of SPI_MEM_FWRITE_QIO field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QIO_Pos = 0xf + // Bit mask of SPI_MEM_FWRITE_QIO field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QIO_Msk = 0x8000 + // Bit SPI_MEM_FWRITE_QIO. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QIO = 0x8000 + // Position of SPI_MEM_USR_MISO_HIGHPART field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of SPI_MEM_USR_MISO_HIGHPART field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit SPI_MEM_USR_MISO_HIGHPART. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART = 0x1000000 + // Position of SPI_MEM_USR_MOSI_HIGHPART field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of SPI_MEM_USR_MOSI_HIGHPART field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit SPI_MEM_USR_MOSI_HIGHPART. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART = 0x2000000 + // Position of SPI_MEM_USR_DUMMY_IDLE field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of SPI_MEM_USR_DUMMY_IDLE field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit SPI_MEM_USR_DUMMY_IDLE. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE = 0x4000000 + // Position of SPI_MEM_USR_MOSI field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_Pos = 0x1b + // Bit mask of SPI_MEM_USR_MOSI field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_Msk = 0x8000000 + // Bit SPI_MEM_USR_MOSI. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI = 0x8000000 + // Position of SPI_MEM_USR_MISO field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_Pos = 0x1c + // Bit mask of SPI_MEM_USR_MISO field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_Msk = 0x10000000 + // Bit SPI_MEM_USR_MISO. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO = 0x10000000 + // Position of SPI_MEM_USR_DUMMY field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Pos = 0x1d + // Bit mask of SPI_MEM_USR_DUMMY field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Msk = 0x20000000 + // Bit SPI_MEM_USR_DUMMY. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY = 0x20000000 + // Position of SPI_MEM_USR_ADDR field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_ADDR_Pos = 0x1e + // Bit mask of SPI_MEM_USR_ADDR field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_ADDR_Msk = 0x40000000 + // Bit SPI_MEM_USR_ADDR. + SPI1_SPI_MEM_USER_SPI_MEM_USR_ADDR = 0x40000000 + // Position of SPI_MEM_USR_COMMAND field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_COMMAND_Pos = 0x1f + // Bit mask of SPI_MEM_USR_COMMAND field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_COMMAND_Msk = 0x80000000 + // Bit SPI_MEM_USR_COMMAND. + SPI1_SPI_MEM_USER_SPI_MEM_USR_COMMAND = 0x80000000 + + // SPI_MEM_USER1: SPI1 user1 register. + // Position of SPI_MEM_USR_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of SPI_MEM_USR_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of SPI_MEM_USR_ADDR_BITLEN field. + SPI1_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of SPI_MEM_USR_ADDR_BITLEN field. + SPI1_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // SPI_MEM_USER2: SPI1 user2 register. + // Position of SPI_MEM_USR_COMMAND_VALUE field. + SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_USR_COMMAND_VALUE field. + SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Msk = 0xffff + // Position of SPI_MEM_USR_COMMAND_BITLEN field. + SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of SPI_MEM_USR_COMMAND_BITLEN field. + SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // SPI_MEM_MOSI_DLEN: SPI1 send data bit length control register. + // Position of SPI_MEM_USR_MOSI_DBITLEN field. + SPI1_SPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN_Pos = 0x0 + // Bit mask of SPI_MEM_USR_MOSI_DBITLEN field. + SPI1_SPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN_Msk = 0x3ff + + // SPI_MEM_MISO_DLEN: SPI1 receive data bit length control register. + // Position of SPI_MEM_USR_MISO_DBITLEN field. + SPI1_SPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN_Pos = 0x0 + // Bit mask of SPI_MEM_USR_MISO_DBITLEN field. + SPI1_SPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN_Msk = 0x3ff + + // SPI_MEM_RD_STATUS: SPI1 status register. + // Position of SPI_MEM_STATUS field. + SPI1_SPI_MEM_RD_STATUS_SPI_MEM_STATUS_Pos = 0x0 + // Bit mask of SPI_MEM_STATUS field. + SPI1_SPI_MEM_RD_STATUS_SPI_MEM_STATUS_Msk = 0xffff + // Position of SPI_MEM_WB_MODE field. + SPI1_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Pos = 0x10 + // Bit mask of SPI_MEM_WB_MODE field. + SPI1_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Msk = 0xff0000 + + // SPI_MEM_MISC: SPI1 misc register + // Position of SPI_MEM_CS0_DIS field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS0_DIS_Pos = 0x0 + // Bit mask of SPI_MEM_CS0_DIS field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS0_DIS_Msk = 0x1 + // Bit SPI_MEM_CS0_DIS. + SPI1_SPI_MEM_MISC_SPI_MEM_CS0_DIS = 0x1 + // Position of SPI_MEM_CS1_DIS field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS1_DIS_Pos = 0x1 + // Bit mask of SPI_MEM_CS1_DIS field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS1_DIS_Msk = 0x2 + // Bit SPI_MEM_CS1_DIS. + SPI1_SPI_MEM_MISC_SPI_MEM_CS1_DIS = 0x2 + // Position of SPI_MEM_CK_IDLE_EDGE field. + SPI1_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of SPI_MEM_CK_IDLE_EDGE field. + SPI1_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Msk = 0x200 + // Bit SPI_MEM_CK_IDLE_EDGE. + SPI1_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE = 0x200 + // Position of SPI_MEM_CS_KEEP_ACTIVE field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of SPI_MEM_CS_KEEP_ACTIVE field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit SPI_MEM_CS_KEEP_ACTIVE. + SPI1_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE = 0x400 + + // SPI_MEM_TX_CRC: SPI1 TX CRC data register. + // Position of DATA field. + SPI1_SPI_MEM_TX_CRC_DATA_Pos = 0x0 + // Bit mask of DATA field. + SPI1_SPI_MEM_TX_CRC_DATA_Msk = 0xffffffff + + // SPI_MEM_CACHE_FCTRL: SPI1 bit mode control register. + // Position of SPI_MEM_CACHE_USR_ADDR_4BYTE field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Pos = 0x1 + // Bit mask of SPI_MEM_CACHE_USR_ADDR_4BYTE field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Msk = 0x2 + // Bit SPI_MEM_CACHE_USR_ADDR_4BYTE. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE = 0x2 + // Position of SPI_MEM_FDIN_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Pos = 0x3 + // Bit mask of SPI_MEM_FDIN_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Msk = 0x8 + // Bit SPI_MEM_FDIN_DUAL. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL = 0x8 + // Position of SPI_MEM_FDOUT_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Pos = 0x4 + // Bit mask of SPI_MEM_FDOUT_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Msk = 0x10 + // Bit SPI_MEM_FDOUT_DUAL. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL = 0x10 + // Position of SPI_MEM_FADDR_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Pos = 0x5 + // Bit mask of SPI_MEM_FADDR_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Msk = 0x20 + // Bit SPI_MEM_FADDR_DUAL. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL = 0x20 + // Position of SPI_MEM_FDIN_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Pos = 0x6 + // Bit mask of SPI_MEM_FDIN_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Msk = 0x40 + // Bit SPI_MEM_FDIN_QUAD. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD = 0x40 + // Position of SPI_MEM_FDOUT_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Pos = 0x7 + // Bit mask of SPI_MEM_FDOUT_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Msk = 0x80 + // Bit SPI_MEM_FDOUT_QUAD. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD = 0x80 + // Position of SPI_MEM_FADDR_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Pos = 0x8 + // Bit mask of SPI_MEM_FADDR_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Msk = 0x100 + // Bit SPI_MEM_FADDR_QUAD. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD = 0x100 + + // SPI_MEM_W0: SPI1 memory data buffer0 + // Position of SPI_MEM_BUF0 field. + SPI1_SPI_MEM_W0_SPI_MEM_BUF0_Pos = 0x0 + // Bit mask of SPI_MEM_BUF0 field. + SPI1_SPI_MEM_W0_SPI_MEM_BUF0_Msk = 0xffffffff + + // SPI_MEM_W1: SPI1 memory data buffer1 + // Position of SPI_MEM_BUF1 field. + SPI1_SPI_MEM_W1_SPI_MEM_BUF1_Pos = 0x0 + // Bit mask of SPI_MEM_BUF1 field. + SPI1_SPI_MEM_W1_SPI_MEM_BUF1_Msk = 0xffffffff + + // SPI_MEM_W2: SPI1 memory data buffer2 + // Position of SPI_MEM_BUF2 field. + SPI1_SPI_MEM_W2_SPI_MEM_BUF2_Pos = 0x0 + // Bit mask of SPI_MEM_BUF2 field. + SPI1_SPI_MEM_W2_SPI_MEM_BUF2_Msk = 0xffffffff + + // SPI_MEM_W3: SPI1 memory data buffer3 + // Position of SPI_MEM_BUF3 field. + SPI1_SPI_MEM_W3_SPI_MEM_BUF3_Pos = 0x0 + // Bit mask of SPI_MEM_BUF3 field. + SPI1_SPI_MEM_W3_SPI_MEM_BUF3_Msk = 0xffffffff + + // SPI_MEM_W4: SPI1 memory data buffer4 + // Position of SPI_MEM_BUF4 field. + SPI1_SPI_MEM_W4_SPI_MEM_BUF4_Pos = 0x0 + // Bit mask of SPI_MEM_BUF4 field. + SPI1_SPI_MEM_W4_SPI_MEM_BUF4_Msk = 0xffffffff + + // SPI_MEM_W5: SPI1 memory data buffer5 + // Position of SPI_MEM_BUF5 field. + SPI1_SPI_MEM_W5_SPI_MEM_BUF5_Pos = 0x0 + // Bit mask of SPI_MEM_BUF5 field. + SPI1_SPI_MEM_W5_SPI_MEM_BUF5_Msk = 0xffffffff + + // SPI_MEM_W6: SPI1 memory data buffer6 + // Position of SPI_MEM_BUF6 field. + SPI1_SPI_MEM_W6_SPI_MEM_BUF6_Pos = 0x0 + // Bit mask of SPI_MEM_BUF6 field. + SPI1_SPI_MEM_W6_SPI_MEM_BUF6_Msk = 0xffffffff + + // SPI_MEM_W7: SPI1 memory data buffer7 + // Position of SPI_MEM_BUF7 field. + SPI1_SPI_MEM_W7_SPI_MEM_BUF7_Pos = 0x0 + // Bit mask of SPI_MEM_BUF7 field. + SPI1_SPI_MEM_W7_SPI_MEM_BUF7_Msk = 0xffffffff + + // SPI_MEM_W8: SPI1 memory data buffer8 + // Position of SPI_MEM_BUF8 field. + SPI1_SPI_MEM_W8_SPI_MEM_BUF8_Pos = 0x0 + // Bit mask of SPI_MEM_BUF8 field. + SPI1_SPI_MEM_W8_SPI_MEM_BUF8_Msk = 0xffffffff + + // SPI_MEM_W9: SPI1 memory data buffer9 + // Position of SPI_MEM_BUF9 field. + SPI1_SPI_MEM_W9_SPI_MEM_BUF9_Pos = 0x0 + // Bit mask of SPI_MEM_BUF9 field. + SPI1_SPI_MEM_W9_SPI_MEM_BUF9_Msk = 0xffffffff + + // SPI_MEM_W10: SPI1 memory data buffer10 + // Position of SPI_MEM_BUF10 field. + SPI1_SPI_MEM_W10_SPI_MEM_BUF10_Pos = 0x0 + // Bit mask of SPI_MEM_BUF10 field. + SPI1_SPI_MEM_W10_SPI_MEM_BUF10_Msk = 0xffffffff + + // SPI_MEM_W11: SPI1 memory data buffer11 + // Position of SPI_MEM_BUF11 field. + SPI1_SPI_MEM_W11_SPI_MEM_BUF11_Pos = 0x0 + // Bit mask of SPI_MEM_BUF11 field. + SPI1_SPI_MEM_W11_SPI_MEM_BUF11_Msk = 0xffffffff + + // SPI_MEM_W12: SPI1 memory data buffer12 + // Position of SPI_MEM_BUF12 field. + SPI1_SPI_MEM_W12_SPI_MEM_BUF12_Pos = 0x0 + // Bit mask of SPI_MEM_BUF12 field. + SPI1_SPI_MEM_W12_SPI_MEM_BUF12_Msk = 0xffffffff + + // SPI_MEM_W13: SPI1 memory data buffer13 + // Position of SPI_MEM_BUF13 field. + SPI1_SPI_MEM_W13_SPI_MEM_BUF13_Pos = 0x0 + // Bit mask of SPI_MEM_BUF13 field. + SPI1_SPI_MEM_W13_SPI_MEM_BUF13_Msk = 0xffffffff + + // SPI_MEM_W14: SPI1 memory data buffer14 + // Position of SPI_MEM_BUF14 field. + SPI1_SPI_MEM_W14_SPI_MEM_BUF14_Pos = 0x0 + // Bit mask of SPI_MEM_BUF14 field. + SPI1_SPI_MEM_W14_SPI_MEM_BUF14_Msk = 0xffffffff + + // SPI_MEM_W15: SPI1 memory data buffer15 + // Position of SPI_MEM_BUF15 field. + SPI1_SPI_MEM_W15_SPI_MEM_BUF15_Pos = 0x0 + // Bit mask of SPI_MEM_BUF15 field. + SPI1_SPI_MEM_W15_SPI_MEM_BUF15_Msk = 0xffffffff + + // SPI_MEM_FLASH_WAITI_CTRL: SPI1 wait idle control register + // Position of SPI_MEM_WAITI_EN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN_Pos = 0x0 + // Bit mask of SPI_MEM_WAITI_EN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN_Msk = 0x1 + // Bit SPI_MEM_WAITI_EN. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN = 0x1 + // Position of SPI_MEM_WAITI_DUMMY field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_Pos = 0x1 + // Bit mask of SPI_MEM_WAITI_DUMMY field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_Msk = 0x2 + // Bit SPI_MEM_WAITI_DUMMY. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY = 0x2 + // Position of SPI_MEM_WAITI_ADDR_EN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN_Pos = 0x2 + // Bit mask of SPI_MEM_WAITI_ADDR_EN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN_Msk = 0x4 + // Bit SPI_MEM_WAITI_ADDR_EN. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN = 0x4 + // Position of SPI_MEM_WAITI_ADDR_CYCLELEN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN_Pos = 0x3 + // Bit mask of SPI_MEM_WAITI_ADDR_CYCLELEN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN_Msk = 0x18 + // Position of SPI_MEM_WAITI_CMD_2B field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B_Pos = 0x9 + // Bit mask of SPI_MEM_WAITI_CMD_2B field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B_Msk = 0x200 + // Bit SPI_MEM_WAITI_CMD_2B. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B = 0x200 + // Position of SPI_MEM_WAITI_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN_Pos = 0xa + // Bit mask of SPI_MEM_WAITI_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN_Msk = 0xfc00 + // Position of SPI_MEM_WAITI_CMD field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_Pos = 0x10 + // Bit mask of SPI_MEM_WAITI_CMD field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_Msk = 0xffff0000 + + // SPI_MEM_FLASH_SUS_CTRL: SPI1 flash suspend control register + // Position of SPI_MEM_FLASH_PER field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_Pos = 0x0 + // Bit mask of SPI_MEM_FLASH_PER field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_Msk = 0x1 + // Bit SPI_MEM_FLASH_PER. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER = 0x1 + // Position of SPI_MEM_FLASH_PES field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_Pos = 0x1 + // Bit mask of SPI_MEM_FLASH_PES field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_Msk = 0x2 + // Bit SPI_MEM_FLASH_PES. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES = 0x2 + // Position of SPI_MEM_FLASH_PER_WAIT_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN_Pos = 0x2 + // Bit mask of SPI_MEM_FLASH_PER_WAIT_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN_Msk = 0x4 + // Bit SPI_MEM_FLASH_PER_WAIT_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN = 0x4 + // Position of SPI_MEM_FLASH_PES_WAIT_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN_Pos = 0x3 + // Bit mask of SPI_MEM_FLASH_PES_WAIT_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN_Msk = 0x8 + // Bit SPI_MEM_FLASH_PES_WAIT_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN = 0x8 + // Position of SPI_MEM_PES_PER_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN_Pos = 0x4 + // Bit mask of SPI_MEM_PES_PER_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN_Msk = 0x10 + // Bit SPI_MEM_PES_PER_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN = 0x10 + // Position of SPI_MEM_FLASH_PES_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN_Pos = 0x5 + // Bit mask of SPI_MEM_FLASH_PES_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN_Msk = 0x20 + // Bit SPI_MEM_FLASH_PES_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN = 0x20 + // Position of SPI_MEM_PESR_END_MSK field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK_Pos = 0x6 + // Bit mask of SPI_MEM_PESR_END_MSK field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK_Msk = 0x3fffc0 + // Position of SPI_FMEM_RD_SUS_2B field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B_Pos = 0x16 + // Bit mask of SPI_FMEM_RD_SUS_2B field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B_Msk = 0x400000 + // Bit SPI_FMEM_RD_SUS_2B. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B = 0x400000 + // Position of SPI_MEM_PER_END_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN_Pos = 0x17 + // Bit mask of SPI_MEM_PER_END_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN_Msk = 0x800000 + // Bit SPI_MEM_PER_END_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN = 0x800000 + // Position of SPI_MEM_PES_END_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN_Pos = 0x18 + // Bit mask of SPI_MEM_PES_END_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN_Msk = 0x1000000 + // Bit SPI_MEM_PES_END_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN = 0x1000000 + // Position of SPI_MEM_SUS_TIMEOUT_CNT field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT_Pos = 0x19 + // Bit mask of SPI_MEM_SUS_TIMEOUT_CNT field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT_Msk = 0xfe000000 + + // SPI_MEM_FLASH_SUS_CMD: SPI1 flash suspend command register + // Position of SPI_MEM_FLASH_PES_COMMAND field. + SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND_Pos = 0x0 + // Bit mask of SPI_MEM_FLASH_PES_COMMAND field. + SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND_Msk = 0xffff + // Position of SPI_MEM_WAIT_PESR_COMMAND field. + SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND_Pos = 0x10 + // Bit mask of SPI_MEM_WAIT_PESR_COMMAND field. + SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND_Msk = 0xffff0000 + + // SPI_MEM_SUS_STATUS: SPI1 flash suspend status register + // Position of SPI_MEM_FLASH_SUS field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS_Pos = 0x0 + // Bit mask of SPI_MEM_FLASH_SUS field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS_Msk = 0x1 + // Bit SPI_MEM_FLASH_SUS. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS = 0x1 + // Position of SPI_MEM_WAIT_PESR_CMD_2B field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B_Pos = 0x1 + // Bit mask of SPI_MEM_WAIT_PESR_CMD_2B field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B_Msk = 0x2 + // Bit SPI_MEM_WAIT_PESR_CMD_2B. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B = 0x2 + // Position of SPI_MEM_FLASH_HPM_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128_Pos = 0x2 + // Bit mask of SPI_MEM_FLASH_HPM_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128_Msk = 0x4 + // Bit SPI_MEM_FLASH_HPM_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128 = 0x4 + // Position of SPI_MEM_FLASH_RES_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128_Pos = 0x3 + // Bit mask of SPI_MEM_FLASH_RES_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128_Msk = 0x8 + // Bit SPI_MEM_FLASH_RES_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128 = 0x8 + // Position of SPI_MEM_FLASH_DP_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128_Pos = 0x4 + // Bit mask of SPI_MEM_FLASH_DP_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128_Msk = 0x10 + // Bit SPI_MEM_FLASH_DP_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128 = 0x10 + // Position of SPI_MEM_FLASH_PER_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128_Pos = 0x5 + // Bit mask of SPI_MEM_FLASH_PER_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128_Msk = 0x20 + // Bit SPI_MEM_FLASH_PER_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128 = 0x20 + // Position of SPI_MEM_FLASH_PES_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128_Pos = 0x6 + // Bit mask of SPI_MEM_FLASH_PES_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128_Msk = 0x40 + // Bit SPI_MEM_FLASH_PES_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128 = 0x40 + // Position of SPI_MEM_SPI0_LOCK_EN field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN_Pos = 0x7 + // Bit mask of SPI_MEM_SPI0_LOCK_EN field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN_Msk = 0x80 + // Bit SPI_MEM_SPI0_LOCK_EN. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN = 0x80 + // Position of SPI_MEM_FLASH_PESR_CMD_2B field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B_Pos = 0xf + // Bit mask of SPI_MEM_FLASH_PESR_CMD_2B field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B_Msk = 0x8000 + // Bit SPI_MEM_FLASH_PESR_CMD_2B. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B = 0x8000 + // Position of SPI_MEM_FLASH_PER_COMMAND field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND_Pos = 0x10 + // Bit mask of SPI_MEM_FLASH_PER_COMMAND field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND_Msk = 0xffff0000 + + // SPI_MEM_INT_ENA: SPI1 interrupt enable register + // Position of SPI_MEM_PER_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA_Pos = 0x0 + // Bit mask of SPI_MEM_PER_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA_Msk = 0x1 + // Bit SPI_MEM_PER_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA = 0x1 + // Position of SPI_MEM_PES_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA_Pos = 0x1 + // Bit mask of SPI_MEM_PES_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA_Msk = 0x2 + // Bit SPI_MEM_PES_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA = 0x2 + // Position of SPI_MEM_WPE_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA_Pos = 0x2 + // Bit mask of SPI_MEM_WPE_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA_Msk = 0x4 + // Bit SPI_MEM_WPE_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA = 0x4 + // Position of SPI_MEM_SLV_ST_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA = 0x10 + // Position of SPI_MEM_BROWN_OUT_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA_Pos = 0xa + // Bit mask of SPI_MEM_BROWN_OUT_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA_Msk = 0x400 + // Bit SPI_MEM_BROWN_OUT_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA = 0x400 + + // SPI_MEM_INT_CLR: SPI1 interrupt clear register + // Position of SPI_MEM_PER_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR_Pos = 0x0 + // Bit mask of SPI_MEM_PER_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR_Msk = 0x1 + // Bit SPI_MEM_PER_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR = 0x1 + // Position of SPI_MEM_PES_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR_Pos = 0x1 + // Bit mask of SPI_MEM_PES_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR_Msk = 0x2 + // Bit SPI_MEM_PES_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR = 0x2 + // Position of SPI_MEM_WPE_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR_Pos = 0x2 + // Bit mask of SPI_MEM_WPE_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR_Msk = 0x4 + // Bit SPI_MEM_WPE_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR = 0x4 + // Position of SPI_MEM_SLV_ST_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR = 0x10 + // Position of SPI_MEM_BROWN_OUT_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR_Pos = 0xa + // Bit mask of SPI_MEM_BROWN_OUT_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR_Msk = 0x400 + // Bit SPI_MEM_BROWN_OUT_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR = 0x400 + + // SPI_MEM_INT_RAW: SPI1 interrupt raw register + // Position of SPI_MEM_PER_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW_Pos = 0x0 + // Bit mask of SPI_MEM_PER_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW_Msk = 0x1 + // Bit SPI_MEM_PER_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW = 0x1 + // Position of SPI_MEM_PES_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW_Pos = 0x1 + // Bit mask of SPI_MEM_PES_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW_Msk = 0x2 + // Bit SPI_MEM_PES_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW = 0x2 + // Position of SPI_MEM_WPE_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW_Pos = 0x2 + // Bit mask of SPI_MEM_WPE_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW_Msk = 0x4 + // Bit SPI_MEM_WPE_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW = 0x4 + // Position of SPI_MEM_SLV_ST_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW = 0x10 + // Position of SPI_MEM_BROWN_OUT_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW_Pos = 0xa + // Bit mask of SPI_MEM_BROWN_OUT_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW_Msk = 0x400 + // Bit SPI_MEM_BROWN_OUT_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW = 0x400 + + // SPI_MEM_INT_ST: SPI1 interrupt status register + // Position of SPI_MEM_PER_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST_Pos = 0x0 + // Bit mask of SPI_MEM_PER_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST_Msk = 0x1 + // Bit SPI_MEM_PER_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST = 0x1 + // Position of SPI_MEM_PES_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST_Pos = 0x1 + // Bit mask of SPI_MEM_PES_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST_Msk = 0x2 + // Bit SPI_MEM_PES_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST = 0x2 + // Position of SPI_MEM_WPE_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST_Pos = 0x2 + // Bit mask of SPI_MEM_WPE_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST_Msk = 0x4 + // Bit SPI_MEM_WPE_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST = 0x4 + // Position of SPI_MEM_SLV_ST_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST = 0x10 + // Position of SPI_MEM_BROWN_OUT_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST_Pos = 0xa + // Bit mask of SPI_MEM_BROWN_OUT_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST_Msk = 0x400 + // Bit SPI_MEM_BROWN_OUT_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST = 0x400 + + // SPI_MEM_DDR: SPI1 DDR control register + // Position of SPI_FMEM_DDR_EN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Pos = 0x0 + // Bit mask of SPI_FMEM_DDR_EN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Msk = 0x1 + // Bit SPI_FMEM_DDR_EN. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_EN = 0x1 + // Position of SPI_FMEM_VAR_DUMMY field. + SPI1_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Pos = 0x1 + // Bit mask of SPI_FMEM_VAR_DUMMY field. + SPI1_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Msk = 0x2 + // Bit SPI_FMEM_VAR_DUMMY. + SPI1_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY = 0x2 + // Position of SPI_FMEM_DDR_RDAT_SWP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Pos = 0x2 + // Bit mask of SPI_FMEM_DDR_RDAT_SWP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Msk = 0x4 + // Bit SPI_FMEM_DDR_RDAT_SWP. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP = 0x4 + // Position of SPI_FMEM_DDR_WDAT_SWP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Pos = 0x3 + // Bit mask of SPI_FMEM_DDR_WDAT_SWP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Msk = 0x8 + // Bit SPI_FMEM_DDR_WDAT_SWP. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP = 0x8 + // Position of SPI_FMEM_DDR_CMD_DIS field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Pos = 0x4 + // Bit mask of SPI_FMEM_DDR_CMD_DIS field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Msk = 0x10 + // Bit SPI_FMEM_DDR_CMD_DIS. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS = 0x10 + // Position of SPI_FMEM_OUTMINBYTELEN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Pos = 0x5 + // Bit mask of SPI_FMEM_OUTMINBYTELEN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Msk = 0xfe0 + // Position of SPI_FMEM_USR_DDR_DQS_THD field. + SPI1_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Pos = 0xe + // Bit mask of SPI_FMEM_USR_DDR_DQS_THD field. + SPI1_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Msk = 0x1fc000 + // Position of SPI_FMEM_DDR_DQS_LOOP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Pos = 0x15 + // Bit mask of SPI_FMEM_DDR_DQS_LOOP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Msk = 0x200000 + // Bit SPI_FMEM_DDR_DQS_LOOP. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP = 0x200000 + // Position of SPI_FMEM_CLK_DIFF_EN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Pos = 0x18 + // Bit mask of SPI_FMEM_CLK_DIFF_EN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Msk = 0x1000000 + // Bit SPI_FMEM_CLK_DIFF_EN. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN = 0x1000000 + // Position of SPI_FMEM_DQS_CA_IN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Pos = 0x1a + // Bit mask of SPI_FMEM_DQS_CA_IN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Msk = 0x4000000 + // Bit SPI_FMEM_DQS_CA_IN. + SPI1_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN = 0x4000000 + // Position of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b + // Bit mask of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000 + // Bit SPI_FMEM_HYPERBUS_DUMMY_2X. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X = 0x8000000 + // Position of SPI_FMEM_CLK_DIFF_INV field. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Pos = 0x1c + // Bit mask of SPI_FMEM_CLK_DIFF_INV field. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Msk = 0x10000000 + // Bit SPI_FMEM_CLK_DIFF_INV. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV = 0x10000000 + // Position of SPI_FMEM_OCTA_RAM_ADDR field. + SPI1_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Pos = 0x1d + // Bit mask of SPI_FMEM_OCTA_RAM_ADDR field. + SPI1_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Msk = 0x20000000 + // Bit SPI_FMEM_OCTA_RAM_ADDR. + SPI1_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR = 0x20000000 + // Position of SPI_FMEM_HYPERBUS_CA field. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Pos = 0x1e + // Bit mask of SPI_FMEM_HYPERBUS_CA field. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Msk = 0x40000000 + // Bit SPI_FMEM_HYPERBUS_CA. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA = 0x40000000 + + // SPI_MEM_TIMING_CALI: SPI1 timing control register + // Position of SPI_MEM_TIMING_CALI field. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Pos = 0x1 + // Bit mask of SPI_MEM_TIMING_CALI field. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Msk = 0x2 + // Bit SPI_MEM_TIMING_CALI. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI = 0x2 + // Position of SPI_MEM_EXTRA_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of SPI_MEM_EXTRA_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + + // SPI_MEM_CLOCK_GATE: SPI1 clk_gate register + // Position of SPI_MEM_CLK_EN field. + SPI1_SPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN_Pos = 0x0 + // Bit mask of SPI_MEM_CLK_EN field. + SPI1_SPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN_Msk = 0x1 + // Bit SPI_MEM_CLK_EN. + SPI1_SPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN = 0x1 + + // SPI_MEM_DATE: Version control register + // Position of SPI_MEM_DATE field. + SPI1_SPI_MEM_DATE_SPI_MEM_DATE_Pos = 0x0 + // Bit mask of SPI_MEM_DATE field. + SPI1_SPI_MEM_DATE_SPI_MEM_DATE_Msk = 0xfffffff +) + +// Constants for SPI2: SPI (Serial Peripheral Interface) Controller 2 +const ( + // CMD: Command control register + // Position of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Pos = 0x0 + // Bit mask of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Msk = 0x3ffff + // Position of UPDATE field. + SPI2_CMD_UPDATE_Pos = 0x17 + // Bit mask of UPDATE field. + SPI2_CMD_UPDATE_Msk = 0x800000 + // Bit UPDATE. + SPI2_CMD_UPDATE = 0x800000 + // Position of USR field. + SPI2_CMD_USR_Pos = 0x18 + // Bit mask of USR field. + SPI2_CMD_USR_Msk = 0x1000000 + // Bit USR. + SPI2_CMD_USR = 0x1000000 + + // ADDR: Address value register + // Position of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Msk = 0xffffffff + + // CTRL: SPI control register + // Position of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Pos = 0x3 + // Bit mask of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Msk = 0x8 + // Bit DUMMY_OUT. + SPI2_CTRL_DUMMY_OUT = 0x8 + // Position of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI2_CTRL_FADDR_DUAL = 0x20 + // Position of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Pos = 0x6 + // Bit mask of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Msk = 0x40 + // Bit FADDR_QUAD. + SPI2_CTRL_FADDR_QUAD = 0x40 + // Position of FADDR_OCT field. + SPI2_CTRL_FADDR_OCT_Pos = 0x7 + // Bit mask of FADDR_OCT field. + SPI2_CTRL_FADDR_OCT_Msk = 0x80 + // Bit FADDR_OCT. + SPI2_CTRL_FADDR_OCT = 0x80 + // Position of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Pos = 0x8 + // Bit mask of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Msk = 0x100 + // Bit FCMD_DUAL. + SPI2_CTRL_FCMD_DUAL = 0x100 + // Position of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Pos = 0x9 + // Bit mask of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Msk = 0x200 + // Bit FCMD_QUAD. + SPI2_CTRL_FCMD_QUAD = 0x200 + // Position of FCMD_OCT field. + SPI2_CTRL_FCMD_OCT_Pos = 0xa + // Bit mask of FCMD_OCT field. + SPI2_CTRL_FCMD_OCT_Msk = 0x400 + // Bit FCMD_OCT. + SPI2_CTRL_FCMD_OCT = 0x400 + // Position of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI2_CTRL_FREAD_DUAL = 0x4000 + // Position of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Pos = 0xf + // Bit mask of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Msk = 0x8000 + // Bit FREAD_QUAD. + SPI2_CTRL_FREAD_QUAD = 0x8000 + // Position of FREAD_OCT field. + SPI2_CTRL_FREAD_OCT_Pos = 0x10 + // Bit mask of FREAD_OCT field. + SPI2_CTRL_FREAD_OCT_Msk = 0x10000 + // Bit FREAD_OCT. + SPI2_CTRL_FREAD_OCT = 0x10000 + // Position of Q_POL field. + SPI2_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI2_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI2_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI2_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI2_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI2_CTRL_D_POL = 0x80000 + // Position of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Pos = 0x14 + // Bit mask of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Msk = 0x100000 + // Bit HOLD_POL. + SPI2_CTRL_HOLD_POL = 0x100000 + // Position of WP_POL field. + SPI2_CTRL_WP_POL_Pos = 0x15 + // Bit mask of WP_POL field. + SPI2_CTRL_WP_POL_Msk = 0x200000 + // Bit WP_POL. + SPI2_CTRL_WP_POL = 0x200000 + // Position of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Pos = 0x17 + // Bit mask of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Msk = 0x1800000 + // Position of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Pos = 0x19 + // Bit mask of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Msk = 0x6000000 + + // CLOCK: SPI clock control register + // Position of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Msk = 0x3f + // Position of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Pos = 0x6 + // Bit mask of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Msk = 0xfc0 + // Position of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Pos = 0xc + // Bit mask of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Msk = 0x3f000 + // Position of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Pos = 0x12 + // Bit mask of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Msk = 0x3c0000 + // Position of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI2_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI USER control register + // Position of DOUTDIN field. + SPI2_USER_DOUTDIN_Pos = 0x0 + // Bit mask of DOUTDIN field. + SPI2_USER_DOUTDIN_Msk = 0x1 + // Bit DOUTDIN. + SPI2_USER_DOUTDIN = 0x1 + // Position of QPI_MODE field. + SPI2_USER_QPI_MODE_Pos = 0x3 + // Bit mask of QPI_MODE field. + SPI2_USER_QPI_MODE_Msk = 0x8 + // Bit QPI_MODE. + SPI2_USER_QPI_MODE = 0x8 + // Position of OPI_MODE field. + SPI2_USER_OPI_MODE_Pos = 0x4 + // Bit mask of OPI_MODE field. + SPI2_USER_OPI_MODE_Msk = 0x10 + // Bit OPI_MODE. + SPI2_USER_OPI_MODE = 0x10 + // Position of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Pos = 0x5 + // Bit mask of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Msk = 0x20 + // Bit TSCK_I_EDGE. + SPI2_USER_TSCK_I_EDGE = 0x20 + // Position of CS_HOLD field. + SPI2_USER_CS_HOLD_Pos = 0x6 + // Bit mask of CS_HOLD field. + SPI2_USER_CS_HOLD_Msk = 0x40 + // Bit CS_HOLD. + SPI2_USER_CS_HOLD = 0x40 + // Position of CS_SETUP field. + SPI2_USER_CS_SETUP_Pos = 0x7 + // Bit mask of CS_SETUP field. + SPI2_USER_CS_SETUP_Msk = 0x80 + // Bit CS_SETUP. + SPI2_USER_CS_SETUP = 0x80 + // Position of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Pos = 0x8 + // Bit mask of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Msk = 0x100 + // Bit RSCK_I_EDGE. + SPI2_USER_RSCK_I_EDGE = 0x100 + // Position of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI2_USER_CK_OUT_EDGE = 0x200 + // Position of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI2_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI2_USER_FWRITE_QUAD = 0x2000 + // Position of FWRITE_OCT field. + SPI2_USER_FWRITE_OCT_Pos = 0xe + // Bit mask of FWRITE_OCT field. + SPI2_USER_FWRITE_OCT_Msk = 0x4000 + // Bit FWRITE_OCT. + SPI2_USER_FWRITE_OCT = 0x4000 + // Position of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Pos = 0xf + // Bit mask of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Msk = 0x8000 + // Bit USR_CONF_NXT. + SPI2_USER_USR_CONF_NXT = 0x8000 + // Position of SIO field. + SPI2_USER_SIO_Pos = 0x11 + // Bit mask of SIO field. + SPI2_USER_SIO_Msk = 0x20000 + // Bit SIO. + SPI2_USER_SIO = 0x20000 + // Position of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI2_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI2_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI2_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI2_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI2_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI2_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI2_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI2_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI2_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI2_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI2_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI2_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI2_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI2_USER_USR_COMMAND = 0x80000000 + + // USER1: SPI USER control register 1 + // Position of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Msk = 0xff + // Position of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Pos = 0x10 + // Bit mask of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Msk = 0x10000 + // Bit MST_WFULL_ERR_END_EN. + SPI2_USER1_MST_WFULL_ERR_END_EN = 0x10000 + // Position of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Pos = 0x11 + // Bit mask of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Msk = 0x3e0000 + // Position of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Pos = 0x16 + // Bit mask of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Msk = 0x7c00000 + // Position of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Pos = 0x1b + // Bit mask of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Msk = 0xf8000000 + + // USER2: SPI USER control register 2 + // Position of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Pos = 0x1b + // Bit mask of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Msk = 0x8000000 + // Bit MST_REMPTY_ERR_END_EN. + SPI2_USER2_MST_REMPTY_ERR_END_EN = 0x8000000 + // Position of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MS_DLEN: SPI data bit length control register + // Position of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Pos = 0x0 + // Bit mask of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Msk = 0x3ffff + + // MISC: SPI misc register + // Position of CS0_DIS field. + SPI2_MISC_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI2_MISC_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI2_MISC_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI2_MISC_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI2_MISC_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI2_MISC_CS1_DIS = 0x2 + // Position of CS2_DIS field. + SPI2_MISC_CS2_DIS_Pos = 0x2 + // Bit mask of CS2_DIS field. + SPI2_MISC_CS2_DIS_Msk = 0x4 + // Bit CS2_DIS. + SPI2_MISC_CS2_DIS = 0x4 + // Position of CS3_DIS field. + SPI2_MISC_CS3_DIS_Pos = 0x3 + // Bit mask of CS3_DIS field. + SPI2_MISC_CS3_DIS_Msk = 0x8 + // Bit CS3_DIS. + SPI2_MISC_CS3_DIS = 0x8 + // Position of CS4_DIS field. + SPI2_MISC_CS4_DIS_Pos = 0x4 + // Bit mask of CS4_DIS field. + SPI2_MISC_CS4_DIS_Msk = 0x10 + // Bit CS4_DIS. + SPI2_MISC_CS4_DIS = 0x10 + // Position of CS5_DIS field. + SPI2_MISC_CS5_DIS_Pos = 0x5 + // Bit mask of CS5_DIS field. + SPI2_MISC_CS5_DIS_Msk = 0x20 + // Bit CS5_DIS. + SPI2_MISC_CS5_DIS = 0x20 + // Position of CK_DIS field. + SPI2_MISC_CK_DIS_Pos = 0x6 + // Bit mask of CK_DIS field. + SPI2_MISC_CK_DIS_Msk = 0x40 + // Bit CK_DIS. + SPI2_MISC_CK_DIS = 0x40 + // Position of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Pos = 0x7 + // Bit mask of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Msk = 0x1f80 + // Position of CLK_DATA_DTR_EN field. + SPI2_MISC_CLK_DATA_DTR_EN_Pos = 0x10 + // Bit mask of CLK_DATA_DTR_EN field. + SPI2_MISC_CLK_DATA_DTR_EN_Msk = 0x10000 + // Bit CLK_DATA_DTR_EN. + SPI2_MISC_CLK_DATA_DTR_EN = 0x10000 + // Position of DATA_DTR_EN field. + SPI2_MISC_DATA_DTR_EN_Pos = 0x11 + // Bit mask of DATA_DTR_EN field. + SPI2_MISC_DATA_DTR_EN_Msk = 0x20000 + // Bit DATA_DTR_EN. + SPI2_MISC_DATA_DTR_EN = 0x20000 + // Position of ADDR_DTR_EN field. + SPI2_MISC_ADDR_DTR_EN_Pos = 0x12 + // Bit mask of ADDR_DTR_EN field. + SPI2_MISC_ADDR_DTR_EN_Msk = 0x40000 + // Bit ADDR_DTR_EN. + SPI2_MISC_ADDR_DTR_EN = 0x40000 + // Position of CMD_DTR_EN field. + SPI2_MISC_CMD_DTR_EN_Pos = 0x13 + // Bit mask of CMD_DTR_EN field. + SPI2_MISC_CMD_DTR_EN_Msk = 0x80000 + // Bit CMD_DTR_EN. + SPI2_MISC_CMD_DTR_EN = 0x80000 + // Position of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Pos = 0x17 + // Bit mask of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Msk = 0x800000 + // Bit SLAVE_CS_POL. + SPI2_MISC_SLAVE_CS_POL = 0x800000 + // Position of DQS_IDLE_EDGE field. + SPI2_MISC_DQS_IDLE_EDGE_Pos = 0x18 + // Bit mask of DQS_IDLE_EDGE field. + SPI2_MISC_DQS_IDLE_EDGE_Msk = 0x1000000 + // Bit DQS_IDLE_EDGE. + SPI2_MISC_DQS_IDLE_EDGE = 0x1000000 + // Position of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Pos = 0x1d + // Bit mask of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Msk = 0x20000000 + // Bit CK_IDLE_EDGE. + SPI2_MISC_CK_IDLE_EDGE = 0x20000000 + // Position of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Pos = 0x1e + // Bit mask of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Msk = 0x40000000 + // Bit CS_KEEP_ACTIVE. + SPI2_MISC_CS_KEEP_ACTIVE = 0x40000000 + // Position of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Pos = 0x1f + // Bit mask of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Msk = 0x80000000 + // Bit QUAD_DIN_PIN_SWAP. + SPI2_MISC_QUAD_DIN_PIN_SWAP = 0x80000000 + + // DIN_MODE: SPI input delay mode configuration + // Position of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Pos = 0x0 + // Bit mask of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Msk = 0x3 + // Position of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Pos = 0x2 + // Bit mask of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Msk = 0xc + // Position of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Pos = 0x4 + // Bit mask of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Msk = 0x30 + // Position of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Pos = 0x6 + // Bit mask of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Msk = 0xc0 + // Position of DIN4_MODE field. + SPI2_DIN_MODE_DIN4_MODE_Pos = 0x8 + // Bit mask of DIN4_MODE field. + SPI2_DIN_MODE_DIN4_MODE_Msk = 0x300 + // Position of DIN5_MODE field. + SPI2_DIN_MODE_DIN5_MODE_Pos = 0xa + // Bit mask of DIN5_MODE field. + SPI2_DIN_MODE_DIN5_MODE_Msk = 0xc00 + // Position of DIN6_MODE field. + SPI2_DIN_MODE_DIN6_MODE_Pos = 0xc + // Bit mask of DIN6_MODE field. + SPI2_DIN_MODE_DIN6_MODE_Msk = 0x3000 + // Position of DIN7_MODE field. + SPI2_DIN_MODE_DIN7_MODE_Pos = 0xe + // Bit mask of DIN7_MODE field. + SPI2_DIN_MODE_DIN7_MODE_Msk = 0xc000 + // Position of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Pos = 0x10 + // Bit mask of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Msk = 0x10000 + // Bit TIMING_HCLK_ACTIVE. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE = 0x10000 + + // DIN_NUM: SPI input delay number configuration + // Position of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Pos = 0x0 + // Bit mask of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Msk = 0x3 + // Position of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Pos = 0x2 + // Bit mask of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Msk = 0xc + // Position of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Pos = 0x4 + // Bit mask of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Msk = 0x30 + // Position of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Pos = 0x6 + // Bit mask of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Msk = 0xc0 + // Position of DIN4_NUM field. + SPI2_DIN_NUM_DIN4_NUM_Pos = 0x8 + // Bit mask of DIN4_NUM field. + SPI2_DIN_NUM_DIN4_NUM_Msk = 0x300 + // Position of DIN5_NUM field. + SPI2_DIN_NUM_DIN5_NUM_Pos = 0xa + // Bit mask of DIN5_NUM field. + SPI2_DIN_NUM_DIN5_NUM_Msk = 0xc00 + // Position of DIN6_NUM field. + SPI2_DIN_NUM_DIN6_NUM_Pos = 0xc + // Bit mask of DIN6_NUM field. + SPI2_DIN_NUM_DIN6_NUM_Msk = 0x3000 + // Position of DIN7_NUM field. + SPI2_DIN_NUM_DIN7_NUM_Pos = 0xe + // Bit mask of DIN7_NUM field. + SPI2_DIN_NUM_DIN7_NUM_Msk = 0xc000 + + // DOUT_MODE: SPI output delay mode configuration + // Position of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Msk = 0x1 + // Bit DOUT0_MODE. + SPI2_DOUT_MODE_DOUT0_MODE = 0x1 + // Position of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Pos = 0x1 + // Bit mask of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Msk = 0x2 + // Bit DOUT1_MODE. + SPI2_DOUT_MODE_DOUT1_MODE = 0x2 + // Position of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Pos = 0x2 + // Bit mask of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Msk = 0x4 + // Bit DOUT2_MODE. + SPI2_DOUT_MODE_DOUT2_MODE = 0x4 + // Position of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Pos = 0x3 + // Bit mask of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Msk = 0x8 + // Bit DOUT3_MODE. + SPI2_DOUT_MODE_DOUT3_MODE = 0x8 + // Position of DOUT4_MODE field. + SPI2_DOUT_MODE_DOUT4_MODE_Pos = 0x4 + // Bit mask of DOUT4_MODE field. + SPI2_DOUT_MODE_DOUT4_MODE_Msk = 0x10 + // Bit DOUT4_MODE. + SPI2_DOUT_MODE_DOUT4_MODE = 0x10 + // Position of DOUT5_MODE field. + SPI2_DOUT_MODE_DOUT5_MODE_Pos = 0x5 + // Bit mask of DOUT5_MODE field. + SPI2_DOUT_MODE_DOUT5_MODE_Msk = 0x20 + // Bit DOUT5_MODE. + SPI2_DOUT_MODE_DOUT5_MODE = 0x20 + // Position of DOUT6_MODE field. + SPI2_DOUT_MODE_DOUT6_MODE_Pos = 0x6 + // Bit mask of DOUT6_MODE field. + SPI2_DOUT_MODE_DOUT6_MODE_Msk = 0x40 + // Bit DOUT6_MODE. + SPI2_DOUT_MODE_DOUT6_MODE = 0x40 + // Position of DOUT7_MODE field. + SPI2_DOUT_MODE_DOUT7_MODE_Pos = 0x7 + // Bit mask of DOUT7_MODE field. + SPI2_DOUT_MODE_DOUT7_MODE_Msk = 0x80 + // Bit DOUT7_MODE. + SPI2_DOUT_MODE_DOUT7_MODE = 0x80 + // Position of D_DQS_MODE field. + SPI2_DOUT_MODE_D_DQS_MODE_Pos = 0x8 + // Bit mask of D_DQS_MODE field. + SPI2_DOUT_MODE_D_DQS_MODE_Msk = 0x100 + // Bit D_DQS_MODE. + SPI2_DOUT_MODE_D_DQS_MODE = 0x100 + + // DMA_CONF: SPI DMA control register + // Position of DMA_OUTFIFO_EMPTY field. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY_Pos = 0x0 + // Bit mask of DMA_OUTFIFO_EMPTY field. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY_Msk = 0x1 + // Bit DMA_OUTFIFO_EMPTY. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY = 0x1 + // Position of DMA_INFIFO_FULL field. + SPI2_DMA_CONF_DMA_INFIFO_FULL_Pos = 0x1 + // Bit mask of DMA_INFIFO_FULL field. + SPI2_DMA_CONF_DMA_INFIFO_FULL_Msk = 0x2 + // Bit DMA_INFIFO_FULL. + SPI2_DMA_CONF_DMA_INFIFO_FULL = 0x2 + // Position of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Pos = 0x12 + // Bit mask of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Msk = 0x40000 + // Bit DMA_SLV_SEG_TRANS_EN. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN = 0x40000 + // Position of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Pos = 0x13 + // Bit mask of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Msk = 0x80000 + // Bit SLV_RX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN = 0x80000 + // Position of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Pos = 0x14 + // Bit mask of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Msk = 0x100000 + // Bit SLV_TX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN = 0x100000 + // Position of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Pos = 0x15 + // Bit mask of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Msk = 0x200000 + // Bit RX_EOF_EN. + SPI2_DMA_CONF_RX_EOF_EN = 0x200000 + // Position of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Pos = 0x1b + // Bit mask of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Msk = 0x8000000 + // Bit DMA_RX_ENA. + SPI2_DMA_CONF_DMA_RX_ENA = 0x8000000 + // Position of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Pos = 0x1c + // Bit mask of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Msk = 0x10000000 + // Bit DMA_TX_ENA. + SPI2_DMA_CONF_DMA_TX_ENA = 0x10000000 + // Position of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Pos = 0x1d + // Bit mask of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Msk = 0x20000000 + // Bit RX_AFIFO_RST. + SPI2_DMA_CONF_RX_AFIFO_RST = 0x20000000 + // Position of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Pos = 0x1e + // Bit mask of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Msk = 0x40000000 + // Bit BUF_AFIFO_RST. + SPI2_DMA_CONF_BUF_AFIFO_RST = 0x40000000 + // Position of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Pos = 0x1f + // Bit mask of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Msk = 0x80000000 + // Bit DMA_AFIFO_RST. + SPI2_DMA_CONF_DMA_AFIFO_RST = 0x80000000 + + // DMA_INT_ENA: SPI interrupt enable register + // Position of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA = 0x2 + // Position of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA = 0x4 + // Position of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA = 0x8 + // Position of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Msk = 0x10 + // Bit SLV_CMD7_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA = 0x10 + // Position of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Msk = 0x20 + // Bit SLV_CMD8_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA = 0x20 + // Position of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Msk = 0x40 + // Bit SLV_CMD9_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA = 0x40 + // Position of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Msk = 0x80 + // Bit SLV_CMDA_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA = 0x800 + // Position of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Msk = 0x1000 + // Bit TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA = 0x8000 + // Position of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA = 0x40000 + // Position of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Pos = 0x13 + // Bit mask of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Msk = 0x80000 + // Bit APP2_INT_ENA. + SPI2_DMA_INT_ENA_APP2_INT_ENA = 0x80000 + // Position of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Pos = 0x14 + // Bit mask of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Msk = 0x100000 + // Bit APP1_INT_ENA. + SPI2_DMA_INT_ENA_APP1_INT_ENA = 0x100000 + + // DMA_INT_CLR: SPI interrupt clear register + // Position of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR = 0x2 + // Position of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Msk = 0x4 + // Bit SLV_EX_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR = 0x4 + // Position of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Msk = 0x8 + // Bit SLV_EN_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR = 0x8 + // Position of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Msk = 0x10 + // Bit SLV_CMD7_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR = 0x10 + // Position of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Msk = 0x20 + // Bit SLV_CMD8_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR = 0x20 + // Position of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Msk = 0x40 + // Bit SLV_CMD9_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR = 0x40 + // Position of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Msk = 0x80 + // Bit SLV_CMDA_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR = 0x80 + // Position of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR = 0x100 + // Position of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR = 0x200 + // Position of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR = 0x400 + // Position of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR = 0x800 + // Position of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Pos = 0xc + // Bit mask of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Msk = 0x1000 + // Bit TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR = 0x2000 + // Position of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR = 0x8000 + // Position of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR = 0x40000 + // Position of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Pos = 0x13 + // Bit mask of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Msk = 0x80000 + // Bit APP2_INT_CLR. + SPI2_DMA_INT_CLR_APP2_INT_CLR = 0x80000 + // Position of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Pos = 0x14 + // Bit mask of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Msk = 0x100000 + // Bit APP1_INT_CLR. + SPI2_DMA_INT_CLR_APP1_INT_CLR = 0x100000 + + // DMA_INT_RAW: SPI interrupt raw register + // Position of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW = 0x2 + // Position of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Msk = 0x4 + // Bit SLV_EX_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW = 0x4 + // Position of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Msk = 0x8 + // Bit SLV_EN_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW = 0x8 + // Position of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Msk = 0x10 + // Bit SLV_CMD7_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW = 0x10 + // Position of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Msk = 0x20 + // Bit SLV_CMD8_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW = 0x20 + // Position of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Msk = 0x40 + // Bit SLV_CMD9_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW = 0x40 + // Position of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Msk = 0x80 + // Bit SLV_CMDA_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW = 0x80 + // Position of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW = 0x100 + // Position of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW = 0x200 + // Position of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW = 0x400 + // Position of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW = 0x800 + // Position of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Pos = 0xc + // Bit mask of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Msk = 0x1000 + // Bit TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW = 0x2000 + // Position of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW = 0x8000 + // Position of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW = 0x40000 + // Position of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Pos = 0x13 + // Bit mask of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Msk = 0x80000 + // Bit APP2_INT_RAW. + SPI2_DMA_INT_RAW_APP2_INT_RAW = 0x80000 + // Position of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Pos = 0x14 + // Bit mask of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Msk = 0x100000 + // Bit APP1_INT_RAW. + SPI2_DMA_INT_RAW_APP1_INT_RAW = 0x100000 + + // DMA_INT_ST: SPI interrupt status register + // Position of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST = 0x2 + // Position of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST = 0x4 + // Position of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST = 0x8 + // Position of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Msk = 0x10 + // Bit SLV_CMD7_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST = 0x10 + // Position of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Msk = 0x20 + // Bit SLV_CMD8_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST = 0x20 + // Position of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Msk = 0x40 + // Bit SLV_CMD9_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST = 0x40 + // Position of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Msk = 0x80 + // Bit SLV_CMDA_INT_ST. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST = 0x800 + // Position of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Msk = 0x1000 + // Bit TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ST. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST = 0x8000 + // Position of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST = 0x40000 + // Position of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Pos = 0x13 + // Bit mask of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Msk = 0x80000 + // Bit APP2_INT_ST. + SPI2_DMA_INT_ST_APP2_INT_ST = 0x80000 + // Position of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Pos = 0x14 + // Bit mask of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Msk = 0x100000 + // Bit APP1_INT_ST. + SPI2_DMA_INT_ST_APP1_INT_ST = 0x100000 + + // DMA_INT_SET: SPI interrupt software set register + // Position of DMA_INFIFO_FULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_SET. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_SET. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET = 0x2 + // Position of SLV_EX_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET_Msk = 0x4 + // Bit SLV_EX_QPI_INT_SET. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET = 0x4 + // Position of SLV_EN_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET_Msk = 0x8 + // Bit SLV_EN_QPI_INT_SET. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET = 0x8 + // Position of SLV_CMD7_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET_Msk = 0x10 + // Bit SLV_CMD7_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET = 0x10 + // Position of SLV_CMD8_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET_Msk = 0x20 + // Bit SLV_CMD8_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET = 0x20 + // Position of SLV_CMD9_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET_Msk = 0x40 + // Bit SLV_CMD9_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET = 0x40 + // Position of SLV_CMDA_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET_Msk = 0x80 + // Bit SLV_CMDA_INT_SET. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET = 0x80 + // Position of SLV_RD_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET = 0x100 + // Position of SLV_WR_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET = 0x200 + // Position of SLV_RD_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET = 0x400 + // Position of SLV_WR_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET = 0x800 + // Position of TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET_Pos = 0xc + // Bit mask of TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET_Msk = 0x1000 + // Bit TRANS_DONE_INT_SET. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_SET. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET = 0x2000 + // Position of SEG_MAGIC_ERR_INT_SET field. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_SET field. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_SET. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_SET. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET = 0x8000 + // Position of SLV_CMD_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_SET. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_SET. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET = 0x40000 + // Position of APP2_INT_SET field. + SPI2_DMA_INT_SET_APP2_INT_SET_Pos = 0x13 + // Bit mask of APP2_INT_SET field. + SPI2_DMA_INT_SET_APP2_INT_SET_Msk = 0x80000 + // Bit APP2_INT_SET. + SPI2_DMA_INT_SET_APP2_INT_SET = 0x80000 + // Position of APP1_INT_SET field. + SPI2_DMA_INT_SET_APP1_INT_SET_Pos = 0x14 + // Bit mask of APP1_INT_SET field. + SPI2_DMA_INT_SET_APP1_INT_SET_Msk = 0x100000 + // Bit APP1_INT_SET. + SPI2_DMA_INT_SET_APP1_INT_SET = 0x100000 + + // W0: SPI CPU-controlled buffer0 + // Position of BUF0 field. + SPI2_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI2_W0_BUF0_Msk = 0xffffffff + + // W1: SPI CPU-controlled buffer1 + // Position of BUF1 field. + SPI2_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI2_W1_BUF1_Msk = 0xffffffff + + // W2: SPI CPU-controlled buffer2 + // Position of BUF2 field. + SPI2_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI2_W2_BUF2_Msk = 0xffffffff + + // W3: SPI CPU-controlled buffer3 + // Position of BUF3 field. + SPI2_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI2_W3_BUF3_Msk = 0xffffffff + + // W4: SPI CPU-controlled buffer4 + // Position of BUF4 field. + SPI2_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI2_W4_BUF4_Msk = 0xffffffff + + // W5: SPI CPU-controlled buffer5 + // Position of BUF5 field. + SPI2_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI2_W5_BUF5_Msk = 0xffffffff + + // W6: SPI CPU-controlled buffer6 + // Position of BUF6 field. + SPI2_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI2_W6_BUF6_Msk = 0xffffffff + + // W7: SPI CPU-controlled buffer7 + // Position of BUF7 field. + SPI2_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI2_W7_BUF7_Msk = 0xffffffff + + // W8: SPI CPU-controlled buffer8 + // Position of BUF8 field. + SPI2_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI2_W8_BUF8_Msk = 0xffffffff + + // W9: SPI CPU-controlled buffer9 + // Position of BUF9 field. + SPI2_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI2_W9_BUF9_Msk = 0xffffffff + + // W10: SPI CPU-controlled buffer10 + // Position of BUF10 field. + SPI2_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI2_W10_BUF10_Msk = 0xffffffff + + // W11: SPI CPU-controlled buffer11 + // Position of BUF11 field. + SPI2_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI2_W11_BUF11_Msk = 0xffffffff + + // W12: SPI CPU-controlled buffer12 + // Position of BUF12 field. + SPI2_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI2_W12_BUF12_Msk = 0xffffffff + + // W13: SPI CPU-controlled buffer13 + // Position of BUF13 field. + SPI2_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI2_W13_BUF13_Msk = 0xffffffff + + // W14: SPI CPU-controlled buffer14 + // Position of BUF14 field. + SPI2_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI2_W14_BUF14_Msk = 0xffffffff + + // W15: SPI CPU-controlled buffer15 + // Position of BUF15 field. + SPI2_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI2_W15_BUF15_Msk = 0xffffffff + + // SLAVE: SPI slave control register + // Position of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Msk = 0x3 + // Position of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Pos = 0x2 + // Bit mask of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Msk = 0x4 + // Bit CLK_MODE_13. + SPI2_SLAVE_CLK_MODE_13 = 0x4 + // Position of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Pos = 0x3 + // Bit mask of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Msk = 0x8 + // Bit RSCK_DATA_OUT. + SPI2_SLAVE_RSCK_DATA_OUT = 0x8 + // Position of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Pos = 0x8 + // Bit mask of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Msk = 0x100 + // Bit SLV_RDDMA_BITLEN_EN. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN = 0x100 + // Position of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Pos = 0x9 + // Bit mask of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Msk = 0x200 + // Bit SLV_WRDMA_BITLEN_EN. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN = 0x200 + // Position of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Pos = 0xa + // Bit mask of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Msk = 0x400 + // Bit SLV_RDBUF_BITLEN_EN. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN = 0x400 + // Position of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Pos = 0xb + // Bit mask of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Msk = 0x800 + // Bit SLV_WRBUF_BITLEN_EN. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN = 0x800 + // Position of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Pos = 0x16 + // Bit mask of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Msk = 0x3c00000 + // Position of MODE field. + SPI2_SLAVE_MODE_Pos = 0x1a + // Bit mask of MODE field. + SPI2_SLAVE_MODE_Msk = 0x4000000 + // Bit MODE. + SPI2_SLAVE_MODE = 0x4000000 + // Position of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Pos = 0x1b + // Bit mask of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Msk = 0x8000000 + // Bit SOFT_RESET. + SPI2_SLAVE_SOFT_RESET = 0x8000000 + // Position of USR_CONF field. + SPI2_SLAVE_USR_CONF_Pos = 0x1c + // Bit mask of USR_CONF field. + SPI2_SLAVE_USR_CONF_Msk = 0x10000000 + // Bit USR_CONF. + SPI2_SLAVE_USR_CONF = 0x10000000 + // Position of MST_FD_WAIT_DMA_TX_DATA field. + SPI2_SLAVE_MST_FD_WAIT_DMA_TX_DATA_Pos = 0x1d + // Bit mask of MST_FD_WAIT_DMA_TX_DATA field. + SPI2_SLAVE_MST_FD_WAIT_DMA_TX_DATA_Msk = 0x20000000 + // Bit MST_FD_WAIT_DMA_TX_DATA. + SPI2_SLAVE_MST_FD_WAIT_DMA_TX_DATA = 0x20000000 + + // SLAVE1: SPI slave control register 1 + // Position of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Pos = 0x0 + // Bit mask of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Msk = 0x3ffff + // Position of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Pos = 0x12 + // Bit mask of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Msk = 0x3fc0000 + // Position of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Pos = 0x1a + // Bit mask of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Msk = 0xfc000000 + + // CLK_GATE: SPI module clock and register clock control + // Position of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI2_CLK_GATE_CLK_EN = 0x1 + // Position of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Pos = 0x1 + // Bit mask of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Msk = 0x2 + // Bit MST_CLK_ACTIVE. + SPI2_CLK_GATE_MST_CLK_ACTIVE = 0x2 + // Position of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Pos = 0x2 + // Bit mask of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Msk = 0x4 + // Bit MST_CLK_SEL. + SPI2_CLK_GATE_MST_CLK_SEL = 0x4 + + // DATE: Version control + // Position of DATE field. + SPI2_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI2_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SYSTIMER: System Timer +const ( + // CONF: Configure system timer clock + // Position of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Pos = 0x0 + // Bit mask of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Msk = 0x1 + // Bit SYSTIMER_CLK_FO. + SYSTIMER_CONF_SYSTIMER_CLK_FO = 0x1 + // Position of ETM_EN field. + SYSTIMER_CONF_ETM_EN_Pos = 0x1 + // Bit mask of ETM_EN field. + SYSTIMER_CONF_ETM_EN_Msk = 0x2 + // Bit ETM_EN. + SYSTIMER_CONF_ETM_EN = 0x2 + // Position of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Pos = 0x16 + // Bit mask of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Msk = 0x400000 + // Bit TARGET2_WORK_EN. + SYSTIMER_CONF_TARGET2_WORK_EN = 0x400000 + // Position of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Pos = 0x17 + // Bit mask of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Msk = 0x800000 + // Bit TARGET1_WORK_EN. + SYSTIMER_CONF_TARGET1_WORK_EN = 0x800000 + // Position of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Pos = 0x18 + // Bit mask of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Msk = 0x1000000 + // Bit TARGET0_WORK_EN. + SYSTIMER_CONF_TARGET0_WORK_EN = 0x1000000 + // Position of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Pos = 0x19 + // Bit mask of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Msk = 0x2000000 + // Bit TIMER_UNIT1_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN = 0x2000000 + // Position of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Pos = 0x1a + // Bit mask of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Msk = 0x4000000 + // Bit TIMER_UNIT1_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN = 0x4000000 + // Position of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Pos = 0x1b + // Bit mask of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Msk = 0x8000000 + // Bit TIMER_UNIT0_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN = 0x8000000 + // Position of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Pos = 0x1c + // Bit mask of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Msk = 0x10000000 + // Bit TIMER_UNIT0_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN = 0x10000000 + // Position of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Pos = 0x1d + // Bit mask of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Msk = 0x20000000 + // Bit TIMER_UNIT1_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN = 0x20000000 + // Position of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Pos = 0x1e + // Bit mask of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Msk = 0x40000000 + // Bit TIMER_UNIT0_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN = 0x40000000 + // Position of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + SYSTIMER_CONF_CLK_EN = 0x80000000 + + // UNIT0_OP: system timer unit0 value update register + // Position of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT0_VALUE_VALID. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT0_UPDATE. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE = 0x40000000 + + // UNIT1_OP: system timer unit1 value update register + // Position of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT1_VALUE_VALID. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT1_UPDATE. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE = 0x40000000 + + // UNIT0_LOAD_HI: system timer unit0 value high load register + // Position of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Msk = 0xfffff + + // UNIT0_LOAD_LO: system timer unit0 value low load register + // Position of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Msk = 0xffffffff + + // UNIT1_LOAD_HI: system timer unit1 value high load register + // Position of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Msk = 0xfffff + + // UNIT1_LOAD_LO: system timer unit1 value low load register + // Position of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Msk = 0xffffffff + + // TARGET0_HI: system timer comp0 value high register + // Position of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Msk = 0xfffff + + // TARGET0_LO: system timer comp0 value low register + // Position of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Msk = 0xffffffff + + // TARGET1_HI: system timer comp1 value high register + // Position of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Msk = 0xfffff + + // TARGET1_LO: system timer comp1 value low register + // Position of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Msk = 0xffffffff + + // TARGET2_HI: system timer comp2 value high register + // Position of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Msk = 0xfffff + + // TARGET2_LO: system timer comp2 value low register + // Position of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Msk = 0xffffffff + + // TARGET0_CONF: system timer comp0 target mode register + // Position of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Pos = 0x0 + // Bit mask of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Msk = 0x3ffffff + // Position of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET0_PERIOD_MODE. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE = 0x40000000 + // Position of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET0_TIMER_UNIT_SEL. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL = 0x80000000 + + // TARGET1_CONF: system timer comp1 target mode register + // Position of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Pos = 0x0 + // Bit mask of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Msk = 0x3ffffff + // Position of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET1_PERIOD_MODE. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE = 0x40000000 + // Position of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET1_TIMER_UNIT_SEL. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL = 0x80000000 + + // TARGET2_CONF: system timer comp2 target mode register + // Position of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Pos = 0x0 + // Bit mask of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Msk = 0x3ffffff + // Position of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET2_PERIOD_MODE. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE = 0x40000000 + // Position of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET2_TIMER_UNIT_SEL. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL = 0x80000000 + + // UNIT0_VALUE_HI: system timer unit0 value high register + // Position of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Msk = 0xfffff + + // UNIT0_VALUE_LO: system timer unit0 value low register + // Position of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Msk = 0xffffffff + + // UNIT1_VALUE_HI: system timer unit1 value high register + // Position of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Msk = 0xfffff + + // UNIT1_VALUE_LO: system timer unit1 value low register + // Position of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Msk = 0xffffffff + + // COMP0_LOAD: system timer comp0 conf sync register + // Position of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Msk = 0x1 + // Bit TIMER_COMP0_LOAD. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD = 0x1 + + // COMP1_LOAD: system timer comp1 conf sync register + // Position of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Msk = 0x1 + // Bit TIMER_COMP1_LOAD. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD = 0x1 + + // COMP2_LOAD: system timer comp2 conf sync register + // Position of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Msk = 0x1 + // Bit TIMER_COMP2_LOAD. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD = 0x1 + + // UNIT0_LOAD: system timer unit0 conf sync register + // Position of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Msk = 0x1 + // Bit TIMER_UNIT0_LOAD. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD = 0x1 + + // UNIT1_LOAD: system timer unit1 conf sync register + // Position of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Msk = 0x1 + // Bit TIMER_UNIT1_LOAD. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD = 0x1 + + // INT_ENA: systimer interrupt enable register + // Position of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Pos = 0x0 + // Bit mask of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Msk = 0x1 + // Bit TARGET0_INT_ENA. + SYSTIMER_INT_ENA_TARGET0_INT_ENA = 0x1 + // Position of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Pos = 0x1 + // Bit mask of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Msk = 0x2 + // Bit TARGET1_INT_ENA. + SYSTIMER_INT_ENA_TARGET1_INT_ENA = 0x2 + // Position of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Pos = 0x2 + // Bit mask of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Msk = 0x4 + // Bit TARGET2_INT_ENA. + SYSTIMER_INT_ENA_TARGET2_INT_ENA = 0x4 + + // INT_RAW: systimer interrupt raw register + // Position of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Pos = 0x0 + // Bit mask of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Msk = 0x1 + // Bit TARGET0_INT_RAW. + SYSTIMER_INT_RAW_TARGET0_INT_RAW = 0x1 + // Position of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Pos = 0x1 + // Bit mask of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Msk = 0x2 + // Bit TARGET1_INT_RAW. + SYSTIMER_INT_RAW_TARGET1_INT_RAW = 0x2 + // Position of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Pos = 0x2 + // Bit mask of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Msk = 0x4 + // Bit TARGET2_INT_RAW. + SYSTIMER_INT_RAW_TARGET2_INT_RAW = 0x4 + + // INT_CLR: systimer interrupt clear register + // Position of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Pos = 0x0 + // Bit mask of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Msk = 0x1 + // Bit TARGET0_INT_CLR. + SYSTIMER_INT_CLR_TARGET0_INT_CLR = 0x1 + // Position of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Pos = 0x1 + // Bit mask of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Msk = 0x2 + // Bit TARGET1_INT_CLR. + SYSTIMER_INT_CLR_TARGET1_INT_CLR = 0x2 + // Position of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Pos = 0x2 + // Bit mask of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Msk = 0x4 + // Bit TARGET2_INT_CLR. + SYSTIMER_INT_CLR_TARGET2_INT_CLR = 0x4 + + // INT_ST: systimer interrupt status register + // Position of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Pos = 0x0 + // Bit mask of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Msk = 0x1 + // Bit TARGET0_INT_ST. + SYSTIMER_INT_ST_TARGET0_INT_ST = 0x1 + // Position of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Pos = 0x1 + // Bit mask of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Msk = 0x2 + // Bit TARGET1_INT_ST. + SYSTIMER_INT_ST_TARGET1_INT_ST = 0x2 + // Position of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Pos = 0x2 + // Bit mask of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Msk = 0x4 + // Bit TARGET2_INT_ST. + SYSTIMER_INT_ST_TARGET2_INT_ST = 0x4 + + // REAL_TARGET0_LO: system timer comp0 actual target value low register + // Position of TARGET0_LO_RO field. + SYSTIMER_REAL_TARGET0_LO_TARGET0_LO_RO_Pos = 0x0 + // Bit mask of TARGET0_LO_RO field. + SYSTIMER_REAL_TARGET0_LO_TARGET0_LO_RO_Msk = 0xffffffff + + // REAL_TARGET0_HI: system timer comp0 actual target value high register + // Position of TARGET0_HI_RO field. + SYSTIMER_REAL_TARGET0_HI_TARGET0_HI_RO_Pos = 0x0 + // Bit mask of TARGET0_HI_RO field. + SYSTIMER_REAL_TARGET0_HI_TARGET0_HI_RO_Msk = 0xfffff + + // REAL_TARGET1_LO: system timer comp1 actual target value low register + // Position of TARGET1_LO_RO field. + SYSTIMER_REAL_TARGET1_LO_TARGET1_LO_RO_Pos = 0x0 + // Bit mask of TARGET1_LO_RO field. + SYSTIMER_REAL_TARGET1_LO_TARGET1_LO_RO_Msk = 0xffffffff + + // REAL_TARGET1_HI: system timer comp1 actual target value high register + // Position of TARGET1_HI_RO field. + SYSTIMER_REAL_TARGET1_HI_TARGET1_HI_RO_Pos = 0x0 + // Bit mask of TARGET1_HI_RO field. + SYSTIMER_REAL_TARGET1_HI_TARGET1_HI_RO_Msk = 0xfffff + + // REAL_TARGET2_LO: system timer comp2 actual target value low register + // Position of TARGET2_LO_RO field. + SYSTIMER_REAL_TARGET2_LO_TARGET2_LO_RO_Pos = 0x0 + // Bit mask of TARGET2_LO_RO field. + SYSTIMER_REAL_TARGET2_LO_TARGET2_LO_RO_Msk = 0xffffffff + + // REAL_TARGET2_HI: system timer comp2 actual target value high register + // Position of TARGET2_HI_RO field. + SYSTIMER_REAL_TARGET2_HI_TARGET2_HI_RO_Pos = 0x0 + // Bit mask of TARGET2_HI_RO field. + SYSTIMER_REAL_TARGET2_HI_TARGET2_HI_RO_Msk = 0xfffff + + // DATE: system timer version control register + // Position of DATE field. + SYSTIMER_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SYSTIMER_DATE_DATE_Msk = 0xffffffff +) + +// Constants for TEE: TEE Peripheral +const ( + // M0_MODE_CTRL: Tee mode control register + // Position of M0_MODE field. + TEE_M0_MODE_CTRL_M0_MODE_Pos = 0x0 + // Bit mask of M0_MODE field. + TEE_M0_MODE_CTRL_M0_MODE_Msk = 0x3 + + // M1_MODE_CTRL: Tee mode control register + // Position of M1_MODE field. + TEE_M1_MODE_CTRL_M1_MODE_Pos = 0x0 + // Bit mask of M1_MODE field. + TEE_M1_MODE_CTRL_M1_MODE_Msk = 0x3 + + // M2_MODE_CTRL: Tee mode control register + // Position of M2_MODE field. + TEE_M2_MODE_CTRL_M2_MODE_Pos = 0x0 + // Bit mask of M2_MODE field. + TEE_M2_MODE_CTRL_M2_MODE_Msk = 0x3 + + // M3_MODE_CTRL: Tee mode control register + // Position of M3_MODE field. + TEE_M3_MODE_CTRL_M3_MODE_Pos = 0x0 + // Bit mask of M3_MODE field. + TEE_M3_MODE_CTRL_M3_MODE_Msk = 0x3 + + // M4_MODE_CTRL: Tee mode control register + // Position of M4_MODE field. + TEE_M4_MODE_CTRL_M4_MODE_Pos = 0x0 + // Bit mask of M4_MODE field. + TEE_M4_MODE_CTRL_M4_MODE_Msk = 0x3 + + // M5_MODE_CTRL: Tee mode control register + // Position of M5_MODE field. + TEE_M5_MODE_CTRL_M5_MODE_Pos = 0x0 + // Bit mask of M5_MODE field. + TEE_M5_MODE_CTRL_M5_MODE_Msk = 0x3 + + // M6_MODE_CTRL: Tee mode control register + // Position of M6_MODE field. + TEE_M6_MODE_CTRL_M6_MODE_Pos = 0x0 + // Bit mask of M6_MODE field. + TEE_M6_MODE_CTRL_M6_MODE_Msk = 0x3 + + // M7_MODE_CTRL: Tee mode control register + // Position of M7_MODE field. + TEE_M7_MODE_CTRL_M7_MODE_Pos = 0x0 + // Bit mask of M7_MODE field. + TEE_M7_MODE_CTRL_M7_MODE_Msk = 0x3 + + // M8_MODE_CTRL: Tee mode control register + // Position of M8_MODE field. + TEE_M8_MODE_CTRL_M8_MODE_Pos = 0x0 + // Bit mask of M8_MODE field. + TEE_M8_MODE_CTRL_M8_MODE_Msk = 0x3 + + // M9_MODE_CTRL: Tee mode control register + // Position of M9_MODE field. + TEE_M9_MODE_CTRL_M9_MODE_Pos = 0x0 + // Bit mask of M9_MODE field. + TEE_M9_MODE_CTRL_M9_MODE_Msk = 0x3 + + // M10_MODE_CTRL: Tee mode control register + // Position of M10_MODE field. + TEE_M10_MODE_CTRL_M10_MODE_Pos = 0x0 + // Bit mask of M10_MODE field. + TEE_M10_MODE_CTRL_M10_MODE_Msk = 0x3 + + // M11_MODE_CTRL: Tee mode control register + // Position of M11_MODE field. + TEE_M11_MODE_CTRL_M11_MODE_Pos = 0x0 + // Bit mask of M11_MODE field. + TEE_M11_MODE_CTRL_M11_MODE_Msk = 0x3 + + // M12_MODE_CTRL: Tee mode control register + // Position of M12_MODE field. + TEE_M12_MODE_CTRL_M12_MODE_Pos = 0x0 + // Bit mask of M12_MODE field. + TEE_M12_MODE_CTRL_M12_MODE_Msk = 0x3 + + // M13_MODE_CTRL: Tee mode control register + // Position of M13_MODE field. + TEE_M13_MODE_CTRL_M13_MODE_Pos = 0x0 + // Bit mask of M13_MODE field. + TEE_M13_MODE_CTRL_M13_MODE_Msk = 0x3 + + // M14_MODE_CTRL: Tee mode control register + // Position of M14_MODE field. + TEE_M14_MODE_CTRL_M14_MODE_Pos = 0x0 + // Bit mask of M14_MODE field. + TEE_M14_MODE_CTRL_M14_MODE_Msk = 0x3 + + // M15_MODE_CTRL: Tee mode control register + // Position of M15_MODE field. + TEE_M15_MODE_CTRL_M15_MODE_Pos = 0x0 + // Bit mask of M15_MODE field. + TEE_M15_MODE_CTRL_M15_MODE_Msk = 0x3 + + // M16_MODE_CTRL: Tee mode control register + // Position of M16_MODE field. + TEE_M16_MODE_CTRL_M16_MODE_Pos = 0x0 + // Bit mask of M16_MODE field. + TEE_M16_MODE_CTRL_M16_MODE_Msk = 0x3 + + // M17_MODE_CTRL: Tee mode control register + // Position of M17_MODE field. + TEE_M17_MODE_CTRL_M17_MODE_Pos = 0x0 + // Bit mask of M17_MODE field. + TEE_M17_MODE_CTRL_M17_MODE_Msk = 0x3 + + // M18_MODE_CTRL: Tee mode control register + // Position of M18_MODE field. + TEE_M18_MODE_CTRL_M18_MODE_Pos = 0x0 + // Bit mask of M18_MODE field. + TEE_M18_MODE_CTRL_M18_MODE_Msk = 0x3 + + // M19_MODE_CTRL: Tee mode control register + // Position of M19_MODE field. + TEE_M19_MODE_CTRL_M19_MODE_Pos = 0x0 + // Bit mask of M19_MODE field. + TEE_M19_MODE_CTRL_M19_MODE_Msk = 0x3 + + // M20_MODE_CTRL: Tee mode control register + // Position of M20_MODE field. + TEE_M20_MODE_CTRL_M20_MODE_Pos = 0x0 + // Bit mask of M20_MODE field. + TEE_M20_MODE_CTRL_M20_MODE_Msk = 0x3 + + // M21_MODE_CTRL: Tee mode control register + // Position of M21_MODE field. + TEE_M21_MODE_CTRL_M21_MODE_Pos = 0x0 + // Bit mask of M21_MODE field. + TEE_M21_MODE_CTRL_M21_MODE_Msk = 0x3 + + // M22_MODE_CTRL: Tee mode control register + // Position of M22_MODE field. + TEE_M22_MODE_CTRL_M22_MODE_Pos = 0x0 + // Bit mask of M22_MODE field. + TEE_M22_MODE_CTRL_M22_MODE_Msk = 0x3 + + // M23_MODE_CTRL: Tee mode control register + // Position of M23_MODE field. + TEE_M23_MODE_CTRL_M23_MODE_Pos = 0x0 + // Bit mask of M23_MODE field. + TEE_M23_MODE_CTRL_M23_MODE_Msk = 0x3 + + // M24_MODE_CTRL: Tee mode control register + // Position of M24_MODE field. + TEE_M24_MODE_CTRL_M24_MODE_Pos = 0x0 + // Bit mask of M24_MODE field. + TEE_M24_MODE_CTRL_M24_MODE_Msk = 0x3 + + // M25_MODE_CTRL: Tee mode control register + // Position of M25_MODE field. + TEE_M25_MODE_CTRL_M25_MODE_Pos = 0x0 + // Bit mask of M25_MODE field. + TEE_M25_MODE_CTRL_M25_MODE_Msk = 0x3 + + // M26_MODE_CTRL: Tee mode control register + // Position of M26_MODE field. + TEE_M26_MODE_CTRL_M26_MODE_Pos = 0x0 + // Bit mask of M26_MODE field. + TEE_M26_MODE_CTRL_M26_MODE_Msk = 0x3 + + // M27_MODE_CTRL: Tee mode control register + // Position of M27_MODE field. + TEE_M27_MODE_CTRL_M27_MODE_Pos = 0x0 + // Bit mask of M27_MODE field. + TEE_M27_MODE_CTRL_M27_MODE_Msk = 0x3 + + // M28_MODE_CTRL: Tee mode control register + // Position of M28_MODE field. + TEE_M28_MODE_CTRL_M28_MODE_Pos = 0x0 + // Bit mask of M28_MODE field. + TEE_M28_MODE_CTRL_M28_MODE_Msk = 0x3 + + // M29_MODE_CTRL: Tee mode control register + // Position of M29_MODE field. + TEE_M29_MODE_CTRL_M29_MODE_Pos = 0x0 + // Bit mask of M29_MODE field. + TEE_M29_MODE_CTRL_M29_MODE_Msk = 0x3 + + // M30_MODE_CTRL: Tee mode control register + // Position of M30_MODE field. + TEE_M30_MODE_CTRL_M30_MODE_Pos = 0x0 + // Bit mask of M30_MODE field. + TEE_M30_MODE_CTRL_M30_MODE_Msk = 0x3 + + // M31_MODE_CTRL: Tee mode control register + // Position of M31_MODE field. + TEE_M31_MODE_CTRL_M31_MODE_Pos = 0x0 + // Bit mask of M31_MODE field. + TEE_M31_MODE_CTRL_M31_MODE_Msk = 0x3 + + // CLOCK_GATE: Clock gating register + // Position of CLK_EN field. + TEE_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + TEE_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + TEE_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + TEE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + TEE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for TIMG0: Timer Group 0 +const ( + // T0CONFIG: Timer %s configuration register + // Position of USE_XTAL field. + TIMG_T0CONFIG_USE_XTAL_Pos = 0x9 + // Bit mask of USE_XTAL field. + TIMG_T0CONFIG_USE_XTAL_Msk = 0x200 + // Bit USE_XTAL. + TIMG_T0CONFIG_USE_XTAL = 0x200 + // Position of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Pos = 0xa + // Bit mask of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Msk = 0x400 + // Bit ALARM_EN. + TIMG_T0CONFIG_ALARM_EN = 0x400 + // Position of DIVCNT_RST field. + TIMG_T0CONFIG_DIVCNT_RST_Pos = 0xc + // Bit mask of DIVCNT_RST field. + TIMG_T0CONFIG_DIVCNT_RST_Msk = 0x1000 + // Bit DIVCNT_RST. + TIMG_T0CONFIG_DIVCNT_RST = 0x1000 + // Position of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Pos = 0xd + // Bit mask of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Msk = 0x1fffe000 + // Position of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Pos = 0x1d + // Bit mask of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Msk = 0x20000000 + // Bit AUTORELOAD. + TIMG_T0CONFIG_AUTORELOAD = 0x20000000 + // Position of INCREASE field. + TIMG_T0CONFIG_INCREASE_Pos = 0x1e + // Bit mask of INCREASE field. + TIMG_T0CONFIG_INCREASE_Msk = 0x40000000 + // Bit INCREASE. + TIMG_T0CONFIG_INCREASE = 0x40000000 + // Position of EN field. + TIMG_T0CONFIG_EN_Pos = 0x1f + // Bit mask of EN field. + TIMG_T0CONFIG_EN_Msk = 0x80000000 + // Bit EN. + TIMG_T0CONFIG_EN = 0x80000000 + + // T0LO: Timer %s current value, low 32 bits + // Position of LO field. + TIMG_T0LO_LO_Pos = 0x0 + // Bit mask of LO field. + TIMG_T0LO_LO_Msk = 0xffffffff + + // T0HI: Timer %s current value, high 22 bits + // Position of HI field. + TIMG_T0HI_HI_Pos = 0x0 + // Bit mask of HI field. + TIMG_T0HI_HI_Msk = 0x3fffff + + // T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + // Position of UPDATE field. + TIMG_T0UPDATE_UPDATE_Pos = 0x1f + // Bit mask of UPDATE field. + TIMG_T0UPDATE_UPDATE_Msk = 0x80000000 + // Bit UPDATE. + TIMG_T0UPDATE_UPDATE = 0x80000000 + + // T0ALARMLO: Timer %s alarm value, low 32 bits + // Position of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Pos = 0x0 + // Bit mask of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Msk = 0xffffffff + + // T0ALARMHI: Timer %s alarm value, high bits + // Position of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Pos = 0x0 + // Bit mask of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Msk = 0x3fffff + + // T0LOADLO: Timer %s reload value, low 32 bits + // Position of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Pos = 0x0 + // Bit mask of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Msk = 0xffffffff + + // T0LOADHI: Timer %s reload value, high 22 bits + // Position of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Pos = 0x0 + // Bit mask of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Msk = 0x3fffff + + // T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + // Position of LOAD field. + TIMG_T0LOAD_LOAD_Pos = 0x0 + // Bit mask of LOAD field. + TIMG_T0LOAD_LOAD_Msk = 0xffffffff + + // WDTCONFIG0: Watchdog timer configuration register + // Position of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xc + // Bit mask of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x1000 + // Bit WDT_APPCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x1000 + // Position of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xd + // Bit mask of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x2000 + // Bit WDT_PROCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x2000 + // Position of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xe + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x4000 + // Bit WDT_FLASHBOOT_MOD_EN. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x4000 + // Position of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xf + // Bit mask of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0x38000 + // Position of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x12 + // Bit mask of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x1c0000 + // Position of WDT_USE_XTAL field. + TIMG_WDTCONFIG0_WDT_USE_XTAL_Pos = 0x15 + // Bit mask of WDT_USE_XTAL field. + TIMG_WDTCONFIG0_WDT_USE_XTAL_Msk = 0x200000 + // Bit WDT_USE_XTAL. + TIMG_WDTCONFIG0_WDT_USE_XTAL = 0x200000 + // Position of WDT_CONF_UPDATE_EN field. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Pos = 0x16 + // Bit mask of WDT_CONF_UPDATE_EN field. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Msk = 0x400000 + // Bit WDT_CONF_UPDATE_EN. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN = 0x400000 + // Position of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Pos = 0x17 + // Bit mask of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Msk = 0x1800000 + // Position of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Pos = 0x19 + // Bit mask of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Msk = 0x6000000 + // Position of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Pos = 0x1b + // Bit mask of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Msk = 0x18000000 + // Position of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Pos = 0x1d + // Bit mask of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Msk = 0x60000000 + // Position of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + TIMG_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: Watchdog timer prescaler register + // Position of WDT_DIVCNT_RST field. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Pos = 0x0 + // Bit mask of WDT_DIVCNT_RST field. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Msk = 0x1 + // Bit WDT_DIVCNT_RST. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST = 0x1 + // Position of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Pos = 0x10 + // Bit mask of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Msk = 0xffff0000 + + // WDTCONFIG2: Watchdog timer stage 0 timeout value + // Position of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: Watchdog timer stage 1 timeout value + // Position of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: Watchdog timer stage 2 timeout value + // Position of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG5: Watchdog timer stage 3 timeout value + // Position of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: Write to feed the watchdog timer + // Position of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Pos = 0x0 + // Bit mask of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Msk = 0xffffffff + + // WDTWPROTECT: Watchdog write protect register + // Position of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // RTCCALICFG: RTC calibration configure register + // Position of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Pos = 0xc + // Bit mask of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Msk = 0x1000 + // Bit RTC_CALI_START_CYCLING. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING = 0x1000 + // Position of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Pos = 0xd + // Bit mask of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Msk = 0x6000 + // Position of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Pos = 0xf + // Bit mask of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Msk = 0x8000 + // Bit RTC_CALI_RDY. + TIMG_RTCCALICFG_RTC_CALI_RDY = 0x8000 + // Position of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Pos = 0x10 + // Bit mask of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Msk = 0x7fff0000 + // Position of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Pos = 0x1f + // Bit mask of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Msk = 0x80000000 + // Bit RTC_CALI_START. + TIMG_RTCCALICFG_RTC_CALI_START = 0x80000000 + + // RTCCALICFG1: RTC calibration configure1 register + // Position of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Pos = 0x0 + // Bit mask of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Msk = 0x1 + // Bit RTC_CALI_CYCLING_DATA_VLD. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD = 0x1 + // Position of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Pos = 0x7 + // Bit mask of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Msk = 0xffffff80 + + // INT_ENA_TIMERS: Interrupt enable bits + // Position of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Pos = 0x0 + // Bit mask of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Msk = 0x1 + // Bit T0_INT_ENA. + TIMG_INT_ENA_TIMERS_T0_INT_ENA = 0x1 + // Position of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Pos = 0x1 + // Bit mask of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Msk = 0x2 + // Bit WDT_INT_ENA. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA = 0x2 + + // INT_RAW_TIMERS: Raw interrupt status + // Position of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Pos = 0x0 + // Bit mask of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Msk = 0x1 + // Bit T0_INT_RAW. + TIMG_INT_RAW_TIMERS_T0_INT_RAW = 0x1 + // Position of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Pos = 0x1 + // Bit mask of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Msk = 0x2 + // Bit WDT_INT_RAW. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW = 0x2 + + // INT_ST_TIMERS: Masked interrupt status + // Position of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Pos = 0x0 + // Bit mask of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Msk = 0x1 + // Bit T0_INT_ST. + TIMG_INT_ST_TIMERS_T0_INT_ST = 0x1 + // Position of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Pos = 0x1 + // Bit mask of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Msk = 0x2 + // Bit WDT_INT_ST. + TIMG_INT_ST_TIMERS_WDT_INT_ST = 0x2 + + // INT_CLR_TIMERS: Interrupt clear bits + // Position of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Pos = 0x0 + // Bit mask of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Msk = 0x1 + // Bit T0_INT_CLR. + TIMG_INT_CLR_TIMERS_T0_INT_CLR = 0x1 + // Position of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Pos = 0x1 + // Bit mask of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Msk = 0x2 + // Bit WDT_INT_CLR. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR = 0x2 + + // RTCCALICFG2: Timer group calibration register + // Position of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Pos = 0x0 + // Bit mask of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Msk = 0x1 + // Bit RTC_CALI_TIMEOUT. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT = 0x1 + // Position of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Pos = 0x3 + // Bit mask of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Msk = 0x78 + // Position of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Pos = 0x7 + // Bit mask of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Msk = 0xffffff80 + + // NTIMERS_DATE: Timer version control register + // Position of NTIMGS_DATE field. + TIMG_NTIMERS_DATE_NTIMGS_DATE_Pos = 0x0 + // Bit mask of NTIMGS_DATE field. + TIMG_NTIMERS_DATE_NTIMGS_DATE_Msk = 0xfffffff + + // REGCLK: Timer group clock gate register + // Position of ETM_EN field. + TIMG_REGCLK_ETM_EN_Pos = 0x1c + // Bit mask of ETM_EN field. + TIMG_REGCLK_ETM_EN_Msk = 0x10000000 + // Bit ETM_EN. + TIMG_REGCLK_ETM_EN = 0x10000000 + // Position of WDT_CLK_IS_ACTIVE field. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Pos = 0x1d + // Bit mask of WDT_CLK_IS_ACTIVE field. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Msk = 0x20000000 + // Bit WDT_CLK_IS_ACTIVE. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE = 0x20000000 + // Position of TIMER_CLK_IS_ACTIVE field. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Pos = 0x1e + // Bit mask of TIMER_CLK_IS_ACTIVE field. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Msk = 0x40000000 + // Bit TIMER_CLK_IS_ACTIVE. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE = 0x40000000 + // Position of CLK_EN field. + TIMG_REGCLK_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + TIMG_REGCLK_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + TIMG_REGCLK_CLK_EN = 0x80000000 +) + +// Constants for TRACE: RISC-V Trace Encoder +const ( + // MEM_START_ADDR: mem start addr + // Position of MEM_STAET_ADDR field. + TRACE_MEM_START_ADDR_MEM_STAET_ADDR_Pos = 0x0 + // Bit mask of MEM_STAET_ADDR field. + TRACE_MEM_START_ADDR_MEM_STAET_ADDR_Msk = 0xffffffff + + // MEM_END_ADDR: mem end addr + // Position of MEM_END_ADDR field. + TRACE_MEM_END_ADDR_MEM_END_ADDR_Pos = 0x0 + // Bit mask of MEM_END_ADDR field. + TRACE_MEM_END_ADDR_MEM_END_ADDR_Msk = 0xffffffff + + // MEM_CURRENT_ADDR: mem current addr + // Position of MEM_CURRENT_ADDR field. + TRACE_MEM_CURRENT_ADDR_MEM_CURRENT_ADDR_Pos = 0x0 + // Bit mask of MEM_CURRENT_ADDR field. + TRACE_MEM_CURRENT_ADDR_MEM_CURRENT_ADDR_Msk = 0xffffffff + + // MEM_ADDR_UPDATE: mem addr update + // Position of MEM_CURRENT_ADDR_UPDATE field. + TRACE_MEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE_Pos = 0x0 + // Bit mask of MEM_CURRENT_ADDR_UPDATE field. + TRACE_MEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE_Msk = 0x1 + // Bit MEM_CURRENT_ADDR_UPDATE. + TRACE_MEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE = 0x1 + + // FIFO_STATUS: fifo status register + // Position of FIFO_EMPTY field. + TRACE_FIFO_STATUS_FIFO_EMPTY_Pos = 0x0 + // Bit mask of FIFO_EMPTY field. + TRACE_FIFO_STATUS_FIFO_EMPTY_Msk = 0x1 + // Bit FIFO_EMPTY. + TRACE_FIFO_STATUS_FIFO_EMPTY = 0x1 + // Position of WORK_STATUS field. + TRACE_FIFO_STATUS_WORK_STATUS_Pos = 0x1 + // Bit mask of WORK_STATUS field. + TRACE_FIFO_STATUS_WORK_STATUS_Msk = 0x2 + // Bit WORK_STATUS. + TRACE_FIFO_STATUS_WORK_STATUS = 0x2 + + // INTR_ENA: interrupt enable register + // Position of FIFO_OVERFLOW_INTR_ENA field. + TRACE_INTR_ENA_FIFO_OVERFLOW_INTR_ENA_Pos = 0x0 + // Bit mask of FIFO_OVERFLOW_INTR_ENA field. + TRACE_INTR_ENA_FIFO_OVERFLOW_INTR_ENA_Msk = 0x1 + // Bit FIFO_OVERFLOW_INTR_ENA. + TRACE_INTR_ENA_FIFO_OVERFLOW_INTR_ENA = 0x1 + // Position of MEM_FULL_INTR_ENA field. + TRACE_INTR_ENA_MEM_FULL_INTR_ENA_Pos = 0x1 + // Bit mask of MEM_FULL_INTR_ENA field. + TRACE_INTR_ENA_MEM_FULL_INTR_ENA_Msk = 0x2 + // Bit MEM_FULL_INTR_ENA. + TRACE_INTR_ENA_MEM_FULL_INTR_ENA = 0x2 + + // INTR_RAW: interrupt status register + // Position of FIFO_OVERFLOW_INTR_RAW field. + TRACE_INTR_RAW_FIFO_OVERFLOW_INTR_RAW_Pos = 0x0 + // Bit mask of FIFO_OVERFLOW_INTR_RAW field. + TRACE_INTR_RAW_FIFO_OVERFLOW_INTR_RAW_Msk = 0x1 + // Bit FIFO_OVERFLOW_INTR_RAW. + TRACE_INTR_RAW_FIFO_OVERFLOW_INTR_RAW = 0x1 + // Position of MEM_FULL_INTR_RAW field. + TRACE_INTR_RAW_MEM_FULL_INTR_RAW_Pos = 0x1 + // Bit mask of MEM_FULL_INTR_RAW field. + TRACE_INTR_RAW_MEM_FULL_INTR_RAW_Msk = 0x2 + // Bit MEM_FULL_INTR_RAW. + TRACE_INTR_RAW_MEM_FULL_INTR_RAW = 0x2 + + // INTR_CLR: interrupt clear register + // Position of FIFO_OVERFLOW_INTR_CLR field. + TRACE_INTR_CLR_FIFO_OVERFLOW_INTR_CLR_Pos = 0x0 + // Bit mask of FIFO_OVERFLOW_INTR_CLR field. + TRACE_INTR_CLR_FIFO_OVERFLOW_INTR_CLR_Msk = 0x1 + // Bit FIFO_OVERFLOW_INTR_CLR. + TRACE_INTR_CLR_FIFO_OVERFLOW_INTR_CLR = 0x1 + // Position of MEM_FULL_INTR_CLR field. + TRACE_INTR_CLR_MEM_FULL_INTR_CLR_Pos = 0x1 + // Bit mask of MEM_FULL_INTR_CLR field. + TRACE_INTR_CLR_MEM_FULL_INTR_CLR_Msk = 0x2 + // Bit MEM_FULL_INTR_CLR. + TRACE_INTR_CLR_MEM_FULL_INTR_CLR = 0x2 + + // TRIGGER: trigger register + // Position of ON field. + TRACE_TRIGGER_ON_Pos = 0x0 + // Bit mask of ON field. + TRACE_TRIGGER_ON_Msk = 0x1 + // Bit ON. + TRACE_TRIGGER_ON = 0x1 + // Position of OFF field. + TRACE_TRIGGER_OFF_Pos = 0x1 + // Bit mask of OFF field. + TRACE_TRIGGER_OFF_Msk = 0x2 + // Bit OFF. + TRACE_TRIGGER_OFF = 0x2 + // Position of MEM_LOOP field. + TRACE_TRIGGER_MEM_LOOP_Pos = 0x2 + // Bit mask of MEM_LOOP field. + TRACE_TRIGGER_MEM_LOOP_Msk = 0x4 + // Bit MEM_LOOP. + TRACE_TRIGGER_MEM_LOOP = 0x4 + // Position of RESTART_ENA field. + TRACE_TRIGGER_RESTART_ENA_Pos = 0x3 + // Bit mask of RESTART_ENA field. + TRACE_TRIGGER_RESTART_ENA_Msk = 0x8 + // Bit RESTART_ENA. + TRACE_TRIGGER_RESTART_ENA = 0x8 + + // RESYNC_PROLONGED: resync configuration register + // Position of RESYNC_PROLONGED field. + TRACE_RESYNC_PROLONGED_RESYNC_PROLONGED_Pos = 0x0 + // Bit mask of RESYNC_PROLONGED field. + TRACE_RESYNC_PROLONGED_RESYNC_PROLONGED_Msk = 0xffffff + // Position of RESYNC_MODE field. + TRACE_RESYNC_PROLONGED_RESYNC_MODE_Pos = 0x18 + // Bit mask of RESYNC_MODE field. + TRACE_RESYNC_PROLONGED_RESYNC_MODE_Msk = 0x1000000 + // Bit RESYNC_MODE. + TRACE_RESYNC_PROLONGED_RESYNC_MODE = 0x1000000 + + // CLOCK_GATE: Clock gate control register + // Position of CLK_EN field. + TRACE_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + TRACE_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + TRACE_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version control register + // Position of DATE field. + TRACE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + TRACE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for TWAI0: Two-Wire Automotive Interface +const ( + // MODE: TWAI mode register. + // Position of RESET_MODE field. + TWAI_MODE_RESET_MODE_Pos = 0x0 + // Bit mask of RESET_MODE field. + TWAI_MODE_RESET_MODE_Msk = 0x1 + // Bit RESET_MODE. + TWAI_MODE_RESET_MODE = 0x1 + // Position of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Pos = 0x1 + // Bit mask of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Msk = 0x2 + // Bit LISTEN_ONLY_MODE. + TWAI_MODE_LISTEN_ONLY_MODE = 0x2 + // Position of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Pos = 0x2 + // Bit mask of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Msk = 0x4 + // Bit SELF_TEST_MODE. + TWAI_MODE_SELF_TEST_MODE = 0x4 + // Position of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Pos = 0x3 + // Bit mask of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Msk = 0x8 + // Bit RX_FILTER_MODE. + TWAI_MODE_RX_FILTER_MODE = 0x8 + + // CMD: TWAI command register. + // Position of TX_REQ field. + TWAI_CMD_TX_REQ_Pos = 0x0 + // Bit mask of TX_REQ field. + TWAI_CMD_TX_REQ_Msk = 0x1 + // Bit TX_REQ. + TWAI_CMD_TX_REQ = 0x1 + // Position of ABORT_TX field. + TWAI_CMD_ABORT_TX_Pos = 0x1 + // Bit mask of ABORT_TX field. + TWAI_CMD_ABORT_TX_Msk = 0x2 + // Bit ABORT_TX. + TWAI_CMD_ABORT_TX = 0x2 + // Position of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Pos = 0x2 + // Bit mask of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Msk = 0x4 + // Bit RELEASE_BUF. + TWAI_CMD_RELEASE_BUF = 0x4 + // Position of CLEAR_DATA_OVERRUN field. + TWAI_CMD_CLEAR_DATA_OVERRUN_Pos = 0x3 + // Bit mask of CLEAR_DATA_OVERRUN field. + TWAI_CMD_CLEAR_DATA_OVERRUN_Msk = 0x8 + // Bit CLEAR_DATA_OVERRUN. + TWAI_CMD_CLEAR_DATA_OVERRUN = 0x8 + // Position of SELF_RX_REQUEST field. + TWAI_CMD_SELF_RX_REQUEST_Pos = 0x4 + // Bit mask of SELF_RX_REQUEST field. + TWAI_CMD_SELF_RX_REQUEST_Msk = 0x10 + // Bit SELF_RX_REQUEST. + TWAI_CMD_SELF_RX_REQUEST = 0x10 + + // STATUS: TWAI status register. + // Position of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Pos = 0x0 + // Bit mask of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Msk = 0x1 + // Bit RX_BUF_ST. + TWAI_STATUS_RX_BUF_ST = 0x1 + // Position of OVERRUN field. + TWAI_STATUS_OVERRUN_Pos = 0x1 + // Bit mask of OVERRUN field. + TWAI_STATUS_OVERRUN_Msk = 0x2 + // Bit OVERRUN. + TWAI_STATUS_OVERRUN = 0x2 + // Position of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Pos = 0x2 + // Bit mask of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Msk = 0x4 + // Bit TX_BUF_ST. + TWAI_STATUS_TX_BUF_ST = 0x4 + // Position of TRANSMISSION_COMPLETE field. + TWAI_STATUS_TRANSMISSION_COMPLETE_Pos = 0x3 + // Bit mask of TRANSMISSION_COMPLETE field. + TWAI_STATUS_TRANSMISSION_COMPLETE_Msk = 0x8 + // Bit TRANSMISSION_COMPLETE. + TWAI_STATUS_TRANSMISSION_COMPLETE = 0x8 + // Position of RECEIVE field. + TWAI_STATUS_RECEIVE_Pos = 0x4 + // Bit mask of RECEIVE field. + TWAI_STATUS_RECEIVE_Msk = 0x10 + // Bit RECEIVE. + TWAI_STATUS_RECEIVE = 0x10 + // Position of TRANSMIT field. + TWAI_STATUS_TRANSMIT_Pos = 0x5 + // Bit mask of TRANSMIT field. + TWAI_STATUS_TRANSMIT_Msk = 0x20 + // Bit TRANSMIT. + TWAI_STATUS_TRANSMIT = 0x20 + // Position of ERR field. + TWAI_STATUS_ERR_Pos = 0x6 + // Bit mask of ERR field. + TWAI_STATUS_ERR_Msk = 0x40 + // Bit ERR. + TWAI_STATUS_ERR = 0x40 + // Position of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Pos = 0x7 + // Bit mask of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Msk = 0x80 + // Bit BUS_OFF_ST. + TWAI_STATUS_BUS_OFF_ST = 0x80 + // Position of MISS_ST field. + TWAI_STATUS_MISS_ST_Pos = 0x8 + // Bit mask of MISS_ST field. + TWAI_STATUS_MISS_ST_Msk = 0x100 + // Bit MISS_ST. + TWAI_STATUS_MISS_ST = 0x100 + + // INTERRUPT: Interrupt signals' register. + // Position of RECEIVE_INT_ST field. + TWAI_INTERRUPT_RECEIVE_INT_ST_Pos = 0x0 + // Bit mask of RECEIVE_INT_ST field. + TWAI_INTERRUPT_RECEIVE_INT_ST_Msk = 0x1 + // Bit RECEIVE_INT_ST. + TWAI_INTERRUPT_RECEIVE_INT_ST = 0x1 + // Position of TRANSMIT_INT_ST field. + TWAI_INTERRUPT_TRANSMIT_INT_ST_Pos = 0x1 + // Bit mask of TRANSMIT_INT_ST field. + TWAI_INTERRUPT_TRANSMIT_INT_ST_Msk = 0x2 + // Bit TRANSMIT_INT_ST. + TWAI_INTERRUPT_TRANSMIT_INT_ST = 0x2 + // Position of ERR_WARNING_INT_ST field. + TWAI_INTERRUPT_ERR_WARNING_INT_ST_Pos = 0x2 + // Bit mask of ERR_WARNING_INT_ST field. + TWAI_INTERRUPT_ERR_WARNING_INT_ST_Msk = 0x4 + // Bit ERR_WARNING_INT_ST. + TWAI_INTERRUPT_ERR_WARNING_INT_ST = 0x4 + // Position of DATA_OVERRUN_INT_ST field. + TWAI_INTERRUPT_DATA_OVERRUN_INT_ST_Pos = 0x3 + // Bit mask of DATA_OVERRUN_INT_ST field. + TWAI_INTERRUPT_DATA_OVERRUN_INT_ST_Msk = 0x8 + // Bit DATA_OVERRUN_INT_ST. + TWAI_INTERRUPT_DATA_OVERRUN_INT_ST = 0x8 + // Position of ERR_PASSIVE_INT_ST field. + TWAI_INTERRUPT_ERR_PASSIVE_INT_ST_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ST field. + TWAI_INTERRUPT_ERR_PASSIVE_INT_ST_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ST. + TWAI_INTERRUPT_ERR_PASSIVE_INT_ST = 0x20 + // Position of ARBITRATION_LOST_INT_ST field. + TWAI_INTERRUPT_ARBITRATION_LOST_INT_ST_Pos = 0x6 + // Bit mask of ARBITRATION_LOST_INT_ST field. + TWAI_INTERRUPT_ARBITRATION_LOST_INT_ST_Msk = 0x40 + // Bit ARBITRATION_LOST_INT_ST. + TWAI_INTERRUPT_ARBITRATION_LOST_INT_ST = 0x40 + // Position of BUS_ERR_INT_ST field. + TWAI_INTERRUPT_BUS_ERR_INT_ST_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ST field. + TWAI_INTERRUPT_BUS_ERR_INT_ST_Msk = 0x80 + // Bit BUS_ERR_INT_ST. + TWAI_INTERRUPT_BUS_ERR_INT_ST = 0x80 + // Position of IDLE_INT_ST field. + TWAI_INTERRUPT_IDLE_INT_ST_Pos = 0x8 + // Bit mask of IDLE_INT_ST field. + TWAI_INTERRUPT_IDLE_INT_ST_Msk = 0x100 + // Bit IDLE_INT_ST. + TWAI_INTERRUPT_IDLE_INT_ST = 0x100 + + // INTERRUPT_ENABLE: Interrupt enable register. + // Position of EXT_RECEIVE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA_Pos = 0x0 + // Bit mask of EXT_RECEIVE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA_Msk = 0x1 + // Bit EXT_RECEIVE_INT_ENA. + TWAI_INTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA = 0x1 + // Position of EXT_TRANSMIT_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA_Pos = 0x1 + // Bit mask of EXT_TRANSMIT_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA_Msk = 0x2 + // Bit EXT_TRANSMIT_INT_ENA. + TWAI_INTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA = 0x2 + // Position of EXT_ERR_WARNING_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA_Pos = 0x2 + // Bit mask of EXT_ERR_WARNING_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA_Msk = 0x4 + // Bit EXT_ERR_WARNING_INT_ENA. + TWAI_INTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA = 0x4 + // Position of EXT_DATA_OVERRUN_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA_Pos = 0x3 + // Bit mask of EXT_DATA_OVERRUN_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA_Msk = 0x8 + // Bit EXT_DATA_OVERRUN_INT_ENA. + TWAI_INTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA = 0x8 + // Position of ERR_PASSIVE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ENA. + TWAI_INTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA = 0x20 + // Position of ARBITRATION_LOST_INT_ENA field. + TWAI_INTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA_Pos = 0x6 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + TWAI_INTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA_Msk = 0x40 + // Bit ARBITRATION_LOST_INT_ENA. + TWAI_INTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA = 0x40 + // Position of BUS_ERR_INT_ENA field. + TWAI_INTERRUPT_ENABLE_BUS_ERR_INT_ENA_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ENA field. + TWAI_INTERRUPT_ENABLE_BUS_ERR_INT_ENA_Msk = 0x80 + // Bit BUS_ERR_INT_ENA. + TWAI_INTERRUPT_ENABLE_BUS_ERR_INT_ENA = 0x80 + // Position of IDLE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_IDLE_INT_ENA_Pos = 0x8 + // Bit mask of IDLE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_IDLE_INT_ENA_Msk = 0x100 + // Bit IDLE_INT_ENA. + TWAI_INTERRUPT_ENABLE_IDLE_INT_ENA = 0x100 + + // BUS_TIMING_0: Bit timing configuration register 0. + // Position of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Pos = 0x0 + // Bit mask of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Msk = 0x3fff + // Position of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Pos = 0xe + // Bit mask of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Msk = 0xc000 + + // BUS_TIMING_1: Bit timing configuration register 1. + // Position of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Pos = 0x0 + // Bit mask of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Msk = 0xf + // Position of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Pos = 0x4 + // Bit mask of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Msk = 0x70 + // Position of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Pos = 0x7 + // Bit mask of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Msk = 0x80 + // Bit TIME_SAMP. + TWAI_BUS_TIMING_1_TIME_SAMP = 0x80 + + // ARB_LOST_CAP: TWAI arbiter lost capture register. + // Position of ARBITRATION_LOST_CAPTURE field. + TWAI_ARB_LOST_CAP_ARBITRATION_LOST_CAPTURE_Pos = 0x0 + // Bit mask of ARBITRATION_LOST_CAPTURE field. + TWAI_ARB_LOST_CAP_ARBITRATION_LOST_CAPTURE_Msk = 0x1f + + // ERR_CODE_CAP: TWAI error info capture register. + // Position of ERR_CAPTURE_CODE_SEGMENT field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT_Pos = 0x0 + // Bit mask of ERR_CAPTURE_CODE_SEGMENT field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT_Msk = 0x1f + // Position of ERR_CAPTURE_CODE_DIRECTION field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION_Pos = 0x5 + // Bit mask of ERR_CAPTURE_CODE_DIRECTION field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION_Msk = 0x20 + // Bit ERR_CAPTURE_CODE_DIRECTION. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION = 0x20 + // Position of ERR_CAPTURE_CODE_TYPE field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE_Pos = 0x6 + // Bit mask of ERR_CAPTURE_CODE_TYPE field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE_Msk = 0xc0 + + // ERR_WARNING_LIMIT: TWAI error threshold configuration register. + // Position of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Pos = 0x0 + // Bit mask of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Msk = 0xff + + // RX_ERR_CNT: Rx error counter register. + // Position of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Pos = 0x0 + // Bit mask of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Msk = 0xff + + // TX_ERR_CNT: Tx error counter register. + // Position of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Pos = 0x0 + // Bit mask of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Msk = 0xff + + // DATA_0: Data register 0. + // Position of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Pos = 0x0 + // Bit mask of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Msk = 0xff + + // DATA_1: Data register 1. + // Position of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Pos = 0x0 + // Bit mask of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Msk = 0xff + + // DATA_2: Data register 2. + // Position of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Pos = 0x0 + // Bit mask of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Msk = 0xff + + // DATA_3: Data register 3. + // Position of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Pos = 0x0 + // Bit mask of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Msk = 0xff + + // DATA_4: Data register 4. + // Position of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Pos = 0x0 + // Bit mask of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Msk = 0xff + + // DATA_5: Data register 5. + // Position of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Pos = 0x0 + // Bit mask of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Msk = 0xff + + // DATA_6: Data register 6. + // Position of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Pos = 0x0 + // Bit mask of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Msk = 0xff + + // DATA_7: Data register 7. + // Position of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Pos = 0x0 + // Bit mask of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Msk = 0xff + + // DATA_8: Data register 8. + // Position of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Pos = 0x0 + // Bit mask of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Msk = 0xff + + // DATA_9: Data register 9. + // Position of DATA_9 field. + TWAI_DATA_9_DATA_9_Pos = 0x0 + // Bit mask of DATA_9 field. + TWAI_DATA_9_DATA_9_Msk = 0xff + + // DATA_10: Data register 10. + // Position of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Pos = 0x0 + // Bit mask of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Msk = 0xff + + // DATA_11: Data register 11. + // Position of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Pos = 0x0 + // Bit mask of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Msk = 0xff + + // DATA_12: Data register 12. + // Position of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Pos = 0x0 + // Bit mask of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Msk = 0xff + + // RX_MESSAGE_CNT: Received message counter register. + // Position of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Pos = 0x0 + // Bit mask of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Msk = 0x7f + + // CLOCK_DIVIDER: Clock divider register. + // Position of CD field. + TWAI_CLOCK_DIVIDER_CD_Pos = 0x0 + // Bit mask of CD field. + TWAI_CLOCK_DIVIDER_CD_Msk = 0xff + // Position of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Pos = 0x8 + // Bit mask of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Msk = 0x100 + // Bit CLOCK_OFF. + TWAI_CLOCK_DIVIDER_CLOCK_OFF = 0x100 + + // SW_STANDBY_CFG: Software configure standby pin directly. + // Position of SW_STANDBY_EN field. + TWAI_SW_STANDBY_CFG_SW_STANDBY_EN_Pos = 0x0 + // Bit mask of SW_STANDBY_EN field. + TWAI_SW_STANDBY_CFG_SW_STANDBY_EN_Msk = 0x1 + // Bit SW_STANDBY_EN. + TWAI_SW_STANDBY_CFG_SW_STANDBY_EN = 0x1 + // Position of SW_STANDBY_CLR field. + TWAI_SW_STANDBY_CFG_SW_STANDBY_CLR_Pos = 0x1 + // Bit mask of SW_STANDBY_CLR field. + TWAI_SW_STANDBY_CFG_SW_STANDBY_CLR_Msk = 0x2 + // Bit SW_STANDBY_CLR. + TWAI_SW_STANDBY_CFG_SW_STANDBY_CLR = 0x2 + + // HW_CFG: Hardware configure standby pin. + // Position of HW_STANDBY_EN field. + TWAI_HW_CFG_HW_STANDBY_EN_Pos = 0x0 + // Bit mask of HW_STANDBY_EN field. + TWAI_HW_CFG_HW_STANDBY_EN_Msk = 0x1 + // Bit HW_STANDBY_EN. + TWAI_HW_CFG_HW_STANDBY_EN = 0x1 + + // HW_STANDBY_CNT: Configure standby counter. + // Position of STANDBY_WAIT_CNT field. + TWAI_HW_STANDBY_CNT_STANDBY_WAIT_CNT_Pos = 0x0 + // Bit mask of STANDBY_WAIT_CNT field. + TWAI_HW_STANDBY_CNT_STANDBY_WAIT_CNT_Msk = 0xffffffff + + // IDLE_INTR_CNT: Configure idle interrupt counter. + // Position of IDLE_INTR_CNT field. + TWAI_IDLE_INTR_CNT_IDLE_INTR_CNT_Pos = 0x0 + // Bit mask of IDLE_INTR_CNT field. + TWAI_IDLE_INTR_CNT_IDLE_INTR_CNT_Msk = 0xffffffff + + // ECO_CFG: ECO configuration register. + // Position of RDN_ENA field. + TWAI_ECO_CFG_RDN_ENA_Pos = 0x0 + // Bit mask of RDN_ENA field. + TWAI_ECO_CFG_RDN_ENA_Msk = 0x1 + // Bit RDN_ENA. + TWAI_ECO_CFG_RDN_ENA = 0x1 + // Position of RDN_RESULT field. + TWAI_ECO_CFG_RDN_RESULT_Pos = 0x1 + // Bit mask of RDN_RESULT field. + TWAI_ECO_CFG_RDN_RESULT_Msk = 0x2 + // Bit RDN_RESULT. + TWAI_ECO_CFG_RDN_RESULT = 0x2 +) + +// Constants for UART0: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +const ( + // FIFO: FIFO data register + // Position of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9 + // Bit mask of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200 + // Bit SW_XON_INT_RAW. + UART_INT_RAW_SW_XON_INT_RAW = 0x200 + // Position of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa + // Bit mask of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400 + // Bit SW_XOFF_INT_RAW. + UART_INT_RAW_SW_XOFF_INT_RAW = 0x400 + // Position of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb + // Bit mask of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800 + // Bit GLITCH_DET_INT_RAW. + UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800 + // Position of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000 + // Position of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit TX_DONE_INT_RAW. + UART_INT_RAW_TX_DONE_INT_RAW = 0x4000 + // Position of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_RAW. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW = 0x8000 + // Position of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_RAW. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW = 0x10000 + // Position of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Msk = 0x20000 + // Bit RS485_CLASH_INT_RAW. + UART_INT_RAW_RS485_CLASH_INT_RAW = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_RAW. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000 + // Position of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13 + // Bit mask of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000 + // Bit WAKEUP_INT_RAW. + UART_INT_RAW_WAKEUP_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Pos = 0x9 + // Bit mask of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Msk = 0x200 + // Bit SW_XON_INT_ST. + UART_INT_ST_SW_XON_INT_ST = 0x200 + // Position of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa + // Bit mask of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400 + // Bit SW_XOFF_INT_ST. + UART_INT_ST_SW_XOFF_INT_ST = 0x400 + // Position of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800 + // Bit GLITCH_DET_INT_ST. + UART_INT_ST_GLITCH_DET_INT_ST = 0x800 + // Position of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ST. + UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ST. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000 + // Position of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000 + // Bit TX_DONE_INT_ST. + UART_INT_ST_TX_DONE_INT_ST = 0x4000 + // Position of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ST. + UART_INT_ST_RS485_PARITY_ERR_INT_ST = 0x8000 + // Position of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ST. + UART_INT_ST_RS485_FRM_ERR_INT_ST = 0x10000 + // Position of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Msk = 0x20000 + // Bit RS485_CLASH_INT_ST. + UART_INT_ST_RS485_CLASH_INT_ST = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ST. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000 + // Position of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13 + // Bit mask of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000 + // Bit WAKEUP_INT_ST. + UART_INT_ST_WAKEUP_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9 + // Bit mask of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200 + // Bit SW_XON_INT_ENA. + UART_INT_ENA_SW_XON_INT_ENA = 0x200 + // Position of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa + // Bit mask of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400 + // Bit SW_XOFF_INT_ENA. + UART_INT_ENA_SW_XOFF_INT_ENA = 0x400 + // Position of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800 + // Bit GLITCH_DET_INT_ENA. + UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800 + // Position of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000 + // Position of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit TX_DONE_INT_ENA. + UART_INT_ENA_TX_DONE_INT_ENA = 0x4000 + // Position of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ENA. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA = 0x8000 + // Position of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ENA. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA = 0x10000 + // Position of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Msk = 0x20000 + // Bit RS485_CLASH_INT_ENA. + UART_INT_ENA_RS485_CLASH_INT_ENA = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ENA. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000 + // Position of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13 + // Bit mask of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000 + // Bit WAKEUP_INT_ENA. + UART_INT_ENA_WAKEUP_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9 + // Bit mask of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200 + // Bit SW_XON_INT_CLR. + UART_INT_CLR_SW_XON_INT_CLR = 0x200 + // Position of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa + // Bit mask of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400 + // Bit SW_XOFF_INT_CLR. + UART_INT_CLR_SW_XOFF_INT_CLR = 0x400 + // Position of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb + // Bit mask of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800 + // Bit GLITCH_DET_INT_CLR. + UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800 + // Position of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000 + // Position of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit TX_DONE_INT_CLR. + UART_INT_CLR_TX_DONE_INT_CLR = 0x4000 + // Position of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_CLR. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR = 0x8000 + // Position of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_CLR. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR = 0x10000 + // Position of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Msk = 0x20000 + // Bit RS485_CLASH_INT_CLR. + UART_INT_CLR_RS485_CLASH_INT_CLR = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_CLR. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000 + // Position of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13 + // Bit mask of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000 + // Bit WAKEUP_INT_CLR. + UART_INT_CLR_WAKEUP_INT_CLR = 0x80000 + + // CLKDIV: Clock divider configuration + // Position of CLKDIV field. + UART_CLKDIV_CLKDIV_Pos = 0x0 + // Bit mask of CLKDIV field. + UART_CLKDIV_CLKDIV_Msk = 0xfff + // Position of FRAG field. + UART_CLKDIV_FRAG_Pos = 0x14 + // Bit mask of FRAG field. + UART_CLKDIV_FRAG_Msk = 0xf00000 + + // RX_FILT: Rx Filter configuration + // Position of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Pos = 0x0 + // Bit mask of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Msk = 0xff + // Position of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Pos = 0x8 + // Bit mask of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Msk = 0x100 + // Bit GLITCH_FILT_EN. + UART_RX_FILT_GLITCH_FILT_EN = 0x100 + + // STATUS: UART status register + // Position of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Pos = 0x0 + // Bit mask of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Msk = 0xff + // Position of DSRN field. + UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + UART_STATUS_DSRN = 0x2000 + // Position of CTSN field. + UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + UART_STATUS_CTSN = 0x4000 + // Position of RXD field. + UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + UART_STATUS_RXD = 0x8000 + // Position of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Pos = 0x10 + // Bit mask of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Msk = 0xff0000 + // Position of DTRN field. + UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + UART_STATUS_DTRN = 0x20000000 + // Position of RTSN field. + UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + UART_STATUS_RTSN = 0x40000000 + // Position of TXD field. + UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + UART_STATUS_TXD = 0x80000000 + + // CONF0: a + // Position of PARITY field. + UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + UART_CONF0_PARITY = 0x1 + // Position of PARITY_EN field. + UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + UART_CONF0_PARITY_EN = 0x2 + // Position of BIT_NUM field. + UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + UART_CONF0_BIT_NUM_Msk = 0xc + // Position of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of TXD_BRK field. + UART_CONF0_TXD_BRK_Pos = 0x6 + // Bit mask of TXD_BRK field. + UART_CONF0_TXD_BRK_Msk = 0x40 + // Bit TXD_BRK. + UART_CONF0_TXD_BRK = 0x40 + // Position of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Pos = 0x7 + // Bit mask of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Msk = 0x80 + // Bit IRDA_DPLX. + UART_CONF0_IRDA_DPLX = 0x80 + // Position of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Pos = 0x8 + // Bit mask of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Msk = 0x100 + // Bit IRDA_TX_EN. + UART_CONF0_IRDA_TX_EN = 0x100 + // Position of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Pos = 0x9 + // Bit mask of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Msk = 0x200 + // Bit IRDA_WCTL. + UART_CONF0_IRDA_WCTL = 0x200 + // Position of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Pos = 0xa + // Bit mask of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Msk = 0x400 + // Bit IRDA_TX_INV. + UART_CONF0_IRDA_TX_INV = 0x400 + // Position of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Pos = 0xb + // Bit mask of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Msk = 0x800 + // Bit IRDA_RX_INV. + UART_CONF0_IRDA_RX_INV = 0x800 + // Position of LOOPBACK field. + UART_CONF0_LOOPBACK_Pos = 0xc + // Bit mask of LOOPBACK field. + UART_CONF0_LOOPBACK_Msk = 0x1000 + // Bit LOOPBACK. + UART_CONF0_LOOPBACK = 0x1000 + // Position of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Pos = 0xd + // Bit mask of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Msk = 0x2000 + // Bit TX_FLOW_EN. + UART_CONF0_TX_FLOW_EN = 0x2000 + // Position of IRDA_EN field. + UART_CONF0_IRDA_EN_Pos = 0xe + // Bit mask of IRDA_EN field. + UART_CONF0_IRDA_EN_Msk = 0x4000 + // Bit IRDA_EN. + UART_CONF0_IRDA_EN = 0x4000 + // Position of RXD_INV field. + UART_CONF0_RXD_INV_Pos = 0xf + // Bit mask of RXD_INV field. + UART_CONF0_RXD_INV_Msk = 0x8000 + // Bit RXD_INV. + UART_CONF0_RXD_INV = 0x8000 + // Position of TXD_INV field. + UART_CONF0_TXD_INV_Pos = 0x10 + // Bit mask of TXD_INV field. + UART_CONF0_TXD_INV_Msk = 0x10000 + // Bit TXD_INV. + UART_CONF0_TXD_INV = 0x10000 + // Position of DIS_RX_DAT_OVF field. + UART_CONF0_DIS_RX_DAT_OVF_Pos = 0x11 + // Bit mask of DIS_RX_DAT_OVF field. + UART_CONF0_DIS_RX_DAT_OVF_Msk = 0x20000 + // Bit DIS_RX_DAT_OVF. + UART_CONF0_DIS_RX_DAT_OVF = 0x20000 + // Position of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Pos = 0x12 + // Bit mask of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Msk = 0x40000 + // Bit ERR_WR_MASK. + UART_CONF0_ERR_WR_MASK = 0x40000 + // Position of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Pos = 0x13 + // Bit mask of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Msk = 0x80000 + // Bit AUTOBAUD_EN. + UART_CONF0_AUTOBAUD_EN = 0x80000 + // Position of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Pos = 0x14 + // Bit mask of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Msk = 0x100000 + // Bit MEM_CLK_EN. + UART_CONF0_MEM_CLK_EN = 0x100000 + // Position of SW_RTS field. + UART_CONF0_SW_RTS_Pos = 0x15 + // Bit mask of SW_RTS field. + UART_CONF0_SW_RTS_Msk = 0x200000 + // Bit SW_RTS. + UART_CONF0_SW_RTS = 0x200000 + // Position of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Pos = 0x16 + // Bit mask of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Msk = 0x400000 + // Bit RXFIFO_RST. + UART_CONF0_RXFIFO_RST = 0x400000 + // Position of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Pos = 0x17 + // Bit mask of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Msk = 0x800000 + // Bit TXFIFO_RST. + UART_CONF0_TXFIFO_RST = 0x800000 + + // CONF1: Configuration register 1 + // Position of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0xff + // Position of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0x8 + // Bit mask of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0xff00 + // Position of CTS_INV field. + UART_CONF1_CTS_INV_Pos = 0x10 + // Bit mask of CTS_INV field. + UART_CONF1_CTS_INV_Msk = 0x10000 + // Bit CTS_INV. + UART_CONF1_CTS_INV = 0x10000 + // Position of DSR_INV field. + UART_CONF1_DSR_INV_Pos = 0x11 + // Bit mask of DSR_INV field. + UART_CONF1_DSR_INV_Msk = 0x20000 + // Bit DSR_INV. + UART_CONF1_DSR_INV = 0x20000 + // Position of RTS_INV field. + UART_CONF1_RTS_INV_Pos = 0x12 + // Bit mask of RTS_INV field. + UART_CONF1_RTS_INV_Msk = 0x40000 + // Bit RTS_INV. + UART_CONF1_RTS_INV = 0x40000 + // Position of DTR_INV field. + UART_CONF1_DTR_INV_Pos = 0x13 + // Bit mask of DTR_INV field. + UART_CONF1_DTR_INV_Msk = 0x80000 + // Bit DTR_INV. + UART_CONF1_DTR_INV = 0x80000 + // Position of SW_DTR field. + UART_CONF1_SW_DTR_Pos = 0x14 + // Bit mask of SW_DTR field. + UART_CONF1_SW_DTR_Msk = 0x100000 + // Bit SW_DTR. + UART_CONF1_SW_DTR = 0x100000 + // Position of CLK_EN field. + UART_CONF1_CLK_EN_Pos = 0x15 + // Bit mask of CLK_EN field. + UART_CONF1_CLK_EN_Msk = 0x200000 + // Bit CLK_EN. + UART_CONF1_CLK_EN = 0x200000 + + // HWFC_CONF: Hardware flow-control configuration + // Position of RX_FLOW_THRHD field. + UART_HWFC_CONF_RX_FLOW_THRHD_Pos = 0x0 + // Bit mask of RX_FLOW_THRHD field. + UART_HWFC_CONF_RX_FLOW_THRHD_Msk = 0xff + // Position of RX_FLOW_EN field. + UART_HWFC_CONF_RX_FLOW_EN_Pos = 0x8 + // Bit mask of RX_FLOW_EN field. + UART_HWFC_CONF_RX_FLOW_EN_Msk = 0x100 + // Bit RX_FLOW_EN. + UART_HWFC_CONF_RX_FLOW_EN = 0x100 + + // SLEEP_CONF0: UART sleep configure register 0 + // Position of WK_CHAR1 field. + UART_SLEEP_CONF0_WK_CHAR1_Pos = 0x0 + // Bit mask of WK_CHAR1 field. + UART_SLEEP_CONF0_WK_CHAR1_Msk = 0xff + // Position of WK_CHAR2 field. + UART_SLEEP_CONF0_WK_CHAR2_Pos = 0x8 + // Bit mask of WK_CHAR2 field. + UART_SLEEP_CONF0_WK_CHAR2_Msk = 0xff00 + // Position of WK_CHAR3 field. + UART_SLEEP_CONF0_WK_CHAR3_Pos = 0x10 + // Bit mask of WK_CHAR3 field. + UART_SLEEP_CONF0_WK_CHAR3_Msk = 0xff0000 + // Position of WK_CHAR4 field. + UART_SLEEP_CONF0_WK_CHAR4_Pos = 0x18 + // Bit mask of WK_CHAR4 field. + UART_SLEEP_CONF0_WK_CHAR4_Msk = 0xff000000 + + // SLEEP_CONF1: UART sleep configure register 1 + // Position of WK_CHAR0 field. + UART_SLEEP_CONF1_WK_CHAR0_Pos = 0x0 + // Bit mask of WK_CHAR0 field. + UART_SLEEP_CONF1_WK_CHAR0_Msk = 0xff + + // SLEEP_CONF2: UART sleep configure register 2 + // Position of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Pos = 0x0 + // Bit mask of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Msk = 0x3ff + // Position of RX_WAKE_UP_THRHD field. + UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Pos = 0xa + // Bit mask of RX_WAKE_UP_THRHD field. + UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Msk = 0x3fc00 + // Position of WK_CHAR_NUM field. + UART_SLEEP_CONF2_WK_CHAR_NUM_Pos = 0x12 + // Bit mask of WK_CHAR_NUM field. + UART_SLEEP_CONF2_WK_CHAR_NUM_Msk = 0x1c0000 + // Position of WK_CHAR_MASK field. + UART_SLEEP_CONF2_WK_CHAR_MASK_Pos = 0x15 + // Bit mask of WK_CHAR_MASK field. + UART_SLEEP_CONF2_WK_CHAR_MASK_Msk = 0x3e00000 + // Position of WK_MODE_SEL field. + UART_SLEEP_CONF2_WK_MODE_SEL_Pos = 0x1a + // Bit mask of WK_MODE_SEL field. + UART_SLEEP_CONF2_WK_MODE_SEL_Msk = 0xc000000 + + // SWFC_CONF0: Software flow-control character configuration + // Position of XON_CHAR field. + UART_SWFC_CONF0_XON_CHAR_Pos = 0x0 + // Bit mask of XON_CHAR field. + UART_SWFC_CONF0_XON_CHAR_Msk = 0xff + // Position of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Pos = 0x8 + // Bit mask of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Msk = 0xff00 + // Position of XON_XOFF_STILL_SEND field. + UART_SWFC_CONF0_XON_XOFF_STILL_SEND_Pos = 0x10 + // Bit mask of XON_XOFF_STILL_SEND field. + UART_SWFC_CONF0_XON_XOFF_STILL_SEND_Msk = 0x10000 + // Bit XON_XOFF_STILL_SEND. + UART_SWFC_CONF0_XON_XOFF_STILL_SEND = 0x10000 + // Position of SW_FLOW_CON_EN field. + UART_SWFC_CONF0_SW_FLOW_CON_EN_Pos = 0x11 + // Bit mask of SW_FLOW_CON_EN field. + UART_SWFC_CONF0_SW_FLOW_CON_EN_Msk = 0x20000 + // Bit SW_FLOW_CON_EN. + UART_SWFC_CONF0_SW_FLOW_CON_EN = 0x20000 + // Position of XONOFF_DEL field. + UART_SWFC_CONF0_XONOFF_DEL_Pos = 0x12 + // Bit mask of XONOFF_DEL field. + UART_SWFC_CONF0_XONOFF_DEL_Msk = 0x40000 + // Bit XONOFF_DEL. + UART_SWFC_CONF0_XONOFF_DEL = 0x40000 + // Position of FORCE_XON field. + UART_SWFC_CONF0_FORCE_XON_Pos = 0x13 + // Bit mask of FORCE_XON field. + UART_SWFC_CONF0_FORCE_XON_Msk = 0x80000 + // Bit FORCE_XON. + UART_SWFC_CONF0_FORCE_XON = 0x80000 + // Position of FORCE_XOFF field. + UART_SWFC_CONF0_FORCE_XOFF_Pos = 0x14 + // Bit mask of FORCE_XOFF field. + UART_SWFC_CONF0_FORCE_XOFF_Msk = 0x100000 + // Bit FORCE_XOFF. + UART_SWFC_CONF0_FORCE_XOFF = 0x100000 + // Position of SEND_XON field. + UART_SWFC_CONF0_SEND_XON_Pos = 0x15 + // Bit mask of SEND_XON field. + UART_SWFC_CONF0_SEND_XON_Msk = 0x200000 + // Bit SEND_XON. + UART_SWFC_CONF0_SEND_XON = 0x200000 + // Position of SEND_XOFF field. + UART_SWFC_CONF0_SEND_XOFF_Pos = 0x16 + // Bit mask of SEND_XOFF field. + UART_SWFC_CONF0_SEND_XOFF_Msk = 0x400000 + // Bit SEND_XOFF. + UART_SWFC_CONF0_SEND_XOFF = 0x400000 + + // SWFC_CONF1: Software flow-control character configuration + // Position of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x0 + // Bit mask of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0xff + // Position of XOFF_THRESHOLD field. + UART_SWFC_CONF1_XOFF_THRESHOLD_Pos = 0x8 + // Bit mask of XOFF_THRESHOLD field. + UART_SWFC_CONF1_XOFF_THRESHOLD_Msk = 0xff00 + + // TXBRK_CONF: Tx Break character configuration + // Position of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Pos = 0x0 + // Bit mask of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Msk = 0xff + + // IDLE_CONF: Frame-end idle configuration + // Position of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Pos = 0x0 + // Bit mask of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Msk = 0x3ff + // Position of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Pos = 0xa + // Bit mask of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Msk = 0xffc00 + + // RS485_CONF: RS485 mode configuration + // Position of RS485_EN field. + UART_RS485_CONF_RS485_EN_Pos = 0x0 + // Bit mask of RS485_EN field. + UART_RS485_CONF_RS485_EN_Msk = 0x1 + // Bit RS485_EN. + UART_RS485_CONF_RS485_EN = 0x1 + // Position of DL0_EN field. + UART_RS485_CONF_DL0_EN_Pos = 0x1 + // Bit mask of DL0_EN field. + UART_RS485_CONF_DL0_EN_Msk = 0x2 + // Bit DL0_EN. + UART_RS485_CONF_DL0_EN = 0x2 + // Position of DL1_EN field. + UART_RS485_CONF_DL1_EN_Pos = 0x2 + // Bit mask of DL1_EN field. + UART_RS485_CONF_DL1_EN_Msk = 0x4 + // Bit DL1_EN. + UART_RS485_CONF_DL1_EN = 0x4 + // Position of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Pos = 0x3 + // Bit mask of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Msk = 0x8 + // Bit RS485TX_RX_EN. + UART_RS485_CONF_RS485TX_RX_EN = 0x8 + // Position of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Pos = 0x4 + // Bit mask of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Msk = 0x10 + // Bit RS485RXBY_TX_EN. + UART_RS485_CONF_RS485RXBY_TX_EN = 0x10 + // Position of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Pos = 0x5 + // Bit mask of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Msk = 0x20 + // Bit RS485_RX_DLY_NUM. + UART_RS485_CONF_RS485_RX_DLY_NUM = 0x20 + // Position of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Pos = 0x6 + // Bit mask of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Msk = 0x3c0 + + // AT_CMD_PRECNT: Pre-sequence timing configuration + // Position of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Pos = 0x0 + // Bit mask of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Msk = 0xffff + + // AT_CMD_POSTCNT: Post-sequence timing configuration + // Position of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Pos = 0x0 + // Bit mask of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Msk = 0xffff + + // AT_CMD_GAPTOUT: Timeout configuration + // Position of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Pos = 0x0 + // Bit mask of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Msk = 0xffff + + // AT_CMD_CHAR: AT escape sequence detection configuration + // Position of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Pos = 0x0 + // Bit mask of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Msk = 0xff + // Position of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Pos = 0x8 + // Bit mask of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Msk = 0xff00 + + // MEM_CONF: UART memory power configuration + // Position of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x19 + // Bit mask of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x2000000 + // Bit MEM_FORCE_PD. + UART_MEM_CONF_MEM_FORCE_PD = 0x2000000 + // Position of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1a + // Bit mask of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x4000000 + // Bit MEM_FORCE_PU. + UART_MEM_CONF_MEM_FORCE_PU = 0x4000000 + + // TOUT_CONF: UART threshold and allocation configuration + // Position of RX_TOUT_EN field. + UART_TOUT_CONF_RX_TOUT_EN_Pos = 0x0 + // Bit mask of RX_TOUT_EN field. + UART_TOUT_CONF_RX_TOUT_EN_Msk = 0x1 + // Bit RX_TOUT_EN. + UART_TOUT_CONF_RX_TOUT_EN = 0x1 + // Position of RX_TOUT_FLOW_DIS field. + UART_TOUT_CONF_RX_TOUT_FLOW_DIS_Pos = 0x1 + // Bit mask of RX_TOUT_FLOW_DIS field. + UART_TOUT_CONF_RX_TOUT_FLOW_DIS_Msk = 0x2 + // Bit RX_TOUT_FLOW_DIS. + UART_TOUT_CONF_RX_TOUT_FLOW_DIS = 0x2 + // Position of RX_TOUT_THRHD field. + UART_TOUT_CONF_RX_TOUT_THRHD_Pos = 0x2 + // Bit mask of RX_TOUT_THRHD field. + UART_TOUT_CONF_RX_TOUT_THRHD_Msk = 0xffc + + // MEM_TX_STATUS: Tx-SRAM write and read offset address. + // Position of TX_SRAM_WADDR field. + UART_MEM_TX_STATUS_TX_SRAM_WADDR_Pos = 0x0 + // Bit mask of TX_SRAM_WADDR field. + UART_MEM_TX_STATUS_TX_SRAM_WADDR_Msk = 0xff + // Position of TX_SRAM_RADDR field. + UART_MEM_TX_STATUS_TX_SRAM_RADDR_Pos = 0x9 + // Bit mask of TX_SRAM_RADDR field. + UART_MEM_TX_STATUS_TX_SRAM_RADDR_Msk = 0x1fe00 + + // MEM_RX_STATUS: Rx-SRAM write and read offset address. + // Position of RX_SRAM_RADDR field. + UART_MEM_RX_STATUS_RX_SRAM_RADDR_Pos = 0x0 + // Bit mask of RX_SRAM_RADDR field. + UART_MEM_RX_STATUS_RX_SRAM_RADDR_Msk = 0xff + // Position of RX_SRAM_WADDR field. + UART_MEM_RX_STATUS_RX_SRAM_WADDR_Pos = 0x9 + // Bit mask of RX_SRAM_WADDR field. + UART_MEM_RX_STATUS_RX_SRAM_WADDR_Msk = 0x1fe00 + + // FSM_STATUS: UART transmit and receive status. + // Position of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0 + // Bit mask of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf + // Position of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4 + // Bit mask of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0 + + // POSPULSE: Autobaud high pulse register + // Position of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Msk = 0xfff + + // NEGPULSE: Autobaud low pulse register + // Position of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Msk = 0xfff + + // LOWPULSE: Autobaud minimum low pulse duration register + // Position of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Msk = 0xfff + + // HIGHPULSE: Autobaud minimum high pulse duration register + // Position of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Msk = 0xfff + + // RXD_CNT: Autobaud edge change count register + // Position of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0 + // Bit mask of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff + + // CLK_CONF: UART core clock configuration + // Position of SCLK_DIV_B field. + UART_CLK_CONF_SCLK_DIV_B_Pos = 0x0 + // Bit mask of SCLK_DIV_B field. + UART_CLK_CONF_SCLK_DIV_B_Msk = 0x3f + // Position of SCLK_DIV_A field. + UART_CLK_CONF_SCLK_DIV_A_Pos = 0x6 + // Bit mask of SCLK_DIV_A field. + UART_CLK_CONF_SCLK_DIV_A_Msk = 0xfc0 + // Position of SCLK_DIV_NUM field. + UART_CLK_CONF_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of SCLK_DIV_NUM field. + UART_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff000 + // Position of SCLK_SEL field. + UART_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + UART_CLK_CONF_SCLK_SEL_Msk = 0x300000 + // Position of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Pos = 0x16 + // Bit mask of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Msk = 0x400000 + // Bit SCLK_EN. + UART_CLK_CONF_SCLK_EN = 0x400000 + // Position of RST_CORE field. + UART_CLK_CONF_RST_CORE_Pos = 0x17 + // Bit mask of RST_CORE field. + UART_CLK_CONF_RST_CORE_Msk = 0x800000 + // Bit RST_CORE. + UART_CLK_CONF_RST_CORE = 0x800000 + // Position of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Pos = 0x18 + // Bit mask of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Msk = 0x1000000 + // Bit TX_SCLK_EN. + UART_CLK_CONF_TX_SCLK_EN = 0x1000000 + // Position of RX_SCLK_EN field. + UART_CLK_CONF_RX_SCLK_EN_Pos = 0x19 + // Bit mask of RX_SCLK_EN field. + UART_CLK_CONF_RX_SCLK_EN_Msk = 0x2000000 + // Bit RX_SCLK_EN. + UART_CLK_CONF_RX_SCLK_EN = 0x2000000 + // Position of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Pos = 0x1a + // Bit mask of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Msk = 0x4000000 + // Bit TX_RST_CORE. + UART_CLK_CONF_TX_RST_CORE = 0x4000000 + // Position of RX_RST_CORE field. + UART_CLK_CONF_RX_RST_CORE_Pos = 0x1b + // Bit mask of RX_RST_CORE field. + UART_CLK_CONF_RX_RST_CORE_Msk = 0x8000000 + // Bit RX_RST_CORE. + UART_CLK_CONF_RX_RST_CORE = 0x8000000 + + // DATE: UART Version register + // Position of DATE field. + UART_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UART_DATE_DATE_Msk = 0xffffffff + + // AFIFO_STATUS: UART AFIFO Status + // Position of TX_AFIFO_FULL field. + UART_AFIFO_STATUS_TX_AFIFO_FULL_Pos = 0x0 + // Bit mask of TX_AFIFO_FULL field. + UART_AFIFO_STATUS_TX_AFIFO_FULL_Msk = 0x1 + // Bit TX_AFIFO_FULL. + UART_AFIFO_STATUS_TX_AFIFO_FULL = 0x1 + // Position of TX_AFIFO_EMPTY field. + UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Pos = 0x1 + // Bit mask of TX_AFIFO_EMPTY field. + UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Msk = 0x2 + // Bit TX_AFIFO_EMPTY. + UART_AFIFO_STATUS_TX_AFIFO_EMPTY = 0x2 + // Position of RX_AFIFO_FULL field. + UART_AFIFO_STATUS_RX_AFIFO_FULL_Pos = 0x2 + // Bit mask of RX_AFIFO_FULL field. + UART_AFIFO_STATUS_RX_AFIFO_FULL_Msk = 0x4 + // Bit RX_AFIFO_FULL. + UART_AFIFO_STATUS_RX_AFIFO_FULL = 0x4 + // Position of RX_AFIFO_EMPTY field. + UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Pos = 0x3 + // Bit mask of RX_AFIFO_EMPTY field. + UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Msk = 0x8 + // Bit RX_AFIFO_EMPTY. + UART_AFIFO_STATUS_RX_AFIFO_EMPTY = 0x8 + + // REG_UPDATE: UART Registers Configuration Update register + // Position of REG_UPDATE field. + UART_REG_UPDATE_REG_UPDATE_Pos = 0x0 + // Bit mask of REG_UPDATE field. + UART_REG_UPDATE_REG_UPDATE_Msk = 0x1 + // Bit REG_UPDATE. + UART_REG_UPDATE_REG_UPDATE = 0x1 + + // ID: UART ID register + // Position of ID field. + UART_ID_ID_Pos = 0x0 + // Bit mask of ID field. + UART_ID_ID_Msk = 0xffffffff +) + +// Constants for UHCI0: Universal Host Controller Interface 0 +const ( + // CONF0: UHCI Configuration Register0 + // Position of TX_RST field. + UHCI_CONF0_TX_RST_Pos = 0x0 + // Bit mask of TX_RST field. + UHCI_CONF0_TX_RST_Msk = 0x1 + // Bit TX_RST. + UHCI_CONF0_TX_RST = 0x1 + // Position of RX_RST field. + UHCI_CONF0_RX_RST_Pos = 0x1 + // Bit mask of RX_RST field. + UHCI_CONF0_RX_RST_Msk = 0x2 + // Bit RX_RST. + UHCI_CONF0_RX_RST = 0x2 + // Position of UART0_CE field. + UHCI_CONF0_UART0_CE_Pos = 0x2 + // Bit mask of UART0_CE field. + UHCI_CONF0_UART0_CE_Msk = 0x4 + // Bit UART0_CE. + UHCI_CONF0_UART0_CE = 0x4 + // Position of UART1_CE field. + UHCI_CONF0_UART1_CE_Pos = 0x3 + // Bit mask of UART1_CE field. + UHCI_CONF0_UART1_CE_Msk = 0x8 + // Bit UART1_CE. + UHCI_CONF0_UART1_CE = 0x8 + // Position of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Pos = 0x5 + // Bit mask of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Msk = 0x20 + // Bit SEPER_EN. + UHCI_CONF0_SEPER_EN = 0x20 + // Position of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Pos = 0x6 + // Bit mask of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Msk = 0x40 + // Bit HEAD_EN. + UHCI_CONF0_HEAD_EN = 0x40 + // Position of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Pos = 0x7 + // Bit mask of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Msk = 0x80 + // Bit CRC_REC_EN. + UHCI_CONF0_CRC_REC_EN = 0x80 + // Position of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Pos = 0x8 + // Bit mask of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Msk = 0x100 + // Bit UART_IDLE_EOF_EN. + UHCI_CONF0_UART_IDLE_EOF_EN = 0x100 + // Position of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Pos = 0x9 + // Bit mask of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Msk = 0x200 + // Bit LEN_EOF_EN. + UHCI_CONF0_LEN_EOF_EN = 0x200 + // Position of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Pos = 0xa + // Bit mask of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Msk = 0x400 + // Bit ENCODE_CRC_EN. + UHCI_CONF0_ENCODE_CRC_EN = 0x400 + // Position of CLK_EN field. + UHCI_CONF0_CLK_EN_Pos = 0xb + // Bit mask of CLK_EN field. + UHCI_CONF0_CLK_EN_Msk = 0x800 + // Bit CLK_EN. + UHCI_CONF0_CLK_EN = 0x800 + // Position of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Pos = 0xc + // Bit mask of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Msk = 0x1000 + // Bit UART_RX_BRK_EOF_EN. + UHCI_CONF0_UART_RX_BRK_EOF_EN = 0x1000 + + // INT_RAW: UHCI Interrupt Raw Register + // Position of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Pos = 0x0 + // Bit mask of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Msk = 0x1 + // Bit RX_START_INT_RAW. + UHCI_INT_RAW_RX_START_INT_RAW = 0x1 + // Position of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Pos = 0x1 + // Bit mask of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Msk = 0x2 + // Bit TX_START_INT_RAW. + UHCI_INT_RAW_TX_START_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + UHCI_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + UHCI_INT_RAW_TX_HUNG_INT_RAW = 0x8 + // Position of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW = 0x10 + // Position of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW = 0x20 + // Position of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x6 + // Bit mask of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x40 + // Bit OUT_EOF_INT_RAW. + UHCI_INT_RAW_OUT_EOF_INT_RAW = 0x40 + // Position of APP_CTRL0_INT_RAW field. + UHCI_INT_RAW_APP_CTRL0_INT_RAW_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_RAW field. + UHCI_INT_RAW_APP_CTRL0_INT_RAW_Msk = 0x80 + // Bit APP_CTRL0_INT_RAW. + UHCI_INT_RAW_APP_CTRL0_INT_RAW = 0x80 + // Position of APP_CTRL1_INT_RAW field. + UHCI_INT_RAW_APP_CTRL1_INT_RAW_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_RAW field. + UHCI_INT_RAW_APP_CTRL1_INT_RAW_Msk = 0x100 + // Bit APP_CTRL1_INT_RAW. + UHCI_INT_RAW_APP_CTRL1_INT_RAW = 0x100 + + // INT_ST: UHCI Interrupt Status Register + // Position of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Pos = 0x0 + // Bit mask of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Msk = 0x1 + // Bit RX_START_INT_ST. + UHCI_INT_ST_RX_START_INT_ST = 0x1 + // Position of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Pos = 0x1 + // Bit mask of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Msk = 0x2 + // Bit TX_START_INT_ST. + UHCI_INT_ST_TX_START_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + UHCI_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + UHCI_INT_ST_TX_HUNG_INT_ST = 0x8 + // Position of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_ST. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST = 0x10 + // Position of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_ST. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST = 0x20 + // Position of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_ST. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST = 0x40 + // Position of APP_CTRL0_INT_ST field. + UHCI_INT_ST_APP_CTRL0_INT_ST_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_ST field. + UHCI_INT_ST_APP_CTRL0_INT_ST_Msk = 0x80 + // Bit APP_CTRL0_INT_ST. + UHCI_INT_ST_APP_CTRL0_INT_ST = 0x80 + // Position of APP_CTRL1_INT_ST field. + UHCI_INT_ST_APP_CTRL1_INT_ST_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_ST field. + UHCI_INT_ST_APP_CTRL1_INT_ST_Msk = 0x100 + // Bit APP_CTRL1_INT_ST. + UHCI_INT_ST_APP_CTRL1_INT_ST = 0x100 + + // INT_ENA: UHCI Interrupt Enable Register + // Position of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Pos = 0x0 + // Bit mask of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Msk = 0x1 + // Bit RX_START_INT_ENA. + UHCI_INT_ENA_RX_START_INT_ENA = 0x1 + // Position of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Pos = 0x1 + // Bit mask of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Msk = 0x2 + // Bit TX_START_INT_ENA. + UHCI_INT_ENA_TX_START_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + UHCI_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + UHCI_INT_ENA_TX_HUNG_INT_ENA = 0x8 + // Position of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA = 0x10 + // Position of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA = 0x20 + // Position of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_ENA. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA = 0x40 + // Position of APP_CTRL0_INT_ENA field. + UHCI_INT_ENA_APP_CTRL0_INT_ENA_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_ENA field. + UHCI_INT_ENA_APP_CTRL0_INT_ENA_Msk = 0x80 + // Bit APP_CTRL0_INT_ENA. + UHCI_INT_ENA_APP_CTRL0_INT_ENA = 0x80 + // Position of APP_CTRL1_INT_ENA field. + UHCI_INT_ENA_APP_CTRL1_INT_ENA_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_ENA field. + UHCI_INT_ENA_APP_CTRL1_INT_ENA_Msk = 0x100 + // Bit APP_CTRL1_INT_ENA. + UHCI_INT_ENA_APP_CTRL1_INT_ENA = 0x100 + + // INT_CLR: UHCI Interrupt Clear Register + // Position of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Pos = 0x0 + // Bit mask of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Msk = 0x1 + // Bit RX_START_INT_CLR. + UHCI_INT_CLR_RX_START_INT_CLR = 0x1 + // Position of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Pos = 0x1 + // Bit mask of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Msk = 0x2 + // Bit TX_START_INT_CLR. + UHCI_INT_CLR_TX_START_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + UHCI_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + UHCI_INT_CLR_TX_HUNG_INT_CLR = 0x8 + // Position of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR = 0x10 + // Position of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR = 0x20 + // Position of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_CLR. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR = 0x40 + // Position of APP_CTRL0_INT_CLR field. + UHCI_INT_CLR_APP_CTRL0_INT_CLR_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_CLR field. + UHCI_INT_CLR_APP_CTRL0_INT_CLR_Msk = 0x80 + // Bit APP_CTRL0_INT_CLR. + UHCI_INT_CLR_APP_CTRL0_INT_CLR = 0x80 + // Position of APP_CTRL1_INT_CLR field. + UHCI_INT_CLR_APP_CTRL1_INT_CLR_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_CLR field. + UHCI_INT_CLR_APP_CTRL1_INT_CLR_Msk = 0x100 + // Bit APP_CTRL1_INT_CLR. + UHCI_INT_CLR_APP_CTRL1_INT_CLR = 0x100 + + // CONF1: UHCI Configuration Register1 + // Position of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Pos = 0x0 + // Bit mask of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Msk = 0x1 + // Bit CHECK_SUM_EN. + UHCI_CONF1_CHECK_SUM_EN = 0x1 + // Position of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Pos = 0x1 + // Bit mask of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Msk = 0x2 + // Bit CHECK_SEQ_EN. + UHCI_CONF1_CHECK_SEQ_EN = 0x2 + // Position of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Pos = 0x2 + // Bit mask of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Msk = 0x4 + // Bit CRC_DISABLE. + UHCI_CONF1_CRC_DISABLE = 0x4 + // Position of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Pos = 0x3 + // Bit mask of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Msk = 0x8 + // Bit SAVE_HEAD. + UHCI_CONF1_SAVE_HEAD = 0x8 + // Position of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Pos = 0x4 + // Bit mask of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Msk = 0x10 + // Bit TX_CHECK_SUM_RE. + UHCI_CONF1_TX_CHECK_SUM_RE = 0x10 + // Position of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Pos = 0x5 + // Bit mask of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Msk = 0x20 + // Bit TX_ACK_NUM_RE. + UHCI_CONF1_TX_ACK_NUM_RE = 0x20 + // Position of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Pos = 0x7 + // Bit mask of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Msk = 0x80 + // Bit WAIT_SW_START. + UHCI_CONF1_WAIT_SW_START = 0x80 + // Position of SW_START field. + UHCI_CONF1_SW_START_Pos = 0x8 + // Bit mask of SW_START field. + UHCI_CONF1_SW_START_Msk = 0x100 + // Bit SW_START. + UHCI_CONF1_SW_START = 0x100 + + // STATE0: UHCI Receive Status Register + // Position of RX_ERR_CAUSE field. + UHCI_STATE0_RX_ERR_CAUSE_Pos = 0x0 + // Bit mask of RX_ERR_CAUSE field. + UHCI_STATE0_RX_ERR_CAUSE_Msk = 0x7 + // Position of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Pos = 0x3 + // Bit mask of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Msk = 0x38 + + // STATE1: UHCI Transmit Status Register + // Position of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Pos = 0x0 + // Bit mask of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Msk = 0x7 + + // ESCAPE_CONF: UHCI Escapes Configuration Register0 + // Position of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Pos = 0x0 + // Bit mask of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Msk = 0x1 + // Bit TX_C0_ESC_EN. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN = 0x1 + // Position of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Pos = 0x1 + // Bit mask of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Msk = 0x2 + // Bit TX_DB_ESC_EN. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN = 0x2 + // Position of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Pos = 0x2 + // Bit mask of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Msk = 0x4 + // Bit TX_11_ESC_EN. + UHCI_ESCAPE_CONF_TX_11_ESC_EN = 0x4 + // Position of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Pos = 0x3 + // Bit mask of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Msk = 0x8 + // Bit TX_13_ESC_EN. + UHCI_ESCAPE_CONF_TX_13_ESC_EN = 0x8 + // Position of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Pos = 0x4 + // Bit mask of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Msk = 0x10 + // Bit RX_C0_ESC_EN. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN = 0x10 + // Position of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Pos = 0x5 + // Bit mask of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Msk = 0x20 + // Bit RX_DB_ESC_EN. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN = 0x20 + // Position of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Pos = 0x6 + // Bit mask of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Msk = 0x40 + // Bit RX_11_ESC_EN. + UHCI_ESCAPE_CONF_RX_11_ESC_EN = 0x40 + // Position of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Pos = 0x7 + // Bit mask of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Msk = 0x80 + // Bit RX_13_ESC_EN. + UHCI_ESCAPE_CONF_RX_13_ESC_EN = 0x80 + + // HUNG_CONF: UHCI Hung Configuration Register0 + // Position of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Pos = 0x0 + // Bit mask of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Msk = 0xff + // Position of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit TXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA = 0x800 + // Position of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Pos = 0xc + // Bit mask of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Msk = 0xff000 + // Position of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Pos = 0x14 + // Bit mask of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Msk = 0x700000 + // Position of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Pos = 0x17 + // Bit mask of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Msk = 0x800000 + // Bit RXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA = 0x800000 + + // ACK_NUM: UHCI Ack Value Configuration Register0 + // Position of ACK_NUM field. + UHCI_ACK_NUM_ACK_NUM_Pos = 0x0 + // Bit mask of ACK_NUM field. + UHCI_ACK_NUM_ACK_NUM_Msk = 0x7 + // Position of LOAD field. + UHCI_ACK_NUM_LOAD_Pos = 0x3 + // Bit mask of LOAD field. + UHCI_ACK_NUM_LOAD_Msk = 0x8 + // Bit LOAD. + UHCI_ACK_NUM_LOAD = 0x8 + + // RX_HEAD: UHCI Head Register + // Position of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Pos = 0x0 + // Bit mask of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Msk = 0xffffffff + + // QUICK_SENT: UCHI Quick send Register + // Position of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Pos = 0x0 + // Bit mask of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Msk = 0x7 + // Position of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Pos = 0x3 + // Bit mask of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Msk = 0x8 + // Bit SINGLE_SEND_EN. + UHCI_QUICK_SENT_SINGLE_SEND_EN = 0x8 + // Position of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Pos = 0x4 + // Bit mask of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Msk = 0x70 + // Position of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Pos = 0x7 + // Bit mask of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Msk = 0x80 + // Bit ALWAYS_SEND_EN. + UHCI_QUICK_SENT_ALWAYS_SEND_EN = 0x80 + + // REG_Q0_WORD0: UHCI Q0_WORD0 Quick Send Register + // Position of SEND_Q0_WORD0 field. + UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Pos = 0x0 + // Bit mask of SEND_Q0_WORD0 field. + UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Msk = 0xffffffff + + // REG_Q0_WORD1: UHCI Q0_WORD1 Quick Send Register + // Position of SEND_Q0_WORD1 field. + UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Pos = 0x0 + // Bit mask of SEND_Q0_WORD1 field. + UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Msk = 0xffffffff + + // REG_Q1_WORD0: UHCI Q1_WORD0 Quick Send Register + // Position of SEND_Q1_WORD0 field. + UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Pos = 0x0 + // Bit mask of SEND_Q1_WORD0 field. + UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Msk = 0xffffffff + + // REG_Q1_WORD1: UHCI Q1_WORD1 Quick Send Register + // Position of SEND_Q1_WORD1 field. + UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Pos = 0x0 + // Bit mask of SEND_Q1_WORD1 field. + UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Msk = 0xffffffff + + // REG_Q2_WORD0: UHCI Q2_WORD0 Quick Send Register + // Position of SEND_Q2_WORD0 field. + UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Pos = 0x0 + // Bit mask of SEND_Q2_WORD0 field. + UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Msk = 0xffffffff + + // REG_Q2_WORD1: UHCI Q2_WORD1 Quick Send Register + // Position of SEND_Q2_WORD1 field. + UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Pos = 0x0 + // Bit mask of SEND_Q2_WORD1 field. + UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Msk = 0xffffffff + + // REG_Q3_WORD0: UHCI Q3_WORD0 Quick Send Register + // Position of SEND_Q3_WORD0 field. + UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Pos = 0x0 + // Bit mask of SEND_Q3_WORD0 field. + UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Msk = 0xffffffff + + // REG_Q3_WORD1: UHCI Q3_WORD1 Quick Send Register + // Position of SEND_Q3_WORD1 field. + UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Pos = 0x0 + // Bit mask of SEND_Q3_WORD1 field. + UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Msk = 0xffffffff + + // REG_Q4_WORD0: UHCI Q4_WORD0 Quick Send Register + // Position of SEND_Q4_WORD0 field. + UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Pos = 0x0 + // Bit mask of SEND_Q4_WORD0 field. + UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Msk = 0xffffffff + + // REG_Q4_WORD1: UHCI Q4_WORD1 Quick Send Register + // Position of SEND_Q4_WORD1 field. + UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Pos = 0x0 + // Bit mask of SEND_Q4_WORD1 field. + UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Msk = 0xffffffff + + // REG_Q5_WORD0: UHCI Q5_WORD0 Quick Send Register + // Position of SEND_Q5_WORD0 field. + UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Pos = 0x0 + // Bit mask of SEND_Q5_WORD0 field. + UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Msk = 0xffffffff + + // REG_Q5_WORD1: UHCI Q5_WORD1 Quick Send Register + // Position of SEND_Q5_WORD1 field. + UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Pos = 0x0 + // Bit mask of SEND_Q5_WORD1 field. + UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Msk = 0xffffffff + + // REG_Q6_WORD0: UHCI Q6_WORD0 Quick Send Register + // Position of SEND_Q6_WORD0 field. + UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Pos = 0x0 + // Bit mask of SEND_Q6_WORD0 field. + UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Msk = 0xffffffff + + // REG_Q6_WORD1: UHCI Q6_WORD1 Quick Send Register + // Position of SEND_Q6_WORD1 field. + UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Pos = 0x0 + // Bit mask of SEND_Q6_WORD1 field. + UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Msk = 0xffffffff + + // ESC_CONF0: UHCI Escapes Sequence Configuration Register0 + // Position of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Pos = 0x0 + // Bit mask of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Msk = 0xff + // Position of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Pos = 0x8 + // Bit mask of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Msk = 0xff00 + // Position of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Pos = 0x10 + // Bit mask of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Msk = 0xff0000 + + // ESC_CONF1: UHCI Escapes Sequence Configuration Register1 + // Position of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Pos = 0x0 + // Bit mask of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Msk = 0xff + // Position of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Msk = 0xff0000 + + // ESC_CONF2: UHCI Escapes Sequence Configuration Register2 + // Position of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Pos = 0x0 + // Bit mask of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Msk = 0xff + // Position of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Msk = 0xff0000 + + // ESC_CONF3: UHCI Escapes Sequence Configuration Register3 + // Position of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Pos = 0x0 + // Bit mask of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Msk = 0xff + // Position of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Msk = 0xff0000 + + // PKT_THRES: UCHI Packet Length Configuration Register + // Position of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Pos = 0x0 + // Bit mask of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Msk = 0x1fff + + // DATE: UHCI Version Register + // Position of DATE field. + UHCI_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UHCI_DATE_DATE_Msk = 0xffffffff +) + +// Constants for USB_DEVICE: Full-speed USB Serial/JTAG Controller +const ( + // EP1: FIFO access for the CDC-ACM data IN and OUT endpoints. + // Position of RDWR_BYTE field. + USB_DEVICE_EP1_RDWR_BYTE_Pos = 0x0 + // Bit mask of RDWR_BYTE field. + USB_DEVICE_EP1_RDWR_BYTE_Msk = 0xff + + // EP1_CONF: Configuration and control registers for the CDC-ACM FIFOs. + // Position of WR_DONE field. + USB_DEVICE_EP1_CONF_WR_DONE_Pos = 0x0 + // Bit mask of WR_DONE field. + USB_DEVICE_EP1_CONF_WR_DONE_Msk = 0x1 + // Bit WR_DONE. + USB_DEVICE_EP1_CONF_WR_DONE = 0x1 + // Position of SERIAL_IN_EP_DATA_FREE field. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE_Pos = 0x1 + // Bit mask of SERIAL_IN_EP_DATA_FREE field. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE_Msk = 0x2 + // Bit SERIAL_IN_EP_DATA_FREE. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE = 0x2 + // Position of SERIAL_OUT_EP_DATA_AVAIL field. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL_Pos = 0x2 + // Bit mask of SERIAL_OUT_EP_DATA_AVAIL field. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL_Msk = 0x4 + // Bit SERIAL_OUT_EP_DATA_AVAIL. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL = 0x4 + + // INT_RAW: Interrupt raw status register. + // Position of JTAG_IN_FLUSH_INT_RAW field. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_RAW field. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_RAW. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW = 0x1 + // Position of SOF_INT_RAW field. + USB_DEVICE_INT_RAW_SOF_INT_RAW_Pos = 0x1 + // Bit mask of SOF_INT_RAW field. + USB_DEVICE_INT_RAW_SOF_INT_RAW_Msk = 0x2 + // Bit SOF_INT_RAW. + USB_DEVICE_INT_RAW_SOF_INT_RAW = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_RAW. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW = 0x4 + // Position of SERIAL_IN_EMPTY_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_RAW. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW = 0x8 + // Position of PID_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW_Pos = 0x4 + // Bit mask of PID_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW_Msk = 0x10 + // Bit PID_ERR_INT_RAW. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW = 0x10 + // Position of CRC5_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW_Msk = 0x20 + // Bit CRC5_ERR_INT_RAW. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW = 0x20 + // Position of CRC16_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW_Msk = 0x40 + // Bit CRC16_ERR_INT_RAW. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW = 0x40 + // Position of STUFF_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW_Msk = 0x80 + // Bit STUFF_ERR_INT_RAW. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_RAW field. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_RAW field. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_RAW. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW = 0x100 + // Position of USB_BUS_RESET_INT_RAW field. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_RAW field. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW_Msk = 0x200 + // Bit USB_BUS_RESET_INT_RAW. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_RAW. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_RAW. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW = 0x800 + // Position of RTS_CHG_INT_RAW field. + USB_DEVICE_INT_RAW_RTS_CHG_INT_RAW_Pos = 0xc + // Bit mask of RTS_CHG_INT_RAW field. + USB_DEVICE_INT_RAW_RTS_CHG_INT_RAW_Msk = 0x1000 + // Bit RTS_CHG_INT_RAW. + USB_DEVICE_INT_RAW_RTS_CHG_INT_RAW = 0x1000 + // Position of DTR_CHG_INT_RAW field. + USB_DEVICE_INT_RAW_DTR_CHG_INT_RAW_Pos = 0xd + // Bit mask of DTR_CHG_INT_RAW field. + USB_DEVICE_INT_RAW_DTR_CHG_INT_RAW_Msk = 0x2000 + // Bit DTR_CHG_INT_RAW. + USB_DEVICE_INT_RAW_DTR_CHG_INT_RAW = 0x2000 + // Position of GET_LINE_CODE_INT_RAW field. + USB_DEVICE_INT_RAW_GET_LINE_CODE_INT_RAW_Pos = 0xe + // Bit mask of GET_LINE_CODE_INT_RAW field. + USB_DEVICE_INT_RAW_GET_LINE_CODE_INT_RAW_Msk = 0x4000 + // Bit GET_LINE_CODE_INT_RAW. + USB_DEVICE_INT_RAW_GET_LINE_CODE_INT_RAW = 0x4000 + // Position of SET_LINE_CODE_INT_RAW field. + USB_DEVICE_INT_RAW_SET_LINE_CODE_INT_RAW_Pos = 0xf + // Bit mask of SET_LINE_CODE_INT_RAW field. + USB_DEVICE_INT_RAW_SET_LINE_CODE_INT_RAW_Msk = 0x8000 + // Bit SET_LINE_CODE_INT_RAW. + USB_DEVICE_INT_RAW_SET_LINE_CODE_INT_RAW = 0x8000 + + // INT_ST: Interrupt status register. + // Position of JTAG_IN_FLUSH_INT_ST field. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_ST field. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_ST. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST = 0x1 + // Position of SOF_INT_ST field. + USB_DEVICE_INT_ST_SOF_INT_ST_Pos = 0x1 + // Bit mask of SOF_INT_ST field. + USB_DEVICE_INT_ST_SOF_INT_ST_Msk = 0x2 + // Bit SOF_INT_ST. + USB_DEVICE_INT_ST_SOF_INT_ST = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_ST. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST = 0x4 + // Position of SERIAL_IN_EMPTY_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_ST. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST = 0x8 + // Position of PID_ERR_INT_ST field. + USB_DEVICE_INT_ST_PID_ERR_INT_ST_Pos = 0x4 + // Bit mask of PID_ERR_INT_ST field. + USB_DEVICE_INT_ST_PID_ERR_INT_ST_Msk = 0x10 + // Bit PID_ERR_INT_ST. + USB_DEVICE_INT_ST_PID_ERR_INT_ST = 0x10 + // Position of CRC5_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST_Msk = 0x20 + // Bit CRC5_ERR_INT_ST. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST = 0x20 + // Position of CRC16_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST_Msk = 0x40 + // Bit CRC16_ERR_INT_ST. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST = 0x40 + // Position of STUFF_ERR_INT_ST field. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_ST field. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST_Msk = 0x80 + // Bit STUFF_ERR_INT_ST. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_ST field. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_ST field. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_ST. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST = 0x100 + // Position of USB_BUS_RESET_INT_ST field. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_ST field. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST_Msk = 0x200 + // Bit USB_BUS_RESET_INT_ST. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_ST. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_ST. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST = 0x800 + // Position of RTS_CHG_INT_ST field. + USB_DEVICE_INT_ST_RTS_CHG_INT_ST_Pos = 0xc + // Bit mask of RTS_CHG_INT_ST field. + USB_DEVICE_INT_ST_RTS_CHG_INT_ST_Msk = 0x1000 + // Bit RTS_CHG_INT_ST. + USB_DEVICE_INT_ST_RTS_CHG_INT_ST = 0x1000 + // Position of DTR_CHG_INT_ST field. + USB_DEVICE_INT_ST_DTR_CHG_INT_ST_Pos = 0xd + // Bit mask of DTR_CHG_INT_ST field. + USB_DEVICE_INT_ST_DTR_CHG_INT_ST_Msk = 0x2000 + // Bit DTR_CHG_INT_ST. + USB_DEVICE_INT_ST_DTR_CHG_INT_ST = 0x2000 + // Position of GET_LINE_CODE_INT_ST field. + USB_DEVICE_INT_ST_GET_LINE_CODE_INT_ST_Pos = 0xe + // Bit mask of GET_LINE_CODE_INT_ST field. + USB_DEVICE_INT_ST_GET_LINE_CODE_INT_ST_Msk = 0x4000 + // Bit GET_LINE_CODE_INT_ST. + USB_DEVICE_INT_ST_GET_LINE_CODE_INT_ST = 0x4000 + // Position of SET_LINE_CODE_INT_ST field. + USB_DEVICE_INT_ST_SET_LINE_CODE_INT_ST_Pos = 0xf + // Bit mask of SET_LINE_CODE_INT_ST field. + USB_DEVICE_INT_ST_SET_LINE_CODE_INT_ST_Msk = 0x8000 + // Bit SET_LINE_CODE_INT_ST. + USB_DEVICE_INT_ST_SET_LINE_CODE_INT_ST = 0x8000 + + // INT_ENA: Interrupt enable status register. + // Position of JTAG_IN_FLUSH_INT_ENA field. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_ENA field. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_ENA. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA = 0x1 + // Position of SOF_INT_ENA field. + USB_DEVICE_INT_ENA_SOF_INT_ENA_Pos = 0x1 + // Bit mask of SOF_INT_ENA field. + USB_DEVICE_INT_ENA_SOF_INT_ENA_Msk = 0x2 + // Bit SOF_INT_ENA. + USB_DEVICE_INT_ENA_SOF_INT_ENA = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_ENA. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA = 0x4 + // Position of SERIAL_IN_EMPTY_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_ENA. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA = 0x8 + // Position of PID_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA_Pos = 0x4 + // Bit mask of PID_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA_Msk = 0x10 + // Bit PID_ERR_INT_ENA. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA = 0x10 + // Position of CRC5_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA_Msk = 0x20 + // Bit CRC5_ERR_INT_ENA. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA = 0x20 + // Position of CRC16_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA_Msk = 0x40 + // Bit CRC16_ERR_INT_ENA. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA = 0x40 + // Position of STUFF_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA_Msk = 0x80 + // Bit STUFF_ERR_INT_ENA. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_ENA field. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_ENA field. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_ENA. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA = 0x100 + // Position of USB_BUS_RESET_INT_ENA field. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_ENA field. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA_Msk = 0x200 + // Bit USB_BUS_RESET_INT_ENA. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_ENA. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_ENA. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA = 0x800 + // Position of RTS_CHG_INT_ENA field. + USB_DEVICE_INT_ENA_RTS_CHG_INT_ENA_Pos = 0xc + // Bit mask of RTS_CHG_INT_ENA field. + USB_DEVICE_INT_ENA_RTS_CHG_INT_ENA_Msk = 0x1000 + // Bit RTS_CHG_INT_ENA. + USB_DEVICE_INT_ENA_RTS_CHG_INT_ENA = 0x1000 + // Position of DTR_CHG_INT_ENA field. + USB_DEVICE_INT_ENA_DTR_CHG_INT_ENA_Pos = 0xd + // Bit mask of DTR_CHG_INT_ENA field. + USB_DEVICE_INT_ENA_DTR_CHG_INT_ENA_Msk = 0x2000 + // Bit DTR_CHG_INT_ENA. + USB_DEVICE_INT_ENA_DTR_CHG_INT_ENA = 0x2000 + // Position of GET_LINE_CODE_INT_ENA field. + USB_DEVICE_INT_ENA_GET_LINE_CODE_INT_ENA_Pos = 0xe + // Bit mask of GET_LINE_CODE_INT_ENA field. + USB_DEVICE_INT_ENA_GET_LINE_CODE_INT_ENA_Msk = 0x4000 + // Bit GET_LINE_CODE_INT_ENA. + USB_DEVICE_INT_ENA_GET_LINE_CODE_INT_ENA = 0x4000 + // Position of SET_LINE_CODE_INT_ENA field. + USB_DEVICE_INT_ENA_SET_LINE_CODE_INT_ENA_Pos = 0xf + // Bit mask of SET_LINE_CODE_INT_ENA field. + USB_DEVICE_INT_ENA_SET_LINE_CODE_INT_ENA_Msk = 0x8000 + // Bit SET_LINE_CODE_INT_ENA. + USB_DEVICE_INT_ENA_SET_LINE_CODE_INT_ENA = 0x8000 + + // INT_CLR: Interrupt clear status register. + // Position of JTAG_IN_FLUSH_INT_CLR field. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_CLR field. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_CLR. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR = 0x1 + // Position of SOF_INT_CLR field. + USB_DEVICE_INT_CLR_SOF_INT_CLR_Pos = 0x1 + // Bit mask of SOF_INT_CLR field. + USB_DEVICE_INT_CLR_SOF_INT_CLR_Msk = 0x2 + // Bit SOF_INT_CLR. + USB_DEVICE_INT_CLR_SOF_INT_CLR = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_CLR. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR = 0x4 + // Position of SERIAL_IN_EMPTY_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_CLR. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR = 0x8 + // Position of PID_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR_Pos = 0x4 + // Bit mask of PID_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR_Msk = 0x10 + // Bit PID_ERR_INT_CLR. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR = 0x10 + // Position of CRC5_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR_Msk = 0x20 + // Bit CRC5_ERR_INT_CLR. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR = 0x20 + // Position of CRC16_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR_Msk = 0x40 + // Bit CRC16_ERR_INT_CLR. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR = 0x40 + // Position of STUFF_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR_Msk = 0x80 + // Bit STUFF_ERR_INT_CLR. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_CLR field. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_CLR field. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_CLR. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR = 0x100 + // Position of USB_BUS_RESET_INT_CLR field. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_CLR field. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR_Msk = 0x200 + // Bit USB_BUS_RESET_INT_CLR. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_CLR. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_CLR. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR = 0x800 + // Position of RTS_CHG_INT_CLR field. + USB_DEVICE_INT_CLR_RTS_CHG_INT_CLR_Pos = 0xc + // Bit mask of RTS_CHG_INT_CLR field. + USB_DEVICE_INT_CLR_RTS_CHG_INT_CLR_Msk = 0x1000 + // Bit RTS_CHG_INT_CLR. + USB_DEVICE_INT_CLR_RTS_CHG_INT_CLR = 0x1000 + // Position of DTR_CHG_INT_CLR field. + USB_DEVICE_INT_CLR_DTR_CHG_INT_CLR_Pos = 0xd + // Bit mask of DTR_CHG_INT_CLR field. + USB_DEVICE_INT_CLR_DTR_CHG_INT_CLR_Msk = 0x2000 + // Bit DTR_CHG_INT_CLR. + USB_DEVICE_INT_CLR_DTR_CHG_INT_CLR = 0x2000 + // Position of GET_LINE_CODE_INT_CLR field. + USB_DEVICE_INT_CLR_GET_LINE_CODE_INT_CLR_Pos = 0xe + // Bit mask of GET_LINE_CODE_INT_CLR field. + USB_DEVICE_INT_CLR_GET_LINE_CODE_INT_CLR_Msk = 0x4000 + // Bit GET_LINE_CODE_INT_CLR. + USB_DEVICE_INT_CLR_GET_LINE_CODE_INT_CLR = 0x4000 + // Position of SET_LINE_CODE_INT_CLR field. + USB_DEVICE_INT_CLR_SET_LINE_CODE_INT_CLR_Pos = 0xf + // Bit mask of SET_LINE_CODE_INT_CLR field. + USB_DEVICE_INT_CLR_SET_LINE_CODE_INT_CLR_Msk = 0x8000 + // Bit SET_LINE_CODE_INT_CLR. + USB_DEVICE_INT_CLR_SET_LINE_CODE_INT_CLR = 0x8000 + + // CONF0: PHY hardware configuration. + // Position of PHY_SEL field. + USB_DEVICE_CONF0_PHY_SEL_Pos = 0x0 + // Bit mask of PHY_SEL field. + USB_DEVICE_CONF0_PHY_SEL_Msk = 0x1 + // Bit PHY_SEL. + USB_DEVICE_CONF0_PHY_SEL = 0x1 + // Position of EXCHG_PINS_OVERRIDE field. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE_Pos = 0x1 + // Bit mask of EXCHG_PINS_OVERRIDE field. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE_Msk = 0x2 + // Bit EXCHG_PINS_OVERRIDE. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE = 0x2 + // Position of EXCHG_PINS field. + USB_DEVICE_CONF0_EXCHG_PINS_Pos = 0x2 + // Bit mask of EXCHG_PINS field. + USB_DEVICE_CONF0_EXCHG_PINS_Msk = 0x4 + // Bit EXCHG_PINS. + USB_DEVICE_CONF0_EXCHG_PINS = 0x4 + // Position of VREFH field. + USB_DEVICE_CONF0_VREFH_Pos = 0x3 + // Bit mask of VREFH field. + USB_DEVICE_CONF0_VREFH_Msk = 0x18 + // Position of VREFL field. + USB_DEVICE_CONF0_VREFL_Pos = 0x5 + // Bit mask of VREFL field. + USB_DEVICE_CONF0_VREFL_Msk = 0x60 + // Position of VREF_OVERRIDE field. + USB_DEVICE_CONF0_VREF_OVERRIDE_Pos = 0x7 + // Bit mask of VREF_OVERRIDE field. + USB_DEVICE_CONF0_VREF_OVERRIDE_Msk = 0x80 + // Bit VREF_OVERRIDE. + USB_DEVICE_CONF0_VREF_OVERRIDE = 0x80 + // Position of PAD_PULL_OVERRIDE field. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE_Pos = 0x8 + // Bit mask of PAD_PULL_OVERRIDE field. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE_Msk = 0x100 + // Bit PAD_PULL_OVERRIDE. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE = 0x100 + // Position of DP_PULLUP field. + USB_DEVICE_CONF0_DP_PULLUP_Pos = 0x9 + // Bit mask of DP_PULLUP field. + USB_DEVICE_CONF0_DP_PULLUP_Msk = 0x200 + // Bit DP_PULLUP. + USB_DEVICE_CONF0_DP_PULLUP = 0x200 + // Position of DP_PULLDOWN field. + USB_DEVICE_CONF0_DP_PULLDOWN_Pos = 0xa + // Bit mask of DP_PULLDOWN field. + USB_DEVICE_CONF0_DP_PULLDOWN_Msk = 0x400 + // Bit DP_PULLDOWN. + USB_DEVICE_CONF0_DP_PULLDOWN = 0x400 + // Position of DM_PULLUP field. + USB_DEVICE_CONF0_DM_PULLUP_Pos = 0xb + // Bit mask of DM_PULLUP field. + USB_DEVICE_CONF0_DM_PULLUP_Msk = 0x800 + // Bit DM_PULLUP. + USB_DEVICE_CONF0_DM_PULLUP = 0x800 + // Position of DM_PULLDOWN field. + USB_DEVICE_CONF0_DM_PULLDOWN_Pos = 0xc + // Bit mask of DM_PULLDOWN field. + USB_DEVICE_CONF0_DM_PULLDOWN_Msk = 0x1000 + // Bit DM_PULLDOWN. + USB_DEVICE_CONF0_DM_PULLDOWN = 0x1000 + // Position of PULLUP_VALUE field. + USB_DEVICE_CONF0_PULLUP_VALUE_Pos = 0xd + // Bit mask of PULLUP_VALUE field. + USB_DEVICE_CONF0_PULLUP_VALUE_Msk = 0x2000 + // Bit PULLUP_VALUE. + USB_DEVICE_CONF0_PULLUP_VALUE = 0x2000 + // Position of USB_PAD_ENABLE field. + USB_DEVICE_CONF0_USB_PAD_ENABLE_Pos = 0xe + // Bit mask of USB_PAD_ENABLE field. + USB_DEVICE_CONF0_USB_PAD_ENABLE_Msk = 0x4000 + // Bit USB_PAD_ENABLE. + USB_DEVICE_CONF0_USB_PAD_ENABLE = 0x4000 + // Position of USB_JTAG_BRIDGE_EN field. + USB_DEVICE_CONF0_USB_JTAG_BRIDGE_EN_Pos = 0xf + // Bit mask of USB_JTAG_BRIDGE_EN field. + USB_DEVICE_CONF0_USB_JTAG_BRIDGE_EN_Msk = 0x8000 + // Bit USB_JTAG_BRIDGE_EN. + USB_DEVICE_CONF0_USB_JTAG_BRIDGE_EN = 0x8000 + + // TEST: Registers used for debugging the PHY. + // Position of TEST_ENABLE field. + USB_DEVICE_TEST_TEST_ENABLE_Pos = 0x0 + // Bit mask of TEST_ENABLE field. + USB_DEVICE_TEST_TEST_ENABLE_Msk = 0x1 + // Bit TEST_ENABLE. + USB_DEVICE_TEST_TEST_ENABLE = 0x1 + // Position of TEST_USB_OE field. + USB_DEVICE_TEST_TEST_USB_OE_Pos = 0x1 + // Bit mask of TEST_USB_OE field. + USB_DEVICE_TEST_TEST_USB_OE_Msk = 0x2 + // Bit TEST_USB_OE. + USB_DEVICE_TEST_TEST_USB_OE = 0x2 + // Position of TEST_TX_DP field. + USB_DEVICE_TEST_TEST_TX_DP_Pos = 0x2 + // Bit mask of TEST_TX_DP field. + USB_DEVICE_TEST_TEST_TX_DP_Msk = 0x4 + // Bit TEST_TX_DP. + USB_DEVICE_TEST_TEST_TX_DP = 0x4 + // Position of TEST_TX_DM field. + USB_DEVICE_TEST_TEST_TX_DM_Pos = 0x3 + // Bit mask of TEST_TX_DM field. + USB_DEVICE_TEST_TEST_TX_DM_Msk = 0x8 + // Bit TEST_TX_DM. + USB_DEVICE_TEST_TEST_TX_DM = 0x8 + // Position of TEST_RX_RCV field. + USB_DEVICE_TEST_TEST_RX_RCV_Pos = 0x4 + // Bit mask of TEST_RX_RCV field. + USB_DEVICE_TEST_TEST_RX_RCV_Msk = 0x10 + // Bit TEST_RX_RCV. + USB_DEVICE_TEST_TEST_RX_RCV = 0x10 + // Position of TEST_RX_DP field. + USB_DEVICE_TEST_TEST_RX_DP_Pos = 0x5 + // Bit mask of TEST_RX_DP field. + USB_DEVICE_TEST_TEST_RX_DP_Msk = 0x20 + // Bit TEST_RX_DP. + USB_DEVICE_TEST_TEST_RX_DP = 0x20 + // Position of TEST_RX_DM field. + USB_DEVICE_TEST_TEST_RX_DM_Pos = 0x6 + // Bit mask of TEST_RX_DM field. + USB_DEVICE_TEST_TEST_RX_DM_Msk = 0x40 + // Bit TEST_RX_DM. + USB_DEVICE_TEST_TEST_RX_DM = 0x40 + + // JFIFO_ST: JTAG FIFO status and control registers. + // Position of IN_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_IN_FIFO_CNT_Pos = 0x0 + // Bit mask of IN_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_IN_FIFO_CNT_Msk = 0x3 + // Position of IN_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY_Pos = 0x2 + // Bit mask of IN_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY_Msk = 0x4 + // Bit IN_FIFO_EMPTY. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY = 0x4 + // Position of IN_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL_Pos = 0x3 + // Bit mask of IN_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL_Msk = 0x8 + // Bit IN_FIFO_FULL. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL = 0x8 + // Position of OUT_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_CNT_Pos = 0x4 + // Bit mask of OUT_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_CNT_Msk = 0x30 + // Position of OUT_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY_Pos = 0x6 + // Bit mask of OUT_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY_Msk = 0x40 + // Bit OUT_FIFO_EMPTY. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY = 0x40 + // Position of OUT_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL_Pos = 0x7 + // Bit mask of OUT_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL_Msk = 0x80 + // Bit OUT_FIFO_FULL. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL = 0x80 + // Position of IN_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET_Pos = 0x8 + // Bit mask of IN_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET_Msk = 0x100 + // Bit IN_FIFO_RESET. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET = 0x100 + // Position of OUT_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET_Pos = 0x9 + // Bit mask of OUT_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET_Msk = 0x200 + // Bit OUT_FIFO_RESET. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET = 0x200 + + // FRAM_NUM: Last received SOF frame index register. + // Position of SOF_FRAME_INDEX field. + USB_DEVICE_FRAM_NUM_SOF_FRAME_INDEX_Pos = 0x0 + // Bit mask of SOF_FRAME_INDEX field. + USB_DEVICE_FRAM_NUM_SOF_FRAME_INDEX_Msk = 0x7ff + + // IN_EP0_ST: Control IN endpoint status information. + // Position of IN_EP0_STATE field. + USB_DEVICE_IN_EP0_ST_IN_EP0_STATE_Pos = 0x0 + // Bit mask of IN_EP0_STATE field. + USB_DEVICE_IN_EP0_ST_IN_EP0_STATE_Msk = 0x3 + // Position of IN_EP0_WR_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP0_WR_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_WR_ADDR_Msk = 0x1fc + // Position of IN_EP0_RD_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP0_RD_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_RD_ADDR_Msk = 0xfe00 + + // IN_EP1_ST: CDC-ACM IN endpoint status information. + // Position of IN_EP1_STATE field. + USB_DEVICE_IN_EP1_ST_IN_EP1_STATE_Pos = 0x0 + // Bit mask of IN_EP1_STATE field. + USB_DEVICE_IN_EP1_ST_IN_EP1_STATE_Msk = 0x3 + // Position of IN_EP1_WR_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP1_WR_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_WR_ADDR_Msk = 0x1fc + // Position of IN_EP1_RD_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP1_RD_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_RD_ADDR_Msk = 0xfe00 + + // IN_EP2_ST: CDC-ACM interrupt IN endpoint status information. + // Position of IN_EP2_STATE field. + USB_DEVICE_IN_EP2_ST_IN_EP2_STATE_Pos = 0x0 + // Bit mask of IN_EP2_STATE field. + USB_DEVICE_IN_EP2_ST_IN_EP2_STATE_Msk = 0x3 + // Position of IN_EP2_WR_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP2_WR_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_WR_ADDR_Msk = 0x1fc + // Position of IN_EP2_RD_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP2_RD_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_RD_ADDR_Msk = 0xfe00 + + // IN_EP3_ST: JTAG IN endpoint status information. + // Position of IN_EP3_STATE field. + USB_DEVICE_IN_EP3_ST_IN_EP3_STATE_Pos = 0x0 + // Bit mask of IN_EP3_STATE field. + USB_DEVICE_IN_EP3_ST_IN_EP3_STATE_Msk = 0x3 + // Position of IN_EP3_WR_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP3_WR_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_WR_ADDR_Msk = 0x1fc + // Position of IN_EP3_RD_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP3_RD_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_RD_ADDR_Msk = 0xfe00 + + // OUT_EP0_ST: Control OUT endpoint status information. + // Position of OUT_EP0_STATE field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_STATE_Pos = 0x0 + // Bit mask of OUT_EP0_STATE field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_STATE_Msk = 0x3 + // Position of OUT_EP0_WR_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP0_WR_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP0_RD_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP0_RD_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_RD_ADDR_Msk = 0xfe00 + + // OUT_EP1_ST: CDC-ACM OUT endpoint status information. + // Position of OUT_EP1_STATE field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_STATE_Pos = 0x0 + // Bit mask of OUT_EP1_STATE field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_STATE_Msk = 0x3 + // Position of OUT_EP1_WR_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP1_WR_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP1_RD_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP1_RD_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_RD_ADDR_Msk = 0xfe00 + // Position of OUT_EP1_REC_DATA_CNT field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_REC_DATA_CNT_Pos = 0x10 + // Bit mask of OUT_EP1_REC_DATA_CNT field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_REC_DATA_CNT_Msk = 0x7f0000 + + // OUT_EP2_ST: JTAG OUT endpoint status information. + // Position of OUT_EP2_STATE field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_STATE_Pos = 0x0 + // Bit mask of OUT_EP2_STATE field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_STATE_Msk = 0x3 + // Position of OUT_EP2_WR_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP2_WR_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP2_RD_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP2_RD_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_RD_ADDR_Msk = 0xfe00 + + // MISC_CONF: Clock enable control + // Position of CLK_EN field. + USB_DEVICE_MISC_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + USB_DEVICE_MISC_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + USB_DEVICE_MISC_CONF_CLK_EN = 0x1 + + // MEM_CONF: Memory power control + // Position of USB_MEM_PD field. + USB_DEVICE_MEM_CONF_USB_MEM_PD_Pos = 0x0 + // Bit mask of USB_MEM_PD field. + USB_DEVICE_MEM_CONF_USB_MEM_PD_Msk = 0x1 + // Bit USB_MEM_PD. + USB_DEVICE_MEM_CONF_USB_MEM_PD = 0x1 + // Position of USB_MEM_CLK_EN field. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN_Pos = 0x1 + // Bit mask of USB_MEM_CLK_EN field. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN_Msk = 0x2 + // Bit USB_MEM_CLK_EN. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN = 0x2 + + // CHIP_RST: CDC-ACM chip reset control. + // Position of RTS field. + USB_DEVICE_CHIP_RST_RTS_Pos = 0x0 + // Bit mask of RTS field. + USB_DEVICE_CHIP_RST_RTS_Msk = 0x1 + // Bit RTS. + USB_DEVICE_CHIP_RST_RTS = 0x1 + // Position of DTR field. + USB_DEVICE_CHIP_RST_DTR_Pos = 0x1 + // Bit mask of DTR field. + USB_DEVICE_CHIP_RST_DTR_Msk = 0x2 + // Bit DTR. + USB_DEVICE_CHIP_RST_DTR = 0x2 + // Position of USB_UART_CHIP_RST_DIS field. + USB_DEVICE_CHIP_RST_USB_UART_CHIP_RST_DIS_Pos = 0x2 + // Bit mask of USB_UART_CHIP_RST_DIS field. + USB_DEVICE_CHIP_RST_USB_UART_CHIP_RST_DIS_Msk = 0x4 + // Bit USB_UART_CHIP_RST_DIS. + USB_DEVICE_CHIP_RST_USB_UART_CHIP_RST_DIS = 0x4 + + // SET_LINE_CODE_W0: W0 of SET_LINE_CODING command. + // Position of DW_DTE_RATE field. + USB_DEVICE_SET_LINE_CODE_W0_DW_DTE_RATE_Pos = 0x0 + // Bit mask of DW_DTE_RATE field. + USB_DEVICE_SET_LINE_CODE_W0_DW_DTE_RATE_Msk = 0xffffffff + + // SET_LINE_CODE_W1: W1 of SET_LINE_CODING command. + // Position of BCHAR_FORMAT field. + USB_DEVICE_SET_LINE_CODE_W1_BCHAR_FORMAT_Pos = 0x0 + // Bit mask of BCHAR_FORMAT field. + USB_DEVICE_SET_LINE_CODE_W1_BCHAR_FORMAT_Msk = 0xff + // Position of BPARITY_TYPE field. + USB_DEVICE_SET_LINE_CODE_W1_BPARITY_TYPE_Pos = 0x8 + // Bit mask of BPARITY_TYPE field. + USB_DEVICE_SET_LINE_CODE_W1_BPARITY_TYPE_Msk = 0xff00 + // Position of BDATA_BITS field. + USB_DEVICE_SET_LINE_CODE_W1_BDATA_BITS_Pos = 0x10 + // Bit mask of BDATA_BITS field. + USB_DEVICE_SET_LINE_CODE_W1_BDATA_BITS_Msk = 0xff0000 + + // GET_LINE_CODE_W0: W0 of GET_LINE_CODING command. + // Position of GET_DW_DTE_RATE field. + USB_DEVICE_GET_LINE_CODE_W0_GET_DW_DTE_RATE_Pos = 0x0 + // Bit mask of GET_DW_DTE_RATE field. + USB_DEVICE_GET_LINE_CODE_W0_GET_DW_DTE_RATE_Msk = 0xffffffff + + // GET_LINE_CODE_W1: W1 of GET_LINE_CODING command. + // Position of GET_BDATA_BITS field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BDATA_BITS_Pos = 0x0 + // Bit mask of GET_BDATA_BITS field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BDATA_BITS_Msk = 0xff + // Position of GET_BPARITY_TYPE field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BPARITY_TYPE_Pos = 0x8 + // Bit mask of GET_BPARITY_TYPE field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BPARITY_TYPE_Msk = 0xff00 + // Position of GET_BCHAR_FORMAT field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BCHAR_FORMAT_Pos = 0x10 + // Bit mask of GET_BCHAR_FORMAT field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BCHAR_FORMAT_Msk = 0xff0000 + + // CONFIG_UPDATE: Configuration registers' value update + // Position of CONFIG_UPDATE field. + USB_DEVICE_CONFIG_UPDATE_CONFIG_UPDATE_Pos = 0x0 + // Bit mask of CONFIG_UPDATE field. + USB_DEVICE_CONFIG_UPDATE_CONFIG_UPDATE_Msk = 0x1 + // Bit CONFIG_UPDATE. + USB_DEVICE_CONFIG_UPDATE_CONFIG_UPDATE = 0x1 + + // SER_AFIFO_CONFIG: Serial AFIFO configure register + // Position of SERIAL_IN_AFIFO_RESET_WR field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR_Pos = 0x0 + // Bit mask of SERIAL_IN_AFIFO_RESET_WR field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR_Msk = 0x1 + // Bit SERIAL_IN_AFIFO_RESET_WR. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR = 0x1 + // Position of SERIAL_IN_AFIFO_RESET_RD field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD_Pos = 0x1 + // Bit mask of SERIAL_IN_AFIFO_RESET_RD field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD_Msk = 0x2 + // Bit SERIAL_IN_AFIFO_RESET_RD. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD = 0x2 + // Position of SERIAL_OUT_AFIFO_RESET_WR field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR_Pos = 0x2 + // Bit mask of SERIAL_OUT_AFIFO_RESET_WR field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR_Msk = 0x4 + // Bit SERIAL_OUT_AFIFO_RESET_WR. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR = 0x4 + // Position of SERIAL_OUT_AFIFO_RESET_RD field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD_Pos = 0x3 + // Bit mask of SERIAL_OUT_AFIFO_RESET_RD field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD_Msk = 0x8 + // Bit SERIAL_OUT_AFIFO_RESET_RD. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD = 0x8 + // Position of SERIAL_OUT_AFIFO_REMPTY field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY_Pos = 0x4 + // Bit mask of SERIAL_OUT_AFIFO_REMPTY field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY_Msk = 0x10 + // Bit SERIAL_OUT_AFIFO_REMPTY. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY = 0x10 + // Position of SERIAL_IN_AFIFO_WFULL field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL_Pos = 0x5 + // Bit mask of SERIAL_IN_AFIFO_WFULL field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL_Msk = 0x20 + // Bit SERIAL_IN_AFIFO_WFULL. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL = 0x20 + + // BUS_RESET_ST: USB Bus reset status register + // Position of USB_BUS_RESET_ST field. + USB_DEVICE_BUS_RESET_ST_USB_BUS_RESET_ST_Pos = 0x0 + // Bit mask of USB_BUS_RESET_ST field. + USB_DEVICE_BUS_RESET_ST_USB_BUS_RESET_ST_Msk = 0x1 + // Bit USB_BUS_RESET_ST. + USB_DEVICE_BUS_RESET_ST_USB_BUS_RESET_ST = 0x1 + + // DATE: Date register + // Position of DATE field. + USB_DEVICE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + USB_DEVICE_DATE_DATE_Msk = 0xffffffff +) diff --git a/emb/device/esp/esp32c6lp.go b/emb/device/esp/esp32c6lp.go new file mode 100644 index 0000000..a19db04 --- /dev/null +++ b/emb/device/esp/esp32c6lp.go @@ -0,0 +1,9803 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32c6-lp.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32c6lp + +/* +// 32-bit RISC-V MCU +*/ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32-C6-LP" + CPU = "RV32IMAC" + FPUPresent = false + NVICPrioBits = 4 +) + +// Interrupt numbers. +const ( + // Low-power Timer + IRQ_LP_TIMER = 7 + + // Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + IRQ_LP_UART = 16 + + // Low-power I2C (Inter-Integrated Circuit) Controller + IRQ_LP_I2C = 17 + + // Low-power Watchdog Timer + IRQ_LP_WDT = 18 + + // LP_PERI Peripheral + IRQ_LP_PERI_TIMEOUT = 19 + + // Low-power Access Permission Management Controller + IRQ_LP_APM_M0 = 20 + + // Low-power Access Permission Management Controller + IRQ_LP_APM_M1 = 21 + + // Highest interrupt number on this device. + IRQ_max = 21 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_LP_TIMER: + callHandlers(IRQ_LP_TIMER) + case IRQ_LP_UART: + callHandlers(IRQ_LP_UART) + case IRQ_LP_I2C: + callHandlers(IRQ_LP_I2C) + case IRQ_LP_WDT: + callHandlers(IRQ_LP_WDT) + case IRQ_LP_PERI_TIMEOUT: + callHandlers(IRQ_LP_PERI_TIMEOUT) + case IRQ_LP_APM_M0: + callHandlers(IRQ_LP_APM_M0) + case IRQ_LP_APM_M1: + callHandlers(IRQ_LP_APM_M1) + } +} + +// Peripherals. +var ( + // Low-power I2C (Inter-Integrated Circuit) Controller + LP_I2C = (*I2C_Type)(unsafe.Pointer(uintptr(0x600b1800))) + + // LP_PERI Peripheral + LP_PERI = (*LPPERI_Type)(unsafe.Pointer(uintptr(0x600b2800))) + + // LP_ANA_PERI Peripheral + LP_ANA_PERI = (*LP_ANA_Type)(unsafe.Pointer(uintptr(0x600b2c00))) + + // LP_AON Peripheral + LP_AON = (*LP_AON_Type)(unsafe.Pointer(uintptr(0x600b1000))) + + // Low-power Access Permission Management Controller + LP_APM = (*LP_APM_Type)(unsafe.Pointer(uintptr(0x600b3800))) + + // LP_CLKRST Peripheral + LP_CLKRST = (*LP_CLKRST_Type)(unsafe.Pointer(uintptr(0x600b0400))) + + // LP_I2C_ANA_MST Peripheral + LP_I2C_ANA_MST = (*LP_I2C_ANA_MST_Type)(unsafe.Pointer(uintptr(0x600b2400))) + + // Low-power Input/Output Multiplexer + LP_IO_MUX = (*LP_IO_Type)(unsafe.Pointer(uintptr(0x600b2000))) + + // Low-power Trusted Execution Environment + LP_TEE = (*LP_TEE_Type)(unsafe.Pointer(uintptr(0x600b3400))) + + // Low-power Timer + LP_TIMER = (*LP_TIMER_Type)(unsafe.Pointer(uintptr(0x600b0c00))) + + // Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + LP_UART = (*LP_UART_Type)(unsafe.Pointer(uintptr(0x600b1400))) + + // Low-power Watchdog Timer + LP_WDT = (*LP_WDT_Type)(unsafe.Pointer(uintptr(0x600b1c00))) +) + +// Low-power I2C (Inter-Integrated Circuit) Controller +type I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + _ [4]byte + FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + FILTER_CFG volatile.Register32 // 0x50 + CLK_CONF volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + SCL_ST_TIME_OUT volatile.Register32 // 0x78 + SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C + SCL_SP_CONF volatile.Register32 // 0x80 + _ [116]byte + DATE volatile.Register32 // 0xF8 + _ [4]byte + TXFIFO_START_ADDR volatile.Register32 // 0x100 + _ [124]byte + RXFIFO_START_ADDR volatile.Register32 // 0x180 +} + +// I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL Clock +func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff +} + +// I2C.CTR: Transmission setting +func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetCTR_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetCTR_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetCTR_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetCTR_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetCTR_CONF_UPGATE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetCTR_CONF_UPGATE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11 +} + +// I2C.SR: Describe I2C work status. +func (o *I2C_Type) SetSR_RESP_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSR_RESP_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1f00)|value<<8) +} +func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x1f00) >> 8 +} +func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7c0000)|value<<18) +} +func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7c0000) >> 18 +} +func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// I2C.TO: Setting time out control for receiving data. +func (o *I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetTO_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0x1f +} +func (o *I2C_Type) SetTO_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetTO_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5 +} + +// I2C.FIFO_ST: FIFO status register. +func (o *I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 { + return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf +} +func (o *I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1e0) >> 5 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3c00)|value<<10) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3c00) >> 10 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x78000)|value<<15) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x78000) >> 15 +} + +// I2C.FIFO_CONF: FIFO configuration register. +func (o *I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xf +} +func (o *I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1e0) >> 5 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14 +} + +// I2C.DATA: Rx FIFO read data. +func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// I2C.INT_RAW: Raw interrupt status +func (o *I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} + +// I2C.INT_CLR: Interrupt clear bits +func (o *I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} + +// I2C.INT_ENA: Interrupt enable bits +func (o *I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} + +// I2C.INT_STATUS: Status of captured I2C communication events +func (o *I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15 +} + +// I2C.SDA_HOLD: Configures the hold time after a negative SCL edge. +func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff +} + +// I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge. +func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff +} + +// I2C.SCL_HIGH_PERIOD: Configures the high level width of SCL +func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff +} +func (o *I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9 +} + +// I2C.SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition +func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA +func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff +} + +// I2C.FILTER_CFG: SCL and SDA filter configuration register +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4 +} +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9 +} + +// I2C.CLK_CONF: I2C CLK configuration register +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} + +// I2C.COMD0: I2C command register 0 +func (o *I2C_Type) SetCOMD0_COMMAND0(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD0_COMMAND0() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD0_COMMAND0_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD0_COMMAND0_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD1: I2C command register 1 +func (o *I2C_Type) SetCOMD1_COMMAND1(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD1_COMMAND1() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD1_COMMAND1_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD1_COMMAND1_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD2: I2C command register 2 +func (o *I2C_Type) SetCOMD2_COMMAND2(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD2_COMMAND2() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD2_COMMAND2_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD2_COMMAND2_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD3: I2C command register 3 +func (o *I2C_Type) SetCOMD3_COMMAND3(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD3_COMMAND3() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD3_COMMAND3_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD3_COMMAND3_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD4: I2C command register 4 +func (o *I2C_Type) SetCOMD4_COMMAND4(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD4_COMMAND4() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD4_COMMAND4_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD4_COMMAND4_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD5: I2C command register 5 +func (o *I2C_Type) SetCOMD5_COMMAND5(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD5_COMMAND5() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD5_COMMAND5_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD5_COMMAND5_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD6: I2C command register 6 +func (o *I2C_Type) SetCOMD6_COMMAND6(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD6_COMMAND6() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD6_COMMAND6_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD6_COMMAND6_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD7: I2C command register 7 +func (o *I2C_Type) SetCOMD7_COMMAND7(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD7_COMMAND7() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD7_COMMAND7_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD7_COMMAND7_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// I2C.SCL_ST_TIME_OUT: SCL status time out register +func (o *I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register +func (o *I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_SP_CONF: Power configuration register +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// I2C.DATE: Version register +func (o *I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2C.TXFIFO_START_ADDR: I2C TXFIFO base address register +func (o *I2C_Type) SetTXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetTXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg) +} + +// I2C.RXFIFO_START_ADDR: I2C RXFIFO base address register +func (o *I2C_Type) SetRXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetRXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg) +} + +// LP_PERI Peripheral +type LPPERI_Type struct { + CLK_EN volatile.Register32 // 0x0 + RESET_EN volatile.Register32 // 0x4 + RNG_DATA volatile.Register32 // 0x8 + CPU volatile.Register32 // 0xC + BUS_TIMEOUT volatile.Register32 // 0x10 + BUS_TIMEOUT_ADDR volatile.Register32 // 0x14 + BUS_TIMEOUT_UID volatile.Register32 // 0x18 + MEM_CTRL volatile.Register32 // 0x1C + INTERRUPT_SOURCE volatile.Register32 // 0x20 + _ [984]byte + DATE volatile.Register32 // 0x3FC +} + +// LPPERI.CLK_EN: need_des +func (o *LPPERI_Type) SetCLK_EN_LP_TOUCH_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x800000)|value<<23) +} +func (o *LPPERI_Type) GetCLK_EN_LP_TOUCH_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x800000) >> 23 +} +func (o *LPPERI_Type) SetCLK_EN_RNG_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *LPPERI_Type) GetCLK_EN_RNG_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1000000) >> 24 +} +func (o *LPPERI_Type) SetCLK_EN_OTP_DBG_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *LPPERI_Type) GetCLK_EN_OTP_DBG_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x2000000) >> 25 +} +func (o *LPPERI_Type) SetCLK_EN_LP_UART_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LPPERI_Type) GetCLK_EN_LP_UART_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x4000000) >> 26 +} +func (o *LPPERI_Type) SetCLK_EN_LP_IO_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LPPERI_Type) GetCLK_EN_LP_IO_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x8000000) >> 27 +} +func (o *LPPERI_Type) SetCLK_EN_LP_EXT_I2C_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LPPERI_Type) GetCLK_EN_LP_EXT_I2C_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10000000) >> 28 +} +func (o *LPPERI_Type) SetCLK_EN_LP_ANA_I2C_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetCLK_EN_LP_ANA_I2C_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetCLK_EN_EFUSE_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetCLK_EN_EFUSE_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetCLK_EN_LP_CPU_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetCLK_EN_LP_CPU_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x80000000) >> 31 +} + +// LPPERI.RESET_EN: need_des +func (o *LPPERI_Type) SetRESET_EN_BUS_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x800000)|value<<23) +} +func (o *LPPERI_Type) GetRESET_EN_BUS_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x800000) >> 23 +} +func (o *LPPERI_Type) SetRESET_EN_LP_TOUCH_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *LPPERI_Type) GetRESET_EN_LP_TOUCH_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x1000000) >> 24 +} +func (o *LPPERI_Type) SetRESET_EN_OTP_DBG_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *LPPERI_Type) GetRESET_EN_OTP_DBG_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x2000000) >> 25 +} +func (o *LPPERI_Type) SetRESET_EN_LP_UART_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LPPERI_Type) GetRESET_EN_LP_UART_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x4000000) >> 26 +} +func (o *LPPERI_Type) SetRESET_EN_LP_IO_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LPPERI_Type) GetRESET_EN_LP_IO_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x8000000) >> 27 +} +func (o *LPPERI_Type) SetRESET_EN_LP_EXT_I2C_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LPPERI_Type) GetRESET_EN_LP_EXT_I2C_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x10000000) >> 28 +} +func (o *LPPERI_Type) SetRESET_EN_LP_ANA_I2C_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetRESET_EN_LP_ANA_I2C_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetRESET_EN_EFUSE_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetRESET_EN_EFUSE_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetRESET_EN_LP_CPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetRESET_EN_LP_CPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x80000000) >> 31 +} + +// LPPERI.RNG_DATA: need_des +func (o *LPPERI_Type) SetRNG_DATA(value uint32) { + volatile.StoreUint32(&o.RNG_DATA.Reg, value) +} +func (o *LPPERI_Type) GetRNG_DATA() uint32 { + return volatile.LoadUint32(&o.RNG_DATA.Reg) +} + +// LPPERI.CPU: need_des +func (o *LPPERI_Type) SetCPU_LPCORE_DBGM_UNAVALIABLE(value uint32) { + volatile.StoreUint32(&o.CPU.Reg, volatile.LoadUint32(&o.CPU.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetCPU_LPCORE_DBGM_UNAVALIABLE() uint32 { + return (volatile.LoadUint32(&o.CPU.Reg) & 0x80000000) >> 31 +} + +// LPPERI.BUS_TIMEOUT: need_des +func (o *LPPERI_Type) SetBUS_TIMEOUT_LP_PERI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT.Reg)&^(0x3fffc000)|value<<14) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_LP_PERI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMEOUT.Reg) & 0x3fffc000) >> 14 +} +func (o *LPPERI_Type) SetBUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMEOUT.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetBUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMEOUT.Reg) & 0x80000000) >> 31 +} + +// LPPERI.BUS_TIMEOUT_ADDR: need_des +func (o *LPPERI_Type) SetBUS_TIMEOUT_ADDR(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT_ADDR.Reg, value) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_ADDR() uint32 { + return volatile.LoadUint32(&o.BUS_TIMEOUT_ADDR.Reg) +} + +// LPPERI.BUS_TIMEOUT_UID: need_des +func (o *LPPERI_Type) SetBUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT_UID.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT_UID.Reg)&^(0x7f)|value) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID() uint32 { + return volatile.LoadUint32(&o.BUS_TIMEOUT_UID.Reg) & 0x7f +} + +// LPPERI.MEM_CTRL: need_des +func (o *LPPERI_Type) SetMEM_CTRL_UART_WAKEUP_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x1)|value) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_WAKEUP_FLAG_CLR() uint32 { + return volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x1 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_WAKEUP_FLAG(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_WAKEUP_FLAG() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x2) >> 1 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x80000000) >> 31 +} + +// LPPERI.INTERRUPT_SOURCE: need_des +func (o *LPPERI_Type) SetINTERRUPT_SOURCE_LP_INTERRUPT_SOURCE(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_SOURCE.Reg, volatile.LoadUint32(&o.INTERRUPT_SOURCE.Reg)&^(0x3f)|value) +} +func (o *LPPERI_Type) GetINTERRUPT_SOURCE_LP_INTERRUPT_SOURCE() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_SOURCE.Reg) & 0x3f +} + +// LPPERI.DATE: need_des +func (o *LPPERI_Type) SetDATE_LPPERI_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LPPERI_Type) GetDATE_LPPERI_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LPPERI_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI Peripheral +type LP_ANA_Type struct { + BOD_MODE0_CNTL volatile.Register32 // 0x0 + BOD_MODE1_CNTL volatile.Register32 // 0x4 + CK_GLITCH_CNTL volatile.Register32 // 0x8 + FIB_ENABLE volatile.Register32 // 0xC + INT_RAW volatile.Register32 // 0x10 + INT_ST volatile.Register32 // 0x14 + INT_ENA volatile.Register32 // 0x18 + INT_CLR volatile.Register32 // 0x1C + LP_INT_RAW volatile.Register32 // 0x20 + LP_INT_ST volatile.Register32 // 0x24 + LP_INT_ENA volatile.Register32 // 0x28 + LP_INT_CLR volatile.Register32 // 0x2C + _ [972]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_ANA.BOD_MODE0_CNTL: need_des +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x40)|value<<6) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x40) >> 6 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x80)|value<<7) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x80) >> 7 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x3ff00)|value<<8) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x3ff00) >> 8 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0xffc0000)|value<<18) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0xffc0000) >> 18 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_RESET_SEL(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_RESET_SEL() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.BOD_MODE1_CNTL: need_des +func (o *LP_ANA_Type) SetBOD_MODE1_CNTL_BOD_MODE1_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE1_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE1_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetBOD_MODE1_CNTL_BOD_MODE1_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE1_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.CK_GLITCH_CNTL: need_des +func (o *LP_ANA_Type) SetCK_GLITCH_CNTL_CK_GLITCH_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.CK_GLITCH_CNTL.Reg, volatile.LoadUint32(&o.CK_GLITCH_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetCK_GLITCH_CNTL_CK_GLITCH_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.CK_GLITCH_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.FIB_ENABLE: need_des +func (o *LP_ANA_Type) SetFIB_ENABLE(value uint32) { + volatile.StoreUint32(&o.FIB_ENABLE.Reg, value) +} +func (o *LP_ANA_Type) GetFIB_ENABLE() uint32 { + return volatile.LoadUint32(&o.FIB_ENABLE.Reg) +} + +// LP_ANA.INT_RAW: need_des +func (o *LP_ANA_Type) SetINT_RAW_BOD_MODE0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_RAW_BOD_MODE0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.INT_ST: need_des +func (o *LP_ANA_Type) SetINT_ST_BOD_MODE0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_ST_BOD_MODE0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.INT_ENA: need_des +func (o *LP_ANA_Type) SetINT_ENA_BOD_MODE0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_ENA_BOD_MODE0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.INT_CLR: need_des +func (o *LP_ANA_Type) SetINT_CLR_BOD_MODE0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_CLR_BOD_MODE0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_RAW: need_des +func (o *LP_ANA_Type) SetLP_INT_RAW_BOD_MODE0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_RAW_BOD_MODE0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_ST: need_des +func (o *LP_ANA_Type) SetLP_INT_ST_BOD_MODE0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_ST_BOD_MODE0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_ENA: need_des +func (o *LP_ANA_Type) SetLP_INT_ENA_BOD_MODE0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_ENA_BOD_MODE0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_CLR: need_des +func (o *LP_ANA_Type) SetLP_INT_CLR_BOD_MODE0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_CLR_BOD_MODE0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.DATE: need_des +func (o *LP_ANA_Type) SetDATE_LP_ANA_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_ANA_Type) GetDATE_LP_ANA_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_ANA_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_AON Peripheral +type LP_AON_Type struct { + STORE0 volatile.Register32 // 0x0 + STORE1 volatile.Register32 // 0x4 + STORE2 volatile.Register32 // 0x8 + STORE3 volatile.Register32 // 0xC + STORE4 volatile.Register32 // 0x10 + STORE5 volatile.Register32 // 0x14 + STORE6 volatile.Register32 // 0x18 + STORE7 volatile.Register32 // 0x1C + STORE8 volatile.Register32 // 0x20 + STORE9 volatile.Register32 // 0x24 + GPIO_MUX volatile.Register32 // 0x28 + GPIO_HOLD0 volatile.Register32 // 0x2C + GPIO_HOLD1 volatile.Register32 // 0x30 + SYS_CFG volatile.Register32 // 0x34 + CPUCORE0_CFG volatile.Register32 // 0x38 + IO_MUX volatile.Register32 // 0x3C + EXT_WAKEUP_CNTL volatile.Register32 // 0x40 + USB volatile.Register32 // 0x44 + LPBUS volatile.Register32 // 0x48 + SDIO_ACTIVE volatile.Register32 // 0x4C + LPCORE volatile.Register32 // 0x50 + SAR_CCT volatile.Register32 // 0x54 + _ [932]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_AON.STORE0: need_des +func (o *LP_AON_Type) SetSTORE0(value uint32) { + volatile.StoreUint32(&o.STORE0.Reg, value) +} +func (o *LP_AON_Type) GetSTORE0() uint32 { + return volatile.LoadUint32(&o.STORE0.Reg) +} + +// LP_AON.STORE1: need_des +func (o *LP_AON_Type) SetSTORE1(value uint32) { + volatile.StoreUint32(&o.STORE1.Reg, value) +} +func (o *LP_AON_Type) GetSTORE1() uint32 { + return volatile.LoadUint32(&o.STORE1.Reg) +} + +// LP_AON.STORE2: need_des +func (o *LP_AON_Type) SetSTORE2(value uint32) { + volatile.StoreUint32(&o.STORE2.Reg, value) +} +func (o *LP_AON_Type) GetSTORE2() uint32 { + return volatile.LoadUint32(&o.STORE2.Reg) +} + +// LP_AON.STORE3: need_des +func (o *LP_AON_Type) SetSTORE3(value uint32) { + volatile.StoreUint32(&o.STORE3.Reg, value) +} +func (o *LP_AON_Type) GetSTORE3() uint32 { + return volatile.LoadUint32(&o.STORE3.Reg) +} + +// LP_AON.STORE4: need_des +func (o *LP_AON_Type) SetSTORE4(value uint32) { + volatile.StoreUint32(&o.STORE4.Reg, value) +} +func (o *LP_AON_Type) GetSTORE4() uint32 { + return volatile.LoadUint32(&o.STORE4.Reg) +} + +// LP_AON.STORE5: need_des +func (o *LP_AON_Type) SetSTORE5(value uint32) { + volatile.StoreUint32(&o.STORE5.Reg, value) +} +func (o *LP_AON_Type) GetSTORE5() uint32 { + return volatile.LoadUint32(&o.STORE5.Reg) +} + +// LP_AON.STORE6: need_des +func (o *LP_AON_Type) SetSTORE6(value uint32) { + volatile.StoreUint32(&o.STORE6.Reg, value) +} +func (o *LP_AON_Type) GetSTORE6() uint32 { + return volatile.LoadUint32(&o.STORE6.Reg) +} + +// LP_AON.STORE7: need_des +func (o *LP_AON_Type) SetSTORE7(value uint32) { + volatile.StoreUint32(&o.STORE7.Reg, value) +} +func (o *LP_AON_Type) GetSTORE7() uint32 { + return volatile.LoadUint32(&o.STORE7.Reg) +} + +// LP_AON.STORE8: need_des +func (o *LP_AON_Type) SetSTORE8(value uint32) { + volatile.StoreUint32(&o.STORE8.Reg, value) +} +func (o *LP_AON_Type) GetSTORE8() uint32 { + return volatile.LoadUint32(&o.STORE8.Reg) +} + +// LP_AON.STORE9: need_des +func (o *LP_AON_Type) SetSTORE9(value uint32) { + volatile.StoreUint32(&o.STORE9.Reg, value) +} +func (o *LP_AON_Type) GetSTORE9() uint32 { + return volatile.LoadUint32(&o.STORE9.Reg) +} + +// LP_AON.GPIO_MUX: need_des +func (o *LP_AON_Type) SetGPIO_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO_MUX.Reg, volatile.LoadUint32(&o.GPIO_MUX.Reg)&^(0xff)|value) +} +func (o *LP_AON_Type) GetGPIO_MUX_SEL() uint32 { + return volatile.LoadUint32(&o.GPIO_MUX.Reg) & 0xff +} + +// LP_AON.GPIO_HOLD0: need_des +func (o *LP_AON_Type) SetGPIO_HOLD0(value uint32) { + volatile.StoreUint32(&o.GPIO_HOLD0.Reg, value) +} +func (o *LP_AON_Type) GetGPIO_HOLD0() uint32 { + return volatile.LoadUint32(&o.GPIO_HOLD0.Reg) +} + +// LP_AON.GPIO_HOLD1: need_des +func (o *LP_AON_Type) SetGPIO_HOLD1(value uint32) { + volatile.StoreUint32(&o.GPIO_HOLD1.Reg, value) +} +func (o *LP_AON_Type) GetGPIO_HOLD1() uint32 { + return volatile.LoadUint32(&o.GPIO_HOLD1.Reg) +} + +// LP_AON.SYS_CFG: need_des +func (o *LP_AON_Type) SetSYS_CFG_FORCE_DOWNLOAD_BOOT(value uint32) { + volatile.StoreUint32(&o.SYS_CFG.Reg, volatile.LoadUint32(&o.SYS_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_Type) GetSYS_CFG_FORCE_DOWNLOAD_BOOT() uint32 { + return (volatile.LoadUint32(&o.SYS_CFG.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_Type) SetSYS_CFG_HPSYS_SW_RESET(value uint32) { + volatile.StoreUint32(&o.SYS_CFG.Reg, volatile.LoadUint32(&o.SYS_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetSYS_CFG_HPSYS_SW_RESET() uint32 { + return (volatile.LoadUint32(&o.SYS_CFG.Reg) & 0x80000000) >> 31 +} + +// LP_AON.CPUCORE0_CFG: need_des +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_SW_STALL(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0xff)|value) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_SW_STALL() uint32 { + return volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0xff +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_SW_RESET(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_SW_RESET() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_DRESET_MASK(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_DRESET_MASK() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x80000000) >> 31 +} + +// LP_AON.IO_MUX: need_des +func (o *LP_AON_Type) SetIO_MUX_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX.Reg, volatile.LoadUint32(&o.IO_MUX.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetIO_MUX_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.IO_MUX.Reg) & 0x80000000) >> 31 +} + +// LP_AON.EXT_WAKEUP_CNTL: need_des +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0xff)|value) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0xff +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x4000)|value<<14) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x4000) >> 14 +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x7f8000)|value<<15) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x7f8000) >> 15 +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x7f800000)|value<<23) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x7f800000) >> 23 +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_AON.USB: need_des +func (o *LP_AON_Type) SetUSB_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.USB.Reg, volatile.LoadUint32(&o.USB.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetUSB_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.USB.Reg) & 0x80000000) >> 31 +} + +// LP_AON.LPBUS: need_des +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_WPULSE(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x70000)|value<<16) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_WPULSE() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x70000) >> 16 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_WA(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x380000)|value<<19) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_WA() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x380000) >> 19 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_RA(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0xc00000)|value<<22) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_RA() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0xc00000) >> 22 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_SEL_STATUS(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_SEL_STATUS() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_SEL_UPDATE(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_SEL_UPDATE() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x80000000) >> 31 +} + +// LP_AON.SDIO_ACTIVE: need_des +func (o *LP_AON_Type) SetSDIO_ACTIVE_SDIO_ACT_DNUM(value uint32) { + volatile.StoreUint32(&o.SDIO_ACTIVE.Reg, volatile.LoadUint32(&o.SDIO_ACTIVE.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_AON_Type) GetSDIO_ACTIVE_SDIO_ACT_DNUM() uint32 { + return (volatile.LoadUint32(&o.SDIO_ACTIVE.Reg) & 0xffc00000) >> 22 +} + +// LP_AON.LPCORE: need_des +func (o *LP_AON_Type) SetLPCORE_ETM_WAKEUP_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.LPCORE.Reg, volatile.LoadUint32(&o.LPCORE.Reg)&^(0x1)|value) +} +func (o *LP_AON_Type) GetLPCORE_ETM_WAKEUP_FLAG_CLR() uint32 { + return volatile.LoadUint32(&o.LPCORE.Reg) & 0x1 +} +func (o *LP_AON_Type) SetLPCORE_ETM_WAKEUP_FLAG(value uint32) { + volatile.StoreUint32(&o.LPCORE.Reg, volatile.LoadUint32(&o.LPCORE.Reg)&^(0x2)|value<<1) +} +func (o *LP_AON_Type) GetLPCORE_ETM_WAKEUP_FLAG() uint32 { + return (volatile.LoadUint32(&o.LPCORE.Reg) & 0x2) >> 1 +} +func (o *LP_AON_Type) SetLPCORE_DISABLE(value uint32) { + volatile.StoreUint32(&o.LPCORE.Reg, volatile.LoadUint32(&o.LPCORE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetLPCORE_DISABLE() uint32 { + return (volatile.LoadUint32(&o.LPCORE.Reg) & 0x80000000) >> 31 +} + +// LP_AON.SAR_CCT: need_des +func (o *LP_AON_Type) SetSAR_CCT_SAR2_PWDET_CCT(value uint32) { + volatile.StoreUint32(&o.SAR_CCT.Reg, volatile.LoadUint32(&o.SAR_CCT.Reg)&^(0xe0000000)|value<<29) +} +func (o *LP_AON_Type) GetSAR_CCT_SAR2_PWDET_CCT() uint32 { + return (volatile.LoadUint32(&o.SAR_CCT.Reg) & 0xe0000000) >> 29 +} + +// LP_AON.DATE: need_des +func (o *LP_AON_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_AON_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_AON_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power Access Permission Management Controller +type LP_APM_Type struct { + REGION_FILTER_EN volatile.Register32 // 0x0 + REGION0_ADDR_START volatile.Register32 // 0x4 + REGION0_ADDR_END volatile.Register32 // 0x8 + REGION0_PMS_ATTR volatile.Register32 // 0xC + REGION1_ADDR_START volatile.Register32 // 0x10 + REGION1_ADDR_END volatile.Register32 // 0x14 + REGION1_PMS_ATTR volatile.Register32 // 0x18 + REGION2_ADDR_START volatile.Register32 // 0x1C + REGION2_ADDR_END volatile.Register32 // 0x20 + REGION2_PMS_ATTR volatile.Register32 // 0x24 + REGION3_ADDR_START volatile.Register32 // 0x28 + REGION3_ADDR_END volatile.Register32 // 0x2C + REGION3_PMS_ATTR volatile.Register32 // 0x30 + _ [144]byte + FUNC_CTRL volatile.Register32 // 0xC4 + M0_STATUS volatile.Register32 // 0xC8 + M0_STATUS_CLR volatile.Register32 // 0xCC + M0_EXCEPTION_INFO0 volatile.Register32 // 0xD0 + M0_EXCEPTION_INFO1 volatile.Register32 // 0xD4 + M1_STATUS volatile.Register32 // 0xD8 + M1_STATUS_CLR volatile.Register32 // 0xDC + M1_EXCEPTION_INFO0 volatile.Register32 // 0xE0 + M1_EXCEPTION_INFO1 volatile.Register32 // 0xE4 + INT_EN volatile.Register32 // 0xE8 + CLOCK_GATE volatile.Register32 // 0xEC + _ [12]byte + DATE volatile.Register32 // 0xFC +} + +// LP_APM.REGION_FILTER_EN: Region filter enable register +func (o *LP_APM_Type) SetREGION_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.REGION_FILTER_EN.Reg, volatile.LoadUint32(&o.REGION_FILTER_EN.Reg)&^(0xf)|value) +} +func (o *LP_APM_Type) GetREGION_FILTER_EN() uint32 { + return volatile.LoadUint32(&o.REGION_FILTER_EN.Reg) & 0xf +} + +// LP_APM.REGION0_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION0_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION0_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_START.Reg) +} + +// LP_APM.REGION0_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION0_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION0_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_END.Reg) +} + +// LP_APM.REGION0_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.REGION1_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION1_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION1_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_START.Reg) +} + +// LP_APM.REGION1_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION1_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION1_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_END.Reg) +} + +// LP_APM.REGION1_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.REGION2_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION2_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION2_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_START.Reg) +} + +// LP_APM.REGION2_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION2_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION2_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_END.Reg) +} + +// LP_APM.REGION2_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.REGION3_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION3_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION3_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_START.Reg) +} + +// LP_APM.REGION3_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION3_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION3_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_END.Reg) +} + +// LP_APM.REGION3_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.FUNC_CTRL: PMS function control register +func (o *LP_APM_Type) SetFUNC_CTRL_M0_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetFUNC_CTRL_M0_PMS_FUNC_EN() uint32 { + return volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x1 +} +func (o *LP_APM_Type) SetFUNC_CTRL_M1_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetFUNC_CTRL_M1_PMS_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x2) >> 1 +} + +// LP_APM.M0_STATUS: M0 status register +func (o *LP_APM_Type) SetM0_STATUS_M0_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M0_STATUS.Reg, volatile.LoadUint32(&o.M0_STATUS.Reg)&^(0x3)|value) +} +func (o *LP_APM_Type) GetM0_STATUS_M0_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M0_STATUS.Reg) & 0x3 +} + +// LP_APM.M0_STATUS_CLR: M0 status clear register +func (o *LP_APM_Type) SetM0_STATUS_CLR_M0_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M0_STATUS_CLR.Reg, volatile.LoadUint32(&o.M0_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetM0_STATUS_CLR_M0_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M0_STATUS_CLR.Reg) & 0x1 +} + +// LP_APM.M0_EXCEPTION_INFO0: M0 exception_info0 register +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0xf)|value) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0xf +} +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// LP_APM.M0_EXCEPTION_INFO1: M0 exception_info1 register +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO1.Reg, value) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO1.Reg) +} + +// LP_APM.M1_STATUS: M1 status register +func (o *LP_APM_Type) SetM1_STATUS_M1_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M1_STATUS.Reg, volatile.LoadUint32(&o.M1_STATUS.Reg)&^(0x3)|value) +} +func (o *LP_APM_Type) GetM1_STATUS_M1_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M1_STATUS.Reg) & 0x3 +} + +// LP_APM.M1_STATUS_CLR: M1 status clear register +func (o *LP_APM_Type) SetM1_STATUS_CLR_M1_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M1_STATUS_CLR.Reg, volatile.LoadUint32(&o.M1_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetM1_STATUS_CLR_M1_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M1_STATUS_CLR.Reg) & 0x1 +} + +// LP_APM.M1_EXCEPTION_INFO0: M1 exception_info0 register +func (o *LP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0xf)|value) +} +func (o *LP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0xf +} +func (o *LP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *LP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *LP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// LP_APM.M1_EXCEPTION_INFO1: M1 exception_info1 register +func (o *LP_APM_Type) SetM1_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO1.Reg, value) +} +func (o *LP_APM_Type) GetM1_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M1_EXCEPTION_INFO1.Reg) +} + +// LP_APM.INT_EN: APM interrupt enable register +func (o *LP_APM_Type) SetINT_EN_M0_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetINT_EN_M0_APM_INT_EN() uint32 { + return volatile.LoadUint32(&o.INT_EN.Reg) & 0x1 +} +func (o *LP_APM_Type) SetINT_EN_M1_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetINT_EN_M1_APM_INT_EN() uint32 { + return (volatile.LoadUint32(&o.INT_EN.Reg) & 0x2) >> 1 +} + +// LP_APM.CLOCK_GATE: clock gating register +func (o *LP_APM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// LP_APM.DATE: Version register +func (o *LP_APM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_APM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LP_CLKRST Peripheral +type LP_CLKRST_Type struct { + LP_CLK_CONF volatile.Register32 // 0x0 + LP_CLK_PO_EN volatile.Register32 // 0x4 + LP_CLK_EN volatile.Register32 // 0x8 + LP_RST_EN volatile.Register32 // 0xC + RESET_CAUSE volatile.Register32 // 0x10 + CPU_RESET volatile.Register32 // 0x14 + FOSC_CNTL volatile.Register32 // 0x18 + RC32K_CNTL volatile.Register32 // 0x1C + CLK_TO_HP volatile.Register32 // 0x20 + LPMEM_FORCE volatile.Register32 // 0x24 + LPPERI volatile.Register32 // 0x28 + XTAL32K volatile.Register32 // 0x2C + _ [972]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_CLKRST.LP_CLK_CONF: need_des +func (o *LP_CLKRST_Type) SetLP_CLK_CONF_SLOW_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_CLK_CONF.Reg)&^(0x3)|value) +} +func (o *LP_CLKRST_Type) GetLP_CLK_CONF_SLOW_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.LP_CLK_CONF.Reg) & 0x3 +} +func (o *LP_CLKRST_Type) SetLP_CLK_CONF_FAST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *LP_CLKRST_Type) GetLP_CLK_CONF_FAST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *LP_CLKRST_Type) SetLP_CLK_CONF_LP_PERI_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_CLK_CONF.Reg)&^(0x7f8)|value<<3) +} +func (o *LP_CLKRST_Type) GetLP_CLK_CONF_LP_PERI_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_CONF.Reg) & 0x7f8) >> 3 +} + +// LP_CLKRST.LP_CLK_PO_EN: need_des +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_AON_SLOW_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x1)|value) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_AON_SLOW_OEN() uint32 { + return volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x1 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_AON_FAST_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x2)|value<<1) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_AON_FAST_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x2) >> 1 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_SOSC_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x4)|value<<2) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_SOSC_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x4) >> 2 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_FOSC_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x8)|value<<3) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_FOSC_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x8) >> 3 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_OSC32K_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x10)|value<<4) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_OSC32K_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x10) >> 4 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_XTAL32K_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x20)|value<<5) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_XTAL32K_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x20) >> 5 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_CORE_EFUSE_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x40)|value<<6) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_CORE_EFUSE_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x40) >> 6 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_SLOW_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x80)|value<<7) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_SLOW_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x80) >> 7 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_FAST_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x100)|value<<8) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_FAST_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x100) >> 8 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_RNG_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x200)|value<<9) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_RNG_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x200) >> 9 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_LPBUS_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x400)|value<<10) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_LPBUS_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x400) >> 10 +} + +// LP_CLKRST.LP_CLK_EN: need_des +func (o *LP_CLKRST_Type) SetLP_CLK_EN_FAST_ORI_GATE(value uint32) { + volatile.StoreUint32(&o.LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_CLK_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLP_CLK_EN_FAST_ORI_GATE() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_EN.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.LP_RST_EN: need_des +func (o *LP_CLKRST_Type) SetLP_RST_EN_AON_EFUSE_CORE_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_AON_EFUSE_CORE_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetLP_RST_EN_LP_TIMER_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_LP_TIMER_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetLP_RST_EN_WDT_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_WDT_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetLP_RST_EN_ANA_PERI_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_ANA_PERI_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.RESET_CAUSE: need_des +func (o *LP_CLKRST_Type) SetRESET_CAUSE(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x1f)|value) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE() uint32 { + return volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x1f +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x20)|value<<5) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_FLAG() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x20) >> 5 +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_FLAG_SET(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_FLAG_SET() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.CPU_RESET: need_des +func (o *LP_CLKRST_Type) SetCPU_RESET_RTC_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_RTC_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x1c00000) >> 22 +} +func (o *LP_CLKRST_Type) SetCPU_RESET_RTC_WDT_CPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_RTC_WDT_CPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x2000000) >> 25 +} +func (o *LP_CLKRST_Type) SetCPU_RESET_CPU_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x7c000000)|value<<26) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_CPU_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x7c000000) >> 26 +} +func (o *LP_CLKRST_Type) SetCPU_RESET_CPU_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_CPU_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.FOSC_CNTL: need_des +func (o *LP_CLKRST_Type) SetFOSC_CNTL_FOSC_DFREQ(value uint32) { + volatile.StoreUint32(&o.FOSC_CNTL.Reg, volatile.LoadUint32(&o.FOSC_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetFOSC_CNTL_FOSC_DFREQ() uint32 { + return (volatile.LoadUint32(&o.FOSC_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_CLKRST.RC32K_CNTL: need_des +func (o *LP_CLKRST_Type) SetRC32K_CNTL_RC32K_DFREQ(value uint32) { + volatile.StoreUint32(&o.RC32K_CNTL.Reg, volatile.LoadUint32(&o.RC32K_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetRC32K_CNTL_RC32K_DFREQ() uint32 { + return (volatile.LoadUint32(&o.RC32K_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_CLKRST.CLK_TO_HP: need_des +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_XTAL32K(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_SOSC(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_SOSC() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_OSC32K(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_OSC32K() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_FOSC(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_FOSC() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.LPMEM_FORCE: need_des +func (o *LP_CLKRST_Type) SetLPMEM_FORCE_LPMEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LPMEM_FORCE.Reg, volatile.LoadUint32(&o.LPMEM_FORCE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLPMEM_FORCE_LPMEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LPMEM_FORCE.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.LPPERI: need_des +func (o *LP_CLKRST_Type) SetLPPERI_LP_I2C_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_I2C_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetLPPERI_LP_UART_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_UART_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.XTAL32K: need_des +func (o *LP_CLKRST_Type) SetXTAL32K_DRES_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DRES_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0x1c00000) >> 22 +} +func (o *LP_CLKRST_Type) SetXTAL32K_DGM_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0xe000000)|value<<25) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DGM_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0xe000000) >> 25 +} +func (o *LP_CLKRST_Type) SetXTAL32K_DBUF_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DBUF_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetXTAL32K_DAC_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0xe0000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DAC_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0xe0000000) >> 29 +} + +// LP_CLKRST.DATE: need_des +func (o *LP_CLKRST_Type) SetDATE_CLKRST_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_CLKRST_Type) GetDATE_CLKRST_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_CLKRST_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_I2C_ANA_MST Peripheral +type LP_I2C_ANA_MST_Type struct { + I2C0_CTRL volatile.Register32 // 0x0 + I2C0_CONF volatile.Register32 // 0x4 + I2C0_DATA volatile.Register32 // 0x8 + ANA_CONF1 volatile.Register32 // 0xC + NOUSE volatile.Register32 // 0x10 + DEVICE_EN volatile.Register32 // 0x14 + _ [996]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_I2C_ANA_MST.I2C0_CTRL: need_des +func (o *LP_I2C_ANA_MST_Type) SetI2C0_CTRL_LP_I2C_ANA_MAST_I2C0_CTRL(value uint32) { + volatile.StoreUint32(&o.I2C0_CTRL.Reg, volatile.LoadUint32(&o.I2C0_CTRL.Reg)&^(0x1ffffff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_CTRL_LP_I2C_ANA_MAST_I2C0_CTRL() uint32 { + return volatile.LoadUint32(&o.I2C0_CTRL.Reg) & 0x1ffffff +} +func (o *LP_I2C_ANA_MST_Type) SetI2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY(value uint32) { + volatile.StoreUint32(&o.I2C0_CTRL.Reg, volatile.LoadUint32(&o.I2C0_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY() uint32 { + return (volatile.LoadUint32(&o.I2C0_CTRL.Reg) & 0x2000000) >> 25 +} + +// LP_I2C_ANA_MST.I2C0_CONF: need_des +func (o *LP_I2C_ANA_MST_Type) SetI2C0_CONF_LP_I2C_ANA_MAST_I2C0_CONF(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0xffffff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_CONF_LP_I2C_ANA_MAST_I2C0_CONF() uint32 { + return volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0xffffff +} +func (o *LP_I2C_ANA_MST_Type) SetI2C0_CONF_LP_I2C_ANA_MAST_I2C0_STATUS(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_CONF_LP_I2C_ANA_MAST_I2C0_STATUS() uint32 { + return (volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0xff000000) >> 24 +} + +// LP_I2C_ANA_MST.I2C0_DATA: need_des +func (o *LP_I2C_ANA_MST_Type) SetI2C0_DATA_LP_I2C_ANA_MAST_I2C0_RDATA(value uint32) { + volatile.StoreUint32(&o.I2C0_DATA.Reg, volatile.LoadUint32(&o.I2C0_DATA.Reg)&^(0xff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_DATA_LP_I2C_ANA_MAST_I2C0_RDATA() uint32 { + return volatile.LoadUint32(&o.I2C0_DATA.Reg) & 0xff +} +func (o *LP_I2C_ANA_MST_Type) SetI2C0_DATA_LP_I2C_ANA_MAST_I2C0_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.I2C0_DATA.Reg, volatile.LoadUint32(&o.I2C0_DATA.Reg)&^(0x700)|value<<8) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_DATA_LP_I2C_ANA_MAST_I2C0_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.I2C0_DATA.Reg) & 0x700) >> 8 +} +func (o *LP_I2C_ANA_MST_Type) SetI2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL(value uint32) { + volatile.StoreUint32(&o.I2C0_DATA.Reg, volatile.LoadUint32(&o.I2C0_DATA.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C_ANA_MST_Type) GetI2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL() uint32 { + return (volatile.LoadUint32(&o.I2C0_DATA.Reg) & 0x800) >> 11 +} + +// LP_I2C_ANA_MST.ANA_CONF1: need_des +func (o *LP_I2C_ANA_MST_Type) SetANA_CONF1_LP_I2C_ANA_MAST_ANA_CONF1(value uint32) { + volatile.StoreUint32(&o.ANA_CONF1.Reg, volatile.LoadUint32(&o.ANA_CONF1.Reg)&^(0xffffff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetANA_CONF1_LP_I2C_ANA_MAST_ANA_CONF1() uint32 { + return volatile.LoadUint32(&o.ANA_CONF1.Reg) & 0xffffff +} + +// LP_I2C_ANA_MST.NOUSE: need_des +func (o *LP_I2C_ANA_MST_Type) SetNOUSE(value uint32) { + volatile.StoreUint32(&o.NOUSE.Reg, value) +} +func (o *LP_I2C_ANA_MST_Type) GetNOUSE() uint32 { + return volatile.LoadUint32(&o.NOUSE.Reg) +} + +// LP_I2C_ANA_MST.DEVICE_EN: need_des +func (o *LP_I2C_ANA_MST_Type) SetDEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_EN.Reg, volatile.LoadUint32(&o.DEVICE_EN.Reg)&^(0xfff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetDEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN() uint32 { + return volatile.LoadUint32(&o.DEVICE_EN.Reg) & 0xfff +} + +// LP_I2C_ANA_MST.DATE: need_des +func (o *LP_I2C_ANA_MST_Type) SetDATE_LP_I2C_ANA_MAST_I2C_MAT_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_I2C_ANA_MST_Type) GetDATE_LP_I2C_ANA_MAST_I2C_MAT_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} +func (o *LP_I2C_ANA_MST_Type) SetDATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_I2C_ANA_MST_Type) GetDATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x10000000) >> 28 +} + +// Low-power Input/Output Multiplexer +type LP_IO_Type struct { + OUT_DATA volatile.Register32 // 0x0 + OUT_DATA_W1TS volatile.Register32 // 0x4 + OUT_DATA_W1TC volatile.Register32 // 0x8 + OUT_ENABLE volatile.Register32 // 0xC + OUT_ENABLE_W1TS volatile.Register32 // 0x10 + OUT_ENABLE_W1TC volatile.Register32 // 0x14 + STATUS volatile.Register32 // 0x18 + STATUS_W1TS volatile.Register32 // 0x1C + STATUS_W1TC volatile.Register32 // 0x20 + IN volatile.Register32 // 0x24 + PIN0 volatile.Register32 // 0x28 + PIN1 volatile.Register32 // 0x2C + PIN2 volatile.Register32 // 0x30 + PIN3 volatile.Register32 // 0x34 + PIN4 volatile.Register32 // 0x38 + PIN5 volatile.Register32 // 0x3C + PIN6 volatile.Register32 // 0x40 + PIN7 volatile.Register32 // 0x44 + GPIO0 volatile.Register32 // 0x48 + GPIO1 volatile.Register32 // 0x4C + GPIO2 volatile.Register32 // 0x50 + GPIO3 volatile.Register32 // 0x54 + GPIO4 volatile.Register32 // 0x58 + GPIO5 volatile.Register32 // 0x5C + GPIO6 volatile.Register32 // 0x60 + GPIO7 volatile.Register32 // 0x64 + STATUS_INTERRUPT volatile.Register32 // 0x68 + DEBUG_SEL0 volatile.Register32 // 0x6C + DEBUG_SEL1 volatile.Register32 // 0x70 + LPI2C volatile.Register32 // 0x74 + _ [900]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_IO.OUT_DATA: need des +func (o *LP_IO_Type) SetOUT_DATA_LP_GPIO_OUT_DATA(value uint32) { + volatile.StoreUint32(&o.OUT_DATA.Reg, volatile.LoadUint32(&o.OUT_DATA.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_DATA_LP_GPIO_OUT_DATA() uint32 { + return volatile.LoadUint32(&o.OUT_DATA.Reg) & 0xff +} + +// LP_IO.OUT_DATA_W1TS: need des +func (o *LP_IO_Type) SetOUT_DATA_W1TS_LP_GPIO_OUT_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_DATA_W1TS.Reg, volatile.LoadUint32(&o.OUT_DATA_W1TS.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_DATA_W1TS_LP_GPIO_OUT_DATA_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_DATA_W1TS.Reg) & 0xff +} + +// LP_IO.OUT_DATA_W1TC: need des +func (o *LP_IO_Type) SetOUT_DATA_W1TC_LP_GPIO_OUT_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_DATA_W1TC.Reg, volatile.LoadUint32(&o.OUT_DATA_W1TC.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_DATA_W1TC_LP_GPIO_OUT_DATA_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_DATA_W1TC.Reg) & 0xff +} + +// LP_IO.OUT_ENABLE: need des +func (o *LP_IO_Type) SetOUT_ENABLE_LP_GPIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.OUT_ENABLE.Reg, volatile.LoadUint32(&o.OUT_ENABLE.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_ENABLE_LP_GPIO_ENABLE() uint32 { + return volatile.LoadUint32(&o.OUT_ENABLE.Reg) & 0xff +} + +// LP_IO.OUT_ENABLE_W1TS: need des +func (o *LP_IO_Type) SetOUT_ENABLE_W1TS_LP_GPIO_ENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_ENABLE_W1TS.Reg, volatile.LoadUint32(&o.OUT_ENABLE_W1TS.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_ENABLE_W1TS_LP_GPIO_ENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_ENABLE_W1TS.Reg) & 0xff +} + +// LP_IO.OUT_ENABLE_W1TC: need des +func (o *LP_IO_Type) SetOUT_ENABLE_W1TC_LP_GPIO_ENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_ENABLE_W1TC.Reg, volatile.LoadUint32(&o.OUT_ENABLE_W1TC.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetOUT_ENABLE_W1TC_LP_GPIO_ENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_ENABLE_W1TC.Reg) & 0xff +} + +// LP_IO.STATUS: need des +func (o *LP_IO_Type) SetSTATUS_LP_GPIO_STATUS_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetSTATUS_LP_GPIO_STATUS_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xff +} + +// LP_IO.STATUS_W1TS: need des +func (o *LP_IO_Type) SetSTATUS_W1TS_LP_GPIO_STATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, volatile.LoadUint32(&o.STATUS_W1TS.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetSTATUS_W1TS_LP_GPIO_STATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) & 0xff +} + +// LP_IO.STATUS_W1TC: need des +func (o *LP_IO_Type) SetSTATUS_W1TC_LP_GPIO_STATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, volatile.LoadUint32(&o.STATUS_W1TC.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetSTATUS_W1TC_LP_GPIO_STATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) & 0xff +} + +// LP_IO.IN: need des +func (o *LP_IO_Type) SetIN_LP_GPIO_IN_DATA_NEXT(value uint32) { + volatile.StoreUint32(&o.IN.Reg, volatile.LoadUint32(&o.IN.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetIN_LP_GPIO_IN_DATA_NEXT() uint32 { + return volatile.LoadUint32(&o.IN.Reg) & 0xff +} + +// LP_IO.PIN0: need des +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN0_LP_GPIO0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN0_LP_GPIO0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN1: need des +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN1_LP_GPIO1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN1_LP_GPIO1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN2: need des +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN2_LP_GPIO2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN2_LP_GPIO2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN3: need des +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN3_LP_GPIO3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN3_LP_GPIO3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN4: need des +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN4_LP_GPIO4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN4_LP_GPIO4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN5: need des +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN5_LP_GPIO5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN5_LP_GPIO5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN6: need des +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN6_LP_GPIO6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN6_LP_GPIO6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x800) >> 11 +} + +// LP_IO.PIN7: need des +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_SYNC_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_SYNC_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x3 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *LP_IO_Type) SetPIN7_LP_GPIO7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x800)|value<<11) +} +func (o *LP_IO_Type) GetPIN7_LP_GPIO7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x800) >> 11 +} + +// LP_IO.GPIO0: need des +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO0_LP_GPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO0_LP_GPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO1: need des +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO1_LP_GPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO1_LP_GPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO2: need des +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO2_LP_GPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO2_LP_GPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO3: need des +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO3_LP_GPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO3_LP_GPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO4: need des +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO4_LP_GPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO4_LP_GPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO5: need des +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO5_LP_GPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO5_LP_GPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO6: need des +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO6_LP_GPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO6_LP_GPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} + +// LP_IO.GPIO7: need des +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x60)|value<<5) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x60) >> 5 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *LP_IO_Type) SetGPIO7_LP_GPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *LP_IO_Type) GetGPIO7_LP_GPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} + +// LP_IO.STATUS_INTERRUPT: need des +func (o *LP_IO_Type) SetSTATUS_INTERRUPT_LP_GPIO_STATUS_INTERRUPT_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_INTERRUPT.Reg, volatile.LoadUint32(&o.STATUS_INTERRUPT.Reg)&^(0xff)|value) +} +func (o *LP_IO_Type) GetSTATUS_INTERRUPT_LP_GPIO_STATUS_INTERRUPT_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_INTERRUPT.Reg) & 0xff +} + +// LP_IO.DEBUG_SEL0: need des +func (o *LP_IO_Type) SetDEBUG_SEL0_LP_DEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0x7f)|value) +} +func (o *LP_IO_Type) GetDEBUG_SEL0_LP_DEBUG_SEL0() uint32 { + return volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0x7f +} +func (o *LP_IO_Type) SetDEBUG_SEL0_LP_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0x3f80)|value<<7) +} +func (o *LP_IO_Type) GetDEBUG_SEL0_LP_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0x3f80) >> 7 +} +func (o *LP_IO_Type) SetDEBUG_SEL0_LP_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0x1fc000)|value<<14) +} +func (o *LP_IO_Type) GetDEBUG_SEL0_LP_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0x1fc000) >> 14 +} +func (o *LP_IO_Type) SetDEBUG_SEL0_LP_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0xfe00000)|value<<21) +} +func (o *LP_IO_Type) GetDEBUG_SEL0_LP_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0xfe00000) >> 21 +} + +// LP_IO.DEBUG_SEL1: need des +func (o *LP_IO_Type) SetDEBUG_SEL1_LP_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL1.Reg, volatile.LoadUint32(&o.DEBUG_SEL1.Reg)&^(0x7f)|value) +} +func (o *LP_IO_Type) GetDEBUG_SEL1_LP_DEBUG_SEL4() uint32 { + return volatile.LoadUint32(&o.DEBUG_SEL1.Reg) & 0x7f +} + +// LP_IO.LPI2C: need des +func (o *LP_IO_Type) SetLPI2C_LP_I2C_SDA_IE(value uint32) { + volatile.StoreUint32(&o.LPI2C.Reg, volatile.LoadUint32(&o.LPI2C.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_IO_Type) GetLPI2C_LP_I2C_SDA_IE() uint32 { + return (volatile.LoadUint32(&o.LPI2C.Reg) & 0x40000000) >> 30 +} +func (o *LP_IO_Type) SetLPI2C_LP_I2C_SCL_IE(value uint32) { + volatile.StoreUint32(&o.LPI2C.Reg, volatile.LoadUint32(&o.LPI2C.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_IO_Type) GetLPI2C_LP_I2C_SCL_IE() uint32 { + return (volatile.LoadUint32(&o.LPI2C.Reg) & 0x80000000) >> 31 +} + +// LP_IO.DATE: need des +func (o *LP_IO_Type) SetDATE_LP_IO_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_IO_Type) GetDATE_LP_IO_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_IO_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_IO_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power Trusted Execution Environment +type LP_TEE_Type struct { + M0_MODE_CTRL volatile.Register32 // 0x0 + CLOCK_GATE volatile.Register32 // 0x4 + _ [136]byte + FORCE_ACC_HP volatile.Register32 // 0x90 + _ [104]byte + DATE volatile.Register32 // 0xFC +} + +// LP_TEE.M0_MODE_CTRL: Tee mode control register +func (o *LP_TEE_Type) SetM0_MODE_CTRL_M0_MODE(value uint32) { + volatile.StoreUint32(&o.M0_MODE_CTRL.Reg, volatile.LoadUint32(&o.M0_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *LP_TEE_Type) GetM0_MODE_CTRL_M0_MODE() uint32 { + return volatile.LoadUint32(&o.M0_MODE_CTRL.Reg) & 0x3 +} + +// LP_TEE.CLOCK_GATE: Clock gating register +func (o *LP_TEE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *LP_TEE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// LP_TEE.FORCE_ACC_HP: need_des +func (o *LP_TEE_Type) SetFORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN(value uint32) { + volatile.StoreUint32(&o.FORCE_ACC_HP.Reg, volatile.LoadUint32(&o.FORCE_ACC_HP.Reg)&^(0x1)|value) +} +func (o *LP_TEE_Type) GetFORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN() uint32 { + return volatile.LoadUint32(&o.FORCE_ACC_HP.Reg) & 0x1 +} + +// LP_TEE.DATE: Version register +func (o *LP_TEE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_TEE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power Timer +type LP_TIMER_Type struct { + TAR0_LOW volatile.Register32 // 0x0 + TAR0_HIGH volatile.Register32 // 0x4 + TAR1_LOW volatile.Register32 // 0x8 + TAR1_HIGH volatile.Register32 // 0xC + UPDATE volatile.Register32 // 0x10 + MAIN_BUF0_LOW volatile.Register32 // 0x14 + MAIN_BUF0_HIGH volatile.Register32 // 0x18 + MAIN_BUF1_LOW volatile.Register32 // 0x1C + MAIN_BUF1_HIGH volatile.Register32 // 0x20 + MAIN_OVERFLOW volatile.Register32 // 0x24 + INT_RAW volatile.Register32 // 0x28 + INT_ST volatile.Register32 // 0x2C + INT_ENA volatile.Register32 // 0x30 + INT_CLR volatile.Register32 // 0x34 + LP_INT_RAW volatile.Register32 // 0x38 + LP_INT_ST volatile.Register32 // 0x3C + LP_INT_ENA volatile.Register32 // 0x40 + LP_INT_CLR volatile.Register32 // 0x44 + _ [948]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_TIMER.TAR0_LOW: need_des +func (o *LP_TIMER_Type) SetTAR0_LOW(value uint32) { + volatile.StoreUint32(&o.TAR0_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetTAR0_LOW() uint32 { + return volatile.LoadUint32(&o.TAR0_LOW.Reg) +} + +// LP_TIMER.TAR0_HIGH: need_des +func (o *LP_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0(value uint32) { + volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0() uint32 { + return volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0xffff +} +func (o *LP_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_EN0(value uint32) { + volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_EN0() uint32 { + return (volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.TAR1_LOW: need_des +func (o *LP_TIMER_Type) SetTAR1_LOW(value uint32) { + volatile.StoreUint32(&o.TAR1_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetTAR1_LOW() uint32 { + return volatile.LoadUint32(&o.TAR1_LOW.Reg) +} + +// LP_TIMER.TAR1_HIGH: need_des +func (o *LP_TIMER_Type) SetTAR1_HIGH_MAIN_TIMER_TAR_HIGH1(value uint32) { + volatile.StoreUint32(&o.TAR1_HIGH.Reg, volatile.LoadUint32(&o.TAR1_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetTAR1_HIGH_MAIN_TIMER_TAR_HIGH1() uint32 { + return volatile.LoadUint32(&o.TAR1_HIGH.Reg) & 0xffff +} +func (o *LP_TIMER_Type) SetTAR1_HIGH_MAIN_TIMER_TAR_EN1(value uint32) { + volatile.StoreUint32(&o.TAR1_HIGH.Reg, volatile.LoadUint32(&o.TAR1_HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetTAR1_HIGH_MAIN_TIMER_TAR_EN1() uint32 { + return (volatile.LoadUint32(&o.TAR1_HIGH.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.UPDATE: need_des +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_UPDATE(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x10000000) >> 28 +} +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_XTAL_OFF(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_XTAL_OFF() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x20000000) >> 29 +} +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_STALL(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_STALL() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_RST(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.MAIN_BUF0_LOW: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF0_LOW(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF0_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF0_LOW() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF0_LOW.Reg) +} + +// LP_TIMER.MAIN_BUF0_HIGH: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF0_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg) & 0xffff +} + +// LP_TIMER.MAIN_BUF1_LOW: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF1_LOW(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF1_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF1_LOW() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF1_LOW.Reg) +} + +// LP_TIMER.MAIN_BUF1_HIGH: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF1_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg) & 0xffff +} + +// LP_TIMER.MAIN_OVERFLOW: need_des +func (o *LP_TIMER_Type) SetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD(value uint32) { + volatile.StoreUint32(&o.MAIN_OVERFLOW.Reg, volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD() uint32 { + return (volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_RAW: need_des +func (o *LP_TIMER_Type) SetINT_RAW_OVERFLOW_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_RAW_OVERFLOW_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_RAW_SOC_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_RAW_SOC_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_ST: need_des +func (o *LP_TIMER_Type) SetINT_ST_OVERFLOW_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_ST_OVERFLOW_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_ST_SOC_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_ST_SOC_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_ENA: need_des +func (o *LP_TIMER_Type) SetINT_ENA_OVERFLOW_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_ENA_OVERFLOW_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_ENA_SOC_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_ENA_SOC_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_CLR: need_des +func (o *LP_TIMER_Type) SetINT_CLR_OVERFLOW_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_CLR_OVERFLOW_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_CLR_SOC_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_CLR_SOC_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.LP_INT_RAW: need_des +func (o *LP_TIMER_Type) SetLP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetLP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetLP_INT_RAW_MAIN_TIMER_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetLP_INT_RAW_MAIN_TIMER_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.LP_INT_ST: need_des +func (o *LP_TIMER_Type) SetLP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetLP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetLP_INT_ST_MAIN_TIMER_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetLP_INT_ST_MAIN_TIMER_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.LP_INT_ENA: need_des +func (o *LP_TIMER_Type) SetLP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetLP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetLP_INT_ENA_MAIN_TIMER_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetLP_INT_ENA_MAIN_TIMER_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.LP_INT_CLR: need_des +func (o *LP_TIMER_Type) SetLP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetLP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetLP_INT_CLR_MAIN_TIMER_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetLP_INT_CLR_MAIN_TIMER_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.DATE: need_des +func (o *LP_TIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_TIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_TIMER_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller +type LP_UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV_SYNC volatile.Register32 // 0x14 + RX_FILT volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0_SYNC volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + _ [4]byte + HWFC_CONF_SYNC volatile.Register32 // 0x2C + SLEEP_CONF0 volatile.Register32 // 0x30 + SLEEP_CONF1 volatile.Register32 // 0x34 + SLEEP_CONF2 volatile.Register32 // 0x38 + SWFC_CONF0_SYNC volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + TXBRK_CONF_SYNC volatile.Register32 // 0x44 + IDLE_CONF_SYNC volatile.Register32 // 0x48 + RS485_CONF_SYNC volatile.Register32 // 0x4C + AT_CMD_PRECNT_SYNC volatile.Register32 // 0x50 + AT_CMD_POSTCNT_SYNC volatile.Register32 // 0x54 + AT_CMD_GAPTOUT_SYNC volatile.Register32 // 0x58 + AT_CMD_CHAR_SYNC volatile.Register32 // 0x5C + MEM_CONF volatile.Register32 // 0x60 + TOUT_CONF_SYNC volatile.Register32 // 0x64 + MEM_TX_STATUS volatile.Register32 // 0x68 + MEM_RX_STATUS volatile.Register32 // 0x6C + FSM_STATUS volatile.Register32 // 0x70 + _ [20]byte + CLK_CONF volatile.Register32 // 0x88 + DATE volatile.Register32 // 0x8C + AFIFO_STATUS volatile.Register32 // 0x90 + _ [4]byte + REG_UPDATE volatile.Register32 // 0x98 + ID volatile.Register32 // 0x9C +} + +// LP_UART.FIFO: FIFO data register +func (o *LP_UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// LP_UART.INT_RAW: Raw interrupt status +func (o *LP_UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// LP_UART.INT_ST: Masked interrupt status +func (o *LP_UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// LP_UART.INT_ENA: Interrupt enable bits +func (o *LP_UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// LP_UART.INT_CLR: Interrupt clear bits +func (o *LP_UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// LP_UART.CLKDIV_SYNC: Clock divider configuration +func (o *LP_UART_Type) SetCLKDIV_SYNC_CLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xfff)|value) +} +func (o *LP_UART_Type) GetCLKDIV_SYNC_CLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xfff +} +func (o *LP_UART_Type) SetCLKDIV_SYNC_CLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xf00000)|value<<20) +} +func (o *LP_UART_Type) GetCLKDIV_SYNC_CLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xf00000) >> 20 +} + +// LP_UART.RX_FILT: Rx Filter configuration +func (o *LP_UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetRX_FILT_GLITCH_FILT() uint32 { + return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff +} +func (o *LP_UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8 +} + +// LP_UART.STATUS: UART status register +func (o *LP_UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *LP_UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *LP_UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf80000)|value<<19) +} +func (o *LP_UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf80000) >> 19 +} +func (o *LP_UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *LP_UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *LP_UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// LP_UART.CONF0_SYNC: Configuration register 0 +func (o *LP_UART_Type) SetCONF0_SYNC_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetCONF0_SYNC_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1 +} +func (o *LP_UART_Type) SetCONF0_SYNC_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetCONF0_SYNC_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetCONF0_SYNC_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *LP_UART_Type) GetCONF0_SYNC_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0xc) >> 2 +} +func (o *LP_UART_Type) SetCONF0_SYNC_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x30)|value<<4) +} +func (o *LP_UART_Type) GetCONF0_SYNC_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x30) >> 4 +} +func (o *LP_UART_Type) SetCONF0_SYNC_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetCONF0_SYNC_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetCONF0_SYNC_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetCONF0_SYNC_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetCONF0_SYNC_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetCONF0_SYNC_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetCONF0_SYNC_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x8000)|value<<15) +} +func (o *LP_UART_Type) GetCONF0_SYNC_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x8000) >> 15 +} +func (o *LP_UART_Type) SetCONF0_SYNC_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x10000)|value<<16) +} +func (o *LP_UART_Type) GetCONF0_SYNC_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x10000) >> 16 +} +func (o *LP_UART_Type) SetCONF0_SYNC_DIS_RX_DAT_OVF(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x20000)|value<<17) +} +func (o *LP_UART_Type) GetCONF0_SYNC_DIS_RX_DAT_OVF() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x20000) >> 17 +} +func (o *LP_UART_Type) SetCONF0_SYNC_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetCONF0_SYNC_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetCONF0_SYNC_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *LP_UART_Type) GetCONF0_SYNC_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x100000) >> 20 +} +func (o *LP_UART_Type) SetCONF0_SYNC_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x200000)|value<<21) +} +func (o *LP_UART_Type) GetCONF0_SYNC_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x200000) >> 21 +} +func (o *LP_UART_Type) SetCONF0_SYNC_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x400000)|value<<22) +} +func (o *LP_UART_Type) GetCONF0_SYNC_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x400000) >> 22 +} +func (o *LP_UART_Type) SetCONF0_SYNC_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x800000)|value<<23) +} +func (o *LP_UART_Type) GetCONF0_SYNC_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x800000) >> 23 +} + +// LP_UART.CONF1: Configuration register 1 +func (o *LP_UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xf800)|value<<11) +} +func (o *LP_UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xf800) >> 11 +} +func (o *LP_UART_Type) SetCONF1_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *LP_UART_Type) GetCONF1_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10000) >> 16 +} +func (o *LP_UART_Type) SetCONF1_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *LP_UART_Type) GetCONF1_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000) >> 17 +} +func (o *LP_UART_Type) SetCONF1_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetCONF1_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetCONF1_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetCONF1_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19 +} +func (o *LP_UART_Type) SetCONF1_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *LP_UART_Type) GetCONF1_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *LP_UART_Type) SetCONF1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *LP_UART_Type) GetCONF1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} + +// LP_UART.HWFC_CONF_SYNC: Hardware flow-control configuration +func (o *LP_UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0x100) >> 8 +} + +// LP_UART.SLEEP_CONF0: UART sleep configure register 0 +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR1(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR1() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff +} +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR2(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR2() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff00) >> 8 +} +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR3(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR3() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff0000) >> 16 +} +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR4(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff000000)|value<<24) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR4() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff000000) >> 24 +} + +// LP_UART.SLEEP_CONF1: UART sleep configure register 1 +func (o *LP_UART_Type) SetSLEEP_CONF1_WK_CHAR0(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF1.Reg, volatile.LoadUint32(&o.SLEEP_CONF1.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetSLEEP_CONF1_WK_CHAR0() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF1.Reg) & 0xff +} + +// LP_UART.SLEEP_CONF2: UART sleep configure register 2 +func (o *LP_UART_Type) SetSLEEP_CONF2_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3ff)|value) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3ff +} +func (o *LP_UART_Type) SetSLEEP_CONF2_RX_WAKE_UP_THRHD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e000)|value<<13) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_RX_WAKE_UP_THRHD() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e000) >> 13 +} +func (o *LP_UART_Type) SetSLEEP_CONF2_WK_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x1c0000)|value<<18) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_WK_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x1c0000) >> 18 +} +func (o *LP_UART_Type) SetSLEEP_CONF2_WK_CHAR_MASK(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e00000)|value<<21) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_WK_CHAR_MASK() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e00000) >> 21 +} +func (o *LP_UART_Type) SetSLEEP_CONF2_WK_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0xc000000)|value<<26) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_WK_MODE_SEL() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0xc000000) >> 26 +} + +// LP_UART.SWFC_CONF0_SYNC: Software flow-control character configuration +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XON_CHAR() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff00)|value<<8) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff00) >> 8 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x10000)|value<<16) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x10000) >> 16 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x20000)|value<<17) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_SW_FLOW_CON_EN() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x20000) >> 17 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x80000) >> 19 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x100000) >> 20 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_SEND_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x200000)|value<<21) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x200000) >> 21 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x400000)|value<<22) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x400000) >> 22 +} + +// LP_UART.SWFC_CONF1: Software flow-control character configuration +func (o *LP_UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetSWFC_CONF1_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xf800)|value<<11) +} +func (o *LP_UART_Type) GetSWFC_CONF1_XOFF_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xf800) >> 11 +} + +// LP_UART.TXBRK_CONF_SYNC: Tx Break character configuration +func (o *LP_UART_Type) SetTXBRK_CONF_SYNC_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.TXBRK_CONF_SYNC.Reg, volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetTXBRK_CONF_SYNC_TX_BRK_NUM() uint32 { + return volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg) & 0xff +} + +// LP_UART.IDLE_CONF_SYNC: Frame-end idle configuration +func (o *LP_UART_Type) SetIDLE_CONF_SYNC_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0x3ff)|value) +} +func (o *LP_UART_Type) GetIDLE_CONF_SYNC_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0x3ff +} +func (o *LP_UART_Type) SetIDLE_CONF_SYNC_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0xffc00)|value<<10) +} +func (o *LP_UART_Type) GetIDLE_CONF_SYNC_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0xffc00) >> 10 +} + +// LP_UART.RS485_CONF_SYNC: RS485 mode configuration +func (o *LP_UART_Type) SetRS485_CONF_SYNC_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetRS485_CONF_SYNC_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetRS485_CONF_SYNC_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetRS485_CONF_SYNC_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x4) >> 2 +} + +// LP_UART.AT_CMD_PRECNT_SYNC: Pre-sequence timing configuration +func (o *LP_UART_Type) SetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg)&^(0xffff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg) & 0xffff +} + +// LP_UART.AT_CMD_POSTCNT_SYNC: Post-sequence timing configuration +func (o *LP_UART_Type) SetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg)&^(0xffff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg) & 0xffff +} + +// LP_UART.AT_CMD_GAPTOUT_SYNC: Timeout configuration +func (o *LP_UART_Type) SetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg)&^(0xffff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg) & 0xffff +} + +// LP_UART.AT_CMD_CHAR_SYNC: AT escape sequence detection configuration +func (o *LP_UART_Type) SetAT_CMD_CHAR_SYNC_AT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_CHAR_SYNC_AT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff +} +func (o *LP_UART_Type) SetAT_CMD_CHAR_SYNC_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff00)|value<<8) +} +func (o *LP_UART_Type) GetAT_CMD_CHAR_SYNC_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff00) >> 8 +} + +// LP_UART.MEM_CONF: UART memory power configuration +func (o *LP_UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LP_UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26 +} + +// LP_UART.TOUT_CONF_SYNC: UART threshold and allocation configuration +func (o *LP_UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_EN() uint32 { + return volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x1 +} +func (o *LP_UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0xffc)|value<<2) +} +func (o *LP_UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0xffc) >> 2 +} + +// LP_UART.MEM_TX_STATUS: Tx-SRAM write and read offset address. +func (o *LP_UART_Type) SetMEM_TX_STATUS_TX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetMEM_TX_STATUS_TX_SRAM_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetMEM_TX_STATUS_TX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1f000)|value<<12) +} +func (o *LP_UART_Type) GetMEM_TX_STATUS_TX_SRAM_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1f000) >> 12 +} + +// LP_UART.MEM_RX_STATUS: Rx-SRAM write and read offset address. +func (o *LP_UART_Type) SetMEM_RX_STATUS_RX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetMEM_RX_STATUS_RX_SRAM_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetMEM_RX_STATUS_RX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1f000)|value<<12) +} +func (o *LP_UART_Type) GetMEM_RX_STATUS_RX_SRAM_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1f000) >> 12 +} + +// LP_UART.FSM_STATUS: UART transmit and receive status. +func (o *LP_UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *LP_UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *LP_UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *LP_UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// LP_UART.CLK_CONF: UART core clock configuration +func (o *LP_UART_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f)|value) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f +} +func (o *LP_UART_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *LP_UART_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *LP_UART_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *LP_UART_Type) SetCLK_CONF_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LP_UART_Type) GetCLK_CONF_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *LP_UART_Type) SetCLK_CONF_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LP_UART_Type) GetCLK_CONF_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x800000) >> 23 +} +func (o *LP_UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LP_UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LP_UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LP_UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *LP_UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} + +// LP_UART.DATE: UART Version register +func (o *LP_UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *LP_UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// LP_UART.AFIFO_STATUS: UART AFIFO Status +func (o *LP_UART_Type) SetAFIFO_STATUS_TX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_TX_AFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x1 +} +func (o *LP_UART_Type) SetAFIFO_STATUS_TX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_TX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetAFIFO_STATUS_RX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_RX_AFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetAFIFO_STATUS_RX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_RX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x8) >> 3 +} + +// LP_UART.REG_UPDATE: UART Registers Configuration Update register +func (o *LP_UART_Type) SetREG_UPDATE(value uint32) { + volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetREG_UPDATE() uint32 { + return volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x1 +} + +// LP_UART.ID: UART ID register +func (o *LP_UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, value) +} +func (o *LP_UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) +} + +// Low-power Watchdog Timer +type LP_WDT_Type struct { + CONFIG0 volatile.Register32 // 0x0 + CONFIG1 volatile.Register32 // 0x4 + CONFIG2 volatile.Register32 // 0x8 + CONFIG3 volatile.Register32 // 0xC + CONFIG4 volatile.Register32 // 0x10 + FEED volatile.Register32 // 0x14 + WPROTECT volatile.Register32 // 0x18 + SWD_CONFIG volatile.Register32 // 0x1C + SWD_WPROTECT volatile.Register32 // 0x20 + INT_RAW volatile.Register32 // 0x24 + INT_ST volatile.Register32 // 0x28 + INT_ENA volatile.Register32 // 0x2C + INT_CLR volatile.Register32 // 0x30 + _ [968]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_WDT.CONFIG0: need_des +func (o *LP_WDT_Type) SetCONFIG0_WDT_CHIP_RESET_WIDTH(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0xff)|value) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_CHIP_RESET_WIDTH() uint32 { + return volatile.LoadUint32(&o.CONFIG0.Reg) & 0xff +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_CHIP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x100)|value<<8) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_CHIP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x100) >> 8 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_PAUSE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x200)|value<<9) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_PAUSE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x200) >> 9 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x400)|value<<10) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x400) >> 10 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x800)|value<<11) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x800) >> 11 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x1000) >> 12 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0xe000)|value<<13) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0xe000) >> 13 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x70000)|value<<16) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x70000) >> 16 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x380000)|value<<19) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x380000) >> 19 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x1c00000) >> 22 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0xe000000)|value<<25) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0xe000000) >> 25 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x70000000)|value<<28) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x70000000) >> 28 +} +func (o *LP_WDT_Type) SetCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.CONFIG1: need_des +func (o *LP_WDT_Type) SetCONFIG1(value uint32) { + volatile.StoreUint32(&o.CONFIG1.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG1() uint32 { + return volatile.LoadUint32(&o.CONFIG1.Reg) +} + +// LP_WDT.CONFIG2: need_des +func (o *LP_WDT_Type) SetCONFIG2(value uint32) { + volatile.StoreUint32(&o.CONFIG2.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG2() uint32 { + return volatile.LoadUint32(&o.CONFIG2.Reg) +} + +// LP_WDT.CONFIG3: need_des +func (o *LP_WDT_Type) SetCONFIG3(value uint32) { + volatile.StoreUint32(&o.CONFIG3.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG3() uint32 { + return volatile.LoadUint32(&o.CONFIG3.Reg) +} + +// LP_WDT.CONFIG4: need_des +func (o *LP_WDT_Type) SetCONFIG4(value uint32) { + volatile.StoreUint32(&o.CONFIG4.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG4() uint32 { + return volatile.LoadUint32(&o.CONFIG4.Reg) +} + +// LP_WDT.FEED: need_des +func (o *LP_WDT_Type) SetFEED_RTC_WDT_FEED(value uint32) { + volatile.StoreUint32(&o.FEED.Reg, volatile.LoadUint32(&o.FEED.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetFEED_RTC_WDT_FEED() uint32 { + return (volatile.LoadUint32(&o.FEED.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.WPROTECT: need_des +func (o *LP_WDT_Type) SetWPROTECT(value uint32) { + volatile.StoreUint32(&o.WPROTECT.Reg, value) +} +func (o *LP_WDT_Type) GetWPROTECT() uint32 { + return volatile.LoadUint32(&o.WPROTECT.Reg) +} + +// LP_WDT.SWD_CONFIG: need_des +func (o *LP_WDT_Type) SetSWD_CONFIG_SWD_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x1)|value) +} +func (o *LP_WDT_Type) GetSWD_CONFIG_SWD_RESET_FLAG() uint32 { + return volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x1 +} +func (o *LP_WDT_Type) SetSWD_CONFIG_SWD_AUTO_FEED_EN(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x40000)|value<<18) +} +func (o *LP_WDT_Type) GetSWD_CONFIG_SWD_AUTO_FEED_EN() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x40000) >> 18 +} +func (o *LP_WDT_Type) SetSWD_CONFIG_SWD_RST_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x80000)|value<<19) +} +func (o *LP_WDT_Type) GetSWD_CONFIG_SWD_RST_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x80000) >> 19 +} +func (o *LP_WDT_Type) SetSWD_CONFIG_SWD_SIGNAL_WIDTH(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LP_WDT_Type) GetSWD_CONFIG_SWD_SIGNAL_WIDTH() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x3ff00000) >> 20 +} +func (o *LP_WDT_Type) SetSWD_CONFIG_SWD_DISABLE(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetSWD_CONFIG_SWD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetSWD_CONFIG_SWD_FEED(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetSWD_CONFIG_SWD_FEED() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.SWD_WPROTECT: need_des +func (o *LP_WDT_Type) SetSWD_WPROTECT(value uint32) { + volatile.StoreUint32(&o.SWD_WPROTECT.Reg, value) +} +func (o *LP_WDT_Type) GetSWD_WPROTECT() uint32 { + return volatile.LoadUint32(&o.SWD_WPROTECT.Reg) +} + +// LP_WDT.INT_RAW: need_des +func (o *LP_WDT_Type) SetINT_RAW_SUPER_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_RAW_SUPER_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_RAW_LP_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_RAW_LP_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.INT_ST: need_des +func (o *LP_WDT_Type) SetINT_ST_SUPER_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_ST_SUPER_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_ST_LP_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_ST_LP_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.INT_ENA: need_des +func (o *LP_WDT_Type) SetINT_ENA_SUPER_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_ENA_SUPER_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_ENA_LP_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_ENA_LP_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.INT_CLR: need_des +func (o *LP_WDT_Type) SetINT_CLR_SUPER_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_CLR_SUPER_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_CLR_LP_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_CLR_LP_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.DATE: need_des +func (o *LP_WDT_Type) SetDATE_LP_WDT_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_WDT_Type) GetDATE_LP_WDT_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_WDT_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Constants for LP_I2C: Low-power I2C (Inter-Integrated Circuit) Controller +const ( + // SCL_LOW_PERIOD: Configures the low level width of the SCL Clock + // Position of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x1ff + + // CTR: Transmission setting + // Position of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + I2C_CTR_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + I2C_CTR_SCL_FORCE_OUT = 0x2 + // Position of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2 + // Bit mask of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4 + // Bit SAMPLE_SCL_LEVEL. + I2C_CTR_SAMPLE_SCL_LEVEL = 0x4 + // Position of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Pos = 0x3 + // Bit mask of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Msk = 0x8 + // Bit RX_FULL_ACK_LEVEL. + I2C_CTR_RX_FULL_ACK_LEVEL = 0x8 + // Position of TRANS_START field. + I2C_CTR_TRANS_START_Pos = 0x5 + // Bit mask of TRANS_START field. + I2C_CTR_TRANS_START_Msk = 0x20 + // Bit TRANS_START. + I2C_CTR_TRANS_START = 0x20 + // Position of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Msk = 0x40 + // Bit TX_LSB_FIRST. + I2C_CTR_TX_LSB_FIRST = 0x40 + // Position of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Msk = 0x80 + // Bit RX_LSB_FIRST. + I2C_CTR_RX_LSB_FIRST = 0x80 + // Position of CLK_EN field. + I2C_CTR_CLK_EN_Pos = 0x8 + // Bit mask of CLK_EN field. + I2C_CTR_CLK_EN_Msk = 0x100 + // Bit CLK_EN. + I2C_CTR_CLK_EN = 0x100 + // Position of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Pos = 0x9 + // Bit mask of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Msk = 0x200 + // Bit ARBITRATION_EN. + I2C_CTR_ARBITRATION_EN = 0x200 + // Position of FSM_RST field. + I2C_CTR_FSM_RST_Pos = 0xa + // Bit mask of FSM_RST field. + I2C_CTR_FSM_RST_Msk = 0x400 + // Bit FSM_RST. + I2C_CTR_FSM_RST = 0x400 + // Position of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Pos = 0xb + // Bit mask of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Msk = 0x800 + // Bit CONF_UPGATE. + I2C_CTR_CONF_UPGATE = 0x800 + + // SR: Describe I2C work status. + // Position of RESP_REC field. + I2C_SR_RESP_REC_Pos = 0x0 + // Bit mask of RESP_REC field. + I2C_SR_RESP_REC_Msk = 0x1 + // Bit RESP_REC. + I2C_SR_RESP_REC = 0x1 + // Position of ARB_LOST field. + I2C_SR_ARB_LOST_Pos = 0x3 + // Bit mask of ARB_LOST field. + I2C_SR_ARB_LOST_Msk = 0x8 + // Bit ARB_LOST. + I2C_SR_ARB_LOST = 0x8 + // Position of BUS_BUSY field. + I2C_SR_BUS_BUSY_Pos = 0x4 + // Bit mask of BUS_BUSY field. + I2C_SR_BUS_BUSY_Msk = 0x10 + // Bit BUS_BUSY. + I2C_SR_BUS_BUSY = 0x10 + // Position of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Pos = 0x8 + // Bit mask of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Msk = 0x1f00 + // Position of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Pos = 0x12 + // Bit mask of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Msk = 0x7c0000 + // Position of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: Setting time out control for receiving data. + // Position of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Pos = 0x0 + // Bit mask of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Msk = 0x1f + // Position of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Pos = 0x5 + // Bit mask of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Msk = 0x20 + // Bit TIME_OUT_EN. + I2C_TO_TIME_OUT_EN = 0x20 + + // FIFO_ST: FIFO status register. + // Position of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Pos = 0x0 + // Bit mask of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Msk = 0xf + // Position of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Pos = 0x5 + // Bit mask of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Msk = 0x1e0 + // Position of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Pos = 0xa + // Bit mask of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Msk = 0x3c00 + // Position of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Pos = 0xf + // Bit mask of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Msk = 0x78000 + + // FIFO_CONF: FIFO configuration register. + // Position of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0xf + // Position of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5 + // Bit mask of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x1e0 + // Position of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa + // Bit mask of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400 + // Bit NONFIFO_EN. + I2C_FIFO_CONF_NONFIFO_EN = 0x400 + // Position of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc + // Bit mask of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000 + // Bit RX_FIFO_RST. + I2C_FIFO_CONF_RX_FIFO_RST = 0x1000 + // Position of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd + // Bit mask of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000 + // Bit TX_FIFO_RST. + I2C_FIFO_CONF_TX_FIFO_RST = 0x2000 + // Position of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Pos = 0xe + // Bit mask of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000 + // Bit FIFO_PRT_EN. + I2C_FIFO_CONF_FIFO_PRT_EN = 0x4000 + + // DATA: Rx FIFO read data. + // Position of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Pos = 0x0 + // Bit mask of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Msk = 0x1 + // Bit RXFIFO_WM_INT_RAW. + I2C_INT_RAW_RXFIFO_WM_INT_RAW = 0x1 + // Position of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Msk = 0x2 + // Bit TXFIFO_WM_INT_RAW. + I2C_INT_RAW_TXFIFO_WM_INT_RAW = 0x2 + // Position of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4 + // Bit RXFIFO_OVF_INT_RAW. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4 + // Position of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3 + // Bit mask of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8 + // Bit END_DETECT_INT_RAW. + I2C_INT_RAW_END_DETECT_INT_RAW = 0x8 + // Position of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_RAW. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW = 0x10 + // Position of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_RAW. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20 + // Position of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_RAW. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW = 0x40 + // Position of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_RAW. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80 + // Position of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8 + // Bit mask of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100 + // Bit TIME_OUT_INT_RAW. + I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100 + // Position of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9 + // Bit mask of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200 + // Bit TRANS_START_INT_RAW. + I2C_INT_RAW_TRANS_START_INT_RAW = 0x200 + // Position of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Pos = 0xa + // Bit mask of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Msk = 0x400 + // Bit NACK_INT_RAW. + I2C_INT_RAW_NACK_INT_RAW = 0x400 + // Position of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Msk = 0x800 + // Bit TXFIFO_OVF_INT_RAW. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW = 0x800 + // Position of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_RAW. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW = 0x1000 + // Position of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Msk = 0x2000 + // Bit SCL_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_ST_TO_INT_RAW = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW = 0x4000 + // Position of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Pos = 0xf + // Bit mask of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Msk = 0x8000 + // Bit DET_START_INT_RAW. + I2C_INT_RAW_DET_START_INT_RAW = 0x8000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Msk = 0x1 + // Bit RXFIFO_WM_INT_CLR. + I2C_INT_CLR_RXFIFO_WM_INT_CLR = 0x1 + // Position of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Msk = 0x2 + // Bit TXFIFO_WM_INT_CLR. + I2C_INT_CLR_TXFIFO_WM_INT_CLR = 0x2 + // Position of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4 + // Bit RXFIFO_OVF_INT_CLR. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4 + // Position of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3 + // Bit mask of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8 + // Bit END_DETECT_INT_CLR. + I2C_INT_CLR_END_DETECT_INT_CLR = 0x8 + // Position of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_CLR. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR = 0x10 + // Position of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_CLR. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_CLR. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR = 0x40 + // Position of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_CLR. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit TIME_OUT_INT_CLR. + I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100 + // Position of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9 + // Bit mask of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200 + // Bit TRANS_START_INT_CLR. + I2C_INT_CLR_TRANS_START_INT_CLR = 0x200 + // Position of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Pos = 0xa + // Bit mask of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Msk = 0x400 + // Bit NACK_INT_CLR. + I2C_INT_CLR_NACK_INT_CLR = 0x400 + // Position of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Msk = 0x800 + // Bit TXFIFO_OVF_INT_CLR. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR = 0x800 + // Position of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_CLR. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR = 0x1000 + // Position of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Msk = 0x2000 + // Bit SCL_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_ST_TO_INT_CLR = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR = 0x4000 + // Position of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Pos = 0xf + // Bit mask of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Msk = 0x8000 + // Bit DET_START_INT_CLR. + I2C_INT_CLR_DET_START_INT_CLR = 0x8000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Msk = 0x1 + // Bit RXFIFO_WM_INT_ENA. + I2C_INT_ENA_RXFIFO_WM_INT_ENA = 0x1 + // Position of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Msk = 0x2 + // Bit TXFIFO_WM_INT_ENA. + I2C_INT_ENA_TXFIFO_WM_INT_ENA = 0x2 + // Position of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ENA. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4 + // Position of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3 + // Bit mask of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8 + // Bit END_DETECT_INT_ENA. + I2C_INT_ENA_END_DETECT_INT_ENA = 0x8 + // Position of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ENA. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA = 0x10 + // Position of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ENA. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20 + // Position of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ENA. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA = 0x40 + // Position of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ENA. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80 + // Position of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100 + // Bit TIME_OUT_INT_ENA. + I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100 + // Position of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9 + // Bit mask of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200 + // Bit TRANS_START_INT_ENA. + I2C_INT_ENA_TRANS_START_INT_ENA = 0x200 + // Position of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Pos = 0xa + // Bit mask of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Msk = 0x400 + // Bit NACK_INT_ENA. + I2C_INT_ENA_NACK_INT_ENA = 0x400 + // Position of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ENA. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA = 0x800 + // Position of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ENA. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA = 0x1000 + // Position of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_ST_TO_INT_ENA = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA = 0x4000 + // Position of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Pos = 0xf + // Bit mask of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Msk = 0x8000 + // Bit DET_START_INT_ENA. + I2C_INT_ENA_DET_START_INT_ENA = 0x8000 + + // INT_STATUS: Status of captured I2C communication events + // Position of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Msk = 0x1 + // Bit RXFIFO_WM_INT_ST. + I2C_INT_STATUS_RXFIFO_WM_INT_ST = 0x1 + // Position of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Msk = 0x2 + // Bit TXFIFO_WM_INT_ST. + I2C_INT_STATUS_TXFIFO_WM_INT_ST = 0x2 + // Position of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ST. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4 + // Position of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3 + // Bit mask of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8 + // Bit END_DETECT_INT_ST. + I2C_INT_STATUS_END_DETECT_INT_ST = 0x8 + // Position of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ST. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST = 0x10 + // Position of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ST. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20 + // Position of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ST. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST = 0x40 + // Position of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ST. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80 + // Position of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100 + // Bit TIME_OUT_INT_ST. + I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100 + // Position of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9 + // Bit mask of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200 + // Bit TRANS_START_INT_ST. + I2C_INT_STATUS_TRANS_START_INT_ST = 0x200 + // Position of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Pos = 0xa + // Bit mask of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Msk = 0x400 + // Bit NACK_INT_ST. + I2C_INT_STATUS_NACK_INT_ST = 0x400 + // Position of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ST. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST = 0x800 + // Position of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ST. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST = 0x1000 + // Position of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_ST_TO_INT_ST = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST = 0x4000 + // Position of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Pos = 0xf + // Bit mask of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Msk = 0x8000 + // Bit DET_START_INT_ST. + I2C_INT_STATUS_DET_START_INT_ST = 0x8000 + + // SDA_HOLD: Configures the hold time after a negative SCL edge. + // Position of TIME field. + I2C_SDA_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_HOLD_TIME_Msk = 0x1ff + + // SDA_SAMPLE: Configures the sample time after a positive SCL edge. + // Position of TIME field. + I2C_SDA_SAMPLE_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_SAMPLE_TIME_Msk = 0x1ff + + // SCL_HIGH_PERIOD: Configures the high level width of SCL + // Position of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x1ff + // Position of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Pos = 0x9 + // Bit mask of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Msk = 0xfe00 + + // SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition + // Position of TIME field. + I2C_SCL_START_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_START_HOLD_TIME_Msk = 0x1ff + + // SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA + // Position of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Msk = 0x1ff + + // SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_HOLD_TIME_Msk = 0x1ff + + // SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_SETUP_TIME_Msk = 0x1ff + + // FILTER_CFG: SCL and SDA filter configuration register + // Position of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0 + // Bit mask of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Msk = 0xf + // Position of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x4 + // Bit mask of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Msk = 0xf0 + // Position of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Pos = 0x8 + // Bit mask of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Msk = 0x100 + // Bit SCL_FILTER_EN. + I2C_FILTER_CFG_SCL_FILTER_EN = 0x100 + // Position of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Pos = 0x9 + // Bit mask of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Msk = 0x200 + // Bit SDA_FILTER_EN. + I2C_FILTER_CFG_SDA_FILTER_EN = 0x200 + + // CLK_CONF: I2C CLK configuration register + // Position of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Pos = 0x0 + // Bit mask of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff + // Position of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Pos = 0x8 + // Bit mask of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Msk = 0x3f00 + // Position of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Pos = 0xe + // Bit mask of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Msk = 0xfc000 + // Position of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Msk = 0x100000 + // Bit SCLK_SEL. + I2C_CLK_CONF_SCLK_SEL = 0x100000 + // Position of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Pos = 0x15 + // Bit mask of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Msk = 0x200000 + // Bit SCLK_ACTIVE. + I2C_CLK_CONF_SCLK_ACTIVE = 0x200000 + + // COMD0: I2C command register 0 + // Position of COMMAND0 field. + I2C_COMD0_COMMAND0_Pos = 0x0 + // Bit mask of COMMAND0 field. + I2C_COMD0_COMMAND0_Msk = 0x3fff + // Position of COMMAND0_DONE field. + I2C_COMD0_COMMAND0_DONE_Pos = 0x1f + // Bit mask of COMMAND0_DONE field. + I2C_COMD0_COMMAND0_DONE_Msk = 0x80000000 + // Bit COMMAND0_DONE. + I2C_COMD0_COMMAND0_DONE = 0x80000000 + + // COMD1: I2C command register 1 + // Position of COMMAND1 field. + I2C_COMD1_COMMAND1_Pos = 0x0 + // Bit mask of COMMAND1 field. + I2C_COMD1_COMMAND1_Msk = 0x3fff + // Position of COMMAND1_DONE field. + I2C_COMD1_COMMAND1_DONE_Pos = 0x1f + // Bit mask of COMMAND1_DONE field. + I2C_COMD1_COMMAND1_DONE_Msk = 0x80000000 + // Bit COMMAND1_DONE. + I2C_COMD1_COMMAND1_DONE = 0x80000000 + + // COMD2: I2C command register 2 + // Position of COMMAND2 field. + I2C_COMD2_COMMAND2_Pos = 0x0 + // Bit mask of COMMAND2 field. + I2C_COMD2_COMMAND2_Msk = 0x3fff + // Position of COMMAND2_DONE field. + I2C_COMD2_COMMAND2_DONE_Pos = 0x1f + // Bit mask of COMMAND2_DONE field. + I2C_COMD2_COMMAND2_DONE_Msk = 0x80000000 + // Bit COMMAND2_DONE. + I2C_COMD2_COMMAND2_DONE = 0x80000000 + + // COMD3: I2C command register 3 + // Position of COMMAND3 field. + I2C_COMD3_COMMAND3_Pos = 0x0 + // Bit mask of COMMAND3 field. + I2C_COMD3_COMMAND3_Msk = 0x3fff + // Position of COMMAND3_DONE field. + I2C_COMD3_COMMAND3_DONE_Pos = 0x1f + // Bit mask of COMMAND3_DONE field. + I2C_COMD3_COMMAND3_DONE_Msk = 0x80000000 + // Bit COMMAND3_DONE. + I2C_COMD3_COMMAND3_DONE = 0x80000000 + + // COMD4: I2C command register 4 + // Position of COMMAND4 field. + I2C_COMD4_COMMAND4_Pos = 0x0 + // Bit mask of COMMAND4 field. + I2C_COMD4_COMMAND4_Msk = 0x3fff + // Position of COMMAND4_DONE field. + I2C_COMD4_COMMAND4_DONE_Pos = 0x1f + // Bit mask of COMMAND4_DONE field. + I2C_COMD4_COMMAND4_DONE_Msk = 0x80000000 + // Bit COMMAND4_DONE. + I2C_COMD4_COMMAND4_DONE = 0x80000000 + + // COMD5: I2C command register 5 + // Position of COMMAND5 field. + I2C_COMD5_COMMAND5_Pos = 0x0 + // Bit mask of COMMAND5 field. + I2C_COMD5_COMMAND5_Msk = 0x3fff + // Position of COMMAND5_DONE field. + I2C_COMD5_COMMAND5_DONE_Pos = 0x1f + // Bit mask of COMMAND5_DONE field. + I2C_COMD5_COMMAND5_DONE_Msk = 0x80000000 + // Bit COMMAND5_DONE. + I2C_COMD5_COMMAND5_DONE = 0x80000000 + + // COMD6: I2C command register 6 + // Position of COMMAND6 field. + I2C_COMD6_COMMAND6_Pos = 0x0 + // Bit mask of COMMAND6 field. + I2C_COMD6_COMMAND6_Msk = 0x3fff + // Position of COMMAND6_DONE field. + I2C_COMD6_COMMAND6_DONE_Pos = 0x1f + // Bit mask of COMMAND6_DONE field. + I2C_COMD6_COMMAND6_DONE_Msk = 0x80000000 + // Bit COMMAND6_DONE. + I2C_COMD6_COMMAND6_DONE = 0x80000000 + + // COMD7: I2C command register 7 + // Position of COMMAND7 field. + I2C_COMD7_COMMAND7_Pos = 0x0 + // Bit mask of COMMAND7 field. + I2C_COMD7_COMMAND7_Msk = 0x3fff + // Position of COMMAND7_DONE field. + I2C_COMD7_COMMAND7_DONE_Pos = 0x1f + // Bit mask of COMMAND7_DONE field. + I2C_COMD7_COMMAND7_DONE_Msk = 0x80000000 + // Bit COMMAND7_DONE. + I2C_COMD7_COMMAND7_DONE = 0x80000000 + + // SCL_ST_TIME_OUT: SCL status time out register + // Position of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Msk = 0x1f + + // SCL_MAIN_ST_TIME_OUT: SCL main status time out register + // Position of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Msk = 0x1f + + // SCL_SP_CONF: Power configuration register + // Position of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Pos = 0x0 + // Bit mask of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Msk = 0x1 + // Bit SCL_RST_SLV_EN. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN = 0x1 + // Position of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Pos = 0x1 + // Bit mask of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Msk = 0x3e + // Position of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Pos = 0x6 + // Bit mask of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Msk = 0x40 + // Bit SCL_PD_EN. + I2C_SCL_SP_CONF_SCL_PD_EN = 0x40 + // Position of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Pos = 0x7 + // Bit mask of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Msk = 0x80 + // Bit SDA_PD_EN. + I2C_SCL_SP_CONF_SDA_PD_EN = 0x80 + + // DATE: Version register + // Position of DATE field. + I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2C_DATE_DATE_Msk = 0xffffffff + + // TXFIFO_START_ADDR: I2C TXFIFO base address register + // Position of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Msk = 0xffffffff + + // RXFIFO_START_ADDR: I2C RXFIFO base address register + // Position of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Msk = 0xffffffff +) + +// Constants for LP_PERI: LP_PERI Peripheral +const ( + // CLK_EN: need_des + // Position of LP_TOUCH_CK_EN field. + LPPERI_CLK_EN_LP_TOUCH_CK_EN_Pos = 0x17 + // Bit mask of LP_TOUCH_CK_EN field. + LPPERI_CLK_EN_LP_TOUCH_CK_EN_Msk = 0x800000 + // Bit LP_TOUCH_CK_EN. + LPPERI_CLK_EN_LP_TOUCH_CK_EN = 0x800000 + // Position of RNG_CK_EN field. + LPPERI_CLK_EN_RNG_CK_EN_Pos = 0x18 + // Bit mask of RNG_CK_EN field. + LPPERI_CLK_EN_RNG_CK_EN_Msk = 0x1000000 + // Bit RNG_CK_EN. + LPPERI_CLK_EN_RNG_CK_EN = 0x1000000 + // Position of OTP_DBG_CK_EN field. + LPPERI_CLK_EN_OTP_DBG_CK_EN_Pos = 0x19 + // Bit mask of OTP_DBG_CK_EN field. + LPPERI_CLK_EN_OTP_DBG_CK_EN_Msk = 0x2000000 + // Bit OTP_DBG_CK_EN. + LPPERI_CLK_EN_OTP_DBG_CK_EN = 0x2000000 + // Position of LP_UART_CK_EN field. + LPPERI_CLK_EN_LP_UART_CK_EN_Pos = 0x1a + // Bit mask of LP_UART_CK_EN field. + LPPERI_CLK_EN_LP_UART_CK_EN_Msk = 0x4000000 + // Bit LP_UART_CK_EN. + LPPERI_CLK_EN_LP_UART_CK_EN = 0x4000000 + // Position of LP_IO_CK_EN field. + LPPERI_CLK_EN_LP_IO_CK_EN_Pos = 0x1b + // Bit mask of LP_IO_CK_EN field. + LPPERI_CLK_EN_LP_IO_CK_EN_Msk = 0x8000000 + // Bit LP_IO_CK_EN. + LPPERI_CLK_EN_LP_IO_CK_EN = 0x8000000 + // Position of LP_EXT_I2C_CK_EN field. + LPPERI_CLK_EN_LP_EXT_I2C_CK_EN_Pos = 0x1c + // Bit mask of LP_EXT_I2C_CK_EN field. + LPPERI_CLK_EN_LP_EXT_I2C_CK_EN_Msk = 0x10000000 + // Bit LP_EXT_I2C_CK_EN. + LPPERI_CLK_EN_LP_EXT_I2C_CK_EN = 0x10000000 + // Position of LP_ANA_I2C_CK_EN field. + LPPERI_CLK_EN_LP_ANA_I2C_CK_EN_Pos = 0x1d + // Bit mask of LP_ANA_I2C_CK_EN field. + LPPERI_CLK_EN_LP_ANA_I2C_CK_EN_Msk = 0x20000000 + // Bit LP_ANA_I2C_CK_EN. + LPPERI_CLK_EN_LP_ANA_I2C_CK_EN = 0x20000000 + // Position of EFUSE_CK_EN field. + LPPERI_CLK_EN_EFUSE_CK_EN_Pos = 0x1e + // Bit mask of EFUSE_CK_EN field. + LPPERI_CLK_EN_EFUSE_CK_EN_Msk = 0x40000000 + // Bit EFUSE_CK_EN. + LPPERI_CLK_EN_EFUSE_CK_EN = 0x40000000 + // Position of LP_CPU_CK_EN field. + LPPERI_CLK_EN_LP_CPU_CK_EN_Pos = 0x1f + // Bit mask of LP_CPU_CK_EN field. + LPPERI_CLK_EN_LP_CPU_CK_EN_Msk = 0x80000000 + // Bit LP_CPU_CK_EN. + LPPERI_CLK_EN_LP_CPU_CK_EN = 0x80000000 + + // RESET_EN: need_des + // Position of BUS_RESET_EN field. + LPPERI_RESET_EN_BUS_RESET_EN_Pos = 0x17 + // Bit mask of BUS_RESET_EN field. + LPPERI_RESET_EN_BUS_RESET_EN_Msk = 0x800000 + // Bit BUS_RESET_EN. + LPPERI_RESET_EN_BUS_RESET_EN = 0x800000 + // Position of LP_TOUCH_RESET_EN field. + LPPERI_RESET_EN_LP_TOUCH_RESET_EN_Pos = 0x18 + // Bit mask of LP_TOUCH_RESET_EN field. + LPPERI_RESET_EN_LP_TOUCH_RESET_EN_Msk = 0x1000000 + // Bit LP_TOUCH_RESET_EN. + LPPERI_RESET_EN_LP_TOUCH_RESET_EN = 0x1000000 + // Position of OTP_DBG_RESET_EN field. + LPPERI_RESET_EN_OTP_DBG_RESET_EN_Pos = 0x19 + // Bit mask of OTP_DBG_RESET_EN field. + LPPERI_RESET_EN_OTP_DBG_RESET_EN_Msk = 0x2000000 + // Bit OTP_DBG_RESET_EN. + LPPERI_RESET_EN_OTP_DBG_RESET_EN = 0x2000000 + // Position of LP_UART_RESET_EN field. + LPPERI_RESET_EN_LP_UART_RESET_EN_Pos = 0x1a + // Bit mask of LP_UART_RESET_EN field. + LPPERI_RESET_EN_LP_UART_RESET_EN_Msk = 0x4000000 + // Bit LP_UART_RESET_EN. + LPPERI_RESET_EN_LP_UART_RESET_EN = 0x4000000 + // Position of LP_IO_RESET_EN field. + LPPERI_RESET_EN_LP_IO_RESET_EN_Pos = 0x1b + // Bit mask of LP_IO_RESET_EN field. + LPPERI_RESET_EN_LP_IO_RESET_EN_Msk = 0x8000000 + // Bit LP_IO_RESET_EN. + LPPERI_RESET_EN_LP_IO_RESET_EN = 0x8000000 + // Position of LP_EXT_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_EXT_I2C_RESET_EN_Pos = 0x1c + // Bit mask of LP_EXT_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_EXT_I2C_RESET_EN_Msk = 0x10000000 + // Bit LP_EXT_I2C_RESET_EN. + LPPERI_RESET_EN_LP_EXT_I2C_RESET_EN = 0x10000000 + // Position of LP_ANA_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_ANA_I2C_RESET_EN_Pos = 0x1d + // Bit mask of LP_ANA_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_ANA_I2C_RESET_EN_Msk = 0x20000000 + // Bit LP_ANA_I2C_RESET_EN. + LPPERI_RESET_EN_LP_ANA_I2C_RESET_EN = 0x20000000 + // Position of EFUSE_RESET_EN field. + LPPERI_RESET_EN_EFUSE_RESET_EN_Pos = 0x1e + // Bit mask of EFUSE_RESET_EN field. + LPPERI_RESET_EN_EFUSE_RESET_EN_Msk = 0x40000000 + // Bit EFUSE_RESET_EN. + LPPERI_RESET_EN_EFUSE_RESET_EN = 0x40000000 + // Position of LP_CPU_RESET_EN field. + LPPERI_RESET_EN_LP_CPU_RESET_EN_Pos = 0x1f + // Bit mask of LP_CPU_RESET_EN field. + LPPERI_RESET_EN_LP_CPU_RESET_EN_Msk = 0x80000000 + // Bit LP_CPU_RESET_EN. + LPPERI_RESET_EN_LP_CPU_RESET_EN = 0x80000000 + + // RNG_DATA: need_des + // Position of RND_DATA field. + LPPERI_RNG_DATA_RND_DATA_Pos = 0x0 + // Bit mask of RND_DATA field. + LPPERI_RNG_DATA_RND_DATA_Msk = 0xffffffff + + // CPU: need_des + // Position of LPCORE_DBGM_UNAVALIABLE field. + LPPERI_CPU_LPCORE_DBGM_UNAVALIABLE_Pos = 0x1f + // Bit mask of LPCORE_DBGM_UNAVALIABLE field. + LPPERI_CPU_LPCORE_DBGM_UNAVALIABLE_Msk = 0x80000000 + // Bit LPCORE_DBGM_UNAVALIABLE. + LPPERI_CPU_LPCORE_DBGM_UNAVALIABLE = 0x80000000 + + // BUS_TIMEOUT: need_des + // Position of LP_PERI_TIMEOUT_THRES field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_THRES_Pos = 0xe + // Bit mask of LP_PERI_TIMEOUT_THRES field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_THRES_Msk = 0x3fffc000 + // Position of LP_PERI_TIMEOUT_INT_CLEAR field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR_Pos = 0x1e + // Bit mask of LP_PERI_TIMEOUT_INT_CLEAR field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR_Msk = 0x40000000 + // Bit LP_PERI_TIMEOUT_INT_CLEAR. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR = 0x40000000 + // Position of LP_PERI_TIMEOUT_PROTECT_EN field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN_Pos = 0x1f + // Bit mask of LP_PERI_TIMEOUT_PROTECT_EN field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN_Msk = 0x80000000 + // Bit LP_PERI_TIMEOUT_PROTECT_EN. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN = 0x80000000 + + // BUS_TIMEOUT_ADDR: need_des + // Position of LP_PERI_TIMEOUT_ADDR field. + LPPERI_BUS_TIMEOUT_ADDR_LP_PERI_TIMEOUT_ADDR_Pos = 0x0 + // Bit mask of LP_PERI_TIMEOUT_ADDR field. + LPPERI_BUS_TIMEOUT_ADDR_LP_PERI_TIMEOUT_ADDR_Msk = 0xffffffff + + // BUS_TIMEOUT_UID: need_des + // Position of LP_PERI_TIMEOUT_UID field. + LPPERI_BUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID_Pos = 0x0 + // Bit mask of LP_PERI_TIMEOUT_UID field. + LPPERI_BUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID_Msk = 0x7f + + // MEM_CTRL: need_des + // Position of UART_WAKEUP_FLAG_CLR field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_CLR_Pos = 0x0 + // Bit mask of UART_WAKEUP_FLAG_CLR field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_CLR_Msk = 0x1 + // Bit UART_WAKEUP_FLAG_CLR. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_CLR = 0x1 + // Position of UART_WAKEUP_FLAG field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_Pos = 0x1 + // Bit mask of UART_WAKEUP_FLAG field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_Msk = 0x2 + // Bit UART_WAKEUP_FLAG. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG = 0x2 + // Position of UART_WAKEUP_EN field. + LPPERI_MEM_CTRL_UART_WAKEUP_EN_Pos = 0x1d + // Bit mask of UART_WAKEUP_EN field. + LPPERI_MEM_CTRL_UART_WAKEUP_EN_Msk = 0x20000000 + // Bit UART_WAKEUP_EN. + LPPERI_MEM_CTRL_UART_WAKEUP_EN = 0x20000000 + // Position of UART_MEM_FORCE_PD field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PD_Pos = 0x1e + // Bit mask of UART_MEM_FORCE_PD field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PD_Msk = 0x40000000 + // Bit UART_MEM_FORCE_PD. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PD = 0x40000000 + // Position of UART_MEM_FORCE_PU field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PU_Pos = 0x1f + // Bit mask of UART_MEM_FORCE_PU field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PU_Msk = 0x80000000 + // Bit UART_MEM_FORCE_PU. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PU = 0x80000000 + + // INTERRUPT_SOURCE: need_des + // Position of LP_INTERRUPT_SOURCE field. + LPPERI_INTERRUPT_SOURCE_LP_INTERRUPT_SOURCE_Pos = 0x0 + // Bit mask of LP_INTERRUPT_SOURCE field. + LPPERI_INTERRUPT_SOURCE_LP_INTERRUPT_SOURCE_Msk = 0x3f + + // DATE: need_des + // Position of LPPERI_DATE field. + LPPERI_DATE_LPPERI_DATE_Pos = 0x0 + // Bit mask of LPPERI_DATE field. + LPPERI_DATE_LPPERI_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LPPERI_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LPPERI_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LPPERI_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_ANA_PERI: LP_ANA_PERI Peripheral +const ( + // BOD_MODE0_CNTL: need_des + // Position of BOD_MODE0_CLOSE_FLASH_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA_Pos = 0x6 + // Bit mask of BOD_MODE0_CLOSE_FLASH_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA_Msk = 0x40 + // Bit BOD_MODE0_CLOSE_FLASH_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA = 0x40 + // Position of BOD_MODE0_PD_RF_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA_Pos = 0x7 + // Bit mask of BOD_MODE0_PD_RF_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA_Msk = 0x80 + // Bit BOD_MODE0_PD_RF_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA = 0x80 + // Position of BOD_MODE0_INTR_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT_Pos = 0x8 + // Bit mask of BOD_MODE0_INTR_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT_Msk = 0x3ff00 + // Position of BOD_MODE0_RESET_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT_Pos = 0x12 + // Bit mask of BOD_MODE0_RESET_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT_Msk = 0xffc0000 + // Position of BOD_MODE0_CNT_CLR field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CNT_CLR_Pos = 0x1c + // Bit mask of BOD_MODE0_CNT_CLR field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CNT_CLR_Msk = 0x10000000 + // Bit BOD_MODE0_CNT_CLR. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CNT_CLR = 0x10000000 + // Position of BOD_MODE0_INTR_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_ENA_Pos = 0x1d + // Bit mask of BOD_MODE0_INTR_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_ENA_Msk = 0x20000000 + // Bit BOD_MODE0_INTR_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_ENA = 0x20000000 + // Position of BOD_MODE0_RESET_SEL field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_SEL_Pos = 0x1e + // Bit mask of BOD_MODE0_RESET_SEL field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_SEL_Msk = 0x40000000 + // Bit BOD_MODE0_RESET_SEL. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_SEL = 0x40000000 + // Position of BOD_MODE0_RESET_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_ENA_Pos = 0x1f + // Bit mask of BOD_MODE0_RESET_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_ENA_Msk = 0x80000000 + // Bit BOD_MODE0_RESET_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_ENA = 0x80000000 + + // BOD_MODE1_CNTL: need_des + // Position of BOD_MODE1_RESET_ENA field. + LP_ANA_BOD_MODE1_CNTL_BOD_MODE1_RESET_ENA_Pos = 0x1f + // Bit mask of BOD_MODE1_RESET_ENA field. + LP_ANA_BOD_MODE1_CNTL_BOD_MODE1_RESET_ENA_Msk = 0x80000000 + // Bit BOD_MODE1_RESET_ENA. + LP_ANA_BOD_MODE1_CNTL_BOD_MODE1_RESET_ENA = 0x80000000 + + // CK_GLITCH_CNTL: need_des + // Position of CK_GLITCH_RESET_ENA field. + LP_ANA_CK_GLITCH_CNTL_CK_GLITCH_RESET_ENA_Pos = 0x1f + // Bit mask of CK_GLITCH_RESET_ENA field. + LP_ANA_CK_GLITCH_CNTL_CK_GLITCH_RESET_ENA_Msk = 0x80000000 + // Bit CK_GLITCH_RESET_ENA. + LP_ANA_CK_GLITCH_CNTL_CK_GLITCH_RESET_ENA = 0x80000000 + + // FIB_ENABLE: need_des + // Position of ANA_FIB_ENA field. + LP_ANA_FIB_ENABLE_ANA_FIB_ENA_Pos = 0x0 + // Bit mask of ANA_FIB_ENA field. + LP_ANA_FIB_ENABLE_ANA_FIB_ENA_Msk = 0xffffffff + + // INT_RAW: need_des + // Position of BOD_MODE0_INT_RAW field. + LP_ANA_INT_RAW_BOD_MODE0_INT_RAW_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_RAW field. + LP_ANA_INT_RAW_BOD_MODE0_INT_RAW_Msk = 0x80000000 + // Bit BOD_MODE0_INT_RAW. + LP_ANA_INT_RAW_BOD_MODE0_INT_RAW = 0x80000000 + + // INT_ST: need_des + // Position of BOD_MODE0_INT_ST field. + LP_ANA_INT_ST_BOD_MODE0_INT_ST_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_ST field. + LP_ANA_INT_ST_BOD_MODE0_INT_ST_Msk = 0x80000000 + // Bit BOD_MODE0_INT_ST. + LP_ANA_INT_ST_BOD_MODE0_INT_ST = 0x80000000 + + // INT_ENA: need_des + // Position of BOD_MODE0_INT_ENA field. + LP_ANA_INT_ENA_BOD_MODE0_INT_ENA_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_ENA field. + LP_ANA_INT_ENA_BOD_MODE0_INT_ENA_Msk = 0x80000000 + // Bit BOD_MODE0_INT_ENA. + LP_ANA_INT_ENA_BOD_MODE0_INT_ENA = 0x80000000 + + // INT_CLR: need_des + // Position of BOD_MODE0_INT_CLR field. + LP_ANA_INT_CLR_BOD_MODE0_INT_CLR_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_CLR field. + LP_ANA_INT_CLR_BOD_MODE0_INT_CLR_Msk = 0x80000000 + // Bit BOD_MODE0_INT_CLR. + LP_ANA_INT_CLR_BOD_MODE0_INT_CLR = 0x80000000 + + // LP_INT_RAW: need_des + // Position of BOD_MODE0_LP_INT_RAW field. + LP_ANA_LP_INT_RAW_BOD_MODE0_LP_INT_RAW_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_RAW field. + LP_ANA_LP_INT_RAW_BOD_MODE0_LP_INT_RAW_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_RAW. + LP_ANA_LP_INT_RAW_BOD_MODE0_LP_INT_RAW = 0x80000000 + + // LP_INT_ST: need_des + // Position of BOD_MODE0_LP_INT_ST field. + LP_ANA_LP_INT_ST_BOD_MODE0_LP_INT_ST_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_ST field. + LP_ANA_LP_INT_ST_BOD_MODE0_LP_INT_ST_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_ST. + LP_ANA_LP_INT_ST_BOD_MODE0_LP_INT_ST = 0x80000000 + + // LP_INT_ENA: need_des + // Position of BOD_MODE0_LP_INT_ENA field. + LP_ANA_LP_INT_ENA_BOD_MODE0_LP_INT_ENA_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_ENA field. + LP_ANA_LP_INT_ENA_BOD_MODE0_LP_INT_ENA_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_ENA. + LP_ANA_LP_INT_ENA_BOD_MODE0_LP_INT_ENA = 0x80000000 + + // LP_INT_CLR: need_des + // Position of BOD_MODE0_LP_INT_CLR field. + LP_ANA_LP_INT_CLR_BOD_MODE0_LP_INT_CLR_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_CLR field. + LP_ANA_LP_INT_CLR_BOD_MODE0_LP_INT_CLR_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_CLR. + LP_ANA_LP_INT_CLR_BOD_MODE0_LP_INT_CLR = 0x80000000 + + // DATE: need_des + // Position of LP_ANA_DATE field. + LP_ANA_DATE_LP_ANA_DATE_Pos = 0x0 + // Bit mask of LP_ANA_DATE field. + LP_ANA_DATE_LP_ANA_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_ANA_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_ANA_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_ANA_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_AON: LP_AON Peripheral +const ( + // STORE0: need_des + // Position of LP_AON_STORE0 field. + LP_AON_STORE0_LP_AON_STORE0_Pos = 0x0 + // Bit mask of LP_AON_STORE0 field. + LP_AON_STORE0_LP_AON_STORE0_Msk = 0xffffffff + + // STORE1: need_des + // Position of LP_AON_STORE1 field. + LP_AON_STORE1_LP_AON_STORE1_Pos = 0x0 + // Bit mask of LP_AON_STORE1 field. + LP_AON_STORE1_LP_AON_STORE1_Msk = 0xffffffff + + // STORE2: need_des + // Position of LP_AON_STORE2 field. + LP_AON_STORE2_LP_AON_STORE2_Pos = 0x0 + // Bit mask of LP_AON_STORE2 field. + LP_AON_STORE2_LP_AON_STORE2_Msk = 0xffffffff + + // STORE3: need_des + // Position of LP_AON_STORE3 field. + LP_AON_STORE3_LP_AON_STORE3_Pos = 0x0 + // Bit mask of LP_AON_STORE3 field. + LP_AON_STORE3_LP_AON_STORE3_Msk = 0xffffffff + + // STORE4: need_des + // Position of LP_AON_STORE4 field. + LP_AON_STORE4_LP_AON_STORE4_Pos = 0x0 + // Bit mask of LP_AON_STORE4 field. + LP_AON_STORE4_LP_AON_STORE4_Msk = 0xffffffff + + // STORE5: need_des + // Position of LP_AON_STORE5 field. + LP_AON_STORE5_LP_AON_STORE5_Pos = 0x0 + // Bit mask of LP_AON_STORE5 field. + LP_AON_STORE5_LP_AON_STORE5_Msk = 0xffffffff + + // STORE6: need_des + // Position of LP_AON_STORE6 field. + LP_AON_STORE6_LP_AON_STORE6_Pos = 0x0 + // Bit mask of LP_AON_STORE6 field. + LP_AON_STORE6_LP_AON_STORE6_Msk = 0xffffffff + + // STORE7: need_des + // Position of LP_AON_STORE7 field. + LP_AON_STORE7_LP_AON_STORE7_Pos = 0x0 + // Bit mask of LP_AON_STORE7 field. + LP_AON_STORE7_LP_AON_STORE7_Msk = 0xffffffff + + // STORE8: need_des + // Position of LP_AON_STORE8 field. + LP_AON_STORE8_LP_AON_STORE8_Pos = 0x0 + // Bit mask of LP_AON_STORE8 field. + LP_AON_STORE8_LP_AON_STORE8_Msk = 0xffffffff + + // STORE9: need_des + // Position of LP_AON_STORE9 field. + LP_AON_STORE9_LP_AON_STORE9_Pos = 0x0 + // Bit mask of LP_AON_STORE9 field. + LP_AON_STORE9_LP_AON_STORE9_Msk = 0xffffffff + + // GPIO_MUX: need_des + // Position of SEL field. + LP_AON_GPIO_MUX_SEL_Pos = 0x0 + // Bit mask of SEL field. + LP_AON_GPIO_MUX_SEL_Msk = 0xff + + // GPIO_HOLD0: need_des + // Position of GPIO_HOLD0 field. + LP_AON_GPIO_HOLD0_GPIO_HOLD0_Pos = 0x0 + // Bit mask of GPIO_HOLD0 field. + LP_AON_GPIO_HOLD0_GPIO_HOLD0_Msk = 0xffffffff + + // GPIO_HOLD1: need_des + // Position of GPIO_HOLD1 field. + LP_AON_GPIO_HOLD1_GPIO_HOLD1_Pos = 0x0 + // Bit mask of GPIO_HOLD1 field. + LP_AON_GPIO_HOLD1_GPIO_HOLD1_Msk = 0xffffffff + + // SYS_CFG: need_des + // Position of FORCE_DOWNLOAD_BOOT field. + LP_AON_SYS_CFG_FORCE_DOWNLOAD_BOOT_Pos = 0x1e + // Bit mask of FORCE_DOWNLOAD_BOOT field. + LP_AON_SYS_CFG_FORCE_DOWNLOAD_BOOT_Msk = 0x40000000 + // Bit FORCE_DOWNLOAD_BOOT. + LP_AON_SYS_CFG_FORCE_DOWNLOAD_BOOT = 0x40000000 + // Position of HPSYS_SW_RESET field. + LP_AON_SYS_CFG_HPSYS_SW_RESET_Pos = 0x1f + // Bit mask of HPSYS_SW_RESET field. + LP_AON_SYS_CFG_HPSYS_SW_RESET_Msk = 0x80000000 + // Bit HPSYS_SW_RESET. + LP_AON_SYS_CFG_HPSYS_SW_RESET = 0x80000000 + + // CPUCORE0_CFG: need_des + // Position of CPU_CORE0_SW_STALL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_STALL_Pos = 0x0 + // Bit mask of CPU_CORE0_SW_STALL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_STALL_Msk = 0xff + // Position of CPU_CORE0_SW_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_RESET_Pos = 0x1c + // Bit mask of CPU_CORE0_SW_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_RESET_Msk = 0x10000000 + // Bit CPU_CORE0_SW_RESET. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_RESET = 0x10000000 + // Position of CPU_CORE0_OCD_HALT_ON_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET_Pos = 0x1d + // Bit mask of CPU_CORE0_OCD_HALT_ON_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET_Msk = 0x20000000 + // Bit CPU_CORE0_OCD_HALT_ON_RESET. + LP_AON_CPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET = 0x20000000 + // Position of CPU_CORE0_STAT_VECTOR_SEL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL_Pos = 0x1e + // Bit mask of CPU_CORE0_STAT_VECTOR_SEL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL_Msk = 0x40000000 + // Bit CPU_CORE0_STAT_VECTOR_SEL. + LP_AON_CPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL = 0x40000000 + // Position of CPU_CORE0_DRESET_MASK field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_DRESET_MASK_Pos = 0x1f + // Bit mask of CPU_CORE0_DRESET_MASK field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_DRESET_MASK_Msk = 0x80000000 + // Bit CPU_CORE0_DRESET_MASK. + LP_AON_CPUCORE0_CFG_CPU_CORE0_DRESET_MASK = 0x80000000 + + // IO_MUX: need_des + // Position of RESET_DISABLE field. + LP_AON_IO_MUX_RESET_DISABLE_Pos = 0x1f + // Bit mask of RESET_DISABLE field. + LP_AON_IO_MUX_RESET_DISABLE_Msk = 0x80000000 + // Bit RESET_DISABLE. + LP_AON_IO_MUX_RESET_DISABLE = 0x80000000 + + // EXT_WAKEUP_CNTL: need_des + // Position of EXT_WAKEUP_STATUS field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_Pos = 0x0 + // Bit mask of EXT_WAKEUP_STATUS field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_Msk = 0xff + // Position of EXT_WAKEUP_STATUS_CLR field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR_Pos = 0xe + // Bit mask of EXT_WAKEUP_STATUS_CLR field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR_Msk = 0x4000 + // Bit EXT_WAKEUP_STATUS_CLR. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR = 0x4000 + // Position of EXT_WAKEUP_SEL field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_SEL_Pos = 0xf + // Bit mask of EXT_WAKEUP_SEL field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_SEL_Msk = 0x7f8000 + // Position of EXT_WAKEUP_LV field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_LV_Pos = 0x17 + // Bit mask of EXT_WAKEUP_LV field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_LV_Msk = 0x7f800000 + // Position of EXT_WAKEUP_FILTER field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER_Pos = 0x1f + // Bit mask of EXT_WAKEUP_FILTER field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER_Msk = 0x80000000 + // Bit EXT_WAKEUP_FILTER. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER = 0x80000000 + + // USB: need_des + // Position of RESET_DISABLE field. + LP_AON_USB_RESET_DISABLE_Pos = 0x1f + // Bit mask of RESET_DISABLE field. + LP_AON_USB_RESET_DISABLE_Msk = 0x80000000 + // Bit RESET_DISABLE. + LP_AON_USB_RESET_DISABLE = 0x80000000 + + // LPBUS: need_des + // Position of FAST_MEM_WPULSE field. + LP_AON_LPBUS_FAST_MEM_WPULSE_Pos = 0x10 + // Bit mask of FAST_MEM_WPULSE field. + LP_AON_LPBUS_FAST_MEM_WPULSE_Msk = 0x70000 + // Position of FAST_MEM_WA field. + LP_AON_LPBUS_FAST_MEM_WA_Pos = 0x13 + // Bit mask of FAST_MEM_WA field. + LP_AON_LPBUS_FAST_MEM_WA_Msk = 0x380000 + // Position of FAST_MEM_RA field. + LP_AON_LPBUS_FAST_MEM_RA_Pos = 0x16 + // Bit mask of FAST_MEM_RA field. + LP_AON_LPBUS_FAST_MEM_RA_Msk = 0xc00000 + // Position of FAST_MEM_MUX_FSM_IDLE field. + LP_AON_LPBUS_FAST_MEM_MUX_FSM_IDLE_Pos = 0x1c + // Bit mask of FAST_MEM_MUX_FSM_IDLE field. + LP_AON_LPBUS_FAST_MEM_MUX_FSM_IDLE_Msk = 0x10000000 + // Bit FAST_MEM_MUX_FSM_IDLE. + LP_AON_LPBUS_FAST_MEM_MUX_FSM_IDLE = 0x10000000 + // Position of FAST_MEM_MUX_SEL_STATUS field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_STATUS_Pos = 0x1d + // Bit mask of FAST_MEM_MUX_SEL_STATUS field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_STATUS_Msk = 0x20000000 + // Bit FAST_MEM_MUX_SEL_STATUS. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_STATUS = 0x20000000 + // Position of FAST_MEM_MUX_SEL_UPDATE field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_UPDATE_Pos = 0x1e + // Bit mask of FAST_MEM_MUX_SEL_UPDATE field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_UPDATE_Msk = 0x40000000 + // Bit FAST_MEM_MUX_SEL_UPDATE. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_UPDATE = 0x40000000 + // Position of FAST_MEM_MUX_SEL field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_Pos = 0x1f + // Bit mask of FAST_MEM_MUX_SEL field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_Msk = 0x80000000 + // Bit FAST_MEM_MUX_SEL. + LP_AON_LPBUS_FAST_MEM_MUX_SEL = 0x80000000 + + // SDIO_ACTIVE: need_des + // Position of SDIO_ACT_DNUM field. + LP_AON_SDIO_ACTIVE_SDIO_ACT_DNUM_Pos = 0x16 + // Bit mask of SDIO_ACT_DNUM field. + LP_AON_SDIO_ACTIVE_SDIO_ACT_DNUM_Msk = 0xffc00000 + + // LPCORE: need_des + // Position of ETM_WAKEUP_FLAG_CLR field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_Pos = 0x0 + // Bit mask of ETM_WAKEUP_FLAG_CLR field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_Msk = 0x1 + // Bit ETM_WAKEUP_FLAG_CLR. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR = 0x1 + // Position of ETM_WAKEUP_FLAG field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_Pos = 0x1 + // Bit mask of ETM_WAKEUP_FLAG field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_Msk = 0x2 + // Bit ETM_WAKEUP_FLAG. + LP_AON_LPCORE_ETM_WAKEUP_FLAG = 0x2 + // Position of DISABLE field. + LP_AON_LPCORE_DISABLE_Pos = 0x1f + // Bit mask of DISABLE field. + LP_AON_LPCORE_DISABLE_Msk = 0x80000000 + // Bit DISABLE. + LP_AON_LPCORE_DISABLE = 0x80000000 + + // SAR_CCT: need_des + // Position of SAR2_PWDET_CCT field. + LP_AON_SAR_CCT_SAR2_PWDET_CCT_Pos = 0x1d + // Bit mask of SAR2_PWDET_CCT field. + LP_AON_SAR_CCT_SAR2_PWDET_CCT_Msk = 0xe0000000 + + // DATE: need_des + // Position of DATE field. + LP_AON_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_AON_DATE_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_AON_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_AON_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_AON_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_APM: Low-power Access Permission Management Controller +const ( + // REGION_FILTER_EN: Region filter enable register + // Position of REGION_FILTER_EN field. + LP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Pos = 0x0 + // Bit mask of REGION_FILTER_EN field. + LP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Msk = 0xf + + // REGION0_ADDR_START: Region address register + // Position of REGION0_ADDR_START field. + LP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Pos = 0x0 + // Bit mask of REGION0_ADDR_START field. + LP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Msk = 0xffffffff + + // REGION0_ADDR_END: Region address register + // Position of REGION0_ADDR_END field. + LP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Pos = 0x0 + // Bit mask of REGION0_ADDR_END field. + LP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Msk = 0xffffffff + + // REGION0_PMS_ATTR: Region access authority attribute register + // Position of REGION0_R0_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION0_R0_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Msk = 0x1 + // Bit REGION0_R0_PMS_X. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X = 0x1 + // Position of REGION0_R0_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION0_R0_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Msk = 0x2 + // Bit REGION0_R0_PMS_W. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W = 0x2 + // Position of REGION0_R0_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION0_R0_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Msk = 0x4 + // Bit REGION0_R0_PMS_R. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R = 0x4 + // Position of REGION0_R1_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION0_R1_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Msk = 0x10 + // Bit REGION0_R1_PMS_X. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X = 0x10 + // Position of REGION0_R1_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION0_R1_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Msk = 0x20 + // Bit REGION0_R1_PMS_W. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W = 0x20 + // Position of REGION0_R1_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION0_R1_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Msk = 0x40 + // Bit REGION0_R1_PMS_R. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R = 0x40 + // Position of REGION0_R2_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION0_R2_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Msk = 0x100 + // Bit REGION0_R2_PMS_X. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X = 0x100 + // Position of REGION0_R2_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION0_R2_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Msk = 0x200 + // Bit REGION0_R2_PMS_W. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W = 0x200 + // Position of REGION0_R2_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Pos = 0xa + // Bit mask of REGION0_R2_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Msk = 0x400 + // Bit REGION0_R2_PMS_R. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R = 0x400 + + // REGION1_ADDR_START: Region address register + // Position of REGION1_ADDR_START field. + LP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Pos = 0x0 + // Bit mask of REGION1_ADDR_START field. + LP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Msk = 0xffffffff + + // REGION1_ADDR_END: Region address register + // Position of REGION1_ADDR_END field. + LP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Pos = 0x0 + // Bit mask of REGION1_ADDR_END field. + LP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Msk = 0xffffffff + + // REGION1_PMS_ATTR: Region access authority attribute register + // Position of REGION1_R0_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION1_R0_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Msk = 0x1 + // Bit REGION1_R0_PMS_X. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X = 0x1 + // Position of REGION1_R0_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION1_R0_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Msk = 0x2 + // Bit REGION1_R0_PMS_W. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W = 0x2 + // Position of REGION1_R0_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION1_R0_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Msk = 0x4 + // Bit REGION1_R0_PMS_R. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R = 0x4 + // Position of REGION1_R1_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION1_R1_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Msk = 0x10 + // Bit REGION1_R1_PMS_X. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X = 0x10 + // Position of REGION1_R1_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION1_R1_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Msk = 0x20 + // Bit REGION1_R1_PMS_W. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W = 0x20 + // Position of REGION1_R1_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION1_R1_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Msk = 0x40 + // Bit REGION1_R1_PMS_R. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R = 0x40 + // Position of REGION1_R2_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION1_R2_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Msk = 0x100 + // Bit REGION1_R2_PMS_X. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X = 0x100 + // Position of REGION1_R2_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION1_R2_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Msk = 0x200 + // Bit REGION1_R2_PMS_W. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W = 0x200 + // Position of REGION1_R2_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Pos = 0xa + // Bit mask of REGION1_R2_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Msk = 0x400 + // Bit REGION1_R2_PMS_R. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R = 0x400 + + // REGION2_ADDR_START: Region address register + // Position of REGION2_ADDR_START field. + LP_APM_REGION2_ADDR_START_REGION2_ADDR_START_Pos = 0x0 + // Bit mask of REGION2_ADDR_START field. + LP_APM_REGION2_ADDR_START_REGION2_ADDR_START_Msk = 0xffffffff + + // REGION2_ADDR_END: Region address register + // Position of REGION2_ADDR_END field. + LP_APM_REGION2_ADDR_END_REGION2_ADDR_END_Pos = 0x0 + // Bit mask of REGION2_ADDR_END field. + LP_APM_REGION2_ADDR_END_REGION2_ADDR_END_Msk = 0xffffffff + + // REGION2_PMS_ATTR: Region access authority attribute register + // Position of REGION2_R0_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION2_R0_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Msk = 0x1 + // Bit REGION2_R0_PMS_X. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X = 0x1 + // Position of REGION2_R0_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION2_R0_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Msk = 0x2 + // Bit REGION2_R0_PMS_W. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W = 0x2 + // Position of REGION2_R0_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION2_R0_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Msk = 0x4 + // Bit REGION2_R0_PMS_R. + LP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R = 0x4 + // Position of REGION2_R1_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION2_R1_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Msk = 0x10 + // Bit REGION2_R1_PMS_X. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X = 0x10 + // Position of REGION2_R1_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION2_R1_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Msk = 0x20 + // Bit REGION2_R1_PMS_W. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W = 0x20 + // Position of REGION2_R1_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION2_R1_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Msk = 0x40 + // Bit REGION2_R1_PMS_R. + LP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R = 0x40 + // Position of REGION2_R2_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION2_R2_PMS_X field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Msk = 0x100 + // Bit REGION2_R2_PMS_X. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X = 0x100 + // Position of REGION2_R2_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION2_R2_PMS_W field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Msk = 0x200 + // Bit REGION2_R2_PMS_W. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W = 0x200 + // Position of REGION2_R2_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Pos = 0xa + // Bit mask of REGION2_R2_PMS_R field. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Msk = 0x400 + // Bit REGION2_R2_PMS_R. + LP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R = 0x400 + + // REGION3_ADDR_START: Region address register + // Position of REGION3_ADDR_START field. + LP_APM_REGION3_ADDR_START_REGION3_ADDR_START_Pos = 0x0 + // Bit mask of REGION3_ADDR_START field. + LP_APM_REGION3_ADDR_START_REGION3_ADDR_START_Msk = 0xffffffff + + // REGION3_ADDR_END: Region address register + // Position of REGION3_ADDR_END field. + LP_APM_REGION3_ADDR_END_REGION3_ADDR_END_Pos = 0x0 + // Bit mask of REGION3_ADDR_END field. + LP_APM_REGION3_ADDR_END_REGION3_ADDR_END_Msk = 0xffffffff + + // REGION3_PMS_ATTR: Region access authority attribute register + // Position of REGION3_R0_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION3_R0_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Msk = 0x1 + // Bit REGION3_R0_PMS_X. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X = 0x1 + // Position of REGION3_R0_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION3_R0_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Msk = 0x2 + // Bit REGION3_R0_PMS_W. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W = 0x2 + // Position of REGION3_R0_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION3_R0_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Msk = 0x4 + // Bit REGION3_R0_PMS_R. + LP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R = 0x4 + // Position of REGION3_R1_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION3_R1_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Msk = 0x10 + // Bit REGION3_R1_PMS_X. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X = 0x10 + // Position of REGION3_R1_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION3_R1_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Msk = 0x20 + // Bit REGION3_R1_PMS_W. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W = 0x20 + // Position of REGION3_R1_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION3_R1_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Msk = 0x40 + // Bit REGION3_R1_PMS_R. + LP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R = 0x40 + // Position of REGION3_R2_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION3_R2_PMS_X field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Msk = 0x100 + // Bit REGION3_R2_PMS_X. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X = 0x100 + // Position of REGION3_R2_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION3_R2_PMS_W field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Msk = 0x200 + // Bit REGION3_R2_PMS_W. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W = 0x200 + // Position of REGION3_R2_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Pos = 0xa + // Bit mask of REGION3_R2_PMS_R field. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Msk = 0x400 + // Bit REGION3_R2_PMS_R. + LP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R = 0x400 + + // FUNC_CTRL: PMS function control register + // Position of M0_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Pos = 0x0 + // Bit mask of M0_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Msk = 0x1 + // Bit M0_PMS_FUNC_EN. + LP_APM_FUNC_CTRL_M0_PMS_FUNC_EN = 0x1 + // Position of M1_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M1_PMS_FUNC_EN_Pos = 0x1 + // Bit mask of M1_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M1_PMS_FUNC_EN_Msk = 0x2 + // Bit M1_PMS_FUNC_EN. + LP_APM_FUNC_CTRL_M1_PMS_FUNC_EN = 0x2 + + // M0_STATUS: M0 status register + // Position of M0_EXCEPTION_STATUS field. + LP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M0_EXCEPTION_STATUS field. + LP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Msk = 0x3 + + // M0_STATUS_CLR: M0 status clear register + // Position of M0_REGION_STATUS_CLR field. + LP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M0_REGION_STATUS_CLR field. + LP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Msk = 0x1 + // Bit M0_REGION_STATUS_CLR. + LP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR = 0x1 + + // M0_EXCEPTION_INFO0: M0 exception_info0 register + // Position of M0_EXCEPTION_REGION field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M0_EXCEPTION_REGION field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Msk = 0xf + // Position of M0_EXCEPTION_MODE field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M0_EXCEPTION_MODE field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Msk = 0x30000 + // Position of M0_EXCEPTION_ID field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M0_EXCEPTION_ID field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Msk = 0x7c0000 + + // M0_EXCEPTION_INFO1: M0 exception_info1 register + // Position of M0_EXCEPTION_ADDR field. + LP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M0_EXCEPTION_ADDR field. + LP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Msk = 0xffffffff + + // M1_STATUS: M1 status register + // Position of M1_EXCEPTION_STATUS field. + LP_APM_M1_STATUS_M1_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M1_EXCEPTION_STATUS field. + LP_APM_M1_STATUS_M1_EXCEPTION_STATUS_Msk = 0x3 + + // M1_STATUS_CLR: M1 status clear register + // Position of M1_REGION_STATUS_CLR field. + LP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M1_REGION_STATUS_CLR field. + LP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR_Msk = 0x1 + // Bit M1_REGION_STATUS_CLR. + LP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR = 0x1 + + // M1_EXCEPTION_INFO0: M1 exception_info0 register + // Position of M1_EXCEPTION_REGION field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M1_EXCEPTION_REGION field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_REGION_Msk = 0xf + // Position of M1_EXCEPTION_MODE field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M1_EXCEPTION_MODE field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_MODE_Msk = 0x30000 + // Position of M1_EXCEPTION_ID field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M1_EXCEPTION_ID field. + LP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_ID_Msk = 0x7c0000 + + // M1_EXCEPTION_INFO1: M1 exception_info1 register + // Position of M1_EXCEPTION_ADDR field. + LP_APM_M1_EXCEPTION_INFO1_M1_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M1_EXCEPTION_ADDR field. + LP_APM_M1_EXCEPTION_INFO1_M1_EXCEPTION_ADDR_Msk = 0xffffffff + + // INT_EN: APM interrupt enable register + // Position of M0_APM_INT_EN field. + LP_APM_INT_EN_M0_APM_INT_EN_Pos = 0x0 + // Bit mask of M0_APM_INT_EN field. + LP_APM_INT_EN_M0_APM_INT_EN_Msk = 0x1 + // Bit M0_APM_INT_EN. + LP_APM_INT_EN_M0_APM_INT_EN = 0x1 + // Position of M1_APM_INT_EN field. + LP_APM_INT_EN_M1_APM_INT_EN_Pos = 0x1 + // Bit mask of M1_APM_INT_EN field. + LP_APM_INT_EN_M1_APM_INT_EN_Msk = 0x2 + // Bit M1_APM_INT_EN. + LP_APM_INT_EN_M1_APM_INT_EN = 0x2 + + // CLOCK_GATE: clock gating register + // Position of CLK_EN field. + LP_APM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + LP_APM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + LP_APM_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + LP_APM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_APM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for LP_CLKRST: LP_CLKRST Peripheral +const ( + // LP_CLK_CONF: need_des + // Position of SLOW_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_SLOW_CLK_SEL_Pos = 0x0 + // Bit mask of SLOW_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_SLOW_CLK_SEL_Msk = 0x3 + // Position of FAST_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_FAST_CLK_SEL_Pos = 0x2 + // Bit mask of FAST_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_FAST_CLK_SEL_Msk = 0x4 + // Bit FAST_CLK_SEL. + LP_CLKRST_LP_CLK_CONF_FAST_CLK_SEL = 0x4 + // Position of LP_PERI_DIV_NUM field. + LP_CLKRST_LP_CLK_CONF_LP_PERI_DIV_NUM_Pos = 0x3 + // Bit mask of LP_PERI_DIV_NUM field. + LP_CLKRST_LP_CLK_CONF_LP_PERI_DIV_NUM_Msk = 0x7f8 + + // LP_CLK_PO_EN: need_des + // Position of AON_SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_SLOW_OEN_Pos = 0x0 + // Bit mask of AON_SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_SLOW_OEN_Msk = 0x1 + // Bit AON_SLOW_OEN. + LP_CLKRST_LP_CLK_PO_EN_AON_SLOW_OEN = 0x1 + // Position of AON_FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_FAST_OEN_Pos = 0x1 + // Bit mask of AON_FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_FAST_OEN_Msk = 0x2 + // Bit AON_FAST_OEN. + LP_CLKRST_LP_CLK_PO_EN_AON_FAST_OEN = 0x2 + // Position of SOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SOSC_OEN_Pos = 0x2 + // Bit mask of SOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SOSC_OEN_Msk = 0x4 + // Bit SOSC_OEN. + LP_CLKRST_LP_CLK_PO_EN_SOSC_OEN = 0x4 + // Position of FOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FOSC_OEN_Pos = 0x3 + // Bit mask of FOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FOSC_OEN_Msk = 0x8 + // Bit FOSC_OEN. + LP_CLKRST_LP_CLK_PO_EN_FOSC_OEN = 0x8 + // Position of OSC32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_OSC32K_OEN_Pos = 0x4 + // Bit mask of OSC32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_OSC32K_OEN_Msk = 0x10 + // Bit OSC32K_OEN. + LP_CLKRST_LP_CLK_PO_EN_OSC32K_OEN = 0x10 + // Position of XTAL32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_XTAL32K_OEN_Pos = 0x5 + // Bit mask of XTAL32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_XTAL32K_OEN_Msk = 0x20 + // Bit XTAL32K_OEN. + LP_CLKRST_LP_CLK_PO_EN_XTAL32K_OEN = 0x20 + // Position of CORE_EFUSE_OEN field. + LP_CLKRST_LP_CLK_PO_EN_CORE_EFUSE_OEN_Pos = 0x6 + // Bit mask of CORE_EFUSE_OEN field. + LP_CLKRST_LP_CLK_PO_EN_CORE_EFUSE_OEN_Msk = 0x40 + // Bit CORE_EFUSE_OEN. + LP_CLKRST_LP_CLK_PO_EN_CORE_EFUSE_OEN = 0x40 + // Position of SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SLOW_OEN_Pos = 0x7 + // Bit mask of SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SLOW_OEN_Msk = 0x80 + // Bit SLOW_OEN. + LP_CLKRST_LP_CLK_PO_EN_SLOW_OEN = 0x80 + // Position of FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FAST_OEN_Pos = 0x8 + // Bit mask of FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FAST_OEN_Msk = 0x100 + // Bit FAST_OEN. + LP_CLKRST_LP_CLK_PO_EN_FAST_OEN = 0x100 + // Position of RNG_OEN field. + LP_CLKRST_LP_CLK_PO_EN_RNG_OEN_Pos = 0x9 + // Bit mask of RNG_OEN field. + LP_CLKRST_LP_CLK_PO_EN_RNG_OEN_Msk = 0x200 + // Bit RNG_OEN. + LP_CLKRST_LP_CLK_PO_EN_RNG_OEN = 0x200 + // Position of LPBUS_OEN field. + LP_CLKRST_LP_CLK_PO_EN_LPBUS_OEN_Pos = 0xa + // Bit mask of LPBUS_OEN field. + LP_CLKRST_LP_CLK_PO_EN_LPBUS_OEN_Msk = 0x400 + // Bit LPBUS_OEN. + LP_CLKRST_LP_CLK_PO_EN_LPBUS_OEN = 0x400 + + // LP_CLK_EN: need_des + // Position of FAST_ORI_GATE field. + LP_CLKRST_LP_CLK_EN_FAST_ORI_GATE_Pos = 0x1f + // Bit mask of FAST_ORI_GATE field. + LP_CLKRST_LP_CLK_EN_FAST_ORI_GATE_Msk = 0x80000000 + // Bit FAST_ORI_GATE. + LP_CLKRST_LP_CLK_EN_FAST_ORI_GATE = 0x80000000 + + // LP_RST_EN: need_des + // Position of AON_EFUSE_CORE_RESET_EN field. + LP_CLKRST_LP_RST_EN_AON_EFUSE_CORE_RESET_EN_Pos = 0x1c + // Bit mask of AON_EFUSE_CORE_RESET_EN field. + LP_CLKRST_LP_RST_EN_AON_EFUSE_CORE_RESET_EN_Msk = 0x10000000 + // Bit AON_EFUSE_CORE_RESET_EN. + LP_CLKRST_LP_RST_EN_AON_EFUSE_CORE_RESET_EN = 0x10000000 + // Position of LP_TIMER_RESET_EN field. + LP_CLKRST_LP_RST_EN_LP_TIMER_RESET_EN_Pos = 0x1d + // Bit mask of LP_TIMER_RESET_EN field. + LP_CLKRST_LP_RST_EN_LP_TIMER_RESET_EN_Msk = 0x20000000 + // Bit LP_TIMER_RESET_EN. + LP_CLKRST_LP_RST_EN_LP_TIMER_RESET_EN = 0x20000000 + // Position of WDT_RESET_EN field. + LP_CLKRST_LP_RST_EN_WDT_RESET_EN_Pos = 0x1e + // Bit mask of WDT_RESET_EN field. + LP_CLKRST_LP_RST_EN_WDT_RESET_EN_Msk = 0x40000000 + // Bit WDT_RESET_EN. + LP_CLKRST_LP_RST_EN_WDT_RESET_EN = 0x40000000 + // Position of ANA_PERI_RESET_EN field. + LP_CLKRST_LP_RST_EN_ANA_PERI_RESET_EN_Pos = 0x1f + // Bit mask of ANA_PERI_RESET_EN field. + LP_CLKRST_LP_RST_EN_ANA_PERI_RESET_EN_Msk = 0x80000000 + // Bit ANA_PERI_RESET_EN. + LP_CLKRST_LP_RST_EN_ANA_PERI_RESET_EN = 0x80000000 + + // RESET_CAUSE: need_des + // Position of RESET_CAUSE field. + LP_CLKRST_RESET_CAUSE_RESET_CAUSE_Pos = 0x0 + // Bit mask of RESET_CAUSE field. + LP_CLKRST_RESET_CAUSE_RESET_CAUSE_Msk = 0x1f + // Position of CORE0_RESET_FLAG field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_Pos = 0x5 + // Bit mask of CORE0_RESET_FLAG field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_Msk = 0x20 + // Bit CORE0_RESET_FLAG. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG = 0x20 + // Position of CORE0_RESET_CAUSE_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_CAUSE_CLR_Pos = 0x1d + // Bit mask of CORE0_RESET_CAUSE_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_CAUSE_CLR_Msk = 0x20000000 + // Bit CORE0_RESET_CAUSE_CLR. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_CAUSE_CLR = 0x20000000 + // Position of CORE0_RESET_FLAG_SET field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_SET_Pos = 0x1e + // Bit mask of CORE0_RESET_FLAG_SET field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_SET_Msk = 0x40000000 + // Bit CORE0_RESET_FLAG_SET. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_SET = 0x40000000 + // Position of CORE0_RESET_FLAG_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_CLR_Pos = 0x1f + // Bit mask of CORE0_RESET_FLAG_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_CLR_Msk = 0x80000000 + // Bit CORE0_RESET_FLAG_CLR. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_CLR = 0x80000000 + + // CPU_RESET: need_des + // Position of RTC_WDT_CPU_RESET_LENGTH field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_LENGTH_Pos = 0x16 + // Bit mask of RTC_WDT_CPU_RESET_LENGTH field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_LENGTH_Msk = 0x1c00000 + // Position of RTC_WDT_CPU_RESET_EN field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_EN_Pos = 0x19 + // Bit mask of RTC_WDT_CPU_RESET_EN field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_EN_Msk = 0x2000000 + // Bit RTC_WDT_CPU_RESET_EN. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_EN = 0x2000000 + // Position of CPU_STALL_WAIT field. + LP_CLKRST_CPU_RESET_CPU_STALL_WAIT_Pos = 0x1a + // Bit mask of CPU_STALL_WAIT field. + LP_CLKRST_CPU_RESET_CPU_STALL_WAIT_Msk = 0x7c000000 + // Position of CPU_STALL_EN field. + LP_CLKRST_CPU_RESET_CPU_STALL_EN_Pos = 0x1f + // Bit mask of CPU_STALL_EN field. + LP_CLKRST_CPU_RESET_CPU_STALL_EN_Msk = 0x80000000 + // Bit CPU_STALL_EN. + LP_CLKRST_CPU_RESET_CPU_STALL_EN = 0x80000000 + + // FOSC_CNTL: need_des + // Position of FOSC_DFREQ field. + LP_CLKRST_FOSC_CNTL_FOSC_DFREQ_Pos = 0x16 + // Bit mask of FOSC_DFREQ field. + LP_CLKRST_FOSC_CNTL_FOSC_DFREQ_Msk = 0xffc00000 + + // RC32K_CNTL: need_des + // Position of RC32K_DFREQ field. + LP_CLKRST_RC32K_CNTL_RC32K_DFREQ_Pos = 0x16 + // Bit mask of RC32K_DFREQ field. + LP_CLKRST_RC32K_CNTL_RC32K_DFREQ_Msk = 0xffc00000 + + // CLK_TO_HP: need_des + // Position of ICG_HP_XTAL32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_XTAL32K_Pos = 0x1c + // Bit mask of ICG_HP_XTAL32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_XTAL32K_Msk = 0x10000000 + // Bit ICG_HP_XTAL32K. + LP_CLKRST_CLK_TO_HP_ICG_HP_XTAL32K = 0x10000000 + // Position of ICG_HP_SOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_SOSC_Pos = 0x1d + // Bit mask of ICG_HP_SOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_SOSC_Msk = 0x20000000 + // Bit ICG_HP_SOSC. + LP_CLKRST_CLK_TO_HP_ICG_HP_SOSC = 0x20000000 + // Position of ICG_HP_OSC32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_OSC32K_Pos = 0x1e + // Bit mask of ICG_HP_OSC32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_OSC32K_Msk = 0x40000000 + // Bit ICG_HP_OSC32K. + LP_CLKRST_CLK_TO_HP_ICG_HP_OSC32K = 0x40000000 + // Position of ICG_HP_FOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_FOSC_Pos = 0x1f + // Bit mask of ICG_HP_FOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_FOSC_Msk = 0x80000000 + // Bit ICG_HP_FOSC. + LP_CLKRST_CLK_TO_HP_ICG_HP_FOSC = 0x80000000 + + // LPMEM_FORCE: need_des + // Position of LPMEM_CLK_FORCE_ON field. + LP_CLKRST_LPMEM_FORCE_LPMEM_CLK_FORCE_ON_Pos = 0x1f + // Bit mask of LPMEM_CLK_FORCE_ON field. + LP_CLKRST_LPMEM_FORCE_LPMEM_CLK_FORCE_ON_Msk = 0x80000000 + // Bit LPMEM_CLK_FORCE_ON. + LP_CLKRST_LPMEM_FORCE_LPMEM_CLK_FORCE_ON = 0x80000000 + + // LPPERI: need_des + // Position of LP_I2C_CLK_SEL field. + LP_CLKRST_LPPERI_LP_I2C_CLK_SEL_Pos = 0x1e + // Bit mask of LP_I2C_CLK_SEL field. + LP_CLKRST_LPPERI_LP_I2C_CLK_SEL_Msk = 0x40000000 + // Bit LP_I2C_CLK_SEL. + LP_CLKRST_LPPERI_LP_I2C_CLK_SEL = 0x40000000 + // Position of LP_UART_CLK_SEL field. + LP_CLKRST_LPPERI_LP_UART_CLK_SEL_Pos = 0x1f + // Bit mask of LP_UART_CLK_SEL field. + LP_CLKRST_LPPERI_LP_UART_CLK_SEL_Msk = 0x80000000 + // Bit LP_UART_CLK_SEL. + LP_CLKRST_LPPERI_LP_UART_CLK_SEL = 0x80000000 + + // XTAL32K: need_des + // Position of DRES_XTAL32K field. + LP_CLKRST_XTAL32K_DRES_XTAL32K_Pos = 0x16 + // Bit mask of DRES_XTAL32K field. + LP_CLKRST_XTAL32K_DRES_XTAL32K_Msk = 0x1c00000 + // Position of DGM_XTAL32K field. + LP_CLKRST_XTAL32K_DGM_XTAL32K_Pos = 0x19 + // Bit mask of DGM_XTAL32K field. + LP_CLKRST_XTAL32K_DGM_XTAL32K_Msk = 0xe000000 + // Position of DBUF_XTAL32K field. + LP_CLKRST_XTAL32K_DBUF_XTAL32K_Pos = 0x1c + // Bit mask of DBUF_XTAL32K field. + LP_CLKRST_XTAL32K_DBUF_XTAL32K_Msk = 0x10000000 + // Bit DBUF_XTAL32K. + LP_CLKRST_XTAL32K_DBUF_XTAL32K = 0x10000000 + // Position of DAC_XTAL32K field. + LP_CLKRST_XTAL32K_DAC_XTAL32K_Pos = 0x1d + // Bit mask of DAC_XTAL32K field. + LP_CLKRST_XTAL32K_DAC_XTAL32K_Msk = 0xe0000000 + + // DATE: need_des + // Position of CLKRST_DATE field. + LP_CLKRST_DATE_CLKRST_DATE_Pos = 0x0 + // Bit mask of CLKRST_DATE field. + LP_CLKRST_DATE_CLKRST_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_CLKRST_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_CLKRST_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_CLKRST_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_I2C_ANA_MST: LP_I2C_ANA_MST Peripheral +const ( + // I2C0_CTRL: need_des + // Position of LP_I2C_ANA_MAST_I2C0_CTRL field. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_CTRL_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C0_CTRL field. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_CTRL_Msk = 0x1ffffff + // Position of LP_I2C_ANA_MAST_I2C0_BUSY field. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY_Pos = 0x19 + // Bit mask of LP_I2C_ANA_MAST_I2C0_BUSY field. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY_Msk = 0x2000000 + // Bit LP_I2C_ANA_MAST_I2C0_BUSY. + LP_I2C_ANA_MST_I2C0_CTRL_LP_I2C_ANA_MAST_I2C0_BUSY = 0x2000000 + + // I2C0_CONF: need_des + // Position of LP_I2C_ANA_MAST_I2C0_CONF field. + LP_I2C_ANA_MST_I2C0_CONF_LP_I2C_ANA_MAST_I2C0_CONF_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C0_CONF field. + LP_I2C_ANA_MST_I2C0_CONF_LP_I2C_ANA_MAST_I2C0_CONF_Msk = 0xffffff + // Position of LP_I2C_ANA_MAST_I2C0_STATUS field. + LP_I2C_ANA_MST_I2C0_CONF_LP_I2C_ANA_MAST_I2C0_STATUS_Pos = 0x18 + // Bit mask of LP_I2C_ANA_MAST_I2C0_STATUS field. + LP_I2C_ANA_MST_I2C0_CONF_LP_I2C_ANA_MAST_I2C0_STATUS_Msk = 0xff000000 + + // I2C0_DATA: need_des + // Position of LP_I2C_ANA_MAST_I2C0_RDATA field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C0_RDATA_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C0_RDATA field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C0_RDATA_Msk = 0xff + // Position of LP_I2C_ANA_MAST_I2C0_CLK_SEL field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C0_CLK_SEL_Pos = 0x8 + // Bit mask of LP_I2C_ANA_MAST_I2C0_CLK_SEL field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C0_CLK_SEL_Msk = 0x700 + // Position of LP_I2C_ANA_MAST_I2C_MST_SEL field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL_Pos = 0xb + // Bit mask of LP_I2C_ANA_MAST_I2C_MST_SEL field. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL_Msk = 0x800 + // Bit LP_I2C_ANA_MAST_I2C_MST_SEL. + LP_I2C_ANA_MST_I2C0_DATA_LP_I2C_ANA_MAST_I2C_MST_SEL = 0x800 + + // ANA_CONF1: need_des + // Position of LP_I2C_ANA_MAST_ANA_CONF1 field. + LP_I2C_ANA_MST_ANA_CONF1_LP_I2C_ANA_MAST_ANA_CONF1_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_ANA_CONF1 field. + LP_I2C_ANA_MST_ANA_CONF1_LP_I2C_ANA_MAST_ANA_CONF1_Msk = 0xffffff + + // NOUSE: need_des + // Position of LP_I2C_ANA_MAST_I2C_MST_NOUSE field. + LP_I2C_ANA_MST_NOUSE_LP_I2C_ANA_MAST_I2C_MST_NOUSE_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C_MST_NOUSE field. + LP_I2C_ANA_MST_NOUSE_LP_I2C_ANA_MAST_I2C_MST_NOUSE_Msk = 0xffffffff + + // DEVICE_EN: need_des + // Position of LP_I2C_ANA_MAST_I2C_DEVICE_EN field. + LP_I2C_ANA_MST_DEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C_DEVICE_EN field. + LP_I2C_ANA_MST_DEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN_Msk = 0xfff + + // DATE: need_des + // Position of LP_I2C_ANA_MAST_I2C_MAT_DATE field. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_DATE_Pos = 0x0 + // Bit mask of LP_I2C_ANA_MAST_I2C_MAT_DATE field. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_DATE_Msk = 0xfffffff + // Position of LP_I2C_ANA_MAST_I2C_MAT_CLK_EN field. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN_Pos = 0x1c + // Bit mask of LP_I2C_ANA_MAST_I2C_MAT_CLK_EN field. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN_Msk = 0x10000000 + // Bit LP_I2C_ANA_MAST_I2C_MAT_CLK_EN. + LP_I2C_ANA_MST_DATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN = 0x10000000 +) + +// Constants for LP_IO_MUX: Low-power Input/Output Multiplexer +const ( + // OUT_DATA: need des + // Position of LP_GPIO_OUT_DATA field. + LP_IO_OUT_DATA_LP_GPIO_OUT_DATA_Pos = 0x0 + // Bit mask of LP_GPIO_OUT_DATA field. + LP_IO_OUT_DATA_LP_GPIO_OUT_DATA_Msk = 0xff + + // OUT_DATA_W1TS: need des + // Position of LP_GPIO_OUT_DATA_W1TS field. + LP_IO_OUT_DATA_W1TS_LP_GPIO_OUT_DATA_W1TS_Pos = 0x0 + // Bit mask of LP_GPIO_OUT_DATA_W1TS field. + LP_IO_OUT_DATA_W1TS_LP_GPIO_OUT_DATA_W1TS_Msk = 0xff + + // OUT_DATA_W1TC: need des + // Position of LP_GPIO_OUT_DATA_W1TC field. + LP_IO_OUT_DATA_W1TC_LP_GPIO_OUT_DATA_W1TC_Pos = 0x0 + // Bit mask of LP_GPIO_OUT_DATA_W1TC field. + LP_IO_OUT_DATA_W1TC_LP_GPIO_OUT_DATA_W1TC_Msk = 0xff + + // OUT_ENABLE: need des + // Position of LP_GPIO_ENABLE field. + LP_IO_OUT_ENABLE_LP_GPIO_ENABLE_Pos = 0x0 + // Bit mask of LP_GPIO_ENABLE field. + LP_IO_OUT_ENABLE_LP_GPIO_ENABLE_Msk = 0xff + + // OUT_ENABLE_W1TS: need des + // Position of LP_GPIO_ENABLE_W1TS field. + LP_IO_OUT_ENABLE_W1TS_LP_GPIO_ENABLE_W1TS_Pos = 0x0 + // Bit mask of LP_GPIO_ENABLE_W1TS field. + LP_IO_OUT_ENABLE_W1TS_LP_GPIO_ENABLE_W1TS_Msk = 0xff + + // OUT_ENABLE_W1TC: need des + // Position of LP_GPIO_ENABLE_W1TC field. + LP_IO_OUT_ENABLE_W1TC_LP_GPIO_ENABLE_W1TC_Pos = 0x0 + // Bit mask of LP_GPIO_ENABLE_W1TC field. + LP_IO_OUT_ENABLE_W1TC_LP_GPIO_ENABLE_W1TC_Msk = 0xff + + // STATUS: need des + // Position of LP_GPIO_STATUS_INTERRUPT field. + LP_IO_STATUS_LP_GPIO_STATUS_INTERRUPT_Pos = 0x0 + // Bit mask of LP_GPIO_STATUS_INTERRUPT field. + LP_IO_STATUS_LP_GPIO_STATUS_INTERRUPT_Msk = 0xff + + // STATUS_W1TS: need des + // Position of LP_GPIO_STATUS_W1TS field. + LP_IO_STATUS_W1TS_LP_GPIO_STATUS_W1TS_Pos = 0x0 + // Bit mask of LP_GPIO_STATUS_W1TS field. + LP_IO_STATUS_W1TS_LP_GPIO_STATUS_W1TS_Msk = 0xff + + // STATUS_W1TC: need des + // Position of LP_GPIO_STATUS_W1TC field. + LP_IO_STATUS_W1TC_LP_GPIO_STATUS_W1TC_Pos = 0x0 + // Bit mask of LP_GPIO_STATUS_W1TC field. + LP_IO_STATUS_W1TC_LP_GPIO_STATUS_W1TC_Msk = 0xff + + // IN: need des + // Position of LP_GPIO_IN_DATA_NEXT field. + LP_IO_IN_LP_GPIO_IN_DATA_NEXT_Pos = 0x0 + // Bit mask of LP_GPIO_IN_DATA_NEXT field. + LP_IO_IN_LP_GPIO_IN_DATA_NEXT_Msk = 0xff + + // PIN0: need des + // Position of LP_GPIO0_SYNC_BYPASS field. + LP_IO_PIN0_LP_GPIO0_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO0_SYNC_BYPASS field. + LP_IO_PIN0_LP_GPIO0_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO0_PAD_DRIVER field. + LP_IO_PIN0_LP_GPIO0_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO0_PAD_DRIVER field. + LP_IO_PIN0_LP_GPIO0_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO0_PAD_DRIVER. + LP_IO_PIN0_LP_GPIO0_PAD_DRIVER = 0x4 + // Position of LP_GPIO0_EDGE_WAKEUP_CLR field. + LP_IO_PIN0_LP_GPIO0_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO0_EDGE_WAKEUP_CLR field. + LP_IO_PIN0_LP_GPIO0_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO0_EDGE_WAKEUP_CLR. + LP_IO_PIN0_LP_GPIO0_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO0_INT_TYPE field. + LP_IO_PIN0_LP_GPIO0_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO0_INT_TYPE field. + LP_IO_PIN0_LP_GPIO0_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO0_WAKEUP_ENABLE field. + LP_IO_PIN0_LP_GPIO0_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO0_WAKEUP_ENABLE field. + LP_IO_PIN0_LP_GPIO0_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO0_WAKEUP_ENABLE. + LP_IO_PIN0_LP_GPIO0_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO0_FILTER_EN field. + LP_IO_PIN0_LP_GPIO0_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO0_FILTER_EN field. + LP_IO_PIN0_LP_GPIO0_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO0_FILTER_EN. + LP_IO_PIN0_LP_GPIO0_FILTER_EN = 0x800 + + // PIN1: need des + // Position of LP_GPIO1_SYNC_BYPASS field. + LP_IO_PIN1_LP_GPIO1_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO1_SYNC_BYPASS field. + LP_IO_PIN1_LP_GPIO1_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO1_PAD_DRIVER field. + LP_IO_PIN1_LP_GPIO1_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO1_PAD_DRIVER field. + LP_IO_PIN1_LP_GPIO1_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO1_PAD_DRIVER. + LP_IO_PIN1_LP_GPIO1_PAD_DRIVER = 0x4 + // Position of LP_GPIO1_EDGE_WAKEUP_CLR field. + LP_IO_PIN1_LP_GPIO1_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO1_EDGE_WAKEUP_CLR field. + LP_IO_PIN1_LP_GPIO1_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO1_EDGE_WAKEUP_CLR. + LP_IO_PIN1_LP_GPIO1_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO1_INT_TYPE field. + LP_IO_PIN1_LP_GPIO1_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO1_INT_TYPE field. + LP_IO_PIN1_LP_GPIO1_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO1_WAKEUP_ENABLE field. + LP_IO_PIN1_LP_GPIO1_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO1_WAKEUP_ENABLE field. + LP_IO_PIN1_LP_GPIO1_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO1_WAKEUP_ENABLE. + LP_IO_PIN1_LP_GPIO1_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO1_FILTER_EN field. + LP_IO_PIN1_LP_GPIO1_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO1_FILTER_EN field. + LP_IO_PIN1_LP_GPIO1_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO1_FILTER_EN. + LP_IO_PIN1_LP_GPIO1_FILTER_EN = 0x800 + + // PIN2: need des + // Position of LP_GPIO2_SYNC_BYPASS field. + LP_IO_PIN2_LP_GPIO2_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO2_SYNC_BYPASS field. + LP_IO_PIN2_LP_GPIO2_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO2_PAD_DRIVER field. + LP_IO_PIN2_LP_GPIO2_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO2_PAD_DRIVER field. + LP_IO_PIN2_LP_GPIO2_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO2_PAD_DRIVER. + LP_IO_PIN2_LP_GPIO2_PAD_DRIVER = 0x4 + // Position of LP_GPIO2_EDGE_WAKEUP_CLR field. + LP_IO_PIN2_LP_GPIO2_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO2_EDGE_WAKEUP_CLR field. + LP_IO_PIN2_LP_GPIO2_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO2_EDGE_WAKEUP_CLR. + LP_IO_PIN2_LP_GPIO2_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO2_INT_TYPE field. + LP_IO_PIN2_LP_GPIO2_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO2_INT_TYPE field. + LP_IO_PIN2_LP_GPIO2_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO2_WAKEUP_ENABLE field. + LP_IO_PIN2_LP_GPIO2_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO2_WAKEUP_ENABLE field. + LP_IO_PIN2_LP_GPIO2_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO2_WAKEUP_ENABLE. + LP_IO_PIN2_LP_GPIO2_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO2_FILTER_EN field. + LP_IO_PIN2_LP_GPIO2_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO2_FILTER_EN field. + LP_IO_PIN2_LP_GPIO2_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO2_FILTER_EN. + LP_IO_PIN2_LP_GPIO2_FILTER_EN = 0x800 + + // PIN3: need des + // Position of LP_GPIO3_SYNC_BYPASS field. + LP_IO_PIN3_LP_GPIO3_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO3_SYNC_BYPASS field. + LP_IO_PIN3_LP_GPIO3_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO3_PAD_DRIVER field. + LP_IO_PIN3_LP_GPIO3_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO3_PAD_DRIVER field. + LP_IO_PIN3_LP_GPIO3_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO3_PAD_DRIVER. + LP_IO_PIN3_LP_GPIO3_PAD_DRIVER = 0x4 + // Position of LP_GPIO3_EDGE_WAKEUP_CLR field. + LP_IO_PIN3_LP_GPIO3_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO3_EDGE_WAKEUP_CLR field. + LP_IO_PIN3_LP_GPIO3_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO3_EDGE_WAKEUP_CLR. + LP_IO_PIN3_LP_GPIO3_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO3_INT_TYPE field. + LP_IO_PIN3_LP_GPIO3_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO3_INT_TYPE field. + LP_IO_PIN3_LP_GPIO3_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO3_WAKEUP_ENABLE field. + LP_IO_PIN3_LP_GPIO3_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO3_WAKEUP_ENABLE field. + LP_IO_PIN3_LP_GPIO3_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO3_WAKEUP_ENABLE. + LP_IO_PIN3_LP_GPIO3_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO3_FILTER_EN field. + LP_IO_PIN3_LP_GPIO3_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO3_FILTER_EN field. + LP_IO_PIN3_LP_GPIO3_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO3_FILTER_EN. + LP_IO_PIN3_LP_GPIO3_FILTER_EN = 0x800 + + // PIN4: need des + // Position of LP_GPIO4_SYNC_BYPASS field. + LP_IO_PIN4_LP_GPIO4_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO4_SYNC_BYPASS field. + LP_IO_PIN4_LP_GPIO4_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO4_PAD_DRIVER field. + LP_IO_PIN4_LP_GPIO4_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO4_PAD_DRIVER field. + LP_IO_PIN4_LP_GPIO4_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO4_PAD_DRIVER. + LP_IO_PIN4_LP_GPIO4_PAD_DRIVER = 0x4 + // Position of LP_GPIO4_EDGE_WAKEUP_CLR field. + LP_IO_PIN4_LP_GPIO4_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO4_EDGE_WAKEUP_CLR field. + LP_IO_PIN4_LP_GPIO4_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO4_EDGE_WAKEUP_CLR. + LP_IO_PIN4_LP_GPIO4_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO4_INT_TYPE field. + LP_IO_PIN4_LP_GPIO4_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO4_INT_TYPE field. + LP_IO_PIN4_LP_GPIO4_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO4_WAKEUP_ENABLE field. + LP_IO_PIN4_LP_GPIO4_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO4_WAKEUP_ENABLE field. + LP_IO_PIN4_LP_GPIO4_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO4_WAKEUP_ENABLE. + LP_IO_PIN4_LP_GPIO4_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO4_FILTER_EN field. + LP_IO_PIN4_LP_GPIO4_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO4_FILTER_EN field. + LP_IO_PIN4_LP_GPIO4_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO4_FILTER_EN. + LP_IO_PIN4_LP_GPIO4_FILTER_EN = 0x800 + + // PIN5: need des + // Position of LP_GPIO5_SYNC_BYPASS field. + LP_IO_PIN5_LP_GPIO5_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO5_SYNC_BYPASS field. + LP_IO_PIN5_LP_GPIO5_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO5_PAD_DRIVER field. + LP_IO_PIN5_LP_GPIO5_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO5_PAD_DRIVER field. + LP_IO_PIN5_LP_GPIO5_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO5_PAD_DRIVER. + LP_IO_PIN5_LP_GPIO5_PAD_DRIVER = 0x4 + // Position of LP_GPIO5_EDGE_WAKEUP_CLR field. + LP_IO_PIN5_LP_GPIO5_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO5_EDGE_WAKEUP_CLR field. + LP_IO_PIN5_LP_GPIO5_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO5_EDGE_WAKEUP_CLR. + LP_IO_PIN5_LP_GPIO5_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO5_INT_TYPE field. + LP_IO_PIN5_LP_GPIO5_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO5_INT_TYPE field. + LP_IO_PIN5_LP_GPIO5_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO5_WAKEUP_ENABLE field. + LP_IO_PIN5_LP_GPIO5_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO5_WAKEUP_ENABLE field. + LP_IO_PIN5_LP_GPIO5_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO5_WAKEUP_ENABLE. + LP_IO_PIN5_LP_GPIO5_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO5_FILTER_EN field. + LP_IO_PIN5_LP_GPIO5_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO5_FILTER_EN field. + LP_IO_PIN5_LP_GPIO5_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO5_FILTER_EN. + LP_IO_PIN5_LP_GPIO5_FILTER_EN = 0x800 + + // PIN6: need des + // Position of LP_GPIO6_SYNC_BYPASS field. + LP_IO_PIN6_LP_GPIO6_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO6_SYNC_BYPASS field. + LP_IO_PIN6_LP_GPIO6_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO6_PAD_DRIVER field. + LP_IO_PIN6_LP_GPIO6_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO6_PAD_DRIVER field. + LP_IO_PIN6_LP_GPIO6_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO6_PAD_DRIVER. + LP_IO_PIN6_LP_GPIO6_PAD_DRIVER = 0x4 + // Position of LP_GPIO6_EDGE_WAKEUP_CLR field. + LP_IO_PIN6_LP_GPIO6_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO6_EDGE_WAKEUP_CLR field. + LP_IO_PIN6_LP_GPIO6_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO6_EDGE_WAKEUP_CLR. + LP_IO_PIN6_LP_GPIO6_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO6_INT_TYPE field. + LP_IO_PIN6_LP_GPIO6_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO6_INT_TYPE field. + LP_IO_PIN6_LP_GPIO6_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO6_WAKEUP_ENABLE field. + LP_IO_PIN6_LP_GPIO6_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO6_WAKEUP_ENABLE field. + LP_IO_PIN6_LP_GPIO6_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO6_WAKEUP_ENABLE. + LP_IO_PIN6_LP_GPIO6_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO6_FILTER_EN field. + LP_IO_PIN6_LP_GPIO6_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO6_FILTER_EN field. + LP_IO_PIN6_LP_GPIO6_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO6_FILTER_EN. + LP_IO_PIN6_LP_GPIO6_FILTER_EN = 0x800 + + // PIN7: need des + // Position of LP_GPIO7_SYNC_BYPASS field. + LP_IO_PIN7_LP_GPIO7_SYNC_BYPASS_Pos = 0x0 + // Bit mask of LP_GPIO7_SYNC_BYPASS field. + LP_IO_PIN7_LP_GPIO7_SYNC_BYPASS_Msk = 0x3 + // Position of LP_GPIO7_PAD_DRIVER field. + LP_IO_PIN7_LP_GPIO7_PAD_DRIVER_Pos = 0x2 + // Bit mask of LP_GPIO7_PAD_DRIVER field. + LP_IO_PIN7_LP_GPIO7_PAD_DRIVER_Msk = 0x4 + // Bit LP_GPIO7_PAD_DRIVER. + LP_IO_PIN7_LP_GPIO7_PAD_DRIVER = 0x4 + // Position of LP_GPIO7_EDGE_WAKEUP_CLR field. + LP_IO_PIN7_LP_GPIO7_EDGE_WAKEUP_CLR_Pos = 0x3 + // Bit mask of LP_GPIO7_EDGE_WAKEUP_CLR field. + LP_IO_PIN7_LP_GPIO7_EDGE_WAKEUP_CLR_Msk = 0x8 + // Bit LP_GPIO7_EDGE_WAKEUP_CLR. + LP_IO_PIN7_LP_GPIO7_EDGE_WAKEUP_CLR = 0x8 + // Position of LP_GPIO7_INT_TYPE field. + LP_IO_PIN7_LP_GPIO7_INT_TYPE_Pos = 0x7 + // Bit mask of LP_GPIO7_INT_TYPE field. + LP_IO_PIN7_LP_GPIO7_INT_TYPE_Msk = 0x380 + // Position of LP_GPIO7_WAKEUP_ENABLE field. + LP_IO_PIN7_LP_GPIO7_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of LP_GPIO7_WAKEUP_ENABLE field. + LP_IO_PIN7_LP_GPIO7_WAKEUP_ENABLE_Msk = 0x400 + // Bit LP_GPIO7_WAKEUP_ENABLE. + LP_IO_PIN7_LP_GPIO7_WAKEUP_ENABLE = 0x400 + // Position of LP_GPIO7_FILTER_EN field. + LP_IO_PIN7_LP_GPIO7_FILTER_EN_Pos = 0xb + // Bit mask of LP_GPIO7_FILTER_EN field. + LP_IO_PIN7_LP_GPIO7_FILTER_EN_Msk = 0x800 + // Bit LP_GPIO7_FILTER_EN. + LP_IO_PIN7_LP_GPIO7_FILTER_EN = 0x800 + + // GPIO0: need des + // Position of LP_GPIO0_MCU_OE field. + LP_IO_GPIO0_LP_GPIO0_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO0_MCU_OE field. + LP_IO_GPIO0_LP_GPIO0_MCU_OE_Msk = 0x1 + // Bit LP_GPIO0_MCU_OE. + LP_IO_GPIO0_LP_GPIO0_MCU_OE = 0x1 + // Position of LP_GPIO0_SLP_SEL field. + LP_IO_GPIO0_LP_GPIO0_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO0_SLP_SEL field. + LP_IO_GPIO0_LP_GPIO0_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO0_SLP_SEL. + LP_IO_GPIO0_LP_GPIO0_SLP_SEL = 0x2 + // Position of LP_GPIO0_MCU_WPD field. + LP_IO_GPIO0_LP_GPIO0_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO0_MCU_WPD field. + LP_IO_GPIO0_LP_GPIO0_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO0_MCU_WPD. + LP_IO_GPIO0_LP_GPIO0_MCU_WPD = 0x4 + // Position of LP_GPIO0_MCU_WPU field. + LP_IO_GPIO0_LP_GPIO0_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO0_MCU_WPU field. + LP_IO_GPIO0_LP_GPIO0_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO0_MCU_WPU. + LP_IO_GPIO0_LP_GPIO0_MCU_WPU = 0x8 + // Position of LP_GPIO0_MCU_IE field. + LP_IO_GPIO0_LP_GPIO0_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO0_MCU_IE field. + LP_IO_GPIO0_LP_GPIO0_MCU_IE_Msk = 0x10 + // Bit LP_GPIO0_MCU_IE. + LP_IO_GPIO0_LP_GPIO0_MCU_IE = 0x10 + // Position of LP_GPIO0_MCU_DRV field. + LP_IO_GPIO0_LP_GPIO0_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO0_MCU_DRV field. + LP_IO_GPIO0_LP_GPIO0_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO0_FUN_WPD field. + LP_IO_GPIO0_LP_GPIO0_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO0_FUN_WPD field. + LP_IO_GPIO0_LP_GPIO0_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO0_FUN_WPD. + LP_IO_GPIO0_LP_GPIO0_FUN_WPD = 0x80 + // Position of LP_GPIO0_FUN_WPU field. + LP_IO_GPIO0_LP_GPIO0_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO0_FUN_WPU field. + LP_IO_GPIO0_LP_GPIO0_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO0_FUN_WPU. + LP_IO_GPIO0_LP_GPIO0_FUN_WPU = 0x100 + // Position of LP_GPIO0_FUN_IE field. + LP_IO_GPIO0_LP_GPIO0_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO0_FUN_IE field. + LP_IO_GPIO0_LP_GPIO0_FUN_IE_Msk = 0x200 + // Bit LP_GPIO0_FUN_IE. + LP_IO_GPIO0_LP_GPIO0_FUN_IE = 0x200 + // Position of LP_GPIO0_FUN_DRV field. + LP_IO_GPIO0_LP_GPIO0_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO0_FUN_DRV field. + LP_IO_GPIO0_LP_GPIO0_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO0_MCU_SEL field. + LP_IO_GPIO0_LP_GPIO0_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO0_MCU_SEL field. + LP_IO_GPIO0_LP_GPIO0_MCU_SEL_Msk = 0x7000 + + // GPIO1: need des + // Position of LP_GPIO1_MCU_OE field. + LP_IO_GPIO1_LP_GPIO1_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO1_MCU_OE field. + LP_IO_GPIO1_LP_GPIO1_MCU_OE_Msk = 0x1 + // Bit LP_GPIO1_MCU_OE. + LP_IO_GPIO1_LP_GPIO1_MCU_OE = 0x1 + // Position of LP_GPIO1_SLP_SEL field. + LP_IO_GPIO1_LP_GPIO1_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO1_SLP_SEL field. + LP_IO_GPIO1_LP_GPIO1_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO1_SLP_SEL. + LP_IO_GPIO1_LP_GPIO1_SLP_SEL = 0x2 + // Position of LP_GPIO1_MCU_WPD field. + LP_IO_GPIO1_LP_GPIO1_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO1_MCU_WPD field. + LP_IO_GPIO1_LP_GPIO1_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO1_MCU_WPD. + LP_IO_GPIO1_LP_GPIO1_MCU_WPD = 0x4 + // Position of LP_GPIO1_MCU_WPU field. + LP_IO_GPIO1_LP_GPIO1_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO1_MCU_WPU field. + LP_IO_GPIO1_LP_GPIO1_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO1_MCU_WPU. + LP_IO_GPIO1_LP_GPIO1_MCU_WPU = 0x8 + // Position of LP_GPIO1_MCU_IE field. + LP_IO_GPIO1_LP_GPIO1_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO1_MCU_IE field. + LP_IO_GPIO1_LP_GPIO1_MCU_IE_Msk = 0x10 + // Bit LP_GPIO1_MCU_IE. + LP_IO_GPIO1_LP_GPIO1_MCU_IE = 0x10 + // Position of LP_GPIO1_MCU_DRV field. + LP_IO_GPIO1_LP_GPIO1_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO1_MCU_DRV field. + LP_IO_GPIO1_LP_GPIO1_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO1_FUN_WPD field. + LP_IO_GPIO1_LP_GPIO1_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO1_FUN_WPD field. + LP_IO_GPIO1_LP_GPIO1_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO1_FUN_WPD. + LP_IO_GPIO1_LP_GPIO1_FUN_WPD = 0x80 + // Position of LP_GPIO1_FUN_WPU field. + LP_IO_GPIO1_LP_GPIO1_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO1_FUN_WPU field. + LP_IO_GPIO1_LP_GPIO1_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO1_FUN_WPU. + LP_IO_GPIO1_LP_GPIO1_FUN_WPU = 0x100 + // Position of LP_GPIO1_FUN_IE field. + LP_IO_GPIO1_LP_GPIO1_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO1_FUN_IE field. + LP_IO_GPIO1_LP_GPIO1_FUN_IE_Msk = 0x200 + // Bit LP_GPIO1_FUN_IE. + LP_IO_GPIO1_LP_GPIO1_FUN_IE = 0x200 + // Position of LP_GPIO1_FUN_DRV field. + LP_IO_GPIO1_LP_GPIO1_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO1_FUN_DRV field. + LP_IO_GPIO1_LP_GPIO1_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO1_MCU_SEL field. + LP_IO_GPIO1_LP_GPIO1_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO1_MCU_SEL field. + LP_IO_GPIO1_LP_GPIO1_MCU_SEL_Msk = 0x7000 + + // GPIO2: need des + // Position of LP_GPIO2_MCU_OE field. + LP_IO_GPIO2_LP_GPIO2_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO2_MCU_OE field. + LP_IO_GPIO2_LP_GPIO2_MCU_OE_Msk = 0x1 + // Bit LP_GPIO2_MCU_OE. + LP_IO_GPIO2_LP_GPIO2_MCU_OE = 0x1 + // Position of LP_GPIO2_SLP_SEL field. + LP_IO_GPIO2_LP_GPIO2_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO2_SLP_SEL field. + LP_IO_GPIO2_LP_GPIO2_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO2_SLP_SEL. + LP_IO_GPIO2_LP_GPIO2_SLP_SEL = 0x2 + // Position of LP_GPIO2_MCU_WPD field. + LP_IO_GPIO2_LP_GPIO2_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO2_MCU_WPD field. + LP_IO_GPIO2_LP_GPIO2_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO2_MCU_WPD. + LP_IO_GPIO2_LP_GPIO2_MCU_WPD = 0x4 + // Position of LP_GPIO2_MCU_WPU field. + LP_IO_GPIO2_LP_GPIO2_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO2_MCU_WPU field. + LP_IO_GPIO2_LP_GPIO2_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO2_MCU_WPU. + LP_IO_GPIO2_LP_GPIO2_MCU_WPU = 0x8 + // Position of LP_GPIO2_MCU_IE field. + LP_IO_GPIO2_LP_GPIO2_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO2_MCU_IE field. + LP_IO_GPIO2_LP_GPIO2_MCU_IE_Msk = 0x10 + // Bit LP_GPIO2_MCU_IE. + LP_IO_GPIO2_LP_GPIO2_MCU_IE = 0x10 + // Position of LP_GPIO2_MCU_DRV field. + LP_IO_GPIO2_LP_GPIO2_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO2_MCU_DRV field. + LP_IO_GPIO2_LP_GPIO2_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO2_FUN_WPD field. + LP_IO_GPIO2_LP_GPIO2_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO2_FUN_WPD field. + LP_IO_GPIO2_LP_GPIO2_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO2_FUN_WPD. + LP_IO_GPIO2_LP_GPIO2_FUN_WPD = 0x80 + // Position of LP_GPIO2_FUN_WPU field. + LP_IO_GPIO2_LP_GPIO2_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO2_FUN_WPU field. + LP_IO_GPIO2_LP_GPIO2_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO2_FUN_WPU. + LP_IO_GPIO2_LP_GPIO2_FUN_WPU = 0x100 + // Position of LP_GPIO2_FUN_IE field. + LP_IO_GPIO2_LP_GPIO2_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO2_FUN_IE field. + LP_IO_GPIO2_LP_GPIO2_FUN_IE_Msk = 0x200 + // Bit LP_GPIO2_FUN_IE. + LP_IO_GPIO2_LP_GPIO2_FUN_IE = 0x200 + // Position of LP_GPIO2_FUN_DRV field. + LP_IO_GPIO2_LP_GPIO2_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO2_FUN_DRV field. + LP_IO_GPIO2_LP_GPIO2_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO2_MCU_SEL field. + LP_IO_GPIO2_LP_GPIO2_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO2_MCU_SEL field. + LP_IO_GPIO2_LP_GPIO2_MCU_SEL_Msk = 0x7000 + + // GPIO3: need des + // Position of LP_GPIO3_MCU_OE field. + LP_IO_GPIO3_LP_GPIO3_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO3_MCU_OE field. + LP_IO_GPIO3_LP_GPIO3_MCU_OE_Msk = 0x1 + // Bit LP_GPIO3_MCU_OE. + LP_IO_GPIO3_LP_GPIO3_MCU_OE = 0x1 + // Position of LP_GPIO3_SLP_SEL field. + LP_IO_GPIO3_LP_GPIO3_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO3_SLP_SEL field. + LP_IO_GPIO3_LP_GPIO3_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO3_SLP_SEL. + LP_IO_GPIO3_LP_GPIO3_SLP_SEL = 0x2 + // Position of LP_GPIO3_MCU_WPD field. + LP_IO_GPIO3_LP_GPIO3_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO3_MCU_WPD field. + LP_IO_GPIO3_LP_GPIO3_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO3_MCU_WPD. + LP_IO_GPIO3_LP_GPIO3_MCU_WPD = 0x4 + // Position of LP_GPIO3_MCU_WPU field. + LP_IO_GPIO3_LP_GPIO3_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO3_MCU_WPU field. + LP_IO_GPIO3_LP_GPIO3_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO3_MCU_WPU. + LP_IO_GPIO3_LP_GPIO3_MCU_WPU = 0x8 + // Position of LP_GPIO3_MCU_IE field. + LP_IO_GPIO3_LP_GPIO3_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO3_MCU_IE field. + LP_IO_GPIO3_LP_GPIO3_MCU_IE_Msk = 0x10 + // Bit LP_GPIO3_MCU_IE. + LP_IO_GPIO3_LP_GPIO3_MCU_IE = 0x10 + // Position of LP_GPIO3_MCU_DRV field. + LP_IO_GPIO3_LP_GPIO3_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO3_MCU_DRV field. + LP_IO_GPIO3_LP_GPIO3_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO3_FUN_WPD field. + LP_IO_GPIO3_LP_GPIO3_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO3_FUN_WPD field. + LP_IO_GPIO3_LP_GPIO3_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO3_FUN_WPD. + LP_IO_GPIO3_LP_GPIO3_FUN_WPD = 0x80 + // Position of LP_GPIO3_FUN_WPU field. + LP_IO_GPIO3_LP_GPIO3_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO3_FUN_WPU field. + LP_IO_GPIO3_LP_GPIO3_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO3_FUN_WPU. + LP_IO_GPIO3_LP_GPIO3_FUN_WPU = 0x100 + // Position of LP_GPIO3_FUN_IE field. + LP_IO_GPIO3_LP_GPIO3_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO3_FUN_IE field. + LP_IO_GPIO3_LP_GPIO3_FUN_IE_Msk = 0x200 + // Bit LP_GPIO3_FUN_IE. + LP_IO_GPIO3_LP_GPIO3_FUN_IE = 0x200 + // Position of LP_GPIO3_FUN_DRV field. + LP_IO_GPIO3_LP_GPIO3_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO3_FUN_DRV field. + LP_IO_GPIO3_LP_GPIO3_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO3_MCU_SEL field. + LP_IO_GPIO3_LP_GPIO3_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO3_MCU_SEL field. + LP_IO_GPIO3_LP_GPIO3_MCU_SEL_Msk = 0x7000 + + // GPIO4: need des + // Position of LP_GPIO4_MCU_OE field. + LP_IO_GPIO4_LP_GPIO4_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO4_MCU_OE field. + LP_IO_GPIO4_LP_GPIO4_MCU_OE_Msk = 0x1 + // Bit LP_GPIO4_MCU_OE. + LP_IO_GPIO4_LP_GPIO4_MCU_OE = 0x1 + // Position of LP_GPIO4_SLP_SEL field. + LP_IO_GPIO4_LP_GPIO4_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO4_SLP_SEL field. + LP_IO_GPIO4_LP_GPIO4_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO4_SLP_SEL. + LP_IO_GPIO4_LP_GPIO4_SLP_SEL = 0x2 + // Position of LP_GPIO4_MCU_WPD field. + LP_IO_GPIO4_LP_GPIO4_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO4_MCU_WPD field. + LP_IO_GPIO4_LP_GPIO4_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO4_MCU_WPD. + LP_IO_GPIO4_LP_GPIO4_MCU_WPD = 0x4 + // Position of LP_GPIO4_MCU_WPU field. + LP_IO_GPIO4_LP_GPIO4_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO4_MCU_WPU field. + LP_IO_GPIO4_LP_GPIO4_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO4_MCU_WPU. + LP_IO_GPIO4_LP_GPIO4_MCU_WPU = 0x8 + // Position of LP_GPIO4_MCU_IE field. + LP_IO_GPIO4_LP_GPIO4_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO4_MCU_IE field. + LP_IO_GPIO4_LP_GPIO4_MCU_IE_Msk = 0x10 + // Bit LP_GPIO4_MCU_IE. + LP_IO_GPIO4_LP_GPIO4_MCU_IE = 0x10 + // Position of LP_GPIO4_MCU_DRV field. + LP_IO_GPIO4_LP_GPIO4_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO4_MCU_DRV field. + LP_IO_GPIO4_LP_GPIO4_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO4_FUN_WPD field. + LP_IO_GPIO4_LP_GPIO4_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO4_FUN_WPD field. + LP_IO_GPIO4_LP_GPIO4_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO4_FUN_WPD. + LP_IO_GPIO4_LP_GPIO4_FUN_WPD = 0x80 + // Position of LP_GPIO4_FUN_WPU field. + LP_IO_GPIO4_LP_GPIO4_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO4_FUN_WPU field. + LP_IO_GPIO4_LP_GPIO4_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO4_FUN_WPU. + LP_IO_GPIO4_LP_GPIO4_FUN_WPU = 0x100 + // Position of LP_GPIO4_FUN_IE field. + LP_IO_GPIO4_LP_GPIO4_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO4_FUN_IE field. + LP_IO_GPIO4_LP_GPIO4_FUN_IE_Msk = 0x200 + // Bit LP_GPIO4_FUN_IE. + LP_IO_GPIO4_LP_GPIO4_FUN_IE = 0x200 + // Position of LP_GPIO4_FUN_DRV field. + LP_IO_GPIO4_LP_GPIO4_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO4_FUN_DRV field. + LP_IO_GPIO4_LP_GPIO4_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO4_MCU_SEL field. + LP_IO_GPIO4_LP_GPIO4_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO4_MCU_SEL field. + LP_IO_GPIO4_LP_GPIO4_MCU_SEL_Msk = 0x7000 + + // GPIO5: need des + // Position of LP_GPIO5_MCU_OE field. + LP_IO_GPIO5_LP_GPIO5_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO5_MCU_OE field. + LP_IO_GPIO5_LP_GPIO5_MCU_OE_Msk = 0x1 + // Bit LP_GPIO5_MCU_OE. + LP_IO_GPIO5_LP_GPIO5_MCU_OE = 0x1 + // Position of LP_GPIO5_SLP_SEL field. + LP_IO_GPIO5_LP_GPIO5_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO5_SLP_SEL field. + LP_IO_GPIO5_LP_GPIO5_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO5_SLP_SEL. + LP_IO_GPIO5_LP_GPIO5_SLP_SEL = 0x2 + // Position of LP_GPIO5_MCU_WPD field. + LP_IO_GPIO5_LP_GPIO5_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO5_MCU_WPD field. + LP_IO_GPIO5_LP_GPIO5_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO5_MCU_WPD. + LP_IO_GPIO5_LP_GPIO5_MCU_WPD = 0x4 + // Position of LP_GPIO5_MCU_WPU field. + LP_IO_GPIO5_LP_GPIO5_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO5_MCU_WPU field. + LP_IO_GPIO5_LP_GPIO5_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO5_MCU_WPU. + LP_IO_GPIO5_LP_GPIO5_MCU_WPU = 0x8 + // Position of LP_GPIO5_MCU_IE field. + LP_IO_GPIO5_LP_GPIO5_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO5_MCU_IE field. + LP_IO_GPIO5_LP_GPIO5_MCU_IE_Msk = 0x10 + // Bit LP_GPIO5_MCU_IE. + LP_IO_GPIO5_LP_GPIO5_MCU_IE = 0x10 + // Position of LP_GPIO5_MCU_DRV field. + LP_IO_GPIO5_LP_GPIO5_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO5_MCU_DRV field. + LP_IO_GPIO5_LP_GPIO5_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO5_FUN_WPD field. + LP_IO_GPIO5_LP_GPIO5_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO5_FUN_WPD field. + LP_IO_GPIO5_LP_GPIO5_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO5_FUN_WPD. + LP_IO_GPIO5_LP_GPIO5_FUN_WPD = 0x80 + // Position of LP_GPIO5_FUN_WPU field. + LP_IO_GPIO5_LP_GPIO5_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO5_FUN_WPU field. + LP_IO_GPIO5_LP_GPIO5_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO5_FUN_WPU. + LP_IO_GPIO5_LP_GPIO5_FUN_WPU = 0x100 + // Position of LP_GPIO5_FUN_IE field. + LP_IO_GPIO5_LP_GPIO5_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO5_FUN_IE field. + LP_IO_GPIO5_LP_GPIO5_FUN_IE_Msk = 0x200 + // Bit LP_GPIO5_FUN_IE. + LP_IO_GPIO5_LP_GPIO5_FUN_IE = 0x200 + // Position of LP_GPIO5_FUN_DRV field. + LP_IO_GPIO5_LP_GPIO5_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO5_FUN_DRV field. + LP_IO_GPIO5_LP_GPIO5_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO5_MCU_SEL field. + LP_IO_GPIO5_LP_GPIO5_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO5_MCU_SEL field. + LP_IO_GPIO5_LP_GPIO5_MCU_SEL_Msk = 0x7000 + + // GPIO6: need des + // Position of LP_GPIO6_MCU_OE field. + LP_IO_GPIO6_LP_GPIO6_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO6_MCU_OE field. + LP_IO_GPIO6_LP_GPIO6_MCU_OE_Msk = 0x1 + // Bit LP_GPIO6_MCU_OE. + LP_IO_GPIO6_LP_GPIO6_MCU_OE = 0x1 + // Position of LP_GPIO6_SLP_SEL field. + LP_IO_GPIO6_LP_GPIO6_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO6_SLP_SEL field. + LP_IO_GPIO6_LP_GPIO6_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO6_SLP_SEL. + LP_IO_GPIO6_LP_GPIO6_SLP_SEL = 0x2 + // Position of LP_GPIO6_MCU_WPD field. + LP_IO_GPIO6_LP_GPIO6_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO6_MCU_WPD field. + LP_IO_GPIO6_LP_GPIO6_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO6_MCU_WPD. + LP_IO_GPIO6_LP_GPIO6_MCU_WPD = 0x4 + // Position of LP_GPIO6_MCU_WPU field. + LP_IO_GPIO6_LP_GPIO6_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO6_MCU_WPU field. + LP_IO_GPIO6_LP_GPIO6_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO6_MCU_WPU. + LP_IO_GPIO6_LP_GPIO6_MCU_WPU = 0x8 + // Position of LP_GPIO6_MCU_IE field. + LP_IO_GPIO6_LP_GPIO6_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO6_MCU_IE field. + LP_IO_GPIO6_LP_GPIO6_MCU_IE_Msk = 0x10 + // Bit LP_GPIO6_MCU_IE. + LP_IO_GPIO6_LP_GPIO6_MCU_IE = 0x10 + // Position of LP_GPIO6_MCU_DRV field. + LP_IO_GPIO6_LP_GPIO6_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO6_MCU_DRV field. + LP_IO_GPIO6_LP_GPIO6_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO6_FUN_WPD field. + LP_IO_GPIO6_LP_GPIO6_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO6_FUN_WPD field. + LP_IO_GPIO6_LP_GPIO6_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO6_FUN_WPD. + LP_IO_GPIO6_LP_GPIO6_FUN_WPD = 0x80 + // Position of LP_GPIO6_FUN_WPU field. + LP_IO_GPIO6_LP_GPIO6_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO6_FUN_WPU field. + LP_IO_GPIO6_LP_GPIO6_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO6_FUN_WPU. + LP_IO_GPIO6_LP_GPIO6_FUN_WPU = 0x100 + // Position of LP_GPIO6_FUN_IE field. + LP_IO_GPIO6_LP_GPIO6_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO6_FUN_IE field. + LP_IO_GPIO6_LP_GPIO6_FUN_IE_Msk = 0x200 + // Bit LP_GPIO6_FUN_IE. + LP_IO_GPIO6_LP_GPIO6_FUN_IE = 0x200 + // Position of LP_GPIO6_FUN_DRV field. + LP_IO_GPIO6_LP_GPIO6_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO6_FUN_DRV field. + LP_IO_GPIO6_LP_GPIO6_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO6_MCU_SEL field. + LP_IO_GPIO6_LP_GPIO6_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO6_MCU_SEL field. + LP_IO_GPIO6_LP_GPIO6_MCU_SEL_Msk = 0x7000 + + // GPIO7: need des + // Position of LP_GPIO7_MCU_OE field. + LP_IO_GPIO7_LP_GPIO7_MCU_OE_Pos = 0x0 + // Bit mask of LP_GPIO7_MCU_OE field. + LP_IO_GPIO7_LP_GPIO7_MCU_OE_Msk = 0x1 + // Bit LP_GPIO7_MCU_OE. + LP_IO_GPIO7_LP_GPIO7_MCU_OE = 0x1 + // Position of LP_GPIO7_SLP_SEL field. + LP_IO_GPIO7_LP_GPIO7_SLP_SEL_Pos = 0x1 + // Bit mask of LP_GPIO7_SLP_SEL field. + LP_IO_GPIO7_LP_GPIO7_SLP_SEL_Msk = 0x2 + // Bit LP_GPIO7_SLP_SEL. + LP_IO_GPIO7_LP_GPIO7_SLP_SEL = 0x2 + // Position of LP_GPIO7_MCU_WPD field. + LP_IO_GPIO7_LP_GPIO7_MCU_WPD_Pos = 0x2 + // Bit mask of LP_GPIO7_MCU_WPD field. + LP_IO_GPIO7_LP_GPIO7_MCU_WPD_Msk = 0x4 + // Bit LP_GPIO7_MCU_WPD. + LP_IO_GPIO7_LP_GPIO7_MCU_WPD = 0x4 + // Position of LP_GPIO7_MCU_WPU field. + LP_IO_GPIO7_LP_GPIO7_MCU_WPU_Pos = 0x3 + // Bit mask of LP_GPIO7_MCU_WPU field. + LP_IO_GPIO7_LP_GPIO7_MCU_WPU_Msk = 0x8 + // Bit LP_GPIO7_MCU_WPU. + LP_IO_GPIO7_LP_GPIO7_MCU_WPU = 0x8 + // Position of LP_GPIO7_MCU_IE field. + LP_IO_GPIO7_LP_GPIO7_MCU_IE_Pos = 0x4 + // Bit mask of LP_GPIO7_MCU_IE field. + LP_IO_GPIO7_LP_GPIO7_MCU_IE_Msk = 0x10 + // Bit LP_GPIO7_MCU_IE. + LP_IO_GPIO7_LP_GPIO7_MCU_IE = 0x10 + // Position of LP_GPIO7_MCU_DRV field. + LP_IO_GPIO7_LP_GPIO7_MCU_DRV_Pos = 0x5 + // Bit mask of LP_GPIO7_MCU_DRV field. + LP_IO_GPIO7_LP_GPIO7_MCU_DRV_Msk = 0x60 + // Position of LP_GPIO7_FUN_WPD field. + LP_IO_GPIO7_LP_GPIO7_FUN_WPD_Pos = 0x7 + // Bit mask of LP_GPIO7_FUN_WPD field. + LP_IO_GPIO7_LP_GPIO7_FUN_WPD_Msk = 0x80 + // Bit LP_GPIO7_FUN_WPD. + LP_IO_GPIO7_LP_GPIO7_FUN_WPD = 0x80 + // Position of LP_GPIO7_FUN_WPU field. + LP_IO_GPIO7_LP_GPIO7_FUN_WPU_Pos = 0x8 + // Bit mask of LP_GPIO7_FUN_WPU field. + LP_IO_GPIO7_LP_GPIO7_FUN_WPU_Msk = 0x100 + // Bit LP_GPIO7_FUN_WPU. + LP_IO_GPIO7_LP_GPIO7_FUN_WPU = 0x100 + // Position of LP_GPIO7_FUN_IE field. + LP_IO_GPIO7_LP_GPIO7_FUN_IE_Pos = 0x9 + // Bit mask of LP_GPIO7_FUN_IE field. + LP_IO_GPIO7_LP_GPIO7_FUN_IE_Msk = 0x200 + // Bit LP_GPIO7_FUN_IE. + LP_IO_GPIO7_LP_GPIO7_FUN_IE = 0x200 + // Position of LP_GPIO7_FUN_DRV field. + LP_IO_GPIO7_LP_GPIO7_FUN_DRV_Pos = 0xa + // Bit mask of LP_GPIO7_FUN_DRV field. + LP_IO_GPIO7_LP_GPIO7_FUN_DRV_Msk = 0xc00 + // Position of LP_GPIO7_MCU_SEL field. + LP_IO_GPIO7_LP_GPIO7_MCU_SEL_Pos = 0xc + // Bit mask of LP_GPIO7_MCU_SEL field. + LP_IO_GPIO7_LP_GPIO7_MCU_SEL_Msk = 0x7000 + + // STATUS_INTERRUPT: need des + // Position of LP_GPIO_STATUS_INTERRUPT_NEXT field. + LP_IO_STATUS_INTERRUPT_LP_GPIO_STATUS_INTERRUPT_NEXT_Pos = 0x0 + // Bit mask of LP_GPIO_STATUS_INTERRUPT_NEXT field. + LP_IO_STATUS_INTERRUPT_LP_GPIO_STATUS_INTERRUPT_NEXT_Msk = 0xff + + // DEBUG_SEL0: need des + // Position of LP_DEBUG_SEL0 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL0_Pos = 0x0 + // Bit mask of LP_DEBUG_SEL0 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL0_Msk = 0x7f + // Position of LP_DEBUG_SEL1 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL1_Pos = 0x7 + // Bit mask of LP_DEBUG_SEL1 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL1_Msk = 0x3f80 + // Position of LP_DEBUG_SEL2 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL2_Pos = 0xe + // Bit mask of LP_DEBUG_SEL2 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL2_Msk = 0x1fc000 + // Position of LP_DEBUG_SEL3 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL3_Pos = 0x15 + // Bit mask of LP_DEBUG_SEL3 field. + LP_IO_DEBUG_SEL0_LP_DEBUG_SEL3_Msk = 0xfe00000 + + // DEBUG_SEL1: need des + // Position of LP_DEBUG_SEL4 field. + LP_IO_DEBUG_SEL1_LP_DEBUG_SEL4_Pos = 0x0 + // Bit mask of LP_DEBUG_SEL4 field. + LP_IO_DEBUG_SEL1_LP_DEBUG_SEL4_Msk = 0x7f + + // LPI2C: need des + // Position of LP_I2C_SDA_IE field. + LP_IO_LPI2C_LP_I2C_SDA_IE_Pos = 0x1e + // Bit mask of LP_I2C_SDA_IE field. + LP_IO_LPI2C_LP_I2C_SDA_IE_Msk = 0x40000000 + // Bit LP_I2C_SDA_IE. + LP_IO_LPI2C_LP_I2C_SDA_IE = 0x40000000 + // Position of LP_I2C_SCL_IE field. + LP_IO_LPI2C_LP_I2C_SCL_IE_Pos = 0x1f + // Bit mask of LP_I2C_SCL_IE field. + LP_IO_LPI2C_LP_I2C_SCL_IE_Msk = 0x80000000 + // Bit LP_I2C_SCL_IE. + LP_IO_LPI2C_LP_I2C_SCL_IE = 0x80000000 + + // DATE: need des + // Position of LP_IO_DATE field. + LP_IO_DATE_LP_IO_DATE_Pos = 0x0 + // Bit mask of LP_IO_DATE field. + LP_IO_DATE_LP_IO_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_IO_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_IO_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_IO_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_TEE: Low-power Trusted Execution Environment +const ( + // M0_MODE_CTRL: Tee mode control register + // Position of M0_MODE field. + LP_TEE_M0_MODE_CTRL_M0_MODE_Pos = 0x0 + // Bit mask of M0_MODE field. + LP_TEE_M0_MODE_CTRL_M0_MODE_Msk = 0x3 + + // CLOCK_GATE: Clock gating register + // Position of CLK_EN field. + LP_TEE_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + LP_TEE_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + LP_TEE_CLOCK_GATE_CLK_EN = 0x1 + + // FORCE_ACC_HP: need_des + // Position of LP_AON_FORCE_ACC_HPMEM_EN field. + LP_TEE_FORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN_Pos = 0x0 + // Bit mask of LP_AON_FORCE_ACC_HPMEM_EN field. + LP_TEE_FORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN_Msk = 0x1 + // Bit LP_AON_FORCE_ACC_HPMEM_EN. + LP_TEE_FORCE_ACC_HP_LP_AON_FORCE_ACC_HPMEM_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + LP_TEE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_TEE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for LP_TIMER: Low-power Timer +const ( + // TAR0_LOW: need_des + // Position of MAIN_TIMER_TAR_LOW0 field. + LP_TIMER_TAR0_LOW_MAIN_TIMER_TAR_LOW0_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_LOW0 field. + LP_TIMER_TAR0_LOW_MAIN_TIMER_TAR_LOW0_Msk = 0xffffffff + + // TAR0_HIGH: need_des + // Position of MAIN_TIMER_TAR_HIGH0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_HIGH0_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_HIGH0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_HIGH0_Msk = 0xffff + // Position of MAIN_TIMER_TAR_EN0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0_Pos = 0x1f + // Bit mask of MAIN_TIMER_TAR_EN0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0_Msk = 0x80000000 + // Bit MAIN_TIMER_TAR_EN0. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0 = 0x80000000 + + // TAR1_LOW: need_des + // Position of MAIN_TIMER_TAR_LOW1 field. + LP_TIMER_TAR1_LOW_MAIN_TIMER_TAR_LOW1_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_LOW1 field. + LP_TIMER_TAR1_LOW_MAIN_TIMER_TAR_LOW1_Msk = 0xffffffff + + // TAR1_HIGH: need_des + // Position of MAIN_TIMER_TAR_HIGH1 field. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_HIGH1_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_HIGH1 field. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_HIGH1_Msk = 0xffff + // Position of MAIN_TIMER_TAR_EN1 field. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_EN1_Pos = 0x1f + // Bit mask of MAIN_TIMER_TAR_EN1 field. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_EN1_Msk = 0x80000000 + // Bit MAIN_TIMER_TAR_EN1. + LP_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_EN1 = 0x80000000 + + // UPDATE: need_des + // Position of MAIN_TIMER_UPDATE field. + LP_TIMER_UPDATE_MAIN_TIMER_UPDATE_Pos = 0x1c + // Bit mask of MAIN_TIMER_UPDATE field. + LP_TIMER_UPDATE_MAIN_TIMER_UPDATE_Msk = 0x10000000 + // Bit MAIN_TIMER_UPDATE. + LP_TIMER_UPDATE_MAIN_TIMER_UPDATE = 0x10000000 + // Position of MAIN_TIMER_XTAL_OFF field. + LP_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF_Pos = 0x1d + // Bit mask of MAIN_TIMER_XTAL_OFF field. + LP_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF_Msk = 0x20000000 + // Bit MAIN_TIMER_XTAL_OFF. + LP_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF = 0x20000000 + // Position of MAIN_TIMER_SYS_STALL field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_STALL_Pos = 0x1e + // Bit mask of MAIN_TIMER_SYS_STALL field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_STALL_Msk = 0x40000000 + // Bit MAIN_TIMER_SYS_STALL. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_STALL = 0x40000000 + // Position of MAIN_TIMER_SYS_RST field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_RST_Pos = 0x1f + // Bit mask of MAIN_TIMER_SYS_RST field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_RST_Msk = 0x80000000 + // Bit MAIN_TIMER_SYS_RST. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_RST = 0x80000000 + + // MAIN_BUF0_LOW: need_des + // Position of MAIN_TIMER_BUF0_LOW field. + LP_TIMER_MAIN_BUF0_LOW_MAIN_TIMER_BUF0_LOW_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF0_LOW field. + LP_TIMER_MAIN_BUF0_LOW_MAIN_TIMER_BUF0_LOW_Msk = 0xffffffff + + // MAIN_BUF0_HIGH: need_des + // Position of MAIN_TIMER_BUF0_HIGH field. + LP_TIMER_MAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF0_HIGH field. + LP_TIMER_MAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH_Msk = 0xffff + + // MAIN_BUF1_LOW: need_des + // Position of MAIN_TIMER_BUF1_LOW field. + LP_TIMER_MAIN_BUF1_LOW_MAIN_TIMER_BUF1_LOW_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF1_LOW field. + LP_TIMER_MAIN_BUF1_LOW_MAIN_TIMER_BUF1_LOW_Msk = 0xffffffff + + // MAIN_BUF1_HIGH: need_des + // Position of MAIN_TIMER_BUF1_HIGH field. + LP_TIMER_MAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF1_HIGH field. + LP_TIMER_MAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH_Msk = 0xffff + + // MAIN_OVERFLOW: need_des + // Position of MAIN_TIMER_ALARM_LOAD field. + LP_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD_Pos = 0x1f + // Bit mask of MAIN_TIMER_ALARM_LOAD field. + LP_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD_Msk = 0x80000000 + // Bit MAIN_TIMER_ALARM_LOAD. + LP_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD = 0x80000000 + + // INT_RAW: need_des + // Position of OVERFLOW_RAW field. + LP_TIMER_INT_RAW_OVERFLOW_RAW_Pos = 0x1e + // Bit mask of OVERFLOW_RAW field. + LP_TIMER_INT_RAW_OVERFLOW_RAW_Msk = 0x40000000 + // Bit OVERFLOW_RAW. + LP_TIMER_INT_RAW_OVERFLOW_RAW = 0x40000000 + // Position of SOC_WAKEUP_INT_RAW field. + LP_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_RAW field. + LP_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_RAW. + LP_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW = 0x80000000 + + // INT_ST: need_des + // Position of OVERFLOW_ST field. + LP_TIMER_INT_ST_OVERFLOW_ST_Pos = 0x1e + // Bit mask of OVERFLOW_ST field. + LP_TIMER_INT_ST_OVERFLOW_ST_Msk = 0x40000000 + // Bit OVERFLOW_ST. + LP_TIMER_INT_ST_OVERFLOW_ST = 0x40000000 + // Position of SOC_WAKEUP_INT_ST field. + LP_TIMER_INT_ST_SOC_WAKEUP_INT_ST_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ST field. + LP_TIMER_INT_ST_SOC_WAKEUP_INT_ST_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ST. + LP_TIMER_INT_ST_SOC_WAKEUP_INT_ST = 0x80000000 + + // INT_ENA: need_des + // Position of OVERFLOW_ENA field. + LP_TIMER_INT_ENA_OVERFLOW_ENA_Pos = 0x1e + // Bit mask of OVERFLOW_ENA field. + LP_TIMER_INT_ENA_OVERFLOW_ENA_Msk = 0x40000000 + // Bit OVERFLOW_ENA. + LP_TIMER_INT_ENA_OVERFLOW_ENA = 0x40000000 + // Position of SOC_WAKEUP_INT_ENA field. + LP_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ENA field. + LP_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ENA. + LP_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA = 0x80000000 + + // INT_CLR: need_des + // Position of OVERFLOW_CLR field. + LP_TIMER_INT_CLR_OVERFLOW_CLR_Pos = 0x1e + // Bit mask of OVERFLOW_CLR field. + LP_TIMER_INT_CLR_OVERFLOW_CLR_Msk = 0x40000000 + // Bit OVERFLOW_CLR. + LP_TIMER_INT_CLR_OVERFLOW_CLR = 0x40000000 + // Position of SOC_WAKEUP_INT_CLR field. + LP_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_CLR field. + LP_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_CLR. + LP_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR = 0x80000000 + + // LP_INT_RAW: need_des + // Position of MAIN_TIMER_OVERFLOW_LP_INT_RAW field. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW_Pos = 0x1e + // Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_RAW field. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW_Msk = 0x40000000 + // Bit MAIN_TIMER_OVERFLOW_LP_INT_RAW. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW = 0x40000000 + // Position of MAIN_TIMER_LP_INT_RAW field. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_LP_INT_RAW_Pos = 0x1f + // Bit mask of MAIN_TIMER_LP_INT_RAW field. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_LP_INT_RAW_Msk = 0x80000000 + // Bit MAIN_TIMER_LP_INT_RAW. + LP_TIMER_LP_INT_RAW_MAIN_TIMER_LP_INT_RAW = 0x80000000 + + // LP_INT_ST: need_des + // Position of MAIN_TIMER_OVERFLOW_LP_INT_ST field. + LP_TIMER_LP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST_Pos = 0x1e + // Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_ST field. + LP_TIMER_LP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST_Msk = 0x40000000 + // Bit MAIN_TIMER_OVERFLOW_LP_INT_ST. + LP_TIMER_LP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST = 0x40000000 + // Position of MAIN_TIMER_LP_INT_ST field. + LP_TIMER_LP_INT_ST_MAIN_TIMER_LP_INT_ST_Pos = 0x1f + // Bit mask of MAIN_TIMER_LP_INT_ST field. + LP_TIMER_LP_INT_ST_MAIN_TIMER_LP_INT_ST_Msk = 0x80000000 + // Bit MAIN_TIMER_LP_INT_ST. + LP_TIMER_LP_INT_ST_MAIN_TIMER_LP_INT_ST = 0x80000000 + + // LP_INT_ENA: need_des + // Position of MAIN_TIMER_OVERFLOW_LP_INT_ENA field. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA_Pos = 0x1e + // Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_ENA field. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA_Msk = 0x40000000 + // Bit MAIN_TIMER_OVERFLOW_LP_INT_ENA. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA = 0x40000000 + // Position of MAIN_TIMER_LP_INT_ENA field. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_LP_INT_ENA_Pos = 0x1f + // Bit mask of MAIN_TIMER_LP_INT_ENA field. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_LP_INT_ENA_Msk = 0x80000000 + // Bit MAIN_TIMER_LP_INT_ENA. + LP_TIMER_LP_INT_ENA_MAIN_TIMER_LP_INT_ENA = 0x80000000 + + // LP_INT_CLR: need_des + // Position of MAIN_TIMER_OVERFLOW_LP_INT_CLR field. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR_Pos = 0x1e + // Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_CLR field. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR_Msk = 0x40000000 + // Bit MAIN_TIMER_OVERFLOW_LP_INT_CLR. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR = 0x40000000 + // Position of MAIN_TIMER_LP_INT_CLR field. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_LP_INT_CLR_Pos = 0x1f + // Bit mask of MAIN_TIMER_LP_INT_CLR field. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_LP_INT_CLR_Msk = 0x80000000 + // Bit MAIN_TIMER_LP_INT_CLR. + LP_TIMER_LP_INT_CLR_MAIN_TIMER_LP_INT_CLR = 0x80000000 + + // DATE: need_des + // Position of DATE field. + LP_TIMER_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_TIMER_DATE_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_TIMER_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_TIMER_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_TIMER_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_UART: Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller +const ( + // FIFO: FIFO data register + // Position of RXFIFO_RD_BYTE field. + LP_UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + LP_UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_FULL_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + LP_UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + LP_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + LP_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + LP_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of PARITY_ERR_INT_RAW field. + LP_UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + LP_UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + LP_UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of FRM_ERR_INT_RAW field. + LP_UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + LP_UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + LP_UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of RXFIFO_OVF_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + LP_UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of DSR_CHG_INT_RAW field. + LP_UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + LP_UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + LP_UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of CTS_CHG_INT_RAW field. + LP_UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + LP_UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + LP_UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of BRK_DET_INT_RAW field. + LP_UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + LP_UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + LP_UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of RXFIFO_TOUT_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + LP_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + LP_UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of SW_XON_INT_RAW field. + LP_UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9 + // Bit mask of SW_XON_INT_RAW field. + LP_UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200 + // Bit SW_XON_INT_RAW. + LP_UART_INT_RAW_SW_XON_INT_RAW = 0x200 + // Position of SW_XOFF_INT_RAW field. + LP_UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa + // Bit mask of SW_XOFF_INT_RAW field. + LP_UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400 + // Bit SW_XOFF_INT_RAW. + LP_UART_INT_RAW_SW_XOFF_INT_RAW = 0x400 + // Position of GLITCH_DET_INT_RAW field. + LP_UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb + // Bit mask of GLITCH_DET_INT_RAW field. + LP_UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800 + // Bit GLITCH_DET_INT_RAW. + LP_UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800 + // Position of TX_BRK_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_RAW. + LP_UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_RAW. + LP_UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000 + // Position of TX_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of TX_DONE_INT_RAW field. + LP_UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit TX_DONE_INT_RAW. + LP_UART_INT_RAW_TX_DONE_INT_RAW = 0x4000 + // Position of AT_CMD_CHAR_DET_INT_RAW field. + LP_UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_RAW field. + LP_UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_RAW. + LP_UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000 + // Position of WAKEUP_INT_RAW field. + LP_UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13 + // Bit mask of WAKEUP_INT_RAW field. + LP_UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000 + // Bit WAKEUP_INT_RAW. + LP_UART_INT_RAW_WAKEUP_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of RXFIFO_FULL_INT_ST field. + LP_UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + LP_UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + LP_UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + LP_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + LP_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + LP_UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of PARITY_ERR_INT_ST field. + LP_UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + LP_UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + LP_UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of FRM_ERR_INT_ST field. + LP_UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + LP_UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + LP_UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of RXFIFO_OVF_INT_ST field. + LP_UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + LP_UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + LP_UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of DSR_CHG_INT_ST field. + LP_UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + LP_UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + LP_UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of CTS_CHG_INT_ST field. + LP_UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + LP_UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + LP_UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of BRK_DET_INT_ST field. + LP_UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + LP_UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + LP_UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of RXFIFO_TOUT_INT_ST field. + LP_UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + LP_UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + LP_UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of SW_XON_INT_ST field. + LP_UART_INT_ST_SW_XON_INT_ST_Pos = 0x9 + // Bit mask of SW_XON_INT_ST field. + LP_UART_INT_ST_SW_XON_INT_ST_Msk = 0x200 + // Bit SW_XON_INT_ST. + LP_UART_INT_ST_SW_XON_INT_ST = 0x200 + // Position of SW_XOFF_INT_ST field. + LP_UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa + // Bit mask of SW_XOFF_INT_ST field. + LP_UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400 + // Bit SW_XOFF_INT_ST. + LP_UART_INT_ST_SW_XOFF_INT_ST = 0x400 + // Position of GLITCH_DET_INT_ST field. + LP_UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ST field. + LP_UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800 + // Bit GLITCH_DET_INT_ST. + LP_UART_INT_ST_GLITCH_DET_INT_ST = 0x800 + // Position of TX_BRK_DONE_INT_ST field. + LP_UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ST field. + LP_UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ST. + LP_UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ST field. + LP_UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ST field. + LP_UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ST. + LP_UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000 + // Position of TX_DONE_INT_ST field. + LP_UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of TX_DONE_INT_ST field. + LP_UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000 + // Bit TX_DONE_INT_ST. + LP_UART_INT_ST_TX_DONE_INT_ST = 0x4000 + // Position of AT_CMD_CHAR_DET_INT_ST field. + LP_UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ST field. + LP_UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ST. + LP_UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000 + // Position of WAKEUP_INT_ST field. + LP_UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13 + // Bit mask of WAKEUP_INT_ST field. + LP_UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000 + // Bit WAKEUP_INT_ST. + LP_UART_INT_ST_WAKEUP_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_FULL_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + LP_UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + LP_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + LP_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + LP_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of PARITY_ERR_INT_ENA field. + LP_UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + LP_UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + LP_UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of FRM_ERR_INT_ENA field. + LP_UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + LP_UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + LP_UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of RXFIFO_OVF_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + LP_UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of DSR_CHG_INT_ENA field. + LP_UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + LP_UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + LP_UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of CTS_CHG_INT_ENA field. + LP_UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + LP_UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + LP_UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of BRK_DET_INT_ENA field. + LP_UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + LP_UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + LP_UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of RXFIFO_TOUT_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + LP_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + LP_UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of SW_XON_INT_ENA field. + LP_UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9 + // Bit mask of SW_XON_INT_ENA field. + LP_UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200 + // Bit SW_XON_INT_ENA. + LP_UART_INT_ENA_SW_XON_INT_ENA = 0x200 + // Position of SW_XOFF_INT_ENA field. + LP_UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa + // Bit mask of SW_XOFF_INT_ENA field. + LP_UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400 + // Bit SW_XOFF_INT_ENA. + LP_UART_INT_ENA_SW_XOFF_INT_ENA = 0x400 + // Position of GLITCH_DET_INT_ENA field. + LP_UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ENA field. + LP_UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800 + // Bit GLITCH_DET_INT_ENA. + LP_UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800 + // Position of TX_BRK_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ENA. + LP_UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ENA. + LP_UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000 + // Position of TX_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of TX_DONE_INT_ENA field. + LP_UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit TX_DONE_INT_ENA. + LP_UART_INT_ENA_TX_DONE_INT_ENA = 0x4000 + // Position of AT_CMD_CHAR_DET_INT_ENA field. + LP_UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ENA field. + LP_UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ENA. + LP_UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000 + // Position of WAKEUP_INT_ENA field. + LP_UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13 + // Bit mask of WAKEUP_INT_ENA field. + LP_UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000 + // Bit WAKEUP_INT_ENA. + LP_UART_INT_ENA_WAKEUP_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_FULL_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + LP_UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + LP_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + LP_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + LP_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of PARITY_ERR_INT_CLR field. + LP_UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + LP_UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + LP_UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of FRM_ERR_INT_CLR field. + LP_UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + LP_UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + LP_UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of RXFIFO_OVF_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + LP_UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of DSR_CHG_INT_CLR field. + LP_UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + LP_UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + LP_UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of CTS_CHG_INT_CLR field. + LP_UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + LP_UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + LP_UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of BRK_DET_INT_CLR field. + LP_UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + LP_UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + LP_UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of RXFIFO_TOUT_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + LP_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + LP_UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of SW_XON_INT_CLR field. + LP_UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9 + // Bit mask of SW_XON_INT_CLR field. + LP_UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200 + // Bit SW_XON_INT_CLR. + LP_UART_INT_CLR_SW_XON_INT_CLR = 0x200 + // Position of SW_XOFF_INT_CLR field. + LP_UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa + // Bit mask of SW_XOFF_INT_CLR field. + LP_UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400 + // Bit SW_XOFF_INT_CLR. + LP_UART_INT_CLR_SW_XOFF_INT_CLR = 0x400 + // Position of GLITCH_DET_INT_CLR field. + LP_UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb + // Bit mask of GLITCH_DET_INT_CLR field. + LP_UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800 + // Bit GLITCH_DET_INT_CLR. + LP_UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800 + // Position of TX_BRK_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_CLR. + LP_UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_CLR. + LP_UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000 + // Position of TX_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of TX_DONE_INT_CLR field. + LP_UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit TX_DONE_INT_CLR. + LP_UART_INT_CLR_TX_DONE_INT_CLR = 0x4000 + // Position of AT_CMD_CHAR_DET_INT_CLR field. + LP_UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_CLR field. + LP_UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_CLR. + LP_UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000 + // Position of WAKEUP_INT_CLR field. + LP_UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13 + // Bit mask of WAKEUP_INT_CLR field. + LP_UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000 + // Bit WAKEUP_INT_CLR. + LP_UART_INT_CLR_WAKEUP_INT_CLR = 0x80000 + + // CLKDIV_SYNC: Clock divider configuration + // Position of CLKDIV field. + LP_UART_CLKDIV_SYNC_CLKDIV_Pos = 0x0 + // Bit mask of CLKDIV field. + LP_UART_CLKDIV_SYNC_CLKDIV_Msk = 0xfff + // Position of CLKDIV_FRAG field. + LP_UART_CLKDIV_SYNC_CLKDIV_FRAG_Pos = 0x14 + // Bit mask of CLKDIV_FRAG field. + LP_UART_CLKDIV_SYNC_CLKDIV_FRAG_Msk = 0xf00000 + + // RX_FILT: Rx Filter configuration + // Position of GLITCH_FILT field. + LP_UART_RX_FILT_GLITCH_FILT_Pos = 0x0 + // Bit mask of GLITCH_FILT field. + LP_UART_RX_FILT_GLITCH_FILT_Msk = 0xff + // Position of GLITCH_FILT_EN field. + LP_UART_RX_FILT_GLITCH_FILT_EN_Pos = 0x8 + // Bit mask of GLITCH_FILT_EN field. + LP_UART_RX_FILT_GLITCH_FILT_EN_Msk = 0x100 + // Bit GLITCH_FILT_EN. + LP_UART_RX_FILT_GLITCH_FILT_EN = 0x100 + + // STATUS: UART status register + // Position of RXFIFO_CNT field. + LP_UART_STATUS_RXFIFO_CNT_Pos = 0x3 + // Bit mask of RXFIFO_CNT field. + LP_UART_STATUS_RXFIFO_CNT_Msk = 0xf8 + // Position of DSRN field. + LP_UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + LP_UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + LP_UART_STATUS_DSRN = 0x2000 + // Position of CTSN field. + LP_UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + LP_UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + LP_UART_STATUS_CTSN = 0x4000 + // Position of RXD field. + LP_UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + LP_UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + LP_UART_STATUS_RXD = 0x8000 + // Position of TXFIFO_CNT field. + LP_UART_STATUS_TXFIFO_CNT_Pos = 0x13 + // Bit mask of TXFIFO_CNT field. + LP_UART_STATUS_TXFIFO_CNT_Msk = 0xf80000 + // Position of DTRN field. + LP_UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + LP_UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + LP_UART_STATUS_DTRN = 0x20000000 + // Position of RTSN field. + LP_UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + LP_UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + LP_UART_STATUS_RTSN = 0x40000000 + // Position of TXD field. + LP_UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + LP_UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + LP_UART_STATUS_TXD = 0x80000000 + + // CONF0_SYNC: Configuration register 0 + // Position of PARITY field. + LP_UART_CONF0_SYNC_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + LP_UART_CONF0_SYNC_PARITY_Msk = 0x1 + // Bit PARITY. + LP_UART_CONF0_SYNC_PARITY = 0x1 + // Position of PARITY_EN field. + LP_UART_CONF0_SYNC_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + LP_UART_CONF0_SYNC_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + LP_UART_CONF0_SYNC_PARITY_EN = 0x2 + // Position of BIT_NUM field. + LP_UART_CONF0_SYNC_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + LP_UART_CONF0_SYNC_BIT_NUM_Msk = 0xc + // Position of STOP_BIT_NUM field. + LP_UART_CONF0_SYNC_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + LP_UART_CONF0_SYNC_STOP_BIT_NUM_Msk = 0x30 + // Position of TXD_BRK field. + LP_UART_CONF0_SYNC_TXD_BRK_Pos = 0x6 + // Bit mask of TXD_BRK field. + LP_UART_CONF0_SYNC_TXD_BRK_Msk = 0x40 + // Bit TXD_BRK. + LP_UART_CONF0_SYNC_TXD_BRK = 0x40 + // Position of LOOPBACK field. + LP_UART_CONF0_SYNC_LOOPBACK_Pos = 0xc + // Bit mask of LOOPBACK field. + LP_UART_CONF0_SYNC_LOOPBACK_Msk = 0x1000 + // Bit LOOPBACK. + LP_UART_CONF0_SYNC_LOOPBACK = 0x1000 + // Position of TX_FLOW_EN field. + LP_UART_CONF0_SYNC_TX_FLOW_EN_Pos = 0xd + // Bit mask of TX_FLOW_EN field. + LP_UART_CONF0_SYNC_TX_FLOW_EN_Msk = 0x2000 + // Bit TX_FLOW_EN. + LP_UART_CONF0_SYNC_TX_FLOW_EN = 0x2000 + // Position of RXD_INV field. + LP_UART_CONF0_SYNC_RXD_INV_Pos = 0xf + // Bit mask of RXD_INV field. + LP_UART_CONF0_SYNC_RXD_INV_Msk = 0x8000 + // Bit RXD_INV. + LP_UART_CONF0_SYNC_RXD_INV = 0x8000 + // Position of TXD_INV field. + LP_UART_CONF0_SYNC_TXD_INV_Pos = 0x10 + // Bit mask of TXD_INV field. + LP_UART_CONF0_SYNC_TXD_INV_Msk = 0x10000 + // Bit TXD_INV. + LP_UART_CONF0_SYNC_TXD_INV = 0x10000 + // Position of DIS_RX_DAT_OVF field. + LP_UART_CONF0_SYNC_DIS_RX_DAT_OVF_Pos = 0x11 + // Bit mask of DIS_RX_DAT_OVF field. + LP_UART_CONF0_SYNC_DIS_RX_DAT_OVF_Msk = 0x20000 + // Bit DIS_RX_DAT_OVF. + LP_UART_CONF0_SYNC_DIS_RX_DAT_OVF = 0x20000 + // Position of ERR_WR_MASK field. + LP_UART_CONF0_SYNC_ERR_WR_MASK_Pos = 0x12 + // Bit mask of ERR_WR_MASK field. + LP_UART_CONF0_SYNC_ERR_WR_MASK_Msk = 0x40000 + // Bit ERR_WR_MASK. + LP_UART_CONF0_SYNC_ERR_WR_MASK = 0x40000 + // Position of MEM_CLK_EN field. + LP_UART_CONF0_SYNC_MEM_CLK_EN_Pos = 0x14 + // Bit mask of MEM_CLK_EN field. + LP_UART_CONF0_SYNC_MEM_CLK_EN_Msk = 0x100000 + // Bit MEM_CLK_EN. + LP_UART_CONF0_SYNC_MEM_CLK_EN = 0x100000 + // Position of SW_RTS field. + LP_UART_CONF0_SYNC_SW_RTS_Pos = 0x15 + // Bit mask of SW_RTS field. + LP_UART_CONF0_SYNC_SW_RTS_Msk = 0x200000 + // Bit SW_RTS. + LP_UART_CONF0_SYNC_SW_RTS = 0x200000 + // Position of RXFIFO_RST field. + LP_UART_CONF0_SYNC_RXFIFO_RST_Pos = 0x16 + // Bit mask of RXFIFO_RST field. + LP_UART_CONF0_SYNC_RXFIFO_RST_Msk = 0x400000 + // Bit RXFIFO_RST. + LP_UART_CONF0_SYNC_RXFIFO_RST = 0x400000 + // Position of TXFIFO_RST field. + LP_UART_CONF0_SYNC_TXFIFO_RST_Pos = 0x17 + // Bit mask of TXFIFO_RST field. + LP_UART_CONF0_SYNC_TXFIFO_RST_Msk = 0x800000 + // Bit TXFIFO_RST. + LP_UART_CONF0_SYNC_TXFIFO_RST = 0x800000 + + // CONF1: Configuration register 1 + // Position of RXFIFO_FULL_THRHD field. + LP_UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x3 + // Bit mask of RXFIFO_FULL_THRHD field. + LP_UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0xf8 + // Position of TXFIFO_EMPTY_THRHD field. + LP_UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0xb + // Bit mask of TXFIFO_EMPTY_THRHD field. + LP_UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0xf800 + // Position of CTS_INV field. + LP_UART_CONF1_CTS_INV_Pos = 0x10 + // Bit mask of CTS_INV field. + LP_UART_CONF1_CTS_INV_Msk = 0x10000 + // Bit CTS_INV. + LP_UART_CONF1_CTS_INV = 0x10000 + // Position of DSR_INV field. + LP_UART_CONF1_DSR_INV_Pos = 0x11 + // Bit mask of DSR_INV field. + LP_UART_CONF1_DSR_INV_Msk = 0x20000 + // Bit DSR_INV. + LP_UART_CONF1_DSR_INV = 0x20000 + // Position of RTS_INV field. + LP_UART_CONF1_RTS_INV_Pos = 0x12 + // Bit mask of RTS_INV field. + LP_UART_CONF1_RTS_INV_Msk = 0x40000 + // Bit RTS_INV. + LP_UART_CONF1_RTS_INV = 0x40000 + // Position of DTR_INV field. + LP_UART_CONF1_DTR_INV_Pos = 0x13 + // Bit mask of DTR_INV field. + LP_UART_CONF1_DTR_INV_Msk = 0x80000 + // Bit DTR_INV. + LP_UART_CONF1_DTR_INV = 0x80000 + // Position of SW_DTR field. + LP_UART_CONF1_SW_DTR_Pos = 0x14 + // Bit mask of SW_DTR field. + LP_UART_CONF1_SW_DTR_Msk = 0x100000 + // Bit SW_DTR. + LP_UART_CONF1_SW_DTR = 0x100000 + // Position of CLK_EN field. + LP_UART_CONF1_CLK_EN_Pos = 0x15 + // Bit mask of CLK_EN field. + LP_UART_CONF1_CLK_EN_Msk = 0x200000 + // Bit CLK_EN. + LP_UART_CONF1_CLK_EN = 0x200000 + + // HWFC_CONF_SYNC: Hardware flow-control configuration + // Position of RX_FLOW_THRHD field. + LP_UART_HWFC_CONF_SYNC_RX_FLOW_THRHD_Pos = 0x3 + // Bit mask of RX_FLOW_THRHD field. + LP_UART_HWFC_CONF_SYNC_RX_FLOW_THRHD_Msk = 0xf8 + // Position of RX_FLOW_EN field. + LP_UART_HWFC_CONF_SYNC_RX_FLOW_EN_Pos = 0x8 + // Bit mask of RX_FLOW_EN field. + LP_UART_HWFC_CONF_SYNC_RX_FLOW_EN_Msk = 0x100 + // Bit RX_FLOW_EN. + LP_UART_HWFC_CONF_SYNC_RX_FLOW_EN = 0x100 + + // SLEEP_CONF0: UART sleep configure register 0 + // Position of WK_CHAR1 field. + LP_UART_SLEEP_CONF0_WK_CHAR1_Pos = 0x0 + // Bit mask of WK_CHAR1 field. + LP_UART_SLEEP_CONF0_WK_CHAR1_Msk = 0xff + // Position of WK_CHAR2 field. + LP_UART_SLEEP_CONF0_WK_CHAR2_Pos = 0x8 + // Bit mask of WK_CHAR2 field. + LP_UART_SLEEP_CONF0_WK_CHAR2_Msk = 0xff00 + // Position of WK_CHAR3 field. + LP_UART_SLEEP_CONF0_WK_CHAR3_Pos = 0x10 + // Bit mask of WK_CHAR3 field. + LP_UART_SLEEP_CONF0_WK_CHAR3_Msk = 0xff0000 + // Position of WK_CHAR4 field. + LP_UART_SLEEP_CONF0_WK_CHAR4_Pos = 0x18 + // Bit mask of WK_CHAR4 field. + LP_UART_SLEEP_CONF0_WK_CHAR4_Msk = 0xff000000 + + // SLEEP_CONF1: UART sleep configure register 1 + // Position of WK_CHAR0 field. + LP_UART_SLEEP_CONF1_WK_CHAR0_Pos = 0x0 + // Bit mask of WK_CHAR0 field. + LP_UART_SLEEP_CONF1_WK_CHAR0_Msk = 0xff + + // SLEEP_CONF2: UART sleep configure register 2 + // Position of ACTIVE_THRESHOLD field. + LP_UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Pos = 0x0 + // Bit mask of ACTIVE_THRESHOLD field. + LP_UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Msk = 0x3ff + // Position of RX_WAKE_UP_THRHD field. + LP_UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Pos = 0xd + // Bit mask of RX_WAKE_UP_THRHD field. + LP_UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Msk = 0x3e000 + // Position of WK_CHAR_NUM field. + LP_UART_SLEEP_CONF2_WK_CHAR_NUM_Pos = 0x12 + // Bit mask of WK_CHAR_NUM field. + LP_UART_SLEEP_CONF2_WK_CHAR_NUM_Msk = 0x1c0000 + // Position of WK_CHAR_MASK field. + LP_UART_SLEEP_CONF2_WK_CHAR_MASK_Pos = 0x15 + // Bit mask of WK_CHAR_MASK field. + LP_UART_SLEEP_CONF2_WK_CHAR_MASK_Msk = 0x3e00000 + // Position of WK_MODE_SEL field. + LP_UART_SLEEP_CONF2_WK_MODE_SEL_Pos = 0x1a + // Bit mask of WK_MODE_SEL field. + LP_UART_SLEEP_CONF2_WK_MODE_SEL_Msk = 0xc000000 + + // SWFC_CONF0_SYNC: Software flow-control character configuration + // Position of XON_CHAR field. + LP_UART_SWFC_CONF0_SYNC_XON_CHAR_Pos = 0x0 + // Bit mask of XON_CHAR field. + LP_UART_SWFC_CONF0_SYNC_XON_CHAR_Msk = 0xff + // Position of XOFF_CHAR field. + LP_UART_SWFC_CONF0_SYNC_XOFF_CHAR_Pos = 0x8 + // Bit mask of XOFF_CHAR field. + LP_UART_SWFC_CONF0_SYNC_XOFF_CHAR_Msk = 0xff00 + // Position of XON_XOFF_STILL_SEND field. + LP_UART_SWFC_CONF0_SYNC_XON_XOFF_STILL_SEND_Pos = 0x10 + // Bit mask of XON_XOFF_STILL_SEND field. + LP_UART_SWFC_CONF0_SYNC_XON_XOFF_STILL_SEND_Msk = 0x10000 + // Bit XON_XOFF_STILL_SEND. + LP_UART_SWFC_CONF0_SYNC_XON_XOFF_STILL_SEND = 0x10000 + // Position of SW_FLOW_CON_EN field. + LP_UART_SWFC_CONF0_SYNC_SW_FLOW_CON_EN_Pos = 0x11 + // Bit mask of SW_FLOW_CON_EN field. + LP_UART_SWFC_CONF0_SYNC_SW_FLOW_CON_EN_Msk = 0x20000 + // Bit SW_FLOW_CON_EN. + LP_UART_SWFC_CONF0_SYNC_SW_FLOW_CON_EN = 0x20000 + // Position of XONOFF_DEL field. + LP_UART_SWFC_CONF0_SYNC_XONOFF_DEL_Pos = 0x12 + // Bit mask of XONOFF_DEL field. + LP_UART_SWFC_CONF0_SYNC_XONOFF_DEL_Msk = 0x40000 + // Bit XONOFF_DEL. + LP_UART_SWFC_CONF0_SYNC_XONOFF_DEL = 0x40000 + // Position of FORCE_XON field. + LP_UART_SWFC_CONF0_SYNC_FORCE_XON_Pos = 0x13 + // Bit mask of FORCE_XON field. + LP_UART_SWFC_CONF0_SYNC_FORCE_XON_Msk = 0x80000 + // Bit FORCE_XON. + LP_UART_SWFC_CONF0_SYNC_FORCE_XON = 0x80000 + // Position of FORCE_XOFF field. + LP_UART_SWFC_CONF0_SYNC_FORCE_XOFF_Pos = 0x14 + // Bit mask of FORCE_XOFF field. + LP_UART_SWFC_CONF0_SYNC_FORCE_XOFF_Msk = 0x100000 + // Bit FORCE_XOFF. + LP_UART_SWFC_CONF0_SYNC_FORCE_XOFF = 0x100000 + // Position of SEND_XON field. + LP_UART_SWFC_CONF0_SYNC_SEND_XON_Pos = 0x15 + // Bit mask of SEND_XON field. + LP_UART_SWFC_CONF0_SYNC_SEND_XON_Msk = 0x200000 + // Bit SEND_XON. + LP_UART_SWFC_CONF0_SYNC_SEND_XON = 0x200000 + // Position of SEND_XOFF field. + LP_UART_SWFC_CONF0_SYNC_SEND_XOFF_Pos = 0x16 + // Bit mask of SEND_XOFF field. + LP_UART_SWFC_CONF0_SYNC_SEND_XOFF_Msk = 0x400000 + // Bit SEND_XOFF. + LP_UART_SWFC_CONF0_SYNC_SEND_XOFF = 0x400000 + + // SWFC_CONF1: Software flow-control character configuration + // Position of XON_THRESHOLD field. + LP_UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x3 + // Bit mask of XON_THRESHOLD field. + LP_UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0xf8 + // Position of XOFF_THRESHOLD field. + LP_UART_SWFC_CONF1_XOFF_THRESHOLD_Pos = 0xb + // Bit mask of XOFF_THRESHOLD field. + LP_UART_SWFC_CONF1_XOFF_THRESHOLD_Msk = 0xf800 + + // TXBRK_CONF_SYNC: Tx Break character configuration + // Position of TX_BRK_NUM field. + LP_UART_TXBRK_CONF_SYNC_TX_BRK_NUM_Pos = 0x0 + // Bit mask of TX_BRK_NUM field. + LP_UART_TXBRK_CONF_SYNC_TX_BRK_NUM_Msk = 0xff + + // IDLE_CONF_SYNC: Frame-end idle configuration + // Position of RX_IDLE_THRHD field. + LP_UART_IDLE_CONF_SYNC_RX_IDLE_THRHD_Pos = 0x0 + // Bit mask of RX_IDLE_THRHD field. + LP_UART_IDLE_CONF_SYNC_RX_IDLE_THRHD_Msk = 0x3ff + // Position of TX_IDLE_NUM field. + LP_UART_IDLE_CONF_SYNC_TX_IDLE_NUM_Pos = 0xa + // Bit mask of TX_IDLE_NUM field. + LP_UART_IDLE_CONF_SYNC_TX_IDLE_NUM_Msk = 0xffc00 + + // RS485_CONF_SYNC: RS485 mode configuration + // Position of DL0_EN field. + LP_UART_RS485_CONF_SYNC_DL0_EN_Pos = 0x1 + // Bit mask of DL0_EN field. + LP_UART_RS485_CONF_SYNC_DL0_EN_Msk = 0x2 + // Bit DL0_EN. + LP_UART_RS485_CONF_SYNC_DL0_EN = 0x2 + // Position of DL1_EN field. + LP_UART_RS485_CONF_SYNC_DL1_EN_Pos = 0x2 + // Bit mask of DL1_EN field. + LP_UART_RS485_CONF_SYNC_DL1_EN_Msk = 0x4 + // Bit DL1_EN. + LP_UART_RS485_CONF_SYNC_DL1_EN = 0x4 + + // AT_CMD_PRECNT_SYNC: Pre-sequence timing configuration + // Position of PRE_IDLE_NUM field. + LP_UART_AT_CMD_PRECNT_SYNC_PRE_IDLE_NUM_Pos = 0x0 + // Bit mask of PRE_IDLE_NUM field. + LP_UART_AT_CMD_PRECNT_SYNC_PRE_IDLE_NUM_Msk = 0xffff + + // AT_CMD_POSTCNT_SYNC: Post-sequence timing configuration + // Position of POST_IDLE_NUM field. + LP_UART_AT_CMD_POSTCNT_SYNC_POST_IDLE_NUM_Pos = 0x0 + // Bit mask of POST_IDLE_NUM field. + LP_UART_AT_CMD_POSTCNT_SYNC_POST_IDLE_NUM_Msk = 0xffff + + // AT_CMD_GAPTOUT_SYNC: Timeout configuration + // Position of RX_GAP_TOUT field. + LP_UART_AT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT_Pos = 0x0 + // Bit mask of RX_GAP_TOUT field. + LP_UART_AT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT_Msk = 0xffff + + // AT_CMD_CHAR_SYNC: AT escape sequence detection configuration + // Position of AT_CMD_CHAR field. + LP_UART_AT_CMD_CHAR_SYNC_AT_CMD_CHAR_Pos = 0x0 + // Bit mask of AT_CMD_CHAR field. + LP_UART_AT_CMD_CHAR_SYNC_AT_CMD_CHAR_Msk = 0xff + // Position of CHAR_NUM field. + LP_UART_AT_CMD_CHAR_SYNC_CHAR_NUM_Pos = 0x8 + // Bit mask of CHAR_NUM field. + LP_UART_AT_CMD_CHAR_SYNC_CHAR_NUM_Msk = 0xff00 + + // MEM_CONF: UART memory power configuration + // Position of MEM_FORCE_PD field. + LP_UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x19 + // Bit mask of MEM_FORCE_PD field. + LP_UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x2000000 + // Bit MEM_FORCE_PD. + LP_UART_MEM_CONF_MEM_FORCE_PD = 0x2000000 + // Position of MEM_FORCE_PU field. + LP_UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1a + // Bit mask of MEM_FORCE_PU field. + LP_UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x4000000 + // Bit MEM_FORCE_PU. + LP_UART_MEM_CONF_MEM_FORCE_PU = 0x4000000 + + // TOUT_CONF_SYNC: UART threshold and allocation configuration + // Position of RX_TOUT_EN field. + LP_UART_TOUT_CONF_SYNC_RX_TOUT_EN_Pos = 0x0 + // Bit mask of RX_TOUT_EN field. + LP_UART_TOUT_CONF_SYNC_RX_TOUT_EN_Msk = 0x1 + // Bit RX_TOUT_EN. + LP_UART_TOUT_CONF_SYNC_RX_TOUT_EN = 0x1 + // Position of RX_TOUT_FLOW_DIS field. + LP_UART_TOUT_CONF_SYNC_RX_TOUT_FLOW_DIS_Pos = 0x1 + // Bit mask of RX_TOUT_FLOW_DIS field. + LP_UART_TOUT_CONF_SYNC_RX_TOUT_FLOW_DIS_Msk = 0x2 + // Bit RX_TOUT_FLOW_DIS. + LP_UART_TOUT_CONF_SYNC_RX_TOUT_FLOW_DIS = 0x2 + // Position of RX_TOUT_THRHD field. + LP_UART_TOUT_CONF_SYNC_RX_TOUT_THRHD_Pos = 0x2 + // Bit mask of RX_TOUT_THRHD field. + LP_UART_TOUT_CONF_SYNC_RX_TOUT_THRHD_Msk = 0xffc + + // MEM_TX_STATUS: Tx-SRAM write and read offset address. + // Position of TX_SRAM_WADDR field. + LP_UART_MEM_TX_STATUS_TX_SRAM_WADDR_Pos = 0x3 + // Bit mask of TX_SRAM_WADDR field. + LP_UART_MEM_TX_STATUS_TX_SRAM_WADDR_Msk = 0xf8 + // Position of TX_SRAM_RADDR field. + LP_UART_MEM_TX_STATUS_TX_SRAM_RADDR_Pos = 0xc + // Bit mask of TX_SRAM_RADDR field. + LP_UART_MEM_TX_STATUS_TX_SRAM_RADDR_Msk = 0x1f000 + + // MEM_RX_STATUS: Rx-SRAM write and read offset address. + // Position of RX_SRAM_RADDR field. + LP_UART_MEM_RX_STATUS_RX_SRAM_RADDR_Pos = 0x3 + // Bit mask of RX_SRAM_RADDR field. + LP_UART_MEM_RX_STATUS_RX_SRAM_RADDR_Msk = 0xf8 + // Position of RX_SRAM_WADDR field. + LP_UART_MEM_RX_STATUS_RX_SRAM_WADDR_Pos = 0xc + // Bit mask of RX_SRAM_WADDR field. + LP_UART_MEM_RX_STATUS_RX_SRAM_WADDR_Msk = 0x1f000 + + // FSM_STATUS: UART transmit and receive status. + // Position of ST_URX_OUT field. + LP_UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0 + // Bit mask of ST_URX_OUT field. + LP_UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf + // Position of ST_UTX_OUT field. + LP_UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4 + // Bit mask of ST_UTX_OUT field. + LP_UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0 + + // CLK_CONF: UART core clock configuration + // Position of SCLK_DIV_B field. + LP_UART_CLK_CONF_SCLK_DIV_B_Pos = 0x0 + // Bit mask of SCLK_DIV_B field. + LP_UART_CLK_CONF_SCLK_DIV_B_Msk = 0x3f + // Position of SCLK_DIV_A field. + LP_UART_CLK_CONF_SCLK_DIV_A_Pos = 0x6 + // Bit mask of SCLK_DIV_A field. + LP_UART_CLK_CONF_SCLK_DIV_A_Msk = 0xfc0 + // Position of SCLK_DIV_NUM field. + LP_UART_CLK_CONF_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of SCLK_DIV_NUM field. + LP_UART_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff000 + // Position of SCLK_SEL field. + LP_UART_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + LP_UART_CLK_CONF_SCLK_SEL_Msk = 0x300000 + // Position of SCLK_EN field. + LP_UART_CLK_CONF_SCLK_EN_Pos = 0x16 + // Bit mask of SCLK_EN field. + LP_UART_CLK_CONF_SCLK_EN_Msk = 0x400000 + // Bit SCLK_EN. + LP_UART_CLK_CONF_SCLK_EN = 0x400000 + // Position of RST_CORE field. + LP_UART_CLK_CONF_RST_CORE_Pos = 0x17 + // Bit mask of RST_CORE field. + LP_UART_CLK_CONF_RST_CORE_Msk = 0x800000 + // Bit RST_CORE. + LP_UART_CLK_CONF_RST_CORE = 0x800000 + // Position of TX_SCLK_EN field. + LP_UART_CLK_CONF_TX_SCLK_EN_Pos = 0x18 + // Bit mask of TX_SCLK_EN field. + LP_UART_CLK_CONF_TX_SCLK_EN_Msk = 0x1000000 + // Bit TX_SCLK_EN. + LP_UART_CLK_CONF_TX_SCLK_EN = 0x1000000 + // Position of RX_SCLK_EN field. + LP_UART_CLK_CONF_RX_SCLK_EN_Pos = 0x19 + // Bit mask of RX_SCLK_EN field. + LP_UART_CLK_CONF_RX_SCLK_EN_Msk = 0x2000000 + // Bit RX_SCLK_EN. + LP_UART_CLK_CONF_RX_SCLK_EN = 0x2000000 + // Position of TX_RST_CORE field. + LP_UART_CLK_CONF_TX_RST_CORE_Pos = 0x1a + // Bit mask of TX_RST_CORE field. + LP_UART_CLK_CONF_TX_RST_CORE_Msk = 0x4000000 + // Bit TX_RST_CORE. + LP_UART_CLK_CONF_TX_RST_CORE = 0x4000000 + // Position of RX_RST_CORE field. + LP_UART_CLK_CONF_RX_RST_CORE_Pos = 0x1b + // Bit mask of RX_RST_CORE field. + LP_UART_CLK_CONF_RX_RST_CORE_Msk = 0x8000000 + // Bit RX_RST_CORE. + LP_UART_CLK_CONF_RX_RST_CORE = 0x8000000 + + // DATE: UART Version register + // Position of DATE field. + LP_UART_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_UART_DATE_DATE_Msk = 0xffffffff + + // AFIFO_STATUS: UART AFIFO Status + // Position of TX_AFIFO_FULL field. + LP_UART_AFIFO_STATUS_TX_AFIFO_FULL_Pos = 0x0 + // Bit mask of TX_AFIFO_FULL field. + LP_UART_AFIFO_STATUS_TX_AFIFO_FULL_Msk = 0x1 + // Bit TX_AFIFO_FULL. + LP_UART_AFIFO_STATUS_TX_AFIFO_FULL = 0x1 + // Position of TX_AFIFO_EMPTY field. + LP_UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Pos = 0x1 + // Bit mask of TX_AFIFO_EMPTY field. + LP_UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Msk = 0x2 + // Bit TX_AFIFO_EMPTY. + LP_UART_AFIFO_STATUS_TX_AFIFO_EMPTY = 0x2 + // Position of RX_AFIFO_FULL field. + LP_UART_AFIFO_STATUS_RX_AFIFO_FULL_Pos = 0x2 + // Bit mask of RX_AFIFO_FULL field. + LP_UART_AFIFO_STATUS_RX_AFIFO_FULL_Msk = 0x4 + // Bit RX_AFIFO_FULL. + LP_UART_AFIFO_STATUS_RX_AFIFO_FULL = 0x4 + // Position of RX_AFIFO_EMPTY field. + LP_UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Pos = 0x3 + // Bit mask of RX_AFIFO_EMPTY field. + LP_UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Msk = 0x8 + // Bit RX_AFIFO_EMPTY. + LP_UART_AFIFO_STATUS_RX_AFIFO_EMPTY = 0x8 + + // REG_UPDATE: UART Registers Configuration Update register + // Position of REG_UPDATE field. + LP_UART_REG_UPDATE_REG_UPDATE_Pos = 0x0 + // Bit mask of REG_UPDATE field. + LP_UART_REG_UPDATE_REG_UPDATE_Msk = 0x1 + // Bit REG_UPDATE. + LP_UART_REG_UPDATE_REG_UPDATE = 0x1 + + // ID: UART ID register + // Position of ID field. + LP_UART_ID_ID_Pos = 0x0 + // Bit mask of ID field. + LP_UART_ID_ID_Msk = 0xffffffff +) + +// Constants for LP_WDT: Low-power Watchdog Timer +const ( + // CONFIG0: need_des + // Position of WDT_CHIP_RESET_WIDTH field. + LP_WDT_CONFIG0_WDT_CHIP_RESET_WIDTH_Pos = 0x0 + // Bit mask of WDT_CHIP_RESET_WIDTH field. + LP_WDT_CONFIG0_WDT_CHIP_RESET_WIDTH_Msk = 0xff + // Position of WDT_CHIP_RESET_EN field. + LP_WDT_CONFIG0_WDT_CHIP_RESET_EN_Pos = 0x8 + // Bit mask of WDT_CHIP_RESET_EN field. + LP_WDT_CONFIG0_WDT_CHIP_RESET_EN_Msk = 0x100 + // Bit WDT_CHIP_RESET_EN. + LP_WDT_CONFIG0_WDT_CHIP_RESET_EN = 0x100 + // Position of WDT_PAUSE_IN_SLP field. + LP_WDT_CONFIG0_WDT_PAUSE_IN_SLP_Pos = 0x9 + // Bit mask of WDT_PAUSE_IN_SLP field. + LP_WDT_CONFIG0_WDT_PAUSE_IN_SLP_Msk = 0x200 + // Bit WDT_PAUSE_IN_SLP. + LP_WDT_CONFIG0_WDT_PAUSE_IN_SLP = 0x200 + // Position of WDT_APPCPU_RESET_EN field. + LP_WDT_CONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xa + // Bit mask of WDT_APPCPU_RESET_EN field. + LP_WDT_CONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x400 + // Bit WDT_APPCPU_RESET_EN. + LP_WDT_CONFIG0_WDT_APPCPU_RESET_EN = 0x400 + // Position of WDT_PROCPU_RESET_EN field. + LP_WDT_CONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xb + // Bit mask of WDT_PROCPU_RESET_EN field. + LP_WDT_CONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x800 + // Bit WDT_PROCPU_RESET_EN. + LP_WDT_CONFIG0_WDT_PROCPU_RESET_EN = 0x800 + // Position of WDT_FLASHBOOT_MOD_EN field. + LP_WDT_CONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xc + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + LP_WDT_CONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x1000 + // Bit WDT_FLASHBOOT_MOD_EN. + LP_WDT_CONFIG0_WDT_FLASHBOOT_MOD_EN = 0x1000 + // Position of WDT_SYS_RESET_LENGTH field. + LP_WDT_CONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xd + // Bit mask of WDT_SYS_RESET_LENGTH field. + LP_WDT_CONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0xe000 + // Position of WDT_CPU_RESET_LENGTH field. + LP_WDT_CONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x10 + // Bit mask of WDT_CPU_RESET_LENGTH field. + LP_WDT_CONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x70000 + // Position of WDT_STG3 field. + LP_WDT_CONFIG0_WDT_STG3_Pos = 0x13 + // Bit mask of WDT_STG3 field. + LP_WDT_CONFIG0_WDT_STG3_Msk = 0x380000 + // Position of WDT_STG2 field. + LP_WDT_CONFIG0_WDT_STG2_Pos = 0x16 + // Bit mask of WDT_STG2 field. + LP_WDT_CONFIG0_WDT_STG2_Msk = 0x1c00000 + // Position of WDT_STG1 field. + LP_WDT_CONFIG0_WDT_STG1_Pos = 0x19 + // Bit mask of WDT_STG1 field. + LP_WDT_CONFIG0_WDT_STG1_Msk = 0xe000000 + // Position of WDT_STG0 field. + LP_WDT_CONFIG0_WDT_STG0_Pos = 0x1c + // Bit mask of WDT_STG0 field. + LP_WDT_CONFIG0_WDT_STG0_Msk = 0x70000000 + // Position of WDT_EN field. + LP_WDT_CONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + LP_WDT_CONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + LP_WDT_CONFIG0_WDT_EN = 0x80000000 + + // CONFIG1: need_des + // Position of WDT_STG0_HOLD field. + LP_WDT_CONFIG1_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + LP_WDT_CONFIG1_WDT_STG0_HOLD_Msk = 0xffffffff + + // CONFIG2: need_des + // Position of WDT_STG1_HOLD field. + LP_WDT_CONFIG2_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + LP_WDT_CONFIG2_WDT_STG1_HOLD_Msk = 0xffffffff + + // CONFIG3: need_des + // Position of WDT_STG2_HOLD field. + LP_WDT_CONFIG3_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + LP_WDT_CONFIG3_WDT_STG2_HOLD_Msk = 0xffffffff + + // CONFIG4: need_des + // Position of WDT_STG3_HOLD field. + LP_WDT_CONFIG4_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + LP_WDT_CONFIG4_WDT_STG3_HOLD_Msk = 0xffffffff + + // FEED: need_des + // Position of RTC_WDT_FEED field. + LP_WDT_FEED_RTC_WDT_FEED_Pos = 0x1f + // Bit mask of RTC_WDT_FEED field. + LP_WDT_FEED_RTC_WDT_FEED_Msk = 0x80000000 + // Bit RTC_WDT_FEED. + LP_WDT_FEED_RTC_WDT_FEED = 0x80000000 + + // WPROTECT: need_des + // Position of WDT_WKEY field. + LP_WDT_WPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + LP_WDT_WPROTECT_WDT_WKEY_Msk = 0xffffffff + + // SWD_CONFIG: need_des + // Position of SWD_RESET_FLAG field. + LP_WDT_SWD_CONFIG_SWD_RESET_FLAG_Pos = 0x0 + // Bit mask of SWD_RESET_FLAG field. + LP_WDT_SWD_CONFIG_SWD_RESET_FLAG_Msk = 0x1 + // Bit SWD_RESET_FLAG. + LP_WDT_SWD_CONFIG_SWD_RESET_FLAG = 0x1 + // Position of SWD_AUTO_FEED_EN field. + LP_WDT_SWD_CONFIG_SWD_AUTO_FEED_EN_Pos = 0x12 + // Bit mask of SWD_AUTO_FEED_EN field. + LP_WDT_SWD_CONFIG_SWD_AUTO_FEED_EN_Msk = 0x40000 + // Bit SWD_AUTO_FEED_EN. + LP_WDT_SWD_CONFIG_SWD_AUTO_FEED_EN = 0x40000 + // Position of SWD_RST_FLAG_CLR field. + LP_WDT_SWD_CONFIG_SWD_RST_FLAG_CLR_Pos = 0x13 + // Bit mask of SWD_RST_FLAG_CLR field. + LP_WDT_SWD_CONFIG_SWD_RST_FLAG_CLR_Msk = 0x80000 + // Bit SWD_RST_FLAG_CLR. + LP_WDT_SWD_CONFIG_SWD_RST_FLAG_CLR = 0x80000 + // Position of SWD_SIGNAL_WIDTH field. + LP_WDT_SWD_CONFIG_SWD_SIGNAL_WIDTH_Pos = 0x14 + // Bit mask of SWD_SIGNAL_WIDTH field. + LP_WDT_SWD_CONFIG_SWD_SIGNAL_WIDTH_Msk = 0x3ff00000 + // Position of SWD_DISABLE field. + LP_WDT_SWD_CONFIG_SWD_DISABLE_Pos = 0x1e + // Bit mask of SWD_DISABLE field. + LP_WDT_SWD_CONFIG_SWD_DISABLE_Msk = 0x40000000 + // Bit SWD_DISABLE. + LP_WDT_SWD_CONFIG_SWD_DISABLE = 0x40000000 + // Position of SWD_FEED field. + LP_WDT_SWD_CONFIG_SWD_FEED_Pos = 0x1f + // Bit mask of SWD_FEED field. + LP_WDT_SWD_CONFIG_SWD_FEED_Msk = 0x80000000 + // Bit SWD_FEED. + LP_WDT_SWD_CONFIG_SWD_FEED = 0x80000000 + + // SWD_WPROTECT: need_des + // Position of SWD_WKEY field. + LP_WDT_SWD_WPROTECT_SWD_WKEY_Pos = 0x0 + // Bit mask of SWD_WKEY field. + LP_WDT_SWD_WPROTECT_SWD_WKEY_Msk = 0xffffffff + + // INT_RAW: need_des + // Position of SUPER_WDT_INT_RAW field. + LP_WDT_INT_RAW_SUPER_WDT_INT_RAW_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_RAW field. + LP_WDT_INT_RAW_SUPER_WDT_INT_RAW_Msk = 0x40000000 + // Bit SUPER_WDT_INT_RAW. + LP_WDT_INT_RAW_SUPER_WDT_INT_RAW = 0x40000000 + // Position of LP_WDT_INT_RAW field. + LP_WDT_INT_RAW_LP_WDT_INT_RAW_Pos = 0x1f + // Bit mask of LP_WDT_INT_RAW field. + LP_WDT_INT_RAW_LP_WDT_INT_RAW_Msk = 0x80000000 + // Bit LP_WDT_INT_RAW. + LP_WDT_INT_RAW_LP_WDT_INT_RAW = 0x80000000 + + // INT_ST: need_des + // Position of SUPER_WDT_INT_ST field. + LP_WDT_INT_ST_SUPER_WDT_INT_ST_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_ST field. + LP_WDT_INT_ST_SUPER_WDT_INT_ST_Msk = 0x40000000 + // Bit SUPER_WDT_INT_ST. + LP_WDT_INT_ST_SUPER_WDT_INT_ST = 0x40000000 + // Position of LP_WDT_INT_ST field. + LP_WDT_INT_ST_LP_WDT_INT_ST_Pos = 0x1f + // Bit mask of LP_WDT_INT_ST field. + LP_WDT_INT_ST_LP_WDT_INT_ST_Msk = 0x80000000 + // Bit LP_WDT_INT_ST. + LP_WDT_INT_ST_LP_WDT_INT_ST = 0x80000000 + + // INT_ENA: need_des + // Position of SUPER_WDT_INT_ENA field. + LP_WDT_INT_ENA_SUPER_WDT_INT_ENA_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_ENA field. + LP_WDT_INT_ENA_SUPER_WDT_INT_ENA_Msk = 0x40000000 + // Bit SUPER_WDT_INT_ENA. + LP_WDT_INT_ENA_SUPER_WDT_INT_ENA = 0x40000000 + // Position of LP_WDT_INT_ENA field. + LP_WDT_INT_ENA_LP_WDT_INT_ENA_Pos = 0x1f + // Bit mask of LP_WDT_INT_ENA field. + LP_WDT_INT_ENA_LP_WDT_INT_ENA_Msk = 0x80000000 + // Bit LP_WDT_INT_ENA. + LP_WDT_INT_ENA_LP_WDT_INT_ENA = 0x80000000 + + // INT_CLR: need_des + // Position of SUPER_WDT_INT_CLR field. + LP_WDT_INT_CLR_SUPER_WDT_INT_CLR_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_CLR field. + LP_WDT_INT_CLR_SUPER_WDT_INT_CLR_Msk = 0x40000000 + // Bit SUPER_WDT_INT_CLR. + LP_WDT_INT_CLR_SUPER_WDT_INT_CLR = 0x40000000 + // Position of LP_WDT_INT_CLR field. + LP_WDT_INT_CLR_LP_WDT_INT_CLR_Pos = 0x1f + // Bit mask of LP_WDT_INT_CLR field. + LP_WDT_INT_CLR_LP_WDT_INT_CLR_Msk = 0x80000000 + // Bit LP_WDT_INT_CLR. + LP_WDT_INT_CLR_LP_WDT_INT_CLR = 0x80000000 + + // DATE: need_des + // Position of LP_WDT_DATE field. + LP_WDT_DATE_LP_WDT_DATE_Pos = 0x0 + // Bit mask of LP_WDT_DATE field. + LP_WDT_DATE_LP_WDT_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_WDT_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_WDT_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_WDT_DATE_CLK_EN = 0x80000000 +) diff --git a/emb/device/esp/esp32h2.go b/emb/device/esp/esp32h2.go new file mode 100644 index 0000000..e565c86 --- /dev/null +++ b/emb/device/esp/esp32h2.go @@ -0,0 +1,79652 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32h2.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32h2 + +/* +// 32-bit RISC-V MCU & Bluetooth 5 (LE) & IEEE 802.15.4 +*/ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32-H2" + CPU = "RV32IMAC" + FPUPresent = false + NVICPrioBits = 0 +) + +// Interrupt numbers. +const ( + // PMU Peripheral + IRQ_PMU = 0 + + // eFuse Controller + IRQ_EFUSE = 1 + + // Low-power Timer + IRQ_LP_RTC_TIMER = 2 + + // Low-power Timer + IRQ_LP_BLE_TIMER = 3 + + // Low-power Watchdog Timer + IRQ_LP_WDT = 4 + + // LP_PERI Peripheral + IRQ_LP_PERI_TIMEOUT = 5 + + // Low-power Access Permission Management Controller + IRQ_LP_APM_M0 = 6 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR0 = 7 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR1 = 8 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR2 = 9 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR3 = 10 + + // Debug Assist + IRQ_ASSIST_DEBUG = 11 + + // RISC-V Trace Encoder + IRQ_TRACE = 12 + + // Interrupt Controller (Core 0) + IRQ_CACHE = 13 + + // Interrupt Controller (Core 0) + IRQ_CPU_PERI_TIMEOUT = 14 + + // Interrupt Controller (Core 0) + IRQ_BT_MAC = 15 + + // Interrupt Controller (Core 0) + IRQ_BT_BB = 16 + + // Interrupt Controller (Core 0) + IRQ_BT_BB_NMI = 17 + + // Interrupt Controller (Core 0) + IRQ_COEX = 18 + + // Interrupt Controller (Core 0) + IRQ_BLE_TIMER = 19 + + // Interrupt Controller (Core 0) + IRQ_BLE_SEC = 20 + + // Interrupt Controller (Core 0) + IRQ_ZB_MAC = 21 + + // General Purpose Input/Output + IRQ_GPIO = 22 + + // General Purpose Input/Output + IRQ_GPIO_NMI = 23 + + // PAU Peripheral + IRQ_PAU = 24 + + // High-Power System + IRQ_HP_PERI_TIMEOUT = 25 + + // HP_APM Peripheral + IRQ_HP_APM_M0 = 26 + + // HP_APM Peripheral + IRQ_HP_APM_M1 = 27 + + // HP_APM Peripheral + IRQ_HP_APM_M2 = 28 + + // HP_APM Peripheral + IRQ_HP_APM_M3 = 29 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_MSPI = 30 + + // I2S (Inter-IC Sound) Controller 0 + IRQ_I2S1 = 31 + + // Universal Host Controller Interface 0 + IRQ_UHCI0 = 32 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + IRQ_UART0 = 33 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + IRQ_UART1 = 34 + + // LED Control PWM (Pulse Width Modulation) + IRQ_LEDC = 35 + + // Two-Wire Automotive Interface + IRQ_TWAI0 = 36 + + // Full-speed USB Serial/JTAG Controller + IRQ_USB_DEVICE = 37 + + // Remote Control + IRQ_RMT = 38 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_EXT0 = 39 + + // I2C (Inter-Integrated Circuit) Controller 1 + IRQ_I2C_EXT1 = 40 + + // Timer Group 0 + IRQ_TG0_T0_LEVEL = 41 + + // Timer Group 0 + IRQ_TG0_WDT_LEVEL = 42 + + // Timer Group 1 + IRQ_TG1_T0_LEVEL = 43 + + // Timer Group 1 + IRQ_TG1_WDT_LEVEL = 44 + + // System Timer + IRQ_SYSTIMER_TARGET0 = 45 + + // System Timer + IRQ_SYSTIMER_TARGET1 = 46 + + // System Timer + IRQ_SYSTIMER_TARGET2 = 47 + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + IRQ_APB_ADC = 48 + + // Motor Control Pulse-Width Modulation 0 + IRQ_MCPWM0 = 49 + + // Pulse Count Controller + IRQ_PCNT = 50 + + // Parallel IO Controller + IRQ_PARL_IO_TX = 51 + + // Parallel IO Controller + IRQ_PARL_IO_RX = 52 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH0 = 53 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH1 = 54 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH2 = 55 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH0 = 56 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH1 = 57 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH2 = 58 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_GPSPI2 = 59 + + // AES (Advanced Encryption Standard) Accelerator + IRQ_AES = 60 + + // SHA (Secure Hash Algorithm) Accelerator + IRQ_SHA = 61 + + // RSA (Rivest Shamir Adleman) Accelerator + IRQ_RSA = 62 + + // ECC (ECC Hardware Accelerator) + IRQ_ECC = 63 + + // Interrupt Controller (Core 0) + IRQ_ECDSA = 64 + + // Highest interrupt number on this device. + IRQ_max = 64 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_PMU: + callHandlers(IRQ_PMU) + case IRQ_EFUSE: + callHandlers(IRQ_EFUSE) + case IRQ_LP_RTC_TIMER: + callHandlers(IRQ_LP_RTC_TIMER) + case IRQ_LP_BLE_TIMER: + callHandlers(IRQ_LP_BLE_TIMER) + case IRQ_LP_WDT: + callHandlers(IRQ_LP_WDT) + case IRQ_LP_PERI_TIMEOUT: + callHandlers(IRQ_LP_PERI_TIMEOUT) + case IRQ_LP_APM_M0: + callHandlers(IRQ_LP_APM_M0) + case IRQ_FROM_CPU_INTR0: + callHandlers(IRQ_FROM_CPU_INTR0) + case IRQ_FROM_CPU_INTR1: + callHandlers(IRQ_FROM_CPU_INTR1) + case IRQ_FROM_CPU_INTR2: + callHandlers(IRQ_FROM_CPU_INTR2) + case IRQ_FROM_CPU_INTR3: + callHandlers(IRQ_FROM_CPU_INTR3) + case IRQ_ASSIST_DEBUG: + callHandlers(IRQ_ASSIST_DEBUG) + case IRQ_TRACE: + callHandlers(IRQ_TRACE) + case IRQ_CACHE: + callHandlers(IRQ_CACHE) + case IRQ_CPU_PERI_TIMEOUT: + callHandlers(IRQ_CPU_PERI_TIMEOUT) + case IRQ_BT_MAC: + callHandlers(IRQ_BT_MAC) + case IRQ_BT_BB: + callHandlers(IRQ_BT_BB) + case IRQ_BT_BB_NMI: + callHandlers(IRQ_BT_BB_NMI) + case IRQ_COEX: + callHandlers(IRQ_COEX) + case IRQ_BLE_TIMER: + callHandlers(IRQ_BLE_TIMER) + case IRQ_BLE_SEC: + callHandlers(IRQ_BLE_SEC) + case IRQ_ZB_MAC: + callHandlers(IRQ_ZB_MAC) + case IRQ_GPIO: + callHandlers(IRQ_GPIO) + case IRQ_GPIO_NMI: + callHandlers(IRQ_GPIO_NMI) + case IRQ_PAU: + callHandlers(IRQ_PAU) + case IRQ_HP_PERI_TIMEOUT: + callHandlers(IRQ_HP_PERI_TIMEOUT) + case IRQ_HP_APM_M0: + callHandlers(IRQ_HP_APM_M0) + case IRQ_HP_APM_M1: + callHandlers(IRQ_HP_APM_M1) + case IRQ_HP_APM_M2: + callHandlers(IRQ_HP_APM_M2) + case IRQ_HP_APM_M3: + callHandlers(IRQ_HP_APM_M3) + case IRQ_MSPI: + callHandlers(IRQ_MSPI) + case IRQ_I2S1: + callHandlers(IRQ_I2S1) + case IRQ_UHCI0: + callHandlers(IRQ_UHCI0) + case IRQ_UART0: + callHandlers(IRQ_UART0) + case IRQ_UART1: + callHandlers(IRQ_UART1) + case IRQ_LEDC: + callHandlers(IRQ_LEDC) + case IRQ_TWAI0: + callHandlers(IRQ_TWAI0) + case IRQ_USB_DEVICE: + callHandlers(IRQ_USB_DEVICE) + case IRQ_RMT: + callHandlers(IRQ_RMT) + case IRQ_I2C_EXT0: + callHandlers(IRQ_I2C_EXT0) + case IRQ_I2C_EXT1: + callHandlers(IRQ_I2C_EXT1) + case IRQ_TG0_T0_LEVEL: + callHandlers(IRQ_TG0_T0_LEVEL) + case IRQ_TG0_WDT_LEVEL: + callHandlers(IRQ_TG0_WDT_LEVEL) + case IRQ_TG1_T0_LEVEL: + callHandlers(IRQ_TG1_T0_LEVEL) + case IRQ_TG1_WDT_LEVEL: + callHandlers(IRQ_TG1_WDT_LEVEL) + case IRQ_SYSTIMER_TARGET0: + callHandlers(IRQ_SYSTIMER_TARGET0) + case IRQ_SYSTIMER_TARGET1: + callHandlers(IRQ_SYSTIMER_TARGET1) + case IRQ_SYSTIMER_TARGET2: + callHandlers(IRQ_SYSTIMER_TARGET2) + case IRQ_APB_ADC: + callHandlers(IRQ_APB_ADC) + case IRQ_MCPWM0: + callHandlers(IRQ_MCPWM0) + case IRQ_PCNT: + callHandlers(IRQ_PCNT) + case IRQ_PARL_IO_TX: + callHandlers(IRQ_PARL_IO_TX) + case IRQ_PARL_IO_RX: + callHandlers(IRQ_PARL_IO_RX) + case IRQ_DMA_IN_CH0: + callHandlers(IRQ_DMA_IN_CH0) + case IRQ_DMA_IN_CH1: + callHandlers(IRQ_DMA_IN_CH1) + case IRQ_DMA_IN_CH2: + callHandlers(IRQ_DMA_IN_CH2) + case IRQ_DMA_OUT_CH0: + callHandlers(IRQ_DMA_OUT_CH0) + case IRQ_DMA_OUT_CH1: + callHandlers(IRQ_DMA_OUT_CH1) + case IRQ_DMA_OUT_CH2: + callHandlers(IRQ_DMA_OUT_CH2) + case IRQ_GPSPI2: + callHandlers(IRQ_GPSPI2) + case IRQ_AES: + callHandlers(IRQ_AES) + case IRQ_SHA: + callHandlers(IRQ_SHA) + case IRQ_RSA: + callHandlers(IRQ_RSA) + case IRQ_ECC: + callHandlers(IRQ_ECC) + case IRQ_ECDSA: + callHandlers(IRQ_ECDSA) + } +} + +// Peripherals. +var ( + // AES (Advanced Encryption Standard) Accelerator + AES = (*AES_Type)(unsafe.Pointer(uintptr(0x60088000))) + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + APB_SARADC = (*APB_SARADC_Type)(unsafe.Pointer(uintptr(0x6000e000))) + + // Debug Assist + ASSIST_DEBUG = (*ASSIST_DEBUG_Type)(unsafe.Pointer(uintptr(0x600c2000))) + + // DMA (Direct Memory Access) Controller + DMA = (*DMA_Type)(unsafe.Pointer(uintptr(0x60080000))) + + // Digital Signature + DS = (*DS_Type)(unsafe.Pointer(uintptr(0x6008c000))) + + // ECC (ECC Hardware Accelerator) + ECC = (*ECC_Type)(unsafe.Pointer(uintptr(0x6008b000))) + + // eFuse Controller + EFUSE = (*EFUSE_Type)(unsafe.Pointer(uintptr(0x600b0800))) + + // General Purpose Input/Output + GPIO = (*GPIO_Type)(unsafe.Pointer(uintptr(0x60091000))) + + // Sigma-Delta Modulation + GPIO_SD = (*GPIOSD_Type)(unsafe.Pointer(uintptr(0x60091f00))) + + // HMAC (Hash-based Message Authentication Code) Accelerator + HMAC = (*HMAC_Type)(unsafe.Pointer(uintptr(0x6008d000))) + + // HP_APM Peripheral + HP_APM = (*HP_APM_Type)(unsafe.Pointer(uintptr(0x60099000))) + + // High-Power System + HP_SYS = (*HP_SYS_Type)(unsafe.Pointer(uintptr(0x60095000))) + + // I2C (Inter-Integrated Circuit) Controller 0 + I2C0 = (*I2C_Type)(unsafe.Pointer(uintptr(0x60004000))) + + // I2S (Inter-IC Sound) Controller 0 + I2S0 = (*I2S_Type)(unsafe.Pointer(uintptr(0x6000d000))) + + // Interrupt Controller (Core 0) + INTERRUPT_CORE0 = (*INTMTX_CORE0_Type)(unsafe.Pointer(uintptr(0x60010000))) + + // INTPRI Peripheral + INTPRI = (*INTPRI_Type)(unsafe.Pointer(uintptr(0x600c5000))) + + // Input/Output Multiplexer + IO_MUX = (*IO_MUX_Type)(unsafe.Pointer(uintptr(0x60090000))) + + // LED Control PWM (Pulse Width Modulation) + LEDC = (*LEDC_Type)(unsafe.Pointer(uintptr(0x60008000))) + + // LP_PERI Peripheral + LP_PERI = (*LPPERI_Type)(unsafe.Pointer(uintptr(0x600b2800))) + + // LP_ANA Peripheral + LP_ANA = (*LP_ANA_Type)(unsafe.Pointer(uintptr(0x600b2c00))) + + // LP_AON Peripheral + LP_AON = (*LP_AON_Type)(unsafe.Pointer(uintptr(0x600b1000))) + + // Low-power Access Permission Management Controller + LP_APM = (*LP_APM_Type)(unsafe.Pointer(uintptr(0x600b3800))) + + // LP_CLKRST Peripheral + LP_CLKRST = (*LP_CLKRST_Type)(unsafe.Pointer(uintptr(0x600b0400))) + + // Low-power Timer + LP_TIMER = (*LP_TIMER_Type)(unsafe.Pointer(uintptr(0x600b0c00))) + + // Low-power Watchdog Timer + LP_WDT = (*LP_WDT_Type)(unsafe.Pointer(uintptr(0x600b1c00))) + + // Motor Control Pulse-Width Modulation 0 + MCPWM0 = (*MCPWM_Type)(unsafe.Pointer(uintptr(0x60014000))) + + // MEM_MONITOR Peripheral + MEM_MONITOR = (*MEM_MONITOR_Type)(unsafe.Pointer(uintptr(0x60092000))) + + // MODEM_LPCON Peripheral + MODEM_LPCON = (*MODEM_LPCON_Type)(unsafe.Pointer(uintptr(0x600ad000))) + + // MODEM_SYSCON Peripheral + MODEM_SYSCON = (*MODEM_SYSCON_Type)(unsafe.Pointer(uintptr(0x600a5400))) + + // OTP_DEBUG Peripheral + OTP_DEBUG = (*OTP_DEBUG_Type)(unsafe.Pointer(uintptr(0x600b3c00))) + + // Parallel IO Controller + PARL_IO = (*PARL_IO_Type)(unsafe.Pointer(uintptr(0x60015000))) + + // PAU Peripheral + PAU = (*PAU_Type)(unsafe.Pointer(uintptr(0x60093000))) + + // Pulse Count Controller + PCNT = (*PCNT_Type)(unsafe.Pointer(uintptr(0x60012000))) + + // PCR Peripheral + PCR = (*PCR_Type)(unsafe.Pointer(uintptr(0x60096000))) + + // PMU Peripheral + PMU = (*PMU_Type)(unsafe.Pointer(uintptr(0x600b0000))) + + // Remote Control + RMT = (*RMT_Type)(unsafe.Pointer(uintptr(0x60007000))) + + // Hardware Random Number Generator + RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x600b2800))) + + // RSA (Rivest Shamir Adleman) Accelerator + RSA = (*RSA_Type)(unsafe.Pointer(uintptr(0x6008a000))) + + // SHA (Secure Hash Algorithm) Accelerator + SHA = (*SHA_Type)(unsafe.Pointer(uintptr(0x60089000))) + + // Event Task Matrix + SOC_ETM = (*SOC_ETM_Type)(unsafe.Pointer(uintptr(0x60013000))) + + // SPI (Serial Peripheral Interface) Controller 0 + SPI0 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x60002000))) + + // SPI (Serial Peripheral Interface) Controller 1 + SPI1 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x60003000))) + + // SPI (Serial Peripheral Interface) Controller 2 + SPI2 = (*SPI2_Type)(unsafe.Pointer(uintptr(0x60081000))) + + // System Timer + SYSTIMER = (*SYSTIMER_Type)(unsafe.Pointer(uintptr(0x6000b000))) + + // TEE Peripheral + TEE = (*TEE_Type)(unsafe.Pointer(uintptr(0x60098000))) + + // Timer Group 0 + TIMG0 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x60009000))) + + // RISC-V Trace Encoder + TRACE = (*TRACE_Type)(unsafe.Pointer(uintptr(0x600c0000))) + + // Two-Wire Automotive Interface + TWAI0 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x6000c000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART0 = (*UART_Type)(unsafe.Pointer(uintptr(0x60000000))) + + // Universal Host Controller Interface 0 + UHCI0 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x60006000))) + + // Full-speed USB Serial/JTAG Controller + USB_DEVICE = (*USB_DEVICE_Type)(unsafe.Pointer(uintptr(0x6000f000))) + + // I2C (Inter-Integrated Circuit) Controller 1 + I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x60005000))) + + // Timer Group 1 + TIMG1 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x6000a000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + UART1 = (*UART_Type)(unsafe.Pointer(uintptr(0x60001000))) +) + +// AES (Advanced Encryption Standard) Accelerator +type AES_Type struct { + KEY_0 volatile.Register32 // 0x0 + KEY_1 volatile.Register32 // 0x4 + KEY_2 volatile.Register32 // 0x8 + KEY_3 volatile.Register32 // 0xC + KEY_4 volatile.Register32 // 0x10 + KEY_5 volatile.Register32 // 0x14 + KEY_6 volatile.Register32 // 0x18 + KEY_7 volatile.Register32 // 0x1C + TEXT_IN_0 volatile.Register32 // 0x20 + TEXT_IN_1 volatile.Register32 // 0x24 + TEXT_IN_2 volatile.Register32 // 0x28 + TEXT_IN_3 volatile.Register32 // 0x2C + TEXT_OUT_0 volatile.Register32 // 0x30 + TEXT_OUT_1 volatile.Register32 // 0x34 + TEXT_OUT_2 volatile.Register32 // 0x38 + TEXT_OUT_3 volatile.Register32 // 0x3C + MODE volatile.Register32 // 0x40 + ENDIAN volatile.Register32 // 0x44 + TRIGGER volatile.Register32 // 0x48 + STATE volatile.Register32 // 0x4C + IV_MEM [16]volatile.Register8 // 0x50 + H_MEM [16]volatile.Register8 // 0x60 + J0_MEM [16]volatile.Register8 // 0x70 + T0_MEM [16]volatile.Register8 // 0x80 + DMA_ENABLE volatile.Register32 // 0x90 + BLOCK_MODE volatile.Register32 // 0x94 + BLOCK_NUM volatile.Register32 // 0x98 + INC_SEL volatile.Register32 // 0x9C + AAD_BLOCK_NUM volatile.Register32 // 0xA0 + REMAINDER_BIT_NUM volatile.Register32 // 0xA4 + CONTINUE volatile.Register32 // 0xA8 + INT_CLEAR volatile.Register32 // 0xAC + INT_ENA volatile.Register32 // 0xB0 + DATE volatile.Register32 // 0xB4 + DMA_EXIT volatile.Register32 // 0xB8 +} + +// AES.KEY_0: Key material key_0 configure register +func (o *AES_Type) SetKEY_0(value uint32) { + volatile.StoreUint32(&o.KEY_0.Reg, value) +} +func (o *AES_Type) GetKEY_0() uint32 { + return volatile.LoadUint32(&o.KEY_0.Reg) +} + +// AES.KEY_1: Key material key_1 configure register +func (o *AES_Type) SetKEY_1(value uint32) { + volatile.StoreUint32(&o.KEY_1.Reg, value) +} +func (o *AES_Type) GetKEY_1() uint32 { + return volatile.LoadUint32(&o.KEY_1.Reg) +} + +// AES.KEY_2: Key material key_2 configure register +func (o *AES_Type) SetKEY_2(value uint32) { + volatile.StoreUint32(&o.KEY_2.Reg, value) +} +func (o *AES_Type) GetKEY_2() uint32 { + return volatile.LoadUint32(&o.KEY_2.Reg) +} + +// AES.KEY_3: Key material key_3 configure register +func (o *AES_Type) SetKEY_3(value uint32) { + volatile.StoreUint32(&o.KEY_3.Reg, value) +} +func (o *AES_Type) GetKEY_3() uint32 { + return volatile.LoadUint32(&o.KEY_3.Reg) +} + +// AES.KEY_4: Key material key_4 configure register +func (o *AES_Type) SetKEY_4(value uint32) { + volatile.StoreUint32(&o.KEY_4.Reg, value) +} +func (o *AES_Type) GetKEY_4() uint32 { + return volatile.LoadUint32(&o.KEY_4.Reg) +} + +// AES.KEY_5: Key material key_5 configure register +func (o *AES_Type) SetKEY_5(value uint32) { + volatile.StoreUint32(&o.KEY_5.Reg, value) +} +func (o *AES_Type) GetKEY_5() uint32 { + return volatile.LoadUint32(&o.KEY_5.Reg) +} + +// AES.KEY_6: Key material key_6 configure register +func (o *AES_Type) SetKEY_6(value uint32) { + volatile.StoreUint32(&o.KEY_6.Reg, value) +} +func (o *AES_Type) GetKEY_6() uint32 { + return volatile.LoadUint32(&o.KEY_6.Reg) +} + +// AES.KEY_7: Key material key_7 configure register +func (o *AES_Type) SetKEY_7(value uint32) { + volatile.StoreUint32(&o.KEY_7.Reg, value) +} +func (o *AES_Type) GetKEY_7() uint32 { + return volatile.LoadUint32(&o.KEY_7.Reg) +} + +// AES.TEXT_IN_0: source text material text_in_0 configure register +func (o *AES_Type) SetTEXT_IN_0(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_0.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_0() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_0.Reg) +} + +// AES.TEXT_IN_1: source text material text_in_1 configure register +func (o *AES_Type) SetTEXT_IN_1(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_1.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_1() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_1.Reg) +} + +// AES.TEXT_IN_2: source text material text_in_2 configure register +func (o *AES_Type) SetTEXT_IN_2(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_2.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_2() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_2.Reg) +} + +// AES.TEXT_IN_3: source text material text_in_3 configure register +func (o *AES_Type) SetTEXT_IN_3(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_3.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_3() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_3.Reg) +} + +// AES.TEXT_OUT_0: result text material text_out_0 configure register +func (o *AES_Type) SetTEXT_OUT_0(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_0.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_0() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_0.Reg) +} + +// AES.TEXT_OUT_1: result text material text_out_1 configure register +func (o *AES_Type) SetTEXT_OUT_1(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_1.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_1() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_1.Reg) +} + +// AES.TEXT_OUT_2: result text material text_out_2 configure register +func (o *AES_Type) SetTEXT_OUT_2(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_2.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_2() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_2.Reg) +} + +// AES.TEXT_OUT_3: result text material text_out_3 configure register +func (o *AES_Type) SetTEXT_OUT_3(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_3.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_3() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_3.Reg) +} + +// AES.MODE: AES Mode register +func (o *AES_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// AES.ENDIAN: AES Endian configure register +func (o *AES_Type) SetENDIAN(value uint32) { + volatile.StoreUint32(&o.ENDIAN.Reg, volatile.LoadUint32(&o.ENDIAN.Reg)&^(0x3f)|value) +} +func (o *AES_Type) GetENDIAN() uint32 { + return volatile.LoadUint32(&o.ENDIAN.Reg) & 0x3f +} + +// AES.TRIGGER: AES trigger register +func (o *AES_Type) SetTRIGGER(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetTRIGGER() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} + +// AES.STATE: AES state register +func (o *AES_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *AES_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// AES.DMA_ENABLE: DMA-AES working mode register +func (o *AES_Type) SetDMA_ENABLE(value uint32) { + volatile.StoreUint32(&o.DMA_ENABLE.Reg, volatile.LoadUint32(&o.DMA_ENABLE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_ENABLE() uint32 { + return volatile.LoadUint32(&o.DMA_ENABLE.Reg) & 0x1 +} + +// AES.BLOCK_MODE: AES cipher block mode register +func (o *AES_Type) SetBLOCK_MODE(value uint32) { + volatile.StoreUint32(&o.BLOCK_MODE.Reg, volatile.LoadUint32(&o.BLOCK_MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetBLOCK_MODE() uint32 { + return volatile.LoadUint32(&o.BLOCK_MODE.Reg) & 0x7 +} + +// AES.BLOCK_NUM: AES block number register +func (o *AES_Type) SetBLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetBLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.BLOCK_NUM.Reg) +} + +// AES.INC_SEL: Standard incrementing function configure register +func (o *AES_Type) SetINC_SEL(value uint32) { + volatile.StoreUint32(&o.INC_SEL.Reg, volatile.LoadUint32(&o.INC_SEL.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINC_SEL() uint32 { + return volatile.LoadUint32(&o.INC_SEL.Reg) & 0x1 +} + +// AES.AAD_BLOCK_NUM: Additional Authential Data block number register +func (o *AES_Type) SetAAD_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.AAD_BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetAAD_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.AAD_BLOCK_NUM.Reg) +} + +// AES.REMAINDER_BIT_NUM: AES remainder bit number register +func (o *AES_Type) SetREMAINDER_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.REMAINDER_BIT_NUM.Reg, volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg)&^(0x7f)|value) +} +func (o *AES_Type) GetREMAINDER_BIT_NUM() uint32 { + return volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg) & 0x7f +} + +// AES.CONTINUE: AES continue register +func (o *AES_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetCONTINUE() uint32 { + return volatile.LoadUint32(&o.CONTINUE.Reg) & 0x1 +} + +// AES.INT_CLEAR: AES Interrupt clear register +func (o *AES_Type) SetINT_CLEAR(value uint32) { + volatile.StoreUint32(&o.INT_CLEAR.Reg, volatile.LoadUint32(&o.INT_CLEAR.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_CLEAR() uint32 { + return volatile.LoadUint32(&o.INT_CLEAR.Reg) & 0x1 +} + +// AES.INT_ENA: AES Interrupt enable register +func (o *AES_Type) SetINT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// AES.DATE: AES version control register +func (o *AES_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *AES_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// AES.DMA_EXIT: AES-DMA exit config +func (o *AES_Type) SetDMA_EXIT(value uint32) { + volatile.StoreUint32(&o.DMA_EXIT.Reg, volatile.LoadUint32(&o.DMA_EXIT.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_EXIT() uint32 { + return volatile.LoadUint32(&o.DMA_EXIT.Reg) & 0x1 +} + +// SAR (Successive Approximation Register) Analog-to-Digital Converter +type APB_SARADC_Type struct { + CTRL volatile.Register32 // 0x0 + CTRL2 volatile.Register32 // 0x4 + FILTER_CTRL1 volatile.Register32 // 0x8 + FSM_WAIT volatile.Register32 // 0xC + SAR1_STATUS volatile.Register32 // 0x10 + SAR2_STATUS volatile.Register32 // 0x14 + SAR_PATT_TAB1 volatile.Register32 // 0x18 + SAR_PATT_TAB2 volatile.Register32 // 0x1C + ONETIME_SAMPLE volatile.Register32 // 0x20 + ARB_CTRL volatile.Register32 // 0x24 + FILTER_CTRL0 volatile.Register32 // 0x28 + SAR1DATA_STATUS volatile.Register32 // 0x2C + SAR2DATA_STATUS volatile.Register32 // 0x30 + THRES0_CTRL volatile.Register32 // 0x34 + THRES1_CTRL volatile.Register32 // 0x38 + THRES_CTRL volatile.Register32 // 0x3C + INT_ENA volatile.Register32 // 0x40 + INT_RAW volatile.Register32 // 0x44 + INT_ST volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + DMA_CONF volatile.Register32 // 0x50 + CLKM_CONF volatile.Register32 // 0x54 + APB_TSENS_CTRL volatile.Register32 // 0x58 + TSENS_CTRL2 volatile.Register32 // 0x5C + CALI volatile.Register32 // 0x60 + APB_TSENS_WAKE volatile.Register32 // 0x64 + APB_TSENS_SAMPLE volatile.Register32 // 0x68 + _ [912]byte + CTRL_DATE volatile.Register32 // 0x3FC +} + +// APB_SARADC.CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetCTRL_SARADC_START_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START_FORCE() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x7f80)|value<<7) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x7f80) >> 7 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x38000)|value<<15) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x38000) >> 15 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_XPD_SAR_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x18000000)|value<<27) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_XPD_SAR_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x18000000) >> 27 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC2_PWDET_DRV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC2_PWDET_DRV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc0000000) >> 30 +} + +// APB_SARADC.CTRL2: digital saradc configure register +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MEAS_NUM_LIMIT(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MEAS_NUM_LIMIT() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MAX_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1fe)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MAX_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1fe) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR1_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR1_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x200) >> 9 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR2_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR2_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x400) >> 10 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff000)|value<<12) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_TARGET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff000) >> 12 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1000000) >> 24 +} + +// APB_SARADC.FILTER_CTRL1: digital saradc configure register +func (o *APB_SARADC_Type) SetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0x1c000000)|value<<26) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0x1c000000) >> 26 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0xe0000000)|value<<29) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_APB_SARADC_FILTER_FACTOR0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0xe0000000) >> 29 +} + +// APB_SARADC.FSM_WAIT: digital saradc configure register +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff00)|value<<8) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff00) >> 8 +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff0000)|value<<16) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff0000) >> 16 +} + +// APB_SARADC.SAR1_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR1_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR1_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR1_STATUS.Reg) +} + +// APB_SARADC.SAR2_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR2_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR2_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR2_STATUS.Reg) +} + +// APB_SARADC.SAR_PATT_TAB1: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR_PATT_TAB1_SARADC_SAR_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR_PATT_TAB1.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR_PATT_TAB1_SARADC_SAR_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR_PATT_TAB1.Reg) & 0xffffff +} + +// APB_SARADC.SAR_PATT_TAB2: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR_PATT_TAB2_SARADC_SAR_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR_PATT_TAB2.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR_PATT_TAB2_SARADC_SAR_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR_PATT_TAB2.Reg) & 0xffffff +} + +// APB_SARADC.ONETIME_SAMPLE: digital saradc configure register +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_ATTEN(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x1800000)|value<<23) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_ATTEN() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x1800000) >> 23 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x1e000000)|value<<25) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x1e000000) >> 25 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC_ONETIME_START(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC_ONETIME_START() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE(value uint32) { + volatile.StoreUint32(&o.ONETIME_SAMPLE.Reg, volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.ONETIME_SAMPLE.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.ARB_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x4) >> 2 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x8) >> 3 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x10) >> 4 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_GRANT_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_GRANT_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x20) >> 5 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc0)|value<<6) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc0) >> 6 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x300)|value<<8) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x300) >> 8 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc00)|value<<10) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc00) >> 10 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_FIX_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_FIX_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x1000) >> 12 +} + +// APB_SARADC.FILTER_CTRL0: digital saradc configure register +func (o *APB_SARADC_Type) SetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x3c0000)|value<<18) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x3c0000) >> 18 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x3c00000) >> 22 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_APB_SARADC_FILTER_RESET(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_APB_SARADC_FILTER_RESET() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.SAR1DATA_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR1DATA_STATUS_APB_SARADC1_DATA(value uint32) { + volatile.StoreUint32(&o.SAR1DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR1DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetSAR1DATA_STATUS_APB_SARADC1_DATA() uint32 { + return volatile.LoadUint32(&o.SAR1DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.SAR2DATA_STATUS: digital saradc configure register +func (o *APB_SARADC_Type) SetSAR2DATA_STATUS_APB_SARADC2_DATA(value uint32) { + volatile.StoreUint32(&o.SAR2DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR2DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetSAR2DATA_STATUS_APB_SARADC2_DATA() uint32 { + return volatile.LoadUint32(&o.SAR2DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.THRES0_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetTHRES0_CTRL_APB_SARADC_THRES0_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0xf)|value) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_APB_SARADC_THRES0_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0xf +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_APB_SARADC_THRES0_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_APB_SARADC_THRES0_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_APB_SARADC_THRES0_LOW(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_APB_SARADC_THRES0_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES1_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetTHRES1_CTRL_APB_SARADC_THRES1_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0xf)|value) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_APB_SARADC_THRES1_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0xf +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_APB_SARADC_THRES1_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_APB_SARADC_THRES1_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_APB_SARADC_THRES1_LOW(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_APB_SARADC_THRES1_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES_CTRL: digital saradc configure register +func (o *APB_SARADC_Type) SetTHRES_CTRL_APB_SARADC_THRES_ALL_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_APB_SARADC_THRES_ALL_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_APB_SARADC_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_APB_SARADC_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_APB_SARADC_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_APB_SARADC_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ENA: digital saradc int register +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_TSENS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_TSENS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES1_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES1_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES0_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES0_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC2_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC2_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC1_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC1_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_RAW: digital saradc int register +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_TSENS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_TSENS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES1_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES1_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES0_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES0_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC2_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC2_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC1_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC1_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ST: digital saradc int register +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_TSENS_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_TSENS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES1_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES1_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES0_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES0_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES1_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES1_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC_THRES0_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC_THRES0_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC2_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC2_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC1_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC1_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_CLR: digital saradc int register +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_TSENS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_TSENS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES1_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES1_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES0_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES0_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC2_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC2_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC1_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC1_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.DMA_CONF: digital saradc configure register +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0xffff)|value) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0xffff +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_RESET_FSM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_RESET_FSM() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_TRANS(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_TRANS() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.CLKM_CONF: digital saradc configure register +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x3f00) >> 8 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xfc000) >> 14 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x100000) >> 20 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x600000)|value<<21) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x600000) >> 21 +} + +// APB_SARADC.APB_TSENS_CTRL: digital tsens configure register +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_OUT(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_OUT() uint32 { + return volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_IN_INV(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_IN_INV() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x2000) >> 13 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_CTRL_TSENS_PU(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_CTRL.Reg, volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_CTRL_TSENS_PU() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_CTRL.Reg) & 0x400000) >> 22 +} + +// APB_SARADC.TSENS_CTRL2: digital tsens configure register +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0xfff)|value) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0xfff +} +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0x3000)|value<<12) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0x3000) >> 12 +} +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_CLK_INV(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *APB_SARADC_Type) SetTSENS_CTRL2_TSENS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TSENS_CTRL2.Reg, volatile.LoadUint32(&o.TSENS_CTRL2.Reg)&^(0x8000)|value<<15) +} +func (o *APB_SARADC_Type) GetTSENS_CTRL2_TSENS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TSENS_CTRL2.Reg) & 0x8000) >> 15 +} + +// APB_SARADC.CALI: digital saradc configure register +func (o *APB_SARADC_Type) SetCALI_APB_SARADC_CALI_CFG(value uint32) { + volatile.StoreUint32(&o.CALI.Reg, volatile.LoadUint32(&o.CALI.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetCALI_APB_SARADC_CALI_CFG() uint32 { + return volatile.LoadUint32(&o.CALI.Reg) & 0x1ffff +} + +// APB_SARADC.APB_TSENS_WAKE: digital tsens configure register +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_TH_LOW(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_TH_LOW() uint32 { + return volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_TH_HIGH(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0xff00)|value<<8) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_TH_HIGH() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0xff00) >> 8 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0x10000)|value<<16) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0x10000) >> 16 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_MODE(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0x20000)|value<<17) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_MODE() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0x20000) >> 17 +} +func (o *APB_SARADC_Type) SetAPB_TSENS_WAKE_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_WAKE.Reg, volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg)&^(0x40000)|value<<18) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_WAKE_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_WAKE.Reg) & 0x40000) >> 18 +} + +// APB_SARADC.APB_TSENS_SAMPLE: digital tsens configure register +func (o *APB_SARADC_Type) SetAPB_TSENS_SAMPLE_TSENS_SAMPLE_RATE(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_SAMPLE.Reg, volatile.LoadUint32(&o.APB_TSENS_SAMPLE.Reg)&^(0xffff)|value) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_SAMPLE_TSENS_SAMPLE_RATE() uint32 { + return volatile.LoadUint32(&o.APB_TSENS_SAMPLE.Reg) & 0xffff +} +func (o *APB_SARADC_Type) SetAPB_TSENS_SAMPLE_TSENS_SAMPLE_EN(value uint32) { + volatile.StoreUint32(&o.APB_TSENS_SAMPLE.Reg, volatile.LoadUint32(&o.APB_TSENS_SAMPLE.Reg)&^(0x10000)|value<<16) +} +func (o *APB_SARADC_Type) GetAPB_TSENS_SAMPLE_TSENS_SAMPLE_EN() uint32 { + return (volatile.LoadUint32(&o.APB_TSENS_SAMPLE.Reg) & 0x10000) >> 16 +} + +// APB_SARADC.CTRL_DATE: version +func (o *APB_SARADC_Type) SetCTRL_DATE(value uint32) { + volatile.StoreUint32(&o.CTRL_DATE.Reg, value) +} +func (o *APB_SARADC_Type) GetCTRL_DATE() uint32 { + return volatile.LoadUint32(&o.CTRL_DATE.Reg) +} + +// Debug Assist +type ASSIST_DEBUG_Type struct { + CORE_0_MONTR_ENA volatile.Register32 // 0x0 + CORE_0_INTR_RAW volatile.Register32 // 0x4 + CORE_0_INTR_ENA volatile.Register32 // 0x8 + CORE_0_INTR_CLR volatile.Register32 // 0xC + CORE_0_AREA_DRAM0_0_MIN volatile.Register32 // 0x10 + CORE_0_AREA_DRAM0_0_MAX volatile.Register32 // 0x14 + CORE_0_AREA_DRAM0_1_MIN volatile.Register32 // 0x18 + CORE_0_AREA_DRAM0_1_MAX volatile.Register32 // 0x1C + CORE_0_AREA_PIF_0_MIN volatile.Register32 // 0x20 + CORE_0_AREA_PIF_0_MAX volatile.Register32 // 0x24 + CORE_0_AREA_PIF_1_MIN volatile.Register32 // 0x28 + CORE_0_AREA_PIF_1_MAX volatile.Register32 // 0x2C + CORE_0_AREA_PC volatile.Register32 // 0x30 + CORE_0_AREA_SP volatile.Register32 // 0x34 + CORE_0_SP_MIN volatile.Register32 // 0x38 + CORE_0_SP_MAX volatile.Register32 // 0x3C + CORE_0_SP_PC volatile.Register32 // 0x40 + CORE_0_RCD_EN volatile.Register32 // 0x44 + CORE_0_RCD_PDEBUGPC volatile.Register32 // 0x48 + CORE_0_RCD_PDEBUGSP volatile.Register32 // 0x4C + CORE_0_IRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x50 + CORE_0_IRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x54 + CORE_0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x58 + CORE_0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x5C + CORE_0_DRAM0_EXCEPTION_MONITOR_2 volatile.Register32 // 0x60 + CORE_0_DRAM0_EXCEPTION_MONITOR_3 volatile.Register32 // 0x64 + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x68 + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x6C + C0RE_0_LASTPC_BEFORE_EXCEPTION volatile.Register32 // 0x70 + C0RE_0_DEBUG_MODE volatile.Register32 // 0x74 + CLOCK_GATE volatile.Register32 // 0x78 + _ [896]byte + DATE volatile.Register32 // 0x3FC +} + +// ASSIST_DEBUG.CORE_0_MONTR_ENA: core0 monitor enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_RAW: core0 monitor interrupt status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_ENA: core0 monitor interrupt enable register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_CLR: core0 monitor interrupt clr register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MIN: core0 dram0 region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MAX: core0 dram0 region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MIN: core0 dram0 region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MAX: core0 dram0 region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MIN: core0 PIF region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MAX: core0 PIF region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MIN: core0 PIF region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MAX: core0 PIF region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PC: core0 area pc status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PC.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_SP: core0 area sp status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_SP(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_SP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_SP() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_SP.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_MIN: stack min value +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_MAX: stack max value +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_PC: stack monitor pc status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_PC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_EN: record enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGPC: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGPC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGPC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGSP: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGSP(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGSP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGSP() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGSP.Reg) +} + +// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0 +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1 +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1e000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1e000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg) +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)&^(0x1e000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) & 0x1e000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_3() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg) +} + +// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register6 +func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xfffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0xfffff +} + +// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register7 +func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xfffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xfffff +} + +// ASSIST_DEBUG.C0RE_0_LASTPC_BEFORE_EXCEPTION: cpu status register +func (o *ASSIST_DEBUG_Type) SetC0RE_0_LASTPC_BEFORE_EXCEPTION(value uint32) { + volatile.StoreUint32(&o.C0RE_0_LASTPC_BEFORE_EXCEPTION.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetC0RE_0_LASTPC_BEFORE_EXCEPTION() uint32 { + return volatile.LoadUint32(&o.C0RE_0_LASTPC_BEFORE_EXCEPTION.Reg) +} + +// ASSIST_DEBUG.C0RE_0_DEBUG_MODE: cpu status register +func (o *ASSIST_DEBUG_Type) SetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE(value uint32) { + volatile.StoreUint32(&o.C0RE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE() uint32 { + return volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE(value uint32) { + volatile.StoreUint32(&o.C0RE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetC0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.C0RE_0_DEBUG_MODE.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CLOCK_GATE: clock register +func (o *ASSIST_DEBUG_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// ASSIST_DEBUG.DATE: version register +func (o *ASSIST_DEBUG_Type) SetDATE_ASSIST_DEBUG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetDATE_ASSIST_DEBUG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// DMA (Direct Memory Access) Controller +type DMA_Type struct { + IN_INT_RAW_CH0 volatile.Register32 // 0x0 + IN_INT_ST_CH0 volatile.Register32 // 0x4 + IN_INT_ENA_CH0 volatile.Register32 // 0x8 + IN_INT_CLR_CH0 volatile.Register32 // 0xC + IN_INT_RAW_CH1 volatile.Register32 // 0x10 + IN_INT_ST_CH1 volatile.Register32 // 0x14 + IN_INT_ENA_CH1 volatile.Register32 // 0x18 + IN_INT_CLR_CH1 volatile.Register32 // 0x1C + IN_INT_RAW_CH2 volatile.Register32 // 0x20 + IN_INT_ST_CH2 volatile.Register32 // 0x24 + IN_INT_ENA_CH2 volatile.Register32 // 0x28 + IN_INT_CLR_CH2 volatile.Register32 // 0x2C + OUT_INT_RAW_CH0 volatile.Register32 // 0x30 + OUT_INT_ST_CH0 volatile.Register32 // 0x34 + OUT_INT_ENA_CH0 volatile.Register32 // 0x38 + OUT_INT_CLR_CH0 volatile.Register32 // 0x3C + OUT_INT_RAW_CH1 volatile.Register32 // 0x40 + OUT_INT_ST_CH1 volatile.Register32 // 0x44 + OUT_INT_ENA_CH1 volatile.Register32 // 0x48 + OUT_INT_CLR_CH1 volatile.Register32 // 0x4C + OUT_INT_RAW_CH2 volatile.Register32 // 0x50 + OUT_INT_ST_CH2 volatile.Register32 // 0x54 + OUT_INT_ENA_CH2 volatile.Register32 // 0x58 + OUT_INT_CLR_CH2 volatile.Register32 // 0x5C + AHB_TEST volatile.Register32 // 0x60 + MISC_CONF volatile.Register32 // 0x64 + DATE volatile.Register32 // 0x68 + _ [4]byte + IN_CONF0_CH0 volatile.Register32 // 0x70 + IN_CONF1_CH0 volatile.Register32 // 0x74 + INFIFO_STATUS_CH0 volatile.Register32 // 0x78 + IN_POP_CH0 volatile.Register32 // 0x7C + IN_LINK_CH0 volatile.Register32 // 0x80 + IN_STATE_CH0 volatile.Register32 // 0x84 + IN_SUC_EOF_DES_ADDR_CH0 volatile.Register32 // 0x88 + IN_ERR_EOF_DES_ADDR_CH0 volatile.Register32 // 0x8C + IN_DSCR_CH0 volatile.Register32 // 0x90 + IN_DSCR_BF0_CH0 volatile.Register32 // 0x94 + IN_DSCR_BF1_CH0 volatile.Register32 // 0x98 + IN_PRI_CH0 volatile.Register32 // 0x9C + IN_PERI_SEL_CH0 volatile.Register32 // 0xA0 + _ [48]byte + OUT_CONF1_CH0 volatile.Register32 // 0xD4 + OUTFIFO_STATUS_CH0 volatile.Register32 // 0xD8 + OUT_PUSH_CH0 volatile.Register32 // 0xDC + OUT_LINK_CH0 volatile.Register32 // 0xE0 + OUT_STATE_CH0 volatile.Register32 // 0xE4 + OUT_EOF_DES_ADDR_CH0 volatile.Register32 // 0xE8 + OUT_EOF_BFR_DES_ADDR_CH0 volatile.Register32 // 0xEC + OUT_DSCR_CH0 volatile.Register32 // 0xF0 + OUT_DSCR_BF0_CH0 volatile.Register32 // 0xF4 + OUT_DSCR_BF1_CH0 volatile.Register32 // 0xF8 + OUT_PRI_CH0 volatile.Register32 // 0xFC + OUT_PERI_SEL_CH0 volatile.Register32 // 0x100 + _ [44]byte + IN_CONF0_CH1 volatile.Register32 // 0x130 + IN_CONF1_CH1 volatile.Register32 // 0x134 + INFIFO_STATUS_CH1 volatile.Register32 // 0x138 + IN_POP_CH1 volatile.Register32 // 0x13C + IN_LINK_CH1 volatile.Register32 // 0x140 + IN_STATE_CH1 volatile.Register32 // 0x144 + IN_SUC_EOF_DES_ADDR_CH1 volatile.Register32 // 0x148 + IN_ERR_EOF_DES_ADDR_CH1 volatile.Register32 // 0x14C + IN_DSCR_CH1 volatile.Register32 // 0x150 + IN_DSCR_BF0_CH1 volatile.Register32 // 0x154 + IN_DSCR_BF1_CH1 volatile.Register32 // 0x158 + IN_PRI_CH1 volatile.Register32 // 0x15C + IN_PERI_SEL_CH1 volatile.Register32 // 0x160 + _ [44]byte + OUT_CONF0_CH0 volatile.Register32 // 0x190 + OUT_CONF1_CH1 volatile.Register32 // 0x194 + OUTFIFO_STATUS_CH1 volatile.Register32 // 0x198 + OUT_PUSH_CH1 volatile.Register32 // 0x19C + OUT_LINK_CH1 volatile.Register32 // 0x1A0 + OUT_STATE_CH1 volatile.Register32 // 0x1A4 + OUT_EOF_DES_ADDR_CH1 volatile.Register32 // 0x1A8 + OUT_EOF_BFR_DES_ADDR_CH1 volatile.Register32 // 0x1AC + OUT_DSCR_CH1 volatile.Register32 // 0x1B0 + OUT_DSCR_BF0_CH1 volatile.Register32 // 0x1B4 + OUT_DSCR_BF1_CH1 volatile.Register32 // 0x1B8 + OUT_PRI_CH1 volatile.Register32 // 0x1BC + OUT_PERI_SEL_CH1 volatile.Register32 // 0x1C0 + _ [44]byte + IN_CONF0_CH2 volatile.Register32 // 0x1F0 + IN_CONF1_CH2 volatile.Register32 // 0x1F4 + INFIFO_STATUS_CH2 volatile.Register32 // 0x1F8 + IN_POP_CH2 volatile.Register32 // 0x1FC + IN_LINK_CH2 volatile.Register32 // 0x200 + IN_STATE_CH2 volatile.Register32 // 0x204 + IN_SUC_EOF_DES_ADDR_CH2 volatile.Register32 // 0x208 + IN_ERR_EOF_DES_ADDR_CH2 volatile.Register32 // 0x20C + IN_DSCR_CH2 volatile.Register32 // 0x210 + IN_DSCR_BF0_CH2 volatile.Register32 // 0x214 + IN_DSCR_BF1_CH2 volatile.Register32 // 0x218 + IN_PRI_CH2 volatile.Register32 // 0x21C + IN_PERI_SEL_CH2 volatile.Register32 // 0x220 + _ [44]byte + OUT_CONF0_CH1 volatile.Register32 // 0x250 + OUT_CONF1_CH2 volatile.Register32 // 0x254 + OUTFIFO_STATUS_CH2 volatile.Register32 // 0x258 + OUT_PUSH_CH2 volatile.Register32 // 0x25C + OUT_LINK_CH2 volatile.Register32 // 0x260 + OUT_STATE_CH2 volatile.Register32 // 0x264 + OUT_EOF_DES_ADDR_CH2 volatile.Register32 // 0x268 + OUT_EOF_BFR_DES_ADDR_CH2 volatile.Register32 // 0x26C + OUT_DSCR_CH2 volatile.Register32 // 0x270 + OUT_DSCR_BF0_CH2 volatile.Register32 // 0x274 + OUT_DSCR_BF1_CH2 volatile.Register32 // 0x278 + OUT_PRI_CH2 volatile.Register32 // 0x27C + OUT_PERI_SEL_CH2 volatile.Register32 // 0x280 + _ [140]byte + OUT_CONF0_CH2 volatile.Register32 // 0x310 +} + +// DMA.IN_INT_RAW_CH0: Raw status interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ST_CH0: Masked interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ENA_CH0: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_CLR_CH0: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_RAW_CH1: Raw status interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ST_CH1: Masked interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ENA_CH1: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_CLR_CH1: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_RAW_CH2: Raw status interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ST_CH2: Masked interrupt of channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_ENA_CH2: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x40) >> 6 +} + +// DMA.IN_INT_CLR_CH2: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x40) >> 6 +} + +// DMA.OUT_INT_RAW_CH0: Raw status interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ST_CH0: Masked interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ENA_CH0: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_CLR_CH0: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_RAW_CH1: Raw status interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ST_CH1: Masked interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ENA_CH1: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_CLR_CH1: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_RAW_CH2: Raw status interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ST_CH2: Masked interrupt of channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_ENA_CH2: Interrupt enable bits of channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x20) >> 5 +} + +// DMA.OUT_INT_CLR_CH2: Interrupt clear bits of channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x20) >> 5 +} + +// DMA.AHB_TEST: reserved +func (o *DMA_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *DMA_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// DMA.MISC_CONF: MISC register +func (o *DMA_Type) SetMISC_CONF_AHBM_RST_INTER(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetMISC_CONF_AHBM_RST_INTER() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} +func (o *DMA_Type) SetMISC_CONF_ARB_PRI_DIS(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetMISC_CONF_ARB_PRI_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetMISC_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x8) >> 3 +} + +// DMA.DATE: Version control register +func (o *DMA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *DMA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// DMA.IN_CONF0_CH0: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH0_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH0_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH0_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_ETM_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x20) >> 5 +} + +// DMA.IN_CONF1_CH0: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH0_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH0_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH0: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH0: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg) +} + +// DMA.IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg) +} + +// DMA.IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg) +} + +// DMA.IN_PRI_CH0: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH0_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH0_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH0_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH0_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg) & 0x3f +} + +// DMA.OUT_CONF1_CH0: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH0_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH0_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH0: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH0: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg) +} + +// DMA.OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg) +} + +// DMA.OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg) +} + +// DMA.OUT_PRI_CH0: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH0_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH0_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH0_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH0_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH1: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH1_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH1_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH1_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_ETM_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x20) >> 5 +} + +// DMA.IN_CONF1_CH1: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH1_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH1_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH1: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH1: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH1_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH1_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH1_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH1_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH1: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH1: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH1_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH1_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH1: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH1: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.IN_DSCR_CH1: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg) +} + +// DMA.IN_DSCR_BF0_CH1: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg) +} + +// DMA.IN_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg) +} + +// DMA.IN_PRI_CH1: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH1_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH1_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH1: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH1_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH1_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH0: Configure 0 register of Tx channel 1 +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_ETM_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x40) >> 6 +} + +// DMA.OUT_CONF1_CH1: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH1_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH1_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH1: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH1: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH1: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH1: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH1_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH1: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH1: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg) +} + +// DMA.OUT_DSCR_CH1: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg) +} + +// DMA.OUT_DSCR_BF0_CH1: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg) +} + +// DMA.OUT_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg) +} + +// DMA.OUT_PRI_CH1: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH1_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH1_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH1: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH1_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH1_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH2: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH2_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH2_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH2_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_ETM_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x20) >> 5 +} + +// DMA.IN_CONF1_CH2: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH2_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH2_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.INFIFO_STATUS_CH2: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27 +} + +// DMA.IN_POP_CH2: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH2_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH2_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH2_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH2_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH2: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH2: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH2_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH2_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH2: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH2: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.IN_DSCR_CH2: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg) +} + +// DMA.IN_DSCR_BF0_CH2: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg) +} + +// DMA.IN_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg) +} + +// DMA.IN_PRI_CH2: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH2_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH2_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH2: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH2_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH2_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH1: Configure 0 register of Tx channel 1 +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_ETM_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x40) >> 6 +} + +// DMA.OUT_CONF1_CH2: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH2_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH2_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.OUTFIFO_STATUS_CH2: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH2: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH2: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH2: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH2_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH2: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH2: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg) +} + +// DMA.OUT_DSCR_CH2: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg) +} + +// DMA.OUT_DSCR_BF0_CH2: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg) +} + +// DMA.OUT_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg) +} + +// DMA.OUT_PRI_CH2: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH2_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH2_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH2: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH2_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH2_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH2: Configure 0 register of Tx channel 1 +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_ETM_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x40) >> 6 +} + +// Digital Signature +type DS_Type struct { + Y_MEM [512]volatile.Register8 // 0x0 + M_MEM [512]volatile.Register8 // 0x200 + RB_MEM [512]volatile.Register8 // 0x400 + BOX_MEM [48]volatile.Register8 // 0x600 + IV_MEM [16]volatile.Register8 // 0x630 + _ [448]byte + X_MEM [512]volatile.Register8 // 0x800 + Z_MEM [512]volatile.Register8 // 0xA00 + _ [512]byte + SET_START volatile.Register32 // 0xE00 + SET_CONTINUE volatile.Register32 // 0xE04 + SET_FINISH volatile.Register32 // 0xE08 + QUERY_BUSY volatile.Register32 // 0xE0C + QUERY_KEY_WRONG volatile.Register32 // 0xE10 + QUERY_CHECK volatile.Register32 // 0xE14 + _ [8]byte + DATE volatile.Register32 // 0xE20 +} + +// DS.SET_START: DS start control register +func (o *DS_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// DS.SET_CONTINUE: DS continue control register +func (o *DS_Type) SetSET_CONTINUE(value uint32) { + volatile.StoreUint32(&o.SET_CONTINUE.Reg, volatile.LoadUint32(&o.SET_CONTINUE.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_CONTINUE() uint32 { + return volatile.LoadUint32(&o.SET_CONTINUE.Reg) & 0x1 +} + +// DS.SET_FINISH: DS finish control register +func (o *DS_Type) SetSET_FINISH(value uint32) { + volatile.StoreUint32(&o.SET_FINISH.Reg, volatile.LoadUint32(&o.SET_FINISH.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_FINISH() uint32 { + return volatile.LoadUint32(&o.SET_FINISH.Reg) & 0x1 +} + +// DS.QUERY_BUSY: DS query busy register +func (o *DS_Type) SetQUERY_BUSY(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_BUSY() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// DS.QUERY_KEY_WRONG: DS query key-wrong counter register +func (o *DS_Type) SetQUERY_KEY_WRONG(value uint32) { + volatile.StoreUint32(&o.QUERY_KEY_WRONG.Reg, volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg)&^(0xf)|value) +} +func (o *DS_Type) GetQUERY_KEY_WRONG() uint32 { + return volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg) & 0xf +} + +// DS.QUERY_CHECK: DS query check result register +func (o *DS_Type) SetQUERY_CHECK_MD_ERROR(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_CHECK_MD_ERROR() uint32 { + return volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x1 +} +func (o *DS_Type) SetQUERY_CHECK_PADDING_BAD(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x2)|value<<1) +} +func (o *DS_Type) GetQUERY_CHECK_PADDING_BAD() uint32 { + return (volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x2) >> 1 +} + +// DS.DATE: DS version control register +func (o *DS_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *DS_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// ECC (ECC Hardware Accelerator) +type ECC_Type struct { + _ [12]byte + MULT_INT_RAW volatile.Register32 // 0xC + MULT_INT_ST volatile.Register32 // 0x10 + MULT_INT_ENA volatile.Register32 // 0x14 + MULT_INT_CLR volatile.Register32 // 0x18 + MULT_CONF volatile.Register32 // 0x1C + _ [220]byte + MULT_DATE volatile.Register32 // 0xFC + K_MEM [32]volatile.Register8 // 0x100 + PX_MEM [32]volatile.Register8 // 0x120 + PY_MEM [32]volatile.Register8 // 0x140 + QX_MEM0 volatile.Register8 // 0x160 + QX_MEM1 volatile.Register8 // 0x161 + QX_MEM2 volatile.Register8 // 0x162 + QX_MEM3 volatile.Register8 // 0x163 + QX_MEM4 volatile.Register8 // 0x164 + QX_MEM5 volatile.Register8 // 0x165 + QX_MEM6 volatile.Register8 // 0x166 + QX_MEM7 volatile.Register8 // 0x167 + QX_MEM8 volatile.Register8 // 0x168 + QX_MEM9 volatile.Register8 // 0x169 + QX_MEM10 volatile.Register8 // 0x16A + QX_MEM11 volatile.Register8 // 0x16B + QX_MEM12 volatile.Register8 // 0x16C + QX_MEM13 volatile.Register8 // 0x16D + QX_MEM14 volatile.Register8 // 0x16E + QX_MEM15 volatile.Register8 // 0x16F + QX_MEM16 volatile.Register8 // 0x170 + QX_MEM17 volatile.Register8 // 0x171 + QX_MEM18 volatile.Register8 // 0x172 + QX_MEM19 volatile.Register8 // 0x173 + QX_MEM20 volatile.Register8 // 0x174 + QX_MEM21 volatile.Register8 // 0x175 + QX_MEM22 volatile.Register8 // 0x176 + QX_MEM23 volatile.Register8 // 0x177 + QX_MEM24 volatile.Register8 // 0x178 + QX_MEM25 volatile.Register8 // 0x179 + QX_MEM26 volatile.Register8 // 0x17A + QX_MEM27 volatile.Register8 // 0x17B + QX_MEM28 volatile.Register8 // 0x17C + QX_MEM29 volatile.Register8 // 0x17D + QX_MEM30 volatile.Register8 // 0x17E + QX_MEM31 volatile.Register8 // 0x17F + QY_MEM0 volatile.Register8 // 0x180 + QY_MEM1 volatile.Register8 // 0x181 + QY_MEM2 volatile.Register8 // 0x182 + QY_MEM3 volatile.Register8 // 0x183 + QY_MEM4 volatile.Register8 // 0x184 + QY_MEM5 volatile.Register8 // 0x185 + QY_MEM6 volatile.Register8 // 0x186 + QY_MEM7 volatile.Register8 // 0x187 + QY_MEM8 volatile.Register8 // 0x188 + QY_MEM9 volatile.Register8 // 0x189 + QY_MEM10 volatile.Register8 // 0x18A + QY_MEM11 volatile.Register8 // 0x18B + QY_MEM12 volatile.Register8 // 0x18C + QY_MEM13 volatile.Register8 // 0x18D + QY_MEM14 volatile.Register8 // 0x18E + QY_MEM15 volatile.Register8 // 0x18F + QY_MEM16 volatile.Register8 // 0x190 + QY_MEM17 volatile.Register8 // 0x191 + QY_MEM18 volatile.Register8 // 0x192 + QY_MEM19 volatile.Register8 // 0x193 + QY_MEM20 volatile.Register8 // 0x194 + QY_MEM21 volatile.Register8 // 0x195 + QY_MEM22 volatile.Register8 // 0x196 + QY_MEM23 volatile.Register8 // 0x197 + QY_MEM24 volatile.Register8 // 0x198 + QY_MEM25 volatile.Register8 // 0x199 + QY_MEM26 volatile.Register8 // 0x19A + QY_MEM27 volatile.Register8 // 0x19B + QY_MEM28 volatile.Register8 // 0x19C + QY_MEM29 volatile.Register8 // 0x19D + QY_MEM30 volatile.Register8 // 0x19E + QY_MEM31 volatile.Register8 // 0x19F + QZ_MEM0 volatile.Register8 // 0x1A0 + QZ_MEM1 volatile.Register8 // 0x1A1 + QZ_MEM2 volatile.Register8 // 0x1A2 + QZ_MEM3 volatile.Register8 // 0x1A3 + QZ_MEM4 volatile.Register8 // 0x1A4 + QZ_MEM5 volatile.Register8 // 0x1A5 + QZ_MEM6 volatile.Register8 // 0x1A6 + QZ_MEM7 volatile.Register8 // 0x1A7 + QZ_MEM8 volatile.Register8 // 0x1A8 + QZ_MEM9 volatile.Register8 // 0x1A9 + QZ_MEM10 volatile.Register8 // 0x1AA + QZ_MEM11 volatile.Register8 // 0x1AB + QZ_MEM12 volatile.Register8 // 0x1AC + QZ_MEM13 volatile.Register8 // 0x1AD + QZ_MEM14 volatile.Register8 // 0x1AE + QZ_MEM15 volatile.Register8 // 0x1AF + QZ_MEM16 volatile.Register8 // 0x1B0 + QZ_MEM17 volatile.Register8 // 0x1B1 + QZ_MEM18 volatile.Register8 // 0x1B2 + QZ_MEM19 volatile.Register8 // 0x1B3 + QZ_MEM20 volatile.Register8 // 0x1B4 + QZ_MEM21 volatile.Register8 // 0x1B5 + QZ_MEM22 volatile.Register8 // 0x1B6 + QZ_MEM23 volatile.Register8 // 0x1B7 + QZ_MEM24 volatile.Register8 // 0x1B8 + QZ_MEM25 volatile.Register8 // 0x1B9 + QZ_MEM26 volatile.Register8 // 0x1BA + QZ_MEM27 volatile.Register8 // 0x1BB + QZ_MEM28 volatile.Register8 // 0x1BC + QZ_MEM29 volatile.Register8 // 0x1BD + QZ_MEM30 volatile.Register8 // 0x1BE + QZ_MEM31 volatile.Register8 // 0x1BF +} + +// ECC.MULT_INT_RAW: ECC interrupt raw register, valid in level. +func (o *ECC_Type) SetMULT_INT_RAW_CALC_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.MULT_INT_RAW.Reg, volatile.LoadUint32(&o.MULT_INT_RAW.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_RAW_CALC_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.MULT_INT_RAW.Reg) & 0x1 +} + +// ECC.MULT_INT_ST: ECC interrupt status register. +func (o *ECC_Type) SetMULT_INT_ST_CALC_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.MULT_INT_ST.Reg, volatile.LoadUint32(&o.MULT_INT_ST.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_ST_CALC_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.MULT_INT_ST.Reg) & 0x1 +} + +// ECC.MULT_INT_ENA: ECC interrupt enable register. +func (o *ECC_Type) SetMULT_INT_ENA_CALC_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.MULT_INT_ENA.Reg, volatile.LoadUint32(&o.MULT_INT_ENA.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_ENA_CALC_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.MULT_INT_ENA.Reg) & 0x1 +} + +// ECC.MULT_INT_CLR: ECC interrupt clear register. +func (o *ECC_Type) SetMULT_INT_CLR_CALC_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.MULT_INT_CLR.Reg, volatile.LoadUint32(&o.MULT_INT_CLR.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_CLR_CALC_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.MULT_INT_CLR.Reg) & 0x1 +} + +// ECC.MULT_CONF: ECC configure register +func (o *ECC_Type) SetMULT_CONF_START(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_CONF_START() uint32 { + return volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x1 +} +func (o *ECC_Type) SetMULT_CONF_RESET(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *ECC_Type) GetMULT_CONF_RESET() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x2) >> 1 +} +func (o *ECC_Type) SetMULT_CONF_KEY_LENGTH(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x4)|value<<2) +} +func (o *ECC_Type) GetMULT_CONF_KEY_LENGTH() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x4) >> 2 +} +func (o *ECC_Type) SetMULT_CONF_MOD_BASE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x8)|value<<3) +} +func (o *ECC_Type) GetMULT_CONF_MOD_BASE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x8) >> 3 +} +func (o *ECC_Type) SetMULT_CONF_WORK_MODE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *ECC_Type) GetMULT_CONF_WORK_MODE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0xf0) >> 4 +} +func (o *ECC_Type) SetMULT_CONF_SECURITY_MODE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x100)|value<<8) +} +func (o *ECC_Type) GetMULT_CONF_SECURITY_MODE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x100) >> 8 +} +func (o *ECC_Type) SetMULT_CONF_VERIFICATION_RESULT(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *ECC_Type) GetMULT_CONF_VERIFICATION_RESULT() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x20000000) >> 29 +} +func (o *ECC_Type) SetMULT_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *ECC_Type) GetMULT_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x40000000) >> 30 +} +func (o *ECC_Type) SetMULT_CONF_MEM_CLOCK_GATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *ECC_Type) GetMULT_CONF_MEM_CLOCK_GATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x80000000) >> 31 +} + +// ECC.MULT_DATE: Version control register +func (o *ECC_Type) SetMULT_DATE_DATE(value uint32) { + volatile.StoreUint32(&o.MULT_DATE.Reg, volatile.LoadUint32(&o.MULT_DATE.Reg)&^(0xfffffff)|value) +} +func (o *ECC_Type) GetMULT_DATE_DATE() uint32 { + return volatile.LoadUint32(&o.MULT_DATE.Reg) & 0xfffffff +} + +// eFuse Controller +type EFUSE_Type struct { + PGM_DATA0 volatile.Register32 // 0x0 + PGM_DATA1 volatile.Register32 // 0x4 + PGM_DATA2 volatile.Register32 // 0x8 + PGM_DATA3 volatile.Register32 // 0xC + PGM_DATA4 volatile.Register32 // 0x10 + PGM_DATA5 volatile.Register32 // 0x14 + PGM_DATA6 volatile.Register32 // 0x18 + PGM_DATA7 volatile.Register32 // 0x1C + PGM_CHECK_VALUE0 volatile.Register32 // 0x20 + PGM_CHECK_VALUE1 volatile.Register32 // 0x24 + PGM_CHECK_VALUE2 volatile.Register32 // 0x28 + RD_WR_DIS volatile.Register32 // 0x2C + RD_REPEAT_DATA0 volatile.Register32 // 0x30 + RD_REPEAT_DATA1 volatile.Register32 // 0x34 + RD_REPEAT_DATA2 volatile.Register32 // 0x38 + RD_REPEAT_DATA3 volatile.Register32 // 0x3C + RD_REPEAT_DATA4 volatile.Register32 // 0x40 + RD_MAC_SYS_0 volatile.Register32 // 0x44 + RD_MAC_SYS_1 volatile.Register32 // 0x48 + RD_MAC_SYS_2 volatile.Register32 // 0x4C + RD_MAC_SYS_3 volatile.Register32 // 0x50 + RD_MAC_SYS_4 volatile.Register32 // 0x54 + RD_MAC_SYS_5 volatile.Register32 // 0x58 + RD_SYS_PART1_DATA0 volatile.Register32 // 0x5C + RD_SYS_PART1_DATA1 volatile.Register32 // 0x60 + RD_SYS_PART1_DATA2 volatile.Register32 // 0x64 + RD_SYS_PART1_DATA3 volatile.Register32 // 0x68 + RD_SYS_PART1_DATA4 volatile.Register32 // 0x6C + RD_SYS_PART1_DATA5 volatile.Register32 // 0x70 + RD_SYS_PART1_DATA6 volatile.Register32 // 0x74 + RD_SYS_PART1_DATA7 volatile.Register32 // 0x78 + RD_USR_DATA0 volatile.Register32 // 0x7C + RD_USR_DATA1 volatile.Register32 // 0x80 + RD_USR_DATA2 volatile.Register32 // 0x84 + RD_USR_DATA3 volatile.Register32 // 0x88 + RD_USR_DATA4 volatile.Register32 // 0x8C + RD_USR_DATA5 volatile.Register32 // 0x90 + RD_USR_DATA6 volatile.Register32 // 0x94 + RD_USR_DATA7 volatile.Register32 // 0x98 + RD_KEY0_DATA0 volatile.Register32 // 0x9C + RD_KEY0_DATA1 volatile.Register32 // 0xA0 + RD_KEY0_DATA2 volatile.Register32 // 0xA4 + RD_KEY0_DATA3 volatile.Register32 // 0xA8 + RD_KEY0_DATA4 volatile.Register32 // 0xAC + RD_KEY0_DATA5 volatile.Register32 // 0xB0 + RD_KEY0_DATA6 volatile.Register32 // 0xB4 + RD_KEY0_DATA7 volatile.Register32 // 0xB8 + RD_KEY1_DATA0 volatile.Register32 // 0xBC + RD_KEY1_DATA1 volatile.Register32 // 0xC0 + RD_KEY1_DATA2 volatile.Register32 // 0xC4 + RD_KEY1_DATA3 volatile.Register32 // 0xC8 + RD_KEY1_DATA4 volatile.Register32 // 0xCC + RD_KEY1_DATA5 volatile.Register32 // 0xD0 + RD_KEY1_DATA6 volatile.Register32 // 0xD4 + RD_KEY1_DATA7 volatile.Register32 // 0xD8 + RD_KEY2_DATA0 volatile.Register32 // 0xDC + RD_KEY2_DATA1 volatile.Register32 // 0xE0 + RD_KEY2_DATA2 volatile.Register32 // 0xE4 + RD_KEY2_DATA3 volatile.Register32 // 0xE8 + RD_KEY2_DATA4 volatile.Register32 // 0xEC + RD_KEY2_DATA5 volatile.Register32 // 0xF0 + RD_KEY2_DATA6 volatile.Register32 // 0xF4 + RD_KEY2_DATA7 volatile.Register32 // 0xF8 + RD_KEY3_DATA0 volatile.Register32 // 0xFC + RD_KEY3_DATA1 volatile.Register32 // 0x100 + RD_KEY3_DATA2 volatile.Register32 // 0x104 + RD_KEY3_DATA3 volatile.Register32 // 0x108 + RD_KEY3_DATA4 volatile.Register32 // 0x10C + RD_KEY3_DATA5 volatile.Register32 // 0x110 + RD_KEY3_DATA6 volatile.Register32 // 0x114 + RD_KEY3_DATA7 volatile.Register32 // 0x118 + RD_KEY4_DATA0 volatile.Register32 // 0x11C + RD_KEY4_DATA1 volatile.Register32 // 0x120 + RD_KEY4_DATA2 volatile.Register32 // 0x124 + RD_KEY4_DATA3 volatile.Register32 // 0x128 + RD_KEY4_DATA4 volatile.Register32 // 0x12C + RD_KEY4_DATA5 volatile.Register32 // 0x130 + RD_KEY4_DATA6 volatile.Register32 // 0x134 + RD_KEY4_DATA7 volatile.Register32 // 0x138 + RD_KEY5_DATA0 volatile.Register32 // 0x13C + RD_KEY5_DATA1 volatile.Register32 // 0x140 + RD_KEY5_DATA2 volatile.Register32 // 0x144 + RD_KEY5_DATA3 volatile.Register32 // 0x148 + RD_KEY5_DATA4 volatile.Register32 // 0x14C + RD_KEY5_DATA5 volatile.Register32 // 0x150 + RD_KEY5_DATA6 volatile.Register32 // 0x154 + RD_KEY5_DATA7 volatile.Register32 // 0x158 + RD_SYS_PART2_DATA0 volatile.Register32 // 0x15C + RD_SYS_PART2_DATA1 volatile.Register32 // 0x160 + RD_SYS_PART2_DATA2 volatile.Register32 // 0x164 + RD_SYS_PART2_DATA3 volatile.Register32 // 0x168 + RD_SYS_PART2_DATA4 volatile.Register32 // 0x16C + RD_SYS_PART2_DATA5 volatile.Register32 // 0x170 + RD_SYS_PART2_DATA6 volatile.Register32 // 0x174 + RD_SYS_PART2_DATA7 volatile.Register32 // 0x178 + RD_REPEAT_ERR0 volatile.Register32 // 0x17C + RD_REPEAT_ERR1 volatile.Register32 // 0x180 + RD_REPEAT_ERR2 volatile.Register32 // 0x184 + RD_REPEAT_ERR3 volatile.Register32 // 0x188 + RD_REPEAT_ERR4 volatile.Register32 // 0x18C + _ [48]byte + RD_RS_ERR0 volatile.Register32 // 0x1C0 + RD_RS_ERR1 volatile.Register32 // 0x1C4 + CLK volatile.Register32 // 0x1C8 + CONF volatile.Register32 // 0x1CC + STATUS volatile.Register32 // 0x1D0 + CMD volatile.Register32 // 0x1D4 + INT_RAW volatile.Register32 // 0x1D8 + INT_ST volatile.Register32 // 0x1DC + INT_ENA volatile.Register32 // 0x1E0 + INT_CLR volatile.Register32 // 0x1E4 + DAC_CONF volatile.Register32 // 0x1E8 + RD_TIM_CONF volatile.Register32 // 0x1EC + WR_TIM_CONF1 volatile.Register32 // 0x1F0 + WR_TIM_CONF2 volatile.Register32 // 0x1F4 + WR_TIM_CONF0_RS_BYPASS volatile.Register32 // 0x1F8 + DATE volatile.Register32 // 0x1FC +} + +// EFUSE.PGM_DATA0: Register 0 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA0(value uint32) { + volatile.StoreUint32(&o.PGM_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA0() uint32 { + return volatile.LoadUint32(&o.PGM_DATA0.Reg) +} + +// EFUSE.PGM_DATA1: Register 1 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA1(value uint32) { + volatile.StoreUint32(&o.PGM_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA1() uint32 { + return volatile.LoadUint32(&o.PGM_DATA1.Reg) +} + +// EFUSE.PGM_DATA2: Register 2 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA2(value uint32) { + volatile.StoreUint32(&o.PGM_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA2() uint32 { + return volatile.LoadUint32(&o.PGM_DATA2.Reg) +} + +// EFUSE.PGM_DATA3: Register 3 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA3(value uint32) { + volatile.StoreUint32(&o.PGM_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA3() uint32 { + return volatile.LoadUint32(&o.PGM_DATA3.Reg) +} + +// EFUSE.PGM_DATA4: Register 4 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA4(value uint32) { + volatile.StoreUint32(&o.PGM_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA4() uint32 { + return volatile.LoadUint32(&o.PGM_DATA4.Reg) +} + +// EFUSE.PGM_DATA5: Register 5 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA5(value uint32) { + volatile.StoreUint32(&o.PGM_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA5() uint32 { + return volatile.LoadUint32(&o.PGM_DATA5.Reg) +} + +// EFUSE.PGM_DATA6: Register 6 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA6(value uint32) { + volatile.StoreUint32(&o.PGM_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA6() uint32 { + return volatile.LoadUint32(&o.PGM_DATA6.Reg) +} + +// EFUSE.PGM_DATA7: Register 7 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA7(value uint32) { + volatile.StoreUint32(&o.PGM_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA7() uint32 { + return volatile.LoadUint32(&o.PGM_DATA7.Reg) +} + +// EFUSE.PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE0(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE0() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE0.Reg) +} + +// EFUSE.PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE1(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE1() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE1.Reg) +} + +// EFUSE.PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE2(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE2() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE2.Reg) +} + +// EFUSE.RD_WR_DIS: BLOCK0 data register 0. +func (o *EFUSE_Type) SetRD_WR_DIS(value uint32) { + volatile.StoreUint32(&o.RD_WR_DIS.Reg, value) +} +func (o *EFUSE_Type) GetRD_WR_DIS() uint32 { + return volatile.LoadUint32(&o.RD_WR_DIS.Reg) +} + +// EFUSE.RD_REPEAT_DATA0: BLOCK0 data register 1. +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RD_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RD_DIS() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED0_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED0_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_POWERGLITCH_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_POWERGLITCH_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_CAN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_CAN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_JTAG_SEL_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_JTAG_SEL_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SOFT_DIS_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SOFT_DIS_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_PAD_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_PAD_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_VDD_SPI_AS_GPIO(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_VDD_SPI_AS_GPIO() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED0_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED0_2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED0_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED0_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED0_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED0_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_DATA1: BLOCK0 data register 2. +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_RPT4_RESERVED1_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_RPT4_RESERVED1_1() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_WDT_DELAY_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_WDT_DELAY_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA2: BLOCK0 data register 3. +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_2() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SEC_DPA_LEVEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SEC_DPA_LEVEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_ECDSA_FORCE_USE_HARDWARE_K(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_ECDSA_FORCE_USE_HARDWARE_K() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_CRYPT_DPA_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_CRYPT_DPA_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_RPT4_RESERVED2_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xfc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_RPT4_RESERVED2_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xfc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_TPUW(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_TPUW() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA3: BLOCK0 data register 4. +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DIRECT_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DIRECT_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_PRINT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_PRINT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED3_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED3_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CONTROL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CONTROL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FORCE_SEND_RESUME(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FORCE_SEND_RESUME() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_VERSION(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1fffe00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_VERSION() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1fffe00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_HYS_EN_PAD0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xfc000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_HYS_EN_PAD0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xfc000000) >> 26 +} + +// EFUSE.RD_REPEAT_DATA4: BLOCK0 data register 5. +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_HYS_EN_PAD1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x3fffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_HYS_EN_PAD1() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x3fffff +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_RPT4_RESERVED4_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_RPT4_RESERVED4_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_RPT4_RESERVED4_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_RPT4_RESERVED4_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xff000000) >> 24 +} + +// EFUSE.RD_MAC_SYS_0: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_0.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_0() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_0.Reg) +} + +// EFUSE.RD_MAC_SYS_1: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_1_MAC_1(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_1_MAC_1() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_MAC_SYS_1_MAC_EXT(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_1_MAC_EXT() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.RD_MAC_SYS_2: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_2_MAC_RESERVED_1(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_2.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg)&^(0x3fff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_2_MAC_RESERVED_1() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg) & 0x3fff +} +func (o *EFUSE_Type) SetRD_MAC_SYS_2_MAC_RESERVED_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_2.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg)&^(0xffffc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_2_MAC_RESERVED_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg) & 0xffffc000) >> 14 +} + +// EFUSE.RD_MAC_SYS_3: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_3_MAC_RESERVED_2(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg)&^(0x3ffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_3_MAC_RESERVED_2() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg) & 0x3ffff +} +func (o *EFUSE_Type) SetRD_MAC_SYS_3_SYS_DATA_PART0_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg)&^(0xfffc0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_3_SYS_DATA_PART0_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg) & 0xfffc0000) >> 18 +} + +// EFUSE.RD_MAC_SYS_4: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_4(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_4.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_4() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_4.Reg) +} + +// EFUSE.RD_MAC_SYS_5: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_5(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_5.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_5() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA0: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA1: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA2: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA3: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA4: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA5: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA6: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA7: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA7.Reg) +} + +// EFUSE.RD_USR_DATA0: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA0.Reg) +} + +// EFUSE.RD_USR_DATA1: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA1.Reg) +} + +// EFUSE.RD_USR_DATA2: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA2.Reg) +} + +// EFUSE.RD_USR_DATA3: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA3.Reg) +} + +// EFUSE.RD_USR_DATA4: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA4.Reg) +} + +// EFUSE.RD_USR_DATA5: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA5.Reg) +} + +// EFUSE.RD_USR_DATA6: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA6.Reg) +} + +// EFUSE.RD_USR_DATA7: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA7.Reg) +} + +// EFUSE.RD_KEY0_DATA0: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA0.Reg) +} + +// EFUSE.RD_KEY0_DATA1: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA1.Reg) +} + +// EFUSE.RD_KEY0_DATA2: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA2.Reg) +} + +// EFUSE.RD_KEY0_DATA3: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA3.Reg) +} + +// EFUSE.RD_KEY0_DATA4: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA4.Reg) +} + +// EFUSE.RD_KEY0_DATA5: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA5.Reg) +} + +// EFUSE.RD_KEY0_DATA6: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA6.Reg) +} + +// EFUSE.RD_KEY0_DATA7: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA7.Reg) +} + +// EFUSE.RD_KEY1_DATA0: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA0.Reg) +} + +// EFUSE.RD_KEY1_DATA1: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA1.Reg) +} + +// EFUSE.RD_KEY1_DATA2: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA2.Reg) +} + +// EFUSE.RD_KEY1_DATA3: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA3.Reg) +} + +// EFUSE.RD_KEY1_DATA4: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA4.Reg) +} + +// EFUSE.RD_KEY1_DATA5: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA5.Reg) +} + +// EFUSE.RD_KEY1_DATA6: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA6.Reg) +} + +// EFUSE.RD_KEY1_DATA7: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA7.Reg) +} + +// EFUSE.RD_KEY2_DATA0: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA0.Reg) +} + +// EFUSE.RD_KEY2_DATA1: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA1.Reg) +} + +// EFUSE.RD_KEY2_DATA2: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA2.Reg) +} + +// EFUSE.RD_KEY2_DATA3: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA3.Reg) +} + +// EFUSE.RD_KEY2_DATA4: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA4.Reg) +} + +// EFUSE.RD_KEY2_DATA5: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA5.Reg) +} + +// EFUSE.RD_KEY2_DATA6: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA6.Reg) +} + +// EFUSE.RD_KEY2_DATA7: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA7.Reg) +} + +// EFUSE.RD_KEY3_DATA0: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA0.Reg) +} + +// EFUSE.RD_KEY3_DATA1: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA1.Reg) +} + +// EFUSE.RD_KEY3_DATA2: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA2.Reg) +} + +// EFUSE.RD_KEY3_DATA3: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA3.Reg) +} + +// EFUSE.RD_KEY3_DATA4: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA4.Reg) +} + +// EFUSE.RD_KEY3_DATA5: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA5.Reg) +} + +// EFUSE.RD_KEY3_DATA6: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA6.Reg) +} + +// EFUSE.RD_KEY3_DATA7: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA7.Reg) +} + +// EFUSE.RD_KEY4_DATA0: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA0.Reg) +} + +// EFUSE.RD_KEY4_DATA1: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA1.Reg) +} + +// EFUSE.RD_KEY4_DATA2: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA2.Reg) +} + +// EFUSE.RD_KEY4_DATA3: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA3.Reg) +} + +// EFUSE.RD_KEY4_DATA4: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA4.Reg) +} + +// EFUSE.RD_KEY4_DATA5: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA5.Reg) +} + +// EFUSE.RD_KEY4_DATA6: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA6.Reg) +} + +// EFUSE.RD_KEY4_DATA7: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA7.Reg) +} + +// EFUSE.RD_KEY5_DATA0: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA0.Reg) +} + +// EFUSE.RD_KEY5_DATA1: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA1.Reg) +} + +// EFUSE.RD_KEY5_DATA2: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA2.Reg) +} + +// EFUSE.RD_KEY5_DATA3: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA3.Reg) +} + +// EFUSE.RD_KEY5_DATA4: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA4.Reg) +} + +// EFUSE.RD_KEY5_DATA5: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA5.Reg) +} + +// EFUSE.RD_KEY5_DATA6: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA6.Reg) +} + +// EFUSE.RD_KEY5_DATA7: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA7.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA0: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA1: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA2: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA3: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA4: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA5: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA6: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA7: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA7.Reg) +} + +// EFUSE.RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RD_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RD_DIS_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_POWERGLITCH_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_POWERGLITCH_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_TWAI_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_TWAI_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_RPT4_RESERVED1_ERR_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_RPT4_RESERVED1_ERR_0() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_RPT4_RESERVED2_ERR_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xfc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_RPT4_RESERVED2_ERR_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xfc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_TPUW_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_TPUW_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_USB_PRINT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_USB_PRINT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_VERSION_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1fffe00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_VERSION_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1fffe00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_HYS_EN_PAD0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xfc000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_HYS_EN_PAD0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xfc000000) >> 26 +} + +// EFUSE.RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_HYS_EN_PAD1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x3fffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_HYS_EN_PAD1_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x3fffff +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xff000000) >> 24 +} + +// EFUSE.RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700)|value<<8) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700) >> 8 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000)|value<<12) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000) >> 12 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700000)|value<<20) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700000) >> 20 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000000) >> 24 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000000) >> 27 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000000) >> 28 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000000)|value<<31) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000000) >> 31 +} + +// EFUSE.RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x80) >> 7 +} + +// EFUSE.CLK: eFuse clcok configuration register. +func (o *EFUSE_Type) SetCLK_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCLK_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCLK_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCLK_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCLK_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetCLK_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x10000) >> 16 +} + +// EFUSE.CONF: eFuse operation mode configuraiton register +func (o *EFUSE_Type) SetCONF_OP_CODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetCONF_OP_CODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0xffff +} +func (o *EFUSE_Type) SetCONF_CFG_ECDSA_BLK(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetCONF_CFG_ECDSA_BLK() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0xf0000) >> 16 +} + +// EFUSE.STATUS: eFuse status register. +func (o *EFUSE_Type) SetSTATUS_STATE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetSTATUS_STATE() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xf +} +func (o *EFUSE_Type) SetSTATUS_OTP_LOAD_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetSTATUS_OTP_LOAD_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_C_SYNC2(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_C_SYNC2() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetSTATUS_OTP_STROBE_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetSTATUS_OTP_STROBE_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetSTATUS_OTP_CSB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetSTATUS_OTP_CSB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetSTATUS_OTP_PGENB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetSTATUS_OTP_PGENB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_IS_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_IS_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetSTATUS_BLK0_VALID_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xffc00)|value<<10) +} +func (o *EFUSE_Type) GetSTATUS_BLK0_VALID_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xffc00) >> 10 +} +func (o *EFUSE_Type) SetSTATUS_CUR_ECDSA_BLK(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf00000)|value<<20) +} +func (o *EFUSE_Type) GetSTATUS_CUR_ECDSA_BLK() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf00000) >> 20 +} + +// EFUSE.CMD: eFuse command register. +func (o *EFUSE_Type) SetCMD_READ_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCMD_READ_CMD() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCMD_PGM_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCMD_PGM_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCMD_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3c)|value<<2) +} +func (o *EFUSE_Type) GetCMD_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x3c) >> 2 +} + +// EFUSE.INT_RAW: eFuse raw interrupt register. +func (o *EFUSE_Type) SetINT_RAW_READ_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_RAW_READ_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_RAW_PGM_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_RAW_PGM_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ST: eFuse interrupt status register. +func (o *EFUSE_Type) SetINT_ST_READ_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ST_READ_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ST_PGM_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ST_PGM_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ENA: eFuse interrupt enable register. +func (o *EFUSE_Type) SetINT_ENA_READ_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ENA_READ_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ENA_PGM_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ENA_PGM_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_CLR: eFuse interrupt clear register. +func (o *EFUSE_Type) SetINT_CLR_READ_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_CLR_READ_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_CLR_PGM_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_CLR_PGM_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// EFUSE.DAC_CONF: Controls the eFuse programming voltage. +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.DAC_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_PAD_SEL(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_PAD_SEL() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_NUM(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x1fe00)|value<<9) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_NUM() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x1fe00) >> 9 +} +func (o *EFUSE_Type) SetDAC_CONF_OE_CLR(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EFUSE_Type) GetDAC_CONF_OE_CLR() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x20000) >> 17 +} + +// EFUSE.RD_TIM_CONF: Configures read timing parameters. +func (o *EFUSE_Type) SetRD_TIM_CONF_THR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_THR_A() uint32 { + return volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TRD(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TRD() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff00) >> 8 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TSUR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TSUR_A() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff0000) >> 16 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_READ_INIT_NUM(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_READ_INIT_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF1_TSUP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_TSUP_A() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff +} +func (o *EFUSE_Type) SetWR_TIM_CONF1_PWR_ON_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xffff00)|value<<8) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_PWR_ON_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xffff00) >> 8 +} +func (o *EFUSE_Type) SetWR_TIM_CONF1_THP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_THP_A() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF2_PWR_OFF_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_PWR_OFF_NUM() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff +} +func (o *EFUSE_Type) SetWR_TIM_CONF2_TPGM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_TPGM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.WR_TIM_CONF0_RS_BYPASS: Configurarion register0 of eFuse programming time parameters and rs bypass operation. +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0xffe)|value<<1) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0xffe) >> 1 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_UPDATE(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_UPDATE() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1fe000)|value<<13) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1fe000) >> 13 +} + +// EFUSE.DATE: eFuse version register. +func (o *EFUSE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *EFUSE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// General Purpose Input/Output +type GPIO_Type struct { + BT_SELECT volatile.Register32 // 0x0 + OUT volatile.Register32 // 0x4 + OUT_W1TS volatile.Register32 // 0x8 + OUT_W1TC volatile.Register32 // 0xC + _ [12]byte + SDIO_SELECT volatile.Register32 // 0x1C + ENABLE volatile.Register32 // 0x20 + ENABLE_W1TS volatile.Register32 // 0x24 + ENABLE_W1TC volatile.Register32 // 0x28 + _ [12]byte + STRAP volatile.Register32 // 0x38 + IN volatile.Register32 // 0x3C + _ [4]byte + STATUS volatile.Register32 // 0x44 + STATUS_W1TS volatile.Register32 // 0x48 + STATUS_W1TC volatile.Register32 // 0x4C + _ [12]byte + PCPU_INT volatile.Register32 // 0x5C + PCPU_NMI_INT volatile.Register32 // 0x60 + CPUSDIO_INT volatile.Register32 // 0x64 + _ [12]byte + PIN0 volatile.Register32 // 0x74 + PIN1 volatile.Register32 // 0x78 + PIN2 volatile.Register32 // 0x7C + PIN3 volatile.Register32 // 0x80 + PIN4 volatile.Register32 // 0x84 + PIN5 volatile.Register32 // 0x88 + PIN6 volatile.Register32 // 0x8C + PIN7 volatile.Register32 // 0x90 + PIN8 volatile.Register32 // 0x94 + PIN9 volatile.Register32 // 0x98 + PIN10 volatile.Register32 // 0x9C + PIN11 volatile.Register32 // 0xA0 + PIN12 volatile.Register32 // 0xA4 + PIN13 volatile.Register32 // 0xA8 + PIN14 volatile.Register32 // 0xAC + PIN15 volatile.Register32 // 0xB0 + PIN16 volatile.Register32 // 0xB4 + PIN17 volatile.Register32 // 0xB8 + PIN18 volatile.Register32 // 0xBC + PIN19 volatile.Register32 // 0xC0 + PIN20 volatile.Register32 // 0xC4 + PIN21 volatile.Register32 // 0xC8 + PIN22 volatile.Register32 // 0xCC + PIN23 volatile.Register32 // 0xD0 + PIN24 volatile.Register32 // 0xD4 + PIN25 volatile.Register32 // 0xD8 + PIN26 volatile.Register32 // 0xDC + PIN27 volatile.Register32 // 0xE0 + PIN28 volatile.Register32 // 0xE4 + PIN29 volatile.Register32 // 0xE8 + PIN30 volatile.Register32 // 0xEC + PIN31 volatile.Register32 // 0xF0 + _ [88]byte + STATUS_NEXT volatile.Register32 // 0x14C + _ [4]byte + FUNC0_IN_SEL_CFG volatile.Register32 // 0x154 + FUNC1_IN_SEL_CFG volatile.Register32 // 0x158 + FUNC2_IN_SEL_CFG volatile.Register32 // 0x15C + FUNC3_IN_SEL_CFG volatile.Register32 // 0x160 + FUNC4_IN_SEL_CFG volatile.Register32 // 0x164 + FUNC5_IN_SEL_CFG volatile.Register32 // 0x168 + FUNC6_IN_SEL_CFG volatile.Register32 // 0x16C + FUNC7_IN_SEL_CFG volatile.Register32 // 0x170 + FUNC8_IN_SEL_CFG volatile.Register32 // 0x174 + FUNC9_IN_SEL_CFG volatile.Register32 // 0x178 + FUNC10_IN_SEL_CFG volatile.Register32 // 0x17C + FUNC11_IN_SEL_CFG volatile.Register32 // 0x180 + FUNC12_IN_SEL_CFG volatile.Register32 // 0x184 + FUNC13_IN_SEL_CFG volatile.Register32 // 0x188 + FUNC14_IN_SEL_CFG volatile.Register32 // 0x18C + FUNC15_IN_SEL_CFG volatile.Register32 // 0x190 + FUNC16_IN_SEL_CFG volatile.Register32 // 0x194 + FUNC17_IN_SEL_CFG volatile.Register32 // 0x198 + FUNC18_IN_SEL_CFG volatile.Register32 // 0x19C + FUNC19_IN_SEL_CFG volatile.Register32 // 0x1A0 + FUNC20_IN_SEL_CFG volatile.Register32 // 0x1A4 + FUNC21_IN_SEL_CFG volatile.Register32 // 0x1A8 + FUNC22_IN_SEL_CFG volatile.Register32 // 0x1AC + FUNC23_IN_SEL_CFG volatile.Register32 // 0x1B0 + FUNC24_IN_SEL_CFG volatile.Register32 // 0x1B4 + FUNC25_IN_SEL_CFG volatile.Register32 // 0x1B8 + FUNC26_IN_SEL_CFG volatile.Register32 // 0x1BC + FUNC27_IN_SEL_CFG volatile.Register32 // 0x1C0 + FUNC28_IN_SEL_CFG volatile.Register32 // 0x1C4 + FUNC29_IN_SEL_CFG volatile.Register32 // 0x1C8 + FUNC30_IN_SEL_CFG volatile.Register32 // 0x1CC + FUNC31_IN_SEL_CFG volatile.Register32 // 0x1D0 + FUNC32_IN_SEL_CFG volatile.Register32 // 0x1D4 + FUNC33_IN_SEL_CFG volatile.Register32 // 0x1D8 + FUNC34_IN_SEL_CFG volatile.Register32 // 0x1DC + FUNC35_IN_SEL_CFG volatile.Register32 // 0x1E0 + FUNC36_IN_SEL_CFG volatile.Register32 // 0x1E4 + FUNC37_IN_SEL_CFG volatile.Register32 // 0x1E8 + FUNC38_IN_SEL_CFG volatile.Register32 // 0x1EC + FUNC39_IN_SEL_CFG volatile.Register32 // 0x1F0 + FUNC40_IN_SEL_CFG volatile.Register32 // 0x1F4 + FUNC41_IN_SEL_CFG volatile.Register32 // 0x1F8 + FUNC42_IN_SEL_CFG volatile.Register32 // 0x1FC + FUNC43_IN_SEL_CFG volatile.Register32 // 0x200 + FUNC44_IN_SEL_CFG volatile.Register32 // 0x204 + FUNC45_IN_SEL_CFG volatile.Register32 // 0x208 + FUNC46_IN_SEL_CFG volatile.Register32 // 0x20C + FUNC47_IN_SEL_CFG volatile.Register32 // 0x210 + FUNC48_IN_SEL_CFG volatile.Register32 // 0x214 + FUNC49_IN_SEL_CFG volatile.Register32 // 0x218 + FUNC50_IN_SEL_CFG volatile.Register32 // 0x21C + FUNC51_IN_SEL_CFG volatile.Register32 // 0x220 + FUNC52_IN_SEL_CFG volatile.Register32 // 0x224 + FUNC53_IN_SEL_CFG volatile.Register32 // 0x228 + FUNC54_IN_SEL_CFG volatile.Register32 // 0x22C + FUNC55_IN_SEL_CFG volatile.Register32 // 0x230 + FUNC56_IN_SEL_CFG volatile.Register32 // 0x234 + FUNC57_IN_SEL_CFG volatile.Register32 // 0x238 + FUNC58_IN_SEL_CFG volatile.Register32 // 0x23C + FUNC59_IN_SEL_CFG volatile.Register32 // 0x240 + FUNC60_IN_SEL_CFG volatile.Register32 // 0x244 + FUNC61_IN_SEL_CFG volatile.Register32 // 0x248 + FUNC62_IN_SEL_CFG volatile.Register32 // 0x24C + FUNC63_IN_SEL_CFG volatile.Register32 // 0x250 + FUNC64_IN_SEL_CFG volatile.Register32 // 0x254 + FUNC65_IN_SEL_CFG volatile.Register32 // 0x258 + FUNC66_IN_SEL_CFG volatile.Register32 // 0x25C + FUNC67_IN_SEL_CFG volatile.Register32 // 0x260 + FUNC68_IN_SEL_CFG volatile.Register32 // 0x264 + FUNC69_IN_SEL_CFG volatile.Register32 // 0x268 + FUNC70_IN_SEL_CFG volatile.Register32 // 0x26C + FUNC71_IN_SEL_CFG volatile.Register32 // 0x270 + FUNC72_IN_SEL_CFG volatile.Register32 // 0x274 + FUNC73_IN_SEL_CFG volatile.Register32 // 0x278 + FUNC74_IN_SEL_CFG volatile.Register32 // 0x27C + FUNC75_IN_SEL_CFG volatile.Register32 // 0x280 + FUNC76_IN_SEL_CFG volatile.Register32 // 0x284 + FUNC77_IN_SEL_CFG volatile.Register32 // 0x288 + FUNC78_IN_SEL_CFG volatile.Register32 // 0x28C + FUNC79_IN_SEL_CFG volatile.Register32 // 0x290 + FUNC80_IN_SEL_CFG volatile.Register32 // 0x294 + FUNC81_IN_SEL_CFG volatile.Register32 // 0x298 + FUNC82_IN_SEL_CFG volatile.Register32 // 0x29C + FUNC83_IN_SEL_CFG volatile.Register32 // 0x2A0 + FUNC84_IN_SEL_CFG volatile.Register32 // 0x2A4 + FUNC85_IN_SEL_CFG volatile.Register32 // 0x2A8 + FUNC86_IN_SEL_CFG volatile.Register32 // 0x2AC + FUNC87_IN_SEL_CFG volatile.Register32 // 0x2B0 + FUNC88_IN_SEL_CFG volatile.Register32 // 0x2B4 + FUNC89_IN_SEL_CFG volatile.Register32 // 0x2B8 + FUNC90_IN_SEL_CFG volatile.Register32 // 0x2BC + FUNC91_IN_SEL_CFG volatile.Register32 // 0x2C0 + FUNC92_IN_SEL_CFG volatile.Register32 // 0x2C4 + FUNC93_IN_SEL_CFG volatile.Register32 // 0x2C8 + FUNC94_IN_SEL_CFG volatile.Register32 // 0x2CC + FUNC95_IN_SEL_CFG volatile.Register32 // 0x2D0 + FUNC96_IN_SEL_CFG volatile.Register32 // 0x2D4 + FUNC97_IN_SEL_CFG volatile.Register32 // 0x2D8 + FUNC98_IN_SEL_CFG volatile.Register32 // 0x2DC + FUNC99_IN_SEL_CFG volatile.Register32 // 0x2E0 + FUNC100_IN_SEL_CFG volatile.Register32 // 0x2E4 + FUNC101_IN_SEL_CFG volatile.Register32 // 0x2E8 + FUNC102_IN_SEL_CFG volatile.Register32 // 0x2EC + FUNC103_IN_SEL_CFG volatile.Register32 // 0x2F0 + FUNC104_IN_SEL_CFG volatile.Register32 // 0x2F4 + FUNC105_IN_SEL_CFG volatile.Register32 // 0x2F8 + FUNC106_IN_SEL_CFG volatile.Register32 // 0x2FC + FUNC107_IN_SEL_CFG volatile.Register32 // 0x300 + FUNC108_IN_SEL_CFG volatile.Register32 // 0x304 + FUNC109_IN_SEL_CFG volatile.Register32 // 0x308 + FUNC110_IN_SEL_CFG volatile.Register32 // 0x30C + FUNC111_IN_SEL_CFG volatile.Register32 // 0x310 + FUNC112_IN_SEL_CFG volatile.Register32 // 0x314 + FUNC113_IN_SEL_CFG volatile.Register32 // 0x318 + FUNC114_IN_SEL_CFG volatile.Register32 // 0x31C + FUNC115_IN_SEL_CFG volatile.Register32 // 0x320 + FUNC116_IN_SEL_CFG volatile.Register32 // 0x324 + FUNC117_IN_SEL_CFG volatile.Register32 // 0x328 + FUNC118_IN_SEL_CFG volatile.Register32 // 0x32C + FUNC119_IN_SEL_CFG volatile.Register32 // 0x330 + FUNC120_IN_SEL_CFG volatile.Register32 // 0x334 + FUNC121_IN_SEL_CFG volatile.Register32 // 0x338 + FUNC122_IN_SEL_CFG volatile.Register32 // 0x33C + FUNC123_IN_SEL_CFG volatile.Register32 // 0x340 + FUNC124_IN_SEL_CFG volatile.Register32 // 0x344 + FUNC125_IN_SEL_CFG volatile.Register32 // 0x348 + FUNC126_IN_SEL_CFG volatile.Register32 // 0x34C + FUNC127_IN_SEL_CFG volatile.Register32 // 0x350 + _ [512]byte + FUNC0_OUT_SEL_CFG volatile.Register32 // 0x554 + FUNC1_OUT_SEL_CFG volatile.Register32 // 0x558 + FUNC2_OUT_SEL_CFG volatile.Register32 // 0x55C + FUNC3_OUT_SEL_CFG volatile.Register32 // 0x560 + FUNC4_OUT_SEL_CFG volatile.Register32 // 0x564 + FUNC5_OUT_SEL_CFG volatile.Register32 // 0x568 + FUNC6_OUT_SEL_CFG volatile.Register32 // 0x56C + FUNC7_OUT_SEL_CFG volatile.Register32 // 0x570 + FUNC8_OUT_SEL_CFG volatile.Register32 // 0x574 + FUNC9_OUT_SEL_CFG volatile.Register32 // 0x578 + FUNC10_OUT_SEL_CFG volatile.Register32 // 0x57C + FUNC11_OUT_SEL_CFG volatile.Register32 // 0x580 + FUNC12_OUT_SEL_CFG volatile.Register32 // 0x584 + FUNC13_OUT_SEL_CFG volatile.Register32 // 0x588 + FUNC14_OUT_SEL_CFG volatile.Register32 // 0x58C + FUNC15_OUT_SEL_CFG volatile.Register32 // 0x590 + FUNC16_OUT_SEL_CFG volatile.Register32 // 0x594 + FUNC17_OUT_SEL_CFG volatile.Register32 // 0x598 + FUNC18_OUT_SEL_CFG volatile.Register32 // 0x59C + FUNC19_OUT_SEL_CFG volatile.Register32 // 0x5A0 + FUNC20_OUT_SEL_CFG volatile.Register32 // 0x5A4 + FUNC21_OUT_SEL_CFG volatile.Register32 // 0x5A8 + FUNC22_OUT_SEL_CFG volatile.Register32 // 0x5AC + FUNC23_OUT_SEL_CFG volatile.Register32 // 0x5B0 + FUNC24_OUT_SEL_CFG volatile.Register32 // 0x5B4 + FUNC25_OUT_SEL_CFG volatile.Register32 // 0x5B8 + FUNC26_OUT_SEL_CFG volatile.Register32 // 0x5BC + FUNC27_OUT_SEL_CFG volatile.Register32 // 0x5C0 + FUNC28_OUT_SEL_CFG volatile.Register32 // 0x5C4 + FUNC29_OUT_SEL_CFG volatile.Register32 // 0x5C8 + _ [96]byte + CLOCK_GATE volatile.Register32 // 0x62C + _ [204]byte + DATE volatile.Register32 // 0x6FC +} + +// GPIO.BT_SELECT: GPIO bit select register +func (o *GPIO_Type) SetBT_SELECT(value uint32) { + volatile.StoreUint32(&o.BT_SELECT.Reg, value) +} +func (o *GPIO_Type) GetBT_SELECT() uint32 { + return volatile.LoadUint32(&o.BT_SELECT.Reg) +} + +// GPIO.OUT: GPIO output register for GPIO0-31 +func (o *GPIO_Type) SetOUT(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, value) +} +func (o *GPIO_Type) GetOUT() uint32 { + return volatile.LoadUint32(&o.OUT.Reg) +} + +// GPIO.OUT_W1TS: GPIO output set register for GPIO0-31 +func (o *GPIO_Type) SetOUT_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_W1TS.Reg) +} + +// GPIO.OUT_W1TC: GPIO output clear register for GPIO0-31 +func (o *GPIO_Type) SetOUT_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_W1TC.Reg) +} + +// GPIO.SDIO_SELECT: GPIO sdio select register +func (o *GPIO_Type) SetSDIO_SELECT_SDIO_SEL(value uint32) { + volatile.StoreUint32(&o.SDIO_SELECT.Reg, volatile.LoadUint32(&o.SDIO_SELECT.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSDIO_SELECT_SDIO_SEL() uint32 { + return volatile.LoadUint32(&o.SDIO_SELECT.Reg) & 0xff +} + +// GPIO.ENABLE: GPIO output enable register for GPIO0-31 +func (o *GPIO_Type) SetENABLE(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, value) +} +func (o *GPIO_Type) GetENABLE() uint32 { + return volatile.LoadUint32(&o.ENABLE.Reg) +} + +// GPIO.ENABLE_W1TS: GPIO output enable set register for GPIO0-31 +func (o *GPIO_Type) SetENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) +} + +// GPIO.ENABLE_W1TC: GPIO output enable clear register for GPIO0-31 +func (o *GPIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) +} + +// GPIO.STRAP: pad strapping register +func (o *GPIO_Type) SetSTRAP_STRAPPING(value uint32) { + volatile.StoreUint32(&o.STRAP.Reg, volatile.LoadUint32(&o.STRAP.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetSTRAP_STRAPPING() uint32 { + return volatile.LoadUint32(&o.STRAP.Reg) & 0xffff +} + +// GPIO.IN: GPIO input register for GPIO0-31 +func (o *GPIO_Type) SetIN(value uint32) { + volatile.StoreUint32(&o.IN.Reg, value) +} +func (o *GPIO_Type) GetIN() uint32 { + return volatile.LoadUint32(&o.IN.Reg) +} + +// GPIO.STATUS: GPIO interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) +} + +// GPIO.STATUS_W1TS: GPIO interrupt status set register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) +} + +// GPIO.STATUS_W1TC: GPIO interrupt status clear register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) +} + +// GPIO.PCPU_INT: GPIO PRO_CPU interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetPCPU_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_INT.Reg) +} + +// GPIO.PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetPCPU_NMI_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT.Reg) +} + +// GPIO.CPUSDIO_INT: GPIO CPUSDIO interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetCPUSDIO_INT(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT.Reg, value) +} +func (o *GPIO_Type) GetCPUSDIO_INT() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT.Reg) +} + +// GPIO.PIN0: GPIO pin configuration register +func (o *GPIO_Type) SetPIN0_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN0_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN0_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN0_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN0_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN0_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN1: GPIO pin configuration register +func (o *GPIO_Type) SetPIN1_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN1_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN1_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN1_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN1_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN1_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN2: GPIO pin configuration register +func (o *GPIO_Type) SetPIN2_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN2_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN2_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN2_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN2_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN2_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN3: GPIO pin configuration register +func (o *GPIO_Type) SetPIN3_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN3_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN3_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN3_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN3_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN3_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN4: GPIO pin configuration register +func (o *GPIO_Type) SetPIN4_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN4_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN4_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN4_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN4_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN4_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN5: GPIO pin configuration register +func (o *GPIO_Type) SetPIN5_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN5_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN5_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN5_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN5_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN5_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN6: GPIO pin configuration register +func (o *GPIO_Type) SetPIN6_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN6_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN6_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN6_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN6_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN6_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN7: GPIO pin configuration register +func (o *GPIO_Type) SetPIN7_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN7_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN7_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN7_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN7_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN7_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN8: GPIO pin configuration register +func (o *GPIO_Type) SetPIN8_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN8_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN8.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN8_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN8_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN8_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN8_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN9: GPIO pin configuration register +func (o *GPIO_Type) SetPIN9_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN9_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN9.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN9_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN9_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN9_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN9_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN10: GPIO pin configuration register +func (o *GPIO_Type) SetPIN10_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN10_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN10.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN10_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN10_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN10_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN10_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN10_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN10_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN11: GPIO pin configuration register +func (o *GPIO_Type) SetPIN11_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN11_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN11.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN11_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN11_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN11_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN11_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN11_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN11_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN12: GPIO pin configuration register +func (o *GPIO_Type) SetPIN12_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN12_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN12.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN12_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN12_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN12_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN12_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN12_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN12_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN13: GPIO pin configuration register +func (o *GPIO_Type) SetPIN13_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN13_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN13.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN13_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN13_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN13_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN13_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN13_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN13_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN14: GPIO pin configuration register +func (o *GPIO_Type) SetPIN14_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN14_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN14.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN14_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN14_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN14_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN14_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN14_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN14_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN15: GPIO pin configuration register +func (o *GPIO_Type) SetPIN15_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN15_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN15.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN15_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN15_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN15_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN15_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN15_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN15_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN16: GPIO pin configuration register +func (o *GPIO_Type) SetPIN16_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN16_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN16.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN16_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN16_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN16_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN16_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN16_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN16_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN17: GPIO pin configuration register +func (o *GPIO_Type) SetPIN17_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN17_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN17.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN17_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN17_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN17_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN17_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN17_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN17_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN18: GPIO pin configuration register +func (o *GPIO_Type) SetPIN18_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN18_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN18.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN18_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN18_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN18_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN18_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN18_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN18_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN19: GPIO pin configuration register +func (o *GPIO_Type) SetPIN19_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN19_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN19.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN19_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN19_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN19_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN19_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN19_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN19_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN20: GPIO pin configuration register +func (o *GPIO_Type) SetPIN20_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN20_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN20.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN20_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN20_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN20_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN20_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN20_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN20_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN21: GPIO pin configuration register +func (o *GPIO_Type) SetPIN21_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN21_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN21.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN21_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN21_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN21_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN21_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN21_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN21_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN22: GPIO pin configuration register +func (o *GPIO_Type) SetPIN22_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN22_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN22.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN22_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN22_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN22_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN22_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN22_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN22_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN22_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN22_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN22_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN22_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN22_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN22_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN23: GPIO pin configuration register +func (o *GPIO_Type) SetPIN23_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN23_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN23.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN23_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN23_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN23_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN23_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN23_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN23_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN23_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN23_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN23_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN23_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN23_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN23_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN24: GPIO pin configuration register +func (o *GPIO_Type) SetPIN24_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN24_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN24.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN24_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN24_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN24_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN24_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN24_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN24_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN24_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN24_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN24_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN24_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN24_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN24_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN25: GPIO pin configuration register +func (o *GPIO_Type) SetPIN25_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN25_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN25.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN25_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN25_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN25_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN25_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN25_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN25_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN25_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN25_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN25_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN25_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN25_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN25_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN26: GPIO pin configuration register +func (o *GPIO_Type) SetPIN26_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN26_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN26.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN26_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN26_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN26_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN26_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN26_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN26_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN26_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN26_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN26_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN26_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN26_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN26_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN27: GPIO pin configuration register +func (o *GPIO_Type) SetPIN27_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN27_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN27.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN27_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN27_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN27_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN27_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN27_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN27_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN27_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN27_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN27_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN27_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN27_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN27_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN28: GPIO pin configuration register +func (o *GPIO_Type) SetPIN28_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN28_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN28.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN28_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN28_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN28_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN28_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN28_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN28_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN28_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN28_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN28_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN28_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN28_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN28_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN29: GPIO pin configuration register +func (o *GPIO_Type) SetPIN29_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN29_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN29.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN29_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN29_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN29_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN29_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN29_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN29_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN29_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN29_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN29_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN29_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN29_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN29_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN30: GPIO pin configuration register +func (o *GPIO_Type) SetPIN30_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN30_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN30.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN30_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN30_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN30_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN30_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN30_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN30_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN30_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN30_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN30_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN30_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN30_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN30_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN31: GPIO pin configuration register +func (o *GPIO_Type) SetPIN31_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN31_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN31.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN31_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN31_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN31_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN31_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN31_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN31_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN31_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN31_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN31_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN31_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN31_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN31_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x3e000) >> 13 +} + +// GPIO.STATUS_NEXT: GPIO interrupt source register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT.Reg) +} + +// GPIO.FUNC0_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC1_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC2_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC3_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC4_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC5_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC6_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC7_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC8_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC9_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC10_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC11_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC12_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC13_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC14_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC15_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC16_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC17_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC18_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC19_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC20_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC21_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC22_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC23_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC24_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC25_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC26_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC27_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC28_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC29_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC30_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC31_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC32_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC33_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC34_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC35_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC36_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC37_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC38_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC39_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC40_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC41_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC42_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC43_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC44_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC45_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC46_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC47_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC48_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC49_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC50_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC51_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC52_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC53_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC54_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC55_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC56_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC57_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC58_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC59_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC60_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC61_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC62_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC63_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC64_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC65_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC66_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC67_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC68_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC69_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC70_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC71_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC72_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC73_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC74_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC75_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC76_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC77_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC78_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC79_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC80_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC81_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC82_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC83_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC84_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC85_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC86_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC87_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC88_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC89_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC90_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC91_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC92_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC93_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC94_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC95_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC96_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC97_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC98_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC99_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC100_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC101_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC102_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC103_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC104_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC105_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC106_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC107_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC108_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC109_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC110_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC111_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC112_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC113_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC114_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC115_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC116_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC117_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC118_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC119_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC120_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC121_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC122_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC123_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC124_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC125_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC126_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC127_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC0_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC1_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC2_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC3_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC4_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC5_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC6_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC7_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC8_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC9_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC10_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC11_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC12_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC13_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC14_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC15_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC16_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC17_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC18_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC19_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC20_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC21_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC22_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC23_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC24_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC25_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC26_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC27_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC28_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.FUNC29_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0xff +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} + +// GPIO.CLOCK_GATE: GPIO clock gate register +func (o *GPIO_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIO.DATE: GPIO version register +func (o *GPIO_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *GPIO_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Sigma-Delta Modulation +type GPIOSD_Type struct { + SIGMADELTA0 volatile.Register32 // 0x0 + SIGMADELTA1 volatile.Register32 // 0x4 + SIGMADELTA2 volatile.Register32 // 0x8 + SIGMADELTA3 volatile.Register32 // 0xC + _ [16]byte + CLOCK_GATE volatile.Register32 // 0x20 + SIGMADELTA_MISC volatile.Register32 // 0x24 + PAD_COMP_CONFIG volatile.Register32 // 0x28 + PAD_COMP_FILTER volatile.Register32 // 0x2C + GLITCH_FILTER_CH0 volatile.Register32 // 0x30 + GLITCH_FILTER_CH1 volatile.Register32 // 0x34 + GLITCH_FILTER_CH2 volatile.Register32 // 0x38 + GLITCH_FILTER_CH3 volatile.Register32 // 0x3C + GLITCH_FILTER_CH4 volatile.Register32 // 0x40 + GLITCH_FILTER_CH5 volatile.Register32 // 0x44 + GLITCH_FILTER_CH6 volatile.Register32 // 0x48 + GLITCH_FILTER_CH7 volatile.Register32 // 0x4C + _ [16]byte + ETM_EVENT_CH0_CFG volatile.Register32 // 0x60 + ETM_EVENT_CH1_CFG volatile.Register32 // 0x64 + ETM_EVENT_CH2_CFG volatile.Register32 // 0x68 + ETM_EVENT_CH3_CFG volatile.Register32 // 0x6C + ETM_EVENT_CH4_CFG volatile.Register32 // 0x70 + ETM_EVENT_CH5_CFG volatile.Register32 // 0x74 + ETM_EVENT_CH6_CFG volatile.Register32 // 0x78 + ETM_EVENT_CH7_CFG volatile.Register32 // 0x7C + _ [32]byte + ETM_TASK_P0_CFG volatile.Register32 // 0xA0 + ETM_TASK_P1_CFG volatile.Register32 // 0xA4 + ETM_TASK_P2_CFG volatile.Register32 // 0xA8 + ETM_TASK_P3_CFG volatile.Register32 // 0xAC + ETM_TASK_P4_CFG volatile.Register32 // 0xB0 + ETM_TASK_P5_CFG volatile.Register32 // 0xB4 + ETM_TASK_P6_CFG volatile.Register32 // 0xB8 + _ [36]byte + INT_RAW volatile.Register32 // 0xE0 + INT_ST volatile.Register32 // 0xE4 + INT_ENA volatile.Register32 // 0xE8 + INT_CLR volatile.Register32 // 0xEC + _ [12]byte + VERSION volatile.Register32 // 0xFC +} + +// GPIOSD.SIGMADELTA0: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA0_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA0_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA1: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA1_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA1_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA2: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA2_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA2_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA3: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA3_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA3_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff00) >> 8 +} + +// GPIOSD.CLOCK_GATE: Clock Gating Configure Register +func (o *GPIOSD_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIOSD.SIGMADELTA_MISC: MISC Register +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_FUNCTION_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_FUNCTION_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x40000000) >> 30 +} +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_SPI_SWAP(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_SPI_SWAP() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x80000000) >> 31 +} + +// GPIOSD.PAD_COMP_CONFIG: PAD Compare configure Register +func (o *GPIOSD_Type) SetPAD_COMP_CONFIG_XPD_COMP(value uint32) { + volatile.StoreUint32(&o.PAD_COMP_CONFIG.Reg, volatile.LoadUint32(&o.PAD_COMP_CONFIG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetPAD_COMP_CONFIG_XPD_COMP() uint32 { + return volatile.LoadUint32(&o.PAD_COMP_CONFIG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetPAD_COMP_CONFIG_MODE_COMP(value uint32) { + volatile.StoreUint32(&o.PAD_COMP_CONFIG.Reg, volatile.LoadUint32(&o.PAD_COMP_CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *GPIOSD_Type) GetPAD_COMP_CONFIG_MODE_COMP() uint32 { + return (volatile.LoadUint32(&o.PAD_COMP_CONFIG.Reg) & 0x2) >> 1 +} +func (o *GPIOSD_Type) SetPAD_COMP_CONFIG_DREF_COMP(value uint32) { + volatile.StoreUint32(&o.PAD_COMP_CONFIG.Reg, volatile.LoadUint32(&o.PAD_COMP_CONFIG.Reg)&^(0x1c)|value<<2) +} +func (o *GPIOSD_Type) GetPAD_COMP_CONFIG_DREF_COMP() uint32 { + return (volatile.LoadUint32(&o.PAD_COMP_CONFIG.Reg) & 0x1c) >> 2 +} +func (o *GPIOSD_Type) SetPAD_COMP_CONFIG_ZERO_DET_MODE(value uint32) { + volatile.StoreUint32(&o.PAD_COMP_CONFIG.Reg, volatile.LoadUint32(&o.PAD_COMP_CONFIG.Reg)&^(0x60)|value<<5) +} +func (o *GPIOSD_Type) GetPAD_COMP_CONFIG_ZERO_DET_MODE() uint32 { + return (volatile.LoadUint32(&o.PAD_COMP_CONFIG.Reg) & 0x60) >> 5 +} + +// GPIOSD.PAD_COMP_FILTER: Zero Detect filter Register +func (o *GPIOSD_Type) SetPAD_COMP_FILTER(value uint32) { + volatile.StoreUint32(&o.PAD_COMP_FILTER.Reg, value) +} +func (o *GPIOSD_Type) GetPAD_COMP_FILTER() uint32 { + return volatile.LoadUint32(&o.PAD_COMP_FILTER.Reg) +} + +// GPIOSD.GLITCH_FILTER_CH0: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH1: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH2: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH3: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH4: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH5: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH6: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH7: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.ETM_EVENT_CH0_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH0_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH0_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH1_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH1_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH1_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH2_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH2_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH2_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH3_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH3_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH3_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH4_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH4_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH4_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH5_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH5_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH5_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH6_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH6_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH6_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH7_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH7_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg)&^(0x1f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg) & 0x1f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH7_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_TASK_P0_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P1_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P2_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P3_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P4_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P5_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P6_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.INT_RAW: GPIOSD interrupt raw register +func (o *GPIOSD_Type) SetINT_RAW_PAD_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetINT_RAW_PAD_COMP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} + +// GPIOSD.INT_ST: GPIOSD interrupt masked register +func (o *GPIOSD_Type) SetINT_ST_PAD_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetINT_ST_PAD_COMP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} + +// GPIOSD.INT_ENA: GPIOSD interrupt enable register +func (o *GPIOSD_Type) SetINT_ENA_PAD_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetINT_ENA_PAD_COMP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// GPIOSD.INT_CLR: GPIOSD interrupt clear register +func (o *GPIOSD_Type) SetINT_CLR_PAD_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetINT_CLR_PAD_COMP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} + +// GPIOSD.VERSION: Version Control Register +func (o *GPIOSD_Type) SetVERSION_GPIO_SD_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *GPIOSD_Type) GetVERSION_GPIO_SD_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// HMAC (Hash-based Message Authentication Code) Accelerator +type HMAC_Type struct { + _ [64]byte + SET_START volatile.Register32 // 0x40 + SET_PARA_PURPOSE volatile.Register32 // 0x44 + SET_PARA_KEY volatile.Register32 // 0x48 + SET_PARA_FINISH volatile.Register32 // 0x4C + SET_MESSAGE_ONE volatile.Register32 // 0x50 + SET_MESSAGE_ING volatile.Register32 // 0x54 + SET_MESSAGE_END volatile.Register32 // 0x58 + SET_RESULT_FINISH volatile.Register32 // 0x5C + SET_INVALIDATE_JTAG volatile.Register32 // 0x60 + SET_INVALIDATE_DS volatile.Register32 // 0x64 + QUERY_ERROR volatile.Register32 // 0x68 + QUERY_BUSY volatile.Register32 // 0x6C + _ [16]byte + WR_MESSAGE_MEM [64]volatile.Register8 // 0x80 + RD_RESULT_MEM [32]volatile.Register8 // 0xC0 + _ [16]byte + SET_MESSAGE_PAD volatile.Register32 // 0xF0 + ONE_BLOCK volatile.Register32 // 0xF4 + SOFT_JTAG_CTRL volatile.Register32 // 0xF8 + WR_JTAG volatile.Register32 // 0xFC + _ [252]byte + DATE volatile.Register32 // 0x1FC +} + +// HMAC.SET_START: Process control register 0. +func (o *HMAC_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// HMAC.SET_PARA_PURPOSE: Configure purpose. +func (o *HMAC_Type) SetSET_PARA_PURPOSE_PURPOSE_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_PURPOSE.Reg, volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg)&^(0xf)|value) +} +func (o *HMAC_Type) GetSET_PARA_PURPOSE_PURPOSE_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg) & 0xf +} + +// HMAC.SET_PARA_KEY: Configure key. +func (o *HMAC_Type) SetSET_PARA_KEY_KEY_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_KEY.Reg, volatile.LoadUint32(&o.SET_PARA_KEY.Reg)&^(0x7)|value) +} +func (o *HMAC_Type) GetSET_PARA_KEY_KEY_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_KEY.Reg) & 0x7 +} + +// HMAC.SET_PARA_FINISH: Finish initial configuration. +func (o *HMAC_Type) SetSET_PARA_FINISH_SET_PARA_END(value uint32) { + volatile.StoreUint32(&o.SET_PARA_FINISH.Reg, volatile.LoadUint32(&o.SET_PARA_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_PARA_FINISH_SET_PARA_END() uint32 { + return volatile.LoadUint32(&o.SET_PARA_FINISH.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ONE: Process control register 1. +func (o *HMAC_Type) SetSET_MESSAGE_ONE_SET_TEXT_ONE(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ONE.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ONE_SET_TEXT_ONE() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ING: Process control register 2. +func (o *HMAC_Type) SetSET_MESSAGE_ING_SET_TEXT_ING(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ING.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ING_SET_TEXT_ING() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_END: Process control register 3. +func (o *HMAC_Type) SetSET_MESSAGE_END_SET_TEXT_END(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_END.Reg, volatile.LoadUint32(&o.SET_MESSAGE_END.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_END_SET_TEXT_END() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_END.Reg) & 0x1 +} + +// HMAC.SET_RESULT_FINISH: Process control register 4. +func (o *HMAC_Type) SetSET_RESULT_FINISH_SET_RESULT_END(value uint32) { + volatile.StoreUint32(&o.SET_RESULT_FINISH.Reg, volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_RESULT_FINISH_SET_RESULT_END() uint32 { + return volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_JTAG: Invalidate register 0. +func (o *HMAC_Type) SetSET_INVALIDATE_JTAG(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_JTAG.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_JTAG() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_DS: Invalidate register 1. +func (o *HMAC_Type) SetSET_INVALIDATE_DS(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_DS.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_DS() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg) & 0x1 +} + +// HMAC.QUERY_ERROR: Error register. +func (o *HMAC_Type) SetQUERY_ERROR_QUERY_CHECK(value uint32) { + volatile.StoreUint32(&o.QUERY_ERROR.Reg, volatile.LoadUint32(&o.QUERY_ERROR.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_ERROR_QUERY_CHECK() uint32 { + return volatile.LoadUint32(&o.QUERY_ERROR.Reg) & 0x1 +} + +// HMAC.QUERY_BUSY: Busy register. +func (o *HMAC_Type) SetQUERY_BUSY_BUSY_STATE(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_BUSY_BUSY_STATE() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_PAD: Process control register 5. +func (o *HMAC_Type) SetSET_MESSAGE_PAD_SET_TEXT_PAD(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_PAD.Reg, volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_PAD_SET_TEXT_PAD() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg) & 0x1 +} + +// HMAC.ONE_BLOCK: Process control register 6. +func (o *HMAC_Type) SetONE_BLOCK_SET_ONE_BLOCK(value uint32) { + volatile.StoreUint32(&o.ONE_BLOCK.Reg, volatile.LoadUint32(&o.ONE_BLOCK.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetONE_BLOCK_SET_ONE_BLOCK() uint32 { + return volatile.LoadUint32(&o.ONE_BLOCK.Reg) & 0x1 +} + +// HMAC.SOFT_JTAG_CTRL: Jtag register 0. +func (o *HMAC_Type) SetSOFT_JTAG_CTRL(value uint32) { + volatile.StoreUint32(&o.SOFT_JTAG_CTRL.Reg, volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSOFT_JTAG_CTRL() uint32 { + return volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg) & 0x1 +} + +// HMAC.WR_JTAG: Jtag register 1. +func (o *HMAC_Type) SetWR_JTAG(value uint32) { + volatile.StoreUint32(&o.WR_JTAG.Reg, value) +} +func (o *HMAC_Type) GetWR_JTAG() uint32 { + return volatile.LoadUint32(&o.WR_JTAG.Reg) +} + +// HMAC.DATE: Date register. +func (o *HMAC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *HMAC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// HP_APM Peripheral +type HP_APM_Type struct { + REGION_FILTER_EN volatile.Register32 // 0x0 + REGION0_ADDR_START volatile.Register32 // 0x4 + REGION0_ADDR_END volatile.Register32 // 0x8 + REGION0_PMS_ATTR volatile.Register32 // 0xC + REGION1_ADDR_START volatile.Register32 // 0x10 + REGION1_ADDR_END volatile.Register32 // 0x14 + REGION1_PMS_ATTR volatile.Register32 // 0x18 + REGION2_ADDR_START volatile.Register32 // 0x1C + REGION2_ADDR_END volatile.Register32 // 0x20 + REGION2_PMS_ATTR volatile.Register32 // 0x24 + REGION3_ADDR_START volatile.Register32 // 0x28 + REGION3_ADDR_END volatile.Register32 // 0x2C + REGION3_PMS_ATTR volatile.Register32 // 0x30 + REGION4_ADDR_START volatile.Register32 // 0x34 + REGION4_ADDR_END volatile.Register32 // 0x38 + REGION4_PMS_ATTR volatile.Register32 // 0x3C + REGION5_ADDR_START volatile.Register32 // 0x40 + REGION5_ADDR_END volatile.Register32 // 0x44 + REGION5_PMS_ATTR volatile.Register32 // 0x48 + REGION6_ADDR_START volatile.Register32 // 0x4C + REGION6_ADDR_END volatile.Register32 // 0x50 + REGION6_PMS_ATTR volatile.Register32 // 0x54 + REGION7_ADDR_START volatile.Register32 // 0x58 + REGION7_ADDR_END volatile.Register32 // 0x5C + REGION7_PMS_ATTR volatile.Register32 // 0x60 + REGION8_ADDR_START volatile.Register32 // 0x64 + REGION8_ADDR_END volatile.Register32 // 0x68 + REGION8_PMS_ATTR volatile.Register32 // 0x6C + REGION9_ADDR_START volatile.Register32 // 0x70 + REGION9_ADDR_END volatile.Register32 // 0x74 + REGION9_PMS_ATTR volatile.Register32 // 0x78 + REGION10_ADDR_START volatile.Register32 // 0x7C + REGION10_ADDR_END volatile.Register32 // 0x80 + REGION10_PMS_ATTR volatile.Register32 // 0x84 + REGION11_ADDR_START volatile.Register32 // 0x88 + REGION11_ADDR_END volatile.Register32 // 0x8C + REGION11_PMS_ATTR volatile.Register32 // 0x90 + REGION12_ADDR_START volatile.Register32 // 0x94 + REGION12_ADDR_END volatile.Register32 // 0x98 + REGION12_PMS_ATTR volatile.Register32 // 0x9C + REGION13_ADDR_START volatile.Register32 // 0xA0 + REGION13_ADDR_END volatile.Register32 // 0xA4 + REGION13_PMS_ATTR volatile.Register32 // 0xA8 + REGION14_ADDR_START volatile.Register32 // 0xAC + REGION14_ADDR_END volatile.Register32 // 0xB0 + REGION14_PMS_ATTR volatile.Register32 // 0xB4 + REGION15_ADDR_START volatile.Register32 // 0xB8 + REGION15_ADDR_END volatile.Register32 // 0xBC + REGION15_PMS_ATTR volatile.Register32 // 0xC0 + FUNC_CTRL volatile.Register32 // 0xC4 + M0_STATUS volatile.Register32 // 0xC8 + M0_STATUS_CLR volatile.Register32 // 0xCC + M0_EXCEPTION_INFO0 volatile.Register32 // 0xD0 + M0_EXCEPTION_INFO1 volatile.Register32 // 0xD4 + M1_STATUS volatile.Register32 // 0xD8 + M1_STATUS_CLR volatile.Register32 // 0xDC + M1_EXCEPTION_INFO0 volatile.Register32 // 0xE0 + M1_EXCEPTION_INFO1 volatile.Register32 // 0xE4 + M2_STATUS volatile.Register32 // 0xE8 + M2_STATUS_CLR volatile.Register32 // 0xEC + M2_EXCEPTION_INFO0 volatile.Register32 // 0xF0 + M2_EXCEPTION_INFO1 volatile.Register32 // 0xF4 + M3_STATUS volatile.Register32 // 0xF8 + M3_STATUS_CLR volatile.Register32 // 0xFC + M3_EXCEPTION_INFO0 volatile.Register32 // 0x100 + M3_EXCEPTION_INFO1 volatile.Register32 // 0x104 + INT_EN volatile.Register32 // 0x108 + CLOCK_GATE volatile.Register32 // 0x10C + _ [1772]byte + DATE volatile.Register32 // 0x7FC +} + +// HP_APM.REGION_FILTER_EN: Region filter enable register +func (o *HP_APM_Type) SetREGION_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.REGION_FILTER_EN.Reg, volatile.LoadUint32(&o.REGION_FILTER_EN.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetREGION_FILTER_EN() uint32 { + return volatile.LoadUint32(&o.REGION_FILTER_EN.Reg) & 0xffff +} + +// HP_APM.REGION0_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION0_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION0_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_START.Reg) +} + +// HP_APM.REGION0_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION0_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION0_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_END.Reg) +} + +// HP_APM.REGION0_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION1_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION1_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION1_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_START.Reg) +} + +// HP_APM.REGION1_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION1_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION1_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_END.Reg) +} + +// HP_APM.REGION1_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION2_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION2_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION2_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_START.Reg) +} + +// HP_APM.REGION2_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION2_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION2_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION2_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION2_ADDR_END.Reg) +} + +// HP_APM.REGION2_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION2_PMS_ATTR_REGION2_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION2_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION2_PMS_ATTR_REGION2_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION2_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION3_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION3_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION3_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_START.Reg) +} + +// HP_APM.REGION3_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION3_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION3_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION3_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION3_ADDR_END.Reg) +} + +// HP_APM.REGION3_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION3_PMS_ATTR_REGION3_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION3_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION3_PMS_ATTR_REGION3_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION3_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION4_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION4_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION4_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION4_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION4_ADDR_START.Reg) +} + +// HP_APM.REGION4_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION4_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION4_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION4_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION4_ADDR_END.Reg) +} + +// HP_APM.REGION4_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION4_PMS_ATTR_REGION4_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION4_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION4_PMS_ATTR_REGION4_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION4_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION5_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION5_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION5_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION5_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION5_ADDR_START.Reg) +} + +// HP_APM.REGION5_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION5_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION5_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION5_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION5_ADDR_END.Reg) +} + +// HP_APM.REGION5_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION5_PMS_ATTR_REGION5_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION5_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION5_PMS_ATTR_REGION5_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION5_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION6_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION6_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION6_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION6_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION6_ADDR_START.Reg) +} + +// HP_APM.REGION6_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION6_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION6_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION6_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION6_ADDR_END.Reg) +} + +// HP_APM.REGION6_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION6_PMS_ATTR_REGION6_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION6_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION6_PMS_ATTR_REGION6_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION6_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION7_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION7_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION7_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION7_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION7_ADDR_START.Reg) +} + +// HP_APM.REGION7_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION7_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION7_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION7_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION7_ADDR_END.Reg) +} + +// HP_APM.REGION7_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION7_PMS_ATTR_REGION7_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION7_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION7_PMS_ATTR_REGION7_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION7_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION8_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION8_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION8_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION8_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION8_ADDR_START.Reg) +} + +// HP_APM.REGION8_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION8_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION8_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION8_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION8_ADDR_END.Reg) +} + +// HP_APM.REGION8_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION8_PMS_ATTR_REGION8_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION8_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION8_PMS_ATTR_REGION8_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION8_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION9_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION9_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION9_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION9_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION9_ADDR_START.Reg) +} + +// HP_APM.REGION9_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION9_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION9_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION9_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION9_ADDR_END.Reg) +} + +// HP_APM.REGION9_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION9_PMS_ATTR_REGION9_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION9_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION9_PMS_ATTR_REGION9_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION9_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION10_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION10_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION10_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION10_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION10_ADDR_START.Reg) +} + +// HP_APM.REGION10_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION10_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION10_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION10_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION10_ADDR_END.Reg) +} + +// HP_APM.REGION10_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION10_PMS_ATTR_REGION10_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION10_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION10_PMS_ATTR_REGION10_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION10_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION11_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION11_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION11_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION11_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION11_ADDR_START.Reg) +} + +// HP_APM.REGION11_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION11_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION11_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION11_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION11_ADDR_END.Reg) +} + +// HP_APM.REGION11_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION11_PMS_ATTR_REGION11_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION11_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION11_PMS_ATTR_REGION11_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION11_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION12_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION12_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION12_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION12_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION12_ADDR_START.Reg) +} + +// HP_APM.REGION12_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION12_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION12_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION12_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION12_ADDR_END.Reg) +} + +// HP_APM.REGION12_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION12_PMS_ATTR_REGION12_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION12_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION12_PMS_ATTR_REGION12_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION12_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION13_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION13_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION13_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION13_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION13_ADDR_START.Reg) +} + +// HP_APM.REGION13_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION13_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION13_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION13_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION13_ADDR_END.Reg) +} + +// HP_APM.REGION13_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION13_PMS_ATTR_REGION13_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION13_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION13_PMS_ATTR_REGION13_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION13_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION14_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION14_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION14_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION14_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION14_ADDR_START.Reg) +} + +// HP_APM.REGION14_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION14_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION14_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION14_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION14_ADDR_END.Reg) +} + +// HP_APM.REGION14_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION14_PMS_ATTR_REGION14_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION14_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION14_PMS_ATTR_REGION14_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION14_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.REGION15_ADDR_START: Region address register +func (o *HP_APM_Type) SetREGION15_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION15_ADDR_START.Reg, value) +} +func (o *HP_APM_Type) GetREGION15_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION15_ADDR_START.Reg) +} + +// HP_APM.REGION15_ADDR_END: Region address register +func (o *HP_APM_Type) SetREGION15_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION15_ADDR_END.Reg, value) +} +func (o *HP_APM_Type) GetREGION15_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION15_ADDR_END.Reg) +} + +// HP_APM.REGION15_PMS_ATTR: Region access authority attribute register +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x1 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *HP_APM_Type) SetREGION15_PMS_ATTR_REGION15_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION15_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *HP_APM_Type) GetREGION15_PMS_ATTR_REGION15_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION15_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// HP_APM.FUNC_CTRL: PMS function control register +func (o *HP_APM_Type) SetFUNC_CTRL_M0_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetFUNC_CTRL_M0_PMS_FUNC_EN() uint32 { + return volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x1 +} +func (o *HP_APM_Type) SetFUNC_CTRL_M1_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetFUNC_CTRL_M1_PMS_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetFUNC_CTRL_M2_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetFUNC_CTRL_M2_PMS_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetFUNC_CTRL_M3_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *HP_APM_Type) GetFUNC_CTRL_M3_PMS_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x8) >> 3 +} + +// HP_APM.M0_STATUS: M0 status register +func (o *HP_APM_Type) SetM0_STATUS_M0_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M0_STATUS.Reg, volatile.LoadUint32(&o.M0_STATUS.Reg)&^(0x3)|value) +} +func (o *HP_APM_Type) GetM0_STATUS_M0_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M0_STATUS.Reg) & 0x3 +} + +// HP_APM.M0_STATUS_CLR: M0 status clear register +func (o *HP_APM_Type) SetM0_STATUS_CLR_M0_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M0_STATUS_CLR.Reg, volatile.LoadUint32(&o.M0_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetM0_STATUS_CLR_M0_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M0_STATUS_CLR.Reg) & 0x1 +} + +// HP_APM.M0_EXCEPTION_INFO0: M0 exception_info0 register +func (o *HP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0xffff +} +func (o *HP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *HP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *HP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *HP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// HP_APM.M0_EXCEPTION_INFO1: M0 exception_info1 register +func (o *HP_APM_Type) SetM0_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO1.Reg, value) +} +func (o *HP_APM_Type) GetM0_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO1.Reg) +} + +// HP_APM.M1_STATUS: M1 status register +func (o *HP_APM_Type) SetM1_STATUS_M1_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M1_STATUS.Reg, volatile.LoadUint32(&o.M1_STATUS.Reg)&^(0x3)|value) +} +func (o *HP_APM_Type) GetM1_STATUS_M1_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M1_STATUS.Reg) & 0x3 +} + +// HP_APM.M1_STATUS_CLR: M1 status clear register +func (o *HP_APM_Type) SetM1_STATUS_CLR_M1_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M1_STATUS_CLR.Reg, volatile.LoadUint32(&o.M1_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetM1_STATUS_CLR_M1_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M1_STATUS_CLR.Reg) & 0x1 +} + +// HP_APM.M1_EXCEPTION_INFO0: M1 exception_info0 register +func (o *HP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0xffff +} +func (o *HP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *HP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *HP_APM_Type) SetM1_EXCEPTION_INFO0_M1_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *HP_APM_Type) GetM1_EXCEPTION_INFO0_M1_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M1_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// HP_APM.M1_EXCEPTION_INFO1: M1 exception_info1 register +func (o *HP_APM_Type) SetM1_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M1_EXCEPTION_INFO1.Reg, value) +} +func (o *HP_APM_Type) GetM1_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M1_EXCEPTION_INFO1.Reg) +} + +// HP_APM.M2_STATUS: M2 status register +func (o *HP_APM_Type) SetM2_STATUS_M2_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M2_STATUS.Reg, volatile.LoadUint32(&o.M2_STATUS.Reg)&^(0x3)|value) +} +func (o *HP_APM_Type) GetM2_STATUS_M2_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M2_STATUS.Reg) & 0x3 +} + +// HP_APM.M2_STATUS_CLR: M2 status clear register +func (o *HP_APM_Type) SetM2_STATUS_CLR_M2_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M2_STATUS_CLR.Reg, volatile.LoadUint32(&o.M2_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetM2_STATUS_CLR_M2_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M2_STATUS_CLR.Reg) & 0x1 +} + +// HP_APM.M2_EXCEPTION_INFO0: M2 exception_info0 register +func (o *HP_APM_Type) SetM2_EXCEPTION_INFO0_M2_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M2_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetM2_EXCEPTION_INFO0_M2_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg) & 0xffff +} +func (o *HP_APM_Type) SetM2_EXCEPTION_INFO0_M2_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M2_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *HP_APM_Type) GetM2_EXCEPTION_INFO0_M2_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *HP_APM_Type) SetM2_EXCEPTION_INFO0_M2_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M2_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *HP_APM_Type) GetM2_EXCEPTION_INFO0_M2_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M2_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// HP_APM.M2_EXCEPTION_INFO1: M2 exception_info1 register +func (o *HP_APM_Type) SetM2_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M2_EXCEPTION_INFO1.Reg, value) +} +func (o *HP_APM_Type) GetM2_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M2_EXCEPTION_INFO1.Reg) +} + +// HP_APM.M3_STATUS: M3 status register +func (o *HP_APM_Type) SetM3_STATUS_M3_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M3_STATUS.Reg, volatile.LoadUint32(&o.M3_STATUS.Reg)&^(0x3)|value) +} +func (o *HP_APM_Type) GetM3_STATUS_M3_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M3_STATUS.Reg) & 0x3 +} + +// HP_APM.M3_STATUS_CLR: M3 status clear register +func (o *HP_APM_Type) SetM3_STATUS_CLR_M3_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M3_STATUS_CLR.Reg, volatile.LoadUint32(&o.M3_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetM3_STATUS_CLR_M3_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M3_STATUS_CLR.Reg) & 0x1 +} + +// HP_APM.M3_EXCEPTION_INFO0: M3 exception_info0 register +func (o *HP_APM_Type) SetM3_EXCEPTION_INFO0_M3_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M3_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg)&^(0xffff)|value) +} +func (o *HP_APM_Type) GetM3_EXCEPTION_INFO0_M3_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg) & 0xffff +} +func (o *HP_APM_Type) SetM3_EXCEPTION_INFO0_M3_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M3_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *HP_APM_Type) GetM3_EXCEPTION_INFO0_M3_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *HP_APM_Type) SetM3_EXCEPTION_INFO0_M3_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M3_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *HP_APM_Type) GetM3_EXCEPTION_INFO0_M3_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M3_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// HP_APM.M3_EXCEPTION_INFO1: M3 exception_info1 register +func (o *HP_APM_Type) SetM3_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M3_EXCEPTION_INFO1.Reg, value) +} +func (o *HP_APM_Type) GetM3_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M3_EXCEPTION_INFO1.Reg) +} + +// HP_APM.INT_EN: APM interrupt enable register +func (o *HP_APM_Type) SetINT_EN_M0_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetINT_EN_M0_APM_INT_EN() uint32 { + return volatile.LoadUint32(&o.INT_EN.Reg) & 0x1 +} +func (o *HP_APM_Type) SetINT_EN_M1_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x2)|value<<1) +} +func (o *HP_APM_Type) GetINT_EN_M1_APM_INT_EN() uint32 { + return (volatile.LoadUint32(&o.INT_EN.Reg) & 0x2) >> 1 +} +func (o *HP_APM_Type) SetINT_EN_M2_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x4)|value<<2) +} +func (o *HP_APM_Type) GetINT_EN_M2_APM_INT_EN() uint32 { + return (volatile.LoadUint32(&o.INT_EN.Reg) & 0x4) >> 2 +} +func (o *HP_APM_Type) SetINT_EN_M3_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x8)|value<<3) +} +func (o *HP_APM_Type) GetINT_EN_M3_APM_INT_EN() uint32 { + return (volatile.LoadUint32(&o.INT_EN.Reg) & 0x8) >> 3 +} + +// HP_APM.CLOCK_GATE: clock gating register +func (o *HP_APM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *HP_APM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// HP_APM.DATE: Version register +func (o *HP_APM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *HP_APM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// High-Power System +type HP_SYS_Type struct { + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL volatile.Register32 // 0x0 + SRAM_USAGE_CONF volatile.Register32 // 0x4 + SEC_DPA_CONF volatile.Register32 // 0x8 + CPU_PERI_TIMEOUT_CONF volatile.Register32 // 0xC + CPU_PERI_TIMEOUT_ADDR volatile.Register32 // 0x10 + CPU_PERI_TIMEOUT_UID volatile.Register32 // 0x14 + HP_PERI_TIMEOUT_CONF volatile.Register32 // 0x18 + HP_PERI_TIMEOUT_ADDR volatile.Register32 // 0x1C + HP_PERI_TIMEOUT_UID volatile.Register32 // 0x20 + ROM_TABLE_LOCK volatile.Register32 // 0x24 + ROM_TABLE volatile.Register32 // 0x28 + MEM_TEST_CONF volatile.Register32 // 0x2C + _ [944]byte + RND_ECO volatile.Register32 // 0x3E0 + RND_ECO_LOW volatile.Register32 // 0x3E4 + RND_ECO_HIGH volatile.Register32 // 0x3E8 + _ [12]byte + CLOCK_GATE volatile.Register32 // 0x3F8 + DATE volatile.Register32 // 0x3FC +} + +// HP_SYS.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register +func (o *HP_SYS_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x8) >> 3 +} + +// HP_SYS.SRAM_USAGE_CONF: HP memory usage configuration register +func (o *HP_SYS_Type) SetSRAM_USAGE_CONF_SRAM_USAGE(value uint32) { + volatile.StoreUint32(&o.SRAM_USAGE_CONF.Reg, volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg)&^(0x7c00)|value<<10) +} +func (o *HP_SYS_Type) GetSRAM_USAGE_CONF_SRAM_USAGE() uint32 { + return (volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg) & 0x7c00) >> 10 +} +func (o *HP_SYS_Type) SetSRAM_USAGE_CONF_MAC_DUMP_ALLOC(value uint32) { + volatile.StoreUint32(&o.SRAM_USAGE_CONF.Reg, volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg)&^(0x1f00000)|value<<20) +} +func (o *HP_SYS_Type) GetSRAM_USAGE_CONF_MAC_DUMP_ALLOC() uint32 { + return (volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg) & 0x1f00000) >> 20 +} +func (o *HP_SYS_Type) SetSRAM_USAGE_CONF_CACHE_USAGE(value uint32) { + volatile.StoreUint32(&o.SRAM_USAGE_CONF.Reg, volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_Type) GetSRAM_USAGE_CONF_CACHE_USAGE() uint32 { + return (volatile.LoadUint32(&o.SRAM_USAGE_CONF.Reg) & 0x80000000) >> 31 +} + +// HP_SYS.SEC_DPA_CONF: HP anti-DPA security configuration register +func (o *HP_SYS_Type) SetSEC_DPA_CONF_SEC_DPA_LEVEL(value uint32) { + volatile.StoreUint32(&o.SEC_DPA_CONF.Reg, volatile.LoadUint32(&o.SEC_DPA_CONF.Reg)&^(0x3)|value) +} +func (o *HP_SYS_Type) GetSEC_DPA_CONF_SEC_DPA_LEVEL() uint32 { + return volatile.LoadUint32(&o.SEC_DPA_CONF.Reg) & 0x3 +} +func (o *HP_SYS_Type) SetSEC_DPA_CONF_SEC_DPA_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.SEC_DPA_CONF.Reg, volatile.LoadUint32(&o.SEC_DPA_CONF.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetSEC_DPA_CONF_SEC_DPA_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.SEC_DPA_CONF.Reg) & 0x4) >> 2 +} + +// HP_SYS.CPU_PERI_TIMEOUT_CONF: CPU_PERI_TIMEOUT configuration register +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg)&^(0xffff)|value) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_THRES() uint32 { + return volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg) & 0xffff +} +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_CONF.Reg) & 0x20000) >> 17 +} + +// HP_SYS.CPU_PERI_TIMEOUT_ADDR: CPU_PERI_TIMEOUT_ADDR register +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_ADDR(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_ADDR.Reg, value) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_ADDR() uint32 { + return volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_ADDR.Reg) +} + +// HP_SYS.CPU_PERI_TIMEOUT_UID: CPU_PERI_TIMEOUT_UID register +func (o *HP_SYS_Type) SetCPU_PERI_TIMEOUT_UID(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_UID.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_UID.Reg)&^(0x7f)|value) +} +func (o *HP_SYS_Type) GetCPU_PERI_TIMEOUT_UID() uint32 { + return volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_UID.Reg) & 0x7f +} + +// HP_SYS.HP_PERI_TIMEOUT_CONF: HP_PERI_TIMEOUT configuration register +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg)&^(0xffff)|value) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_THRES() uint32 { + return volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg) & 0xffff +} +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR() uint32 { + return (volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN() uint32 { + return (volatile.LoadUint32(&o.HP_PERI_TIMEOUT_CONF.Reg) & 0x20000) >> 17 +} + +// HP_SYS.HP_PERI_TIMEOUT_ADDR: HP_PERI_TIMEOUT_ADDR register +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_ADDR(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_ADDR.Reg, value) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_ADDR() uint32 { + return volatile.LoadUint32(&o.HP_PERI_TIMEOUT_ADDR.Reg) +} + +// HP_SYS.HP_PERI_TIMEOUT_UID: HP_PERI_TIMEOUT_UID register +func (o *HP_SYS_Type) SetHP_PERI_TIMEOUT_UID(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_UID.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_UID.Reg)&^(0x7f)|value) +} +func (o *HP_SYS_Type) GetHP_PERI_TIMEOUT_UID() uint32 { + return volatile.LoadUint32(&o.HP_PERI_TIMEOUT_UID.Reg) & 0x7f +} + +// HP_SYS.ROM_TABLE_LOCK: Rom-Table lock register +func (o *HP_SYS_Type) SetROM_TABLE_LOCK(value uint32) { + volatile.StoreUint32(&o.ROM_TABLE_LOCK.Reg, volatile.LoadUint32(&o.ROM_TABLE_LOCK.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetROM_TABLE_LOCK() uint32 { + return volatile.LoadUint32(&o.ROM_TABLE_LOCK.Reg) & 0x1 +} + +// HP_SYS.ROM_TABLE: Rom-Table register +func (o *HP_SYS_Type) SetROM_TABLE(value uint32) { + volatile.StoreUint32(&o.ROM_TABLE.Reg, value) +} +func (o *HP_SYS_Type) GetROM_TABLE() uint32 { + return volatile.LoadUint32(&o.ROM_TABLE.Reg) +} + +// HP_SYS.MEM_TEST_CONF: MEM_TEST configuration register +func (o *HP_SYS_Type) SetMEM_TEST_CONF_HP_MEM_WPULSE(value uint32) { + volatile.StoreUint32(&o.MEM_TEST_CONF.Reg, volatile.LoadUint32(&o.MEM_TEST_CONF.Reg)&^(0x7)|value) +} +func (o *HP_SYS_Type) GetMEM_TEST_CONF_HP_MEM_WPULSE() uint32 { + return volatile.LoadUint32(&o.MEM_TEST_CONF.Reg) & 0x7 +} +func (o *HP_SYS_Type) SetMEM_TEST_CONF_HP_MEM_WA(value uint32) { + volatile.StoreUint32(&o.MEM_TEST_CONF.Reg, volatile.LoadUint32(&o.MEM_TEST_CONF.Reg)&^(0x38)|value<<3) +} +func (o *HP_SYS_Type) GetMEM_TEST_CONF_HP_MEM_WA() uint32 { + return (volatile.LoadUint32(&o.MEM_TEST_CONF.Reg) & 0x38) >> 3 +} +func (o *HP_SYS_Type) SetMEM_TEST_CONF_HP_MEM_RA(value uint32) { + volatile.StoreUint32(&o.MEM_TEST_CONF.Reg, volatile.LoadUint32(&o.MEM_TEST_CONF.Reg)&^(0xc0)|value<<6) +} +func (o *HP_SYS_Type) GetMEM_TEST_CONF_HP_MEM_RA() uint32 { + return (volatile.LoadUint32(&o.MEM_TEST_CONF.Reg) & 0xc0) >> 6 +} +func (o *HP_SYS_Type) SetMEM_TEST_CONF_HP_MEM_RM(value uint32) { + volatile.StoreUint32(&o.MEM_TEST_CONF.Reg, volatile.LoadUint32(&o.MEM_TEST_CONF.Reg)&^(0xf00)|value<<8) +} +func (o *HP_SYS_Type) GetMEM_TEST_CONF_HP_MEM_RM() uint32 { + return (volatile.LoadUint32(&o.MEM_TEST_CONF.Reg) & 0xf00) >> 8 +} +func (o *HP_SYS_Type) SetMEM_TEST_CONF_ROM_RM(value uint32) { + volatile.StoreUint32(&o.MEM_TEST_CONF.Reg, volatile.LoadUint32(&o.MEM_TEST_CONF.Reg)&^(0xf000)|value<<12) +} +func (o *HP_SYS_Type) GetMEM_TEST_CONF_ROM_RM() uint32 { + return (volatile.LoadUint32(&o.MEM_TEST_CONF.Reg) & 0xf000) >> 12 +} + +// HP_SYS.RND_ECO: redcy eco register. +func (o *HP_SYS_Type) SetRND_ECO_REDCY_ENA(value uint32) { + volatile.StoreUint32(&o.RND_ECO.Reg, volatile.LoadUint32(&o.RND_ECO.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetRND_ECO_REDCY_ENA() uint32 { + return volatile.LoadUint32(&o.RND_ECO.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetRND_ECO_REDCY_RESULT(value uint32) { + volatile.StoreUint32(&o.RND_ECO.Reg, volatile.LoadUint32(&o.RND_ECO.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetRND_ECO_REDCY_RESULT() uint32 { + return (volatile.LoadUint32(&o.RND_ECO.Reg) & 0x2) >> 1 +} + +// HP_SYS.RND_ECO_LOW: redcy eco low register. +func (o *HP_SYS_Type) SetRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value) +} +func (o *HP_SYS_Type) GetRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RND_ECO_LOW.Reg) +} + +// HP_SYS.RND_ECO_HIGH: redcy eco high register. +func (o *HP_SYS_Type) SetRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value) +} +func (o *HP_SYS_Type) GetRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg) +} + +// HP_SYS.CLOCK_GATE: HP-SYSTEM clock gating configure register +func (o *HP_SYS_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// HP_SYS.DATE: Date register. +func (o *HP_SYS_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *HP_SYS_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// I2C (Inter-Integrated Circuit) Controller 0 +type I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + FILTER_CFG volatile.Register32 // 0x50 + CLK_CONF volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + SCL_ST_TIME_OUT volatile.Register32 // 0x78 + SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C + SCL_SP_CONF volatile.Register32 // 0x80 + SCL_STRETCH_CONF volatile.Register32 // 0x84 + _ [112]byte + DATE volatile.Register32 // 0xF8 + _ [4]byte + TXFIFO_START_ADDR volatile.Register32 // 0x100 + _ [124]byte + RXFIFO_START_ADDR volatile.Register32 // 0x180 +} + +// I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL Clock +func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff +} + +// I2C.CTR: Transmission setting +func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetCTR_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetCTR_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetCTR_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetCTR_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetCTR_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetCTR_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetCTR_CONF_UPGATE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetCTR_CONF_UPGATE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetCTR_SLV_TX_AUTO_START_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetCTR_SLV_TX_AUTO_START_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetCTR_ADDR_10BIT_RW_CHECK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetCTR_ADDR_10BIT_RW_CHECK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetCTR_ADDR_BROADCASTING_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetCTR_ADDR_BROADCASTING_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4000) >> 14 +} + +// I2C.SR: Describe I2C work status. +func (o *I2C_Type) SetSR_RESP_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSR_RESP_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *I2C_Type) SetSR_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetSR_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetSR_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetSR_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetSR_STRETCH_CAUSE(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xc000)|value<<14) +} +func (o *I2C_Type) GetSR_STRETCH_CAUSE() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xc000) >> 14 +} +func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xfc0000) >> 18 +} +func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// I2C.TO: Setting time out control for receiving data. +func (o *I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetTO_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0x1f +} +func (o *I2C_Type) SetTO_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetTO_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5 +} + +// I2C.SLAVE_ADDR: Local slave address setting +func (o *I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// I2C.FIFO_ST: FIFO status register. +func (o *I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 { + return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x7c00)|value<<10) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x7c00) >> 10 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf8000)|value<<15) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf8000) >> 15 +} +func (o *I2C_Type) SetFIFO_ST_SLAVE_RW_POINT(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3fc00000)|value<<22) +} +func (o *I2C_Type) GetFIFO_ST_SLAVE_RW_POINT() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3fc00000) >> 22 +} + +// I2C.FIFO_CONF: FIFO configuration register. +func (o *I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_ADDR_CFG_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_ADDR_CFG_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14 +} + +// I2C.DATA: Rx FIFO read data. +func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// I2C.INT_RAW: Raw interrupt status +func (o *I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_STRETCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_STRETCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_RAW_GENERAL_CALL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_RAW_GENERAL_CALL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} + +// I2C.INT_CLR: Interrupt clear bits +func (o *I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_STRETCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_STRETCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_CLR_GENERAL_CALL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_CLR_GENERAL_CALL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} + +// I2C.INT_ENA: Interrupt enable bits +func (o *I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_STRETCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_STRETCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_ENA_GENERAL_CALL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_ENA_GENERAL_CALL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} + +// I2C.INT_STATUS: Status of captured I2C communication events +func (o *I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_STRETCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_STRETCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_STATUS_GENERAL_CALL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_STATUS_GENERAL_CALL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40000) >> 18 +} + +// I2C.SDA_HOLD: Configures the hold time after a negative SCL edge. +func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff +} + +// I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge. +func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff +} + +// I2C.SCL_HIGH_PERIOD: Configures the high level width of SCL +func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff +} +func (o *I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9 +} + +// I2C.SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition +func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA +func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff +} + +// I2C.FILTER_CFG: SCL and SDA filter configuration register +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4 +} +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9 +} + +// I2C.CLK_CONF: I2C CLK configuration register +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} + +// I2C.COMD0: I2C command register %s +func (o *I2C_Type) SetCOMD0_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD0_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD0_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD0_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD1: I2C command register %s +func (o *I2C_Type) SetCOMD1_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD1_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD1_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD1_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD2: I2C command register %s +func (o *I2C_Type) SetCOMD2_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD2_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD2_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD2_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD3: I2C command register %s +func (o *I2C_Type) SetCOMD3_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD3_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD3_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD3_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD4: I2C command register %s +func (o *I2C_Type) SetCOMD4_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD4_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD4_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD4_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD5: I2C command register %s +func (o *I2C_Type) SetCOMD5_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD5_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD5_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD5_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD6: I2C command register %s +func (o *I2C_Type) SetCOMD6_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD6_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD6_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD6_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD7: I2C command register %s +func (o *I2C_Type) SetCOMD7_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD7_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD7_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD7_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// I2C.SCL_ST_TIME_OUT: SCL status time out register +func (o *I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register +func (o *I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_SP_CONF: Power configuration register +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// I2C.SCL_STRETCH_CONF: Set SCL stretch of I2C slave +func (o *I2C_Type) SetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM() uint32 { + return volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x3ff +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x2000) >> 13 +} + +// I2C.DATE: Version register +func (o *I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2C.TXFIFO_START_ADDR: I2C TXFIFO base address register +func (o *I2C_Type) SetTXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetTXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg) +} + +// I2C.RXFIFO_START_ADDR: I2C RXFIFO base address register +func (o *I2C_Type) SetRXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetRXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg) +} + +// I2S (Inter-IC Sound) Controller 0 +type I2S_Type struct { + _ [12]byte + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + _ [4]byte + RX_CONF volatile.Register32 // 0x20 + TX_CONF volatile.Register32 // 0x24 + RX_CONF1 volatile.Register32 // 0x28 + TX_CONF1 volatile.Register32 // 0x2C + RX_CLKM_CONF volatile.Register32 // 0x30 + TX_CLKM_CONF volatile.Register32 // 0x34 + RX_CLKM_DIV_CONF volatile.Register32 // 0x38 + TX_CLKM_DIV_CONF volatile.Register32 // 0x3C + TX_PCM2PDM_CONF volatile.Register32 // 0x40 + TX_PCM2PDM_CONF1 volatile.Register32 // 0x44 + _ [8]byte + RX_TDM_CTRL volatile.Register32 // 0x50 + TX_TDM_CTRL volatile.Register32 // 0x54 + RX_TIMING volatile.Register32 // 0x58 + TX_TIMING volatile.Register32 // 0x5C + LC_HUNG_CONF volatile.Register32 // 0x60 + RXEOF_NUM volatile.Register32 // 0x64 + CONF_SIGLE_DATA volatile.Register32 // 0x68 + STATE volatile.Register32 // 0x6C + ETM_CONF volatile.Register32 // 0x70 + _ [12]byte + DATE volatile.Register32 // 0x80 +} + +// I2S.INT_RAW: I2S interrupt raw register, valid in level. +func (o *I2S_Type) SetINT_RAW_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_RAW_RX_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// I2S.INT_ST: I2S interrupt status register. +func (o *I2S_Type) SetINT_ST_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ST_RX_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// I2S.INT_ENA: I2S interrupt enable register. +func (o *I2S_Type) SetINT_ENA_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ENA_RX_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// I2S.INT_CLR: I2S interrupt clear register. +func (o *I2S_Type) SetINT_CLR_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_CLR_RX_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// I2S.RX_CONF: I2S RX configure register +func (o *I2S_Type) SetRX_CONF_RX_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_CONF_RX_RESET() uint32 { + return volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_CONF_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_CONF_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_CONF_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_CONF_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_CONF_RX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_CONF_RX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_CONF_RX_STOP_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetRX_CONF_RX_STOP_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetRX_CONF_RX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_CONF_RX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_CONF_RX_UPDATE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_CONF_RX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_CONF_RX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetRX_CONF_RX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetRX_CONF_RX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_CONF_RX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_CONF_RX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetRX_CONF_RX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetRX_CONF_RX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetRX_CONF_RX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetRX_CONF_RX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetRX_CONF_RX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetRX_CONF_RX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetRX_CONF_RX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetRX_CONF_RX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetRX_CONF_RX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetRX_CONF_RX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x7e00000)|value<<21) +} +func (o *I2S_Type) GetRX_CONF_RX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x7e00000) >> 21 +} + +// I2S.TX_CONF: I2S TX configure register +func (o *I2S_Type) SetTX_CONF_TX_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_CONF_TX_RESET() uint32 { + return volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_CONF_TX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_CONF_TX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_CONF_TX_START(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_CONF_TX_START() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_CONF_TX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_CONF_TX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_CONF_TX_STOP_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetTX_CONF_TX_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_EQUAL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_EQUAL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_CONF_TX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_CONF_TX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_CONF_TX_UPDATE(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_CONF_TX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_CONF_TX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_CONF_TX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_CONF_TX_BCK_NO_DLY(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetTX_CONF_TX_BCK_NO_DLY() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetTX_CONF_TX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_CONF_TX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_CONF_TX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetTX_CONF_TX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetTX_CONF_TX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetTX_CONF_TX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetTX_CONF_TX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetTX_CONF_TX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetTX_CONF_TX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetTX_CONF_TX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetTX_CONF_TX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_CONF_TX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetTX_CONF_TX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x7e00000)|value<<21) +} +func (o *I2S_Type) GetTX_CONF_TX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x7e00000) >> 21 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x38000000)|value<<27) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x38000000) >> 27 +} +func (o *I2S_Type) SetTX_CONF_SIG_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetTX_CONF_SIG_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000000) >> 30 +} + +// I2S.RX_CONF1: I2S RX configure register 1 +func (o *I2S_Type) SetRX_CONF1_RX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1ff +} +func (o *I2S_Type) SetRX_CONF1_RX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7c000)|value<<14) +} +func (o *I2S_Type) GetRX_CONF1_RX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7c000) >> 14 +} +func (o *I2S_Type) SetRX_CONF1_RX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7f80000)|value<<19) +} +func (o *I2S_Type) GetRX_CONF1_RX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7f80000) >> 19 +} +func (o *I2S_Type) SetRX_CONF1_RX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0xf8000000)|value<<27) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0xf8000000) >> 27 +} + +// I2S.TX_CONF1: I2S TX configure register 1 +func (o *I2S_Type) SetTX_CONF1_TX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1ff +} +func (o *I2S_Type) SetTX_CONF1_TX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7c000)|value<<14) +} +func (o *I2S_Type) GetTX_CONF1_TX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7c000) >> 14 +} +func (o *I2S_Type) SetTX_CONF1_TX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7f80000)|value<<19) +} +func (o *I2S_Type) GetTX_CONF1_TX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7f80000) >> 19 +} +func (o *I2S_Type) SetTX_CONF1_TX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0xf8000000)|value<<27) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0xf8000000) >> 27 +} + +// I2S.RX_CLKM_CONF: I2S RX clock configure register +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S_Type) SetRX_CLKM_CONF_MCLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetRX_CLKM_CONF_MCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S.TX_CLKM_CONF: I2S TX clock configure register +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S_Type) SetTX_CLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetTX_CLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S.RX_CLKM_DIV_CONF: I2S RX module clock divider configure register +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.TX_CLKM_DIV_CONF: I2S TX module clock divider configure register +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1e)|value<<1) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1e) >> 1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1fe0)|value<<5) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1fe0) >> 5 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x6000) >> 13 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x18000)|value<<15) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x18000) >> 15 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x60000)|value<<17) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x60000) >> 17 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x180000)|value<<19) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x180000) >> 19 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x400000) >> 22 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x800000) >> 23 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1000000) >> 24 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x2000000) >> 25 +} + +// I2S.TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FP(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3ff)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FP() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3ff +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FS() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x700000)|value<<20) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x700000) >> 20 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3800000) >> 23 +} + +// I2S.RX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} + +// I2S.TX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100000) >> 20 +} + +// I2S.RX_TIMING: I2S RX timing control register +func (o *I2S_Type) SetRX_TIMING_RX_SD_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD_IN_DM() uint32 { + return volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.TX_TIMING: I2S TX timing control register +func (o *I2S_Type) SetTX_TIMING_TX_SD_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD_OUT_DM() uint32 { + return volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetTX_TIMING_TX_SD1_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD1_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.LC_HUNG_CONF: I2S HUNG configure register. +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11 +} + +// I2S.RXEOF_NUM: I2S RX data number control register. +func (o *I2S_Type) SetRXEOF_NUM_RX_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.RXEOF_NUM.Reg, volatile.LoadUint32(&o.RXEOF_NUM.Reg)&^(0xfff)|value) +} +func (o *I2S_Type) GetRXEOF_NUM_RX_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.RXEOF_NUM.Reg) & 0xfff +} + +// I2S.CONF_SIGLE_DATA: I2S signal data register +func (o *I2S_Type) SetCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value) +} +func (o *I2S_Type) GetCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg) +} + +// I2S.STATE: I2S TX status register +func (o *I2S_Type) SetSTATE_TX_IDLE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetSTATE_TX_IDLE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x1 +} + +// I2S.ETM_CONF: I2S ETM configure register +func (o *I2S_Type) SetETM_CONF_ETM_TX_SEND_WORD_NUM(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2S_Type) GetETM_CONF_ETM_TX_SEND_WORD_NUM() uint32 { + return volatile.LoadUint32(&o.ETM_CONF.Reg) & 0x3ff +} +func (o *I2S_Type) SetETM_CONF_ETM_RX_RECEIVE_WORD_NUM(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *I2S_Type) GetETM_CONF_ETM_RX_RECEIVE_WORD_NUM() uint32 { + return (volatile.LoadUint32(&o.ETM_CONF.Reg) & 0xffc00) >> 10 +} + +// I2S.DATE: Version control register +func (o *I2S_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *I2S_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Interrupt Controller (Core 0) +type INTMTX_CORE0_Type struct { + PMU_INTR_MAP volatile.Register32 // 0x0 + EFUSE_INTR_MAP volatile.Register32 // 0x4 + LP_RTC_TIMER_INTR_MAP volatile.Register32 // 0x8 + LP_BLE_TIMER_INTR_MAP volatile.Register32 // 0xC + LP_WDT_INTR_MAP volatile.Register32 // 0x10 + LP_PERI_TIMEOUT_INTR_MAP volatile.Register32 // 0x14 + LP_APM_M0_INTR_MAP volatile.Register32 // 0x18 + CPU_INTR_FROM_CPU_0_MAP volatile.Register32 // 0x1C + CPU_INTR_FROM_CPU_1_MAP volatile.Register32 // 0x20 + CPU_INTR_FROM_CPU_2_MAP volatile.Register32 // 0x24 + CPU_INTR_FROM_CPU_3_MAP volatile.Register32 // 0x28 + ASSIST_DEBUG_INTR_MAP volatile.Register32 // 0x2C + TRACE_INTR_MAP volatile.Register32 // 0x30 + CACHE_INTR_MAP volatile.Register32 // 0x34 + CPU_PERI_TIMEOUT_INTR_MAP volatile.Register32 // 0x38 + BT_MAC_INTR_MAP volatile.Register32 // 0x3C + BT_BB_INTR_MAP volatile.Register32 // 0x40 + BT_BB_NMI_MAP volatile.Register32 // 0x44 + COEX_INTR_MAP volatile.Register32 // 0x48 + BLE_TIMER_INTR_MAP volatile.Register32 // 0x4C + BLE_SEC_INTR_MAP volatile.Register32 // 0x50 + ZB_MAC_INTR_MAP volatile.Register32 // 0x54 + GPIO_INTERRUPT_PRO_MAP volatile.Register32 // 0x58 + GPIO_INTERRUPT_PRO_NMI_MAP volatile.Register32 // 0x5C + PAU_INTR_MAP volatile.Register32 // 0x60 + HP_PERI_TIMEOUT_INTR_MAP volatile.Register32 // 0x64 + HP_APM_M0_INTR_MAP volatile.Register32 // 0x68 + HP_APM_M1_INTR_MAP volatile.Register32 // 0x6C + HP_APM_M2_INTR_MAP volatile.Register32 // 0x70 + HP_APM_M3_INTR_MAP volatile.Register32 // 0x74 + MSPI_INTR_MAP volatile.Register32 // 0x78 + I2S1_INTR_MAP volatile.Register32 // 0x7C + UHCI0_INTR_MAP volatile.Register32 // 0x80 + UART0_INTR_MAP volatile.Register32 // 0x84 + UART1_INTR_MAP volatile.Register32 // 0x88 + LEDC_INTR_MAP volatile.Register32 // 0x8C + CAN0_INTR_MAP volatile.Register32 // 0x90 + USB_INTR_MAP volatile.Register32 // 0x94 + RMT_INTR_MAP volatile.Register32 // 0x98 + I2C_EXT0_INTR_MAP volatile.Register32 // 0x9C + I2C_EXT1_INTR_MAP volatile.Register32 // 0xA0 + TG0_T0_INTR_MAP volatile.Register32 // 0xA4 + TG0_WDT_INTR_MAP volatile.Register32 // 0xA8 + TG1_T0_INTR_MAP volatile.Register32 // 0xAC + TG1_WDT_INTR_MAP volatile.Register32 // 0xB0 + SYSTIMER_TARGET0_INTR_MAP volatile.Register32 // 0xB4 + SYSTIMER_TARGET1_INTR_MAP volatile.Register32 // 0xB8 + SYSTIMER_TARGET2_INTR_MAP volatile.Register32 // 0xBC + APB_ADC_INTR_MAP volatile.Register32 // 0xC0 + PWM_INTR_MAP volatile.Register32 // 0xC4 + PCNT_INTR_MAP volatile.Register32 // 0xC8 + PARL_IO_TX_INTR_MAP volatile.Register32 // 0xCC + PARL_IO_RX_INTR_MAP volatile.Register32 // 0xD0 + DMA_IN_CH0_INTR_MAP volatile.Register32 // 0xD4 + DMA_IN_CH1_INTR_MAP volatile.Register32 // 0xD8 + DMA_IN_CH2_INTR_MAP volatile.Register32 // 0xDC + DMA_OUT_CH0_INTR_MAP volatile.Register32 // 0xE0 + DMA_OUT_CH1_INTR_MAP volatile.Register32 // 0xE4 + DMA_OUT_CH2_INTR_MAP volatile.Register32 // 0xE8 + GPSPI2_INTR_MAP volatile.Register32 // 0xEC + AES_INTR_MAP volatile.Register32 // 0xF0 + SHA_INTR_MAP volatile.Register32 // 0xF4 + RSA_INTR_MAP volatile.Register32 // 0xF8 + ECC_INTR_MAP volatile.Register32 // 0xFC + ECDSA_INTR_MAP volatile.Register32 // 0x100 + INTR_STATUS_REG_0 volatile.Register32 // 0x104 + INTR_STATUS_REG_1 volatile.Register32 // 0x108 + INT_STATUS_REG_2 volatile.Register32 // 0x10C + CLOCK_GATE volatile.Register32 // 0x110 + _ [1768]byte + INTERRUPT_REG_DATE volatile.Register32 // 0x7FC +} + +// INTMTX_CORE0.PMU_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPMU_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PMU_INTR_MAP.Reg, volatile.LoadUint32(&o.PMU_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPMU_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PMU_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.EFUSE_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetEFUSE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.EFUSE_INTR_MAP.Reg, volatile.LoadUint32(&o.EFUSE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetEFUSE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.EFUSE_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_RTC_TIMER_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_RTC_TIMER_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_RTC_TIMER_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_RTC_TIMER_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_RTC_TIMER_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_RTC_TIMER_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_BLE_TIMER_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_BLE_TIMER_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_BLE_TIMER_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_BLE_TIMER_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_BLE_TIMER_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_BLE_TIMER_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_WDT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_WDT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_WDT_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_WDT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_WDT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_WDT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_PERI_TIMEOUT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_PERI_TIMEOUT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_PERI_TIMEOUT_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_PERI_TIMEOUT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_PERI_TIMEOUT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_PERI_TIMEOUT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LP_APM_M0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLP_APM_M0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LP_APM_M0_INTR_MAP.Reg, volatile.LoadUint32(&o.LP_APM_M0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLP_APM_M0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LP_APM_M0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_INTR_FROM_CPU_0_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_INTR_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_INTR_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_INTR_FROM_CPU_1_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_INTR_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_INTR_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_INTR_FROM_CPU_2_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_INTR_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_INTR_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_INTR_FROM_CPU_3_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_INTR_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_INTR_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.ASSIST_DEBUG_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetASSIST_DEBUG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetASSIST_DEBUG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TRACE_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTRACE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TRACE_INTR_MAP.Reg, volatile.LoadUint32(&o.TRACE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTRACE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TRACE_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CACHE_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetCACHE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_INTR_MAP.Reg, volatile.LoadUint32(&o.CACHE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCACHE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CPU_PERI_TIMEOUT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetCPU_PERI_TIMEOUT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_TIMEOUT_INTR_MAP.Reg, volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCPU_PERI_TIMEOUT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_PERI_TIMEOUT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BT_MAC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetBT_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BT_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.BT_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBT_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BT_MAC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BT_BB_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetBT_BB_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_INTR_MAP.Reg, volatile.LoadUint32(&o.BT_BB_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBT_BB_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BT_BB_NMI_MAP: register description +func (o *INTMTX_CORE0_Type) SetBT_BB_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_NMI_MAP.Reg, volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBT_BB_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.COEX_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetCOEX_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.COEX_INTR_MAP.Reg, volatile.LoadUint32(&o.COEX_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCOEX_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.COEX_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BLE_TIMER_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetBLE_TIMER_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BLE_TIMER_INTR_MAP.Reg, volatile.LoadUint32(&o.BLE_TIMER_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBLE_TIMER_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BLE_TIMER_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.BLE_SEC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetBLE_SEC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BLE_SEC_INTR_MAP.Reg, volatile.LoadUint32(&o.BLE_SEC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetBLE_SEC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BLE_SEC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.ZB_MAC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetZB_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ZB_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.ZB_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetZB_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ZB_MAC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.GPIO_INTERRUPT_PRO_MAP: register description +func (o *INTMTX_CORE0_Type) SetGPIO_INTERRUPT_PRO_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetGPIO_INTERRUPT_PRO_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.GPIO_INTERRUPT_PRO_NMI_MAP: register description +func (o *INTMTX_CORE0_Type) SetGPIO_INTERRUPT_PRO_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetGPIO_INTERRUPT_PRO_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PAU_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPAU_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PAU_INTR_MAP.Reg, volatile.LoadUint32(&o.PAU_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPAU_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PAU_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_PERI_TIMEOUT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_PERI_TIMEOUT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_PERI_TIMEOUT_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_PERI_TIMEOUT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_PERI_TIMEOUT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_PERI_TIMEOUT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_APM_M0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_APM_M0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_APM_M0_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_APM_M0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_APM_M0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_APM_M0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_APM_M1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_APM_M1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_APM_M1_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_APM_M1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_APM_M1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_APM_M1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_APM_M2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_APM_M2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_APM_M2_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_APM_M2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_APM_M2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_APM_M2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.HP_APM_M3_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetHP_APM_M3_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.HP_APM_M3_INTR_MAP.Reg, volatile.LoadUint32(&o.HP_APM_M3_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetHP_APM_M3_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.HP_APM_M3_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.MSPI_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetMSPI_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.MSPI_INTR_MAP.Reg, volatile.LoadUint32(&o.MSPI_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetMSPI_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.MSPI_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.I2S1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetI2S1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2S1_INTR_MAP.Reg, volatile.LoadUint32(&o.I2S1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetI2S1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2S1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.UHCI0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetUHCI0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UHCI0_INTR_MAP.Reg, volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetUHCI0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.UART0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetUART0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART0_INTR_MAP.Reg, volatile.LoadUint32(&o.UART0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetUART0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.UART1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetUART1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART1_INTR_MAP.Reg, volatile.LoadUint32(&o.UART1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetUART1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.LEDC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetLEDC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.LEDC_INTR_MAP.Reg, volatile.LoadUint32(&o.LEDC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetLEDC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.LEDC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.CAN0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetCAN0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CAN0_INTR_MAP.Reg, volatile.LoadUint32(&o.CAN0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetCAN0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CAN0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.USB_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetUSB_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.USB_INTR_MAP.Reg, volatile.LoadUint32(&o.USB_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetUSB_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.USB_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.RMT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetRMT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RMT_INTR_MAP.Reg, volatile.LoadUint32(&o.RMT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetRMT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RMT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.I2C_EXT0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetI2C_EXT0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_EXT0_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetI2C_EXT0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.I2C_EXT1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetI2C_EXT1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_EXT1_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_EXT1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetI2C_EXT1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_EXT1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG0_T0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG0_T0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG0_T0_INTR_MAP.Reg, volatile.LoadUint32(&o.TG0_T0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG0_T0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG0_T0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG0_WDT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG0_WDT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG0_WDT_INTR_MAP.Reg, volatile.LoadUint32(&o.TG0_WDT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG0_WDT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG0_WDT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG1_T0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG1_T0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_T0_INTR_MAP.Reg, volatile.LoadUint32(&o.TG1_T0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG1_T0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_T0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.TG1_WDT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetTG1_WDT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_WDT_INTR_MAP.Reg, volatile.LoadUint32(&o.TG1_WDT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetTG1_WDT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_WDT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SYSTIMER_TARGET0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSYSTIMER_TARGET0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET0_INTR_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSYSTIMER_TARGET0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SYSTIMER_TARGET1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSYSTIMER_TARGET1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET1_INTR_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSYSTIMER_TARGET1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SYSTIMER_TARGET2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSYSTIMER_TARGET2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET2_INTR_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSYSTIMER_TARGET2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.APB_ADC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetAPB_ADC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APB_ADC_INTR_MAP.Reg, volatile.LoadUint32(&o.APB_ADC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetAPB_ADC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APB_ADC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PWM_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPWM_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPWM_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PCNT_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPCNT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PCNT_INTR_MAP.Reg, volatile.LoadUint32(&o.PCNT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPCNT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PCNT_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PARL_IO_TX_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPARL_IO_TX_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PARL_IO_TX_INTR_MAP.Reg, volatile.LoadUint32(&o.PARL_IO_TX_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPARL_IO_TX_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PARL_IO_TX_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.PARL_IO_RX_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetPARL_IO_RX_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PARL_IO_RX_INTR_MAP.Reg, volatile.LoadUint32(&o.PARL_IO_RX_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetPARL_IO_RX_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PARL_IO_RX_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_IN_CH0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_IN_CH0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH0_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_IN_CH0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_IN_CH1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_IN_CH1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH1_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_IN_CH1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_IN_CH2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_IN_CH2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH2_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_IN_CH2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_OUT_CH0_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_OUT_CH0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH0_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_OUT_CH0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH0_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_OUT_CH1_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_OUT_CH1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH1_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_OUT_CH1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH1_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.DMA_OUT_CH2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetDMA_OUT_CH2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH2_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetDMA_OUT_CH2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.GPSPI2_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetGPSPI2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.GPSPI2_INTR_MAP.Reg, volatile.LoadUint32(&o.GPSPI2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetGPSPI2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.GPSPI2_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.AES_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetAES_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.AES_INTR_MAP.Reg, volatile.LoadUint32(&o.AES_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetAES_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.AES_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.SHA_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetSHA_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SHA_INTR_MAP.Reg, volatile.LoadUint32(&o.SHA_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetSHA_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SHA_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.RSA_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetRSA_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RSA_INTR_MAP.Reg, volatile.LoadUint32(&o.RSA_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetRSA_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RSA_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.ECC_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetECC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ECC_INTR_MAP.Reg, volatile.LoadUint32(&o.ECC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetECC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ECC_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.ECDSA_INTR_MAP: register description +func (o *INTMTX_CORE0_Type) SetECDSA_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ECDSA_INTR_MAP.Reg, volatile.LoadUint32(&o.ECDSA_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTMTX_CORE0_Type) GetECDSA_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ECDSA_INTR_MAP.Reg) & 0x1f +} + +// INTMTX_CORE0.INTR_STATUS_REG_0: register description +func (o *INTMTX_CORE0_Type) SetINTR_STATUS_REG_0(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_0.Reg, value) +} +func (o *INTMTX_CORE0_Type) GetINTR_STATUS_REG_0() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_0.Reg) +} + +// INTMTX_CORE0.INTR_STATUS_REG_1: register description +func (o *INTMTX_CORE0_Type) SetINTR_STATUS_REG_1(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_1.Reg, value) +} +func (o *INTMTX_CORE0_Type) GetINTR_STATUS_REG_1() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_1.Reg) +} + +// INTMTX_CORE0.INT_STATUS_REG_2: register description +func (o *INTMTX_CORE0_Type) SetINT_STATUS_REG_2(value uint32) { + volatile.StoreUint32(&o.INT_STATUS_REG_2.Reg, value) +} +func (o *INTMTX_CORE0_Type) GetINT_STATUS_REG_2() uint32 { + return volatile.LoadUint32(&o.INT_STATUS_REG_2.Reg) +} + +// INTMTX_CORE0.CLOCK_GATE: register description +func (o *INTMTX_CORE0_Type) SetCLOCK_GATE_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *INTMTX_CORE0_Type) GetCLOCK_GATE_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// INTMTX_CORE0.INTERRUPT_REG_DATE: register description +func (o *INTMTX_CORE0_Type) SetINTERRUPT_REG_DATE(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_REG_DATE.Reg, volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *INTMTX_CORE0_Type) GetINTERRUPT_REG_DATE() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg) & 0xfffffff +} + +// INTPRI Peripheral +type INTPRI_Type struct { + CPU_INT_ENABLE volatile.Register32 // 0x0 + CPU_INT_TYPE volatile.Register32 // 0x4 + CPU_INT_EIP_STATUS volatile.Register32 // 0x8 + CPU_INT_PRI_0 volatile.Register32 // 0xC + CPU_INT_PRI_1 volatile.Register32 // 0x10 + CPU_INT_PRI_2 volatile.Register32 // 0x14 + CPU_INT_PRI_3 volatile.Register32 // 0x18 + CPU_INT_PRI_4 volatile.Register32 // 0x1C + CPU_INT_PRI_5 volatile.Register32 // 0x20 + CPU_INT_PRI_6 volatile.Register32 // 0x24 + CPU_INT_PRI_7 volatile.Register32 // 0x28 + CPU_INT_PRI_8 volatile.Register32 // 0x2C + CPU_INT_PRI_9 volatile.Register32 // 0x30 + CPU_INT_PRI_10 volatile.Register32 // 0x34 + CPU_INT_PRI_11 volatile.Register32 // 0x38 + CPU_INT_PRI_12 volatile.Register32 // 0x3C + CPU_INT_PRI_13 volatile.Register32 // 0x40 + CPU_INT_PRI_14 volatile.Register32 // 0x44 + CPU_INT_PRI_15 volatile.Register32 // 0x48 + CPU_INT_PRI_16 volatile.Register32 // 0x4C + CPU_INT_PRI_17 volatile.Register32 // 0x50 + CPU_INT_PRI_18 volatile.Register32 // 0x54 + CPU_INT_PRI_19 volatile.Register32 // 0x58 + CPU_INT_PRI_20 volatile.Register32 // 0x5C + CPU_INT_PRI_21 volatile.Register32 // 0x60 + CPU_INT_PRI_22 volatile.Register32 // 0x64 + CPU_INT_PRI_23 volatile.Register32 // 0x68 + CPU_INT_PRI_24 volatile.Register32 // 0x6C + CPU_INT_PRI_25 volatile.Register32 // 0x70 + CPU_INT_PRI_26 volatile.Register32 // 0x74 + CPU_INT_PRI_27 volatile.Register32 // 0x78 + CPU_INT_PRI_28 volatile.Register32 // 0x7C + CPU_INT_PRI_29 volatile.Register32 // 0x80 + CPU_INT_PRI_30 volatile.Register32 // 0x84 + CPU_INT_PRI_31 volatile.Register32 // 0x88 + CPU_INT_THRESH volatile.Register32 // 0x8C + CPU_INTR_FROM_CPU_0 volatile.Register32 // 0x90 + CPU_INTR_FROM_CPU_1 volatile.Register32 // 0x94 + CPU_INTR_FROM_CPU_2 volatile.Register32 // 0x98 + CPU_INTR_FROM_CPU_3 volatile.Register32 // 0x9C + DATE volatile.Register32 // 0xA0 + CLOCK_GATE volatile.Register32 // 0xA4 + CPU_INT_CLEAR volatile.Register32 // 0xA8 + RND_ECO volatile.Register32 // 0xAC + RND_ECO_LOW volatile.Register32 // 0xB0 + _ [840]byte + RND_ECO_HIGH volatile.Register32 // 0x3FC +} + +// INTPRI.CPU_INT_ENABLE: register description +func (o *INTPRI_Type) SetCPU_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.CPU_INT_ENABLE.Reg, value) +} +func (o *INTPRI_Type) GetCPU_INT_ENABLE() uint32 { + return volatile.LoadUint32(&o.CPU_INT_ENABLE.Reg) +} + +// INTPRI.CPU_INT_TYPE: register description +func (o *INTPRI_Type) SetCPU_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.CPU_INT_TYPE.Reg, value) +} +func (o *INTPRI_Type) GetCPU_INT_TYPE() uint32 { + return volatile.LoadUint32(&o.CPU_INT_TYPE.Reg) +} + +// INTPRI.CPU_INT_EIP_STATUS: register description +func (o *INTPRI_Type) SetCPU_INT_EIP_STATUS(value uint32) { + volatile.StoreUint32(&o.CPU_INT_EIP_STATUS.Reg, value) +} +func (o *INTPRI_Type) GetCPU_INT_EIP_STATUS() uint32 { + return volatile.LoadUint32(&o.CPU_INT_EIP_STATUS.Reg) +} + +// INTPRI.CPU_INT_PRI_0: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_0_CPU_PRI_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_0.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_0.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_0_CPU_PRI_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_0.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_1: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_1_CPU_PRI_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_1.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_1.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_1_CPU_PRI_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_1.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_2: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_2_CPU_PRI_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_2.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_2.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_2_CPU_PRI_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_2.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_3: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_3_CPU_PRI_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_3.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_3.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_3_CPU_PRI_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_3.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_4: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_4_CPU_PRI_4_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_4.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_4.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_4_CPU_PRI_4_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_4.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_5: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_5_CPU_PRI_5_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_5.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_5.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_5_CPU_PRI_5_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_5.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_6: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_6_CPU_PRI_6_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_6.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_6.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_6_CPU_PRI_6_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_6.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_7: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_7_CPU_PRI_7_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_7.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_7.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_7_CPU_PRI_7_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_7.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_8: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_8_CPU_PRI_8_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_8.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_8.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_8_CPU_PRI_8_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_8.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_9: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_9_CPU_PRI_9_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_9.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_9.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_9_CPU_PRI_9_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_9.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_10: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_10_CPU_PRI_10_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_10.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_10.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_10_CPU_PRI_10_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_10.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_11: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_11_CPU_PRI_11_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_11.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_11.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_11_CPU_PRI_11_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_11.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_12: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_12_CPU_PRI_12_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_12.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_12.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_12_CPU_PRI_12_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_12.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_13: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_13_CPU_PRI_13_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_13.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_13.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_13_CPU_PRI_13_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_13.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_14: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_14_CPU_PRI_14_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_14.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_14.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_14_CPU_PRI_14_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_14.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_15: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_15_CPU_PRI_15_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_15.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_15.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_15_CPU_PRI_15_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_15.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_16: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_16_CPU_PRI_16_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_16.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_16.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_16_CPU_PRI_16_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_16.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_17: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_17_CPU_PRI_17_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_17.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_17.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_17_CPU_PRI_17_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_17.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_18: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_18_CPU_PRI_18_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_18.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_18.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_18_CPU_PRI_18_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_18.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_19: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_19_CPU_PRI_19_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_19.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_19.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_19_CPU_PRI_19_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_19.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_20: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_20_CPU_PRI_20_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_20.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_20.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_20_CPU_PRI_20_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_20.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_21: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_21_CPU_PRI_21_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_21.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_21.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_21_CPU_PRI_21_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_21.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_22: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_22_CPU_PRI_22_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_22.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_22.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_22_CPU_PRI_22_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_22.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_23: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_23_CPU_PRI_23_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_23.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_23.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_23_CPU_PRI_23_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_23.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_24: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_24_CPU_PRI_24_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_24.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_24.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_24_CPU_PRI_24_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_24.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_25: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_25_CPU_PRI_25_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_25.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_25.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_25_CPU_PRI_25_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_25.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_26: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_26_CPU_PRI_26_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_26.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_26.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_26_CPU_PRI_26_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_26.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_27: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_27_CPU_PRI_27_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_27.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_27.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_27_CPU_PRI_27_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_27.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_28: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_28_CPU_PRI_28_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_28.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_28.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_28_CPU_PRI_28_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_28.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_29: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_29_CPU_PRI_29_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_29.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_29.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_29_CPU_PRI_29_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_29.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_30: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_30_CPU_PRI_30_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_30.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_30.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_30_CPU_PRI_30_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_30.Reg) & 0xf +} + +// INTPRI.CPU_INT_PRI_31: register description +func (o *INTPRI_Type) SetCPU_INT_PRI_31_CPU_PRI_31_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_PRI_31.Reg, volatile.LoadUint32(&o.CPU_INT_PRI_31.Reg)&^(0xf)|value) +} +func (o *INTPRI_Type) GetCPU_INT_PRI_31_CPU_PRI_31_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_PRI_31.Reg) & 0xf +} + +// INTPRI.CPU_INT_THRESH: register description +func (o *INTPRI_Type) SetCPU_INT_THRESH(value uint32) { + volatile.StoreUint32(&o.CPU_INT_THRESH.Reg, volatile.LoadUint32(&o.CPU_INT_THRESH.Reg)&^(0xff)|value) +} +func (o *INTPRI_Type) GetCPU_INT_THRESH() uint32 { + return volatile.LoadUint32(&o.CPU_INT_THRESH.Reg) & 0xff +} + +// INTPRI.CPU_INTR_FROM_CPU_0: register description +func (o *INTPRI_Type) SetCPU_INTR_FROM_CPU_0(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCPU_INTR_FROM_CPU_0() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg) & 0x1 +} + +// INTPRI.CPU_INTR_FROM_CPU_1: register description +func (o *INTPRI_Type) SetCPU_INTR_FROM_CPU_1(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCPU_INTR_FROM_CPU_1() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg) & 0x1 +} + +// INTPRI.CPU_INTR_FROM_CPU_2: register description +func (o *INTPRI_Type) SetCPU_INTR_FROM_CPU_2(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCPU_INTR_FROM_CPU_2() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg) & 0x1 +} + +// INTPRI.CPU_INTR_FROM_CPU_3: register description +func (o *INTPRI_Type) SetCPU_INTR_FROM_CPU_3(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCPU_INTR_FROM_CPU_3() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg) & 0x1 +} + +// INTPRI.DATE: register description +func (o *INTPRI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *INTPRI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// INTPRI.CLOCK_GATE: register description +func (o *INTPRI_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// INTPRI.CPU_INT_CLEAR: register description +func (o *INTPRI_Type) SetCPU_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.CPU_INT_CLEAR.Reg, value) +} +func (o *INTPRI_Type) GetCPU_INT_CLEAR() uint32 { + return volatile.LoadUint32(&o.CPU_INT_CLEAR.Reg) +} + +// INTPRI.RND_ECO: redcy eco register. +func (o *INTPRI_Type) SetRND_ECO_REDCY_ENA(value uint32) { + volatile.StoreUint32(&o.RND_ECO.Reg, volatile.LoadUint32(&o.RND_ECO.Reg)&^(0x1)|value) +} +func (o *INTPRI_Type) GetRND_ECO_REDCY_ENA() uint32 { + return volatile.LoadUint32(&o.RND_ECO.Reg) & 0x1 +} +func (o *INTPRI_Type) SetRND_ECO_REDCY_RESULT(value uint32) { + volatile.StoreUint32(&o.RND_ECO.Reg, volatile.LoadUint32(&o.RND_ECO.Reg)&^(0x2)|value<<1) +} +func (o *INTPRI_Type) GetRND_ECO_REDCY_RESULT() uint32 { + return (volatile.LoadUint32(&o.RND_ECO.Reg) & 0x2) >> 1 +} + +// INTPRI.RND_ECO_LOW: redcy eco low register. +func (o *INTPRI_Type) SetRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value) +} +func (o *INTPRI_Type) GetRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RND_ECO_LOW.Reg) +} + +// INTPRI.RND_ECO_HIGH: redcy eco high register. +func (o *INTPRI_Type) SetRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value) +} +func (o *INTPRI_Type) GetRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg) +} + +// Input/Output Multiplexer +type IO_MUX_Type struct { + PIN_CTRL volatile.Register32 // 0x0 + GPIO0 volatile.Register32 // 0x4 + GPIO1 volatile.Register32 // 0x8 + GPIO2 volatile.Register32 // 0xC + GPIO3 volatile.Register32 // 0x10 + GPIO4 volatile.Register32 // 0x14 + GPIO5 volatile.Register32 // 0x18 + GPIO6 volatile.Register32 // 0x1C + GPIO7 volatile.Register32 // 0x20 + GPIO8 volatile.Register32 // 0x24 + GPIO9 volatile.Register32 // 0x28 + GPIO10 volatile.Register32 // 0x2C + GPIO11 volatile.Register32 // 0x30 + GPIO12 volatile.Register32 // 0x34 + GPIO13 volatile.Register32 // 0x38 + GPIO14 volatile.Register32 // 0x3C + GPIO15 volatile.Register32 // 0x40 + GPIO16 volatile.Register32 // 0x44 + GPIO17 volatile.Register32 // 0x48 + GPIO18 volatile.Register32 // 0x4C + GPIO19 volatile.Register32 // 0x50 + GPIO20 volatile.Register32 // 0x54 + GPIO21 volatile.Register32 // 0x58 + GPIO22 volatile.Register32 // 0x5C + GPIO23 volatile.Register32 // 0x60 + GPIO24 volatile.Register32 // 0x64 + GPIO25 volatile.Register32 // 0x68 + GPIO26 volatile.Register32 // 0x6C + GPIO27 volatile.Register32 // 0x70 + _ [72]byte + MODEM_DIAG_EN volatile.Register32 // 0xBC + _ [60]byte + DATE volatile.Register32 // 0xFC +} + +// IO_MUX.PIN_CTRL: Clock Output Configuration Register +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT1(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0x1f)|value) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT1() uint32 { + return volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0x1f +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT2(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0x3e0)|value<<5) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT2() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0x3e0) >> 5 +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT3(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0x7c00)|value<<10) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT3() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0x7c00) >> 10 +} + +// IO_MUX.GPIO0: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO0_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO0_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO0_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO0_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO1: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO1_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO1_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO1_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO1_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO2: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO2_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO2_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO2_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO2_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO3: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO3_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO3_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO3_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO3_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO4: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO4_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO4_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO4_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO4_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO5: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO5_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO5_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO5_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO5_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO6: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO6_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO6_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO6_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO6_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO7: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO7_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO7_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO7_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO7_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO8: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO8_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO8.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO8_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO8_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO8_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO8_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO8_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO8_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO9: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO9_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO9.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO9_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO9_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO9_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO9_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO9_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO9_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO10: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO10_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO10.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO10_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO10_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO10_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO10_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO10_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO10_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO11: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO11_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO11.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO11_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO11_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO11_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO11_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO11_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO11_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO12: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO12_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO12.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO12_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO12_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO12_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO12_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO12_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO12_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO13: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO13_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO13.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO13_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO13_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO13_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO13_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO13_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO13_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO14: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO14_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO14.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO14_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO14_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO14_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO14_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO14_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO14_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO15: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO15_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO15.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO15_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO15_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO15_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO15_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO15_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO15_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO15_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO15_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO16: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO16_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO16.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO16_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO16_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO16_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO16_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO16_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO16_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO16_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO16_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO17: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO17_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO17.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO17_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO17_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO17_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO17_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO17_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO17_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO17_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO17_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO18: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO18_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO18.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO18_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO18_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO18_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO18_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO18_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO18_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO18_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO18_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO19: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO19_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO19.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO19_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO19_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO19_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO19_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO19_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO19_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO20: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO20_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO20.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO20_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO20_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO20_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO20_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO20_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO20_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO21: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO21_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO21.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO21_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO21_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO21_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO21_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO21_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO21_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO22: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO22_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO22.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO22_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO22_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO22_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO22_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO22_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO22_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO22_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO22_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO23: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO23_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO23.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO23_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO23_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO23_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO23_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO23_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO23_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO23_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO23_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO24: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO24_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO24.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO24_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO24_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO24_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO24_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO24_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO24_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO24_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO24_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO25: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO25_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO25.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO25_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO25_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO25_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO25_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO25_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO25_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO25_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO25_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO26: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO26_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO26.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO26_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO26_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO26_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO26_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO26_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO26_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO26_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO26_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x20000) >> 17 +} + +// IO_MUX.GPIO27: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO27_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO27.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO27_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO27_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO27_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO27_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8000) >> 15 +} +func (o *IO_MUX_Type) SetGPIO27_HYS_EN(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x10000)|value<<16) +} +func (o *IO_MUX_Type) GetGPIO27_HYS_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x10000) >> 16 +} +func (o *IO_MUX_Type) SetGPIO27_HYS_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x20000)|value<<17) +} +func (o *IO_MUX_Type) GetGPIO27_HYS_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x20000) >> 17 +} + +// IO_MUX.MODEM_DIAG_EN: GPIO MATRIX Configure Register for modem diag +func (o *IO_MUX_Type) SetMODEM_DIAG_EN(value uint32) { + volatile.StoreUint32(&o.MODEM_DIAG_EN.Reg, value) +} +func (o *IO_MUX_Type) GetMODEM_DIAG_EN() uint32 { + return volatile.LoadUint32(&o.MODEM_DIAG_EN.Reg) +} + +// IO_MUX.DATE: IO MUX Version Control Register +func (o *IO_MUX_Type) SetDATE_REG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *IO_MUX_Type) GetDATE_REG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LED Control PWM (Pulse Width Modulation) +type LEDC_Type struct { + CH0_CONF0 volatile.Register32 // 0x0 + CH0_HPOINT volatile.Register32 // 0x4 + CH0_DUTY volatile.Register32 // 0x8 + CH0_CONF1 volatile.Register32 // 0xC + CH0_DUTY_R volatile.Register32 // 0x10 + CH1_CONF0 volatile.Register32 // 0x14 + CH1_HPOINT volatile.Register32 // 0x18 + CH1_DUTY volatile.Register32 // 0x1C + CH1_CONF1 volatile.Register32 // 0x20 + CH1_DUTY_R volatile.Register32 // 0x24 + CH2_CONF0 volatile.Register32 // 0x28 + CH2_HPOINT volatile.Register32 // 0x2C + CH2_DUTY volatile.Register32 // 0x30 + CH2_CONF1 volatile.Register32 // 0x34 + CH2_DUTY_R volatile.Register32 // 0x38 + CH3_CONF0 volatile.Register32 // 0x3C + CH3_HPOINT volatile.Register32 // 0x40 + CH3_DUTY volatile.Register32 // 0x44 + CH3_CONF1 volatile.Register32 // 0x48 + CH3_DUTY_R volatile.Register32 // 0x4C + CH4_CONF0 volatile.Register32 // 0x50 + CH4_HPOINT volatile.Register32 // 0x54 + CH4_DUTY volatile.Register32 // 0x58 + CH4_CONF1 volatile.Register32 // 0x5C + CH4_DUTY_R volatile.Register32 // 0x60 + CH5_CONF0 volatile.Register32 // 0x64 + CH5_HPOINT volatile.Register32 // 0x68 + CH5_DUTY volatile.Register32 // 0x6C + CH5_CONF1 volatile.Register32 // 0x70 + CH5_DUTY_R volatile.Register32 // 0x74 + _ [40]byte + TIMER0_CONF volatile.Register32 // 0xA0 + TIMER0_VALUE volatile.Register32 // 0xA4 + TIMER1_CONF volatile.Register32 // 0xA8 + TIMER1_VALUE volatile.Register32 // 0xAC + TIMER2_CONF volatile.Register32 // 0xB0 + TIMER2_VALUE volatile.Register32 // 0xB4 + TIMER3_CONF volatile.Register32 // 0xB8 + TIMER3_VALUE volatile.Register32 // 0xBC + INT_RAW volatile.Register32 // 0xC0 + INT_ST volatile.Register32 // 0xC4 + INT_ENA volatile.Register32 // 0xC8 + INT_CLR volatile.Register32 // 0xCC + _ [48]byte + CH0_GAMMA_WR volatile.Register32 // 0x100 + CH0_GAMMA_WR_ADDR volatile.Register32 // 0x104 + CH0_GAMMA_RD_ADDR volatile.Register32 // 0x108 + CH0_GAMMA_RD_DATA volatile.Register32 // 0x10C + CH1_GAMMA_WR volatile.Register32 // 0x110 + CH1_GAMMA_WR_ADDR volatile.Register32 // 0x114 + CH1_GAMMA_RD_ADDR volatile.Register32 // 0x118 + CH1_GAMMA_RD_DATA volatile.Register32 // 0x11C + CH2_GAMMA_WR volatile.Register32 // 0x120 + CH2_GAMMA_WR_ADDR volatile.Register32 // 0x124 + CH2_GAMMA_RD_ADDR volatile.Register32 // 0x128 + CH2_GAMMA_RD_DATA volatile.Register32 // 0x12C + CH3_GAMMA_WR volatile.Register32 // 0x130 + CH3_GAMMA_WR_ADDR volatile.Register32 // 0x134 + CH3_GAMMA_RD_ADDR volatile.Register32 // 0x138 + CH3_GAMMA_RD_DATA volatile.Register32 // 0x13C + CH4_GAMMA_WR volatile.Register32 // 0x140 + CH4_GAMMA_WR_ADDR volatile.Register32 // 0x144 + CH4_GAMMA_RD_ADDR volatile.Register32 // 0x148 + CH4_GAMMA_RD_DATA volatile.Register32 // 0x14C + CH5_GAMMA_WR volatile.Register32 // 0x150 + CH5_GAMMA_WR_ADDR volatile.Register32 // 0x154 + CH5_GAMMA_RD_ADDR volatile.Register32 // 0x158 + CH5_GAMMA_RD_DATA volatile.Register32 // 0x15C + _ [32]byte + CH0_GAMMA_CONF volatile.Register32 // 0x180 + CH1_GAMMA_CONF volatile.Register32 // 0x184 + CH2_GAMMA_CONF volatile.Register32 // 0x188 + CH3_GAMMA_CONF volatile.Register32 // 0x18C + CH4_GAMMA_CONF volatile.Register32 // 0x190 + CH5_GAMMA_CONF volatile.Register32 // 0x194 + _ [8]byte + EVT_TASK_EN0 volatile.Register32 // 0x1A0 + EVT_TASK_EN1 volatile.Register32 // 0x1A4 + EVT_TASK_EN2 volatile.Register32 // 0x1A8 + _ [4]byte + TIMER0_CMP volatile.Register32 // 0x1B0 + TIMER1_CMP volatile.Register32 // 0x1B4 + TIMER2_CMP volatile.Register32 // 0x1B8 + TIMER3_CMP volatile.Register32 // 0x1BC + TIMER0_CNT_CAP volatile.Register32 // 0x1C0 + TIMER1_CNT_CAP volatile.Register32 // 0x1C4 + TIMER2_CNT_CAP volatile.Register32 // 0x1C8 + TIMER3_CNT_CAP volatile.Register32 // 0x1CC + _ [32]byte + CONF volatile.Register32 // 0x1F0 + _ [8]byte + DATE volatile.Register32 // 0x1FC +} + +// LEDC.CH0_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH0_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH0_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH0_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH0_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH0_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH0_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH0_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH0_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH0_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH0_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH0_HPOINT.Reg, volatile.LoadUint32(&o.CH0_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH0_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH0_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH0_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY.Reg, volatile.LoadUint32(&o.CH0_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH0_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH0_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH0_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY_R.Reg, volatile.LoadUint32(&o.CH0_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH1_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH1_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH1_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH1_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH1_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH1_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH1_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH1_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH1_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH1_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH1_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH1_HPOINT.Reg, volatile.LoadUint32(&o.CH1_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH1_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH1_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH1_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY.Reg, volatile.LoadUint32(&o.CH1_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH1_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH1_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH1_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY_R.Reg, volatile.LoadUint32(&o.CH1_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH2_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH2_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH2_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH2_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH2_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH2_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH2_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH2_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH2_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH2_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH2_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH2_HPOINT.Reg, volatile.LoadUint32(&o.CH2_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH2_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH2_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH2_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY.Reg, volatile.LoadUint32(&o.CH2_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH2_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH2_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH2_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY_R.Reg, volatile.LoadUint32(&o.CH2_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH3_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH3_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH3_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH3_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH3_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH3_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH3_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH3_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH3_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH3_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH3_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH3_HPOINT.Reg, volatile.LoadUint32(&o.CH3_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH3_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH3_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH3_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY.Reg, volatile.LoadUint32(&o.CH3_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH3_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH3_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH3_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY_R.Reg, volatile.LoadUint32(&o.CH3_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH4_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH4_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH4_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH4_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH4_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH4_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH4_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH4_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH4_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH4_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH4_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH4_HPOINT.Reg, volatile.LoadUint32(&o.CH4_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH4_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH4_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH4_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY.Reg, volatile.LoadUint32(&o.CH4_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH4_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH4_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH4_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY_R.Reg, volatile.LoadUint32(&o.CH4_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH5_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH5_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH5_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH5_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH5_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH5_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH5_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH5_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH5_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH5_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH5_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH5_HPOINT.Reg, volatile.LoadUint32(&o.CH5_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH5_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH5_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH5_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY.Reg, volatile.LoadUint32(&o.CH5_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH5_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH5_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH5_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY_R.Reg, volatile.LoadUint32(&o.CH5_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.TIMER0_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER0_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER0_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER0_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER0_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER0_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER0_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER0_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER0_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER0_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER0_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER0_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER0_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER0_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER0_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER0_VALUE.Reg, volatile.LoadUint32(&o.TIMER0_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER0_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER0_VALUE.Reg) & 0xfffff +} + +// LEDC.TIMER1_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER1_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER1_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER1_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER1_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER1_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER1_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER1_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER1_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER1_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER1_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER1_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER1_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER1_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER1_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER1_VALUE.Reg, volatile.LoadUint32(&o.TIMER1_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER1_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER1_VALUE.Reg) & 0xfffff +} + +// LEDC.TIMER2_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER2_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER2_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER2_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER2_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER2_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER2_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER2_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER2_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER2_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER2_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER2_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER2_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER2_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER2_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER2_VALUE.Reg, volatile.LoadUint32(&o.TIMER2_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER2_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER2_VALUE.Reg) & 0xfffff +} + +// LEDC.TIMER3_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER3_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER3_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER3_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER3_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER3_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER3_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER3_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER3_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER3_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER3_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER3_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER3_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER3_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER3_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER3_VALUE.Reg, volatile.LoadUint32(&o.TIMER3_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER3_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER3_VALUE.Reg) & 0xfffff +} + +// LEDC.INT_RAW: Raw interrupt status +func (o *LEDC_Type) SetINT_RAW_TIMER0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_RAW_TIMER0_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_RAW_TIMER1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_RAW_TIMER2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_RAW_TIMER3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_RAW_TIMER3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} + +// LEDC.INT_ST: Masked interrupt status +func (o *LEDC_Type) SetINT_ST_TIMER0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ST_TIMER0_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ST_TIMER1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ST_TIMER1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ST_TIMER2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ST_TIMER2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ST_TIMER3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ST_TIMER3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} + +// LEDC.INT_ENA: Interrupt enable bits +func (o *LEDC_Type) SetINT_ENA_TIMER0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ENA_TIMER0_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ENA_TIMER1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ENA_TIMER2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ENA_TIMER3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ENA_TIMER3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} + +// LEDC.INT_CLR: Interrupt clear bits +func (o *LEDC_Type) SetINT_CLR_TIMER0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_CLR_TIMER0_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_CLR_TIMER1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_CLR_TIMER2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_CLR_TIMER3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_CLR_TIMER3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} + +// LEDC.CH0_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH0_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH0_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH0_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH0_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH0_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH0_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH0_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH0_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH0_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH0_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH0_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH0_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH1_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH1_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH1_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH1_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH1_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH1_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH1_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH1_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH1_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH1_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH1_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH1_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH1_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH2_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH2_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH2_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH2_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH2_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH2_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH2_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH2_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH2_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH2_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH2_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH2_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH2_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH3_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH3_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH3_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH3_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH3_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH3_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH3_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH3_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH3_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH3_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH3_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH3_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH3_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH4_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH4_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH4_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH4_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH4_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH4_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH4_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH4_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH4_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH4_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH4_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH4_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH4_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH5_GAMMA_WR: Ledc ch%s gamma ram write register. +func (o *LEDC_Type) SetCH5_GAMMA_WR_CH_GAMMA_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_CH_GAMMA_DUTY_INC() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg) & 0x1 +} +func (o *LEDC_Type) SetCH5_GAMMA_WR_CH_GAMMA_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg)&^(0x7fe)|value<<1) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_CH_GAMMA_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg) & 0x7fe) >> 1 +} +func (o *LEDC_Type) SetCH5_GAMMA_WR_CH_GAMMA_SCALE(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg)&^(0x1ff800)|value<<11) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_CH_GAMMA_SCALE() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg) & 0x1ff800) >> 11 +} +func (o *LEDC_Type) SetCH5_GAMMA_WR_CH_GAMMA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_CH_GAMMA_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_WR.Reg) & 0x7fe00000) >> 21 +} + +// LEDC.CH5_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. +func (o *LEDC_Type) SetCH5_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_WR_ADDR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_WR_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_WR_ADDR.Reg) & 0xf +} + +// LEDC.CH5_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. +func (o *LEDC_Type) SetCH5_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_RD_ADDR.Reg, volatile.LoadUint32(&o.CH5_GAMMA_RD_ADDR.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_RD_ADDR.Reg) & 0xf +} + +// LEDC.CH5_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. +func (o *LEDC_Type) SetCH5_GAMMA_RD_DATA_CH_GAMMA_RD_DATA(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_RD_DATA.Reg, volatile.LoadUint32(&o.CH5_GAMMA_RD_DATA.Reg)&^(0x7fffffff)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_RD_DATA_CH_GAMMA_RD_DATA() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_RD_DATA.Reg) & 0x7fffffff +} + +// LEDC.CH0_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH1_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH2_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH3_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH4_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH5_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.EVT_TASK_EN0: Ledc event task enable bit register0. +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN() uint32 { + return volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME0_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME0_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME1_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME1_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME2_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME2_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME3_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME3_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4000000) >> 26 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8000000) >> 27 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10000000) >> 28 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20000000) >> 29 +} + +// LEDC.EVT_TASK_EN1: Ledc event task enable bit register1. +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN() uint32 { + return volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4000000) >> 26 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8000000)|value<<27) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8000000) >> 27 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10000000)|value<<28) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10000000) >> 28 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20000000)|value<<29) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20000000) >> 29 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80000000) >> 31 +} + +// LEDC.EVT_TASK_EN2: Ledc event task enable bit register2. +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN() uint32 { + return volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x1 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x200000) >> 21 +} + +// LEDC.TIMER0_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER0_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CMP.Reg, volatile.LoadUint32(&o.TIMER0_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER0_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER0_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER1_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER1_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CMP.Reg, volatile.LoadUint32(&o.TIMER1_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER1_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER1_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER2_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER2_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CMP.Reg, volatile.LoadUint32(&o.TIMER2_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER2_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER2_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER3_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER3_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CMP.Reg, volatile.LoadUint32(&o.TIMER3_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER3_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER3_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER0_CNT_CAP: Ledc timer%s count value capture register. +func (o *LEDC_Type) SetTIMER0_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER0_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER0_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER0_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.TIMER1_CNT_CAP: Ledc timer%s count value capture register. +func (o *LEDC_Type) SetTIMER1_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER1_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER1_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER1_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.TIMER2_CNT_CAP: Ledc timer%s count value capture register. +func (o *LEDC_Type) SetTIMER2_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER2_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER2_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER2_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.TIMER3_CNT_CAP: Ledc timer%s count value capture register. +func (o *LEDC_Type) SetTIMER3_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER3_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER3_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER3_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.CONF: Global ledc configuration register +func (o *LEDC_Type) SetCONF_APB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCONF_APB_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x3 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH0(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH1(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH2(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH3(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH4(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH5(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH5() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// LEDC.DATE: Version control register +func (o *LEDC_Type) SetDATE_LEDC_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LEDC_Type) GetDATE_LEDC_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LP_PERI Peripheral +type LPPERI_Type struct { + CLK_EN volatile.Register32 // 0x0 + RESET_EN volatile.Register32 // 0x4 + RNG_DATA volatile.Register32 // 0x8 + CPU volatile.Register32 // 0xC + BUS_TIMEOUT volatile.Register32 // 0x10 + BUS_TIMEOUT_ADDR volatile.Register32 // 0x14 + BUS_TIMEOUT_UID volatile.Register32 // 0x18 + MEM_CTRL volatile.Register32 // 0x1C + INTERRUPT_SOURCE volatile.Register32 // 0x20 + DEBUG_SEL0 volatile.Register32 // 0x24 + DEBUG_SEL1 volatile.Register32 // 0x28 + _ [976]byte + DATE volatile.Register32 // 0x3FC +} + +// LPPERI.CLK_EN: need_des +func (o *LPPERI_Type) SetCLK_EN_RNG_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *LPPERI_Type) GetCLK_EN_RNG_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1000000) >> 24 +} +func (o *LPPERI_Type) SetCLK_EN_OTP_DBG_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *LPPERI_Type) GetCLK_EN_OTP_DBG_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x2000000) >> 25 +} +func (o *LPPERI_Type) SetCLK_EN_LP_UART_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LPPERI_Type) GetCLK_EN_LP_UART_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x4000000) >> 26 +} +func (o *LPPERI_Type) SetCLK_EN_LP_IO_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LPPERI_Type) GetCLK_EN_LP_IO_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x8000000) >> 27 +} +func (o *LPPERI_Type) SetCLK_EN_LP_EXT_I2C_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LPPERI_Type) GetCLK_EN_LP_EXT_I2C_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10000000) >> 28 +} +func (o *LPPERI_Type) SetCLK_EN_LP_ANA_I2C_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetCLK_EN_LP_ANA_I2C_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetCLK_EN_EFUSE_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetCLK_EN_EFUSE_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetCLK_EN_LP_CPU_CK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetCLK_EN_LP_CPU_CK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x80000000) >> 31 +} + +// LPPERI.RESET_EN: need_des +func (o *LPPERI_Type) SetRESET_EN_BUS_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x800000)|value<<23) +} +func (o *LPPERI_Type) GetRESET_EN_BUS_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x800000) >> 23 +} +func (o *LPPERI_Type) SetRESET_EN_LP_BLE_TIMER_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *LPPERI_Type) GetRESET_EN_LP_BLE_TIMER_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x1000000) >> 24 +} +func (o *LPPERI_Type) SetRESET_EN_OTP_DBG_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *LPPERI_Type) GetRESET_EN_OTP_DBG_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x2000000) >> 25 +} +func (o *LPPERI_Type) SetRESET_EN_LP_UART_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LPPERI_Type) GetRESET_EN_LP_UART_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x4000000) >> 26 +} +func (o *LPPERI_Type) SetRESET_EN_LP_IO_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LPPERI_Type) GetRESET_EN_LP_IO_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x8000000) >> 27 +} +func (o *LPPERI_Type) SetRESET_EN_LP_EXT_I2C_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LPPERI_Type) GetRESET_EN_LP_EXT_I2C_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x10000000) >> 28 +} +func (o *LPPERI_Type) SetRESET_EN_LP_ANA_I2C_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetRESET_EN_LP_ANA_I2C_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetRESET_EN_EFUSE_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetRESET_EN_EFUSE_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetRESET_EN_LP_CPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetRESET_EN_LP_CPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x80000000) >> 31 +} + +// LPPERI.RNG_DATA: need_des +func (o *LPPERI_Type) SetRNG_DATA(value uint32) { + volatile.StoreUint32(&o.RNG_DATA.Reg, value) +} +func (o *LPPERI_Type) GetRNG_DATA() uint32 { + return volatile.LoadUint32(&o.RNG_DATA.Reg) +} + +// LPPERI.CPU: need_des +func (o *LPPERI_Type) SetCPU_LPCORE_DBGM_UNAVALIABLE(value uint32) { + volatile.StoreUint32(&o.CPU.Reg, volatile.LoadUint32(&o.CPU.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetCPU_LPCORE_DBGM_UNAVALIABLE() uint32 { + return (volatile.LoadUint32(&o.CPU.Reg) & 0x80000000) >> 31 +} + +// LPPERI.BUS_TIMEOUT: need_des +func (o *LPPERI_Type) SetBUS_TIMEOUT_LP_PERI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT.Reg)&^(0x3fffc000)|value<<14) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_LP_PERI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMEOUT.Reg) & 0x3fffc000) >> 14 +} +func (o *LPPERI_Type) SetBUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMEOUT.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetBUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMEOUT.Reg) & 0x80000000) >> 31 +} + +// LPPERI.BUS_TIMEOUT_ADDR: need_des +func (o *LPPERI_Type) SetBUS_TIMEOUT_ADDR(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT_ADDR.Reg, value) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_ADDR() uint32 { + return volatile.LoadUint32(&o.BUS_TIMEOUT_ADDR.Reg) +} + +// LPPERI.BUS_TIMEOUT_UID: need_des +func (o *LPPERI_Type) SetBUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID(value uint32) { + volatile.StoreUint32(&o.BUS_TIMEOUT_UID.Reg, volatile.LoadUint32(&o.BUS_TIMEOUT_UID.Reg)&^(0x7f)|value) +} +func (o *LPPERI_Type) GetBUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID() uint32 { + return volatile.LoadUint32(&o.BUS_TIMEOUT_UID.Reg) & 0x7f +} + +// LPPERI.MEM_CTRL: need_des +func (o *LPPERI_Type) SetMEM_CTRL_UART_WAKEUP_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x1)|value) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_WAKEUP_FLAG_CLR() uint32 { + return volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x1 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_WAKEUP_FLAG(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_WAKEUP_FLAG() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x2) >> 1 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetMEM_CTRL_UART_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetMEM_CTRL_UART_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x80000000) >> 31 +} + +// LPPERI.INTERRUPT_SOURCE: need_des +func (o *LPPERI_Type) SetINTERRUPT_SOURCE_LP_INTERRUPT_SOURCE(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_SOURCE.Reg, volatile.LoadUint32(&o.INTERRUPT_SOURCE.Reg)&^(0x3f)|value) +} +func (o *LPPERI_Type) GetINTERRUPT_SOURCE_LP_INTERRUPT_SOURCE() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_SOURCE.Reg) & 0x3f +} + +// LPPERI.DEBUG_SEL0: need des +func (o *LPPERI_Type) SetDEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0x7f)|value) +} +func (o *LPPERI_Type) GetDEBUG_SEL0() uint32 { + return volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0x7f +} +func (o *LPPERI_Type) SetDEBUG_SEL0_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0x3f80)|value<<7) +} +func (o *LPPERI_Type) GetDEBUG_SEL0_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0x3f80) >> 7 +} +func (o *LPPERI_Type) SetDEBUG_SEL0_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0x1fc000)|value<<14) +} +func (o *LPPERI_Type) GetDEBUG_SEL0_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0x1fc000) >> 14 +} +func (o *LPPERI_Type) SetDEBUG_SEL0_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL0.Reg, volatile.LoadUint32(&o.DEBUG_SEL0.Reg)&^(0xfe00000)|value<<21) +} +func (o *LPPERI_Type) GetDEBUG_SEL0_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.DEBUG_SEL0.Reg) & 0xfe00000) >> 21 +} + +// LPPERI.DEBUG_SEL1: need des +func (o *LPPERI_Type) SetDEBUG_SEL1_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.DEBUG_SEL1.Reg, volatile.LoadUint32(&o.DEBUG_SEL1.Reg)&^(0x7f)|value) +} +func (o *LPPERI_Type) GetDEBUG_SEL1_DEBUG_SEL4() uint32 { + return volatile.LoadUint32(&o.DEBUG_SEL1.Reg) & 0x7f +} + +// LPPERI.DATE: need_des +func (o *LPPERI_Type) SetDATE_LPPERI_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LPPERI_Type) GetDATE_LPPERI_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LPPERI_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_ANA Peripheral +type LP_ANA_Type struct { + BOD_MODE0_CNTL volatile.Register32 // 0x0 + BOD_MODE1_CNTL volatile.Register32 // 0x4 + VDD_SOURCE_CNTL volatile.Register32 // 0x8 + VDDBAT_BOD_CNTL volatile.Register32 // 0xC + VDDBAT_CHARGE_CNTL volatile.Register32 // 0x10 + CK_GLITCH_CNTL volatile.Register32 // 0x14 + PG_GLITCH_CNTL volatile.Register32 // 0x18 + FIB_ENABLE volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_ST volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_CLR volatile.Register32 // 0x2C + LP_INT_RAW volatile.Register32 // 0x30 + LP_INT_ST volatile.Register32 // 0x34 + LP_INT_ENA volatile.Register32 // 0x38 + LP_INT_CLR volatile.Register32 // 0x3C + _ [956]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_ANA.BOD_MODE0_CNTL: need_des +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x40)|value<<6) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x40) >> 6 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x80)|value<<7) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x80) >> 7 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x3ff00)|value<<8) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x3ff00) >> 8 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0xffc0000)|value<<18) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0xffc0000) >> 18 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_RESET_SEL(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_RESET_SEL() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_Type) SetBOD_MODE0_CNTL_BOD_MODE0_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetBOD_MODE0_CNTL_BOD_MODE0_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE0_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.BOD_MODE1_CNTL: need_des +func (o *LP_ANA_Type) SetBOD_MODE1_CNTL_BOD_MODE1_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.BOD_MODE1_CNTL.Reg, volatile.LoadUint32(&o.BOD_MODE1_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetBOD_MODE1_CNTL_BOD_MODE1_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.BOD_MODE1_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.VDD_SOURCE_CNTL: need_des +func (o *LP_ANA_Type) SetVDD_SOURCE_CNTL_DETMODE_SEL(value uint32) { + volatile.StoreUint32(&o.VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.VDD_SOURCE_CNTL.Reg)&^(0xff)|value) +} +func (o *LP_ANA_Type) GetVDD_SOURCE_CNTL_DETMODE_SEL() uint32 { + return volatile.LoadUint32(&o.VDD_SOURCE_CNTL.Reg) & 0xff +} +func (o *LP_ANA_Type) SetVDD_SOURCE_CNTL_VGOOD_EVENT_RECORD(value uint32) { + volatile.StoreUint32(&o.VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.VDD_SOURCE_CNTL.Reg)&^(0xff00)|value<<8) +} +func (o *LP_ANA_Type) GetVDD_SOURCE_CNTL_VGOOD_EVENT_RECORD() uint32 { + return (volatile.LoadUint32(&o.VDD_SOURCE_CNTL.Reg) & 0xff00) >> 8 +} +func (o *LP_ANA_Type) SetVDD_SOURCE_CNTL_VBAT_EVENT_RECORD_CLR(value uint32) { + volatile.StoreUint32(&o.VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.VDD_SOURCE_CNTL.Reg)&^(0xff0000)|value<<16) +} +func (o *LP_ANA_Type) GetVDD_SOURCE_CNTL_VBAT_EVENT_RECORD_CLR() uint32 { + return (volatile.LoadUint32(&o.VDD_SOURCE_CNTL.Reg) & 0xff0000) >> 16 +} +func (o *LP_ANA_Type) SetVDD_SOURCE_CNTL_BOD_SOURCE_ENA(value uint32) { + volatile.StoreUint32(&o.VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.VDD_SOURCE_CNTL.Reg)&^(0xff000000)|value<<24) +} +func (o *LP_ANA_Type) GetVDD_SOURCE_CNTL_BOD_SOURCE_ENA() uint32 { + return (volatile.LoadUint32(&o.VDD_SOURCE_CNTL.Reg) & 0xff000000) >> 24 +} + +// LP_ANA.VDDBAT_BOD_CNTL: need_des +func (o *LP_ANA_Type) SetVDDBAT_BOD_CNTL_VDDBAT_UNDERVOLTAGE_FLAG(value uint32) { + volatile.StoreUint32(&o.VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg)&^(0x1)|value) +} +func (o *LP_ANA_Type) GetVDDBAT_BOD_CNTL_VDDBAT_UNDERVOLTAGE_FLAG() uint32 { + return volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg) & 0x1 +} +func (o *LP_ANA_Type) SetVDDBAT_BOD_CNTL_VDDBAT_CHARGER(value uint32) { + volatile.StoreUint32(&o.VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg)&^(0x400)|value<<10) +} +func (o *LP_ANA_Type) GetVDDBAT_BOD_CNTL_VDDBAT_CHARGER() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg) & 0x400) >> 10 +} +func (o *LP_ANA_Type) SetVDDBAT_BOD_CNTL_VDDBAT_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg)&^(0x800)|value<<11) +} +func (o *LP_ANA_Type) GetVDDBAT_BOD_CNTL_VDDBAT_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg) & 0x800) >> 11 +} +func (o *LP_ANA_Type) SetVDDBAT_BOD_CNTL_VDDBAT_UPVOLTAGE_TARGET(value uint32) { + volatile.StoreUint32(&o.VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg)&^(0x3ff000)|value<<12) +} +func (o *LP_ANA_Type) GetVDDBAT_BOD_CNTL_VDDBAT_UPVOLTAGE_TARGET() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg) & 0x3ff000) >> 12 +} +func (o *LP_ANA_Type) SetVDDBAT_BOD_CNTL_VDDBAT_UNDERVOLTAGE_TARGET(value uint32) { + volatile.StoreUint32(&o.VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_ANA_Type) GetVDDBAT_BOD_CNTL_VDDBAT_UNDERVOLTAGE_TARGET() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_BOD_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_ANA.VDDBAT_CHARGE_CNTL: need_des +func (o *LP_ANA_Type) SetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG(value uint32) { + volatile.StoreUint32(&o.VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg)&^(0x1)|value) +} +func (o *LP_ANA_Type) GetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG() uint32 { + return volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg) & 0x1 +} +func (o *LP_ANA_Type) SetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CHARGER(value uint32) { + volatile.StoreUint32(&o.VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg)&^(0x400)|value<<10) +} +func (o *LP_ANA_Type) GetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CHARGER() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg) & 0x400) >> 10 +} +func (o *LP_ANA_Type) SetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg)&^(0x800)|value<<11) +} +func (o *LP_ANA_Type) GetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg) & 0x800) >> 11 +} +func (o *LP_ANA_Type) SetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UPVOLTAGE_TARGET(value uint32) { + volatile.StoreUint32(&o.VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg)&^(0x3ff000)|value<<12) +} +func (o *LP_ANA_Type) GetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UPVOLTAGE_TARGET() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg) & 0x3ff000) >> 12 +} +func (o *LP_ANA_Type) SetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET(value uint32) { + volatile.StoreUint32(&o.VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_ANA_Type) GetVDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_CHARGE_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_ANA.CK_GLITCH_CNTL: need_des +func (o *LP_ANA_Type) SetCK_GLITCH_CNTL_CK_GLITCH_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.CK_GLITCH_CNTL.Reg, volatile.LoadUint32(&o.CK_GLITCH_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetCK_GLITCH_CNTL_CK_GLITCH_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.CK_GLITCH_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.PG_GLITCH_CNTL: need_des +func (o *LP_ANA_Type) SetPG_GLITCH_CNTL_POWER_GLITCH_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.PG_GLITCH_CNTL.Reg, volatile.LoadUint32(&o.PG_GLITCH_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetPG_GLITCH_CNTL_POWER_GLITCH_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.PG_GLITCH_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.FIB_ENABLE: need_des +func (o *LP_ANA_Type) SetFIB_ENABLE(value uint32) { + volatile.StoreUint32(&o.FIB_ENABLE.Reg, value) +} +func (o *LP_ANA_Type) GetFIB_ENABLE() uint32 { + return volatile.LoadUint32(&o.FIB_ENABLE.Reg) +} + +// LP_ANA.INT_RAW: need_des +func (o *LP_ANA_Type) SetINT_RAW_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_Type) GetINT_RAW_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_Type) SetINT_RAW_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_Type) GetINT_RAW_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_Type) SetINT_RAW_VDDBAT_UPVOLTAGE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_Type) GetINT_RAW_VDDBAT_UPVOLTAGE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_Type) SetINT_RAW_VDDBAT_UNDERVOLTAGE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_Type) GetINT_RAW_VDDBAT_UNDERVOLTAGE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_Type) SetINT_RAW_BOD_MODE0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_RAW_BOD_MODE0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.INT_ST: need_des +func (o *LP_ANA_Type) SetINT_ST_VDDBAT_CHARGE_UPVOLTAGE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_Type) GetINT_ST_VDDBAT_CHARGE_UPVOLTAGE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_Type) SetINT_ST_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_Type) GetINT_ST_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_Type) SetINT_ST_VDDBAT_UPVOLTAGE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_Type) GetINT_ST_VDDBAT_UPVOLTAGE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_Type) SetINT_ST_VDDBAT_UNDERVOLTAGE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_Type) GetINT_ST_VDDBAT_UNDERVOLTAGE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_Type) SetINT_ST_BOD_MODE0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_ST_BOD_MODE0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.INT_ENA: need_des +func (o *LP_ANA_Type) SetINT_ENA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_Type) GetINT_ENA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_Type) SetINT_ENA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_Type) GetINT_ENA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_Type) SetINT_ENA_VDDBAT_UPVOLTAGE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_Type) GetINT_ENA_VDDBAT_UPVOLTAGE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_Type) SetINT_ENA_VDDBAT_UNDERVOLTAGE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_Type) GetINT_ENA_VDDBAT_UNDERVOLTAGE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_Type) SetINT_ENA_BOD_MODE0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_ENA_BOD_MODE0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.INT_CLR: need_des +func (o *LP_ANA_Type) SetINT_CLR_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_Type) GetINT_CLR_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_Type) SetINT_CLR_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_Type) GetINT_CLR_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_Type) SetINT_CLR_VDDBAT_UPVOLTAGE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_Type) GetINT_CLR_VDDBAT_UPVOLTAGE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_Type) SetINT_CLR_VDDBAT_UNDERVOLTAGE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_Type) GetINT_CLR_VDDBAT_UNDERVOLTAGE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_Type) SetINT_CLR_BOD_MODE0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetINT_CLR_BOD_MODE0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_RAW: need_des +func (o *LP_ANA_Type) SetLP_INT_RAW_BOD_MODE0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_RAW_BOD_MODE0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_ST: need_des +func (o *LP_ANA_Type) SetLP_INT_ST_BOD_MODE0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_ST_BOD_MODE0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_ENA: need_des +func (o *LP_ANA_Type) SetLP_INT_ENA_BOD_MODE0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_ENA_BOD_MODE0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.LP_INT_CLR: need_des +func (o *LP_ANA_Type) SetLP_INT_CLR_BOD_MODE0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetLP_INT_CLR_BOD_MODE0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_ANA.DATE: need_des +func (o *LP_ANA_Type) SetDATE_LP_ANA_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_ANA_Type) GetDATE_LP_ANA_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_ANA_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_AON Peripheral +type LP_AON_Type struct { + STORE0 volatile.Register32 // 0x0 + STORE1 volatile.Register32 // 0x4 + STORE2 volatile.Register32 // 0x8 + STORE3 volatile.Register32 // 0xC + STORE4 volatile.Register32 // 0x10 + STORE5 volatile.Register32 // 0x14 + STORE6 volatile.Register32 // 0x18 + STORE7 volatile.Register32 // 0x1C + STORE8 volatile.Register32 // 0x20 + STORE9 volatile.Register32 // 0x24 + GPIO_MUX volatile.Register32 // 0x28 + GPIO_HOLD0 volatile.Register32 // 0x2C + GPIO_HOLD1 volatile.Register32 // 0x30 + SYS_CFG volatile.Register32 // 0x34 + CPUCORE0_CFG volatile.Register32 // 0x38 + IO_MUX volatile.Register32 // 0x3C + EXT_WAKEUP_CNTL volatile.Register32 // 0x40 + USB volatile.Register32 // 0x44 + LPBUS volatile.Register32 // 0x48 + SDIO_ACTIVE volatile.Register32 // 0x4C + LPCORE volatile.Register32 // 0x50 + SAR_CCT volatile.Register32 // 0x54 + JTAG_SEL volatile.Register32 // 0x58 + _ [928]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_AON.STORE0: need_des +func (o *LP_AON_Type) SetSTORE0(value uint32) { + volatile.StoreUint32(&o.STORE0.Reg, value) +} +func (o *LP_AON_Type) GetSTORE0() uint32 { + return volatile.LoadUint32(&o.STORE0.Reg) +} + +// LP_AON.STORE1: need_des +func (o *LP_AON_Type) SetSTORE1(value uint32) { + volatile.StoreUint32(&o.STORE1.Reg, value) +} +func (o *LP_AON_Type) GetSTORE1() uint32 { + return volatile.LoadUint32(&o.STORE1.Reg) +} + +// LP_AON.STORE2: need_des +func (o *LP_AON_Type) SetSTORE2(value uint32) { + volatile.StoreUint32(&o.STORE2.Reg, value) +} +func (o *LP_AON_Type) GetSTORE2() uint32 { + return volatile.LoadUint32(&o.STORE2.Reg) +} + +// LP_AON.STORE3: need_des +func (o *LP_AON_Type) SetSTORE3(value uint32) { + volatile.StoreUint32(&o.STORE3.Reg, value) +} +func (o *LP_AON_Type) GetSTORE3() uint32 { + return volatile.LoadUint32(&o.STORE3.Reg) +} + +// LP_AON.STORE4: need_des +func (o *LP_AON_Type) SetSTORE4(value uint32) { + volatile.StoreUint32(&o.STORE4.Reg, value) +} +func (o *LP_AON_Type) GetSTORE4() uint32 { + return volatile.LoadUint32(&o.STORE4.Reg) +} + +// LP_AON.STORE5: need_des +func (o *LP_AON_Type) SetSTORE5(value uint32) { + volatile.StoreUint32(&o.STORE5.Reg, value) +} +func (o *LP_AON_Type) GetSTORE5() uint32 { + return volatile.LoadUint32(&o.STORE5.Reg) +} + +// LP_AON.STORE6: need_des +func (o *LP_AON_Type) SetSTORE6(value uint32) { + volatile.StoreUint32(&o.STORE6.Reg, value) +} +func (o *LP_AON_Type) GetSTORE6() uint32 { + return volatile.LoadUint32(&o.STORE6.Reg) +} + +// LP_AON.STORE7: need_des +func (o *LP_AON_Type) SetSTORE7(value uint32) { + volatile.StoreUint32(&o.STORE7.Reg, value) +} +func (o *LP_AON_Type) GetSTORE7() uint32 { + return volatile.LoadUint32(&o.STORE7.Reg) +} + +// LP_AON.STORE8: need_des +func (o *LP_AON_Type) SetSTORE8(value uint32) { + volatile.StoreUint32(&o.STORE8.Reg, value) +} +func (o *LP_AON_Type) GetSTORE8() uint32 { + return volatile.LoadUint32(&o.STORE8.Reg) +} + +// LP_AON.STORE9: need_des +func (o *LP_AON_Type) SetSTORE9(value uint32) { + volatile.StoreUint32(&o.STORE9.Reg, value) +} +func (o *LP_AON_Type) GetSTORE9() uint32 { + return volatile.LoadUint32(&o.STORE9.Reg) +} + +// LP_AON.GPIO_MUX: need_des +func (o *LP_AON_Type) SetGPIO_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO_MUX.Reg, volatile.LoadUint32(&o.GPIO_MUX.Reg)&^(0xff)|value) +} +func (o *LP_AON_Type) GetGPIO_MUX_SEL() uint32 { + return volatile.LoadUint32(&o.GPIO_MUX.Reg) & 0xff +} + +// LP_AON.GPIO_HOLD0: need_des +func (o *LP_AON_Type) SetGPIO_HOLD0(value uint32) { + volatile.StoreUint32(&o.GPIO_HOLD0.Reg, value) +} +func (o *LP_AON_Type) GetGPIO_HOLD0() uint32 { + return volatile.LoadUint32(&o.GPIO_HOLD0.Reg) +} + +// LP_AON.GPIO_HOLD1: need_des +func (o *LP_AON_Type) SetGPIO_HOLD1(value uint32) { + volatile.StoreUint32(&o.GPIO_HOLD1.Reg, value) +} +func (o *LP_AON_Type) GetGPIO_HOLD1() uint32 { + return volatile.LoadUint32(&o.GPIO_HOLD1.Reg) +} + +// LP_AON.SYS_CFG: need_des +func (o *LP_AON_Type) SetSYS_CFG_ANA_FIB_SWD_ENABLE(value uint32) { + volatile.StoreUint32(&o.SYS_CFG.Reg, volatile.LoadUint32(&o.SYS_CFG.Reg)&^(0x1)|value) +} +func (o *LP_AON_Type) GetSYS_CFG_ANA_FIB_SWD_ENABLE() uint32 { + return volatile.LoadUint32(&o.SYS_CFG.Reg) & 0x1 +} +func (o *LP_AON_Type) SetSYS_CFG_ANA_FIB_CK_GLITCH_ENABLE(value uint32) { + volatile.StoreUint32(&o.SYS_CFG.Reg, volatile.LoadUint32(&o.SYS_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_AON_Type) GetSYS_CFG_ANA_FIB_CK_GLITCH_ENABLE() uint32 { + return (volatile.LoadUint32(&o.SYS_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_AON_Type) SetSYS_CFG_ANA_FIB_BOD_ENABLE(value uint32) { + volatile.StoreUint32(&o.SYS_CFG.Reg, volatile.LoadUint32(&o.SYS_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_AON_Type) GetSYS_CFG_ANA_FIB_BOD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.SYS_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_AON_Type) SetSYS_CFG_FORCE_DOWNLOAD_BOOT(value uint32) { + volatile.StoreUint32(&o.SYS_CFG.Reg, volatile.LoadUint32(&o.SYS_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_Type) GetSYS_CFG_FORCE_DOWNLOAD_BOOT() uint32 { + return (volatile.LoadUint32(&o.SYS_CFG.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_Type) SetSYS_CFG_HPSYS_SW_RESET(value uint32) { + volatile.StoreUint32(&o.SYS_CFG.Reg, volatile.LoadUint32(&o.SYS_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetSYS_CFG_HPSYS_SW_RESET() uint32 { + return (volatile.LoadUint32(&o.SYS_CFG.Reg) & 0x80000000) >> 31 +} + +// LP_AON.CPUCORE0_CFG: need_des +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_SW_STALL(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0xff)|value) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_SW_STALL() uint32 { + return volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0xff +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_SW_RESET(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_SW_RESET() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_Type) SetCPUCORE0_CFG_CPU_CORE0_DRESET_MASK(value uint32) { + volatile.StoreUint32(&o.CPUCORE0_CFG.Reg, volatile.LoadUint32(&o.CPUCORE0_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetCPUCORE0_CFG_CPU_CORE0_DRESET_MASK() uint32 { + return (volatile.LoadUint32(&o.CPUCORE0_CFG.Reg) & 0x80000000) >> 31 +} + +// LP_AON.IO_MUX: need_des +func (o *LP_AON_Type) SetIO_MUX_PULL_LDO(value uint32) { + volatile.StoreUint32(&o.IO_MUX.Reg, volatile.LoadUint32(&o.IO_MUX.Reg)&^(0x70000000)|value<<28) +} +func (o *LP_AON_Type) GetIO_MUX_PULL_LDO() uint32 { + return (volatile.LoadUint32(&o.IO_MUX.Reg) & 0x70000000) >> 28 +} +func (o *LP_AON_Type) SetIO_MUX_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX.Reg, volatile.LoadUint32(&o.IO_MUX.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetIO_MUX_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.IO_MUX.Reg) & 0x80000000) >> 31 +} + +// LP_AON.EXT_WAKEUP_CNTL: need_des +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0xff)|value) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0xff +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x4000)|value<<14) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x4000) >> 14 +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x7f8000)|value<<15) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x7f8000) >> 15 +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x7f800000)|value<<23) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x7f800000) >> 23 +} +func (o *LP_AON_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_AON.USB: need_des +func (o *LP_AON_Type) SetUSB_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.USB.Reg, volatile.LoadUint32(&o.USB.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetUSB_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.USB.Reg) & 0x80000000) >> 31 +} + +// LP_AON.LPBUS: need_des +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_WPULSE(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x70000)|value<<16) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_WPULSE() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x70000) >> 16 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_WA(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x380000)|value<<19) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_WA() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x380000) >> 19 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_RA(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0xc00000)|value<<22) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_RA() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0xc00000) >> 22 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_RM(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0xf000000)|value<<24) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_RM() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0xf000000) >> 24 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_SEL_STATUS(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_SEL_STATUS() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_SEL_UPDATE(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_SEL_UPDATE() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_Type) SetLPBUS_FAST_MEM_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.LPBUS.Reg, volatile.LoadUint32(&o.LPBUS.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetLPBUS_FAST_MEM_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.LPBUS.Reg) & 0x80000000) >> 31 +} + +// LP_AON.SDIO_ACTIVE: need_des +func (o *LP_AON_Type) SetSDIO_ACTIVE_SDIO_ACT_DNUM(value uint32) { + volatile.StoreUint32(&o.SDIO_ACTIVE.Reg, volatile.LoadUint32(&o.SDIO_ACTIVE.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_AON_Type) GetSDIO_ACTIVE_SDIO_ACT_DNUM() uint32 { + return (volatile.LoadUint32(&o.SDIO_ACTIVE.Reg) & 0xffc00000) >> 22 +} + +// LP_AON.LPCORE: need_des +func (o *LP_AON_Type) SetLPCORE_ETM_WAKEUP_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.LPCORE.Reg, volatile.LoadUint32(&o.LPCORE.Reg)&^(0x1)|value) +} +func (o *LP_AON_Type) GetLPCORE_ETM_WAKEUP_FLAG_CLR() uint32 { + return volatile.LoadUint32(&o.LPCORE.Reg) & 0x1 +} +func (o *LP_AON_Type) SetLPCORE_ETM_WAKEUP_FLAG(value uint32) { + volatile.StoreUint32(&o.LPCORE.Reg, volatile.LoadUint32(&o.LPCORE.Reg)&^(0x2)|value<<1) +} +func (o *LP_AON_Type) GetLPCORE_ETM_WAKEUP_FLAG() uint32 { + return (volatile.LoadUint32(&o.LPCORE.Reg) & 0x2) >> 1 +} +func (o *LP_AON_Type) SetLPCORE_DISABLE(value uint32) { + volatile.StoreUint32(&o.LPCORE.Reg, volatile.LoadUint32(&o.LPCORE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetLPCORE_DISABLE() uint32 { + return (volatile.LoadUint32(&o.LPCORE.Reg) & 0x80000000) >> 31 +} + +// LP_AON.SAR_CCT: need_des +func (o *LP_AON_Type) SetSAR_CCT_SAR2_PWDET_CCT(value uint32) { + volatile.StoreUint32(&o.SAR_CCT.Reg, volatile.LoadUint32(&o.SAR_CCT.Reg)&^(0xe0000000)|value<<29) +} +func (o *LP_AON_Type) GetSAR_CCT_SAR2_PWDET_CCT() uint32 { + return (volatile.LoadUint32(&o.SAR_CCT.Reg) & 0xe0000000) >> 29 +} + +// LP_AON.JTAG_SEL: need_des +func (o *LP_AON_Type) SetJTAG_SEL_SOFT(value uint32) { + volatile.StoreUint32(&o.JTAG_SEL.Reg, volatile.LoadUint32(&o.JTAG_SEL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetJTAG_SEL_SOFT() uint32 { + return (volatile.LoadUint32(&o.JTAG_SEL.Reg) & 0x80000000) >> 31 +} + +// LP_AON.DATE: need_des +func (o *LP_AON_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_AON_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_AON_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power Access Permission Management Controller +type LP_APM_Type struct { + REGION_FILTER_EN volatile.Register32 // 0x0 + REGION0_ADDR_START volatile.Register32 // 0x4 + REGION0_ADDR_END volatile.Register32 // 0x8 + REGION0_PMS_ATTR volatile.Register32 // 0xC + REGION1_ADDR_START volatile.Register32 // 0x10 + REGION1_ADDR_END volatile.Register32 // 0x14 + REGION1_PMS_ATTR volatile.Register32 // 0x18 + _ [168]byte + FUNC_CTRL volatile.Register32 // 0xC4 + M0_STATUS volatile.Register32 // 0xC8 + M0_STATUS_CLR volatile.Register32 // 0xCC + M0_EXCEPTION_INFO0 volatile.Register32 // 0xD0 + M0_EXCEPTION_INFO1 volatile.Register32 // 0xD4 + _ [16]byte + INT_EN volatile.Register32 // 0xE8 + CLOCK_GATE volatile.Register32 // 0xEC + _ [12]byte + DATE volatile.Register32 // 0xFC +} + +// LP_APM.REGION_FILTER_EN: Region filter enable register +func (o *LP_APM_Type) SetREGION_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.REGION_FILTER_EN.Reg, volatile.LoadUint32(&o.REGION_FILTER_EN.Reg)&^(0x3)|value) +} +func (o *LP_APM_Type) GetREGION_FILTER_EN() uint32 { + return volatile.LoadUint32(&o.REGION_FILTER_EN.Reg) & 0x3 +} + +// LP_APM.REGION0_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION0_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION0_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_START.Reg) +} + +// LP_APM.REGION0_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION0_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION0_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION0_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION0_ADDR_END.Reg) +} + +// LP_APM.REGION0_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION0_PMS_ATTR_REGION0_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION0_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION0_PMS_ATTR_REGION0_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION0_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.REGION1_ADDR_START: Region address register +func (o *LP_APM_Type) SetREGION1_ADDR_START(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_START.Reg, value) +} +func (o *LP_APM_Type) GetREGION1_ADDR_START() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_START.Reg) +} + +// LP_APM.REGION1_ADDR_END: Region address register +func (o *LP_APM_Type) SetREGION1_ADDR_END(value uint32) { + volatile.StoreUint32(&o.REGION1_ADDR_END.Reg, value) +} +func (o *LP_APM_Type) GetREGION1_ADDR_END() uint32 { + return volatile.LoadUint32(&o.REGION1_ADDR_END.Reg) +} + +// LP_APM.REGION1_PMS_ATTR: Region access authority attribute register +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_X() uint32 { + return volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x1 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x2) >> 1 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R0_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R0_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x4) >> 2 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x10)|value<<4) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x10) >> 4 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x20) >> 5 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R1_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R1_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x40) >> 6 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_X(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_X() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x100) >> 8 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_W(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_W() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x200) >> 9 +} +func (o *LP_APM_Type) SetREGION1_PMS_ATTR_REGION1_R2_PMS_R(value uint32) { + volatile.StoreUint32(&o.REGION1_PMS_ATTR.Reg, volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_APM_Type) GetREGION1_PMS_ATTR_REGION1_R2_PMS_R() uint32 { + return (volatile.LoadUint32(&o.REGION1_PMS_ATTR.Reg) & 0x400) >> 10 +} + +// LP_APM.FUNC_CTRL: PMS function control register +func (o *LP_APM_Type) SetFUNC_CTRL_M0_PMS_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.FUNC_CTRL.Reg, volatile.LoadUint32(&o.FUNC_CTRL.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetFUNC_CTRL_M0_PMS_FUNC_EN() uint32 { + return volatile.LoadUint32(&o.FUNC_CTRL.Reg) & 0x1 +} + +// LP_APM.M0_STATUS: M0 status register +func (o *LP_APM_Type) SetM0_STATUS_M0_EXCEPTION_STATUS(value uint32) { + volatile.StoreUint32(&o.M0_STATUS.Reg, volatile.LoadUint32(&o.M0_STATUS.Reg)&^(0x3)|value) +} +func (o *LP_APM_Type) GetM0_STATUS_M0_EXCEPTION_STATUS() uint32 { + return volatile.LoadUint32(&o.M0_STATUS.Reg) & 0x3 +} + +// LP_APM.M0_STATUS_CLR: M0 status clear register +func (o *LP_APM_Type) SetM0_STATUS_CLR_M0_REGION_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.M0_STATUS_CLR.Reg, volatile.LoadUint32(&o.M0_STATUS_CLR.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetM0_STATUS_CLR_M0_REGION_STATUS_CLR() uint32 { + return volatile.LoadUint32(&o.M0_STATUS_CLR.Reg) & 0x1 +} + +// LP_APM.M0_EXCEPTION_INFO0: M0 exception_info0 register +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x3)|value) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_REGION() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x3 +} +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x30000)|value<<16) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_MODE() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x30000) >> 16 +} +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO0.Reg, volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO0_M0_EXCEPTION_ID() uint32 { + return (volatile.LoadUint32(&o.M0_EXCEPTION_INFO0.Reg) & 0x7c0000) >> 18 +} + +// LP_APM.M0_EXCEPTION_INFO1: M0 exception_info1 register +func (o *LP_APM_Type) SetM0_EXCEPTION_INFO1(value uint32) { + volatile.StoreUint32(&o.M0_EXCEPTION_INFO1.Reg, value) +} +func (o *LP_APM_Type) GetM0_EXCEPTION_INFO1() uint32 { + return volatile.LoadUint32(&o.M0_EXCEPTION_INFO1.Reg) +} + +// LP_APM.INT_EN: APM interrupt enable register +func (o *LP_APM_Type) SetINT_EN_M0_APM_INT_EN(value uint32) { + volatile.StoreUint32(&o.INT_EN.Reg, volatile.LoadUint32(&o.INT_EN.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetINT_EN_M0_APM_INT_EN() uint32 { + return volatile.LoadUint32(&o.INT_EN.Reg) & 0x1 +} + +// LP_APM.CLOCK_GATE: clock gating register +func (o *LP_APM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *LP_APM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// LP_APM.DATE: Version register +func (o *LP_APM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_APM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LP_CLKRST Peripheral +type LP_CLKRST_Type struct { + LP_CLK_CONF volatile.Register32 // 0x0 + LP_CLK_PO_EN volatile.Register32 // 0x4 + LP_CLK_EN volatile.Register32 // 0x8 + LP_RST_EN volatile.Register32 // 0xC + RESET_CAUSE volatile.Register32 // 0x10 + CPU_RESET volatile.Register32 // 0x14 + FOSC_CNTL volatile.Register32 // 0x18 + RC32K_CNTL volatile.Register32 // 0x1C + CLK_TO_HP volatile.Register32 // 0x20 + LPMEM_FORCE volatile.Register32 // 0x24 + LPPERI volatile.Register32 // 0x28 + XTAL32K volatile.Register32 // 0x2C + _ [972]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_CLKRST.LP_CLK_CONF: need_des +func (o *LP_CLKRST_Type) SetLP_CLK_CONF_SLOW_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_CLK_CONF.Reg)&^(0x3)|value) +} +func (o *LP_CLKRST_Type) GetLP_CLK_CONF_SLOW_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.LP_CLK_CONF.Reg) & 0x3 +} +func (o *LP_CLKRST_Type) SetLP_CLK_CONF_FAST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_CLK_CONF.Reg)&^(0xc)|value<<2) +} +func (o *LP_CLKRST_Type) GetLP_CLK_CONF_FAST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_CONF.Reg) & 0xc) >> 2 +} +func (o *LP_CLKRST_Type) SetLP_CLK_CONF_LP_PERI_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_CLK_CONF.Reg)&^(0xff0)|value<<4) +} +func (o *LP_CLKRST_Type) GetLP_CLK_CONF_LP_PERI_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_CONF.Reg) & 0xff0) >> 4 +} + +// LP_CLKRST.LP_CLK_PO_EN: need_des +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_AON_SLOW_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x1)|value) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_AON_SLOW_OEN() uint32 { + return volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x1 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_AON_FAST_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x2)|value<<1) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_AON_FAST_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x2) >> 1 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_SOSC_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x4)|value<<2) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_SOSC_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x4) >> 2 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_FOSC_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x8)|value<<3) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_FOSC_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x8) >> 3 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_OSC32K_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x10)|value<<4) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_OSC32K_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x10) >> 4 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_XTAL32K_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x20)|value<<5) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_XTAL32K_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x20) >> 5 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_CORE_EFUSE_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x40)|value<<6) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_CORE_EFUSE_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x40) >> 6 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_SLOW_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x80)|value<<7) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_SLOW_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x80) >> 7 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_FAST_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x100)|value<<8) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_FAST_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x100) >> 8 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_RNG_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x200)|value<<9) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_RNG_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x200) >> 9 +} +func (o *LP_CLKRST_Type) SetLP_CLK_PO_EN_LPBUS_OEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg)&^(0x400)|value<<10) +} +func (o *LP_CLKRST_Type) GetLP_CLK_PO_EN_LPBUS_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_PO_EN.Reg) & 0x400) >> 10 +} + +// LP_CLKRST.LP_CLK_EN: need_des +func (o *LP_CLKRST_Type) SetLP_CLK_EN_FAST_ORI_GATE(value uint32) { + volatile.StoreUint32(&o.LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_CLK_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLP_CLK_EN_FAST_ORI_GATE() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_EN.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.LP_RST_EN: need_des +func (o *LP_CLKRST_Type) SetLP_RST_EN_AON_EFUSE_CORE_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_AON_EFUSE_CORE_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetLP_RST_EN_LP_TIMER_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_LP_TIMER_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetLP_RST_EN_WDT_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_WDT_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetLP_RST_EN_ANA_PERI_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_RST_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLP_RST_EN_ANA_PERI_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_RST_EN.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.RESET_CAUSE: need_des +func (o *LP_CLKRST_Type) SetRESET_CAUSE(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x1f)|value) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE() uint32 { + return volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x1f +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x20)|value<<5) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_FLAG() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x20) >> 5 +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_FLAG_SET(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_FLAG_SET() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetRESET_CAUSE_CORE0_RESET_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_CAUSE.Reg, volatile.LoadUint32(&o.RESET_CAUSE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetRESET_CAUSE_CORE0_RESET_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_CAUSE.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.CPU_RESET: need_des +func (o *LP_CLKRST_Type) SetCPU_RESET_RTC_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_RTC_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x1c00000) >> 22 +} +func (o *LP_CLKRST_Type) SetCPU_RESET_RTC_WDT_CPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_RTC_WDT_CPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x2000000) >> 25 +} +func (o *LP_CLKRST_Type) SetCPU_RESET_CPU_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x7c000000)|value<<26) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_CPU_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x7c000000) >> 26 +} +func (o *LP_CLKRST_Type) SetCPU_RESET_CPU_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CPU_RESET.Reg, volatile.LoadUint32(&o.CPU_RESET.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetCPU_RESET_CPU_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CPU_RESET.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.FOSC_CNTL: need_des +func (o *LP_CLKRST_Type) SetFOSC_CNTL_FOSC_DFREQ(value uint32) { + volatile.StoreUint32(&o.FOSC_CNTL.Reg, volatile.LoadUint32(&o.FOSC_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetFOSC_CNTL_FOSC_DFREQ() uint32 { + return (volatile.LoadUint32(&o.FOSC_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_CLKRST.RC32K_CNTL: need_des +func (o *LP_CLKRST_Type) SetRC32K_CNTL_RC32K_DFREQ(value uint32) { + volatile.StoreUint32(&o.RC32K_CNTL.Reg, volatile.LoadUint32(&o.RC32K_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetRC32K_CNTL_RC32K_DFREQ() uint32 { + return (volatile.LoadUint32(&o.RC32K_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_CLKRST.CLK_TO_HP: need_des +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_XTAL32K(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_SOSC(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_SOSC() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_OSC32K(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_OSC32K() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetCLK_TO_HP_ICG_HP_FOSC(value uint32) { + volatile.StoreUint32(&o.CLK_TO_HP.Reg, volatile.LoadUint32(&o.CLK_TO_HP.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetCLK_TO_HP_ICG_HP_FOSC() uint32 { + return (volatile.LoadUint32(&o.CLK_TO_HP.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.LPMEM_FORCE: need_des +func (o *LP_CLKRST_Type) SetLPMEM_FORCE_LPMEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LPMEM_FORCE.Reg, volatile.LoadUint32(&o.LPMEM_FORCE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLPMEM_FORCE_LPMEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LPMEM_FORCE.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.LPPERI: need_des +func (o *LP_CLKRST_Type) SetLPPERI_LP_BLETIMER_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0xfff000)|value<<12) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_BLETIMER_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0xfff000) >> 12 +} +func (o *LP_CLKRST_Type) SetLPPERI_LP_BLETIMER_32K_SEL(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x3000000)|value<<24) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_BLETIMER_32K_SEL() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x3000000) >> 24 +} +func (o *LP_CLKRST_Type) SetLPPERI_LP_SEL_OSC_SLOW(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_SEL_OSC_SLOW() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x4000000) >> 26 +} +func (o *LP_CLKRST_Type) SetLPPERI_LP_SEL_OSC_FAST(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_SEL_OSC_FAST() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x8000000) >> 27 +} +func (o *LP_CLKRST_Type) SetLPPERI_LP_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetLPPERI_LP_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x20000000) >> 29 +} +func (o *LP_CLKRST_Type) SetLPPERI_LP_I2C_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_I2C_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x40000000) >> 30 +} +func (o *LP_CLKRST_Type) SetLPPERI_LP_UART_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LPPERI.Reg, volatile.LoadUint32(&o.LPPERI.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetLPPERI_LP_UART_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LPPERI.Reg) & 0x80000000) >> 31 +} + +// LP_CLKRST.XTAL32K: need_des +func (o *LP_CLKRST_Type) SetXTAL32K_DRES_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DRES_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0x1c00000) >> 22 +} +func (o *LP_CLKRST_Type) SetXTAL32K_DGM_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0xe000000)|value<<25) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DGM_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0xe000000) >> 25 +} +func (o *LP_CLKRST_Type) SetXTAL32K_DBUF_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DBUF_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0x10000000) >> 28 +} +func (o *LP_CLKRST_Type) SetXTAL32K_DAC_XTAL32K(value uint32) { + volatile.StoreUint32(&o.XTAL32K.Reg, volatile.LoadUint32(&o.XTAL32K.Reg)&^(0xe0000000)|value<<29) +} +func (o *LP_CLKRST_Type) GetXTAL32K_DAC_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.XTAL32K.Reg) & 0xe0000000) >> 29 +} + +// LP_CLKRST.DATE: need_des +func (o *LP_CLKRST_Type) SetDATE_CLKRST_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_CLKRST_Type) GetDATE_CLKRST_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_CLKRST_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_CLKRST_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power Timer +type LP_TIMER_Type struct { + TAR0_LOW volatile.Register32 // 0x0 + TAR0_HIGH volatile.Register32 // 0x4 + _ [8]byte + UPDATE volatile.Register32 // 0x10 + MAIN_BUF0_LOW volatile.Register32 // 0x14 + MAIN_BUF0_HIGH volatile.Register32 // 0x18 + MAIN_BUF1_LOW volatile.Register32 // 0x1C + MAIN_BUF1_HIGH volatile.Register32 // 0x20 + MAIN_OVERFLOW volatile.Register32 // 0x24 + INT_RAW volatile.Register32 // 0x28 + INT_ST volatile.Register32 // 0x2C + INT_ENA volatile.Register32 // 0x30 + INT_CLR volatile.Register32 // 0x34 + _ [964]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_TIMER.TAR0_LOW: need_des +func (o *LP_TIMER_Type) SetTAR0_LOW(value uint32) { + volatile.StoreUint32(&o.TAR0_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetTAR0_LOW() uint32 { + return volatile.LoadUint32(&o.TAR0_LOW.Reg) +} + +// LP_TIMER.TAR0_HIGH: need_des +func (o *LP_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0(value uint32) { + volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0() uint32 { + return volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0xffff +} +func (o *LP_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_EN0(value uint32) { + volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_EN0() uint32 { + return (volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.UPDATE: need_des +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_UPDATE(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x10000000) >> 28 +} +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_XTAL_OFF(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_XTAL_OFF() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x20000000) >> 29 +} +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_STALL(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_STALL() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_RST(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.MAIN_BUF0_LOW: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF0_LOW(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF0_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF0_LOW() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF0_LOW.Reg) +} + +// LP_TIMER.MAIN_BUF0_HIGH: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF0_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg) & 0xffff +} + +// LP_TIMER.MAIN_BUF1_LOW: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF1_LOW(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF1_LOW.Reg, value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF1_LOW() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF1_LOW.Reg) +} + +// LP_TIMER.MAIN_BUF1_HIGH: need_des +func (o *LP_TIMER_Type) SetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF1_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg)&^(0xffff)|value) +} +func (o *LP_TIMER_Type) GetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg) & 0xffff +} + +// LP_TIMER.MAIN_OVERFLOW: need_des +func (o *LP_TIMER_Type) SetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD(value uint32) { + volatile.StoreUint32(&o.MAIN_OVERFLOW.Reg, volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD() uint32 { + return (volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_RAW: need_des +func (o *LP_TIMER_Type) SetINT_RAW_OVERFLOW_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_RAW_OVERFLOW_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_RAW_SOC_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_RAW_SOC_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_ST: need_des +func (o *LP_TIMER_Type) SetINT_ST_OVERFLOW_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_ST_OVERFLOW_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_ST_SOC_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_ST_SOC_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_ENA: need_des +func (o *LP_TIMER_Type) SetINT_ENA_OVERFLOW_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_ENA_OVERFLOW_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_ENA_SOC_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_ENA_SOC_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.INT_CLR: need_des +func (o *LP_TIMER_Type) SetINT_CLR_OVERFLOW_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_TIMER_Type) GetINT_CLR_OVERFLOW_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *LP_TIMER_Type) SetINT_CLR_SOC_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetINT_CLR_SOC_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_TIMER.DATE: need_des +func (o *LP_TIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_TIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_TIMER_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_TIMER_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power Watchdog Timer +type LP_WDT_Type struct { + WDTCONFIG0 volatile.Register32 // 0x0 + CONFIG1 volatile.Register32 // 0x4 + CONFIG2 volatile.Register32 // 0x8 + CONFIG3 volatile.Register32 // 0xC + CONFIG4 volatile.Register32 // 0x10 + CONFIG5 volatile.Register32 // 0x14 + WDTFEED volatile.Register32 // 0x18 + WDTWPROTECT volatile.Register32 // 0x1C + SWD_CONF volatile.Register32 // 0x20 + SWD_WPROTECT volatile.Register32 // 0x24 + INT_RAW volatile.Register32 // 0x28 + INT_ST_RTC volatile.Register32 // 0x2C + INT_ENA_RTC volatile.Register32 // 0x30 + INT_CLR_RTC volatile.Register32 // 0x34 + _ [964]byte + DATE volatile.Register32 // 0x3FC +} + +// LP_WDT.WDTCONFIG0: need_des +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_PAUSE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200)|value<<9) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_PAUSE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200) >> 9 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400)|value<<10) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400) >> 10 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x800)|value<<11) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x800) >> 11 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000)|value<<13) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000) >> 13 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000)|value<<16) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000) >> 16 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x380000)|value<<19) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x380000) >> 19 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c00000) >> 22 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000000)|value<<25) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000000) >> 25 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000000)|value<<28) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000000) >> 28 +} +func (o *LP_WDT_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.CONFIG1: need_des +func (o *LP_WDT_Type) SetCONFIG1(value uint32) { + volatile.StoreUint32(&o.CONFIG1.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG1() uint32 { + return volatile.LoadUint32(&o.CONFIG1.Reg) +} + +// LP_WDT.CONFIG2: need_des +func (o *LP_WDT_Type) SetCONFIG2(value uint32) { + volatile.StoreUint32(&o.CONFIG2.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG2() uint32 { + return volatile.LoadUint32(&o.CONFIG2.Reg) +} + +// LP_WDT.CONFIG3: need_des +func (o *LP_WDT_Type) SetCONFIG3(value uint32) { + volatile.StoreUint32(&o.CONFIG3.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG3() uint32 { + return volatile.LoadUint32(&o.CONFIG3.Reg) +} + +// LP_WDT.CONFIG4: need_des +func (o *LP_WDT_Type) SetCONFIG4(value uint32) { + volatile.StoreUint32(&o.CONFIG4.Reg, value) +} +func (o *LP_WDT_Type) GetCONFIG4() uint32 { + return volatile.LoadUint32(&o.CONFIG4.Reg) +} + +// LP_WDT.CONFIG5: need_des +func (o *LP_WDT_Type) SetCONFIG5_CHIP_RESET_TARGET(value uint32) { + volatile.StoreUint32(&o.CONFIG5.Reg, volatile.LoadUint32(&o.CONFIG5.Reg)&^(0xff)|value) +} +func (o *LP_WDT_Type) GetCONFIG5_CHIP_RESET_TARGET() uint32 { + return volatile.LoadUint32(&o.CONFIG5.Reg) & 0xff +} +func (o *LP_WDT_Type) SetCONFIG5_CHIP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG5.Reg, volatile.LoadUint32(&o.CONFIG5.Reg)&^(0x100)|value<<8) +} +func (o *LP_WDT_Type) GetCONFIG5_CHIP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG5.Reg) & 0x100) >> 8 +} +func (o *LP_WDT_Type) SetCONFIG5_CHIP_RESET_KEY(value uint32) { + volatile.StoreUint32(&o.CONFIG5.Reg, volatile.LoadUint32(&o.CONFIG5.Reg)&^(0x1fe00)|value<<9) +} +func (o *LP_WDT_Type) GetCONFIG5_CHIP_RESET_KEY() uint32 { + return (volatile.LoadUint32(&o.CONFIG5.Reg) & 0x1fe00) >> 9 +} + +// LP_WDT.WDTFEED: need_des +func (o *LP_WDT_Type) SetWDTFEED_RTC_WDT_FEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, volatile.LoadUint32(&o.WDTFEED.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetWDTFEED_RTC_WDT_FEED() uint32 { + return (volatile.LoadUint32(&o.WDTFEED.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.WDTWPROTECT: need_des +func (o *LP_WDT_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *LP_WDT_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// LP_WDT.SWD_CONF: need_des +func (o *LP_WDT_Type) SetSWD_CONF_SWD_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x1)|value) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_RESET_FLAG() uint32 { + return volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x1 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_AUTO_FEED_EN(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_AUTO_FEED_EN() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x40000) >> 18 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_RST_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_RST_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x80000) >> 19 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_SIGNAL_WIDTH(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_SIGNAL_WIDTH() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x3ff00000) >> 20 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_DISABLE(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetSWD_CONF_SWD_FEED(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetSWD_CONF_SWD_FEED() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.SWD_WPROTECT: need_des +func (o *LP_WDT_Type) SetSWD_WPROTECT(value uint32) { + volatile.StoreUint32(&o.SWD_WPROTECT.Reg, value) +} +func (o *LP_WDT_Type) GetSWD_WPROTECT() uint32 { + return volatile.LoadUint32(&o.SWD_WPROTECT.Reg) +} + +// LP_WDT.INT_RAW: need_des +func (o *LP_WDT_Type) SetINT_RAW_SUPER_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_RAW_SUPER_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_RAW_LP_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_RAW_LP_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.INT_ST_RTC: need_des +func (o *LP_WDT_Type) SetINT_ST_RTC_SUPER_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_ST_RTC_SUPER_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_ST_RTC_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_ST_RTC_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.INT_ENA_RTC: need_des +func (o *LP_WDT_Type) SetINT_ENA_RTC_SUPER_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_ENA_RTC_SUPER_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_ENA_RTC_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_ENA_RTC_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.INT_CLR_RTC: need_des +func (o *LP_WDT_Type) SetINT_CLR_RTC_SUPER_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_WDT_Type) GetINT_CLR_RTC_SUPER_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x40000000) >> 30 +} +func (o *LP_WDT_Type) SetINT_CLR_RTC_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetINT_CLR_RTC_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x80000000) >> 31 +} + +// LP_WDT.DATE: need_des +func (o *LP_WDT_Type) SetDATE_LP_WDT_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_WDT_Type) GetDATE_LP_WDT_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *LP_WDT_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_WDT_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Motor Control Pulse-Width Modulation 0 +type MCPWM_Type struct { + CLK_CFG volatile.Register32 // 0x0 + TIMER0_CFG0 volatile.Register32 // 0x4 + TIMER0_CFG1 volatile.Register32 // 0x8 + TIMER0_SYNC volatile.Register32 // 0xC + TIMER0_STATUS volatile.Register32 // 0x10 + TIMER1_CFG0 volatile.Register32 // 0x14 + TIMER1_CFG1 volatile.Register32 // 0x18 + TIMER1_SYNC volatile.Register32 // 0x1C + TIMER1_STATUS volatile.Register32 // 0x20 + TIMER2_CFG0 volatile.Register32 // 0x24 + TIMER2_CFG1 volatile.Register32 // 0x28 + TIMER2_SYNC volatile.Register32 // 0x2C + TIMER2_STATUS volatile.Register32 // 0x30 + TIMER_SYNCI_CFG volatile.Register32 // 0x34 + OPERATOR_TIMERSEL volatile.Register32 // 0x38 + GEN0_STMP_CFG volatile.Register32 // 0x3C + GEN0_TSTMP_A volatile.Register32 // 0x40 + GEN0_TSTMP_B volatile.Register32 // 0x44 + GEN0_CFG0 volatile.Register32 // 0x48 + GEN0_FORCE volatile.Register32 // 0x4C + GEN0_A volatile.Register32 // 0x50 + GEN0_B volatile.Register32 // 0x54 + DT0_CFG volatile.Register32 // 0x58 + DT0_FED_CFG volatile.Register32 // 0x5C + DT0_RED_CFG volatile.Register32 // 0x60 + CARRIER0_CFG volatile.Register32 // 0x64 + FH0_CFG0 volatile.Register32 // 0x68 + FH0_CFG1 volatile.Register32 // 0x6C + FH0_STATUS volatile.Register32 // 0x70 + GEN1_STMP_CFG volatile.Register32 // 0x74 + GEN1_TSTMP_A volatile.Register32 // 0x78 + GEN1_TSTMP_B volatile.Register32 // 0x7C + GEN1_CFG0 volatile.Register32 // 0x80 + GEN1_FORCE volatile.Register32 // 0x84 + GEN1_A volatile.Register32 // 0x88 + GEN1_B volatile.Register32 // 0x8C + DT1_CFG volatile.Register32 // 0x90 + DT1_FED_CFG volatile.Register32 // 0x94 + DT1_RED_CFG volatile.Register32 // 0x98 + CARRIER1_CFG volatile.Register32 // 0x9C + FH1_CFG0 volatile.Register32 // 0xA0 + FH1_CFG1 volatile.Register32 // 0xA4 + FH1_STATUS volatile.Register32 // 0xA8 + GEN2_STMP_CFG volatile.Register32 // 0xAC + GEN2_TSTMP_A volatile.Register32 // 0xB0 + GEN2_TSTMP_B volatile.Register32 // 0xB4 + GEN2_CFG0 volatile.Register32 // 0xB8 + GEN2_FORCE volatile.Register32 // 0xBC + GEN2_A volatile.Register32 // 0xC0 + GEN2_B volatile.Register32 // 0xC4 + DT2_CFG volatile.Register32 // 0xC8 + DT2_FED_CFG volatile.Register32 // 0xCC + DT2_RED_CFG volatile.Register32 // 0xD0 + CARRIER2_CFG volatile.Register32 // 0xD4 + FH2_CFG0 volatile.Register32 // 0xD8 + FH2_CFG1 volatile.Register32 // 0xDC + FH2_STATUS volatile.Register32 // 0xE0 + FAULT_DETECT volatile.Register32 // 0xE4 + CAP_TIMER_CFG volatile.Register32 // 0xE8 + CAP_TIMER_PHASE volatile.Register32 // 0xEC + CAP_CH0_CFG volatile.Register32 // 0xF0 + CAP_CH1_CFG volatile.Register32 // 0xF4 + CAP_CH2_CFG volatile.Register32 // 0xF8 + CAP_CH0 volatile.Register32 // 0xFC + CAP_CH1 volatile.Register32 // 0x100 + CAP_CH2 volatile.Register32 // 0x104 + CAP_STATUS volatile.Register32 // 0x108 + UPDATE_CFG volatile.Register32 // 0x10C + INT_ENA volatile.Register32 // 0x110 + INT_RAW volatile.Register32 // 0x114 + INT_ST volatile.Register32 // 0x118 + INT_CLR volatile.Register32 // 0x11C + EVT_EN volatile.Register32 // 0x120 + TASK_EN volatile.Register32 // 0x124 + CLK volatile.Register32 // 0x128 + VERSION volatile.Register32 // 0x12C +} + +// MCPWM.CLK_CFG: PWM clock prescaler register. +func (o *MCPWM_Type) SetCLK_CFG_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetCLK_CFG_CLK_PRESCALE() uint32 { + return volatile.LoadUint32(&o.CLK_CFG.Reg) & 0xff +} + +// MCPWM.TIMER0_CFG0: PWM timer0 period and update method configuration register. +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER0_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER0_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER0_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER0_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER0_CFG1: PWM timer0 working mode and start/stop control configuration register. +func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER0_START(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER0_START() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER0_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER0_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER0_SYNC: PWM timer0 sync function configuration register. +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER0_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER0_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER0_STATUS: PWM timer0 status register. +func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER0_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER0_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER0_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER0_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER1_CFG0: PWM timer1 period and update method configuration register. +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER1_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER1_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER1_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER1_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER1_CFG1: PWM timer1 working mode and start/stop control configuration register. +func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER1_START(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER1_START() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER1_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER1_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER1_SYNC: PWM timer1 sync function configuration register. +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER1_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER1_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER1_STATUS: PWM timer1 status register. +func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER1_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER1_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER1_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER1_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER2_CFG0: PWM timer2 period and update method configuration register. +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER2_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER2_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER2_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER2_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER2_CFG1: PWM timer2 working mode and start/stop control configuration register. +func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER2_START(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER2_START() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER2_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER2_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER2_SYNC: PWM timer2 sync function configuration register. +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER2_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER2_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER2_STATUS: PWM timer2 status register. +func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER2_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER2_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER2_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER2_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER_SYNCI_CFG: Synchronization input selection for three PWM timers. +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER0_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER0_SYNCISEL() uint32 { + return volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER1_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x38)|value<<3) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER1_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x38) >> 3 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER2_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x1c0)|value<<6) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER2_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x1c0) >> 6 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x800) >> 11 +} + +// MCPWM.OPERATOR_TIMERSEL: Select specific timer for PWM operators. +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL() uint32 { + return volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x3 +} +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x30) >> 4 +} + +// MCPWM.GEN0_STMP_CFG: Transfer status and update method for time stamp registers A and B +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR0_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR0_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR0_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR0_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR0_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR0_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR0_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR0_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN0_TSTMP_A: Shadow register for register A. +func (o *MCPWM_Type) SetGEN0_TSTMP_A_CMPR0_A(value uint32) { + volatile.StoreUint32(&o.GEN0_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN0_TSTMP_A_CMPR0_A() uint32 { + return volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN0_TSTMP_B: Shadow register for register B. +func (o *MCPWM_Type) SetGEN0_TSTMP_B_CMPR0_B(value uint32) { + volatile.StoreUint32(&o.GEN0_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN0_TSTMP_B_CMPR0_B() uint32 { + return volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN0_CFG0: Fault event T0 and T1 handling +func (o *MCPWM_Type) SetGEN0_CFG0_GEN0_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN0_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN0_CFG0_GEN0_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN0_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN0_CFG0_GEN0_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN0_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN0_FORCE: Permissives to force PWM0A and PWM0B outputs by software +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN0_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN0_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN0_A: Actions triggered by events on PWM0A +func (o *MCPWM_Type) SetGEN0_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN0_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN0_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN0_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN0_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN0_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN0_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN0_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN0_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN0_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN0_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN0_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN0_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN0_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN0_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN0_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN0_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN0_B: Actions triggered by events on PWM0B +func (o *MCPWM_Type) SetGEN0_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN0_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN0_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN0_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN0_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN0_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN0_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN0_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN0_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN0_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN0_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN0_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN0_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN0_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN0_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN0_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN0_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT0_CFG: dead time type selection and configuration +func (o *MCPWM_Type) SetDT0_CFG_DB0_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT0_CFG_DB0_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT0_CFG_DB0_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT0_FED_CFG: Shadow register for falling edge delay (FED). +func (o *MCPWM_Type) SetDT0_FED_CFG_DB0_FED(value uint32) { + volatile.StoreUint32(&o.DT0_FED_CFG.Reg, volatile.LoadUint32(&o.DT0_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT0_FED_CFG_DB0_FED() uint32 { + return volatile.LoadUint32(&o.DT0_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT0_RED_CFG: Shadow register for rising edge delay (RED). +func (o *MCPWM_Type) SetDT0_RED_CFG_DB0_RED(value uint32) { + volatile.StoreUint32(&o.DT0_RED_CFG.Reg, volatile.LoadUint32(&o.DT0_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT0_RED_CFG_DB0_RED() uint32 { + return volatile.LoadUint32(&o.DT0_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER0_CFG: Carrier enable and configuratoin +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER0_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER0_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH0_CFG0: Actions on PWM0A and PWM0B trip events +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ0_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ0_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH0_CFG1: Software triggers for fault handler actions +func (o *MCPWM_Type) SetFH0_CFG1_TZ0_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ0_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_CFG1_TZ0_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ0_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH0_CFG1_TZ0_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ0_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH0_CFG1_TZ0_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ0_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH0_STATUS: Status of fault events. +func (o *MCPWM_Type) SetFH0_STATUS_TZ0_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_STATUS_TZ0_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_STATUS_TZ0_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH0_STATUS_TZ0_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.GEN1_STMP_CFG: Transfer status and update method for time stamp registers A and B +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR1_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR1_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR1_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR1_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR1_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR1_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR1_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR1_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN1_TSTMP_A: Shadow register for register A. +func (o *MCPWM_Type) SetGEN1_TSTMP_A_CMPR1_A(value uint32) { + volatile.StoreUint32(&o.GEN1_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN1_TSTMP_A_CMPR1_A() uint32 { + return volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN1_TSTMP_B: Shadow register for register B. +func (o *MCPWM_Type) SetGEN1_TSTMP_B_CMPR1_B(value uint32) { + volatile.StoreUint32(&o.GEN1_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN1_TSTMP_B_CMPR1_B() uint32 { + return volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN1_CFG0: Fault event T0 and T1 handling +func (o *MCPWM_Type) SetGEN1_CFG0_GEN1_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN1_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN1_CFG0_GEN1_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN1_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN1_CFG0_GEN1_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN1_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN1_FORCE: Permissives to force PWM1A and PWM1B outputs by software +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN1_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN1_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN1_A: Actions triggered by events on PWM1A +func (o *MCPWM_Type) SetGEN1_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN1_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN1_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN1_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN1_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN1_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN1_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN1_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN1_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN1_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN1_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN1_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN1_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN1_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN1_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN1_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN1_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN1_B: Actions triggered by events on PWM1B +func (o *MCPWM_Type) SetGEN1_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN1_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN1_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN1_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN1_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN1_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN1_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN1_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN1_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN1_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN1_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN1_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN1_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN1_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN1_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN1_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN1_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT1_CFG: dead time type selection and configuration +func (o *MCPWM_Type) SetDT1_CFG_DB1_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT1_CFG_DB1_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT1_CFG_DB1_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT1_FED_CFG: Shadow register for falling edge delay (FED). +func (o *MCPWM_Type) SetDT1_FED_CFG_DB1_FED(value uint32) { + volatile.StoreUint32(&o.DT1_FED_CFG.Reg, volatile.LoadUint32(&o.DT1_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT1_FED_CFG_DB1_FED() uint32 { + return volatile.LoadUint32(&o.DT1_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT1_RED_CFG: Shadow register for rising edge delay (RED). +func (o *MCPWM_Type) SetDT1_RED_CFG_DB1_RED(value uint32) { + volatile.StoreUint32(&o.DT1_RED_CFG.Reg, volatile.LoadUint32(&o.DT1_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT1_RED_CFG_DB1_RED() uint32 { + return volatile.LoadUint32(&o.DT1_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER1_CFG: Carrier enable and configuratoin +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER1_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER1_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH1_CFG0: Actions on PWM1A and PWM1B trip events +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ1_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ1_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH1_CFG1: Software triggers for fault handler actions +func (o *MCPWM_Type) SetFH1_CFG1_TZ1_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ1_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_CFG1_TZ1_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ1_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH1_CFG1_TZ1_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ1_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH1_CFG1_TZ1_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ1_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH1_STATUS: Status of fault events. +func (o *MCPWM_Type) SetFH1_STATUS_TZ1_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_STATUS_TZ1_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_STATUS_TZ1_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH1_STATUS_TZ1_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.GEN2_STMP_CFG: Transfer status and update method for time stamp registers A and B +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR2_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR2_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR2_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR2_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR2_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR2_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR2_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR2_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN2_TSTMP_A: Shadow register for register A. +func (o *MCPWM_Type) SetGEN2_TSTMP_A_CMPR2_A(value uint32) { + volatile.StoreUint32(&o.GEN2_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN2_TSTMP_A_CMPR2_A() uint32 { + return volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN2_TSTMP_B: Shadow register for register B. +func (o *MCPWM_Type) SetGEN2_TSTMP_B_CMPR2_B(value uint32) { + volatile.StoreUint32(&o.GEN2_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN2_TSTMP_B_CMPR2_B() uint32 { + return volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN2_CFG0: Fault event T0 and T1 handling +func (o *MCPWM_Type) SetGEN2_CFG0_GEN2_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN2_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN2_CFG0_GEN2_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN2_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN2_CFG0_GEN2_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN2_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN2_FORCE: Permissives to force PWM2A and PWM2B outputs by software +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN2_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN2_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN2_A: Actions triggered by events on PWM2A +func (o *MCPWM_Type) SetGEN2_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN2_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN2_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN2_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN2_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN2_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN2_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN2_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN2_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN2_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN2_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN2_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN2_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN2_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN2_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN2_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN2_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN2_B: Actions triggered by events on PWM2B +func (o *MCPWM_Type) SetGEN2_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN2_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN2_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN2_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN2_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN2_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN2_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN2_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN2_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN2_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN2_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN2_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN2_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN2_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN2_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN2_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN2_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT2_CFG: dead time type selection and configuration +func (o *MCPWM_Type) SetDT2_CFG_DB2_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT2_CFG_DB2_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT2_CFG_DB2_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT2_FED_CFG: Shadow register for falling edge delay (FED). +func (o *MCPWM_Type) SetDT2_FED_CFG_DB2_FED(value uint32) { + volatile.StoreUint32(&o.DT2_FED_CFG.Reg, volatile.LoadUint32(&o.DT2_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT2_FED_CFG_DB2_FED() uint32 { + return volatile.LoadUint32(&o.DT2_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT2_RED_CFG: Shadow register for rising edge delay (RED). +func (o *MCPWM_Type) SetDT2_RED_CFG_DB2_RED(value uint32) { + volatile.StoreUint32(&o.DT2_RED_CFG.Reg, volatile.LoadUint32(&o.DT2_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT2_RED_CFG_DB2_RED() uint32 { + return volatile.LoadUint32(&o.DT2_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER2_CFG: Carrier enable and configuratoin +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER2_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER2_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH2_CFG0: Actions on PWM2A and PWM2B trip events +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ2_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ2_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH2_CFG1: Software triggers for fault handler actions +func (o *MCPWM_Type) SetFH2_CFG1_TZ2_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ2_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_CFG1_TZ2_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ2_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH2_CFG1_TZ2_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ2_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH2_CFG1_TZ2_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ2_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH2_STATUS: Status of fault events. +func (o *MCPWM_Type) SetFH2_STATUS_TZ2_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_STATUS_TZ2_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_STATUS_TZ2_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH2_STATUS_TZ2_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.FAULT_DETECT: Fault detection configuration and status +func (o *MCPWM_Type) SetFAULT_DETECT_F0_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F0_EN() uint32 { + return volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F1_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F1_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F2_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F2_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F0_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F0_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F1_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F1_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F2_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F2_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F0(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F0() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F1(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F1() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F2(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F2() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x100) >> 8 +} + +// MCPWM.CAP_TIMER_CFG: Configure capture timer +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_TIMER_EN() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_EN() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_SEL(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1c)|value<<2) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_SEL() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1c) >> 2 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x20) >> 5 +} + +// MCPWM.CAP_TIMER_PHASE: Phase for capture timer sync +func (o *MCPWM_Type) SetCAP_TIMER_PHASE(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_PHASE.Reg, value) +} +func (o *MCPWM_Type) GetCAP_TIMER_PHASE() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_PHASE.Reg) +} + +// MCPWM.CAP_CH0_CFG: Capture channel 0 configuration and enable +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP0_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP0_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH1_CFG: Capture channel 1 configuration and enable +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP1_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP1_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH2_CFG: Capture channel 2 configuration and enable +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP2_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP2_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH0: ch0 capture value status register +func (o *MCPWM_Type) SetCAP_CH0(value uint32) { + volatile.StoreUint32(&o.CAP_CH0.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH0() uint32 { + return volatile.LoadUint32(&o.CAP_CH0.Reg) +} + +// MCPWM.CAP_CH1: ch1 capture value status register +func (o *MCPWM_Type) SetCAP_CH1(value uint32) { + volatile.StoreUint32(&o.CAP_CH1.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH1() uint32 { + return volatile.LoadUint32(&o.CAP_CH1.Reg) +} + +// MCPWM.CAP_CH2: ch2 capture value status register +func (o *MCPWM_Type) SetCAP_CH2(value uint32) { + volatile.StoreUint32(&o.CAP_CH2.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH2() uint32 { + return volatile.LoadUint32(&o.CAP_CH2.Reg) +} + +// MCPWM.CAP_STATUS: Edge of last capture trigger +func (o *MCPWM_Type) SetCAP_STATUS_CAP0_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP0_EDGE() uint32 { + return volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_STATUS_CAP1_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP1_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetCAP_STATUS_CAP2_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP2_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x4) >> 2 +} + +// MCPWM.UPDATE_CFG: Enable update. +func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_UP_EN() uint32 { + return volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP0_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP0_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP0_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP0_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP1_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP1_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP1_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP1_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP2_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP2_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP2_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP2_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x80) >> 7 +} + +// MCPWM.INT_ENA: Interrupt enable bits +func (o *MCPWM_Type) SetINT_ENA_TIMER0_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_STOP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT0_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT0_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT1_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT1_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT2_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT2_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR0_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR0_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR1_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR1_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR2_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR2_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR0_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR0_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR1_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR1_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR2_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR2_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_ENA_TZ0_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_ENA_TZ0_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_ENA_TZ1_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_ENA_TZ1_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_ENA_TZ2_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_ENA_TZ2_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_ENA_TZ0_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_ENA_TZ0_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_ENA_TZ1_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_ENA_TZ1_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_ENA_TZ2_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_ENA_TZ2_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_ENA_CAP0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_ENA_CAP0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_ENA_CAP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_ENA_CAP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_ENA_CAP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_ENA_CAP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_RAW: Raw interrupt status +func (o *MCPWM_Type) SetINT_RAW_TIMER0_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_STOP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT0_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT0_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT1_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT1_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT2_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT2_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR0_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR0_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR1_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR1_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR2_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR2_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR0_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR0_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR1_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR1_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR2_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR2_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_RAW_TZ0_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_RAW_TZ0_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_RAW_TZ1_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_RAW_TZ1_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_RAW_TZ2_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_RAW_TZ2_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_RAW_TZ0_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_RAW_TZ0_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_RAW_TZ1_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_RAW_TZ1_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_RAW_TZ2_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_RAW_TZ2_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_RAW_CAP0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_RAW_CAP0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_RAW_CAP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_RAW_CAP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_RAW_CAP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_RAW_CAP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_ST: Masked interrupt status +func (o *MCPWM_Type) SetINT_ST_TIMER0_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_STOP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_ST_TIMER0_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_ST_TIMER0_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_ST_FAULT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_ST_FAULT0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_ST_FAULT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_ST_FAULT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_ST_FAULT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_ST_FAULT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_ST_FAULT0_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_ST_FAULT0_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_ST_FAULT1_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_ST_FAULT1_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_ST_FAULT2_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_ST_FAULT2_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_ST_CMPR0_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_ST_CMPR0_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_ST_CMPR1_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_ST_CMPR1_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_ST_CMPR2_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_ST_CMPR2_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_ST_CMPR0_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_ST_CMPR0_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_ST_CMPR1_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_ST_CMPR1_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_ST_CMPR2_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_ST_CMPR2_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_ST_TZ0_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_ST_TZ0_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_ST_TZ1_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_ST_TZ1_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_ST_TZ2_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_ST_TZ2_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_ST_TZ0_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_ST_TZ0_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_ST_TZ1_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_ST_TZ1_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_ST_TZ2_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_ST_TZ2_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_ST_CAP0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_ST_CAP0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_ST_CAP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_ST_CAP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_ST_CAP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_ST_CAP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_CLR: Interrupt clear bits +func (o *MCPWM_Type) SetINT_CLR_TIMER0_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_STOP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT0_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT0_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT1_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT1_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT2_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT2_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR0_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR0_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR1_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR1_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR2_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR2_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR0_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR0_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR1_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR1_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR2_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR2_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_CLR_TZ0_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_CLR_TZ0_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_CLR_TZ1_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_CLR_TZ1_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_CLR_TZ2_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_CLR_TZ2_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_CLR_TZ0_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_CLR_TZ0_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_CLR_TZ1_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_CLR_TZ1_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_CLR_TZ2_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_CLR_TZ2_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_CLR_CAP0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_CLR_CAP0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_CLR_CAP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_CLR_CAP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_CLR_CAP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_CLR_CAP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} + +// MCPWM.EVT_EN: MCPWM event enable register +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_STOP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_STOP_EN() uint32 { + return volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_STOP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_STOP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_TEZ_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_TEZ_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_TEZ_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_TEZ_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_TEZ_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_TEZ_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_TEP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_TEP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_TEP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_TEP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_TEP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_TEP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP0_TEA_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP0_TEA_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP1_TEA_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP1_TEA_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP2_TEA_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP2_TEA_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP0_TEB_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP0_TEB_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP1_TEB_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP1_TEB_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP2_TEB_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP2_TEB_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F0_CLR_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F0_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F1_CLR_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F1_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F2_CLR_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F2_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ0_CBC_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ0_CBC_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ1_CBC_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ1_CBC_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ2_CBC_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ2_CBC_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ0_OST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ0_OST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ1_OST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ1_OST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ2_OST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ2_OST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_CAP0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_CAP1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_CAP2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20000000) >> 29 +} + +// MCPWM.TASK_EN: MCPWM task enable register +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR0_A_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR0_A_UP_EN() uint32 { + return volatile.LoadUint32(&o.TASK_EN.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR1_A_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR1_A_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR2_A_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR2_A_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR0_B_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR0_B_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR1_B_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR1_B_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR2_B_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR2_B_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_GEN_STOP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_GEN_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER0_SYNC_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER0_SYNC_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER1_SYNC_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER1_SYNC_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER2_SYNC_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER2_SYNC_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER0_PERIOD_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER0_PERIOD_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER1_PERIOD_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER1_PERIOD_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER2_PERIOD_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER2_PERIOD_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TZ0_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TZ0_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TZ1_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TZ1_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TZ2_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TZ2_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CLR0_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CLR0_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CLR1_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CLR1_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CLR2_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CLR2_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CAP0_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CAP1_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CAP2_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x200000) >> 21 +} + +// MCPWM.CLK: MCPWM APB configuration register +func (o *MCPWM_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} + +// MCPWM.VERSION: Version register. +func (o *MCPWM_Type) SetVERSION_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *MCPWM_Type) GetVERSION_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// MEM_MONITOR Peripheral +type MEM_MONITOR_Type struct { + LOG_SETTING volatile.Register32 // 0x0 + LOG_CHECK_DATA volatile.Register32 // 0x4 + LOG_DATA_MASK volatile.Register32 // 0x8 + LOG_MIN volatile.Register32 // 0xC + LOG_MAX volatile.Register32 // 0x10 + LOG_MEM_START volatile.Register32 // 0x14 + LOG_MEM_END volatile.Register32 // 0x18 + LOG_MEM_CURRENT_ADDR volatile.Register32 // 0x1C + LOG_MEM_ADDR_UPDATE volatile.Register32 // 0x20 + LOG_MEM_FULL_FLAG volatile.Register32 // 0x24 + CLOCK_GATE volatile.Register32 // 0x28 + _ [976]byte + DATE volatile.Register32 // 0x3FC +} + +// MEM_MONITOR.LOG_SETTING: log config regsiter +func (o *MEM_MONITOR_Type) SetLOG_SETTING_LOG_ENA(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x7)|value) +} +func (o *MEM_MONITOR_Type) GetLOG_SETTING_LOG_ENA() uint32 { + return volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x7 +} +func (o *MEM_MONITOR_Type) SetLOG_SETTING_LOG_MODE(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x78)|value<<3) +} +func (o *MEM_MONITOR_Type) GetLOG_SETTING_LOG_MODE() uint32 { + return (volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x78) >> 3 +} +func (o *MEM_MONITOR_Type) SetLOG_SETTING_LOG_MEM_LOOP_ENABLE(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x80)|value<<7) +} +func (o *MEM_MONITOR_Type) GetLOG_SETTING_LOG_MEM_LOOP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x80) >> 7 +} + +// MEM_MONITOR.LOG_CHECK_DATA: check data regsiter +func (o *MEM_MONITOR_Type) SetLOG_CHECK_DATA(value uint32) { + volatile.StoreUint32(&o.LOG_CHECK_DATA.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_CHECK_DATA() uint32 { + return volatile.LoadUint32(&o.LOG_CHECK_DATA.Reg) +} + +// MEM_MONITOR.LOG_DATA_MASK: check data mask register +func (o *MEM_MONITOR_Type) SetLOG_DATA_MASK(value uint32) { + volatile.StoreUint32(&o.LOG_DATA_MASK.Reg, volatile.LoadUint32(&o.LOG_DATA_MASK.Reg)&^(0xf)|value) +} +func (o *MEM_MONITOR_Type) GetLOG_DATA_MASK() uint32 { + return volatile.LoadUint32(&o.LOG_DATA_MASK.Reg) & 0xf +} + +// MEM_MONITOR.LOG_MIN: log boundary regsiter +func (o *MEM_MONITOR_Type) SetLOG_MIN(value uint32) { + volatile.StoreUint32(&o.LOG_MIN.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MIN() uint32 { + return volatile.LoadUint32(&o.LOG_MIN.Reg) +} + +// MEM_MONITOR.LOG_MAX: log boundary regsiter +func (o *MEM_MONITOR_Type) SetLOG_MAX(value uint32) { + volatile.StoreUint32(&o.LOG_MAX.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MAX() uint32 { + return volatile.LoadUint32(&o.LOG_MAX.Reg) +} + +// MEM_MONITOR.LOG_MEM_START: log message store range register +func (o *MEM_MONITOR_Type) SetLOG_MEM_START(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_START.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_START() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_START.Reg) +} + +// MEM_MONITOR.LOG_MEM_END: log message store range register +func (o *MEM_MONITOR_Type) SetLOG_MEM_END(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_END.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_END() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_END.Reg) +} + +// MEM_MONITOR.LOG_MEM_CURRENT_ADDR: current writing address. +func (o *MEM_MONITOR_Type) SetLOG_MEM_CURRENT_ADDR(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_CURRENT_ADDR.Reg, value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_CURRENT_ADDR() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_CURRENT_ADDR.Reg) +} + +// MEM_MONITOR.LOG_MEM_ADDR_UPDATE: writing address update +func (o *MEM_MONITOR_Type) SetLOG_MEM_ADDR_UPDATE(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_ADDR_UPDATE.Reg, volatile.LoadUint32(&o.LOG_MEM_ADDR_UPDATE.Reg)&^(0x1)|value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_ADDR_UPDATE() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_ADDR_UPDATE.Reg) & 0x1 +} + +// MEM_MONITOR.LOG_MEM_FULL_FLAG: full flag status register +func (o *MEM_MONITOR_Type) SetLOG_MEM_FULL_FLAG(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_FULL_FLAG.Reg, volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg)&^(0x1)|value) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_FULL_FLAG() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg) & 0x1 +} +func (o *MEM_MONITOR_Type) SetLOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_FULL_FLAG.Reg, volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg)&^(0x2)|value<<1) +} +func (o *MEM_MONITOR_Type) GetLOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG() uint32 { + return (volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg) & 0x2) >> 1 +} + +// MEM_MONITOR.CLOCK_GATE: clock gate force on register +func (o *MEM_MONITOR_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *MEM_MONITOR_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// MEM_MONITOR.DATE: version register +func (o *MEM_MONITOR_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *MEM_MONITOR_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// MODEM_LPCON Peripheral +type MODEM_LPCON_Type struct { + TEST_CONF volatile.Register32 // 0x0 + COEX_LP_CLK_CONF volatile.Register32 // 0x4 + CLK_CONF volatile.Register32 // 0x8 + CLK_CONF_FORCE_ON volatile.Register32 // 0xC + TICK_CONF volatile.Register32 // 0x10 + RST_CONF volatile.Register32 // 0x14 + MEM_CONF volatile.Register32 // 0x18 + DATE volatile.Register32 // 0x1C +} + +// MODEM_LPCON.TEST_CONF +func (o *MODEM_LPCON_Type) SetTEST_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetTEST_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x1 +} + +// MODEM_LPCON.COEX_LP_CLK_CONF +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW() uint32 { + return volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x1 +} +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0x8) >> 3 +} +func (o *MODEM_LPCON_Type) SetCOEX_LP_CLK_CONF_CLK_COEX_LP_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.COEX_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg)&^(0xfff0)|value<<4) +} +func (o *MODEM_LPCON_Type) GetCOEX_LP_CLK_CONF_CLK_COEX_LP_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.COEX_LP_CLK_CONF.Reg) & 0xfff0) >> 4 +} + +// MODEM_LPCON.CLK_CONF +func (o *MODEM_LPCON_Type) SetCLK_CONF_CLK_COEX_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_CLK_COEX_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_CLK_I2C_MST_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_CLK_I2C_MST_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_CLK_FE_MEM_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x20)|value<<5) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_CLK_FE_MEM_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x20) >> 5 +} + +// MODEM_LPCON.CLK_CONF_FORCE_ON +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_COEX_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_COEX_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_I2C_MST_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_I2C_MST_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetCLK_CONF_FORCE_ON_CLK_FE_MEM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x20)|value<<5) +} +func (o *MODEM_LPCON_Type) GetCLK_CONF_FORCE_ON_CLK_FE_MEM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x20) >> 5 +} + +// MODEM_LPCON.TICK_CONF +func (o *MODEM_LPCON_Type) SetTICK_CONF_PWR_TICK_TARGET(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0x3f)|value) +} +func (o *MODEM_LPCON_Type) GetTICK_CONF_PWR_TICK_TARGET() uint32 { + return volatile.LoadUint32(&o.TICK_CONF.Reg) & 0x3f +} + +// MODEM_LPCON.RST_CONF +func (o *MODEM_LPCON_Type) SetRST_CONF_RST_COEX(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x2)|value<<1) +} +func (o *MODEM_LPCON_Type) GetRST_CONF_RST_COEX() uint32 { + return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x2) >> 1 +} +func (o *MODEM_LPCON_Type) SetRST_CONF_RST_I2C_MST(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetRST_CONF_RST_I2C_MST() uint32 { + return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x4) >> 2 +} + +// MODEM_LPCON.MEM_CONF +func (o *MODEM_LPCON_Type) SetMEM_CONF_AGC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4)|value<<2) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_AGC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4) >> 2 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_AGC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x8)|value<<3) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_AGC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x8) >> 3 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_PBUS_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x10)|value<<4) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_PBUS_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x10) >> 4 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_PBUS_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x20)|value<<5) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_PBUS_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x20) >> 5 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_I2C_MST_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x100)|value<<8) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_I2C_MST_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x100) >> 8 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_I2C_MST_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x200)|value<<9) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_I2C_MST_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x200) >> 9 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_CHAN_FREQ_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x400)|value<<10) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_CHAN_FREQ_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x400) >> 10 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_CHAN_FREQ_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x800)|value<<11) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_CHAN_FREQ_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x800) >> 11 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_MODEM_PWR_MEM_WP(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x7000)|value<<12) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_MODEM_PWR_MEM_WP() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x7000) >> 12 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_MODEM_PWR_MEM_WA(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x38000)|value<<15) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_MODEM_PWR_MEM_WA() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x38000) >> 15 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_MODEM_PWR_MEM_RA(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xc0000)|value<<18) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_MODEM_PWR_MEM_RA() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xc0000) >> 18 +} +func (o *MODEM_LPCON_Type) SetMEM_CONF_MODEM_PWR_MEM_RM(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xf00000)|value<<20) +} +func (o *MODEM_LPCON_Type) GetMEM_CONF_MODEM_PWR_MEM_RM() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xf00000) >> 20 +} + +// MODEM_LPCON.DATE +func (o *MODEM_LPCON_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *MODEM_LPCON_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// MODEM_SYSCON Peripheral +type MODEM_SYSCON_Type struct { + TEST_CONF volatile.Register32 // 0x0 + CLK_CONF volatile.Register32 // 0x4 + CLK_CONF_FORCE_ON volatile.Register32 // 0x8 + MODEM_RST_CONF volatile.Register32 // 0xC + CLK_CONF1 volatile.Register32 // 0x10 + CLK_CONF1_FORCE_ON volatile.Register32 // 0x14 + MEM_CONF volatile.Register32 // 0x18 + DATE volatile.Register32 // 0x1C +} + +// MODEM_SYSCON.TEST_CONF +func (o *MODEM_SYSCON_Type) SetTEST_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x1)|value) +} +func (o *MODEM_SYSCON_Type) GetTEST_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x1 +} + +// MODEM_SYSCON.CLK_CONF +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_ETM_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_ZB_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_ZB_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_ZB_MAC_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_ZB_MAC_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x800000) >> 23 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_ECB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_ECB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_CCM_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_CCM_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_BAH_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_BAH_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_MODEM_SEC_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_MODEM_SEC_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000000) >> 28 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_BLE_TIMER_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_BLE_TIMER_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x20000000) >> 29 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_BLE_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_BLE_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x40000000) >> 30 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_CLK_DATA_DUMP_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_CLK_DATA_DUMP_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x80000000) >> 31 +} + +// MODEM_SYSCON.CLK_CONF_FORCE_ON +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_ETM_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x400000)|value<<22) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_ETM_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x400000) >> 22 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_ZB_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x1000000)|value<<24) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_ZB_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x1000000) >> 24 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x20000000)|value<<29) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x20000000) >> 29 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x40000000)|value<<30) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x40000000) >> 30 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg)&^(0x80000000)|value<<31) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF_FORCE_ON.Reg) & 0x80000000) >> 31 +} + +// MODEM_SYSCON.MODEM_RST_CONF +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_FE(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_FE() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x4000) >> 14 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BTMAC_APB(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BTMAC_APB() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x8000) >> 15 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BTMAC(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BTMAC() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x10000) >> 16 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BTBB_APB(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BTBB_APB() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x20000) >> 17 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BTBB(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BTBB() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x40000) >> 18 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_ETM(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_ETM() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x400000) >> 22 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_ZBMAC(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_ZBMAC() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x1000000) >> 24 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_MODEM_ECB(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_MODEM_ECB() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x2000000) >> 25 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_MODEM_CCM(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_MODEM_CCM() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x4000000) >> 26 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_MODEM_BAH(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_MODEM_BAH() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x8000000) >> 27 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_MODEM_SEC(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_MODEM_SEC() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x20000000) >> 29 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_BLE_TIMER(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_BLE_TIMER() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x40000000) >> 30 +} +func (o *MODEM_SYSCON_Type) SetMODEM_RST_CONF_RST_DATA_DUMP(value uint32) { + volatile.StoreUint32(&o.MODEM_RST_CONF.Reg, volatile.LoadUint32(&o.MODEM_RST_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *MODEM_SYSCON_Type) GetMODEM_RST_CONF_RST_DATA_DUMP() uint32 { + return (volatile.LoadUint32(&o.MODEM_RST_CONF.Reg) & 0x80000000) >> 31 +} + +// MODEM_SYSCON.CLK_CONF1 +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_16M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x1000)|value<<12) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_16M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x1000) >> 12 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_32M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_32M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x2000) >> 13 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_SDM_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_SDM_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x4000) >> 14 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_ADC_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_ADC_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x8000) >> 15 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_FE_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_FE_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x10000) >> 16 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_BT_APB_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_BT_APB_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x20000) >> 17 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_CLK_BT_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1.Reg, volatile.LoadUint32(&o.CLK_CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_CLK_BT_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1.Reg) & 0x40000) >> 18 +} + +// MODEM_SYSCON.CLK_CONF1_FORCE_ON +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_FE_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x10000)|value<<16) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_FE_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x10000) >> 16 +} +func (o *MODEM_SYSCON_Type) SetCLK_CONF1_FORCE_ON_CLK_BT_FO(value uint32) { + volatile.StoreUint32(&o.CLK_CONF1_FORCE_ON.Reg, volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg)&^(0x40000)|value<<18) +} +func (o *MODEM_SYSCON_Type) GetCLK_CONF1_FORCE_ON_CLK_BT_FO() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF1_FORCE_ON.Reg) & 0x40000) >> 18 +} + +// MODEM_SYSCON.MEM_CONF +func (o *MODEM_SYSCON_Type) SetMEM_CONF_MODEM_MEM_WP(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x7)|value) +} +func (o *MODEM_SYSCON_Type) GetMEM_CONF_MODEM_MEM_WP() uint32 { + return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x7 +} +func (o *MODEM_SYSCON_Type) SetMEM_CONF_MODEM_MEM_WA(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x38)|value<<3) +} +func (o *MODEM_SYSCON_Type) GetMEM_CONF_MODEM_MEM_WA() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x38) >> 3 +} +func (o *MODEM_SYSCON_Type) SetMEM_CONF_MODEM_MEM_RA(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xc0)|value<<6) +} +func (o *MODEM_SYSCON_Type) GetMEM_CONF_MODEM_MEM_RA() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xc0) >> 6 +} + +// MODEM_SYSCON.DATE +func (o *MODEM_SYSCON_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *MODEM_SYSCON_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// OTP_DEBUG Peripheral +type OTP_DEBUG_Type struct { + WR_DIS volatile.Register32 // 0x0 + BLK0_BACKUP1_W1 volatile.Register32 // 0x4 + BLK0_BACKUP1_W2 volatile.Register32 // 0x8 + BLK0_BACKUP1_W3 volatile.Register32 // 0xC + BLK0_BACKUP1_W4 volatile.Register32 // 0x10 + BLK0_BACKUP1_W5 volatile.Register32 // 0x14 + BLK0_BACKUP2_W1 volatile.Register32 // 0x18 + BLK0_BACKUP2_W2 volatile.Register32 // 0x1C + BLK0_BACKUP2_W3 volatile.Register32 // 0x20 + BLK0_BACKUP2_W4 volatile.Register32 // 0x24 + BLK0_BACKUP2_W5 volatile.Register32 // 0x28 + BLK0_BACKUP3_W1 volatile.Register32 // 0x2C + BLK0_BACKUP3_W2 volatile.Register32 // 0x30 + BLK0_BACKUP3_W3 volatile.Register32 // 0x34 + BLK0_BACKUP3_W4 volatile.Register32 // 0x38 + BLK0_BACKUP3_W5 volatile.Register32 // 0x3C + BLK0_BACKUP4_W1 volatile.Register32 // 0x40 + BLK0_BACKUP4_W2 volatile.Register32 // 0x44 + BLK0_BACKUP4_W3 volatile.Register32 // 0x48 + BLK0_BACKUP4_W4 volatile.Register32 // 0x4C + BLK0_BACKUP4_W5 volatile.Register32 // 0x50 + BLK1_W1 volatile.Register32 // 0x54 + BLK1_W2 volatile.Register32 // 0x58 + BLK1_W3 volatile.Register32 // 0x5C + BLK1_W4 volatile.Register32 // 0x60 + BLK1_W5 volatile.Register32 // 0x64 + BLK1_W6 volatile.Register32 // 0x68 + BLK1_W7 volatile.Register32 // 0x6C + BLK1_W8 volatile.Register32 // 0x70 + BLK1_W9 volatile.Register32 // 0x74 + BLK2_W1 volatile.Register32 // 0x78 + BLK2_W2 volatile.Register32 // 0x7C + BLK2_W3 volatile.Register32 // 0x80 + BLK2_W4 volatile.Register32 // 0x84 + BLK2_W5 volatile.Register32 // 0x88 + BLK2_W6 volatile.Register32 // 0x8C + BLK2_W7 volatile.Register32 // 0x90 + BLK2_W8 volatile.Register32 // 0x94 + BLK2_W9 volatile.Register32 // 0x98 + BLK2_W10 volatile.Register32 // 0x9C + BLK2_W11 volatile.Register32 // 0xA0 + BLK3_W1 volatile.Register32 // 0xA4 + BLK3_W2 volatile.Register32 // 0xA8 + BLK3_W3 volatile.Register32 // 0xAC + BLK3_W4 volatile.Register32 // 0xB0 + BLK3_W5 volatile.Register32 // 0xB4 + BLK3_W6 volatile.Register32 // 0xB8 + BLK3_W7 volatile.Register32 // 0xBC + BLK3_W8 volatile.Register32 // 0xC0 + BLK3_W9 volatile.Register32 // 0xC4 + BLK3_W10 volatile.Register32 // 0xC8 + BLK3_W11 volatile.Register32 // 0xCC + BLK4_W1 volatile.Register32 // 0xD0 + BLK4_W2 volatile.Register32 // 0xD4 + BLK4_W3 volatile.Register32 // 0xD8 + BLK4_W4 volatile.Register32 // 0xDC + BLK4_W5 volatile.Register32 // 0xE0 + BLK4_W6 volatile.Register32 // 0xE4 + BLK4_W7 volatile.Register32 // 0xE8 + BLK4_W8 volatile.Register32 // 0xEC + BLK4_W9 volatile.Register32 // 0xF0 + BLK4_W10 volatile.Register32 // 0xF4 + BLK4_W11 volatile.Register32 // 0xF8 + BLK5_W1 volatile.Register32 // 0xFC + BLK5_W2 volatile.Register32 // 0x100 + BLK5_W3 volatile.Register32 // 0x104 + BLK5_W4 volatile.Register32 // 0x108 + BLK5_W5 volatile.Register32 // 0x10C + BLK5_W6 volatile.Register32 // 0x110 + BLK5_W7 volatile.Register32 // 0x114 + BLK5_W8 volatile.Register32 // 0x118 + BLK5_W9 volatile.Register32 // 0x11C + BLK5_W10 volatile.Register32 // 0x120 + BLK5_W11 volatile.Register32 // 0x124 + BLK6_W1 volatile.Register32 // 0x128 + BLK6_W2 volatile.Register32 // 0x12C + BLK6_W3 volatile.Register32 // 0x130 + BLK6_W4 volatile.Register32 // 0x134 + BLK6_W5 volatile.Register32 // 0x138 + BLK6_W6 volatile.Register32 // 0x13C + BLK6_W7 volatile.Register32 // 0x140 + BLK6_W8 volatile.Register32 // 0x144 + BLK6_W9 volatile.Register32 // 0x148 + BLK6_W10 volatile.Register32 // 0x14C + BLK6_W11 volatile.Register32 // 0x150 + BLK7_W1 volatile.Register32 // 0x154 + BLK7_W2 volatile.Register32 // 0x158 + BLK7_W3 volatile.Register32 // 0x15C + BLK7_W4 volatile.Register32 // 0x160 + BLK7_W5 volatile.Register32 // 0x164 + BLK7_W6 volatile.Register32 // 0x168 + BLK7_W7 volatile.Register32 // 0x16C + BLK7_W8 volatile.Register32 // 0x170 + BLK7_W9 volatile.Register32 // 0x174 + BLK7_W10 volatile.Register32 // 0x178 + BLK7_W11 volatile.Register32 // 0x17C + BLK8_W1 volatile.Register32 // 0x180 + BLK8_W2 volatile.Register32 // 0x184 + BLK8_W3 volatile.Register32 // 0x188 + BLK8_W4 volatile.Register32 // 0x18C + BLK8_W5 volatile.Register32 // 0x190 + BLK8_W6 volatile.Register32 // 0x194 + BLK8_W7 volatile.Register32 // 0x198 + BLK8_W8 volatile.Register32 // 0x19C + BLK8_W9 volatile.Register32 // 0x1A0 + BLK8_W10 volatile.Register32 // 0x1A4 + BLK8_W11 volatile.Register32 // 0x1A8 + BLK9_W1 volatile.Register32 // 0x1AC + BLK9_W2 volatile.Register32 // 0x1B0 + BLK9_W3 volatile.Register32 // 0x1B4 + BLK9_W4 volatile.Register32 // 0x1B8 + BLK9_W5 volatile.Register32 // 0x1BC + BLK9_W6 volatile.Register32 // 0x1C0 + BLK9_W7 volatile.Register32 // 0x1C4 + BLK9_W8 volatile.Register32 // 0x1C8 + BLK9_W9 volatile.Register32 // 0x1CC + BLK9_W10 volatile.Register32 // 0x1D0 + BLK9_W11 volatile.Register32 // 0x1D4 + BLK10_W1 volatile.Register32 // 0x1D8 + BLK10_W2 volatile.Register32 // 0x1DC + BLK10_W3 volatile.Register32 // 0x1E0 + BLK10_W4 volatile.Register32 // 0x1E4 + BLK10_W5 volatile.Register32 // 0x1E8 + BLK10_W6 volatile.Register32 // 0x1EC + BLK10_W7 volatile.Register32 // 0x1F0 + BLK10_W8 volatile.Register32 // 0x1F4 + BLK10_W9 volatile.Register32 // 0x1F8 + BLK10_W10 volatile.Register32 // 0x1FC + BLK10_W11 volatile.Register32 // 0x200 + CLK volatile.Register32 // 0x204 + APB2OTP_EN volatile.Register32 // 0x208 + DATE volatile.Register32 // 0x20C +} + +// OTP_DEBUG.WR_DIS: Otp debuger block0 data register1. +func (o *OTP_DEBUG_Type) SetWR_DIS(value uint32) { + volatile.StoreUint32(&o.WR_DIS.Reg, value) +} +func (o *OTP_DEBUG_Type) GetWR_DIS() uint32 { + return volatile.LoadUint32(&o.WR_DIS.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W1: Otp debuger block0 data register2. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W1(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W1() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W1.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W2: Otp debuger block0 data register3. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W2(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W2() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W2.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W3: Otp debuger block0 data register4. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W3(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W3() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W3.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W4: Otp debuger block0 data register5. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W4(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W4() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W4.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP1_W5: Otp debuger block0 data register6. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP1_W5(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP1_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP1_W5() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP1_W5.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W1: Otp debuger block0 data register7. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W1(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W1() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W1.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W2: Otp debuger block0 data register8. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W2(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W2() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W2.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W3: Otp debuger block0 data register9. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W3(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W3() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W3.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W4: Otp debuger block0 data register10. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W4(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W4() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W4.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP2_W5: Otp debuger block0 data register11. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP2_W5(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP2_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP2_W5() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP2_W5.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W1: Otp debuger block0 data register12. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W1(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W1() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W1.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W2: Otp debuger block0 data register13. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W2(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W2() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W2.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W3: Otp debuger block0 data register14. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W3(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W3() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W3.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W4: Otp debuger block0 data register15. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W4(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W4() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W4.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP3_W5: Otp debuger block0 data register16. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP3_W5(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP3_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP3_W5() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP3_W5.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W1: Otp debuger block0 data register17. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W1(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W1() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W1.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W2: Otp debuger block0 data register18. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W2(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W2() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W2.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W3: Otp debuger block0 data register19. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W3(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W3() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W3.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W4: Otp debuger block0 data register20. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W4(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W4() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W4.Reg) +} + +// OTP_DEBUG.BLK0_BACKUP4_W5: Otp debuger block0 data register21. +func (o *OTP_DEBUG_Type) SetBLK0_BACKUP4_W5(value uint32) { + volatile.StoreUint32(&o.BLK0_BACKUP4_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK0_BACKUP4_W5() uint32 { + return volatile.LoadUint32(&o.BLK0_BACKUP4_W5.Reg) +} + +// OTP_DEBUG.BLK1_W1: Otp debuger block1 data register1. +func (o *OTP_DEBUG_Type) SetBLK1_W1(value uint32) { + volatile.StoreUint32(&o.BLK1_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W1() uint32 { + return volatile.LoadUint32(&o.BLK1_W1.Reg) +} + +// OTP_DEBUG.BLK1_W2: Otp debuger block1 data register2. +func (o *OTP_DEBUG_Type) SetBLK1_W2(value uint32) { + volatile.StoreUint32(&o.BLK1_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W2() uint32 { + return volatile.LoadUint32(&o.BLK1_W2.Reg) +} + +// OTP_DEBUG.BLK1_W3: Otp debuger block1 data register3. +func (o *OTP_DEBUG_Type) SetBLK1_W3(value uint32) { + volatile.StoreUint32(&o.BLK1_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W3() uint32 { + return volatile.LoadUint32(&o.BLK1_W3.Reg) +} + +// OTP_DEBUG.BLK1_W4: Otp debuger block1 data register4. +func (o *OTP_DEBUG_Type) SetBLK1_W4(value uint32) { + volatile.StoreUint32(&o.BLK1_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W4() uint32 { + return volatile.LoadUint32(&o.BLK1_W4.Reg) +} + +// OTP_DEBUG.BLK1_W5: Otp debuger block1 data register5. +func (o *OTP_DEBUG_Type) SetBLK1_W5(value uint32) { + volatile.StoreUint32(&o.BLK1_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W5() uint32 { + return volatile.LoadUint32(&o.BLK1_W5.Reg) +} + +// OTP_DEBUG.BLK1_W6: Otp debuger block1 data register6. +func (o *OTP_DEBUG_Type) SetBLK1_W6(value uint32) { + volatile.StoreUint32(&o.BLK1_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W6() uint32 { + return volatile.LoadUint32(&o.BLK1_W6.Reg) +} + +// OTP_DEBUG.BLK1_W7: Otp debuger block1 data register7. +func (o *OTP_DEBUG_Type) SetBLK1_W7(value uint32) { + volatile.StoreUint32(&o.BLK1_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W7() uint32 { + return volatile.LoadUint32(&o.BLK1_W7.Reg) +} + +// OTP_DEBUG.BLK1_W8: Otp debuger block1 data register8. +func (o *OTP_DEBUG_Type) SetBLK1_W8(value uint32) { + volatile.StoreUint32(&o.BLK1_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W8() uint32 { + return volatile.LoadUint32(&o.BLK1_W8.Reg) +} + +// OTP_DEBUG.BLK1_W9: Otp debuger block1 data register9. +func (o *OTP_DEBUG_Type) SetBLK1_W9(value uint32) { + volatile.StoreUint32(&o.BLK1_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK1_W9() uint32 { + return volatile.LoadUint32(&o.BLK1_W9.Reg) +} + +// OTP_DEBUG.BLK2_W1: Otp debuger block2 data register1. +func (o *OTP_DEBUG_Type) SetBLK2_W1(value uint32) { + volatile.StoreUint32(&o.BLK2_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W1() uint32 { + return volatile.LoadUint32(&o.BLK2_W1.Reg) +} + +// OTP_DEBUG.BLK2_W2: Otp debuger block2 data register2. +func (o *OTP_DEBUG_Type) SetBLK2_W2(value uint32) { + volatile.StoreUint32(&o.BLK2_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W2() uint32 { + return volatile.LoadUint32(&o.BLK2_W2.Reg) +} + +// OTP_DEBUG.BLK2_W3: Otp debuger block2 data register3. +func (o *OTP_DEBUG_Type) SetBLK2_W3(value uint32) { + volatile.StoreUint32(&o.BLK2_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W3() uint32 { + return volatile.LoadUint32(&o.BLK2_W3.Reg) +} + +// OTP_DEBUG.BLK2_W4: Otp debuger block2 data register4. +func (o *OTP_DEBUG_Type) SetBLK2_W4(value uint32) { + volatile.StoreUint32(&o.BLK2_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W4() uint32 { + return volatile.LoadUint32(&o.BLK2_W4.Reg) +} + +// OTP_DEBUG.BLK2_W5: Otp debuger block2 data register5. +func (o *OTP_DEBUG_Type) SetBLK2_W5(value uint32) { + volatile.StoreUint32(&o.BLK2_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W5() uint32 { + return volatile.LoadUint32(&o.BLK2_W5.Reg) +} + +// OTP_DEBUG.BLK2_W6: Otp debuger block2 data register6. +func (o *OTP_DEBUG_Type) SetBLK2_W6(value uint32) { + volatile.StoreUint32(&o.BLK2_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W6() uint32 { + return volatile.LoadUint32(&o.BLK2_W6.Reg) +} + +// OTP_DEBUG.BLK2_W7: Otp debuger block2 data register7. +func (o *OTP_DEBUG_Type) SetBLK2_W7(value uint32) { + volatile.StoreUint32(&o.BLK2_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W7() uint32 { + return volatile.LoadUint32(&o.BLK2_W7.Reg) +} + +// OTP_DEBUG.BLK2_W8: Otp debuger block2 data register8. +func (o *OTP_DEBUG_Type) SetBLK2_W8(value uint32) { + volatile.StoreUint32(&o.BLK2_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W8() uint32 { + return volatile.LoadUint32(&o.BLK2_W8.Reg) +} + +// OTP_DEBUG.BLK2_W9: Otp debuger block2 data register9. +func (o *OTP_DEBUG_Type) SetBLK2_W9(value uint32) { + volatile.StoreUint32(&o.BLK2_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W9() uint32 { + return volatile.LoadUint32(&o.BLK2_W9.Reg) +} + +// OTP_DEBUG.BLK2_W10: Otp debuger block2 data register10. +func (o *OTP_DEBUG_Type) SetBLK2_W10(value uint32) { + volatile.StoreUint32(&o.BLK2_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W10() uint32 { + return volatile.LoadUint32(&o.BLK2_W10.Reg) +} + +// OTP_DEBUG.BLK2_W11: Otp debuger block2 data register11. +func (o *OTP_DEBUG_Type) SetBLK2_W11(value uint32) { + volatile.StoreUint32(&o.BLK2_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK2_W11() uint32 { + return volatile.LoadUint32(&o.BLK2_W11.Reg) +} + +// OTP_DEBUG.BLK3_W1: Otp debuger block3 data register1. +func (o *OTP_DEBUG_Type) SetBLK3_W1(value uint32) { + volatile.StoreUint32(&o.BLK3_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W1() uint32 { + return volatile.LoadUint32(&o.BLK3_W1.Reg) +} + +// OTP_DEBUG.BLK3_W2: Otp debuger block3 data register2. +func (o *OTP_DEBUG_Type) SetBLK3_W2(value uint32) { + volatile.StoreUint32(&o.BLK3_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W2() uint32 { + return volatile.LoadUint32(&o.BLK3_W2.Reg) +} + +// OTP_DEBUG.BLK3_W3: Otp debuger block3 data register3. +func (o *OTP_DEBUG_Type) SetBLK3_W3(value uint32) { + volatile.StoreUint32(&o.BLK3_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W3() uint32 { + return volatile.LoadUint32(&o.BLK3_W3.Reg) +} + +// OTP_DEBUG.BLK3_W4: Otp debuger block3 data register4. +func (o *OTP_DEBUG_Type) SetBLK3_W4(value uint32) { + volatile.StoreUint32(&o.BLK3_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W4() uint32 { + return volatile.LoadUint32(&o.BLK3_W4.Reg) +} + +// OTP_DEBUG.BLK3_W5: Otp debuger block3 data register5. +func (o *OTP_DEBUG_Type) SetBLK3_W5(value uint32) { + volatile.StoreUint32(&o.BLK3_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W5() uint32 { + return volatile.LoadUint32(&o.BLK3_W5.Reg) +} + +// OTP_DEBUG.BLK3_W6: Otp debuger block3 data register6. +func (o *OTP_DEBUG_Type) SetBLK3_W6(value uint32) { + volatile.StoreUint32(&o.BLK3_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W6() uint32 { + return volatile.LoadUint32(&o.BLK3_W6.Reg) +} + +// OTP_DEBUG.BLK3_W7: Otp debuger block3 data register7. +func (o *OTP_DEBUG_Type) SetBLK3_W7(value uint32) { + volatile.StoreUint32(&o.BLK3_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W7() uint32 { + return volatile.LoadUint32(&o.BLK3_W7.Reg) +} + +// OTP_DEBUG.BLK3_W8: Otp debuger block3 data register8. +func (o *OTP_DEBUG_Type) SetBLK3_W8(value uint32) { + volatile.StoreUint32(&o.BLK3_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W8() uint32 { + return volatile.LoadUint32(&o.BLK3_W8.Reg) +} + +// OTP_DEBUG.BLK3_W9: Otp debuger block3 data register9. +func (o *OTP_DEBUG_Type) SetBLK3_W9(value uint32) { + volatile.StoreUint32(&o.BLK3_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W9() uint32 { + return volatile.LoadUint32(&o.BLK3_W9.Reg) +} + +// OTP_DEBUG.BLK3_W10: Otp debuger block3 data register10. +func (o *OTP_DEBUG_Type) SetBLK3_W10(value uint32) { + volatile.StoreUint32(&o.BLK3_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W10() uint32 { + return volatile.LoadUint32(&o.BLK3_W10.Reg) +} + +// OTP_DEBUG.BLK3_W11: Otp debuger block3 data register11. +func (o *OTP_DEBUG_Type) SetBLK3_W11(value uint32) { + volatile.StoreUint32(&o.BLK3_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK3_W11() uint32 { + return volatile.LoadUint32(&o.BLK3_W11.Reg) +} + +// OTP_DEBUG.BLK4_W1: Otp debuger block4 data register1. +func (o *OTP_DEBUG_Type) SetBLK4_W1(value uint32) { + volatile.StoreUint32(&o.BLK4_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W1() uint32 { + return volatile.LoadUint32(&o.BLK4_W1.Reg) +} + +// OTP_DEBUG.BLK4_W2: Otp debuger block4 data register2. +func (o *OTP_DEBUG_Type) SetBLK4_W2(value uint32) { + volatile.StoreUint32(&o.BLK4_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W2() uint32 { + return volatile.LoadUint32(&o.BLK4_W2.Reg) +} + +// OTP_DEBUG.BLK4_W3: Otp debuger block4 data register3. +func (o *OTP_DEBUG_Type) SetBLK4_W3(value uint32) { + volatile.StoreUint32(&o.BLK4_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W3() uint32 { + return volatile.LoadUint32(&o.BLK4_W3.Reg) +} + +// OTP_DEBUG.BLK4_W4: Otp debuger block4 data register4. +func (o *OTP_DEBUG_Type) SetBLK4_W4(value uint32) { + volatile.StoreUint32(&o.BLK4_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W4() uint32 { + return volatile.LoadUint32(&o.BLK4_W4.Reg) +} + +// OTP_DEBUG.BLK4_W5: Otp debuger block4 data register5. +func (o *OTP_DEBUG_Type) SetBLK4_W5(value uint32) { + volatile.StoreUint32(&o.BLK4_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W5() uint32 { + return volatile.LoadUint32(&o.BLK4_W5.Reg) +} + +// OTP_DEBUG.BLK4_W6: Otp debuger block4 data register6. +func (o *OTP_DEBUG_Type) SetBLK4_W6(value uint32) { + volatile.StoreUint32(&o.BLK4_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W6() uint32 { + return volatile.LoadUint32(&o.BLK4_W6.Reg) +} + +// OTP_DEBUG.BLK4_W7: Otp debuger block4 data register7. +func (o *OTP_DEBUG_Type) SetBLK4_W7(value uint32) { + volatile.StoreUint32(&o.BLK4_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W7() uint32 { + return volatile.LoadUint32(&o.BLK4_W7.Reg) +} + +// OTP_DEBUG.BLK4_W8: Otp debuger block4 data register8. +func (o *OTP_DEBUG_Type) SetBLK4_W8(value uint32) { + volatile.StoreUint32(&o.BLK4_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W8() uint32 { + return volatile.LoadUint32(&o.BLK4_W8.Reg) +} + +// OTP_DEBUG.BLK4_W9: Otp debuger block4 data register9. +func (o *OTP_DEBUG_Type) SetBLK4_W9(value uint32) { + volatile.StoreUint32(&o.BLK4_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W9() uint32 { + return volatile.LoadUint32(&o.BLK4_W9.Reg) +} + +// OTP_DEBUG.BLK4_W10: Otp debuger block4 data registe10. +func (o *OTP_DEBUG_Type) SetBLK4_W10(value uint32) { + volatile.StoreUint32(&o.BLK4_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W10() uint32 { + return volatile.LoadUint32(&o.BLK4_W10.Reg) +} + +// OTP_DEBUG.BLK4_W11: Otp debuger block4 data register11. +func (o *OTP_DEBUG_Type) SetBLK4_W11(value uint32) { + volatile.StoreUint32(&o.BLK4_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK4_W11() uint32 { + return volatile.LoadUint32(&o.BLK4_W11.Reg) +} + +// OTP_DEBUG.BLK5_W1: Otp debuger block5 data register1. +func (o *OTP_DEBUG_Type) SetBLK5_W1(value uint32) { + volatile.StoreUint32(&o.BLK5_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W1() uint32 { + return volatile.LoadUint32(&o.BLK5_W1.Reg) +} + +// OTP_DEBUG.BLK5_W2: Otp debuger block5 data register2. +func (o *OTP_DEBUG_Type) SetBLK5_W2(value uint32) { + volatile.StoreUint32(&o.BLK5_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W2() uint32 { + return volatile.LoadUint32(&o.BLK5_W2.Reg) +} + +// OTP_DEBUG.BLK5_W3: Otp debuger block5 data register3. +func (o *OTP_DEBUG_Type) SetBLK5_W3(value uint32) { + volatile.StoreUint32(&o.BLK5_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W3() uint32 { + return volatile.LoadUint32(&o.BLK5_W3.Reg) +} + +// OTP_DEBUG.BLK5_W4: Otp debuger block5 data register4. +func (o *OTP_DEBUG_Type) SetBLK5_W4(value uint32) { + volatile.StoreUint32(&o.BLK5_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W4() uint32 { + return volatile.LoadUint32(&o.BLK5_W4.Reg) +} + +// OTP_DEBUG.BLK5_W5: Otp debuger block5 data register5. +func (o *OTP_DEBUG_Type) SetBLK5_W5(value uint32) { + volatile.StoreUint32(&o.BLK5_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W5() uint32 { + return volatile.LoadUint32(&o.BLK5_W5.Reg) +} + +// OTP_DEBUG.BLK5_W6: Otp debuger block5 data register6. +func (o *OTP_DEBUG_Type) SetBLK5_W6(value uint32) { + volatile.StoreUint32(&o.BLK5_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W6() uint32 { + return volatile.LoadUint32(&o.BLK5_W6.Reg) +} + +// OTP_DEBUG.BLK5_W7: Otp debuger block5 data register7. +func (o *OTP_DEBUG_Type) SetBLK5_W7(value uint32) { + volatile.StoreUint32(&o.BLK5_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W7() uint32 { + return volatile.LoadUint32(&o.BLK5_W7.Reg) +} + +// OTP_DEBUG.BLK5_W8: Otp debuger block5 data register8. +func (o *OTP_DEBUG_Type) SetBLK5_W8(value uint32) { + volatile.StoreUint32(&o.BLK5_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W8() uint32 { + return volatile.LoadUint32(&o.BLK5_W8.Reg) +} + +// OTP_DEBUG.BLK5_W9: Otp debuger block5 data register9. +func (o *OTP_DEBUG_Type) SetBLK5_W9(value uint32) { + volatile.StoreUint32(&o.BLK5_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W9() uint32 { + return volatile.LoadUint32(&o.BLK5_W9.Reg) +} + +// OTP_DEBUG.BLK5_W10: Otp debuger block5 data register10. +func (o *OTP_DEBUG_Type) SetBLK5_W10(value uint32) { + volatile.StoreUint32(&o.BLK5_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W10() uint32 { + return volatile.LoadUint32(&o.BLK5_W10.Reg) +} + +// OTP_DEBUG.BLK5_W11: Otp debuger block5 data register11. +func (o *OTP_DEBUG_Type) SetBLK5_W11(value uint32) { + volatile.StoreUint32(&o.BLK5_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK5_W11() uint32 { + return volatile.LoadUint32(&o.BLK5_W11.Reg) +} + +// OTP_DEBUG.BLK6_W1: Otp debuger block6 data register1. +func (o *OTP_DEBUG_Type) SetBLK6_W1(value uint32) { + volatile.StoreUint32(&o.BLK6_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W1() uint32 { + return volatile.LoadUint32(&o.BLK6_W1.Reg) +} + +// OTP_DEBUG.BLK6_W2: Otp debuger block6 data register2. +func (o *OTP_DEBUG_Type) SetBLK6_W2(value uint32) { + volatile.StoreUint32(&o.BLK6_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W2() uint32 { + return volatile.LoadUint32(&o.BLK6_W2.Reg) +} + +// OTP_DEBUG.BLK6_W3: Otp debuger block6 data register3. +func (o *OTP_DEBUG_Type) SetBLK6_W3(value uint32) { + volatile.StoreUint32(&o.BLK6_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W3() uint32 { + return volatile.LoadUint32(&o.BLK6_W3.Reg) +} + +// OTP_DEBUG.BLK6_W4: Otp debuger block6 data register4. +func (o *OTP_DEBUG_Type) SetBLK6_W4(value uint32) { + volatile.StoreUint32(&o.BLK6_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W4() uint32 { + return volatile.LoadUint32(&o.BLK6_W4.Reg) +} + +// OTP_DEBUG.BLK6_W5: Otp debuger block6 data register5. +func (o *OTP_DEBUG_Type) SetBLK6_W5(value uint32) { + volatile.StoreUint32(&o.BLK6_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W5() uint32 { + return volatile.LoadUint32(&o.BLK6_W5.Reg) +} + +// OTP_DEBUG.BLK6_W6: Otp debuger block6 data register6. +func (o *OTP_DEBUG_Type) SetBLK6_W6(value uint32) { + volatile.StoreUint32(&o.BLK6_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W6() uint32 { + return volatile.LoadUint32(&o.BLK6_W6.Reg) +} + +// OTP_DEBUG.BLK6_W7: Otp debuger block6 data register7. +func (o *OTP_DEBUG_Type) SetBLK6_W7(value uint32) { + volatile.StoreUint32(&o.BLK6_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W7() uint32 { + return volatile.LoadUint32(&o.BLK6_W7.Reg) +} + +// OTP_DEBUG.BLK6_W8: Otp debuger block6 data register8. +func (o *OTP_DEBUG_Type) SetBLK6_W8(value uint32) { + volatile.StoreUint32(&o.BLK6_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W8() uint32 { + return volatile.LoadUint32(&o.BLK6_W8.Reg) +} + +// OTP_DEBUG.BLK6_W9: Otp debuger block6 data register9. +func (o *OTP_DEBUG_Type) SetBLK6_W9(value uint32) { + volatile.StoreUint32(&o.BLK6_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W9() uint32 { + return volatile.LoadUint32(&o.BLK6_W9.Reg) +} + +// OTP_DEBUG.BLK6_W10: Otp debuger block6 data register10. +func (o *OTP_DEBUG_Type) SetBLK6_W10(value uint32) { + volatile.StoreUint32(&o.BLK6_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W10() uint32 { + return volatile.LoadUint32(&o.BLK6_W10.Reg) +} + +// OTP_DEBUG.BLK6_W11: Otp debuger block6 data register11. +func (o *OTP_DEBUG_Type) SetBLK6_W11(value uint32) { + volatile.StoreUint32(&o.BLK6_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK6_W11() uint32 { + return volatile.LoadUint32(&o.BLK6_W11.Reg) +} + +// OTP_DEBUG.BLK7_W1: Otp debuger block7 data register1. +func (o *OTP_DEBUG_Type) SetBLK7_W1(value uint32) { + volatile.StoreUint32(&o.BLK7_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W1() uint32 { + return volatile.LoadUint32(&o.BLK7_W1.Reg) +} + +// OTP_DEBUG.BLK7_W2: Otp debuger block7 data register2. +func (o *OTP_DEBUG_Type) SetBLK7_W2(value uint32) { + volatile.StoreUint32(&o.BLK7_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W2() uint32 { + return volatile.LoadUint32(&o.BLK7_W2.Reg) +} + +// OTP_DEBUG.BLK7_W3: Otp debuger block7 data register3. +func (o *OTP_DEBUG_Type) SetBLK7_W3(value uint32) { + volatile.StoreUint32(&o.BLK7_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W3() uint32 { + return volatile.LoadUint32(&o.BLK7_W3.Reg) +} + +// OTP_DEBUG.BLK7_W4: Otp debuger block7 data register4. +func (o *OTP_DEBUG_Type) SetBLK7_W4(value uint32) { + volatile.StoreUint32(&o.BLK7_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W4() uint32 { + return volatile.LoadUint32(&o.BLK7_W4.Reg) +} + +// OTP_DEBUG.BLK7_W5: Otp debuger block7 data register5. +func (o *OTP_DEBUG_Type) SetBLK7_W5(value uint32) { + volatile.StoreUint32(&o.BLK7_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W5() uint32 { + return volatile.LoadUint32(&o.BLK7_W5.Reg) +} + +// OTP_DEBUG.BLK7_W6: Otp debuger block7 data register6. +func (o *OTP_DEBUG_Type) SetBLK7_W6(value uint32) { + volatile.StoreUint32(&o.BLK7_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W6() uint32 { + return volatile.LoadUint32(&o.BLK7_W6.Reg) +} + +// OTP_DEBUG.BLK7_W7: Otp debuger block7 data register7. +func (o *OTP_DEBUG_Type) SetBLK7_W7(value uint32) { + volatile.StoreUint32(&o.BLK7_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W7() uint32 { + return volatile.LoadUint32(&o.BLK7_W7.Reg) +} + +// OTP_DEBUG.BLK7_W8: Otp debuger block7 data register8. +func (o *OTP_DEBUG_Type) SetBLK7_W8(value uint32) { + volatile.StoreUint32(&o.BLK7_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W8() uint32 { + return volatile.LoadUint32(&o.BLK7_W8.Reg) +} + +// OTP_DEBUG.BLK7_W9: Otp debuger block7 data register9. +func (o *OTP_DEBUG_Type) SetBLK7_W9(value uint32) { + volatile.StoreUint32(&o.BLK7_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W9() uint32 { + return volatile.LoadUint32(&o.BLK7_W9.Reg) +} + +// OTP_DEBUG.BLK7_W10: Otp debuger block7 data register10. +func (o *OTP_DEBUG_Type) SetBLK7_W10(value uint32) { + volatile.StoreUint32(&o.BLK7_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W10() uint32 { + return volatile.LoadUint32(&o.BLK7_W10.Reg) +} + +// OTP_DEBUG.BLK7_W11: Otp debuger block7 data register11. +func (o *OTP_DEBUG_Type) SetBLK7_W11(value uint32) { + volatile.StoreUint32(&o.BLK7_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK7_W11() uint32 { + return volatile.LoadUint32(&o.BLK7_W11.Reg) +} + +// OTP_DEBUG.BLK8_W1: Otp debuger block8 data register1. +func (o *OTP_DEBUG_Type) SetBLK8_W1(value uint32) { + volatile.StoreUint32(&o.BLK8_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W1() uint32 { + return volatile.LoadUint32(&o.BLK8_W1.Reg) +} + +// OTP_DEBUG.BLK8_W2: Otp debuger block8 data register2. +func (o *OTP_DEBUG_Type) SetBLK8_W2(value uint32) { + volatile.StoreUint32(&o.BLK8_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W2() uint32 { + return volatile.LoadUint32(&o.BLK8_W2.Reg) +} + +// OTP_DEBUG.BLK8_W3: Otp debuger block8 data register3. +func (o *OTP_DEBUG_Type) SetBLK8_W3(value uint32) { + volatile.StoreUint32(&o.BLK8_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W3() uint32 { + return volatile.LoadUint32(&o.BLK8_W3.Reg) +} + +// OTP_DEBUG.BLK8_W4: Otp debuger block8 data register4. +func (o *OTP_DEBUG_Type) SetBLK8_W4(value uint32) { + volatile.StoreUint32(&o.BLK8_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W4() uint32 { + return volatile.LoadUint32(&o.BLK8_W4.Reg) +} + +// OTP_DEBUG.BLK8_W5: Otp debuger block8 data register5. +func (o *OTP_DEBUG_Type) SetBLK8_W5(value uint32) { + volatile.StoreUint32(&o.BLK8_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W5() uint32 { + return volatile.LoadUint32(&o.BLK8_W5.Reg) +} + +// OTP_DEBUG.BLK8_W6: Otp debuger block8 data register6. +func (o *OTP_DEBUG_Type) SetBLK8_W6(value uint32) { + volatile.StoreUint32(&o.BLK8_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W6() uint32 { + return volatile.LoadUint32(&o.BLK8_W6.Reg) +} + +// OTP_DEBUG.BLK8_W7: Otp debuger block8 data register7. +func (o *OTP_DEBUG_Type) SetBLK8_W7(value uint32) { + volatile.StoreUint32(&o.BLK8_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W7() uint32 { + return volatile.LoadUint32(&o.BLK8_W7.Reg) +} + +// OTP_DEBUG.BLK8_W8: Otp debuger block8 data register8. +func (o *OTP_DEBUG_Type) SetBLK8_W8(value uint32) { + volatile.StoreUint32(&o.BLK8_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W8() uint32 { + return volatile.LoadUint32(&o.BLK8_W8.Reg) +} + +// OTP_DEBUG.BLK8_W9: Otp debuger block8 data register9. +func (o *OTP_DEBUG_Type) SetBLK8_W9(value uint32) { + volatile.StoreUint32(&o.BLK8_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W9() uint32 { + return volatile.LoadUint32(&o.BLK8_W9.Reg) +} + +// OTP_DEBUG.BLK8_W10: Otp debuger block8 data register10. +func (o *OTP_DEBUG_Type) SetBLK8_W10(value uint32) { + volatile.StoreUint32(&o.BLK8_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W10() uint32 { + return volatile.LoadUint32(&o.BLK8_W10.Reg) +} + +// OTP_DEBUG.BLK8_W11: Otp debuger block8 data register11. +func (o *OTP_DEBUG_Type) SetBLK8_W11(value uint32) { + volatile.StoreUint32(&o.BLK8_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK8_W11() uint32 { + return volatile.LoadUint32(&o.BLK8_W11.Reg) +} + +// OTP_DEBUG.BLK9_W1: Otp debuger block9 data register1. +func (o *OTP_DEBUG_Type) SetBLK9_W1(value uint32) { + volatile.StoreUint32(&o.BLK9_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W1() uint32 { + return volatile.LoadUint32(&o.BLK9_W1.Reg) +} + +// OTP_DEBUG.BLK9_W2: Otp debuger block9 data register2. +func (o *OTP_DEBUG_Type) SetBLK9_W2(value uint32) { + volatile.StoreUint32(&o.BLK9_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W2() uint32 { + return volatile.LoadUint32(&o.BLK9_W2.Reg) +} + +// OTP_DEBUG.BLK9_W3: Otp debuger block9 data register3. +func (o *OTP_DEBUG_Type) SetBLK9_W3(value uint32) { + volatile.StoreUint32(&o.BLK9_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W3() uint32 { + return volatile.LoadUint32(&o.BLK9_W3.Reg) +} + +// OTP_DEBUG.BLK9_W4: Otp debuger block9 data register4. +func (o *OTP_DEBUG_Type) SetBLK9_W4(value uint32) { + volatile.StoreUint32(&o.BLK9_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W4() uint32 { + return volatile.LoadUint32(&o.BLK9_W4.Reg) +} + +// OTP_DEBUG.BLK9_W5: Otp debuger block9 data register5. +func (o *OTP_DEBUG_Type) SetBLK9_W5(value uint32) { + volatile.StoreUint32(&o.BLK9_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W5() uint32 { + return volatile.LoadUint32(&o.BLK9_W5.Reg) +} + +// OTP_DEBUG.BLK9_W6: Otp debuger block9 data register6. +func (o *OTP_DEBUG_Type) SetBLK9_W6(value uint32) { + volatile.StoreUint32(&o.BLK9_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W6() uint32 { + return volatile.LoadUint32(&o.BLK9_W6.Reg) +} + +// OTP_DEBUG.BLK9_W7: Otp debuger block9 data register7. +func (o *OTP_DEBUG_Type) SetBLK9_W7(value uint32) { + volatile.StoreUint32(&o.BLK9_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W7() uint32 { + return volatile.LoadUint32(&o.BLK9_W7.Reg) +} + +// OTP_DEBUG.BLK9_W8: Otp debuger block9 data register8. +func (o *OTP_DEBUG_Type) SetBLK9_W8(value uint32) { + volatile.StoreUint32(&o.BLK9_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W8() uint32 { + return volatile.LoadUint32(&o.BLK9_W8.Reg) +} + +// OTP_DEBUG.BLK9_W9: Otp debuger block9 data register9. +func (o *OTP_DEBUG_Type) SetBLK9_W9(value uint32) { + volatile.StoreUint32(&o.BLK9_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W9() uint32 { + return volatile.LoadUint32(&o.BLK9_W9.Reg) +} + +// OTP_DEBUG.BLK9_W10: Otp debuger block9 data register10. +func (o *OTP_DEBUG_Type) SetBLK9_W10(value uint32) { + volatile.StoreUint32(&o.BLK9_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W10() uint32 { + return volatile.LoadUint32(&o.BLK9_W10.Reg) +} + +// OTP_DEBUG.BLK9_W11: Otp debuger block9 data register11. +func (o *OTP_DEBUG_Type) SetBLK9_W11(value uint32) { + volatile.StoreUint32(&o.BLK9_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK9_W11() uint32 { + return volatile.LoadUint32(&o.BLK9_W11.Reg) +} + +// OTP_DEBUG.BLK10_W1: Otp debuger block10 data register1. +func (o *OTP_DEBUG_Type) SetBLK10_W1(value uint32) { + volatile.StoreUint32(&o.BLK10_W1.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W1() uint32 { + return volatile.LoadUint32(&o.BLK10_W1.Reg) +} + +// OTP_DEBUG.BLK10_W2: Otp debuger block10 data register2. +func (o *OTP_DEBUG_Type) SetBLK10_W2(value uint32) { + volatile.StoreUint32(&o.BLK10_W2.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W2() uint32 { + return volatile.LoadUint32(&o.BLK10_W2.Reg) +} + +// OTP_DEBUG.BLK10_W3: Otp debuger block10 data register3. +func (o *OTP_DEBUG_Type) SetBLK10_W3(value uint32) { + volatile.StoreUint32(&o.BLK10_W3.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W3() uint32 { + return volatile.LoadUint32(&o.BLK10_W3.Reg) +} + +// OTP_DEBUG.BLK10_W4: Otp debuger block10 data register4. +func (o *OTP_DEBUG_Type) SetBLK10_W4(value uint32) { + volatile.StoreUint32(&o.BLK10_W4.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W4() uint32 { + return volatile.LoadUint32(&o.BLK10_W4.Reg) +} + +// OTP_DEBUG.BLK10_W5: Otp debuger block10 data register5. +func (o *OTP_DEBUG_Type) SetBLK10_W5(value uint32) { + volatile.StoreUint32(&o.BLK10_W5.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W5() uint32 { + return volatile.LoadUint32(&o.BLK10_W5.Reg) +} + +// OTP_DEBUG.BLK10_W6: Otp debuger block10 data register6. +func (o *OTP_DEBUG_Type) SetBLK10_W6(value uint32) { + volatile.StoreUint32(&o.BLK10_W6.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W6() uint32 { + return volatile.LoadUint32(&o.BLK10_W6.Reg) +} + +// OTP_DEBUG.BLK10_W7: Otp debuger block10 data register7. +func (o *OTP_DEBUG_Type) SetBLK10_W7(value uint32) { + volatile.StoreUint32(&o.BLK10_W7.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W7() uint32 { + return volatile.LoadUint32(&o.BLK10_W7.Reg) +} + +// OTP_DEBUG.BLK10_W8: Otp debuger block10 data register8. +func (o *OTP_DEBUG_Type) SetBLK10_W8(value uint32) { + volatile.StoreUint32(&o.BLK10_W8.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W8() uint32 { + return volatile.LoadUint32(&o.BLK10_W8.Reg) +} + +// OTP_DEBUG.BLK10_W9: Otp debuger block10 data register9. +func (o *OTP_DEBUG_Type) SetBLK10_W9(value uint32) { + volatile.StoreUint32(&o.BLK10_W9.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W9() uint32 { + return volatile.LoadUint32(&o.BLK10_W9.Reg) +} + +// OTP_DEBUG.BLK10_W10: Otp debuger block10 data register10. +func (o *OTP_DEBUG_Type) SetBLK10_W10(value uint32) { + volatile.StoreUint32(&o.BLK10_W10.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W10() uint32 { + return volatile.LoadUint32(&o.BLK10_W10.Reg) +} + +// OTP_DEBUG.BLK10_W11: Otp debuger block10 data register11. +func (o *OTP_DEBUG_Type) SetBLK10_W11(value uint32) { + volatile.StoreUint32(&o.BLK10_W11.Reg, value) +} +func (o *OTP_DEBUG_Type) GetBLK10_W11() uint32 { + return volatile.LoadUint32(&o.BLK10_W11.Reg) +} + +// OTP_DEBUG.CLK: Otp debuger clk_en configuration register. +func (o *OTP_DEBUG_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *OTP_DEBUG_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} + +// OTP_DEBUG.APB2OTP_EN: Otp_debuger apb2otp enable configuration register. +func (o *OTP_DEBUG_Type) SetAPB2OTP_EN(value uint32) { + volatile.StoreUint32(&o.APB2OTP_EN.Reg, volatile.LoadUint32(&o.APB2OTP_EN.Reg)&^(0x1)|value) +} +func (o *OTP_DEBUG_Type) GetAPB2OTP_EN() uint32 { + return volatile.LoadUint32(&o.APB2OTP_EN.Reg) & 0x1 +} + +// OTP_DEBUG.DATE: eFuse version register. +func (o *OTP_DEBUG_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *OTP_DEBUG_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Parallel IO Controller +type PARL_IO_Type struct { + RX_MODE_CFG volatile.Register32 // 0x0 + RX_DATA_CFG volatile.Register32 // 0x4 + RX_GENRL_CFG volatile.Register32 // 0x8 + RX_START_CFG volatile.Register32 // 0xC + TX_DATA_CFG volatile.Register32 // 0x10 + TX_START_CFG volatile.Register32 // 0x14 + TX_GENRL_CFG volatile.Register32 // 0x18 + FIFO_CFG volatile.Register32 // 0x1C + REG_UPDATE volatile.Register32 // 0x20 + ST volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_RAW volatile.Register32 // 0x2C + INT_ST volatile.Register32 // 0x30 + INT_CLR volatile.Register32 // 0x34 + RX_ST0 volatile.Register32 // 0x38 + RX_ST1 volatile.Register32 // 0x3C + TX_ST0 volatile.Register32 // 0x40 + RX_CLK_CFG volatile.Register32 // 0x44 + TX_CLK_CFG volatile.Register32 // 0x48 + _ [212]byte + CLK volatile.Register32 // 0x120 + _ [728]byte + VERSION volatile.Register32 // 0x3FC +} + +// PARL_IO.RX_MODE_CFG: Parallel RX Sampling mode configuration register. +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_EXT_EN_SEL(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x1e00000)|value<<21) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_EXT_EN_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x1e00000) >> 21 +} +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_SW_EN(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x2000000)|value<<25) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_SW_EN() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x2000000) >> 25 +} +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_EXT_EN_INV(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x4000000)|value<<26) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_EXT_EN_INV() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x4000000) >> 26 +} +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_PULSE_SUBMODE_SEL(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x38000000)|value<<27) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_PULSE_SUBMODE_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x38000000) >> 27 +} +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_SMP_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0xc0000000)|value<<30) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_SMP_MODE_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0xc0000000) >> 30 +} + +// PARL_IO.RX_DATA_CFG: Parallel RX data configuration register. +func (o *PARL_IO_Type) SetRX_DATA_CFG_RX_BITLEN(value uint32) { + volatile.StoreUint32(&o.RX_DATA_CFG.Reg, volatile.LoadUint32(&o.RX_DATA_CFG.Reg)&^(0xffffe00)|value<<9) +} +func (o *PARL_IO_Type) GetRX_DATA_CFG_RX_BITLEN() uint32 { + return (volatile.LoadUint32(&o.RX_DATA_CFG.Reg) & 0xffffe00) >> 9 +} +func (o *PARL_IO_Type) SetRX_DATA_CFG_RX_DATA_ORDER_INV(value uint32) { + volatile.StoreUint32(&o.RX_DATA_CFG.Reg, volatile.LoadUint32(&o.RX_DATA_CFG.Reg)&^(0x10000000)|value<<28) +} +func (o *PARL_IO_Type) GetRX_DATA_CFG_RX_DATA_ORDER_INV() uint32 { + return (volatile.LoadUint32(&o.RX_DATA_CFG.Reg) & 0x10000000) >> 28 +} +func (o *PARL_IO_Type) SetRX_DATA_CFG_RX_BUS_WID_SEL(value uint32) { + volatile.StoreUint32(&o.RX_DATA_CFG.Reg, volatile.LoadUint32(&o.RX_DATA_CFG.Reg)&^(0xe0000000)|value<<29) +} +func (o *PARL_IO_Type) GetRX_DATA_CFG_RX_BUS_WID_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_DATA_CFG.Reg) & 0xe0000000) >> 29 +} + +// PARL_IO.RX_GENRL_CFG: Parallel RX general configuration register. +func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_GATING_EN(value uint32) { + volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_GATING_EN() uint32 { + return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x1000) >> 12 +} +func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x1fffe000) >> 13 +} +func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x20000000)|value<<29) +} +func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_TIMEOUT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x20000000) >> 29 +} +func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_EOF_GEN_SEL(value uint32) { + volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_EOF_GEN_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x40000000) >> 30 +} + +// PARL_IO.RX_START_CFG: Parallel RX Start configuration register. +func (o *PARL_IO_Type) SetRX_START_CFG_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_START_CFG.Reg, volatile.LoadUint32(&o.RX_START_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetRX_START_CFG_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_START_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.TX_DATA_CFG: Parallel TX data configuration register. +func (o *PARL_IO_Type) SetTX_DATA_CFG_TX_BITLEN(value uint32) { + volatile.StoreUint32(&o.TX_DATA_CFG.Reg, volatile.LoadUint32(&o.TX_DATA_CFG.Reg)&^(0xffffe00)|value<<9) +} +func (o *PARL_IO_Type) GetTX_DATA_CFG_TX_BITLEN() uint32 { + return (volatile.LoadUint32(&o.TX_DATA_CFG.Reg) & 0xffffe00) >> 9 +} +func (o *PARL_IO_Type) SetTX_DATA_CFG_TX_DATA_ORDER_INV(value uint32) { + volatile.StoreUint32(&o.TX_DATA_CFG.Reg, volatile.LoadUint32(&o.TX_DATA_CFG.Reg)&^(0x10000000)|value<<28) +} +func (o *PARL_IO_Type) GetTX_DATA_CFG_TX_DATA_ORDER_INV() uint32 { + return (volatile.LoadUint32(&o.TX_DATA_CFG.Reg) & 0x10000000) >> 28 +} +func (o *PARL_IO_Type) SetTX_DATA_CFG_TX_BUS_WID_SEL(value uint32) { + volatile.StoreUint32(&o.TX_DATA_CFG.Reg, volatile.LoadUint32(&o.TX_DATA_CFG.Reg)&^(0xe0000000)|value<<29) +} +func (o *PARL_IO_Type) GetTX_DATA_CFG_TX_BUS_WID_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_DATA_CFG.Reg) & 0xe0000000) >> 29 +} + +// PARL_IO.TX_START_CFG: Parallel TX Start configuration register. +func (o *PARL_IO_Type) SetTX_START_CFG_TX_START(value uint32) { + volatile.StoreUint32(&o.TX_START_CFG.Reg, volatile.LoadUint32(&o.TX_START_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetTX_START_CFG_TX_START() uint32 { + return (volatile.LoadUint32(&o.TX_START_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.TX_GENRL_CFG: Parallel TX general configuration register. +func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_IDLE_VALUE(value uint32) { + volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x3fffc000)|value<<14) +} +func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_IDLE_VALUE() uint32 { + return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x3fffc000) >> 14 +} +func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_GATING_EN(value uint32) { + volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_GATING_EN() uint32 { + return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x40000000) >> 30 +} +func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_VALID_OUTPUT_EN(value uint32) { + volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_VALID_OUTPUT_EN() uint32 { + return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.FIFO_CFG: Parallel IO FIFO configuration register. +func (o *PARL_IO_Type) SetFIFO_CFG_TX_FIFO_SRST(value uint32) { + volatile.StoreUint32(&o.FIFO_CFG.Reg, volatile.LoadUint32(&o.FIFO_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetFIFO_CFG_TX_FIFO_SRST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CFG.Reg) & 0x40000000) >> 30 +} +func (o *PARL_IO_Type) SetFIFO_CFG_RX_FIFO_SRST(value uint32) { + volatile.StoreUint32(&o.FIFO_CFG.Reg, volatile.LoadUint32(&o.FIFO_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetFIFO_CFG_RX_FIFO_SRST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.REG_UPDATE: Parallel IO FIFO configuration register. +func (o *PARL_IO_Type) SetREG_UPDATE_RX_REG_UPDATE(value uint32) { + volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetREG_UPDATE_RX_REG_UPDATE() uint32 { + return (volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.ST: Parallel IO module status register0. +func (o *PARL_IO_Type) SetST_TX_READY(value uint32) { + volatile.StoreUint32(&o.ST.Reg, volatile.LoadUint32(&o.ST.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetST_TX_READY() uint32 { + return (volatile.LoadUint32(&o.ST.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.INT_ENA: Parallel IO interrupt enable singal configuration register. +func (o *PARL_IO_Type) SetINT_ENA_TX_FIFO_REMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_ENA_TX_FIFO_REMPTY_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_ENA_RX_FIFO_WOVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_ENA_RX_FIFO_WOVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_ENA_TX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_ENA_TX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// PARL_IO.INT_RAW: Parallel IO interrupt raw singal status register. +func (o *PARL_IO_Type) SetINT_RAW_TX_FIFO_REMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_RAW_TX_FIFO_REMPTY_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_RAW_RX_FIFO_WOVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_RAW_RX_FIFO_WOVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_RAW_TX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_RAW_TX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// PARL_IO.INT_ST: Parallel IO interrupt singal status register. +func (o *PARL_IO_Type) SetINT_ST_TX_FIFO_REMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_ST_TX_FIFO_REMPTY_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_ST_RX_FIFO_WOVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_ST_RX_FIFO_WOVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_ST_TX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_ST_TX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// PARL_IO.INT_CLR: Parallel IO interrupt clear singal configuration register. +func (o *PARL_IO_Type) SetINT_CLR_TX_FIFO_REMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_CLR_TX_FIFO_REMPTY_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_CLR_RX_FIFO_WOVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_CLR_RX_FIFO_WOVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_CLR_TX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_CLR_TX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// PARL_IO.RX_ST0: Parallel IO RX status register0 +func (o *PARL_IO_Type) SetRX_ST0_RX_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ST0.Reg, volatile.LoadUint32(&o.RX_ST0.Reg)&^(0x1e00)|value<<9) +} +func (o *PARL_IO_Type) GetRX_ST0_RX_CNT() uint32 { + return (volatile.LoadUint32(&o.RX_ST0.Reg) & 0x1e00) >> 9 +} +func (o *PARL_IO_Type) SetRX_ST0_RX_FIFO_WR_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ST0.Reg, volatile.LoadUint32(&o.RX_ST0.Reg)&^(0xffffe000)|value<<13) +} +func (o *PARL_IO_Type) GetRX_ST0_RX_FIFO_WR_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.RX_ST0.Reg) & 0xffffe000) >> 13 +} + +// PARL_IO.RX_ST1: Parallel IO RX status register1 +func (o *PARL_IO_Type) SetRX_ST1_RX_FIFO_RD_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ST1.Reg, volatile.LoadUint32(&o.RX_ST1.Reg)&^(0xffffe000)|value<<13) +} +func (o *PARL_IO_Type) GetRX_ST1_RX_FIFO_RD_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.RX_ST1.Reg) & 0xffffe000) >> 13 +} + +// PARL_IO.TX_ST0: Parallel IO TX status register0 +func (o *PARL_IO_Type) SetTX_ST0_TX_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ST0.Reg, volatile.LoadUint32(&o.TX_ST0.Reg)&^(0x1fc0)|value<<6) +} +func (o *PARL_IO_Type) GetTX_ST0_TX_CNT() uint32 { + return (volatile.LoadUint32(&o.TX_ST0.Reg) & 0x1fc0) >> 6 +} +func (o *PARL_IO_Type) SetTX_ST0_TX_FIFO_RD_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ST0.Reg, volatile.LoadUint32(&o.TX_ST0.Reg)&^(0xffffe000)|value<<13) +} +func (o *PARL_IO_Type) GetTX_ST0_TX_FIFO_RD_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.TX_ST0.Reg) & 0xffffe000) >> 13 +} + +// PARL_IO.RX_CLK_CFG: Parallel IO RX clk configuration register +func (o *PARL_IO_Type) SetRX_CLK_CFG_RX_CLK_I_INV(value uint32) { + volatile.StoreUint32(&o.RX_CLK_CFG.Reg, volatile.LoadUint32(&o.RX_CLK_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetRX_CLK_CFG_RX_CLK_I_INV() uint32 { + return (volatile.LoadUint32(&o.RX_CLK_CFG.Reg) & 0x40000000) >> 30 +} +func (o *PARL_IO_Type) SetRX_CLK_CFG_RX_CLK_O_INV(value uint32) { + volatile.StoreUint32(&o.RX_CLK_CFG.Reg, volatile.LoadUint32(&o.RX_CLK_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetRX_CLK_CFG_RX_CLK_O_INV() uint32 { + return (volatile.LoadUint32(&o.RX_CLK_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.TX_CLK_CFG: Parallel IO TX clk configuration register +func (o *PARL_IO_Type) SetTX_CLK_CFG_TX_CLK_I_INV(value uint32) { + volatile.StoreUint32(&o.TX_CLK_CFG.Reg, volatile.LoadUint32(&o.TX_CLK_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetTX_CLK_CFG_TX_CLK_I_INV() uint32 { + return (volatile.LoadUint32(&o.TX_CLK_CFG.Reg) & 0x40000000) >> 30 +} +func (o *PARL_IO_Type) SetTX_CLK_CFG_TX_CLK_O_INV(value uint32) { + volatile.StoreUint32(&o.TX_CLK_CFG.Reg, volatile.LoadUint32(&o.TX_CLK_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetTX_CLK_CFG_TX_CLK_O_INV() uint32 { + return (volatile.LoadUint32(&o.TX_CLK_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.CLK: Parallel IO clk configuration register +func (o *PARL_IO_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.VERSION: Version register. +func (o *PARL_IO_Type) SetVERSION_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *PARL_IO_Type) GetVERSION_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// PAU Peripheral +type PAU_Type struct { + REGDMA_CONF volatile.Register32 // 0x0 + REGDMA_CLK_CONF volatile.Register32 // 0x4 + REGDMA_ETM_CTRL volatile.Register32 // 0x8 + REGDMA_LINK_0_ADDR volatile.Register32 // 0xC + REGDMA_LINK_1_ADDR volatile.Register32 // 0x10 + REGDMA_LINK_2_ADDR volatile.Register32 // 0x14 + REGDMA_LINK_3_ADDR volatile.Register32 // 0x18 + REGDMA_LINK_MAC_ADDR volatile.Register32 // 0x1C + REGDMA_CURRENT_LINK_ADDR volatile.Register32 // 0x20 + REGDMA_BACKUP_ADDR volatile.Register32 // 0x24 + REGDMA_MEM_ADDR volatile.Register32 // 0x28 + REGDMA_BKP_CONF volatile.Register32 // 0x2C + RETENTION_LINK_BASE volatile.Register32 // 0x30 + RETENTION_CFG volatile.Register32 // 0x34 + INT_ENA volatile.Register32 // 0x38 + INT_RAW volatile.Register32 // 0x3C + INT_CLR volatile.Register32 // 0x40 + INT_ST volatile.Register32 // 0x44 + _ [948]byte + DATE volatile.Register32 // 0x3FC +} + +// PAU.REGDMA_CONF: Peri backup control register +func (o *PAU_Type) SetREGDMA_CONF_FLOW_ERR(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x7)|value) +} +func (o *PAU_Type) GetREGDMA_CONF_FLOW_ERR() uint32 { + return volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x7 +} +func (o *PAU_Type) SetREGDMA_CONF_START(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PAU_Type) GetREGDMA_CONF_START() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x8) >> 3 +} +func (o *PAU_Type) SetREGDMA_CONF_TO_MEM(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x10)|value<<4) +} +func (o *PAU_Type) GetREGDMA_CONF_TO_MEM() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x10) >> 4 +} +func (o *PAU_Type) SetREGDMA_CONF_LINK_SEL(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x60)|value<<5) +} +func (o *PAU_Type) GetREGDMA_CONF_LINK_SEL() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x60) >> 5 +} +func (o *PAU_Type) SetREGDMA_CONF_START_MAC(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x80)|value<<7) +} +func (o *PAU_Type) GetREGDMA_CONF_START_MAC() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x80) >> 7 +} +func (o *PAU_Type) SetREGDMA_CONF_TO_MEM_MAC(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x100)|value<<8) +} +func (o *PAU_Type) GetREGDMA_CONF_TO_MEM_MAC() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x100) >> 8 +} +func (o *PAU_Type) SetREGDMA_CONF_SEL_MAC(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x200)|value<<9) +} +func (o *PAU_Type) GetREGDMA_CONF_SEL_MAC() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x200) >> 9 +} + +// PAU.REGDMA_CLK_CONF: Clock control register +func (o *PAU_Type) SetREGDMA_CLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGDMA_CLK_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetREGDMA_CLK_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.REGDMA_CLK_CONF.Reg) & 0x1 +} + +// PAU.REGDMA_ETM_CTRL: ETM start ctrl reg +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_0(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_0() uint32 { + return volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x1 +} +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_1(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_1() uint32 { + return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x2) >> 1 +} +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_2(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_2() uint32 { + return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x4) >> 2 +} +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_3(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_3() uint32 { + return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x8) >> 3 +} + +// PAU.REGDMA_LINK_0_ADDR: link_0_addr +func (o *PAU_Type) SetREGDMA_LINK_0_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_0_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_0_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_0_ADDR.Reg) +} + +// PAU.REGDMA_LINK_1_ADDR: Link_1_addr +func (o *PAU_Type) SetREGDMA_LINK_1_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_1_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_1_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_1_ADDR.Reg) +} + +// PAU.REGDMA_LINK_2_ADDR: Link_2_addr +func (o *PAU_Type) SetREGDMA_LINK_2_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_2_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_2_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_2_ADDR.Reg) +} + +// PAU.REGDMA_LINK_3_ADDR: Link_3_addr +func (o *PAU_Type) SetREGDMA_LINK_3_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_3_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_3_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_3_ADDR.Reg) +} + +// PAU.REGDMA_LINK_MAC_ADDR: Link_mac_addr +func (o *PAU_Type) SetREGDMA_LINK_MAC_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_MAC_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_MAC_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_MAC_ADDR.Reg) +} + +// PAU.REGDMA_CURRENT_LINK_ADDR: current link addr +func (o *PAU_Type) SetREGDMA_CURRENT_LINK_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_CURRENT_LINK_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_CURRENT_LINK_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_CURRENT_LINK_ADDR.Reg) +} + +// PAU.REGDMA_BACKUP_ADDR: Backup addr +func (o *PAU_Type) SetREGDMA_BACKUP_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_BACKUP_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_BACKUP_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_BACKUP_ADDR.Reg) +} + +// PAU.REGDMA_MEM_ADDR: mem addr +func (o *PAU_Type) SetREGDMA_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_MEM_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_MEM_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_MEM_ADDR.Reg) +} + +// PAU.REGDMA_BKP_CONF: backup config +func (o *PAU_Type) SetREGDMA_BKP_CONF_READ_INTERVAL(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x7f)|value) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_READ_INTERVAL() uint32 { + return volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x7f +} +func (o *PAU_Type) SetREGDMA_BKP_CONF_LINK_TOUT_THRES(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x1ff80)|value<<7) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_LINK_TOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x1ff80) >> 7 +} +func (o *PAU_Type) SetREGDMA_BKP_CONF_BURST_LIMIT(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x3e0000)|value<<17) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_BURST_LIMIT() uint32 { + return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x3e0000) >> 17 +} +func (o *PAU_Type) SetREGDMA_BKP_CONF_BACKUP_TOUT_THRES(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0xffc00000)|value<<22) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_BACKUP_TOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0xffc00000) >> 22 +} + +// PAU.RETENTION_LINK_BASE: retention dma link base +func (o *PAU_Type) SetRETENTION_LINK_BASE_LINK_BASE_ADDR(value uint32) { + volatile.StoreUint32(&o.RETENTION_LINK_BASE.Reg, volatile.LoadUint32(&o.RETENTION_LINK_BASE.Reg)&^(0x7ffffff)|value) +} +func (o *PAU_Type) GetRETENTION_LINK_BASE_LINK_BASE_ADDR() uint32 { + return volatile.LoadUint32(&o.RETENTION_LINK_BASE.Reg) & 0x7ffffff +} + +// PAU.RETENTION_CFG: retention_cfg +func (o *PAU_Type) SetRETENTION_CFG(value uint32) { + volatile.StoreUint32(&o.RETENTION_CFG.Reg, value) +} +func (o *PAU_Type) GetRETENTION_CFG() uint32 { + return volatile.LoadUint32(&o.RETENTION_CFG.Reg) +} + +// PAU.INT_ENA: Read only register for error and done +func (o *PAU_Type) SetINT_ENA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_ENA_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_ENA_ERROR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_ENA_ERROR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// PAU.INT_RAW: Read only register for error and done +func (o *PAU_Type) SetINT_RAW_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_RAW_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_RAW_ERROR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_RAW_ERROR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// PAU.INT_CLR: Read only register for error and done +func (o *PAU_Type) SetINT_CLR_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_CLR_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_CLR_ERROR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_CLR_ERROR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// PAU.INT_ST: Read only register for error and done +func (o *PAU_Type) SetINT_ST_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_ST_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_ST_ERROR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_ST_ERROR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// PAU.DATE: Date register. +func (o *PAU_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *PAU_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Pulse Count Controller +type PCNT_Type struct { + U0_CONF0 volatile.Register32 // 0x0 + U0_CONF1 volatile.Register32 // 0x4 + U0_CONF2 volatile.Register32 // 0x8 + U1_CONF0 volatile.Register32 // 0xC + U1_CONF1 volatile.Register32 // 0x10 + U1_CONF2 volatile.Register32 // 0x14 + U2_CONF0 volatile.Register32 // 0x18 + U2_CONF1 volatile.Register32 // 0x1C + U2_CONF2 volatile.Register32 // 0x20 + U3_CONF0 volatile.Register32 // 0x24 + U3_CONF1 volatile.Register32 // 0x28 + U3_CONF2 volatile.Register32 // 0x2C + U0_CNT volatile.Register32 // 0x30 + U1_CNT volatile.Register32 // 0x34 + U2_CNT volatile.Register32 // 0x38 + U3_CNT volatile.Register32 // 0x3C + INT_RAW volatile.Register32 // 0x40 + INT_ST volatile.Register32 // 0x44 + INT_ENA volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + U0_STATUS volatile.Register32 // 0x50 + U1_STATUS volatile.Register32 // 0x54 + U2_STATUS volatile.Register32 // 0x58 + U3_STATUS volatile.Register32 // 0x5C + CTRL volatile.Register32 // 0x60 + _ [152]byte + DATE volatile.Register32 // 0xFC +} + +// PCNT.U0_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU0_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU0_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU0_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU0_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU0_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU0_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU0_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU0_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U0_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU0_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU1_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU1_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU1_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU1_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU1_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU1_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU1_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU1_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U1_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU1_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU2_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU2_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU2_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU2_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU2_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU2_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU2_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU2_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U2_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU2_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU3_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU3_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU3_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU3_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU3_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU3_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU3_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU3_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U3_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU3_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU0_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U0_CNT.Reg, volatile.LoadUint32(&o.U0_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U0_CNT.Reg) & 0xffff +} + +// PCNT.U1_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU1_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U1_CNT.Reg, volatile.LoadUint32(&o.U1_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U1_CNT.Reg) & 0xffff +} + +// PCNT.U2_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU2_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U2_CNT.Reg, volatile.LoadUint32(&o.U2_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U2_CNT.Reg) & 0xffff +} + +// PCNT.U3_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU3_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U3_CNT.Reg, volatile.LoadUint32(&o.U3_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U3_CNT.Reg) & 0xffff +} + +// PCNT.INT_RAW: Interrupt raw status register +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ST: Interrupt status register +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ENA: Interrupt enable register +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// PCNT.INT_CLR: Interrupt clear register +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// PCNT.U0_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU0_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU0_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU0_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU0_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU0_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU0_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU0_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU0_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU0_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU0_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U1_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU1_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU1_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU1_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU1_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU1_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU1_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU1_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU1_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU1_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU1_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U2_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU2_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU2_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU2_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU2_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU2_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU2_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU2_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU2_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU2_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU2_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U3_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU3_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU3_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU3_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU3_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU3_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU3_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU3_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU3_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU3_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU3_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.CTRL: Control register for all counters +func (o *PCNT_Type) SetCTRL_CNT_RST_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U0() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U0() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *PCNT_Type) SetCTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *PCNT_Type) GetCTRL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} + +// PCNT.DATE: PCNT version control register +func (o *PCNT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *PCNT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// PCR Peripheral +type PCR_Type struct { + UART0_CONF volatile.Register32 // 0x0 + UART0_SCLK_CONF volatile.Register32 // 0x4 + UART0_PD_CTRL volatile.Register32 // 0x8 + UART1_CONF volatile.Register32 // 0xC + UART1_SCLK_CONF volatile.Register32 // 0x10 + UART1_PD_CTRL volatile.Register32 // 0x14 + MSPI_CONF volatile.Register32 // 0x18 + MSPI_CLK_CONF volatile.Register32 // 0x1C + I2C0_CONF volatile.Register32 // 0x20 + I2C0_SCLK_CONF volatile.Register32 // 0x24 + I2C1_CONF volatile.Register32 // 0x28 + I2C1_SCLK_CONF volatile.Register32 // 0x2C + UHCI_CONF volatile.Register32 // 0x30 + RMT_CONF volatile.Register32 // 0x34 + RMT_SCLK_CONF volatile.Register32 // 0x38 + LEDC_CONF volatile.Register32 // 0x3C + LEDC_SCLK_CONF volatile.Register32 // 0x40 + TIMERGROUP0_CONF volatile.Register32 // 0x44 + TIMERGROUP0_TIMER_CLK_CONF volatile.Register32 // 0x48 + TIMERGROUP0_WDT_CLK_CONF volatile.Register32 // 0x4C + TIMERGROUP1_CONF volatile.Register32 // 0x50 + TIMERGROUP1_TIMER_CLK_CONF volatile.Register32 // 0x54 + TIMERGROUP1_WDT_CLK_CONF volatile.Register32 // 0x58 + SYSTIMER_CONF volatile.Register32 // 0x5C + SYSTIMER_FUNC_CLK_CONF volatile.Register32 // 0x60 + TWAI0_CONF volatile.Register32 // 0x64 + TWAI0_FUNC_CLK_CONF volatile.Register32 // 0x68 + I2S_CONF volatile.Register32 // 0x6C + I2S_TX_CLKM_CONF volatile.Register32 // 0x70 + I2S_TX_CLKM_DIV_CONF volatile.Register32 // 0x74 + I2S_RX_CLKM_CONF volatile.Register32 // 0x78 + I2S_RX_CLKM_DIV_CONF volatile.Register32 // 0x7C + SARADC_CONF volatile.Register32 // 0x80 + SARADC_CLKM_CONF volatile.Register32 // 0x84 + TSENS_CLK_CONF volatile.Register32 // 0x88 + USB_DEVICE_CONF volatile.Register32 // 0x8C + INTMTX_CONF volatile.Register32 // 0x90 + PCNT_CONF volatile.Register32 // 0x94 + ETM_CONF volatile.Register32 // 0x98 + PWM_CONF volatile.Register32 // 0x9C + PWM_CLK_CONF volatile.Register32 // 0xA0 + PARL_IO_CONF volatile.Register32 // 0xA4 + PARL_CLK_RX_CONF volatile.Register32 // 0xA8 + PARL_CLK_TX_CONF volatile.Register32 // 0xAC + PVT_MONITOR_CONF volatile.Register32 // 0xB0 + PVT_MONITOR_FUNC_CLK_CONF volatile.Register32 // 0xB4 + GDMA_CONF volatile.Register32 // 0xB8 + SPI2_CONF volatile.Register32 // 0xBC + SPI2_CLKM_CONF volatile.Register32 // 0xC0 + AES_CONF volatile.Register32 // 0xC4 + SHA_CONF volatile.Register32 // 0xC8 + RSA_CONF volatile.Register32 // 0xCC + RSA_PD_CTRL volatile.Register32 // 0xD0 + ECC_CONF volatile.Register32 // 0xD4 + ECC_PD_CTRL volatile.Register32 // 0xD8 + DS_CONF volatile.Register32 // 0xDC + HMAC_CONF volatile.Register32 // 0xE0 + ECDSA_CONF volatile.Register32 // 0xE4 + IOMUX_CONF volatile.Register32 // 0xE8 + IOMUX_CLK_CONF volatile.Register32 // 0xEC + MEM_MONITOR_CONF volatile.Register32 // 0xF0 + REGDMA_CONF volatile.Register32 // 0xF4 + TRACE_CONF volatile.Register32 // 0xF8 + ASSIST_CONF volatile.Register32 // 0xFC + CACHE_CONF volatile.Register32 // 0x100 + MODEM_CONF volatile.Register32 // 0x104 + TIMEOUT_CONF volatile.Register32 // 0x108 + SYSCLK_CONF volatile.Register32 // 0x10C + CPU_WAITI_CONF volatile.Register32 // 0x110 + CPU_FREQ_CONF volatile.Register32 // 0x114 + AHB_FREQ_CONF volatile.Register32 // 0x118 + APB_FREQ_CONF volatile.Register32 // 0x11C + SYSCLK_FREQ_QUERY_0 volatile.Register32 // 0x120 + PLL_DIV_CLK_EN volatile.Register32 // 0x124 + CTRL_CLK_OUT_EN volatile.Register32 // 0x128 + CTRL_TICK_CONF volatile.Register32 // 0x12C + CTRL_32K_CONF volatile.Register32 // 0x130 + SRAM_POWER_CONF_0 volatile.Register32 // 0x134 + SRAM_POWER_CONF_1 volatile.Register32 // 0x138 + SEC_CONF volatile.Register32 // 0x13C + ADC_INV_PHASE_CONF volatile.Register32 // 0x140 + SDM_INV_PHASE_CONF volatile.Register32 // 0x144 + BUS_CLK_UPDATE volatile.Register32 // 0x148 + SAR_CLK_DIV volatile.Register32 // 0x14C + PWDET_SAR_CLK_CONF volatile.Register32 // 0x150 + _ [3740]byte + RESET_EVENT_BYPASS volatile.Register32 // 0xFF0 + FPGA_DEBUG volatile.Register32 // 0xFF4 + CLOCK_GATE volatile.Register32 // 0xFF8 + DATE volatile.Register32 // 0xFFC +} + +// PCR.UART0_CONF: UART0 configuration register +func (o *PCR_Type) SetUART0_CONF_UART0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.UART0_CONF.Reg, volatile.LoadUint32(&o.UART0_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetUART0_CONF_UART0_CLK_EN() uint32 { + return volatile.LoadUint32(&o.UART0_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetUART0_CONF_UART0_RST_EN(value uint32) { + volatile.StoreUint32(&o.UART0_CONF.Reg, volatile.LoadUint32(&o.UART0_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUART0_CONF_UART0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.UART0_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetUART0_CONF_UART0_READY(value uint32) { + volatile.StoreUint32(&o.UART0_CONF.Reg, volatile.LoadUint32(&o.UART0_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetUART0_CONF_UART0_READY() uint32 { + return (volatile.LoadUint32(&o.UART0_CONF.Reg) & 0x4) >> 2 +} + +// PCR.UART0_SCLK_CONF: UART0_SCLK configuration register +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_DIV_A() uint32 { + return volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetUART0_SCLK_CONF_UART0_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.UART0_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetUART0_SCLK_CONF_UART0_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.UART0_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.UART0_PD_CTRL: UART0 power control register +func (o *PCR_Type) SetUART0_PD_CTRL_UART0_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.UART0_PD_CTRL.Reg, volatile.LoadUint32(&o.UART0_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUART0_PD_CTRL_UART0_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.UART0_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetUART0_PD_CTRL_UART0_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.UART0_PD_CTRL.Reg, volatile.LoadUint32(&o.UART0_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetUART0_PD_CTRL_UART0_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.UART0_PD_CTRL.Reg) & 0x4) >> 2 +} + +// PCR.UART1_CONF: UART1 configuration register +func (o *PCR_Type) SetUART1_CONF_UART1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.UART1_CONF.Reg, volatile.LoadUint32(&o.UART1_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetUART1_CONF_UART1_CLK_EN() uint32 { + return volatile.LoadUint32(&o.UART1_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetUART1_CONF_UART1_RST_EN(value uint32) { + volatile.StoreUint32(&o.UART1_CONF.Reg, volatile.LoadUint32(&o.UART1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUART1_CONF_UART1_RST_EN() uint32 { + return (volatile.LoadUint32(&o.UART1_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetUART1_CONF_UART1_READY(value uint32) { + volatile.StoreUint32(&o.UART1_CONF.Reg, volatile.LoadUint32(&o.UART1_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetUART1_CONF_UART1_READY() uint32 { + return (volatile.LoadUint32(&o.UART1_CONF.Reg) & 0x4) >> 2 +} + +// PCR.UART1_SCLK_CONF: UART1_SCLK configuration register +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_DIV_A() uint32 { + return volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetUART1_SCLK_CONF_UART1_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.UART1_SCLK_CONF.Reg, volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetUART1_SCLK_CONF_UART1_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.UART1_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.UART1_PD_CTRL: UART1 power control register +func (o *PCR_Type) SetUART1_PD_CTRL_UART1_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.UART1_PD_CTRL.Reg, volatile.LoadUint32(&o.UART1_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUART1_PD_CTRL_UART1_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.UART1_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetUART1_PD_CTRL_UART1_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.UART1_PD_CTRL.Reg, volatile.LoadUint32(&o.UART1_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetUART1_PD_CTRL_UART1_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.UART1_PD_CTRL.Reg) & 0x4) >> 2 +} + +// PCR.MSPI_CONF: MSPI configuration register +func (o *PCR_Type) SetMSPI_CONF_MSPI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MSPI_CONF.Reg, volatile.LoadUint32(&o.MSPI_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetMSPI_CONF_MSPI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MSPI_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetMSPI_CONF_MSPI_RST_EN(value uint32) { + volatile.StoreUint32(&o.MSPI_CONF.Reg, volatile.LoadUint32(&o.MSPI_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetMSPI_CONF_MSPI_RST_EN() uint32 { + return (volatile.LoadUint32(&o.MSPI_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetMSPI_CONF_MSPI_PLL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MSPI_CONF.Reg, volatile.LoadUint32(&o.MSPI_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetMSPI_CONF_MSPI_PLL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MSPI_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetMSPI_CONF_MSPI_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.MSPI_CONF.Reg, volatile.LoadUint32(&o.MSPI_CONF.Reg)&^(0x18)|value<<3) +} +func (o *PCR_Type) GetMSPI_CONF_MSPI_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.MSPI_CONF.Reg) & 0x18) >> 3 +} +func (o *PCR_Type) SetMSPI_CONF_MSPI_READY(value uint32) { + volatile.StoreUint32(&o.MSPI_CONF.Reg, volatile.LoadUint32(&o.MSPI_CONF.Reg)&^(0x20)|value<<5) +} +func (o *PCR_Type) GetMSPI_CONF_MSPI_READY() uint32 { + return (volatile.LoadUint32(&o.MSPI_CONF.Reg) & 0x20) >> 5 +} + +// PCR.MSPI_CLK_CONF: MSPI_CLK configuration register +func (o *PCR_Type) SetMSPI_CLK_CONF_MSPI_FAST_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.MSPI_CLK_CONF.Reg, volatile.LoadUint32(&o.MSPI_CLK_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetMSPI_CLK_CONF_MSPI_FAST_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.MSPI_CLK_CONF.Reg) & 0xff +} + +// PCR.I2C0_CONF: I2C configuration register +func (o *PCR_Type) SetI2C0_CONF_I2C0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetI2C0_CONF_I2C0_CLK_EN() uint32 { + return volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetI2C0_CONF_I2C0_RST_EN(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetI2C0_CONF_I2C0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetI2C0_CONF_I2C0_READY(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetI2C0_CONF_I2C0_READY() uint32 { + return (volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0x4) >> 2 +} + +// PCR.I2C0_SCLK_CONF: I2C_SCLK configuration register +func (o *PCR_Type) SetI2C0_SCLK_CONF_I2C0_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.I2C0_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetI2C0_SCLK_CONF_I2C0_SCLK_DIV_A() uint32 { + return volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetI2C0_SCLK_CONF_I2C0_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.I2C0_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetI2C0_SCLK_CONF_I2C0_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetI2C0_SCLK_CONF_I2C0_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2C0_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetI2C0_SCLK_CONF_I2C0_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetI2C0_SCLK_CONF_I2C0_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.I2C0_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetI2C0_SCLK_CONF_I2C0_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetI2C0_SCLK_CONF_I2C0_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.I2C0_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetI2C0_SCLK_CONF_I2C0_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.I2C0_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.I2C1_CONF: I2C configuration register +func (o *PCR_Type) SetI2C1_CONF_I2C1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.I2C1_CONF.Reg, volatile.LoadUint32(&o.I2C1_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetI2C1_CONF_I2C1_CLK_EN() uint32 { + return volatile.LoadUint32(&o.I2C1_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetI2C1_CONF_I2C1_RST_EN(value uint32) { + volatile.StoreUint32(&o.I2C1_CONF.Reg, volatile.LoadUint32(&o.I2C1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetI2C1_CONF_I2C1_RST_EN() uint32 { + return (volatile.LoadUint32(&o.I2C1_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetI2C1_CONF_I2C1_READY(value uint32) { + volatile.StoreUint32(&o.I2C1_CONF.Reg, volatile.LoadUint32(&o.I2C1_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetI2C1_CONF_I2C1_READY() uint32 { + return (volatile.LoadUint32(&o.I2C1_CONF.Reg) & 0x4) >> 2 +} + +// PCR.I2C1_SCLK_CONF: I2C_SCLK configuration register +func (o *PCR_Type) SetI2C1_SCLK_CONF_I2C1_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.I2C1_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetI2C1_SCLK_CONF_I2C1_SCLK_DIV_A() uint32 { + return volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetI2C1_SCLK_CONF_I2C1_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.I2C1_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetI2C1_SCLK_CONF_I2C1_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetI2C1_SCLK_CONF_I2C1_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2C1_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetI2C1_SCLK_CONF_I2C1_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetI2C1_SCLK_CONF_I2C1_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.I2C1_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetI2C1_SCLK_CONF_I2C1_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetI2C1_SCLK_CONF_I2C1_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.I2C1_SCLK_CONF.Reg, volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetI2C1_SCLK_CONF_I2C1_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.I2C1_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.UHCI_CONF: UHCI configuration register +func (o *PCR_Type) SetUHCI_CONF_UHCI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.UHCI_CONF.Reg, volatile.LoadUint32(&o.UHCI_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetUHCI_CONF_UHCI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.UHCI_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetUHCI_CONF_UHCI_RST_EN(value uint32) { + volatile.StoreUint32(&o.UHCI_CONF.Reg, volatile.LoadUint32(&o.UHCI_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUHCI_CONF_UHCI_RST_EN() uint32 { + return (volatile.LoadUint32(&o.UHCI_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetUHCI_CONF_UHCI_READY(value uint32) { + volatile.StoreUint32(&o.UHCI_CONF.Reg, volatile.LoadUint32(&o.UHCI_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetUHCI_CONF_UHCI_READY() uint32 { + return (volatile.LoadUint32(&o.UHCI_CONF.Reg) & 0x4) >> 2 +} + +// PCR.RMT_CONF: RMT configuration register +func (o *PCR_Type) SetRMT_CONF_RMT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.RMT_CONF.Reg, volatile.LoadUint32(&o.RMT_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetRMT_CONF_RMT_CLK_EN() uint32 { + return volatile.LoadUint32(&o.RMT_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetRMT_CONF_RMT_RST_EN(value uint32) { + volatile.StoreUint32(&o.RMT_CONF.Reg, volatile.LoadUint32(&o.RMT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetRMT_CONF_RMT_RST_EN() uint32 { + return (volatile.LoadUint32(&o.RMT_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetRMT_CONF_RMT_READY(value uint32) { + volatile.StoreUint32(&o.RMT_CONF.Reg, volatile.LoadUint32(&o.RMT_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetRMT_CONF_RMT_READY() uint32 { + return (volatile.LoadUint32(&o.RMT_CONF.Reg) & 0x4) >> 2 +} + +// PCR.RMT_SCLK_CONF: RMT_SCLK configuration register +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_DIV_A() uint32 { + return volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetRMT_SCLK_CONF_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.RMT_SCLK_CONF.Reg, volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *PCR_Type) GetRMT_SCLK_CONF_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.RMT_SCLK_CONF.Reg) & 0x200000) >> 21 +} + +// PCR.LEDC_CONF: LEDC configuration register +func (o *PCR_Type) SetLEDC_CONF_LEDC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LEDC_CONF.Reg, volatile.LoadUint32(&o.LEDC_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetLEDC_CONF_LEDC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.LEDC_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetLEDC_CONF_LEDC_RST_EN(value uint32) { + volatile.StoreUint32(&o.LEDC_CONF.Reg, volatile.LoadUint32(&o.LEDC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetLEDC_CONF_LEDC_RST_EN() uint32 { + return (volatile.LoadUint32(&o.LEDC_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetLEDC_CONF_LEDC_READY(value uint32) { + volatile.StoreUint32(&o.LEDC_CONF.Reg, volatile.LoadUint32(&o.LEDC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetLEDC_CONF_LEDC_READY() uint32 { + return (volatile.LoadUint32(&o.LEDC_CONF.Reg) & 0x4) >> 2 +} + +// PCR.LEDC_SCLK_CONF: LEDC_SCLK configuration register +func (o *PCR_Type) SetLEDC_SCLK_CONF_LEDC_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.LEDC_SCLK_CONF.Reg, volatile.LoadUint32(&o.LEDC_SCLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetLEDC_SCLK_CONF_LEDC_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LEDC_SCLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetLEDC_SCLK_CONF_LEDC_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.LEDC_SCLK_CONF.Reg, volatile.LoadUint32(&o.LEDC_SCLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetLEDC_SCLK_CONF_LEDC_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.LEDC_SCLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TIMERGROUP0_CONF: TIMERGROUP0 configuration register +func (o *PCR_Type) SetTIMERGROUP0_CONF_TG0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetTIMERGROUP0_CONF_TG0_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetTIMERGROUP0_CONF_TG0_RST_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTIMERGROUP0_CONF_TG0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetTIMERGROUP0_CONF_TG0_WDT_READY(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetTIMERGROUP0_CONF_TG0_WDT_READY() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetTIMERGROUP0_CONF_TG0_TIMER0_READY(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetTIMERGROUP0_CONF_TG0_TIMER0_READY() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetTIMERGROUP0_CONF_TG0_TIMER1_READY(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg)&^(0x10)|value<<4) +} +func (o *PCR_Type) GetTIMERGROUP0_CONF_TG0_TIMER1_READY() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_CONF.Reg) & 0x10) >> 4 +} + +// PCR.TIMERGROUP0_TIMER_CLK_CONF: TIMERGROUP0_TIMER_CLK configuration register +func (o *PCR_Type) SetTIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetTIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetTIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_TIMER_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TIMERGROUP0_WDT_CLK_CONF: TIMERGROUP0_WDT_CLK configuration register +func (o *PCR_Type) SetTIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetTIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetTIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP0_WDT_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TIMERGROUP1_CONF: TIMERGROUP1 configuration register +func (o *PCR_Type) SetTIMERGROUP1_CONF_TG1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetTIMERGROUP1_CONF_TG1_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetTIMERGROUP1_CONF_TG1_RST_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTIMERGROUP1_CONF_TG1_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetTIMERGROUP1_CONF_TG1_WDT_READY(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetTIMERGROUP1_CONF_TG1_WDT_READY() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetTIMERGROUP1_CONF_TG1_TIMER0_READY(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetTIMERGROUP1_CONF_TG1_TIMER0_READY() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetTIMERGROUP1_CONF_TG1_TIMER1_READY(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg)&^(0x10)|value<<4) +} +func (o *PCR_Type) GetTIMERGROUP1_CONF_TG1_TIMER1_READY() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_CONF.Reg) & 0x10) >> 4 +} + +// PCR.TIMERGROUP1_TIMER_CLK_CONF: TIMERGROUP1_TIMER_CLK configuration register +func (o *PCR_Type) SetTIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetTIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetTIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_TIMER_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TIMERGROUP1_WDT_CLK_CONF: TIMERGROUP1_WDT_CLK configuration register +func (o *PCR_Type) SetTIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetTIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetTIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg, volatile.LoadUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TIMERGROUP1_WDT_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.SYSTIMER_CONF: SYSTIMER configuration register +func (o *PCR_Type) SetSYSTIMER_CONF_SYSTIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_CONF.Reg, volatile.LoadUint32(&o.SYSTIMER_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSYSTIMER_CONF_SYSTIMER_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSYSTIMER_CONF_SYSTIMER_RST_EN(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_CONF.Reg, volatile.LoadUint32(&o.SYSTIMER_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetSYSTIMER_CONF_SYSTIMER_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SYSTIMER_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetSYSTIMER_CONF_SYSTIMER_READY(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_CONF.Reg, volatile.LoadUint32(&o.SYSTIMER_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetSYSTIMER_CONF_SYSTIMER_READY() uint32 { + return (volatile.LoadUint32(&o.SYSTIMER_CONF.Reg) & 0x4) >> 2 +} + +// PCR.SYSTIMER_FUNC_CLK_CONF: SYSTIMER_FUNC_CLK configuration register +func (o *PCR_Type) SetSYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetSYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetSYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetSYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYSTIMER_FUNC_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TWAI0_CONF: TWAI0 configuration register +func (o *PCR_Type) SetTWAI0_CONF_TWAI0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TWAI0_CONF.Reg, volatile.LoadUint32(&o.TWAI0_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetTWAI0_CONF_TWAI0_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TWAI0_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetTWAI0_CONF_TWAI0_RST_EN(value uint32) { + volatile.StoreUint32(&o.TWAI0_CONF.Reg, volatile.LoadUint32(&o.TWAI0_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTWAI0_CONF_TWAI0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TWAI0_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetTWAI0_CONF_TWAI0_READY(value uint32) { + volatile.StoreUint32(&o.TWAI0_CONF.Reg, volatile.LoadUint32(&o.TWAI0_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetTWAI0_CONF_TWAI0_READY() uint32 { + return (volatile.LoadUint32(&o.TWAI0_CONF.Reg) & 0x4) >> 2 +} + +// PCR.TWAI0_FUNC_CLK_CONF: TWAI0_FUNC_CLK configuration register +func (o *PCR_Type) SetTWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TWAI0_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.TWAI0_FUNC_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetTWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TWAI0_FUNC_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetTWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TWAI0_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.TWAI0_FUNC_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TWAI0_FUNC_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.I2S_CONF: I2S configuration register +func (o *PCR_Type) SetI2S_CONF_I2S_CLK_EN(value uint32) { + volatile.StoreUint32(&o.I2S_CONF.Reg, volatile.LoadUint32(&o.I2S_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetI2S_CONF_I2S_CLK_EN() uint32 { + return volatile.LoadUint32(&o.I2S_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetI2S_CONF_I2S_RST_EN(value uint32) { + volatile.StoreUint32(&o.I2S_CONF.Reg, volatile.LoadUint32(&o.I2S_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetI2S_CONF_I2S_RST_EN() uint32 { + return (volatile.LoadUint32(&o.I2S_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetI2S_CONF_I2S_RX_READY(value uint32) { + volatile.StoreUint32(&o.I2S_CONF.Reg, volatile.LoadUint32(&o.I2S_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetI2S_CONF_I2S_RX_READY() uint32 { + return (volatile.LoadUint32(&o.I2S_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetI2S_CONF_I2S_TX_READY(value uint32) { + volatile.StoreUint32(&o.I2S_CONF.Reg, volatile.LoadUint32(&o.I2S_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetI2S_CONF_I2S_TX_READY() uint32 { + return (volatile.LoadUint32(&o.I2S_CONF.Reg) & 0x8) >> 3 +} + +// PCR.I2S_TX_CLKM_CONF: I2S_TX_CLKM configuration register +func (o *PCR_Type) SetI2S_TX_CLKM_CONF_I2S_TX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetI2S_TX_CLKM_CONF_I2S_TX_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetI2S_TX_CLKM_CONF_I2S_TX_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetI2S_TX_CLKM_CONF_I2S_TX_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetI2S_TX_CLKM_CONF_I2S_TX_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetI2S_TX_CLKM_CONF_I2S_TX_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.I2S_TX_CLKM_DIV_CONF: I2S_TX_CLKM_DIV configuration register +func (o *PCR_Type) SetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *PCR_Type) GetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *PCR_Type) SetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *PCR_Type) GetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *PCR_Type) SetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *PCR_Type) GetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *PCR_Type) SetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *PCR_Type) GetI2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.I2S_TX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// PCR.I2S_RX_CLKM_CONF: I2S_RX_CLKM configuration register +func (o *PCR_Type) SetI2S_RX_CLKM_CONF_I2S_RX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetI2S_RX_CLKM_CONF_I2S_RX_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetI2S_RX_CLKM_CONF_I2S_RX_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetI2S_RX_CLKM_CONF_I2S_RX_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetI2S_RX_CLKM_CONF_I2S_RX_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetI2S_RX_CLKM_CONF_I2S_RX_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg) & 0x400000) >> 22 +} +func (o *PCR_Type) SetI2S_RX_CLKM_CONF_I2S_MCLK_SEL(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *PCR_Type) GetI2S_RX_CLKM_CONF_I2S_MCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_CONF.Reg) & 0x800000) >> 23 +} + +// PCR.I2S_RX_CLKM_DIV_CONF: I2S_RX_CLKM_DIV configuration register +func (o *PCR_Type) SetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *PCR_Type) GetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *PCR_Type) SetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *PCR_Type) GetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *PCR_Type) SetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *PCR_Type) GetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *PCR_Type) SetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *PCR_Type) GetI2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.I2S_RX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// PCR.SARADC_CONF: SARADC configuration register +func (o *PCR_Type) SetSARADC_CONF_SARADC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CONF.Reg, volatile.LoadUint32(&o.SARADC_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSARADC_CONF_SARADC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SARADC_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSARADC_CONF_SARADC_RST_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CONF.Reg, volatile.LoadUint32(&o.SARADC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetSARADC_CONF_SARADC_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SARADC_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetSARADC_CONF_SARADC_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CONF.Reg, volatile.LoadUint32(&o.SARADC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetSARADC_CONF_SARADC_REG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SARADC_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetSARADC_CONF_SARADC_REG_RST_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CONF.Reg, volatile.LoadUint32(&o.SARADC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetSARADC_CONF_SARADC_REG_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SARADC_CONF.Reg) & 0x8) >> 3 +} + +// PCR.SARADC_CLKM_CONF: SARADC_CLKM configuration register +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0x3f)|value) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_DIV_A() uint32 { + return volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0x3f +} +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0xfc0) >> 6 +} +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetSARADC_CLKM_CONF_SARADC_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.SARADC_CLKM_CONF.Reg, volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetSARADC_CLKM_CONF_SARADC_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.SARADC_CLKM_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.TSENS_CLK_CONF: TSENS_CLK configuration register +func (o *PCR_Type) SetTSENS_CLK_CONF_TSENS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TSENS_CLK_CONF.Reg, volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetTSENS_CLK_CONF_TSENS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetTSENS_CLK_CONF_TSENS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TSENS_CLK_CONF.Reg, volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetTSENS_CLK_CONF_TSENS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *PCR_Type) SetTSENS_CLK_CONF_TSENS_RST_EN(value uint32) { + volatile.StoreUint32(&o.TSENS_CLK_CONF.Reg, volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *PCR_Type) GetTSENS_CLK_CONF_TSENS_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TSENS_CLK_CONF.Reg) & 0x800000) >> 23 +} + +// PCR.USB_DEVICE_CONF: USB_DEVICE configuration register +func (o *PCR_Type) SetUSB_DEVICE_CONF_USB_DEVICE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.USB_DEVICE_CONF.Reg, volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetUSB_DEVICE_CONF_USB_DEVICE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetUSB_DEVICE_CONF_USB_DEVICE_RST_EN(value uint32) { + volatile.StoreUint32(&o.USB_DEVICE_CONF.Reg, volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetUSB_DEVICE_CONF_USB_DEVICE_RST_EN() uint32 { + return (volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetUSB_DEVICE_CONF_USB_DEVICE_READY(value uint32) { + volatile.StoreUint32(&o.USB_DEVICE_CONF.Reg, volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetUSB_DEVICE_CONF_USB_DEVICE_READY() uint32 { + return (volatile.LoadUint32(&o.USB_DEVICE_CONF.Reg) & 0x4) >> 2 +} + +// PCR.INTMTX_CONF: INTMTX configuration register +func (o *PCR_Type) SetINTMTX_CONF_INTMTX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.INTMTX_CONF.Reg, volatile.LoadUint32(&o.INTMTX_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetINTMTX_CONF_INTMTX_CLK_EN() uint32 { + return volatile.LoadUint32(&o.INTMTX_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetINTMTX_CONF_INTMTX_RST_EN(value uint32) { + volatile.StoreUint32(&o.INTMTX_CONF.Reg, volatile.LoadUint32(&o.INTMTX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetINTMTX_CONF_INTMTX_RST_EN() uint32 { + return (volatile.LoadUint32(&o.INTMTX_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetINTMTX_CONF_INTMTX_READY(value uint32) { + volatile.StoreUint32(&o.INTMTX_CONF.Reg, volatile.LoadUint32(&o.INTMTX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetINTMTX_CONF_INTMTX_READY() uint32 { + return (volatile.LoadUint32(&o.INTMTX_CONF.Reg) & 0x4) >> 2 +} + +// PCR.PCNT_CONF: PCNT configuration register +func (o *PCR_Type) SetPCNT_CONF_PCNT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PCNT_CONF.Reg, volatile.LoadUint32(&o.PCNT_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPCNT_CONF_PCNT_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PCNT_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetPCNT_CONF_PCNT_RST_EN(value uint32) { + volatile.StoreUint32(&o.PCNT_CONF.Reg, volatile.LoadUint32(&o.PCNT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPCNT_CONF_PCNT_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PCNT_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetPCNT_CONF_PCNT_READY(value uint32) { + volatile.StoreUint32(&o.PCNT_CONF.Reg, volatile.LoadUint32(&o.PCNT_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetPCNT_CONF_PCNT_READY() uint32 { + return (volatile.LoadUint32(&o.PCNT_CONF.Reg) & 0x4) >> 2 +} + +// PCR.ETM_CONF: ETM configuration register +func (o *PCR_Type) SetETM_CONF_ETM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetETM_CONF_ETM_CLK_EN() uint32 { + return volatile.LoadUint32(&o.ETM_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetETM_CONF_ETM_RST_EN(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetETM_CONF_ETM_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetETM_CONF_ETM_READY(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetETM_CONF_ETM_READY() uint32 { + return (volatile.LoadUint32(&o.ETM_CONF.Reg) & 0x4) >> 2 +} + +// PCR.PWM_CONF: PWM configuration register +func (o *PCR_Type) SetPWM_CONF_PWM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PWM_CONF.Reg, volatile.LoadUint32(&o.PWM_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPWM_CONF_PWM_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PWM_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetPWM_CONF_PWM_RST_EN(value uint32) { + volatile.StoreUint32(&o.PWM_CONF.Reg, volatile.LoadUint32(&o.PWM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPWM_CONF_PWM_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PWM_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetPWM_CONF_PWM_READY(value uint32) { + volatile.StoreUint32(&o.PWM_CONF.Reg, volatile.LoadUint32(&o.PWM_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetPWM_CONF_PWM_READY() uint32 { + return (volatile.LoadUint32(&o.PWM_CONF.Reg) & 0x4) >> 2 +} + +// PCR.PWM_CLK_CONF: PWM_CLK configuration register +func (o *PCR_Type) SetPWM_CLK_CONF_PWM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PWM_CLK_CONF.Reg, volatile.LoadUint32(&o.PWM_CLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *PCR_Type) GetPWM_CLK_CONF_PWM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PWM_CLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *PCR_Type) SetPWM_CLK_CONF_PWM_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.PWM_CLK_CONF.Reg, volatile.LoadUint32(&o.PWM_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetPWM_CLK_CONF_PWM_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.PWM_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetPWM_CLK_CONF_PWM_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.PWM_CLK_CONF.Reg, volatile.LoadUint32(&o.PWM_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetPWM_CLK_CONF_PWM_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.PWM_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.PARL_IO_CONF: PARL_IO configuration register +func (o *PCR_Type) SetPARL_IO_CONF_PARL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PARL_IO_CONF.Reg, volatile.LoadUint32(&o.PARL_IO_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPARL_IO_CONF_PARL_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PARL_IO_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetPARL_IO_CONF_PARL_RST_EN(value uint32) { + volatile.StoreUint32(&o.PARL_IO_CONF.Reg, volatile.LoadUint32(&o.PARL_IO_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPARL_IO_CONF_PARL_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_IO_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetPARL_IO_CONF_PARL_READY(value uint32) { + volatile.StoreUint32(&o.PARL_IO_CONF.Reg, volatile.LoadUint32(&o.PARL_IO_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetPARL_IO_CONF_PARL_READY() uint32 { + return (volatile.LoadUint32(&o.PARL_IO_CONF.Reg) & 0x4) >> 2 +} + +// PCR.PARL_CLK_RX_CONF: PARL_CLK_RX configuration register +func (o *PCR_Type) SetPARL_CLK_RX_CONF_PARL_CLK_RX_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_RX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg)&^(0xffff)|value) +} +func (o *PCR_Type) GetPARL_CLK_RX_CONF_PARL_CLK_RX_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg) & 0xffff +} +func (o *PCR_Type) SetPARL_CLK_RX_CONF_PARL_CLK_RX_SEL(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_RX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg)&^(0x30000)|value<<16) +} +func (o *PCR_Type) GetPARL_CLK_RX_CONF_PARL_CLK_RX_SEL() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg) & 0x30000) >> 16 +} +func (o *PCR_Type) SetPARL_CLK_RX_CONF_PARL_CLK_RX_EN(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_RX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *PCR_Type) GetPARL_CLK_RX_CONF_PARL_CLK_RX_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg) & 0x40000) >> 18 +} +func (o *PCR_Type) SetPARL_CLK_RX_CONF_PARL_RX_RST_EN(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_RX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *PCR_Type) GetPARL_CLK_RX_CONF_PARL_RX_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_RX_CONF.Reg) & 0x80000) >> 19 +} + +// PCR.PARL_CLK_TX_CONF: PARL_CLK_TX configuration register +func (o *PCR_Type) SetPARL_CLK_TX_CONF_PARL_CLK_TX_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_TX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg)&^(0xffff)|value) +} +func (o *PCR_Type) GetPARL_CLK_TX_CONF_PARL_CLK_TX_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg) & 0xffff +} +func (o *PCR_Type) SetPARL_CLK_TX_CONF_PARL_CLK_TX_SEL(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_TX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg)&^(0x30000)|value<<16) +} +func (o *PCR_Type) GetPARL_CLK_TX_CONF_PARL_CLK_TX_SEL() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg) & 0x30000) >> 16 +} +func (o *PCR_Type) SetPARL_CLK_TX_CONF_PARL_CLK_TX_EN(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_TX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *PCR_Type) GetPARL_CLK_TX_CONF_PARL_CLK_TX_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg) & 0x40000) >> 18 +} +func (o *PCR_Type) SetPARL_CLK_TX_CONF_PARL_TX_RST_EN(value uint32) { + volatile.StoreUint32(&o.PARL_CLK_TX_CONF.Reg, volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *PCR_Type) GetPARL_CLK_TX_CONF_PARL_TX_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PARL_CLK_TX_CONF.Reg) & 0x80000) >> 19 +} + +// PCR.PVT_MONITOR_CONF: PVT_MONITOR configuration register +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_RST_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_RST_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetPVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg)&^(0x10)|value<<4) +} +func (o *PCR_Type) GetPVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_CONF.Reg) & 0x10) >> 4 +} + +// PCR.PVT_MONITOR_FUNC_CLK_CONF: PVT_MONITOR function clock configuration register +func (o *PCR_Type) SetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg)&^(0xf)|value) +} +func (o *PCR_Type) GetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg) & 0xf +} +func (o *PCR_Type) SetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *PCR_Type) GetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *PCR_Type) SetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg, volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetPVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PVT_MONITOR_FUNC_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.GDMA_CONF: GDMA configuration register +func (o *PCR_Type) SetGDMA_CONF_GDMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.GDMA_CONF.Reg, volatile.LoadUint32(&o.GDMA_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetGDMA_CONF_GDMA_CLK_EN() uint32 { + return volatile.LoadUint32(&o.GDMA_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetGDMA_CONF_GDMA_RST_EN(value uint32) { + volatile.StoreUint32(&o.GDMA_CONF.Reg, volatile.LoadUint32(&o.GDMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetGDMA_CONF_GDMA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.GDMA_CONF.Reg) & 0x2) >> 1 +} + +// PCR.SPI2_CONF: SPI2 configuration register +func (o *PCR_Type) SetSPI2_CONF_SPI2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI2_CONF.Reg, volatile.LoadUint32(&o.SPI2_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSPI2_CONF_SPI2_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI2_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSPI2_CONF_SPI2_RST_EN(value uint32) { + volatile.StoreUint32(&o.SPI2_CONF.Reg, volatile.LoadUint32(&o.SPI2_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetSPI2_CONF_SPI2_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SPI2_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetSPI2_CONF_SPI2_READY(value uint32) { + volatile.StoreUint32(&o.SPI2_CONF.Reg, volatile.LoadUint32(&o.SPI2_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetSPI2_CONF_SPI2_READY() uint32 { + return (volatile.LoadUint32(&o.SPI2_CONF.Reg) & 0x4) >> 2 +} + +// PCR.SPI2_CLKM_CONF: SPI2_CLKM configuration register +func (o *PCR_Type) SetSPI2_CLKM_CONF_SPI2_CLKM_SEL(value uint32) { + volatile.StoreUint32(&o.SPI2_CLKM_CONF.Reg, volatile.LoadUint32(&o.SPI2_CLKM_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetSPI2_CLKM_CONF_SPI2_CLKM_SEL() uint32 { + return (volatile.LoadUint32(&o.SPI2_CLKM_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetSPI2_CLKM_CONF_SPI2_CLKM_EN(value uint32) { + volatile.StoreUint32(&o.SPI2_CLKM_CONF.Reg, volatile.LoadUint32(&o.SPI2_CLKM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetSPI2_CLKM_CONF_SPI2_CLKM_EN() uint32 { + return (volatile.LoadUint32(&o.SPI2_CLKM_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.AES_CONF: AES configuration register +func (o *PCR_Type) SetAES_CONF_AES_CLK_EN(value uint32) { + volatile.StoreUint32(&o.AES_CONF.Reg, volatile.LoadUint32(&o.AES_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetAES_CONF_AES_CLK_EN() uint32 { + return volatile.LoadUint32(&o.AES_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetAES_CONF_AES_RST_EN(value uint32) { + volatile.StoreUint32(&o.AES_CONF.Reg, volatile.LoadUint32(&o.AES_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetAES_CONF_AES_RST_EN() uint32 { + return (volatile.LoadUint32(&o.AES_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetAES_CONF_AES_READY(value uint32) { + volatile.StoreUint32(&o.AES_CONF.Reg, volatile.LoadUint32(&o.AES_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetAES_CONF_AES_READY() uint32 { + return (volatile.LoadUint32(&o.AES_CONF.Reg) & 0x4) >> 2 +} + +// PCR.SHA_CONF: SHA configuration register +func (o *PCR_Type) SetSHA_CONF_SHA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SHA_CONF.Reg, volatile.LoadUint32(&o.SHA_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSHA_CONF_SHA_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SHA_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSHA_CONF_SHA_RST_EN(value uint32) { + volatile.StoreUint32(&o.SHA_CONF.Reg, volatile.LoadUint32(&o.SHA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetSHA_CONF_SHA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.SHA_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetSHA_CONF_SHA_READY(value uint32) { + volatile.StoreUint32(&o.SHA_CONF.Reg, volatile.LoadUint32(&o.SHA_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetSHA_CONF_SHA_READY() uint32 { + return (volatile.LoadUint32(&o.SHA_CONF.Reg) & 0x4) >> 2 +} + +// PCR.RSA_CONF: RSA configuration register +func (o *PCR_Type) SetRSA_CONF_RSA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.RSA_CONF.Reg, volatile.LoadUint32(&o.RSA_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetRSA_CONF_RSA_CLK_EN() uint32 { + return volatile.LoadUint32(&o.RSA_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetRSA_CONF_RSA_RST_EN(value uint32) { + volatile.StoreUint32(&o.RSA_CONF.Reg, volatile.LoadUint32(&o.RSA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetRSA_CONF_RSA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.RSA_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetRSA_CONF_RSA_READY(value uint32) { + volatile.StoreUint32(&o.RSA_CONF.Reg, volatile.LoadUint32(&o.RSA_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetRSA_CONF_RSA_READY() uint32 { + return (volatile.LoadUint32(&o.RSA_CONF.Reg) & 0x4) >> 2 +} + +// PCR.RSA_PD_CTRL: RSA power control register +func (o *PCR_Type) SetRSA_PD_CTRL_RSA_MEM_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetRSA_PD_CTRL_RSA_MEM_PD() uint32 { + return volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x1 +} +func (o *PCR_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x4) >> 2 +} + +// PCR.ECC_CONF: ECC configuration register +func (o *PCR_Type) SetECC_CONF_ECC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.ECC_CONF.Reg, volatile.LoadUint32(&o.ECC_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetECC_CONF_ECC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.ECC_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetECC_CONF_ECC_RST_EN(value uint32) { + volatile.StoreUint32(&o.ECC_CONF.Reg, volatile.LoadUint32(&o.ECC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetECC_CONF_ECC_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ECC_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetECC_CONF_ECC_READY(value uint32) { + volatile.StoreUint32(&o.ECC_CONF.Reg, volatile.LoadUint32(&o.ECC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetECC_CONF_ECC_READY() uint32 { + return (volatile.LoadUint32(&o.ECC_CONF.Reg) & 0x4) >> 2 +} + +// PCR.ECC_PD_CTRL: ECC power control register +func (o *PCR_Type) SetECC_PD_CTRL_ECC_MEM_PD(value uint32) { + volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetECC_PD_CTRL_ECC_MEM_PD() uint32 { + return volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x1 +} +func (o *PCR_Type) SetECC_PD_CTRL_ECC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetECC_PD_CTRL_ECC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetECC_PD_CTRL_ECC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetECC_PD_CTRL_ECC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x4) >> 2 +} + +// PCR.DS_CONF: DS configuration register +func (o *PCR_Type) SetDS_CONF_DS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DS_CONF.Reg, volatile.LoadUint32(&o.DS_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetDS_CONF_DS_CLK_EN() uint32 { + return volatile.LoadUint32(&o.DS_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetDS_CONF_DS_RST_EN(value uint32) { + volatile.StoreUint32(&o.DS_CONF.Reg, volatile.LoadUint32(&o.DS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetDS_CONF_DS_RST_EN() uint32 { + return (volatile.LoadUint32(&o.DS_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetDS_CONF_DS_READY(value uint32) { + volatile.StoreUint32(&o.DS_CONF.Reg, volatile.LoadUint32(&o.DS_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetDS_CONF_DS_READY() uint32 { + return (volatile.LoadUint32(&o.DS_CONF.Reg) & 0x4) >> 2 +} + +// PCR.HMAC_CONF: HMAC configuration register +func (o *PCR_Type) SetHMAC_CONF_HMAC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.HMAC_CONF.Reg, volatile.LoadUint32(&o.HMAC_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetHMAC_CONF_HMAC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.HMAC_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetHMAC_CONF_HMAC_RST_EN(value uint32) { + volatile.StoreUint32(&o.HMAC_CONF.Reg, volatile.LoadUint32(&o.HMAC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetHMAC_CONF_HMAC_RST_EN() uint32 { + return (volatile.LoadUint32(&o.HMAC_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetHMAC_CONF_HMAC_READY(value uint32) { + volatile.StoreUint32(&o.HMAC_CONF.Reg, volatile.LoadUint32(&o.HMAC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetHMAC_CONF_HMAC_READY() uint32 { + return (volatile.LoadUint32(&o.HMAC_CONF.Reg) & 0x4) >> 2 +} + +// PCR.ECDSA_CONF: ECDSA configuration register +func (o *PCR_Type) SetECDSA_CONF_ECDSA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.ECDSA_CONF.Reg, volatile.LoadUint32(&o.ECDSA_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetECDSA_CONF_ECDSA_CLK_EN() uint32 { + return volatile.LoadUint32(&o.ECDSA_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetECDSA_CONF_ECDSA_RST_EN(value uint32) { + volatile.StoreUint32(&o.ECDSA_CONF.Reg, volatile.LoadUint32(&o.ECDSA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetECDSA_CONF_ECDSA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ECDSA_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetECDSA_CONF_ECDSA_READY(value uint32) { + volatile.StoreUint32(&o.ECDSA_CONF.Reg, volatile.LoadUint32(&o.ECDSA_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetECDSA_CONF_ECDSA_READY() uint32 { + return (volatile.LoadUint32(&o.ECDSA_CONF.Reg) & 0x4) >> 2 +} + +// PCR.IOMUX_CONF: IOMUX configuration register +func (o *PCR_Type) SetIOMUX_CONF_IOMUX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.IOMUX_CONF.Reg, volatile.LoadUint32(&o.IOMUX_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetIOMUX_CONF_IOMUX_CLK_EN() uint32 { + return volatile.LoadUint32(&o.IOMUX_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetIOMUX_CONF_IOMUX_RST_EN(value uint32) { + volatile.StoreUint32(&o.IOMUX_CONF.Reg, volatile.LoadUint32(&o.IOMUX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetIOMUX_CONF_IOMUX_RST_EN() uint32 { + return (volatile.LoadUint32(&o.IOMUX_CONF.Reg) & 0x2) >> 1 +} + +// PCR.IOMUX_CLK_CONF: IOMUX_CLK configuration register +func (o *PCR_Type) SetIOMUX_CLK_CONF_IOMUX_FUNC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.IOMUX_CLK_CONF.Reg, volatile.LoadUint32(&o.IOMUX_CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *PCR_Type) GetIOMUX_CLK_CONF_IOMUX_FUNC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IOMUX_CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *PCR_Type) SetIOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.IOMUX_CLK_CONF.Reg, volatile.LoadUint32(&o.IOMUX_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *PCR_Type) GetIOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.IOMUX_CLK_CONF.Reg) & 0x400000) >> 22 +} + +// PCR.MEM_MONITOR_CONF: MEM_MONITOR configuration register +func (o *PCR_Type) SetMEM_MONITOR_CONF_MEM_MONITOR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MEM_MONITOR_CONF.Reg, volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetMEM_MONITOR_CONF_MEM_MONITOR_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetMEM_MONITOR_CONF_MEM_MONITOR_RST_EN(value uint32) { + volatile.StoreUint32(&o.MEM_MONITOR_CONF.Reg, volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetMEM_MONITOR_CONF_MEM_MONITOR_RST_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetMEM_MONITOR_CONF_MEM_MONITOR_READY(value uint32) { + volatile.StoreUint32(&o.MEM_MONITOR_CONF.Reg, volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetMEM_MONITOR_CONF_MEM_MONITOR_READY() uint32 { + return (volatile.LoadUint32(&o.MEM_MONITOR_CONF.Reg) & 0x4) >> 2 +} + +// PCR.REGDMA_CONF: REGDMA configuration register +func (o *PCR_Type) SetREGDMA_CONF_REGDMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetREGDMA_CONF_REGDMA_CLK_EN() uint32 { + return volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetREGDMA_CONF_REGDMA_RST_EN(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetREGDMA_CONF_REGDMA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x2) >> 1 +} + +// PCR.TRACE_CONF: TRACE configuration register +func (o *PCR_Type) SetTRACE_CONF_TRACE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TRACE_CONF.Reg, volatile.LoadUint32(&o.TRACE_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetTRACE_CONF_TRACE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.TRACE_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetTRACE_CONF_TRACE_RST_EN(value uint32) { + volatile.StoreUint32(&o.TRACE_CONF.Reg, volatile.LoadUint32(&o.TRACE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTRACE_CONF_TRACE_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TRACE_CONF.Reg) & 0x2) >> 1 +} + +// PCR.ASSIST_CONF: ASSIST configuration register +func (o *PCR_Type) SetASSIST_CONF_ASSIST_CLK_EN(value uint32) { + volatile.StoreUint32(&o.ASSIST_CONF.Reg, volatile.LoadUint32(&o.ASSIST_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetASSIST_CONF_ASSIST_CLK_EN() uint32 { + return volatile.LoadUint32(&o.ASSIST_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetASSIST_CONF_ASSIST_RST_EN(value uint32) { + volatile.StoreUint32(&o.ASSIST_CONF.Reg, volatile.LoadUint32(&o.ASSIST_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetASSIST_CONF_ASSIST_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ASSIST_CONF.Reg) & 0x2) >> 1 +} + +// PCR.CACHE_CONF: CACHE configuration register +func (o *PCR_Type) SetCACHE_CONF_CACHE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF.Reg, volatile.LoadUint32(&o.CACHE_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetCACHE_CONF_CACHE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CACHE_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetCACHE_CONF_CACHE_RST_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF.Reg, volatile.LoadUint32(&o.CACHE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetCACHE_CONF_CACHE_RST_EN() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF.Reg) & 0x2) >> 1 +} + +// PCR.MODEM_CONF: MODEM_APB configuration register +func (o *PCR_Type) SetMODEM_CONF_MODEM_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.MODEM_CONF.Reg, volatile.LoadUint32(&o.MODEM_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetMODEM_CONF_MODEM_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.MODEM_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetMODEM_CONF_MODEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MODEM_CONF.Reg, volatile.LoadUint32(&o.MODEM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetMODEM_CONF_MODEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MODEM_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetMODEM_CONF_MODEM_RST_EN(value uint32) { + volatile.StoreUint32(&o.MODEM_CONF.Reg, volatile.LoadUint32(&o.MODEM_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetMODEM_CONF_MODEM_RST_EN() uint32 { + return (volatile.LoadUint32(&o.MODEM_CONF.Reg) & 0x4) >> 2 +} + +// PCR.TIMEOUT_CONF: TIMEOUT configuration register +func (o *PCR_Type) SetTIMEOUT_CONF_CPU_TIMEOUT_RST_EN(value uint32) { + volatile.StoreUint32(&o.TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.TIMEOUT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetTIMEOUT_CONF_CPU_TIMEOUT_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TIMEOUT_CONF.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetTIMEOUT_CONF_HP_TIMEOUT_RST_EN(value uint32) { + volatile.StoreUint32(&o.TIMEOUT_CONF.Reg, volatile.LoadUint32(&o.TIMEOUT_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetTIMEOUT_CONF_HP_TIMEOUT_RST_EN() uint32 { + return (volatile.LoadUint32(&o.TIMEOUT_CONF.Reg) & 0x4) >> 2 +} + +// PCR.SYSCLK_CONF: SYSCLK configuration register +func (o *PCR_Type) SetSYSCLK_CONF_LS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetSYSCLK_CONF_LS_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetSYSCLK_CONF_HS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetSYSCLK_CONF_HS_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0xff00) >> 8 +} +func (o *PCR_Type) SetSYSCLK_CONF_SOC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x30000)|value<<16) +} +func (o *PCR_Type) GetSYSCLK_CONF_SOC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x30000) >> 16 +} +func (o *PCR_Type) SetSYSCLK_CONF_CLK_XTAL_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x7f000000)|value<<24) +} +func (o *PCR_Type) GetSYSCLK_CONF_CLK_XTAL_FREQ() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x7f000000) >> 24 +} + +// PCR.CPU_WAITI_CONF: CPU_WAITI configuration register +func (o *PCR_Type) SetCPU_WAITI_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x3)|value) +} +func (o *PCR_Type) GetCPU_WAITI_CONF_CPUPERIOD_SEL() uint32 { + return volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x3 +} +func (o *PCR_Type) SetCPU_WAITI_CONF_PLL_FREQ_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetCPU_WAITI_CONF_PLL_FREQ_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetCPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetCPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetCPU_WAITI_CONF_CPU_WAITI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *PCR_Type) GetCPU_WAITI_CONF_CPU_WAITI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0xf0) >> 4 +} + +// PCR.CPU_FREQ_CONF: CPU_FREQ configuration register +func (o *PCR_Type) SetCPU_FREQ_CONF_CPU_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_FREQ_CONF.Reg, volatile.LoadUint32(&o.CPU_FREQ_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetCPU_FREQ_CONF_CPU_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CPU_FREQ_CONF.Reg) & 0xff +} + +// PCR.AHB_FREQ_CONF: AHB_FREQ configuration register +func (o *PCR_Type) SetAHB_FREQ_CONF_AHB_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.AHB_FREQ_CONF.Reg, volatile.LoadUint32(&o.AHB_FREQ_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetAHB_FREQ_CONF_AHB_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.AHB_FREQ_CONF.Reg) & 0xff +} + +// PCR.APB_FREQ_CONF: APB_FREQ configuration register +func (o *PCR_Type) SetAPB_FREQ_CONF_APB_DECREASE_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.APB_FREQ_CONF.Reg, volatile.LoadUint32(&o.APB_FREQ_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetAPB_FREQ_CONF_APB_DECREASE_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.APB_FREQ_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetAPB_FREQ_CONF_APB_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.APB_FREQ_CONF.Reg, volatile.LoadUint32(&o.APB_FREQ_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetAPB_FREQ_CONF_APB_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.APB_FREQ_CONF.Reg) & 0xff00) >> 8 +} + +// PCR.SYSCLK_FREQ_QUERY_0: SYSCLK frequency query 0 register +func (o *PCR_Type) SetSYSCLK_FREQ_QUERY_0_FOSC_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_FREQ_QUERY_0.Reg, volatile.LoadUint32(&o.SYSCLK_FREQ_QUERY_0.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetSYSCLK_FREQ_QUERY_0_FOSC_FREQ() uint32 { + return volatile.LoadUint32(&o.SYSCLK_FREQ_QUERY_0.Reg) & 0xff +} +func (o *PCR_Type) SetSYSCLK_FREQ_QUERY_0_PLL_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_FREQ_QUERY_0.Reg, volatile.LoadUint32(&o.SYSCLK_FREQ_QUERY_0.Reg)&^(0x3ff00)|value<<8) +} +func (o *PCR_Type) GetSYSCLK_FREQ_QUERY_0_PLL_FREQ() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_FREQ_QUERY_0.Reg) & 0x3ff00) >> 8 +} + +// PCR.PLL_DIV_CLK_EN: SPLL DIV clock-gating configuration register +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_240M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_240M_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x1 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_160M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_160M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_120M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_120M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_80M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_80M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_48M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x10)|value<<4) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_48M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x10) >> 4 +} +func (o *PCR_Type) SetPLL_DIV_CLK_EN_PLL_40M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PLL_DIV_CLK_EN.Reg, volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg)&^(0x20)|value<<5) +} +func (o *PCR_Type) GetPLL_DIV_CLK_EN_PLL_40M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PLL_DIV_CLK_EN.Reg) & 0x20) >> 5 +} + +// PCR.CTRL_CLK_OUT_EN: CLK_OUT_EN configuration register +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK8_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK8_OEN() uint32 { + return volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x1 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK16_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK16_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x2) >> 1 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK32_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x4)|value<<2) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK32_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x4) >> 2 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK_ADC_INF_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x8)|value<<3) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK_ADC_INF_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x8) >> 3 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK_DFM_INF_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x10)|value<<4) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK_DFM_INF_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x10) >> 4 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK_SDM_MOD_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x20)|value<<5) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK_SDM_MOD_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x20) >> 5 +} +func (o *PCR_Type) SetCTRL_CLK_OUT_EN_CLK_XTAL_OEN(value uint32) { + volatile.StoreUint32(&o.CTRL_CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg)&^(0x40)|value<<6) +} +func (o *PCR_Type) GetCTRL_CLK_OUT_EN_CLK_XTAL_OEN() uint32 { + return (volatile.LoadUint32(&o.CTRL_CLK_OUT_EN.Reg) & 0x40) >> 6 +} + +// PCR.CTRL_TICK_CONF: TICK configuration register +func (o *PCR_Type) SetCTRL_TICK_CONF_XTAL_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL_TICK_CONF.Reg, volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetCTRL_TICK_CONF_XTAL_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetCTRL_TICK_CONF_FOSC_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL_TICK_CONF.Reg, volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetCTRL_TICK_CONF_FOSC_TICK_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg) & 0xff00) >> 8 +} +func (o *PCR_Type) SetCTRL_TICK_CONF_TICK_ENABLE(value uint32) { + volatile.StoreUint32(&o.CTRL_TICK_CONF.Reg, volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *PCR_Type) GetCTRL_TICK_CONF_TICK_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg) & 0x10000) >> 16 +} +func (o *PCR_Type) SetCTRL_TICK_CONF_RST_TICK_CNT(value uint32) { + volatile.StoreUint32(&o.CTRL_TICK_CONF.Reg, volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *PCR_Type) GetCTRL_TICK_CONF_RST_TICK_CNT() uint32 { + return (volatile.LoadUint32(&o.CTRL_TICK_CONF.Reg) & 0x20000) >> 17 +} + +// PCR.CTRL_32K_CONF: 32KHz clock configuration register +func (o *PCR_Type) SetCTRL_32K_CONF_CLK_32K_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL_32K_CONF.Reg, volatile.LoadUint32(&o.CTRL_32K_CONF.Reg)&^(0x3)|value) +} +func (o *PCR_Type) GetCTRL_32K_CONF_CLK_32K_SEL() uint32 { + return volatile.LoadUint32(&o.CTRL_32K_CONF.Reg) & 0x3 +} +func (o *PCR_Type) SetCTRL_32K_CONF__32K_MODEM_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL_32K_CONF.Reg, volatile.LoadUint32(&o.CTRL_32K_CONF.Reg)&^(0xc)|value<<2) +} +func (o *PCR_Type) GetCTRL_32K_CONF__32K_MODEM_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL_32K_CONF.Reg) & 0xc) >> 2 +} + +// PCR.SRAM_POWER_CONF_0: HP SRAM/ROM configuration register +func (o *PCR_Type) SetSRAM_POWER_CONF_0_ROM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF_0.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF_0.Reg)&^(0x6000)|value<<13) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_0_ROM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF_0.Reg) & 0x6000) >> 13 +} +func (o *PCR_Type) SetSRAM_POWER_CONF_0_ROM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF_0.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF_0.Reg)&^(0x18000)|value<<15) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_0_ROM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF_0.Reg) & 0x18000) >> 15 +} +func (o *PCR_Type) SetSRAM_POWER_CONF_0_ROM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF_0.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF_0.Reg)&^(0x60000)|value<<17) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_0_ROM_CLKGATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF_0.Reg) & 0x60000) >> 17 +} + +// PCR.SRAM_POWER_CONF_1: HP SRAM/ROM configuration register +func (o *PCR_Type) SetSRAM_POWER_CONF_1_SRAM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF_1.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF_1.Reg)&^(0x1f)|value) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_1_SRAM_FORCE_PU() uint32 { + return volatile.LoadUint32(&o.SRAM_POWER_CONF_1.Reg) & 0x1f +} +func (o *PCR_Type) SetSRAM_POWER_CONF_1_SRAM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF_1.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF_1.Reg)&^(0x7c00)|value<<10) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_1_SRAM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF_1.Reg) & 0x7c00) >> 10 +} +func (o *PCR_Type) SetSRAM_POWER_CONF_1_SRAM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SRAM_POWER_CONF_1.Reg, volatile.LoadUint32(&o.SRAM_POWER_CONF_1.Reg)&^(0x3e000000)|value<<25) +} +func (o *PCR_Type) GetSRAM_POWER_CONF_1_SRAM_CLKGATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.SRAM_POWER_CONF_1.Reg) & 0x3e000000) >> 25 +} + +// PCR.SEC_CONF: xxxx +func (o *PCR_Type) SetSEC_CONF_SEC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SEC_CONF.Reg, volatile.LoadUint32(&o.SEC_CONF.Reg)&^(0x3)|value) +} +func (o *PCR_Type) GetSEC_CONF_SEC_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.SEC_CONF.Reg) & 0x3 +} + +// PCR.ADC_INV_PHASE_CONF: xxxx +func (o *PCR_Type) SetADC_INV_PHASE_CONF_CLK_ADC_INV_PHASE_ENA(value uint32) { + volatile.StoreUint32(&o.ADC_INV_PHASE_CONF.Reg, volatile.LoadUint32(&o.ADC_INV_PHASE_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetADC_INV_PHASE_CONF_CLK_ADC_INV_PHASE_ENA() uint32 { + return volatile.LoadUint32(&o.ADC_INV_PHASE_CONF.Reg) & 0x1 +} + +// PCR.SDM_INV_PHASE_CONF: xxxx +func (o *PCR_Type) SetSDM_INV_PHASE_CONF_CLK_SDM_INV_PHASE_ENA(value uint32) { + volatile.StoreUint32(&o.SDM_INV_PHASE_CONF.Reg, volatile.LoadUint32(&o.SDM_INV_PHASE_CONF.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetSDM_INV_PHASE_CONF_CLK_SDM_INV_PHASE_ENA() uint32 { + return volatile.LoadUint32(&o.SDM_INV_PHASE_CONF.Reg) & 0x1 +} +func (o *PCR_Type) SetSDM_INV_PHASE_CONF_CLK_SDM_INV_PHASE_SEL(value uint32) { + volatile.StoreUint32(&o.SDM_INV_PHASE_CONF.Reg, volatile.LoadUint32(&o.SDM_INV_PHASE_CONF.Reg)&^(0xe)|value<<1) +} +func (o *PCR_Type) GetSDM_INV_PHASE_CONF_CLK_SDM_INV_PHASE_SEL() uint32 { + return (volatile.LoadUint32(&o.SDM_INV_PHASE_CONF.Reg) & 0xe) >> 1 +} + +// PCR.BUS_CLK_UPDATE: xxxx +func (o *PCR_Type) SetBUS_CLK_UPDATE_BUS_CLOCK_UPDATE(value uint32) { + volatile.StoreUint32(&o.BUS_CLK_UPDATE.Reg, volatile.LoadUint32(&o.BUS_CLK_UPDATE.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetBUS_CLK_UPDATE_BUS_CLOCK_UPDATE() uint32 { + return volatile.LoadUint32(&o.BUS_CLK_UPDATE.Reg) & 0x1 +} + +// PCR.SAR_CLK_DIV: xxxx +func (o *PCR_Type) SetSAR_CLK_DIV_SAR2_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SAR_CLK_DIV.Reg, volatile.LoadUint32(&o.SAR_CLK_DIV.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetSAR_CLK_DIV_SAR2_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.SAR_CLK_DIV.Reg) & 0xff +} +func (o *PCR_Type) SetSAR_CLK_DIV_SAR1_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SAR_CLK_DIV.Reg, volatile.LoadUint32(&o.SAR_CLK_DIV.Reg)&^(0xff00)|value<<8) +} +func (o *PCR_Type) GetSAR_CLK_DIV_SAR1_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SAR_CLK_DIV.Reg) & 0xff00) >> 8 +} + +// PCR.PWDET_SAR_CLK_CONF: xxxx +func (o *PCR_Type) SetPWDET_SAR_CLK_CONF_PWDET_SAR_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PWDET_SAR_CLK_CONF.Reg, volatile.LoadUint32(&o.PWDET_SAR_CLK_CONF.Reg)&^(0xff)|value) +} +func (o *PCR_Type) GetPWDET_SAR_CLK_CONF_PWDET_SAR_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PWDET_SAR_CLK_CONF.Reg) & 0xff +} +func (o *PCR_Type) SetPWDET_SAR_CLK_CONF_PWDET_SAR_READER_EN(value uint32) { + volatile.StoreUint32(&o.PWDET_SAR_CLK_CONF.Reg, volatile.LoadUint32(&o.PWDET_SAR_CLK_CONF.Reg)&^(0x100)|value<<8) +} +func (o *PCR_Type) GetPWDET_SAR_CLK_CONF_PWDET_SAR_READER_EN() uint32 { + return (volatile.LoadUint32(&o.PWDET_SAR_CLK_CONF.Reg) & 0x100) >> 8 +} + +// PCR.RESET_EVENT_BYPASS: reset event bypass backdoor configuration register +func (o *PCR_Type) SetRESET_EVENT_BYPASS_APM(value uint32) { + volatile.StoreUint32(&o.RESET_EVENT_BYPASS.Reg, volatile.LoadUint32(&o.RESET_EVENT_BYPASS.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetRESET_EVENT_BYPASS_APM() uint32 { + return volatile.LoadUint32(&o.RESET_EVENT_BYPASS.Reg) & 0x1 +} +func (o *PCR_Type) SetRESET_EVENT_BYPASS(value uint32) { + volatile.StoreUint32(&o.RESET_EVENT_BYPASS.Reg, volatile.LoadUint32(&o.RESET_EVENT_BYPASS.Reg)&^(0x2)|value<<1) +} +func (o *PCR_Type) GetRESET_EVENT_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RESET_EVENT_BYPASS.Reg) & 0x2) >> 1 +} + +// PCR.FPGA_DEBUG: fpga debug register +func (o *PCR_Type) SetFPGA_DEBUG(value uint32) { + volatile.StoreUint32(&o.FPGA_DEBUG.Reg, value) +} +func (o *PCR_Type) GetFPGA_DEBUG() uint32 { + return volatile.LoadUint32(&o.FPGA_DEBUG.Reg) +} + +// PCR.CLOCK_GATE: PCR clock gating configure register +func (o *PCR_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *PCR_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// PCR.DATE: Date register. +func (o *PCR_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *PCR_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// PMU Peripheral +type PMU_Type struct { + HP_ACTIVE_DIG_POWER volatile.Register32 // 0x0 + HP_ACTIVE_ICG_HP_FUNC volatile.Register32 // 0x4 + HP_ACTIVE_ICG_HP_APB volatile.Register32 // 0x8 + HP_ACTIVE_ICG_MODEM volatile.Register32 // 0xC + HP_ACTIVE_HP_SYS_CNTL volatile.Register32 // 0x10 + HP_ACTIVE_HP_CK_POWER volatile.Register32 // 0x14 + HP_ACTIVE_BIAS volatile.Register32 // 0x18 + HP_ACTIVE_BACKUP volatile.Register32 // 0x1C + HP_ACTIVE_BACKUP_CLK volatile.Register32 // 0x20 + HP_ACTIVE_SYSCLK volatile.Register32 // 0x24 + HP_ACTIVE_HP_REGULATOR0 volatile.Register32 // 0x28 + HP_ACTIVE_HP_REGULATOR1 volatile.Register32 // 0x2C + HP_ACTIVE_XTAL volatile.Register32 // 0x30 + HP_MODEM_DIG_POWER volatile.Register32 // 0x34 + HP_MODEM_ICG_HP_FUNC volatile.Register32 // 0x38 + HP_MODEM_ICG_HP_APB volatile.Register32 // 0x3C + HP_MODEM_ICG_MODEM volatile.Register32 // 0x40 + HP_MODEM_HP_SYS_CNTL volatile.Register32 // 0x44 + HP_MODEM_HP_CK_POWER volatile.Register32 // 0x48 + HP_MODEM_BIAS volatile.Register32 // 0x4C + HP_MODEM_BACKUP volatile.Register32 // 0x50 + HP_MODEM_BACKUP_CLK volatile.Register32 // 0x54 + HP_MODEM_SYSCLK volatile.Register32 // 0x58 + HP_MODEM_HP_REGULATOR0 volatile.Register32 // 0x5C + HP_MODEM_HP_REGULATOR1 volatile.Register32 // 0x60 + HP_MODEM_XTAL volatile.Register32 // 0x64 + HP_SLEEP_DIG_POWER volatile.Register32 // 0x68 + HP_SLEEP_ICG_HP_FUNC volatile.Register32 // 0x6C + HP_SLEEP_ICG_HP_APB volatile.Register32 // 0x70 + HP_SLEEP_ICG_MODEM volatile.Register32 // 0x74 + HP_SLEEP_HP_SYS_CNTL volatile.Register32 // 0x78 + HP_SLEEP_HP_CK_POWER volatile.Register32 // 0x7C + HP_SLEEP_BIAS volatile.Register32 // 0x80 + HP_SLEEP_BACKUP volatile.Register32 // 0x84 + HP_SLEEP_BACKUP_CLK volatile.Register32 // 0x88 + HP_SLEEP_SYSCLK volatile.Register32 // 0x8C + HP_SLEEP_HP_REGULATOR0 volatile.Register32 // 0x90 + HP_SLEEP_HP_REGULATOR1 volatile.Register32 // 0x94 + HP_SLEEP_XTAL volatile.Register32 // 0x98 + HP_SLEEP_LP_REGULATOR0 volatile.Register32 // 0x9C + HP_SLEEP_LP_REGULATOR1 volatile.Register32 // 0xA0 + HP_SLEEP_LP_DCDC_RESERVE volatile.Register32 // 0xA4 + HP_SLEEP_LP_DIG_POWER volatile.Register32 // 0xA8 + HP_SLEEP_LP_CK_POWER volatile.Register32 // 0xAC + LP_SLEEP_LP_BIAS_RESERVE volatile.Register32 // 0xB0 + LP_SLEEP_LP_REGULATOR0 volatile.Register32 // 0xB4 + LP_SLEEP_LP_REGULATOR1 volatile.Register32 // 0xB8 + LP_SLEEP_XTAL volatile.Register32 // 0xBC + LP_SLEEP_LP_DIG_POWER volatile.Register32 // 0xC0 + LP_SLEEP_LP_CK_POWER volatile.Register32 // 0xC4 + LP_SLEEP_BIAS volatile.Register32 // 0xC8 + IMM_HP_CK_POWER volatile.Register32 // 0xCC + IMM_SLEEP_SYSCLK volatile.Register32 // 0xD0 + IMM_HP_FUNC_ICG volatile.Register32 // 0xD4 + IMM_HP_APB_ICG volatile.Register32 // 0xD8 + IMM_MODEM_ICG volatile.Register32 // 0xDC + IMM_LP_ICG volatile.Register32 // 0xE0 + IMM_PAD_HOLD_ALL volatile.Register32 // 0xE4 + IMM_I2C_ISO volatile.Register32 // 0xE8 + POWER_WAIT_TIMER0 volatile.Register32 // 0xEC + POWER_WAIT_TIMER1 volatile.Register32 // 0xF0 + POWER_PD_TOP_CNTL volatile.Register32 // 0xF4 + POWER_PD_HPAON_CNTL volatile.Register32 // 0xF8 + POWER_PD_HPCPU_CNTL volatile.Register32 // 0xFC + POWER_PD_HPPERI_RESERVE volatile.Register32 // 0x100 + POWER_PD_HPWIFI_CNTL volatile.Register32 // 0x104 + POWER_PD_LPPERI_CNTL volatile.Register32 // 0x108 + POWER_PD_MEM_CNTL volatile.Register32 // 0x10C + POWER_PD_MEM_MASK volatile.Register32 // 0x110 + POWER_HP_PAD volatile.Register32 // 0x114 + POWER_VDD_SPI_CNTL volatile.Register32 // 0x118 + POWER_CK_WAIT_CNTL volatile.Register32 // 0x11C + SLP_WAKEUP_CNTL0 volatile.Register32 // 0x120 + SLP_WAKEUP_CNTL1 volatile.Register32 // 0x124 + SLP_WAKEUP_CNTL2 volatile.Register32 // 0x128 + SLP_WAKEUP_CNTL3 volatile.Register32 // 0x12C + SLP_WAKEUP_CNTL4 volatile.Register32 // 0x130 + SLP_WAKEUP_CNTL5 volatile.Register32 // 0x134 + SLP_WAKEUP_CNTL6 volatile.Register32 // 0x138 + SLP_WAKEUP_CNTL7 volatile.Register32 // 0x13C + SLP_WAKEUP_STATUS0 volatile.Register32 // 0x140 + SLP_WAKEUP_STATUS1 volatile.Register32 // 0x144 + HP_CK_POWERON volatile.Register32 // 0x148 + HP_CK_CNTL volatile.Register32 // 0x14C + POR_STATUS volatile.Register32 // 0x150 + RF_PWC volatile.Register32 // 0x154 + VDDBAT_CFG volatile.Register32 // 0x158 + BACKUP_CFG volatile.Register32 // 0x15C + INT_RAW volatile.Register32 // 0x160 + HP_INT_ST volatile.Register32 // 0x164 + HP_INT_ENA volatile.Register32 // 0x168 + HP_INT_CLR volatile.Register32 // 0x16C + LP_INT_RAW volatile.Register32 // 0x170 + LP_INT_ST volatile.Register32 // 0x174 + LP_INT_ENA volatile.Register32 // 0x178 + LP_INT_CLR volatile.Register32 // 0x17C + LP_CPU_PWR0 volatile.Register32 // 0x180 + LP_CPU_PWR1 volatile.Register32 // 0x184 + HP_LP_CPU_COMM volatile.Register32 // 0x188 + HP_REGULATOR_CFG volatile.Register32 // 0x18C + MAIN_STATE volatile.Register32 // 0x190 + PWR_STATE volatile.Register32 // 0x194 + CLK_STATE0 volatile.Register32 // 0x198 + CLK_STATE1 volatile.Register32 // 0x19C + CLK_STATE2 volatile.Register32 // 0x1A0 + VDD_SPI_STATUS volatile.Register32 // 0x1A4 + _ [596]byte + DATE volatile.Register32 // 0x3FC +} + +// PMU.HP_ACTIVE_DIG_POWER: need_des +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_ACTIVE_ICG_HP_FUNC: need_des +func (o *PMU_Type) SetHP_ACTIVE_ICG_HP_FUNC(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_ICG_HP_FUNC.Reg, value) +} +func (o *PMU_Type) GetHP_ACTIVE_ICG_HP_FUNC() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_ICG_HP_FUNC.Reg) +} + +// PMU.HP_ACTIVE_ICG_HP_APB: need_des +func (o *PMU_Type) SetHP_ACTIVE_ICG_HP_APB(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_ICG_HP_APB.Reg, value) +} +func (o *PMU_Type) GetHP_ACTIVE_ICG_HP_APB() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_ICG_HP_APB.Reg) +} + +// PMU.HP_ACTIVE_ICG_MODEM: need_des +func (o *PMU_Type) SetHP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_ACTIVE_ICG_MODEM.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_ICG_MODEM.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_ACTIVE_HP_SYS_CNTL: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_ACTIVE_HP_CK_POWER: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x40000000) >> 30 +} + +// PMU.HP_ACTIVE_BIAS: need_des +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_TRX(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_TRX() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_ACTIVE_BACKUP: need_des +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x30)|value<<4) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x30) >> 4 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0xc0)|value<<6) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0xc0) >> 6 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x800)|value<<11) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x800) >> 11 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0xc000)|value<<14) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0xc000) >> 14 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x30000) >> 16 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x700000)|value<<20) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x700000) >> 20 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x40000000) >> 30 +} + +// PMU.HP_ACTIVE_BACKUP_CLK: need_des +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_CLK(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP_CLK.Reg, value) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_CLK() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_BACKUP_CLK.Reg) +} + +// PMU.HP_ACTIVE_SYSCLK: need_des +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_ACTIVE_HP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_POWER_DET_BYPASS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_POWER_DET_BYPASS() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x1 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x1f0)|value<<4) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x1f0) >> 4 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x3e00)|value<<9) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x3e00) >> 9 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x780000)|value<<19) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x780000) >> 19 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_ACTIVE_HP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg)&^(0xffffff00)|value<<8) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg) & 0xffffff00) >> 8 +} + +// PMU.HP_ACTIVE_XTAL: need_des +func (o *PMU_Type) SetHP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_XTAL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_MODEM_DIG_POWER: need_des +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_MODEM_ICG_HP_FUNC: need_des +func (o *PMU_Type) SetHP_MODEM_ICG_HP_FUNC(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_ICG_HP_FUNC.Reg, value) +} +func (o *PMU_Type) GetHP_MODEM_ICG_HP_FUNC() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_ICG_HP_FUNC.Reg) +} + +// PMU.HP_MODEM_ICG_HP_APB: need_des +func (o *PMU_Type) SetHP_MODEM_ICG_HP_APB(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_ICG_HP_APB.Reg, value) +} +func (o *PMU_Type) GetHP_MODEM_ICG_HP_APB() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_ICG_HP_APB.Reg) +} + +// PMU.HP_MODEM_ICG_MODEM: need_des +func (o *PMU_Type) SetHP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_MODEM_ICG_MODEM.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_ICG_MODEM.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_MODEM_HP_SYS_CNTL: need_des +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_MODEM_HP_CK_POWER: need_des +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x40000000) >> 30 +} + +// PMU.HP_MODEM_BIAS: need_des +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_XPD_TRX(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_XPD_TRX() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_PD_CUR(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_MODEM_BACKUP: need_des +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x30)|value<<4) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x30) >> 4 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x800)|value<<11) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x800) >> 11 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0xc000)|value<<14) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0xc000) >> 14 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x700000)|value<<20) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x700000) >> 20 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_MODEM_BACKUP_CLK: need_des +func (o *PMU_Type) SetHP_MODEM_BACKUP_CLK(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP_CLK.Reg, value) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_CLK() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_BACKUP_CLK.Reg) +} + +// PMU.HP_MODEM_SYSCLK: need_des +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_MODEM_HP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_POWER_DET_BYPASS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_POWER_DET_BYPASS() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x1 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x780000)|value<<19) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x780000) >> 19 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_MODEM_HP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR1.Reg)&^(0xffffff00)|value<<8) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR1.Reg) & 0xffffff00) >> 8 +} + +// PMU.HP_MODEM_XTAL: need_des +func (o *PMU_Type) SetHP_MODEM_XTAL_HP_MODEM_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_XTAL.Reg, volatile.LoadUint32(&o.HP_MODEM_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_MODEM_XTAL_HP_MODEM_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_DIG_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_ICG_HP_FUNC: need_des +func (o *PMU_Type) SetHP_SLEEP_ICG_HP_FUNC(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_ICG_HP_FUNC.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_ICG_HP_FUNC() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_ICG_HP_FUNC.Reg) +} + +// PMU.HP_SLEEP_ICG_HP_APB: need_des +func (o *PMU_Type) SetHP_SLEEP_ICG_HP_APB(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_ICG_HP_APB.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_ICG_HP_APB() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_ICG_HP_APB.Reg) +} + +// PMU.HP_SLEEP_ICG_MODEM: need_des +func (o *PMU_Type) SetHP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_SLEEP_ICG_MODEM.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_ICG_MODEM.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_SLEEP_HP_SYS_CNTL: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_SLEEP_HP_CK_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x40000000) >> 30 +} + +// PMU.HP_SLEEP_BIAS: need_des +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_XPD_TRX(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_XPD_TRX() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_PD_CUR(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_BACKUP: need_des +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0xc0)|value<<6) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0xc0) >> 6 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x300)|value<<8) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x300) >> 8 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x30000) >> 16 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0xc0000)|value<<18) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0xc0000) >> 18 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x1c000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x1c000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_BACKUP_CLK: need_des +func (o *PMU_Type) SetHP_SLEEP_BACKUP_CLK(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP_CLK.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_CLK() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_BACKUP_CLK.Reg) +} + +// PMU.HP_SLEEP_SYSCLK: need_des +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_SLEEP_HP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_POWER_DET_BYPASS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_POWER_DET_BYPASS() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x1 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x780000)|value<<19) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x780000) >> 19 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_SLEEP_HP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg)&^(0xffffff00)|value<<8) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg) & 0xffffff00) >> 8 +} + +// PMU.HP_SLEEP_XTAL: need_des +func (o *PMU_Type) SetHP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_XTAL.Reg, volatile.LoadUint32(&o.HP_SLEEP_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_LP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_SLEEP_LP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg) & 0xf0000000) >> 28 +} + +// PMU.HP_SLEEP_LP_DCDC_RESERVE: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_DCDC_RESERVE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DCDC_RESERVE.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DCDC_RESERVE() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_LP_DCDC_RESERVE.Reg) +} + +// PMU.HP_SLEEP_LP_DIG_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x30000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x30000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_LP_CK_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_LP_BIAS_RESERVE: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_BIAS_RESERVE(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_BIAS_RESERVE.Reg, value) +} +func (o *PMU_Type) GetLP_SLEEP_LP_BIAS_RESERVE() uint32 { + return volatile.LoadUint32(&o.LP_SLEEP_LP_BIAS_RESERVE.Reg) +} + +// PMU.LP_SLEEP_LP_REGULATOR0: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.LP_SLEEP_LP_REGULATOR1: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg) & 0xf0000000) >> 28 +} + +// PMU.LP_SLEEP_XTAL: need_des +func (o *PMU_Type) SetLP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_XTAL.Reg, volatile.LoadUint32(&o.LP_SLEEP_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_LP_DIG_POWER: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x30000000)|value<<28) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x30000000) >> 28 +} +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_LP_CK_POWER: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_BIAS: need_des +func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_PD_CUR(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_SLEEP_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_HP_CK_POWER: need_des +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG() uint32 { + return volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x1 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x40)|value<<6) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x40) >> 6 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_SLEEP_SYSCLK: need_des +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_HP_FUNC_ICG: need_des +func (o *PMU_Type) SetIMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.IMM_HP_FUNC_ICG.Reg, volatile.LoadUint32(&o.IMM_HP_FUNC_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_FUNC_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_HP_APB_ICG: need_des +func (o *PMU_Type) SetIMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN(value uint32) { + volatile.StoreUint32(&o.IMM_HP_APB_ICG.Reg, volatile.LoadUint32(&o.IMM_HP_APB_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_APB_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_MODEM_ICG: need_des +func (o *PMU_Type) SetIMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN(value uint32) { + volatile.StoreUint32(&o.IMM_MODEM_ICG.Reg, volatile.LoadUint32(&o.IMM_MODEM_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_MODEM_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_LP_ICG: need_des +func (o *PMU_Type) SetIMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_LP_ICG.Reg, volatile.LoadUint32(&o.IMM_LP_ICG.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_LP_ICG.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_LP_ICG.Reg, volatile.LoadUint32(&o.IMM_LP_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_LP_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_PAD_HOLD_ALL: need_des +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_I2C_ISO: need_des +func (o *PMU_Type) SetIMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.IMM_I2C_ISO.Reg, volatile.LoadUint32(&o.IMM_I2C_ISO.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_I2C_ISO.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_I2C_ISO_TIE_LOW_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.IMM_I2C_ISO.Reg, volatile.LoadUint32(&o.IMM_I2C_ISO.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_I2C_ISO_TIE_LOW_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_I2C_ISO.Reg) & 0x80000000) >> 31 +} + +// PMU.POWER_WAIT_TIMER0: need_des +func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0x3fe0)|value<<5) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0x3fe0) >> 5 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0x7fc000)|value<<14) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0x7fc000) >> 14 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0xff800000)|value<<23) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0xff800000) >> 23 +} + +// PMU.POWER_WAIT_TIMER1: need_des +func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0xfe00)|value<<9) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0xfe00) >> 9 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0x7f0000)|value<<16) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0x7f0000) >> 16 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0xff800000)|value<<23) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0xff800000) >> 23 +} + +// PMU.POWER_PD_TOP_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_PD_TOP_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x7c0)|value<<6) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_PD_TOP_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x7c0) >> 6 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_PD_TOP_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_PD_TOP_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_HPAON_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_FORCE_HP_AON_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_PD_HP_AON_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0x7c0)|value<<6) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_PD_HP_AON_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0x7c0) >> 6 +} +func (o *PMU_Type) SetPOWER_PD_HPAON_CNTL_PD_HP_AON_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPAON_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_HPAON_CNTL_PD_HP_AON_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPAON_CNTL.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_HPCPU_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_PD_HP_CPU_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0x7c0)|value<<6) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_PD_HP_CPU_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0x7c0) >> 6 +} +func (o *PMU_Type) SetPOWER_PD_HPCPU_CNTL_PD_HP_CPU_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPCPU_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_HPCPU_CNTL_PD_HP_CPU_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPCPU_CNTL.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_HPPERI_RESERVE: need_des +func (o *PMU_Type) SetPOWER_PD_HPPERI_RESERVE(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPPERI_RESERVE.Reg, value) +} +func (o *PMU_Type) GetPOWER_PD_HPPERI_RESERVE() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPPERI_RESERVE.Reg) +} + +// PMU.POWER_PD_HPWIFI_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_PD_HP_WIFI_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0x7c0)|value<<6) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_PD_HP_WIFI_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0x7c0) >> 6 +} +func (o *PMU_Type) SetPOWER_PD_HPWIFI_CNTL_PD_HP_WIFI_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPWIFI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_HPWIFI_CNTL_PD_HP_WIFI_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPWIFI_CNTL.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_LPPERI_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x20) >> 5 +} + +// PMU.POWER_PD_MEM_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg)&^(0xf)|value) +} +func (o *PMU_Type) GetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_ISO() uint32 { + return volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg) & 0xf +} +func (o *PMU_Type) SetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg)&^(0xf0)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg) & 0xf0) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg)&^(0xf000000)|value<<24) +} +func (o *PMU_Type) GetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg) & 0xf000000) >> 24 +} +func (o *PMU_Type) SetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetPOWER_PD_MEM_CNTL_FORCE_HP_MEM_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_CNTL.Reg) & 0xf0000000) >> 28 +} + +// PMU.POWER_PD_MEM_MASK: need_des +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM2_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x1f)|value) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM2_PD_MASK() uint32 { + return volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x1f +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM1_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x3e0)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM1_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x3e0) >> 5 +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM0_PD_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x7c00)|value<<10) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM0_PD_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x7c00) >> 10 +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM2_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x3e0000)|value<<17) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM2_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x3e0000) >> 17 +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM1_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0x7c00000)|value<<22) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM1_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0x7c00000) >> 22 +} +func (o *PMU_Type) SetPOWER_PD_MEM_MASK_PD_HP_MEM0_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_MEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_MEM_MASK_PD_HP_MEM0_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_MEM_MASK.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_HP_PAD: need_des +func (o *PMU_Type) SetPOWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL(value uint32) { + volatile.StoreUint32(&o.POWER_HP_PAD.Reg, volatile.LoadUint32(&o.POWER_HP_PAD.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL() uint32 { + return volatile.LoadUint32(&o.POWER_HP_PAD.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_HP_PAD_FORCE_HP_PAD_ISO_ALL(value uint32) { + volatile.StoreUint32(&o.POWER_HP_PAD.Reg, volatile.LoadUint32(&o.POWER_HP_PAD.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_HP_PAD_FORCE_HP_PAD_ISO_ALL() uint32 { + return (volatile.LoadUint32(&o.POWER_HP_PAD.Reg) & 0x2) >> 1 +} + +// PMU.POWER_VDD_SPI_CNTL: need_des +func (o *PMU_Type) SetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_WAIT(value uint32) { + volatile.StoreUint32(&o.POWER_VDD_SPI_CNTL.Reg, volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg)&^(0x1ffc0000)|value<<18) +} +func (o *PMU_Type) GetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_WAIT() uint32 { + return (volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg) & 0x1ffc0000) >> 18 +} +func (o *PMU_Type) SetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_SW(value uint32) { + volatile.StoreUint32(&o.POWER_VDD_SPI_CNTL.Reg, volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg)&^(0x60000000)|value<<29) +} +func (o *PMU_Type) GetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_SW() uint32 { + return (volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg) & 0x60000000) >> 29 +} +func (o *PMU_Type) SetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW(value uint32) { + volatile.StoreUint32(&o.POWER_VDD_SPI_CNTL.Reg, volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetPOWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW() uint32 { + return (volatile.LoadUint32(&o.POWER_VDD_SPI_CNTL.Reg) & 0x80000000) >> 31 +} + +// PMU.POWER_CK_WAIT_CNTL: need_des +func (o *PMU_Type) SetPOWER_CK_WAIT_CNTL_WAIT_XTL_STABLE(value uint32) { + volatile.StoreUint32(&o.POWER_CK_WAIT_CNTL.Reg, volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg)&^(0xffff)|value) +} +func (o *PMU_Type) GetPOWER_CK_WAIT_CNTL_WAIT_XTL_STABLE() uint32 { + return volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg) & 0xffff +} +func (o *PMU_Type) SetPOWER_CK_WAIT_CNTL_WAIT_PLL_STABLE(value uint32) { + volatile.StoreUint32(&o.POWER_CK_WAIT_CNTL.Reg, volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg)&^(0xffff0000)|value<<16) +} +func (o *PMU_Type) GetPOWER_CK_WAIT_CNTL_WAIT_PLL_STABLE() uint32 { + return (volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg) & 0xffff0000) >> 16 +} + +// PMU.SLP_WAKEUP_CNTL0: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL0_SLEEP_REQ(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL0.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL0.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL0_SLEEP_REQ() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL0.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_CNTL1: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg) & 0x7fffffff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL1_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL1_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_CNTL2: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL2(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL2.Reg, value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL2() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL2.Reg) +} + +// PMU.SLP_WAKEUP_CNTL3: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0xff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0xff00)|value<<8) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0xff00) >> 8 +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_SLEEP_PRT_SEL(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_SLEEP_PRT_SEL() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0x30000) >> 16 +} + +// PMU.SLP_WAKEUP_CNTL4: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL4.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL4.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL4.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_CNTL5: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL5.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg)&^(0xfffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg) & 0xfffff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL5.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg)&^(0xff000000)|value<<24) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg) & 0xff000000) >> 24 +} + +// PMU.SLP_WAKEUP_CNTL6: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL6.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg)&^(0xfffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg) & 0xfffff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL6.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg) & 0xc0000000) >> 30 +} + +// PMU.SLP_WAKEUP_CNTL7: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL7_ANA_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL7.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL7.Reg)&^(0xffff0000)|value<<16) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL7_ANA_WAIT_TARGET() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL7.Reg) & 0xffff0000) >> 16 +} + +// PMU.SLP_WAKEUP_STATUS0: need_des +func (o *PMU_Type) SetSLP_WAKEUP_STATUS0(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_STATUS0.Reg, value) +} +func (o *PMU_Type) GetSLP_WAKEUP_STATUS0() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_STATUS0.Reg) +} + +// PMU.SLP_WAKEUP_STATUS1: need_des +func (o *PMU_Type) SetSLP_WAKEUP_STATUS1(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_STATUS1.Reg, value) +} +func (o *PMU_Type) GetSLP_WAKEUP_STATUS1() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_STATUS1.Reg) +} + +// PMU.HP_CK_POWERON: need_des +func (o *PMU_Type) SetHP_CK_POWERON_I2C_POR_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.HP_CK_POWERON.Reg, volatile.LoadUint32(&o.HP_CK_POWERON.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetHP_CK_POWERON_I2C_POR_WAIT_TARGET() uint32 { + return volatile.LoadUint32(&o.HP_CK_POWERON.Reg) & 0xff +} + +// PMU.HP_CK_CNTL: need_des +func (o *PMU_Type) SetHP_CK_CNTL_MODIFY_ICG_CNTL_WAIT(value uint32) { + volatile.StoreUint32(&o.HP_CK_CNTL.Reg, volatile.LoadUint32(&o.HP_CK_CNTL.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetHP_CK_CNTL_MODIFY_ICG_CNTL_WAIT() uint32 { + return volatile.LoadUint32(&o.HP_CK_CNTL.Reg) & 0xff +} +func (o *PMU_Type) SetHP_CK_CNTL_SWITCH_ICG_CNTL_WAIT(value uint32) { + volatile.StoreUint32(&o.HP_CK_CNTL.Reg, volatile.LoadUint32(&o.HP_CK_CNTL.Reg)&^(0xff00)|value<<8) +} +func (o *PMU_Type) GetHP_CK_CNTL_SWITCH_ICG_CNTL_WAIT() uint32 { + return (volatile.LoadUint32(&o.HP_CK_CNTL.Reg) & 0xff00) >> 8 +} + +// PMU.POR_STATUS: need_des +func (o *PMU_Type) SetPOR_STATUS_POR_DONE(value uint32) { + volatile.StoreUint32(&o.POR_STATUS.Reg, volatile.LoadUint32(&o.POR_STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetPOR_STATUS_POR_DONE() uint32 { + return (volatile.LoadUint32(&o.POR_STATUS.Reg) & 0x80000000) >> 31 +} + +// PMU.RF_PWC: need_des +func (o *PMU_Type) SetRF_PWC_XPD_PERIF_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetRF_PWC_XPD_PERIF_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetRF_PWC_XPD_RFTX_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetRF_PWC_XPD_RFTX_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetRF_PWC_XPD_RFRX_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetRF_PWC_XPD_RFRX_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetRF_PWC_XPD_RFPLL(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetRF_PWC_XPD_RFPLL() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetRF_PWC_XPD_FORCE_RFPLL(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetRF_PWC_XPD_FORCE_RFPLL() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x80000000) >> 31 +} + +// PMU.VDDBAT_CFG: need_des +func (o *PMU_Type) SetVDDBAT_CFG_VDDBAT_MODE(value uint32) { + volatile.StoreUint32(&o.VDDBAT_CFG.Reg, volatile.LoadUint32(&o.VDDBAT_CFG.Reg)&^(0x3)|value) +} +func (o *PMU_Type) GetVDDBAT_CFG_VDDBAT_MODE() uint32 { + return volatile.LoadUint32(&o.VDDBAT_CFG.Reg) & 0x3 +} +func (o *PMU_Type) SetVDDBAT_CFG_VDDBAT_SW_UPDATE(value uint32) { + volatile.StoreUint32(&o.VDDBAT_CFG.Reg, volatile.LoadUint32(&o.VDDBAT_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetVDDBAT_CFG_VDDBAT_SW_UPDATE() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_CFG.Reg) & 0x80000000) >> 31 +} + +// PMU.BACKUP_CFG: need_des +func (o *PMU_Type) SetBACKUP_CFG_BACKUP_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.BACKUP_CFG.Reg, volatile.LoadUint32(&o.BACKUP_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetBACKUP_CFG_BACKUP_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.BACKUP_CFG.Reg) & 0x80000000) >> 31 +} + +// PMU.INT_RAW: need_des +func (o *PMU_Type) SetINT_RAW_LP_CPU_EXC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetINT_RAW_LP_CPU_EXC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetINT_RAW_SDIO_IDLE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetINT_RAW_SDIO_IDLE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetINT_RAW_SW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetINT_RAW_SW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetINT_RAW_SOC_SLEEP_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetINT_RAW_SOC_SLEEP_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetINT_RAW_SOC_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetINT_RAW_SOC_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_INT_ST: need_des +func (o *PMU_Type) SetHP_INT_ST_LP_CPU_EXC_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_INT_ST_LP_CPU_EXC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_INT_ST_SDIO_IDLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_INT_ST_SDIO_IDLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_INT_ST_SW_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_INT_ST_SW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_INT_ST_SOC_SLEEP_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_INT_ST_SOC_SLEEP_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_INT_ST_SOC_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_INT_ST_SOC_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_INT_ENA: need_des +func (o *PMU_Type) SetHP_INT_ENA_LP_CPU_EXC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_INT_ENA_LP_CPU_EXC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_INT_ENA_SDIO_IDLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_INT_ENA_SDIO_IDLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_INT_ENA_SW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_INT_ENA_SW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_INT_ENA_SOC_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_INT_ENA_SOC_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_INT_CLR: need_des +func (o *PMU_Type) SetHP_INT_CLR_LP_CPU_EXC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_INT_CLR_LP_CPU_EXC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_INT_CLR_SDIO_IDLE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_INT_CLR_SDIO_IDLE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_INT_CLR_SW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_INT_CLR_SW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_INT_CLR_SOC_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_INT_CLR_SOC_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_RAW: need_des +func (o *PMU_Type) SetLP_INT_RAW_LP_CPU_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_RAW_LP_CPU_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_RAW_HP_SW_TRIGGER_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_RAW_HP_SW_TRIGGER_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_ST: need_des +func (o *PMU_Type) SetLP_INT_ST_LP_CPU_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_ST_LP_CPU_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_ST_HP_SW_TRIGGER_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_ST_HP_SW_TRIGGER_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_ENA: need_des +func (o *PMU_Type) SetLP_INT_ENA_LP_CPU_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_ENA_LP_CPU_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_ENA_HP_SW_TRIGGER_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_ENA_HP_SW_TRIGGER_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_CLR: need_des +func (o *PMU_Type) SetLP_INT_CLR_LP_CPU_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_CLR_LP_CPU_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_CLR_HP_SW_TRIGGER_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_CLR_HP_SW_TRIGGER_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_CPU_PWR0: need_des +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_WAITI_RDY(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_WAITI_RDY() uint32 { + return volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x1 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_STALL_RDY(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_STALL_RDY() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_FORCE_STALL(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_FORCE_STALL() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x1fe00000)|value<<21) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x1fe00000) >> 21 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_CPU_PWR1: need_des +func (o *PMU_Type) SetLP_CPU_PWR1_LP_CPU_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR1.Reg, volatile.LoadUint32(&o.LP_CPU_PWR1.Reg)&^(0xffff)|value) +} +func (o *PMU_Type) GetLP_CPU_PWR1_LP_CPU_WAKEUP_EN() uint32 { + return volatile.LoadUint32(&o.LP_CPU_PWR1.Reg) & 0xffff +} +func (o *PMU_Type) SetLP_CPU_PWR1_LP_CPU_SLEEP_REQ(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR1.Reg, volatile.LoadUint32(&o.LP_CPU_PWR1.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_CPU_PWR1_LP_CPU_SLEEP_REQ() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR1.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_LP_CPU_COMM: need_des +func (o *PMU_Type) SetHP_LP_CPU_COMM_LP_TRIGGER_HP(value uint32) { + volatile.StoreUint32(&o.HP_LP_CPU_COMM.Reg, volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_LP_CPU_COMM_LP_TRIGGER_HP() uint32 { + return (volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_LP_CPU_COMM_HP_TRIGGER_LP(value uint32) { + volatile.StoreUint32(&o.HP_LP_CPU_COMM.Reg, volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_LP_CPU_COMM_HP_TRIGGER_LP() uint32 { + return (volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_REGULATOR_CFG: need_des +func (o *PMU_Type) SetHP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL(value uint32) { + volatile.StoreUint32(&o.HP_REGULATOR_CFG.Reg, volatile.LoadUint32(&o.HP_REGULATOR_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL() uint32 { + return (volatile.LoadUint32(&o.HP_REGULATOR_CFG.Reg) & 0x80000000) >> 31 +} + +// PMU.MAIN_STATE: need_des +func (o *PMU_Type) SetMAIN_STATE_MAIN_LAST_ST_STATE(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x3f800)|value<<11) +} +func (o *PMU_Type) GetMAIN_STATE_MAIN_LAST_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x3f800) >> 11 +} +func (o *PMU_Type) SetMAIN_STATE_MAIN_TAR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x1fc0000)|value<<18) +} +func (o *PMU_Type) GetMAIN_STATE_MAIN_TAR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x1fc0000) >> 18 +} +func (o *PMU_Type) SetMAIN_STATE_MAIN_CUR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0xfe000000)|value<<25) +} +func (o *PMU_Type) GetMAIN_STATE_MAIN_CUR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0xfe000000) >> 25 +} + +// PMU.PWR_STATE: need_des +func (o *PMU_Type) SetPWR_STATE_BACKUP_ST_STATE(value uint32) { + volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0x3e000)|value<<13) +} +func (o *PMU_Type) GetPWR_STATE_BACKUP_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0x3e000) >> 13 +} +func (o *PMU_Type) SetPWR_STATE_LP_PWR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0x7c0000)|value<<18) +} +func (o *PMU_Type) GetPWR_STATE_LP_PWR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0x7c0000) >> 18 +} +func (o *PMU_Type) SetPWR_STATE_HP_PWR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0xff800000)|value<<23) +} +func (o *PMU_Type) GetPWR_STATE_HP_PWR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0xff800000) >> 23 +} + +// PMU.CLK_STATE0: need_des +func (o *PMU_Type) SetCLK_STATE0_STABLE_XPD_BBPLL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetCLK_STATE0_STABLE_XPD_BBPLL_STATE() uint32 { + return volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x1 +} +func (o *PMU_Type) SetCLK_STATE0_STABLE_XPD_XTAL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetCLK_STATE0_STABLE_XPD_XTAL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetCLK_STATE0_SYS_CLK_SLP_SEL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetCLK_STATE0_SYS_CLK_SLP_SEL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetCLK_STATE0_SYS_CLK_SEL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetCLK_STATE0_SYS_CLK_SEL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x30000) >> 16 +} +func (o *PMU_Type) SetCLK_STATE0_SYS_CLK_NO_DIV_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetCLK_STATE0_SYS_CLK_NO_DIV_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_SYS_CLK_EN_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_SYS_CLK_EN_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_MODEM_SWITCH_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_MODEM_SWITCH_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_MODEM_CODE_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x600000)|value<<21) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_MODEM_CODE_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x600000) >> 21 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_SLP_SEL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_SLP_SEL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_GLOBAL_XTAL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_GLOBAL_XTAL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetCLK_STATE0_ICG_GLOBAL_PLL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetCLK_STATE0_ICG_GLOBAL_PLL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_I2C_ISO_EN_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_I2C_ISO_EN_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_I2C_RETENTION_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_I2C_RETENTION_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_XPD_BB_I2C_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_XPD_BB_I2C_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_XPD_BBPLL_I2C_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_XPD_BBPLL_I2C_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_XPD_BBPLL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_XPD_BBPLL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetCLK_STATE0_ANA_XPD_XTAL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetCLK_STATE0_ANA_XPD_XTAL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x80000000) >> 31 +} + +// PMU.CLK_STATE1: need_des +func (o *PMU_Type) SetCLK_STATE1(value uint32) { + volatile.StoreUint32(&o.CLK_STATE1.Reg, value) +} +func (o *PMU_Type) GetCLK_STATE1() uint32 { + return volatile.LoadUint32(&o.CLK_STATE1.Reg) +} + +// PMU.CLK_STATE2: need_des +func (o *PMU_Type) SetCLK_STATE2(value uint32) { + volatile.StoreUint32(&o.CLK_STATE2.Reg, value) +} +func (o *PMU_Type) GetCLK_STATE2() uint32 { + return volatile.LoadUint32(&o.CLK_STATE2.Reg) +} + +// PMU.VDD_SPI_STATUS: need_des +func (o *PMU_Type) SetVDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV(value uint32) { + volatile.StoreUint32(&o.VDD_SPI_STATUS.Reg, volatile.LoadUint32(&o.VDD_SPI_STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetVDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV() uint32 { + return (volatile.LoadUint32(&o.VDD_SPI_STATUS.Reg) & 0x80000000) >> 31 +} + +// PMU.DATE: need_des +func (o *PMU_Type) SetDATE_PMU_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetDATE_PMU_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *PMU_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Remote Control +type RMT_Type struct { + CH0DATA volatile.Register32 // 0x0 + CH1DATA volatile.Register32 // 0x4 + CH2DATA volatile.Register32 // 0x8 + CH3DATA volatile.Register32 // 0xC + CH0_TX_CONF0 volatile.Register32 // 0x10 + CH1_TX_CONF0 volatile.Register32 // 0x14 + CH2_RX_CONF0 volatile.Register32 // 0x18 + CH2_RX_CONF1 volatile.Register32 // 0x1C + CH3_RX_CONF0 volatile.Register32 // 0x20 + CH3_RX_CONF1 volatile.Register32 // 0x24 + CH0_TX_STATUS volatile.Register32 // 0x28 + CH1_TX_STATUS volatile.Register32 // 0x2C + CH0_RX_STATUS volatile.Register32 // 0x30 + CH1_RX_STATUS volatile.Register32 // 0x34 + INT_RAW volatile.Register32 // 0x38 + INT_ST volatile.Register32 // 0x3C + INT_ENA volatile.Register32 // 0x40 + INT_CLR volatile.Register32 // 0x44 + CH0CARRIER_DUTY volatile.Register32 // 0x48 + CH1CARRIER_DUTY volatile.Register32 // 0x4C + CH0_RX_CARRIER_RM volatile.Register32 // 0x50 + CH1_RX_CARRIER_RM volatile.Register32 // 0x54 + CH0_TX_LIM volatile.Register32 // 0x58 + CH1_TX_LIM volatile.Register32 // 0x5C + CH0_RX_LIM volatile.Register32 // 0x60 + CH1_RX_LIM volatile.Register32 // 0x64 + SYS_CONF volatile.Register32 // 0x68 + TX_SIM volatile.Register32 // 0x6C + REF_CNT_RST volatile.Register32 // 0x70 + _ [88]byte + DATE volatile.Register32 // 0xCC +} + +// RMT.CH0DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH0DATA(value uint32) { + volatile.StoreUint32(&o.CH0DATA.Reg, value) +} +func (o *RMT_Type) GetCH0DATA() uint32 { + return volatile.LoadUint32(&o.CH0DATA.Reg) +} + +// RMT.CH1DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH1DATA(value uint32) { + volatile.StoreUint32(&o.CH1DATA.Reg, value) +} +func (o *RMT_Type) GetCH1DATA() uint32 { + return volatile.LoadUint32(&o.CH1DATA.Reg) +} + +// RMT.CH2DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH2DATA(value uint32) { + volatile.StoreUint32(&o.CH2DATA.Reg, value) +} +func (o *RMT_Type) GetCH2DATA() uint32 { + return volatile.LoadUint32(&o.CH2DATA.Reg) +} + +// RMT.CH3DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH3DATA(value uint32) { + volatile.StoreUint32(&o.CH3DATA.Reg, value) +} +func (o *RMT_Type) GetCH3DATA() uint32 { + return volatile.LoadUint32(&o.CH3DATA.Reg) +} + +// RMT.CH0_TX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH0_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH0_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH0_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH0_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH0_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH0_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH0_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH0_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH0_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH0_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH0_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x70000)|value<<16) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x70000) >> 16 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH0_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH0_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH1_TX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH1_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH1_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH1_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH1_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH1_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH1_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH1_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH1_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH1_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH1_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH1_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x70000)|value<<16) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x70000) >> 16 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH1_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH1_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH2_RX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH2_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH2_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH2_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH2_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH2_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x3800000)|value<<23) +} +func (o *RMT_Type) GetCH2_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x3800000) >> 23 +} +func (o *RMT_Type) SetCH2_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH2_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH2_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF0.Reg, volatile.LoadUint32(&o.CH2_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH2_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH2_RX_CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH2_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH2_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH2_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH2_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH2_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH2_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH2_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH2_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH2_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH2_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH2_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH2_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH2_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH2_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH2_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH2_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH2_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CONF1.Reg, volatile.LoadUint32(&o.CH2_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH2_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH3_RX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH3_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH3_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH3_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH3_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH3_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x3800000)|value<<23) +} +func (o *RMT_Type) GetCH3_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x3800000) >> 23 +} +func (o *RMT_Type) SetCH3_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH3_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH3_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF0.Reg, volatile.LoadUint32(&o.CH3_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH3_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH3_RX_CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH3_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH3_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH3_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH3_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH3_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH3_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH3_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH3_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH3_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH3_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH3_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH3_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH3_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH3_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH3_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH3_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH3_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CONF1.Reg, volatile.LoadUint32(&o.CH3_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH3_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH0_TX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH0_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0xe00)|value<<9) +} +func (o *RMT_Type) GetCH0_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0xe00) >> 9 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH0_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH0_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0xff000000)|value<<24) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0xff000000) >> 24 +} + +// RMT.CH1_TX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH1_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0xe00)|value<<9) +} +func (o *RMT_Type) GetCH1_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0xe00) >> 9 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH1_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH1_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0xff000000)|value<<24) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0xff000000) >> 24 +} + +// RMT.CH0_RX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH0_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH0_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH0_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH0_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH0_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH0_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH0_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH0_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH0_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH0_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH1_RX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH1_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x1ff000)|value<<12) +} +func (o *RMT_Type) GetCH1_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x1ff000) >> 12 +} +func (o *RMT_Type) SetCH1_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH1_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH1_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH1_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH1_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH1_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH1_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH1_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.INT_RAW: Raw interrupt status +func (o *RMT_Type) SetINT_RAW_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} + +// RMT.INT_ST: Masked interrupt status +func (o *RMT_Type) SetINT_ST_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_ST_CH_s_X_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ST_CH_s_X_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} + +// RMT.INT_ENA: Interrupt enable bits +func (o *RMT_Type) SetINT_ENA_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_ENA_CH_s_X_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ENA_CH_s_X_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} + +// RMT.INT_CLR: Interrupt clear bits +func (o *RMT_Type) SetINT_CLR_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} + +// RMT.CH0CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH0_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH1_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH1_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH0_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH0_RX_LIM_RMT_RX_LIM(value uint32) { + volatile.StoreUint32(&o.CH0_RX_LIM.Reg, volatile.LoadUint32(&o.CH0_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_RX_LIM_RMT_RX_LIM() uint32 { + return volatile.LoadUint32(&o.CH0_RX_LIM.Reg) & 0x1ff +} + +// RMT.CH1_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH1_RX_LIM_RMT_RX_LIM(value uint32) { + volatile.StoreUint32(&o.CH1_RX_LIM.Reg, volatile.LoadUint32(&o.CH1_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_RX_LIM_RMT_RX_LIM() uint32 { + return volatile.LoadUint32(&o.CH1_RX_LIM.Reg) & 0x1ff +} + +// RMT.SYS_CONF: RMT apb configuration register +func (o *RMT_Type) SetSYS_CONF_APB_FIFO_MASK(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetSYS_CONF_APB_FIFO_MASK() uint32 { + return volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetSYS_CONF_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xff0)|value<<4) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xff0) >> 4 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3f000)|value<<12) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3f000) >> 12 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xfc0000)|value<<18) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xfc0000) >> 18 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3000000)|value<<24) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3000000) >> 24 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetSYS_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetSYS_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x80000000) >> 31 +} + +// RMT.TX_SIM: RMT TX synchronous register +func (o *RMT_Type) SetTX_SIM_CH0(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_SIM_CH0() uint32 { + return volatile.LoadUint32(&o.TX_SIM.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_SIM_CH1(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_SIM_CH1() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_SIM_EN(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_SIM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x4) >> 2 +} + +// RMT.REF_CNT_RST: RMT clock divider reset register +func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST() uint32 { + return volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x1 +} +func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH1(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH1() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH2(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH2() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH3(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH3() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x8) >> 3 +} + +// RMT.DATE: RMT version register +func (o *RMT_Type) SetDATE_RMT_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RMT_Type) GetDATE_RMT_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Hardware Random Number Generator +type RNG_Type struct { + _ [8]byte + DATA volatile.Register32 // 0x8 +} + +// RSA (Rivest Shamir Adleman) Accelerator +type RSA_Type struct { + M_MEM [384]volatile.Register8 // 0x0 + _ [128]byte + Z_MEM [384]volatile.Register8 // 0x200 + _ [128]byte + Y_MEM [384]volatile.Register8 // 0x400 + _ [128]byte + X_MEM [384]volatile.Register8 // 0x600 + _ [128]byte + M_PRIME volatile.Register32 // 0x800 + MODE volatile.Register32 // 0x804 + QUERY_CLEAN volatile.Register32 // 0x808 + SET_START_MODEXP volatile.Register32 // 0x80C + SET_START_MODMULT volatile.Register32 // 0x810 + SET_START_MULT volatile.Register32 // 0x814 + QUERY_IDLE volatile.Register32 // 0x818 + INT_CLR volatile.Register32 // 0x81C + CONSTANT_TIME volatile.Register32 // 0x820 + SEARCH_ENABLE volatile.Register32 // 0x824 + SEARCH_POS volatile.Register32 // 0x828 + INT_ENA volatile.Register32 // 0x82C + DATE volatile.Register32 // 0x830 +} + +// RSA.M_PRIME: Represents M’ +func (o *RSA_Type) SetM_PRIME(value uint32) { + volatile.StoreUint32(&o.M_PRIME.Reg, value) +} +func (o *RSA_Type) GetM_PRIME() uint32 { + return volatile.LoadUint32(&o.M_PRIME.Reg) +} + +// RSA.MODE: Configures RSA length +func (o *RSA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7f)|value) +} +func (o *RSA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7f +} + +// RSA.QUERY_CLEAN: RSA clean register +func (o *RSA_Type) SetQUERY_CLEAN(value uint32) { + volatile.StoreUint32(&o.QUERY_CLEAN.Reg, volatile.LoadUint32(&o.QUERY_CLEAN.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetQUERY_CLEAN() uint32 { + return volatile.LoadUint32(&o.QUERY_CLEAN.Reg) & 0x1 +} + +// RSA.SET_START_MODEXP: Starts modular exponentiation +func (o *RSA_Type) SetSET_START_MODEXP(value uint32) { + volatile.StoreUint32(&o.SET_START_MODEXP.Reg, volatile.LoadUint32(&o.SET_START_MODEXP.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MODEXP() uint32 { + return volatile.LoadUint32(&o.SET_START_MODEXP.Reg) & 0x1 +} + +// RSA.SET_START_MODMULT: Starts modular multiplication +func (o *RSA_Type) SetSET_START_MODMULT(value uint32) { + volatile.StoreUint32(&o.SET_START_MODMULT.Reg, volatile.LoadUint32(&o.SET_START_MODMULT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MODMULT() uint32 { + return volatile.LoadUint32(&o.SET_START_MODMULT.Reg) & 0x1 +} + +// RSA.SET_START_MULT: Starts multiplication +func (o *RSA_Type) SetSET_START_MULT(value uint32) { + volatile.StoreUint32(&o.SET_START_MULT.Reg, volatile.LoadUint32(&o.SET_START_MULT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MULT() uint32 { + return volatile.LoadUint32(&o.SET_START_MULT.Reg) & 0x1 +} + +// RSA.QUERY_IDLE: Represents the RSA status +func (o *RSA_Type) SetQUERY_IDLE(value uint32) { + volatile.StoreUint32(&o.QUERY_IDLE.Reg, volatile.LoadUint32(&o.QUERY_IDLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetQUERY_IDLE() uint32 { + return volatile.LoadUint32(&o.QUERY_IDLE.Reg) & 0x1 +} + +// RSA.INT_CLR: Clears RSA interrupt +func (o *RSA_Type) SetINT_CLR_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINT_CLR_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} + +// RSA.CONSTANT_TIME: Configures the constant_time option +func (o *RSA_Type) SetCONSTANT_TIME(value uint32) { + volatile.StoreUint32(&o.CONSTANT_TIME.Reg, volatile.LoadUint32(&o.CONSTANT_TIME.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCONSTANT_TIME() uint32 { + return volatile.LoadUint32(&o.CONSTANT_TIME.Reg) & 0x1 +} + +// RSA.SEARCH_ENABLE: Configures the search option +func (o *RSA_Type) SetSEARCH_ENABLE(value uint32) { + volatile.StoreUint32(&o.SEARCH_ENABLE.Reg, volatile.LoadUint32(&o.SEARCH_ENABLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSEARCH_ENABLE() uint32 { + return volatile.LoadUint32(&o.SEARCH_ENABLE.Reg) & 0x1 +} + +// RSA.SEARCH_POS: Configures the search position +func (o *RSA_Type) SetSEARCH_POS(value uint32) { + volatile.StoreUint32(&o.SEARCH_POS.Reg, volatile.LoadUint32(&o.SEARCH_POS.Reg)&^(0xfff)|value) +} +func (o *RSA_Type) GetSEARCH_POS() uint32 { + return volatile.LoadUint32(&o.SEARCH_POS.Reg) & 0xfff +} + +// RSA.INT_ENA: Enables the RSA interrupt +func (o *RSA_Type) SetINT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// RSA.DATE: Version control register +func (o *RSA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *RSA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// SHA (Secure Hash Algorithm) Accelerator +type SHA_Type struct { + MODE volatile.Register32 // 0x0 + T_STRING volatile.Register32 // 0x4 + T_LENGTH volatile.Register32 // 0x8 + DMA_BLOCK_NUM volatile.Register32 // 0xC + START volatile.Register32 // 0x10 + CONTINUE volatile.Register32 // 0x14 + BUSY volatile.Register32 // 0x18 + DMA_START volatile.Register32 // 0x1C + DMA_CONTINUE volatile.Register32 // 0x20 + CLEAR_IRQ volatile.Register32 // 0x24 + IRQ_ENA volatile.Register32 // 0x28 + DATE volatile.Register32 // 0x2C + _ [16]byte + H_MEM [64]volatile.Register8 // 0x40 + M_MEM [64]volatile.Register8 // 0x80 +} + +// SHA.MODE: Initial configuration register. +func (o *SHA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *SHA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// SHA.T_STRING: SHA 512/t configuration register 0. +func (o *SHA_Type) SetT_STRING(value uint32) { + volatile.StoreUint32(&o.T_STRING.Reg, value) +} +func (o *SHA_Type) GetT_STRING() uint32 { + return volatile.LoadUint32(&o.T_STRING.Reg) +} + +// SHA.T_LENGTH: SHA 512/t configuration register 1. +func (o *SHA_Type) SetT_LENGTH(value uint32) { + volatile.StoreUint32(&o.T_LENGTH.Reg, volatile.LoadUint32(&o.T_LENGTH.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetT_LENGTH() uint32 { + return volatile.LoadUint32(&o.T_LENGTH.Reg) & 0x3f +} + +// SHA.DMA_BLOCK_NUM: DMA configuration register 0. +func (o *SHA_Type) SetDMA_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_NUM.Reg, volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetDMA_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg) & 0x3f +} + +// SHA.START: Typical SHA configuration register 0. +func (o *SHA_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetSTART() uint32 { + return (volatile.LoadUint32(&o.START.Reg) & 0xfffffffe) >> 1 +} + +// SHA.CONTINUE: Typical SHA configuration register 1. +func (o *SHA_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetCONTINUE() uint32 { + return (volatile.LoadUint32(&o.CONTINUE.Reg) & 0xfffffffe) >> 1 +} + +// SHA.BUSY: Busy register. +func (o *SHA_Type) SetBUSY_STATE(value uint32) { + volatile.StoreUint32(&o.BUSY.Reg, volatile.LoadUint32(&o.BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetBUSY_STATE() uint32 { + return volatile.LoadUint32(&o.BUSY.Reg) & 0x1 +} + +// SHA.DMA_START: DMA configuration register 1. +func (o *SHA_Type) SetDMA_START(value uint32) { + volatile.StoreUint32(&o.DMA_START.Reg, volatile.LoadUint32(&o.DMA_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_START() uint32 { + return volatile.LoadUint32(&o.DMA_START.Reg) & 0x1 +} + +// SHA.DMA_CONTINUE: DMA configuration register 2. +func (o *SHA_Type) SetDMA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.DMA_CONTINUE.Reg, volatile.LoadUint32(&o.DMA_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_CONTINUE() uint32 { + return volatile.LoadUint32(&o.DMA_CONTINUE.Reg) & 0x1 +} + +// SHA.CLEAR_IRQ: Interrupt clear register. +func (o *SHA_Type) SetCLEAR_IRQ_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CLEAR_IRQ.Reg, volatile.LoadUint32(&o.CLEAR_IRQ.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetCLEAR_IRQ_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.CLEAR_IRQ.Reg) & 0x1 +} + +// SHA.IRQ_ENA: Interrupt enable register. +func (o *SHA_Type) SetIRQ_ENA_INTERRUPT_ENA(value uint32) { + volatile.StoreUint32(&o.IRQ_ENA.Reg, volatile.LoadUint32(&o.IRQ_ENA.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetIRQ_ENA_INTERRUPT_ENA() uint32 { + return volatile.LoadUint32(&o.IRQ_ENA.Reg) & 0x1 +} + +// SHA.DATE: Date register. +func (o *SHA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SHA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Event Task Matrix +type SOC_ETM_Type struct { + CH_ENA_AD0 volatile.Register32 // 0x0 + CH_ENA_AD0_SET volatile.Register32 // 0x4 + CH_ENA_AD0_CLR volatile.Register32 // 0x8 + CH_ENA_AD1 volatile.Register32 // 0xC + CH_ENA_AD1_SET volatile.Register32 // 0x10 + CH_ENA_AD1_CLR volatile.Register32 // 0x14 + CH0_EVT_ID volatile.Register32 // 0x18 + CH0_TASK_ID volatile.Register32 // 0x1C + CH1_EVT_ID volatile.Register32 // 0x20 + CH1_TASK_ID volatile.Register32 // 0x24 + CH2_EVT_ID volatile.Register32 // 0x28 + CH2_TASK_ID volatile.Register32 // 0x2C + CH3_EVT_ID volatile.Register32 // 0x30 + CH3_TASK_ID volatile.Register32 // 0x34 + CH4_EVT_ID volatile.Register32 // 0x38 + CH4_TASK_ID volatile.Register32 // 0x3C + CH5_EVT_ID volatile.Register32 // 0x40 + CH5_TASK_ID volatile.Register32 // 0x44 + CH6_EVT_ID volatile.Register32 // 0x48 + CH6_TASK_ID volatile.Register32 // 0x4C + CH7_EVT_ID volatile.Register32 // 0x50 + CH7_TASK_ID volatile.Register32 // 0x54 + CH8_EVT_ID volatile.Register32 // 0x58 + CH8_TASK_ID volatile.Register32 // 0x5C + CH9_EVT_ID volatile.Register32 // 0x60 + CH9_TASK_ID volatile.Register32 // 0x64 + CH10_EVT_ID volatile.Register32 // 0x68 + CH10_TASK_ID volatile.Register32 // 0x6C + CH11_EVT_ID volatile.Register32 // 0x70 + CH11_TASK_ID volatile.Register32 // 0x74 + CH12_EVT_ID volatile.Register32 // 0x78 + CH12_TASK_ID volatile.Register32 // 0x7C + CH13_EVT_ID volatile.Register32 // 0x80 + CH13_TASK_ID volatile.Register32 // 0x84 + CH14_EVT_ID volatile.Register32 // 0x88 + CH14_TASK_ID volatile.Register32 // 0x8C + CH15_EVT_ID volatile.Register32 // 0x90 + CH15_TASK_ID volatile.Register32 // 0x94 + CH16_EVT_ID volatile.Register32 // 0x98 + CH16_TASK_ID volatile.Register32 // 0x9C + CH17_EVT_ID volatile.Register32 // 0xA0 + CH17_TASK_ID volatile.Register32 // 0xA4 + CH18_EVT_ID volatile.Register32 // 0xA8 + CH18_TASK_ID volatile.Register32 // 0xAC + CH19_EVT_ID volatile.Register32 // 0xB0 + CH19_TASK_ID volatile.Register32 // 0xB4 + CH20_EVT_ID volatile.Register32 // 0xB8 + CH20_TASK_ID volatile.Register32 // 0xBC + CH21_EVT_ID volatile.Register32 // 0xC0 + CH21_TASK_ID volatile.Register32 // 0xC4 + CH22_EVT_ID volatile.Register32 // 0xC8 + CH22_TASK_ID volatile.Register32 // 0xCC + CH23_EVT_ID volatile.Register32 // 0xD0 + CH23_TASK_ID volatile.Register32 // 0xD4 + CH24_EVT_ID volatile.Register32 // 0xD8 + CH24_TASK_ID volatile.Register32 // 0xDC + CH25_EVT_ID volatile.Register32 // 0xE0 + CH25_TASK_ID volatile.Register32 // 0xE4 + CH26_EVT_ID volatile.Register32 // 0xE8 + CH26_TASK_ID volatile.Register32 // 0xEC + CH27_EVT_ID volatile.Register32 // 0xF0 + CH27_TASK_ID volatile.Register32 // 0xF4 + CH28_EVT_ID volatile.Register32 // 0xF8 + CH28_TASK_ID volatile.Register32 // 0xFC + CH29_EVT_ID volatile.Register32 // 0x100 + CH29_TASK_ID volatile.Register32 // 0x104 + CH30_EVT_ID volatile.Register32 // 0x108 + CH30_TASK_ID volatile.Register32 // 0x10C + CH31_EVT_ID volatile.Register32 // 0x110 + CH31_TASK_ID volatile.Register32 // 0x114 + CH32_EVT_ID volatile.Register32 // 0x118 + CH32_TASK_ID volatile.Register32 // 0x11C + CH33_EVT_ID volatile.Register32 // 0x120 + CH33_TASK_ID volatile.Register32 // 0x124 + CH34_EVT_ID volatile.Register32 // 0x128 + CH34_TASK_ID volatile.Register32 // 0x12C + CH35_EVT_ID volatile.Register32 // 0x130 + CH35_TASK_ID volatile.Register32 // 0x134 + CH36_EVT_ID volatile.Register32 // 0x138 + CH36_TASK_ID volatile.Register32 // 0x13C + CH37_EVT_ID volatile.Register32 // 0x140 + CH37_TASK_ID volatile.Register32 // 0x144 + CH38_EVT_ID volatile.Register32 // 0x148 + CH38_TASK_ID volatile.Register32 // 0x14C + CH39_EVT_ID volatile.Register32 // 0x150 + CH39_TASK_ID volatile.Register32 // 0x154 + CH40_EVT_ID volatile.Register32 // 0x158 + CH40_TASK_ID volatile.Register32 // 0x15C + CH41_EVT_ID volatile.Register32 // 0x160 + CH41_TASK_ID volatile.Register32 // 0x164 + CH42_EVT_ID volatile.Register32 // 0x168 + CH42_TASK_ID volatile.Register32 // 0x16C + CH43_EVT_ID volatile.Register32 // 0x170 + CH43_TASK_ID volatile.Register32 // 0x174 + CH44_EVT_ID volatile.Register32 // 0x178 + CH44_TASK_ID volatile.Register32 // 0x17C + CH45_EVT_ID volatile.Register32 // 0x180 + CH45_TASK_ID volatile.Register32 // 0x184 + CH46_EVT_ID volatile.Register32 // 0x188 + CH46_TASK_ID volatile.Register32 // 0x18C + CH47_EVT_ID volatile.Register32 // 0x190 + CH47_TASK_ID volatile.Register32 // 0x194 + CH48_EVT_ID volatile.Register32 // 0x198 + CH48_TASK_ID volatile.Register32 // 0x19C + CH49_EVT_ID volatile.Register32 // 0x1A0 + CH49_TASK_ID volatile.Register32 // 0x1A4 + CLK_EN volatile.Register32 // 0x1A8 + DATE volatile.Register32 // 0x1AC +} + +// SOC_ETM.CH_ENA_AD0: channel enable register +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA0(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA0() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA1(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA1() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA2(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA2() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA3(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA3() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA4(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA4() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA5(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA5() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA6(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA6() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA7(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA7() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA8(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA8() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA9(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA9() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA10(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA10() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA11(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA11() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA12(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA12() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA13(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA13() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA14(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA14() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA15(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA15() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA16(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA16() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA17(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA17() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA18(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA18() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA19(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA19() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA20(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA20() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA21(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA21() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA22(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA22() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA23(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA23() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA24(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA24() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA25(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA25() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA26(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA26() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA27(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA27() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA28(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA28() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA29(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA29() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA30(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA30() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA31(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA31() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.CH_ENA_AD0_SET: channel enable set register +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET0(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET0() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET1(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET1() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET2(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET2() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET3(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET3() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET4(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET4() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET5(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET5() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET6(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET6() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET7(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET7() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET8(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET8() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET9(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET9() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET10(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET10() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET11(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET11() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET12(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET12() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET13(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET13() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET14(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET14() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET15(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET15() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET16(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET16() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET17(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET17() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET18(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET18() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET19(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET19() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET20(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET20() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET21(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET21() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET22(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET22() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET23(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET23() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET24(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET24() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET25(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET25() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET26(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET26() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET27(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET27() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET28(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET28() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET29(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET29() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET30(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET30() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET31(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET31() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.CH_ENA_AD0_CLR: channel enable clear register +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR0(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR0() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR1(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR1() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR2(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR2() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR3(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR3() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR4(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR4() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR5(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR5() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR6(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR6() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR7(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR7() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR8(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR8() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR9(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR9() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR10(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR10() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR11(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR11() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR12(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR12() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR13(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR13() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR14(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR14() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR15(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR15() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR16(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR16() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR17(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR17() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR18(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR18() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR19(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR19() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR20(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR20() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR21(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR21() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR22(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR22() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR23(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR23() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR24(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR24() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR25(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR25() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR26(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR26() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR27(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR27() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR28(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR28() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR29(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR29() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR30(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR30() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR31(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR31() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.CH_ENA_AD1: channel enable register +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA32(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA32() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA33(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA33() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA34(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA34() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA35(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA35() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA36(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA36() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA37(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA37() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA38(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA38() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA39(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA39() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA40(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA40() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA41(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA41() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA42(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA42() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA43(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA43() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA44(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA44() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA45(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA45() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA46(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA46() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA47(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA47() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA48(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA48() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA49(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA49() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x20000) >> 17 +} + +// SOC_ETM.CH_ENA_AD1_SET: channel enable set register +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET32(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET32() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET33(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET33() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET34(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET34() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET35(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET35() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET36(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET36() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET37(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET37() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET38(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET38() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET39(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET39() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET40(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET40() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET41(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET41() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET42(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET42() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET43(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET43() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET44(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET44() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET45(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET45() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET46(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET46() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET47(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET47() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET48(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET48() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET49(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET49() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x20000) >> 17 +} + +// SOC_ETM.CH_ENA_AD1_CLR: channel enable clear register +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR32(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR32() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR33(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR33() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR34(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR34() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR35(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR35() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR36(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR36() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR37(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR37() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR38(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR38() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR39(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR39() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR40(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR40() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR41(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR41() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR42(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR42() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR43(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR43() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR44(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR44() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR45(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR45() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR46(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR46() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR47(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR47() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR48(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR48() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR49(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR49() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x20000) >> 17 +} + +// SOC_ETM.CH0_EVT_ID: channel0 event id register +func (o *SOC_ETM_Type) SetCH0_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH0_EVT_ID.Reg, volatile.LoadUint32(&o.CH0_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH0_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH0_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH0_TASK_ID: channel0 task id register +func (o *SOC_ETM_Type) SetCH0_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH0_TASK_ID.Reg, volatile.LoadUint32(&o.CH0_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH0_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH0_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH1_EVT_ID: channel1 event id register +func (o *SOC_ETM_Type) SetCH1_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH1_EVT_ID.Reg, volatile.LoadUint32(&o.CH1_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH1_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH1_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH1_TASK_ID: channel1 task id register +func (o *SOC_ETM_Type) SetCH1_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH1_TASK_ID.Reg, volatile.LoadUint32(&o.CH1_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH1_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH1_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH2_EVT_ID: channel2 event id register +func (o *SOC_ETM_Type) SetCH2_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH2_EVT_ID.Reg, volatile.LoadUint32(&o.CH2_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH2_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH2_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH2_TASK_ID: channel2 task id register +func (o *SOC_ETM_Type) SetCH2_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH2_TASK_ID.Reg, volatile.LoadUint32(&o.CH2_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH2_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH2_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH3_EVT_ID: channel3 event id register +func (o *SOC_ETM_Type) SetCH3_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH3_EVT_ID.Reg, volatile.LoadUint32(&o.CH3_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH3_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH3_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH3_TASK_ID: channel3 task id register +func (o *SOC_ETM_Type) SetCH3_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH3_TASK_ID.Reg, volatile.LoadUint32(&o.CH3_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH3_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH3_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH4_EVT_ID: channel4 event id register +func (o *SOC_ETM_Type) SetCH4_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH4_EVT_ID.Reg, volatile.LoadUint32(&o.CH4_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH4_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH4_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH4_TASK_ID: channel4 task id register +func (o *SOC_ETM_Type) SetCH4_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH4_TASK_ID.Reg, volatile.LoadUint32(&o.CH4_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH4_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH4_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH5_EVT_ID: channel5 event id register +func (o *SOC_ETM_Type) SetCH5_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH5_EVT_ID.Reg, volatile.LoadUint32(&o.CH5_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH5_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH5_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH5_TASK_ID: channel5 task id register +func (o *SOC_ETM_Type) SetCH5_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH5_TASK_ID.Reg, volatile.LoadUint32(&o.CH5_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH5_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH5_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH6_EVT_ID: channel6 event id register +func (o *SOC_ETM_Type) SetCH6_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH6_EVT_ID.Reg, volatile.LoadUint32(&o.CH6_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH6_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH6_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH6_TASK_ID: channel6 task id register +func (o *SOC_ETM_Type) SetCH6_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH6_TASK_ID.Reg, volatile.LoadUint32(&o.CH6_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH6_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH6_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH7_EVT_ID: channel7 event id register +func (o *SOC_ETM_Type) SetCH7_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH7_EVT_ID.Reg, volatile.LoadUint32(&o.CH7_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH7_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH7_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH7_TASK_ID: channel7 task id register +func (o *SOC_ETM_Type) SetCH7_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH7_TASK_ID.Reg, volatile.LoadUint32(&o.CH7_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH7_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH7_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH8_EVT_ID: channel8 event id register +func (o *SOC_ETM_Type) SetCH8_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH8_EVT_ID.Reg, volatile.LoadUint32(&o.CH8_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH8_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH8_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH8_TASK_ID: channel8 task id register +func (o *SOC_ETM_Type) SetCH8_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH8_TASK_ID.Reg, volatile.LoadUint32(&o.CH8_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH8_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH8_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH9_EVT_ID: channel9 event id register +func (o *SOC_ETM_Type) SetCH9_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH9_EVT_ID.Reg, volatile.LoadUint32(&o.CH9_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH9_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH9_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH9_TASK_ID: channel9 task id register +func (o *SOC_ETM_Type) SetCH9_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH9_TASK_ID.Reg, volatile.LoadUint32(&o.CH9_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH9_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH9_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH10_EVT_ID: channel10 event id register +func (o *SOC_ETM_Type) SetCH10_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH10_EVT_ID.Reg, volatile.LoadUint32(&o.CH10_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH10_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH10_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH10_TASK_ID: channel10 task id register +func (o *SOC_ETM_Type) SetCH10_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH10_TASK_ID.Reg, volatile.LoadUint32(&o.CH10_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH10_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH10_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH11_EVT_ID: channel11 event id register +func (o *SOC_ETM_Type) SetCH11_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH11_EVT_ID.Reg, volatile.LoadUint32(&o.CH11_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH11_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH11_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH11_TASK_ID: channel11 task id register +func (o *SOC_ETM_Type) SetCH11_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH11_TASK_ID.Reg, volatile.LoadUint32(&o.CH11_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH11_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH11_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH12_EVT_ID: channel12 event id register +func (o *SOC_ETM_Type) SetCH12_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH12_EVT_ID.Reg, volatile.LoadUint32(&o.CH12_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH12_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH12_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH12_TASK_ID: channel12 task id register +func (o *SOC_ETM_Type) SetCH12_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH12_TASK_ID.Reg, volatile.LoadUint32(&o.CH12_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH12_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH12_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH13_EVT_ID: channel13 event id register +func (o *SOC_ETM_Type) SetCH13_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH13_EVT_ID.Reg, volatile.LoadUint32(&o.CH13_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH13_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH13_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH13_TASK_ID: channel13 task id register +func (o *SOC_ETM_Type) SetCH13_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH13_TASK_ID.Reg, volatile.LoadUint32(&o.CH13_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH13_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH13_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH14_EVT_ID: channel14 event id register +func (o *SOC_ETM_Type) SetCH14_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH14_EVT_ID.Reg, volatile.LoadUint32(&o.CH14_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH14_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH14_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH14_TASK_ID: channel14 task id register +func (o *SOC_ETM_Type) SetCH14_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH14_TASK_ID.Reg, volatile.LoadUint32(&o.CH14_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH14_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH14_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH15_EVT_ID: channel15 event id register +func (o *SOC_ETM_Type) SetCH15_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH15_EVT_ID.Reg, volatile.LoadUint32(&o.CH15_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH15_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH15_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH15_TASK_ID: channel15 task id register +func (o *SOC_ETM_Type) SetCH15_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH15_TASK_ID.Reg, volatile.LoadUint32(&o.CH15_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH15_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH15_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH16_EVT_ID: channel16 event id register +func (o *SOC_ETM_Type) SetCH16_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH16_EVT_ID.Reg, volatile.LoadUint32(&o.CH16_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH16_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH16_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH16_TASK_ID: channel16 task id register +func (o *SOC_ETM_Type) SetCH16_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH16_TASK_ID.Reg, volatile.LoadUint32(&o.CH16_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH16_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH16_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH17_EVT_ID: channel17 event id register +func (o *SOC_ETM_Type) SetCH17_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH17_EVT_ID.Reg, volatile.LoadUint32(&o.CH17_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH17_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH17_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH17_TASK_ID: channel17 task id register +func (o *SOC_ETM_Type) SetCH17_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH17_TASK_ID.Reg, volatile.LoadUint32(&o.CH17_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH17_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH17_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH18_EVT_ID: channel18 event id register +func (o *SOC_ETM_Type) SetCH18_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH18_EVT_ID.Reg, volatile.LoadUint32(&o.CH18_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH18_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH18_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH18_TASK_ID: channel18 task id register +func (o *SOC_ETM_Type) SetCH18_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH18_TASK_ID.Reg, volatile.LoadUint32(&o.CH18_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH18_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH18_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH19_EVT_ID: channel19 event id register +func (o *SOC_ETM_Type) SetCH19_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH19_EVT_ID.Reg, volatile.LoadUint32(&o.CH19_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH19_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH19_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH19_TASK_ID: channel19 task id register +func (o *SOC_ETM_Type) SetCH19_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH19_TASK_ID.Reg, volatile.LoadUint32(&o.CH19_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH19_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH19_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH20_EVT_ID: channel20 event id register +func (o *SOC_ETM_Type) SetCH20_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH20_EVT_ID.Reg, volatile.LoadUint32(&o.CH20_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH20_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH20_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH20_TASK_ID: channel20 task id register +func (o *SOC_ETM_Type) SetCH20_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH20_TASK_ID.Reg, volatile.LoadUint32(&o.CH20_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH20_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH20_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH21_EVT_ID: channel21 event id register +func (o *SOC_ETM_Type) SetCH21_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH21_EVT_ID.Reg, volatile.LoadUint32(&o.CH21_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH21_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH21_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH21_TASK_ID: channel21 task id register +func (o *SOC_ETM_Type) SetCH21_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH21_TASK_ID.Reg, volatile.LoadUint32(&o.CH21_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH21_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH21_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH22_EVT_ID: channel22 event id register +func (o *SOC_ETM_Type) SetCH22_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH22_EVT_ID.Reg, volatile.LoadUint32(&o.CH22_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH22_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH22_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH22_TASK_ID: channel22 task id register +func (o *SOC_ETM_Type) SetCH22_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH22_TASK_ID.Reg, volatile.LoadUint32(&o.CH22_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH22_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH22_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH23_EVT_ID: channel23 event id register +func (o *SOC_ETM_Type) SetCH23_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH23_EVT_ID.Reg, volatile.LoadUint32(&o.CH23_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH23_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH23_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH23_TASK_ID: channel23 task id register +func (o *SOC_ETM_Type) SetCH23_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH23_TASK_ID.Reg, volatile.LoadUint32(&o.CH23_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH23_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH23_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH24_EVT_ID: channel24 event id register +func (o *SOC_ETM_Type) SetCH24_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH24_EVT_ID.Reg, volatile.LoadUint32(&o.CH24_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH24_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH24_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH24_TASK_ID: channel24 task id register +func (o *SOC_ETM_Type) SetCH24_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH24_TASK_ID.Reg, volatile.LoadUint32(&o.CH24_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH24_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH24_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH25_EVT_ID: channel25 event id register +func (o *SOC_ETM_Type) SetCH25_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH25_EVT_ID.Reg, volatile.LoadUint32(&o.CH25_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH25_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH25_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH25_TASK_ID: channel25 task id register +func (o *SOC_ETM_Type) SetCH25_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH25_TASK_ID.Reg, volatile.LoadUint32(&o.CH25_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH25_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH25_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH26_EVT_ID: channel26 event id register +func (o *SOC_ETM_Type) SetCH26_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH26_EVT_ID.Reg, volatile.LoadUint32(&o.CH26_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH26_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH26_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH26_TASK_ID: channel26 task id register +func (o *SOC_ETM_Type) SetCH26_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH26_TASK_ID.Reg, volatile.LoadUint32(&o.CH26_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH26_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH26_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH27_EVT_ID: channel27 event id register +func (o *SOC_ETM_Type) SetCH27_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH27_EVT_ID.Reg, volatile.LoadUint32(&o.CH27_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH27_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH27_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH27_TASK_ID: channel27 task id register +func (o *SOC_ETM_Type) SetCH27_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH27_TASK_ID.Reg, volatile.LoadUint32(&o.CH27_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH27_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH27_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH28_EVT_ID: channel28 event id register +func (o *SOC_ETM_Type) SetCH28_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH28_EVT_ID.Reg, volatile.LoadUint32(&o.CH28_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH28_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH28_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH28_TASK_ID: channel28 task id register +func (o *SOC_ETM_Type) SetCH28_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH28_TASK_ID.Reg, volatile.LoadUint32(&o.CH28_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH28_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH28_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH29_EVT_ID: channel29 event id register +func (o *SOC_ETM_Type) SetCH29_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH29_EVT_ID.Reg, volatile.LoadUint32(&o.CH29_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH29_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH29_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH29_TASK_ID: channel29 task id register +func (o *SOC_ETM_Type) SetCH29_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH29_TASK_ID.Reg, volatile.LoadUint32(&o.CH29_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH29_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH29_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH30_EVT_ID: channel30 event id register +func (o *SOC_ETM_Type) SetCH30_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH30_EVT_ID.Reg, volatile.LoadUint32(&o.CH30_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH30_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH30_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH30_TASK_ID: channel30 task id register +func (o *SOC_ETM_Type) SetCH30_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH30_TASK_ID.Reg, volatile.LoadUint32(&o.CH30_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH30_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH30_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH31_EVT_ID: channel31 event id register +func (o *SOC_ETM_Type) SetCH31_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH31_EVT_ID.Reg, volatile.LoadUint32(&o.CH31_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH31_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH31_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH31_TASK_ID: channel31 task id register +func (o *SOC_ETM_Type) SetCH31_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH31_TASK_ID.Reg, volatile.LoadUint32(&o.CH31_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH31_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH31_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH32_EVT_ID: channel32 event id register +func (o *SOC_ETM_Type) SetCH32_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH32_EVT_ID.Reg, volatile.LoadUint32(&o.CH32_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH32_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH32_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH32_TASK_ID: channel32 task id register +func (o *SOC_ETM_Type) SetCH32_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH32_TASK_ID.Reg, volatile.LoadUint32(&o.CH32_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH32_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH32_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH33_EVT_ID: channel33 event id register +func (o *SOC_ETM_Type) SetCH33_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH33_EVT_ID.Reg, volatile.LoadUint32(&o.CH33_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH33_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH33_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH33_TASK_ID: channel33 task id register +func (o *SOC_ETM_Type) SetCH33_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH33_TASK_ID.Reg, volatile.LoadUint32(&o.CH33_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH33_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH33_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH34_EVT_ID: channel34 event id register +func (o *SOC_ETM_Type) SetCH34_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH34_EVT_ID.Reg, volatile.LoadUint32(&o.CH34_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH34_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH34_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH34_TASK_ID: channel34 task id register +func (o *SOC_ETM_Type) SetCH34_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH34_TASK_ID.Reg, volatile.LoadUint32(&o.CH34_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH34_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH34_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH35_EVT_ID: channel35 event id register +func (o *SOC_ETM_Type) SetCH35_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH35_EVT_ID.Reg, volatile.LoadUint32(&o.CH35_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH35_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH35_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH35_TASK_ID: channel35 task id register +func (o *SOC_ETM_Type) SetCH35_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH35_TASK_ID.Reg, volatile.LoadUint32(&o.CH35_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH35_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH35_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH36_EVT_ID: channel36 event id register +func (o *SOC_ETM_Type) SetCH36_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH36_EVT_ID.Reg, volatile.LoadUint32(&o.CH36_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH36_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH36_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH36_TASK_ID: channel36 task id register +func (o *SOC_ETM_Type) SetCH36_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH36_TASK_ID.Reg, volatile.LoadUint32(&o.CH36_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH36_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH36_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH37_EVT_ID: channel37 event id register +func (o *SOC_ETM_Type) SetCH37_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH37_EVT_ID.Reg, volatile.LoadUint32(&o.CH37_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH37_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH37_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH37_TASK_ID: channel37 task id register +func (o *SOC_ETM_Type) SetCH37_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH37_TASK_ID.Reg, volatile.LoadUint32(&o.CH37_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH37_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH37_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH38_EVT_ID: channel38 event id register +func (o *SOC_ETM_Type) SetCH38_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH38_EVT_ID.Reg, volatile.LoadUint32(&o.CH38_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH38_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH38_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH38_TASK_ID: channel38 task id register +func (o *SOC_ETM_Type) SetCH38_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH38_TASK_ID.Reg, volatile.LoadUint32(&o.CH38_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH38_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH38_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH39_EVT_ID: channel39 event id register +func (o *SOC_ETM_Type) SetCH39_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH39_EVT_ID.Reg, volatile.LoadUint32(&o.CH39_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH39_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH39_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH39_TASK_ID: channel39 task id register +func (o *SOC_ETM_Type) SetCH39_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH39_TASK_ID.Reg, volatile.LoadUint32(&o.CH39_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH39_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH39_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH40_EVT_ID: channel40 event id register +func (o *SOC_ETM_Type) SetCH40_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH40_EVT_ID.Reg, volatile.LoadUint32(&o.CH40_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH40_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH40_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH40_TASK_ID: channel40 task id register +func (o *SOC_ETM_Type) SetCH40_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH40_TASK_ID.Reg, volatile.LoadUint32(&o.CH40_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH40_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH40_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH41_EVT_ID: channel41 event id register +func (o *SOC_ETM_Type) SetCH41_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH41_EVT_ID.Reg, volatile.LoadUint32(&o.CH41_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH41_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH41_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH41_TASK_ID: channel41 task id register +func (o *SOC_ETM_Type) SetCH41_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH41_TASK_ID.Reg, volatile.LoadUint32(&o.CH41_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH41_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH41_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH42_EVT_ID: channel42 event id register +func (o *SOC_ETM_Type) SetCH42_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH42_EVT_ID.Reg, volatile.LoadUint32(&o.CH42_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH42_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH42_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH42_TASK_ID: channel42 task id register +func (o *SOC_ETM_Type) SetCH42_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH42_TASK_ID.Reg, volatile.LoadUint32(&o.CH42_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH42_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH42_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH43_EVT_ID: channel43 event id register +func (o *SOC_ETM_Type) SetCH43_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH43_EVT_ID.Reg, volatile.LoadUint32(&o.CH43_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH43_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH43_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH43_TASK_ID: channel43 task id register +func (o *SOC_ETM_Type) SetCH43_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH43_TASK_ID.Reg, volatile.LoadUint32(&o.CH43_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH43_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH43_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH44_EVT_ID: channel44 event id register +func (o *SOC_ETM_Type) SetCH44_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH44_EVT_ID.Reg, volatile.LoadUint32(&o.CH44_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH44_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH44_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH44_TASK_ID: channel44 task id register +func (o *SOC_ETM_Type) SetCH44_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH44_TASK_ID.Reg, volatile.LoadUint32(&o.CH44_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH44_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH44_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH45_EVT_ID: channel45 event id register +func (o *SOC_ETM_Type) SetCH45_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH45_EVT_ID.Reg, volatile.LoadUint32(&o.CH45_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH45_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH45_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH45_TASK_ID: channel45 task id register +func (o *SOC_ETM_Type) SetCH45_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH45_TASK_ID.Reg, volatile.LoadUint32(&o.CH45_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH45_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH45_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH46_EVT_ID: channel46 event id register +func (o *SOC_ETM_Type) SetCH46_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH46_EVT_ID.Reg, volatile.LoadUint32(&o.CH46_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH46_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH46_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH46_TASK_ID: channel46 task id register +func (o *SOC_ETM_Type) SetCH46_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH46_TASK_ID.Reg, volatile.LoadUint32(&o.CH46_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH46_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH46_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH47_EVT_ID: channel47 event id register +func (o *SOC_ETM_Type) SetCH47_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH47_EVT_ID.Reg, volatile.LoadUint32(&o.CH47_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH47_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH47_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH47_TASK_ID: channel47 task id register +func (o *SOC_ETM_Type) SetCH47_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH47_TASK_ID.Reg, volatile.LoadUint32(&o.CH47_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH47_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH47_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH48_EVT_ID: channel48 event id register +func (o *SOC_ETM_Type) SetCH48_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH48_EVT_ID.Reg, volatile.LoadUint32(&o.CH48_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH48_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH48_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH48_TASK_ID: channel48 task id register +func (o *SOC_ETM_Type) SetCH48_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH48_TASK_ID.Reg, volatile.LoadUint32(&o.CH48_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH48_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH48_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH49_EVT_ID: channel49 event id register +func (o *SOC_ETM_Type) SetCH49_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH49_EVT_ID.Reg, volatile.LoadUint32(&o.CH49_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH49_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH49_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH49_TASK_ID: channel49 task id register +func (o *SOC_ETM_Type) SetCH49_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH49_TASK_ID.Reg, volatile.LoadUint32(&o.CH49_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH49_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH49_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CLK_EN: etm clock enable register +func (o *SOC_ETM_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1 +} + +// SOC_ETM.DATE: etm date register +func (o *SOC_ETM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SOC_ETM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 0 +type SPI0_Type struct { + SPI_MEM_CMD volatile.Register32 // 0x0 + _ [4]byte + SPI_MEM_CTRL volatile.Register32 // 0x8 + SPI_MEM_CTRL1 volatile.Register32 // 0xC + SPI_MEM_CTRL2 volatile.Register32 // 0x10 + SPI_MEM_CLOCK volatile.Register32 // 0x14 + SPI_MEM_USER volatile.Register32 // 0x18 + SPI_MEM_USER1 volatile.Register32 // 0x1C + SPI_MEM_USER2 volatile.Register32 // 0x20 + _ [8]byte + SPI_MEM_RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + SPI_MEM_MISC volatile.Register32 // 0x34 + _ [4]byte + SPI_MEM_CACHE_FCTRL volatile.Register32 // 0x3C + SPI_MEM_CACHE_SCTRL volatile.Register32 // 0x40 + SPI_MEM_SRAM_CMD volatile.Register32 // 0x44 + SPI_MEM_SRAM_DRD_CMD volatile.Register32 // 0x48 + SPI_MEM_SRAM_DWR_CMD volatile.Register32 // 0x4C + SPI_MEM_SRAM_CLK volatile.Register32 // 0x50 + SPI_MEM_FSM volatile.Register32 // 0x54 + _ [104]byte + SPI_MEM_INT_ENA volatile.Register32 // 0xC0 + SPI_MEM_INT_CLR volatile.Register32 // 0xC4 + SPI_MEM_INT_RAW volatile.Register32 // 0xC8 + SPI_MEM_INT_ST volatile.Register32 // 0xCC + _ [4]byte + SPI_MEM_DDR volatile.Register32 // 0xD4 + SPI_SMEM_DDR volatile.Register32 // 0xD8 + _ [36]byte + SPI_FMEM_PMS0_ATTR volatile.Register32 // 0x100 + SPI_FMEM_PMS1_ATTR volatile.Register32 // 0x104 + SPI_FMEM_PMS2_ATTR volatile.Register32 // 0x108 + SPI_FMEM_PMS3_ATTR volatile.Register32 // 0x10C + SPI_FMEM_PMS0_ADDR volatile.Register32 // 0x110 + SPI_FMEM_PMS1_ADDR volatile.Register32 // 0x114 + SPI_FMEM_PMS2_ADDR volatile.Register32 // 0x118 + SPI_FMEM_PMS3_ADDR volatile.Register32 // 0x11C + SPI_FMEM_PMS0_SIZE volatile.Register32 // 0x120 + SPI_FMEM_PMS1_SIZE volatile.Register32 // 0x124 + SPI_FMEM_PMS2_SIZE volatile.Register32 // 0x128 + SPI_FMEM_PMS3_SIZE volatile.Register32 // 0x12C + SPI_SMEM_PMS0_ATTR volatile.Register32 // 0x130 + SPI_SMEM_PMS1_ATTR volatile.Register32 // 0x134 + SPI_SMEM_PMS2_ATTR volatile.Register32 // 0x138 + SPI_SMEM_PMS3_ATTR volatile.Register32 // 0x13C + SPI_SMEM_PMS0_ADDR volatile.Register32 // 0x140 + SPI_SMEM_PMS1_ADDR volatile.Register32 // 0x144 + SPI_SMEM_PMS2_ADDR volatile.Register32 // 0x148 + SPI_SMEM_PMS3_ADDR volatile.Register32 // 0x14C + SPI_SMEM_PMS0_SIZE volatile.Register32 // 0x150 + SPI_SMEM_PMS1_SIZE volatile.Register32 // 0x154 + SPI_SMEM_PMS2_SIZE volatile.Register32 // 0x158 + SPI_SMEM_PMS3_SIZE volatile.Register32 // 0x15C + _ [4]byte + SPI_MEM_PMS_REJECT volatile.Register32 // 0x164 + SPI_MEM_ECC_CTRL volatile.Register32 // 0x168 + SPI_MEM_ECC_ERR_ADDR volatile.Register32 // 0x16C + SPI_MEM_AXI_ERR_ADDR volatile.Register32 // 0x170 + SPI_SMEM_ECC_CTRL volatile.Register32 // 0x174 + _ [8]byte + SPI_MEM_TIMING_CALI volatile.Register32 // 0x180 + SPI_MEM_DIN_MODE volatile.Register32 // 0x184 + SPI_MEM_DIN_NUM volatile.Register32 // 0x188 + SPI_MEM_DOUT_MODE volatile.Register32 // 0x18C + SPI_SMEM_TIMING_CALI volatile.Register32 // 0x190 + SPI_SMEM_DIN_MODE volatile.Register32 // 0x194 + SPI_SMEM_DIN_NUM volatile.Register32 // 0x198 + SPI_SMEM_DOUT_MODE volatile.Register32 // 0x19C + SPI_SMEM_AC volatile.Register32 // 0x1A0 + _ [92]byte + SPI_MEM_CLOCK_GATE volatile.Register32 // 0x200 + _ [252]byte + SPI_MEM_XTS_PLAIN_BASE volatile.Register32 // 0x300 + _ [60]byte + SPI_MEM_XTS_LINESIZE volatile.Register32 // 0x340 + SPI_MEM_XTS_DESTINATION volatile.Register32 // 0x344 + SPI_MEM_XTS_PHYSICAL_ADDRESS volatile.Register32 // 0x348 + SPI_MEM_XTS_TRIGGER volatile.Register32 // 0x34C + SPI_MEM_XTS_RELEASE volatile.Register32 // 0x350 + SPI_MEM_XTS_DESTROY volatile.Register32 // 0x354 + SPI_MEM_XTS_STATE volatile.Register32 // 0x358 + SPI_MEM_XTS_DATE volatile.Register32 // 0x35C + _ [28]byte + SPI_MEM_MMU_ITEM_CONTENT volatile.Register32 // 0x37C + SPI_MEM_MMU_ITEM_INDEX volatile.Register32 // 0x380 + SPI_MEM_MMU_POWER_CTRL volatile.Register32 // 0x384 + SPI_MEM_DPA_CTRL volatile.Register32 // 0x388 + _ [100]byte + SPI_MEM_REGISTERRND_ECO_HIGH volatile.Register32 // 0x3F0 + SPI_MEM_REGISTERRND_ECO_LOW volatile.Register32 // 0x3F4 + _ [4]byte + SPI_MEM_DATE volatile.Register32 // 0x3FC +} + +// SPI0.SPI_MEM_CMD: SPI0 FSM status register +func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_MST_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_MST_ST() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf +} +func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_SLV_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf0)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_SLV_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf0) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_USR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000) >> 18 +} + +// SPI0.SPI_MEM_CTRL: SPI0 control register. +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_Q_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_Q_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_D_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_D_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CTRL1: SPI0 control1 register. +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x400000) >> 22 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RAM0_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RAM0_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CTRL2: SPI0 control2 register. +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1f)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1f +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x3e0)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x3e0) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1c00)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1c00) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x7e000000) >> 25 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CLOCK: SPI clock division control register. +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff +} +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_USER: SPI0 user register. +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x20000000) >> 29 +} + +// SPI0.SPI_MEM_USER1: SPI0 user1 register. +func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x3f)|value) +} +func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x3f +} +func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI0.SPI_MEM_USER2: SPI0 user2 register. +func (o *SPI0_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SPI_MEM_RD_STATUS: SPI0 read control register. +func (o *SPI0_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI0.SPI_MEM_MISC: SPI0 misc register +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_FSUB_PIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_FSUB_PIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_SSUB_PIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_SSUB_PIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x400) >> 10 +} + +// SPI0.SPI_MEM_CACHE_FCTRL: SPI0 bit mode control register. +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CACHE_SCTRL: SPI0 external RAM control register +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc00000)|value<<22) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc00000) >> 22 +} + +// SPI0.SPI_MEM_SRAM_CMD: SPI0 external RAM mode control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x3fc)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x3fc) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x400) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x800)|value<<11) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x800) >> 11 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x8000)|value<<15) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x8000) >> 15 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_SRAM_DRD_CMD: SPI0 external RAM DDR read command control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SPI_MEM_SRAM_DWR_CMD: SPI0 external RAM DDR write command control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SPI_MEM_SRAM_CLK: SPI0 external RAM clock control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_FSM: SPI0 FSM status register +func (o *SPI0_Type) SetSPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FSM.Reg, volatile.LoadUint32(&o.SPI_MEM_FSM.Reg)&^(0xf80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FSM.Reg) & 0xf80) >> 7 +} + +// SPI0.SPI_MEM_INT_ENA: SPI0 interrupt enable register +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x200) >> 9 +} + +// SPI0.SPI_MEM_INT_CLR: SPI0 interrupt clear register +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x200) >> 9 +} + +// SPI0.SPI_MEM_INT_RAW: SPI0 interrupt raw register +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x200) >> 9 +} + +// SPI0.SPI_MEM_INT_ST: SPI0 interrupt status register +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x200) >> 9 +} + +// SPI0.SPI_MEM_DDR: SPI0 flash DDR mode control register +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI0.SPI_SMEM_DDR: SPI0 external RAM DDR mode control register +func (o *SPI0_Type) SetSPI_SMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI0.SPI_FMEM_PMS0_ATTR: MSPI flash ACE section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS1_ATTR: MSPI flash ACE section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS2_ATTR: MSPI flash ACE section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS3_ATTR: MSPI flash ACE section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS0_ADDR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS0_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_FMEM_PMS1_ADDR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS1_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_FMEM_PMS2_ADDR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS2_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_FMEM_PMS3_ADDR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS3_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_FMEM_PMS0_SIZE: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS0_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS0_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_FMEM_PMS1_SIZE: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS1_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS1_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_FMEM_PMS2_SIZE: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS2_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS2_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_FMEM_PMS3_SIZE: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS3_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS3_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_SMEM_PMS0_ATTR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS1_ATTR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS2_ATTR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS3_ATTR: SPI1 flash ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS0_ADDR: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS0_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_SMEM_PMS1_ADDR: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS1_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_SMEM_PMS2_ADDR: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS2_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_SMEM_PMS3_ADDR: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS3_ADDR.Reg) & 0x3ffffff +} + +// SPI0.SPI_SMEM_PMS0_SIZE: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS0_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS0_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_SMEM_PMS1_SIZE: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS1_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS1_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_SMEM_PMS2_SIZE: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS2_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS2_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_SMEM_PMS3_SIZE: SPI1 external RAM ACE section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS3_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_SIZE.Reg)&^(0x3fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS3_SIZE.Reg) & 0x3fff +} + +// SPI0.SPI_MEM_PMS_REJECT: SPI1 access reject register +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x3ffffff +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PM_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PM_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_ECC_CTRL: MSPI ECC control register +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x1f800)|value<<11) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x1f800) >> 11 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0xc0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0xc0000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0xfe000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0xfe000000) >> 25 +} + +// SPI0.SPI_MEM_ECC_ERR_ADDR: MSPI ECC error address register +func (o *SPI0_Type) SetSPI_MEM_ECC_ERR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_ERR_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg) & 0x3ffffff +} +func (o *SPI0_Type) SetSPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg) & 0xfc000000) >> 26 +} + +// SPI0.SPI_MEM_AXI_ERR_ADDR: SPI0 AXI request error address. +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x3ffffff +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_SMEM_ECC_CTRL: MSPI ECC control register +func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0xc0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0xc0000) >> 18 +} +func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0x100000) >> 20 +} + +// SPI0.SPI_MEM_TIMING_CALI: SPI0 flash timing calibration register +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_UPDATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_UPDATE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x40) >> 6 +} + +// SPI0.SPI_MEM_DIN_MODE: MSPI flash input timing delay mode control register +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7000000) >> 24 +} + +// SPI0.SPI_MEM_DIN_NUM: MSPI flash input timing delay number control register +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x30000) >> 16 +} + +// SPI0.SPI_MEM_DOUT_MODE: MSPI flash output timing adjustment control register +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI0.SPI_SMEM_TIMING_CALI: MSPI external RAM timing calibration register +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x20) >> 5 +} + +// SPI0.SPI_SMEM_DIN_MODE: MSPI external RAM input timing delay mode control register +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000000) >> 24 +} + +// SPI0.SPI_SMEM_DIN_NUM: MSPI external RAM input timing delay number control register +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc000) >> 14 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30000) >> 16 +} + +// SPI0.SPI_SMEM_DOUT_MODE: MSPI external RAM output timing adjustment control register +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI0.SPI_SMEM_AC: MSPI external RAM ECC and SPI CS timing control register +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7c)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7c) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0xf80)|value<<7) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0xf80) >> 7 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x8000)|value<<15) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x8000) >> 15 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7e000000) >> 25 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CLOCK_GATE: SPI0 clock gate register +func (o *SPI0_Type) SetSPI_MEM_CLOCK_GATE_SPI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK_GATE.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_GATE_SPI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_PLAIN_BASE: The base address of the memory that stores plaintext in Manual Encryption +func (o *SPI0_Type) SetSPI_MEM_XTS_PLAIN_BASE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_PLAIN_BASE.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_PLAIN_BASE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_PLAIN_BASE.Reg) +} + +// SPI0.SPI_MEM_XTS_LINESIZE: Manual Encryption Line-Size register +func (o *SPI0_Type) SetSPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_LINESIZE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_LINESIZE.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_LINESIZE.Reg) & 0x3 +} + +// SPI0.SPI_MEM_XTS_DESTINATION: Manual Encryption destination register +func (o *SPI0_Type) SetSPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_DESTINATION.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DESTINATION.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_DESTINATION.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_PHYSICAL_ADDRESS: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg) & 0x3ffffff +} + +// SPI0.SPI_MEM_XTS_TRIGGER: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_TRIGGER.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_TRIGGER.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_TRIGGER.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_RELEASE: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_RELEASE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_RELEASE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_RELEASE.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_DESTROY: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_DESTROY.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DESTROY.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_DESTROY.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_STATE: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_STATE_SPI_XTS_STATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_STATE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_STATE.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_STATE_SPI_XTS_STATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_STATE.Reg) & 0x3 +} + +// SPI0.SPI_MEM_XTS_DATE: Manual Encryption version register +func (o *SPI0_Type) SetSPI_MEM_XTS_DATE_SPI_XTS_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_DATE_SPI_XTS_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_DATE.Reg) & 0x3fffffff +} + +// SPI0.SPI_MEM_MMU_ITEM_CONTENT: MSPI-MMU item content register +func (o *SPI0_Type) SetSPI_MEM_MMU_ITEM_CONTENT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_ITEM_CONTENT.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_ITEM_CONTENT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MMU_ITEM_CONTENT.Reg) +} + +// SPI0.SPI_MEM_MMU_ITEM_INDEX: MSPI-MMU item index register +func (o *SPI0_Type) SetSPI_MEM_MMU_ITEM_INDEX(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_ITEM_INDEX.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_ITEM_INDEX() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MMU_ITEM_INDEX.Reg) +} + +// SPI0.SPI_MEM_MMU_POWER_CTRL: MSPI MMU power control register +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x18) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x3fff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x3fff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_DPA_CTRL: SPI memory cryption DPA register +func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x10) >> 4 +} + +// SPI0.SPI_MEM_REGISTERRND_ECO_HIGH: MSPI ECO high register +func (o *SPI0_Type) SetSPI_MEM_REGISTERRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REGISTERRND_ECO_HIGH.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_REGISTERRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REGISTERRND_ECO_HIGH.Reg) +} + +// SPI0.SPI_MEM_REGISTERRND_ECO_LOW: MSPI ECO low register +func (o *SPI0_Type) SetSPI_MEM_REGISTERRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REGISTERRND_ECO_LOW.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_REGISTERRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REGISTERRND_ECO_LOW.Reg) +} + +// SPI0.SPI_MEM_DATE: SPI0 version control register +func (o *SPI0_Type) SetSPI_MEM_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 1 +type SPI1_Type struct { + SPI_MEM_CMD volatile.Register32 // 0x0 + SPI_MEM_ADDR volatile.Register32 // 0x4 + SPI_MEM_CTRL volatile.Register32 // 0x8 + SPI_MEM_CTRL1 volatile.Register32 // 0xC + SPI_MEM_CTRL2 volatile.Register32 // 0x10 + SPI_MEM_CLOCK volatile.Register32 // 0x14 + SPI_MEM_USER volatile.Register32 // 0x18 + SPI_MEM_USER1 volatile.Register32 // 0x1C + SPI_MEM_USER2 volatile.Register32 // 0x20 + SPI_MEM_MOSI_DLEN volatile.Register32 // 0x24 + SPI_MEM_MISO_DLEN volatile.Register32 // 0x28 + SPI_MEM_RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + SPI_MEM_MISC volatile.Register32 // 0x34 + SPI_MEM_TX_CRC volatile.Register32 // 0x38 + SPI_MEM_CACHE_FCTRL volatile.Register32 // 0x3C + _ [24]byte + SPI_MEM_W0 volatile.Register32 // 0x58 + SPI_MEM_W1 volatile.Register32 // 0x5C + SPI_MEM_W2 volatile.Register32 // 0x60 + SPI_MEM_W3 volatile.Register32 // 0x64 + SPI_MEM_W4 volatile.Register32 // 0x68 + SPI_MEM_W5 volatile.Register32 // 0x6C + SPI_MEM_W6 volatile.Register32 // 0x70 + SPI_MEM_W7 volatile.Register32 // 0x74 + SPI_MEM_W8 volatile.Register32 // 0x78 + SPI_MEM_W9 volatile.Register32 // 0x7C + SPI_MEM_W10 volatile.Register32 // 0x80 + SPI_MEM_W11 volatile.Register32 // 0x84 + SPI_MEM_W12 volatile.Register32 // 0x88 + SPI_MEM_W13 volatile.Register32 // 0x8C + SPI_MEM_W14 volatile.Register32 // 0x90 + SPI_MEM_W15 volatile.Register32 // 0x94 + SPI_MEM_FLASH_WAITI_CTRL volatile.Register32 // 0x98 + SPI_MEM_FLASH_SUS_CTRL volatile.Register32 // 0x9C + SPI_MEM_FLASH_SUS_CMD volatile.Register32 // 0xA0 + SPI_MEM_SUS_STATUS volatile.Register32 // 0xA4 + _ [24]byte + SPI_MEM_INT_ENA volatile.Register32 // 0xC0 + SPI_MEM_INT_CLR volatile.Register32 // 0xC4 + SPI_MEM_INT_RAW volatile.Register32 // 0xC8 + SPI_MEM_INT_ST volatile.Register32 // 0xCC + _ [4]byte + SPI_MEM_DDR volatile.Register32 // 0xD4 + _ [168]byte + SPI_MEM_TIMING_CALI volatile.Register32 // 0x180 + _ [124]byte + SPI_MEM_CLOCK_GATE volatile.Register32 // 0x200 + _ [504]byte + SPI_MEM_DATE volatile.Register32 // 0x3FC +} + +// SPI1.SPI_MEM_CMD: SPI1 memory command register +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_MST_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_MST_ST() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_SLV_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf0)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_SLV_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf0) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_PE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_PE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_USR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_HPM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_HPM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_DP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_DP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_CE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_CE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_BE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_BE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_SE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_SE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_PP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_PP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WRSR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WRSR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RDSR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RDSR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RDID(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RDID() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WRDI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WRDI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WREN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WREN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_READ(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_READ() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_ADDR: SPI1 address register +func (o *SPI1_Type) SetSPI_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ADDR.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_ADDR.Reg) +} + +// SPI1.SPI_MEM_CTRL: SPI1 control register. +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_TX_CRC_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_TX_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800) >> 11 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_RESANDRES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_RESANDRES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_Q_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_Q_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_D_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_D_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_WP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_WP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_WRSR_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_WRSR_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1000000) >> 24 +} + +// SPI1.SPI_MEM_CTRL1: SPI1 control1 register. +func (o *SPI1_Type) SetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x3 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0xffc)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0xffc) >> 2 +} + +// SPI1.SPI_MEM_CTRL2: SPI1 control2 register. +func (o *SPI1_Type) SetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_CLOCK: SPI1 clock division control register. +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff +} +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_USER: SPI1 user register. +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x1000) >> 12 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MISO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_USER1: SPI1 user1 register. +func (o *SPI1_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x3f)|value) +} +func (o *SPI1_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x3f +} +func (o *SPI1_Type) SetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI1.SPI_MEM_USER2: SPI1 user2 register. +func (o *SPI1_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI1.SPI_MEM_MOSI_DLEN: SPI1 send data bit length control register. +func (o *SPI1_Type) SetSPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MOSI_DLEN.Reg, volatile.LoadUint32(&o.SPI_MEM_MOSI_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MOSI_DLEN.Reg) & 0x3ff +} + +// SPI1.SPI_MEM_MISO_DLEN: SPI1 receive data bit length control register. +func (o *SPI1_Type) SetSPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISO_DLEN.Reg, volatile.LoadUint32(&o.SPI_MEM_MISO_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MISO_DLEN.Reg) & 0x3ff +} + +// SPI1.SPI_MEM_RD_STATUS: SPI1 status register. +func (o *SPI1_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_STATUS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_STATUS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI1.SPI_MEM_MISC: SPI1 misc register +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_TX_CRC: SPI1 TX CRC data register. +func (o *SPI1_Type) SetSPI_MEM_TX_CRC(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TX_CRC.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_TX_CRC() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_TX_CRC.Reg) +} + +// SPI1.SPI_MEM_CACHE_FCTRL: SPI1 bit mode control register. +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x100) >> 8 +} + +// SPI1.SPI_MEM_W0: SPI1 memory data buffer0 +func (o *SPI1_Type) SetSPI_MEM_W0(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W0.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W0() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W0.Reg) +} + +// SPI1.SPI_MEM_W1: SPI1 memory data buffer1 +func (o *SPI1_Type) SetSPI_MEM_W1(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W1.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W1() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W1.Reg) +} + +// SPI1.SPI_MEM_W2: SPI1 memory data buffer2 +func (o *SPI1_Type) SetSPI_MEM_W2(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W2.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W2() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W2.Reg) +} + +// SPI1.SPI_MEM_W3: SPI1 memory data buffer3 +func (o *SPI1_Type) SetSPI_MEM_W3(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W3.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W3() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W3.Reg) +} + +// SPI1.SPI_MEM_W4: SPI1 memory data buffer4 +func (o *SPI1_Type) SetSPI_MEM_W4(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W4.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W4() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W4.Reg) +} + +// SPI1.SPI_MEM_W5: SPI1 memory data buffer5 +func (o *SPI1_Type) SetSPI_MEM_W5(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W5.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W5() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W5.Reg) +} + +// SPI1.SPI_MEM_W6: SPI1 memory data buffer6 +func (o *SPI1_Type) SetSPI_MEM_W6(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W6.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W6() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W6.Reg) +} + +// SPI1.SPI_MEM_W7: SPI1 memory data buffer7 +func (o *SPI1_Type) SetSPI_MEM_W7(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W7.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W7() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W7.Reg) +} + +// SPI1.SPI_MEM_W8: SPI1 memory data buffer8 +func (o *SPI1_Type) SetSPI_MEM_W8(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W8.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W8() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W8.Reg) +} + +// SPI1.SPI_MEM_W9: SPI1 memory data buffer9 +func (o *SPI1_Type) SetSPI_MEM_W9(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W9.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W9() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W9.Reg) +} + +// SPI1.SPI_MEM_W10: SPI1 memory data buffer10 +func (o *SPI1_Type) SetSPI_MEM_W10(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W10.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W10() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W10.Reg) +} + +// SPI1.SPI_MEM_W11: SPI1 memory data buffer11 +func (o *SPI1_Type) SetSPI_MEM_W11(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W11.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W11() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W11.Reg) +} + +// SPI1.SPI_MEM_W12: SPI1 memory data buffer12 +func (o *SPI1_Type) SetSPI_MEM_W12(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W12.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W12() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W12.Reg) +} + +// SPI1.SPI_MEM_W13: SPI1 memory data buffer13 +func (o *SPI1_Type) SetSPI_MEM_W13(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W13.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W13() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W13.Reg) +} + +// SPI1.SPI_MEM_W14: SPI1 memory data buffer14 +func (o *SPI1_Type) SetSPI_MEM_W14(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W14.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W14() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W14.Reg) +} + +// SPI1.SPI_MEM_W15: SPI1 memory data buffer15 +func (o *SPI1_Type) SetSPI_MEM_W15(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W15.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W15() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W15.Reg) +} + +// SPI1.SPI_MEM_FLASH_WAITI_CTRL: SPI1 wait idle control register +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x18) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0xfc00)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0xfc00) >> 10 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SPI_MEM_FLASH_SUS_CTRL: SPI1 flash suspend control register +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x3fffc0)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x3fffc0) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0xfe000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0xfe000000) >> 25 +} + +// SPI1.SPI_MEM_FLASH_SUS_CMD: SPI1 flash suspend command register +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SPI_MEM_SUS_STATUS: SPI1 flash suspend status register +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SPI_MEM_INT_ENA: SPI1 interrupt enable register +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_INT_CLR: SPI1 interrupt clear register +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_INT_RAW: SPI1 interrupt raw register +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_INT_ST: SPI1 interrupt status register +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_DDR: SPI1 DDR control register +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI1.SPI_MEM_TIMING_CALI: SPI1 timing control register +func (o *SPI1_Type) SetSPI_MEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI1.SPI_MEM_CLOCK_GATE: SPI1 clk_gate register +func (o *SPI1_Type) SetSPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK_GATE.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg) & 0x1 +} + +// SPI1.SPI_MEM_DATE: Version control register +func (o *SPI1_Type) SetSPI_MEM_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 2 +type SPI2_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CLOCK volatile.Register32 // 0xC + USER volatile.Register32 // 0x10 + USER1 volatile.Register32 // 0x14 + USER2 volatile.Register32 // 0x18 + MS_DLEN volatile.Register32 // 0x1C + MISC volatile.Register32 // 0x20 + DIN_MODE volatile.Register32 // 0x24 + DIN_NUM volatile.Register32 // 0x28 + DOUT_MODE volatile.Register32 // 0x2C + DMA_CONF volatile.Register32 // 0x30 + DMA_INT_ENA volatile.Register32 // 0x34 + DMA_INT_CLR volatile.Register32 // 0x38 + DMA_INT_RAW volatile.Register32 // 0x3C + DMA_INT_ST volatile.Register32 // 0x40 + DMA_INT_SET volatile.Register32 // 0x44 + _ [80]byte + W0 volatile.Register32 // 0x98 + W1 volatile.Register32 // 0x9C + W2 volatile.Register32 // 0xA0 + W3 volatile.Register32 // 0xA4 + W4 volatile.Register32 // 0xA8 + W5 volatile.Register32 // 0xAC + W6 volatile.Register32 // 0xB0 + W7 volatile.Register32 // 0xB4 + W8 volatile.Register32 // 0xB8 + W9 volatile.Register32 // 0xBC + W10 volatile.Register32 // 0xC0 + W11 volatile.Register32 // 0xC4 + W12 volatile.Register32 // 0xC8 + W13 volatile.Register32 // 0xCC + W14 volatile.Register32 // 0xD0 + W15 volatile.Register32 // 0xD4 + _ [8]byte + SLAVE volatile.Register32 // 0xE0 + SLAVE1 volatile.Register32 // 0xE4 + CLK_GATE volatile.Register32 // 0xE8 + _ [4]byte + DATE volatile.Register32 // 0xF0 +} + +// SPI2.CMD: Command control register +func (o *SPI2_Type) SetCMD_CONF_BITLEN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetCMD_CONF_BITLEN() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetCMD_UPDATE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetCMD_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} + +// SPI2.ADDR: Address value register +func (o *SPI2_Type) SetADDR(value uint32) { + volatile.StoreUint32(&o.ADDR.Reg, value) +} +func (o *SPI2_Type) GetADDR() uint32 { + return volatile.LoadUint32(&o.ADDR.Reg) +} + +// SPI2.CTRL: SPI control register +func (o *SPI2_Type) SetCTRL_DUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetCTRL_DUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetCTRL_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetCTRL_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetCTRL_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetCTRL_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetCTRL_FREAD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetCTRL_FREAD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetCTRL_HOLD_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetCTRL_HOLD_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetCTRL_WP_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetCTRL_WP_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetCTRL_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1800000)|value<<23) +} +func (o *SPI2_Type) GetCTRL_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1800000) >> 23 +} +func (o *SPI2_Type) SetCTRL_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x6000000)|value<<25) +} +func (o *SPI2_Type) GetCTRL_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x6000000) >> 25 +} + +// SPI2.CLOCK: SPI clock control register +func (o *SPI2_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI2_Type) SetCLOCK_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3c0000)|value<<18) +} +func (o *SPI2_Type) GetCLOCK_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3c0000) >> 18 +} +func (o *SPI2_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER: SPI USER control register +func (o *SPI2_Type) SetUSER_DOUTDIN(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetUSER_DOUTDIN() uint32 { + return volatile.LoadUint32(&o.USER.Reg) & 0x1 +} +func (o *SPI2_Type) SetUSER_QPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetUSER_QPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetUSER_OPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetUSER_OPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetUSER_TSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetUSER_TSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetUSER_RSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetUSER_RSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetUSER_FWRITE_OCT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetUSER_FWRITE_OCT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetUSER_USR_CONF_NXT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetUSER_USR_CONF_NXT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetUSER_SIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetUSER_SIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI2_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER1: SPI USER control register 1 +func (o *SPI2_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xff)|value) +} +func (o *SPI2_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0xff +} +func (o *SPI2_Type) SetUSER1_MST_WFULL_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetUSER1_MST_WFULL_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetUSER1_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3e0000)|value<<17) +} +func (o *SPI2_Type) GetUSER1_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x3e0000) >> 17 +} +func (o *SPI2_Type) SetUSER1_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x7c00000)|value<<22) +} +func (o *SPI2_Type) GetUSER1_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x7c00000) >> 22 +} +func (o *SPI2_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xf8000000) >> 27 +} + +// SPI2.USER2: SPI USER control register 2 +func (o *SPI2_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI2_Type) SetUSER2_MST_REMPTY_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER2_MST_REMPTY_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI2.MS_DLEN: SPI data bit length control register +func (o *SPI2_Type) SetMS_DLEN_MS_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.MS_DLEN.Reg, volatile.LoadUint32(&o.MS_DLEN.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetMS_DLEN_MS_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.MS_DLEN.Reg) & 0x3ffff +} + +// SPI2.MISC: SPI misc register +func (o *SPI2_Type) SetMISC_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetMISC_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.MISC.Reg) & 0x1 +} +func (o *SPI2_Type) SetMISC_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetMISC_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetMISC_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetMISC_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetMISC_CS3_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetMISC_CS3_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetMISC_CS4_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetMISC_CS4_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetMISC_CS5_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetMISC_CS5_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetMISC_CK_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetMISC_CK_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetMISC_MASTER_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1f80)|value<<7) +} +func (o *SPI2_Type) GetMISC_MASTER_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1f80) >> 7 +} +func (o *SPI2_Type) SetMISC_CLK_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetMISC_CLK_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetMISC_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetMISC_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetMISC_ADDR_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetMISC_ADDR_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetMISC_CMD_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetMISC_CMD_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetMISC_SLAVE_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetMISC_SLAVE_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetMISC_DQS_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetMISC_DQS_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetMISC_QUAD_DIN_PIN_SWAP(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetMISC_QUAD_DIN_PIN_SWAP() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000000) >> 31 +} + +// SPI2.DIN_MODE: SPI input delay mode configuration +func (o *SPI2_Type) SetDIN_MODE_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_MODE_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_MODE_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_MODE_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_MODE_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_MODE_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_MODE_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_MODE_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetDIN_MODE_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetDIN_MODE_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetDIN_MODE_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetDIN_MODE_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetDIN_MODE_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetDIN_MODE_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetDIN_MODE_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetDIN_MODE_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc000) >> 14 +} +func (o *SPI2_Type) SetDIN_MODE_TIMING_HCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDIN_MODE_TIMING_HCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x10000) >> 16 +} + +// SPI2.DIN_NUM: SPI input delay number configuration +func (o *SPI2_Type) SetDIN_NUM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_NUM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_NUM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_NUM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_NUM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_NUM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_NUM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_NUM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetDIN_NUM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetDIN_NUM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetDIN_NUM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetDIN_NUM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetDIN_NUM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetDIN_NUM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetDIN_NUM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetDIN_NUM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc000) >> 14 +} + +// SPI2.DOUT_MODE: SPI output delay mode configuration +func (o *SPI2_Type) SetDOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDOUT_MODE_D_DQS_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDOUT_MODE_D_DQS_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI2.DMA_CONF: SPI DMA control register +func (o *SPI2_Type) SetDMA_CONF_DMA_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_OUTFIFO_EMPTY() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_INFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_SLV_SEG_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_SLV_SEG_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetDMA_CONF_RX_EOF_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetDMA_CONF_RX_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_RX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_RX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_TX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_TX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetDMA_CONF_RX_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetDMA_CONF_RX_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetDMA_CONF_BUF_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetDMA_CONF_BUF_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// SPI2.DMA_INT_ENA: SPI interrupt enable register +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EX_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EX_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EN_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EN_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMDA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMDA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ENA_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ENA_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_CLR: SPI interrupt clear register +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EX_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EX_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EN_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EN_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD8_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD8_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD9_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD9_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMDA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMDA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_CLR_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_CLR_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_RAW: SPI interrupt raw register +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EX_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EX_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EN_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EN_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD8_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD8_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD9_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD9_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMDA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMDA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_RAW_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_RAW_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_ST: SPI interrupt status register +func (o *SPI2_Type) SetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EX_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EX_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EN_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EN_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD7_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD8_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD8_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD9_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD9_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMDA_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMDA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ST_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ST_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_SET: SPI interrupt software set register +func (o *SPI2_Type) SetDMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET() uint32 { + return volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_EX_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_EX_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_EN_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_EN_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD7_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD7_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD8_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD8_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD9_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD9_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMDA_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMDA_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_RD_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_RD_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_WR_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_WR_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_RD_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_RD_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_WR_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_WR_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_SET_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_SET_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_SET_SEG_MAGIC_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_SET_SEG_MAGIC_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_SET_APP2_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_SET_APP2_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_SET_APP1_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_SET_APP1_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x100000) >> 20 +} + +// SPI2.W0: SPI CPU-controlled buffer0 +func (o *SPI2_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI2_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI2.W1: SPI CPU-controlled buffer1 +func (o *SPI2_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI2_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI2.W2: SPI CPU-controlled buffer2 +func (o *SPI2_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI2_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI2.W3: SPI CPU-controlled buffer3 +func (o *SPI2_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI2_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI2.W4: SPI CPU-controlled buffer4 +func (o *SPI2_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI2_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI2.W5: SPI CPU-controlled buffer5 +func (o *SPI2_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI2_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI2.W6: SPI CPU-controlled buffer6 +func (o *SPI2_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI2_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI2.W7: SPI CPU-controlled buffer7 +func (o *SPI2_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI2_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI2.W8: SPI CPU-controlled buffer8 +func (o *SPI2_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI2_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI2.W9: SPI CPU-controlled buffer9 +func (o *SPI2_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI2_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI2.W10: SPI CPU-controlled buffer10 +func (o *SPI2_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI2_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI2.W11: SPI CPU-controlled buffer11 +func (o *SPI2_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI2_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI2.W12: SPI CPU-controlled buffer12 +func (o *SPI2_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI2_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI2.W13: SPI CPU-controlled buffer13 +func (o *SPI2_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI2_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI2.W14: SPI CPU-controlled buffer14 +func (o *SPI2_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI2_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI2.W15: SPI CPU-controlled buffer15 +func (o *SPI2_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI2_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI2.SLAVE: SPI slave control register +func (o *SPI2_Type) SetSLAVE_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SLAVE.Reg) & 0x3 +} +func (o *SPI2_Type) SetSLAVE_CLK_MODE_13(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE_13() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSLAVE_RSCK_DATA_OUT(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSLAVE_RSCK_DATA_OUT() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSLAVE_DMA_SEG_MAGIC_VALUE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3c00000)|value<<22) +} +func (o *SPI2_Type) GetSLAVE_DMA_SEG_MAGIC_VALUE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x3c00000) >> 22 +} +func (o *SPI2_Type) SetSLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetSLAVE_SOFT_RESET(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetSLAVE_SOFT_RESET() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetSLAVE_USR_CONF(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetSLAVE_USR_CONF() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetSLAVE_MST_FD_WAIT_DMA_TX_DATA(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetSLAVE_MST_FD_WAIT_DMA_TX_DATA() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x20000000) >> 29 +} + +// SPI2.SLAVE1: SPI slave control register 1 +func (o *SPI2_Type) SetSLAVE1_SLV_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetSLAVE1_SLV_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_COMMAND(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3fc0000)|value<<18) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3fc0000) >> 18 +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_ADDR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0xfc000000) >> 26 +} + +// SPI2.CLK_GATE: SPI module clock and register clock control +func (o *SPI2_Type) SetCLK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetCLK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x4) >> 2 +} + +// SPI2.DATE: Version control +func (o *SPI2_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI2_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// System Timer +type SYSTIMER_Type struct { + CONF volatile.Register32 // 0x0 + UNIT0_OP volatile.Register32 // 0x4 + UNIT1_OP volatile.Register32 // 0x8 + UNIT0_LOAD_HI volatile.Register32 // 0xC + UNIT0_LOAD_LO volatile.Register32 // 0x10 + UNIT1_LOAD_HI volatile.Register32 // 0x14 + UNIT1_LOAD_LO volatile.Register32 // 0x18 + TARGET0_HI volatile.Register32 // 0x1C + TARGET0_LO volatile.Register32 // 0x20 + TARGET1_HI volatile.Register32 // 0x24 + TARGET1_LO volatile.Register32 // 0x28 + TARGET2_HI volatile.Register32 // 0x2C + TARGET2_LO volatile.Register32 // 0x30 + TARGET0_CONF volatile.Register32 // 0x34 + TARGET1_CONF volatile.Register32 // 0x38 + TARGET2_CONF volatile.Register32 // 0x3C + UNIT0_VALUE_HI volatile.Register32 // 0x40 + UNIT0_VALUE_LO volatile.Register32 // 0x44 + UNIT1_VALUE_HI volatile.Register32 // 0x48 + UNIT1_VALUE_LO volatile.Register32 // 0x4C + COMP0_LOAD volatile.Register32 // 0x50 + COMP1_LOAD volatile.Register32 // 0x54 + COMP2_LOAD volatile.Register32 // 0x58 + UNIT0_LOAD volatile.Register32 // 0x5C + UNIT1_LOAD volatile.Register32 // 0x60 + INT_ENA volatile.Register32 // 0x64 + INT_RAW volatile.Register32 // 0x68 + INT_CLR volatile.Register32 // 0x6C + INT_ST volatile.Register32 // 0x70 + REAL_TARGET0_LO volatile.Register32 // 0x74 + REAL_TARGET0_HI volatile.Register32 // 0x78 + REAL_TARGET1_LO volatile.Register32 // 0x7C + REAL_TARGET1_HI volatile.Register32 // 0x80 + REAL_TARGET2_LO volatile.Register32 // 0x84 + REAL_TARGET2_HI volatile.Register32 // 0x88 + _ [112]byte + DATE volatile.Register32 // 0xFC +} + +// SYSTIMER.CONF: Configure system timer clock +func (o *SYSTIMER_Type) SetCONF_SYSTIMER_CLK_FO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCONF_SYSTIMER_CLK_FO() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetCONF_ETM_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetCONF_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetCONF_TARGET2_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTIMER_Type) GetCONF_TARGET2_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22 +} +func (o *SYSTIMER_Type) SetCONF_TARGET1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTIMER_Type) GetCONF_TARGET1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23 +} +func (o *SYSTIMER_Type) SetCONF_TARGET0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTIMER_Type) GetCONF_TARGET0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000000) >> 26 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000000) >> 27 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000000) >> 28 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_OP: system timer unit0 value update register +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT1_OP: system timer unit1 value update register +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT0_LOAD_HI: system timer unit0 value high load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_LOAD_LO: system timer unit0 value low load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_LO.Reg) +} + +// SYSTIMER.UNIT1_LOAD_HI: system timer unit1 value high load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_LOAD_LO: system timer unit1 value low load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_LO.Reg) +} + +// SYSTIMER.TARGET0_HI: system timer comp0 value high register +func (o *SYSTIMER_Type) SetTARGET0_HI_TIMER_TARGET0_HI(value uint32) { + volatile.StoreUint32(&o.TARGET0_HI.Reg, volatile.LoadUint32(&o.TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_HI_TIMER_TARGET0_HI() uint32 { + return volatile.LoadUint32(&o.TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET0_LO: system timer comp0 value low register +func (o *SYSTIMER_Type) SetTARGET0_LO(value uint32) { + volatile.StoreUint32(&o.TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET0_LO() uint32 { + return volatile.LoadUint32(&o.TARGET0_LO.Reg) +} + +// SYSTIMER.TARGET1_HI: system timer comp1 value high register +func (o *SYSTIMER_Type) SetTARGET1_HI_TIMER_TARGET1_HI(value uint32) { + volatile.StoreUint32(&o.TARGET1_HI.Reg, volatile.LoadUint32(&o.TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_HI_TIMER_TARGET1_HI() uint32 { + return volatile.LoadUint32(&o.TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET1_LO: system timer comp1 value low register +func (o *SYSTIMER_Type) SetTARGET1_LO(value uint32) { + volatile.StoreUint32(&o.TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET1_LO() uint32 { + return volatile.LoadUint32(&o.TARGET1_LO.Reg) +} + +// SYSTIMER.TARGET2_HI: system timer comp2 value high register +func (o *SYSTIMER_Type) SetTARGET2_HI_TIMER_TARGET2_HI(value uint32) { + volatile.StoreUint32(&o.TARGET2_HI.Reg, volatile.LoadUint32(&o.TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_HI_TIMER_TARGET2_HI() uint32 { + return volatile.LoadUint32(&o.TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET2_LO: system timer comp2 value low register +func (o *SYSTIMER_Type) SetTARGET2_LO(value uint32) { + volatile.StoreUint32(&o.TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET2_LO() uint32 { + return volatile.LoadUint32(&o.TARGET2_LO.Reg) +} + +// SYSTIMER.TARGET0_CONF: system timer comp0 target mode register +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET1_CONF: system timer comp1 target mode register +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET2_CONF: system timer comp2 target mode register +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_VALUE_HI: system timer unit0 value high register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_VALUE_LO: system timer unit0 value low register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_LO.Reg) +} + +// SYSTIMER.UNIT1_VALUE_HI: system timer unit1 value high register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_VALUE_LO: system timer unit1 value low register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_LO.Reg) +} + +// SYSTIMER.COMP0_LOAD: system timer comp0 conf sync register +func (o *SYSTIMER_Type) SetCOMP0_LOAD_TIMER_COMP0_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP0_LOAD.Reg, volatile.LoadUint32(&o.COMP0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP0_LOAD_TIMER_COMP0_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP1_LOAD: system timer comp1 conf sync register +func (o *SYSTIMER_Type) SetCOMP1_LOAD_TIMER_COMP1_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP1_LOAD.Reg, volatile.LoadUint32(&o.COMP1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP1_LOAD_TIMER_COMP1_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP2_LOAD: system timer comp2 conf sync register +func (o *SYSTIMER_Type) SetCOMP2_LOAD_TIMER_COMP2_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP2_LOAD.Reg, volatile.LoadUint32(&o.COMP2_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP2_LOAD_TIMER_COMP2_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP2_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT0_LOAD: system timer unit0 conf sync register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_TIMER_UNIT0_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD.Reg, volatile.LoadUint32(&o.UNIT0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_TIMER_UNIT0_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT1_LOAD: system timer unit1 conf sync register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_TIMER_UNIT1_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD.Reg, volatile.LoadUint32(&o.UNIT1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_TIMER_UNIT1_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.INT_ENA: systimer interrupt enable register +func (o *SYSTIMER_Type) SetINT_ENA_TARGET0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_RAW: systimer interrupt raw register +func (o *SYSTIMER_Type) SetINT_RAW_TARGET0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_CLR: systimer interrupt clear register +func (o *SYSTIMER_Type) SetINT_CLR_TARGET0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_ST: systimer interrupt status register +func (o *SYSTIMER_Type) SetINT_ST_TARGET0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// SYSTIMER.REAL_TARGET0_LO: system timer comp0 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET0_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET0_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET0_LO.Reg) +} + +// SYSTIMER.REAL_TARGET0_HI: system timer comp0 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET0_HI_TARGET0_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET0_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET0_HI_TARGET0_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.REAL_TARGET1_LO: system timer comp1 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET1_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET1_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET1_LO.Reg) +} + +// SYSTIMER.REAL_TARGET1_HI: system timer comp1 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET1_HI_TARGET1_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET1_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET1_HI_TARGET1_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.REAL_TARGET2_LO: system timer comp2 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET2_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET2_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET2_LO.Reg) +} + +// SYSTIMER.REAL_TARGET2_HI: system timer comp2 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET2_HI_TARGET2_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET2_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET2_HI_TARGET2_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.DATE: system timer version control register +func (o *SYSTIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *SYSTIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// TEE Peripheral +type TEE_Type struct { + M0_MODE_CTRL volatile.Register32 // 0x0 + M1_MODE_CTRL volatile.Register32 // 0x4 + M2_MODE_CTRL volatile.Register32 // 0x8 + M3_MODE_CTRL volatile.Register32 // 0xC + M4_MODE_CTRL volatile.Register32 // 0x10 + M5_MODE_CTRL volatile.Register32 // 0x14 + M6_MODE_CTRL volatile.Register32 // 0x18 + M7_MODE_CTRL volatile.Register32 // 0x1C + M8_MODE_CTRL volatile.Register32 // 0x20 + M9_MODE_CTRL volatile.Register32 // 0x24 + M10_MODE_CTRL volatile.Register32 // 0x28 + M11_MODE_CTRL volatile.Register32 // 0x2C + M12_MODE_CTRL volatile.Register32 // 0x30 + M13_MODE_CTRL volatile.Register32 // 0x34 + M14_MODE_CTRL volatile.Register32 // 0x38 + M15_MODE_CTRL volatile.Register32 // 0x3C + M16_MODE_CTRL volatile.Register32 // 0x40 + M17_MODE_CTRL volatile.Register32 // 0x44 + M18_MODE_CTRL volatile.Register32 // 0x48 + M19_MODE_CTRL volatile.Register32 // 0x4C + M20_MODE_CTRL volatile.Register32 // 0x50 + M21_MODE_CTRL volatile.Register32 // 0x54 + M22_MODE_CTRL volatile.Register32 // 0x58 + M23_MODE_CTRL volatile.Register32 // 0x5C + M24_MODE_CTRL volatile.Register32 // 0x60 + M25_MODE_CTRL volatile.Register32 // 0x64 + M26_MODE_CTRL volatile.Register32 // 0x68 + M27_MODE_CTRL volatile.Register32 // 0x6C + M28_MODE_CTRL volatile.Register32 // 0x70 + M29_MODE_CTRL volatile.Register32 // 0x74 + M30_MODE_CTRL volatile.Register32 // 0x78 + M31_MODE_CTRL volatile.Register32 // 0x7C + CLOCK_GATE volatile.Register32 // 0x80 + _ [3960]byte + DATE volatile.Register32 // 0xFFC +} + +// TEE.M0_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM0_MODE_CTRL_M0_MODE(value uint32) { + volatile.StoreUint32(&o.M0_MODE_CTRL.Reg, volatile.LoadUint32(&o.M0_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM0_MODE_CTRL_M0_MODE() uint32 { + return volatile.LoadUint32(&o.M0_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M1_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM1_MODE_CTRL_M1_MODE(value uint32) { + volatile.StoreUint32(&o.M1_MODE_CTRL.Reg, volatile.LoadUint32(&o.M1_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM1_MODE_CTRL_M1_MODE() uint32 { + return volatile.LoadUint32(&o.M1_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M2_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM2_MODE_CTRL_M2_MODE(value uint32) { + volatile.StoreUint32(&o.M2_MODE_CTRL.Reg, volatile.LoadUint32(&o.M2_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM2_MODE_CTRL_M2_MODE() uint32 { + return volatile.LoadUint32(&o.M2_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M3_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM3_MODE_CTRL_M3_MODE(value uint32) { + volatile.StoreUint32(&o.M3_MODE_CTRL.Reg, volatile.LoadUint32(&o.M3_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM3_MODE_CTRL_M3_MODE() uint32 { + return volatile.LoadUint32(&o.M3_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M4_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM4_MODE_CTRL_M4_MODE(value uint32) { + volatile.StoreUint32(&o.M4_MODE_CTRL.Reg, volatile.LoadUint32(&o.M4_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM4_MODE_CTRL_M4_MODE() uint32 { + return volatile.LoadUint32(&o.M4_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M5_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM5_MODE_CTRL_M5_MODE(value uint32) { + volatile.StoreUint32(&o.M5_MODE_CTRL.Reg, volatile.LoadUint32(&o.M5_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM5_MODE_CTRL_M5_MODE() uint32 { + return volatile.LoadUint32(&o.M5_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M6_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM6_MODE_CTRL_M6_MODE(value uint32) { + volatile.StoreUint32(&o.M6_MODE_CTRL.Reg, volatile.LoadUint32(&o.M6_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM6_MODE_CTRL_M6_MODE() uint32 { + return volatile.LoadUint32(&o.M6_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M7_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM7_MODE_CTRL_M7_MODE(value uint32) { + volatile.StoreUint32(&o.M7_MODE_CTRL.Reg, volatile.LoadUint32(&o.M7_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM7_MODE_CTRL_M7_MODE() uint32 { + return volatile.LoadUint32(&o.M7_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M8_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM8_MODE_CTRL_M8_MODE(value uint32) { + volatile.StoreUint32(&o.M8_MODE_CTRL.Reg, volatile.LoadUint32(&o.M8_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM8_MODE_CTRL_M8_MODE() uint32 { + return volatile.LoadUint32(&o.M8_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M9_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM9_MODE_CTRL_M9_MODE(value uint32) { + volatile.StoreUint32(&o.M9_MODE_CTRL.Reg, volatile.LoadUint32(&o.M9_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM9_MODE_CTRL_M9_MODE() uint32 { + return volatile.LoadUint32(&o.M9_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M10_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM10_MODE_CTRL_M10_MODE(value uint32) { + volatile.StoreUint32(&o.M10_MODE_CTRL.Reg, volatile.LoadUint32(&o.M10_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM10_MODE_CTRL_M10_MODE() uint32 { + return volatile.LoadUint32(&o.M10_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M11_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM11_MODE_CTRL_M11_MODE(value uint32) { + volatile.StoreUint32(&o.M11_MODE_CTRL.Reg, volatile.LoadUint32(&o.M11_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM11_MODE_CTRL_M11_MODE() uint32 { + return volatile.LoadUint32(&o.M11_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M12_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM12_MODE_CTRL_M12_MODE(value uint32) { + volatile.StoreUint32(&o.M12_MODE_CTRL.Reg, volatile.LoadUint32(&o.M12_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM12_MODE_CTRL_M12_MODE() uint32 { + return volatile.LoadUint32(&o.M12_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M13_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM13_MODE_CTRL_M13_MODE(value uint32) { + volatile.StoreUint32(&o.M13_MODE_CTRL.Reg, volatile.LoadUint32(&o.M13_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM13_MODE_CTRL_M13_MODE() uint32 { + return volatile.LoadUint32(&o.M13_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M14_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM14_MODE_CTRL_M14_MODE(value uint32) { + volatile.StoreUint32(&o.M14_MODE_CTRL.Reg, volatile.LoadUint32(&o.M14_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM14_MODE_CTRL_M14_MODE() uint32 { + return volatile.LoadUint32(&o.M14_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M15_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM15_MODE_CTRL_M15_MODE(value uint32) { + volatile.StoreUint32(&o.M15_MODE_CTRL.Reg, volatile.LoadUint32(&o.M15_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM15_MODE_CTRL_M15_MODE() uint32 { + return volatile.LoadUint32(&o.M15_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M16_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM16_MODE_CTRL_M16_MODE(value uint32) { + volatile.StoreUint32(&o.M16_MODE_CTRL.Reg, volatile.LoadUint32(&o.M16_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM16_MODE_CTRL_M16_MODE() uint32 { + return volatile.LoadUint32(&o.M16_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M17_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM17_MODE_CTRL_M17_MODE(value uint32) { + volatile.StoreUint32(&o.M17_MODE_CTRL.Reg, volatile.LoadUint32(&o.M17_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM17_MODE_CTRL_M17_MODE() uint32 { + return volatile.LoadUint32(&o.M17_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M18_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM18_MODE_CTRL_M18_MODE(value uint32) { + volatile.StoreUint32(&o.M18_MODE_CTRL.Reg, volatile.LoadUint32(&o.M18_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM18_MODE_CTRL_M18_MODE() uint32 { + return volatile.LoadUint32(&o.M18_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M19_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM19_MODE_CTRL_M19_MODE(value uint32) { + volatile.StoreUint32(&o.M19_MODE_CTRL.Reg, volatile.LoadUint32(&o.M19_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM19_MODE_CTRL_M19_MODE() uint32 { + return volatile.LoadUint32(&o.M19_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M20_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM20_MODE_CTRL_M20_MODE(value uint32) { + volatile.StoreUint32(&o.M20_MODE_CTRL.Reg, volatile.LoadUint32(&o.M20_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM20_MODE_CTRL_M20_MODE() uint32 { + return volatile.LoadUint32(&o.M20_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M21_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM21_MODE_CTRL_M21_MODE(value uint32) { + volatile.StoreUint32(&o.M21_MODE_CTRL.Reg, volatile.LoadUint32(&o.M21_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM21_MODE_CTRL_M21_MODE() uint32 { + return volatile.LoadUint32(&o.M21_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M22_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM22_MODE_CTRL_M22_MODE(value uint32) { + volatile.StoreUint32(&o.M22_MODE_CTRL.Reg, volatile.LoadUint32(&o.M22_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM22_MODE_CTRL_M22_MODE() uint32 { + return volatile.LoadUint32(&o.M22_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M23_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM23_MODE_CTRL_M23_MODE(value uint32) { + volatile.StoreUint32(&o.M23_MODE_CTRL.Reg, volatile.LoadUint32(&o.M23_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM23_MODE_CTRL_M23_MODE() uint32 { + return volatile.LoadUint32(&o.M23_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M24_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM24_MODE_CTRL_M24_MODE(value uint32) { + volatile.StoreUint32(&o.M24_MODE_CTRL.Reg, volatile.LoadUint32(&o.M24_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM24_MODE_CTRL_M24_MODE() uint32 { + return volatile.LoadUint32(&o.M24_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M25_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM25_MODE_CTRL_M25_MODE(value uint32) { + volatile.StoreUint32(&o.M25_MODE_CTRL.Reg, volatile.LoadUint32(&o.M25_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM25_MODE_CTRL_M25_MODE() uint32 { + return volatile.LoadUint32(&o.M25_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M26_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM26_MODE_CTRL_M26_MODE(value uint32) { + volatile.StoreUint32(&o.M26_MODE_CTRL.Reg, volatile.LoadUint32(&o.M26_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM26_MODE_CTRL_M26_MODE() uint32 { + return volatile.LoadUint32(&o.M26_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M27_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM27_MODE_CTRL_M27_MODE(value uint32) { + volatile.StoreUint32(&o.M27_MODE_CTRL.Reg, volatile.LoadUint32(&o.M27_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM27_MODE_CTRL_M27_MODE() uint32 { + return volatile.LoadUint32(&o.M27_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M28_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM28_MODE_CTRL_M28_MODE(value uint32) { + volatile.StoreUint32(&o.M28_MODE_CTRL.Reg, volatile.LoadUint32(&o.M28_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM28_MODE_CTRL_M28_MODE() uint32 { + return volatile.LoadUint32(&o.M28_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M29_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM29_MODE_CTRL_M29_MODE(value uint32) { + volatile.StoreUint32(&o.M29_MODE_CTRL.Reg, volatile.LoadUint32(&o.M29_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM29_MODE_CTRL_M29_MODE() uint32 { + return volatile.LoadUint32(&o.M29_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M30_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM30_MODE_CTRL_M30_MODE(value uint32) { + volatile.StoreUint32(&o.M30_MODE_CTRL.Reg, volatile.LoadUint32(&o.M30_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM30_MODE_CTRL_M30_MODE() uint32 { + return volatile.LoadUint32(&o.M30_MODE_CTRL.Reg) & 0x3 +} + +// TEE.M31_MODE_CTRL: Tee mode control register +func (o *TEE_Type) SetM31_MODE_CTRL_M31_MODE(value uint32) { + volatile.StoreUint32(&o.M31_MODE_CTRL.Reg, volatile.LoadUint32(&o.M31_MODE_CTRL.Reg)&^(0x3)|value) +} +func (o *TEE_Type) GetM31_MODE_CTRL_M31_MODE() uint32 { + return volatile.LoadUint32(&o.M31_MODE_CTRL.Reg) & 0x3 +} + +// TEE.CLOCK_GATE: Clock gating register +func (o *TEE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *TEE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// TEE.DATE: Version register +func (o *TEE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *TEE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Timer Group 0 +type TIMG_Type struct { + T0CONFIG volatile.Register32 // 0x0 + T0LO volatile.Register32 // 0x4 + T0HI volatile.Register32 // 0x8 + T0UPDATE volatile.Register32 // 0xC + T0ALARMLO volatile.Register32 // 0x10 + T0ALARMHI volatile.Register32 // 0x14 + T0LOADLO volatile.Register32 // 0x18 + T0LOADHI volatile.Register32 // 0x1C + T0LOAD volatile.Register32 // 0x20 + _ [36]byte + WDTCONFIG0 volatile.Register32 // 0x48 + WDTCONFIG1 volatile.Register32 // 0x4C + WDTCONFIG2 volatile.Register32 // 0x50 + WDTCONFIG3 volatile.Register32 // 0x54 + WDTCONFIG4 volatile.Register32 // 0x58 + WDTCONFIG5 volatile.Register32 // 0x5C + WDTFEED volatile.Register32 // 0x60 + WDTWPROTECT volatile.Register32 // 0x64 + RTCCALICFG volatile.Register32 // 0x68 + RTCCALICFG1 volatile.Register32 // 0x6C + INT_ENA_TIMERS volatile.Register32 // 0x70 + INT_RAW_TIMERS volatile.Register32 // 0x74 + INT_ST_TIMERS volatile.Register32 // 0x78 + INT_CLR_TIMERS volatile.Register32 // 0x7C + RTCCALICFG2 volatile.Register32 // 0x80 + _ [116]byte + NTIMERS_DATE volatile.Register32 // 0xF8 + REGCLK volatile.Register32 // 0xFC +} + +// TIMG.T0CONFIG: Timer %s configuration register +func (o *TIMG_Type) SetT0CONFIG_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetT0CONFIG_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetT0CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT0CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT0CONFIG_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetT0CONFIG_DIVCNT_RST() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetT0CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT0CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT0CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT0CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT0CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT0CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT0CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0LO: Timer %s current value, low 32 bits +func (o *TIMG_Type) SetT0LO(value uint32) { + volatile.StoreUint32(&o.T0LO.Reg, value) +} +func (o *TIMG_Type) GetT0LO() uint32 { + return volatile.LoadUint32(&o.T0LO.Reg) +} + +// TIMG.T0HI: Timer %s current value, high 22 bits +func (o *TIMG_Type) SetT0HI_HI(value uint32) { + volatile.StoreUint32(&o.T0HI.Reg, volatile.LoadUint32(&o.T0HI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0HI_HI() uint32 { + return volatile.LoadUint32(&o.T0HI.Reg) & 0x3fffff +} + +// TIMG.T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG +func (o *TIMG_Type) SetT0UPDATE_UPDATE(value uint32) { + volatile.StoreUint32(&o.T0UPDATE.Reg, volatile.LoadUint32(&o.T0UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0UPDATE_UPDATE() uint32 { + return (volatile.LoadUint32(&o.T0UPDATE.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0ALARMLO: Timer %s alarm value, low 32 bits +func (o *TIMG_Type) SetT0ALARMLO(value uint32) { + volatile.StoreUint32(&o.T0ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMLO() uint32 { + return volatile.LoadUint32(&o.T0ALARMLO.Reg) +} + +// TIMG.T0ALARMHI: Timer %s alarm value, high bits +func (o *TIMG_Type) SetT0ALARMHI_ALARM_HI(value uint32) { + volatile.StoreUint32(&o.T0ALARMHI.Reg, volatile.LoadUint32(&o.T0ALARMHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0ALARMHI_ALARM_HI() uint32 { + return volatile.LoadUint32(&o.T0ALARMHI.Reg) & 0x3fffff +} + +// TIMG.T0LOADLO: Timer %s reload value, low 32 bits +func (o *TIMG_Type) SetT0LOADLO(value uint32) { + volatile.StoreUint32(&o.T0LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT0LOADLO() uint32 { + return volatile.LoadUint32(&o.T0LOADLO.Reg) +} + +// TIMG.T0LOADHI: Timer %s reload value, high 22 bits +func (o *TIMG_Type) SetT0LOADHI_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.T0LOADHI.Reg, volatile.LoadUint32(&o.T0LOADHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0LOADHI_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.T0LOADHI.Reg) & 0x3fffff +} + +// TIMG.T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG +func (o *TIMG_Type) SetT0LOAD(value uint32) { + volatile.StoreUint32(&o.T0LOAD.Reg, value) +} +func (o *TIMG_Type) GetT0LOAD() uint32 { + return volatile.LoadUint32(&o.T0LOAD.Reg) +} + +// TIMG.WDTCONFIG0: Watchdog timer configuration register +func (o *TIMG_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x2000)|value<<13) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x2000) >> 13 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x4000)|value<<14) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x4000) >> 14 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x38000)|value<<15) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x38000) >> 15 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c0000)|value<<18) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c0000) >> 18 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200000)|value<<21) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200000) >> 21 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CONF_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400000)|value<<22) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CONF_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400000) >> 22 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1800000)|value<<23) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1800000) >> 23 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x6000000)|value<<25) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x6000000) >> 25 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x18000000)|value<<27) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x18000000) >> 27 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x60000000)|value<<29) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x60000000) >> 29 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// TIMG.WDTCONFIG1: Watchdog timer prescaler register +func (o *TIMG_Type) SetWDTCONFIG1_WDT_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_DIVCNT_RST() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetWDTCONFIG1_WDT_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_CLK_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0xffff0000) >> 16 +} + +// TIMG.WDTCONFIG2: Watchdog timer stage 0 timeout value +func (o *TIMG_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// TIMG.WDTCONFIG3: Watchdog timer stage 1 timeout value +func (o *TIMG_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// TIMG.WDTCONFIG4: Watchdog timer stage 2 timeout value +func (o *TIMG_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// TIMG.WDTCONFIG5: Watchdog timer stage 3 timeout value +func (o *TIMG_Type) SetWDTCONFIG5(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG5.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG5() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG5.Reg) +} + +// TIMG.WDTFEED: Write to feed the watchdog timer +func (o *TIMG_Type) SetWDTFEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, value) +} +func (o *TIMG_Type) GetWDTFEED() uint32 { + return volatile.LoadUint32(&o.WDTFEED.Reg) +} + +// TIMG.WDTWPROTECT: Watchdog write protect register +func (o *TIMG_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *TIMG_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// TIMG.RTCCALICFG: RTC calibration configure register +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START_CYCLING(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START_CYCLING() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x6000)|value<<13) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x6000) >> 13 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_RDY(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x8000)|value<<15) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_RDY() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x8000) >> 15 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_MAX(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x7fff0000)|value<<16) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_MAX() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x7fff0000) >> 16 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x80000000) >> 31 +} + +// TIMG.RTCCALICFG1: RTC calibration configure1 register +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_VALUE(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_VALUE() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0xffffff80) >> 7 +} + +// TIMG.INT_ENA_TIMERS: Interrupt enable bits +func (o *TIMG_Type) SetINT_ENA_TIMERS_T0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_RAW_TIMERS: Raw interrupt status +func (o *TIMG_Type) SetINT_RAW_TIMERS_T0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_ST_TIMERS: Masked interrupt status +func (o *TIMG_Type) SetINT_ST_TIMERS_T0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.INT_CLR_TIMERS: Interrupt clear bits +func (o *TIMG_Type) SetINT_CLR_TIMERS_T0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x2) >> 1 +} + +// TIMG.RTCCALICFG2: Timer group calibration register +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x78)|value<<3) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x78) >> 3 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0xffffff80) >> 7 +} + +// TIMG.NTIMERS_DATE: Timer version control register +func (o *TIMG_Type) SetNTIMERS_DATE_NTIMGS_DATE(value uint32) { + volatile.StoreUint32(&o.NTIMERS_DATE.Reg, volatile.LoadUint32(&o.NTIMERS_DATE.Reg)&^(0xfffffff)|value) +} +func (o *TIMG_Type) GetNTIMERS_DATE_NTIMGS_DATE() uint32 { + return volatile.LoadUint32(&o.NTIMERS_DATE.Reg) & 0xfffffff +} + +// TIMG.REGCLK: Timer group clock gate register +func (o *TIMG_Type) SetREGCLK_ETM_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *TIMG_Type) GetREGCLK_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x10000000) >> 28 +} +func (o *TIMG_Type) SetREGCLK_WDT_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetREGCLK_WDT_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetREGCLK_TIMER_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetREGCLK_TIMER_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetREGCLK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetREGCLK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x80000000) >> 31 +} + +// RISC-V Trace Encoder +type TRACE_Type struct { + MEM_START_ADDR volatile.Register32 // 0x0 + MEM_END_ADDR volatile.Register32 // 0x4 + MEM_CURRENT_ADDR volatile.Register32 // 0x8 + MEM_ADDR_UPDATE volatile.Register32 // 0xC + FIFO_STATUS volatile.Register32 // 0x10 + INTR_ENA volatile.Register32 // 0x14 + INTR_RAW volatile.Register32 // 0x18 + INTR_CLR volatile.Register32 // 0x1C + TRIGGER volatile.Register32 // 0x20 + RESYNC_PROLONGED volatile.Register32 // 0x24 + CLOCK_GATE volatile.Register32 // 0x28 + _ [976]byte + DATE volatile.Register32 // 0x3FC +} + +// TRACE.MEM_START_ADDR: mem start addr +func (o *TRACE_Type) SetMEM_START_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_START_ADDR.Reg, value) +} +func (o *TRACE_Type) GetMEM_START_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_START_ADDR.Reg) +} + +// TRACE.MEM_END_ADDR: mem end addr +func (o *TRACE_Type) SetMEM_END_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_END_ADDR.Reg, value) +} +func (o *TRACE_Type) GetMEM_END_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_END_ADDR.Reg) +} + +// TRACE.MEM_CURRENT_ADDR: mem current addr +func (o *TRACE_Type) SetMEM_CURRENT_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_CURRENT_ADDR.Reg, value) +} +func (o *TRACE_Type) GetMEM_CURRENT_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_CURRENT_ADDR.Reg) +} + +// TRACE.MEM_ADDR_UPDATE: mem addr update +func (o *TRACE_Type) SetMEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE(value uint32) { + volatile.StoreUint32(&o.MEM_ADDR_UPDATE.Reg, volatile.LoadUint32(&o.MEM_ADDR_UPDATE.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetMEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE() uint32 { + return volatile.LoadUint32(&o.MEM_ADDR_UPDATE.Reg) & 0x1 +} + +// TRACE.FIFO_STATUS: fifo status register +func (o *TRACE_Type) SetFIFO_STATUS_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.FIFO_STATUS.Reg, volatile.LoadUint32(&o.FIFO_STATUS.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetFIFO_STATUS_FIFO_EMPTY() uint32 { + return volatile.LoadUint32(&o.FIFO_STATUS.Reg) & 0x1 +} +func (o *TRACE_Type) SetFIFO_STATUS_WORK_STATUS(value uint32) { + volatile.StoreUint32(&o.FIFO_STATUS.Reg, volatile.LoadUint32(&o.FIFO_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetFIFO_STATUS_WORK_STATUS() uint32 { + return (volatile.LoadUint32(&o.FIFO_STATUS.Reg) & 0x2) >> 1 +} + +// TRACE.INTR_ENA: interrupt enable register +func (o *TRACE_Type) SetINTR_ENA_FIFO_OVERFLOW_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_ENA.Reg, volatile.LoadUint32(&o.INTR_ENA.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetINTR_ENA_FIFO_OVERFLOW_INTR_ENA() uint32 { + return volatile.LoadUint32(&o.INTR_ENA.Reg) & 0x1 +} +func (o *TRACE_Type) SetINTR_ENA_MEM_FULL_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_ENA.Reg, volatile.LoadUint32(&o.INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetINTR_ENA_MEM_FULL_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_ENA.Reg) & 0x2) >> 1 +} + +// TRACE.INTR_RAW: interrupt status register +func (o *TRACE_Type) SetINTR_RAW_FIFO_OVERFLOW_INTR_RAW(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetINTR_RAW_FIFO_OVERFLOW_INTR_RAW() uint32 { + return volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x1 +} +func (o *TRACE_Type) SetINTR_RAW_MEM_FULL_INTR_RAW(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetINTR_RAW_MEM_FULL_INTR_RAW() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x2) >> 1 +} + +// TRACE.INTR_CLR: interrupt clear register +func (o *TRACE_Type) SetINTR_CLR_FIFO_OVERFLOW_INTR_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetINTR_CLR_FIFO_OVERFLOW_INTR_CLR() uint32 { + return volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x1 +} +func (o *TRACE_Type) SetINTR_CLR_MEM_FULL_INTR_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetINTR_CLR_MEM_FULL_INTR_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x2) >> 1 +} + +// TRACE.TRIGGER: trigger register +func (o *TRACE_Type) SetTRIGGER_ON(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetTRIGGER_ON() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} +func (o *TRACE_Type) SetTRIGGER_OFF(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetTRIGGER_OFF() uint32 { + return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x2) >> 1 +} +func (o *TRACE_Type) SetTRIGGER_MEM_LOOP(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x4)|value<<2) +} +func (o *TRACE_Type) GetTRIGGER_MEM_LOOP() uint32 { + return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x4) >> 2 +} +func (o *TRACE_Type) SetTRIGGER_RESTART_ENA(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x8)|value<<3) +} +func (o *TRACE_Type) GetTRIGGER_RESTART_ENA() uint32 { + return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x8) >> 3 +} + +// TRACE.RESYNC_PROLONGED: resync configuration register +func (o *TRACE_Type) SetRESYNC_PROLONGED(value uint32) { + volatile.StoreUint32(&o.RESYNC_PROLONGED.Reg, volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg)&^(0xffffff)|value) +} +func (o *TRACE_Type) GetRESYNC_PROLONGED() uint32 { + return volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg) & 0xffffff +} +func (o *TRACE_Type) SetRESYNC_PROLONGED_RESYNC_MODE(value uint32) { + volatile.StoreUint32(&o.RESYNC_PROLONGED.Reg, volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg)&^(0x1000000)|value<<24) +} +func (o *TRACE_Type) GetRESYNC_PROLONGED_RESYNC_MODE() uint32 { + return (volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg) & 0x1000000) >> 24 +} + +// TRACE.CLOCK_GATE: Clock gate control register +func (o *TRACE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// TRACE.DATE: Version control register +func (o *TRACE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *TRACE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Two-Wire Automotive Interface +type TWAI_Type struct { + MODE volatile.Register32 // 0x0 + CMD volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + INTERRUPT volatile.Register32 // 0xC + INTERRUPT_ENABLE volatile.Register32 // 0x10 + _ [4]byte + BUS_TIMING_0 volatile.Register32 // 0x18 + BUS_TIMING_1 volatile.Register32 // 0x1C + _ [12]byte + ARB_LOST_CAP volatile.Register32 // 0x2C + ERR_CODE_CAP volatile.Register32 // 0x30 + ERR_WARNING_LIMIT volatile.Register32 // 0x34 + RX_ERR_CNT volatile.Register32 // 0x38 + TX_ERR_CNT volatile.Register32 // 0x3C + DATA_0 volatile.Register32 // 0x40 + DATA_1 volatile.Register32 // 0x44 + DATA_2 volatile.Register32 // 0x48 + DATA_3 volatile.Register32 // 0x4C + DATA_4 volatile.Register32 // 0x50 + DATA_5 volatile.Register32 // 0x54 + DATA_6 volatile.Register32 // 0x58 + DATA_7 volatile.Register32 // 0x5C + DATA_8 volatile.Register32 // 0x60 + DATA_9 volatile.Register32 // 0x64 + DATA_10 volatile.Register32 // 0x68 + DATA_11 volatile.Register32 // 0x6C + DATA_12 volatile.Register32 // 0x70 + RX_MESSAGE_COUNTER volatile.Register32 // 0x74 + _ [4]byte + CLOCK_DIVIDER volatile.Register32 // 0x7C + SW_STANDBY_CFG volatile.Register32 // 0x80 + HW_CFG volatile.Register32 // 0x84 + HW_STANDBY_CNT volatile.Register32 // 0x88 + IDLE_INTR_CNT volatile.Register32 // 0x8C + ECO_CFG volatile.Register32 // 0x90 +} + +// TWAI.MODE: TWAI mode register. +func (o *TWAI_Type) SetMODE_RESET_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetMODE_RESET_MODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x1 +} +func (o *TWAI_Type) SetMODE_LISTEN_ONLY_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetMODE_LISTEN_ONLY_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetMODE_SELF_TEST_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetMODE_SELF_TEST_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetMODE_ACCEPTANCE_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetMODE_ACCEPTANCE_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x8) >> 3 +} + +// TWAI.CMD: TWAI command register. +func (o *TWAI_Type) SetCMD_TX_REQUEST(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetCMD_TX_REQUEST() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *TWAI_Type) SetCMD_ABORT_TX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetCMD_ABORT_TX() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetCMD_RELEASE_BUFFER(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetCMD_RELEASE_BUFFER() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetCMD_CLEAR_DATA_OVERRUN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetCMD_CLEAR_DATA_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetCMD_SELF_RX_REQUEST(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetCMD_SELF_RX_REQUEST() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10) >> 4 +} + +// TWAI.STATUS: TWAI status register. +func (o *TWAI_Type) SetSTATUS_RECEIVE_BUFFER(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSTATUS_RECEIVE_BUFFER() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *TWAI_Type) SetSTATUS_OVERRUN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSTATUS_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetSTATUS_TRANSMIT_BUFFER(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetSTATUS_TRANSMIT_BUFFER() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetSTATUS_TRANSMISSION_COMPLETE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetSTATUS_TRANSMISSION_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetSTATUS_RECEIVE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetSTATUS_RECEIVE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *TWAI_Type) SetSTATUS_TRANSMIT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetSTATUS_TRANSMIT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetSTATUS_ERR(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetSTATUS_ERR() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetSTATUS_NODE_BUS_OFF(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetSTATUS_NODE_BUS_OFF() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetSTATUS_MISS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetSTATUS_MISS() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} + +// TWAI.INTERRUPT: Interrupt signals' register. +func (o *TWAI_Type) SetINTERRUPT_RECEIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINTERRUPT_RECEIVE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x1 +} +func (o *TWAI_Type) SetINTERRUPT_TRANSMIT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINTERRUPT_TRANSMIT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINTERRUPT_ERR_WARNING_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINTERRUPT_ERR_WARNING_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINTERRUPT_DATA_OVERRUN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINTERRUPT_DATA_OVERRUN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINTERRUPT_ERR_PASSIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINTERRUPT_ERR_PASSIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINTERRUPT_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINTERRUPT_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINTERRUPT_BUS_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINTERRUPT_BUS_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetINTERRUPT_IDLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetINTERRUPT_IDLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x100) >> 8 +} + +// TWAI.INTERRUPT_ENABLE: Interrupt enable register. +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x1 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_BUS_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_BUS_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_IDLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_IDLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x100) >> 8 +} + +// TWAI.BUS_TIMING_0: Bit timing configuration register 0. +func (o *TWAI_Type) SetBUS_TIMING_0_BAUD_PRESC(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0x3fff)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_0_BAUD_PRESC() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0x3fff +} +func (o *TWAI_Type) SetBUS_TIMING_0_SYNC_JUMP_WIDTH(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0xc000)|value<<14) +} +func (o *TWAI_Type) GetBUS_TIMING_0_SYNC_JUMP_WIDTH() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0xc000) >> 14 +} + +// TWAI.BUS_TIMING_1: Bit timing configuration register 1. +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEGMENT1(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0xf)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEGMENT1() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0xf +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEGMENT2(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x70)|value<<4) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEGMENT2() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x70) >> 4 +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SAMPLING(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SAMPLING() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x80) >> 7 +} + +// TWAI.ARB_LOST_CAP: TWAI arbiter lost capture register. +func (o *TWAI_Type) SetARB_LOST_CAP_ARBITRATION_LOST_CAPTURE(value uint32) { + volatile.StoreUint32(&o.ARB_LOST_CAP.Reg, volatile.LoadUint32(&o.ARB_LOST_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetARB_LOST_CAP_ARBITRATION_LOST_CAPTURE() uint32 { + return volatile.LoadUint32(&o.ARB_LOST_CAP.Reg) & 0x1f +} + +// TWAI.ERR_CODE_CAP: TWAI error info capture register. +func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT() uint32 { + return volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x1f +} +func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0xc0)|value<<6) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0xc0) >> 6 +} + +// TWAI.ERR_WARNING_LIMIT: TWAI error threshold configuration register. +func (o *TWAI_Type) SetERR_WARNING_LIMIT(value uint32) { + volatile.StoreUint32(&o.ERR_WARNING_LIMIT.Reg, volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetERR_WARNING_LIMIT() uint32 { + return volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg) & 0xff +} + +// TWAI.RX_ERR_CNT: Rx error counter register. +func (o *TWAI_Type) SetRX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ERR_CNT.Reg, volatile.LoadUint32(&o.RX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetRX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.RX_ERR_CNT.Reg) & 0xff +} + +// TWAI.TX_ERR_CNT: Tx error counter register. +func (o *TWAI_Type) SetTX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ERR_CNT.Reg, volatile.LoadUint32(&o.TX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetTX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.TX_ERR_CNT.Reg) & 0xff +} + +// TWAI.DATA_0: Data register 0. +func (o *TWAI_Type) SetDATA_0(value uint32) { + volatile.StoreUint32(&o.DATA_0.Reg, volatile.LoadUint32(&o.DATA_0.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_0() uint32 { + return volatile.LoadUint32(&o.DATA_0.Reg) & 0xff +} + +// TWAI.DATA_1: Data register 1. +func (o *TWAI_Type) SetDATA_1(value uint32) { + volatile.StoreUint32(&o.DATA_1.Reg, volatile.LoadUint32(&o.DATA_1.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_1() uint32 { + return volatile.LoadUint32(&o.DATA_1.Reg) & 0xff +} + +// TWAI.DATA_2: Data register 2. +func (o *TWAI_Type) SetDATA_2(value uint32) { + volatile.StoreUint32(&o.DATA_2.Reg, volatile.LoadUint32(&o.DATA_2.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_2() uint32 { + return volatile.LoadUint32(&o.DATA_2.Reg) & 0xff +} + +// TWAI.DATA_3: Data register 3. +func (o *TWAI_Type) SetDATA_3(value uint32) { + volatile.StoreUint32(&o.DATA_3.Reg, volatile.LoadUint32(&o.DATA_3.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_3() uint32 { + return volatile.LoadUint32(&o.DATA_3.Reg) & 0xff +} + +// TWAI.DATA_4: Data register 4. +func (o *TWAI_Type) SetDATA_4(value uint32) { + volatile.StoreUint32(&o.DATA_4.Reg, volatile.LoadUint32(&o.DATA_4.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_4() uint32 { + return volatile.LoadUint32(&o.DATA_4.Reg) & 0xff +} + +// TWAI.DATA_5: Data register 5. +func (o *TWAI_Type) SetDATA_5(value uint32) { + volatile.StoreUint32(&o.DATA_5.Reg, volatile.LoadUint32(&o.DATA_5.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_5() uint32 { + return volatile.LoadUint32(&o.DATA_5.Reg) & 0xff +} + +// TWAI.DATA_6: Data register 6. +func (o *TWAI_Type) SetDATA_6(value uint32) { + volatile.StoreUint32(&o.DATA_6.Reg, volatile.LoadUint32(&o.DATA_6.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_6() uint32 { + return volatile.LoadUint32(&o.DATA_6.Reg) & 0xff +} + +// TWAI.DATA_7: Data register 7. +func (o *TWAI_Type) SetDATA_7(value uint32) { + volatile.StoreUint32(&o.DATA_7.Reg, volatile.LoadUint32(&o.DATA_7.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_7() uint32 { + return volatile.LoadUint32(&o.DATA_7.Reg) & 0xff +} + +// TWAI.DATA_8: Data register 8. +func (o *TWAI_Type) SetDATA_8(value uint32) { + volatile.StoreUint32(&o.DATA_8.Reg, volatile.LoadUint32(&o.DATA_8.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_8() uint32 { + return volatile.LoadUint32(&o.DATA_8.Reg) & 0xff +} + +// TWAI.DATA_9: Data register 9. +func (o *TWAI_Type) SetDATA_9(value uint32) { + volatile.StoreUint32(&o.DATA_9.Reg, volatile.LoadUint32(&o.DATA_9.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_9() uint32 { + return volatile.LoadUint32(&o.DATA_9.Reg) & 0xff +} + +// TWAI.DATA_10: Data register 10. +func (o *TWAI_Type) SetDATA_10(value uint32) { + volatile.StoreUint32(&o.DATA_10.Reg, volatile.LoadUint32(&o.DATA_10.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_10() uint32 { + return volatile.LoadUint32(&o.DATA_10.Reg) & 0xff +} + +// TWAI.DATA_11: Data register 11. +func (o *TWAI_Type) SetDATA_11(value uint32) { + volatile.StoreUint32(&o.DATA_11.Reg, volatile.LoadUint32(&o.DATA_11.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_11() uint32 { + return volatile.LoadUint32(&o.DATA_11.Reg) & 0xff +} + +// TWAI.DATA_12: Data register 12. +func (o *TWAI_Type) SetDATA_12(value uint32) { + volatile.StoreUint32(&o.DATA_12.Reg, volatile.LoadUint32(&o.DATA_12.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_12() uint32 { + return volatile.LoadUint32(&o.DATA_12.Reg) & 0xff +} + +// TWAI.RX_MESSAGE_COUNTER: Received message counter register. +func (o *TWAI_Type) SetRX_MESSAGE_COUNTER(value uint32) { + volatile.StoreUint32(&o.RX_MESSAGE_COUNTER.Reg, volatile.LoadUint32(&o.RX_MESSAGE_COUNTER.Reg)&^(0x7f)|value) +} +func (o *TWAI_Type) GetRX_MESSAGE_COUNTER() uint32 { + return volatile.LoadUint32(&o.RX_MESSAGE_COUNTER.Reg) & 0x7f +} + +// TWAI.CLOCK_DIVIDER: Clock divider register. +func (o *TWAI_Type) SetCLOCK_DIVIDER_CD(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CD() uint32 { + return volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0xff +} +func (o *TWAI_Type) SetCLOCK_DIVIDER_CLOCK_OFF(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CLOCK_OFF() uint32 { + return (volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0x100) >> 8 +} + +// TWAI.SW_STANDBY_CFG: Software configure standby pin directly. +func (o *TWAI_Type) SetSW_STANDBY_CFG_SW_STANDBY_EN(value uint32) { + volatile.StoreUint32(&o.SW_STANDBY_CFG.Reg, volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSW_STANDBY_CFG_SW_STANDBY_EN() uint32 { + return volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg) & 0x1 +} +func (o *TWAI_Type) SetSW_STANDBY_CFG_SW_STANDBY_CLR(value uint32) { + volatile.StoreUint32(&o.SW_STANDBY_CFG.Reg, volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSW_STANDBY_CFG_SW_STANDBY_CLR() uint32 { + return (volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg) & 0x2) >> 1 +} + +// TWAI.HW_CFG: Hardware configure standby pin. +func (o *TWAI_Type) SetHW_CFG_HW_STANDBY_EN(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetHW_CFG_HW_STANDBY_EN() uint32 { + return volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1 +} + +// TWAI.HW_STANDBY_CNT: Configure standby counter. +func (o *TWAI_Type) SetHW_STANDBY_CNT(value uint32) { + volatile.StoreUint32(&o.HW_STANDBY_CNT.Reg, value) +} +func (o *TWAI_Type) GetHW_STANDBY_CNT() uint32 { + return volatile.LoadUint32(&o.HW_STANDBY_CNT.Reg) +} + +// TWAI.IDLE_INTR_CNT: Configure idle interrupt counter. +func (o *TWAI_Type) SetIDLE_INTR_CNT(value uint32) { + volatile.StoreUint32(&o.IDLE_INTR_CNT.Reg, value) +} +func (o *TWAI_Type) GetIDLE_INTR_CNT() uint32 { + return volatile.LoadUint32(&o.IDLE_INTR_CNT.Reg) +} + +// TWAI.ECO_CFG: ECO configuration register. +func (o *TWAI_Type) SetECO_CFG_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.ECO_CFG.Reg, volatile.LoadUint32(&o.ECO_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetECO_CFG_RDN_ENA() uint32 { + return volatile.LoadUint32(&o.ECO_CFG.Reg) & 0x1 +} +func (o *TWAI_Type) SetECO_CFG_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.ECO_CFG.Reg, volatile.LoadUint32(&o.ECO_CFG.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetECO_CFG_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.ECO_CFG.Reg) & 0x2) >> 1 +} + +// UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +type UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV volatile.Register32 // 0x14 + RX_FILT volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0 volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + _ [4]byte + HWFC_CONF volatile.Register32 // 0x2C + SLEEP_CONF0 volatile.Register32 // 0x30 + SLEEP_CONF1 volatile.Register32 // 0x34 + SLEEP_CONF2 volatile.Register32 // 0x38 + SWFC_CONF0 volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + TXBRK_CONF volatile.Register32 // 0x44 + IDLE_CONF volatile.Register32 // 0x48 + RS485_CONF volatile.Register32 // 0x4C + AT_CMD_PRECNT volatile.Register32 // 0x50 + AT_CMD_POSTCNT volatile.Register32 // 0x54 + AT_CMD_GAPTOUT volatile.Register32 // 0x58 + AT_CMD_CHAR volatile.Register32 // 0x5C + MEM_CONF volatile.Register32 // 0x60 + TOUT_CONF volatile.Register32 // 0x64 + MEM_TX_STATUS volatile.Register32 // 0x68 + MEM_RX_STATUS volatile.Register32 // 0x6C + FSM_STATUS volatile.Register32 // 0x70 + POSPULSE volatile.Register32 // 0x74 + NEGPULSE volatile.Register32 // 0x78 + LOWPULSE volatile.Register32 // 0x7C + HIGHPULSE volatile.Register32 // 0x80 + RXD_CNT volatile.Register32 // 0x84 + CLK_CONF volatile.Register32 // 0x88 + DATE volatile.Register32 // 0x8C + AFIFO_STATUS volatile.Register32 // 0x90 + _ [4]byte + REG_UPDATE volatile.Register32 // 0x98 + ID volatile.Register32 // 0x9C +} + +// UART.FIFO: FIFO data register +func (o *UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// UART.INT_RAW: Raw interrupt status +func (o *UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_RAW_RS485_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_RAW_RS485_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_RAW_RS485_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_RAW_RS485_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_RAW_RS485_CLASH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_RAW_RS485_CLASH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// UART.INT_ST: Masked interrupt status +func (o *UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ST_RS485_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ST_RS485_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ST_RS485_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ST_RS485_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ST_RS485_CLASH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ST_RS485_CLASH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// UART.INT_ENA: Interrupt enable bits +func (o *UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ENA_RS485_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ENA_RS485_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ENA_RS485_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ENA_RS485_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ENA_RS485_CLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ENA_RS485_CLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// UART.INT_CLR: Interrupt clear bits +func (o *UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_CLR_RS485_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_CLR_RS485_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_CLR_RS485_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_CLR_RS485_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_CLR_RS485_CLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_CLR_RS485_CLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// UART.CLKDIV: Clock divider configuration +func (o *UART_Type) SetCLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetCLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xfff +} +func (o *UART_Type) SetCLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xf00000)|value<<20) +} +func (o *UART_Type) GetCLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xf00000) >> 20 +} + +// UART.RX_FILT: Rx Filter configuration +func (o *UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT() uint32 { + return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff +} +func (o *UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8 +} + +// UART.STATUS: UART status register +func (o *UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xff +} +func (o *UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xff0000) >> 16 +} +func (o *UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// UART.CONF0: a +func (o *UART_Type) SetCONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetCONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UART_Type) SetCONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetCONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetCONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0xc)|value<<2) +} +func (o *UART_Type) GetCONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0xc) >> 2 +} +func (o *UART_Type) SetCONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x30)|value<<4) +} +func (o *UART_Type) GetCONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x30) >> 4 +} +func (o *UART_Type) SetCONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetCONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetCONF0_IRDA_DPLX(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetCONF0_IRDA_DPLX() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetCONF0_IRDA_TX_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetCONF0_IRDA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetCONF0_IRDA_WCTL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetCONF0_IRDA_WCTL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetCONF0_IRDA_TX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetCONF0_IRDA_TX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetCONF0_IRDA_RX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetCONF0_IRDA_RX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetCONF0_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetCONF0_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetCONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetCONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetCONF0_IRDA_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetCONF0_IRDA_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetCONF0_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetCONF0_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetCONF0_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF0_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF0_DIS_RX_DAT_OVF(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF0_DIS_RX_DAT_OVF() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF0_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF0_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF0_AUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF0_AUTOBAUD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF0_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF0_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetCONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} + +// UART.CONF1: Configuration register 1 +func (o *UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0xff +} +func (o *UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetCONF1_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF1_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF1_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF1_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF1_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF1_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF1_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF1_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF1_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF1_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} + +// UART.HWFC_CONF: Hardware flow-control configuration +func (o *UART_Type) SetHWFC_CONF_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF.Reg, volatile.LoadUint32(&o.HWFC_CONF.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetHWFC_CONF_RX_FLOW_THRHD() uint32 { + return volatile.LoadUint32(&o.HWFC_CONF.Reg) & 0xff +} +func (o *UART_Type) SetHWFC_CONF_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF.Reg, volatile.LoadUint32(&o.HWFC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetHWFC_CONF_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.HWFC_CONF.Reg) & 0x100) >> 8 +} + +// UART.SLEEP_CONF0: UART sleep configure register 0 +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR1(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR1() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff +} +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR2(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR2() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR3(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR3() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff0000) >> 16 +} +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR4(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff000000)|value<<24) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR4() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff000000) >> 24 +} + +// UART.SLEEP_CONF1: UART sleep configure register 1 +func (o *UART_Type) SetSLEEP_CONF1_WK_CHAR0(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF1.Reg, volatile.LoadUint32(&o.SLEEP_CONF1.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSLEEP_CONF1_WK_CHAR0() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF1.Reg) & 0xff +} + +// UART.SLEEP_CONF2: UART sleep configure register 2 +func (o *UART_Type) SetSLEEP_CONF2_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSLEEP_CONF2_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3ff +} +func (o *UART_Type) SetSLEEP_CONF2_RX_WAKE_UP_THRHD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3fc00)|value<<10) +} +func (o *UART_Type) GetSLEEP_CONF2_RX_WAKE_UP_THRHD() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3fc00) >> 10 +} +func (o *UART_Type) SetSLEEP_CONF2_WK_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x1c0000)|value<<18) +} +func (o *UART_Type) GetSLEEP_CONF2_WK_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x1c0000) >> 18 +} +func (o *UART_Type) SetSLEEP_CONF2_WK_CHAR_MASK(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e00000)|value<<21) +} +func (o *UART_Type) GetSLEEP_CONF2_WK_CHAR_MASK() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e00000) >> 21 +} +func (o *UART_Type) SetSLEEP_CONF2_WK_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0xc000000)|value<<26) +} +func (o *UART_Type) GetSLEEP_CONF2_WK_MODE_SEL() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0xc000000) >> 26 +} + +// UART.SWFC_CONF0: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF0_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSWFC_CONF0_XON_CHAR() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0xff +} +func (o *UART_Type) SetSWFC_CONF0_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetSWFC_CONF0_XON_XOFF_STILL_SEND(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetSWFC_CONF0_XON_XOFF_STILL_SEND() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetSWFC_CONF0_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetSWFC_CONF0_SW_FLOW_CON_EN() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetSWFC_CONF0_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetSWFC_CONF0_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetSWFC_CONF0_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetSWFC_CONF0_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetSWFC_CONF0_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetSWFC_CONF0_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetSWFC_CONF0_SEND_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetSWFC_CONF0_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetSWFC_CONF0_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetSWFC_CONF0_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x400000) >> 22 +} + +// UART.SWFC_CONF1: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xff +} +func (o *UART_Type) SetSWFC_CONF1_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSWFC_CONF1_XOFF_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xff00) >> 8 +} + +// UART.TXBRK_CONF: Tx Break character configuration +func (o *UART_Type) SetTXBRK_CONF_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.TXBRK_CONF.Reg, volatile.LoadUint32(&o.TXBRK_CONF.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetTXBRK_CONF_TX_BRK_NUM() uint32 { + return volatile.LoadUint32(&o.TXBRK_CONF.Reg) & 0xff +} + +// UART.IDLE_CONF: Frame-end idle configuration +func (o *UART_Type) SetIDLE_CONF_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetIDLE_CONF_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0x3ff +} +func (o *UART_Type) SetIDLE_CONF_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *UART_Type) GetIDLE_CONF_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xffc00) >> 10 +} + +// UART.RS485_CONF: RS485 mode configuration +func (o *UART_Type) SetRS485_CONF_RS485_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetRS485_CONF_RS485_EN() uint32 { + return volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetRS485_CONF_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetRS485_CONF_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetRS485_CONF_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetRS485_CONF_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetRS485_CONF_RS485TX_RX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetRS485_CONF_RS485TX_RX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetRS485_CONF_RS485RXBY_TX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetRS485_CONF_RS485RXBY_TX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetRS485_CONF_RS485_RX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetRS485_CONF_RS485_RX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetRS485_CONF_RS485_TX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x3c0)|value<<6) +} +func (o *UART_Type) GetRS485_CONF_RS485_TX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x3c0) >> 6 +} + +// UART.AT_CMD_PRECNT: Pre-sequence timing configuration +func (o *UART_Type) SetAT_CMD_PRECNT_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_PRECNT_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg) & 0xffff +} + +// UART.AT_CMD_POSTCNT: Post-sequence timing configuration +func (o *UART_Type) SetAT_CMD_POSTCNT_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_POSTCNT_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg) & 0xffff +} + +// UART.AT_CMD_GAPTOUT: Timeout configuration +func (o *UART_Type) SetAT_CMD_GAPTOUT_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_GAPTOUT_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg) & 0xffff +} + +// UART.AT_CMD_CHAR: AT escape sequence detection configuration +func (o *UART_Type) SetAT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetAT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff +} +func (o *UART_Type) SetAT_CMD_CHAR_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAT_CMD_CHAR_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff00) >> 8 +} + +// UART.MEM_CONF: UART memory power configuration +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26 +} + +// UART.TOUT_CONF: UART threshold and allocation configuration +func (o *UART_Type) SetTOUT_CONF_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF.Reg, volatile.LoadUint32(&o.TOUT_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetTOUT_CONF_RX_TOUT_EN() uint32 { + return volatile.LoadUint32(&o.TOUT_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetTOUT_CONF_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF.Reg, volatile.LoadUint32(&o.TOUT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetTOUT_CONF_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetTOUT_CONF_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF.Reg, volatile.LoadUint32(&o.TOUT_CONF.Reg)&^(0xffc)|value<<2) +} +func (o *UART_Type) GetTOUT_CONF_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF.Reg) & 0xffc) >> 2 +} + +// UART.MEM_TX_STATUS: Tx-SRAM write and read offset address. +func (o *UART_Type) SetMEM_TX_STATUS_TX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_SRAM_WADDR() uint32 { + return volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0xff +} +func (o *UART_Type) SetMEM_TX_STATUS_TX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_SRAM_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1fe00) >> 9 +} + +// UART.MEM_RX_STATUS: Rx-SRAM write and read offset address. +func (o *UART_Type) SetMEM_RX_STATUS_RX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_SRAM_RADDR() uint32 { + return volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xff +} +func (o *UART_Type) SetMEM_RX_STATUS_RX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_SRAM_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1fe00) >> 9 +} + +// UART.FSM_STATUS: UART transmit and receive status. +func (o *UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// UART.POSPULSE: Autobaud high pulse register +func (o *UART_Type) SetPOSPULSE_POSEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.POSPULSE.Reg, volatile.LoadUint32(&o.POSPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetPOSPULSE_POSEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.POSPULSE.Reg) & 0xfff +} + +// UART.NEGPULSE: Autobaud low pulse register +func (o *UART_Type) SetNEGPULSE_NEGEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.NEGPULSE.Reg, volatile.LoadUint32(&o.NEGPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetNEGPULSE_NEGEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.NEGPULSE.Reg) & 0xfff +} + +// UART.LOWPULSE: Autobaud minimum low pulse duration register +func (o *UART_Type) SetLOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.LOWPULSE.Reg, volatile.LoadUint32(&o.LOWPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetLOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.LOWPULSE.Reg) & 0xfff +} + +// UART.HIGHPULSE: Autobaud minimum high pulse duration register +func (o *UART_Type) SetHIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.HIGHPULSE.Reg, volatile.LoadUint32(&o.HIGHPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetHIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.HIGHPULSE.Reg) & 0xfff +} + +// UART.RXD_CNT: Autobaud edge change count register +func (o *UART_Type) SetRXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.RXD_CNT.Reg, volatile.LoadUint32(&o.RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetRXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.RXD_CNT.Reg) & 0x3ff +} + +// UART.CLK_CONF: UART core clock configuration +func (o *UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCLK_CONF_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCLK_CONF_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCLK_CONF_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCLK_CONF_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} + +// UART.DATE: UART Version register +func (o *UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// UART.AFIFO_STATUS: UART AFIFO Status +func (o *UART_Type) SetAFIFO_STATUS_TX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetAFIFO_STATUS_TX_AFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x1 +} +func (o *UART_Type) SetAFIFO_STATUS_TX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetAFIFO_STATUS_TX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetAFIFO_STATUS_RX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetAFIFO_STATUS_RX_AFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetAFIFO_STATUS_RX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetAFIFO_STATUS_RX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x8) >> 3 +} + +// UART.REG_UPDATE: UART Registers Configuration Update register +func (o *UART_Type) SetREG_UPDATE(value uint32) { + volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetREG_UPDATE() uint32 { + return volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x1 +} + +// UART.ID: UART ID register +func (o *UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, value) +} +func (o *UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) +} + +// Universal Host Controller Interface 0 +type UHCI_Type struct { + CONF0 volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CONF1 volatile.Register32 // 0x14 + STATE0 volatile.Register32 // 0x18 + STATE1 volatile.Register32 // 0x1C + ESCAPE_CONF volatile.Register32 // 0x20 + HUNG_CONF volatile.Register32 // 0x24 + ACK_NUM volatile.Register32 // 0x28 + RX_HEAD volatile.Register32 // 0x2C + QUICK_SENT volatile.Register32 // 0x30 + REG_Q0_WORD0 volatile.Register32 // 0x34 + REG_Q0_WORD1 volatile.Register32 // 0x38 + REG_Q1_WORD0 volatile.Register32 // 0x3C + REG_Q1_WORD1 volatile.Register32 // 0x40 + REG_Q2_WORD0 volatile.Register32 // 0x44 + REG_Q2_WORD1 volatile.Register32 // 0x48 + REG_Q3_WORD0 volatile.Register32 // 0x4C + REG_Q3_WORD1 volatile.Register32 // 0x50 + REG_Q4_WORD0 volatile.Register32 // 0x54 + REG_Q4_WORD1 volatile.Register32 // 0x58 + REG_Q5_WORD0 volatile.Register32 // 0x5C + REG_Q5_WORD1 volatile.Register32 // 0x60 + REG_Q6_WORD0 volatile.Register32 // 0x64 + REG_Q6_WORD1 volatile.Register32 // 0x68 + ESC_CONF0 volatile.Register32 // 0x6C + ESC_CONF1 volatile.Register32 // 0x70 + ESC_CONF2 volatile.Register32 // 0x74 + ESC_CONF3 volatile.Register32 // 0x78 + PKT_THRES volatile.Register32 // 0x7C + DATE volatile.Register32 // 0x80 +} + +// UHCI.CONF0: a +func (o *UHCI_Type) SetCONF0_TX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF0_TX_RST() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF0_RX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF0_RX_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF0_UART0_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF0_UART0_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF0_UART1_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF0_UART1_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF0_SEPER_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF0_SEPER_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF0_HEAD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetCONF0_HEAD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetCONF0_CRC_REC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF0_CRC_REC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF0_UART_IDLE_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF0_UART_IDLE_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetCONF0_LEN_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetCONF0_LEN_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetCONF0_ENCODE_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetCONF0_ENCODE_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetCONF0_UART_RX_BRK_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetCONF0_UART_RX_BRK_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} + +// UHCI.INT_RAW: a +func (o *UHCI_Type) SetINT_RAW_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_RAW_RX_START_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_RAW_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_RAW_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_RAW_SEND_S_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_RAW_SEND_S_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_RAW_SEND_A_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_RAW_SEND_A_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ST: a +func (o *UHCI_Type) SetINT_ST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ST_RX_START_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ST_SEND_S_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ST_SEND_S_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ST_SEND_A_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ST_SEND_A_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ST_OUTLINK_EOF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ST_OUTLINK_EOF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ENA: a +func (o *UHCI_Type) SetINT_ENA_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ENA_RX_START_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ENA_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ENA_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ENA_SEND_S_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ENA_SEND_S_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ENA_SEND_A_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ENA_SEND_A_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ENA_OUTLINK_EOF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ENA_OUTLINK_EOF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// UHCI.INT_CLR: a +func (o *UHCI_Type) SetINT_CLR_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_CLR_RX_START_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_CLR_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_CLR_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_CLR_SEND_S_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_CLR_SEND_S_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_CLR_SEND_A_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_CLR_SEND_A_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_CLR_OUTLINK_EOF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_CLR_OUTLINK_EOF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// UHCI.CONF1: a +func (o *UHCI_Type) SetCONF1_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF1_CHECK_SUM_EN() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF1_CHECK_SEQ_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF1_CHECK_SEQ_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF1_CRC_DISABLE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF1_CRC_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF1_SAVE_HEAD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF1_SAVE_HEAD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF1_TX_CHECK_SUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF1_TX_CHECK_SUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF1_TX_ACK_NUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF1_TX_ACK_NUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF1_WAIT_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF1_WAIT_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF1_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF1_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8 +} + +// UHCI.STATE0: a +func (o *UHCI_Type) SetSTATE0_RX_ERR_CAUSE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE0_RX_ERR_CAUSE() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x7 +} +func (o *UHCI_Type) SetSTATE0_DECODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x38)|value<<3) +} +func (o *UHCI_Type) GetSTATE0_DECODE_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x38) >> 3 +} + +// UHCI.STATE1: a +func (o *UHCI_Type) SetSTATE1_ENCODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE1_ENCODE_STATE() uint32 { + return volatile.LoadUint32(&o.STATE1.Reg) & 0x7 +} + +// UHCI.ESCAPE_CONF: a +func (o *UHCI_Type) SetESCAPE_CONF_TX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_C0_ESC_EN() uint32 { + return volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_C0_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x80) >> 7 +} + +// UHCI.HUNG_CONF: a +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff000) >> 12 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700000) >> 20 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800000) >> 23 +} + +// UHCI.ACK_NUM: a +func (o *UHCI_Type) SetACK_NUM(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetACK_NUM() uint32 { + return volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x7 +} +func (o *UHCI_Type) SetACK_NUM_LOAD(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetACK_NUM_LOAD() uint32 { + return (volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x8) >> 3 +} + +// UHCI.RX_HEAD: a +func (o *UHCI_Type) SetRX_HEAD(value uint32) { + volatile.StoreUint32(&o.RX_HEAD.Reg, value) +} +func (o *UHCI_Type) GetRX_HEAD() uint32 { + return volatile.LoadUint32(&o.RX_HEAD.Reg) +} + +// UHCI.QUICK_SENT: a +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_NUM() uint32 { + return volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x7 +} +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x70)|value<<4) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_NUM() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x70) >> 4 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x80) >> 7 +} + +// UHCI.REG_Q0_WORD0: a +func (o *UHCI_Type) SetREG_Q0_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD0.Reg) +} + +// UHCI.REG_Q0_WORD1: a +func (o *UHCI_Type) SetREG_Q0_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD1.Reg) +} + +// UHCI.REG_Q1_WORD0: a +func (o *UHCI_Type) SetREG_Q1_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD0.Reg) +} + +// UHCI.REG_Q1_WORD1: a +func (o *UHCI_Type) SetREG_Q1_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD1.Reg) +} + +// UHCI.REG_Q2_WORD0: a +func (o *UHCI_Type) SetREG_Q2_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD0.Reg) +} + +// UHCI.REG_Q2_WORD1: a +func (o *UHCI_Type) SetREG_Q2_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD1.Reg) +} + +// UHCI.REG_Q3_WORD0: a +func (o *UHCI_Type) SetREG_Q3_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD0.Reg) +} + +// UHCI.REG_Q3_WORD1: a +func (o *UHCI_Type) SetREG_Q3_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD1.Reg) +} + +// UHCI.REG_Q4_WORD0: a +func (o *UHCI_Type) SetREG_Q4_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD0.Reg) +} + +// UHCI.REG_Q4_WORD1: a +func (o *UHCI_Type) SetREG_Q4_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD1.Reg) +} + +// UHCI.REG_Q5_WORD0: a +func (o *UHCI_Type) SetREG_Q5_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD0.Reg) +} + +// UHCI.REG_Q5_WORD1: a +func (o *UHCI_Type) SetREG_Q5_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD1.Reg) +} + +// UHCI.REG_Q6_WORD0: a +func (o *UHCI_Type) SetREG_Q6_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD0.Reg) +} + +// UHCI.REG_Q6_WORD1: a +func (o *UHCI_Type) SetREG_Q6_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD1.Reg) +} + +// UHCI.ESC_CONF0: a +func (o *UHCI_Type) SetESC_CONF0_SEPER_CHAR(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_CHAR() uint32 { + return volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF1: a +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0() uint32 { + return volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF2: a +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1() uint32 { + return volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF3: a +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2() uint32 { + return volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff0000) >> 16 +} + +// UHCI.PKT_THRES: a +func (o *UHCI_Type) SetPKT_THRES_PKT_THRS(value uint32) { + volatile.StoreUint32(&o.PKT_THRES.Reg, volatile.LoadUint32(&o.PKT_THRES.Reg)&^(0x1fff)|value) +} +func (o *UHCI_Type) GetPKT_THRES_PKT_THRS() uint32 { + return volatile.LoadUint32(&o.PKT_THRES.Reg) & 0x1fff +} + +// UHCI.DATE: a +func (o *UHCI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UHCI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Full-speed USB Serial/JTAG Controller +type USB_DEVICE_Type struct { + EP1 volatile.Register32 // 0x0 + EP1_CONF volatile.Register32 // 0x4 + INT_RAW volatile.Register32 // 0x8 + INT_ST volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + INT_CLR volatile.Register32 // 0x14 + CONF0 volatile.Register32 // 0x18 + TEST volatile.Register32 // 0x1C + JFIFO_ST volatile.Register32 // 0x20 + FRAM_NUM volatile.Register32 // 0x24 + IN_EP0_ST volatile.Register32 // 0x28 + IN_EP1_ST volatile.Register32 // 0x2C + IN_EP2_ST volatile.Register32 // 0x30 + IN_EP3_ST volatile.Register32 // 0x34 + OUT_EP0_ST volatile.Register32 // 0x38 + OUT_EP1_ST volatile.Register32 // 0x3C + OUT_EP2_ST volatile.Register32 // 0x40 + MISC_CONF volatile.Register32 // 0x44 + MEM_CONF volatile.Register32 // 0x48 + CHIP_RST volatile.Register32 // 0x4C + SET_LINE_CODE_W0 volatile.Register32 // 0x50 + SET_LINE_CODE_W1 volatile.Register32 // 0x54 + GET_LINE_CODE_W0 volatile.Register32 // 0x58 + GET_LINE_CODE_W1 volatile.Register32 // 0x5C + CONFIG_UPDATE volatile.Register32 // 0x60 + SER_AFIFO_CONFIG volatile.Register32 // 0x64 + BUS_RESET_ST volatile.Register32 // 0x68 + _ [20]byte + DATE volatile.Register32 // 0x80 +} + +// USB_DEVICE.EP1: FIFO access for the CDC-ACM data IN and OUT endpoints. +func (o *USB_DEVICE_Type) SetEP1_RDWR_BYTE(value uint32) { + volatile.StoreUint32(&o.EP1.Reg, volatile.LoadUint32(&o.EP1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetEP1_RDWR_BYTE() uint32 { + return volatile.LoadUint32(&o.EP1.Reg) & 0xff +} + +// USB_DEVICE.EP1_CONF: Configuration and control registers for the CDC-ACM FIFOs. +func (o *USB_DEVICE_Type) SetEP1_CONF_WR_DONE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_WR_DONE() uint32 { + return volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_SERIAL_IN_EP_DATA_FREE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_SERIAL_IN_EP_DATA_FREE() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_SERIAL_OUT_EP_DATA_AVAIL(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_SERIAL_OUT_EP_DATA_AVAIL() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x4) >> 2 +} + +// USB_DEVICE.INT_RAW: Interrupt raw status register. +func (o *USB_DEVICE_Type) SetINT_RAW_JTAG_IN_FLUSH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_RAW_JTAG_IN_FLUSH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SERIAL_IN_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SERIAL_IN_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_RAW_PID_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_RAW_PID_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_RAW_CRC5_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_RAW_CRC5_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_RAW_CRC16_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_RAW_CRC16_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_RAW_STUFF_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_RAW_STUFF_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_BUS_RESET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_BUS_RESET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_RAW_RTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_RAW_RTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_RAW_DTR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_RAW_DTR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_RAW_GET_LINE_CODE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_RAW_GET_LINE_CODE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SET_LINE_CODE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SET_LINE_CODE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.INT_ST: Interrupt status register. +func (o *USB_DEVICE_Type) SetINT_ST_JTAG_IN_FLUSH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ST_JTAG_IN_FLUSH_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ST_SOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ST_SOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ST_SERIAL_OUT_RECV_PKT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ST_SERIAL_OUT_RECV_PKT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ST_SERIAL_IN_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ST_SERIAL_IN_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ST_PID_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ST_PID_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ST_CRC5_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ST_CRC5_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ST_CRC16_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ST_CRC16_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ST_STUFF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ST_STUFF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ST_IN_TOKEN_REC_IN_EP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ST_IN_TOKEN_REC_IN_EP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_BUS_RESET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_BUS_RESET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_ST_RTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_ST_RTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_ST_DTR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_ST_DTR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_ST_GET_LINE_CODE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_ST_GET_LINE_CODE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_ST_SET_LINE_CODE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_ST_SET_LINE_CODE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.INT_ENA: Interrupt enable status register. +func (o *USB_DEVICE_Type) SetINT_ENA_JTAG_IN_FLUSH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ENA_JTAG_IN_FLUSH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SERIAL_IN_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SERIAL_IN_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ENA_PID_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ENA_PID_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ENA_CRC5_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ENA_CRC5_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ENA_CRC16_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ENA_CRC16_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ENA_STUFF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ENA_STUFF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_BUS_RESET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_BUS_RESET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_ENA_RTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_ENA_RTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_ENA_DTR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_ENA_DTR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_ENA_GET_LINE_CODE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_ENA_GET_LINE_CODE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SET_LINE_CODE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SET_LINE_CODE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.INT_CLR: Interrupt clear status register. +func (o *USB_DEVICE_Type) SetINT_CLR_JTAG_IN_FLUSH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_CLR_JTAG_IN_FLUSH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SERIAL_IN_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SERIAL_IN_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_CLR_PID_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_CLR_PID_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_CLR_CRC5_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_CLR_CRC5_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_CLR_CRC16_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_CLR_CRC16_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_CLR_STUFF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_CLR_STUFF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_BUS_RESET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_BUS_RESET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_CLR_RTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_CLR_RTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_CLR_DTR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_CLR_DTR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_CLR_GET_LINE_CODE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_CLR_GET_LINE_CODE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SET_LINE_CODE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SET_LINE_CODE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.CONF0: PHY hardware configuration. +func (o *USB_DEVICE_Type) SetCONF0_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCONF0_PHY_SEL() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetCONF0_EXCHG_PINS_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetCONF0_EXCHG_PINS_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetCONF0_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetCONF0_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetCONF0_VREFH(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x18)|value<<3) +} +func (o *USB_DEVICE_Type) GetCONF0_VREFH() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x18) >> 3 +} +func (o *USB_DEVICE_Type) SetCONF0_VREFL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x60)|value<<5) +} +func (o *USB_DEVICE_Type) GetCONF0_VREFL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x60) >> 5 +} +func (o *USB_DEVICE_Type) SetCONF0_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetCONF0_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetCONF0_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetCONF0_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetCONF0_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetCONF0_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetCONF0_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetCONF0_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetCONF0_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetCONF0_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetCONF0_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetCONF0_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetCONF0_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetCONF0_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_JTAG_BRIDGE_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_JTAG_BRIDGE_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.TEST: Registers used for debugging the PHY. +func (o *USB_DEVICE_Type) SetTEST_TEST_ENABLE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_ENABLE() uint32 { + return volatile.LoadUint32(&o.TEST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_USB_OE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_USB_OE() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_TX_DP(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_TX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_TX_DM(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_TX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_RX_RCV(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_RX_RCV() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_RX_DP(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_RX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetTEST_TEST_RX_DM(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetTEST_TEST_RX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x40) >> 6 +} + +// USB_DEVICE.JFIFO_ST: JTAG FIFO status and control registers. +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_CNT() uint32 { + return volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x30)|value<<4) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x30) >> 4 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x200) >> 9 +} + +// USB_DEVICE.FRAM_NUM: Last received SOF frame index register. +func (o *USB_DEVICE_Type) SetFRAM_NUM_SOF_FRAME_INDEX(value uint32) { + volatile.StoreUint32(&o.FRAM_NUM.Reg, volatile.LoadUint32(&o.FRAM_NUM.Reg)&^(0x7ff)|value) +} +func (o *USB_DEVICE_Type) GetFRAM_NUM_SOF_FRAME_INDEX() uint32 { + return volatile.LoadUint32(&o.FRAM_NUM.Reg) & 0x7ff +} + +// USB_DEVICE.IN_EP0_ST: Control IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP1_ST: CDC-ACM IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP2_ST: CDC-ACM interrupt IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP3_ST: JTAG IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP0_ST: Control OUT endpoint status information. +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP1_ST: CDC-ACM OUT endpoint status information. +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0xfe00) >> 9 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_REC_DATA_CNT(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x7f0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_REC_DATA_CNT() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x7f0000) >> 16 +} + +// USB_DEVICE.OUT_EP2_ST: JTAG OUT endpoint status information. +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.MISC_CONF: Clock enable control +func (o *USB_DEVICE_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMISC_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} + +// USB_DEVICE.MEM_CONF: Memory power control +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_MEM_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_MEM_PD() uint32 { + return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2) >> 1 +} + +// USB_DEVICE.CHIP_RST: CDC-ACM chip reset control. +func (o *USB_DEVICE_Type) SetCHIP_RST_RTS(value uint32) { + volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCHIP_RST_RTS() uint32 { + return volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetCHIP_RST_DTR(value uint32) { + volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetCHIP_RST_DTR() uint32 { + return (volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetCHIP_RST_USB_UART_CHIP_RST_DIS(value uint32) { + volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetCHIP_RST_USB_UART_CHIP_RST_DIS() uint32 { + return (volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x4) >> 2 +} + +// USB_DEVICE.SET_LINE_CODE_W0: W0 of SET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W0(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W0.Reg, value) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W0() uint32 { + return volatile.LoadUint32(&o.SET_LINE_CODE_W0.Reg) +} + +// USB_DEVICE.SET_LINE_CODE_W1: W1 of SET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_BCHAR_FORMAT(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_BCHAR_FORMAT() uint32 { + return volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff +} +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_BPARITY_TYPE(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff00)|value<<8) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_BPARITY_TYPE() uint32 { + return (volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff00) >> 8 +} +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_BDATA_BITS(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_BDATA_BITS() uint32 { + return (volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff0000) >> 16 +} + +// USB_DEVICE.GET_LINE_CODE_W0: W0 of GET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W0(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W0.Reg, value) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W0() uint32 { + return volatile.LoadUint32(&o.GET_LINE_CODE_W0.Reg) +} + +// USB_DEVICE.GET_LINE_CODE_W1: W1 of GET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_GET_BDATA_BITS(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_GET_BDATA_BITS() uint32 { + return volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff +} +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_GET_BPARITY_TYPE(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff00)|value<<8) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_GET_BPARITY_TYPE() uint32 { + return (volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff00) >> 8 +} +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_GET_BCHAR_FORMAT(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_GET_BCHAR_FORMAT() uint32 { + return (volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff0000) >> 16 +} + +// USB_DEVICE.CONFIG_UPDATE: Configuration registers' value update +func (o *USB_DEVICE_Type) SetCONFIG_UPDATE(value uint32) { + volatile.StoreUint32(&o.CONFIG_UPDATE.Reg, volatile.LoadUint32(&o.CONFIG_UPDATE.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCONFIG_UPDATE() uint32 { + return volatile.LoadUint32(&o.CONFIG_UPDATE.Reg) & 0x1 +} + +// USB_DEVICE.SER_AFIFO_CONFIG: Serial AFIFO configure register +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR() uint32 { + return volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x20) >> 5 +} + +// USB_DEVICE.BUS_RESET_ST: USB Bus reset status register +func (o *USB_DEVICE_Type) SetBUS_RESET_ST_USB_BUS_RESET_ST(value uint32) { + volatile.StoreUint32(&o.BUS_RESET_ST.Reg, volatile.LoadUint32(&o.BUS_RESET_ST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetBUS_RESET_ST_USB_BUS_RESET_ST() uint32 { + return volatile.LoadUint32(&o.BUS_RESET_ST.Reg) & 0x1 +} + +// USB_DEVICE.DATE: Date register +func (o *USB_DEVICE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *USB_DEVICE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Constants for AES: AES (Advanced Encryption Standard) Accelerator +const ( + // KEY_0: Key material key_0 configure register + // Position of KEY_0 field. + AES_KEY_0_KEY_0_Pos = 0x0 + // Bit mask of KEY_0 field. + AES_KEY_0_KEY_0_Msk = 0xffffffff + + // KEY_1: Key material key_1 configure register + // Position of KEY_1 field. + AES_KEY_1_KEY_1_Pos = 0x0 + // Bit mask of KEY_1 field. + AES_KEY_1_KEY_1_Msk = 0xffffffff + + // KEY_2: Key material key_2 configure register + // Position of KEY_2 field. + AES_KEY_2_KEY_2_Pos = 0x0 + // Bit mask of KEY_2 field. + AES_KEY_2_KEY_2_Msk = 0xffffffff + + // KEY_3: Key material key_3 configure register + // Position of KEY_3 field. + AES_KEY_3_KEY_3_Pos = 0x0 + // Bit mask of KEY_3 field. + AES_KEY_3_KEY_3_Msk = 0xffffffff + + // KEY_4: Key material key_4 configure register + // Position of KEY_4 field. + AES_KEY_4_KEY_4_Pos = 0x0 + // Bit mask of KEY_4 field. + AES_KEY_4_KEY_4_Msk = 0xffffffff + + // KEY_5: Key material key_5 configure register + // Position of KEY_5 field. + AES_KEY_5_KEY_5_Pos = 0x0 + // Bit mask of KEY_5 field. + AES_KEY_5_KEY_5_Msk = 0xffffffff + + // KEY_6: Key material key_6 configure register + // Position of KEY_6 field. + AES_KEY_6_KEY_6_Pos = 0x0 + // Bit mask of KEY_6 field. + AES_KEY_6_KEY_6_Msk = 0xffffffff + + // KEY_7: Key material key_7 configure register + // Position of KEY_7 field. + AES_KEY_7_KEY_7_Pos = 0x0 + // Bit mask of KEY_7 field. + AES_KEY_7_KEY_7_Msk = 0xffffffff + + // TEXT_IN_0: source text material text_in_0 configure register + // Position of TEXT_IN_0 field. + AES_TEXT_IN_0_TEXT_IN_0_Pos = 0x0 + // Bit mask of TEXT_IN_0 field. + AES_TEXT_IN_0_TEXT_IN_0_Msk = 0xffffffff + + // TEXT_IN_1: source text material text_in_1 configure register + // Position of TEXT_IN_1 field. + AES_TEXT_IN_1_TEXT_IN_1_Pos = 0x0 + // Bit mask of TEXT_IN_1 field. + AES_TEXT_IN_1_TEXT_IN_1_Msk = 0xffffffff + + // TEXT_IN_2: source text material text_in_2 configure register + // Position of TEXT_IN_2 field. + AES_TEXT_IN_2_TEXT_IN_2_Pos = 0x0 + // Bit mask of TEXT_IN_2 field. + AES_TEXT_IN_2_TEXT_IN_2_Msk = 0xffffffff + + // TEXT_IN_3: source text material text_in_3 configure register + // Position of TEXT_IN_3 field. + AES_TEXT_IN_3_TEXT_IN_3_Pos = 0x0 + // Bit mask of TEXT_IN_3 field. + AES_TEXT_IN_3_TEXT_IN_3_Msk = 0xffffffff + + // TEXT_OUT_0: result text material text_out_0 configure register + // Position of TEXT_OUT_0 field. + AES_TEXT_OUT_0_TEXT_OUT_0_Pos = 0x0 + // Bit mask of TEXT_OUT_0 field. + AES_TEXT_OUT_0_TEXT_OUT_0_Msk = 0xffffffff + + // TEXT_OUT_1: result text material text_out_1 configure register + // Position of TEXT_OUT_1 field. + AES_TEXT_OUT_1_TEXT_OUT_1_Pos = 0x0 + // Bit mask of TEXT_OUT_1 field. + AES_TEXT_OUT_1_TEXT_OUT_1_Msk = 0xffffffff + + // TEXT_OUT_2: result text material text_out_2 configure register + // Position of TEXT_OUT_2 field. + AES_TEXT_OUT_2_TEXT_OUT_2_Pos = 0x0 + // Bit mask of TEXT_OUT_2 field. + AES_TEXT_OUT_2_TEXT_OUT_2_Msk = 0xffffffff + + // TEXT_OUT_3: result text material text_out_3 configure register + // Position of TEXT_OUT_3 field. + AES_TEXT_OUT_3_TEXT_OUT_3_Pos = 0x0 + // Bit mask of TEXT_OUT_3 field. + AES_TEXT_OUT_3_TEXT_OUT_3_Msk = 0xffffffff + + // MODE: AES Mode register + // Position of MODE field. + AES_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + AES_MODE_MODE_Msk = 0x7 + + // ENDIAN: AES Endian configure register + // Position of ENDIAN field. + AES_ENDIAN_ENDIAN_Pos = 0x0 + // Bit mask of ENDIAN field. + AES_ENDIAN_ENDIAN_Msk = 0x3f + + // TRIGGER: AES trigger register + // Position of TRIGGER field. + AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + AES_TRIGGER_TRIGGER = 0x1 + + // STATE: AES state register + // Position of STATE field. + AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + AES_STATE_STATE_Msk = 0x3 + + // DMA_ENABLE: DMA-AES working mode register + // Position of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Pos = 0x0 + // Bit mask of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Msk = 0x1 + // Bit DMA_ENABLE. + AES_DMA_ENABLE_DMA_ENABLE = 0x1 + + // BLOCK_MODE: AES cipher block mode register + // Position of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Pos = 0x0 + // Bit mask of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Msk = 0x7 + + // BLOCK_NUM: AES block number register + // Position of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Pos = 0x0 + // Bit mask of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Msk = 0xffffffff + + // INC_SEL: Standard incrementing function configure register + // Position of INC_SEL field. + AES_INC_SEL_INC_SEL_Pos = 0x0 + // Bit mask of INC_SEL field. + AES_INC_SEL_INC_SEL_Msk = 0x1 + // Bit INC_SEL. + AES_INC_SEL_INC_SEL = 0x1 + + // AAD_BLOCK_NUM: Additional Authential Data block number register + // Position of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Pos = 0x0 + // Bit mask of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Msk = 0xffffffff + + // REMAINDER_BIT_NUM: AES remainder bit number register + // Position of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Pos = 0x0 + // Bit mask of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Msk = 0x7f + + // CONTINUE: AES continue register + // Position of CONTINUE field. + AES_CONTINUE_CONTINUE_Pos = 0x0 + // Bit mask of CONTINUE field. + AES_CONTINUE_CONTINUE_Msk = 0x1 + // Bit CONTINUE. + AES_CONTINUE_CONTINUE = 0x1 + + // INT_CLEAR: AES Interrupt clear register + // Position of INT_CLEAR field. + AES_INT_CLEAR_INT_CLEAR_Pos = 0x0 + // Bit mask of INT_CLEAR field. + AES_INT_CLEAR_INT_CLEAR_Msk = 0x1 + // Bit INT_CLEAR. + AES_INT_CLEAR_INT_CLEAR = 0x1 + + // INT_ENA: AES Interrupt enable register + // Position of INT_ENA field. + AES_INT_ENA_INT_ENA_Pos = 0x0 + // Bit mask of INT_ENA field. + AES_INT_ENA_INT_ENA_Msk = 0x1 + // Bit INT_ENA. + AES_INT_ENA_INT_ENA = 0x1 + + // DATE: AES version control register + // Position of DATE field. + AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + AES_DATE_DATE_Msk = 0x3fffffff + + // DMA_EXIT: AES-DMA exit config + // Position of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Pos = 0x0 + // Bit mask of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Msk = 0x1 + // Bit DMA_EXIT. + AES_DMA_EXIT_DMA_EXIT = 0x1 +) + +// Constants for APB_SARADC: SAR (Successive Approximation Register) Analog-to-Digital Converter +const ( + // CTRL: digital saradc configure register + // Position of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Pos = 0x0 + // Bit mask of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Msk = 0x1 + // Bit SARADC_START_FORCE. + APB_SARADC_CTRL_SARADC_START_FORCE = 0x1 + // Position of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Pos = 0x1 + // Bit mask of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Msk = 0x2 + // Bit SARADC_START. + APB_SARADC_CTRL_SARADC_START = 0x2 + // Position of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Pos = 0x6 + // Bit mask of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Msk = 0x40 + // Bit SARADC_SAR_CLK_GATED. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED = 0x40 + // Position of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Pos = 0x7 + // Bit mask of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Msk = 0x7f80 + // Position of SARADC_SAR_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR_PATT_LEN_Pos = 0xf + // Bit mask of SARADC_SAR_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR_PATT_LEN_Msk = 0x38000 + // Position of SARADC_SAR_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR_Pos = 0x17 + // Bit mask of SARADC_SAR_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR_Msk = 0x800000 + // Bit SARADC_SAR_PATT_P_CLEAR. + APB_SARADC_CTRL_SARADC_SAR_PATT_P_CLEAR = 0x800000 + // Position of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Pos = 0x1b + // Bit mask of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Msk = 0x18000000 + // Position of SARADC2_PWDET_DRV field. + APB_SARADC_CTRL_SARADC2_PWDET_DRV_Pos = 0x1d + // Bit mask of SARADC2_PWDET_DRV field. + APB_SARADC_CTRL_SARADC2_PWDET_DRV_Msk = 0x20000000 + // Bit SARADC2_PWDET_DRV. + APB_SARADC_CTRL_SARADC2_PWDET_DRV = 0x20000000 + // Position of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Pos = 0x1e + // Bit mask of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Msk = 0xc0000000 + + // CTRL2: digital saradc configure register + // Position of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Pos = 0x0 + // Bit mask of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Msk = 0x1 + // Bit SARADC_MEAS_NUM_LIMIT. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT = 0x1 + // Position of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Pos = 0x1 + // Bit mask of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Msk = 0x1fe + // Position of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Pos = 0x9 + // Bit mask of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Msk = 0x200 + // Bit SARADC_SAR1_INV. + APB_SARADC_CTRL2_SARADC_SAR1_INV = 0x200 + // Position of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Pos = 0xa + // Bit mask of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Msk = 0x400 + // Bit SARADC_SAR2_INV. + APB_SARADC_CTRL2_SARADC_SAR2_INV = 0x400 + // Position of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Pos = 0xc + // Bit mask of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Msk = 0xfff000 + // Position of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Pos = 0x18 + // Bit mask of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Msk = 0x1000000 + // Bit SARADC_TIMER_EN. + APB_SARADC_CTRL2_SARADC_TIMER_EN = 0x1000000 + + // FILTER_CTRL1: digital saradc configure register + // Position of APB_SARADC_FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR1_Pos = 0x1a + // Bit mask of APB_SARADC_FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR1_Msk = 0x1c000000 + // Position of APB_SARADC_FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR0_Pos = 0x1d + // Bit mask of APB_SARADC_FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_APB_SARADC_FILTER_FACTOR0_Msk = 0xe0000000 + + // FSM_WAIT: digital saradc configure register + // Position of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Pos = 0x0 + // Bit mask of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Msk = 0xff + // Position of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Pos = 0x8 + // Bit mask of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Msk = 0xff00 + // Position of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Pos = 0x10 + // Bit mask of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Msk = 0xff0000 + + // SAR1_STATUS: digital saradc configure register + // Position of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Msk = 0xffffffff + + // SAR2_STATUS: digital saradc configure register + // Position of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Msk = 0xffffffff + + // SAR_PATT_TAB1: digital saradc configure register + // Position of SARADC_SAR_PATT_TAB1 field. + APB_SARADC_SAR_PATT_TAB1_SARADC_SAR_PATT_TAB1_Pos = 0x0 + // Bit mask of SARADC_SAR_PATT_TAB1 field. + APB_SARADC_SAR_PATT_TAB1_SARADC_SAR_PATT_TAB1_Msk = 0xffffff + + // SAR_PATT_TAB2: digital saradc configure register + // Position of SARADC_SAR_PATT_TAB2 field. + APB_SARADC_SAR_PATT_TAB2_SARADC_SAR_PATT_TAB2_Pos = 0x0 + // Bit mask of SARADC_SAR_PATT_TAB2 field. + APB_SARADC_SAR_PATT_TAB2_SARADC_SAR_PATT_TAB2_Msk = 0xffffff + + // ONETIME_SAMPLE: digital saradc configure register + // Position of SARADC_ONETIME_ATTEN field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_ATTEN_Pos = 0x17 + // Bit mask of SARADC_ONETIME_ATTEN field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_ATTEN_Msk = 0x1800000 + // Position of SARADC_ONETIME_CHANNEL field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_CHANNEL_Pos = 0x19 + // Bit mask of SARADC_ONETIME_CHANNEL field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_CHANNEL_Msk = 0x1e000000 + // Position of SARADC_ONETIME_START field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START_Pos = 0x1d + // Bit mask of SARADC_ONETIME_START field. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START_Msk = 0x20000000 + // Bit SARADC_ONETIME_START. + APB_SARADC_ONETIME_SAMPLE_SARADC_ONETIME_START = 0x20000000 + // Position of SARADC2_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE_Pos = 0x1e + // Bit mask of SARADC2_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE_Msk = 0x40000000 + // Bit SARADC2_ONETIME_SAMPLE. + APB_SARADC_ONETIME_SAMPLE_SARADC2_ONETIME_SAMPLE = 0x40000000 + // Position of SARADC1_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE_Pos = 0x1f + // Bit mask of SARADC1_ONETIME_SAMPLE field. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE_Msk = 0x80000000 + // Bit SARADC1_ONETIME_SAMPLE. + APB_SARADC_ONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE = 0x80000000 + + // ARB_CTRL: digital saradc configure register + // Position of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Pos = 0x2 + // Bit mask of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Msk = 0x4 + // Bit ADC_ARB_APB_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE = 0x4 + // Position of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Pos = 0x3 + // Bit mask of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Msk = 0x8 + // Bit ADC_ARB_RTC_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE = 0x8 + // Position of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Pos = 0x4 + // Bit mask of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Msk = 0x10 + // Bit ADC_ARB_WIFI_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE = 0x10 + // Position of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Pos = 0x5 + // Bit mask of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Msk = 0x20 + // Bit ADC_ARB_GRANT_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE = 0x20 + // Position of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Pos = 0x6 + // Bit mask of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Msk = 0xc0 + // Position of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Pos = 0x8 + // Bit mask of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Msk = 0x300 + // Position of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Pos = 0xa + // Bit mask of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Msk = 0xc00 + // Position of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Pos = 0xc + // Bit mask of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Msk = 0x1000 + // Bit ADC_ARB_FIX_PRIORITY. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY = 0x1000 + + // FILTER_CTRL0: digital saradc configure register + // Position of APB_SARADC_FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1_Pos = 0x12 + // Bit mask of APB_SARADC_FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL1_Msk = 0x3c0000 + // Position of APB_SARADC_FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0_Pos = 0x16 + // Bit mask of APB_SARADC_FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_CHANNEL0_Msk = 0x3c00000 + // Position of APB_SARADC_FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_RESET_Pos = 0x1f + // Bit mask of APB_SARADC_FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_RESET_Msk = 0x80000000 + // Bit APB_SARADC_FILTER_RESET. + APB_SARADC_FILTER_CTRL0_APB_SARADC_FILTER_RESET = 0x80000000 + + // SAR1DATA_STATUS: digital saradc configure register + // Position of APB_SARADC1_DATA field. + APB_SARADC_SAR1DATA_STATUS_APB_SARADC1_DATA_Pos = 0x0 + // Bit mask of APB_SARADC1_DATA field. + APB_SARADC_SAR1DATA_STATUS_APB_SARADC1_DATA_Msk = 0x1ffff + + // SAR2DATA_STATUS: digital saradc configure register + // Position of APB_SARADC2_DATA field. + APB_SARADC_SAR2DATA_STATUS_APB_SARADC2_DATA_Pos = 0x0 + // Bit mask of APB_SARADC2_DATA field. + APB_SARADC_SAR2DATA_STATUS_APB_SARADC2_DATA_Msk = 0x1ffff + + // THRES0_CTRL: digital saradc configure register + // Position of APB_SARADC_THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_CHANNEL_Pos = 0x0 + // Bit mask of APB_SARADC_THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_CHANNEL_Msk = 0xf + // Position of APB_SARADC_THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_HIGH_Pos = 0x5 + // Bit mask of APB_SARADC_THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_HIGH_Msk = 0x3ffe0 + // Position of APB_SARADC_THRES0_LOW field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_LOW_Pos = 0x12 + // Bit mask of APB_SARADC_THRES0_LOW field. + APB_SARADC_THRES0_CTRL_APB_SARADC_THRES0_LOW_Msk = 0x7ffc0000 + + // THRES1_CTRL: digital saradc configure register + // Position of APB_SARADC_THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_CHANNEL_Pos = 0x0 + // Bit mask of APB_SARADC_THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_CHANNEL_Msk = 0xf + // Position of APB_SARADC_THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_HIGH_Pos = 0x5 + // Bit mask of APB_SARADC_THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_HIGH_Msk = 0x3ffe0 + // Position of APB_SARADC_THRES1_LOW field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_LOW_Pos = 0x12 + // Bit mask of APB_SARADC_THRES1_LOW field. + APB_SARADC_THRES1_CTRL_APB_SARADC_THRES1_LOW_Msk = 0x7ffc0000 + + // THRES_CTRL: digital saradc configure register + // Position of APB_SARADC_THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES_ALL_EN_Pos = 0x1b + // Bit mask of APB_SARADC_THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES_ALL_EN_Msk = 0x8000000 + // Bit APB_SARADC_THRES_ALL_EN. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES_ALL_EN = 0x8000000 + // Position of APB_SARADC_THRES1_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES1_EN_Pos = 0x1e + // Bit mask of APB_SARADC_THRES1_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES1_EN_Msk = 0x40000000 + // Bit APB_SARADC_THRES1_EN. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES1_EN = 0x40000000 + // Position of APB_SARADC_THRES0_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES0_EN_Pos = 0x1f + // Bit mask of APB_SARADC_THRES0_EN field. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES0_EN_Msk = 0x80000000 + // Bit APB_SARADC_THRES0_EN. + APB_SARADC_THRES_CTRL_APB_SARADC_THRES0_EN = 0x80000000 + + // INT_ENA: digital saradc int register + // Position of APB_SARADC_TSENS_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_TSENS_INT_ENA_Pos = 0x19 + // Bit mask of APB_SARADC_TSENS_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_TSENS_INT_ENA_Msk = 0x2000000 + // Bit APB_SARADC_TSENS_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_TSENS_INT_ENA = 0x2000000 + // Position of APB_SARADC_THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_LOW_INT_ENA_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_LOW_INT_ENA_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_LOW_INT_ENA = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_LOW_INT_ENA_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_LOW_INT_ENA_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_LOW_INT_ENA = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES1_HIGH_INT_ENA = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC_THRES0_HIGH_INT_ENA = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA = 0x80000000 + + // INT_RAW: digital saradc int register + // Position of APB_SARADC_TSENS_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_TSENS_INT_RAW_Pos = 0x19 + // Bit mask of APB_SARADC_TSENS_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_TSENS_INT_RAW_Msk = 0x2000000 + // Bit APB_SARADC_TSENS_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_TSENS_INT_RAW = 0x2000000 + // Position of APB_SARADC_THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_LOW_INT_RAW_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_LOW_INT_RAW_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_LOW_INT_RAW = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_LOW_INT_RAW_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_LOW_INT_RAW_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_LOW_INT_RAW = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES1_HIGH_INT_RAW = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC_THRES0_HIGH_INT_RAW = 0x20000000 + // Position of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW = 0x40000000 + // Position of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW = 0x80000000 + + // INT_ST: digital saradc int register + // Position of APB_SARADC_TSENS_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_TSENS_INT_ST_Pos = 0x19 + // Bit mask of APB_SARADC_TSENS_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_TSENS_INT_ST_Msk = 0x2000000 + // Bit APB_SARADC_TSENS_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_TSENS_INT_ST = 0x2000000 + // Position of APB_SARADC_THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_LOW_INT_ST_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_LOW_INT_ST_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES1_LOW_INT_ST = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_LOW_INT_ST_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_LOW_INT_ST_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES0_LOW_INT_ST = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_HIGH_INT_ST_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES1_HIGH_INT_ST_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES1_HIGH_INT_ST = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_HIGH_INT_ST_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC_THRES0_HIGH_INT_ST_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_ST. + APB_SARADC_INT_ST_APB_SARADC_THRES0_HIGH_INT_ST = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST = 0x80000000 + + // INT_CLR: digital saradc int register + // Position of APB_SARADC_TSENS_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_TSENS_INT_CLR_Pos = 0x19 + // Bit mask of APB_SARADC_TSENS_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_TSENS_INT_CLR_Msk = 0x2000000 + // Bit APB_SARADC_TSENS_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_TSENS_INT_CLR = 0x2000000 + // Position of APB_SARADC_THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_LOW_INT_CLR_Pos = 0x1a + // Bit mask of APB_SARADC_THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_LOW_INT_CLR_Msk = 0x4000000 + // Bit APB_SARADC_THRES1_LOW_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_LOW_INT_CLR = 0x4000000 + // Position of APB_SARADC_THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_LOW_INT_CLR_Pos = 0x1b + // Bit mask of APB_SARADC_THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_LOW_INT_CLR_Msk = 0x8000000 + // Bit APB_SARADC_THRES0_LOW_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_LOW_INT_CLR = 0x8000000 + // Position of APB_SARADC_THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR_Pos = 0x1c + // Bit mask of APB_SARADC_THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR_Msk = 0x10000000 + // Bit APB_SARADC_THRES1_HIGH_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES1_HIGH_INT_CLR = 0x10000000 + // Position of APB_SARADC_THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR_Pos = 0x1d + // Bit mask of APB_SARADC_THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR_Msk = 0x20000000 + // Bit APB_SARADC_THRES0_HIGH_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC_THRES0_HIGH_INT_CLR = 0x20000000 + // Position of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR = 0x40000000 + // Position of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR = 0x80000000 + + // DMA_CONF: digital saradc configure register + // Position of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Pos = 0x0 + // Bit mask of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Msk = 0xffff + // Position of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Pos = 0x1e + // Bit mask of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Msk = 0x40000000 + // Bit APB_ADC_RESET_FSM. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM = 0x40000000 + // Position of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Pos = 0x1f + // Bit mask of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Msk = 0x80000000 + // Bit APB_ADC_TRANS. + APB_SARADC_DMA_CONF_APB_ADC_TRANS = 0x80000000 + + // CLKM_CONF: digital saradc configure register + // Position of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Msk = 0xff + // Position of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Pos = 0x8 + // Bit mask of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Msk = 0x3f00 + // Position of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Pos = 0xe + // Bit mask of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Msk = 0xfc000 + // Position of CLK_EN field. + APB_SARADC_CLKM_CONF_CLK_EN_Pos = 0x14 + // Bit mask of CLK_EN field. + APB_SARADC_CLKM_CONF_CLK_EN_Msk = 0x100000 + // Bit CLK_EN. + APB_SARADC_CLKM_CONF_CLK_EN = 0x100000 + // Position of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Pos = 0x15 + // Bit mask of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Msk = 0x600000 + + // APB_TSENS_CTRL: digital tsens configure register + // Position of TSENS_OUT field. + APB_SARADC_APB_TSENS_CTRL_TSENS_OUT_Pos = 0x0 + // Bit mask of TSENS_OUT field. + APB_SARADC_APB_TSENS_CTRL_TSENS_OUT_Msk = 0xff + // Position of TSENS_IN_INV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_IN_INV_Pos = 0xd + // Bit mask of TSENS_IN_INV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_IN_INV_Msk = 0x2000 + // Bit TSENS_IN_INV. + APB_SARADC_APB_TSENS_CTRL_TSENS_IN_INV = 0x2000 + // Position of TSENS_CLK_DIV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_CLK_DIV_Pos = 0xe + // Bit mask of TSENS_CLK_DIV field. + APB_SARADC_APB_TSENS_CTRL_TSENS_CLK_DIV_Msk = 0x3fc000 + // Position of TSENS_PU field. + APB_SARADC_APB_TSENS_CTRL_TSENS_PU_Pos = 0x16 + // Bit mask of TSENS_PU field. + APB_SARADC_APB_TSENS_CTRL_TSENS_PU_Msk = 0x400000 + // Bit TSENS_PU. + APB_SARADC_APB_TSENS_CTRL_TSENS_PU = 0x400000 + + // TSENS_CTRL2: digital tsens configure register + // Position of TSENS_XPD_WAIT field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_WAIT_Pos = 0x0 + // Bit mask of TSENS_XPD_WAIT field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_WAIT_Msk = 0xfff + // Position of TSENS_XPD_FORCE field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_FORCE_Pos = 0xc + // Bit mask of TSENS_XPD_FORCE field. + APB_SARADC_TSENS_CTRL2_TSENS_XPD_FORCE_Msk = 0x3000 + // Position of TSENS_CLK_INV field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_INV_Pos = 0xe + // Bit mask of TSENS_CLK_INV field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_INV_Msk = 0x4000 + // Bit TSENS_CLK_INV. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_INV = 0x4000 + // Position of TSENS_CLK_SEL field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_SEL_Pos = 0xf + // Bit mask of TSENS_CLK_SEL field. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_SEL_Msk = 0x8000 + // Bit TSENS_CLK_SEL. + APB_SARADC_TSENS_CTRL2_TSENS_CLK_SEL = 0x8000 + + // CALI: digital saradc configure register + // Position of APB_SARADC_CALI_CFG field. + APB_SARADC_CALI_APB_SARADC_CALI_CFG_Pos = 0x0 + // Bit mask of APB_SARADC_CALI_CFG field. + APB_SARADC_CALI_APB_SARADC_CALI_CFG_Msk = 0x1ffff + + // APB_TSENS_WAKE: digital tsens configure register + // Position of WAKEUP_TH_LOW field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_TH_LOW_Pos = 0x0 + // Bit mask of WAKEUP_TH_LOW field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_TH_LOW_Msk = 0xff + // Position of WAKEUP_TH_HIGH field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_TH_HIGH_Pos = 0x8 + // Bit mask of WAKEUP_TH_HIGH field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_TH_HIGH_Msk = 0xff00 + // Position of WAKEUP_OVER_UPPER_TH field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH_Pos = 0x10 + // Bit mask of WAKEUP_OVER_UPPER_TH field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH_Msk = 0x10000 + // Bit WAKEUP_OVER_UPPER_TH. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_OVER_UPPER_TH = 0x10000 + // Position of WAKEUP_MODE field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_MODE_Pos = 0x11 + // Bit mask of WAKEUP_MODE field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_MODE_Msk = 0x20000 + // Bit WAKEUP_MODE. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_MODE = 0x20000 + // Position of WAKEUP_EN field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_EN_Pos = 0x12 + // Bit mask of WAKEUP_EN field. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_EN_Msk = 0x40000 + // Bit WAKEUP_EN. + APB_SARADC_APB_TSENS_WAKE_WAKEUP_EN = 0x40000 + + // APB_TSENS_SAMPLE: digital tsens configure register + // Position of TSENS_SAMPLE_RATE field. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_RATE_Pos = 0x0 + // Bit mask of TSENS_SAMPLE_RATE field. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_RATE_Msk = 0xffff + // Position of TSENS_SAMPLE_EN field. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_EN_Pos = 0x10 + // Bit mask of TSENS_SAMPLE_EN field. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_EN_Msk = 0x10000 + // Bit TSENS_SAMPLE_EN. + APB_SARADC_APB_TSENS_SAMPLE_TSENS_SAMPLE_EN = 0x10000 + + // CTRL_DATE: version + // Position of DATE field. + APB_SARADC_CTRL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + APB_SARADC_CTRL_DATE_DATE_Msk = 0xffffffff +) + +// Constants for ASSIST_DEBUG: Debug Assist +const ( + // CORE_0_MONTR_ENA: core0 monitor enable configuration register + // Position of CORE_0_AREA_DRAM0_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA = 0x80 + // Position of CORE_0_SP_SPILL_MIN_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA = 0x100 + // Position of CORE_0_SP_SPILL_MAX_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_ENA. + ASSIST_DEBUG_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA = 0x800 + + // CORE_0_INTR_RAW: core0 monitor interrupt status register + // Position of CORE_0_AREA_DRAM0_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW = 0x80 + // Position of CORE_0_SP_SPILL_MIN_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW = 0x100 + // Position of CORE_0_SP_SPILL_MAX_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_RAW. + ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW = 0x800 + + // CORE_0_INTR_ENA: core0 monitor interrupt enable register + // Position of CORE_0_AREA_DRAM0_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA = 0x80 + // Position of CORE_0_SP_SPILL_MIN_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA = 0x100 + // Position of CORE_0_SP_SPILL_MAX_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA field. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA. + ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA = 0x800 + + // CORE_0_INTR_CLR: core0 monitor interrupt clr register + // Position of CORE_0_AREA_DRAM0_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR = 0x80 + // Position of CORE_0_SP_SPILL_MIN_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR = 0x100 + // Position of CORE_0_SP_SPILL_MAX_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_CLR. + ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR = 0x800 + + // CORE_0_AREA_DRAM0_0_MIN: core0 dram0 region0 addr configuration register + // Position of CORE_0_AREA_DRAM0_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_0_MAX: core0 dram0 region0 addr configuration register + // Position of CORE_0_AREA_DRAM0_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_1_MIN: core0 dram0 region1 addr configuration register + // Position of CORE_0_AREA_DRAM0_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_1_MAX: core0 dram0 region1 addr configuration register + // Position of CORE_0_AREA_DRAM0_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PIF_0_MIN: core0 PIF region0 addr configuration register + // Position of CORE_0_AREA_PIF_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_0_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Msk = 0xffffffff + + // CORE_0_AREA_PIF_0_MAX: core0 PIF region0 addr configuration register + // Position of CORE_0_AREA_PIF_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_0_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PIF_1_MIN: core0 PIF region1 addr configuration register + // Position of CORE_0_AREA_PIF_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_1_MIN field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Msk = 0xffffffff + + // CORE_0_AREA_PIF_1_MAX: core0 PIF region1 addr configuration register + // Position of CORE_0_AREA_PIF_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_1_MAX field. + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PC: core0 area pc status register + // Position of CORE_0_AREA_PC field. + ASSIST_DEBUG_CORE_0_AREA_PC_CORE_0_AREA_PC_Pos = 0x0 + // Bit mask of CORE_0_AREA_PC field. + ASSIST_DEBUG_CORE_0_AREA_PC_CORE_0_AREA_PC_Msk = 0xffffffff + + // CORE_0_AREA_SP: core0 area sp status register + // Position of CORE_0_AREA_SP field. + ASSIST_DEBUG_CORE_0_AREA_SP_CORE_0_AREA_SP_Pos = 0x0 + // Bit mask of CORE_0_AREA_SP field. + ASSIST_DEBUG_CORE_0_AREA_SP_CORE_0_AREA_SP_Msk = 0xffffffff + + // CORE_0_SP_MIN: stack min value + // Position of CORE_0_SP_MIN field. + ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Pos = 0x0 + // Bit mask of CORE_0_SP_MIN field. + ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Msk = 0xffffffff + + // CORE_0_SP_MAX: stack max value + // Position of CORE_0_SP_MAX field. + ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Pos = 0x0 + // Bit mask of CORE_0_SP_MAX field. + ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Msk = 0xffffffff + + // CORE_0_SP_PC: stack monitor pc status register + // Position of CORE_0_SP_PC field. + ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Pos = 0x0 + // Bit mask of CORE_0_SP_PC field. + ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Msk = 0xffffffff + + // CORE_0_RCD_EN: record enable configuration register + // Position of CORE_0_RCD_RECORDEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Pos = 0x0 + // Bit mask of CORE_0_RCD_RECORDEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Msk = 0x1 + // Bit CORE_0_RCD_RECORDEN. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN = 0x1 + // Position of CORE_0_RCD_PDEBUGEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Pos = 0x1 + // Bit mask of CORE_0_RCD_PDEBUGEN field. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Msk = 0x2 + // Bit CORE_0_RCD_PDEBUGEN. + ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN = 0x2 + + // CORE_0_RCD_PDEBUGPC: record status regsiter + // Position of CORE_0_RCD_PDEBUGPC field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGPC field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGSP: record status regsiter + // Position of CORE_0_RCD_PDEBUGSP field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGSP field. + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Msk = 0xffffffff + + // CORE_0_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0 + // Position of CORE_0_IRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Msk = 0xffffff + // Position of CORE_0_IRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Pos = 0x18 + // Bit mask of CORE_0_IRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Msk = 0x1000000 + // Bit CORE_0_IRAM0_RECORDING_WR_0. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0 = 0x1000000 + // Position of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Pos = 0x19 + // Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Msk = 0x2000000 + // Bit CORE_0_IRAM0_RECORDING_LOADSTORE_0. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0 = 0x2000000 + + // CORE_0_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1 + // Position of CORE_0_IRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Msk = 0xffffff + // Position of CORE_0_IRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Pos = 0x18 + // Bit mask of CORE_0_IRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Msk = 0x1000000 + // Bit CORE_0_IRAM0_RECORDING_WR_1. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1 = 0x1000000 + // Position of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Pos = 0x19 + // Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Msk = 0x2000000 + // Bit CORE_0_IRAM0_RECORDING_LOADSTORE_1. + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1 = 0x2000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2 + // Position of CORE_0_DRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_ADDR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0_Msk = 0xffffff + // Position of CORE_0_DRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Pos = 0x18 + // Bit mask of CORE_0_DRAM0_RECORDING_WR_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Msk = 0x1000000 + // Bit CORE_0_DRAM0_RECORDING_WR_0. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0 = 0x1000000 + // Position of CORE_0_DRAM0_RECORDING_BYTEEN_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0_Pos = 0x19 + // Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0_Msk = 0x1e000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3 + // Position of CORE_0_DRAM0_RECORDING_PC_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_PC_0_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_PC_0 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_PC_0_Msk = 0xffffffff + + // CORE_0_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4 + // Position of CORE_0_DRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_ADDR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_ADDR_1_Msk = 0xffffff + // Position of CORE_0_DRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1_Pos = 0x18 + // Bit mask of CORE_0_DRAM0_RECORDING_WR_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1_Msk = 0x1000000 + // Bit CORE_0_DRAM0_RECORDING_WR_1. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_WR_1 = 0x1000000 + // Position of CORE_0_DRAM0_RECORDING_BYTEEN_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1_Pos = 0x19 + // Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_BYTEEN_1_Msk = 0x1e000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5 + // Position of CORE_0_DRAM0_RECORDING_PC_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_PC_1_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_PC_1 field. + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_PC_1_Msk = 0xffffffff + + // CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register6 + // Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Msk = 0xfffff + + // CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register7 + // Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field. + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Msk = 0xfffff + + // C0RE_0_LASTPC_BEFORE_EXCEPTION: cpu status register + // Position of CORE_0_LASTPC_BEFORE_EXC field. + ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Pos = 0x0 + // Bit mask of CORE_0_LASTPC_BEFORE_EXC field. + ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Msk = 0xffffffff + + // C0RE_0_DEBUG_MODE: cpu status register + // Position of CORE_0_DEBUG_MODE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Pos = 0x0 + // Bit mask of CORE_0_DEBUG_MODE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Msk = 0x1 + // Bit CORE_0_DEBUG_MODE. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODE = 0x1 + // Position of CORE_0_DEBUG_MODULE_ACTIVE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Pos = 0x1 + // Bit mask of CORE_0_DEBUG_MODULE_ACTIVE field. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Msk = 0x2 + // Bit CORE_0_DEBUG_MODULE_ACTIVE. + ASSIST_DEBUG_C0RE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE = 0x2 + + // CLOCK_GATE: clock register + // Position of CLK_EN field. + ASSIST_DEBUG_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + ASSIST_DEBUG_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + ASSIST_DEBUG_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: version register + // Position of ASSIST_DEBUG_DATE field. + ASSIST_DEBUG_DATE_ASSIST_DEBUG_DATE_Pos = 0x0 + // Bit mask of ASSIST_DEBUG_DATE field. + ASSIST_DEBUG_DATE_ASSIST_DEBUG_DATE_Msk = 0xfffffff +) + +// Constants for DMA: DMA (Direct Memory Access) Controller +const ( + // IN_INT_RAW_CH0: Raw status interrupt of channel 0 + // Position of IN_DONE field. + DMA_IN_INT_RAW_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_RAW_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_RAW_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_RAW_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_RAW_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_RAW_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_RAW_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_RAW_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_RAW_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_RAW_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_RAW_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_RAW_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_OVF field. + DMA_IN_INT_RAW_CH_INFIFO_OVF_Pos = 0x5 + // Bit mask of INFIFO_OVF field. + DMA_IN_INT_RAW_CH_INFIFO_OVF_Msk = 0x20 + // Bit INFIFO_OVF. + DMA_IN_INT_RAW_CH_INFIFO_OVF = 0x20 + // Position of INFIFO_UDF field. + DMA_IN_INT_RAW_CH_INFIFO_UDF_Pos = 0x6 + // Bit mask of INFIFO_UDF field. + DMA_IN_INT_RAW_CH_INFIFO_UDF_Msk = 0x40 + // Bit INFIFO_UDF. + DMA_IN_INT_RAW_CH_INFIFO_UDF = 0x40 + + // IN_INT_ST_CH0: Masked interrupt of channel 0 + // Position of IN_DONE field. + DMA_IN_INT_ST_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_ST_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_ST_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_ST_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_ST_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_ST_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_ST_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_ST_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_ST_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_ST_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_ST_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_ST_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_ST_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_OVF field. + DMA_IN_INT_ST_CH_INFIFO_OVF_Pos = 0x5 + // Bit mask of INFIFO_OVF field. + DMA_IN_INT_ST_CH_INFIFO_OVF_Msk = 0x20 + // Bit INFIFO_OVF. + DMA_IN_INT_ST_CH_INFIFO_OVF = 0x20 + // Position of INFIFO_UDF field. + DMA_IN_INT_ST_CH_INFIFO_UDF_Pos = 0x6 + // Bit mask of INFIFO_UDF field. + DMA_IN_INT_ST_CH_INFIFO_UDF_Msk = 0x40 + // Bit INFIFO_UDF. + DMA_IN_INT_ST_CH_INFIFO_UDF = 0x40 + + // IN_INT_ENA_CH0: Interrupt enable bits of channel 0 + // Position of IN_DONE field. + DMA_IN_INT_ENA_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_ENA_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_ENA_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_ENA_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_ENA_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_ENA_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_ENA_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_ENA_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_ENA_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_ENA_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_ENA_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_ENA_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_OVF field. + DMA_IN_INT_ENA_CH_INFIFO_OVF_Pos = 0x5 + // Bit mask of INFIFO_OVF field. + DMA_IN_INT_ENA_CH_INFIFO_OVF_Msk = 0x20 + // Bit INFIFO_OVF. + DMA_IN_INT_ENA_CH_INFIFO_OVF = 0x20 + // Position of INFIFO_UDF field. + DMA_IN_INT_ENA_CH_INFIFO_UDF_Pos = 0x6 + // Bit mask of INFIFO_UDF field. + DMA_IN_INT_ENA_CH_INFIFO_UDF_Msk = 0x40 + // Bit INFIFO_UDF. + DMA_IN_INT_ENA_CH_INFIFO_UDF = 0x40 + + // IN_INT_CLR_CH0: Interrupt clear bits of channel 0 + // Position of IN_DONE field. + DMA_IN_INT_CLR_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_CLR_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_CLR_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_CLR_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_CLR_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_CLR_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_CLR_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_CLR_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_CLR_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_CLR_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_CLR_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_CLR_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_OVF field. + DMA_IN_INT_CLR_CH_INFIFO_OVF_Pos = 0x5 + // Bit mask of INFIFO_OVF field. + DMA_IN_INT_CLR_CH_INFIFO_OVF_Msk = 0x20 + // Bit INFIFO_OVF. + DMA_IN_INT_CLR_CH_INFIFO_OVF = 0x20 + // Position of INFIFO_UDF field. + DMA_IN_INT_CLR_CH_INFIFO_UDF_Pos = 0x6 + // Bit mask of INFIFO_UDF field. + DMA_IN_INT_CLR_CH_INFIFO_UDF_Msk = 0x40 + // Bit INFIFO_UDF. + DMA_IN_INT_CLR_CH_INFIFO_UDF = 0x40 + + // OUT_INT_RAW_CH0: Raw status interrupt of channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_RAW_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_RAW_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_RAW_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_RAW_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_RAW_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_RAW_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF field. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_Pos = 0x4 + // Bit mask of OUTFIFO_OVF field. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_Msk = 0x10 + // Bit OUTFIFO_OVF. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF = 0x10 + // Position of OUTFIFO_UDF field. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_Pos = 0x5 + // Bit mask of OUTFIFO_UDF field. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_Msk = 0x20 + // Bit OUTFIFO_UDF. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF = 0x20 + + // OUT_INT_ST_CH0: Masked interrupt of channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_ST_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_ST_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_ST_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_ST_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_ST_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_ST_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_ST_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF field. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_Pos = 0x4 + // Bit mask of OUTFIFO_OVF field. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_Msk = 0x10 + // Bit OUTFIFO_OVF. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF = 0x10 + // Position of OUTFIFO_UDF field. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_Pos = 0x5 + // Bit mask of OUTFIFO_UDF field. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_Msk = 0x20 + // Bit OUTFIFO_UDF. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF = 0x20 + + // OUT_INT_ENA_CH0: Interrupt enable bits of channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_ENA_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_ENA_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_ENA_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_ENA_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_ENA_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_ENA_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF field. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_Pos = 0x4 + // Bit mask of OUTFIFO_OVF field. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_Msk = 0x10 + // Bit OUTFIFO_OVF. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF = 0x10 + // Position of OUTFIFO_UDF field. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_Pos = 0x5 + // Bit mask of OUTFIFO_UDF field. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_Msk = 0x20 + // Bit OUTFIFO_UDF. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF = 0x20 + + // OUT_INT_CLR_CH0: Interrupt clear bits of channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_CLR_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_CLR_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_CLR_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_CLR_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_CLR_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_CLR_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF field. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_Pos = 0x4 + // Bit mask of OUTFIFO_OVF field. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_Msk = 0x10 + // Bit OUTFIFO_OVF. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF = 0x10 + // Position of OUTFIFO_UDF field. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_Pos = 0x5 + // Bit mask of OUTFIFO_UDF field. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_Msk = 0x20 + // Bit OUTFIFO_UDF. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF = 0x20 + + // AHB_TEST: reserved + // Position of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // MISC_CONF: MISC register + // Position of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Pos = 0x0 + // Bit mask of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Msk = 0x1 + // Bit AHBM_RST_INTER. + DMA_MISC_CONF_AHBM_RST_INTER = 0x1 + // Position of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Pos = 0x2 + // Bit mask of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Msk = 0x4 + // Bit ARB_PRI_DIS. + DMA_MISC_CONF_ARB_PRI_DIS = 0x4 + // Position of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Pos = 0x3 + // Bit mask of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Msk = 0x8 + // Bit CLK_EN. + DMA_MISC_CONF_CLK_EN = 0x8 + + // DATE: Version control register + // Position of DATE field. + DMA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DMA_DATE_DATE_Msk = 0xffffffff + + // IN_CONF0_CH0: Configure 0 register of Rx channel 0 + // Position of IN_RST field. + DMA_IN_CONF0_CH_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + DMA_IN_CONF0_CH_IN_RST_Msk = 0x1 + // Bit IN_RST. + DMA_IN_CONF0_CH_IN_RST = 0x1 + // Position of IN_LOOP_TEST field. + DMA_IN_CONF0_CH_IN_LOOP_TEST_Pos = 0x1 + // Bit mask of IN_LOOP_TEST field. + DMA_IN_CONF0_CH_IN_LOOP_TEST_Msk = 0x2 + // Bit IN_LOOP_TEST. + DMA_IN_CONF0_CH_IN_LOOP_TEST = 0x2 + // Position of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH_INDSCR_BURST_EN_Pos = 0x2 + // Bit mask of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH_INDSCR_BURST_EN_Msk = 0x4 + // Bit INDSCR_BURST_EN. + DMA_IN_CONF0_CH_INDSCR_BURST_EN = 0x4 + // Position of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH_IN_DATA_BURST_EN_Pos = 0x3 + // Bit mask of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH_IN_DATA_BURST_EN_Msk = 0x8 + // Bit IN_DATA_BURST_EN. + DMA_IN_CONF0_CH_IN_DATA_BURST_EN = 0x8 + // Position of MEM_TRANS_EN field. + DMA_IN_CONF0_CH_MEM_TRANS_EN_Pos = 0x4 + // Bit mask of MEM_TRANS_EN field. + DMA_IN_CONF0_CH_MEM_TRANS_EN_Msk = 0x10 + // Bit MEM_TRANS_EN. + DMA_IN_CONF0_CH_MEM_TRANS_EN = 0x10 + // Position of IN_ETM_EN field. + DMA_IN_CONF0_CH_IN_ETM_EN_Pos = 0x5 + // Bit mask of IN_ETM_EN field. + DMA_IN_CONF0_CH_IN_ETM_EN_Msk = 0x20 + // Bit IN_ETM_EN. + DMA_IN_CONF0_CH_IN_ETM_EN = 0x20 + + // IN_CONF1_CH0: Configure 1 register of Rx channel 0 + // Position of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH_IN_CHECK_OWNER_Pos = 0xc + // Bit mask of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH_IN_CHECK_OWNER_Msk = 0x1000 + // Bit IN_CHECK_OWNER. + DMA_IN_CONF1_CH_IN_CHECK_OWNER = 0x1000 + + // INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0 + // Position of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_Pos = 0x0 + // Bit mask of INFIFO_FULL field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_Msk = 0x1 + // Bit INFIFO_FULL. + DMA_INFIFO_STATUS_CH_INFIFO_FULL = 0x1 + // Position of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_Pos = 0x1 + // Bit mask of INFIFO_EMPTY field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_Msk = 0x2 + // Bit INFIFO_EMPTY. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY = 0x2 + // Position of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_Pos = 0x2 + // Bit mask of INFIFO_CNT field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_Msk = 0xfc + // Position of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of IN_REMAIN_UNDER_1B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit IN_REMAIN_UNDER_1B. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B = 0x800000 + // Position of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of IN_REMAIN_UNDER_2B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit IN_REMAIN_UNDER_2B. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B = 0x1000000 + // Position of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of IN_REMAIN_UNDER_3B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit IN_REMAIN_UNDER_3B. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B = 0x2000000 + // Position of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of IN_REMAIN_UNDER_4B field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit IN_REMAIN_UNDER_4B. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B = 0x4000000 + // Position of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_Pos = 0x1b + // Bit mask of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_Msk = 0x8000000 + // Bit IN_BUF_HUNGRY. + DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY = 0x8000000 + + // IN_POP_CH0: Pop control register of Rx channel 0 + // Position of INFIFO_RDATA field. + DMA_IN_POP_CH_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + DMA_IN_POP_CH_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + DMA_IN_POP_CH_INFIFO_POP_Pos = 0xc + // Bit mask of INFIFO_POP field. + DMA_IN_POP_CH_INFIFO_POP_Msk = 0x1000 + // Bit INFIFO_POP. + DMA_IN_POP_CH_INFIFO_POP = 0x1000 + + // IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0 + // Position of INLINK_ADDR field. + DMA_IN_LINK_CH_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + DMA_IN_LINK_CH_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + DMA_IN_LINK_CH_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + DMA_IN_LINK_CH_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + DMA_IN_LINK_CH_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + DMA_IN_LINK_CH_INLINK_STOP_Pos = 0x15 + // Bit mask of INLINK_STOP field. + DMA_IN_LINK_CH_INLINK_STOP_Msk = 0x200000 + // Bit INLINK_STOP. + DMA_IN_LINK_CH_INLINK_STOP = 0x200000 + // Position of INLINK_START field. + DMA_IN_LINK_CH_INLINK_START_Pos = 0x16 + // Bit mask of INLINK_START field. + DMA_IN_LINK_CH_INLINK_START_Msk = 0x400000 + // Bit INLINK_START. + DMA_IN_LINK_CH_INLINK_START = 0x400000 + // Position of INLINK_RESTART field. + DMA_IN_LINK_CH_INLINK_RESTART_Pos = 0x17 + // Bit mask of INLINK_RESTART field. + DMA_IN_LINK_CH_INLINK_RESTART_Msk = 0x800000 + // Bit INLINK_RESTART. + DMA_IN_LINK_CH_INLINK_RESTART = 0x800000 + // Position of INLINK_PARK field. + DMA_IN_LINK_CH_INLINK_PARK_Pos = 0x18 + // Bit mask of INLINK_PARK field. + DMA_IN_LINK_CH_INLINK_PARK_Msk = 0x1000000 + // Bit INLINK_PARK. + DMA_IN_LINK_CH_INLINK_PARK = 0x1000000 + + // IN_STATE_CH0: Receive status of Rx channel 0 + // Position of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH_INLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH_INLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of IN_DSCR_STATE field. + DMA_IN_STATE_CH_IN_DSCR_STATE_Pos = 0x12 + // Bit mask of IN_DSCR_STATE field. + DMA_IN_STATE_CH_IN_DSCR_STATE_Msk = 0xc0000 + // Position of IN_STATE field. + DMA_IN_STATE_CH_IN_STATE_Pos = 0x14 + // Bit mask of IN_STATE field. + DMA_IN_STATE_CH_IN_STATE_Msk = 0x700000 + + // IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0 + // Position of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0 + // Position of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR field. + DMA_IN_DSCR_CH_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + DMA_IN_DSCR_CH_INLINK_DSCR_Msk = 0xffffffff + + // IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_Msk = 0xffffffff + + // IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_Msk = 0xffffffff + + // IN_PRI_CH0: Priority register of Rx channel 0 + // Position of RX_PRI field. + DMA_IN_PRI_CH_RX_PRI_Pos = 0x0 + // Bit mask of RX_PRI field. + DMA_IN_PRI_CH_RX_PRI_Msk = 0xf + + // IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0 + // Position of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH_PERI_IN_SEL_Pos = 0x0 + // Bit mask of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH_PERI_IN_SEL_Msk = 0x3f + + // OUT_CONF1_CH0: Configure 1 register of Tx channel 0 + // Position of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_Pos = 0xc + // Bit mask of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_Msk = 0x1000 + // Bit OUT_CHECK_OWNER. + DMA_OUT_CONF1_CH_OUT_CHECK_OWNER = 0x1000 + + // OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0 + // Position of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_Pos = 0x0 + // Bit mask of OUTFIFO_FULL field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_Msk = 0x1 + // Bit OUTFIFO_FULL. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL = 0x1 + // Position of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_Pos = 0x1 + // Bit mask of OUTFIFO_EMPTY field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_Msk = 0x2 + // Bit OUTFIFO_EMPTY. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY = 0x2 + // Position of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_Pos = 0x2 + // Bit mask of OUTFIFO_CNT field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_Msk = 0xfc + // Position of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_Pos = 0x17 + // Bit mask of OUT_REMAIN_UNDER_1B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_Msk = 0x800000 + // Bit OUT_REMAIN_UNDER_1B. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B = 0x800000 + // Position of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_Pos = 0x18 + // Bit mask of OUT_REMAIN_UNDER_2B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_Msk = 0x1000000 + // Bit OUT_REMAIN_UNDER_2B. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B = 0x1000000 + // Position of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_Pos = 0x19 + // Bit mask of OUT_REMAIN_UNDER_3B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_Msk = 0x2000000 + // Bit OUT_REMAIN_UNDER_3B. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B = 0x2000000 + // Position of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_Pos = 0x1a + // Bit mask of OUT_REMAIN_UNDER_4B field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_Msk = 0x4000000 + // Bit OUT_REMAIN_UNDER_4B. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B = 0x4000000 + + // OUT_PUSH_CH0: Push control register of Rx channel 0 + // Position of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH_OUTFIFO_PUSH_Pos = 0x9 + // Bit mask of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH_OUTFIFO_PUSH_Msk = 0x200 + // Bit OUTFIFO_PUSH. + DMA_OUT_PUSH_CH_OUTFIFO_PUSH = 0x200 + + // OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0 + // Position of OUTLINK_ADDR field. + DMA_OUT_LINK_CH_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + DMA_OUT_LINK_CH_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + DMA_OUT_LINK_CH_OUTLINK_STOP_Pos = 0x14 + // Bit mask of OUTLINK_STOP field. + DMA_OUT_LINK_CH_OUTLINK_STOP_Msk = 0x100000 + // Bit OUTLINK_STOP. + DMA_OUT_LINK_CH_OUTLINK_STOP = 0x100000 + // Position of OUTLINK_START field. + DMA_OUT_LINK_CH_OUTLINK_START_Pos = 0x15 + // Bit mask of OUTLINK_START field. + DMA_OUT_LINK_CH_OUTLINK_START_Msk = 0x200000 + // Bit OUTLINK_START. + DMA_OUT_LINK_CH_OUTLINK_START = 0x200000 + // Position of OUTLINK_RESTART field. + DMA_OUT_LINK_CH_OUTLINK_RESTART_Pos = 0x16 + // Bit mask of OUTLINK_RESTART field. + DMA_OUT_LINK_CH_OUTLINK_RESTART_Msk = 0x400000 + // Bit OUTLINK_RESTART. + DMA_OUT_LINK_CH_OUTLINK_RESTART = 0x400000 + // Position of OUTLINK_PARK field. + DMA_OUT_LINK_CH_OUTLINK_PARK_Pos = 0x17 + // Bit mask of OUTLINK_PARK field. + DMA_OUT_LINK_CH_OUTLINK_PARK_Msk = 0x800000 + // Bit OUTLINK_PARK. + DMA_OUT_LINK_CH_OUTLINK_PARK = 0x800000 + + // OUT_STATE_CH0: Transmit status of Tx channel 0 + // Position of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH_OUT_DSCR_STATE_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH_OUT_DSCR_STATE_Msk = 0xc0000 + // Position of OUT_STATE field. + DMA_OUT_STATE_CH_OUT_STATE_Pos = 0x14 + // Bit mask of OUT_STATE field. + DMA_OUT_STATE_CH_OUT_STATE_Msk = 0x700000 + + // OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0 + // Position of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0 + // Position of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH_OUTLINK_DSCR_Msk = 0xffffffff + + // OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // OUT_PRI_CH0: Priority register of Tx channel 0. + // Position of TX_PRI field. + DMA_OUT_PRI_CH_TX_PRI_Pos = 0x0 + // Bit mask of TX_PRI field. + DMA_OUT_PRI_CH_TX_PRI_Msk = 0xf + + // OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0 + // Position of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_Pos = 0x0 + // Bit mask of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_Msk = 0x3f + + // OUT_CONF0_CH0: Configure 0 register of Tx channel 1 + // Position of OUT_RST field. + DMA_OUT_CONF0_CH_OUT_RST_Pos = 0x0 + // Bit mask of OUT_RST field. + DMA_OUT_CONF0_CH_OUT_RST_Msk = 0x1 + // Bit OUT_RST. + DMA_OUT_CONF0_CH_OUT_RST = 0x1 + // Position of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH_OUT_LOOP_TEST_Pos = 0x1 + // Bit mask of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH_OUT_LOOP_TEST_Msk = 0x2 + // Bit OUT_LOOP_TEST. + DMA_OUT_CONF0_CH_OUT_LOOP_TEST = 0x2 + // Position of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_Pos = 0x2 + // Bit mask of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_Msk = 0x4 + // Bit OUT_AUTO_WRBACK. + DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK = 0x4 + // Position of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH_OUT_EOF_MODE_Pos = 0x3 + // Bit mask of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH_OUT_EOF_MODE_Msk = 0x8 + // Bit OUT_EOF_MODE. + DMA_OUT_CONF0_CH_OUT_EOF_MODE = 0x8 + // Position of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_Pos = 0x4 + // Bit mask of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_Msk = 0x10 + // Bit OUTDSCR_BURST_EN. + DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN = 0x10 + // Position of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_Pos = 0x5 + // Bit mask of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_Msk = 0x20 + // Bit OUT_DATA_BURST_EN. + DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN = 0x20 + // Position of OUT_ETM_EN field. + DMA_OUT_CONF0_CH_OUT_ETM_EN_Pos = 0x6 + // Bit mask of OUT_ETM_EN field. + DMA_OUT_CONF0_CH_OUT_ETM_EN_Msk = 0x40 + // Bit OUT_ETM_EN. + DMA_OUT_CONF0_CH_OUT_ETM_EN = 0x40 +) + +// Constants for DS: Digital Signature +const ( + // SET_START: DS start control register + // Position of SET_START field. + DS_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + DS_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + DS_SET_START_SET_START = 0x1 + + // SET_CONTINUE: DS continue control register + // Position of SET_CONTINUE field. + DS_SET_CONTINUE_SET_CONTINUE_Pos = 0x0 + // Bit mask of SET_CONTINUE field. + DS_SET_CONTINUE_SET_CONTINUE_Msk = 0x1 + // Bit SET_CONTINUE. + DS_SET_CONTINUE_SET_CONTINUE = 0x1 + + // SET_FINISH: DS finish control register + // Position of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Pos = 0x0 + // Bit mask of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Msk = 0x1 + // Bit SET_FINISH. + DS_SET_FINISH_SET_FINISH = 0x1 + + // QUERY_BUSY: DS query busy register + // Position of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Pos = 0x0 + // Bit mask of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Msk = 0x1 + // Bit QUERY_BUSY. + DS_QUERY_BUSY_QUERY_BUSY = 0x1 + + // QUERY_KEY_WRONG: DS query key-wrong counter register + // Position of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Pos = 0x0 + // Bit mask of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Msk = 0xf + + // QUERY_CHECK: DS query check result register + // Position of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Pos = 0x0 + // Bit mask of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Msk = 0x1 + // Bit MD_ERROR. + DS_QUERY_CHECK_MD_ERROR = 0x1 + // Position of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Pos = 0x1 + // Bit mask of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Msk = 0x2 + // Bit PADDING_BAD. + DS_QUERY_CHECK_PADDING_BAD = 0x2 + + // DATE: DS version control register + // Position of DATE field. + DS_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DS_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for ECC: ECC (ECC Hardware Accelerator) +const ( + // MULT_INT_RAW: ECC interrupt raw register, valid in level. + // Position of CALC_DONE_INT_RAW field. + ECC_MULT_INT_RAW_CALC_DONE_INT_RAW_Pos = 0x0 + // Bit mask of CALC_DONE_INT_RAW field. + ECC_MULT_INT_RAW_CALC_DONE_INT_RAW_Msk = 0x1 + // Bit CALC_DONE_INT_RAW. + ECC_MULT_INT_RAW_CALC_DONE_INT_RAW = 0x1 + + // MULT_INT_ST: ECC interrupt status register. + // Position of CALC_DONE_INT_ST field. + ECC_MULT_INT_ST_CALC_DONE_INT_ST_Pos = 0x0 + // Bit mask of CALC_DONE_INT_ST field. + ECC_MULT_INT_ST_CALC_DONE_INT_ST_Msk = 0x1 + // Bit CALC_DONE_INT_ST. + ECC_MULT_INT_ST_CALC_DONE_INT_ST = 0x1 + + // MULT_INT_ENA: ECC interrupt enable register. + // Position of CALC_DONE_INT_ENA field. + ECC_MULT_INT_ENA_CALC_DONE_INT_ENA_Pos = 0x0 + // Bit mask of CALC_DONE_INT_ENA field. + ECC_MULT_INT_ENA_CALC_DONE_INT_ENA_Msk = 0x1 + // Bit CALC_DONE_INT_ENA. + ECC_MULT_INT_ENA_CALC_DONE_INT_ENA = 0x1 + + // MULT_INT_CLR: ECC interrupt clear register. + // Position of CALC_DONE_INT_CLR field. + ECC_MULT_INT_CLR_CALC_DONE_INT_CLR_Pos = 0x0 + // Bit mask of CALC_DONE_INT_CLR field. + ECC_MULT_INT_CLR_CALC_DONE_INT_CLR_Msk = 0x1 + // Bit CALC_DONE_INT_CLR. + ECC_MULT_INT_CLR_CALC_DONE_INT_CLR = 0x1 + + // MULT_CONF: ECC configure register + // Position of START field. + ECC_MULT_CONF_START_Pos = 0x0 + // Bit mask of START field. + ECC_MULT_CONF_START_Msk = 0x1 + // Bit START. + ECC_MULT_CONF_START = 0x1 + // Position of RESET field. + ECC_MULT_CONF_RESET_Pos = 0x1 + // Bit mask of RESET field. + ECC_MULT_CONF_RESET_Msk = 0x2 + // Bit RESET. + ECC_MULT_CONF_RESET = 0x2 + // Position of KEY_LENGTH field. + ECC_MULT_CONF_KEY_LENGTH_Pos = 0x2 + // Bit mask of KEY_LENGTH field. + ECC_MULT_CONF_KEY_LENGTH_Msk = 0x4 + // Bit KEY_LENGTH. + ECC_MULT_CONF_KEY_LENGTH = 0x4 + // Position of MOD_BASE field. + ECC_MULT_CONF_MOD_BASE_Pos = 0x3 + // Bit mask of MOD_BASE field. + ECC_MULT_CONF_MOD_BASE_Msk = 0x8 + // Bit MOD_BASE. + ECC_MULT_CONF_MOD_BASE = 0x8 + // Position of WORK_MODE field. + ECC_MULT_CONF_WORK_MODE_Pos = 0x4 + // Bit mask of WORK_MODE field. + ECC_MULT_CONF_WORK_MODE_Msk = 0xf0 + // Position of SECURITY_MODE field. + ECC_MULT_CONF_SECURITY_MODE_Pos = 0x8 + // Bit mask of SECURITY_MODE field. + ECC_MULT_CONF_SECURITY_MODE_Msk = 0x100 + // Bit SECURITY_MODE. + ECC_MULT_CONF_SECURITY_MODE = 0x100 + // Position of VERIFICATION_RESULT field. + ECC_MULT_CONF_VERIFICATION_RESULT_Pos = 0x1d + // Bit mask of VERIFICATION_RESULT field. + ECC_MULT_CONF_VERIFICATION_RESULT_Msk = 0x20000000 + // Bit VERIFICATION_RESULT. + ECC_MULT_CONF_VERIFICATION_RESULT = 0x20000000 + // Position of CLK_EN field. + ECC_MULT_CONF_CLK_EN_Pos = 0x1e + // Bit mask of CLK_EN field. + ECC_MULT_CONF_CLK_EN_Msk = 0x40000000 + // Bit CLK_EN. + ECC_MULT_CONF_CLK_EN = 0x40000000 + // Position of MEM_CLOCK_GATE_FORCE_ON field. + ECC_MULT_CONF_MEM_CLOCK_GATE_FORCE_ON_Pos = 0x1f + // Bit mask of MEM_CLOCK_GATE_FORCE_ON field. + ECC_MULT_CONF_MEM_CLOCK_GATE_FORCE_ON_Msk = 0x80000000 + // Bit MEM_CLOCK_GATE_FORCE_ON. + ECC_MULT_CONF_MEM_CLOCK_GATE_FORCE_ON = 0x80000000 + + // MULT_DATE: Version control register + // Position of DATE field. + ECC_MULT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + ECC_MULT_DATE_DATE_Msk = 0xfffffff +) + +// Constants for EFUSE: eFuse Controller +const ( + // PGM_DATA0: Register 0 that stores data to be programmed. + // Position of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Pos = 0x0 + // Bit mask of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Msk = 0xffffffff + + // PGM_DATA1: Register 1 that stores data to be programmed. + // Position of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Pos = 0x0 + // Bit mask of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Msk = 0xffffffff + + // PGM_DATA2: Register 2 that stores data to be programmed. + // Position of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Pos = 0x0 + // Bit mask of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Msk = 0xffffffff + + // PGM_DATA3: Register 3 that stores data to be programmed. + // Position of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Pos = 0x0 + // Bit mask of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Msk = 0xffffffff + + // PGM_DATA4: Register 4 that stores data to be programmed. + // Position of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Pos = 0x0 + // Bit mask of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Msk = 0xffffffff + + // PGM_DATA5: Register 5 that stores data to be programmed. + // Position of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Pos = 0x0 + // Bit mask of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Msk = 0xffffffff + + // PGM_DATA6: Register 6 that stores data to be programmed. + // Position of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Pos = 0x0 + // Bit mask of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Msk = 0xffffffff + + // PGM_DATA7: Register 7 that stores data to be programmed. + // Position of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Pos = 0x0 + // Bit mask of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Msk = 0xffffffff + + // PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Pos = 0x0 + // Bit mask of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Msk = 0xffffffff + + // PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Pos = 0x0 + // Bit mask of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Msk = 0xffffffff + + // PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Pos = 0x0 + // Bit mask of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Msk = 0xffffffff + + // RD_WR_DIS: BLOCK0 data register 0. + // Position of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Pos = 0x0 + // Bit mask of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Msk = 0xffffffff + + // RD_REPEAT_DATA0: BLOCK0 data register 1. + // Position of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Pos = 0x0 + // Bit mask of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Msk = 0x7f + // Position of RPT4_RESERVED0_4 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_4_Pos = 0x7 + // Bit mask of RPT4_RESERVED0_4 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_4_Msk = 0x80 + // Bit RPT4_RESERVED0_4. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_4 = 0x80 + // Position of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Pos = 0x8 + // Bit mask of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Msk = 0x100 + // Bit DIS_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE = 0x100 + // Position of DIS_USB_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG_Pos = 0x9 + // Bit mask of DIS_USB_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG_Msk = 0x200 + // Bit DIS_USB_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG = 0x200 + // Position of POWERGLITCH_EN field. + EFUSE_RD_REPEAT_DATA0_POWERGLITCH_EN_Pos = 0xa + // Bit mask of POWERGLITCH_EN field. + EFUSE_RD_REPEAT_DATA0_POWERGLITCH_EN_Msk = 0x400 + // Bit POWERGLITCH_EN. + EFUSE_RD_REPEAT_DATA0_POWERGLITCH_EN = 0x400 + // Position of DIS_USB_SERIAL_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG_Pos = 0xb + // Bit mask of DIS_USB_SERIAL_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG_Msk = 0x800 + // Bit DIS_USB_SERIAL_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG = 0x800 + // Position of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD = 0x1000 + // Position of SPI_DOWNLOAD_MSPI_DIS field. + EFUSE_RD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS_Pos = 0xd + // Bit mask of SPI_DOWNLOAD_MSPI_DIS field. + EFUSE_RD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS_Msk = 0x2000 + // Bit SPI_DOWNLOAD_MSPI_DIS. + EFUSE_RD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS = 0x2000 + // Position of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Pos = 0xe + // Bit mask of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Msk = 0x4000 + // Bit DIS_CAN. + EFUSE_RD_REPEAT_DATA0_DIS_CAN = 0x4000 + // Position of JTAG_SEL_ENABLE field. + EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE_Pos = 0xf + // Bit mask of JTAG_SEL_ENABLE field. + EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE_Msk = 0x8000 + // Bit JTAG_SEL_ENABLE. + EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE = 0x8000 + // Position of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Pos = 0x10 + // Bit mask of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Msk = 0x70000 + // Position of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Pos = 0x13 + // Bit mask of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Msk = 0x80000 + // Bit DIS_PAD_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG = 0x80000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x14 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x100000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT = 0x100000 + // Position of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Pos = 0x15 + // Bit mask of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Msk = 0x600000 + // Position of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Pos = 0x17 + // Bit mask of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Msk = 0x1800000 + // Position of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Pos = 0x19 + // Bit mask of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Msk = 0x2000000 + // Bit USB_EXCHG_PINS. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS = 0x2000000 + // Position of VDD_SPI_AS_GPIO field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_AS_GPIO_Pos = 0x1a + // Bit mask of VDD_SPI_AS_GPIO field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_AS_GPIO_Msk = 0x4000000 + // Bit VDD_SPI_AS_GPIO. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_AS_GPIO = 0x4000000 + // Position of RPT4_RESERVED0_2 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_2_Pos = 0x1b + // Bit mask of RPT4_RESERVED0_2 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_2_Msk = 0x18000000 + // Position of RPT4_RESERVED0_1 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_1_Pos = 0x1d + // Bit mask of RPT4_RESERVED0_1 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_1_Msk = 0x20000000 + // Bit RPT4_RESERVED0_1. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_1 = 0x20000000 + // Position of RPT4_RESERVED0_0 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_0_Pos = 0x1e + // Bit mask of RPT4_RESERVED0_0 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_0_Msk = 0xc0000000 + + // RD_REPEAT_DATA1: BLOCK0 data register 2. + // Position of RPT4_RESERVED1_1 field. + EFUSE_RD_REPEAT_DATA1_RPT4_RESERVED1_1_Pos = 0x0 + // Bit mask of RPT4_RESERVED1_1 field. + EFUSE_RD_REPEAT_DATA1_RPT4_RESERVED1_1_Msk = 0xffff + // Position of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0 = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1 = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2 = 0x800000 + // Position of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Msk = 0xf000000 + // Position of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Msk = 0xf0000000 + + // RD_REPEAT_DATA2: BLOCK0 data register 3. + // Position of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Msk = 0xf + // Position of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Msk = 0xf0 + // Position of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Msk = 0xf00 + // Position of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Pos = 0xc + // Bit mask of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Msk = 0xf000 + // Position of SEC_DPA_LEVEL field. + EFUSE_RD_REPEAT_DATA2_SEC_DPA_LEVEL_Pos = 0x10 + // Bit mask of SEC_DPA_LEVEL field. + EFUSE_RD_REPEAT_DATA2_SEC_DPA_LEVEL_Msk = 0x30000 + // Position of ECDSA_FORCE_USE_HARDWARE_K field. + EFUSE_RD_REPEAT_DATA2_ECDSA_FORCE_USE_HARDWARE_K_Pos = 0x12 + // Bit mask of ECDSA_FORCE_USE_HARDWARE_K field. + EFUSE_RD_REPEAT_DATA2_ECDSA_FORCE_USE_HARDWARE_K_Msk = 0x40000 + // Bit ECDSA_FORCE_USE_HARDWARE_K. + EFUSE_RD_REPEAT_DATA2_ECDSA_FORCE_USE_HARDWARE_K = 0x40000 + // Position of CRYPT_DPA_ENABLE field. + EFUSE_RD_REPEAT_DATA2_CRYPT_DPA_ENABLE_Pos = 0x13 + // Bit mask of CRYPT_DPA_ENABLE field. + EFUSE_RD_REPEAT_DATA2_CRYPT_DPA_ENABLE_Msk = 0x80000 + // Bit CRYPT_DPA_ENABLE. + EFUSE_RD_REPEAT_DATA2_CRYPT_DPA_ENABLE = 0x80000 + // Position of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Msk = 0x100000 + // Bit SECURE_BOOT_EN. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE = 0x200000 + // Position of RPT4_RESERVED2_0 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED2_0_Pos = 0x16 + // Bit mask of RPT4_RESERVED2_0 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED2_0_Msk = 0xfc00000 + // Position of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Pos = 0x1c + // Bit mask of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Msk = 0xf0000000 + + // RD_REPEAT_DATA3: BLOCK0 data register 4. + // Position of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE = 0x1 + // Position of DIS_DIRECT_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_DIRECT_BOOT_Pos = 0x1 + // Bit mask of DIS_DIRECT_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_DIRECT_BOOT_Msk = 0x2 + // Bit DIS_DIRECT_BOOT. + EFUSE_RD_REPEAT_DATA3_DIS_DIRECT_BOOT = 0x2 + // Position of DIS_USB_PRINT field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_PRINT_Pos = 0x2 + // Bit mask of DIS_USB_PRINT field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_PRINT_Msk = 0x4 + // Bit DIS_USB_PRINT. + EFUSE_RD_REPEAT_DATA3_DIS_USB_PRINT = 0x4 + // Position of RPT4_RESERVED3_5 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_5_Pos = 0x3 + // Bit mask of RPT4_RESERVED3_5 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_5_Msk = 0x8 + // Bit RPT4_RESERVED3_5. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_5 = 0x8 + // Position of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_Pos = 0x4 + // Bit mask of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_Msk = 0x10 + // Bit DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD = 0x20 + // Position of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Msk = 0xc0 + // Position of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Pos = 0x8 + // Bit mask of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Msk = 0x100 + // Bit FORCE_SEND_RESUME. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME = 0x100 + // Position of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Pos = 0x9 + // Bit mask of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Msk = 0x1fffe00 + // Position of SECURE_BOOT_DISABLE_FAST_WAKE field. + EFUSE_RD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE_Pos = 0x19 + // Bit mask of SECURE_BOOT_DISABLE_FAST_WAKE field. + EFUSE_RD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE_Msk = 0x2000000 + // Bit SECURE_BOOT_DISABLE_FAST_WAKE. + EFUSE_RD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE = 0x2000000 + // Position of HYS_EN_PAD0 field. + EFUSE_RD_REPEAT_DATA3_HYS_EN_PAD0_Pos = 0x1a + // Bit mask of HYS_EN_PAD0 field. + EFUSE_RD_REPEAT_DATA3_HYS_EN_PAD0_Msk = 0xfc000000 + + // RD_REPEAT_DATA4: BLOCK0 data register 5. + // Position of HYS_EN_PAD1 field. + EFUSE_RD_REPEAT_DATA4_HYS_EN_PAD1_Pos = 0x0 + // Bit mask of HYS_EN_PAD1 field. + EFUSE_RD_REPEAT_DATA4_HYS_EN_PAD1_Msk = 0x3fffff + // Position of RPT4_RESERVED4_1 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_1_Pos = 0x16 + // Bit mask of RPT4_RESERVED4_1 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_1_Msk = 0xc00000 + // Position of RPT4_RESERVED4_0 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_0_Pos = 0x18 + // Bit mask of RPT4_RESERVED4_0 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_0_Msk = 0xff000000 + + // RD_MAC_SYS_0: BLOCK1 data register $n. + // Position of MAC_0 field. + EFUSE_RD_MAC_SYS_0_MAC_0_Pos = 0x0 + // Bit mask of MAC_0 field. + EFUSE_RD_MAC_SYS_0_MAC_0_Msk = 0xffffffff + + // RD_MAC_SYS_1: BLOCK1 data register $n. + // Position of MAC_1 field. + EFUSE_RD_MAC_SYS_1_MAC_1_Pos = 0x0 + // Bit mask of MAC_1 field. + EFUSE_RD_MAC_SYS_1_MAC_1_Msk = 0xffff + // Position of MAC_EXT field. + EFUSE_RD_MAC_SYS_1_MAC_EXT_Pos = 0x10 + // Bit mask of MAC_EXT field. + EFUSE_RD_MAC_SYS_1_MAC_EXT_Msk = 0xffff0000 + + // RD_MAC_SYS_2: BLOCK1 data register $n. + // Position of MAC_RESERVED_1 field. + EFUSE_RD_MAC_SYS_2_MAC_RESERVED_1_Pos = 0x0 + // Bit mask of MAC_RESERVED_1 field. + EFUSE_RD_MAC_SYS_2_MAC_RESERVED_1_Msk = 0x3fff + // Position of MAC_RESERVED_0 field. + EFUSE_RD_MAC_SYS_2_MAC_RESERVED_0_Pos = 0xe + // Bit mask of MAC_RESERVED_0 field. + EFUSE_RD_MAC_SYS_2_MAC_RESERVED_0_Msk = 0xffffc000 + + // RD_MAC_SYS_3: BLOCK1 data register $n. + // Position of MAC_RESERVED_2 field. + EFUSE_RD_MAC_SYS_3_MAC_RESERVED_2_Pos = 0x0 + // Bit mask of MAC_RESERVED_2 field. + EFUSE_RD_MAC_SYS_3_MAC_RESERVED_2_Msk = 0x3ffff + // Position of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SYS_3_SYS_DATA_PART0_0_Pos = 0x12 + // Bit mask of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SYS_3_SYS_DATA_PART0_0_Msk = 0xfffc0000 + + // RD_MAC_SYS_4: BLOCK1 data register $n. + // Position of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SYS_4_SYS_DATA_PART0_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SYS_4_SYS_DATA_PART0_1_Msk = 0xffffffff + + // RD_MAC_SYS_5: BLOCK1 data register $n. + // Position of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SYS_5_SYS_DATA_PART0_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SYS_5_SYS_DATA_PART0_2_Msk = 0xffffffff + + // RD_SYS_PART1_DATA0: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_0 field. + EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_0 field. + EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Msk = 0xffffffff + + // RD_SYS_PART1_DATA1: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_1 field. + EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_1 field. + EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Msk = 0xffffffff + + // RD_SYS_PART1_DATA2: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_2 field. + EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_2 field. + EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Msk = 0xffffffff + + // RD_SYS_PART1_DATA3: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_3 field. + EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_3 field. + EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Msk = 0xffffffff + + // RD_SYS_PART1_DATA4: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_4 field. + EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_4 field. + EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Msk = 0xffffffff + + // RD_SYS_PART1_DATA5: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_5 field. + EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_5 field. + EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Msk = 0xffffffff + + // RD_SYS_PART1_DATA6: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_6 field. + EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_6 field. + EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Msk = 0xffffffff + + // RD_SYS_PART1_DATA7: Register $n of BLOCK2 (system). + // Position of SYS_DATA_PART1_7 field. + EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_7 field. + EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Msk = 0xffffffff + + // RD_USR_DATA0: Register $n of BLOCK3 (user). + // Position of USR_DATA0 field. + EFUSE_RD_USR_DATA0_USR_DATA0_Pos = 0x0 + // Bit mask of USR_DATA0 field. + EFUSE_RD_USR_DATA0_USR_DATA0_Msk = 0xffffffff + + // RD_USR_DATA1: Register $n of BLOCK3 (user). + // Position of USR_DATA1 field. + EFUSE_RD_USR_DATA1_USR_DATA1_Pos = 0x0 + // Bit mask of USR_DATA1 field. + EFUSE_RD_USR_DATA1_USR_DATA1_Msk = 0xffffffff + + // RD_USR_DATA2: Register $n of BLOCK3 (user). + // Position of USR_DATA2 field. + EFUSE_RD_USR_DATA2_USR_DATA2_Pos = 0x0 + // Bit mask of USR_DATA2 field. + EFUSE_RD_USR_DATA2_USR_DATA2_Msk = 0xffffffff + + // RD_USR_DATA3: Register $n of BLOCK3 (user). + // Position of USR_DATA3 field. + EFUSE_RD_USR_DATA3_USR_DATA3_Pos = 0x0 + // Bit mask of USR_DATA3 field. + EFUSE_RD_USR_DATA3_USR_DATA3_Msk = 0xffffffff + + // RD_USR_DATA4: Register $n of BLOCK3 (user). + // Position of USR_DATA4 field. + EFUSE_RD_USR_DATA4_USR_DATA4_Pos = 0x0 + // Bit mask of USR_DATA4 field. + EFUSE_RD_USR_DATA4_USR_DATA4_Msk = 0xffffffff + + // RD_USR_DATA5: Register $n of BLOCK3 (user). + // Position of USR_DATA5 field. + EFUSE_RD_USR_DATA5_USR_DATA5_Pos = 0x0 + // Bit mask of USR_DATA5 field. + EFUSE_RD_USR_DATA5_USR_DATA5_Msk = 0xffffffff + + // RD_USR_DATA6: Register $n of BLOCK3 (user). + // Position of USR_DATA6 field. + EFUSE_RD_USR_DATA6_USR_DATA6_Pos = 0x0 + // Bit mask of USR_DATA6 field. + EFUSE_RD_USR_DATA6_USR_DATA6_Msk = 0xffffffff + + // RD_USR_DATA7: Register $n of BLOCK3 (user). + // Position of USR_DATA7 field. + EFUSE_RD_USR_DATA7_USR_DATA7_Pos = 0x0 + // Bit mask of USR_DATA7 field. + EFUSE_RD_USR_DATA7_USR_DATA7_Msk = 0xffffffff + + // RD_KEY0_DATA0: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA0 field. + EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Pos = 0x0 + // Bit mask of KEY0_DATA0 field. + EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Msk = 0xffffffff + + // RD_KEY0_DATA1: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA1 field. + EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Pos = 0x0 + // Bit mask of KEY0_DATA1 field. + EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Msk = 0xffffffff + + // RD_KEY0_DATA2: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA2 field. + EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Pos = 0x0 + // Bit mask of KEY0_DATA2 field. + EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Msk = 0xffffffff + + // RD_KEY0_DATA3: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA3 field. + EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Pos = 0x0 + // Bit mask of KEY0_DATA3 field. + EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Msk = 0xffffffff + + // RD_KEY0_DATA4: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA4 field. + EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Pos = 0x0 + // Bit mask of KEY0_DATA4 field. + EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Msk = 0xffffffff + + // RD_KEY0_DATA5: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA5 field. + EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Pos = 0x0 + // Bit mask of KEY0_DATA5 field. + EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Msk = 0xffffffff + + // RD_KEY0_DATA6: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA6 field. + EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Pos = 0x0 + // Bit mask of KEY0_DATA6 field. + EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Msk = 0xffffffff + + // RD_KEY0_DATA7: Register $n of BLOCK4 (KEY0). + // Position of KEY0_DATA7 field. + EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Pos = 0x0 + // Bit mask of KEY0_DATA7 field. + EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Msk = 0xffffffff + + // RD_KEY1_DATA0: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA0 field. + EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Pos = 0x0 + // Bit mask of KEY1_DATA0 field. + EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Msk = 0xffffffff + + // RD_KEY1_DATA1: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA1 field. + EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Pos = 0x0 + // Bit mask of KEY1_DATA1 field. + EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Msk = 0xffffffff + + // RD_KEY1_DATA2: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA2 field. + EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Pos = 0x0 + // Bit mask of KEY1_DATA2 field. + EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Msk = 0xffffffff + + // RD_KEY1_DATA3: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA3 field. + EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Pos = 0x0 + // Bit mask of KEY1_DATA3 field. + EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Msk = 0xffffffff + + // RD_KEY1_DATA4: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA4 field. + EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Pos = 0x0 + // Bit mask of KEY1_DATA4 field. + EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Msk = 0xffffffff + + // RD_KEY1_DATA5: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA5 field. + EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Pos = 0x0 + // Bit mask of KEY1_DATA5 field. + EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Msk = 0xffffffff + + // RD_KEY1_DATA6: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA6 field. + EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Pos = 0x0 + // Bit mask of KEY1_DATA6 field. + EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Msk = 0xffffffff + + // RD_KEY1_DATA7: Register $n of BLOCK5 (KEY1). + // Position of KEY1_DATA7 field. + EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Pos = 0x0 + // Bit mask of KEY1_DATA7 field. + EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Msk = 0xffffffff + + // RD_KEY2_DATA0: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA0 field. + EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Pos = 0x0 + // Bit mask of KEY2_DATA0 field. + EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Msk = 0xffffffff + + // RD_KEY2_DATA1: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA1 field. + EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Pos = 0x0 + // Bit mask of KEY2_DATA1 field. + EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Msk = 0xffffffff + + // RD_KEY2_DATA2: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA2 field. + EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Pos = 0x0 + // Bit mask of KEY2_DATA2 field. + EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Msk = 0xffffffff + + // RD_KEY2_DATA3: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA3 field. + EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Pos = 0x0 + // Bit mask of KEY2_DATA3 field. + EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Msk = 0xffffffff + + // RD_KEY2_DATA4: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA4 field. + EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Pos = 0x0 + // Bit mask of KEY2_DATA4 field. + EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Msk = 0xffffffff + + // RD_KEY2_DATA5: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA5 field. + EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Pos = 0x0 + // Bit mask of KEY2_DATA5 field. + EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Msk = 0xffffffff + + // RD_KEY2_DATA6: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA6 field. + EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Pos = 0x0 + // Bit mask of KEY2_DATA6 field. + EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Msk = 0xffffffff + + // RD_KEY2_DATA7: Register $n of BLOCK6 (KEY2). + // Position of KEY2_DATA7 field. + EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Pos = 0x0 + // Bit mask of KEY2_DATA7 field. + EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Msk = 0xffffffff + + // RD_KEY3_DATA0: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA0 field. + EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Pos = 0x0 + // Bit mask of KEY3_DATA0 field. + EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Msk = 0xffffffff + + // RD_KEY3_DATA1: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA1 field. + EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Pos = 0x0 + // Bit mask of KEY3_DATA1 field. + EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Msk = 0xffffffff + + // RD_KEY3_DATA2: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA2 field. + EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Pos = 0x0 + // Bit mask of KEY3_DATA2 field. + EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Msk = 0xffffffff + + // RD_KEY3_DATA3: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA3 field. + EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Pos = 0x0 + // Bit mask of KEY3_DATA3 field. + EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Msk = 0xffffffff + + // RD_KEY3_DATA4: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA4 field. + EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Pos = 0x0 + // Bit mask of KEY3_DATA4 field. + EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Msk = 0xffffffff + + // RD_KEY3_DATA5: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA5 field. + EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Pos = 0x0 + // Bit mask of KEY3_DATA5 field. + EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Msk = 0xffffffff + + // RD_KEY3_DATA6: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA6 field. + EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Pos = 0x0 + // Bit mask of KEY3_DATA6 field. + EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Msk = 0xffffffff + + // RD_KEY3_DATA7: Register $n of BLOCK7 (KEY3). + // Position of KEY3_DATA7 field. + EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Pos = 0x0 + // Bit mask of KEY3_DATA7 field. + EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Msk = 0xffffffff + + // RD_KEY4_DATA0: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA0 field. + EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Pos = 0x0 + // Bit mask of KEY4_DATA0 field. + EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Msk = 0xffffffff + + // RD_KEY4_DATA1: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA1 field. + EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Pos = 0x0 + // Bit mask of KEY4_DATA1 field. + EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Msk = 0xffffffff + + // RD_KEY4_DATA2: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA2 field. + EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Pos = 0x0 + // Bit mask of KEY4_DATA2 field. + EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Msk = 0xffffffff + + // RD_KEY4_DATA3: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA3 field. + EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Pos = 0x0 + // Bit mask of KEY4_DATA3 field. + EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Msk = 0xffffffff + + // RD_KEY4_DATA4: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA4 field. + EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Pos = 0x0 + // Bit mask of KEY4_DATA4 field. + EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Msk = 0xffffffff + + // RD_KEY4_DATA5: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA5 field. + EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Pos = 0x0 + // Bit mask of KEY4_DATA5 field. + EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Msk = 0xffffffff + + // RD_KEY4_DATA6: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA6 field. + EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Pos = 0x0 + // Bit mask of KEY4_DATA6 field. + EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Msk = 0xffffffff + + // RD_KEY4_DATA7: Register $n of BLOCK8 (KEY4). + // Position of KEY4_DATA7 field. + EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Pos = 0x0 + // Bit mask of KEY4_DATA7 field. + EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Msk = 0xffffffff + + // RD_KEY5_DATA0: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA0 field. + EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Pos = 0x0 + // Bit mask of KEY5_DATA0 field. + EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Msk = 0xffffffff + + // RD_KEY5_DATA1: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA1 field. + EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Pos = 0x0 + // Bit mask of KEY5_DATA1 field. + EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Msk = 0xffffffff + + // RD_KEY5_DATA2: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA2 field. + EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Pos = 0x0 + // Bit mask of KEY5_DATA2 field. + EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Msk = 0xffffffff + + // RD_KEY5_DATA3: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA3 field. + EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Pos = 0x0 + // Bit mask of KEY5_DATA3 field. + EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Msk = 0xffffffff + + // RD_KEY5_DATA4: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA4 field. + EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Pos = 0x0 + // Bit mask of KEY5_DATA4 field. + EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Msk = 0xffffffff + + // RD_KEY5_DATA5: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA5 field. + EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Pos = 0x0 + // Bit mask of KEY5_DATA5 field. + EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Msk = 0xffffffff + + // RD_KEY5_DATA6: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA6 field. + EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Pos = 0x0 + // Bit mask of KEY5_DATA6 field. + EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Msk = 0xffffffff + + // RD_KEY5_DATA7: Register $n of BLOCK9 (KEY5). + // Position of KEY5_DATA7 field. + EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Pos = 0x0 + // Bit mask of KEY5_DATA7 field. + EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Msk = 0xffffffff + + // RD_SYS_PART2_DATA0: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_0 field. + EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_0 field. + EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Msk = 0xffffffff + + // RD_SYS_PART2_DATA1: Register $n of BLOCK9 (KEY5). + // Position of SYS_DATA_PART2_1 field. + EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_1 field. + EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Msk = 0xffffffff + + // RD_SYS_PART2_DATA2: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_2 field. + EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_2 field. + EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Msk = 0xffffffff + + // RD_SYS_PART2_DATA3: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_3 field. + EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_3 field. + EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Msk = 0xffffffff + + // RD_SYS_PART2_DATA4: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_4 field. + EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_4 field. + EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Msk = 0xffffffff + + // RD_SYS_PART2_DATA5: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_5 field. + EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_5 field. + EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Msk = 0xffffffff + + // RD_SYS_PART2_DATA6: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_6 field. + EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_6 field. + EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Msk = 0xffffffff + + // RD_SYS_PART2_DATA7: Register $n of BLOCK10 (system). + // Position of SYS_DATA_PART2_7 field. + EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_7 field. + EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Msk = 0xffffffff + + // RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. + // Position of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Pos = 0x0 + // Bit mask of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Msk = 0x7f + // Position of RPT4_RESERVED0_ERR_4 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_4_Pos = 0x7 + // Bit mask of RPT4_RESERVED0_ERR_4 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_4_Msk = 0x80 + // Bit RPT4_RESERVED0_ERR_4. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_4 = 0x80 + // Position of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Pos = 0x8 + // Bit mask of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Msk = 0x100 + // Bit DIS_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR = 0x100 + // Position of DIS_USB_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR_Pos = 0x9 + // Bit mask of DIS_USB_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR_Msk = 0x200 + // Bit DIS_USB_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR = 0x200 + // Position of POWERGLITCH_EN_ERR field. + EFUSE_RD_REPEAT_ERR0_POWERGLITCH_EN_ERR_Pos = 0xa + // Bit mask of POWERGLITCH_EN_ERR field. + EFUSE_RD_REPEAT_ERR0_POWERGLITCH_EN_ERR_Msk = 0x400 + // Bit POWERGLITCH_EN_ERR. + EFUSE_RD_REPEAT_ERR0_POWERGLITCH_EN_ERR = 0x400 + // Position of DIS_USB_SERIAL_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR_Pos = 0xb + // Bit mask of DIS_USB_SERIAL_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR_Msk = 0x800 + // Bit DIS_USB_SERIAL_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR = 0x800 + // Position of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR = 0x1000 + // Position of SPI_DOWNLOAD_MSPI_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR_Pos = 0xd + // Bit mask of SPI_DOWNLOAD_MSPI_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR_Msk = 0x2000 + // Bit SPI_DOWNLOAD_MSPI_DIS_ERR. + EFUSE_RD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR = 0x2000 + // Position of DIS_TWAI_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_TWAI_ERR_Pos = 0xe + // Bit mask of DIS_TWAI_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_TWAI_ERR_Msk = 0x4000 + // Bit DIS_TWAI_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_TWAI_ERR = 0x4000 + // Position of JTAG_SEL_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR_Pos = 0xf + // Bit mask of JTAG_SEL_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR_Msk = 0x8000 + // Bit JTAG_SEL_ENABLE_ERR. + EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR = 0x8000 + // Position of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Pos = 0x10 + // Bit mask of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Msk = 0x70000 + // Position of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Pos = 0x13 + // Bit mask of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Msk = 0x80000 + // Bit DIS_PAD_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR = 0x80000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Pos = 0x14 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Msk = 0x100000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR = 0x100000 + // Position of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Pos = 0x15 + // Bit mask of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Msk = 0x600000 + // Position of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Pos = 0x17 + // Bit mask of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Msk = 0x1800000 + // Position of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Pos = 0x19 + // Bit mask of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Msk = 0x2000000 + // Bit USB_EXCHG_PINS_ERR. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR = 0x2000000 + // Position of VDD_SPI_AS_GPIO_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR_Pos = 0x1a + // Bit mask of VDD_SPI_AS_GPIO_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR_Msk = 0x4000000 + // Bit VDD_SPI_AS_GPIO_ERR. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_AS_GPIO_ERR = 0x4000000 + // Position of RPT4_RESERVED0_ERR_2 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_2_Pos = 0x1b + // Bit mask of RPT4_RESERVED0_ERR_2 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_2_Msk = 0x18000000 + // Position of RPT4_RESERVED0_ERR_1 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1_Pos = 0x1d + // Bit mask of RPT4_RESERVED0_ERR_1 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1_Msk = 0x20000000 + // Bit RPT4_RESERVED0_ERR_1. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_1 = 0x20000000 + // Position of RPT4_RESERVED0_ERR_0 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_0_Pos = 0x1e + // Bit mask of RPT4_RESERVED0_ERR_0 field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_0_Msk = 0xc0000000 + + // RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. + // Position of RPT4_RESERVED1_ERR_0 field. + EFUSE_RD_REPEAT_ERR1_RPT4_RESERVED1_ERR_0_Pos = 0x0 + // Bit mask of RPT4_RESERVED1_ERR_0 field. + EFUSE_RD_REPEAT_ERR1_RPT4_RESERVED1_ERR_0_Msk = 0xffff + // Position of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR = 0x800000 + // Position of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Msk = 0xf000000 + // Position of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. + // Position of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Msk = 0xf + // Position of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Msk = 0xf0 + // Position of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Msk = 0xf00 + // Position of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Pos = 0xc + // Bit mask of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Msk = 0xf000 + // Position of SEC_DPA_LEVEL_ERR field. + EFUSE_RD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR_Pos = 0x10 + // Bit mask of SEC_DPA_LEVEL_ERR field. + EFUSE_RD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR_Msk = 0x30000 + // Position of RPT4_RESERVED2_ERR_1 field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1_Pos = 0x12 + // Bit mask of RPT4_RESERVED2_ERR_1 field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1_Msk = 0x40000 + // Bit RPT4_RESERVED2_ERR_1. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_1 = 0x40000 + // Position of CRYPT_DPA_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR_Pos = 0x13 + // Bit mask of CRYPT_DPA_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR_Msk = 0x80000 + // Bit CRYPT_DPA_ENABLE_ERR. + EFUSE_RD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR = 0x80000 + // Position of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Msk = 0x100000 + // Bit SECURE_BOOT_EN_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR = 0x200000 + // Position of RPT4_RESERVED2_ERR_0 field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_0_Pos = 0x16 + // Bit mask of RPT4_RESERVED2_ERR_0 field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED2_ERR_0_Msk = 0xfc00000 + // Position of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Pos = 0x1c + // Bit mask of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. + // Position of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR = 0x1 + // Position of DIS_DIRECT_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR_Pos = 0x1 + // Bit mask of DIS_DIRECT_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR_Msk = 0x2 + // Bit DIS_DIRECT_BOOT_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR = 0x2 + // Position of USB_PRINT_ERR field. + EFUSE_RD_REPEAT_ERR3_USB_PRINT_ERR_Pos = 0x2 + // Bit mask of USB_PRINT_ERR field. + EFUSE_RD_REPEAT_ERR3_USB_PRINT_ERR_Msk = 0x4 + // Bit USB_PRINT_ERR. + EFUSE_RD_REPEAT_ERR3_USB_PRINT_ERR = 0x4 + // Position of RPT4_RESERVED3_ERR_5 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5_Pos = 0x3 + // Bit mask of RPT4_RESERVED3_ERR_5 field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5_Msk = 0x8 + // Bit RPT4_RESERVED3_ERR_5. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_5 = 0x8 + // Position of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_Pos = 0x4 + // Bit mask of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_Msk = 0x10 + // Bit DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR = 0x20 + // Position of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Msk = 0xc0 + // Position of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Pos = 0x8 + // Bit mask of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Msk = 0x100 + // Bit FORCE_SEND_RESUME_ERR. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR = 0x100 + // Position of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Pos = 0x9 + // Bit mask of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Msk = 0x1fffe00 + // Position of SECURE_BOOT_DISABLE_FAST_WAKE_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_Pos = 0x19 + // Bit mask of SECURE_BOOT_DISABLE_FAST_WAKE_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_Msk = 0x2000000 + // Bit SECURE_BOOT_DISABLE_FAST_WAKE_ERR. + EFUSE_RD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR = 0x2000000 + // Position of HYS_EN_PAD0_ERR field. + EFUSE_RD_REPEAT_ERR3_HYS_EN_PAD0_ERR_Pos = 0x1a + // Bit mask of HYS_EN_PAD0_ERR field. + EFUSE_RD_REPEAT_ERR3_HYS_EN_PAD0_ERR_Msk = 0xfc000000 + + // RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. + // Position of HYS_EN_PAD1_ERR field. + EFUSE_RD_REPEAT_ERR4_HYS_EN_PAD1_ERR_Pos = 0x0 + // Bit mask of HYS_EN_PAD1_ERR field. + EFUSE_RD_REPEAT_ERR4_HYS_EN_PAD1_ERR_Msk = 0x3fffff + // Position of RPT4_RESERVED4_ERR_1 field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_1_Pos = 0x16 + // Bit mask of RPT4_RESERVED4_ERR_1 field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_1_Msk = 0xc00000 + // Position of RPT4_RESERVED4_ERR_0 field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_0_Pos = 0x18 + // Bit mask of RPT4_RESERVED4_ERR_0 field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_0_Msk = 0xff000000 + + // RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. + // Position of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Pos = 0x0 + // Bit mask of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Msk = 0x7 + // Position of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Pos = 0x3 + // Bit mask of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Msk = 0x8 + // Bit MAC_SPI_8M_FAIL. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL = 0x8 + // Position of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Pos = 0x4 + // Bit mask of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Msk = 0x70 + // Position of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Pos = 0x7 + // Bit mask of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Msk = 0x80 + // Bit SYS_PART1_FAIL. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL = 0x80 + // Position of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Pos = 0x8 + // Bit mask of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Msk = 0x700 + // Position of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Pos = 0xb + // Bit mask of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Msk = 0x800 + // Bit USR_DATA_FAIL. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL = 0x800 + // Position of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Pos = 0xc + // Bit mask of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Msk = 0x7000 + // Position of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Pos = 0xf + // Bit mask of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Msk = 0x8000 + // Bit KEY0_FAIL. + EFUSE_RD_RS_ERR0_KEY0_FAIL = 0x8000 + // Position of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Pos = 0x10 + // Bit mask of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Msk = 0x70000 + // Position of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Pos = 0x13 + // Bit mask of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Msk = 0x80000 + // Bit KEY1_FAIL. + EFUSE_RD_RS_ERR0_KEY1_FAIL = 0x80000 + // Position of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Pos = 0x14 + // Bit mask of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Msk = 0x700000 + // Position of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Pos = 0x17 + // Bit mask of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Msk = 0x800000 + // Bit KEY2_FAIL. + EFUSE_RD_RS_ERR0_KEY2_FAIL = 0x800000 + // Position of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Pos = 0x18 + // Bit mask of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Msk = 0x7000000 + // Position of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Pos = 0x1b + // Bit mask of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Msk = 0x8000000 + // Bit KEY3_FAIL. + EFUSE_RD_RS_ERR0_KEY3_FAIL = 0x8000000 + // Position of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Pos = 0x1c + // Bit mask of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Msk = 0x70000000 + // Position of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Pos = 0x1f + // Bit mask of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Msk = 0x80000000 + // Bit KEY4_FAIL. + EFUSE_RD_RS_ERR0_KEY4_FAIL = 0x80000000 + + // RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. + // Position of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Pos = 0x0 + // Bit mask of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Msk = 0x7 + // Position of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Pos = 0x3 + // Bit mask of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Msk = 0x8 + // Bit KEY5_FAIL. + EFUSE_RD_RS_ERR1_KEY5_FAIL = 0x8 + // Position of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Pos = 0x4 + // Bit mask of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Msk = 0x70 + // Position of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Pos = 0x7 + // Bit mask of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Msk = 0x80 + // Bit SYS_PART2_FAIL. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL = 0x80 + + // CLK: eFuse clcok configuration register. + // Position of MEM_FORCE_PD field. + EFUSE_CLK_MEM_FORCE_PD_Pos = 0x0 + // Bit mask of MEM_FORCE_PD field. + EFUSE_CLK_MEM_FORCE_PD_Msk = 0x1 + // Bit MEM_FORCE_PD. + EFUSE_CLK_MEM_FORCE_PD = 0x1 + // Position of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + EFUSE_CLK_MEM_CLK_FORCE_ON = 0x2 + // Position of MEM_FORCE_PU field. + EFUSE_CLK_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of MEM_FORCE_PU field. + EFUSE_CLK_MEM_FORCE_PU_Msk = 0x4 + // Bit MEM_FORCE_PU. + EFUSE_CLK_MEM_FORCE_PU = 0x4 + // Position of EN field. + EFUSE_CLK_EN_Pos = 0x10 + // Bit mask of EN field. + EFUSE_CLK_EN_Msk = 0x10000 + // Bit EN. + EFUSE_CLK_EN = 0x10000 + + // CONF: eFuse operation mode configuraiton register + // Position of OP_CODE field. + EFUSE_CONF_OP_CODE_Pos = 0x0 + // Bit mask of OP_CODE field. + EFUSE_CONF_OP_CODE_Msk = 0xffff + // Position of CFG_ECDSA_BLK field. + EFUSE_CONF_CFG_ECDSA_BLK_Pos = 0x10 + // Bit mask of CFG_ECDSA_BLK field. + EFUSE_CONF_CFG_ECDSA_BLK_Msk = 0xf0000 + + // STATUS: eFuse status register. + // Position of STATE field. + EFUSE_STATUS_STATE_Pos = 0x0 + // Bit mask of STATE field. + EFUSE_STATUS_STATE_Msk = 0xf + // Position of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Pos = 0x4 + // Bit mask of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Msk = 0x10 + // Bit OTP_LOAD_SW. + EFUSE_STATUS_OTP_LOAD_SW = 0x10 + // Position of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Pos = 0x5 + // Bit mask of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Msk = 0x20 + // Bit OTP_VDDQ_C_SYNC2. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2 = 0x20 + // Position of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Pos = 0x6 + // Bit mask of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Msk = 0x40 + // Bit OTP_STROBE_SW. + EFUSE_STATUS_OTP_STROBE_SW = 0x40 + // Position of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Pos = 0x7 + // Bit mask of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Msk = 0x80 + // Bit OTP_CSB_SW. + EFUSE_STATUS_OTP_CSB_SW = 0x80 + // Position of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Pos = 0x8 + // Bit mask of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Msk = 0x100 + // Bit OTP_PGENB_SW. + EFUSE_STATUS_OTP_PGENB_SW = 0x100 + // Position of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Pos = 0x9 + // Bit mask of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Msk = 0x200 + // Bit OTP_VDDQ_IS_SW. + EFUSE_STATUS_OTP_VDDQ_IS_SW = 0x200 + // Position of BLK0_VALID_BIT_CNT field. + EFUSE_STATUS_BLK0_VALID_BIT_CNT_Pos = 0xa + // Bit mask of BLK0_VALID_BIT_CNT field. + EFUSE_STATUS_BLK0_VALID_BIT_CNT_Msk = 0xffc00 + // Position of CUR_ECDSA_BLK field. + EFUSE_STATUS_CUR_ECDSA_BLK_Pos = 0x14 + // Bit mask of CUR_ECDSA_BLK field. + EFUSE_STATUS_CUR_ECDSA_BLK_Msk = 0xf00000 + + // CMD: eFuse command register. + // Position of READ_CMD field. + EFUSE_CMD_READ_CMD_Pos = 0x0 + // Bit mask of READ_CMD field. + EFUSE_CMD_READ_CMD_Msk = 0x1 + // Bit READ_CMD. + EFUSE_CMD_READ_CMD = 0x1 + // Position of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Pos = 0x1 + // Bit mask of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Msk = 0x2 + // Bit PGM_CMD. + EFUSE_CMD_PGM_CMD = 0x2 + // Position of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Pos = 0x2 + // Bit mask of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Msk = 0x3c + + // INT_RAW: eFuse raw interrupt register. + // Position of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Pos = 0x0 + // Bit mask of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Msk = 0x1 + // Bit READ_DONE_INT_RAW. + EFUSE_INT_RAW_READ_DONE_INT_RAW = 0x1 + // Position of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Pos = 0x1 + // Bit mask of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Msk = 0x2 + // Bit PGM_DONE_INT_RAW. + EFUSE_INT_RAW_PGM_DONE_INT_RAW = 0x2 + + // INT_ST: eFuse interrupt status register. + // Position of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Pos = 0x0 + // Bit mask of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Msk = 0x1 + // Bit READ_DONE_INT_ST. + EFUSE_INT_ST_READ_DONE_INT_ST = 0x1 + // Position of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Msk = 0x2 + // Bit PGM_DONE_INT_ST. + EFUSE_INT_ST_PGM_DONE_INT_ST = 0x2 + + // INT_ENA: eFuse interrupt enable register. + // Position of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Pos = 0x0 + // Bit mask of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Msk = 0x1 + // Bit READ_DONE_INT_ENA. + EFUSE_INT_ENA_READ_DONE_INT_ENA = 0x1 + // Position of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Msk = 0x2 + // Bit PGM_DONE_INT_ENA. + EFUSE_INT_ENA_PGM_DONE_INT_ENA = 0x2 + + // INT_CLR: eFuse interrupt clear register. + // Position of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Pos = 0x0 + // Bit mask of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Msk = 0x1 + // Bit READ_DONE_INT_CLR. + EFUSE_INT_CLR_READ_DONE_INT_CLR = 0x1 + // Position of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Pos = 0x1 + // Bit mask of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Msk = 0x2 + // Bit PGM_DONE_INT_CLR. + EFUSE_INT_CLR_PGM_DONE_INT_CLR = 0x2 + + // DAC_CONF: Controls the eFuse programming voltage. + // Position of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Pos = 0x0 + // Bit mask of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Msk = 0xff + // Position of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Pos = 0x8 + // Bit mask of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Msk = 0x100 + // Bit DAC_CLK_PAD_SEL. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL = 0x100 + // Position of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Pos = 0x9 + // Bit mask of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Msk = 0x1fe00 + // Position of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Pos = 0x11 + // Bit mask of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Msk = 0x20000 + // Bit OE_CLR. + EFUSE_DAC_CONF_OE_CLR = 0x20000 + + // RD_TIM_CONF: Configures read timing parameters. + // Position of THR_A field. + EFUSE_RD_TIM_CONF_THR_A_Pos = 0x0 + // Bit mask of THR_A field. + EFUSE_RD_TIM_CONF_THR_A_Msk = 0xff + // Position of TRD field. + EFUSE_RD_TIM_CONF_TRD_Pos = 0x8 + // Bit mask of TRD field. + EFUSE_RD_TIM_CONF_TRD_Msk = 0xff00 + // Position of TSUR_A field. + EFUSE_RD_TIM_CONF_TSUR_A_Pos = 0x10 + // Bit mask of TSUR_A field. + EFUSE_RD_TIM_CONF_TSUR_A_Msk = 0xff0000 + // Position of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Pos = 0x18 + // Bit mask of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Msk = 0xff000000 + + // WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters. + // Position of TSUP_A field. + EFUSE_WR_TIM_CONF1_TSUP_A_Pos = 0x0 + // Bit mask of TSUP_A field. + EFUSE_WR_TIM_CONF1_TSUP_A_Msk = 0xff + // Position of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Pos = 0x8 + // Bit mask of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Msk = 0xffff00 + // Position of THP_A field. + EFUSE_WR_TIM_CONF1_THP_A_Pos = 0x18 + // Bit mask of THP_A field. + EFUSE_WR_TIM_CONF1_THP_A_Msk = 0xff000000 + + // WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters. + // Position of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Pos = 0x0 + // Bit mask of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Msk = 0xffff + // Position of TPGM field. + EFUSE_WR_TIM_CONF2_TPGM_Pos = 0x10 + // Bit mask of TPGM field. + EFUSE_WR_TIM_CONF2_TPGM_Msk = 0xffff0000 + + // WR_TIM_CONF0_RS_BYPASS: Configurarion register0 of eFuse programming time parameters and rs bypass operation. + // Position of BYPASS_RS_CORRECTION field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION_Pos = 0x0 + // Bit mask of BYPASS_RS_CORRECTION field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION_Msk = 0x1 + // Bit BYPASS_RS_CORRECTION. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION = 0x1 + // Position of BYPASS_RS_BLK_NUM field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM_Pos = 0x1 + // Bit mask of BYPASS_RS_BLK_NUM field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM_Msk = 0xffe + // Position of UPDATE field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_UPDATE_Pos = 0xc + // Bit mask of UPDATE field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_UPDATE_Msk = 0x1000 + // Bit UPDATE. + EFUSE_WR_TIM_CONF0_RS_BYPASS_UPDATE = 0x1000 + // Position of TPGM_INACTIVE field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE_Pos = 0xd + // Bit mask of TPGM_INACTIVE field. + EFUSE_WR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE_Msk = 0x1fe000 + + // DATE: eFuse version register. + // Position of DATE field. + EFUSE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EFUSE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for GPIO: General Purpose Input/Output +const ( + // BT_SELECT: GPIO bit select register + // Position of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Pos = 0x0 + // Bit mask of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Msk = 0xffffffff + + // OUT: GPIO output register for GPIO0-31 + // Position of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Pos = 0x0 + // Bit mask of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Msk = 0xffffffff + + // OUT_W1TS: GPIO output set register for GPIO0-31 + // Position of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Pos = 0x0 + // Bit mask of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Msk = 0xffffffff + + // OUT_W1TC: GPIO output clear register for GPIO0-31 + // Position of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Pos = 0x0 + // Bit mask of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Msk = 0xffffffff + + // SDIO_SELECT: GPIO sdio select register + // Position of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Pos = 0x0 + // Bit mask of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Msk = 0xff + + // ENABLE: GPIO output enable register for GPIO0-31 + // Position of DATA field. + GPIO_ENABLE_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE_DATA_Msk = 0xffffffff + + // ENABLE_W1TS: GPIO output enable set register for GPIO0-31 + // Position of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Pos = 0x0 + // Bit mask of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Msk = 0xffffffff + + // ENABLE_W1TC: GPIO output enable clear register for GPIO0-31 + // Position of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0x0 + // Bit mask of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0xffffffff + + // STRAP: pad strapping register + // Position of STRAPPING field. + GPIO_STRAP_STRAPPING_Pos = 0x0 + // Bit mask of STRAPPING field. + GPIO_STRAP_STRAPPING_Msk = 0xffff + + // IN: GPIO input register for GPIO0-31 + // Position of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Msk = 0xffffffff + + // STATUS: GPIO interrupt status register for GPIO0-31 + // Position of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Msk = 0xffffffff + + // STATUS_W1TS: GPIO interrupt status set register for GPIO0-31 + // Position of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Pos = 0x0 + // Bit mask of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Msk = 0xffffffff + + // STATUS_W1TC: GPIO interrupt status clear register for GPIO0-31 + // Position of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Pos = 0x0 + // Bit mask of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Msk = 0xffffffff + + // PCPU_INT: GPIO PRO_CPU interrupt status register for GPIO0-31 + // Position of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Pos = 0x0 + // Bit mask of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Msk = 0xffffffff + + // PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + // Position of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Msk = 0xffffffff + + // CPUSDIO_INT: GPIO CPUSDIO interrupt status register for GPIO0-31 + // Position of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Pos = 0x0 + // Bit mask of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Msk = 0xffffffff + + // PIN0: GPIO pin configuration register + // Position of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Pos = 0x0 + // Bit mask of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Msk = 0x3 + // Position of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + GPIO_PIN_PAD_DRIVER = 0x4 + // Position of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Pos = 0x3 + // Bit mask of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Msk = 0x18 + // Position of INT_TYPE field. + GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + GPIO_PIN_WAKEUP_ENABLE = 0x400 + // Position of CONFIG field. + GPIO_PIN_CONFIG_Pos = 0xb + // Bit mask of CONFIG field. + GPIO_PIN_CONFIG_Msk = 0x1800 + // Position of INT_ENA field. + GPIO_PIN_INT_ENA_Pos = 0xd + // Bit mask of INT_ENA field. + GPIO_PIN_INT_ENA_Msk = 0x3e000 + + // STATUS_NEXT: GPIO interrupt source register for GPIO0-31 + // Position of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Pos = 0x0 + // Bit mask of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Msk = 0xffffffff + + // FUNC0_IN_SEL_CFG: GPIO input function configuration register + // Position of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Pos = 0x0 + // Bit mask of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Msk = 0x3f + // Position of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Pos = 0x6 + // Bit mask of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Msk = 0x40 + // Bit IN_INV_SEL. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL = 0x40 + // Position of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Pos = 0x7 + // Bit mask of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Msk = 0x80 + // Bit SEL. + GPIO_FUNC_IN_SEL_CFG_SEL = 0x80 + + // FUNC0_OUT_SEL_CFG: GPIO output function select register + // Position of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Pos = 0x0 + // Bit mask of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Msk = 0xff + // Position of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Pos = 0x8 + // Bit mask of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Msk = 0x100 + // Bit INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL = 0x100 + // Position of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Pos = 0x9 + // Bit mask of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Msk = 0x200 + // Bit OEN_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL = 0x200 + // Position of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Pos = 0xa + // Bit mask of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Msk = 0x400 + // Bit OEN_INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL = 0x400 + + // CLOCK_GATE: GPIO clock gate register + // Position of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + GPIO_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: GPIO version register + // Position of DATE field. + GPIO_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + GPIO_DATE_DATE_Msk = 0xfffffff +) + +// Constants for GPIO_SD: Sigma-Delta Modulation +const ( + // SIGMADELTA0: Duty Cycle Configure Register of SDM%s + // Position of SD_IN field. + GPIOSD_SIGMADELTA_SD_IN_Pos = 0x0 + // Bit mask of SD_IN field. + GPIOSD_SIGMADELTA_SD_IN_Msk = 0xff + // Position of SD_PRESCALE field. + GPIOSD_SIGMADELTA_SD_PRESCALE_Pos = 0x8 + // Bit mask of SD_PRESCALE field. + GPIOSD_SIGMADELTA_SD_PRESCALE_Msk = 0xff00 + + // CLOCK_GATE: Clock Gating Configure Register + // Position of CLK_EN field. + GPIOSD_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + GPIOSD_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + GPIOSD_CLOCK_GATE_CLK_EN = 0x1 + + // SIGMADELTA_MISC: MISC Register + // Position of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Pos = 0x1e + // Bit mask of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Msk = 0x40000000 + // Bit FUNCTION_CLK_EN. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN = 0x40000000 + // Position of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Pos = 0x1f + // Bit mask of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Msk = 0x80000000 + // Bit SPI_SWAP. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP = 0x80000000 + + // PAD_COMP_CONFIG: PAD Compare configure Register + // Position of XPD_COMP field. + GPIOSD_PAD_COMP_CONFIG_XPD_COMP_Pos = 0x0 + // Bit mask of XPD_COMP field. + GPIOSD_PAD_COMP_CONFIG_XPD_COMP_Msk = 0x1 + // Bit XPD_COMP. + GPIOSD_PAD_COMP_CONFIG_XPD_COMP = 0x1 + // Position of MODE_COMP field. + GPIOSD_PAD_COMP_CONFIG_MODE_COMP_Pos = 0x1 + // Bit mask of MODE_COMP field. + GPIOSD_PAD_COMP_CONFIG_MODE_COMP_Msk = 0x2 + // Bit MODE_COMP. + GPIOSD_PAD_COMP_CONFIG_MODE_COMP = 0x2 + // Position of DREF_COMP field. + GPIOSD_PAD_COMP_CONFIG_DREF_COMP_Pos = 0x2 + // Bit mask of DREF_COMP field. + GPIOSD_PAD_COMP_CONFIG_DREF_COMP_Msk = 0x1c + // Position of ZERO_DET_MODE field. + GPIOSD_PAD_COMP_CONFIG_ZERO_DET_MODE_Pos = 0x5 + // Bit mask of ZERO_DET_MODE field. + GPIOSD_PAD_COMP_CONFIG_ZERO_DET_MODE_Msk = 0x60 + + // PAD_COMP_FILTER: Zero Detect filter Register + // Position of ZERO_DET_FILTER_CNT field. + GPIOSD_PAD_COMP_FILTER_ZERO_DET_FILTER_CNT_Pos = 0x0 + // Bit mask of ZERO_DET_FILTER_CNT field. + GPIOSD_PAD_COMP_FILTER_ZERO_DET_FILTER_CNT_Msk = 0xffffffff + + // GLITCH_FILTER_CH0: Glitch Filter Configure Register of Channel%s + // Position of FILTER_CH0_EN field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_EN_Pos = 0x0 + // Bit mask of FILTER_CH0_EN field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_EN_Msk = 0x1 + // Bit FILTER_CH0_EN. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_EN = 0x1 + // Position of FILTER_CH0_INPUT_IO_NUM field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_INPUT_IO_NUM_Pos = 0x1 + // Bit mask of FILTER_CH0_INPUT_IO_NUM field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_INPUT_IO_NUM_Msk = 0x7e + // Position of FILTER_CH0_WINDOW_THRES field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_THRES_Pos = 0x7 + // Bit mask of FILTER_CH0_WINDOW_THRES field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_THRES_Msk = 0x1f80 + // Position of FILTER_CH0_WINDOW_WIDTH field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_WIDTH_Pos = 0xd + // Bit mask of FILTER_CH0_WINDOW_WIDTH field. + GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_WIDTH_Msk = 0x7e000 + + // ETM_EVENT_CH0_CFG: Etm Config register of Channel%s + // Position of ETM_CH0_EVENT_SEL field. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_SEL_Pos = 0x0 + // Bit mask of ETM_CH0_EVENT_SEL field. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_SEL_Msk = 0x1f + // Position of ETM_CH0_EVENT_EN field. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_EN_Pos = 0x7 + // Bit mask of ETM_CH0_EVENT_EN field. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_EN_Msk = 0x80 + // Bit ETM_CH0_EVENT_EN. + GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_EN = 0x80 + + // ETM_TASK_P0_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO0_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO0_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO0_EN. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN = 0x1 + // Position of ETM_TASK_GPIO0_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO0_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO1_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO1_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO1_EN. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN = 0x100 + // Position of ETM_TASK_GPIO1_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO1_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO2_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO2_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO2_EN. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN = 0x10000 + // Position of ETM_TASK_GPIO2_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO2_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO3_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO3_EN field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO3_EN. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN = 0x1000000 + // Position of ETM_TASK_GPIO3_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO3_SEL field. + GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL_Msk = 0xe000000 + + // ETM_TASK_P1_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO4_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO4_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO4_EN. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN = 0x1 + // Position of ETM_TASK_GPIO4_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO4_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO5_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO5_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO5_EN. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN = 0x100 + // Position of ETM_TASK_GPIO5_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO5_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO6_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO6_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO6_EN. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN = 0x10000 + // Position of ETM_TASK_GPIO6_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO6_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO7_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO7_EN field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO7_EN. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN = 0x1000000 + // Position of ETM_TASK_GPIO7_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO7_SEL field. + GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL_Msk = 0xe000000 + + // ETM_TASK_P2_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO8_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO8_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO8_EN. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN = 0x1 + // Position of ETM_TASK_GPIO8_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO8_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO9_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO9_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO9_EN. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN = 0x100 + // Position of ETM_TASK_GPIO9_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO9_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO10_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO10_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO10_EN. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN = 0x10000 + // Position of ETM_TASK_GPIO10_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO10_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO11_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO11_EN field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO11_EN. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN = 0x1000000 + // Position of ETM_TASK_GPIO11_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO11_SEL field. + GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL_Msk = 0xe000000 + + // ETM_TASK_P3_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO12_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO12_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO12_EN. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN = 0x1 + // Position of ETM_TASK_GPIO12_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO12_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO13_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO13_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO13_EN. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN = 0x100 + // Position of ETM_TASK_GPIO13_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO13_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO14_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO14_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO14_EN. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN = 0x10000 + // Position of ETM_TASK_GPIO14_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO14_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO15_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO15_EN field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO15_EN. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN = 0x1000000 + // Position of ETM_TASK_GPIO15_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO15_SEL field. + GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL_Msk = 0xe000000 + + // ETM_TASK_P4_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO16_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO16_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO16_EN. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN = 0x1 + // Position of ETM_TASK_GPIO16_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO16_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO17_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO17_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO17_EN. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN = 0x100 + // Position of ETM_TASK_GPIO17_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO17_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO18_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO18_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO18_EN. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN = 0x10000 + // Position of ETM_TASK_GPIO18_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO18_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO19_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO19_EN field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO19_EN. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN = 0x1000000 + // Position of ETM_TASK_GPIO19_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO19_SEL field. + GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL_Msk = 0xe000000 + + // ETM_TASK_P5_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO20_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO20_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO20_EN. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN = 0x1 + // Position of ETM_TASK_GPIO20_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO20_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO21_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO21_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO21_EN. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN = 0x100 + // Position of ETM_TASK_GPIO21_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO21_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO22_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO22_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO22_EN. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN = 0x10000 + // Position of ETM_TASK_GPIO22_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO22_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO23_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO23_EN field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO23_EN. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN = 0x1000000 + // Position of ETM_TASK_GPIO23_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO23_SEL field. + GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL_Msk = 0xe000000 + + // ETM_TASK_P6_CFG: Etm Configure Register to decide which GPIO been chosen + // Position of ETM_TASK_GPIO24_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN_Pos = 0x0 + // Bit mask of ETM_TASK_GPIO24_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN_Msk = 0x1 + // Bit ETM_TASK_GPIO24_EN. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN = 0x1 + // Position of ETM_TASK_GPIO24_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL_Pos = 0x1 + // Bit mask of ETM_TASK_GPIO24_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL_Msk = 0xe + // Position of ETM_TASK_GPIO25_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN_Pos = 0x8 + // Bit mask of ETM_TASK_GPIO25_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN_Msk = 0x100 + // Bit ETM_TASK_GPIO25_EN. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN = 0x100 + // Position of ETM_TASK_GPIO25_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL_Pos = 0x9 + // Bit mask of ETM_TASK_GPIO25_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL_Msk = 0xe00 + // Position of ETM_TASK_GPIO26_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN_Pos = 0x10 + // Bit mask of ETM_TASK_GPIO26_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN_Msk = 0x10000 + // Bit ETM_TASK_GPIO26_EN. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN = 0x10000 + // Position of ETM_TASK_GPIO26_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL_Pos = 0x11 + // Bit mask of ETM_TASK_GPIO26_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL_Msk = 0xe0000 + // Position of ETM_TASK_GPIO27_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN_Pos = 0x18 + // Bit mask of ETM_TASK_GPIO27_EN field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN_Msk = 0x1000000 + // Bit ETM_TASK_GPIO27_EN. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN = 0x1000000 + // Position of ETM_TASK_GPIO27_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL_Pos = 0x19 + // Bit mask of ETM_TASK_GPIO27_SEL field. + GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL_Msk = 0xe000000 + + // INT_RAW: GPIOSD interrupt raw register + // Position of PAD_COMP_INT_RAW field. + GPIOSD_INT_RAW_PAD_COMP_INT_RAW_Pos = 0x0 + // Bit mask of PAD_COMP_INT_RAW field. + GPIOSD_INT_RAW_PAD_COMP_INT_RAW_Msk = 0x1 + // Bit PAD_COMP_INT_RAW. + GPIOSD_INT_RAW_PAD_COMP_INT_RAW = 0x1 + + // INT_ST: GPIOSD interrupt masked register + // Position of PAD_COMP_INT_ST field. + GPIOSD_INT_ST_PAD_COMP_INT_ST_Pos = 0x0 + // Bit mask of PAD_COMP_INT_ST field. + GPIOSD_INT_ST_PAD_COMP_INT_ST_Msk = 0x1 + // Bit PAD_COMP_INT_ST. + GPIOSD_INT_ST_PAD_COMP_INT_ST = 0x1 + + // INT_ENA: GPIOSD interrupt enable register + // Position of PAD_COMP_INT_ENA field. + GPIOSD_INT_ENA_PAD_COMP_INT_ENA_Pos = 0x0 + // Bit mask of PAD_COMP_INT_ENA field. + GPIOSD_INT_ENA_PAD_COMP_INT_ENA_Msk = 0x1 + // Bit PAD_COMP_INT_ENA. + GPIOSD_INT_ENA_PAD_COMP_INT_ENA = 0x1 + + // INT_CLR: GPIOSD interrupt clear register + // Position of PAD_COMP_INT_CLR field. + GPIOSD_INT_CLR_PAD_COMP_INT_CLR_Pos = 0x0 + // Bit mask of PAD_COMP_INT_CLR field. + GPIOSD_INT_CLR_PAD_COMP_INT_CLR_Msk = 0x1 + // Bit PAD_COMP_INT_CLR. + GPIOSD_INT_CLR_PAD_COMP_INT_CLR = 0x1 + + // VERSION: Version Control Register + // Position of GPIO_SD_DATE field. + GPIOSD_VERSION_GPIO_SD_DATE_Pos = 0x0 + // Bit mask of GPIO_SD_DATE field. + GPIOSD_VERSION_GPIO_SD_DATE_Msk = 0xfffffff +) + +// Constants for HMAC: HMAC (Hash-based Message Authentication Code) Accelerator +const ( + // SET_START: Process control register 0. + // Position of SET_START field. + HMAC_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + HMAC_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + HMAC_SET_START_SET_START = 0x1 + + // SET_PARA_PURPOSE: Configure purpose. + // Position of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Pos = 0x0 + // Bit mask of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Msk = 0xf + + // SET_PARA_KEY: Configure key. + // Position of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Pos = 0x0 + // Bit mask of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Msk = 0x7 + + // SET_PARA_FINISH: Finish initial configuration. + // Position of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Pos = 0x0 + // Bit mask of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Msk = 0x1 + // Bit SET_PARA_END. + HMAC_SET_PARA_FINISH_SET_PARA_END = 0x1 + + // SET_MESSAGE_ONE: Process control register 1. + // Position of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Pos = 0x0 + // Bit mask of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Msk = 0x1 + // Bit SET_TEXT_ONE. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE = 0x1 + + // SET_MESSAGE_ING: Process control register 2. + // Position of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Pos = 0x0 + // Bit mask of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Msk = 0x1 + // Bit SET_TEXT_ING. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING = 0x1 + + // SET_MESSAGE_END: Process control register 3. + // Position of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Pos = 0x0 + // Bit mask of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Msk = 0x1 + // Bit SET_TEXT_END. + HMAC_SET_MESSAGE_END_SET_TEXT_END = 0x1 + + // SET_RESULT_FINISH: Process control register 4. + // Position of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Pos = 0x0 + // Bit mask of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Msk = 0x1 + // Bit SET_RESULT_END. + HMAC_SET_RESULT_FINISH_SET_RESULT_END = 0x1 + + // SET_INVALIDATE_JTAG: Invalidate register 0. + // Position of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Pos = 0x0 + // Bit mask of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Msk = 0x1 + // Bit SET_INVALIDATE_JTAG. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG = 0x1 + + // SET_INVALIDATE_DS: Invalidate register 1. + // Position of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Pos = 0x0 + // Bit mask of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Msk = 0x1 + // Bit SET_INVALIDATE_DS. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS = 0x1 + + // QUERY_ERROR: Error register. + // Position of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Pos = 0x0 + // Bit mask of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Msk = 0x1 + // Bit QUERY_CHECK. + HMAC_QUERY_ERROR_QUERY_CHECK = 0x1 + + // QUERY_BUSY: Busy register. + // Position of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Pos = 0x0 + // Bit mask of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Msk = 0x1 + // Bit BUSY_STATE. + HMAC_QUERY_BUSY_BUSY_STATE = 0x1 + + // SET_MESSAGE_PAD: Process control register 5. + // Position of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Pos = 0x0 + // Bit mask of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Msk = 0x1 + // Bit SET_TEXT_PAD. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD = 0x1 + + // ONE_BLOCK: Process control register 6. + // Position of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Pos = 0x0 + // Bit mask of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Msk = 0x1 + // Bit SET_ONE_BLOCK. + HMAC_ONE_BLOCK_SET_ONE_BLOCK = 0x1 + + // SOFT_JTAG_CTRL: Jtag register 0. + // Position of SOFT_JTAG_CTRL field. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Pos = 0x0 + // Bit mask of SOFT_JTAG_CTRL field. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Msk = 0x1 + // Bit SOFT_JTAG_CTRL. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL = 0x1 + + // WR_JTAG: Jtag register 1. + // Position of WR_JTAG field. + HMAC_WR_JTAG_WR_JTAG_Pos = 0x0 + // Bit mask of WR_JTAG field. + HMAC_WR_JTAG_WR_JTAG_Msk = 0xffffffff + + // DATE: Date register. + // Position of DATE field. + HMAC_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + HMAC_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for HP_APM: HP_APM Peripheral +const ( + // REGION_FILTER_EN: Region filter enable register + // Position of REGION_FILTER_EN field. + HP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Pos = 0x0 + // Bit mask of REGION_FILTER_EN field. + HP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Msk = 0xffff + + // REGION0_ADDR_START: Region address register + // Position of REGION0_ADDR_START field. + HP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Pos = 0x0 + // Bit mask of REGION0_ADDR_START field. + HP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Msk = 0xffffffff + + // REGION0_ADDR_END: Region address register + // Position of REGION0_ADDR_END field. + HP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Pos = 0x0 + // Bit mask of REGION0_ADDR_END field. + HP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Msk = 0xffffffff + + // REGION0_PMS_ATTR: Region access authority attribute register + // Position of REGION0_R0_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION0_R0_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Msk = 0x1 + // Bit REGION0_R0_PMS_X. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X = 0x1 + // Position of REGION0_R0_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION0_R0_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Msk = 0x2 + // Bit REGION0_R0_PMS_W. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W = 0x2 + // Position of REGION0_R0_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION0_R0_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Msk = 0x4 + // Bit REGION0_R0_PMS_R. + HP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R = 0x4 + // Position of REGION0_R1_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION0_R1_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Msk = 0x10 + // Bit REGION0_R1_PMS_X. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X = 0x10 + // Position of REGION0_R1_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION0_R1_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Msk = 0x20 + // Bit REGION0_R1_PMS_W. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W = 0x20 + // Position of REGION0_R1_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION0_R1_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Msk = 0x40 + // Bit REGION0_R1_PMS_R. + HP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R = 0x40 + // Position of REGION0_R2_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION0_R2_PMS_X field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Msk = 0x100 + // Bit REGION0_R2_PMS_X. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X = 0x100 + // Position of REGION0_R2_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION0_R2_PMS_W field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Msk = 0x200 + // Bit REGION0_R2_PMS_W. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W = 0x200 + // Position of REGION0_R2_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Pos = 0xa + // Bit mask of REGION0_R2_PMS_R field. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Msk = 0x400 + // Bit REGION0_R2_PMS_R. + HP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R = 0x400 + + // REGION1_ADDR_START: Region address register + // Position of REGION1_ADDR_START field. + HP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Pos = 0x0 + // Bit mask of REGION1_ADDR_START field. + HP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Msk = 0xffffffff + + // REGION1_ADDR_END: Region address register + // Position of REGION1_ADDR_END field. + HP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Pos = 0x0 + // Bit mask of REGION1_ADDR_END field. + HP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Msk = 0xffffffff + + // REGION1_PMS_ATTR: Region access authority attribute register + // Position of REGION1_R0_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION1_R0_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Msk = 0x1 + // Bit REGION1_R0_PMS_X. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X = 0x1 + // Position of REGION1_R0_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION1_R0_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Msk = 0x2 + // Bit REGION1_R0_PMS_W. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W = 0x2 + // Position of REGION1_R0_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION1_R0_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Msk = 0x4 + // Bit REGION1_R0_PMS_R. + HP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R = 0x4 + // Position of REGION1_R1_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION1_R1_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Msk = 0x10 + // Bit REGION1_R1_PMS_X. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X = 0x10 + // Position of REGION1_R1_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION1_R1_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Msk = 0x20 + // Bit REGION1_R1_PMS_W. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W = 0x20 + // Position of REGION1_R1_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION1_R1_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Msk = 0x40 + // Bit REGION1_R1_PMS_R. + HP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R = 0x40 + // Position of REGION1_R2_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION1_R2_PMS_X field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Msk = 0x100 + // Bit REGION1_R2_PMS_X. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X = 0x100 + // Position of REGION1_R2_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION1_R2_PMS_W field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Msk = 0x200 + // Bit REGION1_R2_PMS_W. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W = 0x200 + // Position of REGION1_R2_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Pos = 0xa + // Bit mask of REGION1_R2_PMS_R field. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Msk = 0x400 + // Bit REGION1_R2_PMS_R. + HP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R = 0x400 + + // REGION2_ADDR_START: Region address register + // Position of REGION2_ADDR_START field. + HP_APM_REGION2_ADDR_START_REGION2_ADDR_START_Pos = 0x0 + // Bit mask of REGION2_ADDR_START field. + HP_APM_REGION2_ADDR_START_REGION2_ADDR_START_Msk = 0xffffffff + + // REGION2_ADDR_END: Region address register + // Position of REGION2_ADDR_END field. + HP_APM_REGION2_ADDR_END_REGION2_ADDR_END_Pos = 0x0 + // Bit mask of REGION2_ADDR_END field. + HP_APM_REGION2_ADDR_END_REGION2_ADDR_END_Msk = 0xffffffff + + // REGION2_PMS_ATTR: Region access authority attribute register + // Position of REGION2_R0_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION2_R0_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X_Msk = 0x1 + // Bit REGION2_R0_PMS_X. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_X = 0x1 + // Position of REGION2_R0_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION2_R0_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W_Msk = 0x2 + // Bit REGION2_R0_PMS_W. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_W = 0x2 + // Position of REGION2_R0_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION2_R0_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R_Msk = 0x4 + // Bit REGION2_R0_PMS_R. + HP_APM_REGION2_PMS_ATTR_REGION2_R0_PMS_R = 0x4 + // Position of REGION2_R1_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION2_R1_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X_Msk = 0x10 + // Bit REGION2_R1_PMS_X. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_X = 0x10 + // Position of REGION2_R1_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION2_R1_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W_Msk = 0x20 + // Bit REGION2_R1_PMS_W. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_W = 0x20 + // Position of REGION2_R1_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION2_R1_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R_Msk = 0x40 + // Bit REGION2_R1_PMS_R. + HP_APM_REGION2_PMS_ATTR_REGION2_R1_PMS_R = 0x40 + // Position of REGION2_R2_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION2_R2_PMS_X field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X_Msk = 0x100 + // Bit REGION2_R2_PMS_X. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_X = 0x100 + // Position of REGION2_R2_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION2_R2_PMS_W field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W_Msk = 0x200 + // Bit REGION2_R2_PMS_W. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_W = 0x200 + // Position of REGION2_R2_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Pos = 0xa + // Bit mask of REGION2_R2_PMS_R field. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R_Msk = 0x400 + // Bit REGION2_R2_PMS_R. + HP_APM_REGION2_PMS_ATTR_REGION2_R2_PMS_R = 0x400 + + // REGION3_ADDR_START: Region address register + // Position of REGION3_ADDR_START field. + HP_APM_REGION3_ADDR_START_REGION3_ADDR_START_Pos = 0x0 + // Bit mask of REGION3_ADDR_START field. + HP_APM_REGION3_ADDR_START_REGION3_ADDR_START_Msk = 0xffffffff + + // REGION3_ADDR_END: Region address register + // Position of REGION3_ADDR_END field. + HP_APM_REGION3_ADDR_END_REGION3_ADDR_END_Pos = 0x0 + // Bit mask of REGION3_ADDR_END field. + HP_APM_REGION3_ADDR_END_REGION3_ADDR_END_Msk = 0xffffffff + + // REGION3_PMS_ATTR: Region access authority attribute register + // Position of REGION3_R0_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION3_R0_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X_Msk = 0x1 + // Bit REGION3_R0_PMS_X. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_X = 0x1 + // Position of REGION3_R0_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION3_R0_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W_Msk = 0x2 + // Bit REGION3_R0_PMS_W. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_W = 0x2 + // Position of REGION3_R0_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION3_R0_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R_Msk = 0x4 + // Bit REGION3_R0_PMS_R. + HP_APM_REGION3_PMS_ATTR_REGION3_R0_PMS_R = 0x4 + // Position of REGION3_R1_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION3_R1_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X_Msk = 0x10 + // Bit REGION3_R1_PMS_X. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_X = 0x10 + // Position of REGION3_R1_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION3_R1_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W_Msk = 0x20 + // Bit REGION3_R1_PMS_W. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_W = 0x20 + // Position of REGION3_R1_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION3_R1_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R_Msk = 0x40 + // Bit REGION3_R1_PMS_R. + HP_APM_REGION3_PMS_ATTR_REGION3_R1_PMS_R = 0x40 + // Position of REGION3_R2_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION3_R2_PMS_X field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X_Msk = 0x100 + // Bit REGION3_R2_PMS_X. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_X = 0x100 + // Position of REGION3_R2_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION3_R2_PMS_W field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W_Msk = 0x200 + // Bit REGION3_R2_PMS_W. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_W = 0x200 + // Position of REGION3_R2_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Pos = 0xa + // Bit mask of REGION3_R2_PMS_R field. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R_Msk = 0x400 + // Bit REGION3_R2_PMS_R. + HP_APM_REGION3_PMS_ATTR_REGION3_R2_PMS_R = 0x400 + + // REGION4_ADDR_START: Region address register + // Position of REGION4_ADDR_START field. + HP_APM_REGION4_ADDR_START_REGION4_ADDR_START_Pos = 0x0 + // Bit mask of REGION4_ADDR_START field. + HP_APM_REGION4_ADDR_START_REGION4_ADDR_START_Msk = 0xffffffff + + // REGION4_ADDR_END: Region address register + // Position of REGION4_ADDR_END field. + HP_APM_REGION4_ADDR_END_REGION4_ADDR_END_Pos = 0x0 + // Bit mask of REGION4_ADDR_END field. + HP_APM_REGION4_ADDR_END_REGION4_ADDR_END_Msk = 0xffffffff + + // REGION4_PMS_ATTR: Region access authority attribute register + // Position of REGION4_R0_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION4_R0_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_X_Msk = 0x1 + // Bit REGION4_R0_PMS_X. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_X = 0x1 + // Position of REGION4_R0_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION4_R0_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_W_Msk = 0x2 + // Bit REGION4_R0_PMS_W. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_W = 0x2 + // Position of REGION4_R0_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION4_R0_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_R_Msk = 0x4 + // Bit REGION4_R0_PMS_R. + HP_APM_REGION4_PMS_ATTR_REGION4_R0_PMS_R = 0x4 + // Position of REGION4_R1_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION4_R1_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_X_Msk = 0x10 + // Bit REGION4_R1_PMS_X. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_X = 0x10 + // Position of REGION4_R1_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION4_R1_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_W_Msk = 0x20 + // Bit REGION4_R1_PMS_W. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_W = 0x20 + // Position of REGION4_R1_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION4_R1_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_R_Msk = 0x40 + // Bit REGION4_R1_PMS_R. + HP_APM_REGION4_PMS_ATTR_REGION4_R1_PMS_R = 0x40 + // Position of REGION4_R2_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION4_R2_PMS_X field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_X_Msk = 0x100 + // Bit REGION4_R2_PMS_X. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_X = 0x100 + // Position of REGION4_R2_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION4_R2_PMS_W field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_W_Msk = 0x200 + // Bit REGION4_R2_PMS_W. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_W = 0x200 + // Position of REGION4_R2_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_R_Pos = 0xa + // Bit mask of REGION4_R2_PMS_R field. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_R_Msk = 0x400 + // Bit REGION4_R2_PMS_R. + HP_APM_REGION4_PMS_ATTR_REGION4_R2_PMS_R = 0x400 + + // REGION5_ADDR_START: Region address register + // Position of REGION5_ADDR_START field. + HP_APM_REGION5_ADDR_START_REGION5_ADDR_START_Pos = 0x0 + // Bit mask of REGION5_ADDR_START field. + HP_APM_REGION5_ADDR_START_REGION5_ADDR_START_Msk = 0xffffffff + + // REGION5_ADDR_END: Region address register + // Position of REGION5_ADDR_END field. + HP_APM_REGION5_ADDR_END_REGION5_ADDR_END_Pos = 0x0 + // Bit mask of REGION5_ADDR_END field. + HP_APM_REGION5_ADDR_END_REGION5_ADDR_END_Msk = 0xffffffff + + // REGION5_PMS_ATTR: Region access authority attribute register + // Position of REGION5_R0_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION5_R0_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_X_Msk = 0x1 + // Bit REGION5_R0_PMS_X. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_X = 0x1 + // Position of REGION5_R0_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION5_R0_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_W_Msk = 0x2 + // Bit REGION5_R0_PMS_W. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_W = 0x2 + // Position of REGION5_R0_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION5_R0_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_R_Msk = 0x4 + // Bit REGION5_R0_PMS_R. + HP_APM_REGION5_PMS_ATTR_REGION5_R0_PMS_R = 0x4 + // Position of REGION5_R1_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION5_R1_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_X_Msk = 0x10 + // Bit REGION5_R1_PMS_X. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_X = 0x10 + // Position of REGION5_R1_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION5_R1_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_W_Msk = 0x20 + // Bit REGION5_R1_PMS_W. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_W = 0x20 + // Position of REGION5_R1_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION5_R1_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_R_Msk = 0x40 + // Bit REGION5_R1_PMS_R. + HP_APM_REGION5_PMS_ATTR_REGION5_R1_PMS_R = 0x40 + // Position of REGION5_R2_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION5_R2_PMS_X field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_X_Msk = 0x100 + // Bit REGION5_R2_PMS_X. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_X = 0x100 + // Position of REGION5_R2_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION5_R2_PMS_W field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_W_Msk = 0x200 + // Bit REGION5_R2_PMS_W. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_W = 0x200 + // Position of REGION5_R2_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_R_Pos = 0xa + // Bit mask of REGION5_R2_PMS_R field. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_R_Msk = 0x400 + // Bit REGION5_R2_PMS_R. + HP_APM_REGION5_PMS_ATTR_REGION5_R2_PMS_R = 0x400 + + // REGION6_ADDR_START: Region address register + // Position of REGION6_ADDR_START field. + HP_APM_REGION6_ADDR_START_REGION6_ADDR_START_Pos = 0x0 + // Bit mask of REGION6_ADDR_START field. + HP_APM_REGION6_ADDR_START_REGION6_ADDR_START_Msk = 0xffffffff + + // REGION6_ADDR_END: Region address register + // Position of REGION6_ADDR_END field. + HP_APM_REGION6_ADDR_END_REGION6_ADDR_END_Pos = 0x0 + // Bit mask of REGION6_ADDR_END field. + HP_APM_REGION6_ADDR_END_REGION6_ADDR_END_Msk = 0xffffffff + + // REGION6_PMS_ATTR: Region access authority attribute register + // Position of REGION6_R0_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION6_R0_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_X_Msk = 0x1 + // Bit REGION6_R0_PMS_X. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_X = 0x1 + // Position of REGION6_R0_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION6_R0_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_W_Msk = 0x2 + // Bit REGION6_R0_PMS_W. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_W = 0x2 + // Position of REGION6_R0_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION6_R0_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_R_Msk = 0x4 + // Bit REGION6_R0_PMS_R. + HP_APM_REGION6_PMS_ATTR_REGION6_R0_PMS_R = 0x4 + // Position of REGION6_R1_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION6_R1_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_X_Msk = 0x10 + // Bit REGION6_R1_PMS_X. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_X = 0x10 + // Position of REGION6_R1_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION6_R1_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_W_Msk = 0x20 + // Bit REGION6_R1_PMS_W. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_W = 0x20 + // Position of REGION6_R1_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION6_R1_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_R_Msk = 0x40 + // Bit REGION6_R1_PMS_R. + HP_APM_REGION6_PMS_ATTR_REGION6_R1_PMS_R = 0x40 + // Position of REGION6_R2_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION6_R2_PMS_X field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_X_Msk = 0x100 + // Bit REGION6_R2_PMS_X. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_X = 0x100 + // Position of REGION6_R2_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION6_R2_PMS_W field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_W_Msk = 0x200 + // Bit REGION6_R2_PMS_W. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_W = 0x200 + // Position of REGION6_R2_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_R_Pos = 0xa + // Bit mask of REGION6_R2_PMS_R field. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_R_Msk = 0x400 + // Bit REGION6_R2_PMS_R. + HP_APM_REGION6_PMS_ATTR_REGION6_R2_PMS_R = 0x400 + + // REGION7_ADDR_START: Region address register + // Position of REGION7_ADDR_START field. + HP_APM_REGION7_ADDR_START_REGION7_ADDR_START_Pos = 0x0 + // Bit mask of REGION7_ADDR_START field. + HP_APM_REGION7_ADDR_START_REGION7_ADDR_START_Msk = 0xffffffff + + // REGION7_ADDR_END: Region address register + // Position of REGION7_ADDR_END field. + HP_APM_REGION7_ADDR_END_REGION7_ADDR_END_Pos = 0x0 + // Bit mask of REGION7_ADDR_END field. + HP_APM_REGION7_ADDR_END_REGION7_ADDR_END_Msk = 0xffffffff + + // REGION7_PMS_ATTR: Region access authority attribute register + // Position of REGION7_R0_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION7_R0_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_X_Msk = 0x1 + // Bit REGION7_R0_PMS_X. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_X = 0x1 + // Position of REGION7_R0_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION7_R0_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_W_Msk = 0x2 + // Bit REGION7_R0_PMS_W. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_W = 0x2 + // Position of REGION7_R0_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION7_R0_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_R_Msk = 0x4 + // Bit REGION7_R0_PMS_R. + HP_APM_REGION7_PMS_ATTR_REGION7_R0_PMS_R = 0x4 + // Position of REGION7_R1_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION7_R1_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_X_Msk = 0x10 + // Bit REGION7_R1_PMS_X. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_X = 0x10 + // Position of REGION7_R1_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION7_R1_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_W_Msk = 0x20 + // Bit REGION7_R1_PMS_W. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_W = 0x20 + // Position of REGION7_R1_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION7_R1_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_R_Msk = 0x40 + // Bit REGION7_R1_PMS_R. + HP_APM_REGION7_PMS_ATTR_REGION7_R1_PMS_R = 0x40 + // Position of REGION7_R2_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION7_R2_PMS_X field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_X_Msk = 0x100 + // Bit REGION7_R2_PMS_X. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_X = 0x100 + // Position of REGION7_R2_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION7_R2_PMS_W field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_W_Msk = 0x200 + // Bit REGION7_R2_PMS_W. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_W = 0x200 + // Position of REGION7_R2_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_R_Pos = 0xa + // Bit mask of REGION7_R2_PMS_R field. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_R_Msk = 0x400 + // Bit REGION7_R2_PMS_R. + HP_APM_REGION7_PMS_ATTR_REGION7_R2_PMS_R = 0x400 + + // REGION8_ADDR_START: Region address register + // Position of REGION8_ADDR_START field. + HP_APM_REGION8_ADDR_START_REGION8_ADDR_START_Pos = 0x0 + // Bit mask of REGION8_ADDR_START field. + HP_APM_REGION8_ADDR_START_REGION8_ADDR_START_Msk = 0xffffffff + + // REGION8_ADDR_END: Region address register + // Position of REGION8_ADDR_END field. + HP_APM_REGION8_ADDR_END_REGION8_ADDR_END_Pos = 0x0 + // Bit mask of REGION8_ADDR_END field. + HP_APM_REGION8_ADDR_END_REGION8_ADDR_END_Msk = 0xffffffff + + // REGION8_PMS_ATTR: Region access authority attribute register + // Position of REGION8_R0_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION8_R0_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_X_Msk = 0x1 + // Bit REGION8_R0_PMS_X. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_X = 0x1 + // Position of REGION8_R0_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION8_R0_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_W_Msk = 0x2 + // Bit REGION8_R0_PMS_W. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_W = 0x2 + // Position of REGION8_R0_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION8_R0_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_R_Msk = 0x4 + // Bit REGION8_R0_PMS_R. + HP_APM_REGION8_PMS_ATTR_REGION8_R0_PMS_R = 0x4 + // Position of REGION8_R1_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION8_R1_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_X_Msk = 0x10 + // Bit REGION8_R1_PMS_X. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_X = 0x10 + // Position of REGION8_R1_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION8_R1_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_W_Msk = 0x20 + // Bit REGION8_R1_PMS_W. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_W = 0x20 + // Position of REGION8_R1_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION8_R1_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_R_Msk = 0x40 + // Bit REGION8_R1_PMS_R. + HP_APM_REGION8_PMS_ATTR_REGION8_R1_PMS_R = 0x40 + // Position of REGION8_R2_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION8_R2_PMS_X field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_X_Msk = 0x100 + // Bit REGION8_R2_PMS_X. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_X = 0x100 + // Position of REGION8_R2_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION8_R2_PMS_W field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_W_Msk = 0x200 + // Bit REGION8_R2_PMS_W. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_W = 0x200 + // Position of REGION8_R2_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_R_Pos = 0xa + // Bit mask of REGION8_R2_PMS_R field. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_R_Msk = 0x400 + // Bit REGION8_R2_PMS_R. + HP_APM_REGION8_PMS_ATTR_REGION8_R2_PMS_R = 0x400 + + // REGION9_ADDR_START: Region address register + // Position of REGION9_ADDR_START field. + HP_APM_REGION9_ADDR_START_REGION9_ADDR_START_Pos = 0x0 + // Bit mask of REGION9_ADDR_START field. + HP_APM_REGION9_ADDR_START_REGION9_ADDR_START_Msk = 0xffffffff + + // REGION9_ADDR_END: Region address register + // Position of REGION9_ADDR_END field. + HP_APM_REGION9_ADDR_END_REGION9_ADDR_END_Pos = 0x0 + // Bit mask of REGION9_ADDR_END field. + HP_APM_REGION9_ADDR_END_REGION9_ADDR_END_Msk = 0xffffffff + + // REGION9_PMS_ATTR: Region access authority attribute register + // Position of REGION9_R0_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION9_R0_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_X_Msk = 0x1 + // Bit REGION9_R0_PMS_X. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_X = 0x1 + // Position of REGION9_R0_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION9_R0_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_W_Msk = 0x2 + // Bit REGION9_R0_PMS_W. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_W = 0x2 + // Position of REGION9_R0_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION9_R0_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_R_Msk = 0x4 + // Bit REGION9_R0_PMS_R. + HP_APM_REGION9_PMS_ATTR_REGION9_R0_PMS_R = 0x4 + // Position of REGION9_R1_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION9_R1_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_X_Msk = 0x10 + // Bit REGION9_R1_PMS_X. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_X = 0x10 + // Position of REGION9_R1_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION9_R1_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_W_Msk = 0x20 + // Bit REGION9_R1_PMS_W. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_W = 0x20 + // Position of REGION9_R1_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION9_R1_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_R_Msk = 0x40 + // Bit REGION9_R1_PMS_R. + HP_APM_REGION9_PMS_ATTR_REGION9_R1_PMS_R = 0x40 + // Position of REGION9_R2_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION9_R2_PMS_X field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_X_Msk = 0x100 + // Bit REGION9_R2_PMS_X. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_X = 0x100 + // Position of REGION9_R2_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION9_R2_PMS_W field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_W_Msk = 0x200 + // Bit REGION9_R2_PMS_W. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_W = 0x200 + // Position of REGION9_R2_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_R_Pos = 0xa + // Bit mask of REGION9_R2_PMS_R field. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_R_Msk = 0x400 + // Bit REGION9_R2_PMS_R. + HP_APM_REGION9_PMS_ATTR_REGION9_R2_PMS_R = 0x400 + + // REGION10_ADDR_START: Region address register + // Position of REGION10_ADDR_START field. + HP_APM_REGION10_ADDR_START_REGION10_ADDR_START_Pos = 0x0 + // Bit mask of REGION10_ADDR_START field. + HP_APM_REGION10_ADDR_START_REGION10_ADDR_START_Msk = 0xffffffff + + // REGION10_ADDR_END: Region address register + // Position of REGION10_ADDR_END field. + HP_APM_REGION10_ADDR_END_REGION10_ADDR_END_Pos = 0x0 + // Bit mask of REGION10_ADDR_END field. + HP_APM_REGION10_ADDR_END_REGION10_ADDR_END_Msk = 0xffffffff + + // REGION10_PMS_ATTR: Region access authority attribute register + // Position of REGION10_R0_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION10_R0_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_X_Msk = 0x1 + // Bit REGION10_R0_PMS_X. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_X = 0x1 + // Position of REGION10_R0_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION10_R0_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_W_Msk = 0x2 + // Bit REGION10_R0_PMS_W. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_W = 0x2 + // Position of REGION10_R0_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION10_R0_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_R_Msk = 0x4 + // Bit REGION10_R0_PMS_R. + HP_APM_REGION10_PMS_ATTR_REGION10_R0_PMS_R = 0x4 + // Position of REGION10_R1_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION10_R1_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_X_Msk = 0x10 + // Bit REGION10_R1_PMS_X. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_X = 0x10 + // Position of REGION10_R1_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION10_R1_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_W_Msk = 0x20 + // Bit REGION10_R1_PMS_W. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_W = 0x20 + // Position of REGION10_R1_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION10_R1_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_R_Msk = 0x40 + // Bit REGION10_R1_PMS_R. + HP_APM_REGION10_PMS_ATTR_REGION10_R1_PMS_R = 0x40 + // Position of REGION10_R2_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION10_R2_PMS_X field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_X_Msk = 0x100 + // Bit REGION10_R2_PMS_X. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_X = 0x100 + // Position of REGION10_R2_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION10_R2_PMS_W field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_W_Msk = 0x200 + // Bit REGION10_R2_PMS_W. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_W = 0x200 + // Position of REGION10_R2_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_R_Pos = 0xa + // Bit mask of REGION10_R2_PMS_R field. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_R_Msk = 0x400 + // Bit REGION10_R2_PMS_R. + HP_APM_REGION10_PMS_ATTR_REGION10_R2_PMS_R = 0x400 + + // REGION11_ADDR_START: Region address register + // Position of REGION11_ADDR_START field. + HP_APM_REGION11_ADDR_START_REGION11_ADDR_START_Pos = 0x0 + // Bit mask of REGION11_ADDR_START field. + HP_APM_REGION11_ADDR_START_REGION11_ADDR_START_Msk = 0xffffffff + + // REGION11_ADDR_END: Region address register + // Position of REGION11_ADDR_END field. + HP_APM_REGION11_ADDR_END_REGION11_ADDR_END_Pos = 0x0 + // Bit mask of REGION11_ADDR_END field. + HP_APM_REGION11_ADDR_END_REGION11_ADDR_END_Msk = 0xffffffff + + // REGION11_PMS_ATTR: Region access authority attribute register + // Position of REGION11_R0_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION11_R0_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_X_Msk = 0x1 + // Bit REGION11_R0_PMS_X. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_X = 0x1 + // Position of REGION11_R0_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION11_R0_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_W_Msk = 0x2 + // Bit REGION11_R0_PMS_W. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_W = 0x2 + // Position of REGION11_R0_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION11_R0_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_R_Msk = 0x4 + // Bit REGION11_R0_PMS_R. + HP_APM_REGION11_PMS_ATTR_REGION11_R0_PMS_R = 0x4 + // Position of REGION11_R1_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION11_R1_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_X_Msk = 0x10 + // Bit REGION11_R1_PMS_X. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_X = 0x10 + // Position of REGION11_R1_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION11_R1_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_W_Msk = 0x20 + // Bit REGION11_R1_PMS_W. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_W = 0x20 + // Position of REGION11_R1_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION11_R1_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_R_Msk = 0x40 + // Bit REGION11_R1_PMS_R. + HP_APM_REGION11_PMS_ATTR_REGION11_R1_PMS_R = 0x40 + // Position of REGION11_R2_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION11_R2_PMS_X field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_X_Msk = 0x100 + // Bit REGION11_R2_PMS_X. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_X = 0x100 + // Position of REGION11_R2_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION11_R2_PMS_W field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_W_Msk = 0x200 + // Bit REGION11_R2_PMS_W. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_W = 0x200 + // Position of REGION11_R2_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_R_Pos = 0xa + // Bit mask of REGION11_R2_PMS_R field. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_R_Msk = 0x400 + // Bit REGION11_R2_PMS_R. + HP_APM_REGION11_PMS_ATTR_REGION11_R2_PMS_R = 0x400 + + // REGION12_ADDR_START: Region address register + // Position of REGION12_ADDR_START field. + HP_APM_REGION12_ADDR_START_REGION12_ADDR_START_Pos = 0x0 + // Bit mask of REGION12_ADDR_START field. + HP_APM_REGION12_ADDR_START_REGION12_ADDR_START_Msk = 0xffffffff + + // REGION12_ADDR_END: Region address register + // Position of REGION12_ADDR_END field. + HP_APM_REGION12_ADDR_END_REGION12_ADDR_END_Pos = 0x0 + // Bit mask of REGION12_ADDR_END field. + HP_APM_REGION12_ADDR_END_REGION12_ADDR_END_Msk = 0xffffffff + + // REGION12_PMS_ATTR: Region access authority attribute register + // Position of REGION12_R0_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION12_R0_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_X_Msk = 0x1 + // Bit REGION12_R0_PMS_X. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_X = 0x1 + // Position of REGION12_R0_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION12_R0_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_W_Msk = 0x2 + // Bit REGION12_R0_PMS_W. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_W = 0x2 + // Position of REGION12_R0_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION12_R0_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_R_Msk = 0x4 + // Bit REGION12_R0_PMS_R. + HP_APM_REGION12_PMS_ATTR_REGION12_R0_PMS_R = 0x4 + // Position of REGION12_R1_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION12_R1_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_X_Msk = 0x10 + // Bit REGION12_R1_PMS_X. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_X = 0x10 + // Position of REGION12_R1_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION12_R1_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_W_Msk = 0x20 + // Bit REGION12_R1_PMS_W. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_W = 0x20 + // Position of REGION12_R1_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION12_R1_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_R_Msk = 0x40 + // Bit REGION12_R1_PMS_R. + HP_APM_REGION12_PMS_ATTR_REGION12_R1_PMS_R = 0x40 + // Position of REGION12_R2_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION12_R2_PMS_X field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_X_Msk = 0x100 + // Bit REGION12_R2_PMS_X. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_X = 0x100 + // Position of REGION12_R2_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION12_R2_PMS_W field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_W_Msk = 0x200 + // Bit REGION12_R2_PMS_W. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_W = 0x200 + // Position of REGION12_R2_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_R_Pos = 0xa + // Bit mask of REGION12_R2_PMS_R field. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_R_Msk = 0x400 + // Bit REGION12_R2_PMS_R. + HP_APM_REGION12_PMS_ATTR_REGION12_R2_PMS_R = 0x400 + + // REGION13_ADDR_START: Region address register + // Position of REGION13_ADDR_START field. + HP_APM_REGION13_ADDR_START_REGION13_ADDR_START_Pos = 0x0 + // Bit mask of REGION13_ADDR_START field. + HP_APM_REGION13_ADDR_START_REGION13_ADDR_START_Msk = 0xffffffff + + // REGION13_ADDR_END: Region address register + // Position of REGION13_ADDR_END field. + HP_APM_REGION13_ADDR_END_REGION13_ADDR_END_Pos = 0x0 + // Bit mask of REGION13_ADDR_END field. + HP_APM_REGION13_ADDR_END_REGION13_ADDR_END_Msk = 0xffffffff + + // REGION13_PMS_ATTR: Region access authority attribute register + // Position of REGION13_R0_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION13_R0_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_X_Msk = 0x1 + // Bit REGION13_R0_PMS_X. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_X = 0x1 + // Position of REGION13_R0_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION13_R0_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_W_Msk = 0x2 + // Bit REGION13_R0_PMS_W. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_W = 0x2 + // Position of REGION13_R0_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION13_R0_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_R_Msk = 0x4 + // Bit REGION13_R0_PMS_R. + HP_APM_REGION13_PMS_ATTR_REGION13_R0_PMS_R = 0x4 + // Position of REGION13_R1_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION13_R1_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_X_Msk = 0x10 + // Bit REGION13_R1_PMS_X. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_X = 0x10 + // Position of REGION13_R1_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION13_R1_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_W_Msk = 0x20 + // Bit REGION13_R1_PMS_W. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_W = 0x20 + // Position of REGION13_R1_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION13_R1_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_R_Msk = 0x40 + // Bit REGION13_R1_PMS_R. + HP_APM_REGION13_PMS_ATTR_REGION13_R1_PMS_R = 0x40 + // Position of REGION13_R2_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION13_R2_PMS_X field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_X_Msk = 0x100 + // Bit REGION13_R2_PMS_X. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_X = 0x100 + // Position of REGION13_R2_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION13_R2_PMS_W field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_W_Msk = 0x200 + // Bit REGION13_R2_PMS_W. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_W = 0x200 + // Position of REGION13_R2_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_R_Pos = 0xa + // Bit mask of REGION13_R2_PMS_R field. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_R_Msk = 0x400 + // Bit REGION13_R2_PMS_R. + HP_APM_REGION13_PMS_ATTR_REGION13_R2_PMS_R = 0x400 + + // REGION14_ADDR_START: Region address register + // Position of REGION14_ADDR_START field. + HP_APM_REGION14_ADDR_START_REGION14_ADDR_START_Pos = 0x0 + // Bit mask of REGION14_ADDR_START field. + HP_APM_REGION14_ADDR_START_REGION14_ADDR_START_Msk = 0xffffffff + + // REGION14_ADDR_END: Region address register + // Position of REGION14_ADDR_END field. + HP_APM_REGION14_ADDR_END_REGION14_ADDR_END_Pos = 0x0 + // Bit mask of REGION14_ADDR_END field. + HP_APM_REGION14_ADDR_END_REGION14_ADDR_END_Msk = 0xffffffff + + // REGION14_PMS_ATTR: Region access authority attribute register + // Position of REGION14_R0_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION14_R0_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_X_Msk = 0x1 + // Bit REGION14_R0_PMS_X. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_X = 0x1 + // Position of REGION14_R0_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION14_R0_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_W_Msk = 0x2 + // Bit REGION14_R0_PMS_W. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_W = 0x2 + // Position of REGION14_R0_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION14_R0_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_R_Msk = 0x4 + // Bit REGION14_R0_PMS_R. + HP_APM_REGION14_PMS_ATTR_REGION14_R0_PMS_R = 0x4 + // Position of REGION14_R1_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION14_R1_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_X_Msk = 0x10 + // Bit REGION14_R1_PMS_X. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_X = 0x10 + // Position of REGION14_R1_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION14_R1_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_W_Msk = 0x20 + // Bit REGION14_R1_PMS_W. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_W = 0x20 + // Position of REGION14_R1_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION14_R1_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_R_Msk = 0x40 + // Bit REGION14_R1_PMS_R. + HP_APM_REGION14_PMS_ATTR_REGION14_R1_PMS_R = 0x40 + // Position of REGION14_R2_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION14_R2_PMS_X field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_X_Msk = 0x100 + // Bit REGION14_R2_PMS_X. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_X = 0x100 + // Position of REGION14_R2_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION14_R2_PMS_W field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_W_Msk = 0x200 + // Bit REGION14_R2_PMS_W. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_W = 0x200 + // Position of REGION14_R2_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_R_Pos = 0xa + // Bit mask of REGION14_R2_PMS_R field. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_R_Msk = 0x400 + // Bit REGION14_R2_PMS_R. + HP_APM_REGION14_PMS_ATTR_REGION14_R2_PMS_R = 0x400 + + // REGION15_ADDR_START: Region address register + // Position of REGION15_ADDR_START field. + HP_APM_REGION15_ADDR_START_REGION15_ADDR_START_Pos = 0x0 + // Bit mask of REGION15_ADDR_START field. + HP_APM_REGION15_ADDR_START_REGION15_ADDR_START_Msk = 0xffffffff + + // REGION15_ADDR_END: Region address register + // Position of REGION15_ADDR_END field. + HP_APM_REGION15_ADDR_END_REGION15_ADDR_END_Pos = 0x0 + // Bit mask of REGION15_ADDR_END field. + HP_APM_REGION15_ADDR_END_REGION15_ADDR_END_Msk = 0xffffffff + + // REGION15_PMS_ATTR: Region access authority attribute register + // Position of REGION15_R0_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION15_R0_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_X_Msk = 0x1 + // Bit REGION15_R0_PMS_X. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_X = 0x1 + // Position of REGION15_R0_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION15_R0_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_W_Msk = 0x2 + // Bit REGION15_R0_PMS_W. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_W = 0x2 + // Position of REGION15_R0_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION15_R0_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_R_Msk = 0x4 + // Bit REGION15_R0_PMS_R. + HP_APM_REGION15_PMS_ATTR_REGION15_R0_PMS_R = 0x4 + // Position of REGION15_R1_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION15_R1_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_X_Msk = 0x10 + // Bit REGION15_R1_PMS_X. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_X = 0x10 + // Position of REGION15_R1_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION15_R1_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_W_Msk = 0x20 + // Bit REGION15_R1_PMS_W. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_W = 0x20 + // Position of REGION15_R1_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION15_R1_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_R_Msk = 0x40 + // Bit REGION15_R1_PMS_R. + HP_APM_REGION15_PMS_ATTR_REGION15_R1_PMS_R = 0x40 + // Position of REGION15_R2_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION15_R2_PMS_X field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_X_Msk = 0x100 + // Bit REGION15_R2_PMS_X. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_X = 0x100 + // Position of REGION15_R2_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION15_R2_PMS_W field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_W_Msk = 0x200 + // Bit REGION15_R2_PMS_W. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_W = 0x200 + // Position of REGION15_R2_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_R_Pos = 0xa + // Bit mask of REGION15_R2_PMS_R field. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_R_Msk = 0x400 + // Bit REGION15_R2_PMS_R. + HP_APM_REGION15_PMS_ATTR_REGION15_R2_PMS_R = 0x400 + + // FUNC_CTRL: PMS function control register + // Position of M0_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Pos = 0x0 + // Bit mask of M0_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Msk = 0x1 + // Bit M0_PMS_FUNC_EN. + HP_APM_FUNC_CTRL_M0_PMS_FUNC_EN = 0x1 + // Position of M1_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M1_PMS_FUNC_EN_Pos = 0x1 + // Bit mask of M1_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M1_PMS_FUNC_EN_Msk = 0x2 + // Bit M1_PMS_FUNC_EN. + HP_APM_FUNC_CTRL_M1_PMS_FUNC_EN = 0x2 + // Position of M2_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M2_PMS_FUNC_EN_Pos = 0x2 + // Bit mask of M2_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M2_PMS_FUNC_EN_Msk = 0x4 + // Bit M2_PMS_FUNC_EN. + HP_APM_FUNC_CTRL_M2_PMS_FUNC_EN = 0x4 + // Position of M3_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M3_PMS_FUNC_EN_Pos = 0x3 + // Bit mask of M3_PMS_FUNC_EN field. + HP_APM_FUNC_CTRL_M3_PMS_FUNC_EN_Msk = 0x8 + // Bit M3_PMS_FUNC_EN. + HP_APM_FUNC_CTRL_M3_PMS_FUNC_EN = 0x8 + + // M0_STATUS: M0 status register + // Position of M0_EXCEPTION_STATUS field. + HP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M0_EXCEPTION_STATUS field. + HP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Msk = 0x3 + + // M0_STATUS_CLR: M0 status clear register + // Position of M0_REGION_STATUS_CLR field. + HP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M0_REGION_STATUS_CLR field. + HP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Msk = 0x1 + // Bit M0_REGION_STATUS_CLR. + HP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR = 0x1 + + // M0_EXCEPTION_INFO0: M0 exception_info0 register + // Position of M0_EXCEPTION_REGION field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M0_EXCEPTION_REGION field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Msk = 0xffff + // Position of M0_EXCEPTION_MODE field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M0_EXCEPTION_MODE field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Msk = 0x30000 + // Position of M0_EXCEPTION_ID field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M0_EXCEPTION_ID field. + HP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Msk = 0x7c0000 + + // M0_EXCEPTION_INFO1: M0 exception_info1 register + // Position of M0_EXCEPTION_ADDR field. + HP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M0_EXCEPTION_ADDR field. + HP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Msk = 0xffffffff + + // M1_STATUS: M1 status register + // Position of M1_EXCEPTION_STATUS field. + HP_APM_M1_STATUS_M1_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M1_EXCEPTION_STATUS field. + HP_APM_M1_STATUS_M1_EXCEPTION_STATUS_Msk = 0x3 + + // M1_STATUS_CLR: M1 status clear register + // Position of M1_REGION_STATUS_CLR field. + HP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M1_REGION_STATUS_CLR field. + HP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR_Msk = 0x1 + // Bit M1_REGION_STATUS_CLR. + HP_APM_M1_STATUS_CLR_M1_REGION_STATUS_CLR = 0x1 + + // M1_EXCEPTION_INFO0: M1 exception_info0 register + // Position of M1_EXCEPTION_REGION field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M1_EXCEPTION_REGION field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_REGION_Msk = 0xffff + // Position of M1_EXCEPTION_MODE field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M1_EXCEPTION_MODE field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_MODE_Msk = 0x30000 + // Position of M1_EXCEPTION_ID field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M1_EXCEPTION_ID field. + HP_APM_M1_EXCEPTION_INFO0_M1_EXCEPTION_ID_Msk = 0x7c0000 + + // M1_EXCEPTION_INFO1: M1 exception_info1 register + // Position of M1_EXCEPTION_ADDR field. + HP_APM_M1_EXCEPTION_INFO1_M1_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M1_EXCEPTION_ADDR field. + HP_APM_M1_EXCEPTION_INFO1_M1_EXCEPTION_ADDR_Msk = 0xffffffff + + // M2_STATUS: M2 status register + // Position of M2_EXCEPTION_STATUS field. + HP_APM_M2_STATUS_M2_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M2_EXCEPTION_STATUS field. + HP_APM_M2_STATUS_M2_EXCEPTION_STATUS_Msk = 0x3 + + // M2_STATUS_CLR: M2 status clear register + // Position of M2_REGION_STATUS_CLR field. + HP_APM_M2_STATUS_CLR_M2_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M2_REGION_STATUS_CLR field. + HP_APM_M2_STATUS_CLR_M2_REGION_STATUS_CLR_Msk = 0x1 + // Bit M2_REGION_STATUS_CLR. + HP_APM_M2_STATUS_CLR_M2_REGION_STATUS_CLR = 0x1 + + // M2_EXCEPTION_INFO0: M2 exception_info0 register + // Position of M2_EXCEPTION_REGION field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M2_EXCEPTION_REGION field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_REGION_Msk = 0xffff + // Position of M2_EXCEPTION_MODE field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M2_EXCEPTION_MODE field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_MODE_Msk = 0x30000 + // Position of M2_EXCEPTION_ID field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M2_EXCEPTION_ID field. + HP_APM_M2_EXCEPTION_INFO0_M2_EXCEPTION_ID_Msk = 0x7c0000 + + // M2_EXCEPTION_INFO1: M2 exception_info1 register + // Position of M2_EXCEPTION_ADDR field. + HP_APM_M2_EXCEPTION_INFO1_M2_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M2_EXCEPTION_ADDR field. + HP_APM_M2_EXCEPTION_INFO1_M2_EXCEPTION_ADDR_Msk = 0xffffffff + + // M3_STATUS: M3 status register + // Position of M3_EXCEPTION_STATUS field. + HP_APM_M3_STATUS_M3_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M3_EXCEPTION_STATUS field. + HP_APM_M3_STATUS_M3_EXCEPTION_STATUS_Msk = 0x3 + + // M3_STATUS_CLR: M3 status clear register + // Position of M3_REGION_STATUS_CLR field. + HP_APM_M3_STATUS_CLR_M3_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M3_REGION_STATUS_CLR field. + HP_APM_M3_STATUS_CLR_M3_REGION_STATUS_CLR_Msk = 0x1 + // Bit M3_REGION_STATUS_CLR. + HP_APM_M3_STATUS_CLR_M3_REGION_STATUS_CLR = 0x1 + + // M3_EXCEPTION_INFO0: M3 exception_info0 register + // Position of M3_EXCEPTION_REGION field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M3_EXCEPTION_REGION field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_REGION_Msk = 0xffff + // Position of M3_EXCEPTION_MODE field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M3_EXCEPTION_MODE field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_MODE_Msk = 0x30000 + // Position of M3_EXCEPTION_ID field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M3_EXCEPTION_ID field. + HP_APM_M3_EXCEPTION_INFO0_M3_EXCEPTION_ID_Msk = 0x7c0000 + + // M3_EXCEPTION_INFO1: M3 exception_info1 register + // Position of M3_EXCEPTION_ADDR field. + HP_APM_M3_EXCEPTION_INFO1_M3_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M3_EXCEPTION_ADDR field. + HP_APM_M3_EXCEPTION_INFO1_M3_EXCEPTION_ADDR_Msk = 0xffffffff + + // INT_EN: APM interrupt enable register + // Position of M0_APM_INT_EN field. + HP_APM_INT_EN_M0_APM_INT_EN_Pos = 0x0 + // Bit mask of M0_APM_INT_EN field. + HP_APM_INT_EN_M0_APM_INT_EN_Msk = 0x1 + // Bit M0_APM_INT_EN. + HP_APM_INT_EN_M0_APM_INT_EN = 0x1 + // Position of M1_APM_INT_EN field. + HP_APM_INT_EN_M1_APM_INT_EN_Pos = 0x1 + // Bit mask of M1_APM_INT_EN field. + HP_APM_INT_EN_M1_APM_INT_EN_Msk = 0x2 + // Bit M1_APM_INT_EN. + HP_APM_INT_EN_M1_APM_INT_EN = 0x2 + // Position of M2_APM_INT_EN field. + HP_APM_INT_EN_M2_APM_INT_EN_Pos = 0x2 + // Bit mask of M2_APM_INT_EN field. + HP_APM_INT_EN_M2_APM_INT_EN_Msk = 0x4 + // Bit M2_APM_INT_EN. + HP_APM_INT_EN_M2_APM_INT_EN = 0x4 + // Position of M3_APM_INT_EN field. + HP_APM_INT_EN_M3_APM_INT_EN_Pos = 0x3 + // Bit mask of M3_APM_INT_EN field. + HP_APM_INT_EN_M3_APM_INT_EN_Msk = 0x8 + // Bit M3_APM_INT_EN. + HP_APM_INT_EN_M3_APM_INT_EN = 0x8 + + // CLOCK_GATE: clock gating register + // Position of CLK_EN field. + HP_APM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + HP_APM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + HP_APM_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + HP_APM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + HP_APM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for HP_SYS: High-Power System +const ( + // EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + // Position of ENABLE_SPI_MANUAL_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Pos = 0x0 + // Bit mask of ENABLE_SPI_MANUAL_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Msk = 0x1 + // Bit ENABLE_SPI_MANUAL_ENCRYPT. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT = 0x1 + // Position of ENABLE_DOWNLOAD_DB_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Pos = 0x1 + // Bit mask of ENABLE_DOWNLOAD_DB_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Msk = 0x2 + // Bit ENABLE_DOWNLOAD_DB_ENCRYPT. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT = 0x2 + // Position of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Pos = 0x2 + // Bit mask of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Msk = 0x4 + // Bit ENABLE_DOWNLOAD_G0CB_DECRYPT. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT = 0x4 + // Position of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x3 + // Bit mask of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x8 + // Bit ENABLE_DOWNLOAD_MANUAL_ENCRYPT. + HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT = 0x8 + + // SRAM_USAGE_CONF: HP memory usage configuration register + // Position of SRAM_USAGE field. + HP_SYS_SRAM_USAGE_CONF_SRAM_USAGE_Pos = 0xa + // Bit mask of SRAM_USAGE field. + HP_SYS_SRAM_USAGE_CONF_SRAM_USAGE_Msk = 0x7c00 + // Position of MAC_DUMP_ALLOC field. + HP_SYS_SRAM_USAGE_CONF_MAC_DUMP_ALLOC_Pos = 0x14 + // Bit mask of MAC_DUMP_ALLOC field. + HP_SYS_SRAM_USAGE_CONF_MAC_DUMP_ALLOC_Msk = 0x1f00000 + // Position of CACHE_USAGE field. + HP_SYS_SRAM_USAGE_CONF_CACHE_USAGE_Pos = 0x1f + // Bit mask of CACHE_USAGE field. + HP_SYS_SRAM_USAGE_CONF_CACHE_USAGE_Msk = 0x80000000 + // Bit CACHE_USAGE. + HP_SYS_SRAM_USAGE_CONF_CACHE_USAGE = 0x80000000 + + // SEC_DPA_CONF: HP anti-DPA security configuration register + // Position of SEC_DPA_LEVEL field. + HP_SYS_SEC_DPA_CONF_SEC_DPA_LEVEL_Pos = 0x0 + // Bit mask of SEC_DPA_LEVEL field. + HP_SYS_SEC_DPA_CONF_SEC_DPA_LEVEL_Msk = 0x3 + // Position of SEC_DPA_CFG_SEL field. + HP_SYS_SEC_DPA_CONF_SEC_DPA_CFG_SEL_Pos = 0x2 + // Bit mask of SEC_DPA_CFG_SEL field. + HP_SYS_SEC_DPA_CONF_SEC_DPA_CFG_SEL_Msk = 0x4 + // Bit SEC_DPA_CFG_SEL. + HP_SYS_SEC_DPA_CONF_SEC_DPA_CFG_SEL = 0x4 + + // CPU_PERI_TIMEOUT_CONF: CPU_PERI_TIMEOUT configuration register + // Position of CPU_PERI_TIMEOUT_THRES field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_THRES_Pos = 0x0 + // Bit mask of CPU_PERI_TIMEOUT_THRES field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_THRES_Msk = 0xffff + // Position of CPU_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR_Pos = 0x10 + // Bit mask of CPU_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR_Msk = 0x10000 + // Bit CPU_PERI_TIMEOUT_INT_CLEAR. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_INT_CLEAR = 0x10000 + // Position of CPU_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN_Pos = 0x11 + // Bit mask of CPU_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN_Msk = 0x20000 + // Bit CPU_PERI_TIMEOUT_PROTECT_EN. + HP_SYS_CPU_PERI_TIMEOUT_CONF_CPU_PERI_TIMEOUT_PROTECT_EN = 0x20000 + + // CPU_PERI_TIMEOUT_ADDR: CPU_PERI_TIMEOUT_ADDR register + // Position of CPU_PERI_TIMEOUT_ADDR field. + HP_SYS_CPU_PERI_TIMEOUT_ADDR_CPU_PERI_TIMEOUT_ADDR_Pos = 0x0 + // Bit mask of CPU_PERI_TIMEOUT_ADDR field. + HP_SYS_CPU_PERI_TIMEOUT_ADDR_CPU_PERI_TIMEOUT_ADDR_Msk = 0xffffffff + + // CPU_PERI_TIMEOUT_UID: CPU_PERI_TIMEOUT_UID register + // Position of CPU_PERI_TIMEOUT_UID field. + HP_SYS_CPU_PERI_TIMEOUT_UID_CPU_PERI_TIMEOUT_UID_Pos = 0x0 + // Bit mask of CPU_PERI_TIMEOUT_UID field. + HP_SYS_CPU_PERI_TIMEOUT_UID_CPU_PERI_TIMEOUT_UID_Msk = 0x7f + + // HP_PERI_TIMEOUT_CONF: HP_PERI_TIMEOUT configuration register + // Position of HP_PERI_TIMEOUT_THRES field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_THRES_Pos = 0x0 + // Bit mask of HP_PERI_TIMEOUT_THRES field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_THRES_Msk = 0xffff + // Position of HP_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR_Pos = 0x10 + // Bit mask of HP_PERI_TIMEOUT_INT_CLEAR field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR_Msk = 0x10000 + // Bit HP_PERI_TIMEOUT_INT_CLEAR. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_INT_CLEAR = 0x10000 + // Position of HP_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN_Pos = 0x11 + // Bit mask of HP_PERI_TIMEOUT_PROTECT_EN field. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN_Msk = 0x20000 + // Bit HP_PERI_TIMEOUT_PROTECT_EN. + HP_SYS_HP_PERI_TIMEOUT_CONF_HP_PERI_TIMEOUT_PROTECT_EN = 0x20000 + + // HP_PERI_TIMEOUT_ADDR: HP_PERI_TIMEOUT_ADDR register + // Position of HP_PERI_TIMEOUT_ADDR field. + HP_SYS_HP_PERI_TIMEOUT_ADDR_HP_PERI_TIMEOUT_ADDR_Pos = 0x0 + // Bit mask of HP_PERI_TIMEOUT_ADDR field. + HP_SYS_HP_PERI_TIMEOUT_ADDR_HP_PERI_TIMEOUT_ADDR_Msk = 0xffffffff + + // HP_PERI_TIMEOUT_UID: HP_PERI_TIMEOUT_UID register + // Position of HP_PERI_TIMEOUT_UID field. + HP_SYS_HP_PERI_TIMEOUT_UID_HP_PERI_TIMEOUT_UID_Pos = 0x0 + // Bit mask of HP_PERI_TIMEOUT_UID field. + HP_SYS_HP_PERI_TIMEOUT_UID_HP_PERI_TIMEOUT_UID_Msk = 0x7f + + // ROM_TABLE_LOCK: Rom-Table lock register + // Position of ROM_TABLE_LOCK field. + HP_SYS_ROM_TABLE_LOCK_ROM_TABLE_LOCK_Pos = 0x0 + // Bit mask of ROM_TABLE_LOCK field. + HP_SYS_ROM_TABLE_LOCK_ROM_TABLE_LOCK_Msk = 0x1 + // Bit ROM_TABLE_LOCK. + HP_SYS_ROM_TABLE_LOCK_ROM_TABLE_LOCK = 0x1 + + // ROM_TABLE: Rom-Table register + // Position of ROM_TABLE field. + HP_SYS_ROM_TABLE_ROM_TABLE_Pos = 0x0 + // Bit mask of ROM_TABLE field. + HP_SYS_ROM_TABLE_ROM_TABLE_Msk = 0xffffffff + + // MEM_TEST_CONF: MEM_TEST configuration register + // Position of HP_MEM_WPULSE field. + HP_SYS_MEM_TEST_CONF_HP_MEM_WPULSE_Pos = 0x0 + // Bit mask of HP_MEM_WPULSE field. + HP_SYS_MEM_TEST_CONF_HP_MEM_WPULSE_Msk = 0x7 + // Position of HP_MEM_WA field. + HP_SYS_MEM_TEST_CONF_HP_MEM_WA_Pos = 0x3 + // Bit mask of HP_MEM_WA field. + HP_SYS_MEM_TEST_CONF_HP_MEM_WA_Msk = 0x38 + // Position of HP_MEM_RA field. + HP_SYS_MEM_TEST_CONF_HP_MEM_RA_Pos = 0x6 + // Bit mask of HP_MEM_RA field. + HP_SYS_MEM_TEST_CONF_HP_MEM_RA_Msk = 0xc0 + // Position of HP_MEM_RM field. + HP_SYS_MEM_TEST_CONF_HP_MEM_RM_Pos = 0x8 + // Bit mask of HP_MEM_RM field. + HP_SYS_MEM_TEST_CONF_HP_MEM_RM_Msk = 0xf00 + // Position of ROM_RM field. + HP_SYS_MEM_TEST_CONF_ROM_RM_Pos = 0xc + // Bit mask of ROM_RM field. + HP_SYS_MEM_TEST_CONF_ROM_RM_Msk = 0xf000 + + // RND_ECO: redcy eco register. + // Position of REDCY_ENA field. + HP_SYS_RND_ECO_REDCY_ENA_Pos = 0x0 + // Bit mask of REDCY_ENA field. + HP_SYS_RND_ECO_REDCY_ENA_Msk = 0x1 + // Bit REDCY_ENA. + HP_SYS_RND_ECO_REDCY_ENA = 0x1 + // Position of REDCY_RESULT field. + HP_SYS_RND_ECO_REDCY_RESULT_Pos = 0x1 + // Bit mask of REDCY_RESULT field. + HP_SYS_RND_ECO_REDCY_RESULT_Msk = 0x2 + // Bit REDCY_RESULT. + HP_SYS_RND_ECO_REDCY_RESULT = 0x2 + + // RND_ECO_LOW: redcy eco low register. + // Position of REDCY_LOW field. + HP_SYS_RND_ECO_LOW_REDCY_LOW_Pos = 0x0 + // Bit mask of REDCY_LOW field. + HP_SYS_RND_ECO_LOW_REDCY_LOW_Msk = 0xffffffff + + // RND_ECO_HIGH: redcy eco high register. + // Position of REDCY_HIGH field. + HP_SYS_RND_ECO_HIGH_REDCY_HIGH_Pos = 0x0 + // Bit mask of REDCY_HIGH field. + HP_SYS_RND_ECO_HIGH_REDCY_HIGH_Msk = 0xffffffff + + // CLOCK_GATE: HP-SYSTEM clock gating configure register + // Position of CLK_EN field. + HP_SYS_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + HP_SYS_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + HP_SYS_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Date register. + // Position of DATE field. + HP_SYS_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + HP_SYS_DATE_DATE_Msk = 0xfffffff +) + +// Constants for I2C0: I2C (Inter-Integrated Circuit) Controller 0 +const ( + // SCL_LOW_PERIOD: Configures the low level width of the SCL Clock + // Position of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x1ff + + // CTR: Transmission setting + // Position of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + I2C_CTR_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + I2C_CTR_SCL_FORCE_OUT = 0x2 + // Position of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2 + // Bit mask of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4 + // Bit SAMPLE_SCL_LEVEL. + I2C_CTR_SAMPLE_SCL_LEVEL = 0x4 + // Position of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Pos = 0x3 + // Bit mask of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Msk = 0x8 + // Bit RX_FULL_ACK_LEVEL. + I2C_CTR_RX_FULL_ACK_LEVEL = 0x8 + // Position of MS_MODE field. + I2C_CTR_MS_MODE_Pos = 0x4 + // Bit mask of MS_MODE field. + I2C_CTR_MS_MODE_Msk = 0x10 + // Bit MS_MODE. + I2C_CTR_MS_MODE = 0x10 + // Position of TRANS_START field. + I2C_CTR_TRANS_START_Pos = 0x5 + // Bit mask of TRANS_START field. + I2C_CTR_TRANS_START_Msk = 0x20 + // Bit TRANS_START. + I2C_CTR_TRANS_START = 0x20 + // Position of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Msk = 0x40 + // Bit TX_LSB_FIRST. + I2C_CTR_TX_LSB_FIRST = 0x40 + // Position of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Msk = 0x80 + // Bit RX_LSB_FIRST. + I2C_CTR_RX_LSB_FIRST = 0x80 + // Position of CLK_EN field. + I2C_CTR_CLK_EN_Pos = 0x8 + // Bit mask of CLK_EN field. + I2C_CTR_CLK_EN_Msk = 0x100 + // Bit CLK_EN. + I2C_CTR_CLK_EN = 0x100 + // Position of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Pos = 0x9 + // Bit mask of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Msk = 0x200 + // Bit ARBITRATION_EN. + I2C_CTR_ARBITRATION_EN = 0x200 + // Position of FSM_RST field. + I2C_CTR_FSM_RST_Pos = 0xa + // Bit mask of FSM_RST field. + I2C_CTR_FSM_RST_Msk = 0x400 + // Bit FSM_RST. + I2C_CTR_FSM_RST = 0x400 + // Position of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Pos = 0xb + // Bit mask of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Msk = 0x800 + // Bit CONF_UPGATE. + I2C_CTR_CONF_UPGATE = 0x800 + // Position of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Pos = 0xc + // Bit mask of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Msk = 0x1000 + // Bit SLV_TX_AUTO_START_EN. + I2C_CTR_SLV_TX_AUTO_START_EN = 0x1000 + // Position of ADDR_10BIT_RW_CHECK_EN field. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Pos = 0xd + // Bit mask of ADDR_10BIT_RW_CHECK_EN field. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Msk = 0x2000 + // Bit ADDR_10BIT_RW_CHECK_EN. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN = 0x2000 + // Position of ADDR_BROADCASTING_EN field. + I2C_CTR_ADDR_BROADCASTING_EN_Pos = 0xe + // Bit mask of ADDR_BROADCASTING_EN field. + I2C_CTR_ADDR_BROADCASTING_EN_Msk = 0x4000 + // Bit ADDR_BROADCASTING_EN. + I2C_CTR_ADDR_BROADCASTING_EN = 0x4000 + + // SR: Describe I2C work status. + // Position of RESP_REC field. + I2C_SR_RESP_REC_Pos = 0x0 + // Bit mask of RESP_REC field. + I2C_SR_RESP_REC_Msk = 0x1 + // Bit RESP_REC. + I2C_SR_RESP_REC = 0x1 + // Position of SLAVE_RW field. + I2C_SR_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + I2C_SR_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + I2C_SR_SLAVE_RW = 0x2 + // Position of ARB_LOST field. + I2C_SR_ARB_LOST_Pos = 0x3 + // Bit mask of ARB_LOST field. + I2C_SR_ARB_LOST_Msk = 0x8 + // Bit ARB_LOST. + I2C_SR_ARB_LOST = 0x8 + // Position of BUS_BUSY field. + I2C_SR_BUS_BUSY_Pos = 0x4 + // Bit mask of BUS_BUSY field. + I2C_SR_BUS_BUSY_Msk = 0x10 + // Bit BUS_BUSY. + I2C_SR_BUS_BUSY = 0x10 + // Position of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Pos = 0x5 + // Bit mask of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Msk = 0x20 + // Bit SLAVE_ADDRESSED. + I2C_SR_SLAVE_ADDRESSED = 0x20 + // Position of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Pos = 0x8 + // Bit mask of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Msk = 0x3f00 + // Position of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Pos = 0xe + // Bit mask of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Msk = 0xc000 + // Position of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Pos = 0x12 + // Bit mask of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Msk = 0xfc0000 + // Position of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: Setting time out control for receiving data. + // Position of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Pos = 0x0 + // Bit mask of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Msk = 0x1f + // Position of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Pos = 0x5 + // Bit mask of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Msk = 0x20 + // Bit TIME_OUT_EN. + I2C_TO_TIME_OUT_EN = 0x20 + + // SLAVE_ADDR: Local slave address setting + // Position of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // FIFO_ST: FIFO status register. + // Position of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Pos = 0x0 + // Bit mask of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Msk = 0x1f + // Position of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Pos = 0x5 + // Bit mask of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Msk = 0x3e0 + // Position of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Pos = 0xa + // Bit mask of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Msk = 0x7c00 + // Position of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Pos = 0xf + // Bit mask of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Msk = 0xf8000 + // Position of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Pos = 0x16 + // Bit mask of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Msk = 0x3fc00000 + + // FIFO_CONF: FIFO configuration register. + // Position of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0x1f + // Position of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5 + // Bit mask of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x3e0 + // Position of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa + // Bit mask of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400 + // Bit NONFIFO_EN. + I2C_FIFO_CONF_NONFIFO_EN = 0x400 + // Position of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Pos = 0xb + // Bit mask of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Msk = 0x800 + // Bit FIFO_ADDR_CFG_EN. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN = 0x800 + // Position of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc + // Bit mask of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000 + // Bit RX_FIFO_RST. + I2C_FIFO_CONF_RX_FIFO_RST = 0x1000 + // Position of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd + // Bit mask of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000 + // Bit TX_FIFO_RST. + I2C_FIFO_CONF_TX_FIFO_RST = 0x2000 + // Position of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Pos = 0xe + // Bit mask of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000 + // Bit FIFO_PRT_EN. + I2C_FIFO_CONF_FIFO_PRT_EN = 0x4000 + + // DATA: Rx FIFO read data. + // Position of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Pos = 0x0 + // Bit mask of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Msk = 0x1 + // Bit RXFIFO_WM_INT_RAW. + I2C_INT_RAW_RXFIFO_WM_INT_RAW = 0x1 + // Position of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Msk = 0x2 + // Bit TXFIFO_WM_INT_RAW. + I2C_INT_RAW_TXFIFO_WM_INT_RAW = 0x2 + // Position of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4 + // Bit RXFIFO_OVF_INT_RAW. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4 + // Position of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3 + // Bit mask of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8 + // Bit END_DETECT_INT_RAW. + I2C_INT_RAW_END_DETECT_INT_RAW = 0x8 + // Position of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_RAW. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW = 0x10 + // Position of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_RAW. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20 + // Position of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_RAW. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW = 0x40 + // Position of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_RAW. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80 + // Position of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8 + // Bit mask of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100 + // Bit TIME_OUT_INT_RAW. + I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100 + // Position of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9 + // Bit mask of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200 + // Bit TRANS_START_INT_RAW. + I2C_INT_RAW_TRANS_START_INT_RAW = 0x200 + // Position of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Pos = 0xa + // Bit mask of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Msk = 0x400 + // Bit NACK_INT_RAW. + I2C_INT_RAW_NACK_INT_RAW = 0x400 + // Position of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Msk = 0x800 + // Bit TXFIFO_OVF_INT_RAW. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW = 0x800 + // Position of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_RAW. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW = 0x1000 + // Position of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Msk = 0x2000 + // Bit SCL_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_ST_TO_INT_RAW = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW = 0x4000 + // Position of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Pos = 0xf + // Bit mask of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Msk = 0x8000 + // Bit DET_START_INT_RAW. + I2C_INT_RAW_DET_START_INT_RAW = 0x8000 + // Position of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_RAW. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW = 0x10000 + // Position of GENERAL_CALL_INT_RAW field. + I2C_INT_RAW_GENERAL_CALL_INT_RAW_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_RAW field. + I2C_INT_RAW_GENERAL_CALL_INT_RAW_Msk = 0x20000 + // Bit GENERAL_CALL_INT_RAW. + I2C_INT_RAW_GENERAL_CALL_INT_RAW = 0x20000 + // Position of SLAVE_ADDR_UNMATCH_INT_RAW field. + I2C_INT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW_Pos = 0x12 + // Bit mask of SLAVE_ADDR_UNMATCH_INT_RAW field. + I2C_INT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW_Msk = 0x40000 + // Bit SLAVE_ADDR_UNMATCH_INT_RAW. + I2C_INT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW = 0x40000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Msk = 0x1 + // Bit RXFIFO_WM_INT_CLR. + I2C_INT_CLR_RXFIFO_WM_INT_CLR = 0x1 + // Position of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Msk = 0x2 + // Bit TXFIFO_WM_INT_CLR. + I2C_INT_CLR_TXFIFO_WM_INT_CLR = 0x2 + // Position of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4 + // Bit RXFIFO_OVF_INT_CLR. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4 + // Position of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3 + // Bit mask of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8 + // Bit END_DETECT_INT_CLR. + I2C_INT_CLR_END_DETECT_INT_CLR = 0x8 + // Position of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_CLR. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR = 0x10 + // Position of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_CLR. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_CLR. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR = 0x40 + // Position of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_CLR. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit TIME_OUT_INT_CLR. + I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100 + // Position of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9 + // Bit mask of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200 + // Bit TRANS_START_INT_CLR. + I2C_INT_CLR_TRANS_START_INT_CLR = 0x200 + // Position of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Pos = 0xa + // Bit mask of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Msk = 0x400 + // Bit NACK_INT_CLR. + I2C_INT_CLR_NACK_INT_CLR = 0x400 + // Position of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Msk = 0x800 + // Bit TXFIFO_OVF_INT_CLR. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR = 0x800 + // Position of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_CLR. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR = 0x1000 + // Position of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Msk = 0x2000 + // Bit SCL_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_ST_TO_INT_CLR = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR = 0x4000 + // Position of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Pos = 0xf + // Bit mask of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Msk = 0x8000 + // Bit DET_START_INT_CLR. + I2C_INT_CLR_DET_START_INT_CLR = 0x8000 + // Position of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_CLR. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR = 0x10000 + // Position of GENERAL_CALL_INT_CLR field. + I2C_INT_CLR_GENERAL_CALL_INT_CLR_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_CLR field. + I2C_INT_CLR_GENERAL_CALL_INT_CLR_Msk = 0x20000 + // Bit GENERAL_CALL_INT_CLR. + I2C_INT_CLR_GENERAL_CALL_INT_CLR = 0x20000 + // Position of SLAVE_ADDR_UNMATCH_INT_CLR field. + I2C_INT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR_Pos = 0x12 + // Bit mask of SLAVE_ADDR_UNMATCH_INT_CLR field. + I2C_INT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR_Msk = 0x40000 + // Bit SLAVE_ADDR_UNMATCH_INT_CLR. + I2C_INT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR = 0x40000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Msk = 0x1 + // Bit RXFIFO_WM_INT_ENA. + I2C_INT_ENA_RXFIFO_WM_INT_ENA = 0x1 + // Position of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Msk = 0x2 + // Bit TXFIFO_WM_INT_ENA. + I2C_INT_ENA_TXFIFO_WM_INT_ENA = 0x2 + // Position of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ENA. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4 + // Position of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3 + // Bit mask of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8 + // Bit END_DETECT_INT_ENA. + I2C_INT_ENA_END_DETECT_INT_ENA = 0x8 + // Position of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ENA. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA = 0x10 + // Position of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ENA. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20 + // Position of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ENA. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA = 0x40 + // Position of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ENA. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80 + // Position of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100 + // Bit TIME_OUT_INT_ENA. + I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100 + // Position of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9 + // Bit mask of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200 + // Bit TRANS_START_INT_ENA. + I2C_INT_ENA_TRANS_START_INT_ENA = 0x200 + // Position of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Pos = 0xa + // Bit mask of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Msk = 0x400 + // Bit NACK_INT_ENA. + I2C_INT_ENA_NACK_INT_ENA = 0x400 + // Position of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ENA. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA = 0x800 + // Position of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ENA. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA = 0x1000 + // Position of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_ST_TO_INT_ENA = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA = 0x4000 + // Position of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Pos = 0xf + // Bit mask of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Msk = 0x8000 + // Bit DET_START_INT_ENA. + I2C_INT_ENA_DET_START_INT_ENA = 0x8000 + // Position of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ENA. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA = 0x10000 + // Position of GENERAL_CALL_INT_ENA field. + I2C_INT_ENA_GENERAL_CALL_INT_ENA_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_ENA field. + I2C_INT_ENA_GENERAL_CALL_INT_ENA_Msk = 0x20000 + // Bit GENERAL_CALL_INT_ENA. + I2C_INT_ENA_GENERAL_CALL_INT_ENA = 0x20000 + // Position of SLAVE_ADDR_UNMATCH_INT_ENA field. + I2C_INT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA_Pos = 0x12 + // Bit mask of SLAVE_ADDR_UNMATCH_INT_ENA field. + I2C_INT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA_Msk = 0x40000 + // Bit SLAVE_ADDR_UNMATCH_INT_ENA. + I2C_INT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA = 0x40000 + + // INT_STATUS: Status of captured I2C communication events + // Position of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Msk = 0x1 + // Bit RXFIFO_WM_INT_ST. + I2C_INT_STATUS_RXFIFO_WM_INT_ST = 0x1 + // Position of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Msk = 0x2 + // Bit TXFIFO_WM_INT_ST. + I2C_INT_STATUS_TXFIFO_WM_INT_ST = 0x2 + // Position of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ST. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4 + // Position of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3 + // Bit mask of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8 + // Bit END_DETECT_INT_ST. + I2C_INT_STATUS_END_DETECT_INT_ST = 0x8 + // Position of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ST. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST = 0x10 + // Position of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ST. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20 + // Position of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ST. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST = 0x40 + // Position of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ST. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80 + // Position of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100 + // Bit TIME_OUT_INT_ST. + I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100 + // Position of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9 + // Bit mask of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200 + // Bit TRANS_START_INT_ST. + I2C_INT_STATUS_TRANS_START_INT_ST = 0x200 + // Position of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Pos = 0xa + // Bit mask of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Msk = 0x400 + // Bit NACK_INT_ST. + I2C_INT_STATUS_NACK_INT_ST = 0x400 + // Position of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ST. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST = 0x800 + // Position of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ST. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST = 0x1000 + // Position of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_ST_TO_INT_ST = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST = 0x4000 + // Position of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Pos = 0xf + // Bit mask of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Msk = 0x8000 + // Bit DET_START_INT_ST. + I2C_INT_STATUS_DET_START_INT_ST = 0x8000 + // Position of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ST. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST = 0x10000 + // Position of GENERAL_CALL_INT_ST field. + I2C_INT_STATUS_GENERAL_CALL_INT_ST_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_ST field. + I2C_INT_STATUS_GENERAL_CALL_INT_ST_Msk = 0x20000 + // Bit GENERAL_CALL_INT_ST. + I2C_INT_STATUS_GENERAL_CALL_INT_ST = 0x20000 + // Position of SLAVE_ADDR_UNMATCH_INT_ST field. + I2C_INT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST_Pos = 0x12 + // Bit mask of SLAVE_ADDR_UNMATCH_INT_ST field. + I2C_INT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST_Msk = 0x40000 + // Bit SLAVE_ADDR_UNMATCH_INT_ST. + I2C_INT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST = 0x40000 + + // SDA_HOLD: Configures the hold time after a negative SCL edge. + // Position of TIME field. + I2C_SDA_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_HOLD_TIME_Msk = 0x1ff + + // SDA_SAMPLE: Configures the sample time after a positive SCL edge. + // Position of TIME field. + I2C_SDA_SAMPLE_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_SAMPLE_TIME_Msk = 0x1ff + + // SCL_HIGH_PERIOD: Configures the high level width of SCL + // Position of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x1ff + // Position of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Pos = 0x9 + // Bit mask of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Msk = 0xfe00 + + // SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition + // Position of TIME field. + I2C_SCL_START_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_START_HOLD_TIME_Msk = 0x1ff + + // SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA + // Position of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Msk = 0x1ff + + // SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_HOLD_TIME_Msk = 0x1ff + + // SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_SETUP_TIME_Msk = 0x1ff + + // FILTER_CFG: SCL and SDA filter configuration register + // Position of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0 + // Bit mask of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Msk = 0xf + // Position of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x4 + // Bit mask of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Msk = 0xf0 + // Position of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Pos = 0x8 + // Bit mask of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Msk = 0x100 + // Bit SCL_FILTER_EN. + I2C_FILTER_CFG_SCL_FILTER_EN = 0x100 + // Position of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Pos = 0x9 + // Bit mask of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Msk = 0x200 + // Bit SDA_FILTER_EN. + I2C_FILTER_CFG_SDA_FILTER_EN = 0x200 + + // CLK_CONF: I2C CLK configuration register + // Position of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Pos = 0x0 + // Bit mask of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff + // Position of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Pos = 0x8 + // Bit mask of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Msk = 0x3f00 + // Position of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Pos = 0xe + // Bit mask of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Msk = 0xfc000 + // Position of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Msk = 0x100000 + // Bit SCLK_SEL. + I2C_CLK_CONF_SCLK_SEL = 0x100000 + // Position of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Pos = 0x15 + // Bit mask of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Msk = 0x200000 + // Bit SCLK_ACTIVE. + I2C_CLK_CONF_SCLK_ACTIVE = 0x200000 + + // COMD0: I2C command register %s + // Position of COMMAND field. + I2C_COMD_COMMAND_Pos = 0x0 + // Bit mask of COMMAND field. + I2C_COMD_COMMAND_Msk = 0x3fff + // Position of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Pos = 0x1f + // Bit mask of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Msk = 0x80000000 + // Bit COMMAND_DONE. + I2C_COMD_COMMAND_DONE = 0x80000000 + + // SCL_ST_TIME_OUT: SCL status time out register + // Position of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Msk = 0x1f + + // SCL_MAIN_ST_TIME_OUT: SCL main status time out register + // Position of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Msk = 0x1f + + // SCL_SP_CONF: Power configuration register + // Position of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Pos = 0x0 + // Bit mask of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Msk = 0x1 + // Bit SCL_RST_SLV_EN. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN = 0x1 + // Position of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Pos = 0x1 + // Bit mask of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Msk = 0x3e + // Position of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Pos = 0x6 + // Bit mask of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Msk = 0x40 + // Bit SCL_PD_EN. + I2C_SCL_SP_CONF_SCL_PD_EN = 0x40 + // Position of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Pos = 0x7 + // Bit mask of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Msk = 0x80 + // Bit SDA_PD_EN. + I2C_SCL_SP_CONF_SDA_PD_EN = 0x80 + + // SCL_STRETCH_CONF: Set SCL stretch of I2C slave + // Position of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Pos = 0x0 + // Bit mask of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Msk = 0x3ff + // Position of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Pos = 0xa + // Bit mask of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Msk = 0x400 + // Bit SLAVE_SCL_STRETCH_EN. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN = 0x400 + // Position of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Pos = 0xb + // Bit mask of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Msk = 0x800 + // Bit SLAVE_SCL_STRETCH_CLR. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR = 0x800 + // Position of SLAVE_BYTE_ACK_CTL_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Pos = 0xc + // Bit mask of SLAVE_BYTE_ACK_CTL_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Msk = 0x1000 + // Bit SLAVE_BYTE_ACK_CTL_EN. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN = 0x1000 + // Position of SLAVE_BYTE_ACK_LVL field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Pos = 0xd + // Bit mask of SLAVE_BYTE_ACK_LVL field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Msk = 0x2000 + // Bit SLAVE_BYTE_ACK_LVL. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL = 0x2000 + + // DATE: Version register + // Position of DATE field. + I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2C_DATE_DATE_Msk = 0xffffffff + + // TXFIFO_START_ADDR: I2C TXFIFO base address register + // Position of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Msk = 0xffffffff + + // RXFIFO_START_ADDR: I2C RXFIFO base address register + // Position of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Msk = 0xffffffff +) + +// Constants for I2S0: I2S (Inter-IC Sound) Controller 0 +const ( + // INT_RAW: I2S interrupt raw register, valid in level. + // Position of RX_DONE_INT_RAW field. + I2S_INT_RAW_RX_DONE_INT_RAW_Pos = 0x0 + // Bit mask of RX_DONE_INT_RAW field. + I2S_INT_RAW_RX_DONE_INT_RAW_Msk = 0x1 + // Bit RX_DONE_INT_RAW. + I2S_INT_RAW_RX_DONE_INT_RAW = 0x1 + // Position of TX_DONE_INT_RAW field. + I2S_INT_RAW_TX_DONE_INT_RAW_Pos = 0x1 + // Bit mask of TX_DONE_INT_RAW field. + I2S_INT_RAW_TX_DONE_INT_RAW_Msk = 0x2 + // Bit TX_DONE_INT_RAW. + I2S_INT_RAW_TX_DONE_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + I2S_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + I2S_INT_RAW_TX_HUNG_INT_RAW = 0x8 + + // INT_ST: I2S interrupt status register. + // Position of RX_DONE_INT_ST field. + I2S_INT_ST_RX_DONE_INT_ST_Pos = 0x0 + // Bit mask of RX_DONE_INT_ST field. + I2S_INT_ST_RX_DONE_INT_ST_Msk = 0x1 + // Bit RX_DONE_INT_ST. + I2S_INT_ST_RX_DONE_INT_ST = 0x1 + // Position of TX_DONE_INT_ST field. + I2S_INT_ST_TX_DONE_INT_ST_Pos = 0x1 + // Bit mask of TX_DONE_INT_ST field. + I2S_INT_ST_TX_DONE_INT_ST_Msk = 0x2 + // Bit TX_DONE_INT_ST. + I2S_INT_ST_TX_DONE_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + I2S_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + I2S_INT_ST_TX_HUNG_INT_ST = 0x8 + + // INT_ENA: I2S interrupt enable register. + // Position of RX_DONE_INT_ENA field. + I2S_INT_ENA_RX_DONE_INT_ENA_Pos = 0x0 + // Bit mask of RX_DONE_INT_ENA field. + I2S_INT_ENA_RX_DONE_INT_ENA_Msk = 0x1 + // Bit RX_DONE_INT_ENA. + I2S_INT_ENA_RX_DONE_INT_ENA = 0x1 + // Position of TX_DONE_INT_ENA field. + I2S_INT_ENA_TX_DONE_INT_ENA_Pos = 0x1 + // Bit mask of TX_DONE_INT_ENA field. + I2S_INT_ENA_TX_DONE_INT_ENA_Msk = 0x2 + // Bit TX_DONE_INT_ENA. + I2S_INT_ENA_TX_DONE_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + I2S_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + I2S_INT_ENA_TX_HUNG_INT_ENA = 0x8 + + // INT_CLR: I2S interrupt clear register. + // Position of RX_DONE_INT_CLR field. + I2S_INT_CLR_RX_DONE_INT_CLR_Pos = 0x0 + // Bit mask of RX_DONE_INT_CLR field. + I2S_INT_CLR_RX_DONE_INT_CLR_Msk = 0x1 + // Bit RX_DONE_INT_CLR. + I2S_INT_CLR_RX_DONE_INT_CLR = 0x1 + // Position of TX_DONE_INT_CLR field. + I2S_INT_CLR_TX_DONE_INT_CLR_Pos = 0x1 + // Bit mask of TX_DONE_INT_CLR field. + I2S_INT_CLR_TX_DONE_INT_CLR_Msk = 0x2 + // Bit TX_DONE_INT_CLR. + I2S_INT_CLR_TX_DONE_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + I2S_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + I2S_INT_CLR_TX_HUNG_INT_CLR = 0x8 + + // RX_CONF: I2S RX configure register + // Position of RX_RESET field. + I2S_RX_CONF_RX_RESET_Pos = 0x0 + // Bit mask of RX_RESET field. + I2S_RX_CONF_RX_RESET_Msk = 0x1 + // Bit RX_RESET. + I2S_RX_CONF_RX_RESET = 0x1 + // Position of RX_FIFO_RESET field. + I2S_RX_CONF_RX_FIFO_RESET_Pos = 0x1 + // Bit mask of RX_FIFO_RESET field. + I2S_RX_CONF_RX_FIFO_RESET_Msk = 0x2 + // Bit RX_FIFO_RESET. + I2S_RX_CONF_RX_FIFO_RESET = 0x2 + // Position of RX_START field. + I2S_RX_CONF_RX_START_Pos = 0x2 + // Bit mask of RX_START field. + I2S_RX_CONF_RX_START_Msk = 0x4 + // Bit RX_START. + I2S_RX_CONF_RX_START = 0x4 + // Position of RX_SLAVE_MOD field. + I2S_RX_CONF_RX_SLAVE_MOD_Pos = 0x3 + // Bit mask of RX_SLAVE_MOD field. + I2S_RX_CONF_RX_SLAVE_MOD_Msk = 0x8 + // Bit RX_SLAVE_MOD. + I2S_RX_CONF_RX_SLAVE_MOD = 0x8 + // Position of RX_STOP_MODE field. + I2S_RX_CONF_RX_STOP_MODE_Pos = 0x4 + // Bit mask of RX_STOP_MODE field. + I2S_RX_CONF_RX_STOP_MODE_Msk = 0x30 + // Position of RX_MONO field. + I2S_RX_CONF_RX_MONO_Pos = 0x6 + // Bit mask of RX_MONO field. + I2S_RX_CONF_RX_MONO_Msk = 0x40 + // Bit RX_MONO. + I2S_RX_CONF_RX_MONO = 0x40 + // Position of RX_BIG_ENDIAN field. + I2S_RX_CONF_RX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of RX_BIG_ENDIAN field. + I2S_RX_CONF_RX_BIG_ENDIAN_Msk = 0x80 + // Bit RX_BIG_ENDIAN. + I2S_RX_CONF_RX_BIG_ENDIAN = 0x80 + // Position of RX_UPDATE field. + I2S_RX_CONF_RX_UPDATE_Pos = 0x8 + // Bit mask of RX_UPDATE field. + I2S_RX_CONF_RX_UPDATE_Msk = 0x100 + // Bit RX_UPDATE. + I2S_RX_CONF_RX_UPDATE = 0x100 + // Position of RX_MONO_FST_VLD field. + I2S_RX_CONF_RX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of RX_MONO_FST_VLD field. + I2S_RX_CONF_RX_MONO_FST_VLD_Msk = 0x200 + // Bit RX_MONO_FST_VLD. + I2S_RX_CONF_RX_MONO_FST_VLD = 0x200 + // Position of RX_PCM_CONF field. + I2S_RX_CONF_RX_PCM_CONF_Pos = 0xa + // Bit mask of RX_PCM_CONF field. + I2S_RX_CONF_RX_PCM_CONF_Msk = 0xc00 + // Position of RX_PCM_BYPASS field. + I2S_RX_CONF_RX_PCM_BYPASS_Pos = 0xc + // Bit mask of RX_PCM_BYPASS field. + I2S_RX_CONF_RX_PCM_BYPASS_Msk = 0x1000 + // Bit RX_PCM_BYPASS. + I2S_RX_CONF_RX_PCM_BYPASS = 0x1000 + // Position of RX_MSB_SHIFT field. + I2S_RX_CONF_RX_MSB_SHIFT_Pos = 0xd + // Bit mask of RX_MSB_SHIFT field. + I2S_RX_CONF_RX_MSB_SHIFT_Msk = 0x2000 + // Bit RX_MSB_SHIFT. + I2S_RX_CONF_RX_MSB_SHIFT = 0x2000 + // Position of RX_LEFT_ALIGN field. + I2S_RX_CONF_RX_LEFT_ALIGN_Pos = 0xf + // Bit mask of RX_LEFT_ALIGN field. + I2S_RX_CONF_RX_LEFT_ALIGN_Msk = 0x8000 + // Bit RX_LEFT_ALIGN. + I2S_RX_CONF_RX_LEFT_ALIGN = 0x8000 + // Position of RX_24_FILL_EN field. + I2S_RX_CONF_RX_24_FILL_EN_Pos = 0x10 + // Bit mask of RX_24_FILL_EN field. + I2S_RX_CONF_RX_24_FILL_EN_Msk = 0x10000 + // Bit RX_24_FILL_EN. + I2S_RX_CONF_RX_24_FILL_EN = 0x10000 + // Position of RX_WS_IDLE_POL field. + I2S_RX_CONF_RX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of RX_WS_IDLE_POL field. + I2S_RX_CONF_RX_WS_IDLE_POL_Msk = 0x20000 + // Bit RX_WS_IDLE_POL. + I2S_RX_CONF_RX_WS_IDLE_POL = 0x20000 + // Position of RX_BIT_ORDER field. + I2S_RX_CONF_RX_BIT_ORDER_Pos = 0x12 + // Bit mask of RX_BIT_ORDER field. + I2S_RX_CONF_RX_BIT_ORDER_Msk = 0x40000 + // Bit RX_BIT_ORDER. + I2S_RX_CONF_RX_BIT_ORDER = 0x40000 + // Position of RX_TDM_EN field. + I2S_RX_CONF_RX_TDM_EN_Pos = 0x13 + // Bit mask of RX_TDM_EN field. + I2S_RX_CONF_RX_TDM_EN_Msk = 0x80000 + // Bit RX_TDM_EN. + I2S_RX_CONF_RX_TDM_EN = 0x80000 + // Position of RX_PDM_EN field. + I2S_RX_CONF_RX_PDM_EN_Pos = 0x14 + // Bit mask of RX_PDM_EN field. + I2S_RX_CONF_RX_PDM_EN_Msk = 0x100000 + // Bit RX_PDM_EN. + I2S_RX_CONF_RX_PDM_EN = 0x100000 + // Position of RX_BCK_DIV_NUM field. + I2S_RX_CONF_RX_BCK_DIV_NUM_Pos = 0x15 + // Bit mask of RX_BCK_DIV_NUM field. + I2S_RX_CONF_RX_BCK_DIV_NUM_Msk = 0x7e00000 + + // TX_CONF: I2S TX configure register + // Position of TX_RESET field. + I2S_TX_CONF_TX_RESET_Pos = 0x0 + // Bit mask of TX_RESET field. + I2S_TX_CONF_TX_RESET_Msk = 0x1 + // Bit TX_RESET. + I2S_TX_CONF_TX_RESET = 0x1 + // Position of TX_FIFO_RESET field. + I2S_TX_CONF_TX_FIFO_RESET_Pos = 0x1 + // Bit mask of TX_FIFO_RESET field. + I2S_TX_CONF_TX_FIFO_RESET_Msk = 0x2 + // Bit TX_FIFO_RESET. + I2S_TX_CONF_TX_FIFO_RESET = 0x2 + // Position of TX_START field. + I2S_TX_CONF_TX_START_Pos = 0x2 + // Bit mask of TX_START field. + I2S_TX_CONF_TX_START_Msk = 0x4 + // Bit TX_START. + I2S_TX_CONF_TX_START = 0x4 + // Position of TX_SLAVE_MOD field. + I2S_TX_CONF_TX_SLAVE_MOD_Pos = 0x3 + // Bit mask of TX_SLAVE_MOD field. + I2S_TX_CONF_TX_SLAVE_MOD_Msk = 0x8 + // Bit TX_SLAVE_MOD. + I2S_TX_CONF_TX_SLAVE_MOD = 0x8 + // Position of TX_STOP_EN field. + I2S_TX_CONF_TX_STOP_EN_Pos = 0x4 + // Bit mask of TX_STOP_EN field. + I2S_TX_CONF_TX_STOP_EN_Msk = 0x10 + // Bit TX_STOP_EN. + I2S_TX_CONF_TX_STOP_EN = 0x10 + // Position of TX_CHAN_EQUAL field. + I2S_TX_CONF_TX_CHAN_EQUAL_Pos = 0x5 + // Bit mask of TX_CHAN_EQUAL field. + I2S_TX_CONF_TX_CHAN_EQUAL_Msk = 0x20 + // Bit TX_CHAN_EQUAL. + I2S_TX_CONF_TX_CHAN_EQUAL = 0x20 + // Position of TX_MONO field. + I2S_TX_CONF_TX_MONO_Pos = 0x6 + // Bit mask of TX_MONO field. + I2S_TX_CONF_TX_MONO_Msk = 0x40 + // Bit TX_MONO. + I2S_TX_CONF_TX_MONO = 0x40 + // Position of TX_BIG_ENDIAN field. + I2S_TX_CONF_TX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of TX_BIG_ENDIAN field. + I2S_TX_CONF_TX_BIG_ENDIAN_Msk = 0x80 + // Bit TX_BIG_ENDIAN. + I2S_TX_CONF_TX_BIG_ENDIAN = 0x80 + // Position of TX_UPDATE field. + I2S_TX_CONF_TX_UPDATE_Pos = 0x8 + // Bit mask of TX_UPDATE field. + I2S_TX_CONF_TX_UPDATE_Msk = 0x100 + // Bit TX_UPDATE. + I2S_TX_CONF_TX_UPDATE = 0x100 + // Position of TX_MONO_FST_VLD field. + I2S_TX_CONF_TX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of TX_MONO_FST_VLD field. + I2S_TX_CONF_TX_MONO_FST_VLD_Msk = 0x200 + // Bit TX_MONO_FST_VLD. + I2S_TX_CONF_TX_MONO_FST_VLD = 0x200 + // Position of TX_PCM_CONF field. + I2S_TX_CONF_TX_PCM_CONF_Pos = 0xa + // Bit mask of TX_PCM_CONF field. + I2S_TX_CONF_TX_PCM_CONF_Msk = 0xc00 + // Position of TX_PCM_BYPASS field. + I2S_TX_CONF_TX_PCM_BYPASS_Pos = 0xc + // Bit mask of TX_PCM_BYPASS field. + I2S_TX_CONF_TX_PCM_BYPASS_Msk = 0x1000 + // Bit TX_PCM_BYPASS. + I2S_TX_CONF_TX_PCM_BYPASS = 0x1000 + // Position of TX_MSB_SHIFT field. + I2S_TX_CONF_TX_MSB_SHIFT_Pos = 0xd + // Bit mask of TX_MSB_SHIFT field. + I2S_TX_CONF_TX_MSB_SHIFT_Msk = 0x2000 + // Bit TX_MSB_SHIFT. + I2S_TX_CONF_TX_MSB_SHIFT = 0x2000 + // Position of TX_BCK_NO_DLY field. + I2S_TX_CONF_TX_BCK_NO_DLY_Pos = 0xe + // Bit mask of TX_BCK_NO_DLY field. + I2S_TX_CONF_TX_BCK_NO_DLY_Msk = 0x4000 + // Bit TX_BCK_NO_DLY. + I2S_TX_CONF_TX_BCK_NO_DLY = 0x4000 + // Position of TX_LEFT_ALIGN field. + I2S_TX_CONF_TX_LEFT_ALIGN_Pos = 0xf + // Bit mask of TX_LEFT_ALIGN field. + I2S_TX_CONF_TX_LEFT_ALIGN_Msk = 0x8000 + // Bit TX_LEFT_ALIGN. + I2S_TX_CONF_TX_LEFT_ALIGN = 0x8000 + // Position of TX_24_FILL_EN field. + I2S_TX_CONF_TX_24_FILL_EN_Pos = 0x10 + // Bit mask of TX_24_FILL_EN field. + I2S_TX_CONF_TX_24_FILL_EN_Msk = 0x10000 + // Bit TX_24_FILL_EN. + I2S_TX_CONF_TX_24_FILL_EN = 0x10000 + // Position of TX_WS_IDLE_POL field. + I2S_TX_CONF_TX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of TX_WS_IDLE_POL field. + I2S_TX_CONF_TX_WS_IDLE_POL_Msk = 0x20000 + // Bit TX_WS_IDLE_POL. + I2S_TX_CONF_TX_WS_IDLE_POL = 0x20000 + // Position of TX_BIT_ORDER field. + I2S_TX_CONF_TX_BIT_ORDER_Pos = 0x12 + // Bit mask of TX_BIT_ORDER field. + I2S_TX_CONF_TX_BIT_ORDER_Msk = 0x40000 + // Bit TX_BIT_ORDER. + I2S_TX_CONF_TX_BIT_ORDER = 0x40000 + // Position of TX_TDM_EN field. + I2S_TX_CONF_TX_TDM_EN_Pos = 0x13 + // Bit mask of TX_TDM_EN field. + I2S_TX_CONF_TX_TDM_EN_Msk = 0x80000 + // Bit TX_TDM_EN. + I2S_TX_CONF_TX_TDM_EN = 0x80000 + // Position of TX_PDM_EN field. + I2S_TX_CONF_TX_PDM_EN_Pos = 0x14 + // Bit mask of TX_PDM_EN field. + I2S_TX_CONF_TX_PDM_EN_Msk = 0x100000 + // Bit TX_PDM_EN. + I2S_TX_CONF_TX_PDM_EN = 0x100000 + // Position of TX_BCK_DIV_NUM field. + I2S_TX_CONF_TX_BCK_DIV_NUM_Pos = 0x15 + // Bit mask of TX_BCK_DIV_NUM field. + I2S_TX_CONF_TX_BCK_DIV_NUM_Msk = 0x7e00000 + // Position of TX_CHAN_MOD field. + I2S_TX_CONF_TX_CHAN_MOD_Pos = 0x1b + // Bit mask of TX_CHAN_MOD field. + I2S_TX_CONF_TX_CHAN_MOD_Msk = 0x38000000 + // Position of SIG_LOOPBACK field. + I2S_TX_CONF_SIG_LOOPBACK_Pos = 0x1e + // Bit mask of SIG_LOOPBACK field. + I2S_TX_CONF_SIG_LOOPBACK_Msk = 0x40000000 + // Bit SIG_LOOPBACK. + I2S_TX_CONF_SIG_LOOPBACK = 0x40000000 + + // RX_CONF1: I2S RX configure register 1 + // Position of RX_TDM_WS_WIDTH field. + I2S_RX_CONF1_RX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of RX_TDM_WS_WIDTH field. + I2S_RX_CONF1_RX_TDM_WS_WIDTH_Msk = 0x1ff + // Position of RX_BITS_MOD field. + I2S_RX_CONF1_RX_BITS_MOD_Pos = 0xe + // Bit mask of RX_BITS_MOD field. + I2S_RX_CONF1_RX_BITS_MOD_Msk = 0x7c000 + // Position of RX_HALF_SAMPLE_BITS field. + I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Pos = 0x13 + // Bit mask of RX_HALF_SAMPLE_BITS field. + I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Msk = 0x7f80000 + // Position of RX_TDM_CHAN_BITS field. + I2S_RX_CONF1_RX_TDM_CHAN_BITS_Pos = 0x1b + // Bit mask of RX_TDM_CHAN_BITS field. + I2S_RX_CONF1_RX_TDM_CHAN_BITS_Msk = 0xf8000000 + + // TX_CONF1: I2S TX configure register 1 + // Position of TX_TDM_WS_WIDTH field. + I2S_TX_CONF1_TX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of TX_TDM_WS_WIDTH field. + I2S_TX_CONF1_TX_TDM_WS_WIDTH_Msk = 0x1ff + // Position of TX_BITS_MOD field. + I2S_TX_CONF1_TX_BITS_MOD_Pos = 0xe + // Bit mask of TX_BITS_MOD field. + I2S_TX_CONF1_TX_BITS_MOD_Msk = 0x7c000 + // Position of TX_HALF_SAMPLE_BITS field. + I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Pos = 0x13 + // Bit mask of TX_HALF_SAMPLE_BITS field. + I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Msk = 0x7f80000 + // Position of TX_TDM_CHAN_BITS field. + I2S_TX_CONF1_TX_TDM_CHAN_BITS_Pos = 0x1b + // Bit mask of TX_TDM_CHAN_BITS field. + I2S_TX_CONF1_TX_TDM_CHAN_BITS_Msk = 0xf8000000 + + // RX_CLKM_CONF: I2S RX clock configure register + // Position of RX_CLKM_DIV_NUM field. + I2S_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_NUM field. + I2S_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Msk = 0xff + // Position of RX_CLK_ACTIVE field. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of RX_CLK_ACTIVE field. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE_Msk = 0x4000000 + // Bit RX_CLK_ACTIVE. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE = 0x4000000 + // Position of RX_CLK_SEL field. + I2S_RX_CLKM_CONF_RX_CLK_SEL_Pos = 0x1b + // Bit mask of RX_CLK_SEL field. + I2S_RX_CLKM_CONF_RX_CLK_SEL_Msk = 0x18000000 + // Position of MCLK_SEL field. + I2S_RX_CLKM_CONF_MCLK_SEL_Pos = 0x1d + // Bit mask of MCLK_SEL field. + I2S_RX_CLKM_CONF_MCLK_SEL_Msk = 0x20000000 + // Bit MCLK_SEL. + I2S_RX_CLKM_CONF_MCLK_SEL = 0x20000000 + + // TX_CLKM_CONF: I2S TX clock configure register + // Position of TX_CLKM_DIV_NUM field. + I2S_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_NUM field. + I2S_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Msk = 0xff + // Position of TX_CLK_ACTIVE field. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of TX_CLK_ACTIVE field. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE_Msk = 0x4000000 + // Bit TX_CLK_ACTIVE. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE = 0x4000000 + // Position of TX_CLK_SEL field. + I2S_TX_CLKM_CONF_TX_CLK_SEL_Pos = 0x1b + // Bit mask of TX_CLK_SEL field. + I2S_TX_CLKM_CONF_TX_CLK_SEL_Msk = 0x18000000 + // Position of CLK_EN field. + I2S_TX_CLKM_CONF_CLK_EN_Pos = 0x1d + // Bit mask of CLK_EN field. + I2S_TX_CLKM_CONF_CLK_EN_Msk = 0x20000000 + // Bit CLK_EN. + I2S_TX_CLKM_CONF_CLK_EN = 0x20000000 + + // RX_CLKM_DIV_CONF: I2S RX module clock divider configure register + // Position of RX_CLKM_DIV_Z field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_Z field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Msk = 0x1ff + // Position of RX_CLKM_DIV_Y field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of RX_CLKM_DIV_Y field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of RX_CLKM_DIV_X field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of RX_CLKM_DIV_X field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of RX_CLKM_DIV_YN1 field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of RX_CLKM_DIV_YN1 field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit RX_CLKM_DIV_YN1. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1 = 0x8000000 + + // TX_CLKM_DIV_CONF: I2S TX module clock divider configure register + // Position of TX_CLKM_DIV_Z field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_Z field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Msk = 0x1ff + // Position of TX_CLKM_DIV_Y field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of TX_CLKM_DIV_Y field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of TX_CLKM_DIV_X field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of TX_CLKM_DIV_X field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of TX_CLKM_DIV_YN1 field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of TX_CLKM_DIV_YN1 field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit TX_CLKM_DIV_YN1. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1 = 0x8000000 + + // TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register + // Position of TX_PDM_HP_BYPASS field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Pos = 0x0 + // Bit mask of TX_PDM_HP_BYPASS field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Msk = 0x1 + // Bit TX_PDM_HP_BYPASS. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS = 0x1 + // Position of TX_PDM_SINC_OSR2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Pos = 0x1 + // Bit mask of TX_PDM_SINC_OSR2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Msk = 0x1e + // Position of TX_PDM_PRESCALE field. + I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Pos = 0x5 + // Bit mask of TX_PDM_PRESCALE field. + I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Msk = 0x1fe0 + // Position of TX_PDM_HP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Pos = 0xd + // Bit mask of TX_PDM_HP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Msk = 0x6000 + // Position of TX_PDM_LP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Pos = 0xf + // Bit mask of TX_PDM_LP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Msk = 0x18000 + // Position of TX_PDM_SINC_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Pos = 0x11 + // Bit mask of TX_PDM_SINC_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Msk = 0x60000 + // Position of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Pos = 0x13 + // Bit mask of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Msk = 0x180000 + // Position of TX_PDM_SIGMADELTA_DITHER2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Pos = 0x15 + // Bit mask of TX_PDM_SIGMADELTA_DITHER2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Msk = 0x200000 + // Bit TX_PDM_SIGMADELTA_DITHER2. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2 = 0x200000 + // Position of TX_PDM_SIGMADELTA_DITHER field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Pos = 0x16 + // Bit mask of TX_PDM_SIGMADELTA_DITHER field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Msk = 0x400000 + // Bit TX_PDM_SIGMADELTA_DITHER. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER = 0x400000 + // Position of TX_PDM_DAC_2OUT_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Pos = 0x17 + // Bit mask of TX_PDM_DAC_2OUT_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Msk = 0x800000 + // Bit TX_PDM_DAC_2OUT_EN. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN = 0x800000 + // Position of TX_PDM_DAC_MODE_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Pos = 0x18 + // Bit mask of TX_PDM_DAC_MODE_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Msk = 0x1000000 + // Bit TX_PDM_DAC_MODE_EN. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN = 0x1000000 + // Position of PCM2PDM_CONV_EN field. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Pos = 0x19 + // Bit mask of PCM2PDM_CONV_EN field. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Msk = 0x2000000 + // Bit PCM2PDM_CONV_EN. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN = 0x2000000 + + // TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register + // Position of TX_PDM_FP field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Pos = 0x0 + // Bit mask of TX_PDM_FP field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Msk = 0x3ff + // Position of TX_PDM_FS field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Pos = 0xa + // Bit mask of TX_PDM_FS field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Msk = 0xffc00 + // Position of TX_IIR_HP_MULT12_5 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Pos = 0x14 + // Bit mask of TX_IIR_HP_MULT12_5 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Msk = 0x700000 + // Position of TX_IIR_HP_MULT12_0 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Pos = 0x17 + // Bit mask of TX_IIR_HP_MULT12_0 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Msk = 0x3800000 + + // RX_TDM_CTRL: I2S TX TDM mode control register + // Position of RX_TDM_PDM_CHAN0_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Pos = 0x0 + // Bit mask of RX_TDM_PDM_CHAN0_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Msk = 0x1 + // Bit RX_TDM_PDM_CHAN0_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN = 0x1 + // Position of RX_TDM_PDM_CHAN1_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Pos = 0x1 + // Bit mask of RX_TDM_PDM_CHAN1_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Msk = 0x2 + // Bit RX_TDM_PDM_CHAN1_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN = 0x2 + // Position of RX_TDM_PDM_CHAN2_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Pos = 0x2 + // Bit mask of RX_TDM_PDM_CHAN2_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Msk = 0x4 + // Bit RX_TDM_PDM_CHAN2_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN = 0x4 + // Position of RX_TDM_PDM_CHAN3_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Pos = 0x3 + // Bit mask of RX_TDM_PDM_CHAN3_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Msk = 0x8 + // Bit RX_TDM_PDM_CHAN3_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN = 0x8 + // Position of RX_TDM_PDM_CHAN4_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Pos = 0x4 + // Bit mask of RX_TDM_PDM_CHAN4_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Msk = 0x10 + // Bit RX_TDM_PDM_CHAN4_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN = 0x10 + // Position of RX_TDM_PDM_CHAN5_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Pos = 0x5 + // Bit mask of RX_TDM_PDM_CHAN5_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Msk = 0x20 + // Bit RX_TDM_PDM_CHAN5_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN = 0x20 + // Position of RX_TDM_PDM_CHAN6_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Pos = 0x6 + // Bit mask of RX_TDM_PDM_CHAN6_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Msk = 0x40 + // Bit RX_TDM_PDM_CHAN6_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN = 0x40 + // Position of RX_TDM_PDM_CHAN7_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Pos = 0x7 + // Bit mask of RX_TDM_PDM_CHAN7_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Msk = 0x80 + // Bit RX_TDM_PDM_CHAN7_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN = 0x80 + // Position of RX_TDM_CHAN8_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of RX_TDM_CHAN8_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Msk = 0x100 + // Bit RX_TDM_CHAN8_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN = 0x100 + // Position of RX_TDM_CHAN9_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of RX_TDM_CHAN9_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Msk = 0x200 + // Bit RX_TDM_CHAN9_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN = 0x200 + // Position of RX_TDM_CHAN10_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of RX_TDM_CHAN10_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Msk = 0x400 + // Bit RX_TDM_CHAN10_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN = 0x400 + // Position of RX_TDM_CHAN11_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of RX_TDM_CHAN11_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Msk = 0x800 + // Bit RX_TDM_CHAN11_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN = 0x800 + // Position of RX_TDM_CHAN12_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of RX_TDM_CHAN12_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit RX_TDM_CHAN12_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN = 0x1000 + // Position of RX_TDM_CHAN13_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of RX_TDM_CHAN13_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit RX_TDM_CHAN13_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN = 0x2000 + // Position of RX_TDM_CHAN14_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of RX_TDM_CHAN14_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit RX_TDM_CHAN14_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN = 0x4000 + // Position of RX_TDM_CHAN15_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of RX_TDM_CHAN15_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit RX_TDM_CHAN15_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN = 0x8000 + // Position of RX_TDM_TOT_CHAN_NUM field. + I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of RX_TDM_TOT_CHAN_NUM field. + I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + + // TX_TDM_CTRL: I2S TX TDM mode control register + // Position of TX_TDM_CHAN0_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Pos = 0x0 + // Bit mask of TX_TDM_CHAN0_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Msk = 0x1 + // Bit TX_TDM_CHAN0_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN = 0x1 + // Position of TX_TDM_CHAN1_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Pos = 0x1 + // Bit mask of TX_TDM_CHAN1_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Msk = 0x2 + // Bit TX_TDM_CHAN1_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN = 0x2 + // Position of TX_TDM_CHAN2_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Pos = 0x2 + // Bit mask of TX_TDM_CHAN2_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Msk = 0x4 + // Bit TX_TDM_CHAN2_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN = 0x4 + // Position of TX_TDM_CHAN3_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Pos = 0x3 + // Bit mask of TX_TDM_CHAN3_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Msk = 0x8 + // Bit TX_TDM_CHAN3_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN = 0x8 + // Position of TX_TDM_CHAN4_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Pos = 0x4 + // Bit mask of TX_TDM_CHAN4_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Msk = 0x10 + // Bit TX_TDM_CHAN4_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN = 0x10 + // Position of TX_TDM_CHAN5_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Pos = 0x5 + // Bit mask of TX_TDM_CHAN5_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Msk = 0x20 + // Bit TX_TDM_CHAN5_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN = 0x20 + // Position of TX_TDM_CHAN6_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Pos = 0x6 + // Bit mask of TX_TDM_CHAN6_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Msk = 0x40 + // Bit TX_TDM_CHAN6_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN = 0x40 + // Position of TX_TDM_CHAN7_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Pos = 0x7 + // Bit mask of TX_TDM_CHAN7_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Msk = 0x80 + // Bit TX_TDM_CHAN7_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN = 0x80 + // Position of TX_TDM_CHAN8_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of TX_TDM_CHAN8_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Msk = 0x100 + // Bit TX_TDM_CHAN8_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN = 0x100 + // Position of TX_TDM_CHAN9_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of TX_TDM_CHAN9_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Msk = 0x200 + // Bit TX_TDM_CHAN9_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN = 0x200 + // Position of TX_TDM_CHAN10_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of TX_TDM_CHAN10_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Msk = 0x400 + // Bit TX_TDM_CHAN10_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN = 0x400 + // Position of TX_TDM_CHAN11_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of TX_TDM_CHAN11_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Msk = 0x800 + // Bit TX_TDM_CHAN11_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN = 0x800 + // Position of TX_TDM_CHAN12_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of TX_TDM_CHAN12_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit TX_TDM_CHAN12_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN = 0x1000 + // Position of TX_TDM_CHAN13_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of TX_TDM_CHAN13_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit TX_TDM_CHAN13_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN = 0x2000 + // Position of TX_TDM_CHAN14_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of TX_TDM_CHAN14_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit TX_TDM_CHAN14_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN = 0x4000 + // Position of TX_TDM_CHAN15_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of TX_TDM_CHAN15_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit TX_TDM_CHAN15_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN = 0x8000 + // Position of TX_TDM_TOT_CHAN_NUM field. + I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of TX_TDM_TOT_CHAN_NUM field. + I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + // Position of TX_TDM_SKIP_MSK_EN field. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Pos = 0x14 + // Bit mask of TX_TDM_SKIP_MSK_EN field. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Msk = 0x100000 + // Bit TX_TDM_SKIP_MSK_EN. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN = 0x100000 + + // RX_TIMING: I2S RX timing control register + // Position of RX_SD_IN_DM field. + I2S_RX_TIMING_RX_SD_IN_DM_Pos = 0x0 + // Bit mask of RX_SD_IN_DM field. + I2S_RX_TIMING_RX_SD_IN_DM_Msk = 0x3 + // Position of RX_WS_OUT_DM field. + I2S_RX_TIMING_RX_WS_OUT_DM_Pos = 0x10 + // Bit mask of RX_WS_OUT_DM field. + I2S_RX_TIMING_RX_WS_OUT_DM_Msk = 0x30000 + // Position of RX_BCK_OUT_DM field. + I2S_RX_TIMING_RX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of RX_BCK_OUT_DM field. + I2S_RX_TIMING_RX_BCK_OUT_DM_Msk = 0x300000 + // Position of RX_WS_IN_DM field. + I2S_RX_TIMING_RX_WS_IN_DM_Pos = 0x18 + // Bit mask of RX_WS_IN_DM field. + I2S_RX_TIMING_RX_WS_IN_DM_Msk = 0x3000000 + // Position of RX_BCK_IN_DM field. + I2S_RX_TIMING_RX_BCK_IN_DM_Pos = 0x1c + // Bit mask of RX_BCK_IN_DM field. + I2S_RX_TIMING_RX_BCK_IN_DM_Msk = 0x30000000 + + // TX_TIMING: I2S TX timing control register + // Position of TX_SD_OUT_DM field. + I2S_TX_TIMING_TX_SD_OUT_DM_Pos = 0x0 + // Bit mask of TX_SD_OUT_DM field. + I2S_TX_TIMING_TX_SD_OUT_DM_Msk = 0x3 + // Position of TX_SD1_OUT_DM field. + I2S_TX_TIMING_TX_SD1_OUT_DM_Pos = 0x4 + // Bit mask of TX_SD1_OUT_DM field. + I2S_TX_TIMING_TX_SD1_OUT_DM_Msk = 0x30 + // Position of TX_WS_OUT_DM field. + I2S_TX_TIMING_TX_WS_OUT_DM_Pos = 0x10 + // Bit mask of TX_WS_OUT_DM field. + I2S_TX_TIMING_TX_WS_OUT_DM_Msk = 0x30000 + // Position of TX_BCK_OUT_DM field. + I2S_TX_TIMING_TX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of TX_BCK_OUT_DM field. + I2S_TX_TIMING_TX_BCK_OUT_DM_Msk = 0x300000 + // Position of TX_WS_IN_DM field. + I2S_TX_TIMING_TX_WS_IN_DM_Pos = 0x18 + // Bit mask of TX_WS_IN_DM field. + I2S_TX_TIMING_TX_WS_IN_DM_Msk = 0x3000000 + // Position of TX_BCK_IN_DM field. + I2S_TX_TIMING_TX_BCK_IN_DM_Pos = 0x1c + // Bit mask of TX_BCK_IN_DM field. + I2S_TX_TIMING_TX_BCK_IN_DM_Msk = 0x30000000 + + // LC_HUNG_CONF: I2S HUNG configure register. + // Position of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Pos = 0x0 + // Bit mask of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Msk = 0xff + // Position of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit LC_FIFO_TIMEOUT_ENA. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA = 0x800 + + // RXEOF_NUM: I2S RX data number control register. + // Position of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Pos = 0x0 + // Bit mask of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Msk = 0xfff + + // CONF_SIGLE_DATA: I2S signal data register + // Position of SINGLE_DATA field. + I2S_CONF_SIGLE_DATA_SINGLE_DATA_Pos = 0x0 + // Bit mask of SINGLE_DATA field. + I2S_CONF_SIGLE_DATA_SINGLE_DATA_Msk = 0xffffffff + + // STATE: I2S TX status register + // Position of TX_IDLE field. + I2S_STATE_TX_IDLE_Pos = 0x0 + // Bit mask of TX_IDLE field. + I2S_STATE_TX_IDLE_Msk = 0x1 + // Bit TX_IDLE. + I2S_STATE_TX_IDLE = 0x1 + + // ETM_CONF: I2S ETM configure register + // Position of ETM_TX_SEND_WORD_NUM field. + I2S_ETM_CONF_ETM_TX_SEND_WORD_NUM_Pos = 0x0 + // Bit mask of ETM_TX_SEND_WORD_NUM field. + I2S_ETM_CONF_ETM_TX_SEND_WORD_NUM_Msk = 0x3ff + // Position of ETM_RX_RECEIVE_WORD_NUM field. + I2S_ETM_CONF_ETM_RX_RECEIVE_WORD_NUM_Pos = 0xa + // Bit mask of ETM_RX_RECEIVE_WORD_NUM field. + I2S_ETM_CONF_ETM_RX_RECEIVE_WORD_NUM_Msk = 0xffc00 + + // DATE: Version control register + // Position of DATE field. + I2S_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2S_DATE_DATE_Msk = 0xfffffff +) + +// Constants for INTERRUPT_CORE0: Interrupt Controller (Core 0) +const ( + // PMU_INTR_MAP: register description + // Position of PMU_INTR_MAP field. + INTMTX_CORE0_PMU_INTR_MAP_PMU_INTR_MAP_Pos = 0x0 + // Bit mask of PMU_INTR_MAP field. + INTMTX_CORE0_PMU_INTR_MAP_PMU_INTR_MAP_Msk = 0x1f + + // EFUSE_INTR_MAP: register description + // Position of EFUSE_INTR_MAP field. + INTMTX_CORE0_EFUSE_INTR_MAP_EFUSE_INTR_MAP_Pos = 0x0 + // Bit mask of EFUSE_INTR_MAP field. + INTMTX_CORE0_EFUSE_INTR_MAP_EFUSE_INTR_MAP_Msk = 0x1f + + // LP_RTC_TIMER_INTR_MAP: register description + // Position of LP_RTC_TIMER_INTR_MAP field. + INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_LP_RTC_TIMER_INTR_MAP_Pos = 0x0 + // Bit mask of LP_RTC_TIMER_INTR_MAP field. + INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_LP_RTC_TIMER_INTR_MAP_Msk = 0x1f + + // LP_BLE_TIMER_INTR_MAP: register description + // Position of LP_BLE_TIMER_INTR_MAP field. + INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_LP_BLE_TIMER_INTR_MAP_Pos = 0x0 + // Bit mask of LP_BLE_TIMER_INTR_MAP field. + INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_LP_BLE_TIMER_INTR_MAP_Msk = 0x1f + + // LP_WDT_INTR_MAP: register description + // Position of LP_WDT_INTR_MAP field. + INTMTX_CORE0_LP_WDT_INTR_MAP_LP_WDT_INTR_MAP_Pos = 0x0 + // Bit mask of LP_WDT_INTR_MAP field. + INTMTX_CORE0_LP_WDT_INTR_MAP_LP_WDT_INTR_MAP_Msk = 0x1f + + // LP_PERI_TIMEOUT_INTR_MAP: register description + // Position of LP_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_LP_PERI_TIMEOUT_INTR_MAP_Pos = 0x0 + // Bit mask of LP_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_LP_PERI_TIMEOUT_INTR_MAP_Msk = 0x1f + + // LP_APM_M0_INTR_MAP: register description + // Position of LP_APM_M0_INTR_MAP field. + INTMTX_CORE0_LP_APM_M0_INTR_MAP_LP_APM_M0_INTR_MAP_Pos = 0x0 + // Bit mask of LP_APM_M0_INTR_MAP field. + INTMTX_CORE0_LP_APM_M0_INTR_MAP_LP_APM_M0_INTR_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_0_MAP: register description + // Position of CPU_INTR_FROM_CPU_0_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_1_MAP: register description + // Position of CPU_INTR_FROM_CPU_1_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_2_MAP: register description + // Position of CPU_INTR_FROM_CPU_2_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_3_MAP: register description + // Position of CPU_INTR_FROM_CPU_3_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3_MAP field. + INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Msk = 0x1f + + // ASSIST_DEBUG_INTR_MAP: register description + // Position of ASSIST_DEBUG_INTR_MAP field. + INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Pos = 0x0 + // Bit mask of ASSIST_DEBUG_INTR_MAP field. + INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Msk = 0x1f + + // TRACE_INTR_MAP: register description + // Position of TRACE_INTR_MAP field. + INTMTX_CORE0_TRACE_INTR_MAP_TRACE_INTR_MAP_Pos = 0x0 + // Bit mask of TRACE_INTR_MAP field. + INTMTX_CORE0_TRACE_INTR_MAP_TRACE_INTR_MAP_Msk = 0x1f + + // CACHE_INTR_MAP: register description + // Position of CACHE_INTR_MAP field. + INTMTX_CORE0_CACHE_INTR_MAP_CACHE_INTR_MAP_Pos = 0x0 + // Bit mask of CACHE_INTR_MAP field. + INTMTX_CORE0_CACHE_INTR_MAP_CACHE_INTR_MAP_Msk = 0x1f + + // CPU_PERI_TIMEOUT_INTR_MAP: register description + // Position of CPU_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_CPU_PERI_TIMEOUT_INTR_MAP_Pos = 0x0 + // Bit mask of CPU_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_CPU_PERI_TIMEOUT_INTR_MAP_Msk = 0x1f + + // BT_MAC_INTR_MAP: register description + // Position of BT_MAC_INTR_MAP field. + INTMTX_CORE0_BT_MAC_INTR_MAP_BT_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of BT_MAC_INTR_MAP field. + INTMTX_CORE0_BT_MAC_INTR_MAP_BT_MAC_INTR_MAP_Msk = 0x1f + + // BT_BB_INTR_MAP: register description + // Position of BT_BB_INTR_MAP field. + INTMTX_CORE0_BT_BB_INTR_MAP_BT_BB_INTR_MAP_Pos = 0x0 + // Bit mask of BT_BB_INTR_MAP field. + INTMTX_CORE0_BT_BB_INTR_MAP_BT_BB_INTR_MAP_Msk = 0x1f + + // BT_BB_NMI_MAP: register description + // Position of BT_BB_NMI_MAP field. + INTMTX_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Pos = 0x0 + // Bit mask of BT_BB_NMI_MAP field. + INTMTX_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Msk = 0x1f + + // COEX_INTR_MAP: register description + // Position of COEX_INTR_MAP field. + INTMTX_CORE0_COEX_INTR_MAP_COEX_INTR_MAP_Pos = 0x0 + // Bit mask of COEX_INTR_MAP field. + INTMTX_CORE0_COEX_INTR_MAP_COEX_INTR_MAP_Msk = 0x1f + + // BLE_TIMER_INTR_MAP: register description + // Position of BLE_TIMER_INTR_MAP field. + INTMTX_CORE0_BLE_TIMER_INTR_MAP_BLE_TIMER_INTR_MAP_Pos = 0x0 + // Bit mask of BLE_TIMER_INTR_MAP field. + INTMTX_CORE0_BLE_TIMER_INTR_MAP_BLE_TIMER_INTR_MAP_Msk = 0x1f + + // BLE_SEC_INTR_MAP: register description + // Position of BLE_SEC_INTR_MAP field. + INTMTX_CORE0_BLE_SEC_INTR_MAP_BLE_SEC_INTR_MAP_Pos = 0x0 + // Bit mask of BLE_SEC_INTR_MAP field. + INTMTX_CORE0_BLE_SEC_INTR_MAP_BLE_SEC_INTR_MAP_Msk = 0x1f + + // ZB_MAC_INTR_MAP: register description + // Position of ZB_MAC_INTR_MAP field. + INTMTX_CORE0_ZB_MAC_INTR_MAP_ZB_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of ZB_MAC_INTR_MAP field. + INTMTX_CORE0_ZB_MAC_INTR_MAP_ZB_MAC_INTR_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_MAP: register description + // Position of GPIO_INTERRUPT_PRO_MAP field. + INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_MAP field. + INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_NMI_MAP: register description + // Position of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Msk = 0x1f + + // PAU_INTR_MAP: register description + // Position of PAU_INTR_MAP field. + INTMTX_CORE0_PAU_INTR_MAP_PAU_INTR_MAP_Pos = 0x0 + // Bit mask of PAU_INTR_MAP field. + INTMTX_CORE0_PAU_INTR_MAP_PAU_INTR_MAP_Msk = 0x1f + + // HP_PERI_TIMEOUT_INTR_MAP: register description + // Position of HP_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_HP_PERI_TIMEOUT_INTR_MAP_Pos = 0x0 + // Bit mask of HP_PERI_TIMEOUT_INTR_MAP field. + INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_HP_PERI_TIMEOUT_INTR_MAP_Msk = 0x1f + + // HP_APM_M0_INTR_MAP: register description + // Position of HP_APM_M0_INTR_MAP field. + INTMTX_CORE0_HP_APM_M0_INTR_MAP_HP_APM_M0_INTR_MAP_Pos = 0x0 + // Bit mask of HP_APM_M0_INTR_MAP field. + INTMTX_CORE0_HP_APM_M0_INTR_MAP_HP_APM_M0_INTR_MAP_Msk = 0x1f + + // HP_APM_M1_INTR_MAP: register description + // Position of HP_APM_M1_INTR_MAP field. + INTMTX_CORE0_HP_APM_M1_INTR_MAP_HP_APM_M1_INTR_MAP_Pos = 0x0 + // Bit mask of HP_APM_M1_INTR_MAP field. + INTMTX_CORE0_HP_APM_M1_INTR_MAP_HP_APM_M1_INTR_MAP_Msk = 0x1f + + // HP_APM_M2_INTR_MAP: register description + // Position of HP_APM_M2_INTR_MAP field. + INTMTX_CORE0_HP_APM_M2_INTR_MAP_HP_APM_M2_INTR_MAP_Pos = 0x0 + // Bit mask of HP_APM_M2_INTR_MAP field. + INTMTX_CORE0_HP_APM_M2_INTR_MAP_HP_APM_M2_INTR_MAP_Msk = 0x1f + + // HP_APM_M3_INTR_MAP: register description + // Position of HP_APM_M3_INTR_MAP field. + INTMTX_CORE0_HP_APM_M3_INTR_MAP_HP_APM_M3_INTR_MAP_Pos = 0x0 + // Bit mask of HP_APM_M3_INTR_MAP field. + INTMTX_CORE0_HP_APM_M3_INTR_MAP_HP_APM_M3_INTR_MAP_Msk = 0x1f + + // MSPI_INTR_MAP: register description + // Position of MSPI_INTR_MAP field. + INTMTX_CORE0_MSPI_INTR_MAP_MSPI_INTR_MAP_Pos = 0x0 + // Bit mask of MSPI_INTR_MAP field. + INTMTX_CORE0_MSPI_INTR_MAP_MSPI_INTR_MAP_Msk = 0x1f + + // I2S1_INTR_MAP: register description + // Position of I2S1_INTR_MAP field. + INTMTX_CORE0_I2S1_INTR_MAP_I2S1_INTR_MAP_Pos = 0x0 + // Bit mask of I2S1_INTR_MAP field. + INTMTX_CORE0_I2S1_INTR_MAP_I2S1_INTR_MAP_Msk = 0x1f + + // UHCI0_INTR_MAP: register description + // Position of UHCI0_INTR_MAP field. + INTMTX_CORE0_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Pos = 0x0 + // Bit mask of UHCI0_INTR_MAP field. + INTMTX_CORE0_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Msk = 0x1f + + // UART0_INTR_MAP: register description + // Position of UART0_INTR_MAP field. + INTMTX_CORE0_UART0_INTR_MAP_UART0_INTR_MAP_Pos = 0x0 + // Bit mask of UART0_INTR_MAP field. + INTMTX_CORE0_UART0_INTR_MAP_UART0_INTR_MAP_Msk = 0x1f + + // UART1_INTR_MAP: register description + // Position of UART1_INTR_MAP field. + INTMTX_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Pos = 0x0 + // Bit mask of UART1_INTR_MAP field. + INTMTX_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Msk = 0x1f + + // LEDC_INTR_MAP: register description + // Position of LEDC_INTR_MAP field. + INTMTX_CORE0_LEDC_INTR_MAP_LEDC_INTR_MAP_Pos = 0x0 + // Bit mask of LEDC_INTR_MAP field. + INTMTX_CORE0_LEDC_INTR_MAP_LEDC_INTR_MAP_Msk = 0x1f + + // CAN0_INTR_MAP: register description + // Position of CAN0_INTR_MAP field. + INTMTX_CORE0_CAN0_INTR_MAP_CAN0_INTR_MAP_Pos = 0x0 + // Bit mask of CAN0_INTR_MAP field. + INTMTX_CORE0_CAN0_INTR_MAP_CAN0_INTR_MAP_Msk = 0x1f + + // USB_INTR_MAP: register description + // Position of USB_INTR_MAP field. + INTMTX_CORE0_USB_INTR_MAP_USB_INTR_MAP_Pos = 0x0 + // Bit mask of USB_INTR_MAP field. + INTMTX_CORE0_USB_INTR_MAP_USB_INTR_MAP_Msk = 0x1f + + // RMT_INTR_MAP: register description + // Position of RMT_INTR_MAP field. + INTMTX_CORE0_RMT_INTR_MAP_RMT_INTR_MAP_Pos = 0x0 + // Bit mask of RMT_INTR_MAP field. + INTMTX_CORE0_RMT_INTR_MAP_RMT_INTR_MAP_Msk = 0x1f + + // I2C_EXT0_INTR_MAP: register description + // Position of I2C_EXT0_INTR_MAP field. + INTMTX_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_EXT0_INTR_MAP field. + INTMTX_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Msk = 0x1f + + // I2C_EXT1_INTR_MAP: register description + // Position of I2C_EXT1_INTR_MAP field. + INTMTX_CORE0_I2C_EXT1_INTR_MAP_I2C_EXT1_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_EXT1_INTR_MAP field. + INTMTX_CORE0_I2C_EXT1_INTR_MAP_I2C_EXT1_INTR_MAP_Msk = 0x1f + + // TG0_T0_INTR_MAP: register description + // Position of TG0_T0_INTR_MAP field. + INTMTX_CORE0_TG0_T0_INTR_MAP_TG0_T0_INTR_MAP_Pos = 0x0 + // Bit mask of TG0_T0_INTR_MAP field. + INTMTX_CORE0_TG0_T0_INTR_MAP_TG0_T0_INTR_MAP_Msk = 0x1f + + // TG0_WDT_INTR_MAP: register description + // Position of TG0_WDT_INTR_MAP field. + INTMTX_CORE0_TG0_WDT_INTR_MAP_TG0_WDT_INTR_MAP_Pos = 0x0 + // Bit mask of TG0_WDT_INTR_MAP field. + INTMTX_CORE0_TG0_WDT_INTR_MAP_TG0_WDT_INTR_MAP_Msk = 0x1f + + // TG1_T0_INTR_MAP: register description + // Position of TG1_T0_INTR_MAP field. + INTMTX_CORE0_TG1_T0_INTR_MAP_TG1_T0_INTR_MAP_Pos = 0x0 + // Bit mask of TG1_T0_INTR_MAP field. + INTMTX_CORE0_TG1_T0_INTR_MAP_TG1_T0_INTR_MAP_Msk = 0x1f + + // TG1_WDT_INTR_MAP: register description + // Position of TG1_WDT_INTR_MAP field. + INTMTX_CORE0_TG1_WDT_INTR_MAP_TG1_WDT_INTR_MAP_Pos = 0x0 + // Bit mask of TG1_WDT_INTR_MAP field. + INTMTX_CORE0_TG1_WDT_INTR_MAP_TG1_WDT_INTR_MAP_Msk = 0x1f + + // SYSTIMER_TARGET0_INTR_MAP: register description + // Position of SYSTIMER_TARGET0_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_SYSTIMER_TARGET0_INTR_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET0_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_SYSTIMER_TARGET0_INTR_MAP_Msk = 0x1f + + // SYSTIMER_TARGET1_INTR_MAP: register description + // Position of SYSTIMER_TARGET1_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_SYSTIMER_TARGET1_INTR_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET1_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_SYSTIMER_TARGET1_INTR_MAP_Msk = 0x1f + + // SYSTIMER_TARGET2_INTR_MAP: register description + // Position of SYSTIMER_TARGET2_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_SYSTIMER_TARGET2_INTR_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET2_INTR_MAP field. + INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_SYSTIMER_TARGET2_INTR_MAP_Msk = 0x1f + + // APB_ADC_INTR_MAP: register description + // Position of APB_ADC_INTR_MAP field. + INTMTX_CORE0_APB_ADC_INTR_MAP_APB_ADC_INTR_MAP_Pos = 0x0 + // Bit mask of APB_ADC_INTR_MAP field. + INTMTX_CORE0_APB_ADC_INTR_MAP_APB_ADC_INTR_MAP_Msk = 0x1f + + // PWM_INTR_MAP: register description + // Position of PWM_INTR_MAP field. + INTMTX_CORE0_PWM_INTR_MAP_PWM_INTR_MAP_Pos = 0x0 + // Bit mask of PWM_INTR_MAP field. + INTMTX_CORE0_PWM_INTR_MAP_PWM_INTR_MAP_Msk = 0x1f + + // PCNT_INTR_MAP: register description + // Position of PCNT_INTR_MAP field. + INTMTX_CORE0_PCNT_INTR_MAP_PCNT_INTR_MAP_Pos = 0x0 + // Bit mask of PCNT_INTR_MAP field. + INTMTX_CORE0_PCNT_INTR_MAP_PCNT_INTR_MAP_Msk = 0x1f + + // PARL_IO_TX_INTR_MAP: register description + // Position of PARL_IO_TX_INTR_MAP field. + INTMTX_CORE0_PARL_IO_TX_INTR_MAP_PARL_IO_TX_INTR_MAP_Pos = 0x0 + // Bit mask of PARL_IO_TX_INTR_MAP field. + INTMTX_CORE0_PARL_IO_TX_INTR_MAP_PARL_IO_TX_INTR_MAP_Msk = 0x1f + + // PARL_IO_RX_INTR_MAP: register description + // Position of PARL_IO_RX_INTR_MAP field. + INTMTX_CORE0_PARL_IO_RX_INTR_MAP_PARL_IO_RX_INTR_MAP_Pos = 0x0 + // Bit mask of PARL_IO_RX_INTR_MAP field. + INTMTX_CORE0_PARL_IO_RX_INTR_MAP_PARL_IO_RX_INTR_MAP_Msk = 0x1f + + // DMA_IN_CH0_INTR_MAP: register description + // Position of DMA_IN_CH0_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_DMA_IN_CH0_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH0_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_DMA_IN_CH0_INTR_MAP_Msk = 0x1f + + // DMA_IN_CH1_INTR_MAP: register description + // Position of DMA_IN_CH1_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_DMA_IN_CH1_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH1_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_DMA_IN_CH1_INTR_MAP_Msk = 0x1f + + // DMA_IN_CH2_INTR_MAP: register description + // Position of DMA_IN_CH2_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_DMA_IN_CH2_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH2_INTR_MAP field. + INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_DMA_IN_CH2_INTR_MAP_Msk = 0x1f + + // DMA_OUT_CH0_INTR_MAP: register description + // Position of DMA_OUT_CH0_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_DMA_OUT_CH0_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH0_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_DMA_OUT_CH0_INTR_MAP_Msk = 0x1f + + // DMA_OUT_CH1_INTR_MAP: register description + // Position of DMA_OUT_CH1_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_DMA_OUT_CH1_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH1_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_DMA_OUT_CH1_INTR_MAP_Msk = 0x1f + + // DMA_OUT_CH2_INTR_MAP: register description + // Position of DMA_OUT_CH2_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_DMA_OUT_CH2_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH2_INTR_MAP field. + INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_DMA_OUT_CH2_INTR_MAP_Msk = 0x1f + + // GPSPI2_INTR_MAP: register description + // Position of GPSPI2_INTR_MAP field. + INTMTX_CORE0_GPSPI2_INTR_MAP_GPSPI2_INTR_MAP_Pos = 0x0 + // Bit mask of GPSPI2_INTR_MAP field. + INTMTX_CORE0_GPSPI2_INTR_MAP_GPSPI2_INTR_MAP_Msk = 0x1f + + // AES_INTR_MAP: register description + // Position of AES_INTR_MAP field. + INTMTX_CORE0_AES_INTR_MAP_AES_INTR_MAP_Pos = 0x0 + // Bit mask of AES_INTR_MAP field. + INTMTX_CORE0_AES_INTR_MAP_AES_INTR_MAP_Msk = 0x1f + + // SHA_INTR_MAP: register description + // Position of SHA_INTR_MAP field. + INTMTX_CORE0_SHA_INTR_MAP_SHA_INTR_MAP_Pos = 0x0 + // Bit mask of SHA_INTR_MAP field. + INTMTX_CORE0_SHA_INTR_MAP_SHA_INTR_MAP_Msk = 0x1f + + // RSA_INTR_MAP: register description + // Position of RSA_INTR_MAP field. + INTMTX_CORE0_RSA_INTR_MAP_RSA_INTR_MAP_Pos = 0x0 + // Bit mask of RSA_INTR_MAP field. + INTMTX_CORE0_RSA_INTR_MAP_RSA_INTR_MAP_Msk = 0x1f + + // ECC_INTR_MAP: register description + // Position of ECC_INTR_MAP field. + INTMTX_CORE0_ECC_INTR_MAP_ECC_INTR_MAP_Pos = 0x0 + // Bit mask of ECC_INTR_MAP field. + INTMTX_CORE0_ECC_INTR_MAP_ECC_INTR_MAP_Msk = 0x1f + + // ECDSA_INTR_MAP: register description + // Position of ECDSA_INTR_MAP field. + INTMTX_CORE0_ECDSA_INTR_MAP_ECDSA_INTR_MAP_Pos = 0x0 + // Bit mask of ECDSA_INTR_MAP field. + INTMTX_CORE0_ECDSA_INTR_MAP_ECDSA_INTR_MAP_Msk = 0x1f + + // INTR_STATUS_REG_0: register description + // Position of INTR_STATUS_0 field. + INTMTX_CORE0_INTR_STATUS_REG_0_INTR_STATUS_0_Pos = 0x0 + // Bit mask of INTR_STATUS_0 field. + INTMTX_CORE0_INTR_STATUS_REG_0_INTR_STATUS_0_Msk = 0xffffffff + + // INTR_STATUS_REG_1: register description + // Position of INTR_STATUS_1 field. + INTMTX_CORE0_INTR_STATUS_REG_1_INTR_STATUS_1_Pos = 0x0 + // Bit mask of INTR_STATUS_1 field. + INTMTX_CORE0_INTR_STATUS_REG_1_INTR_STATUS_1_Msk = 0xffffffff + + // INT_STATUS_REG_2: register description + // Position of INT_STATUS_2 field. + INTMTX_CORE0_INT_STATUS_REG_2_INT_STATUS_2_Pos = 0x0 + // Bit mask of INT_STATUS_2 field. + INTMTX_CORE0_INT_STATUS_REG_2_INT_STATUS_2_Msk = 0xffffffff + + // CLOCK_GATE: register description + // Position of REG_CLK_EN field. + INTMTX_CORE0_CLOCK_GATE_REG_CLK_EN_Pos = 0x0 + // Bit mask of REG_CLK_EN field. + INTMTX_CORE0_CLOCK_GATE_REG_CLK_EN_Msk = 0x1 + // Bit REG_CLK_EN. + INTMTX_CORE0_CLOCK_GATE_REG_CLK_EN = 0x1 + + // INTERRUPT_REG_DATE: register description + // Position of INTERRUPT_REG_DATE field. + INTMTX_CORE0_INTERRUPT_REG_DATE_INTERRUPT_REG_DATE_Pos = 0x0 + // Bit mask of INTERRUPT_REG_DATE field. + INTMTX_CORE0_INTERRUPT_REG_DATE_INTERRUPT_REG_DATE_Msk = 0xfffffff +) + +// Constants for INTPRI: INTPRI Peripheral +const ( + // CPU_INT_ENABLE: register description + // Position of CPU_INT_ENABLE field. + INTPRI_CPU_INT_ENABLE_CPU_INT_ENABLE_Pos = 0x0 + // Bit mask of CPU_INT_ENABLE field. + INTPRI_CPU_INT_ENABLE_CPU_INT_ENABLE_Msk = 0xffffffff + + // CPU_INT_TYPE: register description + // Position of CPU_INT_TYPE field. + INTPRI_CPU_INT_TYPE_CPU_INT_TYPE_Pos = 0x0 + // Bit mask of CPU_INT_TYPE field. + INTPRI_CPU_INT_TYPE_CPU_INT_TYPE_Msk = 0xffffffff + + // CPU_INT_EIP_STATUS: register description + // Position of CPU_INT_EIP_STATUS field. + INTPRI_CPU_INT_EIP_STATUS_CPU_INT_EIP_STATUS_Pos = 0x0 + // Bit mask of CPU_INT_EIP_STATUS field. + INTPRI_CPU_INT_EIP_STATUS_CPU_INT_EIP_STATUS_Msk = 0xffffffff + + // CPU_INT_PRI_0: register description + // Position of CPU_PRI_0_MAP field. + INTPRI_CPU_INT_PRI_0_CPU_PRI_0_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_0_MAP field. + INTPRI_CPU_INT_PRI_0_CPU_PRI_0_MAP_Msk = 0xf + + // CPU_INT_PRI_1: register description + // Position of CPU_PRI_1_MAP field. + INTPRI_CPU_INT_PRI_1_CPU_PRI_1_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_1_MAP field. + INTPRI_CPU_INT_PRI_1_CPU_PRI_1_MAP_Msk = 0xf + + // CPU_INT_PRI_2: register description + // Position of CPU_PRI_2_MAP field. + INTPRI_CPU_INT_PRI_2_CPU_PRI_2_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_2_MAP field. + INTPRI_CPU_INT_PRI_2_CPU_PRI_2_MAP_Msk = 0xf + + // CPU_INT_PRI_3: register description + // Position of CPU_PRI_3_MAP field. + INTPRI_CPU_INT_PRI_3_CPU_PRI_3_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_3_MAP field. + INTPRI_CPU_INT_PRI_3_CPU_PRI_3_MAP_Msk = 0xf + + // CPU_INT_PRI_4: register description + // Position of CPU_PRI_4_MAP field. + INTPRI_CPU_INT_PRI_4_CPU_PRI_4_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_4_MAP field. + INTPRI_CPU_INT_PRI_4_CPU_PRI_4_MAP_Msk = 0xf + + // CPU_INT_PRI_5: register description + // Position of CPU_PRI_5_MAP field. + INTPRI_CPU_INT_PRI_5_CPU_PRI_5_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_5_MAP field. + INTPRI_CPU_INT_PRI_5_CPU_PRI_5_MAP_Msk = 0xf + + // CPU_INT_PRI_6: register description + // Position of CPU_PRI_6_MAP field. + INTPRI_CPU_INT_PRI_6_CPU_PRI_6_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_6_MAP field. + INTPRI_CPU_INT_PRI_6_CPU_PRI_6_MAP_Msk = 0xf + + // CPU_INT_PRI_7: register description + // Position of CPU_PRI_7_MAP field. + INTPRI_CPU_INT_PRI_7_CPU_PRI_7_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_7_MAP field. + INTPRI_CPU_INT_PRI_7_CPU_PRI_7_MAP_Msk = 0xf + + // CPU_INT_PRI_8: register description + // Position of CPU_PRI_8_MAP field. + INTPRI_CPU_INT_PRI_8_CPU_PRI_8_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_8_MAP field. + INTPRI_CPU_INT_PRI_8_CPU_PRI_8_MAP_Msk = 0xf + + // CPU_INT_PRI_9: register description + // Position of CPU_PRI_9_MAP field. + INTPRI_CPU_INT_PRI_9_CPU_PRI_9_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_9_MAP field. + INTPRI_CPU_INT_PRI_9_CPU_PRI_9_MAP_Msk = 0xf + + // CPU_INT_PRI_10: register description + // Position of CPU_PRI_10_MAP field. + INTPRI_CPU_INT_PRI_10_CPU_PRI_10_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_10_MAP field. + INTPRI_CPU_INT_PRI_10_CPU_PRI_10_MAP_Msk = 0xf + + // CPU_INT_PRI_11: register description + // Position of CPU_PRI_11_MAP field. + INTPRI_CPU_INT_PRI_11_CPU_PRI_11_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_11_MAP field. + INTPRI_CPU_INT_PRI_11_CPU_PRI_11_MAP_Msk = 0xf + + // CPU_INT_PRI_12: register description + // Position of CPU_PRI_12_MAP field. + INTPRI_CPU_INT_PRI_12_CPU_PRI_12_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_12_MAP field. + INTPRI_CPU_INT_PRI_12_CPU_PRI_12_MAP_Msk = 0xf + + // CPU_INT_PRI_13: register description + // Position of CPU_PRI_13_MAP field. + INTPRI_CPU_INT_PRI_13_CPU_PRI_13_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_13_MAP field. + INTPRI_CPU_INT_PRI_13_CPU_PRI_13_MAP_Msk = 0xf + + // CPU_INT_PRI_14: register description + // Position of CPU_PRI_14_MAP field. + INTPRI_CPU_INT_PRI_14_CPU_PRI_14_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_14_MAP field. + INTPRI_CPU_INT_PRI_14_CPU_PRI_14_MAP_Msk = 0xf + + // CPU_INT_PRI_15: register description + // Position of CPU_PRI_15_MAP field. + INTPRI_CPU_INT_PRI_15_CPU_PRI_15_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_15_MAP field. + INTPRI_CPU_INT_PRI_15_CPU_PRI_15_MAP_Msk = 0xf + + // CPU_INT_PRI_16: register description + // Position of CPU_PRI_16_MAP field. + INTPRI_CPU_INT_PRI_16_CPU_PRI_16_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_16_MAP field. + INTPRI_CPU_INT_PRI_16_CPU_PRI_16_MAP_Msk = 0xf + + // CPU_INT_PRI_17: register description + // Position of CPU_PRI_17_MAP field. + INTPRI_CPU_INT_PRI_17_CPU_PRI_17_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_17_MAP field. + INTPRI_CPU_INT_PRI_17_CPU_PRI_17_MAP_Msk = 0xf + + // CPU_INT_PRI_18: register description + // Position of CPU_PRI_18_MAP field. + INTPRI_CPU_INT_PRI_18_CPU_PRI_18_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_18_MAP field. + INTPRI_CPU_INT_PRI_18_CPU_PRI_18_MAP_Msk = 0xf + + // CPU_INT_PRI_19: register description + // Position of CPU_PRI_19_MAP field. + INTPRI_CPU_INT_PRI_19_CPU_PRI_19_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_19_MAP field. + INTPRI_CPU_INT_PRI_19_CPU_PRI_19_MAP_Msk = 0xf + + // CPU_INT_PRI_20: register description + // Position of CPU_PRI_20_MAP field. + INTPRI_CPU_INT_PRI_20_CPU_PRI_20_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_20_MAP field. + INTPRI_CPU_INT_PRI_20_CPU_PRI_20_MAP_Msk = 0xf + + // CPU_INT_PRI_21: register description + // Position of CPU_PRI_21_MAP field. + INTPRI_CPU_INT_PRI_21_CPU_PRI_21_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_21_MAP field. + INTPRI_CPU_INT_PRI_21_CPU_PRI_21_MAP_Msk = 0xf + + // CPU_INT_PRI_22: register description + // Position of CPU_PRI_22_MAP field. + INTPRI_CPU_INT_PRI_22_CPU_PRI_22_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_22_MAP field. + INTPRI_CPU_INT_PRI_22_CPU_PRI_22_MAP_Msk = 0xf + + // CPU_INT_PRI_23: register description + // Position of CPU_PRI_23_MAP field. + INTPRI_CPU_INT_PRI_23_CPU_PRI_23_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_23_MAP field. + INTPRI_CPU_INT_PRI_23_CPU_PRI_23_MAP_Msk = 0xf + + // CPU_INT_PRI_24: register description + // Position of CPU_PRI_24_MAP field. + INTPRI_CPU_INT_PRI_24_CPU_PRI_24_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_24_MAP field. + INTPRI_CPU_INT_PRI_24_CPU_PRI_24_MAP_Msk = 0xf + + // CPU_INT_PRI_25: register description + // Position of CPU_PRI_25_MAP field. + INTPRI_CPU_INT_PRI_25_CPU_PRI_25_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_25_MAP field. + INTPRI_CPU_INT_PRI_25_CPU_PRI_25_MAP_Msk = 0xf + + // CPU_INT_PRI_26: register description + // Position of CPU_PRI_26_MAP field. + INTPRI_CPU_INT_PRI_26_CPU_PRI_26_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_26_MAP field. + INTPRI_CPU_INT_PRI_26_CPU_PRI_26_MAP_Msk = 0xf + + // CPU_INT_PRI_27: register description + // Position of CPU_PRI_27_MAP field. + INTPRI_CPU_INT_PRI_27_CPU_PRI_27_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_27_MAP field. + INTPRI_CPU_INT_PRI_27_CPU_PRI_27_MAP_Msk = 0xf + + // CPU_INT_PRI_28: register description + // Position of CPU_PRI_28_MAP field. + INTPRI_CPU_INT_PRI_28_CPU_PRI_28_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_28_MAP field. + INTPRI_CPU_INT_PRI_28_CPU_PRI_28_MAP_Msk = 0xf + + // CPU_INT_PRI_29: register description + // Position of CPU_PRI_29_MAP field. + INTPRI_CPU_INT_PRI_29_CPU_PRI_29_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_29_MAP field. + INTPRI_CPU_INT_PRI_29_CPU_PRI_29_MAP_Msk = 0xf + + // CPU_INT_PRI_30: register description + // Position of CPU_PRI_30_MAP field. + INTPRI_CPU_INT_PRI_30_CPU_PRI_30_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_30_MAP field. + INTPRI_CPU_INT_PRI_30_CPU_PRI_30_MAP_Msk = 0xf + + // CPU_INT_PRI_31: register description + // Position of CPU_PRI_31_MAP field. + INTPRI_CPU_INT_PRI_31_CPU_PRI_31_MAP_Pos = 0x0 + // Bit mask of CPU_PRI_31_MAP field. + INTPRI_CPU_INT_PRI_31_CPU_PRI_31_MAP_Msk = 0xf + + // CPU_INT_THRESH: register description + // Position of CPU_INT_THRESH field. + INTPRI_CPU_INT_THRESH_CPU_INT_THRESH_Pos = 0x0 + // Bit mask of CPU_INT_THRESH field. + INTPRI_CPU_INT_THRESH_CPU_INT_THRESH_Msk = 0xff + + // CPU_INTR_FROM_CPU_0: register description + // Position of CPU_INTR_FROM_CPU_0 field. + INTPRI_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0 field. + INTPRI_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_0. + INTPRI_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0 = 0x1 + + // CPU_INTR_FROM_CPU_1: register description + // Position of CPU_INTR_FROM_CPU_1 field. + INTPRI_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1 field. + INTPRI_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_1. + INTPRI_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1 = 0x1 + + // CPU_INTR_FROM_CPU_2: register description + // Position of CPU_INTR_FROM_CPU_2 field. + INTPRI_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2 field. + INTPRI_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_2. + INTPRI_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2 = 0x1 + + // CPU_INTR_FROM_CPU_3: register description + // Position of CPU_INTR_FROM_CPU_3 field. + INTPRI_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3 field. + INTPRI_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_3. + INTPRI_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3 = 0x1 + + // DATE: register description + // Position of DATE field. + INTPRI_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + INTPRI_DATE_DATE_Msk = 0xfffffff + + // CLOCK_GATE: register description + // Position of CLK_EN field. + INTPRI_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + INTPRI_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + INTPRI_CLOCK_GATE_CLK_EN = 0x1 + + // CPU_INT_CLEAR: register description + // Position of CPU_INT_CLEAR field. + INTPRI_CPU_INT_CLEAR_CPU_INT_CLEAR_Pos = 0x0 + // Bit mask of CPU_INT_CLEAR field. + INTPRI_CPU_INT_CLEAR_CPU_INT_CLEAR_Msk = 0xffffffff + + // RND_ECO: redcy eco register. + // Position of REDCY_ENA field. + INTPRI_RND_ECO_REDCY_ENA_Pos = 0x0 + // Bit mask of REDCY_ENA field. + INTPRI_RND_ECO_REDCY_ENA_Msk = 0x1 + // Bit REDCY_ENA. + INTPRI_RND_ECO_REDCY_ENA = 0x1 + // Position of REDCY_RESULT field. + INTPRI_RND_ECO_REDCY_RESULT_Pos = 0x1 + // Bit mask of REDCY_RESULT field. + INTPRI_RND_ECO_REDCY_RESULT_Msk = 0x2 + // Bit REDCY_RESULT. + INTPRI_RND_ECO_REDCY_RESULT = 0x2 + + // RND_ECO_LOW: redcy eco low register. + // Position of REDCY_LOW field. + INTPRI_RND_ECO_LOW_REDCY_LOW_Pos = 0x0 + // Bit mask of REDCY_LOW field. + INTPRI_RND_ECO_LOW_REDCY_LOW_Msk = 0xffffffff + + // RND_ECO_HIGH: redcy eco high register. + // Position of REDCY_HIGH field. + INTPRI_RND_ECO_HIGH_REDCY_HIGH_Pos = 0x0 + // Bit mask of REDCY_HIGH field. + INTPRI_RND_ECO_HIGH_REDCY_HIGH_Msk = 0xffffffff +) + +// Constants for IO_MUX: Input/Output Multiplexer +const ( + // PIN_CTRL: Clock Output Configuration Register + // Position of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Pos = 0x0 + // Bit mask of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Msk = 0x1f + // Position of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Pos = 0x5 + // Bit mask of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Msk = 0x3e0 + // Position of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Pos = 0xa + // Bit mask of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Msk = 0x7c00 + + // GPIO0: IO MUX Configure Register for pad GPIO0 + // Position of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO_MCU_IE = 0x10 + // Position of MCU_DRV field. + IO_MUX_GPIO_MCU_DRV_Pos = 0x5 + // Bit mask of MCU_DRV field. + IO_MUX_GPIO_MCU_DRV_Msk = 0x60 + // Position of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO_FILTER_EN = 0x8000 + // Position of HYS_EN field. + IO_MUX_GPIO_HYS_EN_Pos = 0x10 + // Bit mask of HYS_EN field. + IO_MUX_GPIO_HYS_EN_Msk = 0x10000 + // Bit HYS_EN. + IO_MUX_GPIO_HYS_EN = 0x10000 + // Position of HYS_SEL field. + IO_MUX_GPIO_HYS_SEL_Pos = 0x11 + // Bit mask of HYS_SEL field. + IO_MUX_GPIO_HYS_SEL_Msk = 0x20000 + // Bit HYS_SEL. + IO_MUX_GPIO_HYS_SEL = 0x20000 + + // MODEM_DIAG_EN: GPIO MATRIX Configure Register for modem diag + // Position of MODEM_DIAG_EN field. + IO_MUX_MODEM_DIAG_EN_MODEM_DIAG_EN_Pos = 0x0 + // Bit mask of MODEM_DIAG_EN field. + IO_MUX_MODEM_DIAG_EN_MODEM_DIAG_EN_Msk = 0xffffffff + + // DATE: IO MUX Version Control Register + // Position of REG_DATE field. + IO_MUX_DATE_REG_DATE_Pos = 0x0 + // Bit mask of REG_DATE field. + IO_MUX_DATE_REG_DATE_Msk = 0xfffffff +) + +// Constants for LEDC: LED Control PWM (Pulse Width Modulation) +const ( + // CH0_CONF0: Configuration register 0 for channel %s + // Position of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Pos = 0x0 + // Bit mask of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Msk = 0x3 + // Position of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Pos = 0x2 + // Bit mask of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Msk = 0x4 + // Bit SIG_OUT_EN. + LEDC_CH_CONF0_SIG_OUT_EN = 0x4 + // Position of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Pos = 0x3 + // Bit mask of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Msk = 0x8 + // Bit IDLE_LV. + LEDC_CH_CONF0_IDLE_LV = 0x8 + // Position of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Pos = 0x4 + // Bit mask of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Msk = 0x10 + // Bit PARA_UP. + LEDC_CH_CONF0_PARA_UP = 0x10 + // Position of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Pos = 0x5 + // Bit mask of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Msk = 0x7fe0 + // Position of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Pos = 0xf + // Bit mask of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Msk = 0x8000 + // Bit OVF_CNT_EN. + LEDC_CH_CONF0_OVF_CNT_EN = 0x8000 + // Position of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Pos = 0x10 + // Bit mask of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Msk = 0x10000 + // Bit OVF_CNT_RESET. + LEDC_CH_CONF0_OVF_CNT_RESET = 0x10000 + + // CH0_HPOINT: High point register for channel %s + // Position of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Pos = 0x0 + // Bit mask of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Msk = 0xfffff + + // CH0_DUTY: Initial duty cycle for channel %s + // Position of DUTY field. + LEDC_CH_DUTY_DUTY_Pos = 0x0 + // Bit mask of DUTY field. + LEDC_CH_DUTY_DUTY_Msk = 0x1ffffff + + // CH0_CONF1: Configuration register 1 for channel %s + // Position of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Pos = 0x1f + // Bit mask of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Msk = 0x80000000 + // Bit DUTY_START. + LEDC_CH_CONF1_DUTY_START = 0x80000000 + + // CH0_DUTY_R: Current duty cycle for channel %s + // Position of DUTY_CH_R field. + LEDC_CH_DUTY_R_DUTY_CH_R_Pos = 0x0 + // Bit mask of DUTY_CH_R field. + LEDC_CH_DUTY_R_DUTY_CH_R_Msk = 0x1ffffff + + // TIMER0_CONF: Timer %s configuration + // Position of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Pos = 0x0 + // Bit mask of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Msk = 0x1f + // Position of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Pos = 0x5 + // Bit mask of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Msk = 0x7fffe0 + // Position of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Pos = 0x17 + // Bit mask of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Msk = 0x800000 + // Bit PAUSE. + LEDC_TIMER_CONF_PAUSE = 0x800000 + // Position of RST field. + LEDC_TIMER_CONF_RST_Pos = 0x18 + // Bit mask of RST field. + LEDC_TIMER_CONF_RST_Msk = 0x1000000 + // Bit RST. + LEDC_TIMER_CONF_RST = 0x1000000 + // Position of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Pos = 0x19 + // Bit mask of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Msk = 0x2000000 + // Bit TICK_SEL. + LEDC_TIMER_CONF_TICK_SEL = 0x2000000 + // Position of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Pos = 0x1a + // Bit mask of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Msk = 0x4000000 + // Bit PARA_UP. + LEDC_TIMER_CONF_PARA_UP = 0x4000000 + + // TIMER0_VALUE: Timer %s current counter value + // Position of TIMER_CNT field. + LEDC_TIMER_VALUE_TIMER_CNT_Pos = 0x0 + // Bit mask of TIMER_CNT field. + LEDC_TIMER_VALUE_TIMER_CNT_Msk = 0xfffff + + // INT_RAW: Raw interrupt status + // Position of TIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Msk = 0x1 + // Bit TIMER0_OVF_INT_RAW. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW = 0x1 + // Position of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Msk = 0x2 + // Bit TIMER1_OVF_INT_RAW. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW = 0x2 + // Position of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Msk = 0x4 + // Bit TIMER2_OVF_INT_RAW. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW = 0x4 + // Position of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Msk = 0x8 + // Bit TIMER3_OVF_INT_RAW. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW = 0x200 + // Position of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW = 0x1000 + // Position of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW = 0x2000 + // Position of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW = 0x4000 + // Position of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW = 0x8000 + // Position of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW = 0x10000 + // Position of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW = 0x20000 + + // INT_ST: Masked interrupt status + // Position of TIMER0_OVF_INT_ST field. + LEDC_INT_ST_TIMER0_OVF_INT_ST_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_ST field. + LEDC_INT_ST_TIMER0_OVF_INT_ST_Msk = 0x1 + // Bit TIMER0_OVF_INT_ST. + LEDC_INT_ST_TIMER0_OVF_INT_ST = 0x1 + // Position of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Msk = 0x2 + // Bit TIMER1_OVF_INT_ST. + LEDC_INT_ST_TIMER1_OVF_INT_ST = 0x2 + // Position of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Msk = 0x4 + // Bit TIMER2_OVF_INT_ST. + LEDC_INT_ST_TIMER2_OVF_INT_ST = 0x4 + // Position of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Msk = 0x8 + // Bit TIMER3_OVF_INT_ST. + LEDC_INT_ST_TIMER3_OVF_INT_ST = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST = 0x200 + // Position of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_ST. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST = 0x1000 + // Position of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_ST. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST = 0x2000 + // Position of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_ST. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST = 0x4000 + // Position of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_ST. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST = 0x8000 + // Position of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_ST. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST = 0x10000 + // Position of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_ST. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST = 0x20000 + + // INT_ENA: Interrupt enable bits + // Position of TIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Msk = 0x1 + // Bit TIMER0_OVF_INT_ENA. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA = 0x1 + // Position of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Msk = 0x2 + // Bit TIMER1_OVF_INT_ENA. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA = 0x2 + // Position of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Msk = 0x4 + // Bit TIMER2_OVF_INT_ENA. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA = 0x4 + // Position of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Msk = 0x8 + // Bit TIMER3_OVF_INT_ENA. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA = 0x200 + // Position of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA = 0x1000 + // Position of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA = 0x2000 + // Position of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA = 0x4000 + // Position of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA = 0x8000 + // Position of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA = 0x10000 + // Position of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA = 0x20000 + + // INT_CLR: Interrupt clear bits + // Position of TIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Msk = 0x1 + // Bit TIMER0_OVF_INT_CLR. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR = 0x1 + // Position of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Msk = 0x2 + // Bit TIMER1_OVF_INT_CLR. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR = 0x2 + // Position of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Msk = 0x4 + // Bit TIMER2_OVF_INT_CLR. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR = 0x4 + // Position of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Msk = 0x8 + // Bit TIMER3_OVF_INT_CLR. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR = 0x200 + // Position of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR = 0x1000 + // Position of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR = 0x2000 + // Position of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR = 0x4000 + // Position of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR = 0x8000 + // Position of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR = 0x10000 + // Position of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR = 0x20000 + + // CH0_GAMMA_WR: Ledc ch%s gamma ram write register. + // Position of CH_GAMMA_DUTY_INC field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_INC_Pos = 0x0 + // Bit mask of CH_GAMMA_DUTY_INC field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_INC_Msk = 0x1 + // Bit CH_GAMMA_DUTY_INC. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_INC = 0x1 + // Position of CH_GAMMA_DUTY_CYCLE field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_CYCLE_Pos = 0x1 + // Bit mask of CH_GAMMA_DUTY_CYCLE field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_CYCLE_Msk = 0x7fe + // Position of CH_GAMMA_SCALE field. + LEDC_CH_GAMMA_WR_CH_GAMMA_SCALE_Pos = 0xb + // Bit mask of CH_GAMMA_SCALE field. + LEDC_CH_GAMMA_WR_CH_GAMMA_SCALE_Msk = 0x1ff800 + // Position of CH_GAMMA_DUTY_NUM field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_NUM_Pos = 0x15 + // Bit mask of CH_GAMMA_DUTY_NUM field. + LEDC_CH_GAMMA_WR_CH_GAMMA_DUTY_NUM_Msk = 0x7fe00000 + + // CH0_GAMMA_WR_ADDR: Ledc ch%s gamma ram write address register. + // Position of CH_GAMMA_WR_ADDR field. + LEDC_CH_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR_Pos = 0x0 + // Bit mask of CH_GAMMA_WR_ADDR field. + LEDC_CH_GAMMA_WR_ADDR_CH_GAMMA_WR_ADDR_Msk = 0xf + + // CH0_GAMMA_RD_ADDR: Ledc ch%s gamma ram read address register. + // Position of CH_GAMMA_RD_ADDR field. + LEDC_CH_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR_Pos = 0x0 + // Bit mask of CH_GAMMA_RD_ADDR field. + LEDC_CH_GAMMA_RD_ADDR_CH_GAMMA_RD_ADDR_Msk = 0xf + + // CH0_GAMMA_RD_DATA: Ledc ch%s gamma ram read data register. + // Position of CH_GAMMA_RD_DATA field. + LEDC_CH_GAMMA_RD_DATA_CH_GAMMA_RD_DATA_Pos = 0x0 + // Bit mask of CH_GAMMA_RD_DATA field. + LEDC_CH_GAMMA_RD_DATA_CH_GAMMA_RD_DATA_Msk = 0x7fffffff + + // CH0_GAMMA_CONF: Ledc ch%s gamma config register. + // Position of CH_GAMMA_ENTRY_NUM field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_ENTRY_NUM_Pos = 0x0 + // Bit mask of CH_GAMMA_ENTRY_NUM field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_ENTRY_NUM_Msk = 0x1f + // Position of CH_GAMMA_PAUSE field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_PAUSE_Pos = 0x5 + // Bit mask of CH_GAMMA_PAUSE field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_PAUSE_Msk = 0x20 + // Bit CH_GAMMA_PAUSE. + LEDC_CH_GAMMA_CONF_CH_GAMMA_PAUSE = 0x20 + // Position of CH_GAMMA_RESUME field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_RESUME_Pos = 0x6 + // Bit mask of CH_GAMMA_RESUME field. + LEDC_CH_GAMMA_CONF_CH_GAMMA_RESUME_Msk = 0x40 + // Bit CH_GAMMA_RESUME. + LEDC_CH_GAMMA_CONF_CH_GAMMA_RESUME = 0x40 + + // EVT_TASK_EN0: Ledc event task enable bit register0. + // Position of EVT_DUTY_CHNG_END_CH0_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN_Pos = 0x0 + // Bit mask of EVT_DUTY_CHNG_END_CH0_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN_Msk = 0x1 + // Bit EVT_DUTY_CHNG_END_CH0_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN = 0x1 + // Position of EVT_DUTY_CHNG_END_CH1_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN_Pos = 0x1 + // Bit mask of EVT_DUTY_CHNG_END_CH1_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN_Msk = 0x2 + // Bit EVT_DUTY_CHNG_END_CH1_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN = 0x2 + // Position of EVT_DUTY_CHNG_END_CH2_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN_Pos = 0x2 + // Bit mask of EVT_DUTY_CHNG_END_CH2_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN_Msk = 0x4 + // Bit EVT_DUTY_CHNG_END_CH2_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN = 0x4 + // Position of EVT_DUTY_CHNG_END_CH3_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN_Pos = 0x3 + // Bit mask of EVT_DUTY_CHNG_END_CH3_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN_Msk = 0x8 + // Bit EVT_DUTY_CHNG_END_CH3_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN = 0x8 + // Position of EVT_DUTY_CHNG_END_CH4_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN_Pos = 0x4 + // Bit mask of EVT_DUTY_CHNG_END_CH4_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN_Msk = 0x10 + // Bit EVT_DUTY_CHNG_END_CH4_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN = 0x10 + // Position of EVT_DUTY_CHNG_END_CH5_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN_Pos = 0x5 + // Bit mask of EVT_DUTY_CHNG_END_CH5_EN field. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN_Msk = 0x20 + // Bit EVT_DUTY_CHNG_END_CH5_EN. + LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN = 0x20 + // Position of EVT_OVF_CNT_PLS_CH0_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN_Pos = 0x8 + // Bit mask of EVT_OVF_CNT_PLS_CH0_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN_Msk = 0x100 + // Bit EVT_OVF_CNT_PLS_CH0_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN = 0x100 + // Position of EVT_OVF_CNT_PLS_CH1_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN_Pos = 0x9 + // Bit mask of EVT_OVF_CNT_PLS_CH1_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN_Msk = 0x200 + // Bit EVT_OVF_CNT_PLS_CH1_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN = 0x200 + // Position of EVT_OVF_CNT_PLS_CH2_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN_Pos = 0xa + // Bit mask of EVT_OVF_CNT_PLS_CH2_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN_Msk = 0x400 + // Bit EVT_OVF_CNT_PLS_CH2_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN = 0x400 + // Position of EVT_OVF_CNT_PLS_CH3_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN_Pos = 0xb + // Bit mask of EVT_OVF_CNT_PLS_CH3_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN_Msk = 0x800 + // Bit EVT_OVF_CNT_PLS_CH3_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN = 0x800 + // Position of EVT_OVF_CNT_PLS_CH4_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN_Pos = 0xc + // Bit mask of EVT_OVF_CNT_PLS_CH4_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN_Msk = 0x1000 + // Bit EVT_OVF_CNT_PLS_CH4_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN = 0x1000 + // Position of EVT_OVF_CNT_PLS_CH5_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN_Pos = 0xd + // Bit mask of EVT_OVF_CNT_PLS_CH5_EN field. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN_Msk = 0x2000 + // Bit EVT_OVF_CNT_PLS_CH5_EN. + LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN = 0x2000 + // Position of EVT_TIME_OVF_TIMER0_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN_Pos = 0x10 + // Bit mask of EVT_TIME_OVF_TIMER0_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN_Msk = 0x10000 + // Bit EVT_TIME_OVF_TIMER0_EN. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN = 0x10000 + // Position of EVT_TIME_OVF_TIMER1_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN_Pos = 0x11 + // Bit mask of EVT_TIME_OVF_TIMER1_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN_Msk = 0x20000 + // Bit EVT_TIME_OVF_TIMER1_EN. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN = 0x20000 + // Position of EVT_TIME_OVF_TIMER2_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN_Pos = 0x12 + // Bit mask of EVT_TIME_OVF_TIMER2_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN_Msk = 0x40000 + // Bit EVT_TIME_OVF_TIMER2_EN. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN = 0x40000 + // Position of EVT_TIME_OVF_TIMER3_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN_Pos = 0x13 + // Bit mask of EVT_TIME_OVF_TIMER3_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN_Msk = 0x80000 + // Bit EVT_TIME_OVF_TIMER3_EN. + LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN = 0x80000 + // Position of EVT_TIME0_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME0_CMP_EN_Pos = 0x14 + // Bit mask of EVT_TIME0_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME0_CMP_EN_Msk = 0x100000 + // Bit EVT_TIME0_CMP_EN. + LEDC_EVT_TASK_EN0_EVT_TIME0_CMP_EN = 0x100000 + // Position of EVT_TIME1_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME1_CMP_EN_Pos = 0x15 + // Bit mask of EVT_TIME1_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME1_CMP_EN_Msk = 0x200000 + // Bit EVT_TIME1_CMP_EN. + LEDC_EVT_TASK_EN0_EVT_TIME1_CMP_EN = 0x200000 + // Position of EVT_TIME2_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME2_CMP_EN_Pos = 0x16 + // Bit mask of EVT_TIME2_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME2_CMP_EN_Msk = 0x400000 + // Bit EVT_TIME2_CMP_EN. + LEDC_EVT_TASK_EN0_EVT_TIME2_CMP_EN = 0x400000 + // Position of EVT_TIME3_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME3_CMP_EN_Pos = 0x17 + // Bit mask of EVT_TIME3_CMP_EN field. + LEDC_EVT_TASK_EN0_EVT_TIME3_CMP_EN_Msk = 0x800000 + // Bit EVT_TIME3_CMP_EN. + LEDC_EVT_TASK_EN0_EVT_TIME3_CMP_EN = 0x800000 + // Position of TASK_DUTY_SCALE_UPDATE_CH0_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN_Pos = 0x18 + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH0_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN_Msk = 0x1000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH0_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN = 0x1000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH1_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN_Pos = 0x19 + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH1_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN_Msk = 0x2000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH1_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN = 0x2000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH2_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN_Pos = 0x1a + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH2_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN_Msk = 0x4000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH2_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN = 0x4000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH3_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN_Pos = 0x1b + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH3_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN_Msk = 0x8000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH3_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN = 0x8000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH4_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN_Pos = 0x1c + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH4_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN_Msk = 0x10000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH4_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN = 0x10000000 + // Position of TASK_DUTY_SCALE_UPDATE_CH5_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN_Pos = 0x1d + // Bit mask of TASK_DUTY_SCALE_UPDATE_CH5_EN field. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN_Msk = 0x20000000 + // Bit TASK_DUTY_SCALE_UPDATE_CH5_EN. + LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN = 0x20000000 + + // EVT_TASK_EN1: Ledc event task enable bit register1. + // Position of TASK_TIMER0_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN_Pos = 0x0 + // Bit mask of TASK_TIMER0_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN_Msk = 0x1 + // Bit TASK_TIMER0_RES_UPDATE_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN = 0x1 + // Position of TASK_TIMER1_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN_Pos = 0x1 + // Bit mask of TASK_TIMER1_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN_Msk = 0x2 + // Bit TASK_TIMER1_RES_UPDATE_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN = 0x2 + // Position of TASK_TIMER2_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN_Pos = 0x2 + // Bit mask of TASK_TIMER2_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN_Msk = 0x4 + // Bit TASK_TIMER2_RES_UPDATE_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN = 0x4 + // Position of TASK_TIMER3_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN_Pos = 0x3 + // Bit mask of TASK_TIMER3_RES_UPDATE_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN_Msk = 0x8 + // Bit TASK_TIMER3_RES_UPDATE_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN = 0x8 + // Position of TASK_TIMER0_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_CAP_EN_Pos = 0x4 + // Bit mask of TASK_TIMER0_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_CAP_EN_Msk = 0x10 + // Bit TASK_TIMER0_CAP_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER0_CAP_EN = 0x10 + // Position of TASK_TIMER1_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_CAP_EN_Pos = 0x5 + // Bit mask of TASK_TIMER1_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_CAP_EN_Msk = 0x20 + // Bit TASK_TIMER1_CAP_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER1_CAP_EN = 0x20 + // Position of TASK_TIMER2_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_CAP_EN_Pos = 0x6 + // Bit mask of TASK_TIMER2_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_CAP_EN_Msk = 0x40 + // Bit TASK_TIMER2_CAP_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER2_CAP_EN = 0x40 + // Position of TASK_TIMER3_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_CAP_EN_Pos = 0x7 + // Bit mask of TASK_TIMER3_CAP_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_CAP_EN_Msk = 0x80 + // Bit TASK_TIMER3_CAP_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER3_CAP_EN = 0x80 + // Position of TASK_SIG_OUT_DIS_CH0_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN_Pos = 0x8 + // Bit mask of TASK_SIG_OUT_DIS_CH0_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN_Msk = 0x100 + // Bit TASK_SIG_OUT_DIS_CH0_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN = 0x100 + // Position of TASK_SIG_OUT_DIS_CH1_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN_Pos = 0x9 + // Bit mask of TASK_SIG_OUT_DIS_CH1_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN_Msk = 0x200 + // Bit TASK_SIG_OUT_DIS_CH1_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN = 0x200 + // Position of TASK_SIG_OUT_DIS_CH2_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN_Pos = 0xa + // Bit mask of TASK_SIG_OUT_DIS_CH2_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN_Msk = 0x400 + // Bit TASK_SIG_OUT_DIS_CH2_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN = 0x400 + // Position of TASK_SIG_OUT_DIS_CH3_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN_Pos = 0xb + // Bit mask of TASK_SIG_OUT_DIS_CH3_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN_Msk = 0x800 + // Bit TASK_SIG_OUT_DIS_CH3_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN = 0x800 + // Position of TASK_SIG_OUT_DIS_CH4_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN_Pos = 0xc + // Bit mask of TASK_SIG_OUT_DIS_CH4_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN_Msk = 0x1000 + // Bit TASK_SIG_OUT_DIS_CH4_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN = 0x1000 + // Position of TASK_SIG_OUT_DIS_CH5_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN_Pos = 0xd + // Bit mask of TASK_SIG_OUT_DIS_CH5_EN field. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN_Msk = 0x2000 + // Bit TASK_SIG_OUT_DIS_CH5_EN. + LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN = 0x2000 + // Position of TASK_OVF_CNT_RST_CH0_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN_Pos = 0x10 + // Bit mask of TASK_OVF_CNT_RST_CH0_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN_Msk = 0x10000 + // Bit TASK_OVF_CNT_RST_CH0_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN = 0x10000 + // Position of TASK_OVF_CNT_RST_CH1_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN_Pos = 0x11 + // Bit mask of TASK_OVF_CNT_RST_CH1_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN_Msk = 0x20000 + // Bit TASK_OVF_CNT_RST_CH1_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN = 0x20000 + // Position of TASK_OVF_CNT_RST_CH2_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN_Pos = 0x12 + // Bit mask of TASK_OVF_CNT_RST_CH2_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN_Msk = 0x40000 + // Bit TASK_OVF_CNT_RST_CH2_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN = 0x40000 + // Position of TASK_OVF_CNT_RST_CH3_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN_Pos = 0x13 + // Bit mask of TASK_OVF_CNT_RST_CH3_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN_Msk = 0x80000 + // Bit TASK_OVF_CNT_RST_CH3_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN = 0x80000 + // Position of TASK_OVF_CNT_RST_CH4_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN_Pos = 0x14 + // Bit mask of TASK_OVF_CNT_RST_CH4_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN_Msk = 0x100000 + // Bit TASK_OVF_CNT_RST_CH4_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN = 0x100000 + // Position of TASK_OVF_CNT_RST_CH5_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN_Pos = 0x15 + // Bit mask of TASK_OVF_CNT_RST_CH5_EN field. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN_Msk = 0x200000 + // Bit TASK_OVF_CNT_RST_CH5_EN. + LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN = 0x200000 + // Position of TASK_TIMER0_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RST_EN_Pos = 0x18 + // Bit mask of TASK_TIMER0_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RST_EN_Msk = 0x1000000 + // Bit TASK_TIMER0_RST_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER0_RST_EN = 0x1000000 + // Position of TASK_TIMER1_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RST_EN_Pos = 0x19 + // Bit mask of TASK_TIMER1_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RST_EN_Msk = 0x2000000 + // Bit TASK_TIMER1_RST_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER1_RST_EN = 0x2000000 + // Position of TASK_TIMER2_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RST_EN_Pos = 0x1a + // Bit mask of TASK_TIMER2_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RST_EN_Msk = 0x4000000 + // Bit TASK_TIMER2_RST_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER2_RST_EN = 0x4000000 + // Position of TASK_TIMER3_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RST_EN_Pos = 0x1b + // Bit mask of TASK_TIMER3_RST_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RST_EN_Msk = 0x8000000 + // Bit TASK_TIMER3_RST_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER3_RST_EN = 0x8000000 + // Position of TASK_TIMER0_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN_Pos = 0x1c + // Bit mask of TASK_TIMER0_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN_Msk = 0x10000000 + // Bit TASK_TIMER0_PAUSE_RESUME_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN = 0x10000000 + // Position of TASK_TIMER1_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN_Pos = 0x1d + // Bit mask of TASK_TIMER1_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN_Msk = 0x20000000 + // Bit TASK_TIMER1_PAUSE_RESUME_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN = 0x20000000 + // Position of TASK_TIMER2_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN_Pos = 0x1e + // Bit mask of TASK_TIMER2_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN_Msk = 0x40000000 + // Bit TASK_TIMER2_PAUSE_RESUME_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN = 0x40000000 + // Position of TASK_TIMER3_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN_Pos = 0x1f + // Bit mask of TASK_TIMER3_PAUSE_RESUME_EN field. + LEDC_EVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN_Msk = 0x80000000 + // Bit TASK_TIMER3_PAUSE_RESUME_EN. + LEDC_EVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN = 0x80000000 + + // EVT_TASK_EN2: Ledc event task enable bit register2. + // Position of TASK_GAMMA_RESTART_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN_Pos = 0x0 + // Bit mask of TASK_GAMMA_RESTART_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN_Msk = 0x1 + // Bit TASK_GAMMA_RESTART_CH0_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN = 0x1 + // Position of TASK_GAMMA_RESTART_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN_Pos = 0x1 + // Bit mask of TASK_GAMMA_RESTART_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN_Msk = 0x2 + // Bit TASK_GAMMA_RESTART_CH1_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN = 0x2 + // Position of TASK_GAMMA_RESTART_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN_Pos = 0x2 + // Bit mask of TASK_GAMMA_RESTART_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN_Msk = 0x4 + // Bit TASK_GAMMA_RESTART_CH2_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN = 0x4 + // Position of TASK_GAMMA_RESTART_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN_Pos = 0x3 + // Bit mask of TASK_GAMMA_RESTART_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN_Msk = 0x8 + // Bit TASK_GAMMA_RESTART_CH3_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN = 0x8 + // Position of TASK_GAMMA_RESTART_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN_Pos = 0x4 + // Bit mask of TASK_GAMMA_RESTART_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN_Msk = 0x10 + // Bit TASK_GAMMA_RESTART_CH4_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN = 0x10 + // Position of TASK_GAMMA_RESTART_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN_Pos = 0x5 + // Bit mask of TASK_GAMMA_RESTART_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN_Msk = 0x20 + // Bit TASK_GAMMA_RESTART_CH5_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN = 0x20 + // Position of TASK_GAMMA_PAUSE_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN_Pos = 0x8 + // Bit mask of TASK_GAMMA_PAUSE_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN_Msk = 0x100 + // Bit TASK_GAMMA_PAUSE_CH0_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN = 0x100 + // Position of TASK_GAMMA_PAUSE_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN_Pos = 0x9 + // Bit mask of TASK_GAMMA_PAUSE_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN_Msk = 0x200 + // Bit TASK_GAMMA_PAUSE_CH1_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN = 0x200 + // Position of TASK_GAMMA_PAUSE_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN_Pos = 0xa + // Bit mask of TASK_GAMMA_PAUSE_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN_Msk = 0x400 + // Bit TASK_GAMMA_PAUSE_CH2_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN = 0x400 + // Position of TASK_GAMMA_PAUSE_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN_Pos = 0xb + // Bit mask of TASK_GAMMA_PAUSE_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN_Msk = 0x800 + // Bit TASK_GAMMA_PAUSE_CH3_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN = 0x800 + // Position of TASK_GAMMA_PAUSE_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN_Pos = 0xc + // Bit mask of TASK_GAMMA_PAUSE_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN_Msk = 0x1000 + // Bit TASK_GAMMA_PAUSE_CH4_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN = 0x1000 + // Position of TASK_GAMMA_PAUSE_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN_Pos = 0xd + // Bit mask of TASK_GAMMA_PAUSE_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN_Msk = 0x2000 + // Bit TASK_GAMMA_PAUSE_CH5_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN = 0x2000 + // Position of TASK_GAMMA_RESUME_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN_Pos = 0x10 + // Bit mask of TASK_GAMMA_RESUME_CH0_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN_Msk = 0x10000 + // Bit TASK_GAMMA_RESUME_CH0_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN = 0x10000 + // Position of TASK_GAMMA_RESUME_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN_Pos = 0x11 + // Bit mask of TASK_GAMMA_RESUME_CH1_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN_Msk = 0x20000 + // Bit TASK_GAMMA_RESUME_CH1_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN = 0x20000 + // Position of TASK_GAMMA_RESUME_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN_Pos = 0x12 + // Bit mask of TASK_GAMMA_RESUME_CH2_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN_Msk = 0x40000 + // Bit TASK_GAMMA_RESUME_CH2_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN = 0x40000 + // Position of TASK_GAMMA_RESUME_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN_Pos = 0x13 + // Bit mask of TASK_GAMMA_RESUME_CH3_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN_Msk = 0x80000 + // Bit TASK_GAMMA_RESUME_CH3_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN = 0x80000 + // Position of TASK_GAMMA_RESUME_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN_Pos = 0x14 + // Bit mask of TASK_GAMMA_RESUME_CH4_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN_Msk = 0x100000 + // Bit TASK_GAMMA_RESUME_CH4_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN = 0x100000 + // Position of TASK_GAMMA_RESUME_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN_Pos = 0x15 + // Bit mask of TASK_GAMMA_RESUME_CH5_EN field. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN_Msk = 0x200000 + // Bit TASK_GAMMA_RESUME_CH5_EN. + LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN = 0x200000 + + // TIMER0_CMP: Ledc timer%s compare value register. + // Position of TIMER_CMP field. + LEDC_TIMER_CMP_TIMER_CMP_Pos = 0x0 + // Bit mask of TIMER_CMP field. + LEDC_TIMER_CMP_TIMER_CMP_Msk = 0xfffff + + // TIMER0_CNT_CAP: Ledc timer%s count value capture register. + // Position of TIMER_CNT_CAP field. + LEDC_TIMER_CNT_CAP_TIMER_CNT_CAP_Pos = 0x0 + // Bit mask of TIMER_CNT_CAP field. + LEDC_TIMER_CNT_CAP_TIMER_CNT_CAP_Msk = 0xfffff + + // CONF: Global ledc configuration register + // Position of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Pos = 0x0 + // Bit mask of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Msk = 0x3 + // Position of GAMMA_RAM_CLK_EN_CH0 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH0_Pos = 0x2 + // Bit mask of GAMMA_RAM_CLK_EN_CH0 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH0_Msk = 0x4 + // Bit GAMMA_RAM_CLK_EN_CH0. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH0 = 0x4 + // Position of GAMMA_RAM_CLK_EN_CH1 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH1_Pos = 0x3 + // Bit mask of GAMMA_RAM_CLK_EN_CH1 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH1_Msk = 0x8 + // Bit GAMMA_RAM_CLK_EN_CH1. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH1 = 0x8 + // Position of GAMMA_RAM_CLK_EN_CH2 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH2_Pos = 0x4 + // Bit mask of GAMMA_RAM_CLK_EN_CH2 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH2_Msk = 0x10 + // Bit GAMMA_RAM_CLK_EN_CH2. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH2 = 0x10 + // Position of GAMMA_RAM_CLK_EN_CH3 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH3_Pos = 0x5 + // Bit mask of GAMMA_RAM_CLK_EN_CH3 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH3_Msk = 0x20 + // Bit GAMMA_RAM_CLK_EN_CH3. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH3 = 0x20 + // Position of GAMMA_RAM_CLK_EN_CH4 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH4_Pos = 0x6 + // Bit mask of GAMMA_RAM_CLK_EN_CH4 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH4_Msk = 0x40 + // Bit GAMMA_RAM_CLK_EN_CH4. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH4 = 0x40 + // Position of GAMMA_RAM_CLK_EN_CH5 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH5_Pos = 0x7 + // Bit mask of GAMMA_RAM_CLK_EN_CH5 field. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH5_Msk = 0x80 + // Bit GAMMA_RAM_CLK_EN_CH5. + LEDC_CONF_GAMMA_RAM_CLK_EN_CH5 = 0x80 + // Position of CLK_EN field. + LEDC_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LEDC_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LEDC_CONF_CLK_EN = 0x80000000 + + // DATE: Version control register + // Position of LEDC_DATE field. + LEDC_DATE_LEDC_DATE_Pos = 0x0 + // Bit mask of LEDC_DATE field. + LEDC_DATE_LEDC_DATE_Msk = 0xfffffff +) + +// Constants for LP_PERI: LP_PERI Peripheral +const ( + // CLK_EN: need_des + // Position of RNG_CK_EN field. + LPPERI_CLK_EN_RNG_CK_EN_Pos = 0x18 + // Bit mask of RNG_CK_EN field. + LPPERI_CLK_EN_RNG_CK_EN_Msk = 0x1000000 + // Bit RNG_CK_EN. + LPPERI_CLK_EN_RNG_CK_EN = 0x1000000 + // Position of OTP_DBG_CK_EN field. + LPPERI_CLK_EN_OTP_DBG_CK_EN_Pos = 0x19 + // Bit mask of OTP_DBG_CK_EN field. + LPPERI_CLK_EN_OTP_DBG_CK_EN_Msk = 0x2000000 + // Bit OTP_DBG_CK_EN. + LPPERI_CLK_EN_OTP_DBG_CK_EN = 0x2000000 + // Position of LP_UART_CK_EN field. + LPPERI_CLK_EN_LP_UART_CK_EN_Pos = 0x1a + // Bit mask of LP_UART_CK_EN field. + LPPERI_CLK_EN_LP_UART_CK_EN_Msk = 0x4000000 + // Bit LP_UART_CK_EN. + LPPERI_CLK_EN_LP_UART_CK_EN = 0x4000000 + // Position of LP_IO_CK_EN field. + LPPERI_CLK_EN_LP_IO_CK_EN_Pos = 0x1b + // Bit mask of LP_IO_CK_EN field. + LPPERI_CLK_EN_LP_IO_CK_EN_Msk = 0x8000000 + // Bit LP_IO_CK_EN. + LPPERI_CLK_EN_LP_IO_CK_EN = 0x8000000 + // Position of LP_EXT_I2C_CK_EN field. + LPPERI_CLK_EN_LP_EXT_I2C_CK_EN_Pos = 0x1c + // Bit mask of LP_EXT_I2C_CK_EN field. + LPPERI_CLK_EN_LP_EXT_I2C_CK_EN_Msk = 0x10000000 + // Bit LP_EXT_I2C_CK_EN. + LPPERI_CLK_EN_LP_EXT_I2C_CK_EN = 0x10000000 + // Position of LP_ANA_I2C_CK_EN field. + LPPERI_CLK_EN_LP_ANA_I2C_CK_EN_Pos = 0x1d + // Bit mask of LP_ANA_I2C_CK_EN field. + LPPERI_CLK_EN_LP_ANA_I2C_CK_EN_Msk = 0x20000000 + // Bit LP_ANA_I2C_CK_EN. + LPPERI_CLK_EN_LP_ANA_I2C_CK_EN = 0x20000000 + // Position of EFUSE_CK_EN field. + LPPERI_CLK_EN_EFUSE_CK_EN_Pos = 0x1e + // Bit mask of EFUSE_CK_EN field. + LPPERI_CLK_EN_EFUSE_CK_EN_Msk = 0x40000000 + // Bit EFUSE_CK_EN. + LPPERI_CLK_EN_EFUSE_CK_EN = 0x40000000 + // Position of LP_CPU_CK_EN field. + LPPERI_CLK_EN_LP_CPU_CK_EN_Pos = 0x1f + // Bit mask of LP_CPU_CK_EN field. + LPPERI_CLK_EN_LP_CPU_CK_EN_Msk = 0x80000000 + // Bit LP_CPU_CK_EN. + LPPERI_CLK_EN_LP_CPU_CK_EN = 0x80000000 + + // RESET_EN: need_des + // Position of BUS_RESET_EN field. + LPPERI_RESET_EN_BUS_RESET_EN_Pos = 0x17 + // Bit mask of BUS_RESET_EN field. + LPPERI_RESET_EN_BUS_RESET_EN_Msk = 0x800000 + // Bit BUS_RESET_EN. + LPPERI_RESET_EN_BUS_RESET_EN = 0x800000 + // Position of LP_BLE_TIMER_RESET_EN field. + LPPERI_RESET_EN_LP_BLE_TIMER_RESET_EN_Pos = 0x18 + // Bit mask of LP_BLE_TIMER_RESET_EN field. + LPPERI_RESET_EN_LP_BLE_TIMER_RESET_EN_Msk = 0x1000000 + // Bit LP_BLE_TIMER_RESET_EN. + LPPERI_RESET_EN_LP_BLE_TIMER_RESET_EN = 0x1000000 + // Position of OTP_DBG_RESET_EN field. + LPPERI_RESET_EN_OTP_DBG_RESET_EN_Pos = 0x19 + // Bit mask of OTP_DBG_RESET_EN field. + LPPERI_RESET_EN_OTP_DBG_RESET_EN_Msk = 0x2000000 + // Bit OTP_DBG_RESET_EN. + LPPERI_RESET_EN_OTP_DBG_RESET_EN = 0x2000000 + // Position of LP_UART_RESET_EN field. + LPPERI_RESET_EN_LP_UART_RESET_EN_Pos = 0x1a + // Bit mask of LP_UART_RESET_EN field. + LPPERI_RESET_EN_LP_UART_RESET_EN_Msk = 0x4000000 + // Bit LP_UART_RESET_EN. + LPPERI_RESET_EN_LP_UART_RESET_EN = 0x4000000 + // Position of LP_IO_RESET_EN field. + LPPERI_RESET_EN_LP_IO_RESET_EN_Pos = 0x1b + // Bit mask of LP_IO_RESET_EN field. + LPPERI_RESET_EN_LP_IO_RESET_EN_Msk = 0x8000000 + // Bit LP_IO_RESET_EN. + LPPERI_RESET_EN_LP_IO_RESET_EN = 0x8000000 + // Position of LP_EXT_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_EXT_I2C_RESET_EN_Pos = 0x1c + // Bit mask of LP_EXT_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_EXT_I2C_RESET_EN_Msk = 0x10000000 + // Bit LP_EXT_I2C_RESET_EN. + LPPERI_RESET_EN_LP_EXT_I2C_RESET_EN = 0x10000000 + // Position of LP_ANA_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_ANA_I2C_RESET_EN_Pos = 0x1d + // Bit mask of LP_ANA_I2C_RESET_EN field. + LPPERI_RESET_EN_LP_ANA_I2C_RESET_EN_Msk = 0x20000000 + // Bit LP_ANA_I2C_RESET_EN. + LPPERI_RESET_EN_LP_ANA_I2C_RESET_EN = 0x20000000 + // Position of EFUSE_RESET_EN field. + LPPERI_RESET_EN_EFUSE_RESET_EN_Pos = 0x1e + // Bit mask of EFUSE_RESET_EN field. + LPPERI_RESET_EN_EFUSE_RESET_EN_Msk = 0x40000000 + // Bit EFUSE_RESET_EN. + LPPERI_RESET_EN_EFUSE_RESET_EN = 0x40000000 + // Position of LP_CPU_RESET_EN field. + LPPERI_RESET_EN_LP_CPU_RESET_EN_Pos = 0x1f + // Bit mask of LP_CPU_RESET_EN field. + LPPERI_RESET_EN_LP_CPU_RESET_EN_Msk = 0x80000000 + // Bit LP_CPU_RESET_EN. + LPPERI_RESET_EN_LP_CPU_RESET_EN = 0x80000000 + + // RNG_DATA: need_des + // Position of RND_DATA field. + LPPERI_RNG_DATA_RND_DATA_Pos = 0x0 + // Bit mask of RND_DATA field. + LPPERI_RNG_DATA_RND_DATA_Msk = 0xffffffff + + // CPU: need_des + // Position of LPCORE_DBGM_UNAVALIABLE field. + LPPERI_CPU_LPCORE_DBGM_UNAVALIABLE_Pos = 0x1f + // Bit mask of LPCORE_DBGM_UNAVALIABLE field. + LPPERI_CPU_LPCORE_DBGM_UNAVALIABLE_Msk = 0x80000000 + // Bit LPCORE_DBGM_UNAVALIABLE. + LPPERI_CPU_LPCORE_DBGM_UNAVALIABLE = 0x80000000 + + // BUS_TIMEOUT: need_des + // Position of LP_PERI_TIMEOUT_THRES field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_THRES_Pos = 0xe + // Bit mask of LP_PERI_TIMEOUT_THRES field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_THRES_Msk = 0x3fffc000 + // Position of LP_PERI_TIMEOUT_INT_CLEAR field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR_Pos = 0x1e + // Bit mask of LP_PERI_TIMEOUT_INT_CLEAR field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR_Msk = 0x40000000 + // Bit LP_PERI_TIMEOUT_INT_CLEAR. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_INT_CLEAR = 0x40000000 + // Position of LP_PERI_TIMEOUT_PROTECT_EN field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN_Pos = 0x1f + // Bit mask of LP_PERI_TIMEOUT_PROTECT_EN field. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN_Msk = 0x80000000 + // Bit LP_PERI_TIMEOUT_PROTECT_EN. + LPPERI_BUS_TIMEOUT_LP_PERI_TIMEOUT_PROTECT_EN = 0x80000000 + + // BUS_TIMEOUT_ADDR: need_des + // Position of LP_PERI_TIMEOUT_ADDR field. + LPPERI_BUS_TIMEOUT_ADDR_LP_PERI_TIMEOUT_ADDR_Pos = 0x0 + // Bit mask of LP_PERI_TIMEOUT_ADDR field. + LPPERI_BUS_TIMEOUT_ADDR_LP_PERI_TIMEOUT_ADDR_Msk = 0xffffffff + + // BUS_TIMEOUT_UID: need_des + // Position of LP_PERI_TIMEOUT_UID field. + LPPERI_BUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID_Pos = 0x0 + // Bit mask of LP_PERI_TIMEOUT_UID field. + LPPERI_BUS_TIMEOUT_UID_LP_PERI_TIMEOUT_UID_Msk = 0x7f + + // MEM_CTRL: need_des + // Position of UART_WAKEUP_FLAG_CLR field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_CLR_Pos = 0x0 + // Bit mask of UART_WAKEUP_FLAG_CLR field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_CLR_Msk = 0x1 + // Bit UART_WAKEUP_FLAG_CLR. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_CLR = 0x1 + // Position of UART_WAKEUP_FLAG field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_Pos = 0x1 + // Bit mask of UART_WAKEUP_FLAG field. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG_Msk = 0x2 + // Bit UART_WAKEUP_FLAG. + LPPERI_MEM_CTRL_UART_WAKEUP_FLAG = 0x2 + // Position of UART_WAKEUP_EN field. + LPPERI_MEM_CTRL_UART_WAKEUP_EN_Pos = 0x1d + // Bit mask of UART_WAKEUP_EN field. + LPPERI_MEM_CTRL_UART_WAKEUP_EN_Msk = 0x20000000 + // Bit UART_WAKEUP_EN. + LPPERI_MEM_CTRL_UART_WAKEUP_EN = 0x20000000 + // Position of UART_MEM_FORCE_PD field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PD_Pos = 0x1e + // Bit mask of UART_MEM_FORCE_PD field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PD_Msk = 0x40000000 + // Bit UART_MEM_FORCE_PD. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PD = 0x40000000 + // Position of UART_MEM_FORCE_PU field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PU_Pos = 0x1f + // Bit mask of UART_MEM_FORCE_PU field. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PU_Msk = 0x80000000 + // Bit UART_MEM_FORCE_PU. + LPPERI_MEM_CTRL_UART_MEM_FORCE_PU = 0x80000000 + + // INTERRUPT_SOURCE: need_des + // Position of LP_INTERRUPT_SOURCE field. + LPPERI_INTERRUPT_SOURCE_LP_INTERRUPT_SOURCE_Pos = 0x0 + // Bit mask of LP_INTERRUPT_SOURCE field. + LPPERI_INTERRUPT_SOURCE_LP_INTERRUPT_SOURCE_Msk = 0x3f + + // DEBUG_SEL0: need des + // Position of DEBUG_SEL0 field. + LPPERI_DEBUG_SEL0_DEBUG_SEL0_Pos = 0x0 + // Bit mask of DEBUG_SEL0 field. + LPPERI_DEBUG_SEL0_DEBUG_SEL0_Msk = 0x7f + // Position of DEBUG_SEL1 field. + LPPERI_DEBUG_SEL0_DEBUG_SEL1_Pos = 0x7 + // Bit mask of DEBUG_SEL1 field. + LPPERI_DEBUG_SEL0_DEBUG_SEL1_Msk = 0x3f80 + // Position of DEBUG_SEL2 field. + LPPERI_DEBUG_SEL0_DEBUG_SEL2_Pos = 0xe + // Bit mask of DEBUG_SEL2 field. + LPPERI_DEBUG_SEL0_DEBUG_SEL2_Msk = 0x1fc000 + // Position of DEBUG_SEL3 field. + LPPERI_DEBUG_SEL0_DEBUG_SEL3_Pos = 0x15 + // Bit mask of DEBUG_SEL3 field. + LPPERI_DEBUG_SEL0_DEBUG_SEL3_Msk = 0xfe00000 + + // DEBUG_SEL1: need des + // Position of DEBUG_SEL4 field. + LPPERI_DEBUG_SEL1_DEBUG_SEL4_Pos = 0x0 + // Bit mask of DEBUG_SEL4 field. + LPPERI_DEBUG_SEL1_DEBUG_SEL4_Msk = 0x7f + + // DATE: need_des + // Position of LPPERI_DATE field. + LPPERI_DATE_LPPERI_DATE_Pos = 0x0 + // Bit mask of LPPERI_DATE field. + LPPERI_DATE_LPPERI_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LPPERI_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LPPERI_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LPPERI_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_ANA: LP_ANA Peripheral +const ( + // BOD_MODE0_CNTL: need_des + // Position of BOD_MODE0_CLOSE_FLASH_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA_Pos = 0x6 + // Bit mask of BOD_MODE0_CLOSE_FLASH_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA_Msk = 0x40 + // Bit BOD_MODE0_CLOSE_FLASH_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CLOSE_FLASH_ENA = 0x40 + // Position of BOD_MODE0_PD_RF_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA_Pos = 0x7 + // Bit mask of BOD_MODE0_PD_RF_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA_Msk = 0x80 + // Bit BOD_MODE0_PD_RF_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_PD_RF_ENA = 0x80 + // Position of BOD_MODE0_INTR_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT_Pos = 0x8 + // Bit mask of BOD_MODE0_INTR_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_WAIT_Msk = 0x3ff00 + // Position of BOD_MODE0_RESET_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT_Pos = 0x12 + // Bit mask of BOD_MODE0_RESET_WAIT field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_WAIT_Msk = 0xffc0000 + // Position of BOD_MODE0_CNT_CLR field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CNT_CLR_Pos = 0x1c + // Bit mask of BOD_MODE0_CNT_CLR field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CNT_CLR_Msk = 0x10000000 + // Bit BOD_MODE0_CNT_CLR. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_CNT_CLR = 0x10000000 + // Position of BOD_MODE0_INTR_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_ENA_Pos = 0x1d + // Bit mask of BOD_MODE0_INTR_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_ENA_Msk = 0x20000000 + // Bit BOD_MODE0_INTR_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_INTR_ENA = 0x20000000 + // Position of BOD_MODE0_RESET_SEL field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_SEL_Pos = 0x1e + // Bit mask of BOD_MODE0_RESET_SEL field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_SEL_Msk = 0x40000000 + // Bit BOD_MODE0_RESET_SEL. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_SEL = 0x40000000 + // Position of BOD_MODE0_RESET_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_ENA_Pos = 0x1f + // Bit mask of BOD_MODE0_RESET_ENA field. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_ENA_Msk = 0x80000000 + // Bit BOD_MODE0_RESET_ENA. + LP_ANA_BOD_MODE0_CNTL_BOD_MODE0_RESET_ENA = 0x80000000 + + // BOD_MODE1_CNTL: need_des + // Position of BOD_MODE1_RESET_ENA field. + LP_ANA_BOD_MODE1_CNTL_BOD_MODE1_RESET_ENA_Pos = 0x1f + // Bit mask of BOD_MODE1_RESET_ENA field. + LP_ANA_BOD_MODE1_CNTL_BOD_MODE1_RESET_ENA_Msk = 0x80000000 + // Bit BOD_MODE1_RESET_ENA. + LP_ANA_BOD_MODE1_CNTL_BOD_MODE1_RESET_ENA = 0x80000000 + + // VDD_SOURCE_CNTL: need_des + // Position of DETMODE_SEL field. + LP_ANA_VDD_SOURCE_CNTL_DETMODE_SEL_Pos = 0x0 + // Bit mask of DETMODE_SEL field. + LP_ANA_VDD_SOURCE_CNTL_DETMODE_SEL_Msk = 0xff + // Position of VGOOD_EVENT_RECORD field. + LP_ANA_VDD_SOURCE_CNTL_VGOOD_EVENT_RECORD_Pos = 0x8 + // Bit mask of VGOOD_EVENT_RECORD field. + LP_ANA_VDD_SOURCE_CNTL_VGOOD_EVENT_RECORD_Msk = 0xff00 + // Position of VBAT_EVENT_RECORD_CLR field. + LP_ANA_VDD_SOURCE_CNTL_VBAT_EVENT_RECORD_CLR_Pos = 0x10 + // Bit mask of VBAT_EVENT_RECORD_CLR field. + LP_ANA_VDD_SOURCE_CNTL_VBAT_EVENT_RECORD_CLR_Msk = 0xff0000 + // Position of BOD_SOURCE_ENA field. + LP_ANA_VDD_SOURCE_CNTL_BOD_SOURCE_ENA_Pos = 0x18 + // Bit mask of BOD_SOURCE_ENA field. + LP_ANA_VDD_SOURCE_CNTL_BOD_SOURCE_ENA_Msk = 0xff000000 + + // VDDBAT_BOD_CNTL: need_des + // Position of VDDBAT_UNDERVOLTAGE_FLAG field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_UNDERVOLTAGE_FLAG_Pos = 0x0 + // Bit mask of VDDBAT_UNDERVOLTAGE_FLAG field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_UNDERVOLTAGE_FLAG_Msk = 0x1 + // Bit VDDBAT_UNDERVOLTAGE_FLAG. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_UNDERVOLTAGE_FLAG = 0x1 + // Position of VDDBAT_CHARGER field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_CHARGER_Pos = 0xa + // Bit mask of VDDBAT_CHARGER field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_CHARGER_Msk = 0x400 + // Bit VDDBAT_CHARGER. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_CHARGER = 0x400 + // Position of VDDBAT_CNT_CLR field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_CNT_CLR_Pos = 0xb + // Bit mask of VDDBAT_CNT_CLR field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_CNT_CLR_Msk = 0x800 + // Bit VDDBAT_CNT_CLR. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_CNT_CLR = 0x800 + // Position of VDDBAT_UPVOLTAGE_TARGET field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_UPVOLTAGE_TARGET_Pos = 0xc + // Bit mask of VDDBAT_UPVOLTAGE_TARGET field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_UPVOLTAGE_TARGET_Msk = 0x3ff000 + // Position of VDDBAT_UNDERVOLTAGE_TARGET field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_UNDERVOLTAGE_TARGET_Pos = 0x16 + // Bit mask of VDDBAT_UNDERVOLTAGE_TARGET field. + LP_ANA_VDDBAT_BOD_CNTL_VDDBAT_UNDERVOLTAGE_TARGET_Msk = 0xffc00000 + + // VDDBAT_CHARGE_CNTL: need_des + // Position of VDDBAT_CHARGE_UNDERVOLTAGE_FLAG field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_Pos = 0x0 + // Bit mask of VDDBAT_CHARGE_UNDERVOLTAGE_FLAG field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_Msk = 0x1 + // Bit VDDBAT_CHARGE_UNDERVOLTAGE_FLAG. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG = 0x1 + // Position of VDDBAT_CHARGE_CHARGER field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CHARGER_Pos = 0xa + // Bit mask of VDDBAT_CHARGE_CHARGER field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CHARGER_Msk = 0x400 + // Bit VDDBAT_CHARGE_CHARGER. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CHARGER = 0x400 + // Position of VDDBAT_CHARGE_CNT_CLR field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CNT_CLR_Pos = 0xb + // Bit mask of VDDBAT_CHARGE_CNT_CLR field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CNT_CLR_Msk = 0x800 + // Bit VDDBAT_CHARGE_CNT_CLR. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_CNT_CLR = 0x800 + // Position of VDDBAT_CHARGE_UPVOLTAGE_TARGET field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UPVOLTAGE_TARGET_Pos = 0xc + // Bit mask of VDDBAT_CHARGE_UPVOLTAGE_TARGET field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UPVOLTAGE_TARGET_Msk = 0x3ff000 + // Position of VDDBAT_CHARGE_UNDERVOLTAGE_TARGET field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_Pos = 0x16 + // Bit mask of VDDBAT_CHARGE_UNDERVOLTAGE_TARGET field. + LP_ANA_VDDBAT_CHARGE_CNTL_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_Msk = 0xffc00000 + + // CK_GLITCH_CNTL: need_des + // Position of CK_GLITCH_RESET_ENA field. + LP_ANA_CK_GLITCH_CNTL_CK_GLITCH_RESET_ENA_Pos = 0x1f + // Bit mask of CK_GLITCH_RESET_ENA field. + LP_ANA_CK_GLITCH_CNTL_CK_GLITCH_RESET_ENA_Msk = 0x80000000 + // Bit CK_GLITCH_RESET_ENA. + LP_ANA_CK_GLITCH_CNTL_CK_GLITCH_RESET_ENA = 0x80000000 + + // PG_GLITCH_CNTL: need_des + // Position of POWER_GLITCH_RESET_ENA field. + LP_ANA_PG_GLITCH_CNTL_POWER_GLITCH_RESET_ENA_Pos = 0x1f + // Bit mask of POWER_GLITCH_RESET_ENA field. + LP_ANA_PG_GLITCH_CNTL_POWER_GLITCH_RESET_ENA_Msk = 0x80000000 + // Bit POWER_GLITCH_RESET_ENA. + LP_ANA_PG_GLITCH_CNTL_POWER_GLITCH_RESET_ENA = 0x80000000 + + // FIB_ENABLE: need_des + // Position of ANA_FIB_ENA field. + LP_ANA_FIB_ENABLE_ANA_FIB_ENA_Pos = 0x0 + // Bit mask of ANA_FIB_ENA field. + LP_ANA_FIB_ENABLE_ANA_FIB_ENA_Msk = 0xffffffff + + // INT_RAW: need_des + // Position of VDDBAT_CHARGE_UPVOLTAGE_INT_RAW field. + LP_ANA_INT_RAW_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_Pos = 0x1b + // Bit mask of VDDBAT_CHARGE_UPVOLTAGE_INT_RAW field. + LP_ANA_INT_RAW_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_Msk = 0x8000000 + // Bit VDDBAT_CHARGE_UPVOLTAGE_INT_RAW. + LP_ANA_INT_RAW_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW = 0x8000000 + // Position of VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW field. + LP_ANA_INT_RAW_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_Pos = 0x1c + // Bit mask of VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW field. + LP_ANA_INT_RAW_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_Msk = 0x10000000 + // Bit VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW. + LP_ANA_INT_RAW_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW = 0x10000000 + // Position of VDDBAT_UPVOLTAGE_INT_RAW field. + LP_ANA_INT_RAW_VDDBAT_UPVOLTAGE_INT_RAW_Pos = 0x1d + // Bit mask of VDDBAT_UPVOLTAGE_INT_RAW field. + LP_ANA_INT_RAW_VDDBAT_UPVOLTAGE_INT_RAW_Msk = 0x20000000 + // Bit VDDBAT_UPVOLTAGE_INT_RAW. + LP_ANA_INT_RAW_VDDBAT_UPVOLTAGE_INT_RAW = 0x20000000 + // Position of VDDBAT_UNDERVOLTAGE_INT_RAW field. + LP_ANA_INT_RAW_VDDBAT_UNDERVOLTAGE_INT_RAW_Pos = 0x1e + // Bit mask of VDDBAT_UNDERVOLTAGE_INT_RAW field. + LP_ANA_INT_RAW_VDDBAT_UNDERVOLTAGE_INT_RAW_Msk = 0x40000000 + // Bit VDDBAT_UNDERVOLTAGE_INT_RAW. + LP_ANA_INT_RAW_VDDBAT_UNDERVOLTAGE_INT_RAW = 0x40000000 + // Position of BOD_MODE0_INT_RAW field. + LP_ANA_INT_RAW_BOD_MODE0_INT_RAW_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_RAW field. + LP_ANA_INT_RAW_BOD_MODE0_INT_RAW_Msk = 0x80000000 + // Bit BOD_MODE0_INT_RAW. + LP_ANA_INT_RAW_BOD_MODE0_INT_RAW = 0x80000000 + + // INT_ST: need_des + // Position of VDDBAT_CHARGE_UPVOLTAGE_INT_ST field. + LP_ANA_INT_ST_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_Pos = 0x1b + // Bit mask of VDDBAT_CHARGE_UPVOLTAGE_INT_ST field. + LP_ANA_INT_ST_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_Msk = 0x8000000 + // Bit VDDBAT_CHARGE_UPVOLTAGE_INT_ST. + LP_ANA_INT_ST_VDDBAT_CHARGE_UPVOLTAGE_INT_ST = 0x8000000 + // Position of VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST field. + LP_ANA_INT_ST_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_Pos = 0x1c + // Bit mask of VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST field. + LP_ANA_INT_ST_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_Msk = 0x10000000 + // Bit VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST. + LP_ANA_INT_ST_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST = 0x10000000 + // Position of VDDBAT_UPVOLTAGE_INT_ST field. + LP_ANA_INT_ST_VDDBAT_UPVOLTAGE_INT_ST_Pos = 0x1d + // Bit mask of VDDBAT_UPVOLTAGE_INT_ST field. + LP_ANA_INT_ST_VDDBAT_UPVOLTAGE_INT_ST_Msk = 0x20000000 + // Bit VDDBAT_UPVOLTAGE_INT_ST. + LP_ANA_INT_ST_VDDBAT_UPVOLTAGE_INT_ST = 0x20000000 + // Position of VDDBAT_UNDERVOLTAGE_INT_ST field. + LP_ANA_INT_ST_VDDBAT_UNDERVOLTAGE_INT_ST_Pos = 0x1e + // Bit mask of VDDBAT_UNDERVOLTAGE_INT_ST field. + LP_ANA_INT_ST_VDDBAT_UNDERVOLTAGE_INT_ST_Msk = 0x40000000 + // Bit VDDBAT_UNDERVOLTAGE_INT_ST. + LP_ANA_INT_ST_VDDBAT_UNDERVOLTAGE_INT_ST = 0x40000000 + // Position of BOD_MODE0_INT_ST field. + LP_ANA_INT_ST_BOD_MODE0_INT_ST_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_ST field. + LP_ANA_INT_ST_BOD_MODE0_INT_ST_Msk = 0x80000000 + // Bit BOD_MODE0_INT_ST. + LP_ANA_INT_ST_BOD_MODE0_INT_ST = 0x80000000 + + // INT_ENA: need_des + // Position of VDDBAT_CHARGE_UPVOLTAGE_INT_ENA field. + LP_ANA_INT_ENA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_Pos = 0x1b + // Bit mask of VDDBAT_CHARGE_UPVOLTAGE_INT_ENA field. + LP_ANA_INT_ENA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_Msk = 0x8000000 + // Bit VDDBAT_CHARGE_UPVOLTAGE_INT_ENA. + LP_ANA_INT_ENA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA = 0x8000000 + // Position of VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA field. + LP_ANA_INT_ENA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_Pos = 0x1c + // Bit mask of VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA field. + LP_ANA_INT_ENA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_Msk = 0x10000000 + // Bit VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA. + LP_ANA_INT_ENA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA = 0x10000000 + // Position of VDDBAT_UPVOLTAGE_INT_ENA field. + LP_ANA_INT_ENA_VDDBAT_UPVOLTAGE_INT_ENA_Pos = 0x1d + // Bit mask of VDDBAT_UPVOLTAGE_INT_ENA field. + LP_ANA_INT_ENA_VDDBAT_UPVOLTAGE_INT_ENA_Msk = 0x20000000 + // Bit VDDBAT_UPVOLTAGE_INT_ENA. + LP_ANA_INT_ENA_VDDBAT_UPVOLTAGE_INT_ENA = 0x20000000 + // Position of VDDBAT_UNDERVOLTAGE_INT_ENA field. + LP_ANA_INT_ENA_VDDBAT_UNDERVOLTAGE_INT_ENA_Pos = 0x1e + // Bit mask of VDDBAT_UNDERVOLTAGE_INT_ENA field. + LP_ANA_INT_ENA_VDDBAT_UNDERVOLTAGE_INT_ENA_Msk = 0x40000000 + // Bit VDDBAT_UNDERVOLTAGE_INT_ENA. + LP_ANA_INT_ENA_VDDBAT_UNDERVOLTAGE_INT_ENA = 0x40000000 + // Position of BOD_MODE0_INT_ENA field. + LP_ANA_INT_ENA_BOD_MODE0_INT_ENA_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_ENA field. + LP_ANA_INT_ENA_BOD_MODE0_INT_ENA_Msk = 0x80000000 + // Bit BOD_MODE0_INT_ENA. + LP_ANA_INT_ENA_BOD_MODE0_INT_ENA = 0x80000000 + + // INT_CLR: need_des + // Position of VDDBAT_CHARGE_UPVOLTAGE_INT_CLR field. + LP_ANA_INT_CLR_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_Pos = 0x1b + // Bit mask of VDDBAT_CHARGE_UPVOLTAGE_INT_CLR field. + LP_ANA_INT_CLR_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_Msk = 0x8000000 + // Bit VDDBAT_CHARGE_UPVOLTAGE_INT_CLR. + LP_ANA_INT_CLR_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR = 0x8000000 + // Position of VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR field. + LP_ANA_INT_CLR_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_Pos = 0x1c + // Bit mask of VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR field. + LP_ANA_INT_CLR_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_Msk = 0x10000000 + // Bit VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR. + LP_ANA_INT_CLR_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR = 0x10000000 + // Position of VDDBAT_UPVOLTAGE_INT_CLR field. + LP_ANA_INT_CLR_VDDBAT_UPVOLTAGE_INT_CLR_Pos = 0x1d + // Bit mask of VDDBAT_UPVOLTAGE_INT_CLR field. + LP_ANA_INT_CLR_VDDBAT_UPVOLTAGE_INT_CLR_Msk = 0x20000000 + // Bit VDDBAT_UPVOLTAGE_INT_CLR. + LP_ANA_INT_CLR_VDDBAT_UPVOLTAGE_INT_CLR = 0x20000000 + // Position of VDDBAT_UNDERVOLTAGE_INT_CLR field. + LP_ANA_INT_CLR_VDDBAT_UNDERVOLTAGE_INT_CLR_Pos = 0x1e + // Bit mask of VDDBAT_UNDERVOLTAGE_INT_CLR field. + LP_ANA_INT_CLR_VDDBAT_UNDERVOLTAGE_INT_CLR_Msk = 0x40000000 + // Bit VDDBAT_UNDERVOLTAGE_INT_CLR. + LP_ANA_INT_CLR_VDDBAT_UNDERVOLTAGE_INT_CLR = 0x40000000 + // Position of BOD_MODE0_INT_CLR field. + LP_ANA_INT_CLR_BOD_MODE0_INT_CLR_Pos = 0x1f + // Bit mask of BOD_MODE0_INT_CLR field. + LP_ANA_INT_CLR_BOD_MODE0_INT_CLR_Msk = 0x80000000 + // Bit BOD_MODE0_INT_CLR. + LP_ANA_INT_CLR_BOD_MODE0_INT_CLR = 0x80000000 + + // LP_INT_RAW: need_des + // Position of BOD_MODE0_LP_INT_RAW field. + LP_ANA_LP_INT_RAW_BOD_MODE0_LP_INT_RAW_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_RAW field. + LP_ANA_LP_INT_RAW_BOD_MODE0_LP_INT_RAW_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_RAW. + LP_ANA_LP_INT_RAW_BOD_MODE0_LP_INT_RAW = 0x80000000 + + // LP_INT_ST: need_des + // Position of BOD_MODE0_LP_INT_ST field. + LP_ANA_LP_INT_ST_BOD_MODE0_LP_INT_ST_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_ST field. + LP_ANA_LP_INT_ST_BOD_MODE0_LP_INT_ST_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_ST. + LP_ANA_LP_INT_ST_BOD_MODE0_LP_INT_ST = 0x80000000 + + // LP_INT_ENA: need_des + // Position of BOD_MODE0_LP_INT_ENA field. + LP_ANA_LP_INT_ENA_BOD_MODE0_LP_INT_ENA_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_ENA field. + LP_ANA_LP_INT_ENA_BOD_MODE0_LP_INT_ENA_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_ENA. + LP_ANA_LP_INT_ENA_BOD_MODE0_LP_INT_ENA = 0x80000000 + + // LP_INT_CLR: need_des + // Position of BOD_MODE0_LP_INT_CLR field. + LP_ANA_LP_INT_CLR_BOD_MODE0_LP_INT_CLR_Pos = 0x1f + // Bit mask of BOD_MODE0_LP_INT_CLR field. + LP_ANA_LP_INT_CLR_BOD_MODE0_LP_INT_CLR_Msk = 0x80000000 + // Bit BOD_MODE0_LP_INT_CLR. + LP_ANA_LP_INT_CLR_BOD_MODE0_LP_INT_CLR = 0x80000000 + + // DATE: need_des + // Position of LP_ANA_DATE field. + LP_ANA_DATE_LP_ANA_DATE_Pos = 0x0 + // Bit mask of LP_ANA_DATE field. + LP_ANA_DATE_LP_ANA_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_ANA_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_ANA_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_ANA_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_AON: LP_AON Peripheral +const ( + // STORE0: need_des + // Position of LP_AON_STORE0 field. + LP_AON_STORE0_LP_AON_STORE0_Pos = 0x0 + // Bit mask of LP_AON_STORE0 field. + LP_AON_STORE0_LP_AON_STORE0_Msk = 0xffffffff + + // STORE1: need_des + // Position of LP_AON_STORE1 field. + LP_AON_STORE1_LP_AON_STORE1_Pos = 0x0 + // Bit mask of LP_AON_STORE1 field. + LP_AON_STORE1_LP_AON_STORE1_Msk = 0xffffffff + + // STORE2: need_des + // Position of LP_AON_STORE2 field. + LP_AON_STORE2_LP_AON_STORE2_Pos = 0x0 + // Bit mask of LP_AON_STORE2 field. + LP_AON_STORE2_LP_AON_STORE2_Msk = 0xffffffff + + // STORE3: need_des + // Position of LP_AON_STORE3 field. + LP_AON_STORE3_LP_AON_STORE3_Pos = 0x0 + // Bit mask of LP_AON_STORE3 field. + LP_AON_STORE3_LP_AON_STORE3_Msk = 0xffffffff + + // STORE4: need_des + // Position of LP_AON_STORE4 field. + LP_AON_STORE4_LP_AON_STORE4_Pos = 0x0 + // Bit mask of LP_AON_STORE4 field. + LP_AON_STORE4_LP_AON_STORE4_Msk = 0xffffffff + + // STORE5: need_des + // Position of LP_AON_STORE5 field. + LP_AON_STORE5_LP_AON_STORE5_Pos = 0x0 + // Bit mask of LP_AON_STORE5 field. + LP_AON_STORE5_LP_AON_STORE5_Msk = 0xffffffff + + // STORE6: need_des + // Position of LP_AON_STORE6 field. + LP_AON_STORE6_LP_AON_STORE6_Pos = 0x0 + // Bit mask of LP_AON_STORE6 field. + LP_AON_STORE6_LP_AON_STORE6_Msk = 0xffffffff + + // STORE7: need_des + // Position of LP_AON_STORE7 field. + LP_AON_STORE7_LP_AON_STORE7_Pos = 0x0 + // Bit mask of LP_AON_STORE7 field. + LP_AON_STORE7_LP_AON_STORE7_Msk = 0xffffffff + + // STORE8: need_des + // Position of LP_AON_STORE8 field. + LP_AON_STORE8_LP_AON_STORE8_Pos = 0x0 + // Bit mask of LP_AON_STORE8 field. + LP_AON_STORE8_LP_AON_STORE8_Msk = 0xffffffff + + // STORE9: need_des + // Position of LP_AON_STORE9 field. + LP_AON_STORE9_LP_AON_STORE9_Pos = 0x0 + // Bit mask of LP_AON_STORE9 field. + LP_AON_STORE9_LP_AON_STORE9_Msk = 0xffffffff + + // GPIO_MUX: need_des + // Position of SEL field. + LP_AON_GPIO_MUX_SEL_Pos = 0x0 + // Bit mask of SEL field. + LP_AON_GPIO_MUX_SEL_Msk = 0xff + + // GPIO_HOLD0: need_des + // Position of GPIO_HOLD0 field. + LP_AON_GPIO_HOLD0_GPIO_HOLD0_Pos = 0x0 + // Bit mask of GPIO_HOLD0 field. + LP_AON_GPIO_HOLD0_GPIO_HOLD0_Msk = 0xffffffff + + // GPIO_HOLD1: need_des + // Position of GPIO_HOLD1 field. + LP_AON_GPIO_HOLD1_GPIO_HOLD1_Pos = 0x0 + // Bit mask of GPIO_HOLD1 field. + LP_AON_GPIO_HOLD1_GPIO_HOLD1_Msk = 0xffffffff + + // SYS_CFG: need_des + // Position of ANA_FIB_SWD_ENABLE field. + LP_AON_SYS_CFG_ANA_FIB_SWD_ENABLE_Pos = 0x0 + // Bit mask of ANA_FIB_SWD_ENABLE field. + LP_AON_SYS_CFG_ANA_FIB_SWD_ENABLE_Msk = 0x1 + // Bit ANA_FIB_SWD_ENABLE. + LP_AON_SYS_CFG_ANA_FIB_SWD_ENABLE = 0x1 + // Position of ANA_FIB_CK_GLITCH_ENABLE field. + LP_AON_SYS_CFG_ANA_FIB_CK_GLITCH_ENABLE_Pos = 0x1 + // Bit mask of ANA_FIB_CK_GLITCH_ENABLE field. + LP_AON_SYS_CFG_ANA_FIB_CK_GLITCH_ENABLE_Msk = 0x2 + // Bit ANA_FIB_CK_GLITCH_ENABLE. + LP_AON_SYS_CFG_ANA_FIB_CK_GLITCH_ENABLE = 0x2 + // Position of ANA_FIB_BOD_ENABLE field. + LP_AON_SYS_CFG_ANA_FIB_BOD_ENABLE_Pos = 0x2 + // Bit mask of ANA_FIB_BOD_ENABLE field. + LP_AON_SYS_CFG_ANA_FIB_BOD_ENABLE_Msk = 0x4 + // Bit ANA_FIB_BOD_ENABLE. + LP_AON_SYS_CFG_ANA_FIB_BOD_ENABLE = 0x4 + // Position of FORCE_DOWNLOAD_BOOT field. + LP_AON_SYS_CFG_FORCE_DOWNLOAD_BOOT_Pos = 0x1e + // Bit mask of FORCE_DOWNLOAD_BOOT field. + LP_AON_SYS_CFG_FORCE_DOWNLOAD_BOOT_Msk = 0x40000000 + // Bit FORCE_DOWNLOAD_BOOT. + LP_AON_SYS_CFG_FORCE_DOWNLOAD_BOOT = 0x40000000 + // Position of HPSYS_SW_RESET field. + LP_AON_SYS_CFG_HPSYS_SW_RESET_Pos = 0x1f + // Bit mask of HPSYS_SW_RESET field. + LP_AON_SYS_CFG_HPSYS_SW_RESET_Msk = 0x80000000 + // Bit HPSYS_SW_RESET. + LP_AON_SYS_CFG_HPSYS_SW_RESET = 0x80000000 + + // CPUCORE0_CFG: need_des + // Position of CPU_CORE0_SW_STALL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_STALL_Pos = 0x0 + // Bit mask of CPU_CORE0_SW_STALL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_STALL_Msk = 0xff + // Position of CPU_CORE0_SW_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_RESET_Pos = 0x1c + // Bit mask of CPU_CORE0_SW_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_RESET_Msk = 0x10000000 + // Bit CPU_CORE0_SW_RESET. + LP_AON_CPUCORE0_CFG_CPU_CORE0_SW_RESET = 0x10000000 + // Position of CPU_CORE0_OCD_HALT_ON_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET_Pos = 0x1d + // Bit mask of CPU_CORE0_OCD_HALT_ON_RESET field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET_Msk = 0x20000000 + // Bit CPU_CORE0_OCD_HALT_ON_RESET. + LP_AON_CPUCORE0_CFG_CPU_CORE0_OCD_HALT_ON_RESET = 0x20000000 + // Position of CPU_CORE0_STAT_VECTOR_SEL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL_Pos = 0x1e + // Bit mask of CPU_CORE0_STAT_VECTOR_SEL field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL_Msk = 0x40000000 + // Bit CPU_CORE0_STAT_VECTOR_SEL. + LP_AON_CPUCORE0_CFG_CPU_CORE0_STAT_VECTOR_SEL = 0x40000000 + // Position of CPU_CORE0_DRESET_MASK field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_DRESET_MASK_Pos = 0x1f + // Bit mask of CPU_CORE0_DRESET_MASK field. + LP_AON_CPUCORE0_CFG_CPU_CORE0_DRESET_MASK_Msk = 0x80000000 + // Bit CPU_CORE0_DRESET_MASK. + LP_AON_CPUCORE0_CFG_CPU_CORE0_DRESET_MASK = 0x80000000 + + // IO_MUX: need_des + // Position of PULL_LDO field. + LP_AON_IO_MUX_PULL_LDO_Pos = 0x1c + // Bit mask of PULL_LDO field. + LP_AON_IO_MUX_PULL_LDO_Msk = 0x70000000 + // Position of RESET_DISABLE field. + LP_AON_IO_MUX_RESET_DISABLE_Pos = 0x1f + // Bit mask of RESET_DISABLE field. + LP_AON_IO_MUX_RESET_DISABLE_Msk = 0x80000000 + // Bit RESET_DISABLE. + LP_AON_IO_MUX_RESET_DISABLE = 0x80000000 + + // EXT_WAKEUP_CNTL: need_des + // Position of EXT_WAKEUP_STATUS field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_Pos = 0x0 + // Bit mask of EXT_WAKEUP_STATUS field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_Msk = 0xff + // Position of EXT_WAKEUP_STATUS_CLR field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR_Pos = 0xe + // Bit mask of EXT_WAKEUP_STATUS_CLR field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR_Msk = 0x4000 + // Bit EXT_WAKEUP_STATUS_CLR. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR = 0x4000 + // Position of EXT_WAKEUP_SEL field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_SEL_Pos = 0xf + // Bit mask of EXT_WAKEUP_SEL field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_SEL_Msk = 0x7f8000 + // Position of EXT_WAKEUP_LV field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_LV_Pos = 0x17 + // Bit mask of EXT_WAKEUP_LV field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_LV_Msk = 0x7f800000 + // Position of EXT_WAKEUP_FILTER field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER_Pos = 0x1f + // Bit mask of EXT_WAKEUP_FILTER field. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER_Msk = 0x80000000 + // Bit EXT_WAKEUP_FILTER. + LP_AON_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER = 0x80000000 + + // USB: need_des + // Position of RESET_DISABLE field. + LP_AON_USB_RESET_DISABLE_Pos = 0x1f + // Bit mask of RESET_DISABLE field. + LP_AON_USB_RESET_DISABLE_Msk = 0x80000000 + // Bit RESET_DISABLE. + LP_AON_USB_RESET_DISABLE = 0x80000000 + + // LPBUS: need_des + // Position of FAST_MEM_WPULSE field. + LP_AON_LPBUS_FAST_MEM_WPULSE_Pos = 0x10 + // Bit mask of FAST_MEM_WPULSE field. + LP_AON_LPBUS_FAST_MEM_WPULSE_Msk = 0x70000 + // Position of FAST_MEM_WA field. + LP_AON_LPBUS_FAST_MEM_WA_Pos = 0x13 + // Bit mask of FAST_MEM_WA field. + LP_AON_LPBUS_FAST_MEM_WA_Msk = 0x380000 + // Position of FAST_MEM_RA field. + LP_AON_LPBUS_FAST_MEM_RA_Pos = 0x16 + // Bit mask of FAST_MEM_RA field. + LP_AON_LPBUS_FAST_MEM_RA_Msk = 0xc00000 + // Position of FAST_MEM_RM field. + LP_AON_LPBUS_FAST_MEM_RM_Pos = 0x18 + // Bit mask of FAST_MEM_RM field. + LP_AON_LPBUS_FAST_MEM_RM_Msk = 0xf000000 + // Position of FAST_MEM_MUX_FSM_IDLE field. + LP_AON_LPBUS_FAST_MEM_MUX_FSM_IDLE_Pos = 0x1c + // Bit mask of FAST_MEM_MUX_FSM_IDLE field. + LP_AON_LPBUS_FAST_MEM_MUX_FSM_IDLE_Msk = 0x10000000 + // Bit FAST_MEM_MUX_FSM_IDLE. + LP_AON_LPBUS_FAST_MEM_MUX_FSM_IDLE = 0x10000000 + // Position of FAST_MEM_MUX_SEL_STATUS field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_STATUS_Pos = 0x1d + // Bit mask of FAST_MEM_MUX_SEL_STATUS field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_STATUS_Msk = 0x20000000 + // Bit FAST_MEM_MUX_SEL_STATUS. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_STATUS = 0x20000000 + // Position of FAST_MEM_MUX_SEL_UPDATE field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_UPDATE_Pos = 0x1e + // Bit mask of FAST_MEM_MUX_SEL_UPDATE field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_UPDATE_Msk = 0x40000000 + // Bit FAST_MEM_MUX_SEL_UPDATE. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_UPDATE = 0x40000000 + // Position of FAST_MEM_MUX_SEL field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_Pos = 0x1f + // Bit mask of FAST_MEM_MUX_SEL field. + LP_AON_LPBUS_FAST_MEM_MUX_SEL_Msk = 0x80000000 + // Bit FAST_MEM_MUX_SEL. + LP_AON_LPBUS_FAST_MEM_MUX_SEL = 0x80000000 + + // SDIO_ACTIVE: need_des + // Position of SDIO_ACT_DNUM field. + LP_AON_SDIO_ACTIVE_SDIO_ACT_DNUM_Pos = 0x16 + // Bit mask of SDIO_ACT_DNUM field. + LP_AON_SDIO_ACTIVE_SDIO_ACT_DNUM_Msk = 0xffc00000 + + // LPCORE: need_des + // Position of ETM_WAKEUP_FLAG_CLR field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_Pos = 0x0 + // Bit mask of ETM_WAKEUP_FLAG_CLR field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_Msk = 0x1 + // Bit ETM_WAKEUP_FLAG_CLR. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR = 0x1 + // Position of ETM_WAKEUP_FLAG field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_Pos = 0x1 + // Bit mask of ETM_WAKEUP_FLAG field. + LP_AON_LPCORE_ETM_WAKEUP_FLAG_Msk = 0x2 + // Bit ETM_WAKEUP_FLAG. + LP_AON_LPCORE_ETM_WAKEUP_FLAG = 0x2 + // Position of DISABLE field. + LP_AON_LPCORE_DISABLE_Pos = 0x1f + // Bit mask of DISABLE field. + LP_AON_LPCORE_DISABLE_Msk = 0x80000000 + // Bit DISABLE. + LP_AON_LPCORE_DISABLE = 0x80000000 + + // SAR_CCT: need_des + // Position of SAR2_PWDET_CCT field. + LP_AON_SAR_CCT_SAR2_PWDET_CCT_Pos = 0x1d + // Bit mask of SAR2_PWDET_CCT field. + LP_AON_SAR_CCT_SAR2_PWDET_CCT_Msk = 0xe0000000 + + // JTAG_SEL: need_des + // Position of SOFT field. + LP_AON_JTAG_SEL_SOFT_Pos = 0x1f + // Bit mask of SOFT field. + LP_AON_JTAG_SEL_SOFT_Msk = 0x80000000 + // Bit SOFT. + LP_AON_JTAG_SEL_SOFT = 0x80000000 + + // DATE: need_des + // Position of DATE field. + LP_AON_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_AON_DATE_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_AON_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_AON_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_AON_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_APM: Low-power Access Permission Management Controller +const ( + // REGION_FILTER_EN: Region filter enable register + // Position of REGION_FILTER_EN field. + LP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Pos = 0x0 + // Bit mask of REGION_FILTER_EN field. + LP_APM_REGION_FILTER_EN_REGION_FILTER_EN_Msk = 0x3 + + // REGION0_ADDR_START: Region address register + // Position of REGION0_ADDR_START field. + LP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Pos = 0x0 + // Bit mask of REGION0_ADDR_START field. + LP_APM_REGION0_ADDR_START_REGION0_ADDR_START_Msk = 0xffffffff + + // REGION0_ADDR_END: Region address register + // Position of REGION0_ADDR_END field. + LP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Pos = 0x0 + // Bit mask of REGION0_ADDR_END field. + LP_APM_REGION0_ADDR_END_REGION0_ADDR_END_Msk = 0xffffffff + + // REGION0_PMS_ATTR: Region access authority attribute register + // Position of REGION0_R0_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION0_R0_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X_Msk = 0x1 + // Bit REGION0_R0_PMS_X. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_X = 0x1 + // Position of REGION0_R0_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION0_R0_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W_Msk = 0x2 + // Bit REGION0_R0_PMS_W. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_W = 0x2 + // Position of REGION0_R0_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION0_R0_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R_Msk = 0x4 + // Bit REGION0_R0_PMS_R. + LP_APM_REGION0_PMS_ATTR_REGION0_R0_PMS_R = 0x4 + // Position of REGION0_R1_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION0_R1_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X_Msk = 0x10 + // Bit REGION0_R1_PMS_X. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_X = 0x10 + // Position of REGION0_R1_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION0_R1_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W_Msk = 0x20 + // Bit REGION0_R1_PMS_W. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_W = 0x20 + // Position of REGION0_R1_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION0_R1_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R_Msk = 0x40 + // Bit REGION0_R1_PMS_R. + LP_APM_REGION0_PMS_ATTR_REGION0_R1_PMS_R = 0x40 + // Position of REGION0_R2_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION0_R2_PMS_X field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X_Msk = 0x100 + // Bit REGION0_R2_PMS_X. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_X = 0x100 + // Position of REGION0_R2_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION0_R2_PMS_W field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W_Msk = 0x200 + // Bit REGION0_R2_PMS_W. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_W = 0x200 + // Position of REGION0_R2_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Pos = 0xa + // Bit mask of REGION0_R2_PMS_R field. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R_Msk = 0x400 + // Bit REGION0_R2_PMS_R. + LP_APM_REGION0_PMS_ATTR_REGION0_R2_PMS_R = 0x400 + + // REGION1_ADDR_START: Region address register + // Position of REGION1_ADDR_START field. + LP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Pos = 0x0 + // Bit mask of REGION1_ADDR_START field. + LP_APM_REGION1_ADDR_START_REGION1_ADDR_START_Msk = 0xffffffff + + // REGION1_ADDR_END: Region address register + // Position of REGION1_ADDR_END field. + LP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Pos = 0x0 + // Bit mask of REGION1_ADDR_END field. + LP_APM_REGION1_ADDR_END_REGION1_ADDR_END_Msk = 0xffffffff + + // REGION1_PMS_ATTR: Region access authority attribute register + // Position of REGION1_R0_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Pos = 0x0 + // Bit mask of REGION1_R0_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X_Msk = 0x1 + // Bit REGION1_R0_PMS_X. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_X = 0x1 + // Position of REGION1_R0_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Pos = 0x1 + // Bit mask of REGION1_R0_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W_Msk = 0x2 + // Bit REGION1_R0_PMS_W. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_W = 0x2 + // Position of REGION1_R0_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Pos = 0x2 + // Bit mask of REGION1_R0_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R_Msk = 0x4 + // Bit REGION1_R0_PMS_R. + LP_APM_REGION1_PMS_ATTR_REGION1_R0_PMS_R = 0x4 + // Position of REGION1_R1_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Pos = 0x4 + // Bit mask of REGION1_R1_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X_Msk = 0x10 + // Bit REGION1_R1_PMS_X. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_X = 0x10 + // Position of REGION1_R1_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Pos = 0x5 + // Bit mask of REGION1_R1_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W_Msk = 0x20 + // Bit REGION1_R1_PMS_W. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_W = 0x20 + // Position of REGION1_R1_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Pos = 0x6 + // Bit mask of REGION1_R1_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R_Msk = 0x40 + // Bit REGION1_R1_PMS_R. + LP_APM_REGION1_PMS_ATTR_REGION1_R1_PMS_R = 0x40 + // Position of REGION1_R2_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Pos = 0x8 + // Bit mask of REGION1_R2_PMS_X field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X_Msk = 0x100 + // Bit REGION1_R2_PMS_X. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_X = 0x100 + // Position of REGION1_R2_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Pos = 0x9 + // Bit mask of REGION1_R2_PMS_W field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W_Msk = 0x200 + // Bit REGION1_R2_PMS_W. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_W = 0x200 + // Position of REGION1_R2_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Pos = 0xa + // Bit mask of REGION1_R2_PMS_R field. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R_Msk = 0x400 + // Bit REGION1_R2_PMS_R. + LP_APM_REGION1_PMS_ATTR_REGION1_R2_PMS_R = 0x400 + + // FUNC_CTRL: PMS function control register + // Position of M0_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Pos = 0x0 + // Bit mask of M0_PMS_FUNC_EN field. + LP_APM_FUNC_CTRL_M0_PMS_FUNC_EN_Msk = 0x1 + // Bit M0_PMS_FUNC_EN. + LP_APM_FUNC_CTRL_M0_PMS_FUNC_EN = 0x1 + + // M0_STATUS: M0 status register + // Position of M0_EXCEPTION_STATUS field. + LP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Pos = 0x0 + // Bit mask of M0_EXCEPTION_STATUS field. + LP_APM_M0_STATUS_M0_EXCEPTION_STATUS_Msk = 0x3 + + // M0_STATUS_CLR: M0 status clear register + // Position of M0_REGION_STATUS_CLR field. + LP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Pos = 0x0 + // Bit mask of M0_REGION_STATUS_CLR field. + LP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR_Msk = 0x1 + // Bit M0_REGION_STATUS_CLR. + LP_APM_M0_STATUS_CLR_M0_REGION_STATUS_CLR = 0x1 + + // M0_EXCEPTION_INFO0: M0 exception_info0 register + // Position of M0_EXCEPTION_REGION field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Pos = 0x0 + // Bit mask of M0_EXCEPTION_REGION field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_REGION_Msk = 0x3 + // Position of M0_EXCEPTION_MODE field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Pos = 0x10 + // Bit mask of M0_EXCEPTION_MODE field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_MODE_Msk = 0x30000 + // Position of M0_EXCEPTION_ID field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Pos = 0x12 + // Bit mask of M0_EXCEPTION_ID field. + LP_APM_M0_EXCEPTION_INFO0_M0_EXCEPTION_ID_Msk = 0x7c0000 + + // M0_EXCEPTION_INFO1: M0 exception_info1 register + // Position of M0_EXCEPTION_ADDR field. + LP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Pos = 0x0 + // Bit mask of M0_EXCEPTION_ADDR field. + LP_APM_M0_EXCEPTION_INFO1_M0_EXCEPTION_ADDR_Msk = 0xffffffff + + // INT_EN: APM interrupt enable register + // Position of M0_APM_INT_EN field. + LP_APM_INT_EN_M0_APM_INT_EN_Pos = 0x0 + // Bit mask of M0_APM_INT_EN field. + LP_APM_INT_EN_M0_APM_INT_EN_Msk = 0x1 + // Bit M0_APM_INT_EN. + LP_APM_INT_EN_M0_APM_INT_EN = 0x1 + + // CLOCK_GATE: clock gating register + // Position of CLK_EN field. + LP_APM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + LP_APM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + LP_APM_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + LP_APM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_APM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for LP_CLKRST: LP_CLKRST Peripheral +const ( + // LP_CLK_CONF: need_des + // Position of SLOW_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_SLOW_CLK_SEL_Pos = 0x0 + // Bit mask of SLOW_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_SLOW_CLK_SEL_Msk = 0x3 + // Position of FAST_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_FAST_CLK_SEL_Pos = 0x2 + // Bit mask of FAST_CLK_SEL field. + LP_CLKRST_LP_CLK_CONF_FAST_CLK_SEL_Msk = 0xc + // Position of LP_PERI_DIV_NUM field. + LP_CLKRST_LP_CLK_CONF_LP_PERI_DIV_NUM_Pos = 0x4 + // Bit mask of LP_PERI_DIV_NUM field. + LP_CLKRST_LP_CLK_CONF_LP_PERI_DIV_NUM_Msk = 0xff0 + + // LP_CLK_PO_EN: need_des + // Position of AON_SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_SLOW_OEN_Pos = 0x0 + // Bit mask of AON_SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_SLOW_OEN_Msk = 0x1 + // Bit AON_SLOW_OEN. + LP_CLKRST_LP_CLK_PO_EN_AON_SLOW_OEN = 0x1 + // Position of AON_FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_FAST_OEN_Pos = 0x1 + // Bit mask of AON_FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_AON_FAST_OEN_Msk = 0x2 + // Bit AON_FAST_OEN. + LP_CLKRST_LP_CLK_PO_EN_AON_FAST_OEN = 0x2 + // Position of SOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SOSC_OEN_Pos = 0x2 + // Bit mask of SOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SOSC_OEN_Msk = 0x4 + // Bit SOSC_OEN. + LP_CLKRST_LP_CLK_PO_EN_SOSC_OEN = 0x4 + // Position of FOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FOSC_OEN_Pos = 0x3 + // Bit mask of FOSC_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FOSC_OEN_Msk = 0x8 + // Bit FOSC_OEN. + LP_CLKRST_LP_CLK_PO_EN_FOSC_OEN = 0x8 + // Position of OSC32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_OSC32K_OEN_Pos = 0x4 + // Bit mask of OSC32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_OSC32K_OEN_Msk = 0x10 + // Bit OSC32K_OEN. + LP_CLKRST_LP_CLK_PO_EN_OSC32K_OEN = 0x10 + // Position of XTAL32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_XTAL32K_OEN_Pos = 0x5 + // Bit mask of XTAL32K_OEN field. + LP_CLKRST_LP_CLK_PO_EN_XTAL32K_OEN_Msk = 0x20 + // Bit XTAL32K_OEN. + LP_CLKRST_LP_CLK_PO_EN_XTAL32K_OEN = 0x20 + // Position of CORE_EFUSE_OEN field. + LP_CLKRST_LP_CLK_PO_EN_CORE_EFUSE_OEN_Pos = 0x6 + // Bit mask of CORE_EFUSE_OEN field. + LP_CLKRST_LP_CLK_PO_EN_CORE_EFUSE_OEN_Msk = 0x40 + // Bit CORE_EFUSE_OEN. + LP_CLKRST_LP_CLK_PO_EN_CORE_EFUSE_OEN = 0x40 + // Position of SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SLOW_OEN_Pos = 0x7 + // Bit mask of SLOW_OEN field. + LP_CLKRST_LP_CLK_PO_EN_SLOW_OEN_Msk = 0x80 + // Bit SLOW_OEN. + LP_CLKRST_LP_CLK_PO_EN_SLOW_OEN = 0x80 + // Position of FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FAST_OEN_Pos = 0x8 + // Bit mask of FAST_OEN field. + LP_CLKRST_LP_CLK_PO_EN_FAST_OEN_Msk = 0x100 + // Bit FAST_OEN. + LP_CLKRST_LP_CLK_PO_EN_FAST_OEN = 0x100 + // Position of RNG_OEN field. + LP_CLKRST_LP_CLK_PO_EN_RNG_OEN_Pos = 0x9 + // Bit mask of RNG_OEN field. + LP_CLKRST_LP_CLK_PO_EN_RNG_OEN_Msk = 0x200 + // Bit RNG_OEN. + LP_CLKRST_LP_CLK_PO_EN_RNG_OEN = 0x200 + // Position of LPBUS_OEN field. + LP_CLKRST_LP_CLK_PO_EN_LPBUS_OEN_Pos = 0xa + // Bit mask of LPBUS_OEN field. + LP_CLKRST_LP_CLK_PO_EN_LPBUS_OEN_Msk = 0x400 + // Bit LPBUS_OEN. + LP_CLKRST_LP_CLK_PO_EN_LPBUS_OEN = 0x400 + + // LP_CLK_EN: need_des + // Position of FAST_ORI_GATE field. + LP_CLKRST_LP_CLK_EN_FAST_ORI_GATE_Pos = 0x1f + // Bit mask of FAST_ORI_GATE field. + LP_CLKRST_LP_CLK_EN_FAST_ORI_GATE_Msk = 0x80000000 + // Bit FAST_ORI_GATE. + LP_CLKRST_LP_CLK_EN_FAST_ORI_GATE = 0x80000000 + + // LP_RST_EN: need_des + // Position of AON_EFUSE_CORE_RESET_EN field. + LP_CLKRST_LP_RST_EN_AON_EFUSE_CORE_RESET_EN_Pos = 0x1c + // Bit mask of AON_EFUSE_CORE_RESET_EN field. + LP_CLKRST_LP_RST_EN_AON_EFUSE_CORE_RESET_EN_Msk = 0x10000000 + // Bit AON_EFUSE_CORE_RESET_EN. + LP_CLKRST_LP_RST_EN_AON_EFUSE_CORE_RESET_EN = 0x10000000 + // Position of LP_TIMER_RESET_EN field. + LP_CLKRST_LP_RST_EN_LP_TIMER_RESET_EN_Pos = 0x1d + // Bit mask of LP_TIMER_RESET_EN field. + LP_CLKRST_LP_RST_EN_LP_TIMER_RESET_EN_Msk = 0x20000000 + // Bit LP_TIMER_RESET_EN. + LP_CLKRST_LP_RST_EN_LP_TIMER_RESET_EN = 0x20000000 + // Position of WDT_RESET_EN field. + LP_CLKRST_LP_RST_EN_WDT_RESET_EN_Pos = 0x1e + // Bit mask of WDT_RESET_EN field. + LP_CLKRST_LP_RST_EN_WDT_RESET_EN_Msk = 0x40000000 + // Bit WDT_RESET_EN. + LP_CLKRST_LP_RST_EN_WDT_RESET_EN = 0x40000000 + // Position of ANA_PERI_RESET_EN field. + LP_CLKRST_LP_RST_EN_ANA_PERI_RESET_EN_Pos = 0x1f + // Bit mask of ANA_PERI_RESET_EN field. + LP_CLKRST_LP_RST_EN_ANA_PERI_RESET_EN_Msk = 0x80000000 + // Bit ANA_PERI_RESET_EN. + LP_CLKRST_LP_RST_EN_ANA_PERI_RESET_EN = 0x80000000 + + // RESET_CAUSE: need_des + // Position of RESET_CAUSE field. + LP_CLKRST_RESET_CAUSE_RESET_CAUSE_Pos = 0x0 + // Bit mask of RESET_CAUSE field. + LP_CLKRST_RESET_CAUSE_RESET_CAUSE_Msk = 0x1f + // Position of CORE0_RESET_FLAG field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_Pos = 0x5 + // Bit mask of CORE0_RESET_FLAG field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_Msk = 0x20 + // Bit CORE0_RESET_FLAG. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG = 0x20 + // Position of CORE0_RESET_CAUSE_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_CAUSE_CLR_Pos = 0x1d + // Bit mask of CORE0_RESET_CAUSE_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_CAUSE_CLR_Msk = 0x20000000 + // Bit CORE0_RESET_CAUSE_CLR. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_CAUSE_CLR = 0x20000000 + // Position of CORE0_RESET_FLAG_SET field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_SET_Pos = 0x1e + // Bit mask of CORE0_RESET_FLAG_SET field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_SET_Msk = 0x40000000 + // Bit CORE0_RESET_FLAG_SET. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_SET = 0x40000000 + // Position of CORE0_RESET_FLAG_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_CLR_Pos = 0x1f + // Bit mask of CORE0_RESET_FLAG_CLR field. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_CLR_Msk = 0x80000000 + // Bit CORE0_RESET_FLAG_CLR. + LP_CLKRST_RESET_CAUSE_CORE0_RESET_FLAG_CLR = 0x80000000 + + // CPU_RESET: need_des + // Position of RTC_WDT_CPU_RESET_LENGTH field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_LENGTH_Pos = 0x16 + // Bit mask of RTC_WDT_CPU_RESET_LENGTH field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_LENGTH_Msk = 0x1c00000 + // Position of RTC_WDT_CPU_RESET_EN field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_EN_Pos = 0x19 + // Bit mask of RTC_WDT_CPU_RESET_EN field. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_EN_Msk = 0x2000000 + // Bit RTC_WDT_CPU_RESET_EN. + LP_CLKRST_CPU_RESET_RTC_WDT_CPU_RESET_EN = 0x2000000 + // Position of CPU_STALL_WAIT field. + LP_CLKRST_CPU_RESET_CPU_STALL_WAIT_Pos = 0x1a + // Bit mask of CPU_STALL_WAIT field. + LP_CLKRST_CPU_RESET_CPU_STALL_WAIT_Msk = 0x7c000000 + // Position of CPU_STALL_EN field. + LP_CLKRST_CPU_RESET_CPU_STALL_EN_Pos = 0x1f + // Bit mask of CPU_STALL_EN field. + LP_CLKRST_CPU_RESET_CPU_STALL_EN_Msk = 0x80000000 + // Bit CPU_STALL_EN. + LP_CLKRST_CPU_RESET_CPU_STALL_EN = 0x80000000 + + // FOSC_CNTL: need_des + // Position of FOSC_DFREQ field. + LP_CLKRST_FOSC_CNTL_FOSC_DFREQ_Pos = 0x16 + // Bit mask of FOSC_DFREQ field. + LP_CLKRST_FOSC_CNTL_FOSC_DFREQ_Msk = 0xffc00000 + + // RC32K_CNTL: need_des + // Position of RC32K_DFREQ field. + LP_CLKRST_RC32K_CNTL_RC32K_DFREQ_Pos = 0x16 + // Bit mask of RC32K_DFREQ field. + LP_CLKRST_RC32K_CNTL_RC32K_DFREQ_Msk = 0xffc00000 + + // CLK_TO_HP: need_des + // Position of ICG_HP_XTAL32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_XTAL32K_Pos = 0x1c + // Bit mask of ICG_HP_XTAL32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_XTAL32K_Msk = 0x10000000 + // Bit ICG_HP_XTAL32K. + LP_CLKRST_CLK_TO_HP_ICG_HP_XTAL32K = 0x10000000 + // Position of ICG_HP_SOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_SOSC_Pos = 0x1d + // Bit mask of ICG_HP_SOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_SOSC_Msk = 0x20000000 + // Bit ICG_HP_SOSC. + LP_CLKRST_CLK_TO_HP_ICG_HP_SOSC = 0x20000000 + // Position of ICG_HP_OSC32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_OSC32K_Pos = 0x1e + // Bit mask of ICG_HP_OSC32K field. + LP_CLKRST_CLK_TO_HP_ICG_HP_OSC32K_Msk = 0x40000000 + // Bit ICG_HP_OSC32K. + LP_CLKRST_CLK_TO_HP_ICG_HP_OSC32K = 0x40000000 + // Position of ICG_HP_FOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_FOSC_Pos = 0x1f + // Bit mask of ICG_HP_FOSC field. + LP_CLKRST_CLK_TO_HP_ICG_HP_FOSC_Msk = 0x80000000 + // Bit ICG_HP_FOSC. + LP_CLKRST_CLK_TO_HP_ICG_HP_FOSC = 0x80000000 + + // LPMEM_FORCE: need_des + // Position of LPMEM_CLK_FORCE_ON field. + LP_CLKRST_LPMEM_FORCE_LPMEM_CLK_FORCE_ON_Pos = 0x1f + // Bit mask of LPMEM_CLK_FORCE_ON field. + LP_CLKRST_LPMEM_FORCE_LPMEM_CLK_FORCE_ON_Msk = 0x80000000 + // Bit LPMEM_CLK_FORCE_ON. + LP_CLKRST_LPMEM_FORCE_LPMEM_CLK_FORCE_ON = 0x80000000 + + // LPPERI: need_des + // Position of LP_BLETIMER_DIV_NUM field. + LP_CLKRST_LPPERI_LP_BLETIMER_DIV_NUM_Pos = 0xc + // Bit mask of LP_BLETIMER_DIV_NUM field. + LP_CLKRST_LPPERI_LP_BLETIMER_DIV_NUM_Msk = 0xfff000 + // Position of LP_BLETIMER_32K_SEL field. + LP_CLKRST_LPPERI_LP_BLETIMER_32K_SEL_Pos = 0x18 + // Bit mask of LP_BLETIMER_32K_SEL field. + LP_CLKRST_LPPERI_LP_BLETIMER_32K_SEL_Msk = 0x3000000 + // Position of LP_SEL_OSC_SLOW field. + LP_CLKRST_LPPERI_LP_SEL_OSC_SLOW_Pos = 0x1a + // Bit mask of LP_SEL_OSC_SLOW field. + LP_CLKRST_LPPERI_LP_SEL_OSC_SLOW_Msk = 0x4000000 + // Bit LP_SEL_OSC_SLOW. + LP_CLKRST_LPPERI_LP_SEL_OSC_SLOW = 0x4000000 + // Position of LP_SEL_OSC_FAST field. + LP_CLKRST_LPPERI_LP_SEL_OSC_FAST_Pos = 0x1b + // Bit mask of LP_SEL_OSC_FAST field. + LP_CLKRST_LPPERI_LP_SEL_OSC_FAST_Msk = 0x8000000 + // Bit LP_SEL_OSC_FAST. + LP_CLKRST_LPPERI_LP_SEL_OSC_FAST = 0x8000000 + // Position of LP_SEL_XTAL field. + LP_CLKRST_LPPERI_LP_SEL_XTAL_Pos = 0x1c + // Bit mask of LP_SEL_XTAL field. + LP_CLKRST_LPPERI_LP_SEL_XTAL_Msk = 0x10000000 + // Bit LP_SEL_XTAL. + LP_CLKRST_LPPERI_LP_SEL_XTAL = 0x10000000 + // Position of LP_SEL_XTAL32K field. + LP_CLKRST_LPPERI_LP_SEL_XTAL32K_Pos = 0x1d + // Bit mask of LP_SEL_XTAL32K field. + LP_CLKRST_LPPERI_LP_SEL_XTAL32K_Msk = 0x20000000 + // Bit LP_SEL_XTAL32K. + LP_CLKRST_LPPERI_LP_SEL_XTAL32K = 0x20000000 + // Position of LP_I2C_CLK_SEL field. + LP_CLKRST_LPPERI_LP_I2C_CLK_SEL_Pos = 0x1e + // Bit mask of LP_I2C_CLK_SEL field. + LP_CLKRST_LPPERI_LP_I2C_CLK_SEL_Msk = 0x40000000 + // Bit LP_I2C_CLK_SEL. + LP_CLKRST_LPPERI_LP_I2C_CLK_SEL = 0x40000000 + // Position of LP_UART_CLK_SEL field. + LP_CLKRST_LPPERI_LP_UART_CLK_SEL_Pos = 0x1f + // Bit mask of LP_UART_CLK_SEL field. + LP_CLKRST_LPPERI_LP_UART_CLK_SEL_Msk = 0x80000000 + // Bit LP_UART_CLK_SEL. + LP_CLKRST_LPPERI_LP_UART_CLK_SEL = 0x80000000 + + // XTAL32K: need_des + // Position of DRES_XTAL32K field. + LP_CLKRST_XTAL32K_DRES_XTAL32K_Pos = 0x16 + // Bit mask of DRES_XTAL32K field. + LP_CLKRST_XTAL32K_DRES_XTAL32K_Msk = 0x1c00000 + // Position of DGM_XTAL32K field. + LP_CLKRST_XTAL32K_DGM_XTAL32K_Pos = 0x19 + // Bit mask of DGM_XTAL32K field. + LP_CLKRST_XTAL32K_DGM_XTAL32K_Msk = 0xe000000 + // Position of DBUF_XTAL32K field. + LP_CLKRST_XTAL32K_DBUF_XTAL32K_Pos = 0x1c + // Bit mask of DBUF_XTAL32K field. + LP_CLKRST_XTAL32K_DBUF_XTAL32K_Msk = 0x10000000 + // Bit DBUF_XTAL32K. + LP_CLKRST_XTAL32K_DBUF_XTAL32K = 0x10000000 + // Position of DAC_XTAL32K field. + LP_CLKRST_XTAL32K_DAC_XTAL32K_Pos = 0x1d + // Bit mask of DAC_XTAL32K field. + LP_CLKRST_XTAL32K_DAC_XTAL32K_Msk = 0xe0000000 + + // DATE: need_des + // Position of CLKRST_DATE field. + LP_CLKRST_DATE_CLKRST_DATE_Pos = 0x0 + // Bit mask of CLKRST_DATE field. + LP_CLKRST_DATE_CLKRST_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_CLKRST_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_CLKRST_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_CLKRST_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_TIMER: Low-power Timer +const ( + // TAR0_LOW: need_des + // Position of MAIN_TIMER_TAR_LOW0 field. + LP_TIMER_TAR0_LOW_MAIN_TIMER_TAR_LOW0_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_LOW0 field. + LP_TIMER_TAR0_LOW_MAIN_TIMER_TAR_LOW0_Msk = 0xffffffff + + // TAR0_HIGH: need_des + // Position of MAIN_TIMER_TAR_HIGH0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_HIGH0_Pos = 0x0 + // Bit mask of MAIN_TIMER_TAR_HIGH0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_HIGH0_Msk = 0xffff + // Position of MAIN_TIMER_TAR_EN0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0_Pos = 0x1f + // Bit mask of MAIN_TIMER_TAR_EN0 field. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0_Msk = 0x80000000 + // Bit MAIN_TIMER_TAR_EN0. + LP_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0 = 0x80000000 + + // UPDATE: need_des + // Position of MAIN_TIMER_UPDATE field. + LP_TIMER_UPDATE_MAIN_TIMER_UPDATE_Pos = 0x1c + // Bit mask of MAIN_TIMER_UPDATE field. + LP_TIMER_UPDATE_MAIN_TIMER_UPDATE_Msk = 0x10000000 + // Bit MAIN_TIMER_UPDATE. + LP_TIMER_UPDATE_MAIN_TIMER_UPDATE = 0x10000000 + // Position of MAIN_TIMER_XTAL_OFF field. + LP_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF_Pos = 0x1d + // Bit mask of MAIN_TIMER_XTAL_OFF field. + LP_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF_Msk = 0x20000000 + // Bit MAIN_TIMER_XTAL_OFF. + LP_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF = 0x20000000 + // Position of MAIN_TIMER_SYS_STALL field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_STALL_Pos = 0x1e + // Bit mask of MAIN_TIMER_SYS_STALL field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_STALL_Msk = 0x40000000 + // Bit MAIN_TIMER_SYS_STALL. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_STALL = 0x40000000 + // Position of MAIN_TIMER_SYS_RST field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_RST_Pos = 0x1f + // Bit mask of MAIN_TIMER_SYS_RST field. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_RST_Msk = 0x80000000 + // Bit MAIN_TIMER_SYS_RST. + LP_TIMER_UPDATE_MAIN_TIMER_SYS_RST = 0x80000000 + + // MAIN_BUF0_LOW: need_des + // Position of MAIN_TIMER_BUF0_LOW field. + LP_TIMER_MAIN_BUF0_LOW_MAIN_TIMER_BUF0_LOW_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF0_LOW field. + LP_TIMER_MAIN_BUF0_LOW_MAIN_TIMER_BUF0_LOW_Msk = 0xffffffff + + // MAIN_BUF0_HIGH: need_des + // Position of MAIN_TIMER_BUF0_HIGH field. + LP_TIMER_MAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF0_HIGH field. + LP_TIMER_MAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH_Msk = 0xffff + + // MAIN_BUF1_LOW: need_des + // Position of MAIN_TIMER_BUF1_LOW field. + LP_TIMER_MAIN_BUF1_LOW_MAIN_TIMER_BUF1_LOW_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF1_LOW field. + LP_TIMER_MAIN_BUF1_LOW_MAIN_TIMER_BUF1_LOW_Msk = 0xffffffff + + // MAIN_BUF1_HIGH: need_des + // Position of MAIN_TIMER_BUF1_HIGH field. + LP_TIMER_MAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH_Pos = 0x0 + // Bit mask of MAIN_TIMER_BUF1_HIGH field. + LP_TIMER_MAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH_Msk = 0xffff + + // MAIN_OVERFLOW: need_des + // Position of MAIN_TIMER_ALARM_LOAD field. + LP_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD_Pos = 0x1f + // Bit mask of MAIN_TIMER_ALARM_LOAD field. + LP_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD_Msk = 0x80000000 + // Bit MAIN_TIMER_ALARM_LOAD. + LP_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD = 0x80000000 + + // INT_RAW: need_des + // Position of OVERFLOW_RAW field. + LP_TIMER_INT_RAW_OVERFLOW_RAW_Pos = 0x1e + // Bit mask of OVERFLOW_RAW field. + LP_TIMER_INT_RAW_OVERFLOW_RAW_Msk = 0x40000000 + // Bit OVERFLOW_RAW. + LP_TIMER_INT_RAW_OVERFLOW_RAW = 0x40000000 + // Position of SOC_WAKEUP_INT_RAW field. + LP_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_RAW field. + LP_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_RAW. + LP_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW = 0x80000000 + + // INT_ST: need_des + // Position of OVERFLOW_ST field. + LP_TIMER_INT_ST_OVERFLOW_ST_Pos = 0x1e + // Bit mask of OVERFLOW_ST field. + LP_TIMER_INT_ST_OVERFLOW_ST_Msk = 0x40000000 + // Bit OVERFLOW_ST. + LP_TIMER_INT_ST_OVERFLOW_ST = 0x40000000 + // Position of SOC_WAKEUP_INT_ST field. + LP_TIMER_INT_ST_SOC_WAKEUP_INT_ST_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ST field. + LP_TIMER_INT_ST_SOC_WAKEUP_INT_ST_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ST. + LP_TIMER_INT_ST_SOC_WAKEUP_INT_ST = 0x80000000 + + // INT_ENA: need_des + // Position of OVERFLOW_ENA field. + LP_TIMER_INT_ENA_OVERFLOW_ENA_Pos = 0x1e + // Bit mask of OVERFLOW_ENA field. + LP_TIMER_INT_ENA_OVERFLOW_ENA_Msk = 0x40000000 + // Bit OVERFLOW_ENA. + LP_TIMER_INT_ENA_OVERFLOW_ENA = 0x40000000 + // Position of SOC_WAKEUP_INT_ENA field. + LP_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ENA field. + LP_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ENA. + LP_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA = 0x80000000 + + // INT_CLR: need_des + // Position of OVERFLOW_CLR field. + LP_TIMER_INT_CLR_OVERFLOW_CLR_Pos = 0x1e + // Bit mask of OVERFLOW_CLR field. + LP_TIMER_INT_CLR_OVERFLOW_CLR_Msk = 0x40000000 + // Bit OVERFLOW_CLR. + LP_TIMER_INT_CLR_OVERFLOW_CLR = 0x40000000 + // Position of SOC_WAKEUP_INT_CLR field. + LP_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_CLR field. + LP_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_CLR. + LP_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR = 0x80000000 + + // DATE: need_des + // Position of DATE field. + LP_TIMER_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LP_TIMER_DATE_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_TIMER_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_TIMER_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_TIMER_DATE_CLK_EN = 0x80000000 +) + +// Constants for LP_WDT: Low-power Watchdog Timer +const ( + // WDTCONFIG0: need_des + // Position of WDT_PAUSE_IN_SLP field. + LP_WDT_WDTCONFIG0_WDT_PAUSE_IN_SLP_Pos = 0x9 + // Bit mask of WDT_PAUSE_IN_SLP field. + LP_WDT_WDTCONFIG0_WDT_PAUSE_IN_SLP_Msk = 0x200 + // Bit WDT_PAUSE_IN_SLP. + LP_WDT_WDTCONFIG0_WDT_PAUSE_IN_SLP = 0x200 + // Position of WDT_APPCPU_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xa + // Bit mask of WDT_APPCPU_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x400 + // Bit WDT_APPCPU_RESET_EN. + LP_WDT_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x400 + // Position of WDT_PROCPU_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xb + // Bit mask of WDT_PROCPU_RESET_EN field. + LP_WDT_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x800 + // Bit WDT_PROCPU_RESET_EN. + LP_WDT_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x800 + // Position of WDT_FLASHBOOT_MOD_EN field. + LP_WDT_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xc + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + LP_WDT_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x1000 + // Bit WDT_FLASHBOOT_MOD_EN. + LP_WDT_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x1000 + // Position of WDT_SYS_RESET_LENGTH field. + LP_WDT_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xd + // Bit mask of WDT_SYS_RESET_LENGTH field. + LP_WDT_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0xe000 + // Position of WDT_CPU_RESET_LENGTH field. + LP_WDT_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x10 + // Bit mask of WDT_CPU_RESET_LENGTH field. + LP_WDT_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x70000 + // Position of WDT_STG3 field. + LP_WDT_WDTCONFIG0_WDT_STG3_Pos = 0x13 + // Bit mask of WDT_STG3 field. + LP_WDT_WDTCONFIG0_WDT_STG3_Msk = 0x380000 + // Position of WDT_STG2 field. + LP_WDT_WDTCONFIG0_WDT_STG2_Pos = 0x16 + // Bit mask of WDT_STG2 field. + LP_WDT_WDTCONFIG0_WDT_STG2_Msk = 0x1c00000 + // Position of WDT_STG1 field. + LP_WDT_WDTCONFIG0_WDT_STG1_Pos = 0x19 + // Bit mask of WDT_STG1 field. + LP_WDT_WDTCONFIG0_WDT_STG1_Msk = 0xe000000 + // Position of WDT_STG0 field. + LP_WDT_WDTCONFIG0_WDT_STG0_Pos = 0x1c + // Bit mask of WDT_STG0 field. + LP_WDT_WDTCONFIG0_WDT_STG0_Msk = 0x70000000 + // Position of WDT_EN field. + LP_WDT_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + LP_WDT_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + LP_WDT_WDTCONFIG0_WDT_EN = 0x80000000 + + // CONFIG1: need_des + // Position of WDT_STG0_HOLD field. + LP_WDT_CONFIG1_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + LP_WDT_CONFIG1_WDT_STG0_HOLD_Msk = 0xffffffff + + // CONFIG2: need_des + // Position of WDT_STG1_HOLD field. + LP_WDT_CONFIG2_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + LP_WDT_CONFIG2_WDT_STG1_HOLD_Msk = 0xffffffff + + // CONFIG3: need_des + // Position of WDT_STG2_HOLD field. + LP_WDT_CONFIG3_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + LP_WDT_CONFIG3_WDT_STG2_HOLD_Msk = 0xffffffff + + // CONFIG4: need_des + // Position of WDT_STG3_HOLD field. + LP_WDT_CONFIG4_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + LP_WDT_CONFIG4_WDT_STG3_HOLD_Msk = 0xffffffff + + // CONFIG5: need_des + // Position of CHIP_RESET_TARGET field. + LP_WDT_CONFIG5_CHIP_RESET_TARGET_Pos = 0x0 + // Bit mask of CHIP_RESET_TARGET field. + LP_WDT_CONFIG5_CHIP_RESET_TARGET_Msk = 0xff + // Position of CHIP_RESET_EN field. + LP_WDT_CONFIG5_CHIP_RESET_EN_Pos = 0x8 + // Bit mask of CHIP_RESET_EN field. + LP_WDT_CONFIG5_CHIP_RESET_EN_Msk = 0x100 + // Bit CHIP_RESET_EN. + LP_WDT_CONFIG5_CHIP_RESET_EN = 0x100 + // Position of CHIP_RESET_KEY field. + LP_WDT_CONFIG5_CHIP_RESET_KEY_Pos = 0x9 + // Bit mask of CHIP_RESET_KEY field. + LP_WDT_CONFIG5_CHIP_RESET_KEY_Msk = 0x1fe00 + + // WDTFEED: need_des + // Position of RTC_WDT_FEED field. + LP_WDT_WDTFEED_RTC_WDT_FEED_Pos = 0x1f + // Bit mask of RTC_WDT_FEED field. + LP_WDT_WDTFEED_RTC_WDT_FEED_Msk = 0x80000000 + // Bit RTC_WDT_FEED. + LP_WDT_WDTFEED_RTC_WDT_FEED = 0x80000000 + + // WDTWPROTECT: need_des + // Position of WDT_WKEY field. + LP_WDT_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + LP_WDT_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // SWD_CONF: need_des + // Position of SWD_RESET_FLAG field. + LP_WDT_SWD_CONF_SWD_RESET_FLAG_Pos = 0x0 + // Bit mask of SWD_RESET_FLAG field. + LP_WDT_SWD_CONF_SWD_RESET_FLAG_Msk = 0x1 + // Bit SWD_RESET_FLAG. + LP_WDT_SWD_CONF_SWD_RESET_FLAG = 0x1 + // Position of SWD_AUTO_FEED_EN field. + LP_WDT_SWD_CONF_SWD_AUTO_FEED_EN_Pos = 0x12 + // Bit mask of SWD_AUTO_FEED_EN field. + LP_WDT_SWD_CONF_SWD_AUTO_FEED_EN_Msk = 0x40000 + // Bit SWD_AUTO_FEED_EN. + LP_WDT_SWD_CONF_SWD_AUTO_FEED_EN = 0x40000 + // Position of SWD_RST_FLAG_CLR field. + LP_WDT_SWD_CONF_SWD_RST_FLAG_CLR_Pos = 0x13 + // Bit mask of SWD_RST_FLAG_CLR field. + LP_WDT_SWD_CONF_SWD_RST_FLAG_CLR_Msk = 0x80000 + // Bit SWD_RST_FLAG_CLR. + LP_WDT_SWD_CONF_SWD_RST_FLAG_CLR = 0x80000 + // Position of SWD_SIGNAL_WIDTH field. + LP_WDT_SWD_CONF_SWD_SIGNAL_WIDTH_Pos = 0x14 + // Bit mask of SWD_SIGNAL_WIDTH field. + LP_WDT_SWD_CONF_SWD_SIGNAL_WIDTH_Msk = 0x3ff00000 + // Position of SWD_DISABLE field. + LP_WDT_SWD_CONF_SWD_DISABLE_Pos = 0x1e + // Bit mask of SWD_DISABLE field. + LP_WDT_SWD_CONF_SWD_DISABLE_Msk = 0x40000000 + // Bit SWD_DISABLE. + LP_WDT_SWD_CONF_SWD_DISABLE = 0x40000000 + // Position of SWD_FEED field. + LP_WDT_SWD_CONF_SWD_FEED_Pos = 0x1f + // Bit mask of SWD_FEED field. + LP_WDT_SWD_CONF_SWD_FEED_Msk = 0x80000000 + // Bit SWD_FEED. + LP_WDT_SWD_CONF_SWD_FEED = 0x80000000 + + // SWD_WPROTECT: need_des + // Position of SWD_WKEY field. + LP_WDT_SWD_WPROTECT_SWD_WKEY_Pos = 0x0 + // Bit mask of SWD_WKEY field. + LP_WDT_SWD_WPROTECT_SWD_WKEY_Msk = 0xffffffff + + // INT_RAW: need_des + // Position of SUPER_WDT_INT_RAW field. + LP_WDT_INT_RAW_SUPER_WDT_INT_RAW_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_RAW field. + LP_WDT_INT_RAW_SUPER_WDT_INT_RAW_Msk = 0x40000000 + // Bit SUPER_WDT_INT_RAW. + LP_WDT_INT_RAW_SUPER_WDT_INT_RAW = 0x40000000 + // Position of LP_WDT_INT_RAW field. + LP_WDT_INT_RAW_LP_WDT_INT_RAW_Pos = 0x1f + // Bit mask of LP_WDT_INT_RAW field. + LP_WDT_INT_RAW_LP_WDT_INT_RAW_Msk = 0x80000000 + // Bit LP_WDT_INT_RAW. + LP_WDT_INT_RAW_LP_WDT_INT_RAW = 0x80000000 + + // INT_ST_RTC: need_des + // Position of SUPER_WDT_INT_ST field. + LP_WDT_INT_ST_RTC_SUPER_WDT_INT_ST_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_ST field. + LP_WDT_INT_ST_RTC_SUPER_WDT_INT_ST_Msk = 0x40000000 + // Bit SUPER_WDT_INT_ST. + LP_WDT_INT_ST_RTC_SUPER_WDT_INT_ST = 0x40000000 + // Position of WDT_INT_ST field. + LP_WDT_INT_ST_RTC_WDT_INT_ST_Pos = 0x1f + // Bit mask of WDT_INT_ST field. + LP_WDT_INT_ST_RTC_WDT_INT_ST_Msk = 0x80000000 + // Bit WDT_INT_ST. + LP_WDT_INT_ST_RTC_WDT_INT_ST = 0x80000000 + + // INT_ENA_RTC: need_des + // Position of SUPER_WDT_INT_ENA field. + LP_WDT_INT_ENA_RTC_SUPER_WDT_INT_ENA_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_ENA field. + LP_WDT_INT_ENA_RTC_SUPER_WDT_INT_ENA_Msk = 0x40000000 + // Bit SUPER_WDT_INT_ENA. + LP_WDT_INT_ENA_RTC_SUPER_WDT_INT_ENA = 0x40000000 + // Position of WDT_INT_ENA field. + LP_WDT_INT_ENA_RTC_WDT_INT_ENA_Pos = 0x1f + // Bit mask of WDT_INT_ENA field. + LP_WDT_INT_ENA_RTC_WDT_INT_ENA_Msk = 0x80000000 + // Bit WDT_INT_ENA. + LP_WDT_INT_ENA_RTC_WDT_INT_ENA = 0x80000000 + + // INT_CLR_RTC: need_des + // Position of SUPER_WDT_INT_CLR field. + LP_WDT_INT_CLR_RTC_SUPER_WDT_INT_CLR_Pos = 0x1e + // Bit mask of SUPER_WDT_INT_CLR field. + LP_WDT_INT_CLR_RTC_SUPER_WDT_INT_CLR_Msk = 0x40000000 + // Bit SUPER_WDT_INT_CLR. + LP_WDT_INT_CLR_RTC_SUPER_WDT_INT_CLR = 0x40000000 + // Position of WDT_INT_CLR field. + LP_WDT_INT_CLR_RTC_WDT_INT_CLR_Pos = 0x1f + // Bit mask of WDT_INT_CLR field. + LP_WDT_INT_CLR_RTC_WDT_INT_CLR_Msk = 0x80000000 + // Bit WDT_INT_CLR. + LP_WDT_INT_CLR_RTC_WDT_INT_CLR = 0x80000000 + + // DATE: need_des + // Position of LP_WDT_DATE field. + LP_WDT_DATE_LP_WDT_DATE_Pos = 0x0 + // Bit mask of LP_WDT_DATE field. + LP_WDT_DATE_LP_WDT_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + LP_WDT_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LP_WDT_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LP_WDT_DATE_CLK_EN = 0x80000000 +) + +// Constants for MCPWM0: Motor Control Pulse-Width Modulation 0 +const ( + // CLK_CFG: PWM clock prescaler register. + // Position of CLK_PRESCALE field. + MCPWM_CLK_CFG_CLK_PRESCALE_Pos = 0x0 + // Bit mask of CLK_PRESCALE field. + MCPWM_CLK_CFG_CLK_PRESCALE_Msk = 0xff + + // TIMER0_CFG0: PWM timer0 period and update method configuration register. + // Position of TIMER0_PRESCALE field. + MCPWM_TIMER0_CFG0_TIMER0_PRESCALE_Pos = 0x0 + // Bit mask of TIMER0_PRESCALE field. + MCPWM_TIMER0_CFG0_TIMER0_PRESCALE_Msk = 0xff + // Position of TIMER0_PERIOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_Pos = 0x8 + // Bit mask of TIMER0_PERIOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_Msk = 0xffff00 + // Position of TIMER0_PERIOD_UPMETHOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER0_PERIOD_UPMETHOD field. + MCPWM_TIMER0_CFG0_TIMER0_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER0_CFG1: PWM timer0 working mode and start/stop control configuration register. + // Position of TIMER0_START field. + MCPWM_TIMER0_CFG1_TIMER0_START_Pos = 0x0 + // Bit mask of TIMER0_START field. + MCPWM_TIMER0_CFG1_TIMER0_START_Msk = 0x7 + // Position of TIMER0_MOD field. + MCPWM_TIMER0_CFG1_TIMER0_MOD_Pos = 0x3 + // Bit mask of TIMER0_MOD field. + MCPWM_TIMER0_CFG1_TIMER0_MOD_Msk = 0x18 + + // TIMER0_SYNC: PWM timer0 sync function configuration register. + // Position of TIMER0_SYNCI_EN field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER0_SYNCI_EN field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCI_EN_Msk = 0x1 + // Bit TIMER0_SYNCI_EN. + MCPWM_TIMER0_SYNC_TIMER0_SYNCI_EN = 0x1 + // Position of SW field. + MCPWM_TIMER0_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + MCPWM_TIMER0_SYNC_SW_Msk = 0x2 + // Bit SW. + MCPWM_TIMER0_SYNC_SW = 0x2 + // Position of TIMER0_SYNCO_SEL field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER0_SYNCO_SEL field. + MCPWM_TIMER0_SYNC_TIMER0_SYNCO_SEL_Msk = 0xc + // Position of TIMER0_PHASE field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_Pos = 0x4 + // Bit mask of TIMER0_PHASE field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_Msk = 0xffff0 + // Position of TIMER0_PHASE_DIRECTION field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER0_PHASE_DIRECTION field. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER0_PHASE_DIRECTION. + MCPWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION = 0x100000 + + // TIMER0_STATUS: PWM timer0 status register. + // Position of TIMER0_VALUE field. + MCPWM_TIMER0_STATUS_TIMER0_VALUE_Pos = 0x0 + // Bit mask of TIMER0_VALUE field. + MCPWM_TIMER0_STATUS_TIMER0_VALUE_Msk = 0xffff + // Position of TIMER0_DIRECTION field. + MCPWM_TIMER0_STATUS_TIMER0_DIRECTION_Pos = 0x10 + // Bit mask of TIMER0_DIRECTION field. + MCPWM_TIMER0_STATUS_TIMER0_DIRECTION_Msk = 0x10000 + // Bit TIMER0_DIRECTION. + MCPWM_TIMER0_STATUS_TIMER0_DIRECTION = 0x10000 + + // TIMER1_CFG0: PWM timer1 period and update method configuration register. + // Position of TIMER1_PRESCALE field. + MCPWM_TIMER1_CFG0_TIMER1_PRESCALE_Pos = 0x0 + // Bit mask of TIMER1_PRESCALE field. + MCPWM_TIMER1_CFG0_TIMER1_PRESCALE_Msk = 0xff + // Position of TIMER1_PERIOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_Pos = 0x8 + // Bit mask of TIMER1_PERIOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_Msk = 0xffff00 + // Position of TIMER1_PERIOD_UPMETHOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER1_PERIOD_UPMETHOD field. + MCPWM_TIMER1_CFG0_TIMER1_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER1_CFG1: PWM timer1 working mode and start/stop control configuration register. + // Position of TIMER1_START field. + MCPWM_TIMER1_CFG1_TIMER1_START_Pos = 0x0 + // Bit mask of TIMER1_START field. + MCPWM_TIMER1_CFG1_TIMER1_START_Msk = 0x7 + // Position of TIMER1_MOD field. + MCPWM_TIMER1_CFG1_TIMER1_MOD_Pos = 0x3 + // Bit mask of TIMER1_MOD field. + MCPWM_TIMER1_CFG1_TIMER1_MOD_Msk = 0x18 + + // TIMER1_SYNC: PWM timer1 sync function configuration register. + // Position of TIMER1_SYNCI_EN field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER1_SYNCI_EN field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCI_EN_Msk = 0x1 + // Bit TIMER1_SYNCI_EN. + MCPWM_TIMER1_SYNC_TIMER1_SYNCI_EN = 0x1 + // Position of SW field. + MCPWM_TIMER1_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + MCPWM_TIMER1_SYNC_SW_Msk = 0x2 + // Bit SW. + MCPWM_TIMER1_SYNC_SW = 0x2 + // Position of TIMER1_SYNCO_SEL field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER1_SYNCO_SEL field. + MCPWM_TIMER1_SYNC_TIMER1_SYNCO_SEL_Msk = 0xc + // Position of TIMER1_PHASE field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_Pos = 0x4 + // Bit mask of TIMER1_PHASE field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_Msk = 0xffff0 + // Position of TIMER1_PHASE_DIRECTION field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER1_PHASE_DIRECTION field. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER1_PHASE_DIRECTION. + MCPWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION = 0x100000 + + // TIMER1_STATUS: PWM timer1 status register. + // Position of TIMER1_VALUE field. + MCPWM_TIMER1_STATUS_TIMER1_VALUE_Pos = 0x0 + // Bit mask of TIMER1_VALUE field. + MCPWM_TIMER1_STATUS_TIMER1_VALUE_Msk = 0xffff + // Position of TIMER1_DIRECTION field. + MCPWM_TIMER1_STATUS_TIMER1_DIRECTION_Pos = 0x10 + // Bit mask of TIMER1_DIRECTION field. + MCPWM_TIMER1_STATUS_TIMER1_DIRECTION_Msk = 0x10000 + // Bit TIMER1_DIRECTION. + MCPWM_TIMER1_STATUS_TIMER1_DIRECTION = 0x10000 + + // TIMER2_CFG0: PWM timer2 period and update method configuration register. + // Position of TIMER2_PRESCALE field. + MCPWM_TIMER2_CFG0_TIMER2_PRESCALE_Pos = 0x0 + // Bit mask of TIMER2_PRESCALE field. + MCPWM_TIMER2_CFG0_TIMER2_PRESCALE_Msk = 0xff + // Position of TIMER2_PERIOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_Pos = 0x8 + // Bit mask of TIMER2_PERIOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_Msk = 0xffff00 + // Position of TIMER2_PERIOD_UPMETHOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER2_PERIOD_UPMETHOD field. + MCPWM_TIMER2_CFG0_TIMER2_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER2_CFG1: PWM timer2 working mode and start/stop control configuration register. + // Position of TIMER2_START field. + MCPWM_TIMER2_CFG1_TIMER2_START_Pos = 0x0 + // Bit mask of TIMER2_START field. + MCPWM_TIMER2_CFG1_TIMER2_START_Msk = 0x7 + // Position of TIMER2_MOD field. + MCPWM_TIMER2_CFG1_TIMER2_MOD_Pos = 0x3 + // Bit mask of TIMER2_MOD field. + MCPWM_TIMER2_CFG1_TIMER2_MOD_Msk = 0x18 + + // TIMER2_SYNC: PWM timer2 sync function configuration register. + // Position of TIMER2_SYNCI_EN field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER2_SYNCI_EN field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCI_EN_Msk = 0x1 + // Bit TIMER2_SYNCI_EN. + MCPWM_TIMER2_SYNC_TIMER2_SYNCI_EN = 0x1 + // Position of SW field. + MCPWM_TIMER2_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + MCPWM_TIMER2_SYNC_SW_Msk = 0x2 + // Bit SW. + MCPWM_TIMER2_SYNC_SW = 0x2 + // Position of TIMER2_SYNCO_SEL field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER2_SYNCO_SEL field. + MCPWM_TIMER2_SYNC_TIMER2_SYNCO_SEL_Msk = 0xc + // Position of TIMER2_PHASE field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_Pos = 0x4 + // Bit mask of TIMER2_PHASE field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_Msk = 0xffff0 + // Position of TIMER2_PHASE_DIRECTION field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER2_PHASE_DIRECTION field. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER2_PHASE_DIRECTION. + MCPWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION = 0x100000 + + // TIMER2_STATUS: PWM timer2 status register. + // Position of TIMER2_VALUE field. + MCPWM_TIMER2_STATUS_TIMER2_VALUE_Pos = 0x0 + // Bit mask of TIMER2_VALUE field. + MCPWM_TIMER2_STATUS_TIMER2_VALUE_Msk = 0xffff + // Position of TIMER2_DIRECTION field. + MCPWM_TIMER2_STATUS_TIMER2_DIRECTION_Pos = 0x10 + // Bit mask of TIMER2_DIRECTION field. + MCPWM_TIMER2_STATUS_TIMER2_DIRECTION_Msk = 0x10000 + // Bit TIMER2_DIRECTION. + MCPWM_TIMER2_STATUS_TIMER2_DIRECTION = 0x10000 + + // TIMER_SYNCI_CFG: Synchronization input selection for three PWM timers. + // Position of TIMER0_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Pos = 0x0 + // Bit mask of TIMER0_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Msk = 0x7 + // Position of TIMER1_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Pos = 0x3 + // Bit mask of TIMER1_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Msk = 0x38 + // Position of TIMER2_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Pos = 0x6 + // Bit mask of TIMER2_SYNCISEL field. + MCPWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Msk = 0x1c0 + // Position of EXTERNAL_SYNCI0_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Pos = 0x9 + // Bit mask of EXTERNAL_SYNCI0_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Msk = 0x200 + // Bit EXTERNAL_SYNCI0_INVERT. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT = 0x200 + // Position of EXTERNAL_SYNCI1_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Pos = 0xa + // Bit mask of EXTERNAL_SYNCI1_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Msk = 0x400 + // Bit EXTERNAL_SYNCI1_INVERT. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT = 0x400 + // Position of EXTERNAL_SYNCI2_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Pos = 0xb + // Bit mask of EXTERNAL_SYNCI2_INVERT field. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Msk = 0x800 + // Bit EXTERNAL_SYNCI2_INVERT. + MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT = 0x800 + + // OPERATOR_TIMERSEL: Select specific timer for PWM operators. + // Position of OPERATOR0_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Pos = 0x0 + // Bit mask of OPERATOR0_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Msk = 0x3 + // Position of OPERATOR1_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Pos = 0x2 + // Bit mask of OPERATOR1_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Msk = 0xc + // Position of OPERATOR2_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Pos = 0x4 + // Bit mask of OPERATOR2_TIMERSEL field. + MCPWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Msk = 0x30 + + // GEN0_STMP_CFG: Transfer status and update method for time stamp registers A and B + // Position of CMPR0_A_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_CMPR0_A_UPMETHOD_Pos = 0x0 + // Bit mask of CMPR0_A_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_CMPR0_A_UPMETHOD_Msk = 0xf + // Position of CMPR0_B_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_CMPR0_B_UPMETHOD_Pos = 0x4 + // Bit mask of CMPR0_B_UPMETHOD field. + MCPWM_GEN0_STMP_CFG_CMPR0_B_UPMETHOD_Msk = 0xf0 + // Position of CMPR0_A_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_CMPR0_A_SHDW_FULL_Pos = 0x8 + // Bit mask of CMPR0_A_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_CMPR0_A_SHDW_FULL_Msk = 0x100 + // Bit CMPR0_A_SHDW_FULL. + MCPWM_GEN0_STMP_CFG_CMPR0_A_SHDW_FULL = 0x100 + // Position of CMPR0_B_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_CMPR0_B_SHDW_FULL_Pos = 0x9 + // Bit mask of CMPR0_B_SHDW_FULL field. + MCPWM_GEN0_STMP_CFG_CMPR0_B_SHDW_FULL_Msk = 0x200 + // Bit CMPR0_B_SHDW_FULL. + MCPWM_GEN0_STMP_CFG_CMPR0_B_SHDW_FULL = 0x200 + + // GEN0_TSTMP_A: Shadow register for register A. + // Position of CMPR0_A field. + MCPWM_GEN0_TSTMP_A_CMPR0_A_Pos = 0x0 + // Bit mask of CMPR0_A field. + MCPWM_GEN0_TSTMP_A_CMPR0_A_Msk = 0xffff + + // GEN0_TSTMP_B: Shadow register for register B. + // Position of CMPR0_B field. + MCPWM_GEN0_TSTMP_B_CMPR0_B_Pos = 0x0 + // Bit mask of CMPR0_B field. + MCPWM_GEN0_TSTMP_B_CMPR0_B_Msk = 0xffff + + // GEN0_CFG0: Fault event T0 and T1 handling + // Position of GEN0_CFG_UPMETHOD field. + MCPWM_GEN0_CFG0_GEN0_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN0_CFG_UPMETHOD field. + MCPWM_GEN0_CFG0_GEN0_CFG_UPMETHOD_Msk = 0xf + // Position of GEN0_T0_SEL field. + MCPWM_GEN0_CFG0_GEN0_T0_SEL_Pos = 0x4 + // Bit mask of GEN0_T0_SEL field. + MCPWM_GEN0_CFG0_GEN0_T0_SEL_Msk = 0x70 + // Position of GEN0_T1_SEL field. + MCPWM_GEN0_CFG0_GEN0_T1_SEL_Pos = 0x7 + // Bit mask of GEN0_T1_SEL field. + MCPWM_GEN0_CFG0_GEN0_T1_SEL_Msk = 0x380 + + // GEN0_FORCE: Permissives to force PWM0A and PWM0B outputs by software + // Position of GEN0_CNTUFORCE_UPMETHOD field. + MCPWM_GEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN0_CNTUFORCE_UPMETHOD field. + MCPWM_GEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN0_A_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN0_A_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN0_B_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN0_B_CNTUFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN0_A_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN0_A_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_Msk = 0x400 + // Bit GEN0_A_NCIFORCE. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE = 0x400 + // Position of GEN0_A_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN0_A_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN0_B_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN0_B_NCIFORCE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_Msk = 0x2000 + // Bit GEN0_B_NCIFORCE. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE = 0x2000 + // Position of GEN0_B_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN0_B_NCIFORCE_MODE field. + MCPWM_GEN0_FORCE_GEN0_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN0_A: Actions triggered by events on PWM0A + // Position of UTEZ field. + MCPWM_GEN0_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN0_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN0_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN0_A_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN0_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN0_A_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN0_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN0_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN0_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN0_A_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN0_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN0_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN0_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN0_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN0_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN0_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN0_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN0_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN0_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN0_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN0_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN0_A_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN0_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN0_A_DT1_Msk = 0xc00000 + + // GEN0_B: Actions triggered by events on PWM0B + // Position of UTEZ field. + MCPWM_GEN0_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN0_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN0_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN0_B_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN0_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN0_B_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN0_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN0_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN0_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN0_B_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN0_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN0_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN0_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN0_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN0_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN0_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN0_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN0_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN0_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN0_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN0_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN0_B_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN0_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN0_B_DT1_Msk = 0xc00000 + + // DT0_CFG: dead time type selection and configuration + // Position of DB0_FED_UPMETHOD field. + MCPWM_DT0_CFG_DB0_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DB0_FED_UPMETHOD field. + MCPWM_DT0_CFG_DB0_FED_UPMETHOD_Msk = 0xf + // Position of DB0_RED_UPMETHOD field. + MCPWM_DT0_CFG_DB0_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DB0_RED_UPMETHOD field. + MCPWM_DT0_CFG_DB0_RED_UPMETHOD_Msk = 0xf0 + // Position of DB0_DEB_MODE field. + MCPWM_DT0_CFG_DB0_DEB_MODE_Pos = 0x8 + // Bit mask of DB0_DEB_MODE field. + MCPWM_DT0_CFG_DB0_DEB_MODE_Msk = 0x100 + // Bit DB0_DEB_MODE. + MCPWM_DT0_CFG_DB0_DEB_MODE = 0x100 + // Position of DB0_A_OUTSWAP field. + MCPWM_DT0_CFG_DB0_A_OUTSWAP_Pos = 0x9 + // Bit mask of DB0_A_OUTSWAP field. + MCPWM_DT0_CFG_DB0_A_OUTSWAP_Msk = 0x200 + // Bit DB0_A_OUTSWAP. + MCPWM_DT0_CFG_DB0_A_OUTSWAP = 0x200 + // Position of DB0_B_OUTSWAP field. + MCPWM_DT0_CFG_DB0_B_OUTSWAP_Pos = 0xa + // Bit mask of DB0_B_OUTSWAP field. + MCPWM_DT0_CFG_DB0_B_OUTSWAP_Msk = 0x400 + // Bit DB0_B_OUTSWAP. + MCPWM_DT0_CFG_DB0_B_OUTSWAP = 0x400 + // Position of DB0_RED_INSEL field. + MCPWM_DT0_CFG_DB0_RED_INSEL_Pos = 0xb + // Bit mask of DB0_RED_INSEL field. + MCPWM_DT0_CFG_DB0_RED_INSEL_Msk = 0x800 + // Bit DB0_RED_INSEL. + MCPWM_DT0_CFG_DB0_RED_INSEL = 0x800 + // Position of DB0_FED_INSEL field. + MCPWM_DT0_CFG_DB0_FED_INSEL_Pos = 0xc + // Bit mask of DB0_FED_INSEL field. + MCPWM_DT0_CFG_DB0_FED_INSEL_Msk = 0x1000 + // Bit DB0_FED_INSEL. + MCPWM_DT0_CFG_DB0_FED_INSEL = 0x1000 + // Position of DB0_RED_OUTINVERT field. + MCPWM_DT0_CFG_DB0_RED_OUTINVERT_Pos = 0xd + // Bit mask of DB0_RED_OUTINVERT field. + MCPWM_DT0_CFG_DB0_RED_OUTINVERT_Msk = 0x2000 + // Bit DB0_RED_OUTINVERT. + MCPWM_DT0_CFG_DB0_RED_OUTINVERT = 0x2000 + // Position of DB0_FED_OUTINVERT field. + MCPWM_DT0_CFG_DB0_FED_OUTINVERT_Pos = 0xe + // Bit mask of DB0_FED_OUTINVERT field. + MCPWM_DT0_CFG_DB0_FED_OUTINVERT_Msk = 0x4000 + // Bit DB0_FED_OUTINVERT. + MCPWM_DT0_CFG_DB0_FED_OUTINVERT = 0x4000 + // Position of DB0_A_OUTBYPASS field. + MCPWM_DT0_CFG_DB0_A_OUTBYPASS_Pos = 0xf + // Bit mask of DB0_A_OUTBYPASS field. + MCPWM_DT0_CFG_DB0_A_OUTBYPASS_Msk = 0x8000 + // Bit DB0_A_OUTBYPASS. + MCPWM_DT0_CFG_DB0_A_OUTBYPASS = 0x8000 + // Position of DB0_B_OUTBYPASS field. + MCPWM_DT0_CFG_DB0_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DB0_B_OUTBYPASS field. + MCPWM_DT0_CFG_DB0_B_OUTBYPASS_Msk = 0x10000 + // Bit DB0_B_OUTBYPASS. + MCPWM_DT0_CFG_DB0_B_OUTBYPASS = 0x10000 + // Position of DB0_CLK_SEL field. + MCPWM_DT0_CFG_DB0_CLK_SEL_Pos = 0x11 + // Bit mask of DB0_CLK_SEL field. + MCPWM_DT0_CFG_DB0_CLK_SEL_Msk = 0x20000 + // Bit DB0_CLK_SEL. + MCPWM_DT0_CFG_DB0_CLK_SEL = 0x20000 + + // DT0_FED_CFG: Shadow register for falling edge delay (FED). + // Position of DB0_FED field. + MCPWM_DT0_FED_CFG_DB0_FED_Pos = 0x0 + // Bit mask of DB0_FED field. + MCPWM_DT0_FED_CFG_DB0_FED_Msk = 0xffff + + // DT0_RED_CFG: Shadow register for rising edge delay (RED). + // Position of DB0_RED field. + MCPWM_DT0_RED_CFG_DB0_RED_Pos = 0x0 + // Bit mask of DB0_RED field. + MCPWM_DT0_RED_CFG_DB0_RED_Msk = 0xffff + + // CARRIER0_CFG: Carrier enable and configuratoin + // Position of CHOPPER0_EN field. + MCPWM_CARRIER0_CFG_CHOPPER0_EN_Pos = 0x0 + // Bit mask of CHOPPER0_EN field. + MCPWM_CARRIER0_CFG_CHOPPER0_EN_Msk = 0x1 + // Bit CHOPPER0_EN. + MCPWM_CARRIER0_CFG_CHOPPER0_EN = 0x1 + // Position of CHOPPER0_PRESCALE field. + MCPWM_CARRIER0_CFG_CHOPPER0_PRESCALE_Pos = 0x1 + // Bit mask of CHOPPER0_PRESCALE field. + MCPWM_CARRIER0_CFG_CHOPPER0_PRESCALE_Msk = 0x1e + // Position of CHOPPER0_DUTY field. + MCPWM_CARRIER0_CFG_CHOPPER0_DUTY_Pos = 0x5 + // Bit mask of CHOPPER0_DUTY field. + MCPWM_CARRIER0_CFG_CHOPPER0_DUTY_Msk = 0xe0 + // Position of CHOPPER0_OSHTWTH field. + MCPWM_CARRIER0_CFG_CHOPPER0_OSHTWTH_Pos = 0x8 + // Bit mask of CHOPPER0_OSHTWTH field. + MCPWM_CARRIER0_CFG_CHOPPER0_OSHTWTH_Msk = 0xf00 + // Position of CHOPPER0_OUT_INVERT field. + MCPWM_CARRIER0_CFG_CHOPPER0_OUT_INVERT_Pos = 0xc + // Bit mask of CHOPPER0_OUT_INVERT field. + MCPWM_CARRIER0_CFG_CHOPPER0_OUT_INVERT_Msk = 0x1000 + // Bit CHOPPER0_OUT_INVERT. + MCPWM_CARRIER0_CFG_CHOPPER0_OUT_INVERT = 0x1000 + // Position of CHOPPER0_IN_INVERT field. + MCPWM_CARRIER0_CFG_CHOPPER0_IN_INVERT_Pos = 0xd + // Bit mask of CHOPPER0_IN_INVERT field. + MCPWM_CARRIER0_CFG_CHOPPER0_IN_INVERT_Msk = 0x2000 + // Bit CHOPPER0_IN_INVERT. + MCPWM_CARRIER0_CFG_CHOPPER0_IN_INVERT = 0x2000 + + // FH0_CFG0: Actions on PWM0A and PWM0B trip events + // Position of TZ0_SW_CBC field. + MCPWM_FH0_CFG0_TZ0_SW_CBC_Pos = 0x0 + // Bit mask of TZ0_SW_CBC field. + MCPWM_FH0_CFG0_TZ0_SW_CBC_Msk = 0x1 + // Bit TZ0_SW_CBC. + MCPWM_FH0_CFG0_TZ0_SW_CBC = 0x1 + // Position of TZ0_F2_CBC field. + MCPWM_FH0_CFG0_TZ0_F2_CBC_Pos = 0x1 + // Bit mask of TZ0_F2_CBC field. + MCPWM_FH0_CFG0_TZ0_F2_CBC_Msk = 0x2 + // Bit TZ0_F2_CBC. + MCPWM_FH0_CFG0_TZ0_F2_CBC = 0x2 + // Position of TZ0_F1_CBC field. + MCPWM_FH0_CFG0_TZ0_F1_CBC_Pos = 0x2 + // Bit mask of TZ0_F1_CBC field. + MCPWM_FH0_CFG0_TZ0_F1_CBC_Msk = 0x4 + // Bit TZ0_F1_CBC. + MCPWM_FH0_CFG0_TZ0_F1_CBC = 0x4 + // Position of TZ0_F0_CBC field. + MCPWM_FH0_CFG0_TZ0_F0_CBC_Pos = 0x3 + // Bit mask of TZ0_F0_CBC field. + MCPWM_FH0_CFG0_TZ0_F0_CBC_Msk = 0x8 + // Bit TZ0_F0_CBC. + MCPWM_FH0_CFG0_TZ0_F0_CBC = 0x8 + // Position of TZ0_SW_OST field. + MCPWM_FH0_CFG0_TZ0_SW_OST_Pos = 0x4 + // Bit mask of TZ0_SW_OST field. + MCPWM_FH0_CFG0_TZ0_SW_OST_Msk = 0x10 + // Bit TZ0_SW_OST. + MCPWM_FH0_CFG0_TZ0_SW_OST = 0x10 + // Position of TZ0_F2_OST field. + MCPWM_FH0_CFG0_TZ0_F2_OST_Pos = 0x5 + // Bit mask of TZ0_F2_OST field. + MCPWM_FH0_CFG0_TZ0_F2_OST_Msk = 0x20 + // Bit TZ0_F2_OST. + MCPWM_FH0_CFG0_TZ0_F2_OST = 0x20 + // Position of TZ0_F1_OST field. + MCPWM_FH0_CFG0_TZ0_F1_OST_Pos = 0x6 + // Bit mask of TZ0_F1_OST field. + MCPWM_FH0_CFG0_TZ0_F1_OST_Msk = 0x40 + // Bit TZ0_F1_OST. + MCPWM_FH0_CFG0_TZ0_F1_OST = 0x40 + // Position of TZ0_F0_OST field. + MCPWM_FH0_CFG0_TZ0_F0_OST_Pos = 0x7 + // Bit mask of TZ0_F0_OST field. + MCPWM_FH0_CFG0_TZ0_F0_OST_Msk = 0x80 + // Bit TZ0_F0_OST. + MCPWM_FH0_CFG0_TZ0_F0_OST = 0x80 + // Position of TZ0_A_CBC_D field. + MCPWM_FH0_CFG0_TZ0_A_CBC_D_Pos = 0x8 + // Bit mask of TZ0_A_CBC_D field. + MCPWM_FH0_CFG0_TZ0_A_CBC_D_Msk = 0x300 + // Position of TZ0_A_CBC_U field. + MCPWM_FH0_CFG0_TZ0_A_CBC_U_Pos = 0xa + // Bit mask of TZ0_A_CBC_U field. + MCPWM_FH0_CFG0_TZ0_A_CBC_U_Msk = 0xc00 + // Position of TZ0_A_OST_D field. + MCPWM_FH0_CFG0_TZ0_A_OST_D_Pos = 0xc + // Bit mask of TZ0_A_OST_D field. + MCPWM_FH0_CFG0_TZ0_A_OST_D_Msk = 0x3000 + // Position of TZ0_A_OST_U field. + MCPWM_FH0_CFG0_TZ0_A_OST_U_Pos = 0xe + // Bit mask of TZ0_A_OST_U field. + MCPWM_FH0_CFG0_TZ0_A_OST_U_Msk = 0xc000 + // Position of TZ0_B_CBC_D field. + MCPWM_FH0_CFG0_TZ0_B_CBC_D_Pos = 0x10 + // Bit mask of TZ0_B_CBC_D field. + MCPWM_FH0_CFG0_TZ0_B_CBC_D_Msk = 0x30000 + // Position of TZ0_B_CBC_U field. + MCPWM_FH0_CFG0_TZ0_B_CBC_U_Pos = 0x12 + // Bit mask of TZ0_B_CBC_U field. + MCPWM_FH0_CFG0_TZ0_B_CBC_U_Msk = 0xc0000 + // Position of TZ0_B_OST_D field. + MCPWM_FH0_CFG0_TZ0_B_OST_D_Pos = 0x14 + // Bit mask of TZ0_B_OST_D field. + MCPWM_FH0_CFG0_TZ0_B_OST_D_Msk = 0x300000 + // Position of TZ0_B_OST_U field. + MCPWM_FH0_CFG0_TZ0_B_OST_U_Pos = 0x16 + // Bit mask of TZ0_B_OST_U field. + MCPWM_FH0_CFG0_TZ0_B_OST_U_Msk = 0xc00000 + + // FH0_CFG1: Software triggers for fault handler actions + // Position of TZ0_CLR_OST field. + MCPWM_FH0_CFG1_TZ0_CLR_OST_Pos = 0x0 + // Bit mask of TZ0_CLR_OST field. + MCPWM_FH0_CFG1_TZ0_CLR_OST_Msk = 0x1 + // Bit TZ0_CLR_OST. + MCPWM_FH0_CFG1_TZ0_CLR_OST = 0x1 + // Position of TZ0_CBCPULSE field. + MCPWM_FH0_CFG1_TZ0_CBCPULSE_Pos = 0x1 + // Bit mask of TZ0_CBCPULSE field. + MCPWM_FH0_CFG1_TZ0_CBCPULSE_Msk = 0x6 + // Position of TZ0_FORCE_CBC field. + MCPWM_FH0_CFG1_TZ0_FORCE_CBC_Pos = 0x3 + // Bit mask of TZ0_FORCE_CBC field. + MCPWM_FH0_CFG1_TZ0_FORCE_CBC_Msk = 0x8 + // Bit TZ0_FORCE_CBC. + MCPWM_FH0_CFG1_TZ0_FORCE_CBC = 0x8 + // Position of TZ0_FORCE_OST field. + MCPWM_FH0_CFG1_TZ0_FORCE_OST_Pos = 0x4 + // Bit mask of TZ0_FORCE_OST field. + MCPWM_FH0_CFG1_TZ0_FORCE_OST_Msk = 0x10 + // Bit TZ0_FORCE_OST. + MCPWM_FH0_CFG1_TZ0_FORCE_OST = 0x10 + + // FH0_STATUS: Status of fault events. + // Position of TZ0_CBC_ON field. + MCPWM_FH0_STATUS_TZ0_CBC_ON_Pos = 0x0 + // Bit mask of TZ0_CBC_ON field. + MCPWM_FH0_STATUS_TZ0_CBC_ON_Msk = 0x1 + // Bit TZ0_CBC_ON. + MCPWM_FH0_STATUS_TZ0_CBC_ON = 0x1 + // Position of TZ0_OST_ON field. + MCPWM_FH0_STATUS_TZ0_OST_ON_Pos = 0x1 + // Bit mask of TZ0_OST_ON field. + MCPWM_FH0_STATUS_TZ0_OST_ON_Msk = 0x2 + // Bit TZ0_OST_ON. + MCPWM_FH0_STATUS_TZ0_OST_ON = 0x2 + + // GEN1_STMP_CFG: Transfer status and update method for time stamp registers A and B + // Position of CMPR1_A_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_CMPR1_A_UPMETHOD_Pos = 0x0 + // Bit mask of CMPR1_A_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_CMPR1_A_UPMETHOD_Msk = 0xf + // Position of CMPR1_B_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_CMPR1_B_UPMETHOD_Pos = 0x4 + // Bit mask of CMPR1_B_UPMETHOD field. + MCPWM_GEN1_STMP_CFG_CMPR1_B_UPMETHOD_Msk = 0xf0 + // Position of CMPR1_A_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_CMPR1_A_SHDW_FULL_Pos = 0x8 + // Bit mask of CMPR1_A_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_CMPR1_A_SHDW_FULL_Msk = 0x100 + // Bit CMPR1_A_SHDW_FULL. + MCPWM_GEN1_STMP_CFG_CMPR1_A_SHDW_FULL = 0x100 + // Position of CMPR1_B_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_CMPR1_B_SHDW_FULL_Pos = 0x9 + // Bit mask of CMPR1_B_SHDW_FULL field. + MCPWM_GEN1_STMP_CFG_CMPR1_B_SHDW_FULL_Msk = 0x200 + // Bit CMPR1_B_SHDW_FULL. + MCPWM_GEN1_STMP_CFG_CMPR1_B_SHDW_FULL = 0x200 + + // GEN1_TSTMP_A: Shadow register for register A. + // Position of CMPR1_A field. + MCPWM_GEN1_TSTMP_A_CMPR1_A_Pos = 0x0 + // Bit mask of CMPR1_A field. + MCPWM_GEN1_TSTMP_A_CMPR1_A_Msk = 0xffff + + // GEN1_TSTMP_B: Shadow register for register B. + // Position of CMPR1_B field. + MCPWM_GEN1_TSTMP_B_CMPR1_B_Pos = 0x0 + // Bit mask of CMPR1_B field. + MCPWM_GEN1_TSTMP_B_CMPR1_B_Msk = 0xffff + + // GEN1_CFG0: Fault event T0 and T1 handling + // Position of GEN1_CFG_UPMETHOD field. + MCPWM_GEN1_CFG0_GEN1_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN1_CFG_UPMETHOD field. + MCPWM_GEN1_CFG0_GEN1_CFG_UPMETHOD_Msk = 0xf + // Position of GEN1_T0_SEL field. + MCPWM_GEN1_CFG0_GEN1_T0_SEL_Pos = 0x4 + // Bit mask of GEN1_T0_SEL field. + MCPWM_GEN1_CFG0_GEN1_T0_SEL_Msk = 0x70 + // Position of GEN1_T1_SEL field. + MCPWM_GEN1_CFG0_GEN1_T1_SEL_Pos = 0x7 + // Bit mask of GEN1_T1_SEL field. + MCPWM_GEN1_CFG0_GEN1_T1_SEL_Msk = 0x380 + + // GEN1_FORCE: Permissives to force PWM1A and PWM1B outputs by software + // Position of GEN1_CNTUFORCE_UPMETHOD field. + MCPWM_GEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN1_CNTUFORCE_UPMETHOD field. + MCPWM_GEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN1_A_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN1_A_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN1_B_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN1_B_CNTUFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN1_A_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN1_A_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_Msk = 0x400 + // Bit GEN1_A_NCIFORCE. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE = 0x400 + // Position of GEN1_A_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN1_A_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN1_B_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN1_B_NCIFORCE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_Msk = 0x2000 + // Bit GEN1_B_NCIFORCE. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE = 0x2000 + // Position of GEN1_B_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN1_B_NCIFORCE_MODE field. + MCPWM_GEN1_FORCE_GEN1_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN1_A: Actions triggered by events on PWM1A + // Position of UTEZ field. + MCPWM_GEN1_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN1_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN1_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN1_A_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN1_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN1_A_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN1_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN1_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN1_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN1_A_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN1_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN1_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN1_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN1_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN1_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN1_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN1_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN1_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN1_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN1_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN1_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN1_A_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN1_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN1_A_DT1_Msk = 0xc00000 + + // GEN1_B: Actions triggered by events on PWM1B + // Position of UTEZ field. + MCPWM_GEN1_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN1_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN1_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN1_B_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN1_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN1_B_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN1_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN1_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN1_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN1_B_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN1_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN1_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN1_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN1_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN1_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN1_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN1_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN1_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN1_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN1_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN1_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN1_B_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN1_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN1_B_DT1_Msk = 0xc00000 + + // DT1_CFG: dead time type selection and configuration + // Position of DB1_FED_UPMETHOD field. + MCPWM_DT1_CFG_DB1_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DB1_FED_UPMETHOD field. + MCPWM_DT1_CFG_DB1_FED_UPMETHOD_Msk = 0xf + // Position of DB1_RED_UPMETHOD field. + MCPWM_DT1_CFG_DB1_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DB1_RED_UPMETHOD field. + MCPWM_DT1_CFG_DB1_RED_UPMETHOD_Msk = 0xf0 + // Position of DB1_DEB_MODE field. + MCPWM_DT1_CFG_DB1_DEB_MODE_Pos = 0x8 + // Bit mask of DB1_DEB_MODE field. + MCPWM_DT1_CFG_DB1_DEB_MODE_Msk = 0x100 + // Bit DB1_DEB_MODE. + MCPWM_DT1_CFG_DB1_DEB_MODE = 0x100 + // Position of DB1_A_OUTSWAP field. + MCPWM_DT1_CFG_DB1_A_OUTSWAP_Pos = 0x9 + // Bit mask of DB1_A_OUTSWAP field. + MCPWM_DT1_CFG_DB1_A_OUTSWAP_Msk = 0x200 + // Bit DB1_A_OUTSWAP. + MCPWM_DT1_CFG_DB1_A_OUTSWAP = 0x200 + // Position of DB1_B_OUTSWAP field. + MCPWM_DT1_CFG_DB1_B_OUTSWAP_Pos = 0xa + // Bit mask of DB1_B_OUTSWAP field. + MCPWM_DT1_CFG_DB1_B_OUTSWAP_Msk = 0x400 + // Bit DB1_B_OUTSWAP. + MCPWM_DT1_CFG_DB1_B_OUTSWAP = 0x400 + // Position of DB1_RED_INSEL field. + MCPWM_DT1_CFG_DB1_RED_INSEL_Pos = 0xb + // Bit mask of DB1_RED_INSEL field. + MCPWM_DT1_CFG_DB1_RED_INSEL_Msk = 0x800 + // Bit DB1_RED_INSEL. + MCPWM_DT1_CFG_DB1_RED_INSEL = 0x800 + // Position of DB1_FED_INSEL field. + MCPWM_DT1_CFG_DB1_FED_INSEL_Pos = 0xc + // Bit mask of DB1_FED_INSEL field. + MCPWM_DT1_CFG_DB1_FED_INSEL_Msk = 0x1000 + // Bit DB1_FED_INSEL. + MCPWM_DT1_CFG_DB1_FED_INSEL = 0x1000 + // Position of DB1_RED_OUTINVERT field. + MCPWM_DT1_CFG_DB1_RED_OUTINVERT_Pos = 0xd + // Bit mask of DB1_RED_OUTINVERT field. + MCPWM_DT1_CFG_DB1_RED_OUTINVERT_Msk = 0x2000 + // Bit DB1_RED_OUTINVERT. + MCPWM_DT1_CFG_DB1_RED_OUTINVERT = 0x2000 + // Position of DB1_FED_OUTINVERT field. + MCPWM_DT1_CFG_DB1_FED_OUTINVERT_Pos = 0xe + // Bit mask of DB1_FED_OUTINVERT field. + MCPWM_DT1_CFG_DB1_FED_OUTINVERT_Msk = 0x4000 + // Bit DB1_FED_OUTINVERT. + MCPWM_DT1_CFG_DB1_FED_OUTINVERT = 0x4000 + // Position of DB1_A_OUTBYPASS field. + MCPWM_DT1_CFG_DB1_A_OUTBYPASS_Pos = 0xf + // Bit mask of DB1_A_OUTBYPASS field. + MCPWM_DT1_CFG_DB1_A_OUTBYPASS_Msk = 0x8000 + // Bit DB1_A_OUTBYPASS. + MCPWM_DT1_CFG_DB1_A_OUTBYPASS = 0x8000 + // Position of DB1_B_OUTBYPASS field. + MCPWM_DT1_CFG_DB1_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DB1_B_OUTBYPASS field. + MCPWM_DT1_CFG_DB1_B_OUTBYPASS_Msk = 0x10000 + // Bit DB1_B_OUTBYPASS. + MCPWM_DT1_CFG_DB1_B_OUTBYPASS = 0x10000 + // Position of DB1_CLK_SEL field. + MCPWM_DT1_CFG_DB1_CLK_SEL_Pos = 0x11 + // Bit mask of DB1_CLK_SEL field. + MCPWM_DT1_CFG_DB1_CLK_SEL_Msk = 0x20000 + // Bit DB1_CLK_SEL. + MCPWM_DT1_CFG_DB1_CLK_SEL = 0x20000 + + // DT1_FED_CFG: Shadow register for falling edge delay (FED). + // Position of DB1_FED field. + MCPWM_DT1_FED_CFG_DB1_FED_Pos = 0x0 + // Bit mask of DB1_FED field. + MCPWM_DT1_FED_CFG_DB1_FED_Msk = 0xffff + + // DT1_RED_CFG: Shadow register for rising edge delay (RED). + // Position of DB1_RED field. + MCPWM_DT1_RED_CFG_DB1_RED_Pos = 0x0 + // Bit mask of DB1_RED field. + MCPWM_DT1_RED_CFG_DB1_RED_Msk = 0xffff + + // CARRIER1_CFG: Carrier enable and configuratoin + // Position of CHOPPER1_EN field. + MCPWM_CARRIER1_CFG_CHOPPER1_EN_Pos = 0x0 + // Bit mask of CHOPPER1_EN field. + MCPWM_CARRIER1_CFG_CHOPPER1_EN_Msk = 0x1 + // Bit CHOPPER1_EN. + MCPWM_CARRIER1_CFG_CHOPPER1_EN = 0x1 + // Position of CHOPPER1_PRESCALE field. + MCPWM_CARRIER1_CFG_CHOPPER1_PRESCALE_Pos = 0x1 + // Bit mask of CHOPPER1_PRESCALE field. + MCPWM_CARRIER1_CFG_CHOPPER1_PRESCALE_Msk = 0x1e + // Position of CHOPPER1_DUTY field. + MCPWM_CARRIER1_CFG_CHOPPER1_DUTY_Pos = 0x5 + // Bit mask of CHOPPER1_DUTY field. + MCPWM_CARRIER1_CFG_CHOPPER1_DUTY_Msk = 0xe0 + // Position of CHOPPER1_OSHTWTH field. + MCPWM_CARRIER1_CFG_CHOPPER1_OSHTWTH_Pos = 0x8 + // Bit mask of CHOPPER1_OSHTWTH field. + MCPWM_CARRIER1_CFG_CHOPPER1_OSHTWTH_Msk = 0xf00 + // Position of CHOPPER1_OUT_INVERT field. + MCPWM_CARRIER1_CFG_CHOPPER1_OUT_INVERT_Pos = 0xc + // Bit mask of CHOPPER1_OUT_INVERT field. + MCPWM_CARRIER1_CFG_CHOPPER1_OUT_INVERT_Msk = 0x1000 + // Bit CHOPPER1_OUT_INVERT. + MCPWM_CARRIER1_CFG_CHOPPER1_OUT_INVERT = 0x1000 + // Position of CHOPPER1_IN_INVERT field. + MCPWM_CARRIER1_CFG_CHOPPER1_IN_INVERT_Pos = 0xd + // Bit mask of CHOPPER1_IN_INVERT field. + MCPWM_CARRIER1_CFG_CHOPPER1_IN_INVERT_Msk = 0x2000 + // Bit CHOPPER1_IN_INVERT. + MCPWM_CARRIER1_CFG_CHOPPER1_IN_INVERT = 0x2000 + + // FH1_CFG0: Actions on PWM1A and PWM1B trip events + // Position of TZ1_SW_CBC field. + MCPWM_FH1_CFG0_TZ1_SW_CBC_Pos = 0x0 + // Bit mask of TZ1_SW_CBC field. + MCPWM_FH1_CFG0_TZ1_SW_CBC_Msk = 0x1 + // Bit TZ1_SW_CBC. + MCPWM_FH1_CFG0_TZ1_SW_CBC = 0x1 + // Position of TZ1_F2_CBC field. + MCPWM_FH1_CFG0_TZ1_F2_CBC_Pos = 0x1 + // Bit mask of TZ1_F2_CBC field. + MCPWM_FH1_CFG0_TZ1_F2_CBC_Msk = 0x2 + // Bit TZ1_F2_CBC. + MCPWM_FH1_CFG0_TZ1_F2_CBC = 0x2 + // Position of TZ1_F1_CBC field. + MCPWM_FH1_CFG0_TZ1_F1_CBC_Pos = 0x2 + // Bit mask of TZ1_F1_CBC field. + MCPWM_FH1_CFG0_TZ1_F1_CBC_Msk = 0x4 + // Bit TZ1_F1_CBC. + MCPWM_FH1_CFG0_TZ1_F1_CBC = 0x4 + // Position of TZ1_F0_CBC field. + MCPWM_FH1_CFG0_TZ1_F0_CBC_Pos = 0x3 + // Bit mask of TZ1_F0_CBC field. + MCPWM_FH1_CFG0_TZ1_F0_CBC_Msk = 0x8 + // Bit TZ1_F0_CBC. + MCPWM_FH1_CFG0_TZ1_F0_CBC = 0x8 + // Position of TZ1_SW_OST field. + MCPWM_FH1_CFG0_TZ1_SW_OST_Pos = 0x4 + // Bit mask of TZ1_SW_OST field. + MCPWM_FH1_CFG0_TZ1_SW_OST_Msk = 0x10 + // Bit TZ1_SW_OST. + MCPWM_FH1_CFG0_TZ1_SW_OST = 0x10 + // Position of TZ1_F2_OST field. + MCPWM_FH1_CFG0_TZ1_F2_OST_Pos = 0x5 + // Bit mask of TZ1_F2_OST field. + MCPWM_FH1_CFG0_TZ1_F2_OST_Msk = 0x20 + // Bit TZ1_F2_OST. + MCPWM_FH1_CFG0_TZ1_F2_OST = 0x20 + // Position of TZ1_F1_OST field. + MCPWM_FH1_CFG0_TZ1_F1_OST_Pos = 0x6 + // Bit mask of TZ1_F1_OST field. + MCPWM_FH1_CFG0_TZ1_F1_OST_Msk = 0x40 + // Bit TZ1_F1_OST. + MCPWM_FH1_CFG0_TZ1_F1_OST = 0x40 + // Position of TZ1_F0_OST field. + MCPWM_FH1_CFG0_TZ1_F0_OST_Pos = 0x7 + // Bit mask of TZ1_F0_OST field. + MCPWM_FH1_CFG0_TZ1_F0_OST_Msk = 0x80 + // Bit TZ1_F0_OST. + MCPWM_FH1_CFG0_TZ1_F0_OST = 0x80 + // Position of TZ1_A_CBC_D field. + MCPWM_FH1_CFG0_TZ1_A_CBC_D_Pos = 0x8 + // Bit mask of TZ1_A_CBC_D field. + MCPWM_FH1_CFG0_TZ1_A_CBC_D_Msk = 0x300 + // Position of TZ1_A_CBC_U field. + MCPWM_FH1_CFG0_TZ1_A_CBC_U_Pos = 0xa + // Bit mask of TZ1_A_CBC_U field. + MCPWM_FH1_CFG0_TZ1_A_CBC_U_Msk = 0xc00 + // Position of TZ1_A_OST_D field. + MCPWM_FH1_CFG0_TZ1_A_OST_D_Pos = 0xc + // Bit mask of TZ1_A_OST_D field. + MCPWM_FH1_CFG0_TZ1_A_OST_D_Msk = 0x3000 + // Position of TZ1_A_OST_U field. + MCPWM_FH1_CFG0_TZ1_A_OST_U_Pos = 0xe + // Bit mask of TZ1_A_OST_U field. + MCPWM_FH1_CFG0_TZ1_A_OST_U_Msk = 0xc000 + // Position of TZ1_B_CBC_D field. + MCPWM_FH1_CFG0_TZ1_B_CBC_D_Pos = 0x10 + // Bit mask of TZ1_B_CBC_D field. + MCPWM_FH1_CFG0_TZ1_B_CBC_D_Msk = 0x30000 + // Position of TZ1_B_CBC_U field. + MCPWM_FH1_CFG0_TZ1_B_CBC_U_Pos = 0x12 + // Bit mask of TZ1_B_CBC_U field. + MCPWM_FH1_CFG0_TZ1_B_CBC_U_Msk = 0xc0000 + // Position of TZ1_B_OST_D field. + MCPWM_FH1_CFG0_TZ1_B_OST_D_Pos = 0x14 + // Bit mask of TZ1_B_OST_D field. + MCPWM_FH1_CFG0_TZ1_B_OST_D_Msk = 0x300000 + // Position of TZ1_B_OST_U field. + MCPWM_FH1_CFG0_TZ1_B_OST_U_Pos = 0x16 + // Bit mask of TZ1_B_OST_U field. + MCPWM_FH1_CFG0_TZ1_B_OST_U_Msk = 0xc00000 + + // FH1_CFG1: Software triggers for fault handler actions + // Position of TZ1_CLR_OST field. + MCPWM_FH1_CFG1_TZ1_CLR_OST_Pos = 0x0 + // Bit mask of TZ1_CLR_OST field. + MCPWM_FH1_CFG1_TZ1_CLR_OST_Msk = 0x1 + // Bit TZ1_CLR_OST. + MCPWM_FH1_CFG1_TZ1_CLR_OST = 0x1 + // Position of TZ1_CBCPULSE field. + MCPWM_FH1_CFG1_TZ1_CBCPULSE_Pos = 0x1 + // Bit mask of TZ1_CBCPULSE field. + MCPWM_FH1_CFG1_TZ1_CBCPULSE_Msk = 0x6 + // Position of TZ1_FORCE_CBC field. + MCPWM_FH1_CFG1_TZ1_FORCE_CBC_Pos = 0x3 + // Bit mask of TZ1_FORCE_CBC field. + MCPWM_FH1_CFG1_TZ1_FORCE_CBC_Msk = 0x8 + // Bit TZ1_FORCE_CBC. + MCPWM_FH1_CFG1_TZ1_FORCE_CBC = 0x8 + // Position of TZ1_FORCE_OST field. + MCPWM_FH1_CFG1_TZ1_FORCE_OST_Pos = 0x4 + // Bit mask of TZ1_FORCE_OST field. + MCPWM_FH1_CFG1_TZ1_FORCE_OST_Msk = 0x10 + // Bit TZ1_FORCE_OST. + MCPWM_FH1_CFG1_TZ1_FORCE_OST = 0x10 + + // FH1_STATUS: Status of fault events. + // Position of TZ1_CBC_ON field. + MCPWM_FH1_STATUS_TZ1_CBC_ON_Pos = 0x0 + // Bit mask of TZ1_CBC_ON field. + MCPWM_FH1_STATUS_TZ1_CBC_ON_Msk = 0x1 + // Bit TZ1_CBC_ON. + MCPWM_FH1_STATUS_TZ1_CBC_ON = 0x1 + // Position of TZ1_OST_ON field. + MCPWM_FH1_STATUS_TZ1_OST_ON_Pos = 0x1 + // Bit mask of TZ1_OST_ON field. + MCPWM_FH1_STATUS_TZ1_OST_ON_Msk = 0x2 + // Bit TZ1_OST_ON. + MCPWM_FH1_STATUS_TZ1_OST_ON = 0x2 + + // GEN2_STMP_CFG: Transfer status and update method for time stamp registers A and B + // Position of CMPR2_A_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_CMPR2_A_UPMETHOD_Pos = 0x0 + // Bit mask of CMPR2_A_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_CMPR2_A_UPMETHOD_Msk = 0xf + // Position of CMPR2_B_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_CMPR2_B_UPMETHOD_Pos = 0x4 + // Bit mask of CMPR2_B_UPMETHOD field. + MCPWM_GEN2_STMP_CFG_CMPR2_B_UPMETHOD_Msk = 0xf0 + // Position of CMPR2_A_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_CMPR2_A_SHDW_FULL_Pos = 0x8 + // Bit mask of CMPR2_A_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_CMPR2_A_SHDW_FULL_Msk = 0x100 + // Bit CMPR2_A_SHDW_FULL. + MCPWM_GEN2_STMP_CFG_CMPR2_A_SHDW_FULL = 0x100 + // Position of CMPR2_B_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_CMPR2_B_SHDW_FULL_Pos = 0x9 + // Bit mask of CMPR2_B_SHDW_FULL field. + MCPWM_GEN2_STMP_CFG_CMPR2_B_SHDW_FULL_Msk = 0x200 + // Bit CMPR2_B_SHDW_FULL. + MCPWM_GEN2_STMP_CFG_CMPR2_B_SHDW_FULL = 0x200 + + // GEN2_TSTMP_A: Shadow register for register A. + // Position of CMPR2_A field. + MCPWM_GEN2_TSTMP_A_CMPR2_A_Pos = 0x0 + // Bit mask of CMPR2_A field. + MCPWM_GEN2_TSTMP_A_CMPR2_A_Msk = 0xffff + + // GEN2_TSTMP_B: Shadow register for register B. + // Position of CMPR2_B field. + MCPWM_GEN2_TSTMP_B_CMPR2_B_Pos = 0x0 + // Bit mask of CMPR2_B field. + MCPWM_GEN2_TSTMP_B_CMPR2_B_Msk = 0xffff + + // GEN2_CFG0: Fault event T0 and T1 handling + // Position of GEN2_CFG_UPMETHOD field. + MCPWM_GEN2_CFG0_GEN2_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN2_CFG_UPMETHOD field. + MCPWM_GEN2_CFG0_GEN2_CFG_UPMETHOD_Msk = 0xf + // Position of GEN2_T0_SEL field. + MCPWM_GEN2_CFG0_GEN2_T0_SEL_Pos = 0x4 + // Bit mask of GEN2_T0_SEL field. + MCPWM_GEN2_CFG0_GEN2_T0_SEL_Msk = 0x70 + // Position of GEN2_T1_SEL field. + MCPWM_GEN2_CFG0_GEN2_T1_SEL_Pos = 0x7 + // Bit mask of GEN2_T1_SEL field. + MCPWM_GEN2_CFG0_GEN2_T1_SEL_Msk = 0x380 + + // GEN2_FORCE: Permissives to force PWM2A and PWM2B outputs by software + // Position of GEN2_CNTUFORCE_UPMETHOD field. + MCPWM_GEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN2_CNTUFORCE_UPMETHOD field. + MCPWM_GEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN2_A_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN2_A_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN2_B_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN2_B_CNTUFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN2_A_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN2_A_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_Msk = 0x400 + // Bit GEN2_A_NCIFORCE. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE = 0x400 + // Position of GEN2_A_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN2_A_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN2_B_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN2_B_NCIFORCE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_Msk = 0x2000 + // Bit GEN2_B_NCIFORCE. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE = 0x2000 + // Position of GEN2_B_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN2_B_NCIFORCE_MODE field. + MCPWM_GEN2_FORCE_GEN2_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN2_A: Actions triggered by events on PWM2A + // Position of UTEZ field. + MCPWM_GEN2_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN2_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN2_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN2_A_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN2_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN2_A_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN2_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN2_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN2_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN2_A_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN2_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN2_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN2_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN2_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN2_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN2_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN2_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN2_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN2_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN2_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN2_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN2_A_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN2_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN2_A_DT1_Msk = 0xc00000 + + // GEN2_B: Actions triggered by events on PWM2B + // Position of UTEZ field. + MCPWM_GEN2_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + MCPWM_GEN2_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + MCPWM_GEN2_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + MCPWM_GEN2_B_UTEP_Msk = 0xc + // Position of UTEA field. + MCPWM_GEN2_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + MCPWM_GEN2_B_UTEA_Msk = 0x30 + // Position of UTEB field. + MCPWM_GEN2_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + MCPWM_GEN2_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + MCPWM_GEN2_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + MCPWM_GEN2_B_UT0_Msk = 0x300 + // Position of UT1 field. + MCPWM_GEN2_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + MCPWM_GEN2_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + MCPWM_GEN2_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + MCPWM_GEN2_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + MCPWM_GEN2_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + MCPWM_GEN2_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + MCPWM_GEN2_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + MCPWM_GEN2_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + MCPWM_GEN2_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + MCPWM_GEN2_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + MCPWM_GEN2_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + MCPWM_GEN2_B_DT0_Msk = 0x300000 + // Position of DT1 field. + MCPWM_GEN2_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + MCPWM_GEN2_B_DT1_Msk = 0xc00000 + + // DT2_CFG: dead time type selection and configuration + // Position of DB2_FED_UPMETHOD field. + MCPWM_DT2_CFG_DB2_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DB2_FED_UPMETHOD field. + MCPWM_DT2_CFG_DB2_FED_UPMETHOD_Msk = 0xf + // Position of DB2_RED_UPMETHOD field. + MCPWM_DT2_CFG_DB2_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DB2_RED_UPMETHOD field. + MCPWM_DT2_CFG_DB2_RED_UPMETHOD_Msk = 0xf0 + // Position of DB2_DEB_MODE field. + MCPWM_DT2_CFG_DB2_DEB_MODE_Pos = 0x8 + // Bit mask of DB2_DEB_MODE field. + MCPWM_DT2_CFG_DB2_DEB_MODE_Msk = 0x100 + // Bit DB2_DEB_MODE. + MCPWM_DT2_CFG_DB2_DEB_MODE = 0x100 + // Position of DB2_A_OUTSWAP field. + MCPWM_DT2_CFG_DB2_A_OUTSWAP_Pos = 0x9 + // Bit mask of DB2_A_OUTSWAP field. + MCPWM_DT2_CFG_DB2_A_OUTSWAP_Msk = 0x200 + // Bit DB2_A_OUTSWAP. + MCPWM_DT2_CFG_DB2_A_OUTSWAP = 0x200 + // Position of DB2_B_OUTSWAP field. + MCPWM_DT2_CFG_DB2_B_OUTSWAP_Pos = 0xa + // Bit mask of DB2_B_OUTSWAP field. + MCPWM_DT2_CFG_DB2_B_OUTSWAP_Msk = 0x400 + // Bit DB2_B_OUTSWAP. + MCPWM_DT2_CFG_DB2_B_OUTSWAP = 0x400 + // Position of DB2_RED_INSEL field. + MCPWM_DT2_CFG_DB2_RED_INSEL_Pos = 0xb + // Bit mask of DB2_RED_INSEL field. + MCPWM_DT2_CFG_DB2_RED_INSEL_Msk = 0x800 + // Bit DB2_RED_INSEL. + MCPWM_DT2_CFG_DB2_RED_INSEL = 0x800 + // Position of DB2_FED_INSEL field. + MCPWM_DT2_CFG_DB2_FED_INSEL_Pos = 0xc + // Bit mask of DB2_FED_INSEL field. + MCPWM_DT2_CFG_DB2_FED_INSEL_Msk = 0x1000 + // Bit DB2_FED_INSEL. + MCPWM_DT2_CFG_DB2_FED_INSEL = 0x1000 + // Position of DB2_RED_OUTINVERT field. + MCPWM_DT2_CFG_DB2_RED_OUTINVERT_Pos = 0xd + // Bit mask of DB2_RED_OUTINVERT field. + MCPWM_DT2_CFG_DB2_RED_OUTINVERT_Msk = 0x2000 + // Bit DB2_RED_OUTINVERT. + MCPWM_DT2_CFG_DB2_RED_OUTINVERT = 0x2000 + // Position of DB2_FED_OUTINVERT field. + MCPWM_DT2_CFG_DB2_FED_OUTINVERT_Pos = 0xe + // Bit mask of DB2_FED_OUTINVERT field. + MCPWM_DT2_CFG_DB2_FED_OUTINVERT_Msk = 0x4000 + // Bit DB2_FED_OUTINVERT. + MCPWM_DT2_CFG_DB2_FED_OUTINVERT = 0x4000 + // Position of DB2_A_OUTBYPASS field. + MCPWM_DT2_CFG_DB2_A_OUTBYPASS_Pos = 0xf + // Bit mask of DB2_A_OUTBYPASS field. + MCPWM_DT2_CFG_DB2_A_OUTBYPASS_Msk = 0x8000 + // Bit DB2_A_OUTBYPASS. + MCPWM_DT2_CFG_DB2_A_OUTBYPASS = 0x8000 + // Position of DB2_B_OUTBYPASS field. + MCPWM_DT2_CFG_DB2_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DB2_B_OUTBYPASS field. + MCPWM_DT2_CFG_DB2_B_OUTBYPASS_Msk = 0x10000 + // Bit DB2_B_OUTBYPASS. + MCPWM_DT2_CFG_DB2_B_OUTBYPASS = 0x10000 + // Position of DB2_CLK_SEL field. + MCPWM_DT2_CFG_DB2_CLK_SEL_Pos = 0x11 + // Bit mask of DB2_CLK_SEL field. + MCPWM_DT2_CFG_DB2_CLK_SEL_Msk = 0x20000 + // Bit DB2_CLK_SEL. + MCPWM_DT2_CFG_DB2_CLK_SEL = 0x20000 + + // DT2_FED_CFG: Shadow register for falling edge delay (FED). + // Position of DB2_FED field. + MCPWM_DT2_FED_CFG_DB2_FED_Pos = 0x0 + // Bit mask of DB2_FED field. + MCPWM_DT2_FED_CFG_DB2_FED_Msk = 0xffff + + // DT2_RED_CFG: Shadow register for rising edge delay (RED). + // Position of DB2_RED field. + MCPWM_DT2_RED_CFG_DB2_RED_Pos = 0x0 + // Bit mask of DB2_RED field. + MCPWM_DT2_RED_CFG_DB2_RED_Msk = 0xffff + + // CARRIER2_CFG: Carrier enable and configuratoin + // Position of CHOPPER2_EN field. + MCPWM_CARRIER2_CFG_CHOPPER2_EN_Pos = 0x0 + // Bit mask of CHOPPER2_EN field. + MCPWM_CARRIER2_CFG_CHOPPER2_EN_Msk = 0x1 + // Bit CHOPPER2_EN. + MCPWM_CARRIER2_CFG_CHOPPER2_EN = 0x1 + // Position of CHOPPER2_PRESCALE field. + MCPWM_CARRIER2_CFG_CHOPPER2_PRESCALE_Pos = 0x1 + // Bit mask of CHOPPER2_PRESCALE field. + MCPWM_CARRIER2_CFG_CHOPPER2_PRESCALE_Msk = 0x1e + // Position of CHOPPER2_DUTY field. + MCPWM_CARRIER2_CFG_CHOPPER2_DUTY_Pos = 0x5 + // Bit mask of CHOPPER2_DUTY field. + MCPWM_CARRIER2_CFG_CHOPPER2_DUTY_Msk = 0xe0 + // Position of CHOPPER2_OSHTWTH field. + MCPWM_CARRIER2_CFG_CHOPPER2_OSHTWTH_Pos = 0x8 + // Bit mask of CHOPPER2_OSHTWTH field. + MCPWM_CARRIER2_CFG_CHOPPER2_OSHTWTH_Msk = 0xf00 + // Position of CHOPPER2_OUT_INVERT field. + MCPWM_CARRIER2_CFG_CHOPPER2_OUT_INVERT_Pos = 0xc + // Bit mask of CHOPPER2_OUT_INVERT field. + MCPWM_CARRIER2_CFG_CHOPPER2_OUT_INVERT_Msk = 0x1000 + // Bit CHOPPER2_OUT_INVERT. + MCPWM_CARRIER2_CFG_CHOPPER2_OUT_INVERT = 0x1000 + // Position of CHOPPER2_IN_INVERT field. + MCPWM_CARRIER2_CFG_CHOPPER2_IN_INVERT_Pos = 0xd + // Bit mask of CHOPPER2_IN_INVERT field. + MCPWM_CARRIER2_CFG_CHOPPER2_IN_INVERT_Msk = 0x2000 + // Bit CHOPPER2_IN_INVERT. + MCPWM_CARRIER2_CFG_CHOPPER2_IN_INVERT = 0x2000 + + // FH2_CFG0: Actions on PWM2A and PWM2B trip events + // Position of TZ2_SW_CBC field. + MCPWM_FH2_CFG0_TZ2_SW_CBC_Pos = 0x0 + // Bit mask of TZ2_SW_CBC field. + MCPWM_FH2_CFG0_TZ2_SW_CBC_Msk = 0x1 + // Bit TZ2_SW_CBC. + MCPWM_FH2_CFG0_TZ2_SW_CBC = 0x1 + // Position of TZ2_F2_CBC field. + MCPWM_FH2_CFG0_TZ2_F2_CBC_Pos = 0x1 + // Bit mask of TZ2_F2_CBC field. + MCPWM_FH2_CFG0_TZ2_F2_CBC_Msk = 0x2 + // Bit TZ2_F2_CBC. + MCPWM_FH2_CFG0_TZ2_F2_CBC = 0x2 + // Position of TZ2_F1_CBC field. + MCPWM_FH2_CFG0_TZ2_F1_CBC_Pos = 0x2 + // Bit mask of TZ2_F1_CBC field. + MCPWM_FH2_CFG0_TZ2_F1_CBC_Msk = 0x4 + // Bit TZ2_F1_CBC. + MCPWM_FH2_CFG0_TZ2_F1_CBC = 0x4 + // Position of TZ2_F0_CBC field. + MCPWM_FH2_CFG0_TZ2_F0_CBC_Pos = 0x3 + // Bit mask of TZ2_F0_CBC field. + MCPWM_FH2_CFG0_TZ2_F0_CBC_Msk = 0x8 + // Bit TZ2_F0_CBC. + MCPWM_FH2_CFG0_TZ2_F0_CBC = 0x8 + // Position of TZ2_SW_OST field. + MCPWM_FH2_CFG0_TZ2_SW_OST_Pos = 0x4 + // Bit mask of TZ2_SW_OST field. + MCPWM_FH2_CFG0_TZ2_SW_OST_Msk = 0x10 + // Bit TZ2_SW_OST. + MCPWM_FH2_CFG0_TZ2_SW_OST = 0x10 + // Position of TZ2_F2_OST field. + MCPWM_FH2_CFG0_TZ2_F2_OST_Pos = 0x5 + // Bit mask of TZ2_F2_OST field. + MCPWM_FH2_CFG0_TZ2_F2_OST_Msk = 0x20 + // Bit TZ2_F2_OST. + MCPWM_FH2_CFG0_TZ2_F2_OST = 0x20 + // Position of TZ2_F1_OST field. + MCPWM_FH2_CFG0_TZ2_F1_OST_Pos = 0x6 + // Bit mask of TZ2_F1_OST field. + MCPWM_FH2_CFG0_TZ2_F1_OST_Msk = 0x40 + // Bit TZ2_F1_OST. + MCPWM_FH2_CFG0_TZ2_F1_OST = 0x40 + // Position of TZ2_F0_OST field. + MCPWM_FH2_CFG0_TZ2_F0_OST_Pos = 0x7 + // Bit mask of TZ2_F0_OST field. + MCPWM_FH2_CFG0_TZ2_F0_OST_Msk = 0x80 + // Bit TZ2_F0_OST. + MCPWM_FH2_CFG0_TZ2_F0_OST = 0x80 + // Position of TZ2_A_CBC_D field. + MCPWM_FH2_CFG0_TZ2_A_CBC_D_Pos = 0x8 + // Bit mask of TZ2_A_CBC_D field. + MCPWM_FH2_CFG0_TZ2_A_CBC_D_Msk = 0x300 + // Position of TZ2_A_CBC_U field. + MCPWM_FH2_CFG0_TZ2_A_CBC_U_Pos = 0xa + // Bit mask of TZ2_A_CBC_U field. + MCPWM_FH2_CFG0_TZ2_A_CBC_U_Msk = 0xc00 + // Position of TZ2_A_OST_D field. + MCPWM_FH2_CFG0_TZ2_A_OST_D_Pos = 0xc + // Bit mask of TZ2_A_OST_D field. + MCPWM_FH2_CFG0_TZ2_A_OST_D_Msk = 0x3000 + // Position of TZ2_A_OST_U field. + MCPWM_FH2_CFG0_TZ2_A_OST_U_Pos = 0xe + // Bit mask of TZ2_A_OST_U field. + MCPWM_FH2_CFG0_TZ2_A_OST_U_Msk = 0xc000 + // Position of TZ2_B_CBC_D field. + MCPWM_FH2_CFG0_TZ2_B_CBC_D_Pos = 0x10 + // Bit mask of TZ2_B_CBC_D field. + MCPWM_FH2_CFG0_TZ2_B_CBC_D_Msk = 0x30000 + // Position of TZ2_B_CBC_U field. + MCPWM_FH2_CFG0_TZ2_B_CBC_U_Pos = 0x12 + // Bit mask of TZ2_B_CBC_U field. + MCPWM_FH2_CFG0_TZ2_B_CBC_U_Msk = 0xc0000 + // Position of TZ2_B_OST_D field. + MCPWM_FH2_CFG0_TZ2_B_OST_D_Pos = 0x14 + // Bit mask of TZ2_B_OST_D field. + MCPWM_FH2_CFG0_TZ2_B_OST_D_Msk = 0x300000 + // Position of TZ2_B_OST_U field. + MCPWM_FH2_CFG0_TZ2_B_OST_U_Pos = 0x16 + // Bit mask of TZ2_B_OST_U field. + MCPWM_FH2_CFG0_TZ2_B_OST_U_Msk = 0xc00000 + + // FH2_CFG1: Software triggers for fault handler actions + // Position of TZ2_CLR_OST field. + MCPWM_FH2_CFG1_TZ2_CLR_OST_Pos = 0x0 + // Bit mask of TZ2_CLR_OST field. + MCPWM_FH2_CFG1_TZ2_CLR_OST_Msk = 0x1 + // Bit TZ2_CLR_OST. + MCPWM_FH2_CFG1_TZ2_CLR_OST = 0x1 + // Position of TZ2_CBCPULSE field. + MCPWM_FH2_CFG1_TZ2_CBCPULSE_Pos = 0x1 + // Bit mask of TZ2_CBCPULSE field. + MCPWM_FH2_CFG1_TZ2_CBCPULSE_Msk = 0x6 + // Position of TZ2_FORCE_CBC field. + MCPWM_FH2_CFG1_TZ2_FORCE_CBC_Pos = 0x3 + // Bit mask of TZ2_FORCE_CBC field. + MCPWM_FH2_CFG1_TZ2_FORCE_CBC_Msk = 0x8 + // Bit TZ2_FORCE_CBC. + MCPWM_FH2_CFG1_TZ2_FORCE_CBC = 0x8 + // Position of TZ2_FORCE_OST field. + MCPWM_FH2_CFG1_TZ2_FORCE_OST_Pos = 0x4 + // Bit mask of TZ2_FORCE_OST field. + MCPWM_FH2_CFG1_TZ2_FORCE_OST_Msk = 0x10 + // Bit TZ2_FORCE_OST. + MCPWM_FH2_CFG1_TZ2_FORCE_OST = 0x10 + + // FH2_STATUS: Status of fault events. + // Position of TZ2_CBC_ON field. + MCPWM_FH2_STATUS_TZ2_CBC_ON_Pos = 0x0 + // Bit mask of TZ2_CBC_ON field. + MCPWM_FH2_STATUS_TZ2_CBC_ON_Msk = 0x1 + // Bit TZ2_CBC_ON. + MCPWM_FH2_STATUS_TZ2_CBC_ON = 0x1 + // Position of TZ2_OST_ON field. + MCPWM_FH2_STATUS_TZ2_OST_ON_Pos = 0x1 + // Bit mask of TZ2_OST_ON field. + MCPWM_FH2_STATUS_TZ2_OST_ON_Msk = 0x2 + // Bit TZ2_OST_ON. + MCPWM_FH2_STATUS_TZ2_OST_ON = 0x2 + + // FAULT_DETECT: Fault detection configuration and status + // Position of F0_EN field. + MCPWM_FAULT_DETECT_F0_EN_Pos = 0x0 + // Bit mask of F0_EN field. + MCPWM_FAULT_DETECT_F0_EN_Msk = 0x1 + // Bit F0_EN. + MCPWM_FAULT_DETECT_F0_EN = 0x1 + // Position of F1_EN field. + MCPWM_FAULT_DETECT_F1_EN_Pos = 0x1 + // Bit mask of F1_EN field. + MCPWM_FAULT_DETECT_F1_EN_Msk = 0x2 + // Bit F1_EN. + MCPWM_FAULT_DETECT_F1_EN = 0x2 + // Position of F2_EN field. + MCPWM_FAULT_DETECT_F2_EN_Pos = 0x2 + // Bit mask of F2_EN field. + MCPWM_FAULT_DETECT_F2_EN_Msk = 0x4 + // Bit F2_EN. + MCPWM_FAULT_DETECT_F2_EN = 0x4 + // Position of F0_POLE field. + MCPWM_FAULT_DETECT_F0_POLE_Pos = 0x3 + // Bit mask of F0_POLE field. + MCPWM_FAULT_DETECT_F0_POLE_Msk = 0x8 + // Bit F0_POLE. + MCPWM_FAULT_DETECT_F0_POLE = 0x8 + // Position of F1_POLE field. + MCPWM_FAULT_DETECT_F1_POLE_Pos = 0x4 + // Bit mask of F1_POLE field. + MCPWM_FAULT_DETECT_F1_POLE_Msk = 0x10 + // Bit F1_POLE. + MCPWM_FAULT_DETECT_F1_POLE = 0x10 + // Position of F2_POLE field. + MCPWM_FAULT_DETECT_F2_POLE_Pos = 0x5 + // Bit mask of F2_POLE field. + MCPWM_FAULT_DETECT_F2_POLE_Msk = 0x20 + // Bit F2_POLE. + MCPWM_FAULT_DETECT_F2_POLE = 0x20 + // Position of EVENT_F0 field. + MCPWM_FAULT_DETECT_EVENT_F0_Pos = 0x6 + // Bit mask of EVENT_F0 field. + MCPWM_FAULT_DETECT_EVENT_F0_Msk = 0x40 + // Bit EVENT_F0. + MCPWM_FAULT_DETECT_EVENT_F0 = 0x40 + // Position of EVENT_F1 field. + MCPWM_FAULT_DETECT_EVENT_F1_Pos = 0x7 + // Bit mask of EVENT_F1 field. + MCPWM_FAULT_DETECT_EVENT_F1_Msk = 0x80 + // Bit EVENT_F1. + MCPWM_FAULT_DETECT_EVENT_F1 = 0x80 + // Position of EVENT_F2 field. + MCPWM_FAULT_DETECT_EVENT_F2_Pos = 0x8 + // Bit mask of EVENT_F2 field. + MCPWM_FAULT_DETECT_EVENT_F2_Msk = 0x100 + // Bit EVENT_F2. + MCPWM_FAULT_DETECT_EVENT_F2 = 0x100 + + // CAP_TIMER_CFG: Configure capture timer + // Position of CAP_TIMER_EN field. + MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN_Pos = 0x0 + // Bit mask of CAP_TIMER_EN field. + MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN_Msk = 0x1 + // Bit CAP_TIMER_EN. + MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN = 0x1 + // Position of CAP_SYNCI_EN field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Pos = 0x1 + // Bit mask of CAP_SYNCI_EN field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Msk = 0x2 + // Bit CAP_SYNCI_EN. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN = 0x2 + // Position of CAP_SYNCI_SEL field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Pos = 0x2 + // Bit mask of CAP_SYNCI_SEL field. + MCPWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Msk = 0x1c + // Position of CAP_SYNC_SW field. + MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW_Pos = 0x5 + // Bit mask of CAP_SYNC_SW field. + MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW_Msk = 0x20 + // Bit CAP_SYNC_SW. + MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW = 0x20 + + // CAP_TIMER_PHASE: Phase for capture timer sync + // Position of CAP_PHASE field. + MCPWM_CAP_TIMER_PHASE_CAP_PHASE_Pos = 0x0 + // Bit mask of CAP_PHASE field. + MCPWM_CAP_TIMER_PHASE_CAP_PHASE_Msk = 0xffffffff + + // CAP_CH0_CFG: Capture channel 0 configuration and enable + // Position of CAP0_EN field. + MCPWM_CAP_CH0_CFG_CAP0_EN_Pos = 0x0 + // Bit mask of CAP0_EN field. + MCPWM_CAP_CH0_CFG_CAP0_EN_Msk = 0x1 + // Bit CAP0_EN. + MCPWM_CAP_CH0_CFG_CAP0_EN = 0x1 + // Position of CAP0_MODE field. + MCPWM_CAP_CH0_CFG_CAP0_MODE_Pos = 0x1 + // Bit mask of CAP0_MODE field. + MCPWM_CAP_CH0_CFG_CAP0_MODE_Msk = 0x6 + // Position of CAP0_PRESCALE field. + MCPWM_CAP_CH0_CFG_CAP0_PRESCALE_Pos = 0x3 + // Bit mask of CAP0_PRESCALE field. + MCPWM_CAP_CH0_CFG_CAP0_PRESCALE_Msk = 0x7f8 + // Position of CAP0_IN_INVERT field. + MCPWM_CAP_CH0_CFG_CAP0_IN_INVERT_Pos = 0xb + // Bit mask of CAP0_IN_INVERT field. + MCPWM_CAP_CH0_CFG_CAP0_IN_INVERT_Msk = 0x800 + // Bit CAP0_IN_INVERT. + MCPWM_CAP_CH0_CFG_CAP0_IN_INVERT = 0x800 + // Position of CAP0_SW field. + MCPWM_CAP_CH0_CFG_CAP0_SW_Pos = 0xc + // Bit mask of CAP0_SW field. + MCPWM_CAP_CH0_CFG_CAP0_SW_Msk = 0x1000 + // Bit CAP0_SW. + MCPWM_CAP_CH0_CFG_CAP0_SW = 0x1000 + + // CAP_CH1_CFG: Capture channel 1 configuration and enable + // Position of CAP1_EN field. + MCPWM_CAP_CH1_CFG_CAP1_EN_Pos = 0x0 + // Bit mask of CAP1_EN field. + MCPWM_CAP_CH1_CFG_CAP1_EN_Msk = 0x1 + // Bit CAP1_EN. + MCPWM_CAP_CH1_CFG_CAP1_EN = 0x1 + // Position of CAP1_MODE field. + MCPWM_CAP_CH1_CFG_CAP1_MODE_Pos = 0x1 + // Bit mask of CAP1_MODE field. + MCPWM_CAP_CH1_CFG_CAP1_MODE_Msk = 0x6 + // Position of CAP1_PRESCALE field. + MCPWM_CAP_CH1_CFG_CAP1_PRESCALE_Pos = 0x3 + // Bit mask of CAP1_PRESCALE field. + MCPWM_CAP_CH1_CFG_CAP1_PRESCALE_Msk = 0x7f8 + // Position of CAP1_IN_INVERT field. + MCPWM_CAP_CH1_CFG_CAP1_IN_INVERT_Pos = 0xb + // Bit mask of CAP1_IN_INVERT field. + MCPWM_CAP_CH1_CFG_CAP1_IN_INVERT_Msk = 0x800 + // Bit CAP1_IN_INVERT. + MCPWM_CAP_CH1_CFG_CAP1_IN_INVERT = 0x800 + // Position of CAP1_SW field. + MCPWM_CAP_CH1_CFG_CAP1_SW_Pos = 0xc + // Bit mask of CAP1_SW field. + MCPWM_CAP_CH1_CFG_CAP1_SW_Msk = 0x1000 + // Bit CAP1_SW. + MCPWM_CAP_CH1_CFG_CAP1_SW = 0x1000 + + // CAP_CH2_CFG: Capture channel 2 configuration and enable + // Position of CAP2_EN field. + MCPWM_CAP_CH2_CFG_CAP2_EN_Pos = 0x0 + // Bit mask of CAP2_EN field. + MCPWM_CAP_CH2_CFG_CAP2_EN_Msk = 0x1 + // Bit CAP2_EN. + MCPWM_CAP_CH2_CFG_CAP2_EN = 0x1 + // Position of CAP2_MODE field. + MCPWM_CAP_CH2_CFG_CAP2_MODE_Pos = 0x1 + // Bit mask of CAP2_MODE field. + MCPWM_CAP_CH2_CFG_CAP2_MODE_Msk = 0x6 + // Position of CAP2_PRESCALE field. + MCPWM_CAP_CH2_CFG_CAP2_PRESCALE_Pos = 0x3 + // Bit mask of CAP2_PRESCALE field. + MCPWM_CAP_CH2_CFG_CAP2_PRESCALE_Msk = 0x7f8 + // Position of CAP2_IN_INVERT field. + MCPWM_CAP_CH2_CFG_CAP2_IN_INVERT_Pos = 0xb + // Bit mask of CAP2_IN_INVERT field. + MCPWM_CAP_CH2_CFG_CAP2_IN_INVERT_Msk = 0x800 + // Bit CAP2_IN_INVERT. + MCPWM_CAP_CH2_CFG_CAP2_IN_INVERT = 0x800 + // Position of CAP2_SW field. + MCPWM_CAP_CH2_CFG_CAP2_SW_Pos = 0xc + // Bit mask of CAP2_SW field. + MCPWM_CAP_CH2_CFG_CAP2_SW_Msk = 0x1000 + // Bit CAP2_SW. + MCPWM_CAP_CH2_CFG_CAP2_SW = 0x1000 + + // CAP_CH0: ch0 capture value status register + // Position of CAP0_VALUE field. + MCPWM_CAP_CH0_CAP0_VALUE_Pos = 0x0 + // Bit mask of CAP0_VALUE field. + MCPWM_CAP_CH0_CAP0_VALUE_Msk = 0xffffffff + + // CAP_CH1: ch1 capture value status register + // Position of CAP1_VALUE field. + MCPWM_CAP_CH1_CAP1_VALUE_Pos = 0x0 + // Bit mask of CAP1_VALUE field. + MCPWM_CAP_CH1_CAP1_VALUE_Msk = 0xffffffff + + // CAP_CH2: ch2 capture value status register + // Position of CAP2_VALUE field. + MCPWM_CAP_CH2_CAP2_VALUE_Pos = 0x0 + // Bit mask of CAP2_VALUE field. + MCPWM_CAP_CH2_CAP2_VALUE_Msk = 0xffffffff + + // CAP_STATUS: Edge of last capture trigger + // Position of CAP0_EDGE field. + MCPWM_CAP_STATUS_CAP0_EDGE_Pos = 0x0 + // Bit mask of CAP0_EDGE field. + MCPWM_CAP_STATUS_CAP0_EDGE_Msk = 0x1 + // Bit CAP0_EDGE. + MCPWM_CAP_STATUS_CAP0_EDGE = 0x1 + // Position of CAP1_EDGE field. + MCPWM_CAP_STATUS_CAP1_EDGE_Pos = 0x1 + // Bit mask of CAP1_EDGE field. + MCPWM_CAP_STATUS_CAP1_EDGE_Msk = 0x2 + // Bit CAP1_EDGE. + MCPWM_CAP_STATUS_CAP1_EDGE = 0x2 + // Position of CAP2_EDGE field. + MCPWM_CAP_STATUS_CAP2_EDGE_Pos = 0x2 + // Bit mask of CAP2_EDGE field. + MCPWM_CAP_STATUS_CAP2_EDGE_Msk = 0x4 + // Bit CAP2_EDGE. + MCPWM_CAP_STATUS_CAP2_EDGE = 0x4 + + // UPDATE_CFG: Enable update. + // Position of GLOBAL_UP_EN field. + MCPWM_UPDATE_CFG_GLOBAL_UP_EN_Pos = 0x0 + // Bit mask of GLOBAL_UP_EN field. + MCPWM_UPDATE_CFG_GLOBAL_UP_EN_Msk = 0x1 + // Bit GLOBAL_UP_EN. + MCPWM_UPDATE_CFG_GLOBAL_UP_EN = 0x1 + // Position of GLOBAL_FORCE_UP field. + MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP_Pos = 0x1 + // Bit mask of GLOBAL_FORCE_UP field. + MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP_Msk = 0x2 + // Bit GLOBAL_FORCE_UP. + MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP = 0x2 + // Position of OP0_UP_EN field. + MCPWM_UPDATE_CFG_OP0_UP_EN_Pos = 0x2 + // Bit mask of OP0_UP_EN field. + MCPWM_UPDATE_CFG_OP0_UP_EN_Msk = 0x4 + // Bit OP0_UP_EN. + MCPWM_UPDATE_CFG_OP0_UP_EN = 0x4 + // Position of OP0_FORCE_UP field. + MCPWM_UPDATE_CFG_OP0_FORCE_UP_Pos = 0x3 + // Bit mask of OP0_FORCE_UP field. + MCPWM_UPDATE_CFG_OP0_FORCE_UP_Msk = 0x8 + // Bit OP0_FORCE_UP. + MCPWM_UPDATE_CFG_OP0_FORCE_UP = 0x8 + // Position of OP1_UP_EN field. + MCPWM_UPDATE_CFG_OP1_UP_EN_Pos = 0x4 + // Bit mask of OP1_UP_EN field. + MCPWM_UPDATE_CFG_OP1_UP_EN_Msk = 0x10 + // Bit OP1_UP_EN. + MCPWM_UPDATE_CFG_OP1_UP_EN = 0x10 + // Position of OP1_FORCE_UP field. + MCPWM_UPDATE_CFG_OP1_FORCE_UP_Pos = 0x5 + // Bit mask of OP1_FORCE_UP field. + MCPWM_UPDATE_CFG_OP1_FORCE_UP_Msk = 0x20 + // Bit OP1_FORCE_UP. + MCPWM_UPDATE_CFG_OP1_FORCE_UP = 0x20 + // Position of OP2_UP_EN field. + MCPWM_UPDATE_CFG_OP2_UP_EN_Pos = 0x6 + // Bit mask of OP2_UP_EN field. + MCPWM_UPDATE_CFG_OP2_UP_EN_Msk = 0x40 + // Bit OP2_UP_EN. + MCPWM_UPDATE_CFG_OP2_UP_EN = 0x40 + // Position of OP2_FORCE_UP field. + MCPWM_UPDATE_CFG_OP2_FORCE_UP_Pos = 0x7 + // Bit mask of OP2_FORCE_UP field. + MCPWM_UPDATE_CFG_OP2_FORCE_UP_Msk = 0x80 + // Bit OP2_FORCE_UP. + MCPWM_UPDATE_CFG_OP2_FORCE_UP = 0x80 + + // INT_ENA: Interrupt enable bits + // Position of TIMER0_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_STOP_INT_ENA_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_STOP_INT_ENA_Msk = 0x1 + // Bit TIMER0_STOP_INT_ENA. + MCPWM_INT_ENA_TIMER0_STOP_INT_ENA = 0x1 + // Position of TIMER1_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_STOP_INT_ENA_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_STOP_INT_ENA_Msk = 0x2 + // Bit TIMER1_STOP_INT_ENA. + MCPWM_INT_ENA_TIMER1_STOP_INT_ENA = 0x2 + // Position of TIMER2_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_STOP_INT_ENA_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_STOP_INT_ENA_Msk = 0x4 + // Bit TIMER2_STOP_INT_ENA. + MCPWM_INT_ENA_TIMER2_STOP_INT_ENA = 0x4 + // Position of TIMER0_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA_Msk = 0x8 + // Bit TIMER0_TEZ_INT_ENA. + MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA = 0x8 + // Position of TIMER1_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA_Msk = 0x10 + // Bit TIMER1_TEZ_INT_ENA. + MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA = 0x10 + // Position of TIMER2_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA_Msk = 0x20 + // Bit TIMER2_TEZ_INT_ENA. + MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA = 0x20 + // Position of TIMER0_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEP_INT_ENA_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER0_TEP_INT_ENA_Msk = 0x40 + // Bit TIMER0_TEP_INT_ENA. + MCPWM_INT_ENA_TIMER0_TEP_INT_ENA = 0x40 + // Position of TIMER1_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEP_INT_ENA_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER1_TEP_INT_ENA_Msk = 0x80 + // Bit TIMER1_TEP_INT_ENA. + MCPWM_INT_ENA_TIMER1_TEP_INT_ENA = 0x80 + // Position of TIMER2_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEP_INT_ENA_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_ENA field. + MCPWM_INT_ENA_TIMER2_TEP_INT_ENA_Msk = 0x100 + // Bit TIMER2_TEP_INT_ENA. + MCPWM_INT_ENA_TIMER2_TEP_INT_ENA = 0x100 + // Position of FAULT0_INT_ENA field. + MCPWM_INT_ENA_FAULT0_INT_ENA_Pos = 0x9 + // Bit mask of FAULT0_INT_ENA field. + MCPWM_INT_ENA_FAULT0_INT_ENA_Msk = 0x200 + // Bit FAULT0_INT_ENA. + MCPWM_INT_ENA_FAULT0_INT_ENA = 0x200 + // Position of FAULT1_INT_ENA field. + MCPWM_INT_ENA_FAULT1_INT_ENA_Pos = 0xa + // Bit mask of FAULT1_INT_ENA field. + MCPWM_INT_ENA_FAULT1_INT_ENA_Msk = 0x400 + // Bit FAULT1_INT_ENA. + MCPWM_INT_ENA_FAULT1_INT_ENA = 0x400 + // Position of FAULT2_INT_ENA field. + MCPWM_INT_ENA_FAULT2_INT_ENA_Pos = 0xb + // Bit mask of FAULT2_INT_ENA field. + MCPWM_INT_ENA_FAULT2_INT_ENA_Msk = 0x800 + // Bit FAULT2_INT_ENA. + MCPWM_INT_ENA_FAULT2_INT_ENA = 0x800 + // Position of FAULT0_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT0_CLR_INT_ENA_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT0_CLR_INT_ENA_Msk = 0x1000 + // Bit FAULT0_CLR_INT_ENA. + MCPWM_INT_ENA_FAULT0_CLR_INT_ENA = 0x1000 + // Position of FAULT1_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT1_CLR_INT_ENA_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT1_CLR_INT_ENA_Msk = 0x2000 + // Bit FAULT1_CLR_INT_ENA. + MCPWM_INT_ENA_FAULT1_CLR_INT_ENA = 0x2000 + // Position of FAULT2_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT2_CLR_INT_ENA_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_ENA field. + MCPWM_INT_ENA_FAULT2_CLR_INT_ENA_Msk = 0x4000 + // Bit FAULT2_CLR_INT_ENA. + MCPWM_INT_ENA_FAULT2_CLR_INT_ENA = 0x4000 + // Position of CMPR0_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR0_TEA_INT_ENA_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR0_TEA_INT_ENA_Msk = 0x8000 + // Bit CMPR0_TEA_INT_ENA. + MCPWM_INT_ENA_CMPR0_TEA_INT_ENA = 0x8000 + // Position of CMPR1_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR1_TEA_INT_ENA_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR1_TEA_INT_ENA_Msk = 0x10000 + // Bit CMPR1_TEA_INT_ENA. + MCPWM_INT_ENA_CMPR1_TEA_INT_ENA = 0x10000 + // Position of CMPR2_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR2_TEA_INT_ENA_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_ENA field. + MCPWM_INT_ENA_CMPR2_TEA_INT_ENA_Msk = 0x20000 + // Bit CMPR2_TEA_INT_ENA. + MCPWM_INT_ENA_CMPR2_TEA_INT_ENA = 0x20000 + // Position of CMPR0_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR0_TEB_INT_ENA_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR0_TEB_INT_ENA_Msk = 0x40000 + // Bit CMPR0_TEB_INT_ENA. + MCPWM_INT_ENA_CMPR0_TEB_INT_ENA = 0x40000 + // Position of CMPR1_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR1_TEB_INT_ENA_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR1_TEB_INT_ENA_Msk = 0x80000 + // Bit CMPR1_TEB_INT_ENA. + MCPWM_INT_ENA_CMPR1_TEB_INT_ENA = 0x80000 + // Position of CMPR2_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR2_TEB_INT_ENA_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_ENA field. + MCPWM_INT_ENA_CMPR2_TEB_INT_ENA_Msk = 0x100000 + // Bit CMPR2_TEB_INT_ENA. + MCPWM_INT_ENA_CMPR2_TEB_INT_ENA = 0x100000 + // Position of TZ0_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ0_CBC_INT_ENA_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ0_CBC_INT_ENA_Msk = 0x200000 + // Bit TZ0_CBC_INT_ENA. + MCPWM_INT_ENA_TZ0_CBC_INT_ENA = 0x200000 + // Position of TZ1_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ1_CBC_INT_ENA_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ1_CBC_INT_ENA_Msk = 0x400000 + // Bit TZ1_CBC_INT_ENA. + MCPWM_INT_ENA_TZ1_CBC_INT_ENA = 0x400000 + // Position of TZ2_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ2_CBC_INT_ENA_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_ENA field. + MCPWM_INT_ENA_TZ2_CBC_INT_ENA_Msk = 0x800000 + // Bit TZ2_CBC_INT_ENA. + MCPWM_INT_ENA_TZ2_CBC_INT_ENA = 0x800000 + // Position of TZ0_OST_INT_ENA field. + MCPWM_INT_ENA_TZ0_OST_INT_ENA_Pos = 0x18 + // Bit mask of TZ0_OST_INT_ENA field. + MCPWM_INT_ENA_TZ0_OST_INT_ENA_Msk = 0x1000000 + // Bit TZ0_OST_INT_ENA. + MCPWM_INT_ENA_TZ0_OST_INT_ENA = 0x1000000 + // Position of TZ1_OST_INT_ENA field. + MCPWM_INT_ENA_TZ1_OST_INT_ENA_Pos = 0x19 + // Bit mask of TZ1_OST_INT_ENA field. + MCPWM_INT_ENA_TZ1_OST_INT_ENA_Msk = 0x2000000 + // Bit TZ1_OST_INT_ENA. + MCPWM_INT_ENA_TZ1_OST_INT_ENA = 0x2000000 + // Position of TZ2_OST_INT_ENA field. + MCPWM_INT_ENA_TZ2_OST_INT_ENA_Pos = 0x1a + // Bit mask of TZ2_OST_INT_ENA field. + MCPWM_INT_ENA_TZ2_OST_INT_ENA_Msk = 0x4000000 + // Bit TZ2_OST_INT_ENA. + MCPWM_INT_ENA_TZ2_OST_INT_ENA = 0x4000000 + // Position of CAP0_INT_ENA field. + MCPWM_INT_ENA_CAP0_INT_ENA_Pos = 0x1b + // Bit mask of CAP0_INT_ENA field. + MCPWM_INT_ENA_CAP0_INT_ENA_Msk = 0x8000000 + // Bit CAP0_INT_ENA. + MCPWM_INT_ENA_CAP0_INT_ENA = 0x8000000 + // Position of CAP1_INT_ENA field. + MCPWM_INT_ENA_CAP1_INT_ENA_Pos = 0x1c + // Bit mask of CAP1_INT_ENA field. + MCPWM_INT_ENA_CAP1_INT_ENA_Msk = 0x10000000 + // Bit CAP1_INT_ENA. + MCPWM_INT_ENA_CAP1_INT_ENA = 0x10000000 + // Position of CAP2_INT_ENA field. + MCPWM_INT_ENA_CAP2_INT_ENA_Pos = 0x1d + // Bit mask of CAP2_INT_ENA field. + MCPWM_INT_ENA_CAP2_INT_ENA_Msk = 0x20000000 + // Bit CAP2_INT_ENA. + MCPWM_INT_ENA_CAP2_INT_ENA = 0x20000000 + + // INT_RAW: Raw interrupt status + // Position of TIMER0_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_STOP_INT_RAW_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_STOP_INT_RAW_Msk = 0x1 + // Bit TIMER0_STOP_INT_RAW. + MCPWM_INT_RAW_TIMER0_STOP_INT_RAW = 0x1 + // Position of TIMER1_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_STOP_INT_RAW_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_STOP_INT_RAW_Msk = 0x2 + // Bit TIMER1_STOP_INT_RAW. + MCPWM_INT_RAW_TIMER1_STOP_INT_RAW = 0x2 + // Position of TIMER2_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_STOP_INT_RAW_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_STOP_INT_RAW_Msk = 0x4 + // Bit TIMER2_STOP_INT_RAW. + MCPWM_INT_RAW_TIMER2_STOP_INT_RAW = 0x4 + // Position of TIMER0_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW_Msk = 0x8 + // Bit TIMER0_TEZ_INT_RAW. + MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW = 0x8 + // Position of TIMER1_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW_Msk = 0x10 + // Bit TIMER1_TEZ_INT_RAW. + MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW = 0x10 + // Position of TIMER2_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW_Msk = 0x20 + // Bit TIMER2_TEZ_INT_RAW. + MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW = 0x20 + // Position of TIMER0_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEP_INT_RAW_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER0_TEP_INT_RAW_Msk = 0x40 + // Bit TIMER0_TEP_INT_RAW. + MCPWM_INT_RAW_TIMER0_TEP_INT_RAW = 0x40 + // Position of TIMER1_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEP_INT_RAW_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER1_TEP_INT_RAW_Msk = 0x80 + // Bit TIMER1_TEP_INT_RAW. + MCPWM_INT_RAW_TIMER1_TEP_INT_RAW = 0x80 + // Position of TIMER2_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEP_INT_RAW_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_RAW field. + MCPWM_INT_RAW_TIMER2_TEP_INT_RAW_Msk = 0x100 + // Bit TIMER2_TEP_INT_RAW. + MCPWM_INT_RAW_TIMER2_TEP_INT_RAW = 0x100 + // Position of FAULT0_INT_RAW field. + MCPWM_INT_RAW_FAULT0_INT_RAW_Pos = 0x9 + // Bit mask of FAULT0_INT_RAW field. + MCPWM_INT_RAW_FAULT0_INT_RAW_Msk = 0x200 + // Bit FAULT0_INT_RAW. + MCPWM_INT_RAW_FAULT0_INT_RAW = 0x200 + // Position of FAULT1_INT_RAW field. + MCPWM_INT_RAW_FAULT1_INT_RAW_Pos = 0xa + // Bit mask of FAULT1_INT_RAW field. + MCPWM_INT_RAW_FAULT1_INT_RAW_Msk = 0x400 + // Bit FAULT1_INT_RAW. + MCPWM_INT_RAW_FAULT1_INT_RAW = 0x400 + // Position of FAULT2_INT_RAW field. + MCPWM_INT_RAW_FAULT2_INT_RAW_Pos = 0xb + // Bit mask of FAULT2_INT_RAW field. + MCPWM_INT_RAW_FAULT2_INT_RAW_Msk = 0x800 + // Bit FAULT2_INT_RAW. + MCPWM_INT_RAW_FAULT2_INT_RAW = 0x800 + // Position of FAULT0_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT0_CLR_INT_RAW_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT0_CLR_INT_RAW_Msk = 0x1000 + // Bit FAULT0_CLR_INT_RAW. + MCPWM_INT_RAW_FAULT0_CLR_INT_RAW = 0x1000 + // Position of FAULT1_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT1_CLR_INT_RAW_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT1_CLR_INT_RAW_Msk = 0x2000 + // Bit FAULT1_CLR_INT_RAW. + MCPWM_INT_RAW_FAULT1_CLR_INT_RAW = 0x2000 + // Position of FAULT2_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT2_CLR_INT_RAW_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_RAW field. + MCPWM_INT_RAW_FAULT2_CLR_INT_RAW_Msk = 0x4000 + // Bit FAULT2_CLR_INT_RAW. + MCPWM_INT_RAW_FAULT2_CLR_INT_RAW = 0x4000 + // Position of CMPR0_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR0_TEA_INT_RAW_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR0_TEA_INT_RAW_Msk = 0x8000 + // Bit CMPR0_TEA_INT_RAW. + MCPWM_INT_RAW_CMPR0_TEA_INT_RAW = 0x8000 + // Position of CMPR1_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR1_TEA_INT_RAW_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR1_TEA_INT_RAW_Msk = 0x10000 + // Bit CMPR1_TEA_INT_RAW. + MCPWM_INT_RAW_CMPR1_TEA_INT_RAW = 0x10000 + // Position of CMPR2_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR2_TEA_INT_RAW_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_RAW field. + MCPWM_INT_RAW_CMPR2_TEA_INT_RAW_Msk = 0x20000 + // Bit CMPR2_TEA_INT_RAW. + MCPWM_INT_RAW_CMPR2_TEA_INT_RAW = 0x20000 + // Position of CMPR0_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR0_TEB_INT_RAW_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR0_TEB_INT_RAW_Msk = 0x40000 + // Bit CMPR0_TEB_INT_RAW. + MCPWM_INT_RAW_CMPR0_TEB_INT_RAW = 0x40000 + // Position of CMPR1_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR1_TEB_INT_RAW_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR1_TEB_INT_RAW_Msk = 0x80000 + // Bit CMPR1_TEB_INT_RAW. + MCPWM_INT_RAW_CMPR1_TEB_INT_RAW = 0x80000 + // Position of CMPR2_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR2_TEB_INT_RAW_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_RAW field. + MCPWM_INT_RAW_CMPR2_TEB_INT_RAW_Msk = 0x100000 + // Bit CMPR2_TEB_INT_RAW. + MCPWM_INT_RAW_CMPR2_TEB_INT_RAW = 0x100000 + // Position of TZ0_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ0_CBC_INT_RAW_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ0_CBC_INT_RAW_Msk = 0x200000 + // Bit TZ0_CBC_INT_RAW. + MCPWM_INT_RAW_TZ0_CBC_INT_RAW = 0x200000 + // Position of TZ1_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ1_CBC_INT_RAW_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ1_CBC_INT_RAW_Msk = 0x400000 + // Bit TZ1_CBC_INT_RAW. + MCPWM_INT_RAW_TZ1_CBC_INT_RAW = 0x400000 + // Position of TZ2_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ2_CBC_INT_RAW_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_RAW field. + MCPWM_INT_RAW_TZ2_CBC_INT_RAW_Msk = 0x800000 + // Bit TZ2_CBC_INT_RAW. + MCPWM_INT_RAW_TZ2_CBC_INT_RAW = 0x800000 + // Position of TZ0_OST_INT_RAW field. + MCPWM_INT_RAW_TZ0_OST_INT_RAW_Pos = 0x18 + // Bit mask of TZ0_OST_INT_RAW field. + MCPWM_INT_RAW_TZ0_OST_INT_RAW_Msk = 0x1000000 + // Bit TZ0_OST_INT_RAW. + MCPWM_INT_RAW_TZ0_OST_INT_RAW = 0x1000000 + // Position of TZ1_OST_INT_RAW field. + MCPWM_INT_RAW_TZ1_OST_INT_RAW_Pos = 0x19 + // Bit mask of TZ1_OST_INT_RAW field. + MCPWM_INT_RAW_TZ1_OST_INT_RAW_Msk = 0x2000000 + // Bit TZ1_OST_INT_RAW. + MCPWM_INT_RAW_TZ1_OST_INT_RAW = 0x2000000 + // Position of TZ2_OST_INT_RAW field. + MCPWM_INT_RAW_TZ2_OST_INT_RAW_Pos = 0x1a + // Bit mask of TZ2_OST_INT_RAW field. + MCPWM_INT_RAW_TZ2_OST_INT_RAW_Msk = 0x4000000 + // Bit TZ2_OST_INT_RAW. + MCPWM_INT_RAW_TZ2_OST_INT_RAW = 0x4000000 + // Position of CAP0_INT_RAW field. + MCPWM_INT_RAW_CAP0_INT_RAW_Pos = 0x1b + // Bit mask of CAP0_INT_RAW field. + MCPWM_INT_RAW_CAP0_INT_RAW_Msk = 0x8000000 + // Bit CAP0_INT_RAW. + MCPWM_INT_RAW_CAP0_INT_RAW = 0x8000000 + // Position of CAP1_INT_RAW field. + MCPWM_INT_RAW_CAP1_INT_RAW_Pos = 0x1c + // Bit mask of CAP1_INT_RAW field. + MCPWM_INT_RAW_CAP1_INT_RAW_Msk = 0x10000000 + // Bit CAP1_INT_RAW. + MCPWM_INT_RAW_CAP1_INT_RAW = 0x10000000 + // Position of CAP2_INT_RAW field. + MCPWM_INT_RAW_CAP2_INT_RAW_Pos = 0x1d + // Bit mask of CAP2_INT_RAW field. + MCPWM_INT_RAW_CAP2_INT_RAW_Msk = 0x20000000 + // Bit CAP2_INT_RAW. + MCPWM_INT_RAW_CAP2_INT_RAW = 0x20000000 + + // INT_ST: Masked interrupt status + // Position of TIMER0_STOP_INT_ST field. + MCPWM_INT_ST_TIMER0_STOP_INT_ST_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_ST field. + MCPWM_INT_ST_TIMER0_STOP_INT_ST_Msk = 0x1 + // Bit TIMER0_STOP_INT_ST. + MCPWM_INT_ST_TIMER0_STOP_INT_ST = 0x1 + // Position of TIMER1_STOP_INT_ST field. + MCPWM_INT_ST_TIMER1_STOP_INT_ST_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_ST field. + MCPWM_INT_ST_TIMER1_STOP_INT_ST_Msk = 0x2 + // Bit TIMER1_STOP_INT_ST. + MCPWM_INT_ST_TIMER1_STOP_INT_ST = 0x2 + // Position of TIMER2_STOP_INT_ST field. + MCPWM_INT_ST_TIMER2_STOP_INT_ST_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_ST field. + MCPWM_INT_ST_TIMER2_STOP_INT_ST_Msk = 0x4 + // Bit TIMER2_STOP_INT_ST. + MCPWM_INT_ST_TIMER2_STOP_INT_ST = 0x4 + // Position of TIMER0_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER0_TEZ_INT_ST_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER0_TEZ_INT_ST_Msk = 0x8 + // Bit TIMER0_TEZ_INT_ST. + MCPWM_INT_ST_TIMER0_TEZ_INT_ST = 0x8 + // Position of TIMER1_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER1_TEZ_INT_ST_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER1_TEZ_INT_ST_Msk = 0x10 + // Bit TIMER1_TEZ_INT_ST. + MCPWM_INT_ST_TIMER1_TEZ_INT_ST = 0x10 + // Position of TIMER2_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER2_TEZ_INT_ST_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_ST field. + MCPWM_INT_ST_TIMER2_TEZ_INT_ST_Msk = 0x20 + // Bit TIMER2_TEZ_INT_ST. + MCPWM_INT_ST_TIMER2_TEZ_INT_ST = 0x20 + // Position of TIMER0_TEP_INT_ST field. + MCPWM_INT_ST_TIMER0_TEP_INT_ST_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_ST field. + MCPWM_INT_ST_TIMER0_TEP_INT_ST_Msk = 0x40 + // Bit TIMER0_TEP_INT_ST. + MCPWM_INT_ST_TIMER0_TEP_INT_ST = 0x40 + // Position of TIMER1_TEP_INT_ST field. + MCPWM_INT_ST_TIMER1_TEP_INT_ST_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_ST field. + MCPWM_INT_ST_TIMER1_TEP_INT_ST_Msk = 0x80 + // Bit TIMER1_TEP_INT_ST. + MCPWM_INT_ST_TIMER1_TEP_INT_ST = 0x80 + // Position of TIMER2_TEP_INT_ST field. + MCPWM_INT_ST_TIMER2_TEP_INT_ST_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_ST field. + MCPWM_INT_ST_TIMER2_TEP_INT_ST_Msk = 0x100 + // Bit TIMER2_TEP_INT_ST. + MCPWM_INT_ST_TIMER2_TEP_INT_ST = 0x100 + // Position of FAULT0_INT_ST field. + MCPWM_INT_ST_FAULT0_INT_ST_Pos = 0x9 + // Bit mask of FAULT0_INT_ST field. + MCPWM_INT_ST_FAULT0_INT_ST_Msk = 0x200 + // Bit FAULT0_INT_ST. + MCPWM_INT_ST_FAULT0_INT_ST = 0x200 + // Position of FAULT1_INT_ST field. + MCPWM_INT_ST_FAULT1_INT_ST_Pos = 0xa + // Bit mask of FAULT1_INT_ST field. + MCPWM_INT_ST_FAULT1_INT_ST_Msk = 0x400 + // Bit FAULT1_INT_ST. + MCPWM_INT_ST_FAULT1_INT_ST = 0x400 + // Position of FAULT2_INT_ST field. + MCPWM_INT_ST_FAULT2_INT_ST_Pos = 0xb + // Bit mask of FAULT2_INT_ST field. + MCPWM_INT_ST_FAULT2_INT_ST_Msk = 0x800 + // Bit FAULT2_INT_ST. + MCPWM_INT_ST_FAULT2_INT_ST = 0x800 + // Position of FAULT0_CLR_INT_ST field. + MCPWM_INT_ST_FAULT0_CLR_INT_ST_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_ST field. + MCPWM_INT_ST_FAULT0_CLR_INT_ST_Msk = 0x1000 + // Bit FAULT0_CLR_INT_ST. + MCPWM_INT_ST_FAULT0_CLR_INT_ST = 0x1000 + // Position of FAULT1_CLR_INT_ST field. + MCPWM_INT_ST_FAULT1_CLR_INT_ST_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_ST field. + MCPWM_INT_ST_FAULT1_CLR_INT_ST_Msk = 0x2000 + // Bit FAULT1_CLR_INT_ST. + MCPWM_INT_ST_FAULT1_CLR_INT_ST = 0x2000 + // Position of FAULT2_CLR_INT_ST field. + MCPWM_INT_ST_FAULT2_CLR_INT_ST_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_ST field. + MCPWM_INT_ST_FAULT2_CLR_INT_ST_Msk = 0x4000 + // Bit FAULT2_CLR_INT_ST. + MCPWM_INT_ST_FAULT2_CLR_INT_ST = 0x4000 + // Position of CMPR0_TEA_INT_ST field. + MCPWM_INT_ST_CMPR0_TEA_INT_ST_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_ST field. + MCPWM_INT_ST_CMPR0_TEA_INT_ST_Msk = 0x8000 + // Bit CMPR0_TEA_INT_ST. + MCPWM_INT_ST_CMPR0_TEA_INT_ST = 0x8000 + // Position of CMPR1_TEA_INT_ST field. + MCPWM_INT_ST_CMPR1_TEA_INT_ST_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_ST field. + MCPWM_INT_ST_CMPR1_TEA_INT_ST_Msk = 0x10000 + // Bit CMPR1_TEA_INT_ST. + MCPWM_INT_ST_CMPR1_TEA_INT_ST = 0x10000 + // Position of CMPR2_TEA_INT_ST field. + MCPWM_INT_ST_CMPR2_TEA_INT_ST_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_ST field. + MCPWM_INT_ST_CMPR2_TEA_INT_ST_Msk = 0x20000 + // Bit CMPR2_TEA_INT_ST. + MCPWM_INT_ST_CMPR2_TEA_INT_ST = 0x20000 + // Position of CMPR0_TEB_INT_ST field. + MCPWM_INT_ST_CMPR0_TEB_INT_ST_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_ST field. + MCPWM_INT_ST_CMPR0_TEB_INT_ST_Msk = 0x40000 + // Bit CMPR0_TEB_INT_ST. + MCPWM_INT_ST_CMPR0_TEB_INT_ST = 0x40000 + // Position of CMPR1_TEB_INT_ST field. + MCPWM_INT_ST_CMPR1_TEB_INT_ST_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_ST field. + MCPWM_INT_ST_CMPR1_TEB_INT_ST_Msk = 0x80000 + // Bit CMPR1_TEB_INT_ST. + MCPWM_INT_ST_CMPR1_TEB_INT_ST = 0x80000 + // Position of CMPR2_TEB_INT_ST field. + MCPWM_INT_ST_CMPR2_TEB_INT_ST_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_ST field. + MCPWM_INT_ST_CMPR2_TEB_INT_ST_Msk = 0x100000 + // Bit CMPR2_TEB_INT_ST. + MCPWM_INT_ST_CMPR2_TEB_INT_ST = 0x100000 + // Position of TZ0_CBC_INT_ST field. + MCPWM_INT_ST_TZ0_CBC_INT_ST_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_ST field. + MCPWM_INT_ST_TZ0_CBC_INT_ST_Msk = 0x200000 + // Bit TZ0_CBC_INT_ST. + MCPWM_INT_ST_TZ0_CBC_INT_ST = 0x200000 + // Position of TZ1_CBC_INT_ST field. + MCPWM_INT_ST_TZ1_CBC_INT_ST_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_ST field. + MCPWM_INT_ST_TZ1_CBC_INT_ST_Msk = 0x400000 + // Bit TZ1_CBC_INT_ST. + MCPWM_INT_ST_TZ1_CBC_INT_ST = 0x400000 + // Position of TZ2_CBC_INT_ST field. + MCPWM_INT_ST_TZ2_CBC_INT_ST_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_ST field. + MCPWM_INT_ST_TZ2_CBC_INT_ST_Msk = 0x800000 + // Bit TZ2_CBC_INT_ST. + MCPWM_INT_ST_TZ2_CBC_INT_ST = 0x800000 + // Position of TZ0_OST_INT_ST field. + MCPWM_INT_ST_TZ0_OST_INT_ST_Pos = 0x18 + // Bit mask of TZ0_OST_INT_ST field. + MCPWM_INT_ST_TZ0_OST_INT_ST_Msk = 0x1000000 + // Bit TZ0_OST_INT_ST. + MCPWM_INT_ST_TZ0_OST_INT_ST = 0x1000000 + // Position of TZ1_OST_INT_ST field. + MCPWM_INT_ST_TZ1_OST_INT_ST_Pos = 0x19 + // Bit mask of TZ1_OST_INT_ST field. + MCPWM_INT_ST_TZ1_OST_INT_ST_Msk = 0x2000000 + // Bit TZ1_OST_INT_ST. + MCPWM_INT_ST_TZ1_OST_INT_ST = 0x2000000 + // Position of TZ2_OST_INT_ST field. + MCPWM_INT_ST_TZ2_OST_INT_ST_Pos = 0x1a + // Bit mask of TZ2_OST_INT_ST field. + MCPWM_INT_ST_TZ2_OST_INT_ST_Msk = 0x4000000 + // Bit TZ2_OST_INT_ST. + MCPWM_INT_ST_TZ2_OST_INT_ST = 0x4000000 + // Position of CAP0_INT_ST field. + MCPWM_INT_ST_CAP0_INT_ST_Pos = 0x1b + // Bit mask of CAP0_INT_ST field. + MCPWM_INT_ST_CAP0_INT_ST_Msk = 0x8000000 + // Bit CAP0_INT_ST. + MCPWM_INT_ST_CAP0_INT_ST = 0x8000000 + // Position of CAP1_INT_ST field. + MCPWM_INT_ST_CAP1_INT_ST_Pos = 0x1c + // Bit mask of CAP1_INT_ST field. + MCPWM_INT_ST_CAP1_INT_ST_Msk = 0x10000000 + // Bit CAP1_INT_ST. + MCPWM_INT_ST_CAP1_INT_ST = 0x10000000 + // Position of CAP2_INT_ST field. + MCPWM_INT_ST_CAP2_INT_ST_Pos = 0x1d + // Bit mask of CAP2_INT_ST field. + MCPWM_INT_ST_CAP2_INT_ST_Msk = 0x20000000 + // Bit CAP2_INT_ST. + MCPWM_INT_ST_CAP2_INT_ST = 0x20000000 + + // INT_CLR: Interrupt clear bits + // Position of TIMER0_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_STOP_INT_CLR_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_STOP_INT_CLR_Msk = 0x1 + // Bit TIMER0_STOP_INT_CLR. + MCPWM_INT_CLR_TIMER0_STOP_INT_CLR = 0x1 + // Position of TIMER1_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_STOP_INT_CLR_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_STOP_INT_CLR_Msk = 0x2 + // Bit TIMER1_STOP_INT_CLR. + MCPWM_INT_CLR_TIMER1_STOP_INT_CLR = 0x2 + // Position of TIMER2_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_STOP_INT_CLR_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_STOP_INT_CLR_Msk = 0x4 + // Bit TIMER2_STOP_INT_CLR. + MCPWM_INT_CLR_TIMER2_STOP_INT_CLR = 0x4 + // Position of TIMER0_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR_Msk = 0x8 + // Bit TIMER0_TEZ_INT_CLR. + MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR = 0x8 + // Position of TIMER1_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR_Msk = 0x10 + // Bit TIMER1_TEZ_INT_CLR. + MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR = 0x10 + // Position of TIMER2_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR_Msk = 0x20 + // Bit TIMER2_TEZ_INT_CLR. + MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR = 0x20 + // Position of TIMER0_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEP_INT_CLR_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER0_TEP_INT_CLR_Msk = 0x40 + // Bit TIMER0_TEP_INT_CLR. + MCPWM_INT_CLR_TIMER0_TEP_INT_CLR = 0x40 + // Position of TIMER1_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEP_INT_CLR_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER1_TEP_INT_CLR_Msk = 0x80 + // Bit TIMER1_TEP_INT_CLR. + MCPWM_INT_CLR_TIMER1_TEP_INT_CLR = 0x80 + // Position of TIMER2_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEP_INT_CLR_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_CLR field. + MCPWM_INT_CLR_TIMER2_TEP_INT_CLR_Msk = 0x100 + // Bit TIMER2_TEP_INT_CLR. + MCPWM_INT_CLR_TIMER2_TEP_INT_CLR = 0x100 + // Position of FAULT0_INT_CLR field. + MCPWM_INT_CLR_FAULT0_INT_CLR_Pos = 0x9 + // Bit mask of FAULT0_INT_CLR field. + MCPWM_INT_CLR_FAULT0_INT_CLR_Msk = 0x200 + // Bit FAULT0_INT_CLR. + MCPWM_INT_CLR_FAULT0_INT_CLR = 0x200 + // Position of FAULT1_INT_CLR field. + MCPWM_INT_CLR_FAULT1_INT_CLR_Pos = 0xa + // Bit mask of FAULT1_INT_CLR field. + MCPWM_INT_CLR_FAULT1_INT_CLR_Msk = 0x400 + // Bit FAULT1_INT_CLR. + MCPWM_INT_CLR_FAULT1_INT_CLR = 0x400 + // Position of FAULT2_INT_CLR field. + MCPWM_INT_CLR_FAULT2_INT_CLR_Pos = 0xb + // Bit mask of FAULT2_INT_CLR field. + MCPWM_INT_CLR_FAULT2_INT_CLR_Msk = 0x800 + // Bit FAULT2_INT_CLR. + MCPWM_INT_CLR_FAULT2_INT_CLR = 0x800 + // Position of FAULT0_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT0_CLR_INT_CLR_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT0_CLR_INT_CLR_Msk = 0x1000 + // Bit FAULT0_CLR_INT_CLR. + MCPWM_INT_CLR_FAULT0_CLR_INT_CLR = 0x1000 + // Position of FAULT1_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT1_CLR_INT_CLR_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT1_CLR_INT_CLR_Msk = 0x2000 + // Bit FAULT1_CLR_INT_CLR. + MCPWM_INT_CLR_FAULT1_CLR_INT_CLR = 0x2000 + // Position of FAULT2_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT2_CLR_INT_CLR_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_CLR field. + MCPWM_INT_CLR_FAULT2_CLR_INT_CLR_Msk = 0x4000 + // Bit FAULT2_CLR_INT_CLR. + MCPWM_INT_CLR_FAULT2_CLR_INT_CLR = 0x4000 + // Position of CMPR0_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR0_TEA_INT_CLR_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR0_TEA_INT_CLR_Msk = 0x8000 + // Bit CMPR0_TEA_INT_CLR. + MCPWM_INT_CLR_CMPR0_TEA_INT_CLR = 0x8000 + // Position of CMPR1_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR1_TEA_INT_CLR_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR1_TEA_INT_CLR_Msk = 0x10000 + // Bit CMPR1_TEA_INT_CLR. + MCPWM_INT_CLR_CMPR1_TEA_INT_CLR = 0x10000 + // Position of CMPR2_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR2_TEA_INT_CLR_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_CLR field. + MCPWM_INT_CLR_CMPR2_TEA_INT_CLR_Msk = 0x20000 + // Bit CMPR2_TEA_INT_CLR. + MCPWM_INT_CLR_CMPR2_TEA_INT_CLR = 0x20000 + // Position of CMPR0_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR0_TEB_INT_CLR_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR0_TEB_INT_CLR_Msk = 0x40000 + // Bit CMPR0_TEB_INT_CLR. + MCPWM_INT_CLR_CMPR0_TEB_INT_CLR = 0x40000 + // Position of CMPR1_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR1_TEB_INT_CLR_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR1_TEB_INT_CLR_Msk = 0x80000 + // Bit CMPR1_TEB_INT_CLR. + MCPWM_INT_CLR_CMPR1_TEB_INT_CLR = 0x80000 + // Position of CMPR2_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR2_TEB_INT_CLR_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_CLR field. + MCPWM_INT_CLR_CMPR2_TEB_INT_CLR_Msk = 0x100000 + // Bit CMPR2_TEB_INT_CLR. + MCPWM_INT_CLR_CMPR2_TEB_INT_CLR = 0x100000 + // Position of TZ0_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ0_CBC_INT_CLR_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ0_CBC_INT_CLR_Msk = 0x200000 + // Bit TZ0_CBC_INT_CLR. + MCPWM_INT_CLR_TZ0_CBC_INT_CLR = 0x200000 + // Position of TZ1_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ1_CBC_INT_CLR_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ1_CBC_INT_CLR_Msk = 0x400000 + // Bit TZ1_CBC_INT_CLR. + MCPWM_INT_CLR_TZ1_CBC_INT_CLR = 0x400000 + // Position of TZ2_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ2_CBC_INT_CLR_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_CLR field. + MCPWM_INT_CLR_TZ2_CBC_INT_CLR_Msk = 0x800000 + // Bit TZ2_CBC_INT_CLR. + MCPWM_INT_CLR_TZ2_CBC_INT_CLR = 0x800000 + // Position of TZ0_OST_INT_CLR field. + MCPWM_INT_CLR_TZ0_OST_INT_CLR_Pos = 0x18 + // Bit mask of TZ0_OST_INT_CLR field. + MCPWM_INT_CLR_TZ0_OST_INT_CLR_Msk = 0x1000000 + // Bit TZ0_OST_INT_CLR. + MCPWM_INT_CLR_TZ0_OST_INT_CLR = 0x1000000 + // Position of TZ1_OST_INT_CLR field. + MCPWM_INT_CLR_TZ1_OST_INT_CLR_Pos = 0x19 + // Bit mask of TZ1_OST_INT_CLR field. + MCPWM_INT_CLR_TZ1_OST_INT_CLR_Msk = 0x2000000 + // Bit TZ1_OST_INT_CLR. + MCPWM_INT_CLR_TZ1_OST_INT_CLR = 0x2000000 + // Position of TZ2_OST_INT_CLR field. + MCPWM_INT_CLR_TZ2_OST_INT_CLR_Pos = 0x1a + // Bit mask of TZ2_OST_INT_CLR field. + MCPWM_INT_CLR_TZ2_OST_INT_CLR_Msk = 0x4000000 + // Bit TZ2_OST_INT_CLR. + MCPWM_INT_CLR_TZ2_OST_INT_CLR = 0x4000000 + // Position of CAP0_INT_CLR field. + MCPWM_INT_CLR_CAP0_INT_CLR_Pos = 0x1b + // Bit mask of CAP0_INT_CLR field. + MCPWM_INT_CLR_CAP0_INT_CLR_Msk = 0x8000000 + // Bit CAP0_INT_CLR. + MCPWM_INT_CLR_CAP0_INT_CLR = 0x8000000 + // Position of CAP1_INT_CLR field. + MCPWM_INT_CLR_CAP1_INT_CLR_Pos = 0x1c + // Bit mask of CAP1_INT_CLR field. + MCPWM_INT_CLR_CAP1_INT_CLR_Msk = 0x10000000 + // Bit CAP1_INT_CLR. + MCPWM_INT_CLR_CAP1_INT_CLR = 0x10000000 + // Position of CAP2_INT_CLR field. + MCPWM_INT_CLR_CAP2_INT_CLR_Pos = 0x1d + // Bit mask of CAP2_INT_CLR field. + MCPWM_INT_CLR_CAP2_INT_CLR_Msk = 0x20000000 + // Bit CAP2_INT_CLR. + MCPWM_INT_CLR_CAP2_INT_CLR = 0x20000000 + + // EVT_EN: MCPWM event enable register + // Position of EVT_TIMER0_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER0_STOP_EN_Pos = 0x0 + // Bit mask of EVT_TIMER0_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER0_STOP_EN_Msk = 0x1 + // Bit EVT_TIMER0_STOP_EN. + MCPWM_EVT_EN_EVT_TIMER0_STOP_EN = 0x1 + // Position of EVT_TIMER1_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER1_STOP_EN_Pos = 0x1 + // Bit mask of EVT_TIMER1_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER1_STOP_EN_Msk = 0x2 + // Bit EVT_TIMER1_STOP_EN. + MCPWM_EVT_EN_EVT_TIMER1_STOP_EN = 0x2 + // Position of EVT_TIMER2_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER2_STOP_EN_Pos = 0x2 + // Bit mask of EVT_TIMER2_STOP_EN field. + MCPWM_EVT_EN_EVT_TIMER2_STOP_EN_Msk = 0x4 + // Bit EVT_TIMER2_STOP_EN. + MCPWM_EVT_EN_EVT_TIMER2_STOP_EN = 0x4 + // Position of EVT_TIMER0_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER0_TEZ_EN_Pos = 0x3 + // Bit mask of EVT_TIMER0_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER0_TEZ_EN_Msk = 0x8 + // Bit EVT_TIMER0_TEZ_EN. + MCPWM_EVT_EN_EVT_TIMER0_TEZ_EN = 0x8 + // Position of EVT_TIMER1_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER1_TEZ_EN_Pos = 0x4 + // Bit mask of EVT_TIMER1_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER1_TEZ_EN_Msk = 0x10 + // Bit EVT_TIMER1_TEZ_EN. + MCPWM_EVT_EN_EVT_TIMER1_TEZ_EN = 0x10 + // Position of EVT_TIMER2_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER2_TEZ_EN_Pos = 0x5 + // Bit mask of EVT_TIMER2_TEZ_EN field. + MCPWM_EVT_EN_EVT_TIMER2_TEZ_EN_Msk = 0x20 + // Bit EVT_TIMER2_TEZ_EN. + MCPWM_EVT_EN_EVT_TIMER2_TEZ_EN = 0x20 + // Position of EVT_TIMER0_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER0_TEP_EN_Pos = 0x6 + // Bit mask of EVT_TIMER0_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER0_TEP_EN_Msk = 0x40 + // Bit EVT_TIMER0_TEP_EN. + MCPWM_EVT_EN_EVT_TIMER0_TEP_EN = 0x40 + // Position of EVT_TIMER1_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER1_TEP_EN_Pos = 0x7 + // Bit mask of EVT_TIMER1_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER1_TEP_EN_Msk = 0x80 + // Bit EVT_TIMER1_TEP_EN. + MCPWM_EVT_EN_EVT_TIMER1_TEP_EN = 0x80 + // Position of EVT_TIMER2_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER2_TEP_EN_Pos = 0x8 + // Bit mask of EVT_TIMER2_TEP_EN field. + MCPWM_EVT_EN_EVT_TIMER2_TEP_EN_Msk = 0x100 + // Bit EVT_TIMER2_TEP_EN. + MCPWM_EVT_EN_EVT_TIMER2_TEP_EN = 0x100 + // Position of EVT_OP0_TEA_EN field. + MCPWM_EVT_EN_EVT_OP0_TEA_EN_Pos = 0x9 + // Bit mask of EVT_OP0_TEA_EN field. + MCPWM_EVT_EN_EVT_OP0_TEA_EN_Msk = 0x200 + // Bit EVT_OP0_TEA_EN. + MCPWM_EVT_EN_EVT_OP0_TEA_EN = 0x200 + // Position of EVT_OP1_TEA_EN field. + MCPWM_EVT_EN_EVT_OP1_TEA_EN_Pos = 0xa + // Bit mask of EVT_OP1_TEA_EN field. + MCPWM_EVT_EN_EVT_OP1_TEA_EN_Msk = 0x400 + // Bit EVT_OP1_TEA_EN. + MCPWM_EVT_EN_EVT_OP1_TEA_EN = 0x400 + // Position of EVT_OP2_TEA_EN field. + MCPWM_EVT_EN_EVT_OP2_TEA_EN_Pos = 0xb + // Bit mask of EVT_OP2_TEA_EN field. + MCPWM_EVT_EN_EVT_OP2_TEA_EN_Msk = 0x800 + // Bit EVT_OP2_TEA_EN. + MCPWM_EVT_EN_EVT_OP2_TEA_EN = 0x800 + // Position of EVT_OP0_TEB_EN field. + MCPWM_EVT_EN_EVT_OP0_TEB_EN_Pos = 0xc + // Bit mask of EVT_OP0_TEB_EN field. + MCPWM_EVT_EN_EVT_OP0_TEB_EN_Msk = 0x1000 + // Bit EVT_OP0_TEB_EN. + MCPWM_EVT_EN_EVT_OP0_TEB_EN = 0x1000 + // Position of EVT_OP1_TEB_EN field. + MCPWM_EVT_EN_EVT_OP1_TEB_EN_Pos = 0xd + // Bit mask of EVT_OP1_TEB_EN field. + MCPWM_EVT_EN_EVT_OP1_TEB_EN_Msk = 0x2000 + // Bit EVT_OP1_TEB_EN. + MCPWM_EVT_EN_EVT_OP1_TEB_EN = 0x2000 + // Position of EVT_OP2_TEB_EN field. + MCPWM_EVT_EN_EVT_OP2_TEB_EN_Pos = 0xe + // Bit mask of EVT_OP2_TEB_EN field. + MCPWM_EVT_EN_EVT_OP2_TEB_EN_Msk = 0x4000 + // Bit EVT_OP2_TEB_EN. + MCPWM_EVT_EN_EVT_OP2_TEB_EN = 0x4000 + // Position of EVT_F0_EN field. + MCPWM_EVT_EN_EVT_F0_EN_Pos = 0xf + // Bit mask of EVT_F0_EN field. + MCPWM_EVT_EN_EVT_F0_EN_Msk = 0x8000 + // Bit EVT_F0_EN. + MCPWM_EVT_EN_EVT_F0_EN = 0x8000 + // Position of EVT_F1_EN field. + MCPWM_EVT_EN_EVT_F1_EN_Pos = 0x10 + // Bit mask of EVT_F1_EN field. + MCPWM_EVT_EN_EVT_F1_EN_Msk = 0x10000 + // Bit EVT_F1_EN. + MCPWM_EVT_EN_EVT_F1_EN = 0x10000 + // Position of EVT_F2_EN field. + MCPWM_EVT_EN_EVT_F2_EN_Pos = 0x11 + // Bit mask of EVT_F2_EN field. + MCPWM_EVT_EN_EVT_F2_EN_Msk = 0x20000 + // Bit EVT_F2_EN. + MCPWM_EVT_EN_EVT_F2_EN = 0x20000 + // Position of EVT_F0_CLR_EN field. + MCPWM_EVT_EN_EVT_F0_CLR_EN_Pos = 0x12 + // Bit mask of EVT_F0_CLR_EN field. + MCPWM_EVT_EN_EVT_F0_CLR_EN_Msk = 0x40000 + // Bit EVT_F0_CLR_EN. + MCPWM_EVT_EN_EVT_F0_CLR_EN = 0x40000 + // Position of EVT_F1_CLR_EN field. + MCPWM_EVT_EN_EVT_F1_CLR_EN_Pos = 0x13 + // Bit mask of EVT_F1_CLR_EN field. + MCPWM_EVT_EN_EVT_F1_CLR_EN_Msk = 0x80000 + // Bit EVT_F1_CLR_EN. + MCPWM_EVT_EN_EVT_F1_CLR_EN = 0x80000 + // Position of EVT_F2_CLR_EN field. + MCPWM_EVT_EN_EVT_F2_CLR_EN_Pos = 0x14 + // Bit mask of EVT_F2_CLR_EN field. + MCPWM_EVT_EN_EVT_F2_CLR_EN_Msk = 0x100000 + // Bit EVT_F2_CLR_EN. + MCPWM_EVT_EN_EVT_F2_CLR_EN = 0x100000 + // Position of EVT_TZ0_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ0_CBC_EN_Pos = 0x15 + // Bit mask of EVT_TZ0_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ0_CBC_EN_Msk = 0x200000 + // Bit EVT_TZ0_CBC_EN. + MCPWM_EVT_EN_EVT_TZ0_CBC_EN = 0x200000 + // Position of EVT_TZ1_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ1_CBC_EN_Pos = 0x16 + // Bit mask of EVT_TZ1_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ1_CBC_EN_Msk = 0x400000 + // Bit EVT_TZ1_CBC_EN. + MCPWM_EVT_EN_EVT_TZ1_CBC_EN = 0x400000 + // Position of EVT_TZ2_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ2_CBC_EN_Pos = 0x17 + // Bit mask of EVT_TZ2_CBC_EN field. + MCPWM_EVT_EN_EVT_TZ2_CBC_EN_Msk = 0x800000 + // Bit EVT_TZ2_CBC_EN. + MCPWM_EVT_EN_EVT_TZ2_CBC_EN = 0x800000 + // Position of EVT_TZ0_OST_EN field. + MCPWM_EVT_EN_EVT_TZ0_OST_EN_Pos = 0x18 + // Bit mask of EVT_TZ0_OST_EN field. + MCPWM_EVT_EN_EVT_TZ0_OST_EN_Msk = 0x1000000 + // Bit EVT_TZ0_OST_EN. + MCPWM_EVT_EN_EVT_TZ0_OST_EN = 0x1000000 + // Position of EVT_TZ1_OST_EN field. + MCPWM_EVT_EN_EVT_TZ1_OST_EN_Pos = 0x19 + // Bit mask of EVT_TZ1_OST_EN field. + MCPWM_EVT_EN_EVT_TZ1_OST_EN_Msk = 0x2000000 + // Bit EVT_TZ1_OST_EN. + MCPWM_EVT_EN_EVT_TZ1_OST_EN = 0x2000000 + // Position of EVT_TZ2_OST_EN field. + MCPWM_EVT_EN_EVT_TZ2_OST_EN_Pos = 0x1a + // Bit mask of EVT_TZ2_OST_EN field. + MCPWM_EVT_EN_EVT_TZ2_OST_EN_Msk = 0x4000000 + // Bit EVT_TZ2_OST_EN. + MCPWM_EVT_EN_EVT_TZ2_OST_EN = 0x4000000 + // Position of EVT_CAP0_EN field. + MCPWM_EVT_EN_EVT_CAP0_EN_Pos = 0x1b + // Bit mask of EVT_CAP0_EN field. + MCPWM_EVT_EN_EVT_CAP0_EN_Msk = 0x8000000 + // Bit EVT_CAP0_EN. + MCPWM_EVT_EN_EVT_CAP0_EN = 0x8000000 + // Position of EVT_CAP1_EN field. + MCPWM_EVT_EN_EVT_CAP1_EN_Pos = 0x1c + // Bit mask of EVT_CAP1_EN field. + MCPWM_EVT_EN_EVT_CAP1_EN_Msk = 0x10000000 + // Bit EVT_CAP1_EN. + MCPWM_EVT_EN_EVT_CAP1_EN = 0x10000000 + // Position of EVT_CAP2_EN field. + MCPWM_EVT_EN_EVT_CAP2_EN_Pos = 0x1d + // Bit mask of EVT_CAP2_EN field. + MCPWM_EVT_EN_EVT_CAP2_EN_Msk = 0x20000000 + // Bit EVT_CAP2_EN. + MCPWM_EVT_EN_EVT_CAP2_EN = 0x20000000 + + // TASK_EN: MCPWM task enable register + // Position of TASK_CMPR0_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR0_A_UP_EN_Pos = 0x0 + // Bit mask of TASK_CMPR0_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR0_A_UP_EN_Msk = 0x1 + // Bit TASK_CMPR0_A_UP_EN. + MCPWM_TASK_EN_TASK_CMPR0_A_UP_EN = 0x1 + // Position of TASK_CMPR1_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR1_A_UP_EN_Pos = 0x1 + // Bit mask of TASK_CMPR1_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR1_A_UP_EN_Msk = 0x2 + // Bit TASK_CMPR1_A_UP_EN. + MCPWM_TASK_EN_TASK_CMPR1_A_UP_EN = 0x2 + // Position of TASK_CMPR2_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR2_A_UP_EN_Pos = 0x2 + // Bit mask of TASK_CMPR2_A_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR2_A_UP_EN_Msk = 0x4 + // Bit TASK_CMPR2_A_UP_EN. + MCPWM_TASK_EN_TASK_CMPR2_A_UP_EN = 0x4 + // Position of TASK_CMPR0_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR0_B_UP_EN_Pos = 0x3 + // Bit mask of TASK_CMPR0_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR0_B_UP_EN_Msk = 0x8 + // Bit TASK_CMPR0_B_UP_EN. + MCPWM_TASK_EN_TASK_CMPR0_B_UP_EN = 0x8 + // Position of TASK_CMPR1_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR1_B_UP_EN_Pos = 0x4 + // Bit mask of TASK_CMPR1_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR1_B_UP_EN_Msk = 0x10 + // Bit TASK_CMPR1_B_UP_EN. + MCPWM_TASK_EN_TASK_CMPR1_B_UP_EN = 0x10 + // Position of TASK_CMPR2_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR2_B_UP_EN_Pos = 0x5 + // Bit mask of TASK_CMPR2_B_UP_EN field. + MCPWM_TASK_EN_TASK_CMPR2_B_UP_EN_Msk = 0x20 + // Bit TASK_CMPR2_B_UP_EN. + MCPWM_TASK_EN_TASK_CMPR2_B_UP_EN = 0x20 + // Position of TASK_GEN_STOP_EN field. + MCPWM_TASK_EN_TASK_GEN_STOP_EN_Pos = 0x6 + // Bit mask of TASK_GEN_STOP_EN field. + MCPWM_TASK_EN_TASK_GEN_STOP_EN_Msk = 0x40 + // Bit TASK_GEN_STOP_EN. + MCPWM_TASK_EN_TASK_GEN_STOP_EN = 0x40 + // Position of TASK_TIMER0_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER0_SYNC_EN_Pos = 0x7 + // Bit mask of TASK_TIMER0_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER0_SYNC_EN_Msk = 0x80 + // Bit TASK_TIMER0_SYNC_EN. + MCPWM_TASK_EN_TASK_TIMER0_SYNC_EN = 0x80 + // Position of TASK_TIMER1_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER1_SYNC_EN_Pos = 0x8 + // Bit mask of TASK_TIMER1_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER1_SYNC_EN_Msk = 0x100 + // Bit TASK_TIMER1_SYNC_EN. + MCPWM_TASK_EN_TASK_TIMER1_SYNC_EN = 0x100 + // Position of TASK_TIMER2_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER2_SYNC_EN_Pos = 0x9 + // Bit mask of TASK_TIMER2_SYNC_EN field. + MCPWM_TASK_EN_TASK_TIMER2_SYNC_EN_Msk = 0x200 + // Bit TASK_TIMER2_SYNC_EN. + MCPWM_TASK_EN_TASK_TIMER2_SYNC_EN = 0x200 + // Position of TASK_TIMER0_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER0_PERIOD_UP_EN_Pos = 0xa + // Bit mask of TASK_TIMER0_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER0_PERIOD_UP_EN_Msk = 0x400 + // Bit TASK_TIMER0_PERIOD_UP_EN. + MCPWM_TASK_EN_TASK_TIMER0_PERIOD_UP_EN = 0x400 + // Position of TASK_TIMER1_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER1_PERIOD_UP_EN_Pos = 0xb + // Bit mask of TASK_TIMER1_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER1_PERIOD_UP_EN_Msk = 0x800 + // Bit TASK_TIMER1_PERIOD_UP_EN. + MCPWM_TASK_EN_TASK_TIMER1_PERIOD_UP_EN = 0x800 + // Position of TASK_TIMER2_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER2_PERIOD_UP_EN_Pos = 0xc + // Bit mask of TASK_TIMER2_PERIOD_UP_EN field. + MCPWM_TASK_EN_TASK_TIMER2_PERIOD_UP_EN_Msk = 0x1000 + // Bit TASK_TIMER2_PERIOD_UP_EN. + MCPWM_TASK_EN_TASK_TIMER2_PERIOD_UP_EN = 0x1000 + // Position of TASK_TZ0_OST_EN field. + MCPWM_TASK_EN_TASK_TZ0_OST_EN_Pos = 0xd + // Bit mask of TASK_TZ0_OST_EN field. + MCPWM_TASK_EN_TASK_TZ0_OST_EN_Msk = 0x2000 + // Bit TASK_TZ0_OST_EN. + MCPWM_TASK_EN_TASK_TZ0_OST_EN = 0x2000 + // Position of TASK_TZ1_OST_EN field. + MCPWM_TASK_EN_TASK_TZ1_OST_EN_Pos = 0xe + // Bit mask of TASK_TZ1_OST_EN field. + MCPWM_TASK_EN_TASK_TZ1_OST_EN_Msk = 0x4000 + // Bit TASK_TZ1_OST_EN. + MCPWM_TASK_EN_TASK_TZ1_OST_EN = 0x4000 + // Position of TASK_TZ2_OST_EN field. + MCPWM_TASK_EN_TASK_TZ2_OST_EN_Pos = 0xf + // Bit mask of TASK_TZ2_OST_EN field. + MCPWM_TASK_EN_TASK_TZ2_OST_EN_Msk = 0x8000 + // Bit TASK_TZ2_OST_EN. + MCPWM_TASK_EN_TASK_TZ2_OST_EN = 0x8000 + // Position of TASK_CLR0_OST_EN field. + MCPWM_TASK_EN_TASK_CLR0_OST_EN_Pos = 0x10 + // Bit mask of TASK_CLR0_OST_EN field. + MCPWM_TASK_EN_TASK_CLR0_OST_EN_Msk = 0x10000 + // Bit TASK_CLR0_OST_EN. + MCPWM_TASK_EN_TASK_CLR0_OST_EN = 0x10000 + // Position of TASK_CLR1_OST_EN field. + MCPWM_TASK_EN_TASK_CLR1_OST_EN_Pos = 0x11 + // Bit mask of TASK_CLR1_OST_EN field. + MCPWM_TASK_EN_TASK_CLR1_OST_EN_Msk = 0x20000 + // Bit TASK_CLR1_OST_EN. + MCPWM_TASK_EN_TASK_CLR1_OST_EN = 0x20000 + // Position of TASK_CLR2_OST_EN field. + MCPWM_TASK_EN_TASK_CLR2_OST_EN_Pos = 0x12 + // Bit mask of TASK_CLR2_OST_EN field. + MCPWM_TASK_EN_TASK_CLR2_OST_EN_Msk = 0x40000 + // Bit TASK_CLR2_OST_EN. + MCPWM_TASK_EN_TASK_CLR2_OST_EN = 0x40000 + // Position of TASK_CAP0_EN field. + MCPWM_TASK_EN_TASK_CAP0_EN_Pos = 0x13 + // Bit mask of TASK_CAP0_EN field. + MCPWM_TASK_EN_TASK_CAP0_EN_Msk = 0x80000 + // Bit TASK_CAP0_EN. + MCPWM_TASK_EN_TASK_CAP0_EN = 0x80000 + // Position of TASK_CAP1_EN field. + MCPWM_TASK_EN_TASK_CAP1_EN_Pos = 0x14 + // Bit mask of TASK_CAP1_EN field. + MCPWM_TASK_EN_TASK_CAP1_EN_Msk = 0x100000 + // Bit TASK_CAP1_EN. + MCPWM_TASK_EN_TASK_CAP1_EN = 0x100000 + // Position of TASK_CAP2_EN field. + MCPWM_TASK_EN_TASK_CAP2_EN_Pos = 0x15 + // Bit mask of TASK_CAP2_EN field. + MCPWM_TASK_EN_TASK_CAP2_EN_Msk = 0x200000 + // Bit TASK_CAP2_EN. + MCPWM_TASK_EN_TASK_CAP2_EN = 0x200000 + + // CLK: MCPWM APB configuration register + // Position of EN field. + MCPWM_CLK_EN_Pos = 0x0 + // Bit mask of EN field. + MCPWM_CLK_EN_Msk = 0x1 + // Bit EN. + MCPWM_CLK_EN = 0x1 + + // VERSION: Version register. + // Position of DATE field. + MCPWM_VERSION_DATE_Pos = 0x0 + // Bit mask of DATE field. + MCPWM_VERSION_DATE_Msk = 0xfffffff +) + +// Constants for MEM_MONITOR: MEM_MONITOR Peripheral +const ( + // LOG_SETTING: log config regsiter + // Position of LOG_ENA field. + MEM_MONITOR_LOG_SETTING_LOG_ENA_Pos = 0x0 + // Bit mask of LOG_ENA field. + MEM_MONITOR_LOG_SETTING_LOG_ENA_Msk = 0x7 + // Position of LOG_MODE field. + MEM_MONITOR_LOG_SETTING_LOG_MODE_Pos = 0x3 + // Bit mask of LOG_MODE field. + MEM_MONITOR_LOG_SETTING_LOG_MODE_Msk = 0x78 + // Position of LOG_MEM_LOOP_ENABLE field. + MEM_MONITOR_LOG_SETTING_LOG_MEM_LOOP_ENABLE_Pos = 0x7 + // Bit mask of LOG_MEM_LOOP_ENABLE field. + MEM_MONITOR_LOG_SETTING_LOG_MEM_LOOP_ENABLE_Msk = 0x80 + // Bit LOG_MEM_LOOP_ENABLE. + MEM_MONITOR_LOG_SETTING_LOG_MEM_LOOP_ENABLE = 0x80 + + // LOG_CHECK_DATA: check data regsiter + // Position of LOG_CHECK_DATA field. + MEM_MONITOR_LOG_CHECK_DATA_LOG_CHECK_DATA_Pos = 0x0 + // Bit mask of LOG_CHECK_DATA field. + MEM_MONITOR_LOG_CHECK_DATA_LOG_CHECK_DATA_Msk = 0xffffffff + + // LOG_DATA_MASK: check data mask register + // Position of LOG_DATA_MASK field. + MEM_MONITOR_LOG_DATA_MASK_LOG_DATA_MASK_Pos = 0x0 + // Bit mask of LOG_DATA_MASK field. + MEM_MONITOR_LOG_DATA_MASK_LOG_DATA_MASK_Msk = 0xf + + // LOG_MIN: log boundary regsiter + // Position of LOG_MIN field. + MEM_MONITOR_LOG_MIN_LOG_MIN_Pos = 0x0 + // Bit mask of LOG_MIN field. + MEM_MONITOR_LOG_MIN_LOG_MIN_Msk = 0xffffffff + + // LOG_MAX: log boundary regsiter + // Position of LOG_MAX field. + MEM_MONITOR_LOG_MAX_LOG_MAX_Pos = 0x0 + // Bit mask of LOG_MAX field. + MEM_MONITOR_LOG_MAX_LOG_MAX_Msk = 0xffffffff + + // LOG_MEM_START: log message store range register + // Position of LOG_MEM_START field. + MEM_MONITOR_LOG_MEM_START_LOG_MEM_START_Pos = 0x0 + // Bit mask of LOG_MEM_START field. + MEM_MONITOR_LOG_MEM_START_LOG_MEM_START_Msk = 0xffffffff + + // LOG_MEM_END: log message store range register + // Position of LOG_MEM_END field. + MEM_MONITOR_LOG_MEM_END_LOG_MEM_END_Pos = 0x0 + // Bit mask of LOG_MEM_END field. + MEM_MONITOR_LOG_MEM_END_LOG_MEM_END_Msk = 0xffffffff + + // LOG_MEM_CURRENT_ADDR: current writing address. + // Position of LOG_MEM_CURRENT_ADDR field. + MEM_MONITOR_LOG_MEM_CURRENT_ADDR_LOG_MEM_CURRENT_ADDR_Pos = 0x0 + // Bit mask of LOG_MEM_CURRENT_ADDR field. + MEM_MONITOR_LOG_MEM_CURRENT_ADDR_LOG_MEM_CURRENT_ADDR_Msk = 0xffffffff + + // LOG_MEM_ADDR_UPDATE: writing address update + // Position of LOG_MEM_ADDR_UPDATE field. + MEM_MONITOR_LOG_MEM_ADDR_UPDATE_LOG_MEM_ADDR_UPDATE_Pos = 0x0 + // Bit mask of LOG_MEM_ADDR_UPDATE field. + MEM_MONITOR_LOG_MEM_ADDR_UPDATE_LOG_MEM_ADDR_UPDATE_Msk = 0x1 + // Bit LOG_MEM_ADDR_UPDATE. + MEM_MONITOR_LOG_MEM_ADDR_UPDATE_LOG_MEM_ADDR_UPDATE = 0x1 + + // LOG_MEM_FULL_FLAG: full flag status register + // Position of LOG_MEM_FULL_FLAG field. + MEM_MONITOR_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG_Pos = 0x0 + // Bit mask of LOG_MEM_FULL_FLAG field. + MEM_MONITOR_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG_Msk = 0x1 + // Bit LOG_MEM_FULL_FLAG. + MEM_MONITOR_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG = 0x1 + // Position of CLR_LOG_MEM_FULL_FLAG field. + MEM_MONITOR_LOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG_Pos = 0x1 + // Bit mask of CLR_LOG_MEM_FULL_FLAG field. + MEM_MONITOR_LOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG_Msk = 0x2 + // Bit CLR_LOG_MEM_FULL_FLAG. + MEM_MONITOR_LOG_MEM_FULL_FLAG_CLR_LOG_MEM_FULL_FLAG = 0x2 + + // CLOCK_GATE: clock gate force on register + // Position of CLK_EN field. + MEM_MONITOR_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + MEM_MONITOR_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + MEM_MONITOR_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: version register + // Position of DATE field. + MEM_MONITOR_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + MEM_MONITOR_DATE_DATE_Msk = 0xfffffff +) + +// Constants for MODEM_LPCON: MODEM_LPCON Peripheral +const ( + // TEST_CONF + // Position of CLK_EN field. + MODEM_LPCON_TEST_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + MODEM_LPCON_TEST_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + MODEM_LPCON_TEST_CONF_CLK_EN = 0x1 + + // COEX_LP_CLK_CONF + // Position of CLK_COEX_LP_SEL_OSC_SLOW field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW_Pos = 0x0 + // Bit mask of CLK_COEX_LP_SEL_OSC_SLOW field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW_Msk = 0x1 + // Bit CLK_COEX_LP_SEL_OSC_SLOW. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_SLOW = 0x1 + // Position of CLK_COEX_LP_SEL_OSC_FAST field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST_Pos = 0x1 + // Bit mask of CLK_COEX_LP_SEL_OSC_FAST field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST_Msk = 0x2 + // Bit CLK_COEX_LP_SEL_OSC_FAST. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_OSC_FAST = 0x2 + // Position of CLK_COEX_LP_SEL_XTAL field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL_Pos = 0x2 + // Bit mask of CLK_COEX_LP_SEL_XTAL field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL_Msk = 0x4 + // Bit CLK_COEX_LP_SEL_XTAL. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL = 0x4 + // Position of CLK_COEX_LP_SEL_XTAL32K field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K_Pos = 0x3 + // Bit mask of CLK_COEX_LP_SEL_XTAL32K field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K_Msk = 0x8 + // Bit CLK_COEX_LP_SEL_XTAL32K. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_SEL_XTAL32K = 0x8 + // Position of CLK_COEX_LP_DIV_NUM field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_DIV_NUM_Pos = 0x4 + // Bit mask of CLK_COEX_LP_DIV_NUM field. + MODEM_LPCON_COEX_LP_CLK_CONF_CLK_COEX_LP_DIV_NUM_Msk = 0xfff0 + + // CLK_CONF + // Position of CLK_COEX_EN field. + MODEM_LPCON_CLK_CONF_CLK_COEX_EN_Pos = 0x1 + // Bit mask of CLK_COEX_EN field. + MODEM_LPCON_CLK_CONF_CLK_COEX_EN_Msk = 0x2 + // Bit CLK_COEX_EN. + MODEM_LPCON_CLK_CONF_CLK_COEX_EN = 0x2 + // Position of CLK_I2C_MST_EN field. + MODEM_LPCON_CLK_CONF_CLK_I2C_MST_EN_Pos = 0x2 + // Bit mask of CLK_I2C_MST_EN field. + MODEM_LPCON_CLK_CONF_CLK_I2C_MST_EN_Msk = 0x4 + // Bit CLK_I2C_MST_EN. + MODEM_LPCON_CLK_CONF_CLK_I2C_MST_EN = 0x4 + // Position of CLK_FE_MEM_EN field. + MODEM_LPCON_CLK_CONF_CLK_FE_MEM_EN_Pos = 0x5 + // Bit mask of CLK_FE_MEM_EN field. + MODEM_LPCON_CLK_CONF_CLK_FE_MEM_EN_Msk = 0x20 + // Bit CLK_FE_MEM_EN. + MODEM_LPCON_CLK_CONF_CLK_FE_MEM_EN = 0x20 + + // CLK_CONF_FORCE_ON + // Position of CLK_COEX_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_COEX_FO_Pos = 0x1 + // Bit mask of CLK_COEX_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_COEX_FO_Msk = 0x2 + // Bit CLK_COEX_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_COEX_FO = 0x2 + // Position of CLK_I2C_MST_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_I2C_MST_FO_Pos = 0x2 + // Bit mask of CLK_I2C_MST_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_I2C_MST_FO_Msk = 0x4 + // Bit CLK_I2C_MST_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_I2C_MST_FO = 0x4 + // Position of CLK_FE_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_FE_MEM_FO_Pos = 0x5 + // Bit mask of CLK_FE_MEM_FO field. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_FE_MEM_FO_Msk = 0x20 + // Bit CLK_FE_MEM_FO. + MODEM_LPCON_CLK_CONF_FORCE_ON_CLK_FE_MEM_FO = 0x20 + + // TICK_CONF + // Position of PWR_TICK_TARGET field. + MODEM_LPCON_TICK_CONF_PWR_TICK_TARGET_Pos = 0x0 + // Bit mask of PWR_TICK_TARGET field. + MODEM_LPCON_TICK_CONF_PWR_TICK_TARGET_Msk = 0x3f + + // RST_CONF + // Position of RST_COEX field. + MODEM_LPCON_RST_CONF_RST_COEX_Pos = 0x1 + // Bit mask of RST_COEX field. + MODEM_LPCON_RST_CONF_RST_COEX_Msk = 0x2 + // Bit RST_COEX. + MODEM_LPCON_RST_CONF_RST_COEX = 0x2 + // Position of RST_I2C_MST field. + MODEM_LPCON_RST_CONF_RST_I2C_MST_Pos = 0x2 + // Bit mask of RST_I2C_MST field. + MODEM_LPCON_RST_CONF_RST_I2C_MST_Msk = 0x4 + // Bit RST_I2C_MST. + MODEM_LPCON_RST_CONF_RST_I2C_MST = 0x4 + + // MEM_CONF + // Position of AGC_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of AGC_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PU_Msk = 0x4 + // Bit AGC_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PU = 0x4 + // Position of AGC_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of AGC_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PD_Msk = 0x8 + // Bit AGC_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_AGC_MEM_FORCE_PD = 0x8 + // Position of PBUS_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of PBUS_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PU_Msk = 0x10 + // Bit PBUS_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PU = 0x10 + // Position of PBUS_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PD_Pos = 0x5 + // Bit mask of PBUS_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PD_Msk = 0x20 + // Bit PBUS_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_PBUS_MEM_FORCE_PD = 0x20 + // Position of I2C_MST_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PU_Pos = 0x8 + // Bit mask of I2C_MST_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PU_Msk = 0x100 + // Bit I2C_MST_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PU = 0x100 + // Position of I2C_MST_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PD_Pos = 0x9 + // Bit mask of I2C_MST_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PD_Msk = 0x200 + // Bit I2C_MST_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_I2C_MST_MEM_FORCE_PD = 0x200 + // Position of CHAN_FREQ_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PU_Pos = 0xa + // Bit mask of CHAN_FREQ_MEM_FORCE_PU field. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PU_Msk = 0x400 + // Bit CHAN_FREQ_MEM_FORCE_PU. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PU = 0x400 + // Position of CHAN_FREQ_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PD_Pos = 0xb + // Bit mask of CHAN_FREQ_MEM_FORCE_PD field. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PD_Msk = 0x800 + // Bit CHAN_FREQ_MEM_FORCE_PD. + MODEM_LPCON_MEM_CONF_CHAN_FREQ_MEM_FORCE_PD = 0x800 + // Position of MODEM_PWR_MEM_WP field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_WP_Pos = 0xc + // Bit mask of MODEM_PWR_MEM_WP field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_WP_Msk = 0x7000 + // Position of MODEM_PWR_MEM_WA field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_WA_Pos = 0xf + // Bit mask of MODEM_PWR_MEM_WA field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_WA_Msk = 0x38000 + // Position of MODEM_PWR_MEM_RA field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_RA_Pos = 0x12 + // Bit mask of MODEM_PWR_MEM_RA field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_RA_Msk = 0xc0000 + // Position of MODEM_PWR_MEM_RM field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_RM_Pos = 0x14 + // Bit mask of MODEM_PWR_MEM_RM field. + MODEM_LPCON_MEM_CONF_MODEM_PWR_MEM_RM_Msk = 0xf00000 + + // DATE + // Position of DATE field. + MODEM_LPCON_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + MODEM_LPCON_DATE_DATE_Msk = 0xfffffff +) + +// Constants for MODEM_SYSCON: MODEM_SYSCON Peripheral +const ( + // TEST_CONF + // Position of CLK_EN field. + MODEM_SYSCON_TEST_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + MODEM_SYSCON_TEST_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + MODEM_SYSCON_TEST_CONF_CLK_EN = 0x1 + + // CLK_CONF + // Position of CLK_ETM_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ETM_EN_Pos = 0x15 + // Bit mask of CLK_ETM_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ETM_EN_Msk = 0x200000 + // Bit CLK_ETM_EN. + MODEM_SYSCON_CLK_CONF_CLK_ETM_EN = 0x200000 + // Position of CLK_ZB_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ZB_APB_EN_Pos = 0x16 + // Bit mask of CLK_ZB_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ZB_APB_EN_Msk = 0x400000 + // Bit CLK_ZB_APB_EN. + MODEM_SYSCON_CLK_CONF_CLK_ZB_APB_EN = 0x400000 + // Position of CLK_ZB_MAC_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ZB_MAC_EN_Pos = 0x17 + // Bit mask of CLK_ZB_MAC_EN field. + MODEM_SYSCON_CLK_CONF_CLK_ZB_MAC_EN_Msk = 0x800000 + // Bit CLK_ZB_MAC_EN. + MODEM_SYSCON_CLK_CONF_CLK_ZB_MAC_EN = 0x800000 + // Position of CLK_MODEM_SEC_ECB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_ECB_EN_Pos = 0x18 + // Bit mask of CLK_MODEM_SEC_ECB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_ECB_EN_Msk = 0x1000000 + // Bit CLK_MODEM_SEC_ECB_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_ECB_EN = 0x1000000 + // Position of CLK_MODEM_SEC_CCM_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_CCM_EN_Pos = 0x19 + // Bit mask of CLK_MODEM_SEC_CCM_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_CCM_EN_Msk = 0x2000000 + // Bit CLK_MODEM_SEC_CCM_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_CCM_EN = 0x2000000 + // Position of CLK_MODEM_SEC_BAH_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_BAH_EN_Pos = 0x1a + // Bit mask of CLK_MODEM_SEC_BAH_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_BAH_EN_Msk = 0x4000000 + // Bit CLK_MODEM_SEC_BAH_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_BAH_EN = 0x4000000 + // Position of CLK_MODEM_SEC_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_APB_EN_Pos = 0x1b + // Bit mask of CLK_MODEM_SEC_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_APB_EN_Msk = 0x8000000 + // Bit CLK_MODEM_SEC_APB_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_APB_EN = 0x8000000 + // Position of CLK_MODEM_SEC_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_EN_Pos = 0x1c + // Bit mask of CLK_MODEM_SEC_EN field. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_EN_Msk = 0x10000000 + // Bit CLK_MODEM_SEC_EN. + MODEM_SYSCON_CLK_CONF_CLK_MODEM_SEC_EN = 0x10000000 + // Position of CLK_BLE_TIMER_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_BLE_TIMER_APB_EN_Pos = 0x1d + // Bit mask of CLK_BLE_TIMER_APB_EN field. + MODEM_SYSCON_CLK_CONF_CLK_BLE_TIMER_APB_EN_Msk = 0x20000000 + // Bit CLK_BLE_TIMER_APB_EN. + MODEM_SYSCON_CLK_CONF_CLK_BLE_TIMER_APB_EN = 0x20000000 + // Position of CLK_BLE_TIMER_EN field. + MODEM_SYSCON_CLK_CONF_CLK_BLE_TIMER_EN_Pos = 0x1e + // Bit mask of CLK_BLE_TIMER_EN field. + MODEM_SYSCON_CLK_CONF_CLK_BLE_TIMER_EN_Msk = 0x40000000 + // Bit CLK_BLE_TIMER_EN. + MODEM_SYSCON_CLK_CONF_CLK_BLE_TIMER_EN = 0x40000000 + // Position of CLK_DATA_DUMP_EN field. + MODEM_SYSCON_CLK_CONF_CLK_DATA_DUMP_EN_Pos = 0x1f + // Bit mask of CLK_DATA_DUMP_EN field. + MODEM_SYSCON_CLK_CONF_CLK_DATA_DUMP_EN_Msk = 0x80000000 + // Bit CLK_DATA_DUMP_EN. + MODEM_SYSCON_CLK_CONF_CLK_DATA_DUMP_EN = 0x80000000 + + // CLK_CONF_FORCE_ON + // Position of CLK_ETM_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ETM_FO_Pos = 0x16 + // Bit mask of CLK_ETM_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ETM_FO_Msk = 0x400000 + // Bit CLK_ETM_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ETM_FO = 0x400000 + // Position of CLK_ZB_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ZB_FO_Pos = 0x18 + // Bit mask of CLK_ZB_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ZB_FO_Msk = 0x1000000 + // Bit CLK_ZB_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_ZB_FO = 0x1000000 + // Position of CLK_MODEM_SEC_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO_Pos = 0x1d + // Bit mask of CLK_MODEM_SEC_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO_Msk = 0x20000000 + // Bit CLK_MODEM_SEC_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_MODEM_SEC_FO = 0x20000000 + // Position of CLK_BLE_TIMER_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO_Pos = 0x1e + // Bit mask of CLK_BLE_TIMER_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO_Msk = 0x40000000 + // Bit CLK_BLE_TIMER_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_BLE_TIMER_FO = 0x40000000 + // Position of CLK_DATA_DUMP_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO_Pos = 0x1f + // Bit mask of CLK_DATA_DUMP_FO field. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO_Msk = 0x80000000 + // Bit CLK_DATA_DUMP_FO. + MODEM_SYSCON_CLK_CONF_FORCE_ON_CLK_DATA_DUMP_FO = 0x80000000 + + // MODEM_RST_CONF + // Position of RST_FE field. + MODEM_SYSCON_MODEM_RST_CONF_RST_FE_Pos = 0xe + // Bit mask of RST_FE field. + MODEM_SYSCON_MODEM_RST_CONF_RST_FE_Msk = 0x4000 + // Bit RST_FE. + MODEM_SYSCON_MODEM_RST_CONF_RST_FE = 0x4000 + // Position of RST_BTMAC_APB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_APB_Pos = 0xf + // Bit mask of RST_BTMAC_APB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_APB_Msk = 0x8000 + // Bit RST_BTMAC_APB. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_APB = 0x8000 + // Position of RST_BTMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_Pos = 0x10 + // Bit mask of RST_BTMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC_Msk = 0x10000 + // Bit RST_BTMAC. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTMAC = 0x10000 + // Position of RST_BTBB_APB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_APB_Pos = 0x11 + // Bit mask of RST_BTBB_APB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_APB_Msk = 0x20000 + // Bit RST_BTBB_APB. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_APB = 0x20000 + // Position of RST_BTBB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_Pos = 0x12 + // Bit mask of RST_BTBB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB_Msk = 0x40000 + // Bit RST_BTBB. + MODEM_SYSCON_MODEM_RST_CONF_RST_BTBB = 0x40000 + // Position of RST_ETM field. + MODEM_SYSCON_MODEM_RST_CONF_RST_ETM_Pos = 0x16 + // Bit mask of RST_ETM field. + MODEM_SYSCON_MODEM_RST_CONF_RST_ETM_Msk = 0x400000 + // Bit RST_ETM. + MODEM_SYSCON_MODEM_RST_CONF_RST_ETM = 0x400000 + // Position of RST_ZBMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_ZBMAC_Pos = 0x18 + // Bit mask of RST_ZBMAC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_ZBMAC_Msk = 0x1000000 + // Bit RST_ZBMAC. + MODEM_SYSCON_MODEM_RST_CONF_RST_ZBMAC = 0x1000000 + // Position of RST_MODEM_ECB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_ECB_Pos = 0x19 + // Bit mask of RST_MODEM_ECB field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_ECB_Msk = 0x2000000 + // Bit RST_MODEM_ECB. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_ECB = 0x2000000 + // Position of RST_MODEM_CCM field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_CCM_Pos = 0x1a + // Bit mask of RST_MODEM_CCM field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_CCM_Msk = 0x4000000 + // Bit RST_MODEM_CCM. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_CCM = 0x4000000 + // Position of RST_MODEM_BAH field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_BAH_Pos = 0x1b + // Bit mask of RST_MODEM_BAH field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_BAH_Msk = 0x8000000 + // Bit RST_MODEM_BAH. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_BAH = 0x8000000 + // Position of RST_MODEM_SEC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_SEC_Pos = 0x1d + // Bit mask of RST_MODEM_SEC field. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_SEC_Msk = 0x20000000 + // Bit RST_MODEM_SEC. + MODEM_SYSCON_MODEM_RST_CONF_RST_MODEM_SEC = 0x20000000 + // Position of RST_BLE_TIMER field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BLE_TIMER_Pos = 0x1e + // Bit mask of RST_BLE_TIMER field. + MODEM_SYSCON_MODEM_RST_CONF_RST_BLE_TIMER_Msk = 0x40000000 + // Bit RST_BLE_TIMER. + MODEM_SYSCON_MODEM_RST_CONF_RST_BLE_TIMER = 0x40000000 + // Position of RST_DATA_DUMP field. + MODEM_SYSCON_MODEM_RST_CONF_RST_DATA_DUMP_Pos = 0x1f + // Bit mask of RST_DATA_DUMP field. + MODEM_SYSCON_MODEM_RST_CONF_RST_DATA_DUMP_Msk = 0x80000000 + // Bit RST_DATA_DUMP. + MODEM_SYSCON_MODEM_RST_CONF_RST_DATA_DUMP = 0x80000000 + + // CLK_CONF1 + // Position of CLK_FE_16M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_16M_EN_Pos = 0xc + // Bit mask of CLK_FE_16M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_16M_EN_Msk = 0x1000 + // Bit CLK_FE_16M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_16M_EN = 0x1000 + // Position of CLK_FE_32M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_32M_EN_Pos = 0xd + // Bit mask of CLK_FE_32M_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_32M_EN_Msk = 0x2000 + // Bit CLK_FE_32M_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_32M_EN = 0x2000 + // Position of CLK_FE_SDM_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_SDM_EN_Pos = 0xe + // Bit mask of CLK_FE_SDM_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_SDM_EN_Msk = 0x4000 + // Bit CLK_FE_SDM_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_SDM_EN = 0x4000 + // Position of CLK_FE_ADC_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ADC_EN_Pos = 0xf + // Bit mask of CLK_FE_ADC_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ADC_EN_Msk = 0x8000 + // Bit CLK_FE_ADC_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_ADC_EN = 0x8000 + // Position of CLK_FE_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_APB_EN_Pos = 0x10 + // Bit mask of CLK_FE_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_FE_APB_EN_Msk = 0x10000 + // Bit CLK_FE_APB_EN. + MODEM_SYSCON_CLK_CONF1_CLK_FE_APB_EN = 0x10000 + // Position of CLK_BT_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_BT_APB_EN_Pos = 0x11 + // Bit mask of CLK_BT_APB_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_BT_APB_EN_Msk = 0x20000 + // Bit CLK_BT_APB_EN. + MODEM_SYSCON_CLK_CONF1_CLK_BT_APB_EN = 0x20000 + // Position of CLK_BT_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_BT_EN_Pos = 0x12 + // Bit mask of CLK_BT_EN field. + MODEM_SYSCON_CLK_CONF1_CLK_BT_EN_Msk = 0x40000 + // Bit CLK_BT_EN. + MODEM_SYSCON_CLK_CONF1_CLK_BT_EN = 0x40000 + + // CLK_CONF1_FORCE_ON + // Position of CLK_FE_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_FO_Pos = 0x10 + // Bit mask of CLK_FE_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_FO_Msk = 0x10000 + // Bit CLK_FE_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_FE_FO = 0x10000 + // Position of CLK_BT_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_BT_FO_Pos = 0x12 + // Bit mask of CLK_BT_FO field. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_BT_FO_Msk = 0x40000 + // Bit CLK_BT_FO. + MODEM_SYSCON_CLK_CONF1_FORCE_ON_CLK_BT_FO = 0x40000 + + // MEM_CONF + // Position of MODEM_MEM_WP field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_WP_Pos = 0x0 + // Bit mask of MODEM_MEM_WP field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_WP_Msk = 0x7 + // Position of MODEM_MEM_WA field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_WA_Pos = 0x3 + // Bit mask of MODEM_MEM_WA field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_WA_Msk = 0x38 + // Position of MODEM_MEM_RA field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_RA_Pos = 0x6 + // Bit mask of MODEM_MEM_RA field. + MODEM_SYSCON_MEM_CONF_MODEM_MEM_RA_Msk = 0xc0 + + // DATE + // Position of DATE field. + MODEM_SYSCON_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + MODEM_SYSCON_DATE_DATE_Msk = 0xfffffff +) + +// Constants for OTP_DEBUG: OTP_DEBUG Peripheral +const ( + // WR_DIS: Otp debuger block0 data register1. + // Position of BLOCK0_WR_DIS field. + OTP_DEBUG_WR_DIS_BLOCK0_WR_DIS_Pos = 0x0 + // Bit mask of BLOCK0_WR_DIS field. + OTP_DEBUG_WR_DIS_BLOCK0_WR_DIS_Msk = 0xffffffff + + // BLK0_BACKUP1_W1: Otp debuger block0 data register2. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W1 field. + OTP_DEBUG_BLK0_BACKUP1_W1_OTP_BEBUG_BLOCK0_BACKUP1_W1_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W1 field. + OTP_DEBUG_BLK0_BACKUP1_W1_OTP_BEBUG_BLOCK0_BACKUP1_W1_Msk = 0xffffffff + + // BLK0_BACKUP1_W2: Otp debuger block0 data register3. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W2 field. + OTP_DEBUG_BLK0_BACKUP1_W2_OTP_BEBUG_BLOCK0_BACKUP1_W2_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W2 field. + OTP_DEBUG_BLK0_BACKUP1_W2_OTP_BEBUG_BLOCK0_BACKUP1_W2_Msk = 0xffffffff + + // BLK0_BACKUP1_W3: Otp debuger block0 data register4. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W3 field. + OTP_DEBUG_BLK0_BACKUP1_W3_OTP_BEBUG_BLOCK0_BACKUP1_W3_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W3 field. + OTP_DEBUG_BLK0_BACKUP1_W3_OTP_BEBUG_BLOCK0_BACKUP1_W3_Msk = 0xffffffff + + // BLK0_BACKUP1_W4: Otp debuger block0 data register5. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W4 field. + OTP_DEBUG_BLK0_BACKUP1_W4_OTP_BEBUG_BLOCK0_BACKUP1_W4_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W4 field. + OTP_DEBUG_BLK0_BACKUP1_W4_OTP_BEBUG_BLOCK0_BACKUP1_W4_Msk = 0xffffffff + + // BLK0_BACKUP1_W5: Otp debuger block0 data register6. + // Position of OTP_BEBUG_BLOCK0_BACKUP1_W5 field. + OTP_DEBUG_BLK0_BACKUP1_W5_OTP_BEBUG_BLOCK0_BACKUP1_W5_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP1_W5 field. + OTP_DEBUG_BLK0_BACKUP1_W5_OTP_BEBUG_BLOCK0_BACKUP1_W5_Msk = 0xffffffff + + // BLK0_BACKUP2_W1: Otp debuger block0 data register7. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W1 field. + OTP_DEBUG_BLK0_BACKUP2_W1_OTP_BEBUG_BLOCK0_BACKUP2_W1_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W1 field. + OTP_DEBUG_BLK0_BACKUP2_W1_OTP_BEBUG_BLOCK0_BACKUP2_W1_Msk = 0xffffffff + + // BLK0_BACKUP2_W2: Otp debuger block0 data register8. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W2 field. + OTP_DEBUG_BLK0_BACKUP2_W2_OTP_BEBUG_BLOCK0_BACKUP2_W2_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W2 field. + OTP_DEBUG_BLK0_BACKUP2_W2_OTP_BEBUG_BLOCK0_BACKUP2_W2_Msk = 0xffffffff + + // BLK0_BACKUP2_W3: Otp debuger block0 data register9. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W3 field. + OTP_DEBUG_BLK0_BACKUP2_W3_OTP_BEBUG_BLOCK0_BACKUP2_W3_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W3 field. + OTP_DEBUG_BLK0_BACKUP2_W3_OTP_BEBUG_BLOCK0_BACKUP2_W3_Msk = 0xffffffff + + // BLK0_BACKUP2_W4: Otp debuger block0 data register10. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W4 field. + OTP_DEBUG_BLK0_BACKUP2_W4_OTP_BEBUG_BLOCK0_BACKUP2_W4_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W4 field. + OTP_DEBUG_BLK0_BACKUP2_W4_OTP_BEBUG_BLOCK0_BACKUP2_W4_Msk = 0xffffffff + + // BLK0_BACKUP2_W5: Otp debuger block0 data register11. + // Position of OTP_BEBUG_BLOCK0_BACKUP2_W5 field. + OTP_DEBUG_BLK0_BACKUP2_W5_OTP_BEBUG_BLOCK0_BACKUP2_W5_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP2_W5 field. + OTP_DEBUG_BLK0_BACKUP2_W5_OTP_BEBUG_BLOCK0_BACKUP2_W5_Msk = 0xffffffff + + // BLK0_BACKUP3_W1: Otp debuger block0 data register12. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W1 field. + OTP_DEBUG_BLK0_BACKUP3_W1_OTP_BEBUG_BLOCK0_BACKUP3_W1_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W1 field. + OTP_DEBUG_BLK0_BACKUP3_W1_OTP_BEBUG_BLOCK0_BACKUP3_W1_Msk = 0xffffffff + + // BLK0_BACKUP3_W2: Otp debuger block0 data register13. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W2 field. + OTP_DEBUG_BLK0_BACKUP3_W2_OTP_BEBUG_BLOCK0_BACKUP3_W2_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W2 field. + OTP_DEBUG_BLK0_BACKUP3_W2_OTP_BEBUG_BLOCK0_BACKUP3_W2_Msk = 0xffffffff + + // BLK0_BACKUP3_W3: Otp debuger block0 data register14. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W3 field. + OTP_DEBUG_BLK0_BACKUP3_W3_OTP_BEBUG_BLOCK0_BACKUP3_W3_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W3 field. + OTP_DEBUG_BLK0_BACKUP3_W3_OTP_BEBUG_BLOCK0_BACKUP3_W3_Msk = 0xffffffff + + // BLK0_BACKUP3_W4: Otp debuger block0 data register15. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W4 field. + OTP_DEBUG_BLK0_BACKUP3_W4_OTP_BEBUG_BLOCK0_BACKUP3_W4_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W4 field. + OTP_DEBUG_BLK0_BACKUP3_W4_OTP_BEBUG_BLOCK0_BACKUP3_W4_Msk = 0xffffffff + + // BLK0_BACKUP3_W5: Otp debuger block0 data register16. + // Position of OTP_BEBUG_BLOCK0_BACKUP3_W5 field. + OTP_DEBUG_BLK0_BACKUP3_W5_OTP_BEBUG_BLOCK0_BACKUP3_W5_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP3_W5 field. + OTP_DEBUG_BLK0_BACKUP3_W5_OTP_BEBUG_BLOCK0_BACKUP3_W5_Msk = 0xffffffff + + // BLK0_BACKUP4_W1: Otp debuger block0 data register17. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W1 field. + OTP_DEBUG_BLK0_BACKUP4_W1_OTP_BEBUG_BLOCK0_BACKUP4_W1_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W1 field. + OTP_DEBUG_BLK0_BACKUP4_W1_OTP_BEBUG_BLOCK0_BACKUP4_W1_Msk = 0xffffffff + + // BLK0_BACKUP4_W2: Otp debuger block0 data register18. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W2 field. + OTP_DEBUG_BLK0_BACKUP4_W2_OTP_BEBUG_BLOCK0_BACKUP4_W2_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W2 field. + OTP_DEBUG_BLK0_BACKUP4_W2_OTP_BEBUG_BLOCK0_BACKUP4_W2_Msk = 0xffffffff + + // BLK0_BACKUP4_W3: Otp debuger block0 data register19. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W3 field. + OTP_DEBUG_BLK0_BACKUP4_W3_OTP_BEBUG_BLOCK0_BACKUP4_W3_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W3 field. + OTP_DEBUG_BLK0_BACKUP4_W3_OTP_BEBUG_BLOCK0_BACKUP4_W3_Msk = 0xffffffff + + // BLK0_BACKUP4_W4: Otp debuger block0 data register20. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W4 field. + OTP_DEBUG_BLK0_BACKUP4_W4_OTP_BEBUG_BLOCK0_BACKUP4_W4_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W4 field. + OTP_DEBUG_BLK0_BACKUP4_W4_OTP_BEBUG_BLOCK0_BACKUP4_W4_Msk = 0xffffffff + + // BLK0_BACKUP4_W5: Otp debuger block0 data register21. + // Position of OTP_BEBUG_BLOCK0_BACKUP4_W5 field. + OTP_DEBUG_BLK0_BACKUP4_W5_OTP_BEBUG_BLOCK0_BACKUP4_W5_Pos = 0x0 + // Bit mask of OTP_BEBUG_BLOCK0_BACKUP4_W5 field. + OTP_DEBUG_BLK0_BACKUP4_W5_OTP_BEBUG_BLOCK0_BACKUP4_W5_Msk = 0xffffffff + + // BLK1_W1: Otp debuger block1 data register1. + // Position of BLOCK1_W1 field. + OTP_DEBUG_BLK1_W1_BLOCK1_W1_Pos = 0x0 + // Bit mask of BLOCK1_W1 field. + OTP_DEBUG_BLK1_W1_BLOCK1_W1_Msk = 0xffffffff + + // BLK1_W2: Otp debuger block1 data register2. + // Position of BLOCK1_W2 field. + OTP_DEBUG_BLK1_W2_BLOCK1_W2_Pos = 0x0 + // Bit mask of BLOCK1_W2 field. + OTP_DEBUG_BLK1_W2_BLOCK1_W2_Msk = 0xffffffff + + // BLK1_W3: Otp debuger block1 data register3. + // Position of BLOCK1_W3 field. + OTP_DEBUG_BLK1_W3_BLOCK1_W3_Pos = 0x0 + // Bit mask of BLOCK1_W3 field. + OTP_DEBUG_BLK1_W3_BLOCK1_W3_Msk = 0xffffffff + + // BLK1_W4: Otp debuger block1 data register4. + // Position of BLOCK1_W4 field. + OTP_DEBUG_BLK1_W4_BLOCK1_W4_Pos = 0x0 + // Bit mask of BLOCK1_W4 field. + OTP_DEBUG_BLK1_W4_BLOCK1_W4_Msk = 0xffffffff + + // BLK1_W5: Otp debuger block1 data register5. + // Position of BLOCK1_W5 field. + OTP_DEBUG_BLK1_W5_BLOCK1_W5_Pos = 0x0 + // Bit mask of BLOCK1_W5 field. + OTP_DEBUG_BLK1_W5_BLOCK1_W5_Msk = 0xffffffff + + // BLK1_W6: Otp debuger block1 data register6. + // Position of BLOCK1_W6 field. + OTP_DEBUG_BLK1_W6_BLOCK1_W6_Pos = 0x0 + // Bit mask of BLOCK1_W6 field. + OTP_DEBUG_BLK1_W6_BLOCK1_W6_Msk = 0xffffffff + + // BLK1_W7: Otp debuger block1 data register7. + // Position of BLOCK1_W7 field. + OTP_DEBUG_BLK1_W7_BLOCK1_W7_Pos = 0x0 + // Bit mask of BLOCK1_W7 field. + OTP_DEBUG_BLK1_W7_BLOCK1_W7_Msk = 0xffffffff + + // BLK1_W8: Otp debuger block1 data register8. + // Position of BLOCK1_W8 field. + OTP_DEBUG_BLK1_W8_BLOCK1_W8_Pos = 0x0 + // Bit mask of BLOCK1_W8 field. + OTP_DEBUG_BLK1_W8_BLOCK1_W8_Msk = 0xffffffff + + // BLK1_W9: Otp debuger block1 data register9. + // Position of BLOCK1_W9 field. + OTP_DEBUG_BLK1_W9_BLOCK1_W9_Pos = 0x0 + // Bit mask of BLOCK1_W9 field. + OTP_DEBUG_BLK1_W9_BLOCK1_W9_Msk = 0xffffffff + + // BLK2_W1: Otp debuger block2 data register1. + // Position of BLOCK2_W1 field. + OTP_DEBUG_BLK2_W1_BLOCK2_W1_Pos = 0x0 + // Bit mask of BLOCK2_W1 field. + OTP_DEBUG_BLK2_W1_BLOCK2_W1_Msk = 0xffffffff + + // BLK2_W2: Otp debuger block2 data register2. + // Position of BLOCK2_W2 field. + OTP_DEBUG_BLK2_W2_BLOCK2_W2_Pos = 0x0 + // Bit mask of BLOCK2_W2 field. + OTP_DEBUG_BLK2_W2_BLOCK2_W2_Msk = 0xffffffff + + // BLK2_W3: Otp debuger block2 data register3. + // Position of BLOCK2_W3 field. + OTP_DEBUG_BLK2_W3_BLOCK2_W3_Pos = 0x0 + // Bit mask of BLOCK2_W3 field. + OTP_DEBUG_BLK2_W3_BLOCK2_W3_Msk = 0xffffffff + + // BLK2_W4: Otp debuger block2 data register4. + // Position of BLOCK2_W4 field. + OTP_DEBUG_BLK2_W4_BLOCK2_W4_Pos = 0x0 + // Bit mask of BLOCK2_W4 field. + OTP_DEBUG_BLK2_W4_BLOCK2_W4_Msk = 0xffffffff + + // BLK2_W5: Otp debuger block2 data register5. + // Position of BLOCK2_W5 field. + OTP_DEBUG_BLK2_W5_BLOCK2_W5_Pos = 0x0 + // Bit mask of BLOCK2_W5 field. + OTP_DEBUG_BLK2_W5_BLOCK2_W5_Msk = 0xffffffff + + // BLK2_W6: Otp debuger block2 data register6. + // Position of BLOCK2_W6 field. + OTP_DEBUG_BLK2_W6_BLOCK2_W6_Pos = 0x0 + // Bit mask of BLOCK2_W6 field. + OTP_DEBUG_BLK2_W6_BLOCK2_W6_Msk = 0xffffffff + + // BLK2_W7: Otp debuger block2 data register7. + // Position of BLOCK2_W7 field. + OTP_DEBUG_BLK2_W7_BLOCK2_W7_Pos = 0x0 + // Bit mask of BLOCK2_W7 field. + OTP_DEBUG_BLK2_W7_BLOCK2_W7_Msk = 0xffffffff + + // BLK2_W8: Otp debuger block2 data register8. + // Position of BLOCK2_W8 field. + OTP_DEBUG_BLK2_W8_BLOCK2_W8_Pos = 0x0 + // Bit mask of BLOCK2_W8 field. + OTP_DEBUG_BLK2_W8_BLOCK2_W8_Msk = 0xffffffff + + // BLK2_W9: Otp debuger block2 data register9. + // Position of BLOCK2_W9 field. + OTP_DEBUG_BLK2_W9_BLOCK2_W9_Pos = 0x0 + // Bit mask of BLOCK2_W9 field. + OTP_DEBUG_BLK2_W9_BLOCK2_W9_Msk = 0xffffffff + + // BLK2_W10: Otp debuger block2 data register10. + // Position of BLOCK2_W10 field. + OTP_DEBUG_BLK2_W10_BLOCK2_W10_Pos = 0x0 + // Bit mask of BLOCK2_W10 field. + OTP_DEBUG_BLK2_W10_BLOCK2_W10_Msk = 0xffffffff + + // BLK2_W11: Otp debuger block2 data register11. + // Position of BLOCK2_W11 field. + OTP_DEBUG_BLK2_W11_BLOCK2_W11_Pos = 0x0 + // Bit mask of BLOCK2_W11 field. + OTP_DEBUG_BLK2_W11_BLOCK2_W11_Msk = 0xffffffff + + // BLK3_W1: Otp debuger block3 data register1. + // Position of BLOCK3_W1 field. + OTP_DEBUG_BLK3_W1_BLOCK3_W1_Pos = 0x0 + // Bit mask of BLOCK3_W1 field. + OTP_DEBUG_BLK3_W1_BLOCK3_W1_Msk = 0xffffffff + + // BLK3_W2: Otp debuger block3 data register2. + // Position of BLOCK3_W2 field. + OTP_DEBUG_BLK3_W2_BLOCK3_W2_Pos = 0x0 + // Bit mask of BLOCK3_W2 field. + OTP_DEBUG_BLK3_W2_BLOCK3_W2_Msk = 0xffffffff + + // BLK3_W3: Otp debuger block3 data register3. + // Position of BLOCK3_W3 field. + OTP_DEBUG_BLK3_W3_BLOCK3_W3_Pos = 0x0 + // Bit mask of BLOCK3_W3 field. + OTP_DEBUG_BLK3_W3_BLOCK3_W3_Msk = 0xffffffff + + // BLK3_W4: Otp debuger block3 data register4. + // Position of BLOCK3_W4 field. + OTP_DEBUG_BLK3_W4_BLOCK3_W4_Pos = 0x0 + // Bit mask of BLOCK3_W4 field. + OTP_DEBUG_BLK3_W4_BLOCK3_W4_Msk = 0xffffffff + + // BLK3_W5: Otp debuger block3 data register5. + // Position of BLOCK3_W5 field. + OTP_DEBUG_BLK3_W5_BLOCK3_W5_Pos = 0x0 + // Bit mask of BLOCK3_W5 field. + OTP_DEBUG_BLK3_W5_BLOCK3_W5_Msk = 0xffffffff + + // BLK3_W6: Otp debuger block3 data register6. + // Position of BLOCK3_W6 field. + OTP_DEBUG_BLK3_W6_BLOCK3_W6_Pos = 0x0 + // Bit mask of BLOCK3_W6 field. + OTP_DEBUG_BLK3_W6_BLOCK3_W6_Msk = 0xffffffff + + // BLK3_W7: Otp debuger block3 data register7. + // Position of BLOCK3_W7 field. + OTP_DEBUG_BLK3_W7_BLOCK3_W7_Pos = 0x0 + // Bit mask of BLOCK3_W7 field. + OTP_DEBUG_BLK3_W7_BLOCK3_W7_Msk = 0xffffffff + + // BLK3_W8: Otp debuger block3 data register8. + // Position of BLOCK3_W8 field. + OTP_DEBUG_BLK3_W8_BLOCK3_W8_Pos = 0x0 + // Bit mask of BLOCK3_W8 field. + OTP_DEBUG_BLK3_W8_BLOCK3_W8_Msk = 0xffffffff + + // BLK3_W9: Otp debuger block3 data register9. + // Position of BLOCK3_W9 field. + OTP_DEBUG_BLK3_W9_BLOCK3_W9_Pos = 0x0 + // Bit mask of BLOCK3_W9 field. + OTP_DEBUG_BLK3_W9_BLOCK3_W9_Msk = 0xffffffff + + // BLK3_W10: Otp debuger block3 data register10. + // Position of BLOCK3_W10 field. + OTP_DEBUG_BLK3_W10_BLOCK3_W10_Pos = 0x0 + // Bit mask of BLOCK3_W10 field. + OTP_DEBUG_BLK3_W10_BLOCK3_W10_Msk = 0xffffffff + + // BLK3_W11: Otp debuger block3 data register11. + // Position of BLOCK3_W11 field. + OTP_DEBUG_BLK3_W11_BLOCK3_W11_Pos = 0x0 + // Bit mask of BLOCK3_W11 field. + OTP_DEBUG_BLK3_W11_BLOCK3_W11_Msk = 0xffffffff + + // BLK4_W1: Otp debuger block4 data register1. + // Position of BLOCK4_W1 field. + OTP_DEBUG_BLK4_W1_BLOCK4_W1_Pos = 0x0 + // Bit mask of BLOCK4_W1 field. + OTP_DEBUG_BLK4_W1_BLOCK4_W1_Msk = 0xffffffff + + // BLK4_W2: Otp debuger block4 data register2. + // Position of BLOCK4_W2 field. + OTP_DEBUG_BLK4_W2_BLOCK4_W2_Pos = 0x0 + // Bit mask of BLOCK4_W2 field. + OTP_DEBUG_BLK4_W2_BLOCK4_W2_Msk = 0xffffffff + + // BLK4_W3: Otp debuger block4 data register3. + // Position of BLOCK4_W3 field. + OTP_DEBUG_BLK4_W3_BLOCK4_W3_Pos = 0x0 + // Bit mask of BLOCK4_W3 field. + OTP_DEBUG_BLK4_W3_BLOCK4_W3_Msk = 0xffffffff + + // BLK4_W4: Otp debuger block4 data register4. + // Position of BLOCK4_W4 field. + OTP_DEBUG_BLK4_W4_BLOCK4_W4_Pos = 0x0 + // Bit mask of BLOCK4_W4 field. + OTP_DEBUG_BLK4_W4_BLOCK4_W4_Msk = 0xffffffff + + // BLK4_W5: Otp debuger block4 data register5. + // Position of BLOCK4_W5 field. + OTP_DEBUG_BLK4_W5_BLOCK4_W5_Pos = 0x0 + // Bit mask of BLOCK4_W5 field. + OTP_DEBUG_BLK4_W5_BLOCK4_W5_Msk = 0xffffffff + + // BLK4_W6: Otp debuger block4 data register6. + // Position of BLOCK4_W6 field. + OTP_DEBUG_BLK4_W6_BLOCK4_W6_Pos = 0x0 + // Bit mask of BLOCK4_W6 field. + OTP_DEBUG_BLK4_W6_BLOCK4_W6_Msk = 0xffffffff + + // BLK4_W7: Otp debuger block4 data register7. + // Position of BLOCK4_W7 field. + OTP_DEBUG_BLK4_W7_BLOCK4_W7_Pos = 0x0 + // Bit mask of BLOCK4_W7 field. + OTP_DEBUG_BLK4_W7_BLOCK4_W7_Msk = 0xffffffff + + // BLK4_W8: Otp debuger block4 data register8. + // Position of BLOCK4_W8 field. + OTP_DEBUG_BLK4_W8_BLOCK4_W8_Pos = 0x0 + // Bit mask of BLOCK4_W8 field. + OTP_DEBUG_BLK4_W8_BLOCK4_W8_Msk = 0xffffffff + + // BLK4_W9: Otp debuger block4 data register9. + // Position of BLOCK4_W9 field. + OTP_DEBUG_BLK4_W9_BLOCK4_W9_Pos = 0x0 + // Bit mask of BLOCK4_W9 field. + OTP_DEBUG_BLK4_W9_BLOCK4_W9_Msk = 0xffffffff + + // BLK4_W10: Otp debuger block4 data registe10. + // Position of BLOCK4_W10 field. + OTP_DEBUG_BLK4_W10_BLOCK4_W10_Pos = 0x0 + // Bit mask of BLOCK4_W10 field. + OTP_DEBUG_BLK4_W10_BLOCK4_W10_Msk = 0xffffffff + + // BLK4_W11: Otp debuger block4 data register11. + // Position of BLOCK4_W11 field. + OTP_DEBUG_BLK4_W11_BLOCK4_W11_Pos = 0x0 + // Bit mask of BLOCK4_W11 field. + OTP_DEBUG_BLK4_W11_BLOCK4_W11_Msk = 0xffffffff + + // BLK5_W1: Otp debuger block5 data register1. + // Position of BLOCK5_W1 field. + OTP_DEBUG_BLK5_W1_BLOCK5_W1_Pos = 0x0 + // Bit mask of BLOCK5_W1 field. + OTP_DEBUG_BLK5_W1_BLOCK5_W1_Msk = 0xffffffff + + // BLK5_W2: Otp debuger block5 data register2. + // Position of BLOCK5_W2 field. + OTP_DEBUG_BLK5_W2_BLOCK5_W2_Pos = 0x0 + // Bit mask of BLOCK5_W2 field. + OTP_DEBUG_BLK5_W2_BLOCK5_W2_Msk = 0xffffffff + + // BLK5_W3: Otp debuger block5 data register3. + // Position of BLOCK5_W3 field. + OTP_DEBUG_BLK5_W3_BLOCK5_W3_Pos = 0x0 + // Bit mask of BLOCK5_W3 field. + OTP_DEBUG_BLK5_W3_BLOCK5_W3_Msk = 0xffffffff + + // BLK5_W4: Otp debuger block5 data register4. + // Position of BLOCK5_W4 field. + OTP_DEBUG_BLK5_W4_BLOCK5_W4_Pos = 0x0 + // Bit mask of BLOCK5_W4 field. + OTP_DEBUG_BLK5_W4_BLOCK5_W4_Msk = 0xffffffff + + // BLK5_W5: Otp debuger block5 data register5. + // Position of BLOCK5_W5 field. + OTP_DEBUG_BLK5_W5_BLOCK5_W5_Pos = 0x0 + // Bit mask of BLOCK5_W5 field. + OTP_DEBUG_BLK5_W5_BLOCK5_W5_Msk = 0xffffffff + + // BLK5_W6: Otp debuger block5 data register6. + // Position of BLOCK5_W6 field. + OTP_DEBUG_BLK5_W6_BLOCK5_W6_Pos = 0x0 + // Bit mask of BLOCK5_W6 field. + OTP_DEBUG_BLK5_W6_BLOCK5_W6_Msk = 0xffffffff + + // BLK5_W7: Otp debuger block5 data register7. + // Position of BLOCK5_W7 field. + OTP_DEBUG_BLK5_W7_BLOCK5_W7_Pos = 0x0 + // Bit mask of BLOCK5_W7 field. + OTP_DEBUG_BLK5_W7_BLOCK5_W7_Msk = 0xffffffff + + // BLK5_W8: Otp debuger block5 data register8. + // Position of BLOCK5_W8 field. + OTP_DEBUG_BLK5_W8_BLOCK5_W8_Pos = 0x0 + // Bit mask of BLOCK5_W8 field. + OTP_DEBUG_BLK5_W8_BLOCK5_W8_Msk = 0xffffffff + + // BLK5_W9: Otp debuger block5 data register9. + // Position of BLOCK5_W9 field. + OTP_DEBUG_BLK5_W9_BLOCK5_W9_Pos = 0x0 + // Bit mask of BLOCK5_W9 field. + OTP_DEBUG_BLK5_W9_BLOCK5_W9_Msk = 0xffffffff + + // BLK5_W10: Otp debuger block5 data register10. + // Position of BLOCK5_W10 field. + OTP_DEBUG_BLK5_W10_BLOCK5_W10_Pos = 0x0 + // Bit mask of BLOCK5_W10 field. + OTP_DEBUG_BLK5_W10_BLOCK5_W10_Msk = 0xffffffff + + // BLK5_W11: Otp debuger block5 data register11. + // Position of BLOCK5_W11 field. + OTP_DEBUG_BLK5_W11_BLOCK5_W11_Pos = 0x0 + // Bit mask of BLOCK5_W11 field. + OTP_DEBUG_BLK5_W11_BLOCK5_W11_Msk = 0xffffffff + + // BLK6_W1: Otp debuger block6 data register1. + // Position of BLOCK6_W1 field. + OTP_DEBUG_BLK6_W1_BLOCK6_W1_Pos = 0x0 + // Bit mask of BLOCK6_W1 field. + OTP_DEBUG_BLK6_W1_BLOCK6_W1_Msk = 0xffffffff + + // BLK6_W2: Otp debuger block6 data register2. + // Position of BLOCK6_W2 field. + OTP_DEBUG_BLK6_W2_BLOCK6_W2_Pos = 0x0 + // Bit mask of BLOCK6_W2 field. + OTP_DEBUG_BLK6_W2_BLOCK6_W2_Msk = 0xffffffff + + // BLK6_W3: Otp debuger block6 data register3. + // Position of BLOCK6_W3 field. + OTP_DEBUG_BLK6_W3_BLOCK6_W3_Pos = 0x0 + // Bit mask of BLOCK6_W3 field. + OTP_DEBUG_BLK6_W3_BLOCK6_W3_Msk = 0xffffffff + + // BLK6_W4: Otp debuger block6 data register4. + // Position of BLOCK6_W4 field. + OTP_DEBUG_BLK6_W4_BLOCK6_W4_Pos = 0x0 + // Bit mask of BLOCK6_W4 field. + OTP_DEBUG_BLK6_W4_BLOCK6_W4_Msk = 0xffffffff + + // BLK6_W5: Otp debuger block6 data register5. + // Position of BLOCK6_W5 field. + OTP_DEBUG_BLK6_W5_BLOCK6_W5_Pos = 0x0 + // Bit mask of BLOCK6_W5 field. + OTP_DEBUG_BLK6_W5_BLOCK6_W5_Msk = 0xffffffff + + // BLK6_W6: Otp debuger block6 data register6. + // Position of BLOCK6_W6 field. + OTP_DEBUG_BLK6_W6_BLOCK6_W6_Pos = 0x0 + // Bit mask of BLOCK6_W6 field. + OTP_DEBUG_BLK6_W6_BLOCK6_W6_Msk = 0xffffffff + + // BLK6_W7: Otp debuger block6 data register7. + // Position of BLOCK6_W7 field. + OTP_DEBUG_BLK6_W7_BLOCK6_W7_Pos = 0x0 + // Bit mask of BLOCK6_W7 field. + OTP_DEBUG_BLK6_W7_BLOCK6_W7_Msk = 0xffffffff + + // BLK6_W8: Otp debuger block6 data register8. + // Position of BLOCK6_W8 field. + OTP_DEBUG_BLK6_W8_BLOCK6_W8_Pos = 0x0 + // Bit mask of BLOCK6_W8 field. + OTP_DEBUG_BLK6_W8_BLOCK6_W8_Msk = 0xffffffff + + // BLK6_W9: Otp debuger block6 data register9. + // Position of BLOCK6_W9 field. + OTP_DEBUG_BLK6_W9_BLOCK6_W9_Pos = 0x0 + // Bit mask of BLOCK6_W9 field. + OTP_DEBUG_BLK6_W9_BLOCK6_W9_Msk = 0xffffffff + + // BLK6_W10: Otp debuger block6 data register10. + // Position of BLOCK6_W10 field. + OTP_DEBUG_BLK6_W10_BLOCK6_W10_Pos = 0x0 + // Bit mask of BLOCK6_W10 field. + OTP_DEBUG_BLK6_W10_BLOCK6_W10_Msk = 0xffffffff + + // BLK6_W11: Otp debuger block6 data register11. + // Position of BLOCK6_W11 field. + OTP_DEBUG_BLK6_W11_BLOCK6_W11_Pos = 0x0 + // Bit mask of BLOCK6_W11 field. + OTP_DEBUG_BLK6_W11_BLOCK6_W11_Msk = 0xffffffff + + // BLK7_W1: Otp debuger block7 data register1. + // Position of BLOCK7_W1 field. + OTP_DEBUG_BLK7_W1_BLOCK7_W1_Pos = 0x0 + // Bit mask of BLOCK7_W1 field. + OTP_DEBUG_BLK7_W1_BLOCK7_W1_Msk = 0xffffffff + + // BLK7_W2: Otp debuger block7 data register2. + // Position of BLOCK7_W2 field. + OTP_DEBUG_BLK7_W2_BLOCK7_W2_Pos = 0x0 + // Bit mask of BLOCK7_W2 field. + OTP_DEBUG_BLK7_W2_BLOCK7_W2_Msk = 0xffffffff + + // BLK7_W3: Otp debuger block7 data register3. + // Position of BLOCK7_W3 field. + OTP_DEBUG_BLK7_W3_BLOCK7_W3_Pos = 0x0 + // Bit mask of BLOCK7_W3 field. + OTP_DEBUG_BLK7_W3_BLOCK7_W3_Msk = 0xffffffff + + // BLK7_W4: Otp debuger block7 data register4. + // Position of BLOCK7_W4 field. + OTP_DEBUG_BLK7_W4_BLOCK7_W4_Pos = 0x0 + // Bit mask of BLOCK7_W4 field. + OTP_DEBUG_BLK7_W4_BLOCK7_W4_Msk = 0xffffffff + + // BLK7_W5: Otp debuger block7 data register5. + // Position of BLOCK7_W5 field. + OTP_DEBUG_BLK7_W5_BLOCK7_W5_Pos = 0x0 + // Bit mask of BLOCK7_W5 field. + OTP_DEBUG_BLK7_W5_BLOCK7_W5_Msk = 0xffffffff + + // BLK7_W6: Otp debuger block7 data register6. + // Position of BLOCK7_W6 field. + OTP_DEBUG_BLK7_W6_BLOCK7_W6_Pos = 0x0 + // Bit mask of BLOCK7_W6 field. + OTP_DEBUG_BLK7_W6_BLOCK7_W6_Msk = 0xffffffff + + // BLK7_W7: Otp debuger block7 data register7. + // Position of BLOCK7_W7 field. + OTP_DEBUG_BLK7_W7_BLOCK7_W7_Pos = 0x0 + // Bit mask of BLOCK7_W7 field. + OTP_DEBUG_BLK7_W7_BLOCK7_W7_Msk = 0xffffffff + + // BLK7_W8: Otp debuger block7 data register8. + // Position of BLOCK7_W8 field. + OTP_DEBUG_BLK7_W8_BLOCK7_W8_Pos = 0x0 + // Bit mask of BLOCK7_W8 field. + OTP_DEBUG_BLK7_W8_BLOCK7_W8_Msk = 0xffffffff + + // BLK7_W9: Otp debuger block7 data register9. + // Position of BLOCK7_W9 field. + OTP_DEBUG_BLK7_W9_BLOCK7_W9_Pos = 0x0 + // Bit mask of BLOCK7_W9 field. + OTP_DEBUG_BLK7_W9_BLOCK7_W9_Msk = 0xffffffff + + // BLK7_W10: Otp debuger block7 data register10. + // Position of BLOCK7_W10 field. + OTP_DEBUG_BLK7_W10_BLOCK7_W10_Pos = 0x0 + // Bit mask of BLOCK7_W10 field. + OTP_DEBUG_BLK7_W10_BLOCK7_W10_Msk = 0xffffffff + + // BLK7_W11: Otp debuger block7 data register11. + // Position of BLOCK7_W11 field. + OTP_DEBUG_BLK7_W11_BLOCK7_W11_Pos = 0x0 + // Bit mask of BLOCK7_W11 field. + OTP_DEBUG_BLK7_W11_BLOCK7_W11_Msk = 0xffffffff + + // BLK8_W1: Otp debuger block8 data register1. + // Position of BLOCK8_W1 field. + OTP_DEBUG_BLK8_W1_BLOCK8_W1_Pos = 0x0 + // Bit mask of BLOCK8_W1 field. + OTP_DEBUG_BLK8_W1_BLOCK8_W1_Msk = 0xffffffff + + // BLK8_W2: Otp debuger block8 data register2. + // Position of BLOCK8_W2 field. + OTP_DEBUG_BLK8_W2_BLOCK8_W2_Pos = 0x0 + // Bit mask of BLOCK8_W2 field. + OTP_DEBUG_BLK8_W2_BLOCK8_W2_Msk = 0xffffffff + + // BLK8_W3: Otp debuger block8 data register3. + // Position of BLOCK8_W3 field. + OTP_DEBUG_BLK8_W3_BLOCK8_W3_Pos = 0x0 + // Bit mask of BLOCK8_W3 field. + OTP_DEBUG_BLK8_W3_BLOCK8_W3_Msk = 0xffffffff + + // BLK8_W4: Otp debuger block8 data register4. + // Position of BLOCK8_W4 field. + OTP_DEBUG_BLK8_W4_BLOCK8_W4_Pos = 0x0 + // Bit mask of BLOCK8_W4 field. + OTP_DEBUG_BLK8_W4_BLOCK8_W4_Msk = 0xffffffff + + // BLK8_W5: Otp debuger block8 data register5. + // Position of BLOCK8_W5 field. + OTP_DEBUG_BLK8_W5_BLOCK8_W5_Pos = 0x0 + // Bit mask of BLOCK8_W5 field. + OTP_DEBUG_BLK8_W5_BLOCK8_W5_Msk = 0xffffffff + + // BLK8_W6: Otp debuger block8 data register6. + // Position of BLOCK8_W6 field. + OTP_DEBUG_BLK8_W6_BLOCK8_W6_Pos = 0x0 + // Bit mask of BLOCK8_W6 field. + OTP_DEBUG_BLK8_W6_BLOCK8_W6_Msk = 0xffffffff + + // BLK8_W7: Otp debuger block8 data register7. + // Position of BLOCK8_W7 field. + OTP_DEBUG_BLK8_W7_BLOCK8_W7_Pos = 0x0 + // Bit mask of BLOCK8_W7 field. + OTP_DEBUG_BLK8_W7_BLOCK8_W7_Msk = 0xffffffff + + // BLK8_W8: Otp debuger block8 data register8. + // Position of BLOCK8_W8 field. + OTP_DEBUG_BLK8_W8_BLOCK8_W8_Pos = 0x0 + // Bit mask of BLOCK8_W8 field. + OTP_DEBUG_BLK8_W8_BLOCK8_W8_Msk = 0xffffffff + + // BLK8_W9: Otp debuger block8 data register9. + // Position of BLOCK8_W9 field. + OTP_DEBUG_BLK8_W9_BLOCK8_W9_Pos = 0x0 + // Bit mask of BLOCK8_W9 field. + OTP_DEBUG_BLK8_W9_BLOCK8_W9_Msk = 0xffffffff + + // BLK8_W10: Otp debuger block8 data register10. + // Position of BLOCK8_W10 field. + OTP_DEBUG_BLK8_W10_BLOCK8_W10_Pos = 0x0 + // Bit mask of BLOCK8_W10 field. + OTP_DEBUG_BLK8_W10_BLOCK8_W10_Msk = 0xffffffff + + // BLK8_W11: Otp debuger block8 data register11. + // Position of BLOCK8_W11 field. + OTP_DEBUG_BLK8_W11_BLOCK8_W11_Pos = 0x0 + // Bit mask of BLOCK8_W11 field. + OTP_DEBUG_BLK8_W11_BLOCK8_W11_Msk = 0xffffffff + + // BLK9_W1: Otp debuger block9 data register1. + // Position of BLOCK9_W1 field. + OTP_DEBUG_BLK9_W1_BLOCK9_W1_Pos = 0x0 + // Bit mask of BLOCK9_W1 field. + OTP_DEBUG_BLK9_W1_BLOCK9_W1_Msk = 0xffffffff + + // BLK9_W2: Otp debuger block9 data register2. + // Position of BLOCK9_W2 field. + OTP_DEBUG_BLK9_W2_BLOCK9_W2_Pos = 0x0 + // Bit mask of BLOCK9_W2 field. + OTP_DEBUG_BLK9_W2_BLOCK9_W2_Msk = 0xffffffff + + // BLK9_W3: Otp debuger block9 data register3. + // Position of BLOCK9_W3 field. + OTP_DEBUG_BLK9_W3_BLOCK9_W3_Pos = 0x0 + // Bit mask of BLOCK9_W3 field. + OTP_DEBUG_BLK9_W3_BLOCK9_W3_Msk = 0xffffffff + + // BLK9_W4: Otp debuger block9 data register4. + // Position of BLOCK9_W4 field. + OTP_DEBUG_BLK9_W4_BLOCK9_W4_Pos = 0x0 + // Bit mask of BLOCK9_W4 field. + OTP_DEBUG_BLK9_W4_BLOCK9_W4_Msk = 0xffffffff + + // BLK9_W5: Otp debuger block9 data register5. + // Position of BLOCK9_W5 field. + OTP_DEBUG_BLK9_W5_BLOCK9_W5_Pos = 0x0 + // Bit mask of BLOCK9_W5 field. + OTP_DEBUG_BLK9_W5_BLOCK9_W5_Msk = 0xffffffff + + // BLK9_W6: Otp debuger block9 data register6. + // Position of BLOCK9_W6 field. + OTP_DEBUG_BLK9_W6_BLOCK9_W6_Pos = 0x0 + // Bit mask of BLOCK9_W6 field. + OTP_DEBUG_BLK9_W6_BLOCK9_W6_Msk = 0xffffffff + + // BLK9_W7: Otp debuger block9 data register7. + // Position of BLOCK9_W7 field. + OTP_DEBUG_BLK9_W7_BLOCK9_W7_Pos = 0x0 + // Bit mask of BLOCK9_W7 field. + OTP_DEBUG_BLK9_W7_BLOCK9_W7_Msk = 0xffffffff + + // BLK9_W8: Otp debuger block9 data register8. + // Position of BLOCK9_W8 field. + OTP_DEBUG_BLK9_W8_BLOCK9_W8_Pos = 0x0 + // Bit mask of BLOCK9_W8 field. + OTP_DEBUG_BLK9_W8_BLOCK9_W8_Msk = 0xffffffff + + // BLK9_W9: Otp debuger block9 data register9. + // Position of BLOCK9_W9 field. + OTP_DEBUG_BLK9_W9_BLOCK9_W9_Pos = 0x0 + // Bit mask of BLOCK9_W9 field. + OTP_DEBUG_BLK9_W9_BLOCK9_W9_Msk = 0xffffffff + + // BLK9_W10: Otp debuger block9 data register10. + // Position of BLOCK9_W10 field. + OTP_DEBUG_BLK9_W10_BLOCK9_W10_Pos = 0x0 + // Bit mask of BLOCK9_W10 field. + OTP_DEBUG_BLK9_W10_BLOCK9_W10_Msk = 0xffffffff + + // BLK9_W11: Otp debuger block9 data register11. + // Position of BLOCK9_W11 field. + OTP_DEBUG_BLK9_W11_BLOCK9_W11_Pos = 0x0 + // Bit mask of BLOCK9_W11 field. + OTP_DEBUG_BLK9_W11_BLOCK9_W11_Msk = 0xffffffff + + // BLK10_W1: Otp debuger block10 data register1. + // Position of BLOCK10_W1 field. + OTP_DEBUG_BLK10_W1_BLOCK10_W1_Pos = 0x0 + // Bit mask of BLOCK10_W1 field. + OTP_DEBUG_BLK10_W1_BLOCK10_W1_Msk = 0xffffffff + + // BLK10_W2: Otp debuger block10 data register2. + // Position of BLOCK10_W2 field. + OTP_DEBUG_BLK10_W2_BLOCK10_W2_Pos = 0x0 + // Bit mask of BLOCK10_W2 field. + OTP_DEBUG_BLK10_W2_BLOCK10_W2_Msk = 0xffffffff + + // BLK10_W3: Otp debuger block10 data register3. + // Position of BLOCK10_W3 field. + OTP_DEBUG_BLK10_W3_BLOCK10_W3_Pos = 0x0 + // Bit mask of BLOCK10_W3 field. + OTP_DEBUG_BLK10_W3_BLOCK10_W3_Msk = 0xffffffff + + // BLK10_W4: Otp debuger block10 data register4. + // Position of BLOCK10_W4 field. + OTP_DEBUG_BLK10_W4_BLOCK10_W4_Pos = 0x0 + // Bit mask of BLOCK10_W4 field. + OTP_DEBUG_BLK10_W4_BLOCK10_W4_Msk = 0xffffffff + + // BLK10_W5: Otp debuger block10 data register5. + // Position of BLOCK10_W5 field. + OTP_DEBUG_BLK10_W5_BLOCK10_W5_Pos = 0x0 + // Bit mask of BLOCK10_W5 field. + OTP_DEBUG_BLK10_W5_BLOCK10_W5_Msk = 0xffffffff + + // BLK10_W6: Otp debuger block10 data register6. + // Position of BLOCK10_W6 field. + OTP_DEBUG_BLK10_W6_BLOCK10_W6_Pos = 0x0 + // Bit mask of BLOCK10_W6 field. + OTP_DEBUG_BLK10_W6_BLOCK10_W6_Msk = 0xffffffff + + // BLK10_W7: Otp debuger block10 data register7. + // Position of BLOCK10_W7 field. + OTP_DEBUG_BLK10_W7_BLOCK10_W7_Pos = 0x0 + // Bit mask of BLOCK10_W7 field. + OTP_DEBUG_BLK10_W7_BLOCK10_W7_Msk = 0xffffffff + + // BLK10_W8: Otp debuger block10 data register8. + // Position of BLOCK10_W8 field. + OTP_DEBUG_BLK10_W8_BLOCK10_W8_Pos = 0x0 + // Bit mask of BLOCK10_W8 field. + OTP_DEBUG_BLK10_W8_BLOCK10_W8_Msk = 0xffffffff + + // BLK10_W9: Otp debuger block10 data register9. + // Position of BLOCK10_W9 field. + OTP_DEBUG_BLK10_W9_BLOCK10_W9_Pos = 0x0 + // Bit mask of BLOCK10_W9 field. + OTP_DEBUG_BLK10_W9_BLOCK10_W9_Msk = 0xffffffff + + // BLK10_W10: Otp debuger block10 data register10. + // Position of BLOCK19_W10 field. + OTP_DEBUG_BLK10_W10_BLOCK19_W10_Pos = 0x0 + // Bit mask of BLOCK19_W10 field. + OTP_DEBUG_BLK10_W10_BLOCK19_W10_Msk = 0xffffffff + + // BLK10_W11: Otp debuger block10 data register11. + // Position of BLOCK10_W11 field. + OTP_DEBUG_BLK10_W11_BLOCK10_W11_Pos = 0x0 + // Bit mask of BLOCK10_W11 field. + OTP_DEBUG_BLK10_W11_BLOCK10_W11_Msk = 0xffffffff + + // CLK: Otp debuger clk_en configuration register. + // Position of EN field. + OTP_DEBUG_CLK_EN_Pos = 0x0 + // Bit mask of EN field. + OTP_DEBUG_CLK_EN_Msk = 0x1 + // Bit EN. + OTP_DEBUG_CLK_EN = 0x1 + + // APB2OTP_EN: Otp_debuger apb2otp enable configuration register. + // Position of APB2OTP_EN field. + OTP_DEBUG_APB2OTP_EN_APB2OTP_EN_Pos = 0x0 + // Bit mask of APB2OTP_EN field. + OTP_DEBUG_APB2OTP_EN_APB2OTP_EN_Msk = 0x1 + // Bit APB2OTP_EN. + OTP_DEBUG_APB2OTP_EN_APB2OTP_EN = 0x1 + + // DATE: eFuse version register. + // Position of DATE field. + OTP_DEBUG_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + OTP_DEBUG_DATE_DATE_Msk = 0xfffffff +) + +// Constants for PARL_IO: Parallel IO Controller +const ( + // RX_MODE_CFG: Parallel RX Sampling mode configuration register. + // Position of RX_EXT_EN_SEL field. + PARL_IO_RX_MODE_CFG_RX_EXT_EN_SEL_Pos = 0x15 + // Bit mask of RX_EXT_EN_SEL field. + PARL_IO_RX_MODE_CFG_RX_EXT_EN_SEL_Msk = 0x1e00000 + // Position of RX_SW_EN field. + PARL_IO_RX_MODE_CFG_RX_SW_EN_Pos = 0x19 + // Bit mask of RX_SW_EN field. + PARL_IO_RX_MODE_CFG_RX_SW_EN_Msk = 0x2000000 + // Bit RX_SW_EN. + PARL_IO_RX_MODE_CFG_RX_SW_EN = 0x2000000 + // Position of RX_EXT_EN_INV field. + PARL_IO_RX_MODE_CFG_RX_EXT_EN_INV_Pos = 0x1a + // Bit mask of RX_EXT_EN_INV field. + PARL_IO_RX_MODE_CFG_RX_EXT_EN_INV_Msk = 0x4000000 + // Bit RX_EXT_EN_INV. + PARL_IO_RX_MODE_CFG_RX_EXT_EN_INV = 0x4000000 + // Position of RX_PULSE_SUBMODE_SEL field. + PARL_IO_RX_MODE_CFG_RX_PULSE_SUBMODE_SEL_Pos = 0x1b + // Bit mask of RX_PULSE_SUBMODE_SEL field. + PARL_IO_RX_MODE_CFG_RX_PULSE_SUBMODE_SEL_Msk = 0x38000000 + // Position of RX_SMP_MODE_SEL field. + PARL_IO_RX_MODE_CFG_RX_SMP_MODE_SEL_Pos = 0x1e + // Bit mask of RX_SMP_MODE_SEL field. + PARL_IO_RX_MODE_CFG_RX_SMP_MODE_SEL_Msk = 0xc0000000 + + // RX_DATA_CFG: Parallel RX data configuration register. + // Position of RX_BITLEN field. + PARL_IO_RX_DATA_CFG_RX_BITLEN_Pos = 0x9 + // Bit mask of RX_BITLEN field. + PARL_IO_RX_DATA_CFG_RX_BITLEN_Msk = 0xffffe00 + // Position of RX_DATA_ORDER_INV field. + PARL_IO_RX_DATA_CFG_RX_DATA_ORDER_INV_Pos = 0x1c + // Bit mask of RX_DATA_ORDER_INV field. + PARL_IO_RX_DATA_CFG_RX_DATA_ORDER_INV_Msk = 0x10000000 + // Bit RX_DATA_ORDER_INV. + PARL_IO_RX_DATA_CFG_RX_DATA_ORDER_INV = 0x10000000 + // Position of RX_BUS_WID_SEL field. + PARL_IO_RX_DATA_CFG_RX_BUS_WID_SEL_Pos = 0x1d + // Bit mask of RX_BUS_WID_SEL field. + PARL_IO_RX_DATA_CFG_RX_BUS_WID_SEL_Msk = 0xe0000000 + + // RX_GENRL_CFG: Parallel RX general configuration register. + // Position of RX_GATING_EN field. + PARL_IO_RX_GENRL_CFG_RX_GATING_EN_Pos = 0xc + // Bit mask of RX_GATING_EN field. + PARL_IO_RX_GENRL_CFG_RX_GATING_EN_Msk = 0x1000 + // Bit RX_GATING_EN. + PARL_IO_RX_GENRL_CFG_RX_GATING_EN = 0x1000 + // Position of RX_TIMEOUT_THRES field. + PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_THRES_Pos = 0xd + // Bit mask of RX_TIMEOUT_THRES field. + PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_THRES_Msk = 0x1fffe000 + // Position of RX_TIMEOUT_EN field. + PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_EN_Pos = 0x1d + // Bit mask of RX_TIMEOUT_EN field. + PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_EN_Msk = 0x20000000 + // Bit RX_TIMEOUT_EN. + PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_EN = 0x20000000 + // Position of RX_EOF_GEN_SEL field. + PARL_IO_RX_GENRL_CFG_RX_EOF_GEN_SEL_Pos = 0x1e + // Bit mask of RX_EOF_GEN_SEL field. + PARL_IO_RX_GENRL_CFG_RX_EOF_GEN_SEL_Msk = 0x40000000 + // Bit RX_EOF_GEN_SEL. + PARL_IO_RX_GENRL_CFG_RX_EOF_GEN_SEL = 0x40000000 + + // RX_START_CFG: Parallel RX Start configuration register. + // Position of RX_START field. + PARL_IO_RX_START_CFG_RX_START_Pos = 0x1f + // Bit mask of RX_START field. + PARL_IO_RX_START_CFG_RX_START_Msk = 0x80000000 + // Bit RX_START. + PARL_IO_RX_START_CFG_RX_START = 0x80000000 + + // TX_DATA_CFG: Parallel TX data configuration register. + // Position of TX_BITLEN field. + PARL_IO_TX_DATA_CFG_TX_BITLEN_Pos = 0x9 + // Bit mask of TX_BITLEN field. + PARL_IO_TX_DATA_CFG_TX_BITLEN_Msk = 0xffffe00 + // Position of TX_DATA_ORDER_INV field. + PARL_IO_TX_DATA_CFG_TX_DATA_ORDER_INV_Pos = 0x1c + // Bit mask of TX_DATA_ORDER_INV field. + PARL_IO_TX_DATA_CFG_TX_DATA_ORDER_INV_Msk = 0x10000000 + // Bit TX_DATA_ORDER_INV. + PARL_IO_TX_DATA_CFG_TX_DATA_ORDER_INV = 0x10000000 + // Position of TX_BUS_WID_SEL field. + PARL_IO_TX_DATA_CFG_TX_BUS_WID_SEL_Pos = 0x1d + // Bit mask of TX_BUS_WID_SEL field. + PARL_IO_TX_DATA_CFG_TX_BUS_WID_SEL_Msk = 0xe0000000 + + // TX_START_CFG: Parallel TX Start configuration register. + // Position of TX_START field. + PARL_IO_TX_START_CFG_TX_START_Pos = 0x1f + // Bit mask of TX_START field. + PARL_IO_TX_START_CFG_TX_START_Msk = 0x80000000 + // Bit TX_START. + PARL_IO_TX_START_CFG_TX_START = 0x80000000 + + // TX_GENRL_CFG: Parallel TX general configuration register. + // Position of TX_IDLE_VALUE field. + PARL_IO_TX_GENRL_CFG_TX_IDLE_VALUE_Pos = 0xe + // Bit mask of TX_IDLE_VALUE field. + PARL_IO_TX_GENRL_CFG_TX_IDLE_VALUE_Msk = 0x3fffc000 + // Position of TX_GATING_EN field. + PARL_IO_TX_GENRL_CFG_TX_GATING_EN_Pos = 0x1e + // Bit mask of TX_GATING_EN field. + PARL_IO_TX_GENRL_CFG_TX_GATING_EN_Msk = 0x40000000 + // Bit TX_GATING_EN. + PARL_IO_TX_GENRL_CFG_TX_GATING_EN = 0x40000000 + // Position of TX_VALID_OUTPUT_EN field. + PARL_IO_TX_GENRL_CFG_TX_VALID_OUTPUT_EN_Pos = 0x1f + // Bit mask of TX_VALID_OUTPUT_EN field. + PARL_IO_TX_GENRL_CFG_TX_VALID_OUTPUT_EN_Msk = 0x80000000 + // Bit TX_VALID_OUTPUT_EN. + PARL_IO_TX_GENRL_CFG_TX_VALID_OUTPUT_EN = 0x80000000 + + // FIFO_CFG: Parallel IO FIFO configuration register. + // Position of TX_FIFO_SRST field. + PARL_IO_FIFO_CFG_TX_FIFO_SRST_Pos = 0x1e + // Bit mask of TX_FIFO_SRST field. + PARL_IO_FIFO_CFG_TX_FIFO_SRST_Msk = 0x40000000 + // Bit TX_FIFO_SRST. + PARL_IO_FIFO_CFG_TX_FIFO_SRST = 0x40000000 + // Position of RX_FIFO_SRST field. + PARL_IO_FIFO_CFG_RX_FIFO_SRST_Pos = 0x1f + // Bit mask of RX_FIFO_SRST field. + PARL_IO_FIFO_CFG_RX_FIFO_SRST_Msk = 0x80000000 + // Bit RX_FIFO_SRST. + PARL_IO_FIFO_CFG_RX_FIFO_SRST = 0x80000000 + + // REG_UPDATE: Parallel IO FIFO configuration register. + // Position of RX_REG_UPDATE field. + PARL_IO_REG_UPDATE_RX_REG_UPDATE_Pos = 0x1f + // Bit mask of RX_REG_UPDATE field. + PARL_IO_REG_UPDATE_RX_REG_UPDATE_Msk = 0x80000000 + // Bit RX_REG_UPDATE. + PARL_IO_REG_UPDATE_RX_REG_UPDATE = 0x80000000 + + // ST: Parallel IO module status register0. + // Position of TX_READY field. + PARL_IO_ST_TX_READY_Pos = 0x1f + // Bit mask of TX_READY field. + PARL_IO_ST_TX_READY_Msk = 0x80000000 + // Bit TX_READY. + PARL_IO_ST_TX_READY = 0x80000000 + + // INT_ENA: Parallel IO interrupt enable singal configuration register. + // Position of TX_FIFO_REMPTY_INT_ENA field. + PARL_IO_INT_ENA_TX_FIFO_REMPTY_INT_ENA_Pos = 0x0 + // Bit mask of TX_FIFO_REMPTY_INT_ENA field. + PARL_IO_INT_ENA_TX_FIFO_REMPTY_INT_ENA_Msk = 0x1 + // Bit TX_FIFO_REMPTY_INT_ENA. + PARL_IO_INT_ENA_TX_FIFO_REMPTY_INT_ENA = 0x1 + // Position of RX_FIFO_WOVF_INT_ENA field. + PARL_IO_INT_ENA_RX_FIFO_WOVF_INT_ENA_Pos = 0x1 + // Bit mask of RX_FIFO_WOVF_INT_ENA field. + PARL_IO_INT_ENA_RX_FIFO_WOVF_INT_ENA_Msk = 0x2 + // Bit RX_FIFO_WOVF_INT_ENA. + PARL_IO_INT_ENA_RX_FIFO_WOVF_INT_ENA = 0x2 + // Position of TX_EOF_INT_ENA field. + PARL_IO_INT_ENA_TX_EOF_INT_ENA_Pos = 0x2 + // Bit mask of TX_EOF_INT_ENA field. + PARL_IO_INT_ENA_TX_EOF_INT_ENA_Msk = 0x4 + // Bit TX_EOF_INT_ENA. + PARL_IO_INT_ENA_TX_EOF_INT_ENA = 0x4 + + // INT_RAW: Parallel IO interrupt raw singal status register. + // Position of TX_FIFO_REMPTY_INT_RAW field. + PARL_IO_INT_RAW_TX_FIFO_REMPTY_INT_RAW_Pos = 0x0 + // Bit mask of TX_FIFO_REMPTY_INT_RAW field. + PARL_IO_INT_RAW_TX_FIFO_REMPTY_INT_RAW_Msk = 0x1 + // Bit TX_FIFO_REMPTY_INT_RAW. + PARL_IO_INT_RAW_TX_FIFO_REMPTY_INT_RAW = 0x1 + // Position of RX_FIFO_WOVF_INT_RAW field. + PARL_IO_INT_RAW_RX_FIFO_WOVF_INT_RAW_Pos = 0x1 + // Bit mask of RX_FIFO_WOVF_INT_RAW field. + PARL_IO_INT_RAW_RX_FIFO_WOVF_INT_RAW_Msk = 0x2 + // Bit RX_FIFO_WOVF_INT_RAW. + PARL_IO_INT_RAW_RX_FIFO_WOVF_INT_RAW = 0x2 + // Position of TX_EOF_INT_RAW field. + PARL_IO_INT_RAW_TX_EOF_INT_RAW_Pos = 0x2 + // Bit mask of TX_EOF_INT_RAW field. + PARL_IO_INT_RAW_TX_EOF_INT_RAW_Msk = 0x4 + // Bit TX_EOF_INT_RAW. + PARL_IO_INT_RAW_TX_EOF_INT_RAW = 0x4 + + // INT_ST: Parallel IO interrupt singal status register. + // Position of TX_FIFO_REMPTY_INT_ST field. + PARL_IO_INT_ST_TX_FIFO_REMPTY_INT_ST_Pos = 0x0 + // Bit mask of TX_FIFO_REMPTY_INT_ST field. + PARL_IO_INT_ST_TX_FIFO_REMPTY_INT_ST_Msk = 0x1 + // Bit TX_FIFO_REMPTY_INT_ST. + PARL_IO_INT_ST_TX_FIFO_REMPTY_INT_ST = 0x1 + // Position of RX_FIFO_WOVF_INT_ST field. + PARL_IO_INT_ST_RX_FIFO_WOVF_INT_ST_Pos = 0x1 + // Bit mask of RX_FIFO_WOVF_INT_ST field. + PARL_IO_INT_ST_RX_FIFO_WOVF_INT_ST_Msk = 0x2 + // Bit RX_FIFO_WOVF_INT_ST. + PARL_IO_INT_ST_RX_FIFO_WOVF_INT_ST = 0x2 + // Position of TX_EOF_INT_ST field. + PARL_IO_INT_ST_TX_EOF_INT_ST_Pos = 0x2 + // Bit mask of TX_EOF_INT_ST field. + PARL_IO_INT_ST_TX_EOF_INT_ST_Msk = 0x4 + // Bit TX_EOF_INT_ST. + PARL_IO_INT_ST_TX_EOF_INT_ST = 0x4 + + // INT_CLR: Parallel IO interrupt clear singal configuration register. + // Position of TX_FIFO_REMPTY_INT_CLR field. + PARL_IO_INT_CLR_TX_FIFO_REMPTY_INT_CLR_Pos = 0x0 + // Bit mask of TX_FIFO_REMPTY_INT_CLR field. + PARL_IO_INT_CLR_TX_FIFO_REMPTY_INT_CLR_Msk = 0x1 + // Bit TX_FIFO_REMPTY_INT_CLR. + PARL_IO_INT_CLR_TX_FIFO_REMPTY_INT_CLR = 0x1 + // Position of RX_FIFO_WOVF_INT_CLR field. + PARL_IO_INT_CLR_RX_FIFO_WOVF_INT_CLR_Pos = 0x1 + // Bit mask of RX_FIFO_WOVF_INT_CLR field. + PARL_IO_INT_CLR_RX_FIFO_WOVF_INT_CLR_Msk = 0x2 + // Bit RX_FIFO_WOVF_INT_CLR. + PARL_IO_INT_CLR_RX_FIFO_WOVF_INT_CLR = 0x2 + // Position of TX_EOF_INT_CLR field. + PARL_IO_INT_CLR_TX_EOF_INT_CLR_Pos = 0x2 + // Bit mask of TX_EOF_INT_CLR field. + PARL_IO_INT_CLR_TX_EOF_INT_CLR_Msk = 0x4 + // Bit TX_EOF_INT_CLR. + PARL_IO_INT_CLR_TX_EOF_INT_CLR = 0x4 + + // RX_ST0: Parallel IO RX status register0 + // Position of RX_CNT field. + PARL_IO_RX_ST0_RX_CNT_Pos = 0x9 + // Bit mask of RX_CNT field. + PARL_IO_RX_ST0_RX_CNT_Msk = 0x1e00 + // Position of RX_FIFO_WR_BIT_CNT field. + PARL_IO_RX_ST0_RX_FIFO_WR_BIT_CNT_Pos = 0xd + // Bit mask of RX_FIFO_WR_BIT_CNT field. + PARL_IO_RX_ST0_RX_FIFO_WR_BIT_CNT_Msk = 0xffffe000 + + // RX_ST1: Parallel IO RX status register1 + // Position of RX_FIFO_RD_BIT_CNT field. + PARL_IO_RX_ST1_RX_FIFO_RD_BIT_CNT_Pos = 0xd + // Bit mask of RX_FIFO_RD_BIT_CNT field. + PARL_IO_RX_ST1_RX_FIFO_RD_BIT_CNT_Msk = 0xffffe000 + + // TX_ST0: Parallel IO TX status register0 + // Position of TX_CNT field. + PARL_IO_TX_ST0_TX_CNT_Pos = 0x6 + // Bit mask of TX_CNT field. + PARL_IO_TX_ST0_TX_CNT_Msk = 0x1fc0 + // Position of TX_FIFO_RD_BIT_CNT field. + PARL_IO_TX_ST0_TX_FIFO_RD_BIT_CNT_Pos = 0xd + // Bit mask of TX_FIFO_RD_BIT_CNT field. + PARL_IO_TX_ST0_TX_FIFO_RD_BIT_CNT_Msk = 0xffffe000 + + // RX_CLK_CFG: Parallel IO RX clk configuration register + // Position of RX_CLK_I_INV field. + PARL_IO_RX_CLK_CFG_RX_CLK_I_INV_Pos = 0x1e + // Bit mask of RX_CLK_I_INV field. + PARL_IO_RX_CLK_CFG_RX_CLK_I_INV_Msk = 0x40000000 + // Bit RX_CLK_I_INV. + PARL_IO_RX_CLK_CFG_RX_CLK_I_INV = 0x40000000 + // Position of RX_CLK_O_INV field. + PARL_IO_RX_CLK_CFG_RX_CLK_O_INV_Pos = 0x1f + // Bit mask of RX_CLK_O_INV field. + PARL_IO_RX_CLK_CFG_RX_CLK_O_INV_Msk = 0x80000000 + // Bit RX_CLK_O_INV. + PARL_IO_RX_CLK_CFG_RX_CLK_O_INV = 0x80000000 + + // TX_CLK_CFG: Parallel IO TX clk configuration register + // Position of TX_CLK_I_INV field. + PARL_IO_TX_CLK_CFG_TX_CLK_I_INV_Pos = 0x1e + // Bit mask of TX_CLK_I_INV field. + PARL_IO_TX_CLK_CFG_TX_CLK_I_INV_Msk = 0x40000000 + // Bit TX_CLK_I_INV. + PARL_IO_TX_CLK_CFG_TX_CLK_I_INV = 0x40000000 + // Position of TX_CLK_O_INV field. + PARL_IO_TX_CLK_CFG_TX_CLK_O_INV_Pos = 0x1f + // Bit mask of TX_CLK_O_INV field. + PARL_IO_TX_CLK_CFG_TX_CLK_O_INV_Msk = 0x80000000 + // Bit TX_CLK_O_INV. + PARL_IO_TX_CLK_CFG_TX_CLK_O_INV = 0x80000000 + + // CLK: Parallel IO clk configuration register + // Position of EN field. + PARL_IO_CLK_EN_Pos = 0x1f + // Bit mask of EN field. + PARL_IO_CLK_EN_Msk = 0x80000000 + // Bit EN. + PARL_IO_CLK_EN = 0x80000000 + + // VERSION: Version register. + // Position of DATE field. + PARL_IO_VERSION_DATE_Pos = 0x0 + // Bit mask of DATE field. + PARL_IO_VERSION_DATE_Msk = 0xfffffff +) + +// Constants for PAU: PAU Peripheral +const ( + // REGDMA_CONF: Peri backup control register + // Position of FLOW_ERR field. + PAU_REGDMA_CONF_FLOW_ERR_Pos = 0x0 + // Bit mask of FLOW_ERR field. + PAU_REGDMA_CONF_FLOW_ERR_Msk = 0x7 + // Position of START field. + PAU_REGDMA_CONF_START_Pos = 0x3 + // Bit mask of START field. + PAU_REGDMA_CONF_START_Msk = 0x8 + // Bit START. + PAU_REGDMA_CONF_START = 0x8 + // Position of TO_MEM field. + PAU_REGDMA_CONF_TO_MEM_Pos = 0x4 + // Bit mask of TO_MEM field. + PAU_REGDMA_CONF_TO_MEM_Msk = 0x10 + // Bit TO_MEM. + PAU_REGDMA_CONF_TO_MEM = 0x10 + // Position of LINK_SEL field. + PAU_REGDMA_CONF_LINK_SEL_Pos = 0x5 + // Bit mask of LINK_SEL field. + PAU_REGDMA_CONF_LINK_SEL_Msk = 0x60 + // Position of START_MAC field. + PAU_REGDMA_CONF_START_MAC_Pos = 0x7 + // Bit mask of START_MAC field. + PAU_REGDMA_CONF_START_MAC_Msk = 0x80 + // Bit START_MAC. + PAU_REGDMA_CONF_START_MAC = 0x80 + // Position of TO_MEM_MAC field. + PAU_REGDMA_CONF_TO_MEM_MAC_Pos = 0x8 + // Bit mask of TO_MEM_MAC field. + PAU_REGDMA_CONF_TO_MEM_MAC_Msk = 0x100 + // Bit TO_MEM_MAC. + PAU_REGDMA_CONF_TO_MEM_MAC = 0x100 + // Position of SEL_MAC field. + PAU_REGDMA_CONF_SEL_MAC_Pos = 0x9 + // Bit mask of SEL_MAC field. + PAU_REGDMA_CONF_SEL_MAC_Msk = 0x200 + // Bit SEL_MAC. + PAU_REGDMA_CONF_SEL_MAC = 0x200 + + // REGDMA_CLK_CONF: Clock control register + // Position of CLK_EN field. + PAU_REGDMA_CLK_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + PAU_REGDMA_CLK_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + PAU_REGDMA_CLK_CONF_CLK_EN = 0x1 + + // REGDMA_ETM_CTRL: ETM start ctrl reg + // Position of ETM_START_0 field. + PAU_REGDMA_ETM_CTRL_ETM_START_0_Pos = 0x0 + // Bit mask of ETM_START_0 field. + PAU_REGDMA_ETM_CTRL_ETM_START_0_Msk = 0x1 + // Bit ETM_START_0. + PAU_REGDMA_ETM_CTRL_ETM_START_0 = 0x1 + // Position of ETM_START_1 field. + PAU_REGDMA_ETM_CTRL_ETM_START_1_Pos = 0x1 + // Bit mask of ETM_START_1 field. + PAU_REGDMA_ETM_CTRL_ETM_START_1_Msk = 0x2 + // Bit ETM_START_1. + PAU_REGDMA_ETM_CTRL_ETM_START_1 = 0x2 + // Position of ETM_START_2 field. + PAU_REGDMA_ETM_CTRL_ETM_START_2_Pos = 0x2 + // Bit mask of ETM_START_2 field. + PAU_REGDMA_ETM_CTRL_ETM_START_2_Msk = 0x4 + // Bit ETM_START_2. + PAU_REGDMA_ETM_CTRL_ETM_START_2 = 0x4 + // Position of ETM_START_3 field. + PAU_REGDMA_ETM_CTRL_ETM_START_3_Pos = 0x3 + // Bit mask of ETM_START_3 field. + PAU_REGDMA_ETM_CTRL_ETM_START_3_Msk = 0x8 + // Bit ETM_START_3. + PAU_REGDMA_ETM_CTRL_ETM_START_3 = 0x8 + + // REGDMA_LINK_0_ADDR: link_0_addr + // Position of LINK_ADDR_0 field. + PAU_REGDMA_LINK_0_ADDR_LINK_ADDR_0_Pos = 0x0 + // Bit mask of LINK_ADDR_0 field. + PAU_REGDMA_LINK_0_ADDR_LINK_ADDR_0_Msk = 0xffffffff + + // REGDMA_LINK_1_ADDR: Link_1_addr + // Position of LINK_ADDR_1 field. + PAU_REGDMA_LINK_1_ADDR_LINK_ADDR_1_Pos = 0x0 + // Bit mask of LINK_ADDR_1 field. + PAU_REGDMA_LINK_1_ADDR_LINK_ADDR_1_Msk = 0xffffffff + + // REGDMA_LINK_2_ADDR: Link_2_addr + // Position of LINK_ADDR_2 field. + PAU_REGDMA_LINK_2_ADDR_LINK_ADDR_2_Pos = 0x0 + // Bit mask of LINK_ADDR_2 field. + PAU_REGDMA_LINK_2_ADDR_LINK_ADDR_2_Msk = 0xffffffff + + // REGDMA_LINK_3_ADDR: Link_3_addr + // Position of LINK_ADDR_3 field. + PAU_REGDMA_LINK_3_ADDR_LINK_ADDR_3_Pos = 0x0 + // Bit mask of LINK_ADDR_3 field. + PAU_REGDMA_LINK_3_ADDR_LINK_ADDR_3_Msk = 0xffffffff + + // REGDMA_LINK_MAC_ADDR: Link_mac_addr + // Position of LINK_ADDR_MAC field. + PAU_REGDMA_LINK_MAC_ADDR_LINK_ADDR_MAC_Pos = 0x0 + // Bit mask of LINK_ADDR_MAC field. + PAU_REGDMA_LINK_MAC_ADDR_LINK_ADDR_MAC_Msk = 0xffffffff + + // REGDMA_CURRENT_LINK_ADDR: current link addr + // Position of CURRENT_LINK_ADDR field. + PAU_REGDMA_CURRENT_LINK_ADDR_CURRENT_LINK_ADDR_Pos = 0x0 + // Bit mask of CURRENT_LINK_ADDR field. + PAU_REGDMA_CURRENT_LINK_ADDR_CURRENT_LINK_ADDR_Msk = 0xffffffff + + // REGDMA_BACKUP_ADDR: Backup addr + // Position of BACKUP_ADDR field. + PAU_REGDMA_BACKUP_ADDR_BACKUP_ADDR_Pos = 0x0 + // Bit mask of BACKUP_ADDR field. + PAU_REGDMA_BACKUP_ADDR_BACKUP_ADDR_Msk = 0xffffffff + + // REGDMA_MEM_ADDR: mem addr + // Position of MEM_ADDR field. + PAU_REGDMA_MEM_ADDR_MEM_ADDR_Pos = 0x0 + // Bit mask of MEM_ADDR field. + PAU_REGDMA_MEM_ADDR_MEM_ADDR_Msk = 0xffffffff + + // REGDMA_BKP_CONF: backup config + // Position of READ_INTERVAL field. + PAU_REGDMA_BKP_CONF_READ_INTERVAL_Pos = 0x0 + // Bit mask of READ_INTERVAL field. + PAU_REGDMA_BKP_CONF_READ_INTERVAL_Msk = 0x7f + // Position of LINK_TOUT_THRES field. + PAU_REGDMA_BKP_CONF_LINK_TOUT_THRES_Pos = 0x7 + // Bit mask of LINK_TOUT_THRES field. + PAU_REGDMA_BKP_CONF_LINK_TOUT_THRES_Msk = 0x1ff80 + // Position of BURST_LIMIT field. + PAU_REGDMA_BKP_CONF_BURST_LIMIT_Pos = 0x11 + // Bit mask of BURST_LIMIT field. + PAU_REGDMA_BKP_CONF_BURST_LIMIT_Msk = 0x3e0000 + // Position of BACKUP_TOUT_THRES field. + PAU_REGDMA_BKP_CONF_BACKUP_TOUT_THRES_Pos = 0x16 + // Bit mask of BACKUP_TOUT_THRES field. + PAU_REGDMA_BKP_CONF_BACKUP_TOUT_THRES_Msk = 0xffc00000 + + // RETENTION_LINK_BASE: retention dma link base + // Position of LINK_BASE_ADDR field. + PAU_RETENTION_LINK_BASE_LINK_BASE_ADDR_Pos = 0x0 + // Bit mask of LINK_BASE_ADDR field. + PAU_RETENTION_LINK_BASE_LINK_BASE_ADDR_Msk = 0x7ffffff + + // RETENTION_CFG: retention_cfg + // Position of RET_INV_CFG field. + PAU_RETENTION_CFG_RET_INV_CFG_Pos = 0x0 + // Bit mask of RET_INV_CFG field. + PAU_RETENTION_CFG_RET_INV_CFG_Msk = 0xffffffff + + // INT_ENA: Read only register for error and done + // Position of DONE_INT_ENA field. + PAU_INT_ENA_DONE_INT_ENA_Pos = 0x0 + // Bit mask of DONE_INT_ENA field. + PAU_INT_ENA_DONE_INT_ENA_Msk = 0x1 + // Bit DONE_INT_ENA. + PAU_INT_ENA_DONE_INT_ENA = 0x1 + // Position of ERROR_INT_ENA field. + PAU_INT_ENA_ERROR_INT_ENA_Pos = 0x1 + // Bit mask of ERROR_INT_ENA field. + PAU_INT_ENA_ERROR_INT_ENA_Msk = 0x2 + // Bit ERROR_INT_ENA. + PAU_INT_ENA_ERROR_INT_ENA = 0x2 + + // INT_RAW: Read only register for error and done + // Position of DONE_INT_RAW field. + PAU_INT_RAW_DONE_INT_RAW_Pos = 0x0 + // Bit mask of DONE_INT_RAW field. + PAU_INT_RAW_DONE_INT_RAW_Msk = 0x1 + // Bit DONE_INT_RAW. + PAU_INT_RAW_DONE_INT_RAW = 0x1 + // Position of ERROR_INT_RAW field. + PAU_INT_RAW_ERROR_INT_RAW_Pos = 0x1 + // Bit mask of ERROR_INT_RAW field. + PAU_INT_RAW_ERROR_INT_RAW_Msk = 0x2 + // Bit ERROR_INT_RAW. + PAU_INT_RAW_ERROR_INT_RAW = 0x2 + + // INT_CLR: Read only register for error and done + // Position of DONE_INT_CLR field. + PAU_INT_CLR_DONE_INT_CLR_Pos = 0x0 + // Bit mask of DONE_INT_CLR field. + PAU_INT_CLR_DONE_INT_CLR_Msk = 0x1 + // Bit DONE_INT_CLR. + PAU_INT_CLR_DONE_INT_CLR = 0x1 + // Position of ERROR_INT_CLR field. + PAU_INT_CLR_ERROR_INT_CLR_Pos = 0x1 + // Bit mask of ERROR_INT_CLR field. + PAU_INT_CLR_ERROR_INT_CLR_Msk = 0x2 + // Bit ERROR_INT_CLR. + PAU_INT_CLR_ERROR_INT_CLR = 0x2 + + // INT_ST: Read only register for error and done + // Position of DONE_INT_ST field. + PAU_INT_ST_DONE_INT_ST_Pos = 0x0 + // Bit mask of DONE_INT_ST field. + PAU_INT_ST_DONE_INT_ST_Msk = 0x1 + // Bit DONE_INT_ST. + PAU_INT_ST_DONE_INT_ST = 0x1 + // Position of ERROR_INT_ST field. + PAU_INT_ST_ERROR_INT_ST_Pos = 0x1 + // Bit mask of ERROR_INT_ST field. + PAU_INT_ST_ERROR_INT_ST_Msk = 0x2 + // Bit ERROR_INT_ST. + PAU_INT_ST_ERROR_INT_ST = 0x2 + + // DATE: Date register. + // Position of DATE field. + PAU_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PAU_DATE_DATE_Msk = 0xfffffff +) + +// Constants for PCNT: Pulse Count Controller +const ( + // U0_CONF0: Configuration register 0 for unit %s + // Position of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Pos = 0x0 + // Bit mask of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Msk = 0x3ff + // Position of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Pos = 0xa + // Bit mask of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Msk = 0x400 + // Bit FILTER_EN. + PCNT_U_CONF0_FILTER_EN = 0x400 + // Position of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Pos = 0xb + // Bit mask of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Msk = 0x800 + // Bit THR_ZERO_EN. + PCNT_U_CONF0_THR_ZERO_EN = 0x800 + // Position of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Pos = 0xc + // Bit mask of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Msk = 0x1000 + // Bit THR_H_LIM_EN. + PCNT_U_CONF0_THR_H_LIM_EN = 0x1000 + // Position of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Pos = 0xd + // Bit mask of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Msk = 0x2000 + // Bit THR_L_LIM_EN. + PCNT_U_CONF0_THR_L_LIM_EN = 0x2000 + // Position of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Pos = 0xe + // Bit mask of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Msk = 0x4000 + // Bit THR_THRES0_EN. + PCNT_U_CONF0_THR_THRES0_EN = 0x4000 + // Position of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Pos = 0xf + // Bit mask of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Msk = 0x8000 + // Bit THR_THRES1_EN. + PCNT_U_CONF0_THR_THRES1_EN = 0x8000 + // Position of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Pos = 0x10 + // Bit mask of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Msk = 0x30000 + // Position of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Pos = 0x12 + // Bit mask of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Msk = 0xc0000 + // Position of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Pos = 0x14 + // Bit mask of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Msk = 0x300000 + // Position of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Pos = 0x16 + // Bit mask of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Msk = 0xc00000 + // Position of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Pos = 0x18 + // Bit mask of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Msk = 0x3000000 + // Position of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Pos = 0x1a + // Bit mask of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Msk = 0xc000000 + // Position of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Pos = 0x1c + // Bit mask of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Msk = 0x30000000 + // Position of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Pos = 0x1e + // Bit mask of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Msk = 0xc0000000 + + // U0_CONF1: Configuration register 1 for unit %s + // Position of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Pos = 0x0 + // Bit mask of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Msk = 0xffff + // Position of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Pos = 0x10 + // Bit mask of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Msk = 0xffff0000 + + // U0_CONF2: Configuration register 2 for unit %s + // Position of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Pos = 0x0 + // Bit mask of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Msk = 0xffff + // Position of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Pos = 0x10 + // Bit mask of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Msk = 0xffff0000 + + // U0_CNT: Counter value for unit %s + // Position of CNT field. + PCNT_U_CNT_CNT_Pos = 0x0 + // Bit mask of CNT field. + PCNT_U_CNT_CNT_Msk = 0xffff + + // INT_RAW: Interrupt raw status register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_RAW_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_RAW_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_RAW_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_RAW_CNT_THR_EVENT_U3 = 0x8 + + // INT_ST: Interrupt status register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ST_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ST_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ST_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ST_CNT_THR_EVENT_U3 = 0x8 + + // INT_ENA: Interrupt enable register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ENA_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ENA_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ENA_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ENA_CNT_THR_EVENT_U3 = 0x8 + + // INT_CLR: Interrupt clear register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_CLR_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_CLR_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_CLR_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_CLR_CNT_THR_EVENT_U3 = 0x8 + + // U0_STATUS: PNCT UNIT%s status register + // Position of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Pos = 0x0 + // Bit mask of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Msk = 0x3 + // Position of THRES1 field. + PCNT_U_STATUS_THRES1_Pos = 0x2 + // Bit mask of THRES1 field. + PCNT_U_STATUS_THRES1_Msk = 0x4 + // Bit THRES1. + PCNT_U_STATUS_THRES1 = 0x4 + // Position of THRES0 field. + PCNT_U_STATUS_THRES0_Pos = 0x3 + // Bit mask of THRES0 field. + PCNT_U_STATUS_THRES0_Msk = 0x8 + // Bit THRES0. + PCNT_U_STATUS_THRES0 = 0x8 + // Position of L_LIM field. + PCNT_U_STATUS_L_LIM_Pos = 0x4 + // Bit mask of L_LIM field. + PCNT_U_STATUS_L_LIM_Msk = 0x10 + // Bit L_LIM. + PCNT_U_STATUS_L_LIM = 0x10 + // Position of H_LIM field. + PCNT_U_STATUS_H_LIM_Pos = 0x5 + // Bit mask of H_LIM field. + PCNT_U_STATUS_H_LIM_Msk = 0x20 + // Bit H_LIM. + PCNT_U_STATUS_H_LIM = 0x20 + // Position of ZERO field. + PCNT_U_STATUS_ZERO_Pos = 0x6 + // Bit mask of ZERO field. + PCNT_U_STATUS_ZERO_Msk = 0x40 + // Bit ZERO. + PCNT_U_STATUS_ZERO = 0x40 + + // CTRL: Control register for all counters + // Position of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Pos = 0x0 + // Bit mask of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Msk = 0x1 + // Bit CNT_RST_U0. + PCNT_CTRL_CNT_RST_U0 = 0x1 + // Position of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Pos = 0x1 + // Bit mask of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Msk = 0x2 + // Bit CNT_PAUSE_U0. + PCNT_CTRL_CNT_PAUSE_U0 = 0x2 + // Position of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Pos = 0x2 + // Bit mask of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Msk = 0x4 + // Bit CNT_RST_U1. + PCNT_CTRL_CNT_RST_U1 = 0x4 + // Position of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Pos = 0x3 + // Bit mask of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Msk = 0x8 + // Bit CNT_PAUSE_U1. + PCNT_CTRL_CNT_PAUSE_U1 = 0x8 + // Position of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Pos = 0x4 + // Bit mask of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Msk = 0x10 + // Bit CNT_RST_U2. + PCNT_CTRL_CNT_RST_U2 = 0x10 + // Position of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Pos = 0x5 + // Bit mask of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Msk = 0x20 + // Bit CNT_PAUSE_U2. + PCNT_CTRL_CNT_PAUSE_U2 = 0x20 + // Position of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Pos = 0x6 + // Bit mask of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Msk = 0x40 + // Bit CNT_RST_U3. + PCNT_CTRL_CNT_RST_U3 = 0x40 + // Position of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Pos = 0x7 + // Bit mask of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Msk = 0x80 + // Bit CNT_PAUSE_U3. + PCNT_CTRL_CNT_PAUSE_U3 = 0x80 + // Position of CLK_EN field. + PCNT_CTRL_CLK_EN_Pos = 0x10 + // Bit mask of CLK_EN field. + PCNT_CTRL_CLK_EN_Msk = 0x10000 + // Bit CLK_EN. + PCNT_CTRL_CLK_EN = 0x10000 + + // DATE: PCNT version control register + // Position of DATE field. + PCNT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PCNT_DATE_DATE_Msk = 0xffffffff +) + +// Constants for PCR: PCR Peripheral +const ( + // UART0_CONF: UART0 configuration register + // Position of UART0_CLK_EN field. + PCR_UART0_CONF_UART0_CLK_EN_Pos = 0x0 + // Bit mask of UART0_CLK_EN field. + PCR_UART0_CONF_UART0_CLK_EN_Msk = 0x1 + // Bit UART0_CLK_EN. + PCR_UART0_CONF_UART0_CLK_EN = 0x1 + // Position of UART0_RST_EN field. + PCR_UART0_CONF_UART0_RST_EN_Pos = 0x1 + // Bit mask of UART0_RST_EN field. + PCR_UART0_CONF_UART0_RST_EN_Msk = 0x2 + // Bit UART0_RST_EN. + PCR_UART0_CONF_UART0_RST_EN = 0x2 + // Position of UART0_READY field. + PCR_UART0_CONF_UART0_READY_Pos = 0x2 + // Bit mask of UART0_READY field. + PCR_UART0_CONF_UART0_READY_Msk = 0x4 + // Bit UART0_READY. + PCR_UART0_CONF_UART0_READY = 0x4 + + // UART0_SCLK_CONF: UART0_SCLK configuration register + // Position of UART0_SCLK_DIV_A field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_A_Pos = 0x0 + // Bit mask of UART0_SCLK_DIV_A field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_A_Msk = 0x3f + // Position of UART0_SCLK_DIV_B field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_B_Pos = 0x6 + // Bit mask of UART0_SCLK_DIV_B field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_B_Msk = 0xfc0 + // Position of UART0_SCLK_DIV_NUM field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of UART0_SCLK_DIV_NUM field. + PCR_UART0_SCLK_CONF_UART0_SCLK_DIV_NUM_Msk = 0xff000 + // Position of UART0_SCLK_SEL field. + PCR_UART0_SCLK_CONF_UART0_SCLK_SEL_Pos = 0x14 + // Bit mask of UART0_SCLK_SEL field. + PCR_UART0_SCLK_CONF_UART0_SCLK_SEL_Msk = 0x300000 + // Position of UART0_SCLK_EN field. + PCR_UART0_SCLK_CONF_UART0_SCLK_EN_Pos = 0x16 + // Bit mask of UART0_SCLK_EN field. + PCR_UART0_SCLK_CONF_UART0_SCLK_EN_Msk = 0x400000 + // Bit UART0_SCLK_EN. + PCR_UART0_SCLK_CONF_UART0_SCLK_EN = 0x400000 + + // UART0_PD_CTRL: UART0 power control register + // Position of UART0_MEM_FORCE_PU field. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of UART0_MEM_FORCE_PU field. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PU_Msk = 0x2 + // Bit UART0_MEM_FORCE_PU. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PU = 0x2 + // Position of UART0_MEM_FORCE_PD field. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of UART0_MEM_FORCE_PD field. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PD_Msk = 0x4 + // Bit UART0_MEM_FORCE_PD. + PCR_UART0_PD_CTRL_UART0_MEM_FORCE_PD = 0x4 + + // UART1_CONF: UART1 configuration register + // Position of UART1_CLK_EN field. + PCR_UART1_CONF_UART1_CLK_EN_Pos = 0x0 + // Bit mask of UART1_CLK_EN field. + PCR_UART1_CONF_UART1_CLK_EN_Msk = 0x1 + // Bit UART1_CLK_EN. + PCR_UART1_CONF_UART1_CLK_EN = 0x1 + // Position of UART1_RST_EN field. + PCR_UART1_CONF_UART1_RST_EN_Pos = 0x1 + // Bit mask of UART1_RST_EN field. + PCR_UART1_CONF_UART1_RST_EN_Msk = 0x2 + // Bit UART1_RST_EN. + PCR_UART1_CONF_UART1_RST_EN = 0x2 + // Position of UART1_READY field. + PCR_UART1_CONF_UART1_READY_Pos = 0x2 + // Bit mask of UART1_READY field. + PCR_UART1_CONF_UART1_READY_Msk = 0x4 + // Bit UART1_READY. + PCR_UART1_CONF_UART1_READY = 0x4 + + // UART1_SCLK_CONF: UART1_SCLK configuration register + // Position of UART1_SCLK_DIV_A field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_A_Pos = 0x0 + // Bit mask of UART1_SCLK_DIV_A field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_A_Msk = 0x3f + // Position of UART1_SCLK_DIV_B field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_B_Pos = 0x6 + // Bit mask of UART1_SCLK_DIV_B field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_B_Msk = 0xfc0 + // Position of UART1_SCLK_DIV_NUM field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of UART1_SCLK_DIV_NUM field. + PCR_UART1_SCLK_CONF_UART1_SCLK_DIV_NUM_Msk = 0xff000 + // Position of UART1_SCLK_SEL field. + PCR_UART1_SCLK_CONF_UART1_SCLK_SEL_Pos = 0x14 + // Bit mask of UART1_SCLK_SEL field. + PCR_UART1_SCLK_CONF_UART1_SCLK_SEL_Msk = 0x300000 + // Position of UART1_SCLK_EN field. + PCR_UART1_SCLK_CONF_UART1_SCLK_EN_Pos = 0x16 + // Bit mask of UART1_SCLK_EN field. + PCR_UART1_SCLK_CONF_UART1_SCLK_EN_Msk = 0x400000 + // Bit UART1_SCLK_EN. + PCR_UART1_SCLK_CONF_UART1_SCLK_EN = 0x400000 + + // UART1_PD_CTRL: UART1 power control register + // Position of UART1_MEM_FORCE_PU field. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of UART1_MEM_FORCE_PU field. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PU_Msk = 0x2 + // Bit UART1_MEM_FORCE_PU. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PU = 0x2 + // Position of UART1_MEM_FORCE_PD field. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of UART1_MEM_FORCE_PD field. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PD_Msk = 0x4 + // Bit UART1_MEM_FORCE_PD. + PCR_UART1_PD_CTRL_UART1_MEM_FORCE_PD = 0x4 + + // MSPI_CONF: MSPI configuration register + // Position of MSPI_CLK_EN field. + PCR_MSPI_CONF_MSPI_CLK_EN_Pos = 0x0 + // Bit mask of MSPI_CLK_EN field. + PCR_MSPI_CONF_MSPI_CLK_EN_Msk = 0x1 + // Bit MSPI_CLK_EN. + PCR_MSPI_CONF_MSPI_CLK_EN = 0x1 + // Position of MSPI_RST_EN field. + PCR_MSPI_CONF_MSPI_RST_EN_Pos = 0x1 + // Bit mask of MSPI_RST_EN field. + PCR_MSPI_CONF_MSPI_RST_EN_Msk = 0x2 + // Bit MSPI_RST_EN. + PCR_MSPI_CONF_MSPI_RST_EN = 0x2 + // Position of MSPI_PLL_CLK_EN field. + PCR_MSPI_CONF_MSPI_PLL_CLK_EN_Pos = 0x2 + // Bit mask of MSPI_PLL_CLK_EN field. + PCR_MSPI_CONF_MSPI_PLL_CLK_EN_Msk = 0x4 + // Bit MSPI_PLL_CLK_EN. + PCR_MSPI_CONF_MSPI_PLL_CLK_EN = 0x4 + // Position of MSPI_CLK_SEL field. + PCR_MSPI_CONF_MSPI_CLK_SEL_Pos = 0x3 + // Bit mask of MSPI_CLK_SEL field. + PCR_MSPI_CONF_MSPI_CLK_SEL_Msk = 0x18 + // Position of MSPI_READY field. + PCR_MSPI_CONF_MSPI_READY_Pos = 0x5 + // Bit mask of MSPI_READY field. + PCR_MSPI_CONF_MSPI_READY_Msk = 0x20 + // Bit MSPI_READY. + PCR_MSPI_CONF_MSPI_READY = 0x20 + + // MSPI_CLK_CONF: MSPI_CLK configuration register + // Position of MSPI_FAST_DIV_NUM field. + PCR_MSPI_CLK_CONF_MSPI_FAST_DIV_NUM_Pos = 0x0 + // Bit mask of MSPI_FAST_DIV_NUM field. + PCR_MSPI_CLK_CONF_MSPI_FAST_DIV_NUM_Msk = 0xff + + // I2C0_CONF: I2C configuration register + // Position of I2C0_CLK_EN field. + PCR_I2C0_CONF_I2C0_CLK_EN_Pos = 0x0 + // Bit mask of I2C0_CLK_EN field. + PCR_I2C0_CONF_I2C0_CLK_EN_Msk = 0x1 + // Bit I2C0_CLK_EN. + PCR_I2C0_CONF_I2C0_CLK_EN = 0x1 + // Position of I2C0_RST_EN field. + PCR_I2C0_CONF_I2C0_RST_EN_Pos = 0x1 + // Bit mask of I2C0_RST_EN field. + PCR_I2C0_CONF_I2C0_RST_EN_Msk = 0x2 + // Bit I2C0_RST_EN. + PCR_I2C0_CONF_I2C0_RST_EN = 0x2 + // Position of I2C0_READY field. + PCR_I2C0_CONF_I2C0_READY_Pos = 0x2 + // Bit mask of I2C0_READY field. + PCR_I2C0_CONF_I2C0_READY_Msk = 0x4 + // Bit I2C0_READY. + PCR_I2C0_CONF_I2C0_READY = 0x4 + + // I2C0_SCLK_CONF: I2C_SCLK configuration register + // Position of I2C0_SCLK_DIV_A field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_DIV_A_Pos = 0x0 + // Bit mask of I2C0_SCLK_DIV_A field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_DIV_A_Msk = 0x3f + // Position of I2C0_SCLK_DIV_B field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_DIV_B_Pos = 0x6 + // Bit mask of I2C0_SCLK_DIV_B field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_DIV_B_Msk = 0xfc0 + // Position of I2C0_SCLK_DIV_NUM field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of I2C0_SCLK_DIV_NUM field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_DIV_NUM_Msk = 0xff000 + // Position of I2C0_SCLK_SEL field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_SEL_Pos = 0x14 + // Bit mask of I2C0_SCLK_SEL field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_SEL_Msk = 0x100000 + // Bit I2C0_SCLK_SEL. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_SEL = 0x100000 + // Position of I2C0_SCLK_EN field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_EN_Pos = 0x16 + // Bit mask of I2C0_SCLK_EN field. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_EN_Msk = 0x400000 + // Bit I2C0_SCLK_EN. + PCR_I2C0_SCLK_CONF_I2C0_SCLK_EN = 0x400000 + + // I2C1_CONF: I2C configuration register + // Position of I2C1_CLK_EN field. + PCR_I2C1_CONF_I2C1_CLK_EN_Pos = 0x0 + // Bit mask of I2C1_CLK_EN field. + PCR_I2C1_CONF_I2C1_CLK_EN_Msk = 0x1 + // Bit I2C1_CLK_EN. + PCR_I2C1_CONF_I2C1_CLK_EN = 0x1 + // Position of I2C1_RST_EN field. + PCR_I2C1_CONF_I2C1_RST_EN_Pos = 0x1 + // Bit mask of I2C1_RST_EN field. + PCR_I2C1_CONF_I2C1_RST_EN_Msk = 0x2 + // Bit I2C1_RST_EN. + PCR_I2C1_CONF_I2C1_RST_EN = 0x2 + // Position of I2C1_READY field. + PCR_I2C1_CONF_I2C1_READY_Pos = 0x2 + // Bit mask of I2C1_READY field. + PCR_I2C1_CONF_I2C1_READY_Msk = 0x4 + // Bit I2C1_READY. + PCR_I2C1_CONF_I2C1_READY = 0x4 + + // I2C1_SCLK_CONF: I2C_SCLK configuration register + // Position of I2C1_SCLK_DIV_A field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_DIV_A_Pos = 0x0 + // Bit mask of I2C1_SCLK_DIV_A field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_DIV_A_Msk = 0x3f + // Position of I2C1_SCLK_DIV_B field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_DIV_B_Pos = 0x6 + // Bit mask of I2C1_SCLK_DIV_B field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_DIV_B_Msk = 0xfc0 + // Position of I2C1_SCLK_DIV_NUM field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of I2C1_SCLK_DIV_NUM field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_DIV_NUM_Msk = 0xff000 + // Position of I2C1_SCLK_SEL field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_SEL_Pos = 0x14 + // Bit mask of I2C1_SCLK_SEL field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_SEL_Msk = 0x100000 + // Bit I2C1_SCLK_SEL. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_SEL = 0x100000 + // Position of I2C1_SCLK_EN field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_EN_Pos = 0x16 + // Bit mask of I2C1_SCLK_EN field. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_EN_Msk = 0x400000 + // Bit I2C1_SCLK_EN. + PCR_I2C1_SCLK_CONF_I2C1_SCLK_EN = 0x400000 + + // UHCI_CONF: UHCI configuration register + // Position of UHCI_CLK_EN field. + PCR_UHCI_CONF_UHCI_CLK_EN_Pos = 0x0 + // Bit mask of UHCI_CLK_EN field. + PCR_UHCI_CONF_UHCI_CLK_EN_Msk = 0x1 + // Bit UHCI_CLK_EN. + PCR_UHCI_CONF_UHCI_CLK_EN = 0x1 + // Position of UHCI_RST_EN field. + PCR_UHCI_CONF_UHCI_RST_EN_Pos = 0x1 + // Bit mask of UHCI_RST_EN field. + PCR_UHCI_CONF_UHCI_RST_EN_Msk = 0x2 + // Bit UHCI_RST_EN. + PCR_UHCI_CONF_UHCI_RST_EN = 0x2 + // Position of UHCI_READY field. + PCR_UHCI_CONF_UHCI_READY_Pos = 0x2 + // Bit mask of UHCI_READY field. + PCR_UHCI_CONF_UHCI_READY_Msk = 0x4 + // Bit UHCI_READY. + PCR_UHCI_CONF_UHCI_READY = 0x4 + + // RMT_CONF: RMT configuration register + // Position of RMT_CLK_EN field. + PCR_RMT_CONF_RMT_CLK_EN_Pos = 0x0 + // Bit mask of RMT_CLK_EN field. + PCR_RMT_CONF_RMT_CLK_EN_Msk = 0x1 + // Bit RMT_CLK_EN. + PCR_RMT_CONF_RMT_CLK_EN = 0x1 + // Position of RMT_RST_EN field. + PCR_RMT_CONF_RMT_RST_EN_Pos = 0x1 + // Bit mask of RMT_RST_EN field. + PCR_RMT_CONF_RMT_RST_EN_Msk = 0x2 + // Bit RMT_RST_EN. + PCR_RMT_CONF_RMT_RST_EN = 0x2 + // Position of RMT_READY field. + PCR_RMT_CONF_RMT_READY_Pos = 0x2 + // Bit mask of RMT_READY field. + PCR_RMT_CONF_RMT_READY_Msk = 0x4 + // Bit RMT_READY. + PCR_RMT_CONF_RMT_READY = 0x4 + + // RMT_SCLK_CONF: RMT_SCLK configuration register + // Position of SCLK_DIV_A field. + PCR_RMT_SCLK_CONF_SCLK_DIV_A_Pos = 0x0 + // Bit mask of SCLK_DIV_A field. + PCR_RMT_SCLK_CONF_SCLK_DIV_A_Msk = 0x3f + // Position of SCLK_DIV_B field. + PCR_RMT_SCLK_CONF_SCLK_DIV_B_Pos = 0x6 + // Bit mask of SCLK_DIV_B field. + PCR_RMT_SCLK_CONF_SCLK_DIV_B_Msk = 0xfc0 + // Position of SCLK_DIV_NUM field. + PCR_RMT_SCLK_CONF_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of SCLK_DIV_NUM field. + PCR_RMT_SCLK_CONF_SCLK_DIV_NUM_Msk = 0xff000 + // Position of SCLK_SEL field. + PCR_RMT_SCLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + PCR_RMT_SCLK_CONF_SCLK_SEL_Msk = 0x100000 + // Bit SCLK_SEL. + PCR_RMT_SCLK_CONF_SCLK_SEL = 0x100000 + // Position of SCLK_EN field. + PCR_RMT_SCLK_CONF_SCLK_EN_Pos = 0x15 + // Bit mask of SCLK_EN field. + PCR_RMT_SCLK_CONF_SCLK_EN_Msk = 0x200000 + // Bit SCLK_EN. + PCR_RMT_SCLK_CONF_SCLK_EN = 0x200000 + + // LEDC_CONF: LEDC configuration register + // Position of LEDC_CLK_EN field. + PCR_LEDC_CONF_LEDC_CLK_EN_Pos = 0x0 + // Bit mask of LEDC_CLK_EN field. + PCR_LEDC_CONF_LEDC_CLK_EN_Msk = 0x1 + // Bit LEDC_CLK_EN. + PCR_LEDC_CONF_LEDC_CLK_EN = 0x1 + // Position of LEDC_RST_EN field. + PCR_LEDC_CONF_LEDC_RST_EN_Pos = 0x1 + // Bit mask of LEDC_RST_EN field. + PCR_LEDC_CONF_LEDC_RST_EN_Msk = 0x2 + // Bit LEDC_RST_EN. + PCR_LEDC_CONF_LEDC_RST_EN = 0x2 + // Position of LEDC_READY field. + PCR_LEDC_CONF_LEDC_READY_Pos = 0x2 + // Bit mask of LEDC_READY field. + PCR_LEDC_CONF_LEDC_READY_Msk = 0x4 + // Bit LEDC_READY. + PCR_LEDC_CONF_LEDC_READY = 0x4 + + // LEDC_SCLK_CONF: LEDC_SCLK configuration register + // Position of LEDC_SCLK_SEL field. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_SEL_Pos = 0x14 + // Bit mask of LEDC_SCLK_SEL field. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_SEL_Msk = 0x300000 + // Position of LEDC_SCLK_EN field. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_EN_Pos = 0x16 + // Bit mask of LEDC_SCLK_EN field. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_EN_Msk = 0x400000 + // Bit LEDC_SCLK_EN. + PCR_LEDC_SCLK_CONF_LEDC_SCLK_EN = 0x400000 + + // TIMERGROUP0_CONF: TIMERGROUP0 configuration register + // Position of TG0_CLK_EN field. + PCR_TIMERGROUP0_CONF_TG0_CLK_EN_Pos = 0x0 + // Bit mask of TG0_CLK_EN field. + PCR_TIMERGROUP0_CONF_TG0_CLK_EN_Msk = 0x1 + // Bit TG0_CLK_EN. + PCR_TIMERGROUP0_CONF_TG0_CLK_EN = 0x1 + // Position of TG0_RST_EN field. + PCR_TIMERGROUP0_CONF_TG0_RST_EN_Pos = 0x1 + // Bit mask of TG0_RST_EN field. + PCR_TIMERGROUP0_CONF_TG0_RST_EN_Msk = 0x2 + // Bit TG0_RST_EN. + PCR_TIMERGROUP0_CONF_TG0_RST_EN = 0x2 + // Position of TG0_WDT_READY field. + PCR_TIMERGROUP0_CONF_TG0_WDT_READY_Pos = 0x2 + // Bit mask of TG0_WDT_READY field. + PCR_TIMERGROUP0_CONF_TG0_WDT_READY_Msk = 0x4 + // Bit TG0_WDT_READY. + PCR_TIMERGROUP0_CONF_TG0_WDT_READY = 0x4 + // Position of TG0_TIMER0_READY field. + PCR_TIMERGROUP0_CONF_TG0_TIMER0_READY_Pos = 0x3 + // Bit mask of TG0_TIMER0_READY field. + PCR_TIMERGROUP0_CONF_TG0_TIMER0_READY_Msk = 0x8 + // Bit TG0_TIMER0_READY. + PCR_TIMERGROUP0_CONF_TG0_TIMER0_READY = 0x8 + // Position of TG0_TIMER1_READY field. + PCR_TIMERGROUP0_CONF_TG0_TIMER1_READY_Pos = 0x4 + // Bit mask of TG0_TIMER1_READY field. + PCR_TIMERGROUP0_CONF_TG0_TIMER1_READY_Msk = 0x10 + // Bit TG0_TIMER1_READY. + PCR_TIMERGROUP0_CONF_TG0_TIMER1_READY = 0x10 + + // TIMERGROUP0_TIMER_CLK_CONF: TIMERGROUP0_TIMER_CLK configuration register + // Position of TG0_TIMER_CLK_SEL field. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_SEL_Pos = 0x14 + // Bit mask of TG0_TIMER_CLK_SEL field. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_SEL_Msk = 0x300000 + // Position of TG0_TIMER_CLK_EN field. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN_Pos = 0x16 + // Bit mask of TG0_TIMER_CLK_EN field. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN_Msk = 0x400000 + // Bit TG0_TIMER_CLK_EN. + PCR_TIMERGROUP0_TIMER_CLK_CONF_TG0_TIMER_CLK_EN = 0x400000 + + // TIMERGROUP0_WDT_CLK_CONF: TIMERGROUP0_WDT_CLK configuration register + // Position of TG0_WDT_CLK_SEL field. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_SEL_Pos = 0x14 + // Bit mask of TG0_WDT_CLK_SEL field. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_SEL_Msk = 0x300000 + // Position of TG0_WDT_CLK_EN field. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN_Pos = 0x16 + // Bit mask of TG0_WDT_CLK_EN field. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN_Msk = 0x400000 + // Bit TG0_WDT_CLK_EN. + PCR_TIMERGROUP0_WDT_CLK_CONF_TG0_WDT_CLK_EN = 0x400000 + + // TIMERGROUP1_CONF: TIMERGROUP1 configuration register + // Position of TG1_CLK_EN field. + PCR_TIMERGROUP1_CONF_TG1_CLK_EN_Pos = 0x0 + // Bit mask of TG1_CLK_EN field. + PCR_TIMERGROUP1_CONF_TG1_CLK_EN_Msk = 0x1 + // Bit TG1_CLK_EN. + PCR_TIMERGROUP1_CONF_TG1_CLK_EN = 0x1 + // Position of TG1_RST_EN field. + PCR_TIMERGROUP1_CONF_TG1_RST_EN_Pos = 0x1 + // Bit mask of TG1_RST_EN field. + PCR_TIMERGROUP1_CONF_TG1_RST_EN_Msk = 0x2 + // Bit TG1_RST_EN. + PCR_TIMERGROUP1_CONF_TG1_RST_EN = 0x2 + // Position of TG1_WDT_READY field. + PCR_TIMERGROUP1_CONF_TG1_WDT_READY_Pos = 0x2 + // Bit mask of TG1_WDT_READY field. + PCR_TIMERGROUP1_CONF_TG1_WDT_READY_Msk = 0x4 + // Bit TG1_WDT_READY. + PCR_TIMERGROUP1_CONF_TG1_WDT_READY = 0x4 + // Position of TG1_TIMER0_READY field. + PCR_TIMERGROUP1_CONF_TG1_TIMER0_READY_Pos = 0x3 + // Bit mask of TG1_TIMER0_READY field. + PCR_TIMERGROUP1_CONF_TG1_TIMER0_READY_Msk = 0x8 + // Bit TG1_TIMER0_READY. + PCR_TIMERGROUP1_CONF_TG1_TIMER0_READY = 0x8 + // Position of TG1_TIMER1_READY field. + PCR_TIMERGROUP1_CONF_TG1_TIMER1_READY_Pos = 0x4 + // Bit mask of TG1_TIMER1_READY field. + PCR_TIMERGROUP1_CONF_TG1_TIMER1_READY_Msk = 0x10 + // Bit TG1_TIMER1_READY. + PCR_TIMERGROUP1_CONF_TG1_TIMER1_READY = 0x10 + + // TIMERGROUP1_TIMER_CLK_CONF: TIMERGROUP1_TIMER_CLK configuration register + // Position of TG1_TIMER_CLK_SEL field. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_SEL_Pos = 0x14 + // Bit mask of TG1_TIMER_CLK_SEL field. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_SEL_Msk = 0x300000 + // Position of TG1_TIMER_CLK_EN field. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN_Pos = 0x16 + // Bit mask of TG1_TIMER_CLK_EN field. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN_Msk = 0x400000 + // Bit TG1_TIMER_CLK_EN. + PCR_TIMERGROUP1_TIMER_CLK_CONF_TG1_TIMER_CLK_EN = 0x400000 + + // TIMERGROUP1_WDT_CLK_CONF: TIMERGROUP1_WDT_CLK configuration register + // Position of TG1_WDT_CLK_SEL field. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_SEL_Pos = 0x14 + // Bit mask of TG1_WDT_CLK_SEL field. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_SEL_Msk = 0x300000 + // Position of TG1_WDT_CLK_EN field. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN_Pos = 0x16 + // Bit mask of TG1_WDT_CLK_EN field. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN_Msk = 0x400000 + // Bit TG1_WDT_CLK_EN. + PCR_TIMERGROUP1_WDT_CLK_CONF_TG1_WDT_CLK_EN = 0x400000 + + // SYSTIMER_CONF: SYSTIMER configuration register + // Position of SYSTIMER_CLK_EN field. + PCR_SYSTIMER_CONF_SYSTIMER_CLK_EN_Pos = 0x0 + // Bit mask of SYSTIMER_CLK_EN field. + PCR_SYSTIMER_CONF_SYSTIMER_CLK_EN_Msk = 0x1 + // Bit SYSTIMER_CLK_EN. + PCR_SYSTIMER_CONF_SYSTIMER_CLK_EN = 0x1 + // Position of SYSTIMER_RST_EN field. + PCR_SYSTIMER_CONF_SYSTIMER_RST_EN_Pos = 0x1 + // Bit mask of SYSTIMER_RST_EN field. + PCR_SYSTIMER_CONF_SYSTIMER_RST_EN_Msk = 0x2 + // Bit SYSTIMER_RST_EN. + PCR_SYSTIMER_CONF_SYSTIMER_RST_EN = 0x2 + // Position of SYSTIMER_READY field. + PCR_SYSTIMER_CONF_SYSTIMER_READY_Pos = 0x2 + // Bit mask of SYSTIMER_READY field. + PCR_SYSTIMER_CONF_SYSTIMER_READY_Msk = 0x4 + // Bit SYSTIMER_READY. + PCR_SYSTIMER_CONF_SYSTIMER_READY = 0x4 + + // SYSTIMER_FUNC_CLK_CONF: SYSTIMER_FUNC_CLK configuration register + // Position of SYSTIMER_FUNC_CLK_SEL field. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL_Pos = 0x14 + // Bit mask of SYSTIMER_FUNC_CLK_SEL field. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL_Msk = 0x100000 + // Bit SYSTIMER_FUNC_CLK_SEL. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_SEL = 0x100000 + // Position of SYSTIMER_FUNC_CLK_EN field. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN_Pos = 0x16 + // Bit mask of SYSTIMER_FUNC_CLK_EN field. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN_Msk = 0x400000 + // Bit SYSTIMER_FUNC_CLK_EN. + PCR_SYSTIMER_FUNC_CLK_CONF_SYSTIMER_FUNC_CLK_EN = 0x400000 + + // TWAI0_CONF: TWAI0 configuration register + // Position of TWAI0_CLK_EN field. + PCR_TWAI0_CONF_TWAI0_CLK_EN_Pos = 0x0 + // Bit mask of TWAI0_CLK_EN field. + PCR_TWAI0_CONF_TWAI0_CLK_EN_Msk = 0x1 + // Bit TWAI0_CLK_EN. + PCR_TWAI0_CONF_TWAI0_CLK_EN = 0x1 + // Position of TWAI0_RST_EN field. + PCR_TWAI0_CONF_TWAI0_RST_EN_Pos = 0x1 + // Bit mask of TWAI0_RST_EN field. + PCR_TWAI0_CONF_TWAI0_RST_EN_Msk = 0x2 + // Bit TWAI0_RST_EN. + PCR_TWAI0_CONF_TWAI0_RST_EN = 0x2 + // Position of TWAI0_READY field. + PCR_TWAI0_CONF_TWAI0_READY_Pos = 0x2 + // Bit mask of TWAI0_READY field. + PCR_TWAI0_CONF_TWAI0_READY_Msk = 0x4 + // Bit TWAI0_READY. + PCR_TWAI0_CONF_TWAI0_READY = 0x4 + + // TWAI0_FUNC_CLK_CONF: TWAI0_FUNC_CLK configuration register + // Position of TWAI0_FUNC_CLK_SEL field. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL_Pos = 0x14 + // Bit mask of TWAI0_FUNC_CLK_SEL field. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL_Msk = 0x100000 + // Bit TWAI0_FUNC_CLK_SEL. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_SEL = 0x100000 + // Position of TWAI0_FUNC_CLK_EN field. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN_Pos = 0x16 + // Bit mask of TWAI0_FUNC_CLK_EN field. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN_Msk = 0x400000 + // Bit TWAI0_FUNC_CLK_EN. + PCR_TWAI0_FUNC_CLK_CONF_TWAI0_FUNC_CLK_EN = 0x400000 + + // I2S_CONF: I2S configuration register + // Position of I2S_CLK_EN field. + PCR_I2S_CONF_I2S_CLK_EN_Pos = 0x0 + // Bit mask of I2S_CLK_EN field. + PCR_I2S_CONF_I2S_CLK_EN_Msk = 0x1 + // Bit I2S_CLK_EN. + PCR_I2S_CONF_I2S_CLK_EN = 0x1 + // Position of I2S_RST_EN field. + PCR_I2S_CONF_I2S_RST_EN_Pos = 0x1 + // Bit mask of I2S_RST_EN field. + PCR_I2S_CONF_I2S_RST_EN_Msk = 0x2 + // Bit I2S_RST_EN. + PCR_I2S_CONF_I2S_RST_EN = 0x2 + // Position of I2S_RX_READY field. + PCR_I2S_CONF_I2S_RX_READY_Pos = 0x2 + // Bit mask of I2S_RX_READY field. + PCR_I2S_CONF_I2S_RX_READY_Msk = 0x4 + // Bit I2S_RX_READY. + PCR_I2S_CONF_I2S_RX_READY = 0x4 + // Position of I2S_TX_READY field. + PCR_I2S_CONF_I2S_TX_READY_Pos = 0x3 + // Bit mask of I2S_TX_READY field. + PCR_I2S_CONF_I2S_TX_READY_Msk = 0x8 + // Bit I2S_TX_READY. + PCR_I2S_CONF_I2S_TX_READY = 0x8 + + // I2S_TX_CLKM_CONF: I2S_TX_CLKM configuration register + // Position of I2S_TX_CLKM_DIV_NUM field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_DIV_NUM_Pos = 0xc + // Bit mask of I2S_TX_CLKM_DIV_NUM field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_DIV_NUM_Msk = 0xff000 + // Position of I2S_TX_CLKM_SEL field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_SEL_Pos = 0x14 + // Bit mask of I2S_TX_CLKM_SEL field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_SEL_Msk = 0x300000 + // Position of I2S_TX_CLKM_EN field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_EN_Pos = 0x16 + // Bit mask of I2S_TX_CLKM_EN field. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_EN_Msk = 0x400000 + // Bit I2S_TX_CLKM_EN. + PCR_I2S_TX_CLKM_CONF_I2S_TX_CLKM_EN = 0x400000 + + // I2S_TX_CLKM_DIV_CONF: I2S_TX_CLKM_DIV configuration register + // Position of I2S_TX_CLKM_DIV_Z field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of I2S_TX_CLKM_DIV_Z field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Z_Msk = 0x1ff + // Position of I2S_TX_CLKM_DIV_Y field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of I2S_TX_CLKM_DIV_Y field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of I2S_TX_CLKM_DIV_X field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of I2S_TX_CLKM_DIV_X field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of I2S_TX_CLKM_DIV_YN1 field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of I2S_TX_CLKM_DIV_YN1 field. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit I2S_TX_CLKM_DIV_YN1. + PCR_I2S_TX_CLKM_DIV_CONF_I2S_TX_CLKM_DIV_YN1 = 0x8000000 + + // I2S_RX_CLKM_CONF: I2S_RX_CLKM configuration register + // Position of I2S_RX_CLKM_DIV_NUM field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_DIV_NUM_Pos = 0xc + // Bit mask of I2S_RX_CLKM_DIV_NUM field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_DIV_NUM_Msk = 0xff000 + // Position of I2S_RX_CLKM_SEL field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_SEL_Pos = 0x14 + // Bit mask of I2S_RX_CLKM_SEL field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_SEL_Msk = 0x300000 + // Position of I2S_RX_CLKM_EN field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_EN_Pos = 0x16 + // Bit mask of I2S_RX_CLKM_EN field. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_EN_Msk = 0x400000 + // Bit I2S_RX_CLKM_EN. + PCR_I2S_RX_CLKM_CONF_I2S_RX_CLKM_EN = 0x400000 + // Position of I2S_MCLK_SEL field. + PCR_I2S_RX_CLKM_CONF_I2S_MCLK_SEL_Pos = 0x17 + // Bit mask of I2S_MCLK_SEL field. + PCR_I2S_RX_CLKM_CONF_I2S_MCLK_SEL_Msk = 0x800000 + // Bit I2S_MCLK_SEL. + PCR_I2S_RX_CLKM_CONF_I2S_MCLK_SEL = 0x800000 + + // I2S_RX_CLKM_DIV_CONF: I2S_RX_CLKM_DIV configuration register + // Position of I2S_RX_CLKM_DIV_Z field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of I2S_RX_CLKM_DIV_Z field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Z_Msk = 0x1ff + // Position of I2S_RX_CLKM_DIV_Y field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of I2S_RX_CLKM_DIV_Y field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of I2S_RX_CLKM_DIV_X field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of I2S_RX_CLKM_DIV_X field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of I2S_RX_CLKM_DIV_YN1 field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of I2S_RX_CLKM_DIV_YN1 field. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit I2S_RX_CLKM_DIV_YN1. + PCR_I2S_RX_CLKM_DIV_CONF_I2S_RX_CLKM_DIV_YN1 = 0x8000000 + + // SARADC_CONF: SARADC configuration register + // Position of SARADC_CLK_EN field. + PCR_SARADC_CONF_SARADC_CLK_EN_Pos = 0x0 + // Bit mask of SARADC_CLK_EN field. + PCR_SARADC_CONF_SARADC_CLK_EN_Msk = 0x1 + // Bit SARADC_CLK_EN. + PCR_SARADC_CONF_SARADC_CLK_EN = 0x1 + // Position of SARADC_RST_EN field. + PCR_SARADC_CONF_SARADC_RST_EN_Pos = 0x1 + // Bit mask of SARADC_RST_EN field. + PCR_SARADC_CONF_SARADC_RST_EN_Msk = 0x2 + // Bit SARADC_RST_EN. + PCR_SARADC_CONF_SARADC_RST_EN = 0x2 + // Position of SARADC_REG_CLK_EN field. + PCR_SARADC_CONF_SARADC_REG_CLK_EN_Pos = 0x2 + // Bit mask of SARADC_REG_CLK_EN field. + PCR_SARADC_CONF_SARADC_REG_CLK_EN_Msk = 0x4 + // Bit SARADC_REG_CLK_EN. + PCR_SARADC_CONF_SARADC_REG_CLK_EN = 0x4 + // Position of SARADC_REG_RST_EN field. + PCR_SARADC_CONF_SARADC_REG_RST_EN_Pos = 0x3 + // Bit mask of SARADC_REG_RST_EN field. + PCR_SARADC_CONF_SARADC_REG_RST_EN_Msk = 0x8 + // Bit SARADC_REG_RST_EN. + PCR_SARADC_CONF_SARADC_REG_RST_EN = 0x8 + + // SARADC_CLKM_CONF: SARADC_CLKM configuration register + // Position of SARADC_CLKM_DIV_A field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_A_Pos = 0x0 + // Bit mask of SARADC_CLKM_DIV_A field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_A_Msk = 0x3f + // Position of SARADC_CLKM_DIV_B field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_B_Pos = 0x6 + // Bit mask of SARADC_CLKM_DIV_B field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_B_Msk = 0xfc0 + // Position of SARADC_CLKM_DIV_NUM field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_NUM_Pos = 0xc + // Bit mask of SARADC_CLKM_DIV_NUM field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_DIV_NUM_Msk = 0xff000 + // Position of SARADC_CLKM_SEL field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_SEL_Pos = 0x14 + // Bit mask of SARADC_CLKM_SEL field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_SEL_Msk = 0x300000 + // Position of SARADC_CLKM_EN field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_EN_Pos = 0x16 + // Bit mask of SARADC_CLKM_EN field. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_EN_Msk = 0x400000 + // Bit SARADC_CLKM_EN. + PCR_SARADC_CLKM_CONF_SARADC_CLKM_EN = 0x400000 + + // TSENS_CLK_CONF: TSENS_CLK configuration register + // Position of TSENS_CLK_SEL field. + PCR_TSENS_CLK_CONF_TSENS_CLK_SEL_Pos = 0x14 + // Bit mask of TSENS_CLK_SEL field. + PCR_TSENS_CLK_CONF_TSENS_CLK_SEL_Msk = 0x100000 + // Bit TSENS_CLK_SEL. + PCR_TSENS_CLK_CONF_TSENS_CLK_SEL = 0x100000 + // Position of TSENS_CLK_EN field. + PCR_TSENS_CLK_CONF_TSENS_CLK_EN_Pos = 0x16 + // Bit mask of TSENS_CLK_EN field. + PCR_TSENS_CLK_CONF_TSENS_CLK_EN_Msk = 0x400000 + // Bit TSENS_CLK_EN. + PCR_TSENS_CLK_CONF_TSENS_CLK_EN = 0x400000 + // Position of TSENS_RST_EN field. + PCR_TSENS_CLK_CONF_TSENS_RST_EN_Pos = 0x17 + // Bit mask of TSENS_RST_EN field. + PCR_TSENS_CLK_CONF_TSENS_RST_EN_Msk = 0x800000 + // Bit TSENS_RST_EN. + PCR_TSENS_CLK_CONF_TSENS_RST_EN = 0x800000 + + // USB_DEVICE_CONF: USB_DEVICE configuration register + // Position of USB_DEVICE_CLK_EN field. + PCR_USB_DEVICE_CONF_USB_DEVICE_CLK_EN_Pos = 0x0 + // Bit mask of USB_DEVICE_CLK_EN field. + PCR_USB_DEVICE_CONF_USB_DEVICE_CLK_EN_Msk = 0x1 + // Bit USB_DEVICE_CLK_EN. + PCR_USB_DEVICE_CONF_USB_DEVICE_CLK_EN = 0x1 + // Position of USB_DEVICE_RST_EN field. + PCR_USB_DEVICE_CONF_USB_DEVICE_RST_EN_Pos = 0x1 + // Bit mask of USB_DEVICE_RST_EN field. + PCR_USB_DEVICE_CONF_USB_DEVICE_RST_EN_Msk = 0x2 + // Bit USB_DEVICE_RST_EN. + PCR_USB_DEVICE_CONF_USB_DEVICE_RST_EN = 0x2 + // Position of USB_DEVICE_READY field. + PCR_USB_DEVICE_CONF_USB_DEVICE_READY_Pos = 0x2 + // Bit mask of USB_DEVICE_READY field. + PCR_USB_DEVICE_CONF_USB_DEVICE_READY_Msk = 0x4 + // Bit USB_DEVICE_READY. + PCR_USB_DEVICE_CONF_USB_DEVICE_READY = 0x4 + + // INTMTX_CONF: INTMTX configuration register + // Position of INTMTX_CLK_EN field. + PCR_INTMTX_CONF_INTMTX_CLK_EN_Pos = 0x0 + // Bit mask of INTMTX_CLK_EN field. + PCR_INTMTX_CONF_INTMTX_CLK_EN_Msk = 0x1 + // Bit INTMTX_CLK_EN. + PCR_INTMTX_CONF_INTMTX_CLK_EN = 0x1 + // Position of INTMTX_RST_EN field. + PCR_INTMTX_CONF_INTMTX_RST_EN_Pos = 0x1 + // Bit mask of INTMTX_RST_EN field. + PCR_INTMTX_CONF_INTMTX_RST_EN_Msk = 0x2 + // Bit INTMTX_RST_EN. + PCR_INTMTX_CONF_INTMTX_RST_EN = 0x2 + // Position of INTMTX_READY field. + PCR_INTMTX_CONF_INTMTX_READY_Pos = 0x2 + // Bit mask of INTMTX_READY field. + PCR_INTMTX_CONF_INTMTX_READY_Msk = 0x4 + // Bit INTMTX_READY. + PCR_INTMTX_CONF_INTMTX_READY = 0x4 + + // PCNT_CONF: PCNT configuration register + // Position of PCNT_CLK_EN field. + PCR_PCNT_CONF_PCNT_CLK_EN_Pos = 0x0 + // Bit mask of PCNT_CLK_EN field. + PCR_PCNT_CONF_PCNT_CLK_EN_Msk = 0x1 + // Bit PCNT_CLK_EN. + PCR_PCNT_CONF_PCNT_CLK_EN = 0x1 + // Position of PCNT_RST_EN field. + PCR_PCNT_CONF_PCNT_RST_EN_Pos = 0x1 + // Bit mask of PCNT_RST_EN field. + PCR_PCNT_CONF_PCNT_RST_EN_Msk = 0x2 + // Bit PCNT_RST_EN. + PCR_PCNT_CONF_PCNT_RST_EN = 0x2 + // Position of PCNT_READY field. + PCR_PCNT_CONF_PCNT_READY_Pos = 0x2 + // Bit mask of PCNT_READY field. + PCR_PCNT_CONF_PCNT_READY_Msk = 0x4 + // Bit PCNT_READY. + PCR_PCNT_CONF_PCNT_READY = 0x4 + + // ETM_CONF: ETM configuration register + // Position of ETM_CLK_EN field. + PCR_ETM_CONF_ETM_CLK_EN_Pos = 0x0 + // Bit mask of ETM_CLK_EN field. + PCR_ETM_CONF_ETM_CLK_EN_Msk = 0x1 + // Bit ETM_CLK_EN. + PCR_ETM_CONF_ETM_CLK_EN = 0x1 + // Position of ETM_RST_EN field. + PCR_ETM_CONF_ETM_RST_EN_Pos = 0x1 + // Bit mask of ETM_RST_EN field. + PCR_ETM_CONF_ETM_RST_EN_Msk = 0x2 + // Bit ETM_RST_EN. + PCR_ETM_CONF_ETM_RST_EN = 0x2 + // Position of ETM_READY field. + PCR_ETM_CONF_ETM_READY_Pos = 0x2 + // Bit mask of ETM_READY field. + PCR_ETM_CONF_ETM_READY_Msk = 0x4 + // Bit ETM_READY. + PCR_ETM_CONF_ETM_READY = 0x4 + + // PWM_CONF: PWM configuration register + // Position of PWM_CLK_EN field. + PCR_PWM_CONF_PWM_CLK_EN_Pos = 0x0 + // Bit mask of PWM_CLK_EN field. + PCR_PWM_CONF_PWM_CLK_EN_Msk = 0x1 + // Bit PWM_CLK_EN. + PCR_PWM_CONF_PWM_CLK_EN = 0x1 + // Position of PWM_RST_EN field. + PCR_PWM_CONF_PWM_RST_EN_Pos = 0x1 + // Bit mask of PWM_RST_EN field. + PCR_PWM_CONF_PWM_RST_EN_Msk = 0x2 + // Bit PWM_RST_EN. + PCR_PWM_CONF_PWM_RST_EN = 0x2 + // Position of PWM_READY field. + PCR_PWM_CONF_PWM_READY_Pos = 0x2 + // Bit mask of PWM_READY field. + PCR_PWM_CONF_PWM_READY_Msk = 0x4 + // Bit PWM_READY. + PCR_PWM_CONF_PWM_READY = 0x4 + + // PWM_CLK_CONF: PWM_CLK configuration register + // Position of PWM_DIV_NUM field. + PCR_PWM_CLK_CONF_PWM_DIV_NUM_Pos = 0xc + // Bit mask of PWM_DIV_NUM field. + PCR_PWM_CLK_CONF_PWM_DIV_NUM_Msk = 0xff000 + // Position of PWM_CLKM_SEL field. + PCR_PWM_CLK_CONF_PWM_CLKM_SEL_Pos = 0x14 + // Bit mask of PWM_CLKM_SEL field. + PCR_PWM_CLK_CONF_PWM_CLKM_SEL_Msk = 0x300000 + // Position of PWM_CLKM_EN field. + PCR_PWM_CLK_CONF_PWM_CLKM_EN_Pos = 0x16 + // Bit mask of PWM_CLKM_EN field. + PCR_PWM_CLK_CONF_PWM_CLKM_EN_Msk = 0x400000 + // Bit PWM_CLKM_EN. + PCR_PWM_CLK_CONF_PWM_CLKM_EN = 0x400000 + + // PARL_IO_CONF: PARL_IO configuration register + // Position of PARL_CLK_EN field. + PCR_PARL_IO_CONF_PARL_CLK_EN_Pos = 0x0 + // Bit mask of PARL_CLK_EN field. + PCR_PARL_IO_CONF_PARL_CLK_EN_Msk = 0x1 + // Bit PARL_CLK_EN. + PCR_PARL_IO_CONF_PARL_CLK_EN = 0x1 + // Position of PARL_RST_EN field. + PCR_PARL_IO_CONF_PARL_RST_EN_Pos = 0x1 + // Bit mask of PARL_RST_EN field. + PCR_PARL_IO_CONF_PARL_RST_EN_Msk = 0x2 + // Bit PARL_RST_EN. + PCR_PARL_IO_CONF_PARL_RST_EN = 0x2 + // Position of PARL_READY field. + PCR_PARL_IO_CONF_PARL_READY_Pos = 0x2 + // Bit mask of PARL_READY field. + PCR_PARL_IO_CONF_PARL_READY_Msk = 0x4 + // Bit PARL_READY. + PCR_PARL_IO_CONF_PARL_READY = 0x4 + + // PARL_CLK_RX_CONF: PARL_CLK_RX configuration register + // Position of PARL_CLK_RX_DIV_NUM field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_DIV_NUM_Pos = 0x0 + // Bit mask of PARL_CLK_RX_DIV_NUM field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_DIV_NUM_Msk = 0xffff + // Position of PARL_CLK_RX_SEL field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_SEL_Pos = 0x10 + // Bit mask of PARL_CLK_RX_SEL field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_SEL_Msk = 0x30000 + // Position of PARL_CLK_RX_EN field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_EN_Pos = 0x12 + // Bit mask of PARL_CLK_RX_EN field. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_EN_Msk = 0x40000 + // Bit PARL_CLK_RX_EN. + PCR_PARL_CLK_RX_CONF_PARL_CLK_RX_EN = 0x40000 + // Position of PARL_RX_RST_EN field. + PCR_PARL_CLK_RX_CONF_PARL_RX_RST_EN_Pos = 0x13 + // Bit mask of PARL_RX_RST_EN field. + PCR_PARL_CLK_RX_CONF_PARL_RX_RST_EN_Msk = 0x80000 + // Bit PARL_RX_RST_EN. + PCR_PARL_CLK_RX_CONF_PARL_RX_RST_EN = 0x80000 + + // PARL_CLK_TX_CONF: PARL_CLK_TX configuration register + // Position of PARL_CLK_TX_DIV_NUM field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_DIV_NUM_Pos = 0x0 + // Bit mask of PARL_CLK_TX_DIV_NUM field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_DIV_NUM_Msk = 0xffff + // Position of PARL_CLK_TX_SEL field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_SEL_Pos = 0x10 + // Bit mask of PARL_CLK_TX_SEL field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_SEL_Msk = 0x30000 + // Position of PARL_CLK_TX_EN field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_EN_Pos = 0x12 + // Bit mask of PARL_CLK_TX_EN field. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_EN_Msk = 0x40000 + // Bit PARL_CLK_TX_EN. + PCR_PARL_CLK_TX_CONF_PARL_CLK_TX_EN = 0x40000 + // Position of PARL_TX_RST_EN field. + PCR_PARL_CLK_TX_CONF_PARL_TX_RST_EN_Pos = 0x13 + // Bit mask of PARL_TX_RST_EN field. + PCR_PARL_CLK_TX_CONF_PARL_TX_RST_EN_Msk = 0x80000 + // Bit PARL_TX_RST_EN. + PCR_PARL_CLK_TX_CONF_PARL_TX_RST_EN = 0x80000 + + // PVT_MONITOR_CONF: PVT_MONITOR configuration register + // Position of PVT_MONITOR_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_CLK_EN_Pos = 0x0 + // Bit mask of PVT_MONITOR_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_CLK_EN_Msk = 0x1 + // Bit PVT_MONITOR_CLK_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_CLK_EN = 0x1 + // Position of PVT_MONITOR_RST_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_RST_EN_Pos = 0x1 + // Bit mask of PVT_MONITOR_RST_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_RST_EN_Msk = 0x2 + // Bit PVT_MONITOR_RST_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_RST_EN = 0x2 + // Position of PVT_MONITOR_SITE1_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN_Pos = 0x2 + // Bit mask of PVT_MONITOR_SITE1_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN_Msk = 0x4 + // Bit PVT_MONITOR_SITE1_CLK_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE1_CLK_EN = 0x4 + // Position of PVT_MONITOR_SITE2_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN_Pos = 0x3 + // Bit mask of PVT_MONITOR_SITE2_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN_Msk = 0x8 + // Bit PVT_MONITOR_SITE2_CLK_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE2_CLK_EN = 0x8 + // Position of PVT_MONITOR_SITE3_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN_Pos = 0x4 + // Bit mask of PVT_MONITOR_SITE3_CLK_EN field. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN_Msk = 0x10 + // Bit PVT_MONITOR_SITE3_CLK_EN. + PCR_PVT_MONITOR_CONF_PVT_MONITOR_SITE3_CLK_EN = 0x10 + + // PVT_MONITOR_FUNC_CLK_CONF: PVT_MONITOR function clock configuration register + // Position of PVT_MONITOR_FUNC_CLK_DIV_NUM field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_DIV_NUM_Pos = 0x0 + // Bit mask of PVT_MONITOR_FUNC_CLK_DIV_NUM field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_DIV_NUM_Msk = 0xf + // Position of PVT_MONITOR_FUNC_CLK_SEL field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL_Pos = 0x14 + // Bit mask of PVT_MONITOR_FUNC_CLK_SEL field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL_Msk = 0x100000 + // Bit PVT_MONITOR_FUNC_CLK_SEL. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_SEL = 0x100000 + // Position of PVT_MONITOR_FUNC_CLK_EN field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN_Pos = 0x16 + // Bit mask of PVT_MONITOR_FUNC_CLK_EN field. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN_Msk = 0x400000 + // Bit PVT_MONITOR_FUNC_CLK_EN. + PCR_PVT_MONITOR_FUNC_CLK_CONF_PVT_MONITOR_FUNC_CLK_EN = 0x400000 + + // GDMA_CONF: GDMA configuration register + // Position of GDMA_CLK_EN field. + PCR_GDMA_CONF_GDMA_CLK_EN_Pos = 0x0 + // Bit mask of GDMA_CLK_EN field. + PCR_GDMA_CONF_GDMA_CLK_EN_Msk = 0x1 + // Bit GDMA_CLK_EN. + PCR_GDMA_CONF_GDMA_CLK_EN = 0x1 + // Position of GDMA_RST_EN field. + PCR_GDMA_CONF_GDMA_RST_EN_Pos = 0x1 + // Bit mask of GDMA_RST_EN field. + PCR_GDMA_CONF_GDMA_RST_EN_Msk = 0x2 + // Bit GDMA_RST_EN. + PCR_GDMA_CONF_GDMA_RST_EN = 0x2 + + // SPI2_CONF: SPI2 configuration register + // Position of SPI2_CLK_EN field. + PCR_SPI2_CONF_SPI2_CLK_EN_Pos = 0x0 + // Bit mask of SPI2_CLK_EN field. + PCR_SPI2_CONF_SPI2_CLK_EN_Msk = 0x1 + // Bit SPI2_CLK_EN. + PCR_SPI2_CONF_SPI2_CLK_EN = 0x1 + // Position of SPI2_RST_EN field. + PCR_SPI2_CONF_SPI2_RST_EN_Pos = 0x1 + // Bit mask of SPI2_RST_EN field. + PCR_SPI2_CONF_SPI2_RST_EN_Msk = 0x2 + // Bit SPI2_RST_EN. + PCR_SPI2_CONF_SPI2_RST_EN = 0x2 + // Position of SPI2_READY field. + PCR_SPI2_CONF_SPI2_READY_Pos = 0x2 + // Bit mask of SPI2_READY field. + PCR_SPI2_CONF_SPI2_READY_Msk = 0x4 + // Bit SPI2_READY. + PCR_SPI2_CONF_SPI2_READY = 0x4 + + // SPI2_CLKM_CONF: SPI2_CLKM configuration register + // Position of SPI2_CLKM_SEL field. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_SEL_Pos = 0x14 + // Bit mask of SPI2_CLKM_SEL field. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_SEL_Msk = 0x300000 + // Position of SPI2_CLKM_EN field. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_EN_Pos = 0x16 + // Bit mask of SPI2_CLKM_EN field. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_EN_Msk = 0x400000 + // Bit SPI2_CLKM_EN. + PCR_SPI2_CLKM_CONF_SPI2_CLKM_EN = 0x400000 + + // AES_CONF: AES configuration register + // Position of AES_CLK_EN field. + PCR_AES_CONF_AES_CLK_EN_Pos = 0x0 + // Bit mask of AES_CLK_EN field. + PCR_AES_CONF_AES_CLK_EN_Msk = 0x1 + // Bit AES_CLK_EN. + PCR_AES_CONF_AES_CLK_EN = 0x1 + // Position of AES_RST_EN field. + PCR_AES_CONF_AES_RST_EN_Pos = 0x1 + // Bit mask of AES_RST_EN field. + PCR_AES_CONF_AES_RST_EN_Msk = 0x2 + // Bit AES_RST_EN. + PCR_AES_CONF_AES_RST_EN = 0x2 + // Position of AES_READY field. + PCR_AES_CONF_AES_READY_Pos = 0x2 + // Bit mask of AES_READY field. + PCR_AES_CONF_AES_READY_Msk = 0x4 + // Bit AES_READY. + PCR_AES_CONF_AES_READY = 0x4 + + // SHA_CONF: SHA configuration register + // Position of SHA_CLK_EN field. + PCR_SHA_CONF_SHA_CLK_EN_Pos = 0x0 + // Bit mask of SHA_CLK_EN field. + PCR_SHA_CONF_SHA_CLK_EN_Msk = 0x1 + // Bit SHA_CLK_EN. + PCR_SHA_CONF_SHA_CLK_EN = 0x1 + // Position of SHA_RST_EN field. + PCR_SHA_CONF_SHA_RST_EN_Pos = 0x1 + // Bit mask of SHA_RST_EN field. + PCR_SHA_CONF_SHA_RST_EN_Msk = 0x2 + // Bit SHA_RST_EN. + PCR_SHA_CONF_SHA_RST_EN = 0x2 + // Position of SHA_READY field. + PCR_SHA_CONF_SHA_READY_Pos = 0x2 + // Bit mask of SHA_READY field. + PCR_SHA_CONF_SHA_READY_Msk = 0x4 + // Bit SHA_READY. + PCR_SHA_CONF_SHA_READY = 0x4 + + // RSA_CONF: RSA configuration register + // Position of RSA_CLK_EN field. + PCR_RSA_CONF_RSA_CLK_EN_Pos = 0x0 + // Bit mask of RSA_CLK_EN field. + PCR_RSA_CONF_RSA_CLK_EN_Msk = 0x1 + // Bit RSA_CLK_EN. + PCR_RSA_CONF_RSA_CLK_EN = 0x1 + // Position of RSA_RST_EN field. + PCR_RSA_CONF_RSA_RST_EN_Pos = 0x1 + // Bit mask of RSA_RST_EN field. + PCR_RSA_CONF_RSA_RST_EN_Msk = 0x2 + // Bit RSA_RST_EN. + PCR_RSA_CONF_RSA_RST_EN = 0x2 + // Position of RSA_READY field. + PCR_RSA_CONF_RSA_READY_Pos = 0x2 + // Bit mask of RSA_READY field. + PCR_RSA_CONF_RSA_READY_Msk = 0x4 + // Bit RSA_READY. + PCR_RSA_CONF_RSA_READY = 0x4 + + // RSA_PD_CTRL: RSA power control register + // Position of RSA_MEM_PD field. + PCR_RSA_PD_CTRL_RSA_MEM_PD_Pos = 0x0 + // Bit mask of RSA_MEM_PD field. + PCR_RSA_PD_CTRL_RSA_MEM_PD_Msk = 0x1 + // Bit RSA_MEM_PD. + PCR_RSA_PD_CTRL_RSA_MEM_PD = 0x1 + // Position of RSA_MEM_FORCE_PU field. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of RSA_MEM_FORCE_PU field. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Msk = 0x2 + // Bit RSA_MEM_FORCE_PU. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PU = 0x2 + // Position of RSA_MEM_FORCE_PD field. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of RSA_MEM_FORCE_PD field. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Msk = 0x4 + // Bit RSA_MEM_FORCE_PD. + PCR_RSA_PD_CTRL_RSA_MEM_FORCE_PD = 0x4 + + // ECC_CONF: ECC configuration register + // Position of ECC_CLK_EN field. + PCR_ECC_CONF_ECC_CLK_EN_Pos = 0x0 + // Bit mask of ECC_CLK_EN field. + PCR_ECC_CONF_ECC_CLK_EN_Msk = 0x1 + // Bit ECC_CLK_EN. + PCR_ECC_CONF_ECC_CLK_EN = 0x1 + // Position of ECC_RST_EN field. + PCR_ECC_CONF_ECC_RST_EN_Pos = 0x1 + // Bit mask of ECC_RST_EN field. + PCR_ECC_CONF_ECC_RST_EN_Msk = 0x2 + // Bit ECC_RST_EN. + PCR_ECC_CONF_ECC_RST_EN = 0x2 + // Position of ECC_READY field. + PCR_ECC_CONF_ECC_READY_Pos = 0x2 + // Bit mask of ECC_READY field. + PCR_ECC_CONF_ECC_READY_Msk = 0x4 + // Bit ECC_READY. + PCR_ECC_CONF_ECC_READY = 0x4 + + // ECC_PD_CTRL: ECC power control register + // Position of ECC_MEM_PD field. + PCR_ECC_PD_CTRL_ECC_MEM_PD_Pos = 0x0 + // Bit mask of ECC_MEM_PD field. + PCR_ECC_PD_CTRL_ECC_MEM_PD_Msk = 0x1 + // Bit ECC_MEM_PD. + PCR_ECC_PD_CTRL_ECC_MEM_PD = 0x1 + // Position of ECC_MEM_FORCE_PU field. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of ECC_MEM_FORCE_PU field. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PU_Msk = 0x2 + // Bit ECC_MEM_FORCE_PU. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PU = 0x2 + // Position of ECC_MEM_FORCE_PD field. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of ECC_MEM_FORCE_PD field. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PD_Msk = 0x4 + // Bit ECC_MEM_FORCE_PD. + PCR_ECC_PD_CTRL_ECC_MEM_FORCE_PD = 0x4 + + // DS_CONF: DS configuration register + // Position of DS_CLK_EN field. + PCR_DS_CONF_DS_CLK_EN_Pos = 0x0 + // Bit mask of DS_CLK_EN field. + PCR_DS_CONF_DS_CLK_EN_Msk = 0x1 + // Bit DS_CLK_EN. + PCR_DS_CONF_DS_CLK_EN = 0x1 + // Position of DS_RST_EN field. + PCR_DS_CONF_DS_RST_EN_Pos = 0x1 + // Bit mask of DS_RST_EN field. + PCR_DS_CONF_DS_RST_EN_Msk = 0x2 + // Bit DS_RST_EN. + PCR_DS_CONF_DS_RST_EN = 0x2 + // Position of DS_READY field. + PCR_DS_CONF_DS_READY_Pos = 0x2 + // Bit mask of DS_READY field. + PCR_DS_CONF_DS_READY_Msk = 0x4 + // Bit DS_READY. + PCR_DS_CONF_DS_READY = 0x4 + + // HMAC_CONF: HMAC configuration register + // Position of HMAC_CLK_EN field. + PCR_HMAC_CONF_HMAC_CLK_EN_Pos = 0x0 + // Bit mask of HMAC_CLK_EN field. + PCR_HMAC_CONF_HMAC_CLK_EN_Msk = 0x1 + // Bit HMAC_CLK_EN. + PCR_HMAC_CONF_HMAC_CLK_EN = 0x1 + // Position of HMAC_RST_EN field. + PCR_HMAC_CONF_HMAC_RST_EN_Pos = 0x1 + // Bit mask of HMAC_RST_EN field. + PCR_HMAC_CONF_HMAC_RST_EN_Msk = 0x2 + // Bit HMAC_RST_EN. + PCR_HMAC_CONF_HMAC_RST_EN = 0x2 + // Position of HMAC_READY field. + PCR_HMAC_CONF_HMAC_READY_Pos = 0x2 + // Bit mask of HMAC_READY field. + PCR_HMAC_CONF_HMAC_READY_Msk = 0x4 + // Bit HMAC_READY. + PCR_HMAC_CONF_HMAC_READY = 0x4 + + // ECDSA_CONF: ECDSA configuration register + // Position of ECDSA_CLK_EN field. + PCR_ECDSA_CONF_ECDSA_CLK_EN_Pos = 0x0 + // Bit mask of ECDSA_CLK_EN field. + PCR_ECDSA_CONF_ECDSA_CLK_EN_Msk = 0x1 + // Bit ECDSA_CLK_EN. + PCR_ECDSA_CONF_ECDSA_CLK_EN = 0x1 + // Position of ECDSA_RST_EN field. + PCR_ECDSA_CONF_ECDSA_RST_EN_Pos = 0x1 + // Bit mask of ECDSA_RST_EN field. + PCR_ECDSA_CONF_ECDSA_RST_EN_Msk = 0x2 + // Bit ECDSA_RST_EN. + PCR_ECDSA_CONF_ECDSA_RST_EN = 0x2 + // Position of ECDSA_READY field. + PCR_ECDSA_CONF_ECDSA_READY_Pos = 0x2 + // Bit mask of ECDSA_READY field. + PCR_ECDSA_CONF_ECDSA_READY_Msk = 0x4 + // Bit ECDSA_READY. + PCR_ECDSA_CONF_ECDSA_READY = 0x4 + + // IOMUX_CONF: IOMUX configuration register + // Position of IOMUX_CLK_EN field. + PCR_IOMUX_CONF_IOMUX_CLK_EN_Pos = 0x0 + // Bit mask of IOMUX_CLK_EN field. + PCR_IOMUX_CONF_IOMUX_CLK_EN_Msk = 0x1 + // Bit IOMUX_CLK_EN. + PCR_IOMUX_CONF_IOMUX_CLK_EN = 0x1 + // Position of IOMUX_RST_EN field. + PCR_IOMUX_CONF_IOMUX_RST_EN_Pos = 0x1 + // Bit mask of IOMUX_RST_EN field. + PCR_IOMUX_CONF_IOMUX_RST_EN_Msk = 0x2 + // Bit IOMUX_RST_EN. + PCR_IOMUX_CONF_IOMUX_RST_EN = 0x2 + + // IOMUX_CLK_CONF: IOMUX_CLK configuration register + // Position of IOMUX_FUNC_CLK_SEL field. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_SEL_Pos = 0x14 + // Bit mask of IOMUX_FUNC_CLK_SEL field. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_SEL_Msk = 0x300000 + // Position of IOMUX_FUNC_CLK_EN field. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN_Pos = 0x16 + // Bit mask of IOMUX_FUNC_CLK_EN field. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN_Msk = 0x400000 + // Bit IOMUX_FUNC_CLK_EN. + PCR_IOMUX_CLK_CONF_IOMUX_FUNC_CLK_EN = 0x400000 + + // MEM_MONITOR_CONF: MEM_MONITOR configuration register + // Position of MEM_MONITOR_CLK_EN field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_CLK_EN_Pos = 0x0 + // Bit mask of MEM_MONITOR_CLK_EN field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_CLK_EN_Msk = 0x1 + // Bit MEM_MONITOR_CLK_EN. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_CLK_EN = 0x1 + // Position of MEM_MONITOR_RST_EN field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_RST_EN_Pos = 0x1 + // Bit mask of MEM_MONITOR_RST_EN field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_RST_EN_Msk = 0x2 + // Bit MEM_MONITOR_RST_EN. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_RST_EN = 0x2 + // Position of MEM_MONITOR_READY field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_READY_Pos = 0x2 + // Bit mask of MEM_MONITOR_READY field. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_READY_Msk = 0x4 + // Bit MEM_MONITOR_READY. + PCR_MEM_MONITOR_CONF_MEM_MONITOR_READY = 0x4 + + // REGDMA_CONF: REGDMA configuration register + // Position of REGDMA_CLK_EN field. + PCR_REGDMA_CONF_REGDMA_CLK_EN_Pos = 0x0 + // Bit mask of REGDMA_CLK_EN field. + PCR_REGDMA_CONF_REGDMA_CLK_EN_Msk = 0x1 + // Bit REGDMA_CLK_EN. + PCR_REGDMA_CONF_REGDMA_CLK_EN = 0x1 + // Position of REGDMA_RST_EN field. + PCR_REGDMA_CONF_REGDMA_RST_EN_Pos = 0x1 + // Bit mask of REGDMA_RST_EN field. + PCR_REGDMA_CONF_REGDMA_RST_EN_Msk = 0x2 + // Bit REGDMA_RST_EN. + PCR_REGDMA_CONF_REGDMA_RST_EN = 0x2 + + // TRACE_CONF: TRACE configuration register + // Position of TRACE_CLK_EN field. + PCR_TRACE_CONF_TRACE_CLK_EN_Pos = 0x0 + // Bit mask of TRACE_CLK_EN field. + PCR_TRACE_CONF_TRACE_CLK_EN_Msk = 0x1 + // Bit TRACE_CLK_EN. + PCR_TRACE_CONF_TRACE_CLK_EN = 0x1 + // Position of TRACE_RST_EN field. + PCR_TRACE_CONF_TRACE_RST_EN_Pos = 0x1 + // Bit mask of TRACE_RST_EN field. + PCR_TRACE_CONF_TRACE_RST_EN_Msk = 0x2 + // Bit TRACE_RST_EN. + PCR_TRACE_CONF_TRACE_RST_EN = 0x2 + + // ASSIST_CONF: ASSIST configuration register + // Position of ASSIST_CLK_EN field. + PCR_ASSIST_CONF_ASSIST_CLK_EN_Pos = 0x0 + // Bit mask of ASSIST_CLK_EN field. + PCR_ASSIST_CONF_ASSIST_CLK_EN_Msk = 0x1 + // Bit ASSIST_CLK_EN. + PCR_ASSIST_CONF_ASSIST_CLK_EN = 0x1 + // Position of ASSIST_RST_EN field. + PCR_ASSIST_CONF_ASSIST_RST_EN_Pos = 0x1 + // Bit mask of ASSIST_RST_EN field. + PCR_ASSIST_CONF_ASSIST_RST_EN_Msk = 0x2 + // Bit ASSIST_RST_EN. + PCR_ASSIST_CONF_ASSIST_RST_EN = 0x2 + + // CACHE_CONF: CACHE configuration register + // Position of CACHE_CLK_EN field. + PCR_CACHE_CONF_CACHE_CLK_EN_Pos = 0x0 + // Bit mask of CACHE_CLK_EN field. + PCR_CACHE_CONF_CACHE_CLK_EN_Msk = 0x1 + // Bit CACHE_CLK_EN. + PCR_CACHE_CONF_CACHE_CLK_EN = 0x1 + // Position of CACHE_RST_EN field. + PCR_CACHE_CONF_CACHE_RST_EN_Pos = 0x1 + // Bit mask of CACHE_RST_EN field. + PCR_CACHE_CONF_CACHE_RST_EN_Msk = 0x2 + // Bit CACHE_RST_EN. + PCR_CACHE_CONF_CACHE_RST_EN = 0x2 + + // MODEM_CONF: MODEM_APB configuration register + // Position of MODEM_CLK_SEL field. + PCR_MODEM_CONF_MODEM_CLK_SEL_Pos = 0x0 + // Bit mask of MODEM_CLK_SEL field. + PCR_MODEM_CONF_MODEM_CLK_SEL_Msk = 0x1 + // Bit MODEM_CLK_SEL. + PCR_MODEM_CONF_MODEM_CLK_SEL = 0x1 + // Position of MODEM_CLK_EN field. + PCR_MODEM_CONF_MODEM_CLK_EN_Pos = 0x1 + // Bit mask of MODEM_CLK_EN field. + PCR_MODEM_CONF_MODEM_CLK_EN_Msk = 0x2 + // Bit MODEM_CLK_EN. + PCR_MODEM_CONF_MODEM_CLK_EN = 0x2 + // Position of MODEM_RST_EN field. + PCR_MODEM_CONF_MODEM_RST_EN_Pos = 0x2 + // Bit mask of MODEM_RST_EN field. + PCR_MODEM_CONF_MODEM_RST_EN_Msk = 0x4 + // Bit MODEM_RST_EN. + PCR_MODEM_CONF_MODEM_RST_EN = 0x4 + + // TIMEOUT_CONF: TIMEOUT configuration register + // Position of CPU_TIMEOUT_RST_EN field. + PCR_TIMEOUT_CONF_CPU_TIMEOUT_RST_EN_Pos = 0x1 + // Bit mask of CPU_TIMEOUT_RST_EN field. + PCR_TIMEOUT_CONF_CPU_TIMEOUT_RST_EN_Msk = 0x2 + // Bit CPU_TIMEOUT_RST_EN. + PCR_TIMEOUT_CONF_CPU_TIMEOUT_RST_EN = 0x2 + // Position of HP_TIMEOUT_RST_EN field. + PCR_TIMEOUT_CONF_HP_TIMEOUT_RST_EN_Pos = 0x2 + // Bit mask of HP_TIMEOUT_RST_EN field. + PCR_TIMEOUT_CONF_HP_TIMEOUT_RST_EN_Msk = 0x4 + // Bit HP_TIMEOUT_RST_EN. + PCR_TIMEOUT_CONF_HP_TIMEOUT_RST_EN = 0x4 + + // SYSCLK_CONF: SYSCLK configuration register + // Position of LS_DIV_NUM field. + PCR_SYSCLK_CONF_LS_DIV_NUM_Pos = 0x0 + // Bit mask of LS_DIV_NUM field. + PCR_SYSCLK_CONF_LS_DIV_NUM_Msk = 0xff + // Position of HS_DIV_NUM field. + PCR_SYSCLK_CONF_HS_DIV_NUM_Pos = 0x8 + // Bit mask of HS_DIV_NUM field. + PCR_SYSCLK_CONF_HS_DIV_NUM_Msk = 0xff00 + // Position of SOC_CLK_SEL field. + PCR_SYSCLK_CONF_SOC_CLK_SEL_Pos = 0x10 + // Bit mask of SOC_CLK_SEL field. + PCR_SYSCLK_CONF_SOC_CLK_SEL_Msk = 0x30000 + // Position of CLK_XTAL_FREQ field. + PCR_SYSCLK_CONF_CLK_XTAL_FREQ_Pos = 0x18 + // Bit mask of CLK_XTAL_FREQ field. + PCR_SYSCLK_CONF_CLK_XTAL_FREQ_Msk = 0x7f000000 + + // CPU_WAITI_CONF: CPU_WAITI configuration register + // Position of CPUPERIOD_SEL field. + PCR_CPU_WAITI_CONF_CPUPERIOD_SEL_Pos = 0x0 + // Bit mask of CPUPERIOD_SEL field. + PCR_CPU_WAITI_CONF_CPUPERIOD_SEL_Msk = 0x3 + // Position of PLL_FREQ_SEL field. + PCR_CPU_WAITI_CONF_PLL_FREQ_SEL_Pos = 0x2 + // Bit mask of PLL_FREQ_SEL field. + PCR_CPU_WAITI_CONF_PLL_FREQ_SEL_Msk = 0x4 + // Bit PLL_FREQ_SEL. + PCR_CPU_WAITI_CONF_PLL_FREQ_SEL = 0x4 + // Position of CPU_WAIT_MODE_FORCE_ON field. + PCR_CPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON_Pos = 0x3 + // Bit mask of CPU_WAIT_MODE_FORCE_ON field. + PCR_CPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON_Msk = 0x8 + // Bit CPU_WAIT_MODE_FORCE_ON. + PCR_CPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON = 0x8 + // Position of CPU_WAITI_DELAY_NUM field. + PCR_CPU_WAITI_CONF_CPU_WAITI_DELAY_NUM_Pos = 0x4 + // Bit mask of CPU_WAITI_DELAY_NUM field. + PCR_CPU_WAITI_CONF_CPU_WAITI_DELAY_NUM_Msk = 0xf0 + + // CPU_FREQ_CONF: CPU_FREQ configuration register + // Position of CPU_DIV_NUM field. + PCR_CPU_FREQ_CONF_CPU_DIV_NUM_Pos = 0x0 + // Bit mask of CPU_DIV_NUM field. + PCR_CPU_FREQ_CONF_CPU_DIV_NUM_Msk = 0xff + + // AHB_FREQ_CONF: AHB_FREQ configuration register + // Position of AHB_DIV_NUM field. + PCR_AHB_FREQ_CONF_AHB_DIV_NUM_Pos = 0x0 + // Bit mask of AHB_DIV_NUM field. + PCR_AHB_FREQ_CONF_AHB_DIV_NUM_Msk = 0xff + + // APB_FREQ_CONF: APB_FREQ configuration register + // Position of APB_DECREASE_DIV_NUM field. + PCR_APB_FREQ_CONF_APB_DECREASE_DIV_NUM_Pos = 0x0 + // Bit mask of APB_DECREASE_DIV_NUM field. + PCR_APB_FREQ_CONF_APB_DECREASE_DIV_NUM_Msk = 0xff + // Position of APB_DIV_NUM field. + PCR_APB_FREQ_CONF_APB_DIV_NUM_Pos = 0x8 + // Bit mask of APB_DIV_NUM field. + PCR_APB_FREQ_CONF_APB_DIV_NUM_Msk = 0xff00 + + // SYSCLK_FREQ_QUERY_0: SYSCLK frequency query 0 register + // Position of FOSC_FREQ field. + PCR_SYSCLK_FREQ_QUERY_0_FOSC_FREQ_Pos = 0x0 + // Bit mask of FOSC_FREQ field. + PCR_SYSCLK_FREQ_QUERY_0_FOSC_FREQ_Msk = 0xff + // Position of PLL_FREQ field. + PCR_SYSCLK_FREQ_QUERY_0_PLL_FREQ_Pos = 0x8 + // Bit mask of PLL_FREQ field. + PCR_SYSCLK_FREQ_QUERY_0_PLL_FREQ_Msk = 0x3ff00 + + // PLL_DIV_CLK_EN: SPLL DIV clock-gating configuration register + // Position of PLL_240M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_240M_CLK_EN_Pos = 0x0 + // Bit mask of PLL_240M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_240M_CLK_EN_Msk = 0x1 + // Bit PLL_240M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_240M_CLK_EN = 0x1 + // Position of PLL_160M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_160M_CLK_EN_Pos = 0x1 + // Bit mask of PLL_160M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_160M_CLK_EN_Msk = 0x2 + // Bit PLL_160M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_160M_CLK_EN = 0x2 + // Position of PLL_120M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_120M_CLK_EN_Pos = 0x2 + // Bit mask of PLL_120M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_120M_CLK_EN_Msk = 0x4 + // Bit PLL_120M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_120M_CLK_EN = 0x4 + // Position of PLL_80M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_80M_CLK_EN_Pos = 0x3 + // Bit mask of PLL_80M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_80M_CLK_EN_Msk = 0x8 + // Bit PLL_80M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_80M_CLK_EN = 0x8 + // Position of PLL_48M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_48M_CLK_EN_Pos = 0x4 + // Bit mask of PLL_48M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_48M_CLK_EN_Msk = 0x10 + // Bit PLL_48M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_48M_CLK_EN = 0x10 + // Position of PLL_40M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_40M_CLK_EN_Pos = 0x5 + // Bit mask of PLL_40M_CLK_EN field. + PCR_PLL_DIV_CLK_EN_PLL_40M_CLK_EN_Msk = 0x20 + // Bit PLL_40M_CLK_EN. + PCR_PLL_DIV_CLK_EN_PLL_40M_CLK_EN = 0x20 + + // CTRL_CLK_OUT_EN: CLK_OUT_EN configuration register + // Position of CLK8_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK8_OEN_Pos = 0x0 + // Bit mask of CLK8_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK8_OEN_Msk = 0x1 + // Bit CLK8_OEN. + PCR_CTRL_CLK_OUT_EN_CLK8_OEN = 0x1 + // Position of CLK16_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK16_OEN_Pos = 0x1 + // Bit mask of CLK16_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK16_OEN_Msk = 0x2 + // Bit CLK16_OEN. + PCR_CTRL_CLK_OUT_EN_CLK16_OEN = 0x2 + // Position of CLK32_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK32_OEN_Pos = 0x2 + // Bit mask of CLK32_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK32_OEN_Msk = 0x4 + // Bit CLK32_OEN. + PCR_CTRL_CLK_OUT_EN_CLK32_OEN = 0x4 + // Position of CLK_ADC_INF_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Pos = 0x3 + // Bit mask of CLK_ADC_INF_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Msk = 0x8 + // Bit CLK_ADC_INF_OEN. + PCR_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN = 0x8 + // Position of CLK_DFM_INF_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_DFM_INF_OEN_Pos = 0x4 + // Bit mask of CLK_DFM_INF_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_DFM_INF_OEN_Msk = 0x10 + // Bit CLK_DFM_INF_OEN. + PCR_CTRL_CLK_OUT_EN_CLK_DFM_INF_OEN = 0x10 + // Position of CLK_SDM_MOD_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_SDM_MOD_OEN_Pos = 0x5 + // Bit mask of CLK_SDM_MOD_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_SDM_MOD_OEN_Msk = 0x20 + // Bit CLK_SDM_MOD_OEN. + PCR_CTRL_CLK_OUT_EN_CLK_SDM_MOD_OEN = 0x20 + // Position of CLK_XTAL_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Pos = 0x6 + // Bit mask of CLK_XTAL_OEN field. + PCR_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Msk = 0x40 + // Bit CLK_XTAL_OEN. + PCR_CTRL_CLK_OUT_EN_CLK_XTAL_OEN = 0x40 + + // CTRL_TICK_CONF: TICK configuration register + // Position of XTAL_TICK_NUM field. + PCR_CTRL_TICK_CONF_XTAL_TICK_NUM_Pos = 0x0 + // Bit mask of XTAL_TICK_NUM field. + PCR_CTRL_TICK_CONF_XTAL_TICK_NUM_Msk = 0xff + // Position of FOSC_TICK_NUM field. + PCR_CTRL_TICK_CONF_FOSC_TICK_NUM_Pos = 0x8 + // Bit mask of FOSC_TICK_NUM field. + PCR_CTRL_TICK_CONF_FOSC_TICK_NUM_Msk = 0xff00 + // Position of TICK_ENABLE field. + PCR_CTRL_TICK_CONF_TICK_ENABLE_Pos = 0x10 + // Bit mask of TICK_ENABLE field. + PCR_CTRL_TICK_CONF_TICK_ENABLE_Msk = 0x10000 + // Bit TICK_ENABLE. + PCR_CTRL_TICK_CONF_TICK_ENABLE = 0x10000 + // Position of RST_TICK_CNT field. + PCR_CTRL_TICK_CONF_RST_TICK_CNT_Pos = 0x11 + // Bit mask of RST_TICK_CNT field. + PCR_CTRL_TICK_CONF_RST_TICK_CNT_Msk = 0x20000 + // Bit RST_TICK_CNT. + PCR_CTRL_TICK_CONF_RST_TICK_CNT = 0x20000 + + // CTRL_32K_CONF: 32KHz clock configuration register + // Position of CLK_32K_SEL field. + PCR_CTRL_32K_CONF_CLK_32K_SEL_Pos = 0x0 + // Bit mask of CLK_32K_SEL field. + PCR_CTRL_32K_CONF_CLK_32K_SEL_Msk = 0x3 + // Position of _32K_MODEM_SEL field. + PCR_CTRL_32K_CONF__32K_MODEM_SEL_Pos = 0x2 + // Bit mask of _32K_MODEM_SEL field. + PCR_CTRL_32K_CONF__32K_MODEM_SEL_Msk = 0xc + + // SRAM_POWER_CONF_0: HP SRAM/ROM configuration register + // Position of ROM_FORCE_PU field. + PCR_SRAM_POWER_CONF_0_ROM_FORCE_PU_Pos = 0xd + // Bit mask of ROM_FORCE_PU field. + PCR_SRAM_POWER_CONF_0_ROM_FORCE_PU_Msk = 0x6000 + // Position of ROM_FORCE_PD field. + PCR_SRAM_POWER_CONF_0_ROM_FORCE_PD_Pos = 0xf + // Bit mask of ROM_FORCE_PD field. + PCR_SRAM_POWER_CONF_0_ROM_FORCE_PD_Msk = 0x18000 + // Position of ROM_CLKGATE_FORCE_ON field. + PCR_SRAM_POWER_CONF_0_ROM_CLKGATE_FORCE_ON_Pos = 0x11 + // Bit mask of ROM_CLKGATE_FORCE_ON field. + PCR_SRAM_POWER_CONF_0_ROM_CLKGATE_FORCE_ON_Msk = 0x60000 + + // SRAM_POWER_CONF_1: HP SRAM/ROM configuration register + // Position of SRAM_FORCE_PU field. + PCR_SRAM_POWER_CONF_1_SRAM_FORCE_PU_Pos = 0x0 + // Bit mask of SRAM_FORCE_PU field. + PCR_SRAM_POWER_CONF_1_SRAM_FORCE_PU_Msk = 0x1f + // Position of SRAM_FORCE_PD field. + PCR_SRAM_POWER_CONF_1_SRAM_FORCE_PD_Pos = 0xa + // Bit mask of SRAM_FORCE_PD field. + PCR_SRAM_POWER_CONF_1_SRAM_FORCE_PD_Msk = 0x7c00 + // Position of SRAM_CLKGATE_FORCE_ON field. + PCR_SRAM_POWER_CONF_1_SRAM_CLKGATE_FORCE_ON_Pos = 0x19 + // Bit mask of SRAM_CLKGATE_FORCE_ON field. + PCR_SRAM_POWER_CONF_1_SRAM_CLKGATE_FORCE_ON_Msk = 0x3e000000 + + // SEC_CONF: xxxx + // Position of SEC_CLK_SEL field. + PCR_SEC_CONF_SEC_CLK_SEL_Pos = 0x0 + // Bit mask of SEC_CLK_SEL field. + PCR_SEC_CONF_SEC_CLK_SEL_Msk = 0x3 + + // ADC_INV_PHASE_CONF: xxxx + // Position of CLK_ADC_INV_PHASE_ENA field. + PCR_ADC_INV_PHASE_CONF_CLK_ADC_INV_PHASE_ENA_Pos = 0x0 + // Bit mask of CLK_ADC_INV_PHASE_ENA field. + PCR_ADC_INV_PHASE_CONF_CLK_ADC_INV_PHASE_ENA_Msk = 0x1 + // Bit CLK_ADC_INV_PHASE_ENA. + PCR_ADC_INV_PHASE_CONF_CLK_ADC_INV_PHASE_ENA = 0x1 + + // SDM_INV_PHASE_CONF: xxxx + // Position of CLK_SDM_INV_PHASE_ENA field. + PCR_SDM_INV_PHASE_CONF_CLK_SDM_INV_PHASE_ENA_Pos = 0x0 + // Bit mask of CLK_SDM_INV_PHASE_ENA field. + PCR_SDM_INV_PHASE_CONF_CLK_SDM_INV_PHASE_ENA_Msk = 0x1 + // Bit CLK_SDM_INV_PHASE_ENA. + PCR_SDM_INV_PHASE_CONF_CLK_SDM_INV_PHASE_ENA = 0x1 + // Position of CLK_SDM_INV_PHASE_SEL field. + PCR_SDM_INV_PHASE_CONF_CLK_SDM_INV_PHASE_SEL_Pos = 0x1 + // Bit mask of CLK_SDM_INV_PHASE_SEL field. + PCR_SDM_INV_PHASE_CONF_CLK_SDM_INV_PHASE_SEL_Msk = 0xe + + // BUS_CLK_UPDATE: xxxx + // Position of BUS_CLOCK_UPDATE field. + PCR_BUS_CLK_UPDATE_BUS_CLOCK_UPDATE_Pos = 0x0 + // Bit mask of BUS_CLOCK_UPDATE field. + PCR_BUS_CLK_UPDATE_BUS_CLOCK_UPDATE_Msk = 0x1 + // Bit BUS_CLOCK_UPDATE. + PCR_BUS_CLK_UPDATE_BUS_CLOCK_UPDATE = 0x1 + + // SAR_CLK_DIV: xxxx + // Position of SAR2_CLK_DIV_NUM field. + PCR_SAR_CLK_DIV_SAR2_CLK_DIV_NUM_Pos = 0x0 + // Bit mask of SAR2_CLK_DIV_NUM field. + PCR_SAR_CLK_DIV_SAR2_CLK_DIV_NUM_Msk = 0xff + // Position of SAR1_CLK_DIV_NUM field. + PCR_SAR_CLK_DIV_SAR1_CLK_DIV_NUM_Pos = 0x8 + // Bit mask of SAR1_CLK_DIV_NUM field. + PCR_SAR_CLK_DIV_SAR1_CLK_DIV_NUM_Msk = 0xff00 + + // PWDET_SAR_CLK_CONF: xxxx + // Position of PWDET_SAR_CLK_DIV_NUM field. + PCR_PWDET_SAR_CLK_CONF_PWDET_SAR_CLK_DIV_NUM_Pos = 0x0 + // Bit mask of PWDET_SAR_CLK_DIV_NUM field. + PCR_PWDET_SAR_CLK_CONF_PWDET_SAR_CLK_DIV_NUM_Msk = 0xff + // Position of PWDET_SAR_READER_EN field. + PCR_PWDET_SAR_CLK_CONF_PWDET_SAR_READER_EN_Pos = 0x8 + // Bit mask of PWDET_SAR_READER_EN field. + PCR_PWDET_SAR_CLK_CONF_PWDET_SAR_READER_EN_Msk = 0x100 + // Bit PWDET_SAR_READER_EN. + PCR_PWDET_SAR_CLK_CONF_PWDET_SAR_READER_EN = 0x100 + + // RESET_EVENT_BYPASS: reset event bypass backdoor configuration register + // Position of APM field. + PCR_RESET_EVENT_BYPASS_APM_Pos = 0x0 + // Bit mask of APM field. + PCR_RESET_EVENT_BYPASS_APM_Msk = 0x1 + // Bit APM. + PCR_RESET_EVENT_BYPASS_APM = 0x1 + // Position of RESET_EVENT_BYPASS field. + PCR_RESET_EVENT_BYPASS_RESET_EVENT_BYPASS_Pos = 0x1 + // Bit mask of RESET_EVENT_BYPASS field. + PCR_RESET_EVENT_BYPASS_RESET_EVENT_BYPASS_Msk = 0x2 + // Bit RESET_EVENT_BYPASS. + PCR_RESET_EVENT_BYPASS_RESET_EVENT_BYPASS = 0x2 + + // FPGA_DEBUG: fpga debug register + // Position of FPGA_DEBUG field. + PCR_FPGA_DEBUG_FPGA_DEBUG_Pos = 0x0 + // Bit mask of FPGA_DEBUG field. + PCR_FPGA_DEBUG_FPGA_DEBUG_Msk = 0xffffffff + + // CLOCK_GATE: PCR clock gating configure register + // Position of CLK_EN field. + PCR_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + PCR_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + PCR_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Date register. + // Position of DATE field. + PCR_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PCR_DATE_DATE_Msk = 0xfffffff +) + +// Constants for PMU: PMU Peripheral +const ( + // HP_ACTIVE_DIG_POWER: need_des + // Position of HP_ACTIVE_VDD_SPI_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN_Pos = 0x15 + // Bit mask of HP_ACTIVE_VDD_SPI_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN_Msk = 0x200000 + // Bit HP_ACTIVE_VDD_SPI_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_VDD_SPI_PD_EN = 0x200000 + // Position of HP_ACTIVE_HP_MEM_DSLP field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP_Pos = 0x16 + // Bit mask of HP_ACTIVE_HP_MEM_DSLP field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP_Msk = 0x400000 + // Bit HP_ACTIVE_HP_MEM_DSLP. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP = 0x400000 + // Position of HP_ACTIVE_PD_HP_MEM_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN_Pos = 0x17 + // Bit mask of HP_ACTIVE_PD_HP_MEM_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN_Msk = 0x7800000 + // Position of HP_ACTIVE_PD_HP_WIFI_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN_Pos = 0x1b + // Bit mask of HP_ACTIVE_PD_HP_WIFI_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN_Msk = 0x8000000 + // Bit HP_ACTIVE_PD_HP_WIFI_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_WIFI_PD_EN = 0x8000000 + // Position of HP_ACTIVE_PD_HP_CPU_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN_Pos = 0x1d + // Bit mask of HP_ACTIVE_PD_HP_CPU_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN_Msk = 0x20000000 + // Bit HP_ACTIVE_PD_HP_CPU_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_CPU_PD_EN = 0x20000000 + // Position of HP_ACTIVE_PD_HP_AON_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN_Pos = 0x1e + // Bit mask of HP_ACTIVE_PD_HP_AON_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN_Msk = 0x40000000 + // Bit HP_ACTIVE_PD_HP_AON_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_AON_PD_EN = 0x40000000 + // Position of HP_ACTIVE_PD_TOP_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN_Pos = 0x1f + // Bit mask of HP_ACTIVE_PD_TOP_PD_EN field. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN_Msk = 0x80000000 + // Bit HP_ACTIVE_PD_TOP_PD_EN. + PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN = 0x80000000 + + // HP_ACTIVE_ICG_HP_FUNC: need_des + // Position of HP_ACTIVE_DIG_ICG_FUNC_EN field. + PMU_HP_ACTIVE_ICG_HP_FUNC_HP_ACTIVE_DIG_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_ACTIVE_DIG_ICG_FUNC_EN field. + PMU_HP_ACTIVE_ICG_HP_FUNC_HP_ACTIVE_DIG_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_ACTIVE_ICG_HP_APB: need_des + // Position of HP_ACTIVE_DIG_ICG_APB_EN field. + PMU_HP_ACTIVE_ICG_HP_APB_HP_ACTIVE_DIG_ICG_APB_EN_Pos = 0x0 + // Bit mask of HP_ACTIVE_DIG_ICG_APB_EN field. + PMU_HP_ACTIVE_ICG_HP_APB_HP_ACTIVE_DIG_ICG_APB_EN_Msk = 0xffffffff + + // HP_ACTIVE_ICG_MODEM: need_des + // Position of HP_ACTIVE_DIG_ICG_MODEM_CODE field. + PMU_HP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE_Pos = 0x1e + // Bit mask of HP_ACTIVE_DIG_ICG_MODEM_CODE field. + PMU_HP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE_Msk = 0xc0000000 + + // HP_ACTIVE_HP_SYS_CNTL: need_des + // Position of HP_ACTIVE_UART_WAKEUP_EN field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN_Pos = 0x18 + // Bit mask of HP_ACTIVE_UART_WAKEUP_EN field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN_Msk = 0x1000000 + // Bit HP_ACTIVE_UART_WAKEUP_EN. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN = 0x1000000 + // Position of HP_ACTIVE_LP_PAD_HOLD_ALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL_Pos = 0x19 + // Bit mask of HP_ACTIVE_LP_PAD_HOLD_ALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL_Msk = 0x2000000 + // Bit HP_ACTIVE_LP_PAD_HOLD_ALL. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL = 0x2000000 + // Position of HP_ACTIVE_HP_PAD_HOLD_ALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL_Pos = 0x1a + // Bit mask of HP_ACTIVE_HP_PAD_HOLD_ALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL_Msk = 0x4000000 + // Bit HP_ACTIVE_HP_PAD_HOLD_ALL. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL = 0x4000000 + // Position of HP_ACTIVE_DIG_PAD_SLP_SEL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL_Pos = 0x1b + // Bit mask of HP_ACTIVE_DIG_PAD_SLP_SEL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL_Msk = 0x8000000 + // Bit HP_ACTIVE_DIG_PAD_SLP_SEL. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL = 0x8000000 + // Position of HP_ACTIVE_DIG_PAUSE_WDT field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT_Pos = 0x1c + // Bit mask of HP_ACTIVE_DIG_PAUSE_WDT field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT_Msk = 0x10000000 + // Bit HP_ACTIVE_DIG_PAUSE_WDT. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT = 0x10000000 + // Position of HP_ACTIVE_DIG_CPU_STALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL_Pos = 0x1d + // Bit mask of HP_ACTIVE_DIG_CPU_STALL field. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL_Msk = 0x20000000 + // Bit HP_ACTIVE_DIG_CPU_STALL. + PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL = 0x20000000 + + // HP_ACTIVE_HP_CK_POWER: need_des + // Position of HP_ACTIVE_I2C_ISO_EN field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN_Pos = 0x1a + // Bit mask of HP_ACTIVE_I2C_ISO_EN field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN_Msk = 0x4000000 + // Bit HP_ACTIVE_I2C_ISO_EN. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN = 0x4000000 + // Position of HP_ACTIVE_I2C_RETENTION field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION_Pos = 0x1b + // Bit mask of HP_ACTIVE_I2C_RETENTION field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION_Msk = 0x8000000 + // Bit HP_ACTIVE_I2C_RETENTION. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION = 0x8000000 + // Position of HP_ACTIVE_XPD_BB_I2C field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C_Pos = 0x1c + // Bit mask of HP_ACTIVE_XPD_BB_I2C field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C_Msk = 0x10000000 + // Bit HP_ACTIVE_XPD_BB_I2C. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BB_I2C = 0x10000000 + // Position of HP_ACTIVE_XPD_BBPLL_I2C field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C_Pos = 0x1d + // Bit mask of HP_ACTIVE_XPD_BBPLL_I2C field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C_Msk = 0x20000000 + // Bit HP_ACTIVE_XPD_BBPLL_I2C. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_I2C = 0x20000000 + // Position of HP_ACTIVE_XPD_BBPLL field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_Pos = 0x1e + // Bit mask of HP_ACTIVE_XPD_BBPLL field. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL_Msk = 0x40000000 + // Bit HP_ACTIVE_XPD_BBPLL. + PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_BBPLL = 0x40000000 + + // HP_ACTIVE_BIAS: need_des + // Position of HP_ACTIVE_XPD_TRX field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_TRX_Pos = 0x18 + // Bit mask of HP_ACTIVE_XPD_TRX field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_TRX_Msk = 0x1000000 + // Bit HP_ACTIVE_XPD_TRX. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_TRX = 0x1000000 + // Position of HP_ACTIVE_XPD_BIAS field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS_Pos = 0x19 + // Bit mask of HP_ACTIVE_XPD_BIAS field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS_Msk = 0x2000000 + // Bit HP_ACTIVE_XPD_BIAS. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS = 0x2000000 + // Position of HP_ACTIVE_PD_CUR field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR_Pos = 0x1e + // Bit mask of HP_ACTIVE_PD_CUR field. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR_Msk = 0x40000000 + // Bit HP_ACTIVE_PD_CUR. + PMU_HP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR = 0x40000000 + // Position of SLEEP field. + PMU_HP_ACTIVE_BIAS_SLEEP_Pos = 0x1f + // Bit mask of SLEEP field. + PMU_HP_ACTIVE_BIAS_SLEEP_Msk = 0x80000000 + // Bit SLEEP. + PMU_HP_ACTIVE_BIAS_SLEEP = 0x80000000 + + // HP_ACTIVE_BACKUP: need_des + // Position of HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_Pos = 0x4 + // Bit mask of HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_Msk = 0x30 + // Position of HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_Pos = 0x6 + // Bit mask of HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_Msk = 0xc0 + // Position of HP_ACTIVE_RETENTION_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE_Pos = 0xa + // Bit mask of HP_ACTIVE_RETENTION_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE_Msk = 0x400 + // Bit HP_ACTIVE_RETENTION_MODE. + PMU_HP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE = 0x400 + // Position of HP_SLEEP2ACTIVE_RETENTION_EN field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN_Pos = 0xb + // Bit mask of HP_SLEEP2ACTIVE_RETENTION_EN field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN_Msk = 0x800 + // Bit HP_SLEEP2ACTIVE_RETENTION_EN. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN = 0x800 + // Position of HP_MODEM2ACTIVE_RETENTION_EN field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN_Pos = 0xc + // Bit mask of HP_MODEM2ACTIVE_RETENTION_EN field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN_Msk = 0x1000 + // Bit HP_MODEM2ACTIVE_RETENTION_EN. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN = 0x1000 + // Position of HP_SLEEP2ACTIVE_BACKUP_CLK_SEL field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_Pos = 0xe + // Bit mask of HP_SLEEP2ACTIVE_BACKUP_CLK_SEL field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_Msk = 0xc000 + // Position of HP_MODEM2ACTIVE_BACKUP_CLK_SEL field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_Pos = 0x10 + // Bit mask of HP_MODEM2ACTIVE_BACKUP_CLK_SEL field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_Msk = 0x30000 + // Position of HP_SLEEP2ACTIVE_BACKUP_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE_Pos = 0x14 + // Bit mask of HP_SLEEP2ACTIVE_BACKUP_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE_Msk = 0x700000 + // Position of HP_MODEM2ACTIVE_BACKUP_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE_Pos = 0x17 + // Bit mask of HP_MODEM2ACTIVE_BACKUP_MODE field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE_Msk = 0x3800000 + // Position of HP_SLEEP2ACTIVE_BACKUP_EN field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN_Pos = 0x1d + // Bit mask of HP_SLEEP2ACTIVE_BACKUP_EN field. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN_Msk = 0x20000000 + // Bit HP_SLEEP2ACTIVE_BACKUP_EN. + PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN = 0x20000000 + // Position of HP_MODEM2ACTIVE_BACKUP_EN field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN_Pos = 0x1e + // Bit mask of HP_MODEM2ACTIVE_BACKUP_EN field. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN_Msk = 0x40000000 + // Bit HP_MODEM2ACTIVE_BACKUP_EN. + PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN = 0x40000000 + + // HP_ACTIVE_BACKUP_CLK: need_des + // Position of HP_ACTIVE_BACKUP_ICG_FUNC_EN field. + PMU_HP_ACTIVE_BACKUP_CLK_HP_ACTIVE_BACKUP_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_ACTIVE_BACKUP_ICG_FUNC_EN field. + PMU_HP_ACTIVE_BACKUP_CLK_HP_ACTIVE_BACKUP_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_ACTIVE_SYSCLK: need_des + // Position of HP_ACTIVE_DIG_SYS_CLK_NO_DIV field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_Pos = 0x1a + // Bit mask of HP_ACTIVE_DIG_SYS_CLK_NO_DIV field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_Msk = 0x4000000 + // Bit HP_ACTIVE_DIG_SYS_CLK_NO_DIV. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV = 0x4000000 + // Position of HP_ACTIVE_ICG_SYS_CLOCK_EN field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN_Pos = 0x1b + // Bit mask of HP_ACTIVE_ICG_SYS_CLOCK_EN field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN_Msk = 0x8000000 + // Bit HP_ACTIVE_ICG_SYS_CLOCK_EN. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN = 0x8000000 + // Position of HP_ACTIVE_SYS_CLK_SLP_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL_Pos = 0x1c + // Bit mask of HP_ACTIVE_SYS_CLK_SLP_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL_Msk = 0x10000000 + // Bit HP_ACTIVE_SYS_CLK_SLP_SEL. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL = 0x10000000 + // Position of HP_ACTIVE_ICG_SLP_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL_Pos = 0x1d + // Bit mask of HP_ACTIVE_ICG_SLP_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL_Msk = 0x20000000 + // Bit HP_ACTIVE_ICG_SLP_SEL. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL = 0x20000000 + // Position of HP_ACTIVE_DIG_SYS_CLK_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL_Pos = 0x1e + // Bit mask of HP_ACTIVE_DIG_SYS_CLK_SEL field. + PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL_Msk = 0xc0000000 + + // HP_ACTIVE_HP_REGULATOR0: need_des + // Position of HP_ACTIVE_HP_POWER_DET_BYPASS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_POWER_DET_BYPASS_Pos = 0x0 + // Bit mask of HP_ACTIVE_HP_POWER_DET_BYPASS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_POWER_DET_BYPASS_Msk = 0x1 + // Bit HP_ACTIVE_HP_POWER_DET_BYPASS. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_POWER_DET_BYPASS = 0x1 + // Position of LP_DBIAS_VOL field. + PMU_HP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL_Pos = 0x4 + // Bit mask of LP_DBIAS_VOL field. + PMU_HP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL_Msk = 0x1f0 + // Position of HP_DBIAS_VOL field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL_Pos = 0x9 + // Bit mask of HP_DBIAS_VOL field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL_Msk = 0x3e00 + // Position of DIG_REGULATOR0_DBIAS_SEL field. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL_Pos = 0xe + // Bit mask of DIG_REGULATOR0_DBIAS_SEL field. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL_Msk = 0x4000 + // Bit DIG_REGULATOR0_DBIAS_SEL. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL = 0x4000 + // Position of DIG_DBIAS_INIT field. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT_Pos = 0xf + // Bit mask of DIG_DBIAS_INIT field. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT_Msk = 0x8000 + // Bit DIG_DBIAS_INIT. + PMU_HP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT = 0x8000 + // Position of HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_Pos = 0x10 + // Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_Msk = 0x10000 + // Bit HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD = 0x10000 + // Position of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_Pos = 0x11 + // Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_Msk = 0x20000 + // Bit HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD = 0x20000 + // Position of HP_ACTIVE_HP_REGULATOR_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD_Pos = 0x12 + // Bit mask of HP_ACTIVE_HP_REGULATOR_XPD field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD_Msk = 0x40000 + // Bit HP_ACTIVE_HP_REGULATOR_XPD. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD = 0x40000 + // Position of HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_Pos = 0x13 + // Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_Msk = 0x780000 + // Position of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_Pos = 0x17 + // Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_Msk = 0x7800000 + // Position of HP_ACTIVE_HP_REGULATOR_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of HP_ACTIVE_HP_REGULATOR_DBIAS field. + PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // HP_ACTIVE_HP_REGULATOR1: need_des + // Position of HP_ACTIVE_HP_REGULATOR_DRV_B field. + PMU_HP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B_Pos = 0x8 + // Bit mask of HP_ACTIVE_HP_REGULATOR_DRV_B field. + PMU_HP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B_Msk = 0xffffff00 + + // HP_ACTIVE_XTAL: need_des + // Position of HP_ACTIVE_XPD_XTAL field. + PMU_HP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL_Pos = 0x1f + // Bit mask of HP_ACTIVE_XPD_XTAL field. + PMU_HP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL_Msk = 0x80000000 + // Bit HP_ACTIVE_XPD_XTAL. + PMU_HP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL = 0x80000000 + + // HP_MODEM_DIG_POWER: need_des + // Position of HP_MODEM_VDD_SPI_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN_Pos = 0x15 + // Bit mask of HP_MODEM_VDD_SPI_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN_Msk = 0x200000 + // Bit HP_MODEM_VDD_SPI_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_VDD_SPI_PD_EN = 0x200000 + // Position of HP_MODEM_HP_MEM_DSLP field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP_Pos = 0x16 + // Bit mask of HP_MODEM_HP_MEM_DSLP field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP_Msk = 0x400000 + // Bit HP_MODEM_HP_MEM_DSLP. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP = 0x400000 + // Position of HP_MODEM_PD_HP_MEM_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN_Pos = 0x17 + // Bit mask of HP_MODEM_PD_HP_MEM_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN_Msk = 0x7800000 + // Position of HP_MODEM_PD_HP_WIFI_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN_Pos = 0x1b + // Bit mask of HP_MODEM_PD_HP_WIFI_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN_Msk = 0x8000000 + // Bit HP_MODEM_PD_HP_WIFI_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN = 0x8000000 + // Position of HP_MODEM_PD_HP_CPU_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN_Pos = 0x1d + // Bit mask of HP_MODEM_PD_HP_CPU_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN_Msk = 0x20000000 + // Bit HP_MODEM_PD_HP_CPU_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN = 0x20000000 + // Position of HP_MODEM_PD_HP_AON_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN_Pos = 0x1e + // Bit mask of HP_MODEM_PD_HP_AON_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN_Msk = 0x40000000 + // Bit HP_MODEM_PD_HP_AON_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_AON_PD_EN = 0x40000000 + // Position of HP_MODEM_PD_TOP_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN_Pos = 0x1f + // Bit mask of HP_MODEM_PD_TOP_PD_EN field. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN_Msk = 0x80000000 + // Bit HP_MODEM_PD_TOP_PD_EN. + PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN = 0x80000000 + + // HP_MODEM_ICG_HP_FUNC: need_des + // Position of HP_MODEM_DIG_ICG_FUNC_EN field. + PMU_HP_MODEM_ICG_HP_FUNC_HP_MODEM_DIG_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_MODEM_DIG_ICG_FUNC_EN field. + PMU_HP_MODEM_ICG_HP_FUNC_HP_MODEM_DIG_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_MODEM_ICG_HP_APB: need_des + // Position of HP_MODEM_DIG_ICG_APB_EN field. + PMU_HP_MODEM_ICG_HP_APB_HP_MODEM_DIG_ICG_APB_EN_Pos = 0x0 + // Bit mask of HP_MODEM_DIG_ICG_APB_EN field. + PMU_HP_MODEM_ICG_HP_APB_HP_MODEM_DIG_ICG_APB_EN_Msk = 0xffffffff + + // HP_MODEM_ICG_MODEM: need_des + // Position of HP_MODEM_DIG_ICG_MODEM_CODE field. + PMU_HP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE_Pos = 0x1e + // Bit mask of HP_MODEM_DIG_ICG_MODEM_CODE field. + PMU_HP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE_Msk = 0xc0000000 + + // HP_MODEM_HP_SYS_CNTL: need_des + // Position of HP_MODEM_UART_WAKEUP_EN field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN_Pos = 0x18 + // Bit mask of HP_MODEM_UART_WAKEUP_EN field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN_Msk = 0x1000000 + // Bit HP_MODEM_UART_WAKEUP_EN. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN = 0x1000000 + // Position of HP_MODEM_LP_PAD_HOLD_ALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL_Pos = 0x19 + // Bit mask of HP_MODEM_LP_PAD_HOLD_ALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL_Msk = 0x2000000 + // Bit HP_MODEM_LP_PAD_HOLD_ALL. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL = 0x2000000 + // Position of HP_MODEM_HP_PAD_HOLD_ALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL_Pos = 0x1a + // Bit mask of HP_MODEM_HP_PAD_HOLD_ALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL_Msk = 0x4000000 + // Bit HP_MODEM_HP_PAD_HOLD_ALL. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL = 0x4000000 + // Position of HP_MODEM_DIG_PAD_SLP_SEL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL_Pos = 0x1b + // Bit mask of HP_MODEM_DIG_PAD_SLP_SEL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL_Msk = 0x8000000 + // Bit HP_MODEM_DIG_PAD_SLP_SEL. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL = 0x8000000 + // Position of HP_MODEM_DIG_PAUSE_WDT field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT_Pos = 0x1c + // Bit mask of HP_MODEM_DIG_PAUSE_WDT field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT_Msk = 0x10000000 + // Bit HP_MODEM_DIG_PAUSE_WDT. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT = 0x10000000 + // Position of HP_MODEM_DIG_CPU_STALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL_Pos = 0x1d + // Bit mask of HP_MODEM_DIG_CPU_STALL field. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL_Msk = 0x20000000 + // Bit HP_MODEM_DIG_CPU_STALL. + PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL = 0x20000000 + + // HP_MODEM_HP_CK_POWER: need_des + // Position of HP_MODEM_I2C_ISO_EN field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN_Pos = 0x1a + // Bit mask of HP_MODEM_I2C_ISO_EN field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN_Msk = 0x4000000 + // Bit HP_MODEM_I2C_ISO_EN. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN = 0x4000000 + // Position of HP_MODEM_I2C_RETENTION field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION_Pos = 0x1b + // Bit mask of HP_MODEM_I2C_RETENTION field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION_Msk = 0x8000000 + // Bit HP_MODEM_I2C_RETENTION. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION = 0x8000000 + // Position of HP_MODEM_XPD_BB_I2C field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C_Pos = 0x1c + // Bit mask of HP_MODEM_XPD_BB_I2C field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C_Msk = 0x10000000 + // Bit HP_MODEM_XPD_BB_I2C. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BB_I2C = 0x10000000 + // Position of HP_MODEM_XPD_BBPLL_I2C field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C_Pos = 0x1d + // Bit mask of HP_MODEM_XPD_BBPLL_I2C field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C_Msk = 0x20000000 + // Bit HP_MODEM_XPD_BBPLL_I2C. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_I2C = 0x20000000 + // Position of HP_MODEM_XPD_BBPLL field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_Pos = 0x1e + // Bit mask of HP_MODEM_XPD_BBPLL field. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL_Msk = 0x40000000 + // Bit HP_MODEM_XPD_BBPLL. + PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_BBPLL = 0x40000000 + + // HP_MODEM_BIAS: need_des + // Position of HP_MODEM_XPD_TRX field. + PMU_HP_MODEM_BIAS_HP_MODEM_XPD_TRX_Pos = 0x18 + // Bit mask of HP_MODEM_XPD_TRX field. + PMU_HP_MODEM_BIAS_HP_MODEM_XPD_TRX_Msk = 0x1000000 + // Bit HP_MODEM_XPD_TRX. + PMU_HP_MODEM_BIAS_HP_MODEM_XPD_TRX = 0x1000000 + // Position of HP_MODEM_XPD_BIAS field. + PMU_HP_MODEM_BIAS_HP_MODEM_XPD_BIAS_Pos = 0x19 + // Bit mask of HP_MODEM_XPD_BIAS field. + PMU_HP_MODEM_BIAS_HP_MODEM_XPD_BIAS_Msk = 0x2000000 + // Bit HP_MODEM_XPD_BIAS. + PMU_HP_MODEM_BIAS_HP_MODEM_XPD_BIAS = 0x2000000 + // Position of HP_MODEM_PD_CUR field. + PMU_HP_MODEM_BIAS_HP_MODEM_PD_CUR_Pos = 0x1e + // Bit mask of HP_MODEM_PD_CUR field. + PMU_HP_MODEM_BIAS_HP_MODEM_PD_CUR_Msk = 0x40000000 + // Bit HP_MODEM_PD_CUR. + PMU_HP_MODEM_BIAS_HP_MODEM_PD_CUR = 0x40000000 + // Position of SLEEP field. + PMU_HP_MODEM_BIAS_SLEEP_Pos = 0x1f + // Bit mask of SLEEP field. + PMU_HP_MODEM_BIAS_SLEEP_Msk = 0x80000000 + // Bit SLEEP. + PMU_HP_MODEM_BIAS_SLEEP = 0x80000000 + + // HP_MODEM_BACKUP: need_des + // Position of HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_Pos = 0x4 + // Bit mask of HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_Msk = 0x30 + // Position of HP_MODEM_RETENTION_MODE field. + PMU_HP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE_Pos = 0xa + // Bit mask of HP_MODEM_RETENTION_MODE field. + PMU_HP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE_Msk = 0x400 + // Bit HP_MODEM_RETENTION_MODE. + PMU_HP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE = 0x400 + // Position of HP_SLEEP2MODEM_RETENTION_EN field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN_Pos = 0xb + // Bit mask of HP_SLEEP2MODEM_RETENTION_EN field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN_Msk = 0x800 + // Bit HP_SLEEP2MODEM_RETENTION_EN. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN = 0x800 + // Position of HP_SLEEP2MODEM_BACKUP_CLK_SEL field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL_Pos = 0xe + // Bit mask of HP_SLEEP2MODEM_BACKUP_CLK_SEL field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL_Msk = 0xc000 + // Position of HP_SLEEP2MODEM_BACKUP_MODE field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE_Pos = 0x14 + // Bit mask of HP_SLEEP2MODEM_BACKUP_MODE field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE_Msk = 0x700000 + // Position of HP_SLEEP2MODEM_BACKUP_EN field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN_Pos = 0x1d + // Bit mask of HP_SLEEP2MODEM_BACKUP_EN field. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN_Msk = 0x20000000 + // Bit HP_SLEEP2MODEM_BACKUP_EN. + PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN = 0x20000000 + + // HP_MODEM_BACKUP_CLK: need_des + // Position of HP_MODEM_BACKUP_ICG_FUNC_EN field. + PMU_HP_MODEM_BACKUP_CLK_HP_MODEM_BACKUP_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_MODEM_BACKUP_ICG_FUNC_EN field. + PMU_HP_MODEM_BACKUP_CLK_HP_MODEM_BACKUP_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_MODEM_SYSCLK: need_des + // Position of HP_MODEM_DIG_SYS_CLK_NO_DIV field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV_Pos = 0x1a + // Bit mask of HP_MODEM_DIG_SYS_CLK_NO_DIV field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV_Msk = 0x4000000 + // Bit HP_MODEM_DIG_SYS_CLK_NO_DIV. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV = 0x4000000 + // Position of HP_MODEM_ICG_SYS_CLOCK_EN field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN_Pos = 0x1b + // Bit mask of HP_MODEM_ICG_SYS_CLOCK_EN field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN_Msk = 0x8000000 + // Bit HP_MODEM_ICG_SYS_CLOCK_EN. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN = 0x8000000 + // Position of HP_MODEM_SYS_CLK_SLP_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL_Pos = 0x1c + // Bit mask of HP_MODEM_SYS_CLK_SLP_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL_Msk = 0x10000000 + // Bit HP_MODEM_SYS_CLK_SLP_SEL. + PMU_HP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL = 0x10000000 + // Position of HP_MODEM_ICG_SLP_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL_Pos = 0x1d + // Bit mask of HP_MODEM_ICG_SLP_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL_Msk = 0x20000000 + // Bit HP_MODEM_ICG_SLP_SEL. + PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL = 0x20000000 + // Position of HP_MODEM_DIG_SYS_CLK_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL_Pos = 0x1e + // Bit mask of HP_MODEM_DIG_SYS_CLK_SEL field. + PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL_Msk = 0xc0000000 + + // HP_MODEM_HP_REGULATOR0: need_des + // Position of HP_MODEM_HP_POWER_DET_BYPASS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_POWER_DET_BYPASS_Pos = 0x0 + // Bit mask of HP_MODEM_HP_POWER_DET_BYPASS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_POWER_DET_BYPASS_Msk = 0x1 + // Bit HP_MODEM_HP_POWER_DET_BYPASS. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_POWER_DET_BYPASS = 0x1 + // Position of HP_MODEM_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_Pos = 0x10 + // Bit mask of HP_MODEM_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_Msk = 0x10000 + // Bit HP_MODEM_HP_REGULATOR_SLP_MEM_XPD. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD = 0x10000 + // Position of HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_Pos = 0x11 + // Bit mask of HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_Msk = 0x20000 + // Bit HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD = 0x20000 + // Position of HP_MODEM_HP_REGULATOR_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD_Pos = 0x12 + // Bit mask of HP_MODEM_HP_REGULATOR_XPD field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD_Msk = 0x40000 + // Bit HP_MODEM_HP_REGULATOR_XPD. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD = 0x40000 + // Position of HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_Pos = 0x13 + // Bit mask of HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_Msk = 0x780000 + // Position of HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_Pos = 0x17 + // Bit mask of HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_Msk = 0x7800000 + // Position of HP_MODEM_HP_REGULATOR_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of HP_MODEM_HP_REGULATOR_DBIAS field. + PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // HP_MODEM_HP_REGULATOR1: need_des + // Position of HP_MODEM_HP_REGULATOR_DRV_B field. + PMU_HP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B_Pos = 0x8 + // Bit mask of HP_MODEM_HP_REGULATOR_DRV_B field. + PMU_HP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B_Msk = 0xffffff00 + + // HP_MODEM_XTAL: need_des + // Position of HP_MODEM_XPD_XTAL field. + PMU_HP_MODEM_XTAL_HP_MODEM_XPD_XTAL_Pos = 0x1f + // Bit mask of HP_MODEM_XPD_XTAL field. + PMU_HP_MODEM_XTAL_HP_MODEM_XPD_XTAL_Msk = 0x80000000 + // Bit HP_MODEM_XPD_XTAL. + PMU_HP_MODEM_XTAL_HP_MODEM_XPD_XTAL = 0x80000000 + + // HP_SLEEP_DIG_POWER: need_des + // Position of HP_SLEEP_VDD_SPI_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN_Pos = 0x15 + // Bit mask of HP_SLEEP_VDD_SPI_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN_Msk = 0x200000 + // Bit HP_SLEEP_VDD_SPI_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_VDD_SPI_PD_EN = 0x200000 + // Position of HP_SLEEP_HP_MEM_DSLP field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP_Pos = 0x16 + // Bit mask of HP_SLEEP_HP_MEM_DSLP field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP_Msk = 0x400000 + // Bit HP_SLEEP_HP_MEM_DSLP. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP = 0x400000 + // Position of HP_SLEEP_PD_HP_MEM_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN_Pos = 0x17 + // Bit mask of HP_SLEEP_PD_HP_MEM_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN_Msk = 0x7800000 + // Position of HP_SLEEP_PD_HP_WIFI_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN_Pos = 0x1b + // Bit mask of HP_SLEEP_PD_HP_WIFI_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN_Msk = 0x8000000 + // Bit HP_SLEEP_PD_HP_WIFI_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_WIFI_PD_EN = 0x8000000 + // Position of HP_SLEEP_PD_HP_CPU_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN_Pos = 0x1d + // Bit mask of HP_SLEEP_PD_HP_CPU_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN_Msk = 0x20000000 + // Bit HP_SLEEP_PD_HP_CPU_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_CPU_PD_EN = 0x20000000 + // Position of HP_SLEEP_PD_HP_AON_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN_Pos = 0x1e + // Bit mask of HP_SLEEP_PD_HP_AON_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN_Msk = 0x40000000 + // Bit HP_SLEEP_PD_HP_AON_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_AON_PD_EN = 0x40000000 + // Position of HP_SLEEP_PD_TOP_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN_Pos = 0x1f + // Bit mask of HP_SLEEP_PD_TOP_PD_EN field. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN_Msk = 0x80000000 + // Bit HP_SLEEP_PD_TOP_PD_EN. + PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN = 0x80000000 + + // HP_SLEEP_ICG_HP_FUNC: need_des + // Position of HP_SLEEP_DIG_ICG_FUNC_EN field. + PMU_HP_SLEEP_ICG_HP_FUNC_HP_SLEEP_DIG_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_SLEEP_DIG_ICG_FUNC_EN field. + PMU_HP_SLEEP_ICG_HP_FUNC_HP_SLEEP_DIG_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_SLEEP_ICG_HP_APB: need_des + // Position of HP_SLEEP_DIG_ICG_APB_EN field. + PMU_HP_SLEEP_ICG_HP_APB_HP_SLEEP_DIG_ICG_APB_EN_Pos = 0x0 + // Bit mask of HP_SLEEP_DIG_ICG_APB_EN field. + PMU_HP_SLEEP_ICG_HP_APB_HP_SLEEP_DIG_ICG_APB_EN_Msk = 0xffffffff + + // HP_SLEEP_ICG_MODEM: need_des + // Position of HP_SLEEP_DIG_ICG_MODEM_CODE field. + PMU_HP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE_Pos = 0x1e + // Bit mask of HP_SLEEP_DIG_ICG_MODEM_CODE field. + PMU_HP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE_Msk = 0xc0000000 + + // HP_SLEEP_HP_SYS_CNTL: need_des + // Position of HP_SLEEP_UART_WAKEUP_EN field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN_Pos = 0x18 + // Bit mask of HP_SLEEP_UART_WAKEUP_EN field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN_Msk = 0x1000000 + // Bit HP_SLEEP_UART_WAKEUP_EN. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN = 0x1000000 + // Position of HP_SLEEP_LP_PAD_HOLD_ALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL_Pos = 0x19 + // Bit mask of HP_SLEEP_LP_PAD_HOLD_ALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL_Msk = 0x2000000 + // Bit HP_SLEEP_LP_PAD_HOLD_ALL. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL = 0x2000000 + // Position of HP_SLEEP_HP_PAD_HOLD_ALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL_Pos = 0x1a + // Bit mask of HP_SLEEP_HP_PAD_HOLD_ALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL_Msk = 0x4000000 + // Bit HP_SLEEP_HP_PAD_HOLD_ALL. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL = 0x4000000 + // Position of HP_SLEEP_DIG_PAD_SLP_SEL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL_Pos = 0x1b + // Bit mask of HP_SLEEP_DIG_PAD_SLP_SEL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL_Msk = 0x8000000 + // Bit HP_SLEEP_DIG_PAD_SLP_SEL. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL = 0x8000000 + // Position of HP_SLEEP_DIG_PAUSE_WDT field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT_Pos = 0x1c + // Bit mask of HP_SLEEP_DIG_PAUSE_WDT field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT_Msk = 0x10000000 + // Bit HP_SLEEP_DIG_PAUSE_WDT. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT = 0x10000000 + // Position of HP_SLEEP_DIG_CPU_STALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL_Pos = 0x1d + // Bit mask of HP_SLEEP_DIG_CPU_STALL field. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL_Msk = 0x20000000 + // Bit HP_SLEEP_DIG_CPU_STALL. + PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL = 0x20000000 + + // HP_SLEEP_HP_CK_POWER: need_des + // Position of HP_SLEEP_I2C_ISO_EN field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN_Pos = 0x1a + // Bit mask of HP_SLEEP_I2C_ISO_EN field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN_Msk = 0x4000000 + // Bit HP_SLEEP_I2C_ISO_EN. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN = 0x4000000 + // Position of HP_SLEEP_I2C_RETENTION field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION_Pos = 0x1b + // Bit mask of HP_SLEEP_I2C_RETENTION field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION_Msk = 0x8000000 + // Bit HP_SLEEP_I2C_RETENTION. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION = 0x8000000 + // Position of HP_SLEEP_XPD_BB_I2C field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C_Pos = 0x1c + // Bit mask of HP_SLEEP_XPD_BB_I2C field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C_Msk = 0x10000000 + // Bit HP_SLEEP_XPD_BB_I2C. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BB_I2C = 0x10000000 + // Position of HP_SLEEP_XPD_BBPLL_I2C field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C_Pos = 0x1d + // Bit mask of HP_SLEEP_XPD_BBPLL_I2C field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C_Msk = 0x20000000 + // Bit HP_SLEEP_XPD_BBPLL_I2C. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_I2C = 0x20000000 + // Position of HP_SLEEP_XPD_BBPLL field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_Pos = 0x1e + // Bit mask of HP_SLEEP_XPD_BBPLL field. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL_Msk = 0x40000000 + // Bit HP_SLEEP_XPD_BBPLL. + PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_BBPLL = 0x40000000 + + // HP_SLEEP_BIAS: need_des + // Position of HP_SLEEP_XPD_TRX field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_TRX_Pos = 0x18 + // Bit mask of HP_SLEEP_XPD_TRX field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_TRX_Msk = 0x1000000 + // Bit HP_SLEEP_XPD_TRX. + PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_TRX = 0x1000000 + // Position of HP_SLEEP_XPD_BIAS field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS_Pos = 0x19 + // Bit mask of HP_SLEEP_XPD_BIAS field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS_Msk = 0x2000000 + // Bit HP_SLEEP_XPD_BIAS. + PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS = 0x2000000 + // Position of HP_SLEEP_PD_CUR field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_PD_CUR_Pos = 0x1e + // Bit mask of HP_SLEEP_PD_CUR field. + PMU_HP_SLEEP_BIAS_HP_SLEEP_PD_CUR_Msk = 0x40000000 + // Bit HP_SLEEP_PD_CUR. + PMU_HP_SLEEP_BIAS_HP_SLEEP_PD_CUR = 0x40000000 + // Position of SLEEP field. + PMU_HP_SLEEP_BIAS_SLEEP_Pos = 0x1f + // Bit mask of SLEEP field. + PMU_HP_SLEEP_BIAS_SLEEP_Msk = 0x80000000 + // Bit SLEEP. + PMU_HP_SLEEP_BIAS_SLEEP = 0x80000000 + + // HP_SLEEP_BACKUP: need_des + // Position of HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_Pos = 0x6 + // Bit mask of HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_Msk = 0xc0 + // Position of HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_Pos = 0x8 + // Bit mask of HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_Msk = 0x300 + // Position of HP_SLEEP_RETENTION_MODE field. + PMU_HP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE_Pos = 0xa + // Bit mask of HP_SLEEP_RETENTION_MODE field. + PMU_HP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE_Msk = 0x400 + // Bit HP_SLEEP_RETENTION_MODE. + PMU_HP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE = 0x400 + // Position of HP_MODEM2SLEEP_RETENTION_EN field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN_Pos = 0xc + // Bit mask of HP_MODEM2SLEEP_RETENTION_EN field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN_Msk = 0x1000 + // Bit HP_MODEM2SLEEP_RETENTION_EN. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN = 0x1000 + // Position of HP_ACTIVE2SLEEP_RETENTION_EN field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN_Pos = 0xd + // Bit mask of HP_ACTIVE2SLEEP_RETENTION_EN field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN_Msk = 0x2000 + // Bit HP_ACTIVE2SLEEP_RETENTION_EN. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN = 0x2000 + // Position of HP_MODEM2SLEEP_BACKUP_CLK_SEL field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL_Pos = 0x10 + // Bit mask of HP_MODEM2SLEEP_BACKUP_CLK_SEL field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL_Msk = 0x30000 + // Position of HP_ACTIVE2SLEEP_BACKUP_CLK_SEL field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_Pos = 0x12 + // Bit mask of HP_ACTIVE2SLEEP_BACKUP_CLK_SEL field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_Msk = 0xc0000 + // Position of HP_MODEM2SLEEP_BACKUP_MODE field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE_Pos = 0x17 + // Bit mask of HP_MODEM2SLEEP_BACKUP_MODE field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE_Msk = 0x3800000 + // Position of HP_ACTIVE2SLEEP_BACKUP_MODE field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE_Pos = 0x1a + // Bit mask of HP_ACTIVE2SLEEP_BACKUP_MODE field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE_Msk = 0x1c000000 + // Position of HP_MODEM2SLEEP_BACKUP_EN field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN_Pos = 0x1e + // Bit mask of HP_MODEM2SLEEP_BACKUP_EN field. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN_Msk = 0x40000000 + // Bit HP_MODEM2SLEEP_BACKUP_EN. + PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN = 0x40000000 + // Position of HP_ACTIVE2SLEEP_BACKUP_EN field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN_Pos = 0x1f + // Bit mask of HP_ACTIVE2SLEEP_BACKUP_EN field. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN_Msk = 0x80000000 + // Bit HP_ACTIVE2SLEEP_BACKUP_EN. + PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN = 0x80000000 + + // HP_SLEEP_BACKUP_CLK: need_des + // Position of HP_SLEEP_BACKUP_ICG_FUNC_EN field. + PMU_HP_SLEEP_BACKUP_CLK_HP_SLEEP_BACKUP_ICG_FUNC_EN_Pos = 0x0 + // Bit mask of HP_SLEEP_BACKUP_ICG_FUNC_EN field. + PMU_HP_SLEEP_BACKUP_CLK_HP_SLEEP_BACKUP_ICG_FUNC_EN_Msk = 0xffffffff + + // HP_SLEEP_SYSCLK: need_des + // Position of HP_SLEEP_DIG_SYS_CLK_NO_DIV field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV_Pos = 0x1a + // Bit mask of HP_SLEEP_DIG_SYS_CLK_NO_DIV field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV_Msk = 0x4000000 + // Bit HP_SLEEP_DIG_SYS_CLK_NO_DIV. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV = 0x4000000 + // Position of HP_SLEEP_ICG_SYS_CLOCK_EN field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN_Pos = 0x1b + // Bit mask of HP_SLEEP_ICG_SYS_CLOCK_EN field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN_Msk = 0x8000000 + // Bit HP_SLEEP_ICG_SYS_CLOCK_EN. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN = 0x8000000 + // Position of HP_SLEEP_SYS_CLK_SLP_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL_Pos = 0x1c + // Bit mask of HP_SLEEP_SYS_CLK_SLP_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL_Msk = 0x10000000 + // Bit HP_SLEEP_SYS_CLK_SLP_SEL. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL = 0x10000000 + // Position of HP_SLEEP_ICG_SLP_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL_Pos = 0x1d + // Bit mask of HP_SLEEP_ICG_SLP_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL_Msk = 0x20000000 + // Bit HP_SLEEP_ICG_SLP_SEL. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL = 0x20000000 + // Position of HP_SLEEP_DIG_SYS_CLK_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL_Pos = 0x1e + // Bit mask of HP_SLEEP_DIG_SYS_CLK_SEL field. + PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL_Msk = 0xc0000000 + + // HP_SLEEP_HP_REGULATOR0: need_des + // Position of HP_SLEEP_HP_POWER_DET_BYPASS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_POWER_DET_BYPASS_Pos = 0x0 + // Bit mask of HP_SLEEP_HP_POWER_DET_BYPASS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_POWER_DET_BYPASS_Msk = 0x1 + // Bit HP_SLEEP_HP_POWER_DET_BYPASS. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_POWER_DET_BYPASS = 0x1 + // Position of HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_Pos = 0x10 + // Bit mask of HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_Msk = 0x10000 + // Bit HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD = 0x10000 + // Position of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_Pos = 0x11 + // Bit mask of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_Msk = 0x20000 + // Bit HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD = 0x20000 + // Position of HP_SLEEP_HP_REGULATOR_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD_Pos = 0x12 + // Bit mask of HP_SLEEP_HP_REGULATOR_XPD field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD_Msk = 0x40000 + // Bit HP_SLEEP_HP_REGULATOR_XPD. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD = 0x40000 + // Position of HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_Pos = 0x13 + // Bit mask of HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_Msk = 0x780000 + // Position of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_Pos = 0x17 + // Bit mask of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_Msk = 0x7800000 + // Position of HP_SLEEP_HP_REGULATOR_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of HP_SLEEP_HP_REGULATOR_DBIAS field. + PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // HP_SLEEP_HP_REGULATOR1: need_des + // Position of HP_SLEEP_HP_REGULATOR_DRV_B field. + PMU_HP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B_Pos = 0x8 + // Bit mask of HP_SLEEP_HP_REGULATOR_DRV_B field. + PMU_HP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B_Msk = 0xffffff00 + + // HP_SLEEP_XTAL: need_des + // Position of HP_SLEEP_XPD_XTAL field. + PMU_HP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL_Pos = 0x1f + // Bit mask of HP_SLEEP_XPD_XTAL field. + PMU_HP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL_Msk = 0x80000000 + // Bit HP_SLEEP_XPD_XTAL. + PMU_HP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL = 0x80000000 + + // HP_SLEEP_LP_REGULATOR0: need_des + // Position of HP_SLEEP_LP_REGULATOR_SLP_XPD field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD_Pos = 0x15 + // Bit mask of HP_SLEEP_LP_REGULATOR_SLP_XPD field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD_Msk = 0x200000 + // Bit HP_SLEEP_LP_REGULATOR_SLP_XPD. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD = 0x200000 + // Position of HP_SLEEP_LP_REGULATOR_XPD field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD_Pos = 0x16 + // Bit mask of HP_SLEEP_LP_REGULATOR_XPD field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD_Msk = 0x400000 + // Bit HP_SLEEP_LP_REGULATOR_XPD. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD = 0x400000 + // Position of HP_SLEEP_LP_REGULATOR_SLP_DBIAS field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_Pos = 0x17 + // Bit mask of HP_SLEEP_LP_REGULATOR_SLP_DBIAS field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_Msk = 0x7800000 + // Position of HP_SLEEP_LP_REGULATOR_DBIAS field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of HP_SLEEP_LP_REGULATOR_DBIAS field. + PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // HP_SLEEP_LP_REGULATOR1: need_des + // Position of HP_SLEEP_LP_REGULATOR_DRV_B field. + PMU_HP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B_Pos = 0x1c + // Bit mask of HP_SLEEP_LP_REGULATOR_DRV_B field. + PMU_HP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B_Msk = 0xf0000000 + + // HP_SLEEP_LP_DCDC_RESERVE: need_des + // Position of HP_SLEEP_LP_DCDC_RESERVE field. + PMU_HP_SLEEP_LP_DCDC_RESERVE_HP_SLEEP_LP_DCDC_RESERVE_Pos = 0x0 + // Bit mask of HP_SLEEP_LP_DCDC_RESERVE field. + PMU_HP_SLEEP_LP_DCDC_RESERVE_HP_SLEEP_LP_DCDC_RESERVE_Msk = 0xffffffff + + // HP_SLEEP_LP_DIG_POWER: need_des + // Position of HP_SLEEP_BOD_SOURCE_SEL field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL_Pos = 0x1b + // Bit mask of HP_SLEEP_BOD_SOURCE_SEL field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL_Msk = 0x8000000 + // Bit HP_SLEEP_BOD_SOURCE_SEL. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL = 0x8000000 + // Position of HP_SLEEP_VDDBAT_MODE field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE_Pos = 0x1c + // Bit mask of HP_SLEEP_VDDBAT_MODE field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE_Msk = 0x30000000 + // Position of HP_SLEEP_LP_MEM_DSLP field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP_Pos = 0x1e + // Bit mask of HP_SLEEP_LP_MEM_DSLP field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP_Msk = 0x40000000 + // Bit HP_SLEEP_LP_MEM_DSLP. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP = 0x40000000 + // Position of HP_SLEEP_PD_LP_PERI_PD_EN field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN_Pos = 0x1f + // Bit mask of HP_SLEEP_PD_LP_PERI_PD_EN field. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN_Msk = 0x80000000 + // Bit HP_SLEEP_PD_LP_PERI_PD_EN. + PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN = 0x80000000 + + // HP_SLEEP_LP_CK_POWER: need_des + // Position of HP_SLEEP_XPD_LPPLL field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL_Pos = 0x1b + // Bit mask of HP_SLEEP_XPD_LPPLL field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL_Msk = 0x8000000 + // Bit HP_SLEEP_XPD_LPPLL. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL = 0x8000000 + // Position of HP_SLEEP_XPD_XTAL32K field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K_Pos = 0x1c + // Bit mask of HP_SLEEP_XPD_XTAL32K field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K_Msk = 0x10000000 + // Bit HP_SLEEP_XPD_XTAL32K. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K = 0x10000000 + // Position of HP_SLEEP_XPD_RC32K field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K_Pos = 0x1d + // Bit mask of HP_SLEEP_XPD_RC32K field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K_Msk = 0x20000000 + // Bit HP_SLEEP_XPD_RC32K. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K = 0x20000000 + // Position of HP_SLEEP_XPD_FOSC_CLK field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK_Pos = 0x1e + // Bit mask of HP_SLEEP_XPD_FOSC_CLK field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK_Msk = 0x40000000 + // Bit HP_SLEEP_XPD_FOSC_CLK. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK = 0x40000000 + // Position of HP_SLEEP_PD_OSC_CLK field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK_Pos = 0x1f + // Bit mask of HP_SLEEP_PD_OSC_CLK field. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK_Msk = 0x80000000 + // Bit HP_SLEEP_PD_OSC_CLK. + PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK = 0x80000000 + + // LP_SLEEP_LP_BIAS_RESERVE: need_des + // Position of LP_SLEEP_LP_BIAS_RESERVE field. + PMU_LP_SLEEP_LP_BIAS_RESERVE_LP_SLEEP_LP_BIAS_RESERVE_Pos = 0x0 + // Bit mask of LP_SLEEP_LP_BIAS_RESERVE field. + PMU_LP_SLEEP_LP_BIAS_RESERVE_LP_SLEEP_LP_BIAS_RESERVE_Msk = 0xffffffff + + // LP_SLEEP_LP_REGULATOR0: need_des + // Position of LP_SLEEP_LP_REGULATOR_SLP_XPD field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD_Pos = 0x15 + // Bit mask of LP_SLEEP_LP_REGULATOR_SLP_XPD field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD_Msk = 0x200000 + // Bit LP_SLEEP_LP_REGULATOR_SLP_XPD. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD = 0x200000 + // Position of LP_SLEEP_LP_REGULATOR_XPD field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD_Pos = 0x16 + // Bit mask of LP_SLEEP_LP_REGULATOR_XPD field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD_Msk = 0x400000 + // Bit LP_SLEEP_LP_REGULATOR_XPD. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD = 0x400000 + // Position of LP_SLEEP_LP_REGULATOR_SLP_DBIAS field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_Pos = 0x17 + // Bit mask of LP_SLEEP_LP_REGULATOR_SLP_DBIAS field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_Msk = 0x7800000 + // Position of LP_SLEEP_LP_REGULATOR_DBIAS field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS_Pos = 0x1b + // Bit mask of LP_SLEEP_LP_REGULATOR_DBIAS field. + PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS_Msk = 0xf8000000 + + // LP_SLEEP_LP_REGULATOR1: need_des + // Position of LP_SLEEP_LP_REGULATOR_DRV_B field. + PMU_LP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B_Pos = 0x1c + // Bit mask of LP_SLEEP_LP_REGULATOR_DRV_B field. + PMU_LP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B_Msk = 0xf0000000 + + // LP_SLEEP_XTAL: need_des + // Position of LP_SLEEP_XPD_XTAL field. + PMU_LP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL_Pos = 0x1f + // Bit mask of LP_SLEEP_XPD_XTAL field. + PMU_LP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL_Msk = 0x80000000 + // Bit LP_SLEEP_XPD_XTAL. + PMU_LP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL = 0x80000000 + + // LP_SLEEP_LP_DIG_POWER: need_des + // Position of LP_SLEEP_BOD_SOURCE_SEL field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL_Pos = 0x1b + // Bit mask of LP_SLEEP_BOD_SOURCE_SEL field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL_Msk = 0x8000000 + // Bit LP_SLEEP_BOD_SOURCE_SEL. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL = 0x8000000 + // Position of LP_SLEEP_VDDBAT_MODE field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE_Pos = 0x1c + // Bit mask of LP_SLEEP_VDDBAT_MODE field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE_Msk = 0x30000000 + // Position of LP_SLEEP_LP_MEM_DSLP field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP_Pos = 0x1e + // Bit mask of LP_SLEEP_LP_MEM_DSLP field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP_Msk = 0x40000000 + // Bit LP_SLEEP_LP_MEM_DSLP. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP = 0x40000000 + // Position of LP_SLEEP_PD_LP_PERI_PD_EN field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN_Pos = 0x1f + // Bit mask of LP_SLEEP_PD_LP_PERI_PD_EN field. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN_Msk = 0x80000000 + // Bit LP_SLEEP_PD_LP_PERI_PD_EN. + PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN = 0x80000000 + + // LP_SLEEP_LP_CK_POWER: need_des + // Position of LP_SLEEP_XPD_LPPLL field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL_Pos = 0x1b + // Bit mask of LP_SLEEP_XPD_LPPLL field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL_Msk = 0x8000000 + // Bit LP_SLEEP_XPD_LPPLL. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL = 0x8000000 + // Position of LP_SLEEP_XPD_XTAL32K field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K_Pos = 0x1c + // Bit mask of LP_SLEEP_XPD_XTAL32K field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K_Msk = 0x10000000 + // Bit LP_SLEEP_XPD_XTAL32K. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K = 0x10000000 + // Position of LP_SLEEP_XPD_RC32K field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K_Pos = 0x1d + // Bit mask of LP_SLEEP_XPD_RC32K field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K_Msk = 0x20000000 + // Bit LP_SLEEP_XPD_RC32K. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K = 0x20000000 + // Position of LP_SLEEP_XPD_FOSC_CLK field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK_Pos = 0x1e + // Bit mask of LP_SLEEP_XPD_FOSC_CLK field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK_Msk = 0x40000000 + // Bit LP_SLEEP_XPD_FOSC_CLK. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK = 0x40000000 + // Position of LP_SLEEP_PD_OSC_CLK field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK_Pos = 0x1f + // Bit mask of LP_SLEEP_PD_OSC_CLK field. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK_Msk = 0x80000000 + // Bit LP_SLEEP_PD_OSC_CLK. + PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK = 0x80000000 + + // LP_SLEEP_BIAS: need_des + // Position of LP_SLEEP_XPD_BIAS field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS_Pos = 0x19 + // Bit mask of LP_SLEEP_XPD_BIAS field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS_Msk = 0x2000000 + // Bit LP_SLEEP_XPD_BIAS. + PMU_LP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS = 0x2000000 + // Position of LP_SLEEP_PD_CUR field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_PD_CUR_Pos = 0x1e + // Bit mask of LP_SLEEP_PD_CUR field. + PMU_LP_SLEEP_BIAS_LP_SLEEP_PD_CUR_Msk = 0x40000000 + // Bit LP_SLEEP_PD_CUR. + PMU_LP_SLEEP_BIAS_LP_SLEEP_PD_CUR = 0x40000000 + // Position of SLEEP field. + PMU_LP_SLEEP_BIAS_SLEEP_Pos = 0x1f + // Bit mask of SLEEP field. + PMU_LP_SLEEP_BIAS_SLEEP_Msk = 0x80000000 + // Bit SLEEP. + PMU_LP_SLEEP_BIAS_SLEEP = 0x80000000 + + // IMM_HP_CK_POWER: need_des + // Position of TIE_LOW_GLOBAL_BBPLL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG_Pos = 0x0 + // Bit mask of TIE_LOW_GLOBAL_BBPLL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG_Msk = 0x1 + // Bit TIE_LOW_GLOBAL_BBPLL_ICG. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_BBPLL_ICG = 0x1 + // Position of TIE_LOW_GLOBAL_XTAL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG_Pos = 0x1 + // Bit mask of TIE_LOW_GLOBAL_XTAL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG_Msk = 0x2 + // Bit TIE_LOW_GLOBAL_XTAL_ICG. + PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG = 0x2 + // Position of TIE_LOW_I2C_RETENTION field. + PMU_IMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION_Pos = 0x2 + // Bit mask of TIE_LOW_I2C_RETENTION field. + PMU_IMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION_Msk = 0x4 + // Bit TIE_LOW_I2C_RETENTION. + PMU_IMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION = 0x4 + // Position of TIE_LOW_XPD_BB_I2C field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C_Pos = 0x3 + // Bit mask of TIE_LOW_XPD_BB_I2C field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C_Msk = 0x8 + // Bit TIE_LOW_XPD_BB_I2C. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BB_I2C = 0x8 + // Position of TIE_LOW_XPD_BBPLL_I2C field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C_Pos = 0x4 + // Bit mask of TIE_LOW_XPD_BBPLL_I2C field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C_Msk = 0x10 + // Bit TIE_LOW_XPD_BBPLL_I2C. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_I2C = 0x10 + // Position of TIE_LOW_XPD_BBPLL field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_Pos = 0x5 + // Bit mask of TIE_LOW_XPD_BBPLL field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL_Msk = 0x20 + // Bit TIE_LOW_XPD_BBPLL. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_BBPLL = 0x20 + // Position of TIE_LOW_XPD_XTAL field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_XTAL_Pos = 0x6 + // Bit mask of TIE_LOW_XPD_XTAL field. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_XTAL_Msk = 0x40 + // Bit TIE_LOW_XPD_XTAL. + PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_XTAL = 0x40 + // Position of TIE_HIGH_GLOBAL_BBPLL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG_Pos = 0x19 + // Bit mask of TIE_HIGH_GLOBAL_BBPLL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG_Msk = 0x2000000 + // Bit TIE_HIGH_GLOBAL_BBPLL_ICG. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_BBPLL_ICG = 0x2000000 + // Position of TIE_HIGH_GLOBAL_XTAL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG_Pos = 0x1a + // Bit mask of TIE_HIGH_GLOBAL_XTAL_ICG field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG_Msk = 0x4000000 + // Bit TIE_HIGH_GLOBAL_XTAL_ICG. + PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG = 0x4000000 + // Position of TIE_HIGH_I2C_RETENTION field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION_Pos = 0x1b + // Bit mask of TIE_HIGH_I2C_RETENTION field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION_Msk = 0x8000000 + // Bit TIE_HIGH_I2C_RETENTION. + PMU_IMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION = 0x8000000 + // Position of TIE_HIGH_XPD_BB_I2C field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C_Pos = 0x1c + // Bit mask of TIE_HIGH_XPD_BB_I2C field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C_Msk = 0x10000000 + // Bit TIE_HIGH_XPD_BB_I2C. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BB_I2C = 0x10000000 + // Position of TIE_HIGH_XPD_BBPLL_I2C field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C_Pos = 0x1d + // Bit mask of TIE_HIGH_XPD_BBPLL_I2C field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C_Msk = 0x20000000 + // Bit TIE_HIGH_XPD_BBPLL_I2C. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_I2C = 0x20000000 + // Position of TIE_HIGH_XPD_BBPLL field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_Pos = 0x1e + // Bit mask of TIE_HIGH_XPD_BBPLL field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL_Msk = 0x40000000 + // Bit TIE_HIGH_XPD_BBPLL. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_BBPLL = 0x40000000 + // Position of TIE_HIGH_XPD_XTAL field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL_Pos = 0x1f + // Bit mask of TIE_HIGH_XPD_XTAL field. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL_Msk = 0x80000000 + // Bit TIE_HIGH_XPD_XTAL. + PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL = 0x80000000 + + // IMM_SLEEP_SYSCLK: need_des + // Position of UPDATE_DIG_ICG_SWITCH field. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH_Pos = 0x1c + // Bit mask of UPDATE_DIG_ICG_SWITCH field. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH_Msk = 0x10000000 + // Bit UPDATE_DIG_ICG_SWITCH. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH = 0x10000000 + // Position of TIE_LOW_ICG_SLP_SEL field. + PMU_IMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL_Pos = 0x1d + // Bit mask of TIE_LOW_ICG_SLP_SEL field. + PMU_IMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL_Msk = 0x20000000 + // Bit TIE_LOW_ICG_SLP_SEL. + PMU_IMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL = 0x20000000 + // Position of TIE_HIGH_ICG_SLP_SEL field. + PMU_IMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL_Pos = 0x1e + // Bit mask of TIE_HIGH_ICG_SLP_SEL field. + PMU_IMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL_Msk = 0x40000000 + // Bit TIE_HIGH_ICG_SLP_SEL. + PMU_IMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL = 0x40000000 + // Position of UPDATE_DIG_SYS_CLK_SEL field. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL_Pos = 0x1f + // Bit mask of UPDATE_DIG_SYS_CLK_SEL field. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL_Msk = 0x80000000 + // Bit UPDATE_DIG_SYS_CLK_SEL. + PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL = 0x80000000 + + // IMM_HP_FUNC_ICG: need_des + // Position of UPDATE_DIG_ICG_FUNC_EN field. + PMU_IMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN_Pos = 0x1f + // Bit mask of UPDATE_DIG_ICG_FUNC_EN field. + PMU_IMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN_Msk = 0x80000000 + // Bit UPDATE_DIG_ICG_FUNC_EN. + PMU_IMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN = 0x80000000 + + // IMM_HP_APB_ICG: need_des + // Position of UPDATE_DIG_ICG_APB_EN field. + PMU_IMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN_Pos = 0x1f + // Bit mask of UPDATE_DIG_ICG_APB_EN field. + PMU_IMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN_Msk = 0x80000000 + // Bit UPDATE_DIG_ICG_APB_EN. + PMU_IMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN = 0x80000000 + + // IMM_MODEM_ICG: need_des + // Position of UPDATE_DIG_ICG_MODEM_EN field. + PMU_IMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN_Pos = 0x1f + // Bit mask of UPDATE_DIG_ICG_MODEM_EN field. + PMU_IMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN_Msk = 0x80000000 + // Bit UPDATE_DIG_ICG_MODEM_EN. + PMU_IMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN = 0x80000000 + + // IMM_LP_ICG: need_des + // Position of TIE_LOW_LP_ROOTCLK_SEL field. + PMU_IMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL_Pos = 0x1e + // Bit mask of TIE_LOW_LP_ROOTCLK_SEL field. + PMU_IMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL_Msk = 0x40000000 + // Bit TIE_LOW_LP_ROOTCLK_SEL. + PMU_IMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL = 0x40000000 + // Position of TIE_HIGH_LP_ROOTCLK_SEL field. + PMU_IMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL_Pos = 0x1f + // Bit mask of TIE_HIGH_LP_ROOTCLK_SEL field. + PMU_IMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL_Msk = 0x80000000 + // Bit TIE_HIGH_LP_ROOTCLK_SEL. + PMU_IMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL = 0x80000000 + + // IMM_PAD_HOLD_ALL: need_des + // Position of TIE_HIGH_LP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL_Pos = 0x1c + // Bit mask of TIE_HIGH_LP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL_Msk = 0x10000000 + // Bit TIE_HIGH_LP_PAD_HOLD_ALL. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL = 0x10000000 + // Position of TIE_LOW_LP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL_Pos = 0x1d + // Bit mask of TIE_LOW_LP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL_Msk = 0x20000000 + // Bit TIE_LOW_LP_PAD_HOLD_ALL. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL = 0x20000000 + // Position of TIE_HIGH_HP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL_Pos = 0x1e + // Bit mask of TIE_HIGH_HP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL_Msk = 0x40000000 + // Bit TIE_HIGH_HP_PAD_HOLD_ALL. + PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL = 0x40000000 + // Position of TIE_LOW_HP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL_Pos = 0x1f + // Bit mask of TIE_LOW_HP_PAD_HOLD_ALL field. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL_Msk = 0x80000000 + // Bit TIE_LOW_HP_PAD_HOLD_ALL. + PMU_IMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL = 0x80000000 + + // IMM_I2C_ISO: need_des + // Position of TIE_HIGH_I2C_ISO_EN field. + PMU_IMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN_Pos = 0x1e + // Bit mask of TIE_HIGH_I2C_ISO_EN field. + PMU_IMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN_Msk = 0x40000000 + // Bit TIE_HIGH_I2C_ISO_EN. + PMU_IMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN = 0x40000000 + // Position of TIE_LOW_I2C_ISO_EN field. + PMU_IMM_I2C_ISO_TIE_LOW_I2C_ISO_EN_Pos = 0x1f + // Bit mask of TIE_LOW_I2C_ISO_EN field. + PMU_IMM_I2C_ISO_TIE_LOW_I2C_ISO_EN_Msk = 0x80000000 + // Bit TIE_LOW_I2C_ISO_EN. + PMU_IMM_I2C_ISO_TIE_LOW_I2C_ISO_EN = 0x80000000 + + // POWER_WAIT_TIMER0: need_des + // Position of DG_HP_POWERDOWN_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER_Pos = 0x5 + // Bit mask of DG_HP_POWERDOWN_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER_Msk = 0x3fe0 + // Position of DG_HP_POWERUP_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER_Pos = 0xe + // Bit mask of DG_HP_POWERUP_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER_Msk = 0x7fc000 + // Position of DG_HP_WAIT_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_WAIT_TIMER_Pos = 0x17 + // Bit mask of DG_HP_WAIT_TIMER field. + PMU_POWER_WAIT_TIMER0_DG_HP_WAIT_TIMER_Msk = 0xff800000 + + // POWER_WAIT_TIMER1: need_des + // Position of DG_LP_POWERDOWN_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER_Pos = 0x9 + // Bit mask of DG_LP_POWERDOWN_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER_Msk = 0xfe00 + // Position of DG_LP_POWERUP_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER_Pos = 0x10 + // Bit mask of DG_LP_POWERUP_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER_Msk = 0x7f0000 + // Position of DG_LP_WAIT_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_WAIT_TIMER_Pos = 0x17 + // Bit mask of DG_LP_WAIT_TIMER field. + PMU_POWER_WAIT_TIMER1_DG_LP_WAIT_TIMER_Msk = 0xff800000 + + // POWER_PD_TOP_CNTL: need_des + // Position of FORCE_TOP_RESET field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_RESET_Pos = 0x0 + // Bit mask of FORCE_TOP_RESET field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_RESET_Msk = 0x1 + // Bit FORCE_TOP_RESET. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_RESET = 0x1 + // Position of FORCE_TOP_ISO field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_ISO_Pos = 0x1 + // Bit mask of FORCE_TOP_ISO field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_ISO_Msk = 0x2 + // Bit FORCE_TOP_ISO. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_ISO = 0x2 + // Position of FORCE_TOP_PU field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PU_Pos = 0x2 + // Bit mask of FORCE_TOP_PU field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PU_Msk = 0x4 + // Bit FORCE_TOP_PU. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PU = 0x4 + // Position of FORCE_TOP_NO_RESET field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_TOP_NO_RESET field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET_Msk = 0x8 + // Bit FORCE_TOP_NO_RESET. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET = 0x8 + // Position of FORCE_TOP_NO_ISO field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_TOP_NO_ISO field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO_Msk = 0x10 + // Bit FORCE_TOP_NO_ISO. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO = 0x10 + // Position of FORCE_TOP_PD field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PD_Pos = 0x5 + // Bit mask of FORCE_TOP_PD field. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PD_Msk = 0x20 + // Bit FORCE_TOP_PD. + PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PD = 0x20 + // Position of PD_TOP_MASK field. + PMU_POWER_PD_TOP_CNTL_PD_TOP_MASK_Pos = 0x6 + // Bit mask of PD_TOP_MASK field. + PMU_POWER_PD_TOP_CNTL_PD_TOP_MASK_Msk = 0x7c0 + // Position of PD_TOP_PD_MASK field. + PMU_POWER_PD_TOP_CNTL_PD_TOP_PD_MASK_Pos = 0x1b + // Bit mask of PD_TOP_PD_MASK field. + PMU_POWER_PD_TOP_CNTL_PD_TOP_PD_MASK_Msk = 0xf8000000 + + // POWER_PD_HPAON_CNTL: need_des + // Position of FORCE_HP_AON_RESET field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET_Pos = 0x0 + // Bit mask of FORCE_HP_AON_RESET field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET_Msk = 0x1 + // Bit FORCE_HP_AON_RESET. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_RESET = 0x1 + // Position of FORCE_HP_AON_ISO field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO_Pos = 0x1 + // Bit mask of FORCE_HP_AON_ISO field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO_Msk = 0x2 + // Bit FORCE_HP_AON_ISO. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_ISO = 0x2 + // Position of FORCE_HP_AON_PU field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PU_Pos = 0x2 + // Bit mask of FORCE_HP_AON_PU field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PU_Msk = 0x4 + // Bit FORCE_HP_AON_PU. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PU = 0x4 + // Position of FORCE_HP_AON_NO_RESET field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_HP_AON_NO_RESET field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET_Msk = 0x8 + // Bit FORCE_HP_AON_NO_RESET. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_RESET = 0x8 + // Position of FORCE_HP_AON_NO_ISO field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_HP_AON_NO_ISO field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO_Msk = 0x10 + // Bit FORCE_HP_AON_NO_ISO. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_NO_ISO = 0x10 + // Position of FORCE_HP_AON_PD field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PD_Pos = 0x5 + // Bit mask of FORCE_HP_AON_PD field. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PD_Msk = 0x20 + // Bit FORCE_HP_AON_PD. + PMU_POWER_PD_HPAON_CNTL_FORCE_HP_AON_PD = 0x20 + // Position of PD_HP_AON_MASK field. + PMU_POWER_PD_HPAON_CNTL_PD_HP_AON_MASK_Pos = 0x6 + // Bit mask of PD_HP_AON_MASK field. + PMU_POWER_PD_HPAON_CNTL_PD_HP_AON_MASK_Msk = 0x7c0 + // Position of PD_HP_AON_PD_MASK field. + PMU_POWER_PD_HPAON_CNTL_PD_HP_AON_PD_MASK_Pos = 0x1b + // Bit mask of PD_HP_AON_PD_MASK field. + PMU_POWER_PD_HPAON_CNTL_PD_HP_AON_PD_MASK_Msk = 0xf8000000 + + // POWER_PD_HPCPU_CNTL: need_des + // Position of FORCE_HP_CPU_RESET field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET_Pos = 0x0 + // Bit mask of FORCE_HP_CPU_RESET field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET_Msk = 0x1 + // Bit FORCE_HP_CPU_RESET. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_RESET = 0x1 + // Position of FORCE_HP_CPU_ISO field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO_Pos = 0x1 + // Bit mask of FORCE_HP_CPU_ISO field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO_Msk = 0x2 + // Bit FORCE_HP_CPU_ISO. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_ISO = 0x2 + // Position of FORCE_HP_CPU_PU field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU_Pos = 0x2 + // Bit mask of FORCE_HP_CPU_PU field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU_Msk = 0x4 + // Bit FORCE_HP_CPU_PU. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PU = 0x4 + // Position of FORCE_HP_CPU_NO_RESET field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_HP_CPU_NO_RESET field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET_Msk = 0x8 + // Bit FORCE_HP_CPU_NO_RESET. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_RESET = 0x8 + // Position of FORCE_HP_CPU_NO_ISO field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_HP_CPU_NO_ISO field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO_Msk = 0x10 + // Bit FORCE_HP_CPU_NO_ISO. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_NO_ISO = 0x10 + // Position of FORCE_HP_CPU_PD field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD_Pos = 0x5 + // Bit mask of FORCE_HP_CPU_PD field. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD_Msk = 0x20 + // Bit FORCE_HP_CPU_PD. + PMU_POWER_PD_HPCPU_CNTL_FORCE_HP_CPU_PD = 0x20 + // Position of PD_HP_CPU_MASK field. + PMU_POWER_PD_HPCPU_CNTL_PD_HP_CPU_MASK_Pos = 0x6 + // Bit mask of PD_HP_CPU_MASK field. + PMU_POWER_PD_HPCPU_CNTL_PD_HP_CPU_MASK_Msk = 0x7c0 + // Position of PD_HP_CPU_PD_MASK field. + PMU_POWER_PD_HPCPU_CNTL_PD_HP_CPU_PD_MASK_Pos = 0x1b + // Bit mask of PD_HP_CPU_PD_MASK field. + PMU_POWER_PD_HPCPU_CNTL_PD_HP_CPU_PD_MASK_Msk = 0xf8000000 + + // POWER_PD_HPPERI_RESERVE: need_des + // Position of HP_PERI_RESERVE field. + PMU_POWER_PD_HPPERI_RESERVE_HP_PERI_RESERVE_Pos = 0x0 + // Bit mask of HP_PERI_RESERVE field. + PMU_POWER_PD_HPPERI_RESERVE_HP_PERI_RESERVE_Msk = 0xffffffff + + // POWER_PD_HPWIFI_CNTL: need_des + // Position of FORCE_HP_WIFI_RESET field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET_Pos = 0x0 + // Bit mask of FORCE_HP_WIFI_RESET field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET_Msk = 0x1 + // Bit FORCE_HP_WIFI_RESET. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_RESET = 0x1 + // Position of FORCE_HP_WIFI_ISO field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO_Pos = 0x1 + // Bit mask of FORCE_HP_WIFI_ISO field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO_Msk = 0x2 + // Bit FORCE_HP_WIFI_ISO. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_ISO = 0x2 + // Position of FORCE_HP_WIFI_PU field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU_Pos = 0x2 + // Bit mask of FORCE_HP_WIFI_PU field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU_Msk = 0x4 + // Bit FORCE_HP_WIFI_PU. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PU = 0x4 + // Position of FORCE_HP_WIFI_NO_RESET field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_HP_WIFI_NO_RESET field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET_Msk = 0x8 + // Bit FORCE_HP_WIFI_NO_RESET. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_RESET = 0x8 + // Position of FORCE_HP_WIFI_NO_ISO field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_HP_WIFI_NO_ISO field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO_Msk = 0x10 + // Bit FORCE_HP_WIFI_NO_ISO. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_NO_ISO = 0x10 + // Position of FORCE_HP_WIFI_PD field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD_Pos = 0x5 + // Bit mask of FORCE_HP_WIFI_PD field. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD_Msk = 0x20 + // Bit FORCE_HP_WIFI_PD. + PMU_POWER_PD_HPWIFI_CNTL_FORCE_HP_WIFI_PD = 0x20 + // Position of PD_HP_WIFI_MASK field. + PMU_POWER_PD_HPWIFI_CNTL_PD_HP_WIFI_MASK_Pos = 0x6 + // Bit mask of PD_HP_WIFI_MASK field. + PMU_POWER_PD_HPWIFI_CNTL_PD_HP_WIFI_MASK_Msk = 0x7c0 + // Position of PD_HP_WIFI_PD_MASK field. + PMU_POWER_PD_HPWIFI_CNTL_PD_HP_WIFI_PD_MASK_Pos = 0x1b + // Bit mask of PD_HP_WIFI_PD_MASK field. + PMU_POWER_PD_HPWIFI_CNTL_PD_HP_WIFI_PD_MASK_Msk = 0xf8000000 + + // POWER_PD_LPPERI_CNTL: need_des + // Position of FORCE_LP_PERI_RESET field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET_Pos = 0x0 + // Bit mask of FORCE_LP_PERI_RESET field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET_Msk = 0x1 + // Bit FORCE_LP_PERI_RESET. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET = 0x1 + // Position of FORCE_LP_PERI_ISO field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO_Pos = 0x1 + // Bit mask of FORCE_LP_PERI_ISO field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO_Msk = 0x2 + // Bit FORCE_LP_PERI_ISO. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO = 0x2 + // Position of FORCE_LP_PERI_PU field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU_Pos = 0x2 + // Bit mask of FORCE_LP_PERI_PU field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU_Msk = 0x4 + // Bit FORCE_LP_PERI_PU. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU = 0x4 + // Position of FORCE_LP_PERI_NO_RESET field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET_Pos = 0x3 + // Bit mask of FORCE_LP_PERI_NO_RESET field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET_Msk = 0x8 + // Bit FORCE_LP_PERI_NO_RESET. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET = 0x8 + // Position of FORCE_LP_PERI_NO_ISO field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO_Pos = 0x4 + // Bit mask of FORCE_LP_PERI_NO_ISO field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO_Msk = 0x10 + // Bit FORCE_LP_PERI_NO_ISO. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO = 0x10 + // Position of FORCE_LP_PERI_PD field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD_Pos = 0x5 + // Bit mask of FORCE_LP_PERI_PD field. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD_Msk = 0x20 + // Bit FORCE_LP_PERI_PD. + PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD = 0x20 + + // POWER_PD_MEM_CNTL: need_des + // Position of FORCE_HP_MEM_ISO field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_ISO_Pos = 0x0 + // Bit mask of FORCE_HP_MEM_ISO field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_ISO_Msk = 0xf + // Position of FORCE_HP_MEM_PD field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_PD_Pos = 0x4 + // Bit mask of FORCE_HP_MEM_PD field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_PD_Msk = 0xf0 + // Position of FORCE_HP_MEM_NO_ISO field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_NO_ISO_Pos = 0x18 + // Bit mask of FORCE_HP_MEM_NO_ISO field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_NO_ISO_Msk = 0xf000000 + // Position of FORCE_HP_MEM_PU field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_PU_Pos = 0x1c + // Bit mask of FORCE_HP_MEM_PU field. + PMU_POWER_PD_MEM_CNTL_FORCE_HP_MEM_PU_Msk = 0xf0000000 + + // POWER_PD_MEM_MASK: need_des + // Position of PD_HP_MEM2_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM2_PD_MASK_Pos = 0x0 + // Bit mask of PD_HP_MEM2_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM2_PD_MASK_Msk = 0x1f + // Position of PD_HP_MEM1_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM1_PD_MASK_Pos = 0x5 + // Bit mask of PD_HP_MEM1_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM1_PD_MASK_Msk = 0x3e0 + // Position of PD_HP_MEM0_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM0_PD_MASK_Pos = 0xa + // Bit mask of PD_HP_MEM0_PD_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM0_PD_MASK_Msk = 0x7c00 + // Position of PD_HP_MEM2_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM2_MASK_Pos = 0x11 + // Bit mask of PD_HP_MEM2_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM2_MASK_Msk = 0x3e0000 + // Position of PD_HP_MEM1_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM1_MASK_Pos = 0x16 + // Bit mask of PD_HP_MEM1_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM1_MASK_Msk = 0x7c00000 + // Position of PD_HP_MEM0_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM0_MASK_Pos = 0x1b + // Bit mask of PD_HP_MEM0_MASK field. + PMU_POWER_PD_MEM_MASK_PD_HP_MEM0_MASK_Msk = 0xf8000000 + + // POWER_HP_PAD: need_des + // Position of FORCE_HP_PAD_NO_ISO_ALL field. + PMU_POWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL_Pos = 0x0 + // Bit mask of FORCE_HP_PAD_NO_ISO_ALL field. + PMU_POWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL_Msk = 0x1 + // Bit FORCE_HP_PAD_NO_ISO_ALL. + PMU_POWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL = 0x1 + // Position of FORCE_HP_PAD_ISO_ALL field. + PMU_POWER_HP_PAD_FORCE_HP_PAD_ISO_ALL_Pos = 0x1 + // Bit mask of FORCE_HP_PAD_ISO_ALL field. + PMU_POWER_HP_PAD_FORCE_HP_PAD_ISO_ALL_Msk = 0x2 + // Bit FORCE_HP_PAD_ISO_ALL. + PMU_POWER_HP_PAD_FORCE_HP_PAD_ISO_ALL = 0x2 + + // POWER_VDD_SPI_CNTL: need_des + // Position of VDD_SPI_PWR_WAIT field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_WAIT_Pos = 0x12 + // Bit mask of VDD_SPI_PWR_WAIT field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_WAIT_Msk = 0x1ffc0000 + // Position of VDD_SPI_PWR_SW field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SW_Pos = 0x1d + // Bit mask of VDD_SPI_PWR_SW field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SW_Msk = 0x60000000 + // Position of VDD_SPI_PWR_SEL_SW field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW_Pos = 0x1f + // Bit mask of VDD_SPI_PWR_SEL_SW field. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW_Msk = 0x80000000 + // Bit VDD_SPI_PWR_SEL_SW. + PMU_POWER_VDD_SPI_CNTL_VDD_SPI_PWR_SEL_SW = 0x80000000 + + // POWER_CK_WAIT_CNTL: need_des + // Position of WAIT_XTL_STABLE field. + PMU_POWER_CK_WAIT_CNTL_WAIT_XTL_STABLE_Pos = 0x0 + // Bit mask of WAIT_XTL_STABLE field. + PMU_POWER_CK_WAIT_CNTL_WAIT_XTL_STABLE_Msk = 0xffff + // Position of WAIT_PLL_STABLE field. + PMU_POWER_CK_WAIT_CNTL_WAIT_PLL_STABLE_Pos = 0x10 + // Bit mask of WAIT_PLL_STABLE field. + PMU_POWER_CK_WAIT_CNTL_WAIT_PLL_STABLE_Msk = 0xffff0000 + + // SLP_WAKEUP_CNTL0: need_des + // Position of SLEEP_REQ field. + PMU_SLP_WAKEUP_CNTL0_SLEEP_REQ_Pos = 0x1f + // Bit mask of SLEEP_REQ field. + PMU_SLP_WAKEUP_CNTL0_SLEEP_REQ_Msk = 0x80000000 + // Bit SLEEP_REQ. + PMU_SLP_WAKEUP_CNTL0_SLEEP_REQ = 0x80000000 + + // SLP_WAKEUP_CNTL1: need_des + // Position of SLEEP_REJECT_ENA field. + PMU_SLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA_Pos = 0x0 + // Bit mask of SLEEP_REJECT_ENA field. + PMU_SLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA_Msk = 0x7fffffff + // Position of SLP_REJECT_EN field. + PMU_SLP_WAKEUP_CNTL1_SLP_REJECT_EN_Pos = 0x1f + // Bit mask of SLP_REJECT_EN field. + PMU_SLP_WAKEUP_CNTL1_SLP_REJECT_EN_Msk = 0x80000000 + // Bit SLP_REJECT_EN. + PMU_SLP_WAKEUP_CNTL1_SLP_REJECT_EN = 0x80000000 + + // SLP_WAKEUP_CNTL2: need_des + // Position of WAKEUP_ENA field. + PMU_SLP_WAKEUP_CNTL2_WAKEUP_ENA_Pos = 0x0 + // Bit mask of WAKEUP_ENA field. + PMU_SLP_WAKEUP_CNTL2_WAKEUP_ENA_Msk = 0xffffffff + + // SLP_WAKEUP_CNTL3: need_des + // Position of LP_MIN_SLP_VAL field. + PMU_SLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL_Pos = 0x0 + // Bit mask of LP_MIN_SLP_VAL field. + PMU_SLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL_Msk = 0xff + // Position of HP_MIN_SLP_VAL field. + PMU_SLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL_Pos = 0x8 + // Bit mask of HP_MIN_SLP_VAL field. + PMU_SLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL_Msk = 0xff00 + // Position of SLEEP_PRT_SEL field. + PMU_SLP_WAKEUP_CNTL3_SLEEP_PRT_SEL_Pos = 0x10 + // Bit mask of SLEEP_PRT_SEL field. + PMU_SLP_WAKEUP_CNTL3_SLEEP_PRT_SEL_Msk = 0x30000 + + // SLP_WAKEUP_CNTL4: need_des + // Position of SLP_REJECT_CAUSE_CLR field. + PMU_SLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR_Pos = 0x1f + // Bit mask of SLP_REJECT_CAUSE_CLR field. + PMU_SLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR_Msk = 0x80000000 + // Bit SLP_REJECT_CAUSE_CLR. + PMU_SLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR = 0x80000000 + + // SLP_WAKEUP_CNTL5: need_des + // Position of MODEM_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET_Pos = 0x0 + // Bit mask of MODEM_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET_Msk = 0xfffff + // Position of LP_ANA_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET_Pos = 0x18 + // Bit mask of LP_ANA_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET_Msk = 0xff000000 + + // SLP_WAKEUP_CNTL6: need_des + // Position of SOC_WAKEUP_WAIT field. + PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_Pos = 0x0 + // Bit mask of SOC_WAKEUP_WAIT field. + PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_Msk = 0xfffff + // Position of SOC_WAKEUP_WAIT_CFG field. + PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG_Pos = 0x1e + // Bit mask of SOC_WAKEUP_WAIT_CFG field. + PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG_Msk = 0xc0000000 + + // SLP_WAKEUP_CNTL7: need_des + // Position of ANA_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL7_ANA_WAIT_TARGET_Pos = 0x10 + // Bit mask of ANA_WAIT_TARGET field. + PMU_SLP_WAKEUP_CNTL7_ANA_WAIT_TARGET_Msk = 0xffff0000 + + // SLP_WAKEUP_STATUS0: need_des + // Position of WAKEUP_CAUSE field. + PMU_SLP_WAKEUP_STATUS0_WAKEUP_CAUSE_Pos = 0x0 + // Bit mask of WAKEUP_CAUSE field. + PMU_SLP_WAKEUP_STATUS0_WAKEUP_CAUSE_Msk = 0xffffffff + + // SLP_WAKEUP_STATUS1: need_des + // Position of REJECT_CAUSE field. + PMU_SLP_WAKEUP_STATUS1_REJECT_CAUSE_Pos = 0x0 + // Bit mask of REJECT_CAUSE field. + PMU_SLP_WAKEUP_STATUS1_REJECT_CAUSE_Msk = 0xffffffff + + // HP_CK_POWERON: need_des + // Position of I2C_POR_WAIT_TARGET field. + PMU_HP_CK_POWERON_I2C_POR_WAIT_TARGET_Pos = 0x0 + // Bit mask of I2C_POR_WAIT_TARGET field. + PMU_HP_CK_POWERON_I2C_POR_WAIT_TARGET_Msk = 0xff + + // HP_CK_CNTL: need_des + // Position of MODIFY_ICG_CNTL_WAIT field. + PMU_HP_CK_CNTL_MODIFY_ICG_CNTL_WAIT_Pos = 0x0 + // Bit mask of MODIFY_ICG_CNTL_WAIT field. + PMU_HP_CK_CNTL_MODIFY_ICG_CNTL_WAIT_Msk = 0xff + // Position of SWITCH_ICG_CNTL_WAIT field. + PMU_HP_CK_CNTL_SWITCH_ICG_CNTL_WAIT_Pos = 0x8 + // Bit mask of SWITCH_ICG_CNTL_WAIT field. + PMU_HP_CK_CNTL_SWITCH_ICG_CNTL_WAIT_Msk = 0xff00 + + // POR_STATUS: need_des + // Position of POR_DONE field. + PMU_POR_STATUS_POR_DONE_Pos = 0x1f + // Bit mask of POR_DONE field. + PMU_POR_STATUS_POR_DONE_Msk = 0x80000000 + // Bit POR_DONE. + PMU_POR_STATUS_POR_DONE = 0x80000000 + + // RF_PWC: need_des + // Position of XPD_PERIF_I2C field. + PMU_RF_PWC_XPD_PERIF_I2C_Pos = 0x1b + // Bit mask of XPD_PERIF_I2C field. + PMU_RF_PWC_XPD_PERIF_I2C_Msk = 0x8000000 + // Bit XPD_PERIF_I2C. + PMU_RF_PWC_XPD_PERIF_I2C = 0x8000000 + // Position of XPD_RFTX_I2C field. + PMU_RF_PWC_XPD_RFTX_I2C_Pos = 0x1c + // Bit mask of XPD_RFTX_I2C field. + PMU_RF_PWC_XPD_RFTX_I2C_Msk = 0x10000000 + // Bit XPD_RFTX_I2C. + PMU_RF_PWC_XPD_RFTX_I2C = 0x10000000 + // Position of XPD_RFRX_I2C field. + PMU_RF_PWC_XPD_RFRX_I2C_Pos = 0x1d + // Bit mask of XPD_RFRX_I2C field. + PMU_RF_PWC_XPD_RFRX_I2C_Msk = 0x20000000 + // Bit XPD_RFRX_I2C. + PMU_RF_PWC_XPD_RFRX_I2C = 0x20000000 + // Position of XPD_RFPLL field. + PMU_RF_PWC_XPD_RFPLL_Pos = 0x1e + // Bit mask of XPD_RFPLL field. + PMU_RF_PWC_XPD_RFPLL_Msk = 0x40000000 + // Bit XPD_RFPLL. + PMU_RF_PWC_XPD_RFPLL = 0x40000000 + // Position of XPD_FORCE_RFPLL field. + PMU_RF_PWC_XPD_FORCE_RFPLL_Pos = 0x1f + // Bit mask of XPD_FORCE_RFPLL field. + PMU_RF_PWC_XPD_FORCE_RFPLL_Msk = 0x80000000 + // Bit XPD_FORCE_RFPLL. + PMU_RF_PWC_XPD_FORCE_RFPLL = 0x80000000 + + // VDDBAT_CFG: need_des + // Position of VDDBAT_MODE field. + PMU_VDDBAT_CFG_VDDBAT_MODE_Pos = 0x0 + // Bit mask of VDDBAT_MODE field. + PMU_VDDBAT_CFG_VDDBAT_MODE_Msk = 0x3 + // Position of VDDBAT_SW_UPDATE field. + PMU_VDDBAT_CFG_VDDBAT_SW_UPDATE_Pos = 0x1f + // Bit mask of VDDBAT_SW_UPDATE field. + PMU_VDDBAT_CFG_VDDBAT_SW_UPDATE_Msk = 0x80000000 + // Bit VDDBAT_SW_UPDATE. + PMU_VDDBAT_CFG_VDDBAT_SW_UPDATE = 0x80000000 + + // BACKUP_CFG: need_des + // Position of BACKUP_SYS_CLK_NO_DIV field. + PMU_BACKUP_CFG_BACKUP_SYS_CLK_NO_DIV_Pos = 0x1f + // Bit mask of BACKUP_SYS_CLK_NO_DIV field. + PMU_BACKUP_CFG_BACKUP_SYS_CLK_NO_DIV_Msk = 0x80000000 + // Bit BACKUP_SYS_CLK_NO_DIV. + PMU_BACKUP_CFG_BACKUP_SYS_CLK_NO_DIV = 0x80000000 + + // INT_RAW: need_des + // Position of LP_CPU_EXC_INT_RAW field. + PMU_INT_RAW_LP_CPU_EXC_INT_RAW_Pos = 0x1b + // Bit mask of LP_CPU_EXC_INT_RAW field. + PMU_INT_RAW_LP_CPU_EXC_INT_RAW_Msk = 0x8000000 + // Bit LP_CPU_EXC_INT_RAW. + PMU_INT_RAW_LP_CPU_EXC_INT_RAW = 0x8000000 + // Position of SDIO_IDLE_INT_RAW field. + PMU_INT_RAW_SDIO_IDLE_INT_RAW_Pos = 0x1c + // Bit mask of SDIO_IDLE_INT_RAW field. + PMU_INT_RAW_SDIO_IDLE_INT_RAW_Msk = 0x10000000 + // Bit SDIO_IDLE_INT_RAW. + PMU_INT_RAW_SDIO_IDLE_INT_RAW = 0x10000000 + // Position of SW_INT_RAW field. + PMU_INT_RAW_SW_INT_RAW_Pos = 0x1d + // Bit mask of SW_INT_RAW field. + PMU_INT_RAW_SW_INT_RAW_Msk = 0x20000000 + // Bit SW_INT_RAW. + PMU_INT_RAW_SW_INT_RAW = 0x20000000 + // Position of SOC_SLEEP_REJECT_INT_RAW field. + PMU_INT_RAW_SOC_SLEEP_REJECT_INT_RAW_Pos = 0x1e + // Bit mask of SOC_SLEEP_REJECT_INT_RAW field. + PMU_INT_RAW_SOC_SLEEP_REJECT_INT_RAW_Msk = 0x40000000 + // Bit SOC_SLEEP_REJECT_INT_RAW. + PMU_INT_RAW_SOC_SLEEP_REJECT_INT_RAW = 0x40000000 + // Position of SOC_WAKEUP_INT_RAW field. + PMU_INT_RAW_SOC_WAKEUP_INT_RAW_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_RAW field. + PMU_INT_RAW_SOC_WAKEUP_INT_RAW_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_RAW. + PMU_INT_RAW_SOC_WAKEUP_INT_RAW = 0x80000000 + + // HP_INT_ST: need_des + // Position of LP_CPU_EXC_INT_ST field. + PMU_HP_INT_ST_LP_CPU_EXC_INT_ST_Pos = 0x1b + // Bit mask of LP_CPU_EXC_INT_ST field. + PMU_HP_INT_ST_LP_CPU_EXC_INT_ST_Msk = 0x8000000 + // Bit LP_CPU_EXC_INT_ST. + PMU_HP_INT_ST_LP_CPU_EXC_INT_ST = 0x8000000 + // Position of SDIO_IDLE_INT_ST field. + PMU_HP_INT_ST_SDIO_IDLE_INT_ST_Pos = 0x1c + // Bit mask of SDIO_IDLE_INT_ST field. + PMU_HP_INT_ST_SDIO_IDLE_INT_ST_Msk = 0x10000000 + // Bit SDIO_IDLE_INT_ST. + PMU_HP_INT_ST_SDIO_IDLE_INT_ST = 0x10000000 + // Position of SW_INT_ST field. + PMU_HP_INT_ST_SW_INT_ST_Pos = 0x1d + // Bit mask of SW_INT_ST field. + PMU_HP_INT_ST_SW_INT_ST_Msk = 0x20000000 + // Bit SW_INT_ST. + PMU_HP_INT_ST_SW_INT_ST = 0x20000000 + // Position of SOC_SLEEP_REJECT_INT_ST field. + PMU_HP_INT_ST_SOC_SLEEP_REJECT_INT_ST_Pos = 0x1e + // Bit mask of SOC_SLEEP_REJECT_INT_ST field. + PMU_HP_INT_ST_SOC_SLEEP_REJECT_INT_ST_Msk = 0x40000000 + // Bit SOC_SLEEP_REJECT_INT_ST. + PMU_HP_INT_ST_SOC_SLEEP_REJECT_INT_ST = 0x40000000 + // Position of SOC_WAKEUP_INT_ST field. + PMU_HP_INT_ST_SOC_WAKEUP_INT_ST_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ST field. + PMU_HP_INT_ST_SOC_WAKEUP_INT_ST_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ST. + PMU_HP_INT_ST_SOC_WAKEUP_INT_ST = 0x80000000 + + // HP_INT_ENA: need_des + // Position of LP_CPU_EXC_INT_ENA field. + PMU_HP_INT_ENA_LP_CPU_EXC_INT_ENA_Pos = 0x1b + // Bit mask of LP_CPU_EXC_INT_ENA field. + PMU_HP_INT_ENA_LP_CPU_EXC_INT_ENA_Msk = 0x8000000 + // Bit LP_CPU_EXC_INT_ENA. + PMU_HP_INT_ENA_LP_CPU_EXC_INT_ENA = 0x8000000 + // Position of SDIO_IDLE_INT_ENA field. + PMU_HP_INT_ENA_SDIO_IDLE_INT_ENA_Pos = 0x1c + // Bit mask of SDIO_IDLE_INT_ENA field. + PMU_HP_INT_ENA_SDIO_IDLE_INT_ENA_Msk = 0x10000000 + // Bit SDIO_IDLE_INT_ENA. + PMU_HP_INT_ENA_SDIO_IDLE_INT_ENA = 0x10000000 + // Position of SW_INT_ENA field. + PMU_HP_INT_ENA_SW_INT_ENA_Pos = 0x1d + // Bit mask of SW_INT_ENA field. + PMU_HP_INT_ENA_SW_INT_ENA_Msk = 0x20000000 + // Bit SW_INT_ENA. + PMU_HP_INT_ENA_SW_INT_ENA = 0x20000000 + // Position of SOC_SLEEP_REJECT_INT_ENA field. + PMU_HP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA_Pos = 0x1e + // Bit mask of SOC_SLEEP_REJECT_INT_ENA field. + PMU_HP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA_Msk = 0x40000000 + // Bit SOC_SLEEP_REJECT_INT_ENA. + PMU_HP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA = 0x40000000 + // Position of SOC_WAKEUP_INT_ENA field. + PMU_HP_INT_ENA_SOC_WAKEUP_INT_ENA_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_ENA field. + PMU_HP_INT_ENA_SOC_WAKEUP_INT_ENA_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_ENA. + PMU_HP_INT_ENA_SOC_WAKEUP_INT_ENA = 0x80000000 + + // HP_INT_CLR: need_des + // Position of LP_CPU_EXC_INT_CLR field. + PMU_HP_INT_CLR_LP_CPU_EXC_INT_CLR_Pos = 0x1b + // Bit mask of LP_CPU_EXC_INT_CLR field. + PMU_HP_INT_CLR_LP_CPU_EXC_INT_CLR_Msk = 0x8000000 + // Bit LP_CPU_EXC_INT_CLR. + PMU_HP_INT_CLR_LP_CPU_EXC_INT_CLR = 0x8000000 + // Position of SDIO_IDLE_INT_CLR field. + PMU_HP_INT_CLR_SDIO_IDLE_INT_CLR_Pos = 0x1c + // Bit mask of SDIO_IDLE_INT_CLR field. + PMU_HP_INT_CLR_SDIO_IDLE_INT_CLR_Msk = 0x10000000 + // Bit SDIO_IDLE_INT_CLR. + PMU_HP_INT_CLR_SDIO_IDLE_INT_CLR = 0x10000000 + // Position of SW_INT_CLR field. + PMU_HP_INT_CLR_SW_INT_CLR_Pos = 0x1d + // Bit mask of SW_INT_CLR field. + PMU_HP_INT_CLR_SW_INT_CLR_Msk = 0x20000000 + // Bit SW_INT_CLR. + PMU_HP_INT_CLR_SW_INT_CLR = 0x20000000 + // Position of SOC_SLEEP_REJECT_INT_CLR field. + PMU_HP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR_Pos = 0x1e + // Bit mask of SOC_SLEEP_REJECT_INT_CLR field. + PMU_HP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR_Msk = 0x40000000 + // Bit SOC_SLEEP_REJECT_INT_CLR. + PMU_HP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR = 0x40000000 + // Position of SOC_WAKEUP_INT_CLR field. + PMU_HP_INT_CLR_SOC_WAKEUP_INT_CLR_Pos = 0x1f + // Bit mask of SOC_WAKEUP_INT_CLR field. + PMU_HP_INT_CLR_SOC_WAKEUP_INT_CLR_Msk = 0x80000000 + // Bit SOC_WAKEUP_INT_CLR. + PMU_HP_INT_CLR_SOC_WAKEUP_INT_CLR = 0x80000000 + + // LP_INT_RAW: need_des + // Position of LP_CPU_WAKEUP_INT_RAW field. + PMU_LP_INT_RAW_LP_CPU_WAKEUP_INT_RAW_Pos = 0x14 + // Bit mask of LP_CPU_WAKEUP_INT_RAW field. + PMU_LP_INT_RAW_LP_CPU_WAKEUP_INT_RAW_Msk = 0x100000 + // Bit LP_CPU_WAKEUP_INT_RAW. + PMU_LP_INT_RAW_LP_CPU_WAKEUP_INT_RAW = 0x100000 + // Position of MODEM_SWITCH_ACTIVE_END_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW_Pos = 0x15 + // Bit mask of MODEM_SWITCH_ACTIVE_END_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW_Msk = 0x200000 + // Bit MODEM_SWITCH_ACTIVE_END_INT_RAW. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_END_INT_RAW = 0x200000 + // Position of SLEEP_SWITCH_ACTIVE_END_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW_Pos = 0x16 + // Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW_Msk = 0x400000 + // Bit SLEEP_SWITCH_ACTIVE_END_INT_RAW. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW = 0x400000 + // Position of SLEEP_SWITCH_MODEM_END_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW_Pos = 0x17 + // Bit mask of SLEEP_SWITCH_MODEM_END_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW_Msk = 0x800000 + // Bit SLEEP_SWITCH_MODEM_END_INT_RAW. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_END_INT_RAW = 0x800000 + // Position of MODEM_SWITCH_SLEEP_END_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW_Pos = 0x18 + // Bit mask of MODEM_SWITCH_SLEEP_END_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW_Msk = 0x1000000 + // Bit MODEM_SWITCH_SLEEP_END_INT_RAW. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_END_INT_RAW = 0x1000000 + // Position of ACTIVE_SWITCH_SLEEP_END_INT_RAW field. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW_Pos = 0x19 + // Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_RAW field. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW_Msk = 0x2000000 + // Bit ACTIVE_SWITCH_SLEEP_END_INT_RAW. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW = 0x2000000 + // Position of MODEM_SWITCH_ACTIVE_START_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW_Pos = 0x1a + // Bit mask of MODEM_SWITCH_ACTIVE_START_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW_Msk = 0x4000000 + // Bit MODEM_SWITCH_ACTIVE_START_INT_RAW. + PMU_LP_INT_RAW_MODEM_SWITCH_ACTIVE_START_INT_RAW = 0x4000000 + // Position of SLEEP_SWITCH_ACTIVE_START_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW_Pos = 0x1b + // Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW_Msk = 0x8000000 + // Bit SLEEP_SWITCH_ACTIVE_START_INT_RAW. + PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW = 0x8000000 + // Position of SLEEP_SWITCH_MODEM_START_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW_Pos = 0x1c + // Bit mask of SLEEP_SWITCH_MODEM_START_INT_RAW field. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW_Msk = 0x10000000 + // Bit SLEEP_SWITCH_MODEM_START_INT_RAW. + PMU_LP_INT_RAW_SLEEP_SWITCH_MODEM_START_INT_RAW = 0x10000000 + // Position of MODEM_SWITCH_SLEEP_START_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW_Pos = 0x1d + // Bit mask of MODEM_SWITCH_SLEEP_START_INT_RAW field. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW_Msk = 0x20000000 + // Bit MODEM_SWITCH_SLEEP_START_INT_RAW. + PMU_LP_INT_RAW_MODEM_SWITCH_SLEEP_START_INT_RAW = 0x20000000 + // Position of ACTIVE_SWITCH_SLEEP_START_INT_RAW field. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW_Pos = 0x1e + // Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_RAW field. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW_Msk = 0x40000000 + // Bit ACTIVE_SWITCH_SLEEP_START_INT_RAW. + PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW = 0x40000000 + // Position of HP_SW_TRIGGER_INT_RAW field. + PMU_LP_INT_RAW_HP_SW_TRIGGER_INT_RAW_Pos = 0x1f + // Bit mask of HP_SW_TRIGGER_INT_RAW field. + PMU_LP_INT_RAW_HP_SW_TRIGGER_INT_RAW_Msk = 0x80000000 + // Bit HP_SW_TRIGGER_INT_RAW. + PMU_LP_INT_RAW_HP_SW_TRIGGER_INT_RAW = 0x80000000 + + // LP_INT_ST: need_des + // Position of LP_CPU_WAKEUP_INT_ST field. + PMU_LP_INT_ST_LP_CPU_WAKEUP_INT_ST_Pos = 0x14 + // Bit mask of LP_CPU_WAKEUP_INT_ST field. + PMU_LP_INT_ST_LP_CPU_WAKEUP_INT_ST_Msk = 0x100000 + // Bit LP_CPU_WAKEUP_INT_ST. + PMU_LP_INT_ST_LP_CPU_WAKEUP_INT_ST = 0x100000 + // Position of MODEM_SWITCH_ACTIVE_END_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST_Pos = 0x15 + // Bit mask of MODEM_SWITCH_ACTIVE_END_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST_Msk = 0x200000 + // Bit MODEM_SWITCH_ACTIVE_END_INT_ST. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_END_INT_ST = 0x200000 + // Position of SLEEP_SWITCH_ACTIVE_END_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST_Pos = 0x16 + // Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST_Msk = 0x400000 + // Bit SLEEP_SWITCH_ACTIVE_END_INT_ST. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST = 0x400000 + // Position of SLEEP_SWITCH_MODEM_END_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST_Pos = 0x17 + // Bit mask of SLEEP_SWITCH_MODEM_END_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST_Msk = 0x800000 + // Bit SLEEP_SWITCH_MODEM_END_INT_ST. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_END_INT_ST = 0x800000 + // Position of MODEM_SWITCH_SLEEP_END_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST_Pos = 0x18 + // Bit mask of MODEM_SWITCH_SLEEP_END_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST_Msk = 0x1000000 + // Bit MODEM_SWITCH_SLEEP_END_INT_ST. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_END_INT_ST = 0x1000000 + // Position of ACTIVE_SWITCH_SLEEP_END_INT_ST field. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST_Pos = 0x19 + // Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_ST field. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST_Msk = 0x2000000 + // Bit ACTIVE_SWITCH_SLEEP_END_INT_ST. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST = 0x2000000 + // Position of MODEM_SWITCH_ACTIVE_START_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST_Pos = 0x1a + // Bit mask of MODEM_SWITCH_ACTIVE_START_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST_Msk = 0x4000000 + // Bit MODEM_SWITCH_ACTIVE_START_INT_ST. + PMU_LP_INT_ST_MODEM_SWITCH_ACTIVE_START_INT_ST = 0x4000000 + // Position of SLEEP_SWITCH_ACTIVE_START_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST_Pos = 0x1b + // Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST_Msk = 0x8000000 + // Bit SLEEP_SWITCH_ACTIVE_START_INT_ST. + PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST = 0x8000000 + // Position of SLEEP_SWITCH_MODEM_START_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST_Pos = 0x1c + // Bit mask of SLEEP_SWITCH_MODEM_START_INT_ST field. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST_Msk = 0x10000000 + // Bit SLEEP_SWITCH_MODEM_START_INT_ST. + PMU_LP_INT_ST_SLEEP_SWITCH_MODEM_START_INT_ST = 0x10000000 + // Position of MODEM_SWITCH_SLEEP_START_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST_Pos = 0x1d + // Bit mask of MODEM_SWITCH_SLEEP_START_INT_ST field. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST_Msk = 0x20000000 + // Bit MODEM_SWITCH_SLEEP_START_INT_ST. + PMU_LP_INT_ST_MODEM_SWITCH_SLEEP_START_INT_ST = 0x20000000 + // Position of ACTIVE_SWITCH_SLEEP_START_INT_ST field. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST_Pos = 0x1e + // Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_ST field. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST_Msk = 0x40000000 + // Bit ACTIVE_SWITCH_SLEEP_START_INT_ST. + PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST = 0x40000000 + // Position of HP_SW_TRIGGER_INT_ST field. + PMU_LP_INT_ST_HP_SW_TRIGGER_INT_ST_Pos = 0x1f + // Bit mask of HP_SW_TRIGGER_INT_ST field. + PMU_LP_INT_ST_HP_SW_TRIGGER_INT_ST_Msk = 0x80000000 + // Bit HP_SW_TRIGGER_INT_ST. + PMU_LP_INT_ST_HP_SW_TRIGGER_INT_ST = 0x80000000 + + // LP_INT_ENA: need_des + // Position of LP_CPU_WAKEUP_INT_ENA field. + PMU_LP_INT_ENA_LP_CPU_WAKEUP_INT_ENA_Pos = 0x14 + // Bit mask of LP_CPU_WAKEUP_INT_ENA field. + PMU_LP_INT_ENA_LP_CPU_WAKEUP_INT_ENA_Msk = 0x100000 + // Bit LP_CPU_WAKEUP_INT_ENA. + PMU_LP_INT_ENA_LP_CPU_WAKEUP_INT_ENA = 0x100000 + // Position of MODEM_SWITCH_ACTIVE_END_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA_Pos = 0x15 + // Bit mask of MODEM_SWITCH_ACTIVE_END_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA_Msk = 0x200000 + // Bit MODEM_SWITCH_ACTIVE_END_INT_ENA. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_END_INT_ENA = 0x200000 + // Position of SLEEP_SWITCH_ACTIVE_END_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA_Pos = 0x16 + // Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA_Msk = 0x400000 + // Bit SLEEP_SWITCH_ACTIVE_END_INT_ENA. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA = 0x400000 + // Position of SLEEP_SWITCH_MODEM_END_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA_Pos = 0x17 + // Bit mask of SLEEP_SWITCH_MODEM_END_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA_Msk = 0x800000 + // Bit SLEEP_SWITCH_MODEM_END_INT_ENA. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_END_INT_ENA = 0x800000 + // Position of MODEM_SWITCH_SLEEP_END_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA_Pos = 0x18 + // Bit mask of MODEM_SWITCH_SLEEP_END_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA_Msk = 0x1000000 + // Bit MODEM_SWITCH_SLEEP_END_INT_ENA. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_END_INT_ENA = 0x1000000 + // Position of ACTIVE_SWITCH_SLEEP_END_INT_ENA field. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA_Pos = 0x19 + // Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_ENA field. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA_Msk = 0x2000000 + // Bit ACTIVE_SWITCH_SLEEP_END_INT_ENA. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA = 0x2000000 + // Position of MODEM_SWITCH_ACTIVE_START_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA_Pos = 0x1a + // Bit mask of MODEM_SWITCH_ACTIVE_START_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA_Msk = 0x4000000 + // Bit MODEM_SWITCH_ACTIVE_START_INT_ENA. + PMU_LP_INT_ENA_MODEM_SWITCH_ACTIVE_START_INT_ENA = 0x4000000 + // Position of SLEEP_SWITCH_ACTIVE_START_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA_Pos = 0x1b + // Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA_Msk = 0x8000000 + // Bit SLEEP_SWITCH_ACTIVE_START_INT_ENA. + PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA = 0x8000000 + // Position of SLEEP_SWITCH_MODEM_START_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA_Pos = 0x1c + // Bit mask of SLEEP_SWITCH_MODEM_START_INT_ENA field. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA_Msk = 0x10000000 + // Bit SLEEP_SWITCH_MODEM_START_INT_ENA. + PMU_LP_INT_ENA_SLEEP_SWITCH_MODEM_START_INT_ENA = 0x10000000 + // Position of MODEM_SWITCH_SLEEP_START_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA_Pos = 0x1d + // Bit mask of MODEM_SWITCH_SLEEP_START_INT_ENA field. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA_Msk = 0x20000000 + // Bit MODEM_SWITCH_SLEEP_START_INT_ENA. + PMU_LP_INT_ENA_MODEM_SWITCH_SLEEP_START_INT_ENA = 0x20000000 + // Position of ACTIVE_SWITCH_SLEEP_START_INT_ENA field. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA_Pos = 0x1e + // Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_ENA field. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA_Msk = 0x40000000 + // Bit ACTIVE_SWITCH_SLEEP_START_INT_ENA. + PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA = 0x40000000 + // Position of HP_SW_TRIGGER_INT_ENA field. + PMU_LP_INT_ENA_HP_SW_TRIGGER_INT_ENA_Pos = 0x1f + // Bit mask of HP_SW_TRIGGER_INT_ENA field. + PMU_LP_INT_ENA_HP_SW_TRIGGER_INT_ENA_Msk = 0x80000000 + // Bit HP_SW_TRIGGER_INT_ENA. + PMU_LP_INT_ENA_HP_SW_TRIGGER_INT_ENA = 0x80000000 + + // LP_INT_CLR: need_des + // Position of LP_CPU_WAKEUP_INT_CLR field. + PMU_LP_INT_CLR_LP_CPU_WAKEUP_INT_CLR_Pos = 0x14 + // Bit mask of LP_CPU_WAKEUP_INT_CLR field. + PMU_LP_INT_CLR_LP_CPU_WAKEUP_INT_CLR_Msk = 0x100000 + // Bit LP_CPU_WAKEUP_INT_CLR. + PMU_LP_INT_CLR_LP_CPU_WAKEUP_INT_CLR = 0x100000 + // Position of MODEM_SWITCH_ACTIVE_END_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR_Pos = 0x15 + // Bit mask of MODEM_SWITCH_ACTIVE_END_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR_Msk = 0x200000 + // Bit MODEM_SWITCH_ACTIVE_END_INT_CLR. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_END_INT_CLR = 0x200000 + // Position of SLEEP_SWITCH_ACTIVE_END_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR_Pos = 0x16 + // Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR_Msk = 0x400000 + // Bit SLEEP_SWITCH_ACTIVE_END_INT_CLR. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR = 0x400000 + // Position of SLEEP_SWITCH_MODEM_END_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR_Pos = 0x17 + // Bit mask of SLEEP_SWITCH_MODEM_END_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR_Msk = 0x800000 + // Bit SLEEP_SWITCH_MODEM_END_INT_CLR. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_END_INT_CLR = 0x800000 + // Position of MODEM_SWITCH_SLEEP_END_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR_Pos = 0x18 + // Bit mask of MODEM_SWITCH_SLEEP_END_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR_Msk = 0x1000000 + // Bit MODEM_SWITCH_SLEEP_END_INT_CLR. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_END_INT_CLR = 0x1000000 + // Position of ACTIVE_SWITCH_SLEEP_END_INT_CLR field. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR_Pos = 0x19 + // Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_CLR field. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR_Msk = 0x2000000 + // Bit ACTIVE_SWITCH_SLEEP_END_INT_CLR. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR = 0x2000000 + // Position of MODEM_SWITCH_ACTIVE_START_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR_Pos = 0x1a + // Bit mask of MODEM_SWITCH_ACTIVE_START_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR_Msk = 0x4000000 + // Bit MODEM_SWITCH_ACTIVE_START_INT_CLR. + PMU_LP_INT_CLR_MODEM_SWITCH_ACTIVE_START_INT_CLR = 0x4000000 + // Position of SLEEP_SWITCH_ACTIVE_START_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR_Pos = 0x1b + // Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR_Msk = 0x8000000 + // Bit SLEEP_SWITCH_ACTIVE_START_INT_CLR. + PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR = 0x8000000 + // Position of SLEEP_SWITCH_MODEM_START_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR_Pos = 0x1c + // Bit mask of SLEEP_SWITCH_MODEM_START_INT_CLR field. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR_Msk = 0x10000000 + // Bit SLEEP_SWITCH_MODEM_START_INT_CLR. + PMU_LP_INT_CLR_SLEEP_SWITCH_MODEM_START_INT_CLR = 0x10000000 + // Position of MODEM_SWITCH_SLEEP_START_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR_Pos = 0x1d + // Bit mask of MODEM_SWITCH_SLEEP_START_INT_CLR field. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR_Msk = 0x20000000 + // Bit MODEM_SWITCH_SLEEP_START_INT_CLR. + PMU_LP_INT_CLR_MODEM_SWITCH_SLEEP_START_INT_CLR = 0x20000000 + // Position of ACTIVE_SWITCH_SLEEP_START_INT_CLR field. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR_Pos = 0x1e + // Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_CLR field. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR_Msk = 0x40000000 + // Bit ACTIVE_SWITCH_SLEEP_START_INT_CLR. + PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR = 0x40000000 + // Position of HP_SW_TRIGGER_INT_CLR field. + PMU_LP_INT_CLR_HP_SW_TRIGGER_INT_CLR_Pos = 0x1f + // Bit mask of HP_SW_TRIGGER_INT_CLR field. + PMU_LP_INT_CLR_HP_SW_TRIGGER_INT_CLR_Msk = 0x80000000 + // Bit HP_SW_TRIGGER_INT_CLR. + PMU_LP_INT_CLR_HP_SW_TRIGGER_INT_CLR = 0x80000000 + + // LP_CPU_PWR0: need_des + // Position of LP_CPU_WAITI_RDY field. + PMU_LP_CPU_PWR0_LP_CPU_WAITI_RDY_Pos = 0x0 + // Bit mask of LP_CPU_WAITI_RDY field. + PMU_LP_CPU_PWR0_LP_CPU_WAITI_RDY_Msk = 0x1 + // Bit LP_CPU_WAITI_RDY. + PMU_LP_CPU_PWR0_LP_CPU_WAITI_RDY = 0x1 + // Position of LP_CPU_STALL_RDY field. + PMU_LP_CPU_PWR0_LP_CPU_STALL_RDY_Pos = 0x1 + // Bit mask of LP_CPU_STALL_RDY field. + PMU_LP_CPU_PWR0_LP_CPU_STALL_RDY_Msk = 0x2 + // Bit LP_CPU_STALL_RDY. + PMU_LP_CPU_PWR0_LP_CPU_STALL_RDY = 0x2 + // Position of LP_CPU_FORCE_STALL field. + PMU_LP_CPU_PWR0_LP_CPU_FORCE_STALL_Pos = 0x12 + // Bit mask of LP_CPU_FORCE_STALL field. + PMU_LP_CPU_PWR0_LP_CPU_FORCE_STALL_Msk = 0x40000 + // Bit LP_CPU_FORCE_STALL. + PMU_LP_CPU_PWR0_LP_CPU_FORCE_STALL = 0x40000 + // Position of LP_CPU_SLP_WAITI_FLAG_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN_Pos = 0x13 + // Bit mask of LP_CPU_SLP_WAITI_FLAG_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN_Msk = 0x80000 + // Bit LP_CPU_SLP_WAITI_FLAG_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN = 0x80000 + // Position of LP_CPU_SLP_STALL_FLAG_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN_Pos = 0x14 + // Bit mask of LP_CPU_SLP_STALL_FLAG_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN_Msk = 0x100000 + // Bit LP_CPU_SLP_STALL_FLAG_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN = 0x100000 + // Position of LP_CPU_SLP_STALL_WAIT field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT_Pos = 0x15 + // Bit mask of LP_CPU_SLP_STALL_WAIT field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT_Msk = 0x1fe00000 + // Position of LP_CPU_SLP_STALL_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_EN_Pos = 0x1d + // Bit mask of LP_CPU_SLP_STALL_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_EN_Msk = 0x20000000 + // Bit LP_CPU_SLP_STALL_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_EN = 0x20000000 + // Position of LP_CPU_SLP_RESET_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_RESET_EN_Pos = 0x1e + // Bit mask of LP_CPU_SLP_RESET_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_RESET_EN_Msk = 0x40000000 + // Bit LP_CPU_SLP_RESET_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_RESET_EN = 0x40000000 + // Position of LP_CPU_SLP_BYPASS_INTR_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN_Pos = 0x1f + // Bit mask of LP_CPU_SLP_BYPASS_INTR_EN field. + PMU_LP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN_Msk = 0x80000000 + // Bit LP_CPU_SLP_BYPASS_INTR_EN. + PMU_LP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN = 0x80000000 + + // LP_CPU_PWR1: need_des + // Position of LP_CPU_WAKEUP_EN field. + PMU_LP_CPU_PWR1_LP_CPU_WAKEUP_EN_Pos = 0x0 + // Bit mask of LP_CPU_WAKEUP_EN field. + PMU_LP_CPU_PWR1_LP_CPU_WAKEUP_EN_Msk = 0xffff + // Position of LP_CPU_SLEEP_REQ field. + PMU_LP_CPU_PWR1_LP_CPU_SLEEP_REQ_Pos = 0x1f + // Bit mask of LP_CPU_SLEEP_REQ field. + PMU_LP_CPU_PWR1_LP_CPU_SLEEP_REQ_Msk = 0x80000000 + // Bit LP_CPU_SLEEP_REQ. + PMU_LP_CPU_PWR1_LP_CPU_SLEEP_REQ = 0x80000000 + + // HP_LP_CPU_COMM: need_des + // Position of LP_TRIGGER_HP field. + PMU_HP_LP_CPU_COMM_LP_TRIGGER_HP_Pos = 0x1e + // Bit mask of LP_TRIGGER_HP field. + PMU_HP_LP_CPU_COMM_LP_TRIGGER_HP_Msk = 0x40000000 + // Bit LP_TRIGGER_HP. + PMU_HP_LP_CPU_COMM_LP_TRIGGER_HP = 0x40000000 + // Position of HP_TRIGGER_LP field. + PMU_HP_LP_CPU_COMM_HP_TRIGGER_LP_Pos = 0x1f + // Bit mask of HP_TRIGGER_LP field. + PMU_HP_LP_CPU_COMM_HP_TRIGGER_LP_Msk = 0x80000000 + // Bit HP_TRIGGER_LP. + PMU_HP_LP_CPU_COMM_HP_TRIGGER_LP = 0x80000000 + + // HP_REGULATOR_CFG: need_des + // Position of DIG_REGULATOR_EN_CAL field. + PMU_HP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL_Pos = 0x1f + // Bit mask of DIG_REGULATOR_EN_CAL field. + PMU_HP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL_Msk = 0x80000000 + // Bit DIG_REGULATOR_EN_CAL. + PMU_HP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL = 0x80000000 + + // MAIN_STATE: need_des + // Position of MAIN_LAST_ST_STATE field. + PMU_MAIN_STATE_MAIN_LAST_ST_STATE_Pos = 0xb + // Bit mask of MAIN_LAST_ST_STATE field. + PMU_MAIN_STATE_MAIN_LAST_ST_STATE_Msk = 0x3f800 + // Position of MAIN_TAR_ST_STATE field. + PMU_MAIN_STATE_MAIN_TAR_ST_STATE_Pos = 0x12 + // Bit mask of MAIN_TAR_ST_STATE field. + PMU_MAIN_STATE_MAIN_TAR_ST_STATE_Msk = 0x1fc0000 + // Position of MAIN_CUR_ST_STATE field. + PMU_MAIN_STATE_MAIN_CUR_ST_STATE_Pos = 0x19 + // Bit mask of MAIN_CUR_ST_STATE field. + PMU_MAIN_STATE_MAIN_CUR_ST_STATE_Msk = 0xfe000000 + + // PWR_STATE: need_des + // Position of BACKUP_ST_STATE field. + PMU_PWR_STATE_BACKUP_ST_STATE_Pos = 0xd + // Bit mask of BACKUP_ST_STATE field. + PMU_PWR_STATE_BACKUP_ST_STATE_Msk = 0x3e000 + // Position of LP_PWR_ST_STATE field. + PMU_PWR_STATE_LP_PWR_ST_STATE_Pos = 0x12 + // Bit mask of LP_PWR_ST_STATE field. + PMU_PWR_STATE_LP_PWR_ST_STATE_Msk = 0x7c0000 + // Position of HP_PWR_ST_STATE field. + PMU_PWR_STATE_HP_PWR_ST_STATE_Pos = 0x17 + // Bit mask of HP_PWR_ST_STATE field. + PMU_PWR_STATE_HP_PWR_ST_STATE_Msk = 0xff800000 + + // CLK_STATE0: need_des + // Position of STABLE_XPD_BBPLL_STATE field. + PMU_CLK_STATE0_STABLE_XPD_BBPLL_STATE_Pos = 0x0 + // Bit mask of STABLE_XPD_BBPLL_STATE field. + PMU_CLK_STATE0_STABLE_XPD_BBPLL_STATE_Msk = 0x1 + // Bit STABLE_XPD_BBPLL_STATE. + PMU_CLK_STATE0_STABLE_XPD_BBPLL_STATE = 0x1 + // Position of STABLE_XPD_XTAL_STATE field. + PMU_CLK_STATE0_STABLE_XPD_XTAL_STATE_Pos = 0x1 + // Bit mask of STABLE_XPD_XTAL_STATE field. + PMU_CLK_STATE0_STABLE_XPD_XTAL_STATE_Msk = 0x2 + // Bit STABLE_XPD_XTAL_STATE. + PMU_CLK_STATE0_STABLE_XPD_XTAL_STATE = 0x2 + // Position of SYS_CLK_SLP_SEL_STATE field. + PMU_CLK_STATE0_SYS_CLK_SLP_SEL_STATE_Pos = 0xf + // Bit mask of SYS_CLK_SLP_SEL_STATE field. + PMU_CLK_STATE0_SYS_CLK_SLP_SEL_STATE_Msk = 0x8000 + // Bit SYS_CLK_SLP_SEL_STATE. + PMU_CLK_STATE0_SYS_CLK_SLP_SEL_STATE = 0x8000 + // Position of SYS_CLK_SEL_STATE field. + PMU_CLK_STATE0_SYS_CLK_SEL_STATE_Pos = 0x10 + // Bit mask of SYS_CLK_SEL_STATE field. + PMU_CLK_STATE0_SYS_CLK_SEL_STATE_Msk = 0x30000 + // Position of SYS_CLK_NO_DIV_STATE field. + PMU_CLK_STATE0_SYS_CLK_NO_DIV_STATE_Pos = 0x12 + // Bit mask of SYS_CLK_NO_DIV_STATE field. + PMU_CLK_STATE0_SYS_CLK_NO_DIV_STATE_Msk = 0x40000 + // Bit SYS_CLK_NO_DIV_STATE. + PMU_CLK_STATE0_SYS_CLK_NO_DIV_STATE = 0x40000 + // Position of ICG_SYS_CLK_EN_STATE field. + PMU_CLK_STATE0_ICG_SYS_CLK_EN_STATE_Pos = 0x13 + // Bit mask of ICG_SYS_CLK_EN_STATE field. + PMU_CLK_STATE0_ICG_SYS_CLK_EN_STATE_Msk = 0x80000 + // Bit ICG_SYS_CLK_EN_STATE. + PMU_CLK_STATE0_ICG_SYS_CLK_EN_STATE = 0x80000 + // Position of ICG_MODEM_SWITCH_STATE field. + PMU_CLK_STATE0_ICG_MODEM_SWITCH_STATE_Pos = 0x14 + // Bit mask of ICG_MODEM_SWITCH_STATE field. + PMU_CLK_STATE0_ICG_MODEM_SWITCH_STATE_Msk = 0x100000 + // Bit ICG_MODEM_SWITCH_STATE. + PMU_CLK_STATE0_ICG_MODEM_SWITCH_STATE = 0x100000 + // Position of ICG_MODEM_CODE_STATE field. + PMU_CLK_STATE0_ICG_MODEM_CODE_STATE_Pos = 0x15 + // Bit mask of ICG_MODEM_CODE_STATE field. + PMU_CLK_STATE0_ICG_MODEM_CODE_STATE_Msk = 0x600000 + // Position of ICG_SLP_SEL_STATE field. + PMU_CLK_STATE0_ICG_SLP_SEL_STATE_Pos = 0x17 + // Bit mask of ICG_SLP_SEL_STATE field. + PMU_CLK_STATE0_ICG_SLP_SEL_STATE_Msk = 0x800000 + // Bit ICG_SLP_SEL_STATE. + PMU_CLK_STATE0_ICG_SLP_SEL_STATE = 0x800000 + // Position of ICG_GLOBAL_XTAL_STATE field. + PMU_CLK_STATE0_ICG_GLOBAL_XTAL_STATE_Pos = 0x18 + // Bit mask of ICG_GLOBAL_XTAL_STATE field. + PMU_CLK_STATE0_ICG_GLOBAL_XTAL_STATE_Msk = 0x1000000 + // Bit ICG_GLOBAL_XTAL_STATE. + PMU_CLK_STATE0_ICG_GLOBAL_XTAL_STATE = 0x1000000 + // Position of ICG_GLOBAL_PLL_STATE field. + PMU_CLK_STATE0_ICG_GLOBAL_PLL_STATE_Pos = 0x19 + // Bit mask of ICG_GLOBAL_PLL_STATE field. + PMU_CLK_STATE0_ICG_GLOBAL_PLL_STATE_Msk = 0x2000000 + // Bit ICG_GLOBAL_PLL_STATE. + PMU_CLK_STATE0_ICG_GLOBAL_PLL_STATE = 0x2000000 + // Position of ANA_I2C_ISO_EN_STATE field. + PMU_CLK_STATE0_ANA_I2C_ISO_EN_STATE_Pos = 0x1a + // Bit mask of ANA_I2C_ISO_EN_STATE field. + PMU_CLK_STATE0_ANA_I2C_ISO_EN_STATE_Msk = 0x4000000 + // Bit ANA_I2C_ISO_EN_STATE. + PMU_CLK_STATE0_ANA_I2C_ISO_EN_STATE = 0x4000000 + // Position of ANA_I2C_RETENTION_STATE field. + PMU_CLK_STATE0_ANA_I2C_RETENTION_STATE_Pos = 0x1b + // Bit mask of ANA_I2C_RETENTION_STATE field. + PMU_CLK_STATE0_ANA_I2C_RETENTION_STATE_Msk = 0x8000000 + // Bit ANA_I2C_RETENTION_STATE. + PMU_CLK_STATE0_ANA_I2C_RETENTION_STATE = 0x8000000 + // Position of ANA_XPD_BB_I2C_STATE field. + PMU_CLK_STATE0_ANA_XPD_BB_I2C_STATE_Pos = 0x1c + // Bit mask of ANA_XPD_BB_I2C_STATE field. + PMU_CLK_STATE0_ANA_XPD_BB_I2C_STATE_Msk = 0x10000000 + // Bit ANA_XPD_BB_I2C_STATE. + PMU_CLK_STATE0_ANA_XPD_BB_I2C_STATE = 0x10000000 + // Position of ANA_XPD_BBPLL_I2C_STATE field. + PMU_CLK_STATE0_ANA_XPD_BBPLL_I2C_STATE_Pos = 0x1d + // Bit mask of ANA_XPD_BBPLL_I2C_STATE field. + PMU_CLK_STATE0_ANA_XPD_BBPLL_I2C_STATE_Msk = 0x20000000 + // Bit ANA_XPD_BBPLL_I2C_STATE. + PMU_CLK_STATE0_ANA_XPD_BBPLL_I2C_STATE = 0x20000000 + // Position of ANA_XPD_BBPLL_STATE field. + PMU_CLK_STATE0_ANA_XPD_BBPLL_STATE_Pos = 0x1e + // Bit mask of ANA_XPD_BBPLL_STATE field. + PMU_CLK_STATE0_ANA_XPD_BBPLL_STATE_Msk = 0x40000000 + // Bit ANA_XPD_BBPLL_STATE. + PMU_CLK_STATE0_ANA_XPD_BBPLL_STATE = 0x40000000 + // Position of ANA_XPD_XTAL_STATE field. + PMU_CLK_STATE0_ANA_XPD_XTAL_STATE_Pos = 0x1f + // Bit mask of ANA_XPD_XTAL_STATE field. + PMU_CLK_STATE0_ANA_XPD_XTAL_STATE_Msk = 0x80000000 + // Bit ANA_XPD_XTAL_STATE. + PMU_CLK_STATE0_ANA_XPD_XTAL_STATE = 0x80000000 + + // CLK_STATE1: need_des + // Position of ICG_FUNC_EN_STATE field. + PMU_CLK_STATE1_ICG_FUNC_EN_STATE_Pos = 0x0 + // Bit mask of ICG_FUNC_EN_STATE field. + PMU_CLK_STATE1_ICG_FUNC_EN_STATE_Msk = 0xffffffff + + // CLK_STATE2: need_des + // Position of ICG_APB_EN_STATE field. + PMU_CLK_STATE2_ICG_APB_EN_STATE_Pos = 0x0 + // Bit mask of ICG_APB_EN_STATE field. + PMU_CLK_STATE2_ICG_APB_EN_STATE_Msk = 0xffffffff + + // VDD_SPI_STATUS: need_des + // Position of STABLE_VDD_SPI_PWR_DRV field. + PMU_VDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV_Pos = 0x1f + // Bit mask of STABLE_VDD_SPI_PWR_DRV field. + PMU_VDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV_Msk = 0x80000000 + // Bit STABLE_VDD_SPI_PWR_DRV. + PMU_VDD_SPI_STATUS_STABLE_VDD_SPI_PWR_DRV = 0x80000000 + + // DATE: need_des + // Position of PMU_DATE field. + PMU_DATE_PMU_DATE_Pos = 0x0 + // Bit mask of PMU_DATE field. + PMU_DATE_PMU_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + PMU_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + PMU_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + PMU_DATE_CLK_EN = 0x80000000 +) + +// Constants for RMT: Remote Control +const ( + // CH0DATA: The read and write data register for CHANNEL%s by apb fifo access. + // Position of DATA field. + RMT_CHDATA_DATA_Pos = 0x0 + // Bit mask of DATA field. + RMT_CHDATA_DATA_Msk = 0xffffffff + + // CH0_TX_CONF0: Channel %s configure register 0 + // Position of TX_START field. + RMT_CH_TX_CONF0_TX_START_Pos = 0x0 + // Bit mask of TX_START field. + RMT_CH_TX_CONF0_TX_START_Msk = 0x1 + // Bit TX_START. + RMT_CH_TX_CONF0_TX_START = 0x1 + // Position of MEM_RD_RST field. + RMT_CH_TX_CONF0_MEM_RD_RST_Pos = 0x1 + // Bit mask of MEM_RD_RST field. + RMT_CH_TX_CONF0_MEM_RD_RST_Msk = 0x2 + // Bit MEM_RD_RST. + RMT_CH_TX_CONF0_MEM_RD_RST = 0x2 + // Position of APB_MEM_RST field. + RMT_CH_TX_CONF0_APB_MEM_RST_Pos = 0x2 + // Bit mask of APB_MEM_RST field. + RMT_CH_TX_CONF0_APB_MEM_RST_Msk = 0x4 + // Bit APB_MEM_RST. + RMT_CH_TX_CONF0_APB_MEM_RST = 0x4 + // Position of TX_CONTI_MODE field. + RMT_CH_TX_CONF0_TX_CONTI_MODE_Pos = 0x3 + // Bit mask of TX_CONTI_MODE field. + RMT_CH_TX_CONF0_TX_CONTI_MODE_Msk = 0x8 + // Bit TX_CONTI_MODE. + RMT_CH_TX_CONF0_TX_CONTI_MODE = 0x8 + // Position of MEM_TX_WRAP_EN field. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN_Pos = 0x4 + // Bit mask of MEM_TX_WRAP_EN field. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN_Msk = 0x10 + // Bit MEM_TX_WRAP_EN. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN = 0x10 + // Position of IDLE_OUT_LV field. + RMT_CH_TX_CONF0_IDLE_OUT_LV_Pos = 0x5 + // Bit mask of IDLE_OUT_LV field. + RMT_CH_TX_CONF0_IDLE_OUT_LV_Msk = 0x20 + // Bit IDLE_OUT_LV. + RMT_CH_TX_CONF0_IDLE_OUT_LV = 0x20 + // Position of IDLE_OUT_EN field. + RMT_CH_TX_CONF0_IDLE_OUT_EN_Pos = 0x6 + // Bit mask of IDLE_OUT_EN field. + RMT_CH_TX_CONF0_IDLE_OUT_EN_Msk = 0x40 + // Bit IDLE_OUT_EN. + RMT_CH_TX_CONF0_IDLE_OUT_EN = 0x40 + // Position of TX_STOP field. + RMT_CH_TX_CONF0_TX_STOP_Pos = 0x7 + // Bit mask of TX_STOP field. + RMT_CH_TX_CONF0_TX_STOP_Msk = 0x80 + // Bit TX_STOP. + RMT_CH_TX_CONF0_TX_STOP = 0x80 + // Position of DIV_CNT field. + RMT_CH_TX_CONF0_DIV_CNT_Pos = 0x8 + // Bit mask of DIV_CNT field. + RMT_CH_TX_CONF0_DIV_CNT_Msk = 0xff00 + // Position of MEM_SIZE field. + RMT_CH_TX_CONF0_MEM_SIZE_Pos = 0x10 + // Bit mask of MEM_SIZE field. + RMT_CH_TX_CONF0_MEM_SIZE_Msk = 0x70000 + // Position of CARRIER_EFF_EN field. + RMT_CH_TX_CONF0_CARRIER_EFF_EN_Pos = 0x14 + // Bit mask of CARRIER_EFF_EN field. + RMT_CH_TX_CONF0_CARRIER_EFF_EN_Msk = 0x100000 + // Bit CARRIER_EFF_EN. + RMT_CH_TX_CONF0_CARRIER_EFF_EN = 0x100000 + // Position of CARRIER_EN field. + RMT_CH_TX_CONF0_CARRIER_EN_Pos = 0x15 + // Bit mask of CARRIER_EN field. + RMT_CH_TX_CONF0_CARRIER_EN_Msk = 0x200000 + // Bit CARRIER_EN. + RMT_CH_TX_CONF0_CARRIER_EN = 0x200000 + // Position of CARRIER_OUT_LV field. + RMT_CH_TX_CONF0_CARRIER_OUT_LV_Pos = 0x16 + // Bit mask of CARRIER_OUT_LV field. + RMT_CH_TX_CONF0_CARRIER_OUT_LV_Msk = 0x400000 + // Bit CARRIER_OUT_LV. + RMT_CH_TX_CONF0_CARRIER_OUT_LV = 0x400000 + // Position of AFIFO_RST field. + RMT_CH_TX_CONF0_AFIFO_RST_Pos = 0x17 + // Bit mask of AFIFO_RST field. + RMT_CH_TX_CONF0_AFIFO_RST_Msk = 0x800000 + // Bit AFIFO_RST. + RMT_CH_TX_CONF0_AFIFO_RST = 0x800000 + // Position of CONF_UPDATE field. + RMT_CH_TX_CONF0_CONF_UPDATE_Pos = 0x18 + // Bit mask of CONF_UPDATE field. + RMT_CH_TX_CONF0_CONF_UPDATE_Msk = 0x1000000 + // Bit CONF_UPDATE. + RMT_CH_TX_CONF0_CONF_UPDATE = 0x1000000 + + // CH2_RX_CONF0: Channel %s configure register 0 + // Position of DIV_CNT field. + RMT_CH_RX_CONF0_DIV_CNT_Pos = 0x0 + // Bit mask of DIV_CNT field. + RMT_CH_RX_CONF0_DIV_CNT_Msk = 0xff + // Position of IDLE_THRES field. + RMT_CH_RX_CONF0_IDLE_THRES_Pos = 0x8 + // Bit mask of IDLE_THRES field. + RMT_CH_RX_CONF0_IDLE_THRES_Msk = 0x7fff00 + // Position of MEM_SIZE field. + RMT_CH_RX_CONF0_MEM_SIZE_Pos = 0x17 + // Bit mask of MEM_SIZE field. + RMT_CH_RX_CONF0_MEM_SIZE_Msk = 0x3800000 + // Position of CARRIER_EN field. + RMT_CH_RX_CONF0_CARRIER_EN_Pos = 0x1c + // Bit mask of CARRIER_EN field. + RMT_CH_RX_CONF0_CARRIER_EN_Msk = 0x10000000 + // Bit CARRIER_EN. + RMT_CH_RX_CONF0_CARRIER_EN = 0x10000000 + // Position of CARRIER_OUT_LV field. + RMT_CH_RX_CONF0_CARRIER_OUT_LV_Pos = 0x1d + // Bit mask of CARRIER_OUT_LV field. + RMT_CH_RX_CONF0_CARRIER_OUT_LV_Msk = 0x20000000 + // Bit CARRIER_OUT_LV. + RMT_CH_RX_CONF0_CARRIER_OUT_LV = 0x20000000 + + // CH2_RX_CONF1: Channel %s configure register 1 + // Position of RX_EN field. + RMT_CH_RX_CONF1_RX_EN_Pos = 0x0 + // Bit mask of RX_EN field. + RMT_CH_RX_CONF1_RX_EN_Msk = 0x1 + // Bit RX_EN. + RMT_CH_RX_CONF1_RX_EN = 0x1 + // Position of MEM_WR_RST field. + RMT_CH_RX_CONF1_MEM_WR_RST_Pos = 0x1 + // Bit mask of MEM_WR_RST field. + RMT_CH_RX_CONF1_MEM_WR_RST_Msk = 0x2 + // Bit MEM_WR_RST. + RMT_CH_RX_CONF1_MEM_WR_RST = 0x2 + // Position of APB_MEM_RST field. + RMT_CH_RX_CONF1_APB_MEM_RST_Pos = 0x2 + // Bit mask of APB_MEM_RST field. + RMT_CH_RX_CONF1_APB_MEM_RST_Msk = 0x4 + // Bit APB_MEM_RST. + RMT_CH_RX_CONF1_APB_MEM_RST = 0x4 + // Position of MEM_OWNER field. + RMT_CH_RX_CONF1_MEM_OWNER_Pos = 0x3 + // Bit mask of MEM_OWNER field. + RMT_CH_RX_CONF1_MEM_OWNER_Msk = 0x8 + // Bit MEM_OWNER. + RMT_CH_RX_CONF1_MEM_OWNER = 0x8 + // Position of RX_FILTER_EN field. + RMT_CH_RX_CONF1_RX_FILTER_EN_Pos = 0x4 + // Bit mask of RX_FILTER_EN field. + RMT_CH_RX_CONF1_RX_FILTER_EN_Msk = 0x10 + // Bit RX_FILTER_EN. + RMT_CH_RX_CONF1_RX_FILTER_EN = 0x10 + // Position of RX_FILTER_THRES field. + RMT_CH_RX_CONF1_RX_FILTER_THRES_Pos = 0x5 + // Bit mask of RX_FILTER_THRES field. + RMT_CH_RX_CONF1_RX_FILTER_THRES_Msk = 0x1fe0 + // Position of MEM_RX_WRAP_EN field. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN_Pos = 0xd + // Bit mask of MEM_RX_WRAP_EN field. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN_Msk = 0x2000 + // Bit MEM_RX_WRAP_EN. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN = 0x2000 + // Position of AFIFO_RST field. + RMT_CH_RX_CONF1_AFIFO_RST_Pos = 0xe + // Bit mask of AFIFO_RST field. + RMT_CH_RX_CONF1_AFIFO_RST_Msk = 0x4000 + // Bit AFIFO_RST. + RMT_CH_RX_CONF1_AFIFO_RST = 0x4000 + // Position of CONF_UPDATE field. + RMT_CH_RX_CONF1_CONF_UPDATE_Pos = 0xf + // Bit mask of CONF_UPDATE field. + RMT_CH_RX_CONF1_CONF_UPDATE_Msk = 0x8000 + // Bit CONF_UPDATE. + RMT_CH_RX_CONF1_CONF_UPDATE = 0x8000 + + // CH0_TX_STATUS: Channel %s status register + // Position of MEM_RADDR_EX field. + RMT_CH_TX_STATUS_MEM_RADDR_EX_Pos = 0x0 + // Bit mask of MEM_RADDR_EX field. + RMT_CH_TX_STATUS_MEM_RADDR_EX_Msk = 0x1ff + // Position of STATE field. + RMT_CH_TX_STATUS_STATE_Pos = 0x9 + // Bit mask of STATE field. + RMT_CH_TX_STATUS_STATE_Msk = 0xe00 + // Position of APB_MEM_WADDR field. + RMT_CH_TX_STATUS_APB_MEM_WADDR_Pos = 0xc + // Bit mask of APB_MEM_WADDR field. + RMT_CH_TX_STATUS_APB_MEM_WADDR_Msk = 0x1ff000 + // Position of APB_MEM_RD_ERR field. + RMT_CH_TX_STATUS_APB_MEM_RD_ERR_Pos = 0x15 + // Bit mask of APB_MEM_RD_ERR field. + RMT_CH_TX_STATUS_APB_MEM_RD_ERR_Msk = 0x200000 + // Bit APB_MEM_RD_ERR. + RMT_CH_TX_STATUS_APB_MEM_RD_ERR = 0x200000 + // Position of MEM_EMPTY field. + RMT_CH_TX_STATUS_MEM_EMPTY_Pos = 0x16 + // Bit mask of MEM_EMPTY field. + RMT_CH_TX_STATUS_MEM_EMPTY_Msk = 0x400000 + // Bit MEM_EMPTY. + RMT_CH_TX_STATUS_MEM_EMPTY = 0x400000 + // Position of APB_MEM_WR_ERR field. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR_Pos = 0x17 + // Bit mask of APB_MEM_WR_ERR field. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR_Msk = 0x800000 + // Bit APB_MEM_WR_ERR. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR = 0x800000 + // Position of APB_MEM_RADDR field. + RMT_CH_TX_STATUS_APB_MEM_RADDR_Pos = 0x18 + // Bit mask of APB_MEM_RADDR field. + RMT_CH_TX_STATUS_APB_MEM_RADDR_Msk = 0xff000000 + + // CH0_RX_STATUS: Channel %s status register + // Position of MEM_WADDR_EX field. + RMT_CH_RX_STATUS_MEM_WADDR_EX_Pos = 0x0 + // Bit mask of MEM_WADDR_EX field. + RMT_CH_RX_STATUS_MEM_WADDR_EX_Msk = 0x1ff + // Position of APB_MEM_RADDR field. + RMT_CH_RX_STATUS_APB_MEM_RADDR_Pos = 0xc + // Bit mask of APB_MEM_RADDR field. + RMT_CH_RX_STATUS_APB_MEM_RADDR_Msk = 0x1ff000 + // Position of STATE field. + RMT_CH_RX_STATUS_STATE_Pos = 0x16 + // Bit mask of STATE field. + RMT_CH_RX_STATUS_STATE_Msk = 0x1c00000 + // Position of MEM_OWNER_ERR field. + RMT_CH_RX_STATUS_MEM_OWNER_ERR_Pos = 0x19 + // Bit mask of MEM_OWNER_ERR field. + RMT_CH_RX_STATUS_MEM_OWNER_ERR_Msk = 0x2000000 + // Bit MEM_OWNER_ERR. + RMT_CH_RX_STATUS_MEM_OWNER_ERR = 0x2000000 + // Position of MEM_FULL field. + RMT_CH_RX_STATUS_MEM_FULL_Pos = 0x1a + // Bit mask of MEM_FULL field. + RMT_CH_RX_STATUS_MEM_FULL_Msk = 0x4000000 + // Bit MEM_FULL. + RMT_CH_RX_STATUS_MEM_FULL = 0x4000000 + // Position of APB_MEM_RD_ERR field. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR_Pos = 0x1b + // Bit mask of APB_MEM_RD_ERR field. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR_Msk = 0x8000000 + // Bit APB_MEM_RD_ERR. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR = 0x8000000 + + // INT_RAW: Raw interrupt status + // Position of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_RAW_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_RAW_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_RAW_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_RAW_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_RAW_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_RAW_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_RAW_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_RAW_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_RAW_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_RAW_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_RAW_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_RAW_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_RAW_CH_s_TX_LOOP = 0x1000 + + // INT_ST: Masked interrupt status + // Position of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ST_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_ST_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_ST_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_ST_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_ST_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_ST_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_ST_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_ST_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ST_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_ST_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_ST_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_ST_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_X_LOOP field. + RMT_INT_ST_CH_s_X_LOOP_Pos = 0xc + // Bit mask of CH_s_X_LOOP field. + RMT_INT_ST_CH_s_X_LOOP_Msk = 0x1000 + // Bit CH_s_X_LOOP. + RMT_INT_ST_CH_s_X_LOOP = 0x1000 + + // INT_ENA: Interrupt enable bits + // Position of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ENA_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_ENA_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_ENA_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_ENA_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_ENA_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_ENA_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_ENA_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_ENA_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ENA_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_ENA_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_ENA_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_ENA_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_X_LOOP field. + RMT_INT_ENA_CH_s_X_LOOP_Pos = 0xc + // Bit mask of CH_s_X_LOOP field. + RMT_INT_ENA_CH_s_X_LOOP_Msk = 0x1000 + // Bit CH_s_X_LOOP. + RMT_INT_ENA_CH_s_X_LOOP = 0x1000 + + // INT_CLR: Interrupt clear bits + // Position of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_CLR_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Pos = 0x2 + // Bit mask of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Msk = 0x4 + // Bit CH_s_RX_END. + RMT_INT_CLR_CH_s_RX_END = 0x4 + // Position of CH_s_TX_ERR field. + RMT_INT_CLR_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_CLR_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_CLR_CH_s_TX_ERR = 0x10 + // Position of CH_s_RX_ERR field. + RMT_INT_CLR_CH_s_RX_ERR_Pos = 0x6 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_CLR_CH_s_RX_ERR_Msk = 0x40 + // Bit CH_s_RX_ERR. + RMT_INT_CLR_CH_s_RX_ERR = 0x40 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_CLR_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_CLR_CH_s_RX_THR_EVENT_Pos = 0xa + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_CLR_CH_s_RX_THR_EVENT_Msk = 0x400 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_CLR_CH_s_RX_THR_EVENT = 0x400 + // Position of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_CLR_CH_s_TX_LOOP = 0x1000 + + // CH0CARRIER_DUTY: Channel %s duty cycle configuration register + // Position of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Pos = 0x0 + // Bit mask of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Msk = 0xffff + // Position of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Pos = 0x10 + // Bit mask of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Msk = 0xffff0000 + + // CH0_RX_CARRIER_RM: Channel %s carrier remove register + // Position of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Pos = 0x0 + // Bit mask of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Msk = 0xffff + // Position of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Pos = 0x10 + // Bit mask of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Msk = 0xffff0000 + + // CH0_TX_LIM: Channel %s Tx event configuration register + // Position of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Pos = 0x0 + // Bit mask of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Msk = 0x1ff + // Position of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Pos = 0x9 + // Bit mask of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Msk = 0x7fe00 + // Position of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Pos = 0x13 + // Bit mask of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Msk = 0x80000 + // Bit TX_LOOP_CNT_EN. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN = 0x80000 + // Position of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Pos = 0x14 + // Bit mask of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Msk = 0x100000 + // Bit LOOP_COUNT_RESET. + RMT_CH_TX_LIM_LOOP_COUNT_RESET = 0x100000 + // Position of LOOP_STOP_EN field. + RMT_CH_TX_LIM_LOOP_STOP_EN_Pos = 0x15 + // Bit mask of LOOP_STOP_EN field. + RMT_CH_TX_LIM_LOOP_STOP_EN_Msk = 0x200000 + // Bit LOOP_STOP_EN. + RMT_CH_TX_LIM_LOOP_STOP_EN = 0x200000 + + // CH0_RX_LIM: Channel %s Rx event configuration register + // Position of RMT_RX_LIM field. + RMT_CH_RX_LIM_RMT_RX_LIM_Pos = 0x0 + // Bit mask of RMT_RX_LIM field. + RMT_CH_RX_LIM_RMT_RX_LIM_Msk = 0x1ff + + // SYS_CONF: RMT apb configuration register + // Position of APB_FIFO_MASK field. + RMT_SYS_CONF_APB_FIFO_MASK_Pos = 0x0 + // Bit mask of APB_FIFO_MASK field. + RMT_SYS_CONF_APB_FIFO_MASK_Msk = 0x1 + // Bit APB_FIFO_MASK. + RMT_SYS_CONF_APB_FIFO_MASK = 0x1 + // Position of MEM_CLK_FORCE_ON field. + RMT_SYS_CONF_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + RMT_SYS_CONF_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + RMT_SYS_CONF_MEM_CLK_FORCE_ON = 0x2 + // Position of MEM_FORCE_PD field. + RMT_SYS_CONF_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of MEM_FORCE_PD field. + RMT_SYS_CONF_MEM_FORCE_PD_Msk = 0x4 + // Bit MEM_FORCE_PD. + RMT_SYS_CONF_MEM_FORCE_PD = 0x4 + // Position of MEM_FORCE_PU field. + RMT_SYS_CONF_MEM_FORCE_PU_Pos = 0x3 + // Bit mask of MEM_FORCE_PU field. + RMT_SYS_CONF_MEM_FORCE_PU_Msk = 0x8 + // Bit MEM_FORCE_PU. + RMT_SYS_CONF_MEM_FORCE_PU = 0x8 + // Position of SCLK_DIV_NUM field. + RMT_SYS_CONF_SCLK_DIV_NUM_Pos = 0x4 + // Bit mask of SCLK_DIV_NUM field. + RMT_SYS_CONF_SCLK_DIV_NUM_Msk = 0xff0 + // Position of SCLK_DIV_A field. + RMT_SYS_CONF_SCLK_DIV_A_Pos = 0xc + // Bit mask of SCLK_DIV_A field. + RMT_SYS_CONF_SCLK_DIV_A_Msk = 0x3f000 + // Position of SCLK_DIV_B field. + RMT_SYS_CONF_SCLK_DIV_B_Pos = 0x12 + // Bit mask of SCLK_DIV_B field. + RMT_SYS_CONF_SCLK_DIV_B_Msk = 0xfc0000 + // Position of SCLK_SEL field. + RMT_SYS_CONF_SCLK_SEL_Pos = 0x18 + // Bit mask of SCLK_SEL field. + RMT_SYS_CONF_SCLK_SEL_Msk = 0x3000000 + // Position of SCLK_ACTIVE field. + RMT_SYS_CONF_SCLK_ACTIVE_Pos = 0x1a + // Bit mask of SCLK_ACTIVE field. + RMT_SYS_CONF_SCLK_ACTIVE_Msk = 0x4000000 + // Bit SCLK_ACTIVE. + RMT_SYS_CONF_SCLK_ACTIVE = 0x4000000 + // Position of CLK_EN field. + RMT_SYS_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + RMT_SYS_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + RMT_SYS_CONF_CLK_EN = 0x80000000 + + // TX_SIM: RMT TX synchronous register + // Position of CH0 field. + RMT_TX_SIM_CH0_Pos = 0x0 + // Bit mask of CH0 field. + RMT_TX_SIM_CH0_Msk = 0x1 + // Bit CH0. + RMT_TX_SIM_CH0 = 0x1 + // Position of CH1 field. + RMT_TX_SIM_CH1_Pos = 0x1 + // Bit mask of CH1 field. + RMT_TX_SIM_CH1_Msk = 0x2 + // Bit CH1. + RMT_TX_SIM_CH1 = 0x2 + // Position of EN field. + RMT_TX_SIM_EN_Pos = 0x2 + // Bit mask of EN field. + RMT_TX_SIM_EN_Msk = 0x4 + // Bit EN. + RMT_TX_SIM_EN = 0x4 + + // REF_CNT_RST: RMT clock divider reset register + // Position of TX_REF_CNT_RST field. + RMT_REF_CNT_RST_TX_REF_CNT_RST_Pos = 0x0 + // Bit mask of TX_REF_CNT_RST field. + RMT_REF_CNT_RST_TX_REF_CNT_RST_Msk = 0x1 + // Bit TX_REF_CNT_RST. + RMT_REF_CNT_RST_TX_REF_CNT_RST = 0x1 + // Position of TX_REF_CNT_RST_CH1 field. + RMT_REF_CNT_RST_TX_REF_CNT_RST_CH1_Pos = 0x1 + // Bit mask of TX_REF_CNT_RST_CH1 field. + RMT_REF_CNT_RST_TX_REF_CNT_RST_CH1_Msk = 0x2 + // Bit TX_REF_CNT_RST_CH1. + RMT_REF_CNT_RST_TX_REF_CNT_RST_CH1 = 0x2 + // Position of RX_REF_CNT_RST_CH2 field. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH2_Pos = 0x2 + // Bit mask of RX_REF_CNT_RST_CH2 field. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH2_Msk = 0x4 + // Bit RX_REF_CNT_RST_CH2. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH2 = 0x4 + // Position of RX_REF_CNT_RST_CH3 field. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH3_Pos = 0x3 + // Bit mask of RX_REF_CNT_RST_CH3 field. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH3_Msk = 0x8 + // Bit RX_REF_CNT_RST_CH3. + RMT_REF_CNT_RST_RX_REF_CNT_RST_CH3 = 0x8 + + // DATE: RMT version register + // Position of RMT_DATE field. + RMT_DATE_RMT_DATE_Pos = 0x0 + // Bit mask of RMT_DATE field. + RMT_DATE_RMT_DATE_Msk = 0xfffffff +) + +// Constants for RNG: Hardware Random Number Generator +const () + +// Constants for RSA: RSA (Rivest Shamir Adleman) Accelerator +const ( + // M_PRIME: Represents M’ + // Position of M_PRIME field. + RSA_M_PRIME_M_PRIME_Pos = 0x0 + // Bit mask of M_PRIME field. + RSA_M_PRIME_M_PRIME_Msk = 0xffffffff + + // MODE: Configures RSA length + // Position of MODE field. + RSA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + RSA_MODE_MODE_Msk = 0x7f + + // QUERY_CLEAN: RSA clean register + // Position of QUERY_CLEAN field. + RSA_QUERY_CLEAN_QUERY_CLEAN_Pos = 0x0 + // Bit mask of QUERY_CLEAN field. + RSA_QUERY_CLEAN_QUERY_CLEAN_Msk = 0x1 + // Bit QUERY_CLEAN. + RSA_QUERY_CLEAN_QUERY_CLEAN = 0x1 + + // SET_START_MODEXP: Starts modular exponentiation + // Position of SET_START_MODEXP field. + RSA_SET_START_MODEXP_SET_START_MODEXP_Pos = 0x0 + // Bit mask of SET_START_MODEXP field. + RSA_SET_START_MODEXP_SET_START_MODEXP_Msk = 0x1 + // Bit SET_START_MODEXP. + RSA_SET_START_MODEXP_SET_START_MODEXP = 0x1 + + // SET_START_MODMULT: Starts modular multiplication + // Position of SET_START_MODMULT field. + RSA_SET_START_MODMULT_SET_START_MODMULT_Pos = 0x0 + // Bit mask of SET_START_MODMULT field. + RSA_SET_START_MODMULT_SET_START_MODMULT_Msk = 0x1 + // Bit SET_START_MODMULT. + RSA_SET_START_MODMULT_SET_START_MODMULT = 0x1 + + // SET_START_MULT: Starts multiplication + // Position of SET_START_MULT field. + RSA_SET_START_MULT_SET_START_MULT_Pos = 0x0 + // Bit mask of SET_START_MULT field. + RSA_SET_START_MULT_SET_START_MULT_Msk = 0x1 + // Bit SET_START_MULT. + RSA_SET_START_MULT_SET_START_MULT = 0x1 + + // QUERY_IDLE: Represents the RSA status + // Position of QUERY_IDLE field. + RSA_QUERY_IDLE_QUERY_IDLE_Pos = 0x0 + // Bit mask of QUERY_IDLE field. + RSA_QUERY_IDLE_QUERY_IDLE_Msk = 0x1 + // Bit QUERY_IDLE. + RSA_QUERY_IDLE_QUERY_IDLE = 0x1 + + // INT_CLR: Clears RSA interrupt + // Position of CLEAR_INTERRUPT field. + RSA_INT_CLR_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + RSA_INT_CLR_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + RSA_INT_CLR_CLEAR_INTERRUPT = 0x1 + + // CONSTANT_TIME: Configures the constant_time option + // Position of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Pos = 0x0 + // Bit mask of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Msk = 0x1 + // Bit CONSTANT_TIME. + RSA_CONSTANT_TIME_CONSTANT_TIME = 0x1 + + // SEARCH_ENABLE: Configures the search option + // Position of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Pos = 0x0 + // Bit mask of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Msk = 0x1 + // Bit SEARCH_ENABLE. + RSA_SEARCH_ENABLE_SEARCH_ENABLE = 0x1 + + // SEARCH_POS: Configures the search position + // Position of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Pos = 0x0 + // Bit mask of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Msk = 0xfff + + // INT_ENA: Enables the RSA interrupt + // Position of INT_ENA field. + RSA_INT_ENA_INT_ENA_Pos = 0x0 + // Bit mask of INT_ENA field. + RSA_INT_ENA_INT_ENA_Msk = 0x1 + // Bit INT_ENA. + RSA_INT_ENA_INT_ENA = 0x1 + + // DATE: Version control register + // Position of DATE field. + RSA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RSA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for SHA: SHA (Secure Hash Algorithm) Accelerator +const ( + // MODE: Initial configuration register. + // Position of MODE field. + SHA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + SHA_MODE_MODE_Msk = 0x7 + + // T_STRING: SHA 512/t configuration register 0. + // Position of T_STRING field. + SHA_T_STRING_T_STRING_Pos = 0x0 + // Bit mask of T_STRING field. + SHA_T_STRING_T_STRING_Msk = 0xffffffff + + // T_LENGTH: SHA 512/t configuration register 1. + // Position of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Pos = 0x0 + // Bit mask of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Msk = 0x3f + + // DMA_BLOCK_NUM: DMA configuration register 0. + // Position of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Pos = 0x0 + // Bit mask of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Msk = 0x3f + + // START: Typical SHA configuration register 0. + // Position of START field. + SHA_START_START_Pos = 0x1 + // Bit mask of START field. + SHA_START_START_Msk = 0xfffffffe + + // CONTINUE: Typical SHA configuration register 1. + // Position of CONTINUE field. + SHA_CONTINUE_CONTINUE_Pos = 0x1 + // Bit mask of CONTINUE field. + SHA_CONTINUE_CONTINUE_Msk = 0xfffffffe + + // BUSY: Busy register. + // Position of STATE field. + SHA_BUSY_STATE_Pos = 0x0 + // Bit mask of STATE field. + SHA_BUSY_STATE_Msk = 0x1 + // Bit STATE. + SHA_BUSY_STATE = 0x1 + + // DMA_START: DMA configuration register 1. + // Position of DMA_START field. + SHA_DMA_START_DMA_START_Pos = 0x0 + // Bit mask of DMA_START field. + SHA_DMA_START_DMA_START_Msk = 0x1 + // Bit DMA_START. + SHA_DMA_START_DMA_START = 0x1 + + // DMA_CONTINUE: DMA configuration register 2. + // Position of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Pos = 0x0 + // Bit mask of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Msk = 0x1 + // Bit DMA_CONTINUE. + SHA_DMA_CONTINUE_DMA_CONTINUE = 0x1 + + // CLEAR_IRQ: Interrupt clear register. + // Position of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT = 0x1 + + // IRQ_ENA: Interrupt enable register. + // Position of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Pos = 0x0 + // Bit mask of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Msk = 0x1 + // Bit INTERRUPT_ENA. + SHA_IRQ_ENA_INTERRUPT_ENA = 0x1 + + // DATE: Date register. + // Position of DATE field. + SHA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SHA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for SOC_ETM: Event Task Matrix +const ( + // CH_ENA_AD0: channel enable register + // Position of CH_ENA0 field. + SOC_ETM_CH_ENA_AD0_CH_ENA0_Pos = 0x0 + // Bit mask of CH_ENA0 field. + SOC_ETM_CH_ENA_AD0_CH_ENA0_Msk = 0x1 + // Bit CH_ENA0. + SOC_ETM_CH_ENA_AD0_CH_ENA0 = 0x1 + // Position of CH_ENA1 field. + SOC_ETM_CH_ENA_AD0_CH_ENA1_Pos = 0x1 + // Bit mask of CH_ENA1 field. + SOC_ETM_CH_ENA_AD0_CH_ENA1_Msk = 0x2 + // Bit CH_ENA1. + SOC_ETM_CH_ENA_AD0_CH_ENA1 = 0x2 + // Position of CH_ENA2 field. + SOC_ETM_CH_ENA_AD0_CH_ENA2_Pos = 0x2 + // Bit mask of CH_ENA2 field. + SOC_ETM_CH_ENA_AD0_CH_ENA2_Msk = 0x4 + // Bit CH_ENA2. + SOC_ETM_CH_ENA_AD0_CH_ENA2 = 0x4 + // Position of CH_ENA3 field. + SOC_ETM_CH_ENA_AD0_CH_ENA3_Pos = 0x3 + // Bit mask of CH_ENA3 field. + SOC_ETM_CH_ENA_AD0_CH_ENA3_Msk = 0x8 + // Bit CH_ENA3. + SOC_ETM_CH_ENA_AD0_CH_ENA3 = 0x8 + // Position of CH_ENA4 field. + SOC_ETM_CH_ENA_AD0_CH_ENA4_Pos = 0x4 + // Bit mask of CH_ENA4 field. + SOC_ETM_CH_ENA_AD0_CH_ENA4_Msk = 0x10 + // Bit CH_ENA4. + SOC_ETM_CH_ENA_AD0_CH_ENA4 = 0x10 + // Position of CH_ENA5 field. + SOC_ETM_CH_ENA_AD0_CH_ENA5_Pos = 0x5 + // Bit mask of CH_ENA5 field. + SOC_ETM_CH_ENA_AD0_CH_ENA5_Msk = 0x20 + // Bit CH_ENA5. + SOC_ETM_CH_ENA_AD0_CH_ENA5 = 0x20 + // Position of CH_ENA6 field. + SOC_ETM_CH_ENA_AD0_CH_ENA6_Pos = 0x6 + // Bit mask of CH_ENA6 field. + SOC_ETM_CH_ENA_AD0_CH_ENA6_Msk = 0x40 + // Bit CH_ENA6. + SOC_ETM_CH_ENA_AD0_CH_ENA6 = 0x40 + // Position of CH_ENA7 field. + SOC_ETM_CH_ENA_AD0_CH_ENA7_Pos = 0x7 + // Bit mask of CH_ENA7 field. + SOC_ETM_CH_ENA_AD0_CH_ENA7_Msk = 0x80 + // Bit CH_ENA7. + SOC_ETM_CH_ENA_AD0_CH_ENA7 = 0x80 + // Position of CH_ENA8 field. + SOC_ETM_CH_ENA_AD0_CH_ENA8_Pos = 0x8 + // Bit mask of CH_ENA8 field. + SOC_ETM_CH_ENA_AD0_CH_ENA8_Msk = 0x100 + // Bit CH_ENA8. + SOC_ETM_CH_ENA_AD0_CH_ENA8 = 0x100 + // Position of CH_ENA9 field. + SOC_ETM_CH_ENA_AD0_CH_ENA9_Pos = 0x9 + // Bit mask of CH_ENA9 field. + SOC_ETM_CH_ENA_AD0_CH_ENA9_Msk = 0x200 + // Bit CH_ENA9. + SOC_ETM_CH_ENA_AD0_CH_ENA9 = 0x200 + // Position of CH_ENA10 field. + SOC_ETM_CH_ENA_AD0_CH_ENA10_Pos = 0xa + // Bit mask of CH_ENA10 field. + SOC_ETM_CH_ENA_AD0_CH_ENA10_Msk = 0x400 + // Bit CH_ENA10. + SOC_ETM_CH_ENA_AD0_CH_ENA10 = 0x400 + // Position of CH_ENA11 field. + SOC_ETM_CH_ENA_AD0_CH_ENA11_Pos = 0xb + // Bit mask of CH_ENA11 field. + SOC_ETM_CH_ENA_AD0_CH_ENA11_Msk = 0x800 + // Bit CH_ENA11. + SOC_ETM_CH_ENA_AD0_CH_ENA11 = 0x800 + // Position of CH_ENA12 field. + SOC_ETM_CH_ENA_AD0_CH_ENA12_Pos = 0xc + // Bit mask of CH_ENA12 field. + SOC_ETM_CH_ENA_AD0_CH_ENA12_Msk = 0x1000 + // Bit CH_ENA12. + SOC_ETM_CH_ENA_AD0_CH_ENA12 = 0x1000 + // Position of CH_ENA13 field. + SOC_ETM_CH_ENA_AD0_CH_ENA13_Pos = 0xd + // Bit mask of CH_ENA13 field. + SOC_ETM_CH_ENA_AD0_CH_ENA13_Msk = 0x2000 + // Bit CH_ENA13. + SOC_ETM_CH_ENA_AD0_CH_ENA13 = 0x2000 + // Position of CH_ENA14 field. + SOC_ETM_CH_ENA_AD0_CH_ENA14_Pos = 0xe + // Bit mask of CH_ENA14 field. + SOC_ETM_CH_ENA_AD0_CH_ENA14_Msk = 0x4000 + // Bit CH_ENA14. + SOC_ETM_CH_ENA_AD0_CH_ENA14 = 0x4000 + // Position of CH_ENA15 field. + SOC_ETM_CH_ENA_AD0_CH_ENA15_Pos = 0xf + // Bit mask of CH_ENA15 field. + SOC_ETM_CH_ENA_AD0_CH_ENA15_Msk = 0x8000 + // Bit CH_ENA15. + SOC_ETM_CH_ENA_AD0_CH_ENA15 = 0x8000 + // Position of CH_ENA16 field. + SOC_ETM_CH_ENA_AD0_CH_ENA16_Pos = 0x10 + // Bit mask of CH_ENA16 field. + SOC_ETM_CH_ENA_AD0_CH_ENA16_Msk = 0x10000 + // Bit CH_ENA16. + SOC_ETM_CH_ENA_AD0_CH_ENA16 = 0x10000 + // Position of CH_ENA17 field. + SOC_ETM_CH_ENA_AD0_CH_ENA17_Pos = 0x11 + // Bit mask of CH_ENA17 field. + SOC_ETM_CH_ENA_AD0_CH_ENA17_Msk = 0x20000 + // Bit CH_ENA17. + SOC_ETM_CH_ENA_AD0_CH_ENA17 = 0x20000 + // Position of CH_ENA18 field. + SOC_ETM_CH_ENA_AD0_CH_ENA18_Pos = 0x12 + // Bit mask of CH_ENA18 field. + SOC_ETM_CH_ENA_AD0_CH_ENA18_Msk = 0x40000 + // Bit CH_ENA18. + SOC_ETM_CH_ENA_AD0_CH_ENA18 = 0x40000 + // Position of CH_ENA19 field. + SOC_ETM_CH_ENA_AD0_CH_ENA19_Pos = 0x13 + // Bit mask of CH_ENA19 field. + SOC_ETM_CH_ENA_AD0_CH_ENA19_Msk = 0x80000 + // Bit CH_ENA19. + SOC_ETM_CH_ENA_AD0_CH_ENA19 = 0x80000 + // Position of CH_ENA20 field. + SOC_ETM_CH_ENA_AD0_CH_ENA20_Pos = 0x14 + // Bit mask of CH_ENA20 field. + SOC_ETM_CH_ENA_AD0_CH_ENA20_Msk = 0x100000 + // Bit CH_ENA20. + SOC_ETM_CH_ENA_AD0_CH_ENA20 = 0x100000 + // Position of CH_ENA21 field. + SOC_ETM_CH_ENA_AD0_CH_ENA21_Pos = 0x15 + // Bit mask of CH_ENA21 field. + SOC_ETM_CH_ENA_AD0_CH_ENA21_Msk = 0x200000 + // Bit CH_ENA21. + SOC_ETM_CH_ENA_AD0_CH_ENA21 = 0x200000 + // Position of CH_ENA22 field. + SOC_ETM_CH_ENA_AD0_CH_ENA22_Pos = 0x16 + // Bit mask of CH_ENA22 field. + SOC_ETM_CH_ENA_AD0_CH_ENA22_Msk = 0x400000 + // Bit CH_ENA22. + SOC_ETM_CH_ENA_AD0_CH_ENA22 = 0x400000 + // Position of CH_ENA23 field. + SOC_ETM_CH_ENA_AD0_CH_ENA23_Pos = 0x17 + // Bit mask of CH_ENA23 field. + SOC_ETM_CH_ENA_AD0_CH_ENA23_Msk = 0x800000 + // Bit CH_ENA23. + SOC_ETM_CH_ENA_AD0_CH_ENA23 = 0x800000 + // Position of CH_ENA24 field. + SOC_ETM_CH_ENA_AD0_CH_ENA24_Pos = 0x18 + // Bit mask of CH_ENA24 field. + SOC_ETM_CH_ENA_AD0_CH_ENA24_Msk = 0x1000000 + // Bit CH_ENA24. + SOC_ETM_CH_ENA_AD0_CH_ENA24 = 0x1000000 + // Position of CH_ENA25 field. + SOC_ETM_CH_ENA_AD0_CH_ENA25_Pos = 0x19 + // Bit mask of CH_ENA25 field. + SOC_ETM_CH_ENA_AD0_CH_ENA25_Msk = 0x2000000 + // Bit CH_ENA25. + SOC_ETM_CH_ENA_AD0_CH_ENA25 = 0x2000000 + // Position of CH_ENA26 field. + SOC_ETM_CH_ENA_AD0_CH_ENA26_Pos = 0x1a + // Bit mask of CH_ENA26 field. + SOC_ETM_CH_ENA_AD0_CH_ENA26_Msk = 0x4000000 + // Bit CH_ENA26. + SOC_ETM_CH_ENA_AD0_CH_ENA26 = 0x4000000 + // Position of CH_ENA27 field. + SOC_ETM_CH_ENA_AD0_CH_ENA27_Pos = 0x1b + // Bit mask of CH_ENA27 field. + SOC_ETM_CH_ENA_AD0_CH_ENA27_Msk = 0x8000000 + // Bit CH_ENA27. + SOC_ETM_CH_ENA_AD0_CH_ENA27 = 0x8000000 + // Position of CH_ENA28 field. + SOC_ETM_CH_ENA_AD0_CH_ENA28_Pos = 0x1c + // Bit mask of CH_ENA28 field. + SOC_ETM_CH_ENA_AD0_CH_ENA28_Msk = 0x10000000 + // Bit CH_ENA28. + SOC_ETM_CH_ENA_AD0_CH_ENA28 = 0x10000000 + // Position of CH_ENA29 field. + SOC_ETM_CH_ENA_AD0_CH_ENA29_Pos = 0x1d + // Bit mask of CH_ENA29 field. + SOC_ETM_CH_ENA_AD0_CH_ENA29_Msk = 0x20000000 + // Bit CH_ENA29. + SOC_ETM_CH_ENA_AD0_CH_ENA29 = 0x20000000 + // Position of CH_ENA30 field. + SOC_ETM_CH_ENA_AD0_CH_ENA30_Pos = 0x1e + // Bit mask of CH_ENA30 field. + SOC_ETM_CH_ENA_AD0_CH_ENA30_Msk = 0x40000000 + // Bit CH_ENA30. + SOC_ETM_CH_ENA_AD0_CH_ENA30 = 0x40000000 + // Position of CH_ENA31 field. + SOC_ETM_CH_ENA_AD0_CH_ENA31_Pos = 0x1f + // Bit mask of CH_ENA31 field. + SOC_ETM_CH_ENA_AD0_CH_ENA31_Msk = 0x80000000 + // Bit CH_ENA31. + SOC_ETM_CH_ENA_AD0_CH_ENA31 = 0x80000000 + + // CH_ENA_AD0_SET: channel enable set register + // Position of CH_SET0 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET0_Pos = 0x0 + // Bit mask of CH_SET0 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET0_Msk = 0x1 + // Bit CH_SET0. + SOC_ETM_CH_ENA_AD0_SET_CH_SET0 = 0x1 + // Position of CH_SET1 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET1_Pos = 0x1 + // Bit mask of CH_SET1 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET1_Msk = 0x2 + // Bit CH_SET1. + SOC_ETM_CH_ENA_AD0_SET_CH_SET1 = 0x2 + // Position of CH_SET2 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET2_Pos = 0x2 + // Bit mask of CH_SET2 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET2_Msk = 0x4 + // Bit CH_SET2. + SOC_ETM_CH_ENA_AD0_SET_CH_SET2 = 0x4 + // Position of CH_SET3 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET3_Pos = 0x3 + // Bit mask of CH_SET3 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET3_Msk = 0x8 + // Bit CH_SET3. + SOC_ETM_CH_ENA_AD0_SET_CH_SET3 = 0x8 + // Position of CH_SET4 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET4_Pos = 0x4 + // Bit mask of CH_SET4 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET4_Msk = 0x10 + // Bit CH_SET4. + SOC_ETM_CH_ENA_AD0_SET_CH_SET4 = 0x10 + // Position of CH_SET5 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET5_Pos = 0x5 + // Bit mask of CH_SET5 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET5_Msk = 0x20 + // Bit CH_SET5. + SOC_ETM_CH_ENA_AD0_SET_CH_SET5 = 0x20 + // Position of CH_SET6 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET6_Pos = 0x6 + // Bit mask of CH_SET6 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET6_Msk = 0x40 + // Bit CH_SET6. + SOC_ETM_CH_ENA_AD0_SET_CH_SET6 = 0x40 + // Position of CH_SET7 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET7_Pos = 0x7 + // Bit mask of CH_SET7 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET7_Msk = 0x80 + // Bit CH_SET7. + SOC_ETM_CH_ENA_AD0_SET_CH_SET7 = 0x80 + // Position of CH_SET8 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET8_Pos = 0x8 + // Bit mask of CH_SET8 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET8_Msk = 0x100 + // Bit CH_SET8. + SOC_ETM_CH_ENA_AD0_SET_CH_SET8 = 0x100 + // Position of CH_SET9 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET9_Pos = 0x9 + // Bit mask of CH_SET9 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET9_Msk = 0x200 + // Bit CH_SET9. + SOC_ETM_CH_ENA_AD0_SET_CH_SET9 = 0x200 + // Position of CH_SET10 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET10_Pos = 0xa + // Bit mask of CH_SET10 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET10_Msk = 0x400 + // Bit CH_SET10. + SOC_ETM_CH_ENA_AD0_SET_CH_SET10 = 0x400 + // Position of CH_SET11 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET11_Pos = 0xb + // Bit mask of CH_SET11 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET11_Msk = 0x800 + // Bit CH_SET11. + SOC_ETM_CH_ENA_AD0_SET_CH_SET11 = 0x800 + // Position of CH_SET12 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET12_Pos = 0xc + // Bit mask of CH_SET12 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET12_Msk = 0x1000 + // Bit CH_SET12. + SOC_ETM_CH_ENA_AD0_SET_CH_SET12 = 0x1000 + // Position of CH_SET13 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET13_Pos = 0xd + // Bit mask of CH_SET13 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET13_Msk = 0x2000 + // Bit CH_SET13. + SOC_ETM_CH_ENA_AD0_SET_CH_SET13 = 0x2000 + // Position of CH_SET14 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET14_Pos = 0xe + // Bit mask of CH_SET14 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET14_Msk = 0x4000 + // Bit CH_SET14. + SOC_ETM_CH_ENA_AD0_SET_CH_SET14 = 0x4000 + // Position of CH_SET15 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET15_Pos = 0xf + // Bit mask of CH_SET15 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET15_Msk = 0x8000 + // Bit CH_SET15. + SOC_ETM_CH_ENA_AD0_SET_CH_SET15 = 0x8000 + // Position of CH_SET16 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET16_Pos = 0x10 + // Bit mask of CH_SET16 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET16_Msk = 0x10000 + // Bit CH_SET16. + SOC_ETM_CH_ENA_AD0_SET_CH_SET16 = 0x10000 + // Position of CH_SET17 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET17_Pos = 0x11 + // Bit mask of CH_SET17 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET17_Msk = 0x20000 + // Bit CH_SET17. + SOC_ETM_CH_ENA_AD0_SET_CH_SET17 = 0x20000 + // Position of CH_SET18 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET18_Pos = 0x12 + // Bit mask of CH_SET18 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET18_Msk = 0x40000 + // Bit CH_SET18. + SOC_ETM_CH_ENA_AD0_SET_CH_SET18 = 0x40000 + // Position of CH_SET19 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET19_Pos = 0x13 + // Bit mask of CH_SET19 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET19_Msk = 0x80000 + // Bit CH_SET19. + SOC_ETM_CH_ENA_AD0_SET_CH_SET19 = 0x80000 + // Position of CH_SET20 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET20_Pos = 0x14 + // Bit mask of CH_SET20 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET20_Msk = 0x100000 + // Bit CH_SET20. + SOC_ETM_CH_ENA_AD0_SET_CH_SET20 = 0x100000 + // Position of CH_SET21 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET21_Pos = 0x15 + // Bit mask of CH_SET21 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET21_Msk = 0x200000 + // Bit CH_SET21. + SOC_ETM_CH_ENA_AD0_SET_CH_SET21 = 0x200000 + // Position of CH_SET22 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET22_Pos = 0x16 + // Bit mask of CH_SET22 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET22_Msk = 0x400000 + // Bit CH_SET22. + SOC_ETM_CH_ENA_AD0_SET_CH_SET22 = 0x400000 + // Position of CH_SET23 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET23_Pos = 0x17 + // Bit mask of CH_SET23 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET23_Msk = 0x800000 + // Bit CH_SET23. + SOC_ETM_CH_ENA_AD0_SET_CH_SET23 = 0x800000 + // Position of CH_SET24 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET24_Pos = 0x18 + // Bit mask of CH_SET24 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET24_Msk = 0x1000000 + // Bit CH_SET24. + SOC_ETM_CH_ENA_AD0_SET_CH_SET24 = 0x1000000 + // Position of CH_SET25 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET25_Pos = 0x19 + // Bit mask of CH_SET25 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET25_Msk = 0x2000000 + // Bit CH_SET25. + SOC_ETM_CH_ENA_AD0_SET_CH_SET25 = 0x2000000 + // Position of CH_SET26 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET26_Pos = 0x1a + // Bit mask of CH_SET26 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET26_Msk = 0x4000000 + // Bit CH_SET26. + SOC_ETM_CH_ENA_AD0_SET_CH_SET26 = 0x4000000 + // Position of CH_SET27 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET27_Pos = 0x1b + // Bit mask of CH_SET27 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET27_Msk = 0x8000000 + // Bit CH_SET27. + SOC_ETM_CH_ENA_AD0_SET_CH_SET27 = 0x8000000 + // Position of CH_SET28 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET28_Pos = 0x1c + // Bit mask of CH_SET28 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET28_Msk = 0x10000000 + // Bit CH_SET28. + SOC_ETM_CH_ENA_AD0_SET_CH_SET28 = 0x10000000 + // Position of CH_SET29 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET29_Pos = 0x1d + // Bit mask of CH_SET29 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET29_Msk = 0x20000000 + // Bit CH_SET29. + SOC_ETM_CH_ENA_AD0_SET_CH_SET29 = 0x20000000 + // Position of CH_SET30 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET30_Pos = 0x1e + // Bit mask of CH_SET30 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET30_Msk = 0x40000000 + // Bit CH_SET30. + SOC_ETM_CH_ENA_AD0_SET_CH_SET30 = 0x40000000 + // Position of CH_SET31 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET31_Pos = 0x1f + // Bit mask of CH_SET31 field. + SOC_ETM_CH_ENA_AD0_SET_CH_SET31_Msk = 0x80000000 + // Bit CH_SET31. + SOC_ETM_CH_ENA_AD0_SET_CH_SET31 = 0x80000000 + + // CH_ENA_AD0_CLR: channel enable clear register + // Position of CH_CLR0 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR0_Pos = 0x0 + // Bit mask of CH_CLR0 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR0_Msk = 0x1 + // Bit CH_CLR0. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR0 = 0x1 + // Position of CH_CLR1 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR1_Pos = 0x1 + // Bit mask of CH_CLR1 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR1_Msk = 0x2 + // Bit CH_CLR1. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR1 = 0x2 + // Position of CH_CLR2 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR2_Pos = 0x2 + // Bit mask of CH_CLR2 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR2_Msk = 0x4 + // Bit CH_CLR2. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR2 = 0x4 + // Position of CH_CLR3 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR3_Pos = 0x3 + // Bit mask of CH_CLR3 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR3_Msk = 0x8 + // Bit CH_CLR3. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR3 = 0x8 + // Position of CH_CLR4 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR4_Pos = 0x4 + // Bit mask of CH_CLR4 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR4_Msk = 0x10 + // Bit CH_CLR4. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR4 = 0x10 + // Position of CH_CLR5 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR5_Pos = 0x5 + // Bit mask of CH_CLR5 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR5_Msk = 0x20 + // Bit CH_CLR5. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR5 = 0x20 + // Position of CH_CLR6 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR6_Pos = 0x6 + // Bit mask of CH_CLR6 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR6_Msk = 0x40 + // Bit CH_CLR6. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR6 = 0x40 + // Position of CH_CLR7 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR7_Pos = 0x7 + // Bit mask of CH_CLR7 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR7_Msk = 0x80 + // Bit CH_CLR7. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR7 = 0x80 + // Position of CH_CLR8 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR8_Pos = 0x8 + // Bit mask of CH_CLR8 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR8_Msk = 0x100 + // Bit CH_CLR8. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR8 = 0x100 + // Position of CH_CLR9 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR9_Pos = 0x9 + // Bit mask of CH_CLR9 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR9_Msk = 0x200 + // Bit CH_CLR9. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR9 = 0x200 + // Position of CH_CLR10 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR10_Pos = 0xa + // Bit mask of CH_CLR10 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR10_Msk = 0x400 + // Bit CH_CLR10. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR10 = 0x400 + // Position of CH_CLR11 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR11_Pos = 0xb + // Bit mask of CH_CLR11 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR11_Msk = 0x800 + // Bit CH_CLR11. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR11 = 0x800 + // Position of CH_CLR12 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR12_Pos = 0xc + // Bit mask of CH_CLR12 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR12_Msk = 0x1000 + // Bit CH_CLR12. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR12 = 0x1000 + // Position of CH_CLR13 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR13_Pos = 0xd + // Bit mask of CH_CLR13 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR13_Msk = 0x2000 + // Bit CH_CLR13. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR13 = 0x2000 + // Position of CH_CLR14 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR14_Pos = 0xe + // Bit mask of CH_CLR14 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR14_Msk = 0x4000 + // Bit CH_CLR14. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR14 = 0x4000 + // Position of CH_CLR15 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR15_Pos = 0xf + // Bit mask of CH_CLR15 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR15_Msk = 0x8000 + // Bit CH_CLR15. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR15 = 0x8000 + // Position of CH_CLR16 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR16_Pos = 0x10 + // Bit mask of CH_CLR16 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR16_Msk = 0x10000 + // Bit CH_CLR16. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR16 = 0x10000 + // Position of CH_CLR17 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR17_Pos = 0x11 + // Bit mask of CH_CLR17 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR17_Msk = 0x20000 + // Bit CH_CLR17. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR17 = 0x20000 + // Position of CH_CLR18 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR18_Pos = 0x12 + // Bit mask of CH_CLR18 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR18_Msk = 0x40000 + // Bit CH_CLR18. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR18 = 0x40000 + // Position of CH_CLR19 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR19_Pos = 0x13 + // Bit mask of CH_CLR19 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR19_Msk = 0x80000 + // Bit CH_CLR19. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR19 = 0x80000 + // Position of CH_CLR20 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR20_Pos = 0x14 + // Bit mask of CH_CLR20 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR20_Msk = 0x100000 + // Bit CH_CLR20. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR20 = 0x100000 + // Position of CH_CLR21 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR21_Pos = 0x15 + // Bit mask of CH_CLR21 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR21_Msk = 0x200000 + // Bit CH_CLR21. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR21 = 0x200000 + // Position of CH_CLR22 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR22_Pos = 0x16 + // Bit mask of CH_CLR22 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR22_Msk = 0x400000 + // Bit CH_CLR22. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR22 = 0x400000 + // Position of CH_CLR23 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR23_Pos = 0x17 + // Bit mask of CH_CLR23 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR23_Msk = 0x800000 + // Bit CH_CLR23. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR23 = 0x800000 + // Position of CH_CLR24 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR24_Pos = 0x18 + // Bit mask of CH_CLR24 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR24_Msk = 0x1000000 + // Bit CH_CLR24. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR24 = 0x1000000 + // Position of CH_CLR25 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR25_Pos = 0x19 + // Bit mask of CH_CLR25 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR25_Msk = 0x2000000 + // Bit CH_CLR25. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR25 = 0x2000000 + // Position of CH_CLR26 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR26_Pos = 0x1a + // Bit mask of CH_CLR26 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR26_Msk = 0x4000000 + // Bit CH_CLR26. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR26 = 0x4000000 + // Position of CH_CLR27 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR27_Pos = 0x1b + // Bit mask of CH_CLR27 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR27_Msk = 0x8000000 + // Bit CH_CLR27. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR27 = 0x8000000 + // Position of CH_CLR28 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR28_Pos = 0x1c + // Bit mask of CH_CLR28 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR28_Msk = 0x10000000 + // Bit CH_CLR28. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR28 = 0x10000000 + // Position of CH_CLR29 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR29_Pos = 0x1d + // Bit mask of CH_CLR29 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR29_Msk = 0x20000000 + // Bit CH_CLR29. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR29 = 0x20000000 + // Position of CH_CLR30 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR30_Pos = 0x1e + // Bit mask of CH_CLR30 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR30_Msk = 0x40000000 + // Bit CH_CLR30. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR30 = 0x40000000 + // Position of CH_CLR31 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR31_Pos = 0x1f + // Bit mask of CH_CLR31 field. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR31_Msk = 0x80000000 + // Bit CH_CLR31. + SOC_ETM_CH_ENA_AD0_CLR_CH_CLR31 = 0x80000000 + + // CH_ENA_AD1: channel enable register + // Position of CH_ENA32 field. + SOC_ETM_CH_ENA_AD1_CH_ENA32_Pos = 0x0 + // Bit mask of CH_ENA32 field. + SOC_ETM_CH_ENA_AD1_CH_ENA32_Msk = 0x1 + // Bit CH_ENA32. + SOC_ETM_CH_ENA_AD1_CH_ENA32 = 0x1 + // Position of CH_ENA33 field. + SOC_ETM_CH_ENA_AD1_CH_ENA33_Pos = 0x1 + // Bit mask of CH_ENA33 field. + SOC_ETM_CH_ENA_AD1_CH_ENA33_Msk = 0x2 + // Bit CH_ENA33. + SOC_ETM_CH_ENA_AD1_CH_ENA33 = 0x2 + // Position of CH_ENA34 field. + SOC_ETM_CH_ENA_AD1_CH_ENA34_Pos = 0x2 + // Bit mask of CH_ENA34 field. + SOC_ETM_CH_ENA_AD1_CH_ENA34_Msk = 0x4 + // Bit CH_ENA34. + SOC_ETM_CH_ENA_AD1_CH_ENA34 = 0x4 + // Position of CH_ENA35 field. + SOC_ETM_CH_ENA_AD1_CH_ENA35_Pos = 0x3 + // Bit mask of CH_ENA35 field. + SOC_ETM_CH_ENA_AD1_CH_ENA35_Msk = 0x8 + // Bit CH_ENA35. + SOC_ETM_CH_ENA_AD1_CH_ENA35 = 0x8 + // Position of CH_ENA36 field. + SOC_ETM_CH_ENA_AD1_CH_ENA36_Pos = 0x4 + // Bit mask of CH_ENA36 field. + SOC_ETM_CH_ENA_AD1_CH_ENA36_Msk = 0x10 + // Bit CH_ENA36. + SOC_ETM_CH_ENA_AD1_CH_ENA36 = 0x10 + // Position of CH_ENA37 field. + SOC_ETM_CH_ENA_AD1_CH_ENA37_Pos = 0x5 + // Bit mask of CH_ENA37 field. + SOC_ETM_CH_ENA_AD1_CH_ENA37_Msk = 0x20 + // Bit CH_ENA37. + SOC_ETM_CH_ENA_AD1_CH_ENA37 = 0x20 + // Position of CH_ENA38 field. + SOC_ETM_CH_ENA_AD1_CH_ENA38_Pos = 0x6 + // Bit mask of CH_ENA38 field. + SOC_ETM_CH_ENA_AD1_CH_ENA38_Msk = 0x40 + // Bit CH_ENA38. + SOC_ETM_CH_ENA_AD1_CH_ENA38 = 0x40 + // Position of CH_ENA39 field. + SOC_ETM_CH_ENA_AD1_CH_ENA39_Pos = 0x7 + // Bit mask of CH_ENA39 field. + SOC_ETM_CH_ENA_AD1_CH_ENA39_Msk = 0x80 + // Bit CH_ENA39. + SOC_ETM_CH_ENA_AD1_CH_ENA39 = 0x80 + // Position of CH_ENA40 field. + SOC_ETM_CH_ENA_AD1_CH_ENA40_Pos = 0x8 + // Bit mask of CH_ENA40 field. + SOC_ETM_CH_ENA_AD1_CH_ENA40_Msk = 0x100 + // Bit CH_ENA40. + SOC_ETM_CH_ENA_AD1_CH_ENA40 = 0x100 + // Position of CH_ENA41 field. + SOC_ETM_CH_ENA_AD1_CH_ENA41_Pos = 0x9 + // Bit mask of CH_ENA41 field. + SOC_ETM_CH_ENA_AD1_CH_ENA41_Msk = 0x200 + // Bit CH_ENA41. + SOC_ETM_CH_ENA_AD1_CH_ENA41 = 0x200 + // Position of CH_ENA42 field. + SOC_ETM_CH_ENA_AD1_CH_ENA42_Pos = 0xa + // Bit mask of CH_ENA42 field. + SOC_ETM_CH_ENA_AD1_CH_ENA42_Msk = 0x400 + // Bit CH_ENA42. + SOC_ETM_CH_ENA_AD1_CH_ENA42 = 0x400 + // Position of CH_ENA43 field. + SOC_ETM_CH_ENA_AD1_CH_ENA43_Pos = 0xb + // Bit mask of CH_ENA43 field. + SOC_ETM_CH_ENA_AD1_CH_ENA43_Msk = 0x800 + // Bit CH_ENA43. + SOC_ETM_CH_ENA_AD1_CH_ENA43 = 0x800 + // Position of CH_ENA44 field. + SOC_ETM_CH_ENA_AD1_CH_ENA44_Pos = 0xc + // Bit mask of CH_ENA44 field. + SOC_ETM_CH_ENA_AD1_CH_ENA44_Msk = 0x1000 + // Bit CH_ENA44. + SOC_ETM_CH_ENA_AD1_CH_ENA44 = 0x1000 + // Position of CH_ENA45 field. + SOC_ETM_CH_ENA_AD1_CH_ENA45_Pos = 0xd + // Bit mask of CH_ENA45 field. + SOC_ETM_CH_ENA_AD1_CH_ENA45_Msk = 0x2000 + // Bit CH_ENA45. + SOC_ETM_CH_ENA_AD1_CH_ENA45 = 0x2000 + // Position of CH_ENA46 field. + SOC_ETM_CH_ENA_AD1_CH_ENA46_Pos = 0xe + // Bit mask of CH_ENA46 field. + SOC_ETM_CH_ENA_AD1_CH_ENA46_Msk = 0x4000 + // Bit CH_ENA46. + SOC_ETM_CH_ENA_AD1_CH_ENA46 = 0x4000 + // Position of CH_ENA47 field. + SOC_ETM_CH_ENA_AD1_CH_ENA47_Pos = 0xf + // Bit mask of CH_ENA47 field. + SOC_ETM_CH_ENA_AD1_CH_ENA47_Msk = 0x8000 + // Bit CH_ENA47. + SOC_ETM_CH_ENA_AD1_CH_ENA47 = 0x8000 + // Position of CH_ENA48 field. + SOC_ETM_CH_ENA_AD1_CH_ENA48_Pos = 0x10 + // Bit mask of CH_ENA48 field. + SOC_ETM_CH_ENA_AD1_CH_ENA48_Msk = 0x10000 + // Bit CH_ENA48. + SOC_ETM_CH_ENA_AD1_CH_ENA48 = 0x10000 + // Position of CH_ENA49 field. + SOC_ETM_CH_ENA_AD1_CH_ENA49_Pos = 0x11 + // Bit mask of CH_ENA49 field. + SOC_ETM_CH_ENA_AD1_CH_ENA49_Msk = 0x20000 + // Bit CH_ENA49. + SOC_ETM_CH_ENA_AD1_CH_ENA49 = 0x20000 + + // CH_ENA_AD1_SET: channel enable set register + // Position of CH_SET32 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET32_Pos = 0x0 + // Bit mask of CH_SET32 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET32_Msk = 0x1 + // Bit CH_SET32. + SOC_ETM_CH_ENA_AD1_SET_CH_SET32 = 0x1 + // Position of CH_SET33 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET33_Pos = 0x1 + // Bit mask of CH_SET33 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET33_Msk = 0x2 + // Bit CH_SET33. + SOC_ETM_CH_ENA_AD1_SET_CH_SET33 = 0x2 + // Position of CH_SET34 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET34_Pos = 0x2 + // Bit mask of CH_SET34 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET34_Msk = 0x4 + // Bit CH_SET34. + SOC_ETM_CH_ENA_AD1_SET_CH_SET34 = 0x4 + // Position of CH_SET35 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET35_Pos = 0x3 + // Bit mask of CH_SET35 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET35_Msk = 0x8 + // Bit CH_SET35. + SOC_ETM_CH_ENA_AD1_SET_CH_SET35 = 0x8 + // Position of CH_SET36 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET36_Pos = 0x4 + // Bit mask of CH_SET36 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET36_Msk = 0x10 + // Bit CH_SET36. + SOC_ETM_CH_ENA_AD1_SET_CH_SET36 = 0x10 + // Position of CH_SET37 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET37_Pos = 0x5 + // Bit mask of CH_SET37 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET37_Msk = 0x20 + // Bit CH_SET37. + SOC_ETM_CH_ENA_AD1_SET_CH_SET37 = 0x20 + // Position of CH_SET38 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET38_Pos = 0x6 + // Bit mask of CH_SET38 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET38_Msk = 0x40 + // Bit CH_SET38. + SOC_ETM_CH_ENA_AD1_SET_CH_SET38 = 0x40 + // Position of CH_SET39 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET39_Pos = 0x7 + // Bit mask of CH_SET39 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET39_Msk = 0x80 + // Bit CH_SET39. + SOC_ETM_CH_ENA_AD1_SET_CH_SET39 = 0x80 + // Position of CH_SET40 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET40_Pos = 0x8 + // Bit mask of CH_SET40 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET40_Msk = 0x100 + // Bit CH_SET40. + SOC_ETM_CH_ENA_AD1_SET_CH_SET40 = 0x100 + // Position of CH_SET41 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET41_Pos = 0x9 + // Bit mask of CH_SET41 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET41_Msk = 0x200 + // Bit CH_SET41. + SOC_ETM_CH_ENA_AD1_SET_CH_SET41 = 0x200 + // Position of CH_SET42 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET42_Pos = 0xa + // Bit mask of CH_SET42 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET42_Msk = 0x400 + // Bit CH_SET42. + SOC_ETM_CH_ENA_AD1_SET_CH_SET42 = 0x400 + // Position of CH_SET43 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET43_Pos = 0xb + // Bit mask of CH_SET43 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET43_Msk = 0x800 + // Bit CH_SET43. + SOC_ETM_CH_ENA_AD1_SET_CH_SET43 = 0x800 + // Position of CH_SET44 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET44_Pos = 0xc + // Bit mask of CH_SET44 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET44_Msk = 0x1000 + // Bit CH_SET44. + SOC_ETM_CH_ENA_AD1_SET_CH_SET44 = 0x1000 + // Position of CH_SET45 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET45_Pos = 0xd + // Bit mask of CH_SET45 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET45_Msk = 0x2000 + // Bit CH_SET45. + SOC_ETM_CH_ENA_AD1_SET_CH_SET45 = 0x2000 + // Position of CH_SET46 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET46_Pos = 0xe + // Bit mask of CH_SET46 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET46_Msk = 0x4000 + // Bit CH_SET46. + SOC_ETM_CH_ENA_AD1_SET_CH_SET46 = 0x4000 + // Position of CH_SET47 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET47_Pos = 0xf + // Bit mask of CH_SET47 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET47_Msk = 0x8000 + // Bit CH_SET47. + SOC_ETM_CH_ENA_AD1_SET_CH_SET47 = 0x8000 + // Position of CH_SET48 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET48_Pos = 0x10 + // Bit mask of CH_SET48 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET48_Msk = 0x10000 + // Bit CH_SET48. + SOC_ETM_CH_ENA_AD1_SET_CH_SET48 = 0x10000 + // Position of CH_SET49 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET49_Pos = 0x11 + // Bit mask of CH_SET49 field. + SOC_ETM_CH_ENA_AD1_SET_CH_SET49_Msk = 0x20000 + // Bit CH_SET49. + SOC_ETM_CH_ENA_AD1_SET_CH_SET49 = 0x20000 + + // CH_ENA_AD1_CLR: channel enable clear register + // Position of CH_CLR32 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR32_Pos = 0x0 + // Bit mask of CH_CLR32 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR32_Msk = 0x1 + // Bit CH_CLR32. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR32 = 0x1 + // Position of CH_CLR33 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR33_Pos = 0x1 + // Bit mask of CH_CLR33 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR33_Msk = 0x2 + // Bit CH_CLR33. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR33 = 0x2 + // Position of CH_CLR34 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR34_Pos = 0x2 + // Bit mask of CH_CLR34 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR34_Msk = 0x4 + // Bit CH_CLR34. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR34 = 0x4 + // Position of CH_CLR35 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR35_Pos = 0x3 + // Bit mask of CH_CLR35 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR35_Msk = 0x8 + // Bit CH_CLR35. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR35 = 0x8 + // Position of CH_CLR36 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR36_Pos = 0x4 + // Bit mask of CH_CLR36 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR36_Msk = 0x10 + // Bit CH_CLR36. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR36 = 0x10 + // Position of CH_CLR37 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR37_Pos = 0x5 + // Bit mask of CH_CLR37 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR37_Msk = 0x20 + // Bit CH_CLR37. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR37 = 0x20 + // Position of CH_CLR38 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR38_Pos = 0x6 + // Bit mask of CH_CLR38 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR38_Msk = 0x40 + // Bit CH_CLR38. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR38 = 0x40 + // Position of CH_CLR39 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR39_Pos = 0x7 + // Bit mask of CH_CLR39 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR39_Msk = 0x80 + // Bit CH_CLR39. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR39 = 0x80 + // Position of CH_CLR40 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR40_Pos = 0x8 + // Bit mask of CH_CLR40 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR40_Msk = 0x100 + // Bit CH_CLR40. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR40 = 0x100 + // Position of CH_CLR41 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR41_Pos = 0x9 + // Bit mask of CH_CLR41 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR41_Msk = 0x200 + // Bit CH_CLR41. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR41 = 0x200 + // Position of CH_CLR42 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR42_Pos = 0xa + // Bit mask of CH_CLR42 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR42_Msk = 0x400 + // Bit CH_CLR42. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR42 = 0x400 + // Position of CH_CLR43 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR43_Pos = 0xb + // Bit mask of CH_CLR43 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR43_Msk = 0x800 + // Bit CH_CLR43. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR43 = 0x800 + // Position of CH_CLR44 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR44_Pos = 0xc + // Bit mask of CH_CLR44 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR44_Msk = 0x1000 + // Bit CH_CLR44. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR44 = 0x1000 + // Position of CH_CLR45 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR45_Pos = 0xd + // Bit mask of CH_CLR45 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR45_Msk = 0x2000 + // Bit CH_CLR45. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR45 = 0x2000 + // Position of CH_CLR46 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR46_Pos = 0xe + // Bit mask of CH_CLR46 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR46_Msk = 0x4000 + // Bit CH_CLR46. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR46 = 0x4000 + // Position of CH_CLR47 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR47_Pos = 0xf + // Bit mask of CH_CLR47 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR47_Msk = 0x8000 + // Bit CH_CLR47. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR47 = 0x8000 + // Position of CH_CLR48 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR48_Pos = 0x10 + // Bit mask of CH_CLR48 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR48_Msk = 0x10000 + // Bit CH_CLR48. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR48 = 0x10000 + // Position of CH_CLR49 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR49_Pos = 0x11 + // Bit mask of CH_CLR49 field. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR49_Msk = 0x20000 + // Bit CH_CLR49. + SOC_ETM_CH_ENA_AD1_CLR_CH_CLR49 = 0x20000 + + // CH0_EVT_ID: channel0 event id register + // Position of CH0_EVT_ID field. + SOC_ETM_CH0_EVT_ID_CH0_EVT_ID_Pos = 0x0 + // Bit mask of CH0_EVT_ID field. + SOC_ETM_CH0_EVT_ID_CH0_EVT_ID_Msk = 0xff + + // CH0_TASK_ID: channel0 task id register + // Position of CH0_TASK_ID field. + SOC_ETM_CH0_TASK_ID_CH0_TASK_ID_Pos = 0x0 + // Bit mask of CH0_TASK_ID field. + SOC_ETM_CH0_TASK_ID_CH0_TASK_ID_Msk = 0xff + + // CH1_EVT_ID: channel1 event id register + // Position of CH1_EVT_ID field. + SOC_ETM_CH1_EVT_ID_CH1_EVT_ID_Pos = 0x0 + // Bit mask of CH1_EVT_ID field. + SOC_ETM_CH1_EVT_ID_CH1_EVT_ID_Msk = 0xff + + // CH1_TASK_ID: channel1 task id register + // Position of CH1_TASK_ID field. + SOC_ETM_CH1_TASK_ID_CH1_TASK_ID_Pos = 0x0 + // Bit mask of CH1_TASK_ID field. + SOC_ETM_CH1_TASK_ID_CH1_TASK_ID_Msk = 0xff + + // CH2_EVT_ID: channel2 event id register + // Position of CH2_EVT_ID field. + SOC_ETM_CH2_EVT_ID_CH2_EVT_ID_Pos = 0x0 + // Bit mask of CH2_EVT_ID field. + SOC_ETM_CH2_EVT_ID_CH2_EVT_ID_Msk = 0xff + + // CH2_TASK_ID: channel2 task id register + // Position of CH2_TASK_ID field. + SOC_ETM_CH2_TASK_ID_CH2_TASK_ID_Pos = 0x0 + // Bit mask of CH2_TASK_ID field. + SOC_ETM_CH2_TASK_ID_CH2_TASK_ID_Msk = 0xff + + // CH3_EVT_ID: channel3 event id register + // Position of CH3_EVT_ID field. + SOC_ETM_CH3_EVT_ID_CH3_EVT_ID_Pos = 0x0 + // Bit mask of CH3_EVT_ID field. + SOC_ETM_CH3_EVT_ID_CH3_EVT_ID_Msk = 0xff + + // CH3_TASK_ID: channel3 task id register + // Position of CH3_TASK_ID field. + SOC_ETM_CH3_TASK_ID_CH3_TASK_ID_Pos = 0x0 + // Bit mask of CH3_TASK_ID field. + SOC_ETM_CH3_TASK_ID_CH3_TASK_ID_Msk = 0xff + + // CH4_EVT_ID: channel4 event id register + // Position of CH4_EVT_ID field. + SOC_ETM_CH4_EVT_ID_CH4_EVT_ID_Pos = 0x0 + // Bit mask of CH4_EVT_ID field. + SOC_ETM_CH4_EVT_ID_CH4_EVT_ID_Msk = 0xff + + // CH4_TASK_ID: channel4 task id register + // Position of CH4_TASK_ID field. + SOC_ETM_CH4_TASK_ID_CH4_TASK_ID_Pos = 0x0 + // Bit mask of CH4_TASK_ID field. + SOC_ETM_CH4_TASK_ID_CH4_TASK_ID_Msk = 0xff + + // CH5_EVT_ID: channel5 event id register + // Position of CH5_EVT_ID field. + SOC_ETM_CH5_EVT_ID_CH5_EVT_ID_Pos = 0x0 + // Bit mask of CH5_EVT_ID field. + SOC_ETM_CH5_EVT_ID_CH5_EVT_ID_Msk = 0xff + + // CH5_TASK_ID: channel5 task id register + // Position of CH5_TASK_ID field. + SOC_ETM_CH5_TASK_ID_CH5_TASK_ID_Pos = 0x0 + // Bit mask of CH5_TASK_ID field. + SOC_ETM_CH5_TASK_ID_CH5_TASK_ID_Msk = 0xff + + // CH6_EVT_ID: channel6 event id register + // Position of CH6_EVT_ID field. + SOC_ETM_CH6_EVT_ID_CH6_EVT_ID_Pos = 0x0 + // Bit mask of CH6_EVT_ID field. + SOC_ETM_CH6_EVT_ID_CH6_EVT_ID_Msk = 0xff + + // CH6_TASK_ID: channel6 task id register + // Position of CH6_TASK_ID field. + SOC_ETM_CH6_TASK_ID_CH6_TASK_ID_Pos = 0x0 + // Bit mask of CH6_TASK_ID field. + SOC_ETM_CH6_TASK_ID_CH6_TASK_ID_Msk = 0xff + + // CH7_EVT_ID: channel7 event id register + // Position of CH7_EVT_ID field. + SOC_ETM_CH7_EVT_ID_CH7_EVT_ID_Pos = 0x0 + // Bit mask of CH7_EVT_ID field. + SOC_ETM_CH7_EVT_ID_CH7_EVT_ID_Msk = 0xff + + // CH7_TASK_ID: channel7 task id register + // Position of CH7_TASK_ID field. + SOC_ETM_CH7_TASK_ID_CH7_TASK_ID_Pos = 0x0 + // Bit mask of CH7_TASK_ID field. + SOC_ETM_CH7_TASK_ID_CH7_TASK_ID_Msk = 0xff + + // CH8_EVT_ID: channel8 event id register + // Position of CH8_EVT_ID field. + SOC_ETM_CH8_EVT_ID_CH8_EVT_ID_Pos = 0x0 + // Bit mask of CH8_EVT_ID field. + SOC_ETM_CH8_EVT_ID_CH8_EVT_ID_Msk = 0xff + + // CH8_TASK_ID: channel8 task id register + // Position of CH8_TASK_ID field. + SOC_ETM_CH8_TASK_ID_CH8_TASK_ID_Pos = 0x0 + // Bit mask of CH8_TASK_ID field. + SOC_ETM_CH8_TASK_ID_CH8_TASK_ID_Msk = 0xff + + // CH9_EVT_ID: channel9 event id register + // Position of CH9_EVT_ID field. + SOC_ETM_CH9_EVT_ID_CH9_EVT_ID_Pos = 0x0 + // Bit mask of CH9_EVT_ID field. + SOC_ETM_CH9_EVT_ID_CH9_EVT_ID_Msk = 0xff + + // CH9_TASK_ID: channel9 task id register + // Position of CH9_TASK_ID field. + SOC_ETM_CH9_TASK_ID_CH9_TASK_ID_Pos = 0x0 + // Bit mask of CH9_TASK_ID field. + SOC_ETM_CH9_TASK_ID_CH9_TASK_ID_Msk = 0xff + + // CH10_EVT_ID: channel10 event id register + // Position of CH10_EVT_ID field. + SOC_ETM_CH10_EVT_ID_CH10_EVT_ID_Pos = 0x0 + // Bit mask of CH10_EVT_ID field. + SOC_ETM_CH10_EVT_ID_CH10_EVT_ID_Msk = 0xff + + // CH10_TASK_ID: channel10 task id register + // Position of CH10_TASK_ID field. + SOC_ETM_CH10_TASK_ID_CH10_TASK_ID_Pos = 0x0 + // Bit mask of CH10_TASK_ID field. + SOC_ETM_CH10_TASK_ID_CH10_TASK_ID_Msk = 0xff + + // CH11_EVT_ID: channel11 event id register + // Position of CH11_EVT_ID field. + SOC_ETM_CH11_EVT_ID_CH11_EVT_ID_Pos = 0x0 + // Bit mask of CH11_EVT_ID field. + SOC_ETM_CH11_EVT_ID_CH11_EVT_ID_Msk = 0xff + + // CH11_TASK_ID: channel11 task id register + // Position of CH11_TASK_ID field. + SOC_ETM_CH11_TASK_ID_CH11_TASK_ID_Pos = 0x0 + // Bit mask of CH11_TASK_ID field. + SOC_ETM_CH11_TASK_ID_CH11_TASK_ID_Msk = 0xff + + // CH12_EVT_ID: channel12 event id register + // Position of CH12_EVT_ID field. + SOC_ETM_CH12_EVT_ID_CH12_EVT_ID_Pos = 0x0 + // Bit mask of CH12_EVT_ID field. + SOC_ETM_CH12_EVT_ID_CH12_EVT_ID_Msk = 0xff + + // CH12_TASK_ID: channel12 task id register + // Position of CH12_TASK_ID field. + SOC_ETM_CH12_TASK_ID_CH12_TASK_ID_Pos = 0x0 + // Bit mask of CH12_TASK_ID field. + SOC_ETM_CH12_TASK_ID_CH12_TASK_ID_Msk = 0xff + + // CH13_EVT_ID: channel13 event id register + // Position of CH13_EVT_ID field. + SOC_ETM_CH13_EVT_ID_CH13_EVT_ID_Pos = 0x0 + // Bit mask of CH13_EVT_ID field. + SOC_ETM_CH13_EVT_ID_CH13_EVT_ID_Msk = 0xff + + // CH13_TASK_ID: channel13 task id register + // Position of CH13_TASK_ID field. + SOC_ETM_CH13_TASK_ID_CH13_TASK_ID_Pos = 0x0 + // Bit mask of CH13_TASK_ID field. + SOC_ETM_CH13_TASK_ID_CH13_TASK_ID_Msk = 0xff + + // CH14_EVT_ID: channel14 event id register + // Position of CH14_EVT_ID field. + SOC_ETM_CH14_EVT_ID_CH14_EVT_ID_Pos = 0x0 + // Bit mask of CH14_EVT_ID field. + SOC_ETM_CH14_EVT_ID_CH14_EVT_ID_Msk = 0xff + + // CH14_TASK_ID: channel14 task id register + // Position of CH14_TASK_ID field. + SOC_ETM_CH14_TASK_ID_CH14_TASK_ID_Pos = 0x0 + // Bit mask of CH14_TASK_ID field. + SOC_ETM_CH14_TASK_ID_CH14_TASK_ID_Msk = 0xff + + // CH15_EVT_ID: channel15 event id register + // Position of CH15_EVT_ID field. + SOC_ETM_CH15_EVT_ID_CH15_EVT_ID_Pos = 0x0 + // Bit mask of CH15_EVT_ID field. + SOC_ETM_CH15_EVT_ID_CH15_EVT_ID_Msk = 0xff + + // CH15_TASK_ID: channel15 task id register + // Position of CH15_TASK_ID field. + SOC_ETM_CH15_TASK_ID_CH15_TASK_ID_Pos = 0x0 + // Bit mask of CH15_TASK_ID field. + SOC_ETM_CH15_TASK_ID_CH15_TASK_ID_Msk = 0xff + + // CH16_EVT_ID: channel16 event id register + // Position of CH16_EVT_ID field. + SOC_ETM_CH16_EVT_ID_CH16_EVT_ID_Pos = 0x0 + // Bit mask of CH16_EVT_ID field. + SOC_ETM_CH16_EVT_ID_CH16_EVT_ID_Msk = 0xff + + // CH16_TASK_ID: channel16 task id register + // Position of CH16_TASK_ID field. + SOC_ETM_CH16_TASK_ID_CH16_TASK_ID_Pos = 0x0 + // Bit mask of CH16_TASK_ID field. + SOC_ETM_CH16_TASK_ID_CH16_TASK_ID_Msk = 0xff + + // CH17_EVT_ID: channel17 event id register + // Position of CH17_EVT_ID field. + SOC_ETM_CH17_EVT_ID_CH17_EVT_ID_Pos = 0x0 + // Bit mask of CH17_EVT_ID field. + SOC_ETM_CH17_EVT_ID_CH17_EVT_ID_Msk = 0xff + + // CH17_TASK_ID: channel17 task id register + // Position of CH17_TASK_ID field. + SOC_ETM_CH17_TASK_ID_CH17_TASK_ID_Pos = 0x0 + // Bit mask of CH17_TASK_ID field. + SOC_ETM_CH17_TASK_ID_CH17_TASK_ID_Msk = 0xff + + // CH18_EVT_ID: channel18 event id register + // Position of CH18_EVT_ID field. + SOC_ETM_CH18_EVT_ID_CH18_EVT_ID_Pos = 0x0 + // Bit mask of CH18_EVT_ID field. + SOC_ETM_CH18_EVT_ID_CH18_EVT_ID_Msk = 0xff + + // CH18_TASK_ID: channel18 task id register + // Position of CH18_TASK_ID field. + SOC_ETM_CH18_TASK_ID_CH18_TASK_ID_Pos = 0x0 + // Bit mask of CH18_TASK_ID field. + SOC_ETM_CH18_TASK_ID_CH18_TASK_ID_Msk = 0xff + + // CH19_EVT_ID: channel19 event id register + // Position of CH19_EVT_ID field. + SOC_ETM_CH19_EVT_ID_CH19_EVT_ID_Pos = 0x0 + // Bit mask of CH19_EVT_ID field. + SOC_ETM_CH19_EVT_ID_CH19_EVT_ID_Msk = 0xff + + // CH19_TASK_ID: channel19 task id register + // Position of CH19_TASK_ID field. + SOC_ETM_CH19_TASK_ID_CH19_TASK_ID_Pos = 0x0 + // Bit mask of CH19_TASK_ID field. + SOC_ETM_CH19_TASK_ID_CH19_TASK_ID_Msk = 0xff + + // CH20_EVT_ID: channel20 event id register + // Position of CH20_EVT_ID field. + SOC_ETM_CH20_EVT_ID_CH20_EVT_ID_Pos = 0x0 + // Bit mask of CH20_EVT_ID field. + SOC_ETM_CH20_EVT_ID_CH20_EVT_ID_Msk = 0xff + + // CH20_TASK_ID: channel20 task id register + // Position of CH20_TASK_ID field. + SOC_ETM_CH20_TASK_ID_CH20_TASK_ID_Pos = 0x0 + // Bit mask of CH20_TASK_ID field. + SOC_ETM_CH20_TASK_ID_CH20_TASK_ID_Msk = 0xff + + // CH21_EVT_ID: channel21 event id register + // Position of CH21_EVT_ID field. + SOC_ETM_CH21_EVT_ID_CH21_EVT_ID_Pos = 0x0 + // Bit mask of CH21_EVT_ID field. + SOC_ETM_CH21_EVT_ID_CH21_EVT_ID_Msk = 0xff + + // CH21_TASK_ID: channel21 task id register + // Position of CH21_TASK_ID field. + SOC_ETM_CH21_TASK_ID_CH21_TASK_ID_Pos = 0x0 + // Bit mask of CH21_TASK_ID field. + SOC_ETM_CH21_TASK_ID_CH21_TASK_ID_Msk = 0xff + + // CH22_EVT_ID: channel22 event id register + // Position of CH22_EVT_ID field. + SOC_ETM_CH22_EVT_ID_CH22_EVT_ID_Pos = 0x0 + // Bit mask of CH22_EVT_ID field. + SOC_ETM_CH22_EVT_ID_CH22_EVT_ID_Msk = 0xff + + // CH22_TASK_ID: channel22 task id register + // Position of CH22_TASK_ID field. + SOC_ETM_CH22_TASK_ID_CH22_TASK_ID_Pos = 0x0 + // Bit mask of CH22_TASK_ID field. + SOC_ETM_CH22_TASK_ID_CH22_TASK_ID_Msk = 0xff + + // CH23_EVT_ID: channel23 event id register + // Position of CH23_EVT_ID field. + SOC_ETM_CH23_EVT_ID_CH23_EVT_ID_Pos = 0x0 + // Bit mask of CH23_EVT_ID field. + SOC_ETM_CH23_EVT_ID_CH23_EVT_ID_Msk = 0xff + + // CH23_TASK_ID: channel23 task id register + // Position of CH23_TASK_ID field. + SOC_ETM_CH23_TASK_ID_CH23_TASK_ID_Pos = 0x0 + // Bit mask of CH23_TASK_ID field. + SOC_ETM_CH23_TASK_ID_CH23_TASK_ID_Msk = 0xff + + // CH24_EVT_ID: channel24 event id register + // Position of CH24_EVT_ID field. + SOC_ETM_CH24_EVT_ID_CH24_EVT_ID_Pos = 0x0 + // Bit mask of CH24_EVT_ID field. + SOC_ETM_CH24_EVT_ID_CH24_EVT_ID_Msk = 0xff + + // CH24_TASK_ID: channel24 task id register + // Position of CH24_TASK_ID field. + SOC_ETM_CH24_TASK_ID_CH24_TASK_ID_Pos = 0x0 + // Bit mask of CH24_TASK_ID field. + SOC_ETM_CH24_TASK_ID_CH24_TASK_ID_Msk = 0xff + + // CH25_EVT_ID: channel25 event id register + // Position of CH25_EVT_ID field. + SOC_ETM_CH25_EVT_ID_CH25_EVT_ID_Pos = 0x0 + // Bit mask of CH25_EVT_ID field. + SOC_ETM_CH25_EVT_ID_CH25_EVT_ID_Msk = 0xff + + // CH25_TASK_ID: channel25 task id register + // Position of CH25_TASK_ID field. + SOC_ETM_CH25_TASK_ID_CH25_TASK_ID_Pos = 0x0 + // Bit mask of CH25_TASK_ID field. + SOC_ETM_CH25_TASK_ID_CH25_TASK_ID_Msk = 0xff + + // CH26_EVT_ID: channel26 event id register + // Position of CH26_EVT_ID field. + SOC_ETM_CH26_EVT_ID_CH26_EVT_ID_Pos = 0x0 + // Bit mask of CH26_EVT_ID field. + SOC_ETM_CH26_EVT_ID_CH26_EVT_ID_Msk = 0xff + + // CH26_TASK_ID: channel26 task id register + // Position of CH26_TASK_ID field. + SOC_ETM_CH26_TASK_ID_CH26_TASK_ID_Pos = 0x0 + // Bit mask of CH26_TASK_ID field. + SOC_ETM_CH26_TASK_ID_CH26_TASK_ID_Msk = 0xff + + // CH27_EVT_ID: channel27 event id register + // Position of CH27_EVT_ID field. + SOC_ETM_CH27_EVT_ID_CH27_EVT_ID_Pos = 0x0 + // Bit mask of CH27_EVT_ID field. + SOC_ETM_CH27_EVT_ID_CH27_EVT_ID_Msk = 0xff + + // CH27_TASK_ID: channel27 task id register + // Position of CH27_TASK_ID field. + SOC_ETM_CH27_TASK_ID_CH27_TASK_ID_Pos = 0x0 + // Bit mask of CH27_TASK_ID field. + SOC_ETM_CH27_TASK_ID_CH27_TASK_ID_Msk = 0xff + + // CH28_EVT_ID: channel28 event id register + // Position of CH28_EVT_ID field. + SOC_ETM_CH28_EVT_ID_CH28_EVT_ID_Pos = 0x0 + // Bit mask of CH28_EVT_ID field. + SOC_ETM_CH28_EVT_ID_CH28_EVT_ID_Msk = 0xff + + // CH28_TASK_ID: channel28 task id register + // Position of CH28_TASK_ID field. + SOC_ETM_CH28_TASK_ID_CH28_TASK_ID_Pos = 0x0 + // Bit mask of CH28_TASK_ID field. + SOC_ETM_CH28_TASK_ID_CH28_TASK_ID_Msk = 0xff + + // CH29_EVT_ID: channel29 event id register + // Position of CH29_EVT_ID field. + SOC_ETM_CH29_EVT_ID_CH29_EVT_ID_Pos = 0x0 + // Bit mask of CH29_EVT_ID field. + SOC_ETM_CH29_EVT_ID_CH29_EVT_ID_Msk = 0xff + + // CH29_TASK_ID: channel29 task id register + // Position of CH29_TASK_ID field. + SOC_ETM_CH29_TASK_ID_CH29_TASK_ID_Pos = 0x0 + // Bit mask of CH29_TASK_ID field. + SOC_ETM_CH29_TASK_ID_CH29_TASK_ID_Msk = 0xff + + // CH30_EVT_ID: channel30 event id register + // Position of CH30_EVT_ID field. + SOC_ETM_CH30_EVT_ID_CH30_EVT_ID_Pos = 0x0 + // Bit mask of CH30_EVT_ID field. + SOC_ETM_CH30_EVT_ID_CH30_EVT_ID_Msk = 0xff + + // CH30_TASK_ID: channel30 task id register + // Position of CH30_TASK_ID field. + SOC_ETM_CH30_TASK_ID_CH30_TASK_ID_Pos = 0x0 + // Bit mask of CH30_TASK_ID field. + SOC_ETM_CH30_TASK_ID_CH30_TASK_ID_Msk = 0xff + + // CH31_EVT_ID: channel31 event id register + // Position of CH31_EVT_ID field. + SOC_ETM_CH31_EVT_ID_CH31_EVT_ID_Pos = 0x0 + // Bit mask of CH31_EVT_ID field. + SOC_ETM_CH31_EVT_ID_CH31_EVT_ID_Msk = 0xff + + // CH31_TASK_ID: channel31 task id register + // Position of CH31_TASK_ID field. + SOC_ETM_CH31_TASK_ID_CH31_TASK_ID_Pos = 0x0 + // Bit mask of CH31_TASK_ID field. + SOC_ETM_CH31_TASK_ID_CH31_TASK_ID_Msk = 0xff + + // CH32_EVT_ID: channel32 event id register + // Position of CH32_EVT_ID field. + SOC_ETM_CH32_EVT_ID_CH32_EVT_ID_Pos = 0x0 + // Bit mask of CH32_EVT_ID field. + SOC_ETM_CH32_EVT_ID_CH32_EVT_ID_Msk = 0xff + + // CH32_TASK_ID: channel32 task id register + // Position of CH32_TASK_ID field. + SOC_ETM_CH32_TASK_ID_CH32_TASK_ID_Pos = 0x0 + // Bit mask of CH32_TASK_ID field. + SOC_ETM_CH32_TASK_ID_CH32_TASK_ID_Msk = 0xff + + // CH33_EVT_ID: channel33 event id register + // Position of CH33_EVT_ID field. + SOC_ETM_CH33_EVT_ID_CH33_EVT_ID_Pos = 0x0 + // Bit mask of CH33_EVT_ID field. + SOC_ETM_CH33_EVT_ID_CH33_EVT_ID_Msk = 0xff + + // CH33_TASK_ID: channel33 task id register + // Position of CH33_TASK_ID field. + SOC_ETM_CH33_TASK_ID_CH33_TASK_ID_Pos = 0x0 + // Bit mask of CH33_TASK_ID field. + SOC_ETM_CH33_TASK_ID_CH33_TASK_ID_Msk = 0xff + + // CH34_EVT_ID: channel34 event id register + // Position of CH34_EVT_ID field. + SOC_ETM_CH34_EVT_ID_CH34_EVT_ID_Pos = 0x0 + // Bit mask of CH34_EVT_ID field. + SOC_ETM_CH34_EVT_ID_CH34_EVT_ID_Msk = 0xff + + // CH34_TASK_ID: channel34 task id register + // Position of CH34_TASK_ID field. + SOC_ETM_CH34_TASK_ID_CH34_TASK_ID_Pos = 0x0 + // Bit mask of CH34_TASK_ID field. + SOC_ETM_CH34_TASK_ID_CH34_TASK_ID_Msk = 0xff + + // CH35_EVT_ID: channel35 event id register + // Position of CH35_EVT_ID field. + SOC_ETM_CH35_EVT_ID_CH35_EVT_ID_Pos = 0x0 + // Bit mask of CH35_EVT_ID field. + SOC_ETM_CH35_EVT_ID_CH35_EVT_ID_Msk = 0xff + + // CH35_TASK_ID: channel35 task id register + // Position of CH35_TASK_ID field. + SOC_ETM_CH35_TASK_ID_CH35_TASK_ID_Pos = 0x0 + // Bit mask of CH35_TASK_ID field. + SOC_ETM_CH35_TASK_ID_CH35_TASK_ID_Msk = 0xff + + // CH36_EVT_ID: channel36 event id register + // Position of CH36_EVT_ID field. + SOC_ETM_CH36_EVT_ID_CH36_EVT_ID_Pos = 0x0 + // Bit mask of CH36_EVT_ID field. + SOC_ETM_CH36_EVT_ID_CH36_EVT_ID_Msk = 0xff + + // CH36_TASK_ID: channel36 task id register + // Position of CH36_TASK_ID field. + SOC_ETM_CH36_TASK_ID_CH36_TASK_ID_Pos = 0x0 + // Bit mask of CH36_TASK_ID field. + SOC_ETM_CH36_TASK_ID_CH36_TASK_ID_Msk = 0xff + + // CH37_EVT_ID: channel37 event id register + // Position of CH37_EVT_ID field. + SOC_ETM_CH37_EVT_ID_CH37_EVT_ID_Pos = 0x0 + // Bit mask of CH37_EVT_ID field. + SOC_ETM_CH37_EVT_ID_CH37_EVT_ID_Msk = 0xff + + // CH37_TASK_ID: channel37 task id register + // Position of CH37_TASK_ID field. + SOC_ETM_CH37_TASK_ID_CH37_TASK_ID_Pos = 0x0 + // Bit mask of CH37_TASK_ID field. + SOC_ETM_CH37_TASK_ID_CH37_TASK_ID_Msk = 0xff + + // CH38_EVT_ID: channel38 event id register + // Position of CH38_EVT_ID field. + SOC_ETM_CH38_EVT_ID_CH38_EVT_ID_Pos = 0x0 + // Bit mask of CH38_EVT_ID field. + SOC_ETM_CH38_EVT_ID_CH38_EVT_ID_Msk = 0xff + + // CH38_TASK_ID: channel38 task id register + // Position of CH38_TASK_ID field. + SOC_ETM_CH38_TASK_ID_CH38_TASK_ID_Pos = 0x0 + // Bit mask of CH38_TASK_ID field. + SOC_ETM_CH38_TASK_ID_CH38_TASK_ID_Msk = 0xff + + // CH39_EVT_ID: channel39 event id register + // Position of CH39_EVT_ID field. + SOC_ETM_CH39_EVT_ID_CH39_EVT_ID_Pos = 0x0 + // Bit mask of CH39_EVT_ID field. + SOC_ETM_CH39_EVT_ID_CH39_EVT_ID_Msk = 0xff + + // CH39_TASK_ID: channel39 task id register + // Position of CH39_TASK_ID field. + SOC_ETM_CH39_TASK_ID_CH39_TASK_ID_Pos = 0x0 + // Bit mask of CH39_TASK_ID field. + SOC_ETM_CH39_TASK_ID_CH39_TASK_ID_Msk = 0xff + + // CH40_EVT_ID: channel40 event id register + // Position of CH40_EVT_ID field. + SOC_ETM_CH40_EVT_ID_CH40_EVT_ID_Pos = 0x0 + // Bit mask of CH40_EVT_ID field. + SOC_ETM_CH40_EVT_ID_CH40_EVT_ID_Msk = 0xff + + // CH40_TASK_ID: channel40 task id register + // Position of CH40_TASK_ID field. + SOC_ETM_CH40_TASK_ID_CH40_TASK_ID_Pos = 0x0 + // Bit mask of CH40_TASK_ID field. + SOC_ETM_CH40_TASK_ID_CH40_TASK_ID_Msk = 0xff + + // CH41_EVT_ID: channel41 event id register + // Position of CH41_EVT_ID field. + SOC_ETM_CH41_EVT_ID_CH41_EVT_ID_Pos = 0x0 + // Bit mask of CH41_EVT_ID field. + SOC_ETM_CH41_EVT_ID_CH41_EVT_ID_Msk = 0xff + + // CH41_TASK_ID: channel41 task id register + // Position of CH41_TASK_ID field. + SOC_ETM_CH41_TASK_ID_CH41_TASK_ID_Pos = 0x0 + // Bit mask of CH41_TASK_ID field. + SOC_ETM_CH41_TASK_ID_CH41_TASK_ID_Msk = 0xff + + // CH42_EVT_ID: channel42 event id register + // Position of CH42_EVT_ID field. + SOC_ETM_CH42_EVT_ID_CH42_EVT_ID_Pos = 0x0 + // Bit mask of CH42_EVT_ID field. + SOC_ETM_CH42_EVT_ID_CH42_EVT_ID_Msk = 0xff + + // CH42_TASK_ID: channel42 task id register + // Position of CH42_TASK_ID field. + SOC_ETM_CH42_TASK_ID_CH42_TASK_ID_Pos = 0x0 + // Bit mask of CH42_TASK_ID field. + SOC_ETM_CH42_TASK_ID_CH42_TASK_ID_Msk = 0xff + + // CH43_EVT_ID: channel43 event id register + // Position of CH43_EVT_ID field. + SOC_ETM_CH43_EVT_ID_CH43_EVT_ID_Pos = 0x0 + // Bit mask of CH43_EVT_ID field. + SOC_ETM_CH43_EVT_ID_CH43_EVT_ID_Msk = 0xff + + // CH43_TASK_ID: channel43 task id register + // Position of CH43_TASK_ID field. + SOC_ETM_CH43_TASK_ID_CH43_TASK_ID_Pos = 0x0 + // Bit mask of CH43_TASK_ID field. + SOC_ETM_CH43_TASK_ID_CH43_TASK_ID_Msk = 0xff + + // CH44_EVT_ID: channel44 event id register + // Position of CH44_EVT_ID field. + SOC_ETM_CH44_EVT_ID_CH44_EVT_ID_Pos = 0x0 + // Bit mask of CH44_EVT_ID field. + SOC_ETM_CH44_EVT_ID_CH44_EVT_ID_Msk = 0xff + + // CH44_TASK_ID: channel44 task id register + // Position of CH44_TASK_ID field. + SOC_ETM_CH44_TASK_ID_CH44_TASK_ID_Pos = 0x0 + // Bit mask of CH44_TASK_ID field. + SOC_ETM_CH44_TASK_ID_CH44_TASK_ID_Msk = 0xff + + // CH45_EVT_ID: channel45 event id register + // Position of CH45_EVT_ID field. + SOC_ETM_CH45_EVT_ID_CH45_EVT_ID_Pos = 0x0 + // Bit mask of CH45_EVT_ID field. + SOC_ETM_CH45_EVT_ID_CH45_EVT_ID_Msk = 0xff + + // CH45_TASK_ID: channel45 task id register + // Position of CH45_TASK_ID field. + SOC_ETM_CH45_TASK_ID_CH45_TASK_ID_Pos = 0x0 + // Bit mask of CH45_TASK_ID field. + SOC_ETM_CH45_TASK_ID_CH45_TASK_ID_Msk = 0xff + + // CH46_EVT_ID: channel46 event id register + // Position of CH46_EVT_ID field. + SOC_ETM_CH46_EVT_ID_CH46_EVT_ID_Pos = 0x0 + // Bit mask of CH46_EVT_ID field. + SOC_ETM_CH46_EVT_ID_CH46_EVT_ID_Msk = 0xff + + // CH46_TASK_ID: channel46 task id register + // Position of CH46_TASK_ID field. + SOC_ETM_CH46_TASK_ID_CH46_TASK_ID_Pos = 0x0 + // Bit mask of CH46_TASK_ID field. + SOC_ETM_CH46_TASK_ID_CH46_TASK_ID_Msk = 0xff + + // CH47_EVT_ID: channel47 event id register + // Position of CH47_EVT_ID field. + SOC_ETM_CH47_EVT_ID_CH47_EVT_ID_Pos = 0x0 + // Bit mask of CH47_EVT_ID field. + SOC_ETM_CH47_EVT_ID_CH47_EVT_ID_Msk = 0xff + + // CH47_TASK_ID: channel47 task id register + // Position of CH47_TASK_ID field. + SOC_ETM_CH47_TASK_ID_CH47_TASK_ID_Pos = 0x0 + // Bit mask of CH47_TASK_ID field. + SOC_ETM_CH47_TASK_ID_CH47_TASK_ID_Msk = 0xff + + // CH48_EVT_ID: channel48 event id register + // Position of CH48_EVT_ID field. + SOC_ETM_CH48_EVT_ID_CH48_EVT_ID_Pos = 0x0 + // Bit mask of CH48_EVT_ID field. + SOC_ETM_CH48_EVT_ID_CH48_EVT_ID_Msk = 0xff + + // CH48_TASK_ID: channel48 task id register + // Position of CH48_TASK_ID field. + SOC_ETM_CH48_TASK_ID_CH48_TASK_ID_Pos = 0x0 + // Bit mask of CH48_TASK_ID field. + SOC_ETM_CH48_TASK_ID_CH48_TASK_ID_Msk = 0xff + + // CH49_EVT_ID: channel49 event id register + // Position of CH49_EVT_ID field. + SOC_ETM_CH49_EVT_ID_CH49_EVT_ID_Pos = 0x0 + // Bit mask of CH49_EVT_ID field. + SOC_ETM_CH49_EVT_ID_CH49_EVT_ID_Msk = 0xff + + // CH49_TASK_ID: channel49 task id register + // Position of CH49_TASK_ID field. + SOC_ETM_CH49_TASK_ID_CH49_TASK_ID_Pos = 0x0 + // Bit mask of CH49_TASK_ID field. + SOC_ETM_CH49_TASK_ID_CH49_TASK_ID_Msk = 0xff + + // CLK_EN: etm clock enable register + // Position of CLK_EN field. + SOC_ETM_CLK_EN_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SOC_ETM_CLK_EN_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SOC_ETM_CLK_EN_CLK_EN = 0x1 + + // DATE: etm date register + // Position of DATE field. + SOC_ETM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SOC_ETM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SPI0: SPI (Serial Peripheral Interface) Controller 0 +const ( + // SPI_MEM_CMD: SPI0 FSM status register + // Position of SPI_MEM_MST_ST field. + SPI0_SPI_MEM_CMD_SPI_MEM_MST_ST_Pos = 0x0 + // Bit mask of SPI_MEM_MST_ST field. + SPI0_SPI_MEM_CMD_SPI_MEM_MST_ST_Msk = 0xf + // Position of SPI_MEM_SLV_ST field. + SPI0_SPI_MEM_CMD_SPI_MEM_SLV_ST_Pos = 0x4 + // Bit mask of SPI_MEM_SLV_ST field. + SPI0_SPI_MEM_CMD_SPI_MEM_SLV_ST_Msk = 0xf0 + // Position of SPI_MEM_USR field. + SPI0_SPI_MEM_CMD_SPI_MEM_USR_Pos = 0x12 + // Bit mask of SPI_MEM_USR field. + SPI0_SPI_MEM_CMD_SPI_MEM_USR_Msk = 0x40000 + // Bit SPI_MEM_USR. + SPI0_SPI_MEM_CMD_SPI_MEM_USR = 0x40000 + + // SPI_MEM_CTRL: SPI0 control register. + // Position of SPI_MEM_WDUMMY_DQS_ALWAYS_OUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_Pos = 0x0 + // Bit mask of SPI_MEM_WDUMMY_DQS_ALWAYS_OUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_Msk = 0x1 + // Bit SPI_MEM_WDUMMY_DQS_ALWAYS_OUT. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT = 0x1 + // Position of SPI_MEM_WDUMMY_ALWAYS_OUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT_Pos = 0x1 + // Bit mask of SPI_MEM_WDUMMY_ALWAYS_OUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT_Msk = 0x2 + // Bit SPI_MEM_WDUMMY_ALWAYS_OUT. + SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT = 0x2 + // Position of SPI_MEM_FDUMMY_RIN field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Pos = 0x2 + // Bit mask of SPI_MEM_FDUMMY_RIN field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Msk = 0x4 + // Bit SPI_MEM_FDUMMY_RIN. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN = 0x4 + // Position of SPI_MEM_FDUMMY_WOUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Pos = 0x3 + // Bit mask of SPI_MEM_FDUMMY_WOUT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Msk = 0x8 + // Bit SPI_MEM_FDUMMY_WOUT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT = 0x8 + // Position of SPI_MEM_FDOUT_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Pos = 0x4 + // Bit mask of SPI_MEM_FDOUT_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Msk = 0x10 + // Bit SPI_MEM_FDOUT_OCT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT = 0x10 + // Position of SPI_MEM_FDIN_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Pos = 0x5 + // Bit mask of SPI_MEM_FDIN_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Msk = 0x20 + // Bit SPI_MEM_FDIN_OCT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT = 0x20 + // Position of SPI_MEM_FADDR_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Pos = 0x6 + // Bit mask of SPI_MEM_FADDR_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Msk = 0x40 + // Bit SPI_MEM_FADDR_OCT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT = 0x40 + // Position of SPI_MEM_FCMD_QUAD field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Pos = 0x8 + // Bit mask of SPI_MEM_FCMD_QUAD field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Msk = 0x100 + // Bit SPI_MEM_FCMD_QUAD. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD = 0x100 + // Position of SPI_MEM_FCMD_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Pos = 0x9 + // Bit mask of SPI_MEM_FCMD_OCT field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Msk = 0x200 + // Bit SPI_MEM_FCMD_OCT. + SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT = 0x200 + // Position of SPI_MEM_FASTRD_MODE field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Pos = 0xd + // Bit mask of SPI_MEM_FASTRD_MODE field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Msk = 0x2000 + // Bit SPI_MEM_FASTRD_MODE. + SPI0_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE = 0x2000 + // Position of SPI_MEM_FREAD_DUAL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Pos = 0xe + // Bit mask of SPI_MEM_FREAD_DUAL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Msk = 0x4000 + // Bit SPI_MEM_FREAD_DUAL. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL = 0x4000 + // Position of SPI_MEM_Q_POL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_Q_POL_Pos = 0x12 + // Bit mask of SPI_MEM_Q_POL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_Q_POL_Msk = 0x40000 + // Bit SPI_MEM_Q_POL. + SPI0_SPI_MEM_CTRL_SPI_MEM_Q_POL = 0x40000 + // Position of SPI_MEM_D_POL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_D_POL_Pos = 0x13 + // Bit mask of SPI_MEM_D_POL field. + SPI0_SPI_MEM_CTRL_SPI_MEM_D_POL_Msk = 0x80000 + // Bit SPI_MEM_D_POL. + SPI0_SPI_MEM_CTRL_SPI_MEM_D_POL = 0x80000 + // Position of SPI_MEM_FREAD_QUAD field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Pos = 0x14 + // Bit mask of SPI_MEM_FREAD_QUAD field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Msk = 0x100000 + // Bit SPI_MEM_FREAD_QUAD. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD = 0x100000 + // Position of SPI_MEM_WP field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WP_Pos = 0x15 + // Bit mask of SPI_MEM_WP field. + SPI0_SPI_MEM_CTRL_SPI_MEM_WP_Msk = 0x200000 + // Bit SPI_MEM_WP. + SPI0_SPI_MEM_CTRL_SPI_MEM_WP = 0x200000 + // Position of SPI_MEM_FREAD_DIO field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Pos = 0x17 + // Bit mask of SPI_MEM_FREAD_DIO field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Msk = 0x800000 + // Bit SPI_MEM_FREAD_DIO. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO = 0x800000 + // Position of SPI_MEM_FREAD_QIO field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Pos = 0x18 + // Bit mask of SPI_MEM_FREAD_QIO field. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Msk = 0x1000000 + // Bit SPI_MEM_FREAD_QIO. + SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO = 0x1000000 + // Position of SPI_MEM_DQS_IE_ALWAYS_ON field. + SPI0_SPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON_Pos = 0x1e + // Bit mask of SPI_MEM_DQS_IE_ALWAYS_ON field. + SPI0_SPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON_Msk = 0x40000000 + // Bit SPI_MEM_DQS_IE_ALWAYS_ON. + SPI0_SPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON = 0x40000000 + // Position of SPI_MEM_DATA_IE_ALWAYS_ON field. + SPI0_SPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON_Pos = 0x1f + // Bit mask of SPI_MEM_DATA_IE_ALWAYS_ON field. + SPI0_SPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON_Msk = 0x80000000 + // Bit SPI_MEM_DATA_IE_ALWAYS_ON. + SPI0_SPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON = 0x80000000 + + // SPI_MEM_CTRL1: SPI0 control1 register. + // Position of SPI_MEM_CLK_MODE field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_CLK_MODE field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Msk = 0x3 + // Position of SPI_AR_SIZE0_1_SUPPORT_EN field. + SPI0_SPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN_Pos = 0x15 + // Bit mask of SPI_AR_SIZE0_1_SUPPORT_EN field. + SPI0_SPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN_Msk = 0x200000 + // Bit SPI_AR_SIZE0_1_SUPPORT_EN. + SPI0_SPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN = 0x200000 + // Position of SPI_AW_SIZE0_1_SUPPORT_EN field. + SPI0_SPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN_Pos = 0x16 + // Bit mask of SPI_AW_SIZE0_1_SUPPORT_EN field. + SPI0_SPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN_Msk = 0x400000 + // Bit SPI_AW_SIZE0_1_SUPPORT_EN. + SPI0_SPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN = 0x400000 + // Position of SPI_AXI_RDATA_BACK_FAST field. + SPI0_SPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST_Pos = 0x17 + // Bit mask of SPI_AXI_RDATA_BACK_FAST field. + SPI0_SPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST_Msk = 0x800000 + // Bit SPI_AXI_RDATA_BACK_FAST. + SPI0_SPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST = 0x800000 + // Position of SPI_MEM_RRESP_ECC_ERR_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN_Pos = 0x18 + // Bit mask of SPI_MEM_RRESP_ECC_ERR_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN_Msk = 0x1000000 + // Bit SPI_MEM_RRESP_ECC_ERR_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN = 0x1000000 + // Position of SPI_MEM_AR_SPLICE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN_Pos = 0x19 + // Bit mask of SPI_MEM_AR_SPLICE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN_Msk = 0x2000000 + // Bit SPI_MEM_AR_SPLICE_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN = 0x2000000 + // Position of SPI_MEM_AW_SPLICE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN_Pos = 0x1a + // Bit mask of SPI_MEM_AW_SPLICE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN_Msk = 0x4000000 + // Bit SPI_MEM_AW_SPLICE_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN = 0x4000000 + // Position of SPI_MEM_RAM0_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RAM0_EN_Pos = 0x1b + // Bit mask of SPI_MEM_RAM0_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RAM0_EN_Msk = 0x8000000 + // Bit SPI_MEM_RAM0_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RAM0_EN = 0x8000000 + // Position of SPI_MEM_DUAL_RAM_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN_Pos = 0x1c + // Bit mask of SPI_MEM_DUAL_RAM_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN_Msk = 0x10000000 + // Bit SPI_MEM_DUAL_RAM_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN = 0x10000000 + // Position of SPI_MEM_FAST_WRITE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN_Pos = 0x1d + // Bit mask of SPI_MEM_FAST_WRITE_EN field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN_Msk = 0x20000000 + // Bit SPI_MEM_FAST_WRITE_EN. + SPI0_SPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN = 0x20000000 + // Position of SPI_MEM_RXFIFO_RST field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST_Pos = 0x1e + // Bit mask of SPI_MEM_RXFIFO_RST field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST_Msk = 0x40000000 + // Bit SPI_MEM_RXFIFO_RST. + SPI0_SPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST = 0x40000000 + // Position of SPI_MEM_TXFIFO_RST field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST_Pos = 0x1f + // Bit mask of SPI_MEM_TXFIFO_RST field. + SPI0_SPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST_Msk = 0x80000000 + // Bit SPI_MEM_TXFIFO_RST. + SPI0_SPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST = 0x80000000 + + // SPI_MEM_CTRL2: SPI0 control2 register. + // Position of SPI_MEM_CS_SETUP_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME_Pos = 0x0 + // Bit mask of SPI_MEM_CS_SETUP_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME_Msk = 0x1f + // Position of SPI_MEM_CS_HOLD_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME_Pos = 0x5 + // Bit mask of SPI_MEM_CS_HOLD_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME_Msk = 0x3e0 + // Position of SPI_MEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME_Pos = 0xa + // Bit mask of SPI_MEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME_Msk = 0x1c00 + // Position of SPI_MEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER_Pos = 0xd + // Bit mask of SPI_MEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER_Msk = 0x2000 + // Bit SPI_MEM_ECC_SKIP_PAGE_CORNER. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER = 0x2000 + // Position of SPI_MEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN_Pos = 0xe + // Bit mask of SPI_MEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN_Msk = 0x4000 + // Bit SPI_MEM_ECC_16TO18_BYTE_EN. + SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN = 0x4000 + // Position of SPI_MEM_SPLIT_TRANS_EN field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN_Pos = 0x18 + // Bit mask of SPI_MEM_SPLIT_TRANS_EN field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN_Msk = 0x1000000 + // Bit SPI_MEM_SPLIT_TRANS_EN. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN = 0x1000000 + // Position of SPI_MEM_CS_HOLD_DELAY field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY_Pos = 0x19 + // Bit mask of SPI_MEM_CS_HOLD_DELAY field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY_Msk = 0x7e000000 + // Position of SPI_MEM_SYNC_RESET field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Pos = 0x1f + // Bit mask of SPI_MEM_SYNC_RESET field. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Msk = 0x80000000 + // Bit SPI_MEM_SYNC_RESET. + SPI0_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET = 0x80000000 + + // SPI_MEM_CLOCK: SPI clock division control register. + // Position of SPI_MEM_CLKCNT_L field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Pos = 0x0 + // Bit mask of SPI_MEM_CLKCNT_L field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Msk = 0xff + // Position of SPI_MEM_CLKCNT_H field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Pos = 0x8 + // Bit mask of SPI_MEM_CLKCNT_H field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Msk = 0xff00 + // Position of SPI_MEM_CLKCNT_N field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Pos = 0x10 + // Bit mask of SPI_MEM_CLKCNT_N field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Msk = 0xff0000 + // Position of SPI_MEM_CLK_EQU_SYSCLK field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of SPI_MEM_CLK_EQU_SYSCLK field. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit SPI_MEM_CLK_EQU_SYSCLK. + SPI0_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK = 0x80000000 + + // SPI_MEM_USER: SPI0 user register. + // Position of SPI_MEM_CS_HOLD field. + SPI0_SPI_MEM_USER_SPI_MEM_CS_HOLD_Pos = 0x6 + // Bit mask of SPI_MEM_CS_HOLD field. + SPI0_SPI_MEM_USER_SPI_MEM_CS_HOLD_Msk = 0x40 + // Bit SPI_MEM_CS_HOLD. + SPI0_SPI_MEM_USER_SPI_MEM_CS_HOLD = 0x40 + // Position of SPI_MEM_CS_SETUP field. + SPI0_SPI_MEM_USER_SPI_MEM_CS_SETUP_Pos = 0x7 + // Bit mask of SPI_MEM_CS_SETUP field. + SPI0_SPI_MEM_USER_SPI_MEM_CS_SETUP_Msk = 0x80 + // Bit SPI_MEM_CS_SETUP. + SPI0_SPI_MEM_USER_SPI_MEM_CS_SETUP = 0x80 + // Position of SPI_MEM_CK_OUT_EDGE field. + SPI0_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of SPI_MEM_CK_OUT_EDGE field. + SPI0_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Msk = 0x200 + // Bit SPI_MEM_CK_OUT_EDGE. + SPI0_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE = 0x200 + // Position of SPI_MEM_USR_DUMMY_IDLE field. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of SPI_MEM_USR_DUMMY_IDLE field. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit SPI_MEM_USR_DUMMY_IDLE. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE = 0x4000000 + // Position of SPI_MEM_USR_DUMMY field. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Pos = 0x1d + // Bit mask of SPI_MEM_USR_DUMMY field. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Msk = 0x20000000 + // Bit SPI_MEM_USR_DUMMY. + SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY = 0x20000000 + + // SPI_MEM_USER1: SPI0 user1 register. + // Position of SPI_MEM_USR_DUMMY_CYCLELEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of SPI_MEM_USR_DUMMY_CYCLELEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of SPI_MEM_USR_DBYTELEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_DBYTELEN_Pos = 0x6 + // Bit mask of SPI_MEM_USR_DBYTELEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_DBYTELEN_Msk = 0x1c0 + // Position of SPI_MEM_USR_ADDR_BITLEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of SPI_MEM_USR_ADDR_BITLEN field. + SPI0_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // SPI_MEM_USER2: SPI0 user2 register. + // Position of SPI_MEM_USR_COMMAND_VALUE field. + SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_USR_COMMAND_VALUE field. + SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Msk = 0xffff + // Position of SPI_MEM_USR_COMMAND_BITLEN field. + SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of SPI_MEM_USR_COMMAND_BITLEN field. + SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // SPI_MEM_RD_STATUS: SPI0 read control register. + // Position of SPI_MEM_WB_MODE field. + SPI0_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Pos = 0x10 + // Bit mask of SPI_MEM_WB_MODE field. + SPI0_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Msk = 0xff0000 + + // SPI_MEM_MISC: SPI0 misc register + // Position of SPI_MEM_FSUB_PIN field. + SPI0_SPI_MEM_MISC_SPI_MEM_FSUB_PIN_Pos = 0x7 + // Bit mask of SPI_MEM_FSUB_PIN field. + SPI0_SPI_MEM_MISC_SPI_MEM_FSUB_PIN_Msk = 0x80 + // Bit SPI_MEM_FSUB_PIN. + SPI0_SPI_MEM_MISC_SPI_MEM_FSUB_PIN = 0x80 + // Position of SPI_MEM_SSUB_PIN field. + SPI0_SPI_MEM_MISC_SPI_MEM_SSUB_PIN_Pos = 0x8 + // Bit mask of SPI_MEM_SSUB_PIN field. + SPI0_SPI_MEM_MISC_SPI_MEM_SSUB_PIN_Msk = 0x100 + // Bit SPI_MEM_SSUB_PIN. + SPI0_SPI_MEM_MISC_SPI_MEM_SSUB_PIN = 0x100 + // Position of SPI_MEM_CK_IDLE_EDGE field. + SPI0_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of SPI_MEM_CK_IDLE_EDGE field. + SPI0_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Msk = 0x200 + // Bit SPI_MEM_CK_IDLE_EDGE. + SPI0_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE = 0x200 + // Position of SPI_MEM_CS_KEEP_ACTIVE field. + SPI0_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of SPI_MEM_CS_KEEP_ACTIVE field. + SPI0_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit SPI_MEM_CS_KEEP_ACTIVE. + SPI0_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE = 0x400 + + // SPI_MEM_CACHE_FCTRL: SPI0 bit mode control register. + // Position of SPI_MEM_AXI_REQ_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN_Pos = 0x0 + // Bit mask of SPI_MEM_AXI_REQ_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN_Msk = 0x1 + // Bit SPI_MEM_AXI_REQ_EN. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN = 0x1 + // Position of SPI_MEM_CACHE_USR_ADDR_4BYTE field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Pos = 0x1 + // Bit mask of SPI_MEM_CACHE_USR_ADDR_4BYTE field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Msk = 0x2 + // Bit SPI_MEM_CACHE_USR_ADDR_4BYTE. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE = 0x2 + // Position of SPI_MEM_CACHE_FLASH_USR_CMD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD_Pos = 0x2 + // Bit mask of SPI_MEM_CACHE_FLASH_USR_CMD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD_Msk = 0x4 + // Bit SPI_MEM_CACHE_FLASH_USR_CMD. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD = 0x4 + // Position of SPI_MEM_FDIN_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Pos = 0x3 + // Bit mask of SPI_MEM_FDIN_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Msk = 0x8 + // Bit SPI_MEM_FDIN_DUAL. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL = 0x8 + // Position of SPI_MEM_FDOUT_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Pos = 0x4 + // Bit mask of SPI_MEM_FDOUT_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Msk = 0x10 + // Bit SPI_MEM_FDOUT_DUAL. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL = 0x10 + // Position of SPI_MEM_FADDR_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Pos = 0x5 + // Bit mask of SPI_MEM_FADDR_DUAL field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Msk = 0x20 + // Bit SPI_MEM_FADDR_DUAL. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL = 0x20 + // Position of SPI_MEM_FDIN_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Pos = 0x6 + // Bit mask of SPI_MEM_FDIN_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Msk = 0x40 + // Bit SPI_MEM_FDIN_QUAD. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD = 0x40 + // Position of SPI_MEM_FDOUT_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Pos = 0x7 + // Bit mask of SPI_MEM_FDOUT_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Msk = 0x80 + // Bit SPI_MEM_FDOUT_QUAD. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD = 0x80 + // Position of SPI_MEM_FADDR_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Pos = 0x8 + // Bit mask of SPI_MEM_FADDR_QUAD field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Msk = 0x100 + // Bit SPI_MEM_FADDR_QUAD. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD = 0x100 + // Position of SPI_SAME_AW_AR_ADDR_CHK_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN_Pos = 0x1e + // Bit mask of SPI_SAME_AW_AR_ADDR_CHK_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN_Msk = 0x40000000 + // Bit SPI_SAME_AW_AR_ADDR_CHK_EN. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN = 0x40000000 + // Position of SPI_CLOSE_AXI_INF_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN_Pos = 0x1f + // Bit mask of SPI_CLOSE_AXI_INF_EN field. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN_Msk = 0x80000000 + // Bit SPI_CLOSE_AXI_INF_EN. + SPI0_SPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN = 0x80000000 + + // SPI_MEM_CACHE_SCTRL: SPI0 external RAM control register + // Position of SPI_MEM_CACHE_USR_SADDR_4BYTE field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE_Pos = 0x0 + // Bit mask of SPI_MEM_CACHE_USR_SADDR_4BYTE field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE_Msk = 0x1 + // Bit SPI_MEM_CACHE_USR_SADDR_4BYTE. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE = 0x1 + // Position of SPI_MEM_USR_SRAM_DIO field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO_Pos = 0x1 + // Bit mask of SPI_MEM_USR_SRAM_DIO field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO_Msk = 0x2 + // Bit SPI_MEM_USR_SRAM_DIO. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO = 0x2 + // Position of SPI_MEM_USR_SRAM_QIO field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO_Pos = 0x2 + // Bit mask of SPI_MEM_USR_SRAM_QIO field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO_Msk = 0x4 + // Bit SPI_MEM_USR_SRAM_QIO. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO = 0x4 + // Position of SPI_MEM_USR_WR_SRAM_DUMMY field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY_Pos = 0x3 + // Bit mask of SPI_MEM_USR_WR_SRAM_DUMMY field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY_Msk = 0x8 + // Bit SPI_MEM_USR_WR_SRAM_DUMMY. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY = 0x8 + // Position of SPI_MEM_USR_RD_SRAM_DUMMY field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY_Pos = 0x4 + // Bit mask of SPI_MEM_USR_RD_SRAM_DUMMY field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY_Msk = 0x10 + // Bit SPI_MEM_USR_RD_SRAM_DUMMY. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY = 0x10 + // Position of SPI_MEM_CACHE_SRAM_USR_RCMD field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD_Pos = 0x5 + // Bit mask of SPI_MEM_CACHE_SRAM_USR_RCMD field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD_Msk = 0x20 + // Bit SPI_MEM_CACHE_SRAM_USR_RCMD. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD = 0x20 + // Position of SPI_MEM_SRAM_RDUMMY_CYCLELEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN_Pos = 0x6 + // Bit mask of SPI_MEM_SRAM_RDUMMY_CYCLELEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN_Msk = 0xfc0 + // Position of SPI_MEM_SRAM_ADDR_BITLEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN_Pos = 0xe + // Bit mask of SPI_MEM_SRAM_ADDR_BITLEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN_Msk = 0xfc000 + // Position of SPI_MEM_CACHE_SRAM_USR_WCMD field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD_Pos = 0x14 + // Bit mask of SPI_MEM_CACHE_SRAM_USR_WCMD field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD_Msk = 0x100000 + // Bit SPI_MEM_CACHE_SRAM_USR_WCMD. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD = 0x100000 + // Position of SPI_MEM_SRAM_OCT field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT_Pos = 0x15 + // Bit mask of SPI_MEM_SRAM_OCT field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT_Msk = 0x200000 + // Bit SPI_MEM_SRAM_OCT. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT = 0x200000 + // Position of SPI_MEM_SRAM_WDUMMY_CYCLELEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN_Pos = 0x16 + // Bit mask of SPI_MEM_SRAM_WDUMMY_CYCLELEN field. + SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN_Msk = 0xfc00000 + + // SPI_MEM_SRAM_CMD: SPI0 external RAM mode control register + // Position of SPI_MEM_SCLK_MODE field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_SCLK_MODE field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE_Msk = 0x3 + // Position of SPI_MEM_SWB_MODE field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE_Pos = 0x2 + // Bit mask of SPI_MEM_SWB_MODE field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE_Msk = 0x3fc + // Position of SPI_MEM_SDIN_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL_Pos = 0xa + // Bit mask of SPI_MEM_SDIN_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL_Msk = 0x400 + // Bit SPI_MEM_SDIN_DUAL. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL = 0x400 + // Position of SPI_MEM_SDOUT_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL_Pos = 0xb + // Bit mask of SPI_MEM_SDOUT_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL_Msk = 0x800 + // Bit SPI_MEM_SDOUT_DUAL. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL = 0x800 + // Position of SPI_MEM_SADDR_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL_Pos = 0xc + // Bit mask of SPI_MEM_SADDR_DUAL field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL_Msk = 0x1000 + // Bit SPI_MEM_SADDR_DUAL. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL = 0x1000 + // Position of SPI_MEM_SDIN_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD_Pos = 0xe + // Bit mask of SPI_MEM_SDIN_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD_Msk = 0x4000 + // Bit SPI_MEM_SDIN_QUAD. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD = 0x4000 + // Position of SPI_MEM_SDOUT_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD_Pos = 0xf + // Bit mask of SPI_MEM_SDOUT_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD_Msk = 0x8000 + // Bit SPI_MEM_SDOUT_QUAD. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD = 0x8000 + // Position of SPI_MEM_SADDR_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD_Pos = 0x10 + // Bit mask of SPI_MEM_SADDR_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD_Msk = 0x10000 + // Bit SPI_MEM_SADDR_QUAD. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD = 0x10000 + // Position of SPI_MEM_SCMD_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD_Pos = 0x11 + // Bit mask of SPI_MEM_SCMD_QUAD field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD_Msk = 0x20000 + // Bit SPI_MEM_SCMD_QUAD. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD = 0x20000 + // Position of SPI_MEM_SDIN_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT_Pos = 0x12 + // Bit mask of SPI_MEM_SDIN_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT_Msk = 0x40000 + // Bit SPI_MEM_SDIN_OCT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT = 0x40000 + // Position of SPI_MEM_SDOUT_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT_Pos = 0x13 + // Bit mask of SPI_MEM_SDOUT_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT_Msk = 0x80000 + // Bit SPI_MEM_SDOUT_OCT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT = 0x80000 + // Position of SPI_MEM_SADDR_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT_Pos = 0x14 + // Bit mask of SPI_MEM_SADDR_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT_Msk = 0x100000 + // Bit SPI_MEM_SADDR_OCT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT = 0x100000 + // Position of SPI_MEM_SCMD_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT_Pos = 0x15 + // Bit mask of SPI_MEM_SCMD_OCT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT_Msk = 0x200000 + // Bit SPI_MEM_SCMD_OCT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT = 0x200000 + // Position of SPI_MEM_SDUMMY_RIN field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN_Pos = 0x16 + // Bit mask of SPI_MEM_SDUMMY_RIN field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN_Msk = 0x400000 + // Bit SPI_MEM_SDUMMY_RIN. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN = 0x400000 + // Position of SPI_MEM_SDUMMY_WOUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT_Pos = 0x17 + // Bit mask of SPI_MEM_SDUMMY_WOUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT_Msk = 0x800000 + // Bit SPI_MEM_SDUMMY_WOUT. + SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT = 0x800000 + // Position of SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_Pos = 0x18 + // Bit mask of SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_Msk = 0x1000000 + // Bit SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT = 0x1000000 + // Position of SPI_SMEM_WDUMMY_ALWAYS_OUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT_Pos = 0x19 + // Bit mask of SPI_SMEM_WDUMMY_ALWAYS_OUT field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT_Msk = 0x2000000 + // Bit SPI_SMEM_WDUMMY_ALWAYS_OUT. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT = 0x2000000 + // Position of SPI_SMEM_DQS_IE_ALWAYS_ON field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON_Pos = 0x1e + // Bit mask of SPI_SMEM_DQS_IE_ALWAYS_ON field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON_Msk = 0x40000000 + // Bit SPI_SMEM_DQS_IE_ALWAYS_ON. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON = 0x40000000 + // Position of SPI_SMEM_DATA_IE_ALWAYS_ON field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON_Pos = 0x1f + // Bit mask of SPI_SMEM_DATA_IE_ALWAYS_ON field. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON_Msk = 0x80000000 + // Bit SPI_SMEM_DATA_IE_ALWAYS_ON. + SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON = 0x80000000 + + // SPI_MEM_SRAM_DRD_CMD: SPI0 external RAM DDR read command control register + // Position of SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE field. + SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE field. + SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_Msk = 0xffff + // Position of SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN field. + SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_Pos = 0x1c + // Bit mask of SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN field. + SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_Msk = 0xf0000000 + + // SPI_MEM_SRAM_DWR_CMD: SPI0 external RAM DDR write command control register + // Position of SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE field. + SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE field. + SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_Msk = 0xffff + // Position of SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN field. + SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_Pos = 0x1c + // Bit mask of SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN field. + SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_Msk = 0xf0000000 + + // SPI_MEM_SRAM_CLK: SPI0 external RAM clock control register + // Position of SPI_MEM_SCLKCNT_L field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L_Pos = 0x0 + // Bit mask of SPI_MEM_SCLKCNT_L field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L_Msk = 0xff + // Position of SPI_MEM_SCLKCNT_H field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H_Pos = 0x8 + // Bit mask of SPI_MEM_SCLKCNT_H field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H_Msk = 0xff00 + // Position of SPI_MEM_SCLKCNT_N field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N_Pos = 0x10 + // Bit mask of SPI_MEM_SCLKCNT_N field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N_Msk = 0xff0000 + // Position of SPI_MEM_SCLK_EQU_SYSCLK field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of SPI_MEM_SCLK_EQU_SYSCLK field. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit SPI_MEM_SCLK_EQU_SYSCLK. + SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK = 0x80000000 + + // SPI_MEM_FSM: SPI0 FSM status register + // Position of SPI_MEM_LOCK_DELAY_TIME field. + SPI0_SPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME_Pos = 0x7 + // Bit mask of SPI_MEM_LOCK_DELAY_TIME field. + SPI0_SPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME_Msk = 0xf80 + + // SPI_MEM_INT_ENA: SPI0 interrupt enable register + // Position of SPI_MEM_SLV_ST_END_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA = 0x10 + // Position of SPI_MEM_ECC_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA_Pos = 0x5 + // Bit mask of SPI_MEM_ECC_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA_Msk = 0x20 + // Bit SPI_MEM_ECC_ERR_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA = 0x20 + // Position of SPI_MEM_PMS_REJECT_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA_Pos = 0x6 + // Bit mask of SPI_MEM_PMS_REJECT_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA_Msk = 0x40 + // Bit SPI_MEM_PMS_REJECT_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA = 0x40 + // Position of SPI_MEM_AXI_RADDR_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA_Pos = 0x7 + // Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA_Msk = 0x80 + // Bit SPI_MEM_AXI_RADDR_ERR_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA = 0x80 + // Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_Pos = 0x8 + // Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_Msk = 0x100 + // Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA = 0x100 + // Position of SPI_MEM_AXI_WADDR_ERR_INT__ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA_Pos = 0x9 + // Bit mask of SPI_MEM_AXI_WADDR_ERR_INT__ENA field. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA_Msk = 0x200 + // Bit SPI_MEM_AXI_WADDR_ERR_INT__ENA. + SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA = 0x200 + + // SPI_MEM_INT_CLR: SPI0 interrupt clear register + // Position of SPI_MEM_SLV_ST_END_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR = 0x10 + // Position of SPI_MEM_ECC_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR_Pos = 0x5 + // Bit mask of SPI_MEM_ECC_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR_Msk = 0x20 + // Bit SPI_MEM_ECC_ERR_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR = 0x20 + // Position of SPI_MEM_PMS_REJECT_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR_Pos = 0x6 + // Bit mask of SPI_MEM_PMS_REJECT_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR_Msk = 0x40 + // Bit SPI_MEM_PMS_REJECT_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR = 0x40 + // Position of SPI_MEM_AXI_RADDR_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR_Pos = 0x7 + // Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR_Msk = 0x80 + // Bit SPI_MEM_AXI_RADDR_ERR_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR = 0x80 + // Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_Pos = 0x8 + // Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_Msk = 0x100 + // Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR = 0x100 + // Position of SPI_MEM_AXI_WADDR_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR_Pos = 0x9 + // Bit mask of SPI_MEM_AXI_WADDR_ERR_INT_CLR field. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR_Msk = 0x200 + // Bit SPI_MEM_AXI_WADDR_ERR_INT_CLR. + SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR = 0x200 + + // SPI_MEM_INT_RAW: SPI0 interrupt raw register + // Position of SPI_MEM_SLV_ST_END_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW = 0x10 + // Position of SPI_MEM_ECC_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW_Pos = 0x5 + // Bit mask of SPI_MEM_ECC_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW_Msk = 0x20 + // Bit SPI_MEM_ECC_ERR_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW = 0x20 + // Position of SPI_MEM_PMS_REJECT_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW_Pos = 0x6 + // Bit mask of SPI_MEM_PMS_REJECT_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW_Msk = 0x40 + // Bit SPI_MEM_PMS_REJECT_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW = 0x40 + // Position of SPI_MEM_AXI_RADDR_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW_Pos = 0x7 + // Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW_Msk = 0x80 + // Bit SPI_MEM_AXI_RADDR_ERR_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW = 0x80 + // Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_Pos = 0x8 + // Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_Msk = 0x100 + // Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW = 0x100 + // Position of SPI_MEM_AXI_WADDR_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW_Pos = 0x9 + // Bit mask of SPI_MEM_AXI_WADDR_ERR_INT_RAW field. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW_Msk = 0x200 + // Bit SPI_MEM_AXI_WADDR_ERR_INT_RAW. + SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW = 0x200 + + // SPI_MEM_INT_ST: SPI0 interrupt status register + // Position of SPI_MEM_SLV_ST_END_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST = 0x10 + // Position of SPI_MEM_ECC_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST_Pos = 0x5 + // Bit mask of SPI_MEM_ECC_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST_Msk = 0x20 + // Bit SPI_MEM_ECC_ERR_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST = 0x20 + // Position of SPI_MEM_PMS_REJECT_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST_Pos = 0x6 + // Bit mask of SPI_MEM_PMS_REJECT_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST_Msk = 0x40 + // Bit SPI_MEM_PMS_REJECT_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST = 0x40 + // Position of SPI_MEM_AXI_RADDR_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST_Pos = 0x7 + // Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST_Msk = 0x80 + // Bit SPI_MEM_AXI_RADDR_ERR_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST = 0x80 + // Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_Pos = 0x8 + // Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_Msk = 0x100 + // Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST = 0x100 + // Position of SPI_MEM_AXI_WADDR_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST_Pos = 0x9 + // Bit mask of SPI_MEM_AXI_WADDR_ERR_INT_ST field. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST_Msk = 0x200 + // Bit SPI_MEM_AXI_WADDR_ERR_INT_ST. + SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST = 0x200 + + // SPI_MEM_DDR: SPI0 flash DDR mode control register + // Position of SPI_FMEM_DDR_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Pos = 0x0 + // Bit mask of SPI_FMEM_DDR_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Msk = 0x1 + // Bit SPI_FMEM_DDR_EN. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_EN = 0x1 + // Position of SPI_FMEM_VAR_DUMMY field. + SPI0_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Pos = 0x1 + // Bit mask of SPI_FMEM_VAR_DUMMY field. + SPI0_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Msk = 0x2 + // Bit SPI_FMEM_VAR_DUMMY. + SPI0_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY = 0x2 + // Position of SPI_FMEM_DDR_RDAT_SWP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Pos = 0x2 + // Bit mask of SPI_FMEM_DDR_RDAT_SWP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Msk = 0x4 + // Bit SPI_FMEM_DDR_RDAT_SWP. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP = 0x4 + // Position of SPI_FMEM_DDR_WDAT_SWP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Pos = 0x3 + // Bit mask of SPI_FMEM_DDR_WDAT_SWP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Msk = 0x8 + // Bit SPI_FMEM_DDR_WDAT_SWP. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP = 0x8 + // Position of SPI_FMEM_DDR_CMD_DIS field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Pos = 0x4 + // Bit mask of SPI_FMEM_DDR_CMD_DIS field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Msk = 0x10 + // Bit SPI_FMEM_DDR_CMD_DIS. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS = 0x10 + // Position of SPI_FMEM_OUTMINBYTELEN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Pos = 0x5 + // Bit mask of SPI_FMEM_OUTMINBYTELEN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Msk = 0xfe0 + // Position of SPI_FMEM_TX_DDR_MSK_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN_Pos = 0xc + // Bit mask of SPI_FMEM_TX_DDR_MSK_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN_Msk = 0x1000 + // Bit SPI_FMEM_TX_DDR_MSK_EN. + SPI0_SPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN = 0x1000 + // Position of SPI_FMEM_RX_DDR_MSK_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN_Pos = 0xd + // Bit mask of SPI_FMEM_RX_DDR_MSK_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN_Msk = 0x2000 + // Bit SPI_FMEM_RX_DDR_MSK_EN. + SPI0_SPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN = 0x2000 + // Position of SPI_FMEM_USR_DDR_DQS_THD field. + SPI0_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Pos = 0xe + // Bit mask of SPI_FMEM_USR_DDR_DQS_THD field. + SPI0_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Msk = 0x1fc000 + // Position of SPI_FMEM_DDR_DQS_LOOP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Pos = 0x15 + // Bit mask of SPI_FMEM_DDR_DQS_LOOP field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Msk = 0x200000 + // Bit SPI_FMEM_DDR_DQS_LOOP. + SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP = 0x200000 + // Position of SPI_FMEM_CLK_DIFF_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Pos = 0x18 + // Bit mask of SPI_FMEM_CLK_DIFF_EN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Msk = 0x1000000 + // Bit SPI_FMEM_CLK_DIFF_EN. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN = 0x1000000 + // Position of SPI_FMEM_DQS_CA_IN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Pos = 0x1a + // Bit mask of SPI_FMEM_DQS_CA_IN field. + SPI0_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Msk = 0x4000000 + // Bit SPI_FMEM_DQS_CA_IN. + SPI0_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN = 0x4000000 + // Position of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b + // Bit mask of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000 + // Bit SPI_FMEM_HYPERBUS_DUMMY_2X. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X = 0x8000000 + // Position of SPI_FMEM_CLK_DIFF_INV field. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Pos = 0x1c + // Bit mask of SPI_FMEM_CLK_DIFF_INV field. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Msk = 0x10000000 + // Bit SPI_FMEM_CLK_DIFF_INV. + SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV = 0x10000000 + // Position of SPI_FMEM_OCTA_RAM_ADDR field. + SPI0_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Pos = 0x1d + // Bit mask of SPI_FMEM_OCTA_RAM_ADDR field. + SPI0_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Msk = 0x20000000 + // Bit SPI_FMEM_OCTA_RAM_ADDR. + SPI0_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR = 0x20000000 + // Position of SPI_FMEM_HYPERBUS_CA field. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Pos = 0x1e + // Bit mask of SPI_FMEM_HYPERBUS_CA field. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Msk = 0x40000000 + // Bit SPI_FMEM_HYPERBUS_CA. + SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA = 0x40000000 + + // SPI_SMEM_DDR: SPI0 external RAM DDR mode control register + // Position of EN field. + SPI0_SPI_SMEM_DDR_EN_Pos = 0x0 + // Bit mask of EN field. + SPI0_SPI_SMEM_DDR_EN_Msk = 0x1 + // Bit EN. + SPI0_SPI_SMEM_DDR_EN = 0x1 + // Position of SPI_SMEM_VAR_DUMMY field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY_Pos = 0x1 + // Bit mask of SPI_SMEM_VAR_DUMMY field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY_Msk = 0x2 + // Bit SPI_SMEM_VAR_DUMMY. + SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY = 0x2 + // Position of RDAT_SWP field. + SPI0_SPI_SMEM_DDR_RDAT_SWP_Pos = 0x2 + // Bit mask of RDAT_SWP field. + SPI0_SPI_SMEM_DDR_RDAT_SWP_Msk = 0x4 + // Bit RDAT_SWP. + SPI0_SPI_SMEM_DDR_RDAT_SWP = 0x4 + // Position of WDAT_SWP field. + SPI0_SPI_SMEM_DDR_WDAT_SWP_Pos = 0x3 + // Bit mask of WDAT_SWP field. + SPI0_SPI_SMEM_DDR_WDAT_SWP_Msk = 0x8 + // Bit WDAT_SWP. + SPI0_SPI_SMEM_DDR_WDAT_SWP = 0x8 + // Position of CMD_DIS field. + SPI0_SPI_SMEM_DDR_CMD_DIS_Pos = 0x4 + // Bit mask of CMD_DIS field. + SPI0_SPI_SMEM_DDR_CMD_DIS_Msk = 0x10 + // Bit CMD_DIS. + SPI0_SPI_SMEM_DDR_CMD_DIS = 0x10 + // Position of SPI_SMEM_OUTMINBYTELEN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN_Pos = 0x5 + // Bit mask of SPI_SMEM_OUTMINBYTELEN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN_Msk = 0xfe0 + // Position of SPI_SMEM_TX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN_Pos = 0xc + // Bit mask of SPI_SMEM_TX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN_Msk = 0x1000 + // Bit SPI_SMEM_TX_DDR_MSK_EN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN = 0x1000 + // Position of SPI_SMEM_RX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN_Pos = 0xd + // Bit mask of SPI_SMEM_RX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN_Msk = 0x2000 + // Bit SPI_SMEM_RX_DDR_MSK_EN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN = 0x2000 + // Position of SPI_SMEM_USR_DDR_DQS_THD field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD_Pos = 0xe + // Bit mask of SPI_SMEM_USR_DDR_DQS_THD field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD_Msk = 0x1fc000 + // Position of DQS_LOOP field. + SPI0_SPI_SMEM_DDR_DQS_LOOP_Pos = 0x15 + // Bit mask of DQS_LOOP field. + SPI0_SPI_SMEM_DDR_DQS_LOOP_Msk = 0x200000 + // Bit DQS_LOOP. + SPI0_SPI_SMEM_DDR_DQS_LOOP = 0x200000 + // Position of SPI_SMEM_CLK_DIFF_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN_Pos = 0x18 + // Bit mask of SPI_SMEM_CLK_DIFF_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN_Msk = 0x1000000 + // Bit SPI_SMEM_CLK_DIFF_EN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN = 0x1000000 + // Position of SPI_SMEM_DQS_CA_IN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN_Pos = 0x1a + // Bit mask of SPI_SMEM_DQS_CA_IN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN_Msk = 0x4000000 + // Bit SPI_SMEM_DQS_CA_IN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN = 0x4000000 + // Position of SPI_SMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b + // Bit mask of SPI_SMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000 + // Bit SPI_SMEM_HYPERBUS_DUMMY_2X. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X = 0x8000000 + // Position of SPI_SMEM_CLK_DIFF_INV field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV_Pos = 0x1c + // Bit mask of SPI_SMEM_CLK_DIFF_INV field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV_Msk = 0x10000000 + // Bit SPI_SMEM_CLK_DIFF_INV. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV = 0x10000000 + // Position of SPI_SMEM_OCTA_RAM_ADDR field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR_Pos = 0x1d + // Bit mask of SPI_SMEM_OCTA_RAM_ADDR field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR_Msk = 0x20000000 + // Bit SPI_SMEM_OCTA_RAM_ADDR. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR = 0x20000000 + // Position of SPI_SMEM_HYPERBUS_CA field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA_Pos = 0x1e + // Bit mask of SPI_SMEM_HYPERBUS_CA field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA_Msk = 0x40000000 + // Bit SPI_SMEM_HYPERBUS_CA. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA = 0x40000000 + + // SPI_FMEM_PMS0_ATTR: MSPI flash ACE section %s attribute register + // Position of SPI_FMEM_PMS_RD_ATTR field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_RD_ATTR_Pos = 0x0 + // Bit mask of SPI_FMEM_PMS_RD_ATTR field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_RD_ATTR_Msk = 0x1 + // Bit SPI_FMEM_PMS_RD_ATTR. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_RD_ATTR = 0x1 + // Position of SPI_FMEM_PMS_WR_ATTR field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_WR_ATTR_Pos = 0x1 + // Bit mask of SPI_FMEM_PMS_WR_ATTR field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_WR_ATTR_Msk = 0x2 + // Bit SPI_FMEM_PMS_WR_ATTR. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_WR_ATTR = 0x2 + // Position of SPI_FMEM_PMS_ECC field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_ECC_Pos = 0x2 + // Bit mask of SPI_FMEM_PMS_ECC field. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_ECC_Msk = 0x4 + // Bit SPI_FMEM_PMS_ECC. + SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_ECC = 0x4 + + // SPI_FMEM_PMS0_ADDR: SPI1 flash ACE section %s start address register + // Position of S field. + SPI0_SPI_FMEM_PMS_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SPI0_SPI_FMEM_PMS_ADDR_S_Msk = 0x3ffffff + + // SPI_FMEM_PMS0_SIZE: SPI1 flash ACE section %s start address register + // Position of SPI_FMEM_PMS_SIZE field. + SPI0_SPI_FMEM_PMS_SIZE_SPI_FMEM_PMS_SIZE_Pos = 0x0 + // Bit mask of SPI_FMEM_PMS_SIZE field. + SPI0_SPI_FMEM_PMS_SIZE_SPI_FMEM_PMS_SIZE_Msk = 0x3fff + + // SPI_SMEM_PMS0_ATTR: SPI1 flash ACE section %s start address register + // Position of SPI_SMEM_PMS_RD_ATTR field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_RD_ATTR_Pos = 0x0 + // Bit mask of SPI_SMEM_PMS_RD_ATTR field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_RD_ATTR_Msk = 0x1 + // Bit SPI_SMEM_PMS_RD_ATTR. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_RD_ATTR = 0x1 + // Position of SPI_SMEM_PMS_WR_ATTR field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_WR_ATTR_Pos = 0x1 + // Bit mask of SPI_SMEM_PMS_WR_ATTR field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_WR_ATTR_Msk = 0x2 + // Bit SPI_SMEM_PMS_WR_ATTR. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_WR_ATTR = 0x2 + // Position of SPI_SMEM_PMS_ECC field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_ECC_Pos = 0x2 + // Bit mask of SPI_SMEM_PMS_ECC field. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_ECC_Msk = 0x4 + // Bit SPI_SMEM_PMS_ECC. + SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_ECC = 0x4 + + // SPI_SMEM_PMS0_ADDR: SPI1 external RAM ACE section %s start address register + // Position of S field. + SPI0_SPI_SMEM_PMS_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SPI0_SPI_SMEM_PMS_ADDR_S_Msk = 0x3ffffff + + // SPI_SMEM_PMS0_SIZE: SPI1 external RAM ACE section %s start address register + // Position of SPI_SMEM_PMS_SIZE field. + SPI0_SPI_SMEM_PMS_SIZE_SPI_SMEM_PMS_SIZE_Pos = 0x0 + // Bit mask of SPI_SMEM_PMS_SIZE field. + SPI0_SPI_SMEM_PMS_SIZE_SPI_SMEM_PMS_SIZE_Msk = 0x3fff + + // SPI_MEM_PMS_REJECT: SPI1 access reject register + // Position of SPI_MEM_REJECT_ADDR field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_ADDR field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR_Msk = 0x3ffffff + // Position of SPI_MEM_PM_EN field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PM_EN_Pos = 0x1a + // Bit mask of SPI_MEM_PM_EN field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PM_EN_Msk = 0x4000000 + // Bit SPI_MEM_PM_EN. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PM_EN = 0x4000000 + // Position of SPI_MEM_PMS_LD field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD_Pos = 0x1c + // Bit mask of SPI_MEM_PMS_LD field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD_Msk = 0x10000000 + // Bit SPI_MEM_PMS_LD. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD = 0x10000000 + // Position of SPI_MEM_PMS_ST field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST_Pos = 0x1d + // Bit mask of SPI_MEM_PMS_ST field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST_Msk = 0x20000000 + // Bit SPI_MEM_PMS_ST. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST = 0x20000000 + // Position of SPI_MEM_PMS_MULTI_HIT field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT_Pos = 0x1e + // Bit mask of SPI_MEM_PMS_MULTI_HIT field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT_Msk = 0x40000000 + // Bit SPI_MEM_PMS_MULTI_HIT. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT = 0x40000000 + // Position of SPI_MEM_PMS_IVD field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD_Pos = 0x1f + // Bit mask of SPI_MEM_PMS_IVD field. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD_Msk = 0x80000000 + // Bit SPI_MEM_PMS_IVD. + SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD = 0x80000000 + + // SPI_MEM_ECC_CTRL: MSPI ECC control register + // Position of SPI_FMEM_ECC_ERR_INT_NUM field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM_Pos = 0xb + // Bit mask of SPI_FMEM_ECC_ERR_INT_NUM field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM_Msk = 0x1f800 + // Position of SPI_FMEM_ECC_ERR_INT_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN_Pos = 0x11 + // Bit mask of SPI_FMEM_ECC_ERR_INT_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN_Msk = 0x20000 + // Bit SPI_FMEM_ECC_ERR_INT_EN. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN = 0x20000 + // Position of SPI_FMEM_PAGE_SIZE field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE_Pos = 0x12 + // Bit mask of SPI_FMEM_PAGE_SIZE field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE_Msk = 0xc0000 + // Position of SPI_FMEM_ECC_ADDR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN_Pos = 0x14 + // Bit mask of SPI_FMEM_ECC_ADDR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN_Msk = 0x100000 + // Bit SPI_FMEM_ECC_ADDR_EN. + SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN = 0x100000 + // Position of SPI_MEM_USR_ECC_ADDR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN_Pos = 0x15 + // Bit mask of SPI_MEM_USR_ECC_ADDR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN_Msk = 0x200000 + // Bit SPI_MEM_USR_ECC_ADDR_EN. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN = 0x200000 + // Position of SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_Pos = 0x18 + // Bit mask of SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_Msk = 0x1000000 + // Bit SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN = 0x1000000 + // Position of SPI_MEM_ECC_ERR_BITS field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS_Pos = 0x19 + // Bit mask of SPI_MEM_ECC_ERR_BITS field. + SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS_Msk = 0xfe000000 + + // SPI_MEM_ECC_ERR_ADDR: MSPI ECC error address register + // Position of SPI_MEM_ECC_ERR_ADDR field. + SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_ECC_ERR_ADDR field. + SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_ADDR_Msk = 0x3ffffff + // Position of SPI_MEM_ECC_ERR_CNT field. + SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_CNT_Pos = 0x1a + // Bit mask of SPI_MEM_ECC_ERR_CNT field. + SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_CNT_Msk = 0xfc000000 + + // SPI_MEM_AXI_ERR_ADDR: SPI0 AXI request error address. + // Position of SPI_MEM_AXI_ERR_ADDR field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_AXI_ERR_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_AXI_ERR_ADDR field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_AXI_ERR_ADDR_Msk = 0x3ffffff + // Position of SPI_MEM_ALL_FIFO_EMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY_Pos = 0x1a + // Bit mask of SPI_MEM_ALL_FIFO_EMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY_Msk = 0x4000000 + // Bit SPI_MEM_ALL_FIFO_EMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_ALL_FIFO_EMPTY = 0x4000000 + // Position of SPI_RDATA_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY_Pos = 0x1b + // Bit mask of SPI_RDATA_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY_Msk = 0x8000000 + // Bit SPI_RDATA_AFIFO_REMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RDATA_AFIFO_REMPTY = 0x8000000 + // Position of SPI_RADDR_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY_Pos = 0x1c + // Bit mask of SPI_RADDR_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY_Msk = 0x10000000 + // Bit SPI_RADDR_AFIFO_REMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_RADDR_AFIFO_REMPTY = 0x10000000 + // Position of SPI_WDATA_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY_Pos = 0x1d + // Bit mask of SPI_WDATA_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY_Msk = 0x20000000 + // Bit SPI_WDATA_AFIFO_REMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WDATA_AFIFO_REMPTY = 0x20000000 + // Position of SPI_WBLEN_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY_Pos = 0x1e + // Bit mask of SPI_WBLEN_AFIFO_REMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY_Msk = 0x40000000 + // Bit SPI_WBLEN_AFIFO_REMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_WBLEN_AFIFO_REMPTY = 0x40000000 + // Position of SPI_ALL_AXI_TRANS_AFIFO_EMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_Pos = 0x1f + // Bit mask of SPI_ALL_AXI_TRANS_AFIFO_EMPTY field. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_Msk = 0x80000000 + // Bit SPI_ALL_AXI_TRANS_AFIFO_EMPTY. + SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_ALL_AXI_TRANS_AFIFO_EMPTY = 0x80000000 + + // SPI_SMEM_ECC_CTRL: MSPI ECC control register + // Position of SPI_SMEM_ECC_ERR_INT_EN field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN_Pos = 0x11 + // Bit mask of SPI_SMEM_ECC_ERR_INT_EN field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN_Msk = 0x20000 + // Bit SPI_SMEM_ECC_ERR_INT_EN. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN = 0x20000 + // Position of SPI_SMEM_PAGE_SIZE field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE_Pos = 0x12 + // Bit mask of SPI_SMEM_PAGE_SIZE field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE_Msk = 0xc0000 + // Position of SPI_SMEM_ECC_ADDR_EN field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN_Pos = 0x14 + // Bit mask of SPI_SMEM_ECC_ADDR_EN field. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN_Msk = 0x100000 + // Bit SPI_SMEM_ECC_ADDR_EN. + SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN = 0x100000 + + // SPI_MEM_TIMING_CALI: SPI0 flash timing calibration register + // Position of SPI_MEM_TIMING_CLK_ENA field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA_Pos = 0x0 + // Bit mask of SPI_MEM_TIMING_CLK_ENA field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA_Msk = 0x1 + // Bit SPI_MEM_TIMING_CLK_ENA. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA = 0x1 + // Position of SPI_MEM_TIMING_CALI field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Pos = 0x1 + // Bit mask of SPI_MEM_TIMING_CALI field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Msk = 0x2 + // Bit SPI_MEM_TIMING_CALI. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI = 0x2 + // Position of SPI_MEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of SPI_MEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + // Position of SPI_MEM_DLL_TIMING_CALI field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI_Pos = 0x5 + // Bit mask of SPI_MEM_DLL_TIMING_CALI field. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI_Msk = 0x20 + // Bit SPI_MEM_DLL_TIMING_CALI. + SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI = 0x20 + // Position of UPDATE field. + SPI0_SPI_MEM_TIMING_CALI_UPDATE_Pos = 0x6 + // Bit mask of UPDATE field. + SPI0_SPI_MEM_TIMING_CALI_UPDATE_Msk = 0x40 + // Bit UPDATE. + SPI0_SPI_MEM_TIMING_CALI_UPDATE = 0x40 + + // SPI_MEM_DIN_MODE: MSPI flash input timing delay mode control register + // Position of SPI_MEM_DIN0_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_DIN0_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE_Msk = 0x7 + // Position of SPI_MEM_DIN1_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE_Pos = 0x3 + // Bit mask of SPI_MEM_DIN1_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE_Msk = 0x38 + // Position of SPI_MEM_DIN2_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE_Pos = 0x6 + // Bit mask of SPI_MEM_DIN2_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE_Msk = 0x1c0 + // Position of SPI_MEM_DIN3_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE_Pos = 0x9 + // Bit mask of SPI_MEM_DIN3_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE_Msk = 0xe00 + // Position of SPI_MEM_DIN4_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE_Pos = 0xc + // Bit mask of SPI_MEM_DIN4_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE_Msk = 0x7000 + // Position of SPI_MEM_DIN5_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE_Pos = 0xf + // Bit mask of SPI_MEM_DIN5_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE_Msk = 0x38000 + // Position of SPI_MEM_DIN6_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE_Pos = 0x12 + // Bit mask of SPI_MEM_DIN6_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE_Msk = 0x1c0000 + // Position of SPI_MEM_DIN7_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE_Pos = 0x15 + // Bit mask of SPI_MEM_DIN7_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE_Msk = 0xe00000 + // Position of SPI_MEM_DINS_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE_Pos = 0x18 + // Bit mask of SPI_MEM_DINS_MODE field. + SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE_Msk = 0x7000000 + + // SPI_MEM_DIN_NUM: MSPI flash input timing delay number control register + // Position of SPI_MEM_DIN0_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM_Pos = 0x0 + // Bit mask of SPI_MEM_DIN0_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM_Msk = 0x3 + // Position of SPI_MEM_DIN1_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM_Pos = 0x2 + // Bit mask of SPI_MEM_DIN1_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM_Msk = 0xc + // Position of SPI_MEM_DIN2_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM_Pos = 0x4 + // Bit mask of SPI_MEM_DIN2_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM_Msk = 0x30 + // Position of SPI_MEM_DIN3_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM_Pos = 0x6 + // Bit mask of SPI_MEM_DIN3_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM_Msk = 0xc0 + // Position of SPI_MEM_DIN4_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM_Pos = 0x8 + // Bit mask of SPI_MEM_DIN4_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM_Msk = 0x300 + // Position of SPI_MEM_DIN5_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM_Pos = 0xa + // Bit mask of SPI_MEM_DIN5_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM_Msk = 0xc00 + // Position of SPI_MEM_DIN6_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM_Pos = 0xc + // Bit mask of SPI_MEM_DIN6_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM_Msk = 0x3000 + // Position of SPI_MEM_DIN7_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM_Pos = 0xe + // Bit mask of SPI_MEM_DIN7_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM_Msk = 0xc000 + // Position of SPI_MEM_DINS_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM_Pos = 0x10 + // Bit mask of SPI_MEM_DINS_NUM field. + SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM_Msk = 0x30000 + + // SPI_MEM_DOUT_MODE: MSPI flash output timing adjustment control register + // Position of SPI_MEM_DOUT0_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_DOUT0_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE_Msk = 0x1 + // Bit SPI_MEM_DOUT0_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE = 0x1 + // Position of SPI_MEM_DOUT1_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE_Pos = 0x1 + // Bit mask of SPI_MEM_DOUT1_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE_Msk = 0x2 + // Bit SPI_MEM_DOUT1_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE = 0x2 + // Position of SPI_MEM_DOUT2_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE_Pos = 0x2 + // Bit mask of SPI_MEM_DOUT2_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE_Msk = 0x4 + // Bit SPI_MEM_DOUT2_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE = 0x4 + // Position of SPI_MEM_DOUT3_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE_Pos = 0x3 + // Bit mask of SPI_MEM_DOUT3_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE_Msk = 0x8 + // Bit SPI_MEM_DOUT3_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE = 0x8 + // Position of SPI_MEM_DOUT4_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE_Pos = 0x4 + // Bit mask of SPI_MEM_DOUT4_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE_Msk = 0x10 + // Bit SPI_MEM_DOUT4_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE = 0x10 + // Position of SPI_MEM_DOUT5_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE_Pos = 0x5 + // Bit mask of SPI_MEM_DOUT5_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE_Msk = 0x20 + // Bit SPI_MEM_DOUT5_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE = 0x20 + // Position of SPI_MEM_DOUT6_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE_Pos = 0x6 + // Bit mask of SPI_MEM_DOUT6_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE_Msk = 0x40 + // Bit SPI_MEM_DOUT6_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE = 0x40 + // Position of SPI_MEM_DOUT7_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE_Pos = 0x7 + // Bit mask of SPI_MEM_DOUT7_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE_Msk = 0x80 + // Bit SPI_MEM_DOUT7_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE = 0x80 + // Position of SPI_MEM_DOUTS_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE_Pos = 0x8 + // Bit mask of SPI_MEM_DOUTS_MODE field. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE_Msk = 0x100 + // Bit SPI_MEM_DOUTS_MODE. + SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE = 0x100 + + // SPI_SMEM_TIMING_CALI: MSPI external RAM timing calibration register + // Position of SPI_SMEM_TIMING_CLK_ENA field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA_Pos = 0x0 + // Bit mask of SPI_SMEM_TIMING_CLK_ENA field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA_Msk = 0x1 + // Bit SPI_SMEM_TIMING_CLK_ENA. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA = 0x1 + // Position of SPI_SMEM_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI_Pos = 0x1 + // Bit mask of SPI_SMEM_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI_Msk = 0x2 + // Bit SPI_SMEM_TIMING_CALI. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI = 0x2 + // Position of SPI_SMEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of SPI_SMEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + // Position of SPI_SMEM_DLL_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI_Pos = 0x5 + // Bit mask of SPI_SMEM_DLL_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI_Msk = 0x20 + // Bit SPI_SMEM_DLL_TIMING_CALI. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI = 0x20 + + // SPI_SMEM_DIN_MODE: MSPI external RAM input timing delay mode control register + // Position of SPI_SMEM_DIN0_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE_Pos = 0x0 + // Bit mask of SPI_SMEM_DIN0_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE_Msk = 0x7 + // Position of SPI_SMEM_DIN1_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE_Pos = 0x3 + // Bit mask of SPI_SMEM_DIN1_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE_Msk = 0x38 + // Position of SPI_SMEM_DIN2_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE_Pos = 0x6 + // Bit mask of SPI_SMEM_DIN2_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE_Msk = 0x1c0 + // Position of SPI_SMEM_DIN3_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE_Pos = 0x9 + // Bit mask of SPI_SMEM_DIN3_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE_Msk = 0xe00 + // Position of SPI_SMEM_DIN4_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE_Pos = 0xc + // Bit mask of SPI_SMEM_DIN4_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE_Msk = 0x7000 + // Position of SPI_SMEM_DIN5_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE_Pos = 0xf + // Bit mask of SPI_SMEM_DIN5_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE_Msk = 0x38000 + // Position of SPI_SMEM_DIN6_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE_Pos = 0x12 + // Bit mask of SPI_SMEM_DIN6_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE_Msk = 0x1c0000 + // Position of SPI_SMEM_DIN7_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE_Pos = 0x15 + // Bit mask of SPI_SMEM_DIN7_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE_Msk = 0xe00000 + // Position of SPI_SMEM_DINS_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE_Pos = 0x18 + // Bit mask of SPI_SMEM_DINS_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE_Msk = 0x7000000 + + // SPI_SMEM_DIN_NUM: MSPI external RAM input timing delay number control register + // Position of SPI_SMEM_DIN0_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM_Pos = 0x0 + // Bit mask of SPI_SMEM_DIN0_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM_Msk = 0x3 + // Position of SPI_SMEM_DIN1_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM_Pos = 0x2 + // Bit mask of SPI_SMEM_DIN1_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM_Msk = 0xc + // Position of SPI_SMEM_DIN2_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM_Pos = 0x4 + // Bit mask of SPI_SMEM_DIN2_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM_Msk = 0x30 + // Position of SPI_SMEM_DIN3_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM_Pos = 0x6 + // Bit mask of SPI_SMEM_DIN3_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM_Msk = 0xc0 + // Position of SPI_SMEM_DIN4_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM_Pos = 0x8 + // Bit mask of SPI_SMEM_DIN4_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM_Msk = 0x300 + // Position of SPI_SMEM_DIN5_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM_Pos = 0xa + // Bit mask of SPI_SMEM_DIN5_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM_Msk = 0xc00 + // Position of SPI_SMEM_DIN6_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM_Pos = 0xc + // Bit mask of SPI_SMEM_DIN6_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM_Msk = 0x3000 + // Position of SPI_SMEM_DIN7_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM_Pos = 0xe + // Bit mask of SPI_SMEM_DIN7_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM_Msk = 0xc000 + // Position of SPI_SMEM_DINS_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM_Pos = 0x10 + // Bit mask of SPI_SMEM_DINS_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM_Msk = 0x30000 + + // SPI_SMEM_DOUT_MODE: MSPI external RAM output timing adjustment control register + // Position of SPI_SMEM_DOUT0_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE_Pos = 0x0 + // Bit mask of SPI_SMEM_DOUT0_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE_Msk = 0x1 + // Bit SPI_SMEM_DOUT0_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE = 0x1 + // Position of SPI_SMEM_DOUT1_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE_Pos = 0x1 + // Bit mask of SPI_SMEM_DOUT1_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE_Msk = 0x2 + // Bit SPI_SMEM_DOUT1_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE = 0x2 + // Position of SPI_SMEM_DOUT2_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE_Pos = 0x2 + // Bit mask of SPI_SMEM_DOUT2_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE_Msk = 0x4 + // Bit SPI_SMEM_DOUT2_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE = 0x4 + // Position of SPI_SMEM_DOUT3_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE_Pos = 0x3 + // Bit mask of SPI_SMEM_DOUT3_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE_Msk = 0x8 + // Bit SPI_SMEM_DOUT3_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE = 0x8 + // Position of SPI_SMEM_DOUT4_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE_Pos = 0x4 + // Bit mask of SPI_SMEM_DOUT4_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE_Msk = 0x10 + // Bit SPI_SMEM_DOUT4_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE = 0x10 + // Position of SPI_SMEM_DOUT5_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE_Pos = 0x5 + // Bit mask of SPI_SMEM_DOUT5_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE_Msk = 0x20 + // Bit SPI_SMEM_DOUT5_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE = 0x20 + // Position of SPI_SMEM_DOUT6_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE_Pos = 0x6 + // Bit mask of SPI_SMEM_DOUT6_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE_Msk = 0x40 + // Bit SPI_SMEM_DOUT6_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE = 0x40 + // Position of SPI_SMEM_DOUT7_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE_Pos = 0x7 + // Bit mask of SPI_SMEM_DOUT7_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE_Msk = 0x80 + // Bit SPI_SMEM_DOUT7_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE = 0x80 + // Position of SPI_SMEM_DOUTS_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE_Pos = 0x8 + // Bit mask of SPI_SMEM_DOUTS_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE_Msk = 0x100 + // Bit SPI_SMEM_DOUTS_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE = 0x100 + + // SPI_SMEM_AC: MSPI external RAM ECC and SPI CS timing control register + // Position of SPI_SMEM_CS_SETUP field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_Pos = 0x0 + // Bit mask of SPI_SMEM_CS_SETUP field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_Msk = 0x1 + // Bit SPI_SMEM_CS_SETUP. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP = 0x1 + // Position of SPI_SMEM_CS_HOLD field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_Pos = 0x1 + // Bit mask of SPI_SMEM_CS_HOLD field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_Msk = 0x2 + // Bit SPI_SMEM_CS_HOLD. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD = 0x2 + // Position of SPI_SMEM_CS_SETUP_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME_Pos = 0x2 + // Bit mask of SPI_SMEM_CS_SETUP_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME_Msk = 0x7c + // Position of SPI_SMEM_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME_Pos = 0x7 + // Bit mask of SPI_SMEM_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME_Msk = 0xf80 + // Position of SPI_SMEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME_Pos = 0xc + // Bit mask of SPI_SMEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME_Msk = 0x7000 + // Position of SPI_SMEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER_Pos = 0xf + // Bit mask of SPI_SMEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER_Msk = 0x8000 + // Bit SPI_SMEM_ECC_SKIP_PAGE_CORNER. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER = 0x8000 + // Position of SPI_SMEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN_Pos = 0x10 + // Bit mask of SPI_SMEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN_Msk = 0x10000 + // Bit SPI_SMEM_ECC_16TO18_BYTE_EN. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN = 0x10000 + // Position of SPI_SMEM_CS_HOLD_DELAY field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY_Pos = 0x19 + // Bit mask of SPI_SMEM_CS_HOLD_DELAY field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY_Msk = 0x7e000000 + // Position of SPI_SMEM_SPLIT_TRANS_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN_Pos = 0x1f + // Bit mask of SPI_SMEM_SPLIT_TRANS_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN_Msk = 0x80000000 + // Bit SPI_SMEM_SPLIT_TRANS_EN. + SPI0_SPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN = 0x80000000 + + // SPI_MEM_CLOCK_GATE: SPI0 clock gate register + // Position of SPI_CLK_EN field. + SPI0_SPI_MEM_CLOCK_GATE_SPI_CLK_EN_Pos = 0x0 + // Bit mask of SPI_CLK_EN field. + SPI0_SPI_MEM_CLOCK_GATE_SPI_CLK_EN_Msk = 0x1 + // Bit SPI_CLK_EN. + SPI0_SPI_MEM_CLOCK_GATE_SPI_CLK_EN = 0x1 + + // SPI_MEM_XTS_PLAIN_BASE: The base address of the memory that stores plaintext in Manual Encryption + // Position of SPI_XTS_PLAIN field. + SPI0_SPI_MEM_XTS_PLAIN_BASE_SPI_XTS_PLAIN_Pos = 0x0 + // Bit mask of SPI_XTS_PLAIN field. + SPI0_SPI_MEM_XTS_PLAIN_BASE_SPI_XTS_PLAIN_Msk = 0xffffffff + + // SPI_MEM_XTS_LINESIZE: Manual Encryption Line-Size register + // Position of SPI_XTS_LINESIZE field. + SPI0_SPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE_Pos = 0x0 + // Bit mask of SPI_XTS_LINESIZE field. + SPI0_SPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE_Msk = 0x3 + + // SPI_MEM_XTS_DESTINATION: Manual Encryption destination register + // Position of SPI_XTS_DESTINATION field. + SPI0_SPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION_Pos = 0x0 + // Bit mask of SPI_XTS_DESTINATION field. + SPI0_SPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION_Msk = 0x1 + // Bit SPI_XTS_DESTINATION. + SPI0_SPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION = 0x1 + + // SPI_MEM_XTS_PHYSICAL_ADDRESS: Manual Encryption physical address register + // Position of SPI_XTS_PHYSICAL_ADDRESS field. + SPI0_SPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS_Pos = 0x0 + // Bit mask of SPI_XTS_PHYSICAL_ADDRESS field. + SPI0_SPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS_Msk = 0x3ffffff + + // SPI_MEM_XTS_TRIGGER: Manual Encryption physical address register + // Position of SPI_XTS_TRIGGER field. + SPI0_SPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER_Pos = 0x0 + // Bit mask of SPI_XTS_TRIGGER field. + SPI0_SPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER_Msk = 0x1 + // Bit SPI_XTS_TRIGGER. + SPI0_SPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER = 0x1 + + // SPI_MEM_XTS_RELEASE: Manual Encryption physical address register + // Position of SPI_XTS_RELEASE field. + SPI0_SPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE_Pos = 0x0 + // Bit mask of SPI_XTS_RELEASE field. + SPI0_SPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE_Msk = 0x1 + // Bit SPI_XTS_RELEASE. + SPI0_SPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE = 0x1 + + // SPI_MEM_XTS_DESTROY: Manual Encryption physical address register + // Position of SPI_XTS_DESTROY field. + SPI0_SPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY_Pos = 0x0 + // Bit mask of SPI_XTS_DESTROY field. + SPI0_SPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY_Msk = 0x1 + // Bit SPI_XTS_DESTROY. + SPI0_SPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY = 0x1 + + // SPI_MEM_XTS_STATE: Manual Encryption physical address register + // Position of SPI_XTS_STATE field. + SPI0_SPI_MEM_XTS_STATE_SPI_XTS_STATE_Pos = 0x0 + // Bit mask of SPI_XTS_STATE field. + SPI0_SPI_MEM_XTS_STATE_SPI_XTS_STATE_Msk = 0x3 + + // SPI_MEM_XTS_DATE: Manual Encryption version register + // Position of SPI_XTS_DATE field. + SPI0_SPI_MEM_XTS_DATE_SPI_XTS_DATE_Pos = 0x0 + // Bit mask of SPI_XTS_DATE field. + SPI0_SPI_MEM_XTS_DATE_SPI_XTS_DATE_Msk = 0x3fffffff + + // SPI_MEM_MMU_ITEM_CONTENT: MSPI-MMU item content register + // Position of SPI_MMU_ITEM_CONTENT field. + SPI0_SPI_MEM_MMU_ITEM_CONTENT_SPI_MMU_ITEM_CONTENT_Pos = 0x0 + // Bit mask of SPI_MMU_ITEM_CONTENT field. + SPI0_SPI_MEM_MMU_ITEM_CONTENT_SPI_MMU_ITEM_CONTENT_Msk = 0xffffffff + + // SPI_MEM_MMU_ITEM_INDEX: MSPI-MMU item index register + // Position of SPI_MMU_ITEM_INDEX field. + SPI0_SPI_MEM_MMU_ITEM_INDEX_SPI_MMU_ITEM_INDEX_Pos = 0x0 + // Bit mask of SPI_MMU_ITEM_INDEX field. + SPI0_SPI_MEM_MMU_ITEM_INDEX_SPI_MMU_ITEM_INDEX_Msk = 0xffffffff + + // SPI_MEM_MMU_POWER_CTRL: MSPI MMU power control register + // Position of SPI_MMU_MEM_FORCE_ON field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of SPI_MMU_MEM_FORCE_ON field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON_Msk = 0x1 + // Bit SPI_MMU_MEM_FORCE_ON. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON = 0x1 + // Position of SPI_MMU_MEM_FORCE_PD field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of SPI_MMU_MEM_FORCE_PD field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD_Msk = 0x2 + // Bit SPI_MMU_MEM_FORCE_PD. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD = 0x2 + // Position of SPI_MMU_MEM_FORCE_PU field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of SPI_MMU_MEM_FORCE_PU field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU_Msk = 0x4 + // Bit SPI_MMU_MEM_FORCE_PU. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU = 0x4 + // Position of SPI_MMU_PAGE_SIZE field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_PAGE_SIZE_Pos = 0x3 + // Bit mask of SPI_MMU_PAGE_SIZE field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_PAGE_SIZE_Msk = 0x18 + // Position of SPI_MEM_AUX_CTRL field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL_Pos = 0x10 + // Bit mask of SPI_MEM_AUX_CTRL field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL_Msk = 0x3fff0000 + // Position of SPI_MEM_RDN_ENA field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA_Pos = 0x1e + // Bit mask of SPI_MEM_RDN_ENA field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA_Msk = 0x40000000 + // Bit SPI_MEM_RDN_ENA. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA = 0x40000000 + // Position of SPI_MEM_RDN_RESULT field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT_Pos = 0x1f + // Bit mask of SPI_MEM_RDN_RESULT field. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT_Msk = 0x80000000 + // Bit SPI_MEM_RDN_RESULT. + SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT = 0x80000000 + + // SPI_MEM_DPA_CTRL: SPI memory cryption DPA register + // Position of SPI_CRYPT_SECURITY_LEVEL field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL_Pos = 0x0 + // Bit mask of SPI_CRYPT_SECURITY_LEVEL field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL_Msk = 0x7 + // Position of SPI_CRYPT_CALC_D_DPA_EN field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN_Pos = 0x3 + // Bit mask of SPI_CRYPT_CALC_D_DPA_EN field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN_Msk = 0x8 + // Bit SPI_CRYPT_CALC_D_DPA_EN. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN = 0x8 + // Position of SPI_CRYPT_DPA_SELECT_REGISTER field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER_Pos = 0x4 + // Bit mask of SPI_CRYPT_DPA_SELECT_REGISTER field. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER_Msk = 0x10 + // Bit SPI_CRYPT_DPA_SELECT_REGISTER. + SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER = 0x10 + + // SPI_MEM_REGISTERRND_ECO_HIGH: MSPI ECO high register + // Position of SPI_MEM_REGISTERRND_ECO_HIGH field. + SPI0_SPI_MEM_REGISTERRND_ECO_HIGH_SPI_MEM_REGISTERRND_ECO_HIGH_Pos = 0x0 + // Bit mask of SPI_MEM_REGISTERRND_ECO_HIGH field. + SPI0_SPI_MEM_REGISTERRND_ECO_HIGH_SPI_MEM_REGISTERRND_ECO_HIGH_Msk = 0xffffffff + + // SPI_MEM_REGISTERRND_ECO_LOW: MSPI ECO low register + // Position of SPI_MEM_REGISTERRND_ECO_LOW field. + SPI0_SPI_MEM_REGISTERRND_ECO_LOW_SPI_MEM_REGISTERRND_ECO_LOW_Pos = 0x0 + // Bit mask of SPI_MEM_REGISTERRND_ECO_LOW field. + SPI0_SPI_MEM_REGISTERRND_ECO_LOW_SPI_MEM_REGISTERRND_ECO_LOW_Msk = 0xffffffff + + // SPI_MEM_DATE: SPI0 version control register + // Position of SPI_MEM_DATE field. + SPI0_SPI_MEM_DATE_SPI_MEM_DATE_Pos = 0x0 + // Bit mask of SPI_MEM_DATE field. + SPI0_SPI_MEM_DATE_SPI_MEM_DATE_Msk = 0xfffffff +) + +// Constants for SPI1: SPI (Serial Peripheral Interface) Controller 1 +const ( + // SPI_MEM_CMD: SPI1 memory command register + // Position of SPI_MEM_MST_ST field. + SPI1_SPI_MEM_CMD_SPI_MEM_MST_ST_Pos = 0x0 + // Bit mask of SPI_MEM_MST_ST field. + SPI1_SPI_MEM_CMD_SPI_MEM_MST_ST_Msk = 0xf + // Position of SPI_MEM_SLV_ST field. + SPI1_SPI_MEM_CMD_SPI_MEM_SLV_ST_Pos = 0x4 + // Bit mask of SPI_MEM_SLV_ST field. + SPI1_SPI_MEM_CMD_SPI_MEM_SLV_ST_Msk = 0xf0 + // Position of SPI_MEM_FLASH_PE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PE_Pos = 0x11 + // Bit mask of SPI_MEM_FLASH_PE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PE_Msk = 0x20000 + // Bit SPI_MEM_FLASH_PE. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PE = 0x20000 + // Position of SPI_MEM_USR field. + SPI1_SPI_MEM_CMD_SPI_MEM_USR_Pos = 0x12 + // Bit mask of SPI_MEM_USR field. + SPI1_SPI_MEM_CMD_SPI_MEM_USR_Msk = 0x40000 + // Bit SPI_MEM_USR. + SPI1_SPI_MEM_CMD_SPI_MEM_USR = 0x40000 + // Position of SPI_MEM_FLASH_HPM field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_HPM_Pos = 0x13 + // Bit mask of SPI_MEM_FLASH_HPM field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_HPM_Msk = 0x80000 + // Bit SPI_MEM_FLASH_HPM. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_HPM = 0x80000 + // Position of SPI_MEM_FLASH_RES field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RES_Pos = 0x14 + // Bit mask of SPI_MEM_FLASH_RES field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RES_Msk = 0x100000 + // Bit SPI_MEM_FLASH_RES. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RES = 0x100000 + // Position of SPI_MEM_FLASH_DP field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_DP_Pos = 0x15 + // Bit mask of SPI_MEM_FLASH_DP field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_DP_Msk = 0x200000 + // Bit SPI_MEM_FLASH_DP. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_DP = 0x200000 + // Position of SPI_MEM_FLASH_CE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_CE_Pos = 0x16 + // Bit mask of SPI_MEM_FLASH_CE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_CE_Msk = 0x400000 + // Bit SPI_MEM_FLASH_CE. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_CE = 0x400000 + // Position of SPI_MEM_FLASH_BE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_BE_Pos = 0x17 + // Bit mask of SPI_MEM_FLASH_BE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_BE_Msk = 0x800000 + // Bit SPI_MEM_FLASH_BE. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_BE = 0x800000 + // Position of SPI_MEM_FLASH_SE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_SE_Pos = 0x18 + // Bit mask of SPI_MEM_FLASH_SE field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_SE_Msk = 0x1000000 + // Bit SPI_MEM_FLASH_SE. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_SE = 0x1000000 + // Position of SPI_MEM_FLASH_PP field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PP_Pos = 0x19 + // Bit mask of SPI_MEM_FLASH_PP field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PP_Msk = 0x2000000 + // Bit SPI_MEM_FLASH_PP. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PP = 0x2000000 + // Position of SPI_MEM_FLASH_WRSR field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRSR_Pos = 0x1a + // Bit mask of SPI_MEM_FLASH_WRSR field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRSR_Msk = 0x4000000 + // Bit SPI_MEM_FLASH_WRSR. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRSR = 0x4000000 + // Position of SPI_MEM_FLASH_RDSR field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDSR_Pos = 0x1b + // Bit mask of SPI_MEM_FLASH_RDSR field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDSR_Msk = 0x8000000 + // Bit SPI_MEM_FLASH_RDSR. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDSR = 0x8000000 + // Position of SPI_MEM_FLASH_RDID field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDID_Pos = 0x1c + // Bit mask of SPI_MEM_FLASH_RDID field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDID_Msk = 0x10000000 + // Bit SPI_MEM_FLASH_RDID. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDID = 0x10000000 + // Position of SPI_MEM_FLASH_WRDI field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRDI_Pos = 0x1d + // Bit mask of SPI_MEM_FLASH_WRDI field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRDI_Msk = 0x20000000 + // Bit SPI_MEM_FLASH_WRDI. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRDI = 0x20000000 + // Position of SPI_MEM_FLASH_WREN field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WREN_Pos = 0x1e + // Bit mask of SPI_MEM_FLASH_WREN field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WREN_Msk = 0x40000000 + // Bit SPI_MEM_FLASH_WREN. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WREN = 0x40000000 + // Position of SPI_MEM_FLASH_READ field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_READ_Pos = 0x1f + // Bit mask of SPI_MEM_FLASH_READ field. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_READ_Msk = 0x80000000 + // Bit SPI_MEM_FLASH_READ. + SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_READ = 0x80000000 + + // SPI_MEM_ADDR: SPI1 address register + // Position of SPI_MEM_USR_ADDR_VALUE field. + SPI1_SPI_MEM_ADDR_SPI_MEM_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_USR_ADDR_VALUE field. + SPI1_SPI_MEM_ADDR_SPI_MEM_USR_ADDR_VALUE_Msk = 0xffffffff + + // SPI_MEM_CTRL: SPI1 control register. + // Position of SPI_MEM_FDUMMY_RIN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Pos = 0x2 + // Bit mask of SPI_MEM_FDUMMY_RIN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Msk = 0x4 + // Bit SPI_MEM_FDUMMY_RIN. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN = 0x4 + // Position of SPI_MEM_FDUMMY_WOUT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Pos = 0x3 + // Bit mask of SPI_MEM_FDUMMY_WOUT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Msk = 0x8 + // Bit SPI_MEM_FDUMMY_WOUT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT = 0x8 + // Position of SPI_MEM_FDOUT_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Pos = 0x4 + // Bit mask of SPI_MEM_FDOUT_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Msk = 0x10 + // Bit SPI_MEM_FDOUT_OCT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT = 0x10 + // Position of SPI_MEM_FDIN_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Pos = 0x5 + // Bit mask of SPI_MEM_FDIN_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Msk = 0x20 + // Bit SPI_MEM_FDIN_OCT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT = 0x20 + // Position of SPI_MEM_FADDR_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Pos = 0x6 + // Bit mask of SPI_MEM_FADDR_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Msk = 0x40 + // Bit SPI_MEM_FADDR_OCT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT = 0x40 + // Position of SPI_MEM_FCMD_QUAD field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Pos = 0x8 + // Bit mask of SPI_MEM_FCMD_QUAD field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Msk = 0x100 + // Bit SPI_MEM_FCMD_QUAD. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD = 0x100 + // Position of SPI_MEM_FCMD_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Pos = 0x9 + // Bit mask of SPI_MEM_FCMD_OCT field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Msk = 0x200 + // Bit SPI_MEM_FCMD_OCT. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT = 0x200 + // Position of SPI_MEM_FCS_CRC_EN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN_Pos = 0xa + // Bit mask of SPI_MEM_FCS_CRC_EN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN_Msk = 0x400 + // Bit SPI_MEM_FCS_CRC_EN. + SPI1_SPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN = 0x400 + // Position of SPI_MEM_TX_CRC_EN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_TX_CRC_EN_Pos = 0xb + // Bit mask of SPI_MEM_TX_CRC_EN field. + SPI1_SPI_MEM_CTRL_SPI_MEM_TX_CRC_EN_Msk = 0x800 + // Bit SPI_MEM_TX_CRC_EN. + SPI1_SPI_MEM_CTRL_SPI_MEM_TX_CRC_EN = 0x800 + // Position of SPI_MEM_FASTRD_MODE field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Pos = 0xd + // Bit mask of SPI_MEM_FASTRD_MODE field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Msk = 0x2000 + // Bit SPI_MEM_FASTRD_MODE. + SPI1_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE = 0x2000 + // Position of SPI_MEM_FREAD_DUAL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Pos = 0xe + // Bit mask of SPI_MEM_FREAD_DUAL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Msk = 0x4000 + // Bit SPI_MEM_FREAD_DUAL. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL = 0x4000 + // Position of SPI_MEM_RESANDRES field. + SPI1_SPI_MEM_CTRL_SPI_MEM_RESANDRES_Pos = 0xf + // Bit mask of SPI_MEM_RESANDRES field. + SPI1_SPI_MEM_CTRL_SPI_MEM_RESANDRES_Msk = 0x8000 + // Bit SPI_MEM_RESANDRES. + SPI1_SPI_MEM_CTRL_SPI_MEM_RESANDRES = 0x8000 + // Position of SPI_MEM_Q_POL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_Q_POL_Pos = 0x12 + // Bit mask of SPI_MEM_Q_POL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_Q_POL_Msk = 0x40000 + // Bit SPI_MEM_Q_POL. + SPI1_SPI_MEM_CTRL_SPI_MEM_Q_POL = 0x40000 + // Position of SPI_MEM_D_POL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_D_POL_Pos = 0x13 + // Bit mask of SPI_MEM_D_POL field. + SPI1_SPI_MEM_CTRL_SPI_MEM_D_POL_Msk = 0x80000 + // Bit SPI_MEM_D_POL. + SPI1_SPI_MEM_CTRL_SPI_MEM_D_POL = 0x80000 + // Position of SPI_MEM_FREAD_QUAD field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Pos = 0x14 + // Bit mask of SPI_MEM_FREAD_QUAD field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Msk = 0x100000 + // Bit SPI_MEM_FREAD_QUAD. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD = 0x100000 + // Position of SPI_MEM_WP field. + SPI1_SPI_MEM_CTRL_SPI_MEM_WP_Pos = 0x15 + // Bit mask of SPI_MEM_WP field. + SPI1_SPI_MEM_CTRL_SPI_MEM_WP_Msk = 0x200000 + // Bit SPI_MEM_WP. + SPI1_SPI_MEM_CTRL_SPI_MEM_WP = 0x200000 + // Position of SPI_MEM_WRSR_2B field. + SPI1_SPI_MEM_CTRL_SPI_MEM_WRSR_2B_Pos = 0x16 + // Bit mask of SPI_MEM_WRSR_2B field. + SPI1_SPI_MEM_CTRL_SPI_MEM_WRSR_2B_Msk = 0x400000 + // Bit SPI_MEM_WRSR_2B. + SPI1_SPI_MEM_CTRL_SPI_MEM_WRSR_2B = 0x400000 + // Position of SPI_MEM_FREAD_DIO field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Pos = 0x17 + // Bit mask of SPI_MEM_FREAD_DIO field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Msk = 0x800000 + // Bit SPI_MEM_FREAD_DIO. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO = 0x800000 + // Position of SPI_MEM_FREAD_QIO field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Pos = 0x18 + // Bit mask of SPI_MEM_FREAD_QIO field. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Msk = 0x1000000 + // Bit SPI_MEM_FREAD_QIO. + SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO = 0x1000000 + + // SPI_MEM_CTRL1: SPI1 control1 register. + // Position of SPI_MEM_CLK_MODE field. + SPI1_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Pos = 0x0 + // Bit mask of SPI_MEM_CLK_MODE field. + SPI1_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Msk = 0x3 + // Position of SPI_MEM_CS_HOLD_DLY_RES field. + SPI1_SPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES_Pos = 0x2 + // Bit mask of SPI_MEM_CS_HOLD_DLY_RES field. + SPI1_SPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES_Msk = 0xffc + + // SPI_MEM_CTRL2: SPI1 control2 register. + // Position of SPI_MEM_SYNC_RESET field. + SPI1_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Pos = 0x1f + // Bit mask of SPI_MEM_SYNC_RESET field. + SPI1_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Msk = 0x80000000 + // Bit SPI_MEM_SYNC_RESET. + SPI1_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET = 0x80000000 + + // SPI_MEM_CLOCK: SPI1 clock division control register. + // Position of SPI_MEM_CLKCNT_L field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Pos = 0x0 + // Bit mask of SPI_MEM_CLKCNT_L field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Msk = 0xff + // Position of SPI_MEM_CLKCNT_H field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Pos = 0x8 + // Bit mask of SPI_MEM_CLKCNT_H field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Msk = 0xff00 + // Position of SPI_MEM_CLKCNT_N field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Pos = 0x10 + // Bit mask of SPI_MEM_CLKCNT_N field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Msk = 0xff0000 + // Position of SPI_MEM_CLK_EQU_SYSCLK field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of SPI_MEM_CLK_EQU_SYSCLK field. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit SPI_MEM_CLK_EQU_SYSCLK. + SPI1_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK = 0x80000000 + + // SPI_MEM_USER: SPI1 user register. + // Position of SPI_MEM_CK_OUT_EDGE field. + SPI1_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of SPI_MEM_CK_OUT_EDGE field. + SPI1_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Msk = 0x200 + // Bit SPI_MEM_CK_OUT_EDGE. + SPI1_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE = 0x200 + // Position of SPI_MEM_FWRITE_DUAL field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DUAL_Pos = 0xc + // Bit mask of SPI_MEM_FWRITE_DUAL field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DUAL_Msk = 0x1000 + // Bit SPI_MEM_FWRITE_DUAL. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DUAL = 0x1000 + // Position of SPI_MEM_FWRITE_QUAD field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QUAD_Pos = 0xd + // Bit mask of SPI_MEM_FWRITE_QUAD field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QUAD_Msk = 0x2000 + // Bit SPI_MEM_FWRITE_QUAD. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QUAD = 0x2000 + // Position of SPI_MEM_FWRITE_DIO field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DIO_Pos = 0xe + // Bit mask of SPI_MEM_FWRITE_DIO field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DIO_Msk = 0x4000 + // Bit SPI_MEM_FWRITE_DIO. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DIO = 0x4000 + // Position of SPI_MEM_FWRITE_QIO field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QIO_Pos = 0xf + // Bit mask of SPI_MEM_FWRITE_QIO field. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QIO_Msk = 0x8000 + // Bit SPI_MEM_FWRITE_QIO. + SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QIO = 0x8000 + // Position of SPI_MEM_USR_MISO_HIGHPART field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of SPI_MEM_USR_MISO_HIGHPART field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit SPI_MEM_USR_MISO_HIGHPART. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART = 0x1000000 + // Position of SPI_MEM_USR_MOSI_HIGHPART field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of SPI_MEM_USR_MOSI_HIGHPART field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit SPI_MEM_USR_MOSI_HIGHPART. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART = 0x2000000 + // Position of SPI_MEM_USR_DUMMY_IDLE field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of SPI_MEM_USR_DUMMY_IDLE field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit SPI_MEM_USR_DUMMY_IDLE. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE = 0x4000000 + // Position of SPI_MEM_USR_MOSI field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_Pos = 0x1b + // Bit mask of SPI_MEM_USR_MOSI field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_Msk = 0x8000000 + // Bit SPI_MEM_USR_MOSI. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI = 0x8000000 + // Position of SPI_MEM_USR_MISO field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_Pos = 0x1c + // Bit mask of SPI_MEM_USR_MISO field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_Msk = 0x10000000 + // Bit SPI_MEM_USR_MISO. + SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO = 0x10000000 + // Position of SPI_MEM_USR_DUMMY field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Pos = 0x1d + // Bit mask of SPI_MEM_USR_DUMMY field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Msk = 0x20000000 + // Bit SPI_MEM_USR_DUMMY. + SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY = 0x20000000 + // Position of SPI_MEM_USR_ADDR field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_ADDR_Pos = 0x1e + // Bit mask of SPI_MEM_USR_ADDR field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_ADDR_Msk = 0x40000000 + // Bit SPI_MEM_USR_ADDR. + SPI1_SPI_MEM_USER_SPI_MEM_USR_ADDR = 0x40000000 + // Position of SPI_MEM_USR_COMMAND field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_COMMAND_Pos = 0x1f + // Bit mask of SPI_MEM_USR_COMMAND field. + SPI1_SPI_MEM_USER_SPI_MEM_USR_COMMAND_Msk = 0x80000000 + // Bit SPI_MEM_USR_COMMAND. + SPI1_SPI_MEM_USER_SPI_MEM_USR_COMMAND = 0x80000000 + + // SPI_MEM_USER1: SPI1 user1 register. + // Position of SPI_MEM_USR_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of SPI_MEM_USR_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of SPI_MEM_USR_ADDR_BITLEN field. + SPI1_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of SPI_MEM_USR_ADDR_BITLEN field. + SPI1_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // SPI_MEM_USER2: SPI1 user2 register. + // Position of SPI_MEM_USR_COMMAND_VALUE field. + SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of SPI_MEM_USR_COMMAND_VALUE field. + SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Msk = 0xffff + // Position of SPI_MEM_USR_COMMAND_BITLEN field. + SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of SPI_MEM_USR_COMMAND_BITLEN field. + SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // SPI_MEM_MOSI_DLEN: SPI1 send data bit length control register. + // Position of SPI_MEM_USR_MOSI_DBITLEN field. + SPI1_SPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN_Pos = 0x0 + // Bit mask of SPI_MEM_USR_MOSI_DBITLEN field. + SPI1_SPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN_Msk = 0x3ff + + // SPI_MEM_MISO_DLEN: SPI1 receive data bit length control register. + // Position of SPI_MEM_USR_MISO_DBITLEN field. + SPI1_SPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN_Pos = 0x0 + // Bit mask of SPI_MEM_USR_MISO_DBITLEN field. + SPI1_SPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN_Msk = 0x3ff + + // SPI_MEM_RD_STATUS: SPI1 status register. + // Position of SPI_MEM_STATUS field. + SPI1_SPI_MEM_RD_STATUS_SPI_MEM_STATUS_Pos = 0x0 + // Bit mask of SPI_MEM_STATUS field. + SPI1_SPI_MEM_RD_STATUS_SPI_MEM_STATUS_Msk = 0xffff + // Position of SPI_MEM_WB_MODE field. + SPI1_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Pos = 0x10 + // Bit mask of SPI_MEM_WB_MODE field. + SPI1_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Msk = 0xff0000 + + // SPI_MEM_MISC: SPI1 misc register + // Position of SPI_MEM_CS0_DIS field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS0_DIS_Pos = 0x0 + // Bit mask of SPI_MEM_CS0_DIS field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS0_DIS_Msk = 0x1 + // Bit SPI_MEM_CS0_DIS. + SPI1_SPI_MEM_MISC_SPI_MEM_CS0_DIS = 0x1 + // Position of SPI_MEM_CS1_DIS field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS1_DIS_Pos = 0x1 + // Bit mask of SPI_MEM_CS1_DIS field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS1_DIS_Msk = 0x2 + // Bit SPI_MEM_CS1_DIS. + SPI1_SPI_MEM_MISC_SPI_MEM_CS1_DIS = 0x2 + // Position of SPI_MEM_CK_IDLE_EDGE field. + SPI1_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of SPI_MEM_CK_IDLE_EDGE field. + SPI1_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Msk = 0x200 + // Bit SPI_MEM_CK_IDLE_EDGE. + SPI1_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE = 0x200 + // Position of SPI_MEM_CS_KEEP_ACTIVE field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of SPI_MEM_CS_KEEP_ACTIVE field. + SPI1_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit SPI_MEM_CS_KEEP_ACTIVE. + SPI1_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE = 0x400 + + // SPI_MEM_TX_CRC: SPI1 TX CRC data register. + // Position of DATA field. + SPI1_SPI_MEM_TX_CRC_DATA_Pos = 0x0 + // Bit mask of DATA field. + SPI1_SPI_MEM_TX_CRC_DATA_Msk = 0xffffffff + + // SPI_MEM_CACHE_FCTRL: SPI1 bit mode control register. + // Position of SPI_MEM_CACHE_USR_ADDR_4BYTE field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Pos = 0x1 + // Bit mask of SPI_MEM_CACHE_USR_ADDR_4BYTE field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Msk = 0x2 + // Bit SPI_MEM_CACHE_USR_ADDR_4BYTE. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE = 0x2 + // Position of SPI_MEM_FDIN_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Pos = 0x3 + // Bit mask of SPI_MEM_FDIN_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Msk = 0x8 + // Bit SPI_MEM_FDIN_DUAL. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL = 0x8 + // Position of SPI_MEM_FDOUT_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Pos = 0x4 + // Bit mask of SPI_MEM_FDOUT_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Msk = 0x10 + // Bit SPI_MEM_FDOUT_DUAL. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL = 0x10 + // Position of SPI_MEM_FADDR_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Pos = 0x5 + // Bit mask of SPI_MEM_FADDR_DUAL field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Msk = 0x20 + // Bit SPI_MEM_FADDR_DUAL. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL = 0x20 + // Position of SPI_MEM_FDIN_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Pos = 0x6 + // Bit mask of SPI_MEM_FDIN_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Msk = 0x40 + // Bit SPI_MEM_FDIN_QUAD. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD = 0x40 + // Position of SPI_MEM_FDOUT_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Pos = 0x7 + // Bit mask of SPI_MEM_FDOUT_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Msk = 0x80 + // Bit SPI_MEM_FDOUT_QUAD. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD = 0x80 + // Position of SPI_MEM_FADDR_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Pos = 0x8 + // Bit mask of SPI_MEM_FADDR_QUAD field. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Msk = 0x100 + // Bit SPI_MEM_FADDR_QUAD. + SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD = 0x100 + + // SPI_MEM_W0: SPI1 memory data buffer0 + // Position of SPI_MEM_BUF0 field. + SPI1_SPI_MEM_W0_SPI_MEM_BUF0_Pos = 0x0 + // Bit mask of SPI_MEM_BUF0 field. + SPI1_SPI_MEM_W0_SPI_MEM_BUF0_Msk = 0xffffffff + + // SPI_MEM_W1: SPI1 memory data buffer1 + // Position of SPI_MEM_BUF1 field. + SPI1_SPI_MEM_W1_SPI_MEM_BUF1_Pos = 0x0 + // Bit mask of SPI_MEM_BUF1 field. + SPI1_SPI_MEM_W1_SPI_MEM_BUF1_Msk = 0xffffffff + + // SPI_MEM_W2: SPI1 memory data buffer2 + // Position of SPI_MEM_BUF2 field. + SPI1_SPI_MEM_W2_SPI_MEM_BUF2_Pos = 0x0 + // Bit mask of SPI_MEM_BUF2 field. + SPI1_SPI_MEM_W2_SPI_MEM_BUF2_Msk = 0xffffffff + + // SPI_MEM_W3: SPI1 memory data buffer3 + // Position of SPI_MEM_BUF3 field. + SPI1_SPI_MEM_W3_SPI_MEM_BUF3_Pos = 0x0 + // Bit mask of SPI_MEM_BUF3 field. + SPI1_SPI_MEM_W3_SPI_MEM_BUF3_Msk = 0xffffffff + + // SPI_MEM_W4: SPI1 memory data buffer4 + // Position of SPI_MEM_BUF4 field. + SPI1_SPI_MEM_W4_SPI_MEM_BUF4_Pos = 0x0 + // Bit mask of SPI_MEM_BUF4 field. + SPI1_SPI_MEM_W4_SPI_MEM_BUF4_Msk = 0xffffffff + + // SPI_MEM_W5: SPI1 memory data buffer5 + // Position of SPI_MEM_BUF5 field. + SPI1_SPI_MEM_W5_SPI_MEM_BUF5_Pos = 0x0 + // Bit mask of SPI_MEM_BUF5 field. + SPI1_SPI_MEM_W5_SPI_MEM_BUF5_Msk = 0xffffffff + + // SPI_MEM_W6: SPI1 memory data buffer6 + // Position of SPI_MEM_BUF6 field. + SPI1_SPI_MEM_W6_SPI_MEM_BUF6_Pos = 0x0 + // Bit mask of SPI_MEM_BUF6 field. + SPI1_SPI_MEM_W6_SPI_MEM_BUF6_Msk = 0xffffffff + + // SPI_MEM_W7: SPI1 memory data buffer7 + // Position of SPI_MEM_BUF7 field. + SPI1_SPI_MEM_W7_SPI_MEM_BUF7_Pos = 0x0 + // Bit mask of SPI_MEM_BUF7 field. + SPI1_SPI_MEM_W7_SPI_MEM_BUF7_Msk = 0xffffffff + + // SPI_MEM_W8: SPI1 memory data buffer8 + // Position of SPI_MEM_BUF8 field. + SPI1_SPI_MEM_W8_SPI_MEM_BUF8_Pos = 0x0 + // Bit mask of SPI_MEM_BUF8 field. + SPI1_SPI_MEM_W8_SPI_MEM_BUF8_Msk = 0xffffffff + + // SPI_MEM_W9: SPI1 memory data buffer9 + // Position of SPI_MEM_BUF9 field. + SPI1_SPI_MEM_W9_SPI_MEM_BUF9_Pos = 0x0 + // Bit mask of SPI_MEM_BUF9 field. + SPI1_SPI_MEM_W9_SPI_MEM_BUF9_Msk = 0xffffffff + + // SPI_MEM_W10: SPI1 memory data buffer10 + // Position of SPI_MEM_BUF10 field. + SPI1_SPI_MEM_W10_SPI_MEM_BUF10_Pos = 0x0 + // Bit mask of SPI_MEM_BUF10 field. + SPI1_SPI_MEM_W10_SPI_MEM_BUF10_Msk = 0xffffffff + + // SPI_MEM_W11: SPI1 memory data buffer11 + // Position of SPI_MEM_BUF11 field. + SPI1_SPI_MEM_W11_SPI_MEM_BUF11_Pos = 0x0 + // Bit mask of SPI_MEM_BUF11 field. + SPI1_SPI_MEM_W11_SPI_MEM_BUF11_Msk = 0xffffffff + + // SPI_MEM_W12: SPI1 memory data buffer12 + // Position of SPI_MEM_BUF12 field. + SPI1_SPI_MEM_W12_SPI_MEM_BUF12_Pos = 0x0 + // Bit mask of SPI_MEM_BUF12 field. + SPI1_SPI_MEM_W12_SPI_MEM_BUF12_Msk = 0xffffffff + + // SPI_MEM_W13: SPI1 memory data buffer13 + // Position of SPI_MEM_BUF13 field. + SPI1_SPI_MEM_W13_SPI_MEM_BUF13_Pos = 0x0 + // Bit mask of SPI_MEM_BUF13 field. + SPI1_SPI_MEM_W13_SPI_MEM_BUF13_Msk = 0xffffffff + + // SPI_MEM_W14: SPI1 memory data buffer14 + // Position of SPI_MEM_BUF14 field. + SPI1_SPI_MEM_W14_SPI_MEM_BUF14_Pos = 0x0 + // Bit mask of SPI_MEM_BUF14 field. + SPI1_SPI_MEM_W14_SPI_MEM_BUF14_Msk = 0xffffffff + + // SPI_MEM_W15: SPI1 memory data buffer15 + // Position of SPI_MEM_BUF15 field. + SPI1_SPI_MEM_W15_SPI_MEM_BUF15_Pos = 0x0 + // Bit mask of SPI_MEM_BUF15 field. + SPI1_SPI_MEM_W15_SPI_MEM_BUF15_Msk = 0xffffffff + + // SPI_MEM_FLASH_WAITI_CTRL: SPI1 wait idle control register + // Position of SPI_MEM_WAITI_EN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN_Pos = 0x0 + // Bit mask of SPI_MEM_WAITI_EN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN_Msk = 0x1 + // Bit SPI_MEM_WAITI_EN. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN = 0x1 + // Position of SPI_MEM_WAITI_DUMMY field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_Pos = 0x1 + // Bit mask of SPI_MEM_WAITI_DUMMY field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_Msk = 0x2 + // Bit SPI_MEM_WAITI_DUMMY. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY = 0x2 + // Position of SPI_MEM_WAITI_ADDR_EN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN_Pos = 0x2 + // Bit mask of SPI_MEM_WAITI_ADDR_EN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN_Msk = 0x4 + // Bit SPI_MEM_WAITI_ADDR_EN. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN = 0x4 + // Position of SPI_MEM_WAITI_ADDR_CYCLELEN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN_Pos = 0x3 + // Bit mask of SPI_MEM_WAITI_ADDR_CYCLELEN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN_Msk = 0x18 + // Position of SPI_MEM_WAITI_CMD_2B field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B_Pos = 0x9 + // Bit mask of SPI_MEM_WAITI_CMD_2B field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B_Msk = 0x200 + // Bit SPI_MEM_WAITI_CMD_2B. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B = 0x200 + // Position of SPI_MEM_WAITI_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN_Pos = 0xa + // Bit mask of SPI_MEM_WAITI_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN_Msk = 0xfc00 + // Position of SPI_MEM_WAITI_CMD field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_Pos = 0x10 + // Bit mask of SPI_MEM_WAITI_CMD field. + SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_Msk = 0xffff0000 + + // SPI_MEM_FLASH_SUS_CTRL: SPI1 flash suspend control register + // Position of SPI_MEM_FLASH_PER field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_Pos = 0x0 + // Bit mask of SPI_MEM_FLASH_PER field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_Msk = 0x1 + // Bit SPI_MEM_FLASH_PER. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER = 0x1 + // Position of SPI_MEM_FLASH_PES field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_Pos = 0x1 + // Bit mask of SPI_MEM_FLASH_PES field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_Msk = 0x2 + // Bit SPI_MEM_FLASH_PES. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES = 0x2 + // Position of SPI_MEM_FLASH_PER_WAIT_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN_Pos = 0x2 + // Bit mask of SPI_MEM_FLASH_PER_WAIT_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN_Msk = 0x4 + // Bit SPI_MEM_FLASH_PER_WAIT_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN = 0x4 + // Position of SPI_MEM_FLASH_PES_WAIT_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN_Pos = 0x3 + // Bit mask of SPI_MEM_FLASH_PES_WAIT_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN_Msk = 0x8 + // Bit SPI_MEM_FLASH_PES_WAIT_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN = 0x8 + // Position of SPI_MEM_PES_PER_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN_Pos = 0x4 + // Bit mask of SPI_MEM_PES_PER_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN_Msk = 0x10 + // Bit SPI_MEM_PES_PER_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN = 0x10 + // Position of SPI_MEM_FLASH_PES_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN_Pos = 0x5 + // Bit mask of SPI_MEM_FLASH_PES_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN_Msk = 0x20 + // Bit SPI_MEM_FLASH_PES_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN = 0x20 + // Position of SPI_MEM_PESR_END_MSK field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK_Pos = 0x6 + // Bit mask of SPI_MEM_PESR_END_MSK field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK_Msk = 0x3fffc0 + // Position of SPI_FMEM_RD_SUS_2B field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B_Pos = 0x16 + // Bit mask of SPI_FMEM_RD_SUS_2B field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B_Msk = 0x400000 + // Bit SPI_FMEM_RD_SUS_2B. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B = 0x400000 + // Position of SPI_MEM_PER_END_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN_Pos = 0x17 + // Bit mask of SPI_MEM_PER_END_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN_Msk = 0x800000 + // Bit SPI_MEM_PER_END_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN = 0x800000 + // Position of SPI_MEM_PES_END_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN_Pos = 0x18 + // Bit mask of SPI_MEM_PES_END_EN field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN_Msk = 0x1000000 + // Bit SPI_MEM_PES_END_EN. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN = 0x1000000 + // Position of SPI_MEM_SUS_TIMEOUT_CNT field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT_Pos = 0x19 + // Bit mask of SPI_MEM_SUS_TIMEOUT_CNT field. + SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT_Msk = 0xfe000000 + + // SPI_MEM_FLASH_SUS_CMD: SPI1 flash suspend command register + // Position of SPI_MEM_FLASH_PES_COMMAND field. + SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND_Pos = 0x0 + // Bit mask of SPI_MEM_FLASH_PES_COMMAND field. + SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND_Msk = 0xffff + // Position of SPI_MEM_WAIT_PESR_COMMAND field. + SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND_Pos = 0x10 + // Bit mask of SPI_MEM_WAIT_PESR_COMMAND field. + SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND_Msk = 0xffff0000 + + // SPI_MEM_SUS_STATUS: SPI1 flash suspend status register + // Position of SPI_MEM_FLASH_SUS field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS_Pos = 0x0 + // Bit mask of SPI_MEM_FLASH_SUS field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS_Msk = 0x1 + // Bit SPI_MEM_FLASH_SUS. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS = 0x1 + // Position of SPI_MEM_WAIT_PESR_CMD_2B field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B_Pos = 0x1 + // Bit mask of SPI_MEM_WAIT_PESR_CMD_2B field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B_Msk = 0x2 + // Bit SPI_MEM_WAIT_PESR_CMD_2B. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B = 0x2 + // Position of SPI_MEM_FLASH_HPM_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128_Pos = 0x2 + // Bit mask of SPI_MEM_FLASH_HPM_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128_Msk = 0x4 + // Bit SPI_MEM_FLASH_HPM_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128 = 0x4 + // Position of SPI_MEM_FLASH_RES_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128_Pos = 0x3 + // Bit mask of SPI_MEM_FLASH_RES_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128_Msk = 0x8 + // Bit SPI_MEM_FLASH_RES_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128 = 0x8 + // Position of SPI_MEM_FLASH_DP_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128_Pos = 0x4 + // Bit mask of SPI_MEM_FLASH_DP_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128_Msk = 0x10 + // Bit SPI_MEM_FLASH_DP_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128 = 0x10 + // Position of SPI_MEM_FLASH_PER_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128_Pos = 0x5 + // Bit mask of SPI_MEM_FLASH_PER_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128_Msk = 0x20 + // Bit SPI_MEM_FLASH_PER_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128 = 0x20 + // Position of SPI_MEM_FLASH_PES_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128_Pos = 0x6 + // Bit mask of SPI_MEM_FLASH_PES_DLY_128 field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128_Msk = 0x40 + // Bit SPI_MEM_FLASH_PES_DLY_128. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128 = 0x40 + // Position of SPI_MEM_SPI0_LOCK_EN field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN_Pos = 0x7 + // Bit mask of SPI_MEM_SPI0_LOCK_EN field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN_Msk = 0x80 + // Bit SPI_MEM_SPI0_LOCK_EN. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN = 0x80 + // Position of SPI_MEM_FLASH_PESR_CMD_2B field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B_Pos = 0xf + // Bit mask of SPI_MEM_FLASH_PESR_CMD_2B field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B_Msk = 0x8000 + // Bit SPI_MEM_FLASH_PESR_CMD_2B. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B = 0x8000 + // Position of SPI_MEM_FLASH_PER_COMMAND field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND_Pos = 0x10 + // Bit mask of SPI_MEM_FLASH_PER_COMMAND field. + SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND_Msk = 0xffff0000 + + // SPI_MEM_INT_ENA: SPI1 interrupt enable register + // Position of SPI_MEM_PER_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA_Pos = 0x0 + // Bit mask of SPI_MEM_PER_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA_Msk = 0x1 + // Bit SPI_MEM_PER_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA = 0x1 + // Position of SPI_MEM_PES_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA_Pos = 0x1 + // Bit mask of SPI_MEM_PES_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA_Msk = 0x2 + // Bit SPI_MEM_PES_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA = 0x2 + // Position of SPI_MEM_WPE_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA_Pos = 0x2 + // Bit mask of SPI_MEM_WPE_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA_Msk = 0x4 + // Bit SPI_MEM_WPE_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA = 0x4 + // Position of SPI_MEM_SLV_ST_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA = 0x10 + // Position of SPI_MEM_BROWN_OUT_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA_Pos = 0xa + // Bit mask of SPI_MEM_BROWN_OUT_INT_ENA field. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA_Msk = 0x400 + // Bit SPI_MEM_BROWN_OUT_INT_ENA. + SPI1_SPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA = 0x400 + + // SPI_MEM_INT_CLR: SPI1 interrupt clear register + // Position of SPI_MEM_PER_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR_Pos = 0x0 + // Bit mask of SPI_MEM_PER_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR_Msk = 0x1 + // Bit SPI_MEM_PER_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR = 0x1 + // Position of SPI_MEM_PES_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR_Pos = 0x1 + // Bit mask of SPI_MEM_PES_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR_Msk = 0x2 + // Bit SPI_MEM_PES_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR = 0x2 + // Position of SPI_MEM_WPE_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR_Pos = 0x2 + // Bit mask of SPI_MEM_WPE_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR_Msk = 0x4 + // Bit SPI_MEM_WPE_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR = 0x4 + // Position of SPI_MEM_SLV_ST_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR = 0x10 + // Position of SPI_MEM_BROWN_OUT_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR_Pos = 0xa + // Bit mask of SPI_MEM_BROWN_OUT_INT_CLR field. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR_Msk = 0x400 + // Bit SPI_MEM_BROWN_OUT_INT_CLR. + SPI1_SPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR = 0x400 + + // SPI_MEM_INT_RAW: SPI1 interrupt raw register + // Position of SPI_MEM_PER_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW_Pos = 0x0 + // Bit mask of SPI_MEM_PER_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW_Msk = 0x1 + // Bit SPI_MEM_PER_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW = 0x1 + // Position of SPI_MEM_PES_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW_Pos = 0x1 + // Bit mask of SPI_MEM_PES_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW_Msk = 0x2 + // Bit SPI_MEM_PES_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW = 0x2 + // Position of SPI_MEM_WPE_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW_Pos = 0x2 + // Bit mask of SPI_MEM_WPE_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW_Msk = 0x4 + // Bit SPI_MEM_WPE_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW = 0x4 + // Position of SPI_MEM_SLV_ST_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW = 0x10 + // Position of SPI_MEM_BROWN_OUT_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW_Pos = 0xa + // Bit mask of SPI_MEM_BROWN_OUT_INT_RAW field. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW_Msk = 0x400 + // Bit SPI_MEM_BROWN_OUT_INT_RAW. + SPI1_SPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW = 0x400 + + // SPI_MEM_INT_ST: SPI1 interrupt status register + // Position of SPI_MEM_PER_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST_Pos = 0x0 + // Bit mask of SPI_MEM_PER_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST_Msk = 0x1 + // Bit SPI_MEM_PER_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST = 0x1 + // Position of SPI_MEM_PES_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST_Pos = 0x1 + // Bit mask of SPI_MEM_PES_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST_Msk = 0x2 + // Bit SPI_MEM_PES_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST = 0x2 + // Position of SPI_MEM_WPE_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST_Pos = 0x2 + // Bit mask of SPI_MEM_WPE_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST_Msk = 0x4 + // Bit SPI_MEM_WPE_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST = 0x4 + // Position of SPI_MEM_SLV_ST_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Pos = 0x3 + // Bit mask of SPI_MEM_SLV_ST_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Msk = 0x8 + // Bit SPI_MEM_SLV_ST_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST = 0x8 + // Position of SPI_MEM_MST_ST_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Pos = 0x4 + // Bit mask of SPI_MEM_MST_ST_END_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Msk = 0x10 + // Bit SPI_MEM_MST_ST_END_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST = 0x10 + // Position of SPI_MEM_BROWN_OUT_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST_Pos = 0xa + // Bit mask of SPI_MEM_BROWN_OUT_INT_ST field. + SPI1_SPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST_Msk = 0x400 + // Bit SPI_MEM_BROWN_OUT_INT_ST. + SPI1_SPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST = 0x400 + + // SPI_MEM_DDR: SPI1 DDR control register + // Position of SPI_FMEM_DDR_EN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Pos = 0x0 + // Bit mask of SPI_FMEM_DDR_EN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Msk = 0x1 + // Bit SPI_FMEM_DDR_EN. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_EN = 0x1 + // Position of SPI_FMEM_VAR_DUMMY field. + SPI1_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Pos = 0x1 + // Bit mask of SPI_FMEM_VAR_DUMMY field. + SPI1_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Msk = 0x2 + // Bit SPI_FMEM_VAR_DUMMY. + SPI1_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY = 0x2 + // Position of SPI_FMEM_DDR_RDAT_SWP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Pos = 0x2 + // Bit mask of SPI_FMEM_DDR_RDAT_SWP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Msk = 0x4 + // Bit SPI_FMEM_DDR_RDAT_SWP. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP = 0x4 + // Position of SPI_FMEM_DDR_WDAT_SWP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Pos = 0x3 + // Bit mask of SPI_FMEM_DDR_WDAT_SWP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Msk = 0x8 + // Bit SPI_FMEM_DDR_WDAT_SWP. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP = 0x8 + // Position of SPI_FMEM_DDR_CMD_DIS field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Pos = 0x4 + // Bit mask of SPI_FMEM_DDR_CMD_DIS field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Msk = 0x10 + // Bit SPI_FMEM_DDR_CMD_DIS. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS = 0x10 + // Position of SPI_FMEM_OUTMINBYTELEN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Pos = 0x5 + // Bit mask of SPI_FMEM_OUTMINBYTELEN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Msk = 0xfe0 + // Position of SPI_FMEM_USR_DDR_DQS_THD field. + SPI1_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Pos = 0xe + // Bit mask of SPI_FMEM_USR_DDR_DQS_THD field. + SPI1_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Msk = 0x1fc000 + // Position of SPI_FMEM_DDR_DQS_LOOP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Pos = 0x15 + // Bit mask of SPI_FMEM_DDR_DQS_LOOP field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Msk = 0x200000 + // Bit SPI_FMEM_DDR_DQS_LOOP. + SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP = 0x200000 + // Position of SPI_FMEM_CLK_DIFF_EN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Pos = 0x18 + // Bit mask of SPI_FMEM_CLK_DIFF_EN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Msk = 0x1000000 + // Bit SPI_FMEM_CLK_DIFF_EN. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN = 0x1000000 + // Position of SPI_FMEM_DQS_CA_IN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Pos = 0x1a + // Bit mask of SPI_FMEM_DQS_CA_IN field. + SPI1_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Msk = 0x4000000 + // Bit SPI_FMEM_DQS_CA_IN. + SPI1_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN = 0x4000000 + // Position of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b + // Bit mask of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000 + // Bit SPI_FMEM_HYPERBUS_DUMMY_2X. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X = 0x8000000 + // Position of SPI_FMEM_CLK_DIFF_INV field. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Pos = 0x1c + // Bit mask of SPI_FMEM_CLK_DIFF_INV field. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Msk = 0x10000000 + // Bit SPI_FMEM_CLK_DIFF_INV. + SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV = 0x10000000 + // Position of SPI_FMEM_OCTA_RAM_ADDR field. + SPI1_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Pos = 0x1d + // Bit mask of SPI_FMEM_OCTA_RAM_ADDR field. + SPI1_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Msk = 0x20000000 + // Bit SPI_FMEM_OCTA_RAM_ADDR. + SPI1_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR = 0x20000000 + // Position of SPI_FMEM_HYPERBUS_CA field. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Pos = 0x1e + // Bit mask of SPI_FMEM_HYPERBUS_CA field. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Msk = 0x40000000 + // Bit SPI_FMEM_HYPERBUS_CA. + SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA = 0x40000000 + + // SPI_MEM_TIMING_CALI: SPI1 timing control register + // Position of SPI_MEM_TIMING_CALI field. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Pos = 0x1 + // Bit mask of SPI_MEM_TIMING_CALI field. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Msk = 0x2 + // Bit SPI_MEM_TIMING_CALI. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI = 0x2 + // Position of SPI_MEM_EXTRA_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of SPI_MEM_EXTRA_DUMMY_CYCLELEN field. + SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + + // SPI_MEM_CLOCK_GATE: SPI1 clk_gate register + // Position of SPI_MEM_CLK_EN field. + SPI1_SPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN_Pos = 0x0 + // Bit mask of SPI_MEM_CLK_EN field. + SPI1_SPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN_Msk = 0x1 + // Bit SPI_MEM_CLK_EN. + SPI1_SPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN = 0x1 + + // SPI_MEM_DATE: Version control register + // Position of SPI_MEM_DATE field. + SPI1_SPI_MEM_DATE_SPI_MEM_DATE_Pos = 0x0 + // Bit mask of SPI_MEM_DATE field. + SPI1_SPI_MEM_DATE_SPI_MEM_DATE_Msk = 0xfffffff +) + +// Constants for SPI2: SPI (Serial Peripheral Interface) Controller 2 +const ( + // CMD: Command control register + // Position of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Pos = 0x0 + // Bit mask of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Msk = 0x3ffff + // Position of UPDATE field. + SPI2_CMD_UPDATE_Pos = 0x17 + // Bit mask of UPDATE field. + SPI2_CMD_UPDATE_Msk = 0x800000 + // Bit UPDATE. + SPI2_CMD_UPDATE = 0x800000 + // Position of USR field. + SPI2_CMD_USR_Pos = 0x18 + // Bit mask of USR field. + SPI2_CMD_USR_Msk = 0x1000000 + // Bit USR. + SPI2_CMD_USR = 0x1000000 + + // ADDR: Address value register + // Position of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Msk = 0xffffffff + + // CTRL: SPI control register + // Position of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Pos = 0x3 + // Bit mask of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Msk = 0x8 + // Bit DUMMY_OUT. + SPI2_CTRL_DUMMY_OUT = 0x8 + // Position of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI2_CTRL_FADDR_DUAL = 0x20 + // Position of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Pos = 0x6 + // Bit mask of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Msk = 0x40 + // Bit FADDR_QUAD. + SPI2_CTRL_FADDR_QUAD = 0x40 + // Position of FADDR_OCT field. + SPI2_CTRL_FADDR_OCT_Pos = 0x7 + // Bit mask of FADDR_OCT field. + SPI2_CTRL_FADDR_OCT_Msk = 0x80 + // Bit FADDR_OCT. + SPI2_CTRL_FADDR_OCT = 0x80 + // Position of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Pos = 0x8 + // Bit mask of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Msk = 0x100 + // Bit FCMD_DUAL. + SPI2_CTRL_FCMD_DUAL = 0x100 + // Position of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Pos = 0x9 + // Bit mask of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Msk = 0x200 + // Bit FCMD_QUAD. + SPI2_CTRL_FCMD_QUAD = 0x200 + // Position of FCMD_OCT field. + SPI2_CTRL_FCMD_OCT_Pos = 0xa + // Bit mask of FCMD_OCT field. + SPI2_CTRL_FCMD_OCT_Msk = 0x400 + // Bit FCMD_OCT. + SPI2_CTRL_FCMD_OCT = 0x400 + // Position of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI2_CTRL_FREAD_DUAL = 0x4000 + // Position of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Pos = 0xf + // Bit mask of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Msk = 0x8000 + // Bit FREAD_QUAD. + SPI2_CTRL_FREAD_QUAD = 0x8000 + // Position of FREAD_OCT field. + SPI2_CTRL_FREAD_OCT_Pos = 0x10 + // Bit mask of FREAD_OCT field. + SPI2_CTRL_FREAD_OCT_Msk = 0x10000 + // Bit FREAD_OCT. + SPI2_CTRL_FREAD_OCT = 0x10000 + // Position of Q_POL field. + SPI2_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI2_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI2_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI2_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI2_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI2_CTRL_D_POL = 0x80000 + // Position of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Pos = 0x14 + // Bit mask of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Msk = 0x100000 + // Bit HOLD_POL. + SPI2_CTRL_HOLD_POL = 0x100000 + // Position of WP_POL field. + SPI2_CTRL_WP_POL_Pos = 0x15 + // Bit mask of WP_POL field. + SPI2_CTRL_WP_POL_Msk = 0x200000 + // Bit WP_POL. + SPI2_CTRL_WP_POL = 0x200000 + // Position of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Pos = 0x17 + // Bit mask of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Msk = 0x1800000 + // Position of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Pos = 0x19 + // Bit mask of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Msk = 0x6000000 + + // CLOCK: SPI clock control register + // Position of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Msk = 0x3f + // Position of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Pos = 0x6 + // Bit mask of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Msk = 0xfc0 + // Position of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Pos = 0xc + // Bit mask of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Msk = 0x3f000 + // Position of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Pos = 0x12 + // Bit mask of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Msk = 0x3c0000 + // Position of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI2_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI USER control register + // Position of DOUTDIN field. + SPI2_USER_DOUTDIN_Pos = 0x0 + // Bit mask of DOUTDIN field. + SPI2_USER_DOUTDIN_Msk = 0x1 + // Bit DOUTDIN. + SPI2_USER_DOUTDIN = 0x1 + // Position of QPI_MODE field. + SPI2_USER_QPI_MODE_Pos = 0x3 + // Bit mask of QPI_MODE field. + SPI2_USER_QPI_MODE_Msk = 0x8 + // Bit QPI_MODE. + SPI2_USER_QPI_MODE = 0x8 + // Position of OPI_MODE field. + SPI2_USER_OPI_MODE_Pos = 0x4 + // Bit mask of OPI_MODE field. + SPI2_USER_OPI_MODE_Msk = 0x10 + // Bit OPI_MODE. + SPI2_USER_OPI_MODE = 0x10 + // Position of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Pos = 0x5 + // Bit mask of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Msk = 0x20 + // Bit TSCK_I_EDGE. + SPI2_USER_TSCK_I_EDGE = 0x20 + // Position of CS_HOLD field. + SPI2_USER_CS_HOLD_Pos = 0x6 + // Bit mask of CS_HOLD field. + SPI2_USER_CS_HOLD_Msk = 0x40 + // Bit CS_HOLD. + SPI2_USER_CS_HOLD = 0x40 + // Position of CS_SETUP field. + SPI2_USER_CS_SETUP_Pos = 0x7 + // Bit mask of CS_SETUP field. + SPI2_USER_CS_SETUP_Msk = 0x80 + // Bit CS_SETUP. + SPI2_USER_CS_SETUP = 0x80 + // Position of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Pos = 0x8 + // Bit mask of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Msk = 0x100 + // Bit RSCK_I_EDGE. + SPI2_USER_RSCK_I_EDGE = 0x100 + // Position of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI2_USER_CK_OUT_EDGE = 0x200 + // Position of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI2_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI2_USER_FWRITE_QUAD = 0x2000 + // Position of FWRITE_OCT field. + SPI2_USER_FWRITE_OCT_Pos = 0xe + // Bit mask of FWRITE_OCT field. + SPI2_USER_FWRITE_OCT_Msk = 0x4000 + // Bit FWRITE_OCT. + SPI2_USER_FWRITE_OCT = 0x4000 + // Position of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Pos = 0xf + // Bit mask of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Msk = 0x8000 + // Bit USR_CONF_NXT. + SPI2_USER_USR_CONF_NXT = 0x8000 + // Position of SIO field. + SPI2_USER_SIO_Pos = 0x11 + // Bit mask of SIO field. + SPI2_USER_SIO_Msk = 0x20000 + // Bit SIO. + SPI2_USER_SIO = 0x20000 + // Position of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI2_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI2_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI2_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI2_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI2_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI2_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI2_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI2_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI2_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI2_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI2_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI2_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI2_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI2_USER_USR_COMMAND = 0x80000000 + + // USER1: SPI USER control register 1 + // Position of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Msk = 0xff + // Position of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Pos = 0x10 + // Bit mask of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Msk = 0x10000 + // Bit MST_WFULL_ERR_END_EN. + SPI2_USER1_MST_WFULL_ERR_END_EN = 0x10000 + // Position of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Pos = 0x11 + // Bit mask of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Msk = 0x3e0000 + // Position of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Pos = 0x16 + // Bit mask of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Msk = 0x7c00000 + // Position of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Pos = 0x1b + // Bit mask of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Msk = 0xf8000000 + + // USER2: SPI USER control register 2 + // Position of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Pos = 0x1b + // Bit mask of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Msk = 0x8000000 + // Bit MST_REMPTY_ERR_END_EN. + SPI2_USER2_MST_REMPTY_ERR_END_EN = 0x8000000 + // Position of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MS_DLEN: SPI data bit length control register + // Position of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Pos = 0x0 + // Bit mask of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Msk = 0x3ffff + + // MISC: SPI misc register + // Position of CS0_DIS field. + SPI2_MISC_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI2_MISC_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI2_MISC_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI2_MISC_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI2_MISC_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI2_MISC_CS1_DIS = 0x2 + // Position of CS2_DIS field. + SPI2_MISC_CS2_DIS_Pos = 0x2 + // Bit mask of CS2_DIS field. + SPI2_MISC_CS2_DIS_Msk = 0x4 + // Bit CS2_DIS. + SPI2_MISC_CS2_DIS = 0x4 + // Position of CS3_DIS field. + SPI2_MISC_CS3_DIS_Pos = 0x3 + // Bit mask of CS3_DIS field. + SPI2_MISC_CS3_DIS_Msk = 0x8 + // Bit CS3_DIS. + SPI2_MISC_CS3_DIS = 0x8 + // Position of CS4_DIS field. + SPI2_MISC_CS4_DIS_Pos = 0x4 + // Bit mask of CS4_DIS field. + SPI2_MISC_CS4_DIS_Msk = 0x10 + // Bit CS4_DIS. + SPI2_MISC_CS4_DIS = 0x10 + // Position of CS5_DIS field. + SPI2_MISC_CS5_DIS_Pos = 0x5 + // Bit mask of CS5_DIS field. + SPI2_MISC_CS5_DIS_Msk = 0x20 + // Bit CS5_DIS. + SPI2_MISC_CS5_DIS = 0x20 + // Position of CK_DIS field. + SPI2_MISC_CK_DIS_Pos = 0x6 + // Bit mask of CK_DIS field. + SPI2_MISC_CK_DIS_Msk = 0x40 + // Bit CK_DIS. + SPI2_MISC_CK_DIS = 0x40 + // Position of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Pos = 0x7 + // Bit mask of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Msk = 0x1f80 + // Position of CLK_DATA_DTR_EN field. + SPI2_MISC_CLK_DATA_DTR_EN_Pos = 0x10 + // Bit mask of CLK_DATA_DTR_EN field. + SPI2_MISC_CLK_DATA_DTR_EN_Msk = 0x10000 + // Bit CLK_DATA_DTR_EN. + SPI2_MISC_CLK_DATA_DTR_EN = 0x10000 + // Position of DATA_DTR_EN field. + SPI2_MISC_DATA_DTR_EN_Pos = 0x11 + // Bit mask of DATA_DTR_EN field. + SPI2_MISC_DATA_DTR_EN_Msk = 0x20000 + // Bit DATA_DTR_EN. + SPI2_MISC_DATA_DTR_EN = 0x20000 + // Position of ADDR_DTR_EN field. + SPI2_MISC_ADDR_DTR_EN_Pos = 0x12 + // Bit mask of ADDR_DTR_EN field. + SPI2_MISC_ADDR_DTR_EN_Msk = 0x40000 + // Bit ADDR_DTR_EN. + SPI2_MISC_ADDR_DTR_EN = 0x40000 + // Position of CMD_DTR_EN field. + SPI2_MISC_CMD_DTR_EN_Pos = 0x13 + // Bit mask of CMD_DTR_EN field. + SPI2_MISC_CMD_DTR_EN_Msk = 0x80000 + // Bit CMD_DTR_EN. + SPI2_MISC_CMD_DTR_EN = 0x80000 + // Position of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Pos = 0x17 + // Bit mask of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Msk = 0x800000 + // Bit SLAVE_CS_POL. + SPI2_MISC_SLAVE_CS_POL = 0x800000 + // Position of DQS_IDLE_EDGE field. + SPI2_MISC_DQS_IDLE_EDGE_Pos = 0x18 + // Bit mask of DQS_IDLE_EDGE field. + SPI2_MISC_DQS_IDLE_EDGE_Msk = 0x1000000 + // Bit DQS_IDLE_EDGE. + SPI2_MISC_DQS_IDLE_EDGE = 0x1000000 + // Position of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Pos = 0x1d + // Bit mask of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Msk = 0x20000000 + // Bit CK_IDLE_EDGE. + SPI2_MISC_CK_IDLE_EDGE = 0x20000000 + // Position of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Pos = 0x1e + // Bit mask of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Msk = 0x40000000 + // Bit CS_KEEP_ACTIVE. + SPI2_MISC_CS_KEEP_ACTIVE = 0x40000000 + // Position of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Pos = 0x1f + // Bit mask of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Msk = 0x80000000 + // Bit QUAD_DIN_PIN_SWAP. + SPI2_MISC_QUAD_DIN_PIN_SWAP = 0x80000000 + + // DIN_MODE: SPI input delay mode configuration + // Position of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Pos = 0x0 + // Bit mask of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Msk = 0x3 + // Position of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Pos = 0x2 + // Bit mask of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Msk = 0xc + // Position of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Pos = 0x4 + // Bit mask of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Msk = 0x30 + // Position of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Pos = 0x6 + // Bit mask of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Msk = 0xc0 + // Position of DIN4_MODE field. + SPI2_DIN_MODE_DIN4_MODE_Pos = 0x8 + // Bit mask of DIN4_MODE field. + SPI2_DIN_MODE_DIN4_MODE_Msk = 0x300 + // Position of DIN5_MODE field. + SPI2_DIN_MODE_DIN5_MODE_Pos = 0xa + // Bit mask of DIN5_MODE field. + SPI2_DIN_MODE_DIN5_MODE_Msk = 0xc00 + // Position of DIN6_MODE field. + SPI2_DIN_MODE_DIN6_MODE_Pos = 0xc + // Bit mask of DIN6_MODE field. + SPI2_DIN_MODE_DIN6_MODE_Msk = 0x3000 + // Position of DIN7_MODE field. + SPI2_DIN_MODE_DIN7_MODE_Pos = 0xe + // Bit mask of DIN7_MODE field. + SPI2_DIN_MODE_DIN7_MODE_Msk = 0xc000 + // Position of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Pos = 0x10 + // Bit mask of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Msk = 0x10000 + // Bit TIMING_HCLK_ACTIVE. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE = 0x10000 + + // DIN_NUM: SPI input delay number configuration + // Position of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Pos = 0x0 + // Bit mask of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Msk = 0x3 + // Position of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Pos = 0x2 + // Bit mask of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Msk = 0xc + // Position of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Pos = 0x4 + // Bit mask of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Msk = 0x30 + // Position of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Pos = 0x6 + // Bit mask of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Msk = 0xc0 + // Position of DIN4_NUM field. + SPI2_DIN_NUM_DIN4_NUM_Pos = 0x8 + // Bit mask of DIN4_NUM field. + SPI2_DIN_NUM_DIN4_NUM_Msk = 0x300 + // Position of DIN5_NUM field. + SPI2_DIN_NUM_DIN5_NUM_Pos = 0xa + // Bit mask of DIN5_NUM field. + SPI2_DIN_NUM_DIN5_NUM_Msk = 0xc00 + // Position of DIN6_NUM field. + SPI2_DIN_NUM_DIN6_NUM_Pos = 0xc + // Bit mask of DIN6_NUM field. + SPI2_DIN_NUM_DIN6_NUM_Msk = 0x3000 + // Position of DIN7_NUM field. + SPI2_DIN_NUM_DIN7_NUM_Pos = 0xe + // Bit mask of DIN7_NUM field. + SPI2_DIN_NUM_DIN7_NUM_Msk = 0xc000 + + // DOUT_MODE: SPI output delay mode configuration + // Position of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Msk = 0x1 + // Bit DOUT0_MODE. + SPI2_DOUT_MODE_DOUT0_MODE = 0x1 + // Position of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Pos = 0x1 + // Bit mask of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Msk = 0x2 + // Bit DOUT1_MODE. + SPI2_DOUT_MODE_DOUT1_MODE = 0x2 + // Position of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Pos = 0x2 + // Bit mask of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Msk = 0x4 + // Bit DOUT2_MODE. + SPI2_DOUT_MODE_DOUT2_MODE = 0x4 + // Position of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Pos = 0x3 + // Bit mask of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Msk = 0x8 + // Bit DOUT3_MODE. + SPI2_DOUT_MODE_DOUT3_MODE = 0x8 + // Position of DOUT4_MODE field. + SPI2_DOUT_MODE_DOUT4_MODE_Pos = 0x4 + // Bit mask of DOUT4_MODE field. + SPI2_DOUT_MODE_DOUT4_MODE_Msk = 0x10 + // Bit DOUT4_MODE. + SPI2_DOUT_MODE_DOUT4_MODE = 0x10 + // Position of DOUT5_MODE field. + SPI2_DOUT_MODE_DOUT5_MODE_Pos = 0x5 + // Bit mask of DOUT5_MODE field. + SPI2_DOUT_MODE_DOUT5_MODE_Msk = 0x20 + // Bit DOUT5_MODE. + SPI2_DOUT_MODE_DOUT5_MODE = 0x20 + // Position of DOUT6_MODE field. + SPI2_DOUT_MODE_DOUT6_MODE_Pos = 0x6 + // Bit mask of DOUT6_MODE field. + SPI2_DOUT_MODE_DOUT6_MODE_Msk = 0x40 + // Bit DOUT6_MODE. + SPI2_DOUT_MODE_DOUT6_MODE = 0x40 + // Position of DOUT7_MODE field. + SPI2_DOUT_MODE_DOUT7_MODE_Pos = 0x7 + // Bit mask of DOUT7_MODE field. + SPI2_DOUT_MODE_DOUT7_MODE_Msk = 0x80 + // Bit DOUT7_MODE. + SPI2_DOUT_MODE_DOUT7_MODE = 0x80 + // Position of D_DQS_MODE field. + SPI2_DOUT_MODE_D_DQS_MODE_Pos = 0x8 + // Bit mask of D_DQS_MODE field. + SPI2_DOUT_MODE_D_DQS_MODE_Msk = 0x100 + // Bit D_DQS_MODE. + SPI2_DOUT_MODE_D_DQS_MODE = 0x100 + + // DMA_CONF: SPI DMA control register + // Position of DMA_OUTFIFO_EMPTY field. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY_Pos = 0x0 + // Bit mask of DMA_OUTFIFO_EMPTY field. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY_Msk = 0x1 + // Bit DMA_OUTFIFO_EMPTY. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY = 0x1 + // Position of DMA_INFIFO_FULL field. + SPI2_DMA_CONF_DMA_INFIFO_FULL_Pos = 0x1 + // Bit mask of DMA_INFIFO_FULL field. + SPI2_DMA_CONF_DMA_INFIFO_FULL_Msk = 0x2 + // Bit DMA_INFIFO_FULL. + SPI2_DMA_CONF_DMA_INFIFO_FULL = 0x2 + // Position of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Pos = 0x12 + // Bit mask of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Msk = 0x40000 + // Bit DMA_SLV_SEG_TRANS_EN. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN = 0x40000 + // Position of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Pos = 0x13 + // Bit mask of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Msk = 0x80000 + // Bit SLV_RX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN = 0x80000 + // Position of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Pos = 0x14 + // Bit mask of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Msk = 0x100000 + // Bit SLV_TX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN = 0x100000 + // Position of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Pos = 0x15 + // Bit mask of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Msk = 0x200000 + // Bit RX_EOF_EN. + SPI2_DMA_CONF_RX_EOF_EN = 0x200000 + // Position of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Pos = 0x1b + // Bit mask of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Msk = 0x8000000 + // Bit DMA_RX_ENA. + SPI2_DMA_CONF_DMA_RX_ENA = 0x8000000 + // Position of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Pos = 0x1c + // Bit mask of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Msk = 0x10000000 + // Bit DMA_TX_ENA. + SPI2_DMA_CONF_DMA_TX_ENA = 0x10000000 + // Position of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Pos = 0x1d + // Bit mask of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Msk = 0x20000000 + // Bit RX_AFIFO_RST. + SPI2_DMA_CONF_RX_AFIFO_RST = 0x20000000 + // Position of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Pos = 0x1e + // Bit mask of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Msk = 0x40000000 + // Bit BUF_AFIFO_RST. + SPI2_DMA_CONF_BUF_AFIFO_RST = 0x40000000 + // Position of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Pos = 0x1f + // Bit mask of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Msk = 0x80000000 + // Bit DMA_AFIFO_RST. + SPI2_DMA_CONF_DMA_AFIFO_RST = 0x80000000 + + // DMA_INT_ENA: SPI interrupt enable register + // Position of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA = 0x2 + // Position of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA = 0x4 + // Position of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA = 0x8 + // Position of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Msk = 0x10 + // Bit SLV_CMD7_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA = 0x10 + // Position of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Msk = 0x20 + // Bit SLV_CMD8_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA = 0x20 + // Position of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Msk = 0x40 + // Bit SLV_CMD9_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA = 0x40 + // Position of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Msk = 0x80 + // Bit SLV_CMDA_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA = 0x800 + // Position of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Msk = 0x1000 + // Bit TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA = 0x8000 + // Position of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA = 0x40000 + // Position of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Pos = 0x13 + // Bit mask of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Msk = 0x80000 + // Bit APP2_INT_ENA. + SPI2_DMA_INT_ENA_APP2_INT_ENA = 0x80000 + // Position of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Pos = 0x14 + // Bit mask of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Msk = 0x100000 + // Bit APP1_INT_ENA. + SPI2_DMA_INT_ENA_APP1_INT_ENA = 0x100000 + + // DMA_INT_CLR: SPI interrupt clear register + // Position of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR = 0x2 + // Position of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Msk = 0x4 + // Bit SLV_EX_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR = 0x4 + // Position of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Msk = 0x8 + // Bit SLV_EN_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR = 0x8 + // Position of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Msk = 0x10 + // Bit SLV_CMD7_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR = 0x10 + // Position of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Msk = 0x20 + // Bit SLV_CMD8_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR = 0x20 + // Position of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Msk = 0x40 + // Bit SLV_CMD9_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR = 0x40 + // Position of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Msk = 0x80 + // Bit SLV_CMDA_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR = 0x80 + // Position of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR = 0x100 + // Position of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR = 0x200 + // Position of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR = 0x400 + // Position of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR = 0x800 + // Position of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Pos = 0xc + // Bit mask of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Msk = 0x1000 + // Bit TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR = 0x2000 + // Position of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR = 0x8000 + // Position of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR = 0x40000 + // Position of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Pos = 0x13 + // Bit mask of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Msk = 0x80000 + // Bit APP2_INT_CLR. + SPI2_DMA_INT_CLR_APP2_INT_CLR = 0x80000 + // Position of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Pos = 0x14 + // Bit mask of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Msk = 0x100000 + // Bit APP1_INT_CLR. + SPI2_DMA_INT_CLR_APP1_INT_CLR = 0x100000 + + // DMA_INT_RAW: SPI interrupt raw register + // Position of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW = 0x2 + // Position of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Msk = 0x4 + // Bit SLV_EX_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW = 0x4 + // Position of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Msk = 0x8 + // Bit SLV_EN_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW = 0x8 + // Position of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Msk = 0x10 + // Bit SLV_CMD7_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW = 0x10 + // Position of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Msk = 0x20 + // Bit SLV_CMD8_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW = 0x20 + // Position of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Msk = 0x40 + // Bit SLV_CMD9_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW = 0x40 + // Position of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Msk = 0x80 + // Bit SLV_CMDA_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW = 0x80 + // Position of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW = 0x100 + // Position of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW = 0x200 + // Position of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW = 0x400 + // Position of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW = 0x800 + // Position of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Pos = 0xc + // Bit mask of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Msk = 0x1000 + // Bit TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW = 0x2000 + // Position of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW = 0x8000 + // Position of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW = 0x40000 + // Position of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Pos = 0x13 + // Bit mask of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Msk = 0x80000 + // Bit APP2_INT_RAW. + SPI2_DMA_INT_RAW_APP2_INT_RAW = 0x80000 + // Position of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Pos = 0x14 + // Bit mask of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Msk = 0x100000 + // Bit APP1_INT_RAW. + SPI2_DMA_INT_RAW_APP1_INT_RAW = 0x100000 + + // DMA_INT_ST: SPI interrupt status register + // Position of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST = 0x2 + // Position of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST = 0x4 + // Position of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST = 0x8 + // Position of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Msk = 0x10 + // Bit SLV_CMD7_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST = 0x10 + // Position of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Msk = 0x20 + // Bit SLV_CMD8_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST = 0x20 + // Position of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Msk = 0x40 + // Bit SLV_CMD9_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST = 0x40 + // Position of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Msk = 0x80 + // Bit SLV_CMDA_INT_ST. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST = 0x800 + // Position of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Msk = 0x1000 + // Bit TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ST. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST = 0x8000 + // Position of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST = 0x40000 + // Position of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Pos = 0x13 + // Bit mask of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Msk = 0x80000 + // Bit APP2_INT_ST. + SPI2_DMA_INT_ST_APP2_INT_ST = 0x80000 + // Position of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Pos = 0x14 + // Bit mask of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Msk = 0x100000 + // Bit APP1_INT_ST. + SPI2_DMA_INT_ST_APP1_INT_ST = 0x100000 + + // DMA_INT_SET: SPI interrupt software set register + // Position of DMA_INFIFO_FULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_SET. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_SET. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET = 0x2 + // Position of SLV_EX_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET_Msk = 0x4 + // Bit SLV_EX_QPI_INT_SET. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET = 0x4 + // Position of SLV_EN_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET_Msk = 0x8 + // Bit SLV_EN_QPI_INT_SET. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET = 0x8 + // Position of SLV_CMD7_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET_Msk = 0x10 + // Bit SLV_CMD7_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET = 0x10 + // Position of SLV_CMD8_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET_Msk = 0x20 + // Bit SLV_CMD8_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET = 0x20 + // Position of SLV_CMD9_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET_Msk = 0x40 + // Bit SLV_CMD9_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET = 0x40 + // Position of SLV_CMDA_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET_Msk = 0x80 + // Bit SLV_CMDA_INT_SET. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET = 0x80 + // Position of SLV_RD_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET = 0x100 + // Position of SLV_WR_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET = 0x200 + // Position of SLV_RD_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET = 0x400 + // Position of SLV_WR_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET = 0x800 + // Position of TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET_Pos = 0xc + // Bit mask of TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET_Msk = 0x1000 + // Bit TRANS_DONE_INT_SET. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_SET. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET = 0x2000 + // Position of SEG_MAGIC_ERR_INT_SET field. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_SET field. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_SET. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_SET. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET = 0x8000 + // Position of SLV_CMD_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_SET. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_SET. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET = 0x40000 + // Position of APP2_INT_SET field. + SPI2_DMA_INT_SET_APP2_INT_SET_Pos = 0x13 + // Bit mask of APP2_INT_SET field. + SPI2_DMA_INT_SET_APP2_INT_SET_Msk = 0x80000 + // Bit APP2_INT_SET. + SPI2_DMA_INT_SET_APP2_INT_SET = 0x80000 + // Position of APP1_INT_SET field. + SPI2_DMA_INT_SET_APP1_INT_SET_Pos = 0x14 + // Bit mask of APP1_INT_SET field. + SPI2_DMA_INT_SET_APP1_INT_SET_Msk = 0x100000 + // Bit APP1_INT_SET. + SPI2_DMA_INT_SET_APP1_INT_SET = 0x100000 + + // W0: SPI CPU-controlled buffer0 + // Position of BUF0 field. + SPI2_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI2_W0_BUF0_Msk = 0xffffffff + + // W1: SPI CPU-controlled buffer1 + // Position of BUF1 field. + SPI2_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI2_W1_BUF1_Msk = 0xffffffff + + // W2: SPI CPU-controlled buffer2 + // Position of BUF2 field. + SPI2_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI2_W2_BUF2_Msk = 0xffffffff + + // W3: SPI CPU-controlled buffer3 + // Position of BUF3 field. + SPI2_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI2_W3_BUF3_Msk = 0xffffffff + + // W4: SPI CPU-controlled buffer4 + // Position of BUF4 field. + SPI2_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI2_W4_BUF4_Msk = 0xffffffff + + // W5: SPI CPU-controlled buffer5 + // Position of BUF5 field. + SPI2_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI2_W5_BUF5_Msk = 0xffffffff + + // W6: SPI CPU-controlled buffer6 + // Position of BUF6 field. + SPI2_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI2_W6_BUF6_Msk = 0xffffffff + + // W7: SPI CPU-controlled buffer7 + // Position of BUF7 field. + SPI2_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI2_W7_BUF7_Msk = 0xffffffff + + // W8: SPI CPU-controlled buffer8 + // Position of BUF8 field. + SPI2_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI2_W8_BUF8_Msk = 0xffffffff + + // W9: SPI CPU-controlled buffer9 + // Position of BUF9 field. + SPI2_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI2_W9_BUF9_Msk = 0xffffffff + + // W10: SPI CPU-controlled buffer10 + // Position of BUF10 field. + SPI2_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI2_W10_BUF10_Msk = 0xffffffff + + // W11: SPI CPU-controlled buffer11 + // Position of BUF11 field. + SPI2_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI2_W11_BUF11_Msk = 0xffffffff + + // W12: SPI CPU-controlled buffer12 + // Position of BUF12 field. + SPI2_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI2_W12_BUF12_Msk = 0xffffffff + + // W13: SPI CPU-controlled buffer13 + // Position of BUF13 field. + SPI2_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI2_W13_BUF13_Msk = 0xffffffff + + // W14: SPI CPU-controlled buffer14 + // Position of BUF14 field. + SPI2_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI2_W14_BUF14_Msk = 0xffffffff + + // W15: SPI CPU-controlled buffer15 + // Position of BUF15 field. + SPI2_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI2_W15_BUF15_Msk = 0xffffffff + + // SLAVE: SPI slave control register + // Position of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Msk = 0x3 + // Position of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Pos = 0x2 + // Bit mask of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Msk = 0x4 + // Bit CLK_MODE_13. + SPI2_SLAVE_CLK_MODE_13 = 0x4 + // Position of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Pos = 0x3 + // Bit mask of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Msk = 0x8 + // Bit RSCK_DATA_OUT. + SPI2_SLAVE_RSCK_DATA_OUT = 0x8 + // Position of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Pos = 0x8 + // Bit mask of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Msk = 0x100 + // Bit SLV_RDDMA_BITLEN_EN. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN = 0x100 + // Position of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Pos = 0x9 + // Bit mask of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Msk = 0x200 + // Bit SLV_WRDMA_BITLEN_EN. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN = 0x200 + // Position of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Pos = 0xa + // Bit mask of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Msk = 0x400 + // Bit SLV_RDBUF_BITLEN_EN. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN = 0x400 + // Position of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Pos = 0xb + // Bit mask of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Msk = 0x800 + // Bit SLV_WRBUF_BITLEN_EN. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN = 0x800 + // Position of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Pos = 0x16 + // Bit mask of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Msk = 0x3c00000 + // Position of MODE field. + SPI2_SLAVE_MODE_Pos = 0x1a + // Bit mask of MODE field. + SPI2_SLAVE_MODE_Msk = 0x4000000 + // Bit MODE. + SPI2_SLAVE_MODE = 0x4000000 + // Position of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Pos = 0x1b + // Bit mask of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Msk = 0x8000000 + // Bit SOFT_RESET. + SPI2_SLAVE_SOFT_RESET = 0x8000000 + // Position of USR_CONF field. + SPI2_SLAVE_USR_CONF_Pos = 0x1c + // Bit mask of USR_CONF field. + SPI2_SLAVE_USR_CONF_Msk = 0x10000000 + // Bit USR_CONF. + SPI2_SLAVE_USR_CONF = 0x10000000 + // Position of MST_FD_WAIT_DMA_TX_DATA field. + SPI2_SLAVE_MST_FD_WAIT_DMA_TX_DATA_Pos = 0x1d + // Bit mask of MST_FD_WAIT_DMA_TX_DATA field. + SPI2_SLAVE_MST_FD_WAIT_DMA_TX_DATA_Msk = 0x20000000 + // Bit MST_FD_WAIT_DMA_TX_DATA. + SPI2_SLAVE_MST_FD_WAIT_DMA_TX_DATA = 0x20000000 + + // SLAVE1: SPI slave control register 1 + // Position of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Pos = 0x0 + // Bit mask of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Msk = 0x3ffff + // Position of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Pos = 0x12 + // Bit mask of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Msk = 0x3fc0000 + // Position of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Pos = 0x1a + // Bit mask of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Msk = 0xfc000000 + + // CLK_GATE: SPI module clock and register clock control + // Position of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI2_CLK_GATE_CLK_EN = 0x1 + // Position of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Pos = 0x1 + // Bit mask of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Msk = 0x2 + // Bit MST_CLK_ACTIVE. + SPI2_CLK_GATE_MST_CLK_ACTIVE = 0x2 + // Position of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Pos = 0x2 + // Bit mask of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Msk = 0x4 + // Bit MST_CLK_SEL. + SPI2_CLK_GATE_MST_CLK_SEL = 0x4 + + // DATE: Version control + // Position of DATE field. + SPI2_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI2_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SYSTIMER: System Timer +const ( + // CONF: Configure system timer clock + // Position of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Pos = 0x0 + // Bit mask of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Msk = 0x1 + // Bit SYSTIMER_CLK_FO. + SYSTIMER_CONF_SYSTIMER_CLK_FO = 0x1 + // Position of ETM_EN field. + SYSTIMER_CONF_ETM_EN_Pos = 0x1 + // Bit mask of ETM_EN field. + SYSTIMER_CONF_ETM_EN_Msk = 0x2 + // Bit ETM_EN. + SYSTIMER_CONF_ETM_EN = 0x2 + // Position of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Pos = 0x16 + // Bit mask of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Msk = 0x400000 + // Bit TARGET2_WORK_EN. + SYSTIMER_CONF_TARGET2_WORK_EN = 0x400000 + // Position of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Pos = 0x17 + // Bit mask of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Msk = 0x800000 + // Bit TARGET1_WORK_EN. + SYSTIMER_CONF_TARGET1_WORK_EN = 0x800000 + // Position of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Pos = 0x18 + // Bit mask of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Msk = 0x1000000 + // Bit TARGET0_WORK_EN. + SYSTIMER_CONF_TARGET0_WORK_EN = 0x1000000 + // Position of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Pos = 0x19 + // Bit mask of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Msk = 0x2000000 + // Bit TIMER_UNIT1_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN = 0x2000000 + // Position of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Pos = 0x1a + // Bit mask of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Msk = 0x4000000 + // Bit TIMER_UNIT1_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN = 0x4000000 + // Position of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Pos = 0x1b + // Bit mask of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Msk = 0x8000000 + // Bit TIMER_UNIT0_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN = 0x8000000 + // Position of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Pos = 0x1c + // Bit mask of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Msk = 0x10000000 + // Bit TIMER_UNIT0_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN = 0x10000000 + // Position of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Pos = 0x1d + // Bit mask of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Msk = 0x20000000 + // Bit TIMER_UNIT1_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN = 0x20000000 + // Position of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Pos = 0x1e + // Bit mask of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Msk = 0x40000000 + // Bit TIMER_UNIT0_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN = 0x40000000 + // Position of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + SYSTIMER_CONF_CLK_EN = 0x80000000 + + // UNIT0_OP: system timer unit0 value update register + // Position of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT0_VALUE_VALID. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT0_UPDATE. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE = 0x40000000 + + // UNIT1_OP: system timer unit1 value update register + // Position of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT1_VALUE_VALID. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT1_UPDATE. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE = 0x40000000 + + // UNIT0_LOAD_HI: system timer unit0 value high load register + // Position of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Msk = 0xfffff + + // UNIT0_LOAD_LO: system timer unit0 value low load register + // Position of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Msk = 0xffffffff + + // UNIT1_LOAD_HI: system timer unit1 value high load register + // Position of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Msk = 0xfffff + + // UNIT1_LOAD_LO: system timer unit1 value low load register + // Position of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Msk = 0xffffffff + + // TARGET0_HI: system timer comp0 value high register + // Position of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Msk = 0xfffff + + // TARGET0_LO: system timer comp0 value low register + // Position of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Msk = 0xffffffff + + // TARGET1_HI: system timer comp1 value high register + // Position of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Msk = 0xfffff + + // TARGET1_LO: system timer comp1 value low register + // Position of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Msk = 0xffffffff + + // TARGET2_HI: system timer comp2 value high register + // Position of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Msk = 0xfffff + + // TARGET2_LO: system timer comp2 value low register + // Position of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Msk = 0xffffffff + + // TARGET0_CONF: system timer comp0 target mode register + // Position of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Pos = 0x0 + // Bit mask of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Msk = 0x3ffffff + // Position of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET0_PERIOD_MODE. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE = 0x40000000 + // Position of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET0_TIMER_UNIT_SEL. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL = 0x80000000 + + // TARGET1_CONF: system timer comp1 target mode register + // Position of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Pos = 0x0 + // Bit mask of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Msk = 0x3ffffff + // Position of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET1_PERIOD_MODE. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE = 0x40000000 + // Position of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET1_TIMER_UNIT_SEL. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL = 0x80000000 + + // TARGET2_CONF: system timer comp2 target mode register + // Position of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Pos = 0x0 + // Bit mask of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Msk = 0x3ffffff + // Position of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET2_PERIOD_MODE. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE = 0x40000000 + // Position of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET2_TIMER_UNIT_SEL. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL = 0x80000000 + + // UNIT0_VALUE_HI: system timer unit0 value high register + // Position of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Msk = 0xfffff + + // UNIT0_VALUE_LO: system timer unit0 value low register + // Position of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Msk = 0xffffffff + + // UNIT1_VALUE_HI: system timer unit1 value high register + // Position of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Msk = 0xfffff + + // UNIT1_VALUE_LO: system timer unit1 value low register + // Position of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Msk = 0xffffffff + + // COMP0_LOAD: system timer comp0 conf sync register + // Position of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Msk = 0x1 + // Bit TIMER_COMP0_LOAD. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD = 0x1 + + // COMP1_LOAD: system timer comp1 conf sync register + // Position of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Msk = 0x1 + // Bit TIMER_COMP1_LOAD. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD = 0x1 + + // COMP2_LOAD: system timer comp2 conf sync register + // Position of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Msk = 0x1 + // Bit TIMER_COMP2_LOAD. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD = 0x1 + + // UNIT0_LOAD: system timer unit0 conf sync register + // Position of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Msk = 0x1 + // Bit TIMER_UNIT0_LOAD. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD = 0x1 + + // UNIT1_LOAD: system timer unit1 conf sync register + // Position of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Msk = 0x1 + // Bit TIMER_UNIT1_LOAD. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD = 0x1 + + // INT_ENA: systimer interrupt enable register + // Position of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Pos = 0x0 + // Bit mask of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Msk = 0x1 + // Bit TARGET0_INT_ENA. + SYSTIMER_INT_ENA_TARGET0_INT_ENA = 0x1 + // Position of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Pos = 0x1 + // Bit mask of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Msk = 0x2 + // Bit TARGET1_INT_ENA. + SYSTIMER_INT_ENA_TARGET1_INT_ENA = 0x2 + // Position of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Pos = 0x2 + // Bit mask of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Msk = 0x4 + // Bit TARGET2_INT_ENA. + SYSTIMER_INT_ENA_TARGET2_INT_ENA = 0x4 + + // INT_RAW: systimer interrupt raw register + // Position of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Pos = 0x0 + // Bit mask of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Msk = 0x1 + // Bit TARGET0_INT_RAW. + SYSTIMER_INT_RAW_TARGET0_INT_RAW = 0x1 + // Position of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Pos = 0x1 + // Bit mask of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Msk = 0x2 + // Bit TARGET1_INT_RAW. + SYSTIMER_INT_RAW_TARGET1_INT_RAW = 0x2 + // Position of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Pos = 0x2 + // Bit mask of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Msk = 0x4 + // Bit TARGET2_INT_RAW. + SYSTIMER_INT_RAW_TARGET2_INT_RAW = 0x4 + + // INT_CLR: systimer interrupt clear register + // Position of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Pos = 0x0 + // Bit mask of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Msk = 0x1 + // Bit TARGET0_INT_CLR. + SYSTIMER_INT_CLR_TARGET0_INT_CLR = 0x1 + // Position of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Pos = 0x1 + // Bit mask of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Msk = 0x2 + // Bit TARGET1_INT_CLR. + SYSTIMER_INT_CLR_TARGET1_INT_CLR = 0x2 + // Position of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Pos = 0x2 + // Bit mask of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Msk = 0x4 + // Bit TARGET2_INT_CLR. + SYSTIMER_INT_CLR_TARGET2_INT_CLR = 0x4 + + // INT_ST: systimer interrupt status register + // Position of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Pos = 0x0 + // Bit mask of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Msk = 0x1 + // Bit TARGET0_INT_ST. + SYSTIMER_INT_ST_TARGET0_INT_ST = 0x1 + // Position of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Pos = 0x1 + // Bit mask of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Msk = 0x2 + // Bit TARGET1_INT_ST. + SYSTIMER_INT_ST_TARGET1_INT_ST = 0x2 + // Position of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Pos = 0x2 + // Bit mask of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Msk = 0x4 + // Bit TARGET2_INT_ST. + SYSTIMER_INT_ST_TARGET2_INT_ST = 0x4 + + // REAL_TARGET0_LO: system timer comp0 actual target value low register + // Position of TARGET0_LO_RO field. + SYSTIMER_REAL_TARGET0_LO_TARGET0_LO_RO_Pos = 0x0 + // Bit mask of TARGET0_LO_RO field. + SYSTIMER_REAL_TARGET0_LO_TARGET0_LO_RO_Msk = 0xffffffff + + // REAL_TARGET0_HI: system timer comp0 actual target value high register + // Position of TARGET0_HI_RO field. + SYSTIMER_REAL_TARGET0_HI_TARGET0_HI_RO_Pos = 0x0 + // Bit mask of TARGET0_HI_RO field. + SYSTIMER_REAL_TARGET0_HI_TARGET0_HI_RO_Msk = 0xfffff + + // REAL_TARGET1_LO: system timer comp1 actual target value low register + // Position of TARGET1_LO_RO field. + SYSTIMER_REAL_TARGET1_LO_TARGET1_LO_RO_Pos = 0x0 + // Bit mask of TARGET1_LO_RO field. + SYSTIMER_REAL_TARGET1_LO_TARGET1_LO_RO_Msk = 0xffffffff + + // REAL_TARGET1_HI: system timer comp1 actual target value high register + // Position of TARGET1_HI_RO field. + SYSTIMER_REAL_TARGET1_HI_TARGET1_HI_RO_Pos = 0x0 + // Bit mask of TARGET1_HI_RO field. + SYSTIMER_REAL_TARGET1_HI_TARGET1_HI_RO_Msk = 0xfffff + + // REAL_TARGET2_LO: system timer comp2 actual target value low register + // Position of TARGET2_LO_RO field. + SYSTIMER_REAL_TARGET2_LO_TARGET2_LO_RO_Pos = 0x0 + // Bit mask of TARGET2_LO_RO field. + SYSTIMER_REAL_TARGET2_LO_TARGET2_LO_RO_Msk = 0xffffffff + + // REAL_TARGET2_HI: system timer comp2 actual target value high register + // Position of TARGET2_HI_RO field. + SYSTIMER_REAL_TARGET2_HI_TARGET2_HI_RO_Pos = 0x0 + // Bit mask of TARGET2_HI_RO field. + SYSTIMER_REAL_TARGET2_HI_TARGET2_HI_RO_Msk = 0xfffff + + // DATE: system timer version control register + // Position of DATE field. + SYSTIMER_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SYSTIMER_DATE_DATE_Msk = 0xffffffff +) + +// Constants for TEE: TEE Peripheral +const ( + // M0_MODE_CTRL: Tee mode control register + // Position of M0_MODE field. + TEE_M0_MODE_CTRL_M0_MODE_Pos = 0x0 + // Bit mask of M0_MODE field. + TEE_M0_MODE_CTRL_M0_MODE_Msk = 0x3 + + // M1_MODE_CTRL: Tee mode control register + // Position of M1_MODE field. + TEE_M1_MODE_CTRL_M1_MODE_Pos = 0x0 + // Bit mask of M1_MODE field. + TEE_M1_MODE_CTRL_M1_MODE_Msk = 0x3 + + // M2_MODE_CTRL: Tee mode control register + // Position of M2_MODE field. + TEE_M2_MODE_CTRL_M2_MODE_Pos = 0x0 + // Bit mask of M2_MODE field. + TEE_M2_MODE_CTRL_M2_MODE_Msk = 0x3 + + // M3_MODE_CTRL: Tee mode control register + // Position of M3_MODE field. + TEE_M3_MODE_CTRL_M3_MODE_Pos = 0x0 + // Bit mask of M3_MODE field. + TEE_M3_MODE_CTRL_M3_MODE_Msk = 0x3 + + // M4_MODE_CTRL: Tee mode control register + // Position of M4_MODE field. + TEE_M4_MODE_CTRL_M4_MODE_Pos = 0x0 + // Bit mask of M4_MODE field. + TEE_M4_MODE_CTRL_M4_MODE_Msk = 0x3 + + // M5_MODE_CTRL: Tee mode control register + // Position of M5_MODE field. + TEE_M5_MODE_CTRL_M5_MODE_Pos = 0x0 + // Bit mask of M5_MODE field. + TEE_M5_MODE_CTRL_M5_MODE_Msk = 0x3 + + // M6_MODE_CTRL: Tee mode control register + // Position of M6_MODE field. + TEE_M6_MODE_CTRL_M6_MODE_Pos = 0x0 + // Bit mask of M6_MODE field. + TEE_M6_MODE_CTRL_M6_MODE_Msk = 0x3 + + // M7_MODE_CTRL: Tee mode control register + // Position of M7_MODE field. + TEE_M7_MODE_CTRL_M7_MODE_Pos = 0x0 + // Bit mask of M7_MODE field. + TEE_M7_MODE_CTRL_M7_MODE_Msk = 0x3 + + // M8_MODE_CTRL: Tee mode control register + // Position of M8_MODE field. + TEE_M8_MODE_CTRL_M8_MODE_Pos = 0x0 + // Bit mask of M8_MODE field. + TEE_M8_MODE_CTRL_M8_MODE_Msk = 0x3 + + // M9_MODE_CTRL: Tee mode control register + // Position of M9_MODE field. + TEE_M9_MODE_CTRL_M9_MODE_Pos = 0x0 + // Bit mask of M9_MODE field. + TEE_M9_MODE_CTRL_M9_MODE_Msk = 0x3 + + // M10_MODE_CTRL: Tee mode control register + // Position of M10_MODE field. + TEE_M10_MODE_CTRL_M10_MODE_Pos = 0x0 + // Bit mask of M10_MODE field. + TEE_M10_MODE_CTRL_M10_MODE_Msk = 0x3 + + // M11_MODE_CTRL: Tee mode control register + // Position of M11_MODE field. + TEE_M11_MODE_CTRL_M11_MODE_Pos = 0x0 + // Bit mask of M11_MODE field. + TEE_M11_MODE_CTRL_M11_MODE_Msk = 0x3 + + // M12_MODE_CTRL: Tee mode control register + // Position of M12_MODE field. + TEE_M12_MODE_CTRL_M12_MODE_Pos = 0x0 + // Bit mask of M12_MODE field. + TEE_M12_MODE_CTRL_M12_MODE_Msk = 0x3 + + // M13_MODE_CTRL: Tee mode control register + // Position of M13_MODE field. + TEE_M13_MODE_CTRL_M13_MODE_Pos = 0x0 + // Bit mask of M13_MODE field. + TEE_M13_MODE_CTRL_M13_MODE_Msk = 0x3 + + // M14_MODE_CTRL: Tee mode control register + // Position of M14_MODE field. + TEE_M14_MODE_CTRL_M14_MODE_Pos = 0x0 + // Bit mask of M14_MODE field. + TEE_M14_MODE_CTRL_M14_MODE_Msk = 0x3 + + // M15_MODE_CTRL: Tee mode control register + // Position of M15_MODE field. + TEE_M15_MODE_CTRL_M15_MODE_Pos = 0x0 + // Bit mask of M15_MODE field. + TEE_M15_MODE_CTRL_M15_MODE_Msk = 0x3 + + // M16_MODE_CTRL: Tee mode control register + // Position of M16_MODE field. + TEE_M16_MODE_CTRL_M16_MODE_Pos = 0x0 + // Bit mask of M16_MODE field. + TEE_M16_MODE_CTRL_M16_MODE_Msk = 0x3 + + // M17_MODE_CTRL: Tee mode control register + // Position of M17_MODE field. + TEE_M17_MODE_CTRL_M17_MODE_Pos = 0x0 + // Bit mask of M17_MODE field. + TEE_M17_MODE_CTRL_M17_MODE_Msk = 0x3 + + // M18_MODE_CTRL: Tee mode control register + // Position of M18_MODE field. + TEE_M18_MODE_CTRL_M18_MODE_Pos = 0x0 + // Bit mask of M18_MODE field. + TEE_M18_MODE_CTRL_M18_MODE_Msk = 0x3 + + // M19_MODE_CTRL: Tee mode control register + // Position of M19_MODE field. + TEE_M19_MODE_CTRL_M19_MODE_Pos = 0x0 + // Bit mask of M19_MODE field. + TEE_M19_MODE_CTRL_M19_MODE_Msk = 0x3 + + // M20_MODE_CTRL: Tee mode control register + // Position of M20_MODE field. + TEE_M20_MODE_CTRL_M20_MODE_Pos = 0x0 + // Bit mask of M20_MODE field. + TEE_M20_MODE_CTRL_M20_MODE_Msk = 0x3 + + // M21_MODE_CTRL: Tee mode control register + // Position of M21_MODE field. + TEE_M21_MODE_CTRL_M21_MODE_Pos = 0x0 + // Bit mask of M21_MODE field. + TEE_M21_MODE_CTRL_M21_MODE_Msk = 0x3 + + // M22_MODE_CTRL: Tee mode control register + // Position of M22_MODE field. + TEE_M22_MODE_CTRL_M22_MODE_Pos = 0x0 + // Bit mask of M22_MODE field. + TEE_M22_MODE_CTRL_M22_MODE_Msk = 0x3 + + // M23_MODE_CTRL: Tee mode control register + // Position of M23_MODE field. + TEE_M23_MODE_CTRL_M23_MODE_Pos = 0x0 + // Bit mask of M23_MODE field. + TEE_M23_MODE_CTRL_M23_MODE_Msk = 0x3 + + // M24_MODE_CTRL: Tee mode control register + // Position of M24_MODE field. + TEE_M24_MODE_CTRL_M24_MODE_Pos = 0x0 + // Bit mask of M24_MODE field. + TEE_M24_MODE_CTRL_M24_MODE_Msk = 0x3 + + // M25_MODE_CTRL: Tee mode control register + // Position of M25_MODE field. + TEE_M25_MODE_CTRL_M25_MODE_Pos = 0x0 + // Bit mask of M25_MODE field. + TEE_M25_MODE_CTRL_M25_MODE_Msk = 0x3 + + // M26_MODE_CTRL: Tee mode control register + // Position of M26_MODE field. + TEE_M26_MODE_CTRL_M26_MODE_Pos = 0x0 + // Bit mask of M26_MODE field. + TEE_M26_MODE_CTRL_M26_MODE_Msk = 0x3 + + // M27_MODE_CTRL: Tee mode control register + // Position of M27_MODE field. + TEE_M27_MODE_CTRL_M27_MODE_Pos = 0x0 + // Bit mask of M27_MODE field. + TEE_M27_MODE_CTRL_M27_MODE_Msk = 0x3 + + // M28_MODE_CTRL: Tee mode control register + // Position of M28_MODE field. + TEE_M28_MODE_CTRL_M28_MODE_Pos = 0x0 + // Bit mask of M28_MODE field. + TEE_M28_MODE_CTRL_M28_MODE_Msk = 0x3 + + // M29_MODE_CTRL: Tee mode control register + // Position of M29_MODE field. + TEE_M29_MODE_CTRL_M29_MODE_Pos = 0x0 + // Bit mask of M29_MODE field. + TEE_M29_MODE_CTRL_M29_MODE_Msk = 0x3 + + // M30_MODE_CTRL: Tee mode control register + // Position of M30_MODE field. + TEE_M30_MODE_CTRL_M30_MODE_Pos = 0x0 + // Bit mask of M30_MODE field. + TEE_M30_MODE_CTRL_M30_MODE_Msk = 0x3 + + // M31_MODE_CTRL: Tee mode control register + // Position of M31_MODE field. + TEE_M31_MODE_CTRL_M31_MODE_Pos = 0x0 + // Bit mask of M31_MODE field. + TEE_M31_MODE_CTRL_M31_MODE_Msk = 0x3 + + // CLOCK_GATE: Clock gating register + // Position of CLK_EN field. + TEE_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + TEE_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + TEE_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version register + // Position of DATE field. + TEE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + TEE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for TIMG0: Timer Group 0 +const ( + // T0CONFIG: Timer %s configuration register + // Position of USE_XTAL field. + TIMG_T0CONFIG_USE_XTAL_Pos = 0x9 + // Bit mask of USE_XTAL field. + TIMG_T0CONFIG_USE_XTAL_Msk = 0x200 + // Bit USE_XTAL. + TIMG_T0CONFIG_USE_XTAL = 0x200 + // Position of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Pos = 0xa + // Bit mask of ALARM_EN field. + TIMG_T0CONFIG_ALARM_EN_Msk = 0x400 + // Bit ALARM_EN. + TIMG_T0CONFIG_ALARM_EN = 0x400 + // Position of DIVCNT_RST field. + TIMG_T0CONFIG_DIVCNT_RST_Pos = 0xc + // Bit mask of DIVCNT_RST field. + TIMG_T0CONFIG_DIVCNT_RST_Msk = 0x1000 + // Bit DIVCNT_RST. + TIMG_T0CONFIG_DIVCNT_RST = 0x1000 + // Position of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Pos = 0xd + // Bit mask of DIVIDER field. + TIMG_T0CONFIG_DIVIDER_Msk = 0x1fffe000 + // Position of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Pos = 0x1d + // Bit mask of AUTORELOAD field. + TIMG_T0CONFIG_AUTORELOAD_Msk = 0x20000000 + // Bit AUTORELOAD. + TIMG_T0CONFIG_AUTORELOAD = 0x20000000 + // Position of INCREASE field. + TIMG_T0CONFIG_INCREASE_Pos = 0x1e + // Bit mask of INCREASE field. + TIMG_T0CONFIG_INCREASE_Msk = 0x40000000 + // Bit INCREASE. + TIMG_T0CONFIG_INCREASE = 0x40000000 + // Position of EN field. + TIMG_T0CONFIG_EN_Pos = 0x1f + // Bit mask of EN field. + TIMG_T0CONFIG_EN_Msk = 0x80000000 + // Bit EN. + TIMG_T0CONFIG_EN = 0x80000000 + + // T0LO: Timer %s current value, low 32 bits + // Position of LO field. + TIMG_T0LO_LO_Pos = 0x0 + // Bit mask of LO field. + TIMG_T0LO_LO_Msk = 0xffffffff + + // T0HI: Timer %s current value, high 22 bits + // Position of HI field. + TIMG_T0HI_HI_Pos = 0x0 + // Bit mask of HI field. + TIMG_T0HI_HI_Msk = 0x3fffff + + // T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + // Position of UPDATE field. + TIMG_T0UPDATE_UPDATE_Pos = 0x1f + // Bit mask of UPDATE field. + TIMG_T0UPDATE_UPDATE_Msk = 0x80000000 + // Bit UPDATE. + TIMG_T0UPDATE_UPDATE = 0x80000000 + + // T0ALARMLO: Timer %s alarm value, low 32 bits + // Position of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Pos = 0x0 + // Bit mask of ALARM_LO field. + TIMG_T0ALARMLO_ALARM_LO_Msk = 0xffffffff + + // T0ALARMHI: Timer %s alarm value, high bits + // Position of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Pos = 0x0 + // Bit mask of ALARM_HI field. + TIMG_T0ALARMHI_ALARM_HI_Msk = 0x3fffff + + // T0LOADLO: Timer %s reload value, low 32 bits + // Position of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Pos = 0x0 + // Bit mask of LOAD_LO field. + TIMG_T0LOADLO_LOAD_LO_Msk = 0xffffffff + + // T0LOADHI: Timer %s reload value, high 22 bits + // Position of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Pos = 0x0 + // Bit mask of LOAD_HI field. + TIMG_T0LOADHI_LOAD_HI_Msk = 0x3fffff + + // T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + // Position of LOAD field. + TIMG_T0LOAD_LOAD_Pos = 0x0 + // Bit mask of LOAD field. + TIMG_T0LOAD_LOAD_Msk = 0xffffffff + + // WDTCONFIG0: Watchdog timer configuration register + // Position of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xc + // Bit mask of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x1000 + // Bit WDT_APPCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x1000 + // Position of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xd + // Bit mask of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x2000 + // Bit WDT_PROCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x2000 + // Position of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xe + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x4000 + // Bit WDT_FLASHBOOT_MOD_EN. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x4000 + // Position of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xf + // Bit mask of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0x38000 + // Position of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x12 + // Bit mask of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x1c0000 + // Position of WDT_USE_XTAL field. + TIMG_WDTCONFIG0_WDT_USE_XTAL_Pos = 0x15 + // Bit mask of WDT_USE_XTAL field. + TIMG_WDTCONFIG0_WDT_USE_XTAL_Msk = 0x200000 + // Bit WDT_USE_XTAL. + TIMG_WDTCONFIG0_WDT_USE_XTAL = 0x200000 + // Position of WDT_CONF_UPDATE_EN field. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Pos = 0x16 + // Bit mask of WDT_CONF_UPDATE_EN field. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Msk = 0x400000 + // Bit WDT_CONF_UPDATE_EN. + TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN = 0x400000 + // Position of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Pos = 0x17 + // Bit mask of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Msk = 0x1800000 + // Position of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Pos = 0x19 + // Bit mask of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Msk = 0x6000000 + // Position of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Pos = 0x1b + // Bit mask of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Msk = 0x18000000 + // Position of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Pos = 0x1d + // Bit mask of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Msk = 0x60000000 + // Position of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + TIMG_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: Watchdog timer prescaler register + // Position of WDT_DIVCNT_RST field. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Pos = 0x0 + // Bit mask of WDT_DIVCNT_RST field. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Msk = 0x1 + // Bit WDT_DIVCNT_RST. + TIMG_WDTCONFIG1_WDT_DIVCNT_RST = 0x1 + // Position of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Pos = 0x10 + // Bit mask of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Msk = 0xffff0000 + + // WDTCONFIG2: Watchdog timer stage 0 timeout value + // Position of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: Watchdog timer stage 1 timeout value + // Position of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: Watchdog timer stage 2 timeout value + // Position of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG5: Watchdog timer stage 3 timeout value + // Position of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: Write to feed the watchdog timer + // Position of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Pos = 0x0 + // Bit mask of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Msk = 0xffffffff + + // WDTWPROTECT: Watchdog write protect register + // Position of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // RTCCALICFG: RTC calibration configure register + // Position of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Pos = 0xc + // Bit mask of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Msk = 0x1000 + // Bit RTC_CALI_START_CYCLING. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING = 0x1000 + // Position of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Pos = 0xd + // Bit mask of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Msk = 0x6000 + // Position of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Pos = 0xf + // Bit mask of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Msk = 0x8000 + // Bit RTC_CALI_RDY. + TIMG_RTCCALICFG_RTC_CALI_RDY = 0x8000 + // Position of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Pos = 0x10 + // Bit mask of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Msk = 0x7fff0000 + // Position of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Pos = 0x1f + // Bit mask of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Msk = 0x80000000 + // Bit RTC_CALI_START. + TIMG_RTCCALICFG_RTC_CALI_START = 0x80000000 + + // RTCCALICFG1: RTC calibration configure1 register + // Position of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Pos = 0x0 + // Bit mask of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Msk = 0x1 + // Bit RTC_CALI_CYCLING_DATA_VLD. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD = 0x1 + // Position of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Pos = 0x7 + // Bit mask of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Msk = 0xffffff80 + + // INT_ENA_TIMERS: Interrupt enable bits + // Position of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Pos = 0x0 + // Bit mask of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Msk = 0x1 + // Bit T0_INT_ENA. + TIMG_INT_ENA_TIMERS_T0_INT_ENA = 0x1 + // Position of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Pos = 0x1 + // Bit mask of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Msk = 0x2 + // Bit WDT_INT_ENA. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA = 0x2 + + // INT_RAW_TIMERS: Raw interrupt status + // Position of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Pos = 0x0 + // Bit mask of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Msk = 0x1 + // Bit T0_INT_RAW. + TIMG_INT_RAW_TIMERS_T0_INT_RAW = 0x1 + // Position of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Pos = 0x1 + // Bit mask of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Msk = 0x2 + // Bit WDT_INT_RAW. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW = 0x2 + + // INT_ST_TIMERS: Masked interrupt status + // Position of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Pos = 0x0 + // Bit mask of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Msk = 0x1 + // Bit T0_INT_ST. + TIMG_INT_ST_TIMERS_T0_INT_ST = 0x1 + // Position of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Pos = 0x1 + // Bit mask of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Msk = 0x2 + // Bit WDT_INT_ST. + TIMG_INT_ST_TIMERS_WDT_INT_ST = 0x2 + + // INT_CLR_TIMERS: Interrupt clear bits + // Position of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Pos = 0x0 + // Bit mask of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Msk = 0x1 + // Bit T0_INT_CLR. + TIMG_INT_CLR_TIMERS_T0_INT_CLR = 0x1 + // Position of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Pos = 0x1 + // Bit mask of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Msk = 0x2 + // Bit WDT_INT_CLR. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR = 0x2 + + // RTCCALICFG2: Timer group calibration register + // Position of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Pos = 0x0 + // Bit mask of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Msk = 0x1 + // Bit RTC_CALI_TIMEOUT. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT = 0x1 + // Position of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Pos = 0x3 + // Bit mask of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Msk = 0x78 + // Position of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Pos = 0x7 + // Bit mask of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Msk = 0xffffff80 + + // NTIMERS_DATE: Timer version control register + // Position of NTIMGS_DATE field. + TIMG_NTIMERS_DATE_NTIMGS_DATE_Pos = 0x0 + // Bit mask of NTIMGS_DATE field. + TIMG_NTIMERS_DATE_NTIMGS_DATE_Msk = 0xfffffff + + // REGCLK: Timer group clock gate register + // Position of ETM_EN field. + TIMG_REGCLK_ETM_EN_Pos = 0x1c + // Bit mask of ETM_EN field. + TIMG_REGCLK_ETM_EN_Msk = 0x10000000 + // Bit ETM_EN. + TIMG_REGCLK_ETM_EN = 0x10000000 + // Position of WDT_CLK_IS_ACTIVE field. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Pos = 0x1d + // Bit mask of WDT_CLK_IS_ACTIVE field. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Msk = 0x20000000 + // Bit WDT_CLK_IS_ACTIVE. + TIMG_REGCLK_WDT_CLK_IS_ACTIVE = 0x20000000 + // Position of TIMER_CLK_IS_ACTIVE field. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Pos = 0x1e + // Bit mask of TIMER_CLK_IS_ACTIVE field. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Msk = 0x40000000 + // Bit TIMER_CLK_IS_ACTIVE. + TIMG_REGCLK_TIMER_CLK_IS_ACTIVE = 0x40000000 + // Position of CLK_EN field. + TIMG_REGCLK_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + TIMG_REGCLK_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + TIMG_REGCLK_CLK_EN = 0x80000000 +) + +// Constants for TRACE: RISC-V Trace Encoder +const ( + // MEM_START_ADDR: mem start addr + // Position of MEM_STAET_ADDR field. + TRACE_MEM_START_ADDR_MEM_STAET_ADDR_Pos = 0x0 + // Bit mask of MEM_STAET_ADDR field. + TRACE_MEM_START_ADDR_MEM_STAET_ADDR_Msk = 0xffffffff + + // MEM_END_ADDR: mem end addr + // Position of MEM_END_ADDR field. + TRACE_MEM_END_ADDR_MEM_END_ADDR_Pos = 0x0 + // Bit mask of MEM_END_ADDR field. + TRACE_MEM_END_ADDR_MEM_END_ADDR_Msk = 0xffffffff + + // MEM_CURRENT_ADDR: mem current addr + // Position of MEM_CURRENT_ADDR field. + TRACE_MEM_CURRENT_ADDR_MEM_CURRENT_ADDR_Pos = 0x0 + // Bit mask of MEM_CURRENT_ADDR field. + TRACE_MEM_CURRENT_ADDR_MEM_CURRENT_ADDR_Msk = 0xffffffff + + // MEM_ADDR_UPDATE: mem addr update + // Position of MEM_CURRENT_ADDR_UPDATE field. + TRACE_MEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE_Pos = 0x0 + // Bit mask of MEM_CURRENT_ADDR_UPDATE field. + TRACE_MEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE_Msk = 0x1 + // Bit MEM_CURRENT_ADDR_UPDATE. + TRACE_MEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE = 0x1 + + // FIFO_STATUS: fifo status register + // Position of FIFO_EMPTY field. + TRACE_FIFO_STATUS_FIFO_EMPTY_Pos = 0x0 + // Bit mask of FIFO_EMPTY field. + TRACE_FIFO_STATUS_FIFO_EMPTY_Msk = 0x1 + // Bit FIFO_EMPTY. + TRACE_FIFO_STATUS_FIFO_EMPTY = 0x1 + // Position of WORK_STATUS field. + TRACE_FIFO_STATUS_WORK_STATUS_Pos = 0x1 + // Bit mask of WORK_STATUS field. + TRACE_FIFO_STATUS_WORK_STATUS_Msk = 0x2 + // Bit WORK_STATUS. + TRACE_FIFO_STATUS_WORK_STATUS = 0x2 + + // INTR_ENA: interrupt enable register + // Position of FIFO_OVERFLOW_INTR_ENA field. + TRACE_INTR_ENA_FIFO_OVERFLOW_INTR_ENA_Pos = 0x0 + // Bit mask of FIFO_OVERFLOW_INTR_ENA field. + TRACE_INTR_ENA_FIFO_OVERFLOW_INTR_ENA_Msk = 0x1 + // Bit FIFO_OVERFLOW_INTR_ENA. + TRACE_INTR_ENA_FIFO_OVERFLOW_INTR_ENA = 0x1 + // Position of MEM_FULL_INTR_ENA field. + TRACE_INTR_ENA_MEM_FULL_INTR_ENA_Pos = 0x1 + // Bit mask of MEM_FULL_INTR_ENA field. + TRACE_INTR_ENA_MEM_FULL_INTR_ENA_Msk = 0x2 + // Bit MEM_FULL_INTR_ENA. + TRACE_INTR_ENA_MEM_FULL_INTR_ENA = 0x2 + + // INTR_RAW: interrupt status register + // Position of FIFO_OVERFLOW_INTR_RAW field. + TRACE_INTR_RAW_FIFO_OVERFLOW_INTR_RAW_Pos = 0x0 + // Bit mask of FIFO_OVERFLOW_INTR_RAW field. + TRACE_INTR_RAW_FIFO_OVERFLOW_INTR_RAW_Msk = 0x1 + // Bit FIFO_OVERFLOW_INTR_RAW. + TRACE_INTR_RAW_FIFO_OVERFLOW_INTR_RAW = 0x1 + // Position of MEM_FULL_INTR_RAW field. + TRACE_INTR_RAW_MEM_FULL_INTR_RAW_Pos = 0x1 + // Bit mask of MEM_FULL_INTR_RAW field. + TRACE_INTR_RAW_MEM_FULL_INTR_RAW_Msk = 0x2 + // Bit MEM_FULL_INTR_RAW. + TRACE_INTR_RAW_MEM_FULL_INTR_RAW = 0x2 + + // INTR_CLR: interrupt clear register + // Position of FIFO_OVERFLOW_INTR_CLR field. + TRACE_INTR_CLR_FIFO_OVERFLOW_INTR_CLR_Pos = 0x0 + // Bit mask of FIFO_OVERFLOW_INTR_CLR field. + TRACE_INTR_CLR_FIFO_OVERFLOW_INTR_CLR_Msk = 0x1 + // Bit FIFO_OVERFLOW_INTR_CLR. + TRACE_INTR_CLR_FIFO_OVERFLOW_INTR_CLR = 0x1 + // Position of MEM_FULL_INTR_CLR field. + TRACE_INTR_CLR_MEM_FULL_INTR_CLR_Pos = 0x1 + // Bit mask of MEM_FULL_INTR_CLR field. + TRACE_INTR_CLR_MEM_FULL_INTR_CLR_Msk = 0x2 + // Bit MEM_FULL_INTR_CLR. + TRACE_INTR_CLR_MEM_FULL_INTR_CLR = 0x2 + + // TRIGGER: trigger register + // Position of ON field. + TRACE_TRIGGER_ON_Pos = 0x0 + // Bit mask of ON field. + TRACE_TRIGGER_ON_Msk = 0x1 + // Bit ON. + TRACE_TRIGGER_ON = 0x1 + // Position of OFF field. + TRACE_TRIGGER_OFF_Pos = 0x1 + // Bit mask of OFF field. + TRACE_TRIGGER_OFF_Msk = 0x2 + // Bit OFF. + TRACE_TRIGGER_OFF = 0x2 + // Position of MEM_LOOP field. + TRACE_TRIGGER_MEM_LOOP_Pos = 0x2 + // Bit mask of MEM_LOOP field. + TRACE_TRIGGER_MEM_LOOP_Msk = 0x4 + // Bit MEM_LOOP. + TRACE_TRIGGER_MEM_LOOP = 0x4 + // Position of RESTART_ENA field. + TRACE_TRIGGER_RESTART_ENA_Pos = 0x3 + // Bit mask of RESTART_ENA field. + TRACE_TRIGGER_RESTART_ENA_Msk = 0x8 + // Bit RESTART_ENA. + TRACE_TRIGGER_RESTART_ENA = 0x8 + + // RESYNC_PROLONGED: resync configuration register + // Position of RESYNC_PROLONGED field. + TRACE_RESYNC_PROLONGED_RESYNC_PROLONGED_Pos = 0x0 + // Bit mask of RESYNC_PROLONGED field. + TRACE_RESYNC_PROLONGED_RESYNC_PROLONGED_Msk = 0xffffff + // Position of RESYNC_MODE field. + TRACE_RESYNC_PROLONGED_RESYNC_MODE_Pos = 0x18 + // Bit mask of RESYNC_MODE field. + TRACE_RESYNC_PROLONGED_RESYNC_MODE_Msk = 0x1000000 + // Bit RESYNC_MODE. + TRACE_RESYNC_PROLONGED_RESYNC_MODE = 0x1000000 + + // CLOCK_GATE: Clock gate control register + // Position of CLK_EN field. + TRACE_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + TRACE_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + TRACE_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version control register + // Position of DATE field. + TRACE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + TRACE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for TWAI0: Two-Wire Automotive Interface +const ( + // MODE: TWAI mode register. + // Position of RESET_MODE field. + TWAI_MODE_RESET_MODE_Pos = 0x0 + // Bit mask of RESET_MODE field. + TWAI_MODE_RESET_MODE_Msk = 0x1 + // Bit RESET_MODE. + TWAI_MODE_RESET_MODE = 0x1 + // Position of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Pos = 0x1 + // Bit mask of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Msk = 0x2 + // Bit LISTEN_ONLY_MODE. + TWAI_MODE_LISTEN_ONLY_MODE = 0x2 + // Position of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Pos = 0x2 + // Bit mask of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Msk = 0x4 + // Bit SELF_TEST_MODE. + TWAI_MODE_SELF_TEST_MODE = 0x4 + // Position of ACCEPTANCE_FILTER_MODE field. + TWAI_MODE_ACCEPTANCE_FILTER_MODE_Pos = 0x3 + // Bit mask of ACCEPTANCE_FILTER_MODE field. + TWAI_MODE_ACCEPTANCE_FILTER_MODE_Msk = 0x8 + // Bit ACCEPTANCE_FILTER_MODE. + TWAI_MODE_ACCEPTANCE_FILTER_MODE = 0x8 + + // CMD: TWAI command register. + // Position of TX_REQUEST field. + TWAI_CMD_TX_REQUEST_Pos = 0x0 + // Bit mask of TX_REQUEST field. + TWAI_CMD_TX_REQUEST_Msk = 0x1 + // Bit TX_REQUEST. + TWAI_CMD_TX_REQUEST = 0x1 + // Position of ABORT_TX field. + TWAI_CMD_ABORT_TX_Pos = 0x1 + // Bit mask of ABORT_TX field. + TWAI_CMD_ABORT_TX_Msk = 0x2 + // Bit ABORT_TX. + TWAI_CMD_ABORT_TX = 0x2 + // Position of RELEASE_BUFFER field. + TWAI_CMD_RELEASE_BUFFER_Pos = 0x2 + // Bit mask of RELEASE_BUFFER field. + TWAI_CMD_RELEASE_BUFFER_Msk = 0x4 + // Bit RELEASE_BUFFER. + TWAI_CMD_RELEASE_BUFFER = 0x4 + // Position of CLEAR_DATA_OVERRUN field. + TWAI_CMD_CLEAR_DATA_OVERRUN_Pos = 0x3 + // Bit mask of CLEAR_DATA_OVERRUN field. + TWAI_CMD_CLEAR_DATA_OVERRUN_Msk = 0x8 + // Bit CLEAR_DATA_OVERRUN. + TWAI_CMD_CLEAR_DATA_OVERRUN = 0x8 + // Position of SELF_RX_REQUEST field. + TWAI_CMD_SELF_RX_REQUEST_Pos = 0x4 + // Bit mask of SELF_RX_REQUEST field. + TWAI_CMD_SELF_RX_REQUEST_Msk = 0x10 + // Bit SELF_RX_REQUEST. + TWAI_CMD_SELF_RX_REQUEST = 0x10 + + // STATUS: TWAI status register. + // Position of RECEIVE_BUFFER field. + TWAI_STATUS_RECEIVE_BUFFER_Pos = 0x0 + // Bit mask of RECEIVE_BUFFER field. + TWAI_STATUS_RECEIVE_BUFFER_Msk = 0x1 + // Bit RECEIVE_BUFFER. + TWAI_STATUS_RECEIVE_BUFFER = 0x1 + // Position of OVERRUN field. + TWAI_STATUS_OVERRUN_Pos = 0x1 + // Bit mask of OVERRUN field. + TWAI_STATUS_OVERRUN_Msk = 0x2 + // Bit OVERRUN. + TWAI_STATUS_OVERRUN = 0x2 + // Position of TRANSMIT_BUFFER field. + TWAI_STATUS_TRANSMIT_BUFFER_Pos = 0x2 + // Bit mask of TRANSMIT_BUFFER field. + TWAI_STATUS_TRANSMIT_BUFFER_Msk = 0x4 + // Bit TRANSMIT_BUFFER. + TWAI_STATUS_TRANSMIT_BUFFER = 0x4 + // Position of TRANSMISSION_COMPLETE field. + TWAI_STATUS_TRANSMISSION_COMPLETE_Pos = 0x3 + // Bit mask of TRANSMISSION_COMPLETE field. + TWAI_STATUS_TRANSMISSION_COMPLETE_Msk = 0x8 + // Bit TRANSMISSION_COMPLETE. + TWAI_STATUS_TRANSMISSION_COMPLETE = 0x8 + // Position of RECEIVE field. + TWAI_STATUS_RECEIVE_Pos = 0x4 + // Bit mask of RECEIVE field. + TWAI_STATUS_RECEIVE_Msk = 0x10 + // Bit RECEIVE. + TWAI_STATUS_RECEIVE = 0x10 + // Position of TRANSMIT field. + TWAI_STATUS_TRANSMIT_Pos = 0x5 + // Bit mask of TRANSMIT field. + TWAI_STATUS_TRANSMIT_Msk = 0x20 + // Bit TRANSMIT. + TWAI_STATUS_TRANSMIT = 0x20 + // Position of ERR field. + TWAI_STATUS_ERR_Pos = 0x6 + // Bit mask of ERR field. + TWAI_STATUS_ERR_Msk = 0x40 + // Bit ERR. + TWAI_STATUS_ERR = 0x40 + // Position of NODE_BUS_OFF field. + TWAI_STATUS_NODE_BUS_OFF_Pos = 0x7 + // Bit mask of NODE_BUS_OFF field. + TWAI_STATUS_NODE_BUS_OFF_Msk = 0x80 + // Bit NODE_BUS_OFF. + TWAI_STATUS_NODE_BUS_OFF = 0x80 + // Position of MISS field. + TWAI_STATUS_MISS_Pos = 0x8 + // Bit mask of MISS field. + TWAI_STATUS_MISS_Msk = 0x100 + // Bit MISS. + TWAI_STATUS_MISS = 0x100 + + // INTERRUPT: Interrupt signals' register. + // Position of RECEIVE_INT_ST field. + TWAI_INTERRUPT_RECEIVE_INT_ST_Pos = 0x0 + // Bit mask of RECEIVE_INT_ST field. + TWAI_INTERRUPT_RECEIVE_INT_ST_Msk = 0x1 + // Bit RECEIVE_INT_ST. + TWAI_INTERRUPT_RECEIVE_INT_ST = 0x1 + // Position of TRANSMIT_INT_ST field. + TWAI_INTERRUPT_TRANSMIT_INT_ST_Pos = 0x1 + // Bit mask of TRANSMIT_INT_ST field. + TWAI_INTERRUPT_TRANSMIT_INT_ST_Msk = 0x2 + // Bit TRANSMIT_INT_ST. + TWAI_INTERRUPT_TRANSMIT_INT_ST = 0x2 + // Position of ERR_WARNING_INT_ST field. + TWAI_INTERRUPT_ERR_WARNING_INT_ST_Pos = 0x2 + // Bit mask of ERR_WARNING_INT_ST field. + TWAI_INTERRUPT_ERR_WARNING_INT_ST_Msk = 0x4 + // Bit ERR_WARNING_INT_ST. + TWAI_INTERRUPT_ERR_WARNING_INT_ST = 0x4 + // Position of DATA_OVERRUN_INT_ST field. + TWAI_INTERRUPT_DATA_OVERRUN_INT_ST_Pos = 0x3 + // Bit mask of DATA_OVERRUN_INT_ST field. + TWAI_INTERRUPT_DATA_OVERRUN_INT_ST_Msk = 0x8 + // Bit DATA_OVERRUN_INT_ST. + TWAI_INTERRUPT_DATA_OVERRUN_INT_ST = 0x8 + // Position of ERR_PASSIVE_INT_ST field. + TWAI_INTERRUPT_ERR_PASSIVE_INT_ST_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ST field. + TWAI_INTERRUPT_ERR_PASSIVE_INT_ST_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ST. + TWAI_INTERRUPT_ERR_PASSIVE_INT_ST = 0x20 + // Position of ARBITRATION_LOST_INT_ST field. + TWAI_INTERRUPT_ARBITRATION_LOST_INT_ST_Pos = 0x6 + // Bit mask of ARBITRATION_LOST_INT_ST field. + TWAI_INTERRUPT_ARBITRATION_LOST_INT_ST_Msk = 0x40 + // Bit ARBITRATION_LOST_INT_ST. + TWAI_INTERRUPT_ARBITRATION_LOST_INT_ST = 0x40 + // Position of BUS_ERR_INT_ST field. + TWAI_INTERRUPT_BUS_ERR_INT_ST_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ST field. + TWAI_INTERRUPT_BUS_ERR_INT_ST_Msk = 0x80 + // Bit BUS_ERR_INT_ST. + TWAI_INTERRUPT_BUS_ERR_INT_ST = 0x80 + // Position of IDLE_INT_ST field. + TWAI_INTERRUPT_IDLE_INT_ST_Pos = 0x8 + // Bit mask of IDLE_INT_ST field. + TWAI_INTERRUPT_IDLE_INT_ST_Msk = 0x100 + // Bit IDLE_INT_ST. + TWAI_INTERRUPT_IDLE_INT_ST = 0x100 + + // INTERRUPT_ENABLE: Interrupt enable register. + // Position of EXT_RECEIVE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA_Pos = 0x0 + // Bit mask of EXT_RECEIVE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA_Msk = 0x1 + // Bit EXT_RECEIVE_INT_ENA. + TWAI_INTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA = 0x1 + // Position of EXT_TRANSMIT_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA_Pos = 0x1 + // Bit mask of EXT_TRANSMIT_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA_Msk = 0x2 + // Bit EXT_TRANSMIT_INT_ENA. + TWAI_INTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA = 0x2 + // Position of EXT_ERR_WARNING_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA_Pos = 0x2 + // Bit mask of EXT_ERR_WARNING_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA_Msk = 0x4 + // Bit EXT_ERR_WARNING_INT_ENA. + TWAI_INTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA = 0x4 + // Position of EXT_DATA_OVERRUN_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA_Pos = 0x3 + // Bit mask of EXT_DATA_OVERRUN_INT_ENA field. + TWAI_INTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA_Msk = 0x8 + // Bit EXT_DATA_OVERRUN_INT_ENA. + TWAI_INTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA = 0x8 + // Position of ERR_PASSIVE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ENA. + TWAI_INTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA = 0x20 + // Position of ARBITRATION_LOST_INT_ENA field. + TWAI_INTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA_Pos = 0x6 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + TWAI_INTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA_Msk = 0x40 + // Bit ARBITRATION_LOST_INT_ENA. + TWAI_INTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA = 0x40 + // Position of BUS_ERR_INT_ENA field. + TWAI_INTERRUPT_ENABLE_BUS_ERR_INT_ENA_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ENA field. + TWAI_INTERRUPT_ENABLE_BUS_ERR_INT_ENA_Msk = 0x80 + // Bit BUS_ERR_INT_ENA. + TWAI_INTERRUPT_ENABLE_BUS_ERR_INT_ENA = 0x80 + // Position of IDLE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_IDLE_INT_ENA_Pos = 0x8 + // Bit mask of IDLE_INT_ENA field. + TWAI_INTERRUPT_ENABLE_IDLE_INT_ENA_Msk = 0x100 + // Bit IDLE_INT_ENA. + TWAI_INTERRUPT_ENABLE_IDLE_INT_ENA = 0x100 + + // BUS_TIMING_0: Bit timing configuration register 0. + // Position of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Pos = 0x0 + // Bit mask of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Msk = 0x3fff + // Position of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Pos = 0xe + // Bit mask of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Msk = 0xc000 + + // BUS_TIMING_1: Bit timing configuration register 1. + // Position of TIME_SEGMENT1 field. + TWAI_BUS_TIMING_1_TIME_SEGMENT1_Pos = 0x0 + // Bit mask of TIME_SEGMENT1 field. + TWAI_BUS_TIMING_1_TIME_SEGMENT1_Msk = 0xf + // Position of TIME_SEGMENT2 field. + TWAI_BUS_TIMING_1_TIME_SEGMENT2_Pos = 0x4 + // Bit mask of TIME_SEGMENT2 field. + TWAI_BUS_TIMING_1_TIME_SEGMENT2_Msk = 0x70 + // Position of TIME_SAMPLING field. + TWAI_BUS_TIMING_1_TIME_SAMPLING_Pos = 0x7 + // Bit mask of TIME_SAMPLING field. + TWAI_BUS_TIMING_1_TIME_SAMPLING_Msk = 0x80 + // Bit TIME_SAMPLING. + TWAI_BUS_TIMING_1_TIME_SAMPLING = 0x80 + + // ARB_LOST_CAP: TWAI arbiter lost capture register. + // Position of ARBITRATION_LOST_CAPTURE field. + TWAI_ARB_LOST_CAP_ARBITRATION_LOST_CAPTURE_Pos = 0x0 + // Bit mask of ARBITRATION_LOST_CAPTURE field. + TWAI_ARB_LOST_CAP_ARBITRATION_LOST_CAPTURE_Msk = 0x1f + + // ERR_CODE_CAP: TWAI error info capture register. + // Position of ERR_CAPTURE_CODE_SEGMENT field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT_Pos = 0x0 + // Bit mask of ERR_CAPTURE_CODE_SEGMENT field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT_Msk = 0x1f + // Position of ERR_CAPTURE_CODE_DIRECTION field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION_Pos = 0x5 + // Bit mask of ERR_CAPTURE_CODE_DIRECTION field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION_Msk = 0x20 + // Bit ERR_CAPTURE_CODE_DIRECTION. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION = 0x20 + // Position of ERR_CAPTURE_CODE_TYPE field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE_Pos = 0x6 + // Bit mask of ERR_CAPTURE_CODE_TYPE field. + TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE_Msk = 0xc0 + + // ERR_WARNING_LIMIT: TWAI error threshold configuration register. + // Position of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Pos = 0x0 + // Bit mask of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Msk = 0xff + + // RX_ERR_CNT: Rx error counter register. + // Position of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Pos = 0x0 + // Bit mask of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Msk = 0xff + + // TX_ERR_CNT: Tx error counter register. + // Position of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Pos = 0x0 + // Bit mask of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Msk = 0xff + + // DATA_0: Data register 0. + // Position of DATA_0 field. + TWAI_DATA_0_DATA_0_Pos = 0x0 + // Bit mask of DATA_0 field. + TWAI_DATA_0_DATA_0_Msk = 0xff + + // DATA_1: Data register 1. + // Position of DATA_1 field. + TWAI_DATA_1_DATA_1_Pos = 0x0 + // Bit mask of DATA_1 field. + TWAI_DATA_1_DATA_1_Msk = 0xff + + // DATA_2: Data register 2. + // Position of DATA_2 field. + TWAI_DATA_2_DATA_2_Pos = 0x0 + // Bit mask of DATA_2 field. + TWAI_DATA_2_DATA_2_Msk = 0xff + + // DATA_3: Data register 3. + // Position of DATA_3 field. + TWAI_DATA_3_DATA_3_Pos = 0x0 + // Bit mask of DATA_3 field. + TWAI_DATA_3_DATA_3_Msk = 0xff + + // DATA_4: Data register 4. + // Position of DATA_4 field. + TWAI_DATA_4_DATA_4_Pos = 0x0 + // Bit mask of DATA_4 field. + TWAI_DATA_4_DATA_4_Msk = 0xff + + // DATA_5: Data register 5. + // Position of DATA_5 field. + TWAI_DATA_5_DATA_5_Pos = 0x0 + // Bit mask of DATA_5 field. + TWAI_DATA_5_DATA_5_Msk = 0xff + + // DATA_6: Data register 6. + // Position of DATA_6 field. + TWAI_DATA_6_DATA_6_Pos = 0x0 + // Bit mask of DATA_6 field. + TWAI_DATA_6_DATA_6_Msk = 0xff + + // DATA_7: Data register 7. + // Position of DATA_7 field. + TWAI_DATA_7_DATA_7_Pos = 0x0 + // Bit mask of DATA_7 field. + TWAI_DATA_7_DATA_7_Msk = 0xff + + // DATA_8: Data register 8. + // Position of DATA_8 field. + TWAI_DATA_8_DATA_8_Pos = 0x0 + // Bit mask of DATA_8 field. + TWAI_DATA_8_DATA_8_Msk = 0xff + + // DATA_9: Data register 9. + // Position of DATA_9 field. + TWAI_DATA_9_DATA_9_Pos = 0x0 + // Bit mask of DATA_9 field. + TWAI_DATA_9_DATA_9_Msk = 0xff + + // DATA_10: Data register 10. + // Position of DATA_10 field. + TWAI_DATA_10_DATA_10_Pos = 0x0 + // Bit mask of DATA_10 field. + TWAI_DATA_10_DATA_10_Msk = 0xff + + // DATA_11: Data register 11. + // Position of DATA_11 field. + TWAI_DATA_11_DATA_11_Pos = 0x0 + // Bit mask of DATA_11 field. + TWAI_DATA_11_DATA_11_Msk = 0xff + + // DATA_12: Data register 12. + // Position of DATA_12 field. + TWAI_DATA_12_DATA_12_Pos = 0x0 + // Bit mask of DATA_12 field. + TWAI_DATA_12_DATA_12_Msk = 0xff + + // RX_MESSAGE_COUNTER: Received message counter register. + // Position of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_COUNTER_RX_MESSAGE_COUNTER_Pos = 0x0 + // Bit mask of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_COUNTER_RX_MESSAGE_COUNTER_Msk = 0x7f + + // CLOCK_DIVIDER: Clock divider register. + // Position of CD field. + TWAI_CLOCK_DIVIDER_CD_Pos = 0x0 + // Bit mask of CD field. + TWAI_CLOCK_DIVIDER_CD_Msk = 0xff + // Position of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Pos = 0x8 + // Bit mask of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Msk = 0x100 + // Bit CLOCK_OFF. + TWAI_CLOCK_DIVIDER_CLOCK_OFF = 0x100 + + // SW_STANDBY_CFG: Software configure standby pin directly. + // Position of SW_STANDBY_EN field. + TWAI_SW_STANDBY_CFG_SW_STANDBY_EN_Pos = 0x0 + // Bit mask of SW_STANDBY_EN field. + TWAI_SW_STANDBY_CFG_SW_STANDBY_EN_Msk = 0x1 + // Bit SW_STANDBY_EN. + TWAI_SW_STANDBY_CFG_SW_STANDBY_EN = 0x1 + // Position of SW_STANDBY_CLR field. + TWAI_SW_STANDBY_CFG_SW_STANDBY_CLR_Pos = 0x1 + // Bit mask of SW_STANDBY_CLR field. + TWAI_SW_STANDBY_CFG_SW_STANDBY_CLR_Msk = 0x2 + // Bit SW_STANDBY_CLR. + TWAI_SW_STANDBY_CFG_SW_STANDBY_CLR = 0x2 + + // HW_CFG: Hardware configure standby pin. + // Position of HW_STANDBY_EN field. + TWAI_HW_CFG_HW_STANDBY_EN_Pos = 0x0 + // Bit mask of HW_STANDBY_EN field. + TWAI_HW_CFG_HW_STANDBY_EN_Msk = 0x1 + // Bit HW_STANDBY_EN. + TWAI_HW_CFG_HW_STANDBY_EN = 0x1 + + // HW_STANDBY_CNT: Configure standby counter. + // Position of STANDBY_WAIT_CNT field. + TWAI_HW_STANDBY_CNT_STANDBY_WAIT_CNT_Pos = 0x0 + // Bit mask of STANDBY_WAIT_CNT field. + TWAI_HW_STANDBY_CNT_STANDBY_WAIT_CNT_Msk = 0xffffffff + + // IDLE_INTR_CNT: Configure idle interrupt counter. + // Position of IDLE_INTR_CNT field. + TWAI_IDLE_INTR_CNT_IDLE_INTR_CNT_Pos = 0x0 + // Bit mask of IDLE_INTR_CNT field. + TWAI_IDLE_INTR_CNT_IDLE_INTR_CNT_Msk = 0xffffffff + + // ECO_CFG: ECO configuration register. + // Position of RDN_ENA field. + TWAI_ECO_CFG_RDN_ENA_Pos = 0x0 + // Bit mask of RDN_ENA field. + TWAI_ECO_CFG_RDN_ENA_Msk = 0x1 + // Bit RDN_ENA. + TWAI_ECO_CFG_RDN_ENA = 0x1 + // Position of RDN_RESULT field. + TWAI_ECO_CFG_RDN_RESULT_Pos = 0x1 + // Bit mask of RDN_RESULT field. + TWAI_ECO_CFG_RDN_RESULT_Msk = 0x2 + // Bit RDN_RESULT. + TWAI_ECO_CFG_RDN_RESULT = 0x2 +) + +// Constants for UART0: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +const ( + // FIFO: FIFO data register + // Position of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9 + // Bit mask of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200 + // Bit SW_XON_INT_RAW. + UART_INT_RAW_SW_XON_INT_RAW = 0x200 + // Position of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa + // Bit mask of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400 + // Bit SW_XOFF_INT_RAW. + UART_INT_RAW_SW_XOFF_INT_RAW = 0x400 + // Position of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb + // Bit mask of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800 + // Bit GLITCH_DET_INT_RAW. + UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800 + // Position of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000 + // Position of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit TX_DONE_INT_RAW. + UART_INT_RAW_TX_DONE_INT_RAW = 0x4000 + // Position of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_RAW. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW = 0x8000 + // Position of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_RAW. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW = 0x10000 + // Position of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Msk = 0x20000 + // Bit RS485_CLASH_INT_RAW. + UART_INT_RAW_RS485_CLASH_INT_RAW = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_RAW. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000 + // Position of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13 + // Bit mask of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000 + // Bit WAKEUP_INT_RAW. + UART_INT_RAW_WAKEUP_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Pos = 0x9 + // Bit mask of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Msk = 0x200 + // Bit SW_XON_INT_ST. + UART_INT_ST_SW_XON_INT_ST = 0x200 + // Position of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa + // Bit mask of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400 + // Bit SW_XOFF_INT_ST. + UART_INT_ST_SW_XOFF_INT_ST = 0x400 + // Position of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800 + // Bit GLITCH_DET_INT_ST. + UART_INT_ST_GLITCH_DET_INT_ST = 0x800 + // Position of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ST. + UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ST. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000 + // Position of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000 + // Bit TX_DONE_INT_ST. + UART_INT_ST_TX_DONE_INT_ST = 0x4000 + // Position of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ST. + UART_INT_ST_RS485_PARITY_ERR_INT_ST = 0x8000 + // Position of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ST. + UART_INT_ST_RS485_FRM_ERR_INT_ST = 0x10000 + // Position of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Msk = 0x20000 + // Bit RS485_CLASH_INT_ST. + UART_INT_ST_RS485_CLASH_INT_ST = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ST. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000 + // Position of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13 + // Bit mask of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000 + // Bit WAKEUP_INT_ST. + UART_INT_ST_WAKEUP_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9 + // Bit mask of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200 + // Bit SW_XON_INT_ENA. + UART_INT_ENA_SW_XON_INT_ENA = 0x200 + // Position of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa + // Bit mask of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400 + // Bit SW_XOFF_INT_ENA. + UART_INT_ENA_SW_XOFF_INT_ENA = 0x400 + // Position of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800 + // Bit GLITCH_DET_INT_ENA. + UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800 + // Position of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000 + // Position of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit TX_DONE_INT_ENA. + UART_INT_ENA_TX_DONE_INT_ENA = 0x4000 + // Position of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ENA. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA = 0x8000 + // Position of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ENA. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA = 0x10000 + // Position of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Msk = 0x20000 + // Bit RS485_CLASH_INT_ENA. + UART_INT_ENA_RS485_CLASH_INT_ENA = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ENA. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000 + // Position of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13 + // Bit mask of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000 + // Bit WAKEUP_INT_ENA. + UART_INT_ENA_WAKEUP_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9 + // Bit mask of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200 + // Bit SW_XON_INT_CLR. + UART_INT_CLR_SW_XON_INT_CLR = 0x200 + // Position of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa + // Bit mask of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400 + // Bit SW_XOFF_INT_CLR. + UART_INT_CLR_SW_XOFF_INT_CLR = 0x400 + // Position of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb + // Bit mask of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800 + // Bit GLITCH_DET_INT_CLR. + UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800 + // Position of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000 + // Position of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit TX_DONE_INT_CLR. + UART_INT_CLR_TX_DONE_INT_CLR = 0x4000 + // Position of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_CLR. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR = 0x8000 + // Position of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_CLR. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR = 0x10000 + // Position of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Msk = 0x20000 + // Bit RS485_CLASH_INT_CLR. + UART_INT_CLR_RS485_CLASH_INT_CLR = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_CLR. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000 + // Position of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13 + // Bit mask of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000 + // Bit WAKEUP_INT_CLR. + UART_INT_CLR_WAKEUP_INT_CLR = 0x80000 + + // CLKDIV: Clock divider configuration + // Position of CLKDIV field. + UART_CLKDIV_CLKDIV_Pos = 0x0 + // Bit mask of CLKDIV field. + UART_CLKDIV_CLKDIV_Msk = 0xfff + // Position of FRAG field. + UART_CLKDIV_FRAG_Pos = 0x14 + // Bit mask of FRAG field. + UART_CLKDIV_FRAG_Msk = 0xf00000 + + // RX_FILT: Rx Filter configuration + // Position of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Pos = 0x0 + // Bit mask of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Msk = 0xff + // Position of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Pos = 0x8 + // Bit mask of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Msk = 0x100 + // Bit GLITCH_FILT_EN. + UART_RX_FILT_GLITCH_FILT_EN = 0x100 + + // STATUS: UART status register + // Position of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Pos = 0x0 + // Bit mask of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Msk = 0xff + // Position of DSRN field. + UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + UART_STATUS_DSRN = 0x2000 + // Position of CTSN field. + UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + UART_STATUS_CTSN = 0x4000 + // Position of RXD field. + UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + UART_STATUS_RXD = 0x8000 + // Position of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Pos = 0x10 + // Bit mask of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Msk = 0xff0000 + // Position of DTRN field. + UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + UART_STATUS_DTRN = 0x20000000 + // Position of RTSN field. + UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + UART_STATUS_RTSN = 0x40000000 + // Position of TXD field. + UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + UART_STATUS_TXD = 0x80000000 + + // CONF0: a + // Position of PARITY field. + UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + UART_CONF0_PARITY = 0x1 + // Position of PARITY_EN field. + UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + UART_CONF0_PARITY_EN = 0x2 + // Position of BIT_NUM field. + UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + UART_CONF0_BIT_NUM_Msk = 0xc + // Position of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of TXD_BRK field. + UART_CONF0_TXD_BRK_Pos = 0x6 + // Bit mask of TXD_BRK field. + UART_CONF0_TXD_BRK_Msk = 0x40 + // Bit TXD_BRK. + UART_CONF0_TXD_BRK = 0x40 + // Position of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Pos = 0x7 + // Bit mask of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Msk = 0x80 + // Bit IRDA_DPLX. + UART_CONF0_IRDA_DPLX = 0x80 + // Position of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Pos = 0x8 + // Bit mask of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Msk = 0x100 + // Bit IRDA_TX_EN. + UART_CONF0_IRDA_TX_EN = 0x100 + // Position of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Pos = 0x9 + // Bit mask of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Msk = 0x200 + // Bit IRDA_WCTL. + UART_CONF0_IRDA_WCTL = 0x200 + // Position of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Pos = 0xa + // Bit mask of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Msk = 0x400 + // Bit IRDA_TX_INV. + UART_CONF0_IRDA_TX_INV = 0x400 + // Position of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Pos = 0xb + // Bit mask of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Msk = 0x800 + // Bit IRDA_RX_INV. + UART_CONF0_IRDA_RX_INV = 0x800 + // Position of LOOPBACK field. + UART_CONF0_LOOPBACK_Pos = 0xc + // Bit mask of LOOPBACK field. + UART_CONF0_LOOPBACK_Msk = 0x1000 + // Bit LOOPBACK. + UART_CONF0_LOOPBACK = 0x1000 + // Position of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Pos = 0xd + // Bit mask of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Msk = 0x2000 + // Bit TX_FLOW_EN. + UART_CONF0_TX_FLOW_EN = 0x2000 + // Position of IRDA_EN field. + UART_CONF0_IRDA_EN_Pos = 0xe + // Bit mask of IRDA_EN field. + UART_CONF0_IRDA_EN_Msk = 0x4000 + // Bit IRDA_EN. + UART_CONF0_IRDA_EN = 0x4000 + // Position of RXD_INV field. + UART_CONF0_RXD_INV_Pos = 0xf + // Bit mask of RXD_INV field. + UART_CONF0_RXD_INV_Msk = 0x8000 + // Bit RXD_INV. + UART_CONF0_RXD_INV = 0x8000 + // Position of TXD_INV field. + UART_CONF0_TXD_INV_Pos = 0x10 + // Bit mask of TXD_INV field. + UART_CONF0_TXD_INV_Msk = 0x10000 + // Bit TXD_INV. + UART_CONF0_TXD_INV = 0x10000 + // Position of DIS_RX_DAT_OVF field. + UART_CONF0_DIS_RX_DAT_OVF_Pos = 0x11 + // Bit mask of DIS_RX_DAT_OVF field. + UART_CONF0_DIS_RX_DAT_OVF_Msk = 0x20000 + // Bit DIS_RX_DAT_OVF. + UART_CONF0_DIS_RX_DAT_OVF = 0x20000 + // Position of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Pos = 0x12 + // Bit mask of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Msk = 0x40000 + // Bit ERR_WR_MASK. + UART_CONF0_ERR_WR_MASK = 0x40000 + // Position of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Pos = 0x13 + // Bit mask of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Msk = 0x80000 + // Bit AUTOBAUD_EN. + UART_CONF0_AUTOBAUD_EN = 0x80000 + // Position of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Pos = 0x14 + // Bit mask of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Msk = 0x100000 + // Bit MEM_CLK_EN. + UART_CONF0_MEM_CLK_EN = 0x100000 + // Position of SW_RTS field. + UART_CONF0_SW_RTS_Pos = 0x15 + // Bit mask of SW_RTS field. + UART_CONF0_SW_RTS_Msk = 0x200000 + // Bit SW_RTS. + UART_CONF0_SW_RTS = 0x200000 + // Position of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Pos = 0x16 + // Bit mask of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Msk = 0x400000 + // Bit RXFIFO_RST. + UART_CONF0_RXFIFO_RST = 0x400000 + // Position of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Pos = 0x17 + // Bit mask of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Msk = 0x800000 + // Bit TXFIFO_RST. + UART_CONF0_TXFIFO_RST = 0x800000 + + // CONF1: Configuration register 1 + // Position of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0xff + // Position of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0x8 + // Bit mask of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0xff00 + // Position of CTS_INV field. + UART_CONF1_CTS_INV_Pos = 0x10 + // Bit mask of CTS_INV field. + UART_CONF1_CTS_INV_Msk = 0x10000 + // Bit CTS_INV. + UART_CONF1_CTS_INV = 0x10000 + // Position of DSR_INV field. + UART_CONF1_DSR_INV_Pos = 0x11 + // Bit mask of DSR_INV field. + UART_CONF1_DSR_INV_Msk = 0x20000 + // Bit DSR_INV. + UART_CONF1_DSR_INV = 0x20000 + // Position of RTS_INV field. + UART_CONF1_RTS_INV_Pos = 0x12 + // Bit mask of RTS_INV field. + UART_CONF1_RTS_INV_Msk = 0x40000 + // Bit RTS_INV. + UART_CONF1_RTS_INV = 0x40000 + // Position of DTR_INV field. + UART_CONF1_DTR_INV_Pos = 0x13 + // Bit mask of DTR_INV field. + UART_CONF1_DTR_INV_Msk = 0x80000 + // Bit DTR_INV. + UART_CONF1_DTR_INV = 0x80000 + // Position of SW_DTR field. + UART_CONF1_SW_DTR_Pos = 0x14 + // Bit mask of SW_DTR field. + UART_CONF1_SW_DTR_Msk = 0x100000 + // Bit SW_DTR. + UART_CONF1_SW_DTR = 0x100000 + // Position of CLK_EN field. + UART_CONF1_CLK_EN_Pos = 0x15 + // Bit mask of CLK_EN field. + UART_CONF1_CLK_EN_Msk = 0x200000 + // Bit CLK_EN. + UART_CONF1_CLK_EN = 0x200000 + + // HWFC_CONF: Hardware flow-control configuration + // Position of RX_FLOW_THRHD field. + UART_HWFC_CONF_RX_FLOW_THRHD_Pos = 0x0 + // Bit mask of RX_FLOW_THRHD field. + UART_HWFC_CONF_RX_FLOW_THRHD_Msk = 0xff + // Position of RX_FLOW_EN field. + UART_HWFC_CONF_RX_FLOW_EN_Pos = 0x8 + // Bit mask of RX_FLOW_EN field. + UART_HWFC_CONF_RX_FLOW_EN_Msk = 0x100 + // Bit RX_FLOW_EN. + UART_HWFC_CONF_RX_FLOW_EN = 0x100 + + // SLEEP_CONF0: UART sleep configure register 0 + // Position of WK_CHAR1 field. + UART_SLEEP_CONF0_WK_CHAR1_Pos = 0x0 + // Bit mask of WK_CHAR1 field. + UART_SLEEP_CONF0_WK_CHAR1_Msk = 0xff + // Position of WK_CHAR2 field. + UART_SLEEP_CONF0_WK_CHAR2_Pos = 0x8 + // Bit mask of WK_CHAR2 field. + UART_SLEEP_CONF0_WK_CHAR2_Msk = 0xff00 + // Position of WK_CHAR3 field. + UART_SLEEP_CONF0_WK_CHAR3_Pos = 0x10 + // Bit mask of WK_CHAR3 field. + UART_SLEEP_CONF0_WK_CHAR3_Msk = 0xff0000 + // Position of WK_CHAR4 field. + UART_SLEEP_CONF0_WK_CHAR4_Pos = 0x18 + // Bit mask of WK_CHAR4 field. + UART_SLEEP_CONF0_WK_CHAR4_Msk = 0xff000000 + + // SLEEP_CONF1: UART sleep configure register 1 + // Position of WK_CHAR0 field. + UART_SLEEP_CONF1_WK_CHAR0_Pos = 0x0 + // Bit mask of WK_CHAR0 field. + UART_SLEEP_CONF1_WK_CHAR0_Msk = 0xff + + // SLEEP_CONF2: UART sleep configure register 2 + // Position of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Pos = 0x0 + // Bit mask of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Msk = 0x3ff + // Position of RX_WAKE_UP_THRHD field. + UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Pos = 0xa + // Bit mask of RX_WAKE_UP_THRHD field. + UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Msk = 0x3fc00 + // Position of WK_CHAR_NUM field. + UART_SLEEP_CONF2_WK_CHAR_NUM_Pos = 0x12 + // Bit mask of WK_CHAR_NUM field. + UART_SLEEP_CONF2_WK_CHAR_NUM_Msk = 0x1c0000 + // Position of WK_CHAR_MASK field. + UART_SLEEP_CONF2_WK_CHAR_MASK_Pos = 0x15 + // Bit mask of WK_CHAR_MASK field. + UART_SLEEP_CONF2_WK_CHAR_MASK_Msk = 0x3e00000 + // Position of WK_MODE_SEL field. + UART_SLEEP_CONF2_WK_MODE_SEL_Pos = 0x1a + // Bit mask of WK_MODE_SEL field. + UART_SLEEP_CONF2_WK_MODE_SEL_Msk = 0xc000000 + + // SWFC_CONF0: Software flow-control character configuration + // Position of XON_CHAR field. + UART_SWFC_CONF0_XON_CHAR_Pos = 0x0 + // Bit mask of XON_CHAR field. + UART_SWFC_CONF0_XON_CHAR_Msk = 0xff + // Position of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Pos = 0x8 + // Bit mask of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Msk = 0xff00 + // Position of XON_XOFF_STILL_SEND field. + UART_SWFC_CONF0_XON_XOFF_STILL_SEND_Pos = 0x10 + // Bit mask of XON_XOFF_STILL_SEND field. + UART_SWFC_CONF0_XON_XOFF_STILL_SEND_Msk = 0x10000 + // Bit XON_XOFF_STILL_SEND. + UART_SWFC_CONF0_XON_XOFF_STILL_SEND = 0x10000 + // Position of SW_FLOW_CON_EN field. + UART_SWFC_CONF0_SW_FLOW_CON_EN_Pos = 0x11 + // Bit mask of SW_FLOW_CON_EN field. + UART_SWFC_CONF0_SW_FLOW_CON_EN_Msk = 0x20000 + // Bit SW_FLOW_CON_EN. + UART_SWFC_CONF0_SW_FLOW_CON_EN = 0x20000 + // Position of XONOFF_DEL field. + UART_SWFC_CONF0_XONOFF_DEL_Pos = 0x12 + // Bit mask of XONOFF_DEL field. + UART_SWFC_CONF0_XONOFF_DEL_Msk = 0x40000 + // Bit XONOFF_DEL. + UART_SWFC_CONF0_XONOFF_DEL = 0x40000 + // Position of FORCE_XON field. + UART_SWFC_CONF0_FORCE_XON_Pos = 0x13 + // Bit mask of FORCE_XON field. + UART_SWFC_CONF0_FORCE_XON_Msk = 0x80000 + // Bit FORCE_XON. + UART_SWFC_CONF0_FORCE_XON = 0x80000 + // Position of FORCE_XOFF field. + UART_SWFC_CONF0_FORCE_XOFF_Pos = 0x14 + // Bit mask of FORCE_XOFF field. + UART_SWFC_CONF0_FORCE_XOFF_Msk = 0x100000 + // Bit FORCE_XOFF. + UART_SWFC_CONF0_FORCE_XOFF = 0x100000 + // Position of SEND_XON field. + UART_SWFC_CONF0_SEND_XON_Pos = 0x15 + // Bit mask of SEND_XON field. + UART_SWFC_CONF0_SEND_XON_Msk = 0x200000 + // Bit SEND_XON. + UART_SWFC_CONF0_SEND_XON = 0x200000 + // Position of SEND_XOFF field. + UART_SWFC_CONF0_SEND_XOFF_Pos = 0x16 + // Bit mask of SEND_XOFF field. + UART_SWFC_CONF0_SEND_XOFF_Msk = 0x400000 + // Bit SEND_XOFF. + UART_SWFC_CONF0_SEND_XOFF = 0x400000 + + // SWFC_CONF1: Software flow-control character configuration + // Position of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x0 + // Bit mask of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0xff + // Position of XOFF_THRESHOLD field. + UART_SWFC_CONF1_XOFF_THRESHOLD_Pos = 0x8 + // Bit mask of XOFF_THRESHOLD field. + UART_SWFC_CONF1_XOFF_THRESHOLD_Msk = 0xff00 + + // TXBRK_CONF: Tx Break character configuration + // Position of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Pos = 0x0 + // Bit mask of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Msk = 0xff + + // IDLE_CONF: Frame-end idle configuration + // Position of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Pos = 0x0 + // Bit mask of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Msk = 0x3ff + // Position of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Pos = 0xa + // Bit mask of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Msk = 0xffc00 + + // RS485_CONF: RS485 mode configuration + // Position of RS485_EN field. + UART_RS485_CONF_RS485_EN_Pos = 0x0 + // Bit mask of RS485_EN field. + UART_RS485_CONF_RS485_EN_Msk = 0x1 + // Bit RS485_EN. + UART_RS485_CONF_RS485_EN = 0x1 + // Position of DL0_EN field. + UART_RS485_CONF_DL0_EN_Pos = 0x1 + // Bit mask of DL0_EN field. + UART_RS485_CONF_DL0_EN_Msk = 0x2 + // Bit DL0_EN. + UART_RS485_CONF_DL0_EN = 0x2 + // Position of DL1_EN field. + UART_RS485_CONF_DL1_EN_Pos = 0x2 + // Bit mask of DL1_EN field. + UART_RS485_CONF_DL1_EN_Msk = 0x4 + // Bit DL1_EN. + UART_RS485_CONF_DL1_EN = 0x4 + // Position of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Pos = 0x3 + // Bit mask of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Msk = 0x8 + // Bit RS485TX_RX_EN. + UART_RS485_CONF_RS485TX_RX_EN = 0x8 + // Position of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Pos = 0x4 + // Bit mask of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Msk = 0x10 + // Bit RS485RXBY_TX_EN. + UART_RS485_CONF_RS485RXBY_TX_EN = 0x10 + // Position of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Pos = 0x5 + // Bit mask of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Msk = 0x20 + // Bit RS485_RX_DLY_NUM. + UART_RS485_CONF_RS485_RX_DLY_NUM = 0x20 + // Position of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Pos = 0x6 + // Bit mask of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Msk = 0x3c0 + + // AT_CMD_PRECNT: Pre-sequence timing configuration + // Position of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Pos = 0x0 + // Bit mask of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Msk = 0xffff + + // AT_CMD_POSTCNT: Post-sequence timing configuration + // Position of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Pos = 0x0 + // Bit mask of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Msk = 0xffff + + // AT_CMD_GAPTOUT: Timeout configuration + // Position of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Pos = 0x0 + // Bit mask of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Msk = 0xffff + + // AT_CMD_CHAR: AT escape sequence detection configuration + // Position of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Pos = 0x0 + // Bit mask of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Msk = 0xff + // Position of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Pos = 0x8 + // Bit mask of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Msk = 0xff00 + + // MEM_CONF: UART memory power configuration + // Position of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x19 + // Bit mask of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x2000000 + // Bit MEM_FORCE_PD. + UART_MEM_CONF_MEM_FORCE_PD = 0x2000000 + // Position of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1a + // Bit mask of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x4000000 + // Bit MEM_FORCE_PU. + UART_MEM_CONF_MEM_FORCE_PU = 0x4000000 + + // TOUT_CONF: UART threshold and allocation configuration + // Position of RX_TOUT_EN field. + UART_TOUT_CONF_RX_TOUT_EN_Pos = 0x0 + // Bit mask of RX_TOUT_EN field. + UART_TOUT_CONF_RX_TOUT_EN_Msk = 0x1 + // Bit RX_TOUT_EN. + UART_TOUT_CONF_RX_TOUT_EN = 0x1 + // Position of RX_TOUT_FLOW_DIS field. + UART_TOUT_CONF_RX_TOUT_FLOW_DIS_Pos = 0x1 + // Bit mask of RX_TOUT_FLOW_DIS field. + UART_TOUT_CONF_RX_TOUT_FLOW_DIS_Msk = 0x2 + // Bit RX_TOUT_FLOW_DIS. + UART_TOUT_CONF_RX_TOUT_FLOW_DIS = 0x2 + // Position of RX_TOUT_THRHD field. + UART_TOUT_CONF_RX_TOUT_THRHD_Pos = 0x2 + // Bit mask of RX_TOUT_THRHD field. + UART_TOUT_CONF_RX_TOUT_THRHD_Msk = 0xffc + + // MEM_TX_STATUS: Tx-SRAM write and read offset address. + // Position of TX_SRAM_WADDR field. + UART_MEM_TX_STATUS_TX_SRAM_WADDR_Pos = 0x0 + // Bit mask of TX_SRAM_WADDR field. + UART_MEM_TX_STATUS_TX_SRAM_WADDR_Msk = 0xff + // Position of TX_SRAM_RADDR field. + UART_MEM_TX_STATUS_TX_SRAM_RADDR_Pos = 0x9 + // Bit mask of TX_SRAM_RADDR field. + UART_MEM_TX_STATUS_TX_SRAM_RADDR_Msk = 0x1fe00 + + // MEM_RX_STATUS: Rx-SRAM write and read offset address. + // Position of RX_SRAM_RADDR field. + UART_MEM_RX_STATUS_RX_SRAM_RADDR_Pos = 0x0 + // Bit mask of RX_SRAM_RADDR field. + UART_MEM_RX_STATUS_RX_SRAM_RADDR_Msk = 0xff + // Position of RX_SRAM_WADDR field. + UART_MEM_RX_STATUS_RX_SRAM_WADDR_Pos = 0x9 + // Bit mask of RX_SRAM_WADDR field. + UART_MEM_RX_STATUS_RX_SRAM_WADDR_Msk = 0x1fe00 + + // FSM_STATUS: UART transmit and receive status. + // Position of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0 + // Bit mask of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf + // Position of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4 + // Bit mask of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0 + + // POSPULSE: Autobaud high pulse register + // Position of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Msk = 0xfff + + // NEGPULSE: Autobaud low pulse register + // Position of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Msk = 0xfff + + // LOWPULSE: Autobaud minimum low pulse duration register + // Position of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Msk = 0xfff + + // HIGHPULSE: Autobaud minimum high pulse duration register + // Position of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Msk = 0xfff + + // RXD_CNT: Autobaud edge change count register + // Position of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0 + // Bit mask of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff + + // CLK_CONF: UART core clock configuration + // Position of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Pos = 0x18 + // Bit mask of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Msk = 0x1000000 + // Bit TX_SCLK_EN. + UART_CLK_CONF_TX_SCLK_EN = 0x1000000 + // Position of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Pos = 0x19 + // Bit mask of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Msk = 0x2000000 + // Bit SCLK_EN. + UART_CLK_CONF_SCLK_EN = 0x2000000 + // Position of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Pos = 0x1a + // Bit mask of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Msk = 0x4000000 + // Bit TX_RST_CORE. + UART_CLK_CONF_TX_RST_CORE = 0x4000000 + // Position of RST_CORE field. + UART_CLK_CONF_RST_CORE_Pos = 0x1b + // Bit mask of RST_CORE field. + UART_CLK_CONF_RST_CORE_Msk = 0x8000000 + // Bit RST_CORE. + UART_CLK_CONF_RST_CORE = 0x8000000 + + // DATE: UART Version register + // Position of DATE field. + UART_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UART_DATE_DATE_Msk = 0xffffffff + + // AFIFO_STATUS: UART AFIFO Status + // Position of TX_AFIFO_FULL field. + UART_AFIFO_STATUS_TX_AFIFO_FULL_Pos = 0x0 + // Bit mask of TX_AFIFO_FULL field. + UART_AFIFO_STATUS_TX_AFIFO_FULL_Msk = 0x1 + // Bit TX_AFIFO_FULL. + UART_AFIFO_STATUS_TX_AFIFO_FULL = 0x1 + // Position of TX_AFIFO_EMPTY field. + UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Pos = 0x1 + // Bit mask of TX_AFIFO_EMPTY field. + UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Msk = 0x2 + // Bit TX_AFIFO_EMPTY. + UART_AFIFO_STATUS_TX_AFIFO_EMPTY = 0x2 + // Position of RX_AFIFO_FULL field. + UART_AFIFO_STATUS_RX_AFIFO_FULL_Pos = 0x2 + // Bit mask of RX_AFIFO_FULL field. + UART_AFIFO_STATUS_RX_AFIFO_FULL_Msk = 0x4 + // Bit RX_AFIFO_FULL. + UART_AFIFO_STATUS_RX_AFIFO_FULL = 0x4 + // Position of RX_AFIFO_EMPTY field. + UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Pos = 0x3 + // Bit mask of RX_AFIFO_EMPTY field. + UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Msk = 0x8 + // Bit RX_AFIFO_EMPTY. + UART_AFIFO_STATUS_RX_AFIFO_EMPTY = 0x8 + + // REG_UPDATE: UART Registers Configuration Update register + // Position of REG_UPDATE field. + UART_REG_UPDATE_REG_UPDATE_Pos = 0x0 + // Bit mask of REG_UPDATE field. + UART_REG_UPDATE_REG_UPDATE_Msk = 0x1 + // Bit REG_UPDATE. + UART_REG_UPDATE_REG_UPDATE = 0x1 + + // ID: UART ID register + // Position of ID field. + UART_ID_ID_Pos = 0x0 + // Bit mask of ID field. + UART_ID_ID_Msk = 0xffffffff +) + +// Constants for UHCI0: Universal Host Controller Interface 0 +const ( + // CONF0: a + // Position of TX_RST field. + UHCI_CONF0_TX_RST_Pos = 0x0 + // Bit mask of TX_RST field. + UHCI_CONF0_TX_RST_Msk = 0x1 + // Bit TX_RST. + UHCI_CONF0_TX_RST = 0x1 + // Position of RX_RST field. + UHCI_CONF0_RX_RST_Pos = 0x1 + // Bit mask of RX_RST field. + UHCI_CONF0_RX_RST_Msk = 0x2 + // Bit RX_RST. + UHCI_CONF0_RX_RST = 0x2 + // Position of UART0_CE field. + UHCI_CONF0_UART0_CE_Pos = 0x2 + // Bit mask of UART0_CE field. + UHCI_CONF0_UART0_CE_Msk = 0x4 + // Bit UART0_CE. + UHCI_CONF0_UART0_CE = 0x4 + // Position of UART1_CE field. + UHCI_CONF0_UART1_CE_Pos = 0x3 + // Bit mask of UART1_CE field. + UHCI_CONF0_UART1_CE_Msk = 0x8 + // Bit UART1_CE. + UHCI_CONF0_UART1_CE = 0x8 + // Position of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Pos = 0x5 + // Bit mask of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Msk = 0x20 + // Bit SEPER_EN. + UHCI_CONF0_SEPER_EN = 0x20 + // Position of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Pos = 0x6 + // Bit mask of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Msk = 0x40 + // Bit HEAD_EN. + UHCI_CONF0_HEAD_EN = 0x40 + // Position of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Pos = 0x7 + // Bit mask of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Msk = 0x80 + // Bit CRC_REC_EN. + UHCI_CONF0_CRC_REC_EN = 0x80 + // Position of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Pos = 0x8 + // Bit mask of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Msk = 0x100 + // Bit UART_IDLE_EOF_EN. + UHCI_CONF0_UART_IDLE_EOF_EN = 0x100 + // Position of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Pos = 0x9 + // Bit mask of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Msk = 0x200 + // Bit LEN_EOF_EN. + UHCI_CONF0_LEN_EOF_EN = 0x200 + // Position of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Pos = 0xa + // Bit mask of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Msk = 0x400 + // Bit ENCODE_CRC_EN. + UHCI_CONF0_ENCODE_CRC_EN = 0x400 + // Position of CLK_EN field. + UHCI_CONF0_CLK_EN_Pos = 0xb + // Bit mask of CLK_EN field. + UHCI_CONF0_CLK_EN_Msk = 0x800 + // Bit CLK_EN. + UHCI_CONF0_CLK_EN = 0x800 + // Position of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Pos = 0xc + // Bit mask of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Msk = 0x1000 + // Bit UART_RX_BRK_EOF_EN. + UHCI_CONF0_UART_RX_BRK_EOF_EN = 0x1000 + + // INT_RAW: a + // Position of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Pos = 0x0 + // Bit mask of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Msk = 0x1 + // Bit RX_START_INT_RAW. + UHCI_INT_RAW_RX_START_INT_RAW = 0x1 + // Position of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Pos = 0x1 + // Bit mask of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Msk = 0x2 + // Bit TX_START_INT_RAW. + UHCI_INT_RAW_TX_START_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + UHCI_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + UHCI_INT_RAW_TX_HUNG_INT_RAW = 0x8 + // Position of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW = 0x10 + // Position of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW = 0x20 + // Position of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x6 + // Bit mask of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x40 + // Bit OUT_EOF_INT_RAW. + UHCI_INT_RAW_OUT_EOF_INT_RAW = 0x40 + // Position of APP_CTRL0_INT_RAW field. + UHCI_INT_RAW_APP_CTRL0_INT_RAW_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_RAW field. + UHCI_INT_RAW_APP_CTRL0_INT_RAW_Msk = 0x80 + // Bit APP_CTRL0_INT_RAW. + UHCI_INT_RAW_APP_CTRL0_INT_RAW = 0x80 + // Position of APP_CTRL1_INT_RAW field. + UHCI_INT_RAW_APP_CTRL1_INT_RAW_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_RAW field. + UHCI_INT_RAW_APP_CTRL1_INT_RAW_Msk = 0x100 + // Bit APP_CTRL1_INT_RAW. + UHCI_INT_RAW_APP_CTRL1_INT_RAW = 0x100 + + // INT_ST: a + // Position of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Pos = 0x0 + // Bit mask of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Msk = 0x1 + // Bit RX_START_INT_ST. + UHCI_INT_ST_RX_START_INT_ST = 0x1 + // Position of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Pos = 0x1 + // Bit mask of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Msk = 0x2 + // Bit TX_START_INT_ST. + UHCI_INT_ST_TX_START_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + UHCI_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + UHCI_INT_ST_TX_HUNG_INT_ST = 0x8 + // Position of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_ST. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST = 0x10 + // Position of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_ST. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST = 0x20 + // Position of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_ST. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST = 0x40 + // Position of APP_CTRL0_INT_ST field. + UHCI_INT_ST_APP_CTRL0_INT_ST_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_ST field. + UHCI_INT_ST_APP_CTRL0_INT_ST_Msk = 0x80 + // Bit APP_CTRL0_INT_ST. + UHCI_INT_ST_APP_CTRL0_INT_ST = 0x80 + // Position of APP_CTRL1_INT_ST field. + UHCI_INT_ST_APP_CTRL1_INT_ST_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_ST field. + UHCI_INT_ST_APP_CTRL1_INT_ST_Msk = 0x100 + // Bit APP_CTRL1_INT_ST. + UHCI_INT_ST_APP_CTRL1_INT_ST = 0x100 + + // INT_ENA: a + // Position of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Pos = 0x0 + // Bit mask of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Msk = 0x1 + // Bit RX_START_INT_ENA. + UHCI_INT_ENA_RX_START_INT_ENA = 0x1 + // Position of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Pos = 0x1 + // Bit mask of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Msk = 0x2 + // Bit TX_START_INT_ENA. + UHCI_INT_ENA_TX_START_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + UHCI_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + UHCI_INT_ENA_TX_HUNG_INT_ENA = 0x8 + // Position of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA = 0x10 + // Position of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA = 0x20 + // Position of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_ENA. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA = 0x40 + // Position of APP_CTRL0_INT_ENA field. + UHCI_INT_ENA_APP_CTRL0_INT_ENA_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_ENA field. + UHCI_INT_ENA_APP_CTRL0_INT_ENA_Msk = 0x80 + // Bit APP_CTRL0_INT_ENA. + UHCI_INT_ENA_APP_CTRL0_INT_ENA = 0x80 + // Position of APP_CTRL1_INT_ENA field. + UHCI_INT_ENA_APP_CTRL1_INT_ENA_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_ENA field. + UHCI_INT_ENA_APP_CTRL1_INT_ENA_Msk = 0x100 + // Bit APP_CTRL1_INT_ENA. + UHCI_INT_ENA_APP_CTRL1_INT_ENA = 0x100 + + // INT_CLR: a + // Position of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Pos = 0x0 + // Bit mask of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Msk = 0x1 + // Bit RX_START_INT_CLR. + UHCI_INT_CLR_RX_START_INT_CLR = 0x1 + // Position of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Pos = 0x1 + // Bit mask of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Msk = 0x2 + // Bit TX_START_INT_CLR. + UHCI_INT_CLR_TX_START_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + UHCI_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + UHCI_INT_CLR_TX_HUNG_INT_CLR = 0x8 + // Position of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR = 0x10 + // Position of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR = 0x20 + // Position of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_CLR. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR = 0x40 + // Position of APP_CTRL0_INT_CLR field. + UHCI_INT_CLR_APP_CTRL0_INT_CLR_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_CLR field. + UHCI_INT_CLR_APP_CTRL0_INT_CLR_Msk = 0x80 + // Bit APP_CTRL0_INT_CLR. + UHCI_INT_CLR_APP_CTRL0_INT_CLR = 0x80 + // Position of APP_CTRL1_INT_CLR field. + UHCI_INT_CLR_APP_CTRL1_INT_CLR_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_CLR field. + UHCI_INT_CLR_APP_CTRL1_INT_CLR_Msk = 0x100 + // Bit APP_CTRL1_INT_CLR. + UHCI_INT_CLR_APP_CTRL1_INT_CLR = 0x100 + + // CONF1: a + // Position of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Pos = 0x0 + // Bit mask of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Msk = 0x1 + // Bit CHECK_SUM_EN. + UHCI_CONF1_CHECK_SUM_EN = 0x1 + // Position of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Pos = 0x1 + // Bit mask of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Msk = 0x2 + // Bit CHECK_SEQ_EN. + UHCI_CONF1_CHECK_SEQ_EN = 0x2 + // Position of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Pos = 0x2 + // Bit mask of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Msk = 0x4 + // Bit CRC_DISABLE. + UHCI_CONF1_CRC_DISABLE = 0x4 + // Position of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Pos = 0x3 + // Bit mask of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Msk = 0x8 + // Bit SAVE_HEAD. + UHCI_CONF1_SAVE_HEAD = 0x8 + // Position of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Pos = 0x4 + // Bit mask of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Msk = 0x10 + // Bit TX_CHECK_SUM_RE. + UHCI_CONF1_TX_CHECK_SUM_RE = 0x10 + // Position of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Pos = 0x5 + // Bit mask of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Msk = 0x20 + // Bit TX_ACK_NUM_RE. + UHCI_CONF1_TX_ACK_NUM_RE = 0x20 + // Position of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Pos = 0x7 + // Bit mask of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Msk = 0x80 + // Bit WAIT_SW_START. + UHCI_CONF1_WAIT_SW_START = 0x80 + // Position of SW_START field. + UHCI_CONF1_SW_START_Pos = 0x8 + // Bit mask of SW_START field. + UHCI_CONF1_SW_START_Msk = 0x100 + // Bit SW_START. + UHCI_CONF1_SW_START = 0x100 + + // STATE0: a + // Position of RX_ERR_CAUSE field. + UHCI_STATE0_RX_ERR_CAUSE_Pos = 0x0 + // Bit mask of RX_ERR_CAUSE field. + UHCI_STATE0_RX_ERR_CAUSE_Msk = 0x7 + // Position of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Pos = 0x3 + // Bit mask of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Msk = 0x38 + + // STATE1: a + // Position of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Pos = 0x0 + // Bit mask of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Msk = 0x7 + + // ESCAPE_CONF: a + // Position of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Pos = 0x0 + // Bit mask of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Msk = 0x1 + // Bit TX_C0_ESC_EN. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN = 0x1 + // Position of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Pos = 0x1 + // Bit mask of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Msk = 0x2 + // Bit TX_DB_ESC_EN. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN = 0x2 + // Position of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Pos = 0x2 + // Bit mask of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Msk = 0x4 + // Bit TX_11_ESC_EN. + UHCI_ESCAPE_CONF_TX_11_ESC_EN = 0x4 + // Position of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Pos = 0x3 + // Bit mask of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Msk = 0x8 + // Bit TX_13_ESC_EN. + UHCI_ESCAPE_CONF_TX_13_ESC_EN = 0x8 + // Position of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Pos = 0x4 + // Bit mask of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Msk = 0x10 + // Bit RX_C0_ESC_EN. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN = 0x10 + // Position of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Pos = 0x5 + // Bit mask of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Msk = 0x20 + // Bit RX_DB_ESC_EN. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN = 0x20 + // Position of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Pos = 0x6 + // Bit mask of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Msk = 0x40 + // Bit RX_11_ESC_EN. + UHCI_ESCAPE_CONF_RX_11_ESC_EN = 0x40 + // Position of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Pos = 0x7 + // Bit mask of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Msk = 0x80 + // Bit RX_13_ESC_EN. + UHCI_ESCAPE_CONF_RX_13_ESC_EN = 0x80 + + // HUNG_CONF: a + // Position of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Pos = 0x0 + // Bit mask of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Msk = 0xff + // Position of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit TXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA = 0x800 + // Position of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Pos = 0xc + // Bit mask of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Msk = 0xff000 + // Position of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Pos = 0x14 + // Bit mask of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Msk = 0x700000 + // Position of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Pos = 0x17 + // Bit mask of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Msk = 0x800000 + // Bit RXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA = 0x800000 + + // ACK_NUM: a + // Position of ACK_NUM field. + UHCI_ACK_NUM_ACK_NUM_Pos = 0x0 + // Bit mask of ACK_NUM field. + UHCI_ACK_NUM_ACK_NUM_Msk = 0x7 + // Position of LOAD field. + UHCI_ACK_NUM_LOAD_Pos = 0x3 + // Bit mask of LOAD field. + UHCI_ACK_NUM_LOAD_Msk = 0x8 + // Bit LOAD. + UHCI_ACK_NUM_LOAD = 0x8 + + // RX_HEAD: a + // Position of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Pos = 0x0 + // Bit mask of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Msk = 0xffffffff + + // QUICK_SENT: a + // Position of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Pos = 0x0 + // Bit mask of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Msk = 0x7 + // Position of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Pos = 0x3 + // Bit mask of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Msk = 0x8 + // Bit SINGLE_SEND_EN. + UHCI_QUICK_SENT_SINGLE_SEND_EN = 0x8 + // Position of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Pos = 0x4 + // Bit mask of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Msk = 0x70 + // Position of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Pos = 0x7 + // Bit mask of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Msk = 0x80 + // Bit ALWAYS_SEND_EN. + UHCI_QUICK_SENT_ALWAYS_SEND_EN = 0x80 + + // REG_Q0_WORD0: a + // Position of SEND_Q0_WORD0 field. + UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Pos = 0x0 + // Bit mask of SEND_Q0_WORD0 field. + UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Msk = 0xffffffff + + // REG_Q0_WORD1: a + // Position of SEND_Q0_WORD1 field. + UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Pos = 0x0 + // Bit mask of SEND_Q0_WORD1 field. + UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Msk = 0xffffffff + + // REG_Q1_WORD0: a + // Position of SEND_Q1_WORD0 field. + UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Pos = 0x0 + // Bit mask of SEND_Q1_WORD0 field. + UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Msk = 0xffffffff + + // REG_Q1_WORD1: a + // Position of SEND_Q1_WORD1 field. + UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Pos = 0x0 + // Bit mask of SEND_Q1_WORD1 field. + UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Msk = 0xffffffff + + // REG_Q2_WORD0: a + // Position of SEND_Q2_WORD0 field. + UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Pos = 0x0 + // Bit mask of SEND_Q2_WORD0 field. + UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Msk = 0xffffffff + + // REG_Q2_WORD1: a + // Position of SEND_Q2_WORD1 field. + UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Pos = 0x0 + // Bit mask of SEND_Q2_WORD1 field. + UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Msk = 0xffffffff + + // REG_Q3_WORD0: a + // Position of SEND_Q3_WORD0 field. + UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Pos = 0x0 + // Bit mask of SEND_Q3_WORD0 field. + UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Msk = 0xffffffff + + // REG_Q3_WORD1: a + // Position of SEND_Q3_WORD1 field. + UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Pos = 0x0 + // Bit mask of SEND_Q3_WORD1 field. + UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Msk = 0xffffffff + + // REG_Q4_WORD0: a + // Position of SEND_Q4_WORD0 field. + UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Pos = 0x0 + // Bit mask of SEND_Q4_WORD0 field. + UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Msk = 0xffffffff + + // REG_Q4_WORD1: a + // Position of SEND_Q4_WORD1 field. + UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Pos = 0x0 + // Bit mask of SEND_Q4_WORD1 field. + UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Msk = 0xffffffff + + // REG_Q5_WORD0: a + // Position of SEND_Q5_WORD0 field. + UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Pos = 0x0 + // Bit mask of SEND_Q5_WORD0 field. + UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Msk = 0xffffffff + + // REG_Q5_WORD1: a + // Position of SEND_Q5_WORD1 field. + UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Pos = 0x0 + // Bit mask of SEND_Q5_WORD1 field. + UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Msk = 0xffffffff + + // REG_Q6_WORD0: a + // Position of SEND_Q6_WORD0 field. + UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Pos = 0x0 + // Bit mask of SEND_Q6_WORD0 field. + UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Msk = 0xffffffff + + // REG_Q6_WORD1: a + // Position of SEND_Q6_WORD1 field. + UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Pos = 0x0 + // Bit mask of SEND_Q6_WORD1 field. + UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Msk = 0xffffffff + + // ESC_CONF0: a + // Position of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Pos = 0x0 + // Bit mask of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Msk = 0xff + // Position of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Pos = 0x8 + // Bit mask of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Msk = 0xff00 + // Position of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Pos = 0x10 + // Bit mask of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Msk = 0xff0000 + + // ESC_CONF1: a + // Position of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Pos = 0x0 + // Bit mask of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Msk = 0xff + // Position of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Msk = 0xff0000 + + // ESC_CONF2: a + // Position of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Pos = 0x0 + // Bit mask of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Msk = 0xff + // Position of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Msk = 0xff0000 + + // ESC_CONF3: a + // Position of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Pos = 0x0 + // Bit mask of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Msk = 0xff + // Position of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Msk = 0xff0000 + + // PKT_THRES: a + // Position of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Pos = 0x0 + // Bit mask of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Msk = 0x1fff + + // DATE: a + // Position of DATE field. + UHCI_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UHCI_DATE_DATE_Msk = 0xffffffff +) + +// Constants for USB_DEVICE: Full-speed USB Serial/JTAG Controller +const ( + // EP1: FIFO access for the CDC-ACM data IN and OUT endpoints. + // Position of RDWR_BYTE field. + USB_DEVICE_EP1_RDWR_BYTE_Pos = 0x0 + // Bit mask of RDWR_BYTE field. + USB_DEVICE_EP1_RDWR_BYTE_Msk = 0xff + + // EP1_CONF: Configuration and control registers for the CDC-ACM FIFOs. + // Position of WR_DONE field. + USB_DEVICE_EP1_CONF_WR_DONE_Pos = 0x0 + // Bit mask of WR_DONE field. + USB_DEVICE_EP1_CONF_WR_DONE_Msk = 0x1 + // Bit WR_DONE. + USB_DEVICE_EP1_CONF_WR_DONE = 0x1 + // Position of SERIAL_IN_EP_DATA_FREE field. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE_Pos = 0x1 + // Bit mask of SERIAL_IN_EP_DATA_FREE field. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE_Msk = 0x2 + // Bit SERIAL_IN_EP_DATA_FREE. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE = 0x2 + // Position of SERIAL_OUT_EP_DATA_AVAIL field. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL_Pos = 0x2 + // Bit mask of SERIAL_OUT_EP_DATA_AVAIL field. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL_Msk = 0x4 + // Bit SERIAL_OUT_EP_DATA_AVAIL. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL = 0x4 + + // INT_RAW: Interrupt raw status register. + // Position of JTAG_IN_FLUSH_INT_RAW field. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_RAW field. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_RAW. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW = 0x1 + // Position of SOF_INT_RAW field. + USB_DEVICE_INT_RAW_SOF_INT_RAW_Pos = 0x1 + // Bit mask of SOF_INT_RAW field. + USB_DEVICE_INT_RAW_SOF_INT_RAW_Msk = 0x2 + // Bit SOF_INT_RAW. + USB_DEVICE_INT_RAW_SOF_INT_RAW = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_RAW. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW = 0x4 + // Position of SERIAL_IN_EMPTY_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_RAW. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW = 0x8 + // Position of PID_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW_Pos = 0x4 + // Bit mask of PID_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW_Msk = 0x10 + // Bit PID_ERR_INT_RAW. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW = 0x10 + // Position of CRC5_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW_Msk = 0x20 + // Bit CRC5_ERR_INT_RAW. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW = 0x20 + // Position of CRC16_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW_Msk = 0x40 + // Bit CRC16_ERR_INT_RAW. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW = 0x40 + // Position of STUFF_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW_Msk = 0x80 + // Bit STUFF_ERR_INT_RAW. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_RAW field. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_RAW field. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_RAW. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW = 0x100 + // Position of USB_BUS_RESET_INT_RAW field. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_RAW field. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW_Msk = 0x200 + // Bit USB_BUS_RESET_INT_RAW. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_RAW. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_RAW. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW = 0x800 + // Position of RTS_CHG_INT_RAW field. + USB_DEVICE_INT_RAW_RTS_CHG_INT_RAW_Pos = 0xc + // Bit mask of RTS_CHG_INT_RAW field. + USB_DEVICE_INT_RAW_RTS_CHG_INT_RAW_Msk = 0x1000 + // Bit RTS_CHG_INT_RAW. + USB_DEVICE_INT_RAW_RTS_CHG_INT_RAW = 0x1000 + // Position of DTR_CHG_INT_RAW field. + USB_DEVICE_INT_RAW_DTR_CHG_INT_RAW_Pos = 0xd + // Bit mask of DTR_CHG_INT_RAW field. + USB_DEVICE_INT_RAW_DTR_CHG_INT_RAW_Msk = 0x2000 + // Bit DTR_CHG_INT_RAW. + USB_DEVICE_INT_RAW_DTR_CHG_INT_RAW = 0x2000 + // Position of GET_LINE_CODE_INT_RAW field. + USB_DEVICE_INT_RAW_GET_LINE_CODE_INT_RAW_Pos = 0xe + // Bit mask of GET_LINE_CODE_INT_RAW field. + USB_DEVICE_INT_RAW_GET_LINE_CODE_INT_RAW_Msk = 0x4000 + // Bit GET_LINE_CODE_INT_RAW. + USB_DEVICE_INT_RAW_GET_LINE_CODE_INT_RAW = 0x4000 + // Position of SET_LINE_CODE_INT_RAW field. + USB_DEVICE_INT_RAW_SET_LINE_CODE_INT_RAW_Pos = 0xf + // Bit mask of SET_LINE_CODE_INT_RAW field. + USB_DEVICE_INT_RAW_SET_LINE_CODE_INT_RAW_Msk = 0x8000 + // Bit SET_LINE_CODE_INT_RAW. + USB_DEVICE_INT_RAW_SET_LINE_CODE_INT_RAW = 0x8000 + + // INT_ST: Interrupt status register. + // Position of JTAG_IN_FLUSH_INT_ST field. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_ST field. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_ST. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST = 0x1 + // Position of SOF_INT_ST field. + USB_DEVICE_INT_ST_SOF_INT_ST_Pos = 0x1 + // Bit mask of SOF_INT_ST field. + USB_DEVICE_INT_ST_SOF_INT_ST_Msk = 0x2 + // Bit SOF_INT_ST. + USB_DEVICE_INT_ST_SOF_INT_ST = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_ST. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST = 0x4 + // Position of SERIAL_IN_EMPTY_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_ST. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST = 0x8 + // Position of PID_ERR_INT_ST field. + USB_DEVICE_INT_ST_PID_ERR_INT_ST_Pos = 0x4 + // Bit mask of PID_ERR_INT_ST field. + USB_DEVICE_INT_ST_PID_ERR_INT_ST_Msk = 0x10 + // Bit PID_ERR_INT_ST. + USB_DEVICE_INT_ST_PID_ERR_INT_ST = 0x10 + // Position of CRC5_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST_Msk = 0x20 + // Bit CRC5_ERR_INT_ST. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST = 0x20 + // Position of CRC16_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST_Msk = 0x40 + // Bit CRC16_ERR_INT_ST. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST = 0x40 + // Position of STUFF_ERR_INT_ST field. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_ST field. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST_Msk = 0x80 + // Bit STUFF_ERR_INT_ST. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_ST field. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_ST field. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_ST. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST = 0x100 + // Position of USB_BUS_RESET_INT_ST field. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_ST field. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST_Msk = 0x200 + // Bit USB_BUS_RESET_INT_ST. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_ST. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_ST. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST = 0x800 + // Position of RTS_CHG_INT_ST field. + USB_DEVICE_INT_ST_RTS_CHG_INT_ST_Pos = 0xc + // Bit mask of RTS_CHG_INT_ST field. + USB_DEVICE_INT_ST_RTS_CHG_INT_ST_Msk = 0x1000 + // Bit RTS_CHG_INT_ST. + USB_DEVICE_INT_ST_RTS_CHG_INT_ST = 0x1000 + // Position of DTR_CHG_INT_ST field. + USB_DEVICE_INT_ST_DTR_CHG_INT_ST_Pos = 0xd + // Bit mask of DTR_CHG_INT_ST field. + USB_DEVICE_INT_ST_DTR_CHG_INT_ST_Msk = 0x2000 + // Bit DTR_CHG_INT_ST. + USB_DEVICE_INT_ST_DTR_CHG_INT_ST = 0x2000 + // Position of GET_LINE_CODE_INT_ST field. + USB_DEVICE_INT_ST_GET_LINE_CODE_INT_ST_Pos = 0xe + // Bit mask of GET_LINE_CODE_INT_ST field. + USB_DEVICE_INT_ST_GET_LINE_CODE_INT_ST_Msk = 0x4000 + // Bit GET_LINE_CODE_INT_ST. + USB_DEVICE_INT_ST_GET_LINE_CODE_INT_ST = 0x4000 + // Position of SET_LINE_CODE_INT_ST field. + USB_DEVICE_INT_ST_SET_LINE_CODE_INT_ST_Pos = 0xf + // Bit mask of SET_LINE_CODE_INT_ST field. + USB_DEVICE_INT_ST_SET_LINE_CODE_INT_ST_Msk = 0x8000 + // Bit SET_LINE_CODE_INT_ST. + USB_DEVICE_INT_ST_SET_LINE_CODE_INT_ST = 0x8000 + + // INT_ENA: Interrupt enable status register. + // Position of JTAG_IN_FLUSH_INT_ENA field. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_ENA field. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_ENA. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA = 0x1 + // Position of SOF_INT_ENA field. + USB_DEVICE_INT_ENA_SOF_INT_ENA_Pos = 0x1 + // Bit mask of SOF_INT_ENA field. + USB_DEVICE_INT_ENA_SOF_INT_ENA_Msk = 0x2 + // Bit SOF_INT_ENA. + USB_DEVICE_INT_ENA_SOF_INT_ENA = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_ENA. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA = 0x4 + // Position of SERIAL_IN_EMPTY_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_ENA. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA = 0x8 + // Position of PID_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA_Pos = 0x4 + // Bit mask of PID_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA_Msk = 0x10 + // Bit PID_ERR_INT_ENA. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA = 0x10 + // Position of CRC5_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA_Msk = 0x20 + // Bit CRC5_ERR_INT_ENA. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA = 0x20 + // Position of CRC16_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA_Msk = 0x40 + // Bit CRC16_ERR_INT_ENA. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA = 0x40 + // Position of STUFF_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA_Msk = 0x80 + // Bit STUFF_ERR_INT_ENA. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_ENA field. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_ENA field. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_ENA. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA = 0x100 + // Position of USB_BUS_RESET_INT_ENA field. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_ENA field. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA_Msk = 0x200 + // Bit USB_BUS_RESET_INT_ENA. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_ENA. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_ENA. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA = 0x800 + // Position of RTS_CHG_INT_ENA field. + USB_DEVICE_INT_ENA_RTS_CHG_INT_ENA_Pos = 0xc + // Bit mask of RTS_CHG_INT_ENA field. + USB_DEVICE_INT_ENA_RTS_CHG_INT_ENA_Msk = 0x1000 + // Bit RTS_CHG_INT_ENA. + USB_DEVICE_INT_ENA_RTS_CHG_INT_ENA = 0x1000 + // Position of DTR_CHG_INT_ENA field. + USB_DEVICE_INT_ENA_DTR_CHG_INT_ENA_Pos = 0xd + // Bit mask of DTR_CHG_INT_ENA field. + USB_DEVICE_INT_ENA_DTR_CHG_INT_ENA_Msk = 0x2000 + // Bit DTR_CHG_INT_ENA. + USB_DEVICE_INT_ENA_DTR_CHG_INT_ENA = 0x2000 + // Position of GET_LINE_CODE_INT_ENA field. + USB_DEVICE_INT_ENA_GET_LINE_CODE_INT_ENA_Pos = 0xe + // Bit mask of GET_LINE_CODE_INT_ENA field. + USB_DEVICE_INT_ENA_GET_LINE_CODE_INT_ENA_Msk = 0x4000 + // Bit GET_LINE_CODE_INT_ENA. + USB_DEVICE_INT_ENA_GET_LINE_CODE_INT_ENA = 0x4000 + // Position of SET_LINE_CODE_INT_ENA field. + USB_DEVICE_INT_ENA_SET_LINE_CODE_INT_ENA_Pos = 0xf + // Bit mask of SET_LINE_CODE_INT_ENA field. + USB_DEVICE_INT_ENA_SET_LINE_CODE_INT_ENA_Msk = 0x8000 + // Bit SET_LINE_CODE_INT_ENA. + USB_DEVICE_INT_ENA_SET_LINE_CODE_INT_ENA = 0x8000 + + // INT_CLR: Interrupt clear status register. + // Position of JTAG_IN_FLUSH_INT_CLR field. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_CLR field. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_CLR. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR = 0x1 + // Position of SOF_INT_CLR field. + USB_DEVICE_INT_CLR_SOF_INT_CLR_Pos = 0x1 + // Bit mask of SOF_INT_CLR field. + USB_DEVICE_INT_CLR_SOF_INT_CLR_Msk = 0x2 + // Bit SOF_INT_CLR. + USB_DEVICE_INT_CLR_SOF_INT_CLR = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_CLR. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR = 0x4 + // Position of SERIAL_IN_EMPTY_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_CLR. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR = 0x8 + // Position of PID_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR_Pos = 0x4 + // Bit mask of PID_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR_Msk = 0x10 + // Bit PID_ERR_INT_CLR. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR = 0x10 + // Position of CRC5_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR_Msk = 0x20 + // Bit CRC5_ERR_INT_CLR. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR = 0x20 + // Position of CRC16_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR_Msk = 0x40 + // Bit CRC16_ERR_INT_CLR. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR = 0x40 + // Position of STUFF_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR_Msk = 0x80 + // Bit STUFF_ERR_INT_CLR. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_CLR field. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_CLR field. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_CLR. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR = 0x100 + // Position of USB_BUS_RESET_INT_CLR field. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_CLR field. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR_Msk = 0x200 + // Bit USB_BUS_RESET_INT_CLR. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_CLR. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_CLR. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR = 0x800 + // Position of RTS_CHG_INT_CLR field. + USB_DEVICE_INT_CLR_RTS_CHG_INT_CLR_Pos = 0xc + // Bit mask of RTS_CHG_INT_CLR field. + USB_DEVICE_INT_CLR_RTS_CHG_INT_CLR_Msk = 0x1000 + // Bit RTS_CHG_INT_CLR. + USB_DEVICE_INT_CLR_RTS_CHG_INT_CLR = 0x1000 + // Position of DTR_CHG_INT_CLR field. + USB_DEVICE_INT_CLR_DTR_CHG_INT_CLR_Pos = 0xd + // Bit mask of DTR_CHG_INT_CLR field. + USB_DEVICE_INT_CLR_DTR_CHG_INT_CLR_Msk = 0x2000 + // Bit DTR_CHG_INT_CLR. + USB_DEVICE_INT_CLR_DTR_CHG_INT_CLR = 0x2000 + // Position of GET_LINE_CODE_INT_CLR field. + USB_DEVICE_INT_CLR_GET_LINE_CODE_INT_CLR_Pos = 0xe + // Bit mask of GET_LINE_CODE_INT_CLR field. + USB_DEVICE_INT_CLR_GET_LINE_CODE_INT_CLR_Msk = 0x4000 + // Bit GET_LINE_CODE_INT_CLR. + USB_DEVICE_INT_CLR_GET_LINE_CODE_INT_CLR = 0x4000 + // Position of SET_LINE_CODE_INT_CLR field. + USB_DEVICE_INT_CLR_SET_LINE_CODE_INT_CLR_Pos = 0xf + // Bit mask of SET_LINE_CODE_INT_CLR field. + USB_DEVICE_INT_CLR_SET_LINE_CODE_INT_CLR_Msk = 0x8000 + // Bit SET_LINE_CODE_INT_CLR. + USB_DEVICE_INT_CLR_SET_LINE_CODE_INT_CLR = 0x8000 + + // CONF0: PHY hardware configuration. + // Position of PHY_SEL field. + USB_DEVICE_CONF0_PHY_SEL_Pos = 0x0 + // Bit mask of PHY_SEL field. + USB_DEVICE_CONF0_PHY_SEL_Msk = 0x1 + // Bit PHY_SEL. + USB_DEVICE_CONF0_PHY_SEL = 0x1 + // Position of EXCHG_PINS_OVERRIDE field. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE_Pos = 0x1 + // Bit mask of EXCHG_PINS_OVERRIDE field. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE_Msk = 0x2 + // Bit EXCHG_PINS_OVERRIDE. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE = 0x2 + // Position of EXCHG_PINS field. + USB_DEVICE_CONF0_EXCHG_PINS_Pos = 0x2 + // Bit mask of EXCHG_PINS field. + USB_DEVICE_CONF0_EXCHG_PINS_Msk = 0x4 + // Bit EXCHG_PINS. + USB_DEVICE_CONF0_EXCHG_PINS = 0x4 + // Position of VREFH field. + USB_DEVICE_CONF0_VREFH_Pos = 0x3 + // Bit mask of VREFH field. + USB_DEVICE_CONF0_VREFH_Msk = 0x18 + // Position of VREFL field. + USB_DEVICE_CONF0_VREFL_Pos = 0x5 + // Bit mask of VREFL field. + USB_DEVICE_CONF0_VREFL_Msk = 0x60 + // Position of VREF_OVERRIDE field. + USB_DEVICE_CONF0_VREF_OVERRIDE_Pos = 0x7 + // Bit mask of VREF_OVERRIDE field. + USB_DEVICE_CONF0_VREF_OVERRIDE_Msk = 0x80 + // Bit VREF_OVERRIDE. + USB_DEVICE_CONF0_VREF_OVERRIDE = 0x80 + // Position of PAD_PULL_OVERRIDE field. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE_Pos = 0x8 + // Bit mask of PAD_PULL_OVERRIDE field. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE_Msk = 0x100 + // Bit PAD_PULL_OVERRIDE. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE = 0x100 + // Position of DP_PULLUP field. + USB_DEVICE_CONF0_DP_PULLUP_Pos = 0x9 + // Bit mask of DP_PULLUP field. + USB_DEVICE_CONF0_DP_PULLUP_Msk = 0x200 + // Bit DP_PULLUP. + USB_DEVICE_CONF0_DP_PULLUP = 0x200 + // Position of DP_PULLDOWN field. + USB_DEVICE_CONF0_DP_PULLDOWN_Pos = 0xa + // Bit mask of DP_PULLDOWN field. + USB_DEVICE_CONF0_DP_PULLDOWN_Msk = 0x400 + // Bit DP_PULLDOWN. + USB_DEVICE_CONF0_DP_PULLDOWN = 0x400 + // Position of DM_PULLUP field. + USB_DEVICE_CONF0_DM_PULLUP_Pos = 0xb + // Bit mask of DM_PULLUP field. + USB_DEVICE_CONF0_DM_PULLUP_Msk = 0x800 + // Bit DM_PULLUP. + USB_DEVICE_CONF0_DM_PULLUP = 0x800 + // Position of DM_PULLDOWN field. + USB_DEVICE_CONF0_DM_PULLDOWN_Pos = 0xc + // Bit mask of DM_PULLDOWN field. + USB_DEVICE_CONF0_DM_PULLDOWN_Msk = 0x1000 + // Bit DM_PULLDOWN. + USB_DEVICE_CONF0_DM_PULLDOWN = 0x1000 + // Position of PULLUP_VALUE field. + USB_DEVICE_CONF0_PULLUP_VALUE_Pos = 0xd + // Bit mask of PULLUP_VALUE field. + USB_DEVICE_CONF0_PULLUP_VALUE_Msk = 0x2000 + // Bit PULLUP_VALUE. + USB_DEVICE_CONF0_PULLUP_VALUE = 0x2000 + // Position of USB_PAD_ENABLE field. + USB_DEVICE_CONF0_USB_PAD_ENABLE_Pos = 0xe + // Bit mask of USB_PAD_ENABLE field. + USB_DEVICE_CONF0_USB_PAD_ENABLE_Msk = 0x4000 + // Bit USB_PAD_ENABLE. + USB_DEVICE_CONF0_USB_PAD_ENABLE = 0x4000 + // Position of USB_JTAG_BRIDGE_EN field. + USB_DEVICE_CONF0_USB_JTAG_BRIDGE_EN_Pos = 0xf + // Bit mask of USB_JTAG_BRIDGE_EN field. + USB_DEVICE_CONF0_USB_JTAG_BRIDGE_EN_Msk = 0x8000 + // Bit USB_JTAG_BRIDGE_EN. + USB_DEVICE_CONF0_USB_JTAG_BRIDGE_EN = 0x8000 + + // TEST: Registers used for debugging the PHY. + // Position of TEST_ENABLE field. + USB_DEVICE_TEST_TEST_ENABLE_Pos = 0x0 + // Bit mask of TEST_ENABLE field. + USB_DEVICE_TEST_TEST_ENABLE_Msk = 0x1 + // Bit TEST_ENABLE. + USB_DEVICE_TEST_TEST_ENABLE = 0x1 + // Position of TEST_USB_OE field. + USB_DEVICE_TEST_TEST_USB_OE_Pos = 0x1 + // Bit mask of TEST_USB_OE field. + USB_DEVICE_TEST_TEST_USB_OE_Msk = 0x2 + // Bit TEST_USB_OE. + USB_DEVICE_TEST_TEST_USB_OE = 0x2 + // Position of TEST_TX_DP field. + USB_DEVICE_TEST_TEST_TX_DP_Pos = 0x2 + // Bit mask of TEST_TX_DP field. + USB_DEVICE_TEST_TEST_TX_DP_Msk = 0x4 + // Bit TEST_TX_DP. + USB_DEVICE_TEST_TEST_TX_DP = 0x4 + // Position of TEST_TX_DM field. + USB_DEVICE_TEST_TEST_TX_DM_Pos = 0x3 + // Bit mask of TEST_TX_DM field. + USB_DEVICE_TEST_TEST_TX_DM_Msk = 0x8 + // Bit TEST_TX_DM. + USB_DEVICE_TEST_TEST_TX_DM = 0x8 + // Position of TEST_RX_RCV field. + USB_DEVICE_TEST_TEST_RX_RCV_Pos = 0x4 + // Bit mask of TEST_RX_RCV field. + USB_DEVICE_TEST_TEST_RX_RCV_Msk = 0x10 + // Bit TEST_RX_RCV. + USB_DEVICE_TEST_TEST_RX_RCV = 0x10 + // Position of TEST_RX_DP field. + USB_DEVICE_TEST_TEST_RX_DP_Pos = 0x5 + // Bit mask of TEST_RX_DP field. + USB_DEVICE_TEST_TEST_RX_DP_Msk = 0x20 + // Bit TEST_RX_DP. + USB_DEVICE_TEST_TEST_RX_DP = 0x20 + // Position of TEST_RX_DM field. + USB_DEVICE_TEST_TEST_RX_DM_Pos = 0x6 + // Bit mask of TEST_RX_DM field. + USB_DEVICE_TEST_TEST_RX_DM_Msk = 0x40 + // Bit TEST_RX_DM. + USB_DEVICE_TEST_TEST_RX_DM = 0x40 + + // JFIFO_ST: JTAG FIFO status and control registers. + // Position of IN_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_IN_FIFO_CNT_Pos = 0x0 + // Bit mask of IN_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_IN_FIFO_CNT_Msk = 0x3 + // Position of IN_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY_Pos = 0x2 + // Bit mask of IN_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY_Msk = 0x4 + // Bit IN_FIFO_EMPTY. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY = 0x4 + // Position of IN_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL_Pos = 0x3 + // Bit mask of IN_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL_Msk = 0x8 + // Bit IN_FIFO_FULL. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL = 0x8 + // Position of OUT_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_CNT_Pos = 0x4 + // Bit mask of OUT_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_CNT_Msk = 0x30 + // Position of OUT_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY_Pos = 0x6 + // Bit mask of OUT_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY_Msk = 0x40 + // Bit OUT_FIFO_EMPTY. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY = 0x40 + // Position of OUT_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL_Pos = 0x7 + // Bit mask of OUT_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL_Msk = 0x80 + // Bit OUT_FIFO_FULL. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL = 0x80 + // Position of IN_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET_Pos = 0x8 + // Bit mask of IN_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET_Msk = 0x100 + // Bit IN_FIFO_RESET. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET = 0x100 + // Position of OUT_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET_Pos = 0x9 + // Bit mask of OUT_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET_Msk = 0x200 + // Bit OUT_FIFO_RESET. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET = 0x200 + + // FRAM_NUM: Last received SOF frame index register. + // Position of SOF_FRAME_INDEX field. + USB_DEVICE_FRAM_NUM_SOF_FRAME_INDEX_Pos = 0x0 + // Bit mask of SOF_FRAME_INDEX field. + USB_DEVICE_FRAM_NUM_SOF_FRAME_INDEX_Msk = 0x7ff + + // IN_EP0_ST: Control IN endpoint status information. + // Position of IN_EP0_STATE field. + USB_DEVICE_IN_EP0_ST_IN_EP0_STATE_Pos = 0x0 + // Bit mask of IN_EP0_STATE field. + USB_DEVICE_IN_EP0_ST_IN_EP0_STATE_Msk = 0x3 + // Position of IN_EP0_WR_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP0_WR_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_WR_ADDR_Msk = 0x1fc + // Position of IN_EP0_RD_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP0_RD_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_RD_ADDR_Msk = 0xfe00 + + // IN_EP1_ST: CDC-ACM IN endpoint status information. + // Position of IN_EP1_STATE field. + USB_DEVICE_IN_EP1_ST_IN_EP1_STATE_Pos = 0x0 + // Bit mask of IN_EP1_STATE field. + USB_DEVICE_IN_EP1_ST_IN_EP1_STATE_Msk = 0x3 + // Position of IN_EP1_WR_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP1_WR_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_WR_ADDR_Msk = 0x1fc + // Position of IN_EP1_RD_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP1_RD_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_RD_ADDR_Msk = 0xfe00 + + // IN_EP2_ST: CDC-ACM interrupt IN endpoint status information. + // Position of IN_EP2_STATE field. + USB_DEVICE_IN_EP2_ST_IN_EP2_STATE_Pos = 0x0 + // Bit mask of IN_EP2_STATE field. + USB_DEVICE_IN_EP2_ST_IN_EP2_STATE_Msk = 0x3 + // Position of IN_EP2_WR_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP2_WR_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_WR_ADDR_Msk = 0x1fc + // Position of IN_EP2_RD_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP2_RD_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_RD_ADDR_Msk = 0xfe00 + + // IN_EP3_ST: JTAG IN endpoint status information. + // Position of IN_EP3_STATE field. + USB_DEVICE_IN_EP3_ST_IN_EP3_STATE_Pos = 0x0 + // Bit mask of IN_EP3_STATE field. + USB_DEVICE_IN_EP3_ST_IN_EP3_STATE_Msk = 0x3 + // Position of IN_EP3_WR_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP3_WR_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_WR_ADDR_Msk = 0x1fc + // Position of IN_EP3_RD_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP3_RD_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_RD_ADDR_Msk = 0xfe00 + + // OUT_EP0_ST: Control OUT endpoint status information. + // Position of OUT_EP0_STATE field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_STATE_Pos = 0x0 + // Bit mask of OUT_EP0_STATE field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_STATE_Msk = 0x3 + // Position of OUT_EP0_WR_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP0_WR_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP0_RD_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP0_RD_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_RD_ADDR_Msk = 0xfe00 + + // OUT_EP1_ST: CDC-ACM OUT endpoint status information. + // Position of OUT_EP1_STATE field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_STATE_Pos = 0x0 + // Bit mask of OUT_EP1_STATE field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_STATE_Msk = 0x3 + // Position of OUT_EP1_WR_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP1_WR_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP1_RD_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP1_RD_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_RD_ADDR_Msk = 0xfe00 + // Position of OUT_EP1_REC_DATA_CNT field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_REC_DATA_CNT_Pos = 0x10 + // Bit mask of OUT_EP1_REC_DATA_CNT field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_REC_DATA_CNT_Msk = 0x7f0000 + + // OUT_EP2_ST: JTAG OUT endpoint status information. + // Position of OUT_EP2_STATE field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_STATE_Pos = 0x0 + // Bit mask of OUT_EP2_STATE field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_STATE_Msk = 0x3 + // Position of OUT_EP2_WR_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP2_WR_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP2_RD_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP2_RD_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_RD_ADDR_Msk = 0xfe00 + + // MISC_CONF: Clock enable control + // Position of CLK_EN field. + USB_DEVICE_MISC_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + USB_DEVICE_MISC_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + USB_DEVICE_MISC_CONF_CLK_EN = 0x1 + + // MEM_CONF: Memory power control + // Position of USB_MEM_PD field. + USB_DEVICE_MEM_CONF_USB_MEM_PD_Pos = 0x0 + // Bit mask of USB_MEM_PD field. + USB_DEVICE_MEM_CONF_USB_MEM_PD_Msk = 0x1 + // Bit USB_MEM_PD. + USB_DEVICE_MEM_CONF_USB_MEM_PD = 0x1 + // Position of USB_MEM_CLK_EN field. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN_Pos = 0x1 + // Bit mask of USB_MEM_CLK_EN field. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN_Msk = 0x2 + // Bit USB_MEM_CLK_EN. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN = 0x2 + + // CHIP_RST: CDC-ACM chip reset control. + // Position of RTS field. + USB_DEVICE_CHIP_RST_RTS_Pos = 0x0 + // Bit mask of RTS field. + USB_DEVICE_CHIP_RST_RTS_Msk = 0x1 + // Bit RTS. + USB_DEVICE_CHIP_RST_RTS = 0x1 + // Position of DTR field. + USB_DEVICE_CHIP_RST_DTR_Pos = 0x1 + // Bit mask of DTR field. + USB_DEVICE_CHIP_RST_DTR_Msk = 0x2 + // Bit DTR. + USB_DEVICE_CHIP_RST_DTR = 0x2 + // Position of USB_UART_CHIP_RST_DIS field. + USB_DEVICE_CHIP_RST_USB_UART_CHIP_RST_DIS_Pos = 0x2 + // Bit mask of USB_UART_CHIP_RST_DIS field. + USB_DEVICE_CHIP_RST_USB_UART_CHIP_RST_DIS_Msk = 0x4 + // Bit USB_UART_CHIP_RST_DIS. + USB_DEVICE_CHIP_RST_USB_UART_CHIP_RST_DIS = 0x4 + + // SET_LINE_CODE_W0: W0 of SET_LINE_CODING command. + // Position of DW_DTE_RATE field. + USB_DEVICE_SET_LINE_CODE_W0_DW_DTE_RATE_Pos = 0x0 + // Bit mask of DW_DTE_RATE field. + USB_DEVICE_SET_LINE_CODE_W0_DW_DTE_RATE_Msk = 0xffffffff + + // SET_LINE_CODE_W1: W1 of SET_LINE_CODING command. + // Position of BCHAR_FORMAT field. + USB_DEVICE_SET_LINE_CODE_W1_BCHAR_FORMAT_Pos = 0x0 + // Bit mask of BCHAR_FORMAT field. + USB_DEVICE_SET_LINE_CODE_W1_BCHAR_FORMAT_Msk = 0xff + // Position of BPARITY_TYPE field. + USB_DEVICE_SET_LINE_CODE_W1_BPARITY_TYPE_Pos = 0x8 + // Bit mask of BPARITY_TYPE field. + USB_DEVICE_SET_LINE_CODE_W1_BPARITY_TYPE_Msk = 0xff00 + // Position of BDATA_BITS field. + USB_DEVICE_SET_LINE_CODE_W1_BDATA_BITS_Pos = 0x10 + // Bit mask of BDATA_BITS field. + USB_DEVICE_SET_LINE_CODE_W1_BDATA_BITS_Msk = 0xff0000 + + // GET_LINE_CODE_W0: W0 of GET_LINE_CODING command. + // Position of GET_DW_DTE_RATE field. + USB_DEVICE_GET_LINE_CODE_W0_GET_DW_DTE_RATE_Pos = 0x0 + // Bit mask of GET_DW_DTE_RATE field. + USB_DEVICE_GET_LINE_CODE_W0_GET_DW_DTE_RATE_Msk = 0xffffffff + + // GET_LINE_CODE_W1: W1 of GET_LINE_CODING command. + // Position of GET_BDATA_BITS field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BDATA_BITS_Pos = 0x0 + // Bit mask of GET_BDATA_BITS field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BDATA_BITS_Msk = 0xff + // Position of GET_BPARITY_TYPE field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BPARITY_TYPE_Pos = 0x8 + // Bit mask of GET_BPARITY_TYPE field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BPARITY_TYPE_Msk = 0xff00 + // Position of GET_BCHAR_FORMAT field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BCHAR_FORMAT_Pos = 0x10 + // Bit mask of GET_BCHAR_FORMAT field. + USB_DEVICE_GET_LINE_CODE_W1_GET_BCHAR_FORMAT_Msk = 0xff0000 + + // CONFIG_UPDATE: Configuration registers' value update + // Position of CONFIG_UPDATE field. + USB_DEVICE_CONFIG_UPDATE_CONFIG_UPDATE_Pos = 0x0 + // Bit mask of CONFIG_UPDATE field. + USB_DEVICE_CONFIG_UPDATE_CONFIG_UPDATE_Msk = 0x1 + // Bit CONFIG_UPDATE. + USB_DEVICE_CONFIG_UPDATE_CONFIG_UPDATE = 0x1 + + // SER_AFIFO_CONFIG: Serial AFIFO configure register + // Position of SERIAL_IN_AFIFO_RESET_WR field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR_Pos = 0x0 + // Bit mask of SERIAL_IN_AFIFO_RESET_WR field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR_Msk = 0x1 + // Bit SERIAL_IN_AFIFO_RESET_WR. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_WR = 0x1 + // Position of SERIAL_IN_AFIFO_RESET_RD field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD_Pos = 0x1 + // Bit mask of SERIAL_IN_AFIFO_RESET_RD field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD_Msk = 0x2 + // Bit SERIAL_IN_AFIFO_RESET_RD. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_RESET_RD = 0x2 + // Position of SERIAL_OUT_AFIFO_RESET_WR field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR_Pos = 0x2 + // Bit mask of SERIAL_OUT_AFIFO_RESET_WR field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR_Msk = 0x4 + // Bit SERIAL_OUT_AFIFO_RESET_WR. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_WR = 0x4 + // Position of SERIAL_OUT_AFIFO_RESET_RD field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD_Pos = 0x3 + // Bit mask of SERIAL_OUT_AFIFO_RESET_RD field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD_Msk = 0x8 + // Bit SERIAL_OUT_AFIFO_RESET_RD. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_RESET_RD = 0x8 + // Position of SERIAL_OUT_AFIFO_REMPTY field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY_Pos = 0x4 + // Bit mask of SERIAL_OUT_AFIFO_REMPTY field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY_Msk = 0x10 + // Bit SERIAL_OUT_AFIFO_REMPTY. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_OUT_AFIFO_REMPTY = 0x10 + // Position of SERIAL_IN_AFIFO_WFULL field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL_Pos = 0x5 + // Bit mask of SERIAL_IN_AFIFO_WFULL field. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL_Msk = 0x20 + // Bit SERIAL_IN_AFIFO_WFULL. + USB_DEVICE_SER_AFIFO_CONFIG_SERIAL_IN_AFIFO_WFULL = 0x20 + + // BUS_RESET_ST: USB Bus reset status register + // Position of USB_BUS_RESET_ST field. + USB_DEVICE_BUS_RESET_ST_USB_BUS_RESET_ST_Pos = 0x0 + // Bit mask of USB_BUS_RESET_ST field. + USB_DEVICE_BUS_RESET_ST_USB_BUS_RESET_ST_Msk = 0x1 + // Bit USB_BUS_RESET_ST. + USB_DEVICE_BUS_RESET_ST_USB_BUS_RESET_ST = 0x1 + + // DATE: Date register + // Position of DATE field. + USB_DEVICE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + USB_DEVICE_DATE_DATE_Msk = 0xffffffff +) diff --git a/emb/device/esp/esp32p4.go b/emb/device/esp/esp32p4.go new file mode 100644 index 0000000..62d3385 --- /dev/null +++ b/emb/device/esp/esp32p4.go @@ -0,0 +1,203958 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32p4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32p4 + +/* +// 32-bit RISC-V MCU +*/ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32-P4" + CPU = "RV32IMAFC" + FPUPresent = true + NVICPrioBits = 0 +) + +// Interrupt numbers. +const ( + // Low-power Watchdog Timer + IRQ_LP_WDT = 1 + + // Low-power Timer + IRQ_LP_TIMER0 = 2 + + // Low-power Timer + IRQ_LP_TIMER1 = 3 + + // PMU Peripheral + IRQ_PMU0 = 6 + + // PMU Peripheral + IRQ_PMU1 = 7 + + // LP_ANA_PERI Peripheral + IRQ_LP_ANA = 8 + + // Low-power Analog to Digital Converter + IRQ_LP_ADC = 9 + + // Low-power General Purpose Input/Output + IRQ_LP_GPIO = 10 + + // Low-power I2C (Inter-Integrated Circuit) Controller 0 + IRQ_LP_I2C0 = 11 + + // Low-power I2S (Inter-IC Sound) Controller 0 + IRQ_LP_I2S0 = 12 + + // LP_TOUCH Peripheral + IRQ_LP_TOUCH = 14 + + // Low-power Temperature Sensor + IRQ_LP_TSENS = 15 + + // Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + IRQ_LP_UART = 16 + + // LP_SYS Peripheral + IRQ_LP_SYS = 19 + + // LP_HUK Peripheral + IRQ_LP_HUK = 20 + + // Full-speed USB Serial/JTAG Controller + IRQ_USB_DEVICE = 22 + + // DMA (Direct Memory Access) Controller + IRQ_DMA = 24 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_SPI2 = 25 + + // SPI (Serial Peripheral Interface) Controller 3 + IRQ_SPI3 = 26 + + // I2S (Inter-IC Sound) Controller 0 + IRQ_I2S0 = 27 + + // I2S (Inter-IC Sound) Controller 1 + IRQ_I2S1 = 28 + + // I2S (Inter-IC Sound) Controller 2 + IRQ_I2S2 = 29 + + // Universal Host Controller Interface 0 + IRQ_UHCI0 = 30 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + IRQ_UART0 = 31 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + IRQ_UART1 = 32 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + IRQ_UART2 = 33 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 3 + IRQ_UART3 = 34 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 4 + IRQ_UART4 = 35 + + // Motor Control Pulse-Width Modulation 0 + IRQ_PWM0 = 38 + + // Motor Control Pulse-Width Modulation 1 + IRQ_PWM1 = 39 + + // Two-Wire Automotive Interface + IRQ_TWAI0 = 40 + + // Two-Wire Automotive Interface + IRQ_TWAI1 = 41 + + // Two-Wire Automotive Interface + IRQ_TWAI2 = 42 + + // Remote Control + IRQ_RMT = 43 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C0 = 44 + + // I2C (Inter-Integrated Circuit) Controller 1 + IRQ_I2C1 = 45 + + // Timer Group 0 + IRQ_TG0_T0 = 46 + + // Timer Group 0 + IRQ_TG0_T1 = 47 + + // Timer Group 0 + IRQ_TG0_WDT = 48 + + // Timer Group 1 + IRQ_TG1_T0 = 49 + + // Timer Group 1 + IRQ_TG1_T1 = 50 + + // Timer Group 1 + IRQ_TG1_WDT = 51 + + // LED Control PWM (Pulse Width Modulation) + IRQ_LEDC = 52 + + // System Timer + IRQ_SYSTIMER_TARGET0 = 53 + + // System Timer + IRQ_SYSTIMER_TARGET1 = 54 + + // System Timer + IRQ_SYSTIMER_TARGET2 = 55 + + // AHB_DMA Peripheral + IRQ_AHB_PDMA_IN_CH0 = 56 + + // AHB_DMA Peripheral + IRQ_AHB_PDMA_IN_CH1 = 57 + + // AHB_DMA Peripheral + IRQ_AHB_PDMA_IN_CH2 = 58 + + // AHB_DMA Peripheral + IRQ_AHB_PDMA_OUT_CH0 = 59 + + // AHB_DMA Peripheral + IRQ_AHB_PDMA_OUT_CH1 = 60 + + // AHB_DMA Peripheral + IRQ_AHB_PDMA_OUT_CH2 = 61 + + // AHB_DMA Peripheral + IRQ_AXI_PDMA_IN_CH0 = 62 + + // AHB_DMA Peripheral + IRQ_AXI_PDMA_IN_CH1 = 63 + + // AHB_DMA Peripheral + IRQ_AXI_PDMA_IN_CH2 = 64 + + // AHB_DMA Peripheral + IRQ_AXI_PDMA_OUT_CH0 = 65 + + // AHB_DMA Peripheral + IRQ_AXI_PDMA_OUT_CH1 = 66 + + // AHB_DMA Peripheral + IRQ_AXI_PDMA_OUT_CH2 = 67 + + // RSA (Rivest Shamir Adleman) Accelerator + IRQ_RSA = 68 + + // AES (Advanced Encryption Standard) Accelerator + IRQ_AES = 69 + + // SHA (Secure Hash Algorithm) Accelerator + IRQ_SHA = 70 + + // ECC (ECC Hardware Accelerator) + IRQ_ECC = 71 + + // General Purpose Input/Output + IRQ_GPIO_INT0 = 74 + + // General Purpose Input/Output + IRQ_GPIO_INT1 = 75 + + // General Purpose Input/Output + IRQ_GPIO_INT2 = 76 + + // General Purpose Input/Output + IRQ_GPIO_INT3 = 77 + + // General Purpose Input/Output + IRQ_GPIO_PAD_COMP = 78 + + // CACHE Peripheral + IRQ_CACHE = 83 + + // MIPI Camera Interface Bridge + IRQ_CSI_BRIDGE = 85 + + // MIPI Camera Interface Bridge + IRQ_DSI_BRIDGE = 86 + + // MIPI Camera Interface Host + IRQ_CSI = 87 + + // MIPI Display Interface Host + IRQ_DSI = 88 + + // JPEG Codec + IRQ_JPEG = 95 + + // PPA Peripheral + IRQ_PPA = 96 + + // ISP Peripheral + IRQ_ISP = 100 + + // I3C Controller (Master) + IRQ_I3C = 101 + + // I3C Controller (Slave) + IRQ_I3C_SLV = 102 + + // High-Power System + IRQ_HP_SYS = 110 + + // Pulse Count Controller + IRQ_PCNT = 111 + + // PAU Peripheral + IRQ_PAU = 112 + + // Parallel IO Controller + IRQ_PARLIO_RX = 113 + + // Parallel IO Controller + IRQ_PARLIO_TX = 114 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_OUT_CH0 = 115 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_OUT_CH1 = 116 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_OUT_CH2 = 117 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_OUT_CH3 = 118 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_OUT_CH4 = 119 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_IN_CH0 = 120 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_IN_CH1 = 121 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_IN_CH2 = 122 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_IN_CH3 = 123 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_IN_CH4 = 124 + + // H264 Encoder (DMA) + IRQ_H264_DMA2D_IN_CH5 = 125 + + // H264 Encoder (Core) + IRQ_H264_REG = 126 + + // Debug Assist + IRQ_ASSIST_DEBUG = 127 + + // Highest interrupt number on this device. + IRQ_max = 127 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_LP_WDT: + callHandlers(IRQ_LP_WDT) + case IRQ_LP_TIMER0: + callHandlers(IRQ_LP_TIMER0) + case IRQ_LP_TIMER1: + callHandlers(IRQ_LP_TIMER1) + case IRQ_PMU0: + callHandlers(IRQ_PMU0) + case IRQ_PMU1: + callHandlers(IRQ_PMU1) + case IRQ_LP_ANA: + callHandlers(IRQ_LP_ANA) + case IRQ_LP_ADC: + callHandlers(IRQ_LP_ADC) + case IRQ_LP_GPIO: + callHandlers(IRQ_LP_GPIO) + case IRQ_LP_I2C0: + callHandlers(IRQ_LP_I2C0) + case IRQ_LP_I2S0: + callHandlers(IRQ_LP_I2S0) + case IRQ_LP_TOUCH: + callHandlers(IRQ_LP_TOUCH) + case IRQ_LP_TSENS: + callHandlers(IRQ_LP_TSENS) + case IRQ_LP_UART: + callHandlers(IRQ_LP_UART) + case IRQ_LP_SYS: + callHandlers(IRQ_LP_SYS) + case IRQ_LP_HUK: + callHandlers(IRQ_LP_HUK) + case IRQ_USB_DEVICE: + callHandlers(IRQ_USB_DEVICE) + case IRQ_DMA: + callHandlers(IRQ_DMA) + case IRQ_SPI2: + callHandlers(IRQ_SPI2) + case IRQ_SPI3: + callHandlers(IRQ_SPI3) + case IRQ_I2S0: + callHandlers(IRQ_I2S0) + case IRQ_I2S1: + callHandlers(IRQ_I2S1) + case IRQ_I2S2: + callHandlers(IRQ_I2S2) + case IRQ_UHCI0: + callHandlers(IRQ_UHCI0) + case IRQ_UART0: + callHandlers(IRQ_UART0) + case IRQ_UART1: + callHandlers(IRQ_UART1) + case IRQ_UART2: + callHandlers(IRQ_UART2) + case IRQ_UART3: + callHandlers(IRQ_UART3) + case IRQ_UART4: + callHandlers(IRQ_UART4) + case IRQ_PWM0: + callHandlers(IRQ_PWM0) + case IRQ_PWM1: + callHandlers(IRQ_PWM1) + case IRQ_TWAI0: + callHandlers(IRQ_TWAI0) + case IRQ_TWAI1: + callHandlers(IRQ_TWAI1) + case IRQ_TWAI2: + callHandlers(IRQ_TWAI2) + case IRQ_RMT: + callHandlers(IRQ_RMT) + case IRQ_I2C0: + callHandlers(IRQ_I2C0) + case IRQ_I2C1: + callHandlers(IRQ_I2C1) + case IRQ_TG0_T0: + callHandlers(IRQ_TG0_T0) + case IRQ_TG0_T1: + callHandlers(IRQ_TG0_T1) + case IRQ_TG0_WDT: + callHandlers(IRQ_TG0_WDT) + case IRQ_TG1_T0: + callHandlers(IRQ_TG1_T0) + case IRQ_TG1_T1: + callHandlers(IRQ_TG1_T1) + case IRQ_TG1_WDT: + callHandlers(IRQ_TG1_WDT) + case IRQ_LEDC: + callHandlers(IRQ_LEDC) + case IRQ_SYSTIMER_TARGET0: + callHandlers(IRQ_SYSTIMER_TARGET0) + case IRQ_SYSTIMER_TARGET1: + callHandlers(IRQ_SYSTIMER_TARGET1) + case IRQ_SYSTIMER_TARGET2: + callHandlers(IRQ_SYSTIMER_TARGET2) + case IRQ_AHB_PDMA_IN_CH0: + callHandlers(IRQ_AHB_PDMA_IN_CH0) + case IRQ_AHB_PDMA_IN_CH1: + callHandlers(IRQ_AHB_PDMA_IN_CH1) + case IRQ_AHB_PDMA_IN_CH2: + callHandlers(IRQ_AHB_PDMA_IN_CH2) + case IRQ_AHB_PDMA_OUT_CH0: + callHandlers(IRQ_AHB_PDMA_OUT_CH0) + case IRQ_AHB_PDMA_OUT_CH1: + callHandlers(IRQ_AHB_PDMA_OUT_CH1) + case IRQ_AHB_PDMA_OUT_CH2: + callHandlers(IRQ_AHB_PDMA_OUT_CH2) + case IRQ_AXI_PDMA_IN_CH0: + callHandlers(IRQ_AXI_PDMA_IN_CH0) + case IRQ_AXI_PDMA_IN_CH1: + callHandlers(IRQ_AXI_PDMA_IN_CH1) + case IRQ_AXI_PDMA_IN_CH2: + callHandlers(IRQ_AXI_PDMA_IN_CH2) + case IRQ_AXI_PDMA_OUT_CH0: + callHandlers(IRQ_AXI_PDMA_OUT_CH0) + case IRQ_AXI_PDMA_OUT_CH1: + callHandlers(IRQ_AXI_PDMA_OUT_CH1) + case IRQ_AXI_PDMA_OUT_CH2: + callHandlers(IRQ_AXI_PDMA_OUT_CH2) + case IRQ_RSA: + callHandlers(IRQ_RSA) + case IRQ_AES: + callHandlers(IRQ_AES) + case IRQ_SHA: + callHandlers(IRQ_SHA) + case IRQ_ECC: + callHandlers(IRQ_ECC) + case IRQ_GPIO_INT0: + callHandlers(IRQ_GPIO_INT0) + case IRQ_GPIO_INT1: + callHandlers(IRQ_GPIO_INT1) + case IRQ_GPIO_INT2: + callHandlers(IRQ_GPIO_INT2) + case IRQ_GPIO_INT3: + callHandlers(IRQ_GPIO_INT3) + case IRQ_GPIO_PAD_COMP: + callHandlers(IRQ_GPIO_PAD_COMP) + case IRQ_CACHE: + callHandlers(IRQ_CACHE) + case IRQ_CSI_BRIDGE: + callHandlers(IRQ_CSI_BRIDGE) + case IRQ_DSI_BRIDGE: + callHandlers(IRQ_DSI_BRIDGE) + case IRQ_CSI: + callHandlers(IRQ_CSI) + case IRQ_DSI: + callHandlers(IRQ_DSI) + case IRQ_JPEG: + callHandlers(IRQ_JPEG) + case IRQ_PPA: + callHandlers(IRQ_PPA) + case IRQ_ISP: + callHandlers(IRQ_ISP) + case IRQ_I3C: + callHandlers(IRQ_I3C) + case IRQ_I3C_SLV: + callHandlers(IRQ_I3C_SLV) + case IRQ_HP_SYS: + callHandlers(IRQ_HP_SYS) + case IRQ_PCNT: + callHandlers(IRQ_PCNT) + case IRQ_PAU: + callHandlers(IRQ_PAU) + case IRQ_PARLIO_RX: + callHandlers(IRQ_PARLIO_RX) + case IRQ_PARLIO_TX: + callHandlers(IRQ_PARLIO_TX) + case IRQ_H264_DMA2D_OUT_CH0: + callHandlers(IRQ_H264_DMA2D_OUT_CH0) + case IRQ_H264_DMA2D_OUT_CH1: + callHandlers(IRQ_H264_DMA2D_OUT_CH1) + case IRQ_H264_DMA2D_OUT_CH2: + callHandlers(IRQ_H264_DMA2D_OUT_CH2) + case IRQ_H264_DMA2D_OUT_CH3: + callHandlers(IRQ_H264_DMA2D_OUT_CH3) + case IRQ_H264_DMA2D_OUT_CH4: + callHandlers(IRQ_H264_DMA2D_OUT_CH4) + case IRQ_H264_DMA2D_IN_CH0: + callHandlers(IRQ_H264_DMA2D_IN_CH0) + case IRQ_H264_DMA2D_IN_CH1: + callHandlers(IRQ_H264_DMA2D_IN_CH1) + case IRQ_H264_DMA2D_IN_CH2: + callHandlers(IRQ_H264_DMA2D_IN_CH2) + case IRQ_H264_DMA2D_IN_CH3: + callHandlers(IRQ_H264_DMA2D_IN_CH3) + case IRQ_H264_DMA2D_IN_CH4: + callHandlers(IRQ_H264_DMA2D_IN_CH4) + case IRQ_H264_DMA2D_IN_CH5: + callHandlers(IRQ_H264_DMA2D_IN_CH5) + case IRQ_H264_REG: + callHandlers(IRQ_H264_REG) + case IRQ_ASSIST_DEBUG: + callHandlers(IRQ_ASSIST_DEBUG) + } +} + +// Peripherals. +var ( + // ADC (Analog to Digital Converter) + ADC = (*ADC_Type)(unsafe.Pointer(uintptr(0x500de000))) + + // AES (Advanced Encryption Standard) Accelerator + AES = (*AES_Type)(unsafe.Pointer(uintptr(0x50090000))) + + // AHB_DMA Peripheral + AHB_DMA = (*AHB_DMA_Type)(unsafe.Pointer(uintptr(0x50085000))) + + // LP_I2C_ANA_MST Peripheral + LP_I2C_ANA_MST = (*ANA_I2C_MST_Type)(unsafe.Pointer(uintptr(0x50124000))) + + // Debug Assist + ASSIST_DEBUG = (*ASSIST_DEBUG_Type)(unsafe.Pointer(uintptr(0x3ff06000))) + + // AXI_DMA Peripheral + AXI_DMA = (*AXI_DMA_Type)(unsafe.Pointer(uintptr(0x5008a000))) + + // BITSCRAMBLER Peripheral + BITSCRAMBLER = (*BITSCRAMBLER_Type)(unsafe.Pointer(uintptr(0x500a3000))) + + // CACHE Peripheral + CACHE = (*CACHE_Type)(unsafe.Pointer(uintptr(0x3ff10000))) + + // Interrupt Controller (Core 0) + INTERRUPT_CORE0 = (*CORE0_Type)(unsafe.Pointer(uintptr(0x500d6000))) + + // Interrupt Controller (Core 1) + INTERRUPT_CORE1 = (*CORE1_Type)(unsafe.Pointer(uintptr(0x500d6800))) + + // MIPI Camera Interface Bridge + MIPI_CSI_BRIDGE = (*CSI_BRIG_Type)(unsafe.Pointer(uintptr(0x5009f800))) + + // MIPI Camera Interface Host + MIPI_CSI_HOST = (*CSI_HOST_Type)(unsafe.Pointer(uintptr(0x5009f000))) + + // DMA (Direct Memory Access) Controller + DMA = (*DMAC_Type)(unsafe.Pointer(uintptr(0x50081000))) + + // Digital Signature + DS = (*DS_Type)(unsafe.Pointer(uintptr(0x50094000))) + + // MIPI Camera Interface Bridge + MIPI_DSI_BRIDGE = (*DSI_BRG_Type)(unsafe.Pointer(uintptr(0x500a0800))) + + // MIPI Display Interface Host + MIPI_DSI_HOST = (*DSI_HOST_Type)(unsafe.Pointer(uintptr(0x500a0000))) + + // ECC (ECC Hardware Accelerator) + ECC = (*ECC_Type)(unsafe.Pointer(uintptr(0x50093000))) + + // ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator + ECDSA = (*ECDSA_Type)(unsafe.Pointer(uintptr(0x50096000))) + + // eFuse Controller + EFUSE = (*EFUSE_Type)(unsafe.Pointer(uintptr(0x5012d000))) + + // General Purpose Input/Output + GPIO = (*GPIO_Type)(unsafe.Pointer(uintptr(0x500e0000))) + + // Sigma-Delta Modulation + GPIO_SD = (*GPIOSD_Type)(unsafe.Pointer(uintptr(0x500e0f00))) + + // H264 Encoder (Core) + H264 = (*H264_Type)(unsafe.Pointer(uintptr(0x50084000))) + + // H264 Encoder (DMA) + H264_DMA = (*H264_DMA_Type)(unsafe.Pointer(uintptr(0x500a7000))) + + // HMAC (Hash-based Message Authentication Code) Accelerator + HMAC = (*HMAC_Type)(unsafe.Pointer(uintptr(0x50095000))) + + // High-Power System + HP_SYS = (*HP_SYS_Type)(unsafe.Pointer(uintptr(0x500e5000))) + + // HP_SYS_CLKRST Peripheral + HP_SYS_CLKRST = (*HP_SYS_CLKRST_Type)(unsafe.Pointer(uintptr(0x500e6000))) + + // LP_HUK Peripheral + LP_HUK = (*HUK_Type)(unsafe.Pointer(uintptr(0x50114000))) + + // I2C (Inter-Integrated Circuit) Controller 0 + I2C0 = (*I2C_Type)(unsafe.Pointer(uintptr(0x500c4000))) + + // I2S (Inter-IC Sound) Controller 0 + I2S0 = (*I2S_Type)(unsafe.Pointer(uintptr(0x500c6000))) + + // I3C Controller (Master) + I3C_MST = (*I3C_MST_Type)(unsafe.Pointer(uintptr(0x500da000))) + + // I3C_MST_MEM Peripheral + I3C_MST_MEM = (*I3C_MST_MEM_Type)(unsafe.Pointer(uintptr(0x500da000))) + + // I3C Controller (Slave) + I3C_SLV = (*I3C_SLV_Type)(unsafe.Pointer(uintptr(0x500db000))) + + // AXI_ICM Peripheral + AXI_ICM = (*ICM_AXI_Type)(unsafe.Pointer(uintptr(0x500a4000))) + + // Input/Output Multiplexer + IO_MUX = (*IO_MUX_Type)(unsafe.Pointer(uintptr(0x500e1000))) + + // ISP Peripheral + ISP = (*ISP_Type)(unsafe.Pointer(uintptr(0x500a1000))) + + // JPEG Codec + JPEG = (*JPEG_Type)(unsafe.Pointer(uintptr(0x50086000))) + + // Camera/LCD Controller + LCD_CAM = (*LCDCAM_Type)(unsafe.Pointer(uintptr(0x500dc000))) + + // LED Control PWM (Pulse Width Modulation) + LEDC = (*LEDC_Type)(unsafe.Pointer(uintptr(0x500d3000))) + + // Low-power Interrupt Controller + LP_INTR = (*LPINTR_Type)(unsafe.Pointer(uintptr(0x5012c000))) + + // LP_PERI Peripheral + LP_PERI = (*LPPERI_Type)(unsafe.Pointer(uintptr(0x50120000))) + + // LP_SYS Peripheral + LP_SYS = (*LPSYSREG_Type)(unsafe.Pointer(uintptr(0x50110000))) + + // LP_ANA_PERI Peripheral + LP_ANA_PERI = (*LP_ANA_PERI_Type)(unsafe.Pointer(uintptr(0x50113000))) + + // LP_AON_CLKRST Peripheral + LP_AON_CLKRST = (*LP_AON_CLKRST_Type)(unsafe.Pointer(uintptr(0x50111000))) + + // Low-power General Purpose Input/Output + LP_GPIO = (*LP_GPIO_Type)(unsafe.Pointer(uintptr(0x5012a000))) + + // Low-power I2C (Inter-Integrated Circuit) Controller 0 + LP_I2C0 = (*LP_I2C_Type)(unsafe.Pointer(uintptr(0x50122000))) + + // Low-power I2S (Inter-IC Sound) Controller 0 + LP_I2S0 = (*LP_I2S_Type)(unsafe.Pointer(uintptr(0x50125000))) + + // Low-power Input/Output Multiplexer + LP_IO_MUX = (*LP_IOMUX_Type)(unsafe.Pointer(uintptr(0x5012b000))) + + // Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + LP_UART = (*LP_UART_Type)(unsafe.Pointer(uintptr(0x50121000))) + + // Motor Control Pulse-Width Modulation 0 + MCPWM0 = (*MCPWM_Type)(unsafe.Pointer(uintptr(0x500c0000))) + + // Parallel IO Controller + PARL_IO = (*PARL_IO_Type)(unsafe.Pointer(uintptr(0x500cf000))) + + // PAU Peripheral + PAU = (*PAU_Type)(unsafe.Pointer(uintptr(0x60093000))) + + // Pulse Count Controller + PCNT = (*PCNT_Type)(unsafe.Pointer(uintptr(0x500c9000))) + + // PMU Peripheral + PMU = (*PMU_Type)(unsafe.Pointer(uintptr(0x50115000))) + + // PPA Peripheral + PPA = (*PPA_Type)(unsafe.Pointer(uintptr(0x50087000))) + + // PVT Peripheral + PVT = (*PVT_Type)(unsafe.Pointer(uintptr(0x5009e000))) + + // Remote Control + RMT = (*RMT_Type)(unsafe.Pointer(uintptr(0x500d4000))) + + // RSA (Rivest Shamir Adleman) Accelerator + RSA = (*RSA_Type)(unsafe.Pointer(uintptr(0x50092000))) + + // Low-power Analog to Digital Converter + LP_ADC = (*RTCADC_Type)(unsafe.Pointer(uintptr(0x50127000))) + + // Low-power Timer + LP_TIMER = (*RTC_TIMER_Type)(unsafe.Pointer(uintptr(0x50112000))) + + // LP_TOUCH Peripheral + LP_TOUCH = (*RTC_TOUCH_Type)(unsafe.Pointer(uintptr(0x50128000))) + + // Low-power Watchdog Timer + LP_WDT = (*RTC_WDT_Type)(unsafe.Pointer(uintptr(0x50116000))) + + // SD/MMC Host Controller + SDHOST = (*SDHOST_Type)(unsafe.Pointer(uintptr(0x50083000))) + + // SHA (Secure Hash Algorithm) Accelerator + SHA = (*SHA_Type)(unsafe.Pointer(uintptr(0x50091000))) + + // Event Task Matrix + SOC_ETM = (*SOC_ETM_Type)(unsafe.Pointer(uintptr(0x500d5000))) + + // SPI (Serial Peripheral Interface) Controller 0 + SPI0 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x5008c000))) + + // SPI (Serial Peripheral Interface) Controller 1 + SPI1 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x5008d000))) + + // SPI (Serial Peripheral Interface) Controller 2 + SPI2 = (*SPI2_Type)(unsafe.Pointer(uintptr(0x500d0000))) + + // SPI (Serial Peripheral Interface) Controller 3 + SPI3 = (*SPI3_Type)(unsafe.Pointer(uintptr(0x500d1000))) + + // System Timer + SYSTIMER = (*SYSTIMER_Type)(unsafe.Pointer(uintptr(0x500e2000))) + + // Timer Group 0 + TIMG0 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x500c2000))) + + // TRACE0 Peripheral + TRACE0 = (*TRACE_Type)(unsafe.Pointer(uintptr(0x3ff04000))) + + // Low-power Temperature Sensor + LP_TSENS = (*TSENS_Type)(unsafe.Pointer(uintptr(0x5012f000))) + + // Two-Wire Automotive Interface + TWAI0 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x500d7000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART0 = (*UART_Type)(unsafe.Pointer(uintptr(0x500ca000))) + + // Universal Host Controller Interface 0 + UHCI0 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x500df000))) + + // Full-speed USB Serial/JTAG Controller + USB_DEVICE = (*USB_DEVICE_Type)(unsafe.Pointer(uintptr(0x500d2000))) + + // USB_WRAP Peripheral + USB_WRAP = (*USB_WRAP_Type)(unsafe.Pointer(uintptr(0x50080000))) + + // I2C (Inter-Integrated Circuit) Controller 1 + I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x500c5000))) + + // I2S (Inter-IC Sound) Controller 1 + I2S1 = (*I2S_Type)(unsafe.Pointer(uintptr(0x500c7000))) + + // I2S (Inter-IC Sound) Controller 2 + I2S2 = (*I2S_Type)(unsafe.Pointer(uintptr(0x500c8000))) + + // Motor Control Pulse-Width Modulation 1 + MCPWM1 = (*MCPWM_Type)(unsafe.Pointer(uintptr(0x500c1000))) + + // Timer Group 1 + TIMG1 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x500c3000))) + + // TRACE1 Peripheral + TRACE1 = (*TRACE_Type)(unsafe.Pointer(uintptr(0x3ff05000))) + + // Two-Wire Automotive Interface + TWAI1 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x500d8000))) + + // Two-Wire Automotive Interface + TWAI2 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x500d9000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + UART1 = (*UART_Type)(unsafe.Pointer(uintptr(0x500cb000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + UART2 = (*UART_Type)(unsafe.Pointer(uintptr(0x500cc000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 3 + UART3 = (*UART_Type)(unsafe.Pointer(uintptr(0x500cd000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 4 + UART4 = (*UART_Type)(unsafe.Pointer(uintptr(0x500ce000))) +) + +// ADC (Analog to Digital Converter) +type ADC_Type struct { + CTRL volatile.Register32 // 0x0 + CTRL2 volatile.Register32 // 0x4 + FILTER_CTRL1 volatile.Register32 // 0x8 + FSM_WAIT volatile.Register32 // 0xC + SAR1_STATUS volatile.Register32 // 0x10 + SAR2_STATUS volatile.Register32 // 0x14 + SAR1_PATT_TAB1 volatile.Register32 // 0x18 + SAR1_PATT_TAB2 volatile.Register32 // 0x1C + SAR1_PATT_TAB3 volatile.Register32 // 0x20 + SAR1_PATT_TAB4 volatile.Register32 // 0x24 + SAR2_PATT_TAB1 volatile.Register32 // 0x28 + SAR2_PATT_TAB2 volatile.Register32 // 0x2C + SAR2_PATT_TAB3 volatile.Register32 // 0x30 + SAR2_PATT_TAB4 volatile.Register32 // 0x34 + ARB_CTRL volatile.Register32 // 0x38 + FILTER_CTRL0 volatile.Register32 // 0x3C + SAR1_DATA_STATUS volatile.Register32 // 0x40 + THRES0_CTRL volatile.Register32 // 0x44 + THRES1_CTRL volatile.Register32 // 0x48 + THRES_CTRL volatile.Register32 // 0x4C + INT_ENA volatile.Register32 // 0x50 + INT_RAW volatile.Register32 // 0x54 + INT_ST volatile.Register32 // 0x58 + INT_CLR volatile.Register32 // 0x5C + DMA_CONF volatile.Register32 // 0x60 + SAR2_DATA_STATUS volatile.Register32 // 0x64 + CALI volatile.Register32 // 0x68 + RND_ECO_LOW volatile.Register32 // 0x6C + RND_ECO_HIGH volatile.Register32 // 0x70 + RND_ECO_CS volatile.Register32 // 0x74 + _ [900]byte + CTRL_DATE volatile.Register32 // 0x3FC +} + +// ADC.CTRL: Register +func (o *ADC_Type) SetCTRL_START_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *ADC_Type) GetCTRL_START_FORCE() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *ADC_Type) SetCTRL_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *ADC_Type) GetCTRL_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *ADC_Type) SetCTRL_WORK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc)|value<<2) +} +func (o *ADC_Type) GetCTRL_WORK_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc) >> 2 +} +func (o *ADC_Type) SetCTRL_SAR_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *ADC_Type) GetCTRL_SAR_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *ADC_Type) SetCTRL_SAR_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *ADC_Type) GetCTRL_SAR_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *ADC_Type) SetCTRL_SAR_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3fc0)|value<<6) +} +func (o *ADC_Type) GetCTRL_SAR_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x3fc0) >> 6 +} +func (o *ADC_Type) SetCTRL_SAR1_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3c000)|value<<14) +} +func (o *ADC_Type) GetCTRL_SAR1_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x3c000) >> 14 +} +func (o *ADC_Type) SetCTRL_SAR2_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3c0000)|value<<18) +} +func (o *ADC_Type) GetCTRL_SAR2_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x3c0000) >> 18 +} +func (o *ADC_Type) SetCTRL_SAR1_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *ADC_Type) GetCTRL_SAR1_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400000) >> 22 +} +func (o *ADC_Type) SetCTRL_SAR2_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *ADC_Type) GetCTRL_SAR2_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *ADC_Type) SetCTRL_DATA_SAR_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *ADC_Type) GetCTRL_DATA_SAR_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} +func (o *ADC_Type) SetCTRL_DATA_TO_I2S(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *ADC_Type) GetCTRL_DATA_TO_I2S() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000000) >> 25 +} +func (o *ADC_Type) SetCTRL_XPD_SAR1_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc000000)|value<<26) +} +func (o *ADC_Type) GetCTRL_XPD_SAR1_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc000000) >> 26 +} +func (o *ADC_Type) SetCTRL_XPD_SAR2_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x30000000)|value<<28) +} +func (o *ADC_Type) GetCTRL_XPD_SAR2_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x30000000) >> 28 +} +func (o *ADC_Type) SetCTRL_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *ADC_Type) GetCTRL_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc0000000) >> 30 +} + +// ADC.CTRL2: Register +func (o *ADC_Type) SetCTRL2_MEAS_NUM_LIMIT(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1)|value) +} +func (o *ADC_Type) GetCTRL2_MEAS_NUM_LIMIT() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1 +} +func (o *ADC_Type) SetCTRL2_MAX_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1fe)|value<<1) +} +func (o *ADC_Type) GetCTRL2_MAX_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1fe) >> 1 +} +func (o *ADC_Type) SetCTRL2_SAR1_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *ADC_Type) GetCTRL2_SAR1_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x200) >> 9 +} +func (o *ADC_Type) SetCTRL2_SAR2_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *ADC_Type) GetCTRL2_SAR2_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x400) >> 10 +} +func (o *ADC_Type) SetCTRL2_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x800)|value<<11) +} +func (o *ADC_Type) GetCTRL2_TIMER_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x800) >> 11 +} +func (o *ADC_Type) SetCTRL2_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff000)|value<<12) +} +func (o *ADC_Type) GetCTRL2_TIMER_TARGET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff000) >> 12 +} +func (o *ADC_Type) SetCTRL2_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *ADC_Type) GetCTRL2_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1000000) >> 24 +} + +// ADC.FILTER_CTRL1: Register +func (o *ADC_Type) SetFILTER_CTRL1_FILTER_FACTOR1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0x1c000000)|value<<26) +} +func (o *ADC_Type) GetFILTER_CTRL1_FILTER_FACTOR1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0x1c000000) >> 26 +} +func (o *ADC_Type) SetFILTER_CTRL1_FILTER_FACTOR0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0xe0000000)|value<<29) +} +func (o *ADC_Type) GetFILTER_CTRL1_FILTER_FACTOR0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0xe0000000) >> 29 +} + +// ADC.FSM_WAIT: Register +func (o *ADC_Type) SetFSM_WAIT_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff)|value) +} +func (o *ADC_Type) GetFSM_WAIT_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff +} +func (o *ADC_Type) SetFSM_WAIT_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff00)|value<<8) +} +func (o *ADC_Type) GetFSM_WAIT_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff00) >> 8 +} +func (o *ADC_Type) SetFSM_WAIT_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff0000)|value<<16) +} +func (o *ADC_Type) GetFSM_WAIT_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff0000) >> 16 +} + +// ADC.SAR1_STATUS: Register +func (o *ADC_Type) SetSAR1_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR1_STATUS.Reg, value) +} +func (o *ADC_Type) GetSAR1_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR1_STATUS.Reg) +} + +// ADC.SAR2_STATUS: Register +func (o *ADC_Type) SetSAR2_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR2_STATUS.Reg, value) +} +func (o *ADC_Type) GetSAR2_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR2_STATUS.Reg) +} + +// ADC.SAR1_PATT_TAB1: Register +func (o *ADC_Type) SetSAR1_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB1.Reg)&^(0xffffff)|value) +} +func (o *ADC_Type) GetSAR1_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB1.Reg) & 0xffffff +} + +// ADC.SAR1_PATT_TAB2: Register +func (o *ADC_Type) SetSAR1_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB2.Reg)&^(0xffffff)|value) +} +func (o *ADC_Type) GetSAR1_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB2.Reg) & 0xffffff +} + +// ADC.SAR1_PATT_TAB3: Register +func (o *ADC_Type) SetSAR1_PATT_TAB3(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB3.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB3.Reg)&^(0xffffff)|value) +} +func (o *ADC_Type) GetSAR1_PATT_TAB3() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB3.Reg) & 0xffffff +} + +// ADC.SAR1_PATT_TAB4: Register +func (o *ADC_Type) SetSAR1_PATT_TAB4(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB4.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB4.Reg)&^(0xffffff)|value) +} +func (o *ADC_Type) GetSAR1_PATT_TAB4() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB4.Reg) & 0xffffff +} + +// ADC.SAR2_PATT_TAB1: Register +func (o *ADC_Type) SetSAR2_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB1.Reg)&^(0xffffff)|value) +} +func (o *ADC_Type) GetSAR2_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB1.Reg) & 0xffffff +} + +// ADC.SAR2_PATT_TAB2: Register +func (o *ADC_Type) SetSAR2_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB2.Reg)&^(0xffffff)|value) +} +func (o *ADC_Type) GetSAR2_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB2.Reg) & 0xffffff +} + +// ADC.SAR2_PATT_TAB3: Register +func (o *ADC_Type) SetSAR2_PATT_TAB3(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB3.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB3.Reg)&^(0xffffff)|value) +} +func (o *ADC_Type) GetSAR2_PATT_TAB3() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB3.Reg) & 0xffffff +} + +// ADC.SAR2_PATT_TAB4: Register +func (o *ADC_Type) SetSAR2_PATT_TAB4(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB4.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB4.Reg)&^(0xffffff)|value) +} +func (o *ADC_Type) GetSAR2_PATT_TAB4() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB4.Reg) & 0xffffff +} + +// ADC.ARB_CTRL: Register +func (o *ADC_Type) SetARB_CTRL_ARB_APB_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *ADC_Type) GetARB_CTRL_ARB_APB_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x4) >> 2 +} +func (o *ADC_Type) SetARB_CTRL_ARB_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *ADC_Type) GetARB_CTRL_ARB_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x8) >> 3 +} +func (o *ADC_Type) SetARB_CTRL_ARB_WIFI_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *ADC_Type) GetARB_CTRL_ARB_WIFI_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x10) >> 4 +} +func (o *ADC_Type) SetARB_CTRL_ARB_GRANT_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *ADC_Type) GetARB_CTRL_ARB_GRANT_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x20) >> 5 +} +func (o *ADC_Type) SetARB_CTRL_ARB_APB_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc0)|value<<6) +} +func (o *ADC_Type) GetARB_CTRL_ARB_APB_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc0) >> 6 +} +func (o *ADC_Type) SetARB_CTRL_ARB_RTC_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x300)|value<<8) +} +func (o *ADC_Type) GetARB_CTRL_ARB_RTC_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x300) >> 8 +} +func (o *ADC_Type) SetARB_CTRL_ARB_WIFI_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc00)|value<<10) +} +func (o *ADC_Type) GetARB_CTRL_ARB_WIFI_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc00) >> 10 +} +func (o *ADC_Type) SetARB_CTRL_ARB_FIX_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *ADC_Type) GetARB_CTRL_ARB_FIX_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x1000) >> 12 +} + +// ADC.FILTER_CTRL0: Register +func (o *ADC_Type) SetFILTER_CTRL0_FILTER_CHANNEL1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x7c000)|value<<14) +} +func (o *ADC_Type) GetFILTER_CTRL0_FILTER_CHANNEL1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x7c000) >> 14 +} +func (o *ADC_Type) SetFILTER_CTRL0_FILTER_CHANNEL0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0xf80000)|value<<19) +} +func (o *ADC_Type) GetFILTER_CTRL0_FILTER_CHANNEL0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0xf80000) >> 19 +} +func (o *ADC_Type) SetFILTER_CTRL0_FILTER_RESET(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x80000000)|value<<31) +} +func (o *ADC_Type) GetFILTER_CTRL0_FILTER_RESET() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x80000000) >> 31 +} + +// ADC.SAR1_DATA_STATUS: Register +func (o *ADC_Type) SetSAR1_DATA_STATUS_APB_SARADC1_DATA(value uint32) { + volatile.StoreUint32(&o.SAR1_DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR1_DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *ADC_Type) GetSAR1_DATA_STATUS_APB_SARADC1_DATA() uint32 { + return volatile.LoadUint32(&o.SAR1_DATA_STATUS.Reg) & 0x1ffff +} + +// ADC.THRES0_CTRL: Register +func (o *ADC_Type) SetTHRES0_CTRL_THRES0_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x1f)|value) +} +func (o *ADC_Type) GetTHRES0_CTRL_THRES0_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x1f +} +func (o *ADC_Type) SetTHRES0_CTRL_THRES0_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *ADC_Type) GetTHRES0_CTRL_THRES0_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *ADC_Type) SetTHRES0_CTRL_THRES0_LOW(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *ADC_Type) GetTHRES0_CTRL_THRES0_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// ADC.THRES1_CTRL: Register +func (o *ADC_Type) SetTHRES1_CTRL_THRES1_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x1f)|value) +} +func (o *ADC_Type) GetTHRES1_CTRL_THRES1_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x1f +} +func (o *ADC_Type) SetTHRES1_CTRL_THRES1_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *ADC_Type) GetTHRES1_CTRL_THRES1_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *ADC_Type) SetTHRES1_CTRL_THRES1_LOW(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *ADC_Type) GetTHRES1_CTRL_THRES1_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// ADC.THRES_CTRL: Register +func (o *ADC_Type) SetTHRES_CTRL_THRES_ALL_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *ADC_Type) GetTHRES_CTRL_THRES_ALL_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *ADC_Type) SetTHRES_CTRL_THRES3_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *ADC_Type) GetTHRES_CTRL_THRES3_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *ADC_Type) SetTHRES_CTRL_THRES2_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *ADC_Type) GetTHRES_CTRL_THRES2_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *ADC_Type) SetTHRES_CTRL_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *ADC_Type) GetTHRES_CTRL_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *ADC_Type) SetTHRES_CTRL_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *ADC_Type) GetTHRES_CTRL_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x80000000) >> 31 +} + +// ADC.INT_ENA: Register +func (o *ADC_Type) SetINT_ENA_THRES1_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *ADC_Type) GetINT_ENA_THRES1_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *ADC_Type) SetINT_ENA_THRES0_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *ADC_Type) GetINT_ENA_THRES0_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *ADC_Type) SetINT_ENA_THRES1_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *ADC_Type) GetINT_ENA_THRES1_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *ADC_Type) SetINT_ENA_THRES0_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *ADC_Type) GetINT_ENA_THRES0_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *ADC_Type) SetINT_ENA_SAR2_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *ADC_Type) GetINT_ENA_SAR2_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *ADC_Type) SetINT_ENA_SAR1_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *ADC_Type) GetINT_ENA_SAR1_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// ADC.INT_RAW: Register +func (o *ADC_Type) SetINT_RAW_THRES1_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *ADC_Type) GetINT_RAW_THRES1_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *ADC_Type) SetINT_RAW_THRES0_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *ADC_Type) GetINT_RAW_THRES0_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *ADC_Type) SetINT_RAW_THRES1_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *ADC_Type) GetINT_RAW_THRES1_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *ADC_Type) SetINT_RAW_THRES0_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *ADC_Type) GetINT_RAW_THRES0_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *ADC_Type) SetINT_RAW_SAR2_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *ADC_Type) GetINT_RAW_SAR2_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *ADC_Type) SetINT_RAW_SAR1_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *ADC_Type) GetINT_RAW_SAR1_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// ADC.INT_ST: Register +func (o *ADC_Type) SetINT_ST_THRES1_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *ADC_Type) GetINT_ST_THRES1_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *ADC_Type) SetINT_ST_THRES0_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *ADC_Type) GetINT_ST_THRES0_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *ADC_Type) SetINT_ST_THRES1_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *ADC_Type) GetINT_ST_THRES1_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *ADC_Type) SetINT_ST_THRES0_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *ADC_Type) GetINT_ST_THRES0_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *ADC_Type) SetINT_ST_APB_SARADC2_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *ADC_Type) GetINT_ST_APB_SARADC2_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *ADC_Type) SetINT_ST_APB_SARADC1_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *ADC_Type) GetINT_ST_APB_SARADC1_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// ADC.INT_CLR: Register +func (o *ADC_Type) SetINT_CLR_THRES1_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *ADC_Type) GetINT_CLR_THRES1_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *ADC_Type) SetINT_CLR_THRES0_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *ADC_Type) GetINT_CLR_THRES0_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *ADC_Type) SetINT_CLR_THRES1_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *ADC_Type) GetINT_CLR_THRES1_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *ADC_Type) SetINT_CLR_THRES0_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *ADC_Type) GetINT_CLR_THRES0_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *ADC_Type) SetINT_CLR_APB_SARADC2_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *ADC_Type) GetINT_CLR_APB_SARADC2_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *ADC_Type) SetINT_CLR_APB_SARADC1_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *ADC_Type) GetINT_CLR_APB_SARADC1_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// ADC.DMA_CONF: Register +func (o *ADC_Type) SetDMA_CONF_APB_ADC_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0xffff)|value) +} +func (o *ADC_Type) GetDMA_CONF_APB_ADC_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0xffff +} +func (o *ADC_Type) SetDMA_CONF_APB_ADC_RESET_FSM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *ADC_Type) GetDMA_CONF_APB_ADC_RESET_FSM() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *ADC_Type) SetDMA_CONF_APB_ADC_TRANS(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *ADC_Type) GetDMA_CONF_APB_ADC_TRANS() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// ADC.SAR2_DATA_STATUS: Register +func (o *ADC_Type) SetSAR2_DATA_STATUS_APB_SARADC2_DATA(value uint32) { + volatile.StoreUint32(&o.SAR2_DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR2_DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *ADC_Type) GetSAR2_DATA_STATUS_APB_SARADC2_DATA() uint32 { + return volatile.LoadUint32(&o.SAR2_DATA_STATUS.Reg) & 0x1ffff +} + +// ADC.CALI: Register +func (o *ADC_Type) SetCALI_CFG(value uint32) { + volatile.StoreUint32(&o.CALI.Reg, volatile.LoadUint32(&o.CALI.Reg)&^(0x1ffff)|value) +} +func (o *ADC_Type) GetCALI_CFG() uint32 { + return volatile.LoadUint32(&o.CALI.Reg) & 0x1ffff +} + +// ADC.RND_ECO_LOW: Register +func (o *ADC_Type) SetRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value) +} +func (o *ADC_Type) GetRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RND_ECO_LOW.Reg) +} + +// ADC.RND_ECO_HIGH: Register +func (o *ADC_Type) SetRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value) +} +func (o *ADC_Type) GetRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg) +} + +// ADC.RND_ECO_CS: Register +func (o *ADC_Type) SetRND_ECO_CS_RND_ECO_EN(value uint32) { + volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x1)|value) +} +func (o *ADC_Type) GetRND_ECO_CS_RND_ECO_EN() uint32 { + return volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x1 +} +func (o *ADC_Type) SetRND_ECO_CS_RND_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *ADC_Type) GetRND_ECO_CS_RND_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x2) >> 1 +} + +// ADC.CTRL_DATE: Register +func (o *ADC_Type) SetCTRL_DATE(value uint32) { + volatile.StoreUint32(&o.CTRL_DATE.Reg, volatile.LoadUint32(&o.CTRL_DATE.Reg)&^(0x7fffffff)|value) +} +func (o *ADC_Type) GetCTRL_DATE() uint32 { + return volatile.LoadUint32(&o.CTRL_DATE.Reg) & 0x7fffffff +} +func (o *ADC_Type) SetCTRL_DATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL_DATE.Reg, volatile.LoadUint32(&o.CTRL_DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *ADC_Type) GetCTRL_DATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL_DATE.Reg) & 0x80000000) >> 31 +} + +// AES (Advanced Encryption Standard) Accelerator +type AES_Type struct { + KEY_0 volatile.Register32 // 0x0 + KEY_1 volatile.Register32 // 0x4 + KEY_2 volatile.Register32 // 0x8 + KEY_3 volatile.Register32 // 0xC + KEY_4 volatile.Register32 // 0x10 + KEY_5 volatile.Register32 // 0x14 + KEY_6 volatile.Register32 // 0x18 + KEY_7 volatile.Register32 // 0x1C + TEXT_IN_0 volatile.Register32 // 0x20 + TEXT_IN_1 volatile.Register32 // 0x24 + TEXT_IN_2 volatile.Register32 // 0x28 + TEXT_IN_3 volatile.Register32 // 0x2C + TEXT_OUT_0 volatile.Register32 // 0x30 + TEXT_OUT_1 volatile.Register32 // 0x34 + TEXT_OUT_2 volatile.Register32 // 0x38 + TEXT_OUT_3 volatile.Register32 // 0x3C + MODE volatile.Register32 // 0x40 + ENDIAN volatile.Register32 // 0x44 + TRIGGER volatile.Register32 // 0x48 + STATE volatile.Register32 // 0x4C + IV_MEM [4]volatile.Register32 // 0x50 + H_MEM [4]volatile.Register32 // 0x60 + J0_MEM [4]volatile.Register32 // 0x70 + T0_MEM [4]volatile.Register32 // 0x80 + DMA_ENABLE volatile.Register32 // 0x90 + BLOCK_MODE volatile.Register32 // 0x94 + BLOCK_NUM volatile.Register32 // 0x98 + INC_SEL volatile.Register32 // 0x9C + AAD_BLOCK_NUM volatile.Register32 // 0xA0 + REMAINDER_BIT_NUM volatile.Register32 // 0xA4 + CONTINUE volatile.Register32 // 0xA8 + INT_CLEAR volatile.Register32 // 0xAC + INT_ENA volatile.Register32 // 0xB0 + DATE volatile.Register32 // 0xB4 + DMA_EXIT volatile.Register32 // 0xB8 +} + +// AES.KEY_0: Key material key_0 configure register +func (o *AES_Type) SetKEY_0(value uint32) { + volatile.StoreUint32(&o.KEY_0.Reg, value) +} +func (o *AES_Type) GetKEY_0() uint32 { + return volatile.LoadUint32(&o.KEY_0.Reg) +} + +// AES.KEY_1: Key material key_1 configure register +func (o *AES_Type) SetKEY_1(value uint32) { + volatile.StoreUint32(&o.KEY_1.Reg, value) +} +func (o *AES_Type) GetKEY_1() uint32 { + return volatile.LoadUint32(&o.KEY_1.Reg) +} + +// AES.KEY_2: Key material key_2 configure register +func (o *AES_Type) SetKEY_2(value uint32) { + volatile.StoreUint32(&o.KEY_2.Reg, value) +} +func (o *AES_Type) GetKEY_2() uint32 { + return volatile.LoadUint32(&o.KEY_2.Reg) +} + +// AES.KEY_3: Key material key_3 configure register +func (o *AES_Type) SetKEY_3(value uint32) { + volatile.StoreUint32(&o.KEY_3.Reg, value) +} +func (o *AES_Type) GetKEY_3() uint32 { + return volatile.LoadUint32(&o.KEY_3.Reg) +} + +// AES.KEY_4: Key material key_4 configure register +func (o *AES_Type) SetKEY_4(value uint32) { + volatile.StoreUint32(&o.KEY_4.Reg, value) +} +func (o *AES_Type) GetKEY_4() uint32 { + return volatile.LoadUint32(&o.KEY_4.Reg) +} + +// AES.KEY_5: Key material key_5 configure register +func (o *AES_Type) SetKEY_5(value uint32) { + volatile.StoreUint32(&o.KEY_5.Reg, value) +} +func (o *AES_Type) GetKEY_5() uint32 { + return volatile.LoadUint32(&o.KEY_5.Reg) +} + +// AES.KEY_6: Key material key_6 configure register +func (o *AES_Type) SetKEY_6(value uint32) { + volatile.StoreUint32(&o.KEY_6.Reg, value) +} +func (o *AES_Type) GetKEY_6() uint32 { + return volatile.LoadUint32(&o.KEY_6.Reg) +} + +// AES.KEY_7: Key material key_7 configure register +func (o *AES_Type) SetKEY_7(value uint32) { + volatile.StoreUint32(&o.KEY_7.Reg, value) +} +func (o *AES_Type) GetKEY_7() uint32 { + return volatile.LoadUint32(&o.KEY_7.Reg) +} + +// AES.TEXT_IN_0: source text material text_in_0 configure register +func (o *AES_Type) SetTEXT_IN_0(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_0.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_0() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_0.Reg) +} + +// AES.TEXT_IN_1: source text material text_in_1 configure register +func (o *AES_Type) SetTEXT_IN_1(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_1.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_1() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_1.Reg) +} + +// AES.TEXT_IN_2: source text material text_in_2 configure register +func (o *AES_Type) SetTEXT_IN_2(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_2.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_2() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_2.Reg) +} + +// AES.TEXT_IN_3: source text material text_in_3 configure register +func (o *AES_Type) SetTEXT_IN_3(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_3.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_3() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_3.Reg) +} + +// AES.TEXT_OUT_0: result text material text_out_0 configure register +func (o *AES_Type) SetTEXT_OUT_0(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_0.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_0() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_0.Reg) +} + +// AES.TEXT_OUT_1: result text material text_out_1 configure register +func (o *AES_Type) SetTEXT_OUT_1(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_1.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_1() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_1.Reg) +} + +// AES.TEXT_OUT_2: result text material text_out_2 configure register +func (o *AES_Type) SetTEXT_OUT_2(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_2.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_2() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_2.Reg) +} + +// AES.TEXT_OUT_3: result text material text_out_3 configure register +func (o *AES_Type) SetTEXT_OUT_3(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_3.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_3() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_3.Reg) +} + +// AES.MODE: AES Mode register +func (o *AES_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// AES.ENDIAN: AES Endian configure register +func (o *AES_Type) SetENDIAN(value uint32) { + volatile.StoreUint32(&o.ENDIAN.Reg, volatile.LoadUint32(&o.ENDIAN.Reg)&^(0x3f)|value) +} +func (o *AES_Type) GetENDIAN() uint32 { + return volatile.LoadUint32(&o.ENDIAN.Reg) & 0x3f +} + +// AES.TRIGGER: AES trigger register +func (o *AES_Type) SetTRIGGER(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetTRIGGER() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} + +// AES.STATE: AES state register +func (o *AES_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *AES_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// AES.DMA_ENABLE: DMA-AES working mode register +func (o *AES_Type) SetDMA_ENABLE(value uint32) { + volatile.StoreUint32(&o.DMA_ENABLE.Reg, volatile.LoadUint32(&o.DMA_ENABLE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_ENABLE() uint32 { + return volatile.LoadUint32(&o.DMA_ENABLE.Reg) & 0x1 +} + +// AES.BLOCK_MODE: AES cipher block mode register +func (o *AES_Type) SetBLOCK_MODE(value uint32) { + volatile.StoreUint32(&o.BLOCK_MODE.Reg, volatile.LoadUint32(&o.BLOCK_MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetBLOCK_MODE() uint32 { + return volatile.LoadUint32(&o.BLOCK_MODE.Reg) & 0x7 +} + +// AES.BLOCK_NUM: AES block number register +func (o *AES_Type) SetBLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetBLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.BLOCK_NUM.Reg) +} + +// AES.INC_SEL: Standard incrementing function configure register +func (o *AES_Type) SetINC_SEL(value uint32) { + volatile.StoreUint32(&o.INC_SEL.Reg, volatile.LoadUint32(&o.INC_SEL.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINC_SEL() uint32 { + return volatile.LoadUint32(&o.INC_SEL.Reg) & 0x1 +} + +// AES.AAD_BLOCK_NUM: Additional Authential Data block number register +func (o *AES_Type) SetAAD_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.AAD_BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetAAD_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.AAD_BLOCK_NUM.Reg) +} + +// AES.REMAINDER_BIT_NUM: AES remainder bit number register +func (o *AES_Type) SetREMAINDER_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.REMAINDER_BIT_NUM.Reg, volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg)&^(0x7f)|value) +} +func (o *AES_Type) GetREMAINDER_BIT_NUM() uint32 { + return volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg) & 0x7f +} + +// AES.CONTINUE: AES continue register +func (o *AES_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetCONTINUE() uint32 { + return volatile.LoadUint32(&o.CONTINUE.Reg) & 0x1 +} + +// AES.INT_CLEAR: AES Interrupt clear register +func (o *AES_Type) SetINT_CLEAR(value uint32) { + volatile.StoreUint32(&o.INT_CLEAR.Reg, volatile.LoadUint32(&o.INT_CLEAR.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_CLEAR() uint32 { + return volatile.LoadUint32(&o.INT_CLEAR.Reg) & 0x1 +} + +// AES.INT_ENA: AES Interrupt enable register +func (o *AES_Type) SetINT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// AES.DATE: AES version control register +func (o *AES_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *AES_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// AES.DMA_EXIT: AES-DMA exit config +func (o *AES_Type) SetDMA_EXIT(value uint32) { + volatile.StoreUint32(&o.DMA_EXIT.Reg, volatile.LoadUint32(&o.DMA_EXIT.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_EXIT() uint32 { + return volatile.LoadUint32(&o.DMA_EXIT.Reg) & 0x1 +} + +// AHB_DMA Peripheral +type AHB_DMA_Type struct { + IN_INT_RAW_CH0 volatile.Register32 // 0x0 + IN_INT_ST_CH0 volatile.Register32 // 0x4 + IN_INT_ENA_CH0 volatile.Register32 // 0x8 + IN_INT_CLR_CH0 volatile.Register32 // 0xC + IN_INT_RAW_CH1 volatile.Register32 // 0x10 + IN_INT_ST_CH1 volatile.Register32 // 0x14 + IN_INT_ENA_CH1 volatile.Register32 // 0x18 + IN_INT_CLR_CH1 volatile.Register32 // 0x1C + IN_INT_RAW_CH2 volatile.Register32 // 0x20 + IN_INT_ST_CH2 volatile.Register32 // 0x24 + IN_INT_ENA_CH2 volatile.Register32 // 0x28 + IN_INT_CLR_CH2 volatile.Register32 // 0x2C + OUT_INT_RAW_CH0 volatile.Register32 // 0x30 + OUT_INT_ST_CH0 volatile.Register32 // 0x34 + OUT_INT_ENA_CH0 volatile.Register32 // 0x38 + OUT_INT_CLR_CH0 volatile.Register32 // 0x3C + OUT_INT_RAW_CH1 volatile.Register32 // 0x40 + OUT_INT_ST_CH1 volatile.Register32 // 0x44 + OUT_INT_ENA_CH1 volatile.Register32 // 0x48 + OUT_INT_CLR_CH1 volatile.Register32 // 0x4C + OUT_INT_RAW_CH2 volatile.Register32 // 0x50 + OUT_INT_ST_CH2 volatile.Register32 // 0x54 + OUT_INT_ENA_CH2 volatile.Register32 // 0x58 + OUT_INT_CLR_CH2 volatile.Register32 // 0x5C + AHB_TEST volatile.Register32 // 0x60 + MISC_CONF volatile.Register32 // 0x64 + DATE volatile.Register32 // 0x68 + _ [4]byte + IN_CONF0_CH0 volatile.Register32 // 0x70 + IN_CONF1_CH0 volatile.Register32 // 0x74 + INFIFO_STATUS_CH0 volatile.Register32 // 0x78 + IN_POP_CH0 volatile.Register32 // 0x7C + IN_LINK_CH0 volatile.Register32 // 0x80 + IN_STATE_CH0 volatile.Register32 // 0x84 + IN_SUC_EOF_DES_ADDR_CH0 volatile.Register32 // 0x88 + IN_ERR_EOF_DES_ADDR_CH0 volatile.Register32 // 0x8C + IN_DSCR_CH0 volatile.Register32 // 0x90 + IN_DSCR_BF0_CH0 volatile.Register32 // 0x94 + IN_DSCR_BF1_CH0 volatile.Register32 // 0x98 + IN_PRI_CH0 volatile.Register32 // 0x9C + IN_PERI_SEL_CH0 volatile.Register32 // 0xA0 + _ [44]byte + OUT_CONF0_CH0 volatile.Register32 // 0xD0 + OUT_CONF1_CH0 volatile.Register32 // 0xD4 + OUTFIFO_STATUS_CH0 volatile.Register32 // 0xD8 + OUT_PUSH_CH0 volatile.Register32 // 0xDC + OUT_LINK_CH0 volatile.Register32 // 0xE0 + OUT_STATE_CH0 volatile.Register32 // 0xE4 + OUT_EOF_DES_ADDR_CH0 volatile.Register32 // 0xE8 + OUT_EOF_BFR_DES_ADDR_CH0 volatile.Register32 // 0xEC + OUT_DSCR_CH0 volatile.Register32 // 0xF0 + OUT_DSCR_BF0_CH0 volatile.Register32 // 0xF4 + OUT_DSCR_BF1_CH0 volatile.Register32 // 0xF8 + OUT_PRI_CH0 volatile.Register32 // 0xFC + OUT_PERI_SEL_CH0 volatile.Register32 // 0x100 + _ [44]byte + IN_CONF0_CH1 volatile.Register32 // 0x130 + IN_CONF1_CH1 volatile.Register32 // 0x134 + INFIFO_STATUS_CH1 volatile.Register32 // 0x138 + IN_POP_CH1 volatile.Register32 // 0x13C + IN_LINK_CH1 volatile.Register32 // 0x140 + IN_STATE_CH1 volatile.Register32 // 0x144 + IN_SUC_EOF_DES_ADDR_CH1 volatile.Register32 // 0x148 + IN_ERR_EOF_DES_ADDR_CH1 volatile.Register32 // 0x14C + IN_DSCR_CH1 volatile.Register32 // 0x150 + IN_DSCR_BF0_CH1 volatile.Register32 // 0x154 + IN_DSCR_BF1_CH1 volatile.Register32 // 0x158 + IN_PRI_CH1 volatile.Register32 // 0x15C + IN_PERI_SEL_CH1 volatile.Register32 // 0x160 + _ [44]byte + OUT_CONF0_CH0 volatile.Register32 // 0x190 + OUT_CONF1_CH1 volatile.Register32 // 0x194 + OUTFIFO_STATUS_CH1 volatile.Register32 // 0x198 + OUT_PUSH_CH1 volatile.Register32 // 0x19C + OUT_LINK_CH1 volatile.Register32 // 0x1A0 + OUT_STATE_CH1 volatile.Register32 // 0x1A4 + OUT_EOF_DES_ADDR_CH1 volatile.Register32 // 0x1A8 + OUT_EOF_BFR_DES_ADDR_CH1 volatile.Register32 // 0x1AC + OUT_DSCR_CH1 volatile.Register32 // 0x1B0 + OUT_DSCR_BF0_CH1 volatile.Register32 // 0x1B4 + OUT_DSCR_BF1_CH1 volatile.Register32 // 0x1B8 + OUT_PRI_CH1 volatile.Register32 // 0x1BC + OUT_PERI_SEL_CH1 volatile.Register32 // 0x1C0 + _ [44]byte + IN_CONF0_CH2 volatile.Register32 // 0x1F0 + IN_CONF1_CH2 volatile.Register32 // 0x1F4 + INFIFO_STATUS_CH2 volatile.Register32 // 0x1F8 + IN_POP_CH2 volatile.Register32 // 0x1FC + IN_LINK_CH2 volatile.Register32 // 0x200 + IN_STATE_CH2 volatile.Register32 // 0x204 + IN_SUC_EOF_DES_ADDR_CH2 volatile.Register32 // 0x208 + IN_ERR_EOF_DES_ADDR_CH2 volatile.Register32 // 0x20C + IN_DSCR_CH2 volatile.Register32 // 0x210 + IN_DSCR_BF0_CH2 volatile.Register32 // 0x214 + IN_DSCR_BF1_CH2 volatile.Register32 // 0x218 + IN_PRI_CH2 volatile.Register32 // 0x21C + IN_PERI_SEL_CH2 volatile.Register32 // 0x220 + _ [44]byte + OUT_CONF0_CH1 volatile.Register32 // 0x250 + OUT_CONF1_CH2 volatile.Register32 // 0x254 + OUTFIFO_STATUS_CH2 volatile.Register32 // 0x258 + OUT_PUSH_CH2 volatile.Register32 // 0x25C + OUT_LINK_CH2 volatile.Register32 // 0x260 + OUT_STATE_CH2 volatile.Register32 // 0x264 + OUT_EOF_DES_ADDR_CH2 volatile.Register32 // 0x268 + OUT_EOF_BFR_DES_ADDR_CH2 volatile.Register32 // 0x26C + OUT_DSCR_CH2 volatile.Register32 // 0x270 + OUT_DSCR_BF0_CH2 volatile.Register32 // 0x274 + OUT_DSCR_BF1_CH2 volatile.Register32 // 0x278 + OUT_PRI_CH2 volatile.Register32 // 0x27C + OUT_PERI_SEL_CH2 volatile.Register32 // 0x280 + _ [56]byte + OUT_CRC_INIT_DATA_CH0 volatile.Register32 // 0x2BC + TX_CRC_WIDTH_CH0 volatile.Register32 // 0x2C0 + OUT_CRC_CLEAR_CH0 volatile.Register32 // 0x2C4 + OUT_CRC_FINAL_RESULT_CH0 volatile.Register32 // 0x2C8 + TX_CRC_EN_WR_DATA_CH0 volatile.Register32 // 0x2CC + TX_CRC_EN_ADDR_CH0 volatile.Register32 // 0x2D0 + TX_CRC_DATA_EN_WR_DATA_CH0 volatile.Register32 // 0x2D4 + TX_CRC_DATA_EN_ADDR_CH0 volatile.Register32 // 0x2D8 + TX_CH_ARB_WEIGH_CH0 volatile.Register32 // 0x2DC + TX_ARB_WEIGH_OPT_DIR_CH0 volatile.Register32 // 0x2E0 + OUT_CRC_INIT_DATA_CH1 volatile.Register32 // 0x2E4 + TX_CRC_WIDTH_CH1 volatile.Register32 // 0x2E8 + OUT_CRC_CLEAR_CH1 volatile.Register32 // 0x2EC + OUT_CRC_FINAL_RESULT_CH1 volatile.Register32 // 0x2F0 + TX_CRC_EN_WR_DATA_CH1 volatile.Register32 // 0x2F4 + TX_CRC_EN_ADDR_CH1 volatile.Register32 // 0x2F8 + TX_CRC_DATA_EN_WR_DATA_CH1 volatile.Register32 // 0x2FC + TX_CRC_DATA_EN_ADDR_CH1 volatile.Register32 // 0x300 + TX_CH_ARB_WEIGH_CH1 volatile.Register32 // 0x304 + TX_ARB_WEIGH_OPT_DIR_CH1 volatile.Register32 // 0x308 + OUT_CRC_INIT_DATA_CH2 volatile.Register32 // 0x30C + TX_CRC_WIDTH_CH2 volatile.Register32 // 0x310 + OUT_CRC_CLEAR_CH2 volatile.Register32 // 0x314 + OUT_CRC_FINAL_RESULT_CH2 volatile.Register32 // 0x318 + TX_CRC_EN_WR_DATA_CH2 volatile.Register32 // 0x31C + TX_CRC_EN_ADDR_CH2 volatile.Register32 // 0x320 + TX_CRC_DATA_EN_WR_DATA_CH2 volatile.Register32 // 0x324 + TX_CRC_DATA_EN_ADDR_CH2 volatile.Register32 // 0x328 + TX_CH_ARB_WEIGH_CH2 volatile.Register32 // 0x32C + TX_ARB_WEIGH_OPT_DIR_CH2 volatile.Register32 // 0x330 + IN_CRC_INIT_DATA_CH0 volatile.Register32 // 0x334 + RX_CRC_WIDTH_CH0 volatile.Register32 // 0x338 + IN_CRC_CLEAR_CH0 volatile.Register32 // 0x33C + IN_CRC_FINAL_RESULT_CH0 volatile.Register32 // 0x340 + RX_CRC_EN_WR_DATA_CH0 volatile.Register32 // 0x344 + RX_CRC_EN_ADDR_CH0 volatile.Register32 // 0x348 + RX_CRC_DATA_EN_WR_DATA_CH0 volatile.Register32 // 0x34C + RX_CRC_DATA_EN_ADDR_CH0 volatile.Register32 // 0x350 + RX_CH_ARB_WEIGH_CH0 volatile.Register32 // 0x354 + RX_ARB_WEIGH_OPT_DIR_CH0 volatile.Register32 // 0x358 + IN_CRC_INIT_DATA_CH1 volatile.Register32 // 0x35C + RX_CRC_WIDTH_CH1 volatile.Register32 // 0x360 + IN_CRC_CLEAR_CH1 volatile.Register32 // 0x364 + IN_CRC_FINAL_RESULT_CH1 volatile.Register32 // 0x368 + RX_CRC_EN_WR_DATA_CH1 volatile.Register32 // 0x36C + RX_CRC_EN_ADDR_CH1 volatile.Register32 // 0x370 + RX_CRC_DATA_EN_WR_DATA_CH1 volatile.Register32 // 0x374 + RX_CRC_DATA_EN_ADDR_CH1 volatile.Register32 // 0x378 + RX_CH_ARB_WEIGH_CH1 volatile.Register32 // 0x37C + RX_ARB_WEIGH_OPT_DIR_CH1 volatile.Register32 // 0x380 + IN_CRC_INIT_DATA_CH2 volatile.Register32 // 0x384 + RX_CRC_WIDTH_CH2 volatile.Register32 // 0x388 + IN_CRC_CLEAR_CH2 volatile.Register32 // 0x38C + IN_CRC_FINAL_RESULT_CH2 volatile.Register32 // 0x390 + RX_CRC_EN_WR_DATA_CH2 volatile.Register32 // 0x394 + RX_CRC_EN_ADDR_CH2 volatile.Register32 // 0x398 + RX_CRC_DATA_EN_WR_DATA_CH2 volatile.Register32 // 0x39C + RX_CRC_DATA_EN_ADDR_CH2 volatile.Register32 // 0x3A0 + RX_CH_ARB_WEIGH_CH2 volatile.Register32 // 0x3A4 + RX_ARB_WEIGH_OPT_DIR_CH2 volatile.Register32 // 0x3A8 + IN_LINK_ADDR_CH0 volatile.Register32 // 0x3AC + IN_LINK_ADDR_CH1 volatile.Register32 // 0x3B0 + IN_LINK_ADDR_CH2 volatile.Register32 // 0x3B4 + OUT_LINK_ADDR_CH0 volatile.Register32 // 0x3B8 + OUT_LINK_ADDR_CH1 volatile.Register32 // 0x3BC + OUT_LINK_ADDR_CH2 volatile.Register32 // 0x3C0 + INTR_MEM_START_ADDR volatile.Register32 // 0x3C4 + INTR_MEM_END_ADDR volatile.Register32 // 0x3C8 + ARB_TIMEOUT_TX volatile.Register32 // 0x3CC + ARB_TIMEOUT_RX volatile.Register32 // 0x3D0 + WEIGHT_EN_TX volatile.Register32 // 0x3D4 + WEIGHT_EN_RX volatile.Register32 // 0x3D8 +} + +// AHB_DMA.IN_INT_RAW_CH0: Raw status interrupt of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_SUC_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_SUC_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_ERR_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_ERR_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_ST_CH0: Masked interrupt of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_SUC_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_SUC_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_ERR_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_ERR_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_ENA_CH0: Interrupt enable bits of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_SUC_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_SUC_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_ERR_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_ERR_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_CLR_CH0: Interrupt clear bits of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_SUC_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_SUC_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_ERR_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_ERR_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_RAW_CH1: Raw status interrupt of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_SUC_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_SUC_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_ERR_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_ERR_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_ST_CH1: Masked interrupt of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_SUC_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_SUC_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_ERR_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_ERR_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_ENA_CH1: Interrupt enable bits of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_SUC_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_SUC_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_ERR_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_ERR_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_CLR_CH1: Interrupt clear bits of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_SUC_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_SUC_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_ERR_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_ERR_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_RAW_CH2: Raw status interrupt of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_SUC_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_SUC_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_ERR_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_ERR_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_ST_CH2: Masked interrupt of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_SUC_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_SUC_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_ERR_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_ERR_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_ENA_CH2: Interrupt enable bits of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_SUC_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_SUC_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_ERR_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_ERR_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x40) >> 6 +} + +// AHB_DMA.IN_INT_CLR_CH2: Interrupt clear bits of channel 0 +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_SUC_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_SUC_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_ERR_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_ERR_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x40) >> 6 +} + +// AHB_DMA.OUT_INT_RAW_CH0: Raw status interrupt of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUT_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUT_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_ST_CH0: Masked interrupt of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUT_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUT_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUT_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUT_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_ENA_CH0: Interrupt enable bits of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUT_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUT_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_CLR_CH0: Interrupt clear bits of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUT_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUT_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_RAW_CH1: Raw status interrupt of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUT_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUT_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_ST_CH1: Masked interrupt of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUT_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUT_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUT_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUT_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_ENA_CH1: Interrupt enable bits of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUT_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUT_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_CLR_CH1: Interrupt clear bits of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUT_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUT_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_RAW_CH2: Raw status interrupt of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUT_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUT_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_ST_CH2: Masked interrupt of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUT_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUT_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUT_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUT_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_ENA_CH2: Interrupt enable bits of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUT_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUT_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x20) >> 5 +} + +// AHB_DMA.OUT_INT_CLR_CH2: Interrupt clear bits of channel 0 +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUT_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUT_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x20) >> 5 +} + +// AHB_DMA.AHB_TEST: reserved +func (o *AHB_DMA_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *AHB_DMA_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *AHB_DMA_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *AHB_DMA_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// AHB_DMA.MISC_CONF: MISC register +func (o *AHB_DMA_Type) SetMISC_CONF_AHBM_RST_INTER(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetMISC_CONF_AHBM_RST_INTER() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetMISC_CONF_ARB_PRI_DIS(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetMISC_CONF_ARB_PRI_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetMISC_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x8) >> 3 +} + +// AHB_DMA.DATE: Version control register +func (o *AHB_DMA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *AHB_DMA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// AHB_DMA.IN_CONF0_CH0: Configure 0 register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_CONF0_CH0_IN_RST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH0_IN_RST_CH() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH0_IN_LOOP_TEST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH0_IN_LOOP_TEST_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH0_IN_DATA_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH0_IN_DATA_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH0_MEM_TRANS_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH0_MEM_TRANS_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH0_IN_ETM_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH0_IN_ETM_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x20) >> 5 +} + +// AHB_DMA.IN_CONF1_CH0: Configure 1 register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_CONF1_CH0_IN_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *AHB_DMA_Type) GetIN_CONF1_CH0_IN_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// AHB_DMA.INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0 +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_CH() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_BUF_HUNGRY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_BUF_HUNGRY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27 +} + +// AHB_DMA.IN_POP_CH0: Pop control register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_POP_CH0_INFIFO_RDATA_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0xfff)|value) +} +func (o *AHB_DMA_Type) GetIN_POP_CH0_INFIFO_RDATA_CH() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0xfff +} +func (o *AHB_DMA_Type) SetIN_POP_CH0_INFIFO_POP_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *AHB_DMA_Type) GetIN_POP_CH0_INFIFO_POP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x1000) >> 12 +} + +// AHB_DMA.IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_AUTO_RET_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_AUTO_RET_CH() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_STOP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x10) >> 4 +} + +// AHB_DMA.IN_STATE_CH0: Receive status of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *AHB_DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff +} +func (o *AHB_DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *AHB_DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *AHB_DMA_Type) SetIN_STATE_CH0_IN_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *AHB_DMA_Type) GetIN_STATE_CH0_IN_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// AHB_DMA.IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg) +} + +// AHB_DMA.IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg) +} + +// AHB_DMA.IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg) +} + +// AHB_DMA.IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg) +} + +// AHB_DMA.IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg) +} + +// AHB_DMA.IN_PRI_CH0: Priority register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_PRI_CH0_RX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetIN_PRI_CH0_RX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf +} + +// AHB_DMA.IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_PERI_SEL_CH0_PERI_IN_SEL_CH(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *AHB_DMA_Type) GetIN_PERI_SEL_CH0_PERI_IN_SEL_CH() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg) & 0x3f +} + +// AHB_DMA.OUT_CONF0_CH0: Configure 0 register of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_RST_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_RST_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_ETM_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_ETM_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x40) >> 6 +} + +// AHB_DMA.OUT_CONF1_CH0: Configure 1 register of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_CONF1_CH0_OUT_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *AHB_DMA_Type) GetOUT_CONF1_CH0_OUT_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// AHB_DMA.OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0 +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_CH() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} + +// AHB_DMA.OUT_PUSH_CH0: Push control register of Rx channel 0 +func (o *AHB_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x1ff)|value) +} +func (o *AHB_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x1ff +} +func (o *AHB_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AHB_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x200) >> 9 +} + +// AHB_DMA.OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_LINK_CH0_OUTLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH0_OUTLINK_STOP_CH() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_LINK_CH0_OUTLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH0_OUTLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_LINK_CH0_OUTLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH0_OUTLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_LINK_CH0_OUTLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH0_OUTLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x8) >> 3 +} + +// AHB_DMA.OUT_STATE_CH0: Transmit status of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *AHB_DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff +} +func (o *AHB_DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *AHB_DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *AHB_DMA_Type) SetOUT_STATE_CH0_OUT_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *AHB_DMA_Type) GetOUT_STATE_CH0_OUT_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// AHB_DMA.OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg) +} + +// AHB_DMA.OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg) +} + +// AHB_DMA.OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg) +} + +// AHB_DMA.OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg) +} + +// AHB_DMA.OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg) +} + +// AHB_DMA.OUT_PRI_CH0: Priority register of Tx channel 0. +func (o *AHB_DMA_Type) SetOUT_PRI_CH0_TX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetOUT_PRI_CH0_TX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf +} + +// AHB_DMA.OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_PERI_SEL_CH0_PERI_OUT_SEL_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *AHB_DMA_Type) GetOUT_PERI_SEL_CH0_PERI_OUT_SEL_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg) & 0x3f +} + +// AHB_DMA.IN_CONF0_CH1: Configure 0 register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_CONF0_CH1_IN_RST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH1_IN_RST_CH() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH1_IN_LOOP_TEST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH1_IN_LOOP_TEST_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH1_IN_DATA_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH1_IN_DATA_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH1_MEM_TRANS_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH1_MEM_TRANS_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH1_IN_ETM_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH1_IN_ETM_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x20) >> 5 +} + +// AHB_DMA.IN_CONF1_CH1: Configure 1 register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_CONF1_CH1_IN_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *AHB_DMA_Type) GetIN_CONF1_CH1_IN_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// AHB_DMA.INFIFO_STATUS_CH1: Receive FIFO status of Rx channel 0 +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_CH() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_BUF_HUNGRY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_BUF_HUNGRY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27 +} + +// AHB_DMA.IN_POP_CH1: Pop control register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_POP_CH1_INFIFO_RDATA_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0xfff)|value) +} +func (o *AHB_DMA_Type) GetIN_POP_CH1_INFIFO_RDATA_CH() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0xfff +} +func (o *AHB_DMA_Type) SetIN_POP_CH1_INFIFO_POP_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *AHB_DMA_Type) GetIN_POP_CH1_INFIFO_POP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x1000) >> 12 +} + +// AHB_DMA.IN_LINK_CH1: Link descriptor configure and control register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_AUTO_RET_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_AUTO_RET_CH() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_STOP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x10) >> 4 +} + +// AHB_DMA.IN_STATE_CH1: Receive status of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *AHB_DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff +} +func (o *AHB_DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *AHB_DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *AHB_DMA_Type) SetIN_STATE_CH1_IN_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *AHB_DMA_Type) GetIN_STATE_CH1_IN_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// AHB_DMA.IN_SUC_EOF_DES_ADDR_CH1: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg) +} + +// AHB_DMA.IN_ERR_EOF_DES_ADDR_CH1: Inlink descriptor address when errors occur of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg) +} + +// AHB_DMA.IN_DSCR_CH1: Current inlink descriptor address of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg) +} + +// AHB_DMA.IN_DSCR_BF0_CH1: The last inlink descriptor address of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg) +} + +// AHB_DMA.IN_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg) +} + +// AHB_DMA.IN_PRI_CH1: Priority register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_PRI_CH1_RX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetIN_PRI_CH1_RX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf +} + +// AHB_DMA.IN_PERI_SEL_CH1: Peripheral selection of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_PERI_SEL_CH1_PERI_IN_SEL_CH(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *AHB_DMA_Type) GetIN_PERI_SEL_CH1_PERI_IN_SEL_CH() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg) & 0x3f +} + +// AHB_DMA.OUT_CONF0_CH0: Configure 0 register of Tx channel 1 +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_RST_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_RST_CH() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_DATA_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_DATA_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_ETM_EN_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_ETM_EN_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x40) >> 6 +} + +// AHB_DMA.OUT_CONF1_CH1: Configure 1 register of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_CONF1_CH1_OUT_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *AHB_DMA_Type) GetOUT_CONF1_CH1_OUT_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// AHB_DMA.OUTFIFO_STATUS_CH1: Transmit FIFO status of Tx channel 0 +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_CH() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} + +// AHB_DMA.OUT_PUSH_CH1: Push control register of Rx channel 0 +func (o *AHB_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x1ff)|value) +} +func (o *AHB_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x1ff +} +func (o *AHB_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AHB_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x200) >> 9 +} + +// AHB_DMA.OUT_LINK_CH1: Link descriptor configure and control register of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_LINK_CH1_OUTLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH1_OUTLINK_STOP_CH() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_LINK_CH1_OUTLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH1_OUTLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_LINK_CH1_OUTLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH1_OUTLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_LINK_CH1_OUTLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH1_OUTLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x8) >> 3 +} + +// AHB_DMA.OUT_STATE_CH1: Transmit status of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *AHB_DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff +} +func (o *AHB_DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *AHB_DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *AHB_DMA_Type) SetOUT_STATE_CH1_OUT_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *AHB_DMA_Type) GetOUT_STATE_CH1_OUT_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// AHB_DMA.OUT_EOF_DES_ADDR_CH1: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg) +} + +// AHB_DMA.OUT_EOF_BFR_DES_ADDR_CH1: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg) +} + +// AHB_DMA.OUT_DSCR_CH1: Current inlink descriptor address of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg) +} + +// AHB_DMA.OUT_DSCR_BF0_CH1: The last inlink descriptor address of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg) +} + +// AHB_DMA.OUT_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg) +} + +// AHB_DMA.OUT_PRI_CH1: Priority register of Tx channel 0. +func (o *AHB_DMA_Type) SetOUT_PRI_CH1_TX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetOUT_PRI_CH1_TX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf +} + +// AHB_DMA.OUT_PERI_SEL_CH1: Peripheral selection of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_PERI_SEL_CH1_PERI_OUT_SEL_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *AHB_DMA_Type) GetOUT_PERI_SEL_CH1_PERI_OUT_SEL_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg) & 0x3f +} + +// AHB_DMA.IN_CONF0_CH2: Configure 0 register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_CONF0_CH2_IN_RST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH2_IN_RST_CH() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH2_IN_LOOP_TEST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH2_IN_LOOP_TEST_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH2_IN_DATA_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH2_IN_DATA_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH2_MEM_TRANS_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH2_MEM_TRANS_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetIN_CONF0_CH2_IN_ETM_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetIN_CONF0_CH2_IN_ETM_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x20) >> 5 +} + +// AHB_DMA.IN_CONF1_CH2: Configure 1 register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_CONF1_CH2_IN_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *AHB_DMA_Type) GetIN_CONF1_CH2_IN_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// AHB_DMA.INFIFO_STATUS_CH2: Receive FIFO status of Rx channel 0 +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_CH() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} +func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_BUF_HUNGRY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27) +} +func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_BUF_HUNGRY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27 +} + +// AHB_DMA.IN_POP_CH2: Pop control register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_POP_CH2_INFIFO_RDATA_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0xfff)|value) +} +func (o *AHB_DMA_Type) GetIN_POP_CH2_INFIFO_RDATA_CH() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0xfff +} +func (o *AHB_DMA_Type) SetIN_POP_CH2_INFIFO_POP_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *AHB_DMA_Type) GetIN_POP_CH2_INFIFO_POP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x1000) >> 12 +} + +// AHB_DMA.IN_LINK_CH2: Link descriptor configure and control register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_AUTO_RET_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_AUTO_RET_CH() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_STOP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x10) >> 4 +} + +// AHB_DMA.IN_STATE_CH2: Receive status of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *AHB_DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff +} +func (o *AHB_DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *AHB_DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *AHB_DMA_Type) SetIN_STATE_CH2_IN_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *AHB_DMA_Type) GetIN_STATE_CH2_IN_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// AHB_DMA.IN_SUC_EOF_DES_ADDR_CH2: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg) +} + +// AHB_DMA.IN_ERR_EOF_DES_ADDR_CH2: Inlink descriptor address when errors occur of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg) +} + +// AHB_DMA.IN_DSCR_CH2: Current inlink descriptor address of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg) +} + +// AHB_DMA.IN_DSCR_BF0_CH2: The last inlink descriptor address of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg) +} + +// AHB_DMA.IN_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg) +} + +// AHB_DMA.IN_PRI_CH2: Priority register of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_PRI_CH2_RX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetIN_PRI_CH2_RX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf +} + +// AHB_DMA.IN_PERI_SEL_CH2: Peripheral selection of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_PERI_SEL_CH2_PERI_IN_SEL_CH(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *AHB_DMA_Type) GetIN_PERI_SEL_CH2_PERI_IN_SEL_CH() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg) & 0x3f +} + +// AHB_DMA.OUT_CONF0_CH1: Configure 0 register of Tx channel 1 +func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_RST_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_RST_CH() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_LOOP_TEST_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_LOOP_TEST_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_DATA_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_DATA_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x20) >> 5 +} +func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_ETM_EN_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_ETM_EN_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x40) >> 6 +} + +// AHB_DMA.OUT_CONF1_CH2: Configure 1 register of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_CONF1_CH2_OUT_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *AHB_DMA_Type) GetOUT_CONF1_CH2_OUT_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// AHB_DMA.OUTFIFO_STATUS_CH2: Transmit FIFO status of Tx channel 0 +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_CH() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} + +// AHB_DMA.OUT_PUSH_CH2: Push control register of Rx channel 0 +func (o *AHB_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x1ff)|value) +} +func (o *AHB_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x1ff +} +func (o *AHB_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AHB_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x200) >> 9 +} + +// AHB_DMA.OUT_LINK_CH2: Link descriptor configure and control register of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_LINK_CH2_OUTLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH2_OUTLINK_STOP_CH() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x1 +} +func (o *AHB_DMA_Type) SetOUT_LINK_CH2_OUTLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH2_OUTLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x2) >> 1 +} +func (o *AHB_DMA_Type) SetOUT_LINK_CH2_OUTLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH2_OUTLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x4) >> 2 +} +func (o *AHB_DMA_Type) SetOUT_LINK_CH2_OUTLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AHB_DMA_Type) GetOUT_LINK_CH2_OUTLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x8) >> 3 +} + +// AHB_DMA.OUT_STATE_CH2: Transmit status of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *AHB_DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff +} +func (o *AHB_DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *AHB_DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *AHB_DMA_Type) SetOUT_STATE_CH2_OUT_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *AHB_DMA_Type) GetOUT_STATE_CH2_OUT_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// AHB_DMA.OUT_EOF_DES_ADDR_CH2: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg) +} + +// AHB_DMA.OUT_EOF_BFR_DES_ADDR_CH2: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg) +} + +// AHB_DMA.OUT_DSCR_CH2: Current inlink descriptor address of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg) +} + +// AHB_DMA.OUT_DSCR_BF0_CH2: The last inlink descriptor address of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg) +} + +// AHB_DMA.OUT_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg) +} + +// AHB_DMA.OUT_PRI_CH2: Priority register of Tx channel 0. +func (o *AHB_DMA_Type) SetOUT_PRI_CH2_TX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetOUT_PRI_CH2_TX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf +} + +// AHB_DMA.OUT_PERI_SEL_CH2: Peripheral selection of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_PERI_SEL_CH2_PERI_OUT_SEL_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *AHB_DMA_Type) GetOUT_PERI_SEL_CH2_PERI_OUT_SEL_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg) & 0x3f +} + +// AHB_DMA.OUT_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AHB_DMA_Type) SetOUT_CRC_INIT_DATA_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_CRC_INIT_DATA_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH0.Reg) +} + +// AHB_DMA.TX_CRC_WIDTH_CH0: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AHB_DMA.OUT_CRC_CLEAR_CH0: This register is used to clear ch0 crc result +func (o *AHB_DMA_Type) SetOUT_CRC_CLEAR_CH0_OUT_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH0.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_CRC_CLEAR_CH0_OUT_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH0.Reg) & 0x1 +} + +// AHB_DMA.OUT_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result +func (o *AHB_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH0.Reg) +} + +// AHB_DMA.TX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit +func (o *AHB_DMA_Type) SetTX_CRC_EN_WR_DATA_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetTX_CRC_EN_WR_DATA_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH0.Reg) +} + +// AHB_DMA.TX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr +func (o *AHB_DMA_Type) SetTX_CRC_EN_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetTX_CRC_EN_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH0.Reg) +} + +// AHB_DMA.TX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en +func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH0_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg)&^(0xff)|value) +} +func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH0_TX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg) & 0xff +} + +// AHB_DMA.TX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en +func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH0.Reg) +} + +// AHB_DMA.TX_CH_ARB_WEIGH_CH0: This register is used to config ch0 arbiter weigh +func (o *AHB_DMA_Type) SetTX_CH_ARB_WEIGH_CH0_TX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.TX_CH_ARB_WEIGH_CH0.Reg, volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH0.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetTX_CH_ARB_WEIGH_CH0_TX_CH_ARB_WEIGH_CH() uint32 { + return volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH0.Reg) & 0xf +} + +// AHB_DMA.TX_ARB_WEIGH_OPT_DIR_CH0: This register is used to config off or on weigh optimization +func (o *AHB_DMA_Type) SetTX_ARB_WEIGH_OPT_DIR_CH0_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH0.Reg, volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetTX_ARB_WEIGH_OPT_DIR_CH0_TX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH0.Reg) & 0x1 +} + +// AHB_DMA.OUT_CRC_INIT_DATA_CH1: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AHB_DMA_Type) SetOUT_CRC_INIT_DATA_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_CRC_INIT_DATA_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH1.Reg) +} + +// AHB_DMA.TX_CRC_WIDTH_CH1: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AHB_DMA.OUT_CRC_CLEAR_CH1: This register is used to clear ch0 crc result +func (o *AHB_DMA_Type) SetOUT_CRC_CLEAR_CH1_OUT_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH1.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_CRC_CLEAR_CH1_OUT_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH1.Reg) & 0x1 +} + +// AHB_DMA.OUT_CRC_FINAL_RESULT_CH1: This register is used to store ch0 crc result +func (o *AHB_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH1.Reg) +} + +// AHB_DMA.TX_CRC_EN_WR_DATA_CH1: This resister is used to config ch0 crc en for every bit +func (o *AHB_DMA_Type) SetTX_CRC_EN_WR_DATA_CH1(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetTX_CRC_EN_WR_DATA_CH1() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH1.Reg) +} + +// AHB_DMA.TX_CRC_EN_ADDR_CH1: This register is used to config ch0 crc en addr +func (o *AHB_DMA_Type) SetTX_CRC_EN_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetTX_CRC_EN_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH1.Reg) +} + +// AHB_DMA.TX_CRC_DATA_EN_WR_DATA_CH1: This register is used to config crc data_8bit en +func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH1_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg)&^(0xff)|value) +} +func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH1_TX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg) & 0xff +} + +// AHB_DMA.TX_CRC_DATA_EN_ADDR_CH1: This register is used to config addr of crc data_8bit en +func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH1.Reg) +} + +// AHB_DMA.TX_CH_ARB_WEIGH_CH1: This register is used to config ch0 arbiter weigh +func (o *AHB_DMA_Type) SetTX_CH_ARB_WEIGH_CH1_TX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.TX_CH_ARB_WEIGH_CH1.Reg, volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH1.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetTX_CH_ARB_WEIGH_CH1_TX_CH_ARB_WEIGH_CH() uint32 { + return volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH1.Reg) & 0xf +} + +// AHB_DMA.TX_ARB_WEIGH_OPT_DIR_CH1: This register is used to config off or on weigh optimization +func (o *AHB_DMA_Type) SetTX_ARB_WEIGH_OPT_DIR_CH1_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH1.Reg, volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetTX_ARB_WEIGH_OPT_DIR_CH1_TX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH1.Reg) & 0x1 +} + +// AHB_DMA.OUT_CRC_INIT_DATA_CH2: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AHB_DMA_Type) SetOUT_CRC_INIT_DATA_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_CRC_INIT_DATA_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH2.Reg) +} + +// AHB_DMA.TX_CRC_WIDTH_CH2: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AHB_DMA.OUT_CRC_CLEAR_CH2: This register is used to clear ch0 crc result +func (o *AHB_DMA_Type) SetOUT_CRC_CLEAR_CH2_OUT_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH2.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetOUT_CRC_CLEAR_CH2_OUT_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH2.Reg) & 0x1 +} + +// AHB_DMA.OUT_CRC_FINAL_RESULT_CH2: This register is used to store ch0 crc result +func (o *AHB_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH2.Reg) +} + +// AHB_DMA.TX_CRC_EN_WR_DATA_CH2: This resister is used to config ch0 crc en for every bit +func (o *AHB_DMA_Type) SetTX_CRC_EN_WR_DATA_CH2(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetTX_CRC_EN_WR_DATA_CH2() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH2.Reg) +} + +// AHB_DMA.TX_CRC_EN_ADDR_CH2: This register is used to config ch0 crc en addr +func (o *AHB_DMA_Type) SetTX_CRC_EN_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetTX_CRC_EN_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH2.Reg) +} + +// AHB_DMA.TX_CRC_DATA_EN_WR_DATA_CH2: This register is used to config crc data_8bit en +func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH2_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg)&^(0xff)|value) +} +func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH2_TX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg) & 0xff +} + +// AHB_DMA.TX_CRC_DATA_EN_ADDR_CH2: This register is used to config addr of crc data_8bit en +func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH2.Reg) +} + +// AHB_DMA.TX_CH_ARB_WEIGH_CH2: This register is used to config ch0 arbiter weigh +func (o *AHB_DMA_Type) SetTX_CH_ARB_WEIGH_CH2_TX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.TX_CH_ARB_WEIGH_CH2.Reg, volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH2.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetTX_CH_ARB_WEIGH_CH2_TX_CH_ARB_WEIGH_CH() uint32 { + return volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH2.Reg) & 0xf +} + +// AHB_DMA.TX_ARB_WEIGH_OPT_DIR_CH2: This register is used to config off or on weigh optimization +func (o *AHB_DMA_Type) SetTX_ARB_WEIGH_OPT_DIR_CH2_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH2.Reg, volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetTX_ARB_WEIGH_OPT_DIR_CH2_TX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH2.Reg) & 0x1 +} + +// AHB_DMA.IN_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AHB_DMA_Type) SetIN_CRC_INIT_DATA_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_CRC_INIT_DATA_CH0() uint32 { + return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH0.Reg) +} + +// AHB_DMA.RX_CRC_WIDTH_CH0: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AHB_DMA.IN_CRC_CLEAR_CH0: This register is used to clear ch0 crc result +func (o *AHB_DMA_Type) SetIN_CRC_CLEAR_CH0_IN_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.IN_CRC_CLEAR_CH0.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_CRC_CLEAR_CH0_IN_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH0.Reg) & 0x1 +} + +// AHB_DMA.IN_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result +func (o *AHB_DMA_Type) SetIN_CRC_FINAL_RESULT_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_CRC_FINAL_RESULT_CH0() uint32 { + return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH0.Reg) +} + +// AHB_DMA.RX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit +func (o *AHB_DMA_Type) SetRX_CRC_EN_WR_DATA_CH0(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetRX_CRC_EN_WR_DATA_CH0() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH0.Reg) +} + +// AHB_DMA.RX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr +func (o *AHB_DMA_Type) SetRX_CRC_EN_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetRX_CRC_EN_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH0.Reg) +} + +// AHB_DMA.RX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en +func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH0_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg)&^(0xff)|value) +} +func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH0_RX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg) & 0xff +} + +// AHB_DMA.RX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en +func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH0.Reg) +} + +// AHB_DMA.RX_CH_ARB_WEIGH_CH0: This register is used to config ch0 arbiter weigh +func (o *AHB_DMA_Type) SetRX_CH_ARB_WEIGH_CH0_RX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.RX_CH_ARB_WEIGH_CH0.Reg, volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH0.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetRX_CH_ARB_WEIGH_CH0_RX_CH_ARB_WEIGH_CH() uint32 { + return volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH0.Reg) & 0xf +} + +// AHB_DMA.RX_ARB_WEIGH_OPT_DIR_CH0: This register is used to config off or on weigh optimization +func (o *AHB_DMA_Type) SetRX_ARB_WEIGH_OPT_DIR_CH0_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH0.Reg, volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH0.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetRX_ARB_WEIGH_OPT_DIR_CH0_RX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH0.Reg) & 0x1 +} + +// AHB_DMA.IN_CRC_INIT_DATA_CH1: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AHB_DMA_Type) SetIN_CRC_INIT_DATA_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_CRC_INIT_DATA_CH1() uint32 { + return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH1.Reg) +} + +// AHB_DMA.RX_CRC_WIDTH_CH1: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AHB_DMA.IN_CRC_CLEAR_CH1: This register is used to clear ch0 crc result +func (o *AHB_DMA_Type) SetIN_CRC_CLEAR_CH1_IN_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.IN_CRC_CLEAR_CH1.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_CRC_CLEAR_CH1_IN_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH1.Reg) & 0x1 +} + +// AHB_DMA.IN_CRC_FINAL_RESULT_CH1: This register is used to store ch0 crc result +func (o *AHB_DMA_Type) SetIN_CRC_FINAL_RESULT_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_CRC_FINAL_RESULT_CH1() uint32 { + return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH1.Reg) +} + +// AHB_DMA.RX_CRC_EN_WR_DATA_CH1: This resister is used to config ch0 crc en for every bit +func (o *AHB_DMA_Type) SetRX_CRC_EN_WR_DATA_CH1(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetRX_CRC_EN_WR_DATA_CH1() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH1.Reg) +} + +// AHB_DMA.RX_CRC_EN_ADDR_CH1: This register is used to config ch0 crc en addr +func (o *AHB_DMA_Type) SetRX_CRC_EN_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetRX_CRC_EN_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH1.Reg) +} + +// AHB_DMA.RX_CRC_DATA_EN_WR_DATA_CH1: This register is used to config crc data_8bit en +func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH1_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg)&^(0xff)|value) +} +func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH1_RX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg) & 0xff +} + +// AHB_DMA.RX_CRC_DATA_EN_ADDR_CH1: This register is used to config addr of crc data_8bit en +func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH1.Reg) +} + +// AHB_DMA.RX_CH_ARB_WEIGH_CH1: This register is used to config ch0 arbiter weigh +func (o *AHB_DMA_Type) SetRX_CH_ARB_WEIGH_CH1_RX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.RX_CH_ARB_WEIGH_CH1.Reg, volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH1.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetRX_CH_ARB_WEIGH_CH1_RX_CH_ARB_WEIGH_CH() uint32 { + return volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH1.Reg) & 0xf +} + +// AHB_DMA.RX_ARB_WEIGH_OPT_DIR_CH1: This register is used to config off or on weigh optimization +func (o *AHB_DMA_Type) SetRX_ARB_WEIGH_OPT_DIR_CH1_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH1.Reg, volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH1.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetRX_ARB_WEIGH_OPT_DIR_CH1_RX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH1.Reg) & 0x1 +} + +// AHB_DMA.IN_CRC_INIT_DATA_CH2: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AHB_DMA_Type) SetIN_CRC_INIT_DATA_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_CRC_INIT_DATA_CH2() uint32 { + return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH2.Reg) +} + +// AHB_DMA.RX_CRC_WIDTH_CH2: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AHB_DMA.IN_CRC_CLEAR_CH2: This register is used to clear ch0 crc result +func (o *AHB_DMA_Type) SetIN_CRC_CLEAR_CH2_IN_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.IN_CRC_CLEAR_CH2.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetIN_CRC_CLEAR_CH2_IN_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH2.Reg) & 0x1 +} + +// AHB_DMA.IN_CRC_FINAL_RESULT_CH2: This register is used to store ch0 crc result +func (o *AHB_DMA_Type) SetIN_CRC_FINAL_RESULT_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_CRC_FINAL_RESULT_CH2() uint32 { + return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH2.Reg) +} + +// AHB_DMA.RX_CRC_EN_WR_DATA_CH2: This resister is used to config ch0 crc en for every bit +func (o *AHB_DMA_Type) SetRX_CRC_EN_WR_DATA_CH2(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetRX_CRC_EN_WR_DATA_CH2() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH2.Reg) +} + +// AHB_DMA.RX_CRC_EN_ADDR_CH2: This register is used to config ch0 crc en addr +func (o *AHB_DMA_Type) SetRX_CRC_EN_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetRX_CRC_EN_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH2.Reg) +} + +// AHB_DMA.RX_CRC_DATA_EN_WR_DATA_CH2: This register is used to config crc data_8bit en +func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH2_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg)&^(0xff)|value) +} +func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH2_RX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg) & 0xff +} + +// AHB_DMA.RX_CRC_DATA_EN_ADDR_CH2: This register is used to config addr of crc data_8bit en +func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH2.Reg) +} + +// AHB_DMA.RX_CH_ARB_WEIGH_CH2: This register is used to config ch0 arbiter weigh +func (o *AHB_DMA_Type) SetRX_CH_ARB_WEIGH_CH2_RX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.RX_CH_ARB_WEIGH_CH2.Reg, volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH2.Reg)&^(0xf)|value) +} +func (o *AHB_DMA_Type) GetRX_CH_ARB_WEIGH_CH2_RX_CH_ARB_WEIGH_CH() uint32 { + return volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH2.Reg) & 0xf +} + +// AHB_DMA.RX_ARB_WEIGH_OPT_DIR_CH2: This register is used to config off or on weigh optimization +func (o *AHB_DMA_Type) SetRX_ARB_WEIGH_OPT_DIR_CH2_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH2.Reg, volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH2.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetRX_ARB_WEIGH_OPT_DIR_CH2_RX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH2.Reg) & 0x1 +} + +// AHB_DMA.IN_LINK_ADDR_CH0: Link descriptor configure of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_LINK_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_LINK_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_LINK_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_LINK_ADDR_CH0.Reg) +} + +// AHB_DMA.IN_LINK_ADDR_CH1: Link descriptor configure of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_LINK_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_LINK_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_LINK_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_LINK_ADDR_CH1.Reg) +} + +// AHB_DMA.IN_LINK_ADDR_CH2: Link descriptor configure of Rx channel 0 +func (o *AHB_DMA_Type) SetIN_LINK_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_LINK_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetIN_LINK_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_LINK_ADDR_CH2.Reg) +} + +// AHB_DMA.OUT_LINK_ADDR_CH0: Link descriptor configure of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_LINK_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_ADDR_CH0.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_LINK_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH0.Reg) +} + +// AHB_DMA.OUT_LINK_ADDR_CH1: Link descriptor configure of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_LINK_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_ADDR_CH1.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_LINK_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH1.Reg) +} + +// AHB_DMA.OUT_LINK_ADDR_CH2: Link descriptor configure of Tx channel 0 +func (o *AHB_DMA_Type) SetOUT_LINK_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_ADDR_CH2.Reg, value) +} +func (o *AHB_DMA_Type) GetOUT_LINK_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH2.Reg) +} + +// AHB_DMA.INTR_MEM_START_ADDR: The start address of accessible address space. +func (o *AHB_DMA_Type) SetINTR_MEM_START_ADDR(value uint32) { + volatile.StoreUint32(&o.INTR_MEM_START_ADDR.Reg, value) +} +func (o *AHB_DMA_Type) GetINTR_MEM_START_ADDR() uint32 { + return volatile.LoadUint32(&o.INTR_MEM_START_ADDR.Reg) +} + +// AHB_DMA.INTR_MEM_END_ADDR: The end address of accessible address space. The access address beyond this range would lead to descriptor error. +func (o *AHB_DMA_Type) SetINTR_MEM_END_ADDR(value uint32) { + volatile.StoreUint32(&o.INTR_MEM_END_ADDR.Reg, value) +} +func (o *AHB_DMA_Type) GetINTR_MEM_END_ADDR() uint32 { + return volatile.LoadUint32(&o.INTR_MEM_END_ADDR.Reg) +} + +// AHB_DMA.ARB_TIMEOUT_TX: This retister is used to config arbiter time slice for tx dir +func (o *AHB_DMA_Type) SetARB_TIMEOUT_TX(value uint32) { + volatile.StoreUint32(&o.ARB_TIMEOUT_TX.Reg, volatile.LoadUint32(&o.ARB_TIMEOUT_TX.Reg)&^(0xffff)|value) +} +func (o *AHB_DMA_Type) GetARB_TIMEOUT_TX() uint32 { + return volatile.LoadUint32(&o.ARB_TIMEOUT_TX.Reg) & 0xffff +} + +// AHB_DMA.ARB_TIMEOUT_RX: This retister is used to config arbiter time slice for rx dir +func (o *AHB_DMA_Type) SetARB_TIMEOUT_RX(value uint32) { + volatile.StoreUint32(&o.ARB_TIMEOUT_RX.Reg, volatile.LoadUint32(&o.ARB_TIMEOUT_RX.Reg)&^(0xffff)|value) +} +func (o *AHB_DMA_Type) GetARB_TIMEOUT_RX() uint32 { + return volatile.LoadUint32(&o.ARB_TIMEOUT_RX.Reg) & 0xffff +} + +// AHB_DMA.WEIGHT_EN_TX: This register is used to config arbiter weigh function to on or off for tx dir +func (o *AHB_DMA_Type) SetWEIGHT_EN_TX(value uint32) { + volatile.StoreUint32(&o.WEIGHT_EN_TX.Reg, volatile.LoadUint32(&o.WEIGHT_EN_TX.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetWEIGHT_EN_TX() uint32 { + return volatile.LoadUint32(&o.WEIGHT_EN_TX.Reg) & 0x1 +} + +// AHB_DMA.WEIGHT_EN_RX: This register is used to config arbiter weigh function to on or off for rx dir +func (o *AHB_DMA_Type) SetWEIGHT_EN_RX(value uint32) { + volatile.StoreUint32(&o.WEIGHT_EN_RX.Reg, volatile.LoadUint32(&o.WEIGHT_EN_RX.Reg)&^(0x1)|value) +} +func (o *AHB_DMA_Type) GetWEIGHT_EN_RX() uint32 { + return volatile.LoadUint32(&o.WEIGHT_EN_RX.Reg) & 0x1 +} + +// LP_I2C_ANA_MST Peripheral +type ANA_I2C_MST_Type struct { + I2C0_CTRL volatile.Register32 // 0x0 + I2C1_CTRL volatile.Register32 // 0x4 + I2C0_CONF volatile.Register32 // 0x8 + I2C1_CONF volatile.Register32 // 0xC + I2C_BURST_CONF volatile.Register32 // 0x10 + I2C_BURST_STATUS volatile.Register32 // 0x14 + ANA_CONF0 volatile.Register32 // 0x18 + ANA_CONF1 volatile.Register32 // 0x1C + ANA_CONF2 volatile.Register32 // 0x20 + I2C0_CTRL1 volatile.Register32 // 0x24 + I2C1_CTRL1 volatile.Register32 // 0x28 + HW_I2C_CTRL volatile.Register32 // 0x2C + NOUSE volatile.Register32 // 0x30 + CLK160M volatile.Register32 // 0x34 + DATE volatile.Register32 // 0x38 +} + +// ANA_I2C_MST.I2C0_CTRL: need des +func (o *ANA_I2C_MST_Type) SetI2C0_CTRL(value uint32) { + volatile.StoreUint32(&o.I2C0_CTRL.Reg, volatile.LoadUint32(&o.I2C0_CTRL.Reg)&^(0x1ffffff)|value) +} +func (o *ANA_I2C_MST_Type) GetI2C0_CTRL() uint32 { + return volatile.LoadUint32(&o.I2C0_CTRL.Reg) & 0x1ffffff +} +func (o *ANA_I2C_MST_Type) SetI2C0_CTRL_I2C0_BUSY(value uint32) { + volatile.StoreUint32(&o.I2C0_CTRL.Reg, volatile.LoadUint32(&o.I2C0_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *ANA_I2C_MST_Type) GetI2C0_CTRL_I2C0_BUSY() uint32 { + return (volatile.LoadUint32(&o.I2C0_CTRL.Reg) & 0x2000000) >> 25 +} + +// ANA_I2C_MST.I2C1_CTRL: need des +func (o *ANA_I2C_MST_Type) SetI2C1_CTRL(value uint32) { + volatile.StoreUint32(&o.I2C1_CTRL.Reg, volatile.LoadUint32(&o.I2C1_CTRL.Reg)&^(0x1ffffff)|value) +} +func (o *ANA_I2C_MST_Type) GetI2C1_CTRL() uint32 { + return volatile.LoadUint32(&o.I2C1_CTRL.Reg) & 0x1ffffff +} +func (o *ANA_I2C_MST_Type) SetI2C1_CTRL_I2C1_BUSY(value uint32) { + volatile.StoreUint32(&o.I2C1_CTRL.Reg, volatile.LoadUint32(&o.I2C1_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *ANA_I2C_MST_Type) GetI2C1_CTRL_I2C1_BUSY() uint32 { + return (volatile.LoadUint32(&o.I2C1_CTRL.Reg) & 0x2000000) >> 25 +} + +// ANA_I2C_MST.I2C0_CONF: need des +func (o *ANA_I2C_MST_Type) SetI2C0_CONF(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0xffffff)|value) +} +func (o *ANA_I2C_MST_Type) GetI2C0_CONF() uint32 { + return volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0xffffff +} +func (o *ANA_I2C_MST_Type) SetI2C0_CONF_I2C0_STATUS(value uint32) { + volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *ANA_I2C_MST_Type) GetI2C0_CONF_I2C0_STATUS() uint32 { + return (volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0xff000000) >> 24 +} + +// ANA_I2C_MST.I2C1_CONF: need des +func (o *ANA_I2C_MST_Type) SetI2C1_CONF(value uint32) { + volatile.StoreUint32(&o.I2C1_CONF.Reg, volatile.LoadUint32(&o.I2C1_CONF.Reg)&^(0xffffff)|value) +} +func (o *ANA_I2C_MST_Type) GetI2C1_CONF() uint32 { + return volatile.LoadUint32(&o.I2C1_CONF.Reg) & 0xffffff +} +func (o *ANA_I2C_MST_Type) SetI2C1_CONF_I2C1_STATUS(value uint32) { + volatile.StoreUint32(&o.I2C1_CONF.Reg, volatile.LoadUint32(&o.I2C1_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *ANA_I2C_MST_Type) GetI2C1_CONF_I2C1_STATUS() uint32 { + return (volatile.LoadUint32(&o.I2C1_CONF.Reg) & 0xff000000) >> 24 +} + +// ANA_I2C_MST.I2C_BURST_CONF: need des +func (o *ANA_I2C_MST_Type) SetI2C_BURST_CONF(value uint32) { + volatile.StoreUint32(&o.I2C_BURST_CONF.Reg, value) +} +func (o *ANA_I2C_MST_Type) GetI2C_BURST_CONF() uint32 { + return volatile.LoadUint32(&o.I2C_BURST_CONF.Reg) +} + +// ANA_I2C_MST.I2C_BURST_STATUS: need des +func (o *ANA_I2C_MST_Type) SetI2C_BURST_STATUS_I2C_MST_BURST_DONE(value uint32) { + volatile.StoreUint32(&o.I2C_BURST_STATUS.Reg, volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg)&^(0x1)|value) +} +func (o *ANA_I2C_MST_Type) GetI2C_BURST_STATUS_I2C_MST_BURST_DONE() uint32 { + return volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg) & 0x1 +} +func (o *ANA_I2C_MST_Type) SetI2C_BURST_STATUS_I2C_MST0_BURST_ERR_FLAG(value uint32) { + volatile.StoreUint32(&o.I2C_BURST_STATUS.Reg, volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *ANA_I2C_MST_Type) GetI2C_BURST_STATUS_I2C_MST0_BURST_ERR_FLAG() uint32 { + return (volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg) & 0x2) >> 1 +} +func (o *ANA_I2C_MST_Type) SetI2C_BURST_STATUS_I2C_MST1_BURST_ERR_FLAG(value uint32) { + volatile.StoreUint32(&o.I2C_BURST_STATUS.Reg, volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *ANA_I2C_MST_Type) GetI2C_BURST_STATUS_I2C_MST1_BURST_ERR_FLAG() uint32 { + return (volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg) & 0x4) >> 2 +} +func (o *ANA_I2C_MST_Type) SetI2C_BURST_STATUS_I2C_MST_BURST_TIMEOUT_CNT(value uint32) { + volatile.StoreUint32(&o.I2C_BURST_STATUS.Reg, volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg)&^(0xfff00000)|value<<20) +} +func (o *ANA_I2C_MST_Type) GetI2C_BURST_STATUS_I2C_MST_BURST_TIMEOUT_CNT() uint32 { + return (volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg) & 0xfff00000) >> 20 +} + +// ANA_I2C_MST.ANA_CONF0: need des +func (o *ANA_I2C_MST_Type) SetANA_CONF0(value uint32) { + volatile.StoreUint32(&o.ANA_CONF0.Reg, volatile.LoadUint32(&o.ANA_CONF0.Reg)&^(0xffffff)|value) +} +func (o *ANA_I2C_MST_Type) GetANA_CONF0() uint32 { + return volatile.LoadUint32(&o.ANA_CONF0.Reg) & 0xffffff +} +func (o *ANA_I2C_MST_Type) SetANA_CONF0_ANA_STATUS0(value uint32) { + volatile.StoreUint32(&o.ANA_CONF0.Reg, volatile.LoadUint32(&o.ANA_CONF0.Reg)&^(0xff000000)|value<<24) +} +func (o *ANA_I2C_MST_Type) GetANA_CONF0_ANA_STATUS0() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF0.Reg) & 0xff000000) >> 24 +} + +// ANA_I2C_MST.ANA_CONF1: need des +func (o *ANA_I2C_MST_Type) SetANA_CONF1(value uint32) { + volatile.StoreUint32(&o.ANA_CONF1.Reg, volatile.LoadUint32(&o.ANA_CONF1.Reg)&^(0xffffff)|value) +} +func (o *ANA_I2C_MST_Type) GetANA_CONF1() uint32 { + return volatile.LoadUint32(&o.ANA_CONF1.Reg) & 0xffffff +} +func (o *ANA_I2C_MST_Type) SetANA_CONF1_ANA_STATUS1(value uint32) { + volatile.StoreUint32(&o.ANA_CONF1.Reg, volatile.LoadUint32(&o.ANA_CONF1.Reg)&^(0xff000000)|value<<24) +} +func (o *ANA_I2C_MST_Type) GetANA_CONF1_ANA_STATUS1() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF1.Reg) & 0xff000000) >> 24 +} + +// ANA_I2C_MST.ANA_CONF2: need des +func (o *ANA_I2C_MST_Type) SetANA_CONF2(value uint32) { + volatile.StoreUint32(&o.ANA_CONF2.Reg, volatile.LoadUint32(&o.ANA_CONF2.Reg)&^(0xffffff)|value) +} +func (o *ANA_I2C_MST_Type) GetANA_CONF2() uint32 { + return volatile.LoadUint32(&o.ANA_CONF2.Reg) & 0xffffff +} +func (o *ANA_I2C_MST_Type) SetANA_CONF2_ANA_STATUS2(value uint32) { + volatile.StoreUint32(&o.ANA_CONF2.Reg, volatile.LoadUint32(&o.ANA_CONF2.Reg)&^(0xff000000)|value<<24) +} +func (o *ANA_I2C_MST_Type) GetANA_CONF2_ANA_STATUS2() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF2.Reg) & 0xff000000) >> 24 +} + +// ANA_I2C_MST.I2C0_CTRL1: need des +func (o *ANA_I2C_MST_Type) SetI2C0_CTRL1_I2C0_SCL_PULSE_DUR(value uint32) { + volatile.StoreUint32(&o.I2C0_CTRL1.Reg, volatile.LoadUint32(&o.I2C0_CTRL1.Reg)&^(0x3f)|value) +} +func (o *ANA_I2C_MST_Type) GetI2C0_CTRL1_I2C0_SCL_PULSE_DUR() uint32 { + return volatile.LoadUint32(&o.I2C0_CTRL1.Reg) & 0x3f +} +func (o *ANA_I2C_MST_Type) SetI2C0_CTRL1_I2C0_SDA_SIDE_GUARD(value uint32) { + volatile.StoreUint32(&o.I2C0_CTRL1.Reg, volatile.LoadUint32(&o.I2C0_CTRL1.Reg)&^(0x7c0)|value<<6) +} +func (o *ANA_I2C_MST_Type) GetI2C0_CTRL1_I2C0_SDA_SIDE_GUARD() uint32 { + return (volatile.LoadUint32(&o.I2C0_CTRL1.Reg) & 0x7c0) >> 6 +} + +// ANA_I2C_MST.I2C1_CTRL1: need des +func (o *ANA_I2C_MST_Type) SetI2C1_CTRL1_I2C1_SCL_PULSE_DUR(value uint32) { + volatile.StoreUint32(&o.I2C1_CTRL1.Reg, volatile.LoadUint32(&o.I2C1_CTRL1.Reg)&^(0x3f)|value) +} +func (o *ANA_I2C_MST_Type) GetI2C1_CTRL1_I2C1_SCL_PULSE_DUR() uint32 { + return volatile.LoadUint32(&o.I2C1_CTRL1.Reg) & 0x3f +} +func (o *ANA_I2C_MST_Type) SetI2C1_CTRL1_I2C1_SDA_SIDE_GUARD(value uint32) { + volatile.StoreUint32(&o.I2C1_CTRL1.Reg, volatile.LoadUint32(&o.I2C1_CTRL1.Reg)&^(0x7c0)|value<<6) +} +func (o *ANA_I2C_MST_Type) GetI2C1_CTRL1_I2C1_SDA_SIDE_GUARD() uint32 { + return (volatile.LoadUint32(&o.I2C1_CTRL1.Reg) & 0x7c0) >> 6 +} + +// ANA_I2C_MST.HW_I2C_CTRL: need des +func (o *ANA_I2C_MST_Type) SetHW_I2C_CTRL_HW_I2C_SCL_PULSE_DUR(value uint32) { + volatile.StoreUint32(&o.HW_I2C_CTRL.Reg, volatile.LoadUint32(&o.HW_I2C_CTRL.Reg)&^(0x3f)|value) +} +func (o *ANA_I2C_MST_Type) GetHW_I2C_CTRL_HW_I2C_SCL_PULSE_DUR() uint32 { + return volatile.LoadUint32(&o.HW_I2C_CTRL.Reg) & 0x3f +} +func (o *ANA_I2C_MST_Type) SetHW_I2C_CTRL_HW_I2C_SDA_SIDE_GUARD(value uint32) { + volatile.StoreUint32(&o.HW_I2C_CTRL.Reg, volatile.LoadUint32(&o.HW_I2C_CTRL.Reg)&^(0x7c0)|value<<6) +} +func (o *ANA_I2C_MST_Type) GetHW_I2C_CTRL_HW_I2C_SDA_SIDE_GUARD() uint32 { + return (volatile.LoadUint32(&o.HW_I2C_CTRL.Reg) & 0x7c0) >> 6 +} +func (o *ANA_I2C_MST_Type) SetHW_I2C_CTRL_ARBITER_DIS(value uint32) { + volatile.StoreUint32(&o.HW_I2C_CTRL.Reg, volatile.LoadUint32(&o.HW_I2C_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *ANA_I2C_MST_Type) GetHW_I2C_CTRL_ARBITER_DIS() uint32 { + return (volatile.LoadUint32(&o.HW_I2C_CTRL.Reg) & 0x800) >> 11 +} + +// ANA_I2C_MST.NOUSE: need des +func (o *ANA_I2C_MST_Type) SetNOUSE(value uint32) { + volatile.StoreUint32(&o.NOUSE.Reg, value) +} +func (o *ANA_I2C_MST_Type) GetNOUSE() uint32 { + return volatile.LoadUint32(&o.NOUSE.Reg) +} + +// ANA_I2C_MST.CLK160M: need des +func (o *ANA_I2C_MST_Type) SetCLK160M_CLK_I2C_MST_SEL_160M(value uint32) { + volatile.StoreUint32(&o.CLK160M.Reg, volatile.LoadUint32(&o.CLK160M.Reg)&^(0x1)|value) +} +func (o *ANA_I2C_MST_Type) GetCLK160M_CLK_I2C_MST_SEL_160M() uint32 { + return volatile.LoadUint32(&o.CLK160M.Reg) & 0x1 +} + +// ANA_I2C_MST.DATE: need des +func (o *ANA_I2C_MST_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *ANA_I2C_MST_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} +func (o *ANA_I2C_MST_Type) SetDATE_I2C_MST_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x10000000)|value<<28) +} +func (o *ANA_I2C_MST_Type) GetDATE_I2C_MST_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x10000000) >> 28 +} + +// Debug Assist +type ASSIST_DEBUG_Type struct { + CORE_0_INTR_ENA volatile.Register32 // 0x0 + CORE_0_INTR_RAW volatile.Register32 // 0x4 + CORE_0_INTR_RLS volatile.Register32 // 0x8 + CORE_0_INTR_CLR volatile.Register32 // 0xC + CORE_0_AREA_DRAM0_0_MIN volatile.Register32 // 0x10 + CORE_0_AREA_DRAM0_0_MAX volatile.Register32 // 0x14 + CORE_0_AREA_DRAM0_1_MIN volatile.Register32 // 0x18 + CORE_0_AREA_DRAM0_1_MAX volatile.Register32 // 0x1C + CORE_0_AREA_PIF_0_MIN volatile.Register32 // 0x20 + CORE_0_AREA_PIF_0_MAX volatile.Register32 // 0x24 + CORE_0_AREA_PIF_1_MIN volatile.Register32 // 0x28 + CORE_0_AREA_PIF_1_MAX volatile.Register32 // 0x2C + CORE_0_AREA_PC volatile.Register32 // 0x30 + CORE_0_AREA_SP volatile.Register32 // 0x34 + CORE_0_SP_MIN volatile.Register32 // 0x38 + CORE_0_SP_MAX volatile.Register32 // 0x3C + CORE_0_SP_PC volatile.Register32 // 0x40 + CORE_0_RCD_EN volatile.Register32 // 0x44 + CORE_0_RCD_PDEBUGPC volatile.Register32 // 0x48 + CORE_0_RCD_PDEBUGSP volatile.Register32 // 0x4C + CORE_0_IRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x50 + CORE_0_IRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x54 + CORE_0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x58 + CORE_0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x5C + CORE_0_DRAM0_EXCEPTION_MONITOR_2 volatile.Register32 // 0x60 + CORE_0_DRAM0_EXCEPTION_MONITOR_3 volatile.Register32 // 0x64 + CORE_0_DRAM0_EXCEPTION_MONITOR_4 volatile.Register32 // 0x68 + CORE_0_DRAM0_EXCEPTION_MONITOR_5 volatile.Register32 // 0x6C + CORE_0_LASTPC_BEFORE_EXCEPTION volatile.Register32 // 0x70 + CORE_0_DEBUG_MODE volatile.Register32 // 0x74 + _ [8]byte + CORE_1_INTR_ENA volatile.Register32 // 0x80 + CORE_1_INTR_RAW volatile.Register32 // 0x84 + CORE_1_INTR_RLS volatile.Register32 // 0x88 + CORE_1_INTR_CLR volatile.Register32 // 0x8C + CORE_1_AREA_DRAM0_0_MIN volatile.Register32 // 0x90 + CORE_1_AREA_DRAM0_0_MAX volatile.Register32 // 0x94 + CORE_1_AREA_DRAM0_1_MIN volatile.Register32 // 0x98 + CORE_1_AREA_DRAM0_1_MAX volatile.Register32 // 0x9C + CORE_1_AREA_PIF_0_MIN volatile.Register32 // 0xA0 + CORE_1_AREA_PIF_0_MAX volatile.Register32 // 0xA4 + CORE_1_AREA_PIF_1_MIN volatile.Register32 // 0xA8 + CORE_1_AREA_PIF_1_MAX volatile.Register32 // 0xAC + CORE_1_AREA_PC volatile.Register32 // 0xB0 + CORE_1_AREA_SP volatile.Register32 // 0xB4 + CORE_1_SP_MIN volatile.Register32 // 0xB8 + CORE_1_SP_MAX volatile.Register32 // 0xBC + CORE_1_SP_PC volatile.Register32 // 0xC0 + CORE_1_RCD_EN volatile.Register32 // 0xC4 + CORE_1_RCD_PDEBUGPC volatile.Register32 // 0xC8 + CORE_1_RCD_PDEBUGSP volatile.Register32 // 0xCC + CORE_1_IRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0xD0 + CORE_1_IRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0xD4 + CORE_1_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0xD8 + CORE_1_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0xDC + CORE_1_DRAM0_EXCEPTION_MONITOR_2 volatile.Register32 // 0xE0 + CORE_1_DRAM0_EXCEPTION_MONITOR_3 volatile.Register32 // 0xE4 + CORE_1_DRAM0_EXCEPTION_MONITOR_4 volatile.Register32 // 0xE8 + CORE_1_DRAM0_EXCEPTION_MONITOR_5 volatile.Register32 // 0xEC + CORE_1_LASTPC_BEFORE_EXCEPTION volatile.Register32 // 0xF0 + CORE_1_DEBUG_MODE volatile.Register32 // 0xF4 + _ [8]byte + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x100 + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x104 + CLOCK_GATE volatile.Register32 // 0x108 + _ [752]byte + DATE volatile.Register32 // 0x3FC +} + +// ASSIST_DEBUG.CORE_0_INTR_ENA: core0 monitor enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_RAW: core0 monitor interrupt status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_RLS: core0 monitor interrupt enable register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_RD_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_RD_RLS() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_WR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_WR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_RD_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_RD_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_WR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_WR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_PIF_0_RD_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_PIF_0_RD_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_PIF_0_WR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_PIF_0_WR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_PIF_1_RD_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_PIF_1_RD_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_PIF_1_WR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_PIF_1_WR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_SP_SPILL_MIN_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_SP_SPILL_MIN_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_SP_SPILL_MAX_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_SP_SPILL_MAX_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_INTR_CLR: core0 monitor interrupt clr register +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MIN: core0 dram0 region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MAX: core0 dram0 region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MIN: core0 dram0 region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MAX: core0 dram0 region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MIN: core0 PIF region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MAX: core0 PIF region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MIN: core0 PIF region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MAX: core0 PIF region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_PC: core0 area pc status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PC.Reg) +} + +// ASSIST_DEBUG.CORE_0_AREA_SP: core0 area sp status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_SP(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_SP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_SP() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_SP.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_MIN: stack min value +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_MAX: stack max value +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_0_SP_PC: stack monitor pc status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_PC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_EN: record enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGPC: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGPC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGPC.Reg) +} + +// ASSIST_DEBUG.CORE_0_RCD_PDEBUGSP: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGSP(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGSP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGSP() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGSP.Reg) +} + +// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0 +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1 +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1fffe)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1fffe) >> 1 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_BYTEEN_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x1fffe)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_BYTEEN_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x1fffe) >> 1 +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_4: exception monitor status register6 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_4.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_4.Reg) & 0xffffff +} + +// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_5: exception monitor status register7 +func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_5(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_5.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_5() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_5.Reg) +} + +// ASSIST_DEBUG.CORE_0_LASTPC_BEFORE_EXCEPTION: cpu status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_LASTPC_BEFORE_EXCEPTION(value uint32) { + volatile.StoreUint32(&o.CORE_0_LASTPC_BEFORE_EXCEPTION.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_LASTPC_BEFORE_EXCEPTION() uint32 { + return volatile.LoadUint32(&o.CORE_0_LASTPC_BEFORE_EXCEPTION.Reg) +} + +// ASSIST_DEBUG.CORE_0_DEBUG_MODE: cpu status register +func (o *ASSIST_DEBUG_Type) SetCORE_0_DEBUG_MODE(value uint32) { + volatile.StoreUint32(&o.CORE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DEBUG_MODE() uint32 { + return volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CORE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_1_INTR_ENA: core1 monitor enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_1_INTR_RAW: core1 monitor interrupt status register +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW() uint32 { + return volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_1_INTR_RLS: core1 monitor interrupt enable register +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_RD_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_RD_RLS() uint32 { + return volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_WR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_WR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_RD_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_RD_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_WR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_WR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_PIF_0_RD_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_PIF_0_RD_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_PIF_0_WR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_PIF_0_WR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_PIF_1_RD_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_PIF_1_RD_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_PIF_1_WR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_PIF_1_WR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_SP_SPILL_MIN_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_SP_SPILL_MIN_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_SP_SPILL_MAX_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_SP_SPILL_MAX_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_1_INTR_CLR: core1 monitor interrupt clr register +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x2) >> 1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x4)|value<<2) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x4) >> 2 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x8)|value<<3) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x8) >> 3 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x10)|value<<4) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x10) >> 4 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x20)|value<<5) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x20) >> 5 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x40)|value<<6) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x40) >> 6 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x80)|value<<7) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x80) >> 7 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x100)|value<<8) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x100) >> 8 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x200)|value<<9) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x200) >> 9 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x400)|value<<10) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x400) >> 10 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x800)|value<<11) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x800) >> 11 +} + +// ASSIST_DEBUG.CORE_1_AREA_DRAM0_0_MIN: core1 dram0 region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_DRAM0_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_DRAM0_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_1_AREA_DRAM0_0_MAX: core1 dram0 region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_DRAM0_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_DRAM0_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_1_AREA_DRAM0_1_MIN: core1 dram0 region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_DRAM0_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_DRAM0_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_1_AREA_DRAM0_1_MAX: core1 dram0 region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_DRAM0_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_DRAM0_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_1_AREA_PIF_0_MIN: core1 PIF region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PIF_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PIF_0_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PIF_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PIF_0_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_1_AREA_PIF_0_MAX: core1 PIF region0 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PIF_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PIF_0_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PIF_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PIF_0_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_1_AREA_PIF_1_MIN: core1 PIF region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PIF_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PIF_1_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PIF_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PIF_1_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_1_AREA_PIF_1_MAX: core1 PIF region1 addr configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PIF_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PIF_1_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PIF_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PIF_1_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_1_AREA_PC: core1 area pc status register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PC(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PC() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PC.Reg) +} + +// ASSIST_DEBUG.CORE_1_AREA_SP: core1 area sp status register +func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_SP(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_SP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_SP() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_SP.Reg) +} + +// ASSIST_DEBUG.CORE_1_SP_MIN: stack min value +func (o *ASSIST_DEBUG_Type) SetCORE_1_SP_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_SP_MIN.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_SP_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_SP_MIN.Reg) +} + +// ASSIST_DEBUG.CORE_1_SP_MAX: stack max value +func (o *ASSIST_DEBUG_Type) SetCORE_1_SP_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_SP_MAX.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_SP_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_SP_MAX.Reg) +} + +// ASSIST_DEBUG.CORE_1_SP_PC: stack monitor pc status register +func (o *ASSIST_DEBUG_Type) SetCORE_1_SP_PC(value uint32) { + volatile.StoreUint32(&o.CORE_1_SP_PC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_SP_PC() uint32 { + return volatile.LoadUint32(&o.CORE_1_SP_PC.Reg) +} + +// ASSIST_DEBUG.CORE_1_RCD_EN: record enable configuration register +func (o *ASSIST_DEBUG_Type) SetCORE_1_RCD_EN_CORE_1_RCD_RECORDEN(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_1_RCD_EN.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_RCD_EN_CORE_1_RCD_RECORDEN() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_EN.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_RCD_EN_CORE_1_RCD_PDEBUGEN(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_1_RCD_EN.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_RCD_EN_CORE_1_RCD_PDEBUGEN() uint32 { + return (volatile.LoadUint32(&o.CORE_1_RCD_EN.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_1_RCD_PDEBUGPC: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_1_RCD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGPC.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_RCD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGPC.Reg) +} + +// ASSIST_DEBUG.CORE_1_RCD_PDEBUGSP: record status regsiter +func (o *ASSIST_DEBUG_Type) SetCORE_1_RCD_PDEBUGSP(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGSP.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_RCD_PDEBUGSP() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGSP.Reg) +} + +// ASSIST_DEBUG.CORE_1_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0 +func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_1_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1 +func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x1000000)|value<<24) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x1000000) >> 24 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x2000000)|value<<25) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x2000000) >> 25 +} + +// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2 +func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_BYTEEN_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1fffe)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_BYTEEN_0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1fffe) >> 1 +} + +// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3 +func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff +} + +// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4 +func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_2(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_2.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_2() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_2.Reg) +} + +// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5 +func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_BYTEEN_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x1fffe)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_BYTEEN_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x1fffe) >> 1 +} + +// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_4: exception monitor status register6 +func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_4.Reg)&^(0xffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_4.Reg) & 0xffffff +} + +// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_5: exception monitor status register7 +func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_5(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_5.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_5() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_5.Reg) +} + +// ASSIST_DEBUG.CORE_1_LASTPC_BEFORE_EXCEPTION: cpu status register +func (o *ASSIST_DEBUG_Type) SetCORE_1_LASTPC_BEFORE_EXCEPTION(value uint32) { + volatile.StoreUint32(&o.CORE_1_LASTPC_BEFORE_EXCEPTION.Reg, value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_LASTPC_BEFORE_EXCEPTION() uint32 { + return volatile.LoadUint32(&o.CORE_1_LASTPC_BEFORE_EXCEPTION.Reg) +} + +// ASSIST_DEBUG.CORE_1_DEBUG_MODE: cpu status register +func (o *ASSIST_DEBUG_Type) SetCORE_1_DEBUG_MODE(value uint32) { + volatile.StoreUint32(&o.CORE_1_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_1_DEBUG_MODE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DEBUG_MODE() uint32 { + return volatile.LoadUint32(&o.CORE_1_DEBUG_MODE.Reg) & 0x1 +} +func (o *ASSIST_DEBUG_Type) SetCORE_1_DEBUG_MODE_CORE_1_DEBUG_MODULE_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CORE_1_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_1_DEBUG_MODE.Reg)&^(0x2)|value<<1) +} +func (o *ASSIST_DEBUG_Type) GetCORE_1_DEBUG_MODE_CORE_1_DEBUG_MODULE_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DEBUG_MODE.Reg) & 0x2) >> 1 +} + +// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register6 +func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xfffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0xfffff +} + +// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register7 +func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xfffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xfffff +} + +// ASSIST_DEBUG.CLOCK_GATE: clock register +func (o *ASSIST_DEBUG_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *ASSIST_DEBUG_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// ASSIST_DEBUG.DATE: version register +func (o *ASSIST_DEBUG_Type) SetDATE_ASSIST_DEBUG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *ASSIST_DEBUG_Type) GetDATE_ASSIST_DEBUG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// AXI_DMA Peripheral +type AXI_DMA_Type struct { + IN_INT_RAW_CH0 volatile.Register32 // 0x0 + IN_INT_ST_CH0 volatile.Register32 // 0x4 + IN_INT_ENA_CH0 volatile.Register32 // 0x8 + IN_INT_CLR_CH0 volatile.Register32 // 0xC + IN_CONF0_CH0 volatile.Register32 // 0x10 + IN_CONF1_CH0 volatile.Register32 // 0x14 + INFIFO_STATUS_CH0 volatile.Register32 // 0x18 + IN_POP_CH0 volatile.Register32 // 0x1C + IN_LINK1_CH0 volatile.Register32 // 0x20 + IN_LINK2_CH0 volatile.Register32 // 0x24 + IN_STATE_CH0 volatile.Register32 // 0x28 + IN_SUC_EOF_DES_ADDR_CH0 volatile.Register32 // 0x2C + IN_ERR_EOF_DES_ADDR_CH0 volatile.Register32 // 0x30 + IN_DSCR_CH0 volatile.Register32 // 0x34 + IN_DSCR_BF0_CH0 volatile.Register32 // 0x38 + IN_DSCR_BF1_CH0 volatile.Register32 // 0x3C + IN_PRI_CH0 volatile.Register32 // 0x40 + IN_PERI_SEL_CH0 volatile.Register32 // 0x44 + IN_CRC_INIT_DATA_CH0 volatile.Register32 // 0x48 + RX_CRC_WIDTH_CH0 volatile.Register32 // 0x4C + IN_CRC_CLEAR_CH0 volatile.Register32 // 0x50 + IN_CRC_FINAL_RESULT_CH0 volatile.Register32 // 0x54 + RX_CRC_EN_WR_DATA_CH0 volatile.Register32 // 0x58 + RX_CRC_EN_ADDR_CH0 volatile.Register32 // 0x5C + RX_CRC_DATA_EN_WR_DATA_CH0 volatile.Register32 // 0x60 + RX_CRC_DATA_EN_ADDR_CH0 volatile.Register32 // 0x64 + IN_INT_RAW_CH1 volatile.Register32 // 0x68 + IN_INT_ST_CH1 volatile.Register32 // 0x6C + IN_INT_ENA_CH1 volatile.Register32 // 0x70 + IN_INT_CLR_CH1 volatile.Register32 // 0x74 + IN_CONF0_CH1 volatile.Register32 // 0x78 + IN_CONF1_CH1 volatile.Register32 // 0x7C + INFIFO_STATUS_CH1 volatile.Register32 // 0x80 + IN_POP_CH1 volatile.Register32 // 0x84 + IN_LINK1_CH1 volatile.Register32 // 0x88 + IN_LINK2_CH1 volatile.Register32 // 0x8C + IN_STATE_CH1 volatile.Register32 // 0x90 + IN_SUC_EOF_DES_ADDR_CH1 volatile.Register32 // 0x94 + IN_ERR_EOF_DES_ADDR_CH1 volatile.Register32 // 0x98 + IN_DSCR_CH1 volatile.Register32 // 0x9C + IN_DSCR_BF0_CH1 volatile.Register32 // 0xA0 + IN_DSCR_BF1_CH1 volatile.Register32 // 0xA4 + IN_PRI_CH1 volatile.Register32 // 0xA8 + IN_PERI_SEL_CH1 volatile.Register32 // 0xAC + IN_CRC_INIT_DATA_CH1 volatile.Register32 // 0xB0 + RX_CRC_WIDTH_CH1 volatile.Register32 // 0xB4 + IN_CRC_CLEAR_CH1 volatile.Register32 // 0xB8 + IN_CRC_FINAL_RESULT_CH1 volatile.Register32 // 0xBC + RX_CRC_EN_WR_DATA_CH1 volatile.Register32 // 0xC0 + RX_CRC_EN_ADDR_CH1 volatile.Register32 // 0xC4 + RX_CRC_DATA_EN_WR_DATA_CH1 volatile.Register32 // 0xC8 + RX_CRC_DATA_EN_ADDR_CH1 volatile.Register32 // 0xCC + IN_INT_RAW_CH2 volatile.Register32 // 0xD0 + IN_INT_ST_CH2 volatile.Register32 // 0xD4 + IN_INT_ENA_CH2 volatile.Register32 // 0xD8 + IN_INT_CLR_CH2 volatile.Register32 // 0xDC + IN_CONF0_CH2 volatile.Register32 // 0xE0 + IN_CONF1_CH2 volatile.Register32 // 0xE4 + INFIFO_STATUS_CH2 volatile.Register32 // 0xE8 + IN_POP_CH2 volatile.Register32 // 0xEC + IN_LINK1_CH2 volatile.Register32 // 0xF0 + IN_LINK2_CH2 volatile.Register32 // 0xF4 + IN_STATE_CH2 volatile.Register32 // 0xF8 + IN_SUC_EOF_DES_ADDR_CH2 volatile.Register32 // 0xFC + IN_ERR_EOF_DES_ADDR_CH2 volatile.Register32 // 0x100 + IN_DSCR_CH2 volatile.Register32 // 0x104 + IN_DSCR_BF0_CH2 volatile.Register32 // 0x108 + IN_DSCR_BF1_CH2 volatile.Register32 // 0x10C + IN_PRI_CH2 volatile.Register32 // 0x110 + IN_PERI_SEL_CH2 volatile.Register32 // 0x114 + IN_CRC_INIT_DATA_CH2 volatile.Register32 // 0x118 + RX_CRC_WIDTH_CH2 volatile.Register32 // 0x11C + IN_CRC_CLEAR_CH2 volatile.Register32 // 0x120 + IN_CRC_FINAL_RESULT_CH2 volatile.Register32 // 0x124 + RX_CRC_EN_WR_DATA_CH2 volatile.Register32 // 0x128 + RX_CRC_EN_ADDR_CH2 volatile.Register32 // 0x12C + RX_CRC_DATA_EN_WR_DATA_CH2 volatile.Register32 // 0x130 + RX_CRC_DATA_EN_ADDR_CH2 volatile.Register32 // 0x134 + OUT_INT_RAW_CH0 volatile.Register32 // 0x138 + OUT_INT_ST_CH0 volatile.Register32 // 0x13C + OUT_INT_ENA_CH0 volatile.Register32 // 0x140 + OUT_INT_CLR_CH0 volatile.Register32 // 0x144 + OUT_CONF0_CH0 volatile.Register32 // 0x148 + OUT_CONF1_CH0 volatile.Register32 // 0x14C + OUTFIFO_STATUS_CH0 volatile.Register32 // 0x150 + OUT_PUSH_CH0 volatile.Register32 // 0x154 + OUT_LINK1_CH0 volatile.Register32 // 0x158 + OUT_LINK2_CH0 volatile.Register32 // 0x15C + OUT_STATE_CH0 volatile.Register32 // 0x160 + OUT_EOF_DES_ADDR_CH0 volatile.Register32 // 0x164 + OUT_EOF_BFR_DES_ADDR_CH0 volatile.Register32 // 0x168 + OUT_DSCR_CH0 volatile.Register32 // 0x16C + OUT_DSCR_BF0_CH0 volatile.Register32 // 0x170 + OUT_DSCR_BF1_CH0 volatile.Register32 // 0x174 + OUT_PRI_CH0 volatile.Register32 // 0x178 + OUT_PERI_SEL_CH0 volatile.Register32 // 0x17C + OUT_CRC_INIT_DATA_CH0 volatile.Register32 // 0x180 + TX_CRC_WIDTH_CH0 volatile.Register32 // 0x184 + OUT_CRC_CLEAR_CH0 volatile.Register32 // 0x188 + OUT_CRC_FINAL_RESULT_CH0 volatile.Register32 // 0x18C + TX_CRC_EN_WR_DATA_CH0 volatile.Register32 // 0x190 + TX_CRC_EN_ADDR_CH0 volatile.Register32 // 0x194 + TX_CRC_DATA_EN_WR_DATA_CH0 volatile.Register32 // 0x198 + TX_CRC_DATA_EN_ADDR_CH0 volatile.Register32 // 0x19C + OUT_INT_RAW_CH1 volatile.Register32 // 0x1A0 + OUT_INT_ST_CH1 volatile.Register32 // 0x1A4 + OUT_INT_ENA_CH1 volatile.Register32 // 0x1A8 + OUT_INT_CLR_CH1 volatile.Register32 // 0x1AC + OUT_CONF0_CH1 volatile.Register32 // 0x1B0 + OUT_CONF1_CH1 volatile.Register32 // 0x1B4 + OUTFIFO_STATUS_CH1 volatile.Register32 // 0x1B8 + OUT_PUSH_CH1 volatile.Register32 // 0x1BC + OUT_LINK1_CH1 volatile.Register32 // 0x1C0 + OUT_LINK2_CH1 volatile.Register32 // 0x1C4 + OUT_STATE_CH1 volatile.Register32 // 0x1C8 + OUT_EOF_DES_ADDR_CH1 volatile.Register32 // 0x1CC + OUT_EOF_BFR_DES_ADDR_CH1 volatile.Register32 // 0x1D0 + OUT_DSCR_CH1 volatile.Register32 // 0x1D4 + OUT_DSCR_BF0_CH1 volatile.Register32 // 0x1D8 + OUT_DSCR_BF1_CH1 volatile.Register32 // 0x1DC + OUT_PRI_CH1 volatile.Register32 // 0x1E0 + OUT_PERI_SEL_CH1 volatile.Register32 // 0x1E4 + OUT_CRC_INIT_DATA_CH1 volatile.Register32 // 0x1E8 + TX_CRC_WIDTH_CH1 volatile.Register32 // 0x1EC + OUT_CRC_CLEAR_CH1 volatile.Register32 // 0x1F0 + OUT_CRC_FINAL_RESULT_CH1 volatile.Register32 // 0x1F4 + TX_CRC_EN_WR_DATA_CH1 volatile.Register32 // 0x1F8 + TX_CRC_EN_ADDR_CH1 volatile.Register32 // 0x1FC + TX_CRC_DATA_EN_WR_DATA_CH1 volatile.Register32 // 0x200 + TX_CRC_DATA_EN_ADDR_CH1 volatile.Register32 // 0x204 + OUT_INT_RAW_CH2 volatile.Register32 // 0x208 + OUT_INT_ST_CH2 volatile.Register32 // 0x20C + OUT_INT_ENA_CH2 volatile.Register32 // 0x210 + OUT_INT_CLR_CH2 volatile.Register32 // 0x214 + OUT_CONF0_CH2 volatile.Register32 // 0x218 + OUT_CONF1_CH2 volatile.Register32 // 0x21C + OUTFIFO_STATUS_CH2 volatile.Register32 // 0x220 + OUT_PUSH_CH2 volatile.Register32 // 0x224 + OUT_LINK1_CH2 volatile.Register32 // 0x228 + OUT_LINK2_CH2 volatile.Register32 // 0x22C + OUT_STATE_CH2 volatile.Register32 // 0x230 + OUT_EOF_DES_ADDR_CH2 volatile.Register32 // 0x234 + OUT_EOF_BFR_DES_ADDR_CH2 volatile.Register32 // 0x238 + OUT_DSCR_CH2 volatile.Register32 // 0x23C + OUT_DSCR_BF0_CH2 volatile.Register32 // 0x240 + OUT_DSCR_BF1_CH2 volatile.Register32 // 0x244 + OUT_PRI_CH2 volatile.Register32 // 0x248 + OUT_PERI_SEL_CH2 volatile.Register32 // 0x24C + OUT_CRC_INIT_DATA_CH2 volatile.Register32 // 0x250 + TX_CRC_WIDTH_CH2 volatile.Register32 // 0x254 + OUT_CRC_CLEAR_CH2 volatile.Register32 // 0x258 + OUT_CRC_FINAL_RESULT_CH2 volatile.Register32 // 0x25C + TX_CRC_EN_WR_DATA_CH2 volatile.Register32 // 0x260 + TX_CRC_EN_ADDR_CH2 volatile.Register32 // 0x264 + TX_CRC_DATA_EN_WR_DATA_CH2 volatile.Register32 // 0x268 + TX_CRC_DATA_EN_ADDR_CH2 volatile.Register32 // 0x26C + ARB_TIMEOUT volatile.Register32 // 0x270 + WEIGHT_EN volatile.Register32 // 0x274 + IN_MEM_CONF volatile.Register32 // 0x278 + INTR_MEM_START_ADDR volatile.Register32 // 0x27C + INTR_MEM_END_ADDR volatile.Register32 // 0x280 + EXTR_MEM_START_ADDR volatile.Register32 // 0x284 + EXTR_MEM_END_ADDR volatile.Register32 // 0x288 + IN_RESET_AVAIL_CH0 volatile.Register32 // 0x28C + IN_RESET_AVAIL_CH1 volatile.Register32 // 0x290 + IN_RESET_AVAIL_CH2 volatile.Register32 // 0x294 + OUT_RESET_AVAIL_CH0 volatile.Register32 // 0x298 + OUT_RESET_AVAIL_CH1 volatile.Register32 // 0x29C + OUT_RESET_AVAIL_CH2 volatile.Register32 // 0x2A0 + _ [4]byte + MISC_CONF volatile.Register32 // 0x2A8 + RDN_RESULT volatile.Register32 // 0x2AC + RDN_ECO_HIGH volatile.Register32 // 0x2B0 + RDN_ECO_LOW volatile.Register32 // 0x2B4 + WRESP_CNT volatile.Register32 // 0x2B8 + RRESP_CNT volatile.Register32 // 0x2BC + INFIFO_STATUS1_CH0 volatile.Register32 // 0x2C0 + INFIFO_STATUS1_CH1 volatile.Register32 // 0x2C4 + INFIFO_STATUS1_CH2 volatile.Register32 // 0x2C8 + OUTFIFO_STATUS1_CH0 volatile.Register32 // 0x2CC + OUTFIFO_STATUS1_CH1 volatile.Register32 // 0x2D0 + OUTFIFO_STATUS1_CH2 volatile.Register32 // 0x2D4 + DATE volatile.Register32 // 0x2D8 +} + +// AXI_DMA.IN_INT_RAW_CH0: Raw status interrupt of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_SUC_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_SUC_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_ERR_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_ERR_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L1_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L1_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L1_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L1_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L2_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L2_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L2_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L2_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L3_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L3_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L3_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L3_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_INT_ST_CH0: Masked interrupt of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_SUC_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_SUC_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_ERR_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_ERR_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_L1_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_L1_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_L1_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_L1_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_L3_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_L3_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_L3_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_L3_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_INT_ENA_CH0: Interrupt enable bits of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_SUC_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_SUC_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_ERR_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_ERR_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L1_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L1_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L1_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L1_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L2_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L2_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L2_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L2_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L3_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L3_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L3_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L3_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_INT_CLR_CH0: Interrupt clear bits of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_SUC_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_SUC_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_ERR_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_ERR_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L1_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L1_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L1_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L1_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L2_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L2_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L2_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L2_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L3_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L3_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L3_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L3_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_CONF0_CH0: Configure 0 register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_RST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_RST_CH() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_LOOP_TEST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_LOOP_TEST_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH0_MEM_TRANS_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH0_MEM_TRANS_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_ETM_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_ETM_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_BURST_SIZE_SEL_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x70)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_BURST_SIZE_SEL_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x70) >> 4 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_CMD_DISABLE_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_CMD_DISABLE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_ECC_AEC_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_ECC_AEC_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x200) >> 9 +} + +// AXI_DMA.IN_CONF1_CH0: Configure 1 register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_CONF1_CH0_IN_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetIN_CONF1_CH0_IN_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// AXI_DMA.INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0 +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_FULL_CH() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_UDF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_OVF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L1_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L1_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x400) >> 10 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L1_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800)|value<<11) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L1_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800) >> 11 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L1_UDF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L1_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000) >> 12 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L1_OVF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000)|value<<13) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L1_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000) >> 13 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L2_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000)|value<<14) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L2_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000) >> 14 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L2_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000)|value<<15) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L2_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000) >> 15 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L2_UDF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x10000)|value<<16) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L2_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x10000) >> 16 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L2_OVF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x20000)|value<<17) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L2_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x20000) >> 17 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_5B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_5B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_6B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x10000000)|value<<28) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_6B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x10000000) >> 28 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_7B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x20000000)|value<<29) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_7B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x20000000) >> 29 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_8B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x40000000)|value<<30) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_8B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x40000000) >> 30 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_BUF_HUNGRY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x80000000)|value<<31) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_BUF_HUNGRY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x80000000) >> 31 +} + +// AXI_DMA.IN_POP_CH0: Pop control register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_POP_CH0_INFIFO_RDATA_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0xfff)|value) +} +func (o *AXI_DMA_Type) GetIN_POP_CH0_INFIFO_RDATA_CH() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0xfff +} +func (o *AXI_DMA_Type) SetIN_POP_CH0_INFIFO_POP_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetIN_POP_CH0_INFIFO_POP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x1000) >> 12 +} + +// AXI_DMA.IN_LINK1_CH0: Link descriptor configure and control register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_AUTO_RET_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_AUTO_RET_CH() uint32 { + return volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_STOP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x10) >> 4 +} + +// AXI_DMA.IN_LINK2_CH0: Link descriptor configure and control register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_LINK2_CH0(value uint32) { + volatile.StoreUint32(&o.IN_LINK2_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_LINK2_CH0() uint32 { + return volatile.LoadUint32(&o.IN_LINK2_CH0.Reg) +} + +// AXI_DMA.IN_STATE_CH0: Receive status of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *AXI_DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff +} +func (o *AXI_DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *AXI_DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *AXI_DMA_Type) SetIN_STATE_CH0_IN_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *AXI_DMA_Type) GetIN_STATE_CH0_IN_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// AXI_DMA.IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg) +} + +// AXI_DMA.IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg) +} + +// AXI_DMA.IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg) +} + +// AXI_DMA.IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg) +} + +// AXI_DMA.IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg) +} + +// AXI_DMA.IN_PRI_CH0: Priority register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_PRI_CH0_RX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *AXI_DMA_Type) GetIN_PRI_CH0_RX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf +} +func (o *AXI_DMA_Type) SetIN_PRI_CH0_RX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf0)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_PRI_CH0_RX_CH_ARB_WEIGH_CH() uint32 { + return (volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf0) >> 4 +} +func (o *AXI_DMA_Type) SetIN_PRI_CH0_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_PRI_CH0_RX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return (volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0x100) >> 8 +} + +// AXI_DMA.IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_PERI_SEL_CH0_PERI_IN_SEL_CH(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetIN_PERI_SEL_CH0_PERI_IN_SEL_CH() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg) & 0x3f +} + +// AXI_DMA.IN_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AXI_DMA_Type) SetIN_CRC_INIT_DATA_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_CRC_INIT_DATA_CH0() uint32 { + return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH0.Reg) +} + +// AXI_DMA.RX_CRC_WIDTH_CH0: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AXI_DMA.IN_CRC_CLEAR_CH0: This register is used to clear ch0 crc result +func (o *AXI_DMA_Type) SetIN_CRC_CLEAR_CH0_IN_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.IN_CRC_CLEAR_CH0.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_CRC_CLEAR_CH0_IN_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH0.Reg) & 0x1 +} + +// AXI_DMA.IN_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result +func (o *AXI_DMA_Type) SetIN_CRC_FINAL_RESULT_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_CRC_FINAL_RESULT_CH0() uint32 { + return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH0.Reg) +} + +// AXI_DMA.RX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit +func (o *AXI_DMA_Type) SetRX_CRC_EN_WR_DATA_CH0(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetRX_CRC_EN_WR_DATA_CH0() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH0.Reg) +} + +// AXI_DMA.RX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr +func (o *AXI_DMA_Type) SetRX_CRC_EN_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetRX_CRC_EN_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH0.Reg) +} + +// AXI_DMA.RX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en +func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH0_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg)&^(0xffff)|value) +} +func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH0_RX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg) & 0xffff +} + +// AXI_DMA.RX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en +func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH0.Reg) +} + +// AXI_DMA.IN_INT_RAW_CH1: Raw status interrupt of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_SUC_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_SUC_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_ERR_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_ERR_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L1_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L1_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L1_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L1_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L2_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L2_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L2_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L2_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L3_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L3_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L3_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L3_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_INT_ST_CH1: Masked interrupt of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_SUC_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_SUC_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_ERR_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_ERR_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_L1_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_L1_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_L1_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_L1_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_L3_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_L3_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_L3_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_L3_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_INT_ENA_CH1: Interrupt enable bits of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_SUC_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_SUC_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_ERR_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_ERR_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L1_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L1_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L1_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L1_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L2_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L2_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L2_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L2_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L3_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L3_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L3_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L3_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_INT_CLR_CH1: Interrupt clear bits of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_SUC_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_SUC_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_ERR_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_ERR_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L1_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L1_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L1_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L1_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L2_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L2_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L2_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L2_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L3_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L3_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L3_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L3_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_CONF0_CH1: Configure 0 register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_RST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_RST_CH() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_LOOP_TEST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_LOOP_TEST_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH1_MEM_TRANS_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH1_MEM_TRANS_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_ETM_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_ETM_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_BURST_SIZE_SEL_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x70)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_BURST_SIZE_SEL_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x70) >> 4 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_CMD_DISABLE_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_CMD_DISABLE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_ECC_AEC_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_ECC_AEC_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x200) >> 9 +} + +// AXI_DMA.IN_CONF1_CH1: Configure 1 register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_CONF1_CH1_IN_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetIN_CONF1_CH1_IN_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// AXI_DMA.INFIFO_STATUS_CH1: Receive FIFO status of Rx channel 0 +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_FULL_CH() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_UDF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_OVF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L1_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L1_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x400) >> 10 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L1_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x800)|value<<11) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L1_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x800) >> 11 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L1_UDF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L1_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000) >> 12 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L1_OVF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000)|value<<13) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L1_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000) >> 13 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L2_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000)|value<<14) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L2_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000) >> 14 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L2_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000)|value<<15) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L2_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000) >> 15 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L2_UDF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x10000)|value<<16) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L2_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x10000) >> 16 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L2_OVF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x20000)|value<<17) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L2_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x20000) >> 17 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_5B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_5B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_6B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x10000000)|value<<28) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_6B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x10000000) >> 28 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_7B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x20000000)|value<<29) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_7B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x20000000) >> 29 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_8B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x40000000)|value<<30) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_8B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x40000000) >> 30 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_BUF_HUNGRY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x80000000)|value<<31) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_BUF_HUNGRY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x80000000) >> 31 +} + +// AXI_DMA.IN_POP_CH1: Pop control register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_POP_CH1_INFIFO_RDATA_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0xfff)|value) +} +func (o *AXI_DMA_Type) GetIN_POP_CH1_INFIFO_RDATA_CH() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0xfff +} +func (o *AXI_DMA_Type) SetIN_POP_CH1_INFIFO_POP_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetIN_POP_CH1_INFIFO_POP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x1000) >> 12 +} + +// AXI_DMA.IN_LINK1_CH1: Link descriptor configure and control register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_AUTO_RET_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_AUTO_RET_CH() uint32 { + return volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_STOP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x10) >> 4 +} + +// AXI_DMA.IN_LINK2_CH1: Link descriptor configure and control register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_LINK2_CH1(value uint32) { + volatile.StoreUint32(&o.IN_LINK2_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_LINK2_CH1() uint32 { + return volatile.LoadUint32(&o.IN_LINK2_CH1.Reg) +} + +// AXI_DMA.IN_STATE_CH1: Receive status of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *AXI_DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff +} +func (o *AXI_DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *AXI_DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *AXI_DMA_Type) SetIN_STATE_CH1_IN_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *AXI_DMA_Type) GetIN_STATE_CH1_IN_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// AXI_DMA.IN_SUC_EOF_DES_ADDR_CH1: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg) +} + +// AXI_DMA.IN_ERR_EOF_DES_ADDR_CH1: Inlink descriptor address when errors occur of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg) +} + +// AXI_DMA.IN_DSCR_CH1: Current inlink descriptor address of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg) +} + +// AXI_DMA.IN_DSCR_BF0_CH1: The last inlink descriptor address of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg) +} + +// AXI_DMA.IN_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg) +} + +// AXI_DMA.IN_PRI_CH1: Priority register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_PRI_CH1_RX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *AXI_DMA_Type) GetIN_PRI_CH1_RX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf +} +func (o *AXI_DMA_Type) SetIN_PRI_CH1_RX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf0)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_PRI_CH1_RX_CH_ARB_WEIGH_CH() uint32 { + return (volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf0) >> 4 +} +func (o *AXI_DMA_Type) SetIN_PRI_CH1_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_PRI_CH1_RX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return (volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0x100) >> 8 +} + +// AXI_DMA.IN_PERI_SEL_CH1: Peripheral selection of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_PERI_SEL_CH1_PERI_IN_SEL_CH(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetIN_PERI_SEL_CH1_PERI_IN_SEL_CH() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg) & 0x3f +} + +// AXI_DMA.IN_CRC_INIT_DATA_CH1: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AXI_DMA_Type) SetIN_CRC_INIT_DATA_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_CRC_INIT_DATA_CH1() uint32 { + return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH1.Reg) +} + +// AXI_DMA.RX_CRC_WIDTH_CH1: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AXI_DMA.IN_CRC_CLEAR_CH1: This register is used to clear ch0 crc result +func (o *AXI_DMA_Type) SetIN_CRC_CLEAR_CH1_IN_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.IN_CRC_CLEAR_CH1.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_CRC_CLEAR_CH1_IN_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH1.Reg) & 0x1 +} + +// AXI_DMA.IN_CRC_FINAL_RESULT_CH1: This register is used to store ch0 crc result +func (o *AXI_DMA_Type) SetIN_CRC_FINAL_RESULT_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_CRC_FINAL_RESULT_CH1() uint32 { + return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH1.Reg) +} + +// AXI_DMA.RX_CRC_EN_WR_DATA_CH1: This resister is used to config ch0 crc en for every bit +func (o *AXI_DMA_Type) SetRX_CRC_EN_WR_DATA_CH1(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetRX_CRC_EN_WR_DATA_CH1() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH1.Reg) +} + +// AXI_DMA.RX_CRC_EN_ADDR_CH1: This register is used to config ch0 crc en addr +func (o *AXI_DMA_Type) SetRX_CRC_EN_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetRX_CRC_EN_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH1.Reg) +} + +// AXI_DMA.RX_CRC_DATA_EN_WR_DATA_CH1: This register is used to config crc data_8bit en +func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH1_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg)&^(0xffff)|value) +} +func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH1_RX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg) & 0xffff +} + +// AXI_DMA.RX_CRC_DATA_EN_ADDR_CH1: This register is used to config addr of crc data_8bit en +func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH1.Reg) +} + +// AXI_DMA.IN_INT_RAW_CH2: Raw status interrupt of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_SUC_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_SUC_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_ERR_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_ERR_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L1_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L1_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L1_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L1_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L2_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L2_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L2_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L2_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L3_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L3_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L3_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L3_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_INT_ST_CH2: Masked interrupt of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_SUC_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_SUC_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_ERR_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_ERR_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_L1_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_L1_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_L1_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_L1_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_L3_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_L3_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_L3_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_L3_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_INT_ENA_CH2: Interrupt enable bits of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_SUC_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_SUC_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_ERR_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_ERR_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L1_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L1_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L1_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L1_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L2_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L2_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L2_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L2_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L3_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L3_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L3_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L3_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_INT_CLR_CH2: Interrupt clear bits of channel 0 +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_SUC_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_SUC_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_ERR_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_ERR_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L1_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L1_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L1_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L1_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L2_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L2_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L2_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L2_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L3_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L3_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L3_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L3_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x400) >> 10 +} + +// AXI_DMA.IN_CONF0_CH2: Configure 0 register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_RST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_RST_CH() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_LOOP_TEST_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_LOOP_TEST_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH2_MEM_TRANS_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH2_MEM_TRANS_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_ETM_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_ETM_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_BURST_SIZE_SEL_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x70)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_BURST_SIZE_SEL_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x70) >> 4 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_CMD_DISABLE_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_CMD_DISABLE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_ECC_AEC_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_ECC_AEC_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x200) >> 9 +} + +// AXI_DMA.IN_CONF1_CH2: Configure 1 register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_CONF1_CH2_IN_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetIN_CONF1_CH2_IN_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// AXI_DMA.INFIFO_STATUS_CH2: Receive FIFO status of Rx channel 0 +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_FULL_CH() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_UDF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_OVF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L1_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L1_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x400) >> 10 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L1_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x800)|value<<11) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L1_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x800) >> 11 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L1_UDF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L1_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000) >> 12 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L1_OVF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000)|value<<13) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L1_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000) >> 13 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L2_FULL_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000)|value<<14) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L2_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000) >> 14 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L2_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000)|value<<15) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L2_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000) >> 15 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L2_UDF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x10000)|value<<16) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L2_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x10000) >> 16 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L2_OVF_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x20000)|value<<17) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L2_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x20000) >> 17 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_5B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_5B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_6B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x10000000)|value<<28) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_6B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x10000000) >> 28 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_7B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x20000000)|value<<29) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_7B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x20000000) >> 29 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_8B_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x40000000)|value<<30) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_8B_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x40000000) >> 30 +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_BUF_HUNGRY_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x80000000)|value<<31) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_BUF_HUNGRY_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x80000000) >> 31 +} + +// AXI_DMA.IN_POP_CH2: Pop control register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_POP_CH2_INFIFO_RDATA_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0xfff)|value) +} +func (o *AXI_DMA_Type) GetIN_POP_CH2_INFIFO_RDATA_CH() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0xfff +} +func (o *AXI_DMA_Type) SetIN_POP_CH2_INFIFO_POP_CH(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetIN_POP_CH2_INFIFO_POP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x1000) >> 12 +} + +// AXI_DMA.IN_LINK1_CH2: Link descriptor configure and control register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_AUTO_RET_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_AUTO_RET_CH() uint32 { + return volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_STOP_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x10) >> 4 +} + +// AXI_DMA.IN_LINK2_CH2: Link descriptor configure and control register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_LINK2_CH2(value uint32) { + volatile.StoreUint32(&o.IN_LINK2_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_LINK2_CH2() uint32 { + return volatile.LoadUint32(&o.IN_LINK2_CH2.Reg) +} + +// AXI_DMA.IN_STATE_CH2: Receive status of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *AXI_DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff +} +func (o *AXI_DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *AXI_DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *AXI_DMA_Type) SetIN_STATE_CH2_IN_STATE_CH(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *AXI_DMA_Type) GetIN_STATE_CH2_IN_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// AXI_DMA.IN_SUC_EOF_DES_ADDR_CH2: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg) +} + +// AXI_DMA.IN_ERR_EOF_DES_ADDR_CH2: Inlink descriptor address when errors occur of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg) +} + +// AXI_DMA.IN_DSCR_CH2: Current inlink descriptor address of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg) +} + +// AXI_DMA.IN_DSCR_BF0_CH2: The last inlink descriptor address of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg) +} + +// AXI_DMA.IN_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg) +} + +// AXI_DMA.IN_PRI_CH2: Priority register of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_PRI_CH2_RX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *AXI_DMA_Type) GetIN_PRI_CH2_RX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf +} +func (o *AXI_DMA_Type) SetIN_PRI_CH2_RX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf0)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_PRI_CH2_RX_CH_ARB_WEIGH_CH() uint32 { + return (volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf0) >> 4 +} +func (o *AXI_DMA_Type) SetIN_PRI_CH2_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetIN_PRI_CH2_RX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return (volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0x100) >> 8 +} + +// AXI_DMA.IN_PERI_SEL_CH2: Peripheral selection of Rx channel 0 +func (o *AXI_DMA_Type) SetIN_PERI_SEL_CH2_PERI_IN_SEL_CH(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetIN_PERI_SEL_CH2_PERI_IN_SEL_CH() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg) & 0x3f +} + +// AXI_DMA.IN_CRC_INIT_DATA_CH2: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AXI_DMA_Type) SetIN_CRC_INIT_DATA_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_CRC_INIT_DATA_CH2() uint32 { + return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH2.Reg) +} + +// AXI_DMA.RX_CRC_WIDTH_CH2: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AXI_DMA.IN_CRC_CLEAR_CH2: This register is used to clear ch0 crc result +func (o *AXI_DMA_Type) SetIN_CRC_CLEAR_CH2_IN_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.IN_CRC_CLEAR_CH2.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_CRC_CLEAR_CH2_IN_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH2.Reg) & 0x1 +} + +// AXI_DMA.IN_CRC_FINAL_RESULT_CH2: This register is used to store ch0 crc result +func (o *AXI_DMA_Type) SetIN_CRC_FINAL_RESULT_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetIN_CRC_FINAL_RESULT_CH2() uint32 { + return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH2.Reg) +} + +// AXI_DMA.RX_CRC_EN_WR_DATA_CH2: This resister is used to config ch0 crc en for every bit +func (o *AXI_DMA_Type) SetRX_CRC_EN_WR_DATA_CH2(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetRX_CRC_EN_WR_DATA_CH2() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH2.Reg) +} + +// AXI_DMA.RX_CRC_EN_ADDR_CH2: This register is used to config ch0 crc en addr +func (o *AXI_DMA_Type) SetRX_CRC_EN_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetRX_CRC_EN_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH2.Reg) +} + +// AXI_DMA.RX_CRC_DATA_EN_WR_DATA_CH2: This register is used to config crc data_8bit en +func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH2_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg)&^(0xffff)|value) +} +func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH2_RX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg) & 0xffff +} + +// AXI_DMA.RX_CRC_DATA_EN_ADDR_CH2: This register is used to config addr of crc data_8bit en +func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH2.Reg) +} + +// AXI_DMA.OUT_INT_RAW_CH0: Raw status interrupt of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUT_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUT_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L1_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L1_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L1_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L1_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L2_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L2_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L2_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L2_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L3_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L3_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L3_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L3_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_INT_ST_CH0: Masked interrupt of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUT_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUT_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUT_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUT_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_L1_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_L1_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_L1_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_L1_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_L3_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_L3_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_L3_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_L3_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_INT_ENA_CH0: Interrupt enable bits of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUT_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUT_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L1_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L1_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L1_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L1_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L2_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L2_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L2_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L2_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L3_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L3_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L3_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L3_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_INT_CLR_CH0: Interrupt clear bits of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUT_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUT_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L1_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L1_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L1_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L1_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L2_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L2_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L2_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L2_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L3_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L3_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L3_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L3_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_CONF0_CH0: Configure 0 register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_RST_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_RST_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_ETM_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_ETM_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_BURST_SIZE_SEL_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0xe0)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_BURST_SIZE_SEL_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0xe0) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_CMD_DISABLE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_CMD_DISABLE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_ECC_AEC_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_ECC_AEC_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x400) >> 10 +} + +// AXI_DMA.OUT_CONF1_CH0: Configure 1 register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_CONF1_CH0_OUT_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetOUT_CONF1_CH0_OUT_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x1000) >> 12 +} + +// AXI_DMA.OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel0 +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_FULL_CH() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xfc) >> 2 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_UDF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_OVF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L1_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L1_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x400) >> 10 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L1_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800)|value<<11) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L1_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800) >> 11 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L1_UDF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L1_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000) >> 12 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L1_OVF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000)|value<<13) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L1_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000) >> 13 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L2_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000)|value<<14) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L2_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000) >> 14 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L2_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x8000)|value<<15) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L2_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x8000) >> 15 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L2_UDF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x10000)|value<<16) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L2_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x10000) >> 16 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L2_OVF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x20000)|value<<17) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L2_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x20000) >> 17 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_5B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_5B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_6B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x10000000)|value<<28) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_6B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x10000000) >> 28 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_7B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x20000000)|value<<29) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_7B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x20000000) >> 29 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_8B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x40000000)|value<<30) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_8B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x40000000) >> 30 +} + +// AXI_DMA.OUT_PUSH_CH0: Push control register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x1ff)|value) +} +func (o *AXI_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x1ff +} +func (o *AXI_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_LINK1_CH0: Link descriptor configure and control register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_LINK1_CH0_OUTLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH0_OUTLINK_STOP_CH() uint32 { + return volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_LINK1_CH0_OUTLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH0_OUTLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_LINK1_CH0_OUTLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH0_OUTLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_LINK1_CH0_OUTLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH0_OUTLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg) & 0x8) >> 3 +} + +// AXI_DMA.OUT_LINK2_CH0: Link descriptor configure and control register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_LINK2_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_LINK2_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_LINK2_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_LINK2_CH0.Reg) +} + +// AXI_DMA.OUT_STATE_CH0: Transmit status of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *AXI_DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff +} +func (o *AXI_DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *AXI_DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *AXI_DMA_Type) SetOUT_STATE_CH0_OUT_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *AXI_DMA_Type) GetOUT_STATE_CH0_OUT_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// AXI_DMA.OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg) +} + +// AXI_DMA.OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg) +} + +// AXI_DMA.OUT_DSCR_CH0: Current outlink descriptor address of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg) +} + +// AXI_DMA.OUT_DSCR_BF0_CH0: The last outlink descriptor address of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg) +} + +// AXI_DMA.OUT_DSCR_BF1_CH0: The second-to-last outlink descriptor address of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg) +} + +// AXI_DMA.OUT_PRI_CH0: Priority register of Tx channel0. +func (o *AXI_DMA_Type) SetOUT_PRI_CH0_TX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *AXI_DMA_Type) GetOUT_PRI_CH0_TX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf +} +func (o *AXI_DMA_Type) SetOUT_PRI_CH0_TX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf0)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_PRI_CH0_TX_CH_ARB_WEIGH_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf0) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_PRI_CH0_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_PRI_CH0_TX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0x100) >> 8 +} + +// AXI_DMA.OUT_PERI_SEL_CH0: Peripheral selection of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_PERI_SEL_CH0_PERI_OUT_SEL_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetOUT_PERI_SEL_CH0_PERI_OUT_SEL_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg) & 0x3f +} + +// AXI_DMA.OUT_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AXI_DMA_Type) SetOUT_CRC_INIT_DATA_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_CRC_INIT_DATA_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH0.Reg) +} + +// AXI_DMA.TX_CRC_WIDTH_CH0: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AXI_DMA.OUT_CRC_CLEAR_CH0: This register is used to clear ch0 crc result +func (o *AXI_DMA_Type) SetOUT_CRC_CLEAR_CH0_OUT_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH0.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_CRC_CLEAR_CH0_OUT_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH0.Reg) & 0x1 +} + +// AXI_DMA.OUT_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result +func (o *AXI_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH0.Reg) +} + +// AXI_DMA.TX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit +func (o *AXI_DMA_Type) SetTX_CRC_EN_WR_DATA_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetTX_CRC_EN_WR_DATA_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH0.Reg) +} + +// AXI_DMA.TX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr +func (o *AXI_DMA_Type) SetTX_CRC_EN_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetTX_CRC_EN_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH0.Reg) +} + +// AXI_DMA.TX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en +func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH0_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg)&^(0xffff)|value) +} +func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH0_TX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg) & 0xffff +} + +// AXI_DMA.TX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en +func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH0.Reg, value) +} +func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH0.Reg) +} + +// AXI_DMA.OUT_INT_RAW_CH1: Raw status interrupt of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUT_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUT_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L1_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L1_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L1_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L1_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L2_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L2_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L2_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L2_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L3_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L3_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L3_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L3_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_INT_ST_CH1: Masked interrupt of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUT_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUT_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUT_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUT_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_L1_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_L1_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_L1_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_L1_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_L3_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_L3_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_L3_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_L3_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_INT_ENA_CH1: Interrupt enable bits of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUT_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUT_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L1_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L1_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L1_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L1_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L2_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L2_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L2_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L2_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L3_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L3_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L3_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L3_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_INT_CLR_CH1: Interrupt clear bits of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUT_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUT_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L1_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L1_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L1_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L1_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L2_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L2_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L2_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L2_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L3_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L3_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L3_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L3_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_CONF0_CH1: Configure 0 register of Tx channel1 +func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_RST_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_RST_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_LOOP_TEST_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_LOOP_TEST_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_ETM_EN_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_ETM_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_BURST_SIZE_SEL_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0xe0)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_BURST_SIZE_SEL_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0xe0) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_CMD_DISABLE_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_CMD_DISABLE_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_ECC_AEC_EN_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_ECC_AEC_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x400) >> 10 +} + +// AXI_DMA.OUT_CONF1_CH1: Configure 1 register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_CONF1_CH1_OUT_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetOUT_CONF1_CH1_OUT_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg) & 0x1000) >> 12 +} + +// AXI_DMA.OUTFIFO_STATUS_CH1: Transmit FIFO status of Tx channel0 +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_FULL_CH() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0xfc) >> 2 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_UDF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_OVF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L1_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L1_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x400) >> 10 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L1_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800)|value<<11) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L1_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800) >> 11 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L1_UDF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L1_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000) >> 12 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L1_OVF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000)|value<<13) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L1_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000) >> 13 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L2_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000)|value<<14) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L2_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000) >> 14 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L2_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x8000)|value<<15) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L2_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x8000) >> 15 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L2_UDF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x10000)|value<<16) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L2_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x10000) >> 16 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L2_OVF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x20000)|value<<17) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L2_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x20000) >> 17 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_5B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_5B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_6B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x10000000)|value<<28) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_6B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x10000000) >> 28 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_7B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x20000000)|value<<29) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_7B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x20000000) >> 29 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_8B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x40000000)|value<<30) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_8B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x40000000) >> 30 +} + +// AXI_DMA.OUT_PUSH_CH1: Push control register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x1ff)|value) +} +func (o *AXI_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x1ff +} +func (o *AXI_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_LINK1_CH1: Link descriptor configure and control register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_LINK1_CH1_OUTLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH1_OUTLINK_STOP_CH() uint32 { + return volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_LINK1_CH1_OUTLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH1_OUTLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_LINK1_CH1_OUTLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH1_OUTLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_LINK1_CH1_OUTLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH1_OUTLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg) & 0x8) >> 3 +} + +// AXI_DMA.OUT_LINK2_CH1: Link descriptor configure and control register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_LINK2_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_LINK2_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_LINK2_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_LINK2_CH1.Reg) +} + +// AXI_DMA.OUT_STATE_CH1: Transmit status of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *AXI_DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff +} +func (o *AXI_DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *AXI_DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *AXI_DMA_Type) SetOUT_STATE_CH1_OUT_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *AXI_DMA_Type) GetOUT_STATE_CH1_OUT_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// AXI_DMA.OUT_EOF_DES_ADDR_CH1: Outlink descriptor address when EOF occurs of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg) +} + +// AXI_DMA.OUT_EOF_BFR_DES_ADDR_CH1: The last outlink descriptor address when EOF occurs of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg) +} + +// AXI_DMA.OUT_DSCR_CH1: Current outlink descriptor address of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg) +} + +// AXI_DMA.OUT_DSCR_BF0_CH1: The last outlink descriptor address of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg) +} + +// AXI_DMA.OUT_DSCR_BF1_CH1: The second-to-last outlink descriptor address of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg) +} + +// AXI_DMA.OUT_PRI_CH1: Priority register of Tx channel0. +func (o *AXI_DMA_Type) SetOUT_PRI_CH1_TX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *AXI_DMA_Type) GetOUT_PRI_CH1_TX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf +} +func (o *AXI_DMA_Type) SetOUT_PRI_CH1_TX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf0)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_PRI_CH1_TX_CH_ARB_WEIGH_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf0) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_PRI_CH1_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_PRI_CH1_TX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0x100) >> 8 +} + +// AXI_DMA.OUT_PERI_SEL_CH1: Peripheral selection of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_PERI_SEL_CH1_PERI_OUT_SEL_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetOUT_PERI_SEL_CH1_PERI_OUT_SEL_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg) & 0x3f +} + +// AXI_DMA.OUT_CRC_INIT_DATA_CH1: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AXI_DMA_Type) SetOUT_CRC_INIT_DATA_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_CRC_INIT_DATA_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH1.Reg) +} + +// AXI_DMA.TX_CRC_WIDTH_CH1: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AXI_DMA.OUT_CRC_CLEAR_CH1: This register is used to clear ch0 crc result +func (o *AXI_DMA_Type) SetOUT_CRC_CLEAR_CH1_OUT_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH1.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_CRC_CLEAR_CH1_OUT_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH1.Reg) & 0x1 +} + +// AXI_DMA.OUT_CRC_FINAL_RESULT_CH1: This register is used to store ch0 crc result +func (o *AXI_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH1.Reg) +} + +// AXI_DMA.TX_CRC_EN_WR_DATA_CH1: This resister is used to config ch0 crc en for every bit +func (o *AXI_DMA_Type) SetTX_CRC_EN_WR_DATA_CH1(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetTX_CRC_EN_WR_DATA_CH1() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH1.Reg) +} + +// AXI_DMA.TX_CRC_EN_ADDR_CH1: This register is used to config ch0 crc en addr +func (o *AXI_DMA_Type) SetTX_CRC_EN_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetTX_CRC_EN_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH1.Reg) +} + +// AXI_DMA.TX_CRC_DATA_EN_WR_DATA_CH1: This register is used to config crc data_8bit en +func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH1_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg)&^(0xffff)|value) +} +func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH1_TX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg) & 0xffff +} + +// AXI_DMA.TX_CRC_DATA_EN_ADDR_CH1: This register is used to config addr of crc data_8bit en +func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH1.Reg, value) +} +func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH1.Reg) +} + +// AXI_DMA.OUT_INT_RAW_CH2: Raw status interrupt of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DONE_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DONE_CH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUT_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUT_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L1_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L1_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L1_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L1_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L2_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L2_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L2_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L2_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L3_OVF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L3_OVF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L3_UDF_CH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L3_UDF_CH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_INT_ST_CH2: Masked interrupt of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUT_DONE_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUT_DONE_CH_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUT_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUT_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_L1_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_L1_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_L1_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_L1_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_L3_OVF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_L3_OVF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_L3_UDF_CH_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_L3_UDF_CH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_INT_ENA_CH2: Interrupt enable bits of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DONE_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DONE_CH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUT_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUT_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L1_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L1_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L1_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L1_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L2_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L2_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L2_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L2_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L3_OVF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L3_OVF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L3_UDF_CH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L3_UDF_CH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_INT_CLR_CH2: Interrupt clear bits of channel0 +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DONE_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DONE_CH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUT_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUT_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L1_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L1_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L1_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L1_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L2_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L2_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x40) >> 6 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L2_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x80)|value<<7) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L2_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x80) >> 7 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L3_OVF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L3_OVF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L3_UDF_CH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L3_UDF_CH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_CONF0_CH2: Configure 0 register of Tx channel2 +func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_RST_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_RST_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_LOOP_TEST_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_LOOP_TEST_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_EOF_MODE_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_EOF_MODE_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_ETM_EN_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_ETM_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_BURST_SIZE_SEL_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0xe0)|value<<5) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_BURST_SIZE_SEL_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0xe0) >> 5 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_CMD_DISABLE_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_CMD_DISABLE_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_ECC_AEC_EN_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_ECC_AEC_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x400) >> 10 +} + +// AXI_DMA.OUT_CONF1_CH2: Configure 1 register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_CONF1_CH2_OUT_CHECK_OWNER_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetOUT_CONF1_CH2_OUT_CHECK_OWNER_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg) & 0x1000) >> 12 +} + +// AXI_DMA.OUTFIFO_STATUS_CH2: Transmit FIFO status of Tx channel0 +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_FULL_CH() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0xfc) >> 2 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_UDF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x100) >> 8 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_OVF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x200) >> 9 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L1_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x400)|value<<10) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L1_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x400) >> 10 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L1_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800)|value<<11) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L1_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800) >> 11 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L1_UDF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L1_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000) >> 12 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L1_OVF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000)|value<<13) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L1_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000) >> 13 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L2_FULL_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000)|value<<14) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L2_FULL_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000) >> 14 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L2_EMPTY_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x8000)|value<<15) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L2_EMPTY_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x8000) >> 15 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L2_UDF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x10000)|value<<16) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L2_UDF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x10000) >> 16 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L2_OVF_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x20000)|value<<17) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L2_OVF_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x20000) >> 17 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_5B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_5B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_6B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x10000000)|value<<28) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_6B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x10000000) >> 28 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_7B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x20000000)|value<<29) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_7B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x20000000) >> 29 +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_8B_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x40000000)|value<<30) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_8B_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x40000000) >> 30 +} + +// AXI_DMA.OUT_PUSH_CH2: Push control register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x1ff)|value) +} +func (o *AXI_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x1ff +} +func (o *AXI_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x200)|value<<9) +} +func (o *AXI_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x200) >> 9 +} + +// AXI_DMA.OUT_LINK1_CH2: Link descriptor configure and control register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_LINK1_CH2_OUTLINK_STOP_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH2_OUTLINK_STOP_CH() uint32 { + return volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetOUT_LINK1_CH2_OUTLINK_START_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH2_OUTLINK_START_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetOUT_LINK1_CH2_OUTLINK_RESTART_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH2_OUTLINK_RESTART_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetOUT_LINK1_CH2_OUTLINK_PARK_CH(value uint32) { + volatile.StoreUint32(&o.OUT_LINK1_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetOUT_LINK1_CH2_OUTLINK_PARK_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg) & 0x8) >> 3 +} + +// AXI_DMA.OUT_LINK2_CH2: Link descriptor configure and control register of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_LINK2_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_LINK2_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_LINK2_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_LINK2_CH2.Reg) +} + +// AXI_DMA.OUT_STATE_CH2: Transmit status of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *AXI_DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff +} +func (o *AXI_DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *AXI_DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *AXI_DMA_Type) SetOUT_STATE_CH2_OUT_STATE_CH(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *AXI_DMA_Type) GetOUT_STATE_CH2_OUT_STATE_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// AXI_DMA.OUT_EOF_DES_ADDR_CH2: Outlink descriptor address when EOF occurs of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg) +} + +// AXI_DMA.OUT_EOF_BFR_DES_ADDR_CH2: The last outlink descriptor address when EOF occurs of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg) +} + +// AXI_DMA.OUT_DSCR_CH2: Current outlink descriptor address of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg) +} + +// AXI_DMA.OUT_DSCR_BF0_CH2: The last outlink descriptor address of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg) +} + +// AXI_DMA.OUT_DSCR_BF1_CH2: The second-to-last outlink descriptor address of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg) +} + +// AXI_DMA.OUT_PRI_CH2: Priority register of Tx channel0. +func (o *AXI_DMA_Type) SetOUT_PRI_CH2_TX_PRI_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *AXI_DMA_Type) GetOUT_PRI_CH2_TX_PRI_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf +} +func (o *AXI_DMA_Type) SetOUT_PRI_CH2_TX_CH_ARB_WEIGH_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf0)|value<<4) +} +func (o *AXI_DMA_Type) GetOUT_PRI_CH2_TX_CH_ARB_WEIGH_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf0) >> 4 +} +func (o *AXI_DMA_Type) SetOUT_PRI_CH2_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0x100)|value<<8) +} +func (o *AXI_DMA_Type) GetOUT_PRI_CH2_TX_ARB_WEIGH_OPT_DIR_CH() uint32 { + return (volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0x100) >> 8 +} + +// AXI_DMA.OUT_PERI_SEL_CH2: Peripheral selection of Tx channel0 +func (o *AXI_DMA_Type) SetOUT_PERI_SEL_CH2_PERI_OUT_SEL_CH(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetOUT_PERI_SEL_CH2_PERI_OUT_SEL_CH() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg) & 0x3f +} + +// AXI_DMA.OUT_CRC_INIT_DATA_CH2: This register is used to config ch0 crc initial data(max 32 bit) +func (o *AXI_DMA_Type) SetOUT_CRC_INIT_DATA_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_CRC_INIT_DATA_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH2.Reg) +} + +// AXI_DMA.TX_CRC_WIDTH_CH2: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 2 +} + +// AXI_DMA.OUT_CRC_CLEAR_CH2: This register is used to clear ch0 crc result +func (o *AXI_DMA_Type) SetOUT_CRC_CLEAR_CH2_OUT_CRC_CLEAR_CH(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH2.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_CRC_CLEAR_CH2_OUT_CRC_CLEAR_CH() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH2.Reg) & 0x1 +} + +// AXI_DMA.OUT_CRC_FINAL_RESULT_CH2: This register is used to store ch0 crc result +func (o *AXI_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH2.Reg) +} + +// AXI_DMA.TX_CRC_EN_WR_DATA_CH2: This resister is used to config ch0 crc en for every bit +func (o *AXI_DMA_Type) SetTX_CRC_EN_WR_DATA_CH2(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetTX_CRC_EN_WR_DATA_CH2() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH2.Reg) +} + +// AXI_DMA.TX_CRC_EN_ADDR_CH2: This register is used to config ch0 crc en addr +func (o *AXI_DMA_Type) SetTX_CRC_EN_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetTX_CRC_EN_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH2.Reg) +} + +// AXI_DMA.TX_CRC_DATA_EN_WR_DATA_CH2: This register is used to config crc data_8bit en +func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH2_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg)&^(0xffff)|value) +} +func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH2_TX_CRC_DATA_EN_WR_DATA_CH() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg) & 0xffff +} + +// AXI_DMA.TX_CRC_DATA_EN_ADDR_CH2: This register is used to config addr of crc data_8bit en +func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH2.Reg, value) +} +func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH2.Reg) +} + +// AXI_DMA.ARB_TIMEOUT: This retister is used to config arbiter time slice +func (o *AXI_DMA_Type) SetARB_TIMEOUT_TX(value uint32) { + volatile.StoreUint32(&o.ARB_TIMEOUT.Reg, volatile.LoadUint32(&o.ARB_TIMEOUT.Reg)&^(0xffff)|value) +} +func (o *AXI_DMA_Type) GetARB_TIMEOUT_TX() uint32 { + return volatile.LoadUint32(&o.ARB_TIMEOUT.Reg) & 0xffff +} +func (o *AXI_DMA_Type) SetARB_TIMEOUT_RX(value uint32) { + volatile.StoreUint32(&o.ARB_TIMEOUT.Reg, volatile.LoadUint32(&o.ARB_TIMEOUT.Reg)&^(0xffff0000)|value<<16) +} +func (o *AXI_DMA_Type) GetARB_TIMEOUT_RX() uint32 { + return (volatile.LoadUint32(&o.ARB_TIMEOUT.Reg) & 0xffff0000) >> 16 +} + +// AXI_DMA.WEIGHT_EN: This register is used to config arbiter weight function to on or off +func (o *AXI_DMA_Type) SetWEIGHT_EN_TX(value uint32) { + volatile.StoreUint32(&o.WEIGHT_EN.Reg, volatile.LoadUint32(&o.WEIGHT_EN.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetWEIGHT_EN_TX() uint32 { + return volatile.LoadUint32(&o.WEIGHT_EN.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetWEIGHT_EN_RX(value uint32) { + volatile.StoreUint32(&o.WEIGHT_EN.Reg, volatile.LoadUint32(&o.WEIGHT_EN.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetWEIGHT_EN_RX() uint32 { + return (volatile.LoadUint32(&o.WEIGHT_EN.Reg) & 0x2) >> 1 +} + +// AXI_DMA.IN_MEM_CONF: Mem power configure register of Rx channel +func (o *AXI_DMA_Type) SetIN_MEM_CONF_IN_MEM_CLK_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_MEM_CONF_IN_MEM_CLK_FORCE_EN() uint32 { + return volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetIN_MEM_CONF_IN_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetIN_MEM_CONF_IN_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetIN_MEM_CONF_IN_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x4)|value<<2) +} +func (o *AXI_DMA_Type) GetIN_MEM_CONF_IN_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x4) >> 2 +} +func (o *AXI_DMA_Type) SetIN_MEM_CONF_OUT_MEM_CLK_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetIN_MEM_CONF_OUT_MEM_CLK_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetIN_MEM_CONF_OUT_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetIN_MEM_CONF_OUT_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x10) >> 4 +} +func (o *AXI_DMA_Type) SetIN_MEM_CONF_OUT_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x20)|value<<5) +} +func (o *AXI_DMA_Type) GetIN_MEM_CONF_OUT_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x20) >> 5 +} + +// AXI_DMA.INTR_MEM_START_ADDR: The start address of accessible address space. +func (o *AXI_DMA_Type) SetINTR_MEM_START_ADDR(value uint32) { + volatile.StoreUint32(&o.INTR_MEM_START_ADDR.Reg, value) +} +func (o *AXI_DMA_Type) GetINTR_MEM_START_ADDR() uint32 { + return volatile.LoadUint32(&o.INTR_MEM_START_ADDR.Reg) +} + +// AXI_DMA.INTR_MEM_END_ADDR: The end address of accessible address space. The access address beyond this range would lead to descriptor error. +func (o *AXI_DMA_Type) SetINTR_MEM_END_ADDR(value uint32) { + volatile.StoreUint32(&o.INTR_MEM_END_ADDR.Reg, value) +} +func (o *AXI_DMA_Type) GetINTR_MEM_END_ADDR() uint32 { + return volatile.LoadUint32(&o.INTR_MEM_END_ADDR.Reg) +} + +// AXI_DMA.EXTR_MEM_START_ADDR: The start address of accessible address space. +func (o *AXI_DMA_Type) SetEXTR_MEM_START_ADDR(value uint32) { + volatile.StoreUint32(&o.EXTR_MEM_START_ADDR.Reg, value) +} +func (o *AXI_DMA_Type) GetEXTR_MEM_START_ADDR() uint32 { + return volatile.LoadUint32(&o.EXTR_MEM_START_ADDR.Reg) +} + +// AXI_DMA.EXTR_MEM_END_ADDR: The end address of accessible address space. The access address beyond this range would lead to descriptor error. +func (o *AXI_DMA_Type) SetEXTR_MEM_END_ADDR(value uint32) { + volatile.StoreUint32(&o.EXTR_MEM_END_ADDR.Reg, value) +} +func (o *AXI_DMA_Type) GetEXTR_MEM_END_ADDR() uint32 { + return volatile.LoadUint32(&o.EXTR_MEM_END_ADDR.Reg) +} + +// AXI_DMA.IN_RESET_AVAIL_CH0: The rx channel 0 reset valid_flag register. +func (o *AXI_DMA_Type) SetIN_RESET_AVAIL_CH0_IN_RESET_AVAIL_CH(value uint32) { + volatile.StoreUint32(&o.IN_RESET_AVAIL_CH0.Reg, volatile.LoadUint32(&o.IN_RESET_AVAIL_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_RESET_AVAIL_CH0_IN_RESET_AVAIL_CH() uint32 { + return volatile.LoadUint32(&o.IN_RESET_AVAIL_CH0.Reg) & 0x1 +} + +// AXI_DMA.IN_RESET_AVAIL_CH1: The rx channel 0 reset valid_flag register. +func (o *AXI_DMA_Type) SetIN_RESET_AVAIL_CH1_IN_RESET_AVAIL_CH(value uint32) { + volatile.StoreUint32(&o.IN_RESET_AVAIL_CH1.Reg, volatile.LoadUint32(&o.IN_RESET_AVAIL_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_RESET_AVAIL_CH1_IN_RESET_AVAIL_CH() uint32 { + return volatile.LoadUint32(&o.IN_RESET_AVAIL_CH1.Reg) & 0x1 +} + +// AXI_DMA.IN_RESET_AVAIL_CH2: The rx channel 0 reset valid_flag register. +func (o *AXI_DMA_Type) SetIN_RESET_AVAIL_CH2_IN_RESET_AVAIL_CH(value uint32) { + volatile.StoreUint32(&o.IN_RESET_AVAIL_CH2.Reg, volatile.LoadUint32(&o.IN_RESET_AVAIL_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetIN_RESET_AVAIL_CH2_IN_RESET_AVAIL_CH() uint32 { + return volatile.LoadUint32(&o.IN_RESET_AVAIL_CH2.Reg) & 0x1 +} + +// AXI_DMA.OUT_RESET_AVAIL_CH0: The tx channel 0 reset valid_flag register. +func (o *AXI_DMA_Type) SetOUT_RESET_AVAIL_CH0_OUT_RESET_AVAIL_CH(value uint32) { + volatile.StoreUint32(&o.OUT_RESET_AVAIL_CH0.Reg, volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH0.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_RESET_AVAIL_CH0_OUT_RESET_AVAIL_CH() uint32 { + return volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH0.Reg) & 0x1 +} + +// AXI_DMA.OUT_RESET_AVAIL_CH1: The tx channel 0 reset valid_flag register. +func (o *AXI_DMA_Type) SetOUT_RESET_AVAIL_CH1_OUT_RESET_AVAIL_CH(value uint32) { + volatile.StoreUint32(&o.OUT_RESET_AVAIL_CH1.Reg, volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH1.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_RESET_AVAIL_CH1_OUT_RESET_AVAIL_CH() uint32 { + return volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH1.Reg) & 0x1 +} + +// AXI_DMA.OUT_RESET_AVAIL_CH2: The tx channel 0 reset valid_flag register. +func (o *AXI_DMA_Type) SetOUT_RESET_AVAIL_CH2_OUT_RESET_AVAIL_CH(value uint32) { + volatile.StoreUint32(&o.OUT_RESET_AVAIL_CH2.Reg, volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH2.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetOUT_RESET_AVAIL_CH2_OUT_RESET_AVAIL_CH() uint32 { + return volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH2.Reg) & 0x1 +} + +// AXI_DMA.MISC_CONF: MISC register +func (o *AXI_DMA_Type) SetMISC_CONF_AXIM_RST_WR_INTER(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetMISC_CONF_AXIM_RST_WR_INTER() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetMISC_CONF_AXIM_RST_RD_INTER(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetMISC_CONF_AXIM_RST_RD_INTER() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x2) >> 1 +} +func (o *AXI_DMA_Type) SetMISC_CONF_ARB_PRI_DIS(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *AXI_DMA_Type) GetMISC_CONF_ARB_PRI_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x8) >> 3 +} +func (o *AXI_DMA_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x10)|value<<4) +} +func (o *AXI_DMA_Type) GetMISC_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x10) >> 4 +} + +// AXI_DMA.RDN_RESULT: reserved +func (o *AXI_DMA_Type) SetRDN_RESULT_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.RDN_RESULT.Reg, volatile.LoadUint32(&o.RDN_RESULT.Reg)&^(0x1)|value) +} +func (o *AXI_DMA_Type) GetRDN_RESULT_RDN_ENA() uint32 { + return volatile.LoadUint32(&o.RDN_RESULT.Reg) & 0x1 +} +func (o *AXI_DMA_Type) SetRDN_RESULT(value uint32) { + volatile.StoreUint32(&o.RDN_RESULT.Reg, volatile.LoadUint32(&o.RDN_RESULT.Reg)&^(0x2)|value<<1) +} +func (o *AXI_DMA_Type) GetRDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.RDN_RESULT.Reg) & 0x2) >> 1 +} + +// AXI_DMA.RDN_ECO_HIGH: reserved +func (o *AXI_DMA_Type) SetRDN_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_HIGH.Reg, value) +} +func (o *AXI_DMA_Type) GetRDN_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_HIGH.Reg) +} + +// AXI_DMA.RDN_ECO_LOW: reserved +func (o *AXI_DMA_Type) SetRDN_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_LOW.Reg, value) +} +func (o *AXI_DMA_Type) GetRDN_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_LOW.Reg) +} + +// AXI_DMA.WRESP_CNT: AXI wr responce cnt register. +func (o *AXI_DMA_Type) SetWRESP_CNT(value uint32) { + volatile.StoreUint32(&o.WRESP_CNT.Reg, volatile.LoadUint32(&o.WRESP_CNT.Reg)&^(0xf)|value) +} +func (o *AXI_DMA_Type) GetWRESP_CNT() uint32 { + return volatile.LoadUint32(&o.WRESP_CNT.Reg) & 0xf +} + +// AXI_DMA.RRESP_CNT: AXI wr responce cnt register. +func (o *AXI_DMA_Type) SetRRESP_CNT(value uint32) { + volatile.StoreUint32(&o.RRESP_CNT.Reg, volatile.LoadUint32(&o.RRESP_CNT.Reg)&^(0xf)|value) +} +func (o *AXI_DMA_Type) GetRRESP_CNT() uint32 { + return volatile.LoadUint32(&o.RRESP_CNT.Reg) & 0xf +} + +// AXI_DMA.INFIFO_STATUS1_CH0: Receive FIFO status of Rx channel 0 +func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH0_L1INFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS1_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH0.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH0_L1INFIFO_CNT_CH() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS1_CH0.Reg) & 0x3f +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH0_L2INFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS1_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH0.Reg)&^(0x3c0)|value<<6) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH0_L2INFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS1_CH0.Reg) & 0x3c0) >> 6 +} + +// AXI_DMA.INFIFO_STATUS1_CH1: Receive FIFO status of Rx channel 0 +func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH1_L1INFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS1_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH1.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH1_L1INFIFO_CNT_CH() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS1_CH1.Reg) & 0x3f +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH1_L2INFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS1_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH1.Reg)&^(0x3c0)|value<<6) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH1_L2INFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS1_CH1.Reg) & 0x3c0) >> 6 +} + +// AXI_DMA.INFIFO_STATUS1_CH2: Receive FIFO status of Rx channel 0 +func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH2_L1INFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS1_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH2.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH2_L1INFIFO_CNT_CH() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS1_CH2.Reg) & 0x3f +} +func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH2_L2INFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS1_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH2.Reg)&^(0x3c0)|value<<6) +} +func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH2_L2INFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS1_CH2.Reg) & 0x3c0) >> 6 +} + +// AXI_DMA.OUTFIFO_STATUS1_CH0: Receive FIFO status of Tx channel 0 +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH0_L1OUTFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH0.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH0_L1OUTFIFO_CNT_CH() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH0.Reg) & 0x3f +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH0_L2OUTFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH0.Reg)&^(0x3c0)|value<<6) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH0_L2OUTFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH0.Reg) & 0x3c0) >> 6 +} + +// AXI_DMA.OUTFIFO_STATUS1_CH1: Receive FIFO status of Tx channel 0 +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH1_L1OUTFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH1.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH1_L1OUTFIFO_CNT_CH() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH1.Reg) & 0x3f +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH1_L2OUTFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH1.Reg)&^(0x3c0)|value<<6) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH1_L2OUTFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH1.Reg) & 0x3c0) >> 6 +} + +// AXI_DMA.OUTFIFO_STATUS1_CH2: Receive FIFO status of Tx channel 0 +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH2_L1OUTFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH2.Reg)&^(0x3f)|value) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH2_L1OUTFIFO_CNT_CH() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH2.Reg) & 0x3f +} +func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH2_L2OUTFIFO_CNT_CH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH2.Reg)&^(0x3c0)|value<<6) +} +func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH2_L2OUTFIFO_CNT_CH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH2.Reg) & 0x3c0) >> 6 +} + +// AXI_DMA.DATE: Version control register +func (o *AXI_DMA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *AXI_DMA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// BITSCRAMBLER Peripheral +type BITSCRAMBLER_Type struct { + TX_INST_CFG0 volatile.Register32 // 0x0 + TX_INST_CFG1 volatile.Register32 // 0x4 + RX_INST_CFG0 volatile.Register32 // 0x8 + RX_INST_CFG1 volatile.Register32 // 0xC + TX_LUT_CFG0 volatile.Register32 // 0x10 + TX_LUT_CFG1 volatile.Register32 // 0x14 + RX_LUT_CFG0 volatile.Register32 // 0x18 + RX_LUT_CFG1 volatile.Register32 // 0x1C + TX_TAILING_BITS volatile.Register32 // 0x20 + RX_TAILING_BITS volatile.Register32 // 0x24 + TX_CTRL volatile.Register32 // 0x28 + RX_CTRL volatile.Register32 // 0x2C + TX_STATE volatile.Register32 // 0x30 + RX_STATE volatile.Register32 // 0x34 + _ [192]byte + SYS volatile.Register32 // 0xF8 + VERSION volatile.Register32 // 0xFC +} + +// BITSCRAMBLER.TX_INST_CFG0: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetTX_INST_CFG0_TX_INST_IDX(value uint32) { + volatile.StoreUint32(&o.TX_INST_CFG0.Reg, volatile.LoadUint32(&o.TX_INST_CFG0.Reg)&^(0x7)|value) +} +func (o *BITSCRAMBLER_Type) GetTX_INST_CFG0_TX_INST_IDX() uint32 { + return volatile.LoadUint32(&o.TX_INST_CFG0.Reg) & 0x7 +} +func (o *BITSCRAMBLER_Type) SetTX_INST_CFG0_TX_INST_POS(value uint32) { + volatile.StoreUint32(&o.TX_INST_CFG0.Reg, volatile.LoadUint32(&o.TX_INST_CFG0.Reg)&^(0x78)|value<<3) +} +func (o *BITSCRAMBLER_Type) GetTX_INST_CFG0_TX_INST_POS() uint32 { + return (volatile.LoadUint32(&o.TX_INST_CFG0.Reg) & 0x78) >> 3 +} + +// BITSCRAMBLER.TX_INST_CFG1: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetTX_INST_CFG1(value uint32) { + volatile.StoreUint32(&o.TX_INST_CFG1.Reg, value) +} +func (o *BITSCRAMBLER_Type) GetTX_INST_CFG1() uint32 { + return volatile.LoadUint32(&o.TX_INST_CFG1.Reg) +} + +// BITSCRAMBLER.RX_INST_CFG0: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetRX_INST_CFG0_RX_INST_IDX(value uint32) { + volatile.StoreUint32(&o.RX_INST_CFG0.Reg, volatile.LoadUint32(&o.RX_INST_CFG0.Reg)&^(0x7)|value) +} +func (o *BITSCRAMBLER_Type) GetRX_INST_CFG0_RX_INST_IDX() uint32 { + return volatile.LoadUint32(&o.RX_INST_CFG0.Reg) & 0x7 +} +func (o *BITSCRAMBLER_Type) SetRX_INST_CFG0_RX_INST_POS(value uint32) { + volatile.StoreUint32(&o.RX_INST_CFG0.Reg, volatile.LoadUint32(&o.RX_INST_CFG0.Reg)&^(0x78)|value<<3) +} +func (o *BITSCRAMBLER_Type) GetRX_INST_CFG0_RX_INST_POS() uint32 { + return (volatile.LoadUint32(&o.RX_INST_CFG0.Reg) & 0x78) >> 3 +} + +// BITSCRAMBLER.RX_INST_CFG1: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetRX_INST_CFG1(value uint32) { + volatile.StoreUint32(&o.RX_INST_CFG1.Reg, value) +} +func (o *BITSCRAMBLER_Type) GetRX_INST_CFG1() uint32 { + return volatile.LoadUint32(&o.RX_INST_CFG1.Reg) +} + +// BITSCRAMBLER.TX_LUT_CFG0: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetTX_LUT_CFG0_TX_LUT_IDX(value uint32) { + volatile.StoreUint32(&o.TX_LUT_CFG0.Reg, volatile.LoadUint32(&o.TX_LUT_CFG0.Reg)&^(0x7ff)|value) +} +func (o *BITSCRAMBLER_Type) GetTX_LUT_CFG0_TX_LUT_IDX() uint32 { + return volatile.LoadUint32(&o.TX_LUT_CFG0.Reg) & 0x7ff +} +func (o *BITSCRAMBLER_Type) SetTX_LUT_CFG0_TX_LUT_MODE(value uint32) { + volatile.StoreUint32(&o.TX_LUT_CFG0.Reg, volatile.LoadUint32(&o.TX_LUT_CFG0.Reg)&^(0x1800)|value<<11) +} +func (o *BITSCRAMBLER_Type) GetTX_LUT_CFG0_TX_LUT_MODE() uint32 { + return (volatile.LoadUint32(&o.TX_LUT_CFG0.Reg) & 0x1800) >> 11 +} + +// BITSCRAMBLER.TX_LUT_CFG1: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetTX_LUT_CFG1(value uint32) { + volatile.StoreUint32(&o.TX_LUT_CFG1.Reg, value) +} +func (o *BITSCRAMBLER_Type) GetTX_LUT_CFG1() uint32 { + return volatile.LoadUint32(&o.TX_LUT_CFG1.Reg) +} + +// BITSCRAMBLER.RX_LUT_CFG0: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetRX_LUT_CFG0_RX_LUT_IDX(value uint32) { + volatile.StoreUint32(&o.RX_LUT_CFG0.Reg, volatile.LoadUint32(&o.RX_LUT_CFG0.Reg)&^(0x7ff)|value) +} +func (o *BITSCRAMBLER_Type) GetRX_LUT_CFG0_RX_LUT_IDX() uint32 { + return volatile.LoadUint32(&o.RX_LUT_CFG0.Reg) & 0x7ff +} +func (o *BITSCRAMBLER_Type) SetRX_LUT_CFG0_RX_LUT_MODE(value uint32) { + volatile.StoreUint32(&o.RX_LUT_CFG0.Reg, volatile.LoadUint32(&o.RX_LUT_CFG0.Reg)&^(0x1800)|value<<11) +} +func (o *BITSCRAMBLER_Type) GetRX_LUT_CFG0_RX_LUT_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_LUT_CFG0.Reg) & 0x1800) >> 11 +} + +// BITSCRAMBLER.RX_LUT_CFG1: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetRX_LUT_CFG1(value uint32) { + volatile.StoreUint32(&o.RX_LUT_CFG1.Reg, value) +} +func (o *BITSCRAMBLER_Type) GetRX_LUT_CFG1() uint32 { + return volatile.LoadUint32(&o.RX_LUT_CFG1.Reg) +} + +// BITSCRAMBLER.TX_TAILING_BITS: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetTX_TAILING_BITS(value uint32) { + volatile.StoreUint32(&o.TX_TAILING_BITS.Reg, volatile.LoadUint32(&o.TX_TAILING_BITS.Reg)&^(0xffff)|value) +} +func (o *BITSCRAMBLER_Type) GetTX_TAILING_BITS() uint32 { + return volatile.LoadUint32(&o.TX_TAILING_BITS.Reg) & 0xffff +} + +// BITSCRAMBLER.RX_TAILING_BITS: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetRX_TAILING_BITS(value uint32) { + volatile.StoreUint32(&o.RX_TAILING_BITS.Reg, volatile.LoadUint32(&o.RX_TAILING_BITS.Reg)&^(0xffff)|value) +} +func (o *BITSCRAMBLER_Type) GetRX_TAILING_BITS() uint32 { + return volatile.LoadUint32(&o.RX_TAILING_BITS.Reg) & 0xffff +} + +// BITSCRAMBLER.TX_CTRL: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_ENA(value uint32) { + volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x1)|value) +} +func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_ENA() uint32 { + return volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x1 +} +func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_PAUSE(value uint32) { + volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x2) >> 1 +} +func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_HALT(value uint32) { + volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_HALT() uint32 { + return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x4) >> 2 +} +func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x8) >> 3 +} +func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_COND_MODE(value uint32) { + volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_COND_MODE() uint32 { + return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x10) >> 4 +} +func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_FETCH_MODE(value uint32) { + volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_FETCH_MODE() uint32 { + return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x20) >> 5 +} +func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_HALT_MODE(value uint32) { + volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_HALT_MODE() uint32 { + return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x40) >> 6 +} +func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_RD_DUMMY(value uint32) { + volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_RD_DUMMY() uint32 { + return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x80) >> 7 +} +func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x100) >> 8 +} + +// BITSCRAMBLER.RX_CTRL: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_ENA(value uint32) { + volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x1)|value) +} +func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_ENA() uint32 { + return volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x1 +} +func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_PAUSE(value uint32) { + volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_PAUSE() uint32 { + return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x2) >> 1 +} +func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_HALT(value uint32) { + volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_HALT() uint32 { + return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x4) >> 2 +} +func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x8) >> 3 +} +func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_COND_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_COND_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x10) >> 4 +} +func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_FETCH_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_FETCH_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x20) >> 5 +} +func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_HALT_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_HALT_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x40) >> 6 +} +func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_RD_DUMMY(value uint32) { + volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_RD_DUMMY() uint32 { + return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x80) >> 7 +} +func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x100) >> 8 +} + +// BITSCRAMBLER.TX_STATE: Status registers +func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_IN_IDLE(value uint32) { + volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x1)|value) +} +func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_IN_IDLE() uint32 { + return volatile.LoadUint32(&o.TX_STATE.Reg) & 0x1 +} +func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_IN_RUN(value uint32) { + volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x2)|value<<1) +} +func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_IN_RUN() uint32 { + return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x2) >> 1 +} +func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_IN_WAIT(value uint32) { + volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x4)|value<<2) +} +func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_IN_WAIT() uint32 { + return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x4) >> 2 +} +func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_IN_PAUSE(value uint32) { + volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x8)|value<<3) +} +func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_IN_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x8) >> 3 +} +func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x10)|value<<4) +} +func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x10) >> 4 +} +func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_EOF_GET_CNT(value uint32) { + volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_EOF_GET_CNT() uint32 { + return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x3fff0000) >> 16 +} +func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_EOF_OVERLOAD(value uint32) { + volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x40000000)|value<<30) +} +func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_EOF_OVERLOAD() uint32 { + return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x40000000) >> 30 +} +func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_EOF_TRACE_CLR(value uint32) { + volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x80000000)|value<<31) +} +func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_EOF_TRACE_CLR() uint32 { + return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x80000000) >> 31 +} + +// BITSCRAMBLER.RX_STATE: Status registers +func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_IN_IDLE(value uint32) { + volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x1)|value) +} +func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_IN_IDLE() uint32 { + return volatile.LoadUint32(&o.RX_STATE.Reg) & 0x1 +} +func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_IN_RUN(value uint32) { + volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x2)|value<<1) +} +func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_IN_RUN() uint32 { + return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x2) >> 1 +} +func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_IN_WAIT(value uint32) { + volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x4)|value<<2) +} +func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_IN_WAIT() uint32 { + return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x4) >> 2 +} +func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_IN_PAUSE(value uint32) { + volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x8)|value<<3) +} +func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_IN_PAUSE() uint32 { + return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x8) >> 3 +} +func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x10)|value<<4) +} +func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x10) >> 4 +} +func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_EOF_GET_CNT(value uint32) { + volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_EOF_GET_CNT() uint32 { + return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x3fff0000) >> 16 +} +func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_EOF_OVERLOAD(value uint32) { + volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x40000000)|value<<30) +} +func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_EOF_OVERLOAD() uint32 { + return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x40000000) >> 30 +} +func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_EOF_TRACE_CLR(value uint32) { + volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x80000000)|value<<31) +} +func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_EOF_TRACE_CLR() uint32 { + return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x80000000) >> 31 +} + +// BITSCRAMBLER.SYS: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetSYS_LOOP_MODE(value uint32) { + volatile.StoreUint32(&o.SYS.Reg, volatile.LoadUint32(&o.SYS.Reg)&^(0x1)|value) +} +func (o *BITSCRAMBLER_Type) GetSYS_LOOP_MODE() uint32 { + return volatile.LoadUint32(&o.SYS.Reg) & 0x1 +} +func (o *BITSCRAMBLER_Type) SetSYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYS.Reg, volatile.LoadUint32(&o.SYS.Reg)&^(0x80000000)|value<<31) +} +func (o *BITSCRAMBLER_Type) GetSYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYS.Reg) & 0x80000000) >> 31 +} + +// BITSCRAMBLER.VERSION: Control and configuration registers +func (o *BITSCRAMBLER_Type) SetVERSION_BITSCRAMBLER_VER(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *BITSCRAMBLER_Type) GetVERSION_BITSCRAMBLER_VER() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// CACHE Peripheral +type CACHE_Type struct { + L1_ICACHE_CTRL volatile.Register32 // 0x0 + L1_DCACHE_CTRL volatile.Register32 // 0x4 + L1_BYPASS_CACHE_CONF volatile.Register32 // 0x8 + L1_CACHE_ATOMIC_CONF volatile.Register32 // 0xC + L1_ICACHE_CACHESIZE_CONF volatile.Register32 // 0x10 + L1_ICACHE_BLOCKSIZE_CONF volatile.Register32 // 0x14 + L1_DCACHE_CACHESIZE_CONF volatile.Register32 // 0x18 + L1_DCACHE_BLOCKSIZE_CONF volatile.Register32 // 0x1C + L1_CACHE_WRAP_AROUND_CTRL volatile.Register32 // 0x20 + L1_CACHE_TAG_MEM_POWER_CTRL volatile.Register32 // 0x24 + L1_CACHE_DATA_MEM_POWER_CTRL volatile.Register32 // 0x28 + L1_CACHE_FREEZE_CTRL volatile.Register32 // 0x2C + L1_CACHE_DATA_MEM_ACS_CONF volatile.Register32 // 0x30 + L1_CACHE_TAG_MEM_ACS_CONF volatile.Register32 // 0x34 + L1_ICACHE0_PRELOCK_CONF volatile.Register32 // 0x38 + L1_ICACHE0_PRELOCK_SCT0_ADDR volatile.Register32 // 0x3C + L1_ICACHE0_PRELOCK_SCT1_ADDR volatile.Register32 // 0x40 + L1_ICACHE0_PRELOCK_SCT_SIZE volatile.Register32 // 0x44 + L1_ICACHE1_PRELOCK_CONF volatile.Register32 // 0x48 + L1_ICACHE1_PRELOCK_SCT0_ADDR volatile.Register32 // 0x4C + L1_ICACHE1_PRELOCK_SCT1_ADDR volatile.Register32 // 0x50 + L1_ICACHE1_PRELOCK_SCT_SIZE volatile.Register32 // 0x54 + L1_ICACHE2_PRELOCK_CONF volatile.Register32 // 0x58 + L1_ICACHE2_PRELOCK_SCT0_ADDR volatile.Register32 // 0x5C + L1_ICACHE2_PRELOCK_SCT1_ADDR volatile.Register32 // 0x60 + L1_ICACHE2_PRELOCK_SCT_SIZE volatile.Register32 // 0x64 + L1_ICACHE3_PRELOCK_CONF volatile.Register32 // 0x68 + L1_ICACHE3_PRELOCK_SCT0_ADDR volatile.Register32 // 0x6C + L1_ICACHE3_PRELOCK_SCT1_ADDR volatile.Register32 // 0x70 + L1_ICACHE3_PRELOCK_SCT_SIZE volatile.Register32 // 0x74 + L1_DCACHE_PRELOCK_CONF volatile.Register32 // 0x78 + L1_DCACHE_PRELOCK_SCT0_ADDR volatile.Register32 // 0x7C + L1_DCACHE_PRELOCK_SCT1_ADDR volatile.Register32 // 0x80 + L1_DCACHE_PRELOCK_SCT_SIZE volatile.Register32 // 0x84 + LOCK_CTRL volatile.Register32 // 0x88 + LOCK_MAP volatile.Register32 // 0x8C + LOCK_ADDR volatile.Register32 // 0x90 + LOCK_SIZE volatile.Register32 // 0x94 + SYNC_CTRL volatile.Register32 // 0x98 + SYNC_MAP volatile.Register32 // 0x9C + SYNC_ADDR volatile.Register32 // 0xA0 + SYNC_SIZE volatile.Register32 // 0xA4 + L1_ICACHE0_PRELOAD_CTRL volatile.Register32 // 0xA8 + L1_ICACHE0_PRELOAD_ADDR volatile.Register32 // 0xAC + L1_ICACHE0_PRELOAD_SIZE volatile.Register32 // 0xB0 + L1_ICACHE1_PRELOAD_CTRL volatile.Register32 // 0xB4 + L1_ICACHE1_PRELOAD_ADDR volatile.Register32 // 0xB8 + L1_ICACHE1_PRELOAD_SIZE volatile.Register32 // 0xBC + L1_ICACHE2_PRELOAD_CTRL volatile.Register32 // 0xC0 + L1_ICACHE2_PRELOAD_ADDR volatile.Register32 // 0xC4 + L1_ICACHE2_PRELOAD_SIZE volatile.Register32 // 0xC8 + L1_ICACHE3_PRELOAD_CTRL volatile.Register32 // 0xCC + L1_ICACHE3_PRELOAD_ADDR volatile.Register32 // 0xD0 + L1_ICACHE3_PRELOAD_SIZE volatile.Register32 // 0xD4 + L1_DCACHE_PRELOAD_CTRL volatile.Register32 // 0xD8 + L1_DCACHE_PRELOAD_ADDR volatile.Register32 // 0xDC + L1_DCACHE_PRELOAD_SIZE volatile.Register32 // 0xE0 + L1_ICACHE0_AUTOLOAD_CTRL volatile.Register32 // 0xE4 + L1_ICACHE0_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0xE8 + L1_ICACHE0_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0xEC + L1_ICACHE0_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0xF0 + L1_ICACHE0_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0xF4 + L1_ICACHE1_AUTOLOAD_CTRL volatile.Register32 // 0xF8 + L1_ICACHE1_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0xFC + L1_ICACHE1_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x100 + L1_ICACHE1_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x104 + L1_ICACHE1_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x108 + L1_ICACHE2_AUTOLOAD_CTRL volatile.Register32 // 0x10C + L1_ICACHE2_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x110 + L1_ICACHE2_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x114 + L1_ICACHE2_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x118 + L1_ICACHE2_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x11C + L1_ICACHE3_AUTOLOAD_CTRL volatile.Register32 // 0x120 + L1_ICACHE3_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x124 + L1_ICACHE3_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x128 + L1_ICACHE3_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x12C + L1_ICACHE3_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x130 + L1_DCACHE_AUTOLOAD_CTRL volatile.Register32 // 0x134 + L1_DCACHE_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x138 + L1_DCACHE_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x13C + L1_DCACHE_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x140 + L1_DCACHE_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x144 + L1_DCACHE_AUTOLOAD_SCT2_ADDR volatile.Register32 // 0x148 + L1_DCACHE_AUTOLOAD_SCT2_SIZE volatile.Register32 // 0x14C + L1_DCACHE_AUTOLOAD_SCT3_ADDR volatile.Register32 // 0x150 + L1_DCACHE_AUTOLOAD_SCT3_SIZE volatile.Register32 // 0x154 + L1_CACHE_ACS_CNT_INT_ENA volatile.Register32 // 0x158 + L1_CACHE_ACS_CNT_INT_CLR volatile.Register32 // 0x15C + L1_CACHE_ACS_CNT_INT_RAW volatile.Register32 // 0x160 + L1_CACHE_ACS_CNT_INT_ST volatile.Register32 // 0x164 + L1_CACHE_ACS_FAIL_CTRL volatile.Register32 // 0x168 + L1_CACHE_ACS_FAIL_INT_ENA volatile.Register32 // 0x16C + L1_CACHE_ACS_FAIL_INT_CLR volatile.Register32 // 0x170 + L1_CACHE_ACS_FAIL_INT_RAW volatile.Register32 // 0x174 + L1_CACHE_ACS_FAIL_INT_ST volatile.Register32 // 0x178 + L1_CACHE_ACS_CNT_CTRL volatile.Register32 // 0x17C + L1_IBUS0_ACS_HIT_CNT volatile.Register32 // 0x180 + L1_IBUS0_ACS_MISS_CNT volatile.Register32 // 0x184 + L1_IBUS0_ACS_CONFLICT_CNT volatile.Register32 // 0x188 + L1_IBUS0_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x18C + L1_IBUS1_ACS_HIT_CNT volatile.Register32 // 0x190 + L1_IBUS1_ACS_MISS_CNT volatile.Register32 // 0x194 + L1_IBUS1_ACS_CONFLICT_CNT volatile.Register32 // 0x198 + L1_IBUS1_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x19C + L1_IBUS2_ACS_HIT_CNT volatile.Register32 // 0x1A0 + L1_IBUS2_ACS_MISS_CNT volatile.Register32 // 0x1A4 + L1_IBUS2_ACS_CONFLICT_CNT volatile.Register32 // 0x1A8 + L1_IBUS2_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x1AC + L1_IBUS3_ACS_HIT_CNT volatile.Register32 // 0x1B0 + L1_IBUS3_ACS_MISS_CNT volatile.Register32 // 0x1B4 + L1_IBUS3_ACS_CONFLICT_CNT volatile.Register32 // 0x1B8 + L1_IBUS3_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x1BC + L1_DBUS0_ACS_HIT_CNT volatile.Register32 // 0x1C0 + L1_DBUS0_ACS_MISS_CNT volatile.Register32 // 0x1C4 + L1_DBUS0_ACS_CONFLICT_CNT volatile.Register32 // 0x1C8 + L1_DBUS0_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x1CC + L1_DBUS0_ACS_NXTLVL_WR_CNT volatile.Register32 // 0x1D0 + L1_DBUS1_ACS_HIT_CNT volatile.Register32 // 0x1D4 + L1_DBUS1_ACS_MISS_CNT volatile.Register32 // 0x1D8 + L1_DBUS1_ACS_CONFLICT_CNT volatile.Register32 // 0x1DC + L1_DBUS1_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x1E0 + L1_DBUS1_ACS_NXTLVL_WR_CNT volatile.Register32 // 0x1E4 + L1_DBUS2_ACS_HIT_CNT volatile.Register32 // 0x1E8 + L1_DBUS2_ACS_MISS_CNT volatile.Register32 // 0x1EC + L1_DBUS2_ACS_CONFLICT_CNT volatile.Register32 // 0x1F0 + L1_DBUS2_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x1F4 + L1_DBUS2_ACS_NXTLVL_WR_CNT volatile.Register32 // 0x1F8 + L1_DBUS3_ACS_HIT_CNT volatile.Register32 // 0x1FC + L1_DBUS3_ACS_MISS_CNT volatile.Register32 // 0x200 + L1_DBUS3_ACS_CONFLICT_CNT volatile.Register32 // 0x204 + L1_DBUS3_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x208 + L1_DBUS3_ACS_NXTLVL_WR_CNT volatile.Register32 // 0x20C + L1_ICACHE0_ACS_FAIL_ID_ATTR volatile.Register32 // 0x210 + L1_ICACHE0_ACS_FAIL_ADDR volatile.Register32 // 0x214 + L1_ICACHE1_ACS_FAIL_ID_ATTR volatile.Register32 // 0x218 + L1_ICACHE1_ACS_FAIL_ADDR volatile.Register32 // 0x21C + L1_ICACHE2_ACS_FAIL_ID_ATTR volatile.Register32 // 0x220 + L1_ICACHE2_ACS_FAIL_ADDR volatile.Register32 // 0x224 + L1_ICACHE3_ACS_FAIL_ID_ATTR volatile.Register32 // 0x228 + L1_ICACHE3_ACS_FAIL_ADDR volatile.Register32 // 0x22C + L1_DCACHE_ACS_FAIL_ID_ATTR volatile.Register32 // 0x230 + L1_DCACHE_ACS_FAIL_ADDR volatile.Register32 // 0x234 + SYNC_L1_CACHE_PRELOAD_INT_ENA volatile.Register32 // 0x238 + SYNC_L1_CACHE_PRELOAD_INT_CLR volatile.Register32 // 0x23C + SYNC_L1_CACHE_PRELOAD_INT_RAW volatile.Register32 // 0x240 + SYNC_L1_CACHE_PRELOAD_INT_ST volatile.Register32 // 0x244 + SYNC_L1_CACHE_PRELOAD_EXCEPTION volatile.Register32 // 0x248 + L1_CACHE_SYNC_RST_CTRL volatile.Register32 // 0x24C + L1_CACHE_PRELOAD_RST_CTRL volatile.Register32 // 0x250 + L1_CACHE_AUTOLOAD_BUF_CLR_CTRL volatile.Register32 // 0x254 + L1_UNALLOCATE_BUFFER_CLEAR volatile.Register32 // 0x258 + L1_CACHE_OBJECT_CTRL volatile.Register32 // 0x25C + L1_CACHE_WAY_OBJECT volatile.Register32 // 0x260 + L1_CACHE_VADDR volatile.Register32 // 0x264 + L1_CACHE_DEBUG_BUS volatile.Register32 // 0x268 + LEVEL_SPLIT0 volatile.Register32 // 0x26C + L2_CACHE_CTRL volatile.Register32 // 0x270 + L2_BYPASS_CACHE_CONF volatile.Register32 // 0x274 + L2_CACHE_CACHESIZE_CONF volatile.Register32 // 0x278 + L2_CACHE_BLOCKSIZE_CONF volatile.Register32 // 0x27C + L2_CACHE_WRAP_AROUND_CTRL volatile.Register32 // 0x280 + L2_CACHE_TAG_MEM_POWER_CTRL volatile.Register32 // 0x284 + L2_CACHE_DATA_MEM_POWER_CTRL volatile.Register32 // 0x288 + L2_CACHE_FREEZE_CTRL volatile.Register32 // 0x28C + L2_CACHE_DATA_MEM_ACS_CONF volatile.Register32 // 0x290 + L2_CACHE_TAG_MEM_ACS_CONF volatile.Register32 // 0x294 + L2_CACHE_PRELOCK_CONF volatile.Register32 // 0x298 + L2_CACHE_PRELOCK_SCT0_ADDR volatile.Register32 // 0x29C + L2_CACHE_PRELOCK_SCT1_ADDR volatile.Register32 // 0x2A0 + L2_CACHE_PRELOCK_SCT_SIZE volatile.Register32 // 0x2A4 + L2_CACHE_PRELOAD_CTRL volatile.Register32 // 0x2A8 + L2_CACHE_PRELOAD_ADDR volatile.Register32 // 0x2AC + L2_CACHE_PRELOAD_SIZE volatile.Register32 // 0x2B0 + L2_CACHE_AUTOLOAD_CTRL volatile.Register32 // 0x2B4 + L2_CACHE_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x2B8 + L2_CACHE_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x2BC + L2_CACHE_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x2C0 + L2_CACHE_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x2C4 + L2_CACHE_AUTOLOAD_SCT2_ADDR volatile.Register32 // 0x2C8 + L2_CACHE_AUTOLOAD_SCT2_SIZE volatile.Register32 // 0x2CC + L2_CACHE_AUTOLOAD_SCT3_ADDR volatile.Register32 // 0x2D0 + L2_CACHE_AUTOLOAD_SCT3_SIZE volatile.Register32 // 0x2D4 + L2_CACHE_ACS_CNT_INT_ENA volatile.Register32 // 0x2D8 + L2_CACHE_ACS_CNT_INT_CLR volatile.Register32 // 0x2DC + L2_CACHE_ACS_CNT_INT_RAW volatile.Register32 // 0x2E0 + L2_CACHE_ACS_CNT_INT_ST volatile.Register32 // 0x2E4 + L2_CACHE_ACS_FAIL_CTRL volatile.Register32 // 0x2E8 + L2_CACHE_ACS_FAIL_INT_ENA volatile.Register32 // 0x2EC + L2_CACHE_ACS_FAIL_INT_CLR volatile.Register32 // 0x2F0 + L2_CACHE_ACS_FAIL_INT_RAW volatile.Register32 // 0x2F4 + L2_CACHE_ACS_FAIL_INT_ST volatile.Register32 // 0x2F8 + L2_CACHE_ACS_CNT_CTRL volatile.Register32 // 0x2FC + L2_IBUS0_ACS_HIT_CNT volatile.Register32 // 0x300 + L2_IBUS0_ACS_MISS_CNT volatile.Register32 // 0x304 + L2_IBUS0_ACS_CONFLICT_CNT volatile.Register32 // 0x308 + L2_IBUS0_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x30C + L2_IBUS1_ACS_HIT_CNT volatile.Register32 // 0x310 + L2_IBUS1_ACS_MISS_CNT volatile.Register32 // 0x314 + L2_IBUS1_ACS_CONFLICT_CNT volatile.Register32 // 0x318 + L2_IBUS1_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x31C + L2_IBUS2_ACS_HIT_CNT volatile.Register32 // 0x320 + L2_IBUS2_ACS_MISS_CNT volatile.Register32 // 0x324 + L2_IBUS2_ACS_CONFLICT_CNT volatile.Register32 // 0x328 + L2_IBUS2_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x32C + L2_IBUS3_ACS_HIT_CNT volatile.Register32 // 0x330 + L2_IBUS3_ACS_MISS_CNT volatile.Register32 // 0x334 + L2_IBUS3_ACS_CONFLICT_CNT volatile.Register32 // 0x338 + L2_IBUS3_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x33C + L2_DBUS0_ACS_HIT_CNT volatile.Register32 // 0x340 + L2_DBUS0_ACS_MISS_CNT volatile.Register32 // 0x344 + L2_DBUS0_ACS_CONFLICT_CNT volatile.Register32 // 0x348 + L2_DBUS0_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x34C + L2_DBUS0_ACS_NXTLVL_WR_CNT volatile.Register32 // 0x350 + L2_DBUS1_ACS_HIT_CNT volatile.Register32 // 0x354 + L2_DBUS1_ACS_MISS_CNT volatile.Register32 // 0x358 + L2_DBUS1_ACS_CONFLICT_CNT volatile.Register32 // 0x35C + L2_DBUS1_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x360 + L2_DBUS1_ACS_NXTLVL_WR_CNT volatile.Register32 // 0x364 + L2_DBUS2_ACS_HIT_CNT volatile.Register32 // 0x368 + L2_DBUS2_ACS_MISS_CNT volatile.Register32 // 0x36C + L2_DBUS2_ACS_CONFLICT_CNT volatile.Register32 // 0x370 + L2_DBUS2_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x374 + L2_DBUS2_ACS_NXTLVL_WR_CNT volatile.Register32 // 0x378 + L2_DBUS3_ACS_HIT_CNT volatile.Register32 // 0x37C + L2_DBUS3_ACS_MISS_CNT volatile.Register32 // 0x380 + L2_DBUS3_ACS_CONFLICT_CNT volatile.Register32 // 0x384 + L2_DBUS3_ACS_NXTLVL_RD_CNT volatile.Register32 // 0x388 + L2_DBUS3_ACS_NXTLVL_WR_CNT volatile.Register32 // 0x38C + L2_CACHE_ACS_FAIL_ID_ATTR volatile.Register32 // 0x390 + L2_CACHE_ACS_FAIL_ADDR volatile.Register32 // 0x394 + L2_CACHE_SYNC_PRELOAD_INT_ENA volatile.Register32 // 0x398 + L2_CACHE_SYNC_PRELOAD_INT_CLR volatile.Register32 // 0x39C + L2_CACHE_SYNC_PRELOAD_INT_RAW volatile.Register32 // 0x3A0 + L2_CACHE_SYNC_PRELOAD_INT_ST volatile.Register32 // 0x3A4 + L2_CACHE_SYNC_PRELOAD_EXCEPTION volatile.Register32 // 0x3A8 + L2_CACHE_SYNC_RST_CTRL volatile.Register32 // 0x3AC + L2_CACHE_PRELOAD_RST_CTRL volatile.Register32 // 0x3B0 + L2_CACHE_AUTOLOAD_BUF_CLR_CTRL volatile.Register32 // 0x3B4 + L2_UNALLOCATE_BUFFER_CLEAR volatile.Register32 // 0x3B8 + L2_CACHE_ACCESS_ATTR_CTRL volatile.Register32 // 0x3BC + L2_CACHE_OBJECT_CTRL volatile.Register32 // 0x3C0 + L2_CACHE_WAY_OBJECT volatile.Register32 // 0x3C4 + L2_CACHE_VADDR volatile.Register32 // 0x3C8 + L2_CACHE_DEBUG_BUS volatile.Register32 // 0x3CC + LEVEL_SPLIT1 volatile.Register32 // 0x3D0 + CLOCK_GATE volatile.Register32 // 0x3D4 + REDUNDANCY_SIG0 volatile.Register32 // 0x3D8 + REDUNDANCY_SIG1 volatile.Register32 // 0x3DC + REDUNDANCY_SIG2 volatile.Register32 // 0x3E0 + REDUNDANCY_SIG3 volatile.Register32 // 0x3E4 + REDUNDANCY_SIG4 volatile.Register32 // 0x3E8 + _ [16]byte + DATE volatile.Register32 // 0x3FC +} + +// CACHE.L1_ICACHE_CTRL: L1 instruction Cache(L1-ICache) control register +func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0xff00) >> 8 +} + +// CACHE.L1_DCACHE_CTRL: L1 data Cache(L1-DCache) control register +func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS0(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS0() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS1(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS1() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS2(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS2() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS3(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS3() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DMA(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DMA() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_UNDEF_OP(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_UNDEF_OP() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0xff00) >> 8 +} + +// CACHE.L1_BYPASS_CACHE_CONF: Bypass Cache configure register +func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN() uint32 { + return volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN() uint32 { + return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN() uint32 { + return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN(value uint32) { + volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_ATOMIC_CONF: L1 Cache atomic feature configure register +func (o *CACHE_Type) SetL1_CACHE_ATOMIC_CONF_L1_DCACHE_ATOMIC_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ATOMIC_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_ATOMIC_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ATOMIC_CONF_L1_DCACHE_ATOMIC_EN() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ATOMIC_CONF.Reg) & 0x1 +} + +// CACHE.L1_ICACHE_CACHESIZE_CONF: L1 instruction Cache CacheSize mode configure register +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x80) >> 7 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x1000) >> 12 +} + +// CACHE.L1_ICACHE_BLOCKSIZE_CONF: L1 instruction Cache BlockSize mode configure register +func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x20) >> 5 +} + +// CACHE.L1_DCACHE_CACHESIZE_CONF: L1 data Cache CacheSize mode configure register +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_2K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_2K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_4K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_4K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_8K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_8K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_16K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_16K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_32K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_32K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x80) >> 7 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_64K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_64K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_128K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_128K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1024K(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1024K() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x1000) >> 12 +} + +// CACHE.L1_DCACHE_BLOCKSIZE_CONF: L1 data Cache BlockSize mode configure register +func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_8(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_8() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_16(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_16() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_32(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_32() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_64(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_64() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_128(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_128() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_256(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_256() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x20) >> 5 +} + +// CACHE.L1_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register +func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_DCACHE_WRAP(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_DCACHE_WRAP() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x4000) >> 14 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x10000) >> 16 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x20000) >> 17 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x40000) >> 18 +} + +// CACHE.L1_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x4000) >> 14 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x10000) >> 16 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x20000) >> 17 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x40000) >> 18 +} + +// CACHE.L1_CACHE_FREEZE_CTRL: Cache Freeze control register +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x4000) >> 14 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x10000) >> 16 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x20000) >> 17 +} +func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x40000) >> 18 +} + +// CACHE.L1_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x10000) >> 16 +} +func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x20000) >> 17 +} + +// CACHE.L1_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x10000) >> 16 +} +func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x20000) >> 17 +} + +// CACHE.L1_ICACHE0_PRELOCK_CONF: L1 instruction Cache 0 prelock configure register +func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// CACHE.L1_ICACHE0_PRELOCK_SCT0_ADDR: L1 instruction Cache 0 prelock section0 address configure register +func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT0_ADDR.Reg) +} + +// CACHE.L1_ICACHE0_PRELOCK_SCT1_ADDR: L1 instruction Cache 0 prelock section1 address configure register +func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT1_ADDR.Reg) +} + +// CACHE.L1_ICACHE0_PRELOCK_SCT_SIZE: L1 instruction Cache 0 prelock section size configure register +func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// CACHE.L1_ICACHE1_PRELOCK_CONF: L1 instruction Cache 1 prelock configure register +func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// CACHE.L1_ICACHE1_PRELOCK_SCT0_ADDR: L1 instruction Cache 1 prelock section0 address configure register +func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT0_ADDR.Reg) +} + +// CACHE.L1_ICACHE1_PRELOCK_SCT1_ADDR: L1 instruction Cache 1 prelock section1 address configure register +func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT1_ADDR.Reg) +} + +// CACHE.L1_ICACHE1_PRELOCK_SCT_SIZE: L1 instruction Cache 1 prelock section size configure register +func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// CACHE.L1_ICACHE2_PRELOCK_CONF: L1 instruction Cache 2 prelock configure register +func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// CACHE.L1_ICACHE2_PRELOCK_SCT0_ADDR: L1 instruction Cache 2 prelock section0 address configure register +func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT0_ADDR.Reg) +} + +// CACHE.L1_ICACHE2_PRELOCK_SCT1_ADDR: L1 instruction Cache 2 prelock section1 address configure register +func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT1_ADDR.Reg) +} + +// CACHE.L1_ICACHE2_PRELOCK_SCT_SIZE: L1 instruction Cache 2 prelock section size configure register +func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// CACHE.L1_ICACHE3_PRELOCK_CONF: L1 instruction Cache 3 prelock configure register +func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// CACHE.L1_ICACHE3_PRELOCK_SCT0_ADDR: L1 instruction Cache 3 prelock section0 address configure register +func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT0_ADDR.Reg) +} + +// CACHE.L1_ICACHE3_PRELOCK_SCT1_ADDR: L1 instruction Cache 3 prelock section1 address configure register +func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT1_ADDR.Reg) +} + +// CACHE.L1_ICACHE3_PRELOCK_SCT_SIZE: L1 instruction Cache 3 prelock section size configure register +func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// CACHE.L1_DCACHE_PRELOCK_CONF: L1 data Cache prelock configure register +func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// CACHE.L1_DCACHE_PRELOCK_SCT0_ADDR: L1 data Cache prelock section0 address configure register +func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT0_ADDR.Reg) +} + +// CACHE.L1_DCACHE_PRELOCK_SCT1_ADDR: L1 data Cache prelock section1 address configure register +func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT1_ADDR.Reg) +} + +// CACHE.L1_DCACHE_PRELOCK_SCT_SIZE: L1 data Cache prelock section size configure register +func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg) & 0x3fff +} +func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16 +} + +// CACHE.LOCK_CTRL: Lock-class (manual lock) operation control register +func (o *CACHE_Type) SetLOCK_CTRL_LOCK_ENA(value uint32) { + volatile.StoreUint32(&o.LOCK_CTRL.Reg, volatile.LoadUint32(&o.LOCK_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetLOCK_CTRL_LOCK_ENA() uint32 { + return volatile.LoadUint32(&o.LOCK_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetLOCK_CTRL_UNLOCK_ENA(value uint32) { + volatile.StoreUint32(&o.LOCK_CTRL.Reg, volatile.LoadUint32(&o.LOCK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetLOCK_CTRL_UNLOCK_ENA() uint32 { + return (volatile.LoadUint32(&o.LOCK_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetLOCK_CTRL_LOCK_DONE(value uint32) { + volatile.StoreUint32(&o.LOCK_CTRL.Reg, volatile.LoadUint32(&o.LOCK_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetLOCK_CTRL_LOCK_DONE() uint32 { + return (volatile.LoadUint32(&o.LOCK_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetLOCK_CTRL_LOCK_RGID(value uint32) { + volatile.StoreUint32(&o.LOCK_CTRL.Reg, volatile.LoadUint32(&o.LOCK_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *CACHE_Type) GetLOCK_CTRL_LOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.LOCK_CTRL.Reg) & 0x78) >> 3 +} + +// CACHE.LOCK_MAP: Lock (manual lock) map configure register +func (o *CACHE_Type) SetLOCK_MAP(value uint32) { + volatile.StoreUint32(&o.LOCK_MAP.Reg, volatile.LoadUint32(&o.LOCK_MAP.Reg)&^(0x3f)|value) +} +func (o *CACHE_Type) GetLOCK_MAP() uint32 { + return volatile.LoadUint32(&o.LOCK_MAP.Reg) & 0x3f +} + +// CACHE.LOCK_ADDR: Lock (manual lock) address configure register +func (o *CACHE_Type) SetLOCK_ADDR(value uint32) { + volatile.StoreUint32(&o.LOCK_ADDR.Reg, value) +} +func (o *CACHE_Type) GetLOCK_ADDR() uint32 { + return volatile.LoadUint32(&o.LOCK_ADDR.Reg) +} + +// CACHE.LOCK_SIZE: Lock (manual lock) size configure register +func (o *CACHE_Type) SetLOCK_SIZE(value uint32) { + volatile.StoreUint32(&o.LOCK_SIZE.Reg, volatile.LoadUint32(&o.LOCK_SIZE.Reg)&^(0xffff)|value) +} +func (o *CACHE_Type) GetLOCK_SIZE() uint32 { + return volatile.LoadUint32(&o.LOCK_SIZE.Reg) & 0xffff +} + +// CACHE.SYNC_CTRL: Sync-class operation control register +func (o *CACHE_Type) SetSYNC_CTRL_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetSYNC_CTRL_INVALIDATE_ENA() uint32 { + return volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetSYNC_CTRL_CLEAN_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetSYNC_CTRL_CLEAN_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetSYNC_CTRL_WRITEBACK_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetSYNC_CTRL_WRITEBACK_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetSYNC_CTRL_WRITEBACK_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetSYNC_CTRL_WRITEBACK_INVALIDATE_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetSYNC_CTRL_SYNC_DONE(value uint32) { + volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetSYNC_CTRL_SYNC_DONE() uint32 { + return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetSYNC_CTRL_SYNC_RGID(value uint32) { + volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x1e0)|value<<5) +} +func (o *CACHE_Type) GetSYNC_CTRL_SYNC_RGID() uint32 { + return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x1e0) >> 5 +} + +// CACHE.SYNC_MAP: Sync map configure register +func (o *CACHE_Type) SetSYNC_MAP(value uint32) { + volatile.StoreUint32(&o.SYNC_MAP.Reg, volatile.LoadUint32(&o.SYNC_MAP.Reg)&^(0x3f)|value) +} +func (o *CACHE_Type) GetSYNC_MAP() uint32 { + return volatile.LoadUint32(&o.SYNC_MAP.Reg) & 0x3f +} + +// CACHE.SYNC_ADDR: Sync address configure register +func (o *CACHE_Type) SetSYNC_ADDR(value uint32) { + volatile.StoreUint32(&o.SYNC_ADDR.Reg, value) +} +func (o *CACHE_Type) GetSYNC_ADDR() uint32 { + return volatile.LoadUint32(&o.SYNC_ADDR.Reg) +} + +// CACHE.SYNC_SIZE: Sync size configure register +func (o *CACHE_Type) SetSYNC_SIZE(value uint32) { + volatile.StoreUint32(&o.SYNC_SIZE.Reg, volatile.LoadUint32(&o.SYNC_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetSYNC_SIZE() uint32 { + return volatile.LoadUint32(&o.SYNC_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_ICACHE0_PRELOAD_CTRL: L1 instruction Cache 0 preload-operation control register +func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// CACHE.L1_ICACHE0_PRELOAD_ADDR: L1 instruction Cache 0 preload address configure register +func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_ADDR.Reg) +} + +// CACHE.L1_ICACHE0_PRELOAD_SIZE: L1 instruction Cache 0 preload size configure register +func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_SIZE.Reg) & 0x3fff +} + +// CACHE.L1_ICACHE1_PRELOAD_CTRL: L1 instruction Cache 1 preload-operation control register +func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// CACHE.L1_ICACHE1_PRELOAD_ADDR: L1 instruction Cache 1 preload address configure register +func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_ADDR.Reg) +} + +// CACHE.L1_ICACHE1_PRELOAD_SIZE: L1 instruction Cache 1 preload size configure register +func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_SIZE.Reg) & 0x3fff +} + +// CACHE.L1_ICACHE2_PRELOAD_CTRL: L1 instruction Cache 2 preload-operation control register +func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// CACHE.L1_ICACHE2_PRELOAD_ADDR: L1 instruction Cache 2 preload address configure register +func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_ADDR.Reg) +} + +// CACHE.L1_ICACHE2_PRELOAD_SIZE: L1 instruction Cache 2 preload size configure register +func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_SIZE.Reg) & 0x3fff +} + +// CACHE.L1_ICACHE3_PRELOAD_CTRL: L1 instruction Cache 3 preload-operation control register +func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// CACHE.L1_ICACHE3_PRELOAD_ADDR: L1 instruction Cache 3 preload address configure register +func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_ADDR.Reg) +} + +// CACHE.L1_ICACHE3_PRELOAD_SIZE: L1 instruction Cache 3 preload size configure register +func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_SIZE.Reg) & 0x3fff +} + +// CACHE.L1_DCACHE_PRELOAD_CTRL: L1 data Cache preload-operation control register +func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// CACHE.L1_DCACHE_PRELOAD_ADDR: L1 data Cache preload address configure register +func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_ADDR.Reg) +} + +// CACHE.L1_DCACHE_PRELOAD_SIZE: L1 data Cache preload size configure register +func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_SIZE.Reg)&^(0x3fff)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_SIZE.Reg) & 0x3fff +} + +// CACHE.L1_ICACHE0_AUTOLOAD_CTRL: L1 instruction Cache 0 autoload-operation control register +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10 +} + +// CACHE.L1_ICACHE0_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 0 autoload section 0 address configure register +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_ADDR.Reg) +} + +// CACHE.L1_ICACHE0_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 0 autoload section 0 size configure register +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_ICACHE0_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 0 autoload section 1 address configure register +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_ADDR.Reg) +} + +// CACHE.L1_ICACHE0_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 0 autoload section 1 size configure register +func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_ICACHE1_AUTOLOAD_CTRL: L1 instruction Cache 1 autoload-operation control register +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10 +} + +// CACHE.L1_ICACHE1_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 1 autoload section 0 address configure register +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_ADDR.Reg) +} + +// CACHE.L1_ICACHE1_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 1 autoload section 0 size configure register +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_ICACHE1_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 1 autoload section 1 address configure register +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_ADDR.Reg) +} + +// CACHE.L1_ICACHE1_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 1 autoload section 1 size configure register +func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_ICACHE2_AUTOLOAD_CTRL: L1 instruction Cache 2 autoload-operation control register +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10 +} + +// CACHE.L1_ICACHE2_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 2 autoload section 0 address configure register +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_ADDR.Reg) +} + +// CACHE.L1_ICACHE2_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 2 autoload section 0 size configure register +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_ICACHE2_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 2 autoload section 1 address configure register +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_ADDR.Reg) +} + +// CACHE.L1_ICACHE2_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 2 autoload section 1 size configure register +func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_ICACHE3_AUTOLOAD_CTRL: L1 instruction Cache 3 autoload-operation control register +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10 +} + +// CACHE.L1_ICACHE3_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 3 autoload section 0 address configure register +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_ADDR.Reg) +} + +// CACHE.L1_ICACHE3_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 3 autoload section 0 size configure register +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_ICACHE3_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 3 autoload section 1 address configure register +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_ADDR.Reg) +} + +// CACHE.L1_ICACHE3_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 3 autoload section 1 size configure register +func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_DCACHE_AUTOLOAD_CTRL: L1 data Cache autoload-operation control register +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT2_ENA(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT2_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT3_ENA(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT3_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0xf000)|value<<12) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0xf000) >> 12 +} + +// CACHE.L1_DCACHE_AUTOLOAD_SCT0_ADDR: L1 data Cache autoload section 0 address configure register +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_ADDR.Reg) +} + +// CACHE.L1_DCACHE_AUTOLOAD_SCT0_SIZE: L1 data Cache autoload section 0 size configure register +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_DCACHE_AUTOLOAD_SCT1_ADDR: L1 data Cache autoload section 1 address configure register +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_ADDR.Reg) +} + +// CACHE.L1_DCACHE_AUTOLOAD_SCT1_SIZE: L1 data Cache autoload section 1 size configure register +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_DCACHE_AUTOLOAD_SCT2_ADDR: L1 data Cache autoload section 2 address configure register +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT2_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT2_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_ADDR.Reg) +} + +// CACHE.L1_DCACHE_AUTOLOAD_SCT2_SIZE: L1 data Cache autoload section 2 size configure register +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT2_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT2_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_DCACHE_AUTOLOAD_SCT3_ADDR: L1 data Cache autoload section 1 address configure register +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT3_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT3_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_ADDR.Reg) +} + +// CACHE.L1_DCACHE_AUTOLOAD_SCT3_SIZE: L1 data Cache autoload section 1 size configure register +func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT3_SIZE(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT3_SIZE() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_SIZE.Reg) & 0xfffffff +} + +// CACHE.L1_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS0_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x80) >> 7 +} + +// CACHE.L1_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS0_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x80) >> 7 +} + +// CACHE.L1_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS0_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x80) >> 7 +} + +// CACHE.L1_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS0_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x80) >> 7 +} + +// CACHE.L1_CACHE_ACS_FAIL_CTRL: Cache Access Fail Configuration register +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE0_ACS_FAIL_CHECK_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE0_ACS_FAIL_CHECK_MODE() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE1_ACS_FAIL_CHECK_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE1_ACS_FAIL_CHECK_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE2_ACS_FAIL_CHECK_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE2_ACS_FAIL_CHECK_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE3_ACS_FAIL_CHECK_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE3_ACS_FAIL_CHECK_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_DCACHE_ACS_FAIL_CHECK_MODE(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_DCACHE_ACS_FAIL_CHECK_MODE() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_DCACHE_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_DCACHE_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_DCACHE_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_DCACHE_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_DCACHE_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_DCACHE_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_DCACHE_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_DCACHE_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x80) >> 7 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x10000) >> 16 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x20000) >> 17 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x40000) >> 18 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x80000) >> 19 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x100000) >> 20 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x200000) >> 21 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x400000) >> 22 +} +func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x800000) >> 23 +} + +// CACHE.L1_IBUS0_ACS_HIT_CNT: L1-ICache bus0 Hit-Access Counter register +func (o *CACHE_Type) SetL1_IBUS0_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS0_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS0_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS0_ACS_HIT_CNT.Reg) +} + +// CACHE.L1_IBUS0_ACS_MISS_CNT: L1-ICache bus0 Miss-Access Counter register +func (o *CACHE_Type) SetL1_IBUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS0_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS0_ACS_MISS_CNT.Reg) +} + +// CACHE.L1_IBUS0_ACS_CONFLICT_CNT: L1-ICache bus0 Conflict-Access Counter register +func (o *CACHE_Type) SetL1_IBUS0_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS0_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS0_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS0_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L1_IBUS0_ACS_NXTLVL_RD_CNT: L1-ICache bus0 Next-Level-Access Counter register +func (o *CACHE_Type) SetL1_IBUS0_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS0_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS0_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS0_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L1_IBUS1_ACS_HIT_CNT: L1-ICache bus1 Hit-Access Counter register +func (o *CACHE_Type) SetL1_IBUS1_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS1_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS1_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS1_ACS_HIT_CNT.Reg) +} + +// CACHE.L1_IBUS1_ACS_MISS_CNT: L1-ICache bus1 Miss-Access Counter register +func (o *CACHE_Type) SetL1_IBUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS1_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS1_ACS_MISS_CNT.Reg) +} + +// CACHE.L1_IBUS1_ACS_CONFLICT_CNT: L1-ICache bus1 Conflict-Access Counter register +func (o *CACHE_Type) SetL1_IBUS1_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS1_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS1_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS1_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L1_IBUS1_ACS_NXTLVL_RD_CNT: L1-ICache bus1 Next-Level-Access Counter register +func (o *CACHE_Type) SetL1_IBUS1_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS1_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS1_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS1_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L1_IBUS2_ACS_HIT_CNT: L1-ICache bus2 Hit-Access Counter register +func (o *CACHE_Type) SetL1_IBUS2_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS2_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS2_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS2_ACS_HIT_CNT.Reg) +} + +// CACHE.L1_IBUS2_ACS_MISS_CNT: L1-ICache bus2 Miss-Access Counter register +func (o *CACHE_Type) SetL1_IBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS2_ACS_MISS_CNT.Reg) +} + +// CACHE.L1_IBUS2_ACS_CONFLICT_CNT: L1-ICache bus2 Conflict-Access Counter register +func (o *CACHE_Type) SetL1_IBUS2_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS2_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS2_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS2_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L1_IBUS2_ACS_NXTLVL_RD_CNT: L1-ICache bus2 Next-Level-Access Counter register +func (o *CACHE_Type) SetL1_IBUS2_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS2_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS2_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS2_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L1_IBUS3_ACS_HIT_CNT: L1-ICache bus3 Hit-Access Counter register +func (o *CACHE_Type) SetL1_IBUS3_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS3_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS3_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS3_ACS_HIT_CNT.Reg) +} + +// CACHE.L1_IBUS3_ACS_MISS_CNT: L1-ICache bus3 Miss-Access Counter register +func (o *CACHE_Type) SetL1_IBUS3_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS3_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS3_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS3_ACS_MISS_CNT.Reg) +} + +// CACHE.L1_IBUS3_ACS_CONFLICT_CNT: L1-ICache bus3 Conflict-Access Counter register +func (o *CACHE_Type) SetL1_IBUS3_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS3_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS3_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS3_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L1_IBUS3_ACS_NXTLVL_RD_CNT: L1-ICache bus3 Next-Level-Access Counter register +func (o *CACHE_Type) SetL1_IBUS3_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L1_IBUS3_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_IBUS3_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L1_IBUS3_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L1_DBUS0_ACS_HIT_CNT: L1-DCache bus0 Hit-Access Counter register +func (o *CACHE_Type) SetL1_DBUS0_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS0_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS0_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS0_ACS_HIT_CNT.Reg) +} + +// CACHE.L1_DBUS0_ACS_MISS_CNT: L1-DCache bus0 Miss-Access Counter register +func (o *CACHE_Type) SetL1_DBUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS0_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS0_ACS_MISS_CNT.Reg) +} + +// CACHE.L1_DBUS0_ACS_CONFLICT_CNT: L1-DCache bus0 Conflict-Access Counter register +func (o *CACHE_Type) SetL1_DBUS0_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS0_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS0_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS0_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L1_DBUS0_ACS_NXTLVL_RD_CNT: L1-DCache bus0 Next-Level-Access Counter register +func (o *CACHE_Type) SetL1_DBUS0_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS0_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS0_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS0_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L1_DBUS0_ACS_NXTLVL_WR_CNT: L1-DCache bus0 WB-Access Counter register +func (o *CACHE_Type) SetL1_DBUS0_ACS_NXTLVL_WR_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS0_ACS_NXTLVL_WR_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS0_ACS_NXTLVL_WR_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS0_ACS_NXTLVL_WR_CNT.Reg) +} + +// CACHE.L1_DBUS1_ACS_HIT_CNT: L1-DCache bus1 Hit-Access Counter register +func (o *CACHE_Type) SetL1_DBUS1_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS1_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS1_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS1_ACS_HIT_CNT.Reg) +} + +// CACHE.L1_DBUS1_ACS_MISS_CNT: L1-DCache bus1 Miss-Access Counter register +func (o *CACHE_Type) SetL1_DBUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS1_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS1_ACS_MISS_CNT.Reg) +} + +// CACHE.L1_DBUS1_ACS_CONFLICT_CNT: L1-DCache bus1 Conflict-Access Counter register +func (o *CACHE_Type) SetL1_DBUS1_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS1_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS1_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS1_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L1_DBUS1_ACS_NXTLVL_RD_CNT: L1-DCache bus1 Next-Level-Access Counter register +func (o *CACHE_Type) SetL1_DBUS1_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS1_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS1_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS1_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L1_DBUS1_ACS_NXTLVL_WR_CNT: L1-DCache bus1 WB-Access Counter register +func (o *CACHE_Type) SetL1_DBUS1_ACS_NXTLVL_WR_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS1_ACS_NXTLVL_WR_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS1_ACS_NXTLVL_WR_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS1_ACS_NXTLVL_WR_CNT.Reg) +} + +// CACHE.L1_DBUS2_ACS_HIT_CNT: L1-DCache bus2 Hit-Access Counter register +func (o *CACHE_Type) SetL1_DBUS2_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS2_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS2_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS2_ACS_HIT_CNT.Reg) +} + +// CACHE.L1_DBUS2_ACS_MISS_CNT: L1-DCache bus2 Miss-Access Counter register +func (o *CACHE_Type) SetL1_DBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS2_ACS_MISS_CNT.Reg) +} + +// CACHE.L1_DBUS2_ACS_CONFLICT_CNT: L1-DCache bus2 Conflict-Access Counter register +func (o *CACHE_Type) SetL1_DBUS2_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS2_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS2_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS2_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L1_DBUS2_ACS_NXTLVL_RD_CNT: L1-DCache bus2 Next-Level-Access Counter register +func (o *CACHE_Type) SetL1_DBUS2_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS2_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS2_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS2_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L1_DBUS2_ACS_NXTLVL_WR_CNT: L1-DCache bus2 WB-Access Counter register +func (o *CACHE_Type) SetL1_DBUS2_ACS_NXTLVL_WR_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS2_ACS_NXTLVL_WR_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS2_ACS_NXTLVL_WR_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS2_ACS_NXTLVL_WR_CNT.Reg) +} + +// CACHE.L1_DBUS3_ACS_HIT_CNT: L1-DCache bus3 Hit-Access Counter register +func (o *CACHE_Type) SetL1_DBUS3_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS3_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS3_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS3_ACS_HIT_CNT.Reg) +} + +// CACHE.L1_DBUS3_ACS_MISS_CNT: L1-DCache bus3 Miss-Access Counter register +func (o *CACHE_Type) SetL1_DBUS3_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS3_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS3_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS3_ACS_MISS_CNT.Reg) +} + +// CACHE.L1_DBUS3_ACS_CONFLICT_CNT: L1-DCache bus3 Conflict-Access Counter register +func (o *CACHE_Type) SetL1_DBUS3_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS3_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS3_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS3_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L1_DBUS3_ACS_NXTLVL_RD_CNT: L1-DCache bus3 Next-Level-Access Counter register +func (o *CACHE_Type) SetL1_DBUS3_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS3_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS3_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS3_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L1_DBUS3_ACS_NXTLVL_WR_CNT: L1-DCache bus3 WB-Access Counter register +func (o *CACHE_Type) SetL1_DBUS3_ACS_NXTLVL_WR_CNT(value uint32) { + volatile.StoreUint32(&o.L1_DBUS3_ACS_NXTLVL_WR_CNT.Reg, value) +} +func (o *CACHE_Type) GetL1_DBUS3_ACS_NXTLVL_WR_CNT() uint32 { + return volatile.LoadUint32(&o.L1_DBUS3_ACS_NXTLVL_WR_CNT.Reg) +} + +// CACHE.L1_ICACHE0_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register +func (o *CACHE_Type) SetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *CACHE_Type) SetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// CACHE.L1_ICACHE0_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register +func (o *CACHE_Type) SetL1_ICACHE0_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE0_ACS_FAIL_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE0_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ADDR.Reg) +} + +// CACHE.L1_ICACHE1_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register +func (o *CACHE_Type) SetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *CACHE_Type) SetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// CACHE.L1_ICACHE1_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register +func (o *CACHE_Type) SetL1_ICACHE1_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE1_ACS_FAIL_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE1_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ADDR.Reg) +} + +// CACHE.L1_ICACHE2_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register +func (o *CACHE_Type) SetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *CACHE_Type) SetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// CACHE.L1_ICACHE2_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register +func (o *CACHE_Type) SetL1_ICACHE2_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE2_ACS_FAIL_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE2_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ADDR.Reg) +} + +// CACHE.L1_ICACHE3_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register +func (o *CACHE_Type) SetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *CACHE_Type) GetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *CACHE_Type) SetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// CACHE.L1_ICACHE3_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register +func (o *CACHE_Type) SetL1_ICACHE3_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_ICACHE3_ACS_FAIL_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_ICACHE3_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ADDR.Reg) +} + +// CACHE.L1_DCACHE_ACS_FAIL_ID_ATTR: L1-DCache Access Fail ID/attribution information register +func (o *CACHE_Type) SetL1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *CACHE_Type) GetL1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *CACHE_Type) SetL1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *CACHE_Type) GetL1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// CACHE.L1_DCACHE_ACS_FAIL_ADDR: L1-DCache Access Fail Address information register +func (o *CACHE_Type) SetL1_DCACHE_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L1_DCACHE_ACS_FAIL_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_DCACHE_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ADDR.Reg) +} + +// CACHE.SYNC_L1_CACHE_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x1 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x2000) >> 13 +} + +// CACHE.SYNC_L1_CACHE_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x1 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x2000) >> 13 +} + +// CACHE.SYNC_L1_CACHE_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x1 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x2000) >> 13 +} + +// CACHE.SYNC_L1_CACHE_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x1 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x80) >> 7 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x2000) >> 13 +} + +// CACHE.SYNC_L1_CACHE_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0x3)|value) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE() uint32 { + return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0x3 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0xc)|value<<2) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0xc) >> 2 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0x30)|value<<4) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0x30) >> 4 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0xc0)|value<<6) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0xc0) >> 6 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_DCACHE_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0x300)|value<<8) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_DCACHE_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0x300) >> 8 +} +func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_SYNC_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0x3000)|value<<12) +} +func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_SYNC_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0x3000) >> 12 +} + +// CACHE.L1_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register +func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_DCACHE_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_DCACHE_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register +func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_DCACHE_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_DCACHE_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register +func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_DCACHE_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_DCACHE_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x10) >> 4 +} + +// CACHE.L1_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers +func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR() uint32 { + return volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_DCACHE_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_DCACHE_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x10) >> 4 +} + +// CACHE.L1_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_DCACHE_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_DCACHE_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x80) >> 7 +} +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_DCACHE_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_DCACHE_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x400) >> 10 +} + +// CACHE.L1_CACHE_WAY_OBJECT: Cache Tag and Data memory way register +func (o *CACHE_Type) SetL1_CACHE_WAY_OBJECT(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_WAY_OBJECT.Reg, volatile.LoadUint32(&o.L1_CACHE_WAY_OBJECT.Reg)&^(0x7)|value) +} +func (o *CACHE_Type) GetL1_CACHE_WAY_OBJECT() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_WAY_OBJECT.Reg) & 0x7 +} + +// CACHE.L1_CACHE_VADDR: Cache Vaddr register +func (o *CACHE_Type) SetL1_CACHE_VADDR(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_VADDR.Reg, value) +} +func (o *CACHE_Type) GetL1_CACHE_VADDR() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_VADDR.Reg) +} + +// CACHE.L1_CACHE_DEBUG_BUS: Cache Tag/data memory content register +func (o *CACHE_Type) SetL1_CACHE_DEBUG_BUS(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_DEBUG_BUS.Reg, value) +} +func (o *CACHE_Type) GetL1_CACHE_DEBUG_BUS() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_DEBUG_BUS.Reg) +} + +// CACHE.LEVEL_SPLIT0: USED TO SPLIT L1 CACHE AND L2 CACHE +func (o *CACHE_Type) SetLEVEL_SPLIT0(value uint32) { + volatile.StoreUint32(&o.LEVEL_SPLIT0.Reg, value) +} +func (o *CACHE_Type) GetLEVEL_SPLIT0() uint32 { + return volatile.LoadUint32(&o.LEVEL_SPLIT0.Reg) +} + +// CACHE.L2_CACHE_CTRL: L2 Cache(L2-Cache) control register +func (o *CACHE_Type) SetL2_CACHE_CTRL_L2_CACHE_SHUT_DMA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL2_CACHE_CTRL_L2_CACHE_SHUT_DMA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL2_CACHE_CTRL_L2_CACHE_UNDEF_OP(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *CACHE_Type) GetL2_CACHE_CTRL_L2_CACHE_UNDEF_OP() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg) & 0xff00) >> 8 +} + +// CACHE.L2_BYPASS_CACHE_CONF: Bypass Cache configure register +func (o *CACHE_Type) SetL2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN(value uint32) { + volatile.StoreUint32(&o.L2_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L2_BYPASS_CACHE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN() uint32 { + return (volatile.LoadUint32(&o.L2_BYPASS_CACHE_CONF.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_CACHESIZE_CONF: L2 Cache CacheSize mode configure register +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x40) >> 6 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x80) >> 7 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x1000) >> 12 +} + +// CACHE.L2_CACHE_BLOCKSIZE_CONF: L2 Cache BlockSize mode configure register +func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x8) >> 3 +} +func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x10) >> 4 +} +func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register +func (o *CACHE_Type) SetL2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_WRAP_AROUND_CTRL.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register +func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x100000) >> 20 +} +func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x200000) >> 21 +} +func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x400000) >> 22 +} + +// CACHE.L2_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register +func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x100000) >> 20 +} +func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x200000) >> 21 +} +func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x400000) >> 22 +} + +// CACHE.L2_CACHE_FREEZE_CTRL: Cache Freeze control register +func (o *CACHE_Type) SetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *CACHE_Type) GetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg) & 0x100000) >> 20 +} +func (o *CACHE_Type) SetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *CACHE_Type) GetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg) & 0x200000) >> 21 +} +func (o *CACHE_Type) SetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *CACHE_Type) GetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg) & 0x400000) >> 22 +} + +// CACHE.L2_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register +func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x100000) >> 20 +} +func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x200000) >> 21 +} + +// CACHE.L2_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register +func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x100000) >> 20 +} +func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x200000) >> 21 +} + +// CACHE.L2_CACHE_PRELOCK_CONF: L2 Cache prelock configure register +func (o *CACHE_Type) SetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg) & 0x1 +} +func (o *CACHE_Type) SetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg)&^(0x3c)|value<<2) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg) & 0x3c) >> 2 +} + +// CACHE.L2_CACHE_PRELOCK_SCT0_ADDR: L2 Cache prelock section0 address configure register +func (o *CACHE_Type) SetL2_CACHE_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT0_ADDR.Reg) +} + +// CACHE.L2_CACHE_PRELOCK_SCT1_ADDR: L2 Cache prelock section1 address configure register +func (o *CACHE_Type) SetL2_CACHE_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT1_ADDR.Reg) +} + +// CACHE.L2_CACHE_PRELOCK_SCT_SIZE: L2 Cache prelock section size configure register +func (o *CACHE_Type) SetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff)|value) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff +} +func (o *CACHE_Type) SetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff0000)|value<<16) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff0000) >> 16 +} + +// CACHE.L2_CACHE_PRELOAD_CTRL: L2 Cache preload-operation control register +func (o *CACHE_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x78)|value<<3) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x78) >> 3 +} + +// CACHE.L2_CACHE_PRELOAD_ADDR: L2 Cache preload address configure register +func (o *CACHE_Type) SetL2_CACHE_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOAD_ADDR.Reg) +} + +// CACHE.L2_CACHE_PRELOAD_SIZE: L2 Cache preload size configure register +func (o *CACHE_Type) SetL2_CACHE_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_SIZE.Reg)&^(0xffff)|value) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PRELOAD_SIZE.Reg) & 0xffff +} + +// CACHE.L2_CACHE_AUTOLOAD_CTRL: L2 Cache autoload-operation control register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x18) >> 3 +} +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0xf000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0xf000) >> 12 +} + +// CACHE.L2_CACHE_AUTOLOAD_SCT0_ADDR: L2 Cache autoload section 0 address configure register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT0_ADDR.Reg) +} + +// CACHE.L2_CACHE_AUTOLOAD_SCT0_SIZE: L2 Cache autoload section 0 size configure register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff +} + +// CACHE.L2_CACHE_AUTOLOAD_SCT1_ADDR: L2 Cache autoload section 1 address configure register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT1_ADDR.Reg) +} + +// CACHE.L2_CACHE_AUTOLOAD_SCT1_SIZE: L2 Cache autoload section 1 size configure register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff +} + +// CACHE.L2_CACHE_AUTOLOAD_SCT2_ADDR: L2 Cache autoload section 2 address configure register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT2_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT2_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT2_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT2_ADDR.Reg) +} + +// CACHE.L2_CACHE_AUTOLOAD_SCT2_SIZE: L2 Cache autoload section 2 size configure register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT2_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT2_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT2_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT2_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT2_SIZE.Reg) & 0xfffffff +} + +// CACHE.L2_CACHE_AUTOLOAD_SCT3_ADDR: L2 Cache autoload section 3 address configure register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT3_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT3_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT3_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT3_ADDR.Reg) +} + +// CACHE.L2_CACHE_AUTOLOAD_SCT3_SIZE: L2 Cache autoload section 3 size configure register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT3_SIZE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT3_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT3_SIZE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT3_SIZE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT3_SIZE.Reg) & 0xfffffff +} + +// CACHE.L2_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x8000) >> 15 +} + +// CACHE.L2_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x8000) >> 15 +} + +// CACHE.L2_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x8000) >> 15 +} + +// CACHE.L2_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x8000) >> 15 +} + +// CACHE.L2_CACHE_ACS_FAIL_CTRL: Cache Access Fail Configuration register +func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_CTRL_L2_CACHE_ACS_FAIL_CHECK_MODE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_CTRL_L2_CACHE_ACS_FAIL_CHECK_MODE() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_CTRL.Reg) & 0x1 +} + +// CACHE.L2_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register +func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register +func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register +func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register +func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ST.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x100) >> 8 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x200) >> 9 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x400) >> 10 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x800) >> 11 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x1000) >> 12 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x2000) >> 13 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x4000) >> 14 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x8000) >> 15 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x80000000) >> 31 +} + +// CACHE.L2_IBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register +func (o *CACHE_Type) SetL2_IBUS0_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS0_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS0_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS0_ACS_HIT_CNT.Reg) +} + +// CACHE.L2_IBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register +func (o *CACHE_Type) SetL2_IBUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS0_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS0_ACS_MISS_CNT.Reg) +} + +// CACHE.L2_IBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register +func (o *CACHE_Type) SetL2_IBUS0_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS0_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS0_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS0_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L2_IBUS0_ACS_NXTLVL_RD_CNT: L2-Cache bus0 Next-Level-Access Counter register +func (o *CACHE_Type) SetL2_IBUS0_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS0_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS0_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS0_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L2_IBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register +func (o *CACHE_Type) SetL2_IBUS1_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS1_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS1_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS1_ACS_HIT_CNT.Reg) +} + +// CACHE.L2_IBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register +func (o *CACHE_Type) SetL2_IBUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS1_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS1_ACS_MISS_CNT.Reg) +} + +// CACHE.L2_IBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register +func (o *CACHE_Type) SetL2_IBUS1_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS1_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS1_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS1_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L2_IBUS1_ACS_NXTLVL_RD_CNT: L2-Cache bus1 Next-Level-Access Counter register +func (o *CACHE_Type) SetL2_IBUS1_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS1_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS1_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS1_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L2_IBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register +func (o *CACHE_Type) SetL2_IBUS2_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS2_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS2_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS2_ACS_HIT_CNT.Reg) +} + +// CACHE.L2_IBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register +func (o *CACHE_Type) SetL2_IBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS2_ACS_MISS_CNT.Reg) +} + +// CACHE.L2_IBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register +func (o *CACHE_Type) SetL2_IBUS2_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS2_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS2_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS2_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L2_IBUS2_ACS_NXTLVL_RD_CNT: L2-Cache bus2 Next-Level-Access Counter register +func (o *CACHE_Type) SetL2_IBUS2_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS2_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS2_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS2_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L2_IBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register +func (o *CACHE_Type) SetL2_IBUS3_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS3_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS3_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS3_ACS_HIT_CNT.Reg) +} + +// CACHE.L2_IBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register +func (o *CACHE_Type) SetL2_IBUS3_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS3_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS3_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS3_ACS_MISS_CNT.Reg) +} + +// CACHE.L2_IBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register +func (o *CACHE_Type) SetL2_IBUS3_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS3_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS3_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS3_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L2_IBUS3_ACS_NXTLVL_RD_CNT: L2-Cache bus3 Next-Level-Access Counter register +func (o *CACHE_Type) SetL2_IBUS3_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L2_IBUS3_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_IBUS3_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L2_IBUS3_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L2_DBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register +func (o *CACHE_Type) SetL2_DBUS0_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS0_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS0_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS0_ACS_HIT_CNT.Reg) +} + +// CACHE.L2_DBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register +func (o *CACHE_Type) SetL2_DBUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS0_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS0_ACS_MISS_CNT.Reg) +} + +// CACHE.L2_DBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register +func (o *CACHE_Type) SetL2_DBUS0_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS0_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS0_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS0_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L2_DBUS0_ACS_NXTLVL_RD_CNT: L2-Cache bus0 Next-Level-Access Counter register +func (o *CACHE_Type) SetL2_DBUS0_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS0_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS0_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS0_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L2_DBUS0_ACS_NXTLVL_WR_CNT: L2-Cache bus0 WB-Access Counter register +func (o *CACHE_Type) SetL2_DBUS0_ACS_NXTLVL_WR_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS0_ACS_NXTLVL_WR_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS0_ACS_NXTLVL_WR_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS0_ACS_NXTLVL_WR_CNT.Reg) +} + +// CACHE.L2_DBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register +func (o *CACHE_Type) SetL2_DBUS1_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS1_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS1_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS1_ACS_HIT_CNT.Reg) +} + +// CACHE.L2_DBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register +func (o *CACHE_Type) SetL2_DBUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS1_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS1_ACS_MISS_CNT.Reg) +} + +// CACHE.L2_DBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register +func (o *CACHE_Type) SetL2_DBUS1_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS1_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS1_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS1_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L2_DBUS1_ACS_NXTLVL_RD_CNT: L2-Cache bus1 Next-Level-Access Counter register +func (o *CACHE_Type) SetL2_DBUS1_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS1_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS1_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS1_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L2_DBUS1_ACS_NXTLVL_WR_CNT: L2-Cache bus1 WB-Access Counter register +func (o *CACHE_Type) SetL2_DBUS1_ACS_NXTLVL_WR_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS1_ACS_NXTLVL_WR_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS1_ACS_NXTLVL_WR_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS1_ACS_NXTLVL_WR_CNT.Reg) +} + +// CACHE.L2_DBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register +func (o *CACHE_Type) SetL2_DBUS2_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS2_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS2_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS2_ACS_HIT_CNT.Reg) +} + +// CACHE.L2_DBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register +func (o *CACHE_Type) SetL2_DBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS2_ACS_MISS_CNT.Reg) +} + +// CACHE.L2_DBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register +func (o *CACHE_Type) SetL2_DBUS2_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS2_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS2_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS2_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L2_DBUS2_ACS_NXTLVL_RD_CNT: L2-Cache bus2 Next-Level-Access Counter register +func (o *CACHE_Type) SetL2_DBUS2_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS2_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS2_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS2_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L2_DBUS2_ACS_NXTLVL_WR_CNT: L2-Cache bus2 WB-Access Counter register +func (o *CACHE_Type) SetL2_DBUS2_ACS_NXTLVL_WR_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS2_ACS_NXTLVL_WR_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS2_ACS_NXTLVL_WR_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS2_ACS_NXTLVL_WR_CNT.Reg) +} + +// CACHE.L2_DBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register +func (o *CACHE_Type) SetL2_DBUS3_ACS_HIT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS3_ACS_HIT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS3_ACS_HIT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS3_ACS_HIT_CNT.Reg) +} + +// CACHE.L2_DBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register +func (o *CACHE_Type) SetL2_DBUS3_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS3_ACS_MISS_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS3_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS3_ACS_MISS_CNT.Reg) +} + +// CACHE.L2_DBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register +func (o *CACHE_Type) SetL2_DBUS3_ACS_CONFLICT_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS3_ACS_CONFLICT_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS3_ACS_CONFLICT_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS3_ACS_CONFLICT_CNT.Reg) +} + +// CACHE.L2_DBUS3_ACS_NXTLVL_RD_CNT: L2-Cache bus3 Next-Level-Access Counter register +func (o *CACHE_Type) SetL2_DBUS3_ACS_NXTLVL_RD_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS3_ACS_NXTLVL_RD_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS3_ACS_NXTLVL_RD_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS3_ACS_NXTLVL_RD_CNT.Reg) +} + +// CACHE.L2_DBUS3_ACS_NXTLVL_WR_CNT: L2-Cache bus3 WB-Access Counter register +func (o *CACHE_Type) SetL2_DBUS3_ACS_NXTLVL_WR_CNT(value uint32) { + volatile.StoreUint32(&o.L2_DBUS3_ACS_NXTLVL_WR_CNT.Reg, value) +} +func (o *CACHE_Type) GetL2_DBUS3_ACS_NXTLVL_WR_CNT() uint32 { + return volatile.LoadUint32(&o.L2_DBUS3_ACS_NXTLVL_WR_CNT.Reg) +} + +// CACHE.L2_CACHE_ACS_FAIL_ID_ATTR: L2-Cache Access Fail ID/attribution information register +func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff +} +func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16 +} + +// CACHE.L2_CACHE_ACS_FAIL_ADDR: L2-Cache Access Fail Address information register +func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_ADDR.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ADDR.Reg) +} + +// CACHE.L2_CACHE_SYNC_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register +func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x1000) >> 12 +} + +// CACHE.L2_CACHE_SYNC_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register +func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x1000) >> 12 +} + +// CACHE.L2_CACHE_SYNC_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register +func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x1000) >> 12 +} + +// CACHE.L2_CACHE_SYNC_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register +func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x1000) >> 12 +} + +// CACHE.L2_CACHE_SYNC_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register +func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_EXCEPTION.Reg)&^(0xc00)|value<<10) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_EXCEPTION.Reg) & 0xc00) >> 10 +} + +// CACHE.L2_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register +func (o *CACHE_Type) SetL2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_RST_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_SYNC_RST_CTRL.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register +func (o *CACHE_Type) SetL2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_RST_CTRL.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register +func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x20) >> 5 +} + +// CACHE.L2_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers +func (o *CACHE_Type) SetL2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR(value uint32) { + volatile.StoreUint32(&o.L2_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L2_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x20) >> 5 +} + +// CACHE.L2_CACHE_ACCESS_ATTR_CTRL: L2 cache access attribute control register +func (o *CACHE_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x1 +} +func (o *CACHE_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CACHE_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x2) >> 1 +} +func (o *CACHE_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CACHE_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x4) >> 2 +} +func (o *CACHE_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *CACHE_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x8) >> 3 +} + +// CACHE.L2_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register +func (o *CACHE_Type) SetL2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *CACHE_Type) GetL2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg) & 0x20) >> 5 +} +func (o *CACHE_Type) SetL2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *CACHE_Type) GetL2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT() uint32 { + return (volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg) & 0x800) >> 11 +} + +// CACHE.L2_CACHE_WAY_OBJECT: Cache Tag and Data memory way register +func (o *CACHE_Type) SetL2_CACHE_WAY_OBJECT(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_WAY_OBJECT.Reg, volatile.LoadUint32(&o.L2_CACHE_WAY_OBJECT.Reg)&^(0x7)|value) +} +func (o *CACHE_Type) GetL2_CACHE_WAY_OBJECT() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_WAY_OBJECT.Reg) & 0x7 +} + +// CACHE.L2_CACHE_VADDR: Cache Vaddr register +func (o *CACHE_Type) SetL2_CACHE_VADDR(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_VADDR.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_VADDR() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_VADDR.Reg) +} + +// CACHE.L2_CACHE_DEBUG_BUS: Cache Tag/data memory content register +func (o *CACHE_Type) SetL2_CACHE_DEBUG_BUS(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_DEBUG_BUS.Reg, value) +} +func (o *CACHE_Type) GetL2_CACHE_DEBUG_BUS() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_DEBUG_BUS.Reg) +} + +// CACHE.LEVEL_SPLIT1: USED TO SPLIT L1 CACHE AND L2 CACHE +func (o *CACHE_Type) SetLEVEL_SPLIT1(value uint32) { + volatile.StoreUint32(&o.LEVEL_SPLIT1.Reg, value) +} +func (o *CACHE_Type) GetLEVEL_SPLIT1() uint32 { + return volatile.LoadUint32(&o.LEVEL_SPLIT1.Reg) +} + +// CACHE.CLOCK_GATE: Clock gate control register +func (o *CACHE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *CACHE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// CACHE.REDUNDANCY_SIG0: Cache redundancy signal 0 register +func (o *CACHE_Type) SetREDUNDANCY_SIG0(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG0.Reg, value) +} +func (o *CACHE_Type) GetREDUNDANCY_SIG0() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG0.Reg) +} + +// CACHE.REDUNDANCY_SIG1: Cache redundancy signal 1 register +func (o *CACHE_Type) SetREDUNDANCY_SIG1(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG1.Reg, value) +} +func (o *CACHE_Type) GetREDUNDANCY_SIG1() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG1.Reg) +} + +// CACHE.REDUNDANCY_SIG2: Cache redundancy signal 2 register +func (o *CACHE_Type) SetREDUNDANCY_SIG2(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG2.Reg, value) +} +func (o *CACHE_Type) GetREDUNDANCY_SIG2() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG2.Reg) +} + +// CACHE.REDUNDANCY_SIG3: Cache redundancy signal 3 register +func (o *CACHE_Type) SetREDUNDANCY_SIG3(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG3.Reg, value) +} +func (o *CACHE_Type) GetREDUNDANCY_SIG3() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG3.Reg) +} + +// CACHE.REDUNDANCY_SIG4: Cache redundancy signal 0 register +func (o *CACHE_Type) SetREDUNDANCY_SIG4_REDCY_SIG4(value uint32) { + volatile.StoreUint32(&o.REDUNDANCY_SIG4.Reg, volatile.LoadUint32(&o.REDUNDANCY_SIG4.Reg)&^(0xf)|value) +} +func (o *CACHE_Type) GetREDUNDANCY_SIG4_REDCY_SIG4() uint32 { + return volatile.LoadUint32(&o.REDUNDANCY_SIG4.Reg) & 0xf +} + +// CACHE.DATE: Version control register +func (o *CACHE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *CACHE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Interrupt Controller (Core 0) +type CORE0_Type struct { + LP_RTC_INT_MAP volatile.Register32 // 0x0 + LP_WDT_INT_MAP volatile.Register32 // 0x4 + LP_TIMER_REG_0_INT_MAP volatile.Register32 // 0x8 + LP_TIMER_REG_1_INT_MAP volatile.Register32 // 0xC + MB_HP_INT_MAP volatile.Register32 // 0x10 + MB_LP_INT_MAP volatile.Register32 // 0x14 + PMU_REG_0_INT_MAP volatile.Register32 // 0x18 + PMU_REG_1_INT_MAP volatile.Register32 // 0x1C + LP_ANAPERI_INT_MAP volatile.Register32 // 0x20 + LP_ADC_INT_MAP volatile.Register32 // 0x24 + LP_GPIO_INT_MAP volatile.Register32 // 0x28 + LP_I2C_INT_MAP volatile.Register32 // 0x2C + LP_I2S_INT_MAP volatile.Register32 // 0x30 + LP_SPI_INT_MAP volatile.Register32 // 0x34 + LP_TOUCH_INT_MAP volatile.Register32 // 0x38 + LP_TSENS_INT_MAP volatile.Register32 // 0x3C + LP_UART_INT_MAP volatile.Register32 // 0x40 + LP_EFUSE_INT_MAP volatile.Register32 // 0x44 + LP_SW_INT_MAP volatile.Register32 // 0x48 + LP_SYSREG_INT_MAP volatile.Register32 // 0x4C + LP_HUK_INT_MAP volatile.Register32 // 0x50 + SYS_ICM_INT_MAP volatile.Register32 // 0x54 + USB_DEVICE_INT_MAP volatile.Register32 // 0x58 + SDIO_HOST_INT_MAP volatile.Register32 // 0x5C + GDMA_INT_MAP volatile.Register32 // 0x60 + SPI2_INT_MAP volatile.Register32 // 0x64 + SPI3_INT_MAP volatile.Register32 // 0x68 + I2S0_INT_MAP volatile.Register32 // 0x6C + I2S1_INT_MAP volatile.Register32 // 0x70 + I2S2_INT_MAP volatile.Register32 // 0x74 + UHCI0_INT_MAP volatile.Register32 // 0x78 + UART0_INT_MAP volatile.Register32 // 0x7C + UART1_INT_MAP volatile.Register32 // 0x80 + UART2_INT_MAP volatile.Register32 // 0x84 + UART3_INT_MAP volatile.Register32 // 0x88 + UART4_INT_MAP volatile.Register32 // 0x8C + LCD_CAM_INT_MAP volatile.Register32 // 0x90 + ADC_INT_MAP volatile.Register32 // 0x94 + PWM0_INT_MAP volatile.Register32 // 0x98 + PWM1_INT_MAP volatile.Register32 // 0x9C + CAN0_INT_MAP volatile.Register32 // 0xA0 + CAN1_INT_MAP volatile.Register32 // 0xA4 + CAN2_INT_MAP volatile.Register32 // 0xA8 + RMT_INT_MAP volatile.Register32 // 0xAC + I2C0_INT_MAP volatile.Register32 // 0xB0 + I2C1_INT_MAP volatile.Register32 // 0xB4 + TIMERGRP0_T0_INT_MAP volatile.Register32 // 0xB8 + TIMERGRP0_T1_INT_MAP volatile.Register32 // 0xBC + TIMERGRP0_WDT_INT_MAP volatile.Register32 // 0xC0 + TIMERGRP1_T0_INT_MAP volatile.Register32 // 0xC4 + TIMERGRP1_T1_INT_MAP volatile.Register32 // 0xC8 + TIMERGRP1_WDT_INT_MAP volatile.Register32 // 0xCC + LEDC_INT_MAP volatile.Register32 // 0xD0 + SYSTIMER_TARGET0_INT_MAP volatile.Register32 // 0xD4 + SYSTIMER_TARGET1_INT_MAP volatile.Register32 // 0xD8 + SYSTIMER_TARGET2_INT_MAP volatile.Register32 // 0xDC + AHB_PDMA_IN_CH0_INT_MAP volatile.Register32 // 0xE0 + AHB_PDMA_IN_CH1_INT_MAP volatile.Register32 // 0xE4 + AHB_PDMA_IN_CH2_INT_MAP volatile.Register32 // 0xE8 + AHB_PDMA_OUT_CH0_INT_MAP volatile.Register32 // 0xEC + AHB_PDMA_OUT_CH1_INT_MAP volatile.Register32 // 0xF0 + AHB_PDMA_OUT_CH2_INT_MAP volatile.Register32 // 0xF4 + AXI_PDMA_IN_CH0_INT_MAP volatile.Register32 // 0xF8 + AXI_PDMA_IN_CH1_INT_MAP volatile.Register32 // 0xFC + AXI_PDMA_IN_CH2_INT_MAP volatile.Register32 // 0x100 + AXI_PDMA_OUT_CH0_INT_MAP volatile.Register32 // 0x104 + AXI_PDMA_OUT_CH1_INT_MAP volatile.Register32 // 0x108 + AXI_PDMA_OUT_CH2_INT_MAP volatile.Register32 // 0x10C + RSA_INT_MAP volatile.Register32 // 0x110 + AES_INT_MAP volatile.Register32 // 0x114 + SHA_INT_MAP volatile.Register32 // 0x118 + ECC_INT_MAP volatile.Register32 // 0x11C + ECDSA_INT_MAP volatile.Register32 // 0x120 + KM_INT_MAP volatile.Register32 // 0x124 + GPIO_INT0_MAP volatile.Register32 // 0x128 + GPIO_INT1_MAP volatile.Register32 // 0x12C + GPIO_INT2_MAP volatile.Register32 // 0x130 + GPIO_INT3_MAP volatile.Register32 // 0x134 + GPIO_PAD_COMP_INT_MAP volatile.Register32 // 0x138 + CPU_INT_FROM_CPU_0_MAP volatile.Register32 // 0x13C + CPU_INT_FROM_CPU_1_MAP volatile.Register32 // 0x140 + CPU_INT_FROM_CPU_2_MAP volatile.Register32 // 0x144 + CPU_INT_FROM_CPU_3_MAP volatile.Register32 // 0x148 + CACHE_INT_MAP volatile.Register32 // 0x14C + FLASH_MSPI_INT_MAP volatile.Register32 // 0x150 + CSI_BRIDGE_INT_MAP volatile.Register32 // 0x154 + DSI_BRIDGE_INT_MAP volatile.Register32 // 0x158 + CSI_INT_MAP volatile.Register32 // 0x15C + DSI_INT_MAP volatile.Register32 // 0x160 + GMII_PHY_INT_MAP volatile.Register32 // 0x164 + LPI_INT_MAP volatile.Register32 // 0x168 + PMT_INT_MAP volatile.Register32 // 0x16C + SBD_INT_MAP volatile.Register32 // 0x170 + USB_OTG_INT_MAP volatile.Register32 // 0x174 + USB_OTG_ENDP_MULTI_PROC_INT_MAP volatile.Register32 // 0x178 + JPEG_INT_MAP volatile.Register32 // 0x17C + PPA_INT_MAP volatile.Register32 // 0x180 + CORE0_TRACE_INT_MAP volatile.Register32 // 0x184 + CORE1_TRACE_INT_MAP volatile.Register32 // 0x188 + HP_CORE_CTRL_INT_MAP volatile.Register32 // 0x18C + ISP_INT_MAP volatile.Register32 // 0x190 + I3C_MST_INT_MAP volatile.Register32 // 0x194 + I3C_SLV_INT_MAP volatile.Register32 // 0x198 + USB_OTG11_INT_MAP volatile.Register32 // 0x19C + DMA2D_IN_CH0_INT_MAP volatile.Register32 // 0x1A0 + DMA2D_IN_CH1_INT_MAP volatile.Register32 // 0x1A4 + DMA2D_OUT_CH0_INT_MAP volatile.Register32 // 0x1A8 + DMA2D_OUT_CH1_INT_MAP volatile.Register32 // 0x1AC + DMA2D_OUT_CH2_INT_MAP volatile.Register32 // 0x1B0 + PSRAM_MSPI_INT_MAP volatile.Register32 // 0x1B4 + HP_SYSREG_INT_MAP volatile.Register32 // 0x1B8 + PCNT_INT_MAP volatile.Register32 // 0x1BC + HP_PAU_INT_MAP volatile.Register32 // 0x1C0 + HP_PARLIO_RX_INT_MAP volatile.Register32 // 0x1C4 + HP_PARLIO_TX_INT_MAP volatile.Register32 // 0x1C8 + H264_DMA2D_OUT_CH0_INT_MAP volatile.Register32 // 0x1CC + H264_DMA2D_OUT_CH1_INT_MAP volatile.Register32 // 0x1D0 + H264_DMA2D_OUT_CH2_INT_MAP volatile.Register32 // 0x1D4 + H264_DMA2D_OUT_CH3_INT_MAP volatile.Register32 // 0x1D8 + H264_DMA2D_OUT_CH4_INT_MAP volatile.Register32 // 0x1DC + H264_DMA2D_IN_CH0_INT_MAP volatile.Register32 // 0x1E0 + H264_DMA2D_IN_CH1_INT_MAP volatile.Register32 // 0x1E4 + H264_DMA2D_IN_CH2_INT_MAP volatile.Register32 // 0x1E8 + H264_DMA2D_IN_CH3_INT_MAP volatile.Register32 // 0x1EC + H264_DMA2D_IN_CH4_INT_MAP volatile.Register32 // 0x1F0 + H264_DMA2D_IN_CH5_INT_MAP volatile.Register32 // 0x1F4 + H264_REG_INT_MAP volatile.Register32 // 0x1F8 + ASSIST_DEBUG_INT_MAP volatile.Register32 // 0x1FC + INTR_STATUS_REG_0 volatile.Register32 // 0x200 + INTR_STATUS_REG_1 volatile.Register32 // 0x204 + INTR_STATUS_REG_2 volatile.Register32 // 0x208 + INTR_STATUS_REG_3 volatile.Register32 // 0x20C + CLOCK_GATE volatile.Register32 // 0x210 + _ [488]byte + INTERRUPT_REG_DATE volatile.Register32 // 0x3FC +} + +// CORE0.LP_RTC_INT_MAP: NA +func (o *CORE0_Type) SetLP_RTC_INT_MAP_CORE0_LP_RTC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_RTC_INT_MAP.Reg, volatile.LoadUint32(&o.LP_RTC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_RTC_INT_MAP_CORE0_LP_RTC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_RTC_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_WDT_INT_MAP: NA +func (o *CORE0_Type) SetLP_WDT_INT_MAP_CORE0_LP_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.LP_WDT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_WDT_INT_MAP_CORE0_LP_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_WDT_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_TIMER_REG_0_INT_MAP: NA +func (o *CORE0_Type) SetLP_TIMER_REG_0_INT_MAP_CORE0_LP_TIMER_REG_0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_TIMER_REG_0_INT_MAP_CORE0_LP_TIMER_REG_0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_TIMER_REG_1_INT_MAP: NA +func (o *CORE0_Type) SetLP_TIMER_REG_1_INT_MAP_CORE0_LP_TIMER_REG_1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_TIMER_REG_1_INT_MAP_CORE0_LP_TIMER_REG_1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg) & 0x3f +} + +// CORE0.MB_HP_INT_MAP: NA +func (o *CORE0_Type) SetMB_HP_INT_MAP_CORE0_MB_HP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.MB_HP_INT_MAP.Reg, volatile.LoadUint32(&o.MB_HP_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetMB_HP_INT_MAP_CORE0_MB_HP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.MB_HP_INT_MAP.Reg) & 0x3f +} + +// CORE0.MB_LP_INT_MAP: NA +func (o *CORE0_Type) SetMB_LP_INT_MAP_CORE0_MB_LP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.MB_LP_INT_MAP.Reg, volatile.LoadUint32(&o.MB_LP_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetMB_LP_INT_MAP_CORE0_MB_LP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.MB_LP_INT_MAP.Reg) & 0x3f +} + +// CORE0.PMU_REG_0_INT_MAP: NA +func (o *CORE0_Type) SetPMU_REG_0_INT_MAP_CORE0_PMU_REG_0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PMU_REG_0_INT_MAP.Reg, volatile.LoadUint32(&o.PMU_REG_0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetPMU_REG_0_INT_MAP_CORE0_PMU_REG_0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PMU_REG_0_INT_MAP.Reg) & 0x3f +} + +// CORE0.PMU_REG_1_INT_MAP: NA +func (o *CORE0_Type) SetPMU_REG_1_INT_MAP_CORE0_PMU_REG_1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PMU_REG_1_INT_MAP.Reg, volatile.LoadUint32(&o.PMU_REG_1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetPMU_REG_1_INT_MAP_CORE0_PMU_REG_1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PMU_REG_1_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_ANAPERI_INT_MAP: NA +func (o *CORE0_Type) SetLP_ANAPERI_INT_MAP_CORE0_LP_ANAPERI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_ANAPERI_INT_MAP.Reg, volatile.LoadUint32(&o.LP_ANAPERI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_ANAPERI_INT_MAP_CORE0_LP_ANAPERI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_ANAPERI_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_ADC_INT_MAP: NA +func (o *CORE0_Type) SetLP_ADC_INT_MAP_CORE0_LP_ADC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_ADC_INT_MAP.Reg, volatile.LoadUint32(&o.LP_ADC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_ADC_INT_MAP_CORE0_LP_ADC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_ADC_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_GPIO_INT_MAP: NA +func (o *CORE0_Type) SetLP_GPIO_INT_MAP_CORE0_LP_GPIO_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_GPIO_INT_MAP.Reg, volatile.LoadUint32(&o.LP_GPIO_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_GPIO_INT_MAP_CORE0_LP_GPIO_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_GPIO_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_I2C_INT_MAP: NA +func (o *CORE0_Type) SetLP_I2C_INT_MAP_CORE0_LP_I2C_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_I2C_INT_MAP.Reg, volatile.LoadUint32(&o.LP_I2C_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_I2C_INT_MAP_CORE0_LP_I2C_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_I2C_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_I2S_INT_MAP: NA +func (o *CORE0_Type) SetLP_I2S_INT_MAP_CORE0_LP_I2S_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_I2S_INT_MAP.Reg, volatile.LoadUint32(&o.LP_I2S_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_I2S_INT_MAP_CORE0_LP_I2S_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_I2S_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_SPI_INT_MAP: NA +func (o *CORE0_Type) SetLP_SPI_INT_MAP_CORE0_LP_SPI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_SPI_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SPI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_SPI_INT_MAP_CORE0_LP_SPI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_SPI_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_TOUCH_INT_MAP: NA +func (o *CORE0_Type) SetLP_TOUCH_INT_MAP_CORE0_LP_TOUCH_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TOUCH_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TOUCH_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_TOUCH_INT_MAP_CORE0_LP_TOUCH_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TOUCH_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_TSENS_INT_MAP: NA +func (o *CORE0_Type) SetLP_TSENS_INT_MAP_CORE0_LP_TSENS_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TSENS_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TSENS_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_TSENS_INT_MAP_CORE0_LP_TSENS_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TSENS_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_UART_INT_MAP: NA +func (o *CORE0_Type) SetLP_UART_INT_MAP_CORE0_LP_UART_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_UART_INT_MAP.Reg, volatile.LoadUint32(&o.LP_UART_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_UART_INT_MAP_CORE0_LP_UART_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_UART_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_EFUSE_INT_MAP: NA +func (o *CORE0_Type) SetLP_EFUSE_INT_MAP_CORE0_LP_EFUSE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.LP_EFUSE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_EFUSE_INT_MAP_CORE0_LP_EFUSE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_EFUSE_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_SW_INT_MAP: NA +func (o *CORE0_Type) SetLP_SW_INT_MAP_CORE0_LP_SW_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_SW_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SW_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_SW_INT_MAP_CORE0_LP_SW_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_SW_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_SYSREG_INT_MAP: NA +func (o *CORE0_Type) SetLP_SYSREG_INT_MAP_CORE0_LP_SYSREG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_SYSREG_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SYSREG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_SYSREG_INT_MAP_CORE0_LP_SYSREG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_SYSREG_INT_MAP.Reg) & 0x3f +} + +// CORE0.LP_HUK_INT_MAP: NA +func (o *CORE0_Type) SetLP_HUK_INT_MAP_CORE0_LP_HUK_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_HUK_INT_MAP.Reg, volatile.LoadUint32(&o.LP_HUK_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLP_HUK_INT_MAP_CORE0_LP_HUK_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_HUK_INT_MAP.Reg) & 0x3f +} + +// CORE0.SYS_ICM_INT_MAP: NA +func (o *CORE0_Type) SetSYS_ICM_INT_MAP_CORE0_SYS_ICM_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYS_ICM_INT_MAP.Reg, volatile.LoadUint32(&o.SYS_ICM_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetSYS_ICM_INT_MAP_CORE0_SYS_ICM_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYS_ICM_INT_MAP.Reg) & 0x3f +} + +// CORE0.USB_DEVICE_INT_MAP: NA +func (o *CORE0_Type) SetUSB_DEVICE_INT_MAP_CORE0_USB_DEVICE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_DEVICE_INT_MAP.Reg, volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUSB_DEVICE_INT_MAP_CORE0_USB_DEVICE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg) & 0x3f +} + +// CORE0.SDIO_HOST_INT_MAP: NA +func (o *CORE0_Type) SetSDIO_HOST_INT_MAP_CORE0_SDIO_HOST_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SDIO_HOST_INT_MAP.Reg, volatile.LoadUint32(&o.SDIO_HOST_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetSDIO_HOST_INT_MAP_CORE0_SDIO_HOST_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SDIO_HOST_INT_MAP.Reg) & 0x3f +} + +// CORE0.GDMA_INT_MAP: NA +func (o *CORE0_Type) SetGDMA_INT_MAP_CORE0_GDMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.GDMA_INT_MAP.Reg, volatile.LoadUint32(&o.GDMA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetGDMA_INT_MAP_CORE0_GDMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.GDMA_INT_MAP.Reg) & 0x3f +} + +// CORE0.SPI2_INT_MAP: NA +func (o *CORE0_Type) SetSPI2_INT_MAP_CORE0_SPI2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI2_INT_MAP.Reg, volatile.LoadUint32(&o.SPI2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetSPI2_INT_MAP_CORE0_SPI2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI2_INT_MAP.Reg) & 0x3f +} + +// CORE0.SPI3_INT_MAP: NA +func (o *CORE0_Type) SetSPI3_INT_MAP_CORE0_SPI3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI3_INT_MAP.Reg, volatile.LoadUint32(&o.SPI3_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetSPI3_INT_MAP_CORE0_SPI3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI3_INT_MAP.Reg) & 0x3f +} + +// CORE0.I2S0_INT_MAP: NA +func (o *CORE0_Type) SetI2S0_INT_MAP_CORE0_I2S0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S0_INT_MAP.Reg, volatile.LoadUint32(&o.I2S0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetI2S0_INT_MAP_CORE0_I2S0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S0_INT_MAP.Reg) & 0x3f +} + +// CORE0.I2S1_INT_MAP: NA +func (o *CORE0_Type) SetI2S1_INT_MAP_CORE0_I2S1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.I2S1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetI2S1_INT_MAP_CORE0_I2S1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S1_INT_MAP.Reg) & 0x3f +} + +// CORE0.I2S2_INT_MAP: NA +func (o *CORE0_Type) SetI2S2_INT_MAP_CORE0_I2S2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S2_INT_MAP.Reg, volatile.LoadUint32(&o.I2S2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetI2S2_INT_MAP_CORE0_I2S2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S2_INT_MAP.Reg) & 0x3f +} + +// CORE0.UHCI0_INT_MAP: NA +func (o *CORE0_Type) SetUHCI0_INT_MAP_CORE0_UHCI0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UHCI0_INT_MAP.Reg, volatile.LoadUint32(&o.UHCI0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUHCI0_INT_MAP_CORE0_UHCI0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UHCI0_INT_MAP.Reg) & 0x3f +} + +// CORE0.UART0_INT_MAP: NA +func (o *CORE0_Type) SetUART0_INT_MAP_CORE0_UART0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART0_INT_MAP.Reg, volatile.LoadUint32(&o.UART0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUART0_INT_MAP_CORE0_UART0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART0_INT_MAP.Reg) & 0x3f +} + +// CORE0.UART1_INT_MAP: NA +func (o *CORE0_Type) SetUART1_INT_MAP_CORE0_UART1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART1_INT_MAP.Reg, volatile.LoadUint32(&o.UART1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUART1_INT_MAP_CORE0_UART1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART1_INT_MAP.Reg) & 0x3f +} + +// CORE0.UART2_INT_MAP: NA +func (o *CORE0_Type) SetUART2_INT_MAP_CORE0_UART2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART2_INT_MAP.Reg, volatile.LoadUint32(&o.UART2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUART2_INT_MAP_CORE0_UART2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART2_INT_MAP.Reg) & 0x3f +} + +// CORE0.UART3_INT_MAP: NA +func (o *CORE0_Type) SetUART3_INT_MAP_CORE0_UART3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART3_INT_MAP.Reg, volatile.LoadUint32(&o.UART3_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUART3_INT_MAP_CORE0_UART3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART3_INT_MAP.Reg) & 0x3f +} + +// CORE0.UART4_INT_MAP: NA +func (o *CORE0_Type) SetUART4_INT_MAP_CORE0_UART4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART4_INT_MAP.Reg, volatile.LoadUint32(&o.UART4_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUART4_INT_MAP_CORE0_UART4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART4_INT_MAP.Reg) & 0x3f +} + +// CORE0.LCD_CAM_INT_MAP: NA +func (o *CORE0_Type) SetLCD_CAM_INT_MAP_CORE0_LCD_CAM_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LCD_CAM_INT_MAP.Reg, volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLCD_CAM_INT_MAP_CORE0_LCD_CAM_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg) & 0x3f +} + +// CORE0.ADC_INT_MAP: NA +func (o *CORE0_Type) SetADC_INT_MAP_CORE0_ADC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ADC_INT_MAP.Reg, volatile.LoadUint32(&o.ADC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetADC_INT_MAP_CORE0_ADC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ADC_INT_MAP.Reg) & 0x3f +} + +// CORE0.PWM0_INT_MAP: NA +func (o *CORE0_Type) SetPWM0_INT_MAP_CORE0_PWM0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PWM0_INT_MAP.Reg, volatile.LoadUint32(&o.PWM0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetPWM0_INT_MAP_CORE0_PWM0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PWM0_INT_MAP.Reg) & 0x3f +} + +// CORE0.PWM1_INT_MAP: NA +func (o *CORE0_Type) SetPWM1_INT_MAP_CORE0_PWM1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PWM1_INT_MAP.Reg, volatile.LoadUint32(&o.PWM1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetPWM1_INT_MAP_CORE0_PWM1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PWM1_INT_MAP.Reg) & 0x3f +} + +// CORE0.CAN0_INT_MAP: NA +func (o *CORE0_Type) SetCAN0_INT_MAP_CORE0_CAN0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CAN0_INT_MAP.Reg, volatile.LoadUint32(&o.CAN0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCAN0_INT_MAP_CORE0_CAN0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CAN0_INT_MAP.Reg) & 0x3f +} + +// CORE0.CAN1_INT_MAP: NA +func (o *CORE0_Type) SetCAN1_INT_MAP_CORE0_CAN1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CAN1_INT_MAP.Reg, volatile.LoadUint32(&o.CAN1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCAN1_INT_MAP_CORE0_CAN1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CAN1_INT_MAP.Reg) & 0x3f +} + +// CORE0.CAN2_INT_MAP: NA +func (o *CORE0_Type) SetCAN2_INT_MAP_CORE0_CAN2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CAN2_INT_MAP.Reg, volatile.LoadUint32(&o.CAN2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCAN2_INT_MAP_CORE0_CAN2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CAN2_INT_MAP.Reg) & 0x3f +} + +// CORE0.RMT_INT_MAP: NA +func (o *CORE0_Type) SetRMT_INT_MAP_CORE0_RMT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.RMT_INT_MAP.Reg, volatile.LoadUint32(&o.RMT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetRMT_INT_MAP_CORE0_RMT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.RMT_INT_MAP.Reg) & 0x3f +} + +// CORE0.I2C0_INT_MAP: NA +func (o *CORE0_Type) SetI2C0_INT_MAP_CORE0_I2C0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2C0_INT_MAP.Reg, volatile.LoadUint32(&o.I2C0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetI2C0_INT_MAP_CORE0_I2C0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2C0_INT_MAP.Reg) & 0x3f +} + +// CORE0.I2C1_INT_MAP: NA +func (o *CORE0_Type) SetI2C1_INT_MAP_CORE0_I2C1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2C1_INT_MAP.Reg, volatile.LoadUint32(&o.I2C1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetI2C1_INT_MAP_CORE0_I2C1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2C1_INT_MAP.Reg) & 0x3f +} + +// CORE0.TIMERGRP0_T0_INT_MAP: NA +func (o *CORE0_Type) SetTIMERGRP0_T0_INT_MAP_CORE0_TIMERGRP0_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP0_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_T0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetTIMERGRP0_T0_INT_MAP_CORE0_TIMERGRP0_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP0_T0_INT_MAP.Reg) & 0x3f +} + +// CORE0.TIMERGRP0_T1_INT_MAP: NA +func (o *CORE0_Type) SetTIMERGRP0_T1_INT_MAP_CORE0_TIMERGRP0_T1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP0_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_T1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetTIMERGRP0_T1_INT_MAP_CORE0_TIMERGRP0_T1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP0_T1_INT_MAP.Reg) & 0x3f +} + +// CORE0.TIMERGRP0_WDT_INT_MAP: NA +func (o *CORE0_Type) SetTIMERGRP0_WDT_INT_MAP_CORE0_TIMERGRP0_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetTIMERGRP0_WDT_INT_MAP_CORE0_TIMERGRP0_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg) & 0x3f +} + +// CORE0.TIMERGRP1_T0_INT_MAP: NA +func (o *CORE0_Type) SetTIMERGRP1_T0_INT_MAP_CORE0_TIMERGRP1_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP1_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_T0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetTIMERGRP1_T0_INT_MAP_CORE0_TIMERGRP1_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP1_T0_INT_MAP.Reg) & 0x3f +} + +// CORE0.TIMERGRP1_T1_INT_MAP: NA +func (o *CORE0_Type) SetTIMERGRP1_T1_INT_MAP_CORE0_TIMERGRP1_T1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP1_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_T1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetTIMERGRP1_T1_INT_MAP_CORE0_TIMERGRP1_T1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP1_T1_INT_MAP.Reg) & 0x3f +} + +// CORE0.TIMERGRP1_WDT_INT_MAP: NA +func (o *CORE0_Type) SetTIMERGRP1_WDT_INT_MAP_CORE0_TIMERGRP1_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetTIMERGRP1_WDT_INT_MAP_CORE0_TIMERGRP1_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg) & 0x3f +} + +// CORE0.LEDC_INT_MAP: NA +func (o *CORE0_Type) SetLEDC_INT_MAP_CORE0_LEDC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.LEDC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLEDC_INT_MAP_CORE0_LEDC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LEDC_INT_MAP.Reg) & 0x3f +} + +// CORE0.SYSTIMER_TARGET0_INT_MAP: NA +func (o *CORE0_Type) SetSYSTIMER_TARGET0_INT_MAP_CORE0_SYSTIMER_TARGET0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetSYSTIMER_TARGET0_INT_MAP_CORE0_SYSTIMER_TARGET0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg) & 0x3f +} + +// CORE0.SYSTIMER_TARGET1_INT_MAP: NA +func (o *CORE0_Type) SetSYSTIMER_TARGET1_INT_MAP_CORE0_SYSTIMER_TARGET1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetSYSTIMER_TARGET1_INT_MAP_CORE0_SYSTIMER_TARGET1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg) & 0x3f +} + +// CORE0.SYSTIMER_TARGET2_INT_MAP: NA +func (o *CORE0_Type) SetSYSTIMER_TARGET2_INT_MAP_CORE0_SYSTIMER_TARGET2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetSYSTIMER_TARGET2_INT_MAP_CORE0_SYSTIMER_TARGET2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg) & 0x3f +} + +// CORE0.AHB_PDMA_IN_CH0_INT_MAP: NA +func (o *CORE0_Type) SetAHB_PDMA_IN_CH0_INT_MAP_CORE0_AHB_PDMA_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAHB_PDMA_IN_CH0_INT_MAP_CORE0_AHB_PDMA_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE0.AHB_PDMA_IN_CH1_INT_MAP: NA +func (o *CORE0_Type) SetAHB_PDMA_IN_CH1_INT_MAP_CORE0_AHB_PDMA_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAHB_PDMA_IN_CH1_INT_MAP_CORE0_AHB_PDMA_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE0.AHB_PDMA_IN_CH2_INT_MAP: NA +func (o *CORE0_Type) SetAHB_PDMA_IN_CH2_INT_MAP_CORE0_AHB_PDMA_IN_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAHB_PDMA_IN_CH2_INT_MAP_CORE0_AHB_PDMA_IN_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE0.AHB_PDMA_OUT_CH0_INT_MAP: NA +func (o *CORE0_Type) SetAHB_PDMA_OUT_CH0_INT_MAP_CORE0_AHB_PDMA_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAHB_PDMA_OUT_CH0_INT_MAP_CORE0_AHB_PDMA_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE0.AHB_PDMA_OUT_CH1_INT_MAP: NA +func (o *CORE0_Type) SetAHB_PDMA_OUT_CH1_INT_MAP_CORE0_AHB_PDMA_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAHB_PDMA_OUT_CH1_INT_MAP_CORE0_AHB_PDMA_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE0.AHB_PDMA_OUT_CH2_INT_MAP: NA +func (o *CORE0_Type) SetAHB_PDMA_OUT_CH2_INT_MAP_CORE0_AHB_PDMA_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAHB_PDMA_OUT_CH2_INT_MAP_CORE0_AHB_PDMA_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE0.AXI_PDMA_IN_CH0_INT_MAP: NA +func (o *CORE0_Type) SetAXI_PDMA_IN_CH0_INT_MAP_CORE0_AXI_PDMA_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAXI_PDMA_IN_CH0_INT_MAP_CORE0_AXI_PDMA_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE0.AXI_PDMA_IN_CH1_INT_MAP: NA +func (o *CORE0_Type) SetAXI_PDMA_IN_CH1_INT_MAP_CORE0_AXI_PDMA_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAXI_PDMA_IN_CH1_INT_MAP_CORE0_AXI_PDMA_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE0.AXI_PDMA_IN_CH2_INT_MAP: NA +func (o *CORE0_Type) SetAXI_PDMA_IN_CH2_INT_MAP_CORE0_AXI_PDMA_IN_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAXI_PDMA_IN_CH2_INT_MAP_CORE0_AXI_PDMA_IN_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE0.AXI_PDMA_OUT_CH0_INT_MAP: NA +func (o *CORE0_Type) SetAXI_PDMA_OUT_CH0_INT_MAP_CORE0_AXI_PDMA_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAXI_PDMA_OUT_CH0_INT_MAP_CORE0_AXI_PDMA_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE0.AXI_PDMA_OUT_CH1_INT_MAP: NA +func (o *CORE0_Type) SetAXI_PDMA_OUT_CH1_INT_MAP_CORE0_AXI_PDMA_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAXI_PDMA_OUT_CH1_INT_MAP_CORE0_AXI_PDMA_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE0.AXI_PDMA_OUT_CH2_INT_MAP: NA +func (o *CORE0_Type) SetAXI_PDMA_OUT_CH2_INT_MAP_CORE0_AXI_PDMA_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAXI_PDMA_OUT_CH2_INT_MAP_CORE0_AXI_PDMA_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE0.RSA_INT_MAP: NA +func (o *CORE0_Type) SetRSA_INT_MAP_CORE0_RSA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.RSA_INT_MAP.Reg, volatile.LoadUint32(&o.RSA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetRSA_INT_MAP_CORE0_RSA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.RSA_INT_MAP.Reg) & 0x3f +} + +// CORE0.AES_INT_MAP: NA +func (o *CORE0_Type) SetAES_INT_MAP_CORE0_AES_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AES_INT_MAP.Reg, volatile.LoadUint32(&o.AES_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetAES_INT_MAP_CORE0_AES_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AES_INT_MAP.Reg) & 0x3f +} + +// CORE0.SHA_INT_MAP: NA +func (o *CORE0_Type) SetSHA_INT_MAP_CORE0_SHA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SHA_INT_MAP.Reg, volatile.LoadUint32(&o.SHA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetSHA_INT_MAP_CORE0_SHA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SHA_INT_MAP.Reg) & 0x3f +} + +// CORE0.ECC_INT_MAP: NA +func (o *CORE0_Type) SetECC_INT_MAP_CORE0_ECC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ECC_INT_MAP.Reg, volatile.LoadUint32(&o.ECC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetECC_INT_MAP_CORE0_ECC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ECC_INT_MAP.Reg) & 0x3f +} + +// CORE0.ECDSA_INT_MAP: NA +func (o *CORE0_Type) SetECDSA_INT_MAP_CORE0_ECDSA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ECDSA_INT_MAP.Reg, volatile.LoadUint32(&o.ECDSA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetECDSA_INT_MAP_CORE0_ECDSA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ECDSA_INT_MAP.Reg) & 0x3f +} + +// CORE0.KM_INT_MAP: NA +func (o *CORE0_Type) SetKM_INT_MAP_CORE0_KM_INT_MAP(value uint32) { + volatile.StoreUint32(&o.KM_INT_MAP.Reg, volatile.LoadUint32(&o.KM_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetKM_INT_MAP_CORE0_KM_INT_MAP() uint32 { + return volatile.LoadUint32(&o.KM_INT_MAP.Reg) & 0x3f +} + +// CORE0.GPIO_INT0_MAP: NA +func (o *CORE0_Type) SetGPIO_INT0_MAP_CORE0_GPIO_INT0_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INT0_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT0_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetGPIO_INT0_MAP_CORE0_GPIO_INT0_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INT0_MAP.Reg) & 0x3f +} + +// CORE0.GPIO_INT1_MAP: NA +func (o *CORE0_Type) SetGPIO_INT1_MAP_CORE0_GPIO_INT1_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INT1_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT1_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetGPIO_INT1_MAP_CORE0_GPIO_INT1_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INT1_MAP.Reg) & 0x3f +} + +// CORE0.GPIO_INT2_MAP: NA +func (o *CORE0_Type) SetGPIO_INT2_MAP_CORE0_GPIO_INT2_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INT2_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT2_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetGPIO_INT2_MAP_CORE0_GPIO_INT2_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INT2_MAP.Reg) & 0x3f +} + +// CORE0.GPIO_INT3_MAP: NA +func (o *CORE0_Type) SetGPIO_INT3_MAP_CORE0_GPIO_INT3_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INT3_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT3_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetGPIO_INT3_MAP_CORE0_GPIO_INT3_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INT3_MAP.Reg) & 0x3f +} + +// CORE0.GPIO_PAD_COMP_INT_MAP: NA +func (o *CORE0_Type) SetGPIO_PAD_COMP_INT_MAP_CORE0_GPIO_PAD_COMP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg, volatile.LoadUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetGPIO_PAD_COMP_INT_MAP_CORE0_GPIO_PAD_COMP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg) & 0x3f +} + +// CORE0.CPU_INT_FROM_CPU_0_MAP: NA +func (o *CORE0_Type) SetCPU_INT_FROM_CPU_0_MAP_CORE0_CPU_INT_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCPU_INT_FROM_CPU_0_MAP_CORE0_CPU_INT_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg) & 0x3f +} + +// CORE0.CPU_INT_FROM_CPU_1_MAP: NA +func (o *CORE0_Type) SetCPU_INT_FROM_CPU_1_MAP_CORE0_CPU_INT_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCPU_INT_FROM_CPU_1_MAP_CORE0_CPU_INT_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg) & 0x3f +} + +// CORE0.CPU_INT_FROM_CPU_2_MAP: NA +func (o *CORE0_Type) SetCPU_INT_FROM_CPU_2_MAP_CORE0_CPU_INT_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCPU_INT_FROM_CPU_2_MAP_CORE0_CPU_INT_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg) & 0x3f +} + +// CORE0.CPU_INT_FROM_CPU_3_MAP: NA +func (o *CORE0_Type) SetCPU_INT_FROM_CPU_3_MAP_CORE0_CPU_INT_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCPU_INT_FROM_CPU_3_MAP_CORE0_CPU_INT_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg) & 0x3f +} + +// CORE0.CACHE_INT_MAP: NA +func (o *CORE0_Type) SetCACHE_INT_MAP_CORE0_CACHE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCACHE_INT_MAP_CORE0_CACHE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_INT_MAP.Reg) & 0x3f +} + +// CORE0.FLASH_MSPI_INT_MAP: NA +func (o *CORE0_Type) SetFLASH_MSPI_INT_MAP_CORE0_FLASH_MSPI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.FLASH_MSPI_INT_MAP.Reg, volatile.LoadUint32(&o.FLASH_MSPI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetFLASH_MSPI_INT_MAP_CORE0_FLASH_MSPI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.FLASH_MSPI_INT_MAP.Reg) & 0x3f +} + +// CORE0.CSI_BRIDGE_INT_MAP: NA +func (o *CORE0_Type) SetCSI_BRIDGE_INT_MAP_CORE0_CSI_BRIDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CSI_BRIDGE_INT_MAP.Reg, volatile.LoadUint32(&o.CSI_BRIDGE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCSI_BRIDGE_INT_MAP_CORE0_CSI_BRIDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CSI_BRIDGE_INT_MAP.Reg) & 0x3f +} + +// CORE0.DSI_BRIDGE_INT_MAP: NA +func (o *CORE0_Type) SetDSI_BRIDGE_INT_MAP_CORE0_DSI_BRIDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DSI_BRIDGE_INT_MAP.Reg, volatile.LoadUint32(&o.DSI_BRIDGE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetDSI_BRIDGE_INT_MAP_CORE0_DSI_BRIDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DSI_BRIDGE_INT_MAP.Reg) & 0x3f +} + +// CORE0.CSI_INT_MAP: NA +func (o *CORE0_Type) SetCSI_INT_MAP_CORE0_CSI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CSI_INT_MAP.Reg, volatile.LoadUint32(&o.CSI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCSI_INT_MAP_CORE0_CSI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CSI_INT_MAP.Reg) & 0x3f +} + +// CORE0.DSI_INT_MAP: NA +func (o *CORE0_Type) SetDSI_INT_MAP_CORE0_DSI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DSI_INT_MAP.Reg, volatile.LoadUint32(&o.DSI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetDSI_INT_MAP_CORE0_DSI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DSI_INT_MAP.Reg) & 0x3f +} + +// CORE0.GMII_PHY_INT_MAP: NA +func (o *CORE0_Type) SetGMII_PHY_INT_MAP_CORE0_GMII_PHY_INT_MAP(value uint32) { + volatile.StoreUint32(&o.GMII_PHY_INT_MAP.Reg, volatile.LoadUint32(&o.GMII_PHY_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetGMII_PHY_INT_MAP_CORE0_GMII_PHY_INT_MAP() uint32 { + return volatile.LoadUint32(&o.GMII_PHY_INT_MAP.Reg) & 0x3f +} + +// CORE0.LPI_INT_MAP: NA +func (o *CORE0_Type) SetLPI_INT_MAP_CORE0_LPI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LPI_INT_MAP.Reg, volatile.LoadUint32(&o.LPI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetLPI_INT_MAP_CORE0_LPI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LPI_INT_MAP.Reg) & 0x3f +} + +// CORE0.PMT_INT_MAP: NA +func (o *CORE0_Type) SetPMT_INT_MAP_CORE0_PMT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PMT_INT_MAP.Reg, volatile.LoadUint32(&o.PMT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetPMT_INT_MAP_CORE0_PMT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PMT_INT_MAP.Reg) & 0x3f +} + +// CORE0.SBD_INT_MAP: NA +func (o *CORE0_Type) SetSBD_INT_MAP_CORE0_SBD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SBD_INT_MAP.Reg, volatile.LoadUint32(&o.SBD_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetSBD_INT_MAP_CORE0_SBD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SBD_INT_MAP.Reg) & 0x3f +} + +// CORE0.USB_OTG_INT_MAP: NA +func (o *CORE0_Type) SetUSB_OTG_INT_MAP_CORE0_USB_OTG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_OTG_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUSB_OTG_INT_MAP_CORE0_USB_OTG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_OTG_INT_MAP.Reg) & 0x3f +} + +// CORE0.USB_OTG_ENDP_MULTI_PROC_INT_MAP: NA +func (o *CORE0_Type) SetUSB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUSB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg) & 0x3f +} + +// CORE0.JPEG_INT_MAP: NA +func (o *CORE0_Type) SetJPEG_INT_MAP_CORE0_JPEG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.JPEG_INT_MAP.Reg, volatile.LoadUint32(&o.JPEG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetJPEG_INT_MAP_CORE0_JPEG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.JPEG_INT_MAP.Reg) & 0x3f +} + +// CORE0.PPA_INT_MAP: NA +func (o *CORE0_Type) SetPPA_INT_MAP_CORE0_PPA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PPA_INT_MAP.Reg, volatile.LoadUint32(&o.PPA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetPPA_INT_MAP_CORE0_PPA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PPA_INT_MAP.Reg) & 0x3f +} + +// CORE0.CORE0_TRACE_INT_MAP: NA +func (o *CORE0_Type) SetCORE0_TRACE_INT_MAP_CORE0_CORE0_TRACE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CORE0_TRACE_INT_MAP.Reg, volatile.LoadUint32(&o.CORE0_TRACE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCORE0_TRACE_INT_MAP_CORE0_CORE0_TRACE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CORE0_TRACE_INT_MAP.Reg) & 0x3f +} + +// CORE0.CORE1_TRACE_INT_MAP: NA +func (o *CORE0_Type) SetCORE1_TRACE_INT_MAP_CORE0_CORE1_TRACE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CORE1_TRACE_INT_MAP.Reg, volatile.LoadUint32(&o.CORE1_TRACE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetCORE1_TRACE_INT_MAP_CORE0_CORE1_TRACE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CORE1_TRACE_INT_MAP.Reg) & 0x3f +} + +// CORE0.HP_CORE_CTRL_INT_MAP: NA +func (o *CORE0_Type) SetHP_CORE_CTRL_INT_MAP_CORE0_HP_CORE_CTRL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_CORE_CTRL_INT_MAP.Reg, volatile.LoadUint32(&o.HP_CORE_CTRL_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetHP_CORE_CTRL_INT_MAP_CORE0_HP_CORE_CTRL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_CORE_CTRL_INT_MAP.Reg) & 0x3f +} + +// CORE0.ISP_INT_MAP: NA +func (o *CORE0_Type) SetISP_INT_MAP_CORE0_ISP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ISP_INT_MAP.Reg, volatile.LoadUint32(&o.ISP_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetISP_INT_MAP_CORE0_ISP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ISP_INT_MAP.Reg) & 0x3f +} + +// CORE0.I3C_MST_INT_MAP: NA +func (o *CORE0_Type) SetI3C_MST_INT_MAP_CORE0_I3C_MST_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I3C_MST_INT_MAP.Reg, volatile.LoadUint32(&o.I3C_MST_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetI3C_MST_INT_MAP_CORE0_I3C_MST_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I3C_MST_INT_MAP.Reg) & 0x3f +} + +// CORE0.I3C_SLV_INT_MAP: NA +func (o *CORE0_Type) SetI3C_SLV_INT_MAP_CORE0_I3C_SLV_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I3C_SLV_INT_MAP.Reg, volatile.LoadUint32(&o.I3C_SLV_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetI3C_SLV_INT_MAP_CORE0_I3C_SLV_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I3C_SLV_INT_MAP.Reg) & 0x3f +} + +// CORE0.USB_OTG11_INT_MAP: NA +func (o *CORE0_Type) SetUSB_OTG11_INT_MAP_CORE0_USB_OTG11_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_OTG11_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG11_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetUSB_OTG11_INT_MAP_CORE0_USB_OTG11_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_OTG11_INT_MAP.Reg) & 0x3f +} + +// CORE0.DMA2D_IN_CH0_INT_MAP: NA +func (o *CORE0_Type) SetDMA2D_IN_CH0_INT_MAP_CORE0_DMA2D_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetDMA2D_IN_CH0_INT_MAP_CORE0_DMA2D_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE0.DMA2D_IN_CH1_INT_MAP: NA +func (o *CORE0_Type) SetDMA2D_IN_CH1_INT_MAP_CORE0_DMA2D_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetDMA2D_IN_CH1_INT_MAP_CORE0_DMA2D_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE0.DMA2D_OUT_CH0_INT_MAP: NA +func (o *CORE0_Type) SetDMA2D_OUT_CH0_INT_MAP_CORE0_DMA2D_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetDMA2D_OUT_CH0_INT_MAP_CORE0_DMA2D_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE0.DMA2D_OUT_CH1_INT_MAP: NA +func (o *CORE0_Type) SetDMA2D_OUT_CH1_INT_MAP_CORE0_DMA2D_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetDMA2D_OUT_CH1_INT_MAP_CORE0_DMA2D_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE0.DMA2D_OUT_CH2_INT_MAP: NA +func (o *CORE0_Type) SetDMA2D_OUT_CH2_INT_MAP_CORE0_DMA2D_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetDMA2D_OUT_CH2_INT_MAP_CORE0_DMA2D_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE0.PSRAM_MSPI_INT_MAP: NA +func (o *CORE0_Type) SetPSRAM_MSPI_INT_MAP_CORE0_PSRAM_MSPI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PSRAM_MSPI_INT_MAP.Reg, volatile.LoadUint32(&o.PSRAM_MSPI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetPSRAM_MSPI_INT_MAP_CORE0_PSRAM_MSPI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PSRAM_MSPI_INT_MAP.Reg) & 0x3f +} + +// CORE0.HP_SYSREG_INT_MAP: NA +func (o *CORE0_Type) SetHP_SYSREG_INT_MAP_CORE0_HP_SYSREG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_SYSREG_INT_MAP.Reg, volatile.LoadUint32(&o.HP_SYSREG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetHP_SYSREG_INT_MAP_CORE0_HP_SYSREG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_SYSREG_INT_MAP.Reg) & 0x3f +} + +// CORE0.PCNT_INT_MAP: NA +func (o *CORE0_Type) SetPCNT_INT_MAP_CORE0_PCNT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PCNT_INT_MAP.Reg, volatile.LoadUint32(&o.PCNT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetPCNT_INT_MAP_CORE0_PCNT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PCNT_INT_MAP.Reg) & 0x3f +} + +// CORE0.HP_PAU_INT_MAP: NA +func (o *CORE0_Type) SetHP_PAU_INT_MAP_CORE0_HP_PAU_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_PAU_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PAU_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetHP_PAU_INT_MAP_CORE0_HP_PAU_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_PAU_INT_MAP.Reg) & 0x3f +} + +// CORE0.HP_PARLIO_RX_INT_MAP: NA +func (o *CORE0_Type) SetHP_PARLIO_RX_INT_MAP_CORE0_HP_PARLIO_RX_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_PARLIO_RX_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PARLIO_RX_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetHP_PARLIO_RX_INT_MAP_CORE0_HP_PARLIO_RX_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_PARLIO_RX_INT_MAP.Reg) & 0x3f +} + +// CORE0.HP_PARLIO_TX_INT_MAP: NA +func (o *CORE0_Type) SetHP_PARLIO_TX_INT_MAP_CORE0_HP_PARLIO_TX_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_PARLIO_TX_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PARLIO_TX_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetHP_PARLIO_TX_INT_MAP_CORE0_HP_PARLIO_TX_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_PARLIO_TX_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_OUT_CH0_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_OUT_CH0_INT_MAP_CORE0_H264_DMA2D_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_OUT_CH0_INT_MAP_CORE0_H264_DMA2D_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_OUT_CH1_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_OUT_CH1_INT_MAP_CORE0_H264_DMA2D_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_OUT_CH1_INT_MAP_CORE0_H264_DMA2D_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_OUT_CH2_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_OUT_CH2_INT_MAP_CORE0_H264_DMA2D_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_OUT_CH2_INT_MAP_CORE0_H264_DMA2D_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_OUT_CH3_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_OUT_CH3_INT_MAP_CORE0_H264_DMA2D_OUT_CH3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_OUT_CH3_INT_MAP_CORE0_H264_DMA2D_OUT_CH3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_OUT_CH4_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_OUT_CH4_INT_MAP_CORE0_H264_DMA2D_OUT_CH4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_OUT_CH4_INT_MAP_CORE0_H264_DMA2D_OUT_CH4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_IN_CH0_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_IN_CH0_INT_MAP_CORE0_H264_DMA2D_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_IN_CH0_INT_MAP_CORE0_H264_DMA2D_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_IN_CH1_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_IN_CH1_INT_MAP_CORE0_H264_DMA2D_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_IN_CH1_INT_MAP_CORE0_H264_DMA2D_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_IN_CH2_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_IN_CH2_INT_MAP_CORE0_H264_DMA2D_IN_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_IN_CH2_INT_MAP_CORE0_H264_DMA2D_IN_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_IN_CH3_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_IN_CH3_INT_MAP_CORE0_H264_DMA2D_IN_CH3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_IN_CH3_INT_MAP_CORE0_H264_DMA2D_IN_CH3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_IN_CH4_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_IN_CH4_INT_MAP_CORE0_H264_DMA2D_IN_CH4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_IN_CH4_INT_MAP_CORE0_H264_DMA2D_IN_CH4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_DMA2D_IN_CH5_INT_MAP: NA +func (o *CORE0_Type) SetH264_DMA2D_IN_CH5_INT_MAP_CORE0_H264_DMA2D_IN_CH5_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_DMA2D_IN_CH5_INT_MAP_CORE0_H264_DMA2D_IN_CH5_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg) & 0x3f +} + +// CORE0.H264_REG_INT_MAP: NA +func (o *CORE0_Type) SetH264_REG_INT_MAP_CORE0_H264_REG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_REG_INT_MAP.Reg, volatile.LoadUint32(&o.H264_REG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetH264_REG_INT_MAP_CORE0_H264_REG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_REG_INT_MAP.Reg) & 0x3f +} + +// CORE0.ASSIST_DEBUG_INT_MAP: NA +func (o *CORE0_Type) SetASSIST_DEBUG_INT_MAP_CORE0_ASSIST_DEBUG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ASSIST_DEBUG_INT_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE0_Type) GetASSIST_DEBUG_INT_MAP_CORE0_ASSIST_DEBUG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ASSIST_DEBUG_INT_MAP.Reg) & 0x3f +} + +// CORE0.INTR_STATUS_REG_0: NA +func (o *CORE0_Type) SetINTR_STATUS_REG_0(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_0.Reg, value) +} +func (o *CORE0_Type) GetINTR_STATUS_REG_0() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_0.Reg) +} + +// CORE0.INTR_STATUS_REG_1: NA +func (o *CORE0_Type) SetINTR_STATUS_REG_1(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_1.Reg, value) +} +func (o *CORE0_Type) GetINTR_STATUS_REG_1() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_1.Reg) +} + +// CORE0.INTR_STATUS_REG_2: NA +func (o *CORE0_Type) SetINTR_STATUS_REG_2(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_2.Reg, value) +} +func (o *CORE0_Type) GetINTR_STATUS_REG_2() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_2.Reg) +} + +// CORE0.INTR_STATUS_REG_3: NA +func (o *CORE0_Type) SetINTR_STATUS_REG_3(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_3.Reg, value) +} +func (o *CORE0_Type) GetINTR_STATUS_REG_3() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_3.Reg) +} + +// CORE0.CLOCK_GATE: NA +func (o *CORE0_Type) SetCLOCK_GATE_CORE0_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *CORE0_Type) GetCLOCK_GATE_CORE0_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// CORE0.INTERRUPT_REG_DATE: NA +func (o *CORE0_Type) SetINTERRUPT_REG_DATE_CORE0_INTERRUPT_REG_DATE(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_REG_DATE.Reg, volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *CORE0_Type) GetINTERRUPT_REG_DATE_CORE0_INTERRUPT_REG_DATE() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg) & 0xfffffff +} + +// Interrupt Controller (Core 1) +type CORE1_Type struct { + LP_RTC_INT_MAP volatile.Register32 // 0x0 + LP_WDT_INT_MAP volatile.Register32 // 0x4 + LP_TIMER_REG_0_INT_MAP volatile.Register32 // 0x8 + LP_TIMER_REG_1_INT_MAP volatile.Register32 // 0xC + MB_HP_INT_MAP volatile.Register32 // 0x10 + MB_LP_INT_MAP volatile.Register32 // 0x14 + PMU_REG_0_INT_MAP volatile.Register32 // 0x18 + PMU_REG_1_INT_MAP volatile.Register32 // 0x1C + LP_ANAPERI_INT_MAP volatile.Register32 // 0x20 + LP_ADC_INT_MAP volatile.Register32 // 0x24 + LP_GPIO_INT_MAP volatile.Register32 // 0x28 + LP_I2C_INT_MAP volatile.Register32 // 0x2C + LP_I2S_INT_MAP volatile.Register32 // 0x30 + LP_SPI_INT_MAP volatile.Register32 // 0x34 + LP_TOUCH_INT_MAP volatile.Register32 // 0x38 + LP_TSENS_INT_MAP volatile.Register32 // 0x3C + LP_UART_INT_MAP volatile.Register32 // 0x40 + LP_EFUSE_INT_MAP volatile.Register32 // 0x44 + LP_SW_INT_MAP volatile.Register32 // 0x48 + LP_SYSREG_INT_MAP volatile.Register32 // 0x4C + LP_HUK_INT_MAP volatile.Register32 // 0x50 + SYS_ICM_INT_MAP volatile.Register32 // 0x54 + USB_DEVICE_INT_MAP volatile.Register32 // 0x58 + SDIO_HOST_INT_MAP volatile.Register32 // 0x5C + GDMA_INT_MAP volatile.Register32 // 0x60 + SPI2_INT_MAP volatile.Register32 // 0x64 + SPI3_INT_MAP volatile.Register32 // 0x68 + I2S0_INT_MAP volatile.Register32 // 0x6C + I2S1_INT_MAP volatile.Register32 // 0x70 + I2S2_INT_MAP volatile.Register32 // 0x74 + UHCI0_INT_MAP volatile.Register32 // 0x78 + UART0_INT_MAP volatile.Register32 // 0x7C + UART1_INT_MAP volatile.Register32 // 0x80 + UART2_INT_MAP volatile.Register32 // 0x84 + UART3_INT_MAP volatile.Register32 // 0x88 + UART4_INT_MAP volatile.Register32 // 0x8C + LCD_CAM_INT_MAP volatile.Register32 // 0x90 + ADC_INT_MAP volatile.Register32 // 0x94 + PWM0_INT_MAP volatile.Register32 // 0x98 + PWM1_INT_MAP volatile.Register32 // 0x9C + CAN0_INT_MAP volatile.Register32 // 0xA0 + CAN1_INT_MAP volatile.Register32 // 0xA4 + CAN2_INT_MAP volatile.Register32 // 0xA8 + RMT_INT_MAP volatile.Register32 // 0xAC + I2C0_INT_MAP volatile.Register32 // 0xB0 + I2C1_INT_MAP volatile.Register32 // 0xB4 + TIMERGRP0_T0_INT_MAP volatile.Register32 // 0xB8 + TIMERGRP0_T1_INT_MAP volatile.Register32 // 0xBC + TIMERGRP0_WDT_INT_MAP volatile.Register32 // 0xC0 + TIMERGRP1_T0_INT_MAP volatile.Register32 // 0xC4 + TIMERGRP1_T1_INT_MAP volatile.Register32 // 0xC8 + TIMERGRP1_WDT_INT_MAP volatile.Register32 // 0xCC + LEDC_INT_MAP volatile.Register32 // 0xD0 + SYSTIMER_TARGET0_INT_MAP volatile.Register32 // 0xD4 + SYSTIMER_TARGET1_INT_MAP volatile.Register32 // 0xD8 + SYSTIMER_TARGET2_INT_MAP volatile.Register32 // 0xDC + AHB_PDMA_IN_CH0_INT_MAP volatile.Register32 // 0xE0 + AHB_PDMA_IN_CH1_INT_MAP volatile.Register32 // 0xE4 + AHB_PDMA_IN_CH2_INT_MAP volatile.Register32 // 0xE8 + AHB_PDMA_OUT_CH0_INT_MAP volatile.Register32 // 0xEC + AHB_PDMA_OUT_CH1_INT_MAP volatile.Register32 // 0xF0 + AHB_PDMA_OUT_CH2_INT_MAP volatile.Register32 // 0xF4 + AXI_PDMA_IN_CH0_INT_MAP volatile.Register32 // 0xF8 + AXI_PDMA_IN_CH1_INT_MAP volatile.Register32 // 0xFC + AXI_PDMA_IN_CH2_INT_MAP volatile.Register32 // 0x100 + AXI_PDMA_OUT_CH0_INT_MAP volatile.Register32 // 0x104 + AXI_PDMA_OUT_CH1_INT_MAP volatile.Register32 // 0x108 + AXI_PDMA_OUT_CH2_INT_MAP volatile.Register32 // 0x10C + RSA_INT_MAP volatile.Register32 // 0x110 + AES_INT_MAP volatile.Register32 // 0x114 + SHA_INT_MAP volatile.Register32 // 0x118 + ECC_INT_MAP volatile.Register32 // 0x11C + ECDSA_INT_MAP volatile.Register32 // 0x120 + KM_INT_MAP volatile.Register32 // 0x124 + GPIO_INT0_MAP volatile.Register32 // 0x128 + GPIO_INT1_MAP volatile.Register32 // 0x12C + GPIO_INT2_MAP volatile.Register32 // 0x130 + GPIO_INT3_MAP volatile.Register32 // 0x134 + GPIO_PAD_COMP_INT_MAP volatile.Register32 // 0x138 + CPU_INT_FROM_CPU_0_MAP volatile.Register32 // 0x13C + CPU_INT_FROM_CPU_1_MAP volatile.Register32 // 0x140 + CPU_INT_FROM_CPU_2_MAP volatile.Register32 // 0x144 + CPU_INT_FROM_CPU_3_MAP volatile.Register32 // 0x148 + CACHE_INT_MAP volatile.Register32 // 0x14C + FLASH_MSPI_INT_MAP volatile.Register32 // 0x150 + CSI_BRIDGE_INT_MAP volatile.Register32 // 0x154 + DSI_BRIDGE_INT_MAP volatile.Register32 // 0x158 + CSI_INT_MAP volatile.Register32 // 0x15C + DSI_INT_MAP volatile.Register32 // 0x160 + GMII_PHY_INT_MAP volatile.Register32 // 0x164 + LPI_INT_MAP volatile.Register32 // 0x168 + PMT_INT_MAP volatile.Register32 // 0x16C + SBD_INT_MAP volatile.Register32 // 0x170 + USB_OTG_INT_MAP volatile.Register32 // 0x174 + USB_OTG_ENDP_MULTI_PROC_INT_MAP volatile.Register32 // 0x178 + JPEG_INT_MAP volatile.Register32 // 0x17C + PPA_INT_MAP volatile.Register32 // 0x180 + CORE0_TRACE_INT_MAP volatile.Register32 // 0x184 + CORE1_TRACE_INT_MAP volatile.Register32 // 0x188 + HP_CORE_CTRL_INT_MAP volatile.Register32 // 0x18C + ISP_INT_MAP volatile.Register32 // 0x190 + I3C_MST_INT_MAP volatile.Register32 // 0x194 + I3C_SLV_INT_MAP volatile.Register32 // 0x198 + USB_OTG11_INT_MAP volatile.Register32 // 0x19C + DMA2D_IN_CH0_INT_MAP volatile.Register32 // 0x1A0 + DMA2D_IN_CH1_INT_MAP volatile.Register32 // 0x1A4 + DMA2D_OUT_CH0_INT_MAP volatile.Register32 // 0x1A8 + DMA2D_OUT_CH1_INT_MAP volatile.Register32 // 0x1AC + DMA2D_OUT_CH2_INT_MAP volatile.Register32 // 0x1B0 + PSRAM_MSPI_INT_MAP volatile.Register32 // 0x1B4 + HP_SYSREG_INT_MAP volatile.Register32 // 0x1B8 + PCNT_INT_MAP volatile.Register32 // 0x1BC + HP_PAU_INT_MAP volatile.Register32 // 0x1C0 + HP_PARLIO_RX_INT_MAP volatile.Register32 // 0x1C4 + HP_PARLIO_TX_INT_MAP volatile.Register32 // 0x1C8 + H264_DMA2D_OUT_CH0_INT_MAP volatile.Register32 // 0x1CC + H264_DMA2D_OUT_CH1_INT_MAP volatile.Register32 // 0x1D0 + H264_DMA2D_OUT_CH2_INT_MAP volatile.Register32 // 0x1D4 + H264_DMA2D_OUT_CH3_INT_MAP volatile.Register32 // 0x1D8 + H264_DMA2D_OUT_CH4_INT_MAP volatile.Register32 // 0x1DC + H264_DMA2D_IN_CH0_INT_MAP volatile.Register32 // 0x1E0 + H264_DMA2D_IN_CH1_INT_MAP volatile.Register32 // 0x1E4 + H264_DMA2D_IN_CH2_INT_MAP volatile.Register32 // 0x1E8 + H264_DMA2D_IN_CH3_INT_MAP volatile.Register32 // 0x1EC + H264_DMA2D_IN_CH4_INT_MAP volatile.Register32 // 0x1F0 + H264_DMA2D_IN_CH5_INT_MAP volatile.Register32 // 0x1F4 + H264_REG_INT_MAP volatile.Register32 // 0x1F8 + ASSIST_DEBUG_INT_MAP volatile.Register32 // 0x1FC + INTR_STATUS_REG_0 volatile.Register32 // 0x200 + INTR_STATUS_REG_1 volatile.Register32 // 0x204 + INTR_STATUS_REG_2 volatile.Register32 // 0x208 + INTR_STATUS_REG_3 volatile.Register32 // 0x20C + CLOCK_GATE volatile.Register32 // 0x210 + _ [488]byte + INTERRUPT_REG_DATE volatile.Register32 // 0x3FC +} + +// CORE1.LP_RTC_INT_MAP: NA +func (o *CORE1_Type) SetLP_RTC_INT_MAP_CORE1_LP_RTC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_RTC_INT_MAP.Reg, volatile.LoadUint32(&o.LP_RTC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_RTC_INT_MAP_CORE1_LP_RTC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_RTC_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_WDT_INT_MAP: NA +func (o *CORE1_Type) SetLP_WDT_INT_MAP_CORE1_LP_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.LP_WDT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_WDT_INT_MAP_CORE1_LP_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_WDT_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_TIMER_REG_0_INT_MAP: NA +func (o *CORE1_Type) SetLP_TIMER_REG_0_INT_MAP_CORE1_LP_TIMER_REG_0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_TIMER_REG_0_INT_MAP_CORE1_LP_TIMER_REG_0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_TIMER_REG_1_INT_MAP: NA +func (o *CORE1_Type) SetLP_TIMER_REG_1_INT_MAP_CORE1_LP_TIMER_REG_1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_TIMER_REG_1_INT_MAP_CORE1_LP_TIMER_REG_1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg) & 0x3f +} + +// CORE1.MB_HP_INT_MAP: NA +func (o *CORE1_Type) SetMB_HP_INT_MAP_CORE1_MB_HP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.MB_HP_INT_MAP.Reg, volatile.LoadUint32(&o.MB_HP_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetMB_HP_INT_MAP_CORE1_MB_HP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.MB_HP_INT_MAP.Reg) & 0x3f +} + +// CORE1.MB_LP_INT_MAP: NA +func (o *CORE1_Type) SetMB_LP_INT_MAP_CORE1_MB_LP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.MB_LP_INT_MAP.Reg, volatile.LoadUint32(&o.MB_LP_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetMB_LP_INT_MAP_CORE1_MB_LP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.MB_LP_INT_MAP.Reg) & 0x3f +} + +// CORE1.PMU_REG_0_INT_MAP: NA +func (o *CORE1_Type) SetPMU_REG_0_INT_MAP_CORE1_PMU_REG_0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PMU_REG_0_INT_MAP.Reg, volatile.LoadUint32(&o.PMU_REG_0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetPMU_REG_0_INT_MAP_CORE1_PMU_REG_0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PMU_REG_0_INT_MAP.Reg) & 0x3f +} + +// CORE1.PMU_REG_1_INT_MAP: NA +func (o *CORE1_Type) SetPMU_REG_1_INT_MAP_CORE1_PMU_REG_1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PMU_REG_1_INT_MAP.Reg, volatile.LoadUint32(&o.PMU_REG_1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetPMU_REG_1_INT_MAP_CORE1_PMU_REG_1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PMU_REG_1_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_ANAPERI_INT_MAP: NA +func (o *CORE1_Type) SetLP_ANAPERI_INT_MAP_CORE1_LP_ANAPERI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_ANAPERI_INT_MAP.Reg, volatile.LoadUint32(&o.LP_ANAPERI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_ANAPERI_INT_MAP_CORE1_LP_ANAPERI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_ANAPERI_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_ADC_INT_MAP: NA +func (o *CORE1_Type) SetLP_ADC_INT_MAP_CORE1_LP_ADC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_ADC_INT_MAP.Reg, volatile.LoadUint32(&o.LP_ADC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_ADC_INT_MAP_CORE1_LP_ADC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_ADC_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_GPIO_INT_MAP: NA +func (o *CORE1_Type) SetLP_GPIO_INT_MAP_CORE1_LP_GPIO_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_GPIO_INT_MAP.Reg, volatile.LoadUint32(&o.LP_GPIO_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_GPIO_INT_MAP_CORE1_LP_GPIO_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_GPIO_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_I2C_INT_MAP: NA +func (o *CORE1_Type) SetLP_I2C_INT_MAP_CORE1_LP_I2C_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_I2C_INT_MAP.Reg, volatile.LoadUint32(&o.LP_I2C_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_I2C_INT_MAP_CORE1_LP_I2C_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_I2C_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_I2S_INT_MAP: NA +func (o *CORE1_Type) SetLP_I2S_INT_MAP_CORE1_LP_I2S_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_I2S_INT_MAP.Reg, volatile.LoadUint32(&o.LP_I2S_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_I2S_INT_MAP_CORE1_LP_I2S_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_I2S_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_SPI_INT_MAP: NA +func (o *CORE1_Type) SetLP_SPI_INT_MAP_CORE1_LP_SPI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_SPI_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SPI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_SPI_INT_MAP_CORE1_LP_SPI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_SPI_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_TOUCH_INT_MAP: NA +func (o *CORE1_Type) SetLP_TOUCH_INT_MAP_CORE1_LP_TOUCH_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TOUCH_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TOUCH_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_TOUCH_INT_MAP_CORE1_LP_TOUCH_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TOUCH_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_TSENS_INT_MAP: NA +func (o *CORE1_Type) SetLP_TSENS_INT_MAP_CORE1_LP_TSENS_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_TSENS_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TSENS_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_TSENS_INT_MAP_CORE1_LP_TSENS_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_TSENS_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_UART_INT_MAP: NA +func (o *CORE1_Type) SetLP_UART_INT_MAP_CORE1_LP_UART_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_UART_INT_MAP.Reg, volatile.LoadUint32(&o.LP_UART_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_UART_INT_MAP_CORE1_LP_UART_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_UART_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_EFUSE_INT_MAP: NA +func (o *CORE1_Type) SetLP_EFUSE_INT_MAP_CORE1_LP_EFUSE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.LP_EFUSE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_EFUSE_INT_MAP_CORE1_LP_EFUSE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_EFUSE_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_SW_INT_MAP: NA +func (o *CORE1_Type) SetLP_SW_INT_MAP_CORE1_LP_SW_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_SW_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SW_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_SW_INT_MAP_CORE1_LP_SW_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_SW_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_SYSREG_INT_MAP: NA +func (o *CORE1_Type) SetLP_SYSREG_INT_MAP_CORE1_LP_SYSREG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_SYSREG_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SYSREG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_SYSREG_INT_MAP_CORE1_LP_SYSREG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_SYSREG_INT_MAP.Reg) & 0x3f +} + +// CORE1.LP_HUK_INT_MAP: NA +func (o *CORE1_Type) SetLP_HUK_INT_MAP_CORE1_LP_HUK_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LP_HUK_INT_MAP.Reg, volatile.LoadUint32(&o.LP_HUK_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLP_HUK_INT_MAP_CORE1_LP_HUK_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LP_HUK_INT_MAP.Reg) & 0x3f +} + +// CORE1.SYS_ICM_INT_MAP: NA +func (o *CORE1_Type) SetSYS_ICM_INT_MAP_CORE1_SYS_ICM_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYS_ICM_INT_MAP.Reg, volatile.LoadUint32(&o.SYS_ICM_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetSYS_ICM_INT_MAP_CORE1_SYS_ICM_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYS_ICM_INT_MAP.Reg) & 0x3f +} + +// CORE1.USB_DEVICE_INT_MAP: NA +func (o *CORE1_Type) SetUSB_DEVICE_INT_MAP_CORE1_USB_DEVICE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_DEVICE_INT_MAP.Reg, volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUSB_DEVICE_INT_MAP_CORE1_USB_DEVICE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg) & 0x3f +} + +// CORE1.SDIO_HOST_INT_MAP: NA +func (o *CORE1_Type) SetSDIO_HOST_INT_MAP_CORE1_SDIO_HOST_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SDIO_HOST_INT_MAP.Reg, volatile.LoadUint32(&o.SDIO_HOST_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetSDIO_HOST_INT_MAP_CORE1_SDIO_HOST_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SDIO_HOST_INT_MAP.Reg) & 0x3f +} + +// CORE1.GDMA_INT_MAP: NA +func (o *CORE1_Type) SetGDMA_INT_MAP_CORE1_GDMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.GDMA_INT_MAP.Reg, volatile.LoadUint32(&o.GDMA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetGDMA_INT_MAP_CORE1_GDMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.GDMA_INT_MAP.Reg) & 0x3f +} + +// CORE1.SPI2_INT_MAP: NA +func (o *CORE1_Type) SetSPI2_INT_MAP_CORE1_SPI2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI2_INT_MAP.Reg, volatile.LoadUint32(&o.SPI2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetSPI2_INT_MAP_CORE1_SPI2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI2_INT_MAP.Reg) & 0x3f +} + +// CORE1.SPI3_INT_MAP: NA +func (o *CORE1_Type) SetSPI3_INT_MAP_CORE1_SPI3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI3_INT_MAP.Reg, volatile.LoadUint32(&o.SPI3_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetSPI3_INT_MAP_CORE1_SPI3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI3_INT_MAP.Reg) & 0x3f +} + +// CORE1.I2S0_INT_MAP: NA +func (o *CORE1_Type) SetI2S0_INT_MAP_CORE1_I2S0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S0_INT_MAP.Reg, volatile.LoadUint32(&o.I2S0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetI2S0_INT_MAP_CORE1_I2S0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S0_INT_MAP.Reg) & 0x3f +} + +// CORE1.I2S1_INT_MAP: NA +func (o *CORE1_Type) SetI2S1_INT_MAP_CORE1_I2S1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.I2S1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetI2S1_INT_MAP_CORE1_I2S1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S1_INT_MAP.Reg) & 0x3f +} + +// CORE1.I2S2_INT_MAP: NA +func (o *CORE1_Type) SetI2S2_INT_MAP_CORE1_I2S2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S2_INT_MAP.Reg, volatile.LoadUint32(&o.I2S2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetI2S2_INT_MAP_CORE1_I2S2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S2_INT_MAP.Reg) & 0x3f +} + +// CORE1.UHCI0_INT_MAP: NA +func (o *CORE1_Type) SetUHCI0_INT_MAP_CORE1_UHCI0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UHCI0_INT_MAP.Reg, volatile.LoadUint32(&o.UHCI0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUHCI0_INT_MAP_CORE1_UHCI0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UHCI0_INT_MAP.Reg) & 0x3f +} + +// CORE1.UART0_INT_MAP: NA +func (o *CORE1_Type) SetUART0_INT_MAP_CORE1_UART0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART0_INT_MAP.Reg, volatile.LoadUint32(&o.UART0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUART0_INT_MAP_CORE1_UART0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART0_INT_MAP.Reg) & 0x3f +} + +// CORE1.UART1_INT_MAP: NA +func (o *CORE1_Type) SetUART1_INT_MAP_CORE1_UART1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART1_INT_MAP.Reg, volatile.LoadUint32(&o.UART1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUART1_INT_MAP_CORE1_UART1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART1_INT_MAP.Reg) & 0x3f +} + +// CORE1.UART2_INT_MAP: NA +func (o *CORE1_Type) SetUART2_INT_MAP_CORE1_UART2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART2_INT_MAP.Reg, volatile.LoadUint32(&o.UART2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUART2_INT_MAP_CORE1_UART2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART2_INT_MAP.Reg) & 0x3f +} + +// CORE1.UART3_INT_MAP: NA +func (o *CORE1_Type) SetUART3_INT_MAP_CORE1_UART3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART3_INT_MAP.Reg, volatile.LoadUint32(&o.UART3_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUART3_INT_MAP_CORE1_UART3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART3_INT_MAP.Reg) & 0x3f +} + +// CORE1.UART4_INT_MAP: NA +func (o *CORE1_Type) SetUART4_INT_MAP_CORE1_UART4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.UART4_INT_MAP.Reg, volatile.LoadUint32(&o.UART4_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUART4_INT_MAP_CORE1_UART4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.UART4_INT_MAP.Reg) & 0x3f +} + +// CORE1.LCD_CAM_INT_MAP: NA +func (o *CORE1_Type) SetLCD_CAM_INT_MAP_CORE1_LCD_CAM_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LCD_CAM_INT_MAP.Reg, volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLCD_CAM_INT_MAP_CORE1_LCD_CAM_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg) & 0x3f +} + +// CORE1.ADC_INT_MAP: NA +func (o *CORE1_Type) SetADC_INT_MAP_CORE1_ADC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ADC_INT_MAP.Reg, volatile.LoadUint32(&o.ADC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetADC_INT_MAP_CORE1_ADC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ADC_INT_MAP.Reg) & 0x3f +} + +// CORE1.PWM0_INT_MAP: NA +func (o *CORE1_Type) SetPWM0_INT_MAP_CORE1_PWM0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PWM0_INT_MAP.Reg, volatile.LoadUint32(&o.PWM0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetPWM0_INT_MAP_CORE1_PWM0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PWM0_INT_MAP.Reg) & 0x3f +} + +// CORE1.PWM1_INT_MAP: NA +func (o *CORE1_Type) SetPWM1_INT_MAP_CORE1_PWM1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PWM1_INT_MAP.Reg, volatile.LoadUint32(&o.PWM1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetPWM1_INT_MAP_CORE1_PWM1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PWM1_INT_MAP.Reg) & 0x3f +} + +// CORE1.CAN0_INT_MAP: NA +func (o *CORE1_Type) SetCAN0_INT_MAP_CORE1_CAN0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CAN0_INT_MAP.Reg, volatile.LoadUint32(&o.CAN0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCAN0_INT_MAP_CORE1_CAN0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CAN0_INT_MAP.Reg) & 0x3f +} + +// CORE1.CAN1_INT_MAP: NA +func (o *CORE1_Type) SetCAN1_INT_MAP_CORE1_CAN1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CAN1_INT_MAP.Reg, volatile.LoadUint32(&o.CAN1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCAN1_INT_MAP_CORE1_CAN1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CAN1_INT_MAP.Reg) & 0x3f +} + +// CORE1.CAN2_INT_MAP: NA +func (o *CORE1_Type) SetCAN2_INT_MAP_CORE1_CAN2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CAN2_INT_MAP.Reg, volatile.LoadUint32(&o.CAN2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCAN2_INT_MAP_CORE1_CAN2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CAN2_INT_MAP.Reg) & 0x3f +} + +// CORE1.RMT_INT_MAP: NA +func (o *CORE1_Type) SetRMT_INT_MAP_CORE1_RMT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.RMT_INT_MAP.Reg, volatile.LoadUint32(&o.RMT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetRMT_INT_MAP_CORE1_RMT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.RMT_INT_MAP.Reg) & 0x3f +} + +// CORE1.I2C0_INT_MAP: NA +func (o *CORE1_Type) SetI2C0_INT_MAP_CORE1_I2C0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2C0_INT_MAP.Reg, volatile.LoadUint32(&o.I2C0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetI2C0_INT_MAP_CORE1_I2C0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2C0_INT_MAP.Reg) & 0x3f +} + +// CORE1.I2C1_INT_MAP: NA +func (o *CORE1_Type) SetI2C1_INT_MAP_CORE1_I2C1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2C1_INT_MAP.Reg, volatile.LoadUint32(&o.I2C1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetI2C1_INT_MAP_CORE1_I2C1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2C1_INT_MAP.Reg) & 0x3f +} + +// CORE1.TIMERGRP0_T0_INT_MAP: NA +func (o *CORE1_Type) SetTIMERGRP0_T0_INT_MAP_CORE1_TIMERGRP0_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP0_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_T0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetTIMERGRP0_T0_INT_MAP_CORE1_TIMERGRP0_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP0_T0_INT_MAP.Reg) & 0x3f +} + +// CORE1.TIMERGRP0_T1_INT_MAP: NA +func (o *CORE1_Type) SetTIMERGRP0_T1_INT_MAP_CORE1_TIMERGRP0_T1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP0_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_T1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetTIMERGRP0_T1_INT_MAP_CORE1_TIMERGRP0_T1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP0_T1_INT_MAP.Reg) & 0x3f +} + +// CORE1.TIMERGRP0_WDT_INT_MAP: NA +func (o *CORE1_Type) SetTIMERGRP0_WDT_INT_MAP_CORE1_TIMERGRP0_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetTIMERGRP0_WDT_INT_MAP_CORE1_TIMERGRP0_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg) & 0x3f +} + +// CORE1.TIMERGRP1_T0_INT_MAP: NA +func (o *CORE1_Type) SetTIMERGRP1_T0_INT_MAP_CORE1_TIMERGRP1_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP1_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_T0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetTIMERGRP1_T0_INT_MAP_CORE1_TIMERGRP1_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP1_T0_INT_MAP.Reg) & 0x3f +} + +// CORE1.TIMERGRP1_T1_INT_MAP: NA +func (o *CORE1_Type) SetTIMERGRP1_T1_INT_MAP_CORE1_TIMERGRP1_T1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP1_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_T1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetTIMERGRP1_T1_INT_MAP_CORE1_TIMERGRP1_T1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP1_T1_INT_MAP.Reg) & 0x3f +} + +// CORE1.TIMERGRP1_WDT_INT_MAP: NA +func (o *CORE1_Type) SetTIMERGRP1_WDT_INT_MAP_CORE1_TIMERGRP1_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetTIMERGRP1_WDT_INT_MAP_CORE1_TIMERGRP1_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg) & 0x3f +} + +// CORE1.LEDC_INT_MAP: NA +func (o *CORE1_Type) SetLEDC_INT_MAP_CORE1_LEDC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.LEDC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLEDC_INT_MAP_CORE1_LEDC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LEDC_INT_MAP.Reg) & 0x3f +} + +// CORE1.SYSTIMER_TARGET0_INT_MAP: NA +func (o *CORE1_Type) SetSYSTIMER_TARGET0_INT_MAP_CORE1_SYSTIMER_TARGET0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetSYSTIMER_TARGET0_INT_MAP_CORE1_SYSTIMER_TARGET0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg) & 0x3f +} + +// CORE1.SYSTIMER_TARGET1_INT_MAP: NA +func (o *CORE1_Type) SetSYSTIMER_TARGET1_INT_MAP_CORE1_SYSTIMER_TARGET1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetSYSTIMER_TARGET1_INT_MAP_CORE1_SYSTIMER_TARGET1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg) & 0x3f +} + +// CORE1.SYSTIMER_TARGET2_INT_MAP: NA +func (o *CORE1_Type) SetSYSTIMER_TARGET2_INT_MAP_CORE1_SYSTIMER_TARGET2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetSYSTIMER_TARGET2_INT_MAP_CORE1_SYSTIMER_TARGET2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg) & 0x3f +} + +// CORE1.AHB_PDMA_IN_CH0_INT_MAP: NA +func (o *CORE1_Type) SetAHB_PDMA_IN_CH0_INT_MAP_CORE1_AHB_PDMA_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAHB_PDMA_IN_CH0_INT_MAP_CORE1_AHB_PDMA_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE1.AHB_PDMA_IN_CH1_INT_MAP: NA +func (o *CORE1_Type) SetAHB_PDMA_IN_CH1_INT_MAP_CORE1_AHB_PDMA_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAHB_PDMA_IN_CH1_INT_MAP_CORE1_AHB_PDMA_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE1.AHB_PDMA_IN_CH2_INT_MAP: NA +func (o *CORE1_Type) SetAHB_PDMA_IN_CH2_INT_MAP_CORE1_AHB_PDMA_IN_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAHB_PDMA_IN_CH2_INT_MAP_CORE1_AHB_PDMA_IN_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE1.AHB_PDMA_OUT_CH0_INT_MAP: NA +func (o *CORE1_Type) SetAHB_PDMA_OUT_CH0_INT_MAP_CORE1_AHB_PDMA_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAHB_PDMA_OUT_CH0_INT_MAP_CORE1_AHB_PDMA_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE1.AHB_PDMA_OUT_CH1_INT_MAP: NA +func (o *CORE1_Type) SetAHB_PDMA_OUT_CH1_INT_MAP_CORE1_AHB_PDMA_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAHB_PDMA_OUT_CH1_INT_MAP_CORE1_AHB_PDMA_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE1.AHB_PDMA_OUT_CH2_INT_MAP: NA +func (o *CORE1_Type) SetAHB_PDMA_OUT_CH2_INT_MAP_CORE1_AHB_PDMA_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAHB_PDMA_OUT_CH2_INT_MAP_CORE1_AHB_PDMA_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE1.AXI_PDMA_IN_CH0_INT_MAP: NA +func (o *CORE1_Type) SetAXI_PDMA_IN_CH0_INT_MAP_CORE1_AXI_PDMA_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAXI_PDMA_IN_CH0_INT_MAP_CORE1_AXI_PDMA_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE1.AXI_PDMA_IN_CH1_INT_MAP: NA +func (o *CORE1_Type) SetAXI_PDMA_IN_CH1_INT_MAP_CORE1_AXI_PDMA_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAXI_PDMA_IN_CH1_INT_MAP_CORE1_AXI_PDMA_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE1.AXI_PDMA_IN_CH2_INT_MAP: NA +func (o *CORE1_Type) SetAXI_PDMA_IN_CH2_INT_MAP_CORE1_AXI_PDMA_IN_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAXI_PDMA_IN_CH2_INT_MAP_CORE1_AXI_PDMA_IN_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE1.AXI_PDMA_OUT_CH0_INT_MAP: NA +func (o *CORE1_Type) SetAXI_PDMA_OUT_CH0_INT_MAP_CORE1_AXI_PDMA_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAXI_PDMA_OUT_CH0_INT_MAP_CORE1_AXI_PDMA_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE1.AXI_PDMA_OUT_CH1_INT_MAP: NA +func (o *CORE1_Type) SetAXI_PDMA_OUT_CH1_INT_MAP_CORE1_AXI_PDMA_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAXI_PDMA_OUT_CH1_INT_MAP_CORE1_AXI_PDMA_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE1.AXI_PDMA_OUT_CH2_INT_MAP: NA +func (o *CORE1_Type) SetAXI_PDMA_OUT_CH2_INT_MAP_CORE1_AXI_PDMA_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAXI_PDMA_OUT_CH2_INT_MAP_CORE1_AXI_PDMA_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE1.RSA_INT_MAP: NA +func (o *CORE1_Type) SetRSA_INT_MAP_CORE1_RSA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.RSA_INT_MAP.Reg, volatile.LoadUint32(&o.RSA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetRSA_INT_MAP_CORE1_RSA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.RSA_INT_MAP.Reg) & 0x3f +} + +// CORE1.AES_INT_MAP: NA +func (o *CORE1_Type) SetAES_INT_MAP_CORE1_AES_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AES_INT_MAP.Reg, volatile.LoadUint32(&o.AES_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetAES_INT_MAP_CORE1_AES_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AES_INT_MAP.Reg) & 0x3f +} + +// CORE1.SHA_INT_MAP: NA +func (o *CORE1_Type) SetSHA_INT_MAP_CORE1_SHA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SHA_INT_MAP.Reg, volatile.LoadUint32(&o.SHA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetSHA_INT_MAP_CORE1_SHA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SHA_INT_MAP.Reg) & 0x3f +} + +// CORE1.ECC_INT_MAP: NA +func (o *CORE1_Type) SetECC_INT_MAP_CORE1_ECC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ECC_INT_MAP.Reg, volatile.LoadUint32(&o.ECC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetECC_INT_MAP_CORE1_ECC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ECC_INT_MAP.Reg) & 0x3f +} + +// CORE1.ECDSA_INT_MAP: NA +func (o *CORE1_Type) SetECDSA_INT_MAP_CORE1_ECDSA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ECDSA_INT_MAP.Reg, volatile.LoadUint32(&o.ECDSA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetECDSA_INT_MAP_CORE1_ECDSA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ECDSA_INT_MAP.Reg) & 0x3f +} + +// CORE1.KM_INT_MAP: NA +func (o *CORE1_Type) SetKM_INT_MAP_CORE1_KM_INT_MAP(value uint32) { + volatile.StoreUint32(&o.KM_INT_MAP.Reg, volatile.LoadUint32(&o.KM_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetKM_INT_MAP_CORE1_KM_INT_MAP() uint32 { + return volatile.LoadUint32(&o.KM_INT_MAP.Reg) & 0x3f +} + +// CORE1.GPIO_INT0_MAP: NA +func (o *CORE1_Type) SetGPIO_INT0_MAP_CORE1_GPIO_INT0_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INT0_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT0_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetGPIO_INT0_MAP_CORE1_GPIO_INT0_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INT0_MAP.Reg) & 0x3f +} + +// CORE1.GPIO_INT1_MAP: NA +func (o *CORE1_Type) SetGPIO_INT1_MAP_CORE1_GPIO_INT1_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INT1_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT1_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetGPIO_INT1_MAP_CORE1_GPIO_INT1_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INT1_MAP.Reg) & 0x3f +} + +// CORE1.GPIO_INT2_MAP: NA +func (o *CORE1_Type) SetGPIO_INT2_MAP_CORE1_GPIO_INT2_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INT2_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT2_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetGPIO_INT2_MAP_CORE1_GPIO_INT2_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INT2_MAP.Reg) & 0x3f +} + +// CORE1.GPIO_INT3_MAP: NA +func (o *CORE1_Type) SetGPIO_INT3_MAP_CORE1_GPIO_INT3_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INT3_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT3_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetGPIO_INT3_MAP_CORE1_GPIO_INT3_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INT3_MAP.Reg) & 0x3f +} + +// CORE1.GPIO_PAD_COMP_INT_MAP: NA +func (o *CORE1_Type) SetGPIO_PAD_COMP_INT_MAP_CORE1_GPIO_PAD_COMP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg, volatile.LoadUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetGPIO_PAD_COMP_INT_MAP_CORE1_GPIO_PAD_COMP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg) & 0x3f +} + +// CORE1.CPU_INT_FROM_CPU_0_MAP: NA +func (o *CORE1_Type) SetCPU_INT_FROM_CPU_0_MAP_CORE1_CPU_INT_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCPU_INT_FROM_CPU_0_MAP_CORE1_CPU_INT_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg) & 0x3f +} + +// CORE1.CPU_INT_FROM_CPU_1_MAP: NA +func (o *CORE1_Type) SetCPU_INT_FROM_CPU_1_MAP_CORE1_CPU_INT_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCPU_INT_FROM_CPU_1_MAP_CORE1_CPU_INT_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg) & 0x3f +} + +// CORE1.CPU_INT_FROM_CPU_2_MAP: NA +func (o *CORE1_Type) SetCPU_INT_FROM_CPU_2_MAP_CORE1_CPU_INT_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCPU_INT_FROM_CPU_2_MAP_CORE1_CPU_INT_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg) & 0x3f +} + +// CORE1.CPU_INT_FROM_CPU_3_MAP: NA +func (o *CORE1_Type) SetCPU_INT_FROM_CPU_3_MAP_CORE1_CPU_INT_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCPU_INT_FROM_CPU_3_MAP_CORE1_CPU_INT_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg) & 0x3f +} + +// CORE1.CACHE_INT_MAP: NA +func (o *CORE1_Type) SetCACHE_INT_MAP_CORE1_CACHE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCACHE_INT_MAP_CORE1_CACHE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_INT_MAP.Reg) & 0x3f +} + +// CORE1.FLASH_MSPI_INT_MAP: NA +func (o *CORE1_Type) SetFLASH_MSPI_INT_MAP_CORE1_FLASH_MSPI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.FLASH_MSPI_INT_MAP.Reg, volatile.LoadUint32(&o.FLASH_MSPI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetFLASH_MSPI_INT_MAP_CORE1_FLASH_MSPI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.FLASH_MSPI_INT_MAP.Reg) & 0x3f +} + +// CORE1.CSI_BRIDGE_INT_MAP: NA +func (o *CORE1_Type) SetCSI_BRIDGE_INT_MAP_CORE1_CSI_BRIDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CSI_BRIDGE_INT_MAP.Reg, volatile.LoadUint32(&o.CSI_BRIDGE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCSI_BRIDGE_INT_MAP_CORE1_CSI_BRIDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CSI_BRIDGE_INT_MAP.Reg) & 0x3f +} + +// CORE1.DSI_BRIDGE_INT_MAP: NA +func (o *CORE1_Type) SetDSI_BRIDGE_INT_MAP_CORE1_DSI_BRIDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DSI_BRIDGE_INT_MAP.Reg, volatile.LoadUint32(&o.DSI_BRIDGE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetDSI_BRIDGE_INT_MAP_CORE1_DSI_BRIDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DSI_BRIDGE_INT_MAP.Reg) & 0x3f +} + +// CORE1.CSI_INT_MAP: NA +func (o *CORE1_Type) SetCSI_INT_MAP_CORE1_CSI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CSI_INT_MAP.Reg, volatile.LoadUint32(&o.CSI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCSI_INT_MAP_CORE1_CSI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CSI_INT_MAP.Reg) & 0x3f +} + +// CORE1.DSI_INT_MAP: NA +func (o *CORE1_Type) SetDSI_INT_MAP_CORE1_DSI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DSI_INT_MAP.Reg, volatile.LoadUint32(&o.DSI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetDSI_INT_MAP_CORE1_DSI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DSI_INT_MAP.Reg) & 0x3f +} + +// CORE1.GMII_PHY_INT_MAP: NA +func (o *CORE1_Type) SetGMII_PHY_INT_MAP_CORE1_GMII_PHY_INT_MAP(value uint32) { + volatile.StoreUint32(&o.GMII_PHY_INT_MAP.Reg, volatile.LoadUint32(&o.GMII_PHY_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetGMII_PHY_INT_MAP_CORE1_GMII_PHY_INT_MAP() uint32 { + return volatile.LoadUint32(&o.GMII_PHY_INT_MAP.Reg) & 0x3f +} + +// CORE1.LPI_INT_MAP: NA +func (o *CORE1_Type) SetLPI_INT_MAP_CORE1_LPI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LPI_INT_MAP.Reg, volatile.LoadUint32(&o.LPI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetLPI_INT_MAP_CORE1_LPI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LPI_INT_MAP.Reg) & 0x3f +} + +// CORE1.PMT_INT_MAP: NA +func (o *CORE1_Type) SetPMT_INT_MAP_CORE1_PMT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PMT_INT_MAP.Reg, volatile.LoadUint32(&o.PMT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetPMT_INT_MAP_CORE1_PMT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PMT_INT_MAP.Reg) & 0x3f +} + +// CORE1.SBD_INT_MAP: NA +func (o *CORE1_Type) SetSBD_INT_MAP_CORE1_SBD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SBD_INT_MAP.Reg, volatile.LoadUint32(&o.SBD_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetSBD_INT_MAP_CORE1_SBD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SBD_INT_MAP.Reg) & 0x3f +} + +// CORE1.USB_OTG_INT_MAP: NA +func (o *CORE1_Type) SetUSB_OTG_INT_MAP_CORE1_USB_OTG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_OTG_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUSB_OTG_INT_MAP_CORE1_USB_OTG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_OTG_INT_MAP.Reg) & 0x3f +} + +// CORE1.USB_OTG_ENDP_MULTI_PROC_INT_MAP: NA +func (o *CORE1_Type) SetUSB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUSB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg) & 0x3f +} + +// CORE1.JPEG_INT_MAP: NA +func (o *CORE1_Type) SetJPEG_INT_MAP_CORE1_JPEG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.JPEG_INT_MAP.Reg, volatile.LoadUint32(&o.JPEG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetJPEG_INT_MAP_CORE1_JPEG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.JPEG_INT_MAP.Reg) & 0x3f +} + +// CORE1.PPA_INT_MAP: NA +func (o *CORE1_Type) SetPPA_INT_MAP_CORE1_PPA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PPA_INT_MAP.Reg, volatile.LoadUint32(&o.PPA_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetPPA_INT_MAP_CORE1_PPA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PPA_INT_MAP.Reg) & 0x3f +} + +// CORE1.CORE0_TRACE_INT_MAP: NA +func (o *CORE1_Type) SetCORE0_TRACE_INT_MAP_CORE1_CORE0_TRACE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CORE0_TRACE_INT_MAP.Reg, volatile.LoadUint32(&o.CORE0_TRACE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCORE0_TRACE_INT_MAP_CORE1_CORE0_TRACE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CORE0_TRACE_INT_MAP.Reg) & 0x3f +} + +// CORE1.CORE1_TRACE_INT_MAP: NA +func (o *CORE1_Type) SetCORE1_TRACE_INT_MAP_CORE1_CORE1_TRACE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CORE1_TRACE_INT_MAP.Reg, volatile.LoadUint32(&o.CORE1_TRACE_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetCORE1_TRACE_INT_MAP_CORE1_CORE1_TRACE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CORE1_TRACE_INT_MAP.Reg) & 0x3f +} + +// CORE1.HP_CORE_CTRL_INT_MAP: NA +func (o *CORE1_Type) SetHP_CORE_CTRL_INT_MAP_CORE1_HP_CORE_CTRL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_CORE_CTRL_INT_MAP.Reg, volatile.LoadUint32(&o.HP_CORE_CTRL_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetHP_CORE_CTRL_INT_MAP_CORE1_HP_CORE_CTRL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_CORE_CTRL_INT_MAP.Reg) & 0x3f +} + +// CORE1.ISP_INT_MAP: NA +func (o *CORE1_Type) SetISP_INT_MAP_CORE1_ISP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ISP_INT_MAP.Reg, volatile.LoadUint32(&o.ISP_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetISP_INT_MAP_CORE1_ISP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ISP_INT_MAP.Reg) & 0x3f +} + +// CORE1.I3C_MST_INT_MAP: NA +func (o *CORE1_Type) SetI3C_MST_INT_MAP_CORE1_I3C_MST_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I3C_MST_INT_MAP.Reg, volatile.LoadUint32(&o.I3C_MST_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetI3C_MST_INT_MAP_CORE1_I3C_MST_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I3C_MST_INT_MAP.Reg) & 0x3f +} + +// CORE1.I3C_SLV_INT_MAP: NA +func (o *CORE1_Type) SetI3C_SLV_INT_MAP_CORE1_I3C_SLV_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I3C_SLV_INT_MAP.Reg, volatile.LoadUint32(&o.I3C_SLV_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetI3C_SLV_INT_MAP_CORE1_I3C_SLV_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I3C_SLV_INT_MAP.Reg) & 0x3f +} + +// CORE1.USB_OTG11_INT_MAP: NA +func (o *CORE1_Type) SetUSB_OTG11_INT_MAP_CORE1_USB_OTG11_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_OTG11_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG11_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetUSB_OTG11_INT_MAP_CORE1_USB_OTG11_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_OTG11_INT_MAP.Reg) & 0x3f +} + +// CORE1.DMA2D_IN_CH0_INT_MAP: NA +func (o *CORE1_Type) SetDMA2D_IN_CH0_INT_MAP_CORE1_DMA2D_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetDMA2D_IN_CH0_INT_MAP_CORE1_DMA2D_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE1.DMA2D_IN_CH1_INT_MAP: NA +func (o *CORE1_Type) SetDMA2D_IN_CH1_INT_MAP_CORE1_DMA2D_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetDMA2D_IN_CH1_INT_MAP_CORE1_DMA2D_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE1.DMA2D_OUT_CH0_INT_MAP: NA +func (o *CORE1_Type) SetDMA2D_OUT_CH0_INT_MAP_CORE1_DMA2D_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetDMA2D_OUT_CH0_INT_MAP_CORE1_DMA2D_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE1.DMA2D_OUT_CH1_INT_MAP: NA +func (o *CORE1_Type) SetDMA2D_OUT_CH1_INT_MAP_CORE1_DMA2D_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetDMA2D_OUT_CH1_INT_MAP_CORE1_DMA2D_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE1.DMA2D_OUT_CH2_INT_MAP: NA +func (o *CORE1_Type) SetDMA2D_OUT_CH2_INT_MAP_CORE1_DMA2D_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetDMA2D_OUT_CH2_INT_MAP_CORE1_DMA2D_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE1.PSRAM_MSPI_INT_MAP: NA +func (o *CORE1_Type) SetPSRAM_MSPI_INT_MAP_CORE1_PSRAM_MSPI_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PSRAM_MSPI_INT_MAP.Reg, volatile.LoadUint32(&o.PSRAM_MSPI_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetPSRAM_MSPI_INT_MAP_CORE1_PSRAM_MSPI_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PSRAM_MSPI_INT_MAP.Reg) & 0x3f +} + +// CORE1.HP_SYSREG_INT_MAP: NA +func (o *CORE1_Type) SetHP_SYSREG_INT_MAP_CORE1_HP_SYSREG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_SYSREG_INT_MAP.Reg, volatile.LoadUint32(&o.HP_SYSREG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetHP_SYSREG_INT_MAP_CORE1_HP_SYSREG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_SYSREG_INT_MAP.Reg) & 0x3f +} + +// CORE1.PCNT_INT_MAP: NA +func (o *CORE1_Type) SetPCNT_INT_MAP_CORE1_PCNT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PCNT_INT_MAP.Reg, volatile.LoadUint32(&o.PCNT_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetPCNT_INT_MAP_CORE1_PCNT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PCNT_INT_MAP.Reg) & 0x3f +} + +// CORE1.HP_PAU_INT_MAP: NA +func (o *CORE1_Type) SetHP_PAU_INT_MAP_CORE1_HP_PAU_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_PAU_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PAU_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetHP_PAU_INT_MAP_CORE1_HP_PAU_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_PAU_INT_MAP.Reg) & 0x3f +} + +// CORE1.HP_PARLIO_RX_INT_MAP: NA +func (o *CORE1_Type) SetHP_PARLIO_RX_INT_MAP_CORE1_HP_PARLIO_RX_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_PARLIO_RX_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PARLIO_RX_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetHP_PARLIO_RX_INT_MAP_CORE1_HP_PARLIO_RX_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_PARLIO_RX_INT_MAP.Reg) & 0x3f +} + +// CORE1.HP_PARLIO_TX_INT_MAP: NA +func (o *CORE1_Type) SetHP_PARLIO_TX_INT_MAP_CORE1_HP_PARLIO_TX_INT_MAP(value uint32) { + volatile.StoreUint32(&o.HP_PARLIO_TX_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PARLIO_TX_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetHP_PARLIO_TX_INT_MAP_CORE1_HP_PARLIO_TX_INT_MAP() uint32 { + return volatile.LoadUint32(&o.HP_PARLIO_TX_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_OUT_CH0_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_OUT_CH0_INT_MAP_CORE1_H264_DMA2D_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_OUT_CH0_INT_MAP_CORE1_H264_DMA2D_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_OUT_CH1_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_OUT_CH1_INT_MAP_CORE1_H264_DMA2D_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_OUT_CH1_INT_MAP_CORE1_H264_DMA2D_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_OUT_CH2_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_OUT_CH2_INT_MAP_CORE1_H264_DMA2D_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_OUT_CH2_INT_MAP_CORE1_H264_DMA2D_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_OUT_CH3_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_OUT_CH3_INT_MAP_CORE1_H264_DMA2D_OUT_CH3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_OUT_CH3_INT_MAP_CORE1_H264_DMA2D_OUT_CH3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_OUT_CH4_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_OUT_CH4_INT_MAP_CORE1_H264_DMA2D_OUT_CH4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_OUT_CH4_INT_MAP_CORE1_H264_DMA2D_OUT_CH4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_IN_CH0_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_IN_CH0_INT_MAP_CORE1_H264_DMA2D_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_IN_CH0_INT_MAP_CORE1_H264_DMA2D_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_IN_CH1_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_IN_CH1_INT_MAP_CORE1_H264_DMA2D_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_IN_CH1_INT_MAP_CORE1_H264_DMA2D_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_IN_CH2_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_IN_CH2_INT_MAP_CORE1_H264_DMA2D_IN_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_IN_CH2_INT_MAP_CORE1_H264_DMA2D_IN_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_IN_CH3_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_IN_CH3_INT_MAP_CORE1_H264_DMA2D_IN_CH3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_IN_CH3_INT_MAP_CORE1_H264_DMA2D_IN_CH3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_IN_CH4_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_IN_CH4_INT_MAP_CORE1_H264_DMA2D_IN_CH4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_IN_CH4_INT_MAP_CORE1_H264_DMA2D_IN_CH4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_DMA2D_IN_CH5_INT_MAP: NA +func (o *CORE1_Type) SetH264_DMA2D_IN_CH5_INT_MAP_CORE1_H264_DMA2D_IN_CH5_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_DMA2D_IN_CH5_INT_MAP_CORE1_H264_DMA2D_IN_CH5_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg) & 0x3f +} + +// CORE1.H264_REG_INT_MAP: NA +func (o *CORE1_Type) SetH264_REG_INT_MAP_CORE1_H264_REG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.H264_REG_INT_MAP.Reg, volatile.LoadUint32(&o.H264_REG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetH264_REG_INT_MAP_CORE1_H264_REG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.H264_REG_INT_MAP.Reg) & 0x3f +} + +// CORE1.ASSIST_DEBUG_INT_MAP: NA +func (o *CORE1_Type) SetASSIST_DEBUG_INT_MAP_CORE1_ASSIST_DEBUG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ASSIST_DEBUG_INT_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INT_MAP.Reg)&^(0x3f)|value) +} +func (o *CORE1_Type) GetASSIST_DEBUG_INT_MAP_CORE1_ASSIST_DEBUG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ASSIST_DEBUG_INT_MAP.Reg) & 0x3f +} + +// CORE1.INTR_STATUS_REG_0: NA +func (o *CORE1_Type) SetINTR_STATUS_REG_0(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_0.Reg, value) +} +func (o *CORE1_Type) GetINTR_STATUS_REG_0() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_0.Reg) +} + +// CORE1.INTR_STATUS_REG_1: NA +func (o *CORE1_Type) SetINTR_STATUS_REG_1(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_1.Reg, value) +} +func (o *CORE1_Type) GetINTR_STATUS_REG_1() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_1.Reg) +} + +// CORE1.INTR_STATUS_REG_2: NA +func (o *CORE1_Type) SetINTR_STATUS_REG_2(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_2.Reg, value) +} +func (o *CORE1_Type) GetINTR_STATUS_REG_2() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_2.Reg) +} + +// CORE1.INTR_STATUS_REG_3: NA +func (o *CORE1_Type) SetINTR_STATUS_REG_3(value uint32) { + volatile.StoreUint32(&o.INTR_STATUS_REG_3.Reg, value) +} +func (o *CORE1_Type) GetINTR_STATUS_REG_3() uint32 { + return volatile.LoadUint32(&o.INTR_STATUS_REG_3.Reg) +} + +// CORE1.CLOCK_GATE: NA +func (o *CORE1_Type) SetCLOCK_GATE_CORE1_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *CORE1_Type) GetCLOCK_GATE_CORE1_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// CORE1.INTERRUPT_REG_DATE: NA +func (o *CORE1_Type) SetINTERRUPT_REG_DATE_CORE1_INTERRUPT_REG_DATE(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_REG_DATE.Reg, volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *CORE1_Type) GetINTERRUPT_REG_DATE_CORE1_INTERRUPT_REG_DATE() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg) & 0xfffffff +} + +// MIPI Camera Interface Bridge +type CSI_BRIG_Type struct { + CLK_EN volatile.Register32 // 0x0 + CSI_EN volatile.Register32 // 0x4 + DMA_REQ_CFG volatile.Register32 // 0x8 + BUF_FLOW_CTL volatile.Register32 // 0xC + DATA_TYPE_CFG volatile.Register32 // 0x10 + FRAME_CFG volatile.Register32 // 0x14 + ENDIAN_MODE volatile.Register32 // 0x18 + INT_RAW volatile.Register32 // 0x1C + INT_CLR volatile.Register32 // 0x20 + INT_ST volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + DMA_REQ_INTERVAL volatile.Register32 // 0x2C + DMABLK_SIZE volatile.Register32 // 0x30 + RDN_ECO_CS volatile.Register32 // 0x34 + RDN_ECO_LOW volatile.Register32 // 0x38 + RDN_ECO_HIGH volatile.Register32 // 0x3C + HOST_CTRL volatile.Register32 // 0x40 + MEM_CTRL volatile.Register32 // 0x44 +} + +// CSI_BRIG.CLK_EN: csi bridge register mapping unit clock gating. +func (o *CSI_BRIG_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1 +} + +// CSI_BRIG.CSI_EN: csi bridge enable. +func (o *CSI_BRIG_Type) SetCSI_EN_CSI_BRIG_EN(value uint32) { + volatile.StoreUint32(&o.CSI_EN.Reg, volatile.LoadUint32(&o.CSI_EN.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetCSI_EN_CSI_BRIG_EN() uint32 { + return volatile.LoadUint32(&o.CSI_EN.Reg) & 0x1 +} + +// CSI_BRIG.DMA_REQ_CFG: dma request configuration. +func (o *CSI_BRIG_Type) SetDMA_REQ_CFG_DMA_BURST_LEN(value uint32) { + volatile.StoreUint32(&o.DMA_REQ_CFG.Reg, volatile.LoadUint32(&o.DMA_REQ_CFG.Reg)&^(0xfff)|value) +} +func (o *CSI_BRIG_Type) GetDMA_REQ_CFG_DMA_BURST_LEN() uint32 { + return volatile.LoadUint32(&o.DMA_REQ_CFG.Reg) & 0xfff +} +func (o *CSI_BRIG_Type) SetDMA_REQ_CFG_DMA_CFG_UPD_BY_BLK(value uint32) { + volatile.StoreUint32(&o.DMA_REQ_CFG.Reg, volatile.LoadUint32(&o.DMA_REQ_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_BRIG_Type) GetDMA_REQ_CFG_DMA_CFG_UPD_BY_BLK() uint32 { + return (volatile.LoadUint32(&o.DMA_REQ_CFG.Reg) & 0x1000) >> 12 +} +func (o *CSI_BRIG_Type) SetDMA_REQ_CFG_DMA_FORCE_RD_STATUS(value uint32) { + volatile.StoreUint32(&o.DMA_REQ_CFG.Reg, volatile.LoadUint32(&o.DMA_REQ_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *CSI_BRIG_Type) GetDMA_REQ_CFG_DMA_FORCE_RD_STATUS() uint32 { + return (volatile.LoadUint32(&o.DMA_REQ_CFG.Reg) & 0x10000) >> 16 +} + +// CSI_BRIG.BUF_FLOW_CTL: csi bridge buffer control. +func (o *CSI_BRIG_Type) SetBUF_FLOW_CTL_CSI_BUF_AFULL_THRD(value uint32) { + volatile.StoreUint32(&o.BUF_FLOW_CTL.Reg, volatile.LoadUint32(&o.BUF_FLOW_CTL.Reg)&^(0x3fff)|value) +} +func (o *CSI_BRIG_Type) GetBUF_FLOW_CTL_CSI_BUF_AFULL_THRD() uint32 { + return volatile.LoadUint32(&o.BUF_FLOW_CTL.Reg) & 0x3fff +} +func (o *CSI_BRIG_Type) SetBUF_FLOW_CTL_CSI_BUF_DEPTH(value uint32) { + volatile.StoreUint32(&o.BUF_FLOW_CTL.Reg, volatile.LoadUint32(&o.BUF_FLOW_CTL.Reg)&^(0x3fff0000)|value<<16) +} +func (o *CSI_BRIG_Type) GetBUF_FLOW_CTL_CSI_BUF_DEPTH() uint32 { + return (volatile.LoadUint32(&o.BUF_FLOW_CTL.Reg) & 0x3fff0000) >> 16 +} + +// CSI_BRIG.DATA_TYPE_CFG: pixel data type configuration. +func (o *CSI_BRIG_Type) SetDATA_TYPE_CFG_DATA_TYPE_MIN(value uint32) { + volatile.StoreUint32(&o.DATA_TYPE_CFG.Reg, volatile.LoadUint32(&o.DATA_TYPE_CFG.Reg)&^(0x3f)|value) +} +func (o *CSI_BRIG_Type) GetDATA_TYPE_CFG_DATA_TYPE_MIN() uint32 { + return volatile.LoadUint32(&o.DATA_TYPE_CFG.Reg) & 0x3f +} +func (o *CSI_BRIG_Type) SetDATA_TYPE_CFG_DATA_TYPE_MAX(value uint32) { + volatile.StoreUint32(&o.DATA_TYPE_CFG.Reg, volatile.LoadUint32(&o.DATA_TYPE_CFG.Reg)&^(0x3f00)|value<<8) +} +func (o *CSI_BRIG_Type) GetDATA_TYPE_CFG_DATA_TYPE_MAX() uint32 { + return (volatile.LoadUint32(&o.DATA_TYPE_CFG.Reg) & 0x3f00) >> 8 +} + +// CSI_BRIG.FRAME_CFG: frame configuration. +func (o *CSI_BRIG_Type) SetFRAME_CFG_VADR_NUM(value uint32) { + volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0xfff)|value) +} +func (o *CSI_BRIG_Type) GetFRAME_CFG_VADR_NUM() uint32 { + return volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0xfff +} +func (o *CSI_BRIG_Type) SetFRAME_CFG_HADR_NUM(value uint32) { + volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0xfff000)|value<<12) +} +func (o *CSI_BRIG_Type) GetFRAME_CFG_HADR_NUM() uint32 { + return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0xfff000) >> 12 +} +func (o *CSI_BRIG_Type) SetFRAME_CFG_HAS_HSYNC_E(value uint32) { + volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *CSI_BRIG_Type) GetFRAME_CFG_HAS_HSYNC_E() uint32 { + return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x1000000) >> 24 +} +func (o *CSI_BRIG_Type) SetFRAME_CFG_VADR_NUM_CHECK(value uint32) { + volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x2000000)|value<<25) +} +func (o *CSI_BRIG_Type) GetFRAME_CFG_VADR_NUM_CHECK() uint32 { + return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x2000000) >> 25 +} + +// CSI_BRIG.ENDIAN_MODE: data endianness order configuration. +func (o *CSI_BRIG_Type) SetENDIAN_MODE_BYTE_ENDIAN_ORDER(value uint32) { + volatile.StoreUint32(&o.ENDIAN_MODE.Reg, volatile.LoadUint32(&o.ENDIAN_MODE.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetENDIAN_MODE_BYTE_ENDIAN_ORDER() uint32 { + return volatile.LoadUint32(&o.ENDIAN_MODE.Reg) & 0x1 +} +func (o *CSI_BRIG_Type) SetENDIAN_MODE_BIT_ENDIAN_ORDER(value uint32) { + volatile.StoreUint32(&o.ENDIAN_MODE.Reg, volatile.LoadUint32(&o.ENDIAN_MODE.Reg)&^(0x2)|value<<1) +} +func (o *CSI_BRIG_Type) GetENDIAN_MODE_BIT_ENDIAN_ORDER() uint32 { + return (volatile.LoadUint32(&o.ENDIAN_MODE.Reg) & 0x2) >> 1 +} + +// CSI_BRIG.INT_RAW: csi bridge interrupt raw. +func (o *CSI_BRIG_Type) SetINT_RAW_VADR_NUM_GT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetINT_RAW_VADR_NUM_GT_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *CSI_BRIG_Type) SetINT_RAW_VADR_NUM_LT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *CSI_BRIG_Type) GetINT_RAW_VADR_NUM_LT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *CSI_BRIG_Type) SetINT_RAW_DISCARD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *CSI_BRIG_Type) GetINT_RAW_DISCARD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *CSI_BRIG_Type) SetINT_RAW_CSI_BUF_OVERRUN_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *CSI_BRIG_Type) GetINT_RAW_CSI_BUF_OVERRUN_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *CSI_BRIG_Type) SetINT_RAW_CSI_ASYNC_FIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *CSI_BRIG_Type) GetINT_RAW_CSI_ASYNC_FIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *CSI_BRIG_Type) SetINT_RAW_DMA_CFG_HAS_UPDATED_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *CSI_BRIG_Type) GetINT_RAW_DMA_CFG_HAS_UPDATED_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} + +// CSI_BRIG.INT_CLR: csi bridge interrupt clr. +func (o *CSI_BRIG_Type) SetINT_CLR_VADR_NUM_GT_REAL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetINT_CLR_VADR_NUM_GT_REAL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *CSI_BRIG_Type) SetINT_CLR_VADR_NUM_LT_REAL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *CSI_BRIG_Type) GetINT_CLR_VADR_NUM_LT_REAL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *CSI_BRIG_Type) SetINT_CLR_DISCARD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *CSI_BRIG_Type) GetINT_CLR_DISCARD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *CSI_BRIG_Type) SetINT_CLR_CSI_BUF_OVERRUN_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *CSI_BRIG_Type) GetINT_CLR_CSI_BUF_OVERRUN_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *CSI_BRIG_Type) SetINT_CLR_CSI_ASYNC_FIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *CSI_BRIG_Type) GetINT_CLR_CSI_ASYNC_FIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *CSI_BRIG_Type) SetINT_CLR_DMA_CFG_HAS_UPDATED_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *CSI_BRIG_Type) GetINT_CLR_DMA_CFG_HAS_UPDATED_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} + +// CSI_BRIG.INT_ST: csi bridge interrupt st. +func (o *CSI_BRIG_Type) SetINT_ST_VADR_NUM_GT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetINT_ST_VADR_NUM_GT_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *CSI_BRIG_Type) SetINT_ST_VADR_NUM_LT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *CSI_BRIG_Type) GetINT_ST_VADR_NUM_LT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *CSI_BRIG_Type) SetINT_ST_DISCARD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *CSI_BRIG_Type) GetINT_ST_DISCARD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *CSI_BRIG_Type) SetINT_ST_CSI_BUF_OVERRUN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *CSI_BRIG_Type) GetINT_ST_CSI_BUF_OVERRUN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *CSI_BRIG_Type) SetINT_ST_CSI_ASYNC_FIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *CSI_BRIG_Type) GetINT_ST_CSI_ASYNC_FIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *CSI_BRIG_Type) SetINT_ST_DMA_CFG_HAS_UPDATED_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *CSI_BRIG_Type) GetINT_ST_DMA_CFG_HAS_UPDATED_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} + +// CSI_BRIG.INT_ENA: csi bridge interrupt enable. +func (o *CSI_BRIG_Type) SetINT_ENA_VADR_NUM_GT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetINT_ENA_VADR_NUM_GT_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *CSI_BRIG_Type) SetINT_ENA_VADR_NUM_LT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *CSI_BRIG_Type) GetINT_ENA_VADR_NUM_LT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *CSI_BRIG_Type) SetINT_ENA_DISCARD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *CSI_BRIG_Type) GetINT_ENA_DISCARD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *CSI_BRIG_Type) SetINT_ENA_CSI_BUF_OVERRUN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *CSI_BRIG_Type) GetINT_ENA_CSI_BUF_OVERRUN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *CSI_BRIG_Type) SetINT_ENA_CSI_ASYNC_FIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *CSI_BRIG_Type) GetINT_ENA_CSI_ASYNC_FIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *CSI_BRIG_Type) SetINT_ENA_DMA_CFG_HAS_UPDATED_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *CSI_BRIG_Type) GetINT_ENA_DMA_CFG_HAS_UPDATED_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} + +// CSI_BRIG.DMA_REQ_INTERVAL: DMA interval configuration. +func (o *CSI_BRIG_Type) SetDMA_REQ_INTERVAL(value uint32) { + volatile.StoreUint32(&o.DMA_REQ_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_REQ_INTERVAL.Reg)&^(0xffff)|value) +} +func (o *CSI_BRIG_Type) GetDMA_REQ_INTERVAL() uint32 { + return volatile.LoadUint32(&o.DMA_REQ_INTERVAL.Reg) & 0xffff +} + +// CSI_BRIG.DMABLK_SIZE: DMA block size configuration. +func (o *CSI_BRIG_Type) SetDMABLK_SIZE(value uint32) { + volatile.StoreUint32(&o.DMABLK_SIZE.Reg, volatile.LoadUint32(&o.DMABLK_SIZE.Reg)&^(0x1fff)|value) +} +func (o *CSI_BRIG_Type) GetDMABLK_SIZE() uint32 { + return volatile.LoadUint32(&o.DMABLK_SIZE.Reg) & 0x1fff +} + +// CSI_BRIG.RDN_ECO_CS: N/A +func (o *CSI_BRIG_Type) SetRDN_ECO_CS_RDN_ECO_EN(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetRDN_ECO_CS_RDN_ECO_EN() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x1 +} +func (o *CSI_BRIG_Type) SetRDN_ECO_CS_RDN_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *CSI_BRIG_Type) GetRDN_ECO_CS_RDN_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x2) >> 1 +} + +// CSI_BRIG.RDN_ECO_LOW: N/A +func (o *CSI_BRIG_Type) SetRDN_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_LOW.Reg, value) +} +func (o *CSI_BRIG_Type) GetRDN_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_LOW.Reg) +} + +// CSI_BRIG.RDN_ECO_HIGH: N/A +func (o *CSI_BRIG_Type) SetRDN_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_HIGH.Reg, value) +} +func (o *CSI_BRIG_Type) GetRDN_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_HIGH.Reg) +} + +// CSI_BRIG.HOST_CTRL: csi host control by csi bridge. +func (o *CSI_BRIG_Type) SetHOST_CTRL_CSI_ENABLECLK(value uint32) { + volatile.StoreUint32(&o.HOST_CTRL.Reg, volatile.LoadUint32(&o.HOST_CTRL.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetHOST_CTRL_CSI_ENABLECLK() uint32 { + return volatile.LoadUint32(&o.HOST_CTRL.Reg) & 0x1 +} +func (o *CSI_BRIG_Type) SetHOST_CTRL_CSI_CFG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.HOST_CTRL.Reg, volatile.LoadUint32(&o.HOST_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_BRIG_Type) GetHOST_CTRL_CSI_CFG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.HOST_CTRL.Reg) & 0x2) >> 1 +} +func (o *CSI_BRIG_Type) SetHOST_CTRL_LOOPBK_TEST_EN(value uint32) { + volatile.StoreUint32(&o.HOST_CTRL.Reg, volatile.LoadUint32(&o.HOST_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_BRIG_Type) GetHOST_CTRL_LOOPBK_TEST_EN() uint32 { + return (volatile.LoadUint32(&o.HOST_CTRL.Reg) & 0x4) >> 2 +} + +// CSI_BRIG.MEM_CTRL: csi bridge buffer control. +func (o *CSI_BRIG_Type) SetMEM_CTRL_CSI_BRIDGE_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x1)|value) +} +func (o *CSI_BRIG_Type) GetMEM_CTRL_CSI_BRIDGE_MEM_CLK_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x1 +} +func (o *CSI_BRIG_Type) SetMEM_CTRL_CSI_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x7ffe)|value<<1) +} +func (o *CSI_BRIG_Type) GetMEM_CTRL_CSI_MEM_AUX_CTRL() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x7ffe) >> 1 +} + +// MIPI Camera Interface Host +type CSI_HOST_Type struct { + VERSION volatile.Register32 // 0x0 + N_LANES volatile.Register32 // 0x4 + CSI2_RESETN volatile.Register32 // 0x8 + INT_ST_MAIN volatile.Register32 // 0xC + _ [48]byte + PHY_SHUTDOWNZ volatile.Register32 // 0x40 + DPHY_RSTZ volatile.Register32 // 0x44 + PHY_RX volatile.Register32 // 0x48 + PHY_STOPSTATE volatile.Register32 // 0x4C + PHY_TEST_CTRL0 volatile.Register32 // 0x50 + PHY_TEST_CTRL1 volatile.Register32 // 0x54 + _ [112]byte + VC_EXTENSION volatile.Register32 // 0xC8 + PHY_CAL volatile.Register32 // 0xCC + _ [16]byte + INT_ST_PHY_FATAL volatile.Register32 // 0xE0 + INT_MSK_PHY_FATAL volatile.Register32 // 0xE4 + INT_FORCE_PHY_FATAL volatile.Register32 // 0xE8 + _ [4]byte + INT_ST_PKT_FATAL volatile.Register32 // 0xF0 + INT_MSK_PKT_FATAL volatile.Register32 // 0xF4 + INT_FORCE_PKT_FATAL volatile.Register32 // 0xF8 + _ [20]byte + INT_ST_PHY volatile.Register32 // 0x110 + INT_MSK_PHY volatile.Register32 // 0x114 + INT_FORCE_PHY volatile.Register32 // 0x118 + _ [356]byte + INT_ST_BNDRY_FRAME_FATAL volatile.Register32 // 0x280 + INT_MSK_BNDRY_FRAME_FATAL volatile.Register32 // 0x284 + INT_FORCE_BNDRY_FRAME_FATAL volatile.Register32 // 0x288 + _ [4]byte + INT_ST_SEQ_FRAME_FATAL volatile.Register32 // 0x290 + INT_MSK_SEQ_FRAME_FATAL volatile.Register32 // 0x294 + INT_FORCE_SEQ_FRAME_FATAL volatile.Register32 // 0x298 + _ [4]byte + INT_ST_CRC_FRAME_FATAL volatile.Register32 // 0x2A0 + INT_MSK_CRC_FRAME_FATAL volatile.Register32 // 0x2A4 + INT_FORCE_CRC_FRAME_FATAL volatile.Register32 // 0x2A8 + _ [4]byte + INT_ST_PLD_CRC_FATAL volatile.Register32 // 0x2B0 + INT_MSK_PLD_CRC_FATAL volatile.Register32 // 0x2B4 + INT_FORCE_PLD_CRC_FATAL volatile.Register32 // 0x2B8 + _ [4]byte + INT_ST_DATA_ID volatile.Register32 // 0x2C0 + INT_MSK_DATA_ID volatile.Register32 // 0x2C4 + INT_FORCE_DATA_ID volatile.Register32 // 0x2C8 + _ [4]byte + INT_ST_ECC_CORRECTED volatile.Register32 // 0x2D0 + INT_MSK_ECC_CORRECTED volatile.Register32 // 0x2D4 + INT_FORCE_ECC_CORRECTED volatile.Register32 // 0x2D8 + _ [36]byte + SCRAMBLING volatile.Register32 // 0x300 + SCRAMBLING_SEED1 volatile.Register32 // 0x304 + SCRAMBLING_SEED2 volatile.Register32 // 0x308 +} + +// CSI_HOST.VERSION: NA +func (o *CSI_HOST_Type) SetVERSION(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, value) +} +func (o *CSI_HOST_Type) GetVERSION() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) +} + +// CSI_HOST.N_LANES: NA +func (o *CSI_HOST_Type) SetN_LANES(value uint32) { + volatile.StoreUint32(&o.N_LANES.Reg, volatile.LoadUint32(&o.N_LANES.Reg)&^(0x7)|value) +} +func (o *CSI_HOST_Type) GetN_LANES() uint32 { + return volatile.LoadUint32(&o.N_LANES.Reg) & 0x7 +} + +// CSI_HOST.CSI2_RESETN: NA +func (o *CSI_HOST_Type) SetCSI2_RESETN(value uint32) { + volatile.StoreUint32(&o.CSI2_RESETN.Reg, volatile.LoadUint32(&o.CSI2_RESETN.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetCSI2_RESETN() uint32 { + return volatile.LoadUint32(&o.CSI2_RESETN.Reg) & 0x1 +} + +// CSI_HOST.INT_ST_MAIN: NA +func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_PHY_FATAL(value uint32) { + volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_PHY_FATAL() uint32 { + return volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_PKT_FATAL(value uint32) { + volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_PKT_FATAL() uint32 { + return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_BNDRY_FRAME_FATAL(value uint32) { + volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_BNDRY_FRAME_FATAL() uint32 { + return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_SEQ_FRAME_FATAL(value uint32) { + volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_SEQ_FRAME_FATAL() uint32 { + return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_CRC_FRAME_FATAL(value uint32) { + volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_CRC_FRAME_FATAL() uint32 { + return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_PLD_CRC_FATAL(value uint32) { + volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_PLD_CRC_FATAL() uint32 { + return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_DATA_ID(value uint32) { + volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_DATA_ID() uint32 { + return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_ECC_CORRECTED(value uint32) { + volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_ECC_CORRECTED() uint32 { + return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_PHY(value uint32) { + volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x10000)|value<<16) +} +func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_PHY() uint32 { + return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x10000) >> 16 +} + +// CSI_HOST.PHY_SHUTDOWNZ: NA +func (o *CSI_HOST_Type) SetPHY_SHUTDOWNZ(value uint32) { + volatile.StoreUint32(&o.PHY_SHUTDOWNZ.Reg, volatile.LoadUint32(&o.PHY_SHUTDOWNZ.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetPHY_SHUTDOWNZ() uint32 { + return volatile.LoadUint32(&o.PHY_SHUTDOWNZ.Reg) & 0x1 +} + +// CSI_HOST.DPHY_RSTZ: NA +func (o *CSI_HOST_Type) SetDPHY_RSTZ(value uint32) { + volatile.StoreUint32(&o.DPHY_RSTZ.Reg, volatile.LoadUint32(&o.DPHY_RSTZ.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetDPHY_RSTZ() uint32 { + return volatile.LoadUint32(&o.DPHY_RSTZ.Reg) & 0x1 +} + +// CSI_HOST.PHY_RX: NA +func (o *CSI_HOST_Type) SetPHY_RX_PHY_RXULPSESC_0(value uint32) { + volatile.StoreUint32(&o.PHY_RX.Reg, volatile.LoadUint32(&o.PHY_RX.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetPHY_RX_PHY_RXULPSESC_0() uint32 { + return volatile.LoadUint32(&o.PHY_RX.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetPHY_RX_PHY_RXULPSESC_1(value uint32) { + volatile.StoreUint32(&o.PHY_RX.Reg, volatile.LoadUint32(&o.PHY_RX.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetPHY_RX_PHY_RXULPSESC_1() uint32 { + return (volatile.LoadUint32(&o.PHY_RX.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetPHY_RX_PHY_RXULPSCLKNOT(value uint32) { + volatile.StoreUint32(&o.PHY_RX.Reg, volatile.LoadUint32(&o.PHY_RX.Reg)&^(0x10000)|value<<16) +} +func (o *CSI_HOST_Type) GetPHY_RX_PHY_RXULPSCLKNOT() uint32 { + return (volatile.LoadUint32(&o.PHY_RX.Reg) & 0x10000) >> 16 +} +func (o *CSI_HOST_Type) SetPHY_RX_PHY_RXCLKACTIVEHS(value uint32) { + volatile.StoreUint32(&o.PHY_RX.Reg, volatile.LoadUint32(&o.PHY_RX.Reg)&^(0x20000)|value<<17) +} +func (o *CSI_HOST_Type) GetPHY_RX_PHY_RXCLKACTIVEHS() uint32 { + return (volatile.LoadUint32(&o.PHY_RX.Reg) & 0x20000) >> 17 +} + +// CSI_HOST.PHY_STOPSTATE: NA +func (o *CSI_HOST_Type) SetPHY_STOPSTATE_PHY_STOPSTATEDATA_0(value uint32) { + volatile.StoreUint32(&o.PHY_STOPSTATE.Reg, volatile.LoadUint32(&o.PHY_STOPSTATE.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetPHY_STOPSTATE_PHY_STOPSTATEDATA_0() uint32 { + return volatile.LoadUint32(&o.PHY_STOPSTATE.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetPHY_STOPSTATE_PHY_STOPSTATEDATA_1(value uint32) { + volatile.StoreUint32(&o.PHY_STOPSTATE.Reg, volatile.LoadUint32(&o.PHY_STOPSTATE.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetPHY_STOPSTATE_PHY_STOPSTATEDATA_1() uint32 { + return (volatile.LoadUint32(&o.PHY_STOPSTATE.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetPHY_STOPSTATE_PHY_STOPSTATECLK(value uint32) { + volatile.StoreUint32(&o.PHY_STOPSTATE.Reg, volatile.LoadUint32(&o.PHY_STOPSTATE.Reg)&^(0x10000)|value<<16) +} +func (o *CSI_HOST_Type) GetPHY_STOPSTATE_PHY_STOPSTATECLK() uint32 { + return (volatile.LoadUint32(&o.PHY_STOPSTATE.Reg) & 0x10000) >> 16 +} + +// CSI_HOST.PHY_TEST_CTRL0: NA +func (o *CSI_HOST_Type) SetPHY_TEST_CTRL0_PHY_TESTCLR(value uint32) { + volatile.StoreUint32(&o.PHY_TEST_CTRL0.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL0.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetPHY_TEST_CTRL0_PHY_TESTCLR() uint32 { + return volatile.LoadUint32(&o.PHY_TEST_CTRL0.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetPHY_TEST_CTRL0_PHY_TESTCLK(value uint32) { + volatile.StoreUint32(&o.PHY_TEST_CTRL0.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL0.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetPHY_TEST_CTRL0_PHY_TESTCLK() uint32 { + return (volatile.LoadUint32(&o.PHY_TEST_CTRL0.Reg) & 0x2) >> 1 +} + +// CSI_HOST.PHY_TEST_CTRL1: NA +func (o *CSI_HOST_Type) SetPHY_TEST_CTRL1_PHY_TESTDIN(value uint32) { + volatile.StoreUint32(&o.PHY_TEST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg)&^(0xff)|value) +} +func (o *CSI_HOST_Type) GetPHY_TEST_CTRL1_PHY_TESTDIN() uint32 { + return volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg) & 0xff +} +func (o *CSI_HOST_Type) SetPHY_TEST_CTRL1_PHY_TESTDOUT(value uint32) { + volatile.StoreUint32(&o.PHY_TEST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg)&^(0xff00)|value<<8) +} +func (o *CSI_HOST_Type) GetPHY_TEST_CTRL1_PHY_TESTDOUT() uint32 { + return (volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg) & 0xff00) >> 8 +} +func (o *CSI_HOST_Type) SetPHY_TEST_CTRL1_PHY_TESTEN(value uint32) { + volatile.StoreUint32(&o.PHY_TEST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg)&^(0x10000)|value<<16) +} +func (o *CSI_HOST_Type) GetPHY_TEST_CTRL1_PHY_TESTEN() uint32 { + return (volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg) & 0x10000) >> 16 +} + +// CSI_HOST.VC_EXTENSION: NA +func (o *CSI_HOST_Type) SetVC_EXTENSION_VCX(value uint32) { + volatile.StoreUint32(&o.VC_EXTENSION.Reg, volatile.LoadUint32(&o.VC_EXTENSION.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetVC_EXTENSION_VCX() uint32 { + return volatile.LoadUint32(&o.VC_EXTENSION.Reg) & 0x1 +} + +// CSI_HOST.PHY_CAL: NA +func (o *CSI_HOST_Type) SetPHY_CAL_RXSKEWCALHS(value uint32) { + volatile.StoreUint32(&o.PHY_CAL.Reg, volatile.LoadUint32(&o.PHY_CAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetPHY_CAL_RXSKEWCALHS() uint32 { + return volatile.LoadUint32(&o.PHY_CAL.Reg) & 0x1 +} + +// CSI_HOST.INT_ST_PHY_FATAL: NA +func (o *CSI_HOST_Type) SetINT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_0(value uint32) { + volatile.StoreUint32(&o.INT_ST_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PHY_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_0() uint32 { + return volatile.LoadUint32(&o.INT_ST_PHY_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_1(value uint32) { + volatile.StoreUint32(&o.INT_ST_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PHY_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_1() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PHY_FATAL.Reg) & 0x2) >> 1 +} + +// CSI_HOST.INT_MSK_PHY_FATAL: NA +func (o *CSI_HOST_Type) SetINT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PHY_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0() uint32 { + return volatile.LoadUint32(&o.INT_MSK_PHY_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PHY_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PHY_FATAL.Reg) & 0x2) >> 1 +} + +// CSI_HOST.INT_FORCE_PHY_FATAL: NA +func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0() uint32 { + return volatile.LoadUint32(&o.INT_FORCE_PHY_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PHY_FATAL.Reg) & 0x2) >> 1 +} + +// CSI_HOST.INT_ST_PKT_FATAL: NA +func (o *CSI_HOST_Type) SetINT_ST_PKT_FATAL_ST_ERR_ECC_DOUBLE(value uint32) { + volatile.StoreUint32(&o.INT_ST_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PKT_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_PKT_FATAL_ST_ERR_ECC_DOUBLE() uint32 { + return volatile.LoadUint32(&o.INT_ST_PKT_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_PKT_FATAL_ST_SHORTER_PAYLOAD(value uint32) { + volatile.StoreUint32(&o.INT_ST_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PKT_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_PKT_FATAL_ST_SHORTER_PAYLOAD() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PKT_FATAL.Reg) & 0x2) >> 1 +} + +// CSI_HOST.INT_MSK_PKT_FATAL: NA +func (o *CSI_HOST_Type) SetINT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PKT_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE() uint32 { + return volatile.LoadUint32(&o.INT_MSK_PKT_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_MSK_PKT_FATAL_MASK_SHORTER_PAYLOAD(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PKT_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_MSK_PKT_FATAL_MASK_SHORTER_PAYLOAD() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PKT_FATAL.Reg) & 0x2) >> 1 +} + +// CSI_HOST.INT_FORCE_PKT_FATAL: NA +func (o *CSI_HOST_Type) SetINT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PKT_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE() uint32 { + return volatile.LoadUint32(&o.INT_FORCE_PKT_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PKT_FATAL_FORCE_SHORTER_PAYLOAD(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PKT_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PKT_FATAL_FORCE_SHORTER_PAYLOAD() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PKT_FATAL.Reg) & 0x2) >> 1 +} + +// CSI_HOST.INT_ST_PHY: NA +func (o *CSI_HOST_Type) SetINT_ST_PHY_ST_PHY_ERRSOTHS_0(value uint32) { + volatile.StoreUint32(&o.INT_ST_PHY.Reg, volatile.LoadUint32(&o.INT_ST_PHY.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_PHY_ST_PHY_ERRSOTHS_0() uint32 { + return volatile.LoadUint32(&o.INT_ST_PHY.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_PHY_ST_PHY_ERRSOTHS_1(value uint32) { + volatile.StoreUint32(&o.INT_ST_PHY.Reg, volatile.LoadUint32(&o.INT_ST_PHY.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_PHY_ST_PHY_ERRSOTHS_1() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PHY.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_ST_PHY_ST_PHY_ERRESC_0(value uint32) { + volatile.StoreUint32(&o.INT_ST_PHY.Reg, volatile.LoadUint32(&o.INT_ST_PHY.Reg)&^(0x10000)|value<<16) +} +func (o *CSI_HOST_Type) GetINT_ST_PHY_ST_PHY_ERRESC_0() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PHY.Reg) & 0x10000) >> 16 +} +func (o *CSI_HOST_Type) SetINT_ST_PHY_ST_PHY_ERRESC_1(value uint32) { + volatile.StoreUint32(&o.INT_ST_PHY.Reg, volatile.LoadUint32(&o.INT_ST_PHY.Reg)&^(0x20000)|value<<17) +} +func (o *CSI_HOST_Type) GetINT_ST_PHY_ST_PHY_ERRESC_1() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PHY.Reg) & 0x20000) >> 17 +} + +// CSI_HOST.INT_MSK_PHY: NA +func (o *CSI_HOST_Type) SetINT_MSK_PHY_MASK_PHY_ERRSOTHS_0(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PHY.Reg, volatile.LoadUint32(&o.INT_MSK_PHY.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_MSK_PHY_MASK_PHY_ERRSOTHS_0() uint32 { + return volatile.LoadUint32(&o.INT_MSK_PHY.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_MSK_PHY_MASK_PHY_ERRSOTHS_1(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PHY.Reg, volatile.LoadUint32(&o.INT_MSK_PHY.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_MSK_PHY_MASK_PHY_ERRSOTHS_1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PHY.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_MSK_PHY_MASK_PHY_ERRESC_0(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PHY.Reg, volatile.LoadUint32(&o.INT_MSK_PHY.Reg)&^(0x10000)|value<<16) +} +func (o *CSI_HOST_Type) GetINT_MSK_PHY_MASK_PHY_ERRESC_0() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PHY.Reg) & 0x10000) >> 16 +} +func (o *CSI_HOST_Type) SetINT_MSK_PHY_MASK_PHY_ERRESC_1(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PHY.Reg, volatile.LoadUint32(&o.INT_MSK_PHY.Reg)&^(0x20000)|value<<17) +} +func (o *CSI_HOST_Type) GetINT_MSK_PHY_MASK_PHY_ERRESC_1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PHY.Reg) & 0x20000) >> 17 +} + +// CSI_HOST.INT_FORCE_PHY: NA +func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PHY.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0() uint32 { + return volatile.LoadUint32(&o.INT_FORCE_PHY.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PHY.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PHY.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FORCE_PHY_ERRESC_0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PHY.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY.Reg)&^(0x10000)|value<<16) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FORCE_PHY_ERRESC_0() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PHY.Reg) & 0x10000) >> 16 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FORCE_PHY_ERRESC_1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PHY.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY.Reg)&^(0x20000)|value<<17) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FORCE_PHY_ERRESC_1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PHY.Reg) & 0x20000) >> 17 +} + +// CSI_HOST.INT_ST_BNDRY_FRAME_FATAL: NA +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC0(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC0() uint32 { + return volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC1(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC2(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC3(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC4(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC5(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC6(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC7(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC8(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC9(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC10(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC11(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC12(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC13(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC14(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC15(value uint32) { + volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_MSK_BNDRY_FRAME_FATAL: NA +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC0(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC0() uint32 { + return volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC1(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC2(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC3(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC4(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC5(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC6(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC7(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC8(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC9(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC10(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC11(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC12(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC13(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC14(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC15(value uint32) { + volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_FORCE_BNDRY_FRAME_FATAL: NA +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0() uint32 { + return volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_ST_SEQ_FRAME_FATAL: NA +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC0(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC0() uint32 { + return volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC1(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC2(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC3(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC4(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC5(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC6(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC7(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC8(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC9(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC10(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC11(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC12(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC13(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC14(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC15(value uint32) { + volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_MSK_SEQ_FRAME_FATAL: NA +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC0(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC0() uint32 { + return volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC1(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC2(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC3(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC4(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC5(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC6(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC7(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC8(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC9(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC10(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC11(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC12(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC13(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC14(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC15(value uint32) { + volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_FORCE_SEQ_FRAME_FATAL: NA +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC0() uint32 { + return volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC2(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC3(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC4(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC5(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC6(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC7(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC8(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC9(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC10(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC11(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC12(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC13(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC14(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC15(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_ST_CRC_FRAME_FATAL: NA +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC0(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC0() uint32 { + return volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC1(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC2(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC3(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC4(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC5(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC6(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC7(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC8(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC9(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC10(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC11(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC12(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC13(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC14(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC15(value uint32) { + volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_MSK_CRC_FRAME_FATAL: NA +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC0(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC0() uint32 { + return volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC1(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC2(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC3(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC4(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC5(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC6(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC7(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC8(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC9(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC10(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC11(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC12(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC13(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC14(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC15(value uint32) { + volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_FORCE_CRC_FRAME_FATAL: NA +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC0() uint32 { + return volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC2(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC3(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC4(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC5(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC6(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC7(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC8(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC9(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC10(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC11(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC12(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC13(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC14(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC15(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_ST_PLD_CRC_FATAL: NA +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC0(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC0() uint32 { + return volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC1(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC2(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC3(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC4(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC5(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC6(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC7(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC8(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC9(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC10(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC11(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC12(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC13(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC14(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC15(value uint32) { + volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_MSK_PLD_CRC_FATAL: NA +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC0(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC0() uint32 { + return volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC1(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC2(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC3(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC4(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC5(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC6(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC7(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC8(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC9(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC10(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC11(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC12(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC13(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC14(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC15(value uint32) { + volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_FORCE_PLD_CRC_FATAL: NA +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC0() uint32 { + return volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC2(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC3(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC4(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC5(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC6(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC7(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC8(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC9(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC10(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC11(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC12(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC13(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC14(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC15(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_ST_DATA_ID: NA +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC0(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC0() uint32 { + return volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC1(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC2(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC3(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC4(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC5(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC6(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC7(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC8(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC9(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC10(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC11(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC12(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC13(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC14(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC15(value uint32) { + volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_MSK_DATA_ID: NA +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC0(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC0() uint32 { + return volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC1(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC2(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC3(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC4(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC5(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC6(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC7(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC8(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC9(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC10(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC11(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC12(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC13(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC14(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC15(value uint32) { + volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_FORCE_DATA_ID: NA +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC0() uint32 { + return volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC2(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC3(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC4(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC5(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC6(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC7(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC8(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC9(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC10(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC11(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC12(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC13(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC14(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC15(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_ST_ECC_CORRECTED: NA +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC0(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC0() uint32 { + return volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC1(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC2(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC3(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC4(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC5(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC6(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC7(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC8(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC9(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC10(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC11(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC12(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC13(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC14(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC15(value uint32) { + volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_MSK_ECC_CORRECTED: NA +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC0(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC0() uint32 { + return volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC1(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC2(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC3(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC4(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC5(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC6(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC7(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC8(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC9(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC10(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC11(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC12(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC13(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC14(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC15(value uint32) { + volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.INT_FORCE_ECC_CORRECTED: NA +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC0() uint32 { + return volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x2)|value<<1) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x2) >> 1 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC2(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x4)|value<<2) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC2() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x4) >> 2 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC3(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x8)|value<<3) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC3() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x8) >> 3 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC4(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x10)|value<<4) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC4() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x10) >> 4 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC5(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x20)|value<<5) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC5() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x20) >> 5 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC6(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x40)|value<<6) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC6() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x40) >> 6 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC7(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x80)|value<<7) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC7() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x80) >> 7 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC8(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x100)|value<<8) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC8() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x100) >> 8 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC9(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x200)|value<<9) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC9() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x200) >> 9 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC10(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x400)|value<<10) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC10() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x400) >> 10 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC11(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x800)|value<<11) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC11() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x800) >> 11 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC12(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x1000)|value<<12) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC12() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x1000) >> 12 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC13(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x2000)|value<<13) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC13() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x2000) >> 13 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC14(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x4000)|value<<14) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC14() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x4000) >> 14 +} +func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC15(value uint32) { + volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x8000)|value<<15) +} +func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC15() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x8000) >> 15 +} + +// CSI_HOST.SCRAMBLING: NA +func (o *CSI_HOST_Type) SetSCRAMBLING_SCRAMBLE_ENABLE(value uint32) { + volatile.StoreUint32(&o.SCRAMBLING.Reg, volatile.LoadUint32(&o.SCRAMBLING.Reg)&^(0x1)|value) +} +func (o *CSI_HOST_Type) GetSCRAMBLING_SCRAMBLE_ENABLE() uint32 { + return volatile.LoadUint32(&o.SCRAMBLING.Reg) & 0x1 +} + +// CSI_HOST.SCRAMBLING_SEED1: NA +func (o *CSI_HOST_Type) SetSCRAMBLING_SEED1_SCRAMBLE_SEED_LANE1(value uint32) { + volatile.StoreUint32(&o.SCRAMBLING_SEED1.Reg, volatile.LoadUint32(&o.SCRAMBLING_SEED1.Reg)&^(0xffff)|value) +} +func (o *CSI_HOST_Type) GetSCRAMBLING_SEED1_SCRAMBLE_SEED_LANE1() uint32 { + return volatile.LoadUint32(&o.SCRAMBLING_SEED1.Reg) & 0xffff +} + +// CSI_HOST.SCRAMBLING_SEED2: NA +func (o *CSI_HOST_Type) SetSCRAMBLING_SEED2_SCRAMBLE_SEED_LANE2(value uint32) { + volatile.StoreUint32(&o.SCRAMBLING_SEED2.Reg, volatile.LoadUint32(&o.SCRAMBLING_SEED2.Reg)&^(0xffff)|value) +} +func (o *CSI_HOST_Type) GetSCRAMBLING_SEED2_SCRAMBLE_SEED_LANE2() uint32 { + return volatile.LoadUint32(&o.SCRAMBLING_SEED2.Reg) & 0xffff +} + +// DMA (Direct Memory Access) Controller +type DMAC_Type struct { + ID0 volatile.Register32 // 0x0 + _ [4]byte + COMPVER0 volatile.Register32 // 0x8 + _ [4]byte + CFG0 volatile.Register32 // 0x10 + _ [4]byte + CHEN0 volatile.Register32 // 0x18 + CHEN1 volatile.Register32 // 0x1C + _ [16]byte + INTSTATUS0 volatile.Register32 // 0x30 + _ [4]byte + COMMONREG_INTCLEAR0 volatile.Register32 // 0x38 + _ [4]byte + COMMONREG_INTSTATUS_ENABLE0 volatile.Register32 // 0x40 + _ [4]byte + COMMONREG_INTSIGNAL_ENABLE0 volatile.Register32 // 0x48 + _ [4]byte + COMMONREG_INTSTATUS0 volatile.Register32 // 0x50 + _ [4]byte + RESET0 volatile.Register32 // 0x58 + _ [4]byte + LOWPOWER_CFG0 volatile.Register32 // 0x60 + LOWPOWER_CFG1 volatile.Register32 // 0x64 + _ [152]byte + CH1_SAR0 volatile.Register32 // 0x100 + CH1_SAR1 volatile.Register32 // 0x104 + CH1_DAR0 volatile.Register32 // 0x108 + CH1_DAR1 volatile.Register32 // 0x10C + CH1_BLOCK_TS0 volatile.Register32 // 0x110 + _ [4]byte + CH1_CTL0 volatile.Register32 // 0x118 + CH1_CTL1 volatile.Register32 // 0x11C + CH1_CFG0 volatile.Register32 // 0x120 + CH1_CFG1 volatile.Register32 // 0x124 + CH1_LLP0 volatile.Register32 // 0x128 + CH1_LLP1 volatile.Register32 // 0x12C + CH1_STATUS0 volatile.Register32 // 0x130 + CH1_STATUS1 volatile.Register32 // 0x134 + CH1_SWHSSRC0 volatile.Register32 // 0x138 + _ [4]byte + CH1_SWHSDST0 volatile.Register32 // 0x140 + _ [4]byte + CH1_BLK_TFR_RESUMEREQ0 volatile.Register32 // 0x148 + _ [4]byte + CH1_AXI_ID0 volatile.Register32 // 0x150 + _ [4]byte + CH1_AXI_QOS0 volatile.Register32 // 0x158 + _ [4]byte + CH1_SSTAT0 volatile.Register32 // 0x160 + _ [4]byte + CH1_DSTAT0 volatile.Register32 // 0x168 + _ [4]byte + CH1_SSTATAR0 volatile.Register32 // 0x170 + CH1_SSTATAR1 volatile.Register32 // 0x174 + CH1_DSTATAR0 volatile.Register32 // 0x178 + CH1_DSTATAR1 volatile.Register32 // 0x17C + CH1_INTSTATUS_ENABLE0 volatile.Register32 // 0x180 + CH1_INTSTATUS_ENABLE1 volatile.Register32 // 0x184 + CH1_INTSTATUS0 volatile.Register32 // 0x188 + CH1_INTSTATUS1 volatile.Register32 // 0x18C + CH1_INTSIGNAL_ENABLE0 volatile.Register32 // 0x190 + CH1_INTSIGNAL_ENABLE1 volatile.Register32 // 0x194 + CH1_INTCLEAR0 volatile.Register32 // 0x198 + CH1_INTCLEAR1 volatile.Register32 // 0x19C + _ [96]byte + CH2_SAR0 volatile.Register32 // 0x200 + CH2_SAR1 volatile.Register32 // 0x204 + CH2_DAR0 volatile.Register32 // 0x208 + CH2_DAR1 volatile.Register32 // 0x20C + CH2_BLOCK_TS0 volatile.Register32 // 0x210 + _ [4]byte + CH2_CTL0 volatile.Register32 // 0x218 + CH2_CTL1 volatile.Register32 // 0x21C + CH2_CFG0 volatile.Register32 // 0x220 + CH2_CFG1 volatile.Register32 // 0x224 + CH2_LLP0 volatile.Register32 // 0x228 + CH2_LLP1 volatile.Register32 // 0x22C + CH2_STATUS0 volatile.Register32 // 0x230 + CH2_STATUS1 volatile.Register32 // 0x234 + CH2_SWHSSRC0 volatile.Register32 // 0x238 + _ [4]byte + CH2_SWHSDST0 volatile.Register32 // 0x240 + _ [4]byte + CH2_BLK_TFR_RESUMEREQ0 volatile.Register32 // 0x248 + _ [4]byte + CH2_AXI_ID0 volatile.Register32 // 0x250 + _ [4]byte + CH2_AXI_QOS0 volatile.Register32 // 0x258 + _ [4]byte + CH2_SSTAT0 volatile.Register32 // 0x260 + _ [4]byte + CH2_DSTAT0 volatile.Register32 // 0x268 + _ [4]byte + CH2_SSTATAR0 volatile.Register32 // 0x270 + CH2_SSTATAR1 volatile.Register32 // 0x274 + CH2_DSTATAR0 volatile.Register32 // 0x278 + CH2_DSTATAR1 volatile.Register32 // 0x27C + CH2_INTSTATUS_ENABLE0 volatile.Register32 // 0x280 + CH2_INTSTATUS_ENABLE1 volatile.Register32 // 0x284 + CH2_INTSTATUS0 volatile.Register32 // 0x288 + CH2_INTSTATUS1 volatile.Register32 // 0x28C + CH2_INTSIGNAL_ENABLE0 volatile.Register32 // 0x290 + CH2_INTSIGNAL_ENABLE1 volatile.Register32 // 0x294 + CH2_INTCLEAR0 volatile.Register32 // 0x298 + CH2_INTCLEAR1 volatile.Register32 // 0x29C + _ [96]byte + CH3_SAR0 volatile.Register32 // 0x300 + CH3_SAR1 volatile.Register32 // 0x304 + CH3_DAR0 volatile.Register32 // 0x308 + CH3_DAR1 volatile.Register32 // 0x30C + CH3_BLOCK_TS0 volatile.Register32 // 0x310 + _ [4]byte + CH3_CTL0 volatile.Register32 // 0x318 + CH3_CTL1 volatile.Register32 // 0x31C + CH3_CFG0 volatile.Register32 // 0x320 + CH3_CFG1 volatile.Register32 // 0x324 + CH3_LLP0 volatile.Register32 // 0x328 + CH3_LLP1 volatile.Register32 // 0x32C + CH3_STATUS0 volatile.Register32 // 0x330 + CH3_STATUS1 volatile.Register32 // 0x334 + CH3_SWHSSRC0 volatile.Register32 // 0x338 + _ [4]byte + CH3_SWHSDST0 volatile.Register32 // 0x340 + _ [4]byte + CH3_BLK_TFR_RESUMEREQ0 volatile.Register32 // 0x348 + _ [4]byte + CH3_AXI_ID0 volatile.Register32 // 0x350 + _ [4]byte + CH3_AXI_QOS0 volatile.Register32 // 0x358 + _ [4]byte + CH3_SSTAT0 volatile.Register32 // 0x360 + _ [4]byte + CH3_DSTAT0 volatile.Register32 // 0x368 + _ [4]byte + CH3_SSTATAR0 volatile.Register32 // 0x370 + CH3_SSTATAR1 volatile.Register32 // 0x374 + CH3_DSTATAR0 volatile.Register32 // 0x378 + CH3_DSTATAR1 volatile.Register32 // 0x37C + CH3_INTSTATUS_ENABLE0 volatile.Register32 // 0x380 + CH3_INTSTATUS_ENABLE1 volatile.Register32 // 0x384 + CH3_INTSTATUS0 volatile.Register32 // 0x388 + CH3_INTSTATUS1 volatile.Register32 // 0x38C + CH3_INTSIGNAL_ENABLE0 volatile.Register32 // 0x390 + CH3_INTSIGNAL_ENABLE1 volatile.Register32 // 0x394 + CH3_INTCLEAR0 volatile.Register32 // 0x398 + CH3_INTCLEAR1 volatile.Register32 // 0x39C + _ [96]byte + CH4_SAR0 volatile.Register32 // 0x400 + CH4_SAR1 volatile.Register32 // 0x404 + CH4_DAR0 volatile.Register32 // 0x408 + CH4_DAR1 volatile.Register32 // 0x40C + CH4_BLOCK_TS0 volatile.Register32 // 0x410 + _ [4]byte + CH4_CTL0 volatile.Register32 // 0x418 + CH4_CTL1 volatile.Register32 // 0x41C + CH4_CFG0 volatile.Register32 // 0x420 + CH4_CFG1 volatile.Register32 // 0x424 + CH4_LLP0 volatile.Register32 // 0x428 + CH4_LLP1 volatile.Register32 // 0x42C + CH4_STATUS0 volatile.Register32 // 0x430 + CH4_STATUS1 volatile.Register32 // 0x434 + CH4_SWHSSRC0 volatile.Register32 // 0x438 + _ [4]byte + CH4_SWHSDST0 volatile.Register32 // 0x440 + _ [4]byte + CH4_BLK_TFR_RESUMEREQ0 volatile.Register32 // 0x448 + _ [4]byte + CH4_AXI_ID0 volatile.Register32 // 0x450 + _ [4]byte + CH4_AXI_QOS0 volatile.Register32 // 0x458 + _ [4]byte + CH4_SSTAT0 volatile.Register32 // 0x460 + _ [4]byte + CH4_DSTAT0 volatile.Register32 // 0x468 + _ [4]byte + CH4_SSTATAR0 volatile.Register32 // 0x470 + CH4_SSTATAR1 volatile.Register32 // 0x474 + CH4_DSTATAR0 volatile.Register32 // 0x478 + CH4_DSTATAR1 volatile.Register32 // 0x47C + CH4_INTSTATUS_ENABLE0 volatile.Register32 // 0x480 + CH4_INTSTATUS_ENABLE1 volatile.Register32 // 0x484 + CH4_INTSTATUS0 volatile.Register32 // 0x488 + CH4_INTSTATUS1 volatile.Register32 // 0x48C + CH4_INTSIGNAL_ENABLE0 volatile.Register32 // 0x490 + CH4_INTSIGNAL_ENABLE1 volatile.Register32 // 0x494 + CH4_INTCLEAR0 volatile.Register32 // 0x498 + CH4_INTCLEAR1 volatile.Register32 // 0x49C +} + +// DMAC.ID0: NA +func (o *DMAC_Type) SetID0(value uint32) { + volatile.StoreUint32(&o.ID0.Reg, value) +} +func (o *DMAC_Type) GetID0() uint32 { + return volatile.LoadUint32(&o.ID0.Reg) +} + +// DMAC.COMPVER0: NA +func (o *DMAC_Type) SetCOMPVER0(value uint32) { + volatile.StoreUint32(&o.COMPVER0.Reg, value) +} +func (o *DMAC_Type) GetCOMPVER0() uint32 { + return volatile.LoadUint32(&o.COMPVER0.Reg) +} + +// DMAC.CFG0: NA +func (o *DMAC_Type) SetCFG0_DMAC_EN(value uint32) { + volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCFG0_DMAC_EN() uint32 { + return volatile.LoadUint32(&o.CFG0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCFG0_INT_EN(value uint32) { + volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCFG0_INT_EN() uint32 { + return (volatile.LoadUint32(&o.CFG0.Reg) & 0x2) >> 1 +} + +// DMAC.CHEN0: NA +func (o *DMAC_Type) SetCHEN0_CH1_EN(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCHEN0_CH1_EN() uint32 { + return volatile.LoadUint32(&o.CHEN0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCHEN0_CH2_EN(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCHEN0_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCHEN0_CH3_EN(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCHEN0_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCHEN0_CH4_EN(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCHEN0_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCHEN0_CH1_EN_WE(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCHEN0_CH1_EN_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCHEN0_CH2_EN_WE(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCHEN0_CH2_EN_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCHEN0_CH3_EN_WE(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCHEN0_CH3_EN_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCHEN0_CH4_EN_WE(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCHEN0_CH4_EN_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCHEN0_CH1_SUSP(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCHEN0_CH1_SUSP() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCHEN0_CH2_SUSP(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCHEN0_CH2_SUSP() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCHEN0_CH3_SUSP(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCHEN0_CH3_SUSP() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCHEN0_CH4_SUSP(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCHEN0_CH4_SUSP() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCHEN0_CH1_SUSP_WE(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMAC_Type) GetCHEN0_CH1_SUSP_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x1000000) >> 24 +} +func (o *DMAC_Type) SetCHEN0_CH2_SUSP_WE(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCHEN0_CH2_SUSP_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCHEN0_CH3_SUSP_WE(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMAC_Type) GetCHEN0_CH3_SUSP_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x4000000) >> 26 +} +func (o *DMAC_Type) SetCHEN0_CH4_SUSP_WE(value uint32) { + volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCHEN0_CH4_SUSP_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x8000000) >> 27 +} + +// DMAC.CHEN1: NA +func (o *DMAC_Type) SetCHEN1_CH1_ABORT(value uint32) { + volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCHEN1_CH1_ABORT() uint32 { + return volatile.LoadUint32(&o.CHEN1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCHEN1_CH2_ABORT(value uint32) { + volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCHEN1_CH2_ABORT() uint32 { + return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCHEN1_CH3_ABORT(value uint32) { + volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCHEN1_CH3_ABORT() uint32 { + return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCHEN1_CH4_ABORT(value uint32) { + volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCHEN1_CH4_ABORT() uint32 { + return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCHEN1_CH1_ABORT_WE(value uint32) { + volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCHEN1_CH1_ABORT_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCHEN1_CH2_ABORT_WE(value uint32) { + volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCHEN1_CH2_ABORT_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCHEN1_CH3_ABORT_WE(value uint32) { + volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCHEN1_CH3_ABORT_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCHEN1_CH4_ABORT_WE(value uint32) { + volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCHEN1_CH4_ABORT_WE() uint32 { + return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x800) >> 11 +} + +// DMAC.INTSTATUS0: NA +func (o *DMAC_Type) SetINTSTATUS0_CH1_INTSTAT(value uint32) { + volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetINTSTATUS0_CH1_INTSTAT() uint32 { + return volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x1 +} +func (o *DMAC_Type) SetINTSTATUS0_CH2_INTSTAT(value uint32) { + volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetINTSTATUS0_CH2_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetINTSTATUS0_CH3_INTSTAT(value uint32) { + volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetINTSTATUS0_CH3_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetINTSTATUS0_CH4_INTSTAT(value uint32) { + volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetINTSTATUS0_CH4_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetINTSTATUS0_COMMONREG_INTSTAT(value uint32) { + volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetINTSTATUS0_COMMONREG_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x10000) >> 16 +} + +// DMAC.COMMONREG_INTCLEAR0: NA +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x8000)|value<<15) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x8000) >> 15 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x100000) >> 20 +} + +// DMAC.COMMONREG_INTSTATUS_ENABLE0: NA +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x8000)|value<<15) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x8000) >> 15 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20 +} + +// DMAC.COMMONREG_INTSIGNAL_ENABLE0: NA +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL() uint32 { + return volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x8000)|value<<15) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x8000) >> 15 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20 +} + +// DMAC.COMMONREG_INTSTATUS0: NA +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_DEC_ERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x8000)|value<<15) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x8000) >> 15 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x100000) >> 20 +} + +// DMAC.RESET0: NA +func (o *DMAC_Type) SetRESET0_DMAC_RST(value uint32) { + volatile.StoreUint32(&o.RESET0.Reg, volatile.LoadUint32(&o.RESET0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetRESET0_DMAC_RST() uint32 { + return volatile.LoadUint32(&o.RESET0.Reg) & 0x1 +} + +// DMAC.LOWPOWER_CFG0: NA +func (o *DMAC_Type) SetLOWPOWER_CFG0_GBL_CSLP_EN(value uint32) { + volatile.StoreUint32(&o.LOWPOWER_CFG0.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetLOWPOWER_CFG0_GBL_CSLP_EN() uint32 { + return volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg) & 0x1 +} +func (o *DMAC_Type) SetLOWPOWER_CFG0_CHNL_CSLP_EN(value uint32) { + volatile.StoreUint32(&o.LOWPOWER_CFG0.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetLOWPOWER_CFG0_CHNL_CSLP_EN() uint32 { + return (volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetLOWPOWER_CFG0_SBIU_CSLP_EN(value uint32) { + volatile.StoreUint32(&o.LOWPOWER_CFG0.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetLOWPOWER_CFG0_SBIU_CSLP_EN() uint32 { + return (volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetLOWPOWER_CFG0_MXIF_CSLP_EN(value uint32) { + volatile.StoreUint32(&o.LOWPOWER_CFG0.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetLOWPOWER_CFG0_MXIF_CSLP_EN() uint32 { + return (volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg) & 0x8) >> 3 +} + +// DMAC.LOWPOWER_CFG1: NA +func (o *DMAC_Type) SetLOWPOWER_CFG1_GLCH_LPDLY(value uint32) { + volatile.StoreUint32(&o.LOWPOWER_CFG1.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg)&^(0xff)|value) +} +func (o *DMAC_Type) GetLOWPOWER_CFG1_GLCH_LPDLY() uint32 { + return volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg) & 0xff +} +func (o *DMAC_Type) SetLOWPOWER_CFG1_SBIU_LPDLY(value uint32) { + volatile.StoreUint32(&o.LOWPOWER_CFG1.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg)&^(0xff00)|value<<8) +} +func (o *DMAC_Type) GetLOWPOWER_CFG1_SBIU_LPDLY() uint32 { + return (volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg) & 0xff00) >> 8 +} +func (o *DMAC_Type) SetLOWPOWER_CFG1_MXIF_LPDLY(value uint32) { + volatile.StoreUint32(&o.LOWPOWER_CFG1.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg)&^(0xff0000)|value<<16) +} +func (o *DMAC_Type) GetLOWPOWER_CFG1_MXIF_LPDLY() uint32 { + return (volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg) & 0xff0000) >> 16 +} + +// DMAC.CH1_SAR0: NA +func (o *DMAC_Type) SetCH1_SAR0(value uint32) { + volatile.StoreUint32(&o.CH1_SAR0.Reg, value) +} +func (o *DMAC_Type) GetCH1_SAR0() uint32 { + return volatile.LoadUint32(&o.CH1_SAR0.Reg) +} + +// DMAC.CH1_SAR1: NA +func (o *DMAC_Type) SetCH1_SAR1(value uint32) { + volatile.StoreUint32(&o.CH1_SAR1.Reg, value) +} +func (o *DMAC_Type) GetCH1_SAR1() uint32 { + return volatile.LoadUint32(&o.CH1_SAR1.Reg) +} + +// DMAC.CH1_DAR0: NA +func (o *DMAC_Type) SetCH1_DAR0(value uint32) { + volatile.StoreUint32(&o.CH1_DAR0.Reg, value) +} +func (o *DMAC_Type) GetCH1_DAR0() uint32 { + return volatile.LoadUint32(&o.CH1_DAR0.Reg) +} + +// DMAC.CH1_DAR1: NA +func (o *DMAC_Type) SetCH1_DAR1(value uint32) { + volatile.StoreUint32(&o.CH1_DAR1.Reg, value) +} +func (o *DMAC_Type) GetCH1_DAR1() uint32 { + return volatile.LoadUint32(&o.CH1_DAR1.Reg) +} + +// DMAC.CH1_BLOCK_TS0: NA +func (o *DMAC_Type) SetCH1_BLOCK_TS0_CH1_BLOCK_TS(value uint32) { + volatile.StoreUint32(&o.CH1_BLOCK_TS0.Reg, volatile.LoadUint32(&o.CH1_BLOCK_TS0.Reg)&^(0x3fffff)|value) +} +func (o *DMAC_Type) GetCH1_BLOCK_TS0_CH1_BLOCK_TS() uint32 { + return volatile.LoadUint32(&o.CH1_BLOCK_TS0.Reg) & 0x3fffff +} + +// DMAC.CH1_CTL0: NA +func (o *DMAC_Type) SetCH1_CTL0_CH1_SMS(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_SMS() uint32 { + return volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_DMS(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_DMS() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_SINC(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_SINC() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_DINC(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_DINC() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_SRC_TR_WIDTH(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x700)|value<<8) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_SRC_TR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x700) >> 8 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_DST_TR_WIDTH(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3800)|value<<11) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_DST_TR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3800) >> 11 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_SRC_MSIZE(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3c000)|value<<14) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_SRC_MSIZE() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3c000) >> 14 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_DST_MSIZE(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3c0000)|value<<18) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_DST_MSIZE() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3c0000) >> 18 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_AR_CACHE(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_AR_CACHE() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3c00000) >> 22 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_AW_CACHE(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3c000000)|value<<26) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_AW_CACHE() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3c000000) >> 26 +} +func (o *DMAC_Type) SetCH1_CTL0_CH1_NONPOSTED_LASTWRITE_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH1_CTL0_CH1_NONPOSTED_LASTWRITE_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x40000000) >> 30 +} + +// DMAC.CH1_CTL1: NA +func (o *DMAC_Type) SetCH1_CTL1_CH1_AR_PROT(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x7)|value) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_AR_PROT() uint32 { + return volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x7 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_AW_PROT(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x38)|value<<3) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_AW_PROT() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x38) >> 3 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_ARLEN_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_ARLEN_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_ARLEN(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x7f80)|value<<7) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_ARLEN() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x7f80) >> 7 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_AWLEN_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x8000)|value<<15) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_AWLEN_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x8000) >> 15 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_AWLEN(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0xff0000)|value<<16) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_AWLEN() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0xff0000) >> 16 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_SRC_STAT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_SRC_STAT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x1000000) >> 24 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_DST_STAT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_DST_STAT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_IOC_BLKTFR(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_IOC_BLKTFR() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x4000000) >> 26 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_SHADOWREG_OR_LLI_LAST(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_SHADOWREG_OR_LLI_LAST() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH1_CTL1_CH1_SHADOWREG_OR_LLI_VALID(value uint32) { + volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH1_CTL1_CH1_SHADOWREG_OR_LLI_VALID() uint32 { + return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH1_CFG0: NA +func (o *DMAC_Type) SetCH1_CFG0_CH1_SRC_MULTBLK_TYPE(value uint32) { + volatile.StoreUint32(&o.CH1_CFG0.Reg, volatile.LoadUint32(&o.CH1_CFG0.Reg)&^(0x3)|value) +} +func (o *DMAC_Type) GetCH1_CFG0_CH1_SRC_MULTBLK_TYPE() uint32 { + return volatile.LoadUint32(&o.CH1_CFG0.Reg) & 0x3 +} +func (o *DMAC_Type) SetCH1_CFG0_CH1_DST_MULTBLK_TYPE(value uint32) { + volatile.StoreUint32(&o.CH1_CFG0.Reg, volatile.LoadUint32(&o.CH1_CFG0.Reg)&^(0xc)|value<<2) +} +func (o *DMAC_Type) GetCH1_CFG0_CH1_DST_MULTBLK_TYPE() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG0.Reg) & 0xc) >> 2 +} +func (o *DMAC_Type) SetCH1_CFG0_CH1_RD_UID(value uint32) { + volatile.StoreUint32(&o.CH1_CFG0.Reg, volatile.LoadUint32(&o.CH1_CFG0.Reg)&^(0x3c0000)|value<<18) +} +func (o *DMAC_Type) GetCH1_CFG0_CH1_RD_UID() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG0.Reg) & 0x3c0000) >> 18 +} +func (o *DMAC_Type) SetCH1_CFG0_CH1_WR_UID(value uint32) { + volatile.StoreUint32(&o.CH1_CFG0.Reg, volatile.LoadUint32(&o.CH1_CFG0.Reg)&^(0x1e000000)|value<<25) +} +func (o *DMAC_Type) GetCH1_CFG0_CH1_WR_UID() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG0.Reg) & 0x1e000000) >> 25 +} + +// DMAC.CH1_CFG1: NA +func (o *DMAC_Type) SetCH1_CFG1_CH1_TT_FC(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x7)|value) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_TT_FC() uint32 { + return volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x7 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_HS_SEL_SRC(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_HS_SEL_SRC() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_HS_SEL_DST(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_HS_SEL_DST() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_SRC_HWHS_POL(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_SRC_HWHS_POL() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_DST_HWHS_POL(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_DST_HWHS_POL() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_SRC_PER(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x180)|value<<7) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_SRC_PER() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x180) >> 7 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_DST_PER(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x3000)|value<<12) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_DST_PER() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x3000) >> 12 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_CH_PRIOR(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0xe0000)|value<<17) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_CH_PRIOR() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0xe0000) >> 17 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_LOCK_CH(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_LOCK_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_LOCK_CH_L(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x600000)|value<<21) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_LOCK_CH_L() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x600000) >> 21 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_SRC_OSR_LMT(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x7800000)|value<<23) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_SRC_OSR_LMT() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x7800000) >> 23 +} +func (o *DMAC_Type) SetCH1_CFG1_CH1_DST_OSR_LMT(value uint32) { + volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x78000000)|value<<27) +} +func (o *DMAC_Type) GetCH1_CFG1_CH1_DST_OSR_LMT() uint32 { + return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x78000000) >> 27 +} + +// DMAC.CH1_LLP0: NA +func (o *DMAC_Type) SetCH1_LLP0_CH1_LMS(value uint32) { + volatile.StoreUint32(&o.CH1_LLP0.Reg, volatile.LoadUint32(&o.CH1_LLP0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_LLP0_CH1_LMS() uint32 { + return volatile.LoadUint32(&o.CH1_LLP0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_LLP0_CH1_LOC0(value uint32) { + volatile.StoreUint32(&o.CH1_LLP0.Reg, volatile.LoadUint32(&o.CH1_LLP0.Reg)&^(0xffffffc0)|value<<6) +} +func (o *DMAC_Type) GetCH1_LLP0_CH1_LOC0() uint32 { + return (volatile.LoadUint32(&o.CH1_LLP0.Reg) & 0xffffffc0) >> 6 +} + +// DMAC.CH1_LLP1: NA +func (o *DMAC_Type) SetCH1_LLP1(value uint32) { + volatile.StoreUint32(&o.CH1_LLP1.Reg, value) +} +func (o *DMAC_Type) GetCH1_LLP1() uint32 { + return volatile.LoadUint32(&o.CH1_LLP1.Reg) +} + +// DMAC.CH1_STATUS0: NA +func (o *DMAC_Type) SetCH1_STATUS0_CH1_CMPLTD_BLK_TFR_SIZE(value uint32) { + volatile.StoreUint32(&o.CH1_STATUS0.Reg, volatile.LoadUint32(&o.CH1_STATUS0.Reg)&^(0x3fffff)|value) +} +func (o *DMAC_Type) GetCH1_STATUS0_CH1_CMPLTD_BLK_TFR_SIZE() uint32 { + return volatile.LoadUint32(&o.CH1_STATUS0.Reg) & 0x3fffff +} + +// DMAC.CH1_STATUS1: NA +func (o *DMAC_Type) SetCH1_STATUS1_CH1_DATA_LEFT_IN_FIFO(value uint32) { + volatile.StoreUint32(&o.CH1_STATUS1.Reg, volatile.LoadUint32(&o.CH1_STATUS1.Reg)&^(0x7fff)|value) +} +func (o *DMAC_Type) GetCH1_STATUS1_CH1_DATA_LEFT_IN_FIFO() uint32 { + return volatile.LoadUint32(&o.CH1_STATUS1.Reg) & 0x7fff +} + +// DMAC.CH1_SWHSSRC0: NA +func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_REQ_SRC(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_REQ_SRC() uint32 { + return volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_REQ_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_REQ_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_LST_SRC(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_LST_SRC() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_LST_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_LST_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x20) >> 5 +} + +// DMAC.CH1_SWHSDST0: NA +func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_REQ_DST(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_REQ_DST() uint32 { + return volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_REQ_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_REQ_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_SGLREQ_DST(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_SGLREQ_DST() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_SGLREQ_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_SGLREQ_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_LST_DST(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_LST_DST() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_LST_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_LST_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x20) >> 5 +} + +// DMAC.CH1_BLK_TFR_RESUMEREQ0: NA +func (o *DMAC_Type) SetCH1_BLK_TFR_RESUMEREQ0_CH1_BLK_TFR_RESUMEREQ(value uint32) { + volatile.StoreUint32(&o.CH1_BLK_TFR_RESUMEREQ0.Reg, volatile.LoadUint32(&o.CH1_BLK_TFR_RESUMEREQ0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_BLK_TFR_RESUMEREQ0_CH1_BLK_TFR_RESUMEREQ() uint32 { + return volatile.LoadUint32(&o.CH1_BLK_TFR_RESUMEREQ0.Reg) & 0x1 +} + +// DMAC.CH1_AXI_ID0: NA +func (o *DMAC_Type) SetCH1_AXI_ID0_CH1_AXI_READ_ID_SUFFIX(value uint32) { + volatile.StoreUint32(&o.CH1_AXI_ID0.Reg, volatile.LoadUint32(&o.CH1_AXI_ID0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_AXI_ID0_CH1_AXI_READ_ID_SUFFIX() uint32 { + return volatile.LoadUint32(&o.CH1_AXI_ID0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_AXI_ID0_CH1_AXI_WRITE_ID_SUFFIX(value uint32) { + volatile.StoreUint32(&o.CH1_AXI_ID0.Reg, volatile.LoadUint32(&o.CH1_AXI_ID0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH1_AXI_ID0_CH1_AXI_WRITE_ID_SUFFIX() uint32 { + return (volatile.LoadUint32(&o.CH1_AXI_ID0.Reg) & 0x10000) >> 16 +} + +// DMAC.CH1_AXI_QOS0: NA +func (o *DMAC_Type) SetCH1_AXI_QOS0_CH1_AXI_AWQOS(value uint32) { + volatile.StoreUint32(&o.CH1_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH1_AXI_QOS0.Reg)&^(0xf)|value) +} +func (o *DMAC_Type) GetCH1_AXI_QOS0_CH1_AXI_AWQOS() uint32 { + return volatile.LoadUint32(&o.CH1_AXI_QOS0.Reg) & 0xf +} +func (o *DMAC_Type) SetCH1_AXI_QOS0_CH1_AXI_ARQOS(value uint32) { + volatile.StoreUint32(&o.CH1_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH1_AXI_QOS0.Reg)&^(0xf0)|value<<4) +} +func (o *DMAC_Type) GetCH1_AXI_QOS0_CH1_AXI_ARQOS() uint32 { + return (volatile.LoadUint32(&o.CH1_AXI_QOS0.Reg) & 0xf0) >> 4 +} + +// DMAC.CH1_SSTAT0: NA +func (o *DMAC_Type) SetCH1_SSTAT0(value uint32) { + volatile.StoreUint32(&o.CH1_SSTAT0.Reg, value) +} +func (o *DMAC_Type) GetCH1_SSTAT0() uint32 { + return volatile.LoadUint32(&o.CH1_SSTAT0.Reg) +} + +// DMAC.CH1_DSTAT0: NA +func (o *DMAC_Type) SetCH1_DSTAT0(value uint32) { + volatile.StoreUint32(&o.CH1_DSTAT0.Reg, value) +} +func (o *DMAC_Type) GetCH1_DSTAT0() uint32 { + return volatile.LoadUint32(&o.CH1_DSTAT0.Reg) +} + +// DMAC.CH1_SSTATAR0: NA +func (o *DMAC_Type) SetCH1_SSTATAR0(value uint32) { + volatile.StoreUint32(&o.CH1_SSTATAR0.Reg, value) +} +func (o *DMAC_Type) GetCH1_SSTATAR0() uint32 { + return volatile.LoadUint32(&o.CH1_SSTATAR0.Reg) +} + +// DMAC.CH1_SSTATAR1: NA +func (o *DMAC_Type) SetCH1_SSTATAR1(value uint32) { + volatile.StoreUint32(&o.CH1_SSTATAR1.Reg, value) +} +func (o *DMAC_Type) GetCH1_SSTATAR1() uint32 { + return volatile.LoadUint32(&o.CH1_SSTATAR1.Reg) +} + +// DMAC.CH1_DSTATAR0: NA +func (o *DMAC_Type) SetCH1_DSTATAR0(value uint32) { + volatile.StoreUint32(&o.CH1_DSTATAR0.Reg, value) +} +func (o *DMAC_Type) GetCH1_DSTATAR0() uint32 { + return volatile.LoadUint32(&o.CH1_DSTATAR0.Reg) +} + +// DMAC.CH1_DSTATAR1: NA +func (o *DMAC_Type) SetCH1_DSTATAR1(value uint32) { + volatile.StoreUint32(&o.CH1_DSTATAR1.Reg, value) +} +func (o *DMAC_Type) GetCH1_DSTATAR1() uint32 { + return volatile.LoadUint32(&o.CH1_DSTATAR1.Reg) +} + +// DMAC.CH1_INTSTATUS_ENABLE0: NA +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH1_INTSTATUS_ENABLE1: NA +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg) & 0x8) >> 3 +} + +// DMAC.CH1_INTSTATUS0: NA +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH1_INTSTATUS1: NA +func (o *DMAC_Type) SetCH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg) & 0x8) >> 3 +} + +// DMAC.CH1_INTSIGNAL_ENABLE0: NA +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL() uint32 { + return volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH1_INTSIGNAL_ENABLE1: NA +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL() uint32 { + return volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg) & 0x8) >> 3 +} + +// DMAC.CH1_INTCLEAR0: NA +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH1_INTCLEAR1: NA +func (o *DMAC_Type) SetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH1_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg) & 0x8) >> 3 +} + +// DMAC.CH2_SAR0: NA +func (o *DMAC_Type) SetCH2_SAR0(value uint32) { + volatile.StoreUint32(&o.CH2_SAR0.Reg, value) +} +func (o *DMAC_Type) GetCH2_SAR0() uint32 { + return volatile.LoadUint32(&o.CH2_SAR0.Reg) +} + +// DMAC.CH2_SAR1: NA +func (o *DMAC_Type) SetCH2_SAR1(value uint32) { + volatile.StoreUint32(&o.CH2_SAR1.Reg, value) +} +func (o *DMAC_Type) GetCH2_SAR1() uint32 { + return volatile.LoadUint32(&o.CH2_SAR1.Reg) +} + +// DMAC.CH2_DAR0: NA +func (o *DMAC_Type) SetCH2_DAR0(value uint32) { + volatile.StoreUint32(&o.CH2_DAR0.Reg, value) +} +func (o *DMAC_Type) GetCH2_DAR0() uint32 { + return volatile.LoadUint32(&o.CH2_DAR0.Reg) +} + +// DMAC.CH2_DAR1: NA +func (o *DMAC_Type) SetCH2_DAR1(value uint32) { + volatile.StoreUint32(&o.CH2_DAR1.Reg, value) +} +func (o *DMAC_Type) GetCH2_DAR1() uint32 { + return volatile.LoadUint32(&o.CH2_DAR1.Reg) +} + +// DMAC.CH2_BLOCK_TS0: NA +func (o *DMAC_Type) SetCH2_BLOCK_TS0_CH2_BLOCK_TS(value uint32) { + volatile.StoreUint32(&o.CH2_BLOCK_TS0.Reg, volatile.LoadUint32(&o.CH2_BLOCK_TS0.Reg)&^(0x3fffff)|value) +} +func (o *DMAC_Type) GetCH2_BLOCK_TS0_CH2_BLOCK_TS() uint32 { + return volatile.LoadUint32(&o.CH2_BLOCK_TS0.Reg) & 0x3fffff +} + +// DMAC.CH2_CTL0: NA +func (o *DMAC_Type) SetCH2_CTL0_CH2_SMS(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_SMS() uint32 { + return volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_DMS(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_DMS() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_SINC(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_SINC() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_DINC(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_DINC() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_SRC_TR_WIDTH(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x700)|value<<8) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_SRC_TR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x700) >> 8 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_DST_TR_WIDTH(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3800)|value<<11) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_DST_TR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3800) >> 11 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_SRC_MSIZE(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3c000)|value<<14) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_SRC_MSIZE() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3c000) >> 14 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_DST_MSIZE(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3c0000)|value<<18) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_DST_MSIZE() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3c0000) >> 18 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_AR_CACHE(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_AR_CACHE() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3c00000) >> 22 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_AW_CACHE(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3c000000)|value<<26) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_AW_CACHE() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3c000000) >> 26 +} +func (o *DMAC_Type) SetCH2_CTL0_CH2_NONPOSTED_LASTWRITE_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH2_CTL0_CH2_NONPOSTED_LASTWRITE_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x40000000) >> 30 +} + +// DMAC.CH2_CTL1: NA +func (o *DMAC_Type) SetCH2_CTL1_CH2_AR_PROT(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x7)|value) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_AR_PROT() uint32 { + return volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x7 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_AW_PROT(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x38)|value<<3) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_AW_PROT() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x38) >> 3 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_ARLEN_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_ARLEN_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_ARLEN(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x7f80)|value<<7) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_ARLEN() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x7f80) >> 7 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_AWLEN_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x8000)|value<<15) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_AWLEN_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x8000) >> 15 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_AWLEN(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0xff0000)|value<<16) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_AWLEN() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0xff0000) >> 16 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_SRC_STAT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_SRC_STAT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x1000000) >> 24 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_DST_STAT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_DST_STAT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_IOC_BLKTFR(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_IOC_BLKTFR() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x4000000) >> 26 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_SHADOWREG_OR_LLI_LAST(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_SHADOWREG_OR_LLI_LAST() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH2_CTL1_CH2_SHADOWREG_OR_LLI_VALID(value uint32) { + volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH2_CTL1_CH2_SHADOWREG_OR_LLI_VALID() uint32 { + return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH2_CFG0: NA +func (o *DMAC_Type) SetCH2_CFG0_CH2_SRC_MULTBLK_TYPE(value uint32) { + volatile.StoreUint32(&o.CH2_CFG0.Reg, volatile.LoadUint32(&o.CH2_CFG0.Reg)&^(0x3)|value) +} +func (o *DMAC_Type) GetCH2_CFG0_CH2_SRC_MULTBLK_TYPE() uint32 { + return volatile.LoadUint32(&o.CH2_CFG0.Reg) & 0x3 +} +func (o *DMAC_Type) SetCH2_CFG0_CH2_DST_MULTBLK_TYPE(value uint32) { + volatile.StoreUint32(&o.CH2_CFG0.Reg, volatile.LoadUint32(&o.CH2_CFG0.Reg)&^(0xc)|value<<2) +} +func (o *DMAC_Type) GetCH2_CFG0_CH2_DST_MULTBLK_TYPE() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG0.Reg) & 0xc) >> 2 +} +func (o *DMAC_Type) SetCH2_CFG0_CH2_RD_UID(value uint32) { + volatile.StoreUint32(&o.CH2_CFG0.Reg, volatile.LoadUint32(&o.CH2_CFG0.Reg)&^(0x3c0000)|value<<18) +} +func (o *DMAC_Type) GetCH2_CFG0_CH2_RD_UID() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG0.Reg) & 0x3c0000) >> 18 +} +func (o *DMAC_Type) SetCH2_CFG0_CH2_WR_UID(value uint32) { + volatile.StoreUint32(&o.CH2_CFG0.Reg, volatile.LoadUint32(&o.CH2_CFG0.Reg)&^(0x1e000000)|value<<25) +} +func (o *DMAC_Type) GetCH2_CFG0_CH2_WR_UID() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG0.Reg) & 0x1e000000) >> 25 +} + +// DMAC.CH2_CFG1: NA +func (o *DMAC_Type) SetCH2_CFG1_CH2_TT_FC(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x7)|value) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_TT_FC() uint32 { + return volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x7 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_HS_SEL_SRC(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_HS_SEL_SRC() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_HS_SEL_DST(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_HS_SEL_DST() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_SRC_HWHS_POL(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_SRC_HWHS_POL() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_DST_HWHS_POL(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_DST_HWHS_POL() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_SRC_PER(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x180)|value<<7) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_SRC_PER() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x180) >> 7 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_DST_PER(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x3000)|value<<12) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_DST_PER() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x3000) >> 12 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_CH_PRIOR(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0xe0000)|value<<17) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_CH_PRIOR() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0xe0000) >> 17 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_LOCK_CH(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_LOCK_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_LOCK_CH_L(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x600000)|value<<21) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_LOCK_CH_L() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x600000) >> 21 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_SRC_OSR_LMT(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x7800000)|value<<23) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_SRC_OSR_LMT() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x7800000) >> 23 +} +func (o *DMAC_Type) SetCH2_CFG1_CH2_DST_OSR_LMT(value uint32) { + volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x78000000)|value<<27) +} +func (o *DMAC_Type) GetCH2_CFG1_CH2_DST_OSR_LMT() uint32 { + return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x78000000) >> 27 +} + +// DMAC.CH2_LLP0: NA +func (o *DMAC_Type) SetCH2_LLP0_CH2_LMS(value uint32) { + volatile.StoreUint32(&o.CH2_LLP0.Reg, volatile.LoadUint32(&o.CH2_LLP0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_LLP0_CH2_LMS() uint32 { + return volatile.LoadUint32(&o.CH2_LLP0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_LLP0_CH2_LOC0(value uint32) { + volatile.StoreUint32(&o.CH2_LLP0.Reg, volatile.LoadUint32(&o.CH2_LLP0.Reg)&^(0xffffffc0)|value<<6) +} +func (o *DMAC_Type) GetCH2_LLP0_CH2_LOC0() uint32 { + return (volatile.LoadUint32(&o.CH2_LLP0.Reg) & 0xffffffc0) >> 6 +} + +// DMAC.CH2_LLP1: NA +func (o *DMAC_Type) SetCH2_LLP1(value uint32) { + volatile.StoreUint32(&o.CH2_LLP1.Reg, value) +} +func (o *DMAC_Type) GetCH2_LLP1() uint32 { + return volatile.LoadUint32(&o.CH2_LLP1.Reg) +} + +// DMAC.CH2_STATUS0: NA +func (o *DMAC_Type) SetCH2_STATUS0_CH2_CMPLTD_BLK_TFR_SIZE(value uint32) { + volatile.StoreUint32(&o.CH2_STATUS0.Reg, volatile.LoadUint32(&o.CH2_STATUS0.Reg)&^(0x3fffff)|value) +} +func (o *DMAC_Type) GetCH2_STATUS0_CH2_CMPLTD_BLK_TFR_SIZE() uint32 { + return volatile.LoadUint32(&o.CH2_STATUS0.Reg) & 0x3fffff +} + +// DMAC.CH2_STATUS1: NA +func (o *DMAC_Type) SetCH2_STATUS1_CH2_DATA_LEFT_IN_FIFO(value uint32) { + volatile.StoreUint32(&o.CH2_STATUS1.Reg, volatile.LoadUint32(&o.CH2_STATUS1.Reg)&^(0x7fff)|value) +} +func (o *DMAC_Type) GetCH2_STATUS1_CH2_DATA_LEFT_IN_FIFO() uint32 { + return volatile.LoadUint32(&o.CH2_STATUS1.Reg) & 0x7fff +} + +// DMAC.CH2_SWHSSRC0: NA +func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_REQ_SRC(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_REQ_SRC() uint32 { + return volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_REQ_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_REQ_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_LST_SRC(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_LST_SRC() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_LST_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_LST_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x20) >> 5 +} + +// DMAC.CH2_SWHSDST0: NA +func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_REQ_DST(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_REQ_DST() uint32 { + return volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_REQ_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_REQ_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_SGLREQ_DST(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_SGLREQ_DST() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_SGLREQ_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_SGLREQ_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_LST_DST(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_LST_DST() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_LST_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_LST_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x20) >> 5 +} + +// DMAC.CH2_BLK_TFR_RESUMEREQ0: NA +func (o *DMAC_Type) SetCH2_BLK_TFR_RESUMEREQ0_CH2_BLK_TFR_RESUMEREQ(value uint32) { + volatile.StoreUint32(&o.CH2_BLK_TFR_RESUMEREQ0.Reg, volatile.LoadUint32(&o.CH2_BLK_TFR_RESUMEREQ0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_BLK_TFR_RESUMEREQ0_CH2_BLK_TFR_RESUMEREQ() uint32 { + return volatile.LoadUint32(&o.CH2_BLK_TFR_RESUMEREQ0.Reg) & 0x1 +} + +// DMAC.CH2_AXI_ID0: NA +func (o *DMAC_Type) SetCH2_AXI_ID0_CH2_AXI_READ_ID_SUFFIX(value uint32) { + volatile.StoreUint32(&o.CH2_AXI_ID0.Reg, volatile.LoadUint32(&o.CH2_AXI_ID0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_AXI_ID0_CH2_AXI_READ_ID_SUFFIX() uint32 { + return volatile.LoadUint32(&o.CH2_AXI_ID0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_AXI_ID0_CH2_AXI_WRITE_ID_SUFFIX(value uint32) { + volatile.StoreUint32(&o.CH2_AXI_ID0.Reg, volatile.LoadUint32(&o.CH2_AXI_ID0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH2_AXI_ID0_CH2_AXI_WRITE_ID_SUFFIX() uint32 { + return (volatile.LoadUint32(&o.CH2_AXI_ID0.Reg) & 0x10000) >> 16 +} + +// DMAC.CH2_AXI_QOS0: NA +func (o *DMAC_Type) SetCH2_AXI_QOS0_CH2_AXI_AWQOS(value uint32) { + volatile.StoreUint32(&o.CH2_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH2_AXI_QOS0.Reg)&^(0xf)|value) +} +func (o *DMAC_Type) GetCH2_AXI_QOS0_CH2_AXI_AWQOS() uint32 { + return volatile.LoadUint32(&o.CH2_AXI_QOS0.Reg) & 0xf +} +func (o *DMAC_Type) SetCH2_AXI_QOS0_CH2_AXI_ARQOS(value uint32) { + volatile.StoreUint32(&o.CH2_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH2_AXI_QOS0.Reg)&^(0xf0)|value<<4) +} +func (o *DMAC_Type) GetCH2_AXI_QOS0_CH2_AXI_ARQOS() uint32 { + return (volatile.LoadUint32(&o.CH2_AXI_QOS0.Reg) & 0xf0) >> 4 +} + +// DMAC.CH2_SSTAT0: NA +func (o *DMAC_Type) SetCH2_SSTAT0(value uint32) { + volatile.StoreUint32(&o.CH2_SSTAT0.Reg, value) +} +func (o *DMAC_Type) GetCH2_SSTAT0() uint32 { + return volatile.LoadUint32(&o.CH2_SSTAT0.Reg) +} + +// DMAC.CH2_DSTAT0: NA +func (o *DMAC_Type) SetCH2_DSTAT0(value uint32) { + volatile.StoreUint32(&o.CH2_DSTAT0.Reg, value) +} +func (o *DMAC_Type) GetCH2_DSTAT0() uint32 { + return volatile.LoadUint32(&o.CH2_DSTAT0.Reg) +} + +// DMAC.CH2_SSTATAR0: NA +func (o *DMAC_Type) SetCH2_SSTATAR0(value uint32) { + volatile.StoreUint32(&o.CH2_SSTATAR0.Reg, value) +} +func (o *DMAC_Type) GetCH2_SSTATAR0() uint32 { + return volatile.LoadUint32(&o.CH2_SSTATAR0.Reg) +} + +// DMAC.CH2_SSTATAR1: NA +func (o *DMAC_Type) SetCH2_SSTATAR1(value uint32) { + volatile.StoreUint32(&o.CH2_SSTATAR1.Reg, value) +} +func (o *DMAC_Type) GetCH2_SSTATAR1() uint32 { + return volatile.LoadUint32(&o.CH2_SSTATAR1.Reg) +} + +// DMAC.CH2_DSTATAR0: NA +func (o *DMAC_Type) SetCH2_DSTATAR0(value uint32) { + volatile.StoreUint32(&o.CH2_DSTATAR0.Reg, value) +} +func (o *DMAC_Type) GetCH2_DSTATAR0() uint32 { + return volatile.LoadUint32(&o.CH2_DSTATAR0.Reg) +} + +// DMAC.CH2_DSTATAR1: NA +func (o *DMAC_Type) SetCH2_DSTATAR1(value uint32) { + volatile.StoreUint32(&o.CH2_DSTATAR1.Reg, value) +} +func (o *DMAC_Type) GetCH2_DSTATAR1() uint32 { + return volatile.LoadUint32(&o.CH2_DSTATAR1.Reg) +} + +// DMAC.CH2_INTSTATUS_ENABLE0: NA +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH2_INTSTATUS_ENABLE1: NA +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg) & 0x8) >> 3 +} + +// DMAC.CH2_INTSTATUS0: NA +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH2_INTSTATUS1: NA +func (o *DMAC_Type) SetCH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg) & 0x8) >> 3 +} + +// DMAC.CH2_INTSIGNAL_ENABLE0: NA +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL() uint32 { + return volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH2_INTSIGNAL_ENABLE1: NA +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL() uint32 { + return volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg) & 0x8) >> 3 +} + +// DMAC.CH2_INTCLEAR0: NA +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH2_INTCLEAR1: NA +func (o *DMAC_Type) SetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH2_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg) & 0x8) >> 3 +} + +// DMAC.CH3_SAR0: NA +func (o *DMAC_Type) SetCH3_SAR0(value uint32) { + volatile.StoreUint32(&o.CH3_SAR0.Reg, value) +} +func (o *DMAC_Type) GetCH3_SAR0() uint32 { + return volatile.LoadUint32(&o.CH3_SAR0.Reg) +} + +// DMAC.CH3_SAR1: NA +func (o *DMAC_Type) SetCH3_SAR1(value uint32) { + volatile.StoreUint32(&o.CH3_SAR1.Reg, value) +} +func (o *DMAC_Type) GetCH3_SAR1() uint32 { + return volatile.LoadUint32(&o.CH3_SAR1.Reg) +} + +// DMAC.CH3_DAR0: NA +func (o *DMAC_Type) SetCH3_DAR0(value uint32) { + volatile.StoreUint32(&o.CH3_DAR0.Reg, value) +} +func (o *DMAC_Type) GetCH3_DAR0() uint32 { + return volatile.LoadUint32(&o.CH3_DAR0.Reg) +} + +// DMAC.CH3_DAR1: NA +func (o *DMAC_Type) SetCH3_DAR1(value uint32) { + volatile.StoreUint32(&o.CH3_DAR1.Reg, value) +} +func (o *DMAC_Type) GetCH3_DAR1() uint32 { + return volatile.LoadUint32(&o.CH3_DAR1.Reg) +} + +// DMAC.CH3_BLOCK_TS0: NA +func (o *DMAC_Type) SetCH3_BLOCK_TS0_CH3_BLOCK_TS(value uint32) { + volatile.StoreUint32(&o.CH3_BLOCK_TS0.Reg, volatile.LoadUint32(&o.CH3_BLOCK_TS0.Reg)&^(0x3fffff)|value) +} +func (o *DMAC_Type) GetCH3_BLOCK_TS0_CH3_BLOCK_TS() uint32 { + return volatile.LoadUint32(&o.CH3_BLOCK_TS0.Reg) & 0x3fffff +} + +// DMAC.CH3_CTL0: NA +func (o *DMAC_Type) SetCH3_CTL0_CH3_SMS(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_SMS() uint32 { + return volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_DMS(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_DMS() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_SINC(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_SINC() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_DINC(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_DINC() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_SRC_TR_WIDTH(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x700)|value<<8) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_SRC_TR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x700) >> 8 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_DST_TR_WIDTH(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3800)|value<<11) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_DST_TR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3800) >> 11 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_SRC_MSIZE(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3c000)|value<<14) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_SRC_MSIZE() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3c000) >> 14 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_DST_MSIZE(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3c0000)|value<<18) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_DST_MSIZE() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3c0000) >> 18 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_AR_CACHE(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_AR_CACHE() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3c00000) >> 22 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_AW_CACHE(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3c000000)|value<<26) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_AW_CACHE() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3c000000) >> 26 +} +func (o *DMAC_Type) SetCH3_CTL0_CH3_NONPOSTED_LASTWRITE_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH3_CTL0_CH3_NONPOSTED_LASTWRITE_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x40000000) >> 30 +} + +// DMAC.CH3_CTL1: NA +func (o *DMAC_Type) SetCH3_CTL1_CH3_AR_PROT(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x7)|value) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_AR_PROT() uint32 { + return volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x7 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_AW_PROT(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x38)|value<<3) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_AW_PROT() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x38) >> 3 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_ARLEN_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_ARLEN_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_ARLEN(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x7f80)|value<<7) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_ARLEN() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x7f80) >> 7 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_AWLEN_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x8000)|value<<15) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_AWLEN_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x8000) >> 15 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_AWLEN(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0xff0000)|value<<16) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_AWLEN() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0xff0000) >> 16 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_SRC_STAT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_SRC_STAT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x1000000) >> 24 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_DST_STAT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_DST_STAT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_IOC_BLKTFR(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_IOC_BLKTFR() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x4000000) >> 26 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_SHADOWREG_OR_LLI_LAST(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_SHADOWREG_OR_LLI_LAST() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH3_CTL1_CH3_SHADOWREG_OR_LLI_VALID(value uint32) { + volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH3_CTL1_CH3_SHADOWREG_OR_LLI_VALID() uint32 { + return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH3_CFG0: NA +func (o *DMAC_Type) SetCH3_CFG0_CH3_SRC_MULTBLK_TYPE(value uint32) { + volatile.StoreUint32(&o.CH3_CFG0.Reg, volatile.LoadUint32(&o.CH3_CFG0.Reg)&^(0x3)|value) +} +func (o *DMAC_Type) GetCH3_CFG0_CH3_SRC_MULTBLK_TYPE() uint32 { + return volatile.LoadUint32(&o.CH3_CFG0.Reg) & 0x3 +} +func (o *DMAC_Type) SetCH3_CFG0_CH3_DST_MULTBLK_TYPE(value uint32) { + volatile.StoreUint32(&o.CH3_CFG0.Reg, volatile.LoadUint32(&o.CH3_CFG0.Reg)&^(0xc)|value<<2) +} +func (o *DMAC_Type) GetCH3_CFG0_CH3_DST_MULTBLK_TYPE() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG0.Reg) & 0xc) >> 2 +} +func (o *DMAC_Type) SetCH3_CFG0_CH3_RD_UID(value uint32) { + volatile.StoreUint32(&o.CH3_CFG0.Reg, volatile.LoadUint32(&o.CH3_CFG0.Reg)&^(0x3c0000)|value<<18) +} +func (o *DMAC_Type) GetCH3_CFG0_CH3_RD_UID() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG0.Reg) & 0x3c0000) >> 18 +} +func (o *DMAC_Type) SetCH3_CFG0_CH3_WR_UID(value uint32) { + volatile.StoreUint32(&o.CH3_CFG0.Reg, volatile.LoadUint32(&o.CH3_CFG0.Reg)&^(0x1e000000)|value<<25) +} +func (o *DMAC_Type) GetCH3_CFG0_CH3_WR_UID() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG0.Reg) & 0x1e000000) >> 25 +} + +// DMAC.CH3_CFG1: NA +func (o *DMAC_Type) SetCH3_CFG1_CH3_TT_FC(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x7)|value) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_TT_FC() uint32 { + return volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x7 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_HS_SEL_SRC(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_HS_SEL_SRC() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_HS_SEL_DST(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_HS_SEL_DST() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_SRC_HWHS_POL(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_SRC_HWHS_POL() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_DST_HWHS_POL(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_DST_HWHS_POL() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_SRC_PER(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x180)|value<<7) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_SRC_PER() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x180) >> 7 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_DST_PER(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x3000)|value<<12) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_DST_PER() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x3000) >> 12 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_CH_PRIOR(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0xe0000)|value<<17) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_CH_PRIOR() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0xe0000) >> 17 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_LOCK_CH(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_LOCK_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_LOCK_CH_L(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x600000)|value<<21) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_LOCK_CH_L() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x600000) >> 21 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_SRC_OSR_LMT(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x7800000)|value<<23) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_SRC_OSR_LMT() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x7800000) >> 23 +} +func (o *DMAC_Type) SetCH3_CFG1_CH3_DST_OSR_LMT(value uint32) { + volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x78000000)|value<<27) +} +func (o *DMAC_Type) GetCH3_CFG1_CH3_DST_OSR_LMT() uint32 { + return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x78000000) >> 27 +} + +// DMAC.CH3_LLP0: NA +func (o *DMAC_Type) SetCH3_LLP0_CH3_LMS(value uint32) { + volatile.StoreUint32(&o.CH3_LLP0.Reg, volatile.LoadUint32(&o.CH3_LLP0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_LLP0_CH3_LMS() uint32 { + return volatile.LoadUint32(&o.CH3_LLP0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_LLP0_CH3_LOC0(value uint32) { + volatile.StoreUint32(&o.CH3_LLP0.Reg, volatile.LoadUint32(&o.CH3_LLP0.Reg)&^(0xffffffc0)|value<<6) +} +func (o *DMAC_Type) GetCH3_LLP0_CH3_LOC0() uint32 { + return (volatile.LoadUint32(&o.CH3_LLP0.Reg) & 0xffffffc0) >> 6 +} + +// DMAC.CH3_LLP1: NA +func (o *DMAC_Type) SetCH3_LLP1(value uint32) { + volatile.StoreUint32(&o.CH3_LLP1.Reg, value) +} +func (o *DMAC_Type) GetCH3_LLP1() uint32 { + return volatile.LoadUint32(&o.CH3_LLP1.Reg) +} + +// DMAC.CH3_STATUS0: NA +func (o *DMAC_Type) SetCH3_STATUS0_CH3_CMPLTD_BLK_TFR_SIZE(value uint32) { + volatile.StoreUint32(&o.CH3_STATUS0.Reg, volatile.LoadUint32(&o.CH3_STATUS0.Reg)&^(0x3fffff)|value) +} +func (o *DMAC_Type) GetCH3_STATUS0_CH3_CMPLTD_BLK_TFR_SIZE() uint32 { + return volatile.LoadUint32(&o.CH3_STATUS0.Reg) & 0x3fffff +} + +// DMAC.CH3_STATUS1: NA +func (o *DMAC_Type) SetCH3_STATUS1_CH3_DATA_LEFT_IN_FIFO(value uint32) { + volatile.StoreUint32(&o.CH3_STATUS1.Reg, volatile.LoadUint32(&o.CH3_STATUS1.Reg)&^(0x7fff)|value) +} +func (o *DMAC_Type) GetCH3_STATUS1_CH3_DATA_LEFT_IN_FIFO() uint32 { + return volatile.LoadUint32(&o.CH3_STATUS1.Reg) & 0x7fff +} + +// DMAC.CH3_SWHSSRC0: NA +func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_REQ_SRC(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_REQ_SRC() uint32 { + return volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_REQ_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_REQ_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_LST_SRC(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_LST_SRC() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_LST_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_LST_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x20) >> 5 +} + +// DMAC.CH3_SWHSDST0: NA +func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_REQ_DST(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_REQ_DST() uint32 { + return volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_REQ_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_REQ_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_SGLREQ_DST(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_SGLREQ_DST() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_SGLREQ_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_SGLREQ_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_LST_DST(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_LST_DST() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_LST_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_LST_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x20) >> 5 +} + +// DMAC.CH3_BLK_TFR_RESUMEREQ0: NA +func (o *DMAC_Type) SetCH3_BLK_TFR_RESUMEREQ0_CH3_BLK_TFR_RESUMEREQ(value uint32) { + volatile.StoreUint32(&o.CH3_BLK_TFR_RESUMEREQ0.Reg, volatile.LoadUint32(&o.CH3_BLK_TFR_RESUMEREQ0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_BLK_TFR_RESUMEREQ0_CH3_BLK_TFR_RESUMEREQ() uint32 { + return volatile.LoadUint32(&o.CH3_BLK_TFR_RESUMEREQ0.Reg) & 0x1 +} + +// DMAC.CH3_AXI_ID0: NA +func (o *DMAC_Type) SetCH3_AXI_ID0_CH3_AXI_READ_ID_SUFFIX(value uint32) { + volatile.StoreUint32(&o.CH3_AXI_ID0.Reg, volatile.LoadUint32(&o.CH3_AXI_ID0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_AXI_ID0_CH3_AXI_READ_ID_SUFFIX() uint32 { + return volatile.LoadUint32(&o.CH3_AXI_ID0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_AXI_ID0_CH3_AXI_WRITE_ID_SUFFIX(value uint32) { + volatile.StoreUint32(&o.CH3_AXI_ID0.Reg, volatile.LoadUint32(&o.CH3_AXI_ID0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH3_AXI_ID0_CH3_AXI_WRITE_ID_SUFFIX() uint32 { + return (volatile.LoadUint32(&o.CH3_AXI_ID0.Reg) & 0x10000) >> 16 +} + +// DMAC.CH3_AXI_QOS0: NA +func (o *DMAC_Type) SetCH3_AXI_QOS0_CH3_AXI_AWQOS(value uint32) { + volatile.StoreUint32(&o.CH3_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH3_AXI_QOS0.Reg)&^(0xf)|value) +} +func (o *DMAC_Type) GetCH3_AXI_QOS0_CH3_AXI_AWQOS() uint32 { + return volatile.LoadUint32(&o.CH3_AXI_QOS0.Reg) & 0xf +} +func (o *DMAC_Type) SetCH3_AXI_QOS0_CH3_AXI_ARQOS(value uint32) { + volatile.StoreUint32(&o.CH3_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH3_AXI_QOS0.Reg)&^(0xf0)|value<<4) +} +func (o *DMAC_Type) GetCH3_AXI_QOS0_CH3_AXI_ARQOS() uint32 { + return (volatile.LoadUint32(&o.CH3_AXI_QOS0.Reg) & 0xf0) >> 4 +} + +// DMAC.CH3_SSTAT0: NA +func (o *DMAC_Type) SetCH3_SSTAT0(value uint32) { + volatile.StoreUint32(&o.CH3_SSTAT0.Reg, value) +} +func (o *DMAC_Type) GetCH3_SSTAT0() uint32 { + return volatile.LoadUint32(&o.CH3_SSTAT0.Reg) +} + +// DMAC.CH3_DSTAT0: NA +func (o *DMAC_Type) SetCH3_DSTAT0(value uint32) { + volatile.StoreUint32(&o.CH3_DSTAT0.Reg, value) +} +func (o *DMAC_Type) GetCH3_DSTAT0() uint32 { + return volatile.LoadUint32(&o.CH3_DSTAT0.Reg) +} + +// DMAC.CH3_SSTATAR0: NA +func (o *DMAC_Type) SetCH3_SSTATAR0(value uint32) { + volatile.StoreUint32(&o.CH3_SSTATAR0.Reg, value) +} +func (o *DMAC_Type) GetCH3_SSTATAR0() uint32 { + return volatile.LoadUint32(&o.CH3_SSTATAR0.Reg) +} + +// DMAC.CH3_SSTATAR1: NA +func (o *DMAC_Type) SetCH3_SSTATAR1(value uint32) { + volatile.StoreUint32(&o.CH3_SSTATAR1.Reg, value) +} +func (o *DMAC_Type) GetCH3_SSTATAR1() uint32 { + return volatile.LoadUint32(&o.CH3_SSTATAR1.Reg) +} + +// DMAC.CH3_DSTATAR0: NA +func (o *DMAC_Type) SetCH3_DSTATAR0(value uint32) { + volatile.StoreUint32(&o.CH3_DSTATAR0.Reg, value) +} +func (o *DMAC_Type) GetCH3_DSTATAR0() uint32 { + return volatile.LoadUint32(&o.CH3_DSTATAR0.Reg) +} + +// DMAC.CH3_DSTATAR1: NA +func (o *DMAC_Type) SetCH3_DSTATAR1(value uint32) { + volatile.StoreUint32(&o.CH3_DSTATAR1.Reg, value) +} +func (o *DMAC_Type) GetCH3_DSTATAR1() uint32 { + return volatile.LoadUint32(&o.CH3_DSTATAR1.Reg) +} + +// DMAC.CH3_INTSTATUS_ENABLE0: NA +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH3_INTSTATUS_ENABLE1: NA +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg) & 0x8) >> 3 +} + +// DMAC.CH3_INTSTATUS0: NA +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH3_INTSTATUS1: NA +func (o *DMAC_Type) SetCH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg) & 0x8) >> 3 +} + +// DMAC.CH3_INTSIGNAL_ENABLE0: NA +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL() uint32 { + return volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH3_INTSIGNAL_ENABLE1: NA +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL() uint32 { + return volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg) & 0x8) >> 3 +} + +// DMAC.CH3_INTCLEAR0: NA +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH3_INTCLEAR1: NA +func (o *DMAC_Type) SetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH3_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg) & 0x8) >> 3 +} + +// DMAC.CH4_SAR0: NA +func (o *DMAC_Type) SetCH4_SAR0(value uint32) { + volatile.StoreUint32(&o.CH4_SAR0.Reg, value) +} +func (o *DMAC_Type) GetCH4_SAR0() uint32 { + return volatile.LoadUint32(&o.CH4_SAR0.Reg) +} + +// DMAC.CH4_SAR1: NA +func (o *DMAC_Type) SetCH4_SAR1(value uint32) { + volatile.StoreUint32(&o.CH4_SAR1.Reg, value) +} +func (o *DMAC_Type) GetCH4_SAR1() uint32 { + return volatile.LoadUint32(&o.CH4_SAR1.Reg) +} + +// DMAC.CH4_DAR0: NA +func (o *DMAC_Type) SetCH4_DAR0(value uint32) { + volatile.StoreUint32(&o.CH4_DAR0.Reg, value) +} +func (o *DMAC_Type) GetCH4_DAR0() uint32 { + return volatile.LoadUint32(&o.CH4_DAR0.Reg) +} + +// DMAC.CH4_DAR1: NA +func (o *DMAC_Type) SetCH4_DAR1(value uint32) { + volatile.StoreUint32(&o.CH4_DAR1.Reg, value) +} +func (o *DMAC_Type) GetCH4_DAR1() uint32 { + return volatile.LoadUint32(&o.CH4_DAR1.Reg) +} + +// DMAC.CH4_BLOCK_TS0: NA +func (o *DMAC_Type) SetCH4_BLOCK_TS0_CH4_BLOCK_TS(value uint32) { + volatile.StoreUint32(&o.CH4_BLOCK_TS0.Reg, volatile.LoadUint32(&o.CH4_BLOCK_TS0.Reg)&^(0x3fffff)|value) +} +func (o *DMAC_Type) GetCH4_BLOCK_TS0_CH4_BLOCK_TS() uint32 { + return volatile.LoadUint32(&o.CH4_BLOCK_TS0.Reg) & 0x3fffff +} + +// DMAC.CH4_CTL0: NA +func (o *DMAC_Type) SetCH4_CTL0_CH4_SMS(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_SMS() uint32 { + return volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_DMS(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_DMS() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_SINC(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_SINC() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_DINC(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_DINC() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_SRC_TR_WIDTH(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x700)|value<<8) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_SRC_TR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x700) >> 8 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_DST_TR_WIDTH(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3800)|value<<11) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_DST_TR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3800) >> 11 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_SRC_MSIZE(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3c000)|value<<14) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_SRC_MSIZE() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3c000) >> 14 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_DST_MSIZE(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3c0000)|value<<18) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_DST_MSIZE() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3c0000) >> 18 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_AR_CACHE(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_AR_CACHE() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3c00000) >> 22 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_AW_CACHE(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3c000000)|value<<26) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_AW_CACHE() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3c000000) >> 26 +} +func (o *DMAC_Type) SetCH4_CTL0_CH4_NONPOSTED_LASTWRITE_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH4_CTL0_CH4_NONPOSTED_LASTWRITE_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x40000000) >> 30 +} + +// DMAC.CH4_CTL1: NA +func (o *DMAC_Type) SetCH4_CTL1_CH4_AR_PROT(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x7)|value) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_AR_PROT() uint32 { + return volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x7 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_AW_PROT(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x38)|value<<3) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_AW_PROT() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x38) >> 3 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_ARLEN_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_ARLEN_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_ARLEN(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x7f80)|value<<7) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_ARLEN() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x7f80) >> 7 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_AWLEN_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x8000)|value<<15) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_AWLEN_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x8000) >> 15 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_AWLEN(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0xff0000)|value<<16) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_AWLEN() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0xff0000) >> 16 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_SRC_STAT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_SRC_STAT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x1000000) >> 24 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_DST_STAT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_DST_STAT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_IOC_BLKTFR(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_IOC_BLKTFR() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x4000000) >> 26 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_SHADOWREG_OR_LLI_LAST(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_SHADOWREG_OR_LLI_LAST() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH4_CTL1_CH4_SHADOWREG_OR_LLI_VALID(value uint32) { + volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH4_CTL1_CH4_SHADOWREG_OR_LLI_VALID() uint32 { + return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH4_CFG0: NA +func (o *DMAC_Type) SetCH4_CFG0_CH4_SRC_MULTBLK_TYPE(value uint32) { + volatile.StoreUint32(&o.CH4_CFG0.Reg, volatile.LoadUint32(&o.CH4_CFG0.Reg)&^(0x3)|value) +} +func (o *DMAC_Type) GetCH4_CFG0_CH4_SRC_MULTBLK_TYPE() uint32 { + return volatile.LoadUint32(&o.CH4_CFG0.Reg) & 0x3 +} +func (o *DMAC_Type) SetCH4_CFG0_CH4_DST_MULTBLK_TYPE(value uint32) { + volatile.StoreUint32(&o.CH4_CFG0.Reg, volatile.LoadUint32(&o.CH4_CFG0.Reg)&^(0xc)|value<<2) +} +func (o *DMAC_Type) GetCH4_CFG0_CH4_DST_MULTBLK_TYPE() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG0.Reg) & 0xc) >> 2 +} +func (o *DMAC_Type) SetCH4_CFG0_CH4_RD_UID(value uint32) { + volatile.StoreUint32(&o.CH4_CFG0.Reg, volatile.LoadUint32(&o.CH4_CFG0.Reg)&^(0x3c0000)|value<<18) +} +func (o *DMAC_Type) GetCH4_CFG0_CH4_RD_UID() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG0.Reg) & 0x3c0000) >> 18 +} +func (o *DMAC_Type) SetCH4_CFG0_CH4_WR_UID(value uint32) { + volatile.StoreUint32(&o.CH4_CFG0.Reg, volatile.LoadUint32(&o.CH4_CFG0.Reg)&^(0x1e000000)|value<<25) +} +func (o *DMAC_Type) GetCH4_CFG0_CH4_WR_UID() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG0.Reg) & 0x1e000000) >> 25 +} + +// DMAC.CH4_CFG1: NA +func (o *DMAC_Type) SetCH4_CFG1_CH4_TT_FC(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x7)|value) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_TT_FC() uint32 { + return volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x7 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_HS_SEL_SRC(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_HS_SEL_SRC() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_HS_SEL_DST(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_HS_SEL_DST() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_SRC_HWHS_POL(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_SRC_HWHS_POL() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_DST_HWHS_POL(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_DST_HWHS_POL() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_SRC_PER(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x180)|value<<7) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_SRC_PER() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x180) >> 7 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_DST_PER(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x3000)|value<<12) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_DST_PER() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x3000) >> 12 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_CH_PRIOR(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0xe0000)|value<<17) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_CH_PRIOR() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0xe0000) >> 17 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_LOCK_CH(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_LOCK_CH() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_LOCK_CH_L(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x600000)|value<<21) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_LOCK_CH_L() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x600000) >> 21 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_SRC_OSR_LMT(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x7800000)|value<<23) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_SRC_OSR_LMT() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x7800000) >> 23 +} +func (o *DMAC_Type) SetCH4_CFG1_CH4_DST_OSR_LMT(value uint32) { + volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x78000000)|value<<27) +} +func (o *DMAC_Type) GetCH4_CFG1_CH4_DST_OSR_LMT() uint32 { + return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x78000000) >> 27 +} + +// DMAC.CH4_LLP0: NA +func (o *DMAC_Type) SetCH4_LLP0_CH4_LMS(value uint32) { + volatile.StoreUint32(&o.CH4_LLP0.Reg, volatile.LoadUint32(&o.CH4_LLP0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_LLP0_CH4_LMS() uint32 { + return volatile.LoadUint32(&o.CH4_LLP0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_LLP0_CH4_LOC0(value uint32) { + volatile.StoreUint32(&o.CH4_LLP0.Reg, volatile.LoadUint32(&o.CH4_LLP0.Reg)&^(0xffffffc0)|value<<6) +} +func (o *DMAC_Type) GetCH4_LLP0_CH4_LOC0() uint32 { + return (volatile.LoadUint32(&o.CH4_LLP0.Reg) & 0xffffffc0) >> 6 +} + +// DMAC.CH4_LLP1: NA +func (o *DMAC_Type) SetCH4_LLP1(value uint32) { + volatile.StoreUint32(&o.CH4_LLP1.Reg, value) +} +func (o *DMAC_Type) GetCH4_LLP1() uint32 { + return volatile.LoadUint32(&o.CH4_LLP1.Reg) +} + +// DMAC.CH4_STATUS0: NA +func (o *DMAC_Type) SetCH4_STATUS0_CH4_CMPLTD_BLK_TFR_SIZE(value uint32) { + volatile.StoreUint32(&o.CH4_STATUS0.Reg, volatile.LoadUint32(&o.CH4_STATUS0.Reg)&^(0x3fffff)|value) +} +func (o *DMAC_Type) GetCH4_STATUS0_CH4_CMPLTD_BLK_TFR_SIZE() uint32 { + return volatile.LoadUint32(&o.CH4_STATUS0.Reg) & 0x3fffff +} + +// DMAC.CH4_STATUS1: NA +func (o *DMAC_Type) SetCH4_STATUS1_CH4_DATA_LEFT_IN_FIFO(value uint32) { + volatile.StoreUint32(&o.CH4_STATUS1.Reg, volatile.LoadUint32(&o.CH4_STATUS1.Reg)&^(0x7fff)|value) +} +func (o *DMAC_Type) GetCH4_STATUS1_CH4_DATA_LEFT_IN_FIFO() uint32 { + return volatile.LoadUint32(&o.CH4_STATUS1.Reg) & 0x7fff +} + +// DMAC.CH4_SWHSSRC0: NA +func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_REQ_SRC(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_REQ_SRC() uint32 { + return volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_REQ_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_REQ_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_LST_SRC(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_LST_SRC() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_LST_SRC_WE(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_LST_SRC_WE() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x20) >> 5 +} + +// DMAC.CH4_SWHSDST0: NA +func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_REQ_DST(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_REQ_DST() uint32 { + return volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_REQ_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_REQ_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_SGLREQ_DST(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_SGLREQ_DST() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_SGLREQ_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_SGLREQ_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_LST_DST(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_LST_DST() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_LST_DST_WE(value uint32) { + volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_LST_DST_WE() uint32 { + return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x20) >> 5 +} + +// DMAC.CH4_BLK_TFR_RESUMEREQ0: NA +func (o *DMAC_Type) SetCH4_BLK_TFR_RESUMEREQ0_CH4_BLK_TFR_RESUMEREQ(value uint32) { + volatile.StoreUint32(&o.CH4_BLK_TFR_RESUMEREQ0.Reg, volatile.LoadUint32(&o.CH4_BLK_TFR_RESUMEREQ0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_BLK_TFR_RESUMEREQ0_CH4_BLK_TFR_RESUMEREQ() uint32 { + return volatile.LoadUint32(&o.CH4_BLK_TFR_RESUMEREQ0.Reg) & 0x1 +} + +// DMAC.CH4_AXI_ID0: NA +func (o *DMAC_Type) SetCH4_AXI_ID0_CH4_AXI_READ_ID_SUFFIX(value uint32) { + volatile.StoreUint32(&o.CH4_AXI_ID0.Reg, volatile.LoadUint32(&o.CH4_AXI_ID0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_AXI_ID0_CH4_AXI_READ_ID_SUFFIX() uint32 { + return volatile.LoadUint32(&o.CH4_AXI_ID0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_AXI_ID0_CH4_AXI_WRITE_ID_SUFFIX(value uint32) { + volatile.StoreUint32(&o.CH4_AXI_ID0.Reg, volatile.LoadUint32(&o.CH4_AXI_ID0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH4_AXI_ID0_CH4_AXI_WRITE_ID_SUFFIX() uint32 { + return (volatile.LoadUint32(&o.CH4_AXI_ID0.Reg) & 0x10000) >> 16 +} + +// DMAC.CH4_AXI_QOS0: NA +func (o *DMAC_Type) SetCH4_AXI_QOS0_CH4_AXI_AWQOS(value uint32) { + volatile.StoreUint32(&o.CH4_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH4_AXI_QOS0.Reg)&^(0xf)|value) +} +func (o *DMAC_Type) GetCH4_AXI_QOS0_CH4_AXI_AWQOS() uint32 { + return volatile.LoadUint32(&o.CH4_AXI_QOS0.Reg) & 0xf +} +func (o *DMAC_Type) SetCH4_AXI_QOS0_CH4_AXI_ARQOS(value uint32) { + volatile.StoreUint32(&o.CH4_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH4_AXI_QOS0.Reg)&^(0xf0)|value<<4) +} +func (o *DMAC_Type) GetCH4_AXI_QOS0_CH4_AXI_ARQOS() uint32 { + return (volatile.LoadUint32(&o.CH4_AXI_QOS0.Reg) & 0xf0) >> 4 +} + +// DMAC.CH4_SSTAT0: NA +func (o *DMAC_Type) SetCH4_SSTAT0(value uint32) { + volatile.StoreUint32(&o.CH4_SSTAT0.Reg, value) +} +func (o *DMAC_Type) GetCH4_SSTAT0() uint32 { + return volatile.LoadUint32(&o.CH4_SSTAT0.Reg) +} + +// DMAC.CH4_DSTAT0: NA +func (o *DMAC_Type) SetCH4_DSTAT0(value uint32) { + volatile.StoreUint32(&o.CH4_DSTAT0.Reg, value) +} +func (o *DMAC_Type) GetCH4_DSTAT0() uint32 { + return volatile.LoadUint32(&o.CH4_DSTAT0.Reg) +} + +// DMAC.CH4_SSTATAR0: NA +func (o *DMAC_Type) SetCH4_SSTATAR0(value uint32) { + volatile.StoreUint32(&o.CH4_SSTATAR0.Reg, value) +} +func (o *DMAC_Type) GetCH4_SSTATAR0() uint32 { + return volatile.LoadUint32(&o.CH4_SSTATAR0.Reg) +} + +// DMAC.CH4_SSTATAR1: NA +func (o *DMAC_Type) SetCH4_SSTATAR1(value uint32) { + volatile.StoreUint32(&o.CH4_SSTATAR1.Reg, value) +} +func (o *DMAC_Type) GetCH4_SSTATAR1() uint32 { + return volatile.LoadUint32(&o.CH4_SSTATAR1.Reg) +} + +// DMAC.CH4_DSTATAR0: NA +func (o *DMAC_Type) SetCH4_DSTATAR0(value uint32) { + volatile.StoreUint32(&o.CH4_DSTATAR0.Reg, value) +} +func (o *DMAC_Type) GetCH4_DSTATAR0() uint32 { + return volatile.LoadUint32(&o.CH4_DSTATAR0.Reg) +} + +// DMAC.CH4_DSTATAR1: NA +func (o *DMAC_Type) SetCH4_DSTATAR1(value uint32) { + volatile.StoreUint32(&o.CH4_DSTATAR1.Reg, value) +} +func (o *DMAC_Type) GetCH4_DSTATAR1() uint32 { + return volatile.LoadUint32(&o.CH4_DSTATAR1.Reg) +} + +// DMAC.CH4_INTSTATUS_ENABLE0: NA +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH4_INTSTATUS_ENABLE1: NA +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg) & 0x8) >> 3 +} + +// DMAC.CH4_INTSTATUS0: NA +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH4_INTSTATUS1: NA +func (o *DMAC_Type) SetCH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg) & 0x8) >> 3 +} + +// DMAC.CH4_INTSIGNAL_ENABLE0: NA +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL() uint32 { + return volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH4_INTSIGNAL_ENABLE1: NA +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL() uint32 { + return volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL(value uint32) { + volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL() uint32 { + return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg) & 0x8) >> 3 +} + +// DMAC.CH4_INTCLEAR0: NA +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_DMA_TFR_DONE_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_DMA_TFR_DONE_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x8) >> 3 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_DST_TRANSCOMP_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x10)|value<<4) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_DST_TRANSCOMP_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x10) >> 4 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SRC_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x20)|value<<5) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SRC_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x20) >> 5 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_DST_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x40)|value<<6) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_DST_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x40) >> 6 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SRC_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x80)|value<<7) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SRC_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x80) >> 7 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_DST_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x100)|value<<8) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_DST_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x100) >> 8 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x200)|value<<9) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x200) >> 9 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x400)|value<<10) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x400) >> 10 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x800)|value<<11) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x800) >> 11 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x1000)|value<<12) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x1000) >> 12 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x2000)|value<<13) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x2000) >> 13 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x4000)|value<<14) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x4000) >> 14 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x10000)|value<<16) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x10000) >> 16 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x20000)|value<<17) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x20000) >> 17 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x40000)|value<<18) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x40000) >> 18 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x80000)|value<<19) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x80000) >> 19 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x100000)|value<<20) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x100000) >> 20 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x200000)|value<<21) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x200000) >> 21 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x2000000) >> 25 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x8000000) >> 27 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x10000000) >> 28 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_SUSPENDED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x20000000)|value<<29) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_SUSPENDED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x20000000) >> 29 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_DISABLED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x40000000)|value<<30) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_DISABLED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x40000000) >> 30 +} +func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_ABORTED_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x80000000)|value<<31) +} +func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_ABORTED_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x80000000) >> 31 +} + +// DMAC.CH4_INTCLEAR1: NA +func (o *DMAC_Type) SetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg)&^(0x1)|value) +} +func (o *DMAC_Type) GetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 { + return volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg) & 0x1 +} +func (o *DMAC_Type) SetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg)&^(0x2)|value<<1) +} +func (o *DMAC_Type) GetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg) & 0x2) >> 1 +} +func (o *DMAC_Type) SetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg)&^(0x4)|value<<2) +} +func (o *DMAC_Type) GetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg) & 0x4) >> 2 +} +func (o *DMAC_Type) SetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) { + volatile.StoreUint32(&o.CH4_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg)&^(0x8)|value<<3) +} +func (o *DMAC_Type) GetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 { + return (volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg) & 0x8) >> 3 +} + +// Digital Signature +type DS_Type struct { + Y_MEM [128]volatile.Register32 // 0x0 + M_MEM [128]volatile.Register32 // 0x200 + RB_MEM [128]volatile.Register32 // 0x400 + BOX_MEM [12]volatile.Register32 // 0x600 + IV_MEM [4]volatile.Register32 // 0x630 + _ [448]byte + X_MEM [128]volatile.Register32 // 0x800 + Z_MEM [128]volatile.Register32 // 0xA00 + _ [512]byte + SET_START volatile.Register32 // 0xE00 + SET_CONTINUE volatile.Register32 // 0xE04 + SET_FINISH volatile.Register32 // 0xE08 + QUERY_BUSY volatile.Register32 // 0xE0C + QUERY_KEY_WRONG volatile.Register32 // 0xE10 + QUERY_CHECK volatile.Register32 // 0xE14 + _ [8]byte + DATE volatile.Register32 // 0xE20 +} + +// DS.SET_START: DS start control register +func (o *DS_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// DS.SET_CONTINUE: DS continue control register +func (o *DS_Type) SetSET_CONTINUE(value uint32) { + volatile.StoreUint32(&o.SET_CONTINUE.Reg, volatile.LoadUint32(&o.SET_CONTINUE.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_CONTINUE() uint32 { + return volatile.LoadUint32(&o.SET_CONTINUE.Reg) & 0x1 +} + +// DS.SET_FINISH: DS finish control register +func (o *DS_Type) SetSET_FINISH(value uint32) { + volatile.StoreUint32(&o.SET_FINISH.Reg, volatile.LoadUint32(&o.SET_FINISH.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_FINISH() uint32 { + return volatile.LoadUint32(&o.SET_FINISH.Reg) & 0x1 +} + +// DS.QUERY_BUSY: DS query busy register +func (o *DS_Type) SetQUERY_BUSY(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_BUSY() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// DS.QUERY_KEY_WRONG: DS query key-wrong counter register +func (o *DS_Type) SetQUERY_KEY_WRONG(value uint32) { + volatile.StoreUint32(&o.QUERY_KEY_WRONG.Reg, volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg)&^(0xf)|value) +} +func (o *DS_Type) GetQUERY_KEY_WRONG() uint32 { + return volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg) & 0xf +} + +// DS.QUERY_CHECK: DS query check result register +func (o *DS_Type) SetQUERY_CHECK_MD_ERROR(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_CHECK_MD_ERROR() uint32 { + return volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x1 +} +func (o *DS_Type) SetQUERY_CHECK_PADDING_BAD(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x2)|value<<1) +} +func (o *DS_Type) GetQUERY_CHECK_PADDING_BAD() uint32 { + return (volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x2) >> 1 +} + +// DS.DATE: DS version control register +func (o *DS_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *DS_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// MIPI Camera Interface Bridge +type DSI_BRG_Type struct { + CLK_EN volatile.Register32 // 0x0 + EN volatile.Register32 // 0x4 + DMA_REQ_CFG volatile.Register32 // 0x8 + RAW_NUM_CFG volatile.Register32 // 0xC + RAW_BUF_CREDIT_CTL volatile.Register32 // 0x10 + FIFO_FLOW_STATUS volatile.Register32 // 0x14 + PIXEL_TYPE volatile.Register32 // 0x18 + DMA_BLOCK_INTERVAL volatile.Register32 // 0x1C + DMA_REQ_INTERVAL volatile.Register32 // 0x20 + DPI_LCD_CTL volatile.Register32 // 0x24 + DPI_RSV_DPI_DATA volatile.Register32 // 0x28 + _ [4]byte + DPI_V_CFG0 volatile.Register32 // 0x30 + DPI_V_CFG1 volatile.Register32 // 0x34 + DPI_H_CFG0 volatile.Register32 // 0x38 + DPI_H_CFG1 volatile.Register32 // 0x3C + DPI_MISC_CONFIG volatile.Register32 // 0x40 + DPI_CONFIG_UPDATE volatile.Register32 // 0x44 + _ [8]byte + INT_ENA volatile.Register32 // 0x50 + INT_CLR volatile.Register32 // 0x54 + INT_RAW volatile.Register32 // 0x58 + INT_ST volatile.Register32 // 0x5C + HOST_BIST_CTL volatile.Register32 // 0x60 + HOST_TRIGGER_REV volatile.Register32 // 0x64 + BLK_RAW_NUM_CFG volatile.Register32 // 0x68 + DMA_FRAME_INTERVAL volatile.Register32 // 0x6C + MEM_AUX_CTRL volatile.Register32 // 0x70 + RDN_ECO_CS volatile.Register32 // 0x74 + RDN_ECO_LOW volatile.Register32 // 0x78 + RDN_ECO_HIGH volatile.Register32 // 0x7C + HOST_CTRL volatile.Register32 // 0x80 + MEM_CLK_CTRL volatile.Register32 // 0x84 + DMA_FLOW_CTRL volatile.Register32 // 0x88 + RAW_BUF_ALMOST_EMPTY_THRD volatile.Register32 // 0x8C + YUV_CFG volatile.Register32 // 0x90 + PHY_LP_LOOPBACK_CTRL volatile.Register32 // 0x94 + PHY_HS_LOOPBACK_CTRL volatile.Register32 // 0x98 + PHY_LOOPBACK_CNT volatile.Register32 // 0x9C +} + +// DSI_BRG.CLK_EN: dsi bridge clk control register +func (o *DSI_BRG_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1 +} + +// DSI_BRG.EN: dsi bridge en register +func (o *DSI_BRG_Type) SetEN_DSI_EN(value uint32) { + volatile.StoreUint32(&o.EN.Reg, volatile.LoadUint32(&o.EN.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetEN_DSI_EN() uint32 { + return volatile.LoadUint32(&o.EN.Reg) & 0x1 +} + +// DSI_BRG.DMA_REQ_CFG: dsi bridge dma burst len register +func (o *DSI_BRG_Type) SetDMA_REQ_CFG_DMA_BURST_LEN(value uint32) { + volatile.StoreUint32(&o.DMA_REQ_CFG.Reg, volatile.LoadUint32(&o.DMA_REQ_CFG.Reg)&^(0xfff)|value) +} +func (o *DSI_BRG_Type) GetDMA_REQ_CFG_DMA_BURST_LEN() uint32 { + return volatile.LoadUint32(&o.DMA_REQ_CFG.Reg) & 0xfff +} + +// DSI_BRG.RAW_NUM_CFG: dsi bridge raw number control register +func (o *DSI_BRG_Type) SetRAW_NUM_CFG_RAW_NUM_TOTAL(value uint32) { + volatile.StoreUint32(&o.RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.RAW_NUM_CFG.Reg)&^(0x3fffff)|value) +} +func (o *DSI_BRG_Type) GetRAW_NUM_CFG_RAW_NUM_TOTAL() uint32 { + return volatile.LoadUint32(&o.RAW_NUM_CFG.Reg) & 0x3fffff +} +func (o *DSI_BRG_Type) SetRAW_NUM_CFG_UNALIGN_64BIT_EN(value uint32) { + volatile.StoreUint32(&o.RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.RAW_NUM_CFG.Reg)&^(0x400000)|value<<22) +} +func (o *DSI_BRG_Type) GetRAW_NUM_CFG_UNALIGN_64BIT_EN() uint32 { + return (volatile.LoadUint32(&o.RAW_NUM_CFG.Reg) & 0x400000) >> 22 +} +func (o *DSI_BRG_Type) SetRAW_NUM_CFG_RAW_NUM_TOTAL_SET(value uint32) { + volatile.StoreUint32(&o.RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.RAW_NUM_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *DSI_BRG_Type) GetRAW_NUM_CFG_RAW_NUM_TOTAL_SET() uint32 { + return (volatile.LoadUint32(&o.RAW_NUM_CFG.Reg) & 0x80000000) >> 31 +} + +// DSI_BRG.RAW_BUF_CREDIT_CTL: dsi bridge credit register +func (o *DSI_BRG_Type) SetRAW_BUF_CREDIT_CTL_CREDIT_THRD(value uint32) { + volatile.StoreUint32(&o.RAW_BUF_CREDIT_CTL.Reg, volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg)&^(0x7fff)|value) +} +func (o *DSI_BRG_Type) GetRAW_BUF_CREDIT_CTL_CREDIT_THRD() uint32 { + return volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg) & 0x7fff +} +func (o *DSI_BRG_Type) SetRAW_BUF_CREDIT_CTL_CREDIT_BURST_THRD(value uint32) { + volatile.StoreUint32(&o.RAW_BUF_CREDIT_CTL.Reg, volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg)&^(0x7fff0000)|value<<16) +} +func (o *DSI_BRG_Type) GetRAW_BUF_CREDIT_CTL_CREDIT_BURST_THRD() uint32 { + return (volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg) & 0x7fff0000) >> 16 +} +func (o *DSI_BRG_Type) SetRAW_BUF_CREDIT_CTL_CREDIT_RESET(value uint32) { + volatile.StoreUint32(&o.RAW_BUF_CREDIT_CTL.Reg, volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg)&^(0x80000000)|value<<31) +} +func (o *DSI_BRG_Type) GetRAW_BUF_CREDIT_CTL_CREDIT_RESET() uint32 { + return (volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg) & 0x80000000) >> 31 +} + +// DSI_BRG.FIFO_FLOW_STATUS: dsi bridge raw buffer depth register +func (o *DSI_BRG_Type) SetFIFO_FLOW_STATUS_RAW_BUF_DEPTH(value uint32) { + volatile.StoreUint32(&o.FIFO_FLOW_STATUS.Reg, volatile.LoadUint32(&o.FIFO_FLOW_STATUS.Reg)&^(0x3fff)|value) +} +func (o *DSI_BRG_Type) GetFIFO_FLOW_STATUS_RAW_BUF_DEPTH() uint32 { + return volatile.LoadUint32(&o.FIFO_FLOW_STATUS.Reg) & 0x3fff +} + +// DSI_BRG.PIXEL_TYPE: dsi bridge dpi type control register +func (o *DSI_BRG_Type) SetPIXEL_TYPE_RAW_TYPE(value uint32) { + volatile.StoreUint32(&o.PIXEL_TYPE.Reg, volatile.LoadUint32(&o.PIXEL_TYPE.Reg)&^(0xf)|value) +} +func (o *DSI_BRG_Type) GetPIXEL_TYPE_RAW_TYPE() uint32 { + return volatile.LoadUint32(&o.PIXEL_TYPE.Reg) & 0xf +} +func (o *DSI_BRG_Type) SetPIXEL_TYPE_DPI_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIXEL_TYPE.Reg, volatile.LoadUint32(&o.PIXEL_TYPE.Reg)&^(0x30)|value<<4) +} +func (o *DSI_BRG_Type) GetPIXEL_TYPE_DPI_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIXEL_TYPE.Reg) & 0x30) >> 4 +} +func (o *DSI_BRG_Type) SetPIXEL_TYPE_DATA_IN_TYPE(value uint32) { + volatile.StoreUint32(&o.PIXEL_TYPE.Reg, volatile.LoadUint32(&o.PIXEL_TYPE.Reg)&^(0x40)|value<<6) +} +func (o *DSI_BRG_Type) GetPIXEL_TYPE_DATA_IN_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIXEL_TYPE.Reg) & 0x40) >> 6 +} + +// DSI_BRG.DMA_BLOCK_INTERVAL: dsi bridge dma block interval control register +func (o *DSI_BRG_Type) SetDMA_BLOCK_INTERVAL_DMA_BLOCK_SLOT(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg)&^(0x3ff)|value) +} +func (o *DSI_BRG_Type) GetDMA_BLOCK_INTERVAL_DMA_BLOCK_SLOT() uint32 { + return volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg) & 0x3ff +} +func (o *DSI_BRG_Type) SetDMA_BLOCK_INTERVAL(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg)&^(0xffffc00)|value<<10) +} +func (o *DSI_BRG_Type) GetDMA_BLOCK_INTERVAL() uint32 { + return (volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg) & 0xffffc00) >> 10 +} +func (o *DSI_BRG_Type) SetDMA_BLOCK_INTERVAL_RAW_NUM_TOTAL_AUTO_RELOAD(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg)&^(0x10000000)|value<<28) +} +func (o *DSI_BRG_Type) GetDMA_BLOCK_INTERVAL_RAW_NUM_TOTAL_AUTO_RELOAD() uint32 { + return (volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg) & 0x10000000) >> 28 +} +func (o *DSI_BRG_Type) SetDMA_BLOCK_INTERVAL_EN(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg)&^(0x20000000)|value<<29) +} +func (o *DSI_BRG_Type) GetDMA_BLOCK_INTERVAL_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg) & 0x20000000) >> 29 +} + +// DSI_BRG.DMA_REQ_INTERVAL: dsi bridge dma req interval control register +func (o *DSI_BRG_Type) SetDMA_REQ_INTERVAL(value uint32) { + volatile.StoreUint32(&o.DMA_REQ_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_REQ_INTERVAL.Reg)&^(0xffff)|value) +} +func (o *DSI_BRG_Type) GetDMA_REQ_INTERVAL() uint32 { + return volatile.LoadUint32(&o.DMA_REQ_INTERVAL.Reg) & 0xffff +} + +// DSI_BRG.DPI_LCD_CTL: dsi bridge dpi signal control register +func (o *DSI_BRG_Type) SetDPI_LCD_CTL_DPISHUTDN(value uint32) { + volatile.StoreUint32(&o.DPI_LCD_CTL.Reg, volatile.LoadUint32(&o.DPI_LCD_CTL.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetDPI_LCD_CTL_DPISHUTDN() uint32 { + return volatile.LoadUint32(&o.DPI_LCD_CTL.Reg) & 0x1 +} +func (o *DSI_BRG_Type) SetDPI_LCD_CTL_DPICOLORM(value uint32) { + volatile.StoreUint32(&o.DPI_LCD_CTL.Reg, volatile.LoadUint32(&o.DPI_LCD_CTL.Reg)&^(0x2)|value<<1) +} +func (o *DSI_BRG_Type) GetDPI_LCD_CTL_DPICOLORM() uint32 { + return (volatile.LoadUint32(&o.DPI_LCD_CTL.Reg) & 0x2) >> 1 +} +func (o *DSI_BRG_Type) SetDPI_LCD_CTL_DPIUPDATECFG(value uint32) { + volatile.StoreUint32(&o.DPI_LCD_CTL.Reg, volatile.LoadUint32(&o.DPI_LCD_CTL.Reg)&^(0x4)|value<<2) +} +func (o *DSI_BRG_Type) GetDPI_LCD_CTL_DPIUPDATECFG() uint32 { + return (volatile.LoadUint32(&o.DPI_LCD_CTL.Reg) & 0x4) >> 2 +} + +// DSI_BRG.DPI_RSV_DPI_DATA: dsi bridge dpi reserved data register +func (o *DSI_BRG_Type) SetDPI_RSV_DPI_DATA_DPI_RSV_DATA(value uint32) { + volatile.StoreUint32(&o.DPI_RSV_DPI_DATA.Reg, volatile.LoadUint32(&o.DPI_RSV_DPI_DATA.Reg)&^(0x3fffffff)|value) +} +func (o *DSI_BRG_Type) GetDPI_RSV_DPI_DATA_DPI_RSV_DATA() uint32 { + return volatile.LoadUint32(&o.DPI_RSV_DPI_DATA.Reg) & 0x3fffffff +} + +// DSI_BRG.DPI_V_CFG0: dsi bridge dpi v config register 0 +func (o *DSI_BRG_Type) SetDPI_V_CFG0_VTOTAL(value uint32) { + volatile.StoreUint32(&o.DPI_V_CFG0.Reg, volatile.LoadUint32(&o.DPI_V_CFG0.Reg)&^(0xfff)|value) +} +func (o *DSI_BRG_Type) GetDPI_V_CFG0_VTOTAL() uint32 { + return volatile.LoadUint32(&o.DPI_V_CFG0.Reg) & 0xfff +} +func (o *DSI_BRG_Type) SetDPI_V_CFG0_VDISP(value uint32) { + volatile.StoreUint32(&o.DPI_V_CFG0.Reg, volatile.LoadUint32(&o.DPI_V_CFG0.Reg)&^(0xfff0000)|value<<16) +} +func (o *DSI_BRG_Type) GetDPI_V_CFG0_VDISP() uint32 { + return (volatile.LoadUint32(&o.DPI_V_CFG0.Reg) & 0xfff0000) >> 16 +} + +// DSI_BRG.DPI_V_CFG1: dsi bridge dpi v config register 1 +func (o *DSI_BRG_Type) SetDPI_V_CFG1_VBANK(value uint32) { + volatile.StoreUint32(&o.DPI_V_CFG1.Reg, volatile.LoadUint32(&o.DPI_V_CFG1.Reg)&^(0xfff)|value) +} +func (o *DSI_BRG_Type) GetDPI_V_CFG1_VBANK() uint32 { + return volatile.LoadUint32(&o.DPI_V_CFG1.Reg) & 0xfff +} +func (o *DSI_BRG_Type) SetDPI_V_CFG1_VSYNC(value uint32) { + volatile.StoreUint32(&o.DPI_V_CFG1.Reg, volatile.LoadUint32(&o.DPI_V_CFG1.Reg)&^(0xfff0000)|value<<16) +} +func (o *DSI_BRG_Type) GetDPI_V_CFG1_VSYNC() uint32 { + return (volatile.LoadUint32(&o.DPI_V_CFG1.Reg) & 0xfff0000) >> 16 +} + +// DSI_BRG.DPI_H_CFG0: dsi bridge dpi h config register 0 +func (o *DSI_BRG_Type) SetDPI_H_CFG0_HTOTAL(value uint32) { + volatile.StoreUint32(&o.DPI_H_CFG0.Reg, volatile.LoadUint32(&o.DPI_H_CFG0.Reg)&^(0xfff)|value) +} +func (o *DSI_BRG_Type) GetDPI_H_CFG0_HTOTAL() uint32 { + return volatile.LoadUint32(&o.DPI_H_CFG0.Reg) & 0xfff +} +func (o *DSI_BRG_Type) SetDPI_H_CFG0_HDISP(value uint32) { + volatile.StoreUint32(&o.DPI_H_CFG0.Reg, volatile.LoadUint32(&o.DPI_H_CFG0.Reg)&^(0xfff0000)|value<<16) +} +func (o *DSI_BRG_Type) GetDPI_H_CFG0_HDISP() uint32 { + return (volatile.LoadUint32(&o.DPI_H_CFG0.Reg) & 0xfff0000) >> 16 +} + +// DSI_BRG.DPI_H_CFG1: dsi bridge dpi h config register 1 +func (o *DSI_BRG_Type) SetDPI_H_CFG1_HBANK(value uint32) { + volatile.StoreUint32(&o.DPI_H_CFG1.Reg, volatile.LoadUint32(&o.DPI_H_CFG1.Reg)&^(0xfff)|value) +} +func (o *DSI_BRG_Type) GetDPI_H_CFG1_HBANK() uint32 { + return volatile.LoadUint32(&o.DPI_H_CFG1.Reg) & 0xfff +} +func (o *DSI_BRG_Type) SetDPI_H_CFG1_HSYNC(value uint32) { + volatile.StoreUint32(&o.DPI_H_CFG1.Reg, volatile.LoadUint32(&o.DPI_H_CFG1.Reg)&^(0xfff0000)|value<<16) +} +func (o *DSI_BRG_Type) GetDPI_H_CFG1_HSYNC() uint32 { + return (volatile.LoadUint32(&o.DPI_H_CFG1.Reg) & 0xfff0000) >> 16 +} + +// DSI_BRG.DPI_MISC_CONFIG: dsi_bridge dpi misc config register +func (o *DSI_BRG_Type) SetDPI_MISC_CONFIG_DPI_EN(value uint32) { + volatile.StoreUint32(&o.DPI_MISC_CONFIG.Reg, volatile.LoadUint32(&o.DPI_MISC_CONFIG.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetDPI_MISC_CONFIG_DPI_EN() uint32 { + return volatile.LoadUint32(&o.DPI_MISC_CONFIG.Reg) & 0x1 +} +func (o *DSI_BRG_Type) SetDPI_MISC_CONFIG_FIFO_UNDERRUN_DISCARD_VCNT(value uint32) { + volatile.StoreUint32(&o.DPI_MISC_CONFIG.Reg, volatile.LoadUint32(&o.DPI_MISC_CONFIG.Reg)&^(0xfff0)|value<<4) +} +func (o *DSI_BRG_Type) GetDPI_MISC_CONFIG_FIFO_UNDERRUN_DISCARD_VCNT() uint32 { + return (volatile.LoadUint32(&o.DPI_MISC_CONFIG.Reg) & 0xfff0) >> 4 +} + +// DSI_BRG.DPI_CONFIG_UPDATE: dsi_bridge dpi config update register +func (o *DSI_BRG_Type) SetDPI_CONFIG_UPDATE(value uint32) { + volatile.StoreUint32(&o.DPI_CONFIG_UPDATE.Reg, volatile.LoadUint32(&o.DPI_CONFIG_UPDATE.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetDPI_CONFIG_UPDATE() uint32 { + return volatile.LoadUint32(&o.DPI_CONFIG_UPDATE.Reg) & 0x1 +} + +// DSI_BRG.INT_ENA: dsi_bridge interrupt enable register +func (o *DSI_BRG_Type) SetINT_ENA_UNDERRUN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetINT_ENA_UNDERRUN_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// DSI_BRG.INT_CLR: dsi_bridge interrupt clear register +func (o *DSI_BRG_Type) SetINT_CLR_UNDERRUN_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetINT_CLR_UNDERRUN_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} + +// DSI_BRG.INT_RAW: dsi_bridge raw interrupt register +func (o *DSI_BRG_Type) SetINT_RAW_UNDERRUN_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetINT_RAW_UNDERRUN_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} + +// DSI_BRG.INT_ST: dsi_bridge masked interrupt register +func (o *DSI_BRG_Type) SetINT_ST_UNDERRUN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetINT_ST_UNDERRUN_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} + +// DSI_BRG.HOST_BIST_CTL: dsi_bridge host bist control register +func (o *DSI_BRG_Type) SetHOST_BIST_CTL_BISTOK(value uint32) { + volatile.StoreUint32(&o.HOST_BIST_CTL.Reg, volatile.LoadUint32(&o.HOST_BIST_CTL.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetHOST_BIST_CTL_BISTOK() uint32 { + return volatile.LoadUint32(&o.HOST_BIST_CTL.Reg) & 0x1 +} +func (o *DSI_BRG_Type) SetHOST_BIST_CTL_BISTON(value uint32) { + volatile.StoreUint32(&o.HOST_BIST_CTL.Reg, volatile.LoadUint32(&o.HOST_BIST_CTL.Reg)&^(0x2)|value<<1) +} +func (o *DSI_BRG_Type) GetHOST_BIST_CTL_BISTON() uint32 { + return (volatile.LoadUint32(&o.HOST_BIST_CTL.Reg) & 0x2) >> 1 +} + +// DSI_BRG.HOST_TRIGGER_REV: dsi_bridge host trigger reverse control register +func (o *DSI_BRG_Type) SetHOST_TRIGGER_REV_TX_TRIGGER_REV_EN(value uint32) { + volatile.StoreUint32(&o.HOST_TRIGGER_REV.Reg, volatile.LoadUint32(&o.HOST_TRIGGER_REV.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetHOST_TRIGGER_REV_TX_TRIGGER_REV_EN() uint32 { + return volatile.LoadUint32(&o.HOST_TRIGGER_REV.Reg) & 0x1 +} +func (o *DSI_BRG_Type) SetHOST_TRIGGER_REV_RX_TRIGGER_REV_EN(value uint32) { + volatile.StoreUint32(&o.HOST_TRIGGER_REV.Reg, volatile.LoadUint32(&o.HOST_TRIGGER_REV.Reg)&^(0x2)|value<<1) +} +func (o *DSI_BRG_Type) GetHOST_TRIGGER_REV_RX_TRIGGER_REV_EN() uint32 { + return (volatile.LoadUint32(&o.HOST_TRIGGER_REV.Reg) & 0x2) >> 1 +} + +// DSI_BRG.BLK_RAW_NUM_CFG: dsi_bridge block raw number control register +func (o *DSI_BRG_Type) SetBLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL(value uint32) { + volatile.StoreUint32(&o.BLK_RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.BLK_RAW_NUM_CFG.Reg)&^(0x3fffff)|value) +} +func (o *DSI_BRG_Type) GetBLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL() uint32 { + return volatile.LoadUint32(&o.BLK_RAW_NUM_CFG.Reg) & 0x3fffff +} +func (o *DSI_BRG_Type) SetBLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL_SET(value uint32) { + volatile.StoreUint32(&o.BLK_RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.BLK_RAW_NUM_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *DSI_BRG_Type) GetBLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL_SET() uint32 { + return (volatile.LoadUint32(&o.BLK_RAW_NUM_CFG.Reg) & 0x80000000) >> 31 +} + +// DSI_BRG.DMA_FRAME_INTERVAL: dsi_bridge dam frame interval control register +func (o *DSI_BRG_Type) SetDMA_FRAME_INTERVAL_DMA_FRAME_SLOT(value uint32) { + volatile.StoreUint32(&o.DMA_FRAME_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg)&^(0x3ff)|value) +} +func (o *DSI_BRG_Type) GetDMA_FRAME_INTERVAL_DMA_FRAME_SLOT() uint32 { + return volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg) & 0x3ff +} +func (o *DSI_BRG_Type) SetDMA_FRAME_INTERVAL(value uint32) { + volatile.StoreUint32(&o.DMA_FRAME_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg)&^(0xffffc00)|value<<10) +} +func (o *DSI_BRG_Type) GetDMA_FRAME_INTERVAL() uint32 { + return (volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg) & 0xffffc00) >> 10 +} +func (o *DSI_BRG_Type) SetDMA_FRAME_INTERVAL_DMA_MULTIBLK_EN(value uint32) { + volatile.StoreUint32(&o.DMA_FRAME_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg)&^(0x10000000)|value<<28) +} +func (o *DSI_BRG_Type) GetDMA_FRAME_INTERVAL_DMA_MULTIBLK_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg) & 0x10000000) >> 28 +} +func (o *DSI_BRG_Type) SetDMA_FRAME_INTERVAL_EN(value uint32) { + volatile.StoreUint32(&o.DMA_FRAME_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg)&^(0x20000000)|value<<29) +} +func (o *DSI_BRG_Type) GetDMA_FRAME_INTERVAL_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg) & 0x20000000) >> 29 +} + +// DSI_BRG.MEM_AUX_CTRL: dsi_bridge mem aux control register +func (o *DSI_BRG_Type) SetMEM_AUX_CTRL_DSI_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL.Reg)&^(0x3fff)|value) +} +func (o *DSI_BRG_Type) GetMEM_AUX_CTRL_DSI_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.MEM_AUX_CTRL.Reg) & 0x3fff +} + +// DSI_BRG.RDN_ECO_CS: dsi_bridge rdn eco cs register +func (o *DSI_BRG_Type) SetRDN_ECO_CS_RDN_ECO_EN(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetRDN_ECO_CS_RDN_ECO_EN() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x1 +} +func (o *DSI_BRG_Type) SetRDN_ECO_CS_RDN_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *DSI_BRG_Type) GetRDN_ECO_CS_RDN_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x2) >> 1 +} + +// DSI_BRG.RDN_ECO_LOW: dsi_bridge rdn eco all low register +func (o *DSI_BRG_Type) SetRDN_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_LOW.Reg, value) +} +func (o *DSI_BRG_Type) GetRDN_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_LOW.Reg) +} + +// DSI_BRG.RDN_ECO_HIGH: dsi_bridge rdn eco all high register +func (o *DSI_BRG_Type) SetRDN_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_HIGH.Reg, value) +} +func (o *DSI_BRG_Type) GetRDN_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_HIGH.Reg) +} + +// DSI_BRG.HOST_CTRL: dsi_bridge host control register +func (o *DSI_BRG_Type) SetHOST_CTRL_DSI_CFG_REF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.HOST_CTRL.Reg, volatile.LoadUint32(&o.HOST_CTRL.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetHOST_CTRL_DSI_CFG_REF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.HOST_CTRL.Reg) & 0x1 +} + +// DSI_BRG.MEM_CLK_CTRL: dsi_bridge mem force on control register +func (o *DSI_BRG_Type) SetMEM_CLK_CTRL_DSI_BRIDGE_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.MEM_CLK_CTRL.Reg, volatile.LoadUint32(&o.MEM_CLK_CTRL.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetMEM_CLK_CTRL_DSI_BRIDGE_MEM_CLK_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.MEM_CLK_CTRL.Reg) & 0x1 +} +func (o *DSI_BRG_Type) SetMEM_CLK_CTRL_DSI_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.MEM_CLK_CTRL.Reg, volatile.LoadUint32(&o.MEM_CLK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *DSI_BRG_Type) GetMEM_CLK_CTRL_DSI_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.MEM_CLK_CTRL.Reg) & 0x2) >> 1 +} + +// DSI_BRG.DMA_FLOW_CTRL: dsi_bridge dma flow controller register +func (o *DSI_BRG_Type) SetDMA_FLOW_CTRL_DSI_DMA_FLOW_CONTROLLER(value uint32) { + volatile.StoreUint32(&o.DMA_FLOW_CTRL.Reg, volatile.LoadUint32(&o.DMA_FLOW_CTRL.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetDMA_FLOW_CTRL_DSI_DMA_FLOW_CONTROLLER() uint32 { + return volatile.LoadUint32(&o.DMA_FLOW_CTRL.Reg) & 0x1 +} +func (o *DSI_BRG_Type) SetDMA_FLOW_CTRL_DMA_FLOW_MULTIBLK_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_FLOW_CTRL.Reg, volatile.LoadUint32(&o.DMA_FLOW_CTRL.Reg)&^(0xf0)|value<<4) +} +func (o *DSI_BRG_Type) GetDMA_FLOW_CTRL_DMA_FLOW_MULTIBLK_NUM() uint32 { + return (volatile.LoadUint32(&o.DMA_FLOW_CTRL.Reg) & 0xf0) >> 4 +} + +// DSI_BRG.RAW_BUF_ALMOST_EMPTY_THRD: dsi_bridge buffer empty threshold register +func (o *DSI_BRG_Type) SetRAW_BUF_ALMOST_EMPTY_THRD_DSI_RAW_BUF_ALMOST_EMPTY_THRD(value uint32) { + volatile.StoreUint32(&o.RAW_BUF_ALMOST_EMPTY_THRD.Reg, volatile.LoadUint32(&o.RAW_BUF_ALMOST_EMPTY_THRD.Reg)&^(0x7ff)|value) +} +func (o *DSI_BRG_Type) GetRAW_BUF_ALMOST_EMPTY_THRD_DSI_RAW_BUF_ALMOST_EMPTY_THRD() uint32 { + return volatile.LoadUint32(&o.RAW_BUF_ALMOST_EMPTY_THRD.Reg) & 0x7ff +} + +// DSI_BRG.YUV_CFG: dsi_bridge yuv format config register +func (o *DSI_BRG_Type) SetYUV_CFG_PROTOCAL(value uint32) { + volatile.StoreUint32(&o.YUV_CFG.Reg, volatile.LoadUint32(&o.YUV_CFG.Reg)&^(0x1)|value) +} +func (o *DSI_BRG_Type) GetYUV_CFG_PROTOCAL() uint32 { + return volatile.LoadUint32(&o.YUV_CFG.Reg) & 0x1 +} +func (o *DSI_BRG_Type) SetYUV_CFG_YUV_PIX_ENDIAN(value uint32) { + volatile.StoreUint32(&o.YUV_CFG.Reg, volatile.LoadUint32(&o.YUV_CFG.Reg)&^(0x2)|value<<1) +} +func (o *DSI_BRG_Type) GetYUV_CFG_YUV_PIX_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.YUV_CFG.Reg) & 0x2) >> 1 +} +func (o *DSI_BRG_Type) SetYUV_CFG_YUV422_FORMAT(value uint32) { + volatile.StoreUint32(&o.YUV_CFG.Reg, volatile.LoadUint32(&o.YUV_CFG.Reg)&^(0xc)|value<<2) +} +func (o *DSI_BRG_Type) GetYUV_CFG_YUV422_FORMAT() uint32 { + return (volatile.LoadUint32(&o.YUV_CFG.Reg) & 0xc) >> 2 +} + +// DSI_BRG.PHY_LP_LOOPBACK_CTRL: dsi phy lp_loopback test ctrl +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_1(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0xff)|value) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_1() uint32 { + return volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0xff +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_1(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_1() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x100) >> 8 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_1(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_1() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x200) >> 9 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_1(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_1() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x400) >> 10 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_1(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_1() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x800) >> 11 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_0(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_0() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_0(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_0() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_0(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_0() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_0(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_0() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_0(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_0() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK_DONE(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK_DONE() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_EN(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_EN() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_OK(value uint32) { + volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_OK() uint32 { + return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x80000000) >> 31 +} + +// DSI_BRG.PHY_HS_LOOPBACK_CTRL: dsi phy hp_loopback test ctrl +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_1(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0xff)|value) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_1() uint32 { + return volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0xff +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_1(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_1() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x100) >> 8 +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_1(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_1() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x200) >> 9 +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_0(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_0() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_0(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_0() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_0(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_0() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTHSCLK(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTHSCLK() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK_DONE(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK_DONE() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_EN(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_EN() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_OK(value uint32) { + volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_OK() uint32 { + return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x80000000) >> 31 +} + +// DSI_BRG.PHY_LOOPBACK_CNT: loopback test cnt +func (o *DSI_BRG_Type) SetPHY_LOOPBACK_CNT_PHY_HS_CHECK_CNT_TH(value uint32) { + volatile.StoreUint32(&o.PHY_LOOPBACK_CNT.Reg, volatile.LoadUint32(&o.PHY_LOOPBACK_CNT.Reg)&^(0xff)|value) +} +func (o *DSI_BRG_Type) GetPHY_LOOPBACK_CNT_PHY_HS_CHECK_CNT_TH() uint32 { + return volatile.LoadUint32(&o.PHY_LOOPBACK_CNT.Reg) & 0xff +} +func (o *DSI_BRG_Type) SetPHY_LOOPBACK_CNT_PHY_LP_CHECK_CNT_TH(value uint32) { + volatile.StoreUint32(&o.PHY_LOOPBACK_CNT.Reg, volatile.LoadUint32(&o.PHY_LOOPBACK_CNT.Reg)&^(0xff0000)|value<<16) +} +func (o *DSI_BRG_Type) GetPHY_LOOPBACK_CNT_PHY_LP_CHECK_CNT_TH() uint32 { + return (volatile.LoadUint32(&o.PHY_LOOPBACK_CNT.Reg) & 0xff0000) >> 16 +} + +// MIPI Display Interface Host +type DSI_HOST_Type struct { + VERSION volatile.Register32 // 0x0 + PWR_UP volatile.Register32 // 0x4 + CLKMGR_CFG volatile.Register32 // 0x8 + DPI_VCID volatile.Register32 // 0xC + DPI_COLOR_CODING volatile.Register32 // 0x10 + DPI_CFG_POL volatile.Register32 // 0x14 + DPI_LP_CMD_TIM volatile.Register32 // 0x18 + DBI_VCID volatile.Register32 // 0x1C + DBI_CFG volatile.Register32 // 0x20 + DBI_PARTITIONING_EN volatile.Register32 // 0x24 + DBI_CMDSIZE volatile.Register32 // 0x28 + PCKHDL_CFG volatile.Register32 // 0x2C + GEN_VCID volatile.Register32 // 0x30 + MODE_CFG volatile.Register32 // 0x34 + VID_MODE_CFG volatile.Register32 // 0x38 + VID_PKT_SIZE volatile.Register32 // 0x3C + VID_NUM_CHUNKS volatile.Register32 // 0x40 + VID_NULL_SIZE volatile.Register32 // 0x44 + VID_HSA_TIME volatile.Register32 // 0x48 + VID_HBP_TIME volatile.Register32 // 0x4C + VID_HLINE_TIME volatile.Register32 // 0x50 + VID_VSA_LINES volatile.Register32 // 0x54 + VID_VBP_LINES volatile.Register32 // 0x58 + VID_VFP_LINES volatile.Register32 // 0x5C + VID_VACTIVE_LINES volatile.Register32 // 0x60 + EDPI_CMD_SIZE volatile.Register32 // 0x64 + CMD_MODE_CFG volatile.Register32 // 0x68 + GEN_HDR volatile.Register32 // 0x6C + GEN_PLD_DATA volatile.Register32 // 0x70 + CMD_PKT_STATUS volatile.Register32 // 0x74 + TO_CNT_CFG volatile.Register32 // 0x78 + HS_RD_TO_CNT volatile.Register32 // 0x7C + LP_RD_TO_CNT volatile.Register32 // 0x80 + HS_WR_TO_CNT volatile.Register32 // 0x84 + LP_WR_TO_CNT volatile.Register32 // 0x88 + BTA_TO_CNT volatile.Register32 // 0x8C + SDF_3D volatile.Register32 // 0x90 + LPCLK_CTRL volatile.Register32 // 0x94 + PHY_TMR_LPCLK_CFG volatile.Register32 // 0x98 + PHY_TMR_CFG volatile.Register32 // 0x9C + PHY_RSTZ volatile.Register32 // 0xA0 + PHY_IF_CFG volatile.Register32 // 0xA4 + PHY_ULPS_CTRL volatile.Register32 // 0xA8 + PHY_TX_TRIGGERS volatile.Register32 // 0xAC + PHY_STATUS volatile.Register32 // 0xB0 + PHY_TST_CTRL0 volatile.Register32 // 0xB4 + PHY_TST_CTRL1 volatile.Register32 // 0xB8 + INT_ST0 volatile.Register32 // 0xBC + INT_ST1 volatile.Register32 // 0xC0 + INT_MSK0 volatile.Register32 // 0xC4 + INT_MSK1 volatile.Register32 // 0xC8 + PHY_CAL volatile.Register32 // 0xCC + _ [8]byte + INT_FORCE0 volatile.Register32 // 0xD8 + INT_FORCE1 volatile.Register32 // 0xDC + _ [16]byte + DSC_PARAMETER volatile.Register32 // 0xF0 + PHY_TMR_RD_CFG volatile.Register32 // 0xF4 + _ [8]byte + VID_SHADOW_CTRL volatile.Register32 // 0x100 + _ [8]byte + DPI_VCID_ACT volatile.Register32 // 0x10C + DPI_COLOR_CODING_ACT volatile.Register32 // 0x110 + _ [4]byte + DPI_LP_CMD_TIM_ACT volatile.Register32 // 0x118 + EDPI_TE_HW_CFG volatile.Register32 // 0x11C + _ [24]byte + VID_MODE_CFG_ACT volatile.Register32 // 0x138 + VID_PKT_SIZE_ACT volatile.Register32 // 0x13C + VID_NUM_CHUNKS_ACT volatile.Register32 // 0x140 + VID_NULL_SIZE_ACT volatile.Register32 // 0x144 + VID_HSA_TIME_ACT volatile.Register32 // 0x148 + VID_HBP_TIME_ACT volatile.Register32 // 0x14C + VID_HLINE_TIME_ACT volatile.Register32 // 0x150 + VID_VSA_LINES_ACT volatile.Register32 // 0x154 + VID_VBP_LINES_ACT volatile.Register32 // 0x158 + VID_VFP_LINES_ACT volatile.Register32 // 0x15C + VID_VACTIVE_LINES_ACT volatile.Register32 // 0x160 + _ [4]byte + VID_PKT_STATUS volatile.Register32 // 0x168 + _ [36]byte + SDF_3D_ACT volatile.Register32 // 0x190 +} + +// DSI_HOST.VERSION: NA +func (o *DSI_HOST_Type) SetVERSION(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, value) +} +func (o *DSI_HOST_Type) GetVERSION() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) +} + +// DSI_HOST.PWR_UP: NA +func (o *DSI_HOST_Type) SetPWR_UP_SHUTDOWNZ(value uint32) { + volatile.StoreUint32(&o.PWR_UP.Reg, volatile.LoadUint32(&o.PWR_UP.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetPWR_UP_SHUTDOWNZ() uint32 { + return volatile.LoadUint32(&o.PWR_UP.Reg) & 0x1 +} + +// DSI_HOST.CLKMGR_CFG: NA +func (o *DSI_HOST_Type) SetCLKMGR_CFG_TX_ESC_CLK_DIVISION(value uint32) { + volatile.StoreUint32(&o.CLKMGR_CFG.Reg, volatile.LoadUint32(&o.CLKMGR_CFG.Reg)&^(0xff)|value) +} +func (o *DSI_HOST_Type) GetCLKMGR_CFG_TX_ESC_CLK_DIVISION() uint32 { + return volatile.LoadUint32(&o.CLKMGR_CFG.Reg) & 0xff +} +func (o *DSI_HOST_Type) SetCLKMGR_CFG_TO_CLK_DIVISION(value uint32) { + volatile.StoreUint32(&o.CLKMGR_CFG.Reg, volatile.LoadUint32(&o.CLKMGR_CFG.Reg)&^(0xff00)|value<<8) +} +func (o *DSI_HOST_Type) GetCLKMGR_CFG_TO_CLK_DIVISION() uint32 { + return (volatile.LoadUint32(&o.CLKMGR_CFG.Reg) & 0xff00) >> 8 +} + +// DSI_HOST.DPI_VCID: NA +func (o *DSI_HOST_Type) SetDPI_VCID(value uint32) { + volatile.StoreUint32(&o.DPI_VCID.Reg, volatile.LoadUint32(&o.DPI_VCID.Reg)&^(0x3)|value) +} +func (o *DSI_HOST_Type) GetDPI_VCID() uint32 { + return volatile.LoadUint32(&o.DPI_VCID.Reg) & 0x3 +} + +// DSI_HOST.DPI_COLOR_CODING: NA +func (o *DSI_HOST_Type) SetDPI_COLOR_CODING(value uint32) { + volatile.StoreUint32(&o.DPI_COLOR_CODING.Reg, volatile.LoadUint32(&o.DPI_COLOR_CODING.Reg)&^(0xf)|value) +} +func (o *DSI_HOST_Type) GetDPI_COLOR_CODING() uint32 { + return volatile.LoadUint32(&o.DPI_COLOR_CODING.Reg) & 0xf +} +func (o *DSI_HOST_Type) SetDPI_COLOR_CODING_LOOSELY18_EN(value uint32) { + volatile.StoreUint32(&o.DPI_COLOR_CODING.Reg, volatile.LoadUint32(&o.DPI_COLOR_CODING.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetDPI_COLOR_CODING_LOOSELY18_EN() uint32 { + return (volatile.LoadUint32(&o.DPI_COLOR_CODING.Reg) & 0x100) >> 8 +} + +// DSI_HOST.DPI_CFG_POL: NA +func (o *DSI_HOST_Type) SetDPI_CFG_POL_DATAEN_ACTIVE_LOW(value uint32) { + volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetDPI_CFG_POL_DATAEN_ACTIVE_LOW() uint32 { + return volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetDPI_CFG_POL_VSYNC_ACTIVE_LOW(value uint32) { + volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetDPI_CFG_POL_VSYNC_ACTIVE_LOW() uint32 { + return (volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetDPI_CFG_POL_HSYNC_ACTIVE_LOW(value uint32) { + volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetDPI_CFG_POL_HSYNC_ACTIVE_LOW() uint32 { + return (volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetDPI_CFG_POL_SHUTD_ACTIVE_LOW(value uint32) { + volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetDPI_CFG_POL_SHUTD_ACTIVE_LOW() uint32 { + return (volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetDPI_CFG_POL_COLORM_ACTIVE_LOW(value uint32) { + volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetDPI_CFG_POL_COLORM_ACTIVE_LOW() uint32 { + return (volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x10) >> 4 +} + +// DSI_HOST.DPI_LP_CMD_TIM: NA +func (o *DSI_HOST_Type) SetDPI_LP_CMD_TIM_INVACT_LPCMD_TIME(value uint32) { + volatile.StoreUint32(&o.DPI_LP_CMD_TIM.Reg, volatile.LoadUint32(&o.DPI_LP_CMD_TIM.Reg)&^(0xff)|value) +} +func (o *DSI_HOST_Type) GetDPI_LP_CMD_TIM_INVACT_LPCMD_TIME() uint32 { + return volatile.LoadUint32(&o.DPI_LP_CMD_TIM.Reg) & 0xff +} +func (o *DSI_HOST_Type) SetDPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME(value uint32) { + volatile.StoreUint32(&o.DPI_LP_CMD_TIM.Reg, volatile.LoadUint32(&o.DPI_LP_CMD_TIM.Reg)&^(0xff0000)|value<<16) +} +func (o *DSI_HOST_Type) GetDPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME() uint32 { + return (volatile.LoadUint32(&o.DPI_LP_CMD_TIM.Reg) & 0xff0000) >> 16 +} + +// DSI_HOST.DBI_VCID: NA +func (o *DSI_HOST_Type) SetDBI_VCID(value uint32) { + volatile.StoreUint32(&o.DBI_VCID.Reg, volatile.LoadUint32(&o.DBI_VCID.Reg)&^(0x3)|value) +} +func (o *DSI_HOST_Type) GetDBI_VCID() uint32 { + return volatile.LoadUint32(&o.DBI_VCID.Reg) & 0x3 +} + +// DSI_HOST.DBI_CFG: NA +func (o *DSI_HOST_Type) SetDBI_CFG_IN_DBI_CONF(value uint32) { + volatile.StoreUint32(&o.DBI_CFG.Reg, volatile.LoadUint32(&o.DBI_CFG.Reg)&^(0xf)|value) +} +func (o *DSI_HOST_Type) GetDBI_CFG_IN_DBI_CONF() uint32 { + return volatile.LoadUint32(&o.DBI_CFG.Reg) & 0xf +} +func (o *DSI_HOST_Type) SetDBI_CFG_OUT_DBI_CONF(value uint32) { + volatile.StoreUint32(&o.DBI_CFG.Reg, volatile.LoadUint32(&o.DBI_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *DSI_HOST_Type) GetDBI_CFG_OUT_DBI_CONF() uint32 { + return (volatile.LoadUint32(&o.DBI_CFG.Reg) & 0xf00) >> 8 +} +func (o *DSI_HOST_Type) SetDBI_CFG_LUT_SIZE_CONF(value uint32) { + volatile.StoreUint32(&o.DBI_CFG.Reg, volatile.LoadUint32(&o.DBI_CFG.Reg)&^(0x30000)|value<<16) +} +func (o *DSI_HOST_Type) GetDBI_CFG_LUT_SIZE_CONF() uint32 { + return (volatile.LoadUint32(&o.DBI_CFG.Reg) & 0x30000) >> 16 +} + +// DSI_HOST.DBI_PARTITIONING_EN: NA +func (o *DSI_HOST_Type) SetDBI_PARTITIONING_EN_PARTITIONING_EN(value uint32) { + volatile.StoreUint32(&o.DBI_PARTITIONING_EN.Reg, volatile.LoadUint32(&o.DBI_PARTITIONING_EN.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetDBI_PARTITIONING_EN_PARTITIONING_EN() uint32 { + return volatile.LoadUint32(&o.DBI_PARTITIONING_EN.Reg) & 0x1 +} + +// DSI_HOST.DBI_CMDSIZE: NA +func (o *DSI_HOST_Type) SetDBI_CMDSIZE_WR_CMD_SIZE(value uint32) { + volatile.StoreUint32(&o.DBI_CMDSIZE.Reg, volatile.LoadUint32(&o.DBI_CMDSIZE.Reg)&^(0xffff)|value) +} +func (o *DSI_HOST_Type) GetDBI_CMDSIZE_WR_CMD_SIZE() uint32 { + return volatile.LoadUint32(&o.DBI_CMDSIZE.Reg) & 0xffff +} +func (o *DSI_HOST_Type) SetDBI_CMDSIZE_ALLOWED_CMD_SIZE(value uint32) { + volatile.StoreUint32(&o.DBI_CMDSIZE.Reg, volatile.LoadUint32(&o.DBI_CMDSIZE.Reg)&^(0xffff0000)|value<<16) +} +func (o *DSI_HOST_Type) GetDBI_CMDSIZE_ALLOWED_CMD_SIZE() uint32 { + return (volatile.LoadUint32(&o.DBI_CMDSIZE.Reg) & 0xffff0000) >> 16 +} + +// DSI_HOST.PCKHDL_CFG: NA +func (o *DSI_HOST_Type) SetPCKHDL_CFG_EOTP_TX_EN(value uint32) { + volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetPCKHDL_CFG_EOTP_TX_EN() uint32 { + return volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetPCKHDL_CFG_EOTP_RX_EN(value uint32) { + volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetPCKHDL_CFG_EOTP_RX_EN() uint32 { + return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetPCKHDL_CFG_BTA_EN(value uint32) { + volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetPCKHDL_CFG_BTA_EN() uint32 { + return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetPCKHDL_CFG_ECC_RX_EN(value uint32) { + volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetPCKHDL_CFG_ECC_RX_EN() uint32 { + return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetPCKHDL_CFG_CRC_RX_EN(value uint32) { + volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetPCKHDL_CFG_CRC_RX_EN() uint32 { + return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetPCKHDL_CFG_EOTP_TX_LP_EN(value uint32) { + volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetPCKHDL_CFG_EOTP_TX_LP_EN() uint32 { + return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x20) >> 5 +} + +// DSI_HOST.GEN_VCID: NA +func (o *DSI_HOST_Type) SetGEN_VCID_RX(value uint32) { + volatile.StoreUint32(&o.GEN_VCID.Reg, volatile.LoadUint32(&o.GEN_VCID.Reg)&^(0x3)|value) +} +func (o *DSI_HOST_Type) GetGEN_VCID_RX() uint32 { + return volatile.LoadUint32(&o.GEN_VCID.Reg) & 0x3 +} +func (o *DSI_HOST_Type) SetGEN_VCID_TEAR_AUTO(value uint32) { + volatile.StoreUint32(&o.GEN_VCID.Reg, volatile.LoadUint32(&o.GEN_VCID.Reg)&^(0x300)|value<<8) +} +func (o *DSI_HOST_Type) GetGEN_VCID_TEAR_AUTO() uint32 { + return (volatile.LoadUint32(&o.GEN_VCID.Reg) & 0x300) >> 8 +} +func (o *DSI_HOST_Type) SetGEN_VCID_TX_AUTO(value uint32) { + volatile.StoreUint32(&o.GEN_VCID.Reg, volatile.LoadUint32(&o.GEN_VCID.Reg)&^(0x30000)|value<<16) +} +func (o *DSI_HOST_Type) GetGEN_VCID_TX_AUTO() uint32 { + return (volatile.LoadUint32(&o.GEN_VCID.Reg) & 0x30000) >> 16 +} + +// DSI_HOST.MODE_CFG: NA +func (o *DSI_HOST_Type) SetMODE_CFG_CMD_VIDEO_MODE(value uint32) { + volatile.StoreUint32(&o.MODE_CFG.Reg, volatile.LoadUint32(&o.MODE_CFG.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetMODE_CFG_CMD_VIDEO_MODE() uint32 { + return volatile.LoadUint32(&o.MODE_CFG.Reg) & 0x1 +} + +// DSI_HOST.VID_MODE_CFG: NA +func (o *DSI_HOST_Type) SetVID_MODE_CFG_VID_MODE_TYPE(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x3)|value) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_VID_MODE_TYPE() uint32 { + return volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x3 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_VSA_EN(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_VSA_EN() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_VBP_EN(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x200)|value<<9) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_VBP_EN() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x200) >> 9 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_VFP_EN(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x400)|value<<10) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_VFP_EN() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x400) >> 10 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_VACT_EN(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x800)|value<<11) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_VACT_EN() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x800) >> 11 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_HBP_EN(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_HBP_EN() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x1000) >> 12 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_HFP_EN(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_HFP_EN() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x2000) >> 13 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_FRAME_BTA_ACK_EN(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_FRAME_BTA_ACK_EN() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x4000) >> 14 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_CMD_EN(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_CMD_EN() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x8000) >> 15 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_VPG_EN(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_VPG_EN() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x10000) >> 16 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_VPG_MODE(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x100000)|value<<20) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_VPG_MODE() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x100000) >> 20 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_VPG_ORIENTATION(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_VPG_ORIENTATION() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x1000000) >> 24 +} + +// DSI_HOST.VID_PKT_SIZE: NA +func (o *DSI_HOST_Type) SetVID_PKT_SIZE(value uint32) { + volatile.StoreUint32(&o.VID_PKT_SIZE.Reg, volatile.LoadUint32(&o.VID_PKT_SIZE.Reg)&^(0x3fff)|value) +} +func (o *DSI_HOST_Type) GetVID_PKT_SIZE() uint32 { + return volatile.LoadUint32(&o.VID_PKT_SIZE.Reg) & 0x3fff +} + +// DSI_HOST.VID_NUM_CHUNKS: NA +func (o *DSI_HOST_Type) SetVID_NUM_CHUNKS(value uint32) { + volatile.StoreUint32(&o.VID_NUM_CHUNKS.Reg, volatile.LoadUint32(&o.VID_NUM_CHUNKS.Reg)&^(0x1fff)|value) +} +func (o *DSI_HOST_Type) GetVID_NUM_CHUNKS() uint32 { + return volatile.LoadUint32(&o.VID_NUM_CHUNKS.Reg) & 0x1fff +} + +// DSI_HOST.VID_NULL_SIZE: NA +func (o *DSI_HOST_Type) SetVID_NULL_SIZE(value uint32) { + volatile.StoreUint32(&o.VID_NULL_SIZE.Reg, volatile.LoadUint32(&o.VID_NULL_SIZE.Reg)&^(0x1fff)|value) +} +func (o *DSI_HOST_Type) GetVID_NULL_SIZE() uint32 { + return volatile.LoadUint32(&o.VID_NULL_SIZE.Reg) & 0x1fff +} + +// DSI_HOST.VID_HSA_TIME: NA +func (o *DSI_HOST_Type) SetVID_HSA_TIME(value uint32) { + volatile.StoreUint32(&o.VID_HSA_TIME.Reg, volatile.LoadUint32(&o.VID_HSA_TIME.Reg)&^(0xfff)|value) +} +func (o *DSI_HOST_Type) GetVID_HSA_TIME() uint32 { + return volatile.LoadUint32(&o.VID_HSA_TIME.Reg) & 0xfff +} + +// DSI_HOST.VID_HBP_TIME: NA +func (o *DSI_HOST_Type) SetVID_HBP_TIME(value uint32) { + volatile.StoreUint32(&o.VID_HBP_TIME.Reg, volatile.LoadUint32(&o.VID_HBP_TIME.Reg)&^(0xfff)|value) +} +func (o *DSI_HOST_Type) GetVID_HBP_TIME() uint32 { + return volatile.LoadUint32(&o.VID_HBP_TIME.Reg) & 0xfff +} + +// DSI_HOST.VID_HLINE_TIME: NA +func (o *DSI_HOST_Type) SetVID_HLINE_TIME(value uint32) { + volatile.StoreUint32(&o.VID_HLINE_TIME.Reg, volatile.LoadUint32(&o.VID_HLINE_TIME.Reg)&^(0x7fff)|value) +} +func (o *DSI_HOST_Type) GetVID_HLINE_TIME() uint32 { + return volatile.LoadUint32(&o.VID_HLINE_TIME.Reg) & 0x7fff +} + +// DSI_HOST.VID_VSA_LINES: NA +func (o *DSI_HOST_Type) SetVID_VSA_LINES_VSA_LINES(value uint32) { + volatile.StoreUint32(&o.VID_VSA_LINES.Reg, volatile.LoadUint32(&o.VID_VSA_LINES.Reg)&^(0x3ff)|value) +} +func (o *DSI_HOST_Type) GetVID_VSA_LINES_VSA_LINES() uint32 { + return volatile.LoadUint32(&o.VID_VSA_LINES.Reg) & 0x3ff +} + +// DSI_HOST.VID_VBP_LINES: NA +func (o *DSI_HOST_Type) SetVID_VBP_LINES_VBP_LINES(value uint32) { + volatile.StoreUint32(&o.VID_VBP_LINES.Reg, volatile.LoadUint32(&o.VID_VBP_LINES.Reg)&^(0x3ff)|value) +} +func (o *DSI_HOST_Type) GetVID_VBP_LINES_VBP_LINES() uint32 { + return volatile.LoadUint32(&o.VID_VBP_LINES.Reg) & 0x3ff +} + +// DSI_HOST.VID_VFP_LINES: NA +func (o *DSI_HOST_Type) SetVID_VFP_LINES_VFP_LINES(value uint32) { + volatile.StoreUint32(&o.VID_VFP_LINES.Reg, volatile.LoadUint32(&o.VID_VFP_LINES.Reg)&^(0x3ff)|value) +} +func (o *DSI_HOST_Type) GetVID_VFP_LINES_VFP_LINES() uint32 { + return volatile.LoadUint32(&o.VID_VFP_LINES.Reg) & 0x3ff +} + +// DSI_HOST.VID_VACTIVE_LINES: NA +func (o *DSI_HOST_Type) SetVID_VACTIVE_LINES_V_ACTIVE_LINES(value uint32) { + volatile.StoreUint32(&o.VID_VACTIVE_LINES.Reg, volatile.LoadUint32(&o.VID_VACTIVE_LINES.Reg)&^(0x3fff)|value) +} +func (o *DSI_HOST_Type) GetVID_VACTIVE_LINES_V_ACTIVE_LINES() uint32 { + return volatile.LoadUint32(&o.VID_VACTIVE_LINES.Reg) & 0x3fff +} + +// DSI_HOST.EDPI_CMD_SIZE: NA +func (o *DSI_HOST_Type) SetEDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE(value uint32) { + volatile.StoreUint32(&o.EDPI_CMD_SIZE.Reg, volatile.LoadUint32(&o.EDPI_CMD_SIZE.Reg)&^(0xffff)|value) +} +func (o *DSI_HOST_Type) GetEDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE() uint32 { + return volatile.LoadUint32(&o.EDPI_CMD_SIZE.Reg) & 0xffff +} + +// DSI_HOST.CMD_MODE_CFG: NA +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_TEAR_FX_EN(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_TEAR_FX_EN() uint32 { + return volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_ACK_RQST_EN(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_ACK_RQST_EN() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SW_0P_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SW_0P_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SW_1P_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x200)|value<<9) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SW_1P_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x200) >> 9 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SW_2P_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x400)|value<<10) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SW_2P_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x400) >> 10 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SR_0P_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x800)|value<<11) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SR_0P_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x800) >> 11 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SR_1P_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SR_1P_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x1000) >> 12 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SR_2P_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SR_2P_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x2000) >> 13 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_LW_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_LW_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x4000) >> 14 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_DCS_SW_0P_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_DCS_SW_0P_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x10000) >> 16 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_DCS_SW_1P_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_DCS_SW_1P_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x20000) >> 17 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_DCS_SR_0P_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x40000)|value<<18) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_DCS_SR_0P_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x40000) >> 18 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_DCS_LW_TX(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x80000)|value<<19) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_DCS_LW_TX() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x80000) >> 19 +} +func (o *DSI_HOST_Type) SetCMD_MODE_CFG_MAX_RD_PKT_SIZE(value uint32) { + volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *DSI_HOST_Type) GetCMD_MODE_CFG_MAX_RD_PKT_SIZE() uint32 { + return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x1000000) >> 24 +} + +// DSI_HOST.GEN_HDR: NA +func (o *DSI_HOST_Type) SetGEN_HDR_GEN_DT(value uint32) { + volatile.StoreUint32(&o.GEN_HDR.Reg, volatile.LoadUint32(&o.GEN_HDR.Reg)&^(0x3f)|value) +} +func (o *DSI_HOST_Type) GetGEN_HDR_GEN_DT() uint32 { + return volatile.LoadUint32(&o.GEN_HDR.Reg) & 0x3f +} +func (o *DSI_HOST_Type) SetGEN_HDR_GEN_VC(value uint32) { + volatile.StoreUint32(&o.GEN_HDR.Reg, volatile.LoadUint32(&o.GEN_HDR.Reg)&^(0xc0)|value<<6) +} +func (o *DSI_HOST_Type) GetGEN_HDR_GEN_VC() uint32 { + return (volatile.LoadUint32(&o.GEN_HDR.Reg) & 0xc0) >> 6 +} +func (o *DSI_HOST_Type) SetGEN_HDR_GEN_WC_LSBYTE(value uint32) { + volatile.StoreUint32(&o.GEN_HDR.Reg, volatile.LoadUint32(&o.GEN_HDR.Reg)&^(0xff00)|value<<8) +} +func (o *DSI_HOST_Type) GetGEN_HDR_GEN_WC_LSBYTE() uint32 { + return (volatile.LoadUint32(&o.GEN_HDR.Reg) & 0xff00) >> 8 +} +func (o *DSI_HOST_Type) SetGEN_HDR_GEN_WC_MSBYTE(value uint32) { + volatile.StoreUint32(&o.GEN_HDR.Reg, volatile.LoadUint32(&o.GEN_HDR.Reg)&^(0xff0000)|value<<16) +} +func (o *DSI_HOST_Type) GetGEN_HDR_GEN_WC_MSBYTE() uint32 { + return (volatile.LoadUint32(&o.GEN_HDR.Reg) & 0xff0000) >> 16 +} + +// DSI_HOST.GEN_PLD_DATA: NA +func (o *DSI_HOST_Type) SetGEN_PLD_DATA_GEN_PLD_B1(value uint32) { + volatile.StoreUint32(&o.GEN_PLD_DATA.Reg, volatile.LoadUint32(&o.GEN_PLD_DATA.Reg)&^(0xff)|value) +} +func (o *DSI_HOST_Type) GetGEN_PLD_DATA_GEN_PLD_B1() uint32 { + return volatile.LoadUint32(&o.GEN_PLD_DATA.Reg) & 0xff +} +func (o *DSI_HOST_Type) SetGEN_PLD_DATA_GEN_PLD_B2(value uint32) { + volatile.StoreUint32(&o.GEN_PLD_DATA.Reg, volatile.LoadUint32(&o.GEN_PLD_DATA.Reg)&^(0xff00)|value<<8) +} +func (o *DSI_HOST_Type) GetGEN_PLD_DATA_GEN_PLD_B2() uint32 { + return (volatile.LoadUint32(&o.GEN_PLD_DATA.Reg) & 0xff00) >> 8 +} +func (o *DSI_HOST_Type) SetGEN_PLD_DATA_GEN_PLD_B3(value uint32) { + volatile.StoreUint32(&o.GEN_PLD_DATA.Reg, volatile.LoadUint32(&o.GEN_PLD_DATA.Reg)&^(0xff0000)|value<<16) +} +func (o *DSI_HOST_Type) GetGEN_PLD_DATA_GEN_PLD_B3() uint32 { + return (volatile.LoadUint32(&o.GEN_PLD_DATA.Reg) & 0xff0000) >> 16 +} +func (o *DSI_HOST_Type) SetGEN_PLD_DATA_GEN_PLD_B4(value uint32) { + volatile.StoreUint32(&o.GEN_PLD_DATA.Reg, volatile.LoadUint32(&o.GEN_PLD_DATA.Reg)&^(0xff000000)|value<<24) +} +func (o *DSI_HOST_Type) GetGEN_PLD_DATA_GEN_PLD_B4() uint32 { + return (volatile.LoadUint32(&o.GEN_PLD_DATA.Reg) & 0xff000000) >> 24 +} + +// DSI_HOST.CMD_PKT_STATUS: NA +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_CMD_EMPTY(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_CMD_EMPTY() uint32 { + return volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_CMD_FULL(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_CMD_FULL() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_PLD_W_EMPTY(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_PLD_W_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_PLD_W_FULL(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_PLD_W_FULL() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_PLD_R_EMPTY(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_PLD_R_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_PLD_R_FULL(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_PLD_R_FULL() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_RD_CMD_BUSY(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_RD_CMD_BUSY() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x40) >> 6 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x10000) >> 16 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_BUFF_CMD_FULL(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_BUFF_CMD_FULL() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x20000) >> 17 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x40000)|value<<18) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x40000) >> 18 +} +func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_BUFF_PLD_FULL(value uint32) { + volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x80000)|value<<19) +} +func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_BUFF_PLD_FULL() uint32 { + return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x80000) >> 19 +} + +// DSI_HOST.TO_CNT_CFG: NA +func (o *DSI_HOST_Type) SetTO_CNT_CFG_LPRX_TO_CNT(value uint32) { + volatile.StoreUint32(&o.TO_CNT_CFG.Reg, volatile.LoadUint32(&o.TO_CNT_CFG.Reg)&^(0xffff)|value) +} +func (o *DSI_HOST_Type) GetTO_CNT_CFG_LPRX_TO_CNT() uint32 { + return volatile.LoadUint32(&o.TO_CNT_CFG.Reg) & 0xffff +} +func (o *DSI_HOST_Type) SetTO_CNT_CFG_HSTX_TO_CNT(value uint32) { + volatile.StoreUint32(&o.TO_CNT_CFG.Reg, volatile.LoadUint32(&o.TO_CNT_CFG.Reg)&^(0xffff0000)|value<<16) +} +func (o *DSI_HOST_Type) GetTO_CNT_CFG_HSTX_TO_CNT() uint32 { + return (volatile.LoadUint32(&o.TO_CNT_CFG.Reg) & 0xffff0000) >> 16 +} + +// DSI_HOST.HS_RD_TO_CNT: NA +func (o *DSI_HOST_Type) SetHS_RD_TO_CNT(value uint32) { + volatile.StoreUint32(&o.HS_RD_TO_CNT.Reg, volatile.LoadUint32(&o.HS_RD_TO_CNT.Reg)&^(0xffff)|value) +} +func (o *DSI_HOST_Type) GetHS_RD_TO_CNT() uint32 { + return volatile.LoadUint32(&o.HS_RD_TO_CNT.Reg) & 0xffff +} + +// DSI_HOST.LP_RD_TO_CNT: NA +func (o *DSI_HOST_Type) SetLP_RD_TO_CNT(value uint32) { + volatile.StoreUint32(&o.LP_RD_TO_CNT.Reg, volatile.LoadUint32(&o.LP_RD_TO_CNT.Reg)&^(0xffff)|value) +} +func (o *DSI_HOST_Type) GetLP_RD_TO_CNT() uint32 { + return volatile.LoadUint32(&o.LP_RD_TO_CNT.Reg) & 0xffff +} + +// DSI_HOST.HS_WR_TO_CNT: NA +func (o *DSI_HOST_Type) SetHS_WR_TO_CNT(value uint32) { + volatile.StoreUint32(&o.HS_WR_TO_CNT.Reg, volatile.LoadUint32(&o.HS_WR_TO_CNT.Reg)&^(0xffff)|value) +} +func (o *DSI_HOST_Type) GetHS_WR_TO_CNT() uint32 { + return volatile.LoadUint32(&o.HS_WR_TO_CNT.Reg) & 0xffff +} + +// DSI_HOST.LP_WR_TO_CNT: NA +func (o *DSI_HOST_Type) SetLP_WR_TO_CNT(value uint32) { + volatile.StoreUint32(&o.LP_WR_TO_CNT.Reg, volatile.LoadUint32(&o.LP_WR_TO_CNT.Reg)&^(0xffff)|value) +} +func (o *DSI_HOST_Type) GetLP_WR_TO_CNT() uint32 { + return volatile.LoadUint32(&o.LP_WR_TO_CNT.Reg) & 0xffff +} + +// DSI_HOST.BTA_TO_CNT: NA +func (o *DSI_HOST_Type) SetBTA_TO_CNT(value uint32) { + volatile.StoreUint32(&o.BTA_TO_CNT.Reg, volatile.LoadUint32(&o.BTA_TO_CNT.Reg)&^(0xffff)|value) +} +func (o *DSI_HOST_Type) GetBTA_TO_CNT() uint32 { + return volatile.LoadUint32(&o.BTA_TO_CNT.Reg) & 0xffff +} + +// DSI_HOST.SDF_3D: NA +func (o *DSI_HOST_Type) SetSDF_3D_MODE_3D(value uint32) { + volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0x3)|value) +} +func (o *DSI_HOST_Type) GetSDF_3D_MODE_3D() uint32 { + return volatile.LoadUint32(&o.SDF_3D.Reg) & 0x3 +} +func (o *DSI_HOST_Type) SetSDF_3D_FORMAT_3D(value uint32) { + volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0xc)|value<<2) +} +func (o *DSI_HOST_Type) GetSDF_3D_FORMAT_3D() uint32 { + return (volatile.LoadUint32(&o.SDF_3D.Reg) & 0xc) >> 2 +} +func (o *DSI_HOST_Type) SetSDF_3D_SECOND_VSYNC(value uint32) { + volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetSDF_3D_SECOND_VSYNC() uint32 { + return (volatile.LoadUint32(&o.SDF_3D.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetSDF_3D_RIGHT_FIRST(value uint32) { + volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetSDF_3D_RIGHT_FIRST() uint32 { + return (volatile.LoadUint32(&o.SDF_3D.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetSDF_3D_SEND_3D_CFG(value uint32) { + volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetSDF_3D_SEND_3D_CFG() uint32 { + return (volatile.LoadUint32(&o.SDF_3D.Reg) & 0x10000) >> 16 +} + +// DSI_HOST.LPCLK_CTRL: NA +func (o *DSI_HOST_Type) SetLPCLK_CTRL_PHY_TXREQUESTCLKHS(value uint32) { + volatile.StoreUint32(&o.LPCLK_CTRL.Reg, volatile.LoadUint32(&o.LPCLK_CTRL.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetLPCLK_CTRL_PHY_TXREQUESTCLKHS() uint32 { + return volatile.LoadUint32(&o.LPCLK_CTRL.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetLPCLK_CTRL_AUTO_CLKLANE_CTRL(value uint32) { + volatile.StoreUint32(&o.LPCLK_CTRL.Reg, volatile.LoadUint32(&o.LPCLK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetLPCLK_CTRL_AUTO_CLKLANE_CTRL() uint32 { + return (volatile.LoadUint32(&o.LPCLK_CTRL.Reg) & 0x2) >> 1 +} + +// DSI_HOST.PHY_TMR_LPCLK_CFG: NA +func (o *DSI_HOST_Type) SetPHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME(value uint32) { + volatile.StoreUint32(&o.PHY_TMR_LPCLK_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_LPCLK_CFG.Reg)&^(0x3ff)|value) +} +func (o *DSI_HOST_Type) GetPHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME() uint32 { + return volatile.LoadUint32(&o.PHY_TMR_LPCLK_CFG.Reg) & 0x3ff +} +func (o *DSI_HOST_Type) SetPHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME(value uint32) { + volatile.StoreUint32(&o.PHY_TMR_LPCLK_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_LPCLK_CFG.Reg)&^(0x3ff0000)|value<<16) +} +func (o *DSI_HOST_Type) GetPHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME() uint32 { + return (volatile.LoadUint32(&o.PHY_TMR_LPCLK_CFG.Reg) & 0x3ff0000) >> 16 +} + +// DSI_HOST.PHY_TMR_CFG: NA +func (o *DSI_HOST_Type) SetPHY_TMR_CFG_PHY_LP2HS_TIME(value uint32) { + volatile.StoreUint32(&o.PHY_TMR_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_CFG.Reg)&^(0x3ff)|value) +} +func (o *DSI_HOST_Type) GetPHY_TMR_CFG_PHY_LP2HS_TIME() uint32 { + return volatile.LoadUint32(&o.PHY_TMR_CFG.Reg) & 0x3ff +} +func (o *DSI_HOST_Type) SetPHY_TMR_CFG_PHY_HS2LP_TIME(value uint32) { + volatile.StoreUint32(&o.PHY_TMR_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_CFG.Reg)&^(0x3ff0000)|value<<16) +} +func (o *DSI_HOST_Type) GetPHY_TMR_CFG_PHY_HS2LP_TIME() uint32 { + return (volatile.LoadUint32(&o.PHY_TMR_CFG.Reg) & 0x3ff0000) >> 16 +} + +// DSI_HOST.PHY_RSTZ: NA +func (o *DSI_HOST_Type) SetPHY_RSTZ_PHY_SHUTDOWNZ(value uint32) { + volatile.StoreUint32(&o.PHY_RSTZ.Reg, volatile.LoadUint32(&o.PHY_RSTZ.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetPHY_RSTZ_PHY_SHUTDOWNZ() uint32 { + return volatile.LoadUint32(&o.PHY_RSTZ.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetPHY_RSTZ(value uint32) { + volatile.StoreUint32(&o.PHY_RSTZ.Reg, volatile.LoadUint32(&o.PHY_RSTZ.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetPHY_RSTZ() uint32 { + return (volatile.LoadUint32(&o.PHY_RSTZ.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetPHY_RSTZ_PHY_ENABLECLK(value uint32) { + volatile.StoreUint32(&o.PHY_RSTZ.Reg, volatile.LoadUint32(&o.PHY_RSTZ.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetPHY_RSTZ_PHY_ENABLECLK() uint32 { + return (volatile.LoadUint32(&o.PHY_RSTZ.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetPHY_RSTZ_PHY_FORCEPLL(value uint32) { + volatile.StoreUint32(&o.PHY_RSTZ.Reg, volatile.LoadUint32(&o.PHY_RSTZ.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetPHY_RSTZ_PHY_FORCEPLL() uint32 { + return (volatile.LoadUint32(&o.PHY_RSTZ.Reg) & 0x8) >> 3 +} + +// DSI_HOST.PHY_IF_CFG: NA +func (o *DSI_HOST_Type) SetPHY_IF_CFG_N_LANES(value uint32) { + volatile.StoreUint32(&o.PHY_IF_CFG.Reg, volatile.LoadUint32(&o.PHY_IF_CFG.Reg)&^(0x3)|value) +} +func (o *DSI_HOST_Type) GetPHY_IF_CFG_N_LANES() uint32 { + return volatile.LoadUint32(&o.PHY_IF_CFG.Reg) & 0x3 +} +func (o *DSI_HOST_Type) SetPHY_IF_CFG_PHY_STOP_WAIT_TIME(value uint32) { + volatile.StoreUint32(&o.PHY_IF_CFG.Reg, volatile.LoadUint32(&o.PHY_IF_CFG.Reg)&^(0xff00)|value<<8) +} +func (o *DSI_HOST_Type) GetPHY_IF_CFG_PHY_STOP_WAIT_TIME() uint32 { + return (volatile.LoadUint32(&o.PHY_IF_CFG.Reg) & 0xff00) >> 8 +} + +// DSI_HOST.PHY_ULPS_CTRL: NA +func (o *DSI_HOST_Type) SetPHY_ULPS_CTRL_PHY_TXREQULPSCLK(value uint32) { + volatile.StoreUint32(&o.PHY_ULPS_CTRL.Reg, volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetPHY_ULPS_CTRL_PHY_TXREQULPSCLK() uint32 { + return volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetPHY_ULPS_CTRL_PHY_TXEXITULPSCLK(value uint32) { + volatile.StoreUint32(&o.PHY_ULPS_CTRL.Reg, volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetPHY_ULPS_CTRL_PHY_TXEXITULPSCLK() uint32 { + return (volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetPHY_ULPS_CTRL_PHY_TXREQULPSLAN(value uint32) { + volatile.StoreUint32(&o.PHY_ULPS_CTRL.Reg, volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetPHY_ULPS_CTRL_PHY_TXREQULPSLAN() uint32 { + return (volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetPHY_ULPS_CTRL_PHY_TXEXITULPSLAN(value uint32) { + volatile.StoreUint32(&o.PHY_ULPS_CTRL.Reg, volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetPHY_ULPS_CTRL_PHY_TXEXITULPSLAN() uint32 { + return (volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg) & 0x8) >> 3 +} + +// DSI_HOST.PHY_TX_TRIGGERS: NA +func (o *DSI_HOST_Type) SetPHY_TX_TRIGGERS(value uint32) { + volatile.StoreUint32(&o.PHY_TX_TRIGGERS.Reg, volatile.LoadUint32(&o.PHY_TX_TRIGGERS.Reg)&^(0xf)|value) +} +func (o *DSI_HOST_Type) GetPHY_TX_TRIGGERS() uint32 { + return volatile.LoadUint32(&o.PHY_TX_TRIGGERS.Reg) & 0xf +} + +// DSI_HOST.PHY_STATUS: NA +func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_LOCK(value uint32) { + volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_LOCK() uint32 { + return volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_DIRECTION(value uint32) { + volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_STOPSTATECLKLANE(value uint32) { + volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_STOPSTATECLKLANE() uint32 { + return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_ULPSACTIVENOTCLK(value uint32) { + volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_ULPSACTIVENOTCLK() uint32 { + return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_STOPSTATE0LANE(value uint32) { + volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_STOPSTATE0LANE() uint32 { + return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_ULPSACTIVENOT0LANE(value uint32) { + volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_ULPSACTIVENOT0LANE() uint32 { + return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_RXULPSESC0LANE(value uint32) { + volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_RXULPSESC0LANE() uint32 { + return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x40) >> 6 +} +func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_STOPSTATE1LANE(value uint32) { + volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_STOPSTATE1LANE() uint32 { + return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x80) >> 7 +} +func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_ULPSACTIVENOT1LANE(value uint32) { + volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_ULPSACTIVENOT1LANE() uint32 { + return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x100) >> 8 +} + +// DSI_HOST.PHY_TST_CTRL0: NA +func (o *DSI_HOST_Type) SetPHY_TST_CTRL0_PHY_TESTCLR(value uint32) { + volatile.StoreUint32(&o.PHY_TST_CTRL0.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL0.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetPHY_TST_CTRL0_PHY_TESTCLR() uint32 { + return volatile.LoadUint32(&o.PHY_TST_CTRL0.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetPHY_TST_CTRL0_PHY_TESTCLK(value uint32) { + volatile.StoreUint32(&o.PHY_TST_CTRL0.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL0.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetPHY_TST_CTRL0_PHY_TESTCLK() uint32 { + return (volatile.LoadUint32(&o.PHY_TST_CTRL0.Reg) & 0x2) >> 1 +} + +// DSI_HOST.PHY_TST_CTRL1: NA +func (o *DSI_HOST_Type) SetPHY_TST_CTRL1_PHY_TESTDIN(value uint32) { + volatile.StoreUint32(&o.PHY_TST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg)&^(0xff)|value) +} +func (o *DSI_HOST_Type) GetPHY_TST_CTRL1_PHY_TESTDIN() uint32 { + return volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg) & 0xff +} +func (o *DSI_HOST_Type) SetPHY_TST_CTRL1_PHT_TESTDOUT(value uint32) { + volatile.StoreUint32(&o.PHY_TST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg)&^(0xff00)|value<<8) +} +func (o *DSI_HOST_Type) GetPHY_TST_CTRL1_PHT_TESTDOUT() uint32 { + return (volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg) & 0xff00) >> 8 +} +func (o *DSI_HOST_Type) SetPHY_TST_CTRL1_PHY_TESTEN(value uint32) { + volatile.StoreUint32(&o.PHY_TST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetPHY_TST_CTRL1_PHY_TESTEN() uint32 { + return (volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg) & 0x10000) >> 16 +} + +// DSI_HOST.INT_ST0: NA +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_0(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_0() uint32 { + return volatile.LoadUint32(&o.INT_ST0.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_1(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_1() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_2(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_2() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_3(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_3() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_4(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_4() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_5(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_5() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_6(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x40)|value<<6) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_6() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x40) >> 6 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_7(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x80)|value<<7) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_7() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x80) >> 7 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_8(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_8() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_9(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x200)|value<<9) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_9() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x200) >> 9 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_10(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x400)|value<<10) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_10() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x400) >> 10 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_11(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x800)|value<<11) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_11() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x800) >> 11 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_12(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x1000)|value<<12) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_12() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x1000) >> 12 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_13(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x2000)|value<<13) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_13() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x2000) >> 13 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_14(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x4000)|value<<14) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_14() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x4000) >> 14 +} +func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_15(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x8000)|value<<15) +} +func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_15() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x8000) >> 15 +} +func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_0(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_0() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x10000) >> 16 +} +func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_1(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x20000)|value<<17) +} +func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_1() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x20000) >> 17 +} +func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_2(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x40000)|value<<18) +} +func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_2() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x40000) >> 18 +} +func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_3(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x80000)|value<<19) +} +func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_3() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x80000) >> 19 +} +func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_4(value uint32) { + volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x100000)|value<<20) +} +func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_4() uint32 { + return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x100000) >> 20 +} + +// DSI_HOST.INT_ST1: NA +func (o *DSI_HOST_Type) SetINT_ST1_TO_HS_TX(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetINT_ST1_TO_HS_TX() uint32 { + return volatile.LoadUint32(&o.INT_ST1.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetINT_ST1_TO_LP_RX(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetINT_ST1_TO_LP_RX() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetINT_ST1_ECC_SINGLE_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetINT_ST1_ECC_SINGLE_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetINT_ST1_ECC_MILTI_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetINT_ST1_ECC_MILTI_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetINT_ST1_CRC_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetINT_ST1_CRC_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetINT_ST1_PKT_SIZE_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetINT_ST1_PKT_SIZE_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetINT_ST1_EOPT_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x40)|value<<6) +} +func (o *DSI_HOST_Type) GetINT_ST1_EOPT_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x40) >> 6 +} +func (o *DSI_HOST_Type) SetINT_ST1_DPI_PLD_WR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x80)|value<<7) +} +func (o *DSI_HOST_Type) GetINT_ST1_DPI_PLD_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x80) >> 7 +} +func (o *DSI_HOST_Type) SetINT_ST1_GEN_CMD_WR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetINT_ST1_GEN_CMD_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetINT_ST1_GEN_PLD_WR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x200)|value<<9) +} +func (o *DSI_HOST_Type) GetINT_ST1_GEN_PLD_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x200) >> 9 +} +func (o *DSI_HOST_Type) SetINT_ST1_GEN_PLD_SEND_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x400)|value<<10) +} +func (o *DSI_HOST_Type) GetINT_ST1_GEN_PLD_SEND_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x400) >> 10 +} +func (o *DSI_HOST_Type) SetINT_ST1_GEN_PLD_RD_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x800)|value<<11) +} +func (o *DSI_HOST_Type) GetINT_ST1_GEN_PLD_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x800) >> 11 +} +func (o *DSI_HOST_Type) SetINT_ST1_GEN_PLD_RECEV_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x1000)|value<<12) +} +func (o *DSI_HOST_Type) GetINT_ST1_GEN_PLD_RECEV_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x1000) >> 12 +} +func (o *DSI_HOST_Type) SetINT_ST1_DPI_BUFF_PLD_UNDER(value uint32) { + volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x80000)|value<<19) +} +func (o *DSI_HOST_Type) GetINT_ST1_DPI_BUFF_PLD_UNDER() uint32 { + return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x80000) >> 19 +} + +// DSI_HOST.INT_MSK0: NA +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_0(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_0() uint32 { + return volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_1(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_2(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_2() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_3(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_3() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_4(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_4() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_5(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_5() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_6(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x40)|value<<6) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_6() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x40) >> 6 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_7(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x80)|value<<7) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_7() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x80) >> 7 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_8(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_8() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_9(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x200)|value<<9) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_9() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x200) >> 9 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_10(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x400)|value<<10) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_10() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x400) >> 10 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_11(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x800)|value<<11) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_11() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x800) >> 11 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_12(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x1000)|value<<12) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_12() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x1000) >> 12 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_13(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x2000)|value<<13) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_13() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x2000) >> 13 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_14(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x4000)|value<<14) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_14() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x4000) >> 14 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_15(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x8000)|value<<15) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_15() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x8000) >> 15 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_0(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_0() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x10000) >> 16 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_1(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x20000)|value<<17) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_1() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x20000) >> 17 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_2(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x40000)|value<<18) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_2() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x40000) >> 18 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_3(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x80000)|value<<19) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_3() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x80000) >> 19 +} +func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_4(value uint32) { + volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x100000)|value<<20) +} +func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_4() uint32 { + return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x100000) >> 20 +} + +// DSI_HOST.INT_MSK1: NA +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_TO_HS_TX(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_TO_HS_TX() uint32 { + return volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_TO_LP_RX(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_TO_LP_RX() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_ECC_SINGLE_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_ECC_SINGLE_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_ECC_MILTI_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_ECC_MILTI_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_CRC_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_CRC_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_PKT_SIZE_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_PKT_SIZE_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_EOPT_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x40)|value<<6) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_EOPT_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x40) >> 6 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_DPI_PLD_WR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x80)|value<<7) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_DPI_PLD_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x80) >> 7 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_CMD_WR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_CMD_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_PLD_WR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x200)|value<<9) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_PLD_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x200) >> 9 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_PLD_SEND_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x400)|value<<10) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_PLD_SEND_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x400) >> 10 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_PLD_RD_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x800)|value<<11) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_PLD_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x800) >> 11 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_PLD_RECEV_ERR(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x1000)|value<<12) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_PLD_RECEV_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x1000) >> 12 +} +func (o *DSI_HOST_Type) SetINT_MSK1_MASK_DPI_BUFF_PLD_UNDER(value uint32) { + volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x80000)|value<<19) +} +func (o *DSI_HOST_Type) GetINT_MSK1_MASK_DPI_BUFF_PLD_UNDER() uint32 { + return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x80000) >> 19 +} + +// DSI_HOST.PHY_CAL: NA +func (o *DSI_HOST_Type) SetPHY_CAL_TXSKEWCALHS(value uint32) { + volatile.StoreUint32(&o.PHY_CAL.Reg, volatile.LoadUint32(&o.PHY_CAL.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetPHY_CAL_TXSKEWCALHS() uint32 { + return volatile.LoadUint32(&o.PHY_CAL.Reg) & 0x1 +} + +// DSI_HOST.INT_FORCE0: NA +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_0() uint32 { + return volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_2(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_2() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_3(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_3() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_4(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_4() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_5(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_5() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_6(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x40)|value<<6) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_6() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x40) >> 6 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_7(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x80)|value<<7) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_7() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x80) >> 7 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_8(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_8() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_9(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x200)|value<<9) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_9() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x200) >> 9 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_10(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x400)|value<<10) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_10() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x400) >> 10 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_11(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x800)|value<<11) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_11() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x800) >> 11 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_12(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x1000)|value<<12) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_12() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x1000) >> 12 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_13(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x2000)|value<<13) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_13() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x2000) >> 13 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_14(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x4000)|value<<14) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_14() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x4000) >> 14 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_15(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x8000)|value<<15) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_15() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x8000) >> 15 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_0(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_0() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x10000) >> 16 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_1(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x20000)|value<<17) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_1() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x20000) >> 17 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_2(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x40000)|value<<18) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_2() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x40000) >> 18 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_3(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x80000)|value<<19) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_3() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x80000) >> 19 +} +func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_4(value uint32) { + volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x100000)|value<<20) +} +func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_4() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x100000) >> 20 +} + +// DSI_HOST.INT_FORCE1: NA +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_TO_HS_TX(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_TO_HS_TX() uint32 { + return volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_TO_LP_RX(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_TO_LP_RX() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_ECC_SINGLE_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_ECC_SINGLE_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_ECC_MILTI_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_ECC_MILTI_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_CRC_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_CRC_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_PKT_SIZE_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_PKT_SIZE_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_EOPT_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x40)|value<<6) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_EOPT_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x40) >> 6 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_DPI_PLD_WR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x80)|value<<7) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_DPI_PLD_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x80) >> 7 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_CMD_WR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_CMD_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_PLD_WR_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x200)|value<<9) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_PLD_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x200) >> 9 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_PLD_SEND_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x400)|value<<10) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_PLD_SEND_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x400) >> 10 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_PLD_RD_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x800)|value<<11) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_PLD_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x800) >> 11 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_PLD_RECEV_ERR(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x1000)|value<<12) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_PLD_RECEV_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x1000) >> 12 +} +func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER(value uint32) { + volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x80000)|value<<19) +} +func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER() uint32 { + return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x80000) >> 19 +} + +// DSI_HOST.DSC_PARAMETER: NA +func (o *DSI_HOST_Type) SetDSC_PARAMETER_COMPRESSION_MODE(value uint32) { + volatile.StoreUint32(&o.DSC_PARAMETER.Reg, volatile.LoadUint32(&o.DSC_PARAMETER.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetDSC_PARAMETER_COMPRESSION_MODE() uint32 { + return volatile.LoadUint32(&o.DSC_PARAMETER.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetDSC_PARAMETER_COMPRESS_ALGO(value uint32) { + volatile.StoreUint32(&o.DSC_PARAMETER.Reg, volatile.LoadUint32(&o.DSC_PARAMETER.Reg)&^(0x300)|value<<8) +} +func (o *DSI_HOST_Type) GetDSC_PARAMETER_COMPRESS_ALGO() uint32 { + return (volatile.LoadUint32(&o.DSC_PARAMETER.Reg) & 0x300) >> 8 +} +func (o *DSI_HOST_Type) SetDSC_PARAMETER_PPS_SEL(value uint32) { + volatile.StoreUint32(&o.DSC_PARAMETER.Reg, volatile.LoadUint32(&o.DSC_PARAMETER.Reg)&^(0x30000)|value<<16) +} +func (o *DSI_HOST_Type) GetDSC_PARAMETER_PPS_SEL() uint32 { + return (volatile.LoadUint32(&o.DSC_PARAMETER.Reg) & 0x30000) >> 16 +} + +// DSI_HOST.PHY_TMR_RD_CFG: NA +func (o *DSI_HOST_Type) SetPHY_TMR_RD_CFG_MAX_RD_TIME(value uint32) { + volatile.StoreUint32(&o.PHY_TMR_RD_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_RD_CFG.Reg)&^(0x7fff)|value) +} +func (o *DSI_HOST_Type) GetPHY_TMR_RD_CFG_MAX_RD_TIME() uint32 { + return volatile.LoadUint32(&o.PHY_TMR_RD_CFG.Reg) & 0x7fff +} + +// DSI_HOST.VID_SHADOW_CTRL: NA +func (o *DSI_HOST_Type) SetVID_SHADOW_CTRL_VID_SHADOW_EN(value uint32) { + volatile.StoreUint32(&o.VID_SHADOW_CTRL.Reg, volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetVID_SHADOW_CTRL_VID_SHADOW_EN() uint32 { + return volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetVID_SHADOW_CTRL_VID_SHADOW_REQ(value uint32) { + volatile.StoreUint32(&o.VID_SHADOW_CTRL.Reg, volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetVID_SHADOW_CTRL_VID_SHADOW_REQ() uint32 { + return (volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetVID_SHADOW_CTRL_VID_SHADOW_PIN_REQ(value uint32) { + volatile.StoreUint32(&o.VID_SHADOW_CTRL.Reg, volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetVID_SHADOW_CTRL_VID_SHADOW_PIN_REQ() uint32 { + return (volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg) & 0x10000) >> 16 +} + +// DSI_HOST.DPI_VCID_ACT: NA +func (o *DSI_HOST_Type) SetDPI_VCID_ACT(value uint32) { + volatile.StoreUint32(&o.DPI_VCID_ACT.Reg, volatile.LoadUint32(&o.DPI_VCID_ACT.Reg)&^(0x3)|value) +} +func (o *DSI_HOST_Type) GetDPI_VCID_ACT() uint32 { + return volatile.LoadUint32(&o.DPI_VCID_ACT.Reg) & 0x3 +} + +// DSI_HOST.DPI_COLOR_CODING_ACT: NA +func (o *DSI_HOST_Type) SetDPI_COLOR_CODING_ACT(value uint32) { + volatile.StoreUint32(&o.DPI_COLOR_CODING_ACT.Reg, volatile.LoadUint32(&o.DPI_COLOR_CODING_ACT.Reg)&^(0xf)|value) +} +func (o *DSI_HOST_Type) GetDPI_COLOR_CODING_ACT() uint32 { + return volatile.LoadUint32(&o.DPI_COLOR_CODING_ACT.Reg) & 0xf +} +func (o *DSI_HOST_Type) SetDPI_COLOR_CODING_ACT_LOOSELY18_EN_ACT(value uint32) { + volatile.StoreUint32(&o.DPI_COLOR_CODING_ACT.Reg, volatile.LoadUint32(&o.DPI_COLOR_CODING_ACT.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetDPI_COLOR_CODING_ACT_LOOSELY18_EN_ACT() uint32 { + return (volatile.LoadUint32(&o.DPI_COLOR_CODING_ACT.Reg) & 0x100) >> 8 +} + +// DSI_HOST.DPI_LP_CMD_TIM_ACT: NA +func (o *DSI_HOST_Type) SetDPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_ACT(value uint32) { + volatile.StoreUint32(&o.DPI_LP_CMD_TIM_ACT.Reg, volatile.LoadUint32(&o.DPI_LP_CMD_TIM_ACT.Reg)&^(0xff)|value) +} +func (o *DSI_HOST_Type) GetDPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_ACT() uint32 { + return volatile.LoadUint32(&o.DPI_LP_CMD_TIM_ACT.Reg) & 0xff +} +func (o *DSI_HOST_Type) SetDPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_ACT(value uint32) { + volatile.StoreUint32(&o.DPI_LP_CMD_TIM_ACT.Reg, volatile.LoadUint32(&o.DPI_LP_CMD_TIM_ACT.Reg)&^(0xff0000)|value<<16) +} +func (o *DSI_HOST_Type) GetDPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_ACT() uint32 { + return (volatile.LoadUint32(&o.DPI_LP_CMD_TIM_ACT.Reg) & 0xff0000) >> 16 +} + +// DSI_HOST.EDPI_TE_HW_CFG: NA +func (o *DSI_HOST_Type) SetEDPI_TE_HW_CFG_HW_TEAR_EFFECT_ON(value uint32) { + volatile.StoreUint32(&o.EDPI_TE_HW_CFG.Reg, volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetEDPI_TE_HW_CFG_HW_TEAR_EFFECT_ON() uint32 { + return volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetEDPI_TE_HW_CFG_HW_TEAR_EFFECT_GEN(value uint32) { + volatile.StoreUint32(&o.EDPI_TE_HW_CFG.Reg, volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetEDPI_TE_HW_CFG_HW_TEAR_EFFECT_GEN() uint32 { + return (volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetEDPI_TE_HW_CFG_HW_SET_SCAN_LINE(value uint32) { + volatile.StoreUint32(&o.EDPI_TE_HW_CFG.Reg, volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetEDPI_TE_HW_CFG_HW_SET_SCAN_LINE() uint32 { + return (volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetEDPI_TE_HW_CFG_SCAN_LINE_PARAMETER(value uint32) { + volatile.StoreUint32(&o.EDPI_TE_HW_CFG.Reg, volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg)&^(0xffff0000)|value<<16) +} +func (o *DSI_HOST_Type) GetEDPI_TE_HW_CFG_SCAN_LINE_PARAMETER() uint32 { + return (volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg) & 0xffff0000) >> 16 +} + +// DSI_HOST.VID_MODE_CFG_ACT: NA +func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_VID_MODE_TYPE_ACT(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x3)|value) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_VID_MODE_TYPE_ACT() uint32 { + return volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x3 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_VSA_EN_ACT(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_VSA_EN_ACT() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_VBP_EN_ACT(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_VBP_EN_ACT() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_VFP_EN_ACT(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_VFP_EN_ACT() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_VACT_EN_ACT(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_VACT_EN_ACT() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_HBP_EN_ACT(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x40)|value<<6) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_HBP_EN_ACT() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x40) >> 6 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_HFP_EN_ACT(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x80)|value<<7) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_HFP_EN_ACT() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x80) >> 7 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_ACT(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x100)|value<<8) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_ACT() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x100) >> 8 +} +func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_CMD_EN_ACT(value uint32) { + volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x200)|value<<9) +} +func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_CMD_EN_ACT() uint32 { + return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x200) >> 9 +} + +// DSI_HOST.VID_PKT_SIZE_ACT: NA +func (o *DSI_HOST_Type) SetVID_PKT_SIZE_ACT(value uint32) { + volatile.StoreUint32(&o.VID_PKT_SIZE_ACT.Reg, volatile.LoadUint32(&o.VID_PKT_SIZE_ACT.Reg)&^(0x3fff)|value) +} +func (o *DSI_HOST_Type) GetVID_PKT_SIZE_ACT() uint32 { + return volatile.LoadUint32(&o.VID_PKT_SIZE_ACT.Reg) & 0x3fff +} + +// DSI_HOST.VID_NUM_CHUNKS_ACT: NA +func (o *DSI_HOST_Type) SetVID_NUM_CHUNKS_ACT(value uint32) { + volatile.StoreUint32(&o.VID_NUM_CHUNKS_ACT.Reg, volatile.LoadUint32(&o.VID_NUM_CHUNKS_ACT.Reg)&^(0x1fff)|value) +} +func (o *DSI_HOST_Type) GetVID_NUM_CHUNKS_ACT() uint32 { + return volatile.LoadUint32(&o.VID_NUM_CHUNKS_ACT.Reg) & 0x1fff +} + +// DSI_HOST.VID_NULL_SIZE_ACT: NA +func (o *DSI_HOST_Type) SetVID_NULL_SIZE_ACT(value uint32) { + volatile.StoreUint32(&o.VID_NULL_SIZE_ACT.Reg, volatile.LoadUint32(&o.VID_NULL_SIZE_ACT.Reg)&^(0x1fff)|value) +} +func (o *DSI_HOST_Type) GetVID_NULL_SIZE_ACT() uint32 { + return volatile.LoadUint32(&o.VID_NULL_SIZE_ACT.Reg) & 0x1fff +} + +// DSI_HOST.VID_HSA_TIME_ACT: NA +func (o *DSI_HOST_Type) SetVID_HSA_TIME_ACT(value uint32) { + volatile.StoreUint32(&o.VID_HSA_TIME_ACT.Reg, volatile.LoadUint32(&o.VID_HSA_TIME_ACT.Reg)&^(0xfff)|value) +} +func (o *DSI_HOST_Type) GetVID_HSA_TIME_ACT() uint32 { + return volatile.LoadUint32(&o.VID_HSA_TIME_ACT.Reg) & 0xfff +} + +// DSI_HOST.VID_HBP_TIME_ACT: NA +func (o *DSI_HOST_Type) SetVID_HBP_TIME_ACT(value uint32) { + volatile.StoreUint32(&o.VID_HBP_TIME_ACT.Reg, volatile.LoadUint32(&o.VID_HBP_TIME_ACT.Reg)&^(0xfff)|value) +} +func (o *DSI_HOST_Type) GetVID_HBP_TIME_ACT() uint32 { + return volatile.LoadUint32(&o.VID_HBP_TIME_ACT.Reg) & 0xfff +} + +// DSI_HOST.VID_HLINE_TIME_ACT: NA +func (o *DSI_HOST_Type) SetVID_HLINE_TIME_ACT(value uint32) { + volatile.StoreUint32(&o.VID_HLINE_TIME_ACT.Reg, volatile.LoadUint32(&o.VID_HLINE_TIME_ACT.Reg)&^(0x7fff)|value) +} +func (o *DSI_HOST_Type) GetVID_HLINE_TIME_ACT() uint32 { + return volatile.LoadUint32(&o.VID_HLINE_TIME_ACT.Reg) & 0x7fff +} + +// DSI_HOST.VID_VSA_LINES_ACT: NA +func (o *DSI_HOST_Type) SetVID_VSA_LINES_ACT_VSA_LINES_ACT(value uint32) { + volatile.StoreUint32(&o.VID_VSA_LINES_ACT.Reg, volatile.LoadUint32(&o.VID_VSA_LINES_ACT.Reg)&^(0x3ff)|value) +} +func (o *DSI_HOST_Type) GetVID_VSA_LINES_ACT_VSA_LINES_ACT() uint32 { + return volatile.LoadUint32(&o.VID_VSA_LINES_ACT.Reg) & 0x3ff +} + +// DSI_HOST.VID_VBP_LINES_ACT: NA +func (o *DSI_HOST_Type) SetVID_VBP_LINES_ACT_VBP_LINES_ACT(value uint32) { + volatile.StoreUint32(&o.VID_VBP_LINES_ACT.Reg, volatile.LoadUint32(&o.VID_VBP_LINES_ACT.Reg)&^(0x3ff)|value) +} +func (o *DSI_HOST_Type) GetVID_VBP_LINES_ACT_VBP_LINES_ACT() uint32 { + return volatile.LoadUint32(&o.VID_VBP_LINES_ACT.Reg) & 0x3ff +} + +// DSI_HOST.VID_VFP_LINES_ACT: NA +func (o *DSI_HOST_Type) SetVID_VFP_LINES_ACT_VFP_LINES_ACT(value uint32) { + volatile.StoreUint32(&o.VID_VFP_LINES_ACT.Reg, volatile.LoadUint32(&o.VID_VFP_LINES_ACT.Reg)&^(0x3ff)|value) +} +func (o *DSI_HOST_Type) GetVID_VFP_LINES_ACT_VFP_LINES_ACT() uint32 { + return volatile.LoadUint32(&o.VID_VFP_LINES_ACT.Reg) & 0x3ff +} + +// DSI_HOST.VID_VACTIVE_LINES_ACT: NA +func (o *DSI_HOST_Type) SetVID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_ACT(value uint32) { + volatile.StoreUint32(&o.VID_VACTIVE_LINES_ACT.Reg, volatile.LoadUint32(&o.VID_VACTIVE_LINES_ACT.Reg)&^(0x3fff)|value) +} +func (o *DSI_HOST_Type) GetVID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_ACT() uint32 { + return volatile.LoadUint32(&o.VID_VACTIVE_LINES_ACT.Reg) & 0x3fff +} + +// DSI_HOST.VID_PKT_STATUS: NA +func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_CMD_W_EMPTY(value uint32) { + volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x1)|value) +} +func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_CMD_W_EMPTY() uint32 { + return volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x1 +} +func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_CMD_W_FULL(value uint32) { + volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_CMD_W_FULL() uint32 { + return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x2) >> 1 +} +func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_PLD_W_EMPTY(value uint32) { + volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_PLD_W_EMPTY() uint32 { + return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x4) >> 2 +} +func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_PLD_W_FULL(value uint32) { + volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_PLD_W_FULL() uint32 { + return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x8) >> 3 +} +func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_BUFF_PLD_EMPTY(value uint32) { + volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_BUFF_PLD_EMPTY() uint32 { + return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x10000) >> 16 +} +func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_BUFF_PLD_FULL(value uint32) { + volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_BUFF_PLD_FULL() uint32 { + return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x20000) >> 17 +} + +// DSI_HOST.SDF_3D_ACT: NA +func (o *DSI_HOST_Type) SetSDF_3D_ACT_MODE_3D_ACT(value uint32) { + volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0x3)|value) +} +func (o *DSI_HOST_Type) GetSDF_3D_ACT_MODE_3D_ACT() uint32 { + return volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0x3 +} +func (o *DSI_HOST_Type) SetSDF_3D_ACT_FORMAT_3D_ACT(value uint32) { + volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0xc)|value<<2) +} +func (o *DSI_HOST_Type) GetSDF_3D_ACT_FORMAT_3D_ACT() uint32 { + return (volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0xc) >> 2 +} +func (o *DSI_HOST_Type) SetSDF_3D_ACT_SECOND_VSYNC_ACT(value uint32) { + volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0x10)|value<<4) +} +func (o *DSI_HOST_Type) GetSDF_3D_ACT_SECOND_VSYNC_ACT() uint32 { + return (volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0x10) >> 4 +} +func (o *DSI_HOST_Type) SetSDF_3D_ACT_RIGHT_FIRST_ACT(value uint32) { + volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0x20)|value<<5) +} +func (o *DSI_HOST_Type) GetSDF_3D_ACT_RIGHT_FIRST_ACT() uint32 { + return (volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0x20) >> 5 +} +func (o *DSI_HOST_Type) SetSDF_3D_ACT_SEND_3D_CFG_ACT(value uint32) { + volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0x10000)|value<<16) +} +func (o *DSI_HOST_Type) GetSDF_3D_ACT_SEND_3D_CFG_ACT() uint32 { + return (volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0x10000) >> 16 +} + +// ECC (ECC Hardware Accelerator) +type ECC_Type struct { + _ [12]byte + MULT_INT_RAW volatile.Register32 // 0xC + MULT_INT_ST volatile.Register32 // 0x10 + MULT_INT_ENA volatile.Register32 // 0x14 + MULT_INT_CLR volatile.Register32 // 0x18 + MULT_CONF volatile.Register32 // 0x1C + _ [220]byte + MULT_DATE volatile.Register32 // 0xFC + K_MEM [8]volatile.Register32 // 0x100 + PX_MEM [8]volatile.Register32 // 0x120 + PY_MEM [8]volatile.Register32 // 0x140 +} + +// ECC.MULT_INT_RAW: ECC interrupt raw register, valid in level. +func (o *ECC_Type) SetMULT_INT_RAW_CALC_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.MULT_INT_RAW.Reg, volatile.LoadUint32(&o.MULT_INT_RAW.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_RAW_CALC_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.MULT_INT_RAW.Reg) & 0x1 +} + +// ECC.MULT_INT_ST: ECC interrupt status register. +func (o *ECC_Type) SetMULT_INT_ST_CALC_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.MULT_INT_ST.Reg, volatile.LoadUint32(&o.MULT_INT_ST.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_ST_CALC_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.MULT_INT_ST.Reg) & 0x1 +} + +// ECC.MULT_INT_ENA: ECC interrupt enable register. +func (o *ECC_Type) SetMULT_INT_ENA_CALC_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.MULT_INT_ENA.Reg, volatile.LoadUint32(&o.MULT_INT_ENA.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_ENA_CALC_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.MULT_INT_ENA.Reg) & 0x1 +} + +// ECC.MULT_INT_CLR: ECC interrupt clear register. +func (o *ECC_Type) SetMULT_INT_CLR_CALC_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.MULT_INT_CLR.Reg, volatile.LoadUint32(&o.MULT_INT_CLR.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_INT_CLR_CALC_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.MULT_INT_CLR.Reg) & 0x1 +} + +// ECC.MULT_CONF: ECC configure register +func (o *ECC_Type) SetMULT_CONF_START(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x1)|value) +} +func (o *ECC_Type) GetMULT_CONF_START() uint32 { + return volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x1 +} +func (o *ECC_Type) SetMULT_CONF_RESET(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *ECC_Type) GetMULT_CONF_RESET() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x2) >> 1 +} +func (o *ECC_Type) SetMULT_CONF_KEY_LENGTH(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x4)|value<<2) +} +func (o *ECC_Type) GetMULT_CONF_KEY_LENGTH() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x4) >> 2 +} +func (o *ECC_Type) SetMULT_CONF_MOD_BASE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x8)|value<<3) +} +func (o *ECC_Type) GetMULT_CONF_MOD_BASE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x8) >> 3 +} +func (o *ECC_Type) SetMULT_CONF_WORK_MODE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *ECC_Type) GetMULT_CONF_WORK_MODE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0xf0) >> 4 +} +func (o *ECC_Type) SetMULT_CONF_SECURITY_MODE(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x100)|value<<8) +} +func (o *ECC_Type) GetMULT_CONF_SECURITY_MODE() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x100) >> 8 +} +func (o *ECC_Type) SetMULT_CONF_VERIFICATION_RESULT(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *ECC_Type) GetMULT_CONF_VERIFICATION_RESULT() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x20000000) >> 29 +} +func (o *ECC_Type) SetMULT_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *ECC_Type) GetMULT_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x40000000) >> 30 +} +func (o *ECC_Type) SetMULT_CONF_MEM_CLOCK_GATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *ECC_Type) GetMULT_CONF_MEM_CLOCK_GATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x80000000) >> 31 +} + +// ECC.MULT_DATE: Version control register +func (o *ECC_Type) SetMULT_DATE_DATE(value uint32) { + volatile.StoreUint32(&o.MULT_DATE.Reg, volatile.LoadUint32(&o.MULT_DATE.Reg)&^(0xfffffff)|value) +} +func (o *ECC_Type) GetMULT_DATE_DATE() uint32 { + return volatile.LoadUint32(&o.MULT_DATE.Reg) & 0xfffffff +} + +// ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator +type ECDSA_Type struct { + _ [4]byte + CONF volatile.Register32 // 0x4 + CLK volatile.Register32 // 0x8 + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + START volatile.Register32 // 0x1C + STATE volatile.Register32 // 0x20 + RESULT volatile.Register32 // 0x24 + _ [212]byte + DATE volatile.Register32 // 0xFC + _ [256]byte + SHA_MODE volatile.Register32 // 0x200 + _ [12]byte + SHA_START volatile.Register32 // 0x210 + SHA_CONTINUE volatile.Register32 // 0x214 + SHA_BUSY volatile.Register32 // 0x218 + _ [100]byte + MESSAGE_MEM [8]volatile.Register32 // 0x280 + _ [1888]byte + R_MEM [8]volatile.Register32 // 0xA00 + S_MEM [8]volatile.Register32 // 0xA20 + Z_MEM [8]volatile.Register32 // 0xA40 + QAX_MEM [8]volatile.Register32 // 0xA60 + QAY_MEM [8]volatile.Register32 // 0xA80 +} + +// ECDSA.CONF: ECDSA configure register +func (o *ECDSA_Type) SetCONF_WORK_MODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value) +} +func (o *ECDSA_Type) GetCONF_WORK_MODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x3 +} +func (o *ECDSA_Type) SetCONF_ECC_CURVE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2) +} +func (o *ECDSA_Type) GetCONF_ECC_CURVE() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2 +} +func (o *ECDSA_Type) SetCONF_SOFTWARE_SET_K(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3) +} +func (o *ECDSA_Type) GetCONF_SOFTWARE_SET_K() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3 +} +func (o *ECDSA_Type) SetCONF_SOFTWARE_SET_Z(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4) +} +func (o *ECDSA_Type) GetCONF_SOFTWARE_SET_Z() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4 +} +func (o *ECDSA_Type) SetCONF_DETERMINISTIC_K(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5) +} +func (o *ECDSA_Type) GetCONF_DETERMINISTIC_K() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5 +} +func (o *ECDSA_Type) SetCONF_DETERMINISTIC_LOOP(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3fffc0)|value<<6) +} +func (o *ECDSA_Type) GetCONF_DETERMINISTIC_LOOP() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x3fffc0) >> 6 +} + +// ECDSA.CLK: ECDSA clock gate register +func (o *ECDSA_Type) SetCLK_GATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetCLK_GATE_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} + +// ECDSA.INT_RAW: ECDSA interrupt raw register, valid in level. +func (o *ECDSA_Type) SetINT_RAW_CALC_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetINT_RAW_CALC_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *ECDSA_Type) SetINT_RAW_SHA_RELEASE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *ECDSA_Type) GetINT_RAW_SHA_RELEASE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// ECDSA.INT_ST: ECDSA interrupt status register. +func (o *ECDSA_Type) SetINT_ST_CALC_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetINT_ST_CALC_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *ECDSA_Type) SetINT_ST_SHA_RELEASE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *ECDSA_Type) GetINT_ST_SHA_RELEASE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// ECDSA.INT_ENA: ECDSA interrupt enable register. +func (o *ECDSA_Type) SetINT_ENA_CALC_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetINT_ENA_CALC_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *ECDSA_Type) SetINT_ENA_SHA_RELEASE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ECDSA_Type) GetINT_ENA_SHA_RELEASE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// ECDSA.INT_CLR: ECDSA interrupt clear register. +func (o *ECDSA_Type) SetINT_CLR_CALC_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetINT_CLR_CALC_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *ECDSA_Type) SetINT_CLR_SHA_RELEASE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *ECDSA_Type) GetINT_CLR_SHA_RELEASE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// ECDSA.START: ECDSA start register +func (o *ECDSA_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetSTART() uint32 { + return volatile.LoadUint32(&o.START.Reg) & 0x1 +} +func (o *ECDSA_Type) SetSTART_LOAD_DONE(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x2)|value<<1) +} +func (o *ECDSA_Type) GetSTART_LOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.START.Reg) & 0x2) >> 1 +} +func (o *ECDSA_Type) SetSTART_GET_DONE(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x4)|value<<2) +} +func (o *ECDSA_Type) GetSTART_GET_DONE() uint32 { + return (volatile.LoadUint32(&o.START.Reg) & 0x4) >> 2 +} + +// ECDSA.STATE: ECDSA status register +func (o *ECDSA_Type) SetSTATE_BUSY(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *ECDSA_Type) GetSTATE_BUSY() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// ECDSA.RESULT: ECDSA result register +func (o *ECDSA_Type) SetRESULT_OPERATION_RESULT(value uint32) { + volatile.StoreUint32(&o.RESULT.Reg, volatile.LoadUint32(&o.RESULT.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetRESULT_OPERATION_RESULT() uint32 { + return volatile.LoadUint32(&o.RESULT.Reg) & 0x1 +} +func (o *ECDSA_Type) SetRESULT_K_VALUE_WARNING(value uint32) { + volatile.StoreUint32(&o.RESULT.Reg, volatile.LoadUint32(&o.RESULT.Reg)&^(0x2)|value<<1) +} +func (o *ECDSA_Type) GetRESULT_K_VALUE_WARNING() uint32 { + return (volatile.LoadUint32(&o.RESULT.Reg) & 0x2) >> 1 +} + +// ECDSA.DATE: Version control register +func (o *ECDSA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *ECDSA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// ECDSA.SHA_MODE: ECDSA control SHA register +func (o *ECDSA_Type) SetSHA_MODE(value uint32) { + volatile.StoreUint32(&o.SHA_MODE.Reg, volatile.LoadUint32(&o.SHA_MODE.Reg)&^(0x7)|value) +} +func (o *ECDSA_Type) GetSHA_MODE() uint32 { + return volatile.LoadUint32(&o.SHA_MODE.Reg) & 0x7 +} + +// ECDSA.SHA_START: ECDSA control SHA register +func (o *ECDSA_Type) SetSHA_START(value uint32) { + volatile.StoreUint32(&o.SHA_START.Reg, volatile.LoadUint32(&o.SHA_START.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetSHA_START() uint32 { + return volatile.LoadUint32(&o.SHA_START.Reg) & 0x1 +} + +// ECDSA.SHA_CONTINUE: ECDSA control SHA register +func (o *ECDSA_Type) SetSHA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.SHA_CONTINUE.Reg, volatile.LoadUint32(&o.SHA_CONTINUE.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetSHA_CONTINUE() uint32 { + return volatile.LoadUint32(&o.SHA_CONTINUE.Reg) & 0x1 +} + +// ECDSA.SHA_BUSY: ECDSA status register +func (o *ECDSA_Type) SetSHA_BUSY(value uint32) { + volatile.StoreUint32(&o.SHA_BUSY.Reg, volatile.LoadUint32(&o.SHA_BUSY.Reg)&^(0x1)|value) +} +func (o *ECDSA_Type) GetSHA_BUSY() uint32 { + return volatile.LoadUint32(&o.SHA_BUSY.Reg) & 0x1 +} + +// eFuse Controller +type EFUSE_Type struct { + PGM_DATA0 volatile.Register32 // 0x0 + PGM_DATA1 volatile.Register32 // 0x4 + PGM_DATA2 volatile.Register32 // 0x8 + PGM_DATA3 volatile.Register32 // 0xC + PGM_DATA4 volatile.Register32 // 0x10 + PGM_DATA5 volatile.Register32 // 0x14 + PGM_DATA6 volatile.Register32 // 0x18 + PGM_DATA7 volatile.Register32 // 0x1C + PGM_CHECK_VALUE0 volatile.Register32 // 0x20 + PGM_CHECK_VALUE1 volatile.Register32 // 0x24 + PGM_CHECK_VALUE2 volatile.Register32 // 0x28 + RD_WR_DIS volatile.Register32 // 0x2C + RD_REPEAT_DATA0 volatile.Register32 // 0x30 + RD_REPEAT_DATA1 volatile.Register32 // 0x34 + RD_REPEAT_DATA2 volatile.Register32 // 0x38 + RD_REPEAT_DATA3 volatile.Register32 // 0x3C + RD_REPEAT_DATA4 volatile.Register32 // 0x40 + RD_MAC_SYS_0 volatile.Register32 // 0x44 + RD_MAC_SYS_1 volatile.Register32 // 0x48 + RD_MAC_SYS_2 volatile.Register32 // 0x4C + RD_MAC_SYS_3 volatile.Register32 // 0x50 + RD_MAC_SYS_4 volatile.Register32 // 0x54 + RD_MAC_SYS_5 volatile.Register32 // 0x58 + RD_SYS_PART1_DATA0 volatile.Register32 // 0x5C + RD_SYS_PART1_DATA1 volatile.Register32 // 0x60 + RD_SYS_PART1_DATA2 volatile.Register32 // 0x64 + RD_SYS_PART1_DATA3 volatile.Register32 // 0x68 + RD_SYS_PART1_DATA4 volatile.Register32 // 0x6C + RD_SYS_PART1_DATA5 volatile.Register32 // 0x70 + RD_SYS_PART1_DATA6 volatile.Register32 // 0x74 + RD_SYS_PART1_DATA7 volatile.Register32 // 0x78 + RD_USR_DATA0 volatile.Register32 // 0x7C + RD_USR_DATA1 volatile.Register32 // 0x80 + RD_USR_DATA2 volatile.Register32 // 0x84 + RD_USR_DATA3 volatile.Register32 // 0x88 + RD_USR_DATA4 volatile.Register32 // 0x8C + RD_USR_DATA5 volatile.Register32 // 0x90 + RD_USR_DATA6 volatile.Register32 // 0x94 + RD_USR_DATA7 volatile.Register32 // 0x98 + RD_KEY0_DATA0 volatile.Register32 // 0x9C + RD_KEY0_DATA1 volatile.Register32 // 0xA0 + RD_KEY0_DATA2 volatile.Register32 // 0xA4 + RD_KEY0_DATA3 volatile.Register32 // 0xA8 + RD_KEY0_DATA4 volatile.Register32 // 0xAC + RD_KEY0_DATA5 volatile.Register32 // 0xB0 + RD_KEY0_DATA6 volatile.Register32 // 0xB4 + RD_KEY0_DATA7 volatile.Register32 // 0xB8 + RD_KEY1_DATA0 volatile.Register32 // 0xBC + RD_KEY1_DATA1 volatile.Register32 // 0xC0 + RD_KEY1_DATA2 volatile.Register32 // 0xC4 + RD_KEY1_DATA3 volatile.Register32 // 0xC8 + RD_KEY1_DATA4 volatile.Register32 // 0xCC + RD_KEY1_DATA5 volatile.Register32 // 0xD0 + RD_KEY1_DATA6 volatile.Register32 // 0xD4 + RD_KEY1_DATA7 volatile.Register32 // 0xD8 + RD_KEY2_DATA0 volatile.Register32 // 0xDC + RD_KEY2_DATA1 volatile.Register32 // 0xE0 + RD_KEY2_DATA2 volatile.Register32 // 0xE4 + RD_KEY2_DATA3 volatile.Register32 // 0xE8 + RD_KEY2_DATA4 volatile.Register32 // 0xEC + RD_KEY2_DATA5 volatile.Register32 // 0xF0 + RD_KEY2_DATA6 volatile.Register32 // 0xF4 + RD_KEY2_DATA7 volatile.Register32 // 0xF8 + RD_KEY3_DATA0 volatile.Register32 // 0xFC + RD_KEY3_DATA1 volatile.Register32 // 0x100 + RD_KEY3_DATA2 volatile.Register32 // 0x104 + RD_KEY3_DATA3 volatile.Register32 // 0x108 + RD_KEY3_DATA4 volatile.Register32 // 0x10C + RD_KEY3_DATA5 volatile.Register32 // 0x110 + RD_KEY3_DATA6 volatile.Register32 // 0x114 + RD_KEY3_DATA7 volatile.Register32 // 0x118 + RD_KEY4_DATA0 volatile.Register32 // 0x11C + RD_KEY4_DATA1 volatile.Register32 // 0x120 + RD_KEY4_DATA2 volatile.Register32 // 0x124 + RD_KEY4_DATA3 volatile.Register32 // 0x128 + RD_KEY4_DATA4 volatile.Register32 // 0x12C + RD_KEY4_DATA5 volatile.Register32 // 0x130 + RD_KEY4_DATA6 volatile.Register32 // 0x134 + RD_KEY4_DATA7 volatile.Register32 // 0x138 + RD_KEY5_DATA0 volatile.Register32 // 0x13C + RD_KEY5_DATA1 volatile.Register32 // 0x140 + RD_KEY5_DATA2 volatile.Register32 // 0x144 + RD_KEY5_DATA3 volatile.Register32 // 0x148 + RD_KEY5_DATA4 volatile.Register32 // 0x14C + RD_KEY5_DATA5 volatile.Register32 // 0x150 + RD_KEY5_DATA6 volatile.Register32 // 0x154 + RD_KEY5_DATA7 volatile.Register32 // 0x158 + RD_SYS_PART2_DATA0 volatile.Register32 // 0x15C + RD_SYS_PART2_DATA1 volatile.Register32 // 0x160 + RD_SYS_PART2_DATA2 volatile.Register32 // 0x164 + RD_SYS_PART2_DATA3 volatile.Register32 // 0x168 + RD_SYS_PART2_DATA4 volatile.Register32 // 0x16C + RD_SYS_PART2_DATA5 volatile.Register32 // 0x170 + RD_SYS_PART2_DATA6 volatile.Register32 // 0x174 + RD_SYS_PART2_DATA7 volatile.Register32 // 0x178 + RD_REPEAT_ERR0 volatile.Register32 // 0x17C + RD_REPEAT_ERR1 volatile.Register32 // 0x180 + RD_REPEAT_ERR2 volatile.Register32 // 0x184 + RD_REPEAT_ERR3 volatile.Register32 // 0x188 + RD_REPEAT_ERR4 volatile.Register32 // 0x18C + _ [48]byte + RD_RS_ERR0 volatile.Register32 // 0x1C0 + RD_RS_ERR1 volatile.Register32 // 0x1C4 + CLK volatile.Register32 // 0x1C8 + CONF volatile.Register32 // 0x1CC + STATUS volatile.Register32 // 0x1D0 + CMD volatile.Register32 // 0x1D4 + INT_RAW volatile.Register32 // 0x1D8 + INT_ST volatile.Register32 // 0x1DC + INT_ENA volatile.Register32 // 0x1E0 + INT_CLR volatile.Register32 // 0x1E4 + DAC_CONF volatile.Register32 // 0x1E8 + RD_TIM_CONF volatile.Register32 // 0x1EC + WR_TIM_CONF1 volatile.Register32 // 0x1F0 + WR_TIM_CONF2 volatile.Register32 // 0x1F4 + WR_TIM_CONF0_RS_BYPASS volatile.Register32 // 0x1F8 + DATE volatile.Register32 // 0x1FC + _ [1536]byte + APB2OTP_WR_DIS volatile.Register32 // 0x800 + APB2OTP_BLK0_BACKUP1_W1 volatile.Register32 // 0x804 + APB2OTP_BLK0_BACKUP1_W2 volatile.Register32 // 0x808 + APB2OTP_BLK0_BACKUP1_W3 volatile.Register32 // 0x80C + APB2OTP_BLK0_BACKUP1_W4 volatile.Register32 // 0x810 + APB2OTP_BLK0_BACKUP1_W5 volatile.Register32 // 0x814 + APB2OTP_BLK0_BACKUP2_W1 volatile.Register32 // 0x818 + APB2OTP_BLK0_BACKUP2_W2 volatile.Register32 // 0x81C + APB2OTP_BLK0_BACKUP2_W3 volatile.Register32 // 0x820 + APB2OTP_BLK0_BACKUP2_W4 volatile.Register32 // 0x824 + APB2OTP_BLK0_BACKUP2_W5 volatile.Register32 // 0x828 + APB2OTP_BLK0_BACKUP3_W1 volatile.Register32 // 0x82C + APB2OTP_BLK0_BACKUP3_W2 volatile.Register32 // 0x830 + APB2OTP_BLK0_BACKUP3_W3 volatile.Register32 // 0x834 + APB2OTP_BLK0_BACKUP3_W4 volatile.Register32 // 0x838 + APB2OTP_BLK0_BACKUP3_W5 volatile.Register32 // 0x83C + APB2OTP_BLK0_BACKUP4_W1 volatile.Register32 // 0x840 + APB2OTP_BLK0_BACKUP4_W2 volatile.Register32 // 0x844 + APB2OTP_BLK0_BACKUP4_W3 volatile.Register32 // 0x848 + APB2OTP_BLK0_BACKUP4_W4 volatile.Register32 // 0x84C + APB2OTP_BLK0_BACKUP4_W5 volatile.Register32 // 0x850 + APB2OTP_BLK1_W1 volatile.Register32 // 0x854 + APB2OTP_BLK1_W2 volatile.Register32 // 0x858 + APB2OTP_BLK1_W3 volatile.Register32 // 0x85C + APB2OTP_BLK1_W4 volatile.Register32 // 0x860 + APB2OTP_BLK1_W5 volatile.Register32 // 0x864 + APB2OTP_BLK1_W6 volatile.Register32 // 0x868 + APB2OTP_BLK1_W7 volatile.Register32 // 0x86C + APB2OTP_BLK1_W8 volatile.Register32 // 0x870 + APB2OTP_BLK1_W9 volatile.Register32 // 0x874 + APB2OTP_BLK2_W1 volatile.Register32 // 0x878 + APB2OTP_BLK2_W2 volatile.Register32 // 0x87C + APB2OTP_BLK2_W3 volatile.Register32 // 0x880 + APB2OTP_BLK2_W4 volatile.Register32 // 0x884 + APB2OTP_BLK2_W5 volatile.Register32 // 0x888 + APB2OTP_BLK2_W6 volatile.Register32 // 0x88C + APB2OTP_BLK2_W7 volatile.Register32 // 0x890 + APB2OTP_BLK2_W8 volatile.Register32 // 0x894 + APB2OTP_BLK2_W9 volatile.Register32 // 0x898 + APB2OTP_BLK2_W10 volatile.Register32 // 0x89C + APB2OTP_BLK2_W11 volatile.Register32 // 0x8A0 + APB2OTP_BLK3_W1 volatile.Register32 // 0x8A4 + APB2OTP_BLK3_W2 volatile.Register32 // 0x8A8 + APB2OTP_BLK3_W3 volatile.Register32 // 0x8AC + APB2OTP_BLK3_W4 volatile.Register32 // 0x8B0 + APB2OTP_BLK3_W5 volatile.Register32 // 0x8B4 + APB2OTP_BLK3_W6 volatile.Register32 // 0x8B8 + APB2OTP_BLK3_W7 volatile.Register32 // 0x8BC + APB2OTP_BLK3_W8 volatile.Register32 // 0x8C0 + APB2OTP_BLK3_W9 volatile.Register32 // 0x8C4 + APB2OTP_BLK3_W10 volatile.Register32 // 0x8C8 + APB2OTP_BLK3_W11 volatile.Register32 // 0x8CC + APB2OTP_BLK4_W1 volatile.Register32 // 0x8D0 + APB2OTP_BLK4_W2 volatile.Register32 // 0x8D4 + APB2OTP_BLK4_W3 volatile.Register32 // 0x8D8 + APB2OTP_BLK4_W4 volatile.Register32 // 0x8DC + APB2OTP_BLK4_W5 volatile.Register32 // 0x8E0 + APB2OTP_BLK4_W6 volatile.Register32 // 0x8E4 + APB2OTP_BLK4_W7 volatile.Register32 // 0x8E8 + APB2OTP_BLK4_W8 volatile.Register32 // 0x8EC + APB2OTP_BLK4_W9 volatile.Register32 // 0x8F0 + APB2OTP_BLK4_W10 volatile.Register32 // 0x8F4 + APB2OTP_BLK4_W11 volatile.Register32 // 0x8F8 + APB2OTP_BLK5_W1 volatile.Register32 // 0x8FC + APB2OTP_BLK5_W2 volatile.Register32 // 0x900 + APB2OTP_BLK5_W3 volatile.Register32 // 0x904 + APB2OTP_BLK5_W4 volatile.Register32 // 0x908 + APB2OTP_BLK5_W5 volatile.Register32 // 0x90C + APB2OTP_BLK5_W6 volatile.Register32 // 0x910 + APB2OTP_BLK5_W7 volatile.Register32 // 0x914 + APB2OTP_BLK5_W8 volatile.Register32 // 0x918 + APB2OTP_BLK5_W9 volatile.Register32 // 0x91C + APB2OTP_BLK5_W10 volatile.Register32 // 0x920 + APB2OTP_BLK5_W11 volatile.Register32 // 0x924 + APB2OTP_BLK6_W1 volatile.Register32 // 0x928 + APB2OTP_BLK6_W2 volatile.Register32 // 0x92C + APB2OTP_BLK6_W3 volatile.Register32 // 0x930 + APB2OTP_BLK6_W4 volatile.Register32 // 0x934 + APB2OTP_BLK6_W5 volatile.Register32 // 0x938 + APB2OTP_BLK6_W6 volatile.Register32 // 0x93C + APB2OTP_BLK6_W7 volatile.Register32 // 0x940 + APB2OTP_BLK6_W8 volatile.Register32 // 0x944 + APB2OTP_BLK6_W9 volatile.Register32 // 0x948 + APB2OTP_BLK6_W10 volatile.Register32 // 0x94C + APB2OTP_BLK6_W11 volatile.Register32 // 0x950 + APB2OTP_BLK7_W1 volatile.Register32 // 0x954 + APB2OTP_BLK7_W2 volatile.Register32 // 0x958 + APB2OTP_BLK7_W3 volatile.Register32 // 0x95C + APB2OTP_BLK7_W4 volatile.Register32 // 0x960 + APB2OTP_BLK7_W5 volatile.Register32 // 0x964 + APB2OTP_BLK7_W6 volatile.Register32 // 0x968 + APB2OTP_BLK7_W7 volatile.Register32 // 0x96C + APB2OTP_BLK7_W8 volatile.Register32 // 0x970 + APB2OTP_BLK7_W9 volatile.Register32 // 0x974 + APB2OTP_BLK7_W10 volatile.Register32 // 0x978 + APB2OTP_BLK7_W11 volatile.Register32 // 0x97C + APB2OTP_BLK8_W1 volatile.Register32 // 0x980 + APB2OTP_BLK8_W2 volatile.Register32 // 0x984 + APB2OTP_BLK8_W3 volatile.Register32 // 0x988 + APB2OTP_BLK8_W4 volatile.Register32 // 0x98C + APB2OTP_BLK8_W5 volatile.Register32 // 0x990 + APB2OTP_BLK8_W6 volatile.Register32 // 0x994 + APB2OTP_BLK8_W7 volatile.Register32 // 0x998 + APB2OTP_BLK8_W8 volatile.Register32 // 0x99C + APB2OTP_BLK8_W9 volatile.Register32 // 0x9A0 + APB2OTP_BLK8_W10 volatile.Register32 // 0x9A4 + APB2OTP_BLK8_W11 volatile.Register32 // 0x9A8 + APB2OTP_BLK9_W1 volatile.Register32 // 0x9AC + APB2OTP_BLK9_W2 volatile.Register32 // 0x9B0 + APB2OTP_BLK9_W3 volatile.Register32 // 0x9B4 + APB2OTP_BLK9_W4 volatile.Register32 // 0x9B8 + APB2OTP_BLK9_W5 volatile.Register32 // 0x9BC + APB2OTP_BLK9_W6 volatile.Register32 // 0x9C0 + APB2OTP_BLK9_W7 volatile.Register32 // 0x9C4 + APB2OTP_BLK9_W8 volatile.Register32 // 0x9C8 + APB2OTP_BLK9_W9 volatile.Register32 // 0x9CC + APB2OTP_BLK9_W10 volatile.Register32 // 0x9D0 + APB2OTP_BLK9_W11 volatile.Register32 // 0x9D4 + APB2OTP_BLK10_W1 volatile.Register32 // 0x9D8 + APB2OTP_BLK10_W2 volatile.Register32 // 0x9DC + APB2OTP_BLK10_W3 volatile.Register32 // 0x9E0 + APB2OTP_BLK10_W4 volatile.Register32 // 0x9E4 + APB2OTP_BLK10_W5 volatile.Register32 // 0x9E8 + APB2OTP_BLK10_W6 volatile.Register32 // 0x9EC + APB2OTP_BLK10_W7 volatile.Register32 // 0x9F0 + APB2OTP_BLK10_W8 volatile.Register32 // 0x9F4 + APB2OTP_BLK10_W9 volatile.Register32 // 0x9F8 + APB2OTP_BLK10_W10 volatile.Register32 // 0x9FC + APB2OTP_BLK10_W11 volatile.Register32 // 0xA00 + _ [4]byte + APB2OTP_EN volatile.Register32 // 0xA08 +} + +// EFUSE.PGM_DATA0: Register 0 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA0(value uint32) { + volatile.StoreUint32(&o.PGM_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA0() uint32 { + return volatile.LoadUint32(&o.PGM_DATA0.Reg) +} + +// EFUSE.PGM_DATA1: Register 1 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA1(value uint32) { + volatile.StoreUint32(&o.PGM_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA1() uint32 { + return volatile.LoadUint32(&o.PGM_DATA1.Reg) +} + +// EFUSE.PGM_DATA2: Register 2 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA2(value uint32) { + volatile.StoreUint32(&o.PGM_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA2() uint32 { + return volatile.LoadUint32(&o.PGM_DATA2.Reg) +} + +// EFUSE.PGM_DATA3: Register 3 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA3(value uint32) { + volatile.StoreUint32(&o.PGM_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA3() uint32 { + return volatile.LoadUint32(&o.PGM_DATA3.Reg) +} + +// EFUSE.PGM_DATA4: Register 4 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA4(value uint32) { + volatile.StoreUint32(&o.PGM_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA4() uint32 { + return volatile.LoadUint32(&o.PGM_DATA4.Reg) +} + +// EFUSE.PGM_DATA5: Register 5 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA5(value uint32) { + volatile.StoreUint32(&o.PGM_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA5() uint32 { + return volatile.LoadUint32(&o.PGM_DATA5.Reg) +} + +// EFUSE.PGM_DATA6: Register 6 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA6(value uint32) { + volatile.StoreUint32(&o.PGM_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA6() uint32 { + return volatile.LoadUint32(&o.PGM_DATA6.Reg) +} + +// EFUSE.PGM_DATA7: Register 7 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA7(value uint32) { + volatile.StoreUint32(&o.PGM_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA7() uint32 { + return volatile.LoadUint32(&o.PGM_DATA7.Reg) +} + +// EFUSE.PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE0(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE0() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE0.Reg) +} + +// EFUSE.PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE1(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE1() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE1.Reg) +} + +// EFUSE.PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE2(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE2() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE2.Reg) +} + +// EFUSE.RD_WR_DIS: BLOCK0 data register 0. +func (o *EFUSE_Type) SetRD_WR_DIS(value uint32) { + volatile.StoreUint32(&o.RD_WR_DIS.Reg, value) +} +func (o *EFUSE_Type) GetRD_WR_DIS() uint32 { + return volatile.LoadUint32(&o.RD_WR_DIS.Reg) +} + +// EFUSE.RD_REPEAT_DATA0: BLOCK0 data register 1. +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RD_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RD_DIS() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DEVICE_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DEVICE_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_OTG11_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_OTG11_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_POWERGLITCH_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_POWERGLITCH_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_TWAI(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_TWAI() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_JTAG_SEL_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_JTAG_SEL_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SOFT_DIS_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SOFT_DIS_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_PAD_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_PAD_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DEVICE_DREFH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DEVICE_DREFH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_OTG11_DREFH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_OTG11_DREFH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_PHY_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_KM_HUK_GEN_STATE_LOW(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xfc000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_KM_HUK_GEN_STATE_LOW() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xfc000000) >> 26 +} + +// EFUSE.RD_REPEAT_DATA1: BLOCK0 data register 2. +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KM_HUK_GEN_STATE_HIGH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KM_HUK_GEN_STATE_HIGH() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KM_RND_SWITCH_CYCLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x18)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KM_RND_SWITCH_CYCLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x18) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KM_DEPLOY_ONLY_ONCE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1e0)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KM_DEPLOY_ONLY_ONCE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1e0) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_FORCE_USE_KEY_MANAGER_KEY(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1e00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_FORCE_USE_KEY_MANAGER_KEY() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1e00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_FORCE_DISABLE_SW_INIT_KEY(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_FORCE_DISABLE_SW_INIT_KEY() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_XTS_KEY_LENGTH_256(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_XTS_KEY_LENGTH_256() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_WDT_DELAY_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_WDT_DELAY_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA2: BLOCK0 data register 3. +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_2() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SEC_DPA_LEVEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SEC_DPA_LEVEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_ECDSA_ENABLE_SOFT_K(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_ECDSA_ENABLE_SOFT_K() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_CRYPT_DPA_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_CRYPT_DPA_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_TYPE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_TYPE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x3000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x3000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_ECC_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_ECC_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_DIS_USB_OTG_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_DIS_USB_OTG_DOWNLOAD_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x8000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_TPUW(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_TPUW() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA3: BLOCK0 data register 4. +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DIRECT_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DIRECT_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_ROM_PRINT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_ROM_PRINT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_LOCK_KM_KEY(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_LOCK_KM_KEY() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CONTROL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CONTROL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FORCE_SEND_RESUME(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FORCE_SEND_RESUME() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_VERSION(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1fffe00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_VERSION() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1fffe00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_HYS_EN_PAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_HYS_EN_PAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DCDC_VSET(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xf8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DCDC_VSET() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xf8000000) >> 27 +} + +// EFUSE.RD_REPEAT_DATA4: BLOCK0 data register 5. +func (o *EFUSE_Type) SetRD_REPEAT_DATA4__0PXA_TIEH_SEL_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4__0PXA_TIEH_SEL_0() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4__0PXA_TIEH_SEL_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xc)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4__0PXA_TIEH_SEL_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xc) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4__0PXA_TIEH_SEL_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x30)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4__0PXA_TIEH_SEL_2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x30) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4__0PXA_TIEH_SEL_3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4__0PXA_TIEH_SEL_3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_KM_DISABLE_DEPLOY_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_KM_DISABLE_DEPLOY_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_USB_DEVICE_DREFL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x3000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_USB_DEVICE_DREFL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x3000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_USB_OTG11_DREFL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_USB_OTG11_DREFL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_HP_PWR_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_HP_PWR_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_DCDC_VSET_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_DCDC_VSET_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_DIS_WDT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_DIS_WDT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_DIS_SWD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_DIS_SWD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x200000) >> 21 +} + +// EFUSE.RD_MAC_SYS_0: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_0.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_0() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_0.Reg) +} + +// EFUSE.RD_MAC_SYS_1: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_1_MAC_1(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_1_MAC_1() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_MAC_SYS_1_MAC_EXT(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_1_MAC_EXT() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.RD_MAC_SYS_2: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_2_MAC_RESERVED_1(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_2.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg)&^(0x3fff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_2_MAC_RESERVED_1() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg) & 0x3fff +} +func (o *EFUSE_Type) SetRD_MAC_SYS_2_MAC_RESERVED_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_2.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg)&^(0xffffc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_2_MAC_RESERVED_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg) & 0xffffc000) >> 14 +} + +// EFUSE.RD_MAC_SYS_3: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_3_MAC_RESERVED_2(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg)&^(0x3ffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_3_MAC_RESERVED_2() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg) & 0x3ffff +} +func (o *EFUSE_Type) SetRD_MAC_SYS_3_SYS_DATA_PART0_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg)&^(0xfffc0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_3_SYS_DATA_PART0_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg) & 0xfffc0000) >> 18 +} + +// EFUSE.RD_MAC_SYS_4: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_4(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_4.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_4() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_4.Reg) +} + +// EFUSE.RD_MAC_SYS_5: BLOCK1 data register $n. +func (o *EFUSE_Type) SetRD_MAC_SYS_5(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SYS_5.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SYS_5() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SYS_5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA0: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA1: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA2: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA3: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA4: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA5: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA6: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA7: Register $n of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA7.Reg) +} + +// EFUSE.RD_USR_DATA0: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA0.Reg) +} + +// EFUSE.RD_USR_DATA1: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA1.Reg) +} + +// EFUSE.RD_USR_DATA2: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA2.Reg) +} + +// EFUSE.RD_USR_DATA3: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA3.Reg) +} + +// EFUSE.RD_USR_DATA4: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA4.Reg) +} + +// EFUSE.RD_USR_DATA5: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA5.Reg) +} + +// EFUSE.RD_USR_DATA6: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA6.Reg) +} + +// EFUSE.RD_USR_DATA7: Register $n of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA7.Reg) +} + +// EFUSE.RD_KEY0_DATA0: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA0.Reg) +} + +// EFUSE.RD_KEY0_DATA1: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA1.Reg) +} + +// EFUSE.RD_KEY0_DATA2: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA2.Reg) +} + +// EFUSE.RD_KEY0_DATA3: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA3.Reg) +} + +// EFUSE.RD_KEY0_DATA4: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA4.Reg) +} + +// EFUSE.RD_KEY0_DATA5: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA5.Reg) +} + +// EFUSE.RD_KEY0_DATA6: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA6.Reg) +} + +// EFUSE.RD_KEY0_DATA7: Register $n of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA7.Reg) +} + +// EFUSE.RD_KEY1_DATA0: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA0.Reg) +} + +// EFUSE.RD_KEY1_DATA1: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA1.Reg) +} + +// EFUSE.RD_KEY1_DATA2: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA2.Reg) +} + +// EFUSE.RD_KEY1_DATA3: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA3.Reg) +} + +// EFUSE.RD_KEY1_DATA4: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA4.Reg) +} + +// EFUSE.RD_KEY1_DATA5: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA5.Reg) +} + +// EFUSE.RD_KEY1_DATA6: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA6.Reg) +} + +// EFUSE.RD_KEY1_DATA7: Register $n of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA7.Reg) +} + +// EFUSE.RD_KEY2_DATA0: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA0.Reg) +} + +// EFUSE.RD_KEY2_DATA1: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA1.Reg) +} + +// EFUSE.RD_KEY2_DATA2: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA2.Reg) +} + +// EFUSE.RD_KEY2_DATA3: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA3.Reg) +} + +// EFUSE.RD_KEY2_DATA4: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA4.Reg) +} + +// EFUSE.RD_KEY2_DATA5: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA5.Reg) +} + +// EFUSE.RD_KEY2_DATA6: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA6.Reg) +} + +// EFUSE.RD_KEY2_DATA7: Register $n of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA7.Reg) +} + +// EFUSE.RD_KEY3_DATA0: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA0.Reg) +} + +// EFUSE.RD_KEY3_DATA1: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA1.Reg) +} + +// EFUSE.RD_KEY3_DATA2: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA2.Reg) +} + +// EFUSE.RD_KEY3_DATA3: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA3.Reg) +} + +// EFUSE.RD_KEY3_DATA4: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA4.Reg) +} + +// EFUSE.RD_KEY3_DATA5: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA5.Reg) +} + +// EFUSE.RD_KEY3_DATA6: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA6.Reg) +} + +// EFUSE.RD_KEY3_DATA7: Register $n of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA7.Reg) +} + +// EFUSE.RD_KEY4_DATA0: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA0.Reg) +} + +// EFUSE.RD_KEY4_DATA1: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA1.Reg) +} + +// EFUSE.RD_KEY4_DATA2: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA2.Reg) +} + +// EFUSE.RD_KEY4_DATA3: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA3.Reg) +} + +// EFUSE.RD_KEY4_DATA4: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA4.Reg) +} + +// EFUSE.RD_KEY4_DATA5: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA5.Reg) +} + +// EFUSE.RD_KEY4_DATA6: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA6.Reg) +} + +// EFUSE.RD_KEY4_DATA7: Register $n of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA7.Reg) +} + +// EFUSE.RD_KEY5_DATA0: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA0.Reg) +} + +// EFUSE.RD_KEY5_DATA1: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA1.Reg) +} + +// EFUSE.RD_KEY5_DATA2: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA2.Reg) +} + +// EFUSE.RD_KEY5_DATA3: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA3.Reg) +} + +// EFUSE.RD_KEY5_DATA4: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA4.Reg) +} + +// EFUSE.RD_KEY5_DATA5: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA5.Reg) +} + +// EFUSE.RD_KEY5_DATA6: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA6.Reg) +} + +// EFUSE.RD_KEY5_DATA7: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA7.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA0: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA1: Register $n of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA2: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA3: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA4: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA5: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA6: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA7: Register $n of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA7.Reg) +} + +// EFUSE.RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RD_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RD_DIS_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_DEVICE_EXCHG_PINS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_DEVICE_EXCHG_PINS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_OTG11_EXCHG_PINS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_OTG11_EXCHG_PINS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_POWERGLITCH_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_POWERGLITCH_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_TWAI_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_TWAI_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DEVICE_DREFH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DEVICE_DREFH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_OTG11_DREFH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_OTG11_DREFH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_PHY_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_PHY_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_HUK_GEN_STATE_LOW_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0xfc000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_HUK_GEN_STATE_LOW_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0xfc000000) >> 26 +} + +// EFUSE.RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KM_HUK_GEN_STATE_HIGH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KM_HUK_GEN_STATE_HIGH_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KM_RND_SWITCH_CYCLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x18)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KM_RND_SWITCH_CYCLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x18) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KM_DEPLOY_ONLY_ONCE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1e0)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KM_DEPLOY_ONLY_ONCE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1e0) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_FORCE_USE_KEY_MANAGER_KEY_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1e00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_FORCE_USE_KEY_MANAGER_KEY_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1e00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_FORCE_DISABLE_SW_INIT_KEY_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_FORCE_DISABLE_SW_INIT_KEY_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_XTS_KEY_LENGTH_256_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_XTS_KEY_LENGTH_256_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_ECDSA_ENABLE_SOFT_K_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_ECDSA_ENABLE_SOFT_K_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_TYPE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_TYPE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_PAGE_SIZE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x3000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_PAGE_SIZE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x3000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_ECC_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_ECC_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_DIS_USB_OTG_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_DIS_USB_OTG_DOWNLOAD_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x8000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_TPUW_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_TPUW_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_LOCK_KM_KEY_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_LOCK_KM_KEY_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_VERSION_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1fffe00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_VERSION_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1fffe00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_HYS_EN_PAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_HYS_EN_PAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DCDC_VSET_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xf8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DCDC_VSET_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xf8000000) >> 27 +} + +// EFUSE.RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR4__0PXA_TIEH_SEL_0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4__0PXA_TIEH_SEL_0_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4__0PXA_TIEH_SEL_1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xc)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4__0PXA_TIEH_SEL_1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xc) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4__0PXA_TIEH_SEL_2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x30)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4__0PXA_TIEH_SEL_2_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x30) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4__0PXA_TIEH_SEL_3_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4__0PXA_TIEH_SEL_3_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_KM_DISABLE_DEPLOY_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_KM_DISABLE_DEPLOY_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_USB_DEVICE_DREFL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x3000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_USB_DEVICE_DREFL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x3000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_USB_OTG11_DREFL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_USB_OTG11_DREFL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_HP_PWR_SRC_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_HP_PWR_SRC_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_DCDC_VSET_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_DCDC_VSET_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_DIS_WDT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_DIS_WDT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_DIS_SWD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_DIS_SWD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x200000) >> 21 +} + +// EFUSE.RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SYS_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SYS_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SYS_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SYS_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700)|value<<8) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700) >> 8 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000)|value<<12) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000) >> 12 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700000)|value<<20) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700000) >> 20 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000000) >> 24 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000000) >> 27 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000000) >> 28 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000000)|value<<31) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000000) >> 31 +} + +// EFUSE.RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x80) >> 7 +} + +// EFUSE.CLK: eFuse clcok configuration register. +func (o *EFUSE_Type) SetCLK_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCLK_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCLK_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCLK_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCLK_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetCLK_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x10000) >> 16 +} + +// EFUSE.CONF: eFuse operation mode configuraiton register +func (o *EFUSE_Type) SetCONF_OP_CODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetCONF_OP_CODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0xffff +} +func (o *EFUSE_Type) SetCONF_CFG_ECDSA_BLK(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetCONF_CFG_ECDSA_BLK() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0xf0000) >> 16 +} + +// EFUSE.STATUS: eFuse status register. +func (o *EFUSE_Type) SetSTATUS_STATE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetSTATUS_STATE() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xf +} +func (o *EFUSE_Type) SetSTATUS_OTP_LOAD_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetSTATUS_OTP_LOAD_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_C_SYNC2(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_C_SYNC2() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetSTATUS_OTP_STROBE_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetSTATUS_OTP_STROBE_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetSTATUS_OTP_CSB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetSTATUS_OTP_CSB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetSTATUS_OTP_PGENB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetSTATUS_OTP_PGENB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_IS_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_IS_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetSTATUS_BLK0_VALID_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xffc00)|value<<10) +} +func (o *EFUSE_Type) GetSTATUS_BLK0_VALID_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xffc00) >> 10 +} +func (o *EFUSE_Type) SetSTATUS_CUR_ECDSA_BLK(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf00000)|value<<20) +} +func (o *EFUSE_Type) GetSTATUS_CUR_ECDSA_BLK() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf00000) >> 20 +} + +// EFUSE.CMD: eFuse command register. +func (o *EFUSE_Type) SetCMD_READ_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCMD_READ_CMD() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCMD_PGM_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCMD_PGM_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCMD_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3c)|value<<2) +} +func (o *EFUSE_Type) GetCMD_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x3c) >> 2 +} + +// EFUSE.INT_RAW: eFuse raw interrupt register. +func (o *EFUSE_Type) SetINT_RAW_READ_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_RAW_READ_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_RAW_PGM_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_RAW_PGM_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ST: eFuse interrupt status register. +func (o *EFUSE_Type) SetINT_ST_READ_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ST_READ_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ST_PGM_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ST_PGM_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ENA: eFuse interrupt enable register. +func (o *EFUSE_Type) SetINT_ENA_READ_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ENA_READ_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ENA_PGM_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ENA_PGM_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_CLR: eFuse interrupt clear register. +func (o *EFUSE_Type) SetINT_CLR_READ_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_CLR_READ_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_CLR_PGM_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_CLR_PGM_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// EFUSE.DAC_CONF: Controls the eFuse programming voltage. +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.DAC_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_PAD_SEL(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_PAD_SEL() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_NUM(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x1fe00)|value<<9) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_NUM() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x1fe00) >> 9 +} +func (o *EFUSE_Type) SetDAC_CONF_OE_CLR(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EFUSE_Type) GetDAC_CONF_OE_CLR() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x20000) >> 17 +} + +// EFUSE.RD_TIM_CONF: Configures read timing parameters. +func (o *EFUSE_Type) SetRD_TIM_CONF_THR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_THR_A() uint32 { + return volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TRD(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TRD() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff00) >> 8 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TSUR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TSUR_A() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff0000) >> 16 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_READ_INIT_NUM(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_READ_INIT_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF1_TSUP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_TSUP_A() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff +} +func (o *EFUSE_Type) SetWR_TIM_CONF1_PWR_ON_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xffff00)|value<<8) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_PWR_ON_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xffff00) >> 8 +} +func (o *EFUSE_Type) SetWR_TIM_CONF1_THP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_THP_A() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF2_PWR_OFF_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_PWR_OFF_NUM() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff +} +func (o *EFUSE_Type) SetWR_TIM_CONF2_TPGM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_TPGM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.WR_TIM_CONF0_RS_BYPASS: Configurarion register0 of eFuse programming time parameters and rs bypass operation. +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0xffe)|value<<1) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0xffe) >> 1 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_UPDATE(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_UPDATE() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1fe000)|value<<13) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1fe000) >> 13 +} + +// EFUSE.DATE: eFuse version register. +func (o *EFUSE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *EFUSE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// EFUSE.APB2OTP_WR_DIS: eFuse apb2otp block0 data register1. +func (o *EFUSE_Type) SetAPB2OTP_WR_DIS(value uint32) { + volatile.StoreUint32(&o.APB2OTP_WR_DIS.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_WR_DIS() uint32 { + return volatile.LoadUint32(&o.APB2OTP_WR_DIS.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP1_W1: eFuse apb2otp block0 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W1.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP1_W2: eFuse apb2otp block0 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W2.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP1_W3: eFuse apb2otp block0 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W3.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP1_W4: eFuse apb2otp block0 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W4.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP1_W5: eFuse apb2otp block0 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W5.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP2_W1: eFuse apb2otp block0 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W1.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP2_W2: eFuse apb2otp block0 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W2.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP2_W3: eFuse apb2otp block0 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W3.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP2_W4: eFuse apb2otp block0 data register10. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W4.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP2_W5: eFuse apb2otp block0 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W5.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP3_W1: eFuse apb2otp block0 data register12. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W1.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP3_W2: eFuse apb2otp block0 data register13. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W2.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP3_W3: eFuse apb2otp block0 data register14. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W3.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP3_W4: eFuse apb2otp block0 data register15. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W4.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP3_W5: eFuse apb2otp block0 data register16. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W5.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP4_W1: eFuse apb2otp block0 data register17. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W1.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP4_W2: eFuse apb2otp block0 data register18. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W2.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP4_W3: eFuse apb2otp block0 data register19. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W3.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP4_W4: eFuse apb2otp block0 data register20. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W4.Reg) +} + +// EFUSE.APB2OTP_BLK0_BACKUP4_W5: eFuse apb2otp block0 data register21. +func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W5.Reg) +} + +// EFUSE.APB2OTP_BLK1_W1: eFuse apb2otp block1 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK1_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK1_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK1_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK1_W1.Reg) +} + +// EFUSE.APB2OTP_BLK1_W2: eFuse apb2otp block1 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK1_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK1_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK1_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK1_W2.Reg) +} + +// EFUSE.APB2OTP_BLK1_W3: eFuse apb2otp block1 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK1_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK1_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK1_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK1_W3.Reg) +} + +// EFUSE.APB2OTP_BLK1_W4: eFuse apb2otp block1 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK1_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK1_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK1_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK1_W4.Reg) +} + +// EFUSE.APB2OTP_BLK1_W5: eFuse apb2otp block1 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK1_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK1_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK1_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK1_W5.Reg) +} + +// EFUSE.APB2OTP_BLK1_W6: eFuse apb2otp block1 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK1_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK1_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK1_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK1_W6.Reg) +} + +// EFUSE.APB2OTP_BLK1_W7: eFuse apb2otp block1 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK1_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK1_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK1_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK1_W7.Reg) +} + +// EFUSE.APB2OTP_BLK1_W8: eFuse apb2otp block1 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK1_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK1_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK1_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK1_W8.Reg) +} + +// EFUSE.APB2OTP_BLK1_W9: eFuse apb2otp block1 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK1_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK1_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK1_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK1_W9.Reg) +} + +// EFUSE.APB2OTP_BLK2_W1: eFuse apb2otp block2 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W1.Reg) +} + +// EFUSE.APB2OTP_BLK2_W2: eFuse apb2otp block2 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W2.Reg) +} + +// EFUSE.APB2OTP_BLK2_W3: eFuse apb2otp block2 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W3.Reg) +} + +// EFUSE.APB2OTP_BLK2_W4: eFuse apb2otp block2 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W4.Reg) +} + +// EFUSE.APB2OTP_BLK2_W5: eFuse apb2otp block2 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W5.Reg) +} + +// EFUSE.APB2OTP_BLK2_W6: eFuse apb2otp block2 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W6.Reg) +} + +// EFUSE.APB2OTP_BLK2_W7: eFuse apb2otp block2 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W7.Reg) +} + +// EFUSE.APB2OTP_BLK2_W8: eFuse apb2otp block2 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W8.Reg) +} + +// EFUSE.APB2OTP_BLK2_W9: eFuse apb2otp block2 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W9.Reg) +} + +// EFUSE.APB2OTP_BLK2_W10: eFuse apb2otp block2 data register10. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W10(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W10.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W10() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W10.Reg) +} + +// EFUSE.APB2OTP_BLK2_W11: eFuse apb2otp block2 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK2_W11(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK2_W11.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK2_W11() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK2_W11.Reg) +} + +// EFUSE.APB2OTP_BLK3_W1: eFuse apb2otp block3 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W1.Reg) +} + +// EFUSE.APB2OTP_BLK3_W2: eFuse apb2otp block3 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W2.Reg) +} + +// EFUSE.APB2OTP_BLK3_W3: eFuse apb2otp block3 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W3.Reg) +} + +// EFUSE.APB2OTP_BLK3_W4: eFuse apb2otp block3 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W4.Reg) +} + +// EFUSE.APB2OTP_BLK3_W5: eFuse apb2otp block3 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W5.Reg) +} + +// EFUSE.APB2OTP_BLK3_W6: eFuse apb2otp block3 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W6.Reg) +} + +// EFUSE.APB2OTP_BLK3_W7: eFuse apb2otp block3 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W7.Reg) +} + +// EFUSE.APB2OTP_BLK3_W8: eFuse apb2otp block3 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W8.Reg) +} + +// EFUSE.APB2OTP_BLK3_W9: eFuse apb2otp block3 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W9.Reg) +} + +// EFUSE.APB2OTP_BLK3_W10: eFuse apb2otp block3 data register10. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W10(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W10.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W10() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W10.Reg) +} + +// EFUSE.APB2OTP_BLK3_W11: eFuse apb2otp block3 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK3_W11(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK3_W11.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK3_W11() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK3_W11.Reg) +} + +// EFUSE.APB2OTP_BLK4_W1: eFuse apb2otp block4 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W1.Reg) +} + +// EFUSE.APB2OTP_BLK4_W2: eFuse apb2otp block4 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W2.Reg) +} + +// EFUSE.APB2OTP_BLK4_W3: eFuse apb2otp block4 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W3.Reg) +} + +// EFUSE.APB2OTP_BLK4_W4: eFuse apb2otp block4 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W4.Reg) +} + +// EFUSE.APB2OTP_BLK4_W5: eFuse apb2otp block4 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W5.Reg) +} + +// EFUSE.APB2OTP_BLK4_W6: eFuse apb2otp block4 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W6.Reg) +} + +// EFUSE.APB2OTP_BLK4_W7: eFuse apb2otp block4 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W7.Reg) +} + +// EFUSE.APB2OTP_BLK4_W8: eFuse apb2otp block4 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W8.Reg) +} + +// EFUSE.APB2OTP_BLK4_W9: eFuse apb2otp block4 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W9.Reg) +} + +// EFUSE.APB2OTP_BLK4_W10: eFuse apb2otp block4 data registe10. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W10(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W10.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W10() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W10.Reg) +} + +// EFUSE.APB2OTP_BLK4_W11: eFuse apb2otp block4 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK4_W11(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK4_W11.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK4_W11() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK4_W11.Reg) +} + +// EFUSE.APB2OTP_BLK5_W1: eFuse apb2otp block5 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W1.Reg) +} + +// EFUSE.APB2OTP_BLK5_W2: eFuse apb2otp block5 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W2.Reg) +} + +// EFUSE.APB2OTP_BLK5_W3: eFuse apb2otp block5 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W3.Reg) +} + +// EFUSE.APB2OTP_BLK5_W4: eFuse apb2otp block5 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W4.Reg) +} + +// EFUSE.APB2OTP_BLK5_W5: eFuse apb2otp block5 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W5.Reg) +} + +// EFUSE.APB2OTP_BLK5_W6: eFuse apb2otp block5 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W6.Reg) +} + +// EFUSE.APB2OTP_BLK5_W7: eFuse apb2otp block5 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W7.Reg) +} + +// EFUSE.APB2OTP_BLK5_W8: eFuse apb2otp block5 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W8.Reg) +} + +// EFUSE.APB2OTP_BLK5_W9: eFuse apb2otp block5 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W9.Reg) +} + +// EFUSE.APB2OTP_BLK5_W10: eFuse apb2otp block5 data register10. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W10(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W10.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W10() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W10.Reg) +} + +// EFUSE.APB2OTP_BLK5_W11: eFuse apb2otp block5 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK5_W11(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK5_W11.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK5_W11() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK5_W11.Reg) +} + +// EFUSE.APB2OTP_BLK6_W1: eFuse apb2otp block6 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W1.Reg) +} + +// EFUSE.APB2OTP_BLK6_W2: eFuse apb2otp block6 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W2.Reg) +} + +// EFUSE.APB2OTP_BLK6_W3: eFuse apb2otp block6 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W3.Reg) +} + +// EFUSE.APB2OTP_BLK6_W4: eFuse apb2otp block6 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W4.Reg) +} + +// EFUSE.APB2OTP_BLK6_W5: eFuse apb2otp block6 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W5.Reg) +} + +// EFUSE.APB2OTP_BLK6_W6: eFuse apb2otp block6 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W6.Reg) +} + +// EFUSE.APB2OTP_BLK6_W7: eFuse apb2otp block6 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W7.Reg) +} + +// EFUSE.APB2OTP_BLK6_W8: eFuse apb2otp block6 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W8.Reg) +} + +// EFUSE.APB2OTP_BLK6_W9: eFuse apb2otp block6 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W9.Reg) +} + +// EFUSE.APB2OTP_BLK6_W10: eFuse apb2otp block6 data register10. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W10(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W10.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W10() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W10.Reg) +} + +// EFUSE.APB2OTP_BLK6_W11: eFuse apb2otp block6 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK6_W11(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK6_W11.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK6_W11() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK6_W11.Reg) +} + +// EFUSE.APB2OTP_BLK7_W1: eFuse apb2otp block7 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W1.Reg) +} + +// EFUSE.APB2OTP_BLK7_W2: eFuse apb2otp block7 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W2.Reg) +} + +// EFUSE.APB2OTP_BLK7_W3: eFuse apb2otp block7 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W3.Reg) +} + +// EFUSE.APB2OTP_BLK7_W4: eFuse apb2otp block7 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W4.Reg) +} + +// EFUSE.APB2OTP_BLK7_W5: eFuse apb2otp block7 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W5.Reg) +} + +// EFUSE.APB2OTP_BLK7_W6: eFuse apb2otp block7 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W6.Reg) +} + +// EFUSE.APB2OTP_BLK7_W7: eFuse apb2otp block7 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W7.Reg) +} + +// EFUSE.APB2OTP_BLK7_W8: eFuse apb2otp block7 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W8.Reg) +} + +// EFUSE.APB2OTP_BLK7_W9: eFuse apb2otp block7 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W9.Reg) +} + +// EFUSE.APB2OTP_BLK7_W10: eFuse apb2otp block7 data register10. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W10(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W10.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W10() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W10.Reg) +} + +// EFUSE.APB2OTP_BLK7_W11: eFuse apb2otp block7 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK7_W11(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK7_W11.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK7_W11() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK7_W11.Reg) +} + +// EFUSE.APB2OTP_BLK8_W1: eFuse apb2otp block8 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W1.Reg) +} + +// EFUSE.APB2OTP_BLK8_W2: eFuse apb2otp block8 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W2.Reg) +} + +// EFUSE.APB2OTP_BLK8_W3: eFuse apb2otp block8 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W3.Reg) +} + +// EFUSE.APB2OTP_BLK8_W4: eFuse apb2otp block8 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W4.Reg) +} + +// EFUSE.APB2OTP_BLK8_W5: eFuse apb2otp block8 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W5.Reg) +} + +// EFUSE.APB2OTP_BLK8_W6: eFuse apb2otp block8 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W6.Reg) +} + +// EFUSE.APB2OTP_BLK8_W7: eFuse apb2otp block8 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W7.Reg) +} + +// EFUSE.APB2OTP_BLK8_W8: eFuse apb2otp block8 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W8.Reg) +} + +// EFUSE.APB2OTP_BLK8_W9: eFuse apb2otp block8 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W9.Reg) +} + +// EFUSE.APB2OTP_BLK8_W10: eFuse apb2otp block8 data register10. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W10(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W10.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W10() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W10.Reg) +} + +// EFUSE.APB2OTP_BLK8_W11: eFuse apb2otp block8 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK8_W11(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK8_W11.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK8_W11() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK8_W11.Reg) +} + +// EFUSE.APB2OTP_BLK9_W1: eFuse apb2otp block9 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W1.Reg) +} + +// EFUSE.APB2OTP_BLK9_W2: eFuse apb2otp block9 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W2.Reg) +} + +// EFUSE.APB2OTP_BLK9_W3: eFuse apb2otp block9 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W3.Reg) +} + +// EFUSE.APB2OTP_BLK9_W4: eFuse apb2otp block9 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W4.Reg) +} + +// EFUSE.APB2OTP_BLK9_W5: eFuse apb2otp block9 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W5.Reg) +} + +// EFUSE.APB2OTP_BLK9_W6: eFuse apb2otp block9 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W6.Reg) +} + +// EFUSE.APB2OTP_BLK9_W7: eFuse apb2otp block9 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W7.Reg) +} + +// EFUSE.APB2OTP_BLK9_W8: eFuse apb2otp block9 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W8.Reg) +} + +// EFUSE.APB2OTP_BLK9_W9: eFuse apb2otp block9 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W9.Reg) +} + +// EFUSE.APB2OTP_BLK9_W10: eFuse apb2otp block9 data register10. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W10(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W10.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W10() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W10.Reg) +} + +// EFUSE.APB2OTP_BLK9_W11: eFuse apb2otp block9 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK9_W11(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK9_W11.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK9_W11() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK9_W11.Reg) +} + +// EFUSE.APB2OTP_BLK10_W1: eFuse apb2otp block10 data register1. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W1(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W1.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W1() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W1.Reg) +} + +// EFUSE.APB2OTP_BLK10_W2: eFuse apb2otp block10 data register2. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W2(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W2.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W2() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W2.Reg) +} + +// EFUSE.APB2OTP_BLK10_W3: eFuse apb2otp block10 data register3. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W3(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W3.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W3() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W3.Reg) +} + +// EFUSE.APB2OTP_BLK10_W4: eFuse apb2otp block10 data register4. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W4(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W4.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W4() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W4.Reg) +} + +// EFUSE.APB2OTP_BLK10_W5: eFuse apb2otp block10 data register5. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W5(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W5.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W5() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W5.Reg) +} + +// EFUSE.APB2OTP_BLK10_W6: eFuse apb2otp block10 data register6. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W6(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W6.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W6() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W6.Reg) +} + +// EFUSE.APB2OTP_BLK10_W7: eFuse apb2otp block10 data register7. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W7(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W7.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W7() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W7.Reg) +} + +// EFUSE.APB2OTP_BLK10_W8: eFuse apb2otp block10 data register8. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W8(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W8.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W8() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W8.Reg) +} + +// EFUSE.APB2OTP_BLK10_W9: eFuse apb2otp block10 data register9. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W9(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W9.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W9() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W9.Reg) +} + +// EFUSE.APB2OTP_BLK10_W10: eFuse apb2otp block10 data register10. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W10(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W10.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W10() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W10.Reg) +} + +// EFUSE.APB2OTP_BLK10_W11: eFuse apb2otp block10 data register11. +func (o *EFUSE_Type) SetAPB2OTP_BLK10_W11(value uint32) { + volatile.StoreUint32(&o.APB2OTP_BLK10_W11.Reg, value) +} +func (o *EFUSE_Type) GetAPB2OTP_BLK10_W11() uint32 { + return volatile.LoadUint32(&o.APB2OTP_BLK10_W11.Reg) +} + +// EFUSE.APB2OTP_EN: eFuse apb2otp enable configuration register. +func (o *EFUSE_Type) SetAPB2OTP_EN_APB2OTP_APB2OTP_EN(value uint32) { + volatile.StoreUint32(&o.APB2OTP_EN.Reg, volatile.LoadUint32(&o.APB2OTP_EN.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetAPB2OTP_EN_APB2OTP_APB2OTP_EN() uint32 { + return volatile.LoadUint32(&o.APB2OTP_EN.Reg) & 0x1 +} + +// General Purpose Input/Output +type GPIO_Type struct { + BT_SELECT volatile.Register32 // 0x0 + OUT volatile.Register32 // 0x4 + OUT_W1TS volatile.Register32 // 0x8 + OUT_W1TC volatile.Register32 // 0xC + OUT1 volatile.Register32 // 0x10 + OUT1_W1TS volatile.Register32 // 0x14 + OUT1_W1TC volatile.Register32 // 0x18 + _ [4]byte + ENABLE volatile.Register32 // 0x20 + ENABLE_W1TS volatile.Register32 // 0x24 + ENABLE_W1TC volatile.Register32 // 0x28 + ENABLE1 volatile.Register32 // 0x2C + ENABLE1_W1TS volatile.Register32 // 0x30 + ENABLE1_W1TC volatile.Register32 // 0x34 + STRAP volatile.Register32 // 0x38 + IN volatile.Register32 // 0x3C + IN1 volatile.Register32 // 0x40 + STATUS volatile.Register32 // 0x44 + STATUS_W1TS volatile.Register32 // 0x48 + STATUS_W1TC volatile.Register32 // 0x4C + STATUS1 volatile.Register32 // 0x50 + STATUS1_W1TS volatile.Register32 // 0x54 + STATUS1_W1TC volatile.Register32 // 0x58 + INTR_0 volatile.Register32 // 0x5C + INTR1_0 volatile.Register32 // 0x60 + INTR_1 volatile.Register32 // 0x64 + INTR1_1 volatile.Register32 // 0x68 + STATUS_NEXT volatile.Register32 // 0x6C + STATUS_NEXT1 volatile.Register32 // 0x70 + PIN0 volatile.Register32 // 0x74 + PIN1 volatile.Register32 // 0x78 + PIN2 volatile.Register32 // 0x7C + PIN3 volatile.Register32 // 0x80 + PIN4 volatile.Register32 // 0x84 + PIN5 volatile.Register32 // 0x88 + PIN6 volatile.Register32 // 0x8C + PIN7 volatile.Register32 // 0x90 + PIN8 volatile.Register32 // 0x94 + PIN9 volatile.Register32 // 0x98 + PIN10 volatile.Register32 // 0x9C + PIN11 volatile.Register32 // 0xA0 + PIN12 volatile.Register32 // 0xA4 + PIN13 volatile.Register32 // 0xA8 + PIN14 volatile.Register32 // 0xAC + PIN15 volatile.Register32 // 0xB0 + PIN16 volatile.Register32 // 0xB4 + PIN17 volatile.Register32 // 0xB8 + PIN18 volatile.Register32 // 0xBC + PIN19 volatile.Register32 // 0xC0 + PIN20 volatile.Register32 // 0xC4 + PIN21 volatile.Register32 // 0xC8 + PIN22 volatile.Register32 // 0xCC + PIN23 volatile.Register32 // 0xD0 + PIN24 volatile.Register32 // 0xD4 + PIN25 volatile.Register32 // 0xD8 + PIN26 volatile.Register32 // 0xDC + PIN27 volatile.Register32 // 0xE0 + PIN28 volatile.Register32 // 0xE4 + PIN29 volatile.Register32 // 0xE8 + PIN30 volatile.Register32 // 0xEC + PIN31 volatile.Register32 // 0xF0 + PIN32 volatile.Register32 // 0xF4 + PIN33 volatile.Register32 // 0xF8 + PIN34 volatile.Register32 // 0xFC + PIN35 volatile.Register32 // 0x100 + PIN36 volatile.Register32 // 0x104 + PIN37 volatile.Register32 // 0x108 + PIN38 volatile.Register32 // 0x10C + PIN39 volatile.Register32 // 0x110 + PIN40 volatile.Register32 // 0x114 + PIN41 volatile.Register32 // 0x118 + PIN42 volatile.Register32 // 0x11C + PIN43 volatile.Register32 // 0x120 + PIN44 volatile.Register32 // 0x124 + PIN45 volatile.Register32 // 0x128 + PIN46 volatile.Register32 // 0x12C + PIN47 volatile.Register32 // 0x130 + PIN48 volatile.Register32 // 0x134 + PIN49 volatile.Register32 // 0x138 + PIN50 volatile.Register32 // 0x13C + PIN51 volatile.Register32 // 0x140 + PIN52 volatile.Register32 // 0x144 + PIN53 volatile.Register32 // 0x148 + PIN54 volatile.Register32 // 0x14C + PIN55 volatile.Register32 // 0x150 + PIN56 volatile.Register32 // 0x154 + _ [4]byte + FUNC1_IN_SEL_CFG volatile.Register32 // 0x15C + FUNC2_IN_SEL_CFG volatile.Register32 // 0x160 + FUNC3_IN_SEL_CFG volatile.Register32 // 0x164 + FUNC4_IN_SEL_CFG volatile.Register32 // 0x168 + FUNC5_IN_SEL_CFG volatile.Register32 // 0x16C + FUNC6_IN_SEL_CFG volatile.Register32 // 0x170 + FUNC7_IN_SEL_CFG volatile.Register32 // 0x174 + FUNC8_IN_SEL_CFG volatile.Register32 // 0x178 + FUNC9_IN_SEL_CFG volatile.Register32 // 0x17C + FUNC10_IN_SEL_CFG volatile.Register32 // 0x180 + FUNC11_IN_SEL_CFG volatile.Register32 // 0x184 + FUNC12_IN_SEL_CFG volatile.Register32 // 0x188 + FUNC13_IN_SEL_CFG volatile.Register32 // 0x18C + FUNC14_IN_SEL_CFG volatile.Register32 // 0x190 + FUNC15_IN_SEL_CFG volatile.Register32 // 0x194 + FUNC16_IN_SEL_CFG volatile.Register32 // 0x198 + FUNC17_IN_SEL_CFG volatile.Register32 // 0x19C + FUNC18_IN_SEL_CFG volatile.Register32 // 0x1A0 + FUNC19_IN_SEL_CFG volatile.Register32 // 0x1A4 + FUNC20_IN_SEL_CFG volatile.Register32 // 0x1A8 + FUNC21_IN_SEL_CFG volatile.Register32 // 0x1AC + FUNC22_IN_SEL_CFG volatile.Register32 // 0x1B0 + FUNC23_IN_SEL_CFG volatile.Register32 // 0x1B4 + FUNC24_IN_SEL_CFG volatile.Register32 // 0x1B8 + FUNC25_IN_SEL_CFG volatile.Register32 // 0x1BC + FUNC26_IN_SEL_CFG volatile.Register32 // 0x1C0 + FUNC27_IN_SEL_CFG volatile.Register32 // 0x1C4 + FUNC28_IN_SEL_CFG volatile.Register32 // 0x1C8 + FUNC29_IN_SEL_CFG volatile.Register32 // 0x1CC + FUNC30_IN_SEL_CFG volatile.Register32 // 0x1D0 + FUNC31_IN_SEL_CFG volatile.Register32 // 0x1D4 + FUNC32_IN_SEL_CFG volatile.Register32 // 0x1D8 + FUNC33_IN_SEL_CFG volatile.Register32 // 0x1DC + FUNC34_IN_SEL_CFG volatile.Register32 // 0x1E0 + FUNC35_IN_SEL_CFG volatile.Register32 // 0x1E4 + FUNC36_IN_SEL_CFG volatile.Register32 // 0x1E8 + FUNC37_IN_SEL_CFG volatile.Register32 // 0x1EC + FUNC38_IN_SEL_CFG volatile.Register32 // 0x1F0 + FUNC39_IN_SEL_CFG volatile.Register32 // 0x1F4 + FUNC40_IN_SEL_CFG volatile.Register32 // 0x1F8 + FUNC41_IN_SEL_CFG volatile.Register32 // 0x1FC + FUNC42_IN_SEL_CFG volatile.Register32 // 0x200 + FUNC43_IN_SEL_CFG volatile.Register32 // 0x204 + FUNC44_IN_SEL_CFG volatile.Register32 // 0x208 + FUNC45_IN_SEL_CFG volatile.Register32 // 0x20C + FUNC46_IN_SEL_CFG volatile.Register32 // 0x210 + FUNC47_IN_SEL_CFG volatile.Register32 // 0x214 + FUNC48_IN_SEL_CFG volatile.Register32 // 0x218 + FUNC49_IN_SEL_CFG volatile.Register32 // 0x21C + FUNC50_IN_SEL_CFG volatile.Register32 // 0x220 + FUNC51_IN_SEL_CFG volatile.Register32 // 0x224 + FUNC52_IN_SEL_CFG volatile.Register32 // 0x228 + FUNC53_IN_SEL_CFG volatile.Register32 // 0x22C + FUNC54_IN_SEL_CFG volatile.Register32 // 0x230 + FUNC55_IN_SEL_CFG volatile.Register32 // 0x234 + FUNC56_IN_SEL_CFG volatile.Register32 // 0x238 + FUNC57_IN_SEL_CFG volatile.Register32 // 0x23C + FUNC58_IN_SEL_CFG volatile.Register32 // 0x240 + FUNC59_IN_SEL_CFG volatile.Register32 // 0x244 + FUNC60_IN_SEL_CFG volatile.Register32 // 0x248 + FUNC61_IN_SEL_CFG volatile.Register32 // 0x24C + FUNC62_IN_SEL_CFG volatile.Register32 // 0x250 + FUNC63_IN_SEL_CFG volatile.Register32 // 0x254 + FUNC64_IN_SEL_CFG volatile.Register32 // 0x258 + FUNC65_IN_SEL_CFG volatile.Register32 // 0x25C + FUNC66_IN_SEL_CFG volatile.Register32 // 0x260 + FUNC67_IN_SEL_CFG volatile.Register32 // 0x264 + FUNC68_IN_SEL_CFG volatile.Register32 // 0x268 + FUNC69_IN_SEL_CFG volatile.Register32 // 0x26C + FUNC70_IN_SEL_CFG volatile.Register32 // 0x270 + FUNC71_IN_SEL_CFG volatile.Register32 // 0x274 + FUNC72_IN_SEL_CFG volatile.Register32 // 0x278 + FUNC73_IN_SEL_CFG volatile.Register32 // 0x27C + FUNC74_IN_SEL_CFG volatile.Register32 // 0x280 + FUNC75_IN_SEL_CFG volatile.Register32 // 0x284 + FUNC76_IN_SEL_CFG volatile.Register32 // 0x288 + FUNC77_IN_SEL_CFG volatile.Register32 // 0x28C + FUNC78_IN_SEL_CFG volatile.Register32 // 0x290 + FUNC79_IN_SEL_CFG volatile.Register32 // 0x294 + FUNC80_IN_SEL_CFG volatile.Register32 // 0x298 + FUNC81_IN_SEL_CFG volatile.Register32 // 0x29C + FUNC82_IN_SEL_CFG volatile.Register32 // 0x2A0 + FUNC83_IN_SEL_CFG volatile.Register32 // 0x2A4 + FUNC84_IN_SEL_CFG volatile.Register32 // 0x2A8 + FUNC85_IN_SEL_CFG volatile.Register32 // 0x2AC + FUNC86_IN_SEL_CFG volatile.Register32 // 0x2B0 + FUNC87_IN_SEL_CFG volatile.Register32 // 0x2B4 + FUNC88_IN_SEL_CFG volatile.Register32 // 0x2B8 + FUNC89_IN_SEL_CFG volatile.Register32 // 0x2BC + FUNC90_IN_SEL_CFG volatile.Register32 // 0x2C0 + FUNC91_IN_SEL_CFG volatile.Register32 // 0x2C4 + FUNC92_IN_SEL_CFG volatile.Register32 // 0x2C8 + FUNC93_IN_SEL_CFG volatile.Register32 // 0x2CC + FUNC94_IN_SEL_CFG volatile.Register32 // 0x2D0 + FUNC95_IN_SEL_CFG volatile.Register32 // 0x2D4 + FUNC96_IN_SEL_CFG volatile.Register32 // 0x2D8 + FUNC97_IN_SEL_CFG volatile.Register32 // 0x2DC + FUNC98_IN_SEL_CFG volatile.Register32 // 0x2E0 + FUNC99_IN_SEL_CFG volatile.Register32 // 0x2E4 + FUNC100_IN_SEL_CFG volatile.Register32 // 0x2E8 + FUNC101_IN_SEL_CFG volatile.Register32 // 0x2EC + FUNC102_IN_SEL_CFG volatile.Register32 // 0x2F0 + FUNC103_IN_SEL_CFG volatile.Register32 // 0x2F4 + FUNC104_IN_SEL_CFG volatile.Register32 // 0x2F8 + FUNC105_IN_SEL_CFG volatile.Register32 // 0x2FC + FUNC106_IN_SEL_CFG volatile.Register32 // 0x300 + FUNC107_IN_SEL_CFG volatile.Register32 // 0x304 + FUNC108_IN_SEL_CFG volatile.Register32 // 0x308 + FUNC109_IN_SEL_CFG volatile.Register32 // 0x30C + FUNC110_IN_SEL_CFG volatile.Register32 // 0x310 + FUNC111_IN_SEL_CFG volatile.Register32 // 0x314 + FUNC112_IN_SEL_CFG volatile.Register32 // 0x318 + FUNC113_IN_SEL_CFG volatile.Register32 // 0x31C + FUNC114_IN_SEL_CFG volatile.Register32 // 0x320 + FUNC115_IN_SEL_CFG volatile.Register32 // 0x324 + FUNC116_IN_SEL_CFG volatile.Register32 // 0x328 + FUNC117_IN_SEL_CFG volatile.Register32 // 0x32C + FUNC118_IN_SEL_CFG volatile.Register32 // 0x330 + FUNC119_IN_SEL_CFG volatile.Register32 // 0x334 + FUNC120_IN_SEL_CFG volatile.Register32 // 0x338 + FUNC121_IN_SEL_CFG volatile.Register32 // 0x33C + FUNC122_IN_SEL_CFG volatile.Register32 // 0x340 + FUNC123_IN_SEL_CFG volatile.Register32 // 0x344 + FUNC124_IN_SEL_CFG volatile.Register32 // 0x348 + FUNC125_IN_SEL_CFG volatile.Register32 // 0x34C + FUNC126_IN_SEL_CFG volatile.Register32 // 0x350 + FUNC127_IN_SEL_CFG volatile.Register32 // 0x354 + FUNC128_IN_SEL_CFG volatile.Register32 // 0x358 + FUNC129_IN_SEL_CFG volatile.Register32 // 0x35C + FUNC130_IN_SEL_CFG volatile.Register32 // 0x360 + FUNC131_IN_SEL_CFG volatile.Register32 // 0x364 + FUNC132_IN_SEL_CFG volatile.Register32 // 0x368 + FUNC133_IN_SEL_CFG volatile.Register32 // 0x36C + FUNC134_IN_SEL_CFG volatile.Register32 // 0x370 + FUNC135_IN_SEL_CFG volatile.Register32 // 0x374 + FUNC136_IN_SEL_CFG volatile.Register32 // 0x378 + FUNC137_IN_SEL_CFG volatile.Register32 // 0x37C + FUNC138_IN_SEL_CFG volatile.Register32 // 0x380 + FUNC139_IN_SEL_CFG volatile.Register32 // 0x384 + FUNC140_IN_SEL_CFG volatile.Register32 // 0x388 + FUNC141_IN_SEL_CFG volatile.Register32 // 0x38C + FUNC142_IN_SEL_CFG volatile.Register32 // 0x390 + FUNC143_IN_SEL_CFG volatile.Register32 // 0x394 + FUNC144_IN_SEL_CFG volatile.Register32 // 0x398 + FUNC145_IN_SEL_CFG volatile.Register32 // 0x39C + FUNC146_IN_SEL_CFG volatile.Register32 // 0x3A0 + FUNC147_IN_SEL_CFG volatile.Register32 // 0x3A4 + FUNC148_IN_SEL_CFG volatile.Register32 // 0x3A8 + FUNC149_IN_SEL_CFG volatile.Register32 // 0x3AC + FUNC150_IN_SEL_CFG volatile.Register32 // 0x3B0 + FUNC151_IN_SEL_CFG volatile.Register32 // 0x3B4 + FUNC152_IN_SEL_CFG volatile.Register32 // 0x3B8 + FUNC153_IN_SEL_CFG volatile.Register32 // 0x3BC + FUNC154_IN_SEL_CFG volatile.Register32 // 0x3C0 + FUNC155_IN_SEL_CFG volatile.Register32 // 0x3C4 + FUNC156_IN_SEL_CFG volatile.Register32 // 0x3C8 + FUNC157_IN_SEL_CFG volatile.Register32 // 0x3CC + FUNC158_IN_SEL_CFG volatile.Register32 // 0x3D0 + FUNC159_IN_SEL_CFG volatile.Register32 // 0x3D4 + FUNC160_IN_SEL_CFG volatile.Register32 // 0x3D8 + FUNC161_IN_SEL_CFG volatile.Register32 // 0x3DC + FUNC162_IN_SEL_CFG volatile.Register32 // 0x3E0 + FUNC163_IN_SEL_CFG volatile.Register32 // 0x3E4 + FUNC164_IN_SEL_CFG volatile.Register32 // 0x3E8 + FUNC165_IN_SEL_CFG volatile.Register32 // 0x3EC + FUNC166_IN_SEL_CFG volatile.Register32 // 0x3F0 + FUNC167_IN_SEL_CFG volatile.Register32 // 0x3F4 + FUNC168_IN_SEL_CFG volatile.Register32 // 0x3F8 + FUNC169_IN_SEL_CFG volatile.Register32 // 0x3FC + FUNC170_IN_SEL_CFG volatile.Register32 // 0x400 + FUNC171_IN_SEL_CFG volatile.Register32 // 0x404 + FUNC172_IN_SEL_CFG volatile.Register32 // 0x408 + FUNC173_IN_SEL_CFG volatile.Register32 // 0x40C + FUNC174_IN_SEL_CFG volatile.Register32 // 0x410 + FUNC175_IN_SEL_CFG volatile.Register32 // 0x414 + FUNC176_IN_SEL_CFG volatile.Register32 // 0x418 + FUNC177_IN_SEL_CFG volatile.Register32 // 0x41C + FUNC178_IN_SEL_CFG volatile.Register32 // 0x420 + FUNC179_IN_SEL_CFG volatile.Register32 // 0x424 + FUNC180_IN_SEL_CFG volatile.Register32 // 0x428 + FUNC181_IN_SEL_CFG volatile.Register32 // 0x42C + FUNC182_IN_SEL_CFG volatile.Register32 // 0x430 + FUNC183_IN_SEL_CFG volatile.Register32 // 0x434 + FUNC184_IN_SEL_CFG volatile.Register32 // 0x438 + FUNC185_IN_SEL_CFG volatile.Register32 // 0x43C + FUNC186_IN_SEL_CFG volatile.Register32 // 0x440 + FUNC187_IN_SEL_CFG volatile.Register32 // 0x444 + FUNC188_IN_SEL_CFG volatile.Register32 // 0x448 + FUNC189_IN_SEL_CFG volatile.Register32 // 0x44C + FUNC190_IN_SEL_CFG volatile.Register32 // 0x450 + FUNC191_IN_SEL_CFG volatile.Register32 // 0x454 + FUNC192_IN_SEL_CFG volatile.Register32 // 0x458 + FUNC193_IN_SEL_CFG volatile.Register32 // 0x45C + FUNC194_IN_SEL_CFG volatile.Register32 // 0x460 + FUNC195_IN_SEL_CFG volatile.Register32 // 0x464 + FUNC196_IN_SEL_CFG volatile.Register32 // 0x468 + FUNC197_IN_SEL_CFG volatile.Register32 // 0x46C + FUNC198_IN_SEL_CFG volatile.Register32 // 0x470 + FUNC199_IN_SEL_CFG volatile.Register32 // 0x474 + FUNC200_IN_SEL_CFG volatile.Register32 // 0x478 + FUNC201_IN_SEL_CFG volatile.Register32 // 0x47C + FUNC202_IN_SEL_CFG volatile.Register32 // 0x480 + FUNC203_IN_SEL_CFG volatile.Register32 // 0x484 + FUNC204_IN_SEL_CFG volatile.Register32 // 0x488 + FUNC205_IN_SEL_CFG volatile.Register32 // 0x48C + FUNC206_IN_SEL_CFG volatile.Register32 // 0x490 + FUNC207_IN_SEL_CFG volatile.Register32 // 0x494 + FUNC208_IN_SEL_CFG volatile.Register32 // 0x498 + FUNC209_IN_SEL_CFG volatile.Register32 // 0x49C + FUNC210_IN_SEL_CFG volatile.Register32 // 0x4A0 + FUNC211_IN_SEL_CFG volatile.Register32 // 0x4A4 + FUNC212_IN_SEL_CFG volatile.Register32 // 0x4A8 + FUNC213_IN_SEL_CFG volatile.Register32 // 0x4AC + FUNC214_IN_SEL_CFG volatile.Register32 // 0x4B0 + FUNC215_IN_SEL_CFG volatile.Register32 // 0x4B4 + FUNC216_IN_SEL_CFG volatile.Register32 // 0x4B8 + FUNC217_IN_SEL_CFG volatile.Register32 // 0x4BC + FUNC218_IN_SEL_CFG volatile.Register32 // 0x4C0 + FUNC219_IN_SEL_CFG volatile.Register32 // 0x4C4 + FUNC220_IN_SEL_CFG volatile.Register32 // 0x4C8 + FUNC221_IN_SEL_CFG volatile.Register32 // 0x4CC + FUNC222_IN_SEL_CFG volatile.Register32 // 0x4D0 + FUNC223_IN_SEL_CFG volatile.Register32 // 0x4D4 + FUNC224_IN_SEL_CFG volatile.Register32 // 0x4D8 + FUNC225_IN_SEL_CFG volatile.Register32 // 0x4DC + FUNC226_IN_SEL_CFG volatile.Register32 // 0x4E0 + FUNC227_IN_SEL_CFG volatile.Register32 // 0x4E4 + FUNC228_IN_SEL_CFG volatile.Register32 // 0x4E8 + FUNC229_IN_SEL_CFG volatile.Register32 // 0x4EC + FUNC230_IN_SEL_CFG volatile.Register32 // 0x4F0 + FUNC231_IN_SEL_CFG volatile.Register32 // 0x4F4 + FUNC232_IN_SEL_CFG volatile.Register32 // 0x4F8 + FUNC233_IN_SEL_CFG volatile.Register32 // 0x4FC + FUNC234_IN_SEL_CFG volatile.Register32 // 0x500 + FUNC235_IN_SEL_CFG volatile.Register32 // 0x504 + FUNC236_IN_SEL_CFG volatile.Register32 // 0x508 + FUNC237_IN_SEL_CFG volatile.Register32 // 0x50C + FUNC238_IN_SEL_CFG volatile.Register32 // 0x510 + FUNC239_IN_SEL_CFG volatile.Register32 // 0x514 + FUNC240_IN_SEL_CFG volatile.Register32 // 0x518 + FUNC241_IN_SEL_CFG volatile.Register32 // 0x51C + FUNC242_IN_SEL_CFG volatile.Register32 // 0x520 + FUNC243_IN_SEL_CFG volatile.Register32 // 0x524 + FUNC244_IN_SEL_CFG volatile.Register32 // 0x528 + FUNC245_IN_SEL_CFG volatile.Register32 // 0x52C + FUNC246_IN_SEL_CFG volatile.Register32 // 0x530 + FUNC247_IN_SEL_CFG volatile.Register32 // 0x534 + FUNC248_IN_SEL_CFG volatile.Register32 // 0x538 + FUNC249_IN_SEL_CFG volatile.Register32 // 0x53C + FUNC250_IN_SEL_CFG volatile.Register32 // 0x540 + FUNC251_IN_SEL_CFG volatile.Register32 // 0x544 + FUNC252_IN_SEL_CFG volatile.Register32 // 0x548 + FUNC253_IN_SEL_CFG volatile.Register32 // 0x54C + FUNC254_IN_SEL_CFG volatile.Register32 // 0x550 + _ [4]byte + FUNC0_OUT_SEL_CFG volatile.Register32 // 0x558 + FUNC1_OUT_SEL_CFG volatile.Register32 // 0x55C + FUNC2_OUT_SEL_CFG volatile.Register32 // 0x560 + FUNC3_OUT_SEL_CFG volatile.Register32 // 0x564 + FUNC4_OUT_SEL_CFG volatile.Register32 // 0x568 + FUNC5_OUT_SEL_CFG volatile.Register32 // 0x56C + FUNC6_OUT_SEL_CFG volatile.Register32 // 0x570 + FUNC7_OUT_SEL_CFG volatile.Register32 // 0x574 + FUNC8_OUT_SEL_CFG volatile.Register32 // 0x578 + FUNC9_OUT_SEL_CFG volatile.Register32 // 0x57C + FUNC10_OUT_SEL_CFG volatile.Register32 // 0x580 + FUNC11_OUT_SEL_CFG volatile.Register32 // 0x584 + FUNC12_OUT_SEL_CFG volatile.Register32 // 0x588 + FUNC13_OUT_SEL_CFG volatile.Register32 // 0x58C + FUNC14_OUT_SEL_CFG volatile.Register32 // 0x590 + FUNC15_OUT_SEL_CFG volatile.Register32 // 0x594 + FUNC16_OUT_SEL_CFG volatile.Register32 // 0x598 + FUNC17_OUT_SEL_CFG volatile.Register32 // 0x59C + FUNC18_OUT_SEL_CFG volatile.Register32 // 0x5A0 + FUNC19_OUT_SEL_CFG volatile.Register32 // 0x5A4 + FUNC20_OUT_SEL_CFG volatile.Register32 // 0x5A8 + FUNC21_OUT_SEL_CFG volatile.Register32 // 0x5AC + FUNC22_OUT_SEL_CFG volatile.Register32 // 0x5B0 + FUNC23_OUT_SEL_CFG volatile.Register32 // 0x5B4 + FUNC24_OUT_SEL_CFG volatile.Register32 // 0x5B8 + FUNC25_OUT_SEL_CFG volatile.Register32 // 0x5BC + FUNC26_OUT_SEL_CFG volatile.Register32 // 0x5C0 + FUNC27_OUT_SEL_CFG volatile.Register32 // 0x5C4 + FUNC28_OUT_SEL_CFG volatile.Register32 // 0x5C8 + FUNC29_OUT_SEL_CFG volatile.Register32 // 0x5CC + FUNC30_OUT_SEL_CFG volatile.Register32 // 0x5D0 + FUNC31_OUT_SEL_CFG volatile.Register32 // 0x5D4 + FUNC32_OUT_SEL_CFG volatile.Register32 // 0x5D8 + FUNC33_OUT_SEL_CFG volatile.Register32 // 0x5DC + FUNC34_OUT_SEL_CFG volatile.Register32 // 0x5E0 + FUNC35_OUT_SEL_CFG volatile.Register32 // 0x5E4 + FUNC36_OUT_SEL_CFG volatile.Register32 // 0x5E8 + FUNC37_OUT_SEL_CFG volatile.Register32 // 0x5EC + FUNC38_OUT_SEL_CFG volatile.Register32 // 0x5F0 + FUNC39_OUT_SEL_CFG volatile.Register32 // 0x5F4 + FUNC40_OUT_SEL_CFG volatile.Register32 // 0x5F8 + FUNC41_OUT_SEL_CFG volatile.Register32 // 0x5FC + FUNC42_OUT_SEL_CFG volatile.Register32 // 0x600 + FUNC43_OUT_SEL_CFG volatile.Register32 // 0x604 + FUNC44_OUT_SEL_CFG volatile.Register32 // 0x608 + FUNC45_OUT_SEL_CFG volatile.Register32 // 0x60C + FUNC46_OUT_SEL_CFG volatile.Register32 // 0x610 + FUNC47_OUT_SEL_CFG volatile.Register32 // 0x614 + FUNC48_OUT_SEL_CFG volatile.Register32 // 0x618 + FUNC49_OUT_SEL_CFG volatile.Register32 // 0x61C + FUNC50_OUT_SEL_CFG volatile.Register32 // 0x620 + FUNC51_OUT_SEL_CFG volatile.Register32 // 0x624 + FUNC52_OUT_SEL_CFG volatile.Register32 // 0x628 + FUNC53_OUT_SEL_CFG volatile.Register32 // 0x62C + FUNC54_OUT_SEL_CFG volatile.Register32 // 0x630 + FUNC55_OUT_SEL_CFG volatile.Register32 // 0x634 + FUNC56_OUT_SEL_CFG volatile.Register32 // 0x638 + INTR_2 volatile.Register32 // 0x63C + INTR1_2 volatile.Register32 // 0x640 + INTR_3 volatile.Register32 // 0x644 + INTR1_3 volatile.Register32 // 0x648 + CLOCK_GATE volatile.Register32 // 0x64C + _ [176]byte + INT_RAW volatile.Register32 // 0x700 + INT_ST volatile.Register32 // 0x704 + INT_ENA volatile.Register32 // 0x708 + INT_CLR volatile.Register32 // 0x70C + ZERO_DET0_FILTER_CNT volatile.Register32 // 0x710 + ZERO_DET1_FILTER_CNT volatile.Register32 // 0x714 + SEND_SEQ volatile.Register32 // 0x718 + RECIVE_SEQ volatile.Register32 // 0x71C + BISTIN_SEL volatile.Register32 // 0x720 + BIST_CTRL volatile.Register32 // 0x724 + _ [212]byte + DATE volatile.Register32 // 0x7FC +} + +// GPIO.BT_SELECT: GPIO bit select register +func (o *GPIO_Type) SetBT_SELECT(value uint32) { + volatile.StoreUint32(&o.BT_SELECT.Reg, value) +} +func (o *GPIO_Type) GetBT_SELECT() uint32 { + return volatile.LoadUint32(&o.BT_SELECT.Reg) +} + +// GPIO.OUT: GPIO output register for GPIO0-31 +func (o *GPIO_Type) SetOUT(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, value) +} +func (o *GPIO_Type) GetOUT() uint32 { + return volatile.LoadUint32(&o.OUT.Reg) +} + +// GPIO.OUT_W1TS: GPIO output set register for GPIO0-31 +func (o *GPIO_Type) SetOUT_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_W1TS.Reg) +} + +// GPIO.OUT_W1TC: GPIO output clear register for GPIO0-31 +func (o *GPIO_Type) SetOUT_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_W1TC.Reg) +} + +// GPIO.OUT1: GPIO output register for GPIO32-56 +func (o *GPIO_Type) SetOUT1_DATA_ORIG(value uint32) { + volatile.StoreUint32(&o.OUT1.Reg, volatile.LoadUint32(&o.OUT1.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetOUT1_DATA_ORIG() uint32 { + return volatile.LoadUint32(&o.OUT1.Reg) & 0x1ffffff +} + +// GPIO.OUT1_W1TS: GPIO output set register for GPIO32-56 +func (o *GPIO_Type) SetOUT1_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TS.Reg, volatile.LoadUint32(&o.OUT1_W1TS.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetOUT1_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TS.Reg) & 0x1ffffff +} + +// GPIO.OUT1_W1TC: GPIO output clear register for GPIO32-56 +func (o *GPIO_Type) SetOUT1_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TC.Reg, volatile.LoadUint32(&o.OUT1_W1TC.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetOUT1_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TC.Reg) & 0x1ffffff +} + +// GPIO.ENABLE: GPIO output enable register for GPIO0-31 +func (o *GPIO_Type) SetENABLE(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, value) +} +func (o *GPIO_Type) GetENABLE() uint32 { + return volatile.LoadUint32(&o.ENABLE.Reg) +} + +// GPIO.ENABLE_W1TS: GPIO output enable set register for GPIO0-31 +func (o *GPIO_Type) SetENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) +} + +// GPIO.ENABLE_W1TC: GPIO output enable clear register for GPIO0-31 +func (o *GPIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) +} + +// GPIO.ENABLE1: GPIO output enable register for GPIO32-56 +func (o *GPIO_Type) SetENABLE1_DATA(value uint32) { + volatile.StoreUint32(&o.ENABLE1.Reg, volatile.LoadUint32(&o.ENABLE1.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetENABLE1_DATA() uint32 { + return volatile.LoadUint32(&o.ENABLE1.Reg) & 0x1ffffff +} + +// GPIO.ENABLE1_W1TS: GPIO output enable set register for GPIO32-56 +func (o *GPIO_Type) SetENABLE1_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TS.Reg, volatile.LoadUint32(&o.ENABLE1_W1TS.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TS.Reg) & 0x1ffffff +} + +// GPIO.ENABLE1_W1TC: GPIO output enable clear register for GPIO32-56 +func (o *GPIO_Type) SetENABLE1_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TC.Reg, volatile.LoadUint32(&o.ENABLE1_W1TC.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TC.Reg) & 0x1ffffff +} + +// GPIO.STRAP: pad strapping register +func (o *GPIO_Type) SetSTRAP_STRAPPING(value uint32) { + volatile.StoreUint32(&o.STRAP.Reg, volatile.LoadUint32(&o.STRAP.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetSTRAP_STRAPPING() uint32 { + return volatile.LoadUint32(&o.STRAP.Reg) & 0xffff +} + +// GPIO.IN: GPIO input register for GPIO0-31 +func (o *GPIO_Type) SetIN(value uint32) { + volatile.StoreUint32(&o.IN.Reg, value) +} +func (o *GPIO_Type) GetIN() uint32 { + return volatile.LoadUint32(&o.IN.Reg) +} + +// GPIO.IN1: GPIO input register for GPIO32-56 +func (o *GPIO_Type) SetIN1_DATA_NEXT(value uint32) { + volatile.StoreUint32(&o.IN1.Reg, volatile.LoadUint32(&o.IN1.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetIN1_DATA_NEXT() uint32 { + return volatile.LoadUint32(&o.IN1.Reg) & 0x1ffffff +} + +// GPIO.STATUS: GPIO interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) +} + +// GPIO.STATUS_W1TS: GPIO interrupt status set register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) +} + +// GPIO.STATUS_W1TC: GPIO interrupt status clear register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) +} + +// GPIO.STATUS1: GPIO interrupt status register for GPIO32-56 +func (o *GPIO_Type) SetSTATUS1_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.STATUS1.Reg, volatile.LoadUint32(&o.STATUS1.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS1_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.STATUS1.Reg) & 0x1ffffff +} + +// GPIO.STATUS1_W1TS: GPIO interrupt status set register for GPIO32-56 +func (o *GPIO_Type) SetSTATUS1_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TS.Reg, volatile.LoadUint32(&o.STATUS1_W1TS.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TS.Reg) & 0x1ffffff +} + +// GPIO.STATUS1_W1TC: GPIO interrupt status clear register for GPIO32-56 +func (o *GPIO_Type) SetSTATUS1_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TC.Reg, volatile.LoadUint32(&o.STATUS1_W1TC.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TC.Reg) & 0x1ffffff +} + +// GPIO.INTR_0: GPIO interrupt 0 status register for GPIO0-31 +func (o *GPIO_Type) SetINTR_0(value uint32) { + volatile.StoreUint32(&o.INTR_0.Reg, value) +} +func (o *GPIO_Type) GetINTR_0() uint32 { + return volatile.LoadUint32(&o.INTR_0.Reg) +} + +// GPIO.INTR1_0: GPIO interrupt 0 status register for GPIO32-56 +func (o *GPIO_Type) SetINTR1_0_INT1_0(value uint32) { + volatile.StoreUint32(&o.INTR1_0.Reg, volatile.LoadUint32(&o.INTR1_0.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetINTR1_0_INT1_0() uint32 { + return volatile.LoadUint32(&o.INTR1_0.Reg) & 0x1ffffff +} + +// GPIO.INTR_1: GPIO interrupt 1 status register for GPIO0-31 +func (o *GPIO_Type) SetINTR_1(value uint32) { + volatile.StoreUint32(&o.INTR_1.Reg, value) +} +func (o *GPIO_Type) GetINTR_1() uint32 { + return volatile.LoadUint32(&o.INTR_1.Reg) +} + +// GPIO.INTR1_1: GPIO interrupt 1 status register for GPIO32-56 +func (o *GPIO_Type) SetINTR1_1_INT1_1(value uint32) { + volatile.StoreUint32(&o.INTR1_1.Reg, volatile.LoadUint32(&o.INTR1_1.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetINTR1_1_INT1_1() uint32 { + return volatile.LoadUint32(&o.INTR1_1.Reg) & 0x1ffffff +} + +// GPIO.STATUS_NEXT: GPIO interrupt source register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT.Reg) +} + +// GPIO.STATUS_NEXT1: GPIO interrupt source register for GPIO32-56 +func (o *GPIO_Type) SetSTATUS_NEXT1_STATUS_INTERRUPT_NEXT1(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT1.Reg, volatile.LoadUint32(&o.STATUS_NEXT1.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetSTATUS_NEXT1_STATUS_INTERRUPT_NEXT1() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT1.Reg) & 0x1ffffff +} + +// GPIO.PIN0: GPIO pin configuration register +func (o *GPIO_Type) SetPIN0_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN0_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN0_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN0_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN0_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN0_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN1: GPIO pin configuration register +func (o *GPIO_Type) SetPIN1_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN1_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN1_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN1_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN1_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN1_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN2: GPIO pin configuration register +func (o *GPIO_Type) SetPIN2_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN2_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN2_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN2_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN2_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN2_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN3: GPIO pin configuration register +func (o *GPIO_Type) SetPIN3_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN3_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN3_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN3_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN3_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN3_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN4: GPIO pin configuration register +func (o *GPIO_Type) SetPIN4_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN4_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN4_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN4_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN4_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN4_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN5: GPIO pin configuration register +func (o *GPIO_Type) SetPIN5_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN5_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN5_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN5_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN5_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN5_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN6: GPIO pin configuration register +func (o *GPIO_Type) SetPIN6_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN6_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN6_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN6_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN6_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN6_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN7: GPIO pin configuration register +func (o *GPIO_Type) SetPIN7_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN7_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN7_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN7_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN7_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN7_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN8: GPIO pin configuration register +func (o *GPIO_Type) SetPIN8_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN8_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN8.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN8_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN8_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN8_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN8_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN9: GPIO pin configuration register +func (o *GPIO_Type) SetPIN9_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN9_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN9.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN9_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN9_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN9_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN9_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN10: GPIO pin configuration register +func (o *GPIO_Type) SetPIN10_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN10_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN10.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN10_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN10_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN10_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN10_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN10_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN10_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN11: GPIO pin configuration register +func (o *GPIO_Type) SetPIN11_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN11_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN11.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN11_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN11_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN11_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN11_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN11_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN11_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN12: GPIO pin configuration register +func (o *GPIO_Type) SetPIN12_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN12_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN12.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN12_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN12_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN12_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN12_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN12_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN12_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN13: GPIO pin configuration register +func (o *GPIO_Type) SetPIN13_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN13_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN13.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN13_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN13_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN13_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN13_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN13_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN13_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN14: GPIO pin configuration register +func (o *GPIO_Type) SetPIN14_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN14_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN14.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN14_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN14_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN14_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN14_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN14_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN14_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN15: GPIO pin configuration register +func (o *GPIO_Type) SetPIN15_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN15_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN15.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN15_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN15_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN15_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN15_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN15_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN15_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN16: GPIO pin configuration register +func (o *GPIO_Type) SetPIN16_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN16_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN16.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN16_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN16_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN16_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN16_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN16_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN16_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN17: GPIO pin configuration register +func (o *GPIO_Type) SetPIN17_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN17_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN17.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN17_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN17_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN17_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN17_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN17_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN17_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN18: GPIO pin configuration register +func (o *GPIO_Type) SetPIN18_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN18_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN18.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN18_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN18_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN18_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN18_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN18_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN18_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN19: GPIO pin configuration register +func (o *GPIO_Type) SetPIN19_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN19_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN19.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN19_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN19_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN19_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN19_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN19_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN19_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN20: GPIO pin configuration register +func (o *GPIO_Type) SetPIN20_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN20_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN20.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN20_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN20_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN20_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN20_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN20_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN20_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN21: GPIO pin configuration register +func (o *GPIO_Type) SetPIN21_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN21_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN21.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN21_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN21_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN21_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN21_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN21_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN21_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN22: GPIO pin configuration register +func (o *GPIO_Type) SetPIN22_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN22_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN22.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN22_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN22_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN22_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN22_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN22_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN22_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN22_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN22_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN22_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN22_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN22_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN22_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN23: GPIO pin configuration register +func (o *GPIO_Type) SetPIN23_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN23_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN23.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN23_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN23_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN23_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN23_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN23_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN23_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN23_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN23_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN23_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN23_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN23_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN23_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN24: GPIO pin configuration register +func (o *GPIO_Type) SetPIN24_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN24_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN24.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN24_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN24_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN24_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN24_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN24_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN24_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN24_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN24_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN24_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN24_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN24_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN24_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN25: GPIO pin configuration register +func (o *GPIO_Type) SetPIN25_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN25_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN25.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN25_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN25_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN25_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN25_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN25_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN25_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN25_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN25_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN25_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN25_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN25_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN25_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN26: GPIO pin configuration register +func (o *GPIO_Type) SetPIN26_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN26_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN26.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN26_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN26_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN26_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN26_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN26_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN26_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN26_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN26_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN26_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN26_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN26_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN26_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN27: GPIO pin configuration register +func (o *GPIO_Type) SetPIN27_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN27_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN27.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN27_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN27_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN27_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN27_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN27_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN27_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN27_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN27_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN27_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN27_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN27_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN27_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN28: GPIO pin configuration register +func (o *GPIO_Type) SetPIN28_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN28_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN28.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN28_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN28_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN28_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN28_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN28_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN28_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN28_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN28_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN28_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN28_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN28_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN28_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN29: GPIO pin configuration register +func (o *GPIO_Type) SetPIN29_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN29_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN29.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN29_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN29_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN29_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN29_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN29_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN29_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN29_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN29_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN29_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN29_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN29_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN29_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN30: GPIO pin configuration register +func (o *GPIO_Type) SetPIN30_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN30_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN30.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN30_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN30_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN30_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN30_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN30_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN30_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN30_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN30_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN30_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN30_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN30_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN30_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN31: GPIO pin configuration register +func (o *GPIO_Type) SetPIN31_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN31_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN31.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN31_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN31_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN31_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN31_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN31_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN31_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN31_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN31_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN31_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN31_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN31_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN31_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN32: GPIO pin configuration register +func (o *GPIO_Type) SetPIN32_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN32_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN32.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN32_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN32_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN32_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN32_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN32_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN32_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN32_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN32_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN32_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN32_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN32_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN32_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN33: GPIO pin configuration register +func (o *GPIO_Type) SetPIN33_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN33_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN33.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN33_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN33_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN33_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN33_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN33_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN33_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN33_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN33_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN33_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN33_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN33_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN33_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN34: GPIO pin configuration register +func (o *GPIO_Type) SetPIN34_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN34_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN34.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN34_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN34_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN34_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN34_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN34_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN34_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN34_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN34_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN34_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN34_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN34_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN34_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN35: GPIO pin configuration register +func (o *GPIO_Type) SetPIN35_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN35_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN35.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN35_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN35_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN35_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN35_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN35_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN35_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN35_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN35_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN35_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN35_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN35_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN35_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN36: GPIO pin configuration register +func (o *GPIO_Type) SetPIN36_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN36_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN36.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN36_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN36_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN36_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN36_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN36_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN36_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN36_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN36_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN36_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN36_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN36_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN36_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN37: GPIO pin configuration register +func (o *GPIO_Type) SetPIN37_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN37_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN37.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN37_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN37_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN37_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN37_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN37_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN37_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN37_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN37_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN37_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN37_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN37_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN37_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN38: GPIO pin configuration register +func (o *GPIO_Type) SetPIN38_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN38_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN38.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN38_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN38_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN38_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN38_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN38_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN38_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN38_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN38_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN38_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN38_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN38_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN38_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN39: GPIO pin configuration register +func (o *GPIO_Type) SetPIN39_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN39_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN39.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN39_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN39_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN39_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN39_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN39_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN39_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN39_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN39_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN39_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN39_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN39_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN39_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN40: GPIO pin configuration register +func (o *GPIO_Type) SetPIN40_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN40_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN40.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN40_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN40_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN40_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN40_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN40_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN40_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN40_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN40_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN40_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN40_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN40_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN40_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN41: GPIO pin configuration register +func (o *GPIO_Type) SetPIN41_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN41_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN41.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN41_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN41_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN41_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN41_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN41_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN41_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN41_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN41_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN41_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN41_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN41_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN41_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN42: GPIO pin configuration register +func (o *GPIO_Type) SetPIN42_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN42_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN42.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN42_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN42_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN42_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN42_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN42_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN42_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN42_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN42_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN42_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN42_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN42_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN42_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN43: GPIO pin configuration register +func (o *GPIO_Type) SetPIN43_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN43_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN43.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN43_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN43_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN43_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN43_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN43_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN43_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN43_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN43_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN43_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN43_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN43_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN43_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN44: GPIO pin configuration register +func (o *GPIO_Type) SetPIN44_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN44_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN44.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN44_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN44_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN44_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN44_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN44_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN44_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN44_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN44_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN44_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN44_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN44_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN44_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN45: GPIO pin configuration register +func (o *GPIO_Type) SetPIN45_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN45_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN45.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN45_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN45_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN45_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN45_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN45_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN45_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN45_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN45_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN45_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN45_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN45_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN45_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN46: GPIO pin configuration register +func (o *GPIO_Type) SetPIN46_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN46_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN46.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN46_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN46_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN46_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN46_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN46_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN46_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN46_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN46_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN46_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN46_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN46_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN46_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN47: GPIO pin configuration register +func (o *GPIO_Type) SetPIN47_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN47_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN47.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN47_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN47_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN47_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN47_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN47_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN47_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN47_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN47_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN47_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN47_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN47_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN47_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN48: GPIO pin configuration register +func (o *GPIO_Type) SetPIN48_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN48_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN48.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN48_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN48_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN48_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN48_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN48_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN48_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN48_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN48_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN48_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN48_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN48_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN48_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN49: GPIO pin configuration register +func (o *GPIO_Type) SetPIN49_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN49_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN49.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN49_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN49_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN49_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN49_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN49_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN49_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN49_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN49_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN49_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN49_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN49_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN49_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN50: GPIO pin configuration register +func (o *GPIO_Type) SetPIN50_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN50_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN50.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN50_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN50_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN50_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN50_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN50_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN50_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN50_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN50_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN50_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN50_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN50_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN50_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN51: GPIO pin configuration register +func (o *GPIO_Type) SetPIN51_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN51_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN51.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN51_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN51_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN51_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN51_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN51_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN51_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN51_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN51_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN51_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN51_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN51_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN51_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN52: GPIO pin configuration register +func (o *GPIO_Type) SetPIN52_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN52_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN52.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN52_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN52_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN52_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN52_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN52_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN52_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN52_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN52_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN52_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN52_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN52_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN52_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN53: GPIO pin configuration register +func (o *GPIO_Type) SetPIN53_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN53_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN53.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN53_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN53_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN53_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN53_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN53_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN53_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN53_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN53_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN53_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN53_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN53_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN53_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN54: GPIO pin configuration register +func (o *GPIO_Type) SetPIN54_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN54_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN54.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN54_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN54_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN54.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN54_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN54_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN54.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN54_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN54_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN54.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN54_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN54_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN54.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN54_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN54_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN54.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN54_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN54_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN54.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN55: GPIO pin configuration register +func (o *GPIO_Type) SetPIN55_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN55_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN55.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN55_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN55_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN55.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN55_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN55_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN55.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN55_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN55_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN55.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN55_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN55_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN55.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN55_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN55_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN55.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN55_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN55_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN55.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN56: GPIO pin configuration register +func (o *GPIO_Type) SetPIN56_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN56_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN56.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN56_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN56_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN56.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN56_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN56_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN56.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN56_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN56_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN56.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN56_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN56_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN56.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN56_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN56_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN56.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN56_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN56_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN56.Reg) & 0x3e000) >> 13 +} + +// GPIO.FUNC1_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC2_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC3_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC4_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC5_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC6_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC7_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC8_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC9_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC10_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC11_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC12_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC13_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC14_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC15_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC16_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC17_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC18_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC19_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC20_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC21_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC22_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC23_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC24_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC25_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC26_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC27_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC28_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC29_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC30_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC31_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC32_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC33_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC34_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC35_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC36_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC37_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC38_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC39_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC40_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC41_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC42_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC43_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC44_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC45_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC46_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC47_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC48_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC49_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC50_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC51_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC52_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC53_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC54_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC55_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC56_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC57_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC58_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC59_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC60_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC61_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC62_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC63_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC64_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC65_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC66_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC67_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC68_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC69_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC70_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC71_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC72_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC73_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC74_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC75_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC76_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC77_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC78_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC79_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC80_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC81_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC82_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC83_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC84_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC85_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC86_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC87_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC88_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC89_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC90_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC91_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC92_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC93_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC94_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC95_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC96_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC97_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC98_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC99_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC100_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC101_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC102_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC103_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC104_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC105_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC106_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC107_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC108_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC109_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC110_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC111_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC112_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC113_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC114_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC115_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC116_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC117_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC118_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC119_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC120_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC121_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC122_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC123_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC124_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC125_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC126_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC127_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC128_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC129_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC130_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC131_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC132_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC133_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC134_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC135_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC136_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC137_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC138_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC139_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC140_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC141_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC142_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC143_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC144_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC145_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC146_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC147_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC148_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC149_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC150_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC151_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC152_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC153_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC154_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC155_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC156_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC157_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC158_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC159_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC160_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC161_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC162_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC163_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC164_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC165_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC166_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC167_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC168_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC169_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC170_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC171_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC172_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC173_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC174_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC175_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC176_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC177_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC178_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC179_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC180_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC181_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC182_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC183_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC184_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC185_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC186_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC187_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC188_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC189_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC190_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC191_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC192_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC193_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC194_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC195_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC196_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC197_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC198_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC199_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC200_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC201_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC202_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC203_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC204_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC205_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC206_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC207_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC208_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC209_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC210_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC211_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC212_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC213_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC214_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC215_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC216_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC217_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC218_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC219_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC220_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC221_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC222_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC223_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC224_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC225_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC226_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC227_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC228_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC229_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC230_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC231_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC232_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC233_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC234_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC235_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC236_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC237_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC238_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC239_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC240_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC241_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC242_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC243_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC244_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC245_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC246_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC247_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC248_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC249_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC250_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC251_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC252_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC253_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC254_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC0_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC1_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC2_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC3_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC4_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC5_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC6_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC7_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC8_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC9_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC10_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC11_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC12_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC13_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC14_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC15_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC16_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC17_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC18_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC19_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC20_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC21_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC22_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC23_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC24_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC25_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC26_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC27_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC28_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC29_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC30_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC31_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC32_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC33_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC34_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC35_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC36_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC37_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC38_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC39_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC40_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC41_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC42_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC43_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC44_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC45_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC46_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC47_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC48_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC49_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC50_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC51_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC52_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC53_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC54_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC54_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC54_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC54_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC54_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC54_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC54_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC54_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC54_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC55_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC55_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC55_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC55_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC55_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC55_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC55_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC55_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC55_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC56_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC56_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC56_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC56_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC56_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC56_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC56_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC56_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC56_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.INTR_2: GPIO interrupt 2 status register for GPIO0-31 +func (o *GPIO_Type) SetINTR_2(value uint32) { + volatile.StoreUint32(&o.INTR_2.Reg, value) +} +func (o *GPIO_Type) GetINTR_2() uint32 { + return volatile.LoadUint32(&o.INTR_2.Reg) +} + +// GPIO.INTR1_2: GPIO interrupt 2 status register for GPIO32-56 +func (o *GPIO_Type) SetINTR1_2_INT1_2(value uint32) { + volatile.StoreUint32(&o.INTR1_2.Reg, volatile.LoadUint32(&o.INTR1_2.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetINTR1_2_INT1_2() uint32 { + return volatile.LoadUint32(&o.INTR1_2.Reg) & 0x1ffffff +} + +// GPIO.INTR_3: GPIO interrupt 3 status register for GPIO0-31 +func (o *GPIO_Type) SetINTR_3(value uint32) { + volatile.StoreUint32(&o.INTR_3.Reg, value) +} +func (o *GPIO_Type) GetINTR_3() uint32 { + return volatile.LoadUint32(&o.INTR_3.Reg) +} + +// GPIO.INTR1_3: GPIO interrupt 3 status register for GPIO32-56 +func (o *GPIO_Type) SetINTR1_3_INT1_3(value uint32) { + volatile.StoreUint32(&o.INTR1_3.Reg, volatile.LoadUint32(&o.INTR1_3.Reg)&^(0x1ffffff)|value) +} +func (o *GPIO_Type) GetINTR1_3_INT1_3() uint32 { + return volatile.LoadUint32(&o.INTR1_3.Reg) & 0x1ffffff +} + +// GPIO.CLOCK_GATE: GPIO clock gate register +func (o *GPIO_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIO.INT_RAW: analog comparator interrupt raw +func (o *GPIO_Type) SetINT_RAW_COMP0_NEG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetINT_RAW_COMP0_NEG_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *GPIO_Type) SetINT_RAW_COMP0_POS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *GPIO_Type) GetINT_RAW_COMP0_POS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *GPIO_Type) SetINT_RAW_COMP0_ALL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetINT_RAW_COMP0_ALL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetINT_RAW_COMP1_NEG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *GPIO_Type) GetINT_RAW_COMP1_NEG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *GPIO_Type) SetINT_RAW_COMP1_POS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *GPIO_Type) GetINT_RAW_COMP1_POS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *GPIO_Type) SetINT_RAW_COMP1_ALL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetINT_RAW_COMP1_ALL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetINT_RAW_BISTOK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetINT_RAW_BISTOK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetINT_RAW_BISTFAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetINT_RAW_BISTFAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} + +// GPIO.INT_ST: analog comparator interrupt status +func (o *GPIO_Type) SetINT_ST_COMP0_NEG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetINT_ST_COMP0_NEG_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *GPIO_Type) SetINT_ST_COMP0_POS_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *GPIO_Type) GetINT_ST_COMP0_POS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *GPIO_Type) SetINT_ST_COMP0_ALL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetINT_ST_COMP0_ALL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetINT_ST_COMP1_NEG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *GPIO_Type) GetINT_ST_COMP1_NEG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *GPIO_Type) SetINT_ST_COMP1_POS_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *GPIO_Type) GetINT_ST_COMP1_POS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *GPIO_Type) SetINT_ST_COMP1_ALL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetINT_ST_COMP1_ALL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetINT_ST_BISTOK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetINT_ST_BISTOK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetINT_ST_BISTFAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetINT_ST_BISTFAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} + +// GPIO.INT_ENA: analog comparator interrupt enable +func (o *GPIO_Type) SetINT_ENA_COMP0_NEG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetINT_ENA_COMP0_NEG_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *GPIO_Type) SetINT_ENA_COMP0_POS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *GPIO_Type) GetINT_ENA_COMP0_POS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *GPIO_Type) SetINT_ENA_COMP0_ALL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetINT_ENA_COMP0_ALL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetINT_ENA_COMP1_NEG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *GPIO_Type) GetINT_ENA_COMP1_NEG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *GPIO_Type) SetINT_ENA_COMP1_POS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *GPIO_Type) GetINT_ENA_COMP1_POS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *GPIO_Type) SetINT_ENA_COMP1_ALL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetINT_ENA_COMP1_ALL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetINT_ENA_BISTOK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetINT_ENA_BISTOK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetINT_ENA_BISTFAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetINT_ENA_BISTFAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} + +// GPIO.INT_CLR: analog comparator interrupt clear +func (o *GPIO_Type) SetINT_CLR_COMP0_NEG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetINT_CLR_COMP0_NEG_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *GPIO_Type) SetINT_CLR_COMP0_POS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *GPIO_Type) GetINT_CLR_COMP0_POS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *GPIO_Type) SetINT_CLR_COMP0_ALL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetINT_CLR_COMP0_ALL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetINT_CLR_COMP1_NEG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *GPIO_Type) GetINT_CLR_COMP1_NEG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *GPIO_Type) SetINT_CLR_COMP1_POS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *GPIO_Type) GetINT_CLR_COMP1_POS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *GPIO_Type) SetINT_CLR_COMP1_ALL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *GPIO_Type) GetINT_CLR_COMP1_ALL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *GPIO_Type) SetINT_CLR_BISTOK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetINT_CLR_BISTOK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetINT_CLR_BISTFAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetINT_CLR_BISTFAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} + +// GPIO.ZERO_DET0_FILTER_CNT: GPIO analog comparator zero detect filter count +func (o *GPIO_Type) SetZERO_DET0_FILTER_CNT(value uint32) { + volatile.StoreUint32(&o.ZERO_DET0_FILTER_CNT.Reg, value) +} +func (o *GPIO_Type) GetZERO_DET0_FILTER_CNT() uint32 { + return volatile.LoadUint32(&o.ZERO_DET0_FILTER_CNT.Reg) +} + +// GPIO.ZERO_DET1_FILTER_CNT: GPIO analog comparator zero detect filter count +func (o *GPIO_Type) SetZERO_DET1_FILTER_CNT(value uint32) { + volatile.StoreUint32(&o.ZERO_DET1_FILTER_CNT.Reg, value) +} +func (o *GPIO_Type) GetZERO_DET1_FILTER_CNT() uint32 { + return volatile.LoadUint32(&o.ZERO_DET1_FILTER_CNT.Reg) +} + +// GPIO.SEND_SEQ: High speed sdio pad bist send sequence +func (o *GPIO_Type) SetSEND_SEQ(value uint32) { + volatile.StoreUint32(&o.SEND_SEQ.Reg, value) +} +func (o *GPIO_Type) GetSEND_SEQ() uint32 { + return volatile.LoadUint32(&o.SEND_SEQ.Reg) +} + +// GPIO.RECIVE_SEQ: High speed sdio pad bist recive sequence +func (o *GPIO_Type) SetRECIVE_SEQ(value uint32) { + volatile.StoreUint32(&o.RECIVE_SEQ.Reg, value) +} +func (o *GPIO_Type) GetRECIVE_SEQ() uint32 { + return volatile.LoadUint32(&o.RECIVE_SEQ.Reg) +} + +// GPIO.BISTIN_SEL: High speed sdio pad bist in pad sel +func (o *GPIO_Type) SetBISTIN_SEL(value uint32) { + volatile.StoreUint32(&o.BISTIN_SEL.Reg, volatile.LoadUint32(&o.BISTIN_SEL.Reg)&^(0xf)|value) +} +func (o *GPIO_Type) GetBISTIN_SEL() uint32 { + return volatile.LoadUint32(&o.BISTIN_SEL.Reg) & 0xf +} + +// GPIO.BIST_CTRL: High speed sdio pad bist control +func (o *GPIO_Type) SetBIST_CTRL_BIST_PAD_OE(value uint32) { + volatile.StoreUint32(&o.BIST_CTRL.Reg, volatile.LoadUint32(&o.BIST_CTRL.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetBIST_CTRL_BIST_PAD_OE() uint32 { + return volatile.LoadUint32(&o.BIST_CTRL.Reg) & 0x1 +} +func (o *GPIO_Type) SetBIST_CTRL_BIST_START(value uint32) { + volatile.StoreUint32(&o.BIST_CTRL.Reg, volatile.LoadUint32(&o.BIST_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *GPIO_Type) GetBIST_CTRL_BIST_START() uint32 { + return (volatile.LoadUint32(&o.BIST_CTRL.Reg) & 0x2) >> 1 +} + +// GPIO.DATE: GPIO version register +func (o *GPIO_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *GPIO_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Sigma-Delta Modulation +type GPIOSD_Type struct { + SIGMADELTA0 volatile.Register32 // 0x0 + SIGMADELTA1 volatile.Register32 // 0x4 + SIGMADELTA2 volatile.Register32 // 0x8 + SIGMADELTA3 volatile.Register32 // 0xC + SIGMADELTA4 volatile.Register32 // 0x10 + SIGMADELTA5 volatile.Register32 // 0x14 + SIGMADELTA6 volatile.Register32 // 0x18 + SIGMADELTA7 volatile.Register32 // 0x1C + CLOCK_GATE volatile.Register32 // 0x20 + SIGMADELTA_MISC volatile.Register32 // 0x24 + _ [8]byte + GLITCH_FILTER_CH0 volatile.Register32 // 0x30 + GLITCH_FILTER_CH1 volatile.Register32 // 0x34 + GLITCH_FILTER_CH2 volatile.Register32 // 0x38 + GLITCH_FILTER_CH3 volatile.Register32 // 0x3C + GLITCH_FILTER_CH4 volatile.Register32 // 0x40 + GLITCH_FILTER_CH5 volatile.Register32 // 0x44 + GLITCH_FILTER_CH6 volatile.Register32 // 0x48 + GLITCH_FILTER_CH7 volatile.Register32 // 0x4C + _ [16]byte + ETM_EVENT_CH0_CFG volatile.Register32 // 0x60 + ETM_EVENT_CH1_CFG volatile.Register32 // 0x64 + ETM_EVENT_CH2_CFG volatile.Register32 // 0x68 + ETM_EVENT_CH3_CFG volatile.Register32 // 0x6C + ETM_EVENT_CH4_CFG volatile.Register32 // 0x70 + ETM_EVENT_CH5_CFG volatile.Register32 // 0x74 + ETM_EVENT_CH6_CFG volatile.Register32 // 0x78 + ETM_EVENT_CH7_CFG volatile.Register32 // 0x7C + _ [32]byte + ETM_TASK_P0_CFG volatile.Register32 // 0xA0 + ETM_TASK_P1_CFG volatile.Register32 // 0xA4 + ETM_TASK_P2_CFG volatile.Register32 // 0xA8 + ETM_TASK_P3_CFG volatile.Register32 // 0xAC + ETM_TASK_P4_CFG volatile.Register32 // 0xB0 + ETM_TASK_P5_CFG volatile.Register32 // 0xB4 + ETM_TASK_P6_CFG volatile.Register32 // 0xB8 + ETM_TASK_P7_CFG volatile.Register32 // 0xBC + ETM_TASK_P8_CFG volatile.Register32 // 0xC0 + ETM_TASK_P9_CFG volatile.Register32 // 0xC4 + ETM_TASK_P10_CFG volatile.Register32 // 0xC8 + ETM_TASK_P11_CFG volatile.Register32 // 0xCC + ETM_TASK_P12_CFG volatile.Register32 // 0xD0 + ETM_TASK_P13_CFG volatile.Register32 // 0xD4 + _ [36]byte + VERSION volatile.Register32 // 0xFC +} + +// GPIOSD.SIGMADELTA0: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA0_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA0_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA1: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA1_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA1_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA2: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA2_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA2_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA3: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA3_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA3_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA4: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA4_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA4_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA4_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA4_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA5: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA5_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA5_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA5_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA5_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA6: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA6_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA6_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA6_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA6_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA7: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA7_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA7_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA7_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA7_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff00) >> 8 +} + +// GPIOSD.CLOCK_GATE: Clock Gating Configure Register +func (o *GPIOSD_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIOSD.SIGMADELTA_MISC: MISC Register +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_FUNCTION_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_FUNCTION_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x40000000) >> 30 +} +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_SPI_SWAP(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_SPI_SWAP() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x80000000) >> 31 +} + +// GPIOSD.GLITCH_FILTER_CH0: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH1: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH2: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH3: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH4: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH5: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH6: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.GLITCH_FILTER_CH7: Glitch Filter Configure Register of Channel%s +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_EN(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_EN() uint32 { + return volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_INPUT_IO_NUM(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x7e)|value<<1) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_INPUT_IO_NUM() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x7e) >> 1 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_THRES(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x1f80)|value<<7) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_THRES() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x1f80) >> 7 +} +func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_WIDTH(value uint32) { + volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x7e000)|value<<13) +} +func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_WIDTH() uint32 { + return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x7e000) >> 13 +} + +// GPIOSD.ETM_EVENT_CH0_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH0_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg) & 0x3f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH0_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH1_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH1_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg) & 0x3f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH1_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH2_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH2_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg) & 0x3f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH2_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH3_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH3_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg) & 0x3f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH3_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH4_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH4_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg) & 0x3f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH4_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH5_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH5_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg) & 0x3f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH5_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH6_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH6_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg) & 0x3f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH6_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_EVENT_CH7_CFG: Etm Config register of Channel%s +func (o *GPIOSD_Type) SetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH7_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_SEL() uint32 { + return volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg) & 0x3f +} +func (o *GPIOSD_Type) SetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_EN(value uint32) { + volatile.StoreUint32(&o.ETM_EVENT_CH7_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIOSD_Type) GetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg) & 0x80) >> 7 +} + +// GPIOSD.ETM_TASK_P0_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P1_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P2_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P3_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P4_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P5_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P6_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P7_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO31_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO31_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO31_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO31_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P8_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO32_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO32_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO32_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO32_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO33_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO33_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO33_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO33_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO34_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO34_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO34_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO34_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO35_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO35_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO35_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO35_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P9_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO36_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO36_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO36_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO36_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO37_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO37_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO37_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO37_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO38_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO38_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO38_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO38_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO39_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO39_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO39_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO39_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P10_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO40_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO40_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO40_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO40_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO41_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO41_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO41_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO41_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO42_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO42_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO42_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO42_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO43_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO43_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO43_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO43_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P11_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO44_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO44_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO44_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO44_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO45_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO45_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO45_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO45_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO46_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO46_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO46_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO46_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO47_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO47_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO47_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO47_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P12_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO48_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO48_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO48_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO48_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO49_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO49_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO49_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO49_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO50_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO50_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO50_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO50_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0xe0000) >> 17 +} +func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO51_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0x1000000)|value<<24) +} +func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO51_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0x1000000) >> 24 +} +func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO51_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0xe000000)|value<<25) +} +func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO51_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0xe000000) >> 25 +} + +// GPIOSD.ETM_TASK_P13_CFG: Etm Configure Register to decide which GPIO been chosen +func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO52_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0x1)|value) +} +func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO52_EN() uint32 { + return volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0x1 +} +func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO52_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0xe)|value<<1) +} +func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO52_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0xe) >> 1 +} +func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO53_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0x100)|value<<8) +} +func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO53_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0x100) >> 8 +} +func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO53_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0xe00)|value<<9) +} +func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO53_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0xe00) >> 9 +} +func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO54_EN(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO54_EN() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0x10000) >> 16 +} +func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO54_SEL(value uint32) { + volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0xe0000)|value<<17) +} +func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO54_SEL() uint32 { + return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0xe0000) >> 17 +} + +// GPIOSD.VERSION: Version Control Register +func (o *GPIOSD_Type) SetVERSION_GPIO_SD_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *GPIOSD_Type) GetVERSION_GPIO_SD_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// H264 Encoder (Core) +type H264_Type struct { + SYS_CTRL volatile.Register32 // 0x0 + GOP_CONF volatile.Register32 // 0x4 + A_SYS_MB_RES volatile.Register32 // 0x8 + A_SYS_CONF volatile.Register32 // 0xC + A_DECI_SCORE volatile.Register32 // 0x10 + A_DECI_SCORE_OFFSET volatile.Register32 // 0x14 + A_RC_CONF0 volatile.Register32 // 0x18 + A_RC_CONF1 volatile.Register32 // 0x1C + A_DB_BYPASS volatile.Register32 // 0x20 + A_ROI_REGION0 volatile.Register32 // 0x24 + A_ROI_REGION1 volatile.Register32 // 0x28 + A_ROI_REGION2 volatile.Register32 // 0x2C + A_ROI_REGION3 volatile.Register32 // 0x30 + A_ROI_REGION4 volatile.Register32 // 0x34 + A_ROI_REGION5 volatile.Register32 // 0x38 + A_ROI_REGION6 volatile.Register32 // 0x3C + A_ROI_REGION7 volatile.Register32 // 0x40 + A_ROI_REGION0_3_QP volatile.Register32 // 0x44 + A_ROI_REGION4_7_QP volatile.Register32 // 0x48 + A_NO_ROI_REGION_QP_OFFSET volatile.Register32 // 0x4C + A_ROI_CONFIG volatile.Register32 // 0x50 + B_SYS_MB_RES volatile.Register32 // 0x54 + B_SYS_CONF volatile.Register32 // 0x58 + B_DECI_SCORE volatile.Register32 // 0x5C + B_DECI_SCORE_OFFSET volatile.Register32 // 0x60 + B_RC_CONF0 volatile.Register32 // 0x64 + B_RC_CONF1 volatile.Register32 // 0x68 + B_DB_BYPASS volatile.Register32 // 0x6C + B_ROI_REGION0 volatile.Register32 // 0x70 + B_ROI_REGION1 volatile.Register32 // 0x74 + B_ROI_REGION2 volatile.Register32 // 0x78 + B_ROI_REGION3 volatile.Register32 // 0x7C + B_ROI_REGION4 volatile.Register32 // 0x80 + B_ROI_REGION5 volatile.Register32 // 0x84 + B_ROI_REGION6 volatile.Register32 // 0x88 + B_ROI_REGION7 volatile.Register32 // 0x8C + B_ROI_REGION0_3_QP volatile.Register32 // 0x90 + B_ROI_REGION4_7_QP volatile.Register32 // 0x94 + B_NO_ROI_REGION_QP_OFFSET volatile.Register32 // 0x98 + B_ROI_CONFIG volatile.Register32 // 0x9C + RC_STATUS0 volatile.Register32 // 0xA0 + RC_STATUS1 volatile.Register32 // 0xA4 + RC_STATUS2 volatile.Register32 // 0xA8 + SLICE_HEADER_REMAIN volatile.Register32 // 0xAC + SLICE_HEADER_BYTE_LENGTH volatile.Register32 // 0xB0 + BS_THRESHOLD volatile.Register32 // 0xB4 + SLICE_HEADER_BYTE0 volatile.Register32 // 0xB8 + SLICE_HEADER_BYTE1 volatile.Register32 // 0xBC + INT_RAW volatile.Register32 // 0xC0 + INT_ST volatile.Register32 // 0xC4 + INT_ENA volatile.Register32 // 0xC8 + INT_CLR volatile.Register32 // 0xCC + CONF volatile.Register32 // 0xD0 + MV_MERGE_CONFIG volatile.Register32 // 0xD4 + DEBUG_DMA_SEL volatile.Register32 // 0xD8 + SYS_STATUS volatile.Register32 // 0xDC + FRAME_CODE_LENGTH volatile.Register32 // 0xE0 + DEBUG_INFO0 volatile.Register32 // 0xE4 + DEBUG_INFO1 volatile.Register32 // 0xE8 + DEBUG_INFO2 volatile.Register32 // 0xEC + DATE volatile.Register32 // 0xF0 +} + +// H264.SYS_CTRL: H264 system level control register. +func (o *H264_Type) SetSYS_CTRL_FRAME_START(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetSYS_CTRL_FRAME_START() uint32 { + return volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x1 +} +func (o *H264_Type) SetSYS_CTRL_DMA_MOVE_START(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *H264_Type) GetSYS_CTRL_DMA_MOVE_START() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x2) >> 1 +} +func (o *H264_Type) SetSYS_CTRL_FRAME_MODE(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *H264_Type) GetSYS_CTRL_FRAME_MODE() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x4) >> 2 +} +func (o *H264_Type) SetSYS_CTRL_SYS_RST_PULSE(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *H264_Type) GetSYS_CTRL_SYS_RST_PULSE() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x8) >> 3 +} + +// H264.GOP_CONF: GOP related configuration register. +func (o *H264_Type) SetGOP_CONF_DUAL_STREAM_MODE(value uint32) { + volatile.StoreUint32(&o.GOP_CONF.Reg, volatile.LoadUint32(&o.GOP_CONF.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetGOP_CONF_DUAL_STREAM_MODE() uint32 { + return volatile.LoadUint32(&o.GOP_CONF.Reg) & 0x1 +} +func (o *H264_Type) SetGOP_CONF_GOP_NUM(value uint32) { + volatile.StoreUint32(&o.GOP_CONF.Reg, volatile.LoadUint32(&o.GOP_CONF.Reg)&^(0x1fe)|value<<1) +} +func (o *H264_Type) GetGOP_CONF_GOP_NUM() uint32 { + return (volatile.LoadUint32(&o.GOP_CONF.Reg) & 0x1fe) >> 1 +} + +// H264.A_SYS_MB_RES: Video A horizontal and vertical MB resolution register. +func (o *H264_Type) SetA_SYS_MB_RES_A_SYS_TOTAL_MB_Y(value uint32) { + volatile.StoreUint32(&o.A_SYS_MB_RES.Reg, volatile.LoadUint32(&o.A_SYS_MB_RES.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_SYS_MB_RES_A_SYS_TOTAL_MB_Y() uint32 { + return volatile.LoadUint32(&o.A_SYS_MB_RES.Reg) & 0x7f +} +func (o *H264_Type) SetA_SYS_MB_RES_A_SYS_TOTAL_MB_X(value uint32) { + volatile.StoreUint32(&o.A_SYS_MB_RES.Reg, volatile.LoadUint32(&o.A_SYS_MB_RES.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_SYS_MB_RES_A_SYS_TOTAL_MB_X() uint32 { + return (volatile.LoadUint32(&o.A_SYS_MB_RES.Reg) & 0x3f80) >> 7 +} + +// H264.A_SYS_CONF: Video A system level configuration register. +func (o *H264_Type) SetA_SYS_CONF_A_DB_TMP_READY_TRIGGER_MB_NUM(value uint32) { + volatile.StoreUint32(&o.A_SYS_CONF.Reg, volatile.LoadUint32(&o.A_SYS_CONF.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_SYS_CONF_A_DB_TMP_READY_TRIGGER_MB_NUM() uint32 { + return volatile.LoadUint32(&o.A_SYS_CONF.Reg) & 0x7f +} +func (o *H264_Type) SetA_SYS_CONF_A_REC_READY_TRIGGER_MB_LINES(value uint32) { + volatile.StoreUint32(&o.A_SYS_CONF.Reg, volatile.LoadUint32(&o.A_SYS_CONF.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_SYS_CONF_A_REC_READY_TRIGGER_MB_LINES() uint32 { + return (volatile.LoadUint32(&o.A_SYS_CONF.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_SYS_CONF_A_INTRA_COST_CMP_OFFSET(value uint32) { + volatile.StoreUint32(&o.A_SYS_CONF.Reg, volatile.LoadUint32(&o.A_SYS_CONF.Reg)&^(0x3fffc000)|value<<14) +} +func (o *H264_Type) GetA_SYS_CONF_A_INTRA_COST_CMP_OFFSET() uint32 { + return (volatile.LoadUint32(&o.A_SYS_CONF.Reg) & 0x3fffc000) >> 14 +} + +// H264.A_DECI_SCORE: Video A luma and chroma MB decimate score Register. +func (o *H264_Type) SetA_DECI_SCORE_A_C_DECI_SCORE(value uint32) { + volatile.StoreUint32(&o.A_DECI_SCORE.Reg, volatile.LoadUint32(&o.A_DECI_SCORE.Reg)&^(0x3ff)|value) +} +func (o *H264_Type) GetA_DECI_SCORE_A_C_DECI_SCORE() uint32 { + return volatile.LoadUint32(&o.A_DECI_SCORE.Reg) & 0x3ff +} +func (o *H264_Type) SetA_DECI_SCORE_A_L_DECI_SCORE(value uint32) { + volatile.StoreUint32(&o.A_DECI_SCORE.Reg, volatile.LoadUint32(&o.A_DECI_SCORE.Reg)&^(0xffc00)|value<<10) +} +func (o *H264_Type) GetA_DECI_SCORE_A_L_DECI_SCORE() uint32 { + return (volatile.LoadUint32(&o.A_DECI_SCORE.Reg) & 0xffc00) >> 10 +} + +// H264.A_DECI_SCORE_OFFSET: Video A luma and chroma MB decimate score offset Register. +func (o *H264_Type) SetA_DECI_SCORE_OFFSET_A_I16X16_DECI_SCORE_OFFSET(value uint32) { + volatile.StoreUint32(&o.A_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg)&^(0x3f)|value) +} +func (o *H264_Type) GetA_DECI_SCORE_OFFSET_A_I16X16_DECI_SCORE_OFFSET() uint32 { + return volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg) & 0x3f +} +func (o *H264_Type) SetA_DECI_SCORE_OFFSET_A_I_CHROMA_DECI_SCORE_OFFSET(value uint32) { + volatile.StoreUint32(&o.A_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg)&^(0xfc0)|value<<6) +} +func (o *H264_Type) GetA_DECI_SCORE_OFFSET_A_I_CHROMA_DECI_SCORE_OFFSET() uint32 { + return (volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg) & 0xfc0) >> 6 +} +func (o *H264_Type) SetA_DECI_SCORE_OFFSET_A_P16X16_DECI_SCORE_OFFSET(value uint32) { + volatile.StoreUint32(&o.A_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg)&^(0x3f000)|value<<12) +} +func (o *H264_Type) GetA_DECI_SCORE_OFFSET_A_P16X16_DECI_SCORE_OFFSET() uint32 { + return (volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg) & 0x3f000) >> 12 +} +func (o *H264_Type) SetA_DECI_SCORE_OFFSET_A_P_CHROMA_DECI_SCORE_OFFSET(value uint32) { + volatile.StoreUint32(&o.A_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg)&^(0xfc0000)|value<<18) +} +func (o *H264_Type) GetA_DECI_SCORE_OFFSET_A_P_CHROMA_DECI_SCORE_OFFSET() uint32 { + return (volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg) & 0xfc0000) >> 18 +} + +// H264.A_RC_CONF0: Video A rate control configuration register0. +func (o *H264_Type) SetA_RC_CONF0_A_QP(value uint32) { + volatile.StoreUint32(&o.A_RC_CONF0.Reg, volatile.LoadUint32(&o.A_RC_CONF0.Reg)&^(0x3f)|value) +} +func (o *H264_Type) GetA_RC_CONF0_A_QP() uint32 { + return volatile.LoadUint32(&o.A_RC_CONF0.Reg) & 0x3f +} +func (o *H264_Type) SetA_RC_CONF0_A_RATE_CTRL_U(value uint32) { + volatile.StoreUint32(&o.A_RC_CONF0.Reg, volatile.LoadUint32(&o.A_RC_CONF0.Reg)&^(0x3fffc0)|value<<6) +} +func (o *H264_Type) GetA_RC_CONF0_A_RATE_CTRL_U() uint32 { + return (volatile.LoadUint32(&o.A_RC_CONF0.Reg) & 0x3fffc0) >> 6 +} +func (o *H264_Type) SetA_RC_CONF0_A_MB_RATE_CTRL_EN(value uint32) { + volatile.StoreUint32(&o.A_RC_CONF0.Reg, volatile.LoadUint32(&o.A_RC_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *H264_Type) GetA_RC_CONF0_A_MB_RATE_CTRL_EN() uint32 { + return (volatile.LoadUint32(&o.A_RC_CONF0.Reg) & 0x400000) >> 22 +} + +// H264.A_RC_CONF1: Video A rate control configuration register1. +func (o *H264_Type) SetA_RC_CONF1_A_CHROMA_DC_QP_DELTA(value uint32) { + volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x7)|value) +} +func (o *H264_Type) GetA_RC_CONF1_A_CHROMA_DC_QP_DELTA() uint32 { + return volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x7 +} +func (o *H264_Type) SetA_RC_CONF1_A_CHROMA_QP_DELTA(value uint32) { + volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x78)|value<<3) +} +func (o *H264_Type) GetA_RC_CONF1_A_CHROMA_QP_DELTA() uint32 { + return (volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x78) >> 3 +} +func (o *H264_Type) SetA_RC_CONF1_A_QP_MIN(value uint32) { + volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *H264_Type) GetA_RC_CONF1_A_QP_MIN() uint32 { + return (volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *H264_Type) SetA_RC_CONF1_A_QP_MAX(value uint32) { + volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x7e000)|value<<13) +} +func (o *H264_Type) GetA_RC_CONF1_A_QP_MAX() uint32 { + return (volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x7e000) >> 13 +} +func (o *H264_Type) SetA_RC_CONF1_A_MAD_FRAME_PRED(value uint32) { + volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x7ff80000)|value<<19) +} +func (o *H264_Type) GetA_RC_CONF1_A_MAD_FRAME_PRED() uint32 { + return (volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x7ff80000) >> 19 +} + +// H264.A_DB_BYPASS: Video A Deblocking bypass register +func (o *H264_Type) SetA_DB_BYPASS_A_BYPASS_DB_FILTER(value uint32) { + volatile.StoreUint32(&o.A_DB_BYPASS.Reg, volatile.LoadUint32(&o.A_DB_BYPASS.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetA_DB_BYPASS_A_BYPASS_DB_FILTER() uint32 { + return volatile.LoadUint32(&o.A_DB_BYPASS.Reg) & 0x1 +} + +// H264.A_ROI_REGION0: Video A H264 ROI region0 range configure register. +func (o *H264_Type) SetA_ROI_REGION0_X(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION0_X() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION0_Y(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION0_Y() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION0_X_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION0_X_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION0_Y_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION0_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetA_ROI_REGION0_EN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetA_ROI_REGION0_EN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0x10000000) >> 28 +} + +// H264.A_ROI_REGION1: Video A H264 ROI region1 range configure register. +func (o *H264_Type) SetA_ROI_REGION1_X(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION1_X() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION1_Y(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION1_Y() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION1_X_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION1_X_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION1_Y_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION1_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetA_ROI_REGION1_EN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetA_ROI_REGION1_EN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0x10000000) >> 28 +} + +// H264.A_ROI_REGION2: Video A H264 ROI region2 range configure register. +func (o *H264_Type) SetA_ROI_REGION2_X(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION2_X() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION2_Y(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION2_Y() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION2_X_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION2_X_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION2_Y_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION2_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetA_ROI_REGION2_EN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetA_ROI_REGION2_EN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0x10000000) >> 28 +} + +// H264.A_ROI_REGION3: Video A H264 ROI region3 range configure register. +func (o *H264_Type) SetA_ROI_REGION3_X(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION3_X() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION3_Y(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION3_Y() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION3_X_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION3_X_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION3_Y_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION3_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetA_ROI_REGION3_EN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetA_ROI_REGION3_EN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0x10000000) >> 28 +} + +// H264.A_ROI_REGION4: Video A H264 ROI region4 range configure register. +func (o *H264_Type) SetA_ROI_REGION4_X(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION4_X() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION4_Y(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION4_Y() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION4_X_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION4_X_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION4_Y_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION4_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetA_ROI_REGION4_EN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetA_ROI_REGION4_EN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0x10000000) >> 28 +} + +// H264.A_ROI_REGION5: Video A H264 ROI region5 range configure register. +func (o *H264_Type) SetA_ROI_REGION5_X(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION5_X() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION5_Y(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION5_Y() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION5_X_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION5_X_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION5_Y_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION5_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetA_ROI_REGION5_EN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetA_ROI_REGION5_EN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0x10000000) >> 28 +} + +// H264.A_ROI_REGION6: Video A H264 ROI region6 range configure register. +func (o *H264_Type) SetA_ROI_REGION6_X(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION6_X() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION6_Y(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION6_Y() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION6_X_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION6_X_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION6_Y_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION6_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetA_ROI_REGION6_EN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetA_ROI_REGION6_EN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0x10000000) >> 28 +} + +// H264.A_ROI_REGION7: Video A H264 ROI region7 range configure register. +func (o *H264_Type) SetA_ROI_REGION7_X(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION7_X() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION7_Y(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION7_Y() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION7_X_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION7_X_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION7_Y_LEN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION7_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetA_ROI_REGION7_EN(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetA_ROI_REGION7_EN() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0x10000000) >> 28 +} + +// H264.A_ROI_REGION0_3_QP: Video A H264 ROI region0, region1,region2,region3 QP register. +func (o *H264_Type) SetA_ROI_REGION0_3_QP_A_ROI_REGION0_QP(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION0_3_QP_A_ROI_REGION0_QP() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION0_3_QP_A_ROI_REGION1_QP(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION0_3_QP_A_ROI_REGION1_QP() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION0_3_QP_A_ROI_REGION2_QP(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION0_3_QP_A_ROI_REGION2_QP() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION0_3_QP_A_ROI_REGION3_QP(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION0_3_QP_A_ROI_REGION3_QP() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg) & 0xfe00000) >> 21 +} + +// H264.A_ROI_REGION4_7_QP: Video A H264 ROI region4, region5,region6,region7 QP register. +func (o *H264_Type) SetA_ROI_REGION4_7_QP_A_ROI_REGION4_QP(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_ROI_REGION4_7_QP_A_ROI_REGION4_QP() uint32 { + return volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg) & 0x7f +} +func (o *H264_Type) SetA_ROI_REGION4_7_QP_A_ROI_REGION5_QP(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetA_ROI_REGION4_7_QP_A_ROI_REGION5_QP() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetA_ROI_REGION4_7_QP_A_ROI_REGION6_QP(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetA_ROI_REGION4_7_QP_A_ROI_REGION6_QP() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetA_ROI_REGION4_7_QP_A_ROI_REGION7_QP(value uint32) { + volatile.StoreUint32(&o.A_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetA_ROI_REGION4_7_QP_A_ROI_REGION7_QP() uint32 { + return (volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg) & 0xfe00000) >> 21 +} + +// H264.A_NO_ROI_REGION_QP_OFFSET: Video A H264 no roi region QP register. +func (o *H264_Type) SetA_NO_ROI_REGION_QP_OFFSET_A_NO_ROI_REGION_QP(value uint32) { + volatile.StoreUint32(&o.A_NO_ROI_REGION_QP_OFFSET.Reg, volatile.LoadUint32(&o.A_NO_ROI_REGION_QP_OFFSET.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetA_NO_ROI_REGION_QP_OFFSET_A_NO_ROI_REGION_QP() uint32 { + return volatile.LoadUint32(&o.A_NO_ROI_REGION_QP_OFFSET.Reg) & 0x7f +} + +// H264.A_ROI_CONFIG: Video A H264 ROI configure register. +func (o *H264_Type) SetA_ROI_CONFIG_A_ROI_EN(value uint32) { + volatile.StoreUint32(&o.A_ROI_CONFIG.Reg, volatile.LoadUint32(&o.A_ROI_CONFIG.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetA_ROI_CONFIG_A_ROI_EN() uint32 { + return volatile.LoadUint32(&o.A_ROI_CONFIG.Reg) & 0x1 +} +func (o *H264_Type) SetA_ROI_CONFIG_A_ROI_MODE(value uint32) { + volatile.StoreUint32(&o.A_ROI_CONFIG.Reg, volatile.LoadUint32(&o.A_ROI_CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *H264_Type) GetA_ROI_CONFIG_A_ROI_MODE() uint32 { + return (volatile.LoadUint32(&o.A_ROI_CONFIG.Reg) & 0x2) >> 1 +} + +// H264.B_SYS_MB_RES: Video B horizontal and vertical MB resolution register. +func (o *H264_Type) SetB_SYS_MB_RES_B_SYS_TOTAL_MB_Y(value uint32) { + volatile.StoreUint32(&o.B_SYS_MB_RES.Reg, volatile.LoadUint32(&o.B_SYS_MB_RES.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_SYS_MB_RES_B_SYS_TOTAL_MB_Y() uint32 { + return volatile.LoadUint32(&o.B_SYS_MB_RES.Reg) & 0x7f +} +func (o *H264_Type) SetB_SYS_MB_RES_B_SYS_TOTAL_MB_X(value uint32) { + volatile.StoreUint32(&o.B_SYS_MB_RES.Reg, volatile.LoadUint32(&o.B_SYS_MB_RES.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_SYS_MB_RES_B_SYS_TOTAL_MB_X() uint32 { + return (volatile.LoadUint32(&o.B_SYS_MB_RES.Reg) & 0x3f80) >> 7 +} + +// H264.B_SYS_CONF: Video B system level configuration register. +func (o *H264_Type) SetB_SYS_CONF_B_DB_TMP_READY_TRIGGER_MB_NUM(value uint32) { + volatile.StoreUint32(&o.B_SYS_CONF.Reg, volatile.LoadUint32(&o.B_SYS_CONF.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_SYS_CONF_B_DB_TMP_READY_TRIGGER_MB_NUM() uint32 { + return volatile.LoadUint32(&o.B_SYS_CONF.Reg) & 0x7f +} +func (o *H264_Type) SetB_SYS_CONF_B_REC_READY_TRIGGER_MB_LINES(value uint32) { + volatile.StoreUint32(&o.B_SYS_CONF.Reg, volatile.LoadUint32(&o.B_SYS_CONF.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_SYS_CONF_B_REC_READY_TRIGGER_MB_LINES() uint32 { + return (volatile.LoadUint32(&o.B_SYS_CONF.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_SYS_CONF_B_INTRA_COST_CMP_OFFSET(value uint32) { + volatile.StoreUint32(&o.B_SYS_CONF.Reg, volatile.LoadUint32(&o.B_SYS_CONF.Reg)&^(0x3fffc000)|value<<14) +} +func (o *H264_Type) GetB_SYS_CONF_B_INTRA_COST_CMP_OFFSET() uint32 { + return (volatile.LoadUint32(&o.B_SYS_CONF.Reg) & 0x3fffc000) >> 14 +} + +// H264.B_DECI_SCORE: Video B luma and chroma MB decimate score Register. +func (o *H264_Type) SetB_DECI_SCORE_B_C_DECI_SCORE(value uint32) { + volatile.StoreUint32(&o.B_DECI_SCORE.Reg, volatile.LoadUint32(&o.B_DECI_SCORE.Reg)&^(0x3ff)|value) +} +func (o *H264_Type) GetB_DECI_SCORE_B_C_DECI_SCORE() uint32 { + return volatile.LoadUint32(&o.B_DECI_SCORE.Reg) & 0x3ff +} +func (o *H264_Type) SetB_DECI_SCORE_B_L_DECI_SCORE(value uint32) { + volatile.StoreUint32(&o.B_DECI_SCORE.Reg, volatile.LoadUint32(&o.B_DECI_SCORE.Reg)&^(0xffc00)|value<<10) +} +func (o *H264_Type) GetB_DECI_SCORE_B_L_DECI_SCORE() uint32 { + return (volatile.LoadUint32(&o.B_DECI_SCORE.Reg) & 0xffc00) >> 10 +} + +// H264.B_DECI_SCORE_OFFSET: Video B luma and chroma MB decimate score offset Register. +func (o *H264_Type) SetB_DECI_SCORE_OFFSET_B_I16X16_DECI_SCORE_OFFSET(value uint32) { + volatile.StoreUint32(&o.B_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg)&^(0x3f)|value) +} +func (o *H264_Type) GetB_DECI_SCORE_OFFSET_B_I16X16_DECI_SCORE_OFFSET() uint32 { + return volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg) & 0x3f +} +func (o *H264_Type) SetB_DECI_SCORE_OFFSET_B_I_CHROMA_DECI_SCORE_OFFSET(value uint32) { + volatile.StoreUint32(&o.B_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg)&^(0xfc0)|value<<6) +} +func (o *H264_Type) GetB_DECI_SCORE_OFFSET_B_I_CHROMA_DECI_SCORE_OFFSET() uint32 { + return (volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg) & 0xfc0) >> 6 +} +func (o *H264_Type) SetB_DECI_SCORE_OFFSET_B_P16X16_DECI_SCORE_OFFSET(value uint32) { + volatile.StoreUint32(&o.B_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg)&^(0x3f000)|value<<12) +} +func (o *H264_Type) GetB_DECI_SCORE_OFFSET_B_P16X16_DECI_SCORE_OFFSET() uint32 { + return (volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg) & 0x3f000) >> 12 +} +func (o *H264_Type) SetB_DECI_SCORE_OFFSET_B_P_CHROMA_DECI_SCORE_OFFSET(value uint32) { + volatile.StoreUint32(&o.B_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg)&^(0xfc0000)|value<<18) +} +func (o *H264_Type) GetB_DECI_SCORE_OFFSET_B_P_CHROMA_DECI_SCORE_OFFSET() uint32 { + return (volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg) & 0xfc0000) >> 18 +} + +// H264.B_RC_CONF0: Video B rate control configuration register0. +func (o *H264_Type) SetB_RC_CONF0_B_QP(value uint32) { + volatile.StoreUint32(&o.B_RC_CONF0.Reg, volatile.LoadUint32(&o.B_RC_CONF0.Reg)&^(0x3f)|value) +} +func (o *H264_Type) GetB_RC_CONF0_B_QP() uint32 { + return volatile.LoadUint32(&o.B_RC_CONF0.Reg) & 0x3f +} +func (o *H264_Type) SetB_RC_CONF0_B_RATE_CTRL_U(value uint32) { + volatile.StoreUint32(&o.B_RC_CONF0.Reg, volatile.LoadUint32(&o.B_RC_CONF0.Reg)&^(0x3fffc0)|value<<6) +} +func (o *H264_Type) GetB_RC_CONF0_B_RATE_CTRL_U() uint32 { + return (volatile.LoadUint32(&o.B_RC_CONF0.Reg) & 0x3fffc0) >> 6 +} +func (o *H264_Type) SetB_RC_CONF0_B_MB_RATE_CTRL_EN(value uint32) { + volatile.StoreUint32(&o.B_RC_CONF0.Reg, volatile.LoadUint32(&o.B_RC_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *H264_Type) GetB_RC_CONF0_B_MB_RATE_CTRL_EN() uint32 { + return (volatile.LoadUint32(&o.B_RC_CONF0.Reg) & 0x400000) >> 22 +} + +// H264.B_RC_CONF1: Video B rate control configuration register1. +func (o *H264_Type) SetB_RC_CONF1_B_CHROMA_DC_QP_DELTA(value uint32) { + volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x7)|value) +} +func (o *H264_Type) GetB_RC_CONF1_B_CHROMA_DC_QP_DELTA() uint32 { + return volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x7 +} +func (o *H264_Type) SetB_RC_CONF1_B_CHROMA_QP_DELTA(value uint32) { + volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x78)|value<<3) +} +func (o *H264_Type) GetB_RC_CONF1_B_CHROMA_QP_DELTA() uint32 { + return (volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x78) >> 3 +} +func (o *H264_Type) SetB_RC_CONF1_B_QP_MIN(value uint32) { + volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *H264_Type) GetB_RC_CONF1_B_QP_MIN() uint32 { + return (volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *H264_Type) SetB_RC_CONF1_B_QP_MAX(value uint32) { + volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x7e000)|value<<13) +} +func (o *H264_Type) GetB_RC_CONF1_B_QP_MAX() uint32 { + return (volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x7e000) >> 13 +} +func (o *H264_Type) SetB_RC_CONF1_B_MAD_FRAME_PRED(value uint32) { + volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x7ff80000)|value<<19) +} +func (o *H264_Type) GetB_RC_CONF1_B_MAD_FRAME_PRED() uint32 { + return (volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x7ff80000) >> 19 +} + +// H264.B_DB_BYPASS: Video B Deblocking bypass register +func (o *H264_Type) SetB_DB_BYPASS_B_BYPASS_DB_FILTER(value uint32) { + volatile.StoreUint32(&o.B_DB_BYPASS.Reg, volatile.LoadUint32(&o.B_DB_BYPASS.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetB_DB_BYPASS_B_BYPASS_DB_FILTER() uint32 { + return volatile.LoadUint32(&o.B_DB_BYPASS.Reg) & 0x1 +} + +// H264.B_ROI_REGION0: Video B H264 ROI region0 range configure register. +func (o *H264_Type) SetB_ROI_REGION0_X(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION0_X() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION0_Y(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION0_Y() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION0_X_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION0_X_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION0_Y_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION0_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetB_ROI_REGION0_EN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetB_ROI_REGION0_EN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0x10000000) >> 28 +} + +// H264.B_ROI_REGION1: Video B H264 ROI region1 range configure register. +func (o *H264_Type) SetB_ROI_REGION1_X(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION1_X() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION1_Y(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION1_Y() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION1_X_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION1_X_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION1_Y_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION1_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetB_ROI_REGION1_EN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetB_ROI_REGION1_EN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0x10000000) >> 28 +} + +// H264.B_ROI_REGION2: Video B H264 ROI region2 range configure register. +func (o *H264_Type) SetB_ROI_REGION2_X(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION2_X() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION2_Y(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION2_Y() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION2_X_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION2_X_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION2_Y_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION2_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetB_ROI_REGION2_EN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetB_ROI_REGION2_EN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0x10000000) >> 28 +} + +// H264.B_ROI_REGION3: Video B H264 ROI region3 range configure register. +func (o *H264_Type) SetB_ROI_REGION3_X(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION3_X() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION3_Y(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION3_Y() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION3_X_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION3_X_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION3_Y_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION3_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetB_ROI_REGION3_EN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetB_ROI_REGION3_EN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0x10000000) >> 28 +} + +// H264.B_ROI_REGION4: Video B H264 ROI region4 range configure register. +func (o *H264_Type) SetB_ROI_REGION4_X(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION4_X() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION4_Y(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION4_Y() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION4_X_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION4_X_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION4_Y_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION4_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetB_ROI_REGION4_EN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetB_ROI_REGION4_EN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0x10000000) >> 28 +} + +// H264.B_ROI_REGION5: Video B H264 ROI region5 range configure register. +func (o *H264_Type) SetB_ROI_REGION5_X(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION5_X() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION5_Y(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION5_Y() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION5_X_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION5_X_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION5_Y_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION5_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetB_ROI_REGION5_EN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetB_ROI_REGION5_EN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0x10000000) >> 28 +} + +// H264.B_ROI_REGION6: Video B H264 ROI region6 range configure register. +func (o *H264_Type) SetB_ROI_REGION6_X(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION6_X() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION6_Y(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION6_Y() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION6_X_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION6_X_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION6_Y_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION6_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetB_ROI_REGION6_EN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetB_ROI_REGION6_EN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0x10000000) >> 28 +} + +// H264.B_ROI_REGION7: Video B H264 ROI region7 range configure register. +func (o *H264_Type) SetB_ROI_REGION7_X(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION7_X() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION7_Y(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION7_Y() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION7_X_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION7_X_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION7_Y_LEN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION7_Y_LEN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0xfe00000) >> 21 +} +func (o *H264_Type) SetB_ROI_REGION7_EN(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0x10000000)|value<<28) +} +func (o *H264_Type) GetB_ROI_REGION7_EN() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0x10000000) >> 28 +} + +// H264.B_ROI_REGION0_3_QP: Video B H264 ROI region0, region1,region2,region3 QP register. +func (o *H264_Type) SetB_ROI_REGION0_3_QP_B_ROI_REGION0_QP(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION0_3_QP_B_ROI_REGION0_QP() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION0_3_QP_B_ROI_REGION1_QP(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION0_3_QP_B_ROI_REGION1_QP() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION0_3_QP_B_ROI_REGION2_QP(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION0_3_QP_B_ROI_REGION2_QP() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION0_3_QP_B_ROI_REGION3_QP(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION0_3_QP_B_ROI_REGION3_QP() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg) & 0xfe00000) >> 21 +} + +// H264.B_ROI_REGION4_7_QP: Video B H264 ROI region4, region5,region6,region7 QP register. +func (o *H264_Type) SetB_ROI_REGION4_7_QP_B_ROI_REGION4_QP(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_ROI_REGION4_7_QP_B_ROI_REGION4_QP() uint32 { + return volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg) & 0x7f +} +func (o *H264_Type) SetB_ROI_REGION4_7_QP_B_ROI_REGION5_QP(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg)&^(0x3f80)|value<<7) +} +func (o *H264_Type) GetB_ROI_REGION4_7_QP_B_ROI_REGION5_QP() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg) & 0x3f80) >> 7 +} +func (o *H264_Type) SetB_ROI_REGION4_7_QP_B_ROI_REGION6_QP(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg)&^(0x1fc000)|value<<14) +} +func (o *H264_Type) GetB_ROI_REGION4_7_QP_B_ROI_REGION6_QP() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg) & 0x1fc000) >> 14 +} +func (o *H264_Type) SetB_ROI_REGION4_7_QP_B_ROI_REGION7_QP(value uint32) { + volatile.StoreUint32(&o.B_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg)&^(0xfe00000)|value<<21) +} +func (o *H264_Type) GetB_ROI_REGION4_7_QP_B_ROI_REGION7_QP() uint32 { + return (volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg) & 0xfe00000) >> 21 +} + +// H264.B_NO_ROI_REGION_QP_OFFSET: Video B H264 no roi region QP register. +func (o *H264_Type) SetB_NO_ROI_REGION_QP_OFFSET_B_NO_ROI_REGION_QP(value uint32) { + volatile.StoreUint32(&o.B_NO_ROI_REGION_QP_OFFSET.Reg, volatile.LoadUint32(&o.B_NO_ROI_REGION_QP_OFFSET.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetB_NO_ROI_REGION_QP_OFFSET_B_NO_ROI_REGION_QP() uint32 { + return volatile.LoadUint32(&o.B_NO_ROI_REGION_QP_OFFSET.Reg) & 0x7f +} + +// H264.B_ROI_CONFIG: Video B H264 ROI configure register. +func (o *H264_Type) SetB_ROI_CONFIG_B_ROI_EN(value uint32) { + volatile.StoreUint32(&o.B_ROI_CONFIG.Reg, volatile.LoadUint32(&o.B_ROI_CONFIG.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetB_ROI_CONFIG_B_ROI_EN() uint32 { + return volatile.LoadUint32(&o.B_ROI_CONFIG.Reg) & 0x1 +} +func (o *H264_Type) SetB_ROI_CONFIG_B_ROI_MODE(value uint32) { + volatile.StoreUint32(&o.B_ROI_CONFIG.Reg, volatile.LoadUint32(&o.B_ROI_CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *H264_Type) GetB_ROI_CONFIG_B_ROI_MODE() uint32 { + return (volatile.LoadUint32(&o.B_ROI_CONFIG.Reg) & 0x2) >> 1 +} + +// H264.RC_STATUS0: Rate control status register0. +func (o *H264_Type) SetRC_STATUS0_FRAME_MAD_SUM(value uint32) { + volatile.StoreUint32(&o.RC_STATUS0.Reg, volatile.LoadUint32(&o.RC_STATUS0.Reg)&^(0x1fffff)|value) +} +func (o *H264_Type) GetRC_STATUS0_FRAME_MAD_SUM() uint32 { + return volatile.LoadUint32(&o.RC_STATUS0.Reg) & 0x1fffff +} + +// H264.RC_STATUS1: Rate control status register1. +func (o *H264_Type) SetRC_STATUS1_FRAME_ENC_BITS(value uint32) { + volatile.StoreUint32(&o.RC_STATUS1.Reg, volatile.LoadUint32(&o.RC_STATUS1.Reg)&^(0x7ffffff)|value) +} +func (o *H264_Type) GetRC_STATUS1_FRAME_ENC_BITS() uint32 { + return volatile.LoadUint32(&o.RC_STATUS1.Reg) & 0x7ffffff +} + +// H264.RC_STATUS2: Rate control status register2. +func (o *H264_Type) SetRC_STATUS2_FRAME_QP_SUM(value uint32) { + volatile.StoreUint32(&o.RC_STATUS2.Reg, volatile.LoadUint32(&o.RC_STATUS2.Reg)&^(0x7ffff)|value) +} +func (o *H264_Type) GetRC_STATUS2_FRAME_QP_SUM() uint32 { + return volatile.LoadUint32(&o.RC_STATUS2.Reg) & 0x7ffff +} + +// H264.SLICE_HEADER_REMAIN: Frame Slice Header remain bit register. +func (o *H264_Type) SetSLICE_HEADER_REMAIN_SLICE_REMAIN_BITLENGTH(value uint32) { + volatile.StoreUint32(&o.SLICE_HEADER_REMAIN.Reg, volatile.LoadUint32(&o.SLICE_HEADER_REMAIN.Reg)&^(0x7)|value) +} +func (o *H264_Type) GetSLICE_HEADER_REMAIN_SLICE_REMAIN_BITLENGTH() uint32 { + return volatile.LoadUint32(&o.SLICE_HEADER_REMAIN.Reg) & 0x7 +} +func (o *H264_Type) SetSLICE_HEADER_REMAIN_SLICE_REMAIN_BIT(value uint32) { + volatile.StoreUint32(&o.SLICE_HEADER_REMAIN.Reg, volatile.LoadUint32(&o.SLICE_HEADER_REMAIN.Reg)&^(0x7f8)|value<<3) +} +func (o *H264_Type) GetSLICE_HEADER_REMAIN_SLICE_REMAIN_BIT() uint32 { + return (volatile.LoadUint32(&o.SLICE_HEADER_REMAIN.Reg) & 0x7f8) >> 3 +} + +// H264.SLICE_HEADER_BYTE_LENGTH: Frame Slice Header byte length register. +func (o *H264_Type) SetSLICE_HEADER_BYTE_LENGTH_SLICE_BYTE_LENGTH(value uint32) { + volatile.StoreUint32(&o.SLICE_HEADER_BYTE_LENGTH.Reg, volatile.LoadUint32(&o.SLICE_HEADER_BYTE_LENGTH.Reg)&^(0xf)|value) +} +func (o *H264_Type) GetSLICE_HEADER_BYTE_LENGTH_SLICE_BYTE_LENGTH() uint32 { + return volatile.LoadUint32(&o.SLICE_HEADER_BYTE_LENGTH.Reg) & 0xf +} + +// H264.BS_THRESHOLD: Bitstream buffer overflow threshold register +func (o *H264_Type) SetBS_THRESHOLD_BS_BUFFER_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.BS_THRESHOLD.Reg, volatile.LoadUint32(&o.BS_THRESHOLD.Reg)&^(0x7f)|value) +} +func (o *H264_Type) GetBS_THRESHOLD_BS_BUFFER_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.BS_THRESHOLD.Reg) & 0x7f +} + +// H264.SLICE_HEADER_BYTE0: Frame Slice Header byte low 32 bit register. +func (o *H264_Type) SetSLICE_HEADER_BYTE0(value uint32) { + volatile.StoreUint32(&o.SLICE_HEADER_BYTE0.Reg, value) +} +func (o *H264_Type) GetSLICE_HEADER_BYTE0() uint32 { + return volatile.LoadUint32(&o.SLICE_HEADER_BYTE0.Reg) +} + +// H264.SLICE_HEADER_BYTE1: Frame Slice Header byte high 32 bit register. +func (o *H264_Type) SetSLICE_HEADER_BYTE1(value uint32) { + volatile.StoreUint32(&o.SLICE_HEADER_BYTE1.Reg, value) +} +func (o *H264_Type) GetSLICE_HEADER_BYTE1() uint32 { + return volatile.LoadUint32(&o.SLICE_HEADER_BYTE1.Reg) +} + +// H264.INT_RAW: Interrupt raw status register +func (o *H264_Type) SetINT_RAW_DB_TMP_READY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetINT_RAW_DB_TMP_READY_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *H264_Type) SetINT_RAW_REC_READY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *H264_Type) GetINT_RAW_REC_READY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *H264_Type) SetINT_RAW_FRAME_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *H264_Type) GetINT_RAW_FRAME_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *H264_Type) SetINT_RAW_DMA_MOVE_2MB_LINE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *H264_Type) GetINT_RAW_DMA_MOVE_2MB_LINE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// H264.INT_ST: Interrupt masked status register +func (o *H264_Type) SetINT_ST_DB_TMP_READY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetINT_ST_DB_TMP_READY_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *H264_Type) SetINT_ST_REC_READY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *H264_Type) GetINT_ST_REC_READY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *H264_Type) SetINT_ST_FRAME_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *H264_Type) GetINT_ST_FRAME_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *H264_Type) SetINT_ST_DMA_MOVE_2MB_LINE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *H264_Type) GetINT_ST_DMA_MOVE_2MB_LINE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// H264.INT_ENA: Interrupt enable register +func (o *H264_Type) SetINT_ENA_DB_TMP_READY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetINT_ENA_DB_TMP_READY_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *H264_Type) SetINT_ENA_REC_READY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *H264_Type) GetINT_ENA_REC_READY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *H264_Type) SetINT_ENA_FRAME_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *H264_Type) GetINT_ENA_FRAME_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *H264_Type) SetINT_ENA_DMA_MOVE_2MB_LINE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *H264_Type) GetINT_ENA_DMA_MOVE_2MB_LINE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// H264.INT_CLR: Interrupt clear register +func (o *H264_Type) SetINT_CLR_DB_TMP_READY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetINT_CLR_DB_TMP_READY_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *H264_Type) SetINT_CLR_REC_READY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *H264_Type) GetINT_CLR_REC_READY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *H264_Type) SetINT_CLR_FRAME_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *H264_Type) GetINT_CLR_FRAME_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *H264_Type) SetINT_CLR_DMA_MOVE_2MB_LINE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *H264_Type) GetINT_CLR_DMA_MOVE_2MB_LINE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// H264.CONF: General configuration register. +func (o *H264_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetCONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *H264_Type) SetCONF_REC_RAM_CLK_EN2(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2)|value<<1) +} +func (o *H264_Type) GetCONF_REC_RAM_CLK_EN2() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2) >> 1 +} +func (o *H264_Type) SetCONF_REC_RAM_CLK_EN1(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2) +} +func (o *H264_Type) GetCONF_REC_RAM_CLK_EN1() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2 +} +func (o *H264_Type) SetCONF_QUANT_RAM_CLK_EN2(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3) +} +func (o *H264_Type) GetCONF_QUANT_RAM_CLK_EN2() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3 +} +func (o *H264_Type) SetCONF_QUANT_RAM_CLK_EN1(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4) +} +func (o *H264_Type) GetCONF_QUANT_RAM_CLK_EN1() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4 +} +func (o *H264_Type) SetCONF_PRE_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5) +} +func (o *H264_Type) GetCONF_PRE_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5 +} +func (o *H264_Type) SetCONF_MVD_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40)|value<<6) +} +func (o *H264_Type) GetCONF_MVD_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40) >> 6 +} +func (o *H264_Type) SetCONF_MC_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80)|value<<7) +} +func (o *H264_Type) GetCONF_MC_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80) >> 7 +} +func (o *H264_Type) SetCONF_REF_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x100)|value<<8) +} +func (o *H264_Type) GetCONF_REF_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x100) >> 8 +} +func (o *H264_Type) SetCONF_I4X4_REF_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x200)|value<<9) +} +func (o *H264_Type) GetCONF_I4X4_REF_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x200) >> 9 +} +func (o *H264_Type) SetCONF_IME_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400)|value<<10) +} +func (o *H264_Type) GetCONF_IME_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400) >> 10 +} +func (o *H264_Type) SetCONF_FME_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800)|value<<11) +} +func (o *H264_Type) GetCONF_FME_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800) >> 11 +} +func (o *H264_Type) SetCONF_FETCH_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000)|value<<12) +} +func (o *H264_Type) GetCONF_FETCH_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000) >> 12 +} +func (o *H264_Type) SetCONF_DB_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000)|value<<13) +} +func (o *H264_Type) GetCONF_DB_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000) >> 13 +} +func (o *H264_Type) SetCONF_CUR_MB_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000)|value<<14) +} +func (o *H264_Type) GetCONF_CUR_MB_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000) >> 14 +} +func (o *H264_Type) SetCONF_CAVLC_RAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000)|value<<15) +} +func (o *H264_Type) GetCONF_CAVLC_RAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000) >> 15 +} +func (o *H264_Type) SetCONF_IME_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000)|value<<16) +} +func (o *H264_Type) GetCONF_IME_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000) >> 16 +} +func (o *H264_Type) SetCONF_FME_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000)|value<<17) +} +func (o *H264_Type) GetCONF_FME_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000) >> 17 +} +func (o *H264_Type) SetCONF_MC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000)|value<<18) +} +func (o *H264_Type) GetCONF_MC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000) >> 18 +} +func (o *H264_Type) SetCONF_INTERPOLATOR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000)|value<<19) +} +func (o *H264_Type) GetCONF_INTERPOLATOR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000) >> 19 +} +func (o *H264_Type) SetCONF_DB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x100000)|value<<20) +} +func (o *H264_Type) GetCONF_DB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x100000) >> 20 +} +func (o *H264_Type) SetCONF_CLAVLC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x200000)|value<<21) +} +func (o *H264_Type) GetCONF_CLAVLC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x200000) >> 21 +} +func (o *H264_Type) SetCONF_INTRA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22) +} +func (o *H264_Type) GetCONF_INTRA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22 +} +func (o *H264_Type) SetCONF_DECI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23) +} +func (o *H264_Type) GetCONF_DECI_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23 +} +func (o *H264_Type) SetCONF_BS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_Type) GetCONF_BS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24 +} +func (o *H264_Type) SetCONF_MV_MERGE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_Type) GetCONF_MV_MERGE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25 +} + +// H264.MV_MERGE_CONFIG: Mv merge configuration register. +func (o *H264_Type) SetMV_MERGE_CONFIG_MV_MERGE_TYPE(value uint32) { + volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x3)|value) +} +func (o *H264_Type) GetMV_MERGE_CONFIG_MV_MERGE_TYPE() uint32 { + return volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x3 +} +func (o *H264_Type) SetMV_MERGE_CONFIG_INT_MV_OUT_EN(value uint32) { + volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x4)|value<<2) +} +func (o *H264_Type) GetMV_MERGE_CONFIG_INT_MV_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x4) >> 2 +} +func (o *H264_Type) SetMV_MERGE_CONFIG_A_MV_MERGE_EN(value uint32) { + volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x8)|value<<3) +} +func (o *H264_Type) GetMV_MERGE_CONFIG_A_MV_MERGE_EN() uint32 { + return (volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x8) >> 3 +} +func (o *H264_Type) SetMV_MERGE_CONFIG_B_MV_MERGE_EN(value uint32) { + volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x10)|value<<4) +} +func (o *H264_Type) GetMV_MERGE_CONFIG_B_MV_MERGE_EN() uint32 { + return (volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x10) >> 4 +} +func (o *H264_Type) SetMV_MERGE_CONFIG_MB_VALID_NUM(value uint32) { + volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x3ffe0)|value<<5) +} +func (o *H264_Type) GetMV_MERGE_CONFIG_MB_VALID_NUM() uint32 { + return (volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x3ffe0) >> 5 +} + +// H264.DEBUG_DMA_SEL: Debug H264 DMA select register +func (o *H264_Type) SetDEBUG_DMA_SEL_DBG_DMA_SEL(value uint32) { + volatile.StoreUint32(&o.DEBUG_DMA_SEL.Reg, volatile.LoadUint32(&o.DEBUG_DMA_SEL.Reg)&^(0xff)|value) +} +func (o *H264_Type) GetDEBUG_DMA_SEL_DBG_DMA_SEL() uint32 { + return volatile.LoadUint32(&o.DEBUG_DMA_SEL.Reg) & 0xff +} + +// H264.SYS_STATUS: System status register. +func (o *H264_Type) SetSYS_STATUS_FRAME_NUM(value uint32) { + volatile.StoreUint32(&o.SYS_STATUS.Reg, volatile.LoadUint32(&o.SYS_STATUS.Reg)&^(0x1ff)|value) +} +func (o *H264_Type) GetSYS_STATUS_FRAME_NUM() uint32 { + return volatile.LoadUint32(&o.SYS_STATUS.Reg) & 0x1ff +} +func (o *H264_Type) SetSYS_STATUS_DUAL_STREAM_SEL(value uint32) { + volatile.StoreUint32(&o.SYS_STATUS.Reg, volatile.LoadUint32(&o.SYS_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *H264_Type) GetSYS_STATUS_DUAL_STREAM_SEL() uint32 { + return (volatile.LoadUint32(&o.SYS_STATUS.Reg) & 0x200) >> 9 +} +func (o *H264_Type) SetSYS_STATUS_INTRA_FLAG(value uint32) { + volatile.StoreUint32(&o.SYS_STATUS.Reg, volatile.LoadUint32(&o.SYS_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *H264_Type) GetSYS_STATUS_INTRA_FLAG() uint32 { + return (volatile.LoadUint32(&o.SYS_STATUS.Reg) & 0x400) >> 10 +} + +// H264.FRAME_CODE_LENGTH: Frame code byte length register. +func (o *H264_Type) SetFRAME_CODE_LENGTH(value uint32) { + volatile.StoreUint32(&o.FRAME_CODE_LENGTH.Reg, volatile.LoadUint32(&o.FRAME_CODE_LENGTH.Reg)&^(0xffffff)|value) +} +func (o *H264_Type) GetFRAME_CODE_LENGTH() uint32 { + return volatile.LoadUint32(&o.FRAME_CODE_LENGTH.Reg) & 0xffffff +} + +// H264.DEBUG_INFO0: Debug information register0. +func (o *H264_Type) SetDEBUG_INFO0_TOP_CTRL_INTER_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0xf)|value) +} +func (o *H264_Type) GetDEBUG_INFO0_TOP_CTRL_INTER_DEBUG_STATE() uint32 { + return volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0xf +} +func (o *H264_Type) SetDEBUG_INFO0_TOP_CTRL_INTRA_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x70)|value<<4) +} +func (o *H264_Type) GetDEBUG_INFO0_TOP_CTRL_INTRA_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x70) >> 4 +} +func (o *H264_Type) SetDEBUG_INFO0_P_I_CMP_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x380)|value<<7) +} +func (o *H264_Type) GetDEBUG_INFO0_P_I_CMP_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x380) >> 7 +} +func (o *H264_Type) SetDEBUG_INFO0_MVD_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x1c00)|value<<10) +} +func (o *H264_Type) GetDEBUG_INFO0_MVD_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x1c00) >> 10 +} +func (o *H264_Type) SetDEBUG_INFO0_MC_CHROMA_IP_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x2000)|value<<13) +} +func (o *H264_Type) GetDEBUG_INFO0_MC_CHROMA_IP_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x2000) >> 13 +} +func (o *H264_Type) SetDEBUG_INFO0_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x3c000)|value<<14) +} +func (o *H264_Type) GetDEBUG_INFO0_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x3c000) >> 14 +} +func (o *H264_Type) SetDEBUG_INFO0_INTRA_4X4_CTRL_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x3c0000)|value<<18) +} +func (o *H264_Type) GetDEBUG_INFO0_INTRA_4X4_CTRL_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x3c0000) >> 18 +} +func (o *H264_Type) SetDEBUG_INFO0_INTRA_TOP_CTRL_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x1c00000)|value<<22) +} +func (o *H264_Type) GetDEBUG_INFO0_INTRA_TOP_CTRL_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x1c00000) >> 22 +} +func (o *H264_Type) SetDEBUG_INFO0_IME_CTRL_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0xe000000)|value<<25) +} +func (o *H264_Type) GetDEBUG_INFO0_IME_CTRL_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0xe000000) >> 25 +} + +// H264.DEBUG_INFO1: Debug information register1. +func (o *H264_Type) SetDEBUG_INFO1_FME_CTRL_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0x7)|value) +} +func (o *H264_Type) GetDEBUG_INFO1_FME_CTRL_DEBUG_STATE() uint32 { + return volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0x7 +} +func (o *H264_Type) SetDEBUG_INFO1_DECI_CALC_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0x18)|value<<3) +} +func (o *H264_Type) GetDEBUG_INFO1_DECI_CALC_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0x18) >> 3 +} +func (o *H264_Type) SetDEBUG_INFO1_DB_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0xe0)|value<<5) +} +func (o *H264_Type) GetDEBUG_INFO1_DB_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0xe0) >> 5 +} +func (o *H264_Type) SetDEBUG_INFO1_CAVLC_ENC_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0xf00)|value<<8) +} +func (o *H264_Type) GetDEBUG_INFO1_CAVLC_ENC_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0xf00) >> 8 +} +func (o *H264_Type) SetDEBUG_INFO1_CAVLC_SCAN_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0xf000)|value<<12) +} +func (o *H264_Type) GetDEBUG_INFO1_CAVLC_SCAN_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0xf000) >> 12 +} +func (o *H264_Type) SetDEBUG_INFO1_CAVLC_CTRL_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0x30000)|value<<16) +} +func (o *H264_Type) GetDEBUG_INFO1_CAVLC_CTRL_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0x30000) >> 16 +} +func (o *H264_Type) SetDEBUG_INFO1_BS_BUFFER_DEBUG_STATE(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0x40000)|value<<18) +} +func (o *H264_Type) GetDEBUG_INFO1_BS_BUFFER_DEBUG_STATE() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0x40000) >> 18 +} + +// H264.DEBUG_INFO2: Debug information register2. +func (o *H264_Type) SetDEBUG_INFO2_P_RC_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x1)|value) +} +func (o *H264_Type) GetDEBUG_INFO2_P_RC_DONE_DEBUG_FLAG() uint32 { + return volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x1 +} +func (o *H264_Type) SetDEBUG_INFO2_P_P_I_CMP_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x2)|value<<1) +} +func (o *H264_Type) GetDEBUG_INFO2_P_P_I_CMP_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x2) >> 1 +} +func (o *H264_Type) SetDEBUG_INFO2_P_MV_MERGE_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x4)|value<<2) +} +func (o *H264_Type) GetDEBUG_INFO2_P_MV_MERGE_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x4) >> 2 +} +func (o *H264_Type) SetDEBUG_INFO2_P_MOVE_ORI_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x8)|value<<3) +} +func (o *H264_Type) GetDEBUG_INFO2_P_MOVE_ORI_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x8) >> 3 +} +func (o *H264_Type) SetDEBUG_INFO2_P_MC_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x10)|value<<4) +} +func (o *H264_Type) GetDEBUG_INFO2_P_MC_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x10) >> 4 +} +func (o *H264_Type) SetDEBUG_INFO2_P_IME_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x20)|value<<5) +} +func (o *H264_Type) GetDEBUG_INFO2_P_IME_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x20) >> 5 +} +func (o *H264_Type) SetDEBUG_INFO2_P_GET_ORI_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x40)|value<<6) +} +func (o *H264_Type) GetDEBUG_INFO2_P_GET_ORI_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x40) >> 6 +} +func (o *H264_Type) SetDEBUG_INFO2_P_FME_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x80)|value<<7) +} +func (o *H264_Type) GetDEBUG_INFO2_P_FME_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x80) >> 7 +} +func (o *H264_Type) SetDEBUG_INFO2_P_FETCH_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x100)|value<<8) +} +func (o *H264_Type) GetDEBUG_INFO2_P_FETCH_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x100) >> 8 +} +func (o *H264_Type) SetDEBUG_INFO2_P_DB_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x200)|value<<9) +} +func (o *H264_Type) GetDEBUG_INFO2_P_DB_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x200) >> 9 +} +func (o *H264_Type) SetDEBUG_INFO2_P_BS_BUF_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x400)|value<<10) +} +func (o *H264_Type) GetDEBUG_INFO2_P_BS_BUF_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x400) >> 10 +} +func (o *H264_Type) SetDEBUG_INFO2_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x800)|value<<11) +} +func (o *H264_Type) GetDEBUG_INFO2_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x800) >> 11 +} +func (o *H264_Type) SetDEBUG_INFO2_I_P_I_CMP_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x1000)|value<<12) +} +func (o *H264_Type) GetDEBUG_INFO2_I_P_I_CMP_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x1000) >> 12 +} +func (o *H264_Type) SetDEBUG_INFO2_I_MOVE_ORI_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x2000)|value<<13) +} +func (o *H264_Type) GetDEBUG_INFO2_I_MOVE_ORI_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x2000) >> 13 +} +func (o *H264_Type) SetDEBUG_INFO2_I_GET_ORI_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x4000)|value<<14) +} +func (o *H264_Type) GetDEBUG_INFO2_I_GET_ORI_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x4000) >> 14 +} +func (o *H264_Type) SetDEBUG_INFO2_I_EC_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x8000)|value<<15) +} +func (o *H264_Type) GetDEBUG_INFO2_I_EC_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x8000) >> 15 +} +func (o *H264_Type) SetDEBUG_INFO2_I_DB_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x10000)|value<<16) +} +func (o *H264_Type) GetDEBUG_INFO2_I_DB_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x10000) >> 16 +} +func (o *H264_Type) SetDEBUG_INFO2_I_BS_BUF_DONE_DEBUG_FLAG(value uint32) { + volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x20000)|value<<17) +} +func (o *H264_Type) GetDEBUG_INFO2_I_BS_BUF_DONE_DEBUG_FLAG() uint32 { + return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x20000) >> 17 +} + +// H264.DATE: Version control register +func (o *H264_Type) SetDATE_LEDC_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *H264_Type) GetDATE_LEDC_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// H264 Encoder (DMA) +type H264_DMA_Type struct { + OUT_CONF0_CH0 volatile.Register32 // 0x0 + OUT_INT_RAW_CH0 volatile.Register32 // 0x4 + OUT_INT_ENA_CH0 volatile.Register32 // 0x8 + OUT_INT_ST_CH0 volatile.Register32 // 0xC + OUT_INT_CLR_CH0 volatile.Register32 // 0x10 + OUTFIFO_STATUS_CH0 volatile.Register32 // 0x14 + OUT_PUSH_CH0 volatile.Register32 // 0x18 + OUT_LINK_CONF_CH0 volatile.Register32 // 0x1C + OUT_LINK_ADDR_CH0 volatile.Register32 // 0x20 + OUT_STATE_CH0 volatile.Register32 // 0x24 + OUT_EOF_DES_ADDR_CH0 volatile.Register32 // 0x28 + OUT_DSCR_CH0 volatile.Register32 // 0x2C + OUT_DSCR_BF0_CH0 volatile.Register32 // 0x30 + OUT_DSCR_BF1_CH0 volatile.Register32 // 0x34 + _ [4]byte + OUT_ARB_CH0 volatile.Register32 // 0x3C + OUT_RO_STATUS_CH0 volatile.Register32 // 0x40 + OUT_RO_PD_CONF_CH0 volatile.Register32 // 0x44 + _ [8]byte + OUT_MODE_ENABLE_CH0 volatile.Register32 // 0x50 + OUT_MODE_YUV_CH0 volatile.Register32 // 0x54 + _ [16]byte + OUT_ETM_CONF_CH0 volatile.Register32 // 0x68 + _ [4]byte + OUT_BUF_LEN_CH0 volatile.Register32 // 0x70 + OUT_FIFO_BCNT_CH0 volatile.Register32 // 0x74 + OUT_PUSH_BYTECNT_CH0 volatile.Register32 // 0x78 + OUT_XADDR_CH0 volatile.Register32 // 0x7C + _ [128]byte + OUT_CONF0_CH1 volatile.Register32 // 0x100 + OUT_INT_RAW_CH1 volatile.Register32 // 0x104 + OUT_INT_ENA_CH1 volatile.Register32 // 0x108 + OUT_INT_ST_CH1 volatile.Register32 // 0x10C + OUT_INT_CLR_CH1 volatile.Register32 // 0x110 + OUTFIFO_STATUS_CH1 volatile.Register32 // 0x114 + OUT_PUSH_CH1 volatile.Register32 // 0x118 + OUT_LINK_CONF_CH1 volatile.Register32 // 0x11C + OUT_LINK_ADDR_CH1 volatile.Register32 // 0x120 + OUT_STATE_CH1 volatile.Register32 // 0x124 + OUT_EOF_DES_ADDR_CH1 volatile.Register32 // 0x128 + OUT_DSCR_CH1 volatile.Register32 // 0x12C + OUT_DSCR_BF0_CH1 volatile.Register32 // 0x130 + OUT_DSCR_BF1_CH1 volatile.Register32 // 0x134 + _ [4]byte + OUT_ARB_CH1 volatile.Register32 // 0x13C + _ [40]byte + OUT_ETM_CONF_CH1 volatile.Register32 // 0x168 + _ [4]byte + OUT_BUF_LEN_CH1 volatile.Register32 // 0x170 + OUT_FIFO_BCNT_CH1 volatile.Register32 // 0x174 + OUT_PUSH_BYTECNT_CH1 volatile.Register32 // 0x178 + OUT_XADDR_CH1 volatile.Register32 // 0x17C + _ [128]byte + OUT_CONF0_CH2 volatile.Register32 // 0x200 + OUT_INT_RAW_CH2 volatile.Register32 // 0x204 + OUT_INT_ENA_CH2 volatile.Register32 // 0x208 + OUT_INT_ST_CH2 volatile.Register32 // 0x20C + OUT_INT_CLR_CH2 volatile.Register32 // 0x210 + OUTFIFO_STATUS_CH2 volatile.Register32 // 0x214 + OUT_PUSH_CH2 volatile.Register32 // 0x218 + OUT_LINK_CONF_CH2 volatile.Register32 // 0x21C + OUT_LINK_ADDR_CH2 volatile.Register32 // 0x220 + OUT_STATE_CH2 volatile.Register32 // 0x224 + OUT_EOF_DES_ADDR_CH2 volatile.Register32 // 0x228 + OUT_DSCR_CH2 volatile.Register32 // 0x22C + OUT_DSCR_BF0_CH2 volatile.Register32 // 0x230 + OUT_DSCR_BF1_CH2 volatile.Register32 // 0x234 + _ [4]byte + OUT_ARB_CH2 volatile.Register32 // 0x23C + _ [40]byte + OUT_ETM_CONF_CH2 volatile.Register32 // 0x268 + _ [4]byte + OUT_BUF_LEN_CH2 volatile.Register32 // 0x270 + OUT_FIFO_BCNT_CH2 volatile.Register32 // 0x274 + OUT_PUSH_BYTECNT_CH2 volatile.Register32 // 0x278 + OUT_XADDR_CH2 volatile.Register32 // 0x27C + _ [128]byte + OUT_CONF0_CH3 volatile.Register32 // 0x300 + OUT_INT_RAW_CH3 volatile.Register32 // 0x304 + OUT_INT_ENA_CH3 volatile.Register32 // 0x308 + OUT_INT_ST_CH3 volatile.Register32 // 0x30C + OUT_INT_CLR_CH3 volatile.Register32 // 0x310 + OUTFIFO_STATUS_CH3 volatile.Register32 // 0x314 + OUT_PUSH_CH3 volatile.Register32 // 0x318 + OUT_LINK_CONF_CH3 volatile.Register32 // 0x31C + OUT_LINK_ADDR_CH3 volatile.Register32 // 0x320 + OUT_STATE_CH3 volatile.Register32 // 0x324 + OUT_EOF_DES_ADDR_CH3 volatile.Register32 // 0x328 + OUT_DSCR_CH3 volatile.Register32 // 0x32C + OUT_DSCR_BF0_CH3 volatile.Register32 // 0x330 + OUT_DSCR_BF1_CH3 volatile.Register32 // 0x334 + _ [4]byte + OUT_ARB_CH3 volatile.Register32 // 0x33C + _ [40]byte + OUT_ETM_CONF_CH3 volatile.Register32 // 0x368 + _ [4]byte + OUT_BUF_LEN_CH3 volatile.Register32 // 0x370 + OUT_FIFO_BCNT_CH3 volatile.Register32 // 0x374 + OUT_PUSH_BYTECNT_CH3 volatile.Register32 // 0x378 + OUT_XADDR_CH3 volatile.Register32 // 0x37C + OUT_BLOCK_BUF_LEN_CH3 volatile.Register32 // 0x380 + _ [124]byte + OUT_CONF0_CH4 volatile.Register32 // 0x400 + OUT_INT_RAW_CH4 volatile.Register32 // 0x404 + OUT_INT_ENA_CH4 volatile.Register32 // 0x408 + OUT_INT_ST_CH4 volatile.Register32 // 0x40C + OUT_INT_CLR_CH4 volatile.Register32 // 0x410 + OUTFIFO_STATUS_CH4 volatile.Register32 // 0x414 + OUT_PUSH_CH4 volatile.Register32 // 0x418 + OUT_LINK_CONF_CH4 volatile.Register32 // 0x41C + OUT_LINK_ADDR_CH4 volatile.Register32 // 0x420 + OUT_STATE_CH4 volatile.Register32 // 0x424 + OUT_EOF_DES_ADDR_CH4 volatile.Register32 // 0x428 + OUT_DSCR_CH4 volatile.Register32 // 0x42C + OUT_DSCR_BF0_CH4 volatile.Register32 // 0x430 + OUT_DSCR_BF1_CH4 volatile.Register32 // 0x434 + _ [4]byte + OUT_ARB_CH4 volatile.Register32 // 0x43C + _ [40]byte + OUT_ETM_CONF_CH4 volatile.Register32 // 0x468 + _ [4]byte + OUT_BUF_LEN_CH4 volatile.Register32 // 0x470 + OUT_FIFO_BCNT_CH4 volatile.Register32 // 0x474 + OUT_PUSH_BYTECNT_CH4 volatile.Register32 // 0x478 + OUT_XADDR_CH4 volatile.Register32 // 0x47C + OUT_BLOCK_BUF_LEN_CH4 volatile.Register32 // 0x480 + _ [124]byte + IN_CONF0_CH0 volatile.Register32 // 0x500 + IN_INT_RAW_CH0 volatile.Register32 // 0x504 + IN_INT_ENA_CH0 volatile.Register32 // 0x508 + IN_INT_ST_CH0 volatile.Register32 // 0x50C + IN_INT_CLR_CH0 volatile.Register32 // 0x510 + INFIFO_STATUS_CH0 volatile.Register32 // 0x514 + IN_POP_CH0 volatile.Register32 // 0x518 + IN_LINK_CONF_CH0 volatile.Register32 // 0x51C + IN_LINK_ADDR_CH0 volatile.Register32 // 0x520 + IN_STATE_CH0 volatile.Register32 // 0x524 + IN_SUC_EOF_DES_ADDR_CH0 volatile.Register32 // 0x528 + IN_ERR_EOF_DES_ADDR_CH0 volatile.Register32 // 0x52C + IN_DSCR_CH0 volatile.Register32 // 0x530 + IN_DSCR_BF0_CH0 volatile.Register32 // 0x534 + IN_DSCR_BF1_CH0 volatile.Register32 // 0x538 + _ [4]byte + IN_ARB_CH0 volatile.Register32 // 0x540 + _ [4]byte + IN_RO_PD_CONF_CH0 volatile.Register32 // 0x548 + _ [32]byte + IN_ETM_CONF_CH0 volatile.Register32 // 0x56C + _ [16]byte + IN_FIFO_CNT_CH0 volatile.Register32 // 0x580 + IN_POP_DATA_CNT_CH0 volatile.Register32 // 0x584 + IN_XADDR_CH0 volatile.Register32 // 0x588 + IN_BUF_HB_RCV_CH0 volatile.Register32 // 0x58C + _ [112]byte + IN_CONF0_CH1 volatile.Register32 // 0x600 + IN_INT_RAW_CH1 volatile.Register32 // 0x604 + IN_INT_ENA_CH1 volatile.Register32 // 0x608 + IN_INT_ST_CH1 volatile.Register32 // 0x60C + IN_INT_CLR_CH1 volatile.Register32 // 0x610 + INFIFO_STATUS_CH1 volatile.Register32 // 0x614 + IN_POP_CH1 volatile.Register32 // 0x618 + IN_LINK_CONF_CH1 volatile.Register32 // 0x61C + IN_LINK_ADDR_CH1 volatile.Register32 // 0x620 + IN_STATE_CH1 volatile.Register32 // 0x624 + IN_SUC_EOF_DES_ADDR_CH1 volatile.Register32 // 0x628 + IN_ERR_EOF_DES_ADDR_CH1 volatile.Register32 // 0x62C + IN_DSCR_CH1 volatile.Register32 // 0x630 + IN_DSCR_BF0_CH1 volatile.Register32 // 0x634 + IN_DSCR_BF1_CH1 volatile.Register32 // 0x638 + _ [4]byte + IN_ARB_CH1 volatile.Register32 // 0x640 + _ [4]byte + IN_ETM_CONF_CH1 volatile.Register32 // 0x648 + _ [52]byte + IN_FIFO_CNT_CH1 volatile.Register32 // 0x680 + IN_POP_DATA_CNT_CH1 volatile.Register32 // 0x684 + IN_XADDR_CH1 volatile.Register32 // 0x688 + IN_BUF_HB_RCV_CH1 volatile.Register32 // 0x68C + _ [112]byte + IN_CONF0_CH2 volatile.Register32 // 0x700 + IN_INT_RAW_CH2 volatile.Register32 // 0x704 + IN_INT_ENA_CH2 volatile.Register32 // 0x708 + IN_INT_ST_CH2 volatile.Register32 // 0x70C + IN_INT_CLR_CH2 volatile.Register32 // 0x710 + INFIFO_STATUS_CH2 volatile.Register32 // 0x714 + IN_POP_CH2 volatile.Register32 // 0x718 + IN_LINK_CONF_CH2 volatile.Register32 // 0x71C + IN_LINK_ADDR_CH2 volatile.Register32 // 0x720 + IN_STATE_CH2 volatile.Register32 // 0x724 + IN_SUC_EOF_DES_ADDR_CH2 volatile.Register32 // 0x728 + IN_ERR_EOF_DES_ADDR_CH2 volatile.Register32 // 0x72C + IN_DSCR_CH2 volatile.Register32 // 0x730 + IN_DSCR_BF0_CH2 volatile.Register32 // 0x734 + IN_DSCR_BF1_CH2 volatile.Register32 // 0x738 + _ [4]byte + IN_ARB_CH2 volatile.Register32 // 0x740 + _ [4]byte + IN_ETM_CONF_CH2 volatile.Register32 // 0x748 + _ [52]byte + IN_FIFO_CNT_CH2 volatile.Register32 // 0x780 + IN_POP_DATA_CNT_CH2 volatile.Register32 // 0x784 + IN_XADDR_CH2 volatile.Register32 // 0x788 + IN_BUF_HB_RCV_CH2 volatile.Register32 // 0x78C + _ [112]byte + IN_CONF0_CH3 volatile.Register32 // 0x800 + IN_INT_RAW_CH3 volatile.Register32 // 0x804 + IN_INT_ENA_CH3 volatile.Register32 // 0x808 + IN_INT_ST_CH3 volatile.Register32 // 0x80C + IN_INT_CLR_CH3 volatile.Register32 // 0x810 + INFIFO_STATUS_CH3 volatile.Register32 // 0x814 + IN_POP_CH3 volatile.Register32 // 0x818 + IN_LINK_CONF_CH3 volatile.Register32 // 0x81C + IN_LINK_ADDR_CH3 volatile.Register32 // 0x820 + IN_STATE_CH3 volatile.Register32 // 0x824 + IN_SUC_EOF_DES_ADDR_CH3 volatile.Register32 // 0x828 + IN_ERR_EOF_DES_ADDR_CH3 volatile.Register32 // 0x82C + IN_DSCR_CH3 volatile.Register32 // 0x830 + IN_DSCR_BF0_CH3 volatile.Register32 // 0x834 + IN_DSCR_BF1_CH3 volatile.Register32 // 0x838 + _ [4]byte + IN_ARB_CH3 volatile.Register32 // 0x840 + _ [4]byte + IN_ETM_CONF_CH3 volatile.Register32 // 0x848 + _ [52]byte + IN_FIFO_CNT_CH3 volatile.Register32 // 0x880 + IN_POP_DATA_CNT_CH3 volatile.Register32 // 0x884 + IN_XADDR_CH3 volatile.Register32 // 0x888 + IN_BUF_HB_RCV_CH3 volatile.Register32 // 0x88C + _ [112]byte + IN_CONF0_CH4 volatile.Register32 // 0x900 + IN_INT_RAW_CH4 volatile.Register32 // 0x904 + IN_INT_ENA_CH4 volatile.Register32 // 0x908 + IN_INT_ST_CH4 volatile.Register32 // 0x90C + IN_INT_CLR_CH4 volatile.Register32 // 0x910 + INFIFO_STATUS_CH4 volatile.Register32 // 0x914 + IN_POP_CH4 volatile.Register32 // 0x918 + IN_LINK_CONF_CH4 volatile.Register32 // 0x91C + IN_LINK_ADDR_CH4 volatile.Register32 // 0x920 + IN_STATE_CH4 volatile.Register32 // 0x924 + IN_SUC_EOF_DES_ADDR_CH4 volatile.Register32 // 0x928 + IN_ERR_EOF_DES_ADDR_CH4 volatile.Register32 // 0x92C + IN_DSCR_CH4 volatile.Register32 // 0x930 + IN_DSCR_BF0_CH4 volatile.Register32 // 0x934 + IN_DSCR_BF1_CH4 volatile.Register32 // 0x938 + _ [4]byte + IN_ARB_CH4 volatile.Register32 // 0x940 + _ [4]byte + IN_ETM_CONF_CH4 volatile.Register32 // 0x948 + _ [52]byte + IN_FIFO_CNT_CH4 volatile.Register32 // 0x980 + IN_POP_DATA_CNT_CH4 volatile.Register32 // 0x984 + IN_XADDR_CH4 volatile.Register32 // 0x988 + IN_BUF_HB_RCV_CH4 volatile.Register32 // 0x98C + _ [112]byte + IN_CONF0_CH5 volatile.Register32 // 0xA00 + IN_CONF1_CH5 volatile.Register32 // 0xA04 + IN_CONF2_CH5 volatile.Register32 // 0xA08 + IN_CONF3_CH5 volatile.Register32 // 0xA0C + IN_INT_RAW_CH5 volatile.Register32 // 0xA10 + IN_INT_ENA_CH5 volatile.Register32 // 0xA14 + IN_INT_ST_CH5 volatile.Register32 // 0xA18 + IN_INT_CLR_CH5 volatile.Register32 // 0xA1C + INFIFO_STATUS_CH5 volatile.Register32 // 0xA20 + IN_POP_CH5 volatile.Register32 // 0xA24 + IN_STATE_CH5 volatile.Register32 // 0xA28 + _ [20]byte + IN_ARB_CH5 volatile.Register32 // 0xA40 + _ [60]byte + IN_FIFO_CNT_CH5 volatile.Register32 // 0xA80 + IN_POP_DATA_CNT_CH5 volatile.Register32 // 0xA84 + IN_XADDR_CH5 volatile.Register32 // 0xA88 + IN_BUF_HB_RCV_CH5 volatile.Register32 // 0xA8C + _ [112]byte + INTER_AXI_ERR volatile.Register32 // 0xB00 + EXTER_AXI_ERR volatile.Register32 // 0xB04 + RST_CONF volatile.Register32 // 0xB08 + INTER_MEM_START_ADDR0 volatile.Register32 // 0xB0C + INTER_MEM_END_ADDR0 volatile.Register32 // 0xB10 + INTER_MEM_START_ADDR1 volatile.Register32 // 0xB14 + INTER_MEM_END_ADDR1 volatile.Register32 // 0xB18 + _ [4]byte + EXTER_MEM_START_ADDR0 volatile.Register32 // 0xB20 + EXTER_MEM_END_ADDR0 volatile.Register32 // 0xB24 + EXTER_MEM_START_ADDR1 volatile.Register32 // 0xB28 + EXTER_MEM_END_ADDR1 volatile.Register32 // 0xB2C + OUT_ARB_CONFIG volatile.Register32 // 0xB30 + IN_ARB_CONFIG volatile.Register32 // 0xB34 + _ [4]byte + DATE volatile.Register32 // 0xB3C + _ [16]byte + COUNTER_RST volatile.Register32 // 0xB50 + RX_CH0_COUNTER volatile.Register32 // 0xB54 + RX_CH1_COUNTER volatile.Register32 // 0xB58 + RX_CH2_COUNTER volatile.Register32 // 0xB5C + RX_CH5_COUNTER volatile.Register32 // 0xB60 +} + +// H264_DMA.OUT_CONF0_CH0: TX CH0 config0 register +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_ECC_AES_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_ECC_AES_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_CHECK_OWNER_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_CHECK_OWNER_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_MEM_BURST_LENGTH_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_MEM_BURST_LENGTH_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_PAGE_BOUND_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_PAGE_BOUND_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_REORDER_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_REORDER_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_RST_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1000000) >> 24 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_CMD_DISABLE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_CMD_DISABLE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2000000) >> 25 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_ARB_WEIGHT_OPT_DIS_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_ARB_WEIGHT_OPT_DIS_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.OUT_INT_RAW_CH0: TX CH0 interrupt raw register +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DONE_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DONE_CH0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_EOF_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_EOF_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF_L1_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF_L1_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF_L1_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF_L1_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF_L2_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF_L2_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF_L2_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF_L2_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_TASK_OVF_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_TASK_OVF_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ENA_CH0: TX CH0 interrupt ena register +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DONE_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DONE_CH0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_EOF_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_EOF_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF_L1_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF_L1_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF_L1_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF_L1_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF_L2_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF_L2_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF_L2_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF_L2_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ST_CH0: TX CH0 interrupt st register +func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_DONE_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_DONE_CH0_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_EOF_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_EOF_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_L1_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_L1_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_L1_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_L1_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_L2_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_L2_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_L2_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_L2_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_CLR_CH0: TX CH0 interrupt clr register +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DONE_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DONE_CH0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_EOF_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_EOF_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF_L1_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF_L1_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF_L1_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF_L1_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF_L2_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF_L2_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF_L2_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF_L2_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_TASK_OVF_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_TASK_OVF_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUTFIFO_STATUS_CH0: TX CH0 outfifo status register +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L2_CH0(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L2_CH0() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L2_CH0(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L2_CH0() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L2_CH0(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L2_CH0() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L1_CH0(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L1_CH0() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L1_CH0(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L1_CH0() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L1_CH0(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L1_CH0() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L3_CH0(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L3_CH0() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L3_CH0(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L3_CH0() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L3_CH0(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L3_CH0() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.OUT_PUSH_CH0: TX CH0 outfifo push register +func (o *H264_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x3ff +} +func (o *H264_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x400)|value<<10) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x400) >> 10 +} + +// H264_DMA.OUT_LINK_CONF_CH0: TX CH0 out_link dscr ctrl register +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH0_OUTLINK_STOP_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH0_OUTLINK_STOP_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH0_OUTLINK_START_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH0_OUTLINK_START_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH0_OUTLINK_RESTART_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH0_OUTLINK_RESTART_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH0_OUTLINK_PARK_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH0_OUTLINK_PARK_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg) & 0x800000) >> 23 +} + +// H264_DMA.OUT_LINK_ADDR_CH0: TX CH0 out_link dscr addr register +func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_ADDR_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH0.Reg) +} + +// H264_DMA.OUT_STATE_CH0: TX CH0 state register +func (o *H264_DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetOUT_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xf00000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xf00000) >> 20 +} +func (o *H264_DMA_Type) SetOUT_STATE_CH0_OUT_RESET_AVAIL_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH0_OUT_RESET_AVAIL_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x1000000) >> 24 +} + +// H264_DMA.OUT_EOF_DES_ADDR_CH0: TX CH0 eof des addr register +func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg) +} + +// H264_DMA.OUT_DSCR_CH0: TX CH0 next dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg) +} + +// H264_DMA.OUT_DSCR_BF0_CH0: TX CH0 last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg) +} + +// H264_DMA.OUT_DSCR_BF1_CH0: TX CH0 second-to-last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg) +} + +// H264_DMA.OUT_ARB_CH0: TX CH0 arb register +func (o *H264_DMA_Type) SetOUT_ARB_CH0_OUT_ARB_TOKEN_NUM_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH0.Reg, volatile.LoadUint32(&o.OUT_ARB_CH0.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH0_OUT_ARB_TOKEN_NUM_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_ARB_CH0.Reg) & 0xf +} +func (o *H264_DMA_Type) SetOUT_ARB_CH0_EXTER_OUT_ARB_PRIORITY_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH0.Reg, volatile.LoadUint32(&o.OUT_ARB_CH0.Reg)&^(0x30)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH0_EXTER_OUT_ARB_PRIORITY_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_ARB_CH0.Reg) & 0x30) >> 4 +} + +// H264_DMA.OUT_RO_STATUS_CH0: TX CH0 reorder status register +func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUTFIFO_RO_CNT_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0x3)|value) +} +func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUTFIFO_RO_CNT_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0x3 +} +func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUT_RO_WR_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0xc0)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUT_RO_WR_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0xc0) >> 6 +} +func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUT_RO_RD_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0x300)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUT_RO_RD_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0x300) >> 8 +} +func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUT_PIXEL_BYTE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0x3c00)|value<<10) +} +func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUT_PIXEL_BYTE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0x3c00) >> 10 +} +func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUT_BURST_BLOCK_NUM_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0x3c000)|value<<14) +} +func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUT_BURST_BLOCK_NUM_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0x3c000) >> 14 +} + +// H264_DMA.OUT_RO_PD_CONF_CH0: TX CH0 reorder power config register +func (o *H264_DMA_Type) SetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PD_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_RO_PD_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PD_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PU_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_RO_PD_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PU_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_CLK_FO_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_RO_PD_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_CLK_FO_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg) & 0x40) >> 6 +} + +// H264_DMA.OUT_MODE_ENABLE_CH0: tx CH0 mode enable register +func (o *H264_DMA_Type) SetOUT_MODE_ENABLE_CH0_OUT_TEST_MODE_ENABLE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_MODE_ENABLE_CH0.Reg, volatile.LoadUint32(&o.OUT_MODE_ENABLE_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_MODE_ENABLE_CH0_OUT_TEST_MODE_ENABLE_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_MODE_ENABLE_CH0.Reg) & 0x1 +} + +// H264_DMA.OUT_MODE_YUV_CH0: tx CH0 test mode yuv value register +func (o *H264_DMA_Type) SetOUT_MODE_YUV_CH0_OUT_TEST_Y_VALUE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_MODE_YUV_CH0.Reg, volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetOUT_MODE_YUV_CH0_OUT_TEST_Y_VALUE_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg) & 0xff +} +func (o *H264_DMA_Type) SetOUT_MODE_YUV_CH0_OUT_TEST_U_VALUE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_MODE_YUV_CH0.Reg, volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg)&^(0xff00)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_MODE_YUV_CH0_OUT_TEST_U_VALUE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg) & 0xff00) >> 8 +} +func (o *H264_DMA_Type) SetOUT_MODE_YUV_CH0_OUT_TEST_V_VALUE_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_MODE_YUV_CH0.Reg, volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg)&^(0xff0000)|value<<16) +} +func (o *H264_DMA_Type) GetOUT_MODE_YUV_CH0_OUT_TEST_V_VALUE_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg) & 0xff0000) >> 16 +} + +// H264_DMA.OUT_ETM_CONF_CH0: TX CH0 ETM config register +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH0_OUT_ETM_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH0_OUT_ETM_EN_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH0_OUT_ETM_LOOP_EN_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH0_OUT_ETM_LOOP_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH0_OUT_DSCR_TASK_MAK_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH0_OUT_DSCR_TASK_MAK_CH0() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg) & 0xc) >> 2 +} + +// H264_DMA.OUT_BUF_LEN_CH0: tx CH0 buf len register +func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH0_OUT_CMDFIFO_BUF_LEN_HB_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_BUF_LEN_CH0.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH0.Reg)&^(0x1fff)|value) +} +func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH0_OUT_CMDFIFO_BUF_LEN_HB_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_BUF_LEN_CH0.Reg) & 0x1fff +} + +// H264_DMA.OUT_FIFO_BCNT_CH0: tx CH0 fifo byte cnt register +func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH0_OUT_CMDFIFO_OUTFIFO_BCNT_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH0.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH0.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH0_OUT_CMDFIFO_OUTFIFO_BCNT_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH0.Reg) & 0x3ff +} + +// H264_DMA.OUT_PUSH_BYTECNT_CH0: tx CH0 push byte cnt register +func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH0_OUT_CMDFIFO_PUSH_BYTECNT_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH0.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH0_OUT_CMDFIFO_PUSH_BYTECNT_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH0.Reg) & 0xff +} + +// H264_DMA.OUT_XADDR_CH0: tx CH0 xaddr register +func (o *H264_DMA_Type) SetOUT_XADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_XADDR_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_XADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_XADDR_CH0.Reg) +} + +// H264_DMA.OUT_CONF0_CH1: TX CH1 config0 register +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_ECC_AES_EN_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_ECC_AES_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_CHECK_OWNER_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_CHECK_OWNER_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_MEM_BURST_LENGTH_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_MEM_BURST_LENGTH_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_PAGE_BOUND_EN_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_PAGE_BOUND_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_RST_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_RST_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1000000) >> 24 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_CMD_DISABLE_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_CMD_DISABLE_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2000000) >> 25 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_ARB_WEIGHT_OPT_DIS_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_ARB_WEIGHT_OPT_DIS_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.OUT_INT_RAW_CH1: TX CH1 interrupt raw register +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DONE_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DONE_CH1_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_EOF_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_EOF_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF_L1_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF_L1_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF_L1_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF_L1_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF_L2_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF_L2_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF_L2_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF_L2_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_TASK_OVF_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_TASK_OVF_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ENA_CH1: TX CH1 interrupt ena register +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DONE_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DONE_CH1_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_EOF_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_EOF_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF_L1_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF_L1_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF_L1_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF_L1_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF_L2_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF_L2_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF_L2_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF_L2_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ST_CH1: TX CH1 interrupt st register +func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_DONE_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_DONE_CH1_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_EOF_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_EOF_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_L1_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_L1_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_L1_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_L1_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_L2_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_L2_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_L2_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_L2_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_CLR_CH1: TX CH1 interrupt clr register +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DONE_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DONE_CH1_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_EOF_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_EOF_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF_L1_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF_L1_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF_L1_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF_L1_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF_L2_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF_L2_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF_L2_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF_L2_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_TASK_OVF_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_TASK_OVF_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUTFIFO_STATUS_CH1: TX CH1 outfifo status register +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L2_CH1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L2_CH1() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L2_CH1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L2_CH1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L2_CH1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L2_CH1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L1_CH1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L1_CH1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L1_CH1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L1_CH1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L1_CH1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L1_CH1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L3_CH1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L3_CH1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L3_CH1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L3_CH1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L3_CH1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L3_CH1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.OUT_PUSH_CH1: TX CH1 outfifo push register +func (o *H264_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x3ff +} +func (o *H264_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x400)|value<<10) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x400) >> 10 +} + +// H264_DMA.OUT_LINK_CONF_CH1: TX CH1 out_link dscr ctrl register +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH1_OUTLINK_STOP_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH1_OUTLINK_STOP_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH1_OUTLINK_START_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH1_OUTLINK_START_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH1_OUTLINK_RESTART_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH1_OUTLINK_RESTART_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH1_OUTLINK_PARK_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH1_OUTLINK_PARK_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg) & 0x800000) >> 23 +} + +// H264_DMA.OUT_LINK_ADDR_CH1: TX CH1 out_link dscr addr register +func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_ADDR_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH1.Reg) +} + +// H264_DMA.OUT_STATE_CH1: TX CH1 state register +func (o *H264_DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetOUT_STATE_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xf00000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xf00000) >> 20 +} +func (o *H264_DMA_Type) SetOUT_STATE_CH1_OUT_RESET_AVAIL_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH1_OUT_RESET_AVAIL_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x1000000) >> 24 +} + +// H264_DMA.OUT_EOF_DES_ADDR_CH1: TX CH1 eof des addr register +func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg) +} + +// H264_DMA.OUT_DSCR_CH1: TX CH1 next dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg) +} + +// H264_DMA.OUT_DSCR_BF0_CH1: TX CH1 last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg) +} + +// H264_DMA.OUT_DSCR_BF1_CH1: TX CH1 second-to-last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg) +} + +// H264_DMA.OUT_ARB_CH1: TX CH1 arb register +func (o *H264_DMA_Type) SetOUT_ARB_CH1_OUT_ARB_TOKEN_NUM_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH1.Reg, volatile.LoadUint32(&o.OUT_ARB_CH1.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH1_OUT_ARB_TOKEN_NUM_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_ARB_CH1.Reg) & 0xf +} +func (o *H264_DMA_Type) SetOUT_ARB_CH1_INTER_OUT_ARB_PRIORITY_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH1.Reg, volatile.LoadUint32(&o.OUT_ARB_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH1_INTER_OUT_ARB_PRIORITY_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_ARB_CH1.Reg) & 0x40) >> 6 +} + +// H264_DMA.OUT_ETM_CONF_CH1: TX CH1 ETM config register +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH1_OUT_ETM_EN_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH1_OUT_ETM_EN_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH1_OUT_ETM_LOOP_EN_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH1_OUT_ETM_LOOP_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH1_OUT_DSCR_TASK_MAK_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH1_OUT_DSCR_TASK_MAK_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg) & 0xc) >> 2 +} + +// H264_DMA.OUT_BUF_LEN_CH1: tx CH1 buf len register +func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH1_OUT_CMDFIFO_BUF_LEN_HB_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_BUF_LEN_CH1.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH1.Reg)&^(0x1fff)|value) +} +func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH1_OUT_CMDFIFO_BUF_LEN_HB_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_BUF_LEN_CH1.Reg) & 0x1fff +} + +// H264_DMA.OUT_FIFO_BCNT_CH1: tx CH1 fifo byte cnt register +func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH1_OUT_CMDFIFO_OUTFIFO_BCNT_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH1.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH1.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH1_OUT_CMDFIFO_OUTFIFO_BCNT_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH1.Reg) & 0x3ff +} + +// H264_DMA.OUT_PUSH_BYTECNT_CH1: tx CH1 push byte cnt register +func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH1_OUT_CMDFIFO_PUSH_BYTECNT_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH1.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH1_OUT_CMDFIFO_PUSH_BYTECNT_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH1.Reg) & 0xff +} + +// H264_DMA.OUT_XADDR_CH1: tx CH1 xaddr register +func (o *H264_DMA_Type) SetOUT_XADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_XADDR_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_XADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_XADDR_CH1.Reg) +} + +// H264_DMA.OUT_CONF0_CH2: TX CH2 config0 register +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_EOF_MODE_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_EOF_MODE_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_ECC_AES_EN_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_ECC_AES_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_CHECK_OWNER_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_CHECK_OWNER_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_MEM_BURST_LENGTH_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_MEM_BURST_LENGTH_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_PAGE_BOUND_EN_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_PAGE_BOUND_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_RST_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_RST_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1000000) >> 24 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_CMD_DISABLE_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_CMD_DISABLE_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2000000) >> 25 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_ARB_WEIGHT_OPT_DIS_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_ARB_WEIGHT_OPT_DIS_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.OUT_INT_RAW_CH2: TX CH2 interrupt raw register +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DONE_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DONE_CH2_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_EOF_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_EOF_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF_L1_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF_L1_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF_L1_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF_L1_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF_L2_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF_L2_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF_L2_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF_L2_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_TASK_OVF_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_TASK_OVF_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ENA_CH2: TX CH2 interrupt ena register +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DONE_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DONE_CH2_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_EOF_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_EOF_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF_L1_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF_L1_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF_L1_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF_L1_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF_L2_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF_L2_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF_L2_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF_L2_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ST_CH2: TX CH2 interrupt st register +func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_DONE_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_DONE_CH2_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_EOF_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_EOF_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_L1_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_L1_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_L1_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_L1_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_L2_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_L2_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_L2_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_L2_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_CLR_CH2: TX CH2 interrupt clr register +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DONE_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DONE_CH2_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_EOF_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_EOF_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF_L1_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF_L1_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF_L1_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF_L1_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF_L2_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF_L2_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF_L2_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF_L2_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_TASK_OVF_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_TASK_OVF_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUTFIFO_STATUS_CH2: TX CH2 outfifo status register +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L2_CH2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L2_CH2() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L2_CH2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L2_CH2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L2_CH2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L2_CH2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L1_CH2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L1_CH2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L1_CH2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L1_CH2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L1_CH2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L1_CH2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L3_CH2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L3_CH2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L3_CH2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L3_CH2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L3_CH2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L3_CH2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.OUT_PUSH_CH2: TX CH2 outfifo push register +func (o *H264_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x3ff +} +func (o *H264_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x400)|value<<10) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x400) >> 10 +} + +// H264_DMA.OUT_LINK_CONF_CH2: TX CH2 out_link dscr ctrl register +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH2_OUTLINK_STOP_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH2_OUTLINK_STOP_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH2_OUTLINK_START_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH2_OUTLINK_START_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH2_OUTLINK_RESTART_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH2_OUTLINK_RESTART_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH2_OUTLINK_PARK_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH2_OUTLINK_PARK_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg) & 0x800000) >> 23 +} + +// H264_DMA.OUT_LINK_ADDR_CH2: TX CH2 out_link dscr addr register +func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_ADDR_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH2.Reg) +} + +// H264_DMA.OUT_STATE_CH2: TX CH2 state register +func (o *H264_DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetOUT_STATE_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xf00000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xf00000) >> 20 +} +func (o *H264_DMA_Type) SetOUT_STATE_CH2_OUT_RESET_AVAIL_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH2_OUT_RESET_AVAIL_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x1000000) >> 24 +} + +// H264_DMA.OUT_EOF_DES_ADDR_CH2: TX CH2 eof des addr register +func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg) +} + +// H264_DMA.OUT_DSCR_CH2: TX CH2 next dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg) +} + +// H264_DMA.OUT_DSCR_BF0_CH2: TX CH2 last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg) +} + +// H264_DMA.OUT_DSCR_BF1_CH2: TX CH2 second-to-last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg) +} + +// H264_DMA.OUT_ARB_CH2: TX CH2 arb register +func (o *H264_DMA_Type) SetOUT_ARB_CH2_OUT_ARB_TOKEN_NUM_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH2.Reg, volatile.LoadUint32(&o.OUT_ARB_CH2.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH2_OUT_ARB_TOKEN_NUM_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_ARB_CH2.Reg) & 0xf +} +func (o *H264_DMA_Type) SetOUT_ARB_CH2_INTER_OUT_ARB_PRIORITY_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH2.Reg, volatile.LoadUint32(&o.OUT_ARB_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH2_INTER_OUT_ARB_PRIORITY_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_ARB_CH2.Reg) & 0x40) >> 6 +} + +// H264_DMA.OUT_ETM_CONF_CH2: TX CH2 ETM config register +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH2_OUT_ETM_EN_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH2_OUT_ETM_EN_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH2_OUT_ETM_LOOP_EN_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH2_OUT_ETM_LOOP_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH2_OUT_DSCR_TASK_MAK_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH2_OUT_DSCR_TASK_MAK_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg) & 0xc) >> 2 +} + +// H264_DMA.OUT_BUF_LEN_CH2: tx CH2 buf len register +func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH2_OUT_CMDFIFO_BUF_LEN_HB_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_BUF_LEN_CH2.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH2.Reg)&^(0x1fff)|value) +} +func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH2_OUT_CMDFIFO_BUF_LEN_HB_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_BUF_LEN_CH2.Reg) & 0x1fff +} + +// H264_DMA.OUT_FIFO_BCNT_CH2: tx CH2 fifo byte cnt register +func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH2_OUT_CMDFIFO_OUTFIFO_BCNT_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH2.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH2.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH2_OUT_CMDFIFO_OUTFIFO_BCNT_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH2.Reg) & 0x3ff +} + +// H264_DMA.OUT_PUSH_BYTECNT_CH2: tx CH2 push byte cnt register +func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH2_OUT_CMDFIFO_PUSH_BYTECNT_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH2.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH2_OUT_CMDFIFO_PUSH_BYTECNT_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH2.Reg) & 0xff +} + +// H264_DMA.OUT_XADDR_CH2: tx CH2 xaddr register +func (o *H264_DMA_Type) SetOUT_XADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_XADDR_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_XADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_XADDR_CH2.Reg) +} + +// H264_DMA.OUT_CONF0_CH3: TX CH3 config0 register +func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_AUTO_WRBACK_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_AUTO_WRBACK_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_EOF_MODE_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_EOF_MODE_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUTDSCR_BURST_EN_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUTDSCR_BURST_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_ECC_AES_EN_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_ECC_AES_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_CHECK_OWNER_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_CHECK_OWNER_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_MEM_BURST_LENGTH_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_MEM_BURST_LENGTH_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_PAGE_BOUND_EN_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_PAGE_BOUND_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_ARB_WEIGHT_OPT_DIS_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_ARB_WEIGHT_OPT_DIS_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.OUT_INT_RAW_CH3: TX CH3 interrupt raw register +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_DONE_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_DONE_CH3_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_EOF_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_EOF_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_DSCR_ERR_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_DSCR_ERR_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_TOTAL_EOF_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_TOTAL_EOF_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_OVF_L1_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_OVF_L1_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_UDF_L1_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_UDF_L1_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_OVF_L2_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_OVF_L2_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_UDF_L2_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_UDF_L2_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_DSCR_TASK_OVF_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_DSCR_TASK_OVF_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ENA_CH3: TX CH3 interrupt ena register +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_DONE_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_DONE_CH3_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_EOF_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_EOF_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_DSCR_ERR_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_DSCR_ERR_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_TOTAL_EOF_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_TOTAL_EOF_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_OVF_L1_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_OVF_L1_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_UDF_L1_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_UDF_L1_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_OVF_L2_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_OVF_L2_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_UDF_L2_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_UDF_L2_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ST_CH3: TX CH3 interrupt st register +func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_DONE_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_DONE_CH3_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_EOF_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_EOF_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_DSCR_ERR_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_DSCR_ERR_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_TOTAL_EOF_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_TOTAL_EOF_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_OVF_L1_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_OVF_L1_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_UDF_L1_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_UDF_L1_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_OVF_L2_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_OVF_L2_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_UDF_L2_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_UDF_L2_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_CLR_CH3: TX CH3 interrupt clr register +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_DONE_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_DONE_CH3_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_EOF_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_EOF_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_DSCR_ERR_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_DSCR_ERR_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_TOTAL_EOF_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_TOTAL_EOF_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_OVF_L1_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_OVF_L1_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_UDF_L1_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_UDF_L1_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_OVF_L2_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_OVF_L2_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_UDF_L2_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_UDF_L2_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_DSCR_TASK_OVF_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_DSCR_TASK_OVF_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUTFIFO_STATUS_CH3: TX CH3 outfifo status register +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L2_CH3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L2_CH3() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L2_CH3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L2_CH3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L2_CH3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L2_CH3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L1_CH3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L1_CH3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L1_CH3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L1_CH3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L1_CH3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L1_CH3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L3_CH3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L3_CH3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L3_CH3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L3_CH3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L3_CH3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L3_CH3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.OUT_PUSH_CH3: TX CH3 outfifo push register +func (o *H264_DMA_Type) SetOUT_PUSH_CH3_OUTFIFO_WDATA_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH3.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH3_OUTFIFO_WDATA_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg) & 0x3ff +} +func (o *H264_DMA_Type) SetOUT_PUSH_CH3_OUTFIFO_PUSH_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH3.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg)&^(0x400)|value<<10) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH3_OUTFIFO_PUSH_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg) & 0x400) >> 10 +} + +// H264_DMA.OUT_LINK_CONF_CH3: TX CH3 out_link dscr ctrl register +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH3_OUTLINK_STOP_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH3_OUTLINK_STOP_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH3_OUTLINK_START_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH3_OUTLINK_START_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH3_OUTLINK_RESTART_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH3_OUTLINK_RESTART_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH3_OUTLINK_PARK_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH3_OUTLINK_PARK_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg) & 0x800000) >> 23 +} + +// H264_DMA.OUT_LINK_ADDR_CH3: TX CH3 out_link dscr addr register +func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_ADDR_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH3.Reg) +} + +// H264_DMA.OUT_STATE_CH3: TX CH3 state register +func (o *H264_DMA_Type) SetOUT_STATE_CH3_OUTLINK_DSCR_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH3.Reg, volatile.LoadUint32(&o.OUT_STATE_CH3.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH3_OUTLINK_DSCR_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH3.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetOUT_STATE_CH3_OUT_DSCR_STATE_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH3.Reg, volatile.LoadUint32(&o.OUT_STATE_CH3.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH3_OUT_DSCR_STATE_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH3.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetOUT_STATE_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH3.Reg, volatile.LoadUint32(&o.OUT_STATE_CH3.Reg)&^(0xf00000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH3.Reg) & 0xf00000) >> 20 +} + +// H264_DMA.OUT_EOF_DES_ADDR_CH3: TX CH3 eof des addr register +func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH3.Reg) +} + +// H264_DMA.OUT_DSCR_CH3: TX CH3 next dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH3.Reg) +} + +// H264_DMA.OUT_DSCR_BF0_CH3: TX CH3 last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH3.Reg) +} + +// H264_DMA.OUT_DSCR_BF1_CH3: TX CH3 second-to-last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH3.Reg) +} + +// H264_DMA.OUT_ARB_CH3: TX CH3 arb register +func (o *H264_DMA_Type) SetOUT_ARB_CH3_OUT_ARB_TOKEN_NUM_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH3.Reg, volatile.LoadUint32(&o.OUT_ARB_CH3.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH3_OUT_ARB_TOKEN_NUM_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_ARB_CH3.Reg) & 0xf +} +func (o *H264_DMA_Type) SetOUT_ARB_CH3_EXTER_OUT_ARB_PRIORITY_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH3.Reg, volatile.LoadUint32(&o.OUT_ARB_CH3.Reg)&^(0x30)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH3_EXTER_OUT_ARB_PRIORITY_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_ARB_CH3.Reg) & 0x30) >> 4 +} + +// H264_DMA.OUT_ETM_CONF_CH3: TX CH3 ETM config register +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH3_OUT_ETM_EN_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH3_OUT_ETM_EN_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH3_OUT_ETM_LOOP_EN_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH3_OUT_ETM_LOOP_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH3_OUT_DSCR_TASK_MAK_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH3_OUT_DSCR_TASK_MAK_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg) & 0xc) >> 2 +} + +// H264_DMA.OUT_BUF_LEN_CH3: tx CH3 buf len register +func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH3_OUT_CMDFIFO_BUF_LEN_HB_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_BUF_LEN_CH3.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH3.Reg)&^(0x1fff)|value) +} +func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH3_OUT_CMDFIFO_BUF_LEN_HB_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_BUF_LEN_CH3.Reg) & 0x1fff +} + +// H264_DMA.OUT_FIFO_BCNT_CH3: tx CH3 fifo byte cnt register +func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH3_OUT_CMDFIFO_OUTFIFO_BCNT_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH3.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH3.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH3_OUT_CMDFIFO_OUTFIFO_BCNT_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH3.Reg) & 0x3ff +} + +// H264_DMA.OUT_PUSH_BYTECNT_CH3: tx CH3 push byte cnt register +func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH3_OUT_CMDFIFO_PUSH_BYTECNT_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH3.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH3.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH3_OUT_CMDFIFO_PUSH_BYTECNT_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH3.Reg) & 0xff +} + +// H264_DMA.OUT_XADDR_CH3: tx CH3 xaddr register +func (o *H264_DMA_Type) SetOUT_XADDR_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_XADDR_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_XADDR_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_XADDR_CH3.Reg) +} + +// H264_DMA.OUT_BLOCK_BUF_LEN_CH3: tx CH3 block buf len register +func (o *H264_DMA_Type) SetOUT_BLOCK_BUF_LEN_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_BLOCK_BUF_LEN_CH3.Reg, volatile.LoadUint32(&o.OUT_BLOCK_BUF_LEN_CH3.Reg)&^(0xfffffff)|value) +} +func (o *H264_DMA_Type) GetOUT_BLOCK_BUF_LEN_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_BLOCK_BUF_LEN_CH3.Reg) & 0xfffffff +} + +// H264_DMA.OUT_CONF0_CH4: TX CH4 config0 register +func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_AUTO_WRBACK_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_AUTO_WRBACK_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_EOF_MODE_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_EOF_MODE_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUTDSCR_BURST_EN_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUTDSCR_BURST_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_ECC_AES_EN_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_ECC_AES_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_CHECK_OWNER_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_CHECK_OWNER_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_MEM_BURST_LENGTH_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_MEM_BURST_LENGTH_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_PAGE_BOUND_EN_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_PAGE_BOUND_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_ARB_WEIGHT_OPT_DIS_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_ARB_WEIGHT_OPT_DIS_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.OUT_INT_RAW_CH4: TX CH4 interrupt raw register +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_DONE_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_DONE_CH4_INT_RAW() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_EOF_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_EOF_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_DSCR_ERR_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_DSCR_ERR_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_TOTAL_EOF_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_TOTAL_EOF_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_OVF_L1_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_OVF_L1_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_UDF_L1_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_UDF_L1_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_OVF_L2_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_OVF_L2_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_UDF_L2_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_UDF_L2_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_DSCR_TASK_OVF_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_DSCR_TASK_OVF_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ENA_CH4: TX CH4 interrupt ena register +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_DONE_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_DONE_CH4_INT_ENA() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_EOF_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_EOF_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_DSCR_ERR_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_DSCR_ERR_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_TOTAL_EOF_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_TOTAL_EOF_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_OVF_L1_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_OVF_L1_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_UDF_L1_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_UDF_L1_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_OVF_L2_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_OVF_L2_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_UDF_L2_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_UDF_L2_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_ST_CH4: TX CH4 interrupt st register +func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_DONE_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_DONE_CH4_INT_ST() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_EOF_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_EOF_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_DSCR_ERR_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_DSCR_ERR_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_TOTAL_EOF_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_TOTAL_EOF_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_OVF_L1_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_OVF_L1_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_UDF_L1_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_UDF_L1_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_OVF_L2_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_OVF_L2_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_UDF_L2_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_UDF_L2_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUT_INT_CLR_CH4: TX CH4 interrupt clr register +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_DONE_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_DONE_CH4_INT_CLR() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_EOF_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_EOF_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_DSCR_ERR_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_DSCR_ERR_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_TOTAL_EOF_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_TOTAL_EOF_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_OVF_L1_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_OVF_L1_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_UDF_L1_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_UDF_L1_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_OVF_L2_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_OVF_L2_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_UDF_L2_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_UDF_L2_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_DSCR_TASK_OVF_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_DSCR_TASK_OVF_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x100) >> 8 +} + +// H264_DMA.OUTFIFO_STATUS_CH4: TX CH4 outfifo status register +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L2_CH4(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L2_CH4() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L2_CH4(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L2_CH4() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L2_CH4(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L2_CH4() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L1_CH4(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L1_CH4() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L1_CH4(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L1_CH4() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L1_CH4(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L1_CH4() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L3_CH4(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L3_CH4() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L3_CH4(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L3_CH4() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L3_CH4(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L3_CH4() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.OUT_PUSH_CH4: TX CH4 outfifo push register +func (o *H264_DMA_Type) SetOUT_PUSH_CH4_OUTFIFO_WDATA_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH4.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH4_OUTFIFO_WDATA_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg) & 0x3ff +} +func (o *H264_DMA_Type) SetOUT_PUSH_CH4_OUTFIFO_PUSH_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH4.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg)&^(0x400)|value<<10) +} +func (o *H264_DMA_Type) GetOUT_PUSH_CH4_OUTFIFO_PUSH_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg) & 0x400) >> 10 +} + +// H264_DMA.OUT_LINK_CONF_CH4: TX CH4 out_link dscr ctrl register +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH4_OUTLINK_STOP_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH4_OUTLINK_STOP_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH4_OUTLINK_START_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH4_OUTLINK_START_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH4_OUTLINK_RESTART_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH4_OUTLINK_RESTART_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH4_OUTLINK_PARK_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH4_OUTLINK_PARK_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg) & 0x800000) >> 23 +} + +// H264_DMA.OUT_LINK_ADDR_CH4: TX CH4 out_link dscr addr register +func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_ADDR_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH4.Reg) +} + +// H264_DMA.OUT_STATE_CH4: TX CH4 state register +func (o *H264_DMA_Type) SetOUT_STATE_CH4_OUTLINK_DSCR_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH4.Reg, volatile.LoadUint32(&o.OUT_STATE_CH4.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH4_OUTLINK_DSCR_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH4.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetOUT_STATE_CH4_OUT_DSCR_STATE_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH4.Reg, volatile.LoadUint32(&o.OUT_STATE_CH4.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH4_OUT_DSCR_STATE_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH4.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetOUT_STATE_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH4.Reg, volatile.LoadUint32(&o.OUT_STATE_CH4.Reg)&^(0xf00000)|value<<20) +} +func (o *H264_DMA_Type) GetOUT_STATE_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH4.Reg) & 0xf00000) >> 20 +} + +// H264_DMA.OUT_EOF_DES_ADDR_CH4: TX CH4 eof des addr register +func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH4.Reg) +} + +// H264_DMA.OUT_DSCR_CH4: TX CH4 next dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH4.Reg) +} + +// H264_DMA.OUT_DSCR_BF0_CH4: TX CH4 last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH4.Reg) +} + +// H264_DMA.OUT_DSCR_BF1_CH4: TX CH4 second-to-last dscr addr register +func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH4.Reg) +} + +// H264_DMA.OUT_ARB_CH4: TX CH4 arb register +func (o *H264_DMA_Type) SetOUT_ARB_CH4_OUT_ARB_TOKEN_NUM_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH4.Reg, volatile.LoadUint32(&o.OUT_ARB_CH4.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH4_OUT_ARB_TOKEN_NUM_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_ARB_CH4.Reg) & 0xf +} +func (o *H264_DMA_Type) SetOUT_ARB_CH4_EXTER_OUT_ARB_PRIORITY_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CH4.Reg, volatile.LoadUint32(&o.OUT_ARB_CH4.Reg)&^(0x30)|value<<4) +} +func (o *H264_DMA_Type) GetOUT_ARB_CH4_EXTER_OUT_ARB_PRIORITY_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_ARB_CH4.Reg) & 0x30) >> 4 +} + +// H264_DMA.OUT_ETM_CONF_CH4: TX CH4 ETM config register +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH4_OUT_ETM_EN_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH4_OUT_ETM_EN_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH4_OUT_ETM_LOOP_EN_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH4_OUT_ETM_LOOP_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH4_OUT_DSCR_TASK_MAK_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH4_OUT_DSCR_TASK_MAK_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg) & 0xc) >> 2 +} + +// H264_DMA.OUT_BUF_LEN_CH4: tx CH4 buf len register +func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH4_OUT_CMDFIFO_BUF_LEN_HB_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_BUF_LEN_CH4.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH4.Reg)&^(0x1fff)|value) +} +func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH4_OUT_CMDFIFO_BUF_LEN_HB_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_BUF_LEN_CH4.Reg) & 0x1fff +} + +// H264_DMA.OUT_FIFO_BCNT_CH4: tx CH4 fifo byte cnt register +func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH4_OUT_CMDFIFO_OUTFIFO_BCNT_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH4.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH4.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH4_OUT_CMDFIFO_OUTFIFO_BCNT_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH4.Reg) & 0x3ff +} + +// H264_DMA.OUT_PUSH_BYTECNT_CH4: tx CH4 push byte cnt register +func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH4_OUT_CMDFIFO_PUSH_BYTECNT_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH4.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH4.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH4_OUT_CMDFIFO_PUSH_BYTECNT_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH4.Reg) & 0xff +} + +// H264_DMA.OUT_XADDR_CH4: tx CH4 xaddr register +func (o *H264_DMA_Type) SetOUT_XADDR_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_XADDR_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetOUT_XADDR_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_XADDR_CH4.Reg) +} + +// H264_DMA.OUT_BLOCK_BUF_LEN_CH4: tx CH4 block buf len register +func (o *H264_DMA_Type) SetOUT_BLOCK_BUF_LEN_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_BLOCK_BUF_LEN_CH4.Reg, volatile.LoadUint32(&o.OUT_BLOCK_BUF_LEN_CH4.Reg)&^(0xfffffff)|value) +} +func (o *H264_DMA_Type) GetOUT_BLOCK_BUF_LEN_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_BLOCK_BUF_LEN_CH4.Reg) & 0xfffffff +} + +// H264_DMA.IN_CONF0_CH0: RX CH0 config0 register +func (o *H264_DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_ECC_AES_EN_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_ECC_AES_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_CHECK_OWNER_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_CHECK_OWNER_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_MEM_BURST_LENGTH_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_MEM_BURST_LENGTH_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_PAGE_BOUND_EN_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_PAGE_BOUND_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_RST_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1000000) >> 24 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_CMD_DISABLE_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_CMD_DISABLE_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2000000) >> 25 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_ARB_WEIGHT_OPT_DIS_CH0(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_ARB_WEIGHT_OPT_DIS_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.IN_INT_RAW_CH0: RX CH0 interrupt raw register +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_DONE_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_DONE_CH0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_SUC_EOF_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_SUC_EOF_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_ERR_EOF_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_ERR_EOF_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_ERR_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_ERR_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF_L1_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF_L1_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF_L1_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF_L1_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF_L2_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF_L2_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF_L2_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF_L2_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_TASK_OVF_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_TASK_OVF_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ENA_CH0: RX CH0 interrupt ena register +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_DONE_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_DONE_CH0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_SUC_EOF_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_SUC_EOF_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_ERR_EOF_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_ERR_EOF_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_ERR_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_ERR_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF_L1_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF_L1_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF_L1_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF_L1_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF_L2_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF_L2_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF_L2_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF_L2_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_TASK_OVF_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_TASK_OVF_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ST_CH0: RX CH0 interrupt st register +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_DONE_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_DONE_CH0_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_SUC_EOF_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_SUC_EOF_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_ERR_EOF_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_ERR_EOF_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_ERR_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_ERR_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_L1_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_L1_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_L1_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_L1_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_L2_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_L2_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_L2_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_L2_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_TASK_OVF_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_TASK_OVF_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_CLR_CH0: RX CH0 interrupt clr register +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_DONE_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_DONE_CH0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_SUC_EOF_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_SUC_EOF_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_ERR_EOF_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_ERR_EOF_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_ERR_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_ERR_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF_L1_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF_L1_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF_L1_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF_L1_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF_L2_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF_L2_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF_L2_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF_L2_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_TASK_OVF_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_TASK_OVF_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x200) >> 9 +} + +// H264_DMA.INFIFO_STATUS_CH0: RX CH0 INFIFO status register +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_L2_CH0(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_L2_CH0() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_L2_CH0(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_L2_CH0() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_L2_CH0(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_L2_CH0() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_L1_CH0(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_L1_CH0() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_L1_CH0(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_L1_CH0() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_L1_CH0(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_L1_CH0() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_L3_CH0(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_L3_CH0() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_L3_CH0(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_L3_CH0() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_L3_CH0(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_L3_CH0() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.IN_POP_CH0: RX CH0 INFIFO pop register +func (o *H264_DMA_Type) SetIN_POP_CH0_INFIFO_RDATA_CH0(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x7ff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_CH0_INFIFO_RDATA_CH0() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x7ff +} +func (o *H264_DMA_Type) SetIN_POP_CH0_INFIFO_POP_CH0(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x800)|value<<11) +} +func (o *H264_DMA_Type) GetIN_POP_CH0_INFIFO_POP_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x800) >> 11 +} + +// H264_DMA.IN_LINK_CONF_CH0: RX CH0 in_link dscr ctrl register +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_AUTO_RET_CH0(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_AUTO_RET_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_STOP_CH0(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_STOP_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_START_CH0(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_START_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_RESTART_CH0(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_RESTART_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x800000) >> 23 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_PARK_CH0(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_PARK_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x1000000) >> 24 +} + +// H264_DMA.IN_LINK_ADDR_CH0: RX CH0 in_link dscr addr register +func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_LINK_ADDR_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_LINK_ADDR_CH0.Reg) +} + +// H264_DMA.IN_STATE_CH0: RX CH0 state register +func (o *H264_DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetIN_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20 +} +func (o *H264_DMA_Type) SetIN_STATE_CH0_IN_RESET_AVAIL_CH0(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_STATE_CH0_IN_RESET_AVAIL_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x800000) >> 23 +} + +// H264_DMA.IN_SUC_EOF_DES_ADDR_CH0: RX CH0 eof des addr register +func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg) +} + +// H264_DMA.IN_ERR_EOF_DES_ADDR_CH0: RX CH0 err eof des addr register +func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg) +} + +// H264_DMA.IN_DSCR_CH0: RX CH0 next dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg) +} + +// H264_DMA.IN_DSCR_BF0_CH0: RX CH0 last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg) +} + +// H264_DMA.IN_DSCR_BF1_CH0: RX CH0 second-to-last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg) +} + +// H264_DMA.IN_ARB_CH0: RX CH0 arb register +func (o *H264_DMA_Type) SetIN_ARB_CH0_IN_ARB_TOKEN_NUM_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH0.Reg, volatile.LoadUint32(&o.IN_ARB_CH0.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetIN_ARB_CH0_IN_ARB_TOKEN_NUM_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ARB_CH0.Reg) & 0xf +} +func (o *H264_DMA_Type) SetIN_ARB_CH0_EXTER_IN_ARB_PRIORITY_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH0.Reg, volatile.LoadUint32(&o.IN_ARB_CH0.Reg)&^(0x30)|value<<4) +} +func (o *H264_DMA_Type) GetIN_ARB_CH0_EXTER_IN_ARB_PRIORITY_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CH0.Reg) & 0x30) >> 4 +} +func (o *H264_DMA_Type) SetIN_ARB_CH0_INTER_IN_ARB_PRIORITY_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH0.Reg, volatile.LoadUint32(&o.IN_ARB_CH0.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_ARB_CH0_INTER_IN_ARB_PRIORITY_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CH0.Reg) & 0x1c0) >> 6 +} + +// H264_DMA.IN_RO_PD_CONF_CH0: RX CH0 reorder power config register +func (o *H264_DMA_Type) SetIN_RO_PD_CONF_CH0_IN_RO_RAM_CLK_FO_CH0(value uint32) { + volatile.StoreUint32(&o.IN_RO_PD_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_RO_PD_CONF_CH0.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_RO_PD_CONF_CH0_IN_RO_RAM_CLK_FO_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_RO_PD_CONF_CH0.Reg) & 0x40) >> 6 +} + +// H264_DMA.IN_ETM_CONF_CH0: RX CH0 ETM config register +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH0_IN_ETM_EN_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH0_IN_ETM_EN_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH0_IN_ETM_LOOP_EN_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH0_IN_ETM_LOOP_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH0_IN_DSCR_TASK_MAK_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH0_IN_DSCR_TASK_MAK_CH0() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg) & 0xc) >> 2 +} + +// H264_DMA.IN_FIFO_CNT_CH0: rx CH0 fifo cnt register +func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH0_IN_CMDFIFO_INFIFO_CNT_CH0(value uint32) { + volatile.StoreUint32(&o.IN_FIFO_CNT_CH0.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH0.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH0_IN_CMDFIFO_INFIFO_CNT_CH0() uint32 { + return volatile.LoadUint32(&o.IN_FIFO_CNT_CH0.Reg) & 0x3ff +} + +// H264_DMA.IN_POP_DATA_CNT_CH0: rx CH0 pop data cnt register +func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH0_IN_CMDFIFO_POP_DATA_CNT_CH0(value uint32) { + volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH0.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH0.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH0_IN_CMDFIFO_POP_DATA_CNT_CH0() uint32 { + return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH0.Reg) & 0xff +} + +// H264_DMA.IN_XADDR_CH0: rx CH0 xaddr register +func (o *H264_DMA_Type) SetIN_XADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_XADDR_CH0.Reg, value) +} +func (o *H264_DMA_Type) GetIN_XADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_XADDR_CH0.Reg) +} + +// H264_DMA.IN_BUF_HB_RCV_CH0: rx CH0 buf len hb rcv register +func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH0_IN_CMDFIFO_BUF_HB_RCV_CH0(value uint32) { + volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH0.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH0.Reg)&^(0x1fffffff)|value) +} +func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH0_IN_CMDFIFO_BUF_HB_RCV_CH0() uint32 { + return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH0.Reg) & 0x1fffffff +} + +// H264_DMA.IN_CONF0_CH1: RX CH1 config0 register +func (o *H264_DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_ECC_AES_EN_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_ECC_AES_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_CHECK_OWNER_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_CHECK_OWNER_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_MEM_BURST_LENGTH_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_MEM_BURST_LENGTH_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_PAGE_BOUND_EN_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_PAGE_BOUND_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_RST_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_RST_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1000000) >> 24 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_CMD_DISABLE_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_CMD_DISABLE_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2000000) >> 25 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_ARB_WEIGHT_OPT_DIS_CH1(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_ARB_WEIGHT_OPT_DIS_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.IN_INT_RAW_CH1: RX CH1 interrupt raw register +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_DONE_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_DONE_CH1_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_SUC_EOF_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_SUC_EOF_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_ERR_EOF_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_ERR_EOF_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_ERR_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_ERR_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF_L1_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF_L1_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF_L1_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF_L1_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF_L2_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF_L2_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF_L2_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF_L2_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_TASK_OVF_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_TASK_OVF_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ENA_CH1: RX CH1 interrupt ena register +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_DONE_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_DONE_CH1_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_SUC_EOF_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_SUC_EOF_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_ERR_EOF_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_ERR_EOF_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_ERR_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_ERR_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF_L1_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF_L1_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF_L1_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF_L1_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF_L2_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF_L2_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF_L2_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF_L2_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_TASK_OVF_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_TASK_OVF_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ST_CH1: RX CH1 interrupt st register +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_DONE_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_DONE_CH1_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_SUC_EOF_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_SUC_EOF_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_ERR_EOF_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_ERR_EOF_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_ERR_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_ERR_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_L1_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_L1_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_L1_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_L1_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_L2_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_L2_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_L2_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_L2_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_TASK_OVF_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_TASK_OVF_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_CLR_CH1: RX CH1 interrupt clr register +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_DONE_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_DONE_CH1_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_SUC_EOF_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_SUC_EOF_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_ERR_EOF_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_ERR_EOF_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_ERR_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_ERR_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF_L1_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF_L1_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF_L1_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF_L1_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF_L2_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF_L2_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF_L2_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF_L2_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_TASK_OVF_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_TASK_OVF_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x200) >> 9 +} + +// H264_DMA.INFIFO_STATUS_CH1: RX CH1 INFIFO status register +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_L2_CH1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_L2_CH1() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_L2_CH1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_L2_CH1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_L2_CH1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_L2_CH1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_L1_CH1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_L1_CH1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_L1_CH1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_L1_CH1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_L1_CH1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_L1_CH1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_L3_CH1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_L3_CH1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_L3_CH1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_L3_CH1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_L3_CH1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_L3_CH1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.IN_POP_CH1: RX CH1 INFIFO pop register +func (o *H264_DMA_Type) SetIN_POP_CH1_INFIFO_RDATA_CH1(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x7ff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_CH1_INFIFO_RDATA_CH1() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x7ff +} +func (o *H264_DMA_Type) SetIN_POP_CH1_INFIFO_POP_CH1(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x800)|value<<11) +} +func (o *H264_DMA_Type) GetIN_POP_CH1_INFIFO_POP_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x800) >> 11 +} + +// H264_DMA.IN_LINK_CONF_CH1: RX CH1 in_link dscr ctrl register +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_AUTO_RET_CH1(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_AUTO_RET_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_STOP_CH1(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_STOP_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_START_CH1(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_START_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_RESTART_CH1(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_RESTART_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x800000) >> 23 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_PARK_CH1(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_PARK_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x1000000) >> 24 +} + +// H264_DMA.IN_LINK_ADDR_CH1: RX CH1 in_link dscr addr register +func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_LINK_ADDR_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_LINK_ADDR_CH1.Reg) +} + +// H264_DMA.IN_STATE_CH1: RX CH1 state register +func (o *H264_DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE_CH1(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetIN_STATE_CH1(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_STATE_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20 +} +func (o *H264_DMA_Type) SetIN_STATE_CH1_IN_RESET_AVAIL_CH1(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_STATE_CH1_IN_RESET_AVAIL_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x800000) >> 23 +} + +// H264_DMA.IN_SUC_EOF_DES_ADDR_CH1: RX CH1 eof des addr register +func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg) +} + +// H264_DMA.IN_ERR_EOF_DES_ADDR_CH1: RX CH1 err eof des addr register +func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg) +} + +// H264_DMA.IN_DSCR_CH1: RX CH1 next dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg) +} + +// H264_DMA.IN_DSCR_BF0_CH1: RX CH1 last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg) +} + +// H264_DMA.IN_DSCR_BF1_CH1: RX CH1 second-to-last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg) +} + +// H264_DMA.IN_ARB_CH1: RX CH1 arb register +func (o *H264_DMA_Type) SetIN_ARB_CH1_IN_ARB_TOKEN_NUM_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH1.Reg, volatile.LoadUint32(&o.IN_ARB_CH1.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetIN_ARB_CH1_IN_ARB_TOKEN_NUM_CH1() uint32 { + return volatile.LoadUint32(&o.IN_ARB_CH1.Reg) & 0xf +} +func (o *H264_DMA_Type) SetIN_ARB_CH1_EXTER_IN_ARB_PRIORITY_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH1.Reg, volatile.LoadUint32(&o.IN_ARB_CH1.Reg)&^(0x30)|value<<4) +} +func (o *H264_DMA_Type) GetIN_ARB_CH1_EXTER_IN_ARB_PRIORITY_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CH1.Reg) & 0x30) >> 4 +} +func (o *H264_DMA_Type) SetIN_ARB_CH1_INTER_IN_ARB_PRIORITY_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH1.Reg, volatile.LoadUint32(&o.IN_ARB_CH1.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_ARB_CH1_INTER_IN_ARB_PRIORITY_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CH1.Reg) & 0x1c0) >> 6 +} + +// H264_DMA.IN_ETM_CONF_CH1: RX CH1 ETM config register +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH1_IN_ETM_EN_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH1_IN_ETM_EN_CH1() uint32 { + return volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH1_IN_ETM_LOOP_EN_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH1_IN_ETM_LOOP_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH1_IN_DSCR_TASK_MAK_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH1_IN_DSCR_TASK_MAK_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg) & 0xc) >> 2 +} + +// H264_DMA.IN_FIFO_CNT_CH1: rx CH1 fifo cnt register +func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH1_IN_CMDFIFO_INFIFO_CNT_CH1(value uint32) { + volatile.StoreUint32(&o.IN_FIFO_CNT_CH1.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH1.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH1_IN_CMDFIFO_INFIFO_CNT_CH1() uint32 { + return volatile.LoadUint32(&o.IN_FIFO_CNT_CH1.Reg) & 0x3ff +} + +// H264_DMA.IN_POP_DATA_CNT_CH1: rx CH1 pop data cnt register +func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH1_IN_CMDFIFO_POP_DATA_CNT_CH1(value uint32) { + volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH1.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH1.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH1_IN_CMDFIFO_POP_DATA_CNT_CH1() uint32 { + return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH1.Reg) & 0xff +} + +// H264_DMA.IN_XADDR_CH1: rx CH1 xaddr register +func (o *H264_DMA_Type) SetIN_XADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_XADDR_CH1.Reg, value) +} +func (o *H264_DMA_Type) GetIN_XADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_XADDR_CH1.Reg) +} + +// H264_DMA.IN_BUF_HB_RCV_CH1: rx CH1 buf len hb rcv register +func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH1_IN_CMDFIFO_BUF_HB_RCV_CH1(value uint32) { + volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH1.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH1.Reg)&^(0x1fffffff)|value) +} +func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH1_IN_CMDFIFO_BUF_HB_RCV_CH1() uint32 { + return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH1.Reg) & 0x1fffffff +} + +// H264_DMA.IN_CONF0_CH2: RX CH2 config0 register +func (o *H264_DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_ECC_AES_EN_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_ECC_AES_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_CHECK_OWNER_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_CHECK_OWNER_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_MEM_BURST_LENGTH_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_MEM_BURST_LENGTH_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_PAGE_BOUND_EN_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_PAGE_BOUND_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_RST_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_RST_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1000000) >> 24 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_CMD_DISABLE_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_CMD_DISABLE_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2000000) >> 25 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_ARB_WEIGHT_OPT_DIS_CH2(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_ARB_WEIGHT_OPT_DIS_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.IN_INT_RAW_CH2: RX CH2 interrupt raw register +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_DONE_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_DONE_CH2_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_SUC_EOF_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_SUC_EOF_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_ERR_EOF_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_ERR_EOF_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_ERR_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_ERR_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF_L1_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF_L1_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF_L1_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF_L1_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF_L2_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF_L2_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF_L2_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF_L2_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_TASK_OVF_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_TASK_OVF_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ENA_CH2: RX CH2 interrupt ena register +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_DONE_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_DONE_CH2_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_SUC_EOF_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_SUC_EOF_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_ERR_EOF_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_ERR_EOF_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_ERR_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_ERR_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF_L1_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF_L1_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF_L1_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF_L1_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF_L2_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF_L2_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF_L2_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF_L2_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_TASK_OVF_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_TASK_OVF_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ST_CH2: RX CH2 interrupt st register +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_DONE_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_DONE_CH2_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_SUC_EOF_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_SUC_EOF_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_ERR_EOF_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_ERR_EOF_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_ERR_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_ERR_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_L1_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_L1_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_L1_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_L1_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_L2_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_L2_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_L2_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_L2_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_TASK_OVF_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_TASK_OVF_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_CLR_CH2: RX CH2 interrupt clr register +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_DONE_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_DONE_CH2_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_SUC_EOF_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_SUC_EOF_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_ERR_EOF_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_ERR_EOF_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_ERR_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_ERR_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF_L1_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF_L1_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF_L1_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF_L1_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF_L2_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF_L2_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF_L2_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF_L2_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_TASK_OVF_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_TASK_OVF_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x200) >> 9 +} + +// H264_DMA.INFIFO_STATUS_CH2: RX CH2 INFIFO status register +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_L2_CH2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_L2_CH2() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_L2_CH2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_L2_CH2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_L2_CH2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_L2_CH2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_L1_CH2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_L1_CH2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_L1_CH2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_L1_CH2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_L1_CH2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_L1_CH2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_L3_CH2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_L3_CH2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_L3_CH2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_L3_CH2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_L3_CH2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_L3_CH2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.IN_POP_CH2: RX CH2 INFIFO pop register +func (o *H264_DMA_Type) SetIN_POP_CH2_INFIFO_RDATA_CH2(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x7ff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_CH2_INFIFO_RDATA_CH2() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x7ff +} +func (o *H264_DMA_Type) SetIN_POP_CH2_INFIFO_POP_CH2(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x800)|value<<11) +} +func (o *H264_DMA_Type) GetIN_POP_CH2_INFIFO_POP_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x800) >> 11 +} + +// H264_DMA.IN_LINK_CONF_CH2: RX CH2 in_link dscr ctrl register +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_AUTO_RET_CH2(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_AUTO_RET_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_STOP_CH2(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_STOP_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_START_CH2(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_START_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_RESTART_CH2(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_RESTART_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x800000) >> 23 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_PARK_CH2(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_PARK_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x1000000) >> 24 +} + +// H264_DMA.IN_LINK_ADDR_CH2: RX CH2 in_link dscr addr register +func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_LINK_ADDR_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_LINK_ADDR_CH2.Reg) +} + +// H264_DMA.IN_STATE_CH2: RX CH2 state register +func (o *H264_DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE_CH2(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetIN_STATE_CH2(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_STATE_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20 +} +func (o *H264_DMA_Type) SetIN_STATE_CH2_IN_RESET_AVAIL_CH2(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_STATE_CH2_IN_RESET_AVAIL_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x800000) >> 23 +} + +// H264_DMA.IN_SUC_EOF_DES_ADDR_CH2: RX CH2 eof des addr register +func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg) +} + +// H264_DMA.IN_ERR_EOF_DES_ADDR_CH2: RX CH2 err eof des addr register +func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg) +} + +// H264_DMA.IN_DSCR_CH2: RX CH2 next dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg) +} + +// H264_DMA.IN_DSCR_BF0_CH2: RX CH2 last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg) +} + +// H264_DMA.IN_DSCR_BF1_CH2: RX CH2 second-to-last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg) +} + +// H264_DMA.IN_ARB_CH2: RX CH2 arb register +func (o *H264_DMA_Type) SetIN_ARB_CH2_IN_ARB_TOKEN_NUM_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH2.Reg, volatile.LoadUint32(&o.IN_ARB_CH2.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetIN_ARB_CH2_IN_ARB_TOKEN_NUM_CH2() uint32 { + return volatile.LoadUint32(&o.IN_ARB_CH2.Reg) & 0xf +} +func (o *H264_DMA_Type) SetIN_ARB_CH2_INTER_IN_ARB_PRIORITY_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH2.Reg, volatile.LoadUint32(&o.IN_ARB_CH2.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_ARB_CH2_INTER_IN_ARB_PRIORITY_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CH2.Reg) & 0x1c0) >> 6 +} + +// H264_DMA.IN_ETM_CONF_CH2: RX CH2 ETM config register +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH2_IN_ETM_EN_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH2_IN_ETM_EN_CH2() uint32 { + return volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH2_IN_ETM_LOOP_EN_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH2_IN_ETM_LOOP_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH2_IN_DSCR_TASK_MAK_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH2_IN_DSCR_TASK_MAK_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg) & 0xc) >> 2 +} + +// H264_DMA.IN_FIFO_CNT_CH2: rx CH2 fifo cnt register +func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH2_IN_CMDFIFO_INFIFO_CNT_CH2(value uint32) { + volatile.StoreUint32(&o.IN_FIFO_CNT_CH2.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH2.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH2_IN_CMDFIFO_INFIFO_CNT_CH2() uint32 { + return volatile.LoadUint32(&o.IN_FIFO_CNT_CH2.Reg) & 0x3ff +} + +// H264_DMA.IN_POP_DATA_CNT_CH2: rx CH2 pop data cnt register +func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH2_IN_CMDFIFO_POP_DATA_CNT_CH2(value uint32) { + volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH2.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH2.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH2_IN_CMDFIFO_POP_DATA_CNT_CH2() uint32 { + return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH2.Reg) & 0xff +} + +// H264_DMA.IN_XADDR_CH2: rx CH2 xaddr register +func (o *H264_DMA_Type) SetIN_XADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_XADDR_CH2.Reg, value) +} +func (o *H264_DMA_Type) GetIN_XADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_XADDR_CH2.Reg) +} + +// H264_DMA.IN_BUF_HB_RCV_CH2: rx CH2 buf len hb rcv register +func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH2_IN_CMDFIFO_BUF_HB_RCV_CH2(value uint32) { + volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH2.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH2.Reg)&^(0x1fffffff)|value) +} +func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH2_IN_CMDFIFO_BUF_HB_RCV_CH2() uint32 { + return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH2.Reg) & 0x1fffffff +} + +// H264_DMA.IN_CONF0_CH3: RX CH3 config0 register +func (o *H264_DMA_Type) SetIN_CONF0_CH3_INDSCR_BURST_EN_CH3(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH3_INDSCR_BURST_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_ECC_AES_EN_CH3(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_ECC_AES_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_CHECK_OWNER_CH3(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_CHECK_OWNER_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_MEM_BURST_LENGTH_CH3(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_MEM_BURST_LENGTH_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_PAGE_BOUND_EN_CH3(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_PAGE_BOUND_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_RST_CH3(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_RST_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x1000000) >> 24 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_CMD_DISABLE_CH3(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_CMD_DISABLE_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x2000000) >> 25 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_ARB_WEIGHT_OPT_DIS_CH3(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_ARB_WEIGHT_OPT_DIS_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.IN_INT_RAW_CH3: RX CH3 interrupt raw register +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_DONE_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_DONE_CH3_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_SUC_EOF_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_SUC_EOF_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_ERR_EOF_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_ERR_EOF_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_DSCR_ERR_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_DSCR_ERR_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_INFIFO_OVF_L1_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_INFIFO_OVF_L1_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_INFIFO_UDF_L1_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_INFIFO_UDF_L1_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_INFIFO_OVF_L2_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_INFIFO_OVF_L2_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_INFIFO_UDF_L2_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_INFIFO_UDF_L2_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_DSCR_EMPTY_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_DSCR_EMPTY_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_DSCR_TASK_OVF_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_DSCR_TASK_OVF_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ENA_CH3: RX CH3 interrupt ena register +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_DONE_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_DONE_CH3_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_SUC_EOF_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_SUC_EOF_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_ERR_EOF_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_ERR_EOF_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_DSCR_ERR_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_DSCR_ERR_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_INFIFO_OVF_L1_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_INFIFO_OVF_L1_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_INFIFO_UDF_L1_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_INFIFO_UDF_L1_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_INFIFO_OVF_L2_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_INFIFO_OVF_L2_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_INFIFO_UDF_L2_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_INFIFO_UDF_L2_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_DSCR_EMPTY_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_DSCR_EMPTY_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_DSCR_TASK_OVF_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_DSCR_TASK_OVF_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ST_CH3: RX CH3 interrupt st register +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_DONE_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_DONE_CH3_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_SUC_EOF_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_SUC_EOF_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_ERR_EOF_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_ERR_EOF_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_DSCR_ERR_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_DSCR_ERR_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_INFIFO_OVF_L1_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_INFIFO_OVF_L1_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_INFIFO_UDF_L1_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_INFIFO_UDF_L1_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_INFIFO_OVF_L2_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_INFIFO_OVF_L2_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_INFIFO_UDF_L2_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_INFIFO_UDF_L2_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_DSCR_EMPTY_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_DSCR_EMPTY_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_DSCR_TASK_OVF_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_DSCR_TASK_OVF_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_CLR_CH3: RX CH3 interrupt clr register +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_DONE_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_DONE_CH3_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_SUC_EOF_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_SUC_EOF_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_ERR_EOF_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_ERR_EOF_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_DSCR_ERR_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_DSCR_ERR_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_INFIFO_OVF_L1_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_INFIFO_OVF_L1_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_INFIFO_UDF_L1_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_INFIFO_UDF_L1_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_INFIFO_OVF_L2_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_INFIFO_OVF_L2_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_INFIFO_UDF_L2_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_INFIFO_UDF_L2_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_DSCR_EMPTY_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_DSCR_EMPTY_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_DSCR_TASK_OVF_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_DSCR_TASK_OVF_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x200) >> 9 +} + +// H264_DMA.INFIFO_STATUS_CH3: RX CH3 INFIFO status register +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_FULL_L2_CH3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_FULL_L2_CH3() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_EMPTY_L2_CH3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_EMPTY_L2_CH3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_CNT_L2_CH3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_CNT_L2_CH3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_FULL_L1_CH3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_FULL_L1_CH3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_EMPTY_L1_CH3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_EMPTY_L1_CH3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_CNT_L1_CH3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_CNT_L1_CH3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_FULL_L3_CH3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_FULL_L3_CH3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_EMPTY_L3_CH3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_EMPTY_L3_CH3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_CNT_L3_CH3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_CNT_L3_CH3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.IN_POP_CH3: RX CH3 INFIFO pop register +func (o *H264_DMA_Type) SetIN_POP_CH3_INFIFO_RDATA_CH3(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH3.Reg, volatile.LoadUint32(&o.IN_POP_CH3.Reg)&^(0x7ff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_CH3_INFIFO_RDATA_CH3() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH3.Reg) & 0x7ff +} +func (o *H264_DMA_Type) SetIN_POP_CH3_INFIFO_POP_CH3(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH3.Reg, volatile.LoadUint32(&o.IN_POP_CH3.Reg)&^(0x800)|value<<11) +} +func (o *H264_DMA_Type) GetIN_POP_CH3_INFIFO_POP_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH3.Reg) & 0x800) >> 11 +} + +// H264_DMA.IN_LINK_CONF_CH3: RX CH3 in_link dscr ctrl register +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_AUTO_RET_CH3(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_AUTO_RET_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_STOP_CH3(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_STOP_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_START_CH3(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_START_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_RESTART_CH3(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_RESTART_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x800000) >> 23 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_PARK_CH3(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_PARK_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x1000000) >> 24 +} + +// H264_DMA.IN_LINK_ADDR_CH3: RX CH3 in_link dscr addr register +func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.IN_LINK_ADDR_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.IN_LINK_ADDR_CH3.Reg) +} + +// H264_DMA.IN_STATE_CH3: RX CH3 state register +func (o *H264_DMA_Type) SetIN_STATE_CH3_INLINK_DSCR_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetIN_STATE_CH3_INLINK_DSCR_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetIN_STATE_CH3_IN_DSCR_STATE_CH3(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetIN_STATE_CH3_IN_DSCR_STATE_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetIN_STATE_CH3(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0x700000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_STATE_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0x700000) >> 20 +} +func (o *H264_DMA_Type) SetIN_STATE_CH3_IN_RESET_AVAIL_CH3(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_STATE_CH3_IN_RESET_AVAIL_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0x800000) >> 23 +} + +// H264_DMA.IN_SUC_EOF_DES_ADDR_CH3: RX CH3 eof des addr register +func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH3.Reg) +} + +// H264_DMA.IN_ERR_EOF_DES_ADDR_CH3: RX CH3 err eof des addr register +func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH3.Reg) +} + +// H264_DMA.IN_DSCR_CH3: RX CH3 next dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_CH3(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_CH3() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH3.Reg) +} + +// H264_DMA.IN_DSCR_BF0_CH3: RX CH3 last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH3(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH3() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH3.Reg) +} + +// H264_DMA.IN_DSCR_BF1_CH3: RX CH3 second-to-last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH3(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH3() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH3.Reg) +} + +// H264_DMA.IN_ARB_CH3: RX CH3 arb register +func (o *H264_DMA_Type) SetIN_ARB_CH3_IN_ARB_TOKEN_NUM_CH3(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH3.Reg, volatile.LoadUint32(&o.IN_ARB_CH3.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetIN_ARB_CH3_IN_ARB_TOKEN_NUM_CH3() uint32 { + return volatile.LoadUint32(&o.IN_ARB_CH3.Reg) & 0xf +} +func (o *H264_DMA_Type) SetIN_ARB_CH3_INTER_IN_ARB_PRIORITY_CH3(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH3.Reg, volatile.LoadUint32(&o.IN_ARB_CH3.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_ARB_CH3_INTER_IN_ARB_PRIORITY_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CH3.Reg) & 0x1c0) >> 6 +} + +// H264_DMA.IN_ETM_CONF_CH3: RX CH3 ETM config register +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH3_IN_ETM_EN_CH3(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH3_IN_ETM_EN_CH3() uint32 { + return volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH3_IN_ETM_LOOP_EN_CH3(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH3_IN_ETM_LOOP_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH3_IN_DSCR_TASK_MAK_CH3(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH3_IN_DSCR_TASK_MAK_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg) & 0xc) >> 2 +} + +// H264_DMA.IN_FIFO_CNT_CH3: rx CH3 fifo cnt register +func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH3_IN_CMDFIFO_INFIFO_CNT_CH3(value uint32) { + volatile.StoreUint32(&o.IN_FIFO_CNT_CH3.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH3.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH3_IN_CMDFIFO_INFIFO_CNT_CH3() uint32 { + return volatile.LoadUint32(&o.IN_FIFO_CNT_CH3.Reg) & 0x3ff +} + +// H264_DMA.IN_POP_DATA_CNT_CH3: rx CH3 pop data cnt register +func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH3_IN_CMDFIFO_POP_DATA_CNT_CH3(value uint32) { + volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH3.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH3.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH3_IN_CMDFIFO_POP_DATA_CNT_CH3() uint32 { + return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH3.Reg) & 0xff +} + +// H264_DMA.IN_XADDR_CH3: rx CH3 xaddr register +func (o *H264_DMA_Type) SetIN_XADDR_CH3(value uint32) { + volatile.StoreUint32(&o.IN_XADDR_CH3.Reg, value) +} +func (o *H264_DMA_Type) GetIN_XADDR_CH3() uint32 { + return volatile.LoadUint32(&o.IN_XADDR_CH3.Reg) +} + +// H264_DMA.IN_BUF_HB_RCV_CH3: rx CH3 buf len hb rcv register +func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH3_IN_CMDFIFO_BUF_HB_RCV_CH3(value uint32) { + volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH3.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH3.Reg)&^(0x1fffffff)|value) +} +func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH3_IN_CMDFIFO_BUF_HB_RCV_CH3() uint32 { + return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH3.Reg) & 0x1fffffff +} + +// H264_DMA.IN_CONF0_CH4: RX CH4 config0 register +func (o *H264_DMA_Type) SetIN_CONF0_CH4_INDSCR_BURST_EN_CH4(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH4_INDSCR_BURST_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_ECC_AES_EN_CH4(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_ECC_AES_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_CHECK_OWNER_CH4(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_CHECK_OWNER_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_MEM_BURST_LENGTH_CH4(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_MEM_BURST_LENGTH_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_PAGE_BOUND_EN_CH4(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_PAGE_BOUND_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_RST_CH4(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x1000000) >> 24 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_CMD_DISABLE_CH4(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_CMD_DISABLE_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x2000000) >> 25 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_ARB_WEIGHT_OPT_DIS_CH4(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x4000000)|value<<26) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_ARB_WEIGHT_OPT_DIS_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x4000000) >> 26 +} + +// H264_DMA.IN_INT_RAW_CH4: RX CH4 interrupt raw register +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_DONE_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_DONE_CH4_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_SUC_EOF_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_SUC_EOF_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_ERR_EOF_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_ERR_EOF_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_DSCR_ERR_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_DSCR_ERR_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_INFIFO_OVF_L1_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_INFIFO_OVF_L1_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_INFIFO_UDF_L1_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_INFIFO_UDF_L1_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_INFIFO_OVF_L2_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_INFIFO_OVF_L2_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_INFIFO_UDF_L2_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_INFIFO_UDF_L2_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_DSCR_EMPTY_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_DSCR_EMPTY_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_DSCR_TASK_OVF_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_DSCR_TASK_OVF_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ENA_CH4: RX CH4 interrupt ena register +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_DONE_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_DONE_CH4_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_SUC_EOF_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_SUC_EOF_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_ERR_EOF_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_ERR_EOF_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_DSCR_ERR_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_DSCR_ERR_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_INFIFO_OVF_L1_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_INFIFO_OVF_L1_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_INFIFO_UDF_L1_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_INFIFO_UDF_L1_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_INFIFO_OVF_L2_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_INFIFO_OVF_L2_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_INFIFO_UDF_L2_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_INFIFO_UDF_L2_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_DSCR_EMPTY_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_DSCR_EMPTY_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_DSCR_TASK_OVF_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_DSCR_TASK_OVF_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_ST_CH4: RX CH4 interrupt st register +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_DONE_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_DONE_CH4_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_SUC_EOF_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_SUC_EOF_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_ERR_EOF_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_ERR_EOF_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_DSCR_ERR_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_DSCR_ERR_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_INFIFO_OVF_L1_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_INFIFO_OVF_L1_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_INFIFO_UDF_L1_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_INFIFO_UDF_L1_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_INFIFO_OVF_L2_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_INFIFO_OVF_L2_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_INFIFO_UDF_L2_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_INFIFO_UDF_L2_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_DSCR_EMPTY_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_DSCR_EMPTY_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_DSCR_TASK_OVF_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_DSCR_TASK_OVF_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x200) >> 9 +} + +// H264_DMA.IN_INT_CLR_CH4: RX CH4 interrupt clr register +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_DONE_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_DONE_CH4_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_SUC_EOF_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_SUC_EOF_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_ERR_EOF_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_ERR_EOF_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_DSCR_ERR_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_DSCR_ERR_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_INFIFO_OVF_L1_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_INFIFO_OVF_L1_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x10) >> 4 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_INFIFO_UDF_L1_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x20)|value<<5) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_INFIFO_UDF_L1_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x20) >> 5 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_INFIFO_OVF_L2_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_INFIFO_OVF_L2_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_INFIFO_UDF_L2_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_INFIFO_UDF_L2_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_DSCR_EMPTY_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x100)|value<<8) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_DSCR_EMPTY_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x100) >> 8 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_DSCR_TASK_OVF_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x200)|value<<9) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_DSCR_TASK_OVF_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x200) >> 9 +} + +// H264_DMA.INFIFO_STATUS_CH4: RX CH4 INFIFO status register +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_FULL_L2_CH4(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_FULL_L2_CH4() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_EMPTY_L2_CH4(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_EMPTY_L2_CH4() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_CNT_L2_CH4(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x3c)|value<<2) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_CNT_L2_CH4() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x3c) >> 2 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_FULL_L1_CH4(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x40)|value<<6) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_FULL_L1_CH4() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x40) >> 6 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_EMPTY_L1_CH4(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x80)|value<<7) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_EMPTY_L1_CH4() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x80) >> 7 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_CNT_L1_CH4(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x1f00)|value<<8) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_CNT_L1_CH4() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x1f00) >> 8 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_FULL_L3_CH4(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_FULL_L3_CH4() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x10000) >> 16 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_EMPTY_L3_CH4(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x20000)|value<<17) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_EMPTY_L3_CH4() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x20000) >> 17 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_CNT_L3_CH4(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_CNT_L3_CH4() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0xc0000) >> 18 +} + +// H264_DMA.IN_POP_CH4: RX CH4 INFIFO pop register +func (o *H264_DMA_Type) SetIN_POP_CH4_INFIFO_RDATA_CH4(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH4.Reg, volatile.LoadUint32(&o.IN_POP_CH4.Reg)&^(0x7ff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_CH4_INFIFO_RDATA_CH4() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH4.Reg) & 0x7ff +} +func (o *H264_DMA_Type) SetIN_POP_CH4_INFIFO_POP_CH4(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH4.Reg, volatile.LoadUint32(&o.IN_POP_CH4.Reg)&^(0x800)|value<<11) +} +func (o *H264_DMA_Type) GetIN_POP_CH4_INFIFO_POP_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH4.Reg) & 0x800) >> 11 +} + +// H264_DMA.IN_LINK_CONF_CH4: RX CH4 in_link dscr ctrl register +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_AUTO_RET_CH4(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x100000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_AUTO_RET_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x100000) >> 20 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_STOP_CH4(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x200000)|value<<21) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_STOP_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x200000) >> 21 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_START_CH4(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x400000)|value<<22) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_START_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x400000) >> 22 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_RESTART_CH4(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_RESTART_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x800000) >> 23 +} +func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_PARK_CH4(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_PARK_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x1000000) >> 24 +} + +// H264_DMA.IN_LINK_ADDR_CH4: RX CH4 in_link dscr addr register +func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.IN_LINK_ADDR_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.IN_LINK_ADDR_CH4.Reg) +} + +// H264_DMA.IN_STATE_CH4: RX CH4 state register +func (o *H264_DMA_Type) SetIN_STATE_CH4_INLINK_DSCR_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0x3ffff)|value) +} +func (o *H264_DMA_Type) GetIN_STATE_CH4_INLINK_DSCR_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0x3ffff +} +func (o *H264_DMA_Type) SetIN_STATE_CH4_IN_DSCR_STATE_CH4(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0xc0000)|value<<18) +} +func (o *H264_DMA_Type) GetIN_STATE_CH4_IN_DSCR_STATE_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0xc0000) >> 18 +} +func (o *H264_DMA_Type) SetIN_STATE_CH4(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0x700000)|value<<20) +} +func (o *H264_DMA_Type) GetIN_STATE_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0x700000) >> 20 +} +func (o *H264_DMA_Type) SetIN_STATE_CH4_IN_RESET_AVAIL_CH4(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0x800000)|value<<23) +} +func (o *H264_DMA_Type) GetIN_STATE_CH4_IN_RESET_AVAIL_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0x800000) >> 23 +} + +// H264_DMA.IN_SUC_EOF_DES_ADDR_CH4: RX CH4 eof des addr register +func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH4.Reg) +} + +// H264_DMA.IN_ERR_EOF_DES_ADDR_CH4: RX CH4 err eof des addr register +func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH4.Reg) +} + +// H264_DMA.IN_DSCR_CH4: RX CH4 next dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_CH4(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_CH4() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH4.Reg) +} + +// H264_DMA.IN_DSCR_BF0_CH4: RX CH4 last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH4(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH4() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH4.Reg) +} + +// H264_DMA.IN_DSCR_BF1_CH4: RX CH4 second-to-last dscr addr register +func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH4(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH4() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH4.Reg) +} + +// H264_DMA.IN_ARB_CH4: RX CH4 arb register +func (o *H264_DMA_Type) SetIN_ARB_CH4_IN_ARB_TOKEN_NUM_CH4(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH4.Reg, volatile.LoadUint32(&o.IN_ARB_CH4.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetIN_ARB_CH4_IN_ARB_TOKEN_NUM_CH4() uint32 { + return volatile.LoadUint32(&o.IN_ARB_CH4.Reg) & 0xf +} +func (o *H264_DMA_Type) SetIN_ARB_CH4_EXTER_IN_ARB_PRIORITY_CH4(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH4.Reg, volatile.LoadUint32(&o.IN_ARB_CH4.Reg)&^(0x30)|value<<4) +} +func (o *H264_DMA_Type) GetIN_ARB_CH4_EXTER_IN_ARB_PRIORITY_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CH4.Reg) & 0x30) >> 4 +} +func (o *H264_DMA_Type) SetIN_ARB_CH4_INTER_IN_ARB_PRIORITY_CH4(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH4.Reg, volatile.LoadUint32(&o.IN_ARB_CH4.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_ARB_CH4_INTER_IN_ARB_PRIORITY_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CH4.Reg) & 0x1c0) >> 6 +} + +// H264_DMA.IN_ETM_CONF_CH4: RX CH4 ETM config register +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH4_IN_ETM_EN_CH4(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH4_IN_ETM_EN_CH4() uint32 { + return volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH4_IN_ETM_LOOP_EN_CH4(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH4_IN_ETM_LOOP_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_ETM_CONF_CH4_IN_DSCR_TASK_MAK_CH4(value uint32) { + volatile.StoreUint32(&o.IN_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg)&^(0xc)|value<<2) +} +func (o *H264_DMA_Type) GetIN_ETM_CONF_CH4_IN_DSCR_TASK_MAK_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg) & 0xc) >> 2 +} + +// H264_DMA.IN_FIFO_CNT_CH4: rx CH4 fifo cnt register +func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH4_IN_CMDFIFO_INFIFO_CNT_CH4(value uint32) { + volatile.StoreUint32(&o.IN_FIFO_CNT_CH4.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH4.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH4_IN_CMDFIFO_INFIFO_CNT_CH4() uint32 { + return volatile.LoadUint32(&o.IN_FIFO_CNT_CH4.Reg) & 0x3ff +} + +// H264_DMA.IN_POP_DATA_CNT_CH4: rx CH4 pop data cnt register +func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH4_IN_CMDFIFO_POP_DATA_CNT_CH4(value uint32) { + volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH4.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH4.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH4_IN_CMDFIFO_POP_DATA_CNT_CH4() uint32 { + return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH4.Reg) & 0xff +} + +// H264_DMA.IN_XADDR_CH4: rx CH4 xaddr register +func (o *H264_DMA_Type) SetIN_XADDR_CH4(value uint32) { + volatile.StoreUint32(&o.IN_XADDR_CH4.Reg, value) +} +func (o *H264_DMA_Type) GetIN_XADDR_CH4() uint32 { + return volatile.LoadUint32(&o.IN_XADDR_CH4.Reg) +} + +// H264_DMA.IN_BUF_HB_RCV_CH4: rx CH4 buf len hb rcv register +func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH4_IN_CMDFIFO_BUF_HB_RCV_CH4(value uint32) { + volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH4.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH4.Reg)&^(0x1fffffff)|value) +} +func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH4_IN_CMDFIFO_BUF_HB_RCV_CH4() uint32 { + return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH4.Reg) & 0x1fffffff +} + +// H264_DMA.IN_CONF0_CH5: RX CH5 config0 register +func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_ECC_AES_EN_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_ECC_AES_EN_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_MEM_BURST_LENGTH_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_MEM_BURST_LENGTH_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x1c0) >> 6 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_PAGE_BOUND_EN_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x1000)|value<<12) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_PAGE_BOUND_EN_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x1000) >> 12 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_RST_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x1000000)|value<<24) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_RST_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x1000000) >> 24 +} +func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_CMD_DISABLE_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x2000000)|value<<25) +} +func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_CMD_DISABLE_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x2000000) >> 25 +} + +// H264_DMA.IN_CONF1_CH5: RX CH5 config1 register +func (o *H264_DMA_Type) SetIN_CONF1_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH5.Reg, value) +} +func (o *H264_DMA_Type) GetIN_CONF1_CH5() uint32 { + return volatile.LoadUint32(&o.IN_CONF1_CH5.Reg) +} + +// H264_DMA.IN_CONF2_CH5: RX CH5 config2 register +func (o *H264_DMA_Type) SetIN_CONF2_CH5_BLOCK_ROW_LENGTH_12LINE_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF2_CH5.Reg, volatile.LoadUint32(&o.IN_CONF2_CH5.Reg)&^(0xffff)|value) +} +func (o *H264_DMA_Type) GetIN_CONF2_CH5_BLOCK_ROW_LENGTH_12LINE_CH5() uint32 { + return volatile.LoadUint32(&o.IN_CONF2_CH5.Reg) & 0xffff +} +func (o *H264_DMA_Type) SetIN_CONF2_CH5_BLOCK_ROW_LENGTH_4LINE_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF2_CH5.Reg, volatile.LoadUint32(&o.IN_CONF2_CH5.Reg)&^(0xffff0000)|value<<16) +} +func (o *H264_DMA_Type) GetIN_CONF2_CH5_BLOCK_ROW_LENGTH_4LINE_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_CONF2_CH5.Reg) & 0xffff0000) >> 16 +} + +// H264_DMA.IN_CONF3_CH5: RX CH5 config3 register +func (o *H264_DMA_Type) SetIN_CONF3_CH5_BLOCK_LENGTH_12LINE_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF3_CH5.Reg, volatile.LoadUint32(&o.IN_CONF3_CH5.Reg)&^(0x3fff)|value) +} +func (o *H264_DMA_Type) GetIN_CONF3_CH5_BLOCK_LENGTH_12LINE_CH5() uint32 { + return volatile.LoadUint32(&o.IN_CONF3_CH5.Reg) & 0x3fff +} +func (o *H264_DMA_Type) SetIN_CONF3_CH5_BLOCK_LENGTH_4LINE_CH5(value uint32) { + volatile.StoreUint32(&o.IN_CONF3_CH5.Reg, volatile.LoadUint32(&o.IN_CONF3_CH5.Reg)&^(0xfffc000)|value<<14) +} +func (o *H264_DMA_Type) GetIN_CONF3_CH5_BLOCK_LENGTH_4LINE_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_CONF3_CH5.Reg) & 0xfffc000) >> 14 +} + +// H264_DMA.IN_INT_RAW_CH5: RX CH5 interrupt raw register +func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_IN_DONE_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_IN_DONE_CH5_INT_RAW() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_IN_SUC_EOF_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_IN_SUC_EOF_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_INFIFO_OVF_L1_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_INFIFO_OVF_L1_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_INFIFO_UDF_L1_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_INFIFO_UDF_L1_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x10) >> 4 +} + +// H264_DMA.IN_INT_ENA_CH5: RX CH5 interrupt ena register +func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_IN_DONE_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_IN_DONE_CH5_INT_ENA() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_IN_SUC_EOF_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_IN_SUC_EOF_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_INFIFO_OVF_L1_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_INFIFO_OVF_L1_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_INFIFO_UDF_L1_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_INFIFO_UDF_L1_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x10) >> 4 +} + +// H264_DMA.IN_INT_ST_CH5: RX CH5 interrupt st register +func (o *H264_DMA_Type) SetIN_INT_ST_CH5_IN_DONE_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH5_IN_DONE_CH5_INT_ST() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH5_IN_SUC_EOF_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH5_IN_SUC_EOF_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH5_INFIFO_OVF_L1_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH5_INFIFO_OVF_L1_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH5_INFIFO_UDF_L1_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH5_INFIFO_UDF_L1_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_ST_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_ST_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x10) >> 4 +} + +// H264_DMA.IN_INT_CLR_CH5: RX CH5 interrupt clr register +func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_IN_DONE_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_IN_DONE_CH5_INT_CLR() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_IN_SUC_EOF_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_IN_SUC_EOF_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_INFIFO_OVF_L1_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_INFIFO_OVF_L1_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_INFIFO_UDF_L1_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_INFIFO_UDF_L1_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x10) >> 4 +} + +// H264_DMA.INFIFO_STATUS_CH5: RX CH5 INFIFO status register +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH5_INFIFO_FULL_L1_CH5(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH5.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH5_INFIFO_FULL_L1_CH5() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH5_INFIFO_EMPTY_L1_CH5(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH5.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH5_INFIFO_EMPTY_L1_CH5() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetINFIFO_STATUS_CH5_INFIFO_CNT_L1_CH5(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH5.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg)&^(0x7c)|value<<2) +} +func (o *H264_DMA_Type) GetINFIFO_STATUS_CH5_INFIFO_CNT_L1_CH5() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg) & 0x7c) >> 2 +} + +// H264_DMA.IN_POP_CH5: RX CH5 INFIFO pop register +func (o *H264_DMA_Type) SetIN_POP_CH5_INFIFO_RDATA_CH5(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH5.Reg, volatile.LoadUint32(&o.IN_POP_CH5.Reg)&^(0x7ff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_CH5_INFIFO_RDATA_CH5() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH5.Reg) & 0x7ff +} +func (o *H264_DMA_Type) SetIN_POP_CH5_INFIFO_POP_CH5(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH5.Reg, volatile.LoadUint32(&o.IN_POP_CH5.Reg)&^(0x800)|value<<11) +} +func (o *H264_DMA_Type) GetIN_POP_CH5_INFIFO_POP_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH5.Reg) & 0x800) >> 11 +} + +// H264_DMA.IN_STATE_CH5: RX CH5 state register +func (o *H264_DMA_Type) SetIN_STATE_CH5(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH5.Reg, volatile.LoadUint32(&o.IN_STATE_CH5.Reg)&^(0x7)|value) +} +func (o *H264_DMA_Type) GetIN_STATE_CH5() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH5.Reg) & 0x7 +} +func (o *H264_DMA_Type) SetIN_STATE_CH5_IN_RESET_AVAIL_CH5(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH5.Reg, volatile.LoadUint32(&o.IN_STATE_CH5.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetIN_STATE_CH5_IN_RESET_AVAIL_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH5.Reg) & 0x8) >> 3 +} + +// H264_DMA.IN_ARB_CH5: RX CH5 arb register +func (o *H264_DMA_Type) SetIN_ARB_CH5_IN_ARB_TOKEN_NUM_CH5(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH5.Reg, volatile.LoadUint32(&o.IN_ARB_CH5.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetIN_ARB_CH5_IN_ARB_TOKEN_NUM_CH5() uint32 { + return volatile.LoadUint32(&o.IN_ARB_CH5.Reg) & 0xf +} +func (o *H264_DMA_Type) SetIN_ARB_CH5_INTER_IN_ARB_PRIORITY_CH5(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CH5.Reg, volatile.LoadUint32(&o.IN_ARB_CH5.Reg)&^(0x1c0)|value<<6) +} +func (o *H264_DMA_Type) GetIN_ARB_CH5_INTER_IN_ARB_PRIORITY_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CH5.Reg) & 0x1c0) >> 6 +} + +// H264_DMA.IN_FIFO_CNT_CH5: rx CH5 fifo cnt register +func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH5_IN_CMDFIFO_INFIFO_CNT_CH5(value uint32) { + volatile.StoreUint32(&o.IN_FIFO_CNT_CH5.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH5.Reg)&^(0x3ff)|value) +} +func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH5_IN_CMDFIFO_INFIFO_CNT_CH5() uint32 { + return volatile.LoadUint32(&o.IN_FIFO_CNT_CH5.Reg) & 0x3ff +} + +// H264_DMA.IN_POP_DATA_CNT_CH5: rx CH5 pop data cnt register +func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH5_IN_CMDFIFO_POP_DATA_CNT_CH5(value uint32) { + volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH5.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH5.Reg)&^(0xff)|value) +} +func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH5_IN_CMDFIFO_POP_DATA_CNT_CH5() uint32 { + return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH5.Reg) & 0xff +} + +// H264_DMA.IN_XADDR_CH5: rx CH5 xaddr register +func (o *H264_DMA_Type) SetIN_XADDR_CH5(value uint32) { + volatile.StoreUint32(&o.IN_XADDR_CH5.Reg, value) +} +func (o *H264_DMA_Type) GetIN_XADDR_CH5() uint32 { + return volatile.LoadUint32(&o.IN_XADDR_CH5.Reg) +} + +// H264_DMA.IN_BUF_HB_RCV_CH5: rx CH5 buf len hb rcv register +func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH5_IN_CMDFIFO_BUF_HB_RCV_CH5(value uint32) { + volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH5.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH5.Reg)&^(0x1fffffff)|value) +} +func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH5_IN_CMDFIFO_BUF_HB_RCV_CH5() uint32 { + return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH5.Reg) & 0x1fffffff +} + +// H264_DMA.INTER_AXI_ERR: inter memory axi err register +func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_RID_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_RID_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0xf +} +func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_RRESP_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0xf0)|value<<4) +} +func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_RRESP_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0xf0) >> 4 +} +func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_WRESP_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0xf00)|value<<8) +} +func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_WRESP_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0xf00) >> 8 +} +func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_RD_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0x7000)|value<<12) +} +func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_RD_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0x7000) >> 12 +} +func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_RD_BAK_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0x78000)|value<<15) +} +func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_RD_BAK_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0x78000) >> 15 +} +func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_WR_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0x380000)|value<<19) +} +func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_WR_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0x380000) >> 19 +} +func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_WR_BAK_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0x3c00000)|value<<22) +} +func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_WR_BAK_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0x3c00000) >> 22 +} + +// H264_DMA.EXTER_AXI_ERR: exter memory axi err register +func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_RID_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0xf)|value) +} +func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_RID_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0xf +} +func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_RRESP_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0xf0)|value<<4) +} +func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_RRESP_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0xf0) >> 4 +} +func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_WRESP_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0xf00)|value<<8) +} +func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_WRESP_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0xf00) >> 8 +} +func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_RD_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0x7000)|value<<12) +} +func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_RD_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0x7000) >> 12 +} +func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_RD_BAK_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0x78000)|value<<15) +} +func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_RD_BAK_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0x78000) >> 15 +} +func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_WR_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0x380000)|value<<19) +} +func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_WR_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0x380000) >> 19 +} +func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_WR_BAK_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0x3c00000)|value<<22) +} +func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_WR_BAK_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0x3c00000) >> 22 +} + +// H264_DMA.RST_CONF: axi reset config register +func (o *H264_DMA_Type) SetRST_CONF_INTER_AXIM_RD_RST(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetRST_CONF_INTER_AXIM_RD_RST() uint32 { + return volatile.LoadUint32(&o.RST_CONF.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetRST_CONF_INTER_AXIM_WR_RST(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetRST_CONF_INTER_AXIM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetRST_CONF_EXTER_AXIM_RD_RST(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetRST_CONF_EXTER_AXIM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetRST_CONF_EXTER_AXIM_WR_RST(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetRST_CONF_EXTER_AXIM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x8) >> 3 +} +func (o *H264_DMA_Type) SetRST_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x10)|value<<4) +} +func (o *H264_DMA_Type) GetRST_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x10) >> 4 +} + +// H264_DMA.INTER_MEM_START_ADDR0: Start address of inter memory range0 register +func (o *H264_DMA_Type) SetINTER_MEM_START_ADDR0(value uint32) { + volatile.StoreUint32(&o.INTER_MEM_START_ADDR0.Reg, value) +} +func (o *H264_DMA_Type) GetINTER_MEM_START_ADDR0() uint32 { + return volatile.LoadUint32(&o.INTER_MEM_START_ADDR0.Reg) +} + +// H264_DMA.INTER_MEM_END_ADDR0: end address of inter memory range0 register +func (o *H264_DMA_Type) SetINTER_MEM_END_ADDR0(value uint32) { + volatile.StoreUint32(&o.INTER_MEM_END_ADDR0.Reg, value) +} +func (o *H264_DMA_Type) GetINTER_MEM_END_ADDR0() uint32 { + return volatile.LoadUint32(&o.INTER_MEM_END_ADDR0.Reg) +} + +// H264_DMA.INTER_MEM_START_ADDR1: Start address of inter memory range1 register +func (o *H264_DMA_Type) SetINTER_MEM_START_ADDR1(value uint32) { + volatile.StoreUint32(&o.INTER_MEM_START_ADDR1.Reg, value) +} +func (o *H264_DMA_Type) GetINTER_MEM_START_ADDR1() uint32 { + return volatile.LoadUint32(&o.INTER_MEM_START_ADDR1.Reg) +} + +// H264_DMA.INTER_MEM_END_ADDR1: end address of inter memory range1 register +func (o *H264_DMA_Type) SetINTER_MEM_END_ADDR1(value uint32) { + volatile.StoreUint32(&o.INTER_MEM_END_ADDR1.Reg, value) +} +func (o *H264_DMA_Type) GetINTER_MEM_END_ADDR1() uint32 { + return volatile.LoadUint32(&o.INTER_MEM_END_ADDR1.Reg) +} + +// H264_DMA.EXTER_MEM_START_ADDR0: Start address of exter memory range0 register +func (o *H264_DMA_Type) SetEXTER_MEM_START_ADDR0(value uint32) { + volatile.StoreUint32(&o.EXTER_MEM_START_ADDR0.Reg, value) +} +func (o *H264_DMA_Type) GetEXTER_MEM_START_ADDR0() uint32 { + return volatile.LoadUint32(&o.EXTER_MEM_START_ADDR0.Reg) +} + +// H264_DMA.EXTER_MEM_END_ADDR0: end address of exter memory range0 register +func (o *H264_DMA_Type) SetEXTER_MEM_END_ADDR0(value uint32) { + volatile.StoreUint32(&o.EXTER_MEM_END_ADDR0.Reg, value) +} +func (o *H264_DMA_Type) GetEXTER_MEM_END_ADDR0() uint32 { + return volatile.LoadUint32(&o.EXTER_MEM_END_ADDR0.Reg) +} + +// H264_DMA.EXTER_MEM_START_ADDR1: Start address of exter memory range1 register +func (o *H264_DMA_Type) SetEXTER_MEM_START_ADDR1(value uint32) { + volatile.StoreUint32(&o.EXTER_MEM_START_ADDR1.Reg, value) +} +func (o *H264_DMA_Type) GetEXTER_MEM_START_ADDR1() uint32 { + return volatile.LoadUint32(&o.EXTER_MEM_START_ADDR1.Reg) +} + +// H264_DMA.EXTER_MEM_END_ADDR1: end address of exter memory range1 register +func (o *H264_DMA_Type) SetEXTER_MEM_END_ADDR1(value uint32) { + volatile.StoreUint32(&o.EXTER_MEM_END_ADDR1.Reg, value) +} +func (o *H264_DMA_Type) GetEXTER_MEM_END_ADDR1() uint32 { + return volatile.LoadUint32(&o.EXTER_MEM_END_ADDR1.Reg) +} + +// H264_DMA.OUT_ARB_CONFIG: reserved +func (o *H264_DMA_Type) SetOUT_ARB_CONFIG_OUT_ARB_TIMEOUT_NUM(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CONFIG.Reg, volatile.LoadUint32(&o.OUT_ARB_CONFIG.Reg)&^(0xffff)|value) +} +func (o *H264_DMA_Type) GetOUT_ARB_CONFIG_OUT_ARB_TIMEOUT_NUM() uint32 { + return volatile.LoadUint32(&o.OUT_ARB_CONFIG.Reg) & 0xffff +} +func (o *H264_DMA_Type) SetOUT_ARB_CONFIG_OUT_WEIGHT_EN(value uint32) { + volatile.StoreUint32(&o.OUT_ARB_CONFIG.Reg, volatile.LoadUint32(&o.OUT_ARB_CONFIG.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetOUT_ARB_CONFIG_OUT_WEIGHT_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_ARB_CONFIG.Reg) & 0x10000) >> 16 +} + +// H264_DMA.IN_ARB_CONFIG: reserved +func (o *H264_DMA_Type) SetIN_ARB_CONFIG_IN_ARB_TIMEOUT_NUM(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CONFIG.Reg, volatile.LoadUint32(&o.IN_ARB_CONFIG.Reg)&^(0xffff)|value) +} +func (o *H264_DMA_Type) GetIN_ARB_CONFIG_IN_ARB_TIMEOUT_NUM() uint32 { + return volatile.LoadUint32(&o.IN_ARB_CONFIG.Reg) & 0xffff +} +func (o *H264_DMA_Type) SetIN_ARB_CONFIG_IN_WEIGHT_EN(value uint32) { + volatile.StoreUint32(&o.IN_ARB_CONFIG.Reg, volatile.LoadUint32(&o.IN_ARB_CONFIG.Reg)&^(0x10000)|value<<16) +} +func (o *H264_DMA_Type) GetIN_ARB_CONFIG_IN_WEIGHT_EN() uint32 { + return (volatile.LoadUint32(&o.IN_ARB_CONFIG.Reg) & 0x10000) >> 16 +} + +// H264_DMA.DATE: reserved +func (o *H264_DMA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *H264_DMA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// H264_DMA.COUNTER_RST: counter reset register +func (o *H264_DMA_Type) SetCOUNTER_RST_RX_CH0_EXTER_COUNTER_RST(value uint32) { + volatile.StoreUint32(&o.COUNTER_RST.Reg, volatile.LoadUint32(&o.COUNTER_RST.Reg)&^(0x1)|value) +} +func (o *H264_DMA_Type) GetCOUNTER_RST_RX_CH0_EXTER_COUNTER_RST() uint32 { + return volatile.LoadUint32(&o.COUNTER_RST.Reg) & 0x1 +} +func (o *H264_DMA_Type) SetCOUNTER_RST_RX_CH1_EXTER_COUNTER_RST(value uint32) { + volatile.StoreUint32(&o.COUNTER_RST.Reg, volatile.LoadUint32(&o.COUNTER_RST.Reg)&^(0x2)|value<<1) +} +func (o *H264_DMA_Type) GetCOUNTER_RST_RX_CH1_EXTER_COUNTER_RST() uint32 { + return (volatile.LoadUint32(&o.COUNTER_RST.Reg) & 0x2) >> 1 +} +func (o *H264_DMA_Type) SetCOUNTER_RST_RX_CH2_INTER_COUNTER_RST(value uint32) { + volatile.StoreUint32(&o.COUNTER_RST.Reg, volatile.LoadUint32(&o.COUNTER_RST.Reg)&^(0x4)|value<<2) +} +func (o *H264_DMA_Type) GetCOUNTER_RST_RX_CH2_INTER_COUNTER_RST() uint32 { + return (volatile.LoadUint32(&o.COUNTER_RST.Reg) & 0x4) >> 2 +} +func (o *H264_DMA_Type) SetCOUNTER_RST_RX_CH5_INTER_COUNTER_RST(value uint32) { + volatile.StoreUint32(&o.COUNTER_RST.Reg, volatile.LoadUint32(&o.COUNTER_RST.Reg)&^(0x8)|value<<3) +} +func (o *H264_DMA_Type) GetCOUNTER_RST_RX_CH5_INTER_COUNTER_RST() uint32 { + return (volatile.LoadUint32(&o.COUNTER_RST.Reg) & 0x8) >> 3 +} + +// H264_DMA.RX_CH0_COUNTER: rx ch0 counter register +func (o *H264_DMA_Type) SetRX_CH0_COUNTER_RX_CH0_CNT(value uint32) { + volatile.StoreUint32(&o.RX_CH0_COUNTER.Reg, volatile.LoadUint32(&o.RX_CH0_COUNTER.Reg)&^(0x7fffff)|value) +} +func (o *H264_DMA_Type) GetRX_CH0_COUNTER_RX_CH0_CNT() uint32 { + return volatile.LoadUint32(&o.RX_CH0_COUNTER.Reg) & 0x7fffff +} + +// H264_DMA.RX_CH1_COUNTER: rx ch1 counter register +func (o *H264_DMA_Type) SetRX_CH1_COUNTER_RX_CH1_CNT(value uint32) { + volatile.StoreUint32(&o.RX_CH1_COUNTER.Reg, volatile.LoadUint32(&o.RX_CH1_COUNTER.Reg)&^(0x1fffff)|value) +} +func (o *H264_DMA_Type) GetRX_CH1_COUNTER_RX_CH1_CNT() uint32 { + return volatile.LoadUint32(&o.RX_CH1_COUNTER.Reg) & 0x1fffff +} + +// H264_DMA.RX_CH2_COUNTER: rx ch2 counter register +func (o *H264_DMA_Type) SetRX_CH2_COUNTER_RX_CH2_CNT(value uint32) { + volatile.StoreUint32(&o.RX_CH2_COUNTER.Reg, volatile.LoadUint32(&o.RX_CH2_COUNTER.Reg)&^(0x7ff)|value) +} +func (o *H264_DMA_Type) GetRX_CH2_COUNTER_RX_CH2_CNT() uint32 { + return volatile.LoadUint32(&o.RX_CH2_COUNTER.Reg) & 0x7ff +} + +// H264_DMA.RX_CH5_COUNTER: rx ch5 counter register +func (o *H264_DMA_Type) SetRX_CH5_COUNTER_RX_CH5_CNT(value uint32) { + volatile.StoreUint32(&o.RX_CH5_COUNTER.Reg, volatile.LoadUint32(&o.RX_CH5_COUNTER.Reg)&^(0x1ffff)|value) +} +func (o *H264_DMA_Type) GetRX_CH5_COUNTER_RX_CH5_CNT() uint32 { + return volatile.LoadUint32(&o.RX_CH5_COUNTER.Reg) & 0x1ffff +} + +// HMAC (Hash-based Message Authentication Code) Accelerator +type HMAC_Type struct { + _ [64]byte + SET_START volatile.Register32 // 0x40 + SET_PARA_PURPOSE volatile.Register32 // 0x44 + SET_PARA_KEY volatile.Register32 // 0x48 + SET_PARA_FINISH volatile.Register32 // 0x4C + SET_MESSAGE_ONE volatile.Register32 // 0x50 + SET_MESSAGE_ING volatile.Register32 // 0x54 + SET_MESSAGE_END volatile.Register32 // 0x58 + SET_RESULT_FINISH volatile.Register32 // 0x5C + SET_INVALIDATE_JTAG volatile.Register32 // 0x60 + SET_INVALIDATE_DS volatile.Register32 // 0x64 + QUERY_ERROR volatile.Register32 // 0x68 + QUERY_BUSY volatile.Register32 // 0x6C + _ [16]byte + WR_MESSAGE_MEM [16]volatile.Register32 // 0x80 + RD_RESULT_MEM [8]volatile.Register32 // 0xC0 + _ [16]byte + SET_MESSAGE_PAD volatile.Register32 // 0xF0 + ONE_BLOCK volatile.Register32 // 0xF4 + SOFT_JTAG_CTRL volatile.Register32 // 0xF8 + WR_JTAG volatile.Register32 // 0xFC + _ [252]byte + DATE volatile.Register32 // 0x1FC +} + +// HMAC.SET_START: Process control register 0. +func (o *HMAC_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// HMAC.SET_PARA_PURPOSE: Configure purpose. +func (o *HMAC_Type) SetSET_PARA_PURPOSE_PURPOSE_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_PURPOSE.Reg, volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg)&^(0xf)|value) +} +func (o *HMAC_Type) GetSET_PARA_PURPOSE_PURPOSE_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg) & 0xf +} + +// HMAC.SET_PARA_KEY: Configure key. +func (o *HMAC_Type) SetSET_PARA_KEY_KEY_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_KEY.Reg, volatile.LoadUint32(&o.SET_PARA_KEY.Reg)&^(0x7)|value) +} +func (o *HMAC_Type) GetSET_PARA_KEY_KEY_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_KEY.Reg) & 0x7 +} + +// HMAC.SET_PARA_FINISH: Finish initial configuration. +func (o *HMAC_Type) SetSET_PARA_FINISH_SET_PARA_END(value uint32) { + volatile.StoreUint32(&o.SET_PARA_FINISH.Reg, volatile.LoadUint32(&o.SET_PARA_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_PARA_FINISH_SET_PARA_END() uint32 { + return volatile.LoadUint32(&o.SET_PARA_FINISH.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ONE: Process control register 1. +func (o *HMAC_Type) SetSET_MESSAGE_ONE_SET_TEXT_ONE(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ONE.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ONE_SET_TEXT_ONE() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ING: Process control register 2. +func (o *HMAC_Type) SetSET_MESSAGE_ING_SET_TEXT_ING(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ING.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ING_SET_TEXT_ING() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_END: Process control register 3. +func (o *HMAC_Type) SetSET_MESSAGE_END_SET_TEXT_END(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_END.Reg, volatile.LoadUint32(&o.SET_MESSAGE_END.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_END_SET_TEXT_END() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_END.Reg) & 0x1 +} + +// HMAC.SET_RESULT_FINISH: Process control register 4. +func (o *HMAC_Type) SetSET_RESULT_FINISH_SET_RESULT_END(value uint32) { + volatile.StoreUint32(&o.SET_RESULT_FINISH.Reg, volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_RESULT_FINISH_SET_RESULT_END() uint32 { + return volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_JTAG: Invalidate register 0. +func (o *HMAC_Type) SetSET_INVALIDATE_JTAG(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_JTAG.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_JTAG() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_DS: Invalidate register 1. +func (o *HMAC_Type) SetSET_INVALIDATE_DS(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_DS.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_DS() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg) & 0x1 +} + +// HMAC.QUERY_ERROR: Error register. +func (o *HMAC_Type) SetQUERY_ERROR_QUERY_CHECK(value uint32) { + volatile.StoreUint32(&o.QUERY_ERROR.Reg, volatile.LoadUint32(&o.QUERY_ERROR.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_ERROR_QUERY_CHECK() uint32 { + return volatile.LoadUint32(&o.QUERY_ERROR.Reg) & 0x1 +} + +// HMAC.QUERY_BUSY: Busy register. +func (o *HMAC_Type) SetQUERY_BUSY_BUSY_STATE(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_BUSY_BUSY_STATE() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_PAD: Process control register 5. +func (o *HMAC_Type) SetSET_MESSAGE_PAD_SET_TEXT_PAD(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_PAD.Reg, volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_PAD_SET_TEXT_PAD() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg) & 0x1 +} + +// HMAC.ONE_BLOCK: Process control register 6. +func (o *HMAC_Type) SetONE_BLOCK_SET_ONE_BLOCK(value uint32) { + volatile.StoreUint32(&o.ONE_BLOCK.Reg, volatile.LoadUint32(&o.ONE_BLOCK.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetONE_BLOCK_SET_ONE_BLOCK() uint32 { + return volatile.LoadUint32(&o.ONE_BLOCK.Reg) & 0x1 +} + +// HMAC.SOFT_JTAG_CTRL: Jtag register 0. +func (o *HMAC_Type) SetSOFT_JTAG_CTRL(value uint32) { + volatile.StoreUint32(&o.SOFT_JTAG_CTRL.Reg, volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSOFT_JTAG_CTRL() uint32 { + return volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg) & 0x1 +} + +// HMAC.WR_JTAG: Jtag register 1. +func (o *HMAC_Type) SetWR_JTAG(value uint32) { + volatile.StoreUint32(&o.WR_JTAG.Reg, value) +} +func (o *HMAC_Type) GetWR_JTAG() uint32 { + return volatile.LoadUint32(&o.WR_JTAG.Reg) +} + +// HMAC.DATE: Date register. +func (o *HMAC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *HMAC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// High-Power System +type HP_SYS_Type struct { + VER_DATE volatile.Register32 // 0x0 + CLK_EN volatile.Register32 // 0x4 + _ [8]byte + CPU_INTR_FROM_CPU_0 volatile.Register32 // 0x10 + CPU_INTR_FROM_CPU_1 volatile.Register32 // 0x14 + CPU_INTR_FROM_CPU_2 volatile.Register32 // 0x18 + CPU_INTR_FROM_CPU_3 volatile.Register32 // 0x1C + CACHE_CLK_CONFIG volatile.Register32 // 0x20 + CACHE_RESET_CONFIG volatile.Register32 // 0x24 + _ [4]byte + DMA_ADDR_CTRL volatile.Register32 // 0x2C + _ [4]byte + TCM_RAM_WRR_CONFIG volatile.Register32 // 0x34 + TCM_SW_PARITY_BWE_MASK volatile.Register32 // 0x38 + TCM_RAM_PWR_CTRL0 volatile.Register32 // 0x3C + L2_ROM_PWR_CTRL0 volatile.Register32 // 0x40 + _ [12]byte + PROBEA_CTRL volatile.Register32 // 0x50 + PROBEB_CTRL volatile.Register32 // 0x54 + _ [4]byte + PROBE_OUT volatile.Register32 // 0x5C + L2_MEM_RAM_PWR_CTRL0 volatile.Register32 // 0x60 + CPU_CORESTALLED_ST volatile.Register32 // 0x64 + _ [8]byte + CRYPTO_CTRL volatile.Register32 // 0x70 + GPIO_O_HOLD_CTRL0 volatile.Register32 // 0x74 + GPIO_O_HOLD_CTRL1 volatile.Register32 // 0x78 + RDN_ECO_CS volatile.Register32 // 0x7C + CACHE_APB_POSTW_EN volatile.Register32 // 0x80 + L2_MEM_SUBSIZE volatile.Register32 // 0x84 + _ [20]byte + L2_MEM_INT_RAW volatile.Register32 // 0x9C + L2_MEM_INT_ST volatile.Register32 // 0xA0 + L2_MEM_INT_ENA volatile.Register32 // 0xA4 + L2_MEM_INT_CLR volatile.Register32 // 0xA8 + L2_MEM_L2_RAM_ECC volatile.Register32 // 0xAC + L2_MEM_INT_RECORD0 volatile.Register32 // 0xB0 + L2_MEM_INT_RECORD1 volatile.Register32 // 0xB4 + _ [12]byte + L2_MEM_L2_CACHE_ECC volatile.Register32 // 0xC4 + L1CACHE_BUS0_ID volatile.Register32 // 0xC8 + L1CACHE_BUS1_ID volatile.Register32 // 0xCC + _ [8]byte + L2_MEM_RDN_ECO_CS volatile.Register32 // 0xD8 + L2_MEM_RDN_ECO_LOW volatile.Register32 // 0xDC + L2_MEM_RDN_ECO_HIGH volatile.Register32 // 0xE0 + TCM_RDN_ECO_CS volatile.Register32 // 0xE4 + TCM_RDN_ECO_LOW volatile.Register32 // 0xE8 + TCM_RDN_ECO_HIGH volatile.Register32 // 0xEC + GPIO_DED_HOLD_CTRL volatile.Register32 // 0xF0 + L2_MEM_SW_ECC_BWE_MASK volatile.Register32 // 0xF4 + USB20OTG_MEM_CTRL volatile.Register32 // 0xF8 + TCM_INT_RAW volatile.Register32 // 0xFC + TCM_INT_ST volatile.Register32 // 0x100 + TCM_INT_ENA volatile.Register32 // 0x104 + TCM_INT_CLR volatile.Register32 // 0x108 + TCM_PARITY_INT_RECORD volatile.Register32 // 0x10C + L1_CACHE_PWR_CTRL volatile.Register32 // 0x110 + L2_CACHE_PWR_CTRL volatile.Register32 // 0x114 + CPU_WAITI_CONF volatile.Register32 // 0x118 + CORE_DEBUG_RUNSTALL_CONF volatile.Register32 // 0x11C + CORE_AHB_TIMEOUT volatile.Register32 // 0x120 + CORE_IBUS_TIMEOUT volatile.Register32 // 0x124 + CORE_DBUS_TIMEOUT volatile.Register32 // 0x128 + _ [12]byte + ICM_CPU_H2X_CFG volatile.Register32 // 0x138 + PERI1_APB_POSTW_EN volatile.Register32 // 0x13C + BITSCRAMBLER_PERI_SEL volatile.Register32 // 0x140 + APB_SYNC_POSTW_EN volatile.Register32 // 0x144 + GDMA_CTRL volatile.Register32 // 0x148 + GMAC_CTRL0 volatile.Register32 // 0x14C + GMAC_CTRL1 volatile.Register32 // 0x150 + GMAC_CTRL2 volatile.Register32 // 0x154 + VPU_CTRL volatile.Register32 // 0x158 + USBOTG20_CTRL volatile.Register32 // 0x15C + TCM_ERR_RESP_CTRL volatile.Register32 // 0x160 + L2_MEM_REFRESH volatile.Register32 // 0x164 + TCM_INIT volatile.Register32 // 0x168 + TCM_PARITY_CHECK_CTRL volatile.Register32 // 0x16C + DESIGN_FOR_VERIFICATION0 volatile.Register32 // 0x170 + DESIGN_FOR_VERIFICATION1 volatile.Register32 // 0x174 + _ [8]byte + PSRAM_FLASH_ADDR_INTERCHANGE volatile.Register32 // 0x180 + _ [4]byte + AHB2AXI_BRESP_ERR_INT_RAW volatile.Register32 // 0x188 + AHB2AXI_BRESP_ERR_INT_ST volatile.Register32 // 0x18C + AHB2AXI_BRESP_ERR_INT_ENA volatile.Register32 // 0x190 + AHB2AXI_BRESP_ERR_INT_CLR volatile.Register32 // 0x194 + L2_MEM_ERR_RESP_CTRL volatile.Register32 // 0x198 + L2_MEM_AHB_BUFFER_CTRL volatile.Register32 // 0x19C + CORE_DMACTIVE_LPCORE volatile.Register32 // 0x1A0 + CORE_ERR_RESP_DIS volatile.Register32 // 0x1A4 + CORE_TIMEOUT_INT_RAW volatile.Register32 // 0x1A8 + CORE_TIMEOUT_INT_ST volatile.Register32 // 0x1AC + CORE_TIMEOUT_INT_ENA volatile.Register32 // 0x1B0 + CORE_TIMEOUT_INT_CLR volatile.Register32 // 0x1B4 + _ [8]byte + GPIO_O_HYS_CTRL0 volatile.Register32 // 0x1C0 + GPIO_O_HYS_CTRL1 volatile.Register32 // 0x1C4 + _ [8]byte + RSA_PD_CTRL volatile.Register32 // 0x1D0 + ECC_PD_CTRL volatile.Register32 // 0x1D4 + RNG_CFG volatile.Register32 // 0x1D8 + UART_PD_CTRL volatile.Register32 // 0x1DC + PERI_MEM_CLK_FORCE_ON volatile.Register32 // 0x1E0 +} + +// HP_SYS.VER_DATE: NA +func (o *HP_SYS_Type) SetVER_DATE(value uint32) { + volatile.StoreUint32(&o.VER_DATE.Reg, value) +} +func (o *HP_SYS_Type) GetVER_DATE() uint32 { + return volatile.LoadUint32(&o.VER_DATE.Reg) +} + +// HP_SYS.CLK_EN: NA +func (o *HP_SYS_Type) SetCLK_EN_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCLK_EN_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1 +} + +// HP_SYS.CPU_INTR_FROM_CPU_0: NA +func (o *HP_SYS_Type) SetCPU_INTR_FROM_CPU_0(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCPU_INTR_FROM_CPU_0() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg) & 0x1 +} + +// HP_SYS.CPU_INTR_FROM_CPU_1: NA +func (o *HP_SYS_Type) SetCPU_INTR_FROM_CPU_1(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCPU_INTR_FROM_CPU_1() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg) & 0x1 +} + +// HP_SYS.CPU_INTR_FROM_CPU_2: NA +func (o *HP_SYS_Type) SetCPU_INTR_FROM_CPU_2(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCPU_INTR_FROM_CPU_2() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg) & 0x1 +} + +// HP_SYS.CPU_INTR_FROM_CPU_3: NA +func (o *HP_SYS_Type) SetCPU_INTR_FROM_CPU_3(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCPU_INTR_FROM_CPU_3() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg) & 0x1 +} + +// HP_SYS.CACHE_CLK_CONFIG: NA +func (o *HP_SYS_Type) SetCACHE_CLK_CONFIG_REG_L2_CACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CLK_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCACHE_CLK_CONFIG_REG_L2_CACHE_CLK_ON() uint32 { + return volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCACHE_CLK_CONFIG_REG_L1_D_CACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CLK_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetCACHE_CLK_CONFIG_REG_L1_D_CACHE_CLK_ON() uint32 { + return (volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetCACHE_CLK_CONFIG_REG_L1_I1_CACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CLK_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_Type) GetCACHE_CLK_CONFIG_REG_L1_I1_CACHE_CLK_ON() uint32 { + return (volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_Type) SetCACHE_CLK_CONFIG_REG_L1_I0_CACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CLK_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_Type) GetCACHE_CLK_CONFIG_REG_L1_I0_CACHE_CLK_ON() uint32 { + return (volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg) & 0x20) >> 5 +} + +// HP_SYS.CACHE_RESET_CONFIG: NA +func (o *HP_SYS_Type) SetCACHE_RESET_CONFIG_REG_L1_D_CACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_RESET_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetCACHE_RESET_CONFIG_REG_L1_D_CACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetCACHE_RESET_CONFIG_REG_L1_I1_CACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_RESET_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_Type) GetCACHE_RESET_CONFIG_REG_L1_I1_CACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_Type) SetCACHE_RESET_CONFIG_REG_L1_I0_CACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_RESET_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_Type) GetCACHE_RESET_CONFIG_REG_L1_I0_CACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg) & 0x20) >> 5 +} + +// HP_SYS.DMA_ADDR_CTRL: NA +func (o *HP_SYS_Type) SetDMA_ADDR_CTRL_REG_SYS_DMA_ADDR_SEL(value uint32) { + volatile.StoreUint32(&o.DMA_ADDR_CTRL.Reg, volatile.LoadUint32(&o.DMA_ADDR_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetDMA_ADDR_CTRL_REG_SYS_DMA_ADDR_SEL() uint32 { + return volatile.LoadUint32(&o.DMA_ADDR_CTRL.Reg) & 0x1 +} + +// HP_SYS.TCM_RAM_WRR_CONFIG: NA +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS0_WT(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x7)|value) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS0_WT() uint32 { + return volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x7 +} +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS1_WT(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x38)|value<<3) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS1_WT() uint32 { + return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x38) >> 3 +} +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS2_WT(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x1c0)|value<<6) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS2_WT() uint32 { + return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x1c0) >> 6 +} +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS3_WT(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0xe00)|value<<9) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS3_WT() uint32 { + return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0xe00) >> 9 +} +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS0_WT(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x7000)|value<<12) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS0_WT() uint32 { + return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x7000) >> 12 +} +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS1_WT(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x38000)|value<<15) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS1_WT() uint32 { + return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x38000) >> 15 +} +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS2_WT(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x1c0000)|value<<18) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS2_WT() uint32 { + return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x1c0000) >> 18 +} +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS3_WT(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0xe00000)|value<<21) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS3_WT() uint32 { + return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0xe00000) >> 21 +} +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DMA_WT(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x7000000)|value<<24) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DMA_WT() uint32 { + return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x7000000) >> 24 +} +func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_WRR_HIGH(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_WRR_HIGH() uint32 { + return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x80000000) >> 31 +} + +// HP_SYS.TCM_SW_PARITY_BWE_MASK: NA +func (o *HP_SYS_Type) SetTCM_SW_PARITY_BWE_MASK_REG_TCM_SW_PARITY_BWE_MASK_CTRL(value uint32) { + volatile.StoreUint32(&o.TCM_SW_PARITY_BWE_MASK.Reg, volatile.LoadUint32(&o.TCM_SW_PARITY_BWE_MASK.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetTCM_SW_PARITY_BWE_MASK_REG_TCM_SW_PARITY_BWE_MASK_CTRL() uint32 { + return volatile.LoadUint32(&o.TCM_SW_PARITY_BWE_MASK.Reg) & 0x1 +} + +// HP_SYS.TCM_RAM_PWR_CTRL0: NA +func (o *HP_SYS_Type) SetTCM_RAM_PWR_CTRL0_REG_HP_TCM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.TCM_RAM_PWR_CTRL0.Reg, volatile.LoadUint32(&o.TCM_RAM_PWR_CTRL0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetTCM_RAM_PWR_CTRL0_REG_HP_TCM_CLK_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.TCM_RAM_PWR_CTRL0.Reg) & 0x1 +} + +// HP_SYS.L2_ROM_PWR_CTRL0: NA +func (o *HP_SYS_Type) SetL2_ROM_PWR_CTRL0_REG_L2_ROM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L2_ROM_PWR_CTRL0.Reg, volatile.LoadUint32(&o.L2_ROM_PWR_CTRL0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_ROM_PWR_CTRL0_REG_L2_ROM_CLK_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.L2_ROM_PWR_CTRL0.Reg) & 0x1 +} + +// HP_SYS.PROBEA_CTRL: NA +func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_A_MOD_SEL(value uint32) { + volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0xffff)|value) +} +func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_A_MOD_SEL() uint32 { + return volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0xffff +} +func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_A_TOP_SEL(value uint32) { + volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_A_TOP_SEL() uint32 { + return (volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_L_SEL(value uint32) { + volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0x3000000)|value<<24) +} +func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_L_SEL() uint32 { + return (volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0x3000000) >> 24 +} +func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_H_SEL(value uint32) { + volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0xc000000)|value<<26) +} +func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_H_SEL() uint32 { + return (volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0xc000000) >> 26 +} +func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_GLOBAL_EN(value uint32) { + volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_GLOBAL_EN() uint32 { + return (volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0x10000000) >> 28 +} + +// HP_SYS.PROBEB_CTRL: NA +func (o *HP_SYS_Type) SetPROBEB_CTRL_REG_PROBE_B_MOD_SEL(value uint32) { + volatile.StoreUint32(&o.PROBEB_CTRL.Reg, volatile.LoadUint32(&o.PROBEB_CTRL.Reg)&^(0xffff)|value) +} +func (o *HP_SYS_Type) GetPROBEB_CTRL_REG_PROBE_B_MOD_SEL() uint32 { + return volatile.LoadUint32(&o.PROBEB_CTRL.Reg) & 0xffff +} +func (o *HP_SYS_Type) SetPROBEB_CTRL_REG_PROBE_B_TOP_SEL(value uint32) { + volatile.StoreUint32(&o.PROBEB_CTRL.Reg, volatile.LoadUint32(&o.PROBEB_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_Type) GetPROBEB_CTRL_REG_PROBE_B_TOP_SEL() uint32 { + return (volatile.LoadUint32(&o.PROBEB_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_Type) SetPROBEB_CTRL_REG_PROBE_B_EN(value uint32) { + volatile.StoreUint32(&o.PROBEB_CTRL.Reg, volatile.LoadUint32(&o.PROBEB_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_Type) GetPROBEB_CTRL_REG_PROBE_B_EN() uint32 { + return (volatile.LoadUint32(&o.PROBEB_CTRL.Reg) & 0x1000000) >> 24 +} + +// HP_SYS.PROBE_OUT: NA +func (o *HP_SYS_Type) SetPROBE_OUT(value uint32) { + volatile.StoreUint32(&o.PROBE_OUT.Reg, value) +} +func (o *HP_SYS_Type) GetPROBE_OUT() uint32 { + return volatile.LoadUint32(&o.PROBE_OUT.Reg) +} + +// HP_SYS.L2_MEM_RAM_PWR_CTRL0: NA +func (o *HP_SYS_Type) SetL2_MEM_RAM_PWR_CTRL0_REG_L2_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.L2_MEM_RAM_PWR_CTRL0.Reg, volatile.LoadUint32(&o.L2_MEM_RAM_PWR_CTRL0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_RAM_PWR_CTRL0_REG_L2_MEM_CLK_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.L2_MEM_RAM_PWR_CTRL0.Reg) & 0x1 +} + +// HP_SYS.CPU_CORESTALLED_ST: NA +func (o *HP_SYS_Type) SetCPU_CORESTALLED_ST_REG_CORE0_CORESTALLED_ST(value uint32) { + volatile.StoreUint32(&o.CPU_CORESTALLED_ST.Reg, volatile.LoadUint32(&o.CPU_CORESTALLED_ST.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCPU_CORESTALLED_ST_REG_CORE0_CORESTALLED_ST() uint32 { + return volatile.LoadUint32(&o.CPU_CORESTALLED_ST.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCPU_CORESTALLED_ST_REG_CORE1_CORESTALLED_ST(value uint32) { + volatile.StoreUint32(&o.CPU_CORESTALLED_ST.Reg, volatile.LoadUint32(&o.CPU_CORESTALLED_ST.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetCPU_CORESTALLED_ST_REG_CORE1_CORESTALLED_ST() uint32 { + return (volatile.LoadUint32(&o.CPU_CORESTALLED_ST.Reg) & 0x2) >> 1 +} + +// HP_SYS.CRYPTO_CTRL: NA +func (o *HP_SYS_Type) SetCRYPTO_CTRL_REG_ENABLE_SPI_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.CRYPTO_CTRL.Reg, volatile.LoadUint32(&o.CRYPTO_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCRYPTO_CTRL_REG_ENABLE_SPI_MANUAL_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.CRYPTO_CTRL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.CRYPTO_CTRL.Reg, volatile.LoadUint32(&o.CRYPTO_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_DB_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.CRYPTO_CTRL.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.CRYPTO_CTRL.Reg, volatile.LoadUint32(&o.CRYPTO_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.CRYPTO_CTRL.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.CRYPTO_CTRL.Reg, volatile.LoadUint32(&o.CRYPTO_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.CRYPTO_CTRL.Reg) & 0x8) >> 3 +} + +// HP_SYS.GPIO_O_HOLD_CTRL0: NA +func (o *HP_SYS_Type) SetGPIO_O_HOLD_CTRL0(value uint32) { + volatile.StoreUint32(&o.GPIO_O_HOLD_CTRL0.Reg, value) +} +func (o *HP_SYS_Type) GetGPIO_O_HOLD_CTRL0() uint32 { + return volatile.LoadUint32(&o.GPIO_O_HOLD_CTRL0.Reg) +} + +// HP_SYS.GPIO_O_HOLD_CTRL1: NA +func (o *HP_SYS_Type) SetGPIO_O_HOLD_CTRL1_REG_GPIO_0_HOLD_HIGH(value uint32) { + volatile.StoreUint32(&o.GPIO_O_HOLD_CTRL1.Reg, volatile.LoadUint32(&o.GPIO_O_HOLD_CTRL1.Reg)&^(0x1ff)|value) +} +func (o *HP_SYS_Type) GetGPIO_O_HOLD_CTRL1_REG_GPIO_0_HOLD_HIGH() uint32 { + return volatile.LoadUint32(&o.GPIO_O_HOLD_CTRL1.Reg) & 0x1ff +} + +// HP_SYS.RDN_ECO_CS: NA +func (o *HP_SYS_Type) SetRDN_ECO_CS_REG_HP_SYS_RDN_ECO_EN(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetRDN_ECO_CS_REG_HP_SYS_RDN_ECO_EN() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetRDN_ECO_CS_REG_HP_SYS_RDN_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetRDN_ECO_CS_REG_HP_SYS_RDN_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x2) >> 1 +} + +// HP_SYS.CACHE_APB_POSTW_EN: NA +func (o *HP_SYS_Type) SetCACHE_APB_POSTW_EN_REG_CACHE_APB_POSTW_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_APB_POSTW_EN.Reg, volatile.LoadUint32(&o.CACHE_APB_POSTW_EN.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCACHE_APB_POSTW_EN_REG_CACHE_APB_POSTW_EN() uint32 { + return volatile.LoadUint32(&o.CACHE_APB_POSTW_EN.Reg) & 0x1 +} + +// HP_SYS.L2_MEM_SUBSIZE: NA +func (o *HP_SYS_Type) SetL2_MEM_SUBSIZE_REG_L2_MEM_SUB_BLKSIZE(value uint32) { + volatile.StoreUint32(&o.L2_MEM_SUBSIZE.Reg, volatile.LoadUint32(&o.L2_MEM_SUBSIZE.Reg)&^(0x3)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_SUBSIZE_REG_L2_MEM_SUB_BLKSIZE() uint32 { + return volatile.LoadUint32(&o.L2_MEM_SUBSIZE.Reg) & 0x3 +} + +// HP_SYS.L2_MEM_INT_RAW: NA +func (o *HP_SYS_Type) SetL2_MEM_INT_RAW_REG_L2_MEM_ECC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RAW_REG_L2_MEM_ECC_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_RAW_REG_L2_MEM_EXCEED_ADDR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RAW_REG_L2_MEM_EXCEED_ADDR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_RAW_REG_L2_MEM_ERR_RESP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RAW_REG_L2_MEM_ERR_RESP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg) & 0x4) >> 2 +} + +// HP_SYS.L2_MEM_INT_ST: NA +func (o *HP_SYS_Type) SetL2_MEM_INT_ST_REG_L2_MEM_ECC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_ST.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_ST_REG_L2_MEM_ECC_ERR_INT_ST() uint32 { + return volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_ST_REG_L2_MEM_EXCEED_ADDR_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_ST.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_ST_REG_L2_MEM_EXCEED_ADDR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_ST_REG_L2_MEM_ERR_RESP_INT_ST(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_ST.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_ST_REG_L2_MEM_ERR_RESP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg) & 0x4) >> 2 +} + +// HP_SYS.L2_MEM_INT_ENA: NA +func (o *HP_SYS_Type) SetL2_MEM_INT_ENA_REG_L2_MEM_ECC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_ENA_REG_L2_MEM_ECC_ERR_INT_ENA() uint32 { + return volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_ENA_REG_L2_MEM_EXCEED_ADDR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_ENA_REG_L2_MEM_EXCEED_ADDR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_ENA_REG_L2_MEM_ERR_RESP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_ENA_REG_L2_MEM_ERR_RESP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg) & 0x4) >> 2 +} + +// HP_SYS.L2_MEM_INT_CLR: NA +func (o *HP_SYS_Type) SetL2_MEM_INT_CLR_REG_L2_MEM_ECC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_CLR_REG_L2_MEM_ECC_ERR_INT_CLR() uint32 { + return volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_CLR_REG_L2_MEM_EXCEED_ADDR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_CLR_REG_L2_MEM_EXCEED_ADDR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_CLR_REG_L2_MEM_ERR_RESP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_CLR_REG_L2_MEM_ERR_RESP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg) & 0x4) >> 2 +} + +// HP_SYS.L2_MEM_L2_RAM_ECC: NA +func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT0_ECC_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT0_ECC_EN() uint32 { + return volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT1_ECC_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT1_ECC_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT2_ECC_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT2_ECC_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT3_ECC_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT3_ECC_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT4_ECC_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT4_ECC_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT5_ECC_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT5_ECC_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x20) >> 5 +} + +// HP_SYS.L2_MEM_INT_RECORD0: NA +func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RECORD0.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg)&^(0x1fffff)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg) & 0x1fffff +} +func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_WE(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RECORD0.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_WE() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_MASTER(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RECORD0.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg)&^(0x1c00000)|value<<22) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_MASTER() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg) & 0x1c00000) >> 22 +} + +// HP_SYS.L2_MEM_INT_RECORD1: NA +func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_INT_ADDR(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x7fff)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_INT_ADDR() uint32 { + return volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x7fff +} +func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ONE_BIT_ERR(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ONE_BIT_ERR() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_TWO_BIT_ERR(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_TWO_BIT_ERR() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_BIT(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x3fe0000)|value<<17) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_BIT() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x3fe0000) >> 17 +} +func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_CACHE_ERR_BANK(value uint32) { + volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_CACHE_ERR_BANK() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x4000000) >> 26 +} + +// HP_SYS.L2_MEM_L2_CACHE_ECC: NA +func (o *HP_SYS_Type) SetL2_MEM_L2_CACHE_ECC_REG_L2_CACHE_ECC_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_L2_CACHE_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_CACHE_ECC.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_L2_CACHE_ECC_REG_L2_CACHE_ECC_EN() uint32 { + return volatile.LoadUint32(&o.L2_MEM_L2_CACHE_ECC.Reg) & 0x1 +} + +// HP_SYS.L1CACHE_BUS0_ID: NA +func (o *HP_SYS_Type) SetL1CACHE_BUS0_ID_REG_L1_CACHE_BUS0_ID(value uint32) { + volatile.StoreUint32(&o.L1CACHE_BUS0_ID.Reg, volatile.LoadUint32(&o.L1CACHE_BUS0_ID.Reg)&^(0xf)|value) +} +func (o *HP_SYS_Type) GetL1CACHE_BUS0_ID_REG_L1_CACHE_BUS0_ID() uint32 { + return volatile.LoadUint32(&o.L1CACHE_BUS0_ID.Reg) & 0xf +} + +// HP_SYS.L1CACHE_BUS1_ID: NA +func (o *HP_SYS_Type) SetL1CACHE_BUS1_ID_REG_L1_CACHE_BUS1_ID(value uint32) { + volatile.StoreUint32(&o.L1CACHE_BUS1_ID.Reg, volatile.LoadUint32(&o.L1CACHE_BUS1_ID.Reg)&^(0xf)|value) +} +func (o *HP_SYS_Type) GetL1CACHE_BUS1_ID_REG_L1_CACHE_BUS1_ID() uint32 { + return volatile.LoadUint32(&o.L1CACHE_BUS1_ID.Reg) & 0xf +} + +// HP_SYS.L2_MEM_RDN_ECO_CS: NA +func (o *HP_SYS_Type) SetL2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.L2_MEM_RDN_ECO_CS.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_EN() uint32 { + return volatile.LoadUint32(&o.L2_MEM_RDN_ECO_CS.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetL2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.L2_MEM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.L2_MEM_RDN_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetL2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_RDN_ECO_CS.Reg) & 0x2) >> 1 +} + +// HP_SYS.L2_MEM_RDN_ECO_LOW: NA +func (o *HP_SYS_Type) SetL2_MEM_RDN_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.L2_MEM_RDN_ECO_LOW.Reg, value) +} +func (o *HP_SYS_Type) GetL2_MEM_RDN_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.L2_MEM_RDN_ECO_LOW.Reg) +} + +// HP_SYS.L2_MEM_RDN_ECO_HIGH: NA +func (o *HP_SYS_Type) SetL2_MEM_RDN_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.L2_MEM_RDN_ECO_HIGH.Reg, value) +} +func (o *HP_SYS_Type) GetL2_MEM_RDN_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.L2_MEM_RDN_ECO_HIGH.Reg) +} + +// HP_SYS.TCM_RDN_ECO_CS: NA +func (o *HP_SYS_Type) SetTCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_EN(value uint32) { + volatile.StoreUint32(&o.TCM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.TCM_RDN_ECO_CS.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetTCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_EN() uint32 { + return volatile.LoadUint32(&o.TCM_RDN_ECO_CS.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetTCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.TCM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.TCM_RDN_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetTCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.TCM_RDN_ECO_CS.Reg) & 0x2) >> 1 +} + +// HP_SYS.TCM_RDN_ECO_LOW: NA +func (o *HP_SYS_Type) SetTCM_RDN_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.TCM_RDN_ECO_LOW.Reg, value) +} +func (o *HP_SYS_Type) GetTCM_RDN_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.TCM_RDN_ECO_LOW.Reg) +} + +// HP_SYS.TCM_RDN_ECO_HIGH: NA +func (o *HP_SYS_Type) SetTCM_RDN_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.TCM_RDN_ECO_HIGH.Reg, value) +} +func (o *HP_SYS_Type) GetTCM_RDN_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.TCM_RDN_ECO_HIGH.Reg) +} + +// HP_SYS.GPIO_DED_HOLD_CTRL: NA +func (o *HP_SYS_Type) SetGPIO_DED_HOLD_CTRL_REG_GPIO_DED_HOLD(value uint32) { + volatile.StoreUint32(&o.GPIO_DED_HOLD_CTRL.Reg, volatile.LoadUint32(&o.GPIO_DED_HOLD_CTRL.Reg)&^(0x3ffffff)|value) +} +func (o *HP_SYS_Type) GetGPIO_DED_HOLD_CTRL_REG_GPIO_DED_HOLD() uint32 { + return volatile.LoadUint32(&o.GPIO_DED_HOLD_CTRL.Reg) & 0x3ffffff +} + +// HP_SYS.L2_MEM_SW_ECC_BWE_MASK: NA +func (o *HP_SYS_Type) SetL2_MEM_SW_ECC_BWE_MASK_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL(value uint32) { + volatile.StoreUint32(&o.L2_MEM_SW_ECC_BWE_MASK.Reg, volatile.LoadUint32(&o.L2_MEM_SW_ECC_BWE_MASK.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_SW_ECC_BWE_MASK_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL() uint32 { + return volatile.LoadUint32(&o.L2_MEM_SW_ECC_BWE_MASK.Reg) & 0x1 +} + +// HP_SYS.USB20OTG_MEM_CTRL: NA +func (o *HP_SYS_Type) SetUSB20OTG_MEM_CTRL_REG_USB20_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.USB20OTG_MEM_CTRL.Reg, volatile.LoadUint32(&o.USB20OTG_MEM_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetUSB20OTG_MEM_CTRL_REG_USB20_MEM_CLK_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.USB20OTG_MEM_CTRL.Reg) & 0x1 +} + +// HP_SYS.TCM_INT_RAW: need_des +func (o *HP_SYS_Type) SetTCM_INT_RAW_TCM_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.TCM_INT_RAW.Reg, volatile.LoadUint32(&o.TCM_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_Type) GetTCM_INT_RAW_TCM_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.TCM_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// HP_SYS.TCM_INT_ST: need_des +func (o *HP_SYS_Type) SetTCM_INT_ST_TCM_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.TCM_INT_ST.Reg, volatile.LoadUint32(&o.TCM_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_Type) GetTCM_INT_ST_TCM_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.TCM_INT_ST.Reg) & 0x80000000) >> 31 +} + +// HP_SYS.TCM_INT_ENA: need_des +func (o *HP_SYS_Type) SetTCM_INT_ENA_TCM_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.TCM_INT_ENA.Reg, volatile.LoadUint32(&o.TCM_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_Type) GetTCM_INT_ENA_TCM_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.TCM_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// HP_SYS.TCM_INT_CLR: need_des +func (o *HP_SYS_Type) SetTCM_INT_CLR_TCM_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.TCM_INT_CLR.Reg, volatile.LoadUint32(&o.TCM_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_Type) GetTCM_INT_CLR_TCM_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.TCM_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// HP_SYS.TCM_PARITY_INT_RECORD: need_des +func (o *HP_SYS_Type) SetTCM_PARITY_INT_RECORD_TCM_PARITY_ERR_INT_ADDR(value uint32) { + volatile.StoreUint32(&o.TCM_PARITY_INT_RECORD.Reg, volatile.LoadUint32(&o.TCM_PARITY_INT_RECORD.Reg)&^(0x1fff)|value) +} +func (o *HP_SYS_Type) GetTCM_PARITY_INT_RECORD_TCM_PARITY_ERR_INT_ADDR() uint32 { + return volatile.LoadUint32(&o.TCM_PARITY_INT_RECORD.Reg) & 0x1fff +} + +// HP_SYS.L1_CACHE_PWR_CTRL: NA +func (o *HP_SYS_Type) SetL1_CACHE_PWR_CTRL_REG_L1_CACHE_MEM_FO(value uint32) { + volatile.StoreUint32(&o.L1_CACHE_PWR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PWR_CTRL.Reg)&^(0x3f)|value) +} +func (o *HP_SYS_Type) GetL1_CACHE_PWR_CTRL_REG_L1_CACHE_MEM_FO() uint32 { + return volatile.LoadUint32(&o.L1_CACHE_PWR_CTRL.Reg) & 0x3f +} + +// HP_SYS.L2_CACHE_PWR_CTRL: NA +func (o *HP_SYS_Type) SetL2_CACHE_PWR_CTRL_REG_L2_CACHE_MEM_FO(value uint32) { + volatile.StoreUint32(&o.L2_CACHE_PWR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PWR_CTRL.Reg)&^(0x3)|value) +} +func (o *HP_SYS_Type) GetL2_CACHE_PWR_CTRL_REG_L2_CACHE_MEM_FO() uint32 { + return volatile.LoadUint32(&o.L2_CACHE_PWR_CTRL.Reg) & 0x3 +} + +// HP_SYS.CPU_WAITI_CONF: CPU_WAITI configuration register +func (o *HP_SYS_Type) SetCPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCPU_WAITI_CONF_CPU_WAITI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x1e)|value<<1) +} +func (o *HP_SYS_Type) GetCPU_WAITI_CONF_CPU_WAITI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x1e) >> 1 +} + +// HP_SYS.CORE_DEBUG_RUNSTALL_CONF: Core Debug runstall configure register +func (o *HP_SYS_Type) SetCORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE(value uint32) { + volatile.StoreUint32(&o.CORE_DEBUG_RUNSTALL_CONF.Reg, volatile.LoadUint32(&o.CORE_DEBUG_RUNSTALL_CONF.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE() uint32 { + return volatile.LoadUint32(&o.CORE_DEBUG_RUNSTALL_CONF.Reg) & 0x1 +} + +// HP_SYS.CORE_AHB_TIMEOUT: need_des +func (o *HP_SYS_Type) SetCORE_AHB_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_AHB_TIMEOUT.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_AHB_TIMEOUT_EN() uint32 { + return volatile.LoadUint32(&o.CORE_AHB_TIMEOUT.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCORE_AHB_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_AHB_TIMEOUT.Reg)&^(0x1fffe)|value<<1) +} +func (o *HP_SYS_Type) GetCORE_AHB_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.CORE_AHB_TIMEOUT.Reg) & 0x1fffe) >> 1 +} + +// HP_SYS.CORE_IBUS_TIMEOUT: need_des +func (o *HP_SYS_Type) SetCORE_IBUS_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.CORE_IBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_IBUS_TIMEOUT.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_IBUS_TIMEOUT_EN() uint32 { + return volatile.LoadUint32(&o.CORE_IBUS_TIMEOUT.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCORE_IBUS_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.CORE_IBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_IBUS_TIMEOUT.Reg)&^(0x1fffe)|value<<1) +} +func (o *HP_SYS_Type) GetCORE_IBUS_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.CORE_IBUS_TIMEOUT.Reg) & 0x1fffe) >> 1 +} + +// HP_SYS.CORE_DBUS_TIMEOUT: need_des +func (o *HP_SYS_Type) SetCORE_DBUS_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.CORE_DBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_DBUS_TIMEOUT.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_DBUS_TIMEOUT_EN() uint32 { + return volatile.LoadUint32(&o.CORE_DBUS_TIMEOUT.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCORE_DBUS_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.CORE_DBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_DBUS_TIMEOUT.Reg)&^(0x1fffe)|value<<1) +} +func (o *HP_SYS_Type) GetCORE_DBUS_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.CORE_DBUS_TIMEOUT.Reg) & 0x1fffe) >> 1 +} + +// HP_SYS.ICM_CPU_H2X_CFG: need_des +func (o *HP_SYS_Type) SetICM_CPU_H2X_CFG_CPU_ICM_H2X_POST_WR_EN(value uint32) { + volatile.StoreUint32(&o.ICM_CPU_H2X_CFG.Reg, volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetICM_CPU_H2X_CFG_CPU_ICM_H2X_POST_WR_EN() uint32 { + return volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetICM_CPU_H2X_CFG_CPU_ICM_H2X_CUT_THROUGH_EN(value uint32) { + volatile.StoreUint32(&o.ICM_CPU_H2X_CFG.Reg, volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetICM_CPU_H2X_CFG_CPU_ICM_H2X_CUT_THROUGH_EN() uint32 { + return (volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetICM_CPU_H2X_CFG_CPU_ICM_H2X_BRIDGE_BUSY(value uint32) { + volatile.StoreUint32(&o.ICM_CPU_H2X_CFG.Reg, volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetICM_CPU_H2X_CFG_CPU_ICM_H2X_BRIDGE_BUSY() uint32 { + return (volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg) & 0x4) >> 2 +} + +// HP_SYS.PERI1_APB_POSTW_EN: NA +func (o *HP_SYS_Type) SetPERI1_APB_POSTW_EN(value uint32) { + volatile.StoreUint32(&o.PERI1_APB_POSTW_EN.Reg, volatile.LoadUint32(&o.PERI1_APB_POSTW_EN.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetPERI1_APB_POSTW_EN() uint32 { + return volatile.LoadUint32(&o.PERI1_APB_POSTW_EN.Reg) & 0x1 +} + +// HP_SYS.BITSCRAMBLER_PERI_SEL: Bitscrambler Peri Sel +func (o *HP_SYS_Type) SetBITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_RX_SEL(value uint32) { + volatile.StoreUint32(&o.BITSCRAMBLER_PERI_SEL.Reg, volatile.LoadUint32(&o.BITSCRAMBLER_PERI_SEL.Reg)&^(0xf)|value) +} +func (o *HP_SYS_Type) GetBITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_RX_SEL() uint32 { + return volatile.LoadUint32(&o.BITSCRAMBLER_PERI_SEL.Reg) & 0xf +} +func (o *HP_SYS_Type) SetBITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_TX_SEL(value uint32) { + volatile.StoreUint32(&o.BITSCRAMBLER_PERI_SEL.Reg, volatile.LoadUint32(&o.BITSCRAMBLER_PERI_SEL.Reg)&^(0xf0)|value<<4) +} +func (o *HP_SYS_Type) GetBITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_TX_SEL() uint32 { + return (volatile.LoadUint32(&o.BITSCRAMBLER_PERI_SEL.Reg) & 0xf0) >> 4 +} + +// HP_SYS.APB_SYNC_POSTW_EN: N/A +func (o *HP_SYS_Type) SetAPB_SYNC_POSTW_EN_GMAC_APB_POSTW_EN(value uint32) { + volatile.StoreUint32(&o.APB_SYNC_POSTW_EN.Reg, volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetAPB_SYNC_POSTW_EN_GMAC_APB_POSTW_EN() uint32 { + return volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetAPB_SYNC_POSTW_EN_DSI_HOST_APB_POSTW_EN(value uint32) { + volatile.StoreUint32(&o.APB_SYNC_POSTW_EN.Reg, volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetAPB_SYNC_POSTW_EN_DSI_HOST_APB_POSTW_EN() uint32 { + return (volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetAPB_SYNC_POSTW_EN_CSI_HOST_APB_SYNC_POSTW_EN(value uint32) { + volatile.StoreUint32(&o.APB_SYNC_POSTW_EN.Reg, volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetAPB_SYNC_POSTW_EN_CSI_HOST_APB_SYNC_POSTW_EN() uint32 { + return (volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetAPB_SYNC_POSTW_EN_CSI_HOST_APB_ASYNC_POSTW_EN(value uint32) { + volatile.StoreUint32(&o.APB_SYNC_POSTW_EN.Reg, volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetAPB_SYNC_POSTW_EN_CSI_HOST_APB_ASYNC_POSTW_EN() uint32 { + return (volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg) & 0x8) >> 3 +} + +// HP_SYS.GDMA_CTRL: N/A +func (o *HP_SYS_Type) SetGDMA_CTRL_DEBUG_CH_NUM(value uint32) { + volatile.StoreUint32(&o.GDMA_CTRL.Reg, volatile.LoadUint32(&o.GDMA_CTRL.Reg)&^(0x3)|value) +} +func (o *HP_SYS_Type) GetGDMA_CTRL_DEBUG_CH_NUM() uint32 { + return volatile.LoadUint32(&o.GDMA_CTRL.Reg) & 0x3 +} + +// HP_SYS.GMAC_CTRL0: N/A +func (o *HP_SYS_Type) SetGMAC_CTRL0_PTP_PPS(value uint32) { + volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetGMAC_CTRL0_PTP_PPS() uint32 { + return volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetGMAC_CTRL0_SBD_FLOWCTRL(value uint32) { + volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetGMAC_CTRL0_SBD_FLOWCTRL() uint32 { + return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetGMAC_CTRL0_PHY_INTF_SEL(value uint32) { + volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x1c)|value<<2) +} +func (o *HP_SYS_Type) GetGMAC_CTRL0_PHY_INTF_SEL() uint32 { + return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x1c) >> 2 +} +func (o *HP_SYS_Type) SetGMAC_CTRL0_GMAC_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_Type) GetGMAC_CTRL0_GMAC_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_Type) SetGMAC_CTRL0_GMAC_RST_CLK_TX_N(value uint32) { + volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_Type) GetGMAC_CTRL0_GMAC_RST_CLK_TX_N() uint32 { + return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_Type) SetGMAC_CTRL0_GMAC_RST_CLK_RX_N(value uint32) { + volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_Type) GetGMAC_CTRL0_GMAC_RST_CLK_RX_N() uint32 { + return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x80) >> 7 +} + +// HP_SYS.GMAC_CTRL1: N/A +func (o *HP_SYS_Type) SetGMAC_CTRL1(value uint32) { + volatile.StoreUint32(&o.GMAC_CTRL1.Reg, value) +} +func (o *HP_SYS_Type) GetGMAC_CTRL1() uint32 { + return volatile.LoadUint32(&o.GMAC_CTRL1.Reg) +} + +// HP_SYS.GMAC_CTRL2: N/A +func (o *HP_SYS_Type) SetGMAC_CTRL2(value uint32) { + volatile.StoreUint32(&o.GMAC_CTRL2.Reg, value) +} +func (o *HP_SYS_Type) GetGMAC_CTRL2() uint32 { + return volatile.LoadUint32(&o.GMAC_CTRL2.Reg) +} + +// HP_SYS.VPU_CTRL: N/A +func (o *HP_SYS_Type) SetVPU_CTRL_PPA_LSLP_MEM_PD(value uint32) { + volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetVPU_CTRL_PPA_LSLP_MEM_PD() uint32 { + return volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetVPU_CTRL_JPEG_SDSLP_MEM_PD(value uint32) { + volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetVPU_CTRL_JPEG_SDSLP_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetVPU_CTRL_JPEG_LSLP_MEM_PD(value uint32) { + volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetVPU_CTRL_JPEG_LSLP_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetVPU_CTRL_JPEG_DSLP_MEM_PD(value uint32) { + volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetVPU_CTRL_JPEG_DSLP_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_Type) SetVPU_CTRL_DMA2D_LSLP_MEM_PD(value uint32) { + volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_Type) GetVPU_CTRL_DMA2D_LSLP_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x10) >> 4 +} + +// HP_SYS.USBOTG20_CTRL: N/A +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_PHY_TEST_DONE(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_PHY_TEST_DONE() uint32 { + return volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_USB_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x7ffe)|value<<1) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_USB_MEM_AUX_CTRL() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x7ffe) >> 1 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_SUSPENDM(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_SUSPENDM() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_SUSPEND_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_SUSPEND_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_RSTN(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_RSTN() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_RESET_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_RESET_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_PLL_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_PLL_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_PLL_EN(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_PLL_EN() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_SUSPENDM(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_SUSPENDM() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_PHY_TXBITSTUFF_EN(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_PHY_TXBITSTUFF_EN() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_PHY_REFCLK_MODE(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_PHY_REFCLK_MODE() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_PHY_BISTEN(value uint32) { + volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_PHY_BISTEN() uint32 { + return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x1000000) >> 24 +} + +// HP_SYS.TCM_ERR_RESP_CTRL: need_des +func (o *HP_SYS_Type) SetTCM_ERR_RESP_CTRL_TCM_ERR_RESP_EN(value uint32) { + volatile.StoreUint32(&o.TCM_ERR_RESP_CTRL.Reg, volatile.LoadUint32(&o.TCM_ERR_RESP_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetTCM_ERR_RESP_CTRL_TCM_ERR_RESP_EN() uint32 { + return volatile.LoadUint32(&o.TCM_ERR_RESP_CTRL.Reg) & 0x1 +} + +// HP_SYS.L2_MEM_REFRESH: NA +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFERSH_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFERSH_EN() uint32 { + return volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFERSH_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFERSH_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFERSH_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFERSH_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFERSH_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFERSH_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFERSH_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFERSH_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFERSH_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFERSH_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_REFERSH_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_REFERSH_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFRESH_DONE(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFRESH_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFRESH_DONE(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFRESH_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFRESH_DONE(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFRESH_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFRESH_DONE(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFRESH_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFRESH_DONE(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFRESH_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFRESH_DONE(value uint32) { + volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFRESH_DONE() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x1000) >> 12 +} + +// HP_SYS.TCM_INIT: NA +func (o *HP_SYS_Type) SetTCM_INIT_REG_TCM_INIT_EN(value uint32) { + volatile.StoreUint32(&o.TCM_INIT.Reg, volatile.LoadUint32(&o.TCM_INIT.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetTCM_INIT_REG_TCM_INIT_EN() uint32 { + return volatile.LoadUint32(&o.TCM_INIT.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetTCM_INIT_REG_TCM_INIT_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.TCM_INIT.Reg, volatile.LoadUint32(&o.TCM_INIT.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetTCM_INIT_REG_TCM_INIT_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.TCM_INIT.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetTCM_INIT_REG_TCM_INIT_DONE(value uint32) { + volatile.StoreUint32(&o.TCM_INIT.Reg, volatile.LoadUint32(&o.TCM_INIT.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetTCM_INIT_REG_TCM_INIT_DONE() uint32 { + return (volatile.LoadUint32(&o.TCM_INIT.Reg) & 0x4) >> 2 +} + +// HP_SYS.TCM_PARITY_CHECK_CTRL: need_des +func (o *HP_SYS_Type) SetTCM_PARITY_CHECK_CTRL_TCM_PARITY_CHECK_EN(value uint32) { + volatile.StoreUint32(&o.TCM_PARITY_CHECK_CTRL.Reg, volatile.LoadUint32(&o.TCM_PARITY_CHECK_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetTCM_PARITY_CHECK_CTRL_TCM_PARITY_CHECK_EN() uint32 { + return volatile.LoadUint32(&o.TCM_PARITY_CHECK_CTRL.Reg) & 0x1 +} + +// HP_SYS.DESIGN_FOR_VERIFICATION0: need_des +func (o *HP_SYS_Type) SetDESIGN_FOR_VERIFICATION0(value uint32) { + volatile.StoreUint32(&o.DESIGN_FOR_VERIFICATION0.Reg, value) +} +func (o *HP_SYS_Type) GetDESIGN_FOR_VERIFICATION0() uint32 { + return volatile.LoadUint32(&o.DESIGN_FOR_VERIFICATION0.Reg) +} + +// HP_SYS.DESIGN_FOR_VERIFICATION1: need_des +func (o *HP_SYS_Type) SetDESIGN_FOR_VERIFICATION1(value uint32) { + volatile.StoreUint32(&o.DESIGN_FOR_VERIFICATION1.Reg, value) +} +func (o *HP_SYS_Type) GetDESIGN_FOR_VERIFICATION1() uint32 { + return volatile.LoadUint32(&o.DESIGN_FOR_VERIFICATION1.Reg) +} + +// HP_SYS.PSRAM_FLASH_ADDR_INTERCHANGE: need_des +func (o *HP_SYS_Type) SetPSRAM_FLASH_ADDR_INTERCHANGE_CPU(value uint32) { + volatile.StoreUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg, volatile.LoadUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetPSRAM_FLASH_ADDR_INTERCHANGE_CPU() uint32 { + return volatile.LoadUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetPSRAM_FLASH_ADDR_INTERCHANGE_DMA(value uint32) { + volatile.StoreUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg, volatile.LoadUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetPSRAM_FLASH_ADDR_INTERCHANGE_DMA() uint32 { + return (volatile.LoadUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg) & 0x2) >> 1 +} + +// HP_SYS.AHB2AXI_BRESP_ERR_INT_RAW: NA +func (o *HP_SYS_Type) SetAHB2AXI_BRESP_ERR_INT_RAW_CPU_ICM_H2X_BRESP_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.AHB2AXI_BRESP_ERR_INT_RAW.Reg, volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_RAW.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetAHB2AXI_BRESP_ERR_INT_RAW_CPU_ICM_H2X_BRESP_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_RAW.Reg) & 0x1 +} + +// HP_SYS.AHB2AXI_BRESP_ERR_INT_ST: need_des +func (o *HP_SYS_Type) SetAHB2AXI_BRESP_ERR_INT_ST_CPU_ICM_H2X_BRESP_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.AHB2AXI_BRESP_ERR_INT_ST.Reg, volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_Type) GetAHB2AXI_BRESP_ERR_INT_ST_CPU_ICM_H2X_BRESP_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_ST.Reg) & 0x80000000) >> 31 +} + +// HP_SYS.AHB2AXI_BRESP_ERR_INT_ENA: need_des +func (o *HP_SYS_Type) SetAHB2AXI_BRESP_ERR_INT_ENA_CPU_ICM_H2X_BRESP_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.AHB2AXI_BRESP_ERR_INT_ENA.Reg, volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_Type) GetAHB2AXI_BRESP_ERR_INT_ENA_CPU_ICM_H2X_BRESP_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// HP_SYS.AHB2AXI_BRESP_ERR_INT_CLR: need_des +func (o *HP_SYS_Type) SetAHB2AXI_BRESP_ERR_INT_CLR_CPU_ICM_H2X_BRESP_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.AHB2AXI_BRESP_ERR_INT_CLR.Reg, volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_Type) GetAHB2AXI_BRESP_ERR_INT_CLR_CPU_ICM_H2X_BRESP_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// HP_SYS.L2_MEM_ERR_RESP_CTRL: need_des +func (o *HP_SYS_Type) SetL2_MEM_ERR_RESP_CTRL_L2_MEM_ERR_RESP_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_ERR_RESP_CTRL.Reg, volatile.LoadUint32(&o.L2_MEM_ERR_RESP_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_ERR_RESP_CTRL_L2_MEM_ERR_RESP_EN() uint32 { + return volatile.LoadUint32(&o.L2_MEM_ERR_RESP_CTRL.Reg) & 0x1 +} + +// HP_SYS.L2_MEM_AHB_BUFFER_CTRL: need_des +func (o *HP_SYS_Type) SetL2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_WRBUFFER_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg, volatile.LoadUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetL2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_WRBUFFER_EN() uint32 { + return volatile.LoadUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetL2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_RDBUFFER_EN(value uint32) { + volatile.StoreUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg, volatile.LoadUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetL2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_RDBUFFER_EN() uint32 { + return (volatile.LoadUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg) & 0x2) >> 1 +} + +// HP_SYS.CORE_DMACTIVE_LPCORE: need_des +func (o *HP_SYS_Type) SetCORE_DMACTIVE_LPCORE(value uint32) { + volatile.StoreUint32(&o.CORE_DMACTIVE_LPCORE.Reg, volatile.LoadUint32(&o.CORE_DMACTIVE_LPCORE.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_DMACTIVE_LPCORE() uint32 { + return volatile.LoadUint32(&o.CORE_DMACTIVE_LPCORE.Reg) & 0x1 +} + +// HP_SYS.CORE_ERR_RESP_DIS: need_des +func (o *HP_SYS_Type) SetCORE_ERR_RESP_DIS(value uint32) { + volatile.StoreUint32(&o.CORE_ERR_RESP_DIS.Reg, volatile.LoadUint32(&o.CORE_ERR_RESP_DIS.Reg)&^(0x7)|value) +} +func (o *HP_SYS_Type) GetCORE_ERR_RESP_DIS() uint32 { + return volatile.LoadUint32(&o.CORE_ERR_RESP_DIS.Reg) & 0x7 +} + +// HP_SYS.CORE_TIMEOUT_INT_RAW: Hp core bus timeout interrupt raw register +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE0_AHB_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE0_AHB_TIMEOUT_INT_RAW() uint32 { + return volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE1_AHB_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE1_AHB_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE0_IBUS_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE0_IBUS_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE1_IBUS_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE1_IBUS_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE0_DBUS_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE0_DBUS_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE1_DBUS_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE1_DBUS_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x20) >> 5 +} + +// HP_SYS.CORE_TIMEOUT_INT_ST: masked interrupt register +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE0_AHB_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE0_AHB_TIMEOUT_INT_ST() uint32 { + return volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE1_AHB_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE1_AHB_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE0_IBUS_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE0_IBUS_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE1_IBUS_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE1_IBUS_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE0_DBUS_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE0_DBUS_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE1_DBUS_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE1_DBUS_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x20) >> 5 +} + +// HP_SYS.CORE_TIMEOUT_INT_ENA: masked interrupt register +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE0_AHB_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE0_AHB_TIMEOUT_INT_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE1_AHB_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE1_AHB_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE0_IBUS_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE0_IBUS_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE1_IBUS_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE1_IBUS_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE0_DBUS_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE0_DBUS_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE1_DBUS_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE1_DBUS_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x20) >> 5 +} + +// HP_SYS.CORE_TIMEOUT_INT_CLR: interrupt clear register +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE0_AHB_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE0_AHB_TIMEOUT_INT_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE1_AHB_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE1_AHB_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE0_IBUS_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE0_IBUS_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE1_IBUS_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE1_IBUS_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE0_DBUS_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE0_DBUS_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE1_DBUS_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE1_DBUS_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x20) >> 5 +} + +// HP_SYS.GPIO_O_HYS_CTRL0: NA +func (o *HP_SYS_Type) SetGPIO_O_HYS_CTRL0(value uint32) { + volatile.StoreUint32(&o.GPIO_O_HYS_CTRL0.Reg, value) +} +func (o *HP_SYS_Type) GetGPIO_O_HYS_CTRL0() uint32 { + return volatile.LoadUint32(&o.GPIO_O_HYS_CTRL0.Reg) +} + +// HP_SYS.GPIO_O_HYS_CTRL1: NA +func (o *HP_SYS_Type) SetGPIO_O_HYS_CTRL1_REG_GPIO_0_HYS_HIGH(value uint32) { + volatile.StoreUint32(&o.GPIO_O_HYS_CTRL1.Reg, volatile.LoadUint32(&o.GPIO_O_HYS_CTRL1.Reg)&^(0x1ff)|value) +} +func (o *HP_SYS_Type) GetGPIO_O_HYS_CTRL1_REG_GPIO_0_HYS_HIGH() uint32 { + return volatile.LoadUint32(&o.GPIO_O_HYS_CTRL1.Reg) & 0x1ff +} + +// HP_SYS.RSA_PD_CTRL: rsa pd ctrl register +func (o *HP_SYS_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetRSA_PD_CTRL_RSA_MEM_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetRSA_PD_CTRL_RSA_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x4) >> 2 +} + +// HP_SYS.ECC_PD_CTRL: ecc pd ctrl register +func (o *HP_SYS_Type) SetECC_PD_CTRL_ECC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetECC_PD_CTRL_ECC_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetECC_PD_CTRL_ECC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetECC_PD_CTRL_ECC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetECC_PD_CTRL_ECC_MEM_PD(value uint32) { + volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetECC_PD_CTRL_ECC_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x4) >> 2 +} + +// HP_SYS.RNG_CFG: rng cfg register +func (o *HP_SYS_Type) SetRNG_CFG_RNG_SAMPLE_ENABLE(value uint32) { + volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetRNG_CFG_RNG_SAMPLE_ENABLE() uint32 { + return volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetRNG_CFG_RNG_CHAIN_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_Type) GetRNG_CFG_RNG_CHAIN_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_Type) SetRNG_CFG_RNG_SAMPLE_CNT(value uint32) { + volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0xff000000)|value<<24) +} +func (o *HP_SYS_Type) GetRNG_CFG_RNG_SAMPLE_CNT() uint32 { + return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0xff000000) >> 24 +} + +// HP_SYS.UART_PD_CTRL: ecc pd ctrl register +func (o *HP_SYS_Type) SetUART_PD_CTRL_UART_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.UART_PD_CTRL.Reg, volatile.LoadUint32(&o.UART_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetUART_PD_CTRL_UART_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.UART_PD_CTRL.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetUART_PD_CTRL_UART_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.UART_PD_CTRL.Reg, volatile.LoadUint32(&o.UART_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetUART_PD_CTRL_UART_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.UART_PD_CTRL.Reg) & 0x2) >> 1 +} + +// HP_SYS.PERI_MEM_CLK_FORCE_ON: hp peri mem clk force on regpster +func (o *HP_SYS_Type) SetPERI_MEM_CLK_FORCE_ON_RMT_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg)&^(0x1)|value) +} +func (o *HP_SYS_Type) GetPERI_MEM_CLK_FORCE_ON_RMT_MEM_CLK_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg) & 0x1 +} +func (o *HP_SYS_Type) SetPERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_Type) GetPERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_Type) SetPERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_Type) GetPERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_Type) SetPERI_MEM_CLK_FORCE_ON_GDMA_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_Type) GetPERI_MEM_CLK_FORCE_ON_GDMA_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg) & 0x8) >> 3 +} + +// HP_SYS_CLKRST Peripheral +type HP_SYS_CLKRST_Type struct { + CLK_EN0 volatile.Register32 // 0x0 + ROOT_CLK_CTRL0 volatile.Register32 // 0x4 + ROOT_CLK_CTRL1 volatile.Register32 // 0x8 + ROOT_CLK_CTRL2 volatile.Register32 // 0xC + ROOT_CLK_CTRL3 volatile.Register32 // 0x10 + SOC_CLK_CTRL0 volatile.Register32 // 0x14 + SOC_CLK_CTRL1 volatile.Register32 // 0x18 + SOC_CLK_CTRL2 volatile.Register32 // 0x1C + SOC_CLK_CTRL3 volatile.Register32 // 0x20 + REF_CLK_CTRL0 volatile.Register32 // 0x24 + REF_CLK_CTRL1 volatile.Register32 // 0x28 + REF_CLK_CTRL2 volatile.Register32 // 0x2C + PERI_CLK_CTRL00 volatile.Register32 // 0x30 + PERI_CLK_CTRL01 volatile.Register32 // 0x34 + PERI_CLK_CTRL02 volatile.Register32 // 0x38 + PERI_CLK_CTRL03 volatile.Register32 // 0x3C + PERI_CLK_CTRL10 volatile.Register32 // 0x40 + PERI_CLK_CTRL11 volatile.Register32 // 0x44 + PERI_CLK_CTRL12 volatile.Register32 // 0x48 + PERI_CLK_CTRL13 volatile.Register32 // 0x4C + PERI_CLK_CTRL14 volatile.Register32 // 0x50 + PERI_CLK_CTRL15 volatile.Register32 // 0x54 + PERI_CLK_CTRL16 volatile.Register32 // 0x58 + PERI_CLK_CTRL17 volatile.Register32 // 0x5C + PERI_CLK_CTRL18 volatile.Register32 // 0x60 + PERI_CLK_CTRL19 volatile.Register32 // 0x64 + PERI_CLK_CTRL110 volatile.Register32 // 0x68 + PERI_CLK_CTRL111 volatile.Register32 // 0x6C + PERI_CLK_CTRL112 volatile.Register32 // 0x70 + PERI_CLK_CTRL113 volatile.Register32 // 0x74 + PERI_CLK_CTRL114 volatile.Register32 // 0x78 + PERI_CLK_CTRL115 volatile.Register32 // 0x7C + PERI_CLK_CTRL116 volatile.Register32 // 0x80 + PERI_CLK_CTRL117 volatile.Register32 // 0x84 + PERI_CLK_CTRL118 volatile.Register32 // 0x88 + PERI_CLK_CTRL119 volatile.Register32 // 0x8C + PERI_CLK_CTRL120 volatile.Register32 // 0x90 + PERI_CLK_CTRL20 volatile.Register32 // 0x94 + PERI_CLK_CTRL21 volatile.Register32 // 0x98 + PERI_CLK_CTRL22 volatile.Register32 // 0x9C + PERI_CLK_CTRL23 volatile.Register32 // 0xA0 + PERI_CLK_CTRL24 volatile.Register32 // 0xA4 + PERI_CLK_CTRL25 volatile.Register32 // 0xA8 + PERI_CLK_CTRL26 volatile.Register32 // 0xAC + PERI_CLK_CTRL27 volatile.Register32 // 0xB0 + CLK_FORCE_ON_CTRL0 volatile.Register32 // 0xB4 + DPA_CTRL0 volatile.Register32 // 0xB8 + ANA_PLL_CTRL0 volatile.Register32 // 0xBC + HP_RST_EN0 volatile.Register32 // 0xC0 + HP_RST_EN1 volatile.Register32 // 0xC4 + HP_RST_EN2 volatile.Register32 // 0xC8 + HP_FORCE_NORST0 volatile.Register32 // 0xCC + HP_FORCE_NORST1 volatile.Register32 // 0xD0 + HPWDT_CORE0_RST_CTRL0 volatile.Register32 // 0xD4 + HPWDT_CORE1_RST_CTRL0 volatile.Register32 // 0xD8 + CPU_SRC_FREQ0 volatile.Register32 // 0xDC + CPU_CLK_STATUS0 volatile.Register32 // 0xE0 + DBG_CLK_CTRL0 volatile.Register32 // 0xE4 + DBG_CLK_CTRL1 volatile.Register32 // 0xE8 + HPCORE_WDT_RESET_SOURCE0 volatile.Register32 // 0xEC +} + +// HP_SYS_CLKRST.CLK_EN0: Reserved +func (o *HP_SYS_CLKRST_Type) SetCLK_EN0_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN0.Reg, volatile.LoadUint32(&o.CLK_EN0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_EN0_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN0.Reg) & 0x1 +} + +// HP_SYS_CLKRST.ROOT_CLK_CTRL0: Reserved +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_CPUICM_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0xf)|value) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_CPUICM_DELAY_NUM() uint32 { + return volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0xf +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_SOC_CLK_DIV_UPDATE(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_SOC_CLK_DIV_UPDATE() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0x1fe0)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0x1fe0) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0x1fe000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0x1fe000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0x1fe00000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0x1fe00000) >> 21 +} + +// HP_SYS_CLKRST.ROOT_CLK_CTRL1: Reserved +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL1.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL1.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL1.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL1_REG_SYS_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL1.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg)&^(0xff000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL1_REG_SYS_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg) & 0xff000000) >> 24 +} + +// HP_SYS_CLKRST.ROOT_CLK_CTRL2: Reserved +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL2_REG_SYS_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL2.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL2_REG_SYS_CLK_DIV_NUMERATOR() uint32 { + return volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL2_REG_SYS_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL2.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL2_REG_SYS_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL2.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL2.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg)&^(0xff000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg) & 0xff000000) >> 24 +} + +// HP_SYS_CLKRST.ROOT_CLK_CTRL3: Reserved +func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL3_REG_APB_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.ROOT_CLK_CTRL3.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL3.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL3_REG_APB_CLK_DIV_DENOMINATOR() uint32 { + return volatile.LoadUint32(&o.ROOT_CLK_CTRL3.Reg) & 0xff +} + +// HP_SYS_CLKRST.SOC_CLK_CTRL0: Reserved +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_CORE0_CLIC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_CORE0_CLIC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_CORE1_CLIC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_CORE1_CLIC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_MISC_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_MISC_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_CORE0_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_CORE0_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_CORE1_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_CORE1_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_TCM_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_TCM_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_BUSMON_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_BUSMON_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_D_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_D_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_I0_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_I0_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_I1_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_I1_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_TRACE_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_TRACE_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_ICM_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_ICM_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x1000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_GDMA_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_GDMA_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_VPU_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_VPU_CPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_D_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_D_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_I0_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_I0_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_I1_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_I1_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2CACHE_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2CACHE_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2MEM_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2MEM_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2MEMMON_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2MEMMON_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_ICM_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_ICM_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_MISC_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_MISC_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_TRACE_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_TRACE_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2CACHE_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2CACHE_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2MEM_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2MEM_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x4000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2MEMMON_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2MEMMON_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_TCMMON_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_TCMMON_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_ICM_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_ICM_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x20000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_FLASH_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x40000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_FLASH_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x40000000) >> 30 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_PSRAM_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_PSRAM_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x80000000) >> 31 +} + +// HP_SYS_CLKRST.SOC_CLK_CTRL1: Reserved +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_GPSPI2_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_GPSPI2_SYS_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_GPSPI3_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_GPSPI3_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_REGDMA_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_REGDMA_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_AHB_PDMA_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_AHB_PDMA_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_AXI_PDMA_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_AXI_PDMA_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_GDMA_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_GDMA_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_DMA2D_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_DMA2D_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_VPU_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_VPU_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_JPEG_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_JPEG_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_PPA_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_PPA_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_CSI_BRG_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_CSI_BRG_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_CSI_HOST_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_CSI_HOST_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_DSI_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_DSI_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x1000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_EMAC_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_EMAC_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_SDMMC_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_SDMMC_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_USB_OTG11_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_USB_OTG11_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_USB_OTG20_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_USB_OTG20_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UHCI_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UHCI_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART0_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART0_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART1_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART1_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART2_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART2_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART3_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART3_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART4_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART4_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_PARLIO_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_PARLIO_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_ETM_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_ETM_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_PVT_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_PVT_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_CRYPTO_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_CRYPTO_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x4000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_KEY_MANAGER_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_KEY_MANAGER_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_BITSRAMBLER_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_BITSRAMBLER_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_BITSRAMBLER_RX_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_BITSRAMBLER_RX_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x20000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_BITSRAMBLER_TX_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_BITSRAMBLER_TX_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x40000000) >> 30 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_H264_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_H264_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x80000000) >> 31 +} + +// HP_SYS_CLKRST.SOC_CLK_CTRL2: Reserved +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_RMT_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_RMT_SYS_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_HP_CLKRST_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_HP_CLKRST_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_SYSREG_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_SYSREG_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_ICM_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_ICM_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_INTRMTX_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_INTRMTX_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_ADC_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_ADC_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UHCI_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UHCI_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART0_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART0_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART1_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART1_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART2_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART2_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART3_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART3_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART4_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART4_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2C0_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2C0_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x1000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2C1_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2C1_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2S0_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2S0_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2S1_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2S1_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2S2_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2S2_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I3C_MST_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I3C_MST_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I3C_SLV_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I3C_SLV_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_GPSPI2_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_GPSPI2_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_GPSPI3_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_GPSPI3_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TIMERGRP0_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TIMERGRP0_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TIMERGRP1_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TIMERGRP1_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_SYSTIMER_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_SYSTIMER_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TWAI0_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TWAI0_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TWAI1_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TWAI1_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TWAI2_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TWAI2_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x4000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_MCPWM0_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_MCPWM0_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_MCPWM1_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_MCPWM1_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_USB_DEVICE_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_USB_DEVICE_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x20000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_PCNT_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x40000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_PCNT_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x40000000) >> 30 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_PARLIO_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_PARLIO_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x80000000) >> 31 +} + +// HP_SYS_CLKRST.SOC_CLK_CTRL3: Reserved +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL3_REG_LEDC_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL3.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL3_REG_LEDC_APB_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL3_REG_LCDCAM_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL3.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL3_REG_LCDCAM_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL3_REG_ETM_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL3.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL3_REG_ETM_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL3_REG_IOMUX_APB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SOC_CLK_CTRL3.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL3_REG_IOMUX_APB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg) & 0x8) >> 3 +} + +// HP_SYS_CLKRST.REF_CLK_CTRL0: Reserved +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL0_REG_REF_50M_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL0.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL0_REG_REF_50M_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL0_REG_REF_25M_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL0.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL0_REG_REF_25M_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL0_REG_REF_240M_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL0.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL0_REG_REF_240M_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL0_REG_REF_160M_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL0.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg)&^(0xff000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL0_REG_REF_160M_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg) & 0xff000000) >> 24 +} + +// HP_SYS_CLKRST.REF_CLK_CTRL1: Reserved +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_120M_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_120M_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_80M_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_80M_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_20M_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_20M_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_400M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_400M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_200M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_200M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_100M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_100M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x4000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_50M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_50M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_25M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_25M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_480M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_480M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x20000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_240M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_240M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x40000000) >> 30 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_240M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_240M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x80000000) >> 31 +} + +// HP_SYS_CLKRST.REF_CLK_CTRL2: Reserved +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_REF_160M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_REF_160M_CLK_EN() uint32 { + return volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_160M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_160M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_REF_120M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_REF_120M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_120M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_120M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_REF_80M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_REF_80M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_80M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_80M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_60M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_60M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_48M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_48M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_REF_20M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_REF_20M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_20M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_20M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x200) >> 9 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL00: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_FLASH_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x3)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_FLASH_CLK_SRC_SEL() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x3 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_FLASH_PLL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_FLASH_PLL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_FLASH_CORE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_FLASH_CORE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_FLASH_CORE_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0xff0)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_FLASH_CORE_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0xff0) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PSRAM_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x3000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PSRAM_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x3000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PSRAM_PLL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PSRAM_PLL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PAD_EMAC_REF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PAD_EMAC_REF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_EMAC_RMII_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x6000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_EMAC_RMII_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x6000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_EMAC_RMII_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_EMAC_RMII_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_EMAC_RX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_EMAC_RX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_EMAC_RX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_EMAC_RX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x20000000) >> 29 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL01: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_RX_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_RX_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x3fc00)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x3fc00) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_UNUSED0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_UNUSED0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_UNUSED1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_UNUSED1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_SDIO_HS_MODE(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_SDIO_HS_MODE() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_SDIO_LS_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_SDIO_LS_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_SDIO_LS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_SDIO_LS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x1000000) >> 24 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL02: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_L(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x1e00)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_L() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x1e00) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_H(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x1e000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_H() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x1e000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_N(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x1e0000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_N() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x1e0000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EDGE_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x600000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x600000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EDGE_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x1800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x1800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EDGE_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x6000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x6000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x20000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_MIPI_DSI_DPHY_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0xc0000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_MIPI_DSI_DPHY_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0xc0000000) >> 30 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL03: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_CFG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_CFG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0xc)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0xc) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CFG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CFG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x60)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x60) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0xff00) >> 8 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL10: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_SRC_SEL() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x3fc)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x3fc) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x3fc00)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x3fc00) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x3fc0000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x3fc0000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C1_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C1_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x4000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x8000000) >> 27 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL11: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2S0_RX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2S0_RX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2S0_RX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0x6000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2S0_RX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0x6000000) >> 25 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL12: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_N(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL12.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_N() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_X(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL12.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg)&^(0x1ff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_X() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg) & 0x1ff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_Y(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL12.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg)&^(0x3fe0000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg) & 0x3fe0000) >> 17 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL13: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_RX_DIV_Z(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x1ff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_RX_DIV_Z() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x1ff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_RX_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_RX_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_TX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_TX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_TX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x1800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_TX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x1800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_TX_DIV_N(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x1fe000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_TX_DIV_N() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x1fe000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_TX_DIV_X(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x3fe00000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_TX_DIV_X() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x3fe00000) >> 21 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL14: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_Y(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x1ff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_Y() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x1ff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_Z(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x3fe00)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_Z() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x3fe00) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S0_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S0_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S1_RX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S1_RX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S1_RX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x600000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S1_RX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x600000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S1_RX_DIV_N(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x7f800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S1_RX_DIV_N() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x7f800000) >> 23 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL15: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_X(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x1ff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_X() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x1ff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_Y(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x3fe00)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x3fe00) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_Z(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x7fc0000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_Z() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x7fc0000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_TX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_TX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_TX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x60000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_TX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x60000000) >> 29 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL16: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_N(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL16.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_N() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_X(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL16.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg)&^(0x1ff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_X() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg) & 0x1ff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_Y(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL16.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg)&^(0x3fe0000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg) & 0x3fe0000) >> 17 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL17: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S1_TX_DIV_Z(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x1ff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S1_TX_DIV_Z() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x1ff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S1_TX_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S1_TX_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S1_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S1_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S2_RX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S2_RX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S2_RX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x3000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S2_RX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x3000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S2_RX_DIV_N(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x3fc000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S2_RX_DIV_N() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x3fc000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S2_RX_DIV_X(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x7fc00000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S2_RX_DIV_X() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x7fc00000) >> 22 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL18: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_Y(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x1ff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_Y() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x1ff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_Z(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x3fe00)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_Z() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x3fe00) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_TX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_TX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_TX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x300000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_TX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x300000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_TX_DIV_N(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x3fc00000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_TX_DIV_N() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x3fc00000) >> 22 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL19: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_X(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x1ff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_X() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x1ff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_Y(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x3fe00)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x3fe00) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_Z(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x7fc0000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_Z() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x7fc0000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_LCD_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x60000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_LCD_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x60000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_LCD_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_LCD_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x80000000) >> 31 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL110: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_UART0_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0x3000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_UART0_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0x3000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_UART0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_UART0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0x4000000) >> 26 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL111: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART1_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0x3000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART1_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0x3000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0x4000000) >> 26 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL112: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART2_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0x3000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART2_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0x3000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0x4000000) >> 26 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL113: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART3_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0x3000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART3_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0x3000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0x4000000) >> 26 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL114: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART4_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0x3000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART4_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0x3000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART4_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART4_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0x4000000) >> 26 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL115: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI0_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI0_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI1_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI1_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x4000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI2_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI2_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x20000000) >> 29 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL116: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0x7)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_CLK_SRC_SEL() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0x7 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0xff0)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0xff0) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0xff000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0xff000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI3_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0xe00000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI3_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0xe00000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI3_HS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI3_HS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0x1000000) >> 24 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL117: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_GPSPI3_HS_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_GPSPI3_HS_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0x60000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0x60000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0xff00000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0xff00000) >> 20 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL118: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_NUMERATOR() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0x30000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0x30000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0x7f80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0x7f80000) >> 19 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL119: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_NUMERATOR() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_I3C_MST_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x30000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_I3C_MST_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x30000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_I3C_MST_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_I3C_MST_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_I3C_MST_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x7f80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_I3C_MST_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x7f80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_CAM_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x18000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_CAM_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x18000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_CAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_CAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x20000000) >> 29 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL120: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL120.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL120.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL120.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg) & 0xff0000) >> 16 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL20: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM0_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x3)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM0_CLK_SRC_SEL() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x3 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM0_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x7f8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM0_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x7f8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM1_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x1800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM1_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x1800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM1_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x3fc000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM1_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x3fc000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_T0_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0xc00000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_T0_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0xc00000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_T0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_T0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_T1_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x6000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_T1_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x6000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_T1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_T1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_WDT_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x30000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_WDT_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x30000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_WDT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x40000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_WDT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x40000000) >> 30 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_TGRT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_TGRT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x80000000) >> 31 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL21: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0xf)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_SRC_SEL() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0xf +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0xffff0)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0xffff0) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_T0_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x300000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_T0_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x300000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_T0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_T0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_T1_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x1800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_T1_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x1800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_T1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_T1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_WDT_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0xc000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_WDT_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0xc000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_WDT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_WDT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_SYSTIMER_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_SYSTIMER_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x20000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_SYSTIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x40000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_SYSTIMER_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x40000000) >> 30 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL22: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_LEDC_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x3)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_LEDC_CLK_SRC_SEL() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x3 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_LEDC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_LEDC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x18)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x18) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x3fc0)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x3fc0) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x3fc000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x3fc000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x3fc00000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x3fc00000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_ADC_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0xc0000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_ADC_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0xc0000000) >> 30 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL23: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL23_REG_ADC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL23.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL23_REG_ADC_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL23.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg)&^(0x1fe)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg) & 0x1fe) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUMERATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL23.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg)&^(0x1fe00)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUMERATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg) & 0x1fe00) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_DENOMINATOR(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL23.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg)&^(0x1fe0000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_DENOMINATOR() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg) & 0x1fe0000) >> 17 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL24: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL24_REG_ADC_SAR1_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL24.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL24_REG_ADC_SAR1_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL24_REG_ADC_SAR2_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL24.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL24_REG_ADC_SAR2_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL24_REG_PVT_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL24.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL24_REG_PVT_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL24_REG_PVT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL24.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL24_REG_PVT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg) & 0x1000000) >> 24 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL25: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP4_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP4_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x3000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x3000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_AES_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_AES_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_DS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_DS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_ECC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_ECC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_HMAC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_HMAC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_RSA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_RSA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_SEC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_SEC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_SHA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_SHA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_ECDSA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_ECDSA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_KM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_KM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_ISP_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x1800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_ISP_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x1800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_ISP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_ISP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x2000000) >> 25 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL26: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_ISP_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_ISP_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_IOMUX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_IOMUX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_IOMUX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_IOMUX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_IOMUX_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x3fc00)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_IOMUX_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x3fc00) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_H264_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_H264_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_H264_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_H264_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_H264_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0xff00000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_H264_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0xff00000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_PADBIST_RX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_PADBIST_RX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_PADBIST_RX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_PADBIST_RX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x20000000) >> 29 +} + +// HP_SYS_CLKRST.PERI_CLK_CTRL27: Reserved +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL27_REG_PADBIST_RX_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL27.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL27_REG_PADBIST_RX_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL27.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL27.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.PERI_CLK_CTRL27.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg)&^(0x3fc00)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg) & 0x3fc00) >> 10 +} + +// HP_SYS_CLKRST.CLK_FORCE_ON_CTRL0: Reserved +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_CPUICM_GATED_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_CPUICM_GATED_CLK_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_TCM_CPU_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_TCM_CPU_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_BUSMON_CPU_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_BUSMON_CPU_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_CPU_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_CPU_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_D_CPU_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_D_CPU_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_CPU_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_CPU_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_CPU_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_CPU_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_TRACE_CPU_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_TRACE_CPU_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_TRACE_SYS_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_TRACE_SYS_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_D_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_D_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x1000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L2CACHE_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L2CACHE_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L2MEM_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L2MEM_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_SAR1_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_SAR1_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_SAR2_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_SAR2_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_GMAC_TX_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_GMAC_TX_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x20000) >> 17 +} + +// HP_SYS_CLKRST.DPA_CTRL0: Reserved +func (o *HP_SYS_CLKRST_Type) SetDPA_CTRL0_REG_SEC_DPA_LEVEL(value uint32) { + volatile.StoreUint32(&o.DPA_CTRL0.Reg, volatile.LoadUint32(&o.DPA_CTRL0.Reg)&^(0x3)|value) +} +func (o *HP_SYS_CLKRST_Type) GetDPA_CTRL0_REG_SEC_DPA_LEVEL() uint32 { + return volatile.LoadUint32(&o.DPA_CTRL0.Reg) & 0x3 +} +func (o *HP_SYS_CLKRST_Type) SetDPA_CTRL0_REG_SEC_DPA_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.DPA_CTRL0.Reg, volatile.LoadUint32(&o.DPA_CTRL0.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetDPA_CTRL0_REG_SEC_DPA_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.DPA_CTRL0.Reg) & 0x4) >> 2 +} + +// HP_SYS_CLKRST.ANA_PLL_CTRL0: Reserved +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_PLLA_CAL_END(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_PLLA_CAL_END() uint32 { + return volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_PLLA_CAL_STOP(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_PLLA_CAL_STOP() uint32 { + return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_CPU_PLL_CAL_END(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_CPU_PLL_CAL_END() uint32 { + return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_CPU_PLL_CAL_STOP(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_CPU_PLL_CAL_STOP() uint32 { + return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_SDIO_PLL_CAL_END(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_SDIO_PLL_CAL_END() uint32 { + return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_SDIO_PLL_CAL_STOP(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_SDIO_PLL_CAL_STOP() uint32 { + return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_SYS_PLL_CAL_END(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_SYS_PLL_CAL_END() uint32 { + return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_SYS_PLL_CAL_STOP(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_SYS_PLL_CAL_STOP() uint32 { + return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_MSPI_CAL_END(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_MSPI_CAL_END() uint32 { + return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_MSPI_CAL_STOP(value uint32) { + volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_MSPI_CAL_STOP() uint32 { + return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x200) >> 9 +} + +// HP_SYS_CLKRST.HP_RST_EN0: Reserved +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORECTRL(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORECTRL() uint32 { + return volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_TOP(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_TOP() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP1(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP1() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP2(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP2() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP3(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP3() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP4(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP4() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_REGDMA(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_REGDMA() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORE0_GLOBAL(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORE0_GLOBAL() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORE1_GLOBAL(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORE1_GLOBAL() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORETRACE0(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORETRACE0() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORETRACE1(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORETRACE1() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_HP_TCM(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_HP_TCM() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_HP_CACHE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_HP_CACHE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x1000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L1_I0_CACHE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L1_I0_CACHE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L1_I1_CACHE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L1_I1_CACHE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L1_D_CACHE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L1_D_CACHE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L2_CACHE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L2_CACHE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L2_MEM(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L2_MEM() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L2MEMMON(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L2MEMMON() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_TCMMON(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_TCMMON() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_GDMA(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_GDMA() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_MSPI_AXI(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_MSPI_AXI() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_DUAL_MSPI_AXI(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_DUAL_MSPI_AXI() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_MSPI_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_MSPI_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_DUAL_MSPI_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_DUAL_MSPI_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_DSI_BRG(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_DSI_BRG() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x4000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CSI_HOST(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CSI_HOST() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CSI_BRG(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CSI_BRG() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_ISP(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_ISP() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x20000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_JPEG(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_JPEG() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x40000000) >> 30 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_DMA2D(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_DMA2D() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x80000000) >> 31 +} + +// HP_SYS_CLKRST.HP_RST_EN1: Reserved +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PPA(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PPA() uint32 { + return volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_AHB_PDMA(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_AHB_PDMA() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_AXI_PDMA(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_AXI_PDMA() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_IOMUX(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_IOMUX() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PADBIST(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PADBIST() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_STIMER(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_STIMER() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_TIMERGRP0(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_TIMERGRP0() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_TIMERGRP1(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_TIMERGRP1() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART0_CORE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART0_CORE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART1_CORE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART1_CORE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART2_CORE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART2_CORE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART3_CORE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART3_CORE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART4_CORE(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART4_CORE() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x1000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART0_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART0_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART1_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART1_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART2_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART2_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART3_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART3_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART4_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART4_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UHCI(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UHCI() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_I3CMST(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_I3CMST() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_I3CSLV(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_I3CSLV() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_I2C1(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_I2C1() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_I2C0(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_I2C0() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_RMT(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_RMT() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PWM0(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PWM0() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PWM1(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PWM1() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_CAN0(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_CAN0() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x4000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_CAN1(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_CAN1() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_CAN2(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_CAN2() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_LEDC(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_LEDC() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x20000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PCNT(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x40000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PCNT() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x40000000) >> 30 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_ETM(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_ETM() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x80000000) >> 31 +} + +// HP_SYS_CLKRST.HP_RST_EN2: Reserved +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_INTRMTX(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_INTRMTX() uint32 { + return volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_PARLIO(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_PARLIO() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_PARLIO_RX(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_PARLIO_RX() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_PARLIO_TX(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_PARLIO_TX() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_I2S0_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_I2S0_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_I2S1_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_I2S1_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_I2S2_APB(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_I2S2_APB() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_SPI2(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_SPI2() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_SPI3(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_SPI3() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_LCDCAM(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_LCDCAM() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_ADC(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_ADC() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_BITSRAMBLER(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_BITSRAMBLER() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_BITSRAMBLER_RX(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_BITSRAMBLER_RX() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x1000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_BITSRAMBLER_TX(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_BITSRAMBLER_TX() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_CRYPTO(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_CRYPTO() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_SEC(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_SEC() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_AES(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_AES() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_DS(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_DS() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_SHA(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_SHA() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_HMAC(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_HMAC() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_ECDSA(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_ECDSA() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_RSA(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_RSA() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_ECC(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_ECC() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_KM(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_KM() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_H264(value uint32) { + volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_H264() uint32 { + return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x1000000) >> 24 +} + +// HP_SYS_CLKRST.HP_FORCE_NORST0: Reserved +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CORE0(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CORE0() uint32 { + return volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CORE1(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CORE1() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE0(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE0() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE1(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE1() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_L2MEMMON(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_L2MEMMON() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_TCMMON(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_TCMMON() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_GDMA(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_GDMA() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_MSPI_AXI(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_MSPI_AXI() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_AXI(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_AXI() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_MSPI_APB(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_MSPI_APB() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_APB(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_APB() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_DSI_BRG(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_DSI_BRG() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CSI_HOST(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CSI_HOST() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x1000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CSI_BRG(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CSI_BRG() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_ISP(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_ISP() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_JPEG(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_JPEG() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_DMA2D(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_DMA2D() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_PPA(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_PPA() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_AHB_PDMA(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_AHB_PDMA() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_AXI_PDMA(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_AXI_PDMA() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_IOMUX(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_IOMUX() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_PADBIST(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_PADBIST() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_STIMER(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_STIMER() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP0(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP0() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP1(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP1() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART0(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART0() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART1(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART1() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x4000000) >> 26 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART2(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x8000000)|value<<27) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART2() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x8000000) >> 27 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART3(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x10000000)|value<<28) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART3() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x10000000) >> 28 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART4(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x20000000)|value<<29) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART4() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x20000000) >> 29 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UHCI(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x40000000)|value<<30) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UHCI() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x40000000) >> 30 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_I3CMST(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x80000000)|value<<31) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_I3CMST() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x80000000) >> 31 +} + +// HP_SYS_CLKRST.HP_FORCE_NORST1: Reserved +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I3CSLV(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I3CSLV() uint32 { + return volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2C1(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2C1() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2C0(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2C0() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_RMT(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_RMT() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PWM0(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x10)|value<<4) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PWM0() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x10) >> 4 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PWM1(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x20)|value<<5) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PWM1() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x20) >> 5 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_CAN0(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x40)|value<<6) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_CAN0() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x40) >> 6 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_CAN1(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x80)|value<<7) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_CAN1() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x80) >> 7 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_CAN2(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x100)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_CAN2() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x100) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_LEDC(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x200)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_LEDC() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x200) >> 9 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PCNT(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x400)|value<<10) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PCNT() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x400) >> 10 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_ETM(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_ETM() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_INTRMTX(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x1000)|value<<12) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_INTRMTX() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x1000) >> 12 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x2000)|value<<13) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x2000) >> 13 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_RX(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x4000)|value<<14) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_RX() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x4000) >> 14 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_TX(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x8000)|value<<15) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_TX() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x8000) >> 15 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2S0(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2S0() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2S1(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2S1() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2S2(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2S2() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x40000) >> 18 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_SPI2(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_SPI2() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x80000) >> 19 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_SPI3(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x100000)|value<<20) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_SPI3() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x100000) >> 20 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_LCDCAM(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x200000)|value<<21) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_LCDCAM() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x200000) >> 21 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_ADC(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x400000)|value<<22) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_ADC() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x400000) >> 22 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x800000)|value<<23) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x800000) >> 23 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_RX(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x1000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_RX() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x1000000) >> 24 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_TX(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x2000000)|value<<25) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_TX() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x2000000) >> 25 +} +func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_H264(value uint32) { + volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x4000000)|value<<26) +} +func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_H264() uint32 { + return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x4000000) >> 26 +} + +// HP_SYS_CLKRST.HPWDT_CORE0_RST_CTRL0: Reserved +func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_EN() uint32 { + return volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_WAIT_NUM(value uint32) { + volatile.StoreUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg)&^(0x1fe)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_WAIT_NUM() uint32 { + return (volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg) & 0x1fe) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE0_RST_CTRL0_REG_WDT_HPCORE0_RST_LEN(value uint32) { + volatile.StoreUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg)&^(0x1fe00)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE0_RST_CTRL0_REG_WDT_HPCORE0_RST_LEN() uint32 { + return (volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg) & 0x1fe00) >> 9 +} + +// HP_SYS_CLKRST.HPWDT_CORE1_RST_CTRL0: Reserved +func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_EN() uint32 { + return volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_WAIT_NUM(value uint32) { + volatile.StoreUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg)&^(0x1fe)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_WAIT_NUM() uint32 { + return (volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg) & 0x1fe) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE1_RST_CTRL0_REG_WDT_HPCORE1_RST_LEN(value uint32) { + volatile.StoreUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg)&^(0x1fe00)|value<<9) +} +func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE1_RST_CTRL0_REG_WDT_HPCORE1_RST_LEN() uint32 { + return (volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg) & 0x1fe00) >> 9 +} + +// HP_SYS_CLKRST.CPU_SRC_FREQ0: CPU Source Frequency +func (o *HP_SYS_CLKRST_Type) SetCPU_SRC_FREQ0(value uint32) { + volatile.StoreUint32(&o.CPU_SRC_FREQ0.Reg, value) +} +func (o *HP_SYS_CLKRST_Type) GetCPU_SRC_FREQ0() uint32 { + return volatile.LoadUint32(&o.CPU_SRC_FREQ0.Reg) +} + +// HP_SYS_CLKRST.CPU_CLK_STATUS0: CPU Clock Status +func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_ASIC_OR_FPGA(value uint32) { + volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_ASIC_OR_FPGA() uint32 { + return volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_DIV_EFFECT(value uint32) { + volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_DIV_EFFECT() uint32 { + return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x2) >> 1 +} +func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_SRC_IS_CPLL(value uint32) { + volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x4)|value<<2) +} +func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_SRC_IS_CPLL() uint32 { + return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x4) >> 2 +} +func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_DIV_NUM_CUR(value uint32) { + volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x7f8)|value<<3) +} +func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_DIV_NUM_CUR() uint32 { + return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x7f8) >> 3 +} +func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_DIV_NUMERATOR_CUR(value uint32) { + volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x7f800)|value<<11) +} +func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_DIV_NUMERATOR_CUR() uint32 { + return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x7f800) >> 11 +} +func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_DIV_DENOMINATOR_CUR(value uint32) { + volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x7f80000)|value<<19) +} +func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_DIV_DENOMINATOR_CUR() uint32 { + return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x7f80000) >> 19 +} + +// HP_SYS_CLKRST.DBG_CLK_CTRL0: Reserved +func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL0_REG_DBG_CH0_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_CLK_CTRL0.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL0_REG_DBG_CH0_SEL() uint32 { + return volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL0_REG_DBG_CH1_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_CLK_CTRL0.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL0_REG_DBG_CH1_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL0_REG_DBG_CH2_SEL(value uint32) { + volatile.StoreUint32(&o.DBG_CLK_CTRL0.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg)&^(0xff0000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL0_REG_DBG_CH2_SEL() uint32 { + return (volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg) & 0xff0000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL0_REG_DBG_CH0_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.DBG_CLK_CTRL0.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg)&^(0xff000000)|value<<24) +} +func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL0_REG_DBG_CH0_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg) & 0xff000000) >> 24 +} + +// HP_SYS_CLKRST.DBG_CLK_CTRL1: Reserved +func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH1_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0xff)|value) +} +func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH1_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0xff +} +func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH2_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0xff00)|value<<8) +} +func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH2_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0xff00) >> 8 +} +func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH0_EN(value uint32) { + volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0x10000)|value<<16) +} +func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0x10000) >> 16 +} +func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH1_EN(value uint32) { + volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0x20000)|value<<17) +} +func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0x20000) >> 17 +} +func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH2_EN(value uint32) { + volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0x40000)|value<<18) +} +func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0x40000) >> 18 +} + +// HP_SYS_CLKRST.HPCORE_WDT_RESET_SOURCE0: Reserved +func (o *HP_SYS_CLKRST_Type) SetHPCORE_WDT_RESET_SOURCE0_REG_HPCORE0_WDT_RESET_SOURCE_SEL(value uint32) { + volatile.StoreUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg, volatile.LoadUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg)&^(0x1)|value) +} +func (o *HP_SYS_CLKRST_Type) GetHPCORE_WDT_RESET_SOURCE0_REG_HPCORE0_WDT_RESET_SOURCE_SEL() uint32 { + return volatile.LoadUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg) & 0x1 +} +func (o *HP_SYS_CLKRST_Type) SetHPCORE_WDT_RESET_SOURCE0_REG_HPCORE1_WDT_RESET_SOURCE_SEL(value uint32) { + volatile.StoreUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg, volatile.LoadUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg)&^(0x2)|value<<1) +} +func (o *HP_SYS_CLKRST_Type) GetHPCORE_WDT_RESET_SOURCE0_REG_HPCORE1_WDT_RESET_SOURCE_SEL() uint32 { + return (volatile.LoadUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg) & 0x2) >> 1 +} + +// LP_HUK Peripheral +type HUK_Type struct { + _ [4]byte + CLK volatile.Register32 // 0x4 + INT_RAW volatile.Register32 // 0x8 + INT_ST volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + INT_CLR volatile.Register32 // 0x14 + _ [8]byte + CONF volatile.Register32 // 0x20 + START volatile.Register32 // 0x24 + STATE volatile.Register32 // 0x28 + _ [8]byte + STATUS volatile.Register32 // 0x34 + _ [196]byte + DATE volatile.Register32 // 0xFC + INFO_MEM [96]volatile.Register32 // 0x100 +} + +// HUK.CLK: HUK Generator clock gate control register +func (o *HUK_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *HUK_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} +func (o *HUK_Type) SetCLK_MEM_CG_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1) +} +func (o *HUK_Type) GetCLK_MEM_CG_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1 +} + +// HUK.INT_RAW: HUK Generator interrupt raw register, valid in level. +func (o *HUK_Type) SetINT_RAW_PREP_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *HUK_Type) GetINT_RAW_PREP_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *HUK_Type) SetINT_RAW_PROC_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *HUK_Type) GetINT_RAW_PROC_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *HUK_Type) SetINT_RAW_POST_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *HUK_Type) GetINT_RAW_POST_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// HUK.INT_ST: HUK Generator interrupt status register. +func (o *HUK_Type) SetINT_ST_PREP_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *HUK_Type) GetINT_ST_PREP_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *HUK_Type) SetINT_ST_PROC_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *HUK_Type) GetINT_ST_PROC_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *HUK_Type) SetINT_ST_POST_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *HUK_Type) GetINT_ST_POST_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// HUK.INT_ENA: HUK Generator interrupt enable register. +func (o *HUK_Type) SetINT_ENA_PREP_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *HUK_Type) GetINT_ENA_PREP_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *HUK_Type) SetINT_ENA_PROC_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *HUK_Type) GetINT_ENA_PROC_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *HUK_Type) SetINT_ENA_POST_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *HUK_Type) GetINT_ENA_POST_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// HUK.INT_CLR: HUK Generator interrupt clear register. +func (o *HUK_Type) SetINT_CLR_PREP_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *HUK_Type) GetINT_CLR_PREP_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *HUK_Type) SetINT_CLR_PROC_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *HUK_Type) GetINT_CLR_PROC_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *HUK_Type) SetINT_CLR_POST_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *HUK_Type) GetINT_CLR_POST_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// HUK.CONF: HUK Generator configuration register +func (o *HUK_Type) SetCONF_MODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *HUK_Type) GetCONF_MODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} + +// HUK.START: HUK Generator control register +func (o *HUK_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x1)|value) +} +func (o *HUK_Type) GetSTART() uint32 { + return volatile.LoadUint32(&o.START.Reg) & 0x1 +} +func (o *HUK_Type) SetSTART_CONTINUE(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x2)|value<<1) +} +func (o *HUK_Type) GetSTART_CONTINUE() uint32 { + return (volatile.LoadUint32(&o.START.Reg) & 0x2) >> 1 +} + +// HUK.STATE: HUK Generator state register +func (o *HUK_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *HUK_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// HUK.STATUS: HUK Generator HUK status register +func (o *HUK_Type) SetSTATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3)|value) +} +func (o *HUK_Type) GetSTATUS() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x3 +} +func (o *HUK_Type) SetSTATUS_RISK_LEVEL(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1c)|value<<2) +} +func (o *HUK_Type) GetSTATUS_RISK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1c) >> 2 +} + +// HUK.DATE: Version control register +func (o *HUK_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *HUK_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// I2C (Inter-Integrated Circuit) Controller 0 +type I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + FILTER_CFG volatile.Register32 // 0x50 + CLK_CONF volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + SCL_ST_TIME_OUT volatile.Register32 // 0x78 + SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C + SCL_SP_CONF volatile.Register32 // 0x80 + SCL_STRETCH_CONF volatile.Register32 // 0x84 + _ [112]byte + DATE volatile.Register32 // 0xF8 + _ [4]byte + TXFIFO_START_ADDR volatile.Register32 // 0x100 + _ [124]byte + RXFIFO_START_ADDR volatile.Register32 // 0x180 +} + +// I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL Clock. +func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff +} + +// I2C.CTR: Transmission setting +func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetCTR_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetCTR_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetCTR_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetCTR_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetCTR_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetCTR_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetCTR_CONF_UPGATE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetCTR_CONF_UPGATE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetCTR_SLV_TX_AUTO_START_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetCTR_SLV_TX_AUTO_START_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetCTR_ADDR_10BIT_RW_CHECK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetCTR_ADDR_10BIT_RW_CHECK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetCTR_ADDR_BROADCASTING_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetCTR_ADDR_BROADCASTING_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4000) >> 14 +} + +// I2C.SR: Describe I2C work status. +func (o *I2C_Type) SetSR_RESP_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSR_RESP_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *I2C_Type) SetSR_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetSR_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetSR_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetSR_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetSR_STRETCH_CAUSE(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xc000)|value<<14) +} +func (o *I2C_Type) GetSR_STRETCH_CAUSE() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xc000) >> 14 +} +func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xfc0000) >> 18 +} +func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// I2C.TO: Setting time out control for receiving data. +func (o *I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetTO_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0x1f +} +func (o *I2C_Type) SetTO_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetTO_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5 +} + +// I2C.SLAVE_ADDR: Local slave address setting +func (o *I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// I2C.FIFO_ST: FIFO status register. +func (o *I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 { + return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x7c00)|value<<10) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x7c00) >> 10 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf8000)|value<<15) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf8000) >> 15 +} +func (o *I2C_Type) SetFIFO_ST_SLAVE_RW_POINT(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3fc00000)|value<<22) +} +func (o *I2C_Type) GetFIFO_ST_SLAVE_RW_POINT() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3fc00000) >> 22 +} + +// I2C.FIFO_CONF: FIFO configuration register. +func (o *I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_ADDR_CFG_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_ADDR_CFG_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14 +} + +// I2C.DATA: Rx FIFO read data. +func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// I2C.INT_RAW: Raw interrupt status +func (o *I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_STRETCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_STRETCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_RAW_GENERAL_CALL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_RAW_GENERAL_CALL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} + +// I2C.INT_CLR: Interrupt clear bits +func (o *I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_STRETCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_STRETCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_CLR_GENERAL_CALL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_CLR_GENERAL_CALL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} + +// I2C.INT_ENA: Interrupt enable bits +func (o *I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_STRETCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_STRETCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_ENA_GENERAL_CALL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_ENA_GENERAL_CALL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} + +// I2C.INT_STATUS: Status of captured I2C communication events +func (o *I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_STRETCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_STRETCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_STATUS_GENERAL_CALL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_STATUS_GENERAL_CALL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20000) >> 17 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40000)|value<<18) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40000) >> 18 +} + +// I2C.SDA_HOLD: Configures the hold time after a negative SCL edge. +func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff +} + +// I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge. +func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff +} + +// I2C.SCL_HIGH_PERIOD: Configures the high level width of SCL +func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff +} +func (o *I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9 +} + +// I2C.SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition +func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA +func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL rising edge for a stop condition. Measurement unit: i2c_sclk +func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff +} + +// I2C.FILTER_CFG: SCL and SDA filter configuration register +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4 +} +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9 +} + +// I2C.CLK_CONF: I2C CLK configuration register +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} + +// I2C.COMD0: I2C command register 0 +func (o *I2C_Type) SetCOMD0_COMMAND0(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD0_COMMAND0() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD0_COMMAND0_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD0_COMMAND0_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD1: I2C command register 1 +func (o *I2C_Type) SetCOMD1_COMMAND1(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD1_COMMAND1() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD1_COMMAND1_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD1_COMMAND1_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD2: I2C command register 2 +func (o *I2C_Type) SetCOMD2_COMMAND2(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD2_COMMAND2() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD2_COMMAND2_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD2_COMMAND2_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD3: I2C command register 3 +func (o *I2C_Type) SetCOMD3_COMMAND3(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD3_COMMAND3() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD3_COMMAND3_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD3_COMMAND3_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD4: I2C command register 4 +func (o *I2C_Type) SetCOMD4_COMMAND4(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD4_COMMAND4() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD4_COMMAND4_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD4_COMMAND4_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD5: I2C command register 5 +func (o *I2C_Type) SetCOMD5_COMMAND5(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD5_COMMAND5() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD5_COMMAND5_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD5_COMMAND5_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD6: I2C command register 6 +func (o *I2C_Type) SetCOMD6_COMMAND6(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD6_COMMAND6() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD6_COMMAND6_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD6_COMMAND6_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD7: I2C command register 7 +func (o *I2C_Type) SetCOMD7_COMMAND7(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD7_COMMAND7() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD7_COMMAND7_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD7_COMMAND7_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// I2C.SCL_ST_TIME_OUT: SCL status time out register +func (o *I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register +func (o *I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_SP_CONF: Power configuration register +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// I2C.SCL_STRETCH_CONF: Set SCL stretch of I2C slave +func (o *I2C_Type) SetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM() uint32 { + return volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x3ff +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x2000) >> 13 +} + +// I2C.DATE: Version register +func (o *I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2C.TXFIFO_START_ADDR: I2C TXFIFO base address register +func (o *I2C_Type) SetTXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetTXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg) +} + +// I2C.RXFIFO_START_ADDR: I2C RXFIFO base address register +func (o *I2C_Type) SetRXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetRXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg) +} + +// I2S (Inter-IC Sound) Controller 0 +type I2S_Type struct { + _ [12]byte + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + _ [4]byte + RX_CONF volatile.Register32 // 0x20 + TX_CONF volatile.Register32 // 0x24 + RX_CONF1 volatile.Register32 // 0x28 + TX_CONF1 volatile.Register32 // 0x2C + _ [16]byte + TX_PCM2PDM_CONF volatile.Register32 // 0x40 + TX_PCM2PDM_CONF1 volatile.Register32 // 0x44 + RX_PDM2PCM_CONF volatile.Register32 // 0x48 + _ [4]byte + RX_TDM_CTRL volatile.Register32 // 0x50 + TX_TDM_CTRL volatile.Register32 // 0x54 + RX_TIMING volatile.Register32 // 0x58 + TX_TIMING volatile.Register32 // 0x5C + LC_HUNG_CONF volatile.Register32 // 0x60 + RXEOF_NUM volatile.Register32 // 0x64 + CONF_SIGLE_DATA volatile.Register32 // 0x68 + STATE volatile.Register32 // 0x6C + ETM_CONF volatile.Register32 // 0x70 + FIFO_CNT volatile.Register32 // 0x74 + BCK_CNT volatile.Register32 // 0x78 + CLK_GATE volatile.Register32 // 0x7C + DATE volatile.Register32 // 0x80 +} + +// I2S.INT_RAW: I2S interrupt raw register, valid in level. +func (o *I2S_Type) SetINT_RAW_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_RAW_RX_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// I2S.INT_ST: I2S interrupt status register. +func (o *I2S_Type) SetINT_ST_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ST_RX_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// I2S.INT_ENA: I2S interrupt enable register. +func (o *I2S_Type) SetINT_ENA_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ENA_RX_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// I2S.INT_CLR: I2S interrupt clear register. +func (o *I2S_Type) SetINT_CLR_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_CLR_RX_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// I2S.RX_CONF: I2S RX configure register +func (o *I2S_Type) SetRX_CONF_RX_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_CONF_RX_RESET() uint32 { + return volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_CONF_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_CONF_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_CONF_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_CONF_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_CONF_RX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_CONF_RX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_CONF_RX_STOP_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetRX_CONF_RX_STOP_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetRX_CONF_RX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_CONF_RX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_CONF_RX_UPDATE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_CONF_RX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_CONF_RX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetRX_CONF_RX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetRX_CONF_RX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_CONF_RX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_CONF_RX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetRX_CONF_RX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetRX_CONF_RX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetRX_CONF_RX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetRX_CONF_RX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetRX_CONF_RX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetRX_CONF_RX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetRX_CONF_RX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetRX_CONF_RX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetRX_CONF_RX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetRX_CONF_RX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x7e00000)|value<<21) +} +func (o *I2S_Type) GetRX_CONF_RX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x7e00000) >> 21 +} + +// I2S.TX_CONF: I2S TX configure register +func (o *I2S_Type) SetTX_CONF_TX_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_CONF_TX_RESET() uint32 { + return volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_CONF_TX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_CONF_TX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_CONF_TX_START(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_CONF_TX_START() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_CONF_TX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_CONF_TX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_CONF_TX_STOP_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetTX_CONF_TX_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_EQUAL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_EQUAL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_CONF_TX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_CONF_TX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_CONF_TX_UPDATE(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_CONF_TX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_CONF_TX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_CONF_TX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_CONF_TX_BCK_NO_DLY(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetTX_CONF_TX_BCK_NO_DLY() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetTX_CONF_TX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_CONF_TX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_CONF_TX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetTX_CONF_TX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetTX_CONF_TX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetTX_CONF_TX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetTX_CONF_TX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetTX_CONF_TX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetTX_CONF_TX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetTX_CONF_TX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetTX_CONF_TX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_CONF_TX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetTX_CONF_TX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x7e00000)|value<<21) +} +func (o *I2S_Type) GetTX_CONF_TX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x7e00000) >> 21 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x38000000)|value<<27) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x38000000) >> 27 +} +func (o *I2S_Type) SetTX_CONF_SIG_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetTX_CONF_SIG_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000000) >> 30 +} + +// I2S.RX_CONF1: I2S RX configure register 1 +func (o *I2S_Type) SetRX_CONF1_RX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1ff +} +func (o *I2S_Type) SetRX_CONF1_RX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7c000)|value<<14) +} +func (o *I2S_Type) GetRX_CONF1_RX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7c000) >> 14 +} +func (o *I2S_Type) SetRX_CONF1_RX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7f80000)|value<<19) +} +func (o *I2S_Type) GetRX_CONF1_RX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7f80000) >> 19 +} +func (o *I2S_Type) SetRX_CONF1_RX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0xf8000000)|value<<27) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0xf8000000) >> 27 +} + +// I2S.TX_CONF1: I2S TX configure register 1 +func (o *I2S_Type) SetTX_CONF1_TX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1ff +} +func (o *I2S_Type) SetTX_CONF1_TX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7c000)|value<<14) +} +func (o *I2S_Type) GetTX_CONF1_TX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7c000) >> 14 +} +func (o *I2S_Type) SetTX_CONF1_TX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7f80000)|value<<19) +} +func (o *I2S_Type) GetTX_CONF1_TX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7f80000) >> 19 +} +func (o *I2S_Type) SetTX_CONF1_TX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0xf8000000)|value<<27) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0xf8000000) >> 27 +} + +// I2S.TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1e)|value<<1) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1e) >> 1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1fe0)|value<<5) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1fe0) >> 5 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x6000) >> 13 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x18000)|value<<15) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x18000) >> 15 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x60000)|value<<17) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x60000) >> 17 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x180000)|value<<19) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x180000) >> 19 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x400000) >> 22 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x800000) >> 23 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1000000) >> 24 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x2000000) >> 25 +} + +// I2S.TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FP(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3ff)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FP() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3ff +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FS() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x700000)|value<<20) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x700000) >> 20 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3800000) >> 23 +} + +// I2S.RX_PDM2PCM_CONF: I2S RX configure register +func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_PDM2PCM_EN(value uint32) { + volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_PDM2PCM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_PDM_SINC_DSR_16_EN(value uint32) { + volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_PDM_SINC_DSR_16_EN() uint32 { + return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_PDM2PCM_AMPLIFY_NUM(value uint32) { + volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x1e00000)|value<<21) +} +func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_PDM2PCM_AMPLIFY_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x1e00000) >> 21 +} +func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_PDM_HP_BYPASS(value uint32) { + volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_PDM_HP_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x2000000) >> 25 +} +func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_IIR_HP_MULT12_5(value uint32) { + volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x1c000000)|value<<26) +} +func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_IIR_HP_MULT12_5() uint32 { + return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x1c000000) >> 26 +} +func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_IIR_HP_MULT12_0(value uint32) { + volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0xe0000000)|value<<29) +} +func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_IIR_HP_MULT12_0() uint32 { + return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0xe0000000) >> 29 +} + +// I2S.RX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} + +// I2S.TX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100000) >> 20 +} + +// I2S.RX_TIMING: I2S RX timing control register +func (o *I2S_Type) SetRX_TIMING_RX_SD_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD_IN_DM() uint32 { + return volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetRX_TIMING_RX_SD1_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD1_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetRX_TIMING_RX_SD2_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300)|value<<8) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD2_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300) >> 8 +} +func (o *I2S_Type) SetRX_TIMING_RX_SD3_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000)|value<<12) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD3_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000) >> 12 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.TX_TIMING: I2S TX timing control register +func (o *I2S_Type) SetTX_TIMING_TX_SD_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD_OUT_DM() uint32 { + return volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetTX_TIMING_TX_SD1_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD1_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.LC_HUNG_CONF: I2S HUNG configure register. +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11 +} + +// I2S.RXEOF_NUM: I2S RX data number control register. +func (o *I2S_Type) SetRXEOF_NUM_RX_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.RXEOF_NUM.Reg, volatile.LoadUint32(&o.RXEOF_NUM.Reg)&^(0xfff)|value) +} +func (o *I2S_Type) GetRXEOF_NUM_RX_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.RXEOF_NUM.Reg) & 0xfff +} + +// I2S.CONF_SIGLE_DATA: I2S signal data register +func (o *I2S_Type) SetCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value) +} +func (o *I2S_Type) GetCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg) +} + +// I2S.STATE: I2S TX status register +func (o *I2S_Type) SetSTATE_TX_IDLE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetSTATE_TX_IDLE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x1 +} + +// I2S.ETM_CONF: I2S ETM configure register +func (o *I2S_Type) SetETM_CONF_ETM_TX_SEND_WORD_NUM(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2S_Type) GetETM_CONF_ETM_TX_SEND_WORD_NUM() uint32 { + return volatile.LoadUint32(&o.ETM_CONF.Reg) & 0x3ff +} +func (o *I2S_Type) SetETM_CONF_ETM_RX_RECEIVE_WORD_NUM(value uint32) { + volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *I2S_Type) GetETM_CONF_ETM_RX_RECEIVE_WORD_NUM() uint32 { + return (volatile.LoadUint32(&o.ETM_CONF.Reg) & 0xffc00) >> 10 +} + +// I2S.FIFO_CNT: I2S sync counter register +func (o *I2S_Type) SetFIFO_CNT_TX_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.FIFO_CNT.Reg, volatile.LoadUint32(&o.FIFO_CNT.Reg)&^(0x7fffffff)|value) +} +func (o *I2S_Type) GetFIFO_CNT_TX_FIFO_CNT() uint32 { + return volatile.LoadUint32(&o.FIFO_CNT.Reg) & 0x7fffffff +} +func (o *I2S_Type) SetFIFO_CNT_TX_FIFO_CNT_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CNT.Reg, volatile.LoadUint32(&o.FIFO_CNT.Reg)&^(0x80000000)|value<<31) +} +func (o *I2S_Type) GetFIFO_CNT_TX_FIFO_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CNT.Reg) & 0x80000000) >> 31 +} + +// I2S.BCK_CNT: I2S sync counter register +func (o *I2S_Type) SetBCK_CNT_TX_BCK_CNT(value uint32) { + volatile.StoreUint32(&o.BCK_CNT.Reg, volatile.LoadUint32(&o.BCK_CNT.Reg)&^(0x7fffffff)|value) +} +func (o *I2S_Type) GetBCK_CNT_TX_BCK_CNT() uint32 { + return volatile.LoadUint32(&o.BCK_CNT.Reg) & 0x7fffffff +} +func (o *I2S_Type) SetBCK_CNT_TX_BCK_CNT_RST(value uint32) { + volatile.StoreUint32(&o.BCK_CNT.Reg, volatile.LoadUint32(&o.BCK_CNT.Reg)&^(0x80000000)|value<<31) +} +func (o *I2S_Type) GetBCK_CNT_TX_BCK_CNT_RST() uint32 { + return (volatile.LoadUint32(&o.BCK_CNT.Reg) & 0x80000000) >> 31 +} + +// I2S.CLK_GATE: Clock gate register +func (o *I2S_Type) SetCLK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetCLK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x1 +} + +// I2S.DATE: Version control register +func (o *I2S_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *I2S_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// I3C Controller (Master) +type I3C_MST_Type struct { + DEVICE_CTRL volatile.Register32 // 0x0 + _ [24]byte + BUFFER_THLD_CTRL volatile.Register32 // 0x1C + DATA_BUFFER_THLD_CTRL volatile.Register32 // 0x20 + IBI_NOTIFY_CTRL volatile.Register32 // 0x24 + IBI_SIR_REQ_PAYLOAD volatile.Register32 // 0x28 + IBI_SIR_REQ_REJECT volatile.Register32 // 0x2C + INT_CLR volatile.Register32 // 0x30 + INT_RAW volatile.Register32 // 0x34 + INT_ST volatile.Register32 // 0x38 + INT_ST_ENA volatile.Register32 // 0x3C + _ [4]byte + RESET_CTRL volatile.Register32 // 0x44 + BUFFER_STATUS_LEVEL volatile.Register32 // 0x48 + DATA_BUFFER_STATUS_LEVEL volatile.Register32 // 0x4C + PRESENT_STATE0 volatile.Register32 // 0x50 + PRESENT_STATE1 volatile.Register32 // 0x54 + DEVICE_TABLE volatile.Register32 // 0x58 + TIME_OUT_VALUE volatile.Register32 // 0x5C + SCL_I3C_MST_OD_TIME volatile.Register32 // 0x60 + SCL_I3C_MST_PP_TIME volatile.Register32 // 0x64 + SCL_I2C_FM_TIME volatile.Register32 // 0x68 + SCL_I2C_FMP_TIME volatile.Register32 // 0x6C + SCL_EXT_LOW_TIME volatile.Register32 // 0x70 + SDA_SAMPLE_TIME volatile.Register32 // 0x74 + SDA_HOLD_TIME volatile.Register32 // 0x78 + SCL_START_HOLD volatile.Register32 // 0x7C + SCL_RSTART_SETUP volatile.Register32 // 0x80 + SCL_STOP_HOLD volatile.Register32 // 0x84 + SCL_STOP_SETUP volatile.Register32 // 0x88 + _ [4]byte + BUS_FREE_TIME volatile.Register32 // 0x90 + SCL_TERMN_T_EXT_LOW_TIME volatile.Register32 // 0x94 + _ [8]byte + VER_ID volatile.Register32 // 0xA0 + VER_TYPE volatile.Register32 // 0xA4 + _ [4]byte + FPGA_DEBUG_PROBE volatile.Register32 // 0xAC + RND_ECO_CS volatile.Register32 // 0xB0 + RND_ECO_LOW volatile.Register32 // 0xB4 + RND_ECO_HIGH volatile.Register32 // 0xB8 +} + +// I3C_MST.DEVICE_CTRL: DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities. +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_BA_INCLUDE(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_BA_INCLUDE() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x2) >> 1 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_TRANS_START(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x4) >> 2 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x8) >> 3 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_IBI_RSTART_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_IBI_RSTART_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x10) >> 4 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_AUTO_DIS_IBI_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_AUTO_DIS_IBI_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x20) >> 5 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_DMA_RX_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_DMA_RX_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x40) >> 6 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_DMA_TX_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_DMA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x80) >> 7 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_MULTI_SLV_SINGLE_CCC_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_MULTI_SLV_SINGLE_CCC_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x100) >> 8 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_RX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_RX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x200) >> 9 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_RX_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_RX_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x400) >> 10 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SCL_PULLUP_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SCL_PULLUP_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x800) >> 11 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SCL_OE_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SCL_OE_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SDA_PP_RD_PULLUP_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SDA_PP_RD_PULLUP_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SDA_RD_TBIT_HLVL_PULLUP_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SDA_RD_TBIT_HLVL_PULLUP_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SDA_PP_WR_PULLUP_EN(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SDA_PP_WR_PULLUP_EN() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_DATA_BYTE_CNT_UNLATCH(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_DATA_BYTE_CNT_UNLATCH() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x10000) >> 16 +} +func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x20000) >> 17 +} + +// I3C_MST.BUFFER_THLD_CTRL: In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. +func (o *I3C_MST_Type) SetBUFFER_THLD_CTRL_REG_CMD_BUF_EMPTY_THLD(value uint32) { + volatile.StoreUint32(&o.BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg)&^(0xf)|value) +} +func (o *I3C_MST_Type) GetBUFFER_THLD_CTRL_REG_CMD_BUF_EMPTY_THLD() uint32 { + return volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg) & 0xf +} +func (o *I3C_MST_Type) SetBUFFER_THLD_CTRL_REG_RESP_BUF_THLD(value uint32) { + volatile.StoreUint32(&o.BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg)&^(0x1c0)|value<<6) +} +func (o *I3C_MST_Type) GetBUFFER_THLD_CTRL_REG_RESP_BUF_THLD() uint32 { + return (volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg) & 0x1c0) >> 6 +} +func (o *I3C_MST_Type) SetBUFFER_THLD_CTRL_REG_IBI_DATA_BUF_THLD(value uint32) { + volatile.StoreUint32(&o.BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg)&^(0x7000)|value<<12) +} +func (o *I3C_MST_Type) GetBUFFER_THLD_CTRL_REG_IBI_DATA_BUF_THLD() uint32 { + return (volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg) & 0x7000) >> 12 +} +func (o *I3C_MST_Type) SetBUFFER_THLD_CTRL_REG_IBI_STATUS_BUF_THLD(value uint32) { + volatile.StoreUint32(&o.BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg)&^(0x1c0000)|value<<18) +} +func (o *I3C_MST_Type) GetBUFFER_THLD_CTRL_REG_IBI_STATUS_BUF_THLD() uint32 { + return (volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg) & 0x1c0000) >> 18 +} + +// I3C_MST.DATA_BUFFER_THLD_CTRL: NA +func (o *I3C_MST_Type) SetDATA_BUFFER_THLD_CTRL_REG_TX_DATA_BUF_THLD(value uint32) { + volatile.StoreUint32(&o.DATA_BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.DATA_BUFFER_THLD_CTRL.Reg)&^(0x7)|value) +} +func (o *I3C_MST_Type) GetDATA_BUFFER_THLD_CTRL_REG_TX_DATA_BUF_THLD() uint32 { + return volatile.LoadUint32(&o.DATA_BUFFER_THLD_CTRL.Reg) & 0x7 +} +func (o *I3C_MST_Type) SetDATA_BUFFER_THLD_CTRL_REG_RX_DATA_BUF_THLD(value uint32) { + volatile.StoreUint32(&o.DATA_BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.DATA_BUFFER_THLD_CTRL.Reg)&^(0x38)|value<<3) +} +func (o *I3C_MST_Type) GetDATA_BUFFER_THLD_CTRL_REG_RX_DATA_BUF_THLD() uint32 { + return (volatile.LoadUint32(&o.DATA_BUFFER_THLD_CTRL.Reg) & 0x38) >> 3 +} + +// I3C_MST.IBI_NOTIFY_CTRL: NA +func (o *I3C_MST_Type) SetIBI_NOTIFY_CTRL_REG_NOTIFY_SIR_REJECTED(value uint32) { + volatile.StoreUint32(&o.IBI_NOTIFY_CTRL.Reg, volatile.LoadUint32(&o.IBI_NOTIFY_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I3C_MST_Type) GetIBI_NOTIFY_CTRL_REG_NOTIFY_SIR_REJECTED() uint32 { + return (volatile.LoadUint32(&o.IBI_NOTIFY_CTRL.Reg) & 0x4) >> 2 +} + +// I3C_MST.IBI_SIR_REQ_PAYLOAD: NA +func (o *I3C_MST_Type) SetIBI_SIR_REQ_PAYLOAD(value uint32) { + volatile.StoreUint32(&o.IBI_SIR_REQ_PAYLOAD.Reg, value) +} +func (o *I3C_MST_Type) GetIBI_SIR_REQ_PAYLOAD() uint32 { + return volatile.LoadUint32(&o.IBI_SIR_REQ_PAYLOAD.Reg) +} + +// I3C_MST.IBI_SIR_REQ_REJECT: NA +func (o *I3C_MST_Type) SetIBI_SIR_REQ_REJECT(value uint32) { + volatile.StoreUint32(&o.IBI_SIR_REQ_REJECT.Reg, value) +} +func (o *I3C_MST_Type) GetIBI_SIR_REQ_REJECT() uint32 { + return volatile.LoadUint32(&o.IBI_SIR_REQ_REJECT.Reg) +} + +// I3C_MST.INT_CLR: NA +func (o *I3C_MST_Type) SetINT_CLR_TX_DATA_BUF_THLD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I3C_MST_Type) GetINT_CLR_TX_DATA_BUF_THLD_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I3C_MST_Type) SetINT_CLR_RX_DATA_BUF_THLD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I3C_MST_Type) GetINT_CLR_RX_DATA_BUF_THLD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I3C_MST_Type) SetINT_CLR_IBI_STATUS_THLD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I3C_MST_Type) GetINT_CLR_IBI_STATUS_THLD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I3C_MST_Type) SetINT_CLR_CMD_BUF_EMPTY_THLD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I3C_MST_Type) GetINT_CLR_CMD_BUF_EMPTY_THLD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I3C_MST_Type) SetINT_CLR_RESP_READY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I3C_MST_Type) GetINT_CLR_RESP_READY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I3C_MST_Type) SetINT_CLR_NXT_CMD_REQ_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I3C_MST_Type) GetINT_CLR_NXT_CMD_REQ_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I3C_MST_Type) SetINT_CLR_TRANSFER_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I3C_MST_Type) GetINT_CLR_TRANSFER_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I3C_MST_Type) SetINT_CLR_TRANSFER_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I3C_MST_Type) GetINT_CLR_TRANSFER_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I3C_MST_Type) SetINT_CLR_COMMAND_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I3C_MST_Type) GetINT_CLR_COMMAND_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I3C_MST_Type) SetINT_CLR_DETECT_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I3C_MST_Type) GetINT_CLR_DETECT_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I3C_MST_Type) SetINT_CLR_RESP_BUF_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I3C_MST_Type) GetINT_CLR_RESP_BUF_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I3C_MST_Type) SetINT_CLR_IBI_DATA_BUF_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I3C_MST_Type) GetINT_CLR_IBI_DATA_BUF_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I3C_MST_Type) SetINT_CLR_IBI_STATUS_BUF_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I3C_MST_Type) GetINT_CLR_IBI_STATUS_BUF_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I3C_MST_Type) SetINT_CLR_IBI_HANDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I3C_MST_Type) GetINT_CLR_IBI_HANDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I3C_MST_Type) SetINT_CLR_IBI_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I3C_MST_Type) GetINT_CLR_IBI_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I3C_MST_Type) SetINT_CLR_CMD_CCC_MISMATCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I3C_MST_Type) GetINT_CLR_CMD_CCC_MISMATCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} + +// I3C_MST.INT_RAW: NA +func (o *I3C_MST_Type) SetINT_RAW_TX_DATA_BUF_THLD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I3C_MST_Type) GetINT_RAW_TX_DATA_BUF_THLD_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I3C_MST_Type) SetINT_RAW_RX_DATA_BUF_THLD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I3C_MST_Type) GetINT_RAW_RX_DATA_BUF_THLD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I3C_MST_Type) SetINT_RAW_IBI_STATUS_THLD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I3C_MST_Type) GetINT_RAW_IBI_STATUS_THLD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I3C_MST_Type) SetINT_RAW_CMD_BUF_EMPTY_THLD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I3C_MST_Type) GetINT_RAW_CMD_BUF_EMPTY_THLD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I3C_MST_Type) SetINT_RAW_RESP_READY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I3C_MST_Type) GetINT_RAW_RESP_READY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I3C_MST_Type) SetINT_RAW_NXT_CMD_REQ_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I3C_MST_Type) GetINT_RAW_NXT_CMD_REQ_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I3C_MST_Type) SetINT_RAW_TRANSFER_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I3C_MST_Type) GetINT_RAW_TRANSFER_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I3C_MST_Type) SetINT_RAW_TRANSFER_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I3C_MST_Type) GetINT_RAW_TRANSFER_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I3C_MST_Type) SetINT_RAW_COMMAND_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I3C_MST_Type) GetINT_RAW_COMMAND_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I3C_MST_Type) SetINT_RAW_DETECT_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I3C_MST_Type) GetINT_RAW_DETECT_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I3C_MST_Type) SetINT_RAW_RESP_BUF_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I3C_MST_Type) GetINT_RAW_RESP_BUF_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I3C_MST_Type) SetINT_RAW_IBI_DATA_BUF_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I3C_MST_Type) GetINT_RAW_IBI_DATA_BUF_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I3C_MST_Type) SetINT_RAW_IBI_STATUS_BUF_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I3C_MST_Type) GetINT_RAW_IBI_STATUS_BUF_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I3C_MST_Type) SetINT_RAW_IBI_HANDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I3C_MST_Type) GetINT_RAW_IBI_HANDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I3C_MST_Type) SetINT_RAW_IBI_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I3C_MST_Type) GetINT_RAW_IBI_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I3C_MST_Type) SetINT_RAW_CMD_CCC_MISMATCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I3C_MST_Type) GetINT_RAW_CMD_CCC_MISMATCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} + +// I3C_MST.INT_ST: NA +func (o *I3C_MST_Type) SetINT_ST_TX_DATA_BUF_THLD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *I3C_MST_Type) GetINT_ST_TX_DATA_BUF_THLD_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *I3C_MST_Type) SetINT_ST_RX_DATA_BUF_THLD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I3C_MST_Type) GetINT_ST_RX_DATA_BUF_THLD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *I3C_MST_Type) SetINT_ST_IBI_STATUS_THLD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I3C_MST_Type) GetINT_ST_IBI_STATUS_THLD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *I3C_MST_Type) SetINT_ST_CMD_BUF_EMPTY_THLD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I3C_MST_Type) GetINT_ST_CMD_BUF_EMPTY_THLD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *I3C_MST_Type) SetINT_ST_RESP_READY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *I3C_MST_Type) GetINT_ST_RESP_READY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *I3C_MST_Type) SetINT_ST_NXT_CMD_REQ_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *I3C_MST_Type) GetINT_ST_NXT_CMD_REQ_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *I3C_MST_Type) SetINT_ST_TRANSFER_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *I3C_MST_Type) GetINT_ST_TRANSFER_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *I3C_MST_Type) SetINT_ST_TRANSFER_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *I3C_MST_Type) GetINT_ST_TRANSFER_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *I3C_MST_Type) SetINT_ST_COMMAND_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *I3C_MST_Type) GetINT_ST_COMMAND_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *I3C_MST_Type) SetINT_ST_DETECT_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *I3C_MST_Type) GetINT_ST_DETECT_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *I3C_MST_Type) SetINT_ST_RESP_BUF_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *I3C_MST_Type) GetINT_ST_RESP_BUF_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *I3C_MST_Type) SetINT_ST_IBI_DATA_BUF_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *I3C_MST_Type) GetINT_ST_IBI_DATA_BUF_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *I3C_MST_Type) SetINT_ST_IBI_STATUS_BUF_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *I3C_MST_Type) GetINT_ST_IBI_STATUS_BUF_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *I3C_MST_Type) SetINT_ST_IBI_HANDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *I3C_MST_Type) GetINT_ST_IBI_HANDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *I3C_MST_Type) SetINT_ST_IBI_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *I3C_MST_Type) GetINT_ST_IBI_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *I3C_MST_Type) SetINT_ST_CMD_CCC_MISMATCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *I3C_MST_Type) GetINT_ST_CMD_CCC_MISMATCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} + +// I3C_MST.INT_ST_ENA: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set. +func (o *I3C_MST_Type) SetINT_ST_ENA_TX_DATA_BUF_THLD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x1)|value) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_TX_DATA_BUF_THLD_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x1 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_RX_DATA_BUF_THLD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_RX_DATA_BUF_THLD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x2) >> 1 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_STATUS_THLD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_STATUS_THLD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x4) >> 2 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_CMD_BUF_EMPTY_THLD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_CMD_BUF_EMPTY_THLD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x8) >> 3 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_RESP_READY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_RESP_READY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x10) >> 4 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_NXT_CMD_REQ_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_NXT_CMD_REQ_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x20) >> 5 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_TRANSFER_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_TRANSFER_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x40) >> 6 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_TRANSFER_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_TRANSFER_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x80) >> 7 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_COMMAND_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_COMMAND_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x100) >> 8 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_DETECT_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_DETECT_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x200) >> 9 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_RESP_BUF_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_RESP_BUF_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x400) >> 10 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_DATA_BUF_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_DATA_BUF_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x800) >> 11 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_STATUS_BUF_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_STATUS_BUF_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x1000) >> 12 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_HANDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_HANDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x2000) >> 13 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x4000) >> 14 +} +func (o *I3C_MST_Type) SetINT_ST_ENA_CMD_CCC_MISMATCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I3C_MST_Type) GetINT_ST_ENA_CMD_CCC_MISMATCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x8000) >> 15 +} + +// I3C_MST.RESET_CTRL: NA +func (o *I3C_MST_Type) SetRESET_CTRL_REG_CORE_SOFT_RST(value uint32) { + volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x1)|value) +} +func (o *I3C_MST_Type) GetRESET_CTRL_REG_CORE_SOFT_RST() uint32 { + return volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x1 +} +func (o *I3C_MST_Type) SetRESET_CTRL_REG_CMD_BUF_RST(value uint32) { + volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I3C_MST_Type) GetRESET_CTRL_REG_CMD_BUF_RST() uint32 { + return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x2) >> 1 +} +func (o *I3C_MST_Type) SetRESET_CTRL_REG_RESP_BUF_RST(value uint32) { + volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I3C_MST_Type) GetRESET_CTRL_REG_RESP_BUF_RST() uint32 { + return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x4) >> 2 +} +func (o *I3C_MST_Type) SetRESET_CTRL_REG_TX_DATA_BUF_BUF_RST(value uint32) { + volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I3C_MST_Type) GetRESET_CTRL_REG_TX_DATA_BUF_BUF_RST() uint32 { + return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x8) >> 3 +} +func (o *I3C_MST_Type) SetRESET_CTRL_REG_RX_DATA_BUF_RST(value uint32) { + volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I3C_MST_Type) GetRESET_CTRL_REG_RX_DATA_BUF_RST() uint32 { + return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x10) >> 4 +} +func (o *I3C_MST_Type) SetRESET_CTRL_REG_IBI_DATA_BUF_RST(value uint32) { + volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I3C_MST_Type) GetRESET_CTRL_REG_IBI_DATA_BUF_RST() uint32 { + return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x20) >> 5 +} +func (o *I3C_MST_Type) SetRESET_CTRL_REG_IBI_STATUS_BUF_RST(value uint32) { + volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I3C_MST_Type) GetRESET_CTRL_REG_IBI_STATUS_BUF_RST() uint32 { + return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x40) >> 6 +} + +// I3C_MST.BUFFER_STATUS_LEVEL: BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller. +func (o *I3C_MST_Type) SetBUFFER_STATUS_LEVEL_CMD_BUF_EMPTY_CNT(value uint32) { + volatile.StoreUint32(&o.BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg)&^(0x1f)|value) +} +func (o *I3C_MST_Type) GetBUFFER_STATUS_LEVEL_CMD_BUF_EMPTY_CNT() uint32 { + return volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg) & 0x1f +} +func (o *I3C_MST_Type) SetBUFFER_STATUS_LEVEL_RESP_BUF_CNT(value uint32) { + volatile.StoreUint32(&o.BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg)&^(0xf00)|value<<8) +} +func (o *I3C_MST_Type) GetBUFFER_STATUS_LEVEL_RESP_BUF_CNT() uint32 { + return (volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg) & 0xf00) >> 8 +} +func (o *I3C_MST_Type) SetBUFFER_STATUS_LEVEL_IBI_DATA_BUF_CNT(value uint32) { + volatile.StoreUint32(&o.BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg)&^(0xf0000)|value<<16) +} +func (o *I3C_MST_Type) GetBUFFER_STATUS_LEVEL_IBI_DATA_BUF_CNT() uint32 { + return (volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg) & 0xf0000) >> 16 +} +func (o *I3C_MST_Type) SetBUFFER_STATUS_LEVEL_IBI_STATUS_BUF_CNT(value uint32) { + volatile.StoreUint32(&o.BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg)&^(0xf000000)|value<<24) +} +func (o *I3C_MST_Type) GetBUFFER_STATUS_LEVEL_IBI_STATUS_BUF_CNT() uint32 { + return (volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg) & 0xf000000) >> 24 +} + +// I3C_MST.DATA_BUFFER_STATUS_LEVEL: DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller. +func (o *I3C_MST_Type) SetDATA_BUFFER_STATUS_LEVEL_TX_DATA_BUF_EMPTY_CNT(value uint32) { + volatile.StoreUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg)&^(0x3f)|value) +} +func (o *I3C_MST_Type) GetDATA_BUFFER_STATUS_LEVEL_TX_DATA_BUF_EMPTY_CNT() uint32 { + return volatile.LoadUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg) & 0x3f +} +func (o *I3C_MST_Type) SetDATA_BUFFER_STATUS_LEVEL_RX_DATA_BUF_CNT(value uint32) { + volatile.StoreUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg)&^(0x3f0000)|value<<16) +} +func (o *I3C_MST_Type) GetDATA_BUFFER_STATUS_LEVEL_RX_DATA_BUF_CNT() uint32 { + return (volatile.LoadUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg) & 0x3f0000) >> 16 +} + +// I3C_MST.PRESENT_STATE0: NA +func (o *I3C_MST_Type) SetPRESENT_STATE0_SDA_LVL(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x1)|value) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_SDA_LVL() uint32 { + return volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x1 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_SCL_LVL(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x2)|value<<1) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_SCL_LVL() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x2) >> 1 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x4)|value<<2) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x4) >> 2 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_BUS_FREE(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x8)|value<<3) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_BUS_FREE() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x8) >> 3 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_CMD_TID(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x1e00)|value<<9) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_CMD_TID() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x1e00) >> 9 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_SCL_GEN_FSM_STATE(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0xe000)|value<<13) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_SCL_GEN_FSM_STATE() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0xe000) >> 13 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_IBI_EV_HANDLE_FSM_STATE(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x70000)|value<<16) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_IBI_EV_HANDLE_FSM_STATE() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x70000) >> 16 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_I2C_MODE_FSM_STATE(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x380000)|value<<19) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_I2C_MODE_FSM_STATE() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x380000) >> 19 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_SDR_MODE_FSM_STATE(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x3c00000)|value<<22) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_SDR_MODE_FSM_STATE() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x3c00000) >> 22 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_DAA_MODE_FSM_STATE(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x1c000000)|value<<26) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_DAA_MODE_FSM_STATE() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x1c000000) >> 26 +} +func (o *I3C_MST_Type) SetPRESENT_STATE0_MAIN_FSM_STATE(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0xe0000000)|value<<29) +} +func (o *I3C_MST_Type) GetPRESENT_STATE0_MAIN_FSM_STATE() uint32 { + return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0xe0000000) >> 29 +} + +// I3C_MST.PRESENT_STATE1: NA +func (o *I3C_MST_Type) SetPRESENT_STATE1_DATA_BYTE_CNT(value uint32) { + volatile.StoreUint32(&o.PRESENT_STATE1.Reg, volatile.LoadUint32(&o.PRESENT_STATE1.Reg)&^(0xffff)|value) +} +func (o *I3C_MST_Type) GetPRESENT_STATE1_DATA_BYTE_CNT() uint32 { + return volatile.LoadUint32(&o.PRESENT_STATE1.Reg) & 0xffff +} + +// I3C_MST.DEVICE_TABLE: Pointer for Device Address Table +func (o *I3C_MST_Type) SetDEVICE_TABLE_REG_DCT_DAA_INIT_INDEX(value uint32) { + volatile.StoreUint32(&o.DEVICE_TABLE.Reg, volatile.LoadUint32(&o.DEVICE_TABLE.Reg)&^(0xf)|value) +} +func (o *I3C_MST_Type) GetDEVICE_TABLE_REG_DCT_DAA_INIT_INDEX() uint32 { + return volatile.LoadUint32(&o.DEVICE_TABLE.Reg) & 0xf +} +func (o *I3C_MST_Type) SetDEVICE_TABLE_REG_DAT_DAA_INIT_INDEX(value uint32) { + volatile.StoreUint32(&o.DEVICE_TABLE.Reg, volatile.LoadUint32(&o.DEVICE_TABLE.Reg)&^(0xf0)|value<<4) +} +func (o *I3C_MST_Type) GetDEVICE_TABLE_REG_DAT_DAA_INIT_INDEX() uint32 { + return (volatile.LoadUint32(&o.DEVICE_TABLE.Reg) & 0xf0) >> 4 +} +func (o *I3C_MST_Type) SetDEVICE_TABLE_PRESENT_DCT_INDEX(value uint32) { + volatile.StoreUint32(&o.DEVICE_TABLE.Reg, volatile.LoadUint32(&o.DEVICE_TABLE.Reg)&^(0xf00)|value<<8) +} +func (o *I3C_MST_Type) GetDEVICE_TABLE_PRESENT_DCT_INDEX() uint32 { + return (volatile.LoadUint32(&o.DEVICE_TABLE.Reg) & 0xf00) >> 8 +} +func (o *I3C_MST_Type) SetDEVICE_TABLE_PRESENT_DAT_INDEX(value uint32) { + volatile.StoreUint32(&o.DEVICE_TABLE.Reg, volatile.LoadUint32(&o.DEVICE_TABLE.Reg)&^(0xf000)|value<<12) +} +func (o *I3C_MST_Type) GetDEVICE_TABLE_PRESENT_DAT_INDEX() uint32 { + return (volatile.LoadUint32(&o.DEVICE_TABLE.Reg) & 0xf000) >> 12 +} + +// I3C_MST.TIME_OUT_VALUE: NA +func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_RESP_BUF_TO_VALUE(value uint32) { + volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x1f)|value) +} +func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_RESP_BUF_TO_VALUE() uint32 { + return volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x1f +} +func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_RESP_BUF_TO_EN(value uint32) { + volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x20)|value<<5) +} +func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_RESP_BUF_TO_EN() uint32 { + return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x20) >> 5 +} +func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_VALUE(value uint32) { + volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x7c0)|value<<6) +} +func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_VALUE() uint32 { + return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x7c0) >> 6 +} +func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_EN(value uint32) { + volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x800)|value<<11) +} +func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_EN() uint32 { + return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x800) >> 11 +} +func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_VALUE(value uint32) { + volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x1f000)|value<<12) +} +func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_VALUE() uint32 { + return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x1f000) >> 12 +} +func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_EN(value uint32) { + volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x20000)|value<<17) +} +func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_EN() uint32 { + return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x20000) >> 17 +} +func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_RX_DATA_BUF_TO_VALUE(value uint32) { + volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x7c0000)|value<<18) +} +func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_RX_DATA_BUF_TO_VALUE() uint32 { + return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x7c0000) >> 18 +} +func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_RX_DATA_BUF_TO_EN(value uint32) { + volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x800000)|value<<23) +} +func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_RX_DATA_BUF_TO_EN() uint32 { + return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x800000) >> 23 +} + +// I3C_MST.SCL_I3C_MST_OD_TIME: NA +func (o *I3C_MST_Type) SetSCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_I3C_MST_OD_TIME.Reg, volatile.LoadUint32(&o.SCL_I3C_MST_OD_TIME.Reg)&^(0xffff)|value) +} +func (o *I3C_MST_Type) GetSCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_I3C_MST_OD_TIME.Reg) & 0xffff +} +func (o *I3C_MST_Type) SetSCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_I3C_MST_OD_TIME.Reg, volatile.LoadUint32(&o.SCL_I3C_MST_OD_TIME.Reg)&^(0xffff0000)|value<<16) +} +func (o *I3C_MST_Type) GetSCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_I3C_MST_OD_TIME.Reg) & 0xffff0000) >> 16 +} + +// I3C_MST.SCL_I3C_MST_PP_TIME: NA +func (o *I3C_MST_Type) SetSCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_I3C_MST_PP_TIME.Reg, volatile.LoadUint32(&o.SCL_I3C_MST_PP_TIME.Reg)&^(0xff)|value) +} +func (o *I3C_MST_Type) GetSCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_I3C_MST_PP_TIME.Reg) & 0xff +} +func (o *I3C_MST_Type) SetSCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_I3C_MST_PP_TIME.Reg, volatile.LoadUint32(&o.SCL_I3C_MST_PP_TIME.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_Type) GetSCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_I3C_MST_PP_TIME.Reg) & 0xff0000) >> 16 +} + +// I3C_MST.SCL_I2C_FM_TIME: NA +func (o *I3C_MST_Type) SetSCL_I2C_FM_TIME_REG_I2C_FM_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_I2C_FM_TIME.Reg, volatile.LoadUint32(&o.SCL_I2C_FM_TIME.Reg)&^(0xffff)|value) +} +func (o *I3C_MST_Type) GetSCL_I2C_FM_TIME_REG_I2C_FM_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_I2C_FM_TIME.Reg) & 0xffff +} +func (o *I3C_MST_Type) SetSCL_I2C_FM_TIME_REG_I2C_FM_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_I2C_FM_TIME.Reg, volatile.LoadUint32(&o.SCL_I2C_FM_TIME.Reg)&^(0xffff0000)|value<<16) +} +func (o *I3C_MST_Type) GetSCL_I2C_FM_TIME_REG_I2C_FM_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_I2C_FM_TIME.Reg) & 0xffff0000) >> 16 +} + +// I3C_MST.SCL_I2C_FMP_TIME: NA +func (o *I3C_MST_Type) SetSCL_I2C_FMP_TIME_REG_I2C_FMP_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_I2C_FMP_TIME.Reg, volatile.LoadUint32(&o.SCL_I2C_FMP_TIME.Reg)&^(0xffff)|value) +} +func (o *I3C_MST_Type) GetSCL_I2C_FMP_TIME_REG_I2C_FMP_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_I2C_FMP_TIME.Reg) & 0xffff +} +func (o *I3C_MST_Type) SetSCL_I2C_FMP_TIME_REG_I2C_FMP_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_I2C_FMP_TIME.Reg, volatile.LoadUint32(&o.SCL_I2C_FMP_TIME.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_Type) GetSCL_I2C_FMP_TIME_REG_I2C_FMP_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_I2C_FMP_TIME.Reg) & 0xff0000) >> 16 +} + +// I3C_MST.SCL_EXT_LOW_TIME: NA +func (o *I3C_MST_Type) SetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD1(value uint32) { + volatile.StoreUint32(&o.SCL_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg)&^(0xff)|value) +} +func (o *I3C_MST_Type) GetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD1() uint32 { + return volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg) & 0xff +} +func (o *I3C_MST_Type) SetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD2(value uint32) { + volatile.StoreUint32(&o.SCL_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg)&^(0xff00)|value<<8) +} +func (o *I3C_MST_Type) GetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD2() uint32 { + return (volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg) & 0xff00) >> 8 +} +func (o *I3C_MST_Type) SetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD3(value uint32) { + volatile.StoreUint32(&o.SCL_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_Type) GetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD3() uint32 { + return (volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_Type) SetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD4(value uint32) { + volatile.StoreUint32(&o.SCL_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg)&^(0xff000000)|value<<24) +} +func (o *I3C_MST_Type) GetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD4() uint32 { + return (volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg) & 0xff000000) >> 24 +} + +// I3C_MST.SDA_SAMPLE_TIME: NA +func (o *I3C_MST_Type) SetSDA_SAMPLE_TIME_REG_SDA_OD_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE_TIME.Reg, volatile.LoadUint32(&o.SDA_SAMPLE_TIME.Reg)&^(0x1ff)|value) +} +func (o *I3C_MST_Type) GetSDA_SAMPLE_TIME_REG_SDA_OD_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE_TIME.Reg) & 0x1ff +} +func (o *I3C_MST_Type) SetSDA_SAMPLE_TIME_REG_SDA_PP_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE_TIME.Reg, volatile.LoadUint32(&o.SDA_SAMPLE_TIME.Reg)&^(0x3e00)|value<<9) +} +func (o *I3C_MST_Type) GetSDA_SAMPLE_TIME_REG_SDA_PP_SAMPLE_TIME() uint32 { + return (volatile.LoadUint32(&o.SDA_SAMPLE_TIME.Reg) & 0x3e00) >> 9 +} + +// I3C_MST.SDA_HOLD_TIME: NA +func (o *I3C_MST_Type) SetSDA_HOLD_TIME_REG_SDA_OD_TX_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD_TIME.Reg, volatile.LoadUint32(&o.SDA_HOLD_TIME.Reg)&^(0x1ff)|value) +} +func (o *I3C_MST_Type) GetSDA_HOLD_TIME_REG_SDA_OD_TX_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD_TIME.Reg) & 0x1ff +} +func (o *I3C_MST_Type) SetSDA_HOLD_TIME_REG_SDA_PP_TX_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD_TIME.Reg, volatile.LoadUint32(&o.SDA_HOLD_TIME.Reg)&^(0x3e00)|value<<9) +} +func (o *I3C_MST_Type) GetSDA_HOLD_TIME_REG_SDA_PP_TX_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SDA_HOLD_TIME.Reg) & 0x3e00) >> 9 +} + +// I3C_MST.SCL_START_HOLD: NA +func (o *I3C_MST_Type) SetSCL_START_HOLD_REG_SCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I3C_MST_Type) GetSCL_START_HOLD_REG_SCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff +} +func (o *I3C_MST_Type) SetSCL_START_HOLD_REG_START_DET_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x600)|value<<9) +} +func (o *I3C_MST_Type) GetSCL_START_HOLD_REG_START_DET_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x600) >> 9 +} + +// I3C_MST.SCL_RSTART_SETUP: NA +func (o *I3C_MST_Type) SetSCL_RSTART_SETUP_REG_SCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I3C_MST_Type) GetSCL_RSTART_SETUP_REG_SCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// I3C_MST.SCL_STOP_HOLD: NA +func (o *I3C_MST_Type) SetSCL_STOP_HOLD_REG_SCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I3C_MST_Type) GetSCL_STOP_HOLD_REG_SCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff +} + +// I3C_MST.SCL_STOP_SETUP: NA +func (o *I3C_MST_Type) SetSCL_STOP_SETUP_REG_SCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I3C_MST_Type) GetSCL_STOP_SETUP_REG_SCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff +} + +// I3C_MST.BUS_FREE_TIME: NA +func (o *I3C_MST_Type) SetBUS_FREE_TIME_REG_BUS_FREE_TIME(value uint32) { + volatile.StoreUint32(&o.BUS_FREE_TIME.Reg, volatile.LoadUint32(&o.BUS_FREE_TIME.Reg)&^(0xffff)|value) +} +func (o *I3C_MST_Type) GetBUS_FREE_TIME_REG_BUS_FREE_TIME() uint32 { + return volatile.LoadUint32(&o.BUS_FREE_TIME.Reg) & 0xffff +} + +// I3C_MST.SCL_TERMN_T_EXT_LOW_TIME: NA +func (o *I3C_MST_Type) SetSCL_TERMN_T_EXT_LOW_TIME_REG_I3C_MST_TERMN_T_EXT_LOW_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_TERMN_T_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_TERMN_T_EXT_LOW_TIME.Reg)&^(0xff)|value) +} +func (o *I3C_MST_Type) GetSCL_TERMN_T_EXT_LOW_TIME_REG_I3C_MST_TERMN_T_EXT_LOW_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_TERMN_T_EXT_LOW_TIME.Reg) & 0xff +} + +// I3C_MST.VER_ID: NA +func (o *I3C_MST_Type) SetVER_ID(value uint32) { + volatile.StoreUint32(&o.VER_ID.Reg, value) +} +func (o *I3C_MST_Type) GetVER_ID() uint32 { + return volatile.LoadUint32(&o.VER_ID.Reg) +} + +// I3C_MST.VER_TYPE: NA +func (o *I3C_MST_Type) SetVER_TYPE(value uint32) { + volatile.StoreUint32(&o.VER_TYPE.Reg, value) +} +func (o *I3C_MST_Type) GetVER_TYPE() uint32 { + return volatile.LoadUint32(&o.VER_TYPE.Reg) +} + +// I3C_MST.FPGA_DEBUG_PROBE: NA +func (o *I3C_MST_Type) SetFPGA_DEBUG_PROBE(value uint32) { + volatile.StoreUint32(&o.FPGA_DEBUG_PROBE.Reg, value) +} +func (o *I3C_MST_Type) GetFPGA_DEBUG_PROBE() uint32 { + return volatile.LoadUint32(&o.FPGA_DEBUG_PROBE.Reg) +} + +// I3C_MST.RND_ECO_CS: NA +func (o *I3C_MST_Type) SetRND_ECO_CS_REG_RND_ECO_EN(value uint32) { + volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x1)|value) +} +func (o *I3C_MST_Type) GetRND_ECO_CS_REG_RND_ECO_EN() uint32 { + return volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x1 +} +func (o *I3C_MST_Type) SetRND_ECO_CS_RND_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *I3C_MST_Type) GetRND_ECO_CS_RND_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x2) >> 1 +} + +// I3C_MST.RND_ECO_LOW: NA +func (o *I3C_MST_Type) SetRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value) +} +func (o *I3C_MST_Type) GetRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RND_ECO_LOW.Reg) +} + +// I3C_MST.RND_ECO_HIGH: NA +func (o *I3C_MST_Type) SetRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value) +} +func (o *I3C_MST_Type) GetRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg) +} + +// I3C_MST_MEM Peripheral +type I3C_MST_MEM_Type struct { + _ [8]byte + COMMAND_BUF_PORT volatile.Register32 // 0x8 + RESPONSE_BUF_PORT volatile.Register32 // 0xC + RX_DATA_PORT volatile.Register32 // 0x10 + TX_DATA_PORT volatile.Register32 // 0x14 + IBI_STATUS_BUF volatile.Register32 // 0x18 + _ [36]byte + IBI_DATA_BUF volatile.Register32 // 0x40 + _ [124]byte + DEV_ADDR_TABLE1_LOC volatile.Register32 // 0xC0 + DEV_ADDR_TABLE2_LOC volatile.Register32 // 0xC4 + DEV_ADDR_TABLE3_LOC volatile.Register32 // 0xC8 + DEV_ADDR_TABLE4_LOC volatile.Register32 // 0xCC + DEV_ADDR_TABLE5_LOC volatile.Register32 // 0xD0 + DEV_ADDR_TABLE6_LOC volatile.Register32 // 0xD4 + DEV_ADDR_TABLE7_LOC volatile.Register32 // 0xD8 + DEV_ADDR_TABLE8_LOC volatile.Register32 // 0xDC + DEV_ADDR_TABLE9_LOC volatile.Register32 // 0xE0 + DEV_ADDR_TABLE10_LOC volatile.Register32 // 0xE4 + DEV_ADDR_TABLE11_LOC volatile.Register32 // 0xE8 + DEV_ADDR_TABLE12_LOC volatile.Register32 // 0xEC + _ [16]byte + DEV_CHAR_TABLE1_LOC1 volatile.Register32 // 0x100 + DEV_CHAR_TABLE1_LOC2 volatile.Register32 // 0x104 + DEV_CHAR_TABLE1_LOC3 volatile.Register32 // 0x108 + DEV_CHAR_TABLE1_LOC4 volatile.Register32 // 0x10C + DEV_CHAR_TABLE2_LOC1 volatile.Register32 // 0x110 + DEV_CHAR_TABLE2_LOC2 volatile.Register32 // 0x114 + DEV_CHAR_TABLE2_LOC3 volatile.Register32 // 0x118 + DEV_CHAR_TABLE2_LOC4 volatile.Register32 // 0x11C + DEV_CHAR_TABLE3_LOC1 volatile.Register32 // 0x120 + DEV_CHAR_TABLE3_LOC2 volatile.Register32 // 0x124 + DEV_CHAR_TABLE3_LOC3 volatile.Register32 // 0x128 + DEV_CHAR_TABLE3_LOC4 volatile.Register32 // 0x12C + DEV_CHAR_TABLE4_LOC1 volatile.Register32 // 0x130 + DEV_CHAR_TABLE4_LOC2 volatile.Register32 // 0x134 + DEV_CHAR_TABLE4_LOC3 volatile.Register32 // 0x138 + DEV_CHAR_TABLE4_LOC4 volatile.Register32 // 0x13C + DEV_CHAR_TABLE5_LOC1 volatile.Register32 // 0x140 + DEV_CHAR_TABLE5_LOC2 volatile.Register32 // 0x144 + DEV_CHAR_TABLE5_LOC3 volatile.Register32 // 0x148 + DEV_CHAR_TABLE5_LOC4 volatile.Register32 // 0x14C + DEV_CHAR_TABLE6_LOC1 volatile.Register32 // 0x150 + DEV_CHAR_TABLE6_LOC2 volatile.Register32 // 0x154 + DEV_CHAR_TABLE6_LOC3 volatile.Register32 // 0x158 + DEV_CHAR_TABLE6_LOC4 volatile.Register32 // 0x15C + DEV_CHAR_TABLE7_LOC1 volatile.Register32 // 0x160 + DEV_CHAR_TABLE7_LOC2 volatile.Register32 // 0x164 + DEV_CHAR_TABLE7_LOC3 volatile.Register32 // 0x168 + DEV_CHAR_TABLE7_LOC4 volatile.Register32 // 0x16C + DEV_CHAR_TABLE8_LOC1 volatile.Register32 // 0x170 + DEV_CHAR_TABLE8_LOC2 volatile.Register32 // 0x174 + DEV_CHAR_TABLE8_LOC3 volatile.Register32 // 0x178 + DEV_CHAR_TABLE8_LOC4 volatile.Register32 // 0x17C + DEV_CHAR_TABLE9_LOC1 volatile.Register32 // 0x180 + DEV_CHAR_TABLE9_LOC2 volatile.Register32 // 0x184 + DEV_CHAR_TABLE9_LOC3 volatile.Register32 // 0x188 + DEV_CHAR_TABLE9_LOC4 volatile.Register32 // 0x18C + DEV_CHAR_TABLE10_LOC1 volatile.Register32 // 0x190 + DEV_CHAR_TABLE10_LOC2 volatile.Register32 // 0x194 + DEV_CHAR_TABLE10_LOC3 volatile.Register32 // 0x198 + DEV_CHAR_TABLE10_LOC4 volatile.Register32 // 0x19C + DEV_CHAR_TABLE11_LOC1 volatile.Register32 // 0x1A0 + DEV_CHAR_TABLE11_LOC2 volatile.Register32 // 0x1A4 + DEV_CHAR_TABLE11_LOC3 volatile.Register32 // 0x1A8 + DEV_CHAR_TABLE11_LOC4 volatile.Register32 // 0x1AC + DEV_CHAR_TABLE12_LOC1 volatile.Register32 // 0x1B0 + DEV_CHAR_TABLE12_LOC2 volatile.Register32 // 0x1B4 + DEV_CHAR_TABLE12_LOC3 volatile.Register32 // 0x1B8 + DEV_CHAR_TABLE12_LOC4 volatile.Register32 // 0x1BC +} + +// I3C_MST_MEM.COMMAND_BUF_PORT: NA +func (o *I3C_MST_MEM_Type) SetCOMMAND_BUF_PORT(value uint32) { + volatile.StoreUint32(&o.COMMAND_BUF_PORT.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetCOMMAND_BUF_PORT() uint32 { + return volatile.LoadUint32(&o.COMMAND_BUF_PORT.Reg) +} + +// I3C_MST_MEM.RESPONSE_BUF_PORT: NA +func (o *I3C_MST_MEM_Type) SetRESPONSE_BUF_PORT(value uint32) { + volatile.StoreUint32(&o.RESPONSE_BUF_PORT.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetRESPONSE_BUF_PORT() uint32 { + return volatile.LoadUint32(&o.RESPONSE_BUF_PORT.Reg) +} + +// I3C_MST_MEM.RX_DATA_PORT: NA +func (o *I3C_MST_MEM_Type) SetRX_DATA_PORT(value uint32) { + volatile.StoreUint32(&o.RX_DATA_PORT.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetRX_DATA_PORT() uint32 { + return volatile.LoadUint32(&o.RX_DATA_PORT.Reg) +} + +// I3C_MST_MEM.TX_DATA_PORT: NA +func (o *I3C_MST_MEM_Type) SetTX_DATA_PORT(value uint32) { + volatile.StoreUint32(&o.TX_DATA_PORT.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetTX_DATA_PORT() uint32 { + return volatile.LoadUint32(&o.TX_DATA_PORT.Reg) +} + +// I3C_MST_MEM.IBI_STATUS_BUF: In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data) +func (o *I3C_MST_MEM_Type) SetIBI_STATUS_BUF_DATA_LENGTH(value uint32) { + volatile.StoreUint32(&o.IBI_STATUS_BUF.Reg, volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg)&^(0xff)|value) +} +func (o *I3C_MST_MEM_Type) GetIBI_STATUS_BUF_DATA_LENGTH() uint32 { + return volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg) & 0xff +} +func (o *I3C_MST_MEM_Type) SetIBI_STATUS_BUF_IBI_ID(value uint32) { + volatile.StoreUint32(&o.IBI_STATUS_BUF.Reg, volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg)&^(0xff00)|value<<8) +} +func (o *I3C_MST_MEM_Type) GetIBI_STATUS_BUF_IBI_ID() uint32 { + return (volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg) & 0xff00) >> 8 +} +func (o *I3C_MST_MEM_Type) SetIBI_STATUS_BUF_IBI_STS(value uint32) { + volatile.StoreUint32(&o.IBI_STATUS_BUF.Reg, volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg)&^(0x10000000)|value<<28) +} +func (o *I3C_MST_MEM_Type) GetIBI_STATUS_BUF_IBI_STS() uint32 { + return (volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg) & 0x10000000) >> 28 +} + +// I3C_MST_MEM.IBI_DATA_BUF: NA +func (o *I3C_MST_MEM_Type) SetIBI_DATA_BUF(value uint32) { + volatile.StoreUint32(&o.IBI_DATA_BUF.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetIBI_DATA_BUF() uint32 { + return volatile.LoadUint32(&o.IBI_DATA_BUF.Reg) +} + +// I3C_MST_MEM.DEV_ADDR_TABLE1_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE1_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE1_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE1_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE1_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE2_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE2_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE2_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE2_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE2_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE3_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE3_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE3_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE3_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE3_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE4_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE4_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE4_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE4_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE4_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE5_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE5_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE5_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE5_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE5_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE6_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE6_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE6_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE6_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE6_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE7_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE7_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE7_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE7_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE7_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE8_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE8_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE8_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE8_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE8_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE9_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE9_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE9_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE9_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE9_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE10_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE10_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE10_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE10_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE10_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE11_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE11_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE11_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE11_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE11_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_ADDR_TABLE12_LOC: NA +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_STATIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE12_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg)&^(0x7f)|value) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_STATIC_ADDR() uint32 { + return volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg) & 0x7f +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_DYNAMIC_ADDR(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE12_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_DYNAMIC_ADDR() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg) & 0xff0000) >> 16 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_NACK_RETRY_CNT(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE12_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg)&^(0x60000000)|value<<29) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_NACK_RETRY_CNT() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg) & 0x60000000) >> 29 +} +func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_I2C(value uint32) { + volatile.StoreUint32(&o.DEV_ADDR_TABLE12_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_I2C() uint32 { + return (volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg) & 0x80000000) >> 31 +} + +// I3C_MST_MEM.DEV_CHAR_TABLE1_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE1_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE1_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE1_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE1_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE1_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE1_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE1_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE1_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE1_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE1_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE1_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE1_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE1_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE1_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE1_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE1_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE1_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE1_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE1_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE2_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE2_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE2_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE2_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE2_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE2_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE2_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE2_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE2_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE2_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE2_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE2_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE2_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE2_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE2_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE2_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE2_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE2_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE2_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE2_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE3_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE3_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE3_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE3_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE3_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE3_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE3_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE3_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE3_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE3_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE3_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE3_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE3_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE3_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE3_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE3_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE3_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE3_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE3_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE3_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE4_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE4_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE4_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE4_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE4_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE4_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE4_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE4_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE4_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE4_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE4_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE4_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE4_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE4_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE4_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE4_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE4_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE4_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE4_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE4_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE5_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE5_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE5_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE5_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE5_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE5_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE5_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE5_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE5_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE5_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE5_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE5_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE5_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE5_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE5_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE5_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE5_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE5_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE5_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE5_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE6_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE6_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE6_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE6_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE6_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE6_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE6_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE6_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE6_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE6_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE6_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE6_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE6_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE6_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE6_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE6_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE6_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE6_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE6_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE6_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE7_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE7_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE7_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE7_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE7_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE7_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE7_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE7_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE7_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE7_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE7_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE7_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE7_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE7_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE7_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE7_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE7_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE7_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE7_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE7_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE8_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE8_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE8_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE8_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE8_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE8_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE8_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE8_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE8_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE8_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE8_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE8_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE8_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE8_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE8_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE8_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE8_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE8_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE8_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE8_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE9_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE9_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE9_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE9_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE9_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE9_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE9_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE9_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE9_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE9_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE9_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE9_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE9_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE9_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE9_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE9_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE9_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE9_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE9_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE9_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE10_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE10_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE10_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE10_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE10_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE10_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE10_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE10_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE10_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE10_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE10_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE10_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE10_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE10_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE10_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE10_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE10_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE10_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE10_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE10_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE11_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE11_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE11_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE11_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE11_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE11_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE11_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE11_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE11_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE11_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE11_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE11_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE11_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE11_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE11_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE11_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE11_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE11_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE11_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE11_LOC4.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE12_LOC1: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE12_LOC1(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE12_LOC1.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE12_LOC1() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE12_LOC1.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE12_LOC2: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE12_LOC2(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE12_LOC2.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE12_LOC2() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE12_LOC2.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE12_LOC3: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE12_LOC3(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE12_LOC3.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE12_LOC3() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE12_LOC3.Reg) +} + +// I3C_MST_MEM.DEV_CHAR_TABLE12_LOC4: NA +func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE12_LOC4(value uint32) { + volatile.StoreUint32(&o.DEV_CHAR_TABLE12_LOC4.Reg, value) +} +func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE12_LOC4() uint32 { + return volatile.LoadUint32(&o.DEV_CHAR_TABLE12_LOC4.Reg) +} + +// I3C Controller (Slave) +type I3C_SLV_Type struct { + _ [4]byte + CONFIG volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + CTRL volatile.Register32 // 0xC + INTSET volatile.Register32 // 0x10 + INTCLR volatile.Register32 // 0x14 + INTMASKED volatile.Register32 // 0x18 + _ [16]byte + DATACTRL volatile.Register32 // 0x2C + WDATAB volatile.Register32 // 0x30 + WDATABE volatile.Register32 // 0x34 + _ [8]byte + RDARAB volatile.Register32 // 0x40 + _ [4]byte + RDATAH volatile.Register32 // 0x48 + _ [16]byte + CAPABILITIES2 volatile.Register32 // 0x5C + CAPABILITIES volatile.Register32 // 0x60 + _ [8]byte + IDPARTNO volatile.Register32 // 0x6C + IDEXT volatile.Register32 // 0x70 + VENDORID volatile.Register32 // 0x74 +} + +// I3C_SLV.CONFIG: NA +func (o *I3C_SLV_Type) SetCONFIG_SLVENA(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1)|value) +} +func (o *I3C_SLV_Type) GetCONFIG_SLVENA() uint32 { + return volatile.LoadUint32(&o.CONFIG.Reg) & 0x1 +} +func (o *I3C_SLV_Type) SetCONFIG_NACK(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *I3C_SLV_Type) GetCONFIG_NACK() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x2) >> 1 +} +func (o *I3C_SLV_Type) SetCONFIG_MATCHSS(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x4)|value<<2) +} +func (o *I3C_SLV_Type) GetCONFIG_MATCHSS() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x4) >> 2 +} +func (o *I3C_SLV_Type) SetCONFIG_S0IGNORE(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8)|value<<3) +} +func (o *I3C_SLV_Type) GetCONFIG_S0IGNORE() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8) >> 3 +} +func (o *I3C_SLV_Type) SetCONFIG_DDROK(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x10)|value<<4) +} +func (o *I3C_SLV_Type) GetCONFIG_DDROK() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x10) >> 4 +} +func (o *I3C_SLV_Type) SetCONFIG_IDRAND(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x100)|value<<8) +} +func (o *I3C_SLV_Type) GetCONFIG_IDRAND() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x100) >> 8 +} +func (o *I3C_SLV_Type) SetCONFIG_OFFLINE(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *I3C_SLV_Type) GetCONFIG_OFFLINE() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x200) >> 9 +} +func (o *I3C_SLV_Type) SetCONFIG_BAMATCH(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0xff0000)|value<<16) +} +func (o *I3C_SLV_Type) GetCONFIG_BAMATCH() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0xff0000) >> 16 +} +func (o *I3C_SLV_Type) SetCONFIG_SADDR(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0xfe000000)|value<<25) +} +func (o *I3C_SLV_Type) GetCONFIG_SADDR() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0xfe000000) >> 25 +} + +// I3C_SLV.STATUS: NA +func (o *I3C_SLV_Type) SetSTATUS_STNOTSTOP(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *I3C_SLV_Type) GetSTATUS_STNOTSTOP() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *I3C_SLV_Type) SetSTATUS_STMSG(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I3C_SLV_Type) GetSTATUS_STMSG() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *I3C_SLV_Type) SetSTATUS_STCCCH(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I3C_SLV_Type) GetSTATUS_STCCCH() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *I3C_SLV_Type) SetSTATUS_STREQRD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I3C_SLV_Type) GetSTATUS_STREQRD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *I3C_SLV_Type) SetSTATUS_STREQWR(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I3C_SLV_Type) GetSTATUS_STREQWR() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *I3C_SLV_Type) SetSTATUS_STDAA(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I3C_SLV_Type) GetSTATUS_STDAA() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *I3C_SLV_Type) SetSTATUS_STHDR(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I3C_SLV_Type) GetSTATUS_STHDR() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *I3C_SLV_Type) SetSTATUS_START(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I3C_SLV_Type) GetSTATUS_START() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *I3C_SLV_Type) SetSTATUS_MATCHED(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I3C_SLV_Type) GetSTATUS_MATCHED() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *I3C_SLV_Type) SetSTATUS_STOP(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I3C_SLV_Type) GetSTATUS_STOP() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400) >> 10 +} +func (o *I3C_SLV_Type) SetSTATUS_RXPEND(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I3C_SLV_Type) GetSTATUS_RXPEND() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x800) >> 11 +} +func (o *I3C_SLV_Type) SetSTATUS_TXNOTFULL(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I3C_SLV_Type) GetSTATUS_TXNOTFULL() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1000) >> 12 +} +func (o *I3C_SLV_Type) SetSTATUS_DACHG(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *I3C_SLV_Type) GetSTATUS_DACHG() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *I3C_SLV_Type) SetSTATUS_CCC(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *I3C_SLV_Type) GetSTATUS_CCC() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *I3C_SLV_Type) SetSTATUS_ERRWARN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *I3C_SLV_Type) GetSTATUS_ERRWARN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *I3C_SLV_Type) SetSTATUS_HDRMATCH(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *I3C_SLV_Type) GetSTATUS_HDRMATCH() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10000) >> 16 +} + +// I3C_SLV.CTRL: NA +func (o *I3C_SLV_Type) SetCTRL_SLV_EVENT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3)|value) +} +func (o *I3C_SLV_Type) GetCTRL_SLV_EVENT() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x3 +} +func (o *I3C_SLV_Type) SetCTRL_EXTDATA(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I3C_SLV_Type) GetCTRL_EXTDATA() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *I3C_SLV_Type) SetCTRL_MAPIDX(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xf0)|value<<4) +} +func (o *I3C_SLV_Type) GetCTRL_MAPIDX() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xf0) >> 4 +} +func (o *I3C_SLV_Type) SetCTRL_IBIDATA(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *I3C_SLV_Type) GetCTRL_IBIDATA() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xff00) >> 8 +} +func (o *I3C_SLV_Type) SetCTRL_PENDINT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I3C_SLV_Type) GetCTRL_PENDINT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xf0000) >> 16 +} +func (o *I3C_SLV_Type) SetCTRL_ACTSTATE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x300000)|value<<20) +} +func (o *I3C_SLV_Type) GetCTRL_ACTSTATE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x300000) >> 20 +} +func (o *I3C_SLV_Type) SetCTRL_VENDINFO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xff000000)|value<<24) +} +func (o *I3C_SLV_Type) GetCTRL_VENDINFO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xff000000) >> 24 +} + +// I3C_SLV.INTSET: INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor) +func (o *I3C_SLV_Type) SetINTSET_STOP_ENA(value uint32) { + volatile.StoreUint32(&o.INTSET.Reg, volatile.LoadUint32(&o.INTSET.Reg)&^(0x400)|value<<10) +} +func (o *I3C_SLV_Type) GetINTSET_STOP_ENA() uint32 { + return (volatile.LoadUint32(&o.INTSET.Reg) & 0x400) >> 10 +} +func (o *I3C_SLV_Type) SetINTSET_RXPEND_ENA(value uint32) { + volatile.StoreUint32(&o.INTSET.Reg, volatile.LoadUint32(&o.INTSET.Reg)&^(0x800)|value<<11) +} +func (o *I3C_SLV_Type) GetINTSET_RXPEND_ENA() uint32 { + return (volatile.LoadUint32(&o.INTSET.Reg) & 0x800) >> 11 +} +func (o *I3C_SLV_Type) SetINTSET_TXSEND_ENA(value uint32) { + volatile.StoreUint32(&o.INTSET.Reg, volatile.LoadUint32(&o.INTSET.Reg)&^(0x1000)|value<<12) +} +func (o *I3C_SLV_Type) GetINTSET_TXSEND_ENA() uint32 { + return (volatile.LoadUint32(&o.INTSET.Reg) & 0x1000) >> 12 +} + +// I3C_SLV.INTCLR: NA +func (o *I3C_SLV_Type) SetINTCLR_STOP_CLR(value uint32) { + volatile.StoreUint32(&o.INTCLR.Reg, volatile.LoadUint32(&o.INTCLR.Reg)&^(0x400)|value<<10) +} +func (o *I3C_SLV_Type) GetINTCLR_STOP_CLR() uint32 { + return (volatile.LoadUint32(&o.INTCLR.Reg) & 0x400) >> 10 +} +func (o *I3C_SLV_Type) SetINTCLR_RXPEND_CLR(value uint32) { + volatile.StoreUint32(&o.INTCLR.Reg, volatile.LoadUint32(&o.INTCLR.Reg)&^(0x800)|value<<11) +} +func (o *I3C_SLV_Type) GetINTCLR_RXPEND_CLR() uint32 { + return (volatile.LoadUint32(&o.INTCLR.Reg) & 0x800) >> 11 +} +func (o *I3C_SLV_Type) SetINTCLR_TXSEND_CLR(value uint32) { + volatile.StoreUint32(&o.INTCLR.Reg, volatile.LoadUint32(&o.INTCLR.Reg)&^(0x1000)|value<<12) +} +func (o *I3C_SLV_Type) GetINTCLR_TXSEND_CLR() uint32 { + return (volatile.LoadUint32(&o.INTCLR.Reg) & 0x1000) >> 12 +} + +// I3C_SLV.INTMASKED: NA +func (o *I3C_SLV_Type) SetINTMASKED_STOP_MASK(value uint32) { + volatile.StoreUint32(&o.INTMASKED.Reg, volatile.LoadUint32(&o.INTMASKED.Reg)&^(0x400)|value<<10) +} +func (o *I3C_SLV_Type) GetINTMASKED_STOP_MASK() uint32 { + return (volatile.LoadUint32(&o.INTMASKED.Reg) & 0x400) >> 10 +} +func (o *I3C_SLV_Type) SetINTMASKED_RXPEND_MASK(value uint32) { + volatile.StoreUint32(&o.INTMASKED.Reg, volatile.LoadUint32(&o.INTMASKED.Reg)&^(0x800)|value<<11) +} +func (o *I3C_SLV_Type) GetINTMASKED_RXPEND_MASK() uint32 { + return (volatile.LoadUint32(&o.INTMASKED.Reg) & 0x800) >> 11 +} +func (o *I3C_SLV_Type) SetINTMASKED_TXSEND_MASK(value uint32) { + volatile.StoreUint32(&o.INTMASKED.Reg, volatile.LoadUint32(&o.INTMASKED.Reg)&^(0x1000)|value<<12) +} +func (o *I3C_SLV_Type) GetINTMASKED_TXSEND_MASK() uint32 { + return (volatile.LoadUint32(&o.INTMASKED.Reg) & 0x1000) >> 12 +} + +// I3C_SLV.DATACTRL: NA +func (o *I3C_SLV_Type) SetDATACTRL_FLUSHTB(value uint32) { + volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x1)|value) +} +func (o *I3C_SLV_Type) GetDATACTRL_FLUSHTB() uint32 { + return volatile.LoadUint32(&o.DATACTRL.Reg) & 0x1 +} +func (o *I3C_SLV_Type) SetDATACTRL_FLUSHFB(value uint32) { + volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x2)|value<<1) +} +func (o *I3C_SLV_Type) GetDATACTRL_FLUSHFB() uint32 { + return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x2) >> 1 +} +func (o *I3C_SLV_Type) SetDATACTRL_UNLOCK(value uint32) { + volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x8)|value<<3) +} +func (o *I3C_SLV_Type) GetDATACTRL_UNLOCK() uint32 { + return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x8) >> 3 +} +func (o *I3C_SLV_Type) SetDATACTRL_TXTRIG(value uint32) { + volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x30)|value<<4) +} +func (o *I3C_SLV_Type) GetDATACTRL_TXTRIG() uint32 { + return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x30) >> 4 +} +func (o *I3C_SLV_Type) SetDATACTRL_RXTRIG(value uint32) { + volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0xc0)|value<<6) +} +func (o *I3C_SLV_Type) GetDATACTRL_RXTRIG() uint32 { + return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0xc0) >> 6 +} +func (o *I3C_SLV_Type) SetDATACTRL_TXCOUNT(value uint32) { + volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x1f0000)|value<<16) +} +func (o *I3C_SLV_Type) GetDATACTRL_TXCOUNT() uint32 { + return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x1f0000) >> 16 +} +func (o *I3C_SLV_Type) SetDATACTRL_RXCOUNT(value uint32) { + volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x1f000000)|value<<24) +} +func (o *I3C_SLV_Type) GetDATACTRL_RXCOUNT() uint32 { + return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x1f000000) >> 24 +} +func (o *I3C_SLV_Type) SetDATACTRL_TXFULL(value uint32) { + volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *I3C_SLV_Type) GetDATACTRL_TXFULL() uint32 { + return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x40000000) >> 30 +} +func (o *I3C_SLV_Type) SetDATACTRL_RXEMPTY(value uint32) { + volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *I3C_SLV_Type) GetDATACTRL_RXEMPTY() uint32 { + return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x80000000) >> 31 +} + +// I3C_SLV.WDATAB: NA +func (o *I3C_SLV_Type) SetWDATAB(value uint32) { + volatile.StoreUint32(&o.WDATAB.Reg, volatile.LoadUint32(&o.WDATAB.Reg)&^(0xff)|value) +} +func (o *I3C_SLV_Type) GetWDATAB() uint32 { + return volatile.LoadUint32(&o.WDATAB.Reg) & 0xff +} +func (o *I3C_SLV_Type) SetWDATAB_WDATA_END(value uint32) { + volatile.StoreUint32(&o.WDATAB.Reg, volatile.LoadUint32(&o.WDATAB.Reg)&^(0x100)|value<<8) +} +func (o *I3C_SLV_Type) GetWDATAB_WDATA_END() uint32 { + return (volatile.LoadUint32(&o.WDATAB.Reg) & 0x100) >> 8 +} + +// I3C_SLV.WDATABE: NA +func (o *I3C_SLV_Type) SetWDATABE(value uint32) { + volatile.StoreUint32(&o.WDATABE.Reg, volatile.LoadUint32(&o.WDATABE.Reg)&^(0xff)|value) +} +func (o *I3C_SLV_Type) GetWDATABE() uint32 { + return volatile.LoadUint32(&o.WDATABE.Reg) & 0xff +} + +// I3C_SLV.RDARAB: Read Byte Data (from-bus) register +func (o *I3C_SLV_Type) SetRDARAB_DATA0(value uint32) { + volatile.StoreUint32(&o.RDARAB.Reg, volatile.LoadUint32(&o.RDARAB.Reg)&^(0xff)|value) +} +func (o *I3C_SLV_Type) GetRDARAB_DATA0() uint32 { + return volatile.LoadUint32(&o.RDARAB.Reg) & 0xff +} + +// I3C_SLV.RDATAH: Read Half-word Data (from-bus) register +func (o *I3C_SLV_Type) SetRDATAH_DATA_LSB(value uint32) { + volatile.StoreUint32(&o.RDATAH.Reg, volatile.LoadUint32(&o.RDATAH.Reg)&^(0xff)|value) +} +func (o *I3C_SLV_Type) GetRDATAH_DATA_LSB() uint32 { + return volatile.LoadUint32(&o.RDATAH.Reg) & 0xff +} +func (o *I3C_SLV_Type) SetRDATAH_DATA_MSB(value uint32) { + volatile.StoreUint32(&o.RDATAH.Reg, volatile.LoadUint32(&o.RDATAH.Reg)&^(0xff00)|value<<8) +} +func (o *I3C_SLV_Type) GetRDATAH_DATA_MSB() uint32 { + return (volatile.LoadUint32(&o.RDATAH.Reg) & 0xff00) >> 8 +} + +// I3C_SLV.CAPABILITIES2: NA +func (o *I3C_SLV_Type) SetCAPABILITIES2(value uint32) { + volatile.StoreUint32(&o.CAPABILITIES2.Reg, value) +} +func (o *I3C_SLV_Type) GetCAPABILITIES2() uint32 { + return volatile.LoadUint32(&o.CAPABILITIES2.Reg) +} + +// I3C_SLV.CAPABILITIES: NA +func (o *I3C_SLV_Type) SetCAPABILITIES(value uint32) { + volatile.StoreUint32(&o.CAPABILITIES.Reg, value) +} +func (o *I3C_SLV_Type) GetCAPABILITIES() uint32 { + return volatile.LoadUint32(&o.CAPABILITIES.Reg) +} + +// I3C_SLV.IDPARTNO: NA +func (o *I3C_SLV_Type) SetIDPARTNO(value uint32) { + volatile.StoreUint32(&o.IDPARTNO.Reg, value) +} +func (o *I3C_SLV_Type) GetIDPARTNO() uint32 { + return volatile.LoadUint32(&o.IDPARTNO.Reg) +} + +// I3C_SLV.IDEXT: NA +func (o *I3C_SLV_Type) SetIDEXT(value uint32) { + volatile.StoreUint32(&o.IDEXT.Reg, value) +} +func (o *I3C_SLV_Type) GetIDEXT() uint32 { + return volatile.LoadUint32(&o.IDEXT.Reg) +} + +// I3C_SLV.VENDORID: NA +func (o *I3C_SLV_Type) SetVENDORID_VID(value uint32) { + volatile.StoreUint32(&o.VENDORID.Reg, volatile.LoadUint32(&o.VENDORID.Reg)&^(0x7fff)|value) +} +func (o *I3C_SLV_Type) GetVENDORID_VID() uint32 { + return volatile.LoadUint32(&o.VENDORID.Reg) & 0x7fff +} + +// AXI_ICM Peripheral +type ICM_AXI_Type struct { + VERID_FILEDS volatile.Register32 // 0x0 + HW_CFG volatile.Register32 // 0x4 + CMD volatile.Register32 // 0x8 + DATA volatile.Register32 // 0xC +} + +// ICM_AXI.VERID_FILEDS: NA +func (o *ICM_AXI_Type) SetVERID_FILEDS(value uint32) { + volatile.StoreUint32(&o.VERID_FILEDS.Reg, value) +} +func (o *ICM_AXI_Type) GetVERID_FILEDS() uint32 { + return volatile.LoadUint32(&o.VERID_FILEDS.Reg) +} + +// ICM_AXI.HW_CFG: NA +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_QOS_SUPPORT(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1)|value) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_QOS_SUPPORT() uint32 { + return volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_APB3_SUPPORT(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x2)|value<<1) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_APB3_SUPPORT() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x2) >> 1 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_AXI4_SUPPORT(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x4)|value<<2) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_AXI4_SUPPORT() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x4) >> 2 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_LOCK_EN(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x8)|value<<3) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_LOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x8) >> 3 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_TRUST_ZONE_EN(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x10)|value<<4) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_TRUST_ZONE_EN() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x10) >> 4 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_DECODER_TYPE(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x20)|value<<5) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_DECODER_TYPE() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x20) >> 5 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_REMAP_EN(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x40)|value<<6) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_REMAP_EN() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x40) >> 6 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x80)|value<<7) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x80) >> 7 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x100)|value<<8) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x100) >> 8 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1f000)|value<<12) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1f000) >> 12 +} +func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1f00000)|value<<20) +} +func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES() uint32 { + return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1f00000) >> 20 +} + +// ICM_AXI.CMD: NA +func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x7)|value) +} +func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_CMD() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x7 +} +func (o *ICM_AXI_Type) SetCMD_ICM_REG_RD_WR_CHAN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80)|value<<7) +} +func (o *ICM_AXI_Type) GetCMD_ICM_REG_RD_WR_CHAN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80) >> 7 +} +func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_MASTER_PORT(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0xf00)|value<<8) +} +func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_MASTER_PORT() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0xf00) >> 8 +} +func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_ERR_BIT(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_ERR_BIT() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10000000) >> 28 +} +func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_SOFT_RESET_BIT(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_SOFT_RESET_BIT() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29 +} +func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_RD_WR_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_RD_WR_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000000) >> 30 +} +func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_CMD_EN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_CMD_EN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31 +} + +// ICM_AXI.DATA: NA +func (o *ICM_AXI_Type) SetDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, value) +} +func (o *ICM_AXI_Type) GetDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) +} + +// Input/Output Multiplexer +type IO_MUX_Type struct { + _ [4]byte + GPIO0 volatile.Register32 // 0x4 + GPIO1 volatile.Register32 // 0x8 + GPIO2 volatile.Register32 // 0xC + GPIO3 volatile.Register32 // 0x10 + GPIO4 volatile.Register32 // 0x14 + GPIO5 volatile.Register32 // 0x18 + GPIO6 volatile.Register32 // 0x1C + GPIO7 volatile.Register32 // 0x20 + GPIO8 volatile.Register32 // 0x24 + GPIO9 volatile.Register32 // 0x28 + GPIO10 volatile.Register32 // 0x2C + GPIO11 volatile.Register32 // 0x30 + GPIO12 volatile.Register32 // 0x34 + GPIO13 volatile.Register32 // 0x38 + GPIO14 volatile.Register32 // 0x3C + GPIO15 volatile.Register32 // 0x40 + GPIO16 volatile.Register32 // 0x44 + GPIO17 volatile.Register32 // 0x48 + GPIO18 volatile.Register32 // 0x4C + GPIO19 volatile.Register32 // 0x50 + GPIO20 volatile.Register32 // 0x54 + GPIO21 volatile.Register32 // 0x58 + GPIO22 volatile.Register32 // 0x5C + GPIO23 volatile.Register32 // 0x60 + GPIO24 volatile.Register32 // 0x64 + GPIO25 volatile.Register32 // 0x68 + GPIO26 volatile.Register32 // 0x6C + GPIO27 volatile.Register32 // 0x70 + GPIO28 volatile.Register32 // 0x74 + GPIO29 volatile.Register32 // 0x78 + GPIO30 volatile.Register32 // 0x7C + GPIO31 volatile.Register32 // 0x80 + GPIO32 volatile.Register32 // 0x84 + GPIO33 volatile.Register32 // 0x88 + GPIO34 volatile.Register32 // 0x8C + GPIO35 volatile.Register32 // 0x90 + GPIO36 volatile.Register32 // 0x94 + GPIO37 volatile.Register32 // 0x98 + GPIO38 volatile.Register32 // 0x9C + GPIO39 volatile.Register32 // 0xA0 + GPIO40 volatile.Register32 // 0xA4 + GPIO41 volatile.Register32 // 0xA8 + GPIO42 volatile.Register32 // 0xAC + GPIO43 volatile.Register32 // 0xB0 + GPIO44 volatile.Register32 // 0xB4 + GPIO45 volatile.Register32 // 0xB8 + GPIO46 volatile.Register32 // 0xBC + GPIO47 volatile.Register32 // 0xC0 + GPIO48 volatile.Register32 // 0xC4 + GPIO49 volatile.Register32 // 0xC8 + GPIO50 volatile.Register32 // 0xCC + GPIO51 volatile.Register32 // 0xD0 + GPIO52 volatile.Register32 // 0xD4 + GPIO53 volatile.Register32 // 0xD8 + _ [40]byte + DATE volatile.Register32 // 0x104 +} + +// IO_MUX.GPIO0: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO1: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO2: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO3: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO4: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO5: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO6: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO7: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO8: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO8_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO8.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO8_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO8_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO9: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO9_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO9.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO9_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO9_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO10: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO10_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO10.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO10_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO10_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO11: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO11_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO11.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO11_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO11_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO12: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO12_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO12.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO12_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO12_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO13: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO13_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO13.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO13_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO13_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO14: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO14_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO14.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO14_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO14_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO15: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO15_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO15.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO15_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO15_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO15_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO15_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO16: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO16_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO16.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO16_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO16_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO16_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO16_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO17: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO17_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO17.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO17_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO17_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO17_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO17_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO18: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO18_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO18.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO18_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO18_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO18_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO18_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO19: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO19_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO19.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO19_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO19_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO20: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO20_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO20.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO20_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO20_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO21: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO21_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO21.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO21_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO21_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO22: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO22_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO22.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO22_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO22_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO22_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO22_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO23: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO23_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO23.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO23_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO23_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO23_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO23_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO24: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO24_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO24.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO24_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO24_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO24_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO24_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO25: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO25_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO25.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO25_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO25_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO25_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO25_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO26: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO26_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO26.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO26_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO26_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO26_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO26_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO27: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO27_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO27.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO27_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO27_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO27_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO27_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO28: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO28_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO28.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO28_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO28_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO28_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO28_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO29: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO29_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO29.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO29_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO29_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO29_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO29_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO30: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO30_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO30.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO30_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO30_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO30_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO30_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO31: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO31_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO31.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO31_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO31_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO31_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO31_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO32: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO32_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO32.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO32_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO32_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO32_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO32_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO33: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO33_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO33.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO33_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO33_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO33_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO33_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO34: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO34_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO34.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO34_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO34_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO34_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO34_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO35: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO35_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO35.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO35_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO35_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO35_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO35_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO36: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO36_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO36.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO36_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO36_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO36_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO36_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO37: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO37_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO37.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO37_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO37_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO37_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO37_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO38: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO38_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO38.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO38_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO38_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO38_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO38_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO39: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO39_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO39.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO39_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO39_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO39_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO39_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO40: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO40_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO40.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO40_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO40_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO40_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO40_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO41: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO41_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO41.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO41_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO41_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO41_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO41_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO42: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO42_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO42.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO42_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO42_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO42_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO42_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO43: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO43_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO43.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO43_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO43_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO43_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO43_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO44: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO44_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO44.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO44_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO44_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO44_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO44_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO45: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO45_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO45.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO45_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO45_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO45_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO45_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO46: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO46_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO46.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO46_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO46_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO46_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO46_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO47: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO47_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO47.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO47_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO47_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO47_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO47_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO47_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO47_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO47_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO47_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO47_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO47_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO47_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO47_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO47_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO47_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO47_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO47_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO47_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO48: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO48_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO48.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO48_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO48_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO48_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO48_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO48_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO48_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO48_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO48_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO48_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO48_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO48_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO48_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO48_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO48_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO48_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO48_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO48_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO49: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO49_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO49_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO49.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO49_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO49_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO49_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO49_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO49_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO49_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO49_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO49_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO49_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO49_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO49_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO49_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO49_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO49_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO49_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO49_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO49_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO49_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO49_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO49_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO49_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO49_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO50: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO50_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO50_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO50.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO50_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO50_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO50_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO50_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO50_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO50_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO50_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO50_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO50_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO50_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO50_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO50_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO50_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO50_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO50_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO50_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO50_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO50_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO50_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO50_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO50_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO50_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO51: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO51_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO51_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO51.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO51_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO51_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO51_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO51_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO51_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO51_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO51_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO51_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO51_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO51_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO51_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO51_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO51_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO51_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO51_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO51_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO51_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO51_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO51_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO51_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO51_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO51_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO52: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO52_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO52_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO52.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO52_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO52_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO52_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO52_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO52_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO52_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO52_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO52_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO52_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO52_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO52_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO52_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO52_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO52_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO52_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO52_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO52_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO52_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO52_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO52_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO52_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO52_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO53: IO_MUX Control Register +func (o *IO_MUX_Type) SetGPIO53_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO53_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO53.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO53_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO53_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO53_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO53_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO53_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO53_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO53_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO53_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO53_MCU_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x60)|value<<5) +} +func (o *IO_MUX_Type) GetGPIO53_MCU_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x60) >> 5 +} +func (o *IO_MUX_Type) SetGPIO53_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO53_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO53_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO53_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO53_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO53_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO53_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO53_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO53_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO53_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO53_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO53_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x8000) >> 15 +} + +// IO_MUX.DATE: iomux version +func (o *IO_MUX_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *IO_MUX_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// ISP Peripheral +type ISP_Type struct { + VER_DATE volatile.Register32 // 0x0 + CLK_EN volatile.Register32 // 0x4 + CNTL volatile.Register32 // 0x8 + HSYNC_CNT volatile.Register32 // 0xC + FRAME_CFG volatile.Register32 // 0x10 + CCM_COEF0 volatile.Register32 // 0x14 + CCM_COEF1 volatile.Register32 // 0x18 + CCM_COEF3 volatile.Register32 // 0x1C + CCM_COEF4 volatile.Register32 // 0x20 + CCM_COEF5 volatile.Register32 // 0x24 + BF_MATRIX_CTRL volatile.Register32 // 0x28 + BF_SIGMA volatile.Register32 // 0x2C + BF_GAU0 volatile.Register32 // 0x30 + BF_GAU1 volatile.Register32 // 0x34 + DPC_CTRL volatile.Register32 // 0x38 + DPC_CONF volatile.Register32 // 0x3C + DPC_MATRIX_CTRL volatile.Register32 // 0x40 + DPC_DEADPIX_CNT volatile.Register32 // 0x44 + LUT_CMD volatile.Register32 // 0x48 + LUT_WDATA volatile.Register32 // 0x4C + LUT_RDATA volatile.Register32 // 0x50 + LSC_TABLESIZE volatile.Register32 // 0x54 + DEMOSAIC_MATRIX_CTRL volatile.Register32 // 0x58 + DEMOSAIC_GRAD_RATIO volatile.Register32 // 0x5C + MEDIAN_MATRIX_CTRL volatile.Register32 // 0x60 + INT_RAW volatile.Register32 // 0x64 + INT_ST volatile.Register32 // 0x68 + INT_ENA volatile.Register32 // 0x6C + INT_CLR volatile.Register32 // 0x70 + GAMMA_CTRL volatile.Register32 // 0x74 + GAMMA_RY1 volatile.Register32 // 0x78 + GAMMA_RY2 volatile.Register32 // 0x7C + GAMMA_RY3 volatile.Register32 // 0x80 + GAMMA_RY4 volatile.Register32 // 0x84 + GAMMA_GY1 volatile.Register32 // 0x88 + GAMMA_GY2 volatile.Register32 // 0x8C + GAMMA_GY3 volatile.Register32 // 0x90 + GAMMA_GY4 volatile.Register32 // 0x94 + GAMMA_BY1 volatile.Register32 // 0x98 + GAMMA_BY2 volatile.Register32 // 0x9C + GAMMA_BY3 volatile.Register32 // 0xA0 + GAMMA_BY4 volatile.Register32 // 0xA4 + GAMMA_RX1 volatile.Register32 // 0xA8 + GAMMA_RX2 volatile.Register32 // 0xAC + GAMMA_GX1 volatile.Register32 // 0xB0 + GAMMA_GX2 volatile.Register32 // 0xB4 + GAMMA_BX1 volatile.Register32 // 0xB8 + GAMMA_BX2 volatile.Register32 // 0xBC + AE_CTRL volatile.Register32 // 0xC0 + AE_MONITOR volatile.Register32 // 0xC4 + AE_BX volatile.Register32 // 0xC8 + AE_BY volatile.Register32 // 0xCC + AE_WINPIXNUM volatile.Register32 // 0xD0 + AE_WIN_RECIPROCAL volatile.Register32 // 0xD4 + AE_BLOCK_MEAN_0 volatile.Register32 // 0xD8 + AE_BLOCK_MEAN_1 volatile.Register32 // 0xDC + AE_BLOCK_MEAN_2 volatile.Register32 // 0xE0 + AE_BLOCK_MEAN_3 volatile.Register32 // 0xE4 + AE_BLOCK_MEAN_4 volatile.Register32 // 0xE8 + AE_BLOCK_MEAN_5 volatile.Register32 // 0xEC + AE_BLOCK_MEAN_6 volatile.Register32 // 0xF0 + SHARP_CTRL0 volatile.Register32 // 0xF4 + SHARP_FILTER0 volatile.Register32 // 0xF8 + SHARP_FILTER1 volatile.Register32 // 0xFC + SHARP_FILTER2 volatile.Register32 // 0x100 + SHARP_MATRIX_CTRL volatile.Register32 // 0x104 + SHARP_CTRL1 volatile.Register32 // 0x108 + DMA_CNTL volatile.Register32 // 0x10C + DMA_RAW_DATA volatile.Register32 // 0x110 + CAM_CNTL volatile.Register32 // 0x114 + CAM_CONF volatile.Register32 // 0x118 + AF_CTRL0 volatile.Register32 // 0x11C + AF_CTRL1 volatile.Register32 // 0x120 + AF_GEN_TH_CTRL volatile.Register32 // 0x124 + AF_ENV_USER_TH_SUM volatile.Register32 // 0x128 + AF_ENV_USER_TH_LUM volatile.Register32 // 0x12C + AF_THRESHOLD volatile.Register32 // 0x130 + AF_HSCALE_A volatile.Register32 // 0x134 + AF_VSCALE_A volatile.Register32 // 0x138 + AF_HSCALE_B volatile.Register32 // 0x13C + AF_VSCALE_B volatile.Register32 // 0x140 + AF_HSCALE_C volatile.Register32 // 0x144 + AF_VSCALE_C volatile.Register32 // 0x148 + AF_SUM_A volatile.Register32 // 0x14C + AF_SUM_B volatile.Register32 // 0x150 + AF_SUM_C volatile.Register32 // 0x154 + AF_LUM_A volatile.Register32 // 0x158 + AF_LUM_B volatile.Register32 // 0x15C + AF_LUM_C volatile.Register32 // 0x160 + AWB_MODE volatile.Register32 // 0x164 + AWB_HSCALE volatile.Register32 // 0x168 + AWB_VSCALE volatile.Register32 // 0x16C + AWB_TH_LUM volatile.Register32 // 0x170 + AWB_TH_RG volatile.Register32 // 0x174 + AWB_TH_BG volatile.Register32 // 0x178 + AWB0_WHITE_CNT volatile.Register32 // 0x17C + AWB0_ACC_R volatile.Register32 // 0x180 + AWB0_ACC_G volatile.Register32 // 0x184 + AWB0_ACC_B volatile.Register32 // 0x188 + COLOR_CTRL volatile.Register32 // 0x18C + BLC_VALUE volatile.Register32 // 0x190 + BLC_CTRL0 volatile.Register32 // 0x194 + BLC_CTRL1 volatile.Register32 // 0x198 + BLC_CTRL2 volatile.Register32 // 0x19C + BLC_MEAN volatile.Register32 // 0x1A0 + HIST_MODE volatile.Register32 // 0x1A4 + HIST_COEFF volatile.Register32 // 0x1A8 + HIST_OFFS volatile.Register32 // 0x1AC + HIST_SIZE volatile.Register32 // 0x1B0 + HIST_SEG0 volatile.Register32 // 0x1B4 + HIST_SEG1 volatile.Register32 // 0x1B8 + HIST_SEG2 volatile.Register32 // 0x1BC + HIST_SEG3 volatile.Register32 // 0x1C0 + HIST_WEIGHT0 volatile.Register32 // 0x1C4 + HIST_WEIGHT1 volatile.Register32 // 0x1C8 + HIST_WEIGHT2 volatile.Register32 // 0x1CC + HIST_WEIGHT3 volatile.Register32 // 0x1D0 + HIST_WEIGHT4 volatile.Register32 // 0x1D4 + HIST_WEIGHT5 volatile.Register32 // 0x1D8 + HIST_WEIGHT6 volatile.Register32 // 0x1DC + HIST_BIN0 volatile.Register32 // 0x1E0 + HIST_BIN1 volatile.Register32 // 0x1E4 + HIST_BIN2 volatile.Register32 // 0x1E8 + HIST_BIN3 volatile.Register32 // 0x1EC + HIST_BIN4 volatile.Register32 // 0x1F0 + HIST_BIN5 volatile.Register32 // 0x1F4 + HIST_BIN6 volatile.Register32 // 0x1F8 + HIST_BIN7 volatile.Register32 // 0x1FC + HIST_BIN8 volatile.Register32 // 0x200 + HIST_BIN9 volatile.Register32 // 0x204 + HIST_BIN10 volatile.Register32 // 0x208 + HIST_BIN11 volatile.Register32 // 0x20C + HIST_BIN12 volatile.Register32 // 0x210 + HIST_BIN13 volatile.Register32 // 0x214 + HIST_BIN14 volatile.Register32 // 0x218 + HIST_BIN15 volatile.Register32 // 0x21C + MEM_AUX_CTRL_0 volatile.Register32 // 0x220 + MEM_AUX_CTRL_1 volatile.Register32 // 0x224 + MEM_AUX_CTRL_2 volatile.Register32 // 0x228 + MEM_AUX_CTRL_3 volatile.Register32 // 0x22C + MEM_AUX_CTRL_4 volatile.Register32 // 0x230 + YUV_FORMAT volatile.Register32 // 0x234 + RDN_ECO_CS volatile.Register32 // 0x238 + RDN_ECO_LOW volatile.Register32 // 0x23C + RDN_ECO_HIGH volatile.Register32 // 0x240 +} + +// ISP.VER_DATE: version control register +func (o *ISP_Type) SetVER_DATE(value uint32) { + volatile.StoreUint32(&o.VER_DATE.Reg, value) +} +func (o *ISP_Type) GetVER_DATE() uint32 { + return volatile.LoadUint32(&o.VER_DATE.Reg) +} + +// ISP.CLK_EN: isp clk control register +func (o *ISP_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1 +} +func (o *ISP_Type) SetCLK_EN_CLK_BLC_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetCLK_EN_CLK_BLC_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetCLK_EN_CLK_DPC_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetCLK_EN_CLK_DPC_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetCLK_EN_CLK_BF_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetCLK_EN_CLK_BF_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x8) >> 3 +} +func (o *ISP_Type) SetCLK_EN_CLK_LSC_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10)|value<<4) +} +func (o *ISP_Type) GetCLK_EN_CLK_LSC_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10) >> 4 +} +func (o *ISP_Type) SetCLK_EN_CLK_DEMOSAIC_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20)|value<<5) +} +func (o *ISP_Type) GetCLK_EN_CLK_DEMOSAIC_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20) >> 5 +} +func (o *ISP_Type) SetCLK_EN_CLK_MEDIAN_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40)|value<<6) +} +func (o *ISP_Type) GetCLK_EN_CLK_MEDIAN_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40) >> 6 +} +func (o *ISP_Type) SetCLK_EN_CLK_CCM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x80)|value<<7) +} +func (o *ISP_Type) GetCLK_EN_CLK_CCM_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x80) >> 7 +} +func (o *ISP_Type) SetCLK_EN_CLK_GAMMA_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x100)|value<<8) +} +func (o *ISP_Type) GetCLK_EN_CLK_GAMMA_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x100) >> 8 +} +func (o *ISP_Type) SetCLK_EN_CLK_RGB2YUV_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x200)|value<<9) +} +func (o *ISP_Type) GetCLK_EN_CLK_RGB2YUV_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x200) >> 9 +} +func (o *ISP_Type) SetCLK_EN_CLK_SHARP_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x400)|value<<10) +} +func (o *ISP_Type) GetCLK_EN_CLK_SHARP_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x400) >> 10 +} +func (o *ISP_Type) SetCLK_EN_CLK_COLOR_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x800)|value<<11) +} +func (o *ISP_Type) GetCLK_EN_CLK_COLOR_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x800) >> 11 +} +func (o *ISP_Type) SetCLK_EN_CLK_YUV2RGB_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1000)|value<<12) +} +func (o *ISP_Type) GetCLK_EN_CLK_YUV2RGB_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1000) >> 12 +} +func (o *ISP_Type) SetCLK_EN_CLK_AE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x2000)|value<<13) +} +func (o *ISP_Type) GetCLK_EN_CLK_AE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x2000) >> 13 +} +func (o *ISP_Type) SetCLK_EN_CLK_AF_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x4000)|value<<14) +} +func (o *ISP_Type) GetCLK_EN_CLK_AF_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x4000) >> 14 +} +func (o *ISP_Type) SetCLK_EN_CLK_AWB_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x8000)|value<<15) +} +func (o *ISP_Type) GetCLK_EN_CLK_AWB_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x8000) >> 15 +} +func (o *ISP_Type) SetCLK_EN_CLK_HIST_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10000)|value<<16) +} +func (o *ISP_Type) GetCLK_EN_CLK_HIST_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10000) >> 16 +} +func (o *ISP_Type) SetCLK_EN_CLK_MIPI_IDI_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20000)|value<<17) +} +func (o *ISP_Type) GetCLK_EN_CLK_MIPI_IDI_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20000) >> 17 +} +func (o *ISP_Type) SetCLK_EN_ISP_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40000)|value<<18) +} +func (o *ISP_Type) GetCLK_EN_ISP_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40000) >> 18 +} + +// ISP.CNTL: isp module enable control register +func (o *ISP_Type) SetCNTL_MIPI_DATA_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetCNTL_MIPI_DATA_EN() uint32 { + return volatile.LoadUint32(&o.CNTL.Reg) & 0x1 +} +func (o *ISP_Type) SetCNTL_ISP_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetCNTL_ISP_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetCNTL_BLC_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetCNTL_BLC_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetCNTL_DPC_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetCNTL_DPC_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x8) >> 3 +} +func (o *ISP_Type) SetCNTL_BF_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x10)|value<<4) +} +func (o *ISP_Type) GetCNTL_BF_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x10) >> 4 +} +func (o *ISP_Type) SetCNTL_LSC_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x20)|value<<5) +} +func (o *ISP_Type) GetCNTL_LSC_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x20) >> 5 +} +func (o *ISP_Type) SetCNTL_DEMOSAIC_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x40)|value<<6) +} +func (o *ISP_Type) GetCNTL_DEMOSAIC_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x40) >> 6 +} +func (o *ISP_Type) SetCNTL_MEDIAN_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x80)|value<<7) +} +func (o *ISP_Type) GetCNTL_MEDIAN_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x80) >> 7 +} +func (o *ISP_Type) SetCNTL_CCM_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x100)|value<<8) +} +func (o *ISP_Type) GetCNTL_CCM_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x100) >> 8 +} +func (o *ISP_Type) SetCNTL_GAMMA_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x200)|value<<9) +} +func (o *ISP_Type) GetCNTL_GAMMA_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x200) >> 9 +} +func (o *ISP_Type) SetCNTL_RGB2YUV_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x400)|value<<10) +} +func (o *ISP_Type) GetCNTL_RGB2YUV_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x400) >> 10 +} +func (o *ISP_Type) SetCNTL_SHARP_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x800)|value<<11) +} +func (o *ISP_Type) GetCNTL_SHARP_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x800) >> 11 +} +func (o *ISP_Type) SetCNTL_COLOR_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x1000)|value<<12) +} +func (o *ISP_Type) GetCNTL_COLOR_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x1000) >> 12 +} +func (o *ISP_Type) SetCNTL_YUV2RGB_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x2000)|value<<13) +} +func (o *ISP_Type) GetCNTL_YUV2RGB_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x2000) >> 13 +} +func (o *ISP_Type) SetCNTL_AE_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x4000)|value<<14) +} +func (o *ISP_Type) GetCNTL_AE_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x4000) >> 14 +} +func (o *ISP_Type) SetCNTL_AF_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x8000)|value<<15) +} +func (o *ISP_Type) GetCNTL_AF_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x8000) >> 15 +} +func (o *ISP_Type) SetCNTL_AWB_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x10000)|value<<16) +} +func (o *ISP_Type) GetCNTL_AWB_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x10000) >> 16 +} +func (o *ISP_Type) SetCNTL_HIST_EN(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x20000)|value<<17) +} +func (o *ISP_Type) GetCNTL_HIST_EN() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x20000) >> 17 +} +func (o *ISP_Type) SetCNTL_BYTE_ENDIAN_ORDER(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *ISP_Type) GetCNTL_BYTE_ENDIAN_ORDER() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x1000000) >> 24 +} +func (o *ISP_Type) SetCNTL_ISP_DATA_TYPE(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x6000000)|value<<25) +} +func (o *ISP_Type) GetCNTL_ISP_DATA_TYPE() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x6000000) >> 25 +} +func (o *ISP_Type) SetCNTL_ISP_IN_SRC(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x18000000)|value<<27) +} +func (o *ISP_Type) GetCNTL_ISP_IN_SRC() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0x18000000) >> 27 +} +func (o *ISP_Type) SetCNTL_ISP_OUT_TYPE(value uint32) { + volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0xe0000000)|value<<29) +} +func (o *ISP_Type) GetCNTL_ISP_OUT_TYPE() uint32 { + return (volatile.LoadUint32(&o.CNTL.Reg) & 0xe0000000) >> 29 +} + +// ISP.HSYNC_CNT: header hsync interval control register +func (o *ISP_Type) SetHSYNC_CNT(value uint32) { + volatile.StoreUint32(&o.HSYNC_CNT.Reg, volatile.LoadUint32(&o.HSYNC_CNT.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHSYNC_CNT() uint32 { + return volatile.LoadUint32(&o.HSYNC_CNT.Reg) & 0xff +} + +// ISP.FRAME_CFG: frame control parameter register +func (o *ISP_Type) SetFRAME_CFG_VADR_NUM(value uint32) { + volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetFRAME_CFG_VADR_NUM() uint32 { + return volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0xfff +} +func (o *ISP_Type) SetFRAME_CFG_HADR_NUM(value uint32) { + volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0xfff000)|value<<12) +} +func (o *ISP_Type) GetFRAME_CFG_HADR_NUM() uint32 { + return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0xfff000) >> 12 +} +func (o *ISP_Type) SetFRAME_CFG_BAYER_MODE(value uint32) { + volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x18000000)|value<<27) +} +func (o *ISP_Type) GetFRAME_CFG_BAYER_MODE() uint32 { + return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x18000000) >> 27 +} +func (o *ISP_Type) SetFRAME_CFG_HSYNC_START_EXIST(value uint32) { + volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x20000000)|value<<29) +} +func (o *ISP_Type) GetFRAME_CFG_HSYNC_START_EXIST() uint32 { + return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x20000000) >> 29 +} +func (o *ISP_Type) SetFRAME_CFG_HSYNC_END_EXIST(value uint32) { + volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *ISP_Type) GetFRAME_CFG_HSYNC_END_EXIST() uint32 { + return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x40000000) >> 30 +} + +// ISP.CCM_COEF0: ccm coef register 0 +func (o *ISP_Type) SetCCM_COEF0_CCM_RR(value uint32) { + volatile.StoreUint32(&o.CCM_COEF0.Reg, volatile.LoadUint32(&o.CCM_COEF0.Reg)&^(0x1fff)|value) +} +func (o *ISP_Type) GetCCM_COEF0_CCM_RR() uint32 { + return volatile.LoadUint32(&o.CCM_COEF0.Reg) & 0x1fff +} +func (o *ISP_Type) SetCCM_COEF0_CCM_RG(value uint32) { + volatile.StoreUint32(&o.CCM_COEF0.Reg, volatile.LoadUint32(&o.CCM_COEF0.Reg)&^(0x3ffe000)|value<<13) +} +func (o *ISP_Type) GetCCM_COEF0_CCM_RG() uint32 { + return (volatile.LoadUint32(&o.CCM_COEF0.Reg) & 0x3ffe000) >> 13 +} + +// ISP.CCM_COEF1: ccm coef register 1 +func (o *ISP_Type) SetCCM_COEF1_CCM_RB(value uint32) { + volatile.StoreUint32(&o.CCM_COEF1.Reg, volatile.LoadUint32(&o.CCM_COEF1.Reg)&^(0x1fff)|value) +} +func (o *ISP_Type) GetCCM_COEF1_CCM_RB() uint32 { + return volatile.LoadUint32(&o.CCM_COEF1.Reg) & 0x1fff +} +func (o *ISP_Type) SetCCM_COEF1_CCM_GR(value uint32) { + volatile.StoreUint32(&o.CCM_COEF1.Reg, volatile.LoadUint32(&o.CCM_COEF1.Reg)&^(0x3ffe000)|value<<13) +} +func (o *ISP_Type) GetCCM_COEF1_CCM_GR() uint32 { + return (volatile.LoadUint32(&o.CCM_COEF1.Reg) & 0x3ffe000) >> 13 +} + +// ISP.CCM_COEF3: ccm coef register 3 +func (o *ISP_Type) SetCCM_COEF3_CCM_GG(value uint32) { + volatile.StoreUint32(&o.CCM_COEF3.Reg, volatile.LoadUint32(&o.CCM_COEF3.Reg)&^(0x1fff)|value) +} +func (o *ISP_Type) GetCCM_COEF3_CCM_GG() uint32 { + return volatile.LoadUint32(&o.CCM_COEF3.Reg) & 0x1fff +} +func (o *ISP_Type) SetCCM_COEF3_CCM_GB(value uint32) { + volatile.StoreUint32(&o.CCM_COEF3.Reg, volatile.LoadUint32(&o.CCM_COEF3.Reg)&^(0x3ffe000)|value<<13) +} +func (o *ISP_Type) GetCCM_COEF3_CCM_GB() uint32 { + return (volatile.LoadUint32(&o.CCM_COEF3.Reg) & 0x3ffe000) >> 13 +} + +// ISP.CCM_COEF4: ccm coef register 4 +func (o *ISP_Type) SetCCM_COEF4_CCM_BR(value uint32) { + volatile.StoreUint32(&o.CCM_COEF4.Reg, volatile.LoadUint32(&o.CCM_COEF4.Reg)&^(0x1fff)|value) +} +func (o *ISP_Type) GetCCM_COEF4_CCM_BR() uint32 { + return volatile.LoadUint32(&o.CCM_COEF4.Reg) & 0x1fff +} +func (o *ISP_Type) SetCCM_COEF4_CCM_BG(value uint32) { + volatile.StoreUint32(&o.CCM_COEF4.Reg, volatile.LoadUint32(&o.CCM_COEF4.Reg)&^(0x3ffe000)|value<<13) +} +func (o *ISP_Type) GetCCM_COEF4_CCM_BG() uint32 { + return (volatile.LoadUint32(&o.CCM_COEF4.Reg) & 0x3ffe000) >> 13 +} + +// ISP.CCM_COEF5: ccm coef register 5 +func (o *ISP_Type) SetCCM_COEF5_CCM_BB(value uint32) { + volatile.StoreUint32(&o.CCM_COEF5.Reg, volatile.LoadUint32(&o.CCM_COEF5.Reg)&^(0x1fff)|value) +} +func (o *ISP_Type) GetCCM_COEF5_CCM_BB() uint32 { + return volatile.LoadUint32(&o.CCM_COEF5.Reg) & 0x1fff +} + +// ISP.BF_MATRIX_CTRL: bf pix2matrix ctrl +func (o *ISP_Type) SetBF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TL(value uint32) { + volatile.StoreUint32(&o.BF_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetBF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TL() uint32 { + return volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg) & 0xff +} +func (o *ISP_Type) SetBF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TH(value uint32) { + volatile.StoreUint32(&o.BF_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetBF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TH() uint32 { + return (volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetBF_MATRIX_CTRL_BF_PADDING_DATA(value uint32) { + volatile.StoreUint32(&o.BF_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetBF_MATRIX_CTRL_BF_PADDING_DATA() uint32 { + return (volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetBF_MATRIX_CTRL_BF_PADDING_MODE(value uint32) { + volatile.StoreUint32(&o.BF_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *ISP_Type) GetBF_MATRIX_CTRL_BF_PADDING_MODE() uint32 { + return (volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg) & 0x1000000) >> 24 +} + +// ISP.BF_SIGMA: bf denoising level control register +func (o *ISP_Type) SetBF_SIGMA_SIGMA(value uint32) { + volatile.StoreUint32(&o.BF_SIGMA.Reg, volatile.LoadUint32(&o.BF_SIGMA.Reg)&^(0x3f)|value) +} +func (o *ISP_Type) GetBF_SIGMA_SIGMA() uint32 { + return volatile.LoadUint32(&o.BF_SIGMA.Reg) & 0x3f +} + +// ISP.BF_GAU0: bf gau template register 0 +func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE21(value uint32) { + volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf)|value) +} +func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE21() uint32 { + return volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf +} +func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE20(value uint32) { + volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf0)|value<<4) +} +func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE20() uint32 { + return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf0) >> 4 +} +func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE12(value uint32) { + volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf00)|value<<8) +} +func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE12() uint32 { + return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf00) >> 8 +} +func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE11(value uint32) { + volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf000)|value<<12) +} +func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE11() uint32 { + return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf000) >> 12 +} +func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE10(value uint32) { + volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf0000)|value<<16) +} +func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE10() uint32 { + return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf0000) >> 16 +} +func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE02(value uint32) { + volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf00000)|value<<20) +} +func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE02() uint32 { + return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf00000) >> 20 +} +func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE01(value uint32) { + volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf000000)|value<<24) +} +func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE01() uint32 { + return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf000000) >> 24 +} +func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE00(value uint32) { + volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf0000000)|value<<28) +} +func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE00() uint32 { + return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf0000000) >> 28 +} + +// ISP.BF_GAU1: bf gau template register 1 +func (o *ISP_Type) SetBF_GAU1_GAU_TEMPLATE22(value uint32) { + volatile.StoreUint32(&o.BF_GAU1.Reg, volatile.LoadUint32(&o.BF_GAU1.Reg)&^(0xf)|value) +} +func (o *ISP_Type) GetBF_GAU1_GAU_TEMPLATE22() uint32 { + return volatile.LoadUint32(&o.BF_GAU1.Reg) & 0xf +} + +// ISP.DPC_CTRL: DPC mode control register +func (o *ISP_Type) SetDPC_CTRL_DPC_CHECK_EN(value uint32) { + volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetDPC_CTRL_DPC_CHECK_EN() uint32 { + return volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x1 +} +func (o *ISP_Type) SetDPC_CTRL_STA_EN(value uint32) { + volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetDPC_CTRL_STA_EN() uint32 { + return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetDPC_CTRL_DYN_EN(value uint32) { + volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetDPC_CTRL_DYN_EN() uint32 { + return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetDPC_CTRL_DPC_BLACK_EN(value uint32) { + volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetDPC_CTRL_DPC_BLACK_EN() uint32 { + return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x8) >> 3 +} +func (o *ISP_Type) SetDPC_CTRL_DPC_METHOD_SEL(value uint32) { + volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *ISP_Type) GetDPC_CTRL_DPC_METHOD_SEL() uint32 { + return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x10) >> 4 +} +func (o *ISP_Type) SetDPC_CTRL_DPC_CHECK_OD_EN(value uint32) { + volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *ISP_Type) GetDPC_CTRL_DPC_CHECK_OD_EN() uint32 { + return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x20) >> 5 +} + +// ISP.DPC_CONF: DPC parameter config register +func (o *ISP_Type) SetDPC_CONF_DPC_THRESHOLD_L(value uint32) { + volatile.StoreUint32(&o.DPC_CONF.Reg, volatile.LoadUint32(&o.DPC_CONF.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetDPC_CONF_DPC_THRESHOLD_L() uint32 { + return volatile.LoadUint32(&o.DPC_CONF.Reg) & 0xff +} +func (o *ISP_Type) SetDPC_CONF_DPC_THRESHOLD_H(value uint32) { + volatile.StoreUint32(&o.DPC_CONF.Reg, volatile.LoadUint32(&o.DPC_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetDPC_CONF_DPC_THRESHOLD_H() uint32 { + return (volatile.LoadUint32(&o.DPC_CONF.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetDPC_CONF_DPC_FACTOR_DARK(value uint32) { + volatile.StoreUint32(&o.DPC_CONF.Reg, volatile.LoadUint32(&o.DPC_CONF.Reg)&^(0x3f0000)|value<<16) +} +func (o *ISP_Type) GetDPC_CONF_DPC_FACTOR_DARK() uint32 { + return (volatile.LoadUint32(&o.DPC_CONF.Reg) & 0x3f0000) >> 16 +} +func (o *ISP_Type) SetDPC_CONF_DPC_FACTOR_BRIG(value uint32) { + volatile.StoreUint32(&o.DPC_CONF.Reg, volatile.LoadUint32(&o.DPC_CONF.Reg)&^(0xfc00000)|value<<22) +} +func (o *ISP_Type) GetDPC_CONF_DPC_FACTOR_BRIG() uint32 { + return (volatile.LoadUint32(&o.DPC_CONF.Reg) & 0xfc00000) >> 22 +} + +// ISP.DPC_MATRIX_CTRL: dpc pix2matrix ctrl +func (o *ISP_Type) SetDPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TL(value uint32) { + volatile.StoreUint32(&o.DPC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetDPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TL() uint32 { + return volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg) & 0xff +} +func (o *ISP_Type) SetDPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TH(value uint32) { + volatile.StoreUint32(&o.DPC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetDPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TH() uint32 { + return (volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetDPC_MATRIX_CTRL_DPC_PADDING_DATA(value uint32) { + volatile.StoreUint32(&o.DPC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetDPC_MATRIX_CTRL_DPC_PADDING_DATA() uint32 { + return (volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetDPC_MATRIX_CTRL_DPC_PADDING_MODE(value uint32) { + volatile.StoreUint32(&o.DPC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *ISP_Type) GetDPC_MATRIX_CTRL_DPC_PADDING_MODE() uint32 { + return (volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg) & 0x1000000) >> 24 +} + +// ISP.DPC_DEADPIX_CNT: DPC dead-pix number register +func (o *ISP_Type) SetDPC_DEADPIX_CNT(value uint32) { + volatile.StoreUint32(&o.DPC_DEADPIX_CNT.Reg, volatile.LoadUint32(&o.DPC_DEADPIX_CNT.Reg)&^(0x3ff)|value) +} +func (o *ISP_Type) GetDPC_DEADPIX_CNT() uint32 { + return volatile.LoadUint32(&o.DPC_DEADPIX_CNT.Reg) & 0x3ff +} + +// ISP.LUT_CMD: LUT command register +func (o *ISP_Type) SetLUT_CMD_LUT_ADDR(value uint32) { + volatile.StoreUint32(&o.LUT_CMD.Reg, volatile.LoadUint32(&o.LUT_CMD.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetLUT_CMD_LUT_ADDR() uint32 { + return volatile.LoadUint32(&o.LUT_CMD.Reg) & 0xfff +} +func (o *ISP_Type) SetLUT_CMD_LUT_NUM(value uint32) { + volatile.StoreUint32(&o.LUT_CMD.Reg, volatile.LoadUint32(&o.LUT_CMD.Reg)&^(0xf000)|value<<12) +} +func (o *ISP_Type) GetLUT_CMD_LUT_NUM() uint32 { + return (volatile.LoadUint32(&o.LUT_CMD.Reg) & 0xf000) >> 12 +} +func (o *ISP_Type) SetLUT_CMD(value uint32) { + volatile.StoreUint32(&o.LUT_CMD.Reg, volatile.LoadUint32(&o.LUT_CMD.Reg)&^(0x10000)|value<<16) +} +func (o *ISP_Type) GetLUT_CMD() uint32 { + return (volatile.LoadUint32(&o.LUT_CMD.Reg) & 0x10000) >> 16 +} + +// ISP.LUT_WDATA: LUT write data register +func (o *ISP_Type) SetLUT_WDATA(value uint32) { + volatile.StoreUint32(&o.LUT_WDATA.Reg, value) +} +func (o *ISP_Type) GetLUT_WDATA() uint32 { + return volatile.LoadUint32(&o.LUT_WDATA.Reg) +} + +// ISP.LUT_RDATA: LUT read data register +func (o *ISP_Type) SetLUT_RDATA(value uint32) { + volatile.StoreUint32(&o.LUT_RDATA.Reg, value) +} +func (o *ISP_Type) GetLUT_RDATA() uint32 { + return volatile.LoadUint32(&o.LUT_RDATA.Reg) +} + +// ISP.LSC_TABLESIZE: LSC point in x-direction +func (o *ISP_Type) SetLSC_TABLESIZE_LSC_XTABLESIZE(value uint32) { + volatile.StoreUint32(&o.LSC_TABLESIZE.Reg, volatile.LoadUint32(&o.LSC_TABLESIZE.Reg)&^(0x1f)|value) +} +func (o *ISP_Type) GetLSC_TABLESIZE_LSC_XTABLESIZE() uint32 { + return volatile.LoadUint32(&o.LSC_TABLESIZE.Reg) & 0x1f +} + +// ISP.DEMOSAIC_MATRIX_CTRL: demosaic pix2matrix ctrl +func (o *ISP_Type) SetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TL(value uint32) { + volatile.StoreUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TL() uint32 { + return volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg) & 0xff +} +func (o *ISP_Type) SetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TH(value uint32) { + volatile.StoreUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TH() uint32 { + return (volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_DATA(value uint32) { + volatile.StoreUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_DATA() uint32 { + return (volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_MODE(value uint32) { + volatile.StoreUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *ISP_Type) GetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_MODE() uint32 { + return (volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg) & 0x1000000) >> 24 +} + +// ISP.DEMOSAIC_GRAD_RATIO: demosaic gradient select ratio +func (o *ISP_Type) SetDEMOSAIC_GRAD_RATIO(value uint32) { + volatile.StoreUint32(&o.DEMOSAIC_GRAD_RATIO.Reg, volatile.LoadUint32(&o.DEMOSAIC_GRAD_RATIO.Reg)&^(0x3f)|value) +} +func (o *ISP_Type) GetDEMOSAIC_GRAD_RATIO() uint32 { + return volatile.LoadUint32(&o.DEMOSAIC_GRAD_RATIO.Reg) & 0x3f +} + +// ISP.MEDIAN_MATRIX_CTRL: median pix2matrix ctrl +func (o *ISP_Type) SetMEDIAN_MATRIX_CTRL_MEDIAN_PADDING_DATA(value uint32) { + volatile.StoreUint32(&o.MEDIAN_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.MEDIAN_MATRIX_CTRL.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetMEDIAN_MATRIX_CTRL_MEDIAN_PADDING_DATA() uint32 { + return volatile.LoadUint32(&o.MEDIAN_MATRIX_CTRL.Reg) & 0xff +} +func (o *ISP_Type) SetMEDIAN_MATRIX_CTRL_MEDIAN_PADDING_MODE(value uint32) { + volatile.StoreUint32(&o.MEDIAN_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.MEDIAN_MATRIX_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *ISP_Type) GetMEDIAN_MATRIX_CTRL_MEDIAN_PADDING_MODE() uint32 { + return (volatile.LoadUint32(&o.MEDIAN_MATRIX_CTRL.Reg) & 0x100) >> 8 +} + +// ISP.INT_RAW: raw interrupt register +func (o *ISP_Type) SetINT_RAW_ISP_DATA_TYPE_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetINT_RAW_ISP_DATA_TYPE_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *ISP_Type) SetINT_RAW_ISP_ASYNC_FIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetINT_RAW_ISP_ASYNC_FIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetINT_RAW_ISP_BUF_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetINT_RAW_ISP_BUF_FULL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetINT_RAW_ISP_HVNUM_SETTING_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetINT_RAW_ISP_HVNUM_SETTING_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *ISP_Type) SetINT_RAW_ISP_DATA_TYPE_SETTING_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *ISP_Type) GetINT_RAW_ISP_DATA_TYPE_SETTING_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *ISP_Type) SetINT_RAW_ISP_MIPI_HNUM_UNMATCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *ISP_Type) GetINT_RAW_ISP_MIPI_HNUM_UNMATCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *ISP_Type) SetINT_RAW_DPC_CHECK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *ISP_Type) GetINT_RAW_DPC_CHECK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *ISP_Type) SetINT_RAW_GAMMA_XCOORD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *ISP_Type) GetINT_RAW_GAMMA_XCOORD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *ISP_Type) SetINT_RAW_AE_MONITOR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *ISP_Type) GetINT_RAW_AE_MONITOR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *ISP_Type) SetINT_RAW_AE_FRAME_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *ISP_Type) GetINT_RAW_AE_FRAME_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *ISP_Type) SetINT_RAW_AF_FDONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *ISP_Type) GetINT_RAW_AF_FDONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *ISP_Type) SetINT_RAW_AF_ENV_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *ISP_Type) GetINT_RAW_AF_ENV_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *ISP_Type) SetINT_RAW_AWB_FDONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *ISP_Type) GetINT_RAW_AWB_FDONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *ISP_Type) SetINT_RAW_HIST_FDONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *ISP_Type) GetINT_RAW_HIST_FDONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *ISP_Type) SetINT_RAW_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *ISP_Type) GetINT_RAW_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *ISP_Type) SetINT_RAW_BLC_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *ISP_Type) GetINT_RAW_BLC_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *ISP_Type) SetINT_RAW_LSC_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *ISP_Type) GetINT_RAW_LSC_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *ISP_Type) SetINT_RAW_DPC_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *ISP_Type) GetINT_RAW_DPC_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *ISP_Type) SetINT_RAW_BF_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *ISP_Type) GetINT_RAW_BF_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *ISP_Type) SetINT_RAW_DEMOSAIC_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *ISP_Type) GetINT_RAW_DEMOSAIC_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *ISP_Type) SetINT_RAW_MEDIAN_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *ISP_Type) GetINT_RAW_MEDIAN_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *ISP_Type) SetINT_RAW_CCM_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *ISP_Type) GetINT_RAW_CCM_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *ISP_Type) SetINT_RAW_GAMMA_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *ISP_Type) GetINT_RAW_GAMMA_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *ISP_Type) SetINT_RAW_RGB2YUV_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *ISP_Type) GetINT_RAW_RGB2YUV_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *ISP_Type) SetINT_RAW_SHARP_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *ISP_Type) GetINT_RAW_SHARP_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *ISP_Type) SetINT_RAW_COLOR_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *ISP_Type) GetINT_RAW_COLOR_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *ISP_Type) SetINT_RAW_YUV2RGB_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *ISP_Type) GetINT_RAW_YUV2RGB_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *ISP_Type) SetINT_RAW_TAIL_IDI_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *ISP_Type) GetINT_RAW_TAIL_IDI_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *ISP_Type) SetINT_RAW_HEADER_IDI_FRAME_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *ISP_Type) GetINT_RAW_HEADER_IDI_FRAME_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} + +// ISP.INT_ST: masked interrupt register +func (o *ISP_Type) SetINT_ST_ISP_DATA_TYPE_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetINT_ST_ISP_DATA_TYPE_ERR_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *ISP_Type) SetINT_ST_ISP_ASYNC_FIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetINT_ST_ISP_ASYNC_FIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetINT_ST_ISP_BUF_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetINT_ST_ISP_BUF_FULL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetINT_ST_ISP_HVNUM_SETTING_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetINT_ST_ISP_HVNUM_SETTING_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *ISP_Type) SetINT_ST_ISP_DATA_TYPE_SETTING_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *ISP_Type) GetINT_ST_ISP_DATA_TYPE_SETTING_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *ISP_Type) SetINT_ST_ISP_MIPI_HNUM_UNMATCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *ISP_Type) GetINT_ST_ISP_MIPI_HNUM_UNMATCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *ISP_Type) SetINT_ST_DPC_CHECK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *ISP_Type) GetINT_ST_DPC_CHECK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *ISP_Type) SetINT_ST_GAMMA_XCOORD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *ISP_Type) GetINT_ST_GAMMA_XCOORD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *ISP_Type) SetINT_ST_AE_MONITOR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *ISP_Type) GetINT_ST_AE_MONITOR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *ISP_Type) SetINT_ST_AE_FRAME_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *ISP_Type) GetINT_ST_AE_FRAME_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *ISP_Type) SetINT_ST_AF_FDONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *ISP_Type) GetINT_ST_AF_FDONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *ISP_Type) SetINT_ST_AF_ENV_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *ISP_Type) GetINT_ST_AF_ENV_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *ISP_Type) SetINT_ST_AWB_FDONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *ISP_Type) GetINT_ST_AWB_FDONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *ISP_Type) SetINT_ST_HIST_FDONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *ISP_Type) GetINT_ST_HIST_FDONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *ISP_Type) SetINT_ST_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *ISP_Type) GetINT_ST_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *ISP_Type) SetINT_ST_BLC_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *ISP_Type) GetINT_ST_BLC_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *ISP_Type) SetINT_ST_LSC_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *ISP_Type) GetINT_ST_LSC_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *ISP_Type) SetINT_ST_DPC_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *ISP_Type) GetINT_ST_DPC_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *ISP_Type) SetINT_ST_BF_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *ISP_Type) GetINT_ST_BF_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *ISP_Type) SetINT_ST_DEMOSAIC_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *ISP_Type) GetINT_ST_DEMOSAIC_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} +func (o *ISP_Type) SetINT_ST_MEDIAN_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *ISP_Type) GetINT_ST_MEDIAN_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *ISP_Type) SetINT_ST_CCM_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *ISP_Type) GetINT_ST_CCM_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21 +} +func (o *ISP_Type) SetINT_ST_GAMMA_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *ISP_Type) GetINT_ST_GAMMA_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22 +} +func (o *ISP_Type) SetINT_ST_RGB2YUV_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *ISP_Type) GetINT_ST_RGB2YUV_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23 +} +func (o *ISP_Type) SetINT_ST_SHARP_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *ISP_Type) GetINT_ST_SHARP_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *ISP_Type) SetINT_ST_COLOR_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *ISP_Type) GetINT_ST_COLOR_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *ISP_Type) SetINT_ST_YUV2RGB_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *ISP_Type) GetINT_ST_YUV2RGB_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *ISP_Type) SetINT_ST_TAIL_IDI_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *ISP_Type) GetINT_ST_TAIL_IDI_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *ISP_Type) SetINT_ST_HEADER_IDI_FRAME_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *ISP_Type) GetINT_ST_HEADER_IDI_FRAME_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} + +// ISP.INT_ENA: interrupt enable register +func (o *ISP_Type) SetINT_ENA_ISP_DATA_TYPE_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetINT_ENA_ISP_DATA_TYPE_ERR_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *ISP_Type) SetINT_ENA_ISP_ASYNC_FIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetINT_ENA_ISP_ASYNC_FIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetINT_ENA_ISP_BUF_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetINT_ENA_ISP_BUF_FULL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetINT_ENA_ISP_HVNUM_SETTING_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetINT_ENA_ISP_HVNUM_SETTING_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *ISP_Type) SetINT_ENA_ISP_DATA_TYPE_SETTING_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *ISP_Type) GetINT_ENA_ISP_DATA_TYPE_SETTING_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *ISP_Type) SetINT_ENA_ISP_MIPI_HNUM_UNMATCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *ISP_Type) GetINT_ENA_ISP_MIPI_HNUM_UNMATCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *ISP_Type) SetINT_ENA_DPC_CHECK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *ISP_Type) GetINT_ENA_DPC_CHECK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *ISP_Type) SetINT_ENA_GAMMA_XCOORD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *ISP_Type) GetINT_ENA_GAMMA_XCOORD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *ISP_Type) SetINT_ENA_AE_MONITOR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *ISP_Type) GetINT_ENA_AE_MONITOR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *ISP_Type) SetINT_ENA_AE_FRAME_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *ISP_Type) GetINT_ENA_AE_FRAME_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *ISP_Type) SetINT_ENA_AF_FDONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *ISP_Type) GetINT_ENA_AF_FDONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *ISP_Type) SetINT_ENA_AF_ENV_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *ISP_Type) GetINT_ENA_AF_ENV_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *ISP_Type) SetINT_ENA_AWB_FDONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *ISP_Type) GetINT_ENA_AWB_FDONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *ISP_Type) SetINT_ENA_HIST_FDONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *ISP_Type) GetINT_ENA_HIST_FDONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *ISP_Type) SetINT_ENA_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *ISP_Type) GetINT_ENA_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *ISP_Type) SetINT_ENA_BLC_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *ISP_Type) GetINT_ENA_BLC_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *ISP_Type) SetINT_ENA_LSC_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *ISP_Type) GetINT_ENA_LSC_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *ISP_Type) SetINT_ENA_DPC_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *ISP_Type) GetINT_ENA_DPC_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *ISP_Type) SetINT_ENA_BF_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *ISP_Type) GetINT_ENA_BF_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *ISP_Type) SetINT_ENA_DEMOSAIC_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *ISP_Type) GetINT_ENA_DEMOSAIC_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *ISP_Type) SetINT_ENA_MEDIAN_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *ISP_Type) GetINT_ENA_MEDIAN_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *ISP_Type) SetINT_ENA_CCM_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *ISP_Type) GetINT_ENA_CCM_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *ISP_Type) SetINT_ENA_GAMMA_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *ISP_Type) GetINT_ENA_GAMMA_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *ISP_Type) SetINT_ENA_RGB2YUV_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *ISP_Type) GetINT_ENA_RGB2YUV_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *ISP_Type) SetINT_ENA_SHARP_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *ISP_Type) GetINT_ENA_SHARP_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *ISP_Type) SetINT_ENA_COLOR_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *ISP_Type) GetINT_ENA_COLOR_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *ISP_Type) SetINT_ENA_YUV2RGB_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *ISP_Type) GetINT_ENA_YUV2RGB_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *ISP_Type) SetINT_ENA_TAIL_IDI_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *ISP_Type) GetINT_ENA_TAIL_IDI_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *ISP_Type) SetINT_ENA_HEADER_IDI_FRAME_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *ISP_Type) GetINT_ENA_HEADER_IDI_FRAME_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} + +// ISP.INT_CLR: interrupt clear register +func (o *ISP_Type) SetINT_CLR_ISP_DATA_TYPE_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetINT_CLR_ISP_DATA_TYPE_ERR_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *ISP_Type) SetINT_CLR_ISP_ASYNC_FIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetINT_CLR_ISP_ASYNC_FIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetINT_CLR_ISP_BUF_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetINT_CLR_ISP_BUF_FULL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetINT_CLR_ISP_HVNUM_SETTING_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetINT_CLR_ISP_HVNUM_SETTING_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *ISP_Type) SetINT_CLR_ISP_DATA_TYPE_SETTING_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *ISP_Type) GetINT_CLR_ISP_DATA_TYPE_SETTING_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *ISP_Type) SetINT_CLR_ISP_MIPI_HNUM_UNMATCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *ISP_Type) GetINT_CLR_ISP_MIPI_HNUM_UNMATCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *ISP_Type) SetINT_CLR_DPC_CHECK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *ISP_Type) GetINT_CLR_DPC_CHECK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *ISP_Type) SetINT_CLR_GAMMA_XCOORD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *ISP_Type) GetINT_CLR_GAMMA_XCOORD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *ISP_Type) SetINT_CLR_AE_MONITOR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *ISP_Type) GetINT_CLR_AE_MONITOR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *ISP_Type) SetINT_CLR_AE_FRAME_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *ISP_Type) GetINT_CLR_AE_FRAME_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *ISP_Type) SetINT_CLR_AF_FDONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *ISP_Type) GetINT_CLR_AF_FDONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *ISP_Type) SetINT_CLR_AF_ENV_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *ISP_Type) GetINT_CLR_AF_ENV_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *ISP_Type) SetINT_CLR_AWB_FDONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *ISP_Type) GetINT_CLR_AWB_FDONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *ISP_Type) SetINT_CLR_HIST_FDONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *ISP_Type) GetINT_CLR_HIST_FDONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *ISP_Type) SetINT_CLR_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *ISP_Type) GetINT_CLR_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *ISP_Type) SetINT_CLR_BLC_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *ISP_Type) GetINT_CLR_BLC_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *ISP_Type) SetINT_CLR_LSC_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *ISP_Type) GetINT_CLR_LSC_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *ISP_Type) SetINT_CLR_DPC_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *ISP_Type) GetINT_CLR_DPC_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *ISP_Type) SetINT_CLR_BF_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *ISP_Type) GetINT_CLR_BF_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *ISP_Type) SetINT_CLR_DEMOSAIC_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *ISP_Type) GetINT_CLR_DEMOSAIC_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *ISP_Type) SetINT_CLR_MEDIAN_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *ISP_Type) GetINT_CLR_MEDIAN_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *ISP_Type) SetINT_CLR_CCM_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *ISP_Type) GetINT_CLR_CCM_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *ISP_Type) SetINT_CLR_GAMMA_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *ISP_Type) GetINT_CLR_GAMMA_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *ISP_Type) SetINT_CLR_RGB2YUV_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *ISP_Type) GetINT_CLR_RGB2YUV_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *ISP_Type) SetINT_CLR_SHARP_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *ISP_Type) GetINT_CLR_SHARP_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *ISP_Type) SetINT_CLR_COLOR_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *ISP_Type) GetINT_CLR_COLOR_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *ISP_Type) SetINT_CLR_YUV2RGB_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *ISP_Type) GetINT_CLR_YUV2RGB_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *ISP_Type) SetINT_CLR_TAIL_IDI_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *ISP_Type) GetINT_CLR_TAIL_IDI_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *ISP_Type) SetINT_CLR_HEADER_IDI_FRAME_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *ISP_Type) GetINT_CLR_HEADER_IDI_FRAME_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} + +// ISP.GAMMA_CTRL: gamma control register +func (o *ISP_Type) SetGAMMA_CTRL_GAMMA_UPDATE(value uint32) { + volatile.StoreUint32(&o.GAMMA_CTRL.Reg, volatile.LoadUint32(&o.GAMMA_CTRL.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetGAMMA_CTRL_GAMMA_UPDATE() uint32 { + return volatile.LoadUint32(&o.GAMMA_CTRL.Reg) & 0x1 +} +func (o *ISP_Type) SetGAMMA_CTRL_GAMMA_B_LAST_CORRECT(value uint32) { + volatile.StoreUint32(&o.GAMMA_CTRL.Reg, volatile.LoadUint32(&o.GAMMA_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetGAMMA_CTRL_GAMMA_B_LAST_CORRECT() uint32 { + return (volatile.LoadUint32(&o.GAMMA_CTRL.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetGAMMA_CTRL_GAMMA_G_LAST_CORRECT(value uint32) { + volatile.StoreUint32(&o.GAMMA_CTRL.Reg, volatile.LoadUint32(&o.GAMMA_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetGAMMA_CTRL_GAMMA_G_LAST_CORRECT() uint32 { + return (volatile.LoadUint32(&o.GAMMA_CTRL.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetGAMMA_CTRL_GAMMA_R_LAST_CORRECT(value uint32) { + volatile.StoreUint32(&o.GAMMA_CTRL.Reg, volatile.LoadUint32(&o.GAMMA_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetGAMMA_CTRL_GAMMA_R_LAST_CORRECT() uint32 { + return (volatile.LoadUint32(&o.GAMMA_CTRL.Reg) & 0x8) >> 3 +} + +// ISP.GAMMA_RY1: point of Y-axis of r channel gamma curve register 1 +func (o *ISP_Type) SetGAMMA_RY1_GAMMA_R_Y03(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY1.Reg, volatile.LoadUint32(&o.GAMMA_RY1.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_RY1_GAMMA_R_Y03() uint32 { + return volatile.LoadUint32(&o.GAMMA_RY1.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_RY1_GAMMA_R_Y02(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY1.Reg, volatile.LoadUint32(&o.GAMMA_RY1.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_RY1_GAMMA_R_Y02() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY1.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_RY1_GAMMA_R_Y01(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY1.Reg, volatile.LoadUint32(&o.GAMMA_RY1.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_RY1_GAMMA_R_Y01() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY1.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_RY1_GAMMA_R_Y00(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY1.Reg, volatile.LoadUint32(&o.GAMMA_RY1.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_RY1_GAMMA_R_Y00() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY1.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_RY2: point of Y-axis of r channel gamma curve register 2 +func (o *ISP_Type) SetGAMMA_RY2_GAMMA_R_Y07(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY2.Reg, volatile.LoadUint32(&o.GAMMA_RY2.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_RY2_GAMMA_R_Y07() uint32 { + return volatile.LoadUint32(&o.GAMMA_RY2.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_RY2_GAMMA_R_Y06(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY2.Reg, volatile.LoadUint32(&o.GAMMA_RY2.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_RY2_GAMMA_R_Y06() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY2.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_RY2_GAMMA_R_Y05(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY2.Reg, volatile.LoadUint32(&o.GAMMA_RY2.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_RY2_GAMMA_R_Y05() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY2.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_RY2_GAMMA_R_Y04(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY2.Reg, volatile.LoadUint32(&o.GAMMA_RY2.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_RY2_GAMMA_R_Y04() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY2.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_RY3: point of Y-axis of r channel gamma curve register 3 +func (o *ISP_Type) SetGAMMA_RY3_GAMMA_R_Y0B(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY3.Reg, volatile.LoadUint32(&o.GAMMA_RY3.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_RY3_GAMMA_R_Y0B() uint32 { + return volatile.LoadUint32(&o.GAMMA_RY3.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_RY3_GAMMA_R_Y0A(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY3.Reg, volatile.LoadUint32(&o.GAMMA_RY3.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_RY3_GAMMA_R_Y0A() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY3.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_RY3_GAMMA_R_Y09(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY3.Reg, volatile.LoadUint32(&o.GAMMA_RY3.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_RY3_GAMMA_R_Y09() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY3.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_RY3_GAMMA_R_Y08(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY3.Reg, volatile.LoadUint32(&o.GAMMA_RY3.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_RY3_GAMMA_R_Y08() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY3.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_RY4: point of Y-axis of r channel gamma curve register 4 +func (o *ISP_Type) SetGAMMA_RY4_GAMMA_R_Y0F(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY4.Reg, volatile.LoadUint32(&o.GAMMA_RY4.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_RY4_GAMMA_R_Y0F() uint32 { + return volatile.LoadUint32(&o.GAMMA_RY4.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_RY4_GAMMA_R_Y0E(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY4.Reg, volatile.LoadUint32(&o.GAMMA_RY4.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_RY4_GAMMA_R_Y0E() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY4.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_RY4_GAMMA_R_Y0D(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY4.Reg, volatile.LoadUint32(&o.GAMMA_RY4.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_RY4_GAMMA_R_Y0D() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY4.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_RY4_GAMMA_R_Y0C(value uint32) { + volatile.StoreUint32(&o.GAMMA_RY4.Reg, volatile.LoadUint32(&o.GAMMA_RY4.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_RY4_GAMMA_R_Y0C() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RY4.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_GY1: point of Y-axis of g channel gamma curve register 1 +func (o *ISP_Type) SetGAMMA_GY1_GAMMA_G_Y03(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY1.Reg, volatile.LoadUint32(&o.GAMMA_GY1.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_GY1_GAMMA_G_Y03() uint32 { + return volatile.LoadUint32(&o.GAMMA_GY1.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_GY1_GAMMA_G_Y02(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY1.Reg, volatile.LoadUint32(&o.GAMMA_GY1.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_GY1_GAMMA_G_Y02() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY1.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_GY1_GAMMA_G_Y01(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY1.Reg, volatile.LoadUint32(&o.GAMMA_GY1.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_GY1_GAMMA_G_Y01() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY1.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_GY1_GAMMA_G_Y00(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY1.Reg, volatile.LoadUint32(&o.GAMMA_GY1.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_GY1_GAMMA_G_Y00() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY1.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_GY2: point of Y-axis of g channel gamma curve register 2 +func (o *ISP_Type) SetGAMMA_GY2_GAMMA_G_Y07(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY2.Reg, volatile.LoadUint32(&o.GAMMA_GY2.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_GY2_GAMMA_G_Y07() uint32 { + return volatile.LoadUint32(&o.GAMMA_GY2.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_GY2_GAMMA_G_Y06(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY2.Reg, volatile.LoadUint32(&o.GAMMA_GY2.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_GY2_GAMMA_G_Y06() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY2.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_GY2_GAMMA_G_Y05(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY2.Reg, volatile.LoadUint32(&o.GAMMA_GY2.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_GY2_GAMMA_G_Y05() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY2.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_GY2_GAMMA_G_Y04(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY2.Reg, volatile.LoadUint32(&o.GAMMA_GY2.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_GY2_GAMMA_G_Y04() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY2.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_GY3: point of Y-axis of g channel gamma curve register 3 +func (o *ISP_Type) SetGAMMA_GY3_GAMMA_G_Y0B(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY3.Reg, volatile.LoadUint32(&o.GAMMA_GY3.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_GY3_GAMMA_G_Y0B() uint32 { + return volatile.LoadUint32(&o.GAMMA_GY3.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_GY3_GAMMA_G_Y0A(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY3.Reg, volatile.LoadUint32(&o.GAMMA_GY3.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_GY3_GAMMA_G_Y0A() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY3.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_GY3_GAMMA_G_Y09(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY3.Reg, volatile.LoadUint32(&o.GAMMA_GY3.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_GY3_GAMMA_G_Y09() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY3.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_GY3_GAMMA_G_Y08(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY3.Reg, volatile.LoadUint32(&o.GAMMA_GY3.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_GY3_GAMMA_G_Y08() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY3.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_GY4: point of Y-axis of g channel gamma curve register 4 +func (o *ISP_Type) SetGAMMA_GY4_GAMMA_G_Y0F(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY4.Reg, volatile.LoadUint32(&o.GAMMA_GY4.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_GY4_GAMMA_G_Y0F() uint32 { + return volatile.LoadUint32(&o.GAMMA_GY4.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_GY4_GAMMA_G_Y0E(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY4.Reg, volatile.LoadUint32(&o.GAMMA_GY4.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_GY4_GAMMA_G_Y0E() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY4.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_GY4_GAMMA_G_Y0D(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY4.Reg, volatile.LoadUint32(&o.GAMMA_GY4.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_GY4_GAMMA_G_Y0D() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY4.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_GY4_GAMMA_G_Y0C(value uint32) { + volatile.StoreUint32(&o.GAMMA_GY4.Reg, volatile.LoadUint32(&o.GAMMA_GY4.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_GY4_GAMMA_G_Y0C() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GY4.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_BY1: point of Y-axis of b channel gamma curve register 1 +func (o *ISP_Type) SetGAMMA_BY1_GAMMA_B_Y03(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY1.Reg, volatile.LoadUint32(&o.GAMMA_BY1.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_BY1_GAMMA_B_Y03() uint32 { + return volatile.LoadUint32(&o.GAMMA_BY1.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_BY1_GAMMA_B_Y02(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY1.Reg, volatile.LoadUint32(&o.GAMMA_BY1.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_BY1_GAMMA_B_Y02() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY1.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_BY1_GAMMA_B_Y01(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY1.Reg, volatile.LoadUint32(&o.GAMMA_BY1.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_BY1_GAMMA_B_Y01() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY1.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_BY1_GAMMA_B_Y00(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY1.Reg, volatile.LoadUint32(&o.GAMMA_BY1.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_BY1_GAMMA_B_Y00() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY1.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_BY2: point of Y-axis of b channel gamma curve register 2 +func (o *ISP_Type) SetGAMMA_BY2_GAMMA_B_Y07(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY2.Reg, volatile.LoadUint32(&o.GAMMA_BY2.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_BY2_GAMMA_B_Y07() uint32 { + return volatile.LoadUint32(&o.GAMMA_BY2.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_BY2_GAMMA_B_Y06(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY2.Reg, volatile.LoadUint32(&o.GAMMA_BY2.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_BY2_GAMMA_B_Y06() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY2.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_BY2_GAMMA_B_Y05(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY2.Reg, volatile.LoadUint32(&o.GAMMA_BY2.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_BY2_GAMMA_B_Y05() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY2.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_BY2_GAMMA_B_Y04(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY2.Reg, volatile.LoadUint32(&o.GAMMA_BY2.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_BY2_GAMMA_B_Y04() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY2.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_BY3: point of Y-axis of b channel gamma curve register 3 +func (o *ISP_Type) SetGAMMA_BY3_GAMMA_B_Y0B(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY3.Reg, volatile.LoadUint32(&o.GAMMA_BY3.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_BY3_GAMMA_B_Y0B() uint32 { + return volatile.LoadUint32(&o.GAMMA_BY3.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_BY3_GAMMA_B_Y0A(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY3.Reg, volatile.LoadUint32(&o.GAMMA_BY3.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_BY3_GAMMA_B_Y0A() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY3.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_BY3_GAMMA_B_Y09(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY3.Reg, volatile.LoadUint32(&o.GAMMA_BY3.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_BY3_GAMMA_B_Y09() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY3.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_BY3_GAMMA_B_Y08(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY3.Reg, volatile.LoadUint32(&o.GAMMA_BY3.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_BY3_GAMMA_B_Y08() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY3.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_BY4: point of Y-axis of b channel gamma curve register 4 +func (o *ISP_Type) SetGAMMA_BY4_GAMMA_B_Y0F(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY4.Reg, volatile.LoadUint32(&o.GAMMA_BY4.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetGAMMA_BY4_GAMMA_B_Y0F() uint32 { + return volatile.LoadUint32(&o.GAMMA_BY4.Reg) & 0xff +} +func (o *ISP_Type) SetGAMMA_BY4_GAMMA_B_Y0E(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY4.Reg, volatile.LoadUint32(&o.GAMMA_BY4.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetGAMMA_BY4_GAMMA_B_Y0E() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY4.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetGAMMA_BY4_GAMMA_B_Y0D(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY4.Reg, volatile.LoadUint32(&o.GAMMA_BY4.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetGAMMA_BY4_GAMMA_B_Y0D() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY4.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetGAMMA_BY4_GAMMA_B_Y0C(value uint32) { + volatile.StoreUint32(&o.GAMMA_BY4.Reg, volatile.LoadUint32(&o.GAMMA_BY4.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetGAMMA_BY4_GAMMA_B_Y0C() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BY4.Reg) & 0xff000000) >> 24 +} + +// ISP.GAMMA_RX1: point of X-axis of r channel gamma curve register 1 +func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X07(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x7)|value) +} +func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X07() uint32 { + return volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x7 +} +func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X06(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x38)|value<<3) +} +func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X06() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x38) >> 3 +} +func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X05(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x1c0)|value<<6) +} +func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X05() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x1c0) >> 6 +} +func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X04(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0xe00)|value<<9) +} +func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X04() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0xe00) >> 9 +} +func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X03(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x7000)|value<<12) +} +func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X03() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x7000) >> 12 +} +func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X02(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x38000)|value<<15) +} +func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X02() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x38000) >> 15 +} +func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X01(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x1c0000)|value<<18) +} +func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X01() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x1c0000) >> 18 +} +func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X00(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0xe00000)|value<<21) +} +func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X00() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0xe00000) >> 21 +} + +// ISP.GAMMA_RX2: point of X-axis of r channel gamma curve register 2 +func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0F(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x7)|value) +} +func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0F() uint32 { + return volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x7 +} +func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0E(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x38)|value<<3) +} +func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0E() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x38) >> 3 +} +func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0D(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x1c0)|value<<6) +} +func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0D() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x1c0) >> 6 +} +func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0C(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0xe00)|value<<9) +} +func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0C() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0xe00) >> 9 +} +func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0B(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x7000)|value<<12) +} +func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0B() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x7000) >> 12 +} +func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0A(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x38000)|value<<15) +} +func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0A() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x38000) >> 15 +} +func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X09(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x1c0000)|value<<18) +} +func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X09() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x1c0000) >> 18 +} +func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X08(value uint32) { + volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0xe00000)|value<<21) +} +func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X08() uint32 { + return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0xe00000) >> 21 +} + +// ISP.GAMMA_GX1: point of X-axis of g channel gamma curve register 1 +func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X07(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x7)|value) +} +func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X07() uint32 { + return volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x7 +} +func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X06(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x38)|value<<3) +} +func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X06() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x38) >> 3 +} +func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X05(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x1c0)|value<<6) +} +func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X05() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x1c0) >> 6 +} +func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X04(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0xe00)|value<<9) +} +func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X04() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0xe00) >> 9 +} +func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X03(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x7000)|value<<12) +} +func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X03() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x7000) >> 12 +} +func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X02(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x38000)|value<<15) +} +func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X02() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x38000) >> 15 +} +func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X01(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x1c0000)|value<<18) +} +func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X01() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x1c0000) >> 18 +} +func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X00(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0xe00000)|value<<21) +} +func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X00() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0xe00000) >> 21 +} + +// ISP.GAMMA_GX2: point of X-axis of g channel gamma curve register 2 +func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0F(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x7)|value) +} +func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0F() uint32 { + return volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x7 +} +func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0E(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x38)|value<<3) +} +func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0E() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x38) >> 3 +} +func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0D(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x1c0)|value<<6) +} +func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0D() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x1c0) >> 6 +} +func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0C(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0xe00)|value<<9) +} +func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0C() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0xe00) >> 9 +} +func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0B(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x7000)|value<<12) +} +func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0B() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x7000) >> 12 +} +func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0A(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x38000)|value<<15) +} +func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0A() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x38000) >> 15 +} +func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X09(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x1c0000)|value<<18) +} +func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X09() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x1c0000) >> 18 +} +func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X08(value uint32) { + volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0xe00000)|value<<21) +} +func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X08() uint32 { + return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0xe00000) >> 21 +} + +// ISP.GAMMA_BX1: point of X-axis of b channel gamma curve register 1 +func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X07(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x7)|value) +} +func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X07() uint32 { + return volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x7 +} +func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X06(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x38)|value<<3) +} +func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X06() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x38) >> 3 +} +func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X05(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x1c0)|value<<6) +} +func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X05() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x1c0) >> 6 +} +func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X04(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0xe00)|value<<9) +} +func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X04() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0xe00) >> 9 +} +func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X03(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x7000)|value<<12) +} +func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X03() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x7000) >> 12 +} +func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X02(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x38000)|value<<15) +} +func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X02() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x38000) >> 15 +} +func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X01(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x1c0000)|value<<18) +} +func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X01() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x1c0000) >> 18 +} +func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X00(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0xe00000)|value<<21) +} +func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X00() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0xe00000) >> 21 +} + +// ISP.GAMMA_BX2: point of X-axis of b channel gamma curve register 2 +func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0F(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x7)|value) +} +func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0F() uint32 { + return volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x7 +} +func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0E(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x38)|value<<3) +} +func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0E() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x38) >> 3 +} +func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0D(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x1c0)|value<<6) +} +func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0D() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x1c0) >> 6 +} +func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0C(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0xe00)|value<<9) +} +func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0C() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0xe00) >> 9 +} +func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0B(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x7000)|value<<12) +} +func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0B() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x7000) >> 12 +} +func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0A(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x38000)|value<<15) +} +func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0A() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x38000) >> 15 +} +func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X09(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x1c0000)|value<<18) +} +func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X09() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x1c0000) >> 18 +} +func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X08(value uint32) { + volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0xe00000)|value<<21) +} +func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X08() uint32 { + return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0xe00000) >> 21 +} + +// ISP.AE_CTRL: ae control register +func (o *ISP_Type) SetAE_CTRL_AE_UPDATE(value uint32) { + volatile.StoreUint32(&o.AE_CTRL.Reg, volatile.LoadUint32(&o.AE_CTRL.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetAE_CTRL_AE_UPDATE() uint32 { + return volatile.LoadUint32(&o.AE_CTRL.Reg) & 0x1 +} +func (o *ISP_Type) SetAE_CTRL_AE_SELECT(value uint32) { + volatile.StoreUint32(&o.AE_CTRL.Reg, volatile.LoadUint32(&o.AE_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetAE_CTRL_AE_SELECT() uint32 { + return (volatile.LoadUint32(&o.AE_CTRL.Reg) & 0x2) >> 1 +} + +// ISP.AE_MONITOR: ae monitor control register +func (o *ISP_Type) SetAE_MONITOR_TL(value uint32) { + volatile.StoreUint32(&o.AE_MONITOR.Reg, volatile.LoadUint32(&o.AE_MONITOR.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetAE_MONITOR_TL() uint32 { + return volatile.LoadUint32(&o.AE_MONITOR.Reg) & 0xff +} +func (o *ISP_Type) SetAE_MONITOR_TH(value uint32) { + volatile.StoreUint32(&o.AE_MONITOR.Reg, volatile.LoadUint32(&o.AE_MONITOR.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetAE_MONITOR_TH() uint32 { + return (volatile.LoadUint32(&o.AE_MONITOR.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetAE_MONITOR_PERIOD(value uint32) { + volatile.StoreUint32(&o.AE_MONITOR.Reg, volatile.LoadUint32(&o.AE_MONITOR.Reg)&^(0x3f0000)|value<<16) +} +func (o *ISP_Type) GetAE_MONITOR_PERIOD() uint32 { + return (volatile.LoadUint32(&o.AE_MONITOR.Reg) & 0x3f0000) >> 16 +} + +// ISP.AE_BX: ae window register in x-direction +func (o *ISP_Type) SetAE_BX_AE_X_BSIZE(value uint32) { + volatile.StoreUint32(&o.AE_BX.Reg, volatile.LoadUint32(&o.AE_BX.Reg)&^(0x7ff)|value) +} +func (o *ISP_Type) GetAE_BX_AE_X_BSIZE() uint32 { + return volatile.LoadUint32(&o.AE_BX.Reg) & 0x7ff +} +func (o *ISP_Type) SetAE_BX_AE_X_START(value uint32) { + volatile.StoreUint32(&o.AE_BX.Reg, volatile.LoadUint32(&o.AE_BX.Reg)&^(0x3ff800)|value<<11) +} +func (o *ISP_Type) GetAE_BX_AE_X_START() uint32 { + return (volatile.LoadUint32(&o.AE_BX.Reg) & 0x3ff800) >> 11 +} + +// ISP.AE_BY: ae window register in y-direction +func (o *ISP_Type) SetAE_BY_AE_Y_BSIZE(value uint32) { + volatile.StoreUint32(&o.AE_BY.Reg, volatile.LoadUint32(&o.AE_BY.Reg)&^(0x7ff)|value) +} +func (o *ISP_Type) GetAE_BY_AE_Y_BSIZE() uint32 { + return volatile.LoadUint32(&o.AE_BY.Reg) & 0x7ff +} +func (o *ISP_Type) SetAE_BY_AE_Y_START(value uint32) { + volatile.StoreUint32(&o.AE_BY.Reg, volatile.LoadUint32(&o.AE_BY.Reg)&^(0x3ff800)|value<<11) +} +func (o *ISP_Type) GetAE_BY_AE_Y_START() uint32 { + return (volatile.LoadUint32(&o.AE_BY.Reg) & 0x3ff800) >> 11 +} + +// ISP.AE_WINPIXNUM: ae sub-window pix num register +func (o *ISP_Type) SetAE_WINPIXNUM_AE_SUBWIN_PIXNUM(value uint32) { + volatile.StoreUint32(&o.AE_WINPIXNUM.Reg, volatile.LoadUint32(&o.AE_WINPIXNUM.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetAE_WINPIXNUM_AE_SUBWIN_PIXNUM() uint32 { + return volatile.LoadUint32(&o.AE_WINPIXNUM.Reg) & 0x1ffff +} + +// ISP.AE_WIN_RECIPROCAL: reciprocal of ae sub-window pixel number +func (o *ISP_Type) SetAE_WIN_RECIPROCAL_AE_SUBWIN_RECIP(value uint32) { + volatile.StoreUint32(&o.AE_WIN_RECIPROCAL.Reg, volatile.LoadUint32(&o.AE_WIN_RECIPROCAL.Reg)&^(0xfffff)|value) +} +func (o *ISP_Type) GetAE_WIN_RECIPROCAL_AE_SUBWIN_RECIP() uint32 { + return volatile.LoadUint32(&o.AE_WIN_RECIPROCAL.Reg) & 0xfffff +} + +// ISP.AE_BLOCK_MEAN_0: ae statistic result register 0 +func (o *ISP_Type) SetAE_BLOCK_MEAN_0_AE_B03_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_0.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_0_AE_B03_MEAN() uint32 { + return volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg) & 0xff +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_0_AE_B02_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_0.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_0_AE_B02_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_0_AE_B01_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_0.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_0_AE_B01_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_0_AE_B00_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_0.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_0_AE_B00_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg) & 0xff000000) >> 24 +} + +// ISP.AE_BLOCK_MEAN_1: ae statistic result register 1 +func (o *ISP_Type) SetAE_BLOCK_MEAN_1_AE_B12_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_1.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_1_AE_B12_MEAN() uint32 { + return volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg) & 0xff +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_1_AE_B11_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_1.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_1_AE_B11_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_1_AE_B10_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_1.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_1_AE_B10_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_1_AE_B04_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_1.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_1_AE_B04_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg) & 0xff000000) >> 24 +} + +// ISP.AE_BLOCK_MEAN_2: ae statistic result register 2 +func (o *ISP_Type) SetAE_BLOCK_MEAN_2_AE_B21_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_2.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_2_AE_B21_MEAN() uint32 { + return volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg) & 0xff +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_2_AE_B20_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_2.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_2_AE_B20_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_2_AE_B14_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_2.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_2_AE_B14_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_2_AE_B13_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_2.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_2_AE_B13_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg) & 0xff000000) >> 24 +} + +// ISP.AE_BLOCK_MEAN_3: ae statistic result register 3 +func (o *ISP_Type) SetAE_BLOCK_MEAN_3_AE_B30_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_3.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_3_AE_B30_MEAN() uint32 { + return volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg) & 0xff +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_3_AE_B24_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_3.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_3_AE_B24_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_3_AE_B23_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_3.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_3_AE_B23_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_3_AE_B22_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_3.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_3_AE_B22_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg) & 0xff000000) >> 24 +} + +// ISP.AE_BLOCK_MEAN_4: ae statistic result register 4 +func (o *ISP_Type) SetAE_BLOCK_MEAN_4_AE_B34_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_4.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_4_AE_B34_MEAN() uint32 { + return volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg) & 0xff +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_4_AE_B33_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_4.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_4_AE_B33_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_4_AE_B32_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_4.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_4_AE_B32_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_4_AE_B31_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_4.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_4_AE_B31_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg) & 0xff000000) >> 24 +} + +// ISP.AE_BLOCK_MEAN_5: ae statistic result register 5 +func (o *ISP_Type) SetAE_BLOCK_MEAN_5_AE_B43_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_5.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_5_AE_B43_MEAN() uint32 { + return volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg) & 0xff +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_5_AE_B42_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_5.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_5_AE_B42_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_5_AE_B41_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_5.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_5_AE_B41_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetAE_BLOCK_MEAN_5_AE_B40_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_5.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_5_AE_B40_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg) & 0xff000000) >> 24 +} + +// ISP.AE_BLOCK_MEAN_6: ae statistic result register 6 +func (o *ISP_Type) SetAE_BLOCK_MEAN_6_AE_B44_MEAN(value uint32) { + volatile.StoreUint32(&o.AE_BLOCK_MEAN_6.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_6.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetAE_BLOCK_MEAN_6_AE_B44_MEAN() uint32 { + return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_6.Reg) & 0xff000000) >> 24 +} + +// ISP.SHARP_CTRL0: sharp control register 0 +func (o *ISP_Type) SetSHARP_CTRL0_SHARP_THRESHOLD_LOW(value uint32) { + volatile.StoreUint32(&o.SHARP_CTRL0.Reg, volatile.LoadUint32(&o.SHARP_CTRL0.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetSHARP_CTRL0_SHARP_THRESHOLD_LOW() uint32 { + return volatile.LoadUint32(&o.SHARP_CTRL0.Reg) & 0xff +} +func (o *ISP_Type) SetSHARP_CTRL0_SHARP_THRESHOLD_HIGH(value uint32) { + volatile.StoreUint32(&o.SHARP_CTRL0.Reg, volatile.LoadUint32(&o.SHARP_CTRL0.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetSHARP_CTRL0_SHARP_THRESHOLD_HIGH() uint32 { + return (volatile.LoadUint32(&o.SHARP_CTRL0.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetSHARP_CTRL0_SHARP_AMOUNT_LOW(value uint32) { + volatile.StoreUint32(&o.SHARP_CTRL0.Reg, volatile.LoadUint32(&o.SHARP_CTRL0.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetSHARP_CTRL0_SHARP_AMOUNT_LOW() uint32 { + return (volatile.LoadUint32(&o.SHARP_CTRL0.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetSHARP_CTRL0_SHARP_AMOUNT_HIGH(value uint32) { + volatile.StoreUint32(&o.SHARP_CTRL0.Reg, volatile.LoadUint32(&o.SHARP_CTRL0.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetSHARP_CTRL0_SHARP_AMOUNT_HIGH() uint32 { + return (volatile.LoadUint32(&o.SHARP_CTRL0.Reg) & 0xff000000) >> 24 +} + +// ISP.SHARP_FILTER0: sharp usm config register 0 +func (o *ISP_Type) SetSHARP_FILTER0_SHARP_FILTER_COE00(value uint32) { + volatile.StoreUint32(&o.SHARP_FILTER0.Reg, volatile.LoadUint32(&o.SHARP_FILTER0.Reg)&^(0x1f)|value) +} +func (o *ISP_Type) GetSHARP_FILTER0_SHARP_FILTER_COE00() uint32 { + return volatile.LoadUint32(&o.SHARP_FILTER0.Reg) & 0x1f +} +func (o *ISP_Type) SetSHARP_FILTER0_SHARP_FILTER_COE01(value uint32) { + volatile.StoreUint32(&o.SHARP_FILTER0.Reg, volatile.LoadUint32(&o.SHARP_FILTER0.Reg)&^(0x3e0)|value<<5) +} +func (o *ISP_Type) GetSHARP_FILTER0_SHARP_FILTER_COE01() uint32 { + return (volatile.LoadUint32(&o.SHARP_FILTER0.Reg) & 0x3e0) >> 5 +} +func (o *ISP_Type) SetSHARP_FILTER0_SHARP_FILTER_COE02(value uint32) { + volatile.StoreUint32(&o.SHARP_FILTER0.Reg, volatile.LoadUint32(&o.SHARP_FILTER0.Reg)&^(0x7c00)|value<<10) +} +func (o *ISP_Type) GetSHARP_FILTER0_SHARP_FILTER_COE02() uint32 { + return (volatile.LoadUint32(&o.SHARP_FILTER0.Reg) & 0x7c00) >> 10 +} + +// ISP.SHARP_FILTER1: sharp usm config register 1 +func (o *ISP_Type) SetSHARP_FILTER1_SHARP_FILTER_COE10(value uint32) { + volatile.StoreUint32(&o.SHARP_FILTER1.Reg, volatile.LoadUint32(&o.SHARP_FILTER1.Reg)&^(0x1f)|value) +} +func (o *ISP_Type) GetSHARP_FILTER1_SHARP_FILTER_COE10() uint32 { + return volatile.LoadUint32(&o.SHARP_FILTER1.Reg) & 0x1f +} +func (o *ISP_Type) SetSHARP_FILTER1_SHARP_FILTER_COE11(value uint32) { + volatile.StoreUint32(&o.SHARP_FILTER1.Reg, volatile.LoadUint32(&o.SHARP_FILTER1.Reg)&^(0x3e0)|value<<5) +} +func (o *ISP_Type) GetSHARP_FILTER1_SHARP_FILTER_COE11() uint32 { + return (volatile.LoadUint32(&o.SHARP_FILTER1.Reg) & 0x3e0) >> 5 +} +func (o *ISP_Type) SetSHARP_FILTER1_SHARP_FILTER_COE12(value uint32) { + volatile.StoreUint32(&o.SHARP_FILTER1.Reg, volatile.LoadUint32(&o.SHARP_FILTER1.Reg)&^(0x7c00)|value<<10) +} +func (o *ISP_Type) GetSHARP_FILTER1_SHARP_FILTER_COE12() uint32 { + return (volatile.LoadUint32(&o.SHARP_FILTER1.Reg) & 0x7c00) >> 10 +} + +// ISP.SHARP_FILTER2: sharp usm config register 2 +func (o *ISP_Type) SetSHARP_FILTER2_SHARP_FILTER_COE20(value uint32) { + volatile.StoreUint32(&o.SHARP_FILTER2.Reg, volatile.LoadUint32(&o.SHARP_FILTER2.Reg)&^(0x1f)|value) +} +func (o *ISP_Type) GetSHARP_FILTER2_SHARP_FILTER_COE20() uint32 { + return volatile.LoadUint32(&o.SHARP_FILTER2.Reg) & 0x1f +} +func (o *ISP_Type) SetSHARP_FILTER2_SHARP_FILTER_COE21(value uint32) { + volatile.StoreUint32(&o.SHARP_FILTER2.Reg, volatile.LoadUint32(&o.SHARP_FILTER2.Reg)&^(0x3e0)|value<<5) +} +func (o *ISP_Type) GetSHARP_FILTER2_SHARP_FILTER_COE21() uint32 { + return (volatile.LoadUint32(&o.SHARP_FILTER2.Reg) & 0x3e0) >> 5 +} +func (o *ISP_Type) SetSHARP_FILTER2_SHARP_FILTER_COE22(value uint32) { + volatile.StoreUint32(&o.SHARP_FILTER2.Reg, volatile.LoadUint32(&o.SHARP_FILTER2.Reg)&^(0x7c00)|value<<10) +} +func (o *ISP_Type) GetSHARP_FILTER2_SHARP_FILTER_COE22() uint32 { + return (volatile.LoadUint32(&o.SHARP_FILTER2.Reg) & 0x7c00) >> 10 +} + +// ISP.SHARP_MATRIX_CTRL: sharp pix2matrix ctrl +func (o *ISP_Type) SetSHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TL(value uint32) { + volatile.StoreUint32(&o.SHARP_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetSHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TL() uint32 { + return volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg) & 0xff +} +func (o *ISP_Type) SetSHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TH(value uint32) { + volatile.StoreUint32(&o.SHARP_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetSHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TH() uint32 { + return (volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetSHARP_MATRIX_CTRL_SHARP_PADDING_DATA(value uint32) { + volatile.StoreUint32(&o.SHARP_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetSHARP_MATRIX_CTRL_SHARP_PADDING_DATA() uint32 { + return (volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetSHARP_MATRIX_CTRL_SHARP_PADDING_MODE(value uint32) { + volatile.StoreUint32(&o.SHARP_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *ISP_Type) GetSHARP_MATRIX_CTRL_SHARP_PADDING_MODE() uint32 { + return (volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg) & 0x1000000) >> 24 +} + +// ISP.SHARP_CTRL1: sharp control register 1 +func (o *ISP_Type) SetSHARP_CTRL1_SHARP_GRADIENT_MAX(value uint32) { + volatile.StoreUint32(&o.SHARP_CTRL1.Reg, volatile.LoadUint32(&o.SHARP_CTRL1.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetSHARP_CTRL1_SHARP_GRADIENT_MAX() uint32 { + return volatile.LoadUint32(&o.SHARP_CTRL1.Reg) & 0xff +} + +// ISP.DMA_CNTL: isp dma source trans control register +func (o *ISP_Type) SetDMA_CNTL_DMA_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetDMA_CNTL_DMA_EN() uint32 { + return volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0x1 +} +func (o *ISP_Type) SetDMA_CNTL_DMA_UPDATE(value uint32) { + volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetDMA_CNTL_DMA_UPDATE() uint32 { + return (volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetDMA_CNTL_DMA_DATA_TYPE(value uint32) { + volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0xfc)|value<<2) +} +func (o *ISP_Type) GetDMA_CNTL_DMA_DATA_TYPE() uint32 { + return (volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0xfc) >> 2 +} +func (o *ISP_Type) SetDMA_CNTL_DMA_BURST_LEN(value uint32) { + volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0xfff00)|value<<8) +} +func (o *ISP_Type) GetDMA_CNTL_DMA_BURST_LEN() uint32 { + return (volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0xfff00) >> 8 +} +func (o *ISP_Type) SetDMA_CNTL_DMA_INTERVAL(value uint32) { + volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0xfff00000)|value<<20) +} +func (o *ISP_Type) GetDMA_CNTL_DMA_INTERVAL() uint32 { + return (volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0xfff00000) >> 20 +} + +// ISP.DMA_RAW_DATA: isp dma source total raw number set register +func (o *ISP_Type) SetDMA_RAW_DATA_DMA_RAW_NUM_TOTAL(value uint32) { + volatile.StoreUint32(&o.DMA_RAW_DATA.Reg, volatile.LoadUint32(&o.DMA_RAW_DATA.Reg)&^(0x3fffff)|value) +} +func (o *ISP_Type) GetDMA_RAW_DATA_DMA_RAW_NUM_TOTAL() uint32 { + return volatile.LoadUint32(&o.DMA_RAW_DATA.Reg) & 0x3fffff +} +func (o *ISP_Type) SetDMA_RAW_DATA_DMA_RAW_NUM_TOTAL_SET(value uint32) { + volatile.StoreUint32(&o.DMA_RAW_DATA.Reg, volatile.LoadUint32(&o.DMA_RAW_DATA.Reg)&^(0x80000000)|value<<31) +} +func (o *ISP_Type) GetDMA_RAW_DATA_DMA_RAW_NUM_TOTAL_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_RAW_DATA.Reg) & 0x80000000) >> 31 +} + +// ISP.CAM_CNTL: isp cam source control register +func (o *ISP_Type) SetCAM_CNTL_CAM_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CNTL.Reg, volatile.LoadUint32(&o.CAM_CNTL.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetCAM_CNTL_CAM_EN() uint32 { + return volatile.LoadUint32(&o.CAM_CNTL.Reg) & 0x1 +} +func (o *ISP_Type) SetCAM_CNTL_CAM_UPDATE(value uint32) { + volatile.StoreUint32(&o.CAM_CNTL.Reg, volatile.LoadUint32(&o.CAM_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetCAM_CNTL_CAM_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CAM_CNTL.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetCAM_CNTL_CAM_RESET(value uint32) { + volatile.StoreUint32(&o.CAM_CNTL.Reg, volatile.LoadUint32(&o.CAM_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetCAM_CNTL_CAM_RESET() uint32 { + return (volatile.LoadUint32(&o.CAM_CNTL.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetCAM_CNTL_CAM_CLK_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CNTL.Reg, volatile.LoadUint32(&o.CAM_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetCAM_CNTL_CAM_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CNTL.Reg) & 0x8) >> 3 +} + +// ISP.CAM_CONF: isp cam source config register +func (o *ISP_Type) SetCAM_CONF_CAM_DATA_ORDER(value uint32) { + volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetCAM_CONF_CAM_DATA_ORDER() uint32 { + return volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x1 +} +func (o *ISP_Type) SetCAM_CONF_CAM_2BYTE_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetCAM_CONF_CAM_2BYTE_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetCAM_CONF_CAM_DATA_TYPE(value uint32) { + volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0xfc)|value<<2) +} +func (o *ISP_Type) GetCAM_CONF_CAM_DATA_TYPE() uint32 { + return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0xfc) >> 2 +} +func (o *ISP_Type) SetCAM_CONF_CAM_DE_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x100)|value<<8) +} +func (o *ISP_Type) GetCAM_CONF_CAM_DE_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x100) >> 8 +} +func (o *ISP_Type) SetCAM_CONF_CAM_HSYNC_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x200)|value<<9) +} +func (o *ISP_Type) GetCAM_CONF_CAM_HSYNC_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x200) >> 9 +} +func (o *ISP_Type) SetCAM_CONF_CAM_VSYNC_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x400)|value<<10) +} +func (o *ISP_Type) GetCAM_CONF_CAM_VSYNC_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x400) >> 10 +} +func (o *ISP_Type) SetCAM_CONF_CAM_VSYNC_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x3800)|value<<11) +} +func (o *ISP_Type) GetCAM_CONF_CAM_VSYNC_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x3800) >> 11 +} +func (o *ISP_Type) SetCAM_CONF_CAM_VSYNC_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *ISP_Type) GetCAM_CONF_CAM_VSYNC_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x4000) >> 14 +} + +// ISP.AF_CTRL0: af control register 0 +func (o *ISP_Type) SetAF_CTRL0_AF_AUTO_UPDATE(value uint32) { + volatile.StoreUint32(&o.AF_CTRL0.Reg, volatile.LoadUint32(&o.AF_CTRL0.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetAF_CTRL0_AF_AUTO_UPDATE() uint32 { + return volatile.LoadUint32(&o.AF_CTRL0.Reg) & 0x1 +} +func (o *ISP_Type) SetAF_CTRL0_AF_MANUAL_UPDATE(value uint32) { + volatile.StoreUint32(&o.AF_CTRL0.Reg, volatile.LoadUint32(&o.AF_CTRL0.Reg)&^(0x10)|value<<4) +} +func (o *ISP_Type) GetAF_CTRL0_AF_MANUAL_UPDATE() uint32 { + return (volatile.LoadUint32(&o.AF_CTRL0.Reg) & 0x10) >> 4 +} +func (o *ISP_Type) SetAF_CTRL0_AF_ENV_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.AF_CTRL0.Reg, volatile.LoadUint32(&o.AF_CTRL0.Reg)&^(0xf00)|value<<8) +} +func (o *ISP_Type) GetAF_CTRL0_AF_ENV_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.AF_CTRL0.Reg) & 0xf00) >> 8 +} +func (o *ISP_Type) SetAF_CTRL0_AF_ENV_PERIOD(value uint32) { + volatile.StoreUint32(&o.AF_CTRL0.Reg, volatile.LoadUint32(&o.AF_CTRL0.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetAF_CTRL0_AF_ENV_PERIOD() uint32 { + return (volatile.LoadUint32(&o.AF_CTRL0.Reg) & 0xff0000) >> 16 +} + +// ISP.AF_CTRL1: af control register 1 +func (o *ISP_Type) SetAF_CTRL1_AF_THPIXNUM(value uint32) { + volatile.StoreUint32(&o.AF_CTRL1.Reg, volatile.LoadUint32(&o.AF_CTRL1.Reg)&^(0x3fffff)|value) +} +func (o *ISP_Type) GetAF_CTRL1_AF_THPIXNUM() uint32 { + return volatile.LoadUint32(&o.AF_CTRL1.Reg) & 0x3fffff +} + +// ISP.AF_GEN_TH_CTRL: af gen threshold control register +func (o *ISP_Type) SetAF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MIN(value uint32) { + volatile.StoreUint32(&o.AF_GEN_TH_CTRL.Reg, volatile.LoadUint32(&o.AF_GEN_TH_CTRL.Reg)&^(0xffff)|value) +} +func (o *ISP_Type) GetAF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MIN() uint32 { + return volatile.LoadUint32(&o.AF_GEN_TH_CTRL.Reg) & 0xffff +} +func (o *ISP_Type) SetAF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MAX(value uint32) { + volatile.StoreUint32(&o.AF_GEN_TH_CTRL.Reg, volatile.LoadUint32(&o.AF_GEN_TH_CTRL.Reg)&^(0xffff0000)|value<<16) +} +func (o *ISP_Type) GetAF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MAX() uint32 { + return (volatile.LoadUint32(&o.AF_GEN_TH_CTRL.Reg) & 0xffff0000) >> 16 +} + +// ISP.AF_ENV_USER_TH_SUM: af monitor user sum threshold register +func (o *ISP_Type) SetAF_ENV_USER_TH_SUM(value uint32) { + volatile.StoreUint32(&o.AF_ENV_USER_TH_SUM.Reg, value) +} +func (o *ISP_Type) GetAF_ENV_USER_TH_SUM() uint32 { + return volatile.LoadUint32(&o.AF_ENV_USER_TH_SUM.Reg) +} + +// ISP.AF_ENV_USER_TH_LUM: af monitor user lum threshold register +func (o *ISP_Type) SetAF_ENV_USER_TH_LUM_AF_ENV_USER_THRESHOLD_LUM(value uint32) { + volatile.StoreUint32(&o.AF_ENV_USER_TH_LUM.Reg, volatile.LoadUint32(&o.AF_ENV_USER_TH_LUM.Reg)&^(0x3fffffff)|value) +} +func (o *ISP_Type) GetAF_ENV_USER_TH_LUM_AF_ENV_USER_THRESHOLD_LUM() uint32 { + return volatile.LoadUint32(&o.AF_ENV_USER_TH_LUM.Reg) & 0x3fffffff +} + +// ISP.AF_THRESHOLD: af threshold register +func (o *ISP_Type) SetAF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.AF_THRESHOLD.Reg, volatile.LoadUint32(&o.AF_THRESHOLD.Reg)&^(0xffff)|value) +} +func (o *ISP_Type) GetAF_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.AF_THRESHOLD.Reg) & 0xffff +} +func (o *ISP_Type) SetAF_THRESHOLD_AF_GEN_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.AF_THRESHOLD.Reg, volatile.LoadUint32(&o.AF_THRESHOLD.Reg)&^(0xffff0000)|value<<16) +} +func (o *ISP_Type) GetAF_THRESHOLD_AF_GEN_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.AF_THRESHOLD.Reg) & 0xffff0000) >> 16 +} + +// ISP.AF_HSCALE_A: h-scale of af window a register +func (o *ISP_Type) SetAF_HSCALE_A_AF_RPOINT_A(value uint32) { + volatile.StoreUint32(&o.AF_HSCALE_A.Reg, volatile.LoadUint32(&o.AF_HSCALE_A.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetAF_HSCALE_A_AF_RPOINT_A() uint32 { + return volatile.LoadUint32(&o.AF_HSCALE_A.Reg) & 0xfff +} +func (o *ISP_Type) SetAF_HSCALE_A_AF_LPOINT_A(value uint32) { + volatile.StoreUint32(&o.AF_HSCALE_A.Reg, volatile.LoadUint32(&o.AF_HSCALE_A.Reg)&^(0xfff0000)|value<<16) +} +func (o *ISP_Type) GetAF_HSCALE_A_AF_LPOINT_A() uint32 { + return (volatile.LoadUint32(&o.AF_HSCALE_A.Reg) & 0xfff0000) >> 16 +} + +// ISP.AF_VSCALE_A: v-scale of af window a register +func (o *ISP_Type) SetAF_VSCALE_A_AF_BPOINT_A(value uint32) { + volatile.StoreUint32(&o.AF_VSCALE_A.Reg, volatile.LoadUint32(&o.AF_VSCALE_A.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetAF_VSCALE_A_AF_BPOINT_A() uint32 { + return volatile.LoadUint32(&o.AF_VSCALE_A.Reg) & 0xfff +} +func (o *ISP_Type) SetAF_VSCALE_A_AF_TPOINT_A(value uint32) { + volatile.StoreUint32(&o.AF_VSCALE_A.Reg, volatile.LoadUint32(&o.AF_VSCALE_A.Reg)&^(0xfff0000)|value<<16) +} +func (o *ISP_Type) GetAF_VSCALE_A_AF_TPOINT_A() uint32 { + return (volatile.LoadUint32(&o.AF_VSCALE_A.Reg) & 0xfff0000) >> 16 +} + +// ISP.AF_HSCALE_B: h-scale of af window b register +func (o *ISP_Type) SetAF_HSCALE_B_AF_RPOINT_B(value uint32) { + volatile.StoreUint32(&o.AF_HSCALE_B.Reg, volatile.LoadUint32(&o.AF_HSCALE_B.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetAF_HSCALE_B_AF_RPOINT_B() uint32 { + return volatile.LoadUint32(&o.AF_HSCALE_B.Reg) & 0xfff +} +func (o *ISP_Type) SetAF_HSCALE_B_AF_LPOINT_B(value uint32) { + volatile.StoreUint32(&o.AF_HSCALE_B.Reg, volatile.LoadUint32(&o.AF_HSCALE_B.Reg)&^(0xfff0000)|value<<16) +} +func (o *ISP_Type) GetAF_HSCALE_B_AF_LPOINT_B() uint32 { + return (volatile.LoadUint32(&o.AF_HSCALE_B.Reg) & 0xfff0000) >> 16 +} + +// ISP.AF_VSCALE_B: v-scale of af window b register +func (o *ISP_Type) SetAF_VSCALE_B_AF_BPOINT_B(value uint32) { + volatile.StoreUint32(&o.AF_VSCALE_B.Reg, volatile.LoadUint32(&o.AF_VSCALE_B.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetAF_VSCALE_B_AF_BPOINT_B() uint32 { + return volatile.LoadUint32(&o.AF_VSCALE_B.Reg) & 0xfff +} +func (o *ISP_Type) SetAF_VSCALE_B_AF_TPOINT_B(value uint32) { + volatile.StoreUint32(&o.AF_VSCALE_B.Reg, volatile.LoadUint32(&o.AF_VSCALE_B.Reg)&^(0xfff0000)|value<<16) +} +func (o *ISP_Type) GetAF_VSCALE_B_AF_TPOINT_B() uint32 { + return (volatile.LoadUint32(&o.AF_VSCALE_B.Reg) & 0xfff0000) >> 16 +} + +// ISP.AF_HSCALE_C: v-scale of af window c register +func (o *ISP_Type) SetAF_HSCALE_C_AF_RPOINT_C(value uint32) { + volatile.StoreUint32(&o.AF_HSCALE_C.Reg, volatile.LoadUint32(&o.AF_HSCALE_C.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetAF_HSCALE_C_AF_RPOINT_C() uint32 { + return volatile.LoadUint32(&o.AF_HSCALE_C.Reg) & 0xfff +} +func (o *ISP_Type) SetAF_HSCALE_C_AF_LPOINT_C(value uint32) { + volatile.StoreUint32(&o.AF_HSCALE_C.Reg, volatile.LoadUint32(&o.AF_HSCALE_C.Reg)&^(0xfff0000)|value<<16) +} +func (o *ISP_Type) GetAF_HSCALE_C_AF_LPOINT_C() uint32 { + return (volatile.LoadUint32(&o.AF_HSCALE_C.Reg) & 0xfff0000) >> 16 +} + +// ISP.AF_VSCALE_C: v-scale of af window c register +func (o *ISP_Type) SetAF_VSCALE_C_AF_BPOINT_C(value uint32) { + volatile.StoreUint32(&o.AF_VSCALE_C.Reg, volatile.LoadUint32(&o.AF_VSCALE_C.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetAF_VSCALE_C_AF_BPOINT_C() uint32 { + return volatile.LoadUint32(&o.AF_VSCALE_C.Reg) & 0xfff +} +func (o *ISP_Type) SetAF_VSCALE_C_AF_TPOINT_C(value uint32) { + volatile.StoreUint32(&o.AF_VSCALE_C.Reg, volatile.LoadUint32(&o.AF_VSCALE_C.Reg)&^(0xfff0000)|value<<16) +} +func (o *ISP_Type) GetAF_VSCALE_C_AF_TPOINT_C() uint32 { + return (volatile.LoadUint32(&o.AF_VSCALE_C.Reg) & 0xfff0000) >> 16 +} + +// ISP.AF_SUM_A: result of sum of af window a +func (o *ISP_Type) SetAF_SUM_A_AF_SUMA(value uint32) { + volatile.StoreUint32(&o.AF_SUM_A.Reg, volatile.LoadUint32(&o.AF_SUM_A.Reg)&^(0x3fffffff)|value) +} +func (o *ISP_Type) GetAF_SUM_A_AF_SUMA() uint32 { + return volatile.LoadUint32(&o.AF_SUM_A.Reg) & 0x3fffffff +} + +// ISP.AF_SUM_B: result of sum of af window b +func (o *ISP_Type) SetAF_SUM_B_AF_SUMB(value uint32) { + volatile.StoreUint32(&o.AF_SUM_B.Reg, volatile.LoadUint32(&o.AF_SUM_B.Reg)&^(0x3fffffff)|value) +} +func (o *ISP_Type) GetAF_SUM_B_AF_SUMB() uint32 { + return volatile.LoadUint32(&o.AF_SUM_B.Reg) & 0x3fffffff +} + +// ISP.AF_SUM_C: result of sum of af window c +func (o *ISP_Type) SetAF_SUM_C_AF_SUMC(value uint32) { + volatile.StoreUint32(&o.AF_SUM_C.Reg, volatile.LoadUint32(&o.AF_SUM_C.Reg)&^(0x3fffffff)|value) +} +func (o *ISP_Type) GetAF_SUM_C_AF_SUMC() uint32 { + return volatile.LoadUint32(&o.AF_SUM_C.Reg) & 0x3fffffff +} + +// ISP.AF_LUM_A: result of lum of af window a +func (o *ISP_Type) SetAF_LUM_A_AF_LUMA(value uint32) { + volatile.StoreUint32(&o.AF_LUM_A.Reg, volatile.LoadUint32(&o.AF_LUM_A.Reg)&^(0xfffffff)|value) +} +func (o *ISP_Type) GetAF_LUM_A_AF_LUMA() uint32 { + return volatile.LoadUint32(&o.AF_LUM_A.Reg) & 0xfffffff +} + +// ISP.AF_LUM_B: result of lum of af window b +func (o *ISP_Type) SetAF_LUM_B_AF_LUMB(value uint32) { + volatile.StoreUint32(&o.AF_LUM_B.Reg, volatile.LoadUint32(&o.AF_LUM_B.Reg)&^(0xfffffff)|value) +} +func (o *ISP_Type) GetAF_LUM_B_AF_LUMB() uint32 { + return volatile.LoadUint32(&o.AF_LUM_B.Reg) & 0xfffffff +} + +// ISP.AF_LUM_C: result of lum of af window c +func (o *ISP_Type) SetAF_LUM_C_AF_LUMC(value uint32) { + volatile.StoreUint32(&o.AF_LUM_C.Reg, volatile.LoadUint32(&o.AF_LUM_C.Reg)&^(0xfffffff)|value) +} +func (o *ISP_Type) GetAF_LUM_C_AF_LUMC() uint32 { + return volatile.LoadUint32(&o.AF_LUM_C.Reg) & 0xfffffff +} + +// ISP.AWB_MODE: awb mode control register +func (o *ISP_Type) SetAWB_MODE(value uint32) { + volatile.StoreUint32(&o.AWB_MODE.Reg, volatile.LoadUint32(&o.AWB_MODE.Reg)&^(0x3)|value) +} +func (o *ISP_Type) GetAWB_MODE() uint32 { + return volatile.LoadUint32(&o.AWB_MODE.Reg) & 0x3 +} +func (o *ISP_Type) SetAWB_MODE_AWB_SAMPLE(value uint32) { + volatile.StoreUint32(&o.AWB_MODE.Reg, volatile.LoadUint32(&o.AWB_MODE.Reg)&^(0x10)|value<<4) +} +func (o *ISP_Type) GetAWB_MODE_AWB_SAMPLE() uint32 { + return (volatile.LoadUint32(&o.AWB_MODE.Reg) & 0x10) >> 4 +} + +// ISP.AWB_HSCALE: h-scale of awb window +func (o *ISP_Type) SetAWB_HSCALE_AWB_RPOINT(value uint32) { + volatile.StoreUint32(&o.AWB_HSCALE.Reg, volatile.LoadUint32(&o.AWB_HSCALE.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetAWB_HSCALE_AWB_RPOINT() uint32 { + return volatile.LoadUint32(&o.AWB_HSCALE.Reg) & 0xfff +} +func (o *ISP_Type) SetAWB_HSCALE_AWB_LPOINT(value uint32) { + volatile.StoreUint32(&o.AWB_HSCALE.Reg, volatile.LoadUint32(&o.AWB_HSCALE.Reg)&^(0xfff0000)|value<<16) +} +func (o *ISP_Type) GetAWB_HSCALE_AWB_LPOINT() uint32 { + return (volatile.LoadUint32(&o.AWB_HSCALE.Reg) & 0xfff0000) >> 16 +} + +// ISP.AWB_VSCALE: v-scale of awb window +func (o *ISP_Type) SetAWB_VSCALE_AWB_BPOINT(value uint32) { + volatile.StoreUint32(&o.AWB_VSCALE.Reg, volatile.LoadUint32(&o.AWB_VSCALE.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetAWB_VSCALE_AWB_BPOINT() uint32 { + return volatile.LoadUint32(&o.AWB_VSCALE.Reg) & 0xfff +} +func (o *ISP_Type) SetAWB_VSCALE_AWB_TPOINT(value uint32) { + volatile.StoreUint32(&o.AWB_VSCALE.Reg, volatile.LoadUint32(&o.AWB_VSCALE.Reg)&^(0xfff0000)|value<<16) +} +func (o *ISP_Type) GetAWB_VSCALE_AWB_TPOINT() uint32 { + return (volatile.LoadUint32(&o.AWB_VSCALE.Reg) & 0xfff0000) >> 16 +} + +// ISP.AWB_TH_LUM: awb lum threshold register +func (o *ISP_Type) SetAWB_TH_LUM_AWB_MIN_LUM(value uint32) { + volatile.StoreUint32(&o.AWB_TH_LUM.Reg, volatile.LoadUint32(&o.AWB_TH_LUM.Reg)&^(0x3ff)|value) +} +func (o *ISP_Type) GetAWB_TH_LUM_AWB_MIN_LUM() uint32 { + return volatile.LoadUint32(&o.AWB_TH_LUM.Reg) & 0x3ff +} +func (o *ISP_Type) SetAWB_TH_LUM_AWB_MAX_LUM(value uint32) { + volatile.StoreUint32(&o.AWB_TH_LUM.Reg, volatile.LoadUint32(&o.AWB_TH_LUM.Reg)&^(0x3ff0000)|value<<16) +} +func (o *ISP_Type) GetAWB_TH_LUM_AWB_MAX_LUM() uint32 { + return (volatile.LoadUint32(&o.AWB_TH_LUM.Reg) & 0x3ff0000) >> 16 +} + +// ISP.AWB_TH_RG: awb r/g threshold register +func (o *ISP_Type) SetAWB_TH_RG_AWB_MIN_RG(value uint32) { + volatile.StoreUint32(&o.AWB_TH_RG.Reg, volatile.LoadUint32(&o.AWB_TH_RG.Reg)&^(0x3ff)|value) +} +func (o *ISP_Type) GetAWB_TH_RG_AWB_MIN_RG() uint32 { + return volatile.LoadUint32(&o.AWB_TH_RG.Reg) & 0x3ff +} +func (o *ISP_Type) SetAWB_TH_RG_AWB_MAX_RG(value uint32) { + volatile.StoreUint32(&o.AWB_TH_RG.Reg, volatile.LoadUint32(&o.AWB_TH_RG.Reg)&^(0x3ff0000)|value<<16) +} +func (o *ISP_Type) GetAWB_TH_RG_AWB_MAX_RG() uint32 { + return (volatile.LoadUint32(&o.AWB_TH_RG.Reg) & 0x3ff0000) >> 16 +} + +// ISP.AWB_TH_BG: awb b/g threshold register +func (o *ISP_Type) SetAWB_TH_BG_AWB_MIN_BG(value uint32) { + volatile.StoreUint32(&o.AWB_TH_BG.Reg, volatile.LoadUint32(&o.AWB_TH_BG.Reg)&^(0x3ff)|value) +} +func (o *ISP_Type) GetAWB_TH_BG_AWB_MIN_BG() uint32 { + return volatile.LoadUint32(&o.AWB_TH_BG.Reg) & 0x3ff +} +func (o *ISP_Type) SetAWB_TH_BG_AWB_MAX_BG(value uint32) { + volatile.StoreUint32(&o.AWB_TH_BG.Reg, volatile.LoadUint32(&o.AWB_TH_BG.Reg)&^(0x3ff0000)|value<<16) +} +func (o *ISP_Type) GetAWB_TH_BG_AWB_MAX_BG() uint32 { + return (volatile.LoadUint32(&o.AWB_TH_BG.Reg) & 0x3ff0000) >> 16 +} + +// ISP.AWB0_WHITE_CNT: result of awb white point number +func (o *ISP_Type) SetAWB0_WHITE_CNT(value uint32) { + volatile.StoreUint32(&o.AWB0_WHITE_CNT.Reg, volatile.LoadUint32(&o.AWB0_WHITE_CNT.Reg)&^(0xffffff)|value) +} +func (o *ISP_Type) GetAWB0_WHITE_CNT() uint32 { + return volatile.LoadUint32(&o.AWB0_WHITE_CNT.Reg) & 0xffffff +} + +// ISP.AWB0_ACC_R: result of accumulate of r channel of all white points +func (o *ISP_Type) SetAWB0_ACC_R(value uint32) { + volatile.StoreUint32(&o.AWB0_ACC_R.Reg, value) +} +func (o *ISP_Type) GetAWB0_ACC_R() uint32 { + return volatile.LoadUint32(&o.AWB0_ACC_R.Reg) +} + +// ISP.AWB0_ACC_G: result of accumulate of g channel of all white points +func (o *ISP_Type) SetAWB0_ACC_G(value uint32) { + volatile.StoreUint32(&o.AWB0_ACC_G.Reg, value) +} +func (o *ISP_Type) GetAWB0_ACC_G() uint32 { + return volatile.LoadUint32(&o.AWB0_ACC_G.Reg) +} + +// ISP.AWB0_ACC_B: result of accumulate of b channel of all white points +func (o *ISP_Type) SetAWB0_ACC_B(value uint32) { + volatile.StoreUint32(&o.AWB0_ACC_B.Reg, value) +} +func (o *ISP_Type) GetAWB0_ACC_B() uint32 { + return volatile.LoadUint32(&o.AWB0_ACC_B.Reg) +} + +// ISP.COLOR_CTRL: color control register +func (o *ISP_Type) SetCOLOR_CTRL_COLOR_SATURATION(value uint32) { + volatile.StoreUint32(&o.COLOR_CTRL.Reg, volatile.LoadUint32(&o.COLOR_CTRL.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetCOLOR_CTRL_COLOR_SATURATION() uint32 { + return volatile.LoadUint32(&o.COLOR_CTRL.Reg) & 0xff +} +func (o *ISP_Type) SetCOLOR_CTRL_COLOR_HUE(value uint32) { + volatile.StoreUint32(&o.COLOR_CTRL.Reg, volatile.LoadUint32(&o.COLOR_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetCOLOR_CTRL_COLOR_HUE() uint32 { + return (volatile.LoadUint32(&o.COLOR_CTRL.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetCOLOR_CTRL_COLOR_CONTRAST(value uint32) { + volatile.StoreUint32(&o.COLOR_CTRL.Reg, volatile.LoadUint32(&o.COLOR_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetCOLOR_CTRL_COLOR_CONTRAST() uint32 { + return (volatile.LoadUint32(&o.COLOR_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetCOLOR_CTRL_COLOR_BRIGHTNESS(value uint32) { + volatile.StoreUint32(&o.COLOR_CTRL.Reg, volatile.LoadUint32(&o.COLOR_CTRL.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetCOLOR_CTRL_COLOR_BRIGHTNESS() uint32 { + return (volatile.LoadUint32(&o.COLOR_CTRL.Reg) & 0xff000000) >> 24 +} + +// ISP.BLC_VALUE: blc black level register +func (o *ISP_Type) SetBLC_VALUE_BLC_R3_VALUE(value uint32) { + volatile.StoreUint32(&o.BLC_VALUE.Reg, volatile.LoadUint32(&o.BLC_VALUE.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetBLC_VALUE_BLC_R3_VALUE() uint32 { + return volatile.LoadUint32(&o.BLC_VALUE.Reg) & 0xff +} +func (o *ISP_Type) SetBLC_VALUE_BLC_R2_VALUE(value uint32) { + volatile.StoreUint32(&o.BLC_VALUE.Reg, volatile.LoadUint32(&o.BLC_VALUE.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetBLC_VALUE_BLC_R2_VALUE() uint32 { + return (volatile.LoadUint32(&o.BLC_VALUE.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetBLC_VALUE_BLC_R1_VALUE(value uint32) { + volatile.StoreUint32(&o.BLC_VALUE.Reg, volatile.LoadUint32(&o.BLC_VALUE.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetBLC_VALUE_BLC_R1_VALUE() uint32 { + return (volatile.LoadUint32(&o.BLC_VALUE.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetBLC_VALUE_BLC_R0_VALUE(value uint32) { + volatile.StoreUint32(&o.BLC_VALUE.Reg, volatile.LoadUint32(&o.BLC_VALUE.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetBLC_VALUE_BLC_R0_VALUE() uint32 { + return (volatile.LoadUint32(&o.BLC_VALUE.Reg) & 0xff000000) >> 24 +} + +// ISP.BLC_CTRL0: blc stretch control register +func (o *ISP_Type) SetBLC_CTRL0_BLC_R3_STRETCH(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL0.Reg, volatile.LoadUint32(&o.BLC_CTRL0.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetBLC_CTRL0_BLC_R3_STRETCH() uint32 { + return volatile.LoadUint32(&o.BLC_CTRL0.Reg) & 0x1 +} +func (o *ISP_Type) SetBLC_CTRL0_BLC_R2_STRETCH(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL0.Reg, volatile.LoadUint32(&o.BLC_CTRL0.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetBLC_CTRL0_BLC_R2_STRETCH() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL0.Reg) & 0x2) >> 1 +} +func (o *ISP_Type) SetBLC_CTRL0_BLC_R1_STRETCH(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL0.Reg, volatile.LoadUint32(&o.BLC_CTRL0.Reg)&^(0x4)|value<<2) +} +func (o *ISP_Type) GetBLC_CTRL0_BLC_R1_STRETCH() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL0.Reg) & 0x4) >> 2 +} +func (o *ISP_Type) SetBLC_CTRL0_BLC_R0_STRETCH(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL0.Reg, volatile.LoadUint32(&o.BLC_CTRL0.Reg)&^(0x8)|value<<3) +} +func (o *ISP_Type) GetBLC_CTRL0_BLC_R0_STRETCH() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL0.Reg) & 0x8) >> 3 +} + +// ISP.BLC_CTRL1: blc window control register +func (o *ISP_Type) SetBLC_CTRL1_BLC_WINDOW_TOP(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x7ff)|value) +} +func (o *ISP_Type) GetBLC_CTRL1_BLC_WINDOW_TOP() uint32 { + return volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x7ff +} +func (o *ISP_Type) SetBLC_CTRL1_BLC_WINDOW_LEFT(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x3ff800)|value<<11) +} +func (o *ISP_Type) GetBLC_CTRL1_BLC_WINDOW_LEFT() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x3ff800) >> 11 +} +func (o *ISP_Type) SetBLC_CTRL1_BLC_WINDOW_VNUM(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x3c00000)|value<<22) +} +func (o *ISP_Type) GetBLC_CTRL1_BLC_WINDOW_VNUM() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x3c00000) >> 22 +} +func (o *ISP_Type) SetBLC_CTRL1_BLC_WINDOW_HNUM(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x3c000000)|value<<26) +} +func (o *ISP_Type) GetBLC_CTRL1_BLC_WINDOW_HNUM() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x3c000000) >> 26 +} +func (o *ISP_Type) SetBLC_CTRL1_BLC_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *ISP_Type) GetBLC_CTRL1_BLC_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x40000000) >> 30 +} + +// ISP.BLC_CTRL2: blc black threshold control register +func (o *ISP_Type) SetBLC_CTRL2_BLC_R3_TH(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL2.Reg, volatile.LoadUint32(&o.BLC_CTRL2.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetBLC_CTRL2_BLC_R3_TH() uint32 { + return volatile.LoadUint32(&o.BLC_CTRL2.Reg) & 0xff +} +func (o *ISP_Type) SetBLC_CTRL2_BLC_R2_TH(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL2.Reg, volatile.LoadUint32(&o.BLC_CTRL2.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetBLC_CTRL2_BLC_R2_TH() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL2.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetBLC_CTRL2_BLC_R1_TH(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL2.Reg, volatile.LoadUint32(&o.BLC_CTRL2.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetBLC_CTRL2_BLC_R1_TH() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL2.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetBLC_CTRL2_BLC_R0_TH(value uint32) { + volatile.StoreUint32(&o.BLC_CTRL2.Reg, volatile.LoadUint32(&o.BLC_CTRL2.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetBLC_CTRL2_BLC_R0_TH() uint32 { + return (volatile.LoadUint32(&o.BLC_CTRL2.Reg) & 0xff000000) >> 24 +} + +// ISP.BLC_MEAN: results of the average of black window +func (o *ISP_Type) SetBLC_MEAN_BLC_R3_MEAN(value uint32) { + volatile.StoreUint32(&o.BLC_MEAN.Reg, volatile.LoadUint32(&o.BLC_MEAN.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetBLC_MEAN_BLC_R3_MEAN() uint32 { + return volatile.LoadUint32(&o.BLC_MEAN.Reg) & 0xff +} +func (o *ISP_Type) SetBLC_MEAN_BLC_R2_MEAN(value uint32) { + volatile.StoreUint32(&o.BLC_MEAN.Reg, volatile.LoadUint32(&o.BLC_MEAN.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetBLC_MEAN_BLC_R2_MEAN() uint32 { + return (volatile.LoadUint32(&o.BLC_MEAN.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetBLC_MEAN_BLC_R1_MEAN(value uint32) { + volatile.StoreUint32(&o.BLC_MEAN.Reg, volatile.LoadUint32(&o.BLC_MEAN.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetBLC_MEAN_BLC_R1_MEAN() uint32 { + return (volatile.LoadUint32(&o.BLC_MEAN.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetBLC_MEAN_BLC_R0_MEAN(value uint32) { + volatile.StoreUint32(&o.BLC_MEAN.Reg, volatile.LoadUint32(&o.BLC_MEAN.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetBLC_MEAN_BLC_R0_MEAN() uint32 { + return (volatile.LoadUint32(&o.BLC_MEAN.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_MODE: histogram mode control register +func (o *ISP_Type) SetHIST_MODE(value uint32) { + volatile.StoreUint32(&o.HIST_MODE.Reg, volatile.LoadUint32(&o.HIST_MODE.Reg)&^(0x7)|value) +} +func (o *ISP_Type) GetHIST_MODE() uint32 { + return volatile.LoadUint32(&o.HIST_MODE.Reg) & 0x7 +} + +// ISP.HIST_COEFF: histogram rgb to gray coefficients register +func (o *ISP_Type) SetHIST_COEFF_B(value uint32) { + volatile.StoreUint32(&o.HIST_COEFF.Reg, volatile.LoadUint32(&o.HIST_COEFF.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_COEFF_B() uint32 { + return volatile.LoadUint32(&o.HIST_COEFF.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_COEFF_G(value uint32) { + volatile.StoreUint32(&o.HIST_COEFF.Reg, volatile.LoadUint32(&o.HIST_COEFF.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_COEFF_G() uint32 { + return (volatile.LoadUint32(&o.HIST_COEFF.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_COEFF_R(value uint32) { + volatile.StoreUint32(&o.HIST_COEFF.Reg, volatile.LoadUint32(&o.HIST_COEFF.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_COEFF_R() uint32 { + return (volatile.LoadUint32(&o.HIST_COEFF.Reg) & 0xff0000) >> 16 +} + +// ISP.HIST_OFFS: histogram window offsets register +func (o *ISP_Type) SetHIST_OFFS_HIST_Y_OFFS(value uint32) { + volatile.StoreUint32(&o.HIST_OFFS.Reg, volatile.LoadUint32(&o.HIST_OFFS.Reg)&^(0xfff)|value) +} +func (o *ISP_Type) GetHIST_OFFS_HIST_Y_OFFS() uint32 { + return volatile.LoadUint32(&o.HIST_OFFS.Reg) & 0xfff +} +func (o *ISP_Type) SetHIST_OFFS_HIST_X_OFFS(value uint32) { + volatile.StoreUint32(&o.HIST_OFFS.Reg, volatile.LoadUint32(&o.HIST_OFFS.Reg)&^(0xfff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_OFFS_HIST_X_OFFS() uint32 { + return (volatile.LoadUint32(&o.HIST_OFFS.Reg) & 0xfff0000) >> 16 +} + +// ISP.HIST_SIZE: histogram sub-window size register +func (o *ISP_Type) SetHIST_SIZE_HIST_Y_SIZE(value uint32) { + volatile.StoreUint32(&o.HIST_SIZE.Reg, volatile.LoadUint32(&o.HIST_SIZE.Reg)&^(0x1ff)|value) +} +func (o *ISP_Type) GetHIST_SIZE_HIST_Y_SIZE() uint32 { + return volatile.LoadUint32(&o.HIST_SIZE.Reg) & 0x1ff +} +func (o *ISP_Type) SetHIST_SIZE_HIST_X_SIZE(value uint32) { + volatile.StoreUint32(&o.HIST_SIZE.Reg, volatile.LoadUint32(&o.HIST_SIZE.Reg)&^(0x1ff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_SIZE_HIST_X_SIZE() uint32 { + return (volatile.LoadUint32(&o.HIST_SIZE.Reg) & 0x1ff0000) >> 16 +} + +// ISP.HIST_SEG0: histogram bin control register 0 +func (o *ISP_Type) SetHIST_SEG0_HIST_SEG_3_4(value uint32) { + volatile.StoreUint32(&o.HIST_SEG0.Reg, volatile.LoadUint32(&o.HIST_SEG0.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_SEG0_HIST_SEG_3_4() uint32 { + return volatile.LoadUint32(&o.HIST_SEG0.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_SEG0_HIST_SEG_2_3(value uint32) { + volatile.StoreUint32(&o.HIST_SEG0.Reg, volatile.LoadUint32(&o.HIST_SEG0.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_SEG0_HIST_SEG_2_3() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG0.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_SEG0_HIST_SEG_1_2(value uint32) { + volatile.StoreUint32(&o.HIST_SEG0.Reg, volatile.LoadUint32(&o.HIST_SEG0.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_SEG0_HIST_SEG_1_2() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG0.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetHIST_SEG0_HIST_SEG_0_1(value uint32) { + volatile.StoreUint32(&o.HIST_SEG0.Reg, volatile.LoadUint32(&o.HIST_SEG0.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetHIST_SEG0_HIST_SEG_0_1() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG0.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_SEG1: histogram bin control register 1 +func (o *ISP_Type) SetHIST_SEG1_HIST_SEG_7_8(value uint32) { + volatile.StoreUint32(&o.HIST_SEG1.Reg, volatile.LoadUint32(&o.HIST_SEG1.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_SEG1_HIST_SEG_7_8() uint32 { + return volatile.LoadUint32(&o.HIST_SEG1.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_SEG1_HIST_SEG_6_7(value uint32) { + volatile.StoreUint32(&o.HIST_SEG1.Reg, volatile.LoadUint32(&o.HIST_SEG1.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_SEG1_HIST_SEG_6_7() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG1.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_SEG1_HIST_SEG_5_6(value uint32) { + volatile.StoreUint32(&o.HIST_SEG1.Reg, volatile.LoadUint32(&o.HIST_SEG1.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_SEG1_HIST_SEG_5_6() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG1.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetHIST_SEG1_HIST_SEG_4_5(value uint32) { + volatile.StoreUint32(&o.HIST_SEG1.Reg, volatile.LoadUint32(&o.HIST_SEG1.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetHIST_SEG1_HIST_SEG_4_5() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG1.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_SEG2: histogram bin control register 2 +func (o *ISP_Type) SetHIST_SEG2_HIST_SEG_11_12(value uint32) { + volatile.StoreUint32(&o.HIST_SEG2.Reg, volatile.LoadUint32(&o.HIST_SEG2.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_SEG2_HIST_SEG_11_12() uint32 { + return volatile.LoadUint32(&o.HIST_SEG2.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_SEG2_HIST_SEG_10_11(value uint32) { + volatile.StoreUint32(&o.HIST_SEG2.Reg, volatile.LoadUint32(&o.HIST_SEG2.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_SEG2_HIST_SEG_10_11() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG2.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_SEG2_HIST_SEG_9_10(value uint32) { + volatile.StoreUint32(&o.HIST_SEG2.Reg, volatile.LoadUint32(&o.HIST_SEG2.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_SEG2_HIST_SEG_9_10() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG2.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetHIST_SEG2_HIST_SEG_8_9(value uint32) { + volatile.StoreUint32(&o.HIST_SEG2.Reg, volatile.LoadUint32(&o.HIST_SEG2.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetHIST_SEG2_HIST_SEG_8_9() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG2.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_SEG3: histogram bin control register 3 +func (o *ISP_Type) SetHIST_SEG3_HIST_SEG_14_15(value uint32) { + volatile.StoreUint32(&o.HIST_SEG3.Reg, volatile.LoadUint32(&o.HIST_SEG3.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_SEG3_HIST_SEG_14_15() uint32 { + return volatile.LoadUint32(&o.HIST_SEG3.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_SEG3_HIST_SEG_13_14(value uint32) { + volatile.StoreUint32(&o.HIST_SEG3.Reg, volatile.LoadUint32(&o.HIST_SEG3.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_SEG3_HIST_SEG_13_14() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG3.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_SEG3_HIST_SEG_12_13(value uint32) { + volatile.StoreUint32(&o.HIST_SEG3.Reg, volatile.LoadUint32(&o.HIST_SEG3.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_SEG3_HIST_SEG_12_13() uint32 { + return (volatile.LoadUint32(&o.HIST_SEG3.Reg) & 0xff0000) >> 16 +} + +// ISP.HIST_WEIGHT0: histogram sub-window weight register 0 +func (o *ISP_Type) SetHIST_WEIGHT0_HIST_WEIGHT_03(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT0.Reg, volatile.LoadUint32(&o.HIST_WEIGHT0.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_WEIGHT0_HIST_WEIGHT_03() uint32 { + return volatile.LoadUint32(&o.HIST_WEIGHT0.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_WEIGHT0_HIST_WEIGHT_02(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT0.Reg, volatile.LoadUint32(&o.HIST_WEIGHT0.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_WEIGHT0_HIST_WEIGHT_02() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT0.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_WEIGHT0_HIST_WEIGHT_01(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT0.Reg, volatile.LoadUint32(&o.HIST_WEIGHT0.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_WEIGHT0_HIST_WEIGHT_01() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT0.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetHIST_WEIGHT0_HIST_WEIGHT_00(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT0.Reg, volatile.LoadUint32(&o.HIST_WEIGHT0.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetHIST_WEIGHT0_HIST_WEIGHT_00() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT0.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_WEIGHT1: histogram sub-window weight register 1 +func (o *ISP_Type) SetHIST_WEIGHT1_HIST_WEIGHT_12(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT1.Reg, volatile.LoadUint32(&o.HIST_WEIGHT1.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_WEIGHT1_HIST_WEIGHT_12() uint32 { + return volatile.LoadUint32(&o.HIST_WEIGHT1.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_WEIGHT1_HIST_WEIGHT_11(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT1.Reg, volatile.LoadUint32(&o.HIST_WEIGHT1.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_WEIGHT1_HIST_WEIGHT_11() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT1.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_WEIGHT1_HIST_WEIGHT_10(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT1.Reg, volatile.LoadUint32(&o.HIST_WEIGHT1.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_WEIGHT1_HIST_WEIGHT_10() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT1.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetHIST_WEIGHT1_HIST_WEIGHT_04(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT1.Reg, volatile.LoadUint32(&o.HIST_WEIGHT1.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetHIST_WEIGHT1_HIST_WEIGHT_04() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT1.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_WEIGHT2: histogram sub-window weight register 2 +func (o *ISP_Type) SetHIST_WEIGHT2_HIST_WEIGHT_21(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT2.Reg, volatile.LoadUint32(&o.HIST_WEIGHT2.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_WEIGHT2_HIST_WEIGHT_21() uint32 { + return volatile.LoadUint32(&o.HIST_WEIGHT2.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_WEIGHT2_HIST_WEIGHT_20(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT2.Reg, volatile.LoadUint32(&o.HIST_WEIGHT2.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_WEIGHT2_HIST_WEIGHT_20() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT2.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_WEIGHT2_HIST_WEIGHT_14(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT2.Reg, volatile.LoadUint32(&o.HIST_WEIGHT2.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_WEIGHT2_HIST_WEIGHT_14() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT2.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetHIST_WEIGHT2_HIST_WEIGHT_13(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT2.Reg, volatile.LoadUint32(&o.HIST_WEIGHT2.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetHIST_WEIGHT2_HIST_WEIGHT_13() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT2.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_WEIGHT3: histogram sub-window weight register 3 +func (o *ISP_Type) SetHIST_WEIGHT3_HIST_WEIGHT_30(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT3.Reg, volatile.LoadUint32(&o.HIST_WEIGHT3.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_WEIGHT3_HIST_WEIGHT_30() uint32 { + return volatile.LoadUint32(&o.HIST_WEIGHT3.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_WEIGHT3_HIST_WEIGHT_24(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT3.Reg, volatile.LoadUint32(&o.HIST_WEIGHT3.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_WEIGHT3_HIST_WEIGHT_24() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT3.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_WEIGHT3_HIST_WEIGHT_23(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT3.Reg, volatile.LoadUint32(&o.HIST_WEIGHT3.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_WEIGHT3_HIST_WEIGHT_23() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT3.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetHIST_WEIGHT3_HIST_WEIGHT_22(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT3.Reg, volatile.LoadUint32(&o.HIST_WEIGHT3.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetHIST_WEIGHT3_HIST_WEIGHT_22() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT3.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_WEIGHT4: histogram sub-window weight register 4 +func (o *ISP_Type) SetHIST_WEIGHT4_HIST_WEIGHT_34(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT4.Reg, volatile.LoadUint32(&o.HIST_WEIGHT4.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_WEIGHT4_HIST_WEIGHT_34() uint32 { + return volatile.LoadUint32(&o.HIST_WEIGHT4.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_WEIGHT4_HIST_WEIGHT_33(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT4.Reg, volatile.LoadUint32(&o.HIST_WEIGHT4.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_WEIGHT4_HIST_WEIGHT_33() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT4.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_WEIGHT4_HIST_WEIGHT_32(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT4.Reg, volatile.LoadUint32(&o.HIST_WEIGHT4.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_WEIGHT4_HIST_WEIGHT_32() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT4.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetHIST_WEIGHT4_HIST_WEIGHT_31(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT4.Reg, volatile.LoadUint32(&o.HIST_WEIGHT4.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetHIST_WEIGHT4_HIST_WEIGHT_31() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT4.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_WEIGHT5: histogram sub-window weight register 5 +func (o *ISP_Type) SetHIST_WEIGHT5_HIST_WEIGHT_43(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT5.Reg, volatile.LoadUint32(&o.HIST_WEIGHT5.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_WEIGHT5_HIST_WEIGHT_43() uint32 { + return volatile.LoadUint32(&o.HIST_WEIGHT5.Reg) & 0xff +} +func (o *ISP_Type) SetHIST_WEIGHT5_HIST_WEIGHT_42(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT5.Reg, volatile.LoadUint32(&o.HIST_WEIGHT5.Reg)&^(0xff00)|value<<8) +} +func (o *ISP_Type) GetHIST_WEIGHT5_HIST_WEIGHT_42() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT5.Reg) & 0xff00) >> 8 +} +func (o *ISP_Type) SetHIST_WEIGHT5_HIST_WEIGHT_41(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT5.Reg, volatile.LoadUint32(&o.HIST_WEIGHT5.Reg)&^(0xff0000)|value<<16) +} +func (o *ISP_Type) GetHIST_WEIGHT5_HIST_WEIGHT_41() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT5.Reg) & 0xff0000) >> 16 +} +func (o *ISP_Type) SetHIST_WEIGHT5_HIST_WEIGHT_40(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT5.Reg, volatile.LoadUint32(&o.HIST_WEIGHT5.Reg)&^(0xff000000)|value<<24) +} +func (o *ISP_Type) GetHIST_WEIGHT5_HIST_WEIGHT_40() uint32 { + return (volatile.LoadUint32(&o.HIST_WEIGHT5.Reg) & 0xff000000) >> 24 +} + +// ISP.HIST_WEIGHT6: histogram sub-window weight register 6 +func (o *ISP_Type) SetHIST_WEIGHT6_HIST_WEIGHT_44(value uint32) { + volatile.StoreUint32(&o.HIST_WEIGHT6.Reg, volatile.LoadUint32(&o.HIST_WEIGHT6.Reg)&^(0xff)|value) +} +func (o *ISP_Type) GetHIST_WEIGHT6_HIST_WEIGHT_44() uint32 { + return volatile.LoadUint32(&o.HIST_WEIGHT6.Reg) & 0xff +} + +// ISP.HIST_BIN0: result of histogram bin 0 +func (o *ISP_Type) SetHIST_BIN0_HIST_BIN_0(value uint32) { + volatile.StoreUint32(&o.HIST_BIN0.Reg, volatile.LoadUint32(&o.HIST_BIN0.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN0_HIST_BIN_0() uint32 { + return volatile.LoadUint32(&o.HIST_BIN0.Reg) & 0x1ffff +} + +// ISP.HIST_BIN1: result of histogram bin 1 +func (o *ISP_Type) SetHIST_BIN1_HIST_BIN_1(value uint32) { + volatile.StoreUint32(&o.HIST_BIN1.Reg, volatile.LoadUint32(&o.HIST_BIN1.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN1_HIST_BIN_1() uint32 { + return volatile.LoadUint32(&o.HIST_BIN1.Reg) & 0x1ffff +} + +// ISP.HIST_BIN2: result of histogram bin 2 +func (o *ISP_Type) SetHIST_BIN2_HIST_BIN_2(value uint32) { + volatile.StoreUint32(&o.HIST_BIN2.Reg, volatile.LoadUint32(&o.HIST_BIN2.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN2_HIST_BIN_2() uint32 { + return volatile.LoadUint32(&o.HIST_BIN2.Reg) & 0x1ffff +} + +// ISP.HIST_BIN3: result of histogram bin 3 +func (o *ISP_Type) SetHIST_BIN3_HIST_BIN_3(value uint32) { + volatile.StoreUint32(&o.HIST_BIN3.Reg, volatile.LoadUint32(&o.HIST_BIN3.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN3_HIST_BIN_3() uint32 { + return volatile.LoadUint32(&o.HIST_BIN3.Reg) & 0x1ffff +} + +// ISP.HIST_BIN4: result of histogram bin 4 +func (o *ISP_Type) SetHIST_BIN4_HIST_BIN_4(value uint32) { + volatile.StoreUint32(&o.HIST_BIN4.Reg, volatile.LoadUint32(&o.HIST_BIN4.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN4_HIST_BIN_4() uint32 { + return volatile.LoadUint32(&o.HIST_BIN4.Reg) & 0x1ffff +} + +// ISP.HIST_BIN5: result of histogram bin 5 +func (o *ISP_Type) SetHIST_BIN5_HIST_BIN_5(value uint32) { + volatile.StoreUint32(&o.HIST_BIN5.Reg, volatile.LoadUint32(&o.HIST_BIN5.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN5_HIST_BIN_5() uint32 { + return volatile.LoadUint32(&o.HIST_BIN5.Reg) & 0x1ffff +} + +// ISP.HIST_BIN6: result of histogram bin 6 +func (o *ISP_Type) SetHIST_BIN6_HIST_BIN_6(value uint32) { + volatile.StoreUint32(&o.HIST_BIN6.Reg, volatile.LoadUint32(&o.HIST_BIN6.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN6_HIST_BIN_6() uint32 { + return volatile.LoadUint32(&o.HIST_BIN6.Reg) & 0x1ffff +} + +// ISP.HIST_BIN7: result of histogram bin 7 +func (o *ISP_Type) SetHIST_BIN7_HIST_BIN_7(value uint32) { + volatile.StoreUint32(&o.HIST_BIN7.Reg, volatile.LoadUint32(&o.HIST_BIN7.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN7_HIST_BIN_7() uint32 { + return volatile.LoadUint32(&o.HIST_BIN7.Reg) & 0x1ffff +} + +// ISP.HIST_BIN8: result of histogram bin 8 +func (o *ISP_Type) SetHIST_BIN8_HIST_BIN_8(value uint32) { + volatile.StoreUint32(&o.HIST_BIN8.Reg, volatile.LoadUint32(&o.HIST_BIN8.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN8_HIST_BIN_8() uint32 { + return volatile.LoadUint32(&o.HIST_BIN8.Reg) & 0x1ffff +} + +// ISP.HIST_BIN9: result of histogram bin 9 +func (o *ISP_Type) SetHIST_BIN9_HIST_BIN_9(value uint32) { + volatile.StoreUint32(&o.HIST_BIN9.Reg, volatile.LoadUint32(&o.HIST_BIN9.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN9_HIST_BIN_9() uint32 { + return volatile.LoadUint32(&o.HIST_BIN9.Reg) & 0x1ffff +} + +// ISP.HIST_BIN10: result of histogram bin 10 +func (o *ISP_Type) SetHIST_BIN10_HIST_BIN_10(value uint32) { + volatile.StoreUint32(&o.HIST_BIN10.Reg, volatile.LoadUint32(&o.HIST_BIN10.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN10_HIST_BIN_10() uint32 { + return volatile.LoadUint32(&o.HIST_BIN10.Reg) & 0x1ffff +} + +// ISP.HIST_BIN11: result of histogram bin 11 +func (o *ISP_Type) SetHIST_BIN11_HIST_BIN_11(value uint32) { + volatile.StoreUint32(&o.HIST_BIN11.Reg, volatile.LoadUint32(&o.HIST_BIN11.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN11_HIST_BIN_11() uint32 { + return volatile.LoadUint32(&o.HIST_BIN11.Reg) & 0x1ffff +} + +// ISP.HIST_BIN12: result of histogram bin 12 +func (o *ISP_Type) SetHIST_BIN12_HIST_BIN_12(value uint32) { + volatile.StoreUint32(&o.HIST_BIN12.Reg, volatile.LoadUint32(&o.HIST_BIN12.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN12_HIST_BIN_12() uint32 { + return volatile.LoadUint32(&o.HIST_BIN12.Reg) & 0x1ffff +} + +// ISP.HIST_BIN13: result of histogram bin 13 +func (o *ISP_Type) SetHIST_BIN13_HIST_BIN_13(value uint32) { + volatile.StoreUint32(&o.HIST_BIN13.Reg, volatile.LoadUint32(&o.HIST_BIN13.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN13_HIST_BIN_13() uint32 { + return volatile.LoadUint32(&o.HIST_BIN13.Reg) & 0x1ffff +} + +// ISP.HIST_BIN14: result of histogram bin 14 +func (o *ISP_Type) SetHIST_BIN14_HIST_BIN_14(value uint32) { + volatile.StoreUint32(&o.HIST_BIN14.Reg, volatile.LoadUint32(&o.HIST_BIN14.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN14_HIST_BIN_14() uint32 { + return volatile.LoadUint32(&o.HIST_BIN14.Reg) & 0x1ffff +} + +// ISP.HIST_BIN15: result of histogram bin 15 +func (o *ISP_Type) SetHIST_BIN15_HIST_BIN_15(value uint32) { + volatile.StoreUint32(&o.HIST_BIN15.Reg, volatile.LoadUint32(&o.HIST_BIN15.Reg)&^(0x1ffff)|value) +} +func (o *ISP_Type) GetHIST_BIN15_HIST_BIN_15() uint32 { + return volatile.LoadUint32(&o.HIST_BIN15.Reg) & 0x1ffff +} + +// ISP.MEM_AUX_CTRL_0: mem aux control register 0 +func (o *ISP_Type) SetMEM_AUX_CTRL_0_HEADER_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL_0.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_0.Reg)&^(0x3fff)|value) +} +func (o *ISP_Type) GetMEM_AUX_CTRL_0_HEADER_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.MEM_AUX_CTRL_0.Reg) & 0x3fff +} +func (o *ISP_Type) SetMEM_AUX_CTRL_0_DPC_LUT_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL_0.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_0.Reg)&^(0x3fff0000)|value<<16) +} +func (o *ISP_Type) GetMEM_AUX_CTRL_0_DPC_LUT_MEM_AUX_CTRL() uint32 { + return (volatile.LoadUint32(&o.MEM_AUX_CTRL_0.Reg) & 0x3fff0000) >> 16 +} + +// ISP.MEM_AUX_CTRL_1: mem aux control register 1 +func (o *ISP_Type) SetMEM_AUX_CTRL_1_LSC_LUT_R_GR_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL_1.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_1.Reg)&^(0x3fff)|value) +} +func (o *ISP_Type) GetMEM_AUX_CTRL_1_LSC_LUT_R_GR_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.MEM_AUX_CTRL_1.Reg) & 0x3fff +} +func (o *ISP_Type) SetMEM_AUX_CTRL_1_LSC_LUT_GB_B_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL_1.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_1.Reg)&^(0x3fff0000)|value<<16) +} +func (o *ISP_Type) GetMEM_AUX_CTRL_1_LSC_LUT_GB_B_MEM_AUX_CTRL() uint32 { + return (volatile.LoadUint32(&o.MEM_AUX_CTRL_1.Reg) & 0x3fff0000) >> 16 +} + +// ISP.MEM_AUX_CTRL_2: mem aux control register 2 +func (o *ISP_Type) SetMEM_AUX_CTRL_2_BF_MATRIX_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL_2.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_2.Reg)&^(0x3fff)|value) +} +func (o *ISP_Type) GetMEM_AUX_CTRL_2_BF_MATRIX_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.MEM_AUX_CTRL_2.Reg) & 0x3fff +} +func (o *ISP_Type) SetMEM_AUX_CTRL_2_DPC_MATRIX_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL_2.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_2.Reg)&^(0x3fff0000)|value<<16) +} +func (o *ISP_Type) GetMEM_AUX_CTRL_2_DPC_MATRIX_MEM_AUX_CTRL() uint32 { + return (volatile.LoadUint32(&o.MEM_AUX_CTRL_2.Reg) & 0x3fff0000) >> 16 +} + +// ISP.MEM_AUX_CTRL_3: mem aux control register 3 +func (o *ISP_Type) SetMEM_AUX_CTRL_3_SHARP_MATRIX_Y_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL_3.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_3.Reg)&^(0x3fff)|value) +} +func (o *ISP_Type) GetMEM_AUX_CTRL_3_SHARP_MATRIX_Y_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.MEM_AUX_CTRL_3.Reg) & 0x3fff +} +func (o *ISP_Type) SetMEM_AUX_CTRL_3_DEMOSAIC_MATRIX_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL_3.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_3.Reg)&^(0x3fff0000)|value<<16) +} +func (o *ISP_Type) GetMEM_AUX_CTRL_3_DEMOSAIC_MATRIX_MEM_AUX_CTRL() uint32 { + return (volatile.LoadUint32(&o.MEM_AUX_CTRL_3.Reg) & 0x3fff0000) >> 16 +} + +// ISP.MEM_AUX_CTRL_4: mem aux control register 4 +func (o *ISP_Type) SetMEM_AUX_CTRL_4_SHARP_MATRIX_UV_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.MEM_AUX_CTRL_4.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_4.Reg)&^(0x3fff)|value) +} +func (o *ISP_Type) GetMEM_AUX_CTRL_4_SHARP_MATRIX_UV_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.MEM_AUX_CTRL_4.Reg) & 0x3fff +} + +// ISP.YUV_FORMAT: yuv format control register +func (o *ISP_Type) SetYUV_FORMAT_YUV_MODE(value uint32) { + volatile.StoreUint32(&o.YUV_FORMAT.Reg, volatile.LoadUint32(&o.YUV_FORMAT.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetYUV_FORMAT_YUV_MODE() uint32 { + return volatile.LoadUint32(&o.YUV_FORMAT.Reg) & 0x1 +} +func (o *ISP_Type) SetYUV_FORMAT_YUV_RANGE(value uint32) { + volatile.StoreUint32(&o.YUV_FORMAT.Reg, volatile.LoadUint32(&o.YUV_FORMAT.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetYUV_FORMAT_YUV_RANGE() uint32 { + return (volatile.LoadUint32(&o.YUV_FORMAT.Reg) & 0x2) >> 1 +} + +// ISP.RDN_ECO_CS: rdn eco cs register +func (o *ISP_Type) SetRDN_ECO_CS_RDN_ECO_EN(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x1)|value) +} +func (o *ISP_Type) GetRDN_ECO_CS_RDN_ECO_EN() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x1 +} +func (o *ISP_Type) SetRDN_ECO_CS_RDN_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *ISP_Type) GetRDN_ECO_CS_RDN_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x2) >> 1 +} + +// ISP.RDN_ECO_LOW: rdn eco all low register +func (o *ISP_Type) SetRDN_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_LOW.Reg, value) +} +func (o *ISP_Type) GetRDN_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_LOW.Reg) +} + +// ISP.RDN_ECO_HIGH: rdn eco all high register +func (o *ISP_Type) SetRDN_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RDN_ECO_HIGH.Reg, value) +} +func (o *ISP_Type) GetRDN_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RDN_ECO_HIGH.Reg) +} + +// JPEG Codec +type JPEG_Type struct { + CONFIG volatile.Register32 // 0x0 + DQT_INFO volatile.Register32 // 0x4 + PIC_SIZE volatile.Register32 // 0x8 + _ [4]byte + T0QNR volatile.Register32 // 0x10 + T1QNR volatile.Register32 // 0x14 + T2QNR volatile.Register32 // 0x18 + T3QNR volatile.Register32 // 0x1C + DECODE_CONF volatile.Register32 // 0x20 + C0 volatile.Register32 // 0x24 + C1 volatile.Register32 // 0x28 + C2 volatile.Register32 // 0x2C + C3 volatile.Register32 // 0x30 + DHT_INFO volatile.Register32 // 0x34 + INT_RAW volatile.Register32 // 0x38 + INT_ENA volatile.Register32 // 0x3C + INT_ST volatile.Register32 // 0x40 + INT_CLR volatile.Register32 // 0x44 + STATUS0 volatile.Register32 // 0x48 + STATUS2 volatile.Register32 // 0x4C + STATUS3 volatile.Register32 // 0x50 + STATUS4 volatile.Register32 // 0x54 + DHT_TOTLEN_DC0 volatile.Register32 // 0x58 + DHT_VAl_DC0 volatile.Register32 // 0x5C + DHT_TOTLEN_AC0 volatile.Register32 // 0x60 + DHT_VAl_AC0 volatile.Register32 // 0x64 + DHT_TOTLEN_DC1 volatile.Register32 // 0x68 + DHT_VAl_DC1 volatile.Register32 // 0x6C + DHT_TOTLEN_AC1 volatile.Register32 // 0x70 + DHT_VAl_AC1 volatile.Register32 // 0x74 + DHT_CODEMIN_DC0 volatile.Register32 // 0x78 + DHT_CODEMIN_AC0 volatile.Register32 // 0x7C + DHT_CODEMIN_DC1 volatile.Register32 // 0x80 + DHT_CODEMIN_AC1 volatile.Register32 // 0x84 + DECODER_STATUS0 volatile.Register32 // 0x88 + DECODER_STATUS1 volatile.Register32 // 0x8C + DECODER_STATUS2 volatile.Register32 // 0x90 + DECODER_STATUS3 volatile.Register32 // 0x94 + DECODER_STATUS4 volatile.Register32 // 0x98 + DECODER_STATUS5 volatile.Register32 // 0x9C + STATUS5 volatile.Register32 // 0xA0 + ECO_LOW volatile.Register32 // 0xA4 + ECO_HIGH volatile.Register32 // 0xA8 + _ [76]byte + SYS volatile.Register32 // 0xF8 + VERSION volatile.Register32 // 0xFC +} + +// JPEG.CONFIG: Control and configuration registers +func (o *JPEG_Type) SetCONFIG_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1)|value) +} +func (o *JPEG_Type) GetCONFIG_FSM_RST() uint32 { + return volatile.LoadUint32(&o.CONFIG.Reg) & 0x1 +} +func (o *JPEG_Type) SetCONFIG_JPEG_START(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *JPEG_Type) GetCONFIG_JPEG_START() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x2) >> 1 +} +func (o *JPEG_Type) SetCONFIG_QNR_PRESITION(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x4)|value<<2) +} +func (o *JPEG_Type) GetCONFIG_QNR_PRESITION() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x4) >> 2 +} +func (o *JPEG_Type) SetCONFIG_FF_CHECK_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8)|value<<3) +} +func (o *JPEG_Type) GetCONFIG_FF_CHECK_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8) >> 3 +} +func (o *JPEG_Type) SetCONFIG_SAMPLE_SEL(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x30)|value<<4) +} +func (o *JPEG_Type) GetCONFIG_SAMPLE_SEL() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x30) >> 4 +} +func (o *JPEG_Type) SetCONFIG_DMA_LINKLIST_MODE(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x40)|value<<6) +} +func (o *JPEG_Type) GetCONFIG_DMA_LINKLIST_MODE() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x40) >> 6 +} +func (o *JPEG_Type) SetCONFIG_DEBUG_DIRECT_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x80)|value<<7) +} +func (o *JPEG_Type) GetCONFIG_DEBUG_DIRECT_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x80) >> 7 +} +func (o *JPEG_Type) SetCONFIG_GRAY_SEL(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x100)|value<<8) +} +func (o *JPEG_Type) GetCONFIG_GRAY_SEL() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x100) >> 8 +} +func (o *JPEG_Type) SetCONFIG_LQNR_TBL_SEL(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x600)|value<<9) +} +func (o *JPEG_Type) GetCONFIG_LQNR_TBL_SEL() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x600) >> 9 +} +func (o *JPEG_Type) SetCONFIG_CQNR_TBL_SEL(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1800)|value<<11) +} +func (o *JPEG_Type) GetCONFIG_CQNR_TBL_SEL() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x1800) >> 11 +} +func (o *JPEG_Type) SetCONFIG_COLOR_SPACE(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x6000)|value<<13) +} +func (o *JPEG_Type) GetCONFIG_COLOR_SPACE() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x6000) >> 13 +} +func (o *JPEG_Type) SetCONFIG_DHT_FIFO_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8000)|value<<15) +} +func (o *JPEG_Type) GetCONFIG_DHT_FIFO_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8000) >> 15 +} +func (o *JPEG_Type) SetCONFIG_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x10000)|value<<16) +} +func (o *JPEG_Type) GetCONFIG_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x10000) >> 16 +} +func (o *JPEG_Type) SetCONFIG_JFIF_VER(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x7e0000)|value<<17) +} +func (o *JPEG_Type) GetCONFIG_JFIF_VER() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x7e0000) >> 17 +} +func (o *JPEG_Type) SetCONFIG_DECODE_TIMEOUT_TASK_SEL(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x800000)|value<<23) +} +func (o *JPEG_Type) GetCONFIG_DECODE_TIMEOUT_TASK_SEL() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x800000) >> 23 +} +func (o *JPEG_Type) SetCONFIG_SOFT_RST(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1000000)|value<<24) +} +func (o *JPEG_Type) GetCONFIG_SOFT_RST() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x1000000) >> 24 +} +func (o *JPEG_Type) SetCONFIG_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x2000000)|value<<25) +} +func (o *JPEG_Type) GetCONFIG_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x2000000) >> 25 +} +func (o *JPEG_Type) SetCONFIG_PIXEL_REV(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x4000000)|value<<26) +} +func (o *JPEG_Type) GetCONFIG_PIXEL_REV() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x4000000) >> 26 +} +func (o *JPEG_Type) SetCONFIG_TAILER_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8000000)|value<<27) +} +func (o *JPEG_Type) GetCONFIG_TAILER_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8000000) >> 27 +} +func (o *JPEG_Type) SetCONFIG_PAUSE_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x10000000)|value<<28) +} +func (o *JPEG_Type) GetCONFIG_PAUSE_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x10000000) >> 28 +} +func (o *JPEG_Type) SetCONFIG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *JPEG_Type) GetCONFIG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *JPEG_Type) SetCONFIG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *JPEG_Type) GetCONFIG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *JPEG_Type) SetCONFIG_MODE(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *JPEG_Type) GetCONFIG_MODE() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x80000000) >> 31 +} + +// JPEG.DQT_INFO: Control and configuration registers +func (o *JPEG_Type) SetDQT_INFO_T0_DQT_INFO(value uint32) { + volatile.StoreUint32(&o.DQT_INFO.Reg, volatile.LoadUint32(&o.DQT_INFO.Reg)&^(0xff)|value) +} +func (o *JPEG_Type) GetDQT_INFO_T0_DQT_INFO() uint32 { + return volatile.LoadUint32(&o.DQT_INFO.Reg) & 0xff +} +func (o *JPEG_Type) SetDQT_INFO_T1_DQT_INFO(value uint32) { + volatile.StoreUint32(&o.DQT_INFO.Reg, volatile.LoadUint32(&o.DQT_INFO.Reg)&^(0xff00)|value<<8) +} +func (o *JPEG_Type) GetDQT_INFO_T1_DQT_INFO() uint32 { + return (volatile.LoadUint32(&o.DQT_INFO.Reg) & 0xff00) >> 8 +} +func (o *JPEG_Type) SetDQT_INFO_T2_DQT_INFO(value uint32) { + volatile.StoreUint32(&o.DQT_INFO.Reg, volatile.LoadUint32(&o.DQT_INFO.Reg)&^(0xff0000)|value<<16) +} +func (o *JPEG_Type) GetDQT_INFO_T2_DQT_INFO() uint32 { + return (volatile.LoadUint32(&o.DQT_INFO.Reg) & 0xff0000) >> 16 +} +func (o *JPEG_Type) SetDQT_INFO_T3_DQT_INFO(value uint32) { + volatile.StoreUint32(&o.DQT_INFO.Reg, volatile.LoadUint32(&o.DQT_INFO.Reg)&^(0xff000000)|value<<24) +} +func (o *JPEG_Type) GetDQT_INFO_T3_DQT_INFO() uint32 { + return (volatile.LoadUint32(&o.DQT_INFO.Reg) & 0xff000000) >> 24 +} + +// JPEG.PIC_SIZE: Control and configuration registers +func (o *JPEG_Type) SetPIC_SIZE_VA(value uint32) { + volatile.StoreUint32(&o.PIC_SIZE.Reg, volatile.LoadUint32(&o.PIC_SIZE.Reg)&^(0xffff)|value) +} +func (o *JPEG_Type) GetPIC_SIZE_VA() uint32 { + return volatile.LoadUint32(&o.PIC_SIZE.Reg) & 0xffff +} +func (o *JPEG_Type) SetPIC_SIZE_HA(value uint32) { + volatile.StoreUint32(&o.PIC_SIZE.Reg, volatile.LoadUint32(&o.PIC_SIZE.Reg)&^(0xffff0000)|value<<16) +} +func (o *JPEG_Type) GetPIC_SIZE_HA() uint32 { + return (volatile.LoadUint32(&o.PIC_SIZE.Reg) & 0xffff0000) >> 16 +} + +// JPEG.T0QNR: Control and configuration registers +func (o *JPEG_Type) SetT0QNR(value uint32) { + volatile.StoreUint32(&o.T0QNR.Reg, value) +} +func (o *JPEG_Type) GetT0QNR() uint32 { + return volatile.LoadUint32(&o.T0QNR.Reg) +} + +// JPEG.T1QNR: Control and configuration registers +func (o *JPEG_Type) SetT1QNR(value uint32) { + volatile.StoreUint32(&o.T1QNR.Reg, value) +} +func (o *JPEG_Type) GetT1QNR() uint32 { + return volatile.LoadUint32(&o.T1QNR.Reg) +} + +// JPEG.T2QNR: Control and configuration registers +func (o *JPEG_Type) SetT2QNR(value uint32) { + volatile.StoreUint32(&o.T2QNR.Reg, value) +} +func (o *JPEG_Type) GetT2QNR() uint32 { + return volatile.LoadUint32(&o.T2QNR.Reg) +} + +// JPEG.T3QNR: Control and configuration registers +func (o *JPEG_Type) SetT3QNR(value uint32) { + volatile.StoreUint32(&o.T3QNR.Reg, value) +} +func (o *JPEG_Type) GetT3QNR() uint32 { + return volatile.LoadUint32(&o.T3QNR.Reg) +} + +// JPEG.DECODE_CONF: Control and configuration registers +func (o *JPEG_Type) SetDECODE_CONF_RESTART_INTERVAL(value uint32) { + volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0xffff)|value) +} +func (o *JPEG_Type) GetDECODE_CONF_RESTART_INTERVAL() uint32 { + return volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0xffff +} +func (o *JPEG_Type) SetDECODE_CONF_COMPONENT_NUM(value uint32) { + volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0xff0000)|value<<16) +} +func (o *JPEG_Type) GetDECODE_CONF_COMPONENT_NUM() uint32 { + return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0xff0000) >> 16 +} +func (o *JPEG_Type) SetDECODE_CONF_SW_DHT_EN(value uint32) { + volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *JPEG_Type) GetDECODE_CONF_SW_DHT_EN() uint32 { + return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x1000000) >> 24 +} +func (o *JPEG_Type) SetDECODE_CONF_SOS_CHECK_BYTE_NUM(value uint32) { + volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x6000000)|value<<25) +} +func (o *JPEG_Type) GetDECODE_CONF_SOS_CHECK_BYTE_NUM() uint32 { + return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x6000000) >> 25 +} +func (o *JPEG_Type) SetDECODE_CONF_RST_CHECK_BYTE_NUM(value uint32) { + volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *JPEG_Type) GetDECODE_CONF_RST_CHECK_BYTE_NUM() uint32 { + return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x18000000) >> 27 +} +func (o *JPEG_Type) SetDECODE_CONF_MULTI_SCAN_ERR_CHECK(value uint32) { + volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *JPEG_Type) GetDECODE_CONF_MULTI_SCAN_ERR_CHECK() uint32 { + return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x20000000) >> 29 +} +func (o *JPEG_Type) SetDECODE_CONF_DEZIGZAG_READY_CTL(value uint32) { + volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *JPEG_Type) GetDECODE_CONF_DEZIGZAG_READY_CTL() uint32 { + return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x40000000) >> 30 +} + +// JPEG.C0: Control and configuration registers +func (o *JPEG_Type) SetC0_DQT_TBL_SEL(value uint32) { + volatile.StoreUint32(&o.C0.Reg, volatile.LoadUint32(&o.C0.Reg)&^(0xff)|value) +} +func (o *JPEG_Type) GetC0_DQT_TBL_SEL() uint32 { + return volatile.LoadUint32(&o.C0.Reg) & 0xff +} +func (o *JPEG_Type) SetC0_Y_FACTOR(value uint32) { + volatile.StoreUint32(&o.C0.Reg, volatile.LoadUint32(&o.C0.Reg)&^(0xf00)|value<<8) +} +func (o *JPEG_Type) GetC0_Y_FACTOR() uint32 { + return (volatile.LoadUint32(&o.C0.Reg) & 0xf00) >> 8 +} +func (o *JPEG_Type) SetC0_X_FACTOR(value uint32) { + volatile.StoreUint32(&o.C0.Reg, volatile.LoadUint32(&o.C0.Reg)&^(0xf000)|value<<12) +} +func (o *JPEG_Type) GetC0_X_FACTOR() uint32 { + return (volatile.LoadUint32(&o.C0.Reg) & 0xf000) >> 12 +} +func (o *JPEG_Type) SetC0_ID(value uint32) { + volatile.StoreUint32(&o.C0.Reg, volatile.LoadUint32(&o.C0.Reg)&^(0xff0000)|value<<16) +} +func (o *JPEG_Type) GetC0_ID() uint32 { + return (volatile.LoadUint32(&o.C0.Reg) & 0xff0000) >> 16 +} + +// JPEG.C1: Control and configuration registers +func (o *JPEG_Type) SetC1_DQT_TBL_SEL(value uint32) { + volatile.StoreUint32(&o.C1.Reg, volatile.LoadUint32(&o.C1.Reg)&^(0xff)|value) +} +func (o *JPEG_Type) GetC1_DQT_TBL_SEL() uint32 { + return volatile.LoadUint32(&o.C1.Reg) & 0xff +} +func (o *JPEG_Type) SetC1_Y_FACTOR(value uint32) { + volatile.StoreUint32(&o.C1.Reg, volatile.LoadUint32(&o.C1.Reg)&^(0xf00)|value<<8) +} +func (o *JPEG_Type) GetC1_Y_FACTOR() uint32 { + return (volatile.LoadUint32(&o.C1.Reg) & 0xf00) >> 8 +} +func (o *JPEG_Type) SetC1_X_FACTOR(value uint32) { + volatile.StoreUint32(&o.C1.Reg, volatile.LoadUint32(&o.C1.Reg)&^(0xf000)|value<<12) +} +func (o *JPEG_Type) GetC1_X_FACTOR() uint32 { + return (volatile.LoadUint32(&o.C1.Reg) & 0xf000) >> 12 +} +func (o *JPEG_Type) SetC1_ID(value uint32) { + volatile.StoreUint32(&o.C1.Reg, volatile.LoadUint32(&o.C1.Reg)&^(0xff0000)|value<<16) +} +func (o *JPEG_Type) GetC1_ID() uint32 { + return (volatile.LoadUint32(&o.C1.Reg) & 0xff0000) >> 16 +} + +// JPEG.C2: Control and configuration registers +func (o *JPEG_Type) SetC2_DQT_TBL_SEL(value uint32) { + volatile.StoreUint32(&o.C2.Reg, volatile.LoadUint32(&o.C2.Reg)&^(0xff)|value) +} +func (o *JPEG_Type) GetC2_DQT_TBL_SEL() uint32 { + return volatile.LoadUint32(&o.C2.Reg) & 0xff +} +func (o *JPEG_Type) SetC2_Y_FACTOR(value uint32) { + volatile.StoreUint32(&o.C2.Reg, volatile.LoadUint32(&o.C2.Reg)&^(0xf00)|value<<8) +} +func (o *JPEG_Type) GetC2_Y_FACTOR() uint32 { + return (volatile.LoadUint32(&o.C2.Reg) & 0xf00) >> 8 +} +func (o *JPEG_Type) SetC2_X_FACTOR(value uint32) { + volatile.StoreUint32(&o.C2.Reg, volatile.LoadUint32(&o.C2.Reg)&^(0xf000)|value<<12) +} +func (o *JPEG_Type) GetC2_X_FACTOR() uint32 { + return (volatile.LoadUint32(&o.C2.Reg) & 0xf000) >> 12 +} +func (o *JPEG_Type) SetC2_ID(value uint32) { + volatile.StoreUint32(&o.C2.Reg, volatile.LoadUint32(&o.C2.Reg)&^(0xff0000)|value<<16) +} +func (o *JPEG_Type) GetC2_ID() uint32 { + return (volatile.LoadUint32(&o.C2.Reg) & 0xff0000) >> 16 +} + +// JPEG.C3: Control and configuration registers +func (o *JPEG_Type) SetC3_DQT_TBL_SEL(value uint32) { + volatile.StoreUint32(&o.C3.Reg, volatile.LoadUint32(&o.C3.Reg)&^(0xff)|value) +} +func (o *JPEG_Type) GetC3_DQT_TBL_SEL() uint32 { + return volatile.LoadUint32(&o.C3.Reg) & 0xff +} +func (o *JPEG_Type) SetC3_Y_FACTOR(value uint32) { + volatile.StoreUint32(&o.C3.Reg, volatile.LoadUint32(&o.C3.Reg)&^(0xf00)|value<<8) +} +func (o *JPEG_Type) GetC3_Y_FACTOR() uint32 { + return (volatile.LoadUint32(&o.C3.Reg) & 0xf00) >> 8 +} +func (o *JPEG_Type) SetC3_X_FACTOR(value uint32) { + volatile.StoreUint32(&o.C3.Reg, volatile.LoadUint32(&o.C3.Reg)&^(0xf000)|value<<12) +} +func (o *JPEG_Type) GetC3_X_FACTOR() uint32 { + return (volatile.LoadUint32(&o.C3.Reg) & 0xf000) >> 12 +} +func (o *JPEG_Type) SetC3_ID(value uint32) { + volatile.StoreUint32(&o.C3.Reg, volatile.LoadUint32(&o.C3.Reg)&^(0xff0000)|value<<16) +} +func (o *JPEG_Type) GetC3_ID() uint32 { + return (volatile.LoadUint32(&o.C3.Reg) & 0xff0000) >> 16 +} + +// JPEG.DHT_INFO: Control and configuration registers +func (o *JPEG_Type) SetDHT_INFO_DC0_DHT_ID(value uint32) { + volatile.StoreUint32(&o.DHT_INFO.Reg, volatile.LoadUint32(&o.DHT_INFO.Reg)&^(0xf)|value) +} +func (o *JPEG_Type) GetDHT_INFO_DC0_DHT_ID() uint32 { + return volatile.LoadUint32(&o.DHT_INFO.Reg) & 0xf +} +func (o *JPEG_Type) SetDHT_INFO_DC1_DHT_ID(value uint32) { + volatile.StoreUint32(&o.DHT_INFO.Reg, volatile.LoadUint32(&o.DHT_INFO.Reg)&^(0xf0)|value<<4) +} +func (o *JPEG_Type) GetDHT_INFO_DC1_DHT_ID() uint32 { + return (volatile.LoadUint32(&o.DHT_INFO.Reg) & 0xf0) >> 4 +} +func (o *JPEG_Type) SetDHT_INFO_AC0_DHT_ID(value uint32) { + volatile.StoreUint32(&o.DHT_INFO.Reg, volatile.LoadUint32(&o.DHT_INFO.Reg)&^(0xf00)|value<<8) +} +func (o *JPEG_Type) GetDHT_INFO_AC0_DHT_ID() uint32 { + return (volatile.LoadUint32(&o.DHT_INFO.Reg) & 0xf00) >> 8 +} +func (o *JPEG_Type) SetDHT_INFO_AC1_DHT_ID(value uint32) { + volatile.StoreUint32(&o.DHT_INFO.Reg, volatile.LoadUint32(&o.DHT_INFO.Reg)&^(0xf000)|value<<12) +} +func (o *JPEG_Type) GetDHT_INFO_AC1_DHT_ID() uint32 { + return (volatile.LoadUint32(&o.DHT_INFO.Reg) & 0xf000) >> 12 +} + +// JPEG.INT_RAW: Interrupt raw registers +func (o *JPEG_Type) SetINT_RAW_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *JPEG_Type) GetINT_RAW_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *JPEG_Type) SetINT_RAW_RLE_PARALLEL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *JPEG_Type) GetINT_RAW_RLE_PARALLEL_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *JPEG_Type) SetINT_RAW_CID_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *JPEG_Type) GetINT_RAW_CID_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *JPEG_Type) SetINT_RAW_C_DHT_DC_ID_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *JPEG_Type) GetINT_RAW_C_DHT_DC_ID_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *JPEG_Type) SetINT_RAW_C_DHT_AC_ID_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *JPEG_Type) GetINT_RAW_C_DHT_AC_ID_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *JPEG_Type) SetINT_RAW_C_DQT_ID_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *JPEG_Type) GetINT_RAW_C_DQT_ID_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *JPEG_Type) SetINT_RAW_RST_UXP_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *JPEG_Type) GetINT_RAW_RST_UXP_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *JPEG_Type) SetINT_RAW_RST_CHECK_NONE_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *JPEG_Type) GetINT_RAW_RST_CHECK_NONE_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *JPEG_Type) SetINT_RAW_RST_CHECK_POS_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *JPEG_Type) GetINT_RAW_RST_CHECK_POS_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *JPEG_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *JPEG_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *JPEG_Type) SetINT_RAW_SR_COLOR_MODE_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *JPEG_Type) GetINT_RAW_SR_COLOR_MODE_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *JPEG_Type) SetINT_RAW_DCT_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *JPEG_Type) GetINT_RAW_DCT_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *JPEG_Type) SetINT_RAW_BS_LAST_BLOCK_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *JPEG_Type) GetINT_RAW_BS_LAST_BLOCK_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *JPEG_Type) SetINT_RAW_SCAN_CHECK_NONE_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *JPEG_Type) GetINT_RAW_SCAN_CHECK_NONE_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *JPEG_Type) SetINT_RAW_SCAN_CHECK_POS_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *JPEG_Type) GetINT_RAW_SCAN_CHECK_POS_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *JPEG_Type) SetINT_RAW_UXP_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *JPEG_Type) GetINT_RAW_UXP_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *JPEG_Type) SetINT_RAW_EN_FRAME_EOF_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *JPEG_Type) GetINT_RAW_EN_FRAME_EOF_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *JPEG_Type) SetINT_RAW_EN_FRAME_EOF_LACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *JPEG_Type) GetINT_RAW_EN_FRAME_EOF_LACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *JPEG_Type) SetINT_RAW_DE_FRAME_EOF_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *JPEG_Type) GetINT_RAW_DE_FRAME_EOF_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *JPEG_Type) SetINT_RAW_DE_FRAME_EOF_LACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *JPEG_Type) GetINT_RAW_DE_FRAME_EOF_LACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *JPEG_Type) SetINT_RAW_SOS_UNMATCH_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *JPEG_Type) GetINT_RAW_SOS_UNMATCH_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *JPEG_Type) SetINT_RAW_MARKER_ERR_FST_SCAN_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *JPEG_Type) GetINT_RAW_MARKER_ERR_FST_SCAN_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *JPEG_Type) SetINT_RAW_MARKER_ERR_OTHER_SCAN_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *JPEG_Type) GetINT_RAW_MARKER_ERR_OTHER_SCAN_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *JPEG_Type) SetINT_RAW_UNDET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *JPEG_Type) GetINT_RAW_UNDET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *JPEG_Type) SetINT_RAW_DECODE_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *JPEG_Type) GetINT_RAW_DECODE_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} + +// JPEG.INT_ENA: Interrupt enable registers +func (o *JPEG_Type) SetINT_ENA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *JPEG_Type) GetINT_ENA_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *JPEG_Type) SetINT_ENA_RLE_PARALLEL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *JPEG_Type) GetINT_ENA_RLE_PARALLEL_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *JPEG_Type) SetINT_ENA_CID_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *JPEG_Type) GetINT_ENA_CID_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *JPEG_Type) SetINT_ENA_C_DHT_DC_ID_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *JPEG_Type) GetINT_ENA_C_DHT_DC_ID_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *JPEG_Type) SetINT_ENA_C_DHT_AC_ID_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *JPEG_Type) GetINT_ENA_C_DHT_AC_ID_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *JPEG_Type) SetINT_ENA_C_DQT_ID_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *JPEG_Type) GetINT_ENA_C_DQT_ID_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *JPEG_Type) SetINT_ENA_RST_UXP_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *JPEG_Type) GetINT_ENA_RST_UXP_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *JPEG_Type) SetINT_ENA_RST_CHECK_NONE_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *JPEG_Type) GetINT_ENA_RST_CHECK_NONE_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *JPEG_Type) SetINT_ENA_RST_CHECK_POS_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *JPEG_Type) GetINT_ENA_RST_CHECK_POS_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *JPEG_Type) SetINT_ENA_OUT_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *JPEG_Type) GetINT_ENA_OUT_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *JPEG_Type) SetINT_ENA_SR_COLOR_MODE_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *JPEG_Type) GetINT_ENA_SR_COLOR_MODE_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *JPEG_Type) SetINT_ENA_DCT_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *JPEG_Type) GetINT_ENA_DCT_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *JPEG_Type) SetINT_ENA_BS_LAST_BLOCK_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *JPEG_Type) GetINT_ENA_BS_LAST_BLOCK_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *JPEG_Type) SetINT_ENA_SCAN_CHECK_NONE_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *JPEG_Type) GetINT_ENA_SCAN_CHECK_NONE_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *JPEG_Type) SetINT_ENA_SCAN_CHECK_POS_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *JPEG_Type) GetINT_ENA_SCAN_CHECK_POS_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *JPEG_Type) SetINT_ENA_UXP_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *JPEG_Type) GetINT_ENA_UXP_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *JPEG_Type) SetINT_ENA_EN_FRAME_EOF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *JPEG_Type) GetINT_ENA_EN_FRAME_EOF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *JPEG_Type) SetINT_ENA_EN_FRAME_EOF_LACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *JPEG_Type) GetINT_ENA_EN_FRAME_EOF_LACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *JPEG_Type) SetINT_ENA_DE_FRAME_EOF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *JPEG_Type) GetINT_ENA_DE_FRAME_EOF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *JPEG_Type) SetINT_ENA_DE_FRAME_EOF_LACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *JPEG_Type) GetINT_ENA_DE_FRAME_EOF_LACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *JPEG_Type) SetINT_ENA_SOS_UNMATCH_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *JPEG_Type) GetINT_ENA_SOS_UNMATCH_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *JPEG_Type) SetINT_ENA_MARKER_ERR_FST_SCAN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *JPEG_Type) GetINT_ENA_MARKER_ERR_FST_SCAN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *JPEG_Type) SetINT_ENA_MARKER_ERR_OTHER_SCAN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *JPEG_Type) GetINT_ENA_MARKER_ERR_OTHER_SCAN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *JPEG_Type) SetINT_ENA_UNDET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *JPEG_Type) GetINT_ENA_UNDET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *JPEG_Type) SetINT_ENA_DECODE_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *JPEG_Type) GetINT_ENA_DECODE_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} + +// JPEG.INT_ST: Interrupt status registers +func (o *JPEG_Type) SetINT_ST_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *JPEG_Type) GetINT_ST_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *JPEG_Type) SetINT_ST_RLE_PARALLEL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *JPEG_Type) GetINT_ST_RLE_PARALLEL_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *JPEG_Type) SetINT_ST_CID_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *JPEG_Type) GetINT_ST_CID_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *JPEG_Type) SetINT_ST_C_DHT_DC_ID_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *JPEG_Type) GetINT_ST_C_DHT_DC_ID_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *JPEG_Type) SetINT_ST_C_DHT_AC_ID_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *JPEG_Type) GetINT_ST_C_DHT_AC_ID_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *JPEG_Type) SetINT_ST_C_DQT_ID_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *JPEG_Type) GetINT_ST_C_DQT_ID_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *JPEG_Type) SetINT_ST_RST_UXP_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *JPEG_Type) GetINT_ST_RST_UXP_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *JPEG_Type) SetINT_ST_RST_CHECK_NONE_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *JPEG_Type) GetINT_ST_RST_CHECK_NONE_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *JPEG_Type) SetINT_ST_RST_CHECK_POS_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *JPEG_Type) GetINT_ST_RST_CHECK_POS_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *JPEG_Type) SetINT_ST_OUT_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *JPEG_Type) GetINT_ST_OUT_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *JPEG_Type) SetINT_ST_SR_COLOR_MODE_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *JPEG_Type) GetINT_ST_SR_COLOR_MODE_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *JPEG_Type) SetINT_ST_DCT_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *JPEG_Type) GetINT_ST_DCT_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *JPEG_Type) SetINT_ST_BS_LAST_BLOCK_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *JPEG_Type) GetINT_ST_BS_LAST_BLOCK_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *JPEG_Type) SetINT_ST_SCAN_CHECK_NONE_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *JPEG_Type) GetINT_ST_SCAN_CHECK_NONE_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *JPEG_Type) SetINT_ST_SCAN_CHECK_POS_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *JPEG_Type) GetINT_ST_SCAN_CHECK_POS_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *JPEG_Type) SetINT_ST_UXP_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *JPEG_Type) GetINT_ST_UXP_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *JPEG_Type) SetINT_ST_EN_FRAME_EOF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *JPEG_Type) GetINT_ST_EN_FRAME_EOF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *JPEG_Type) SetINT_ST_EN_FRAME_EOF_LACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *JPEG_Type) GetINT_ST_EN_FRAME_EOF_LACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *JPEG_Type) SetINT_ST_DE_FRAME_EOF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *JPEG_Type) GetINT_ST_DE_FRAME_EOF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *JPEG_Type) SetINT_ST_DE_FRAME_EOF_LACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *JPEG_Type) GetINT_ST_DE_FRAME_EOF_LACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} +func (o *JPEG_Type) SetINT_ST_SOS_UNMATCH_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *JPEG_Type) GetINT_ST_SOS_UNMATCH_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *JPEG_Type) SetINT_ST_MARKER_ERR_FST_SCAN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *JPEG_Type) GetINT_ST_MARKER_ERR_FST_SCAN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21 +} +func (o *JPEG_Type) SetINT_ST_MARKER_ERR_OTHER_SCAN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *JPEG_Type) GetINT_ST_MARKER_ERR_OTHER_SCAN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22 +} +func (o *JPEG_Type) SetINT_ST_UNDET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *JPEG_Type) GetINT_ST_UNDET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23 +} +func (o *JPEG_Type) SetINT_ST_DECODE_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *JPEG_Type) GetINT_ST_DECODE_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} + +// JPEG.INT_CLR: Interrupt clear registers +func (o *JPEG_Type) SetINT_CLR_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *JPEG_Type) GetINT_CLR_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *JPEG_Type) SetINT_CLR_RLE_PARALLEL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *JPEG_Type) GetINT_CLR_RLE_PARALLEL_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *JPEG_Type) SetINT_CLR_CID_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *JPEG_Type) GetINT_CLR_CID_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *JPEG_Type) SetINT_CLR_C_DHT_DC_ID_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *JPEG_Type) GetINT_CLR_C_DHT_DC_ID_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *JPEG_Type) SetINT_CLR_C_DHT_AC_ID_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *JPEG_Type) GetINT_CLR_C_DHT_AC_ID_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *JPEG_Type) SetINT_CLR_C_DQT_ID_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *JPEG_Type) GetINT_CLR_C_DQT_ID_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *JPEG_Type) SetINT_CLR_RST_UXP_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *JPEG_Type) GetINT_CLR_RST_UXP_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *JPEG_Type) SetINT_CLR_RST_CHECK_NONE_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *JPEG_Type) GetINT_CLR_RST_CHECK_NONE_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *JPEG_Type) SetINT_CLR_RST_CHECK_POS_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *JPEG_Type) GetINT_CLR_RST_CHECK_POS_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *JPEG_Type) SetINT_CLR_OUT_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *JPEG_Type) GetINT_CLR_OUT_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *JPEG_Type) SetINT_CLR_SR_COLOR_MODE_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *JPEG_Type) GetINT_CLR_SR_COLOR_MODE_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *JPEG_Type) SetINT_CLR_DCT_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *JPEG_Type) GetINT_CLR_DCT_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *JPEG_Type) SetINT_CLR_BS_LAST_BLOCK_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *JPEG_Type) GetINT_CLR_BS_LAST_BLOCK_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *JPEG_Type) SetINT_CLR_SCAN_CHECK_NONE_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *JPEG_Type) GetINT_CLR_SCAN_CHECK_NONE_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *JPEG_Type) SetINT_CLR_SCAN_CHECK_POS_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *JPEG_Type) GetINT_CLR_SCAN_CHECK_POS_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *JPEG_Type) SetINT_CLR_UXP_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *JPEG_Type) GetINT_CLR_UXP_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *JPEG_Type) SetINT_CLR_EN_FRAME_EOF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *JPEG_Type) GetINT_CLR_EN_FRAME_EOF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *JPEG_Type) SetINT_CLR_EN_FRAME_EOF_LACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *JPEG_Type) GetINT_CLR_EN_FRAME_EOF_LACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *JPEG_Type) SetINT_CLR_DE_FRAME_EOF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *JPEG_Type) GetINT_CLR_DE_FRAME_EOF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *JPEG_Type) SetINT_CLR_DE_FRAME_EOF_LACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *JPEG_Type) GetINT_CLR_DE_FRAME_EOF_LACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *JPEG_Type) SetINT_CLR_SOS_UNMATCH_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *JPEG_Type) GetINT_CLR_SOS_UNMATCH_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *JPEG_Type) SetINT_CLR_MARKER_ERR_FST_SCAN_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *JPEG_Type) GetINT_CLR_MARKER_ERR_FST_SCAN_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *JPEG_Type) SetINT_CLR_MARKER_ERR_OTHER_SCAN_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *JPEG_Type) GetINT_CLR_MARKER_ERR_OTHER_SCAN_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *JPEG_Type) SetINT_CLR_UNDET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *JPEG_Type) GetINT_CLR_UNDET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *JPEG_Type) SetINT_CLR_DECODE_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *JPEG_Type) GetINT_CLR_DECODE_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} + +// JPEG.STATUS0: Trace and Debug registers +func (o *JPEG_Type) SetSTATUS0_BITSTREAM_EOF_VLD_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS0.Reg, volatile.LoadUint32(&o.STATUS0.Reg)&^(0x1f800)|value<<11) +} +func (o *JPEG_Type) GetSTATUS0_BITSTREAM_EOF_VLD_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS0.Reg) & 0x1f800) >> 11 +} +func (o *JPEG_Type) SetSTATUS0_DCTOUT_ZZSCAN_ADDR(value uint32) { + volatile.StoreUint32(&o.STATUS0.Reg, volatile.LoadUint32(&o.STATUS0.Reg)&^(0x7e0000)|value<<17) +} +func (o *JPEG_Type) GetSTATUS0_DCTOUT_ZZSCAN_ADDR() uint32 { + return (volatile.LoadUint32(&o.STATUS0.Reg) & 0x7e0000) >> 17 +} +func (o *JPEG_Type) SetSTATUS0_QNRVAL_ZZSCAN_ADDR(value uint32) { + volatile.StoreUint32(&o.STATUS0.Reg, volatile.LoadUint32(&o.STATUS0.Reg)&^(0x1f800000)|value<<23) +} +func (o *JPEG_Type) GetSTATUS0_QNRVAL_ZZSCAN_ADDR() uint32 { + return (volatile.LoadUint32(&o.STATUS0.Reg) & 0x1f800000) >> 23 +} +func (o *JPEG_Type) SetSTATUS0_REG_STATE_YUV(value uint32) { + volatile.StoreUint32(&o.STATUS0.Reg, volatile.LoadUint32(&o.STATUS0.Reg)&^(0xe0000000)|value<<29) +} +func (o *JPEG_Type) GetSTATUS0_REG_STATE_YUV() uint32 { + return (volatile.LoadUint32(&o.STATUS0.Reg) & 0xe0000000) >> 29 +} + +// JPEG.STATUS2: Trace and Debug registers +func (o *JPEG_Type) SetSTATUS2_SOURCE_PIXEL(value uint32) { + volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0xffffff)|value) +} +func (o *JPEG_Type) GetSTATUS2_SOURCE_PIXEL() uint32 { + return volatile.LoadUint32(&o.STATUS2.Reg) & 0xffffff +} +func (o *JPEG_Type) SetSTATUS2_LAST_BLOCK(value uint32) { + volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0x1000000)|value<<24) +} +func (o *JPEG_Type) GetSTATUS2_LAST_BLOCK() uint32 { + return (volatile.LoadUint32(&o.STATUS2.Reg) & 0x1000000) >> 24 +} +func (o *JPEG_Type) SetSTATUS2_LAST_MCU(value uint32) { + volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0x2000000)|value<<25) +} +func (o *JPEG_Type) GetSTATUS2_LAST_MCU() uint32 { + return (volatile.LoadUint32(&o.STATUS2.Reg) & 0x2000000) >> 25 +} +func (o *JPEG_Type) SetSTATUS2_LAST_DC(value uint32) { + volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0x4000000)|value<<26) +} +func (o *JPEG_Type) GetSTATUS2_LAST_DC() uint32 { + return (volatile.LoadUint32(&o.STATUS2.Reg) & 0x4000000) >> 26 +} +func (o *JPEG_Type) SetSTATUS2_PACKFIFO_READY(value uint32) { + volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0x8000000)|value<<27) +} +func (o *JPEG_Type) GetSTATUS2_PACKFIFO_READY() uint32 { + return (volatile.LoadUint32(&o.STATUS2.Reg) & 0x8000000) >> 27 +} + +// JPEG.STATUS3: Trace and Debug registers +func (o *JPEG_Type) SetSTATUS3_YO(value uint32) { + volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x1ff)|value) +} +func (o *JPEG_Type) GetSTATUS3_YO() uint32 { + return volatile.LoadUint32(&o.STATUS3.Reg) & 0x1ff +} +func (o *JPEG_Type) SetSTATUS3_Y_READY(value uint32) { + volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x200)|value<<9) +} +func (o *JPEG_Type) GetSTATUS3_Y_READY() uint32 { + return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x200) >> 9 +} +func (o *JPEG_Type) SetSTATUS3_CBO(value uint32) { + volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x7fc00)|value<<10) +} +func (o *JPEG_Type) GetSTATUS3_CBO() uint32 { + return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x7fc00) >> 10 +} +func (o *JPEG_Type) SetSTATUS3_CB_READY(value uint32) { + volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x80000)|value<<19) +} +func (o *JPEG_Type) GetSTATUS3_CB_READY() uint32 { + return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x80000) >> 19 +} +func (o *JPEG_Type) SetSTATUS3_CRO(value uint32) { + volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x1ff00000)|value<<20) +} +func (o *JPEG_Type) GetSTATUS3_CRO() uint32 { + return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x1ff00000) >> 20 +} +func (o *JPEG_Type) SetSTATUS3_CR_READY(value uint32) { + volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x20000000)|value<<29) +} +func (o *JPEG_Type) GetSTATUS3_CR_READY() uint32 { + return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x20000000) >> 29 +} + +// JPEG.STATUS4: Trace and Debug registers +func (o *JPEG_Type) SetSTATUS4(value uint32) { + volatile.StoreUint32(&o.STATUS4.Reg, value) +} +func (o *JPEG_Type) GetSTATUS4() uint32 { + return volatile.LoadUint32(&o.STATUS4.Reg) +} + +// JPEG.DHT_TOTLEN_DC0: Trace and Debug registers +func (o *JPEG_Type) SetDHT_TOTLEN_DC0(value uint32) { + volatile.StoreUint32(&o.DHT_TOTLEN_DC0.Reg, value) +} +func (o *JPEG_Type) GetDHT_TOTLEN_DC0() uint32 { + return volatile.LoadUint32(&o.DHT_TOTLEN_DC0.Reg) +} + +// JPEG.DHT_VAl_DC0: Trace and Debug registers +func (o *JPEG_Type) SetDHT_VAl_DC0(value uint32) { + volatile.StoreUint32(&o.DHT_VAl_DC0.Reg, value) +} +func (o *JPEG_Type) GetDHT_VAl_DC0() uint32 { + return volatile.LoadUint32(&o.DHT_VAl_DC0.Reg) +} + +// JPEG.DHT_TOTLEN_AC0: Trace and Debug registers +func (o *JPEG_Type) SetDHT_TOTLEN_AC0(value uint32) { + volatile.StoreUint32(&o.DHT_TOTLEN_AC0.Reg, value) +} +func (o *JPEG_Type) GetDHT_TOTLEN_AC0() uint32 { + return volatile.LoadUint32(&o.DHT_TOTLEN_AC0.Reg) +} + +// JPEG.DHT_VAl_AC0: Trace and Debug registers +func (o *JPEG_Type) SetDHT_VAl_AC0(value uint32) { + volatile.StoreUint32(&o.DHT_VAl_AC0.Reg, value) +} +func (o *JPEG_Type) GetDHT_VAl_AC0() uint32 { + return volatile.LoadUint32(&o.DHT_VAl_AC0.Reg) +} + +// JPEG.DHT_TOTLEN_DC1: Trace and Debug registers +func (o *JPEG_Type) SetDHT_TOTLEN_DC1(value uint32) { + volatile.StoreUint32(&o.DHT_TOTLEN_DC1.Reg, value) +} +func (o *JPEG_Type) GetDHT_TOTLEN_DC1() uint32 { + return volatile.LoadUint32(&o.DHT_TOTLEN_DC1.Reg) +} + +// JPEG.DHT_VAl_DC1: Trace and Debug registers +func (o *JPEG_Type) SetDHT_VAl_DC1(value uint32) { + volatile.StoreUint32(&o.DHT_VAl_DC1.Reg, value) +} +func (o *JPEG_Type) GetDHT_VAl_DC1() uint32 { + return volatile.LoadUint32(&o.DHT_VAl_DC1.Reg) +} + +// JPEG.DHT_TOTLEN_AC1: Trace and Debug registers +func (o *JPEG_Type) SetDHT_TOTLEN_AC1(value uint32) { + volatile.StoreUint32(&o.DHT_TOTLEN_AC1.Reg, value) +} +func (o *JPEG_Type) GetDHT_TOTLEN_AC1() uint32 { + return volatile.LoadUint32(&o.DHT_TOTLEN_AC1.Reg) +} + +// JPEG.DHT_VAl_AC1: Trace and Debug registers +func (o *JPEG_Type) SetDHT_VAl_AC1(value uint32) { + volatile.StoreUint32(&o.DHT_VAl_AC1.Reg, value) +} +func (o *JPEG_Type) GetDHT_VAl_AC1() uint32 { + return volatile.LoadUint32(&o.DHT_VAl_AC1.Reg) +} + +// JPEG.DHT_CODEMIN_DC0: Trace and Debug registers +func (o *JPEG_Type) SetDHT_CODEMIN_DC0(value uint32) { + volatile.StoreUint32(&o.DHT_CODEMIN_DC0.Reg, value) +} +func (o *JPEG_Type) GetDHT_CODEMIN_DC0() uint32 { + return volatile.LoadUint32(&o.DHT_CODEMIN_DC0.Reg) +} + +// JPEG.DHT_CODEMIN_AC0: Trace and Debug registers +func (o *JPEG_Type) SetDHT_CODEMIN_AC0(value uint32) { + volatile.StoreUint32(&o.DHT_CODEMIN_AC0.Reg, value) +} +func (o *JPEG_Type) GetDHT_CODEMIN_AC0() uint32 { + return volatile.LoadUint32(&o.DHT_CODEMIN_AC0.Reg) +} + +// JPEG.DHT_CODEMIN_DC1: Trace and Debug registers +func (o *JPEG_Type) SetDHT_CODEMIN_DC1(value uint32) { + volatile.StoreUint32(&o.DHT_CODEMIN_DC1.Reg, value) +} +func (o *JPEG_Type) GetDHT_CODEMIN_DC1() uint32 { + return volatile.LoadUint32(&o.DHT_CODEMIN_DC1.Reg) +} + +// JPEG.DHT_CODEMIN_AC1: Trace and Debug registers +func (o *JPEG_Type) SetDHT_CODEMIN_AC1(value uint32) { + volatile.StoreUint32(&o.DHT_CODEMIN_AC1.Reg, value) +} +func (o *JPEG_Type) GetDHT_CODEMIN_AC1() uint32 { + return volatile.LoadUint32(&o.DHT_CODEMIN_AC1.Reg) +} + +// JPEG.DECODER_STATUS0: Trace and Debug registers +func (o *JPEG_Type) SetDECODER_STATUS0_DECODE_BYTE_CNT(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS0.Reg, volatile.LoadUint32(&o.DECODER_STATUS0.Reg)&^(0x3ffffff)|value) +} +func (o *JPEG_Type) GetDECODER_STATUS0_DECODE_BYTE_CNT() uint32 { + return volatile.LoadUint32(&o.DECODER_STATUS0.Reg) & 0x3ffffff +} +func (o *JPEG_Type) SetDECODER_STATUS0_HEADER_DEC_ST(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS0.Reg, volatile.LoadUint32(&o.DECODER_STATUS0.Reg)&^(0x3c000000)|value<<26) +} +func (o *JPEG_Type) GetDECODER_STATUS0_HEADER_DEC_ST() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS0.Reg) & 0x3c000000) >> 26 +} +func (o *JPEG_Type) SetDECODER_STATUS0_DECODE_SAMPLE_SEL(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS0.Reg, volatile.LoadUint32(&o.DECODER_STATUS0.Reg)&^(0xc0000000)|value<<30) +} +func (o *JPEG_Type) GetDECODER_STATUS0_DECODE_SAMPLE_SEL() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS0.Reg) & 0xc0000000) >> 30 +} + +// JPEG.DECODER_STATUS1: Trace and Debug registers +func (o *JPEG_Type) SetDECODER_STATUS1_ENCODE_DATA(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS1.Reg, volatile.LoadUint32(&o.DECODER_STATUS1.Reg)&^(0xffff)|value) +} +func (o *JPEG_Type) GetDECODER_STATUS1_ENCODE_DATA() uint32 { + return volatile.LoadUint32(&o.DECODER_STATUS1.Reg) & 0xffff +} +func (o *JPEG_Type) SetDECODER_STATUS1_COUNT_Q(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS1.Reg, volatile.LoadUint32(&o.DECODER_STATUS1.Reg)&^(0x7f0000)|value<<16) +} +func (o *JPEG_Type) GetDECODER_STATUS1_COUNT_Q() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS1.Reg) & 0x7f0000) >> 16 +} +func (o *JPEG_Type) SetDECODER_STATUS1_MCU_FSM_READY(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS1.Reg, volatile.LoadUint32(&o.DECODER_STATUS1.Reg)&^(0x800000)|value<<23) +} +func (o *JPEG_Type) GetDECODER_STATUS1_MCU_FSM_READY() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS1.Reg) & 0x800000) >> 23 +} +func (o *JPEG_Type) SetDECODER_STATUS1_DECODE_DATA(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS1.Reg, volatile.LoadUint32(&o.DECODER_STATUS1.Reg)&^(0xff000000)|value<<24) +} +func (o *JPEG_Type) GetDECODER_STATUS1_DECODE_DATA() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS1.Reg) & 0xff000000) >> 24 +} + +// JPEG.DECODER_STATUS2: Trace and Debug registers +func (o *JPEG_Type) SetDECODER_STATUS2_COMP_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x3ffffff)|value) +} +func (o *JPEG_Type) GetDECODER_STATUS2_COMP_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x3ffffff +} +func (o *JPEG_Type) SetDECODER_STATUS2_SCAN_NUM(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x1c000000)|value<<26) +} +func (o *JPEG_Type) GetDECODER_STATUS2_SCAN_NUM() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x1c000000) >> 26 +} +func (o *JPEG_Type) SetDECODER_STATUS2_RST_CHECK_WAIT(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x20000000)|value<<29) +} +func (o *JPEG_Type) GetDECODER_STATUS2_RST_CHECK_WAIT() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x20000000) >> 29 +} +func (o *JPEG_Type) SetDECODER_STATUS2_SCAN_CHECK_WAIT(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x40000000)|value<<30) +} +func (o *JPEG_Type) GetDECODER_STATUS2_SCAN_CHECK_WAIT() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x40000000) >> 30 +} +func (o *JPEG_Type) SetDECODER_STATUS2_MCU_IN_PROC(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x80000000)|value<<31) +} +func (o *JPEG_Type) GetDECODER_STATUS2_MCU_IN_PROC() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x80000000) >> 31 +} + +// JPEG.DECODER_STATUS3: Trace and Debug registers +func (o *JPEG_Type) SetDECODER_STATUS3(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS3.Reg, value) +} +func (o *JPEG_Type) GetDECODER_STATUS3() uint32 { + return volatile.LoadUint32(&o.DECODER_STATUS3.Reg) +} + +// JPEG.DECODER_STATUS4: Trace and Debug registers +func (o *JPEG_Type) SetDECODER_STATUS4_BLOCK_EOF_CNT(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS4.Reg, volatile.LoadUint32(&o.DECODER_STATUS4.Reg)&^(0x3ffffff)|value) +} +func (o *JPEG_Type) GetDECODER_STATUS4_BLOCK_EOF_CNT() uint32 { + return volatile.LoadUint32(&o.DECODER_STATUS4.Reg) & 0x3ffffff +} +func (o *JPEG_Type) SetDECODER_STATUS4_DEZIGZAG_READY(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS4.Reg, volatile.LoadUint32(&o.DECODER_STATUS4.Reg)&^(0x4000000)|value<<26) +} +func (o *JPEG_Type) GetDECODER_STATUS4_DEZIGZAG_READY() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS4.Reg) & 0x4000000) >> 26 +} +func (o *JPEG_Type) SetDECODER_STATUS4_DE_FRAME_EOF_CHECK(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS4.Reg, volatile.LoadUint32(&o.DECODER_STATUS4.Reg)&^(0x8000000)|value<<27) +} +func (o *JPEG_Type) GetDECODER_STATUS4_DE_FRAME_EOF_CHECK() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS4.Reg) & 0x8000000) >> 27 +} +func (o *JPEG_Type) SetDECODER_STATUS4_DE_DMA2D_IN_PUSH(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS4.Reg, volatile.LoadUint32(&o.DECODER_STATUS4.Reg)&^(0x10000000)|value<<28) +} +func (o *JPEG_Type) GetDECODER_STATUS4_DE_DMA2D_IN_PUSH() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS4.Reg) & 0x10000000) >> 28 +} + +// JPEG.DECODER_STATUS5: Trace and Debug registers +func (o *JPEG_Type) SetDECODER_STATUS5_IDCT_HFM_DATA(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0xffff)|value) +} +func (o *JPEG_Type) GetDECODER_STATUS5_IDCT_HFM_DATA() uint32 { + return volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0xffff +} +func (o *JPEG_Type) SetDECODER_STATUS5_NS0(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x70000)|value<<16) +} +func (o *JPEG_Type) GetDECODER_STATUS5_NS0() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x70000) >> 16 +} +func (o *JPEG_Type) SetDECODER_STATUS5_NS1(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x380000)|value<<19) +} +func (o *JPEG_Type) GetDECODER_STATUS5_NS1() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x380000) >> 19 +} +func (o *JPEG_Type) SetDECODER_STATUS5_NS2(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x1c00000)|value<<22) +} +func (o *JPEG_Type) GetDECODER_STATUS5_NS2() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x1c00000) >> 22 +} +func (o *JPEG_Type) SetDECODER_STATUS5_NS3(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0xe000000)|value<<25) +} +func (o *JPEG_Type) GetDECODER_STATUS5_NS3() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0xe000000) >> 25 +} +func (o *JPEG_Type) SetDECODER_STATUS5_DATA_LAST_O(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x10000000)|value<<28) +} +func (o *JPEG_Type) GetDECODER_STATUS5_DATA_LAST_O() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x10000000) >> 28 +} +func (o *JPEG_Type) SetDECODER_STATUS5_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x20000000)|value<<29) +} +func (o *JPEG_Type) GetDECODER_STATUS5_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x20000000) >> 29 +} +func (o *JPEG_Type) SetDECODER_STATUS5_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x40000000)|value<<30) +} +func (o *JPEG_Type) GetDECODER_STATUS5_RDN_ENA() uint32 { + return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x40000000) >> 30 +} + +// JPEG.STATUS5: Trace and Debug registers +func (o *JPEG_Type) SetSTATUS5_PIC_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.STATUS5.Reg, volatile.LoadUint32(&o.STATUS5.Reg)&^(0xffffff)|value) +} +func (o *JPEG_Type) GetSTATUS5_PIC_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.STATUS5.Reg) & 0xffffff +} + +// JPEG.ECO_LOW: Trace and Debug registers +func (o *JPEG_Type) SetECO_LOW(value uint32) { + volatile.StoreUint32(&o.ECO_LOW.Reg, value) +} +func (o *JPEG_Type) GetECO_LOW() uint32 { + return volatile.LoadUint32(&o.ECO_LOW.Reg) +} + +// JPEG.ECO_HIGH: Trace and Debug registers +func (o *JPEG_Type) SetECO_HIGH(value uint32) { + volatile.StoreUint32(&o.ECO_HIGH.Reg, value) +} +func (o *JPEG_Type) GetECO_HIGH() uint32 { + return volatile.LoadUint32(&o.ECO_HIGH.Reg) +} + +// JPEG.SYS: Trace and Debug registers +func (o *JPEG_Type) SetSYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYS.Reg, volatile.LoadUint32(&o.SYS.Reg)&^(0x80000000)|value<<31) +} +func (o *JPEG_Type) GetSYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYS.Reg) & 0x80000000) >> 31 +} + +// JPEG.VERSION: Trace and Debug registers +func (o *JPEG_Type) SetVERSION_JPEG_VER(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *JPEG_Type) GetVERSION_JPEG_VER() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// Camera/LCD Controller +type LCDCAM_Type struct { + LCD_CLOCK volatile.Register32 // 0x0 + CAM_CTRL volatile.Register32 // 0x4 + CAM_CTRL1 volatile.Register32 // 0x8 + CAM_RGB_YUV volatile.Register32 // 0xC + LCD_RGB_YUV volatile.Register32 // 0x10 + LCD_USER volatile.Register32 // 0x14 + LCD_MISC volatile.Register32 // 0x18 + LCD_CTRL volatile.Register32 // 0x1C + LCD_CTRL1 volatile.Register32 // 0x20 + LCD_CTRL2 volatile.Register32 // 0x24 + LCD_FIRST_CMD_VAL volatile.Register32 // 0x28 + LCD_LATTER_CMD_VAL volatile.Register32 // 0x2C + LCD_DLY_MODE_CFG1 volatile.Register32 // 0x30 + _ [4]byte + LCD_DLY_MODE_CFG2 volatile.Register32 // 0x38 + _ [40]byte + LC_DMA_INT_ENA volatile.Register32 // 0x64 + LC_DMA_INT_RAW volatile.Register32 // 0x68 + LC_DMA_INT_ST volatile.Register32 // 0x6C + LC_DMA_INT_CLR volatile.Register32 // 0x70 + _ [136]byte + LC_REG_DATE volatile.Register32 // 0xFC +} + +// LCDCAM.LCD_CLOCK: LCD clock config register. +func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x3f)|value) +} +func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLKCNT_N() uint32 { + return volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x3f +} +func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x40)|value<<6) +} +func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x40) >> 6 +} +func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x80)|value<<7) +} +func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x80) >> 7 +} +func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x100)|value<<8) +} +func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x100) >> 8 +} +func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x1fe00)|value<<9) +} +func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x1fe00) >> 9 +} +func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x7e0000)|value<<17) +} +func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x7e0000) >> 17 +} +func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x1f800000)|value<<23) +} +func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x1f800000) >> 23 +} +func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x60000000)|value<<29) +} +func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x60000000) >> 29 +} +func (o *LCDCAM_Type) SetLCD_CLOCK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *LCDCAM_Type) GetLCD_CLOCK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x80000000) >> 31 +} + +// LCDCAM.CAM_CTRL: CAM config register. +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x1)|value) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_STOP_EN() uint32 { + return volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x1 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_VSYNC_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0xe)|value<<1) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_VSYNC_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0xe) >> 1 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_UPDATE(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x10) >> 4 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x20) >> 5 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x40) >> 6 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_LINE_INT_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_LINE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x80) >> 7 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_VS_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_VS_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x100) >> 8 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x1fe00)|value<<9) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x1fe00) >> 9 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x7e0000)|value<<17) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x7e0000) >> 17 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x1f800000)|value<<23) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x1f800000) >> 23 +} +func (o *LCDCAM_Type) SetCAM_CTRL_CAM_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x60000000)|value<<29) +} +func (o *LCDCAM_Type) GetCAM_CTRL_CAM_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x60000000) >> 29 +} + +// LCDCAM.CAM_CTRL1: CAM config register. +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_REC_DATA_BYTELEN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0xffff)|value) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_REC_DATA_BYTELEN() uint32 { + return volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0xffff +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_LINE_INT_NUM(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x3f0000)|value<<16) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_LINE_INT_NUM() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x3f0000) >> 16 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_CLK_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x400000)|value<<22) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x400000) >> 22 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_VSYNC_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x800000)|value<<23) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_VSYNC_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x800000) >> 23 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_2BYTE_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_2BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_DE_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_DE_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x2000000) >> 25 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_HSYNC_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x4000000)|value<<26) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_HSYNC_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x4000000) >> 26 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_VSYNC_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x8000000)|value<<27) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_VSYNC_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x8000000) >> 27 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_VH_DE_MODE_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x10000000)|value<<28) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_VH_DE_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x10000000) >> 28 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_START(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x20000000)|value<<29) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_START() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x20000000) >> 29 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_RESET(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_RESET() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x40000000) >> 30 +} +func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_AFIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x80000000)|value<<31) +} +func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_AFIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x80000000) >> 31 +} + +// LCDCAM.CAM_RGB_YUV: CAM YUV/RGB converter configuration register. +func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x200000)|value<<21) +} +func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x200000) >> 21 +} +func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0xc00000)|value<<22) +} +func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0xc00000) >> 22 +} +func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_YUV_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x3000000)|value<<24) +} +func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_YUV_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x3000000) >> 24 +} +func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x4000000)|value<<26) +} +func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x4000000) >> 26 +} +func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x8000000)|value<<27) +} +func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x8000000) >> 27 +} +func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_DATA_IN_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x10000000)|value<<28) +} +func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_DATA_IN_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x10000000) >> 28 +} +func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x20000000)|value<<29) +} +func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x20000000) >> 29 +} +func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_TRANS_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x40000000)|value<<30) +} +func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_TRANS_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x40000000) >> 30 +} +func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_ENABLE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x80000000)|value<<31) +} +func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x80000000) >> 31 +} + +// LCDCAM.LCD_RGB_YUV: LCD YUV/RGB converter configuration register. +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x100000)|value<<20) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x100000) >> 20 +} +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_TXTORX(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x200000)|value<<21) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_TXTORX() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x200000) >> 21 +} +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0xc00000)|value<<22) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0xc00000) >> 22 +} +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_YUV_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x3000000)|value<<24) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_YUV_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x3000000) >> 24 +} +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x4000000)|value<<26) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x4000000) >> 26 +} +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x8000000)|value<<27) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x8000000) >> 27 +} +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_DATA_IN_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x10000000)|value<<28) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_DATA_IN_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x10000000) >> 28 +} +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x20000000)|value<<29) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x20000000) >> 29 +} +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_TRANS_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x40000000)|value<<30) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_TRANS_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x40000000) >> 30 +} +func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_ENABLE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x80000000)|value<<31) +} +func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_ENABLE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x80000000) >> 31 +} + +// LCDCAM.LCD_USER: LCD config register. +func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x1fff)|value) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.LCD_USER.Reg) & 0x1fff +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_ALWAYS_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x2000)|value<<13) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_ALWAYS_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x2000) >> 13 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT_BYTE_SWIZZLE_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x1c000)|value<<14) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT_BYTE_SWIZZLE_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x1c000) >> 14 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT_BYTE_SWIZZLE_ENABLE(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x20000)|value<<17) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT_BYTE_SWIZZLE_ENABLE() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x20000) >> 17 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x40000)|value<<18) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x40000) >> 18 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_BYTE_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x180000)|value<<19) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_BYTE_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x180000) >> 19 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_UPDATE(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x200000)|value<<21) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_UPDATE() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x200000) >> 21 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x400000)|value<<22) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x400000) >> 22 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x800000)|value<<23) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x800000) >> 23 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x1000000)|value<<24) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x1000000) >> 24 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_DUMMY(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x2000000)|value<<25) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_DUMMY() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x2000000) >> 25 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_CMD(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_CMD() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x4000000) >> 26 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_START(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x8000000)|value<<27) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_START() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x8000000) >> 27 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_RESET(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x10000000)|value<<28) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_RESET() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x10000000) >> 28 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x60000000)|value<<29) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x60000000) >> 29 +} +func (o *LCDCAM_Type) SetLCD_USER_LCD_CMD_2_CYCLE_EN(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x80000000)|value<<31) +} +func (o *LCDCAM_Type) GetLCD_USER_LCD_CMD_2_CYCLE_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x80000000) >> 31 +} + +// LCDCAM.LCD_MISC: LCD config register. +func (o *LCDCAM_Type) SetLCD_MISC_LCD_WIRE_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x30)|value<<4) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_WIRE_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x30) >> 4 +} +func (o *LCDCAM_Type) SetLCD_MISC_LCD_VFK_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0xfc0)|value<<6) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_VFK_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0xfc0) >> 6 +} +func (o *LCDCAM_Type) SetLCD_MISC_LCD_VBK_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x1fff000)|value<<12) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_VBK_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x1fff000) >> 12 +} +func (o *LCDCAM_Type) SetLCD_MISC_LCD_NEXT_FRAME_EN(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x2000000)|value<<25) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_NEXT_FRAME_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x2000000) >> 25 +} +func (o *LCDCAM_Type) SetLCD_MISC_LCD_BK_EN(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x4000000)|value<<26) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_BK_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x4000000) >> 26 +} +func (o *LCDCAM_Type) SetLCD_MISC_LCD_AFIFO_RESET(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x8000000)|value<<27) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_AFIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x8000000) >> 27 +} +func (o *LCDCAM_Type) SetLCD_MISC_LCD_CD_DATA_SET(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x10000000)|value<<28) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_CD_DATA_SET() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x10000000) >> 28 +} +func (o *LCDCAM_Type) SetLCD_MISC_LCD_CD_DUMMY_SET(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_CD_DUMMY_SET() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x20000000) >> 29 +} +func (o *LCDCAM_Type) SetLCD_MISC_LCD_CD_CMD_SET(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_CD_CMD_SET() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x40000000) >> 30 +} +func (o *LCDCAM_Type) SetLCD_MISC_LCD_CD_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *LCDCAM_Type) GetLCD_MISC_LCD_CD_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x80000000) >> 31 +} + +// LCDCAM.LCD_CTRL: LCD config register. +func (o *LCDCAM_Type) SetLCD_CTRL_LCD_HB_FRONT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x7ff)|value) +} +func (o *LCDCAM_Type) GetLCD_CTRL_LCD_HB_FRONT() uint32 { + return volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x7ff +} +func (o *LCDCAM_Type) SetLCD_CTRL_LCD_VA_HEIGHT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x1ff800)|value<<11) +} +func (o *LCDCAM_Type) GetLCD_CTRL_LCD_VA_HEIGHT() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x1ff800) >> 11 +} +func (o *LCDCAM_Type) SetLCD_CTRL_LCD_VT_HEIGHT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LCDCAM_Type) GetLCD_CTRL_LCD_VT_HEIGHT() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x7fe00000) >> 21 +} +func (o *LCDCAM_Type) SetLCD_CTRL_LCD_RGB_MODE_EN(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *LCDCAM_Type) GetLCD_CTRL_LCD_RGB_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x80000000) >> 31 +} + +// LCDCAM.LCD_CTRL1: LCD config register. +func (o *LCDCAM_Type) SetLCD_CTRL1_LCD_VB_FRONT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xff)|value) +} +func (o *LCDCAM_Type) GetLCD_CTRL1_LCD_VB_FRONT() uint32 { + return volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xff +} +func (o *LCDCAM_Type) SetLCD_CTRL1_LCD_HA_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xfff00)|value<<8) +} +func (o *LCDCAM_Type) GetLCD_CTRL1_LCD_HA_WIDTH() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xfff00) >> 8 +} +func (o *LCDCAM_Type) SetLCD_CTRL1_LCD_HT_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xfff00000)|value<<20) +} +func (o *LCDCAM_Type) GetLCD_CTRL1_LCD_HT_WIDTH() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xfff00000) >> 20 +} + +// LCDCAM.LCD_CTRL2: LCD config register. +func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_VSYNC_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x7f)|value) +} +func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_VSYNC_WIDTH() uint32 { + return volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x7f +} +func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_VSYNC_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x80)|value<<7) +} +func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_VSYNC_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x80) >> 7 +} +func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_DE_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x100)|value<<8) +} +func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_DE_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x100) >> 8 +} +func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_HS_BLANK_EN(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_HS_BLANK_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x200) >> 9 +} +func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_HSYNC_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x7f0000)|value<<16) +} +func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_HSYNC_WIDTH() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x7f0000) >> 16 +} +func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_HSYNC_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x800000)|value<<23) +} +func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_HSYNC_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x800000) >> 23 +} +func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_HSYNC_POSITION(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0xff000000)|value<<24) +} +func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_HSYNC_POSITION() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0xff000000) >> 24 +} + +// LCDCAM.LCD_FIRST_CMD_VAL: LCD config register. +func (o *LCDCAM_Type) SetLCD_FIRST_CMD_VAL(value uint32) { + volatile.StoreUint32(&o.LCD_FIRST_CMD_VAL.Reg, value) +} +func (o *LCDCAM_Type) GetLCD_FIRST_CMD_VAL() uint32 { + return volatile.LoadUint32(&o.LCD_FIRST_CMD_VAL.Reg) +} + +// LCDCAM.LCD_LATTER_CMD_VAL: LCD config register. +func (o *LCDCAM_Type) SetLCD_LATTER_CMD_VAL(value uint32) { + volatile.StoreUint32(&o.LCD_LATTER_CMD_VAL.Reg, value) +} +func (o *LCDCAM_Type) GetLCD_LATTER_CMD_VAL() uint32 { + return volatile.LoadUint32(&o.LCD_LATTER_CMD_VAL.Reg) +} + +// LCDCAM.LCD_DLY_MODE_CFG1: LCD config register. +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT16_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x3)|value) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT16_MODE() uint32 { + return volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x3 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT17_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc)|value<<2) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT17_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc) >> 2 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT18_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x30)|value<<4) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT18_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x30) >> 4 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT19_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc0)|value<<6) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT19_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc0) >> 6 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT20_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x300)|value<<8) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT20_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x300) >> 8 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT21_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc00)|value<<10) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT21_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc00) >> 10 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT22_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x3000)|value<<12) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT22_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x3000) >> 12 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT23_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc000)|value<<14) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT23_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc000) >> 14 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_LCD_CD_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x30000)|value<<16) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_LCD_CD_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x30000) >> 16 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_LCD_DE_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc0000)|value<<18) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_LCD_DE_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc0000) >> 18 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_LCD_HSYNC_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x300000)|value<<20) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_LCD_HSYNC_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x300000) >> 20 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_LCD_VSYNC_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc00000)|value<<22) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_LCD_VSYNC_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc00000) >> 22 +} + +// LCDCAM.LCD_DLY_MODE_CFG2: LCD config register. +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x3)|value) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x3 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc)|value<<2) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc) >> 2 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x30)|value<<4) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x30) >> 4 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc0)|value<<6) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc0) >> 6 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x300)|value<<8) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x300) >> 8 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc00)|value<<10) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc00) >> 10 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x3000)|value<<12) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x3000) >> 12 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc000)|value<<14) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc000) >> 14 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT8_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x30000)|value<<16) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT8_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x30000) >> 16 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT9_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc0000)|value<<18) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT9_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc0000) >> 18 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT10_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x300000)|value<<20) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT10_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x300000) >> 20 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT11_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc00000)|value<<22) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT11_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc00000) >> 22 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT12_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x3000000)|value<<24) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT12_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x3000000) >> 24 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT13_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc000000)|value<<26) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT13_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc000000) >> 26 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT14_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x30000000)|value<<28) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT14_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x30000000) >> 28 +} +func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT15_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc0000000)|value<<30) +} +func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT15_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc0000000) >> 30 +} + +// LCDCAM.LC_DMA_INT_ENA: LCDCAM interrupt enable register. +func (o *LCDCAM_Type) SetLC_DMA_INT_ENA_LCD_VSYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_ENA_LCD_VSYNC_INT_ENA() uint32 { + return volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x1 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_ENA_CAM_VSYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_ENA_CAM_VSYNC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_ENA_CAM_HS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_ENA_CAM_HS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x8) >> 3 +} + +// LCDCAM.LC_DMA_INT_RAW: LCDCAM interrupt raw register, valid in level. +func (o *LCDCAM_Type) SetLC_DMA_INT_RAW_LCD_VSYNC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_RAW_LCD_VSYNC_INT_RAW() uint32 { + return volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x1 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_RAW_CAM_VSYNC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_RAW_CAM_VSYNC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_RAW_CAM_HS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_RAW_CAM_HS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x8) >> 3 +} + +// LCDCAM.LC_DMA_INT_ST: LCDCAM interrupt status register. +func (o *LCDCAM_Type) SetLC_DMA_INT_ST_LCD_VSYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_ST_LCD_VSYNC_INT_ST() uint32 { + return volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x1 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_ST_CAM_VSYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_ST_CAM_VSYNC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_ST_CAM_HS_INT_ST(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_ST_CAM_HS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x8) >> 3 +} + +// LCDCAM.LC_DMA_INT_CLR: LCDCAM interrupt clear register. +func (o *LCDCAM_Type) SetLC_DMA_INT_CLR_LCD_VSYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_CLR_LCD_VSYNC_INT_CLR() uint32 { + return volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x1 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_CLR_CAM_VSYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_CLR_CAM_VSYNC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LCDCAM_Type) SetLC_DMA_INT_CLR_CAM_HS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LCDCAM_Type) GetLC_DMA_INT_CLR_CAM_HS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x8) >> 3 +} + +// LCDCAM.LC_REG_DATE: Version register +func (o *LCDCAM_Type) SetLC_REG_DATE_LC_DATE(value uint32) { + volatile.StoreUint32(&o.LC_REG_DATE.Reg, volatile.LoadUint32(&o.LC_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *LCDCAM_Type) GetLC_REG_DATE_LC_DATE() uint32 { + return volatile.LoadUint32(&o.LC_REG_DATE.Reg) & 0xfffffff +} + +// LED Control PWM (Pulse Width Modulation) +type LEDC_Type struct { + CH0_CONF0 volatile.Register32 // 0x0 + CH0_HPOINT volatile.Register32 // 0x4 + CH0_DUTY volatile.Register32 // 0x8 + CH0_CONF1 volatile.Register32 // 0xC + CH0_DUTY_R volatile.Register32 // 0x10 + CH1_CONF0 volatile.Register32 // 0x14 + CH1_HPOINT volatile.Register32 // 0x18 + CH1_DUTY volatile.Register32 // 0x1C + CH1_CONF1 volatile.Register32 // 0x20 + CH1_DUTY_R volatile.Register32 // 0x24 + CH2_CONF0 volatile.Register32 // 0x28 + CH2_HPOINT volatile.Register32 // 0x2C + CH2_DUTY volatile.Register32 // 0x30 + CH2_CONF1 volatile.Register32 // 0x34 + CH2_DUTY_R volatile.Register32 // 0x38 + CH3_CONF0 volatile.Register32 // 0x3C + CH3_HPOINT volatile.Register32 // 0x40 + CH3_DUTY volatile.Register32 // 0x44 + CH3_CONF1 volatile.Register32 // 0x48 + CH3_DUTY_R volatile.Register32 // 0x4C + CH4_CONF0 volatile.Register32 // 0x50 + CH4_HPOINT volatile.Register32 // 0x54 + CH4_DUTY volatile.Register32 // 0x58 + CH4_CONF1 volatile.Register32 // 0x5C + CH4_DUTY_R volatile.Register32 // 0x60 + CH5_CONF0 volatile.Register32 // 0x64 + CH5_HPOINT volatile.Register32 // 0x68 + CH5_DUTY volatile.Register32 // 0x6C + CH5_CONF1 volatile.Register32 // 0x70 + CH5_DUTY_R volatile.Register32 // 0x74 + CH6_CONF0 volatile.Register32 // 0x78 + CH6_HPOINT volatile.Register32 // 0x7C + CH6_DUTY volatile.Register32 // 0x80 + CH6_CONF1 volatile.Register32 // 0x84 + CH6_DUTY_R volatile.Register32 // 0x88 + CH7_CONF0 volatile.Register32 // 0x8C + CH7_HPOINT volatile.Register32 // 0x90 + CH7_DUTY volatile.Register32 // 0x94 + CH7_CONF1 volatile.Register32 // 0x98 + CH7_DUTY_R volatile.Register32 // 0x9C + TIMER0_CONF volatile.Register32 // 0xA0 + TIMER0_VALUE volatile.Register32 // 0xA4 + TIMER1_CONF volatile.Register32 // 0xA8 + TIMER1_VALUE volatile.Register32 // 0xAC + TIMER2_CONF volatile.Register32 // 0xB0 + TIMER2_VALUE volatile.Register32 // 0xB4 + TIMER3_CONF volatile.Register32 // 0xB8 + TIMER3_VALUE volatile.Register32 // 0xBC + INT_RAW volatile.Register32 // 0xC0 + INT_ST volatile.Register32 // 0xC4 + INT_ENA volatile.Register32 // 0xC8 + INT_CLR volatile.Register32 // 0xCC + _ [48]byte + CH0_GAMMA_CONF volatile.Register32 // 0x100 + CH1_GAMMA_CONF volatile.Register32 // 0x104 + CH2_GAMMA_CONF volatile.Register32 // 0x108 + CH3_GAMMA_CONF volatile.Register32 // 0x10C + CH4_GAMMA_CONF volatile.Register32 // 0x110 + CH5_GAMMA_CONF volatile.Register32 // 0x114 + CH6_GAMMA_CONF volatile.Register32 // 0x118 + CH7_GAMMA_CONF volatile.Register32 // 0x11C + EVT_TASK_EN0 volatile.Register32 // 0x120 + EVT_TASK_EN1 volatile.Register32 // 0x124 + EVT_TASK_EN2 volatile.Register32 // 0x128 + _ [20]byte + TIMER0_CMP volatile.Register32 // 0x140 + TIMER1_CMP volatile.Register32 // 0x144 + TIMER2_CMP volatile.Register32 // 0x148 + TIMER3_CMP volatile.Register32 // 0x14C + TIMER0_CNT_CAP volatile.Register32 // 0x150 + TIMER1_CNT_CAP volatile.Register32 // 0x154 + TIMER2_CNT_CAP volatile.Register32 // 0x158 + TIMER3_CNT_CAP volatile.Register32 // 0x15C + _ [16]byte + CONF volatile.Register32 // 0x170 + DATE volatile.Register32 // 0x174 +} + +// LEDC.CH0_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH0_CONF0_TIMER_SEL_CH(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH0_CONF0_TIMER_SEL_CH() uint32 { + return volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH0_CONF0_SIG_OUT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH0_CONF0_SIG_OUT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH0_CONF0_IDLE_LV_CH(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH0_CONF0_IDLE_LV_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH0_CONF0_PARA_UP_CH(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH0_CONF0_PARA_UP_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH0_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH0_HPOINT_HPOINT_CH(value uint32) { + volatile.StoreUint32(&o.CH0_HPOINT.Reg, volatile.LoadUint32(&o.CH0_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH0_HPOINT_HPOINT_CH() uint32 { + return volatile.LoadUint32(&o.CH0_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH0_DUTY: Initial duty cycle register for channel %s +func (o *LEDC_Type) SetCH0_DUTY_DUTY_CH(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY.Reg, volatile.LoadUint32(&o.CH0_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_DUTY_CH() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH0_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH0_CONF1_DUTY_START_CH(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_START_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH0_DUTY_R: Current duty cycle register for channel %s +func (o *LEDC_Type) SetCH0_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY_R.Reg, volatile.LoadUint32(&o.CH0_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH1_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH1_CONF0_TIMER_SEL_CH(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH1_CONF0_TIMER_SEL_CH() uint32 { + return volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH1_CONF0_SIG_OUT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH1_CONF0_SIG_OUT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH1_CONF0_IDLE_LV_CH(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH1_CONF0_IDLE_LV_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH1_CONF0_PARA_UP_CH(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH1_CONF0_PARA_UP_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH1_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH1_HPOINT_HPOINT_CH(value uint32) { + volatile.StoreUint32(&o.CH1_HPOINT.Reg, volatile.LoadUint32(&o.CH1_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH1_HPOINT_HPOINT_CH() uint32 { + return volatile.LoadUint32(&o.CH1_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH1_DUTY: Initial duty cycle register for channel %s +func (o *LEDC_Type) SetCH1_DUTY_DUTY_CH(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY.Reg, volatile.LoadUint32(&o.CH1_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_DUTY_CH() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH1_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH1_CONF1_DUTY_START_CH(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_START_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH1_DUTY_R: Current duty cycle register for channel %s +func (o *LEDC_Type) SetCH1_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY_R.Reg, volatile.LoadUint32(&o.CH1_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH2_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH2_CONF0_TIMER_SEL_CH(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH2_CONF0_TIMER_SEL_CH() uint32 { + return volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH2_CONF0_SIG_OUT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH2_CONF0_SIG_OUT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH2_CONF0_IDLE_LV_CH(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH2_CONF0_IDLE_LV_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH2_CONF0_PARA_UP_CH(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH2_CONF0_PARA_UP_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH2_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH2_HPOINT_HPOINT_CH(value uint32) { + volatile.StoreUint32(&o.CH2_HPOINT.Reg, volatile.LoadUint32(&o.CH2_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH2_HPOINT_HPOINT_CH() uint32 { + return volatile.LoadUint32(&o.CH2_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH2_DUTY: Initial duty cycle register for channel %s +func (o *LEDC_Type) SetCH2_DUTY_DUTY_CH(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY.Reg, volatile.LoadUint32(&o.CH2_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_DUTY_CH() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH2_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH2_CONF1_DUTY_START_CH(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_START_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH2_DUTY_R: Current duty cycle register for channel %s +func (o *LEDC_Type) SetCH2_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY_R.Reg, volatile.LoadUint32(&o.CH2_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH3_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH3_CONF0_TIMER_SEL_CH(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH3_CONF0_TIMER_SEL_CH() uint32 { + return volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH3_CONF0_SIG_OUT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH3_CONF0_SIG_OUT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH3_CONF0_IDLE_LV_CH(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH3_CONF0_IDLE_LV_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH3_CONF0_PARA_UP_CH(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH3_CONF0_PARA_UP_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH3_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH3_HPOINT_HPOINT_CH(value uint32) { + volatile.StoreUint32(&o.CH3_HPOINT.Reg, volatile.LoadUint32(&o.CH3_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH3_HPOINT_HPOINT_CH() uint32 { + return volatile.LoadUint32(&o.CH3_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH3_DUTY: Initial duty cycle register for channel %s +func (o *LEDC_Type) SetCH3_DUTY_DUTY_CH(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY.Reg, volatile.LoadUint32(&o.CH3_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_DUTY_CH() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH3_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH3_CONF1_DUTY_START_CH(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_START_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH3_DUTY_R: Current duty cycle register for channel %s +func (o *LEDC_Type) SetCH3_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY_R.Reg, volatile.LoadUint32(&o.CH3_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH4_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH4_CONF0_TIMER_SEL_CH(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH4_CONF0_TIMER_SEL_CH() uint32 { + return volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH4_CONF0_SIG_OUT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH4_CONF0_SIG_OUT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH4_CONF0_IDLE_LV_CH(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH4_CONF0_IDLE_LV_CH() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH4_CONF0_PARA_UP_CH(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH4_CONF0_PARA_UP_CH() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH4_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH4_HPOINT_HPOINT_CH(value uint32) { + volatile.StoreUint32(&o.CH4_HPOINT.Reg, volatile.LoadUint32(&o.CH4_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH4_HPOINT_HPOINT_CH() uint32 { + return volatile.LoadUint32(&o.CH4_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH4_DUTY: Initial duty cycle register for channel %s +func (o *LEDC_Type) SetCH4_DUTY_DUTY_CH(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY.Reg, volatile.LoadUint32(&o.CH4_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_DUTY_CH() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH4_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH4_CONF1_DUTY_START_CH(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_START_CH() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH4_DUTY_R: Current duty cycle register for channel %s +func (o *LEDC_Type) SetCH4_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY_R.Reg, volatile.LoadUint32(&o.CH4_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH5_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH5_CONF0_TIMER_SEL_CH(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH5_CONF0_TIMER_SEL_CH() uint32 { + return volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH5_CONF0_SIG_OUT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH5_CONF0_SIG_OUT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH5_CONF0_IDLE_LV_CH(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH5_CONF0_IDLE_LV_CH() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH5_CONF0_PARA_UP_CH(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH5_CONF0_PARA_UP_CH() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH5_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH5_HPOINT_HPOINT_CH(value uint32) { + volatile.StoreUint32(&o.CH5_HPOINT.Reg, volatile.LoadUint32(&o.CH5_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH5_HPOINT_HPOINT_CH() uint32 { + return volatile.LoadUint32(&o.CH5_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH5_DUTY: Initial duty cycle register for channel %s +func (o *LEDC_Type) SetCH5_DUTY_DUTY_CH(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY.Reg, volatile.LoadUint32(&o.CH5_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_DUTY_CH() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH5_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH5_CONF1_DUTY_START_CH(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_START_CH() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH5_DUTY_R: Current duty cycle register for channel %s +func (o *LEDC_Type) SetCH5_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY_R.Reg, volatile.LoadUint32(&o.CH5_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH6_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH6_CONF0_TIMER_SEL_CH(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH6_CONF0_TIMER_SEL_CH() uint32 { + return volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH6_CONF0_SIG_OUT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH6_CONF0_SIG_OUT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH6_CONF0_IDLE_LV_CH(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH6_CONF0_IDLE_LV_CH() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH6_CONF0_PARA_UP_CH(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH6_CONF0_PARA_UP_CH() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH6_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH6_HPOINT_HPOINT_CH(value uint32) { + volatile.StoreUint32(&o.CH6_HPOINT.Reg, volatile.LoadUint32(&o.CH6_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH6_HPOINT_HPOINT_CH() uint32 { + return volatile.LoadUint32(&o.CH6_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH6_DUTY: Initial duty cycle register for channel %s +func (o *LEDC_Type) SetCH6_DUTY_DUTY_CH(value uint32) { + volatile.StoreUint32(&o.CH6_DUTY.Reg, volatile.LoadUint32(&o.CH6_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH6_DUTY_DUTY_CH() uint32 { + return volatile.LoadUint32(&o.CH6_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH6_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH6_CONF1_DUTY_START_CH(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_START_CH() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH6_DUTY_R: Current duty cycle register for channel %s +func (o *LEDC_Type) SetCH6_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH6_DUTY_R.Reg, volatile.LoadUint32(&o.CH6_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH6_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH6_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.CH7_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH7_CONF0_TIMER_SEL_CH(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH7_CONF0_TIMER_SEL_CH() uint32 { + return volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH7_CONF0_SIG_OUT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH7_CONF0_SIG_OUT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH7_CONF0_IDLE_LV_CH(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH7_CONF0_IDLE_LV_CH() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH7_CONF0_PARA_UP_CH(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH7_CONF0_PARA_UP_CH() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x10000) >> 16 +} + +// LEDC.CH7_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH7_HPOINT_HPOINT_CH(value uint32) { + volatile.StoreUint32(&o.CH7_HPOINT.Reg, volatile.LoadUint32(&o.CH7_HPOINT.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetCH7_HPOINT_HPOINT_CH() uint32 { + return volatile.LoadUint32(&o.CH7_HPOINT.Reg) & 0xfffff +} + +// LEDC.CH7_DUTY: Initial duty cycle register for channel %s +func (o *LEDC_Type) SetCH7_DUTY_DUTY_CH(value uint32) { + volatile.StoreUint32(&o.CH7_DUTY.Reg, volatile.LoadUint32(&o.CH7_DUTY.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH7_DUTY_DUTY_CH() uint32 { + return volatile.LoadUint32(&o.CH7_DUTY.Reg) & 0x1ffffff +} + +// LEDC.CH7_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH7_CONF1_DUTY_START_CH(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_START_CH() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH7_DUTY_R: Current duty cycle register for channel %s +func (o *LEDC_Type) SetCH7_DUTY_R_DUTY_CH_R(value uint32) { + volatile.StoreUint32(&o.CH7_DUTY_R.Reg, volatile.LoadUint32(&o.CH7_DUTY_R.Reg)&^(0x1ffffff)|value) +} +func (o *LEDC_Type) GetCH7_DUTY_R_DUTY_CH_R() uint32 { + return volatile.LoadUint32(&o.CH7_DUTY_R.Reg) & 0x1ffffff +} + +// LEDC.TIMER0_CONF: Timer %s configuration register +func (o *LEDC_Type) SetTIMER0_CONF_TIMER_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER0_CONF_TIMER_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER0_CONF_CLK_DIV_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER0_CONF_CLK_DIV_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER0_CONF_TIMER_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER0_CONF_TIMER_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER0_CONF_TIMER_RST(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER0_CONF_TIMER_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER0_CONF_TICK_SEL_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER0_CONF_TICK_SEL_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER0_CONF_TIMER_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER0_CONF_TIMER_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER0_VALUE: Timer %s current counter value register +func (o *LEDC_Type) SetTIMER0_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER0_VALUE.Reg, volatile.LoadUint32(&o.TIMER0_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER0_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER0_VALUE.Reg) & 0xfffff +} + +// LEDC.TIMER1_CONF: Timer %s configuration register +func (o *LEDC_Type) SetTIMER1_CONF_TIMER_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER1_CONF_TIMER_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER1_CONF_CLK_DIV_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER1_CONF_CLK_DIV_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER1_CONF_TIMER_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER1_CONF_TIMER_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER1_CONF_TIMER_RST(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER1_CONF_TIMER_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER1_CONF_TICK_SEL_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER1_CONF_TICK_SEL_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER1_CONF_TIMER_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER1_CONF_TIMER_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER1_VALUE: Timer %s current counter value register +func (o *LEDC_Type) SetTIMER1_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER1_VALUE.Reg, volatile.LoadUint32(&o.TIMER1_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER1_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER1_VALUE.Reg) & 0xfffff +} + +// LEDC.TIMER2_CONF: Timer %s configuration register +func (o *LEDC_Type) SetTIMER2_CONF_TIMER_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER2_CONF_TIMER_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER2_CONF_CLK_DIV_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER2_CONF_CLK_DIV_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER2_CONF_TIMER_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER2_CONF_TIMER_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER2_CONF_TIMER_RST(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER2_CONF_TIMER_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER2_CONF_TICK_SEL_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER2_CONF_TICK_SEL_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER2_CONF_TIMER_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER2_CONF_TIMER_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER2_VALUE: Timer %s current counter value register +func (o *LEDC_Type) SetTIMER2_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER2_VALUE.Reg, volatile.LoadUint32(&o.TIMER2_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER2_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER2_VALUE.Reg) & 0xfffff +} + +// LEDC.TIMER3_CONF: Timer %s configuration register +func (o *LEDC_Type) SetTIMER3_CONF_TIMER_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetTIMER3_CONF_TIMER_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetTIMER3_CONF_CLK_DIV_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x7fffe0)|value<<5) +} +func (o *LEDC_Type) GetTIMER3_CONF_CLK_DIV_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x7fffe0) >> 5 +} +func (o *LEDC_Type) SetTIMER3_CONF_TIMER_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER3_CONF_TIMER_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER3_CONF_TIMER_RST(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER3_CONF_TIMER_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER3_CONF_TICK_SEL_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER3_CONF_TICK_SEL_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetTIMER3_CONF_TIMER_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetTIMER3_CONF_TIMER_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x4000000) >> 26 +} + +// LEDC.TIMER3_VALUE: Timer %s current counter value register +func (o *LEDC_Type) SetTIMER3_VALUE_TIMER_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER3_VALUE.Reg, volatile.LoadUint32(&o.TIMER3_VALUE.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER3_VALUE_TIMER_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER3_VALUE.Reg) & 0xfffff +} + +// LEDC.INT_RAW: Interrupt raw status register +func (o *LEDC_Type) SetINT_RAW_TIMER0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_RAW_TIMER0_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_RAW_TIMER1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_RAW_TIMER2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_RAW_TIMER3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_RAW_TIMER3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// LEDC.INT_ST: Interrupt masked status register +func (o *LEDC_Type) SetINT_ST_TIMER0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ST_TIMER0_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ST_TIMER1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ST_TIMER1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ST_TIMER2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ST_TIMER2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ST_TIMER3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ST_TIMER3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH6_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH7_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH6_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH7_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// LEDC.INT_ENA: Interrupt enable register +func (o *LEDC_Type) SetINT_ENA_TIMER0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ENA_TIMER0_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ENA_TIMER1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ENA_TIMER2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ENA_TIMER3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ENA_TIMER3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// LEDC.INT_CLR: Interrupt clear register +func (o *LEDC_Type) SetINT_CLR_TIMER0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_CLR_TIMER0_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_CLR_TIMER1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_CLR_TIMER2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_CLR_TIMER3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_CLR_TIMER3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// LEDC.CH0_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH1_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH2_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH3_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH4_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH5_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH6_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH6_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH6_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH6_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH6_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH6_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH6_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH6_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH6_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH6_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.CH7_GAMMA_CONF: Ledc ch%s gamma config register. +func (o *LEDC_Type) SetCH7_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) { + volatile.StoreUint32(&o.CH7_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg)&^(0x1f)|value) +} +func (o *LEDC_Type) GetCH7_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 { + return volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg) & 0x1f +} +func (o *LEDC_Type) SetCH7_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) { + volatile.StoreUint32(&o.CH7_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCH7_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 { + return (volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCH7_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) { + volatile.StoreUint32(&o.CH7_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCH7_GAMMA_CONF_CH_GAMMA_RESUME() uint32 { + return (volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg) & 0x40) >> 6 +} + +// LEDC.EVT_TASK_EN0: Ledc event task enable bit register0. +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN() uint32 { + return volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH6_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH6_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH7_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH7_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH6_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH6_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH7_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH7_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME0_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME0_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME1_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME1_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME2_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME2_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME3_CMP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME3_CMP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4000000) >> 26 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8000000) >> 27 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10000000) >> 28 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20000000) >> 29 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH6_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH6_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH7_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH7_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x80000000) >> 31 +} + +// LEDC.EVT_TASK_EN1: Ledc event task enable bit register1. +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN() uint32 { + return volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_CAP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_CAP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH6_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH6_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH7_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH7_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH6_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH6_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH7_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH7_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2000000) >> 25 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4000000)|value<<26) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4000000) >> 26 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_RST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8000000)|value<<27) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_RST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8000000) >> 27 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10000000)|value<<28) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10000000) >> 28 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20000000)|value<<29) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20000000) >> 29 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80000000) >> 31 +} + +// LEDC.EVT_TASK_EN2: Ledc event task enable bit register2. +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN() uint32 { + return volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x1 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH6_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH6_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH7_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH7_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH6_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH6_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH7_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH7_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x80000) >> 19 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x100000)|value<<20) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x100000) >> 20 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x200000)|value<<21) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x200000) >> 21 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH6_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH6_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH7_EN(value uint32) { + volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH7_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x800000) >> 23 +} + +// LEDC.TIMER0_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER0_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CMP.Reg, volatile.LoadUint32(&o.TIMER0_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER0_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER0_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER1_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER1_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CMP.Reg, volatile.LoadUint32(&o.TIMER1_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER1_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER1_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER2_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER2_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CMP.Reg, volatile.LoadUint32(&o.TIMER2_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER2_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER2_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER3_CMP: Ledc timer%s compare value register. +func (o *LEDC_Type) SetTIMER3_CMP_TIMER_CMP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CMP.Reg, volatile.LoadUint32(&o.TIMER3_CMP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER3_CMP_TIMER_CMP() uint32 { + return volatile.LoadUint32(&o.TIMER3_CMP.Reg) & 0xfffff +} + +// LEDC.TIMER0_CNT_CAP: Ledc timer%s captured count value register. +func (o *LEDC_Type) SetTIMER0_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER0_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER0_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER0_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.TIMER1_CNT_CAP: Ledc timer%s captured count value register. +func (o *LEDC_Type) SetTIMER1_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER1_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER1_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER1_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.TIMER2_CNT_CAP: Ledc timer%s captured count value register. +func (o *LEDC_Type) SetTIMER2_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER2_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER2_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER2_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.TIMER3_CNT_CAP: Ledc timer%s captured count value register. +func (o *LEDC_Type) SetTIMER3_CNT_CAP_TIMER_CNT_CAP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER3_CNT_CAP.Reg)&^(0xfffff)|value) +} +func (o *LEDC_Type) GetTIMER3_CNT_CAP_TIMER_CNT_CAP() uint32 { + return volatile.LoadUint32(&o.TIMER3_CNT_CAP.Reg) & 0xfffff +} + +// LEDC.CONF: LEDC global configuration register +func (o *LEDC_Type) SetCONF_APB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCONF_APB_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x3 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH0(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH1(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH1() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH2(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH2() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH3(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH3() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH4(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH5(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH5() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH6(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH6() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH7(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH7() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// LEDC.DATE: Version control register +func (o *LEDC_Type) SetDATE_LEDC_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LEDC_Type) GetDATE_LEDC_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power Interrupt Controller +type LPINTR_Type struct { + SW_INT_RAW volatile.Register32 // 0x0 + SW_INT_ST volatile.Register32 // 0x4 + SW_INT_ENA volatile.Register32 // 0x8 + SW_INT_CLR volatile.Register32 // 0xC + STATUS volatile.Register32 // 0x10 + _ [1000]byte + DATE volatile.Register32 // 0x3FC +} + +// LPINTR.SW_INT_RAW: need_des +func (o *LPINTR_Type) SetSW_INT_RAW_LP_SW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SW_INT_RAW.Reg, volatile.LoadUint32(&o.SW_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LPINTR_Type) GetSW_INT_RAW_LP_SW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SW_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LPINTR.SW_INT_ST: need_des +func (o *LPINTR_Type) SetSW_INT_ST_LP_SW_INT_ST(value uint32) { + volatile.StoreUint32(&o.SW_INT_ST.Reg, volatile.LoadUint32(&o.SW_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LPINTR_Type) GetSW_INT_ST_LP_SW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SW_INT_ST.Reg) & 0x80000000) >> 31 +} + +// LPINTR.SW_INT_ENA: need_des +func (o *LPINTR_Type) SetSW_INT_ENA_LP_SW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SW_INT_ENA.Reg, volatile.LoadUint32(&o.SW_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LPINTR_Type) GetSW_INT_ENA_LP_SW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SW_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LPINTR.SW_INT_CLR: need_des +func (o *LPINTR_Type) SetSW_INT_CLR_LP_SW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SW_INT_CLR.Reg, volatile.LoadUint32(&o.SW_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LPINTR_Type) GetSW_INT_CLR_LP_SW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SW_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LPINTR.STATUS: need_des +func (o *LPINTR_Type) SetSTATUS_LP_HUK_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400)|value<<10) +} +func (o *LPINTR_Type) GetSTATUS_LP_HUK_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400) >> 10 +} +func (o *LPINTR_Type) SetSTATUS_SYSREG_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x800)|value<<11) +} +func (o *LPINTR_Type) GetSTATUS_SYSREG_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x800) >> 11 +} +func (o *LPINTR_Type) SetSTATUS_LP_SW_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *LPINTR_Type) GetSTATUS_LP_SW_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1000) >> 12 +} +func (o *LPINTR_Type) SetSTATUS_LP_EFUSE_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *LPINTR_Type) GetSTATUS_LP_EFUSE_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *LPINTR_Type) SetSTATUS_LP_UART_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *LPINTR_Type) GetSTATUS_LP_UART_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *LPINTR_Type) SetSTATUS_LP_TSENS_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *LPINTR_Type) GetSTATUS_LP_TSENS_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *LPINTR_Type) SetSTATUS_LP_TOUCH_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *LPINTR_Type) GetSTATUS_LP_TOUCH_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10000) >> 16 +} +func (o *LPINTR_Type) SetSTATUS_LP_SPI_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *LPINTR_Type) GetSTATUS_LP_SPI_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000) >> 17 +} +func (o *LPINTR_Type) SetSTATUS_LP_I2S_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000)|value<<18) +} +func (o *LPINTR_Type) GetSTATUS_LP_I2S_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000) >> 18 +} +func (o *LPINTR_Type) SetSTATUS_LP_I2C_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000)|value<<19) +} +func (o *LPINTR_Type) GetSTATUS_LP_I2C_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000) >> 19 +} +func (o *LPINTR_Type) SetSTATUS_LP_GPIO_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100000)|value<<20) +} +func (o *LPINTR_Type) GetSTATUS_LP_GPIO_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100000) >> 20 +} +func (o *LPINTR_Type) SetSTATUS_LP_ADC_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200000)|value<<21) +} +func (o *LPINTR_Type) GetSTATUS_LP_ADC_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200000) >> 21 +} +func (o *LPINTR_Type) SetSTATUS_ANAPERI_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400000)|value<<22) +} +func (o *LPINTR_Type) GetSTATUS_ANAPERI_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400000) >> 22 +} +func (o *LPINTR_Type) SetSTATUS_PMU_REG_1_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *LPINTR_Type) GetSTATUS_PMU_REG_1_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x800000) >> 23 +} +func (o *LPINTR_Type) SetSTATUS_PMU_REG_0_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1000000)|value<<24) +} +func (o *LPINTR_Type) GetSTATUS_PMU_REG_0_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1000000) >> 24 +} +func (o *LPINTR_Type) SetSTATUS_MB_LP_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *LPINTR_Type) GetSTATUS_MB_LP_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000000) >> 25 +} +func (o *LPINTR_Type) SetSTATUS_MB_HP_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *LPINTR_Type) GetSTATUS_MB_HP_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000000) >> 26 +} +func (o *LPINTR_Type) SetSTATUS_LP_TIMER_REG_1_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *LPINTR_Type) GetSTATUS_LP_TIMER_REG_1_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000000) >> 27 +} +func (o *LPINTR_Type) SetSTATUS_LP_TIMER_REG_0_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10000000)|value<<28) +} +func (o *LPINTR_Type) GetSTATUS_LP_TIMER_REG_0_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10000000) >> 28 +} +func (o *LPINTR_Type) SetSTATUS_LP_WDT_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *LPINTR_Type) GetSTATUS_LP_WDT_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *LPINTR_Type) SetSTATUS_LP_RTC_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *LPINTR_Type) GetSTATUS_LP_RTC_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *LPINTR_Type) SetSTATUS_HP_INTR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *LPINTR_Type) GetSTATUS_HP_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// LPINTR.DATE: need_des +func (o *LPINTR_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LPINTR_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_PERI Peripheral +type LPPERI_Type struct { + CLK_EN volatile.Register32 // 0x0 + CORE_CLK_SEL volatile.Register32 // 0x4 + RESET_EN volatile.Register32 // 0x8 + CPU volatile.Register32 // 0xC + _ [24]byte + MEM_CTRL volatile.Register32 // 0x28 + ADC_CTRL volatile.Register32 // 0x2C + LP_I2S_RXCLK_DIV_NUM volatile.Register32 // 0x30 + LP_I2S_RXCLK_DIV_XYZ volatile.Register32 // 0x34 + LP_I2S_TXCLK_DIV_NUM volatile.Register32 // 0x38 + LP_I2S_TXCLK_DIV_XYZ volatile.Register32 // 0x3C + _ [956]byte + DATE volatile.Register32 // 0x3FC +} + +// LPPERI.CLK_EN: need_des +func (o *LPPERI_Type) SetCLK_EN_CK_EN_RNG(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10000)|value<<16) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_RNG() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10000) >> 16 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_TSENS(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20000)|value<<17) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_TSENS() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20000) >> 17 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_PMS(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40000)|value<<18) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_PMS() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40000) >> 18 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_EFUSE(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x80000)|value<<19) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_EFUSE() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x80000) >> 19 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_IOMUX(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x100000)|value<<20) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_IOMUX() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x100000) >> 20 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_TOUCH(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x200000)|value<<21) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_TOUCH() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x200000) >> 21 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_SPI(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x400000)|value<<22) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_SPI() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x400000) >> 22 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_ADC(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x800000)|value<<23) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_ADC() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x800000) >> 23 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2S_TX(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2S_TX() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1000000) >> 24 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2S_RX(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2S_RX() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x2000000) >> 25 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2S(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2S() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x4000000) >> 26 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2CMST(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2CMST() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x8000000) >> 27 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2C(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2C() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10000000) >> 28 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_UART(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_UART() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_INTR(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_INTR() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x80000000) >> 31 +} + +// LPPERI.CORE_CLK_SEL: need_des +func (o *LPPERI_Type) SetCORE_CLK_SEL_LP_I2S_TX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0x3000000)|value<<24) +} +func (o *LPPERI_Type) GetCORE_CLK_SEL_LP_I2S_TX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0x3000000) >> 24 +} +func (o *LPPERI_Type) SetCORE_CLK_SEL_LP_I2S_RX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0xc000000)|value<<26) +} +func (o *LPPERI_Type) GetCORE_CLK_SEL_LP_I2S_RX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0xc000000) >> 26 +} +func (o *LPPERI_Type) SetCORE_CLK_SEL_LP_I2C_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0x30000000)|value<<28) +} +func (o *LPPERI_Type) GetCORE_CLK_SEL_LP_I2C_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0x30000000) >> 28 +} +func (o *LPPERI_Type) SetCORE_CLK_SEL_LP_UART_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0xc0000000)|value<<30) +} +func (o *LPPERI_Type) GetCORE_CLK_SEL_LP_UART_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0xc0000000) >> 30 +} + +// LPPERI.RESET_EN: need_des +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_TSENS(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x40000)|value<<18) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_TSENS() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x40000) >> 18 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_PMS(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x80000)|value<<19) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_PMS() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x80000) >> 19 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_EFUSE(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x100000)|value<<20) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_EFUSE() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x100000) >> 20 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_IOMUX(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x200000)|value<<21) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_IOMUX() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x200000) >> 21 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_TOUCH(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x400000)|value<<22) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_TOUCH() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x400000) >> 22 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_SPI(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x800000)|value<<23) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_SPI() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x800000) >> 23 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_ADC(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_ADC() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x1000000) >> 24 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_I2S(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_I2S() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x2000000) >> 25 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_I2CMST(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_I2CMST() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x4000000) >> 26 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_I2C(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_I2C() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x8000000) >> 27 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_UART(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_UART() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x10000000) >> 28 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_INTR(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_INTR() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_ROM(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_ROM() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_CORE(value uint32) { + volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_CORE() uint32 { + return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x80000000) >> 31 +} + +// LPPERI.CPU: need_des +func (o *LPPERI_Type) SetCPU_LPCORE_DBGM_UNAVAILABLE(value uint32) { + volatile.StoreUint32(&o.CPU.Reg, volatile.LoadUint32(&o.CPU.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetCPU_LPCORE_DBGM_UNAVAILABLE() uint32 { + return (volatile.LoadUint32(&o.CPU.Reg) & 0x80000000) >> 31 +} + +// LPPERI.MEM_CTRL: need_des +func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_WAKEUP_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x1)|value) +} +func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_WAKEUP_FLAG_CLR() uint32 { + return volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x1 +} +func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_WAKEUP_FLAG(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_WAKEUP_FLAG() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x2) >> 1 +} +func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x80000000) >> 31 +} + +// LPPERI.ADC_CTRL: need_des +func (o *LPPERI_Type) SetADC_CTRL_SAR2_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *LPPERI_Type) GetADC_CTRL_SAR2_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0x40) >> 6 +} +func (o *LPPERI_Type) SetADC_CTRL_SAR1_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *LPPERI_Type) GetADC_CTRL_SAR1_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0x80) >> 7 +} +func (o *LPPERI_Type) SetADC_CTRL_LPADC_FUNC_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *LPPERI_Type) GetADC_CTRL_LPADC_FUNC_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0xff00) >> 8 +} +func (o *LPPERI_Type) SetADC_CTRL_LPADC_SAR2_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *LPPERI_Type) GetADC_CTRL_LPADC_SAR2_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *LPPERI_Type) SetADC_CTRL_LPADC_SAR1_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0xff000000)|value<<24) +} +func (o *LPPERI_Type) GetADC_CTRL_LPADC_SAR1_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0xff000000) >> 24 +} + +// LPPERI.LP_I2S_RXCLK_DIV_NUM: need_des +func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_NUM_LP_I2S_RX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_NUM.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_NUM.Reg)&^(0xff000000)|value<<24) +} +func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_NUM_LP_I2S_RX_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_NUM.Reg) & 0xff000000) >> 24 +} + +// LPPERI.LP_I2S_RXCLK_DIV_XYZ: need_des +func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg)&^(0x10)|value<<4) +} +func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg) & 0x10) >> 4 +} +func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg)&^(0x3fe0)|value<<5) +} +func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Z() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg) & 0x3fe0) >> 5 +} +func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg)&^(0x7fc000)|value<<14) +} +func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg) & 0x7fc000) >> 14 +} +func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg)&^(0xff800000)|value<<23) +} +func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg) & 0xff800000) >> 23 +} + +// LPPERI.LP_I2S_TXCLK_DIV_NUM: need_des +func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_NUM_LP_I2S_TX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_NUM.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_NUM.Reg)&^(0xff000000)|value<<24) +} +func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_NUM_LP_I2S_TX_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_NUM.Reg) & 0xff000000) >> 24 +} + +// LPPERI.LP_I2S_TXCLK_DIV_XYZ: need_des +func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg)&^(0x10)|value<<4) +} +func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg) & 0x10) >> 4 +} +func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg)&^(0x3fe0)|value<<5) +} +func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Z() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg) & 0x3fe0) >> 5 +} +func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg)&^(0x7fc000)|value<<14) +} +func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg) & 0x7fc000) >> 14 +} +func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg)&^(0xff800000)|value<<23) +} +func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg) & 0xff800000) >> 23 +} + +// LPPERI.DATE: need_des +func (o *LPPERI_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LPPERI_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_SYS Peripheral +type LPSYSREG_Type struct { + LP_SYS_VER_DATE volatile.Register32 // 0x0 + CLK_SEL_CTRL volatile.Register32 // 0x4 + SYS_CTRL volatile.Register32 // 0x8 + LP_CLK_CTRL volatile.Register32 // 0xC + LP_RST_CTRL volatile.Register32 // 0x10 + _ [4]byte + LP_CORE_BOOT_ADDR volatile.Register32 // 0x18 + EXT_WAKEUP1 volatile.Register32 // 0x1C + EXT_WAKEUP1_STATUS volatile.Register32 // 0x20 + LP_TCM_PWR_CTRL volatile.Register32 // 0x24 + BOOT_ADDR_HP_LP volatile.Register32 // 0x28 + LP_STORE0 volatile.Register32 // 0x2C + LP_STORE1 volatile.Register32 // 0x30 + LP_STORE2 volatile.Register32 // 0x34 + LP_STORE3 volatile.Register32 // 0x38 + LP_STORE4 volatile.Register32 // 0x3C + LP_STORE5 volatile.Register32 // 0x40 + LP_STORE6 volatile.Register32 // 0x44 + LP_STORE7 volatile.Register32 // 0x48 + LP_STORE8 volatile.Register32 // 0x4C + LP_STORE9 volatile.Register32 // 0x50 + LP_STORE10 volatile.Register32 // 0x54 + LP_STORE11 volatile.Register32 // 0x58 + LP_STORE12 volatile.Register32 // 0x5C + LP_STORE13 volatile.Register32 // 0x60 + LP_STORE14 volatile.Register32 // 0x64 + LP_STORE15 volatile.Register32 // 0x68 + LP_PROBEA_CTRL volatile.Register32 // 0x6C + LP_PROBEB_CTRL volatile.Register32 // 0x70 + LP_PROBE_OUT volatile.Register32 // 0x74 + _ [36]byte + F2S_APB_BRG_CNTL volatile.Register32 // 0x9C + _ [96]byte + USB_CTRL volatile.Register32 // 0x100 + _ [8]byte + ANA_XPD_PAD_GROUP volatile.Register32 // 0x10C + LP_TCM_RAM_RDN_ECO_CS volatile.Register32 // 0x110 + LP_TCM_RAM_RDN_ECO_LOW volatile.Register32 // 0x114 + LP_TCM_RAM_RDN_ECO_HIGH volatile.Register32 // 0x118 + LP_TCM_ROM_RDN_ECO_CS volatile.Register32 // 0x11C + LP_TCM_ROM_RDN_ECO_LOW volatile.Register32 // 0x120 + LP_TCM_ROM_RDN_ECO_HIGH volatile.Register32 // 0x124 + _ [8]byte + HP_ROOT_CLK_CTRL volatile.Register32 // 0x130 + _ [4]byte + LP_PMU_RDN_ECO_LOW volatile.Register32 // 0x138 + LP_PMU_RDN_ECO_HIGH volatile.Register32 // 0x13C + _ [8]byte + PAD_COMP0 volatile.Register32 // 0x148 + PAD_COMP1 volatile.Register32 // 0x14C + _ [4]byte + BACKUP_DMA_CFG0 volatile.Register32 // 0x154 + BACKUP_DMA_CFG1 volatile.Register32 // 0x158 + BACKUP_DMA_CFG2 volatile.Register32 // 0x15C + _ [4]byte + BOOT_ADDR_HP_CORE1 volatile.Register32 // 0x164 + LP_ADDRHOLE_ADDR volatile.Register32 // 0x168 + LP_ADDRHOLE_INFO volatile.Register32 // 0x16C + INT_RAW volatile.Register32 // 0x170 + INT_ST volatile.Register32 // 0x174 + INT_ENA volatile.Register32 // 0x178 + INT_CLR volatile.Register32 // 0x17C + HP_MEM_AUX_CTRL volatile.Register32 // 0x180 + LP_MEM_AUX_CTRL volatile.Register32 // 0x184 + HP_ROM_AUX_CTRL volatile.Register32 // 0x188 + LP_ROM_AUX_CTRL volatile.Register32 // 0x18C + LP_CPU_DBG_PC volatile.Register32 // 0x190 + LP_CPU_EXC_PC volatile.Register32 // 0x194 + IDBUS_ADDRHOLE_ADDR volatile.Register32 // 0x198 + IDBUS_ADDRHOLE_INFO volatile.Register32 // 0x19C + HP_POR_RST_BYPASS_CTRL volatile.Register32 // 0x1A0 + RNG_DATA volatile.Register32 // 0x1A4 + _ [8]byte + LP_CORE_AHB_TIMEOUT volatile.Register32 // 0x1B0 + LP_CORE_IBUS_TIMEOUT volatile.Register32 // 0x1B4 + LP_CORE_DBUS_TIMEOUT volatile.Register32 // 0x1B8 + LP_CORE_ERR_RESP_DIS volatile.Register32 // 0x1BC + RNG_CFG volatile.Register32 // 0x1C0 +} + +// LPSYSREG.LP_SYS_VER_DATE: need_des +func (o *LPSYSREG_Type) SetLP_SYS_VER_DATE(value uint32) { + volatile.StoreUint32(&o.LP_SYS_VER_DATE.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_SYS_VER_DATE() uint32 { + return volatile.LoadUint32(&o.LP_SYS_VER_DATE.Reg) +} + +// LPSYSREG.CLK_SEL_CTRL: need_des +func (o *LPSYSREG_Type) SetCLK_SEL_CTRL_ENA_SW_SEL_SYS_CLK(value uint32) { + volatile.StoreUint32(&o.CLK_SEL_CTRL.Reg, volatile.LoadUint32(&o.CLK_SEL_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *LPSYSREG_Type) GetCLK_SEL_CTRL_ENA_SW_SEL_SYS_CLK() uint32 { + return (volatile.LoadUint32(&o.CLK_SEL_CTRL.Reg) & 0x10000) >> 16 +} +func (o *LPSYSREG_Type) SetCLK_SEL_CTRL_SW_SYS_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_SEL_CTRL.Reg, volatile.LoadUint32(&o.CLK_SEL_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *LPSYSREG_Type) GetCLK_SEL_CTRL_SW_SYS_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_SEL_CTRL.Reg) & 0x20000) >> 17 +} + +// LPSYSREG.SYS_CTRL: need_des +func (o *LPSYSREG_Type) SetSYS_CTRL_LP_CORE_DISABLE(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_LP_CORE_DISABLE() uint32 { + return volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetSYS_CTRL_SYS_SW_RST(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_SYS_SW_RST() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x2) >> 1 +} +func (o *LPSYSREG_Type) SetSYS_CTRL_FORCE_DOWNLOAD_BOOT(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_FORCE_DOWNLOAD_BOOT() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x4) >> 2 +} +func (o *LPSYSREG_Type) SetSYS_CTRL_DIG_FIB(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x7f8)|value<<3) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_DIG_FIB() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x7f8) >> 3 +} +func (o *LPSYSREG_Type) SetSYS_CTRL_IO_MUX_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_IO_MUX_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x800) >> 11 +} +func (o *LPSYSREG_Type) SetSYS_CTRL_ANA_FIB(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x1fc000)|value<<14) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_ANA_FIB() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x1fc000) >> 14 +} +func (o *LPSYSREG_Type) SetSYS_CTRL_LP_FIB_SEL(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x1fe00000)|value<<21) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_LP_FIB_SEL() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x1fe00000) >> 21 +} +func (o *LPSYSREG_Type) SetSYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *LPSYSREG_Type) SetSYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *LPSYSREG_Type) SetSYS_CTRL_SYSTIMER_STALL_SEL(value uint32) { + volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *LPSYSREG_Type) GetSYS_CTRL_SYSTIMER_STALL_SEL() uint32 { + return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x80000000) >> 31 +} + +// LPSYSREG.LP_CLK_CTRL: need_des +func (o *LPSYSREG_Type) SetLP_CLK_CTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_CLK_CTRL.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetLP_CLK_CTRL_CLK_EN() uint32 { + return volatile.LoadUint32(&o.LP_CLK_CTRL.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetLP_CLK_CTRL_LP_FOSC_HP_CKEN(value uint32) { + volatile.StoreUint32(&o.LP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_CLK_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *LPSYSREG_Type) GetLP_CLK_CTRL_LP_FOSC_HP_CKEN() uint32 { + return (volatile.LoadUint32(&o.LP_CLK_CTRL.Reg) & 0x4000) >> 14 +} + +// LPSYSREG.LP_RST_CTRL: need_des +func (o *LPSYSREG_Type) SetLP_RST_CTRL_ANA_RST_BYPASS(value uint32) { + volatile.StoreUint32(&o.LP_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_RST_CTRL.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetLP_RST_CTRL_ANA_RST_BYPASS() uint32 { + return volatile.LoadUint32(&o.LP_RST_CTRL.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetLP_RST_CTRL_SYS_RST_BYPASS(value uint32) { + volatile.StoreUint32(&o.LP_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_RST_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetLP_RST_CTRL_SYS_RST_BYPASS() uint32 { + return (volatile.LoadUint32(&o.LP_RST_CTRL.Reg) & 0x2) >> 1 +} +func (o *LPSYSREG_Type) SetLP_RST_CTRL_EFUSE_FORCE_NORST(value uint32) { + volatile.StoreUint32(&o.LP_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_RST_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *LPSYSREG_Type) GetLP_RST_CTRL_EFUSE_FORCE_NORST() uint32 { + return (volatile.LoadUint32(&o.LP_RST_CTRL.Reg) & 0x4) >> 2 +} + +// LPSYSREG.LP_CORE_BOOT_ADDR: need_des +func (o *LPSYSREG_Type) SetLP_CORE_BOOT_ADDR(value uint32) { + volatile.StoreUint32(&o.LP_CORE_BOOT_ADDR.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_CORE_BOOT_ADDR() uint32 { + return volatile.LoadUint32(&o.LP_CORE_BOOT_ADDR.Reg) +} + +// LPSYSREG.EXT_WAKEUP1: need_des +func (o *LPSYSREG_Type) SetEXT_WAKEUP1_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0xffff)|value) +} +func (o *LPSYSREG_Type) GetEXT_WAKEUP1_SEL() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0xffff +} +func (o *LPSYSREG_Type) SetEXT_WAKEUP1_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0x10000)|value<<16) +} +func (o *LPSYSREG_Type) GetEXT_WAKEUP1_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0x10000) >> 16 +} + +// LPSYSREG.EXT_WAKEUP1_STATUS: need_des +func (o *LPSYSREG_Type) SetEXT_WAKEUP1_STATUS(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1_STATUS.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg)&^(0xffff)|value) +} +func (o *LPSYSREG_Type) GetEXT_WAKEUP1_STATUS() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg) & 0xffff +} + +// LPSYSREG.LP_TCM_PWR_CTRL: need_des +func (o *LPSYSREG_Type) SetLP_TCM_PWR_CTRL_LP_TCM_ROM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LP_TCM_PWR_CTRL.Reg, volatile.LoadUint32(&o.LP_TCM_PWR_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *LPSYSREG_Type) GetLP_TCM_PWR_CTRL_LP_TCM_ROM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LP_TCM_PWR_CTRL.Reg) & 0x20) >> 5 +} +func (o *LPSYSREG_Type) SetLP_TCM_PWR_CTRL_LP_TCM_RAM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LP_TCM_PWR_CTRL.Reg, volatile.LoadUint32(&o.LP_TCM_PWR_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *LPSYSREG_Type) GetLP_TCM_PWR_CTRL_LP_TCM_RAM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LP_TCM_PWR_CTRL.Reg) & 0x80) >> 7 +} + +// LPSYSREG.BOOT_ADDR_HP_LP: need_des +func (o *LPSYSREG_Type) SetBOOT_ADDR_HP_LP(value uint32) { + volatile.StoreUint32(&o.BOOT_ADDR_HP_LP.Reg, value) +} +func (o *LPSYSREG_Type) GetBOOT_ADDR_HP_LP() uint32 { + return volatile.LoadUint32(&o.BOOT_ADDR_HP_LP.Reg) +} + +// LPSYSREG.LP_STORE0: need_des +func (o *LPSYSREG_Type) SetLP_STORE0(value uint32) { + volatile.StoreUint32(&o.LP_STORE0.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE0() uint32 { + return volatile.LoadUint32(&o.LP_STORE0.Reg) +} + +// LPSYSREG.LP_STORE1: need_des +func (o *LPSYSREG_Type) SetLP_STORE1(value uint32) { + volatile.StoreUint32(&o.LP_STORE1.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE1() uint32 { + return volatile.LoadUint32(&o.LP_STORE1.Reg) +} + +// LPSYSREG.LP_STORE2: need_des +func (o *LPSYSREG_Type) SetLP_STORE2(value uint32) { + volatile.StoreUint32(&o.LP_STORE2.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE2() uint32 { + return volatile.LoadUint32(&o.LP_STORE2.Reg) +} + +// LPSYSREG.LP_STORE3: need_des +func (o *LPSYSREG_Type) SetLP_STORE3(value uint32) { + volatile.StoreUint32(&o.LP_STORE3.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE3() uint32 { + return volatile.LoadUint32(&o.LP_STORE3.Reg) +} + +// LPSYSREG.LP_STORE4: need_des +func (o *LPSYSREG_Type) SetLP_STORE4(value uint32) { + volatile.StoreUint32(&o.LP_STORE4.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE4() uint32 { + return volatile.LoadUint32(&o.LP_STORE4.Reg) +} + +// LPSYSREG.LP_STORE5: need_des +func (o *LPSYSREG_Type) SetLP_STORE5(value uint32) { + volatile.StoreUint32(&o.LP_STORE5.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE5() uint32 { + return volatile.LoadUint32(&o.LP_STORE5.Reg) +} + +// LPSYSREG.LP_STORE6: need_des +func (o *LPSYSREG_Type) SetLP_STORE6(value uint32) { + volatile.StoreUint32(&o.LP_STORE6.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE6() uint32 { + return volatile.LoadUint32(&o.LP_STORE6.Reg) +} + +// LPSYSREG.LP_STORE7: need_des +func (o *LPSYSREG_Type) SetLP_STORE7(value uint32) { + volatile.StoreUint32(&o.LP_STORE7.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE7() uint32 { + return volatile.LoadUint32(&o.LP_STORE7.Reg) +} + +// LPSYSREG.LP_STORE8: need_des +func (o *LPSYSREG_Type) SetLP_STORE8(value uint32) { + volatile.StoreUint32(&o.LP_STORE8.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE8() uint32 { + return volatile.LoadUint32(&o.LP_STORE8.Reg) +} + +// LPSYSREG.LP_STORE9: need_des +func (o *LPSYSREG_Type) SetLP_STORE9(value uint32) { + volatile.StoreUint32(&o.LP_STORE9.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE9() uint32 { + return volatile.LoadUint32(&o.LP_STORE9.Reg) +} + +// LPSYSREG.LP_STORE10: need_des +func (o *LPSYSREG_Type) SetLP_STORE10(value uint32) { + volatile.StoreUint32(&o.LP_STORE10.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE10() uint32 { + return volatile.LoadUint32(&o.LP_STORE10.Reg) +} + +// LPSYSREG.LP_STORE11: need_des +func (o *LPSYSREG_Type) SetLP_STORE11(value uint32) { + volatile.StoreUint32(&o.LP_STORE11.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE11() uint32 { + return volatile.LoadUint32(&o.LP_STORE11.Reg) +} + +// LPSYSREG.LP_STORE12: need_des +func (o *LPSYSREG_Type) SetLP_STORE12(value uint32) { + volatile.StoreUint32(&o.LP_STORE12.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE12() uint32 { + return volatile.LoadUint32(&o.LP_STORE12.Reg) +} + +// LPSYSREG.LP_STORE13: need_des +func (o *LPSYSREG_Type) SetLP_STORE13(value uint32) { + volatile.StoreUint32(&o.LP_STORE13.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE13() uint32 { + return volatile.LoadUint32(&o.LP_STORE13.Reg) +} + +// LPSYSREG.LP_STORE14: need_des +func (o *LPSYSREG_Type) SetLP_STORE14(value uint32) { + volatile.StoreUint32(&o.LP_STORE14.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE14() uint32 { + return volatile.LoadUint32(&o.LP_STORE14.Reg) +} + +// LPSYSREG.LP_STORE15: need_des +func (o *LPSYSREG_Type) SetLP_STORE15(value uint32) { + volatile.StoreUint32(&o.LP_STORE15.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_STORE15() uint32 { + return volatile.LoadUint32(&o.LP_STORE15.Reg) +} + +// LPSYSREG.LP_PROBEA_CTRL: need_des +func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_A_MOD_SEL(value uint32) { + volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0xffff)|value) +} +func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_A_MOD_SEL() uint32 { + return volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0xffff +} +func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_A_TOP_SEL(value uint32) { + volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_A_TOP_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_L_SEL(value uint32) { + volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0x3000000)|value<<24) +} +func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_L_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0x3000000) >> 24 +} +func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_H_SEL(value uint32) { + volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0xc000000)|value<<26) +} +func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_H_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0xc000000) >> 26 +} +func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_GLOBAL_EN(value uint32) { + volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_GLOBAL_EN() uint32 { + return (volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0x10000000) >> 28 +} + +// LPSYSREG.LP_PROBEB_CTRL: need_des +func (o *LPSYSREG_Type) SetLP_PROBEB_CTRL_PROBE_B_MOD_SEL(value uint32) { + volatile.StoreUint32(&o.LP_PROBEB_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg)&^(0xffff)|value) +} +func (o *LPSYSREG_Type) GetLP_PROBEB_CTRL_PROBE_B_MOD_SEL() uint32 { + return volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg) & 0xffff +} +func (o *LPSYSREG_Type) SetLP_PROBEB_CTRL_PROBE_B_TOP_SEL(value uint32) { + volatile.StoreUint32(&o.LP_PROBEB_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *LPSYSREG_Type) GetLP_PROBEB_CTRL_PROBE_B_TOP_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *LPSYSREG_Type) SetLP_PROBEB_CTRL_PROBE_B_EN(value uint32) { + volatile.StoreUint32(&o.LP_PROBEB_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *LPSYSREG_Type) GetLP_PROBEB_CTRL_PROBE_B_EN() uint32 { + return (volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg) & 0x1000000) >> 24 +} + +// LPSYSREG.LP_PROBE_OUT: need_des +func (o *LPSYSREG_Type) SetLP_PROBE_OUT(value uint32) { + volatile.StoreUint32(&o.LP_PROBE_OUT.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_PROBE_OUT() uint32 { + return volatile.LoadUint32(&o.LP_PROBE_OUT.Reg) +} + +// LPSYSREG.F2S_APB_BRG_CNTL: need_des +func (o *LPSYSREG_Type) SetF2S_APB_BRG_CNTL_F2S_APB_POSTW_EN(value uint32) { + volatile.StoreUint32(&o.F2S_APB_BRG_CNTL.Reg, volatile.LoadUint32(&o.F2S_APB_BRG_CNTL.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetF2S_APB_BRG_CNTL_F2S_APB_POSTW_EN() uint32 { + return volatile.LoadUint32(&o.F2S_APB_BRG_CNTL.Reg) & 0x1 +} + +// LPSYSREG.USB_CTRL: need_des +func (o *LPSYSREG_Type) SetUSB_CTRL_SW_HW_USB_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.USB_CTRL.Reg, volatile.LoadUint32(&o.USB_CTRL.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetUSB_CTRL_SW_HW_USB_PHY_SEL() uint32 { + return volatile.LoadUint32(&o.USB_CTRL.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetUSB_CTRL_SW_USB_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.USB_CTRL.Reg, volatile.LoadUint32(&o.USB_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetUSB_CTRL_SW_USB_PHY_SEL() uint32 { + return (volatile.LoadUint32(&o.USB_CTRL.Reg) & 0x2) >> 1 +} +func (o *LPSYSREG_Type) SetUSB_CTRL_USBOTG20_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.USB_CTRL.Reg, volatile.LoadUint32(&o.USB_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *LPSYSREG_Type) GetUSB_CTRL_USBOTG20_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.USB_CTRL.Reg) & 0x4) >> 2 +} +func (o *LPSYSREG_Type) SetUSB_CTRL_USBOTG20_IN_SUSPEND(value uint32) { + volatile.StoreUint32(&o.USB_CTRL.Reg, volatile.LoadUint32(&o.USB_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *LPSYSREG_Type) GetUSB_CTRL_USBOTG20_IN_SUSPEND() uint32 { + return (volatile.LoadUint32(&o.USB_CTRL.Reg) & 0x8) >> 3 +} + +// LPSYSREG.ANA_XPD_PAD_GROUP: need_des +func (o *LPSYSREG_Type) SetANA_XPD_PAD_GROUP_ANA_REG_XPD_PAD_GROUP(value uint32) { + volatile.StoreUint32(&o.ANA_XPD_PAD_GROUP.Reg, volatile.LoadUint32(&o.ANA_XPD_PAD_GROUP.Reg)&^(0xff)|value) +} +func (o *LPSYSREG_Type) GetANA_XPD_PAD_GROUP_ANA_REG_XPD_PAD_GROUP() uint32 { + return volatile.LoadUint32(&o.ANA_XPD_PAD_GROUP.Reg) & 0xff +} + +// LPSYSREG.LP_TCM_RAM_RDN_ECO_CS: need_des +func (o *LPSYSREG_Type) SetLP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_EN(value uint32) { + volatile.StoreUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetLP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_EN() uint32 { + return volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetLP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetLP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg) & 0x2) >> 1 +} + +// LPSYSREG.LP_TCM_RAM_RDN_ECO_LOW: need_des +func (o *LPSYSREG_Type) SetLP_TCM_RAM_RDN_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.LP_TCM_RAM_RDN_ECO_LOW.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_TCM_RAM_RDN_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_LOW.Reg) +} + +// LPSYSREG.LP_TCM_RAM_RDN_ECO_HIGH: need_des +func (o *LPSYSREG_Type) SetLP_TCM_RAM_RDN_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.LP_TCM_RAM_RDN_ECO_HIGH.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_TCM_RAM_RDN_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_HIGH.Reg) +} + +// LPSYSREG.LP_TCM_ROM_RDN_ECO_CS: need_des +func (o *LPSYSREG_Type) SetLP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_EN(value uint32) { + volatile.StoreUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetLP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_EN() uint32 { + return volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetLP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetLP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg) & 0x2) >> 1 +} + +// LPSYSREG.LP_TCM_ROM_RDN_ECO_LOW: need_des +func (o *LPSYSREG_Type) SetLP_TCM_ROM_RDN_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.LP_TCM_ROM_RDN_ECO_LOW.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_TCM_ROM_RDN_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_LOW.Reg) +} + +// LPSYSREG.LP_TCM_ROM_RDN_ECO_HIGH: need_des +func (o *LPSYSREG_Type) SetLP_TCM_ROM_RDN_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.LP_TCM_ROM_RDN_ECO_HIGH.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_TCM_ROM_RDN_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_HIGH.Reg) +} + +// LPSYSREG.HP_ROOT_CLK_CTRL: need_des +func (o *LPSYSREG_Type) SetHP_ROOT_CLK_CTRL_CPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.HP_ROOT_CLK_CTRL.Reg, volatile.LoadUint32(&o.HP_ROOT_CLK_CTRL.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetHP_ROOT_CLK_CTRL_CPU_CLK_EN() uint32 { + return volatile.LoadUint32(&o.HP_ROOT_CLK_CTRL.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetHP_ROOT_CLK_CTRL_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.HP_ROOT_CLK_CTRL.Reg, volatile.LoadUint32(&o.HP_ROOT_CLK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetHP_ROOT_CLK_CTRL_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ROOT_CLK_CTRL.Reg) & 0x2) >> 1 +} + +// LPSYSREG.LP_PMU_RDN_ECO_LOW: need_des +func (o *LPSYSREG_Type) SetLP_PMU_RDN_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.LP_PMU_RDN_ECO_LOW.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_PMU_RDN_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.LP_PMU_RDN_ECO_LOW.Reg) +} + +// LPSYSREG.LP_PMU_RDN_ECO_HIGH: need_des +func (o *LPSYSREG_Type) SetLP_PMU_RDN_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.LP_PMU_RDN_ECO_HIGH.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_PMU_RDN_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.LP_PMU_RDN_ECO_HIGH.Reg) +} + +// LPSYSREG.PAD_COMP0: need_des +func (o *LPSYSREG_Type) SetPAD_COMP0_DREF_COMP0(value uint32) { + volatile.StoreUint32(&o.PAD_COMP0.Reg, volatile.LoadUint32(&o.PAD_COMP0.Reg)&^(0x7)|value) +} +func (o *LPSYSREG_Type) GetPAD_COMP0_DREF_COMP0() uint32 { + return volatile.LoadUint32(&o.PAD_COMP0.Reg) & 0x7 +} +func (o *LPSYSREG_Type) SetPAD_COMP0_MODE_COMP0(value uint32) { + volatile.StoreUint32(&o.PAD_COMP0.Reg, volatile.LoadUint32(&o.PAD_COMP0.Reg)&^(0x8)|value<<3) +} +func (o *LPSYSREG_Type) GetPAD_COMP0_MODE_COMP0() uint32 { + return (volatile.LoadUint32(&o.PAD_COMP0.Reg) & 0x8) >> 3 +} +func (o *LPSYSREG_Type) SetPAD_COMP0_XPD_COMP0(value uint32) { + volatile.StoreUint32(&o.PAD_COMP0.Reg, volatile.LoadUint32(&o.PAD_COMP0.Reg)&^(0x10)|value<<4) +} +func (o *LPSYSREG_Type) GetPAD_COMP0_XPD_COMP0() uint32 { + return (volatile.LoadUint32(&o.PAD_COMP0.Reg) & 0x10) >> 4 +} + +// LPSYSREG.PAD_COMP1: need_des +func (o *LPSYSREG_Type) SetPAD_COMP1_DREF_COMP1(value uint32) { + volatile.StoreUint32(&o.PAD_COMP1.Reg, volatile.LoadUint32(&o.PAD_COMP1.Reg)&^(0x7)|value) +} +func (o *LPSYSREG_Type) GetPAD_COMP1_DREF_COMP1() uint32 { + return volatile.LoadUint32(&o.PAD_COMP1.Reg) & 0x7 +} +func (o *LPSYSREG_Type) SetPAD_COMP1_MODE_COMP1(value uint32) { + volatile.StoreUint32(&o.PAD_COMP1.Reg, volatile.LoadUint32(&o.PAD_COMP1.Reg)&^(0x8)|value<<3) +} +func (o *LPSYSREG_Type) GetPAD_COMP1_MODE_COMP1() uint32 { + return (volatile.LoadUint32(&o.PAD_COMP1.Reg) & 0x8) >> 3 +} +func (o *LPSYSREG_Type) SetPAD_COMP1_XPD_COMP1(value uint32) { + volatile.StoreUint32(&o.PAD_COMP1.Reg, volatile.LoadUint32(&o.PAD_COMP1.Reg)&^(0x10)|value<<4) +} +func (o *LPSYSREG_Type) GetPAD_COMP1_XPD_COMP1() uint32 { + return (volatile.LoadUint32(&o.PAD_COMP1.Reg) & 0x10) >> 4 +} + +// LPSYSREG.BACKUP_DMA_CFG0: need_des +func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG0_BURST_LIMIT_AON(value uint32) { + volatile.StoreUint32(&o.BACKUP_DMA_CFG0.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg)&^(0x1f)|value) +} +func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG0_BURST_LIMIT_AON() uint32 { + return volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg) & 0x1f +} +func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG0_READ_INTERVAL_AON(value uint32) { + volatile.StoreUint32(&o.BACKUP_DMA_CFG0.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg)&^(0xfe0)|value<<5) +} +func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG0_READ_INTERVAL_AON() uint32 { + return (volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg) & 0xfe0) >> 5 +} +func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG0_LINK_BACKUP_TOUT_THRES_AON(value uint32) { + volatile.StoreUint32(&o.BACKUP_DMA_CFG0.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg)&^(0x3ff000)|value<<12) +} +func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG0_LINK_BACKUP_TOUT_THRES_AON() uint32 { + return (volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg) & 0x3ff000) >> 12 +} +func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG0_LINK_TOUT_THRES_AON(value uint32) { + volatile.StoreUint32(&o.BACKUP_DMA_CFG0.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg)&^(0xffc00000)|value<<22) +} +func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG0_LINK_TOUT_THRES_AON() uint32 { + return (volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg) & 0xffc00000) >> 22 +} + +// LPSYSREG.BACKUP_DMA_CFG1: need_des +func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG1_AON_BYPASS(value uint32) { + volatile.StoreUint32(&o.BACKUP_DMA_CFG1.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG1.Reg)&^(0x80000000)|value<<31) +} +func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG1_AON_BYPASS() uint32 { + return (volatile.LoadUint32(&o.BACKUP_DMA_CFG1.Reg) & 0x80000000) >> 31 +} + +// LPSYSREG.BACKUP_DMA_CFG2: need_des +func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG2(value uint32) { + volatile.StoreUint32(&o.BACKUP_DMA_CFG2.Reg, value) +} +func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG2() uint32 { + return volatile.LoadUint32(&o.BACKUP_DMA_CFG2.Reg) +} + +// LPSYSREG.BOOT_ADDR_HP_CORE1: need_des +func (o *LPSYSREG_Type) SetBOOT_ADDR_HP_CORE1(value uint32) { + volatile.StoreUint32(&o.BOOT_ADDR_HP_CORE1.Reg, value) +} +func (o *LPSYSREG_Type) GetBOOT_ADDR_HP_CORE1() uint32 { + return volatile.LoadUint32(&o.BOOT_ADDR_HP_CORE1.Reg) +} + +// LPSYSREG.LP_ADDRHOLE_ADDR: need_des +func (o *LPSYSREG_Type) SetLP_ADDRHOLE_ADDR(value uint32) { + volatile.StoreUint32(&o.LP_ADDRHOLE_ADDR.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_ADDRHOLE_ADDR() uint32 { + return volatile.LoadUint32(&o.LP_ADDRHOLE_ADDR.Reg) +} + +// LPSYSREG.LP_ADDRHOLE_INFO: need_des +func (o *LPSYSREG_Type) SetLP_ADDRHOLE_INFO_LP_ADDRHOLE_ID(value uint32) { + volatile.StoreUint32(&o.LP_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg)&^(0x1f)|value) +} +func (o *LPSYSREG_Type) GetLP_ADDRHOLE_INFO_LP_ADDRHOLE_ID() uint32 { + return volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg) & 0x1f +} +func (o *LPSYSREG_Type) SetLP_ADDRHOLE_INFO_LP_ADDRHOLE_WR(value uint32) { + volatile.StoreUint32(&o.LP_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg)&^(0x20)|value<<5) +} +func (o *LPSYSREG_Type) GetLP_ADDRHOLE_INFO_LP_ADDRHOLE_WR() uint32 { + return (volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg) & 0x20) >> 5 +} +func (o *LPSYSREG_Type) SetLP_ADDRHOLE_INFO_LP_ADDRHOLE_SECURE(value uint32) { + volatile.StoreUint32(&o.LP_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg)&^(0x40)|value<<6) +} +func (o *LPSYSREG_Type) GetLP_ADDRHOLE_INFO_LP_ADDRHOLE_SECURE() uint32 { + return (volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg) & 0x40) >> 6 +} + +// LPSYSREG.INT_RAW: raw interrupt register +func (o *LPSYSREG_Type) SetINT_RAW_LP_ADDRHOLE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetINT_RAW_LP_ADDRHOLE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetINT_RAW_IDBUS_ADDRHOLE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetINT_RAW_IDBUS_ADDRHOLE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LPSYSREG_Type) SetINT_RAW_LP_CORE_AHB_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LPSYSREG_Type) GetINT_RAW_LP_CORE_AHB_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LPSYSREG_Type) SetINT_RAW_LP_CORE_IBUS_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LPSYSREG_Type) GetINT_RAW_LP_CORE_IBUS_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LPSYSREG_Type) SetINT_RAW_LP_CORE_DBUS_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LPSYSREG_Type) GetINT_RAW_LP_CORE_DBUS_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LPSYSREG_Type) SetINT_RAW_ETM_TASK_ULP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LPSYSREG_Type) GetINT_RAW_ETM_TASK_ULP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LPSYSREG_Type) SetINT_RAW_SLOW_CLK_TICK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LPSYSREG_Type) GetINT_RAW_SLOW_CLK_TICK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} + +// LPSYSREG.INT_ST: masked interrupt register +func (o *LPSYSREG_Type) SetINT_ST_LP_ADDRHOLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetINT_ST_LP_ADDRHOLE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetINT_ST_IDBUS_ADDRHOLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetINT_ST_IDBUS_ADDRHOLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LPSYSREG_Type) SetINT_ST_LP_CORE_AHB_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LPSYSREG_Type) GetINT_ST_LP_CORE_AHB_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LPSYSREG_Type) SetINT_ST_LP_CORE_IBUS_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LPSYSREG_Type) GetINT_ST_LP_CORE_IBUS_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LPSYSREG_Type) SetINT_ST_LP_CORE_DBUS_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LPSYSREG_Type) GetINT_ST_LP_CORE_DBUS_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LPSYSREG_Type) SetINT_ST_ETM_TASK_ULP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LPSYSREG_Type) GetINT_ST_ETM_TASK_ULP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LPSYSREG_Type) SetINT_ST_SLOW_CLK_TICK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LPSYSREG_Type) GetINT_ST_SLOW_CLK_TICK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} + +// LPSYSREG.INT_ENA: masked interrupt register +func (o *LPSYSREG_Type) SetINT_ENA_LP_ADDRHOLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetINT_ENA_LP_ADDRHOLE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetINT_ENA_IDBUS_ADDRHOLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetINT_ENA_IDBUS_ADDRHOLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LPSYSREG_Type) SetINT_ENA_LP_CORE_AHB_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LPSYSREG_Type) GetINT_ENA_LP_CORE_AHB_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LPSYSREG_Type) SetINT_ENA_LP_CORE_IBUS_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LPSYSREG_Type) GetINT_ENA_LP_CORE_IBUS_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LPSYSREG_Type) SetINT_ENA_LP_CORE_DBUS_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LPSYSREG_Type) GetINT_ENA_LP_CORE_DBUS_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LPSYSREG_Type) SetINT_ENA_ETM_TASK_ULP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LPSYSREG_Type) GetINT_ENA_ETM_TASK_ULP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LPSYSREG_Type) SetINT_ENA_SLOW_CLK_TICK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LPSYSREG_Type) GetINT_ENA_SLOW_CLK_TICK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} + +// LPSYSREG.INT_CLR: interrupt clear register +func (o *LPSYSREG_Type) SetINT_CLR_LP_ADDRHOLE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetINT_CLR_LP_ADDRHOLE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetINT_CLR_IDBUS_ADDRHOLE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LPSYSREG_Type) GetINT_CLR_IDBUS_ADDRHOLE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LPSYSREG_Type) SetINT_CLR_LP_CORE_AHB_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LPSYSREG_Type) GetINT_CLR_LP_CORE_AHB_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LPSYSREG_Type) SetINT_CLR_LP_CORE_IBUS_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LPSYSREG_Type) GetINT_CLR_LP_CORE_IBUS_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LPSYSREG_Type) SetINT_CLR_LP_CORE_DBUS_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LPSYSREG_Type) GetINT_CLR_LP_CORE_DBUS_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LPSYSREG_Type) SetINT_CLR_ETM_TASK_ULP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LPSYSREG_Type) GetINT_CLR_ETM_TASK_ULP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LPSYSREG_Type) SetINT_CLR_SLOW_CLK_TICK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LPSYSREG_Type) GetINT_CLR_SLOW_CLK_TICK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} + +// LPSYSREG.HP_MEM_AUX_CTRL: need_des +func (o *LPSYSREG_Type) SetHP_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.HP_MEM_AUX_CTRL.Reg, value) +} +func (o *LPSYSREG_Type) GetHP_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.HP_MEM_AUX_CTRL.Reg) +} + +// LPSYSREG.LP_MEM_AUX_CTRL: need_des +func (o *LPSYSREG_Type) SetLP_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.LP_MEM_AUX_CTRL.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.LP_MEM_AUX_CTRL.Reg) +} + +// LPSYSREG.HP_ROM_AUX_CTRL: need_des +func (o *LPSYSREG_Type) SetHP_ROM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.HP_ROM_AUX_CTRL.Reg, value) +} +func (o *LPSYSREG_Type) GetHP_ROM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.HP_ROM_AUX_CTRL.Reg) +} + +// LPSYSREG.LP_ROM_AUX_CTRL: need_des +func (o *LPSYSREG_Type) SetLP_ROM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.LP_ROM_AUX_CTRL.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_ROM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.LP_ROM_AUX_CTRL.Reg) +} + +// LPSYSREG.LP_CPU_DBG_PC: need_des +func (o *LPSYSREG_Type) SetLP_CPU_DBG_PC(value uint32) { + volatile.StoreUint32(&o.LP_CPU_DBG_PC.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_CPU_DBG_PC() uint32 { + return volatile.LoadUint32(&o.LP_CPU_DBG_PC.Reg) +} + +// LPSYSREG.LP_CPU_EXC_PC: need_des +func (o *LPSYSREG_Type) SetLP_CPU_EXC_PC(value uint32) { + volatile.StoreUint32(&o.LP_CPU_EXC_PC.Reg, value) +} +func (o *LPSYSREG_Type) GetLP_CPU_EXC_PC() uint32 { + return volatile.LoadUint32(&o.LP_CPU_EXC_PC.Reg) +} + +// LPSYSREG.IDBUS_ADDRHOLE_ADDR: need_des +func (o *LPSYSREG_Type) SetIDBUS_ADDRHOLE_ADDR(value uint32) { + volatile.StoreUint32(&o.IDBUS_ADDRHOLE_ADDR.Reg, value) +} +func (o *LPSYSREG_Type) GetIDBUS_ADDRHOLE_ADDR() uint32 { + return volatile.LoadUint32(&o.IDBUS_ADDRHOLE_ADDR.Reg) +} + +// LPSYSREG.IDBUS_ADDRHOLE_INFO: need_des +func (o *LPSYSREG_Type) SetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_ID(value uint32) { + volatile.StoreUint32(&o.IDBUS_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg)&^(0x1f)|value) +} +func (o *LPSYSREG_Type) GetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_ID() uint32 { + return volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg) & 0x1f +} +func (o *LPSYSREG_Type) SetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_WR(value uint32) { + volatile.StoreUint32(&o.IDBUS_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg)&^(0x20)|value<<5) +} +func (o *LPSYSREG_Type) GetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_WR() uint32 { + return (volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg) & 0x20) >> 5 +} +func (o *LPSYSREG_Type) SetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_SECURE(value uint32) { + volatile.StoreUint32(&o.IDBUS_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg)&^(0x40)|value<<6) +} +func (o *LPSYSREG_Type) GetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_SECURE() uint32 { + return (volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg) & 0x40) >> 6 +} + +// LPSYSREG.HP_POR_RST_BYPASS_CTRL: need_des +func (o *LPSYSREG_Type) SetHP_POR_RST_BYPASS_CTRL_HP_PO_CNNT_RSTN_BYPASS_CTRL(value uint32) { + volatile.StoreUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg, volatile.LoadUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg)&^(0xff00)|value<<8) +} +func (o *LPSYSREG_Type) GetHP_POR_RST_BYPASS_CTRL_HP_PO_CNNT_RSTN_BYPASS_CTRL() uint32 { + return (volatile.LoadUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg) & 0xff00) >> 8 +} +func (o *LPSYSREG_Type) SetHP_POR_RST_BYPASS_CTRL_HP_PO_RSTN_BYPASS_CTRL(value uint32) { + volatile.StoreUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg, volatile.LoadUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg)&^(0xff000000)|value<<24) +} +func (o *LPSYSREG_Type) GetHP_POR_RST_BYPASS_CTRL_HP_PO_RSTN_BYPASS_CTRL() uint32 { + return (volatile.LoadUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg) & 0xff000000) >> 24 +} + +// LPSYSREG.RNG_DATA: rng data register +func (o *LPSYSREG_Type) SetRNG_DATA(value uint32) { + volatile.StoreUint32(&o.RNG_DATA.Reg, value) +} +func (o *LPSYSREG_Type) GetRNG_DATA() uint32 { + return volatile.LoadUint32(&o.RNG_DATA.Reg) +} + +// LPSYSREG.LP_CORE_AHB_TIMEOUT: need_des +func (o *LPSYSREG_Type) SetLP_CORE_AHB_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.LP_CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetLP_CORE_AHB_TIMEOUT_EN() uint32 { + return volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetLP_CORE_AHB_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.LP_CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg)&^(0x1fffe)|value<<1) +} +func (o *LPSYSREG_Type) GetLP_CORE_AHB_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg) & 0x1fffe) >> 1 +} +func (o *LPSYSREG_Type) SetLP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.LP_CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg)&^(0x20000)|value<<17) +} +func (o *LPSYSREG_Type) GetLP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg) & 0x20000) >> 17 +} +func (o *LPSYSREG_Type) SetLP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.LP_CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg)&^(0x7c0000)|value<<18) +} +func (o *LPSYSREG_Type) GetLP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg) & 0x7c0000) >> 18 +} + +// LPSYSREG.LP_CORE_IBUS_TIMEOUT: need_des +func (o *LPSYSREG_Type) SetLP_CORE_IBUS_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetLP_CORE_IBUS_TIMEOUT_EN() uint32 { + return volatile.LoadUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetLP_CORE_IBUS_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg)&^(0x1fffe)|value<<1) +} +func (o *LPSYSREG_Type) GetLP_CORE_IBUS_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg) & 0x1fffe) >> 1 +} + +// LPSYSREG.LP_CORE_DBUS_TIMEOUT: need_des +func (o *LPSYSREG_Type) SetLP_CORE_DBUS_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetLP_CORE_DBUS_TIMEOUT_EN() uint32 { + return volatile.LoadUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetLP_CORE_DBUS_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg)&^(0x1fffe)|value<<1) +} +func (o *LPSYSREG_Type) GetLP_CORE_DBUS_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg) & 0x1fffe) >> 1 +} + +// LPSYSREG.LP_CORE_ERR_RESP_DIS: need_des +func (o *LPSYSREG_Type) SetLP_CORE_ERR_RESP_DIS(value uint32) { + volatile.StoreUint32(&o.LP_CORE_ERR_RESP_DIS.Reg, volatile.LoadUint32(&o.LP_CORE_ERR_RESP_DIS.Reg)&^(0x7)|value) +} +func (o *LPSYSREG_Type) GetLP_CORE_ERR_RESP_DIS() uint32 { + return volatile.LoadUint32(&o.LP_CORE_ERR_RESP_DIS.Reg) & 0x7 +} + +// LPSYSREG.RNG_CFG: rng cfg register +func (o *LPSYSREG_Type) SetRNG_CFG_RNG_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x1)|value) +} +func (o *LPSYSREG_Type) GetRNG_CFG_RNG_TIMER_EN() uint32 { + return volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x1 +} +func (o *LPSYSREG_Type) SetRNG_CFG_RNG_TIMER_PSCALE(value uint32) { + volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x1fe)|value<<1) +} +func (o *LPSYSREG_Type) GetRNG_CFG_RNG_TIMER_PSCALE() uint32 { + return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x1fe) >> 1 +} +func (o *LPSYSREG_Type) SetRNG_CFG_RNG_SAR_ENABLE(value uint32) { + volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x200)|value<<9) +} +func (o *LPSYSREG_Type) GetRNG_CFG_RNG_SAR_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x200) >> 9 +} +func (o *LPSYSREG_Type) SetRNG_CFG_RNG_SAR_DATA(value uint32) { + volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x1fff0000)|value<<16) +} +func (o *LPSYSREG_Type) GetRNG_CFG_RNG_SAR_DATA() uint32 { + return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x1fff0000) >> 16 +} + +// LP_ANA_PERI Peripheral +type LP_ANA_PERI_Type struct { + LP_ANA_BOD_MODE0_CNTL volatile.Register32 // 0x0 + LP_ANA_BOD_MODE1_CNTL volatile.Register32 // 0x4 + LP_ANA_VDD_SOURCE_CNTL volatile.Register32 // 0x8 + LP_ANA_VDDBAT_BOD_CNTL volatile.Register32 // 0xC + LP_ANA_VDDBAT_CHARGE_CNTL volatile.Register32 // 0x10 + LP_ANA_CK_GLITCH_CNTL volatile.Register32 // 0x14 + LP_ANA_PG_GLITCH_CNTL volatile.Register32 // 0x18 + LP_ANA_FIB_ENABLE volatile.Register32 // 0x1C + LP_ANA_INT_RAW volatile.Register32 // 0x20 + LP_ANA_INT_ST volatile.Register32 // 0x24 + LP_ANA_INT_ENA volatile.Register32 // 0x28 + LP_ANA_INT_CLR volatile.Register32 // 0x2C + LP_ANA_LP_INT_RAW volatile.Register32 // 0x30 + LP_ANA_LP_INT_ST volatile.Register32 // 0x34 + LP_ANA_LP_INT_ENA volatile.Register32 // 0x38 + LP_ANA_LP_INT_CLR volatile.Register32 // 0x3C + _ [188]byte + LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM volatile.Register32 // 0xFC + LP_ANA_TOUCH_SCAN_CTRL1 volatile.Register32 // 0x100 + LP_ANA_TOUCH_SCAN_CTRL2 volatile.Register32 // 0x104 + LP_ANA_TOUCH_WORK volatile.Register32 // 0x108 + LP_ANA_TOUCH_WORK_MEAS_NUM volatile.Register32 // 0x10C + LP_ANA_TOUCH_FILTER1 volatile.Register32 // 0x110 + LP_ANA_TOUCH_FILTER2 volatile.Register32 // 0x114 + LP_ANA_TOUCH_FILTER3 volatile.Register32 // 0x118 + LP_ANA_TOUCH_SLP0 volatile.Register32 // 0x11C + LP_ANA_TOUCH_SLP1 volatile.Register32 // 0x120 + LP_ANA_TOUCH_CLR volatile.Register32 // 0x124 + LP_ANA_TOUCH_APPROACH volatile.Register32 // 0x128 + LP_ANA_TOUCH_FREQ0_SCAN_PARA volatile.Register32 // 0x12C + LP_ANA_TOUCH_FREQ1_SCAN_PARA volatile.Register32 // 0x130 + LP_ANA_TOUCH_FREQ2_SCAN_PARA volatile.Register32 // 0x134 + LP_ANA_TOUCH_ANA_PARA volatile.Register32 // 0x138 + LP_ANA_TOUCH_MUX0 volatile.Register32 // 0x13C + LP_ANA_TOUCH_MUX1 volatile.Register32 // 0x140 + LP_ANA_TOUCH_PAD0_TH0 volatile.Register32 // 0x144 + LP_ANA_TOUCH_PAD0_TH1 volatile.Register32 // 0x148 + LP_ANA_TOUCH_PAD0_TH2 volatile.Register32 // 0x14C + LP_ANA_TOUCH_PAD1_TH0 volatile.Register32 // 0x150 + LP_ANA_TOUCH_PAD1_TH1 volatile.Register32 // 0x154 + LP_ANA_TOUCH_PAD1_TH2 volatile.Register32 // 0x158 + LP_ANA_TOUCH_PAD2_TH0 volatile.Register32 // 0x15C + LP_ANA_TOUCH_PAD2_TH1 volatile.Register32 // 0x160 + LP_ANA_TOUCH_PAD2_TH2 volatile.Register32 // 0x164 + LP_ANA_TOUCH_PAD3_TH0 volatile.Register32 // 0x168 + LP_ANA_TOUCH_PAD3_TH1 volatile.Register32 // 0x16C + LP_ANA_TOUCH_PAD3_TH2 volatile.Register32 // 0x170 + LP_ANA_TOUCH_PAD4_TH0 volatile.Register32 // 0x174 + LP_ANA_TOUCH_PAD4_TH1 volatile.Register32 // 0x178 + LP_ANA_TOUCH_PAD4_TH2 volatile.Register32 // 0x17C + LP_ANA_TOUCH_PAD5_TH0 volatile.Register32 // 0x180 + LP_ANA_TOUCH_PAD5_TH1 volatile.Register32 // 0x184 + LP_ANA_TOUCH_PAD5_TH2 volatile.Register32 // 0x188 + LP_ANA_TOUCH_PAD6_TH0 volatile.Register32 // 0x18C + LP_ANA_TOUCH_PAD6_TH1 volatile.Register32 // 0x190 + LP_ANA_TOUCH_PAD6_TH2 volatile.Register32 // 0x194 + LP_ANA_TOUCH_PAD7_TH0 volatile.Register32 // 0x198 + LP_ANA_TOUCH_PAD7_TH1 volatile.Register32 // 0x19C + LP_ANA_TOUCH_PAD7_TH2 volatile.Register32 // 0x1A0 + LP_ANA_TOUCH_PAD8_TH0 volatile.Register32 // 0x1A4 + LP_ANA_TOUCH_PAD8_TH1 volatile.Register32 // 0x1A8 + LP_ANA_TOUCH_PAD8_TH2 volatile.Register32 // 0x1AC + LP_ANA_TOUCH_PAD9_TH0 volatile.Register32 // 0x1B0 + LP_ANA_TOUCH_PAD9_TH1 volatile.Register32 // 0x1B4 + LP_ANA_TOUCH_PAD9_TH2 volatile.Register32 // 0x1B8 + LP_ANA_TOUCH_PAD10_TH0 volatile.Register32 // 0x1BC + LP_ANA_TOUCH_PAD10_TH1 volatile.Register32 // 0x1C0 + LP_ANA_TOUCH_PAD10_TH2 volatile.Register32 // 0x1C4 + LP_ANA_TOUCH_PAD11_TH0 volatile.Register32 // 0x1C8 + LP_ANA_TOUCH_PAD11_TH1 volatile.Register32 // 0x1CC + LP_ANA_TOUCH_PAD11_TH2 volatile.Register32 // 0x1D0 + LP_ANA_TOUCH_PAD12_TH0 volatile.Register32 // 0x1D4 + LP_ANA_TOUCH_PAD12_TH1 volatile.Register32 // 0x1D8 + LP_ANA_TOUCH_PAD12_TH2 volatile.Register32 // 0x1DC + LP_ANA_TOUCH_PAD13_TH0 volatile.Register32 // 0x1E0 + LP_ANA_TOUCH_PAD13_TH1 volatile.Register32 // 0x1E4 + LP_ANA_TOUCH_PAD13_TH2 volatile.Register32 // 0x1E8 + LP_ANA_TOUCH_PAD14_TH0 volatile.Register32 // 0x1EC + LP_ANA_TOUCH_PAD14_TH1 volatile.Register32 // 0x1F0 + LP_ANA_TOUCH_PAD14_TH2 volatile.Register32 // 0x1F4 + _ [516]byte + LP_ANA_DATE volatile.Register32 // 0x3FC +} + +// LP_ANA_PERI.LP_ANA_BOD_MODE0_CNTL: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x40)|value<<6) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x40) >> 6 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_PD_RF_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x80)|value<<7) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_PD_RF_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x80) >> 7 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_WAIT(value uint32) { + volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x3ff00)|value<<8) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_WAIT() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x3ff00) >> 8 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_WAIT(value uint32) { + volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0xffc0000)|value<<18) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_WAIT() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0xffc0000) >> 18 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_SEL(value uint32) { + volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_BOD_MODE1_CNTL: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE1_CNTL_LP_ANA_BOD_MODE1_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_BOD_MODE1_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE1_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE1_CNTL_LP_ANA_BOD_MODE1_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE1_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_VDD_SOURCE_CNTL: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_DETMODE_SEL(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg)&^(0xff)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_DETMODE_SEL() uint32 { + return volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg) & 0xff +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_VGOOD_EVENT_RECORD(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg)&^(0xff00)|value<<8) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_VGOOD_EVENT_RECORD() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg) & 0xff00) >> 8 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_VBAT_EVENT_RECORD_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg)&^(0xff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_VBAT_EVENT_RECORD_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg) & 0xff0000) >> 16 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_BOD_SOURCE_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg)&^(0xff000000)|value<<24) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_BOD_SOURCE_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg) & 0xff000000) >> 24 +} + +// LP_ANA_PERI.LP_ANA_VDDBAT_BOD_CNTL: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0x1)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG() uint32 { + return volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0x1 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CHARGER(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0x400)|value<<10) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CHARGER() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0x400) >> 10 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0x800)|value<<11) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0x800) >> 11 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UPVOLTAGE_TARGET(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0x3ff000)|value<<12) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UPVOLTAGE_TARGET() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0x3ff000) >> 12 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_ANA_PERI.LP_ANA_VDDBAT_CHARGE_CNTL: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0x1)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG() uint32 { + return volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0x1 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CHARGER(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0x400)|value<<10) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CHARGER() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0x400) >> 10 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0x800)|value<<11) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0x800) >> 11 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0x3ff000)|value<<12) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0x3ff000) >> 12 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET(value uint32) { + volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_ANA_PERI.LP_ANA_CK_GLITCH_CNTL: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_CK_GLITCH_CNTL_LP_ANA_CK_GLITCH_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_CK_GLITCH_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_CK_GLITCH_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_CK_GLITCH_CNTL_LP_ANA_CK_GLITCH_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_CK_GLITCH_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_PG_GLITCH_CNTL: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_PG_GLITCH_CNTL_LP_ANA_POWER_GLITCH_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_PG_GLITCH_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_PG_GLITCH_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_PG_GLITCH_CNTL_LP_ANA_POWER_GLITCH_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_PG_GLITCH_CNTL.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_FIB_ENABLE: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_FIB_ENABLE(value uint32) { + volatile.StoreUint32(&o.LP_ANA_FIB_ENABLE.Reg, value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_FIB_ENABLE() uint32 { + return volatile.LoadUint32(&o.LP_ANA_FIB_ENABLE.Reg) +} + +// LP_ANA_PERI.LP_ANA_INT_RAW: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_BOD_MODE0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_BOD_MODE0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_INT_ST: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_BOD_MODE0_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_BOD_MODE0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_INT_ENA: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_BOD_MODE0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_BOD_MODE0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_INT_CLR: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_BOD_MODE0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_BOD_MODE0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_LP_INT_RAW: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_LP_INT_RAW_LP_ANA_BOD_MODE0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_ANA_LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_LP_INT_RAW_LP_ANA_BOD_MODE0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_LP_INT_ST: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_LP_INT_ST_LP_ANA_BOD_MODE0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_ANA_LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_LP_INT_ST_LP_ANA_BOD_MODE0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_LP_INT_ENA: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_LP_INT_ENA_LP_ANA_BOD_MODE0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_ANA_LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_LP_INT_ENA_LP_ANA_BOD_MODE0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_LP_INT_CLR: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_LP_INT_CLR_LP_ANA_BOD_MODE0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_LP_INT_CLR_LP_ANA_BOD_MODE0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg)&^(0x3ff)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM2() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg) & 0x3ff +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg)&^(0xffc00)|value<<10) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg) & 0xffc00) >> 10 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg) & 0x3ff00000) >> 20 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_SCAN_CTRL1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SHIELD_PAD_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg)&^(0x1)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SHIELD_PAD_EN() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg) & 0x1 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_INACTIVE_CONNECTION(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_INACTIVE_CONNECTION() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg) & 0x2) >> 1 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SCAN_PAD_MAP(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg)&^(0x1fffc)|value<<2) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SCAN_PAD_MAP() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg) & 0x1fffc) >> 2 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg)&^(0xfffe0000)|value<<17) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_XPD_WAIT() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg) & 0xfffe0000) >> 17 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_SCAN_CTRL2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_NUM(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x3fffc0)|value<<6) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x3fffc0) >> 6 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x400000)|value<<22) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_EN() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x400000) >> 22 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_OUT_RING(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x7800000)|value<<23) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_OUT_RING() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x7800000) >> 23 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_EN() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_CNT_LIMIT(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x30000000)|value<<28) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_CNT_LIMIT() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x30000000) >> 28 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_WORK: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x70000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x70000) >> 16 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x380000)|value<<19) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x380000) >> 19 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x1c00000) >> 22 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x2000000) >> 25 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_RESET(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_RESET() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x4000000) >> 26 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_GATE(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_GATE() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x8000000) >> 27 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_WORK_MEAS_NUM: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg)&^(0x3ff)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM2() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg) & 0x3ff +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg)&^(0xffc00)|value<<10) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg) & 0xffc00) >> 10 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg) & 0x3ff00000) >> 20 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_FILTER1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x1)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x1 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_HYSTERESIS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x6)|value<<1) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_HYSTERESIS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x6) >> 1 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x18)|value<<3) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x18) >> 3 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x60)|value<<5) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x60) >> 5 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_SMOOTH_LVL(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x180)|value<<7) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_SMOOTH_LVL() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x180) >> 7 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_JITTER_STEP(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x1e00)|value<<9) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_JITTER_STEP() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x1e00) >> 9 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0xe000)|value<<13) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0xe000) >> 13 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x10000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x10000) >> 16 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_LIMIT(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x1e0000)|value<<17) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_LIMIT() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x1e0000) >> 17 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_APPROACH_LIMIT(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x1fe00000)|value<<21) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_APPROACH_LIMIT() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x1fe00000) >> 21 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_DEBOUNCE_LIMIT(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0xe0000000)|value<<29) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_DEBOUNCE_LIMIT() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0xe0000000) >> 29 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_FILTER2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_OUTEN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg)&^(0x3fff8000)|value<<15) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_OUTEN() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg) & 0x3fff8000) >> 15 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_FILTER3: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_BASELINE_SW(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER3.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER3.Reg)&^(0xffff)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_BASELINE_SW() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER3.Reg) & 0xffff +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_UPDATE_BASELINE_SW(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER3.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER3.Reg)&^(0x10000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_UPDATE_BASELINE_SW() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER3.Reg) & 0x10000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_SLP0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg)&^(0xffff)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_TH0() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg) & 0xffff +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_CHANNEL_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg)&^(0x10000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_CHANNEL_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg) & 0x10000) >> 16 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_PAD(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg)&^(0x1e0000)|value<<17) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_PAD() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg) & 0x1e0000) >> 17 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_SLP1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP1.Reg)&^(0xffff)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH2() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP1.Reg) & 0xffff +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_CLR: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_CLR_LP_ANA_TOUCH_CHANNEL_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_CLR.Reg)&^(0x7fff)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_CLR_LP_ANA_TOUCH_CHANNEL_CLR() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_CLR.Reg) & 0x7fff +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_CLR_LP_ANA_TOUCH_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_CLR_LP_ANA_TOUCH_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_CLR.Reg) & 0x8000) >> 15 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_APPROACH: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_PAD0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg)&^(0xf)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_PAD0() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg) & 0xf +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_PAD1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg)&^(0xf0)|value<<4) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_PAD1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg) & 0xf0) >> 4 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_PAD2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg)&^(0xf00)|value<<8) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_PAD2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg) & 0xf00) >> 8 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_LP_ANA_TOUCH_SLP_APPROACH_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg)&^(0x1000)|value<<12) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_LP_ANA_TOUCH_SLP_APPROACH_EN() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg) & 0x1000) >> 12 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_FREQ0_SCAN_PARA: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DCAP_LPF(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x7f)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DCAP_LPF() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x7f +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRES_LPF(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x180)|value<<7) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRES_LPF() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x180) >> 7 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_LS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x1e00)|value<<9) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_LS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x1e00) >> 9 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_HS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x3e000)|value<<13) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_HS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x3e000) >> 13 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DBIAS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DBIAS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x7c0000) >> 18 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_FREQ1_SCAN_PARA: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DCAP_LPF(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x7f)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DCAP_LPF() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x7f +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRES_LPF(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x180)|value<<7) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRES_LPF() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x180) >> 7 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_LS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x1e00)|value<<9) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_LS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x1e00) >> 9 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_HS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x3e000)|value<<13) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_HS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x3e000) >> 13 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DBIAS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DBIAS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x7c0000) >> 18 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_FREQ2_SCAN_PARA: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DCAP_LPF(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x7f)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DCAP_LPF() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x7f +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRES_LPF(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x180)|value<<7) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRES_LPF() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x180) >> 7 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_LS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x1e00)|value<<9) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_LS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x1e00) >> 9 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_HS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x3e000)|value<<13) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_HS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x3e000) >> 13 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DBIAS(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DBIAS() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x7c0000) >> 18 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_ANA_PARA: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_BUF_DRV(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg)&^(0x7)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_BUF_DRV() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg) & 0x7 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_EN_CAL(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg)&^(0x8)|value<<3) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_EN_CAL() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg) & 0x8) >> 3 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_DCAP_CAL(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg)&^(0x7f0)|value<<4) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_DCAP_CAL() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg) & 0x7f0) >> 4 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_MUX0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DATA_SEL(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x300)|value<<8) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DATA_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x300) >> 8 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FREQ_SEL(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0xc00)|value<<10) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FREQ_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0xc00) >> 10 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_BUFSEL(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x7fff000)|value<<12) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_BUFSEL() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x7fff000) >> 12 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_EN() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x8000000) >> 27 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_FORCE(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_FORCE() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x10000000) >> 28 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FSM_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FSM_EN() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x20000000) >> 29 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_EN() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x40000000) >> 30 +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_FORCE(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x80000000) >> 31 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_MUX1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_START(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX1.Reg)&^(0x7fff)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_START() uint32 { + return volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX1.Reg) & 0x7fff +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_XPD(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX1.Reg)&^(0x3fff8000)|value<<15) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_XPD() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX1.Reg) & 0x3fff8000) >> 15 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD0_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD0_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD0_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD0_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD0_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD0_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD0_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD0_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD0_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD0_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD0_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD0_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD1_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD1_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD1_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD1_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD1_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD1_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD1_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD1_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD1_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD1_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD1_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD1_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD2_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD2_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD2_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD2_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD2_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD2_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD2_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD2_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD2_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD2_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD2_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD2_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD3_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD3_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD3_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD3_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD3_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD3_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD3_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD3_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD3_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD3_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD3_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD3_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD4_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD4_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD4_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD4_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD4_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD4_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD4_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD4_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD4_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD4_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD4_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD4_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD5_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD5_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD5_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD5_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD5_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD5_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD5_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD5_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD5_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD5_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD5_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD5_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD6_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD6_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD6_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD6_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD6_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD6_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD6_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD6_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD6_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD6_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD6_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD6_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD7_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD7_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD7_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD7_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD7_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD7_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD7_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD7_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD7_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD7_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD7_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD7_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD8_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD8_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD8_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD8_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD8_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD8_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD8_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD8_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD8_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD8_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD8_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD8_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD9_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD9_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD9_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD9_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD9_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD9_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD9_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD9_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD9_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD9_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD9_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD9_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD10_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD10_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD10_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD10_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD10_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD10_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD10_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD10_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD10_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD10_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD10_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD10_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD11_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD11_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD11_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD11_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD11_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD11_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD11_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD11_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD11_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD11_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD11_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD11_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD12_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD12_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD12_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD12_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD12_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD12_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD12_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD12_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD12_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD12_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD12_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD12_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD13_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD13_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD13_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD13_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD13_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD13_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD13_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD13_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD13_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD13_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD13_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD13_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD14_TH0: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD14_TH0(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD14_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD14_TH0() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH0.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD14_TH1: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD14_TH1(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD14_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD14_TH1() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH1.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_TOUCH_PAD14_TH2: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD14_TH2(value uint32) { + volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD14_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD14_TH2() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH2.Reg) & 0xffff0000) >> 16 +} + +// LP_ANA_PERI.LP_ANA_DATE: need_des +func (o *LP_ANA_PERI_Type) SetLP_ANA_DATE_LP_ANA_LP_ANA_DATE(value uint32) { + volatile.StoreUint32(&o.LP_ANA_DATE.Reg, volatile.LoadUint32(&o.LP_ANA_DATE.Reg)&^(0x7fffffff)|value) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_DATE_LP_ANA_LP_ANA_DATE() uint32 { + return volatile.LoadUint32(&o.LP_ANA_DATE.Reg) & 0x7fffffff +} +func (o *LP_ANA_PERI_Type) SetLP_ANA_DATE_LP_ANA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_ANA_DATE.Reg, volatile.LoadUint32(&o.LP_ANA_DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_ANA_PERI_Type) GetLP_ANA_DATE_LP_ANA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_ANA_DATE.Reg) & 0x80000000) >> 31 +} + +// LP_AON_CLKRST Peripheral +type LP_AON_CLKRST_Type struct { + LP_AONCLKRST_LP_CLK_CONF volatile.Register32 // 0x0 + LP_AONCLKRST_LP_CLK_PO_EN volatile.Register32 // 0x4 + LP_AONCLKRST_LP_CLK_EN volatile.Register32 // 0x8 + LP_AONCLKRST_LP_RST_EN volatile.Register32 // 0xC + LP_AONCLKRST_RESET_CAUSE volatile.Register32 // 0x10 + LP_AONCLKRST_HPCPU_RESET_CTRL0 volatile.Register32 // 0x14 + LP_AONCLKRST_HPCPU_RESET_CTRL1 volatile.Register32 // 0x18 + LP_AONCLKRST_FOSC_CNTL volatile.Register32 // 0x1C + LP_AONCLKRST_RC32K_CNTL volatile.Register32 // 0x20 + LP_AONCLKRST_SOSC_CNTL volatile.Register32 // 0x24 + LP_AONCLKRST_CLK_TO_HP volatile.Register32 // 0x28 + LP_AONCLKRST_LPMEM_FORCE volatile.Register32 // 0x2C + LP_AONCLKRST_XTAL32K volatile.Register32 // 0x30 + LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS volatile.Register32 // 0x34 + LP_AONCLKRST_HPSYS_0_RESET_BYPASS volatile.Register32 // 0x38 + LP_AONCLKRST_HPSYS_APM_RESET_BYPASS volatile.Register32 // 0x3C + LP_AONCLKRST_HP_CLK_CTRL volatile.Register32 // 0x40 + LP_AONCLKRST_HP_USB_CLKRST_CTRL0 volatile.Register32 // 0x44 + LP_AONCLKRST_HP_USB_CLKRST_CTRL1 volatile.Register32 // 0x48 + LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL volatile.Register32 // 0x4C + _ [940]byte + LP_AONCLKRST_DATE volatile.Register32 // 0x3FC +} + +// LP_AON_CLKRST.LP_AONCLKRST_LP_CLK_CONF: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_SLOW_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg)&^(0x3)|value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_SLOW_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg) & 0x3 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_FAST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg)&^(0xc)|value<<2) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_FAST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg) & 0xc) >> 2 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_LP_PERI_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg)&^(0x3f0)|value<<4) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_LP_PERI_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg) & 0x3f0) >> 4 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_ANA_SEL_REF_PLL8M(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_ANA_SEL_REF_PLL8M() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg) & 0x400) >> 10 +} + +// LP_AON_CLKRST.LP_AONCLKRST_LP_CLK_PO_EN: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_CORE_EFUSE_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x1)|value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_CORE_EFUSE_OEN() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x1 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_LP_BUS_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x2)|value<<1) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_LP_BUS_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x2) >> 1 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_SLOW_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x4)|value<<2) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_SLOW_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x4) >> 2 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_FAST_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x8)|value<<3) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_FAST_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x8) >> 3 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SLOW_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x10)|value<<4) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SLOW_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x10) >> 4 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FAST_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x20)|value<<5) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FAST_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x20) >> 5 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FOSC_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x40)|value<<6) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FOSC_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x40) >> 6 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_RC32K_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x80)|value<<7) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_RC32K_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x80) >> 7 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SXTAL_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x100)|value<<8) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SXTAL_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x100) >> 8 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SOSC_OEN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x200)|value<<9) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SOSC_OEN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x200) >> 9 +} + +// LP_AON_CLKRST.LP_AONCLKRST_LP_CLK_EN: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x4000000) >> 26 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_CK_EN_LP_RAM(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_CK_EN_LP_RAM() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x8000000) >> 27 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_ETM_EVENT_TICK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_ETM_EVENT_TICK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_PLL8M_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_PLL8M_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_XTAL_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_XTAL_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_FOSC_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_FOSC_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x80000000) >> 31 +} + +// LP_AON_CLKRST.LP_AONCLKRST_LP_RST_EN: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_HUK(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_HUK() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x1000000) >> 24 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_ANAPERI(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_ANAPERI() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x2000000) >> 25 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_WDT(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_WDT() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x4000000) >> 26 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_TIMER(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_TIMER() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x8000000) >> 27 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RTC(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RTC() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_MAILBOX(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_MAILBOX() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_AONEFUSEREG(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_AONEFUSEREG() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RAM(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RAM() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x80000000) >> 31 +} + +// LP_AON_CLKRST.LP_AONCLKRST_RESET_CAUSE: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x3f)|value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x3f +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x40)|value<<6) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x40) >> 6 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x1f80)|value<<7) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x1f80) >> 7 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x2000)|value<<13) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x2000) >> 13 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0xfc000)|value<<14) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0xfc000) >> 14 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x100000)|value<<20) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x100000) >> 20 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x2000000) >> 25 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x4000000) >> 26 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x8000000) >> 27 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x80000000) >> 31 +} + +// LP_AON_CLKRST.LP_AONCLKRST_HPCPU_RESET_CTRL0: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x1)|value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x1 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0xe)|value<<1) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0xe) >> 1 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x10)|value<<4) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x10) >> 4 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0xfe0)|value<<5) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0xfe0) >> 5 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x1000)|value<<12) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x1000) >> 12 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_SW_RESET(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x2000)|value<<13) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_SW_RESET() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x2000) >> 13 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x4000)|value<<14) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x4000) >> 14 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x8000)|value<<15) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x8000) >> 15 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x10000)|value<<16) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x10000) >> 16 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0xe0000)|value<<17) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0xe0000) >> 17 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x100000)|value<<20) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x100000) >> 20 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0xfe00000)|value<<21) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0xfe00000) >> 21 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_SW_RESET(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_SW_RESET() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x80000000) >> 31 +} + +// LP_AON_CLKRST.LP_AONCLKRST_HPCPU_RESET_CTRL1: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE0_SW_STALL_CODE(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg)&^(0xff0000)|value<<16) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE0_SW_STALL_CODE() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg) & 0xff0000) >> 16 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE1_SW_STALL_CODE(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg)&^(0xff000000)|value<<24) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE1_SW_STALL_CODE() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg) & 0xff000000) >> 24 +} + +// LP_AON_CLKRST.LP_AONCLKRST_FOSC_CNTL: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_FOSC_CNTL_LP_AONCLKRST_FOSC_DFREQ(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_FOSC_CNTL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_FOSC_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_FOSC_CNTL_LP_AONCLKRST_FOSC_DFREQ() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_FOSC_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_AON_CLKRST.LP_AONCLKRST_RC32K_CNTL: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RC32K_CNTL(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_RC32K_CNTL.Reg, value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RC32K_CNTL() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_RC32K_CNTL.Reg) +} + +// LP_AON_CLKRST.LP_AONCLKRST_SOSC_CNTL: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_SOSC_CNTL_LP_AONCLKRST_SOSC_DFREQ(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_SOSC_CNTL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_SOSC_CNTL.Reg)&^(0xffc00000)|value<<22) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_SOSC_CNTL_LP_AONCLKRST_SOSC_DFREQ() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_SOSC_CNTL.Reg) & 0xffc00000) >> 22 +} + +// LP_AON_CLKRST.LP_AONCLKRST_CLK_TO_HP: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_SOSC(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_SOSC() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_OSC32K(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_OSC32K() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_FOSC(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_FOSC() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg) & 0x80000000) >> 31 +} + +// LP_AON_CLKRST.LP_AONCLKRST_LPMEM_FORCE: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LPMEM_FORCE_LP_AONCLKRST_LPMEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_LPMEM_FORCE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LPMEM_FORCE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LPMEM_FORCE_LP_AONCLKRST_LPMEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_LPMEM_FORCE.Reg) & 0x80000000) >> 31 +} + +// LP_AON_CLKRST.LP_AONCLKRST_XTAL32K: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DRES_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_XTAL32K.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg)&^(0x1c00000)|value<<22) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DRES_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg) & 0x1c00000) >> 22 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DGM_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_XTAL32K.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg)&^(0xe000000)|value<<25) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DGM_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg) & 0xe000000) >> 25 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DBUF_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_XTAL32K.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DBUF_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DAC_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_XTAL32K.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg)&^(0xe0000000)|value<<29) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DAC_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg) & 0xe0000000) >> 29 +} + +// LP_AON_CLKRST.LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_MUX_HPSYS_RESET_BYPASS(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS.Reg, value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_MUX_HPSYS_RESET_BYPASS() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS.Reg) +} + +// LP_AON_CLKRST.LP_AONCLKRST_HPSYS_0_RESET_BYPASS: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPSYS_0_RESET_BYPASS(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPSYS_0_RESET_BYPASS.Reg, value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPSYS_0_RESET_BYPASS() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_HPSYS_0_RESET_BYPASS.Reg) +} + +// LP_AON_CLKRST.LP_AONCLKRST_HPSYS_APM_RESET_BYPASS: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPSYS_APM_RESET_BYPASS(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HPSYS_APM_RESET_BYPASS.Reg, value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPSYS_APM_RESET_BYPASS() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_HPSYS_APM_RESET_BYPASS.Reg) +} + +// LP_AON_CLKRST.LP_AONCLKRST_HP_CLK_CTRL: HP Clock Control Register. +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x3)|value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x3 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x4) >> 2 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x8) >> 3 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x10) >> 4 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x20) >> 5 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x40) >> 6 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x80) >> 7 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x100) >> 8 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x200) >> 9 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x400) >> 10 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x800) >> 11 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x1000) >> 12 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x2000) >> 13 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x4000) >> 14 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x8000) >> 15 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_32K_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_32K_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x10000) >> 16 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_RC_32K_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_RC_32K_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x20000) >> 17 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SOSC_150K_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SOSC_150K_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x40000) >> 18 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PLL_8M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PLL_8M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x80000) >> 19 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x100000) >> 20 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x200000) >> 21 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x400000) >> 22 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x800000) >> 23 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_FOSC_20M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_FOSC_20M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_40M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_40M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_CPLL_400M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_CPLL_400M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SPLL_480M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SPLL_480M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_MPLL_500M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_MPLL_500M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x10000000) >> 28 +} + +// LP_AON_CLKRST.LP_AONCLKRST_HP_USB_CLKRST_CTRL0: HP USB Clock Reset Control Register. +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_SLEEP_MODE(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x1)|value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_SLEEP_MODE() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x1 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x2)|value<<1) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x2) >> 1 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_SLEEP_MODE(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x4)|value<<2) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_SLEEP_MODE() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x4) >> 2 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x8)|value<<3) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x8) >> 3 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_48M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x10)|value<<4) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_48M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x10) >> 4 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_DEVICE_48M_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x20)|value<<5) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_DEVICE_48M_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x20) >> 5 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_48M_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x3fc0)|value<<6) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_48M_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x3fc0) >> 6 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_25M_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x3fc000)|value<<14) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_25M_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x3fc000) >> 14 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_12M_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x3fc00000)|value<<22) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_12M_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x3fc00000) >> 22 +} + +// LP_AON_CLKRST.LP_AONCLKRST_HP_USB_CLKRST_CTRL1: HP USB Clock Reset Control Register. +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_ADP(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x1)|value) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_ADP() uint32 { + return volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x1 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_PHY(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_PHY() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x2) >> 1 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x4)|value<<2) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x4) >> 2 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG11(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x8)|value<<3) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG11() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x8) >> 3 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x10)|value<<4) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_DEVICE() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x10) >> 4 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x30000000)|value<<28) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x30000000) >> 28 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x80000000) >> 31 +} + +// LP_AON_CLKRST.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_SDMMC(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_SDMMC() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_SDMMC(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_SDMMC() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_EMAC(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_EMAC() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_EMAC(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_EMAC() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg) & 0x80000000) >> 31 +} + +// LP_AON_CLKRST.LP_AONCLKRST_DATE: need_des +func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_DATE_LP_AONCLKRST_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LP_AONCLKRST_DATE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_DATE_LP_AONCLKRST_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LP_AONCLKRST_DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power General Purpose Input/Output +type LP_GPIO_Type struct { + CLK_EN volatile.Register32 // 0x0 + VER_DATE volatile.Register32 // 0x4 + OUT volatile.Register32 // 0x8 + OUT_W1TS volatile.Register32 // 0xC + OUT_W1TC volatile.Register32 // 0x10 + ENABLE volatile.Register32 // 0x14 + ENABLE_W1TS volatile.Register32 // 0x18 + ENABLE_W1TC volatile.Register32 // 0x1C + STATUS volatile.Register32 // 0x20 + STATUS_W1TS volatile.Register32 // 0x24 + STATUS_W1TC volatile.Register32 // 0x28 + STATUS_NEXT volatile.Register32 // 0x2C + IN volatile.Register32 // 0x30 + PIN0 volatile.Register32 // 0x34 + PIN1 volatile.Register32 // 0x38 + PIN2 volatile.Register32 // 0x3C + PIN3 volatile.Register32 // 0x40 + PIN4 volatile.Register32 // 0x44 + PIN5 volatile.Register32 // 0x48 + PIN6 volatile.Register32 // 0x4C + PIN7 volatile.Register32 // 0x50 + PIN8 volatile.Register32 // 0x54 + PIN9 volatile.Register32 // 0x58 + PIN10 volatile.Register32 // 0x5C + PIN11 volatile.Register32 // 0x60 + PIN12 volatile.Register32 // 0x64 + PIN13 volatile.Register32 // 0x68 + PIN14 volatile.Register32 // 0x6C + PIN15 volatile.Register32 // 0x70 + FUNC0_IN_SEL_CFG volatile.Register32 // 0x74 + FUNC1_IN_SEL_CFG volatile.Register32 // 0x78 + FUNC2_IN_SEL_CFG volatile.Register32 // 0x7C + FUNC3_IN_SEL_CFG volatile.Register32 // 0x80 + FUNC4_IN_SEL_CFG volatile.Register32 // 0x84 + FUNC5_IN_SEL_CFG volatile.Register32 // 0x88 + FUNC6_IN_SEL_CFG volatile.Register32 // 0x8C + FUNC7_IN_SEL_CFG volatile.Register32 // 0x90 + FUNC8_IN_SEL_CFG volatile.Register32 // 0x94 + FUNC9_IN_SEL_CFG volatile.Register32 // 0x98 + FUNC10_IN_SEL_CFG volatile.Register32 // 0x9C + FUNC11_IN_SEL_CFG volatile.Register32 // 0xA0 + FUNC12_IN_SEL_CFG volatile.Register32 // 0xA4 + FUNC13_IN_SEL_CFG volatile.Register32 // 0xA8 + _ [72]byte + FUNC0_OUT_SEL_CFG volatile.Register32 // 0xF4 + FUNC1_OUT_SEL_CFG volatile.Register32 // 0xF8 + FUNC2_OUT_SEL_CFG volatile.Register32 // 0xFC + FUNC3_OUT_SEL_CFG volatile.Register32 // 0x100 + FUNC4_OUT_SEL_CFG volatile.Register32 // 0x104 + FUNC5_OUT_SEL_CFG volatile.Register32 // 0x108 + FUNC6_OUT_SEL_CFG volatile.Register32 // 0x10C + FUNC7_OUT_SEL_CFG volatile.Register32 // 0x110 + FUNC8_OUT_SEL_CFG volatile.Register32 // 0x114 + FUNC9_OUT_SEL_CFG volatile.Register32 // 0x118 + FUNC10_OUT_SEL_CFG volatile.Register32 // 0x11C + FUNC11_OUT_SEL_CFG volatile.Register32 // 0x120 + FUNC12_OUT_SEL_CFG volatile.Register32 // 0x124 + FUNC13_OUT_SEL_CFG volatile.Register32 // 0x128 + FUNC14_OUT_SEL_CFG volatile.Register32 // 0x12C + FUNC15_OUT_SEL_CFG volatile.Register32 // 0x130 +} + +// LP_GPIO.CLK_EN: Reserved +func (o *LP_GPIO_Type) SetCLK_EN_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetCLK_EN_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1 +} + +// LP_GPIO.VER_DATE: Reserved +func (o *LP_GPIO_Type) SetVER_DATE_REG_VER_DATE(value uint32) { + volatile.StoreUint32(&o.VER_DATE.Reg, volatile.LoadUint32(&o.VER_DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_GPIO_Type) GetVER_DATE_REG_VER_DATE() uint32 { + return volatile.LoadUint32(&o.VER_DATE.Reg) & 0xfffffff +} + +// LP_GPIO.OUT: Reserved +func (o *LP_GPIO_Type) SetOUT_REG_GPIO_OUT_DATA(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, volatile.LoadUint32(&o.OUT.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetOUT_REG_GPIO_OUT_DATA() uint32 { + return volatile.LoadUint32(&o.OUT.Reg) & 0xffff +} + +// LP_GPIO.OUT_W1TS: Reserved +func (o *LP_GPIO_Type) SetOUT_W1TS_REG_GPIO_OUT_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, volatile.LoadUint32(&o.OUT_W1TS.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetOUT_W1TS_REG_GPIO_OUT_DATA_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_W1TS.Reg) & 0xffff +} + +// LP_GPIO.OUT_W1TC: Reserved +func (o *LP_GPIO_Type) SetOUT_W1TC_REG_GPIO_OUT_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, volatile.LoadUint32(&o.OUT_W1TC.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetOUT_W1TC_REG_GPIO_OUT_DATA_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_W1TC.Reg) & 0xffff +} + +// LP_GPIO.ENABLE: Reserved +func (o *LP_GPIO_Type) SetENABLE_REG_GPIO_ENABLE_DATA(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, volatile.LoadUint32(&o.ENABLE.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetENABLE_REG_GPIO_ENABLE_DATA() uint32 { + return volatile.LoadUint32(&o.ENABLE.Reg) & 0xffff +} + +// LP_GPIO.ENABLE_W1TS: Reserved +func (o *LP_GPIO_Type) SetENABLE_W1TS_REG_GPIO_ENABLE_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, volatile.LoadUint32(&o.ENABLE_W1TS.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetENABLE_W1TS_REG_GPIO_ENABLE_DATA_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) & 0xffff +} + +// LP_GPIO.ENABLE_W1TC: Reserved +func (o *LP_GPIO_Type) SetENABLE_W1TC_REG_GPIO_ENABLE_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, volatile.LoadUint32(&o.ENABLE_W1TC.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetENABLE_W1TC_REG_GPIO_ENABLE_DATA_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) & 0xffff +} + +// LP_GPIO.STATUS: Reserved +func (o *LP_GPIO_Type) SetSTATUS_REG_GPIO_STATUS_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetSTATUS_REG_GPIO_STATUS_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xffff +} + +// LP_GPIO.STATUS_W1TS: Reserved +func (o *LP_GPIO_Type) SetSTATUS_W1TS_REG_GPIO_STATUS_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, volatile.LoadUint32(&o.STATUS_W1TS.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetSTATUS_W1TS_REG_GPIO_STATUS_DATA_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) & 0xffff +} + +// LP_GPIO.STATUS_W1TC: Reserved +func (o *LP_GPIO_Type) SetSTATUS_W1TC_REG_GPIO_STATUS_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, volatile.LoadUint32(&o.STATUS_W1TC.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetSTATUS_W1TC_REG_GPIO_STATUS_DATA_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) & 0xffff +} + +// LP_GPIO.STATUS_NEXT: Reserved +func (o *LP_GPIO_Type) SetSTATUS_NEXT_REG_GPIO_STATUS_INTERRUPT_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT.Reg, volatile.LoadUint32(&o.STATUS_NEXT.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetSTATUS_NEXT_REG_GPIO_STATUS_INTERRUPT_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT.Reg) & 0xffff +} + +// LP_GPIO.IN: Reserved +func (o *LP_GPIO_Type) SetIN_REG_GPIO_IN_DATA_NEXT(value uint32) { + volatile.StoreUint32(&o.IN.Reg, volatile.LoadUint32(&o.IN.Reg)&^(0xffff)|value) +} +func (o *LP_GPIO_Type) GetIN_REG_GPIO_IN_DATA_NEXT() uint32 { + return volatile.LoadUint32(&o.IN.Reg) & 0xffff +} + +// LP_GPIO.PIN0: Reserved +func (o *LP_GPIO_Type) SetPIN0_REG_GPIO_PIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN0_REG_GPIO_PIN0_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN0_REG_GPIO_PIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN0_REG_GPIO_PIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN0_REG_GPIO_PIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN0_REG_GPIO_PIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN0_REG_GPIO_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN0_REG_GPIO_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN1: Reserved +func (o *LP_GPIO_Type) SetPIN1_REG_GPIO_PIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN1_REG_GPIO_PIN1_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN1_REG_GPIO_PIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN1_REG_GPIO_PIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN1_REG_GPIO_PIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN1_REG_GPIO_PIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN1_REG_GPI1_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN1_REG_GPI1_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN2: Reserved +func (o *LP_GPIO_Type) SetPIN2_REG_GPIO_PIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN2_REG_GPIO_PIN2_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN2_REG_GPIO_PIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN2_REG_GPIO_PIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN2_REG_GPIO_PIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN2_REG_GPIO_PIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN2_REG_GPI2_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN2_REG_GPI2_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN3: Reserved +func (o *LP_GPIO_Type) SetPIN3_REG_GPIO_PIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN3_REG_GPIO_PIN3_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN3_REG_GPIO_PIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN3_REG_GPIO_PIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN3_REG_GPIO_PIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN3_REG_GPIO_PIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN3_REG_GPI3_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN3_REG_GPI3_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN4: Reserved +func (o *LP_GPIO_Type) SetPIN4_REG_GPIO_PIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN4_REG_GPIO_PIN4_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN4_REG_GPIO_PIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN4_REG_GPIO_PIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN4_REG_GPIO_PIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN4_REG_GPIO_PIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN4_REG_GPI4_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN4_REG_GPI4_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN5: Reserved +func (o *LP_GPIO_Type) SetPIN5_REG_GPIO_PIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN5_REG_GPIO_PIN5_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN5_REG_GPIO_PIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN5_REG_GPIO_PIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN5_REG_GPIO_PIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN5_REG_GPIO_PIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN5_REG_GPI5_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN5_REG_GPI5_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN6: Reserved +func (o *LP_GPIO_Type) SetPIN6_REG_GPIO_PIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN6_REG_GPIO_PIN6_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN6_REG_GPIO_PIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN6_REG_GPIO_PIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN6_REG_GPIO_PIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN6_REG_GPIO_PIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN6_REG_GPI6_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN6_REG_GPI6_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN7: Reserved +func (o *LP_GPIO_Type) SetPIN7_REG_GPIO_PIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN7_REG_GPIO_PIN7_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN7_REG_GPIO_PIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN7_REG_GPIO_PIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN7_REG_GPIO_PIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN7_REG_GPIO_PIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN7_REG_GPI7_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN7_REG_GPI7_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN8: Reserved +func (o *LP_GPIO_Type) SetPIN8_REG_GPIO_PIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN8_REG_GPIO_PIN8_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN8.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN8_REG_GPIO_PIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN8_REG_GPIO_PIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN8_REG_GPIO_PIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN8_REG_GPIO_PIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN8_REG_GPI8_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN8_REG_GPI8_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN9: Reserved +func (o *LP_GPIO_Type) SetPIN9_REG_GPIO_PIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN9_REG_GPIO_PIN9_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN9.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN9_REG_GPIO_PIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN9_REG_GPIO_PIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN9_REG_GPIO_PIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN9_REG_GPIO_PIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN9_REG_GPI9_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN9_REG_GPI9_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN10: Reserved +func (o *LP_GPIO_Type) SetPIN10_REG_GPIO_PIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN10_REG_GPIO_PIN10_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN10.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN10_REG_GPIO_PIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN10_REG_GPIO_PIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN10_REG_GPIO_PIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN10_REG_GPIO_PIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN10_REG_GPI10_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN10_REG_GPI10_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN11: Reserved +func (o *LP_GPIO_Type) SetPIN11_REG_GPIO_PIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN11_REG_GPIO_PIN11_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN11.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN11_REG_GPIO_PIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN11_REG_GPIO_PIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN11_REG_GPIO_PIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN11_REG_GPIO_PIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN11_REG_GPI11_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN11_REG_GPI11_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN12: Reserved +func (o *LP_GPIO_Type) SetPIN12_REG_GPIO_PIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN12_REG_GPIO_PIN12_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN12.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN12_REG_GPIO_PIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN12_REG_GPIO_PIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN12_REG_GPIO_PIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN12_REG_GPIO_PIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN12_REG_GPI12_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN12_REG_GPI12_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN13: Reserved +func (o *LP_GPIO_Type) SetPIN13_REG_GPIO_PIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN13_REG_GPIO_PIN13_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN13.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN13_REG_GPIO_PIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN13_REG_GPIO_PIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN13_REG_GPIO_PIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN13_REG_GPIO_PIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN13_REG_GPI13_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN13_REG_GPI13_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN14: Reserved +func (o *LP_GPIO_Type) SetPIN14_REG_GPIO_PIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN14_REG_GPIO_PIN14_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN14.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN14_REG_GPIO_PIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN14_REG_GPIO_PIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN14_REG_GPIO_PIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN14_REG_GPIO_PIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN14_REG_GPI14_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN14_REG_GPI14_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x20) >> 5 +} + +// LP_GPIO.PIN15: Reserved +func (o *LP_GPIO_Type) SetPIN15_REG_GPIO_PIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetPIN15_REG_GPIO_PIN15_WAKEUP_ENABLE() uint32 { + return volatile.LoadUint32(&o.PIN15.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetPIN15_REG_GPIO_PIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0xe)|value<<1) +} +func (o *LP_GPIO_Type) GetPIN15_REG_GPIO_PIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0xe) >> 1 +} +func (o *LP_GPIO_Type) SetPIN15_REG_GPIO_PIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x10)|value<<4) +} +func (o *LP_GPIO_Type) GetPIN15_REG_GPIO_PIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x10) >> 4 +} +func (o *LP_GPIO_Type) SetPIN15_REG_GPI15_PIN0_EDGE_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x20)|value<<5) +} +func (o *LP_GPIO_Type) GetPIN15_REG_GPI15_PIN0_EDGE_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x20) >> 5 +} + +// LP_GPIO.FUNC0_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC0_IN_SEL_CFG_REG_GPIO_SIG0_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC0_IN_SEL_CFG_REG_GPIO_SIG0_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC1_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC1_IN_SEL_CFG_REG_GPIO_SIG1_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC1_IN_SEL_CFG_REG_GPIO_SIG1_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC2_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC2_IN_SEL_CFG_REG_GPIO_SIG2_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC2_IN_SEL_CFG_REG_GPIO_SIG2_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC3_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC3_IN_SEL_CFG_REG_GPIO_SIG3_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC3_IN_SEL_CFG_REG_GPIO_SIG3_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC4_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC4_IN_SEL_CFG_REG_GPIO_SIG4_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC4_IN_SEL_CFG_REG_GPIO_SIG4_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC5_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC5_IN_SEL_CFG_REG_GPIO_SIG5_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC5_IN_SEL_CFG_REG_GPIO_SIG5_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC6_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC6_IN_SEL_CFG_REG_GPIO_SIG6_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC6_IN_SEL_CFG_REG_GPIO_SIG6_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC7_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC7_IN_SEL_CFG_REG_GPIO_SIG7_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC7_IN_SEL_CFG_REG_GPIO_SIG7_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC8_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC8_IN_SEL_CFG_REG_GPIO_SIG8_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC8_IN_SEL_CFG_REG_GPIO_SIG8_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC9_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC9_IN_SEL_CFG_REG_GPIO_SIG9_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC9_IN_SEL_CFG_REG_GPIO_SIG9_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC10_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC10_IN_SEL_CFG_REG_GPIO_SIG10_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC10_IN_SEL_CFG_REG_GPIO_SIG10_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC11_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC11_IN_SEL_CFG_REG_GPIO_SIG11_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC11_IN_SEL_CFG_REG_GPIO_SIG11_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC12_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC12_IN_SEL_CFG_REG_GPIO_SIG12_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC12_IN_SEL_CFG_REG_GPIO_SIG12_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC13_IN_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC13_IN_SEL_CFG_REG_GPIO_SIG13_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC13_IN_SEL_CFG_REG_GPIO_SIG13_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0xfc)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0xfc) >> 2 +} + +// LP_GPIO.FUNC0_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC1_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC2_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC3_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC4_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC5_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC6_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC7_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC8_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC9_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC10_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC11_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC12_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC13_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC14_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// LP_GPIO.FUNC15_OUT_SEL_CFG: Reserved +func (o *LP_GPIO_Type) SetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x1)|value) +} +func (o *LP_GPIO_Type) GetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_INV_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x1 +} +func (o *LP_GPIO_Type) SetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x2)|value<<1) +} +func (o *LP_GPIO_Type) GetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x2) >> 1 +} +func (o *LP_GPIO_Type) SetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x4)|value<<2) +} +func (o *LP_GPIO_Type) GetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x4) >> 2 +} +func (o *LP_GPIO_Type) SetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3) +} +func (o *LP_GPIO_Type) GetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x1f8) >> 3 +} + +// Low-power I2C (Inter-Integrated Circuit) Controller 0 +type LP_I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + _ [4]byte + FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + FILTER_CFG volatile.Register32 // 0x50 + CLK_CONF volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + SCL_ST_TIME_OUT volatile.Register32 // 0x78 + SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C + SCL_SP_CONF volatile.Register32 // 0x80 + _ [116]byte + DATE volatile.Register32 // 0xF8 + _ [4]byte + TXFIFO_START_ADDR volatile.Register32 // 0x100 + _ [124]byte + RXFIFO_START_ADDR volatile.Register32 // 0x180 +} + +// LP_I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL Clock +func (o *LP_I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff +} + +// LP_I2C.CTR: Transmission setting +func (o *LP_I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *LP_I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *LP_I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *LP_I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *LP_I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3 +} +func (o *LP_I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *LP_I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *LP_I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *LP_I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} +func (o *LP_I2C_Type) SetCTR_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C_Type) GetCTR_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9 +} +func (o *LP_I2C_Type) SetCTR_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C_Type) GetCTR_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10 +} +func (o *LP_I2C_Type) SetCTR_CONF_UPGATE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C_Type) GetCTR_CONF_UPGATE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11 +} + +// LP_I2C.SR: Describe I2C work status. +func (o *LP_I2C_Type) SetSR_RESP_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *LP_I2C_Type) GetSR_RESP_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *LP_I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *LP_I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *LP_I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1f00)|value<<8) +} +func (o *LP_I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x1f00) >> 8 +} +func (o *LP_I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7c0000)|value<<18) +} +func (o *LP_I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7c0000) >> 18 +} +func (o *LP_I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *LP_I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *LP_I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *LP_I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// LP_I2C.TO: Setting time out control for receiving data. +func (o *LP_I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value) +} +func (o *LP_I2C_Type) GetTO_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0x1f +} +func (o *LP_I2C_Type) SetTO_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C_Type) GetTO_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5 +} + +// LP_I2C.FIFO_ST: FIFO status register. +func (o *LP_I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf)|value) +} +func (o *LP_I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 { + return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf +} +func (o *LP_I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1e0)|value<<5) +} +func (o *LP_I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1e0) >> 5 +} +func (o *LP_I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3c00)|value<<10) +} +func (o *LP_I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3c00) >> 10 +} +func (o *LP_I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x78000)|value<<15) +} +func (o *LP_I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x78000) >> 15 +} + +// LP_I2C.FIFO_CONF: FIFO configuration register. +func (o *LP_I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xf)|value) +} +func (o *LP_I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xf +} +func (o *LP_I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1e0)|value<<5) +} +func (o *LP_I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1e0) >> 5 +} +func (o *LP_I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *LP_I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14 +} + +// LP_I2C.DATA: Rx FIFO read data. +func (o *LP_I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *LP_I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// LP_I2C.INT_RAW: Raw interrupt status +func (o *LP_I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LP_I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LP_I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LP_I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LP_I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LP_I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LP_I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LP_I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LP_I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LP_I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LP_I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LP_I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LP_I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LP_I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LP_I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LP_I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} + +// LP_I2C.INT_CLR: Interrupt clear bits +func (o *LP_I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LP_I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LP_I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LP_I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LP_I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LP_I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LP_I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LP_I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LP_I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LP_I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LP_I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LP_I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LP_I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LP_I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LP_I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LP_I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} + +// LP_I2C.INT_ENA: Interrupt enable bits +func (o *LP_I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LP_I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LP_I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LP_I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LP_I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LP_I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LP_I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LP_I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LP_I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LP_I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LP_I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LP_I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LP_I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LP_I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LP_I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LP_I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} + +// LP_I2C.INT_STATUS: Status of captured I2C communication events +func (o *LP_I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *LP_I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *LP_I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *LP_I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *LP_I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *LP_I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *LP_I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *LP_I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *LP_I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *LP_I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *LP_I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *LP_I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *LP_I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *LP_I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *LP_I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *LP_I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *LP_I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *LP_I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *LP_I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *LP_I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *LP_I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15 +} + +// LP_I2C.SDA_HOLD: Configures the hold time after a negative SCL edge. +func (o *LP_I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff +} + +// LP_I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge. +func (o *LP_I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff +} + +// LP_I2C.SCL_HIGH_PERIOD: Configures the high level width of SCL +func (o *LP_I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff +} +func (o *LP_I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9) +} +func (o *LP_I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9 +} + +// LP_I2C.SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition +func (o *LP_I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff +} + +// LP_I2C.SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA +func (o *LP_I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// LP_I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition +func (o *LP_I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff +} + +// LP_I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition +func (o *LP_I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *LP_I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff +} + +// LP_I2C.FILTER_CFG: SCL and SDA filter configuration register +func (o *LP_I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *LP_I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf +} +func (o *LP_I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *LP_I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4 +} +func (o *LP_I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8 +} +func (o *LP_I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9 +} + +// LP_I2C.CLK_CONF: I2C CLK configuration register +func (o *LP_I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value) +} +func (o *LP_I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff +} +func (o *LP_I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *LP_I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8 +} +func (o *LP_I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *LP_I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14 +} +func (o *LP_I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *LP_I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *LP_I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *LP_I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} + +// LP_I2C.COMD0: I2C command register 0 +func (o *LP_I2C_Type) SetCOMD0_COMMAND0(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C_Type) GetCOMD0_COMMAND0() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *LP_I2C_Type) SetCOMD0_COMMAND0_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C_Type) GetCOMD0_COMMAND0_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// LP_I2C.COMD1: I2C command register 1 +func (o *LP_I2C_Type) SetCOMD1_COMMAND1(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C_Type) GetCOMD1_COMMAND1() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *LP_I2C_Type) SetCOMD1_COMMAND1_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C_Type) GetCOMD1_COMMAND1_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// LP_I2C.COMD2: I2C command register 2 +func (o *LP_I2C_Type) SetCOMD2_COMMAND2(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C_Type) GetCOMD2_COMMAND2() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *LP_I2C_Type) SetCOMD2_COMMAND2_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C_Type) GetCOMD2_COMMAND2_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// LP_I2C.COMD3: I2C command register 3 +func (o *LP_I2C_Type) SetCOMD3_COMMAND3(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C_Type) GetCOMD3_COMMAND3() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *LP_I2C_Type) SetCOMD3_COMMAND3_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C_Type) GetCOMD3_COMMAND3_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// LP_I2C.COMD4: I2C command register 4 +func (o *LP_I2C_Type) SetCOMD4_COMMAND4(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C_Type) GetCOMD4_COMMAND4() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *LP_I2C_Type) SetCOMD4_COMMAND4_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C_Type) GetCOMD4_COMMAND4_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// LP_I2C.COMD5: I2C command register 5 +func (o *LP_I2C_Type) SetCOMD5_COMMAND5(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C_Type) GetCOMD5_COMMAND5() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *LP_I2C_Type) SetCOMD5_COMMAND5_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C_Type) GetCOMD5_COMMAND5_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// LP_I2C.COMD6: I2C command register 6 +func (o *LP_I2C_Type) SetCOMD6_COMMAND6(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C_Type) GetCOMD6_COMMAND6() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *LP_I2C_Type) SetCOMD6_COMMAND6_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C_Type) GetCOMD6_COMMAND6_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// LP_I2C.COMD7: I2C command register 7 +func (o *LP_I2C_Type) SetCOMD7_COMMAND7(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *LP_I2C_Type) GetCOMD7_COMMAND7() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *LP_I2C_Type) SetCOMD7_COMMAND7_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2C_Type) GetCOMD7_COMMAND7_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// LP_I2C.SCL_ST_TIME_OUT: SCL status time out register +func (o *LP_I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *LP_I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f +} + +// LP_I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register +func (o *LP_I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *LP_I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f +} + +// LP_I2C.SCL_SP_CONF: Power configuration register +func (o *LP_I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *LP_I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1 +} +func (o *LP_I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *LP_I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *LP_I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *LP_I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *LP_I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// LP_I2C.DATE: Version register +func (o *LP_I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *LP_I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// LP_I2C.TXFIFO_START_ADDR: I2C TXFIFO base address register +func (o *LP_I2C_Type) SetTXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value) +} +func (o *LP_I2C_Type) GetTXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg) +} + +// LP_I2C.RXFIFO_START_ADDR: I2C RXFIFO base address register +func (o *LP_I2C_Type) SetRXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value) +} +func (o *LP_I2C_Type) GetRXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg) +} + +// Low-power I2S (Inter-IC Sound) Controller 0 +type LP_I2S_Type struct { + VAD_CONF volatile.Register32 // 0x0 + VAD_RESULT volatile.Register32 // 0x4 + RX_MEM_CONF volatile.Register32 // 0x8 + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + _ [4]byte + RX_CONF volatile.Register32 // 0x20 + _ [4]byte + RX_CONF1 volatile.Register32 // 0x28 + _ [36]byte + RX_TDM_CTRL volatile.Register32 // 0x50 + _ [4]byte + RX_TIMING volatile.Register32 // 0x58 + _ [4]byte + LC_HUNG_CONF volatile.Register32 // 0x60 + RXEOF_NUM volatile.Register32 // 0x64 + CONF_SIGLE_DATA volatile.Register32 // 0x68 + _ [4]byte + RX_PDM_CONF volatile.Register32 // 0x70 + ECO_LOW volatile.Register32 // 0x74 + ECO_HIGH volatile.Register32 // 0x78 + ECO_CONF volatile.Register32 // 0x7C + VAD_PARAM0 volatile.Register32 // 0x80 + VAD_PARAM1 volatile.Register32 // 0x84 + VAD_PARAM2 volatile.Register32 // 0x88 + VAD_PARAM3 volatile.Register32 // 0x8C + VAD_PARAM4 volatile.Register32 // 0x90 + VAD_PARAM5 volatile.Register32 // 0x94 + VAD_PARAM6 volatile.Register32 // 0x98 + VAD_PARAM7 volatile.Register32 // 0x9C + VAD_PARAM8 volatile.Register32 // 0xA0 + _ [12]byte + VAD_OB0 volatile.Register32 // 0xB0 + VAD_OB1 volatile.Register32 // 0xB4 + VAD_OB2 volatile.Register32 // 0xB8 + VAD_OB3 volatile.Register32 // 0xBC + VAD_OB4 volatile.Register32 // 0xC0 + VAD_OB5 volatile.Register32 // 0xC4 + VAD_OB6 volatile.Register32 // 0xC8 + VAD_OB7 volatile.Register32 // 0xCC + VAD_OB8 volatile.Register32 // 0xD0 + _ [36]byte + CLK_GATE volatile.Register32 // 0xF8 + DATE volatile.Register32 // 0xFC +} + +// LP_I2S.VAD_CONF: I2S VAD Configure register +func (o *LP_I2S_Type) SetVAD_CONF_VAD_EN(value uint32) { + volatile.StoreUint32(&o.VAD_CONF.Reg, volatile.LoadUint32(&o.VAD_CONF.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetVAD_CONF_VAD_EN() uint32 { + return volatile.LoadUint32(&o.VAD_CONF.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetVAD_CONF_VAD_RESET(value uint32) { + volatile.StoreUint32(&o.VAD_CONF.Reg, volatile.LoadUint32(&o.VAD_CONF.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetVAD_CONF_VAD_RESET() uint32 { + return (volatile.LoadUint32(&o.VAD_CONF.Reg) & 0x2) >> 1 +} +func (o *LP_I2S_Type) SetVAD_CONF_VAD_FORCE_START(value uint32) { + volatile.StoreUint32(&o.VAD_CONF.Reg, volatile.LoadUint32(&o.VAD_CONF.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2S_Type) GetVAD_CONF_VAD_FORCE_START() uint32 { + return (volatile.LoadUint32(&o.VAD_CONF.Reg) & 0x4) >> 2 +} + +// LP_I2S.VAD_RESULT: I2S VAD Result register +func (o *LP_I2S_Type) SetVAD_RESULT_VAD_FLAG(value uint32) { + volatile.StoreUint32(&o.VAD_RESULT.Reg, volatile.LoadUint32(&o.VAD_RESULT.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetVAD_RESULT_VAD_FLAG() uint32 { + return volatile.LoadUint32(&o.VAD_RESULT.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetVAD_RESULT_ENERGY_ENOUGH(value uint32) { + volatile.StoreUint32(&o.VAD_RESULT.Reg, volatile.LoadUint32(&o.VAD_RESULT.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetVAD_RESULT_ENERGY_ENOUGH() uint32 { + return (volatile.LoadUint32(&o.VAD_RESULT.Reg) & 0x2) >> 1 +} + +// LP_I2S.RX_MEM_CONF: I2S VAD Observe register +func (o *LP_I2S_Type) SetRX_MEM_CONF_RX_MEM_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.RX_MEM_CONF.Reg, volatile.LoadUint32(&o.RX_MEM_CONF.Reg)&^(0x1ff)|value) +} +func (o *LP_I2S_Type) GetRX_MEM_CONF_RX_MEM_FIFO_CNT() uint32 { + return volatile.LoadUint32(&o.RX_MEM_CONF.Reg) & 0x1ff +} +func (o *LP_I2S_Type) SetRX_MEM_CONF_RX_MEM_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.RX_MEM_CONF.Reg, volatile.LoadUint32(&o.RX_MEM_CONF.Reg)&^(0x1fe00)|value<<9) +} +func (o *LP_I2S_Type) GetRX_MEM_CONF_RX_MEM_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.RX_MEM_CONF.Reg) & 0x1fe00) >> 9 +} + +// LP_I2S.INT_RAW: I2S interrupt raw register, valid in level. +func (o *LP_I2S_Type) SetINT_RAW_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetINT_RAW_RX_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LP_I2S_Type) SetINT_RAW_RX_FIFOMEM_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2S_Type) GetINT_RAW_RX_FIFOMEM_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LP_I2S_Type) SetINT_RAW_VAD_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2S_Type) GetINT_RAW_VAD_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LP_I2S_Type) SetINT_RAW_VAD_RESET_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2S_Type) GetINT_RAW_VAD_RESET_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LP_I2S_Type) SetINT_RAW_RX_MEM_THRESHOLD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2S_Type) GetINT_RAW_RX_MEM_THRESHOLD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} + +// LP_I2S.INT_ST: I2S interrupt status register. +func (o *LP_I2S_Type) SetINT_ST_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetINT_ST_RX_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LP_I2S_Type) SetINT_ST_RX_FIFOMEM_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2S_Type) GetINT_ST_RX_FIFOMEM_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LP_I2S_Type) SetINT_ST_LP_VAD_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2S_Type) GetINT_ST_LP_VAD_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LP_I2S_Type) SetINT_ST_LP_VAD_RESET_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2S_Type) GetINT_ST_LP_VAD_RESET_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LP_I2S_Type) SetINT_ST_RX_MEM_THRESHOLD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2S_Type) GetINT_ST_RX_MEM_THRESHOLD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} + +// LP_I2S.INT_ENA: I2S interrupt enable register. +func (o *LP_I2S_Type) SetINT_ENA_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetINT_ENA_RX_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LP_I2S_Type) SetINT_ENA_RX_FIFOMEM_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2S_Type) GetINT_ENA_RX_FIFOMEM_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LP_I2S_Type) SetINT_ENA_LP_VAD_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2S_Type) GetINT_ENA_LP_VAD_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LP_I2S_Type) SetINT_ENA_LP_VAD_RESET_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2S_Type) GetINT_ENA_LP_VAD_RESET_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LP_I2S_Type) SetINT_ENA_RX_MEM_THRESHOLD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2S_Type) GetINT_ENA_RX_MEM_THRESHOLD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} + +// LP_I2S.INT_CLR: I2S interrupt clear register. +func (o *LP_I2S_Type) SetINT_CLR_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetINT_CLR_RX_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LP_I2S_Type) SetINT_CLR_RX_FIFOMEM_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2S_Type) GetINT_CLR_RX_FIFOMEM_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LP_I2S_Type) SetINT_CLR_LP_VAD_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2S_Type) GetINT_CLR_LP_VAD_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LP_I2S_Type) SetINT_CLR_LP_VAD_RESET_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2S_Type) GetINT_CLR_LP_VAD_RESET_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LP_I2S_Type) SetINT_CLR_RX_MEM_THRESHOLD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2S_Type) GetINT_CLR_RX_MEM_THRESHOLD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} + +// LP_I2S.RX_CONF: I2S RX configure register +func (o *LP_I2S_Type) SetRX_CONF_RX_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_RESET() uint32 { + return volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2) >> 1 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x4) >> 2 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8) >> 3 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_FIFOMEM_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10)|value<<4) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_FIFOMEM_RESET() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10) >> 4 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_MONO(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_MONO() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20) >> 5 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80) >> 7 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_UPDATE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100) >> 8 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200) >> 9 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0xc00) >> 10 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1000) >> 12 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_STOP_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_STOP_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x6000) >> 13 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8000) >> 15 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10000) >> 16 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20000) >> 17 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40000) >> 18 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80000) >> 19 +} +func (o *LP_I2S_Type) SetRX_CONF_RX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *LP_I2S_Type) GetRX_CONF_RX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100000) >> 20 +} + +// LP_I2S.RX_CONF1: I2S RX configure register 1 +func (o *LP_I2S_Type) SetRX_CONF1_RX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7f)|value) +} +func (o *LP_I2S_Type) GetRX_CONF1_RX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7f +} +func (o *LP_I2S_Type) SetRX_CONF1_RX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *LP_I2S_Type) GetRX_CONF1_RX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *LP_I2S_Type) SetRX_CONF1_RX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x3e000)|value<<13) +} +func (o *LP_I2S_Type) GetRX_CONF1_RX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x3e000) >> 13 +} +func (o *LP_I2S_Type) SetRX_CONF1_RX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0xfc0000)|value<<18) +} +func (o *LP_I2S_Type) GetRX_CONF1_RX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0xfc0000) >> 18 +} +func (o *LP_I2S_Type) SetRX_CONF1_RX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f000000)|value<<24) +} +func (o *LP_I2S_Type) GetRX_CONF1_RX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f000000) >> 24 +} +func (o *LP_I2S_Type) SetRX_CONF1_RX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_I2S_Type) GetRX_CONF1_RX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x20000000) >> 29 +} + +// LP_I2S.RX_TDM_CTRL: I2S TX TDM mode control register +func (o *LP_I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *LP_I2S_Type) SetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *LP_I2S_Type) GetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} + +// LP_I2S.RX_TIMING: I2S RX timing control register +func (o *LP_I2S_Type) SetRX_TIMING_RX_SD_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3)|value) +} +func (o *LP_I2S_Type) GetRX_TIMING_RX_SD_IN_DM() uint32 { + return volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3 +} +func (o *LP_I2S_Type) SetRX_TIMING_RX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *LP_I2S_Type) GetRX_TIMING_RX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *LP_I2S_Type) SetRX_TIMING_RX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *LP_I2S_Type) GetRX_TIMING_RX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *LP_I2S_Type) SetRX_TIMING_RX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *LP_I2S_Type) GetRX_TIMING_RX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *LP_I2S_Type) SetRX_TIMING_RX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *LP_I2S_Type) GetRX_TIMING_RX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000000) >> 28 +} + +// LP_I2S.LC_HUNG_CONF: I2S HUNG configure register. +func (o *LP_I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *LP_I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff +} +func (o *LP_I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *LP_I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *LP_I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *LP_I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11 +} + +// LP_I2S.RXEOF_NUM: I2S RX data number control register. +func (o *LP_I2S_Type) SetRXEOF_NUM_RX_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.RXEOF_NUM.Reg, volatile.LoadUint32(&o.RXEOF_NUM.Reg)&^(0xfff)|value) +} +func (o *LP_I2S_Type) GetRXEOF_NUM_RX_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.RXEOF_NUM.Reg) & 0xfff +} + +// LP_I2S.CONF_SIGLE_DATA: I2S signal data register +func (o *LP_I2S_Type) SetCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value) +} +func (o *LP_I2S_Type) GetCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg) +} + +// LP_I2S.RX_PDM_CONF: I2S RX configure register +func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_PDM2PCM_EN(value uint32) { + volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_PDM2PCM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x80000) >> 19 +} +func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_PDM_SINC_DSR_16_EN(value uint32) { + volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_PDM_SINC_DSR_16_EN() uint32 { + return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x100000) >> 20 +} +func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_PDM2PCM_AMPLIFY_NUM(value uint32) { + volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x1e00000)|value<<21) +} +func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_PDM2PCM_AMPLIFY_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x1e00000) >> 21 +} +func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_PDM_HP_BYPASS(value uint32) { + volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_PDM_HP_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_IIR_HP_MULT12_5(value uint32) { + volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x1c000000)|value<<26) +} +func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_IIR_HP_MULT12_5() uint32 { + return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x1c000000) >> 26 +} +func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_IIR_HP_MULT12_0(value uint32) { + volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0xe0000000)|value<<29) +} +func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_IIR_HP_MULT12_0() uint32 { + return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0xe0000000) >> 29 +} + +// LP_I2S.ECO_LOW: I2S ECO register +func (o *LP_I2S_Type) SetECO_LOW(value uint32) { + volatile.StoreUint32(&o.ECO_LOW.Reg, value) +} +func (o *LP_I2S_Type) GetECO_LOW() uint32 { + return volatile.LoadUint32(&o.ECO_LOW.Reg) +} + +// LP_I2S.ECO_HIGH: I2S ECO register +func (o *LP_I2S_Type) SetECO_HIGH(value uint32) { + volatile.StoreUint32(&o.ECO_HIGH.Reg, value) +} +func (o *LP_I2S_Type) GetECO_HIGH() uint32 { + return volatile.LoadUint32(&o.ECO_HIGH.Reg) +} + +// LP_I2S.ECO_CONF: I2S ECO register +func (o *LP_I2S_Type) SetECO_CONF_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.ECO_CONF.Reg, volatile.LoadUint32(&o.ECO_CONF.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetECO_CONF_RDN_ENA() uint32 { + return volatile.LoadUint32(&o.ECO_CONF.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetECO_CONF_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.ECO_CONF.Reg, volatile.LoadUint32(&o.ECO_CONF.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetECO_CONF_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.ECO_CONF.Reg) & 0x2) >> 1 +} + +// LP_I2S.VAD_PARAM0: I2S VAD Parameter register +func (o *LP_I2S_Type) SetVAD_PARAM0_PARAM_MIN_ENERGY(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM0.Reg, volatile.LoadUint32(&o.VAD_PARAM0.Reg)&^(0xffff)|value) +} +func (o *LP_I2S_Type) GetVAD_PARAM0_PARAM_MIN_ENERGY() uint32 { + return volatile.LoadUint32(&o.VAD_PARAM0.Reg) & 0xffff +} +func (o *LP_I2S_Type) SetVAD_PARAM0_PARAM_INIT_FRAME_NUM(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM0.Reg, volatile.LoadUint32(&o.VAD_PARAM0.Reg)&^(0x1ff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_PARAM0_PARAM_INIT_FRAME_NUM() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM0.Reg) & 0x1ff0000) >> 16 +} + +// LP_I2S.VAD_PARAM1: I2S VAD Parameter register +func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_MIN_SPEECH_COUNT(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0xf)|value) +} +func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_MIN_SPEECH_COUNT() uint32 { + return volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0xf +} +func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_MAX_SPEECH_COUNT(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0x7f0)|value<<4) +} +func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_MAX_SPEECH_COUNT() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0x7f0) >> 4 +} +func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_HANGOVER_SPEECH(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0xf800)|value<<11) +} +func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_HANGOVER_SPEECH() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0xf800) >> 11 +} +func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_HANGOVER_SILENT(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0xff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_HANGOVER_SILENT() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0xff0000) >> 16 +} +func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_MAX_OFFSET(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0x7f000000)|value<<24) +} +func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_MAX_OFFSET() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0x7f000000) >> 24 +} +func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_SKIP_BAND_ENERGY(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_SKIP_BAND_ENERGY() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0x80000000) >> 31 +} + +// LP_I2S.VAD_PARAM2: I2S VAD Parameter register +func (o *LP_I2S_Type) SetVAD_PARAM2_PARAM_NOISE_AMP_DOWN(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM2.Reg, volatile.LoadUint32(&o.VAD_PARAM2.Reg)&^(0xffff)|value) +} +func (o *LP_I2S_Type) GetVAD_PARAM2_PARAM_NOISE_AMP_DOWN() uint32 { + return volatile.LoadUint32(&o.VAD_PARAM2.Reg) & 0xffff +} +func (o *LP_I2S_Type) SetVAD_PARAM2_PARAM_NOISE_AMP_UP(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM2.Reg, volatile.LoadUint32(&o.VAD_PARAM2.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_PARAM2_PARAM_NOISE_AMP_UP() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM2.Reg) & 0xffff0000) >> 16 +} + +// LP_I2S.VAD_PARAM3: I2S VAD Parameter register +func (o *LP_I2S_Type) SetVAD_PARAM3_PARAM_NOISE_SPE_UP0(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM3.Reg, volatile.LoadUint32(&o.VAD_PARAM3.Reg)&^(0xffff)|value) +} +func (o *LP_I2S_Type) GetVAD_PARAM3_PARAM_NOISE_SPE_UP0() uint32 { + return volatile.LoadUint32(&o.VAD_PARAM3.Reg) & 0xffff +} +func (o *LP_I2S_Type) SetVAD_PARAM3_PARAM_NOISE_SPE_UP1(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM3.Reg, volatile.LoadUint32(&o.VAD_PARAM3.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_PARAM3_PARAM_NOISE_SPE_UP1() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM3.Reg) & 0xffff0000) >> 16 +} + +// LP_I2S.VAD_PARAM4: I2S VAD Parameter register +func (o *LP_I2S_Type) SetVAD_PARAM4_PARAM_NOISE_SPE_DOWN(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM4.Reg, volatile.LoadUint32(&o.VAD_PARAM4.Reg)&^(0xffff)|value) +} +func (o *LP_I2S_Type) GetVAD_PARAM4_PARAM_NOISE_SPE_DOWN() uint32 { + return volatile.LoadUint32(&o.VAD_PARAM4.Reg) & 0xffff +} +func (o *LP_I2S_Type) SetVAD_PARAM4_PARAM_NOISE_MEAN_DOWN(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM4.Reg, volatile.LoadUint32(&o.VAD_PARAM4.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_PARAM4_PARAM_NOISE_MEAN_DOWN() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM4.Reg) & 0xffff0000) >> 16 +} + +// LP_I2S.VAD_PARAM5: I2S VAD Parameter register +func (o *LP_I2S_Type) SetVAD_PARAM5_PARAM_NOISE_MEAN_UP0(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM5.Reg, volatile.LoadUint32(&o.VAD_PARAM5.Reg)&^(0xffff)|value) +} +func (o *LP_I2S_Type) GetVAD_PARAM5_PARAM_NOISE_MEAN_UP0() uint32 { + return volatile.LoadUint32(&o.VAD_PARAM5.Reg) & 0xffff +} +func (o *LP_I2S_Type) SetVAD_PARAM5_PARAM_NOISE_MEAN_UP1(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM5.Reg, volatile.LoadUint32(&o.VAD_PARAM5.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_PARAM5_PARAM_NOISE_MEAN_UP1() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM5.Reg) & 0xffff0000) >> 16 +} + +// LP_I2S.VAD_PARAM6: I2S VAD Parameter register +func (o *LP_I2S_Type) SetVAD_PARAM6_PARAM_NOISE_STD_FS_THSL(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM6.Reg, volatile.LoadUint32(&o.VAD_PARAM6.Reg)&^(0xffff)|value) +} +func (o *LP_I2S_Type) GetVAD_PARAM6_PARAM_NOISE_STD_FS_THSL() uint32 { + return volatile.LoadUint32(&o.VAD_PARAM6.Reg) & 0xffff +} +func (o *LP_I2S_Type) SetVAD_PARAM6_PARAM_NOISE_STD_FS_THSH(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM6.Reg, volatile.LoadUint32(&o.VAD_PARAM6.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_PARAM6_PARAM_NOISE_STD_FS_THSH() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM6.Reg) & 0xffff0000) >> 16 +} + +// LP_I2S.VAD_PARAM7: I2S VAD Parameter register +func (o *LP_I2S_Type) SetVAD_PARAM7_PARAM_THRES_UPD_BASE(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM7.Reg, volatile.LoadUint32(&o.VAD_PARAM7.Reg)&^(0xffff)|value) +} +func (o *LP_I2S_Type) GetVAD_PARAM7_PARAM_THRES_UPD_BASE() uint32 { + return volatile.LoadUint32(&o.VAD_PARAM7.Reg) & 0xffff +} +func (o *LP_I2S_Type) SetVAD_PARAM7_PARAM_THRES_UPD_VARY(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM7.Reg, volatile.LoadUint32(&o.VAD_PARAM7.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_PARAM7_PARAM_THRES_UPD_VARY() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM7.Reg) & 0xffff0000) >> 16 +} + +// LP_I2S.VAD_PARAM8: I2S VAD Parameter register +func (o *LP_I2S_Type) SetVAD_PARAM8_PARAM_THRES_UPD_BDL(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM8.Reg, volatile.LoadUint32(&o.VAD_PARAM8.Reg)&^(0xff)|value) +} +func (o *LP_I2S_Type) GetVAD_PARAM8_PARAM_THRES_UPD_BDL() uint32 { + return volatile.LoadUint32(&o.VAD_PARAM8.Reg) & 0xff +} +func (o *LP_I2S_Type) SetVAD_PARAM8_PARAM_THRES_UPD_BDH(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM8.Reg, volatile.LoadUint32(&o.VAD_PARAM8.Reg)&^(0xff00)|value<<8) +} +func (o *LP_I2S_Type) GetVAD_PARAM8_PARAM_THRES_UPD_BDH() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM8.Reg) & 0xff00) >> 8 +} +func (o *LP_I2S_Type) SetVAD_PARAM8_PARAM_FEATURE_BURST(value uint32) { + volatile.StoreUint32(&o.VAD_PARAM8.Reg, volatile.LoadUint32(&o.VAD_PARAM8.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_PARAM8_PARAM_FEATURE_BURST() uint32 { + return (volatile.LoadUint32(&o.VAD_PARAM8.Reg) & 0xffff0000) >> 16 +} + +// LP_I2S.VAD_OB0: I2S VAD Observe register +func (o *LP_I2S_Type) SetVAD_OB0_SPEECH_COUNT_OB(value uint32) { + volatile.StoreUint32(&o.VAD_OB0.Reg, volatile.LoadUint32(&o.VAD_OB0.Reg)&^(0xff)|value) +} +func (o *LP_I2S_Type) GetVAD_OB0_SPEECH_COUNT_OB() uint32 { + return volatile.LoadUint32(&o.VAD_OB0.Reg) & 0xff +} +func (o *LP_I2S_Type) SetVAD_OB0_SILENT_COUNT_OB(value uint32) { + volatile.StoreUint32(&o.VAD_OB0.Reg, volatile.LoadUint32(&o.VAD_OB0.Reg)&^(0xff00)|value<<8) +} +func (o *LP_I2S_Type) GetVAD_OB0_SILENT_COUNT_OB() uint32 { + return (volatile.LoadUint32(&o.VAD_OB0.Reg) & 0xff00) >> 8 +} +func (o *LP_I2S_Type) SetVAD_OB0_MAX_SIGNAL0_OB(value uint32) { + volatile.StoreUint32(&o.VAD_OB0.Reg, volatile.LoadUint32(&o.VAD_OB0.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_OB0_MAX_SIGNAL0_OB() uint32 { + return (volatile.LoadUint32(&o.VAD_OB0.Reg) & 0xffff0000) >> 16 +} + +// LP_I2S.VAD_OB1: I2S VAD Observe register +func (o *LP_I2S_Type) SetVAD_OB1_MAX_SIGNAL1_OB(value uint32) { + volatile.StoreUint32(&o.VAD_OB1.Reg, volatile.LoadUint32(&o.VAD_OB1.Reg)&^(0xffff)|value) +} +func (o *LP_I2S_Type) GetVAD_OB1_MAX_SIGNAL1_OB() uint32 { + return volatile.LoadUint32(&o.VAD_OB1.Reg) & 0xffff +} +func (o *LP_I2S_Type) SetVAD_OB1_MAX_SIGNAL2_OB(value uint32) { + volatile.StoreUint32(&o.VAD_OB1.Reg, volatile.LoadUint32(&o.VAD_OB1.Reg)&^(0xffff0000)|value<<16) +} +func (o *LP_I2S_Type) GetVAD_OB1_MAX_SIGNAL2_OB() uint32 { + return (volatile.LoadUint32(&o.VAD_OB1.Reg) & 0xffff0000) >> 16 +} + +// LP_I2S.VAD_OB2: I2S VAD Observe register +func (o *LP_I2S_Type) SetVAD_OB2(value uint32) { + volatile.StoreUint32(&o.VAD_OB2.Reg, value) +} +func (o *LP_I2S_Type) GetVAD_OB2() uint32 { + return volatile.LoadUint32(&o.VAD_OB2.Reg) +} + +// LP_I2S.VAD_OB3: I2S VAD Observe register +func (o *LP_I2S_Type) SetVAD_OB3(value uint32) { + volatile.StoreUint32(&o.VAD_OB3.Reg, value) +} +func (o *LP_I2S_Type) GetVAD_OB3() uint32 { + return volatile.LoadUint32(&o.VAD_OB3.Reg) +} + +// LP_I2S.VAD_OB4: I2S VAD Observe register +func (o *LP_I2S_Type) SetVAD_OB4(value uint32) { + volatile.StoreUint32(&o.VAD_OB4.Reg, value) +} +func (o *LP_I2S_Type) GetVAD_OB4() uint32 { + return volatile.LoadUint32(&o.VAD_OB4.Reg) +} + +// LP_I2S.VAD_OB5: I2S VAD Observe register +func (o *LP_I2S_Type) SetVAD_OB5(value uint32) { + volatile.StoreUint32(&o.VAD_OB5.Reg, value) +} +func (o *LP_I2S_Type) GetVAD_OB5() uint32 { + return volatile.LoadUint32(&o.VAD_OB5.Reg) +} + +// LP_I2S.VAD_OB6: I2S VAD Observe register +func (o *LP_I2S_Type) SetVAD_OB6(value uint32) { + volatile.StoreUint32(&o.VAD_OB6.Reg, value) +} +func (o *LP_I2S_Type) GetVAD_OB6() uint32 { + return volatile.LoadUint32(&o.VAD_OB6.Reg) +} + +// LP_I2S.VAD_OB7: I2S VAD Observe register +func (o *LP_I2S_Type) SetVAD_OB7(value uint32) { + volatile.StoreUint32(&o.VAD_OB7.Reg, value) +} +func (o *LP_I2S_Type) GetVAD_OB7() uint32 { + return volatile.LoadUint32(&o.VAD_OB7.Reg) +} + +// LP_I2S.VAD_OB8: I2S VAD Observe register +func (o *LP_I2S_Type) SetVAD_OB8(value uint32) { + volatile.StoreUint32(&o.VAD_OB8.Reg, value) +} +func (o *LP_I2S_Type) GetVAD_OB8() uint32 { + return volatile.LoadUint32(&o.VAD_OB8.Reg) +} + +// LP_I2S.CLK_GATE: Clock gate register +func (o *LP_I2S_Type) SetCLK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x1)|value) +} +func (o *LP_I2S_Type) GetCLK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x1 +} +func (o *LP_I2S_Type) SetCLK_GATE_VAD_CG_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x2)|value<<1) +} +func (o *LP_I2S_Type) GetCLK_GATE_VAD_CG_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x2) >> 1 +} +func (o *LP_I2S_Type) SetCLK_GATE_RX_MEM_CG_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x4)|value<<2) +} +func (o *LP_I2S_Type) GetCLK_GATE_RX_MEM_CG_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x4) >> 2 +} +func (o *LP_I2S_Type) SetCLK_GATE_RX_REG_CG_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x8)|value<<3) +} +func (o *LP_I2S_Type) GetCLK_GATE_RX_REG_CG_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x8) >> 3 +} + +// LP_I2S.DATE: Version control register +func (o *LP_I2S_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_I2S_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power Input/Output Multiplexer +type LP_IOMUX_Type struct { + CLK_EN volatile.Register32 // 0x0 + VER_DATE volatile.Register32 // 0x4 + PAD0 volatile.Register32 // 0x8 + PAD1 volatile.Register32 // 0xC + PAD2 volatile.Register32 // 0x10 + PAD3 volatile.Register32 // 0x14 + PAD4 volatile.Register32 // 0x18 + PAD5 volatile.Register32 // 0x1C + PAD6 volatile.Register32 // 0x20 + PAD7 volatile.Register32 // 0x24 + PAD8 volatile.Register32 // 0x28 + PAD9 volatile.Register32 // 0x2C + PAD10 volatile.Register32 // 0x30 + PAD11 volatile.Register32 // 0x34 + PAD120 volatile.Register32 // 0x38 + PAD13 volatile.Register32 // 0x3C + PAD14 volatile.Register32 // 0x40 + PAD15 volatile.Register32 // 0x44 + EXT_WAKEUP0_SEL volatile.Register32 // 0x48 + LP_PAD_HOLD volatile.Register32 // 0x4C + LP_PAD_HYS volatile.Register32 // 0x50 +} + +// LP_IOMUX.CLK_EN: Reserved +func (o *LP_IOMUX_Type) SetCLK_EN_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value) +} +func (o *LP_IOMUX_Type) GetCLK_EN_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1 +} + +// LP_IOMUX.VER_DATE: Reserved +func (o *LP_IOMUX_Type) SetVER_DATE_REG_VER_DATE(value uint32) { + volatile.StoreUint32(&o.VER_DATE.Reg, volatile.LoadUint32(&o.VER_DATE.Reg)&^(0xfffffff)|value) +} +func (o *LP_IOMUX_Type) GetVER_DATE_REG_VER_DATE() uint32 { + return volatile.LoadUint32(&o.VER_DATE.Reg) & 0xfffffff +} + +// LP_IOMUX.PAD0: Reserved +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_DRV(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_DRV() uint32 { + return volatile.LoadUint32(&o.PAD0.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_RDE(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD0.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_RUE(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD0.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD0.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD0.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD0.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD0.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD0.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD0.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD0.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD1: Reserved +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_DRV(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_DRV() uint32 { + return volatile.LoadUint32(&o.PAD1.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_RDE(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD1.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_RUE(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD1.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD1.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD1.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD1.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD1.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD1.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD1.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD1.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD2: Reserved +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_DRV(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_DRV() uint32 { + return volatile.LoadUint32(&o.PAD2.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_RDE(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD2.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_RUE(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD2.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD2.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD2.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD2.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD2.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD2.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD2.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD2.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD3: Reserved +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_DRV(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_DRV() uint32 { + return volatile.LoadUint32(&o.PAD3.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_RDE(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD3.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_RUE(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD3.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD3.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD3.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD3.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD3.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD3.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD3.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD3.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD4: Reserved +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_DRV(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_DRV() uint32 { + return volatile.LoadUint32(&o.PAD4.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_RDE(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD4.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_RUE(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD4.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD4.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD4.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD4.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD4.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD4.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD4.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD4.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD5: Reserved +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_DRV(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_DRV() uint32 { + return volatile.LoadUint32(&o.PAD5.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_RDE(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD5.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_RUE(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD5.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD5.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD5.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD5.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD5.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD5.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD5.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD5.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD6: Reserved +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_DRV(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_DRV() uint32 { + return volatile.LoadUint32(&o.PAD6.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_RDE(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD6.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_RUE(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD6.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD6.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD6.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD6.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD6.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD6.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD6.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD6.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD7: Reserved +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_DRV(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_DRV() uint32 { + return volatile.LoadUint32(&o.PAD7.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_RDE(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD7.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_RUE(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD7.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD7.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD7.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD7.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD7.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD7.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD7.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD7.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD8: Reserved +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_DRV(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_DRV() uint32 { + return volatile.LoadUint32(&o.PAD8.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_RDE(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD8.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_RUE(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD8.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD8.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD8.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD8.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD8.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD8.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD8.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD8.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD9: Reserved +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_DRV(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_DRV() uint32 { + return volatile.LoadUint32(&o.PAD9.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_RDE(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD9.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_RUE(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD9.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD9.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD9.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD9.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD9.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD9.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD9.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD9.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD10: Reserved +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_DRV(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_DRV() uint32 { + return volatile.LoadUint32(&o.PAD10.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_RDE(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD10.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_RUE(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD10.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD10.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD10.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD10.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD10.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD10.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD10.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD10.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD11: Reserved +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_DRV(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_DRV() uint32 { + return volatile.LoadUint32(&o.PAD11.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_RDE(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD11.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_RUE(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD11.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD11.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD11.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD11.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD11.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD11.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD11.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD11.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD120: Reserved +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_DRV(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_DRV() uint32 { + return volatile.LoadUint32(&o.PAD120.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_RDE(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD120.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_RUE(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD120.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD120.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD120.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD120.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD120.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD120.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD120.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD120.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD13: Reserved +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_DRV(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_DRV() uint32 { + return volatile.LoadUint32(&o.PAD13.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_RDE(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD13.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_RUE(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD13.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD13.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD13.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD13.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD13.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD13.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD13.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD13.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD14: Reserved +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_DRV(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_DRV() uint32 { + return volatile.LoadUint32(&o.PAD14.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_RDE(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD14.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_RUE(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD14.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD14.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD14.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD14.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD14.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD14.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD14.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD14.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.PAD15: Reserved +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_DRV(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x3)|value) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_DRV() uint32 { + return volatile.LoadUint32(&o.PAD15.Reg) & 0x3 +} +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_RDE(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x4)|value<<2) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD15.Reg) & 0x4) >> 2 +} +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_RUE(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x8)|value<<3) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD15.Reg) & 0x8) >> 3 +} +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x10)|value<<4) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD15.Reg) & 0x10) >> 4 +} +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x60)|value<<5) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD15.Reg) & 0x60) >> 5 +} +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x80)|value<<7) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD15.Reg) & 0x80) >> 7 +} +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x100)|value<<8) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD15.Reg) & 0x100) >> 8 +} +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x200)|value<<9) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD15.Reg) & 0x200) >> 9 +} +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x400)|value<<10) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD15.Reg) & 0x400) >> 10 +} +func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x800)|value<<11) +} +func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.PAD15.Reg) & 0x800) >> 11 +} + +// LP_IOMUX.EXT_WAKEUP0_SEL: Reserved +func (o *LP_IOMUX_Type) SetEXT_WAKEUP0_SEL_REG_XTL_EXT_CTR_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP0_SEL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP0_SEL.Reg)&^(0x1f)|value) +} +func (o *LP_IOMUX_Type) GetEXT_WAKEUP0_SEL_REG_XTL_EXT_CTR_SEL() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP0_SEL.Reg) & 0x1f +} +func (o *LP_IOMUX_Type) SetEXT_WAKEUP0_SEL_REG_EXT_WAKEUP0_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP0_SEL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP0_SEL.Reg)&^(0x3e0)|value<<5) +} +func (o *LP_IOMUX_Type) GetEXT_WAKEUP0_SEL_REG_EXT_WAKEUP0_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP0_SEL.Reg) & 0x3e0) >> 5 +} + +// LP_IOMUX.LP_PAD_HOLD: Reserved +func (o *LP_IOMUX_Type) SetLP_PAD_HOLD_REG_LP_GPIO_HOLD(value uint32) { + volatile.StoreUint32(&o.LP_PAD_HOLD.Reg, volatile.LoadUint32(&o.LP_PAD_HOLD.Reg)&^(0xffff)|value) +} +func (o *LP_IOMUX_Type) GetLP_PAD_HOLD_REG_LP_GPIO_HOLD() uint32 { + return volatile.LoadUint32(&o.LP_PAD_HOLD.Reg) & 0xffff +} + +// LP_IOMUX.LP_PAD_HYS: Reserved +func (o *LP_IOMUX_Type) SetLP_PAD_HYS_REG_LP_GPIO_HYS(value uint32) { + volatile.StoreUint32(&o.LP_PAD_HYS.Reg, volatile.LoadUint32(&o.LP_PAD_HYS.Reg)&^(0xffff)|value) +} +func (o *LP_IOMUX_Type) GetLP_PAD_HYS_REG_LP_GPIO_HYS() uint32 { + return volatile.LoadUint32(&o.LP_PAD_HYS.Reg) & 0xffff +} + +// Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller +type LP_UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV_SYNC volatile.Register32 // 0x14 + RX_FILT volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0_SYNC volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + _ [4]byte + HWFC_CONF_SYNC volatile.Register32 // 0x2C + SLEEP_CONF0 volatile.Register32 // 0x30 + SLEEP_CONF1 volatile.Register32 // 0x34 + SLEEP_CONF2 volatile.Register32 // 0x38 + SWFC_CONF0_SYNC volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + TXBRK_CONF_SYNC volatile.Register32 // 0x44 + IDLE_CONF_SYNC volatile.Register32 // 0x48 + RS485_CONF_SYNC volatile.Register32 // 0x4C + AT_CMD_PRECNT_SYNC volatile.Register32 // 0x50 + AT_CMD_POSTCNT_SYNC volatile.Register32 // 0x54 + AT_CMD_GAPTOUT_SYNC volatile.Register32 // 0x58 + AT_CMD_CHAR_SYNC volatile.Register32 // 0x5C + MEM_CONF volatile.Register32 // 0x60 + TOUT_CONF_SYNC volatile.Register32 // 0x64 + MEM_TX_STATUS volatile.Register32 // 0x68 + MEM_RX_STATUS volatile.Register32 // 0x6C + FSM_STATUS volatile.Register32 // 0x70 + _ [20]byte + CLK_CONF volatile.Register32 // 0x88 + DATE volatile.Register32 // 0x8C + AFIFO_STATUS volatile.Register32 // 0x90 + _ [4]byte + REG_UPDATE volatile.Register32 // 0x98 + ID volatile.Register32 // 0x9C +} + +// LP_UART.FIFO: FIFO data register +func (o *LP_UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// LP_UART.INT_RAW: Raw interrupt status +func (o *LP_UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// LP_UART.INT_ST: Masked interrupt status +func (o *LP_UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// LP_UART.INT_ENA: Interrupt enable bits +func (o *LP_UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// LP_UART.INT_CLR: Interrupt clear bits +func (o *LP_UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LP_UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LP_UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LP_UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LP_UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LP_UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LP_UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LP_UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LP_UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LP_UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LP_UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LP_UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LP_UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LP_UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LP_UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LP_UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// LP_UART.CLKDIV_SYNC: Clock divider configuration +func (o *LP_UART_Type) SetCLKDIV_SYNC_CLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xfff)|value) +} +func (o *LP_UART_Type) GetCLKDIV_SYNC_CLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xfff +} +func (o *LP_UART_Type) SetCLKDIV_SYNC_CLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xf00000)|value<<20) +} +func (o *LP_UART_Type) GetCLKDIV_SYNC_CLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xf00000) >> 20 +} + +// LP_UART.RX_FILT: Rx Filter configuration +func (o *LP_UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetRX_FILT_GLITCH_FILT() uint32 { + return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff +} +func (o *LP_UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8 +} + +// LP_UART.STATUS: UART status register +func (o *LP_UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *LP_UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *LP_UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *LP_UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *LP_UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf80000)|value<<19) +} +func (o *LP_UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf80000) >> 19 +} +func (o *LP_UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *LP_UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *LP_UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *LP_UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *LP_UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *LP_UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// LP_UART.CONF0_SYNC: Configuration register 0 +func (o *LP_UART_Type) SetCONF0_SYNC_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetCONF0_SYNC_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1 +} +func (o *LP_UART_Type) SetCONF0_SYNC_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetCONF0_SYNC_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetCONF0_SYNC_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *LP_UART_Type) GetCONF0_SYNC_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0xc) >> 2 +} +func (o *LP_UART_Type) SetCONF0_SYNC_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x30)|value<<4) +} +func (o *LP_UART_Type) GetCONF0_SYNC_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x30) >> 4 +} +func (o *LP_UART_Type) SetCONF0_SYNC_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40)|value<<6) +} +func (o *LP_UART_Type) GetCONF0_SYNC_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40) >> 6 +} +func (o *LP_UART_Type) SetCONF0_SYNC_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1000)|value<<12) +} +func (o *LP_UART_Type) GetCONF0_SYNC_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1000) >> 12 +} +func (o *LP_UART_Type) SetCONF0_SYNC_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2000)|value<<13) +} +func (o *LP_UART_Type) GetCONF0_SYNC_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2000) >> 13 +} +func (o *LP_UART_Type) SetCONF0_SYNC_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x8000)|value<<15) +} +func (o *LP_UART_Type) GetCONF0_SYNC_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x8000) >> 15 +} +func (o *LP_UART_Type) SetCONF0_SYNC_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x10000)|value<<16) +} +func (o *LP_UART_Type) GetCONF0_SYNC_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x10000) >> 16 +} +func (o *LP_UART_Type) SetCONF0_SYNC_DIS_RX_DAT_OVF(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x20000)|value<<17) +} +func (o *LP_UART_Type) GetCONF0_SYNC_DIS_RX_DAT_OVF() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x20000) >> 17 +} +func (o *LP_UART_Type) SetCONF0_SYNC_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetCONF0_SYNC_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetCONF0_SYNC_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *LP_UART_Type) GetCONF0_SYNC_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x100000) >> 20 +} +func (o *LP_UART_Type) SetCONF0_SYNC_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x200000)|value<<21) +} +func (o *LP_UART_Type) GetCONF0_SYNC_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x200000) >> 21 +} +func (o *LP_UART_Type) SetCONF0_SYNC_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x400000)|value<<22) +} +func (o *LP_UART_Type) GetCONF0_SYNC_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x400000) >> 22 +} +func (o *LP_UART_Type) SetCONF0_SYNC_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x800000)|value<<23) +} +func (o *LP_UART_Type) GetCONF0_SYNC_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x800000) >> 23 +} + +// LP_UART.CONF1: Configuration register 1 +func (o *LP_UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xf800)|value<<11) +} +func (o *LP_UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xf800) >> 11 +} +func (o *LP_UART_Type) SetCONF1_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *LP_UART_Type) GetCONF1_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10000) >> 16 +} +func (o *LP_UART_Type) SetCONF1_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *LP_UART_Type) GetCONF1_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000) >> 17 +} +func (o *LP_UART_Type) SetCONF1_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetCONF1_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetCONF1_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetCONF1_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19 +} +func (o *LP_UART_Type) SetCONF1_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *LP_UART_Type) GetCONF1_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *LP_UART_Type) SetCONF1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *LP_UART_Type) GetCONF1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} + +// LP_UART.HWFC_CONF_SYNC: Hardware flow-control configuration +func (o *LP_UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0x100)|value<<8) +} +func (o *LP_UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0x100) >> 8 +} + +// LP_UART.SLEEP_CONF0: UART sleep configure register 0 +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR1(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR1() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff +} +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR2(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR2() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff00) >> 8 +} +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR3(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR3() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff0000) >> 16 +} +func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR4(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff000000)|value<<24) +} +func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR4() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff000000) >> 24 +} + +// LP_UART.SLEEP_CONF1: UART sleep configure register 1 +func (o *LP_UART_Type) SetSLEEP_CONF1_WK_CHAR0(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF1.Reg, volatile.LoadUint32(&o.SLEEP_CONF1.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetSLEEP_CONF1_WK_CHAR0() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF1.Reg) & 0xff +} + +// LP_UART.SLEEP_CONF2: UART sleep configure register 2 +func (o *LP_UART_Type) SetSLEEP_CONF2_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3ff)|value) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3ff +} +func (o *LP_UART_Type) SetSLEEP_CONF2_RX_WAKE_UP_THRHD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e000)|value<<13) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_RX_WAKE_UP_THRHD() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e000) >> 13 +} +func (o *LP_UART_Type) SetSLEEP_CONF2_WK_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x1c0000)|value<<18) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_WK_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x1c0000) >> 18 +} +func (o *LP_UART_Type) SetSLEEP_CONF2_WK_CHAR_MASK(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e00000)|value<<21) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_WK_CHAR_MASK() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e00000) >> 21 +} +func (o *LP_UART_Type) SetSLEEP_CONF2_WK_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0xc000000)|value<<26) +} +func (o *LP_UART_Type) GetSLEEP_CONF2_WK_MODE_SEL() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0xc000000) >> 26 +} + +// LP_UART.SWFC_CONF0_SYNC: Software flow-control character configuration +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XON_CHAR() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff00)|value<<8) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff00) >> 8 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x10000)|value<<16) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x10000) >> 16 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x20000)|value<<17) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_SW_FLOW_CON_EN() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x20000) >> 17 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x40000)|value<<18) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x40000) >> 18 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x80000)|value<<19) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x80000) >> 19 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x100000) >> 20 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_SEND_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x200000)|value<<21) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x200000) >> 21 +} +func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x400000)|value<<22) +} +func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x400000) >> 22 +} + +// LP_UART.SWFC_CONF1: Software flow-control character configuration +func (o *LP_UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetSWFC_CONF1_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xf800)|value<<11) +} +func (o *LP_UART_Type) GetSWFC_CONF1_XOFF_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xf800) >> 11 +} + +// LP_UART.TXBRK_CONF_SYNC: Tx Break character configuration +func (o *LP_UART_Type) SetTXBRK_CONF_SYNC_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.TXBRK_CONF_SYNC.Reg, volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetTXBRK_CONF_SYNC_TX_BRK_NUM() uint32 { + return volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg) & 0xff +} + +// LP_UART.IDLE_CONF_SYNC: Frame-end idle configuration +func (o *LP_UART_Type) SetIDLE_CONF_SYNC_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0x3ff)|value) +} +func (o *LP_UART_Type) GetIDLE_CONF_SYNC_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0x3ff +} +func (o *LP_UART_Type) SetIDLE_CONF_SYNC_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0xffc00)|value<<10) +} +func (o *LP_UART_Type) GetIDLE_CONF_SYNC_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0xffc00) >> 10 +} + +// LP_UART.RS485_CONF_SYNC: RS485 mode configuration +func (o *LP_UART_Type) SetRS485_CONF_SYNC_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetRS485_CONF_SYNC_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetRS485_CONF_SYNC_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetRS485_CONF_SYNC_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x4) >> 2 +} + +// LP_UART.AT_CMD_PRECNT_SYNC: Pre-sequence timing configuration +func (o *LP_UART_Type) SetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg)&^(0xffff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg) & 0xffff +} + +// LP_UART.AT_CMD_POSTCNT_SYNC: Post-sequence timing configuration +func (o *LP_UART_Type) SetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg)&^(0xffff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg) & 0xffff +} + +// LP_UART.AT_CMD_GAPTOUT_SYNC: Timeout configuration +func (o *LP_UART_Type) SetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg)&^(0xffff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg) & 0xffff +} + +// LP_UART.AT_CMD_CHAR_SYNC: AT escape sequence detection configuration +func (o *LP_UART_Type) SetAT_CMD_CHAR_SYNC_AT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff)|value) +} +func (o *LP_UART_Type) GetAT_CMD_CHAR_SYNC_AT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff +} +func (o *LP_UART_Type) SetAT_CMD_CHAR_SYNC_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff00)|value<<8) +} +func (o *LP_UART_Type) GetAT_CMD_CHAR_SYNC_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff00) >> 8 +} + +// LP_UART.MEM_CONF: UART memory power configuration +func (o *LP_UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LP_UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26 +} + +// LP_UART.TOUT_CONF_SYNC: UART threshold and allocation configuration +func (o *LP_UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_EN() uint32 { + return volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x1 +} +func (o *LP_UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0xffc)|value<<2) +} +func (o *LP_UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0xffc) >> 2 +} + +// LP_UART.MEM_TX_STATUS: Tx-SRAM write and read offset address. +func (o *LP_UART_Type) SetMEM_TX_STATUS_TX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetMEM_TX_STATUS_TX_SRAM_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetMEM_TX_STATUS_TX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1f000)|value<<12) +} +func (o *LP_UART_Type) GetMEM_TX_STATUS_TX_SRAM_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1f000) >> 12 +} + +// LP_UART.MEM_RX_STATUS: Rx-SRAM write and read offset address. +func (o *LP_UART_Type) SetMEM_RX_STATUS_RX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xf8)|value<<3) +} +func (o *LP_UART_Type) GetMEM_RX_STATUS_RX_SRAM_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xf8) >> 3 +} +func (o *LP_UART_Type) SetMEM_RX_STATUS_RX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1f000)|value<<12) +} +func (o *LP_UART_Type) GetMEM_RX_STATUS_RX_SRAM_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1f000) >> 12 +} + +// LP_UART.FSM_STATUS: UART transmit and receive status. +func (o *LP_UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *LP_UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *LP_UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *LP_UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// LP_UART.CLK_CONF: UART core clock configuration +func (o *LP_UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LP_UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LP_UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LP_UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *LP_UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *LP_UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *LP_UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *LP_UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} + +// LP_UART.DATE: UART Version register +func (o *LP_UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *LP_UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// LP_UART.AFIFO_STATUS: UART AFIFO Status +func (o *LP_UART_Type) SetAFIFO_STATUS_TX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_TX_AFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x1 +} +func (o *LP_UART_Type) SetAFIFO_STATUS_TX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_TX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x2) >> 1 +} +func (o *LP_UART_Type) SetAFIFO_STATUS_RX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_RX_AFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x4) >> 2 +} +func (o *LP_UART_Type) SetAFIFO_STATUS_RX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *LP_UART_Type) GetAFIFO_STATUS_RX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x8) >> 3 +} + +// LP_UART.REG_UPDATE: UART Registers Configuration Update register +func (o *LP_UART_Type) SetREG_UPDATE(value uint32) { + volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x1)|value) +} +func (o *LP_UART_Type) GetREG_UPDATE() uint32 { + return volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x1 +} + +// LP_UART.ID: UART ID register +func (o *LP_UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, value) +} +func (o *LP_UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) +} + +// Motor Control Pulse-Width Modulation 0 +type MCPWM_Type struct { + CLK_CFG volatile.Register32 // 0x0 + TIMER0_CFG0 volatile.Register32 // 0x4 + TIMER0_CFG1 volatile.Register32 // 0x8 + TIMER0_SYNC volatile.Register32 // 0xC + TIMER0_STATUS volatile.Register32 // 0x10 + TIMER1_CFG0 volatile.Register32 // 0x14 + TIMER1_CFG1 volatile.Register32 // 0x18 + TIMER1_SYNC volatile.Register32 // 0x1C + TIMER1_STATUS volatile.Register32 // 0x20 + TIMER2_CFG0 volatile.Register32 // 0x24 + TIMER2_CFG1 volatile.Register32 // 0x28 + TIMER2_SYNC volatile.Register32 // 0x2C + TIMER2_STATUS volatile.Register32 // 0x30 + TIMER_SYNCI_CFG volatile.Register32 // 0x34 + OPERATOR_TIMERSEL volatile.Register32 // 0x38 + GEN0_STMP_CFG volatile.Register32 // 0x3C + GEN0_TSTMP_A volatile.Register32 // 0x40 + GEN0_TSTMP_B volatile.Register32 // 0x44 + GEN0_CFG0 volatile.Register32 // 0x48 + GEN0_FORCE volatile.Register32 // 0x4C + GEN0_A volatile.Register32 // 0x50 + GEN0_B volatile.Register32 // 0x54 + DT0_CFG volatile.Register32 // 0x58 + DT0_FED_CFG volatile.Register32 // 0x5C + DT0_RED_CFG volatile.Register32 // 0x60 + CARRIER0_CFG volatile.Register32 // 0x64 + FH0_CFG0 volatile.Register32 // 0x68 + FH0_CFG1 volatile.Register32 // 0x6C + FH0_STATUS volatile.Register32 // 0x70 + GEN1_STMP_CFG volatile.Register32 // 0x74 + GEN1_TSTMP_A volatile.Register32 // 0x78 + GEN1_TSTMP_B volatile.Register32 // 0x7C + GEN1_CFG0 volatile.Register32 // 0x80 + GEN1_FORCE volatile.Register32 // 0x84 + GEN1_A volatile.Register32 // 0x88 + GEN1_B volatile.Register32 // 0x8C + DT1_CFG volatile.Register32 // 0x90 + DT1_FED_CFG volatile.Register32 // 0x94 + DT1_RED_CFG volatile.Register32 // 0x98 + CARRIER1_CFG volatile.Register32 // 0x9C + FH1_CFG0 volatile.Register32 // 0xA0 + FH1_CFG1 volatile.Register32 // 0xA4 + FH1_STATUS volatile.Register32 // 0xA8 + GEN2_STMP_CFG volatile.Register32 // 0xAC + GEN2_TSTMP_A volatile.Register32 // 0xB0 + GEN2_TSTMP_B volatile.Register32 // 0xB4 + GEN2_CFG0 volatile.Register32 // 0xB8 + GEN2_FORCE volatile.Register32 // 0xBC + GEN2_A volatile.Register32 // 0xC0 + GEN2_B volatile.Register32 // 0xC4 + DT2_CFG volatile.Register32 // 0xC8 + DT2_FED_CFG volatile.Register32 // 0xCC + DT2_RED_CFG volatile.Register32 // 0xD0 + CARRIER2_CFG volatile.Register32 // 0xD4 + FH2_CFG0 volatile.Register32 // 0xD8 + FH2_CFG1 volatile.Register32 // 0xDC + FH2_STATUS volatile.Register32 // 0xE0 + FAULT_DETECT volatile.Register32 // 0xE4 + CAP_TIMER_CFG volatile.Register32 // 0xE8 + CAP_TIMER_PHASE volatile.Register32 // 0xEC + CAP_CH0_CFG volatile.Register32 // 0xF0 + CAP_CH1_CFG volatile.Register32 // 0xF4 + CAP_CH2_CFG volatile.Register32 // 0xF8 + CAP_CH0 volatile.Register32 // 0xFC + CAP_CH1 volatile.Register32 // 0x100 + CAP_CH2 volatile.Register32 // 0x104 + CAP_STATUS volatile.Register32 // 0x108 + UPDATE_CFG volatile.Register32 // 0x10C + INT_ENA volatile.Register32 // 0x110 + INT_RAW volatile.Register32 // 0x114 + INT_ST volatile.Register32 // 0x118 + INT_CLR volatile.Register32 // 0x11C + EVT_EN volatile.Register32 // 0x120 + TASK_EN volatile.Register32 // 0x124 + EVT_EN2 volatile.Register32 // 0x128 + OP0_TSTMP_E1 volatile.Register32 // 0x12C + OP0_TSTMP_E2 volatile.Register32 // 0x130 + OP1_TSTMP_E1 volatile.Register32 // 0x134 + OP1_TSTMP_E2 volatile.Register32 // 0x138 + OP2_TSTMP_E1 volatile.Register32 // 0x13C + OP2_TSTMP_E2 volatile.Register32 // 0x140 + CLK volatile.Register32 // 0x144 + VERSION volatile.Register32 // 0x148 +} + +// MCPWM.CLK_CFG: PWM clock prescaler register. +func (o *MCPWM_Type) SetCLK_CFG_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetCLK_CFG_CLK_PRESCALE() uint32 { + return volatile.LoadUint32(&o.CLK_CFG.Reg) & 0xff +} + +// MCPWM.TIMER0_CFG0: PWM timer%s period and update method configuration register. +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER0_CFG1: PWM timer%s working mode and start/stop control register. +func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER_START(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER_START() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER0_SYNC: PWM timer%s sync function configuration register. +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER0_STATUS: PWM timer%s status register. +func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER1_CFG0: PWM timer%s period and update method configuration register. +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER1_CFG1: PWM timer%s working mode and start/stop control register. +func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER_START(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER_START() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER1_SYNC: PWM timer%s sync function configuration register. +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER1_STATUS: PWM timer%s status register. +func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER2_CFG0: PWM timer%s period and update method configuration register. +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xff)|value) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xff +} +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0x3000000) >> 24 +} + +// MCPWM.TIMER2_CFG1: PWM timer%s working mode and start/stop control register. +func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER_START(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER_START() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x18) >> 3 +} + +// MCPWM.TIMER2_SYNC: PWM timer%s sync function configuration register. +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x100000) >> 20 +} + +// MCPWM.TIMER2_STATUS: PWM timer%s status register. +func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0xffff +} +func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0x10000) >> 16 +} + +// MCPWM.TIMER_SYNCI_CFG: Synchronization input selection register for PWM timers. +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER0_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x7)|value) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER0_SYNCISEL() uint32 { + return volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x7 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER1_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x38)|value<<3) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER1_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x38) >> 3 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER2_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x1c0)|value<<6) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER2_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x1c0) >> 6 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x800) >> 11 +} + +// MCPWM.OPERATOR_TIMERSEL: PWM operator's timer select register +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL() uint32 { + return volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x3 +} +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x30) >> 4 +} + +// MCPWM.GEN0_STMP_CFG: Generator%s time stamp registers A and B transfer status and update method register +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN0_TSTMP_A: Generator%s time stamp A's shadow register +func (o *MCPWM_Type) SetGEN0_TSTMP_A_CMPR_A(value uint32) { + volatile.StoreUint32(&o.GEN0_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN0_TSTMP_A_CMPR_A() uint32 { + return volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN0_TSTMP_B: Generator%s time stamp B's shadow register +func (o *MCPWM_Type) SetGEN0_TSTMP_B_CMPR_B(value uint32) { + volatile.StoreUint32(&o.GEN0_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN0_TSTMP_B_CMPR_B() uint32 { + return volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN0_CFG0: Generator%s fault event T0 and T1 configuration register +func (o *MCPWM_Type) SetGEN0_CFG0_GEN_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN0_CFG0_GEN_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN0_CFG0_GEN_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN0_CFG0_GEN_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN0_FORCE: Generator%s output signal force mode register. +func (o *MCPWM_Type) SetGEN0_FORCE_GEN_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN0_FORCE_GEN_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_FORCE_GEN_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN0_A: PWM%s output signal A actions configuration register +func (o *MCPWM_Type) SetGEN0_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN0_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN0_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN0_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN0_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN0_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN0_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN0_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN0_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN0_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN0_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN0_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN0_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN0_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN0_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN0_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN0_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN0_B: PWM%s output signal B actions configuration register +func (o *MCPWM_Type) SetGEN0_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN0_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN0_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN0_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN0_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN0_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN0_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN0_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN0_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN0_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN0_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN0_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN0_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN0_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN0_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN0_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN0_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN0_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN0_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN0_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN0_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN0_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN0_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN0_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT0_CFG: Dead time configuration register +func (o *MCPWM_Type) SetDT0_CFG_DB_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT0_CFG_DB_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT0_CFG_DB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT0_CFG_DB_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT0_FED_CFG: Falling edge delay (FED) shadow register +func (o *MCPWM_Type) SetDT0_FED_CFG_DB_FED(value uint32) { + volatile.StoreUint32(&o.DT0_FED_CFG.Reg, volatile.LoadUint32(&o.DT0_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT0_FED_CFG_DB_FED() uint32 { + return volatile.LoadUint32(&o.DT0_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT0_RED_CFG: Rising edge delay (RED) shadow register +func (o *MCPWM_Type) SetDT0_RED_CFG_DB_RED(value uint32) { + volatile.StoreUint32(&o.DT0_RED_CFG.Reg, volatile.LoadUint32(&o.DT0_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT0_RED_CFG_DB_RED() uint32 { + return volatile.LoadUint32(&o.DT0_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER0_CFG: Carrier%s configuration register +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH0_CFG0: PWM%s A and PWM%s B trip events actions configuration register +func (o *MCPWM_Type) SetFH0_CFG0_TZ_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH0_CFG0_TZ_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH0_CFG0_TZ_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH0_CFG1: Software triggers for fault handler actions configuration register +func (o *MCPWM_Type) SetFH0_CFG1_TZ_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_CFG1_TZ_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH0_CFG1_TZ_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH0_CFG1_TZ_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH0_CFG1_TZ_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH0_STATUS: Fault events status register +func (o *MCPWM_Type) SetFH0_STATUS_TZ_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH0_STATUS_TZ_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH0_STATUS_TZ_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH0_STATUS_TZ_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.GEN1_STMP_CFG: Generator%s time stamp registers A and B transfer status and update method register +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN1_TSTMP_A: Generator%s time stamp A's shadow register +func (o *MCPWM_Type) SetGEN1_TSTMP_A_CMPR_A(value uint32) { + volatile.StoreUint32(&o.GEN1_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN1_TSTMP_A_CMPR_A() uint32 { + return volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN1_TSTMP_B: Generator%s time stamp B's shadow register +func (o *MCPWM_Type) SetGEN1_TSTMP_B_CMPR_B(value uint32) { + volatile.StoreUint32(&o.GEN1_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN1_TSTMP_B_CMPR_B() uint32 { + return volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN1_CFG0: Generator%s fault event T0 and T1 configuration register +func (o *MCPWM_Type) SetGEN1_CFG0_GEN_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN1_CFG0_GEN_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN1_CFG0_GEN_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN1_CFG0_GEN_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN1_FORCE: Generator%s output signal force mode register. +func (o *MCPWM_Type) SetGEN1_FORCE_GEN_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN1_FORCE_GEN_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_FORCE_GEN_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN1_A: PWM%s output signal A actions configuration register +func (o *MCPWM_Type) SetGEN1_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN1_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN1_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN1_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN1_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN1_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN1_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN1_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN1_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN1_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN1_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN1_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN1_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN1_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN1_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN1_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN1_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN1_B: PWM%s output signal B actions configuration register +func (o *MCPWM_Type) SetGEN1_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN1_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN1_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN1_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN1_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN1_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN1_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN1_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN1_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN1_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN1_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN1_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN1_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN1_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN1_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN1_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN1_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN1_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN1_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN1_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN1_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN1_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN1_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN1_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT1_CFG: Dead time configuration register +func (o *MCPWM_Type) SetDT1_CFG_DB_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT1_CFG_DB_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT1_CFG_DB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT1_CFG_DB_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT1_FED_CFG: Falling edge delay (FED) shadow register +func (o *MCPWM_Type) SetDT1_FED_CFG_DB_FED(value uint32) { + volatile.StoreUint32(&o.DT1_FED_CFG.Reg, volatile.LoadUint32(&o.DT1_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT1_FED_CFG_DB_FED() uint32 { + return volatile.LoadUint32(&o.DT1_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT1_RED_CFG: Rising edge delay (RED) shadow register +func (o *MCPWM_Type) SetDT1_RED_CFG_DB_RED(value uint32) { + volatile.StoreUint32(&o.DT1_RED_CFG.Reg, volatile.LoadUint32(&o.DT1_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT1_RED_CFG_DB_RED() uint32 { + return volatile.LoadUint32(&o.DT1_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER1_CFG: Carrier%s configuration register +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH1_CFG0: PWM%s A and PWM%s B trip events actions configuration register +func (o *MCPWM_Type) SetFH1_CFG0_TZ_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH1_CFG0_TZ_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH1_CFG0_TZ_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH1_CFG1: Software triggers for fault handler actions configuration register +func (o *MCPWM_Type) SetFH1_CFG1_TZ_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_CFG1_TZ_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH1_CFG1_TZ_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH1_CFG1_TZ_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH1_CFG1_TZ_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH1_STATUS: Fault events status register +func (o *MCPWM_Type) SetFH1_STATUS_TZ_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH1_STATUS_TZ_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH1_STATUS_TZ_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH1_STATUS_TZ_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.GEN2_STMP_CFG: Generator%s time stamp registers A and B transfer status and update method register +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x200) >> 9 +} + +// MCPWM.GEN2_TSTMP_A: Generator%s time stamp A's shadow register +func (o *MCPWM_Type) SetGEN2_TSTMP_A_CMPR_A(value uint32) { + volatile.StoreUint32(&o.GEN2_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN2_TSTMP_A_CMPR_A() uint32 { + return volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg) & 0xffff +} + +// MCPWM.GEN2_TSTMP_B: Generator%s time stamp B's shadow register +func (o *MCPWM_Type) SetGEN2_TSTMP_B_CMPR_B(value uint32) { + volatile.StoreUint32(&o.GEN2_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetGEN2_TSTMP_B_CMPR_B() uint32 { + return volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg) & 0xffff +} + +// MCPWM.GEN2_CFG0: Generator%s fault event T0 and T1 configuration register +func (o *MCPWM_Type) SetGEN2_CFG0_GEN_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0xf +} +func (o *MCPWM_Type) SetGEN2_CFG0_GEN_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x70) >> 4 +} +func (o *MCPWM_Type) SetGEN2_CFG0_GEN_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *MCPWM_Type) GetGEN2_CFG0_GEN_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x380) >> 7 +} + +// MCPWM.GEN2_FORCE: Generator%s output signal force mode register. +func (o *MCPWM_Type) SetGEN2_FORCE_GEN_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x3f)|value) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x3f +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x1800) >> 11 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetGEN2_FORCE_GEN_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_FORCE_GEN_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc000) >> 14 +} + +// MCPWM.GEN2_A: PWM%s output signal A actions configuration register +func (o *MCPWM_Type) SetGEN2_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN2_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN2_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN2_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN2_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN2_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN2_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN2_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN2_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN2_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN2_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN2_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN2_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN2_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN2_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN2_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN2_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00000) >> 22 +} + +// MCPWM.GEN2_B: PWM%s output signal B actions configuration register +func (o *MCPWM_Type) SetGEN2_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3)|value) +} +func (o *MCPWM_Type) GetGEN2_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3 +} +func (o *MCPWM_Type) SetGEN2_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc)|value<<2) +} +func (o *MCPWM_Type) GetGEN2_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc) >> 2 +} +func (o *MCPWM_Type) SetGEN2_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30)|value<<4) +} +func (o *MCPWM_Type) GetGEN2_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30) >> 4 +} +func (o *MCPWM_Type) SetGEN2_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0)|value<<6) +} +func (o *MCPWM_Type) GetGEN2_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0) >> 6 +} +func (o *MCPWM_Type) SetGEN2_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetGEN2_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetGEN2_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetGEN2_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetGEN2_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetGEN2_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetGEN2_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetGEN2_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetGEN2_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetGEN2_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetGEN2_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetGEN2_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetGEN2_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetGEN2_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetGEN2_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetGEN2_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00000) >> 22 +} + +// MCPWM.DT2_CFG: Dead time configuration register +func (o *MCPWM_Type) SetDT2_CFG_DB_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf)|value) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf +} +func (o *MCPWM_Type) SetDT2_CFG_DB_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf0) >> 4 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetDT2_CFG_DB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetDT2_CFG_DB_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x20000) >> 17 +} + +// MCPWM.DT2_FED_CFG: Falling edge delay (FED) shadow register +func (o *MCPWM_Type) SetDT2_FED_CFG_DB_FED(value uint32) { + volatile.StoreUint32(&o.DT2_FED_CFG.Reg, volatile.LoadUint32(&o.DT2_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT2_FED_CFG_DB_FED() uint32 { + return volatile.LoadUint32(&o.DT2_FED_CFG.Reg) & 0xffff +} + +// MCPWM.DT2_RED_CFG: Rising edge delay (RED) shadow register +func (o *MCPWM_Type) SetDT2_RED_CFG_DB_RED(value uint32) { + volatile.StoreUint32(&o.DT2_RED_CFG.Reg, volatile.LoadUint32(&o.DT2_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetDT2_RED_CFG_DB_RED() uint32 { + return volatile.LoadUint32(&o.DT2_RED_CFG.Reg) & 0xffff +} + +// MCPWM.CARRIER2_CFG: Carrier%s configuration register +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_EN(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_EN() uint32 { + return volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1e) >> 1 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_DUTY(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_DUTY() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xe0) >> 5 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xf00) >> 8 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x2000) >> 13 +} + +// MCPWM.FH2_CFG0: PWM%s A and PWM%s B trip events actions configuration register +func (o *MCPWM_Type) SetFH2_CFG0_TZ_SW_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_SW_CBC() uint32 { + return volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_F2_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_F1_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_F0_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_SW_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_SW_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_F2_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_F2_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_F1_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_F1_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_F0_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_F0_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300) >> 8 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00) >> 10 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_A_OST_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x3000) >> 12 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_A_OST_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc000) >> 14 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x30000) >> 16 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_B_OST_D(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300000) >> 20 +} +func (o *MCPWM_Type) SetFH2_CFG0_TZ_B_OST_U(value uint32) { + volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *MCPWM_Type) GetFH2_CFG0_TZ_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00000) >> 22 +} + +// MCPWM.FH2_CFG1: Software triggers for fault handler actions configuration register +func (o *MCPWM_Type) SetFH2_CFG1_TZ_CLR_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ_CLR_OST() uint32 { + return volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_CFG1_TZ_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetFH2_CFG1_TZ_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFH2_CFG1_TZ_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFH2_CFG1_TZ_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x10) >> 4 +} + +// MCPWM.FH2_STATUS: Fault events status register +func (o *MCPWM_Type) SetFH2_STATUS_TZ_CBC_ON(value uint32) { + volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFH2_STATUS_TZ_CBC_ON() uint32 { + return volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFH2_STATUS_TZ_OST_ON(value uint32) { + volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFH2_STATUS_TZ_OST_ON() uint32 { + return (volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x2) >> 1 +} + +// MCPWM.FAULT_DETECT: Fault detection configuration and status register +func (o *MCPWM_Type) SetFAULT_DETECT_F0_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F0_EN() uint32 { + return volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x1 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F1_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F1_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F2_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F2_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F0_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F0_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F1_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F1_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetFAULT_DETECT_F2_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetFAULT_DETECT_F2_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F0(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F0() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F1(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F1() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F2(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F2() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x100) >> 8 +} + +// MCPWM.CAP_TIMER_CFG: Capture timer configuration register +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_TIMER_EN() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_EN() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_SEL(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1c)|value<<2) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_SEL() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1c) >> 2 +} +func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x20) >> 5 +} + +// MCPWM.CAP_TIMER_PHASE: Capture timer sync phase register +func (o *MCPWM_Type) SetCAP_TIMER_PHASE(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_PHASE.Reg, value) +} +func (o *MCPWM_Type) GetCAP_TIMER_PHASE() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_PHASE.Reg) +} + +// MCPWM.CAP_CH0_CFG: Capture channel %s configuration register +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH1_CFG: Capture channel %s configuration register +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH2_CFG: Capture channel %s configuration register +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x6)|value<<1) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x6) >> 1 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x7f8) >> 3 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1000) >> 12 +} + +// MCPWM.CAP_CH0: CAP%s capture value register +func (o *MCPWM_Type) SetCAP_CH0(value uint32) { + volatile.StoreUint32(&o.CAP_CH0.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH0() uint32 { + return volatile.LoadUint32(&o.CAP_CH0.Reg) +} + +// MCPWM.CAP_CH1: CAP%s capture value register +func (o *MCPWM_Type) SetCAP_CH1(value uint32) { + volatile.StoreUint32(&o.CAP_CH1.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH1() uint32 { + return volatile.LoadUint32(&o.CAP_CH1.Reg) +} + +// MCPWM.CAP_CH2: CAP%s capture value register +func (o *MCPWM_Type) SetCAP_CH2(value uint32) { + volatile.StoreUint32(&o.CAP_CH2.Reg, value) +} +func (o *MCPWM_Type) GetCAP_CH2() uint32 { + return volatile.LoadUint32(&o.CAP_CH2.Reg) +} + +// MCPWM.CAP_STATUS: Last capture trigger edge information register +func (o *MCPWM_Type) SetCAP_STATUS_CAP0_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP0_EDGE() uint32 { + return volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x1 +} +func (o *MCPWM_Type) SetCAP_STATUS_CAP1_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP1_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetCAP_STATUS_CAP2_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetCAP_STATUS_CAP2_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x4) >> 2 +} + +// MCPWM.UPDATE_CFG: Generator Update configuration register +func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_UP_EN() uint32 { + return volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x1 +} +func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP0_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP0_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP0_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP0_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP1_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP1_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP1_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP1_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP2_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP2_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetUPDATE_CFG_OP2_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetUPDATE_CFG_OP2_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x80) >> 7 +} + +// MCPWM.INT_ENA: Interrupt enable register +func (o *MCPWM_Type) SetINT_ENA_TIMER0_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_STOP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT0_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT0_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT1_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT1_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_ENA_FAULT2_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_ENA_FAULT2_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR0_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR0_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR1_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR1_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR2_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR2_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR0_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR0_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR1_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR1_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_ENA_CMPR2_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_ENA_CMPR2_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_ENA_TZ0_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_ENA_TZ0_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_ENA_TZ1_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_ENA_TZ1_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_ENA_TZ2_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_ENA_TZ2_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_ENA_TZ0_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_ENA_TZ0_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_ENA_TZ1_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_ENA_TZ1_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_ENA_TZ2_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_ENA_TZ2_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_ENA_CAP0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_ENA_CAP0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_ENA_CAP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_ENA_CAP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_ENA_CAP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_ENA_CAP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_RAW: Interrupt raw status register +func (o *MCPWM_Type) SetINT_RAW_TIMER0_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_STOP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT0_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT0_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT1_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT1_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_RAW_FAULT2_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_RAW_FAULT2_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR0_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR0_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR1_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR1_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR2_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR2_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR0_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR0_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR1_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR1_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_RAW_CMPR2_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_RAW_CMPR2_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_RAW_TZ0_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_RAW_TZ0_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_RAW_TZ1_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_RAW_TZ1_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_RAW_TZ2_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_RAW_TZ2_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_RAW_TZ0_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_RAW_TZ0_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_RAW_TZ1_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_RAW_TZ1_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_RAW_TZ2_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_RAW_TZ2_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_RAW_CAP0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_RAW_CAP0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_RAW_CAP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_RAW_CAP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_RAW_CAP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_RAW_CAP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_ST: Interrupt masked status register +func (o *MCPWM_Type) SetINT_ST_TIMER0_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_STOP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_ST_TIMER0_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_ST_TIMER0_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_ST_TIMER0_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_ST_TIMER1_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_ST_TIMER1_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_ST_TIMER2_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_ST_TIMER2_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_ST_FAULT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_ST_FAULT0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_ST_FAULT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_ST_FAULT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_ST_FAULT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_ST_FAULT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_ST_FAULT0_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_ST_FAULT0_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_ST_FAULT1_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_ST_FAULT1_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_ST_FAULT2_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_ST_FAULT2_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_ST_CMPR0_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_ST_CMPR0_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_ST_CMPR1_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_ST_CMPR1_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_ST_CMPR2_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_ST_CMPR2_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_ST_CMPR0_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_ST_CMPR0_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_ST_CMPR1_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_ST_CMPR1_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_ST_CMPR2_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_ST_CMPR2_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_ST_TZ0_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_ST_TZ0_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_ST_TZ1_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_ST_TZ1_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_ST_TZ2_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_ST_TZ2_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_ST_TZ0_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_ST_TZ0_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_ST_TZ1_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_ST_TZ1_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_ST_TZ2_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_ST_TZ2_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_ST_CAP0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_ST_CAP0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_ST_CAP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_ST_CAP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_ST_CAP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_ST_CAP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} + +// MCPWM.INT_CLR: Interrupt clear register +func (o *MCPWM_Type) SetINT_CLR_TIMER0_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_STOP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT0_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT0_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT1_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT1_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetINT_CLR_FAULT2_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetINT_CLR_FAULT2_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR0_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR0_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR1_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR1_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR2_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR2_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR0_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR0_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR1_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR1_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetINT_CLR_CMPR2_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetINT_CLR_CMPR2_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetINT_CLR_TZ0_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetINT_CLR_TZ0_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetINT_CLR_TZ1_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetINT_CLR_TZ1_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetINT_CLR_TZ2_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetINT_CLR_TZ2_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetINT_CLR_TZ0_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetINT_CLR_TZ0_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetINT_CLR_TZ1_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetINT_CLR_TZ1_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetINT_CLR_TZ2_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetINT_CLR_TZ2_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetINT_CLR_CAP0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetINT_CLR_CAP0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetINT_CLR_CAP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetINT_CLR_CAP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetINT_CLR_CAP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetINT_CLR_CAP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} + +// MCPWM.EVT_EN: Event enable register +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_STOP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_STOP_EN() uint32 { + return volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_STOP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_STOP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_TEZ_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_TEZ_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_TEZ_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_TEZ_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_TEZ_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_TEZ_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_TEP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_TEP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_TEP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_TEP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_TEP_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_TEP_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP0_TEA_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP0_TEA_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP1_TEA_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP1_TEA_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP2_TEA_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP2_TEA_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP0_TEB_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP0_TEB_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP1_TEB_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP1_TEB_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_OP2_TEB_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_OP2_TEB_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F0_CLR_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F0_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F1_CLR_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F1_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_F2_CLR_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_F2_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ0_CBC_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ0_CBC_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x200000) >> 21 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ1_CBC_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x400000)|value<<22) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ1_CBC_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x400000) >> 22 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ2_CBC_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x800000)|value<<23) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ2_CBC_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x800000) >> 23 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ0_OST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1000000)|value<<24) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ0_OST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1000000) >> 24 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ1_OST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2000000)|value<<25) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ1_OST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2000000) >> 25 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_TZ2_OST_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4000000)|value<<26) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_TZ2_OST_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4000000) >> 26 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8000000)|value<<27) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_CAP0_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8000000) >> 27 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10000000)|value<<28) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_CAP1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10000000) >> 28 +} +func (o *MCPWM_Type) SetEVT_EN_EVT_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20000000)|value<<29) +} +func (o *MCPWM_Type) GetEVT_EN_EVT_CAP2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20000000) >> 29 +} + +// MCPWM.TASK_EN: Task enable register +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR0_A_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR0_A_UP_EN() uint32 { + return volatile.LoadUint32(&o.TASK_EN.Reg) & 0x1 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR1_A_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR1_A_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR2_A_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR2_A_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR0_B_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR0_B_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR1_B_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR1_B_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR2_B_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR2_B_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x20) >> 5 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_GEN_STOP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x40)|value<<6) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_GEN_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x40) >> 6 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER0_SYNC_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x80)|value<<7) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER0_SYNC_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x80) >> 7 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER1_SYNC_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x100)|value<<8) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER1_SYNC_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x100) >> 8 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER2_SYNC_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x200)|value<<9) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER2_SYNC_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x200) >> 9 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER0_PERIOD_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x400)|value<<10) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER0_PERIOD_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x400) >> 10 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER1_PERIOD_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x800)|value<<11) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER1_PERIOD_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x800) >> 11 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER2_PERIOD_UP_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x1000)|value<<12) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER2_PERIOD_UP_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x1000) >> 12 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TZ0_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x2000)|value<<13) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TZ0_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x2000) >> 13 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TZ1_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x4000)|value<<14) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TZ1_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x4000) >> 14 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_TZ2_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x8000)|value<<15) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_TZ2_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x8000) >> 15 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CLR0_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x10000)|value<<16) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CLR0_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x10000) >> 16 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CLR1_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x20000)|value<<17) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CLR1_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x20000) >> 17 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CLR2_OST_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x40000)|value<<18) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CLR2_OST_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x40000) >> 18 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x80000)|value<<19) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CAP0_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x80000) >> 19 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x100000)|value<<20) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CAP1_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x100000) >> 20 +} +func (o *MCPWM_Type) SetTASK_EN_TASK_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x200000)|value<<21) +} +func (o *MCPWM_Type) GetTASK_EN_TASK_CAP2_EN() uint32 { + return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x200000) >> 21 +} + +// MCPWM.EVT_EN2: Event enable register2 +func (o *MCPWM_Type) SetEVT_EN2_EVT_OP0_TEE1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetEVT_EN2_EVT_OP0_TEE1_EN() uint32 { + return volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x1 +} +func (o *MCPWM_Type) SetEVT_EN2_EVT_OP1_TEE1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x2)|value<<1) +} +func (o *MCPWM_Type) GetEVT_EN2_EVT_OP1_TEE1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x2) >> 1 +} +func (o *MCPWM_Type) SetEVT_EN2_EVT_OP2_TEE1_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x4)|value<<2) +} +func (o *MCPWM_Type) GetEVT_EN2_EVT_OP2_TEE1_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x4) >> 2 +} +func (o *MCPWM_Type) SetEVT_EN2_EVT_OP0_TEE2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x8)|value<<3) +} +func (o *MCPWM_Type) GetEVT_EN2_EVT_OP0_TEE2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x8) >> 3 +} +func (o *MCPWM_Type) SetEVT_EN2_EVT_OP1_TEE2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x10)|value<<4) +} +func (o *MCPWM_Type) GetEVT_EN2_EVT_OP1_TEE2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x10) >> 4 +} +func (o *MCPWM_Type) SetEVT_EN2_EVT_OP2_TEE2_EN(value uint32) { + volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x20)|value<<5) +} +func (o *MCPWM_Type) GetEVT_EN2_EVT_OP2_TEE2_EN() uint32 { + return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x20) >> 5 +} + +// MCPWM.OP0_TSTMP_E1: Generator%s timer stamp E1 value register +func (o *MCPWM_Type) SetOP0_TSTMP_E1_OP_TSTMP_E1(value uint32) { + volatile.StoreUint32(&o.OP0_TSTMP_E1.Reg, volatile.LoadUint32(&o.OP0_TSTMP_E1.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetOP0_TSTMP_E1_OP_TSTMP_E1() uint32 { + return volatile.LoadUint32(&o.OP0_TSTMP_E1.Reg) & 0xffff +} + +// MCPWM.OP0_TSTMP_E2: Generator%s timer stamp E2 value register +func (o *MCPWM_Type) SetOP0_TSTMP_E2_OP_TSTMP_E2(value uint32) { + volatile.StoreUint32(&o.OP0_TSTMP_E2.Reg, volatile.LoadUint32(&o.OP0_TSTMP_E2.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetOP0_TSTMP_E2_OP_TSTMP_E2() uint32 { + return volatile.LoadUint32(&o.OP0_TSTMP_E2.Reg) & 0xffff +} + +// MCPWM.OP1_TSTMP_E1: Generator%s timer stamp E1 value register +func (o *MCPWM_Type) SetOP1_TSTMP_E1_OP_TSTMP_E1(value uint32) { + volatile.StoreUint32(&o.OP1_TSTMP_E1.Reg, volatile.LoadUint32(&o.OP1_TSTMP_E1.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetOP1_TSTMP_E1_OP_TSTMP_E1() uint32 { + return volatile.LoadUint32(&o.OP1_TSTMP_E1.Reg) & 0xffff +} + +// MCPWM.OP1_TSTMP_E2: Generator%s timer stamp E2 value register +func (o *MCPWM_Type) SetOP1_TSTMP_E2_OP_TSTMP_E2(value uint32) { + volatile.StoreUint32(&o.OP1_TSTMP_E2.Reg, volatile.LoadUint32(&o.OP1_TSTMP_E2.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetOP1_TSTMP_E2_OP_TSTMP_E2() uint32 { + return volatile.LoadUint32(&o.OP1_TSTMP_E2.Reg) & 0xffff +} + +// MCPWM.OP2_TSTMP_E1: Generator%s timer stamp E1 value register +func (o *MCPWM_Type) SetOP2_TSTMP_E1_OP_TSTMP_E1(value uint32) { + volatile.StoreUint32(&o.OP2_TSTMP_E1.Reg, volatile.LoadUint32(&o.OP2_TSTMP_E1.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetOP2_TSTMP_E1_OP_TSTMP_E1() uint32 { + return volatile.LoadUint32(&o.OP2_TSTMP_E1.Reg) & 0xffff +} + +// MCPWM.OP2_TSTMP_E2: Generator%s timer stamp E2 value register +func (o *MCPWM_Type) SetOP2_TSTMP_E2_OP_TSTMP_E2(value uint32) { + volatile.StoreUint32(&o.OP2_TSTMP_E2.Reg, volatile.LoadUint32(&o.OP2_TSTMP_E2.Reg)&^(0xffff)|value) +} +func (o *MCPWM_Type) GetOP2_TSTMP_E2_OP_TSTMP_E2() uint32 { + return volatile.LoadUint32(&o.OP2_TSTMP_E2.Reg) & 0xffff +} + +// MCPWM.CLK: Global configuration register +func (o *MCPWM_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *MCPWM_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} + +// MCPWM.VERSION: Version register. +func (o *MCPWM_Type) SetVERSION_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *MCPWM_Type) GetVERSION_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// Parallel IO Controller +type PARL_IO_Type struct { + RX_MODE_CFG volatile.Register32 // 0x0 + RX_DATA_CFG volatile.Register32 // 0x4 + RX_GENRL_CFG volatile.Register32 // 0x8 + RX_START_CFG volatile.Register32 // 0xC + TX_DATA_CFG volatile.Register32 // 0x10 + TX_START_CFG volatile.Register32 // 0x14 + TX_GENRL_CFG volatile.Register32 // 0x18 + FIFO_CFG volatile.Register32 // 0x1C + REG_UPDATE volatile.Register32 // 0x20 + ST volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_RAW volatile.Register32 // 0x2C + INT_ST volatile.Register32 // 0x30 + INT_CLR volatile.Register32 // 0x34 + RX_ST0 volatile.Register32 // 0x38 + RX_ST1 volatile.Register32 // 0x3C + TX_ST0 volatile.Register32 // 0x40 + RX_CLK_CFG volatile.Register32 // 0x44 + TX_CLK_CFG volatile.Register32 // 0x48 + _ [212]byte + CLK volatile.Register32 // 0x120 + _ [728]byte + VERSION volatile.Register32 // 0x3FC +} + +// PARL_IO.RX_MODE_CFG: Parallel RX Sampling mode configuration register. +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_EXT_EN_SEL(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x1e00000)|value<<21) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_EXT_EN_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x1e00000) >> 21 +} +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_SW_EN(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x2000000)|value<<25) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_SW_EN() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x2000000) >> 25 +} +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_EXT_EN_INV(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x4000000)|value<<26) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_EXT_EN_INV() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x4000000) >> 26 +} +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_PULSE_SUBMODE_SEL(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x38000000)|value<<27) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_PULSE_SUBMODE_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x38000000) >> 27 +} +func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_SMP_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0xc0000000)|value<<30) +} +func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_SMP_MODE_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0xc0000000) >> 30 +} + +// PARL_IO.RX_DATA_CFG: Parallel RX data configuration register. +func (o *PARL_IO_Type) SetRX_DATA_CFG_RX_BITLEN(value uint32) { + volatile.StoreUint32(&o.RX_DATA_CFG.Reg, volatile.LoadUint32(&o.RX_DATA_CFG.Reg)&^(0xffffe00)|value<<9) +} +func (o *PARL_IO_Type) GetRX_DATA_CFG_RX_BITLEN() uint32 { + return (volatile.LoadUint32(&o.RX_DATA_CFG.Reg) & 0xffffe00) >> 9 +} +func (o *PARL_IO_Type) SetRX_DATA_CFG_RX_DATA_ORDER_INV(value uint32) { + volatile.StoreUint32(&o.RX_DATA_CFG.Reg, volatile.LoadUint32(&o.RX_DATA_CFG.Reg)&^(0x10000000)|value<<28) +} +func (o *PARL_IO_Type) GetRX_DATA_CFG_RX_DATA_ORDER_INV() uint32 { + return (volatile.LoadUint32(&o.RX_DATA_CFG.Reg) & 0x10000000) >> 28 +} +func (o *PARL_IO_Type) SetRX_DATA_CFG_RX_BUS_WID_SEL(value uint32) { + volatile.StoreUint32(&o.RX_DATA_CFG.Reg, volatile.LoadUint32(&o.RX_DATA_CFG.Reg)&^(0xe0000000)|value<<29) +} +func (o *PARL_IO_Type) GetRX_DATA_CFG_RX_BUS_WID_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_DATA_CFG.Reg) & 0xe0000000) >> 29 +} + +// PARL_IO.RX_GENRL_CFG: Parallel RX general configuration register. +func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_GATING_EN(value uint32) { + volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_GATING_EN() uint32 { + return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x1000) >> 12 +} +func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x1fffe000) >> 13 +} +func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x20000000)|value<<29) +} +func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_TIMEOUT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x20000000) >> 29 +} +func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_EOF_GEN_SEL(value uint32) { + volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_EOF_GEN_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x40000000) >> 30 +} + +// PARL_IO.RX_START_CFG: Parallel RX Start configuration register. +func (o *PARL_IO_Type) SetRX_START_CFG_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_START_CFG.Reg, volatile.LoadUint32(&o.RX_START_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetRX_START_CFG_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_START_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.TX_DATA_CFG: Parallel TX data configuration register. +func (o *PARL_IO_Type) SetTX_DATA_CFG_TX_BITLEN(value uint32) { + volatile.StoreUint32(&o.TX_DATA_CFG.Reg, volatile.LoadUint32(&o.TX_DATA_CFG.Reg)&^(0xffffe00)|value<<9) +} +func (o *PARL_IO_Type) GetTX_DATA_CFG_TX_BITLEN() uint32 { + return (volatile.LoadUint32(&o.TX_DATA_CFG.Reg) & 0xffffe00) >> 9 +} +func (o *PARL_IO_Type) SetTX_DATA_CFG_TX_DATA_ORDER_INV(value uint32) { + volatile.StoreUint32(&o.TX_DATA_CFG.Reg, volatile.LoadUint32(&o.TX_DATA_CFG.Reg)&^(0x10000000)|value<<28) +} +func (o *PARL_IO_Type) GetTX_DATA_CFG_TX_DATA_ORDER_INV() uint32 { + return (volatile.LoadUint32(&o.TX_DATA_CFG.Reg) & 0x10000000) >> 28 +} +func (o *PARL_IO_Type) SetTX_DATA_CFG_TX_BUS_WID_SEL(value uint32) { + volatile.StoreUint32(&o.TX_DATA_CFG.Reg, volatile.LoadUint32(&o.TX_DATA_CFG.Reg)&^(0xe0000000)|value<<29) +} +func (o *PARL_IO_Type) GetTX_DATA_CFG_TX_BUS_WID_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_DATA_CFG.Reg) & 0xe0000000) >> 29 +} + +// PARL_IO.TX_START_CFG: Parallel TX Start configuration register. +func (o *PARL_IO_Type) SetTX_START_CFG_TX_START(value uint32) { + volatile.StoreUint32(&o.TX_START_CFG.Reg, volatile.LoadUint32(&o.TX_START_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetTX_START_CFG_TX_START() uint32 { + return (volatile.LoadUint32(&o.TX_START_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.TX_GENRL_CFG: Parallel TX general configuration register. +func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_EOF_GEN_SEL(value uint32) { + volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_EOF_GEN_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x2000) >> 13 +} +func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_IDLE_VALUE(value uint32) { + volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x3fffc000)|value<<14) +} +func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_IDLE_VALUE() uint32 { + return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x3fffc000) >> 14 +} +func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_GATING_EN(value uint32) { + volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_GATING_EN() uint32 { + return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x40000000) >> 30 +} +func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_VALID_OUTPUT_EN(value uint32) { + volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_VALID_OUTPUT_EN() uint32 { + return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.FIFO_CFG: Parallel IO FIFO configuration register. +func (o *PARL_IO_Type) SetFIFO_CFG_TX_FIFO_SRST(value uint32) { + volatile.StoreUint32(&o.FIFO_CFG.Reg, volatile.LoadUint32(&o.FIFO_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetFIFO_CFG_TX_FIFO_SRST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CFG.Reg) & 0x40000000) >> 30 +} +func (o *PARL_IO_Type) SetFIFO_CFG_RX_FIFO_SRST(value uint32) { + volatile.StoreUint32(&o.FIFO_CFG.Reg, volatile.LoadUint32(&o.FIFO_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetFIFO_CFG_RX_FIFO_SRST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.REG_UPDATE: Parallel IO FIFO configuration register. +func (o *PARL_IO_Type) SetREG_UPDATE_RX_REG_UPDATE(value uint32) { + volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetREG_UPDATE_RX_REG_UPDATE() uint32 { + return (volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.ST: Parallel IO module status register0. +func (o *PARL_IO_Type) SetST_TX_READY(value uint32) { + volatile.StoreUint32(&o.ST.Reg, volatile.LoadUint32(&o.ST.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetST_TX_READY() uint32 { + return (volatile.LoadUint32(&o.ST.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.INT_ENA: Parallel IO interrupt enable singal configuration register. +func (o *PARL_IO_Type) SetINT_ENA_TX_FIFO_REMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_ENA_TX_FIFO_REMPTY_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_ENA_RX_FIFO_WOVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_ENA_RX_FIFO_WOVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_ENA_TX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_ENA_TX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// PARL_IO.INT_RAW: Parallel IO interrupt raw singal status register. +func (o *PARL_IO_Type) SetINT_RAW_TX_FIFO_REMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_RAW_TX_FIFO_REMPTY_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_RAW_RX_FIFO_WOVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_RAW_RX_FIFO_WOVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_RAW_TX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_RAW_TX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// PARL_IO.INT_ST: Parallel IO interrupt singal status register. +func (o *PARL_IO_Type) SetINT_ST_TX_FIFO_REMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_ST_TX_FIFO_REMPTY_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_ST_RX_FIFO_WOVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_ST_RX_FIFO_WOVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_ST_TX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_ST_TX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// PARL_IO.INT_CLR: Parallel IO interrupt clear singal configuration register. +func (o *PARL_IO_Type) SetINT_CLR_TX_FIFO_REMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PARL_IO_Type) GetINT_CLR_TX_FIFO_REMPTY_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PARL_IO_Type) SetINT_CLR_RX_FIFO_WOVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PARL_IO_Type) GetINT_CLR_RX_FIFO_WOVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PARL_IO_Type) SetINT_CLR_TX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PARL_IO_Type) GetINT_CLR_TX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// PARL_IO.RX_ST0: Parallel IO RX status register0 +func (o *PARL_IO_Type) SetRX_ST0_RX_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ST0.Reg, volatile.LoadUint32(&o.RX_ST0.Reg)&^(0x1f00)|value<<8) +} +func (o *PARL_IO_Type) GetRX_ST0_RX_CNT() uint32 { + return (volatile.LoadUint32(&o.RX_ST0.Reg) & 0x1f00) >> 8 +} +func (o *PARL_IO_Type) SetRX_ST0_RX_FIFO_WR_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ST0.Reg, volatile.LoadUint32(&o.RX_ST0.Reg)&^(0xffffe000)|value<<13) +} +func (o *PARL_IO_Type) GetRX_ST0_RX_FIFO_WR_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.RX_ST0.Reg) & 0xffffe000) >> 13 +} + +// PARL_IO.RX_ST1: Parallel IO RX status register1 +func (o *PARL_IO_Type) SetRX_ST1_RX_FIFO_RD_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ST1.Reg, volatile.LoadUint32(&o.RX_ST1.Reg)&^(0xffffe000)|value<<13) +} +func (o *PARL_IO_Type) GetRX_ST1_RX_FIFO_RD_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.RX_ST1.Reg) & 0xffffe000) >> 13 +} + +// PARL_IO.TX_ST0: Parallel IO TX status register0 +func (o *PARL_IO_Type) SetTX_ST0_TX_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ST0.Reg, volatile.LoadUint32(&o.TX_ST0.Reg)&^(0x1fc0)|value<<6) +} +func (o *PARL_IO_Type) GetTX_ST0_TX_CNT() uint32 { + return (volatile.LoadUint32(&o.TX_ST0.Reg) & 0x1fc0) >> 6 +} +func (o *PARL_IO_Type) SetTX_ST0_TX_FIFO_RD_BIT_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ST0.Reg, volatile.LoadUint32(&o.TX_ST0.Reg)&^(0xffffe000)|value<<13) +} +func (o *PARL_IO_Type) GetTX_ST0_TX_FIFO_RD_BIT_CNT() uint32 { + return (volatile.LoadUint32(&o.TX_ST0.Reg) & 0xffffe000) >> 13 +} + +// PARL_IO.RX_CLK_CFG: Parallel IO RX clk configuration register +func (o *PARL_IO_Type) SetRX_CLK_CFG_RX_CLK_I_INV(value uint32) { + volatile.StoreUint32(&o.RX_CLK_CFG.Reg, volatile.LoadUint32(&o.RX_CLK_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetRX_CLK_CFG_RX_CLK_I_INV() uint32 { + return (volatile.LoadUint32(&o.RX_CLK_CFG.Reg) & 0x40000000) >> 30 +} +func (o *PARL_IO_Type) SetRX_CLK_CFG_RX_CLK_O_INV(value uint32) { + volatile.StoreUint32(&o.RX_CLK_CFG.Reg, volatile.LoadUint32(&o.RX_CLK_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetRX_CLK_CFG_RX_CLK_O_INV() uint32 { + return (volatile.LoadUint32(&o.RX_CLK_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.TX_CLK_CFG: Parallel IO TX clk configuration register +func (o *PARL_IO_Type) SetTX_CLK_CFG_TX_CLK_I_INV(value uint32) { + volatile.StoreUint32(&o.TX_CLK_CFG.Reg, volatile.LoadUint32(&o.TX_CLK_CFG.Reg)&^(0x40000000)|value<<30) +} +func (o *PARL_IO_Type) GetTX_CLK_CFG_TX_CLK_I_INV() uint32 { + return (volatile.LoadUint32(&o.TX_CLK_CFG.Reg) & 0x40000000) >> 30 +} +func (o *PARL_IO_Type) SetTX_CLK_CFG_TX_CLK_O_INV(value uint32) { + volatile.StoreUint32(&o.TX_CLK_CFG.Reg, volatile.LoadUint32(&o.TX_CLK_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetTX_CLK_CFG_TX_CLK_O_INV() uint32 { + return (volatile.LoadUint32(&o.TX_CLK_CFG.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.CLK: Parallel IO clk configuration register +func (o *PARL_IO_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x80000000)|value<<31) +} +func (o *PARL_IO_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x80000000) >> 31 +} + +// PARL_IO.VERSION: Version register. +func (o *PARL_IO_Type) SetVERSION_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *PARL_IO_Type) GetVERSION_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// PAU Peripheral +type PAU_Type struct { + REGDMA_CONF volatile.Register32 // 0x0 + REGDMA_CLK_CONF volatile.Register32 // 0x4 + REGDMA_ETM_CTRL volatile.Register32 // 0x8 + REGDMA_LINK_0_ADDR volatile.Register32 // 0xC + REGDMA_LINK_1_ADDR volatile.Register32 // 0x10 + REGDMA_LINK_2_ADDR volatile.Register32 // 0x14 + REGDMA_LINK_3_ADDR volatile.Register32 // 0x18 + REGDMA_LINK_MAC_ADDR volatile.Register32 // 0x1C + REGDMA_CURRENT_LINK_ADDR volatile.Register32 // 0x20 + REGDMA_BACKUP_ADDR volatile.Register32 // 0x24 + REGDMA_MEM_ADDR volatile.Register32 // 0x28 + REGDMA_BKP_CONF volatile.Register32 // 0x2C + INT_ENA volatile.Register32 // 0x30 + INT_RAW volatile.Register32 // 0x34 + INT_CLR volatile.Register32 // 0x38 + INT_ST volatile.Register32 // 0x3C + _ [956]byte + DATE volatile.Register32 // 0x3FC +} + +// PAU.REGDMA_CONF: Peri backup control register +func (o *PAU_Type) SetREGDMA_CONF_FLOW_ERR(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x7)|value) +} +func (o *PAU_Type) GetREGDMA_CONF_FLOW_ERR() uint32 { + return volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x7 +} +func (o *PAU_Type) SetREGDMA_CONF_START(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PAU_Type) GetREGDMA_CONF_START() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x8) >> 3 +} +func (o *PAU_Type) SetREGDMA_CONF_TO_MEM(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x10)|value<<4) +} +func (o *PAU_Type) GetREGDMA_CONF_TO_MEM() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x10) >> 4 +} +func (o *PAU_Type) SetREGDMA_CONF_LINK_SEL(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x60)|value<<5) +} +func (o *PAU_Type) GetREGDMA_CONF_LINK_SEL() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x60) >> 5 +} +func (o *PAU_Type) SetREGDMA_CONF_START_MAC(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x80)|value<<7) +} +func (o *PAU_Type) GetREGDMA_CONF_START_MAC() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x80) >> 7 +} +func (o *PAU_Type) SetREGDMA_CONF_TO_MEM_MAC(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x100)|value<<8) +} +func (o *PAU_Type) GetREGDMA_CONF_TO_MEM_MAC() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x100) >> 8 +} +func (o *PAU_Type) SetREGDMA_CONF_SEL_MAC(value uint32) { + volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x200)|value<<9) +} +func (o *PAU_Type) GetREGDMA_CONF_SEL_MAC() uint32 { + return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x200) >> 9 +} + +// PAU.REGDMA_CLK_CONF: Clock control register +func (o *PAU_Type) SetREGDMA_CLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGDMA_CLK_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetREGDMA_CLK_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.REGDMA_CLK_CONF.Reg) & 0x1 +} + +// PAU.REGDMA_ETM_CTRL: ETM start ctrl reg +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_0(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_0() uint32 { + return volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x1 +} +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_1(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_1() uint32 { + return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x2) >> 1 +} +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_2(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_2() uint32 { + return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x4) >> 2 +} +func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_3(value uint32) { + volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_3() uint32 { + return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x8) >> 3 +} + +// PAU.REGDMA_LINK_0_ADDR: link_0_addr +func (o *PAU_Type) SetREGDMA_LINK_0_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_0_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_0_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_0_ADDR.Reg) +} + +// PAU.REGDMA_LINK_1_ADDR: Link_1_addr +func (o *PAU_Type) SetREGDMA_LINK_1_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_1_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_1_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_1_ADDR.Reg) +} + +// PAU.REGDMA_LINK_2_ADDR: Link_2_addr +func (o *PAU_Type) SetREGDMA_LINK_2_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_2_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_2_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_2_ADDR.Reg) +} + +// PAU.REGDMA_LINK_3_ADDR: Link_3_addr +func (o *PAU_Type) SetREGDMA_LINK_3_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_3_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_3_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_3_ADDR.Reg) +} + +// PAU.REGDMA_LINK_MAC_ADDR: Link_mac_addr +func (o *PAU_Type) SetREGDMA_LINK_MAC_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_LINK_MAC_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_LINK_MAC_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_LINK_MAC_ADDR.Reg) +} + +// PAU.REGDMA_CURRENT_LINK_ADDR: current link addr +func (o *PAU_Type) SetREGDMA_CURRENT_LINK_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_CURRENT_LINK_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_CURRENT_LINK_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_CURRENT_LINK_ADDR.Reg) +} + +// PAU.REGDMA_BACKUP_ADDR: Backup addr +func (o *PAU_Type) SetREGDMA_BACKUP_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_BACKUP_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_BACKUP_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_BACKUP_ADDR.Reg) +} + +// PAU.REGDMA_MEM_ADDR: mem addr +func (o *PAU_Type) SetREGDMA_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.REGDMA_MEM_ADDR.Reg, value) +} +func (o *PAU_Type) GetREGDMA_MEM_ADDR() uint32 { + return volatile.LoadUint32(&o.REGDMA_MEM_ADDR.Reg) +} + +// PAU.REGDMA_BKP_CONF: backup config +func (o *PAU_Type) SetREGDMA_BKP_CONF_READ_INTERVAL(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x7f)|value) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_READ_INTERVAL() uint32 { + return volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x7f +} +func (o *PAU_Type) SetREGDMA_BKP_CONF_LINK_TOUT_THRES(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x1ff80)|value<<7) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_LINK_TOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x1ff80) >> 7 +} +func (o *PAU_Type) SetREGDMA_BKP_CONF_BURST_LIMIT(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x3e0000)|value<<17) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_BURST_LIMIT() uint32 { + return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x3e0000) >> 17 +} +func (o *PAU_Type) SetREGDMA_BKP_CONF_BACKUP_TOUT_THRES(value uint32) { + volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0xffc00000)|value<<22) +} +func (o *PAU_Type) GetREGDMA_BKP_CONF_BACKUP_TOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0xffc00000) >> 22 +} + +// PAU.INT_ENA: Read only register for error and done +func (o *PAU_Type) SetINT_ENA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_ENA_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_ENA_ERROR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_ENA_ERROR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// PAU.INT_RAW: Read only register for error and done +func (o *PAU_Type) SetINT_RAW_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_RAW_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_RAW_ERROR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_RAW_ERROR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// PAU.INT_CLR: Read only register for error and done +func (o *PAU_Type) SetINT_CLR_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_CLR_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_CLR_ERROR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_CLR_ERROR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// PAU.INT_ST: Read only register for error and done +func (o *PAU_Type) SetINT_ST_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PAU_Type) GetINT_ST_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PAU_Type) SetINT_ST_ERROR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PAU_Type) GetINT_ST_ERROR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// PAU.DATE: Date register. +func (o *PAU_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *PAU_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Pulse Count Controller +type PCNT_Type struct { + U0_CONF0 volatile.Register32 // 0x0 + U0_CONF1 volatile.Register32 // 0x4 + U0_CONF2 volatile.Register32 // 0x8 + U1_CONF0 volatile.Register32 // 0xC + U1_CONF1 volatile.Register32 // 0x10 + U1_CONF2 volatile.Register32 // 0x14 + U2_CONF0 volatile.Register32 // 0x18 + U2_CONF1 volatile.Register32 // 0x1C + U2_CONF2 volatile.Register32 // 0x20 + U3_CONF0 volatile.Register32 // 0x24 + U3_CONF1 volatile.Register32 // 0x28 + U3_CONF2 volatile.Register32 // 0x2C + U0_CNT volatile.Register32 // 0x30 + U1_CNT volatile.Register32 // 0x34 + U2_CNT volatile.Register32 // 0x38 + U3_CNT volatile.Register32 // 0x3C + INT_RAW volatile.Register32 // 0x40 + INT_ST volatile.Register32 // 0x44 + INT_ENA volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + U0_STATUS volatile.Register32 // 0x50 + U1_STATUS volatile.Register32 // 0x54 + U2_STATUS volatile.Register32 // 0x58 + U3_STATUS volatile.Register32 // 0x5C + CTRL volatile.Register32 // 0x60 + U3_CHANGE_CONF volatile.Register32 // 0x64 + U2_CHANGE_CONF volatile.Register32 // 0x68 + U1_CHANGE_CONF volatile.Register32 // 0x6C + U0_CHANGE_CONF volatile.Register32 // 0x70 + _ [136]byte + DATE volatile.Register32 // 0xFC +} + +// PCNT.U0_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU0_CONF0_FILTER_THRES_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_THRES_U() uint32 { + return volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU0_CONF0_FILTER_EN_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_EN_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU0_CONF0_THR_ZERO_EN_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU0_CONF0_THR_ZERO_EN_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU0_CONF0_THR_H_LIM_EN_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU0_CONF0_THR_H_LIM_EN_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU0_CONF0_THR_L_LIM_EN_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU0_CONF0_THR_L_LIM_EN_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES0_EN_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES0_EN_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES1_EN_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES1_EN_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_NEG_MODE_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_NEG_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_POS_MODE_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_POS_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_HCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_HCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_LCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_LCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_NEG_MODE_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_NEG_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_POS_MODE_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_POS_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_HCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_HCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_LCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_LCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U0_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES0_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES0_U() uint32 { + return volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES1_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES1_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU0_CONF2_CNT_H_LIM_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_H_LIM_U() uint32 { + return volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF2_CNT_L_LIM_U(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_L_LIM_U() uint32 { + return (volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU1_CONF0_FILTER_THRES_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_THRES_U() uint32 { + return volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU1_CONF0_FILTER_EN_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_EN_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU1_CONF0_THR_ZERO_EN_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU1_CONF0_THR_ZERO_EN_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU1_CONF0_THR_H_LIM_EN_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU1_CONF0_THR_H_LIM_EN_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU1_CONF0_THR_L_LIM_EN_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU1_CONF0_THR_L_LIM_EN_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES0_EN_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES0_EN_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES1_EN_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES1_EN_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_NEG_MODE_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_NEG_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_POS_MODE_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_POS_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_HCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_HCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_LCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_LCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_NEG_MODE_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_NEG_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_POS_MODE_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_POS_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_HCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_HCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_LCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_LCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U1_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES0_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES0_U() uint32 { + return volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES1_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES1_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU1_CONF2_CNT_H_LIM_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_H_LIM_U() uint32 { + return volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF2_CNT_L_LIM_U(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_L_LIM_U() uint32 { + return (volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU2_CONF0_FILTER_THRES_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_THRES_U() uint32 { + return volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU2_CONF0_FILTER_EN_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_EN_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU2_CONF0_THR_ZERO_EN_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU2_CONF0_THR_ZERO_EN_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU2_CONF0_THR_H_LIM_EN_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU2_CONF0_THR_H_LIM_EN_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU2_CONF0_THR_L_LIM_EN_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU2_CONF0_THR_L_LIM_EN_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES0_EN_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES0_EN_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES1_EN_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES1_EN_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_NEG_MODE_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_NEG_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_POS_MODE_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_POS_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_HCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_HCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_LCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_LCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_NEG_MODE_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_NEG_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_POS_MODE_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_POS_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_HCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_HCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_LCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_LCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U2_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES0_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES0_U() uint32 { + return volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES1_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES1_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU2_CONF2_CNT_H_LIM_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_H_LIM_U() uint32 { + return volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF2_CNT_L_LIM_U(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_L_LIM_U() uint32 { + return (volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU3_CONF0_FILTER_THRES_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_THRES_U() uint32 { + return volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU3_CONF0_FILTER_EN_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_EN_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU3_CONF0_THR_ZERO_EN_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU3_CONF0_THR_ZERO_EN_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU3_CONF0_THR_H_LIM_EN_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU3_CONF0_THR_H_LIM_EN_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU3_CONF0_THR_L_LIM_EN_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU3_CONF0_THR_L_LIM_EN_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES0_EN_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES0_EN_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES1_EN_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES1_EN_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_NEG_MODE_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_NEG_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_POS_MODE_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_POS_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_HCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_HCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_LCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_LCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_NEG_MODE_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_NEG_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_POS_MODE_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_POS_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_HCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_HCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_LCTRL_MODE_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_LCTRL_MODE_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U3_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES0_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES0_U() uint32 { + return volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES1_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES1_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU3_CONF2_CNT_H_LIM_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_H_LIM_U() uint32 { + return volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF2_CNT_L_LIM_U(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_L_LIM_U() uint32 { + return (volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU0_CNT_PULSE_CNT_U(value uint32) { + volatile.StoreUint32(&o.U0_CNT.Reg, volatile.LoadUint32(&o.U0_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CNT_PULSE_CNT_U() uint32 { + return volatile.LoadUint32(&o.U0_CNT.Reg) & 0xffff +} + +// PCNT.U1_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU1_CNT_PULSE_CNT_U(value uint32) { + volatile.StoreUint32(&o.U1_CNT.Reg, volatile.LoadUint32(&o.U1_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CNT_PULSE_CNT_U() uint32 { + return volatile.LoadUint32(&o.U1_CNT.Reg) & 0xffff +} + +// PCNT.U2_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU2_CNT_PULSE_CNT_U(value uint32) { + volatile.StoreUint32(&o.U2_CNT.Reg, volatile.LoadUint32(&o.U2_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CNT_PULSE_CNT_U() uint32 { + return volatile.LoadUint32(&o.U2_CNT.Reg) & 0xffff +} + +// PCNT.U3_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU3_CNT_PULSE_CNT_U(value uint32) { + volatile.StoreUint32(&o.U3_CNT.Reg, volatile.LoadUint32(&o.U3_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CNT_PULSE_CNT_U() uint32 { + return volatile.LoadUint32(&o.U3_CNT.Reg) & 0xffff +} + +// PCNT.INT_RAW: Interrupt raw status register +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ST: Interrupt status register +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ENA: Interrupt enable register +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// PCNT.INT_CLR: Interrupt clear register +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// PCNT.U0_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU0_STATUS_CNT_THR_ZERO_MODE_U(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU0_STATUS_CNT_THR_ZERO_MODE_U() uint32 { + return volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU0_STATUS_CNT_THR_THRES1_LAT_U(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU0_STATUS_CNT_THR_THRES1_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU0_STATUS_CNT_THR_THRES0_LAT_U(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU0_STATUS_CNT_THR_THRES0_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU0_STATUS_CNT_THR_L_LIM_LAT_U(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU0_STATUS_CNT_THR_L_LIM_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU0_STATUS_CNT_THR_H_LIM_LAT_U(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU0_STATUS_CNT_THR_H_LIM_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU0_STATUS_CNT_THR_ZERO_LAT_U(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU0_STATUS_CNT_THR_ZERO_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U1_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU1_STATUS_CNT_THR_ZERO_MODE_U(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU1_STATUS_CNT_THR_ZERO_MODE_U() uint32 { + return volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU1_STATUS_CNT_THR_THRES1_LAT_U(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU1_STATUS_CNT_THR_THRES1_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU1_STATUS_CNT_THR_THRES0_LAT_U(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU1_STATUS_CNT_THR_THRES0_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU1_STATUS_CNT_THR_L_LIM_LAT_U(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU1_STATUS_CNT_THR_L_LIM_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU1_STATUS_CNT_THR_H_LIM_LAT_U(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU1_STATUS_CNT_THR_H_LIM_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU1_STATUS_CNT_THR_ZERO_LAT_U(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU1_STATUS_CNT_THR_ZERO_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U2_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU2_STATUS_CNT_THR_ZERO_MODE_U(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU2_STATUS_CNT_THR_ZERO_MODE_U() uint32 { + return volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU2_STATUS_CNT_THR_THRES1_LAT_U(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU2_STATUS_CNT_THR_THRES1_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU2_STATUS_CNT_THR_THRES0_LAT_U(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU2_STATUS_CNT_THR_THRES0_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU2_STATUS_CNT_THR_L_LIM_LAT_U(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU2_STATUS_CNT_THR_L_LIM_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU2_STATUS_CNT_THR_H_LIM_LAT_U(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU2_STATUS_CNT_THR_H_LIM_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU2_STATUS_CNT_THR_ZERO_LAT_U(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU2_STATUS_CNT_THR_ZERO_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U3_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU3_STATUS_CNT_THR_ZERO_MODE_U(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU3_STATUS_CNT_THR_ZERO_MODE_U() uint32 { + return volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU3_STATUS_CNT_THR_THRES1_LAT_U(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU3_STATUS_CNT_THR_THRES1_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU3_STATUS_CNT_THR_THRES0_LAT_U(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU3_STATUS_CNT_THR_THRES0_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU3_STATUS_CNT_THR_L_LIM_LAT_U(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU3_STATUS_CNT_THR_L_LIM_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU3_STATUS_CNT_THR_H_LIM_LAT_U(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU3_STATUS_CNT_THR_H_LIM_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU3_STATUS_CNT_THR_ZERO_LAT_U(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU3_STATUS_CNT_THR_ZERO_LAT_U() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.CTRL: Control register for all counters +func (o *PCNT_Type) SetCTRL_PULSE_CNT_RST_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetCTRL_PULSE_CNT_RST_U0() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U0() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetCTRL_PULSE_CNT_RST_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetCTRL_PULSE_CNT_RST_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetCTRL_PULSE_CNT_RST_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetCTRL_PULSE_CNT_RST_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetCTRL_PULSE_CNT_RST_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetCTRL_PULSE_CNT_RST_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *PCNT_Type) SetCTRL_DALTA_CHANGE_EN_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *PCNT_Type) GetCTRL_DALTA_CHANGE_EN_U0() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *PCNT_Type) SetCTRL_DALTA_CHANGE_EN_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *PCNT_Type) GetCTRL_DALTA_CHANGE_EN_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *PCNT_Type) SetCTRL_DALTA_CHANGE_EN_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetCTRL_DALTA_CHANGE_EN_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetCTRL_DALTA_CHANGE_EN_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetCTRL_DALTA_CHANGE_EN_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetCTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *PCNT_Type) GetCTRL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} + +// PCNT.U3_CHANGE_CONF: Configuration register for unit $n's step value. +func (o *PCNT_Type) SetU3_CHANGE_CONF_CNT_STEP_U3(value uint32) { + volatile.StoreUint32(&o.U3_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U3_CHANGE_CONF.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CHANGE_CONF_CNT_STEP_U3() uint32 { + return volatile.LoadUint32(&o.U3_CHANGE_CONF.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CHANGE_CONF_CNT_STEP_LIM_U3(value uint32) { + volatile.StoreUint32(&o.U3_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U3_CHANGE_CONF.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CHANGE_CONF_CNT_STEP_LIM_U3() uint32 { + return (volatile.LoadUint32(&o.U3_CHANGE_CONF.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CHANGE_CONF: Configuration register for unit $n's step value. +func (o *PCNT_Type) SetU2_CHANGE_CONF_CNT_STEP_U2(value uint32) { + volatile.StoreUint32(&o.U2_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U2_CHANGE_CONF.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CHANGE_CONF_CNT_STEP_U2() uint32 { + return volatile.LoadUint32(&o.U2_CHANGE_CONF.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CHANGE_CONF_CNT_STEP_LIM_U2(value uint32) { + volatile.StoreUint32(&o.U2_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U2_CHANGE_CONF.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CHANGE_CONF_CNT_STEP_LIM_U2() uint32 { + return (volatile.LoadUint32(&o.U2_CHANGE_CONF.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CHANGE_CONF: Configuration register for unit $n's step value. +func (o *PCNT_Type) SetU1_CHANGE_CONF_CNT_STEP_U1(value uint32) { + volatile.StoreUint32(&o.U1_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U1_CHANGE_CONF.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CHANGE_CONF_CNT_STEP_U1() uint32 { + return volatile.LoadUint32(&o.U1_CHANGE_CONF.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CHANGE_CONF_CNT_STEP_LIM_U1(value uint32) { + volatile.StoreUint32(&o.U1_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U1_CHANGE_CONF.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CHANGE_CONF_CNT_STEP_LIM_U1() uint32 { + return (volatile.LoadUint32(&o.U1_CHANGE_CONF.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CHANGE_CONF: Configuration register for unit $n's step value. +func (o *PCNT_Type) SetU0_CHANGE_CONF_CNT_STEP_U0(value uint32) { + volatile.StoreUint32(&o.U0_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U0_CHANGE_CONF.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CHANGE_CONF_CNT_STEP_U0() uint32 { + return volatile.LoadUint32(&o.U0_CHANGE_CONF.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CHANGE_CONF_CNT_STEP_LIM_U0(value uint32) { + volatile.StoreUint32(&o.U0_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U0_CHANGE_CONF.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CHANGE_CONF_CNT_STEP_LIM_U0() uint32 { + return (volatile.LoadUint32(&o.U0_CHANGE_CONF.Reg) & 0xffff0000) >> 16 +} + +// PCNT.DATE: PCNT version control register +func (o *PCNT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *PCNT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// PMU Peripheral +type PMU_Type struct { + HP_ACTIVE_DIG_POWER volatile.Register32 // 0x0 + HP_ACTIVE_ICG_HP_FUNC volatile.Register32 // 0x4 + HP_ACTIVE_ICG_HP_APB volatile.Register32 // 0x8 + HP_ACTIVE_ICG_MODEM volatile.Register32 // 0xC + HP_ACTIVE_HP_SYS_CNTL volatile.Register32 // 0x10 + HP_ACTIVE_HP_CK_POWER volatile.Register32 // 0x14 + HP_ACTIVE_BIAS volatile.Register32 // 0x18 + HP_ACTIVE_BACKUP volatile.Register32 // 0x1C + HP_ACTIVE_BACKUP_CLK volatile.Register32 // 0x20 + HP_ACTIVE_SYSCLK volatile.Register32 // 0x24 + HP_ACTIVE_HP_REGULATOR0 volatile.Register32 // 0x28 + HP_ACTIVE_HP_REGULATOR1 volatile.Register32 // 0x2C + HP_ACTIVE_XTAL volatile.Register32 // 0x30 + HP_MODEM_DIG_POWER volatile.Register32 // 0x34 + HP_MODEM_ICG_HP_FUNC volatile.Register32 // 0x38 + HP_MODEM_ICG_HP_APB volatile.Register32 // 0x3C + HP_MODEM_ICG_MODEM volatile.Register32 // 0x40 + HP_MODEM_HP_SYS_CNTL volatile.Register32 // 0x44 + HP_MODEM_HP_CK_POWER volatile.Register32 // 0x48 + HP_MODEM_BIAS volatile.Register32 // 0x4C + HP_MODEM_BACKUP volatile.Register32 // 0x50 + HP_MODEM_BACKUP_CLK volatile.Register32 // 0x54 + HP_MODEM_SYSCLK volatile.Register32 // 0x58 + HP_MODEM_HP_REGULATOR0 volatile.Register32 // 0x5C + HP_MODEM_HP_REGULATOR1 volatile.Register32 // 0x60 + HP_MODEM_XTAL volatile.Register32 // 0x64 + HP_SLEEP_DIG_POWER volatile.Register32 // 0x68 + HP_SLEEP_ICG_HP_FUNC volatile.Register32 // 0x6C + HP_SLEEP_ICG_HP_APB volatile.Register32 // 0x70 + HP_SLEEP_ICG_MODEM volatile.Register32 // 0x74 + HP_SLEEP_HP_SYS_CNTL volatile.Register32 // 0x78 + HP_SLEEP_HP_CK_POWER volatile.Register32 // 0x7C + HP_SLEEP_BIAS volatile.Register32 // 0x80 + HP_SLEEP_BACKUP volatile.Register32 // 0x84 + HP_SLEEP_BACKUP_CLK volatile.Register32 // 0x88 + HP_SLEEP_SYSCLK volatile.Register32 // 0x8C + HP_SLEEP_HP_REGULATOR0 volatile.Register32 // 0x90 + HP_SLEEP_HP_REGULATOR1 volatile.Register32 // 0x94 + HP_SLEEP_XTAL volatile.Register32 // 0x98 + HP_SLEEP_LP_REGULATOR0 volatile.Register32 // 0x9C + HP_SLEEP_LP_REGULATOR1 volatile.Register32 // 0xA0 + HP_SLEEP_LP_DCDC_RESERVE volatile.Register32 // 0xA4 + HP_SLEEP_LP_DIG_POWER volatile.Register32 // 0xA8 + HP_SLEEP_LP_CK_POWER volatile.Register32 // 0xAC + LP_SLEEP_LP_BIAS_RESERVE volatile.Register32 // 0xB0 + LP_SLEEP_LP_REGULATOR0 volatile.Register32 // 0xB4 + LP_SLEEP_LP_REGULATOR1 volatile.Register32 // 0xB8 + LP_SLEEP_XTAL volatile.Register32 // 0xBC + LP_SLEEP_LP_DIG_POWER volatile.Register32 // 0xC0 + LP_SLEEP_LP_CK_POWER volatile.Register32 // 0xC4 + LP_SLEEP_BIAS volatile.Register32 // 0xC8 + IMM_HP_CK_POWER volatile.Register32 // 0xCC + IMM_SLEEP_SYSCLK volatile.Register32 // 0xD0 + IMM_HP_FUNC_ICG volatile.Register32 // 0xD4 + IMM_HP_APB_ICG volatile.Register32 // 0xD8 + IMM_MODEM_ICG volatile.Register32 // 0xDC + IMM_LP_ICG volatile.Register32 // 0xE0 + IMM_PAD_HOLD_ALL volatile.Register32 // 0xE4 + IMM_I2C_ISO volatile.Register32 // 0xE8 + POWER_WAIT_TIMER0 volatile.Register32 // 0xEC + POWER_WAIT_TIMER1 volatile.Register32 // 0xF0 + POWER_PD_TOP_CNTL volatile.Register32 // 0xF4 + POWER_PD_CNNT_CNTL volatile.Register32 // 0xF8 + POWER_PD_HPMEM_CNTL volatile.Register32 // 0xFC + POWER_PD_TOP_MASK volatile.Register32 // 0x100 + POWER_PD_CNNT_MASK volatile.Register32 // 0x104 + POWER_PD_HPMEM_MASK volatile.Register32 // 0x108 + POWER_DCDC_SWITCH volatile.Register32 // 0x10C + POWER_PD_LPPERI_CNTL volatile.Register32 // 0x110 + POWER_PD_LPPERI_MASK volatile.Register32 // 0x114 + POWER_HP_PAD volatile.Register32 // 0x118 + POWER_CK_WAIT_CNTL volatile.Register32 // 0x11C + SLP_WAKEUP_CNTL0 volatile.Register32 // 0x120 + SLP_WAKEUP_CNTL1 volatile.Register32 // 0x124 + SLP_WAKEUP_CNTL2 volatile.Register32 // 0x128 + SLP_WAKEUP_CNTL3 volatile.Register32 // 0x12C + SLP_WAKEUP_CNTL4 volatile.Register32 // 0x130 + SLP_WAKEUP_CNTL5 volatile.Register32 // 0x134 + SLP_WAKEUP_CNTL6 volatile.Register32 // 0x138 + SLP_WAKEUP_CNTL7 volatile.Register32 // 0x13C + SLP_WAKEUP_CNTL8 volatile.Register32 // 0x140 + SLP_WAKEUP_STATUS0 volatile.Register32 // 0x144 + SLP_WAKEUP_STATUS1 volatile.Register32 // 0x148 + SLP_WAKEUP_STATUS2 volatile.Register32 // 0x14C + HP_CK_POWERON volatile.Register32 // 0x150 + HP_CK_CNTL volatile.Register32 // 0x154 + POR_STATUS volatile.Register32 // 0x158 + RF_PWC volatile.Register32 // 0x15C + BACKUP_CFG volatile.Register32 // 0x160 + INT_RAW volatile.Register32 // 0x164 + HP_INT_ST volatile.Register32 // 0x168 + HP_INT_ENA volatile.Register32 // 0x16C + HP_INT_CLR volatile.Register32 // 0x170 + LP_INT_RAW volatile.Register32 // 0x174 + LP_INT_ST volatile.Register32 // 0x178 + LP_INT_ENA volatile.Register32 // 0x17C + LP_INT_CLR volatile.Register32 // 0x180 + LP_CPU_PWR0 volatile.Register32 // 0x184 + LP_CPU_PWR1 volatile.Register32 // 0x188 + LP_CPU_PWR2 volatile.Register32 // 0x18C + LP_CPU_PWR3 volatile.Register32 // 0x190 + LP_CPU_PWR4 volatile.Register32 // 0x194 + LP_CPU_PWR5 volatile.Register32 // 0x198 + HP_LP_CPU_COMM volatile.Register32 // 0x19C + HP_REGULATOR_CFG volatile.Register32 // 0x1A0 + MAIN_STATE volatile.Register32 // 0x1A4 + PWR_STATE volatile.Register32 // 0x1A8 + CLK_STATE0 volatile.Register32 // 0x1AC + CLK_STATE1 volatile.Register32 // 0x1B0 + CLK_STATE2 volatile.Register32 // 0x1B4 + EXT_LDO_P0_0P1A volatile.Register32 // 0x1B8 + EXT_LDO_P0_0P1A_ANA volatile.Register32 // 0x1BC + EXT_LDO_P0_0P2A volatile.Register32 // 0x1C0 + EXT_LDO_P0_0P2A_ANA volatile.Register32 // 0x1C4 + EXT_LDO_P0_0P3A volatile.Register32 // 0x1C8 + EXT_LDO_P0_0P3A_ANA volatile.Register32 // 0x1CC + EXT_LDO_P1_0P1A volatile.Register32 // 0x1D0 + EXT_LDO_P1_0P1A_ANA volatile.Register32 // 0x1D4 + EXT_LDO_P1_0P2A volatile.Register32 // 0x1D8 + EXT_LDO_P1_0P2A_ANA volatile.Register32 // 0x1DC + EXT_LDO_P1_0P3A volatile.Register32 // 0x1E0 + EXT_LDO_P1_0P3A_ANA volatile.Register32 // 0x1E4 + EXT_WAKEUP_LV volatile.Register32 // 0x1E8 + EXT_WAKEUP_SEL volatile.Register32 // 0x1EC + EXT_WAKEUP_ST volatile.Register32 // 0x1F0 + EXT_WAKEUP_CNTL volatile.Register32 // 0x1F4 + SDIO_WAKEUP_CNTL volatile.Register32 // 0x1F8 + XTAL_SLP volatile.Register32 // 0x1FC + CPU_SW_STALL volatile.Register32 // 0x200 + DCM_CTRL volatile.Register32 // 0x204 + DCM_WAIT_DELAY volatile.Register32 // 0x208 + VDDBAT_CFG volatile.Register32 // 0x20C + TOUCH_PWR_CNTL volatile.Register32 // 0x210 + RDN_ECO volatile.Register32 // 0x214 + _ [484]byte + DATE volatile.Register32 // 0x3FC +} + +// PMU.HP_ACTIVE_DIG_POWER: need_des +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_DCDC_SWITCH_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_DCDC_SWITCH_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_CNNT_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_CNNT_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_ACTIVE_ICG_HP_FUNC: need_des +func (o *PMU_Type) SetHP_ACTIVE_ICG_HP_FUNC(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_ICG_HP_FUNC.Reg, value) +} +func (o *PMU_Type) GetHP_ACTIVE_ICG_HP_FUNC() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_ICG_HP_FUNC.Reg) +} + +// PMU.HP_ACTIVE_ICG_HP_APB: need_des +func (o *PMU_Type) SetHP_ACTIVE_ICG_HP_APB(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_ICG_HP_APB.Reg, value) +} +func (o *PMU_Type) GetHP_ACTIVE_ICG_HP_APB() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_ICG_HP_APB.Reg) +} + +// PMU.HP_ACTIVE_ICG_MODEM: need_des +func (o *PMU_Type) SetHP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_ACTIVE_ICG_MODEM.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_ICG_MODEM.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_ACTIVE_HP_SYS_CNTL: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_POWER_DET_BYPASS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_POWER_DET_BYPASS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_ACTIVE_HP_CK_POWER: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL_I2C(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x78000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x78000000) >> 27 +} + +// PMU.HP_ACTIVE_BIAS: need_des +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_DCM_VSET(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x7c0000)|value<<18) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_DCM_VSET() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x7c0000) >> 18 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_DCM_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x1800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_DCM_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x1800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x3c000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x3c000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_ACTIVE_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_ACTIVE_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_ACTIVE_BACKUP: need_des +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x30)|value<<4) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x30) >> 4 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0xc0)|value<<6) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0xc0) >> 6 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x800)|value<<11) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x800) >> 11 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0xc000)|value<<14) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0xc000) >> 14 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x30000) >> 16 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x700000)|value<<20) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x700000) >> 20 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x40000000) >> 30 +} + +// PMU.HP_ACTIVE_BACKUP_CLK: need_des +func (o *PMU_Type) SetHP_ACTIVE_BACKUP_CLK(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_BACKUP_CLK.Reg, value) +} +func (o *PMU_Type) GetHP_ACTIVE_BACKUP_CLK() uint32 { + return volatile.LoadUint32(&o.HP_ACTIVE_BACKUP_CLK.Reg) +} + +// PMU.HP_ACTIVE_SYSCLK: need_des +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_ACTIVE_HP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x1f0)|value<<4) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x1f0) >> 4 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x3e00)|value<<9) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x3e00) >> 9 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x780000)|value<<19) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x780000) >> 19 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_ACTIVE_HP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg)&^(0xfc000000)|value<<26) +} +func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg) & 0xfc000000) >> 26 +} + +// PMU.HP_ACTIVE_XTAL: need_des +func (o *PMU_Type) SetHP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.HP_ACTIVE_XTAL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.HP_ACTIVE_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_MODEM_DIG_POWER: need_des +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_DCDC_SWITCH_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_DCDC_SWITCH_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_CNNT_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_CNNT_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_MODEM_ICG_HP_FUNC: need_des +func (o *PMU_Type) SetHP_MODEM_ICG_HP_FUNC(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_ICG_HP_FUNC.Reg, value) +} +func (o *PMU_Type) GetHP_MODEM_ICG_HP_FUNC() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_ICG_HP_FUNC.Reg) +} + +// PMU.HP_MODEM_ICG_HP_APB: need_des +func (o *PMU_Type) SetHP_MODEM_ICG_HP_APB(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_ICG_HP_APB.Reg, value) +} +func (o *PMU_Type) GetHP_MODEM_ICG_HP_APB() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_ICG_HP_APB.Reg) +} + +// PMU.HP_MODEM_ICG_MODEM: need_des +func (o *PMU_Type) SetHP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_MODEM_ICG_MODEM.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_ICG_MODEM.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_MODEM_HP_SYS_CNTL: need_des +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_POWER_DET_BYPASS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_POWER_DET_BYPASS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_MODEM_HP_CK_POWER: need_des +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL_I2C(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x78000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x78000000) >> 27 +} + +// PMU.HP_MODEM_BIAS: need_des +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_DCM_VSET(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x7c0000)|value<<18) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_DCM_VSET() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x7c0000) >> 18 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_DCM_MODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x1800000)|value<<23) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_DCM_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x1800000) >> 23 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_DBG_ATTEN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x3c000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_DBG_ATTEN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x3c000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_PD_CUR(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_MODEM_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_MODEM_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_MODEM_BACKUP: need_des +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x30)|value<<4) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x30) >> 4 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x800)|value<<11) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x800) >> 11 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0xc000)|value<<14) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0xc000) >> 14 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x700000)|value<<20) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x700000) >> 20 +} +func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_MODEM_BACKUP_CLK: need_des +func (o *PMU_Type) SetHP_MODEM_BACKUP_CLK(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_BACKUP_CLK.Reg, value) +} +func (o *PMU_Type) GetHP_MODEM_BACKUP_CLK() uint32 { + return volatile.LoadUint32(&o.HP_MODEM_BACKUP_CLK.Reg) +} + +// PMU.HP_MODEM_SYSCLK: need_des +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_MODEM_HP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x780000)|value<<19) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x780000) >> 19 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_MODEM_HP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR1.Reg)&^(0xffffff00)|value<<8) +} +func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR1.Reg) & 0xffffff00) >> 8 +} + +// PMU.HP_MODEM_XTAL: need_des +func (o *PMU_Type) SetHP_MODEM_XTAL_HP_MODEM_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.HP_MODEM_XTAL.Reg, volatile.LoadUint32(&o.HP_MODEM_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_MODEM_XTAL_HP_MODEM_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.HP_MODEM_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_DIG_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_DCDC_SWITCH_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_DCDC_SWITCH_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_CNNT_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_CNNT_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_ICG_HP_FUNC: need_des +func (o *PMU_Type) SetHP_SLEEP_ICG_HP_FUNC(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_ICG_HP_FUNC.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_ICG_HP_FUNC() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_ICG_HP_FUNC.Reg) +} + +// PMU.HP_SLEEP_ICG_HP_APB: need_des +func (o *PMU_Type) SetHP_SLEEP_ICG_HP_APB(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_ICG_HP_APB.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_ICG_HP_APB() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_ICG_HP_APB.Reg) +} + +// PMU.HP_SLEEP_ICG_MODEM: need_des +func (o *PMU_Type) SetHP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_SLEEP_ICG_MODEM.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_ICG_MODEM.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_SLEEP_HP_SYS_CNTL: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_POWER_DET_BYPASS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_POWER_DET_BYPASS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x20000000) >> 29 +} + +// PMU.HP_SLEEP_HP_CK_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL_I2C(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL_I2C() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x78000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x78000000) >> 27 +} + +// PMU.HP_SLEEP_BIAS: need_des +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_DCM_VSET(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x7c0000)|value<<18) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_DCM_VSET() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x7c0000) >> 18 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_DCM_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x1800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_DCM_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x1800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x3c000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x3c000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_PD_CUR(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_BACKUP: need_des +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0xc0)|value<<6) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0xc0) >> 6 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x300)|value<<8) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x300) >> 8 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x30000) >> 16 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0xc0000)|value<<18) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0xc0000) >> 18 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x1c000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x1c000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_BACKUP_CLK: need_des +func (o *PMU_Type) SetHP_SLEEP_BACKUP_CLK(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_BACKUP_CLK.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_BACKUP_CLK() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_BACKUP_CLK.Reg) +} + +// PMU.HP_SLEEP_SYSCLK: need_des +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0xc0000000) >> 30 +} + +// PMU.HP_SLEEP_HP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x780000)|value<<19) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x780000) >> 19 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_SLEEP_HP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg)&^(0xfc000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg) & 0xfc000000) >> 26 +} + +// PMU.HP_SLEEP_XTAL: need_des +func (o *PMU_Type) SetHP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_XTAL.Reg, volatile.LoadUint32(&o.HP_SLEEP_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_LP_REGULATOR0: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.HP_SLEEP_LP_REGULATOR1: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg)&^(0xfc000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg) & 0xfc000000) >> 26 +} + +// PMU.HP_SLEEP_LP_DCDC_RESERVE: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_DCDC_RESERVE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DCDC_RESERVE.Reg, value) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DCDC_RESERVE() uint32 { + return volatile.LoadUint32(&o.HP_SLEEP_LP_DCDC_RESERVE.Reg) +} + +// PMU.HP_SLEEP_LP_DIG_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x30000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x30000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_SLEEP_LP_CK_POWER: need_des +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK(value uint32) { + volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK() uint32 { + return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_LP_BIAS_RESERVE: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_BIAS_RESERVE(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_BIAS_RESERVE.Reg, value) +} +func (o *PMU_Type) GetLP_SLEEP_LP_BIAS_RESERVE() uint32 { + return volatile.LoadUint32(&o.LP_SLEEP_LP_BIAS_RESERVE.Reg) +} + +// PMU.LP_SLEEP_LP_REGULATOR0: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0xf8000000) >> 27 +} + +// PMU.LP_SLEEP_LP_REGULATOR1: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg)&^(0xfc000000)|value<<26) +} +func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg) & 0xfc000000) >> 26 +} + +// PMU.LP_SLEEP_XTAL: need_des +func (o *PMU_Type) SetLP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_XTAL.Reg, volatile.LoadUint32(&o.LP_SLEEP_XTAL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_XTAL.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_LP_DIG_POWER: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x30000000)|value<<28) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x30000000) >> 28 +} +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_LP_CK_POWER: need_des +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_SLEEP_BIAS: need_des +func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x3c000000)|value<<26) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x3c000000) >> 26 +} +func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_PD_CUR(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_PD_CUR() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_SLEEP_BIAS_SLEEP(value uint32) { + volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_SLEEP_BIAS_SLEEP() uint32 { + return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_HP_CK_POWER: need_des +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_CALI_XTAL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_CALI_XTAL_ICG() uint32 { + return volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x1 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_PLL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x1e)|value<<1) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_PLL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x1e) >> 1 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x20) >> 5 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x40)|value<<6) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x40) >> 6 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_PLL_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x780)|value<<7) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_PLL_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x780) >> 7 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_PLL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x7800)|value<<11) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_PLL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x7800) >> 11 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_CALI_XTAL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_CALI_XTAL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_PLL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x1e0000)|value<<17) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_PLL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x1e0000) >> 17 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_PLL_I2C(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x7800000)|value<<23) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_PLL_I2C() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x7800000) >> 23 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_PLL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x78000000)|value<<27) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_PLL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x78000000) >> 27 +} +func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL(value uint32) { + volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_SLEEP_SYSCLK: need_des +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_HP_FUNC_ICG: need_des +func (o *PMU_Type) SetIMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN(value uint32) { + volatile.StoreUint32(&o.IMM_HP_FUNC_ICG.Reg, volatile.LoadUint32(&o.IMM_HP_FUNC_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_FUNC_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_HP_APB_ICG: need_des +func (o *PMU_Type) SetIMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN(value uint32) { + volatile.StoreUint32(&o.IMM_HP_APB_ICG.Reg, volatile.LoadUint32(&o.IMM_HP_APB_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_HP_APB_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_MODEM_ICG: need_des +func (o *PMU_Type) SetIMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN(value uint32) { + volatile.StoreUint32(&o.IMM_MODEM_ICG.Reg, volatile.LoadUint32(&o.IMM_MODEM_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_MODEM_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_LP_ICG: need_des +func (o *PMU_Type) SetIMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_LP_ICG.Reg, volatile.LoadUint32(&o.IMM_LP_ICG.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_LP_ICG.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_LP_ICG.Reg, volatile.LoadUint32(&o.IMM_LP_ICG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_LP_ICG.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_PAD_HOLD_ALL: need_des +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_PAD_SLP_SEL() uint32 { + return volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x1 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_PAD_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_PAD_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL(value uint32) { + volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL() uint32 { + return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x80000000) >> 31 +} + +// PMU.IMM_I2C_ISO: need_des +func (o *PMU_Type) SetIMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.IMM_I2C_ISO.Reg, volatile.LoadUint32(&o.IMM_I2C_ISO.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetIMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_I2C_ISO.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetIMM_I2C_ISO_TIE_LOW_I2C_ISO_EN(value uint32) { + volatile.StoreUint32(&o.IMM_I2C_ISO.Reg, volatile.LoadUint32(&o.IMM_I2C_ISO.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetIMM_I2C_ISO_TIE_LOW_I2C_ISO_EN() uint32 { + return (volatile.LoadUint32(&o.IMM_I2C_ISO.Reg) & 0x80000000) >> 31 +} + +// PMU.POWER_WAIT_TIMER0: need_des +func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0x3fe0)|value<<5) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0x3fe0) >> 5 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0x7fc000)|value<<14) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0x7fc000) >> 14 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0xff800000)|value<<23) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0xff800000) >> 23 +} + +// PMU.POWER_WAIT_TIMER1: need_des +func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0x3fe0)|value<<5) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0x3fe0) >> 5 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0x7fc000)|value<<14) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0x7fc000) >> 14 +} +func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0xff800000)|value<<23) +} +func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0xff800000) >> 23 +} + +// PMU.POWER_PD_TOP_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x20) >> 5 +} + +// PMU.POWER_PD_CNNT_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x20) >> 5 +} + +// PMU.POWER_PD_HPMEM_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x20) >> 5 +} + +// PMU.POWER_PD_TOP_MASK: need_des +func (o *PMU_Type) SetPOWER_PD_TOP_MASK_XPD_TOP_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_MASK.Reg)&^(0x1f)|value) +} +func (o *PMU_Type) GetPOWER_PD_TOP_MASK_XPD_TOP_MASK() uint32 { + return volatile.LoadUint32(&o.POWER_PD_TOP_MASK.Reg) & 0x1f +} +func (o *PMU_Type) SetPOWER_PD_TOP_MASK_PD_TOP_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_TOP_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_MASK.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_TOP_MASK_PD_TOP_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_TOP_MASK.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_CNNT_MASK: need_des +func (o *PMU_Type) SetPOWER_PD_CNNT_MASK_XPD_CNNT_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_CNNT_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_MASK.Reg)&^(0x1f)|value) +} +func (o *PMU_Type) GetPOWER_PD_CNNT_MASK_XPD_CNNT_MASK() uint32 { + return volatile.LoadUint32(&o.POWER_PD_CNNT_MASK.Reg) & 0x1f +} +func (o *PMU_Type) SetPOWER_PD_CNNT_MASK_PD_CNNT_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_CNNT_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_MASK.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_CNNT_MASK_PD_CNNT_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_CNNT_MASK.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_PD_HPMEM_MASK: need_des +func (o *PMU_Type) SetPOWER_PD_HPMEM_MASK_XPD_HP_MEM_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPMEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_MASK.Reg)&^(0x3f)|value) +} +func (o *PMU_Type) GetPOWER_PD_HPMEM_MASK_XPD_HP_MEM_MASK() uint32 { + return volatile.LoadUint32(&o.POWER_PD_HPMEM_MASK.Reg) & 0x3f +} +func (o *PMU_Type) SetPOWER_PD_HPMEM_MASK_PD_HP_MEM_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_HPMEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_MASK.Reg)&^(0xfc000000)|value<<26) +} +func (o *PMU_Type) GetPOWER_PD_HPMEM_MASK_PD_HP_MEM_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_HPMEM_MASK.Reg) & 0xfc000000) >> 26 +} + +// PMU.POWER_DCDC_SWITCH: need_des +func (o *PMU_Type) SetPOWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PU(value uint32) { + volatile.StoreUint32(&o.POWER_DCDC_SWITCH.Reg, volatile.LoadUint32(&o.POWER_DCDC_SWITCH.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PU() uint32 { + return volatile.LoadUint32(&o.POWER_DCDC_SWITCH.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PD(value uint32) { + volatile.StoreUint32(&o.POWER_DCDC_SWITCH.Reg, volatile.LoadUint32(&o.POWER_DCDC_SWITCH.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_DCDC_SWITCH.Reg) & 0x2) >> 1 +} + +// PMU.POWER_PD_LPPERI_CNTL: need_des +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET() uint32 { + return volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x10)|value<<4) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x10) >> 4 +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x20)|value<<5) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x20) >> 5 +} + +// PMU.POWER_PD_LPPERI_MASK: need_des +func (o *PMU_Type) SetPOWER_PD_LPPERI_MASK_XPD_LP_PERI_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_MASK.Reg)&^(0x1f)|value) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_MASK_XPD_LP_PERI_MASK() uint32 { + return volatile.LoadUint32(&o.POWER_PD_LPPERI_MASK.Reg) & 0x1f +} +func (o *PMU_Type) SetPOWER_PD_LPPERI_MASK_PD_LP_PERI_MASK(value uint32) { + volatile.StoreUint32(&o.POWER_PD_LPPERI_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_MASK.Reg)&^(0xf8000000)|value<<27) +} +func (o *PMU_Type) GetPOWER_PD_LPPERI_MASK_PD_LP_PERI_MASK() uint32 { + return (volatile.LoadUint32(&o.POWER_PD_LPPERI_MASK.Reg) & 0xf8000000) >> 27 +} + +// PMU.POWER_HP_PAD: need_des +func (o *PMU_Type) SetPOWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL(value uint32) { + volatile.StoreUint32(&o.POWER_HP_PAD.Reg, volatile.LoadUint32(&o.POWER_HP_PAD.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetPOWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL() uint32 { + return volatile.LoadUint32(&o.POWER_HP_PAD.Reg) & 0x1 +} +func (o *PMU_Type) SetPOWER_HP_PAD_FORCE_HP_PAD_ISO_ALL(value uint32) { + volatile.StoreUint32(&o.POWER_HP_PAD.Reg, volatile.LoadUint32(&o.POWER_HP_PAD.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetPOWER_HP_PAD_FORCE_HP_PAD_ISO_ALL() uint32 { + return (volatile.LoadUint32(&o.POWER_HP_PAD.Reg) & 0x2) >> 1 +} + +// PMU.POWER_CK_WAIT_CNTL: need_des +func (o *PMU_Type) SetPOWER_CK_WAIT_CNTL_PMU_WAIT_XTL_STABLE(value uint32) { + volatile.StoreUint32(&o.POWER_CK_WAIT_CNTL.Reg, volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg)&^(0xffff)|value) +} +func (o *PMU_Type) GetPOWER_CK_WAIT_CNTL_PMU_WAIT_XTL_STABLE() uint32 { + return volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg) & 0xffff +} +func (o *PMU_Type) SetPOWER_CK_WAIT_CNTL_PMU_WAIT_PLL_STABLE(value uint32) { + volatile.StoreUint32(&o.POWER_CK_WAIT_CNTL.Reg, volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg)&^(0xffff0000)|value<<16) +} +func (o *PMU_Type) GetPOWER_CK_WAIT_CNTL_PMU_WAIT_PLL_STABLE() uint32 { + return (volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg) & 0xffff0000) >> 16 +} + +// PMU.SLP_WAKEUP_CNTL0: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL0_SLEEP_REQ(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL0.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL0.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL0_SLEEP_REQ() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL0.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_CNTL1: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg) & 0x7fffffff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL1_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL1_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_CNTL2: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL2_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL2.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL2.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL2_WAKEUP_ENA() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL2.Reg) & 0x7fffffff +} + +// PMU.SLP_WAKEUP_CNTL3: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0xff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0xff00)|value<<8) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0xff00) >> 8 +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_SLEEP_PRT_SEL(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_SLEEP_PRT_SEL() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0x30000) >> 16 +} + +// PMU.SLP_WAKEUP_CNTL4: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL4.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL4.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL4.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_CNTL5: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL5.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg)&^(0xfffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg) & 0xfffff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL5.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg)&^(0xff000000)|value<<24) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg) & 0xff000000) >> 24 +} + +// PMU.SLP_WAKEUP_CNTL6: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL6.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg)&^(0xfffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg) & 0xfffff +} +func (o *PMU_Type) SetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL6.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg)&^(0xc0000000)|value<<30) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg) & 0xc0000000) >> 30 +} + +// PMU.SLP_WAKEUP_CNTL7: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL7_ANA_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL7.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL7.Reg)&^(0xffff0000)|value<<16) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL7_ANA_WAIT_TARGET() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL7.Reg) & 0xffff0000) >> 16 +} + +// PMU.SLP_WAKEUP_CNTL8: need_des +func (o *PMU_Type) SetSLP_WAKEUP_CNTL8_LP_LITE_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CNTL8.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL8.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_CNTL8_LP_LITE_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL8.Reg) & 0x80000000) >> 31 +} + +// PMU.SLP_WAKEUP_STATUS0: need_des +func (o *PMU_Type) SetSLP_WAKEUP_STATUS0_WAKEUP_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_STATUS0.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_STATUS0.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_STATUS0_WAKEUP_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_STATUS0.Reg) & 0x7fffffff +} + +// PMU.SLP_WAKEUP_STATUS1: need_des +func (o *PMU_Type) SetSLP_WAKEUP_STATUS1_REJECT_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_STATUS1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_STATUS1.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetSLP_WAKEUP_STATUS1_REJECT_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_STATUS1.Reg) & 0x7fffffff +} + +// PMU.SLP_WAKEUP_STATUS2: need_des +func (o *PMU_Type) SetSLP_WAKEUP_STATUS2_LP_LITE_WAKEUP_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_STATUS2.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_STATUS2.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetSLP_WAKEUP_STATUS2_LP_LITE_WAKEUP_CAUSE() uint32 { + return (volatile.LoadUint32(&o.SLP_WAKEUP_STATUS2.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_CK_POWERON: need_des +func (o *PMU_Type) SetHP_CK_POWERON_I2C_POR_WAIT_TARGET(value uint32) { + volatile.StoreUint32(&o.HP_CK_POWERON.Reg, volatile.LoadUint32(&o.HP_CK_POWERON.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetHP_CK_POWERON_I2C_POR_WAIT_TARGET() uint32 { + return volatile.LoadUint32(&o.HP_CK_POWERON.Reg) & 0xff +} + +// PMU.HP_CK_CNTL: need_des +func (o *PMU_Type) SetHP_CK_CNTL_MODIFY_ICG_CNTL_WAIT(value uint32) { + volatile.StoreUint32(&o.HP_CK_CNTL.Reg, volatile.LoadUint32(&o.HP_CK_CNTL.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetHP_CK_CNTL_MODIFY_ICG_CNTL_WAIT() uint32 { + return volatile.LoadUint32(&o.HP_CK_CNTL.Reg) & 0xff +} +func (o *PMU_Type) SetHP_CK_CNTL_SWITCH_ICG_CNTL_WAIT(value uint32) { + volatile.StoreUint32(&o.HP_CK_CNTL.Reg, volatile.LoadUint32(&o.HP_CK_CNTL.Reg)&^(0xff00)|value<<8) +} +func (o *PMU_Type) GetHP_CK_CNTL_SWITCH_ICG_CNTL_WAIT() uint32 { + return (volatile.LoadUint32(&o.HP_CK_CNTL.Reg) & 0xff00) >> 8 +} + +// PMU.POR_STATUS: need_des +func (o *PMU_Type) SetPOR_STATUS_POR_DONE(value uint32) { + volatile.StoreUint32(&o.POR_STATUS.Reg, volatile.LoadUint32(&o.POR_STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetPOR_STATUS_POR_DONE() uint32 { + return (volatile.LoadUint32(&o.POR_STATUS.Reg) & 0x80000000) >> 31 +} + +// PMU.RF_PWC: need_des +func (o *PMU_Type) SetRF_PWC_MSPI_PHY_XPD(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetRF_PWC_MSPI_PHY_XPD() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetRF_PWC_SDIO_PLL_XPD(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetRF_PWC_SDIO_PLL_XPD() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetRF_PWC_PERIF_I2C_RSTB(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetRF_PWC_PERIF_I2C_RSTB() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetRF_PWC_XPD_PERIF_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetRF_PWC_XPD_PERIF_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetRF_PWC_XPD_TXRF_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetRF_PWC_XPD_TXRF_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetRF_PWC_XPD_RFRX_PBUS(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetRF_PWC_XPD_RFRX_PBUS() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetRF_PWC_XPD_CKGEN_I2C(value uint32) { + volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetRF_PWC_XPD_CKGEN_I2C() uint32 { + return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x40000000) >> 30 +} + +// PMU.BACKUP_CFG: need_des +func (o *PMU_Type) SetBACKUP_CFG_BACKUP_SYS_CLK_NO_DIV(value uint32) { + volatile.StoreUint32(&o.BACKUP_CFG.Reg, volatile.LoadUint32(&o.BACKUP_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetBACKUP_CFG_BACKUP_SYS_CLK_NO_DIV() uint32 { + return (volatile.LoadUint32(&o.BACKUP_CFG.Reg) & 0x80000000) >> 31 +} + +// PMU.INT_RAW: need_des +func (o *PMU_Type) SetINT_RAW__0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetINT_RAW__0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetINT_RAW__0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetINT_RAW__0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetINT_RAW__0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetINT_RAW__0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetINT_RAW__0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetINT_RAW__0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetINT_RAW__0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetINT_RAW__0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetINT_RAW__0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetINT_RAW__0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetINT_RAW__0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetINT_RAW__0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetINT_RAW__0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetINT_RAW__0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetINT_RAW__0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetINT_RAW__0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetINT_RAW__0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetINT_RAW__0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetINT_RAW__0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetINT_RAW__0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetINT_RAW__0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetINT_RAW__0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetINT_RAW_LP_CPU_EXC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetINT_RAW_LP_CPU_EXC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetINT_RAW_SDIO_IDLE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetINT_RAW_SDIO_IDLE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetINT_RAW_SW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetINT_RAW_SW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetINT_RAW_SOC_SLEEP_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetINT_RAW_SOC_SLEEP_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetINT_RAW_SOC_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetINT_RAW_SOC_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_INT_ST: need_des +func (o *PMU_Type) SetHP_INT_ST__0P1A_CNT_TARGET0_REACH_0_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetHP_INT_ST__0P1A_CNT_TARGET0_REACH_0_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetHP_INT_ST__0P1A_CNT_TARGET1_REACH_0_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetHP_INT_ST__0P1A_CNT_TARGET1_REACH_0_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetHP_INT_ST__0P1A_CNT_TARGET0_REACH_1_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_INT_ST__0P1A_CNT_TARGET0_REACH_1_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_INT_ST__0P1A_CNT_TARGET1_REACH_1_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_INT_ST__0P1A_CNT_TARGET1_REACH_1_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_INT_ST__0P2A_CNT_TARGET0_REACH_0_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_INT_ST__0P2A_CNT_TARGET0_REACH_0_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_INT_ST__0P2A_CNT_TARGET1_REACH_0_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetHP_INT_ST__0P2A_CNT_TARGET1_REACH_0_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetHP_INT_ST__0P2A_CNT_TARGET0_REACH_1_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetHP_INT_ST__0P2A_CNT_TARGET0_REACH_1_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetHP_INT_ST__0P2A_CNT_TARGET1_REACH_1_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_INT_ST__0P2A_CNT_TARGET1_REACH_1_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_INT_ST__0P3A_CNT_TARGET0_REACH_0_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_INT_ST__0P3A_CNT_TARGET0_REACH_0_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_INT_ST__0P3A_CNT_TARGET1_REACH_0_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetHP_INT_ST__0P3A_CNT_TARGET1_REACH_0_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetHP_INT_ST__0P3A_CNT_TARGET0_REACH_1_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_INT_ST__0P3A_CNT_TARGET0_REACH_1_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_INT_ST__0P3A_CNT_TARGET1_REACH_1_HP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_INT_ST__0P3A_CNT_TARGET1_REACH_1_HP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_INT_ST_LP_CPU_EXC_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_INT_ST_LP_CPU_EXC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_INT_ST_SDIO_IDLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_INT_ST_SDIO_IDLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_INT_ST_SW_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_INT_ST_SW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_INT_ST_SOC_SLEEP_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_INT_ST_SOC_SLEEP_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_INT_ST_SOC_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_INT_ST_SOC_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_INT_ENA: need_des +func (o *PMU_Type) SetHP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetHP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetHP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetHP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetHP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetHP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetHP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetHP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetHP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetHP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetHP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_INT_ENA_LP_CPU_EXC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_INT_ENA_LP_CPU_EXC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_INT_ENA_SDIO_IDLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_INT_ENA_SDIO_IDLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_INT_ENA_SW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_INT_ENA_SW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_INT_ENA_SOC_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_INT_ENA_SOC_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_INT_CLR: need_des +func (o *PMU_Type) SetHP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetHP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetHP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetHP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetHP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetHP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetHP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetHP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetHP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetHP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetHP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetHP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetHP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetHP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetHP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetHP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetHP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetHP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetHP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetHP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetHP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetHP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetHP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetHP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetHP_INT_CLR_LP_CPU_EXC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetHP_INT_CLR_LP_CPU_EXC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetHP_INT_CLR_SDIO_IDLE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetHP_INT_CLR_SDIO_IDLE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetHP_INT_CLR_SW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetHP_INT_CLR_SW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetHP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_INT_CLR_SOC_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_INT_CLR_SOC_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_RAW: need_des +func (o *PMU_Type) SetLP_INT_RAW_LP_CPU_SLEEP_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetLP_INT_RAW_LP_CPU_SLEEP_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetLP_INT_RAW__0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetLP_INT_RAW__0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetLP_INT_RAW__0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetLP_INT_RAW__0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetLP_INT_RAW__0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetLP_INT_RAW__0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetLP_INT_RAW__0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetLP_INT_RAW__0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetLP_INT_RAW__0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetLP_INT_RAW__0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetLP_INT_RAW__0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetLP_INT_RAW__0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetLP_INT_RAW__0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_RAW__0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_RAW__0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_RAW__0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_RAW__0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_RAW__0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_RAW__0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_RAW__0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_RAW__0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_RAW__0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_RAW__0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_RAW__0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_RAW_LP_CPU_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_RAW_LP_CPU_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_RAW_HP_SW_TRIGGER_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_RAW_HP_SW_TRIGGER_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_ST: need_des +func (o *PMU_Type) SetLP_INT_ST_LP_CPU_SLEEP_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetLP_INT_ST_LP_CPU_SLEEP_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetLP_INT_ST__0P1A_CNT_TARGET0_REACH_0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetLP_INT_ST__0P1A_CNT_TARGET0_REACH_0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetLP_INT_ST__0P1A_CNT_TARGET1_REACH_0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetLP_INT_ST__0P1A_CNT_TARGET1_REACH_0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetLP_INT_ST__0P1A_CNT_TARGET0_REACH_1_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetLP_INT_ST__0P1A_CNT_TARGET0_REACH_1_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetLP_INT_ST__0P1A_CNT_TARGET1_REACH_1_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetLP_INT_ST__0P1A_CNT_TARGET1_REACH_1_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetLP_INT_ST__0P2A_CNT_TARGET0_REACH_0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetLP_INT_ST__0P2A_CNT_TARGET0_REACH_0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetLP_INT_ST__0P2A_CNT_TARGET1_REACH_0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetLP_INT_ST__0P2A_CNT_TARGET1_REACH_0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetLP_INT_ST__0P2A_CNT_TARGET0_REACH_1_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_ST__0P2A_CNT_TARGET0_REACH_1_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_ST__0P2A_CNT_TARGET1_REACH_1_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_ST__0P2A_CNT_TARGET1_REACH_1_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_ST__0P3A_CNT_TARGET0_REACH_0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_ST__0P3A_CNT_TARGET0_REACH_0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_ST__0P3A_CNT_TARGET1_REACH_0_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_ST__0P3A_CNT_TARGET1_REACH_0_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_ST__0P3A_CNT_TARGET0_REACH_1_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_ST__0P3A_CNT_TARGET0_REACH_1_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_ST__0P3A_CNT_TARGET1_REACH_1_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_ST__0P3A_CNT_TARGET1_REACH_1_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_ST_LP_CPU_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_ST_LP_CPU_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_ST_HP_SW_TRIGGER_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_ST_HP_SW_TRIGGER_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_ENA: need_des +func (o *PMU_Type) SetLP_INT_ENA_LP_CPU_SLEEP_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetLP_INT_ENA_LP_CPU_SLEEP_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetLP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetLP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetLP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetLP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetLP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetLP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetLP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetLP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetLP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetLP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetLP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetLP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetLP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_ENA_LP_CPU_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_ENA_LP_CPU_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_ENA_HP_SW_TRIGGER_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_ENA_HP_SW_TRIGGER_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_INT_CLR: need_des +func (o *PMU_Type) SetLP_INT_CLR_LP_CPU_SLEEP_REJECT_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetLP_INT_CLR_LP_CPU_SLEEP_REJECT_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetLP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetLP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetLP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetLP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetLP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *PMU_Type) GetLP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *PMU_Type) SetLP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *PMU_Type) GetLP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *PMU_Type) SetLP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetLP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetLP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetLP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetLP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *PMU_Type) GetLP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *PMU_Type) SetLP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *PMU_Type) GetLP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *PMU_Type) SetLP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *PMU_Type) GetLP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *PMU_Type) SetLP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetLP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetLP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetLP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetLP_INT_CLR_LP_CPU_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetLP_INT_CLR_LP_CPU_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *PMU_Type) GetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_INT_CLR_HP_SW_TRIGGER_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_INT_CLR_HP_SW_TRIGGER_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_CPU_PWR0: need_des +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_WAITI_RDY(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_WAITI_RDY() uint32 { + return volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x1 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_STALL_RDY(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_STALL_RDY() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_FORCE_STALL(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_FORCE_STALL() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x100000)|value<<20) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x100000) >> 20 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x1fe00000)|value<<21) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x1fe00000) >> 21 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x20000000) >> 29 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_CPU_PWR1: need_des +func (o *PMU_Type) SetLP_CPU_PWR1_LP_CPU_SLEEP_REQ(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR1.Reg, volatile.LoadUint32(&o.LP_CPU_PWR1.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetLP_CPU_PWR1_LP_CPU_SLEEP_REQ() uint32 { + return (volatile.LoadUint32(&o.LP_CPU_PWR1.Reg) & 0x80000000) >> 31 +} + +// PMU.LP_CPU_PWR2: need_des +func (o *PMU_Type) SetLP_CPU_PWR2_LP_CPU_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR2.Reg, volatile.LoadUint32(&o.LP_CPU_PWR2.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetLP_CPU_PWR2_LP_CPU_WAKEUP_EN() uint32 { + return volatile.LoadUint32(&o.LP_CPU_PWR2.Reg) & 0x7fffffff +} + +// PMU.LP_CPU_PWR3: need_des +func (o *PMU_Type) SetLP_CPU_PWR3_LP_CPU_WAKEUP_CAUSE(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR3.Reg, volatile.LoadUint32(&o.LP_CPU_PWR3.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetLP_CPU_PWR3_LP_CPU_WAKEUP_CAUSE() uint32 { + return volatile.LoadUint32(&o.LP_CPU_PWR3.Reg) & 0x7fffffff +} + +// PMU.LP_CPU_PWR4: need_des +func (o *PMU_Type) SetLP_CPU_PWR4_LP_CPU_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR4.Reg, volatile.LoadUint32(&o.LP_CPU_PWR4.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetLP_CPU_PWR4_LP_CPU_REJECT_EN() uint32 { + return volatile.LoadUint32(&o.LP_CPU_PWR4.Reg) & 0x7fffffff +} + +// PMU.LP_CPU_PWR5: need_des +func (o *PMU_Type) SetLP_CPU_PWR5_LP_CPU_REJECT_CAUSE(value uint32) { + volatile.StoreUint32(&o.LP_CPU_PWR5.Reg, volatile.LoadUint32(&o.LP_CPU_PWR5.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetLP_CPU_PWR5_LP_CPU_REJECT_CAUSE() uint32 { + return volatile.LoadUint32(&o.LP_CPU_PWR5.Reg) & 0x7fffffff +} + +// PMU.HP_LP_CPU_COMM: need_des +func (o *PMU_Type) SetHP_LP_CPU_COMM_LP_TRIGGER_HP(value uint32) { + volatile.StoreUint32(&o.HP_LP_CPU_COMM.Reg, volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetHP_LP_CPU_COMM_LP_TRIGGER_HP() uint32 { + return (volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetHP_LP_CPU_COMM_HP_TRIGGER_LP(value uint32) { + volatile.StoreUint32(&o.HP_LP_CPU_COMM.Reg, volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_LP_CPU_COMM_HP_TRIGGER_LP() uint32 { + return (volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg) & 0x80000000) >> 31 +} + +// PMU.HP_REGULATOR_CFG: need_des +func (o *PMU_Type) SetHP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL(value uint32) { + volatile.StoreUint32(&o.HP_REGULATOR_CFG.Reg, volatile.LoadUint32(&o.HP_REGULATOR_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetHP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL() uint32 { + return (volatile.LoadUint32(&o.HP_REGULATOR_CFG.Reg) & 0x80000000) >> 31 +} + +// PMU.MAIN_STATE: need_des +func (o *PMU_Type) SetMAIN_STATE_ENABLE_CALI_PMU_CNTL(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetMAIN_STATE_ENABLE_CALI_PMU_CNTL() uint32 { + return volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x1 +} +func (o *PMU_Type) SetMAIN_STATE_PMU_MAIN_LAST_ST_STATE(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x3f800)|value<<11) +} +func (o *PMU_Type) GetMAIN_STATE_PMU_MAIN_LAST_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x3f800) >> 11 +} +func (o *PMU_Type) SetMAIN_STATE_PMU_MAIN_TAR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x1fc0000)|value<<18) +} +func (o *PMU_Type) GetMAIN_STATE_PMU_MAIN_TAR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x1fc0000) >> 18 +} +func (o *PMU_Type) SetMAIN_STATE_PMU_MAIN_CUR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0xfe000000)|value<<25) +} +func (o *PMU_Type) GetMAIN_STATE_PMU_MAIN_CUR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0xfe000000) >> 25 +} + +// PMU.PWR_STATE: need_des +func (o *PMU_Type) SetPWR_STATE_PMU_BACKUP_ST_STATE(value uint32) { + volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0x3e000)|value<<13) +} +func (o *PMU_Type) GetPWR_STATE_PMU_BACKUP_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0x3e000) >> 13 +} +func (o *PMU_Type) SetPWR_STATE_PMU_LP_PWR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0x7c0000)|value<<18) +} +func (o *PMU_Type) GetPWR_STATE_PMU_LP_PWR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0x7c0000) >> 18 +} +func (o *PMU_Type) SetPWR_STATE_PMU_HP_PWR_ST_STATE(value uint32) { + volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0xff800000)|value<<23) +} +func (o *PMU_Type) GetPWR_STATE_PMU_HP_PWR_ST_STATE() uint32 { + return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0xff800000) >> 23 +} + +// PMU.CLK_STATE0: need_des +func (o *PMU_Type) SetCLK_STATE0_STABLE_XPD_PLL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x7)|value) +} +func (o *PMU_Type) GetCLK_STATE0_STABLE_XPD_PLL_STATE() uint32 { + return volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x7 +} +func (o *PMU_Type) SetCLK_STATE0_STABLE_XPD_XTAL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetCLK_STATE0_STABLE_XPD_XTAL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_XPD_PLL_I2C_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x70)|value<<4) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_XPD_PLL_I2C_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x70) >> 4 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_SYS_CLK_SLP_SEL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_SYS_CLK_SLP_SEL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_SYS_CLK_SEL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x1800)|value<<11) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_SYS_CLK_SEL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x1800) >> 11 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_SYS_CLK_NO_DIV_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_SYS_CLK_NO_DIV_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_SYS_CLK_EN_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_SYS_CLK_EN_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_MODEM_SWITCH_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_MODEM_SWITCH_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_MODEM_CODE_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x30000)|value<<16) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_MODEM_CODE_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x30000) >> 16 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_SLP_SEL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x40000)|value<<18) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_SLP_SEL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x40000) >> 18 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_GLOBAL_XTAL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x80000)|value<<19) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_GLOBAL_XTAL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x80000) >> 19 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_GLOBAL_PLL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0xf00000)|value<<20) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_GLOBAL_PLL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0xf00000) >> 20 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_I2C_ISO_EN_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x1000000)|value<<24) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_I2C_ISO_EN_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x1000000) >> 24 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_I2C_RETENTION_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x2000000)|value<<25) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_I2C_RETENTION_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x2000000) >> 25 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_XPD_PLL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x78000000)|value<<27) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_XPD_PLL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x78000000) >> 27 +} +func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_XPD_XTAL_STATE(value uint32) { + volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_XPD_XTAL_STATE() uint32 { + return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x80000000) >> 31 +} + +// PMU.CLK_STATE1: need_des +func (o *PMU_Type) SetCLK_STATE1(value uint32) { + volatile.StoreUint32(&o.CLK_STATE1.Reg, value) +} +func (o *PMU_Type) GetCLK_STATE1() uint32 { + return volatile.LoadUint32(&o.CLK_STATE1.Reg) +} + +// PMU.CLK_STATE2: need_des +func (o *PMU_Type) SetCLK_STATE2(value uint32) { + volatile.StoreUint32(&o.CLK_STATE2.Reg, value) +} +func (o *PMU_Type) GetCLK_STATE2() uint32 { + return volatile.LoadUint32(&o.CLK_STATE2.Reg) +} + +// PMU.EXT_LDO_P0_0P1A: need_des +func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_FORCE_TIEH_SEL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x80)|value<<7) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_FORCE_TIEH_SEL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x80) >> 7 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_XPD_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x100)|value<<8) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_XPD_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x100) >> 8 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TIEH_SEL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0xe00)|value<<9) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TIEH_SEL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0xe00) >> 9 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TIEH_POS_EN_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TIEH_POS_EN_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TIEH_NEG_EN_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TIEH_NEG_EN_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TIEH_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TIEH_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TARGET1_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x7f8000)|value<<15) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TARGET1_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x7f8000) >> 15 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TARGET0_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x7f800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TARGET0_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x7f800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x80000000) >> 31 +} + +// PMU.EXT_LDO_P0_0P1A_ANA: need_des +func (o *PMU_Type) SetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_MUL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_MUL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_VDET_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_VDET_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_DREF_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_DREF_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg) & 0xf0000000) >> 28 +} + +// PMU.EXT_LDO_P0_0P2A: need_des +func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_FORCE_TIEH_SEL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x80)|value<<7) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_FORCE_TIEH_SEL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x80) >> 7 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_XPD_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x100)|value<<8) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_XPD_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x100) >> 8 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TIEH_SEL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0xe00)|value<<9) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TIEH_SEL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0xe00) >> 9 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TIEH_POS_EN_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TIEH_POS_EN_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TIEH_NEG_EN_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TIEH_NEG_EN_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TIEH_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TIEH_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TARGET1_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x7f8000)|value<<15) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TARGET1_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x7f8000) >> 15 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TARGET0_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x7f800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TARGET0_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x7f800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x80000000) >> 31 +} + +// PMU.EXT_LDO_P0_0P2A_ANA: need_des +func (o *PMU_Type) SetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_MUL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_MUL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_VDET_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_VDET_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_DREF_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_DREF_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg) & 0xf0000000) >> 28 +} + +// PMU.EXT_LDO_P0_0P3A: need_des +func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_FORCE_TIEH_SEL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x80)|value<<7) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_FORCE_TIEH_SEL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x80) >> 7 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_XPD_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x100)|value<<8) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_XPD_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x100) >> 8 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TIEH_SEL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0xe00)|value<<9) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TIEH_SEL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0xe00) >> 9 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TIEH_POS_EN_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TIEH_POS_EN_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TIEH_NEG_EN_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TIEH_NEG_EN_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TIEH_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TIEH_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TARGET1_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x7f8000)|value<<15) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TARGET1_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x7f8000) >> 15 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TARGET0_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x7f800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TARGET0_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x7f800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x80000000) >> 31 +} + +// PMU.EXT_LDO_P0_0P3A_ANA: need_des +func (o *PMU_Type) SetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_MUL_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_MUL_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_VDET_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_VDET_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_DREF_0(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_DREF_0() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg) & 0xf0000000) >> 28 +} + +// PMU.EXT_LDO_P1_0P1A: need_des +func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_FORCE_TIEH_SEL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x80)|value<<7) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_FORCE_TIEH_SEL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x80) >> 7 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_XPD_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x100)|value<<8) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_XPD_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x100) >> 8 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TIEH_SEL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0xe00)|value<<9) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TIEH_SEL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0xe00) >> 9 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TIEH_POS_EN_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TIEH_POS_EN_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TIEH_NEG_EN_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TIEH_NEG_EN_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TIEH_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TIEH_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TARGET1_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x7f8000)|value<<15) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TARGET1_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x7f8000) >> 15 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TARGET0_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x7f800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TARGET0_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x7f800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x80000000) >> 31 +} + +// PMU.EXT_LDO_P1_0P1A_ANA: need_des +func (o *PMU_Type) SetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_MUL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_MUL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_VDET_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_VDET_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_DREF_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_DREF_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg) & 0xf0000000) >> 28 +} + +// PMU.EXT_LDO_P1_0P2A: need_des +func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_FORCE_TIEH_SEL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x80)|value<<7) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_FORCE_TIEH_SEL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x80) >> 7 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_XPD_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x100)|value<<8) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_XPD_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x100) >> 8 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TIEH_SEL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0xe00)|value<<9) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TIEH_SEL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0xe00) >> 9 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TIEH_POS_EN_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TIEH_POS_EN_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TIEH_NEG_EN_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TIEH_NEG_EN_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TIEH_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TIEH_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TARGET1_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x7f8000)|value<<15) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TARGET1_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x7f8000) >> 15 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TARGET0_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x7f800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TARGET0_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x7f800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x80000000) >> 31 +} + +// PMU.EXT_LDO_P1_0P2A_ANA: need_des +func (o *PMU_Type) SetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_MUL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_MUL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_VDET_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_VDET_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_DREF_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_DREF_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg) & 0xf0000000) >> 28 +} + +// PMU.EXT_LDO_P1_0P3A: need_des +func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_FORCE_TIEH_SEL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x80)|value<<7) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_FORCE_TIEH_SEL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x80) >> 7 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_XPD_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x100)|value<<8) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_XPD_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x100) >> 8 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TIEH_SEL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0xe00)|value<<9) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TIEH_SEL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0xe00) >> 9 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TIEH_POS_EN_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TIEH_POS_EN_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TIEH_NEG_EN_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TIEH_NEG_EN_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TIEH_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TIEH_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TARGET1_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x7f8000)|value<<15) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TARGET1_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x7f8000) >> 15 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TARGET0_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x7f800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TARGET0_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x7f800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x80000000) >> 31 +} + +// PMU.EXT_LDO_P1_0P3A_ANA: need_des +func (o *PMU_Type) SetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_MUL_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg)&^(0x3800000)|value<<23) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_MUL_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg) & 0x3800000) >> 23 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_VDET_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg)&^(0x4000000)|value<<26) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_VDET_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg) & 0x4000000) >> 26 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg)&^(0x8000000)|value<<27) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg) & 0x8000000) >> 27 +} +func (o *PMU_Type) SetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_DREF_1(value uint32) { + volatile.StoreUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg)&^(0xf0000000)|value<<28) +} +func (o *PMU_Type) GetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_DREF_1() uint32 { + return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg) & 0xf0000000) >> 28 +} + +// PMU.EXT_WAKEUP_LV: need_des +func (o *PMU_Type) SetEXT_WAKEUP_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_LV.Reg, value) +} +func (o *PMU_Type) GetEXT_WAKEUP_LV() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP_LV.Reg) +} + +// PMU.EXT_WAKEUP_SEL: need_des +func (o *PMU_Type) SetEXT_WAKEUP_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_SEL.Reg, value) +} +func (o *PMU_Type) GetEXT_WAKEUP_SEL() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP_SEL.Reg) +} + +// PMU.EXT_WAKEUP_ST: need_des +func (o *PMU_Type) SetEXT_WAKEUP_ST(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_ST.Reg, value) +} +func (o *PMU_Type) GetEXT_WAKEUP_ST() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP_ST.Reg) +} + +// PMU.EXT_WAKEUP_CNTL: need_des +func (o *PMU_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x80000000) >> 31 +} + +// PMU.SDIO_WAKEUP_CNTL: need_des +func (o *PMU_Type) SetSDIO_WAKEUP_CNTL_SDIO_ACT_DNUM(value uint32) { + volatile.StoreUint32(&o.SDIO_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.SDIO_WAKEUP_CNTL.Reg)&^(0x3ff)|value) +} +func (o *PMU_Type) GetSDIO_WAKEUP_CNTL_SDIO_ACT_DNUM() uint32 { + return volatile.LoadUint32(&o.SDIO_WAKEUP_CNTL.Reg) & 0x3ff +} + +// PMU.XTAL_SLP: need_des +func (o *PMU_Type) SetXTAL_SLP_CNT_TARGET(value uint32) { + volatile.StoreUint32(&o.XTAL_SLP.Reg, volatile.LoadUint32(&o.XTAL_SLP.Reg)&^(0xffff0000)|value<<16) +} +func (o *PMU_Type) GetXTAL_SLP_CNT_TARGET() uint32 { + return (volatile.LoadUint32(&o.XTAL_SLP.Reg) & 0xffff0000) >> 16 +} + +// PMU.CPU_SW_STALL: need_des +func (o *PMU_Type) SetCPU_SW_STALL_HPCORE1_SW_STALL_CODE(value uint32) { + volatile.StoreUint32(&o.CPU_SW_STALL.Reg, volatile.LoadUint32(&o.CPU_SW_STALL.Reg)&^(0xff0000)|value<<16) +} +func (o *PMU_Type) GetCPU_SW_STALL_HPCORE1_SW_STALL_CODE() uint32 { + return (volatile.LoadUint32(&o.CPU_SW_STALL.Reg) & 0xff0000) >> 16 +} +func (o *PMU_Type) SetCPU_SW_STALL_HPCORE0_SW_STALL_CODE(value uint32) { + volatile.StoreUint32(&o.CPU_SW_STALL.Reg, volatile.LoadUint32(&o.CPU_SW_STALL.Reg)&^(0xff000000)|value<<24) +} +func (o *PMU_Type) GetCPU_SW_STALL_HPCORE0_SW_STALL_CODE() uint32 { + return (volatile.LoadUint32(&o.CPU_SW_STALL.Reg) & 0xff000000) >> 24 +} + +// PMU.DCM_CTRL: need_des +func (o *PMU_Type) SetDCM_CTRL_DCDC_ON_REQ(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_ON_REQ() uint32 { + return volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x1 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_OFF_REQ(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_OFF_REQ() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x2) >> 1 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_LIGHTSLP_REQ(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_LIGHTSLP_REQ() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x4) >> 2 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_DEEPSLP_REQ(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_DEEPSLP_REQ() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x8) >> 3 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_DONE_FORCE(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_DONE_FORCE() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x80) >> 7 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_ON_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_ON_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x100) >> 8 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_ON_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_ON_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x200) >> 9 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_FB_RES_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_FB_RES_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x400) >> 10 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_FB_RES_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_FB_RES_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x800) >> 11 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_LS_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_LS_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_LS_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_LS_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_DS_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_DS_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_DS_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_DS_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *PMU_Type) SetDCM_CTRL_DCM_CUR_ST(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0xff0000)|value<<16) +} +func (o *PMU_Type) GetDCM_CTRL_DCM_CUR_ST() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0xff0000) >> 16 +} +func (o *PMU_Type) SetDCM_CTRL_DCDC_EN_AMUX_TEST(value uint32) { + volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *PMU_Type) GetDCM_CTRL_DCDC_EN_AMUX_TEST() uint32 { + return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x20000000) >> 29 +} + +// PMU.DCM_WAIT_DELAY: need_des +func (o *PMU_Type) SetDCM_WAIT_DELAY_DCDC_PRE_DELAY(value uint32) { + volatile.StoreUint32(&o.DCM_WAIT_DELAY.Reg, volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg)&^(0xff)|value) +} +func (o *PMU_Type) GetDCM_WAIT_DELAY_DCDC_PRE_DELAY() uint32 { + return volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg) & 0xff +} +func (o *PMU_Type) SetDCM_WAIT_DELAY_DCDC_RES_OFF_DELAY(value uint32) { + volatile.StoreUint32(&o.DCM_WAIT_DELAY.Reg, volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg)&^(0xff00)|value<<8) +} +func (o *PMU_Type) GetDCM_WAIT_DELAY_DCDC_RES_OFF_DELAY() uint32 { + return (volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg) & 0xff00) >> 8 +} +func (o *PMU_Type) SetDCM_WAIT_DELAY_DCDC_STABLE_DELAY(value uint32) { + volatile.StoreUint32(&o.DCM_WAIT_DELAY.Reg, volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg)&^(0x3ff0000)|value<<16) +} +func (o *PMU_Type) GetDCM_WAIT_DELAY_DCDC_STABLE_DELAY() uint32 { + return (volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg) & 0x3ff0000) >> 16 +} + +// PMU.VDDBAT_CFG: need_des +func (o *PMU_Type) SetVDDBAT_CFG_ANA_VDDBAT_MODE(value uint32) { + volatile.StoreUint32(&o.VDDBAT_CFG.Reg, volatile.LoadUint32(&o.VDDBAT_CFG.Reg)&^(0x3)|value) +} +func (o *PMU_Type) GetVDDBAT_CFG_ANA_VDDBAT_MODE() uint32 { + return volatile.LoadUint32(&o.VDDBAT_CFG.Reg) & 0x3 +} +func (o *PMU_Type) SetVDDBAT_CFG_VDDBAT_SW_UPDATE(value uint32) { + volatile.StoreUint32(&o.VDDBAT_CFG.Reg, volatile.LoadUint32(&o.VDDBAT_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetVDDBAT_CFG_VDDBAT_SW_UPDATE() uint32 { + return (volatile.LoadUint32(&o.VDDBAT_CFG.Reg) & 0x80000000) >> 31 +} + +// PMU.TOUCH_PWR_CNTL: need_des +func (o *PMU_Type) SetTOUCH_PWR_CNTL_TOUCH_WAIT_CYCLES(value uint32) { + volatile.StoreUint32(&o.TOUCH_PWR_CNTL.Reg, volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg)&^(0x3fe0)|value<<5) +} +func (o *PMU_Type) GetTOUCH_PWR_CNTL_TOUCH_WAIT_CYCLES() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg) & 0x3fe0) >> 5 +} +func (o *PMU_Type) SetTOUCH_PWR_CNTL_TOUCH_SLEEP_CYCLES(value uint32) { + volatile.StoreUint32(&o.TOUCH_PWR_CNTL.Reg, volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg)&^(0x3fffc000)|value<<14) +} +func (o *PMU_Type) GetTOUCH_PWR_CNTL_TOUCH_SLEEP_CYCLES() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg) & 0x3fffc000) >> 14 +} +func (o *PMU_Type) SetTOUCH_PWR_CNTL_TOUCH_FORCE_DONE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PWR_CNTL.Reg, volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg)&^(0x40000000)|value<<30) +} +func (o *PMU_Type) GetTOUCH_PWR_CNTL_TOUCH_FORCE_DONE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg) & 0x40000000) >> 30 +} +func (o *PMU_Type) SetTOUCH_PWR_CNTL_TOUCH_SLEEP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_PWR_CNTL.Reg, volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetTOUCH_PWR_CNTL_TOUCH_SLEEP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg) & 0x80000000) >> 31 +} + +// PMU.RDN_ECO: need_des +func (o *PMU_Type) SetRDN_ECO_PMU_RDN_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.RDN_ECO.Reg, volatile.LoadUint32(&o.RDN_ECO.Reg)&^(0x1)|value) +} +func (o *PMU_Type) GetRDN_ECO_PMU_RDN_ECO_RESULT() uint32 { + return volatile.LoadUint32(&o.RDN_ECO.Reg) & 0x1 +} +func (o *PMU_Type) SetRDN_ECO_PMU_RDN_ECO_EN(value uint32) { + volatile.StoreUint32(&o.RDN_ECO.Reg, volatile.LoadUint32(&o.RDN_ECO.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetRDN_ECO_PMU_RDN_ECO_EN() uint32 { + return (volatile.LoadUint32(&o.RDN_ECO.Reg) & 0x80000000) >> 31 +} + +// PMU.DATE: need_des +func (o *PMU_Type) SetDATE_PMU_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *PMU_Type) GetDATE_PMU_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *PMU_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *PMU_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// PPA Peripheral +type PPA_Type struct { + BLEND0_CLUT_DATA volatile.Register32 // 0x0 + BLEND1_CLUT_DATA volatile.Register32 // 0x4 + _ [4]byte + CLUT_CONF volatile.Register32 // 0xC + INT_RAW volatile.Register32 // 0x10 + INT_ST volatile.Register32 // 0x14 + INT_ENA volatile.Register32 // 0x18 + INT_CLR volatile.Register32 // 0x1C + SR_COLOR_MODE volatile.Register32 // 0x20 + BLEND_COLOR_MODE volatile.Register32 // 0x24 + SR_BYTE_ORDER volatile.Register32 // 0x28 + BLEND_BYTE_ORDER volatile.Register32 // 0x2C + _ [4]byte + BLEND_TRANS_MODE volatile.Register32 // 0x34 + SR_FIX_ALPHA volatile.Register32 // 0x38 + BLEND_TX_SIZE volatile.Register32 // 0x3C + BLEND_FIX_ALPHA volatile.Register32 // 0x40 + _ [4]byte + BLEND_RGB volatile.Register32 // 0x48 + BLEND_FIX_PIXEL volatile.Register32 // 0x4C + CK_FG_LOW volatile.Register32 // 0x50 + CK_FG_HIGH volatile.Register32 // 0x54 + CK_BG_LOW volatile.Register32 // 0x58 + CK_BG_HIGH volatile.Register32 // 0x5C + CK_DEFAULT volatile.Register32 // 0x60 + SR_SCAL_ROTATE volatile.Register32 // 0x64 + SR_MEM_PD volatile.Register32 // 0x68 + REG_CONF volatile.Register32 // 0x6C + CLUT_CNT volatile.Register32 // 0x70 + BLEND_ST volatile.Register32 // 0x74 + SR_PARAM_ERR_ST volatile.Register32 // 0x78 + SR_STATUS volatile.Register32 // 0x7C + ECO_LOW volatile.Register32 // 0x80 + ECO_HIGH volatile.Register32 // 0x84 + ECO_CELL_CTRL volatile.Register32 // 0x88 + SRAM_CTRL volatile.Register32 // 0x8C + _ [112]byte + DATE volatile.Register32 // 0x100 +} + +// PPA.BLEND0_CLUT_DATA: CLUT sram data read/write register in background plane of blender +func (o *PPA_Type) SetBLEND0_CLUT_DATA(value uint32) { + volatile.StoreUint32(&o.BLEND0_CLUT_DATA.Reg, value) +} +func (o *PPA_Type) GetBLEND0_CLUT_DATA() uint32 { + return volatile.LoadUint32(&o.BLEND0_CLUT_DATA.Reg) +} + +// PPA.BLEND1_CLUT_DATA: CLUT sram data read/write register in foreground plane of blender +func (o *PPA_Type) SetBLEND1_CLUT_DATA(value uint32) { + volatile.StoreUint32(&o.BLEND1_CLUT_DATA.Reg, value) +} +func (o *PPA_Type) GetBLEND1_CLUT_DATA() uint32 { + return volatile.LoadUint32(&o.BLEND1_CLUT_DATA.Reg) +} + +// PPA.CLUT_CONF: CLUT configure register +func (o *PPA_Type) SetCLUT_CONF_APB_FIFO_MASK(value uint32) { + volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetCLUT_CONF_APB_FIFO_MASK() uint32 { + return volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x1 +} +func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetCLUT_CONF_BLEND1_CLUT_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetCLUT_CONF_BLEND1_CLUT_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x4) >> 2 +} +func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_RDADDR_RST(value uint32) { + volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x8)|value<<3) +} +func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_RDADDR_RST() uint32 { + return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x8) >> 3 +} +func (o *PPA_Type) SetCLUT_CONF_BLEND1_CLUT_MEM_RDADDR_RST(value uint32) { + volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x10)|value<<4) +} +func (o *PPA_Type) GetCLUT_CONF_BLEND1_CLUT_MEM_RDADDR_RST() uint32 { + return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x10) >> 4 +} +func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x20)|value<<5) +} +func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x20) >> 5 +} +func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x40) >> 6 +} +func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x80)|value<<7) +} +func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_CLK_ENA() uint32 { + return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x80) >> 7 +} + +// PPA.INT_RAW: Raw status interrupt +func (o *PPA_Type) SetINT_RAW_SR_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetINT_RAW_SR_EOF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PPA_Type) SetINT_RAW_BLEND_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetINT_RAW_BLEND_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetINT_RAW_SR_PARAM_CFG_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetINT_RAW_SR_PARAM_CFG_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// PPA.INT_ST: Masked interrupt +func (o *PPA_Type) SetINT_ST_SR_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetINT_ST_SR_EOF_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PPA_Type) SetINT_ST_BLEND_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetINT_ST_BLEND_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetINT_ST_SR_PARAM_CFG_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetINT_ST_SR_PARAM_CFG_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// PPA.INT_ENA: Interrupt enable bits +func (o *PPA_Type) SetINT_ENA_SR_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetINT_ENA_SR_EOF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PPA_Type) SetINT_ENA_BLEND_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetINT_ENA_BLEND_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetINT_ENA_SR_PARAM_CFG_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetINT_ENA_SR_PARAM_CFG_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// PPA.INT_CLR: Interrupt clear bits +func (o *PPA_Type) SetINT_CLR_SR_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetINT_CLR_SR_EOF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PPA_Type) SetINT_CLR_BLEND_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetINT_CLR_BLEND_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetINT_CLR_SR_PARAM_CFG_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetINT_CLR_SR_PARAM_CFG_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// PPA.SR_COLOR_MODE: Scaling and rotating engine color mode register +func (o *PPA_Type) SetSR_COLOR_MODE_SR_RX_CM(value uint32) { + volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0xf)|value) +} +func (o *PPA_Type) GetSR_COLOR_MODE_SR_RX_CM() uint32 { + return volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0xf +} +func (o *PPA_Type) SetSR_COLOR_MODE_SR_TX_CM(value uint32) { + volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0xf0)|value<<4) +} +func (o *PPA_Type) GetSR_COLOR_MODE_SR_TX_CM() uint32 { + return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0xf0) >> 4 +} +func (o *PPA_Type) SetSR_COLOR_MODE_YUV_RX_RANGE(value uint32) { + volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0x100)|value<<8) +} +func (o *PPA_Type) GetSR_COLOR_MODE_YUV_RX_RANGE() uint32 { + return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0x100) >> 8 +} +func (o *PPA_Type) SetSR_COLOR_MODE_YUV_TX_RANGE(value uint32) { + volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0x200)|value<<9) +} +func (o *PPA_Type) GetSR_COLOR_MODE_YUV_TX_RANGE() uint32 { + return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0x200) >> 9 +} +func (o *PPA_Type) SetSR_COLOR_MODE_YUV2RGB_PROTOCAL(value uint32) { + volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0x400)|value<<10) +} +func (o *PPA_Type) GetSR_COLOR_MODE_YUV2RGB_PROTOCAL() uint32 { + return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0x400) >> 10 +} +func (o *PPA_Type) SetSR_COLOR_MODE_RGB2YUV_PROTOCAL(value uint32) { + volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0x800)|value<<11) +} +func (o *PPA_Type) GetSR_COLOR_MODE_RGB2YUV_PROTOCAL() uint32 { + return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0x800) >> 11 +} + +// PPA.BLEND_COLOR_MODE: blending engine color mode register +func (o *PPA_Type) SetBLEND_COLOR_MODE_BLEND0_RX_CM(value uint32) { + volatile.StoreUint32(&o.BLEND_COLOR_MODE.Reg, volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg)&^(0xf)|value) +} +func (o *PPA_Type) GetBLEND_COLOR_MODE_BLEND0_RX_CM() uint32 { + return volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg) & 0xf +} +func (o *PPA_Type) SetBLEND_COLOR_MODE_BLEND1_RX_CM(value uint32) { + volatile.StoreUint32(&o.BLEND_COLOR_MODE.Reg, volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg)&^(0xf0)|value<<4) +} +func (o *PPA_Type) GetBLEND_COLOR_MODE_BLEND1_RX_CM() uint32 { + return (volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg) & 0xf0) >> 4 +} +func (o *PPA_Type) SetBLEND_COLOR_MODE_BLEND_TX_CM(value uint32) { + volatile.StoreUint32(&o.BLEND_COLOR_MODE.Reg, volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg)&^(0xf00)|value<<8) +} +func (o *PPA_Type) GetBLEND_COLOR_MODE_BLEND_TX_CM() uint32 { + return (volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg) & 0xf00) >> 8 +} + +// PPA.SR_BYTE_ORDER: Scaling and rotating engine byte order register +func (o *PPA_Type) SetSR_BYTE_ORDER_SR_RX_BYTE_SWAP_EN(value uint32) { + volatile.StoreUint32(&o.SR_BYTE_ORDER.Reg, volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetSR_BYTE_ORDER_SR_RX_BYTE_SWAP_EN() uint32 { + return volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg) & 0x1 +} +func (o *PPA_Type) SetSR_BYTE_ORDER_SR_RX_RGB_SWAP_EN(value uint32) { + volatile.StoreUint32(&o.SR_BYTE_ORDER.Reg, volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetSR_BYTE_ORDER_SR_RX_RGB_SWAP_EN() uint32 { + return (volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetSR_BYTE_ORDER_SR_MACRO_BK_RO_BYPASS(value uint32) { + volatile.StoreUint32(&o.SR_BYTE_ORDER.Reg, volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetSR_BYTE_ORDER_SR_MACRO_BK_RO_BYPASS() uint32 { + return (volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg) & 0x4) >> 2 +} + +// PPA.BLEND_BYTE_ORDER: Blending engine byte order register +func (o *PPA_Type) SetBLEND_BYTE_ORDER_BLEND0_RX_BYTE_SWAP_EN(value uint32) { + volatile.StoreUint32(&o.BLEND_BYTE_ORDER.Reg, volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetBLEND_BYTE_ORDER_BLEND0_RX_BYTE_SWAP_EN() uint32 { + return volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg) & 0x1 +} +func (o *PPA_Type) SetBLEND_BYTE_ORDER_BLEND1_RX_BYTE_SWAP_EN(value uint32) { + volatile.StoreUint32(&o.BLEND_BYTE_ORDER.Reg, volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetBLEND_BYTE_ORDER_BLEND1_RX_BYTE_SWAP_EN() uint32 { + return (volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetBLEND_BYTE_ORDER_BLEND0_RX_RGB_SWAP_EN(value uint32) { + volatile.StoreUint32(&o.BLEND_BYTE_ORDER.Reg, volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetBLEND_BYTE_ORDER_BLEND0_RX_RGB_SWAP_EN() uint32 { + return (volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg) & 0x4) >> 2 +} +func (o *PPA_Type) SetBLEND_BYTE_ORDER_BLEND1_RX_RGB_SWAP_EN(value uint32) { + volatile.StoreUint32(&o.BLEND_BYTE_ORDER.Reg, volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg)&^(0x8)|value<<3) +} +func (o *PPA_Type) GetBLEND_BYTE_ORDER_BLEND1_RX_RGB_SWAP_EN() uint32 { + return (volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg) & 0x8) >> 3 +} + +// PPA.BLEND_TRANS_MODE: Blending engine mode configure register +func (o *PPA_Type) SetBLEND_TRANS_MODE_BLEND_EN(value uint32) { + volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetBLEND_TRANS_MODE_BLEND_EN() uint32 { + return volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x1 +} +func (o *PPA_Type) SetBLEND_TRANS_MODE_BLEND_BYPASS(value uint32) { + volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetBLEND_TRANS_MODE_BLEND_BYPASS() uint32 { + return (volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetBLEND_TRANS_MODE_BLEND_FIX_PIXEL_FILL_EN(value uint32) { + volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetBLEND_TRANS_MODE_BLEND_FIX_PIXEL_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x4) >> 2 +} +func (o *PPA_Type) SetBLEND_TRANS_MODE_UPDATE(value uint32) { + volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x8)|value<<3) +} +func (o *PPA_Type) GetBLEND_TRANS_MODE_UPDATE() uint32 { + return (volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x8) >> 3 +} +func (o *PPA_Type) SetBLEND_TRANS_MODE_BLEND_RST(value uint32) { + volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x10)|value<<4) +} +func (o *PPA_Type) GetBLEND_TRANS_MODE_BLEND_RST() uint32 { + return (volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x10) >> 4 +} + +// PPA.SR_FIX_ALPHA: Scaling and rotating engine alpha override register +func (o *PPA_Type) SetSR_FIX_ALPHA_SR_RX_FIX_ALPHA(value uint32) { + volatile.StoreUint32(&o.SR_FIX_ALPHA.Reg, volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg)&^(0xff)|value) +} +func (o *PPA_Type) GetSR_FIX_ALPHA_SR_RX_FIX_ALPHA() uint32 { + return volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg) & 0xff +} +func (o *PPA_Type) SetSR_FIX_ALPHA_SR_RX_ALPHA_MOD(value uint32) { + volatile.StoreUint32(&o.SR_FIX_ALPHA.Reg, volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg)&^(0x300)|value<<8) +} +func (o *PPA_Type) GetSR_FIX_ALPHA_SR_RX_ALPHA_MOD() uint32 { + return (volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg) & 0x300) >> 8 +} +func (o *PPA_Type) SetSR_FIX_ALPHA_SR_RX_ALPHA_INV(value uint32) { + volatile.StoreUint32(&o.SR_FIX_ALPHA.Reg, volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg)&^(0x400)|value<<10) +} +func (o *PPA_Type) GetSR_FIX_ALPHA_SR_RX_ALPHA_INV() uint32 { + return (volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg) & 0x400) >> 10 +} + +// PPA.BLEND_TX_SIZE: Fix pixel filling mode image size register +func (o *PPA_Type) SetBLEND_TX_SIZE_BLEND_HB(value uint32) { + volatile.StoreUint32(&o.BLEND_TX_SIZE.Reg, volatile.LoadUint32(&o.BLEND_TX_SIZE.Reg)&^(0x3fff)|value) +} +func (o *PPA_Type) GetBLEND_TX_SIZE_BLEND_HB() uint32 { + return volatile.LoadUint32(&o.BLEND_TX_SIZE.Reg) & 0x3fff +} +func (o *PPA_Type) SetBLEND_TX_SIZE_BLEND_VB(value uint32) { + volatile.StoreUint32(&o.BLEND_TX_SIZE.Reg, volatile.LoadUint32(&o.BLEND_TX_SIZE.Reg)&^(0xfffc000)|value<<14) +} +func (o *PPA_Type) GetBLEND_TX_SIZE_BLEND_VB() uint32 { + return (volatile.LoadUint32(&o.BLEND_TX_SIZE.Reg) & 0xfffc000) >> 14 +} + +// PPA.BLEND_FIX_ALPHA: Blending engine alpha override register +func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND0_RX_FIX_ALPHA(value uint32) { + volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0xff)|value) +} +func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND0_RX_FIX_ALPHA() uint32 { + return volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0xff +} +func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND1_RX_FIX_ALPHA(value uint32) { + volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0xff00)|value<<8) +} +func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND1_RX_FIX_ALPHA() uint32 { + return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0xff00) >> 8 +} +func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND0_RX_ALPHA_MOD(value uint32) { + volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0x30000)|value<<16) +} +func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND0_RX_ALPHA_MOD() uint32 { + return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0x30000) >> 16 +} +func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND1_RX_ALPHA_MOD(value uint32) { + volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0xc0000)|value<<18) +} +func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND1_RX_ALPHA_MOD() uint32 { + return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0xc0000) >> 18 +} +func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND0_RX_ALPHA_INV(value uint32) { + volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0x100000)|value<<20) +} +func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND0_RX_ALPHA_INV() uint32 { + return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0x100000) >> 20 +} +func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND1_RX_ALPHA_INV(value uint32) { + volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0x200000)|value<<21) +} +func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND1_RX_ALPHA_INV() uint32 { + return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0x200000) >> 21 +} + +// PPA.BLEND_RGB: RGB color register +func (o *PPA_Type) SetBLEND_RGB_BLEND1_RX_B(value uint32) { + volatile.StoreUint32(&o.BLEND_RGB.Reg, volatile.LoadUint32(&o.BLEND_RGB.Reg)&^(0xff)|value) +} +func (o *PPA_Type) GetBLEND_RGB_BLEND1_RX_B() uint32 { + return volatile.LoadUint32(&o.BLEND_RGB.Reg) & 0xff +} +func (o *PPA_Type) SetBLEND_RGB_BLEND1_RX_G(value uint32) { + volatile.StoreUint32(&o.BLEND_RGB.Reg, volatile.LoadUint32(&o.BLEND_RGB.Reg)&^(0xff00)|value<<8) +} +func (o *PPA_Type) GetBLEND_RGB_BLEND1_RX_G() uint32 { + return (volatile.LoadUint32(&o.BLEND_RGB.Reg) & 0xff00) >> 8 +} +func (o *PPA_Type) SetBLEND_RGB_BLEND1_RX_R(value uint32) { + volatile.StoreUint32(&o.BLEND_RGB.Reg, volatile.LoadUint32(&o.BLEND_RGB.Reg)&^(0xff0000)|value<<16) +} +func (o *PPA_Type) GetBLEND_RGB_BLEND1_RX_R() uint32 { + return (volatile.LoadUint32(&o.BLEND_RGB.Reg) & 0xff0000) >> 16 +} + +// PPA.BLEND_FIX_PIXEL: Blending engine fix pixel register +func (o *PPA_Type) SetBLEND_FIX_PIXEL(value uint32) { + volatile.StoreUint32(&o.BLEND_FIX_PIXEL.Reg, value) +} +func (o *PPA_Type) GetBLEND_FIX_PIXEL() uint32 { + return volatile.LoadUint32(&o.BLEND_FIX_PIXEL.Reg) +} + +// PPA.CK_FG_LOW: foreground color key lower threshold +func (o *PPA_Type) SetCK_FG_LOW_COLORKEY_FG_B_LOW(value uint32) { + volatile.StoreUint32(&o.CK_FG_LOW.Reg, volatile.LoadUint32(&o.CK_FG_LOW.Reg)&^(0xff)|value) +} +func (o *PPA_Type) GetCK_FG_LOW_COLORKEY_FG_B_LOW() uint32 { + return volatile.LoadUint32(&o.CK_FG_LOW.Reg) & 0xff +} +func (o *PPA_Type) SetCK_FG_LOW_COLORKEY_FG_G_LOW(value uint32) { + volatile.StoreUint32(&o.CK_FG_LOW.Reg, volatile.LoadUint32(&o.CK_FG_LOW.Reg)&^(0xff00)|value<<8) +} +func (o *PPA_Type) GetCK_FG_LOW_COLORKEY_FG_G_LOW() uint32 { + return (volatile.LoadUint32(&o.CK_FG_LOW.Reg) & 0xff00) >> 8 +} +func (o *PPA_Type) SetCK_FG_LOW_COLORKEY_FG_R_LOW(value uint32) { + volatile.StoreUint32(&o.CK_FG_LOW.Reg, volatile.LoadUint32(&o.CK_FG_LOW.Reg)&^(0xff0000)|value<<16) +} +func (o *PPA_Type) GetCK_FG_LOW_COLORKEY_FG_R_LOW() uint32 { + return (volatile.LoadUint32(&o.CK_FG_LOW.Reg) & 0xff0000) >> 16 +} + +// PPA.CK_FG_HIGH: foreground color key higher threshold +func (o *PPA_Type) SetCK_FG_HIGH_COLORKEY_FG_B_HIGH(value uint32) { + volatile.StoreUint32(&o.CK_FG_HIGH.Reg, volatile.LoadUint32(&o.CK_FG_HIGH.Reg)&^(0xff)|value) +} +func (o *PPA_Type) GetCK_FG_HIGH_COLORKEY_FG_B_HIGH() uint32 { + return volatile.LoadUint32(&o.CK_FG_HIGH.Reg) & 0xff +} +func (o *PPA_Type) SetCK_FG_HIGH_COLORKEY_FG_G_HIGH(value uint32) { + volatile.StoreUint32(&o.CK_FG_HIGH.Reg, volatile.LoadUint32(&o.CK_FG_HIGH.Reg)&^(0xff00)|value<<8) +} +func (o *PPA_Type) GetCK_FG_HIGH_COLORKEY_FG_G_HIGH() uint32 { + return (volatile.LoadUint32(&o.CK_FG_HIGH.Reg) & 0xff00) >> 8 +} +func (o *PPA_Type) SetCK_FG_HIGH_COLORKEY_FG_R_HIGH(value uint32) { + volatile.StoreUint32(&o.CK_FG_HIGH.Reg, volatile.LoadUint32(&o.CK_FG_HIGH.Reg)&^(0xff0000)|value<<16) +} +func (o *PPA_Type) GetCK_FG_HIGH_COLORKEY_FG_R_HIGH() uint32 { + return (volatile.LoadUint32(&o.CK_FG_HIGH.Reg) & 0xff0000) >> 16 +} + +// PPA.CK_BG_LOW: background color key lower threshold +func (o *PPA_Type) SetCK_BG_LOW_COLORKEY_BG_B_LOW(value uint32) { + volatile.StoreUint32(&o.CK_BG_LOW.Reg, volatile.LoadUint32(&o.CK_BG_LOW.Reg)&^(0xff)|value) +} +func (o *PPA_Type) GetCK_BG_LOW_COLORKEY_BG_B_LOW() uint32 { + return volatile.LoadUint32(&o.CK_BG_LOW.Reg) & 0xff +} +func (o *PPA_Type) SetCK_BG_LOW_COLORKEY_BG_G_LOW(value uint32) { + volatile.StoreUint32(&o.CK_BG_LOW.Reg, volatile.LoadUint32(&o.CK_BG_LOW.Reg)&^(0xff00)|value<<8) +} +func (o *PPA_Type) GetCK_BG_LOW_COLORKEY_BG_G_LOW() uint32 { + return (volatile.LoadUint32(&o.CK_BG_LOW.Reg) & 0xff00) >> 8 +} +func (o *PPA_Type) SetCK_BG_LOW_COLORKEY_BG_R_LOW(value uint32) { + volatile.StoreUint32(&o.CK_BG_LOW.Reg, volatile.LoadUint32(&o.CK_BG_LOW.Reg)&^(0xff0000)|value<<16) +} +func (o *PPA_Type) GetCK_BG_LOW_COLORKEY_BG_R_LOW() uint32 { + return (volatile.LoadUint32(&o.CK_BG_LOW.Reg) & 0xff0000) >> 16 +} + +// PPA.CK_BG_HIGH: background color key higher threshold +func (o *PPA_Type) SetCK_BG_HIGH_COLORKEY_BG_B_HIGH(value uint32) { + volatile.StoreUint32(&o.CK_BG_HIGH.Reg, volatile.LoadUint32(&o.CK_BG_HIGH.Reg)&^(0xff)|value) +} +func (o *PPA_Type) GetCK_BG_HIGH_COLORKEY_BG_B_HIGH() uint32 { + return volatile.LoadUint32(&o.CK_BG_HIGH.Reg) & 0xff +} +func (o *PPA_Type) SetCK_BG_HIGH_COLORKEY_BG_G_HIGH(value uint32) { + volatile.StoreUint32(&o.CK_BG_HIGH.Reg, volatile.LoadUint32(&o.CK_BG_HIGH.Reg)&^(0xff00)|value<<8) +} +func (o *PPA_Type) GetCK_BG_HIGH_COLORKEY_BG_G_HIGH() uint32 { + return (volatile.LoadUint32(&o.CK_BG_HIGH.Reg) & 0xff00) >> 8 +} +func (o *PPA_Type) SetCK_BG_HIGH_COLORKEY_BG_R_HIGH(value uint32) { + volatile.StoreUint32(&o.CK_BG_HIGH.Reg, volatile.LoadUint32(&o.CK_BG_HIGH.Reg)&^(0xff0000)|value<<16) +} +func (o *PPA_Type) GetCK_BG_HIGH_COLORKEY_BG_R_HIGH() uint32 { + return (volatile.LoadUint32(&o.CK_BG_HIGH.Reg) & 0xff0000) >> 16 +} + +// PPA.CK_DEFAULT: default value when foreground and background both in color key range +func (o *PPA_Type) SetCK_DEFAULT_COLORKEY_DEFAULT_B(value uint32) { + volatile.StoreUint32(&o.CK_DEFAULT.Reg, volatile.LoadUint32(&o.CK_DEFAULT.Reg)&^(0xff)|value) +} +func (o *PPA_Type) GetCK_DEFAULT_COLORKEY_DEFAULT_B() uint32 { + return volatile.LoadUint32(&o.CK_DEFAULT.Reg) & 0xff +} +func (o *PPA_Type) SetCK_DEFAULT_COLORKEY_DEFAULT_G(value uint32) { + volatile.StoreUint32(&o.CK_DEFAULT.Reg, volatile.LoadUint32(&o.CK_DEFAULT.Reg)&^(0xff00)|value<<8) +} +func (o *PPA_Type) GetCK_DEFAULT_COLORKEY_DEFAULT_G() uint32 { + return (volatile.LoadUint32(&o.CK_DEFAULT.Reg) & 0xff00) >> 8 +} +func (o *PPA_Type) SetCK_DEFAULT_COLORKEY_DEFAULT_R(value uint32) { + volatile.StoreUint32(&o.CK_DEFAULT.Reg, volatile.LoadUint32(&o.CK_DEFAULT.Reg)&^(0xff0000)|value<<16) +} +func (o *PPA_Type) GetCK_DEFAULT_COLORKEY_DEFAULT_R() uint32 { + return (volatile.LoadUint32(&o.CK_DEFAULT.Reg) & 0xff0000) >> 16 +} +func (o *PPA_Type) SetCK_DEFAULT_COLORKEY_FG_BG_REVERSE(value uint32) { + volatile.StoreUint32(&o.CK_DEFAULT.Reg, volatile.LoadUint32(&o.CK_DEFAULT.Reg)&^(0x1000000)|value<<24) +} +func (o *PPA_Type) GetCK_DEFAULT_COLORKEY_FG_BG_REVERSE() uint32 { + return (volatile.LoadUint32(&o.CK_DEFAULT.Reg) & 0x1000000) >> 24 +} + +// PPA.SR_SCAL_ROTATE: Scaling and rotating coefficient register +func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_SCAL_X_INT(value uint32) { + volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0xff)|value) +} +func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_SCAL_X_INT() uint32 { + return volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0xff +} +func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_SCAL_X_FRAG(value uint32) { + volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0xf00)|value<<8) +} +func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_SCAL_X_FRAG() uint32 { + return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0xf00) >> 8 +} +func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_SCAL_Y_INT(value uint32) { + volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0xff000)|value<<12) +} +func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_SCAL_Y_INT() uint32 { + return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0xff000) >> 12 +} +func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_SCAL_Y_FRAG(value uint32) { + volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0xf00000)|value<<20) +} +func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_SCAL_Y_FRAG() uint32 { + return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0xf00000) >> 20 +} +func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_ROTATE_ANGLE(value uint32) { + volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x3000000)|value<<24) +} +func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_ROTATE_ANGLE() uint32 { + return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x3000000) >> 24 +} +func (o *PPA_Type) SetSR_SCAL_ROTATE_SCAL_ROTATE_RST(value uint32) { + volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x4000000)|value<<26) +} +func (o *PPA_Type) GetSR_SCAL_ROTATE_SCAL_ROTATE_RST() uint32 { + return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x4000000) >> 26 +} +func (o *PPA_Type) SetSR_SCAL_ROTATE_SCAL_ROTATE_START(value uint32) { + volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x8000000)|value<<27) +} +func (o *PPA_Type) GetSR_SCAL_ROTATE_SCAL_ROTATE_START() uint32 { + return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x8000000) >> 27 +} +func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_MIRROR_X(value uint32) { + volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x10000000)|value<<28) +} +func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_MIRROR_X() uint32 { + return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x10000000) >> 28 +} +func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_MIRROR_Y(value uint32) { + volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x20000000)|value<<29) +} +func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_MIRROR_Y() uint32 { + return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x20000000) >> 29 +} + +// PPA.SR_MEM_PD: SR memory power done register +func (o *PPA_Type) SetSR_MEM_PD_SR_MEM_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.SR_MEM_PD.Reg, volatile.LoadUint32(&o.SR_MEM_PD.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetSR_MEM_PD_SR_MEM_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.SR_MEM_PD.Reg) & 0x1 +} +func (o *PPA_Type) SetSR_MEM_PD_SR_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SR_MEM_PD.Reg, volatile.LoadUint32(&o.SR_MEM_PD.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetSR_MEM_PD_SR_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SR_MEM_PD.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetSR_MEM_PD_SR_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SR_MEM_PD.Reg, volatile.LoadUint32(&o.SR_MEM_PD.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetSR_MEM_PD_SR_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SR_MEM_PD.Reg) & 0x4) >> 2 +} + +// PPA.REG_CONF: Register clock enable register +func (o *PPA_Type) SetREG_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REG_CONF.Reg, volatile.LoadUint32(&o.REG_CONF.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetREG_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.REG_CONF.Reg) & 0x1 +} + +// PPA.CLUT_CNT: BLEND CLUT write counter register +func (o *PPA_Type) SetCLUT_CNT_BLEND0_CLUT_CNT(value uint32) { + volatile.StoreUint32(&o.CLUT_CNT.Reg, volatile.LoadUint32(&o.CLUT_CNT.Reg)&^(0x1ff)|value) +} +func (o *PPA_Type) GetCLUT_CNT_BLEND0_CLUT_CNT() uint32 { + return volatile.LoadUint32(&o.CLUT_CNT.Reg) & 0x1ff +} +func (o *PPA_Type) SetCLUT_CNT_BLEND1_CLUT_CNT(value uint32) { + volatile.StoreUint32(&o.CLUT_CNT.Reg, volatile.LoadUint32(&o.CLUT_CNT.Reg)&^(0x3fe00)|value<<9) +} +func (o *PPA_Type) GetCLUT_CNT_BLEND1_CLUT_CNT() uint32 { + return (volatile.LoadUint32(&o.CLUT_CNT.Reg) & 0x3fe00) >> 9 +} + +// PPA.BLEND_ST: Blending engine status register +func (o *PPA_Type) SetBLEND_ST_BLEND_SIZE_DIFF_ST(value uint32) { + volatile.StoreUint32(&o.BLEND_ST.Reg, volatile.LoadUint32(&o.BLEND_ST.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetBLEND_ST_BLEND_SIZE_DIFF_ST() uint32 { + return volatile.LoadUint32(&o.BLEND_ST.Reg) & 0x1 +} + +// PPA.SR_PARAM_ERR_ST: Scaling and rotating coefficient error register +func (o *PPA_Type) SetSR_PARAM_ERR_ST_TX_DSCR_VB_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_TX_DSCR_VB_ERR_ST() uint32 { + return volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x1 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_TX_DSCR_HB_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_TX_DSCR_HB_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x2) >> 1 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_Y_RX_SCAL_EQUAL_0_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x4)|value<<2) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_Y_RX_SCAL_EQUAL_0_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x4) >> 2 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_RX_DSCR_VB_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x8)|value<<3) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_RX_DSCR_VB_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x8) >> 3 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_YDST_LEN_TOO_SAMLL_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x10)|value<<4) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_YDST_LEN_TOO_SAMLL_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x10) >> 4 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_YDST_LEN_TOO_LARGE_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x20)|value<<5) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_YDST_LEN_TOO_LARGE_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x20) >> 5 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_X_RX_SCAL_EQUAL_0_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x40)|value<<6) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_X_RX_SCAL_EQUAL_0_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x40) >> 6 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_RX_DSCR_HB_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x80)|value<<7) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_RX_DSCR_HB_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x80) >> 7 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_XDST_LEN_TOO_SAMLL_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x100)|value<<8) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_XDST_LEN_TOO_SAMLL_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x100) >> 8 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_XDST_LEN_TOO_LARGE_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x200)|value<<9) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_XDST_LEN_TOO_LARGE_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x200) >> 9 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_X_YUV420_RX_SCALE_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x400)|value<<10) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_X_YUV420_RX_SCALE_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x400) >> 10 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_Y_YUV420_RX_SCALE_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x800)|value<<11) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_Y_YUV420_RX_SCALE_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x800) >> 11 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_X_YUV420_TX_SCALE_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x1000)|value<<12) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_X_YUV420_TX_SCALE_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x1000) >> 12 +} +func (o *PPA_Type) SetSR_PARAM_ERR_ST_Y_YUV420_TX_SCALE_ERR_ST(value uint32) { + volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x2000)|value<<13) +} +func (o *PPA_Type) GetSR_PARAM_ERR_ST_Y_YUV420_TX_SCALE_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x2000) >> 13 +} + +// PPA.SR_STATUS: SR FSM register +func (o *PPA_Type) SetSR_STATUS_SR_RX_DSCR_SAMPLE_STATE(value uint32) { + volatile.StoreUint32(&o.SR_STATUS.Reg, volatile.LoadUint32(&o.SR_STATUS.Reg)&^(0x3)|value) +} +func (o *PPA_Type) GetSR_STATUS_SR_RX_DSCR_SAMPLE_STATE() uint32 { + return volatile.LoadUint32(&o.SR_STATUS.Reg) & 0x3 +} +func (o *PPA_Type) SetSR_STATUS_SR_RX_SCAN_STATE(value uint32) { + volatile.StoreUint32(&o.SR_STATUS.Reg, volatile.LoadUint32(&o.SR_STATUS.Reg)&^(0xc)|value<<2) +} +func (o *PPA_Type) GetSR_STATUS_SR_RX_SCAN_STATE() uint32 { + return (volatile.LoadUint32(&o.SR_STATUS.Reg) & 0xc) >> 2 +} +func (o *PPA_Type) SetSR_STATUS_SR_TX_DSCR_SAMPLE_STATE(value uint32) { + volatile.StoreUint32(&o.SR_STATUS.Reg, volatile.LoadUint32(&o.SR_STATUS.Reg)&^(0x30)|value<<4) +} +func (o *PPA_Type) GetSR_STATUS_SR_TX_DSCR_SAMPLE_STATE() uint32 { + return (volatile.LoadUint32(&o.SR_STATUS.Reg) & 0x30) >> 4 +} +func (o *PPA_Type) SetSR_STATUS_SR_TX_SCAN_STATE(value uint32) { + volatile.StoreUint32(&o.SR_STATUS.Reg, volatile.LoadUint32(&o.SR_STATUS.Reg)&^(0x1c0)|value<<6) +} +func (o *PPA_Type) GetSR_STATUS_SR_TX_SCAN_STATE() uint32 { + return (volatile.LoadUint32(&o.SR_STATUS.Reg) & 0x1c0) >> 6 +} + +// PPA.ECO_LOW: Reserved. +func (o *PPA_Type) SetECO_LOW(value uint32) { + volatile.StoreUint32(&o.ECO_LOW.Reg, value) +} +func (o *PPA_Type) GetECO_LOW() uint32 { + return volatile.LoadUint32(&o.ECO_LOW.Reg) +} + +// PPA.ECO_HIGH: Reserved. +func (o *PPA_Type) SetECO_HIGH(value uint32) { + volatile.StoreUint32(&o.ECO_HIGH.Reg, value) +} +func (o *PPA_Type) GetECO_HIGH() uint32 { + return volatile.LoadUint32(&o.ECO_HIGH.Reg) +} + +// PPA.ECO_CELL_CTRL: Reserved. +func (o *PPA_Type) SetECO_CELL_CTRL_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.ECO_CELL_CTRL.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL.Reg)&^(0x1)|value) +} +func (o *PPA_Type) GetECO_CELL_CTRL_RDN_RESULT() uint32 { + return volatile.LoadUint32(&o.ECO_CELL_CTRL.Reg) & 0x1 +} +func (o *PPA_Type) SetECO_CELL_CTRL_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.ECO_CELL_CTRL.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PPA_Type) GetECO_CELL_CTRL_RDN_ENA() uint32 { + return (volatile.LoadUint32(&o.ECO_CELL_CTRL.Reg) & 0x2) >> 1 +} + +// PPA.SRAM_CTRL: PPA SRAM Control Register +func (o *PPA_Type) SetSRAM_CTRL_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.SRAM_CTRL.Reg, volatile.LoadUint32(&o.SRAM_CTRL.Reg)&^(0x3fff)|value) +} +func (o *PPA_Type) GetSRAM_CTRL_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.SRAM_CTRL.Reg) & 0x3fff +} + +// PPA.DATE: PPA Version register +func (o *PPA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *PPA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// PVT Peripheral +type PVT_Type struct { + PMUP_BITMAP_HIGH0 volatile.Register32 // 0x0 + PMUP_BITMAP_HIGH1 volatile.Register32 // 0x4 + PMUP_BITMAP_HIGH2 volatile.Register32 // 0x8 + PMUP_BITMAP_HIGH3 volatile.Register32 // 0xC + PMUP_BITMAP_HIGH4 volatile.Register32 // 0x10 + PMUP_BITMAP_LOW0 volatile.Register32 // 0x14 + PMUP_BITMAP_LOW1 volatile.Register32 // 0x18 + PMUP_BITMAP_LOW2 volatile.Register32 // 0x1C + PMUP_BITMAP_LOW3 volatile.Register32 // 0x20 + PMUP_BITMAP_LOW4 volatile.Register32 // 0x24 + PMUP_DRV_CFG volatile.Register32 // 0x28 + PMUP_CHANNEL_CFG volatile.Register32 // 0x2C + CLK_CFG volatile.Register32 // 0x30 + DBIAS_CHANNEL_SEL0 volatile.Register32 // 0x34 + DBIAS_CHANNEL_SEL1 volatile.Register32 // 0x38 + DBIAS_CHANNEL0_SEL volatile.Register32 // 0x3C + DBIAS_CHANNEL1_SEL volatile.Register32 // 0x40 + DBIAS_CHANNEL2_SEL volatile.Register32 // 0x44 + DBIAS_CHANNEL3_SEL volatile.Register32 // 0x48 + DBIAS_CHANNEL4_SEL volatile.Register32 // 0x4C + DBIAS_CMD0 volatile.Register32 // 0x50 + DBIAS_CMD1 volatile.Register32 // 0x54 + DBIAS_CMD2 volatile.Register32 // 0x58 + DBIAS_CMD3 volatile.Register32 // 0x5C + DBIAS_CMD4 volatile.Register32 // 0x60 + DBIAS_TIMER volatile.Register32 // 0x64 + COMB_PD_SITE0_UNIT0_VT0_CONF1 volatile.Register32 // 0x68 + COMB_PD_SITE0_UNIT1_VT0_CONF1 volatile.Register32 // 0x6C + COMB_PD_SITE0_UNIT2_VT0_CONF1 volatile.Register32 // 0x70 + COMB_PD_SITE0_UNIT3_VT0_CONF1 volatile.Register32 // 0x74 + COMB_PD_SITE0_UNIT0_VT1_CONF1 volatile.Register32 // 0x78 + COMB_PD_SITE0_UNIT1_VT1_CONF1 volatile.Register32 // 0x7C + COMB_PD_SITE0_UNIT2_VT1_CONF1 volatile.Register32 // 0x80 + COMB_PD_SITE0_UNIT3_VT1_CONF1 volatile.Register32 // 0x84 + COMB_PD_SITE0_UNIT0_VT2_CONF1 volatile.Register32 // 0x88 + COMB_PD_SITE0_UNIT1_VT2_CONF1 volatile.Register32 // 0x8C + COMB_PD_SITE0_UNIT2_VT2_CONF1 volatile.Register32 // 0x90 + COMB_PD_SITE0_UNIT3_VT2_CONF1 volatile.Register32 // 0x94 + COMB_PD_SITE1_UNIT0_VT0_CONF1 volatile.Register32 // 0x98 + COMB_PD_SITE1_UNIT1_VT0_CONF1 volatile.Register32 // 0x9C + COMB_PD_SITE1_UNIT2_VT0_CONF1 volatile.Register32 // 0xA0 + COMB_PD_SITE1_UNIT3_VT0_CONF1 volatile.Register32 // 0xA4 + COMB_PD_SITE1_UNIT0_VT1_CONF1 volatile.Register32 // 0xA8 + COMB_PD_SITE1_UNIT1_VT1_CONF1 volatile.Register32 // 0xAC + COMB_PD_SITE1_UNIT2_VT1_CONF1 volatile.Register32 // 0xB0 + COMB_PD_SITE1_UNIT3_VT1_CONF1 volatile.Register32 // 0xB4 + COMB_PD_SITE1_UNIT0_VT2_CONF1 volatile.Register32 // 0xB8 + COMB_PD_SITE1_UNIT1_VT2_CONF1 volatile.Register32 // 0xBC + COMB_PD_SITE1_UNIT2_VT2_CONF1 volatile.Register32 // 0xC0 + COMB_PD_SITE1_UNIT3_VT2_CONF1 volatile.Register32 // 0xC4 + COMB_PD_SITE2_UNIT0_VT0_CONF1 volatile.Register32 // 0xC8 + COMB_PD_SITE2_UNIT1_VT0_CONF1 volatile.Register32 // 0xCC + COMB_PD_SITE2_UNIT2_VT0_CONF1 volatile.Register32 // 0xD0 + COMB_PD_SITE2_UNIT3_VT0_CONF1 volatile.Register32 // 0xD4 + COMB_PD_SITE2_UNIT0_VT1_CONF1 volatile.Register32 // 0xD8 + COMB_PD_SITE2_UNIT1_VT1_CONF1 volatile.Register32 // 0xDC + COMB_PD_SITE2_UNIT2_VT1_CONF1 volatile.Register32 // 0xE0 + COMB_PD_SITE2_UNIT3_VT1_CONF1 volatile.Register32 // 0xE4 + COMB_PD_SITE2_UNIT0_VT2_CONF1 volatile.Register32 // 0xE8 + COMB_PD_SITE2_UNIT1_VT2_CONF1 volatile.Register32 // 0xEC + COMB_PD_SITE2_UNIT2_VT2_CONF1 volatile.Register32 // 0xF0 + COMB_PD_SITE2_UNIT3_VT2_CONF1 volatile.Register32 // 0xF4 + COMB_PD_SITE3_UNIT0_VT0_CONF1 volatile.Register32 // 0xF8 + COMB_PD_SITE3_UNIT1_VT0_CONF1 volatile.Register32 // 0xFC + COMB_PD_SITE3_UNIT2_VT0_CONF1 volatile.Register32 // 0x100 + COMB_PD_SITE3_UNIT3_VT0_CONF1 volatile.Register32 // 0x104 + COMB_PD_SITE3_UNIT0_VT1_CONF1 volatile.Register32 // 0x108 + COMB_PD_SITE3_UNIT1_VT1_CONF1 volatile.Register32 // 0x10C + COMB_PD_SITE3_UNIT2_VT1_CONF1 volatile.Register32 // 0x110 + COMB_PD_SITE3_UNIT3_VT1_CONF1 volatile.Register32 // 0x114 + COMB_PD_SITE3_UNIT0_VT2_CONF1 volatile.Register32 // 0x118 + COMB_PD_SITE3_UNIT1_VT2_CONF1 volatile.Register32 // 0x11C + COMB_PD_SITE3_UNIT2_VT2_CONF1 volatile.Register32 // 0x120 + COMB_PD_SITE3_UNIT3_VT2_CONF1 volatile.Register32 // 0x124 + COMB_PD_SITE0_UNIT0_VT0_CONF2 volatile.Register32 // 0x128 + COMB_PD_SITE0_UNIT1_VT0_CONF2 volatile.Register32 // 0x12C + COMB_PD_SITE0_UNIT2_VT0_CONF2 volatile.Register32 // 0x130 + COMB_PD_SITE0_UNIT3_VT0_CONF2 volatile.Register32 // 0x134 + COMB_PD_SITE0_UNIT0_VT1_CONF2 volatile.Register32 // 0x138 + COMB_PD_SITE0_UNIT1_VT1_CONF2 volatile.Register32 // 0x13C + COMB_PD_SITE0_UNIT2_VT1_CONF2 volatile.Register32 // 0x140 + COMB_PD_SITE0_UNIT3_VT1_CONF2 volatile.Register32 // 0x144 + COMB_PD_SITE0_UNIT0_VT2_CONF2 volatile.Register32 // 0x148 + COMB_PD_SITE0_UNIT1_VT2_CONF2 volatile.Register32 // 0x14C + COMB_PD_SITE0_UNIT2_VT2_CONF2 volatile.Register32 // 0x150 + COMB_PD_SITE0_UNIT3_VT2_CONF2 volatile.Register32 // 0x154 + COMB_PD_SITE1_UNIT0_VT0_CONF2 volatile.Register32 // 0x158 + COMB_PD_SITE1_UNIT1_VT0_CONF2 volatile.Register32 // 0x15C + COMB_PD_SITE1_UNIT2_VT0_CONF2 volatile.Register32 // 0x160 + COMB_PD_SITE1_UNIT3_VT0_CONF2 volatile.Register32 // 0x164 + COMB_PD_SITE1_UNIT0_VT1_CONF2 volatile.Register32 // 0x168 + COMB_PD_SITE1_UNIT1_VT1_CONF2 volatile.Register32 // 0x16C + COMB_PD_SITE1_UNIT2_VT1_CONF2 volatile.Register32 // 0x170 + COMB_PD_SITE1_UNIT3_VT1_CONF2 volatile.Register32 // 0x174 + COMB_PD_SITE1_UNIT0_VT2_CONF2 volatile.Register32 // 0x178 + COMB_PD_SITE1_UNIT1_VT2_CONF2 volatile.Register32 // 0x17C + COMB_PD_SITE1_UNIT2_VT2_CONF2 volatile.Register32 // 0x180 + COMB_PD_SITE1_UNIT3_VT2_CONF2 volatile.Register32 // 0x184 + COMB_PD_SITE2_UNIT0_VT0_CONF2 volatile.Register32 // 0x188 + COMB_PD_SITE2_UNIT1_VT0_CONF2 volatile.Register32 // 0x18C + COMB_PD_SITE2_UNIT2_VT0_CONF2 volatile.Register32 // 0x190 + COMB_PD_SITE2_UNIT3_VT0_CONF2 volatile.Register32 // 0x194 + COMB_PD_SITE2_UNIT0_VT1_CONF2 volatile.Register32 // 0x198 + COMB_PD_SITE2_UNIT1_VT1_CONF2 volatile.Register32 // 0x19C + COMB_PD_SITE2_UNIT2_VT1_CONF2 volatile.Register32 // 0x1A0 + COMB_PD_SITE2_UNIT3_VT1_CONF2 volatile.Register32 // 0x1A4 + COMB_PD_SITE2_UNIT0_VT2_CONF2 volatile.Register32 // 0x1A8 + COMB_PD_SITE2_UNIT1_VT2_CONF2 volatile.Register32 // 0x1AC + COMB_PD_SITE2_UNIT2_VT2_CONF2 volatile.Register32 // 0x1B0 + COMB_PD_SITE2_UNIT3_VT2_CONF2 volatile.Register32 // 0x1B4 + COMB_PD_SITE3_UNIT0_VT0_CONF2 volatile.Register32 // 0x1B8 + COMB_PD_SITE3_UNIT1_VT0_CONF2 volatile.Register32 // 0x1BC + COMB_PD_SITE3_UNIT2_VT0_CONF2 volatile.Register32 // 0x1C0 + COMB_PD_SITE3_UNIT3_VT0_CONF2 volatile.Register32 // 0x1C4 + COMB_PD_SITE3_UNIT0_VT1_CONF2 volatile.Register32 // 0x1C8 + COMB_PD_SITE3_UNIT1_VT1_CONF2 volatile.Register32 // 0x1CC + COMB_PD_SITE3_UNIT2_VT1_CONF2 volatile.Register32 // 0x1D0 + COMB_PD_SITE3_UNIT3_VT1_CONF2 volatile.Register32 // 0x1D4 + COMB_PD_SITE3_UNIT0_VT2_CONF2 volatile.Register32 // 0x1D8 + COMB_PD_SITE3_UNIT1_VT2_CONF2 volatile.Register32 // 0x1DC + COMB_PD_SITE3_UNIT2_VT2_CONF2 volatile.Register32 // 0x1E0 + COMB_PD_SITE3_UNIT3_VT2_CONF2 volatile.Register32 // 0x1E4 + VALUE_UPDATE volatile.Register32 // 0x1E8 + _ [3600]byte + DATE volatile.Register32 // 0xFFC +} + +// PVT.PMUP_BITMAP_HIGH0: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_HIGH0(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_HIGH0.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_HIGH0() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH0.Reg) +} + +// PVT.PMUP_BITMAP_HIGH1: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_HIGH1(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_HIGH1.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_HIGH1() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH1.Reg) +} + +// PVT.PMUP_BITMAP_HIGH2: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_HIGH2(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_HIGH2.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_HIGH2() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH2.Reg) +} + +// PVT.PMUP_BITMAP_HIGH3: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_HIGH3(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_HIGH3.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_HIGH3() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH3.Reg) +} + +// PVT.PMUP_BITMAP_HIGH4: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_HIGH4(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_HIGH4.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_HIGH4() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH4.Reg) +} + +// PVT.PMUP_BITMAP_LOW0: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_LOW0(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_LOW0.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_LOW0() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_LOW0.Reg) +} + +// PVT.PMUP_BITMAP_LOW1: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_LOW1(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_LOW1.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_LOW1() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_LOW1.Reg) +} + +// PVT.PMUP_BITMAP_LOW2: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_LOW2(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_LOW2.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_LOW2() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_LOW2.Reg) +} + +// PVT.PMUP_BITMAP_LOW3: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_LOW3(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_LOW3.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_LOW3() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_LOW3.Reg) +} + +// PVT.PMUP_BITMAP_LOW4: select valid pvt channel +func (o *PVT_Type) SetPMUP_BITMAP_LOW4(value uint32) { + volatile.StoreUint32(&o.PMUP_BITMAP_LOW4.Reg, value) +} +func (o *PVT_Type) GetPMUP_BITMAP_LOW4() uint32 { + return volatile.LoadUint32(&o.PMUP_BITMAP_LOW4.Reg) +} + +// PVT.PMUP_DRV_CFG: configure pump drv +func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_EN(value uint32) { + volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x200)|value<<9) +} +func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_EN() uint32 { + return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x200) >> 9 +} +func (o *PVT_Type) SetPMUP_DRV_CFG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x400)|value<<10) +} +func (o *PVT_Type) GetPMUP_DRV_CFG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x400) >> 10 +} +func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV4(value uint32) { + volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x7800)|value<<11) +} +func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV4() uint32 { + return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x7800) >> 11 +} +func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV3(value uint32) { + volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x78000)|value<<15) +} +func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV3() uint32 { + return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x78000) >> 15 +} +func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV2(value uint32) { + volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x780000)|value<<19) +} +func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV2() uint32 { + return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x780000) >> 19 +} +func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV1(value uint32) { + volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x7800000)|value<<23) +} +func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV1() uint32 { + return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x7800000) >> 23 +} +func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV0(value uint32) { + volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x78000000)|value<<27) +} +func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV0() uint32 { + return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x78000000) >> 27 +} + +// PVT.PMUP_CHANNEL_CFG: configure the code of valid pump channel code +func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE4(value uint32) { + volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0xf80)|value<<7) +} +func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE4() uint32 { + return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0xf80) >> 7 +} +func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE3(value uint32) { + volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0x1f000)|value<<12) +} +func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE3() uint32 { + return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0x1f000) >> 12 +} +func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE2(value uint32) { + volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0x3e0000)|value<<17) +} +func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE2() uint32 { + return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0x3e0000) >> 17 +} +func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE1(value uint32) { + volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0x7c00000)|value<<22) +} +func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE1() uint32 { + return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0x7c00000) >> 22 +} +func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE0(value uint32) { + volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0xf8000000)|value<<27) +} +func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE0() uint32 { + return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0xf8000000) >> 27 +} + +// PVT.CLK_CFG: configure pvt clk +func (o *PVT_Type) SetCLK_CFG_PUMP_CLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0xff)|value) +} +func (o *PVT_Type) GetCLK_CFG_PUMP_CLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLK_CFG.Reg) & 0xff +} +func (o *PVT_Type) SetCLK_CFG_MONITOR_CLK_PVT_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0x100)|value<<8) +} +func (o *PVT_Type) GetCLK_CFG_MONITOR_CLK_PVT_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CFG.Reg) & 0x100) >> 8 +} +func (o *PVT_Type) SetCLK_CFG_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCLK_CFG_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CFG.Reg) & 0x80000000) >> 31 +} + +// PVT.DBIAS_CHANNEL_SEL0: needs desc +func (o *PVT_Type) SetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL3_SEL(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL0.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg)&^(0x7f0)|value<<4) +} +func (o *PVT_Type) GetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL3_SEL() uint32 { + return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg) & 0x7f0) >> 4 +} +func (o *PVT_Type) SetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL2_SEL(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL0.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg)&^(0x3f800)|value<<11) +} +func (o *PVT_Type) GetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL2_SEL() uint32 { + return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg) & 0x3f800) >> 11 +} +func (o *PVT_Type) SetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL1_SEL(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL0.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg)&^(0x1fc0000)|value<<18) +} +func (o *PVT_Type) GetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL1_SEL() uint32 { + return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg) & 0x1fc0000) >> 18 +} +func (o *PVT_Type) SetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL0_SEL(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL0.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg)&^(0xfe000000)|value<<25) +} +func (o *PVT_Type) GetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL0_SEL() uint32 { + return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg) & 0xfe000000) >> 25 +} + +// PVT.DBIAS_CHANNEL_SEL1: needs desc +func (o *PVT_Type) SetDBIAS_CHANNEL_SEL1_DBIAS_CHANNEL4_SEL(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL1.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL1.Reg)&^(0xfe000000)|value<<25) +} +func (o *PVT_Type) GetDBIAS_CHANNEL_SEL1_DBIAS_CHANNEL4_SEL() uint32 { + return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL1.Reg) & 0xfe000000) >> 25 +} + +// PVT.DBIAS_CHANNEL0_SEL: needs desc +func (o *PVT_Type) SetDBIAS_CHANNEL0_SEL_DBIAS_CHANNEL0_CFG(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL0_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL0_SEL.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CHANNEL0_SEL_DBIAS_CHANNEL0_CFG() uint32 { + return volatile.LoadUint32(&o.DBIAS_CHANNEL0_SEL.Reg) & 0x1ffff +} + +// PVT.DBIAS_CHANNEL1_SEL: needs desc +func (o *PVT_Type) SetDBIAS_CHANNEL1_SEL_DBIAS_CHANNEL1_CFG(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL1_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL1_SEL.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CHANNEL1_SEL_DBIAS_CHANNEL1_CFG() uint32 { + return volatile.LoadUint32(&o.DBIAS_CHANNEL1_SEL.Reg) & 0x1ffff +} + +// PVT.DBIAS_CHANNEL2_SEL: needs desc +func (o *PVT_Type) SetDBIAS_CHANNEL2_SEL_DBIAS_CHANNEL2_CFG(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL2_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL2_SEL.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CHANNEL2_SEL_DBIAS_CHANNEL2_CFG() uint32 { + return volatile.LoadUint32(&o.DBIAS_CHANNEL2_SEL.Reg) & 0x1ffff +} + +// PVT.DBIAS_CHANNEL3_SEL: needs desc +func (o *PVT_Type) SetDBIAS_CHANNEL3_SEL_DBIAS_CHANNEL3_CFG(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL3_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL3_SEL.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CHANNEL3_SEL_DBIAS_CHANNEL3_CFG() uint32 { + return volatile.LoadUint32(&o.DBIAS_CHANNEL3_SEL.Reg) & 0x1ffff +} + +// PVT.DBIAS_CHANNEL4_SEL: needs desc +func (o *PVT_Type) SetDBIAS_CHANNEL4_SEL_DBIAS_CHANNEL4_CFG(value uint32) { + volatile.StoreUint32(&o.DBIAS_CHANNEL4_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL4_SEL.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CHANNEL4_SEL_DBIAS_CHANNEL4_CFG() uint32 { + return volatile.LoadUint32(&o.DBIAS_CHANNEL4_SEL.Reg) & 0x1ffff +} + +// PVT.DBIAS_CMD0: needs desc +func (o *PVT_Type) SetDBIAS_CMD0(value uint32) { + volatile.StoreUint32(&o.DBIAS_CMD0.Reg, volatile.LoadUint32(&o.DBIAS_CMD0.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CMD0() uint32 { + return volatile.LoadUint32(&o.DBIAS_CMD0.Reg) & 0x1ffff +} + +// PVT.DBIAS_CMD1: needs desc +func (o *PVT_Type) SetDBIAS_CMD1(value uint32) { + volatile.StoreUint32(&o.DBIAS_CMD1.Reg, volatile.LoadUint32(&o.DBIAS_CMD1.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CMD1() uint32 { + return volatile.LoadUint32(&o.DBIAS_CMD1.Reg) & 0x1ffff +} + +// PVT.DBIAS_CMD2: needs desc +func (o *PVT_Type) SetDBIAS_CMD2(value uint32) { + volatile.StoreUint32(&o.DBIAS_CMD2.Reg, volatile.LoadUint32(&o.DBIAS_CMD2.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CMD2() uint32 { + return volatile.LoadUint32(&o.DBIAS_CMD2.Reg) & 0x1ffff +} + +// PVT.DBIAS_CMD3: needs desc +func (o *PVT_Type) SetDBIAS_CMD3(value uint32) { + volatile.StoreUint32(&o.DBIAS_CMD3.Reg, volatile.LoadUint32(&o.DBIAS_CMD3.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CMD3() uint32 { + return volatile.LoadUint32(&o.DBIAS_CMD3.Reg) & 0x1ffff +} + +// PVT.DBIAS_CMD4: needs desc +func (o *PVT_Type) SetDBIAS_CMD4(value uint32) { + volatile.StoreUint32(&o.DBIAS_CMD4.Reg, volatile.LoadUint32(&o.DBIAS_CMD4.Reg)&^(0x1ffff)|value) +} +func (o *PVT_Type) GetDBIAS_CMD4() uint32 { + return volatile.LoadUint32(&o.DBIAS_CMD4.Reg) & 0x1ffff +} + +// PVT.DBIAS_TIMER: needs desc +func (o *PVT_Type) SetDBIAS_TIMER_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.DBIAS_TIMER.Reg, volatile.LoadUint32(&o.DBIAS_TIMER.Reg)&^(0x7fff8000)|value<<15) +} +func (o *PVT_Type) GetDBIAS_TIMER_TIMER_TARGET() uint32 { + return (volatile.LoadUint32(&o.DBIAS_TIMER.Reg) & 0x7fff8000) >> 15 +} +func (o *PVT_Type) SetDBIAS_TIMER_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.DBIAS_TIMER.Reg, volatile.LoadUint32(&o.DBIAS_TIMER.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetDBIAS_TIMER_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.DBIAS_TIMER.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT0_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT1_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT2_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT3_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT0_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT1_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT2_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT3_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT0_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT1_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT2_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT3_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT0_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT1_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT2_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT3_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT0_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT1_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT2_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT3_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT0_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT1_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT2_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE1_UNIT3_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT0_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT1_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT2_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT3_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT0_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT1_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT2_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT3_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT0_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT1_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT2_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE2_UNIT3_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT0_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT1_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT2_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT3_VT0_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT0_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT1_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT2_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT3_VT1_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT0_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT1_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT2_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE3_UNIT3_VT2_CONF1: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x2) >> 1 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x3fc)|value<<2) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x3fc) >> 2 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x7f800000)|value<<23) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x7f800000) >> 23 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x80000000) >> 31 +} + +// PVT.COMB_PD_SITE0_UNIT0_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT1_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT2_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT3_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT0_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT1_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT2_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT3_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT0_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT1_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT2_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE0_UNIT3_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT0_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT1_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT2_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT3_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT0_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT1_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT2_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT3_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT0_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT1_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT2_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE1_UNIT3_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT0_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT1_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT2_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT3_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT0_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT1_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT2_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT3_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT0_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT1_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT2_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE2_UNIT3_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT0_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT1_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT2_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT3_VT0_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT0_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT1_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT2_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT3_VT1_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT0_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT1_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT2_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.COMB_PD_SITE3_UNIT3_VT2_CONF2: needs desc +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg)&^(0x3)|value) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3() uint32 { + return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg) & 0x3 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg)&^(0x8000)|value<<15) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg) & 0x8000) >> 15 +} +func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3(value uint32) { + volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3() uint32 { + return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PVT.VALUE_UPDATE: needs field desc +func (o *PVT_Type) SetVALUE_UPDATE(value uint32) { + volatile.StoreUint32(&o.VALUE_UPDATE.Reg, volatile.LoadUint32(&o.VALUE_UPDATE.Reg)&^(0x1)|value) +} +func (o *PVT_Type) GetVALUE_UPDATE() uint32 { + return volatile.LoadUint32(&o.VALUE_UPDATE.Reg) & 0x1 +} +func (o *PVT_Type) SetVALUE_UPDATE_BYPASS(value uint32) { + volatile.StoreUint32(&o.VALUE_UPDATE.Reg, volatile.LoadUint32(&o.VALUE_UPDATE.Reg)&^(0x2)|value<<1) +} +func (o *PVT_Type) GetVALUE_UPDATE_BYPASS() uint32 { + return (volatile.LoadUint32(&o.VALUE_UPDATE.Reg) & 0x2) >> 1 +} + +// PVT.DATE: version register +func (o *PVT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *PVT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Remote Control +type RMT_Type struct { + TX_CH0DATA volatile.Register32 // 0x0 + TX_CH1DATA volatile.Register32 // 0x4 + TX_CH2DATA volatile.Register32 // 0x8 + TX_CH3DATA volatile.Register32 // 0xC + RX_CH0DATA volatile.Register32 // 0x10 + RX_CH1DATA volatile.Register32 // 0x14 + RX_CH2DATA volatile.Register32 // 0x18 + RX_CH3DATA volatile.Register32 // 0x1C + TX_CH0CONF0 volatile.Register32 // 0x20 + TX_CH1CONF0 volatile.Register32 // 0x24 + TX_CH2CONF0 volatile.Register32 // 0x28 + TX_CH3CONF0 volatile.Register32 // 0x2C + RX_CH0CONF0 volatile.Register32 // 0x30 + RX_CH0CONF1 volatile.Register32 // 0x34 + RX_CH1CONF0 volatile.Register32 // 0x38 + RX_CH1CONF1 volatile.Register32 // 0x3C + RX_CH2CONF0 volatile.Register32 // 0x40 + RX_CH2CONF1 volatile.Register32 // 0x44 + RX_CH3CONF0 volatile.Register32 // 0x48 + RX_CH3CONF1 volatile.Register32 // 0x4C + TX_CH0STATUS volatile.Register32 // 0x50 + TX_CH1STATUS volatile.Register32 // 0x54 + TX_CH2STATUS volatile.Register32 // 0x58 + TX_CH3STATUS volatile.Register32 // 0x5C + RX_CH0STATUS volatile.Register32 // 0x60 + RX_CH1STATUS volatile.Register32 // 0x64 + RX_CH2STATUS volatile.Register32 // 0x68 + RX_CH3STATUS volatile.Register32 // 0x6C + INT_RAW volatile.Register32 // 0x70 + INT_ST volatile.Register32 // 0x74 + INT_ENA volatile.Register32 // 0x78 + INT_CLR volatile.Register32 // 0x7C + CH0CARRIER_DUTY volatile.Register32 // 0x80 + CH1CARRIER_DUTY volatile.Register32 // 0x84 + CH2CARRIER_DUTY volatile.Register32 // 0x88 + CH3CARRIER_DUTY volatile.Register32 // 0x8C + CH0_RX_CARRIER_RM volatile.Register32 // 0x90 + CH1_RX_CARRIER_RM volatile.Register32 // 0x94 + CH2_RX_CARRIER_RM volatile.Register32 // 0x98 + CH3_RX_CARRIER_RM volatile.Register32 // 0x9C + CH0_TX_LIM volatile.Register32 // 0xA0 + CH1_TX_LIM volatile.Register32 // 0xA4 + CH2_TX_LIM volatile.Register32 // 0xA8 + CH3_TX_LIM volatile.Register32 // 0xAC + CH0_RX_LIM volatile.Register32 // 0xB0 + CH1_RX_LIM volatile.Register32 // 0xB4 + CH2_RX_LIM volatile.Register32 // 0xB8 + CH3_RX_LIM volatile.Register32 // 0xBC + SYS_CONF volatile.Register32 // 0xC0 + TX_SIM volatile.Register32 // 0xC4 + REF_CNT_RST volatile.Register32 // 0xC8 + DATE volatile.Register32 // 0xCC +} + +// RMT.TX_CH0DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetTX_CH0DATA(value uint32) { + volatile.StoreUint32(&o.TX_CH0DATA.Reg, value) +} +func (o *RMT_Type) GetTX_CH0DATA() uint32 { + return volatile.LoadUint32(&o.TX_CH0DATA.Reg) +} + +// RMT.TX_CH1DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetTX_CH1DATA(value uint32) { + volatile.StoreUint32(&o.TX_CH1DATA.Reg, value) +} +func (o *RMT_Type) GetTX_CH1DATA() uint32 { + return volatile.LoadUint32(&o.TX_CH1DATA.Reg) +} + +// RMT.TX_CH2DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetTX_CH2DATA(value uint32) { + volatile.StoreUint32(&o.TX_CH2DATA.Reg, value) +} +func (o *RMT_Type) GetTX_CH2DATA() uint32 { + return volatile.LoadUint32(&o.TX_CH2DATA.Reg) +} + +// RMT.TX_CH3DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetTX_CH3DATA(value uint32) { + volatile.StoreUint32(&o.TX_CH3DATA.Reg, value) +} +func (o *RMT_Type) GetTX_CH3DATA() uint32 { + return volatile.LoadUint32(&o.TX_CH3DATA.Reg) +} + +// RMT.RX_CH0DATA: The read and write data register for CHANNEL$n by apb fifo access. +func (o *RMT_Type) SetRX_CH0DATA(value uint32) { + volatile.StoreUint32(&o.RX_CH0DATA.Reg, value) +} +func (o *RMT_Type) GetRX_CH0DATA() uint32 { + return volatile.LoadUint32(&o.RX_CH0DATA.Reg) +} + +// RMT.RX_CH1DATA: The read and write data register for CHANNEL$n by apb fifo access. +func (o *RMT_Type) SetRX_CH1DATA(value uint32) { + volatile.StoreUint32(&o.RX_CH1DATA.Reg, value) +} +func (o *RMT_Type) GetRX_CH1DATA() uint32 { + return volatile.LoadUint32(&o.RX_CH1DATA.Reg) +} + +// RMT.RX_CH2DATA: The read and write data register for CHANNEL$n by apb fifo access. +func (o *RMT_Type) SetRX_CH2DATA(value uint32) { + volatile.StoreUint32(&o.RX_CH2DATA.Reg, value) +} +func (o *RMT_Type) GetRX_CH2DATA() uint32 { + return volatile.LoadUint32(&o.RX_CH2DATA.Reg) +} + +// RMT.RX_CH3DATA: The read and write data register for CHANNEL$n by apb fifo access. +func (o *RMT_Type) SetRX_CH3DATA(value uint32) { + volatile.StoreUint32(&o.RX_CH3DATA.Reg, value) +} +func (o *RMT_Type) GetRX_CH3DATA() uint32 { + return volatile.LoadUint32(&o.RX_CH3DATA.Reg) +} + +// RMT.TX_CH0CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetTX_CH0CONF0_TX_START_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_CH0CONF0_TX_START_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_CH0CONF0_MEM_RD_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_CH0CONF0_MEM_RD_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_CH0CONF0_APB_MEM_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_CH0CONF0_APB_MEM_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetTX_CH0CONF0_TX_CONTI_MODE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetTX_CH0CONF0_TX_CONTI_MODE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetTX_CH0CONF0_MEM_TX_WRAP_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetTX_CH0CONF0_MEM_TX_WRAP_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetTX_CH0CONF0_IDLE_OUT_LV_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetTX_CH0CONF0_IDLE_OUT_LV_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetTX_CH0CONF0_IDLE_OUT_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetTX_CH0CONF0_IDLE_OUT_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetTX_CH0CONF0_TX_STOP_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetTX_CH0CONF0_TX_STOP_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetTX_CH0CONF0_DIV_CNT_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetTX_CH0CONF0_DIV_CNT_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetTX_CH0CONF0_MEM_SIZE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0xf0000)|value<<16) +} +func (o *RMT_Type) GetTX_CH0CONF0_MEM_SIZE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0xf0000) >> 16 +} +func (o *RMT_Type) SetTX_CH0CONF0_CARRIER_EFF_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetTX_CH0CONF0_CARRIER_EFF_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetTX_CH0CONF0_CARRIER_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetTX_CH0CONF0_CARRIER_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetTX_CH0CONF0_CARRIER_OUT_LV_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetTX_CH0CONF0_CARRIER_OUT_LV_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetTX_CH0CONF0_AFIFO_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetTX_CH0CONF0_AFIFO_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetTX_CH0CONF0_CONF_UPDATE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetTX_CH0CONF0_CONF_UPDATE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.TX_CH1CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetTX_CH1CONF0_TX_START_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_CH1CONF0_TX_START_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_CH1CONF0_MEM_RD_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_CH1CONF0_MEM_RD_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_CH1CONF0_APB_MEM_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_CH1CONF0_APB_MEM_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetTX_CH1CONF0_TX_CONTI_MODE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetTX_CH1CONF0_TX_CONTI_MODE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetTX_CH1CONF0_MEM_TX_WRAP_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetTX_CH1CONF0_MEM_TX_WRAP_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetTX_CH1CONF0_IDLE_OUT_LV_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetTX_CH1CONF0_IDLE_OUT_LV_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetTX_CH1CONF0_IDLE_OUT_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetTX_CH1CONF0_IDLE_OUT_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetTX_CH1CONF0_TX_STOP_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetTX_CH1CONF0_TX_STOP_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetTX_CH1CONF0_DIV_CNT_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetTX_CH1CONF0_DIV_CNT_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetTX_CH1CONF0_MEM_SIZE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0xf0000)|value<<16) +} +func (o *RMT_Type) GetTX_CH1CONF0_MEM_SIZE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0xf0000) >> 16 +} +func (o *RMT_Type) SetTX_CH1CONF0_CARRIER_EFF_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetTX_CH1CONF0_CARRIER_EFF_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetTX_CH1CONF0_CARRIER_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetTX_CH1CONF0_CARRIER_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetTX_CH1CONF0_CARRIER_OUT_LV_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetTX_CH1CONF0_CARRIER_OUT_LV_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetTX_CH1CONF0_AFIFO_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetTX_CH1CONF0_AFIFO_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetTX_CH1CONF0_CONF_UPDATE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetTX_CH1CONF0_CONF_UPDATE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.TX_CH2CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetTX_CH2CONF0_TX_START_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_CH2CONF0_TX_START_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_CH2CONF0_MEM_RD_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_CH2CONF0_MEM_RD_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_CH2CONF0_APB_MEM_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_CH2CONF0_APB_MEM_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetTX_CH2CONF0_TX_CONTI_MODE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetTX_CH2CONF0_TX_CONTI_MODE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetTX_CH2CONF0_MEM_TX_WRAP_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetTX_CH2CONF0_MEM_TX_WRAP_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetTX_CH2CONF0_IDLE_OUT_LV_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetTX_CH2CONF0_IDLE_OUT_LV_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetTX_CH2CONF0_IDLE_OUT_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetTX_CH2CONF0_IDLE_OUT_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetTX_CH2CONF0_TX_STOP_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetTX_CH2CONF0_TX_STOP_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetTX_CH2CONF0_DIV_CNT_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetTX_CH2CONF0_DIV_CNT_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetTX_CH2CONF0_MEM_SIZE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0xf0000)|value<<16) +} +func (o *RMT_Type) GetTX_CH2CONF0_MEM_SIZE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0xf0000) >> 16 +} +func (o *RMT_Type) SetTX_CH2CONF0_CARRIER_EFF_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetTX_CH2CONF0_CARRIER_EFF_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetTX_CH2CONF0_CARRIER_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetTX_CH2CONF0_CARRIER_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetTX_CH2CONF0_CARRIER_OUT_LV_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetTX_CH2CONF0_CARRIER_OUT_LV_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetTX_CH2CONF0_AFIFO_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetTX_CH2CONF0_AFIFO_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetTX_CH2CONF0_CONF_UPDATE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetTX_CH2CONF0_CONF_UPDATE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.TX_CH3CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetTX_CH3CONF0_TX_START_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_CH3CONF0_TX_START_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_CH3CONF0_MEM_RD_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_CH3CONF0_MEM_RD_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_CH3CONF0_APB_MEM_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_CH3CONF0_APB_MEM_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetTX_CH3CONF0_TX_CONTI_MODE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetTX_CH3CONF0_TX_CONTI_MODE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetTX_CH3CONF0_MEM_TX_WRAP_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetTX_CH3CONF0_MEM_TX_WRAP_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetTX_CH3CONF0_IDLE_OUT_LV_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetTX_CH3CONF0_IDLE_OUT_LV_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetTX_CH3CONF0_IDLE_OUT_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetTX_CH3CONF0_IDLE_OUT_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetTX_CH3CONF0_TX_STOP_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetTX_CH3CONF0_TX_STOP_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetTX_CH3CONF0_DIV_CNT_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetTX_CH3CONF0_DIV_CNT_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetTX_CH3CONF0_MEM_SIZE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0xf0000)|value<<16) +} +func (o *RMT_Type) GetTX_CH3CONF0_MEM_SIZE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0xf0000) >> 16 +} +func (o *RMT_Type) SetTX_CH3CONF0_CARRIER_EFF_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetTX_CH3CONF0_CARRIER_EFF_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetTX_CH3CONF0_CARRIER_EN_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetTX_CH3CONF0_CARRIER_EN_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetTX_CH3CONF0_CARRIER_OUT_LV_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetTX_CH3CONF0_CARRIER_OUT_LV_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetTX_CH3CONF0_AFIFO_RST_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetTX_CH3CONF0_AFIFO_RST_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetTX_CH3CONF0_CONF_UPDATE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetTX_CH3CONF0_CONF_UPDATE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.RX_CH0CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetRX_CH0CONF0_DIV_CNT_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetRX_CH0CONF0_DIV_CNT_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetRX_CH0CONF0_IDLE_THRES_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetRX_CH0CONF0_IDLE_THRES_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetRX_CH0CONF0_MEM_SIZE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetRX_CH0CONF0_MEM_SIZE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetRX_CH0CONF0_CARRIER_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetRX_CH0CONF0_CARRIER_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetRX_CH0CONF0_CARRIER_OUT_LV_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetRX_CH0CONF0_CARRIER_OUT_LV_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.RX_CH0CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetRX_CH0CONF1_RX_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetRX_CH0CONF1_RX_EN_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetRX_CH0CONF1_MEM_WR_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetRX_CH0CONF1_MEM_WR_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetRX_CH0CONF1_APB_MEM_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetRX_CH0CONF1_APB_MEM_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetRX_CH0CONF1_MEM_OWNER_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetRX_CH0CONF1_MEM_OWNER_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetRX_CH0CONF1_RX_FILTER_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetRX_CH0CONF1_RX_FILTER_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetRX_CH0CONF1_RX_FILTER_THRES_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetRX_CH0CONF1_RX_FILTER_THRES_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetRX_CH0CONF1_MEM_RX_WRAP_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetRX_CH0CONF1_MEM_RX_WRAP_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetRX_CH0CONF1_AFIFO_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetRX_CH0CONF1_AFIFO_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetRX_CH0CONF1_CONF_UPDATE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetRX_CH0CONF1_CONF_UPDATE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.RX_CH1CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetRX_CH1CONF0_DIV_CNT_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetRX_CH1CONF0_DIV_CNT_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetRX_CH1CONF0_IDLE_THRES_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetRX_CH1CONF0_IDLE_THRES_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetRX_CH1CONF0_MEM_SIZE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetRX_CH1CONF0_MEM_SIZE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetRX_CH1CONF0_CARRIER_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetRX_CH1CONF0_CARRIER_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetRX_CH1CONF0_CARRIER_OUT_LV_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetRX_CH1CONF0_CARRIER_OUT_LV_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.RX_CH1CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetRX_CH1CONF1_RX_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetRX_CH1CONF1_RX_EN_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetRX_CH1CONF1_MEM_WR_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetRX_CH1CONF1_MEM_WR_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetRX_CH1CONF1_APB_MEM_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetRX_CH1CONF1_APB_MEM_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetRX_CH1CONF1_MEM_OWNER_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetRX_CH1CONF1_MEM_OWNER_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetRX_CH1CONF1_RX_FILTER_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetRX_CH1CONF1_RX_FILTER_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetRX_CH1CONF1_RX_FILTER_THRES_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetRX_CH1CONF1_RX_FILTER_THRES_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetRX_CH1CONF1_MEM_RX_WRAP_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetRX_CH1CONF1_MEM_RX_WRAP_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetRX_CH1CONF1_AFIFO_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetRX_CH1CONF1_AFIFO_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetRX_CH1CONF1_CONF_UPDATE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetRX_CH1CONF1_CONF_UPDATE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.RX_CH2CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetRX_CH2CONF0_DIV_CNT_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetRX_CH2CONF0_DIV_CNT_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetRX_CH2CONF0_IDLE_THRES_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetRX_CH2CONF0_IDLE_THRES_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetRX_CH2CONF0_MEM_SIZE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetRX_CH2CONF0_MEM_SIZE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetRX_CH2CONF0_CARRIER_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetRX_CH2CONF0_CARRIER_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetRX_CH2CONF0_CARRIER_OUT_LV_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetRX_CH2CONF0_CARRIER_OUT_LV_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.RX_CH2CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetRX_CH2CONF1_RX_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetRX_CH2CONF1_RX_EN_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetRX_CH2CONF1_MEM_WR_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetRX_CH2CONF1_MEM_WR_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetRX_CH2CONF1_APB_MEM_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetRX_CH2CONF1_APB_MEM_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetRX_CH2CONF1_MEM_OWNER_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetRX_CH2CONF1_MEM_OWNER_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetRX_CH2CONF1_RX_FILTER_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetRX_CH2CONF1_RX_FILTER_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetRX_CH2CONF1_RX_FILTER_THRES_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetRX_CH2CONF1_RX_FILTER_THRES_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetRX_CH2CONF1_MEM_RX_WRAP_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetRX_CH2CONF1_MEM_RX_WRAP_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetRX_CH2CONF1_AFIFO_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetRX_CH2CONF1_AFIFO_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetRX_CH2CONF1_CONF_UPDATE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetRX_CH2CONF1_CONF_UPDATE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.RX_CH3CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetRX_CH3CONF0_DIV_CNT_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetRX_CH3CONF0_DIV_CNT_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetRX_CH3CONF0_IDLE_THRES_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetRX_CH3CONF0_IDLE_THRES_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetRX_CH3CONF0_MEM_SIZE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetRX_CH3CONF0_MEM_SIZE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetRX_CH3CONF0_CARRIER_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetRX_CH3CONF0_CARRIER_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetRX_CH3CONF0_CARRIER_OUT_LV_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetRX_CH3CONF0_CARRIER_OUT_LV_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.RX_CH3CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetRX_CH3CONF1_RX_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetRX_CH3CONF1_RX_EN_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetRX_CH3CONF1_MEM_WR_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetRX_CH3CONF1_MEM_WR_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetRX_CH3CONF1_APB_MEM_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetRX_CH3CONF1_APB_MEM_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetRX_CH3CONF1_MEM_OWNER_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetRX_CH3CONF1_MEM_OWNER_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetRX_CH3CONF1_RX_FILTER_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetRX_CH3CONF1_RX_FILTER_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetRX_CH3CONF1_RX_FILTER_THRES_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetRX_CH3CONF1_RX_FILTER_THRES_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetRX_CH3CONF1_MEM_RX_WRAP_EN_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetRX_CH3CONF1_MEM_RX_WRAP_EN_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetRX_CH3CONF1_AFIFO_RST_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetRX_CH3CONF1_AFIFO_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetRX_CH3CONF1_CONF_UPDATE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetRX_CH3CONF1_CONF_UPDATE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.TX_CH0STATUS: Channel %s status register +func (o *RMT_Type) SetTX_CH0STATUS_MEM_RADDR_EX_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetTX_CH0STATUS_MEM_RADDR_EX_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetTX_CH0STATUS_APB_MEM_WADDR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetTX_CH0STATUS_APB_MEM_WADDR_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetTX_CH0STATUS_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetTX_CH0STATUS_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetTX_CH0STATUS_MEM_EMPTY_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetTX_CH0STATUS_MEM_EMPTY_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetTX_CH0STATUS_APB_MEM_WR_ERR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetTX_CH0STATUS_APB_MEM_WR_ERR_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x4000000) >> 26 +} + +// RMT.TX_CH1STATUS: Channel %s status register +func (o *RMT_Type) SetTX_CH1STATUS_MEM_RADDR_EX_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetTX_CH1STATUS_MEM_RADDR_EX_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetTX_CH1STATUS_APB_MEM_WADDR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetTX_CH1STATUS_APB_MEM_WADDR_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetTX_CH1STATUS_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetTX_CH1STATUS_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetTX_CH1STATUS_MEM_EMPTY_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetTX_CH1STATUS_MEM_EMPTY_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetTX_CH1STATUS_APB_MEM_WR_ERR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetTX_CH1STATUS_APB_MEM_WR_ERR_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x4000000) >> 26 +} + +// RMT.TX_CH2STATUS: Channel %s status register +func (o *RMT_Type) SetTX_CH2STATUS_MEM_RADDR_EX_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetTX_CH2STATUS_MEM_RADDR_EX_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetTX_CH2STATUS_APB_MEM_WADDR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetTX_CH2STATUS_APB_MEM_WADDR_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetTX_CH2STATUS_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetTX_CH2STATUS_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetTX_CH2STATUS_MEM_EMPTY_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetTX_CH2STATUS_MEM_EMPTY_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetTX_CH2STATUS_APB_MEM_WR_ERR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetTX_CH2STATUS_APB_MEM_WR_ERR_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x4000000) >> 26 +} + +// RMT.TX_CH3STATUS: Channel %s status register +func (o *RMT_Type) SetTX_CH3STATUS_MEM_RADDR_EX_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetTX_CH3STATUS_MEM_RADDR_EX_CH0() uint32 { + return volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetTX_CH3STATUS_APB_MEM_WADDR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetTX_CH3STATUS_APB_MEM_WADDR_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetTX_CH3STATUS_STATE_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetTX_CH3STATUS_STATE_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetTX_CH3STATUS_MEM_EMPTY_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetTX_CH3STATUS_MEM_EMPTY_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetTX_CH3STATUS_APB_MEM_WR_ERR_CH0(value uint32) { + volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetTX_CH3STATUS_APB_MEM_WR_ERR_CH0() uint32 { + return (volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x4000000) >> 26 +} + +// RMT.RX_CH0STATUS: Channel %s status register +func (o *RMT_Type) SetRX_CH0STATUS_MEM_WADDR_EX_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetRX_CH0STATUS_MEM_WADDR_EX_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetRX_CH0STATUS_APB_MEM_RADDR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetRX_CH0STATUS_APB_MEM_RADDR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetRX_CH0STATUS_STATE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetRX_CH0STATUS_STATE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetRX_CH0STATUS_MEM_OWNER_ERR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetRX_CH0STATUS_MEM_OWNER_ERR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetRX_CH0STATUS_MEM_FULL_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetRX_CH0STATUS_MEM_FULL_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetRX_CH0STATUS_APB_MEM_RD_ERR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetRX_CH0STATUS_APB_MEM_RD_ERR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.RX_CH1STATUS: Channel %s status register +func (o *RMT_Type) SetRX_CH1STATUS_MEM_WADDR_EX_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetRX_CH1STATUS_MEM_WADDR_EX_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetRX_CH1STATUS_APB_MEM_RADDR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetRX_CH1STATUS_APB_MEM_RADDR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetRX_CH1STATUS_STATE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetRX_CH1STATUS_STATE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetRX_CH1STATUS_MEM_OWNER_ERR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetRX_CH1STATUS_MEM_OWNER_ERR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetRX_CH1STATUS_MEM_FULL_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetRX_CH1STATUS_MEM_FULL_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetRX_CH1STATUS_APB_MEM_RD_ERR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetRX_CH1STATUS_APB_MEM_RD_ERR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.RX_CH2STATUS: Channel %s status register +func (o *RMT_Type) SetRX_CH2STATUS_MEM_WADDR_EX_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetRX_CH2STATUS_MEM_WADDR_EX_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetRX_CH2STATUS_APB_MEM_RADDR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetRX_CH2STATUS_APB_MEM_RADDR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetRX_CH2STATUS_STATE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetRX_CH2STATUS_STATE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetRX_CH2STATUS_MEM_OWNER_ERR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetRX_CH2STATUS_MEM_OWNER_ERR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetRX_CH2STATUS_MEM_FULL_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetRX_CH2STATUS_MEM_FULL_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetRX_CH2STATUS_APB_MEM_RD_ERR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetRX_CH2STATUS_APB_MEM_RD_ERR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.RX_CH3STATUS: Channel %s status register +func (o *RMT_Type) SetRX_CH3STATUS_MEM_WADDR_EX_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetRX_CH3STATUS_MEM_WADDR_EX_CH4() uint32 { + return volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetRX_CH3STATUS_APB_MEM_RADDR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetRX_CH3STATUS_APB_MEM_RADDR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetRX_CH3STATUS_STATE_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetRX_CH3STATUS_STATE_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetRX_CH3STATUS_MEM_OWNER_ERR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetRX_CH3STATUS_MEM_OWNER_ERR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetRX_CH3STATUS_MEM_FULL_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetRX_CH3STATUS_MEM_FULL_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetRX_CH3STATUS_APB_MEM_RD_ERR_CH4(value uint32) { + volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetRX_CH3STATUS_APB_MEM_RD_ERR_CH4() uint32 { + return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.INT_RAW: Raw interrupt status +func (o *RMT_Type) SetINT_RAW_CH0_TX_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_RAW_CH0_TX_END_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_RAW_CH1_TX_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_RAW_CH1_TX_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_RAW_CH2_TX_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_RAW_CH2_TX_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_RAW_CH3_TX_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetINT_RAW_CH3_TX_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetINT_RAW_TX_CH0_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_RAW_TX_CH0_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_RAW_TX_CH1_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetINT_RAW_TX_CH1_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetINT_RAW_TX_CH2_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_RAW_TX_CH2_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_RAW_TX_CH3_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetINT_RAW_TX_CH3_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetINT_RAW_CH0_TX_THR_EVENT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_RAW_CH0_TX_THR_EVENT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_RAW_CH1_TX_THR_EVENT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *RMT_Type) GetINT_RAW_CH1_TX_THR_EVENT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *RMT_Type) SetINT_RAW_CH2_TX_THR_EVENT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_RAW_CH2_TX_THR_EVENT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_RAW_CH3_TX_THR_EVENT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *RMT_Type) GetINT_RAW_CH3_TX_THR_EVENT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *RMT_Type) SetINT_RAW_CH0_TX_LOOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_RAW_CH0_TX_LOOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_RAW_CH1_TX_LOOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetINT_RAW_CH1_TX_LOOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetINT_RAW_CH2_TX_LOOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetINT_RAW_CH2_TX_LOOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetINT_RAW_CH3_TX_LOOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetINT_RAW_CH3_TX_LOOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *RMT_Type) SetINT_RAW_CH4_RX_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_RAW_CH4_RX_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetINT_RAW_CH5_RX_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetINT_RAW_CH5_RX_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetINT_RAW_CH6_RX_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetINT_RAW_CH6_RX_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetINT_RAW_CH7_RX_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetINT_RAW_CH7_RX_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetINT_RAW_RX_CH4_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetINT_RAW_RX_CH4_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetINT_RAW_RX_CH5_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetINT_RAW_RX_CH5_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetINT_RAW_RX_CH6_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetINT_RAW_RX_CH6_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetINT_RAW_RX_CH7_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetINT_RAW_RX_CH7_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetINT_RAW_CH4_RX_THR_EVENT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_RAW_CH4_RX_THR_EVENT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetINT_RAW_CH5_RX_THR_EVENT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetINT_RAW_CH5_RX_THR_EVENT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetINT_RAW_CH6_RX_THR_EVENT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetINT_RAW_CH6_RX_THR_EVENT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetINT_RAW_CH7_RX_THR_EVENT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetINT_RAW_CH7_RX_THR_EVENT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetINT_RAW_TX_CH3_DMA_ACCESS_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetINT_RAW_TX_CH3_DMA_ACCESS_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetINT_RAW_RX_CH7_DMA_ACCESS_FAIL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetINT_RAW_RX_CH7_DMA_ACCESS_FAIL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} + +// RMT.INT_ST: Masked interrupt status +func (o *RMT_Type) SetINT_ST_CH0_TX_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ST_CH0_TX_END_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ST_CH1_TX_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_ST_CH1_TX_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_ST_CH2_TX_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ST_CH2_TX_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ST_CH3_TX_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetINT_ST_CH3_TX_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetINT_ST_TX_CH0_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ST_TX_CH0_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ST_TX_CH1_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetINT_ST_TX_CH1_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetINT_ST_TX_CH2_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_ST_TX_CH2_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_ST_TX_CH3_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetINT_ST_TX_CH3_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetINT_ST_CH0_TX_THR_EVENT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ST_CH0_TX_THR_EVENT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ST_CH1_TX_THR_EVENT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *RMT_Type) GetINT_ST_CH1_TX_THR_EVENT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *RMT_Type) SetINT_ST_CH2_TX_THR_EVENT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_ST_CH2_TX_THR_EVENT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_ST_CH3_TX_THR_EVENT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *RMT_Type) GetINT_ST_CH3_TX_THR_EVENT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *RMT_Type) SetINT_ST_CH0_TX_LOOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ST_CH0_TX_LOOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_ST_CH1_TX_LOOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetINT_ST_CH1_TX_LOOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetINT_ST_CH2_TX_LOOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetINT_ST_CH2_TX_LOOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetINT_ST_CH3_TX_LOOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetINT_ST_CH3_TX_LOOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *RMT_Type) SetINT_ST_CH4_RX_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_ST_CH4_RX_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetINT_ST_CH5_RX_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetINT_ST_CH5_RX_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetINT_ST_CH6_RX_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetINT_ST_CH6_RX_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetINT_ST_CH7_RX_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetINT_ST_CH7_RX_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetINT_ST_RX_CH4_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetINT_ST_RX_CH4_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetINT_ST_RX_CH5_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetINT_ST_RX_CH5_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetINT_ST_RX_CH6_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetINT_ST_RX_CH6_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetINT_ST_RX_CH7_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetINT_ST_RX_CH7_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetINT_ST_CH4_RX_THR_EVENT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_ST_CH4_RX_THR_EVENT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetINT_ST_CH5_RX_THR_EVENT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetINT_ST_CH5_RX_THR_EVENT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetINT_ST_CH6_RX_THR_EVENT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetINT_ST_CH6_RX_THR_EVENT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetINT_ST_CH7_RX_THR_EVENT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetINT_ST_CH7_RX_THR_EVENT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetINT_ST_TX_CH3_DMA_ACCESS_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetINT_ST_TX_CH3_DMA_ACCESS_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetINT_ST_RX_CH7_DMA_ACCESS_FAIL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetINT_ST_RX_CH7_DMA_ACCESS_FAIL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} + +// RMT.INT_ENA: Interrupt enable bits +func (o *RMT_Type) SetINT_ENA_CH0_TX_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ENA_CH0_TX_END_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ENA_CH1_TX_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_ENA_CH1_TX_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_ENA_CH2_TX_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ENA_CH2_TX_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ENA_CH3_TX_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetINT_ENA_CH3_TX_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetINT_ENA_TX_CH0_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ENA_TX_CH0_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ENA_TX_CH1_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetINT_ENA_TX_CH1_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetINT_ENA_TX_CH2_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_ENA_TX_CH2_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_ENA_TX_CH3_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetINT_ENA_TX_CH3_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetINT_ENA_CH0_TX_THR_EVENT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ENA_CH0_TX_THR_EVENT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ENA_CH1_TX_THR_EVENT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *RMT_Type) GetINT_ENA_CH1_TX_THR_EVENT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *RMT_Type) SetINT_ENA_CH2_TX_THR_EVENT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_ENA_CH2_TX_THR_EVENT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_ENA_CH3_TX_THR_EVENT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *RMT_Type) GetINT_ENA_CH3_TX_THR_EVENT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *RMT_Type) SetINT_ENA_CH0_TX_LOOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ENA_CH0_TX_LOOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_ENA_CH1_TX_LOOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetINT_ENA_CH1_TX_LOOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetINT_ENA_CH2_TX_LOOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetINT_ENA_CH2_TX_LOOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetINT_ENA_CH3_TX_LOOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetINT_ENA_CH3_TX_LOOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *RMT_Type) SetINT_ENA_CH4_RX_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_ENA_CH4_RX_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetINT_ENA_CH5_RX_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetINT_ENA_CH5_RX_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetINT_ENA_CH6_RX_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetINT_ENA_CH6_RX_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetINT_ENA_CH7_RX_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetINT_ENA_CH7_RX_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetINT_ENA_CH4_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetINT_ENA_CH4_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetINT_ENA_CH5_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetINT_ENA_CH5_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetINT_ENA_CH6_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetINT_ENA_CH6_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetINT_ENA_CH7_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetINT_ENA_CH7_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetINT_ENA_CH4_RX_THR_EVENT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_ENA_CH4_RX_THR_EVENT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetINT_ENA_CH5_RX_THR_EVENT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetINT_ENA_CH5_RX_THR_EVENT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetINT_ENA_CH6_RX_THR_EVENT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetINT_ENA_CH6_RX_THR_EVENT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetINT_ENA_CH7_RX_THR_EVENT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetINT_ENA_CH7_RX_THR_EVENT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetINT_ENA_TX_CH3_DMA_ACCESS_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetINT_ENA_TX_CH3_DMA_ACCESS_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetINT_ENA_RX_CH7_DMA_ACCESS_FAIL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetINT_ENA_RX_CH7_DMA_ACCESS_FAIL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} + +// RMT.INT_CLR: Interrupt clear bits +func (o *RMT_Type) SetINT_CLR_CH0_TX_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_CLR_CH0_TX_END_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_CLR_CH1_TX_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_CLR_CH1_TX_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_CLR_CH2_TX_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_CLR_CH2_TX_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_CLR_CH3_TX_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetINT_CLR_CH3_TX_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetINT_CLR_TX_CH0_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_CLR_TX_CH0_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_CLR_TX_CH1_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetINT_CLR_TX_CH1_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetINT_CLR_TX_CH2_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetINT_CLR_TX_CH2_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetINT_CLR_TX_CH3_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetINT_CLR_TX_CH3_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetINT_CLR_CH0_TX_THR_EVENT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_CLR_CH0_TX_THR_EVENT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_CLR_CH1_TX_THR_EVENT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *RMT_Type) GetINT_CLR_CH1_TX_THR_EVENT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *RMT_Type) SetINT_CLR_CH2_TX_THR_EVENT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *RMT_Type) GetINT_CLR_CH2_TX_THR_EVENT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *RMT_Type) SetINT_CLR_CH3_TX_THR_EVENT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *RMT_Type) GetINT_CLR_CH3_TX_THR_EVENT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *RMT_Type) SetINT_CLR_CH0_TX_LOOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_CLR_CH0_TX_LOOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_CLR_CH1_TX_LOOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetINT_CLR_CH1_TX_LOOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetINT_CLR_CH2_TX_LOOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetINT_CLR_CH2_TX_LOOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetINT_CLR_CH3_TX_LOOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetINT_CLR_CH3_TX_LOOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *RMT_Type) SetINT_CLR_CH4_RX_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_CLR_CH4_RX_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetINT_CLR_CH5_RX_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetINT_CLR_CH5_RX_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetINT_CLR_CH6_RX_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetINT_CLR_CH6_RX_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetINT_CLR_CH7_RX_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetINT_CLR_CH7_RX_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetINT_CLR_RX_CH4_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetINT_CLR_RX_CH4_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetINT_CLR_RX_CH5_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetINT_CLR_RX_CH5_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetINT_CLR_RX_CH6_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetINT_CLR_RX_CH6_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetINT_CLR_RX_CH7_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetINT_CLR_RX_CH7_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetINT_CLR_CH4_RX_THR_EVENT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_CLR_CH4_RX_THR_EVENT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetINT_CLR_CH5_RX_THR_EVENT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetINT_CLR_CH5_RX_THR_EVENT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetINT_CLR_CH6_RX_THR_EVENT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetINT_CLR_CH6_RX_THR_EVENT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetINT_CLR_CH7_RX_THR_EVENT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetINT_CLR_CH7_RX_THR_EVENT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetINT_CLR_TX_CH3_DMA_ACCESS_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetINT_CLR_TX_CH3_DMA_ACCESS_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetINT_CLR_RX_CH7_DMA_ACCESS_FAIL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetINT_CLR_RX_CH7_DMA_ACCESS_FAIL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} + +// RMT.CH0CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_LOW_CH(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_LOW_CH() uint32 { + return volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_HIGH_CH(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_HIGH_CH() uint32 { + return (volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_LOW_CH(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_LOW_CH() uint32 { + return volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_HIGH_CH(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_HIGH_CH() uint32 { + return (volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH2CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_LOW_CH(value uint32) { + volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_LOW_CH() uint32 { + return volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_HIGH_CH(value uint32) { + volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_HIGH_CH() uint32 { + return (volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH3CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_LOW_CH(value uint32) { + volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_LOW_CH() uint32 { + return volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_HIGH_CH(value uint32) { + volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_HIGH_CH() uint32 { + return (volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES_CH(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES_CH() uint32 { + return volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES_CH(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES_CH() uint32 { + return volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH2_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES_CH(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES_CH() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH3_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES_CH(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES_CH() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH0_TX_LIM_TX_LIM_CH(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LIM_CH() uint32 { + return volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_COUNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_COUNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_STOP_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_STOP_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH1_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH1_TX_LIM_TX_LIM_CH(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LIM_CH() uint32 { + return volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_COUNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_COUNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_STOP_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_STOP_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH2_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH2_TX_LIM_TX_LIM_CH(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LIM_CH() uint32 { + return volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH2_TX_LIM_TX_LOOP_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LOOP_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH2_TX_LIM_TX_LOOP_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LOOP_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH2_TX_LIM_LOOP_COUNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH2_TX_LIM_LOOP_COUNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH2_TX_LIM_LOOP_STOP_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH2_TX_LIM_LOOP_STOP_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH3_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH3_TX_LIM_TX_LIM_CH(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LIM_CH() uint32 { + return volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH3_TX_LIM_TX_LOOP_NUM_CH(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LOOP_NUM_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH3_TX_LIM_TX_LOOP_CNT_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LOOP_CNT_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH3_TX_LIM_LOOP_COUNT_RESET_CH(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH3_TX_LIM_LOOP_COUNT_RESET_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH3_TX_LIM_LOOP_STOP_EN_CH(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH3_TX_LIM_LOOP_STOP_EN_CH() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH0_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH0_RX_LIM_RX_LIM_CH4(value uint32) { + volatile.StoreUint32(&o.CH0_RX_LIM.Reg, volatile.LoadUint32(&o.CH0_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_RX_LIM_RX_LIM_CH4() uint32 { + return volatile.LoadUint32(&o.CH0_RX_LIM.Reg) & 0x1ff +} + +// RMT.CH1_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH1_RX_LIM_RX_LIM_CH4(value uint32) { + volatile.StoreUint32(&o.CH1_RX_LIM.Reg, volatile.LoadUint32(&o.CH1_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_RX_LIM_RX_LIM_CH4() uint32 { + return volatile.LoadUint32(&o.CH1_RX_LIM.Reg) & 0x1ff +} + +// RMT.CH2_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH2_RX_LIM_RX_LIM_CH4(value uint32) { + volatile.StoreUint32(&o.CH2_RX_LIM.Reg, volatile.LoadUint32(&o.CH2_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2_RX_LIM_RX_LIM_CH4() uint32 { + return volatile.LoadUint32(&o.CH2_RX_LIM.Reg) & 0x1ff +} + +// RMT.CH3_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH3_RX_LIM_RX_LIM_CH4(value uint32) { + volatile.StoreUint32(&o.CH3_RX_LIM.Reg, volatile.LoadUint32(&o.CH3_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3_RX_LIM_RX_LIM_CH4() uint32 { + return volatile.LoadUint32(&o.CH3_RX_LIM.Reg) & 0x1ff +} + +// RMT.SYS_CONF: RMT apb configuration register +func (o *RMT_Type) SetSYS_CONF_APB_FIFO_MASK(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetSYS_CONF_APB_FIFO_MASK() uint32 { + return volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetSYS_CONF_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xff0)|value<<4) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xff0) >> 4 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3f000)|value<<12) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3f000) >> 12 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xfc0000)|value<<18) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xfc0000) >> 18 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3000000)|value<<24) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3000000) >> 24 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetSYS_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetSYS_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x80000000) >> 31 +} + +// RMT.TX_SIM: RMT TX synchronous register +func (o *RMT_Type) SetTX_SIM_CH0(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_SIM_CH0() uint32 { + return volatile.LoadUint32(&o.TX_SIM.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_SIM_CH1(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_SIM_CH1() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_SIM_CH2(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_SIM_CH2() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetTX_SIM_CH3(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetTX_SIM_CH3() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetTX_SIM_EN(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetTX_SIM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x10) >> 4 +} + +// RMT.REF_CNT_RST: RMT clock divider reset register +func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH0(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH0() uint32 { + return volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x1 +} +func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH1(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH1() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH2(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH2() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH3(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH3() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH4(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH4() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH5(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH5() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH6(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH6() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH7(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH7() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x80) >> 7 +} + +// RMT.DATE: RMT version register +func (o *RMT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RMT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// RSA (Rivest Shamir Adleman) Accelerator +type RSA_Type struct { + M_MEM [4]volatile.Register32 // 0x0 + _ [496]byte + Z_MEM [4]volatile.Register32 // 0x200 + _ [496]byte + Y_MEM [4]volatile.Register32 // 0x400 + _ [496]byte + X_MEM [4]volatile.Register32 // 0x600 + _ [496]byte + M_PRIME volatile.Register32 // 0x800 + MODE volatile.Register32 // 0x804 + QUERY_CLEAN volatile.Register32 // 0x808 + SET_START_MODEXP volatile.Register32 // 0x80C + SET_START_MODMULT volatile.Register32 // 0x810 + SET_START_MULT volatile.Register32 // 0x814 + QUERY_IDLE volatile.Register32 // 0x818 + INT_CLR volatile.Register32 // 0x81C + CONSTANT_TIME volatile.Register32 // 0x820 + SEARCH_ENABLE volatile.Register32 // 0x824 + SEARCH_POS volatile.Register32 // 0x828 + INT_ENA volatile.Register32 // 0x82C + DATE volatile.Register32 // 0x830 +} + +// RSA.M_PRIME: Represents M’ +func (o *RSA_Type) SetM_PRIME(value uint32) { + volatile.StoreUint32(&o.M_PRIME.Reg, value) +} +func (o *RSA_Type) GetM_PRIME() uint32 { + return volatile.LoadUint32(&o.M_PRIME.Reg) +} + +// RSA.MODE: Configures RSA length +func (o *RSA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7f)|value) +} +func (o *RSA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7f +} + +// RSA.QUERY_CLEAN: RSA clean register +func (o *RSA_Type) SetQUERY_CLEAN(value uint32) { + volatile.StoreUint32(&o.QUERY_CLEAN.Reg, volatile.LoadUint32(&o.QUERY_CLEAN.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetQUERY_CLEAN() uint32 { + return volatile.LoadUint32(&o.QUERY_CLEAN.Reg) & 0x1 +} + +// RSA.SET_START_MODEXP: Starts modular exponentiation +func (o *RSA_Type) SetSET_START_MODEXP(value uint32) { + volatile.StoreUint32(&o.SET_START_MODEXP.Reg, volatile.LoadUint32(&o.SET_START_MODEXP.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MODEXP() uint32 { + return volatile.LoadUint32(&o.SET_START_MODEXP.Reg) & 0x1 +} + +// RSA.SET_START_MODMULT: Starts modular multiplication +func (o *RSA_Type) SetSET_START_MODMULT(value uint32) { + volatile.StoreUint32(&o.SET_START_MODMULT.Reg, volatile.LoadUint32(&o.SET_START_MODMULT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MODMULT() uint32 { + return volatile.LoadUint32(&o.SET_START_MODMULT.Reg) & 0x1 +} + +// RSA.SET_START_MULT: Starts multiplication +func (o *RSA_Type) SetSET_START_MULT(value uint32) { + volatile.StoreUint32(&o.SET_START_MULT.Reg, volatile.LoadUint32(&o.SET_START_MULT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSET_START_MULT() uint32 { + return volatile.LoadUint32(&o.SET_START_MULT.Reg) & 0x1 +} + +// RSA.QUERY_IDLE: Represents the RSA status +func (o *RSA_Type) SetQUERY_IDLE(value uint32) { + volatile.StoreUint32(&o.QUERY_IDLE.Reg, volatile.LoadUint32(&o.QUERY_IDLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetQUERY_IDLE() uint32 { + return volatile.LoadUint32(&o.QUERY_IDLE.Reg) & 0x1 +} + +// RSA.INT_CLR: Clears RSA interrupt +func (o *RSA_Type) SetINT_CLR_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINT_CLR_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} + +// RSA.CONSTANT_TIME: Configures the constant_time option +func (o *RSA_Type) SetCONSTANT_TIME(value uint32) { + volatile.StoreUint32(&o.CONSTANT_TIME.Reg, volatile.LoadUint32(&o.CONSTANT_TIME.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCONSTANT_TIME() uint32 { + return volatile.LoadUint32(&o.CONSTANT_TIME.Reg) & 0x1 +} + +// RSA.SEARCH_ENABLE: Configures the search option +func (o *RSA_Type) SetSEARCH_ENABLE(value uint32) { + volatile.StoreUint32(&o.SEARCH_ENABLE.Reg, volatile.LoadUint32(&o.SEARCH_ENABLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSEARCH_ENABLE() uint32 { + return volatile.LoadUint32(&o.SEARCH_ENABLE.Reg) & 0x1 +} + +// RSA.SEARCH_POS: Configures the search position +func (o *RSA_Type) SetSEARCH_POS(value uint32) { + volatile.StoreUint32(&o.SEARCH_POS.Reg, volatile.LoadUint32(&o.SEARCH_POS.Reg)&^(0xfff)|value) +} +func (o *RSA_Type) GetSEARCH_POS() uint32 { + return volatile.LoadUint32(&o.SEARCH_POS.Reg) & 0xfff +} + +// RSA.INT_ENA: Enables the RSA interrupt +func (o *RSA_Type) SetINT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// RSA.DATE: Version control register +func (o *RSA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *RSA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Low-power Analog to Digital Converter +type RTCADC_Type struct { + READER1_CTRL volatile.Register32 // 0x0 + READER1_STATUS volatile.Register32 // 0x4 + MEAS1_CTRL1 volatile.Register32 // 0x8 + MEAS1_CTRL2 volatile.Register32 // 0xC + MEAS1_MUX volatile.Register32 // 0x10 + ATTEN1 volatile.Register32 // 0x14 + AMP_CTRL1 volatile.Register32 // 0x18 + AMP_CTRL2 volatile.Register32 // 0x1C + AMP_CTRL3 volatile.Register32 // 0x20 + READER2_CTRL volatile.Register32 // 0x24 + READER2_STATUS volatile.Register32 // 0x28 + MEAS2_CTRL1 volatile.Register32 // 0x2C + MEAS2_CTRL2 volatile.Register32 // 0x30 + MEAS2_MUX volatile.Register32 // 0x34 + ATTEN2 volatile.Register32 // 0x38 + FORCE_WPD_SAR volatile.Register32 // 0x3C + MEAS_STATUS volatile.Register32 // 0x40 + REG_CLKEN volatile.Register32 // 0x44 + COCPU_INT_RAW volatile.Register32 // 0x48 + INT_ENA volatile.Register32 // 0x4C + INT_ST volatile.Register32 // 0x50 + INT_CLR volatile.Register32 // 0x54 + INT_ENA_W1TS volatile.Register32 // 0x58 + INT_ENA_W1TC volatile.Register32 // 0x5C + WAKEUP1 volatile.Register32 // 0x60 + WAKEUP2 volatile.Register32 // 0x64 + WAKEUP_SEL volatile.Register32 // 0x68 + SAR1_HW_WAKEUP volatile.Register32 // 0x6C + SAR2_HW_WAKEUP volatile.Register32 // 0x70 + RND_ECO_LOW volatile.Register32 // 0x74 + RND_ECO_HIGH volatile.Register32 // 0x78 + RND_ECO_CS volatile.Register32 // 0x7C +} + +// RTCADC.READER1_CTRL: Control the read operation of ADC1. +func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0xff)|value) +} +func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0xff +} +func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0x40000) >> 18 +} +func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_SAMPLE_NUM(value uint32) { + volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0x7f80000)|value<<19) +} +func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_SAMPLE_NUM() uint32 { + return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0x7f80000) >> 19 +} +func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_DATA_INV(value uint32) { + volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_INT_EN(value uint32) { + volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_INT_EN() uint32 { + return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_EN_PAD_FORCE_ENABLE(value uint32) { + volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_EN_PAD_FORCE_ENABLE() uint32 { + return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0xc0000000) >> 30 +} + +// RTCADC.READER1_STATUS: N/A +func (o *RTCADC_Type) SetREADER1_STATUS(value uint32) { + volatile.StoreUint32(&o.READER1_STATUS.Reg, value) +} +func (o *RTCADC_Type) GetREADER1_STATUS() uint32 { + return volatile.LoadUint32(&o.READER1_STATUS.Reg) +} + +// RTCADC.MEAS1_CTRL1: N/A +func (o *RTCADC_Type) SetMEAS1_CTRL1_FORCE_XPD_AMP(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.MEAS1_CTRL1.Reg)&^(0x3000000)|value<<24) +} +func (o *RTCADC_Type) GetMEAS1_CTRL1_FORCE_XPD_AMP() uint32 { + return (volatile.LoadUint32(&o.MEAS1_CTRL1.Reg) & 0x3000000) >> 24 +} +func (o *RTCADC_Type) SetMEAS1_CTRL1_AMP_RST_FB_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.MEAS1_CTRL1.Reg)&^(0xc000000)|value<<26) +} +func (o *RTCADC_Type) GetMEAS1_CTRL1_AMP_RST_FB_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS1_CTRL1.Reg) & 0xc000000) >> 26 +} +func (o *RTCADC_Type) SetMEAS1_CTRL1_AMP_SHORT_REF_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.MEAS1_CTRL1.Reg)&^(0x30000000)|value<<28) +} +func (o *RTCADC_Type) GetMEAS1_CTRL1_AMP_SHORT_REF_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS1_CTRL1.Reg) & 0x30000000) >> 28 +} +func (o *RTCADC_Type) SetMEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.MEAS1_CTRL1.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTCADC_Type) GetMEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS1_CTRL1.Reg) & 0xc0000000) >> 30 +} + +// RTCADC.MEAS1_CTRL2: ADC1 configuration registers. +func (o *RTCADC_Type) SetMEAS1_CTRL2_MEAS1_DATA_SAR(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0xffff)|value) +} +func (o *RTCADC_Type) GetMEAS1_CTRL2_MEAS1_DATA_SAR() uint32 { + return volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0xffff +} +func (o *RTCADC_Type) SetMEAS1_CTRL2_MEAS1_DONE_SAR(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *RTCADC_Type) GetMEAS1_CTRL2_MEAS1_DONE_SAR() uint32 { + return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x10000) >> 16 +} +func (o *RTCADC_Type) SetMEAS1_CTRL2_MEAS1_START_SAR(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x20000)|value<<17) +} +func (o *RTCADC_Type) GetMEAS1_CTRL2_MEAS1_START_SAR() uint32 { + return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x20000) >> 17 +} +func (o *RTCADC_Type) SetMEAS1_CTRL2_MEAS1_START_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x40000)|value<<18) +} +func (o *RTCADC_Type) GetMEAS1_CTRL2_MEAS1_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x40000) >> 18 +} +func (o *RTCADC_Type) SetMEAS1_CTRL2_SAR1_EN_PAD(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x7ff80000)|value<<19) +} +func (o *RTCADC_Type) GetMEAS1_CTRL2_SAR1_EN_PAD() uint32 { + return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x7ff80000) >> 19 +} +func (o *RTCADC_Type) SetMEAS1_CTRL2_SAR1_EN_PAD_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTCADC_Type) GetMEAS1_CTRL2_SAR1_EN_PAD_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x80000000) >> 31 +} + +// RTCADC.MEAS1_MUX: SAR ADC1 MUX register. +func (o *RTCADC_Type) SetMEAS1_MUX_SAR1_DIG_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS1_MUX.Reg, volatile.LoadUint32(&o.MEAS1_MUX.Reg)&^(0x80000000)|value<<31) +} +func (o *RTCADC_Type) GetMEAS1_MUX_SAR1_DIG_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS1_MUX.Reg) & 0x80000000) >> 31 +} + +// RTCADC.ATTEN1: ADC1 attenuation registers. +func (o *RTCADC_Type) SetATTEN1(value uint32) { + volatile.StoreUint32(&o.ATTEN1.Reg, value) +} +func (o *RTCADC_Type) GetATTEN1() uint32 { + return volatile.LoadUint32(&o.ATTEN1.Reg) +} + +// RTCADC.AMP_CTRL1: N/A +func (o *RTCADC_Type) SetAMP_CTRL1_SAR_AMP_WAIT1(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL1.Reg, volatile.LoadUint32(&o.AMP_CTRL1.Reg)&^(0xffff)|value) +} +func (o *RTCADC_Type) GetAMP_CTRL1_SAR_AMP_WAIT1() uint32 { + return volatile.LoadUint32(&o.AMP_CTRL1.Reg) & 0xffff +} +func (o *RTCADC_Type) SetAMP_CTRL1_SAR_AMP_WAIT2(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL1.Reg, volatile.LoadUint32(&o.AMP_CTRL1.Reg)&^(0xffff0000)|value<<16) +} +func (o *RTCADC_Type) GetAMP_CTRL1_SAR_AMP_WAIT2() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL1.Reg) & 0xffff0000) >> 16 +} + +// RTCADC.AMP_CTRL2: N/A +func (o *RTCADC_Type) SetAMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetAMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE() uint32 { + return volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x1 +} +func (o *RTCADC_Type) SetAMP_CTRL2_XPD_SAR_AMP_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x2)|value<<1) +} +func (o *RTCADC_Type) GetAMP_CTRL2_XPD_SAR_AMP_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x2) >> 1 +} +func (o *RTCADC_Type) SetAMP_CTRL2_AMP_RST_FB_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x4)|value<<2) +} +func (o *RTCADC_Type) GetAMP_CTRL2_AMP_RST_FB_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x4) >> 2 +} +func (o *RTCADC_Type) SetAMP_CTRL2_AMP_SHORT_REF_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x8)|value<<3) +} +func (o *RTCADC_Type) GetAMP_CTRL2_AMP_SHORT_REF_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x8) >> 3 +} +func (o *RTCADC_Type) SetAMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x10)|value<<4) +} +func (o *RTCADC_Type) GetAMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x10) >> 4 +} +func (o *RTCADC_Type) SetAMP_CTRL2_XPD_SAR_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x20)|value<<5) +} +func (o *RTCADC_Type) GetAMP_CTRL2_XPD_SAR_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x20) >> 5 +} +func (o *RTCADC_Type) SetAMP_CTRL2_SAR_RSTB_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x40)|value<<6) +} +func (o *RTCADC_Type) GetAMP_CTRL2_SAR_RSTB_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x40) >> 6 +} +func (o *RTCADC_Type) SetAMP_CTRL2_SAR_AMP_WAIT3(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0xffff0000)|value<<16) +} +func (o *RTCADC_Type) GetAMP_CTRL2_SAR_AMP_WAIT3() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0xffff0000) >> 16 +} + +// RTCADC.AMP_CTRL3: N/A +func (o *RTCADC_Type) SetAMP_CTRL3_SAR1_DAC_XPD_FSM(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf)|value) +} +func (o *RTCADC_Type) GetAMP_CTRL3_SAR1_DAC_XPD_FSM() uint32 { + return volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf +} +func (o *RTCADC_Type) SetAMP_CTRL3_XPD_SAR_AMP_FSM(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf0)|value<<4) +} +func (o *RTCADC_Type) GetAMP_CTRL3_XPD_SAR_AMP_FSM() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf0) >> 4 +} +func (o *RTCADC_Type) SetAMP_CTRL3_AMP_RST_FB_FSM(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf00)|value<<8) +} +func (o *RTCADC_Type) GetAMP_CTRL3_AMP_RST_FB_FSM() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf00) >> 8 +} +func (o *RTCADC_Type) SetAMP_CTRL3_AMP_SHORT_REF_FSM(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf000)|value<<12) +} +func (o *RTCADC_Type) GetAMP_CTRL3_AMP_SHORT_REF_FSM() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf000) >> 12 +} +func (o *RTCADC_Type) SetAMP_CTRL3_AMP_SHORT_REF_GND_FSM(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf0000)|value<<16) +} +func (o *RTCADC_Type) GetAMP_CTRL3_AMP_SHORT_REF_GND_FSM() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf0000) >> 16 +} +func (o *RTCADC_Type) SetAMP_CTRL3_XPD_SAR_FSM(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf00000)|value<<20) +} +func (o *RTCADC_Type) GetAMP_CTRL3_XPD_SAR_FSM() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf00000) >> 20 +} +func (o *RTCADC_Type) SetAMP_CTRL3_SAR_RSTB_FSM(value uint32) { + volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf000000)|value<<24) +} +func (o *RTCADC_Type) GetAMP_CTRL3_SAR_RSTB_FSM() uint32 { + return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf000000) >> 24 +} + +// RTCADC.READER2_CTRL: Control the read operation of ADC2. +func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0xff)|value) +} +func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0xff +} +func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x30000)|value<<16) +} +func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x30000) >> 16 +} +func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x40000) >> 18 +} +func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_SAMPLE_NUM(value uint32) { + volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x7f80000)|value<<19) +} +func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_SAMPLE_NUM() uint32 { + return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x7f80000) >> 19 +} +func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_EN_PAD_FORCE_ENABLE(value uint32) { + volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x18000000)|value<<27) +} +func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_EN_PAD_FORCE_ENABLE() uint32 { + return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x18000000) >> 27 +} +func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_DATA_INV(value uint32) { + volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_INT_EN(value uint32) { + volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_INT_EN() uint32 { + return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x40000000) >> 30 +} + +// RTCADC.READER2_STATUS: N/A +func (o *RTCADC_Type) SetREADER2_STATUS(value uint32) { + volatile.StoreUint32(&o.READER2_STATUS.Reg, value) +} +func (o *RTCADC_Type) GetREADER2_STATUS() uint32 { + return volatile.LoadUint32(&o.READER2_STATUS.Reg) +} + +// RTCADC.MEAS2_CTRL1: ADC2 configuration registers. +func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_CNTL_STATE(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0x7)|value) +} +func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_CNTL_STATE() uint32 { + return volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0x7 +} +func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_PWDET_CAL_EN(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0x8)|value<<3) +} +func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_PWDET_CAL_EN() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0x8) >> 3 +} +func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_PKDET_CAL_EN(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0x10)|value<<4) +} +func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_PKDET_CAL_EN() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0x10) >> 4 +} +func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_EN_TEST(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0x20)|value<<5) +} +func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_EN_TEST() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0x20) >> 5 +} +func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_RSTB_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0xc0)|value<<6) +} +func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_RSTB_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0xc0) >> 6 +} +func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0xff00)|value<<8) +} +func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0xff00) >> 8 +} +func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0xff0000)|value<<16) +} +func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0xff0000) >> 16 +} +func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0xff000000)|value<<24) +} +func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_XPD_WAIT() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0xff000000) >> 24 +} + +// RTCADC.MEAS2_CTRL2: ADC2 configuration registers. +func (o *RTCADC_Type) SetMEAS2_CTRL2_MEAS2_DATA_SAR(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0xffff)|value) +} +func (o *RTCADC_Type) GetMEAS2_CTRL2_MEAS2_DATA_SAR() uint32 { + return volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0xffff +} +func (o *RTCADC_Type) SetMEAS2_CTRL2_MEAS2_DONE_SAR(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *RTCADC_Type) GetMEAS2_CTRL2_MEAS2_DONE_SAR() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x10000) >> 16 +} +func (o *RTCADC_Type) SetMEAS2_CTRL2_MEAS2_START_SAR(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x20000)|value<<17) +} +func (o *RTCADC_Type) GetMEAS2_CTRL2_MEAS2_START_SAR() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x20000) >> 17 +} +func (o *RTCADC_Type) SetMEAS2_CTRL2_MEAS2_START_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x40000)|value<<18) +} +func (o *RTCADC_Type) GetMEAS2_CTRL2_MEAS2_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x40000) >> 18 +} +func (o *RTCADC_Type) SetMEAS2_CTRL2_SAR2_EN_PAD(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x7ff80000)|value<<19) +} +func (o *RTCADC_Type) GetMEAS2_CTRL2_SAR2_EN_PAD() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x7ff80000) >> 19 +} +func (o *RTCADC_Type) SetMEAS2_CTRL2_SAR2_EN_PAD_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTCADC_Type) GetMEAS2_CTRL2_SAR2_EN_PAD_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x80000000) >> 31 +} + +// RTCADC.MEAS2_MUX: SAR ADC2 MUX register. +func (o *RTCADC_Type) SetMEAS2_MUX_SAR2_PWDET_CCT(value uint32) { + volatile.StoreUint32(&o.MEAS2_MUX.Reg, volatile.LoadUint32(&o.MEAS2_MUX.Reg)&^(0x70000000)|value<<28) +} +func (o *RTCADC_Type) GetMEAS2_MUX_SAR2_PWDET_CCT() uint32 { + return (volatile.LoadUint32(&o.MEAS2_MUX.Reg) & 0x70000000) >> 28 +} +func (o *RTCADC_Type) SetMEAS2_MUX_SAR2_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.MEAS2_MUX.Reg, volatile.LoadUint32(&o.MEAS2_MUX.Reg)&^(0x80000000)|value<<31) +} +func (o *RTCADC_Type) GetMEAS2_MUX_SAR2_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.MEAS2_MUX.Reg) & 0x80000000) >> 31 +} + +// RTCADC.ATTEN2: ADC1 attenuation registers. +func (o *RTCADC_Type) SetATTEN2(value uint32) { + volatile.StoreUint32(&o.ATTEN2.Reg, value) +} +func (o *RTCADC_Type) GetATTEN2() uint32 { + return volatile.LoadUint32(&o.ATTEN2.Reg) +} + +// RTCADC.FORCE_WPD_SAR: In sleep, force to use rtc to control ADC +func (o *RTCADC_Type) SetFORCE_WPD_SAR_FORCE_XPD_SAR1(value uint32) { + volatile.StoreUint32(&o.FORCE_WPD_SAR.Reg, volatile.LoadUint32(&o.FORCE_WPD_SAR.Reg)&^(0x3)|value) +} +func (o *RTCADC_Type) GetFORCE_WPD_SAR_FORCE_XPD_SAR1() uint32 { + return volatile.LoadUint32(&o.FORCE_WPD_SAR.Reg) & 0x3 +} +func (o *RTCADC_Type) SetFORCE_WPD_SAR_FORCE_XPD_SAR2(value uint32) { + volatile.StoreUint32(&o.FORCE_WPD_SAR.Reg, volatile.LoadUint32(&o.FORCE_WPD_SAR.Reg)&^(0xc)|value<<2) +} +func (o *RTCADC_Type) GetFORCE_WPD_SAR_FORCE_XPD_SAR2() uint32 { + return (volatile.LoadUint32(&o.FORCE_WPD_SAR.Reg) & 0xc) >> 2 +} + +// RTCADC.MEAS_STATUS: N/A +func (o *RTCADC_Type) SetMEAS_STATUS_SARADC_MEAS_STATUS(value uint32) { + volatile.StoreUint32(&o.MEAS_STATUS.Reg, volatile.LoadUint32(&o.MEAS_STATUS.Reg)&^(0xff)|value) +} +func (o *RTCADC_Type) GetMEAS_STATUS_SARADC_MEAS_STATUS() uint32 { + return volatile.LoadUint32(&o.MEAS_STATUS.Reg) & 0xff +} + +// RTCADC.REG_CLKEN: N/A +func (o *RTCADC_Type) SetREG_CLKEN_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REG_CLKEN.Reg, volatile.LoadUint32(&o.REG_CLKEN.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetREG_CLKEN_CLK_EN() uint32 { + return volatile.LoadUint32(&o.REG_CLKEN.Reg) & 0x1 +} + +// RTCADC.COCPU_INT_RAW: Interrupt raw registers. +func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC1_INT_RAW() uint32 { + return volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x1 +} +func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC1_ERROR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC1_ERROR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC2_ERROR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC2_ERROR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC1_WAKE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC1_WAKE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC2_WAKE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC2_WAKE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x20) >> 5 +} + +// RTCADC.INT_ENA: Interrupt enable registers. +func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC1_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC1_ERROR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC1_ERROR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC2_ERROR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC2_ERROR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC1_WAKE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC1_WAKE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC2_WAKE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC2_WAKE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} + +// RTCADC.INT_ST: Interrupt status registers. +func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC1_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC1_ERROR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC1_ERROR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC2_ERROR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC2_ERROR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC1_WAKE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC1_WAKE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC2_WAKE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC2_WAKE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} + +// RTCADC.INT_CLR: Interrupt clear registers. +func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC1_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC1_ERROR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC1_ERROR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC2_ERROR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC2_ERROR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC1_WAKE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC1_WAKE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC2_WAKE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC2_WAKE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} + +// RTCADC.INT_ENA_W1TS: Interrupt enable assert registers. +func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC1_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC1_INT_ENA_W1TS() uint32 { + return volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x1 +} +func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC2_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x2)|value<<1) +} +func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC2_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x2) >> 1 +} +func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC1_ERROR_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x4)|value<<2) +} +func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC1_ERROR_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x4) >> 2 +} +func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC2_ERROR_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x8)|value<<3) +} +func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC2_ERROR_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x8) >> 3 +} +func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC1_WAKE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x10)|value<<4) +} +func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC1_WAKE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x10) >> 4 +} +func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC2_WAKE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x20)|value<<5) +} +func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC2_WAKE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x20) >> 5 +} + +// RTCADC.INT_ENA_W1TC: Interrupt enable deassert registers. +func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC1_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC1_INT_ENA_W1TC() uint32 { + return volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x1 +} +func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC2_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x2)|value<<1) +} +func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC2_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x2) >> 1 +} +func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC1_ERROR_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x4)|value<<2) +} +func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC1_ERROR_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x4) >> 2 +} +func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC2_ERROR_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x8)|value<<3) +} +func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC2_ERROR_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x8) >> 3 +} +func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC1_WAKE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x10)|value<<4) +} +func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC1_WAKE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x10) >> 4 +} +func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC2_WAKE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x20)|value<<5) +} +func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC2_WAKE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x20) >> 5 +} + +// RTCADC.WAKEUP1: ADC1 wakeup configuration registers. +func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_TH_LOW(value uint32) { + volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0xfff)|value) +} +func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_TH_LOW() uint32 { + return volatile.LoadUint32(&o.WAKEUP1.Reg) & 0xfff +} +func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_TH_HIGH(value uint32) { + volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0x3ffc000)|value<<14) +} +func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_TH_HIGH() uint32 { + return (volatile.LoadUint32(&o.WAKEUP1.Reg) & 0x3ffc000) >> 14 +} +func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_OVER_UPPER_TH(value uint32) { + volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0x20000000)|value<<29) +} +func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_OVER_UPPER_TH() uint32 { + return (volatile.LoadUint32(&o.WAKEUP1.Reg) & 0x20000000) >> 29 +} +func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0x40000000)|value<<30) +} +func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.WAKEUP1.Reg) & 0x40000000) >> 30 +} +func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_MODE(value uint32) { + volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0x80000000)|value<<31) +} +func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_MODE() uint32 { + return (volatile.LoadUint32(&o.WAKEUP1.Reg) & 0x80000000) >> 31 +} + +// RTCADC.WAKEUP2: ADC2 wakeup configuration registers. +func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_TH_LOW(value uint32) { + volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0xfff)|value) +} +func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_TH_LOW() uint32 { + return volatile.LoadUint32(&o.WAKEUP2.Reg) & 0xfff +} +func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_TH_HIGH(value uint32) { + volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0x3ffc000)|value<<14) +} +func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_TH_HIGH() uint32 { + return (volatile.LoadUint32(&o.WAKEUP2.Reg) & 0x3ffc000) >> 14 +} +func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_OVER_UPPER_TH(value uint32) { + volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0x20000000)|value<<29) +} +func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_OVER_UPPER_TH() uint32 { + return (volatile.LoadUint32(&o.WAKEUP2.Reg) & 0x20000000) >> 29 +} +func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0x40000000)|value<<30) +} +func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.WAKEUP2.Reg) & 0x40000000) >> 30 +} +func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_MODE(value uint32) { + volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_MODE() uint32 { + return (volatile.LoadUint32(&o.WAKEUP2.Reg) & 0x80000000) >> 31 +} + +// RTCADC.WAKEUP_SEL: Wakeup source select register. +func (o *RTCADC_Type) SetWAKEUP_SEL_SAR_WAKEUP_SEL(value uint32) { + volatile.StoreUint32(&o.WAKEUP_SEL.Reg, volatile.LoadUint32(&o.WAKEUP_SEL.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetWAKEUP_SEL_SAR_WAKEUP_SEL() uint32 { + return volatile.LoadUint32(&o.WAKEUP_SEL.Reg) & 0x1 +} + +// RTCADC.SAR1_HW_WAKEUP: Hardware automatic sampling registers for wakeup function. +func (o *RTCADC_Type) SetSAR1_HW_WAKEUP_ADC1_HW_READ_EN_I(value uint32) { + volatile.StoreUint32(&o.SAR1_HW_WAKEUP.Reg, volatile.LoadUint32(&o.SAR1_HW_WAKEUP.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetSAR1_HW_WAKEUP_ADC1_HW_READ_EN_I() uint32 { + return volatile.LoadUint32(&o.SAR1_HW_WAKEUP.Reg) & 0x1 +} +func (o *RTCADC_Type) SetSAR1_HW_WAKEUP_ADC1_HW_READ_RATE_I(value uint32) { + volatile.StoreUint32(&o.SAR1_HW_WAKEUP.Reg, volatile.LoadUint32(&o.SAR1_HW_WAKEUP.Reg)&^(0x1fffe)|value<<1) +} +func (o *RTCADC_Type) GetSAR1_HW_WAKEUP_ADC1_HW_READ_RATE_I() uint32 { + return (volatile.LoadUint32(&o.SAR1_HW_WAKEUP.Reg) & 0x1fffe) >> 1 +} + +// RTCADC.SAR2_HW_WAKEUP: Hardware automatic sampling registers for wakeup function. +func (o *RTCADC_Type) SetSAR2_HW_WAKEUP_ADC2_HW_READ_EN_I(value uint32) { + volatile.StoreUint32(&o.SAR2_HW_WAKEUP.Reg, volatile.LoadUint32(&o.SAR2_HW_WAKEUP.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetSAR2_HW_WAKEUP_ADC2_HW_READ_EN_I() uint32 { + return volatile.LoadUint32(&o.SAR2_HW_WAKEUP.Reg) & 0x1 +} +func (o *RTCADC_Type) SetSAR2_HW_WAKEUP_ADC2_HW_READ_RATE_I(value uint32) { + volatile.StoreUint32(&o.SAR2_HW_WAKEUP.Reg, volatile.LoadUint32(&o.SAR2_HW_WAKEUP.Reg)&^(0x1fffe)|value<<1) +} +func (o *RTCADC_Type) GetSAR2_HW_WAKEUP_ADC2_HW_READ_RATE_I() uint32 { + return (volatile.LoadUint32(&o.SAR2_HW_WAKEUP.Reg) & 0x1fffe) >> 1 +} + +// RTCADC.RND_ECO_LOW: N/A +func (o *RTCADC_Type) SetRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value) +} +func (o *RTCADC_Type) GetRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RND_ECO_LOW.Reg) +} + +// RTCADC.RND_ECO_HIGH: N/A +func (o *RTCADC_Type) SetRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value) +} +func (o *RTCADC_Type) GetRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg) +} + +// RTCADC.RND_ECO_CS: N/A +func (o *RTCADC_Type) SetRND_ECO_CS_RND_ECO_EN(value uint32) { + volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x1)|value) +} +func (o *RTCADC_Type) GetRND_ECO_CS_RND_ECO_EN() uint32 { + return volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x1 +} +func (o *RTCADC_Type) SetRND_ECO_CS_RND_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *RTCADC_Type) GetRND_ECO_CS_RND_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x2) >> 1 +} + +// Low-power Timer +type RTC_TIMER_Type struct { + TAR0_LOW volatile.Register32 // 0x0 + TAR0_HIGH volatile.Register32 // 0x4 + TAR1_LOW volatile.Register32 // 0x8 + TAR1_HIGH volatile.Register32 // 0xC + UPDATE volatile.Register32 // 0x10 + MAIN_BUF0_LOW volatile.Register32 // 0x14 + MAIN_BUF0_HIGH volatile.Register32 // 0x18 + MAIN_BUF1_LOW volatile.Register32 // 0x1C + MAIN_BUF1_HIGH volatile.Register32 // 0x20 + MAIN_OVERFLOW volatile.Register32 // 0x24 + INT_RAW volatile.Register32 // 0x28 + INT_ST volatile.Register32 // 0x2C + INT_ENA volatile.Register32 // 0x30 + INT_CLR volatile.Register32 // 0x34 + LP_INT_RAW volatile.Register32 // 0x38 + LP_INT_ST volatile.Register32 // 0x3C + LP_INT_ENA volatile.Register32 // 0x40 + LP_INT_CLR volatile.Register32 // 0x44 + _ [948]byte + DATE volatile.Register32 // 0x3FC +} + +// RTC_TIMER.TAR0_LOW: need_des +func (o *RTC_TIMER_Type) SetTAR0_LOW(value uint32) { + volatile.StoreUint32(&o.TAR0_LOW.Reg, value) +} +func (o *RTC_TIMER_Type) GetTAR0_LOW() uint32 { + return volatile.LoadUint32(&o.TAR0_LOW.Reg) +} + +// RTC_TIMER.TAR0_HIGH: need_des +func (o *RTC_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0(value uint32) { + volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0xffff)|value) +} +func (o *RTC_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0() uint32 { + return volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0xffff +} +func (o *RTC_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_EN0(value uint32) { + volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_EN0() uint32 { + return (volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.TAR1_LOW: need_des +func (o *RTC_TIMER_Type) SetTAR1_LOW(value uint32) { + volatile.StoreUint32(&o.TAR1_LOW.Reg, value) +} +func (o *RTC_TIMER_Type) GetTAR1_LOW() uint32 { + return volatile.LoadUint32(&o.TAR1_LOW.Reg) +} + +// RTC_TIMER.TAR1_HIGH: need_des +func (o *RTC_TIMER_Type) SetTAR1_HIGH_MAIN_TIMER_TAR_HIGH1(value uint32) { + volatile.StoreUint32(&o.TAR1_HIGH.Reg, volatile.LoadUint32(&o.TAR1_HIGH.Reg)&^(0xffff)|value) +} +func (o *RTC_TIMER_Type) GetTAR1_HIGH_MAIN_TIMER_TAR_HIGH1() uint32 { + return volatile.LoadUint32(&o.TAR1_HIGH.Reg) & 0xffff +} +func (o *RTC_TIMER_Type) SetTAR1_HIGH_MAIN_TIMER_TAR_EN1(value uint32) { + volatile.StoreUint32(&o.TAR1_HIGH.Reg, volatile.LoadUint32(&o.TAR1_HIGH.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetTAR1_HIGH_MAIN_TIMER_TAR_EN1() uint32 { + return (volatile.LoadUint32(&o.TAR1_HIGH.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.UPDATE: need_des +func (o *RTC_TIMER_Type) SetUPDATE_MAIN_TIMER_UPDATE(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_TIMER_Type) GetUPDATE_MAIN_TIMER_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x10000000) >> 28 +} +func (o *RTC_TIMER_Type) SetUPDATE_MAIN_TIMER_XTAL_OFF(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_TIMER_Type) GetUPDATE_MAIN_TIMER_XTAL_OFF() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x20000000) >> 29 +} +func (o *RTC_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_STALL(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_STALL() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x40000000) >> 30 +} +func (o *RTC_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_RST(value uint32) { + volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.MAIN_BUF0_LOW: need_des +func (o *RTC_TIMER_Type) SetMAIN_BUF0_LOW(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF0_LOW.Reg, value) +} +func (o *RTC_TIMER_Type) GetMAIN_BUF0_LOW() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF0_LOW.Reg) +} + +// RTC_TIMER.MAIN_BUF0_HIGH: need_des +func (o *RTC_TIMER_Type) SetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF0_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg)&^(0xffff)|value) +} +func (o *RTC_TIMER_Type) GetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg) & 0xffff +} + +// RTC_TIMER.MAIN_BUF1_LOW: need_des +func (o *RTC_TIMER_Type) SetMAIN_BUF1_LOW(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF1_LOW.Reg, value) +} +func (o *RTC_TIMER_Type) GetMAIN_BUF1_LOW() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF1_LOW.Reg) +} + +// RTC_TIMER.MAIN_BUF1_HIGH: need_des +func (o *RTC_TIMER_Type) SetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH(value uint32) { + volatile.StoreUint32(&o.MAIN_BUF1_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg)&^(0xffff)|value) +} +func (o *RTC_TIMER_Type) GetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH() uint32 { + return volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg) & 0xffff +} + +// RTC_TIMER.MAIN_OVERFLOW: need_des +func (o *RTC_TIMER_Type) SetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD(value uint32) { + volatile.StoreUint32(&o.MAIN_OVERFLOW.Reg, volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD() uint32 { + return (volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.INT_RAW: need_des +func (o *RTC_TIMER_Type) SetINT_RAW_OVERFLOW_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_TIMER_Type) GetINT_RAW_OVERFLOW_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *RTC_TIMER_Type) SetINT_RAW_SOC_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetINT_RAW_SOC_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.INT_ST: need_des +func (o *RTC_TIMER_Type) SetINT_ST_OVERFLOW_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_TIMER_Type) GetINT_ST_OVERFLOW_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *RTC_TIMER_Type) SetINT_ST_SOC_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetINT_ST_SOC_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.INT_ENA: need_des +func (o *RTC_TIMER_Type) SetINT_ENA_OVERFLOW_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_TIMER_Type) GetINT_ENA_OVERFLOW_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *RTC_TIMER_Type) SetINT_ENA_SOC_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetINT_ENA_SOC_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.INT_CLR: need_des +func (o *RTC_TIMER_Type) SetINT_CLR_OVERFLOW_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_TIMER_Type) GetINT_CLR_OVERFLOW_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *RTC_TIMER_Type) SetINT_CLR_SOC_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetINT_CLR_SOC_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.LP_INT_RAW: need_des +func (o *RTC_TIMER_Type) SetLP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_TIMER_Type) GetLP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *RTC_TIMER_Type) SetLP_INT_RAW_MAIN_TIMER_LP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetLP_INT_RAW_MAIN_TIMER_LP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.LP_INT_ST: need_des +func (o *RTC_TIMER_Type) SetLP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_TIMER_Type) GetLP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *RTC_TIMER_Type) SetLP_INT_ST_MAIN_TIMER_LP_INT_ST(value uint32) { + volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetLP_INT_ST_MAIN_TIMER_LP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.LP_INT_ENA: need_des +func (o *RTC_TIMER_Type) SetLP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_TIMER_Type) GetLP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *RTC_TIMER_Type) SetLP_INT_ENA_MAIN_TIMER_LP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetLP_INT_ENA_MAIN_TIMER_LP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.LP_INT_CLR: need_des +func (o *RTC_TIMER_Type) SetLP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_TIMER_Type) GetLP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *RTC_TIMER_Type) SetLP_INT_CLR_MAIN_TIMER_LP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetLP_INT_CLR_MAIN_TIMER_LP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// RTC_TIMER.DATE: need_des +func (o *RTC_TIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *RTC_TIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *RTC_TIMER_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TIMER_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// LP_TOUCH Peripheral +type RTC_TOUCH_Type struct { + INT_RAW volatile.Register32 // 0x0 + INT_ST volatile.Register32 // 0x4 + INT_ENA volatile.Register32 // 0x8 + INT_CLR volatile.Register32 // 0xC + CHN_STATUS volatile.Register32 // 0x10 + STATUS_0 volatile.Register32 // 0x14 + STATUS_1 volatile.Register32 // 0x18 + STATUS_2 volatile.Register32 // 0x1C + STATUS_3 volatile.Register32 // 0x20 + STATUS_4 volatile.Register32 // 0x24 + STATUS_5 volatile.Register32 // 0x28 + STATUS_6 volatile.Register32 // 0x2C + STATUS_7 volatile.Register32 // 0x30 + STATUS_8 volatile.Register32 // 0x34 + STATUS_9 volatile.Register32 // 0x38 + STATUS_10 volatile.Register32 // 0x3C + STATUS_11 volatile.Register32 // 0x40 + STATUS_12 volatile.Register32 // 0x44 + STATUS_13 volatile.Register32 // 0x48 + STATUS_14 volatile.Register32 // 0x4C + STATUS_15 volatile.Register32 // 0x50 + STATUS_16 volatile.Register32 // 0x54 + STATUS_17 volatile.Register32 // 0x58 + CHN_TMP_STATUS volatile.Register32 // 0x5C + _ [160]byte + DATE volatile.Register32 // 0x100 +} + +// RTC_TOUCH.INT_RAW: need_des +func (o *RTC_TOUCH_Type) SetINT_RAW_SCAN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RTC_TOUCH_Type) GetINT_RAW_SCAN_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RTC_TOUCH_Type) SetINT_RAW_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RTC_TOUCH_Type) GetINT_RAW_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RTC_TOUCH_Type) SetINT_RAW_ACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RTC_TOUCH_Type) GetINT_RAW_ACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RTC_TOUCH_Type) SetINT_RAW_INACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *RTC_TOUCH_Type) GetINT_RAW_INACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *RTC_TOUCH_Type) SetINT_RAW_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RTC_TOUCH_Type) GetINT_RAW_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RTC_TOUCH_Type) SetINT_RAW_APPROACH_LOOP_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *RTC_TOUCH_Type) GetINT_RAW_APPROACH_LOOP_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} + +// RTC_TOUCH.INT_ST: need_des +func (o *RTC_TOUCH_Type) SetINT_ST_SCAN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RTC_TOUCH_Type) GetINT_ST_SCAN_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RTC_TOUCH_Type) SetINT_ST_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RTC_TOUCH_Type) GetINT_ST_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RTC_TOUCH_Type) SetINT_ST_ACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTC_TOUCH_Type) GetINT_ST_ACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RTC_TOUCH_Type) SetINT_ST_INACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTC_TOUCH_Type) GetINT_ST_INACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *RTC_TOUCH_Type) SetINT_ST_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTC_TOUCH_Type) GetINT_ST_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RTC_TOUCH_Type) SetINT_ST_APPROACH_LOOP_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTC_TOUCH_Type) GetINT_ST_APPROACH_LOOP_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} + +// RTC_TOUCH.INT_ENA: need_des +func (o *RTC_TOUCH_Type) SetINT_ENA_SCAN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RTC_TOUCH_Type) GetINT_ENA_SCAN_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RTC_TOUCH_Type) SetINT_ENA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RTC_TOUCH_Type) GetINT_ENA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RTC_TOUCH_Type) SetINT_ENA_ACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RTC_TOUCH_Type) GetINT_ENA_ACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RTC_TOUCH_Type) SetINT_ENA_INACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *RTC_TOUCH_Type) GetINT_ENA_INACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *RTC_TOUCH_Type) SetINT_ENA_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RTC_TOUCH_Type) GetINT_ENA_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RTC_TOUCH_Type) SetINT_ENA_APPROACH_LOOP_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *RTC_TOUCH_Type) GetINT_ENA_APPROACH_LOOP_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} + +// RTC_TOUCH.INT_CLR: need_des +func (o *RTC_TOUCH_Type) SetINT_CLR_SCAN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RTC_TOUCH_Type) GetINT_CLR_SCAN_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RTC_TOUCH_Type) SetINT_CLR_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RTC_TOUCH_Type) GetINT_CLR_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RTC_TOUCH_Type) SetINT_CLR_ACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RTC_TOUCH_Type) GetINT_CLR_ACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RTC_TOUCH_Type) SetINT_CLR_INACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *RTC_TOUCH_Type) GetINT_CLR_INACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *RTC_TOUCH_Type) SetINT_CLR_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RTC_TOUCH_Type) GetINT_CLR_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RTC_TOUCH_Type) SetINT_CLR_APPROACH_LOOP_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *RTC_TOUCH_Type) GetINT_CLR_APPROACH_LOOP_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} + +// RTC_TOUCH.CHN_STATUS: need_des +func (o *RTC_TOUCH_Type) SetCHN_STATUS_PAD_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CHN_STATUS.Reg, volatile.LoadUint32(&o.CHN_STATUS.Reg)&^(0x7fff)|value) +} +func (o *RTC_TOUCH_Type) GetCHN_STATUS_PAD_ACTIVE() uint32 { + return volatile.LoadUint32(&o.CHN_STATUS.Reg) & 0x7fff +} +func (o *RTC_TOUCH_Type) SetCHN_STATUS_MEAS_DONE(value uint32) { + volatile.StoreUint32(&o.CHN_STATUS.Reg, volatile.LoadUint32(&o.CHN_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_TOUCH_Type) GetCHN_STATUS_MEAS_DONE() uint32 { + return (volatile.LoadUint32(&o.CHN_STATUS.Reg) & 0x8000) >> 15 +} +func (o *RTC_TOUCH_Type) SetCHN_STATUS_SCAN_CURR(value uint32) { + volatile.StoreUint32(&o.CHN_STATUS.Reg, volatile.LoadUint32(&o.CHN_STATUS.Reg)&^(0xf0000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetCHN_STATUS_SCAN_CURR() uint32 { + return (volatile.LoadUint32(&o.CHN_STATUS.Reg) & 0xf0000) >> 16 +} + +// RTC_TOUCH.STATUS_0: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_0_PAD0_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_0.Reg, volatile.LoadUint32(&o.STATUS_0.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_0_PAD0_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_0.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_0_PAD0_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_0.Reg, volatile.LoadUint32(&o.STATUS_0.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_0_PAD0_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_0.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_0_PAD0_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_0.Reg, volatile.LoadUint32(&o.STATUS_0.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_0_PAD0_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_0.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_1: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_1_PAD1_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_1.Reg, volatile.LoadUint32(&o.STATUS_1.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_1_PAD1_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_1.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_1_PAD1_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_1.Reg, volatile.LoadUint32(&o.STATUS_1.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_1_PAD1_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_1.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_1_PAD1_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_1.Reg, volatile.LoadUint32(&o.STATUS_1.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_1_PAD1_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_1.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_2: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_2_PAD2_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_2.Reg, volatile.LoadUint32(&o.STATUS_2.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_2_PAD2_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_2.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_2_PAD2_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_2.Reg, volatile.LoadUint32(&o.STATUS_2.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_2_PAD2_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_2.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_2_PAD2_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_2.Reg, volatile.LoadUint32(&o.STATUS_2.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_2_PAD2_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_2.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_3: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_3_PAD3_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_3.Reg, volatile.LoadUint32(&o.STATUS_3.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_3_PAD3_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_3.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_3_PAD3_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_3.Reg, volatile.LoadUint32(&o.STATUS_3.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_3_PAD3_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_3.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_3_PAD3_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_3.Reg, volatile.LoadUint32(&o.STATUS_3.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_3_PAD3_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_3.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_4: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_4_PAD4_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_4.Reg, volatile.LoadUint32(&o.STATUS_4.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_4_PAD4_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_4.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_4_PAD4_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_4.Reg, volatile.LoadUint32(&o.STATUS_4.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_4_PAD4_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_4.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_4_PAD4_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_4.Reg, volatile.LoadUint32(&o.STATUS_4.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_4_PAD4_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_4.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_5: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_5_PAD5_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_5.Reg, volatile.LoadUint32(&o.STATUS_5.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_5_PAD5_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_5.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_5_PAD5_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_5.Reg, volatile.LoadUint32(&o.STATUS_5.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_5_PAD5_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_5.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_5_PAD5_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_5.Reg, volatile.LoadUint32(&o.STATUS_5.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_5_PAD5_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_5.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_6: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_6_PAD6_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_6.Reg, volatile.LoadUint32(&o.STATUS_6.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_6_PAD6_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_6.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_6_PAD6_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_6.Reg, volatile.LoadUint32(&o.STATUS_6.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_6_PAD6_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_6.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_6_PAD6_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_6.Reg, volatile.LoadUint32(&o.STATUS_6.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_6_PAD6_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_6.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_7: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_7_PAD7_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_7.Reg, volatile.LoadUint32(&o.STATUS_7.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_7_PAD7_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_7.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_7_PAD7_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_7.Reg, volatile.LoadUint32(&o.STATUS_7.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_7_PAD7_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_7.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_7_PAD7_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_7.Reg, volatile.LoadUint32(&o.STATUS_7.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_7_PAD7_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_7.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_8: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_8_PAD8_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_8.Reg, volatile.LoadUint32(&o.STATUS_8.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_8_PAD8_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_8.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_8_PAD8_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_8.Reg, volatile.LoadUint32(&o.STATUS_8.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_8_PAD8_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_8.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_8_PAD8_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_8.Reg, volatile.LoadUint32(&o.STATUS_8.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_8_PAD8_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_8.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_9: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_9_PAD9_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_9.Reg, volatile.LoadUint32(&o.STATUS_9.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_9_PAD9_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_9.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_9_PAD9_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_9.Reg, volatile.LoadUint32(&o.STATUS_9.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_9_PAD9_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_9.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_9_PAD9_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_9.Reg, volatile.LoadUint32(&o.STATUS_9.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_9_PAD9_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_9.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_10: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_10_PAD10_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_10.Reg, volatile.LoadUint32(&o.STATUS_10.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_10_PAD10_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_10.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_10_PAD10_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_10.Reg, volatile.LoadUint32(&o.STATUS_10.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_10_PAD10_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_10.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_10_PAD10_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_10.Reg, volatile.LoadUint32(&o.STATUS_10.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_10_PAD10_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_10.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_11: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_11_PAD11_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_11.Reg, volatile.LoadUint32(&o.STATUS_11.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_11_PAD11_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_11.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_11_PAD11_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_11.Reg, volatile.LoadUint32(&o.STATUS_11.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_11_PAD11_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_11.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_11_PAD11_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_11.Reg, volatile.LoadUint32(&o.STATUS_11.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_11_PAD11_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_11.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_12: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_12_PAD12_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_12.Reg, volatile.LoadUint32(&o.STATUS_12.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_12_PAD12_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_12.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_12_PAD12_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_12.Reg, volatile.LoadUint32(&o.STATUS_12.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_12_PAD12_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_12.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_12_PAD12_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_12.Reg, volatile.LoadUint32(&o.STATUS_12.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_12_PAD12_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_12.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_13: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_13_PAD13_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_13.Reg, volatile.LoadUint32(&o.STATUS_13.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_13_PAD13_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_13.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_13_PAD13_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_13.Reg, volatile.LoadUint32(&o.STATUS_13.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_13_PAD13_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_13.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_13_PAD13_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_13.Reg, volatile.LoadUint32(&o.STATUS_13.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_13_PAD13_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_13.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_14: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_14_PAD14_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_14.Reg, volatile.LoadUint32(&o.STATUS_14.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_14_PAD14_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_14.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_14_PAD14_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_14.Reg, volatile.LoadUint32(&o.STATUS_14.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_14_PAD14_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_14.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_14_PAD14_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_14.Reg, volatile.LoadUint32(&o.STATUS_14.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_14_PAD14_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_14.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_15: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_15_SLP_DATA(value uint32) { + volatile.StoreUint32(&o.STATUS_15.Reg, volatile.LoadUint32(&o.STATUS_15.Reg)&^(0xffff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_15_SLP_DATA() uint32 { + return volatile.LoadUint32(&o.STATUS_15.Reg) & 0xffff +} +func (o *RTC_TOUCH_Type) SetSTATUS_15_SLP_DEBOUNCE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_15.Reg, volatile.LoadUint32(&o.STATUS_15.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_15_SLP_DEBOUNCE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_15.Reg) & 0x70000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_15_SLP_NEG_NOISE_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_15.Reg, volatile.LoadUint32(&o.STATUS_15.Reg)&^(0x780000)|value<<19) +} +func (o *RTC_TOUCH_Type) GetSTATUS_15_SLP_NEG_NOISE_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_15.Reg) & 0x780000) >> 19 +} + +// RTC_TOUCH.STATUS_16: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_16_APPROACH_PAD2_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_16.Reg, volatile.LoadUint32(&o.STATUS_16.Reg)&^(0xff)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_16_APPROACH_PAD2_CNT() uint32 { + return volatile.LoadUint32(&o.STATUS_16.Reg) & 0xff +} +func (o *RTC_TOUCH_Type) SetSTATUS_16_APPROACH_PAD1_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_16.Reg, volatile.LoadUint32(&o.STATUS_16.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_TOUCH_Type) GetSTATUS_16_APPROACH_PAD1_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_16.Reg) & 0xff00) >> 8 +} +func (o *RTC_TOUCH_Type) SetSTATUS_16_APPROACH_PAD0_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_16.Reg, volatile.LoadUint32(&o.STATUS_16.Reg)&^(0xff0000)|value<<16) +} +func (o *RTC_TOUCH_Type) GetSTATUS_16_APPROACH_PAD0_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_16.Reg) & 0xff0000) >> 16 +} +func (o *RTC_TOUCH_Type) SetSTATUS_16_SLP_APPROACH_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_16.Reg, volatile.LoadUint32(&o.STATUS_16.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_TOUCH_Type) GetSTATUS_16_SLP_APPROACH_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_16.Reg) & 0xff000000) >> 24 +} + +// RTC_TOUCH.STATUS_17: need_des +func (o *RTC_TOUCH_Type) SetSTATUS_17_DCAP_LPF(value uint32) { + volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x7f)|value) +} +func (o *RTC_TOUCH_Type) GetSTATUS_17_DCAP_LPF() uint32 { + return volatile.LoadUint32(&o.STATUS_17.Reg) & 0x7f +} +func (o *RTC_TOUCH_Type) SetSTATUS_17_DRES_LPF(value uint32) { + volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x180)|value<<7) +} +func (o *RTC_TOUCH_Type) GetSTATUS_17_DRES_LPF() uint32 { + return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x180) >> 7 +} +func (o *RTC_TOUCH_Type) SetSTATUS_17_DRV_LS(value uint32) { + volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x1e00)|value<<9) +} +func (o *RTC_TOUCH_Type) GetSTATUS_17_DRV_LS() uint32 { + return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x1e00) >> 9 +} +func (o *RTC_TOUCH_Type) SetSTATUS_17_DRV_HS(value uint32) { + volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x3e000)|value<<13) +} +func (o *RTC_TOUCH_Type) GetSTATUS_17_DRV_HS() uint32 { + return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x3e000) >> 13 +} +func (o *RTC_TOUCH_Type) SetSTATUS_17_DBIAS(value uint32) { + volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x7c0000)|value<<18) +} +func (o *RTC_TOUCH_Type) GetSTATUS_17_DBIAS() uint32 { + return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x7c0000) >> 18 +} +func (o *RTC_TOUCH_Type) SetSTATUS_17_RTC_FREQ_SCAN_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x1800000)|value<<23) +} +func (o *RTC_TOUCH_Type) GetSTATUS_17_RTC_FREQ_SCAN_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x1800000) >> 23 +} + +// RTC_TOUCH.CHN_TMP_STATUS: need_des +func (o *RTC_TOUCH_Type) SetCHN_TMP_STATUS_PAD_INACTIVE_STATUS(value uint32) { + volatile.StoreUint32(&o.CHN_TMP_STATUS.Reg, volatile.LoadUint32(&o.CHN_TMP_STATUS.Reg)&^(0x7fff)|value) +} +func (o *RTC_TOUCH_Type) GetCHN_TMP_STATUS_PAD_INACTIVE_STATUS() uint32 { + return volatile.LoadUint32(&o.CHN_TMP_STATUS.Reg) & 0x7fff +} +func (o *RTC_TOUCH_Type) SetCHN_TMP_STATUS_PAD_ACTIVE_STATUS(value uint32) { + volatile.StoreUint32(&o.CHN_TMP_STATUS.Reg, volatile.LoadUint32(&o.CHN_TMP_STATUS.Reg)&^(0x3fff8000)|value<<15) +} +func (o *RTC_TOUCH_Type) GetCHN_TMP_STATUS_PAD_ACTIVE_STATUS() uint32 { + return (volatile.LoadUint32(&o.CHN_TMP_STATUS.Reg) & 0x3fff8000) >> 15 +} + +// RTC_TOUCH.DATE: need_des +func (o *RTC_TOUCH_Type) SetDATE_RTC_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_TOUCH_Type) GetDATE_RTC_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} +func (o *RTC_TOUCH_Type) SetDATE_RTC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_TOUCH_Type) GetDATE_RTC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Low-power Watchdog Timer +type RTC_WDT_Type struct { + CONFIG0 volatile.Register32 // 0x0 + CONFIG1 volatile.Register32 // 0x4 + CONFIG2 volatile.Register32 // 0x8 + CONFIG3 volatile.Register32 // 0xC + CONFIG4 volatile.Register32 // 0x10 + FEED volatile.Register32 // 0x14 + WPROTECT volatile.Register32 // 0x18 + SWD_CONFIG volatile.Register32 // 0x1C + SWD_WPROTECT volatile.Register32 // 0x20 + INT_RAW volatile.Register32 // 0x24 + INT_ST volatile.Register32 // 0x28 + INT_ENA volatile.Register32 // 0x2C + INT_CLR volatile.Register32 // 0x30 + _ [968]byte + DATE volatile.Register32 // 0x3FC +} + +// RTC_WDT.CONFIG0: need_des +func (o *RTC_WDT_Type) SetCONFIG0_WDT_CHIP_RESET_WIDTH(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0xff)|value) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_CHIP_RESET_WIDTH() uint32 { + return volatile.LoadUint32(&o.CONFIG0.Reg) & 0xff +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_CHIP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_CHIP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x100) >> 8 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_PAUSE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_PAUSE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x200) >> 9 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x400) >> 10 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x800) >> 11 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x1000) >> 12 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0xe000)|value<<13) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0xe000) >> 13 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x70000) >> 16 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x380000)|value<<19) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x380000) >> 19 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x1c00000)|value<<22) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x1c00000) >> 22 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0xe000000) >> 25 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x70000000) >> 28 +} +func (o *RTC_WDT_Type) SetCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_WDT_Type) GetCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x80000000) >> 31 +} + +// RTC_WDT.CONFIG1: need_des +func (o *RTC_WDT_Type) SetCONFIG1(value uint32) { + volatile.StoreUint32(&o.CONFIG1.Reg, value) +} +func (o *RTC_WDT_Type) GetCONFIG1() uint32 { + return volatile.LoadUint32(&o.CONFIG1.Reg) +} + +// RTC_WDT.CONFIG2: need_des +func (o *RTC_WDT_Type) SetCONFIG2(value uint32) { + volatile.StoreUint32(&o.CONFIG2.Reg, value) +} +func (o *RTC_WDT_Type) GetCONFIG2() uint32 { + return volatile.LoadUint32(&o.CONFIG2.Reg) +} + +// RTC_WDT.CONFIG3: need_des +func (o *RTC_WDT_Type) SetCONFIG3(value uint32) { + volatile.StoreUint32(&o.CONFIG3.Reg, value) +} +func (o *RTC_WDT_Type) GetCONFIG3() uint32 { + return volatile.LoadUint32(&o.CONFIG3.Reg) +} + +// RTC_WDT.CONFIG4: need_des +func (o *RTC_WDT_Type) SetCONFIG4(value uint32) { + volatile.StoreUint32(&o.CONFIG4.Reg, value) +} +func (o *RTC_WDT_Type) GetCONFIG4() uint32 { + return volatile.LoadUint32(&o.CONFIG4.Reg) +} + +// RTC_WDT.FEED: need_des +func (o *RTC_WDT_Type) SetFEED(value uint32) { + volatile.StoreUint32(&o.FEED.Reg, volatile.LoadUint32(&o.FEED.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_WDT_Type) GetFEED() uint32 { + return (volatile.LoadUint32(&o.FEED.Reg) & 0x80000000) >> 31 +} + +// RTC_WDT.WPROTECT: need_des +func (o *RTC_WDT_Type) SetWPROTECT(value uint32) { + volatile.StoreUint32(&o.WPROTECT.Reg, value) +} +func (o *RTC_WDT_Type) GetWPROTECT() uint32 { + return volatile.LoadUint32(&o.WPROTECT.Reg) +} + +// RTC_WDT.SWD_CONFIG: need_des +func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x1)|value) +} +func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_RESET_FLAG() uint32 { + return volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x1 +} +func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_AUTO_FEED_EN(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_AUTO_FEED_EN() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x40000) >> 18 +} +func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_RST_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_RST_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x80000) >> 19 +} +func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_SIGNAL_WIDTH(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x3ff00000)|value<<20) +} +func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_SIGNAL_WIDTH() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x3ff00000) >> 20 +} +func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_DISABLE(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_FEED(value uint32) { + volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_FEED() uint32 { + return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x80000000) >> 31 +} + +// RTC_WDT.SWD_WPROTECT: need_des +func (o *RTC_WDT_Type) SetSWD_WPROTECT(value uint32) { + volatile.StoreUint32(&o.SWD_WPROTECT.Reg, value) +} +func (o *RTC_WDT_Type) GetSWD_WPROTECT() uint32 { + return volatile.LoadUint32(&o.SWD_WPROTECT.Reg) +} + +// RTC_WDT.INT_RAW: need_des +func (o *RTC_WDT_Type) SetINT_RAW_SUPER_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_WDT_Type) GetINT_RAW_SUPER_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *RTC_WDT_Type) SetINT_RAW_LP_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_WDT_Type) GetINT_RAW_LP_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// RTC_WDT.INT_ST: need_des +func (o *RTC_WDT_Type) SetINT_ST_SUPER_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_WDT_Type) GetINT_ST_SUPER_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *RTC_WDT_Type) SetINT_ST_LP_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_WDT_Type) GetINT_ST_LP_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// RTC_WDT.INT_ENA: need_des +func (o *RTC_WDT_Type) SetINT_ENA_SUPER_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_WDT_Type) GetINT_ENA_SUPER_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *RTC_WDT_Type) SetINT_ENA_LP_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_WDT_Type) GetINT_ENA_LP_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// RTC_WDT.INT_CLR: need_des +func (o *RTC_WDT_Type) SetINT_CLR_SUPER_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_WDT_Type) GetINT_CLR_SUPER_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *RTC_WDT_Type) SetINT_CLR_LP_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_WDT_Type) GetINT_CLR_LP_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// RTC_WDT.DATE: need_des +func (o *RTC_WDT_Type) SetDATE_LP_WDT_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value) +} +func (o *RTC_WDT_Type) GetDATE_LP_WDT_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff +} +func (o *RTC_WDT_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_WDT_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// SD/MMC Host Controller +type SDHOST_Type struct { + CTRL volatile.Register32 // 0x0 + _ [4]byte + CLKDIV volatile.Register32 // 0x8 + CLKSRC volatile.Register32 // 0xC + CLKENA volatile.Register32 // 0x10 + TMOUT volatile.Register32 // 0x14 + CTYPE volatile.Register32 // 0x18 + BLKSIZ volatile.Register32 // 0x1C + BYTCNT volatile.Register32 // 0x20 + INTMASK volatile.Register32 // 0x24 + CMDARG volatile.Register32 // 0x28 + CMD volatile.Register32 // 0x2C + RESP0 volatile.Register32 // 0x30 + RESP1 volatile.Register32 // 0x34 + RESP2 volatile.Register32 // 0x38 + RESP3 volatile.Register32 // 0x3C + MINTSTS volatile.Register32 // 0x40 + RINTSTS volatile.Register32 // 0x44 + STATUS volatile.Register32 // 0x48 + FIFOTH volatile.Register32 // 0x4C + CDETECT volatile.Register32 // 0x50 + WRTPRT volatile.Register32 // 0x54 + _ [4]byte + TCBCNT volatile.Register32 // 0x5C + TBBCNT volatile.Register32 // 0x60 + DEBNCE volatile.Register32 // 0x64 + USRID volatile.Register32 // 0x68 + VERID volatile.Register32 // 0x6C + HCON volatile.Register32 // 0x70 + UHS volatile.Register32 // 0x74 + RST_N volatile.Register32 // 0x78 + _ [4]byte + BMOD volatile.Register32 // 0x80 + PLDMND volatile.Register32 // 0x84 + DBADDR volatile.Register32 // 0x88 + IDSTS volatile.Register32 // 0x8C + IDINTEN volatile.Register32 // 0x90 + DSCADDR volatile.Register32 // 0x94 + BUFADDR volatile.Register32 // 0x98 + _ [100]byte + CARDTHRCTL volatile.Register32 // 0x100 + _ [8]byte + EMMCDDR volatile.Register32 // 0x10C + ENSHIFT volatile.Register32 // 0x110 + _ [236]byte + BUFFIFO volatile.Register32 // 0x200 + _ [1532]byte + CLK_EDGE_SEL volatile.Register32 // 0x800 + RAW_INTS volatile.Register32 // 0x804 + DLL_CLK_CONF volatile.Register32 // 0x808 + DLL_CONF volatile.Register32 // 0x80C +} + +// SDHOST.CTRL: Control register +func (o *SDHOST_Type) SetCTRL_CONTROLLER_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetCTRL_CONTROLLER_RESET() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *SDHOST_Type) SetCTRL_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetCTRL_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetCTRL_DMA_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetCTRL_DMA_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetCTRL_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SDHOST_Type) GetCTRL_INT_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *SDHOST_Type) SetCTRL_READ_WAIT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SDHOST_Type) GetCTRL_READ_WAIT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SDHOST_Type) SetCTRL_SEND_IRQ_RESPONSE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SDHOST_Type) GetCTRL_SEND_IRQ_RESPONSE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SDHOST_Type) SetCTRL_ABORT_READ_DATA(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetCTRL_ABORT_READ_DATA() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetCTRL_SEND_CCSD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetCTRL_SEND_CCSD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetCTRL_SEND_AUTO_STOP_CCSD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SDHOST_Type) GetCTRL_SEND_AUTO_STOP_CCSD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SDHOST_Type) SetCTRL_CEATA_DEVICE_INTERRUPT_STATUS(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SDHOST_Type) GetCTRL_CEATA_DEVICE_INTERRUPT_STATUS() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11 +} + +// SDHOST.CLKDIV: Clock divider configuration register +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER0(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff)|value) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER0() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff +} +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER1(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff00)|value<<8) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER1() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff00) >> 8 +} +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER2(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff0000)|value<<16) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER2() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff0000) >> 16 +} +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER3(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff000000)|value<<24) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER3() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff000000) >> 24 +} + +// SDHOST.CLKSRC: Clock source selection register +func (o *SDHOST_Type) SetCLKSRC(value uint32) { + volatile.StoreUint32(&o.CLKSRC.Reg, volatile.LoadUint32(&o.CLKSRC.Reg)&^(0xf)|value) +} +func (o *SDHOST_Type) GetCLKSRC() uint32 { + return volatile.LoadUint32(&o.CLKSRC.Reg) & 0xf +} + +// SDHOST.CLKENA: Clock enable register +func (o *SDHOST_Type) SetCLKENA_CCLK_ENABLE(value uint32) { + volatile.StoreUint32(&o.CLKENA.Reg, volatile.LoadUint32(&o.CLKENA.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetCLKENA_CCLK_ENABLE() uint32 { + return volatile.LoadUint32(&o.CLKENA.Reg) & 0x3 +} +func (o *SDHOST_Type) SetCLKENA_LP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CLKENA.Reg, volatile.LoadUint32(&o.CLKENA.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetCLKENA_LP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CLKENA.Reg) & 0x30000) >> 16 +} + +// SDHOST.TMOUT: Data and response timeout configuration register +func (o *SDHOST_Type) SetTMOUT_RESPONSE_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.TMOUT.Reg, volatile.LoadUint32(&o.TMOUT.Reg)&^(0xff)|value) +} +func (o *SDHOST_Type) GetTMOUT_RESPONSE_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.TMOUT.Reg) & 0xff +} +func (o *SDHOST_Type) SetTMOUT_DATA_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.TMOUT.Reg, volatile.LoadUint32(&o.TMOUT.Reg)&^(0xffffff00)|value<<8) +} +func (o *SDHOST_Type) GetTMOUT_DATA_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.TMOUT.Reg) & 0xffffff00) >> 8 +} + +// SDHOST.CTYPE: Card bus width configuration register +func (o *SDHOST_Type) SetCTYPE_CARD_WIDTH4(value uint32) { + volatile.StoreUint32(&o.CTYPE.Reg, volatile.LoadUint32(&o.CTYPE.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetCTYPE_CARD_WIDTH4() uint32 { + return volatile.LoadUint32(&o.CTYPE.Reg) & 0x3 +} +func (o *SDHOST_Type) SetCTYPE_CARD_WIDTH8(value uint32) { + volatile.StoreUint32(&o.CTYPE.Reg, volatile.LoadUint32(&o.CTYPE.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetCTYPE_CARD_WIDTH8() uint32 { + return (volatile.LoadUint32(&o.CTYPE.Reg) & 0x30000) >> 16 +} + +// SDHOST.BLKSIZ: Card data block size configuration register +func (o *SDHOST_Type) SetBLKSIZ_BLOCK_SIZE(value uint32) { + volatile.StoreUint32(&o.BLKSIZ.Reg, volatile.LoadUint32(&o.BLKSIZ.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetBLKSIZ_BLOCK_SIZE() uint32 { + return volatile.LoadUint32(&o.BLKSIZ.Reg) & 0xffff +} + +// SDHOST.BYTCNT: Data transfer length configuration register +func (o *SDHOST_Type) SetBYTCNT(value uint32) { + volatile.StoreUint32(&o.BYTCNT.Reg, value) +} +func (o *SDHOST_Type) GetBYTCNT() uint32 { + return volatile.LoadUint32(&o.BYTCNT.Reg) +} + +// SDHOST.INTMASK: SDIO interrupt mask register +func (o *SDHOST_Type) SetINTMASK_INT_MASK(value uint32) { + volatile.StoreUint32(&o.INTMASK.Reg, volatile.LoadUint32(&o.INTMASK.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetINTMASK_INT_MASK() uint32 { + return volatile.LoadUint32(&o.INTMASK.Reg) & 0xffff +} +func (o *SDHOST_Type) SetINTMASK_SDIO_INT_MASK(value uint32) { + volatile.StoreUint32(&o.INTMASK.Reg, volatile.LoadUint32(&o.INTMASK.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetINTMASK_SDIO_INT_MASK() uint32 { + return (volatile.LoadUint32(&o.INTMASK.Reg) & 0x30000) >> 16 +} + +// SDHOST.CMDARG: Command argument data register +func (o *SDHOST_Type) SetCMDARG(value uint32) { + volatile.StoreUint32(&o.CMDARG.Reg, value) +} +func (o *SDHOST_Type) GetCMDARG() uint32 { + return volatile.LoadUint32(&o.CMDARG.Reg) +} + +// SDHOST.CMD: Command and boot configuration register +func (o *SDHOST_Type) SetCMD_INDEX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3f)|value) +} +func (o *SDHOST_Type) GetCMD_INDEX() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x3f +} +func (o *SDHOST_Type) SetCMD_RESPONSE_EXPECT(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40)|value<<6) +} +func (o *SDHOST_Type) GetCMD_RESPONSE_EXPECT() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40) >> 6 +} +func (o *SDHOST_Type) SetCMD_RESPONSE_LENGTH(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80)|value<<7) +} +func (o *SDHOST_Type) GetCMD_RESPONSE_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80) >> 7 +} +func (o *SDHOST_Type) SetCMD_CHECK_RESPONSE_CRC(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetCMD_CHECK_RESPONSE_CRC() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetCMD_DATA_EXPECTED(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetCMD_DATA_EXPECTED() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetCMD_READ_WRITE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400)|value<<10) +} +func (o *SDHOST_Type) GetCMD_READ_WRITE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400) >> 10 +} +func (o *SDHOST_Type) SetCMD_TRANSFER_MODE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800)|value<<11) +} +func (o *SDHOST_Type) GetCMD_TRANSFER_MODE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800) >> 11 +} +func (o *SDHOST_Type) SetCMD_SEND_AUTO_STOP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000)|value<<12) +} +func (o *SDHOST_Type) GetCMD_SEND_AUTO_STOP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000) >> 12 +} +func (o *SDHOST_Type) SetCMD_WAIT_PRVDATA_COMPLETE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2000)|value<<13) +} +func (o *SDHOST_Type) GetCMD_WAIT_PRVDATA_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2000) >> 13 +} +func (o *SDHOST_Type) SetCMD_STOP_ABORT_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4000)|value<<14) +} +func (o *SDHOST_Type) GetCMD_STOP_ABORT_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4000) >> 14 +} +func (o *SDHOST_Type) SetCMD_SEND_INITIALIZATION(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8000)|value<<15) +} +func (o *SDHOST_Type) GetCMD_SEND_INITIALIZATION() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8000) >> 15 +} +func (o *SDHOST_Type) SetCMD_CARD_NUMBER(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1f0000)|value<<16) +} +func (o *SDHOST_Type) GetCMD_CARD_NUMBER() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1f0000) >> 16 +} +func (o *SDHOST_Type) SetCMD_UPDATE_CLOCK_REGISTERS_ONLY(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SDHOST_Type) GetCMD_UPDATE_CLOCK_REGISTERS_ONLY() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200000) >> 21 +} +func (o *SDHOST_Type) SetCMD_READ_CEATA_DEVICE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SDHOST_Type) GetCMD_READ_CEATA_DEVICE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400000) >> 22 +} +func (o *SDHOST_Type) SetCMD_CCS_EXPECTED(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SDHOST_Type) GetCMD_CCS_EXPECTED() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SDHOST_Type) SetCMD_USE_HOLE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SDHOST_Type) GetCMD_USE_HOLE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29 +} +func (o *SDHOST_Type) SetCMD_START_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SDHOST_Type) GetCMD_START_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31 +} + +// SDHOST.RESP0: Response data register +func (o *SDHOST_Type) SetRESP0(value uint32) { + volatile.StoreUint32(&o.RESP0.Reg, value) +} +func (o *SDHOST_Type) GetRESP0() uint32 { + return volatile.LoadUint32(&o.RESP0.Reg) +} + +// SDHOST.RESP1: Long response data register +func (o *SDHOST_Type) SetRESP1(value uint32) { + volatile.StoreUint32(&o.RESP1.Reg, value) +} +func (o *SDHOST_Type) GetRESP1() uint32 { + return volatile.LoadUint32(&o.RESP1.Reg) +} + +// SDHOST.RESP2: Long response data register +func (o *SDHOST_Type) SetRESP2(value uint32) { + volatile.StoreUint32(&o.RESP2.Reg, value) +} +func (o *SDHOST_Type) GetRESP2() uint32 { + return volatile.LoadUint32(&o.RESP2.Reg) +} + +// SDHOST.RESP3: Long response data register +func (o *SDHOST_Type) SetRESP3(value uint32) { + volatile.StoreUint32(&o.RESP3.Reg, value) +} +func (o *SDHOST_Type) GetRESP3() uint32 { + return volatile.LoadUint32(&o.RESP3.Reg) +} + +// SDHOST.MINTSTS: Masked interrupt status register +func (o *SDHOST_Type) SetMINTSTS_INT_STATUS_MSK(value uint32) { + volatile.StoreUint32(&o.MINTSTS.Reg, volatile.LoadUint32(&o.MINTSTS.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetMINTSTS_INT_STATUS_MSK() uint32 { + return volatile.LoadUint32(&o.MINTSTS.Reg) & 0xffff +} +func (o *SDHOST_Type) SetMINTSTS_SDIO_INTERRUPT_MSK(value uint32) { + volatile.StoreUint32(&o.MINTSTS.Reg, volatile.LoadUint32(&o.MINTSTS.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetMINTSTS_SDIO_INTERRUPT_MSK() uint32 { + return (volatile.LoadUint32(&o.MINTSTS.Reg) & 0x30000) >> 16 +} + +// SDHOST.RINTSTS: Raw interrupt status register +func (o *SDHOST_Type) SetRINTSTS_INT_STATUS_RAW(value uint32) { + volatile.StoreUint32(&o.RINTSTS.Reg, volatile.LoadUint32(&o.RINTSTS.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetRINTSTS_INT_STATUS_RAW() uint32 { + return volatile.LoadUint32(&o.RINTSTS.Reg) & 0xffff +} +func (o *SDHOST_Type) SetRINTSTS_SDIO_INTERRUPT_RAW(value uint32) { + volatile.StoreUint32(&o.RINTSTS.Reg, volatile.LoadUint32(&o.RINTSTS.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetRINTSTS_SDIO_INTERRUPT_RAW() uint32 { + return (volatile.LoadUint32(&o.RINTSTS.Reg) & 0x30000) >> 16 +} + +// SDHOST.STATUS: SD/MMC status register +func (o *SDHOST_Type) SetSTATUS_FIFO_RX_WATERMARK(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_RX_WATERMARK() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_TX_WATERMARK(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_TX_WATERMARK() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *SDHOST_Type) SetSTATUS_COMMAND_FSM_STATES(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *SDHOST_Type) GetSTATUS_COMMAND_FSM_STATES() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf0) >> 4 +} +func (o *SDHOST_Type) SetSTATUS_DATA_3_STATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetSTATUS_DATA_3_STATUS() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetSTATUS_DATA_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetSTATUS_DATA_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetSTATUS_DATA_STATE_MC_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400)|value<<10) +} +func (o *SDHOST_Type) GetSTATUS_DATA_STATE_MC_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400) >> 10 +} +func (o *SDHOST_Type) SetSTATUS_RESPONSE_INDEX(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1f800)|value<<11) +} +func (o *SDHOST_Type) GetSTATUS_RESPONSE_INDEX() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1f800) >> 11 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_COUNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ffe0000)|value<<17) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_COUNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3ffe0000) >> 17 +} + +// SDHOST.FIFOTH: FIFO configuration register +func (o *SDHOST_Type) SetFIFOTH_TX_WMARK(value uint32) { + volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0xfff)|value) +} +func (o *SDHOST_Type) GetFIFOTH_TX_WMARK() uint32 { + return volatile.LoadUint32(&o.FIFOTH.Reg) & 0xfff +} +func (o *SDHOST_Type) SetFIFOTH_RX_WMARK(value uint32) { + volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0x7ff0000)|value<<16) +} +func (o *SDHOST_Type) GetFIFOTH_RX_WMARK() uint32 { + return (volatile.LoadUint32(&o.FIFOTH.Reg) & 0x7ff0000) >> 16 +} +func (o *SDHOST_Type) SetFIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE(value uint32) { + volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0x70000000)|value<<28) +} +func (o *SDHOST_Type) GetFIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE() uint32 { + return (volatile.LoadUint32(&o.FIFOTH.Reg) & 0x70000000) >> 28 +} + +// SDHOST.CDETECT: Card detect register +func (o *SDHOST_Type) SetCDETECT_CARD_DETECT_N(value uint32) { + volatile.StoreUint32(&o.CDETECT.Reg, volatile.LoadUint32(&o.CDETECT.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetCDETECT_CARD_DETECT_N() uint32 { + return volatile.LoadUint32(&o.CDETECT.Reg) & 0x3 +} + +// SDHOST.WRTPRT: Card write protection (WP) status register +func (o *SDHOST_Type) SetWRTPRT_WRITE_PROTECT(value uint32) { + volatile.StoreUint32(&o.WRTPRT.Reg, volatile.LoadUint32(&o.WRTPRT.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetWRTPRT_WRITE_PROTECT() uint32 { + return volatile.LoadUint32(&o.WRTPRT.Reg) & 0x3 +} + +// SDHOST.TCBCNT: Transferred byte count register +func (o *SDHOST_Type) SetTCBCNT(value uint32) { + volatile.StoreUint32(&o.TCBCNT.Reg, value) +} +func (o *SDHOST_Type) GetTCBCNT() uint32 { + return volatile.LoadUint32(&o.TCBCNT.Reg) +} + +// SDHOST.TBBCNT: Transferred byte count register +func (o *SDHOST_Type) SetTBBCNT(value uint32) { + volatile.StoreUint32(&o.TBBCNT.Reg, value) +} +func (o *SDHOST_Type) GetTBBCNT() uint32 { + return volatile.LoadUint32(&o.TBBCNT.Reg) +} + +// SDHOST.DEBNCE: Debounce filter time configuration register +func (o *SDHOST_Type) SetDEBNCE_DEBOUNCE_COUNT(value uint32) { + volatile.StoreUint32(&o.DEBNCE.Reg, volatile.LoadUint32(&o.DEBNCE.Reg)&^(0xffffff)|value) +} +func (o *SDHOST_Type) GetDEBNCE_DEBOUNCE_COUNT() uint32 { + return volatile.LoadUint32(&o.DEBNCE.Reg) & 0xffffff +} + +// SDHOST.USRID: User ID (scratchpad) register +func (o *SDHOST_Type) SetUSRID(value uint32) { + volatile.StoreUint32(&o.USRID.Reg, value) +} +func (o *SDHOST_Type) GetUSRID() uint32 { + return volatile.LoadUint32(&o.USRID.Reg) +} + +// SDHOST.VERID: Version ID (scratchpad) register +func (o *SDHOST_Type) SetVERID(value uint32) { + volatile.StoreUint32(&o.VERID.Reg, value) +} +func (o *SDHOST_Type) GetVERID() uint32 { + return volatile.LoadUint32(&o.VERID.Reg) +} + +// SDHOST.HCON: Hardware feature register +func (o *SDHOST_Type) SetHCON_CARD_TYPE(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetHCON_CARD_TYPE() uint32 { + return volatile.LoadUint32(&o.HCON.Reg) & 0x1 +} +func (o *SDHOST_Type) SetHCON_CARD_NUM(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x3e)|value<<1) +} +func (o *SDHOST_Type) GetHCON_CARD_NUM() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x3e) >> 1 +} +func (o *SDHOST_Type) SetHCON_BUS_TYPE(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x40)|value<<6) +} +func (o *SDHOST_Type) GetHCON_BUS_TYPE() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x40) >> 6 +} +func (o *SDHOST_Type) SetHCON_DATA_WIDTH(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x380)|value<<7) +} +func (o *SDHOST_Type) GetHCON_DATA_WIDTH() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x380) >> 7 +} +func (o *SDHOST_Type) SetHCON_ADDR_WIDTH(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0xfc00)|value<<10) +} +func (o *SDHOST_Type) GetHCON_ADDR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0xfc00) >> 10 +} +func (o *SDHOST_Type) SetHCON_DMA_WIDTH(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x1c0000)|value<<18) +} +func (o *SDHOST_Type) GetHCON_DMA_WIDTH() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x1c0000) >> 18 +} +func (o *SDHOST_Type) SetHCON_RAM_INDISE(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x200000)|value<<21) +} +func (o *SDHOST_Type) GetHCON_RAM_INDISE() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x200000) >> 21 +} +func (o *SDHOST_Type) SetHCON_HOLD(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x400000)|value<<22) +} +func (o *SDHOST_Type) GetHCON_HOLD() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x400000) >> 22 +} +func (o *SDHOST_Type) SetHCON_NUM_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x3000000)|value<<24) +} +func (o *SDHOST_Type) GetHCON_NUM_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x3000000) >> 24 +} + +// SDHOST.UHS: UHS-1 register +func (o *SDHOST_Type) SetUHS_DDR(value uint32) { + volatile.StoreUint32(&o.UHS.Reg, volatile.LoadUint32(&o.UHS.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetUHS_DDR() uint32 { + return (volatile.LoadUint32(&o.UHS.Reg) & 0x30000) >> 16 +} + +// SDHOST.RST_N: Card reset register +func (o *SDHOST_Type) SetRST_N_CARD_RESET(value uint32) { + volatile.StoreUint32(&o.RST_N.Reg, volatile.LoadUint32(&o.RST_N.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetRST_N_CARD_RESET() uint32 { + return volatile.LoadUint32(&o.RST_N.Reg) & 0x3 +} + +// SDHOST.BMOD: Burst mode transfer configuration register +func (o *SDHOST_Type) SetBMOD_SWR(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetBMOD_SWR() uint32 { + return volatile.LoadUint32(&o.BMOD.Reg) & 0x1 +} +func (o *SDHOST_Type) SetBMOD_FB(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetBMOD_FB() uint32 { + return (volatile.LoadUint32(&o.BMOD.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetBMOD_DE(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x80)|value<<7) +} +func (o *SDHOST_Type) GetBMOD_DE() uint32 { + return (volatile.LoadUint32(&o.BMOD.Reg) & 0x80) >> 7 +} +func (o *SDHOST_Type) SetBMOD_PBL(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x700)|value<<8) +} +func (o *SDHOST_Type) GetBMOD_PBL() uint32 { + return (volatile.LoadUint32(&o.BMOD.Reg) & 0x700) >> 8 +} + +// SDHOST.PLDMND: Poll demand configuration register +func (o *SDHOST_Type) SetPLDMND(value uint32) { + volatile.StoreUint32(&o.PLDMND.Reg, value) +} +func (o *SDHOST_Type) GetPLDMND() uint32 { + return volatile.LoadUint32(&o.PLDMND.Reg) +} + +// SDHOST.DBADDR: Descriptor base address register +func (o *SDHOST_Type) SetDBADDR(value uint32) { + volatile.StoreUint32(&o.DBADDR.Reg, value) +} +func (o *SDHOST_Type) GetDBADDR() uint32 { + return volatile.LoadUint32(&o.DBADDR.Reg) +} + +// SDHOST.IDSTS: IDMAC status register +func (o *SDHOST_Type) SetIDSTS_TI(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetIDSTS_TI() uint32 { + return volatile.LoadUint32(&o.IDSTS.Reg) & 0x1 +} +func (o *SDHOST_Type) SetIDSTS_RI(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetIDSTS_RI() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetIDSTS_FBE(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetIDSTS_FBE() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetIDSTS_DU(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x10)|value<<4) +} +func (o *SDHOST_Type) GetIDSTS_DU() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x10) >> 4 +} +func (o *SDHOST_Type) SetIDSTS_CES(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x20)|value<<5) +} +func (o *SDHOST_Type) GetIDSTS_CES() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x20) >> 5 +} +func (o *SDHOST_Type) SetIDSTS_NIS(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetIDSTS_NIS() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetIDSTS_AIS(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetIDSTS_AIS() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetIDSTS_FBE_CODE(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1c00)|value<<10) +} +func (o *SDHOST_Type) GetIDSTS_FBE_CODE() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x1c00) >> 10 +} +func (o *SDHOST_Type) SetIDSTS_FSM(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1e000)|value<<13) +} +func (o *SDHOST_Type) GetIDSTS_FSM() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x1e000) >> 13 +} + +// SDHOST.IDINTEN: IDMAC interrupt enable register +func (o *SDHOST_Type) SetIDINTEN_TI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetIDINTEN_TI() uint32 { + return volatile.LoadUint32(&o.IDINTEN.Reg) & 0x1 +} +func (o *SDHOST_Type) SetIDINTEN_RI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetIDINTEN_RI() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetIDINTEN_FBE(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetIDINTEN_FBE() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetIDINTEN_DU(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x10)|value<<4) +} +func (o *SDHOST_Type) GetIDINTEN_DU() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x10) >> 4 +} +func (o *SDHOST_Type) SetIDINTEN_CES(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x20)|value<<5) +} +func (o *SDHOST_Type) GetIDINTEN_CES() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x20) >> 5 +} +func (o *SDHOST_Type) SetIDINTEN_NI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetIDINTEN_NI() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetIDINTEN_AI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetIDINTEN_AI() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x200) >> 9 +} + +// SDHOST.DSCADDR: Host descriptor address pointer +func (o *SDHOST_Type) SetDSCADDR(value uint32) { + volatile.StoreUint32(&o.DSCADDR.Reg, value) +} +func (o *SDHOST_Type) GetDSCADDR() uint32 { + return volatile.LoadUint32(&o.DSCADDR.Reg) +} + +// SDHOST.BUFADDR: Host buffer address pointer register +func (o *SDHOST_Type) SetBUFADDR(value uint32) { + volatile.StoreUint32(&o.BUFADDR.Reg, value) +} +func (o *SDHOST_Type) GetBUFADDR() uint32 { + return volatile.LoadUint32(&o.BUFADDR.Reg) +} + +// SDHOST.CARDTHRCTL: Card Threshold Control register +func (o *SDHOST_Type) SetCARDTHRCTL_CARDRDTHREN(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDRDTHREN() uint32 { + return volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x1 +} +func (o *SDHOST_Type) SetCARDTHRCTL_CARDCLRINTEN(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDCLRINTEN() uint32 { + return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetCARDTHRCTL_CARDWRTHREN(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDWRTHREN() uint32 { + return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetCARDTHRCTL_CARDTHRESHOLD(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0xffff0000)|value<<16) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDTHRESHOLD() uint32 { + return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0xffff0000) >> 16 +} + +// SDHOST.EMMCDDR: eMMC DDR register +func (o *SDHOST_Type) SetEMMCDDR_HALFSTARTBIT(value uint32) { + volatile.StoreUint32(&o.EMMCDDR.Reg, volatile.LoadUint32(&o.EMMCDDR.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetEMMCDDR_HALFSTARTBIT() uint32 { + return volatile.LoadUint32(&o.EMMCDDR.Reg) & 0x3 +} +func (o *SDHOST_Type) SetEMMCDDR_HS400_MODE(value uint32) { + volatile.StoreUint32(&o.EMMCDDR.Reg, volatile.LoadUint32(&o.EMMCDDR.Reg)&^(0x80000000)|value<<31) +} +func (o *SDHOST_Type) GetEMMCDDR_HS400_MODE() uint32 { + return (volatile.LoadUint32(&o.EMMCDDR.Reg) & 0x80000000) >> 31 +} + +// SDHOST.ENSHIFT: Enable Phase Shift register +func (o *SDHOST_Type) SetENSHIFT_ENABLE_SHIFT(value uint32) { + volatile.StoreUint32(&o.ENSHIFT.Reg, volatile.LoadUint32(&o.ENSHIFT.Reg)&^(0xf)|value) +} +func (o *SDHOST_Type) GetENSHIFT_ENABLE_SHIFT() uint32 { + return volatile.LoadUint32(&o.ENSHIFT.Reg) & 0xf +} + +// SDHOST.BUFFIFO: CPU write and read transmit data by FIFO +func (o *SDHOST_Type) SetBUFFIFO(value uint32) { + volatile.StoreUint32(&o.BUFFIFO.Reg, value) +} +func (o *SDHOST_Type) GetBUFFIFO() uint32 { + return volatile.LoadUint32(&o.BUFFIFO.Reg) +} + +// SDHOST.CLK_EDGE_SEL: SDIO control register. +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x7)|value) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL() uint32 { + return volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x7 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x38)|value<<3) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x38) >> 3 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1c0)|value<<6) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1c0) >> 6 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_H(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e00)|value<<9) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_H() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e00) >> 9 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_L(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e000)|value<<13) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_L() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e000) >> 13 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_N(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e0000)|value<<17) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_N() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e0000) >> 17 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_ESDIO_MODE(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x200000)|value<<21) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_ESDIO_MODE() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x200000) >> 21 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_ESD_MODE(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x400000)|value<<22) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_ESD_MODE() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x400000) >> 22 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x800000)|value<<23) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x800000) >> 23 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_ULTRA_HIGH_SPEED_MODE(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1000000)|value<<24) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_ULTRA_HIGH_SPEED_MODE() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1000000) >> 24 +} + +// SDHOST.RAW_INTS: SDIO raw ints register. +func (o *SDHOST_Type) SetRAW_INTS(value uint32) { + volatile.StoreUint32(&o.RAW_INTS.Reg, value) +} +func (o *SDHOST_Type) GetRAW_INTS() uint32 { + return volatile.LoadUint32(&o.RAW_INTS.Reg) +} + +// SDHOST.DLL_CLK_CONF: SDIO DLL clock control register. +func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_SLF_EN(value uint32) { + volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_SLF_EN() uint32 { + return volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x1 +} +func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_DRV_EN(value uint32) { + volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_DRV_EN() uint32 { + return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_SAM_EN(value uint32) { + volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_SAM_EN() uint32 { + return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_SLF_PHASE(value uint32) { + volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x1f8)|value<<3) +} +func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_SLF_PHASE() uint32 { + return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x1f8) >> 3 +} +func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_DRV_PHASE(value uint32) { + volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x7e00)|value<<9) +} +func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_DRV_PHASE() uint32 { + return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x7e00) >> 9 +} +func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_SAM_PHASE(value uint32) { + volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x1f8000)|value<<15) +} +func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_SAM_PHASE() uint32 { + return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x1f8000) >> 15 +} + +// SDHOST.DLL_CONF: SDIO DLL configuration register. +func (o *SDHOST_Type) SetDLL_CONF_DLL_CAL_STOP(value uint32) { + volatile.StoreUint32(&o.DLL_CONF.Reg, volatile.LoadUint32(&o.DLL_CONF.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetDLL_CONF_DLL_CAL_STOP() uint32 { + return volatile.LoadUint32(&o.DLL_CONF.Reg) & 0x1 +} +func (o *SDHOST_Type) SetDLL_CONF_DLL_CAL_END(value uint32) { + volatile.StoreUint32(&o.DLL_CONF.Reg, volatile.LoadUint32(&o.DLL_CONF.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetDLL_CONF_DLL_CAL_END() uint32 { + return (volatile.LoadUint32(&o.DLL_CONF.Reg) & 0x2) >> 1 +} + +// SHA (Secure Hash Algorithm) Accelerator +type SHA_Type struct { + MODE volatile.Register32 // 0x0 + T_STRING volatile.Register32 // 0x4 + T_LENGTH volatile.Register32 // 0x8 + DMA_BLOCK_NUM volatile.Register32 // 0xC + START volatile.Register32 // 0x10 + CONTINUE volatile.Register32 // 0x14 + BUSY volatile.Register32 // 0x18 + DMA_START volatile.Register32 // 0x1C + DMA_CONTINUE volatile.Register32 // 0x20 + CLEAR_IRQ volatile.Register32 // 0x24 + IRQ_ENA volatile.Register32 // 0x28 + DATE volatile.Register32 // 0x2C + _ [16]byte + H_MEM [16]volatile.Register32 // 0x40 + M_MEM [16]volatile.Register32 // 0x80 +} + +// SHA.MODE: Initial configuration register. +func (o *SHA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *SHA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// SHA.T_STRING: SHA 512/t configuration register 0. +func (o *SHA_Type) SetT_STRING(value uint32) { + volatile.StoreUint32(&o.T_STRING.Reg, value) +} +func (o *SHA_Type) GetT_STRING() uint32 { + return volatile.LoadUint32(&o.T_STRING.Reg) +} + +// SHA.T_LENGTH: SHA 512/t configuration register 1. +func (o *SHA_Type) SetT_LENGTH(value uint32) { + volatile.StoreUint32(&o.T_LENGTH.Reg, volatile.LoadUint32(&o.T_LENGTH.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetT_LENGTH() uint32 { + return volatile.LoadUint32(&o.T_LENGTH.Reg) & 0x3f +} + +// SHA.DMA_BLOCK_NUM: DMA configuration register 0. +func (o *SHA_Type) SetDMA_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_NUM.Reg, volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetDMA_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg) & 0x3f +} + +// SHA.START: Typical SHA configuration register 0. +func (o *SHA_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetSTART() uint32 { + return (volatile.LoadUint32(&o.START.Reg) & 0xfffffffe) >> 1 +} + +// SHA.CONTINUE: Typical SHA configuration register 1. +func (o *SHA_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetCONTINUE() uint32 { + return (volatile.LoadUint32(&o.CONTINUE.Reg) & 0xfffffffe) >> 1 +} + +// SHA.BUSY: Busy register. +func (o *SHA_Type) SetBUSY_STATE(value uint32) { + volatile.StoreUint32(&o.BUSY.Reg, volatile.LoadUint32(&o.BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetBUSY_STATE() uint32 { + return volatile.LoadUint32(&o.BUSY.Reg) & 0x1 +} + +// SHA.DMA_START: DMA configuration register 1. +func (o *SHA_Type) SetDMA_START(value uint32) { + volatile.StoreUint32(&o.DMA_START.Reg, volatile.LoadUint32(&o.DMA_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_START() uint32 { + return volatile.LoadUint32(&o.DMA_START.Reg) & 0x1 +} + +// SHA.DMA_CONTINUE: DMA configuration register 2. +func (o *SHA_Type) SetDMA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.DMA_CONTINUE.Reg, volatile.LoadUint32(&o.DMA_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_CONTINUE() uint32 { + return volatile.LoadUint32(&o.DMA_CONTINUE.Reg) & 0x1 +} + +// SHA.CLEAR_IRQ: Interrupt clear register. +func (o *SHA_Type) SetCLEAR_IRQ_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CLEAR_IRQ.Reg, volatile.LoadUint32(&o.CLEAR_IRQ.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetCLEAR_IRQ_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.CLEAR_IRQ.Reg) & 0x1 +} + +// SHA.IRQ_ENA: Interrupt enable register. +func (o *SHA_Type) SetIRQ_ENA_INTERRUPT_ENA(value uint32) { + volatile.StoreUint32(&o.IRQ_ENA.Reg, volatile.LoadUint32(&o.IRQ_ENA.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetIRQ_ENA_INTERRUPT_ENA() uint32 { + return volatile.LoadUint32(&o.IRQ_ENA.Reg) & 0x1 +} + +// SHA.DATE: Date register. +func (o *SHA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SHA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Event Task Matrix +type SOC_ETM_Type struct { + CH_ENA_AD0 volatile.Register32 // 0x0 + CH_ENA_AD0_SET volatile.Register32 // 0x4 + CH_ENA_AD0_CLR volatile.Register32 // 0x8 + CH_ENA_AD1 volatile.Register32 // 0xC + CH_ENA_AD1_SET volatile.Register32 // 0x10 + CH_ENA_AD1_CLR volatile.Register32 // 0x14 + CH0_EVT_ID volatile.Register32 // 0x18 + CH0_TASK_ID volatile.Register32 // 0x1C + CH1_EVT_ID volatile.Register32 // 0x20 + CH1_TASK_ID volatile.Register32 // 0x24 + CH2_EVT_ID volatile.Register32 // 0x28 + CH2_TASK_ID volatile.Register32 // 0x2C + CH3_EVT_ID volatile.Register32 // 0x30 + CH3_TASK_ID volatile.Register32 // 0x34 + CH4_EVT_ID volatile.Register32 // 0x38 + CH4_TASK_ID volatile.Register32 // 0x3C + CH5_EVT_ID volatile.Register32 // 0x40 + CH5_TASK_ID volatile.Register32 // 0x44 + CH6_EVT_ID volatile.Register32 // 0x48 + CH6_TASK_ID volatile.Register32 // 0x4C + CH7_EVT_ID volatile.Register32 // 0x50 + CH7_TASK_ID volatile.Register32 // 0x54 + CH8_EVT_ID volatile.Register32 // 0x58 + CH8_TASK_ID volatile.Register32 // 0x5C + CH9_EVT_ID volatile.Register32 // 0x60 + CH9_TASK_ID volatile.Register32 // 0x64 + CH10_EVT_ID volatile.Register32 // 0x68 + CH10_TASK_ID volatile.Register32 // 0x6C + CH11_EVT_ID volatile.Register32 // 0x70 + CH11_TASK_ID volatile.Register32 // 0x74 + CH12_EVT_ID volatile.Register32 // 0x78 + CH12_TASK_ID volatile.Register32 // 0x7C + CH13_EVT_ID volatile.Register32 // 0x80 + CH13_TASK_ID volatile.Register32 // 0x84 + CH14_EVT_ID volatile.Register32 // 0x88 + CH14_TASK_ID volatile.Register32 // 0x8C + CH15_EVT_ID volatile.Register32 // 0x90 + CH15_TASK_ID volatile.Register32 // 0x94 + CH16_EVT_ID volatile.Register32 // 0x98 + CH16_TASK_ID volatile.Register32 // 0x9C + CH17_EVT_ID volatile.Register32 // 0xA0 + CH17_TASK_ID volatile.Register32 // 0xA4 + CH18_EVT_ID volatile.Register32 // 0xA8 + CH18_TASK_ID volatile.Register32 // 0xAC + CH19_EVT_ID volatile.Register32 // 0xB0 + CH19_TASK_ID volatile.Register32 // 0xB4 + CH20_EVT_ID volatile.Register32 // 0xB8 + CH20_TASK_ID volatile.Register32 // 0xBC + CH21_EVT_ID volatile.Register32 // 0xC0 + CH21_TASK_ID volatile.Register32 // 0xC4 + CH22_EVT_ID volatile.Register32 // 0xC8 + CH22_TASK_ID volatile.Register32 // 0xCC + CH23_EVT_ID volatile.Register32 // 0xD0 + CH23_TASK_ID volatile.Register32 // 0xD4 + CH24_EVT_ID volatile.Register32 // 0xD8 + CH24_TASK_ID volatile.Register32 // 0xDC + CH25_EVT_ID volatile.Register32 // 0xE0 + CH25_TASK_ID volatile.Register32 // 0xE4 + CH26_EVT_ID volatile.Register32 // 0xE8 + CH26_TASK_ID volatile.Register32 // 0xEC + CH27_EVT_ID volatile.Register32 // 0xF0 + CH27_TASK_ID volatile.Register32 // 0xF4 + CH28_EVT_ID volatile.Register32 // 0xF8 + CH28_TASK_ID volatile.Register32 // 0xFC + CH29_EVT_ID volatile.Register32 // 0x100 + CH29_TASK_ID volatile.Register32 // 0x104 + CH30_EVT_ID volatile.Register32 // 0x108 + CH30_TASK_ID volatile.Register32 // 0x10C + CH31_EVT_ID volatile.Register32 // 0x110 + CH31_TASK_ID volatile.Register32 // 0x114 + CH32_EVT_ID volatile.Register32 // 0x118 + CH32_TASK_ID volatile.Register32 // 0x11C + CH33_EVT_ID volatile.Register32 // 0x120 + CH33_TASK_ID volatile.Register32 // 0x124 + CH34_EVT_ID volatile.Register32 // 0x128 + CH34_TASK_ID volatile.Register32 // 0x12C + CH35_EVT_ID volatile.Register32 // 0x130 + CH35_TASK_ID volatile.Register32 // 0x134 + CH36_EVT_ID volatile.Register32 // 0x138 + CH36_TASK_ID volatile.Register32 // 0x13C + CH37_EVT_ID volatile.Register32 // 0x140 + CH37_TASK_ID volatile.Register32 // 0x144 + CH38_EVT_ID volatile.Register32 // 0x148 + CH38_TASK_ID volatile.Register32 // 0x14C + CH39_EVT_ID volatile.Register32 // 0x150 + CH39_TASK_ID volatile.Register32 // 0x154 + CH40_EVT_ID volatile.Register32 // 0x158 + CH40_TASK_ID volatile.Register32 // 0x15C + CH41_EVT_ID volatile.Register32 // 0x160 + CH41_TASK_ID volatile.Register32 // 0x164 + CH42_EVT_ID volatile.Register32 // 0x168 + CH42_TASK_ID volatile.Register32 // 0x16C + CH43_EVT_ID volatile.Register32 // 0x170 + CH43_TASK_ID volatile.Register32 // 0x174 + CH44_EVT_ID volatile.Register32 // 0x178 + CH44_TASK_ID volatile.Register32 // 0x17C + CH45_EVT_ID volatile.Register32 // 0x180 + CH45_TASK_ID volatile.Register32 // 0x184 + CH46_EVT_ID volatile.Register32 // 0x188 + CH46_TASK_ID volatile.Register32 // 0x18C + CH47_EVT_ID volatile.Register32 // 0x190 + CH47_TASK_ID volatile.Register32 // 0x194 + CH48_EVT_ID volatile.Register32 // 0x198 + CH48_TASK_ID volatile.Register32 // 0x19C + CH49_EVT_ID volatile.Register32 // 0x1A0 + CH49_TASK_ID volatile.Register32 // 0x1A4 + EVT_ST0 volatile.Register32 // 0x1A8 + EVT_ST0_CLR volatile.Register32 // 0x1AC + EVT_ST1 volatile.Register32 // 0x1B0 + EVT_ST1_CLR volatile.Register32 // 0x1B4 + EVT_ST2 volatile.Register32 // 0x1B8 + EVT_ST2_CLR volatile.Register32 // 0x1BC + EVT_ST3 volatile.Register32 // 0x1C0 + EVT_ST3_CLR volatile.Register32 // 0x1C4 + EVT_ST4 volatile.Register32 // 0x1C8 + EVT_ST4_CLR volatile.Register32 // 0x1CC + EVT_ST5 volatile.Register32 // 0x1D0 + EVT_ST5_CLR volatile.Register32 // 0x1D4 + EVT_ST6 volatile.Register32 // 0x1D8 + EVT_ST6_CLR volatile.Register32 // 0x1DC + EVT_ST7 volatile.Register32 // 0x1E0 + EVT_ST7_CLR volatile.Register32 // 0x1E4 + TASK_ST0 volatile.Register32 // 0x1E8 + TASK_ST0_CLR volatile.Register32 // 0x1EC + TASK_ST1 volatile.Register32 // 0x1F0 + TASK_ST1_CLR volatile.Register32 // 0x1F4 + TASK_ST2 volatile.Register32 // 0x1F8 + TASK_ST2_CLR volatile.Register32 // 0x1FC + TASK_ST3 volatile.Register32 // 0x200 + TASK_ST3_CLR volatile.Register32 // 0x204 + TASK_ST4 volatile.Register32 // 0x208 + TASK_ST4_CLR volatile.Register32 // 0x20C + TASK_ST5 volatile.Register32 // 0x210 + TASK_ST5_CLR volatile.Register32 // 0x214 + TASK_ST6 volatile.Register32 // 0x218 + TASK_ST6_CLR volatile.Register32 // 0x21C + CLK_EN volatile.Register32 // 0x220 + DATE volatile.Register32 // 0x224 +} + +// SOC_ETM.CH_ENA_AD0: Channel enable status register +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA0(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA0() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA1(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA1() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA2(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA2() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA3(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA3() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA4(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA4() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA5(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA5() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA6(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA6() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA7(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA7() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA8(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA8() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA9(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA9() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA10(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA10() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA11(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA11() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA12(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA12() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA13(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA13() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA14(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA14() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA15(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA15() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA16(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA16() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA17(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA17() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA18(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA18() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA19(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA19() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA20(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA20() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA21(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA21() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA22(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA22() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA23(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA23() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA24(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA24() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA25(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA25() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA26(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA26() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA27(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA27() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA28(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA28() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA29(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA29() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA30(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA30() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA31(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA31() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.CH_ENA_AD0_SET: Channel enable set register +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET0(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET0() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET1(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET1() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET2(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET2() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET3(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET3() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET4(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET4() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET5(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET5() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET6(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET6() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET7(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET7() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET8(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET8() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET9(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET9() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET10(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET10() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET11(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET11() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET12(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET12() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET13(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET13() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET14(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET14() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET15(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET15() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET16(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET16() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET17(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET17() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET18(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET18() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET19(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET19() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET20(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET20() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET21(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET21() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET22(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET22() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET23(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET23() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET24(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET24() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET25(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET25() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET26(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET26() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET27(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET27() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET28(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET28() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET29(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET29() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET30(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET30() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET31(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET31() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.CH_ENA_AD0_CLR: Channel enable clear register +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR0(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR0() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR1(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR1() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR2(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR2() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR3(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR3() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR4(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR4() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR5(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR5() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR6(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR6() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR7(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR7() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR8(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR8() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR9(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR9() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR10(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR10() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR11(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR11() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR12(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR12() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR13(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR13() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR14(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR14() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR15(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR15() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR16(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR16() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR17(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR17() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR18(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR18() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR19(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR19() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR20(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR20() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR21(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR21() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR22(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR22() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR23(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR23() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR24(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR24() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR25(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR25() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR26(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR26() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR27(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR27() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR28(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR28() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR29(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR29() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR30(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR30() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR31(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR31() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.CH_ENA_AD1: Channel enable status register +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA32(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA32() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA33(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA33() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA34(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA34() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA35(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA35() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA36(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA36() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA37(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA37() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA38(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA38() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA39(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA39() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA40(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA40() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA41(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA41() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA42(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA42() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA43(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA43() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA44(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA44() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA45(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA45() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA46(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA46() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA47(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA47() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA48(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA48() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA49(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA49() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x20000) >> 17 +} + +// SOC_ETM.CH_ENA_AD1_SET: Channel enable set register +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET32(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET32() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET33(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET33() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET34(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET34() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET35(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET35() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET36(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET36() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET37(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET37() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET38(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET38() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET39(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET39() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET40(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET40() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET41(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET41() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET42(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET42() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET43(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET43() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET44(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET44() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET45(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET45() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET46(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET46() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET47(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET47() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET48(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET48() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET49(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET49() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x20000) >> 17 +} + +// SOC_ETM.CH_ENA_AD1_CLR: Channel enable clear register +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR32(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR32() uint32 { + return volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR33(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR33() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR34(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR34() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR35(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR35() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR36(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR36() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR37(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR37() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR38(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR38() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR39(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR39() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR40(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR40() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR41(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR41() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR42(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR42() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR43(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR43() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR44(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR44() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR45(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR45() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR46(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR46() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR47(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR47() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR48(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR48() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR49(value uint32) { + volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR49() uint32 { + return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x20000) >> 17 +} + +// SOC_ETM.CH0_EVT_ID: Channel0 event id register +func (o *SOC_ETM_Type) SetCH0_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH0_EVT_ID.Reg, volatile.LoadUint32(&o.CH0_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH0_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH0_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH0_TASK_ID: Channel0 task id register +func (o *SOC_ETM_Type) SetCH0_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH0_TASK_ID.Reg, volatile.LoadUint32(&o.CH0_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH0_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH0_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH1_EVT_ID: Channel1 event id register +func (o *SOC_ETM_Type) SetCH1_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH1_EVT_ID.Reg, volatile.LoadUint32(&o.CH1_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH1_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH1_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH1_TASK_ID: Channel1 task id register +func (o *SOC_ETM_Type) SetCH1_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH1_TASK_ID.Reg, volatile.LoadUint32(&o.CH1_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH1_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH1_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH2_EVT_ID: Channel2 event id register +func (o *SOC_ETM_Type) SetCH2_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH2_EVT_ID.Reg, volatile.LoadUint32(&o.CH2_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH2_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH2_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH2_TASK_ID: Channel2 task id register +func (o *SOC_ETM_Type) SetCH2_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH2_TASK_ID.Reg, volatile.LoadUint32(&o.CH2_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH2_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH2_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH3_EVT_ID: Channel3 event id register +func (o *SOC_ETM_Type) SetCH3_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH3_EVT_ID.Reg, volatile.LoadUint32(&o.CH3_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH3_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH3_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH3_TASK_ID: Channel3 task id register +func (o *SOC_ETM_Type) SetCH3_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH3_TASK_ID.Reg, volatile.LoadUint32(&o.CH3_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH3_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH3_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH4_EVT_ID: Channel4 event id register +func (o *SOC_ETM_Type) SetCH4_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH4_EVT_ID.Reg, volatile.LoadUint32(&o.CH4_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH4_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH4_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH4_TASK_ID: Channel4 task id register +func (o *SOC_ETM_Type) SetCH4_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH4_TASK_ID.Reg, volatile.LoadUint32(&o.CH4_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH4_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH4_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH5_EVT_ID: Channel5 event id register +func (o *SOC_ETM_Type) SetCH5_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH5_EVT_ID.Reg, volatile.LoadUint32(&o.CH5_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH5_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH5_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH5_TASK_ID: Channel5 task id register +func (o *SOC_ETM_Type) SetCH5_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH5_TASK_ID.Reg, volatile.LoadUint32(&o.CH5_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH5_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH5_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH6_EVT_ID: Channel6 event id register +func (o *SOC_ETM_Type) SetCH6_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH6_EVT_ID.Reg, volatile.LoadUint32(&o.CH6_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH6_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH6_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH6_TASK_ID: Channel6 task id register +func (o *SOC_ETM_Type) SetCH6_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH6_TASK_ID.Reg, volatile.LoadUint32(&o.CH6_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH6_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH6_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH7_EVT_ID: Channel7 event id register +func (o *SOC_ETM_Type) SetCH7_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH7_EVT_ID.Reg, volatile.LoadUint32(&o.CH7_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH7_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH7_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH7_TASK_ID: Channel7 task id register +func (o *SOC_ETM_Type) SetCH7_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH7_TASK_ID.Reg, volatile.LoadUint32(&o.CH7_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH7_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH7_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH8_EVT_ID: Channel8 event id register +func (o *SOC_ETM_Type) SetCH8_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH8_EVT_ID.Reg, volatile.LoadUint32(&o.CH8_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH8_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH8_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH8_TASK_ID: Channel8 task id register +func (o *SOC_ETM_Type) SetCH8_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH8_TASK_ID.Reg, volatile.LoadUint32(&o.CH8_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH8_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH8_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH9_EVT_ID: Channel9 event id register +func (o *SOC_ETM_Type) SetCH9_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH9_EVT_ID.Reg, volatile.LoadUint32(&o.CH9_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH9_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH9_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH9_TASK_ID: Channel9 task id register +func (o *SOC_ETM_Type) SetCH9_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH9_TASK_ID.Reg, volatile.LoadUint32(&o.CH9_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH9_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH9_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH10_EVT_ID: Channel10 event id register +func (o *SOC_ETM_Type) SetCH10_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH10_EVT_ID.Reg, volatile.LoadUint32(&o.CH10_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH10_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH10_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH10_TASK_ID: Channel10 task id register +func (o *SOC_ETM_Type) SetCH10_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH10_TASK_ID.Reg, volatile.LoadUint32(&o.CH10_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH10_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH10_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH11_EVT_ID: Channel11 event id register +func (o *SOC_ETM_Type) SetCH11_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH11_EVT_ID.Reg, volatile.LoadUint32(&o.CH11_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH11_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH11_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH11_TASK_ID: Channel11 task id register +func (o *SOC_ETM_Type) SetCH11_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH11_TASK_ID.Reg, volatile.LoadUint32(&o.CH11_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH11_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH11_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH12_EVT_ID: Channel12 event id register +func (o *SOC_ETM_Type) SetCH12_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH12_EVT_ID.Reg, volatile.LoadUint32(&o.CH12_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH12_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH12_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH12_TASK_ID: Channel12 task id register +func (o *SOC_ETM_Type) SetCH12_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH12_TASK_ID.Reg, volatile.LoadUint32(&o.CH12_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH12_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH12_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH13_EVT_ID: Channel13 event id register +func (o *SOC_ETM_Type) SetCH13_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH13_EVT_ID.Reg, volatile.LoadUint32(&o.CH13_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH13_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH13_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH13_TASK_ID: Channel13 task id register +func (o *SOC_ETM_Type) SetCH13_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH13_TASK_ID.Reg, volatile.LoadUint32(&o.CH13_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH13_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH13_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH14_EVT_ID: Channel14 event id register +func (o *SOC_ETM_Type) SetCH14_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH14_EVT_ID.Reg, volatile.LoadUint32(&o.CH14_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH14_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH14_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH14_TASK_ID: Channel14 task id register +func (o *SOC_ETM_Type) SetCH14_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH14_TASK_ID.Reg, volatile.LoadUint32(&o.CH14_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH14_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH14_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH15_EVT_ID: Channel15 event id register +func (o *SOC_ETM_Type) SetCH15_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH15_EVT_ID.Reg, volatile.LoadUint32(&o.CH15_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH15_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH15_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH15_TASK_ID: Channel15 task id register +func (o *SOC_ETM_Type) SetCH15_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH15_TASK_ID.Reg, volatile.LoadUint32(&o.CH15_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH15_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH15_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH16_EVT_ID: Channel16 event id register +func (o *SOC_ETM_Type) SetCH16_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH16_EVT_ID.Reg, volatile.LoadUint32(&o.CH16_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH16_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH16_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH16_TASK_ID: Channel16 task id register +func (o *SOC_ETM_Type) SetCH16_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH16_TASK_ID.Reg, volatile.LoadUint32(&o.CH16_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH16_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH16_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH17_EVT_ID: Channel17 event id register +func (o *SOC_ETM_Type) SetCH17_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH17_EVT_ID.Reg, volatile.LoadUint32(&o.CH17_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH17_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH17_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH17_TASK_ID: Channel17 task id register +func (o *SOC_ETM_Type) SetCH17_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH17_TASK_ID.Reg, volatile.LoadUint32(&o.CH17_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH17_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH17_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH18_EVT_ID: Channel18 event id register +func (o *SOC_ETM_Type) SetCH18_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH18_EVT_ID.Reg, volatile.LoadUint32(&o.CH18_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH18_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH18_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH18_TASK_ID: Channel18 task id register +func (o *SOC_ETM_Type) SetCH18_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH18_TASK_ID.Reg, volatile.LoadUint32(&o.CH18_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH18_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH18_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH19_EVT_ID: Channel19 event id register +func (o *SOC_ETM_Type) SetCH19_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH19_EVT_ID.Reg, volatile.LoadUint32(&o.CH19_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH19_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH19_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH19_TASK_ID: Channel19 task id register +func (o *SOC_ETM_Type) SetCH19_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH19_TASK_ID.Reg, volatile.LoadUint32(&o.CH19_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH19_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH19_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH20_EVT_ID: Channel20 event id register +func (o *SOC_ETM_Type) SetCH20_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH20_EVT_ID.Reg, volatile.LoadUint32(&o.CH20_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH20_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH20_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH20_TASK_ID: Channel20 task id register +func (o *SOC_ETM_Type) SetCH20_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH20_TASK_ID.Reg, volatile.LoadUint32(&o.CH20_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH20_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH20_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH21_EVT_ID: Channel21 event id register +func (o *SOC_ETM_Type) SetCH21_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH21_EVT_ID.Reg, volatile.LoadUint32(&o.CH21_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH21_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH21_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH21_TASK_ID: Channel21 task id register +func (o *SOC_ETM_Type) SetCH21_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH21_TASK_ID.Reg, volatile.LoadUint32(&o.CH21_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH21_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH21_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH22_EVT_ID: Channel22 event id register +func (o *SOC_ETM_Type) SetCH22_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH22_EVT_ID.Reg, volatile.LoadUint32(&o.CH22_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH22_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH22_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH22_TASK_ID: Channel22 task id register +func (o *SOC_ETM_Type) SetCH22_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH22_TASK_ID.Reg, volatile.LoadUint32(&o.CH22_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH22_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH22_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH23_EVT_ID: Channel23 event id register +func (o *SOC_ETM_Type) SetCH23_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH23_EVT_ID.Reg, volatile.LoadUint32(&o.CH23_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH23_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH23_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH23_TASK_ID: Channel23 task id register +func (o *SOC_ETM_Type) SetCH23_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH23_TASK_ID.Reg, volatile.LoadUint32(&o.CH23_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH23_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH23_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH24_EVT_ID: Channel24 event id register +func (o *SOC_ETM_Type) SetCH24_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH24_EVT_ID.Reg, volatile.LoadUint32(&o.CH24_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH24_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH24_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH24_TASK_ID: Channel24 task id register +func (o *SOC_ETM_Type) SetCH24_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH24_TASK_ID.Reg, volatile.LoadUint32(&o.CH24_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH24_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH24_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH25_EVT_ID: Channel25 event id register +func (o *SOC_ETM_Type) SetCH25_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH25_EVT_ID.Reg, volatile.LoadUint32(&o.CH25_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH25_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH25_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH25_TASK_ID: Channel25 task id register +func (o *SOC_ETM_Type) SetCH25_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH25_TASK_ID.Reg, volatile.LoadUint32(&o.CH25_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH25_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH25_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH26_EVT_ID: Channel26 event id register +func (o *SOC_ETM_Type) SetCH26_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH26_EVT_ID.Reg, volatile.LoadUint32(&o.CH26_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH26_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH26_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH26_TASK_ID: Channel26 task id register +func (o *SOC_ETM_Type) SetCH26_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH26_TASK_ID.Reg, volatile.LoadUint32(&o.CH26_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH26_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH26_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH27_EVT_ID: Channel27 event id register +func (o *SOC_ETM_Type) SetCH27_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH27_EVT_ID.Reg, volatile.LoadUint32(&o.CH27_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH27_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH27_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH27_TASK_ID: Channel27 task id register +func (o *SOC_ETM_Type) SetCH27_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH27_TASK_ID.Reg, volatile.LoadUint32(&o.CH27_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH27_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH27_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH28_EVT_ID: Channel28 event id register +func (o *SOC_ETM_Type) SetCH28_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH28_EVT_ID.Reg, volatile.LoadUint32(&o.CH28_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH28_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH28_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH28_TASK_ID: Channel28 task id register +func (o *SOC_ETM_Type) SetCH28_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH28_TASK_ID.Reg, volatile.LoadUint32(&o.CH28_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH28_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH28_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH29_EVT_ID: Channel29 event id register +func (o *SOC_ETM_Type) SetCH29_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH29_EVT_ID.Reg, volatile.LoadUint32(&o.CH29_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH29_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH29_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH29_TASK_ID: Channel29 task id register +func (o *SOC_ETM_Type) SetCH29_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH29_TASK_ID.Reg, volatile.LoadUint32(&o.CH29_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH29_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH29_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH30_EVT_ID: Channel30 event id register +func (o *SOC_ETM_Type) SetCH30_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH30_EVT_ID.Reg, volatile.LoadUint32(&o.CH30_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH30_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH30_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH30_TASK_ID: Channel30 task id register +func (o *SOC_ETM_Type) SetCH30_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH30_TASK_ID.Reg, volatile.LoadUint32(&o.CH30_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH30_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH30_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH31_EVT_ID: Channel31 event id register +func (o *SOC_ETM_Type) SetCH31_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH31_EVT_ID.Reg, volatile.LoadUint32(&o.CH31_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH31_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH31_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH31_TASK_ID: Channel31 task id register +func (o *SOC_ETM_Type) SetCH31_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH31_TASK_ID.Reg, volatile.LoadUint32(&o.CH31_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH31_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH31_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH32_EVT_ID: Channel32 event id register +func (o *SOC_ETM_Type) SetCH32_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH32_EVT_ID.Reg, volatile.LoadUint32(&o.CH32_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH32_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH32_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH32_TASK_ID: Channel32 task id register +func (o *SOC_ETM_Type) SetCH32_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH32_TASK_ID.Reg, volatile.LoadUint32(&o.CH32_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH32_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH32_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH33_EVT_ID: Channel33 event id register +func (o *SOC_ETM_Type) SetCH33_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH33_EVT_ID.Reg, volatile.LoadUint32(&o.CH33_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH33_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH33_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH33_TASK_ID: Channel33 task id register +func (o *SOC_ETM_Type) SetCH33_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH33_TASK_ID.Reg, volatile.LoadUint32(&o.CH33_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH33_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH33_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH34_EVT_ID: Channel34 event id register +func (o *SOC_ETM_Type) SetCH34_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH34_EVT_ID.Reg, volatile.LoadUint32(&o.CH34_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH34_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH34_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH34_TASK_ID: Channel34 task id register +func (o *SOC_ETM_Type) SetCH34_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH34_TASK_ID.Reg, volatile.LoadUint32(&o.CH34_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH34_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH34_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH35_EVT_ID: Channel35 event id register +func (o *SOC_ETM_Type) SetCH35_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH35_EVT_ID.Reg, volatile.LoadUint32(&o.CH35_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH35_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH35_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH35_TASK_ID: Channel35 task id register +func (o *SOC_ETM_Type) SetCH35_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH35_TASK_ID.Reg, volatile.LoadUint32(&o.CH35_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH35_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH35_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH36_EVT_ID: Channel36 event id register +func (o *SOC_ETM_Type) SetCH36_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH36_EVT_ID.Reg, volatile.LoadUint32(&o.CH36_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH36_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH36_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH36_TASK_ID: Channel36 task id register +func (o *SOC_ETM_Type) SetCH36_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH36_TASK_ID.Reg, volatile.LoadUint32(&o.CH36_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH36_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH36_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH37_EVT_ID: Channel37 event id register +func (o *SOC_ETM_Type) SetCH37_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH37_EVT_ID.Reg, volatile.LoadUint32(&o.CH37_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH37_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH37_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH37_TASK_ID: Channel37 task id register +func (o *SOC_ETM_Type) SetCH37_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH37_TASK_ID.Reg, volatile.LoadUint32(&o.CH37_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH37_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH37_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH38_EVT_ID: Channel38 event id register +func (o *SOC_ETM_Type) SetCH38_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH38_EVT_ID.Reg, volatile.LoadUint32(&o.CH38_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH38_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH38_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH38_TASK_ID: Channel38 task id register +func (o *SOC_ETM_Type) SetCH38_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH38_TASK_ID.Reg, volatile.LoadUint32(&o.CH38_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH38_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH38_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH39_EVT_ID: Channel39 event id register +func (o *SOC_ETM_Type) SetCH39_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH39_EVT_ID.Reg, volatile.LoadUint32(&o.CH39_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH39_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH39_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH39_TASK_ID: Channel39 task id register +func (o *SOC_ETM_Type) SetCH39_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH39_TASK_ID.Reg, volatile.LoadUint32(&o.CH39_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH39_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH39_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH40_EVT_ID: Channel40 event id register +func (o *SOC_ETM_Type) SetCH40_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH40_EVT_ID.Reg, volatile.LoadUint32(&o.CH40_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH40_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH40_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH40_TASK_ID: Channel40 task id register +func (o *SOC_ETM_Type) SetCH40_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH40_TASK_ID.Reg, volatile.LoadUint32(&o.CH40_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH40_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH40_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH41_EVT_ID: Channel41 event id register +func (o *SOC_ETM_Type) SetCH41_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH41_EVT_ID.Reg, volatile.LoadUint32(&o.CH41_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH41_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH41_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH41_TASK_ID: Channel41 task id register +func (o *SOC_ETM_Type) SetCH41_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH41_TASK_ID.Reg, volatile.LoadUint32(&o.CH41_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH41_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH41_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH42_EVT_ID: Channel42 event id register +func (o *SOC_ETM_Type) SetCH42_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH42_EVT_ID.Reg, volatile.LoadUint32(&o.CH42_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH42_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH42_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH42_TASK_ID: Channel42 task id register +func (o *SOC_ETM_Type) SetCH42_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH42_TASK_ID.Reg, volatile.LoadUint32(&o.CH42_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH42_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH42_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH43_EVT_ID: Channel43 event id register +func (o *SOC_ETM_Type) SetCH43_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH43_EVT_ID.Reg, volatile.LoadUint32(&o.CH43_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH43_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH43_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH43_TASK_ID: Channel43 task id register +func (o *SOC_ETM_Type) SetCH43_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH43_TASK_ID.Reg, volatile.LoadUint32(&o.CH43_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH43_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH43_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH44_EVT_ID: Channel44 event id register +func (o *SOC_ETM_Type) SetCH44_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH44_EVT_ID.Reg, volatile.LoadUint32(&o.CH44_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH44_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH44_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH44_TASK_ID: Channel44 task id register +func (o *SOC_ETM_Type) SetCH44_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH44_TASK_ID.Reg, volatile.LoadUint32(&o.CH44_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH44_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH44_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH45_EVT_ID: Channel45 event id register +func (o *SOC_ETM_Type) SetCH45_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH45_EVT_ID.Reg, volatile.LoadUint32(&o.CH45_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH45_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH45_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH45_TASK_ID: Channel45 task id register +func (o *SOC_ETM_Type) SetCH45_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH45_TASK_ID.Reg, volatile.LoadUint32(&o.CH45_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH45_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH45_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH46_EVT_ID: Channel46 event id register +func (o *SOC_ETM_Type) SetCH46_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH46_EVT_ID.Reg, volatile.LoadUint32(&o.CH46_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH46_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH46_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH46_TASK_ID: Channel46 task id register +func (o *SOC_ETM_Type) SetCH46_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH46_TASK_ID.Reg, volatile.LoadUint32(&o.CH46_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH46_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH46_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH47_EVT_ID: Channel47 event id register +func (o *SOC_ETM_Type) SetCH47_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH47_EVT_ID.Reg, volatile.LoadUint32(&o.CH47_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH47_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH47_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH47_TASK_ID: Channel47 task id register +func (o *SOC_ETM_Type) SetCH47_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH47_TASK_ID.Reg, volatile.LoadUint32(&o.CH47_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH47_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH47_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH48_EVT_ID: Channel48 event id register +func (o *SOC_ETM_Type) SetCH48_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH48_EVT_ID.Reg, volatile.LoadUint32(&o.CH48_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH48_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH48_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH48_TASK_ID: Channel48 task id register +func (o *SOC_ETM_Type) SetCH48_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH48_TASK_ID.Reg, volatile.LoadUint32(&o.CH48_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH48_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH48_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.CH49_EVT_ID: Channel49 event id register +func (o *SOC_ETM_Type) SetCH49_EVT_ID(value uint32) { + volatile.StoreUint32(&o.CH49_EVT_ID.Reg, volatile.LoadUint32(&o.CH49_EVT_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH49_EVT_ID() uint32 { + return volatile.LoadUint32(&o.CH49_EVT_ID.Reg) & 0xff +} + +// SOC_ETM.CH49_TASK_ID: Channel49 task id register +func (o *SOC_ETM_Type) SetCH49_TASK_ID(value uint32) { + volatile.StoreUint32(&o.CH49_TASK_ID.Reg, volatile.LoadUint32(&o.CH49_TASK_ID.Reg)&^(0xff)|value) +} +func (o *SOC_ETM_Type) GetCH49_TASK_ID() uint32 { + return volatile.LoadUint32(&o.CH49_TASK_ID.Reg) & 0xff +} + +// SOC_ETM.EVT_ST0: Events trigger status register +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH0_RISE_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH0_RISE_EDGE_ST() uint32 { + return volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH1_RISE_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH1_RISE_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH2_RISE_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH2_RISE_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH3_RISE_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH3_RISE_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH4_RISE_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH4_RISE_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH5_RISE_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH5_RISE_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH6_RISE_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH6_RISE_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH7_RISE_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH7_RISE_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH0_FALL_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH0_FALL_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH1_FALL_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH1_FALL_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH2_FALL_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH2_FALL_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH3_FALL_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH3_FALL_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH4_FALL_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH4_FALL_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH5_FALL_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH5_FALL_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH6_FALL_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH6_FALL_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH7_FALL_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH7_FALL_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH0_ANY_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH0_ANY_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH1_ANY_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH1_ANY_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH2_ANY_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH2_ANY_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH3_ANY_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH3_ANY_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH4_ANY_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH4_ANY_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH5_ANY_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH5_ANY_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH6_ANY_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH6_ANY_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH7_ANY_EDGE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH7_ANY_EDGE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_ZERO_DET_POS0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_ZERO_DET_POS0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_ZERO_DET_NEG0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_ZERO_DET_NEG0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_ZERO_DET_POS1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_ZERO_DET_POS1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_ZERO_DET_NEG1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_ZERO_DET_NEG1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH3_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH3_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST0_CLR: Events trigger status clear register +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH0_RISE_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH0_RISE_EDGE_ST_CLR() uint32 { + return volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH1_RISE_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH1_RISE_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH2_RISE_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH2_RISE_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH3_RISE_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH3_RISE_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH4_RISE_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH4_RISE_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH5_RISE_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH5_RISE_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH6_RISE_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH6_RISE_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH7_RISE_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH7_RISE_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH0_FALL_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH0_FALL_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH1_FALL_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH1_FALL_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH2_FALL_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH2_FALL_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH3_FALL_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH3_FALL_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH4_FALL_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH4_FALL_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH5_FALL_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH5_FALL_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH6_FALL_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH6_FALL_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH7_FALL_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH7_FALL_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH0_ANY_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH0_ANY_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH1_ANY_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH1_ANY_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH2_ANY_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH2_ANY_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH3_ANY_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH3_ANY_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH4_ANY_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH4_ANY_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH5_ANY_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH5_ANY_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH6_ANY_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH6_ANY_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH7_ANY_EDGE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH7_ANY_EDGE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST1: Events trigger status register +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH4_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH4_ST() uint32 { + return volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH5_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH5_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH6_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH6_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH7_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH7_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH3_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH3_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH4_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH4_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH5_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH5_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH6_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH6_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH7_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH7_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER3_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER3_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIMER0_CMP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIMER0_CMP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIMER1_CMP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIMER1_CMP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIMER2_CMP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIMER2_CMP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIMER3_CMP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIMER3_CMP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST1_TG0_EVT_CNT_CMP_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST1_TG0_EVT_CNT_CMP_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST1_TG0_EVT_CNT_CMP_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST1_TG0_EVT_CNT_CMP_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST1_TG1_EVT_CNT_CMP_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST1_TG1_EVT_CNT_CMP_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST1_TG1_EVT_CNT_CMP_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST1_TG1_EVT_CNT_CMP_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST1_SYSTIMER_EVT_CNT_CMP0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST1_SYSTIMER_EVT_CNT_CMP0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST1_SYSTIMER_EVT_CNT_CMP1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST1_SYSTIMER_EVT_CNT_CMP1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST1_SYSTIMER_EVT_CNT_CMP2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST1_SYSTIMER_EVT_CNT_CMP2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER0_STOP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER0_STOP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER1_STOP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER1_STOP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER2_STOP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER2_STOP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER0_TEZ_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER0_TEZ_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER1_TEZ_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER1_TEZ_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST1_CLR: Events trigger status clear register +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR() uint32 { + return volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIMER0_CMP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIMER0_CMP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIMER1_CMP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIMER1_CMP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIMER2_CMP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIMER2_CMP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIMER3_CMP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIMER3_CMP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER0_STOP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER0_STOP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER1_STOP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER1_STOP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER2_STOP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER2_STOP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER0_TEZ_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER0_TEZ_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER1_TEZ_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER1_TEZ_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST2: Events trigger status register +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TIMER2_TEZ_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TIMER2_TEZ_ST() uint32 { + return volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TIMER0_TEP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TIMER0_TEP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TIMER1_TEP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TIMER1_TEP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TIMER2_TEP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TIMER2_TEP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP0_TEA_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP0_TEA_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP1_TEA_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP1_TEA_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP2_TEA_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP2_TEA_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP0_TEB_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP0_TEB_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP1_TEB_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP1_TEB_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP2_TEB_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP2_TEB_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F0_CLR_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F0_CLR_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F1_CLR_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F1_CLR_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F2_CLR_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F2_CLR_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ0_CBC_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ0_CBC_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ1_CBC_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ1_CBC_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ2_CBC_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ2_CBC_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ0_OST_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ0_OST_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ1_OST_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ1_OST_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ2_OST_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ2_OST_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_CAP0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_CAP0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_CAP1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_CAP1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_CAP2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_CAP2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP0_TEE1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP0_TEE1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP1_TEE1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP1_TEE1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP2_TEE1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP2_TEE1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP0_TEE2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP0_TEE2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP1_TEE2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP1_TEE2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP2_TEE2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP2_TEE2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM1_EVT_TIMER0_STOP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM1_EVT_TIMER0_STOP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST2_CLR: Events trigger status clear register +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEZ_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEZ_ST_CLR() uint32 { + return volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TIMER0_TEP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TIMER0_TEP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TIMER1_TEP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TIMER1_TEP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEA_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEA_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEA_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEA_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEA_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEA_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEB_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEB_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEB_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEB_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEB_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEB_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F0_CLR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F0_CLR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F1_CLR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F1_CLR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F2_CLR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F2_CLR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ0_CBC_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ0_CBC_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ1_CBC_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ1_CBC_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ2_CBC_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ2_CBC_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ0_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ0_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ1_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ1_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ2_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ2_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_CAP0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_CAP0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_CAP1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_CAP1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_CAP2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_CAP2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEE1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEE1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEE1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEE1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEE1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEE1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEE2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEE2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEE2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEE2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEE2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEE2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM1_EVT_TIMER0_STOP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM1_EVT_TIMER0_STOP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST3: Events trigger status register +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER1_STOP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER1_STOP_ST() uint32 { + return volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER2_STOP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER2_STOP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER0_TEZ_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER0_TEZ_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER1_TEZ_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER1_TEZ_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER2_TEZ_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER2_TEZ_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER0_TEP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER0_TEP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER1_TEP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER1_TEP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER2_TEP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER2_TEP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP0_TEA_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP0_TEA_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP1_TEA_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP1_TEA_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP2_TEA_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP2_TEA_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP0_TEB_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP0_TEB_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP1_TEB_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP1_TEB_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP2_TEB_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP2_TEB_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F0_CLR_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F0_CLR_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F1_CLR_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F1_CLR_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F2_CLR_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F2_CLR_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ0_CBC_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ0_CBC_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ1_CBC_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ1_CBC_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ2_CBC_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ2_CBC_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ0_OST_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ0_OST_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ1_OST_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ1_OST_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ2_OST_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ2_OST_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_CAP0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_CAP0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_CAP1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_CAP1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_CAP2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_CAP2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP0_TEE1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP0_TEE1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP1_TEE1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP1_TEE1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP2_TEE1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP2_TEE1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST3_CLR: Events trigger status clear register +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_STOP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_STOP_ST_CLR() uint32 { + return volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_STOP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_STOP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEZ_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEZ_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEZ_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEZ_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEZ_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEZ_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEA_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEA_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEA_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEA_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEA_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEA_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEB_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEB_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEB_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEB_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEB_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEB_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F0_CLR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F0_CLR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F1_CLR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F1_CLR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F2_CLR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F2_CLR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ0_CBC_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ0_CBC_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ1_CBC_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ1_CBC_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ2_CBC_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ2_CBC_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ0_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ0_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ1_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ1_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ2_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ2_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_CAP0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_CAP0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_CAP1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_CAP1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_CAP2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_CAP2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEE1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEE1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEE1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEE1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEE1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEE1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST4: Events trigger status register +func (o *SOC_ETM_Type) SetEVT_ST4_MCPWM1_EVT_OP0_TEE2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST4_MCPWM1_EVT_OP0_TEE2_ST() uint32 { + return volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST4_MCPWM1_EVT_OP1_TEE2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST4_MCPWM1_EVT_OP1_TEE2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST4_MCPWM1_EVT_OP2_TEE2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST4_MCPWM1_EVT_OP2_TEE2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_CONV_CMPLT0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_CONV_CMPLT0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_EQ_ABOVE_THRESH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_EQ_ABOVE_THRESH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_EQ_ABOVE_THRESH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_EQ_ABOVE_THRESH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_EQ_BELOW_THRESH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_EQ_BELOW_THRESH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_EQ_BELOW_THRESH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_EQ_BELOW_THRESH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_RESULT_DONE0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_RESULT_DONE0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_STOPPED0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_STOPPED0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_STARTED0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_STARTED0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_DONE0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_DONE0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_DONE1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_DONE1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_DONE2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_DONE2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_DONE3_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_DONE3_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_ERR0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_ERR0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_ERR1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_ERR1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_ERR2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_ERR2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_ERR3_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_ERR3_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST4_TMPSNSR_EVT_OVER_LIMIT_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST4_TMPSNSR_EVT_OVER_LIMIT_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S0_EVT_RX_DONE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S0_EVT_RX_DONE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S0_EVT_TX_DONE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S0_EVT_TX_DONE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S0_EVT_X_WORDS_RECEIVED_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S0_EVT_X_WORDS_RECEIVED_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S0_EVT_X_WORDS_SENT_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S0_EVT_X_WORDS_SENT_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S1_EVT_RX_DONE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S1_EVT_RX_DONE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S1_EVT_TX_DONE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S1_EVT_TX_DONE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S1_EVT_X_WORDS_RECEIVED_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S1_EVT_X_WORDS_RECEIVED_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S1_EVT_X_WORDS_SENT_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S1_EVT_X_WORDS_SENT_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S2_EVT_RX_DONE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S2_EVT_RX_DONE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S2_EVT_TX_DONE_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S2_EVT_TX_DONE_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S2_EVT_X_WORDS_RECEIVED_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S2_EVT_X_WORDS_RECEIVED_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST4_I2S2_EVT_X_WORDS_SENT_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST4_I2S2_EVT_X_WORDS_SENT_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST4_CLR: Events trigger status clear register +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_MCPWM1_EVT_OP0_TEE2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_MCPWM1_EVT_OP0_TEE2_ST_CLR() uint32 { + return volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_MCPWM1_EVT_OP1_TEE2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_MCPWM1_EVT_OP1_TEE2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_MCPWM1_EVT_OP2_TEE2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_MCPWM1_EVT_OP2_TEE2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_CONV_CMPLT0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_CONV_CMPLT0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_RESULT_DONE0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_RESULT_DONE0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_STOPPED0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_STOPPED0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_STARTED0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_STARTED0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_DONE0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_DONE0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_DONE1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_DONE1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_DONE2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_DONE2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_DONE3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_DONE3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_ERR0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_ERR0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_ERR1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_ERR1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_ERR2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_ERR2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_ERR3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_ERR3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_TMPSNSR_EVT_OVER_LIMIT_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_TMPSNSR_EVT_OVER_LIMIT_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S0_EVT_RX_DONE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S0_EVT_RX_DONE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S0_EVT_TX_DONE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S0_EVT_TX_DONE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S0_EVT_X_WORDS_SENT_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S0_EVT_X_WORDS_SENT_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S1_EVT_RX_DONE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S1_EVT_RX_DONE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S1_EVT_TX_DONE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S1_EVT_TX_DONE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S1_EVT_X_WORDS_SENT_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S1_EVT_X_WORDS_SENT_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S2_EVT_RX_DONE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S2_EVT_RX_DONE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S2_EVT_TX_DONE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S2_EVT_TX_DONE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S2_EVT_X_WORDS_SENT_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S2_EVT_X_WORDS_SENT_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST5: Events trigger status register +func (o *SOC_ETM_Type) SetEVT_ST5_ULP_EVT_ERR_INTR_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST5_ULP_EVT_ERR_INTR_ST() uint32 { + return volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST5_ULP_EVT_HALT_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST5_ULP_EVT_HALT_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST5_ULP_EVT_START_INTR_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST5_ULP_EVT_START_INTR_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST5_RTC_EVT_TICK_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST5_RTC_EVT_TICK_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST5_RTC_EVT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST5_RTC_EVT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST5_RTC_EVT_CMP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST5_RTC_EVT_CMP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST5_CLR: Events trigger status clear register +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_ULP_EVT_ERR_INTR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_ULP_EVT_ERR_INTR_ST_CLR() uint32 { + return volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_ULP_EVT_HALT_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_ULP_EVT_HALT_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_ULP_EVT_START_INTR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_ULP_EVT_START_INTR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_RTC_EVT_TICK_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_RTC_EVT_TICK_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_RTC_EVT_OVF_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_RTC_EVT_OVF_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_RTC_EVT_CMP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_RTC_EVT_CMP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST6: Events trigger status register +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST() uint32 { + return volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST6_PMU_EVT_SLEEP_WEEKUP_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST6_PMU_EVT_SLEEP_WEEKUP_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST6_DMA2D_EVT_IN_DONE_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST6_DMA2D_EVT_IN_DONE_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST6_DMA2D_EVT_IN_DONE_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST6_DMA2D_EVT_IN_DONE_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST6_DMA2D_EVT_IN_SUC_EOF_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST6_DMA2D_EVT_IN_SUC_EOF_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST6_CLR: Events trigger status clear register +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR() uint32 { + return volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PMU_EVT_SLEEP_WEEKUP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PMU_EVT_SLEEP_WEEKUP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetEVT_ST6_CLR_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetEVT_ST6_CLR_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.EVT_ST7: Events trigger status register +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_IN_SUC_EOF_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_IN_SUC_EOF_CH1_ST() uint32 { + return volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_DONE_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_DONE_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_DONE_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_DONE_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_DONE_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_DONE_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_EOF_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_EOF_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_EOF_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_EOF_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_EOF_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_EOF_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST(value uint32) { + volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x200) >> 9 +} + +// SOC_ETM.EVT_ST7_CLR: Events trigger status clear register +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR() uint32 { + return volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x200) >> 9 +} + +// SOC_ETM.TASK_ST0: Tasks trigger status register +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH0_SET_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH0_SET_ST() uint32 { + return volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH1_SET_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH1_SET_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH2_SET_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH2_SET_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH3_SET_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH3_SET_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH4_SET_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH4_SET_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH5_SET_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH5_SET_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH6_SET_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH6_SET_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH7_SET_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH7_SET_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH0_CLEAR_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH0_CLEAR_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH1_CLEAR_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH1_CLEAR_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH2_CLEAR_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH2_CLEAR_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH3_CLEAR_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH3_CLEAR_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH4_CLEAR_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH4_CLEAR_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH5_CLEAR_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH5_CLEAR_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH6_CLEAR_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH6_CLEAR_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH7_CLEAR_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH7_CLEAR_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH0_TOGGLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH0_TOGGLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH1_TOGGLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH1_TOGGLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH2_TOGGLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH2_TOGGLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH3_TOGGLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH3_TOGGLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH4_TOGGLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH4_TOGGLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH5_TOGGLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH5_TOGGLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH6_TOGGLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH6_TOGGLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH7_TOGGLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH7_TOGGLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_TIMER0_RES_UPDATE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_TIMER0_RES_UPDATE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_TIMER1_RES_UPDATE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_TIMER1_RES_UPDATE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_TIMER2_RES_UPDATE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_TIMER2_RES_UPDATE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_TIMER3_RES_UPDATE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_TIMER3_RES_UPDATE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST0_CLR: Tasks trigger status clear register +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH0_SET_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH0_SET_ST_CLR() uint32 { + return volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH1_SET_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH1_SET_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH2_SET_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH2_SET_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH3_SET_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH3_SET_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH4_SET_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH4_SET_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH5_SET_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH5_SET_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH6_SET_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH6_SET_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH7_SET_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH7_SET_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH0_CLEAR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH0_CLEAR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH1_CLEAR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH1_CLEAR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH2_CLEAR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH2_CLEAR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH3_CLEAR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH3_CLEAR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH4_CLEAR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH4_CLEAR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH5_CLEAR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH5_CLEAR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH6_CLEAR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH6_CLEAR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH7_CLEAR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH7_CLEAR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH0_TOGGLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH0_TOGGLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH1_TOGGLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH1_TOGGLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH2_TOGGLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH2_TOGGLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH3_TOGGLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH3_TOGGLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH4_TOGGLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH4_TOGGLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH5_TOGGLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH5_TOGGLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH6_TOGGLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH6_TOGGLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH7_TOGGLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH7_TOGGLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST1: Tasks trigger status register +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST() uint32 { + return volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER0_CAP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER0_CAP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER1_CAP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER1_CAP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER2_CAP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER2_CAP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER3_CAP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER3_CAP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH3_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH3_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH4_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH4_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH5_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH5_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH6_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH6_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH7_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH7_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH3_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH3_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH4_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH4_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH5_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH5_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH6_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH6_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH7_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH7_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER0_RST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER0_RST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER1_RST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER1_RST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER2_RST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER2_RST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER3_RST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER3_RST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER0_RESUME_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER0_RESUME_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER1_RESUME_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER1_RESUME_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER2_RESUME_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER2_RESUME_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER3_RESUME_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER3_RESUME_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST1_CLR: Tasks trigger status clear register +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR() uint32 { + return volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER0_CAP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER0_CAP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER1_CAP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER1_CAP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER2_CAP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER2_CAP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER3_CAP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER3_CAP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER0_RST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER0_RST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER1_RST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER1_RST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER2_RST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER2_RST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER3_RST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER3_RST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER0_RESUME_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER0_RESUME_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER1_RESUME_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER1_RESUME_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER2_RESUME_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER2_RESUME_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER3_RESUME_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER3_RESUME_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST2: Tasks trigger status register +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_TIMER0_PAUSE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_TIMER0_PAUSE_ST() uint32 { + return volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_TIMER1_PAUSE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_TIMER1_PAUSE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_TIMER2_PAUSE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_TIMER2_PAUSE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_TIMER3_PAUSE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_TIMER3_PAUSE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH3_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH3_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH4_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH4_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH5_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH5_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH6_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH6_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH7_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH7_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH3_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH3_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH4_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH4_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH5_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH5_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH6_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH6_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH7_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH7_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH3_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH3_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH4_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH4_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH5_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH5_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH6_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH6_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH7_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH7_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST2_TG0_TASK_CNT_START_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST2_TG0_TASK_CNT_START_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST2_TG0_TASK_ALARM_START_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST2_TG0_TASK_ALARM_START_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST2_TG0_TASK_CNT_STOP_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST2_TG0_TASK_CNT_STOP_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST2_TG0_TASK_CNT_RELOAD_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST2_TG0_TASK_CNT_RELOAD_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST2_CLR: Tasks trigger status clear register +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_TIMER0_PAUSE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_TIMER0_PAUSE_ST_CLR() uint32 { + return volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_TIMER1_PAUSE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_TIMER1_PAUSE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_TIMER2_PAUSE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_TIMER2_PAUSE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_TIMER3_PAUSE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_TIMER3_PAUSE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_TG0_TASK_CNT_START_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_TG0_TASK_CNT_START_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_TG0_TASK_ALARM_START_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_TG0_TASK_ALARM_START_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_TG0_TASK_CNT_STOP_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_TG0_TASK_CNT_STOP_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST2_CLR_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST2_CLR_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST3: Tasks trigger status register +func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_CAP_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_CAP_TIMER0_ST() uint32 { + return volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_START_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_START_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_ALARM_START_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_ALARM_START_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_STOP_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_STOP_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_RELOAD_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_RELOAD_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_CAP_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_CAP_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_START_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_START_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_ALARM_START_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_ALARM_START_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_STOP_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_STOP_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_RELOAD_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_RELOAD_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_CAP_TIMER0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_CAP_TIMER0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_START_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_START_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_ALARM_START_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_ALARM_START_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_STOP_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_STOP_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_RELOAD_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_RELOAD_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_CAP_TIMER1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_CAP_TIMER1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR0_A_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR0_A_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR1_A_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR1_A_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR2_A_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR2_A_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR0_B_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR0_B_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR1_B_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR1_B_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR2_B_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR2_B_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_GEN_STOP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_GEN_STOP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER0_SYN_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER0_SYN_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER1_SYN_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER1_SYN_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER2_SYN_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER2_SYN_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER0_PERIOD_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER0_PERIOD_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER1_PERIOD_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER1_PERIOD_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER2_PERIOD_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER2_PERIOD_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TZ0_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TZ0_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TZ1_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TZ1_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TZ2_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TZ2_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST3_CLR: Tasks trigger status clear register +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER0_ST_CLR() uint32 { + return volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_START_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_START_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_ALARM_START_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_ALARM_START_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_STOP_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_STOP_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_START_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_START_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_START_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_START_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR0_A_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR0_A_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR1_A_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR1_A_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR2_A_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR2_A_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR0_B_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR0_B_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR1_B_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR1_B_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR2_B_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR2_B_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_GEN_STOP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_GEN_STOP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER0_SYN_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER0_SYN_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER1_SYN_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER1_SYN_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER2_SYN_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER2_SYN_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TZ0_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TZ0_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TZ1_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TZ1_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TZ2_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TZ2_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST4: Tasks trigger status register +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CLR0_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CLR0_OST_ST() uint32 { + return volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CLR1_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CLR1_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CLR2_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CLR2_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CAP0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CAP0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CAP1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CAP1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CAP2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CAP2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR0_A_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR0_A_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR1_A_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR1_A_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR2_A_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR2_A_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR0_B_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR0_B_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR1_B_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR1_B_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR2_B_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR2_B_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_GEN_STOP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_GEN_STOP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER0_SYN_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER0_SYN_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER1_SYN_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER1_SYN_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER2_SYN_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER2_SYN_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER0_PERIOD_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER0_PERIOD_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER1_PERIOD_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER1_PERIOD_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER2_PERIOD_UP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER2_PERIOD_UP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TZ0_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TZ0_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TZ1_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TZ1_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TZ2_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TZ2_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CLR0_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CLR0_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CLR1_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CLR1_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CLR2_OST_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CLR2_OST_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CAP0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CAP0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CAP1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CAP1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CAP2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CAP2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST4_ADC_TASK_SAMPLE0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST4_ADC_TASK_SAMPLE0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST4_ADC_TASK_SAMPLE1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST4_ADC_TASK_SAMPLE1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST4_ADC_TASK_START0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST4_ADC_TASK_START0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST4_ADC_TASK_STOP0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST4_ADC_TASK_STOP0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST4_CLR: Tasks trigger status clear register +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CLR0_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CLR0_OST_ST_CLR() uint32 { + return volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CLR1_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CLR1_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CLR2_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CLR2_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CAP0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CAP0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CAP1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CAP1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CAP2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CAP2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR0_A_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR0_A_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR1_A_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR1_A_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR2_A_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR2_A_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR0_B_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR0_B_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR1_B_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR1_B_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR2_B_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR2_B_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_GEN_STOP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_GEN_STOP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER0_SYN_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER0_SYN_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER1_SYN_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER1_SYN_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER2_SYN_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER2_SYN_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TZ0_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TZ0_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TZ1_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TZ1_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TZ2_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TZ2_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CLR0_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CLR0_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CLR1_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CLR1_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CLR2_OST_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CLR2_OST_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CAP0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CAP0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CAP1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CAP1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CAP2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CAP2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_ADC_TASK_SAMPLE0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_ADC_TASK_SAMPLE0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_ADC_TASK_SAMPLE1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_ADC_TASK_SAMPLE1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_ADC_TASK_START0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_ADC_TASK_START0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST4_CLR_ADC_TASK_STOP0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST4_CLR_ADC_TASK_STOP0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST5: Tasks trigger status register +func (o *SOC_ETM_Type) SetTASK_ST5_REGDMA_TASK_START0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST5_REGDMA_TASK_START0_ST() uint32 { + return volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST5_REGDMA_TASK_START1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST5_REGDMA_TASK_START1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST5_REGDMA_TASK_START2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST5_REGDMA_TASK_START2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST5_REGDMA_TASK_START3_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST5_REGDMA_TASK_START3_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST5_TMPSNSR_TASK_START_SAMPLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST5_TMPSNSR_TASK_START_SAMPLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST5_TMPSNSR_TASK_STOP_SAMPLE_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST5_TMPSNSR_TASK_STOP_SAMPLE_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S0_TASK_START_RX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S0_TASK_START_RX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S0_TASK_START_TX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S0_TASK_START_TX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S0_TASK_STOP_RX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S0_TASK_STOP_RX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S0_TASK_STOP_TX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S0_TASK_STOP_TX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S1_TASK_START_RX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S1_TASK_START_RX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S1_TASK_START_TX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S1_TASK_START_TX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S1_TASK_STOP_RX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S1_TASK_STOP_RX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S1_TASK_STOP_TX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S1_TASK_STOP_TX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S2_TASK_START_RX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S2_TASK_START_RX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S2_TASK_START_TX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S2_TASK_START_TX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S2_TASK_STOP_RX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S2_TASK_STOP_RX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST5_I2S2_TASK_STOP_TX_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST5_I2S2_TASK_STOP_TX_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST5_ULP_TASK_WAKEUP_CPU_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST5_ULP_TASK_WAKEUP_CPU_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST5_ULP_TASK_INT_CPU_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST5_ULP_TASK_INT_CPU_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST5_RTC_TASK_START_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST5_RTC_TASK_START_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST5_RTC_TASK_STOP_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST5_RTC_TASK_STOP_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST5_RTC_TASK_CLR_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST5_RTC_TASK_CLR_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST5_RTC_TASK_TRIGGERFLW_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST5_RTC_TASK_TRIGGERFLW_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_IN_START_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_IN_START_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_IN_START_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_IN_START_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_IN_START_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_IN_START_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AXI_TASK_IN_START_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AXI_TASK_IN_START_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AXI_TASK_IN_START_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AXI_TASK_IN_START_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST5_CLR: Tasks trigger status clear register +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_REGDMA_TASK_START0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_REGDMA_TASK_START0_ST_CLR() uint32 { + return volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_REGDMA_TASK_START1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_REGDMA_TASK_START1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_REGDMA_TASK_START2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_REGDMA_TASK_START2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_REGDMA_TASK_START3_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_REGDMA_TASK_START3_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_TMPSNSR_TASK_START_SAMPLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_TMPSNSR_TASK_START_SAMPLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S0_TASK_START_RX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S0_TASK_START_RX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S0_TASK_START_TX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S0_TASK_START_TX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S0_TASK_STOP_RX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S0_TASK_STOP_RX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S0_TASK_STOP_TX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S0_TASK_STOP_TX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S1_TASK_START_RX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S1_TASK_START_RX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S1_TASK_START_TX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S1_TASK_START_TX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S1_TASK_STOP_RX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S1_TASK_STOP_RX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S1_TASK_STOP_TX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S1_TASK_STOP_TX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S2_TASK_START_RX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S2_TASK_START_RX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x4000) >> 14 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S2_TASK_START_TX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S2_TASK_START_TX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x8000) >> 15 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S2_TASK_STOP_RX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S2_TASK_STOP_RX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x10000) >> 16 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S2_TASK_STOP_TX_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S2_TASK_STOP_TX_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x20000) >> 17 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_ULP_TASK_WAKEUP_CPU_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_ULP_TASK_WAKEUP_CPU_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x40000) >> 18 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_ULP_TASK_INT_CPU_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_ULP_TASK_INT_CPU_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x80000) >> 19 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_RTC_TASK_START_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_RTC_TASK_START_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x100000) >> 20 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_RTC_TASK_STOP_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_RTC_TASK_STOP_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x200000) >> 21 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_RTC_TASK_CLR_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_RTC_TASK_CLR_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x400000) >> 22 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_RTC_TASK_TRIGGERFLW_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_RTC_TASK_TRIGGERFLW_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x800000) >> 23 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x1000000) >> 24 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x2000000) >> 25 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x4000000) >> 26 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x8000000) >> 27 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x80000000) >> 31 +} + +// SOC_ETM.TASK_ST6: Tasks trigger status register +func (o *SOC_ETM_Type) SetTASK_ST6_PDMA_AXI_TASK_IN_START_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST6_PDMA_AXI_TASK_IN_START_CH2_ST() uint32 { + return volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST6_PMU_TASK_SLEEP_REQ_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST6_PMU_TASK_SLEEP_REQ_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_IN_START_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_IN_START_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_IN_START_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_IN_START_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_START_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_START_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_START_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_START_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_START_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_START_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH0_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH0_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH1_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH1_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH2_ST(value uint32) { + volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH2_ST() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x4000) >> 14 +} + +// SOC_ETM.TASK_ST6_CLR: Tasks trigger status clear register +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PDMA_AXI_TASK_IN_START_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PDMA_AXI_TASK_IN_START_CH2_ST_CLR() uint32 { + return volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x1 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x2) >> 1 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x4) >> 2 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x8) >> 3 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PMU_TASK_SLEEP_REQ_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PMU_TASK_SLEEP_REQ_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x10) >> 4 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_IN_START_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_IN_START_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x20) >> 5 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_IN_START_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_IN_START_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x40) >> 6 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x80) >> 7 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x100) >> 8 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x200) >> 9 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x400) >> 10 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x800) >> 11 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x1000) >> 12 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x2000) >> 13 +} +func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR(value uint32) { + volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR() uint32 { + return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x4000) >> 14 +} + +// SOC_ETM.CLK_EN: ETM clock enable register +func (o *SOC_ETM_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value) +} +func (o *SOC_ETM_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1 +} + +// SOC_ETM.DATE: ETM date register +func (o *SOC_ETM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SOC_ETM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 0 +type SPI0_Type struct { + SPI_MEM_CMD volatile.Register32 // 0x0 + _ [4]byte + SPI_MEM_CTRL volatile.Register32 // 0x8 + SPI_MEM_CTRL1 volatile.Register32 // 0xC + SPI_MEM_CTRL2 volatile.Register32 // 0x10 + SPI_MEM_CLOCK volatile.Register32 // 0x14 + SPI_MEM_USER volatile.Register32 // 0x18 + SPI_MEM_USER1 volatile.Register32 // 0x1C + SPI_MEM_USER2 volatile.Register32 // 0x20 + _ [8]byte + SPI_MEM_RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + SPI_MEM_MISC volatile.Register32 // 0x34 + _ [4]byte + SPI_MEM_CACHE_FCTRL volatile.Register32 // 0x3C + SPI_MEM_CACHE_SCTRL volatile.Register32 // 0x40 + SPI_MEM_SRAM_CMD volatile.Register32 // 0x44 + SPI_MEM_SRAM_DRD_CMD volatile.Register32 // 0x48 + SPI_MEM_SRAM_DWR_CMD volatile.Register32 // 0x4C + SPI_MEM_SRAM_CLK volatile.Register32 // 0x50 + SPI_MEM_FSM volatile.Register32 // 0x54 + _ [104]byte + SPI_MEM_INT_ENA volatile.Register32 // 0xC0 + SPI_MEM_INT_CLR volatile.Register32 // 0xC4 + SPI_MEM_INT_RAW volatile.Register32 // 0xC8 + SPI_MEM_INT_ST volatile.Register32 // 0xCC + _ [4]byte + SPI_MEM_DDR volatile.Register32 // 0xD4 + SPI_SMEM_DDR volatile.Register32 // 0xD8 + _ [36]byte + SPI_FMEM_PMS0_ATTR volatile.Register32 // 0x100 + SPI_FMEM_PMS1_ATTR volatile.Register32 // 0x104 + SPI_FMEM_PMS2_ATTR volatile.Register32 // 0x108 + SPI_FMEM_PMS3_ATTR volatile.Register32 // 0x10C + SPI_FMEM_PMS0_ADDR volatile.Register32 // 0x110 + SPI_FMEM_PMS1_ADDR volatile.Register32 // 0x114 + SPI_FMEM_PMS2_ADDR volatile.Register32 // 0x118 + SPI_FMEM_PMS3_ADDR volatile.Register32 // 0x11C + SPI_FMEM_PMS0_SIZE volatile.Register32 // 0x120 + SPI_FMEM_PMS1_SIZE volatile.Register32 // 0x124 + SPI_FMEM_PMS2_SIZE volatile.Register32 // 0x128 + SPI_FMEM_PMS3_SIZE volatile.Register32 // 0x12C + SPI_SMEM_PMS0_ATTR volatile.Register32 // 0x130 + SPI_SMEM_PMS1_ATTR volatile.Register32 // 0x134 + SPI_SMEM_PMS2_ATTR volatile.Register32 // 0x138 + SPI_SMEM_PMS3_ATTR volatile.Register32 // 0x13C + SPI_SMEM_PMS0_ADDR volatile.Register32 // 0x140 + SPI_SMEM_PMS1_ADDR volatile.Register32 // 0x144 + SPI_SMEM_PMS2_ADDR volatile.Register32 // 0x148 + SPI_SMEM_PMS3_ADDR volatile.Register32 // 0x14C + SPI_SMEM_PMS0_SIZE volatile.Register32 // 0x150 + SPI_SMEM_PMS1_SIZE volatile.Register32 // 0x154 + SPI_SMEM_PMS2_SIZE volatile.Register32 // 0x158 + SPI_SMEM_PMS3_SIZE volatile.Register32 // 0x15C + _ [4]byte + SPI_MEM_PMS_REJECT volatile.Register32 // 0x164 + SPI_MEM_ECC_CTRL volatile.Register32 // 0x168 + SPI_MEM_ECC_ERR_ADDR volatile.Register32 // 0x16C + SPI_MEM_AXI_ERR_ADDR volatile.Register32 // 0x170 + SPI_SMEM_ECC_CTRL volatile.Register32 // 0x174 + SPI_SMEM_AXI_ADDR_CTRL volatile.Register32 // 0x178 + SPI_MEM_AXI_ERR_RESP_EN volatile.Register32 // 0x17C + SPI_MEM_TIMING_CALI volatile.Register32 // 0x180 + SPI_MEM_DIN_MODE volatile.Register32 // 0x184 + SPI_MEM_DIN_NUM volatile.Register32 // 0x188 + SPI_MEM_DOUT_MODE volatile.Register32 // 0x18C + SPI_SMEM_TIMING_CALI volatile.Register32 // 0x190 + SPI_SMEM_DIN_MODE volatile.Register32 // 0x194 + SPI_SMEM_DIN_NUM volatile.Register32 // 0x198 + SPI_SMEM_DOUT_MODE volatile.Register32 // 0x19C + SPI_SMEM_AC volatile.Register32 // 0x1A0 + SPI_SMEM_DIN_HEX_MODE volatile.Register32 // 0x1A4 + SPI_SMEM_DIN_HEX_NUM volatile.Register32 // 0x1A8 + SPI_SMEM_DOUT_HEX_MODE volatile.Register32 // 0x1AC + _ [80]byte + SPI_MEM_CLOCK_GATE volatile.Register32 // 0x200 + _ [252]byte + SPI_MEM_XTS_PLAIN_BASE volatile.Register32 // 0x300 + _ [60]byte + SPI_MEM_XTS_LINESIZE volatile.Register32 // 0x340 + SPI_MEM_XTS_DESTINATION volatile.Register32 // 0x344 + SPI_MEM_XTS_PHYSICAL_ADDRESS volatile.Register32 // 0x348 + SPI_MEM_XTS_TRIGGER volatile.Register32 // 0x34C + SPI_MEM_XTS_RELEASE volatile.Register32 // 0x350 + SPI_MEM_XTS_DESTROY volatile.Register32 // 0x354 + SPI_MEM_XTS_STATE volatile.Register32 // 0x358 + SPI_MEM_XTS_DATE volatile.Register32 // 0x35C + _ [28]byte + SPI_MEM_MMU_ITEM_CONTENT volatile.Register32 // 0x37C + SPI_MEM_MMU_ITEM_INDEX volatile.Register32 // 0x380 + SPI_MEM_MMU_POWER_CTRL volatile.Register32 // 0x384 + SPI_MEM_DPA_CTRL volatile.Register32 // 0x388 + _ [100]byte + SPI_MEM_REGISTERRND_ECO_HIGH volatile.Register32 // 0x3F0 + SPI_MEM_REGISTERRND_ECO_LOW volatile.Register32 // 0x3F4 + _ [4]byte + SPI_MEM_DATE volatile.Register32 // 0x3FC +} + +// SPI0.SPI_MEM_CMD: SPI0 FSM status register +func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_MST_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_MST_ST() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf +} +func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_SLV_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf0)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_SLV_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf0) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_USR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000) >> 18 +} + +// SPI0.SPI_MEM_CTRL: SPI0 control register. +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_Q_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_Q_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_D_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_D_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CTRL1: SPI0 control1 register. +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x400000) >> 22 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RAM0_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RAM0_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CTRL2: SPI0 control2 register. +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1f)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1f +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x3e0)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x3e0) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1c00)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1c00) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x7e000000) >> 25 +} +func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CLOCK: SPI clock division control register. +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff +} +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_USER: SPI0 user register. +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x20000000) >> 29 +} + +// SPI0.SPI_MEM_USER1: SPI0 user1 register. +func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x3f)|value) +} +func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x3f +} +func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI0.SPI_MEM_USER2: SPI0 user2 register. +func (o *SPI0_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SPI_MEM_RD_STATUS: SPI0 read control register. +func (o *SPI0_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI0.SPI_MEM_MISC: SPI0 misc register +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_FSUB_PIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_FSUB_PIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_SSUB_PIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_SSUB_PIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x400) >> 10 +} + +// SPI0.SPI_MEM_CACHE_FCTRL: SPI0 bit mode control register. +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_CACHE_SCTRL: SPI0 external RAM control register +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc00000)|value<<22) +} +func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc00000) >> 22 +} + +// SPI0.SPI_MEM_SRAM_CMD: SPI0 external RAM mode control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x3fc)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x3fc) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x400) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x800)|value<<11) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x800) >> 11 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x8000)|value<<15) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x8000) >> 15 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_HEX(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_HEX() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_HEX(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_HEX() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_SRAM_DRD_CMD: SPI0 external RAM DDR read command control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SPI_MEM_SRAM_DWR_CMD: SPI0 external RAM DDR write command control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SPI_MEM_SRAM_CLK: SPI0 external RAM clock control register +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_FSM: SPI0 FSM status register +func (o *SPI0_Type) SetSPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FSM.Reg, volatile.LoadUint32(&o.SPI_MEM_FSM.Reg)&^(0xf80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FSM.Reg) & 0xf80) >> 7 +} + +// SPI0.SPI_MEM_INT_ENA: SPI0 interrupt enable register +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_DQS0_AFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_DQS0_AFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_DQS1_AFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_DQS1_AFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO1_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO1_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO0_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO0_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_INT_CLR: SPI0 interrupt clear register +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_DQS0_AFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_DQS0_AFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_DQS1_AFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_DQS1_AFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO1_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO1_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO0_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO0_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_INT_RAW: SPI0 interrupt raw register +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_DQS0_AFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_DQS0_AFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_DQS1_AFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_DQS1_AFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO1_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO1_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO0_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO0_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_INT_ST: SPI0 interrupt status register +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_DQS0_AFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_DQS0_AFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_DQS1_AFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_DQS1_AFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_BUS_FIFO1_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_BUS_FIFO1_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_BUS_FIFO0_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_BUS_FIFO0_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_DDR: SPI0 flash DDR mode control register +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI0.SPI_SMEM_DDR: SPI0 external RAM DDR mode control register +func (o *SPI0_Type) SetSPI_SMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI0.SPI_FMEM_PMS0_ATTR: MSPI flash PMS section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS1_ATTR: MSPI flash PMS section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS2_ATTR: MSPI flash PMS section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS3_ATTR: MSPI flash PMS section %s attribute register +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_FMEM_PMS0_ADDR: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS0_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS0_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_FMEM_PMS1_ADDR: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS1_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS1_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_FMEM_PMS2_ADDR: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS2_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS2_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_FMEM_PMS3_ADDR: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS3_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS3_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_FMEM_PMS0_SIZE: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS0_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS0_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_SIZE.Reg)&^(0x7fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS0_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS0_SIZE.Reg) & 0x7fff +} + +// SPI0.SPI_FMEM_PMS1_SIZE: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS1_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS1_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_SIZE.Reg)&^(0x7fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS1_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS1_SIZE.Reg) & 0x7fff +} + +// SPI0.SPI_FMEM_PMS2_SIZE: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS2_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS2_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_SIZE.Reg)&^(0x7fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS2_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS2_SIZE.Reg) & 0x7fff +} + +// SPI0.SPI_FMEM_PMS3_SIZE: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_FMEM_PMS3_SIZE_SPI_FMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_FMEM_PMS3_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_SIZE.Reg)&^(0x7fff)|value) +} +func (o *SPI0_Type) GetSPI_FMEM_PMS3_SIZE_SPI_FMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_FMEM_PMS3_SIZE.Reg) & 0x7fff +} + +// SPI0.SPI_SMEM_PMS0_ATTR: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS1_ATTR: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS2_ATTR: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS3_ATTR: SPI1 flash PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x4) >> 2 +} + +// SPI0.SPI_SMEM_PMS0_ADDR: SPI1 external RAM PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS0_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS0_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_SMEM_PMS1_ADDR: SPI1 external RAM PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS1_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS1_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_SMEM_PMS2_ADDR: SPI1 external RAM PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS2_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS2_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_SMEM_PMS3_ADDR: SPI1 external RAM PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS3_ADDR_S(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_ADDR_S() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS3_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_SMEM_PMS0_SIZE: SPI1 external RAM PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS0_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS0_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_SIZE.Reg)&^(0x7fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS0_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS0_SIZE.Reg) & 0x7fff +} + +// SPI0.SPI_SMEM_PMS1_SIZE: SPI1 external RAM PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS1_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS1_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_SIZE.Reg)&^(0x7fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS1_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS1_SIZE.Reg) & 0x7fff +} + +// SPI0.SPI_SMEM_PMS2_SIZE: SPI1 external RAM PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS2_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS2_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_SIZE.Reg)&^(0x7fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS2_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS2_SIZE.Reg) & 0x7fff +} + +// SPI0.SPI_SMEM_PMS3_SIZE: SPI1 external RAM PMS section %s start address register +func (o *SPI0_Type) SetSPI_SMEM_PMS3_SIZE_SPI_SMEM_PMS_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_PMS3_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_SIZE.Reg)&^(0x7fff)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_PMS3_SIZE_SPI_SMEM_PMS_SIZE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_PMS3_SIZE.Reg) & 0x7fff +} + +// SPI0.SPI_MEM_PMS_REJECT: SPI1 access reject register +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x7ffffff +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PM_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PM_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_ECC_CTRL: MSPI ECC control register +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x7e0)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x7e0) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x1f800)|value<<11) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x1f800) >> 11 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0xc0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0xc0000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0xfe000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0xfe000000) >> 25 +} + +// SPI0.SPI_MEM_ECC_ERR_ADDR: MSPI ECC error address register +func (o *SPI0_Type) SetSPI_MEM_ECC_ERR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_ECC_ERR_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_MEM_AXI_ERR_ADDR: SPI0 AXI request error address. +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x7ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x7ffffff +} + +// SPI0.SPI_SMEM_ECC_CTRL: MSPI ECC control register +func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0xc0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0xc0000) >> 18 +} +func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0x100000) >> 20 +} + +// SPI0.SPI_SMEM_AXI_ADDR_CTRL: SPI0 AXI address control register +func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_MEM_ALL_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_MEM_ALL_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_RDATA_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_RDATA_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_RADDR_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_RADDR_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_WDATA_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_WDATA_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_WBLEN_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_WBLEN_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_ALL_AXI_TRANS_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_ALL_AXI_TRANS_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_AXI_ERR_RESP_EN: SPI0 AXI error response enable register +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_VLD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_VLD() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_GID(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_GID() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_FLASH(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_FLASH() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_SENS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_SENS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_WSTRB(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_WSTRB() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_VLD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_VLD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_GID(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_GID() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_ECC(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_ECC() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_SENS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_SENS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x400) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_AXI_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x800)|value<<11) +} +func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_AXI_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x800) >> 11 +} + +// SPI0.SPI_MEM_TIMING_CALI: SPI0 flash timing calibration register +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_UPDATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_UPDATE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x40) >> 6 +} + +// SPI0.SPI_MEM_DIN_MODE: MSPI flash input timing delay mode control register +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7000000) >> 24 +} + +// SPI0.SPI_MEM_DIN_NUM: MSPI flash input timing delay number control register +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc000) >> 14 +} +func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x30000) >> 16 +} + +// SPI0.SPI_MEM_DOUT_MODE: MSPI flash output timing adjustment control register +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI0.SPI_SMEM_TIMING_CALI: MSPI external RAM timing calibration register +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x20) >> 5 +} + +// SPI0.SPI_SMEM_DIN_MODE: MSPI external RAM input timing delay mode control register +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000000) >> 24 +} + +// SPI0.SPI_SMEM_DIN_NUM: MSPI external RAM input timing delay number control register +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc000) >> 14 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30000) >> 16 +} + +// SPI0.SPI_SMEM_DOUT_MODE: MSPI external RAM output timing adjustment control register +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI0.SPI_SMEM_AC: MSPI external RAM ECC and SPI CS timing control register +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7c)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7c) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0xf80)|value<<7) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0xf80) >> 7 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x8000)|value<<15) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x8000) >> 15 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7e000000) >> 25 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_SMEM_DIN_HEX_MODE: MSPI 16x external RAM input timing delay mode control register +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN08_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN08_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN09_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN09_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN10_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN10_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN11_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN11_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN12_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN12_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN13_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN13_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN14_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN14_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN15_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN15_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DINS_HEX_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x7000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DINS_HEX_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x7000000) >> 24 +} + +// SPI0.SPI_SMEM_DIN_HEX_NUM: MSPI 16x external RAM input timing delay number control register +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN08_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN08_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN09_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN09_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN10_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN10_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN11_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN11_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN12_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN12_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN13_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN13_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN14_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN14_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN15_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN15_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0xc000) >> 14 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DINS_HEX_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DINS_HEX_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x30000) >> 16 +} + +// SPI0.SPI_SMEM_DOUT_HEX_MODE: MSPI 16x external RAM output timing adjustment control register +func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT08_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT08_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT09_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT09_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT10_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT10_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT11_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT11_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT12_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT12_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT13_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT13_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT14_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT14_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT15_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT15_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUTS_HEX_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUTS_HEX_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x100) >> 8 +} + +// SPI0.SPI_MEM_CLOCK_GATE: SPI0 clock gate register +func (o *SPI0_Type) SetSPI_MEM_CLOCK_GATE_SPI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK_GATE.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_CLOCK_GATE_SPI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_PLAIN_BASE: The base address of the memory that stores plaintext in Manual Encryption +func (o *SPI0_Type) SetSPI_MEM_XTS_PLAIN_BASE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_PLAIN_BASE.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_PLAIN_BASE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_PLAIN_BASE.Reg) +} + +// SPI0.SPI_MEM_XTS_LINESIZE: Manual Encryption Line-Size register +func (o *SPI0_Type) SetSPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_LINESIZE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_LINESIZE.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_LINESIZE.Reg) & 0x3 +} + +// SPI0.SPI_MEM_XTS_DESTINATION: Manual Encryption destination register +func (o *SPI0_Type) SetSPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_DESTINATION.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DESTINATION.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_DESTINATION.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_PHYSICAL_ADDRESS: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg)&^(0x3ffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg) & 0x3ffffff +} + +// SPI0.SPI_MEM_XTS_TRIGGER: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_TRIGGER.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_TRIGGER.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_TRIGGER.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_RELEASE: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_RELEASE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_RELEASE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_RELEASE.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_DESTROY: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_DESTROY.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DESTROY.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_DESTROY.Reg) & 0x1 +} + +// SPI0.SPI_MEM_XTS_STATE: Manual Encryption physical address register +func (o *SPI0_Type) SetSPI_MEM_XTS_STATE_SPI_XTS_STATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_STATE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_STATE.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_STATE_SPI_XTS_STATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_STATE.Reg) & 0x3 +} + +// SPI0.SPI_MEM_XTS_DATE: Manual Encryption version register +func (o *SPI0_Type) SetSPI_MEM_XTS_DATE_SPI_XTS_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_XTS_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_XTS_DATE_SPI_XTS_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_XTS_DATE.Reg) & 0x3fffffff +} + +// SPI0.SPI_MEM_MMU_ITEM_CONTENT: MSPI-MMU item content register +func (o *SPI0_Type) SetSPI_MEM_MMU_ITEM_CONTENT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_ITEM_CONTENT.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_ITEM_CONTENT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MMU_ITEM_CONTENT.Reg) +} + +// SPI0.SPI_MEM_MMU_ITEM_INDEX: MSPI-MMU item index register +func (o *SPI0_Type) SetSPI_MEM_MMU_ITEM_INDEX(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_ITEM_INDEX.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_ITEM_INDEX() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MMU_ITEM_INDEX.Reg) +} + +// SPI0.SPI_MEM_MMU_POWER_CTRL: MSPI MMU power control register +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x3fff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x3fff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x80000000) >> 31 +} + +// SPI0.SPI_MEM_DPA_CTRL: SPI memory cryption DPA register +func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x10) >> 4 +} + +// SPI0.SPI_MEM_REGISTERRND_ECO_HIGH: MSPI ECO high register +func (o *SPI0_Type) SetSPI_MEM_REGISTERRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REGISTERRND_ECO_HIGH.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_REGISTERRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REGISTERRND_ECO_HIGH.Reg) +} + +// SPI0.SPI_MEM_REGISTERRND_ECO_LOW: MSPI ECO low register +func (o *SPI0_Type) SetSPI_MEM_REGISTERRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REGISTERRND_ECO_LOW.Reg, value) +} +func (o *SPI0_Type) GetSPI_MEM_REGISTERRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REGISTERRND_ECO_LOW.Reg) +} + +// SPI0.SPI_MEM_DATE: SPI0 version control register +func (o *SPI0_Type) SetSPI_MEM_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI0_Type) GetSPI_MEM_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 1 +type SPI1_Type struct { + SPI_MEM_CMD volatile.Register32 // 0x0 + SPI_MEM_ADDR volatile.Register32 // 0x4 + SPI_MEM_CTRL volatile.Register32 // 0x8 + SPI_MEM_CTRL1 volatile.Register32 // 0xC + SPI_MEM_CTRL2 volatile.Register32 // 0x10 + SPI_MEM_CLOCK volatile.Register32 // 0x14 + SPI_MEM_USER volatile.Register32 // 0x18 + SPI_MEM_USER1 volatile.Register32 // 0x1C + SPI_MEM_USER2 volatile.Register32 // 0x20 + SPI_MEM_MOSI_DLEN volatile.Register32 // 0x24 + SPI_MEM_MISO_DLEN volatile.Register32 // 0x28 + SPI_MEM_RD_STATUS volatile.Register32 // 0x2C + _ [4]byte + SPI_MEM_MISC volatile.Register32 // 0x34 + SPI_MEM_TX_CRC volatile.Register32 // 0x38 + SPI_MEM_CACHE_FCTRL volatile.Register32 // 0x3C + _ [24]byte + SPI_MEM_W0 volatile.Register32 // 0x58 + SPI_MEM_W1 volatile.Register32 // 0x5C + SPI_MEM_W2 volatile.Register32 // 0x60 + SPI_MEM_W3 volatile.Register32 // 0x64 + SPI_MEM_W4 volatile.Register32 // 0x68 + SPI_MEM_W5 volatile.Register32 // 0x6C + SPI_MEM_W6 volatile.Register32 // 0x70 + SPI_MEM_W7 volatile.Register32 // 0x74 + SPI_MEM_W8 volatile.Register32 // 0x78 + SPI_MEM_W9 volatile.Register32 // 0x7C + SPI_MEM_W10 volatile.Register32 // 0x80 + SPI_MEM_W11 volatile.Register32 // 0x84 + SPI_MEM_W12 volatile.Register32 // 0x88 + SPI_MEM_W13 volatile.Register32 // 0x8C + SPI_MEM_W14 volatile.Register32 // 0x90 + SPI_MEM_W15 volatile.Register32 // 0x94 + SPI_MEM_FLASH_WAITI_CTRL volatile.Register32 // 0x98 + SPI_MEM_FLASH_SUS_CTRL volatile.Register32 // 0x9C + SPI_MEM_FLASH_SUS_CMD volatile.Register32 // 0xA0 + SPI_MEM_SUS_STATUS volatile.Register32 // 0xA4 + _ [24]byte + SPI_MEM_INT_ENA volatile.Register32 // 0xC0 + SPI_MEM_INT_CLR volatile.Register32 // 0xC4 + SPI_MEM_INT_RAW volatile.Register32 // 0xC8 + SPI_MEM_INT_ST volatile.Register32 // 0xCC + _ [4]byte + SPI_MEM_DDR volatile.Register32 // 0xD4 + _ [168]byte + SPI_MEM_TIMING_CALI volatile.Register32 // 0x180 + _ [124]byte + SPI_MEM_CLOCK_GATE volatile.Register32 // 0x200 + _ [504]byte + SPI_MEM_DATE volatile.Register32 // 0x3FC +} + +// SPI1.SPI_MEM_CMD: SPI1 memory command register +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_MST_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_MST_ST() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_SLV_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf0)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_SLV_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf0) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_PE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_PE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_USR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_HPM(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_HPM() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_DP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_DP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_CE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_CE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_BE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_BE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_SE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_SE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_PP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_PP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WRSR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WRSR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RDSR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RDSR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RDID(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RDID() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WRDI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WRDI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WREN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WREN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_READ(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_READ() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_ADDR: SPI1 address register +func (o *SPI1_Type) SetSPI_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ADDR.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_ADDR.Reg) +} + +// SPI1.SPI_MEM_CTRL: SPI1 control register. +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_TX_CRC_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_TX_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800) >> 11 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_RESANDRES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_RESANDRES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_Q_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_Q_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_D_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_D_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_WP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_WP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_WRSR_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_WRSR_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1000000) >> 24 +} + +// SPI1.SPI_MEM_CTRL1: SPI1 control1 register. +func (o *SPI1_Type) SetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x3 +} +func (o *SPI1_Type) SetSPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0xffc)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0xffc) >> 2 +} + +// SPI1.SPI_MEM_CTRL2: SPI1 control2 register. +func (o *SPI1_Type) SetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_CLOCK: SPI1 clock division control register. +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff +} +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_USER: SPI1 user register. +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x1000) >> 12 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MISO(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x80000000) >> 31 +} + +// SPI1.SPI_MEM_USER1: SPI1 user1 register. +func (o *SPI1_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x3f)|value) +} +func (o *SPI1_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x3f +} +func (o *SPI1_Type) SetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI1.SPI_MEM_USER2: SPI1 user2 register. +func (o *SPI1_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI1.SPI_MEM_MOSI_DLEN: SPI1 send data bit length control register. +func (o *SPI1_Type) SetSPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MOSI_DLEN.Reg, volatile.LoadUint32(&o.SPI_MEM_MOSI_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MOSI_DLEN.Reg) & 0x3ff +} + +// SPI1.SPI_MEM_MISO_DLEN: SPI1 receive data bit length control register. +func (o *SPI1_Type) SetSPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISO_DLEN.Reg, volatile.LoadUint32(&o.SPI_MEM_MISO_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MISO_DLEN.Reg) & 0x3ff +} + +// SPI1.SPI_MEM_RD_STATUS: SPI1 status register. +func (o *SPI1_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_STATUS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_STATUS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI1.SPI_MEM_MISC: SPI1 misc register +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_TX_CRC: SPI1 TX CRC data register. +func (o *SPI1_Type) SetSPI_MEM_TX_CRC(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TX_CRC.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_TX_CRC() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_TX_CRC.Reg) +} + +// SPI1.SPI_MEM_CACHE_FCTRL: SPI1 bit mode control register. +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x100) >> 8 +} + +// SPI1.SPI_MEM_W0: SPI1 memory data buffer0 +func (o *SPI1_Type) SetSPI_MEM_W0(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W0.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W0() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W0.Reg) +} + +// SPI1.SPI_MEM_W1: SPI1 memory data buffer1 +func (o *SPI1_Type) SetSPI_MEM_W1(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W1.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W1() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W1.Reg) +} + +// SPI1.SPI_MEM_W2: SPI1 memory data buffer2 +func (o *SPI1_Type) SetSPI_MEM_W2(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W2.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W2() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W2.Reg) +} + +// SPI1.SPI_MEM_W3: SPI1 memory data buffer3 +func (o *SPI1_Type) SetSPI_MEM_W3(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W3.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W3() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W3.Reg) +} + +// SPI1.SPI_MEM_W4: SPI1 memory data buffer4 +func (o *SPI1_Type) SetSPI_MEM_W4(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W4.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W4() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W4.Reg) +} + +// SPI1.SPI_MEM_W5: SPI1 memory data buffer5 +func (o *SPI1_Type) SetSPI_MEM_W5(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W5.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W5() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W5.Reg) +} + +// SPI1.SPI_MEM_W6: SPI1 memory data buffer6 +func (o *SPI1_Type) SetSPI_MEM_W6(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W6.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W6() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W6.Reg) +} + +// SPI1.SPI_MEM_W7: SPI1 memory data buffer7 +func (o *SPI1_Type) SetSPI_MEM_W7(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W7.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W7() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W7.Reg) +} + +// SPI1.SPI_MEM_W8: SPI1 memory data buffer8 +func (o *SPI1_Type) SetSPI_MEM_W8(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W8.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W8() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W8.Reg) +} + +// SPI1.SPI_MEM_W9: SPI1 memory data buffer9 +func (o *SPI1_Type) SetSPI_MEM_W9(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W9.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W9() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W9.Reg) +} + +// SPI1.SPI_MEM_W10: SPI1 memory data buffer10 +func (o *SPI1_Type) SetSPI_MEM_W10(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W10.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W10() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W10.Reg) +} + +// SPI1.SPI_MEM_W11: SPI1 memory data buffer11 +func (o *SPI1_Type) SetSPI_MEM_W11(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W11.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W11() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W11.Reg) +} + +// SPI1.SPI_MEM_W12: SPI1 memory data buffer12 +func (o *SPI1_Type) SetSPI_MEM_W12(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W12.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W12() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W12.Reg) +} + +// SPI1.SPI_MEM_W13: SPI1 memory data buffer13 +func (o *SPI1_Type) SetSPI_MEM_W13(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W13.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W13() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W13.Reg) +} + +// SPI1.SPI_MEM_W14: SPI1 memory data buffer14 +func (o *SPI1_Type) SetSPI_MEM_W14(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W14.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W14() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W14.Reg) +} + +// SPI1.SPI_MEM_W15: SPI1 memory data buffer15 +func (o *SPI1_Type) SetSPI_MEM_W15(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_W15.Reg, value) +} +func (o *SPI1_Type) GetSPI_MEM_W15() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_W15.Reg) +} + +// SPI1.SPI_MEM_FLASH_WAITI_CTRL: SPI1 wait idle control register +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x18) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0xfc00)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0xfc00) >> 10 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SPI_MEM_FLASH_SUS_CTRL: SPI1 flash suspend control register +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x3fffc0)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x3fffc0) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0xfe000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0xfe000000) >> 25 +} + +// SPI1.SPI_MEM_FLASH_SUS_CMD: SPI1 flash suspend command register +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SPI_MEM_SUS_STATUS: SPI1 flash suspend status register +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0xffff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0xffff0000) >> 16 +} + +// SPI1.SPI_MEM_INT_ENA: SPI1 interrupt enable register +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_INT_CLR: SPI1 interrupt clear register +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_INT_RAW: SPI1 interrupt raw register +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_INT_ST: SPI1 interrupt status register +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x400) >> 10 +} + +// SPI1.SPI_MEM_DDR: SPI1 DDR control register +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI1.SPI_MEM_TIMING_CALI: SPI1 timing control register +func (o *SPI1_Type) SetSPI_MEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_MEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI1_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI1.SPI_MEM_CLOCK_GATE: SPI1 clk_gate register +func (o *SPI1_Type) SetSPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_CLOCK_GATE.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg) & 0x1 +} + +// SPI1.SPI_MEM_DATE: Version control register +func (o *SPI1_Type) SetSPI_MEM_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI1_Type) GetSPI_MEM_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 2 +type SPI2_Type struct { + SPI_CMD volatile.Register32 // 0x0 + SPI_ADDR volatile.Register32 // 0x4 + SPI_CTRL volatile.Register32 // 0x8 + SPI_CLOCK volatile.Register32 // 0xC + SPI_USER volatile.Register32 // 0x10 + SPI_USER1 volatile.Register32 // 0x14 + SPI_USER2 volatile.Register32 // 0x18 + SPI_MS_DLEN volatile.Register32 // 0x1C + SPI_MISC volatile.Register32 // 0x20 + SPI_DIN_MODE volatile.Register32 // 0x24 + SPI_DIN_NUM volatile.Register32 // 0x28 + SPI_DOUT_MODE volatile.Register32 // 0x2C + SPI_DMA_CONF volatile.Register32 // 0x30 + SPI_DMA_INT_ENA volatile.Register32 // 0x34 + SPI_DMA_INT_CLR volatile.Register32 // 0x38 + SPI_DMA_INT_RAW volatile.Register32 // 0x3C + SPI_DMA_INT_ST volatile.Register32 // 0x40 + SPI_DMA_INT_SET volatile.Register32 // 0x44 + _ [80]byte + SPI_W0 volatile.Register32 // 0x98 + SPI_W1 volatile.Register32 // 0x9C + SPI_W2 volatile.Register32 // 0xA0 + SPI_W3 volatile.Register32 // 0xA4 + SPI_W4 volatile.Register32 // 0xA8 + SPI_W5 volatile.Register32 // 0xAC + SPI_W6 volatile.Register32 // 0xB0 + SPI_W7 volatile.Register32 // 0xB4 + SPI_W8 volatile.Register32 // 0xB8 + SPI_W9 volatile.Register32 // 0xBC + SPI_W10 volatile.Register32 // 0xC0 + SPI_W11 volatile.Register32 // 0xC4 + SPI_W12 volatile.Register32 // 0xC8 + SPI_W13 volatile.Register32 // 0xCC + SPI_W14 volatile.Register32 // 0xD0 + SPI_W15 volatile.Register32 // 0xD4 + _ [8]byte + SPI_SLAVE volatile.Register32 // 0xE0 + SPI_SLAVE1 volatile.Register32 // 0xE4 + SPI_CLK_GATE volatile.Register32 // 0xE8 + _ [4]byte + SPI_DATE volatile.Register32 // 0xF0 +} + +// SPI2.SPI_CMD: Command control register +func (o *SPI2_Type) SetSPI_CMD_SPI_CONF_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetSPI_CMD_SPI_CONF_BITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetSPI_CMD_SPI_UPDATE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetSPI_CMD_SPI_UPDATE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetSPI_CMD_SPI_USR(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetSPI_CMD_SPI_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x1000000) >> 24 +} + +// SPI2.SPI_ADDR: Address value register +func (o *SPI2_Type) SetSPI_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_ADDR.Reg, value) +} +func (o *SPI2_Type) GetSPI_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_ADDR.Reg) +} + +// SPI2.SPI_CTRL: SPI control register +func (o *SPI2_Type) SetSPI_CTRL_SPI_DUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_DUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_FREAD_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_FREAD_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_Q_POL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_Q_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_D_POL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_D_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_HOLD_POL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_HOLD_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_WP_POL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_WP_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x1800000)|value<<23) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x1800000) >> 23 +} +func (o *SPI2_Type) SetSPI_CTRL_SPI_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x6000000)|value<<25) +} +func (o *SPI2_Type) GetSPI_CTRL_SPI_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x6000000) >> 25 +} + +// SPI2.SPI_CLOCK: SPI clock control register +func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f +} +func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3c0000)|value<<18) +} +func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3c0000) >> 18 +} +func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI2.SPI_USER: SPI USER control register +func (o *SPI2_Type) SetSPI_USER_SPI_DOUTDIN(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_USER_SPI_DOUTDIN() uint32 { + return volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_USER_SPI_QPI_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_USER_SPI_QPI_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_USER_SPI_OPI_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetSPI_USER_SPI_OPI_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetSPI_USER_SPI_TSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetSPI_USER_SPI_TSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetSPI_USER_SPI_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetSPI_USER_SPI_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetSPI_USER_SPI_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetSPI_USER_SPI_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetSPI_USER_SPI_RSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSPI_USER_SPI_RSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSPI_USER_SPI_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSPI_USER_SPI_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSPI_USER_SPI_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetSPI_USER_SPI_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetSPI_USER_SPI_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetSPI_USER_SPI_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetSPI_USER_SPI_FWRITE_OCT(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetSPI_USER_SPI_FWRITE_OCT() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetSPI_USER_SPI_USR_CONF_NXT(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetSPI_USER_SPI_USR_CONF_NXT() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetSPI_USER_SPI_SIO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetSPI_USER_SPI_SIO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetSPI_USER_SPI_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetSPI_USER_SPI_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetSPI_USER_SPI_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI2_Type) GetSPI_USER_SPI_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI2_Type) SetSPI_USER_SPI_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetSPI_USER_SPI_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetSPI_USER_SPI_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetSPI_USER_SPI_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetSPI_USER_SPI_USR_MISO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetSPI_USER_SPI_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetSPI_USER_SPI_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetSPI_USER_SPI_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetSPI_USER_SPI_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetSPI_USER_SPI_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetSPI_USER_SPI_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetSPI_USER_SPI_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80000000) >> 31 +} + +// SPI2.SPI_USER1: SPI USER control register 1 +func (o *SPI2_Type) SetSPI_USER1_SPI_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xff)|value) +} +func (o *SPI2_Type) GetSPI_USER1_SPI_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xff +} +func (o *SPI2_Type) SetSPI_USER1_SPI_MST_WFULL_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetSPI_USER1_SPI_MST_WFULL_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetSPI_USER1_SPI_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x3e0000)|value<<17) +} +func (o *SPI2_Type) GetSPI_USER1_SPI_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x3e0000) >> 17 +} +func (o *SPI2_Type) SetSPI_USER1_SPI_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x7c00000)|value<<22) +} +func (o *SPI2_Type) GetSPI_USER1_SPI_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x7c00000) >> 22 +} +func (o *SPI2_Type) SetSPI_USER1_SPI_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI2_Type) GetSPI_USER1_SPI_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xf8000000) >> 27 +} + +// SPI2.SPI_USER2: SPI USER control register 2 +func (o *SPI2_Type) SetSPI_USER2_SPI_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI2_Type) GetSPI_USER2_SPI_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xffff +} +func (o *SPI2_Type) SetSPI_USER2_SPI_MST_REMPTY_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetSPI_USER2_SPI_MST_REMPTY_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetSPI_USER2_SPI_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI2_Type) GetSPI_USER2_SPI_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI2.SPI_MS_DLEN: SPI data bit length control register +func (o *SPI2_Type) SetSPI_MS_DLEN_SPI_MS_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MS_DLEN.Reg, volatile.LoadUint32(&o.SPI_MS_DLEN.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetSPI_MS_DLEN_SPI_MS_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_MS_DLEN.Reg) & 0x3ffff +} + +// SPI2.SPI_MISC: SPI misc register +func (o *SPI2_Type) SetSPI_MISC_SPI_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CS3_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CS3_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CS4_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CS4_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CS5_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CS5_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CK_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CK_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_MASTER_CS_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x1f80)|value<<7) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_MASTER_CS_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x1f80) >> 7 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CLK_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CLK_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_ADDR_DTR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_ADDR_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CMD_DTR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CMD_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_SLAVE_CS_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_SLAVE_CS_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_DQS_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_DQS_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetSPI_MISC_SPI_QUAD_DIN_PIN_SWAP(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetSPI_MISC_SPI_QUAD_DIN_PIN_SWAP() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x80000000) >> 31 +} + +// SPI2.SPI_DIN_MODE: SPI input delay mode configuration +func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x3 +} +func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc000) >> 14 +} +func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x10000) >> 16 +} + +// SPI2.SPI_DIN_NUM: SPI input delay number configuration +func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x3 +} +func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc000) >> 14 +} + +// SPI2.SPI_DOUT_MODE: SPI output delay mode configuration +func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_D_DQS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_D_DQS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI2.SPI_DMA_CONF: SPI DMA control register +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_INFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_RX_EOF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_RX_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_RX_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_RX_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_TX_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_TX_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_RX_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_RX_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_BUF_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_BUF_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// SPI2.SPI_DMA_INT_ENA: SPI interrupt enable register +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SEG_MAGIC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SEG_MAGIC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_APP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_APP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_APP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_APP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x100000) >> 20 +} + +// SPI2.SPI_DMA_INT_CLR: SPI interrupt clear register +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SEG_MAGIC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SEG_MAGIC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_APP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_APP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_APP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_APP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x100000) >> 20 +} + +// SPI2.SPI_DMA_INT_RAW: SPI interrupt raw register +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SEG_MAGIC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SEG_MAGIC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_APP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_APP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_APP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_APP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x100000) >> 20 +} + +// SPI2.SPI_DMA_INT_ST: SPI interrupt status register +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SEG_MAGIC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SEG_MAGIC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_APP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_APP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_APP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_APP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x100000) >> 20 +} + +// SPI2.SPI_DMA_INT_SET: SPI interrupt software set register +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SEG_MAGIC_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SEG_MAGIC_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_APP2_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_APP2_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_APP1_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_APP1_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x100000) >> 20 +} + +// SPI2.SPI_W0: SPI CPU-controlled buffer0 +func (o *SPI2_Type) SetSPI_W0(value uint32) { + volatile.StoreUint32(&o.SPI_W0.Reg, value) +} +func (o *SPI2_Type) GetSPI_W0() uint32 { + return volatile.LoadUint32(&o.SPI_W0.Reg) +} + +// SPI2.SPI_W1: SPI CPU-controlled buffer1 +func (o *SPI2_Type) SetSPI_W1(value uint32) { + volatile.StoreUint32(&o.SPI_W1.Reg, value) +} +func (o *SPI2_Type) GetSPI_W1() uint32 { + return volatile.LoadUint32(&o.SPI_W1.Reg) +} + +// SPI2.SPI_W2: SPI CPU-controlled buffer2 +func (o *SPI2_Type) SetSPI_W2(value uint32) { + volatile.StoreUint32(&o.SPI_W2.Reg, value) +} +func (o *SPI2_Type) GetSPI_W2() uint32 { + return volatile.LoadUint32(&o.SPI_W2.Reg) +} + +// SPI2.SPI_W3: SPI CPU-controlled buffer3 +func (o *SPI2_Type) SetSPI_W3(value uint32) { + volatile.StoreUint32(&o.SPI_W3.Reg, value) +} +func (o *SPI2_Type) GetSPI_W3() uint32 { + return volatile.LoadUint32(&o.SPI_W3.Reg) +} + +// SPI2.SPI_W4: SPI CPU-controlled buffer4 +func (o *SPI2_Type) SetSPI_W4(value uint32) { + volatile.StoreUint32(&o.SPI_W4.Reg, value) +} +func (o *SPI2_Type) GetSPI_W4() uint32 { + return volatile.LoadUint32(&o.SPI_W4.Reg) +} + +// SPI2.SPI_W5: SPI CPU-controlled buffer5 +func (o *SPI2_Type) SetSPI_W5(value uint32) { + volatile.StoreUint32(&o.SPI_W5.Reg, value) +} +func (o *SPI2_Type) GetSPI_W5() uint32 { + return volatile.LoadUint32(&o.SPI_W5.Reg) +} + +// SPI2.SPI_W6: SPI CPU-controlled buffer6 +func (o *SPI2_Type) SetSPI_W6(value uint32) { + volatile.StoreUint32(&o.SPI_W6.Reg, value) +} +func (o *SPI2_Type) GetSPI_W6() uint32 { + return volatile.LoadUint32(&o.SPI_W6.Reg) +} + +// SPI2.SPI_W7: SPI CPU-controlled buffer7 +func (o *SPI2_Type) SetSPI_W7(value uint32) { + volatile.StoreUint32(&o.SPI_W7.Reg, value) +} +func (o *SPI2_Type) GetSPI_W7() uint32 { + return volatile.LoadUint32(&o.SPI_W7.Reg) +} + +// SPI2.SPI_W8: SPI CPU-controlled buffer8 +func (o *SPI2_Type) SetSPI_W8(value uint32) { + volatile.StoreUint32(&o.SPI_W8.Reg, value) +} +func (o *SPI2_Type) GetSPI_W8() uint32 { + return volatile.LoadUint32(&o.SPI_W8.Reg) +} + +// SPI2.SPI_W9: SPI CPU-controlled buffer9 +func (o *SPI2_Type) SetSPI_W9(value uint32) { + volatile.StoreUint32(&o.SPI_W9.Reg, value) +} +func (o *SPI2_Type) GetSPI_W9() uint32 { + return volatile.LoadUint32(&o.SPI_W9.Reg) +} + +// SPI2.SPI_W10: SPI CPU-controlled buffer10 +func (o *SPI2_Type) SetSPI_W10(value uint32) { + volatile.StoreUint32(&o.SPI_W10.Reg, value) +} +func (o *SPI2_Type) GetSPI_W10() uint32 { + return volatile.LoadUint32(&o.SPI_W10.Reg) +} + +// SPI2.SPI_W11: SPI CPU-controlled buffer11 +func (o *SPI2_Type) SetSPI_W11(value uint32) { + volatile.StoreUint32(&o.SPI_W11.Reg, value) +} +func (o *SPI2_Type) GetSPI_W11() uint32 { + return volatile.LoadUint32(&o.SPI_W11.Reg) +} + +// SPI2.SPI_W12: SPI CPU-controlled buffer12 +func (o *SPI2_Type) SetSPI_W12(value uint32) { + volatile.StoreUint32(&o.SPI_W12.Reg, value) +} +func (o *SPI2_Type) GetSPI_W12() uint32 { + return volatile.LoadUint32(&o.SPI_W12.Reg) +} + +// SPI2.SPI_W13: SPI CPU-controlled buffer13 +func (o *SPI2_Type) SetSPI_W13(value uint32) { + volatile.StoreUint32(&o.SPI_W13.Reg, value) +} +func (o *SPI2_Type) GetSPI_W13() uint32 { + return volatile.LoadUint32(&o.SPI_W13.Reg) +} + +// SPI2.SPI_W14: SPI CPU-controlled buffer14 +func (o *SPI2_Type) SetSPI_W14(value uint32) { + volatile.StoreUint32(&o.SPI_W14.Reg, value) +} +func (o *SPI2_Type) GetSPI_W14() uint32 { + return volatile.LoadUint32(&o.SPI_W14.Reg) +} + +// SPI2.SPI_W15: SPI CPU-controlled buffer15 +func (o *SPI2_Type) SetSPI_W15(value uint32) { + volatile.StoreUint32(&o.SPI_W15.Reg, value) +} +func (o *SPI2_Type) GetSPI_W15() uint32 { + return volatile.LoadUint32(&o.SPI_W15.Reg) +} + +// SPI2.SPI_SLAVE: SPI slave control register +func (o *SPI2_Type) SetSPI_SLAVE_SPI_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x3 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_CLK_MODE_13(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_CLK_MODE_13() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_RSCK_DATA_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_RSCK_DATA_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_LAST_BYTE_STRB(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0xff000)|value<<12) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_LAST_BYTE_STRB() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0xff000) >> 12 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_DMA_SEG_MAGIC_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x3c00000)|value<<22) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_DMA_SEG_MAGIC_VALUE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x3c00000) >> 22 +} +func (o *SPI2_Type) SetSPI_SLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetSPI_SLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_SOFT_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_SOFT_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_USR_CONF(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_USR_CONF() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetSPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetSPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x20000000) >> 29 +} + +// SPI2.SPI_SLAVE1: SPI slave control register 1 +func (o *SPI2_Type) SetSPI_SLAVE1_SPI_SLV_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetSPI_SLAVE1_SPI_SLV_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetSPI_SLAVE1_SPI_SLV_LAST_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3fc0000)|value<<18) +} +func (o *SPI2_Type) GetSPI_SLAVE1_SPI_SLV_LAST_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3fc0000) >> 18 +} +func (o *SPI2_Type) SetSPI_SLAVE1_SPI_SLV_LAST_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI2_Type) GetSPI_SLAVE1_SPI_SLV_LAST_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0xfc000000) >> 26 +} + +// SPI2.SPI_CLK_GATE: SPI module clock and register clock control +func (o *SPI2_Type) SetSPI_CLK_GATE_SPI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetSPI_CLK_GATE_SPI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x1 +} +func (o *SPI2_Type) SetSPI_CLK_GATE_SPI_MST_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetSPI_CLK_GATE_SPI_MST_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetSPI_CLK_GATE_SPI_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSPI_CLK_GATE_SPI_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x4) >> 2 +} + +// SPI2.SPI_DATE: Version control +func (o *SPI2_Type) SetSPI_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_DATE.Reg, volatile.LoadUint32(&o.SPI_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI2_Type) GetSPI_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 3 +type SPI3_Type struct { + SPI_CMD volatile.Register32 // 0x0 + SPI_ADDR volatile.Register32 // 0x4 + SPI_CTRL volatile.Register32 // 0x8 + SPI_CLOCK volatile.Register32 // 0xC + SPI_USER volatile.Register32 // 0x10 + SPI_USER1 volatile.Register32 // 0x14 + SPI_USER2 volatile.Register32 // 0x18 + SPI_MS_DLEN volatile.Register32 // 0x1C + SPI_MISC volatile.Register32 // 0x20 + SPI_DIN_MODE volatile.Register32 // 0x24 + SPI_DIN_NUM volatile.Register32 // 0x28 + SPI_DOUT_MODE volatile.Register32 // 0x2C + SPI_DMA_CONF volatile.Register32 // 0x30 + SPI_DMA_INT_ENA volatile.Register32 // 0x34 + SPI_DMA_INT_CLR volatile.Register32 // 0x38 + SPI_DMA_INT_RAW volatile.Register32 // 0x3C + SPI_DMA_INT_ST volatile.Register32 // 0x40 + SPI_DMA_INT_SET volatile.Register32 // 0x44 + _ [80]byte + SPI_W0 volatile.Register32 // 0x98 + SPI_W1 volatile.Register32 // 0x9C + SPI_W2 volatile.Register32 // 0xA0 + SPI_W3 volatile.Register32 // 0xA4 + SPI_W4 volatile.Register32 // 0xA8 + SPI_W5 volatile.Register32 // 0xAC + SPI_W6 volatile.Register32 // 0xB0 + SPI_W7 volatile.Register32 // 0xB4 + SPI_W8 volatile.Register32 // 0xB8 + SPI_W9 volatile.Register32 // 0xBC + SPI_W10 volatile.Register32 // 0xC0 + SPI_W11 volatile.Register32 // 0xC4 + SPI_W12 volatile.Register32 // 0xC8 + SPI_W13 volatile.Register32 // 0xCC + SPI_W14 volatile.Register32 // 0xD0 + SPI_W15 volatile.Register32 // 0xD4 + _ [8]byte + SPI_SLAVE volatile.Register32 // 0xE0 + SPI_SLAVE1 volatile.Register32 // 0xE4 + SPI_CLK_GATE volatile.Register32 // 0xE8 + _ [4]byte + SPI_DATE volatile.Register32 // 0xF0 +} + +// SPI3.SPI_CMD: Command control register +func (o *SPI3_Type) SetSPI_CMD_SPI_UPDATE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI3_Type) GetSPI_CMD_SPI_UPDATE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI3_Type) SetSPI_CMD_SPI_USR(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI3_Type) GetSPI_CMD_SPI_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x1000000) >> 24 +} + +// SPI3.SPI_ADDR: Address value register +func (o *SPI3_Type) SetSPI_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_ADDR.Reg, value) +} +func (o *SPI3_Type) GetSPI_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_ADDR.Reg) +} + +// SPI3.SPI_CTRL: SPI control register +func (o *SPI3_Type) SetSPI_CTRL_SPI_DUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_DUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_Q_POL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_Q_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_D_POL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_D_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_HOLD_POL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_HOLD_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_WP_POL(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_WP_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x1800000)|value<<23) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x1800000) >> 23 +} +func (o *SPI3_Type) SetSPI_CTRL_SPI_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x6000000)|value<<25) +} +func (o *SPI3_Type) GetSPI_CTRL_SPI_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x6000000) >> 25 +} + +// SPI3.SPI_CLOCK: SPI clock control register +func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f +} +func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3c0000)|value<<18) +} +func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3c0000) >> 18 +} +func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI3.SPI_USER: SPI USER control register +func (o *SPI3_Type) SetSPI_USER_SPI_DOUTDIN(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_USER_SPI_DOUTDIN() uint32 { + return volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_USER_SPI_QPI_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI3_Type) GetSPI_USER_SPI_QPI_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8) >> 3 +} +func (o *SPI3_Type) SetSPI_USER_SPI_TSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI3_Type) GetSPI_USER_SPI_TSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20) >> 5 +} +func (o *SPI3_Type) SetSPI_USER_SPI_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI3_Type) GetSPI_USER_SPI_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40) >> 6 +} +func (o *SPI3_Type) SetSPI_USER_SPI_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI3_Type) GetSPI_USER_SPI_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80) >> 7 +} +func (o *SPI3_Type) SetSPI_USER_SPI_RSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x100)|value<<8) +} +func (o *SPI3_Type) GetSPI_USER_SPI_RSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x100) >> 8 +} +func (o *SPI3_Type) SetSPI_USER_SPI_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI3_Type) GetSPI_USER_SPI_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x200) >> 9 +} +func (o *SPI3_Type) SetSPI_USER_SPI_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI3_Type) GetSPI_USER_SPI_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000) >> 12 +} +func (o *SPI3_Type) SetSPI_USER_SPI_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI3_Type) GetSPI_USER_SPI_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000) >> 13 +} +func (o *SPI3_Type) SetSPI_USER_SPI_SIO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000)|value<<17) +} +func (o *SPI3_Type) GetSPI_USER_SPI_SIO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000) >> 17 +} +func (o *SPI3_Type) SetSPI_USER_SPI_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI3_Type) GetSPI_USER_SPI_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI3_Type) SetSPI_USER_SPI_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI3_Type) GetSPI_USER_SPI_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI3_Type) SetSPI_USER_SPI_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI3_Type) GetSPI_USER_SPI_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI3_Type) SetSPI_USER_SPI_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI3_Type) GetSPI_USER_SPI_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI3_Type) SetSPI_USER_SPI_USR_MISO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI3_Type) GetSPI_USER_SPI_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI3_Type) SetSPI_USER_SPI_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI3_Type) GetSPI_USER_SPI_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI3_Type) SetSPI_USER_SPI_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI3_Type) GetSPI_USER_SPI_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI3_Type) SetSPI_USER_SPI_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI3_Type) GetSPI_USER_SPI_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80000000) >> 31 +} + +// SPI3.SPI_USER1: SPI USER control register 1 +func (o *SPI3_Type) SetSPI_USER1_SPI_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xff)|value) +} +func (o *SPI3_Type) GetSPI_USER1_SPI_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xff +} +func (o *SPI3_Type) SetSPI_USER1_SPI_MST_WFULL_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x10000)|value<<16) +} +func (o *SPI3_Type) GetSPI_USER1_SPI_MST_WFULL_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x10000) >> 16 +} +func (o *SPI3_Type) SetSPI_USER1_SPI_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x3e0000)|value<<17) +} +func (o *SPI3_Type) GetSPI_USER1_SPI_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x3e0000) >> 17 +} +func (o *SPI3_Type) SetSPI_USER1_SPI_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x7c00000)|value<<22) +} +func (o *SPI3_Type) GetSPI_USER1_SPI_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x7c00000) >> 22 +} +func (o *SPI3_Type) SetSPI_USER1_SPI_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI3_Type) GetSPI_USER1_SPI_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xf8000000) >> 27 +} + +// SPI3.SPI_USER2: SPI USER control register 2 +func (o *SPI3_Type) SetSPI_USER2_SPI_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI3_Type) GetSPI_USER2_SPI_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xffff +} +func (o *SPI3_Type) SetSPI_USER2_SPI_MST_REMPTY_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI3_Type) GetSPI_USER2_SPI_MST_REMPTY_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0x8000000) >> 27 +} +func (o *SPI3_Type) SetSPI_USER2_SPI_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI3_Type) GetSPI_USER2_SPI_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI3.SPI_MS_DLEN: SPI data bit length control register +func (o *SPI3_Type) SetSPI_MS_DLEN_SPI_MS_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_MS_DLEN.Reg, volatile.LoadUint32(&o.SPI_MS_DLEN.Reg)&^(0x3ffff)|value) +} +func (o *SPI3_Type) GetSPI_MS_DLEN_SPI_MS_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_MS_DLEN.Reg) & 0x3ffff +} + +// SPI3.SPI_MISC: SPI misc register +func (o *SPI3_Type) SetSPI_MISC_SPI_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_MISC_SPI_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_MISC_SPI_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI3_Type) GetSPI_MISC_SPI_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x2) >> 1 +} +func (o *SPI3_Type) SetSPI_MISC_SPI_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x4)|value<<2) +} +func (o *SPI3_Type) GetSPI_MISC_SPI_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x4) >> 2 +} +func (o *SPI3_Type) SetSPI_MISC_SPI_CK_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI3_Type) GetSPI_MISC_SPI_CK_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40) >> 6 +} +func (o *SPI3_Type) SetSPI_MISC_SPI_MASTER_CS_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x380)|value<<7) +} +func (o *SPI3_Type) GetSPI_MISC_SPI_MASTER_CS_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x380) >> 7 +} +func (o *SPI3_Type) SetSPI_MISC_SPI_SLAVE_CS_POL(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x800000)|value<<23) +} +func (o *SPI3_Type) GetSPI_MISC_SPI_SLAVE_CS_POL() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x800000) >> 23 +} +func (o *SPI3_Type) SetSPI_MISC_SPI_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI3_Type) GetSPI_MISC_SPI_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x20000000) >> 29 +} +func (o *SPI3_Type) SetSPI_MISC_SPI_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI3_Type) GetSPI_MISC_SPI_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40000000) >> 30 +} +func (o *SPI3_Type) SetSPI_MISC_SPI_QUAD_DIN_PIN_SWAP(value uint32) { + volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI3_Type) GetSPI_MISC_SPI_QUAD_DIN_PIN_SWAP() uint32 { + return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x80000000) >> 31 +} + +// SPI3.SPI_DIN_MODE: SPI input delay mode configuration +func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x3)|value) +} +func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x3 +} +func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc)|value<<2) +} +func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc) >> 2 +} +func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x30)|value<<4) +} +func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x30) >> 4 +} +func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc0) >> 6 +} +func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x10000)|value<<16) +} +func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x10000) >> 16 +} + +// SPI3.SPI_DIN_NUM: SPI input delay number configuration +func (o *SPI3_Type) SetSPI_DIN_NUM_SPI_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI3_Type) GetSPI_DIN_NUM_SPI_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x3 +} +func (o *SPI3_Type) SetSPI_DIN_NUM_SPI_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI3_Type) GetSPI_DIN_NUM_SPI_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI3_Type) SetSPI_DIN_NUM_SPI_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI3_Type) GetSPI_DIN_NUM_SPI_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI3_Type) SetSPI_DIN_NUM_SPI_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI3_Type) GetSPI_DIN_NUM_SPI_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc0) >> 6 +} + +// SPI3.SPI_DOUT_MODE: SPI output delay mode configuration +func (o *SPI3_Type) SetSPI_DOUT_MODE_SPI_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_DOUT_MODE_SPI_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_DOUT_MODE_SPI_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI3_Type) GetSPI_DOUT_MODE_SPI_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI3_Type) SetSPI_DOUT_MODE_SPI_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI3_Type) GetSPI_DOUT_MODE_SPI_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI3_Type) SetSPI_DOUT_MODE_SPI_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI3_Type) GetSPI_DOUT_MODE_SPI_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x8) >> 3 +} + +// SPI3.SPI_DMA_CONF: SPI DMA control register +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_INFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x2) >> 1 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x40000) >> 18 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x80000) >> 19 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x100000) >> 20 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_RX_EOF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_RX_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x200000) >> 21 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_RX_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_RX_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_TX_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_TX_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_RX_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_RX_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x20000000) >> 29 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_BUF_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_BUF_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// SPI3.SPI_DMA_INT_ENA: SPI interrupt enable register +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_APP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_APP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_APP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_APP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x100000) >> 20 +} + +// SPI3.SPI_DMA_INT_CLR: SPI interrupt clear register +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_APP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_APP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_APP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_APP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x100000) >> 20 +} + +// SPI3.SPI_DMA_INT_RAW: SPI interrupt raw register +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_APP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_APP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_APP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_APP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x100000) >> 20 +} + +// SPI3.SPI_DMA_INT_ST: SPI interrupt status register +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_APP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_APP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_APP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_APP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x100000) >> 20 +} + +// SPI3.SPI_DMA_INT_SET: SPI interrupt software set register +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET() uint32 { + return volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x2)|value<<1) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x2) >> 1 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x4)|value<<2) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x4) >> 2 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x8)|value<<3) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x8) >> 3 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x10)|value<<4) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x10) >> 4 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x20)|value<<5) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x20) >> 5 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x40)|value<<6) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x40) >> 6 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x80)|value<<7) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x80) >> 7 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x100)|value<<8) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x100) >> 8 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x200)|value<<9) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x200) >> 9 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x400)|value<<10) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x400) >> 10 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x800)|value<<11) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x800) >> 11 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x1000) >> 12 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x2000) >> 13 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x8000) >> 15 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x10000) >> 16 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x20000) >> 17 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x40000)|value<<18) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x40000) >> 18 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_APP2_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x80000)|value<<19) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_APP2_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x80000) >> 19 +} +func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_APP1_INT_SET(value uint32) { + volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x100000)|value<<20) +} +func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_APP1_INT_SET() uint32 { + return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x100000) >> 20 +} + +// SPI3.SPI_W0: SPI CPU-controlled buffer0 +func (o *SPI3_Type) SetSPI_W0(value uint32) { + volatile.StoreUint32(&o.SPI_W0.Reg, value) +} +func (o *SPI3_Type) GetSPI_W0() uint32 { + return volatile.LoadUint32(&o.SPI_W0.Reg) +} + +// SPI3.SPI_W1: SPI CPU-controlled buffer1 +func (o *SPI3_Type) SetSPI_W1(value uint32) { + volatile.StoreUint32(&o.SPI_W1.Reg, value) +} +func (o *SPI3_Type) GetSPI_W1() uint32 { + return volatile.LoadUint32(&o.SPI_W1.Reg) +} + +// SPI3.SPI_W2: SPI CPU-controlled buffer2 +func (o *SPI3_Type) SetSPI_W2(value uint32) { + volatile.StoreUint32(&o.SPI_W2.Reg, value) +} +func (o *SPI3_Type) GetSPI_W2() uint32 { + return volatile.LoadUint32(&o.SPI_W2.Reg) +} + +// SPI3.SPI_W3: SPI CPU-controlled buffer3 +func (o *SPI3_Type) SetSPI_W3(value uint32) { + volatile.StoreUint32(&o.SPI_W3.Reg, value) +} +func (o *SPI3_Type) GetSPI_W3() uint32 { + return volatile.LoadUint32(&o.SPI_W3.Reg) +} + +// SPI3.SPI_W4: SPI CPU-controlled buffer4 +func (o *SPI3_Type) SetSPI_W4(value uint32) { + volatile.StoreUint32(&o.SPI_W4.Reg, value) +} +func (o *SPI3_Type) GetSPI_W4() uint32 { + return volatile.LoadUint32(&o.SPI_W4.Reg) +} + +// SPI3.SPI_W5: SPI CPU-controlled buffer5 +func (o *SPI3_Type) SetSPI_W5(value uint32) { + volatile.StoreUint32(&o.SPI_W5.Reg, value) +} +func (o *SPI3_Type) GetSPI_W5() uint32 { + return volatile.LoadUint32(&o.SPI_W5.Reg) +} + +// SPI3.SPI_W6: SPI CPU-controlled buffer6 +func (o *SPI3_Type) SetSPI_W6(value uint32) { + volatile.StoreUint32(&o.SPI_W6.Reg, value) +} +func (o *SPI3_Type) GetSPI_W6() uint32 { + return volatile.LoadUint32(&o.SPI_W6.Reg) +} + +// SPI3.SPI_W7: SPI CPU-controlled buffer7 +func (o *SPI3_Type) SetSPI_W7(value uint32) { + volatile.StoreUint32(&o.SPI_W7.Reg, value) +} +func (o *SPI3_Type) GetSPI_W7() uint32 { + return volatile.LoadUint32(&o.SPI_W7.Reg) +} + +// SPI3.SPI_W8: SPI CPU-controlled buffer8 +func (o *SPI3_Type) SetSPI_W8(value uint32) { + volatile.StoreUint32(&o.SPI_W8.Reg, value) +} +func (o *SPI3_Type) GetSPI_W8() uint32 { + return volatile.LoadUint32(&o.SPI_W8.Reg) +} + +// SPI3.SPI_W9: SPI CPU-controlled buffer9 +func (o *SPI3_Type) SetSPI_W9(value uint32) { + volatile.StoreUint32(&o.SPI_W9.Reg, value) +} +func (o *SPI3_Type) GetSPI_W9() uint32 { + return volatile.LoadUint32(&o.SPI_W9.Reg) +} + +// SPI3.SPI_W10: SPI CPU-controlled buffer10 +func (o *SPI3_Type) SetSPI_W10(value uint32) { + volatile.StoreUint32(&o.SPI_W10.Reg, value) +} +func (o *SPI3_Type) GetSPI_W10() uint32 { + return volatile.LoadUint32(&o.SPI_W10.Reg) +} + +// SPI3.SPI_W11: SPI CPU-controlled buffer11 +func (o *SPI3_Type) SetSPI_W11(value uint32) { + volatile.StoreUint32(&o.SPI_W11.Reg, value) +} +func (o *SPI3_Type) GetSPI_W11() uint32 { + return volatile.LoadUint32(&o.SPI_W11.Reg) +} + +// SPI3.SPI_W12: SPI CPU-controlled buffer12 +func (o *SPI3_Type) SetSPI_W12(value uint32) { + volatile.StoreUint32(&o.SPI_W12.Reg, value) +} +func (o *SPI3_Type) GetSPI_W12() uint32 { + return volatile.LoadUint32(&o.SPI_W12.Reg) +} + +// SPI3.SPI_W13: SPI CPU-controlled buffer13 +func (o *SPI3_Type) SetSPI_W13(value uint32) { + volatile.StoreUint32(&o.SPI_W13.Reg, value) +} +func (o *SPI3_Type) GetSPI_W13() uint32 { + return volatile.LoadUint32(&o.SPI_W13.Reg) +} + +// SPI3.SPI_W14: SPI CPU-controlled buffer14 +func (o *SPI3_Type) SetSPI_W14(value uint32) { + volatile.StoreUint32(&o.SPI_W14.Reg, value) +} +func (o *SPI3_Type) GetSPI_W14() uint32 { + return volatile.LoadUint32(&o.SPI_W14.Reg) +} + +// SPI3.SPI_W15: SPI CPU-controlled buffer15 +func (o *SPI3_Type) SetSPI_W15(value uint32) { + volatile.StoreUint32(&o.SPI_W15.Reg, value) +} +func (o *SPI3_Type) GetSPI_W15() uint32 { + return volatile.LoadUint32(&o.SPI_W15.Reg) +} + +// SPI3.SPI_SLAVE: SPI slave control register +func (o *SPI3_Type) SetSPI_SLAVE_SPI_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x3)|value) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x3 +} +func (o *SPI3_Type) SetSPI_SLAVE_SPI_CLK_MODE_13(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_CLK_MODE_13() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI3_Type) SetSPI_SLAVE_SPI_RSCK_DATA_OUT(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_RSCK_DATA_OUT() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x100)|value<<8) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x100) >> 8 +} +func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x200)|value<<9) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x200) >> 9 +} +func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x400)|value<<10) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x400) >> 10 +} +func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x800)|value<<11) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x800) >> 11 +} +func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_LAST_BYTE_STRB(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0xff000)|value<<12) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_LAST_BYTE_STRB() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0xff000) >> 12 +} +func (o *SPI3_Type) SetSPI_SLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI3_Type) GetSPI_SLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4000000) >> 26 +} +func (o *SPI3_Type) SetSPI_SLAVE_SPI_SOFT_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_SOFT_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI3_Type) SetSPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI3_Type) GetSPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x20000000) >> 29 +} + +// SPI3.SPI_SLAVE1: SPI slave control register 1 +func (o *SPI3_Type) SetSPI_SLAVE1_SPI_SLV_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3ffff)|value) +} +func (o *SPI3_Type) GetSPI_SLAVE1_SPI_SLV_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3ffff +} +func (o *SPI3_Type) SetSPI_SLAVE1_SPI_SLV_LAST_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3fc0000)|value<<18) +} +func (o *SPI3_Type) GetSPI_SLAVE1_SPI_SLV_LAST_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3fc0000) >> 18 +} +func (o *SPI3_Type) SetSPI_SLAVE1_SPI_SLV_LAST_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI3_Type) GetSPI_SLAVE1_SPI_SLV_LAST_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0xfc000000) >> 26 +} + +// SPI3.SPI_CLK_GATE: SPI module clock and register clock control +func (o *SPI3_Type) SetSPI_CLK_GATE_SPI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI3_Type) GetSPI_CLK_GATE_SPI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x1 +} +func (o *SPI3_Type) SetSPI_CLK_GATE_SPI_MST_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x2)|value<<1) +} +func (o *SPI3_Type) GetSPI_CLK_GATE_SPI_MST_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x2) >> 1 +} +func (o *SPI3_Type) SetSPI_CLK_GATE_SPI_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x4)|value<<2) +} +func (o *SPI3_Type) GetSPI_CLK_GATE_SPI_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x4) >> 2 +} + +// SPI3.SPI_DATE: Version control +func (o *SPI3_Type) SetSPI_DATE(value uint32) { + volatile.StoreUint32(&o.SPI_DATE.Reg, volatile.LoadUint32(&o.SPI_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI3_Type) GetSPI_DATE() uint32 { + return volatile.LoadUint32(&o.SPI_DATE.Reg) & 0xfffffff +} + +// System Timer +type SYSTIMER_Type struct { + CONF volatile.Register32 // 0x0 + UNIT0_OP volatile.Register32 // 0x4 + UNIT1_OP volatile.Register32 // 0x8 + UNIT0_LOAD_HI volatile.Register32 // 0xC + UNIT0_LOAD_LO volatile.Register32 // 0x10 + UNIT1_LOAD_HI volatile.Register32 // 0x14 + UNIT1_LOAD_LO volatile.Register32 // 0x18 + TARGET0_HI volatile.Register32 // 0x1C + TARGET0_LO volatile.Register32 // 0x20 + TARGET1_HI volatile.Register32 // 0x24 + TARGET1_LO volatile.Register32 // 0x28 + TARGET2_HI volatile.Register32 // 0x2C + TARGET2_LO volatile.Register32 // 0x30 + TARGET0_CONF volatile.Register32 // 0x34 + TARGET1_CONF volatile.Register32 // 0x38 + TARGET2_CONF volatile.Register32 // 0x3C + UNIT0_VALUE_HI volatile.Register32 // 0x40 + UNIT0_VALUE_LO volatile.Register32 // 0x44 + UNIT1_VALUE_HI volatile.Register32 // 0x48 + UNIT1_VALUE_LO volatile.Register32 // 0x4C + COMP0_LOAD volatile.Register32 // 0x50 + COMP1_LOAD volatile.Register32 // 0x54 + COMP2_LOAD volatile.Register32 // 0x58 + UNIT0_LOAD volatile.Register32 // 0x5C + UNIT1_LOAD volatile.Register32 // 0x60 + INT_ENA volatile.Register32 // 0x64 + INT_RAW volatile.Register32 // 0x68 + INT_CLR volatile.Register32 // 0x6C + INT_ST volatile.Register32 // 0x70 + REAL_TARGET0_LO volatile.Register32 // 0x74 + REAL_TARGET0_HI volatile.Register32 // 0x78 + REAL_TARGET1_LO volatile.Register32 // 0x7C + REAL_TARGET1_HI volatile.Register32 // 0x80 + REAL_TARGET2_LO volatile.Register32 // 0x84 + REAL_TARGET2_HI volatile.Register32 // 0x88 + _ [112]byte + DATE volatile.Register32 // 0xFC +} + +// SYSTIMER.CONF: Configure system timer clock +func (o *SYSTIMER_Type) SetCONF_SYSTIMER_CLK_FO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCONF_SYSTIMER_CLK_FO() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetCONF_ETM_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetCONF_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetCONF_TARGET2_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTIMER_Type) GetCONF_TARGET2_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22 +} +func (o *SYSTIMER_Type) SetCONF_TARGET1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTIMER_Type) GetCONF_TARGET1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23 +} +func (o *SYSTIMER_Type) SetCONF_TARGET0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTIMER_Type) GetCONF_TARGET0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000000) >> 26 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000000) >> 27 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000000) >> 28 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_OP: system timer unit0 value update register +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT1_OP: system timer unit1 value update register +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT0_LOAD_HI: system timer unit0 value high load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_LOAD_LO: system timer unit0 value low load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_LO.Reg) +} + +// SYSTIMER.UNIT1_LOAD_HI: system timer unit1 value high load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_LOAD_LO: system timer unit1 value low load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_LO.Reg) +} + +// SYSTIMER.TARGET0_HI: system timer comp0 value high register +func (o *SYSTIMER_Type) SetTARGET0_HI_TIMER_TARGET0_HI(value uint32) { + volatile.StoreUint32(&o.TARGET0_HI.Reg, volatile.LoadUint32(&o.TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_HI_TIMER_TARGET0_HI() uint32 { + return volatile.LoadUint32(&o.TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET0_LO: system timer comp0 value low register +func (o *SYSTIMER_Type) SetTARGET0_LO(value uint32) { + volatile.StoreUint32(&o.TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET0_LO() uint32 { + return volatile.LoadUint32(&o.TARGET0_LO.Reg) +} + +// SYSTIMER.TARGET1_HI: system timer comp1 value high register +func (o *SYSTIMER_Type) SetTARGET1_HI_TIMER_TARGET1_HI(value uint32) { + volatile.StoreUint32(&o.TARGET1_HI.Reg, volatile.LoadUint32(&o.TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_HI_TIMER_TARGET1_HI() uint32 { + return volatile.LoadUint32(&o.TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET1_LO: system timer comp1 value low register +func (o *SYSTIMER_Type) SetTARGET1_LO(value uint32) { + volatile.StoreUint32(&o.TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET1_LO() uint32 { + return volatile.LoadUint32(&o.TARGET1_LO.Reg) +} + +// SYSTIMER.TARGET2_HI: system timer comp2 value high register +func (o *SYSTIMER_Type) SetTARGET2_HI_TIMER_TARGET2_HI(value uint32) { + volatile.StoreUint32(&o.TARGET2_HI.Reg, volatile.LoadUint32(&o.TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_HI_TIMER_TARGET2_HI() uint32 { + return volatile.LoadUint32(&o.TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET2_LO: system timer comp2 value low register +func (o *SYSTIMER_Type) SetTARGET2_LO(value uint32) { + volatile.StoreUint32(&o.TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET2_LO() uint32 { + return volatile.LoadUint32(&o.TARGET2_LO.Reg) +} + +// SYSTIMER.TARGET0_CONF: system timer comp0 target mode register +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET1_CONF: system timer comp1 target mode register +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET2_CONF: system timer comp2 target mode register +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_VALUE_HI: system timer unit0 value high register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_VALUE_LO: system timer unit0 value low register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_LO.Reg) +} + +// SYSTIMER.UNIT1_VALUE_HI: system timer unit1 value high register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_VALUE_LO: system timer unit1 value low register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_LO.Reg) +} + +// SYSTIMER.COMP0_LOAD: system timer comp0 conf sync register +func (o *SYSTIMER_Type) SetCOMP0_LOAD_TIMER_COMP0_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP0_LOAD.Reg, volatile.LoadUint32(&o.COMP0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP0_LOAD_TIMER_COMP0_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP1_LOAD: system timer comp1 conf sync register +func (o *SYSTIMER_Type) SetCOMP1_LOAD_TIMER_COMP1_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP1_LOAD.Reg, volatile.LoadUint32(&o.COMP1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP1_LOAD_TIMER_COMP1_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP2_LOAD: system timer comp2 conf sync register +func (o *SYSTIMER_Type) SetCOMP2_LOAD_TIMER_COMP2_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP2_LOAD.Reg, volatile.LoadUint32(&o.COMP2_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP2_LOAD_TIMER_COMP2_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP2_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT0_LOAD: system timer unit0 conf sync register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_TIMER_UNIT0_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD.Reg, volatile.LoadUint32(&o.UNIT0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_TIMER_UNIT0_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT1_LOAD: system timer unit1 conf sync register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_TIMER_UNIT1_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD.Reg, volatile.LoadUint32(&o.UNIT1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_TIMER_UNIT1_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.INT_ENA: systimer interrupt enable register +func (o *SYSTIMER_Type) SetINT_ENA_TARGET0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_RAW: systimer interrupt raw register +func (o *SYSTIMER_Type) SetINT_RAW_TARGET0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_CLR: systimer interrupt clear register +func (o *SYSTIMER_Type) SetINT_CLR_TARGET0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_ST: systimer interrupt status register +func (o *SYSTIMER_Type) SetINT_ST_TARGET0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// SYSTIMER.REAL_TARGET0_LO: system timer comp0 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET0_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET0_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET0_LO.Reg) +} + +// SYSTIMER.REAL_TARGET0_HI: system timer comp0 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET0_HI_TARGET0_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET0_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET0_HI_TARGET0_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.REAL_TARGET1_LO: system timer comp1 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET1_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET1_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET1_LO.Reg) +} + +// SYSTIMER.REAL_TARGET1_HI: system timer comp1 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET1_HI_TARGET1_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET1_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET1_HI_TARGET1_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.REAL_TARGET2_LO: system timer comp2 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET2_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET2_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET2_LO.Reg) +} + +// SYSTIMER.REAL_TARGET2_HI: system timer comp2 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET2_HI_TARGET2_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET2_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET2_HI_TARGET2_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.DATE: system timer version control register +func (o *SYSTIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *SYSTIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Timer Group 0 +type TIMG_Type struct { + T0CONFIG volatile.Register32 // 0x0 + T0LO volatile.Register32 // 0x4 + T0HI volatile.Register32 // 0x8 + T0UPDATE volatile.Register32 // 0xC + T0ALARMLO volatile.Register32 // 0x10 + T0ALARMHI volatile.Register32 // 0x14 + T0LOADLO volatile.Register32 // 0x18 + T0LOADHI volatile.Register32 // 0x1C + T0LOAD volatile.Register32 // 0x20 + _ [36]byte + WDTCONFIG0 volatile.Register32 // 0x48 + WDTCONFIG1 volatile.Register32 // 0x4C + WDTCONFIG2 volatile.Register32 // 0x50 + WDTCONFIG3 volatile.Register32 // 0x54 + WDTCONFIG4 volatile.Register32 // 0x58 + WDTCONFIG5 volatile.Register32 // 0x5C + WDTFEED volatile.Register32 // 0x60 + WDTWPROTECT volatile.Register32 // 0x64 + RTCCALICFG volatile.Register32 // 0x68 + RTCCALICFG1 volatile.Register32 // 0x6C + INT_ENA_TIMERS volatile.Register32 // 0x70 + INT_RAW_TIMERS volatile.Register32 // 0x74 + INT_ST_TIMERS volatile.Register32 // 0x78 + INT_CLR_TIMERS volatile.Register32 // 0x7C + RTCCALICFG2 volatile.Register32 // 0x80 + _ [116]byte + NTIMERS_DATE volatile.Register32 // 0xF8 + REGCLK volatile.Register32 // 0xFC +} + +// TIMG.T0CONFIG: Timer %s configuration register +func (o *TIMG_Type) SetT0CONFIG_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetT0CONFIG_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetT0CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT0CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT0CONFIG_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetT0CONFIG_DIVCNT_RST() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetT0CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT0CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT0CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT0CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT0CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT0CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT0CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0LO: Timer %s current value, low 32 bits +func (o *TIMG_Type) SetT0LO(value uint32) { + volatile.StoreUint32(&o.T0LO.Reg, value) +} +func (o *TIMG_Type) GetT0LO() uint32 { + return volatile.LoadUint32(&o.T0LO.Reg) +} + +// TIMG.T0HI: Timer %s current value, high 22 bits +func (o *TIMG_Type) SetT0HI_HI(value uint32) { + volatile.StoreUint32(&o.T0HI.Reg, volatile.LoadUint32(&o.T0HI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0HI_HI() uint32 { + return volatile.LoadUint32(&o.T0HI.Reg) & 0x3fffff +} + +// TIMG.T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG +func (o *TIMG_Type) SetT0UPDATE_UPDATE(value uint32) { + volatile.StoreUint32(&o.T0UPDATE.Reg, volatile.LoadUint32(&o.T0UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0UPDATE_UPDATE() uint32 { + return (volatile.LoadUint32(&o.T0UPDATE.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0ALARMLO: Timer %s alarm value, low 32 bits +func (o *TIMG_Type) SetT0ALARMLO(value uint32) { + volatile.StoreUint32(&o.T0ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMLO() uint32 { + return volatile.LoadUint32(&o.T0ALARMLO.Reg) +} + +// TIMG.T0ALARMHI: Timer %s alarm value, high bits +func (o *TIMG_Type) SetT0ALARMHI_ALARM_HI(value uint32) { + volatile.StoreUint32(&o.T0ALARMHI.Reg, volatile.LoadUint32(&o.T0ALARMHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0ALARMHI_ALARM_HI() uint32 { + return volatile.LoadUint32(&o.T0ALARMHI.Reg) & 0x3fffff +} + +// TIMG.T0LOADLO: Timer %s reload value, low 32 bits +func (o *TIMG_Type) SetT0LOADLO(value uint32) { + volatile.StoreUint32(&o.T0LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT0LOADLO() uint32 { + return volatile.LoadUint32(&o.T0LOADLO.Reg) +} + +// TIMG.T0LOADHI: Timer %s reload value, high 22 bits +func (o *TIMG_Type) SetT0LOADHI_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.T0LOADHI.Reg, volatile.LoadUint32(&o.T0LOADHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0LOADHI_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.T0LOADHI.Reg) & 0x3fffff +} + +// TIMG.T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG +func (o *TIMG_Type) SetT0LOAD(value uint32) { + volatile.StoreUint32(&o.T0LOAD.Reg, value) +} +func (o *TIMG_Type) GetT0LOAD() uint32 { + return volatile.LoadUint32(&o.T0LOAD.Reg) +} + +// TIMG.WDTCONFIG0: Watchdog timer configuration register +func (o *TIMG_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x2000)|value<<13) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x2000) >> 13 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x4000)|value<<14) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x4000) >> 14 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x38000)|value<<15) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x38000) >> 15 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c0000)|value<<18) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c0000) >> 18 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200000)|value<<21) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200000) >> 21 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CONF_UPDATE_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400000)|value<<22) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CONF_UPDATE_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400000) >> 22 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1800000)|value<<23) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1800000) >> 23 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x6000000)|value<<25) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x6000000) >> 25 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x18000000)|value<<27) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x18000000) >> 27 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x60000000)|value<<29) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x60000000) >> 29 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// TIMG.WDTCONFIG1: Watchdog timer prescaler register +func (o *TIMG_Type) SetWDTCONFIG1_WDT_DIVCNT_RST(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_DIVCNT_RST() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetWDTCONFIG1_WDT_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_CLK_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0xffff0000) >> 16 +} + +// TIMG.WDTCONFIG2: Watchdog timer stage 0 timeout value +func (o *TIMG_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// TIMG.WDTCONFIG3: Watchdog timer stage 1 timeout value +func (o *TIMG_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// TIMG.WDTCONFIG4: Watchdog timer stage 2 timeout value +func (o *TIMG_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// TIMG.WDTCONFIG5: Watchdog timer stage 3 timeout value +func (o *TIMG_Type) SetWDTCONFIG5(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG5.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG5() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG5.Reg) +} + +// TIMG.WDTFEED: Write to feed the watchdog timer +func (o *TIMG_Type) SetWDTFEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, value) +} +func (o *TIMG_Type) GetWDTFEED() uint32 { + return volatile.LoadUint32(&o.WDTFEED.Reg) +} + +// TIMG.WDTWPROTECT: Watchdog write protect register +func (o *TIMG_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *TIMG_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// TIMG.RTCCALICFG: RTC calibration configure register +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START_CYCLING(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START_CYCLING() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x6000)|value<<13) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x6000) >> 13 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_RDY(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x8000)|value<<15) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_RDY() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x8000) >> 15 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_MAX(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x7fff0000)|value<<16) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_MAX() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x7fff0000) >> 16 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x80000000) >> 31 +} + +// TIMG.RTCCALICFG1: RTC calibration configure1 register +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_VALUE(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_VALUE() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0xffffff80) >> 7 +} + +// TIMG.INT_ENA_TIMERS: Interrupt enable bits +func (o *TIMG_Type) SetINT_ENA_TIMERS_T0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_T1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x4) >> 2 +} + +// TIMG.INT_RAW_TIMERS: Raw interrupt status +func (o *TIMG_Type) SetINT_RAW_TIMERS_T0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_T1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x4) >> 2 +} + +// TIMG.INT_ST_TIMERS: Masked interrupt status +func (o *TIMG_Type) SetINT_ST_TIMERS_T0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_T1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x4) >> 2 +} + +// TIMG.INT_CLR_TIMERS: Interrupt clear bits +func (o *TIMG_Type) SetINT_CLR_TIMERS_T0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_T1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x4) >> 2 +} + +// TIMG.RTCCALICFG2: Timer group calibration register +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x78)|value<<3) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x78) >> 3 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0xffffff80) >> 7 +} + +// TIMG.NTIMERS_DATE: Timer version control register +func (o *TIMG_Type) SetNTIMERS_DATE_NTIMGS_DATE(value uint32) { + volatile.StoreUint32(&o.NTIMERS_DATE.Reg, volatile.LoadUint32(&o.NTIMERS_DATE.Reg)&^(0xfffffff)|value) +} +func (o *TIMG_Type) GetNTIMERS_DATE_NTIMGS_DATE() uint32 { + return volatile.LoadUint32(&o.NTIMERS_DATE.Reg) & 0xfffffff +} + +// TIMG.REGCLK: Timer group clock gate register +func (o *TIMG_Type) SetREGCLK_ETM_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x10000000)|value<<28) +} +func (o *TIMG_Type) GetREGCLK_ETM_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x10000000) >> 28 +} +func (o *TIMG_Type) SetREGCLK_WDT_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetREGCLK_WDT_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetREGCLK_TIMER_CLK_IS_ACTIVE(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetREGCLK_TIMER_CLK_IS_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetREGCLK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetREGCLK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x80000000) >> 31 +} + +// TRACE0 Peripheral +type TRACE_Type struct { + MEM_START_ADDR volatile.Register32 // 0x0 + MEM_END_ADDR volatile.Register32 // 0x4 + MEM_CURRENT_ADDR volatile.Register32 // 0x8 + MEM_ADDR_UPDATE volatile.Register32 // 0xC + FIFO_STATUS volatile.Register32 // 0x10 + INTR_ENA volatile.Register32 // 0x14 + INTR_RAW volatile.Register32 // 0x18 + INTR_CLR volatile.Register32 // 0x1C + TRIGGER volatile.Register32 // 0x20 + CONFIG volatile.Register32 // 0x24 + FILTER_CONTROL volatile.Register32 // 0x28 + FILTER_MATCH_CONTROL volatile.Register32 // 0x2C + FILTER_COMPARATOR_CONTROL volatile.Register32 // 0x30 + FILTER_P_COMPARATOR_MATCH volatile.Register32 // 0x34 + FILTER_S_COMPARATOR_MATCH volatile.Register32 // 0x38 + RESYNC_PROLONGED volatile.Register32 // 0x3C + AHB_CONFIG volatile.Register32 // 0x40 + CLOCK_GATE volatile.Register32 // 0x44 + _ [948]byte + DATE volatile.Register32 // 0x3FC +} + +// TRACE.MEM_START_ADDR: mem start addr +func (o *TRACE_Type) SetMEM_START_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_START_ADDR.Reg, value) +} +func (o *TRACE_Type) GetMEM_START_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_START_ADDR.Reg) +} + +// TRACE.MEM_END_ADDR: mem end addr +func (o *TRACE_Type) SetMEM_END_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_END_ADDR.Reg, value) +} +func (o *TRACE_Type) GetMEM_END_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_END_ADDR.Reg) +} + +// TRACE.MEM_CURRENT_ADDR: mem current addr +func (o *TRACE_Type) SetMEM_CURRENT_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_CURRENT_ADDR.Reg, value) +} +func (o *TRACE_Type) GetMEM_CURRENT_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_CURRENT_ADDR.Reg) +} + +// TRACE.MEM_ADDR_UPDATE: mem addr update +func (o *TRACE_Type) SetMEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE(value uint32) { + volatile.StoreUint32(&o.MEM_ADDR_UPDATE.Reg, volatile.LoadUint32(&o.MEM_ADDR_UPDATE.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetMEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE() uint32 { + return volatile.LoadUint32(&o.MEM_ADDR_UPDATE.Reg) & 0x1 +} + +// TRACE.FIFO_STATUS: fifo status register +func (o *TRACE_Type) SetFIFO_STATUS_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.FIFO_STATUS.Reg, volatile.LoadUint32(&o.FIFO_STATUS.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetFIFO_STATUS_FIFO_EMPTY() uint32 { + return volatile.LoadUint32(&o.FIFO_STATUS.Reg) & 0x1 +} +func (o *TRACE_Type) SetFIFO_STATUS_WORK_STATUS(value uint32) { + volatile.StoreUint32(&o.FIFO_STATUS.Reg, volatile.LoadUint32(&o.FIFO_STATUS.Reg)&^(0x6)|value<<1) +} +func (o *TRACE_Type) GetFIFO_STATUS_WORK_STATUS() uint32 { + return (volatile.LoadUint32(&o.FIFO_STATUS.Reg) & 0x6) >> 1 +} + +// TRACE.INTR_ENA: interrupt enable register +func (o *TRACE_Type) SetINTR_ENA_FIFO_OVERFLOW_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_ENA.Reg, volatile.LoadUint32(&o.INTR_ENA.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetINTR_ENA_FIFO_OVERFLOW_INTR_ENA() uint32 { + return volatile.LoadUint32(&o.INTR_ENA.Reg) & 0x1 +} +func (o *TRACE_Type) SetINTR_ENA_MEM_FULL_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_ENA.Reg, volatile.LoadUint32(&o.INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetINTR_ENA_MEM_FULL_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_ENA.Reg) & 0x2) >> 1 +} + +// TRACE.INTR_RAW: interrupt status register +func (o *TRACE_Type) SetINTR_RAW_FIFO_OVERFLOW_INTR_RAW(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetINTR_RAW_FIFO_OVERFLOW_INTR_RAW() uint32 { + return volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x1 +} +func (o *TRACE_Type) SetINTR_RAW_MEM_FULL_INTR_RAW(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetINTR_RAW_MEM_FULL_INTR_RAW() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x2) >> 1 +} + +// TRACE.INTR_CLR: interrupt clear register +func (o *TRACE_Type) SetINTR_CLR_FIFO_OVERFLOW_INTR_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetINTR_CLR_FIFO_OVERFLOW_INTR_CLR() uint32 { + return volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x1 +} +func (o *TRACE_Type) SetINTR_CLR_MEM_FULL_INTR_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetINTR_CLR_MEM_FULL_INTR_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x2) >> 1 +} + +// TRACE.TRIGGER: trigger register +func (o *TRACE_Type) SetTRIGGER_ON(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetTRIGGER_ON() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} +func (o *TRACE_Type) SetTRIGGER_OFF(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetTRIGGER_OFF() uint32 { + return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x2) >> 1 +} +func (o *TRACE_Type) SetTRIGGER_MEM_LOOP(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x4)|value<<2) +} +func (o *TRACE_Type) GetTRIGGER_MEM_LOOP() uint32 { + return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x4) >> 2 +} +func (o *TRACE_Type) SetTRIGGER_RESTART_ENA(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x8)|value<<3) +} +func (o *TRACE_Type) GetTRIGGER_RESTART_ENA() uint32 { + return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x8) >> 3 +} + +// TRACE.CONFIG: trace configuration register +func (o *TRACE_Type) SetCONFIG_DM_TRIGGER_ENA(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetCONFIG_DM_TRIGGER_ENA() uint32 { + return volatile.LoadUint32(&o.CONFIG.Reg) & 0x1 +} +func (o *TRACE_Type) SetCONFIG_RESET_ENA(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetCONFIG_RESET_ENA() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x2) >> 1 +} +func (o *TRACE_Type) SetCONFIG_HALT_ENA(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x4)|value<<2) +} +func (o *TRACE_Type) GetCONFIG_HALT_ENA() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x4) >> 2 +} +func (o *TRACE_Type) SetCONFIG_STALL_ENA(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8)|value<<3) +} +func (o *TRACE_Type) GetCONFIG_STALL_ENA() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8) >> 3 +} +func (o *TRACE_Type) SetCONFIG_FULL_ADDRESS(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x10)|value<<4) +} +func (o *TRACE_Type) GetCONFIG_FULL_ADDRESS() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x10) >> 4 +} +func (o *TRACE_Type) SetCONFIG_IMPLICIT_EXCEPT(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x20)|value<<5) +} +func (o *TRACE_Type) GetCONFIG_IMPLICIT_EXCEPT() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x20) >> 5 +} + +// TRACE.FILTER_CONTROL: filter control register +func (o *TRACE_Type) SetFILTER_CONTROL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetFILTER_CONTROL_FILTER_EN() uint32 { + return volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x1 +} +func (o *TRACE_Type) SetFILTER_CONTROL_MATCH_COMP(value uint32) { + volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetFILTER_CONTROL_MATCH_COMP() uint32 { + return (volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x2) >> 1 +} +func (o *TRACE_Type) SetFILTER_CONTROL_MATCH_PRIVILEGE(value uint32) { + volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *TRACE_Type) GetFILTER_CONTROL_MATCH_PRIVILEGE() uint32 { + return (volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x4) >> 2 +} +func (o *TRACE_Type) SetFILTER_CONTROL_MATCH_ECAUSE(value uint32) { + volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *TRACE_Type) GetFILTER_CONTROL_MATCH_ECAUSE() uint32 { + return (volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x8) >> 3 +} +func (o *TRACE_Type) SetFILTER_CONTROL_MATCH_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x10)|value<<4) +} +func (o *TRACE_Type) GetFILTER_CONTROL_MATCH_INTERRUPT() uint32 { + return (volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x10) >> 4 +} + +// TRACE.FILTER_MATCH_CONTROL: filter match control register +func (o *TRACE_Type) SetFILTER_MATCH_CONTROL_MATCH_CHOICE_PRIVILEGE(value uint32) { + volatile.StoreUint32(&o.FILTER_MATCH_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetFILTER_MATCH_CONTROL_MATCH_CHOICE_PRIVILEGE() uint32 { + return volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg) & 0x1 +} +func (o *TRACE_Type) SetFILTER_MATCH_CONTROL_MATCH_VALUE_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.FILTER_MATCH_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *TRACE_Type) GetFILTER_MATCH_CONTROL_MATCH_VALUE_INTERRUPT() uint32 { + return (volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg) & 0x2) >> 1 +} +func (o *TRACE_Type) SetFILTER_MATCH_CONTROL_MATCH_CHOICE_ECAUSE(value uint32) { + volatile.StoreUint32(&o.FILTER_MATCH_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg)&^(0xfc)|value<<2) +} +func (o *TRACE_Type) GetFILTER_MATCH_CONTROL_MATCH_CHOICE_ECAUSE() uint32 { + return (volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg) & 0xfc) >> 2 +} + +// TRACE.FILTER_COMPARATOR_CONTROL: filter comparator match control register +func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_P_INPUT(value uint32) { + volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_P_INPUT() uint32 { + return volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x1 +} +func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_P_FUNCTION(value uint32) { + volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x1c)|value<<2) +} +func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_P_FUNCTION() uint32 { + return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x1c) >> 2 +} +func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_P_NOTIFY(value uint32) { + volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x20)|value<<5) +} +func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_P_NOTIFY() uint32 { + return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x20) >> 5 +} +func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_S_INPUT(value uint32) { + volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x100)|value<<8) +} +func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_S_INPUT() uint32 { + return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x100) >> 8 +} +func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_S_FUNCTION(value uint32) { + volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x1c00)|value<<10) +} +func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_S_FUNCTION() uint32 { + return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x1c00) >> 10 +} +func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_S_NOTIFY(value uint32) { + volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x2000)|value<<13) +} +func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_S_NOTIFY() uint32 { + return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x2000) >> 13 +} +func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_MATCH_MODE(value uint32) { + volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x30000)|value<<16) +} +func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_MATCH_MODE() uint32 { + return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x30000) >> 16 +} + +// TRACE.FILTER_P_COMPARATOR_MATCH: primary comparator match value +func (o *TRACE_Type) SetFILTER_P_COMPARATOR_MATCH(value uint32) { + volatile.StoreUint32(&o.FILTER_P_COMPARATOR_MATCH.Reg, value) +} +func (o *TRACE_Type) GetFILTER_P_COMPARATOR_MATCH() uint32 { + return volatile.LoadUint32(&o.FILTER_P_COMPARATOR_MATCH.Reg) +} + +// TRACE.FILTER_S_COMPARATOR_MATCH: secondary comparator match value +func (o *TRACE_Type) SetFILTER_S_COMPARATOR_MATCH(value uint32) { + volatile.StoreUint32(&o.FILTER_S_COMPARATOR_MATCH.Reg, value) +} +func (o *TRACE_Type) GetFILTER_S_COMPARATOR_MATCH() uint32 { + return volatile.LoadUint32(&o.FILTER_S_COMPARATOR_MATCH.Reg) +} + +// TRACE.RESYNC_PROLONGED: resync configuration register +func (o *TRACE_Type) SetRESYNC_PROLONGED(value uint32) { + volatile.StoreUint32(&o.RESYNC_PROLONGED.Reg, volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg)&^(0xffffff)|value) +} +func (o *TRACE_Type) GetRESYNC_PROLONGED() uint32 { + return volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg) & 0xffffff +} +func (o *TRACE_Type) SetRESYNC_PROLONGED_RESYNC_MODE(value uint32) { + volatile.StoreUint32(&o.RESYNC_PROLONGED.Reg, volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg)&^(0x3000000)|value<<24) +} +func (o *TRACE_Type) GetRESYNC_PROLONGED_RESYNC_MODE() uint32 { + return (volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg) & 0x3000000) >> 24 +} + +// TRACE.AHB_CONFIG: AHB config register +func (o *TRACE_Type) SetAHB_CONFIG_HBURST(value uint32) { + volatile.StoreUint32(&o.AHB_CONFIG.Reg, volatile.LoadUint32(&o.AHB_CONFIG.Reg)&^(0x7)|value) +} +func (o *TRACE_Type) GetAHB_CONFIG_HBURST() uint32 { + return volatile.LoadUint32(&o.AHB_CONFIG.Reg) & 0x7 +} +func (o *TRACE_Type) SetAHB_CONFIG_MAX_INCR(value uint32) { + volatile.StoreUint32(&o.AHB_CONFIG.Reg, volatile.LoadUint32(&o.AHB_CONFIG.Reg)&^(0x38)|value<<3) +} +func (o *TRACE_Type) GetAHB_CONFIG_MAX_INCR() uint32 { + return (volatile.LoadUint32(&o.AHB_CONFIG.Reg) & 0x38) >> 3 +} + +// TRACE.CLOCK_GATE: Clock gate control register +func (o *TRACE_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *TRACE_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// TRACE.DATE: Version control register +func (o *TRACE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *TRACE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power Temperature Sensor +type TSENS_Type struct { + CTRL volatile.Register32 // 0x0 + CTRL2 volatile.Register32 // 0x4 + INT_RAW volatile.Register32 // 0x8 + INT_ST volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + INT_CLR volatile.Register32 // 0x14 + CLK_CONF volatile.Register32 // 0x18 + INT_ENA_W1TS volatile.Register32 // 0x1C + INT_ENA_W1TC volatile.Register32 // 0x20 + WAKEUP_CTRL volatile.Register32 // 0x24 + SAMPLE_RATE volatile.Register32 // 0x28 + RND_ECO_LOW volatile.Register32 // 0x2C + RND_ECO_HIGH volatile.Register32 // 0x30 + RND_ECO_CS volatile.Register32 // 0x34 +} + +// TSENS.CTRL: Tsens configuration. +func (o *TSENS_Type) SetCTRL_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xff)|value) +} +func (o *TSENS_Type) GetCTRL_OUT() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0xff +} +func (o *TSENS_Type) SetCTRL_READY(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *TSENS_Type) GetCTRL_READY() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *TSENS_Type) SetCTRL_SAMPLE_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *TSENS_Type) GetCTRL_SAMPLE_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *TSENS_Type) SetCTRL_WAKEUP_MASK(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *TSENS_Type) GetCTRL_WAKEUP_MASK() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *TSENS_Type) SetCTRL_INT_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *TSENS_Type) GetCTRL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000) >> 12 +} +func (o *TSENS_Type) SetCTRL_IN_INV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *TSENS_Type) GetCTRL_IN_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13 +} +func (o *TSENS_Type) SetCTRL_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *TSENS_Type) GetCTRL_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *TSENS_Type) SetCTRL_POWER_UP(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *TSENS_Type) GetCTRL_POWER_UP() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400000) >> 22 +} +func (o *TSENS_Type) SetCTRL_POWER_UP_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *TSENS_Type) GetCTRL_POWER_UP_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} + +// TSENS.CTRL2: Tsens configuration. +func (o *TSENS_Type) SetCTRL2_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff)|value) +} +func (o *TSENS_Type) GetCTRL2_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff +} +func (o *TSENS_Type) SetCTRL2_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x3000)|value<<12) +} +func (o *TSENS_Type) GetCTRL2_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x3000) >> 12 +} +func (o *TSENS_Type) SetCTRL2_CLK_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *TSENS_Type) GetCTRL2_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x4000) >> 14 +} + +// TSENS.INT_RAW: Tsens interrupt raw registers. +func (o *TSENS_Type) SetINT_RAW_COCPU_TSENS_WAKE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *TSENS_Type) GetINT_RAW_COCPU_TSENS_WAKE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} + +// TSENS.INT_ST: Tsens interrupt status registers. +func (o *TSENS_Type) SetINT_ST_COCPU_TSENS_WAKE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *TSENS_Type) GetINT_ST_COCPU_TSENS_WAKE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} + +// TSENS.INT_ENA: Tsens interrupt enable registers. +func (o *TSENS_Type) SetINT_ENA_COCPU_TSENS_WAKE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *TSENS_Type) GetINT_ENA_COCPU_TSENS_WAKE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// TSENS.INT_CLR: Tsens interrupt clear registers. +func (o *TSENS_Type) SetINT_CLR_COCPU_TSENS_WAKE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *TSENS_Type) GetINT_CLR_COCPU_TSENS_WAKE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} + +// TSENS.CLK_CONF: Tsens regbank configuration registers. +func (o *TSENS_Type) SetCLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1)|value) +} +func (o *TSENS_Type) GetCLK_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1 +} + +// TSENS.INT_ENA_W1TS: Tsens wakeup interrupt enable assert. +func (o *TSENS_Type) SetINT_ENA_W1TS_COCPU_TSENS_WAKE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x1)|value) +} +func (o *TSENS_Type) GetINT_ENA_W1TS_COCPU_TSENS_WAKE_INT_ENA_W1TS() uint32 { + return volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x1 +} + +// TSENS.INT_ENA_W1TC: Tsens wakeup interrupt enable deassert. +func (o *TSENS_Type) SetINT_ENA_W1TC_COCPU_TSENS_WAKE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x1)|value) +} +func (o *TSENS_Type) GetINT_ENA_W1TC_COCPU_TSENS_WAKE_INT_ENA_W1TC() uint32 { + return volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x1 +} + +// TSENS.WAKEUP_CTRL: Tsens wakeup control registers. +func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_TH_LOW(value uint32) { + volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0xff)|value) +} +func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_TH_LOW() uint32 { + return volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0xff +} +func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_TH_HIGH(value uint32) { + volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_TH_HIGH() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_OVER_UPPER_TH(value uint32) { + volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_OVER_UPPER_TH() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_EN(value uint32) { + volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_EN() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_MODE(value uint32) { + volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_MODE() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0x80000000) >> 31 +} + +// TSENS.SAMPLE_RATE: Hardware automatic sampling control registers. +func (o *TSENS_Type) SetSAMPLE_RATE(value uint32) { + volatile.StoreUint32(&o.SAMPLE_RATE.Reg, volatile.LoadUint32(&o.SAMPLE_RATE.Reg)&^(0xffff)|value) +} +func (o *TSENS_Type) GetSAMPLE_RATE() uint32 { + return volatile.LoadUint32(&o.SAMPLE_RATE.Reg) & 0xffff +} + +// TSENS.RND_ECO_LOW: N/A +func (o *TSENS_Type) SetRND_ECO_LOW(value uint32) { + volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value) +} +func (o *TSENS_Type) GetRND_ECO_LOW() uint32 { + return volatile.LoadUint32(&o.RND_ECO_LOW.Reg) +} + +// TSENS.RND_ECO_HIGH: N/A +func (o *TSENS_Type) SetRND_ECO_HIGH(value uint32) { + volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value) +} +func (o *TSENS_Type) GetRND_ECO_HIGH() uint32 { + return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg) +} + +// TSENS.RND_ECO_CS: N/A +func (o *TSENS_Type) SetRND_ECO_CS_RND_ECO_EN(value uint32) { + volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x1)|value) +} +func (o *TSENS_Type) GetRND_ECO_CS_RND_ECO_EN() uint32 { + return volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x1 +} +func (o *TSENS_Type) SetRND_ECO_CS_RND_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x2)|value<<1) +} +func (o *TSENS_Type) GetRND_ECO_CS_RND_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x2) >> 1 +} + +// Two-Wire Automotive Interface +type TWAI_Type struct { + MODE volatile.Register32 // 0x0 + CMD volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + INTERRUPT volatile.Register32 // 0xC + INTERRUPT_ENABLE volatile.Register32 // 0x10 + _ [4]byte + BUS_TIMING_0 volatile.Register32 // 0x18 + BUS_TIMING_1 volatile.Register32 // 0x1C + _ [12]byte + ARB_LOST_CAP volatile.Register32 // 0x2C + ERR_CODE_CAP volatile.Register32 // 0x30 + ERR_WARNING_LIMIT volatile.Register32 // 0x34 + RX_ERR_CNT volatile.Register32 // 0x38 + TX_ERR_CNT volatile.Register32 // 0x3C + DATA_0 volatile.Register32 // 0x40 + DATA_1 volatile.Register32 // 0x44 + DATA_2 volatile.Register32 // 0x48 + DATA_3 volatile.Register32 // 0x4C + DATA_4 volatile.Register32 // 0x50 + DATA_5 volatile.Register32 // 0x54 + DATA_6 volatile.Register32 // 0x58 + DATA_7 volatile.Register32 // 0x5C + DATA_8 volatile.Register32 // 0x60 + DATA_9 volatile.Register32 // 0x64 + DATA_10 volatile.Register32 // 0x68 + DATA_11 volatile.Register32 // 0x6C + DATA_12 volatile.Register32 // 0x70 + RX_MESSAGE_COUNTER volatile.Register32 // 0x74 + _ [4]byte + CLOCK_DIVIDER volatile.Register32 // 0x7C + SW_STANDBY_CFG volatile.Register32 // 0x80 + HW_CFG volatile.Register32 // 0x84 + HW_STANDBY_CNT volatile.Register32 // 0x88 + IDLE_INTR_CNT volatile.Register32 // 0x8C + ECO_CFG volatile.Register32 // 0x90 + TIMESTAMP_DATA volatile.Register32 // 0x94 + TIMESTAMP_PRESCALER volatile.Register32 // 0x98 + TIMESTAMP_CFG volatile.Register32 // 0x9C +} + +// TWAI.MODE: TWAI mode register. +func (o *TWAI_Type) SetMODE_RESET_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetMODE_RESET_MODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x1 +} +func (o *TWAI_Type) SetMODE_LISTEN_ONLY_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetMODE_LISTEN_ONLY_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetMODE_SELF_TEST_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetMODE_SELF_TEST_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetMODE_ACCEPTANCE_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetMODE_ACCEPTANCE_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x8) >> 3 +} + +// TWAI.CMD: TWAI command register. +func (o *TWAI_Type) SetCMD_TX_REQUEST(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetCMD_TX_REQUEST() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *TWAI_Type) SetCMD_ABORT_TX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetCMD_ABORT_TX() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetCMD_RELEASE_BUFFER(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetCMD_RELEASE_BUFFER() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetCMD_CLEAR_DATA_OVERRUN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetCMD_CLEAR_DATA_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetCMD_SELF_RX_REQUEST(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetCMD_SELF_RX_REQUEST() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10) >> 4 +} + +// TWAI.STATUS: TWAI status register. +func (o *TWAI_Type) SetSTATUS_RECEIVE_BUFFER(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSTATUS_RECEIVE_BUFFER() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *TWAI_Type) SetSTATUS_OVERRUN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSTATUS_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetSTATUS_TRANSMIT_BUFFER(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetSTATUS_TRANSMIT_BUFFER() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetSTATUS_TRANSMISSION_COMPLETE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetSTATUS_TRANSMISSION_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetSTATUS_RECEIVE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetSTATUS_RECEIVE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *TWAI_Type) SetSTATUS_TRANSMIT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetSTATUS_TRANSMIT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetSTATUS_ERR(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetSTATUS_ERR() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetSTATUS_NODE_BUS_OFF(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetSTATUS_NODE_BUS_OFF() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetSTATUS_MISS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetSTATUS_MISS() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} + +// TWAI.INTERRUPT: Interrupt signals' register. +func (o *TWAI_Type) SetINTERRUPT_RECEIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINTERRUPT_RECEIVE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x1 +} +func (o *TWAI_Type) SetINTERRUPT_TRANSMIT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINTERRUPT_TRANSMIT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINTERRUPT_ERR_WARNING_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINTERRUPT_ERR_WARNING_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINTERRUPT_DATA_OVERRUN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINTERRUPT_DATA_OVERRUN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINTERRUPT_TS_COUNTER_OVFL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetINTERRUPT_TS_COUNTER_OVFL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x10) >> 4 +} +func (o *TWAI_Type) SetINTERRUPT_ERR_PASSIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINTERRUPT_ERR_PASSIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINTERRUPT_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINTERRUPT_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINTERRUPT_BUS_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINTERRUPT_BUS_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetINTERRUPT_IDLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetINTERRUPT_IDLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x100) >> 8 +} + +// TWAI.INTERRUPT_ENABLE: Interrupt enable register. +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x1 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_TS_COUNTER_OVFL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_TS_COUNTER_OVFL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x10) >> 4 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_BUS_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_BUS_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetINTERRUPT_ENABLE_IDLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetINTERRUPT_ENABLE_IDLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x100) >> 8 +} + +// TWAI.BUS_TIMING_0: Bit timing configuration register 0. +func (o *TWAI_Type) SetBUS_TIMING_0_BAUD_PRESC(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0x3fff)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_0_BAUD_PRESC() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0x3fff +} +func (o *TWAI_Type) SetBUS_TIMING_0_SYNC_JUMP_WIDTH(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0xc000)|value<<14) +} +func (o *TWAI_Type) GetBUS_TIMING_0_SYNC_JUMP_WIDTH() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0xc000) >> 14 +} + +// TWAI.BUS_TIMING_1: Bit timing configuration register 1. +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEGMENT1(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0xf)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEGMENT1() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0xf +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEGMENT2(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x70)|value<<4) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEGMENT2() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x70) >> 4 +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SAMPLING(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SAMPLING() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x80) >> 7 +} + +// TWAI.ARB_LOST_CAP: TWAI arbiter lost capture register. +func (o *TWAI_Type) SetARB_LOST_CAP_ARBITRATION_LOST_CAPTURE(value uint32) { + volatile.StoreUint32(&o.ARB_LOST_CAP.Reg, volatile.LoadUint32(&o.ARB_LOST_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetARB_LOST_CAP_ARBITRATION_LOST_CAPTURE() uint32 { + return volatile.LoadUint32(&o.ARB_LOST_CAP.Reg) & 0x1f +} + +// TWAI.ERR_CODE_CAP: TWAI error info capture register. +func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT() uint32 { + return volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x1f +} +func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0xc0)|value<<6) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0xc0) >> 6 +} + +// TWAI.ERR_WARNING_LIMIT: TWAI error threshold configuration register. +func (o *TWAI_Type) SetERR_WARNING_LIMIT(value uint32) { + volatile.StoreUint32(&o.ERR_WARNING_LIMIT.Reg, volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetERR_WARNING_LIMIT() uint32 { + return volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg) & 0xff +} + +// TWAI.RX_ERR_CNT: Rx error counter register. +func (o *TWAI_Type) SetRX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ERR_CNT.Reg, volatile.LoadUint32(&o.RX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetRX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.RX_ERR_CNT.Reg) & 0xff +} + +// TWAI.TX_ERR_CNT: Tx error counter register. +func (o *TWAI_Type) SetTX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ERR_CNT.Reg, volatile.LoadUint32(&o.TX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetTX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.TX_ERR_CNT.Reg) & 0xff +} + +// TWAI.DATA_0: Data register 0. +func (o *TWAI_Type) SetDATA_0(value uint32) { + volatile.StoreUint32(&o.DATA_0.Reg, volatile.LoadUint32(&o.DATA_0.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_0() uint32 { + return volatile.LoadUint32(&o.DATA_0.Reg) & 0xff +} + +// TWAI.DATA_1: Data register 1. +func (o *TWAI_Type) SetDATA_1(value uint32) { + volatile.StoreUint32(&o.DATA_1.Reg, volatile.LoadUint32(&o.DATA_1.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_1() uint32 { + return volatile.LoadUint32(&o.DATA_1.Reg) & 0xff +} + +// TWAI.DATA_2: Data register 2. +func (o *TWAI_Type) SetDATA_2(value uint32) { + volatile.StoreUint32(&o.DATA_2.Reg, volatile.LoadUint32(&o.DATA_2.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_2() uint32 { + return volatile.LoadUint32(&o.DATA_2.Reg) & 0xff +} + +// TWAI.DATA_3: Data register 3. +func (o *TWAI_Type) SetDATA_3(value uint32) { + volatile.StoreUint32(&o.DATA_3.Reg, volatile.LoadUint32(&o.DATA_3.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_3() uint32 { + return volatile.LoadUint32(&o.DATA_3.Reg) & 0xff +} + +// TWAI.DATA_4: Data register 4. +func (o *TWAI_Type) SetDATA_4(value uint32) { + volatile.StoreUint32(&o.DATA_4.Reg, volatile.LoadUint32(&o.DATA_4.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_4() uint32 { + return volatile.LoadUint32(&o.DATA_4.Reg) & 0xff +} + +// TWAI.DATA_5: Data register 5. +func (o *TWAI_Type) SetDATA_5(value uint32) { + volatile.StoreUint32(&o.DATA_5.Reg, volatile.LoadUint32(&o.DATA_5.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_5() uint32 { + return volatile.LoadUint32(&o.DATA_5.Reg) & 0xff +} + +// TWAI.DATA_6: Data register 6. +func (o *TWAI_Type) SetDATA_6(value uint32) { + volatile.StoreUint32(&o.DATA_6.Reg, volatile.LoadUint32(&o.DATA_6.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_6() uint32 { + return volatile.LoadUint32(&o.DATA_6.Reg) & 0xff +} + +// TWAI.DATA_7: Data register 7. +func (o *TWAI_Type) SetDATA_7(value uint32) { + volatile.StoreUint32(&o.DATA_7.Reg, volatile.LoadUint32(&o.DATA_7.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_7() uint32 { + return volatile.LoadUint32(&o.DATA_7.Reg) & 0xff +} + +// TWAI.DATA_8: Data register 8. +func (o *TWAI_Type) SetDATA_8(value uint32) { + volatile.StoreUint32(&o.DATA_8.Reg, volatile.LoadUint32(&o.DATA_8.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_8() uint32 { + return volatile.LoadUint32(&o.DATA_8.Reg) & 0xff +} + +// TWAI.DATA_9: Data register 9. +func (o *TWAI_Type) SetDATA_9(value uint32) { + volatile.StoreUint32(&o.DATA_9.Reg, volatile.LoadUint32(&o.DATA_9.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_9() uint32 { + return volatile.LoadUint32(&o.DATA_9.Reg) & 0xff +} + +// TWAI.DATA_10: Data register 10. +func (o *TWAI_Type) SetDATA_10(value uint32) { + volatile.StoreUint32(&o.DATA_10.Reg, volatile.LoadUint32(&o.DATA_10.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_10() uint32 { + return volatile.LoadUint32(&o.DATA_10.Reg) & 0xff +} + +// TWAI.DATA_11: Data register 11. +func (o *TWAI_Type) SetDATA_11(value uint32) { + volatile.StoreUint32(&o.DATA_11.Reg, volatile.LoadUint32(&o.DATA_11.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_11() uint32 { + return volatile.LoadUint32(&o.DATA_11.Reg) & 0xff +} + +// TWAI.DATA_12: Data register 12. +func (o *TWAI_Type) SetDATA_12(value uint32) { + volatile.StoreUint32(&o.DATA_12.Reg, volatile.LoadUint32(&o.DATA_12.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_12() uint32 { + return volatile.LoadUint32(&o.DATA_12.Reg) & 0xff +} + +// TWAI.RX_MESSAGE_COUNTER: Received message counter register. +func (o *TWAI_Type) SetRX_MESSAGE_COUNTER(value uint32) { + volatile.StoreUint32(&o.RX_MESSAGE_COUNTER.Reg, volatile.LoadUint32(&o.RX_MESSAGE_COUNTER.Reg)&^(0x7f)|value) +} +func (o *TWAI_Type) GetRX_MESSAGE_COUNTER() uint32 { + return volatile.LoadUint32(&o.RX_MESSAGE_COUNTER.Reg) & 0x7f +} + +// TWAI.CLOCK_DIVIDER: Clock divider register. +func (o *TWAI_Type) SetCLOCK_DIVIDER_CD(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CD() uint32 { + return volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0xff +} +func (o *TWAI_Type) SetCLOCK_DIVIDER_CLOCK_OFF(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CLOCK_OFF() uint32 { + return (volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0x100) >> 8 +} + +// TWAI.SW_STANDBY_CFG: Software configure standby pin directly. +func (o *TWAI_Type) SetSW_STANDBY_CFG_SW_STANDBY_EN(value uint32) { + volatile.StoreUint32(&o.SW_STANDBY_CFG.Reg, volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSW_STANDBY_CFG_SW_STANDBY_EN() uint32 { + return volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg) & 0x1 +} +func (o *TWAI_Type) SetSW_STANDBY_CFG_SW_STANDBY_CLR(value uint32) { + volatile.StoreUint32(&o.SW_STANDBY_CFG.Reg, volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSW_STANDBY_CFG_SW_STANDBY_CLR() uint32 { + return (volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg) & 0x2) >> 1 +} + +// TWAI.HW_CFG: Hardware configure standby pin. +func (o *TWAI_Type) SetHW_CFG_HW_STANDBY_EN(value uint32) { + volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetHW_CFG_HW_STANDBY_EN() uint32 { + return volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1 +} + +// TWAI.HW_STANDBY_CNT: Configure standby counter. +func (o *TWAI_Type) SetHW_STANDBY_CNT(value uint32) { + volatile.StoreUint32(&o.HW_STANDBY_CNT.Reg, value) +} +func (o *TWAI_Type) GetHW_STANDBY_CNT() uint32 { + return volatile.LoadUint32(&o.HW_STANDBY_CNT.Reg) +} + +// TWAI.IDLE_INTR_CNT: Configure idle interrupt counter. +func (o *TWAI_Type) SetIDLE_INTR_CNT(value uint32) { + volatile.StoreUint32(&o.IDLE_INTR_CNT.Reg, value) +} +func (o *TWAI_Type) GetIDLE_INTR_CNT() uint32 { + return volatile.LoadUint32(&o.IDLE_INTR_CNT.Reg) +} + +// TWAI.ECO_CFG: ECO configuration register. +func (o *TWAI_Type) SetECO_CFG_RDN_ENA(value uint32) { + volatile.StoreUint32(&o.ECO_CFG.Reg, volatile.LoadUint32(&o.ECO_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetECO_CFG_RDN_ENA() uint32 { + return volatile.LoadUint32(&o.ECO_CFG.Reg) & 0x1 +} +func (o *TWAI_Type) SetECO_CFG_RDN_RESULT(value uint32) { + volatile.StoreUint32(&o.ECO_CFG.Reg, volatile.LoadUint32(&o.ECO_CFG.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetECO_CFG_RDN_RESULT() uint32 { + return (volatile.LoadUint32(&o.ECO_CFG.Reg) & 0x2) >> 1 +} + +// TWAI.TIMESTAMP_DATA: Timestamp data register +func (o *TWAI_Type) SetTIMESTAMP_DATA(value uint32) { + volatile.StoreUint32(&o.TIMESTAMP_DATA.Reg, value) +} +func (o *TWAI_Type) GetTIMESTAMP_DATA() uint32 { + return volatile.LoadUint32(&o.TIMESTAMP_DATA.Reg) +} + +// TWAI.TIMESTAMP_PRESCALER: Timestamp configuration register +func (o *TWAI_Type) SetTIMESTAMP_PRESCALER_TS_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TIMESTAMP_PRESCALER.Reg, volatile.LoadUint32(&o.TIMESTAMP_PRESCALER.Reg)&^(0xffff)|value) +} +func (o *TWAI_Type) GetTIMESTAMP_PRESCALER_TS_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.TIMESTAMP_PRESCALER.Reg) & 0xffff +} + +// TWAI.TIMESTAMP_CFG: Timestamp configuration register +func (o *TWAI_Type) SetTIMESTAMP_CFG_TS_ENABLE(value uint32) { + volatile.StoreUint32(&o.TIMESTAMP_CFG.Reg, volatile.LoadUint32(&o.TIMESTAMP_CFG.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetTIMESTAMP_CFG_TS_ENABLE() uint32 { + return volatile.LoadUint32(&o.TIMESTAMP_CFG.Reg) & 0x1 +} + +// UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +type UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV_SYNC volatile.Register32 // 0x14 + RX_FILT volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0_SYNC volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + _ [4]byte + HWFC_CONF_SYNC volatile.Register32 // 0x2C + SLEEP_CONF0 volatile.Register32 // 0x30 + SLEEP_CONF1 volatile.Register32 // 0x34 + SLEEP_CONF2 volatile.Register32 // 0x38 + SWFC_CONF0_SYNC volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + TXBRK_CONF_SYNC volatile.Register32 // 0x44 + IDLE_CONF_SYNC volatile.Register32 // 0x48 + RS485_CONF_SYNC volatile.Register32 // 0x4C + AT_CMD_PRECNT_SYNC volatile.Register32 // 0x50 + AT_CMD_POSTCNT_SYNC volatile.Register32 // 0x54 + AT_CMD_GAPTOUT_SYNC volatile.Register32 // 0x58 + AT_CMD_CHAR_SYNC volatile.Register32 // 0x5C + MEM_CONF volatile.Register32 // 0x60 + TOUT_CONF_SYNC volatile.Register32 // 0x64 + MEM_TX_STATUS volatile.Register32 // 0x68 + MEM_RX_STATUS volatile.Register32 // 0x6C + FSM_STATUS volatile.Register32 // 0x70 + POSPULSE volatile.Register32 // 0x74 + NEGPULSE volatile.Register32 // 0x78 + LOWPULSE volatile.Register32 // 0x7C + HIGHPULSE volatile.Register32 // 0x80 + RXD_CNT volatile.Register32 // 0x84 + CLK_CONF volatile.Register32 // 0x88 + DATE volatile.Register32 // 0x8C + AFIFO_STATUS volatile.Register32 // 0x90 + _ [4]byte + REG_UPDATE volatile.Register32 // 0x98 + ID volatile.Register32 // 0x9C +} + +// UART.FIFO: FIFO data register +func (o *UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// UART.INT_RAW: Raw interrupt status +func (o *UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_RAW_RS485_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_RAW_RS485_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_RAW_RS485_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_RAW_RS485_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_RAW_RS485_CLASH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_RAW_RS485_CLASH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// UART.INT_ST: Masked interrupt status +func (o *UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ST_RS485_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ST_RS485_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ST_RS485_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ST_RS485_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ST_RS485_CLASH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ST_RS485_CLASH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// UART.INT_ENA: Interrupt enable bits +func (o *UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ENA_RS485_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ENA_RS485_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ENA_RS485_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ENA_RS485_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ENA_RS485_CLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ENA_RS485_CLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// UART.INT_CLR: Interrupt clear bits +func (o *UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_CLR_RS485_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_CLR_RS485_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_CLR_RS485_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_CLR_RS485_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_CLR_RS485_CLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_CLR_RS485_CLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// UART.CLKDIV_SYNC: Clock divider configuration +func (o *UART_Type) SetCLKDIV_SYNC_CLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetCLKDIV_SYNC_CLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xfff +} +func (o *UART_Type) SetCLKDIV_SYNC_CLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xf00000)|value<<20) +} +func (o *UART_Type) GetCLKDIV_SYNC_CLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xf00000) >> 20 +} + +// UART.RX_FILT: Rx Filter configuration +func (o *UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT() uint32 { + return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff +} +func (o *UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8 +} + +// UART.STATUS: UART status register +func (o *UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xff +} +func (o *UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xff0000) >> 16 +} +func (o *UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// UART.CONF0_SYNC: a +func (o *UART_Type) SetCONF0_SYNC_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetCONF0_SYNC_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1 +} +func (o *UART_Type) SetCONF0_SYNC_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetCONF0_SYNC_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetCONF0_SYNC_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *UART_Type) GetCONF0_SYNC_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0xc) >> 2 +} +func (o *UART_Type) SetCONF0_SYNC_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x30)|value<<4) +} +func (o *UART_Type) GetCONF0_SYNC_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x30) >> 4 +} +func (o *UART_Type) SetCONF0_SYNC_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetCONF0_SYNC_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetCONF0_SYNC_IRDA_DPLX(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetCONF0_SYNC_IRDA_DPLX() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetCONF0_SYNC_IRDA_TX_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetCONF0_SYNC_IRDA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetCONF0_SYNC_IRDA_WCTL(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetCONF0_SYNC_IRDA_WCTL() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetCONF0_SYNC_IRDA_TX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetCONF0_SYNC_IRDA_TX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetCONF0_SYNC_IRDA_RX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetCONF0_SYNC_IRDA_RX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetCONF0_SYNC_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetCONF0_SYNC_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetCONF0_SYNC_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetCONF0_SYNC_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetCONF0_SYNC_IRDA_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetCONF0_SYNC_IRDA_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetCONF0_SYNC_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetCONF0_SYNC_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetCONF0_SYNC_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF0_SYNC_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF0_SYNC_DIS_RX_DAT_OVF(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF0_SYNC_DIS_RX_DAT_OVF() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF0_SYNC_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF0_SYNC_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF0_SYNC_AUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF0_SYNC_AUTOBAUD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF0_SYNC_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF0_SYNC_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF0_SYNC_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF0_SYNC_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetCONF0_SYNC_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCONF0_SYNC_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCONF0_SYNC_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF0_SYNC_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x800000) >> 23 +} + +// UART.CONF1: Configuration register 1 +func (o *UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0xff +} +func (o *UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetCONF1_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF1_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF1_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF1_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF1_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF1_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF1_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF1_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF1_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF1_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} + +// UART.HWFC_CONF_SYNC: Hardware flow-control configuration +func (o *UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_THRHD() uint32 { + return volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0xff +} +func (o *UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0x100) >> 8 +} + +// UART.SLEEP_CONF0: UART sleep configure register 0 +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR1(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR1() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff +} +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR2(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR2() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR3(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR3() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff0000) >> 16 +} +func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR4(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff000000)|value<<24) +} +func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR4() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff000000) >> 24 +} + +// UART.SLEEP_CONF1: UART sleep configure register 1 +func (o *UART_Type) SetSLEEP_CONF1_WK_CHAR0(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF1.Reg, volatile.LoadUint32(&o.SLEEP_CONF1.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSLEEP_CONF1_WK_CHAR0() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF1.Reg) & 0xff +} + +// UART.SLEEP_CONF2: UART sleep configure register 2 +func (o *UART_Type) SetSLEEP_CONF2_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSLEEP_CONF2_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3ff +} +func (o *UART_Type) SetSLEEP_CONF2_RX_WAKE_UP_THRHD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3fc00)|value<<10) +} +func (o *UART_Type) GetSLEEP_CONF2_RX_WAKE_UP_THRHD() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3fc00) >> 10 +} +func (o *UART_Type) SetSLEEP_CONF2_WK_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x1c0000)|value<<18) +} +func (o *UART_Type) GetSLEEP_CONF2_WK_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x1c0000) >> 18 +} +func (o *UART_Type) SetSLEEP_CONF2_WK_CHAR_MASK(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e00000)|value<<21) +} +func (o *UART_Type) GetSLEEP_CONF2_WK_CHAR_MASK() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e00000) >> 21 +} +func (o *UART_Type) SetSLEEP_CONF2_WK_MODE_SEL(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0xc000000)|value<<26) +} +func (o *UART_Type) GetSLEEP_CONF2_WK_MODE_SEL() uint32 { + return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0xc000000) >> 26 +} + +// UART.SWFC_CONF0_SYNC: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF0_SYNC_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSWFC_CONF0_SYNC_XON_CHAR() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff +} +func (o *UART_Type) SetSWFC_CONF0_SYNC_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSWFC_CONF0_SYNC_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff00) >> 8 +} +func (o *UART_Type) SetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetSWFC_CONF0_SYNC_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetSWFC_CONF0_SYNC_SW_FLOW_CON_EN() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetSWFC_CONF0_SYNC_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetSWFC_CONF0_SYNC_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetSWFC_CONF0_SYNC_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetSWFC_CONF0_SYNC_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetSWFC_CONF0_SYNC_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetSWFC_CONF0_SYNC_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetSWFC_CONF0_SYNC_SEND_XON(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetSWFC_CONF0_SYNC_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetSWFC_CONF0_SYNC_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetSWFC_CONF0_SYNC_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x400000) >> 22 +} + +// UART.SWFC_CONF1: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xff +} +func (o *UART_Type) SetSWFC_CONF1_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetSWFC_CONF1_XOFF_THRESHOLD() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xff00) >> 8 +} + +// UART.TXBRK_CONF_SYNC: Tx Break character configuration +func (o *UART_Type) SetTXBRK_CONF_SYNC_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.TXBRK_CONF_SYNC.Reg, volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetTXBRK_CONF_SYNC_TX_BRK_NUM() uint32 { + return volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg) & 0xff +} + +// UART.IDLE_CONF_SYNC: Frame-end idle configuration +func (o *UART_Type) SetIDLE_CONF_SYNC_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetIDLE_CONF_SYNC_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0x3ff +} +func (o *UART_Type) SetIDLE_CONF_SYNC_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0xffc00)|value<<10) +} +func (o *UART_Type) GetIDLE_CONF_SYNC_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0xffc00) >> 10 +} + +// UART.RS485_CONF_SYNC: RS485 mode configuration +func (o *UART_Type) SetRS485_CONF_SYNC_RS485_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetRS485_CONF_SYNC_RS485_EN() uint32 { + return volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x1 +} +func (o *UART_Type) SetRS485_CONF_SYNC_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetRS485_CONF_SYNC_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetRS485_CONF_SYNC_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetRS485_CONF_SYNC_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetRS485_CONF_SYNC_RS485TX_RX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetRS485_CONF_SYNC_RS485TX_RX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetRS485_CONF_SYNC_RS485RXBY_TX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetRS485_CONF_SYNC_RS485RXBY_TX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetRS485_CONF_SYNC_RS485_RX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetRS485_CONF_SYNC_RS485_RX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetRS485_CONF_SYNC_RS485_TX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x3c0)|value<<6) +} +func (o *UART_Type) GetRS485_CONF_SYNC_RS485_TX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x3c0) >> 6 +} + +// UART.AT_CMD_PRECNT_SYNC: Pre-sequence timing configuration +func (o *UART_Type) SetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg) & 0xffff +} + +// UART.AT_CMD_POSTCNT_SYNC: Post-sequence timing configuration +func (o *UART_Type) SetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg) & 0xffff +} + +// UART.AT_CMD_GAPTOUT_SYNC: Timeout configuration +func (o *UART_Type) SetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg) & 0xffff +} + +// UART.AT_CMD_CHAR_SYNC: AT escape sequence detection configuration +func (o *UART_Type) SetAT_CMD_CHAR_SYNC_AT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetAT_CMD_CHAR_SYNC_AT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff +} +func (o *UART_Type) SetAT_CMD_CHAR_SYNC_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAT_CMD_CHAR_SYNC_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff00) >> 8 +} + +// UART.MEM_CONF: UART memory power configuration +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26 +} + +// UART.TOUT_CONF_SYNC: UART threshold and allocation configuration +func (o *UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_EN() uint32 { + return volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x1 +} +func (o *UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0xffc)|value<<2) +} +func (o *UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0xffc) >> 2 +} + +// UART.MEM_TX_STATUS: Tx-SRAM write and read offset address. +func (o *UART_Type) SetMEM_TX_STATUS_TX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_SRAM_WADDR() uint32 { + return volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0xff +} +func (o *UART_Type) SetMEM_TX_STATUS_TX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_SRAM_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1fe00) >> 9 +} + +// UART.MEM_RX_STATUS: Rx-SRAM write and read offset address. +func (o *UART_Type) SetMEM_RX_STATUS_RX_SRAM_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_SRAM_RADDR() uint32 { + return volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xff +} +func (o *UART_Type) SetMEM_RX_STATUS_RX_SRAM_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_SRAM_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1fe00) >> 9 +} + +// UART.FSM_STATUS: UART transmit and receive status. +func (o *UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// UART.POSPULSE: Autobaud high pulse register +func (o *UART_Type) SetPOSPULSE_POSEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.POSPULSE.Reg, volatile.LoadUint32(&o.POSPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetPOSPULSE_POSEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.POSPULSE.Reg) & 0xfff +} + +// UART.NEGPULSE: Autobaud low pulse register +func (o *UART_Type) SetNEGPULSE_NEGEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.NEGPULSE.Reg, volatile.LoadUint32(&o.NEGPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetNEGPULSE_NEGEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.NEGPULSE.Reg) & 0xfff +} + +// UART.LOWPULSE: Autobaud minimum low pulse duration register +func (o *UART_Type) SetLOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.LOWPULSE.Reg, volatile.LoadUint32(&o.LOWPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetLOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.LOWPULSE.Reg) & 0xfff +} + +// UART.HIGHPULSE: Autobaud minimum high pulse duration register +func (o *UART_Type) SetHIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.HIGHPULSE.Reg, volatile.LoadUint32(&o.HIGHPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetHIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.HIGHPULSE.Reg) & 0xfff +} + +// UART.RXD_CNT: Autobaud edge change count register +func (o *UART_Type) SetRXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.RXD_CNT.Reg, volatile.LoadUint32(&o.RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetRXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.RXD_CNT.Reg) & 0x3ff +} + +// UART.CLK_CONF: UART core clock configuration +func (o *UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} + +// UART.DATE: UART Version register +func (o *UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// UART.AFIFO_STATUS: UART AFIFO Status +func (o *UART_Type) SetAFIFO_STATUS_TX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetAFIFO_STATUS_TX_AFIFO_FULL() uint32 { + return volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x1 +} +func (o *UART_Type) SetAFIFO_STATUS_TX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetAFIFO_STATUS_TX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetAFIFO_STATUS_RX_AFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetAFIFO_STATUS_RX_AFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetAFIFO_STATUS_RX_AFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetAFIFO_STATUS_RX_AFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x8) >> 3 +} + +// UART.REG_UPDATE: UART Registers Configuration Update register +func (o *UART_Type) SetREG_UPDATE(value uint32) { + volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetREG_UPDATE() uint32 { + return volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x1 +} + +// UART.ID: UART ID register +func (o *UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, value) +} +func (o *UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) +} + +// Universal Host Controller Interface 0 +type UHCI_Type struct { + CONF0 volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CONF1 volatile.Register32 // 0x14 + STATE0 volatile.Register32 // 0x18 + STATE1 volatile.Register32 // 0x1C + ESCAPE_CONF volatile.Register32 // 0x20 + HUNG_CONF volatile.Register32 // 0x24 + ACK_NUM volatile.Register32 // 0x28 + RX_HEAD volatile.Register32 // 0x2C + QUICK_SENT volatile.Register32 // 0x30 + REG_Q0_WORD0 volatile.Register32 // 0x34 + REG_Q0_WORD1 volatile.Register32 // 0x38 + REG_Q1_WORD0 volatile.Register32 // 0x3C + REG_Q1_WORD1 volatile.Register32 // 0x40 + REG_Q2_WORD0 volatile.Register32 // 0x44 + REG_Q2_WORD1 volatile.Register32 // 0x48 + REG_Q3_WORD0 volatile.Register32 // 0x4C + REG_Q3_WORD1 volatile.Register32 // 0x50 + REG_Q4_WORD0 volatile.Register32 // 0x54 + REG_Q4_WORD1 volatile.Register32 // 0x58 + REG_Q5_WORD0 volatile.Register32 // 0x5C + REG_Q5_WORD1 volatile.Register32 // 0x60 + REG_Q6_WORD0 volatile.Register32 // 0x64 + REG_Q6_WORD1 volatile.Register32 // 0x68 + ESC_CONF0 volatile.Register32 // 0x6C + ESC_CONF1 volatile.Register32 // 0x70 + ESC_CONF2 volatile.Register32 // 0x74 + ESC_CONF3 volatile.Register32 // 0x78 + PKT_THRES volatile.Register32 // 0x7C + DATE volatile.Register32 // 0x80 +} + +// UHCI.CONF0: UHCI Configuration Register0 +func (o *UHCI_Type) SetCONF0_TX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF0_TX_RST() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF0_RX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF0_RX_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF0_UART_SEL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1c)|value<<2) +} +func (o *UHCI_Type) GetCONF0_UART_SEL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1c) >> 2 +} +func (o *UHCI_Type) SetCONF0_SEPER_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF0_SEPER_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF0_HEAD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetCONF0_HEAD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetCONF0_CRC_REC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF0_CRC_REC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF0_UART_IDLE_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF0_UART_IDLE_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetCONF0_LEN_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetCONF0_LEN_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetCONF0_ENCODE_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetCONF0_ENCODE_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetCONF0_UART_RX_BRK_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetCONF0_UART_RX_BRK_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} + +// UHCI.INT_RAW: UHCI Interrupt Raw Register +func (o *UHCI_Type) SetINT_RAW_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_RAW_RX_START_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_RAW_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_RAW_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_RAW_SEND_S_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_RAW_SEND_S_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_RAW_SEND_A_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_RAW_SEND_A_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ST: UHCI Interrupt Status Register +func (o *UHCI_Type) SetINT_ST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ST_RX_START_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ST_SEND_S_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ST_SEND_S_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ST_SEND_A_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ST_SEND_A_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ST_OUTLINK_EOF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ST_OUTLINK_EOF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ENA: UHCI Interrupt Enable Register +func (o *UHCI_Type) SetINT_ENA_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ENA_RX_START_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ENA_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ENA_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ENA_SEND_S_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ENA_SEND_S_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ENA_SEND_A_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ENA_SEND_A_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ENA_OUTLINK_EOF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ENA_OUTLINK_EOF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// UHCI.INT_CLR: UHCI Interrupt Clear Register +func (o *UHCI_Type) SetINT_CLR_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_CLR_RX_START_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_CLR_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_CLR_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_CLR_SEND_S_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_CLR_SEND_S_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_CLR_SEND_A_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_CLR_SEND_A_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_CLR_OUTLINK_EOF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_CLR_OUTLINK_EOF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// UHCI.CONF1: UHCI Configuration Register1 +func (o *UHCI_Type) SetCONF1_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF1_CHECK_SUM_EN() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF1_CHECK_SEQ_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF1_CHECK_SEQ_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF1_CRC_DISABLE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF1_CRC_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF1_SAVE_HEAD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF1_SAVE_HEAD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF1_TX_CHECK_SUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF1_TX_CHECK_SUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF1_TX_ACK_NUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF1_TX_ACK_NUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF1_WAIT_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF1_WAIT_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF1_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF1_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8 +} + +// UHCI.STATE0: UHCI Receive Status Register +func (o *UHCI_Type) SetSTATE0_RX_ERR_CAUSE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE0_RX_ERR_CAUSE() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x7 +} +func (o *UHCI_Type) SetSTATE0_DECODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x38)|value<<3) +} +func (o *UHCI_Type) GetSTATE0_DECODE_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x38) >> 3 +} + +// UHCI.STATE1: UHCI Transmit Status Register +func (o *UHCI_Type) SetSTATE1_ENCODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE1_ENCODE_STATE() uint32 { + return volatile.LoadUint32(&o.STATE1.Reg) & 0x7 +} + +// UHCI.ESCAPE_CONF: UHCI Escapes Configuration Register0 +func (o *UHCI_Type) SetESCAPE_CONF_TX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_C0_ESC_EN() uint32 { + return volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_C0_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x80) >> 7 +} + +// UHCI.HUNG_CONF: UHCI Hung Configuration Register0 +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff000) >> 12 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700000) >> 20 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800000) >> 23 +} + +// UHCI.ACK_NUM: UHCI Ack Value Configuration Register0 +func (o *UHCI_Type) SetACK_NUM(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetACK_NUM() uint32 { + return volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x7 +} +func (o *UHCI_Type) SetACK_NUM_LOAD(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetACK_NUM_LOAD() uint32 { + return (volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x8) >> 3 +} + +// UHCI.RX_HEAD: UHCI Head Register +func (o *UHCI_Type) SetRX_HEAD(value uint32) { + volatile.StoreUint32(&o.RX_HEAD.Reg, value) +} +func (o *UHCI_Type) GetRX_HEAD() uint32 { + return volatile.LoadUint32(&o.RX_HEAD.Reg) +} + +// UHCI.QUICK_SENT: UCHI Quick send Register +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_NUM() uint32 { + return volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x7 +} +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x70)|value<<4) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_NUM() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x70) >> 4 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x80) >> 7 +} + +// UHCI.REG_Q0_WORD0: UHCI Q0_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q0_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD0.Reg) +} + +// UHCI.REG_Q0_WORD1: UHCI Q0_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q0_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD1.Reg) +} + +// UHCI.REG_Q1_WORD0: UHCI Q1_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q1_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD0.Reg) +} + +// UHCI.REG_Q1_WORD1: UHCI Q1_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q1_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD1.Reg) +} + +// UHCI.REG_Q2_WORD0: UHCI Q2_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q2_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD0.Reg) +} + +// UHCI.REG_Q2_WORD1: UHCI Q2_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q2_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD1.Reg) +} + +// UHCI.REG_Q3_WORD0: UHCI Q3_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q3_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD0.Reg) +} + +// UHCI.REG_Q3_WORD1: UHCI Q3_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q3_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD1.Reg) +} + +// UHCI.REG_Q4_WORD0: UHCI Q4_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q4_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD0.Reg) +} + +// UHCI.REG_Q4_WORD1: UHCI Q4_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q4_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD1.Reg) +} + +// UHCI.REG_Q5_WORD0: UHCI Q5_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q5_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD0.Reg) +} + +// UHCI.REG_Q5_WORD1: UHCI Q5_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q5_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD1.Reg) +} + +// UHCI.REG_Q6_WORD0: UHCI Q6_WORD0 Quick Send Register +func (o *UHCI_Type) SetREG_Q6_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD0.Reg) +} + +// UHCI.REG_Q6_WORD1: UHCI Q6_WORD1 Quick Send Register +func (o *UHCI_Type) SetREG_Q6_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD1.Reg) +} + +// UHCI.ESC_CONF0: UHCI Escapes Sequence Configuration Register0 +func (o *UHCI_Type) SetESC_CONF0_SEPER_CHAR(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_CHAR() uint32 { + return volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF1: UHCI Escapes Sequence Configuration Register1 +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0() uint32 { + return volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF2: UHCI Escapes Sequence Configuration Register2 +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1() uint32 { + return volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF3: UHCI Escapes Sequence Configuration Register3 +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2() uint32 { + return volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff0000) >> 16 +} + +// UHCI.PKT_THRES: UCHI Packet Length Configuration Register +func (o *UHCI_Type) SetPKT_THRES_PKT_THRS(value uint32) { + volatile.StoreUint32(&o.PKT_THRES.Reg, volatile.LoadUint32(&o.PKT_THRES.Reg)&^(0x1fff)|value) +} +func (o *UHCI_Type) GetPKT_THRES_PKT_THRS() uint32 { + return volatile.LoadUint32(&o.PKT_THRES.Reg) & 0x1fff +} + +// UHCI.DATE: UHCI Version Register +func (o *UHCI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UHCI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Full-speed USB Serial/JTAG Controller +type USB_DEVICE_Type struct { + EP1 volatile.Register32 // 0x0 + EP1_CONF volatile.Register32 // 0x4 + INT_RAW volatile.Register32 // 0x8 + INT_ST volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + INT_CLR volatile.Register32 // 0x14 + CONF0 volatile.Register32 // 0x18 + TEST volatile.Register32 // 0x1C + JFIFO_ST volatile.Register32 // 0x20 + FRAM_NUM volatile.Register32 // 0x24 + IN_EP0_ST volatile.Register32 // 0x28 + IN_EP1_ST volatile.Register32 // 0x2C + IN_EP2_ST volatile.Register32 // 0x30 + IN_EP3_ST volatile.Register32 // 0x34 + OUT_EP0_ST volatile.Register32 // 0x38 + OUT_EP1_ST volatile.Register32 // 0x3C + OUT_EP2_ST volatile.Register32 // 0x40 + MISC_CONF volatile.Register32 // 0x44 + MEM_CONF volatile.Register32 // 0x48 + CHIP_RST volatile.Register32 // 0x4C + SET_LINE_CODE_W0 volatile.Register32 // 0x50 + SET_LINE_CODE_W1 volatile.Register32 // 0x54 + GET_LINE_CODE_W0 volatile.Register32 // 0x58 + GET_LINE_CODE_W1 volatile.Register32 // 0x5C + CONFIG_UPDATE volatile.Register32 // 0x60 + SER_AFIFO_CONFIG volatile.Register32 // 0x64 + BUS_RESET_ST volatile.Register32 // 0x68 + ECO_LOW_48 volatile.Register32 // 0x6C + ECO_HIGH_48 volatile.Register32 // 0x70 + ECO_CELL_CTRL_48 volatile.Register32 // 0x74 + ECO_LOW_APB volatile.Register32 // 0x78 + ECO_HIGH_APB volatile.Register32 // 0x7C + ECO_CELL_CTRL_APB volatile.Register32 // 0x80 + SRAM_CTRL volatile.Register32 // 0x84 + DATE volatile.Register32 // 0x88 +} + +// USB_DEVICE.EP1: FIFO access for the CDC-ACM data IN and OUT endpoints. +func (o *USB_DEVICE_Type) SetEP1_USB_SERIAL_JTAG_RDWR_BYTE(value uint32) { + volatile.StoreUint32(&o.EP1.Reg, volatile.LoadUint32(&o.EP1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetEP1_USB_SERIAL_JTAG_RDWR_BYTE() uint32 { + return volatile.LoadUint32(&o.EP1.Reg) & 0xff +} + +// USB_DEVICE.EP1_CONF: Configuration and control registers for the CDC-ACM FIFOs. +func (o *USB_DEVICE_Type) SetEP1_CONF_USB_SERIAL_JTAG_WR_DONE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_USB_SERIAL_JTAG_WR_DONE() uint32 { + return volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x4) >> 2 +} + +// USB_DEVICE.INT_RAW: Interrupt raw status register. +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_SOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_SOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_PID_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_PID_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_CRC5_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_CRC5_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_CRC16_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_CRC16_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_STUFF_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_STUFF_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_RTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_RTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_DTR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_DTR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.INT_ST: Interrupt status register. +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_SOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_SOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_PID_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_PID_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_CRC5_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_CRC5_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_CRC16_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_CRC16_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_STUFF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_STUFF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_RTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_RTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_DTR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_DTR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.INT_ENA: Interrupt enable status register. +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_PID_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_PID_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_CRC5_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_CRC5_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_CRC16_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_CRC16_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_STUFF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_STUFF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_RTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_RTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_DTR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_DTR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.INT_CLR: Interrupt clear status register. +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_SOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_SOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_PID_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_PID_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_CRC5_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_CRC5_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_CRC16_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_CRC16_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_STUFF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_STUFF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_RTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_RTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_DTR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_DTR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.CONF0: PHY hardware configuration. +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_PHY_SEL() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_VREFH(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x18)|value<<3) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_VREFH() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x18) >> 3 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_VREFL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x60)|value<<5) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_VREFL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x60) >> 5 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} + +// USB_DEVICE.TEST: Registers used for debugging the PHY. +func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_ENABLE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_ENABLE() uint32 { + return volatile.LoadUint32(&o.TEST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_USB_OE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_USB_OE() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_TX_DP(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_TX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_TX_DM(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_TX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_RX_RCV(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_RX_RCV() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_RX_DP(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_RX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_RX_DM(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_RX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x40) >> 6 +} + +// USB_DEVICE.JFIFO_ST: JTAG FIFO status and control registers. +func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_CNT() uint32 { + return volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x30)|value<<4) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x30) >> 4 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x200) >> 9 +} + +// USB_DEVICE.FRAM_NUM: Last received SOF frame index register. +func (o *USB_DEVICE_Type) SetFRAM_NUM_USB_SERIAL_JTAG_SOF_FRAME_INDEX(value uint32) { + volatile.StoreUint32(&o.FRAM_NUM.Reg, volatile.LoadUint32(&o.FRAM_NUM.Reg)&^(0x7ff)|value) +} +func (o *USB_DEVICE_Type) GetFRAM_NUM_USB_SERIAL_JTAG_SOF_FRAME_INDEX() uint32 { + return volatile.LoadUint32(&o.FRAM_NUM.Reg) & 0x7ff +} + +// USB_DEVICE.IN_EP0_ST: Control IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP1_ST: CDC-ACM IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP2_ST: CDC-ACM interrupt IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP3_ST: JTAG IN endpoint status information. +func (o *USB_DEVICE_Type) SetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP0_ST: Control OUT endpoint status information. +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP1_ST: CDC-ACM OUT endpoint status information. +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0xfe00) >> 9 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x7f0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x7f0000) >> 16 +} + +// USB_DEVICE.OUT_EP2_ST: JTAG OUT endpoint status information. +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.MISC_CONF: Clock enable control +func (o *USB_DEVICE_Type) SetMISC_CONF_USB_SERIAL_JTAG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMISC_CONF_USB_SERIAL_JTAG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} + +// USB_DEVICE.MEM_CONF: Memory power control +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_SERIAL_JTAG_USB_MEM_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_SERIAL_JTAG_USB_MEM_PD() uint32 { + return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_SERIAL_JTAG_USB_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_SERIAL_JTAG_USB_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2) >> 1 +} + +// USB_DEVICE.CHIP_RST: CDC-ACM chip reset control. +func (o *USB_DEVICE_Type) SetCHIP_RST_USB_SERIAL_JTAG_RTS(value uint32) { + volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCHIP_RST_USB_SERIAL_JTAG_RTS() uint32 { + return volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetCHIP_RST_USB_SERIAL_JTAG_DTR(value uint32) { + volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetCHIP_RST_USB_SERIAL_JTAG_DTR() uint32 { + return (volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetCHIP_RST_USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS(value uint32) { + volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetCHIP_RST_USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS() uint32 { + return (volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x4) >> 2 +} + +// USB_DEVICE.SET_LINE_CODE_W0: W0 of SET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W0(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W0.Reg, value) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W0() uint32 { + return volatile.LoadUint32(&o.SET_LINE_CODE_W0.Reg) +} + +// USB_DEVICE.SET_LINE_CODE_W1: W1 of SET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BCHAR_FORMAT(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BCHAR_FORMAT() uint32 { + return volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff +} +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BPARITY_TYPE(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff00)|value<<8) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BPARITY_TYPE() uint32 { + return (volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff00) >> 8 +} +func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BDATA_BITS(value uint32) { + volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BDATA_BITS() uint32 { + return (volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff0000) >> 16 +} + +// USB_DEVICE.GET_LINE_CODE_W0: W0 of GET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W0(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W0.Reg, value) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W0() uint32 { + return volatile.LoadUint32(&o.GET_LINE_CODE_W0.Reg) +} + +// USB_DEVICE.GET_LINE_CODE_W1: W1 of GET_LINE_CODING command. +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BDATA_BITS(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BDATA_BITS() uint32 { + return volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff +} +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BPARITY_TYPE(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff00)|value<<8) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BPARITY_TYPE() uint32 { + return (volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff00) >> 8 +} +func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BCHAR_FORMAT(value uint32) { + volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BCHAR_FORMAT() uint32 { + return (volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff0000) >> 16 +} + +// USB_DEVICE.CONFIG_UPDATE: Configuration registers' value update +func (o *USB_DEVICE_Type) SetCONFIG_UPDATE_USB_SERIAL_JTAG_CONFIG_UPDATE(value uint32) { + volatile.StoreUint32(&o.CONFIG_UPDATE.Reg, volatile.LoadUint32(&o.CONFIG_UPDATE.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCONFIG_UPDATE_USB_SERIAL_JTAG_CONFIG_UPDATE() uint32 { + return volatile.LoadUint32(&o.CONFIG_UPDATE.Reg) & 0x1 +} + +// USB_DEVICE.SER_AFIFO_CONFIG: Serial AFIFO configure register +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR() uint32 { + return volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL(value uint32) { + volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL() uint32 { + return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x20) >> 5 +} + +// USB_DEVICE.BUS_RESET_ST: USB Bus reset status register +func (o *USB_DEVICE_Type) SetBUS_RESET_ST_USB_SERIAL_JTAG_USB_BUS_RESET_ST(value uint32) { + volatile.StoreUint32(&o.BUS_RESET_ST.Reg, volatile.LoadUint32(&o.BUS_RESET_ST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetBUS_RESET_ST_USB_SERIAL_JTAG_USB_BUS_RESET_ST() uint32 { + return volatile.LoadUint32(&o.BUS_RESET_ST.Reg) & 0x1 +} + +// USB_DEVICE.ECO_LOW_48: Reserved. +func (o *USB_DEVICE_Type) SetECO_LOW_48(value uint32) { + volatile.StoreUint32(&o.ECO_LOW_48.Reg, value) +} +func (o *USB_DEVICE_Type) GetECO_LOW_48() uint32 { + return volatile.LoadUint32(&o.ECO_LOW_48.Reg) +} + +// USB_DEVICE.ECO_HIGH_48: Reserved. +func (o *USB_DEVICE_Type) SetECO_HIGH_48(value uint32) { + volatile.StoreUint32(&o.ECO_HIGH_48.Reg, value) +} +func (o *USB_DEVICE_Type) GetECO_HIGH_48() uint32 { + return volatile.LoadUint32(&o.ECO_HIGH_48.Reg) +} + +// USB_DEVICE.ECO_CELL_CTRL_48: Reserved. +func (o *USB_DEVICE_Type) SetECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_RESULT_48(value uint32) { + volatile.StoreUint32(&o.ECO_CELL_CTRL_48.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL_48.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_RESULT_48() uint32 { + return volatile.LoadUint32(&o.ECO_CELL_CTRL_48.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_ENA_48(value uint32) { + volatile.StoreUint32(&o.ECO_CELL_CTRL_48.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL_48.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_ENA_48() uint32 { + return (volatile.LoadUint32(&o.ECO_CELL_CTRL_48.Reg) & 0x2) >> 1 +} + +// USB_DEVICE.ECO_LOW_APB: Reserved. +func (o *USB_DEVICE_Type) SetECO_LOW_APB(value uint32) { + volatile.StoreUint32(&o.ECO_LOW_APB.Reg, value) +} +func (o *USB_DEVICE_Type) GetECO_LOW_APB() uint32 { + return volatile.LoadUint32(&o.ECO_LOW_APB.Reg) +} + +// USB_DEVICE.ECO_HIGH_APB: Reserved. +func (o *USB_DEVICE_Type) SetECO_HIGH_APB(value uint32) { + volatile.StoreUint32(&o.ECO_HIGH_APB.Reg, value) +} +func (o *USB_DEVICE_Type) GetECO_HIGH_APB() uint32 { + return volatile.LoadUint32(&o.ECO_HIGH_APB.Reg) +} + +// USB_DEVICE.ECO_CELL_CTRL_APB: Reserved. +func (o *USB_DEVICE_Type) SetECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_RESULT_APB(value uint32) { + volatile.StoreUint32(&o.ECO_CELL_CTRL_APB.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL_APB.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_RESULT_APB() uint32 { + return volatile.LoadUint32(&o.ECO_CELL_CTRL_APB.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_ENA_APB(value uint32) { + volatile.StoreUint32(&o.ECO_CELL_CTRL_APB.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL_APB.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_ENA_APB() uint32 { + return (volatile.LoadUint32(&o.ECO_CELL_CTRL_APB.Reg) & 0x2) >> 1 +} + +// USB_DEVICE.SRAM_CTRL: PPA SRAM Control Register +func (o *USB_DEVICE_Type) SetSRAM_CTRL_USB_SERIAL_JTAG_MEM_AUX_CTRL(value uint32) { + volatile.StoreUint32(&o.SRAM_CTRL.Reg, volatile.LoadUint32(&o.SRAM_CTRL.Reg)&^(0x3fff)|value) +} +func (o *USB_DEVICE_Type) GetSRAM_CTRL_USB_SERIAL_JTAG_MEM_AUX_CTRL() uint32 { + return volatile.LoadUint32(&o.SRAM_CTRL.Reg) & 0x3fff +} + +// USB_DEVICE.DATE: Date register +func (o *USB_DEVICE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *USB_DEVICE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// USB_WRAP Peripheral +type USB_WRAP_Type struct { + OTG_CONF volatile.Register32 // 0x0 + TEST_CONF volatile.Register32 // 0x4 + _ [1012]byte + DATE volatile.Register32 // 0x3FC +} + +// USB_WRAP.OTG_CONF: USB wrapper configuration registers. +func (o *USB_WRAP_Type) SetOTG_CONF_SRP_SESSEND_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x1)|value) +} +func (o *USB_WRAP_Type) GetOTG_CONF_SRP_SESSEND_OVERRIDE() uint32 { + return volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x1 +} +func (o *USB_WRAP_Type) SetOTG_CONF_SRP_SESSEND_VALUE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_WRAP_Type) GetOTG_CONF_SRP_SESSEND_VALUE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PHY_SEL() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x4) >> 2 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DFIFO_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x8)|value<<3) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DFIFO_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x8) >> 3 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DBNCE_FLTR_BYPASS(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x10)|value<<4) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DBNCE_FLTR_BYPASS() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x10) >> 4 +} +func (o *USB_WRAP_Type) SetOTG_CONF_EXCHG_PINS_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x20)|value<<5) +} +func (o *USB_WRAP_Type) GetOTG_CONF_EXCHG_PINS_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x20) >> 5 +} +func (o *USB_WRAP_Type) SetOTG_CONF_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x40)|value<<6) +} +func (o *USB_WRAP_Type) GetOTG_CONF_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x40) >> 6 +} +func (o *USB_WRAP_Type) SetOTG_CONF_VREFH(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x180)|value<<7) +} +func (o *USB_WRAP_Type) GetOTG_CONF_VREFH() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x180) >> 7 +} +func (o *USB_WRAP_Type) SetOTG_CONF_VREFL(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x600)|value<<9) +} +func (o *USB_WRAP_Type) GetOTG_CONF_VREFL() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x600) >> 9 +} +func (o *USB_WRAP_Type) SetOTG_CONF_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *USB_WRAP_Type) GetOTG_CONF_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x800) >> 11 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x1000) >> 12 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x2000) >> 13 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x4000) >> 14 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x8000) >> 15 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x10000) >> 16 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x20000) >> 17 +} +func (o *USB_WRAP_Type) SetOTG_CONF_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *USB_WRAP_Type) GetOTG_CONF_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x40000) >> 18 +} +func (o *USB_WRAP_Type) SetOTG_CONF_AHB_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *USB_WRAP_Type) GetOTG_CONF_AHB_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x80000) >> 19 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PHY_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PHY_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x100000) >> 20 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PHY_TX_EDGE_SEL(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PHY_TX_EDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x200000) >> 21 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DFIFO_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DFIFO_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x400000) >> 22 +} +func (o *USB_WRAP_Type) SetOTG_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_WRAP_Type) GetOTG_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x80000000) >> 31 +} + +// USB_WRAP.TEST_CONF: USB wrapper test configuration registers. +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_ENABLE(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x1)|value) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_ENABLE() uint32 { + return volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x1 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_USB_OE(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_USB_OE() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_TX_DP(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_TX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x4) >> 2 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_TX_DM(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x8)|value<<3) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_TX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x8) >> 3 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_RCV(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x10)|value<<4) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_RCV() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x10) >> 4 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_DP(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x20)|value<<5) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x20) >> 5 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_DM(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x40)|value<<6) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x40) >> 6 +} + +// USB_WRAP.DATE: Date register. +func (o *USB_WRAP_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *USB_WRAP_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Constants for ADC: ADC (Analog to Digital Converter) +const ( + // CTRL: Register + // Position of START_FORCE field. + ADC_CTRL_START_FORCE_Pos = 0x0 + // Bit mask of START_FORCE field. + ADC_CTRL_START_FORCE_Msk = 0x1 + // Bit START_FORCE. + ADC_CTRL_START_FORCE = 0x1 + // Position of START field. + ADC_CTRL_START_Pos = 0x1 + // Bit mask of START field. + ADC_CTRL_START_Msk = 0x2 + // Bit START. + ADC_CTRL_START = 0x2 + // Position of WORK_MODE field. + ADC_CTRL_WORK_MODE_Pos = 0x2 + // Bit mask of WORK_MODE field. + ADC_CTRL_WORK_MODE_Msk = 0xc + // Position of SAR_SEL field. + ADC_CTRL_SAR_SEL_Pos = 0x4 + // Bit mask of SAR_SEL field. + ADC_CTRL_SAR_SEL_Msk = 0x10 + // Bit SAR_SEL. + ADC_CTRL_SAR_SEL = 0x10 + // Position of SAR_CLK_GATED field. + ADC_CTRL_SAR_CLK_GATED_Pos = 0x5 + // Bit mask of SAR_CLK_GATED field. + ADC_CTRL_SAR_CLK_GATED_Msk = 0x20 + // Bit SAR_CLK_GATED. + ADC_CTRL_SAR_CLK_GATED = 0x20 + // Position of SAR_CLK_DIV field. + ADC_CTRL_SAR_CLK_DIV_Pos = 0x6 + // Bit mask of SAR_CLK_DIV field. + ADC_CTRL_SAR_CLK_DIV_Msk = 0x3fc0 + // Position of SAR1_PATT_LEN field. + ADC_CTRL_SAR1_PATT_LEN_Pos = 0xe + // Bit mask of SAR1_PATT_LEN field. + ADC_CTRL_SAR1_PATT_LEN_Msk = 0x3c000 + // Position of SAR2_PATT_LEN field. + ADC_CTRL_SAR2_PATT_LEN_Pos = 0x12 + // Bit mask of SAR2_PATT_LEN field. + ADC_CTRL_SAR2_PATT_LEN_Msk = 0x3c0000 + // Position of SAR1_PATT_P_CLEAR field. + ADC_CTRL_SAR1_PATT_P_CLEAR_Pos = 0x16 + // Bit mask of SAR1_PATT_P_CLEAR field. + ADC_CTRL_SAR1_PATT_P_CLEAR_Msk = 0x400000 + // Bit SAR1_PATT_P_CLEAR. + ADC_CTRL_SAR1_PATT_P_CLEAR = 0x400000 + // Position of SAR2_PATT_P_CLEAR field. + ADC_CTRL_SAR2_PATT_P_CLEAR_Pos = 0x17 + // Bit mask of SAR2_PATT_P_CLEAR field. + ADC_CTRL_SAR2_PATT_P_CLEAR_Msk = 0x800000 + // Bit SAR2_PATT_P_CLEAR. + ADC_CTRL_SAR2_PATT_P_CLEAR = 0x800000 + // Position of DATA_SAR_SEL field. + ADC_CTRL_DATA_SAR_SEL_Pos = 0x18 + // Bit mask of DATA_SAR_SEL field. + ADC_CTRL_DATA_SAR_SEL_Msk = 0x1000000 + // Bit DATA_SAR_SEL. + ADC_CTRL_DATA_SAR_SEL = 0x1000000 + // Position of DATA_TO_I2S field. + ADC_CTRL_DATA_TO_I2S_Pos = 0x19 + // Bit mask of DATA_TO_I2S field. + ADC_CTRL_DATA_TO_I2S_Msk = 0x2000000 + // Bit DATA_TO_I2S. + ADC_CTRL_DATA_TO_I2S = 0x2000000 + // Position of XPD_SAR1_FORCE field. + ADC_CTRL_XPD_SAR1_FORCE_Pos = 0x1a + // Bit mask of XPD_SAR1_FORCE field. + ADC_CTRL_XPD_SAR1_FORCE_Msk = 0xc000000 + // Position of XPD_SAR2_FORCE field. + ADC_CTRL_XPD_SAR2_FORCE_Pos = 0x1c + // Bit mask of XPD_SAR2_FORCE field. + ADC_CTRL_XPD_SAR2_FORCE_Msk = 0x30000000 + // Position of WAIT_ARB_CYCLE field. + ADC_CTRL_WAIT_ARB_CYCLE_Pos = 0x1e + // Bit mask of WAIT_ARB_CYCLE field. + ADC_CTRL_WAIT_ARB_CYCLE_Msk = 0xc0000000 + + // CTRL2: Register + // Position of MEAS_NUM_LIMIT field. + ADC_CTRL2_MEAS_NUM_LIMIT_Pos = 0x0 + // Bit mask of MEAS_NUM_LIMIT field. + ADC_CTRL2_MEAS_NUM_LIMIT_Msk = 0x1 + // Bit MEAS_NUM_LIMIT. + ADC_CTRL2_MEAS_NUM_LIMIT = 0x1 + // Position of MAX_MEAS_NUM field. + ADC_CTRL2_MAX_MEAS_NUM_Pos = 0x1 + // Bit mask of MAX_MEAS_NUM field. + ADC_CTRL2_MAX_MEAS_NUM_Msk = 0x1fe + // Position of SAR1_INV field. + ADC_CTRL2_SAR1_INV_Pos = 0x9 + // Bit mask of SAR1_INV field. + ADC_CTRL2_SAR1_INV_Msk = 0x200 + // Bit SAR1_INV. + ADC_CTRL2_SAR1_INV = 0x200 + // Position of SAR2_INV field. + ADC_CTRL2_SAR2_INV_Pos = 0xa + // Bit mask of SAR2_INV field. + ADC_CTRL2_SAR2_INV_Msk = 0x400 + // Bit SAR2_INV. + ADC_CTRL2_SAR2_INV = 0x400 + // Position of TIMER_SEL field. + ADC_CTRL2_TIMER_SEL_Pos = 0xb + // Bit mask of TIMER_SEL field. + ADC_CTRL2_TIMER_SEL_Msk = 0x800 + // Bit TIMER_SEL. + ADC_CTRL2_TIMER_SEL = 0x800 + // Position of TIMER_TARGET field. + ADC_CTRL2_TIMER_TARGET_Pos = 0xc + // Bit mask of TIMER_TARGET field. + ADC_CTRL2_TIMER_TARGET_Msk = 0xfff000 + // Position of TIMER_EN field. + ADC_CTRL2_TIMER_EN_Pos = 0x18 + // Bit mask of TIMER_EN field. + ADC_CTRL2_TIMER_EN_Msk = 0x1000000 + // Bit TIMER_EN. + ADC_CTRL2_TIMER_EN = 0x1000000 + + // FILTER_CTRL1: Register + // Position of FILTER_FACTOR1 field. + ADC_FILTER_CTRL1_FILTER_FACTOR1_Pos = 0x1a + // Bit mask of FILTER_FACTOR1 field. + ADC_FILTER_CTRL1_FILTER_FACTOR1_Msk = 0x1c000000 + // Position of FILTER_FACTOR0 field. + ADC_FILTER_CTRL1_FILTER_FACTOR0_Pos = 0x1d + // Bit mask of FILTER_FACTOR0 field. + ADC_FILTER_CTRL1_FILTER_FACTOR0_Msk = 0xe0000000 + + // FSM_WAIT: Register + // Position of XPD_WAIT field. + ADC_FSM_WAIT_XPD_WAIT_Pos = 0x0 + // Bit mask of XPD_WAIT field. + ADC_FSM_WAIT_XPD_WAIT_Msk = 0xff + // Position of RSTB_WAIT field. + ADC_FSM_WAIT_RSTB_WAIT_Pos = 0x8 + // Bit mask of RSTB_WAIT field. + ADC_FSM_WAIT_RSTB_WAIT_Msk = 0xff00 + // Position of STANDBY_WAIT field. + ADC_FSM_WAIT_STANDBY_WAIT_Pos = 0x10 + // Bit mask of STANDBY_WAIT field. + ADC_FSM_WAIT_STANDBY_WAIT_Msk = 0xff0000 + + // SAR1_STATUS: Register + // Position of SAR1_STATUS field. + ADC_SAR1_STATUS_SAR1_STATUS_Pos = 0x0 + // Bit mask of SAR1_STATUS field. + ADC_SAR1_STATUS_SAR1_STATUS_Msk = 0xffffffff + + // SAR2_STATUS: Register + // Position of SAR2_STATUS field. + ADC_SAR2_STATUS_SAR2_STATUS_Pos = 0x0 + // Bit mask of SAR2_STATUS field. + ADC_SAR2_STATUS_SAR2_STATUS_Msk = 0xffffffff + + // SAR1_PATT_TAB1: Register + // Position of SAR1_PATT_TAB1 field. + ADC_SAR1_PATT_TAB1_SAR1_PATT_TAB1_Pos = 0x0 + // Bit mask of SAR1_PATT_TAB1 field. + ADC_SAR1_PATT_TAB1_SAR1_PATT_TAB1_Msk = 0xffffff + + // SAR1_PATT_TAB2: Register + // Position of SAR1_PATT_TAB2 field. + ADC_SAR1_PATT_TAB2_SAR1_PATT_TAB2_Pos = 0x0 + // Bit mask of SAR1_PATT_TAB2 field. + ADC_SAR1_PATT_TAB2_SAR1_PATT_TAB2_Msk = 0xffffff + + // SAR1_PATT_TAB3: Register + // Position of SAR1_PATT_TAB3 field. + ADC_SAR1_PATT_TAB3_SAR1_PATT_TAB3_Pos = 0x0 + // Bit mask of SAR1_PATT_TAB3 field. + ADC_SAR1_PATT_TAB3_SAR1_PATT_TAB3_Msk = 0xffffff + + // SAR1_PATT_TAB4: Register + // Position of SAR1_PATT_TAB4 field. + ADC_SAR1_PATT_TAB4_SAR1_PATT_TAB4_Pos = 0x0 + // Bit mask of SAR1_PATT_TAB4 field. + ADC_SAR1_PATT_TAB4_SAR1_PATT_TAB4_Msk = 0xffffff + + // SAR2_PATT_TAB1: Register + // Position of SAR2_PATT_TAB1 field. + ADC_SAR2_PATT_TAB1_SAR2_PATT_TAB1_Pos = 0x0 + // Bit mask of SAR2_PATT_TAB1 field. + ADC_SAR2_PATT_TAB1_SAR2_PATT_TAB1_Msk = 0xffffff + + // SAR2_PATT_TAB2: Register + // Position of SAR2_PATT_TAB2 field. + ADC_SAR2_PATT_TAB2_SAR2_PATT_TAB2_Pos = 0x0 + // Bit mask of SAR2_PATT_TAB2 field. + ADC_SAR2_PATT_TAB2_SAR2_PATT_TAB2_Msk = 0xffffff + + // SAR2_PATT_TAB3: Register + // Position of SAR2_PATT_TAB3 field. + ADC_SAR2_PATT_TAB3_SAR2_PATT_TAB3_Pos = 0x0 + // Bit mask of SAR2_PATT_TAB3 field. + ADC_SAR2_PATT_TAB3_SAR2_PATT_TAB3_Msk = 0xffffff + + // SAR2_PATT_TAB4: Register + // Position of SAR2_PATT_TAB4 field. + ADC_SAR2_PATT_TAB4_SAR2_PATT_TAB4_Pos = 0x0 + // Bit mask of SAR2_PATT_TAB4 field. + ADC_SAR2_PATT_TAB4_SAR2_PATT_TAB4_Msk = 0xffffff + + // ARB_CTRL: Register + // Position of ARB_APB_FORCE field. + ADC_ARB_CTRL_ARB_APB_FORCE_Pos = 0x2 + // Bit mask of ARB_APB_FORCE field. + ADC_ARB_CTRL_ARB_APB_FORCE_Msk = 0x4 + // Bit ARB_APB_FORCE. + ADC_ARB_CTRL_ARB_APB_FORCE = 0x4 + // Position of ARB_RTC_FORCE field. + ADC_ARB_CTRL_ARB_RTC_FORCE_Pos = 0x3 + // Bit mask of ARB_RTC_FORCE field. + ADC_ARB_CTRL_ARB_RTC_FORCE_Msk = 0x8 + // Bit ARB_RTC_FORCE. + ADC_ARB_CTRL_ARB_RTC_FORCE = 0x8 + // Position of ARB_WIFI_FORCE field. + ADC_ARB_CTRL_ARB_WIFI_FORCE_Pos = 0x4 + // Bit mask of ARB_WIFI_FORCE field. + ADC_ARB_CTRL_ARB_WIFI_FORCE_Msk = 0x10 + // Bit ARB_WIFI_FORCE. + ADC_ARB_CTRL_ARB_WIFI_FORCE = 0x10 + // Position of ARB_GRANT_FORCE field. + ADC_ARB_CTRL_ARB_GRANT_FORCE_Pos = 0x5 + // Bit mask of ARB_GRANT_FORCE field. + ADC_ARB_CTRL_ARB_GRANT_FORCE_Msk = 0x20 + // Bit ARB_GRANT_FORCE. + ADC_ARB_CTRL_ARB_GRANT_FORCE = 0x20 + // Position of ARB_APB_PRIORITY field. + ADC_ARB_CTRL_ARB_APB_PRIORITY_Pos = 0x6 + // Bit mask of ARB_APB_PRIORITY field. + ADC_ARB_CTRL_ARB_APB_PRIORITY_Msk = 0xc0 + // Position of ARB_RTC_PRIORITY field. + ADC_ARB_CTRL_ARB_RTC_PRIORITY_Pos = 0x8 + // Bit mask of ARB_RTC_PRIORITY field. + ADC_ARB_CTRL_ARB_RTC_PRIORITY_Msk = 0x300 + // Position of ARB_WIFI_PRIORITY field. + ADC_ARB_CTRL_ARB_WIFI_PRIORITY_Pos = 0xa + // Bit mask of ARB_WIFI_PRIORITY field. + ADC_ARB_CTRL_ARB_WIFI_PRIORITY_Msk = 0xc00 + // Position of ARB_FIX_PRIORITY field. + ADC_ARB_CTRL_ARB_FIX_PRIORITY_Pos = 0xc + // Bit mask of ARB_FIX_PRIORITY field. + ADC_ARB_CTRL_ARB_FIX_PRIORITY_Msk = 0x1000 + // Bit ARB_FIX_PRIORITY. + ADC_ARB_CTRL_ARB_FIX_PRIORITY = 0x1000 + + // FILTER_CTRL0: Register + // Position of FILTER_CHANNEL1 field. + ADC_FILTER_CTRL0_FILTER_CHANNEL1_Pos = 0xe + // Bit mask of FILTER_CHANNEL1 field. + ADC_FILTER_CTRL0_FILTER_CHANNEL1_Msk = 0x7c000 + // Position of FILTER_CHANNEL0 field. + ADC_FILTER_CTRL0_FILTER_CHANNEL0_Pos = 0x13 + // Bit mask of FILTER_CHANNEL0 field. + ADC_FILTER_CTRL0_FILTER_CHANNEL0_Msk = 0xf80000 + // Position of FILTER_RESET field. + ADC_FILTER_CTRL0_FILTER_RESET_Pos = 0x1f + // Bit mask of FILTER_RESET field. + ADC_FILTER_CTRL0_FILTER_RESET_Msk = 0x80000000 + // Bit FILTER_RESET. + ADC_FILTER_CTRL0_FILTER_RESET = 0x80000000 + + // SAR1_DATA_STATUS: Register + // Position of APB_SARADC1_DATA field. + ADC_SAR1_DATA_STATUS_APB_SARADC1_DATA_Pos = 0x0 + // Bit mask of APB_SARADC1_DATA field. + ADC_SAR1_DATA_STATUS_APB_SARADC1_DATA_Msk = 0x1ffff + + // THRES0_CTRL: Register + // Position of THRES0_CHANNEL field. + ADC_THRES0_CTRL_THRES0_CHANNEL_Pos = 0x0 + // Bit mask of THRES0_CHANNEL field. + ADC_THRES0_CTRL_THRES0_CHANNEL_Msk = 0x1f + // Position of THRES0_HIGH field. + ADC_THRES0_CTRL_THRES0_HIGH_Pos = 0x5 + // Bit mask of THRES0_HIGH field. + ADC_THRES0_CTRL_THRES0_HIGH_Msk = 0x3ffe0 + // Position of THRES0_LOW field. + ADC_THRES0_CTRL_THRES0_LOW_Pos = 0x12 + // Bit mask of THRES0_LOW field. + ADC_THRES0_CTRL_THRES0_LOW_Msk = 0x7ffc0000 + + // THRES1_CTRL: Register + // Position of THRES1_CHANNEL field. + ADC_THRES1_CTRL_THRES1_CHANNEL_Pos = 0x0 + // Bit mask of THRES1_CHANNEL field. + ADC_THRES1_CTRL_THRES1_CHANNEL_Msk = 0x1f + // Position of THRES1_HIGH field. + ADC_THRES1_CTRL_THRES1_HIGH_Pos = 0x5 + // Bit mask of THRES1_HIGH field. + ADC_THRES1_CTRL_THRES1_HIGH_Msk = 0x3ffe0 + // Position of THRES1_LOW field. + ADC_THRES1_CTRL_THRES1_LOW_Pos = 0x12 + // Bit mask of THRES1_LOW field. + ADC_THRES1_CTRL_THRES1_LOW_Msk = 0x7ffc0000 + + // THRES_CTRL: Register + // Position of THRES_ALL_EN field. + ADC_THRES_CTRL_THRES_ALL_EN_Pos = 0x1b + // Bit mask of THRES_ALL_EN field. + ADC_THRES_CTRL_THRES_ALL_EN_Msk = 0x8000000 + // Bit THRES_ALL_EN. + ADC_THRES_CTRL_THRES_ALL_EN = 0x8000000 + // Position of THRES3_EN field. + ADC_THRES_CTRL_THRES3_EN_Pos = 0x1c + // Bit mask of THRES3_EN field. + ADC_THRES_CTRL_THRES3_EN_Msk = 0x10000000 + // Bit THRES3_EN. + ADC_THRES_CTRL_THRES3_EN = 0x10000000 + // Position of THRES2_EN field. + ADC_THRES_CTRL_THRES2_EN_Pos = 0x1d + // Bit mask of THRES2_EN field. + ADC_THRES_CTRL_THRES2_EN_Msk = 0x20000000 + // Bit THRES2_EN. + ADC_THRES_CTRL_THRES2_EN = 0x20000000 + // Position of THRES1_EN field. + ADC_THRES_CTRL_THRES1_EN_Pos = 0x1e + // Bit mask of THRES1_EN field. + ADC_THRES_CTRL_THRES1_EN_Msk = 0x40000000 + // Bit THRES1_EN. + ADC_THRES_CTRL_THRES1_EN = 0x40000000 + // Position of THRES0_EN field. + ADC_THRES_CTRL_THRES0_EN_Pos = 0x1f + // Bit mask of THRES0_EN field. + ADC_THRES_CTRL_THRES0_EN_Msk = 0x80000000 + // Bit THRES0_EN. + ADC_THRES_CTRL_THRES0_EN = 0x80000000 + + // INT_ENA: Register + // Position of THRES1_LOW_INT_ENA field. + ADC_INT_ENA_THRES1_LOW_INT_ENA_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_ENA field. + ADC_INT_ENA_THRES1_LOW_INT_ENA_Msk = 0x4000000 + // Bit THRES1_LOW_INT_ENA. + ADC_INT_ENA_THRES1_LOW_INT_ENA = 0x4000000 + // Position of THRES0_LOW_INT_ENA field. + ADC_INT_ENA_THRES0_LOW_INT_ENA_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_ENA field. + ADC_INT_ENA_THRES0_LOW_INT_ENA_Msk = 0x8000000 + // Bit THRES0_LOW_INT_ENA. + ADC_INT_ENA_THRES0_LOW_INT_ENA = 0x8000000 + // Position of THRES1_HIGH_INT_ENA field. + ADC_INT_ENA_THRES1_HIGH_INT_ENA_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_ENA field. + ADC_INT_ENA_THRES1_HIGH_INT_ENA_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_ENA. + ADC_INT_ENA_THRES1_HIGH_INT_ENA = 0x10000000 + // Position of THRES0_HIGH_INT_ENA field. + ADC_INT_ENA_THRES0_HIGH_INT_ENA_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_ENA field. + ADC_INT_ENA_THRES0_HIGH_INT_ENA_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_ENA. + ADC_INT_ENA_THRES0_HIGH_INT_ENA = 0x20000000 + // Position of SAR2_DONE_INT_ENA field. + ADC_INT_ENA_SAR2_DONE_INT_ENA_Pos = 0x1e + // Bit mask of SAR2_DONE_INT_ENA field. + ADC_INT_ENA_SAR2_DONE_INT_ENA_Msk = 0x40000000 + // Bit SAR2_DONE_INT_ENA. + ADC_INT_ENA_SAR2_DONE_INT_ENA = 0x40000000 + // Position of SAR1_DONE_INT_ENA field. + ADC_INT_ENA_SAR1_DONE_INT_ENA_Pos = 0x1f + // Bit mask of SAR1_DONE_INT_ENA field. + ADC_INT_ENA_SAR1_DONE_INT_ENA_Msk = 0x80000000 + // Bit SAR1_DONE_INT_ENA. + ADC_INT_ENA_SAR1_DONE_INT_ENA = 0x80000000 + + // INT_RAW: Register + // Position of THRES1_LOW_INT_RAW field. + ADC_INT_RAW_THRES1_LOW_INT_RAW_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_RAW field. + ADC_INT_RAW_THRES1_LOW_INT_RAW_Msk = 0x4000000 + // Bit THRES1_LOW_INT_RAW. + ADC_INT_RAW_THRES1_LOW_INT_RAW = 0x4000000 + // Position of THRES0_LOW_INT_RAW field. + ADC_INT_RAW_THRES0_LOW_INT_RAW_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_RAW field. + ADC_INT_RAW_THRES0_LOW_INT_RAW_Msk = 0x8000000 + // Bit THRES0_LOW_INT_RAW. + ADC_INT_RAW_THRES0_LOW_INT_RAW = 0x8000000 + // Position of THRES1_HIGH_INT_RAW field. + ADC_INT_RAW_THRES1_HIGH_INT_RAW_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_RAW field. + ADC_INT_RAW_THRES1_HIGH_INT_RAW_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_RAW. + ADC_INT_RAW_THRES1_HIGH_INT_RAW = 0x10000000 + // Position of THRES0_HIGH_INT_RAW field. + ADC_INT_RAW_THRES0_HIGH_INT_RAW_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_RAW field. + ADC_INT_RAW_THRES0_HIGH_INT_RAW_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_RAW. + ADC_INT_RAW_THRES0_HIGH_INT_RAW = 0x20000000 + // Position of SAR2_DONE_INT_RAW field. + ADC_INT_RAW_SAR2_DONE_INT_RAW_Pos = 0x1e + // Bit mask of SAR2_DONE_INT_RAW field. + ADC_INT_RAW_SAR2_DONE_INT_RAW_Msk = 0x40000000 + // Bit SAR2_DONE_INT_RAW. + ADC_INT_RAW_SAR2_DONE_INT_RAW = 0x40000000 + // Position of SAR1_DONE_INT_RAW field. + ADC_INT_RAW_SAR1_DONE_INT_RAW_Pos = 0x1f + // Bit mask of SAR1_DONE_INT_RAW field. + ADC_INT_RAW_SAR1_DONE_INT_RAW_Msk = 0x80000000 + // Bit SAR1_DONE_INT_RAW. + ADC_INT_RAW_SAR1_DONE_INT_RAW = 0x80000000 + + // INT_ST: Register + // Position of THRES1_LOW_INT_ST field. + ADC_INT_ST_THRES1_LOW_INT_ST_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_ST field. + ADC_INT_ST_THRES1_LOW_INT_ST_Msk = 0x4000000 + // Bit THRES1_LOW_INT_ST. + ADC_INT_ST_THRES1_LOW_INT_ST = 0x4000000 + // Position of THRES0_LOW_INT_ST field. + ADC_INT_ST_THRES0_LOW_INT_ST_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_ST field. + ADC_INT_ST_THRES0_LOW_INT_ST_Msk = 0x8000000 + // Bit THRES0_LOW_INT_ST. + ADC_INT_ST_THRES0_LOW_INT_ST = 0x8000000 + // Position of THRES1_HIGH_INT_ST field. + ADC_INT_ST_THRES1_HIGH_INT_ST_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_ST field. + ADC_INT_ST_THRES1_HIGH_INT_ST_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_ST. + ADC_INT_ST_THRES1_HIGH_INT_ST = 0x10000000 + // Position of THRES0_HIGH_INT_ST field. + ADC_INT_ST_THRES0_HIGH_INT_ST_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_ST field. + ADC_INT_ST_THRES0_HIGH_INT_ST_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_ST. + ADC_INT_ST_THRES0_HIGH_INT_ST = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ST field. + ADC_INT_ST_APB_SARADC2_DONE_INT_ST_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ST field. + ADC_INT_ST_APB_SARADC2_DONE_INT_ST_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ST. + ADC_INT_ST_APB_SARADC2_DONE_INT_ST = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ST field. + ADC_INT_ST_APB_SARADC1_DONE_INT_ST_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ST field. + ADC_INT_ST_APB_SARADC1_DONE_INT_ST_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ST. + ADC_INT_ST_APB_SARADC1_DONE_INT_ST = 0x80000000 + + // INT_CLR: Register + // Position of THRES1_LOW_INT_CLR field. + ADC_INT_CLR_THRES1_LOW_INT_CLR_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_CLR field. + ADC_INT_CLR_THRES1_LOW_INT_CLR_Msk = 0x4000000 + // Bit THRES1_LOW_INT_CLR. + ADC_INT_CLR_THRES1_LOW_INT_CLR = 0x4000000 + // Position of THRES0_LOW_INT_CLR field. + ADC_INT_CLR_THRES0_LOW_INT_CLR_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_CLR field. + ADC_INT_CLR_THRES0_LOW_INT_CLR_Msk = 0x8000000 + // Bit THRES0_LOW_INT_CLR. + ADC_INT_CLR_THRES0_LOW_INT_CLR = 0x8000000 + // Position of THRES1_HIGH_INT_CLR field. + ADC_INT_CLR_THRES1_HIGH_INT_CLR_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_CLR field. + ADC_INT_CLR_THRES1_HIGH_INT_CLR_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_CLR. + ADC_INT_CLR_THRES1_HIGH_INT_CLR = 0x10000000 + // Position of THRES0_HIGH_INT_CLR field. + ADC_INT_CLR_THRES0_HIGH_INT_CLR_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_CLR field. + ADC_INT_CLR_THRES0_HIGH_INT_CLR_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_CLR. + ADC_INT_CLR_THRES0_HIGH_INT_CLR = 0x20000000 + // Position of APB_SARADC2_DONE_INT_CLR field. + ADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_CLR field. + ADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_CLR. + ADC_INT_CLR_APB_SARADC2_DONE_INT_CLR = 0x40000000 + // Position of APB_SARADC1_DONE_INT_CLR field. + ADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_CLR field. + ADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_CLR. + ADC_INT_CLR_APB_SARADC1_DONE_INT_CLR = 0x80000000 + + // DMA_CONF: Register + // Position of APB_ADC_EOF_NUM field. + ADC_DMA_CONF_APB_ADC_EOF_NUM_Pos = 0x0 + // Bit mask of APB_ADC_EOF_NUM field. + ADC_DMA_CONF_APB_ADC_EOF_NUM_Msk = 0xffff + // Position of APB_ADC_RESET_FSM field. + ADC_DMA_CONF_APB_ADC_RESET_FSM_Pos = 0x1e + // Bit mask of APB_ADC_RESET_FSM field. + ADC_DMA_CONF_APB_ADC_RESET_FSM_Msk = 0x40000000 + // Bit APB_ADC_RESET_FSM. + ADC_DMA_CONF_APB_ADC_RESET_FSM = 0x40000000 + // Position of APB_ADC_TRANS field. + ADC_DMA_CONF_APB_ADC_TRANS_Pos = 0x1f + // Bit mask of APB_ADC_TRANS field. + ADC_DMA_CONF_APB_ADC_TRANS_Msk = 0x80000000 + // Bit APB_ADC_TRANS. + ADC_DMA_CONF_APB_ADC_TRANS = 0x80000000 + + // SAR2_DATA_STATUS: Register + // Position of APB_SARADC2_DATA field. + ADC_SAR2_DATA_STATUS_APB_SARADC2_DATA_Pos = 0x0 + // Bit mask of APB_SARADC2_DATA field. + ADC_SAR2_DATA_STATUS_APB_SARADC2_DATA_Msk = 0x1ffff + + // CALI: Register + // Position of CFG field. + ADC_CALI_CFG_Pos = 0x0 + // Bit mask of CFG field. + ADC_CALI_CFG_Msk = 0x1ffff + + // RND_ECO_LOW: Register + // Position of RND_ECO_LOW field. + ADC_RND_ECO_LOW_RND_ECO_LOW_Pos = 0x0 + // Bit mask of RND_ECO_LOW field. + ADC_RND_ECO_LOW_RND_ECO_LOW_Msk = 0xffffffff + + // RND_ECO_HIGH: Register + // Position of RND_ECO_HIGH field. + ADC_RND_ECO_HIGH_RND_ECO_HIGH_Pos = 0x0 + // Bit mask of RND_ECO_HIGH field. + ADC_RND_ECO_HIGH_RND_ECO_HIGH_Msk = 0xffffffff + + // RND_ECO_CS: Register + // Position of RND_ECO_EN field. + ADC_RND_ECO_CS_RND_ECO_EN_Pos = 0x0 + // Bit mask of RND_ECO_EN field. + ADC_RND_ECO_CS_RND_ECO_EN_Msk = 0x1 + // Bit RND_ECO_EN. + ADC_RND_ECO_CS_RND_ECO_EN = 0x1 + // Position of RND_ECO_RESULT field. + ADC_RND_ECO_CS_RND_ECO_RESULT_Pos = 0x1 + // Bit mask of RND_ECO_RESULT field. + ADC_RND_ECO_CS_RND_ECO_RESULT_Msk = 0x2 + // Bit RND_ECO_RESULT. + ADC_RND_ECO_CS_RND_ECO_RESULT = 0x2 + + // CTRL_DATE: Register + // Position of CTRL_DATE field. + ADC_CTRL_DATE_CTRL_DATE_Pos = 0x0 + // Bit mask of CTRL_DATE field. + ADC_CTRL_DATE_CTRL_DATE_Msk = 0x7fffffff + // Position of CLK_EN field. + ADC_CTRL_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + ADC_CTRL_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + ADC_CTRL_DATE_CLK_EN = 0x80000000 +) + +// Constants for AES: AES (Advanced Encryption Standard) Accelerator +const ( + // KEY_0: Key material key_0 configure register + // Position of KEY_0 field. + AES_KEY_0_KEY_0_Pos = 0x0 + // Bit mask of KEY_0 field. + AES_KEY_0_KEY_0_Msk = 0xffffffff + + // KEY_1: Key material key_1 configure register + // Position of KEY_1 field. + AES_KEY_1_KEY_1_Pos = 0x0 + // Bit mask of KEY_1 field. + AES_KEY_1_KEY_1_Msk = 0xffffffff + + // KEY_2: Key material key_2 configure register + // Position of KEY_2 field. + AES_KEY_2_KEY_2_Pos = 0x0 + // Bit mask of KEY_2 field. + AES_KEY_2_KEY_2_Msk = 0xffffffff + + // KEY_3: Key material key_3 configure register + // Position of KEY_3 field. + AES_KEY_3_KEY_3_Pos = 0x0 + // Bit mask of KEY_3 field. + AES_KEY_3_KEY_3_Msk = 0xffffffff + + // KEY_4: Key material key_4 configure register + // Position of KEY_4 field. + AES_KEY_4_KEY_4_Pos = 0x0 + // Bit mask of KEY_4 field. + AES_KEY_4_KEY_4_Msk = 0xffffffff + + // KEY_5: Key material key_5 configure register + // Position of KEY_5 field. + AES_KEY_5_KEY_5_Pos = 0x0 + // Bit mask of KEY_5 field. + AES_KEY_5_KEY_5_Msk = 0xffffffff + + // KEY_6: Key material key_6 configure register + // Position of KEY_6 field. + AES_KEY_6_KEY_6_Pos = 0x0 + // Bit mask of KEY_6 field. + AES_KEY_6_KEY_6_Msk = 0xffffffff + + // KEY_7: Key material key_7 configure register + // Position of KEY_7 field. + AES_KEY_7_KEY_7_Pos = 0x0 + // Bit mask of KEY_7 field. + AES_KEY_7_KEY_7_Msk = 0xffffffff + + // TEXT_IN_0: source text material text_in_0 configure register + // Position of TEXT_IN_0 field. + AES_TEXT_IN_0_TEXT_IN_0_Pos = 0x0 + // Bit mask of TEXT_IN_0 field. + AES_TEXT_IN_0_TEXT_IN_0_Msk = 0xffffffff + + // TEXT_IN_1: source text material text_in_1 configure register + // Position of TEXT_IN_1 field. + AES_TEXT_IN_1_TEXT_IN_1_Pos = 0x0 + // Bit mask of TEXT_IN_1 field. + AES_TEXT_IN_1_TEXT_IN_1_Msk = 0xffffffff + + // TEXT_IN_2: source text material text_in_2 configure register + // Position of TEXT_IN_2 field. + AES_TEXT_IN_2_TEXT_IN_2_Pos = 0x0 + // Bit mask of TEXT_IN_2 field. + AES_TEXT_IN_2_TEXT_IN_2_Msk = 0xffffffff + + // TEXT_IN_3: source text material text_in_3 configure register + // Position of TEXT_IN_3 field. + AES_TEXT_IN_3_TEXT_IN_3_Pos = 0x0 + // Bit mask of TEXT_IN_3 field. + AES_TEXT_IN_3_TEXT_IN_3_Msk = 0xffffffff + + // TEXT_OUT_0: result text material text_out_0 configure register + // Position of TEXT_OUT_0 field. + AES_TEXT_OUT_0_TEXT_OUT_0_Pos = 0x0 + // Bit mask of TEXT_OUT_0 field. + AES_TEXT_OUT_0_TEXT_OUT_0_Msk = 0xffffffff + + // TEXT_OUT_1: result text material text_out_1 configure register + // Position of TEXT_OUT_1 field. + AES_TEXT_OUT_1_TEXT_OUT_1_Pos = 0x0 + // Bit mask of TEXT_OUT_1 field. + AES_TEXT_OUT_1_TEXT_OUT_1_Msk = 0xffffffff + + // TEXT_OUT_2: result text material text_out_2 configure register + // Position of TEXT_OUT_2 field. + AES_TEXT_OUT_2_TEXT_OUT_2_Pos = 0x0 + // Bit mask of TEXT_OUT_2 field. + AES_TEXT_OUT_2_TEXT_OUT_2_Msk = 0xffffffff + + // TEXT_OUT_3: result text material text_out_3 configure register + // Position of TEXT_OUT_3 field. + AES_TEXT_OUT_3_TEXT_OUT_3_Pos = 0x0 + // Bit mask of TEXT_OUT_3 field. + AES_TEXT_OUT_3_TEXT_OUT_3_Msk = 0xffffffff + + // MODE: AES Mode register + // Position of MODE field. + AES_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + AES_MODE_MODE_Msk = 0x7 + + // ENDIAN: AES Endian configure register + // Position of ENDIAN field. + AES_ENDIAN_ENDIAN_Pos = 0x0 + // Bit mask of ENDIAN field. + AES_ENDIAN_ENDIAN_Msk = 0x3f + + // TRIGGER: AES trigger register + // Position of TRIGGER field. + AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + AES_TRIGGER_TRIGGER = 0x1 + + // STATE: AES state register + // Position of STATE field. + AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + AES_STATE_STATE_Msk = 0x3 + + // DMA_ENABLE: DMA-AES working mode register + // Position of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Pos = 0x0 + // Bit mask of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Msk = 0x1 + // Bit DMA_ENABLE. + AES_DMA_ENABLE_DMA_ENABLE = 0x1 + + // BLOCK_MODE: AES cipher block mode register + // Position of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Pos = 0x0 + // Bit mask of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Msk = 0x7 + + // BLOCK_NUM: AES block number register + // Position of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Pos = 0x0 + // Bit mask of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Msk = 0xffffffff + + // INC_SEL: Standard incrementing function configure register + // Position of INC_SEL field. + AES_INC_SEL_INC_SEL_Pos = 0x0 + // Bit mask of INC_SEL field. + AES_INC_SEL_INC_SEL_Msk = 0x1 + // Bit INC_SEL. + AES_INC_SEL_INC_SEL = 0x1 + + // AAD_BLOCK_NUM: Additional Authential Data block number register + // Position of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Pos = 0x0 + // Bit mask of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Msk = 0xffffffff + + // REMAINDER_BIT_NUM: AES remainder bit number register + // Position of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Pos = 0x0 + // Bit mask of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Msk = 0x7f + + // CONTINUE: AES continue register + // Position of CONTINUE field. + AES_CONTINUE_CONTINUE_Pos = 0x0 + // Bit mask of CONTINUE field. + AES_CONTINUE_CONTINUE_Msk = 0x1 + // Bit CONTINUE. + AES_CONTINUE_CONTINUE = 0x1 + + // INT_CLEAR: AES Interrupt clear register + // Position of INT_CLEAR field. + AES_INT_CLEAR_INT_CLEAR_Pos = 0x0 + // Bit mask of INT_CLEAR field. + AES_INT_CLEAR_INT_CLEAR_Msk = 0x1 + // Bit INT_CLEAR. + AES_INT_CLEAR_INT_CLEAR = 0x1 + + // INT_ENA: AES Interrupt enable register + // Position of INT_ENA field. + AES_INT_ENA_INT_ENA_Pos = 0x0 + // Bit mask of INT_ENA field. + AES_INT_ENA_INT_ENA_Msk = 0x1 + // Bit INT_ENA. + AES_INT_ENA_INT_ENA = 0x1 + + // DATE: AES version control register + // Position of DATE field. + AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + AES_DATE_DATE_Msk = 0x3fffffff + + // DMA_EXIT: AES-DMA exit config + // Position of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Pos = 0x0 + // Bit mask of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Msk = 0x1 + // Bit DMA_EXIT. + AES_DMA_EXIT_DMA_EXIT = 0x1 +) + +// Constants for AHB_DMA: AHB_DMA Peripheral +const ( + // IN_INT_RAW_CH0: Raw status interrupt of channel 0 + // Position of IN_DONE_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_DONE_CH_INT_RAW_Pos = 0x0 + // Bit mask of IN_DONE_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_DONE_CH_INT_RAW_Msk = 0x1 + // Bit IN_DONE_CH_INT_RAW. + AHB_DMA_IN_INT_RAW_CH_IN_DONE_CH_INT_RAW = 0x1 + // Position of IN_SUC_EOF_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_SUC_EOF_CH_INT_RAW_Pos = 0x1 + // Bit mask of IN_SUC_EOF_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_SUC_EOF_CH_INT_RAW_Msk = 0x2 + // Bit IN_SUC_EOF_CH_INT_RAW. + AHB_DMA_IN_INT_RAW_CH_IN_SUC_EOF_CH_INT_RAW = 0x2 + // Position of IN_ERR_EOF_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_ERR_EOF_CH_INT_RAW_Pos = 0x2 + // Bit mask of IN_ERR_EOF_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_ERR_EOF_CH_INT_RAW_Msk = 0x4 + // Bit IN_ERR_EOF_CH_INT_RAW. + AHB_DMA_IN_INT_RAW_CH_IN_ERR_EOF_CH_INT_RAW = 0x4 + // Position of IN_DSCR_ERR_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_DSCR_ERR_CH_INT_RAW_Pos = 0x3 + // Bit mask of IN_DSCR_ERR_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_DSCR_ERR_CH_INT_RAW_Msk = 0x8 + // Bit IN_DSCR_ERR_CH_INT_RAW. + AHB_DMA_IN_INT_RAW_CH_IN_DSCR_ERR_CH_INT_RAW = 0x8 + // Position of IN_DSCR_EMPTY_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_CH_INT_RAW_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_CH_INT_RAW_Msk = 0x10 + // Bit IN_DSCR_EMPTY_CH_INT_RAW. + AHB_DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_CH_INT_RAW = 0x10 + // Position of INFIFO_OVF_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_INFIFO_OVF_CH_INT_RAW_Pos = 0x5 + // Bit mask of INFIFO_OVF_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_INFIFO_OVF_CH_INT_RAW_Msk = 0x20 + // Bit INFIFO_OVF_CH_INT_RAW. + AHB_DMA_IN_INT_RAW_CH_INFIFO_OVF_CH_INT_RAW = 0x20 + // Position of INFIFO_UDF_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_INFIFO_UDF_CH_INT_RAW_Pos = 0x6 + // Bit mask of INFIFO_UDF_CH_INT_RAW field. + AHB_DMA_IN_INT_RAW_CH_INFIFO_UDF_CH_INT_RAW_Msk = 0x40 + // Bit INFIFO_UDF_CH_INT_RAW. + AHB_DMA_IN_INT_RAW_CH_INFIFO_UDF_CH_INT_RAW = 0x40 + + // IN_INT_ST_CH0: Masked interrupt of channel 0 + // Position of IN_DONE_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_DONE_CH_INT_ST_Pos = 0x0 + // Bit mask of IN_DONE_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_DONE_CH_INT_ST_Msk = 0x1 + // Bit IN_DONE_CH_INT_ST. + AHB_DMA_IN_INT_ST_CH_IN_DONE_CH_INT_ST = 0x1 + // Position of IN_SUC_EOF_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_SUC_EOF_CH_INT_ST_Pos = 0x1 + // Bit mask of IN_SUC_EOF_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_SUC_EOF_CH_INT_ST_Msk = 0x2 + // Bit IN_SUC_EOF_CH_INT_ST. + AHB_DMA_IN_INT_ST_CH_IN_SUC_EOF_CH_INT_ST = 0x2 + // Position of IN_ERR_EOF_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_ERR_EOF_CH_INT_ST_Pos = 0x2 + // Bit mask of IN_ERR_EOF_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_ERR_EOF_CH_INT_ST_Msk = 0x4 + // Bit IN_ERR_EOF_CH_INT_ST. + AHB_DMA_IN_INT_ST_CH_IN_ERR_EOF_CH_INT_ST = 0x4 + // Position of IN_DSCR_ERR_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_DSCR_ERR_CH_INT_ST_Pos = 0x3 + // Bit mask of IN_DSCR_ERR_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_DSCR_ERR_CH_INT_ST_Msk = 0x8 + // Bit IN_DSCR_ERR_CH_INT_ST. + AHB_DMA_IN_INT_ST_CH_IN_DSCR_ERR_CH_INT_ST = 0x8 + // Position of IN_DSCR_EMPTY_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_CH_INT_ST_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_CH_INT_ST_Msk = 0x10 + // Bit IN_DSCR_EMPTY_CH_INT_ST. + AHB_DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_CH_INT_ST = 0x10 + // Position of INFIFO_OVF_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_INFIFO_OVF_CH_INT_ST_Pos = 0x5 + // Bit mask of INFIFO_OVF_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_INFIFO_OVF_CH_INT_ST_Msk = 0x20 + // Bit INFIFO_OVF_CH_INT_ST. + AHB_DMA_IN_INT_ST_CH_INFIFO_OVF_CH_INT_ST = 0x20 + // Position of INFIFO_UDF_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_INFIFO_UDF_CH_INT_ST_Pos = 0x6 + // Bit mask of INFIFO_UDF_CH_INT_ST field. + AHB_DMA_IN_INT_ST_CH_INFIFO_UDF_CH_INT_ST_Msk = 0x40 + // Bit INFIFO_UDF_CH_INT_ST. + AHB_DMA_IN_INT_ST_CH_INFIFO_UDF_CH_INT_ST = 0x40 + + // IN_INT_ENA_CH0: Interrupt enable bits of channel 0 + // Position of IN_DONE_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_DONE_CH_INT_ENA_Pos = 0x0 + // Bit mask of IN_DONE_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_DONE_CH_INT_ENA_Msk = 0x1 + // Bit IN_DONE_CH_INT_ENA. + AHB_DMA_IN_INT_ENA_CH_IN_DONE_CH_INT_ENA = 0x1 + // Position of IN_SUC_EOF_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_SUC_EOF_CH_INT_ENA_Pos = 0x1 + // Bit mask of IN_SUC_EOF_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_SUC_EOF_CH_INT_ENA_Msk = 0x2 + // Bit IN_SUC_EOF_CH_INT_ENA. + AHB_DMA_IN_INT_ENA_CH_IN_SUC_EOF_CH_INT_ENA = 0x2 + // Position of IN_ERR_EOF_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_ERR_EOF_CH_INT_ENA_Pos = 0x2 + // Bit mask of IN_ERR_EOF_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_ERR_EOF_CH_INT_ENA_Msk = 0x4 + // Bit IN_ERR_EOF_CH_INT_ENA. + AHB_DMA_IN_INT_ENA_CH_IN_ERR_EOF_CH_INT_ENA = 0x4 + // Position of IN_DSCR_ERR_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_DSCR_ERR_CH_INT_ENA_Pos = 0x3 + // Bit mask of IN_DSCR_ERR_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_DSCR_ERR_CH_INT_ENA_Msk = 0x8 + // Bit IN_DSCR_ERR_CH_INT_ENA. + AHB_DMA_IN_INT_ENA_CH_IN_DSCR_ERR_CH_INT_ENA = 0x8 + // Position of IN_DSCR_EMPTY_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_CH_INT_ENA_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_CH_INT_ENA_Msk = 0x10 + // Bit IN_DSCR_EMPTY_CH_INT_ENA. + AHB_DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_CH_INT_ENA = 0x10 + // Position of INFIFO_OVF_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_INFIFO_OVF_CH_INT_ENA_Pos = 0x5 + // Bit mask of INFIFO_OVF_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_INFIFO_OVF_CH_INT_ENA_Msk = 0x20 + // Bit INFIFO_OVF_CH_INT_ENA. + AHB_DMA_IN_INT_ENA_CH_INFIFO_OVF_CH_INT_ENA = 0x20 + // Position of INFIFO_UDF_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_INFIFO_UDF_CH_INT_ENA_Pos = 0x6 + // Bit mask of INFIFO_UDF_CH_INT_ENA field. + AHB_DMA_IN_INT_ENA_CH_INFIFO_UDF_CH_INT_ENA_Msk = 0x40 + // Bit INFIFO_UDF_CH_INT_ENA. + AHB_DMA_IN_INT_ENA_CH_INFIFO_UDF_CH_INT_ENA = 0x40 + + // IN_INT_CLR_CH0: Interrupt clear bits of channel 0 + // Position of IN_DONE_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_DONE_CH_INT_CLR_Pos = 0x0 + // Bit mask of IN_DONE_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_DONE_CH_INT_CLR_Msk = 0x1 + // Bit IN_DONE_CH_INT_CLR. + AHB_DMA_IN_INT_CLR_CH_IN_DONE_CH_INT_CLR = 0x1 + // Position of IN_SUC_EOF_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_SUC_EOF_CH_INT_CLR_Pos = 0x1 + // Bit mask of IN_SUC_EOF_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_SUC_EOF_CH_INT_CLR_Msk = 0x2 + // Bit IN_SUC_EOF_CH_INT_CLR. + AHB_DMA_IN_INT_CLR_CH_IN_SUC_EOF_CH_INT_CLR = 0x2 + // Position of IN_ERR_EOF_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_ERR_EOF_CH_INT_CLR_Pos = 0x2 + // Bit mask of IN_ERR_EOF_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_ERR_EOF_CH_INT_CLR_Msk = 0x4 + // Bit IN_ERR_EOF_CH_INT_CLR. + AHB_DMA_IN_INT_CLR_CH_IN_ERR_EOF_CH_INT_CLR = 0x4 + // Position of IN_DSCR_ERR_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_DSCR_ERR_CH_INT_CLR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_DSCR_ERR_CH_INT_CLR_Msk = 0x8 + // Bit IN_DSCR_ERR_CH_INT_CLR. + AHB_DMA_IN_INT_CLR_CH_IN_DSCR_ERR_CH_INT_CLR = 0x8 + // Position of IN_DSCR_EMPTY_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_CH_INT_CLR_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_CH_INT_CLR_Msk = 0x10 + // Bit IN_DSCR_EMPTY_CH_INT_CLR. + AHB_DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_CH_INT_CLR = 0x10 + // Position of INFIFO_OVF_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_INFIFO_OVF_CH_INT_CLR_Pos = 0x5 + // Bit mask of INFIFO_OVF_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_INFIFO_OVF_CH_INT_CLR_Msk = 0x20 + // Bit INFIFO_OVF_CH_INT_CLR. + AHB_DMA_IN_INT_CLR_CH_INFIFO_OVF_CH_INT_CLR = 0x20 + // Position of INFIFO_UDF_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_INFIFO_UDF_CH_INT_CLR_Pos = 0x6 + // Bit mask of INFIFO_UDF_CH_INT_CLR field. + AHB_DMA_IN_INT_CLR_CH_INFIFO_UDF_CH_INT_CLR_Msk = 0x40 + // Bit INFIFO_UDF_CH_INT_CLR. + AHB_DMA_IN_INT_CLR_CH_INFIFO_UDF_CH_INT_CLR = 0x40 + + // OUT_INT_RAW_CH0: Raw status interrupt of channel 0 + // Position of OUT_DONE_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUT_DONE_CH_INT_RAW_Pos = 0x0 + // Bit mask of OUT_DONE_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUT_DONE_CH_INT_RAW_Msk = 0x1 + // Bit OUT_DONE_CH_INT_RAW. + AHB_DMA_OUT_INT_RAW_CH_OUT_DONE_CH_INT_RAW = 0x1 + // Position of OUT_EOF_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUT_EOF_CH_INT_RAW_Pos = 0x1 + // Bit mask of OUT_EOF_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUT_EOF_CH_INT_RAW_Msk = 0x2 + // Bit OUT_EOF_CH_INT_RAW. + AHB_DMA_OUT_INT_RAW_CH_OUT_EOF_CH_INT_RAW = 0x2 + // Position of OUT_DSCR_ERR_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_CH_INT_RAW_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_CH_INT_RAW_Msk = 0x4 + // Bit OUT_DSCR_ERR_CH_INT_RAW. + AHB_DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_CH_INT_RAW = 0x4 + // Position of OUT_TOTAL_EOF_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_CH_INT_RAW_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_CH_INT_RAW_Msk = 0x8 + // Bit OUT_TOTAL_EOF_CH_INT_RAW. + AHB_DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_CH_INT_RAW = 0x8 + // Position of OUTFIFO_OVF_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_CH_INT_RAW_Pos = 0x4 + // Bit mask of OUTFIFO_OVF_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_CH_INT_RAW_Msk = 0x10 + // Bit OUTFIFO_OVF_CH_INT_RAW. + AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_CH_INT_RAW = 0x10 + // Position of OUTFIFO_UDF_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_CH_INT_RAW_Pos = 0x5 + // Bit mask of OUTFIFO_UDF_CH_INT_RAW field. + AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_CH_INT_RAW_Msk = 0x20 + // Bit OUTFIFO_UDF_CH_INT_RAW. + AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_CH_INT_RAW = 0x20 + + // OUT_INT_ST_CH0: Masked interrupt of channel 0 + // Position of OUT_DONE_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUT_DONE_CH_INT_ST_Pos = 0x0 + // Bit mask of OUT_DONE_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUT_DONE_CH_INT_ST_Msk = 0x1 + // Bit OUT_DONE_CH_INT_ST. + AHB_DMA_OUT_INT_ST_CH_OUT_DONE_CH_INT_ST = 0x1 + // Position of OUT_EOF_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUT_EOF_CH_INT_ST_Pos = 0x1 + // Bit mask of OUT_EOF_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUT_EOF_CH_INT_ST_Msk = 0x2 + // Bit OUT_EOF_CH_INT_ST. + AHB_DMA_OUT_INT_ST_CH_OUT_EOF_CH_INT_ST = 0x2 + // Position of OUT_DSCR_ERR_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_CH_INT_ST_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_CH_INT_ST_Msk = 0x4 + // Bit OUT_DSCR_ERR_CH_INT_ST. + AHB_DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_CH_INT_ST = 0x4 + // Position of OUT_TOTAL_EOF_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_CH_INT_ST_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_CH_INT_ST_Msk = 0x8 + // Bit OUT_TOTAL_EOF_CH_INT_ST. + AHB_DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_CH_INT_ST = 0x8 + // Position of OUTFIFO_OVF_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUTFIFO_OVF_CH_INT_ST_Pos = 0x4 + // Bit mask of OUTFIFO_OVF_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUTFIFO_OVF_CH_INT_ST_Msk = 0x10 + // Bit OUTFIFO_OVF_CH_INT_ST. + AHB_DMA_OUT_INT_ST_CH_OUTFIFO_OVF_CH_INT_ST = 0x10 + // Position of OUTFIFO_UDF_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUTFIFO_UDF_CH_INT_ST_Pos = 0x5 + // Bit mask of OUTFIFO_UDF_CH_INT_ST field. + AHB_DMA_OUT_INT_ST_CH_OUTFIFO_UDF_CH_INT_ST_Msk = 0x20 + // Bit OUTFIFO_UDF_CH_INT_ST. + AHB_DMA_OUT_INT_ST_CH_OUTFIFO_UDF_CH_INT_ST = 0x20 + + // OUT_INT_ENA_CH0: Interrupt enable bits of channel 0 + // Position of OUT_DONE_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUT_DONE_CH_INT_ENA_Pos = 0x0 + // Bit mask of OUT_DONE_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUT_DONE_CH_INT_ENA_Msk = 0x1 + // Bit OUT_DONE_CH_INT_ENA. + AHB_DMA_OUT_INT_ENA_CH_OUT_DONE_CH_INT_ENA = 0x1 + // Position of OUT_EOF_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUT_EOF_CH_INT_ENA_Pos = 0x1 + // Bit mask of OUT_EOF_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUT_EOF_CH_INT_ENA_Msk = 0x2 + // Bit OUT_EOF_CH_INT_ENA. + AHB_DMA_OUT_INT_ENA_CH_OUT_EOF_CH_INT_ENA = 0x2 + // Position of OUT_DSCR_ERR_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_CH_INT_ENA_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_CH_INT_ENA_Msk = 0x4 + // Bit OUT_DSCR_ERR_CH_INT_ENA. + AHB_DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_CH_INT_ENA = 0x4 + // Position of OUT_TOTAL_EOF_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_CH_INT_ENA_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_CH_INT_ENA_Msk = 0x8 + // Bit OUT_TOTAL_EOF_CH_INT_ENA. + AHB_DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_CH_INT_ENA = 0x8 + // Position of OUTFIFO_OVF_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_CH_INT_ENA_Pos = 0x4 + // Bit mask of OUTFIFO_OVF_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_CH_INT_ENA_Msk = 0x10 + // Bit OUTFIFO_OVF_CH_INT_ENA. + AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_CH_INT_ENA = 0x10 + // Position of OUTFIFO_UDF_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_CH_INT_ENA_Pos = 0x5 + // Bit mask of OUTFIFO_UDF_CH_INT_ENA field. + AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_CH_INT_ENA_Msk = 0x20 + // Bit OUTFIFO_UDF_CH_INT_ENA. + AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_CH_INT_ENA = 0x20 + + // OUT_INT_CLR_CH0: Interrupt clear bits of channel 0 + // Position of OUT_DONE_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUT_DONE_CH_INT_CLR_Pos = 0x0 + // Bit mask of OUT_DONE_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUT_DONE_CH_INT_CLR_Msk = 0x1 + // Bit OUT_DONE_CH_INT_CLR. + AHB_DMA_OUT_INT_CLR_CH_OUT_DONE_CH_INT_CLR = 0x1 + // Position of OUT_EOF_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUT_EOF_CH_INT_CLR_Pos = 0x1 + // Bit mask of OUT_EOF_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUT_EOF_CH_INT_CLR_Msk = 0x2 + // Bit OUT_EOF_CH_INT_CLR. + AHB_DMA_OUT_INT_CLR_CH_OUT_EOF_CH_INT_CLR = 0x2 + // Position of OUT_DSCR_ERR_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_CH_INT_CLR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_CH_INT_CLR_Msk = 0x4 + // Bit OUT_DSCR_ERR_CH_INT_CLR. + AHB_DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_CH_INT_CLR = 0x4 + // Position of OUT_TOTAL_EOF_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_CH_INT_CLR_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_CH_INT_CLR_Msk = 0x8 + // Bit OUT_TOTAL_EOF_CH_INT_CLR. + AHB_DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_CH_INT_CLR = 0x8 + // Position of OUTFIFO_OVF_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_CH_INT_CLR_Pos = 0x4 + // Bit mask of OUTFIFO_OVF_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_CH_INT_CLR_Msk = 0x10 + // Bit OUTFIFO_OVF_CH_INT_CLR. + AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_CH_INT_CLR = 0x10 + // Position of OUTFIFO_UDF_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_CH_INT_CLR_Pos = 0x5 + // Bit mask of OUTFIFO_UDF_CH_INT_CLR field. + AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_CH_INT_CLR_Msk = 0x20 + // Bit OUTFIFO_UDF_CH_INT_CLR. + AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_CH_INT_CLR = 0x20 + + // AHB_TEST: reserved + // Position of AHB_TESTMODE field. + AHB_DMA_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + AHB_DMA_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + AHB_DMA_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + AHB_DMA_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // MISC_CONF: MISC register + // Position of AHBM_RST_INTER field. + AHB_DMA_MISC_CONF_AHBM_RST_INTER_Pos = 0x0 + // Bit mask of AHBM_RST_INTER field. + AHB_DMA_MISC_CONF_AHBM_RST_INTER_Msk = 0x1 + // Bit AHBM_RST_INTER. + AHB_DMA_MISC_CONF_AHBM_RST_INTER = 0x1 + // Position of ARB_PRI_DIS field. + AHB_DMA_MISC_CONF_ARB_PRI_DIS_Pos = 0x2 + // Bit mask of ARB_PRI_DIS field. + AHB_DMA_MISC_CONF_ARB_PRI_DIS_Msk = 0x4 + // Bit ARB_PRI_DIS. + AHB_DMA_MISC_CONF_ARB_PRI_DIS = 0x4 + // Position of CLK_EN field. + AHB_DMA_MISC_CONF_CLK_EN_Pos = 0x3 + // Bit mask of CLK_EN field. + AHB_DMA_MISC_CONF_CLK_EN_Msk = 0x8 + // Bit CLK_EN. + AHB_DMA_MISC_CONF_CLK_EN = 0x8 + + // DATE: Version control register + // Position of DATE field. + AHB_DMA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + AHB_DMA_DATE_DATE_Msk = 0xffffffff + + // IN_CONF0_CH0: Configure 0 register of Rx channel 0 + // Position of IN_RST_CH field. + AHB_DMA_IN_CONF0_CH_IN_RST_CH_Pos = 0x0 + // Bit mask of IN_RST_CH field. + AHB_DMA_IN_CONF0_CH_IN_RST_CH_Msk = 0x1 + // Bit IN_RST_CH. + AHB_DMA_IN_CONF0_CH_IN_RST_CH = 0x1 + // Position of IN_LOOP_TEST_CH field. + AHB_DMA_IN_CONF0_CH_IN_LOOP_TEST_CH_Pos = 0x1 + // Bit mask of IN_LOOP_TEST_CH field. + AHB_DMA_IN_CONF0_CH_IN_LOOP_TEST_CH_Msk = 0x2 + // Bit IN_LOOP_TEST_CH. + AHB_DMA_IN_CONF0_CH_IN_LOOP_TEST_CH = 0x2 + // Position of INDSCR_BURST_EN_CH field. + AHB_DMA_IN_CONF0_CH_INDSCR_BURST_EN_CH_Pos = 0x2 + // Bit mask of INDSCR_BURST_EN_CH field. + AHB_DMA_IN_CONF0_CH_INDSCR_BURST_EN_CH_Msk = 0x4 + // Bit INDSCR_BURST_EN_CH. + AHB_DMA_IN_CONF0_CH_INDSCR_BURST_EN_CH = 0x4 + // Position of IN_DATA_BURST_EN_CH field. + AHB_DMA_IN_CONF0_CH_IN_DATA_BURST_EN_CH_Pos = 0x3 + // Bit mask of IN_DATA_BURST_EN_CH field. + AHB_DMA_IN_CONF0_CH_IN_DATA_BURST_EN_CH_Msk = 0x8 + // Bit IN_DATA_BURST_EN_CH. + AHB_DMA_IN_CONF0_CH_IN_DATA_BURST_EN_CH = 0x8 + // Position of MEM_TRANS_EN_CH field. + AHB_DMA_IN_CONF0_CH_MEM_TRANS_EN_CH_Pos = 0x4 + // Bit mask of MEM_TRANS_EN_CH field. + AHB_DMA_IN_CONF0_CH_MEM_TRANS_EN_CH_Msk = 0x10 + // Bit MEM_TRANS_EN_CH. + AHB_DMA_IN_CONF0_CH_MEM_TRANS_EN_CH = 0x10 + // Position of IN_ETM_EN_CH field. + AHB_DMA_IN_CONF0_CH_IN_ETM_EN_CH_Pos = 0x5 + // Bit mask of IN_ETM_EN_CH field. + AHB_DMA_IN_CONF0_CH_IN_ETM_EN_CH_Msk = 0x20 + // Bit IN_ETM_EN_CH. + AHB_DMA_IN_CONF0_CH_IN_ETM_EN_CH = 0x20 + + // IN_CONF1_CH0: Configure 1 register of Rx channel 0 + // Position of IN_CHECK_OWNER_CH field. + AHB_DMA_IN_CONF1_CH_IN_CHECK_OWNER_CH_Pos = 0xc + // Bit mask of IN_CHECK_OWNER_CH field. + AHB_DMA_IN_CONF1_CH_IN_CHECK_OWNER_CH_Msk = 0x1000 + // Bit IN_CHECK_OWNER_CH. + AHB_DMA_IN_CONF1_CH_IN_CHECK_OWNER_CH = 0x1000 + + // INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0 + // Position of INFIFO_FULL_CH field. + AHB_DMA_INFIFO_STATUS_CH_INFIFO_FULL_CH_Pos = 0x0 + // Bit mask of INFIFO_FULL_CH field. + AHB_DMA_INFIFO_STATUS_CH_INFIFO_FULL_CH_Msk = 0x1 + // Bit INFIFO_FULL_CH. + AHB_DMA_INFIFO_STATUS_CH_INFIFO_FULL_CH = 0x1 + // Position of INFIFO_EMPTY_CH field. + AHB_DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_CH_Pos = 0x1 + // Bit mask of INFIFO_EMPTY_CH field. + AHB_DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_CH_Msk = 0x2 + // Bit INFIFO_EMPTY_CH. + AHB_DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_CH = 0x2 + // Position of INFIFO_CNT_CH field. + AHB_DMA_INFIFO_STATUS_CH_INFIFO_CNT_CH_Pos = 0x2 + // Bit mask of INFIFO_CNT_CH field. + AHB_DMA_INFIFO_STATUS_CH_INFIFO_CNT_CH_Msk = 0xfc + // Position of IN_REMAIN_UNDER_1B_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_CH_Pos = 0x17 + // Bit mask of IN_REMAIN_UNDER_1B_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_CH_Msk = 0x800000 + // Bit IN_REMAIN_UNDER_1B_CH. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_CH = 0x800000 + // Position of IN_REMAIN_UNDER_2B_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_CH_Pos = 0x18 + // Bit mask of IN_REMAIN_UNDER_2B_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_CH_Msk = 0x1000000 + // Bit IN_REMAIN_UNDER_2B_CH. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_CH = 0x1000000 + // Position of IN_REMAIN_UNDER_3B_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_CH_Pos = 0x19 + // Bit mask of IN_REMAIN_UNDER_3B_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_CH_Msk = 0x2000000 + // Bit IN_REMAIN_UNDER_3B_CH. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_CH = 0x2000000 + // Position of IN_REMAIN_UNDER_4B_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_CH_Pos = 0x1a + // Bit mask of IN_REMAIN_UNDER_4B_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_CH_Msk = 0x4000000 + // Bit IN_REMAIN_UNDER_4B_CH. + AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_CH = 0x4000000 + // Position of IN_BUF_HUNGRY_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_CH_Pos = 0x1b + // Bit mask of IN_BUF_HUNGRY_CH field. + AHB_DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_CH_Msk = 0x8000000 + // Bit IN_BUF_HUNGRY_CH. + AHB_DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_CH = 0x8000000 + + // IN_POP_CH0: Pop control register of Rx channel 0 + // Position of INFIFO_RDATA_CH field. + AHB_DMA_IN_POP_CH_INFIFO_RDATA_CH_Pos = 0x0 + // Bit mask of INFIFO_RDATA_CH field. + AHB_DMA_IN_POP_CH_INFIFO_RDATA_CH_Msk = 0xfff + // Position of INFIFO_POP_CH field. + AHB_DMA_IN_POP_CH_INFIFO_POP_CH_Pos = 0xc + // Bit mask of INFIFO_POP_CH field. + AHB_DMA_IN_POP_CH_INFIFO_POP_CH_Msk = 0x1000 + // Bit INFIFO_POP_CH. + AHB_DMA_IN_POP_CH_INFIFO_POP_CH = 0x1000 + + // IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0 + // Position of INLINK_AUTO_RET_CH field. + AHB_DMA_IN_LINK_CH_INLINK_AUTO_RET_CH_Pos = 0x0 + // Bit mask of INLINK_AUTO_RET_CH field. + AHB_DMA_IN_LINK_CH_INLINK_AUTO_RET_CH_Msk = 0x1 + // Bit INLINK_AUTO_RET_CH. + AHB_DMA_IN_LINK_CH_INLINK_AUTO_RET_CH = 0x1 + // Position of INLINK_STOP_CH field. + AHB_DMA_IN_LINK_CH_INLINK_STOP_CH_Pos = 0x1 + // Bit mask of INLINK_STOP_CH field. + AHB_DMA_IN_LINK_CH_INLINK_STOP_CH_Msk = 0x2 + // Bit INLINK_STOP_CH. + AHB_DMA_IN_LINK_CH_INLINK_STOP_CH = 0x2 + // Position of INLINK_START_CH field. + AHB_DMA_IN_LINK_CH_INLINK_START_CH_Pos = 0x2 + // Bit mask of INLINK_START_CH field. + AHB_DMA_IN_LINK_CH_INLINK_START_CH_Msk = 0x4 + // Bit INLINK_START_CH. + AHB_DMA_IN_LINK_CH_INLINK_START_CH = 0x4 + // Position of INLINK_RESTART_CH field. + AHB_DMA_IN_LINK_CH_INLINK_RESTART_CH_Pos = 0x3 + // Bit mask of INLINK_RESTART_CH field. + AHB_DMA_IN_LINK_CH_INLINK_RESTART_CH_Msk = 0x8 + // Bit INLINK_RESTART_CH. + AHB_DMA_IN_LINK_CH_INLINK_RESTART_CH = 0x8 + // Position of INLINK_PARK_CH field. + AHB_DMA_IN_LINK_CH_INLINK_PARK_CH_Pos = 0x4 + // Bit mask of INLINK_PARK_CH field. + AHB_DMA_IN_LINK_CH_INLINK_PARK_CH_Msk = 0x10 + // Bit INLINK_PARK_CH. + AHB_DMA_IN_LINK_CH_INLINK_PARK_CH = 0x10 + + // IN_STATE_CH0: Receive status of Rx channel 0 + // Position of INLINK_DSCR_ADDR_CH field. + AHB_DMA_IN_STATE_CH_INLINK_DSCR_ADDR_CH_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR_CH field. + AHB_DMA_IN_STATE_CH_INLINK_DSCR_ADDR_CH_Msk = 0x3ffff + // Position of IN_DSCR_STATE_CH field. + AHB_DMA_IN_STATE_CH_IN_DSCR_STATE_CH_Pos = 0x12 + // Bit mask of IN_DSCR_STATE_CH field. + AHB_DMA_IN_STATE_CH_IN_DSCR_STATE_CH_Msk = 0xc0000 + // Position of IN_STATE_CH field. + AHB_DMA_IN_STATE_CH_IN_STATE_CH_Pos = 0x14 + // Bit mask of IN_STATE_CH field. + AHB_DMA_IN_STATE_CH_IN_STATE_CH_Msk = 0x700000 + + // IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0 + // Position of IN_SUC_EOF_DES_ADDR_CH field. + AHB_DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_CH_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR_CH field. + AHB_DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_CH_Msk = 0xffffffff + + // IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0 + // Position of IN_ERR_EOF_DES_ADDR_CH field. + AHB_DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_CH_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR_CH field. + AHB_DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_CH_Msk = 0xffffffff + + // IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR_CH field. + AHB_DMA_IN_DSCR_CH_INLINK_DSCR_CH_Pos = 0x0 + // Bit mask of INLINK_DSCR_CH field. + AHB_DMA_IN_DSCR_CH_INLINK_DSCR_CH_Msk = 0xffffffff + + // IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR_BF0_CH field. + AHB_DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_CH_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0_CH field. + AHB_DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_CH_Msk = 0xffffffff + + // IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR_BF1_CH field. + AHB_DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_CH_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1_CH field. + AHB_DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_CH_Msk = 0xffffffff + + // IN_PRI_CH0: Priority register of Rx channel 0 + // Position of RX_PRI_CH field. + AHB_DMA_IN_PRI_CH_RX_PRI_CH_Pos = 0x0 + // Bit mask of RX_PRI_CH field. + AHB_DMA_IN_PRI_CH_RX_PRI_CH_Msk = 0xf + + // IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0 + // Position of PERI_IN_SEL_CH field. + AHB_DMA_IN_PERI_SEL_CH_PERI_IN_SEL_CH_Pos = 0x0 + // Bit mask of PERI_IN_SEL_CH field. + AHB_DMA_IN_PERI_SEL_CH_PERI_IN_SEL_CH_Msk = 0x3f + + // OUT_CONF0_CH0: Configure 0 register of Tx channel 0 + // Position of OUT_RST_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_RST_CH0_Pos = 0x0 + // Bit mask of OUT_RST_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_RST_CH0_Msk = 0x1 + // Bit OUT_RST_CH0. + AHB_DMA_OUT_CONF0_CH0_OUT_RST_CH0 = 0x1 + // Position of OUT_LOOP_TEST_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_CH0_Pos = 0x1 + // Bit mask of OUT_LOOP_TEST_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_CH0_Msk = 0x2 + // Bit OUT_LOOP_TEST_CH0. + AHB_DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_CH0 = 0x2 + // Position of OUT_AUTO_WRBACK_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0_Pos = 0x2 + // Bit mask of OUT_AUTO_WRBACK_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0_Msk = 0x4 + // Bit OUT_AUTO_WRBACK_CH0. + AHB_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0 = 0x4 + // Position of OUT_EOF_MODE_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0_Pos = 0x3 + // Bit mask of OUT_EOF_MODE_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0_Msk = 0x8 + // Bit OUT_EOF_MODE_CH0. + AHB_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0 = 0x8 + // Position of OUTDSCR_BURST_EN_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0_Pos = 0x4 + // Bit mask of OUTDSCR_BURST_EN_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0_Msk = 0x10 + // Bit OUTDSCR_BURST_EN_CH0. + AHB_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0 = 0x10 + // Position of OUT_DATA_BURST_EN_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0_Pos = 0x5 + // Bit mask of OUT_DATA_BURST_EN_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0_Msk = 0x20 + // Bit OUT_DATA_BURST_EN_CH0. + AHB_DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0 = 0x20 + // Position of OUT_ETM_EN_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_ETM_EN_CH0_Pos = 0x6 + // Bit mask of OUT_ETM_EN_CH0 field. + AHB_DMA_OUT_CONF0_CH0_OUT_ETM_EN_CH0_Msk = 0x40 + // Bit OUT_ETM_EN_CH0. + AHB_DMA_OUT_CONF0_CH0_OUT_ETM_EN_CH0 = 0x40 + + // OUT_CONF1_CH0: Configure 1 register of Tx channel 0 + // Position of OUT_CHECK_OWNER_CH field. + AHB_DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_CH_Pos = 0xc + // Bit mask of OUT_CHECK_OWNER_CH field. + AHB_DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_CH_Msk = 0x1000 + // Bit OUT_CHECK_OWNER_CH. + AHB_DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_CH = 0x1000 + + // OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0 + // Position of OUTFIFO_FULL_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_CH_Pos = 0x0 + // Bit mask of OUTFIFO_FULL_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_CH_Msk = 0x1 + // Bit OUTFIFO_FULL_CH. + AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_CH = 0x1 + // Position of OUTFIFO_EMPTY_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_CH_Pos = 0x1 + // Bit mask of OUTFIFO_EMPTY_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_CH_Msk = 0x2 + // Bit OUTFIFO_EMPTY_CH. + AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_CH = 0x2 + // Position of OUTFIFO_CNT_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_CH_Pos = 0x2 + // Bit mask of OUTFIFO_CNT_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_CH_Msk = 0xfc + // Position of OUT_REMAIN_UNDER_1B_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_CH_Pos = 0x17 + // Bit mask of OUT_REMAIN_UNDER_1B_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_CH_Msk = 0x800000 + // Bit OUT_REMAIN_UNDER_1B_CH. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_CH = 0x800000 + // Position of OUT_REMAIN_UNDER_2B_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_CH_Pos = 0x18 + // Bit mask of OUT_REMAIN_UNDER_2B_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_CH_Msk = 0x1000000 + // Bit OUT_REMAIN_UNDER_2B_CH. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_CH = 0x1000000 + // Position of OUT_REMAIN_UNDER_3B_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_CH_Pos = 0x19 + // Bit mask of OUT_REMAIN_UNDER_3B_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_CH_Msk = 0x2000000 + // Bit OUT_REMAIN_UNDER_3B_CH. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_CH = 0x2000000 + // Position of OUT_REMAIN_UNDER_4B_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_CH_Pos = 0x1a + // Bit mask of OUT_REMAIN_UNDER_4B_CH field. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_CH_Msk = 0x4000000 + // Bit OUT_REMAIN_UNDER_4B_CH. + AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_CH = 0x4000000 + + // OUT_PUSH_CH0: Push control register of Rx channel 0 + // Position of OUTFIFO_WDATA_CH field. + AHB_DMA_OUT_PUSH_CH_OUTFIFO_WDATA_CH_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA_CH field. + AHB_DMA_OUT_PUSH_CH_OUTFIFO_WDATA_CH_Msk = 0x1ff + // Position of OUTFIFO_PUSH_CH field. + AHB_DMA_OUT_PUSH_CH_OUTFIFO_PUSH_CH_Pos = 0x9 + // Bit mask of OUTFIFO_PUSH_CH field. + AHB_DMA_OUT_PUSH_CH_OUTFIFO_PUSH_CH_Msk = 0x200 + // Bit OUTFIFO_PUSH_CH. + AHB_DMA_OUT_PUSH_CH_OUTFIFO_PUSH_CH = 0x200 + + // OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0 + // Position of OUTLINK_STOP_CH field. + AHB_DMA_OUT_LINK_CH_OUTLINK_STOP_CH_Pos = 0x0 + // Bit mask of OUTLINK_STOP_CH field. + AHB_DMA_OUT_LINK_CH_OUTLINK_STOP_CH_Msk = 0x1 + // Bit OUTLINK_STOP_CH. + AHB_DMA_OUT_LINK_CH_OUTLINK_STOP_CH = 0x1 + // Position of OUTLINK_START_CH field. + AHB_DMA_OUT_LINK_CH_OUTLINK_START_CH_Pos = 0x1 + // Bit mask of OUTLINK_START_CH field. + AHB_DMA_OUT_LINK_CH_OUTLINK_START_CH_Msk = 0x2 + // Bit OUTLINK_START_CH. + AHB_DMA_OUT_LINK_CH_OUTLINK_START_CH = 0x2 + // Position of OUTLINK_RESTART_CH field. + AHB_DMA_OUT_LINK_CH_OUTLINK_RESTART_CH_Pos = 0x2 + // Bit mask of OUTLINK_RESTART_CH field. + AHB_DMA_OUT_LINK_CH_OUTLINK_RESTART_CH_Msk = 0x4 + // Bit OUTLINK_RESTART_CH. + AHB_DMA_OUT_LINK_CH_OUTLINK_RESTART_CH = 0x4 + // Position of OUTLINK_PARK_CH field. + AHB_DMA_OUT_LINK_CH_OUTLINK_PARK_CH_Pos = 0x3 + // Bit mask of OUTLINK_PARK_CH field. + AHB_DMA_OUT_LINK_CH_OUTLINK_PARK_CH_Msk = 0x8 + // Bit OUTLINK_PARK_CH. + AHB_DMA_OUT_LINK_CH_OUTLINK_PARK_CH = 0x8 + + // OUT_STATE_CH0: Transmit status of Tx channel 0 + // Position of OUTLINK_DSCR_ADDR_CH field. + AHB_DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_CH_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR_CH field. + AHB_DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_CH_Msk = 0x3ffff + // Position of OUT_DSCR_STATE_CH field. + AHB_DMA_OUT_STATE_CH_OUT_DSCR_STATE_CH_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE_CH field. + AHB_DMA_OUT_STATE_CH_OUT_DSCR_STATE_CH_Msk = 0xc0000 + // Position of OUT_STATE_CH field. + AHB_DMA_OUT_STATE_CH_OUT_STATE_CH_Pos = 0x14 + // Bit mask of OUT_STATE_CH field. + AHB_DMA_OUT_STATE_CH_OUT_STATE_CH_Msk = 0x700000 + + // OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0 + // Position of OUT_EOF_DES_ADDR_CH field. + AHB_DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_CH_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR_CH field. + AHB_DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_CH_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0 + // Position of OUT_EOF_BFR_DES_ADDR_CH field. + AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_CH_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR_CH field. + AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_CH_Msk = 0xffffffff + + // OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR_CH field. + AHB_DMA_OUT_DSCR_CH_OUTLINK_DSCR_CH_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_CH field. + AHB_DMA_OUT_DSCR_CH_OUTLINK_DSCR_CH_Msk = 0xffffffff + + // OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR_BF0_CH field. + AHB_DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_CH_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0_CH field. + AHB_DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_CH_Msk = 0xffffffff + + // OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR_BF1_CH field. + AHB_DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_CH_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1_CH field. + AHB_DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_CH_Msk = 0xffffffff + + // OUT_PRI_CH0: Priority register of Tx channel 0. + // Position of TX_PRI_CH field. + AHB_DMA_OUT_PRI_CH_TX_PRI_CH_Pos = 0x0 + // Bit mask of TX_PRI_CH field. + AHB_DMA_OUT_PRI_CH_TX_PRI_CH_Msk = 0xf + + // OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0 + // Position of PERI_OUT_SEL_CH field. + AHB_DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_CH_Pos = 0x0 + // Bit mask of PERI_OUT_SEL_CH field. + AHB_DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_CH_Msk = 0x3f + + // OUT_CONF0_CH0: Configure 0 register of Tx channel 1 + // Position of OUT_RST_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_RST_CH_Pos = 0x0 + // Bit mask of OUT_RST_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_RST_CH_Msk = 0x1 + // Bit OUT_RST_CH. + AHB_DMA_OUT_CONF0_CH_OUT_RST_CH = 0x1 + // Position of OUT_LOOP_TEST_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_LOOP_TEST_CH_Pos = 0x1 + // Bit mask of OUT_LOOP_TEST_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_LOOP_TEST_CH_Msk = 0x2 + // Bit OUT_LOOP_TEST_CH. + AHB_DMA_OUT_CONF0_CH_OUT_LOOP_TEST_CH = 0x2 + // Position of OUT_AUTO_WRBACK_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_CH_Pos = 0x2 + // Bit mask of OUT_AUTO_WRBACK_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_CH_Msk = 0x4 + // Bit OUT_AUTO_WRBACK_CH. + AHB_DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_CH = 0x4 + // Position of OUT_EOF_MODE_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_EOF_MODE_CH_Pos = 0x3 + // Bit mask of OUT_EOF_MODE_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_EOF_MODE_CH_Msk = 0x8 + // Bit OUT_EOF_MODE_CH. + AHB_DMA_OUT_CONF0_CH_OUT_EOF_MODE_CH = 0x8 + // Position of OUTDSCR_BURST_EN_CH field. + AHB_DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_CH_Pos = 0x4 + // Bit mask of OUTDSCR_BURST_EN_CH field. + AHB_DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_CH_Msk = 0x10 + // Bit OUTDSCR_BURST_EN_CH. + AHB_DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_CH = 0x10 + // Position of OUT_DATA_BURST_EN_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_CH_Pos = 0x5 + // Bit mask of OUT_DATA_BURST_EN_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_CH_Msk = 0x20 + // Bit OUT_DATA_BURST_EN_CH. + AHB_DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_CH = 0x20 + // Position of OUT_ETM_EN_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_ETM_EN_CH_Pos = 0x6 + // Bit mask of OUT_ETM_EN_CH field. + AHB_DMA_OUT_CONF0_CH_OUT_ETM_EN_CH_Msk = 0x40 + // Bit OUT_ETM_EN_CH. + AHB_DMA_OUT_CONF0_CH_OUT_ETM_EN_CH = 0x40 + + // OUT_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit) + // Position of OUT_CRC_INIT_DATA_CH field. + AHB_DMA_OUT_CRC_INIT_DATA_CH_OUT_CRC_INIT_DATA_CH_Pos = 0x0 + // Bit mask of OUT_CRC_INIT_DATA_CH field. + AHB_DMA_OUT_CRC_INIT_DATA_CH_OUT_CRC_INIT_DATA_CH_Msk = 0xffffffff + + // TX_CRC_WIDTH_CH0: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8> 1 +} +func (o *APB_SARADC_Type) SetCTRL_WORK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x18)|value<<3) +} +func (o *APB_SARADC_Type) GetCTRL_WORK_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x18) >> 3 +} +func (o *APB_SARADC_Type) SetCTRL_SAR_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *APB_SARADC_Type) GetCTRL_SAR_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *APB_SARADC_Type) SetCTRL_SAR_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *APB_SARADC_Type) GetCTRL_SAR_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *APB_SARADC_Type) SetCTRL_SAR_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x7f80)|value<<7) +} +func (o *APB_SARADC_Type) GetCTRL_SAR_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x7f80) >> 7 +} +func (o *APB_SARADC_Type) SetCTRL_SAR1_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x78000)|value<<15) +} +func (o *APB_SARADC_Type) GetCTRL_SAR1_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x78000) >> 15 +} +func (o *APB_SARADC_Type) SetCTRL_SAR2_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x780000)|value<<19) +} +func (o *APB_SARADC_Type) GetCTRL_SAR2_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x780000) >> 19 +} +func (o *APB_SARADC_Type) SetCTRL_SAR1_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *APB_SARADC_Type) GetCTRL_SAR1_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *APB_SARADC_Type) SetCTRL_SAR2_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *APB_SARADC_Type) GetCTRL_SAR2_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} +func (o *APB_SARADC_Type) SetCTRL_DATA_SAR_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetCTRL_DATA_SAR_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetCTRL_DATA_TO_I2S(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetCTRL_DATA_TO_I2S() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetCTRL_XPD_SAR_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x18000000)|value<<27) +} +func (o *APB_SARADC_Type) GetCTRL_XPD_SAR_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x18000000) >> 27 +} +func (o *APB_SARADC_Type) SetCTRL_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *APB_SARADC_Type) GetCTRL_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc0000000) >> 30 +} + +// APB_SARADC.CTRL2: DIG ADC common configuration +func (o *APB_SARADC_Type) SetCTRL2_MEAS_NUM_LIMIT(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL2_MEAS_NUM_LIMIT() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL2_MAX_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1fe)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL2_MAX_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1fe) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL2_SAR1_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *APB_SARADC_Type) GetCTRL2_SAR1_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x200) >> 9 +} +func (o *APB_SARADC_Type) SetCTRL2_SAR2_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *APB_SARADC_Type) GetCTRL2_SAR2_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x400) >> 10 +} +func (o *APB_SARADC_Type) SetCTRL2_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x800)|value<<11) +} +func (o *APB_SARADC_Type) GetCTRL2_TIMER_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x800) >> 11 +} +func (o *APB_SARADC_Type) SetCTRL2_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff000)|value<<12) +} +func (o *APB_SARADC_Type) GetCTRL2_TIMER_TARGET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff000) >> 12 +} +func (o *APB_SARADC_Type) SetCTRL2_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *APB_SARADC_Type) GetCTRL2_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1000000) >> 24 +} + +// APB_SARADC.FSM: digital adc control register +func (o *APB_SARADC_Type) SetFSM_SAMPLE_NUM(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0xff0000)|value<<16) +} +func (o *APB_SARADC_Type) GetFSM_SAMPLE_NUM() uint32 { + return (volatile.LoadUint32(&o.FSM.Reg) & 0xff0000) >> 16 +} +func (o *APB_SARADC_Type) SetFSM_SAMPLE_CYCLE(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0xff000000)|value<<24) +} +func (o *APB_SARADC_Type) GetFSM_SAMPLE_CYCLE() uint32 { + return (volatile.LoadUint32(&o.FSM.Reg) & 0xff000000) >> 24 +} + +// APB_SARADC.FSM_WAIT: configure saradc fsm internal parameter base on test +func (o *APB_SARADC_Type) SetFSM_WAIT_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetFSM_WAIT_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff00)|value<<8) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff00) >> 8 +} +func (o *APB_SARADC_Type) SetFSM_WAIT_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff0000)|value<<16) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff0000) >> 16 +} + +// APB_SARADC.SAR1_STATUS: digital adc1 status +func (o *APB_SARADC_Type) SetSAR1_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR1_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR1_STATUS.Reg) +} + +// APB_SARADC.SAR2_STATUS: digital adc2 status +func (o *APB_SARADC_Type) SetSAR2_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR2_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR2_STATUS.Reg) +} + +// APB_SARADC.SAR1_PATT_TAB1: item 0 ~ 3 for pattern table 1 (each item one byte) +func (o *APB_SARADC_Type) SetSAR1_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB1.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB1.Reg) +} + +// APB_SARADC.SAR1_PATT_TAB2: Item 4 ~ 7 for pattern table 1 (each item one byte) +func (o *APB_SARADC_Type) SetSAR1_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB2.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB2.Reg) +} + +// APB_SARADC.SAR1_PATT_TAB3: Item 8 ~ 11 for pattern table 1 (each item one byte) +func (o *APB_SARADC_Type) SetSAR1_PATT_TAB3(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB3.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_PATT_TAB3() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB3.Reg) +} + +// APB_SARADC.SAR1_PATT_TAB4: Item 12 ~ 15 for pattern table 1 (each item one byte) +func (o *APB_SARADC_Type) SetSAR1_PATT_TAB4(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB4.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_PATT_TAB4() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB4.Reg) +} + +// APB_SARADC.SAR2_PATT_TAB1: item 0 ~ 3 for pattern table 2 (each item one byte) +func (o *APB_SARADC_Type) SetSAR2_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB1.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB1.Reg) +} + +// APB_SARADC.SAR2_PATT_TAB2: Item 4 ~ 7 for pattern table 2 (each item one byte) +func (o *APB_SARADC_Type) SetSAR2_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB2.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB2.Reg) +} + +// APB_SARADC.SAR2_PATT_TAB3: Item 8 ~ 11 for pattern table 2 (each item one byte) +func (o *APB_SARADC_Type) SetSAR2_PATT_TAB3(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB3.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_PATT_TAB3() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB3.Reg) +} + +// APB_SARADC.SAR2_PATT_TAB4: Item 12 ~ 15 for pattern table 2 (each item one byte) +func (o *APB_SARADC_Type) SetSAR2_PATT_TAB4(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB4.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_PATT_TAB4() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB4.Reg) +} + +// APB_SARADC.ARB_CTRL: Configure the settings of DIG ADC2 arbiter +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x4) >> 2 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x8) >> 3 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x10) >> 4 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_GRANT_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_GRANT_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x20) >> 5 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc0)|value<<6) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc0) >> 6 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x300)|value<<8) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x300) >> 8 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc00)|value<<10) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc00) >> 10 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_FIX_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_FIX_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x1000) >> 12 +} + +// APB_SARADC.FILTER_CTRL: Configure the settings of DIG ADC2 filter +func (o *APB_SARADC_Type) SetFILTER_CTRL_ADC2_FILTER_RESET(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL.Reg, volatile.LoadUint32(&o.FILTER_CTRL.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL_ADC2_FILTER_RESET() uint32 { + return volatile.LoadUint32(&o.FILTER_CTRL.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL_ADC1_FILTER_RESET(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL.Reg, volatile.LoadUint32(&o.FILTER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL_ADC1_FILTER_RESET() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL_ADC2_FILTER_FACTOR(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL.Reg, volatile.LoadUint32(&o.FILTER_CTRL.Reg)&^(0x7f0000)|value<<16) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL_ADC2_FILTER_FACTOR() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL.Reg) & 0x7f0000) >> 16 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL_ADC1_FILTER_FACTOR(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL.Reg, volatile.LoadUint32(&o.FILTER_CTRL.Reg)&^(0x3f800000)|value<<23) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL_ADC1_FILTER_FACTOR() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL.Reg) & 0x3f800000) >> 23 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL_ADC2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL.Reg, volatile.LoadUint32(&o.FILTER_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL_ADC2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL_ADC1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL.Reg, volatile.LoadUint32(&o.FILTER_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL_ADC1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.FILTER_STATUS: Data status of DIG ADC2 filter +func (o *APB_SARADC_Type) SetFILTER_STATUS_ADC2_FILTER_DATA(value uint32) { + volatile.StoreUint32(&o.FILTER_STATUS.Reg, volatile.LoadUint32(&o.FILTER_STATUS.Reg)&^(0xffff)|value) +} +func (o *APB_SARADC_Type) GetFILTER_STATUS_ADC2_FILTER_DATA() uint32 { + return volatile.LoadUint32(&o.FILTER_STATUS.Reg) & 0xffff +} +func (o *APB_SARADC_Type) SetFILTER_STATUS_ADC1_FILTER_DATA(value uint32) { + volatile.StoreUint32(&o.FILTER_STATUS.Reg, volatile.LoadUint32(&o.FILTER_STATUS.Reg)&^(0xffff0000)|value<<16) +} +func (o *APB_SARADC_Type) GetFILTER_STATUS_ADC1_FILTER_DATA() uint32 { + return (volatile.LoadUint32(&o.FILTER_STATUS.Reg) & 0xffff0000) >> 16 +} + +// APB_SARADC.THRES_CTRL: Configure monitor threshold for DIG ADC2 +func (o *APB_SARADC_Type) SetTHRES_CTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_CLK_EN() uint32 { + return volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_ADC2_THRES_MODE(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_ADC2_THRES_MODE() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x4) >> 2 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_ADC1_THRES_MODE(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_ADC1_THRES_MODE() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x8) >> 3 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_ADC2_THRES(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x1fff0)|value<<4) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_ADC2_THRES() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x1fff0) >> 4 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_ADC1_THRES(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x3ffe0000)|value<<17) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_ADC1_THRES() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x3ffe0000) >> 17 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_ADC2_THRES_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_ADC2_THRES_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_ADC1_THRES_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_ADC1_THRES_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ENA: Enable DIG ADC interrupts +func (o *APB_SARADC_Type) SetINT_ENA_ADC2_THRES_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ENA_ADC2_THRES_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ENA_ADC1_THRES_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ENA_ADC1_THRES_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ENA_ADC2_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ENA_ADC2_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ENA_ADC1_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ENA_ADC1_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_RAW: DIG ADC interrupt raw bits +func (o *APB_SARADC_Type) SetINT_RAW_ADC2_THRES_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_RAW_ADC2_THRES_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_RAW_ADC1_THRES_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_RAW_ADC1_THRES_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_RAW_ADC2_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_RAW_ADC2_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_RAW_ADC1_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_RAW_ADC1_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ST: DIG ADC interrupt status +func (o *APB_SARADC_Type) SetINT_ST_ADC2_THRES_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ST_ADC2_THRES_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ST_ADC1_THRES_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ST_ADC1_THRES_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ST_ADC2_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ST_ADC2_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ST_ADC1_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ST_ADC1_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_CLR: Clear DIG ADC interrupts +func (o *APB_SARADC_Type) SetINT_CLR_ADC2_THRES_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_CLR_ADC2_THRES_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_CLR_ADC1_THRES_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_CLR_ADC1_THRES_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_CLR_ADC2_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_CLR_ADC2_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_CLR_ADC1_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_CLR_ADC1_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.DMA_CONF: Configure digital ADC DMA path +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0xffff)|value) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0xffff +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_RESET_FSM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_RESET_FSM() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_TRANS(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_TRANS() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.CLKM_CONF: Configure DIG ADC clock +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x3f00) >> 8 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xfc000) >> 14 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x600000)|value<<21) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x600000) >> 21 +} + +// APB_SARADC.APB_DAC_CTRL: Configure DAC settings +func (o *APB_SARADC_Type) SetAPB_DAC_CTRL_DAC_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.APB_DAC_CTRL.Reg, volatile.LoadUint32(&o.APB_DAC_CTRL.Reg)&^(0xfff)|value) +} +func (o *APB_SARADC_Type) GetAPB_DAC_CTRL_DAC_TIMER_TARGET() uint32 { + return volatile.LoadUint32(&o.APB_DAC_CTRL.Reg) & 0xfff +} +func (o *APB_SARADC_Type) SetAPB_DAC_CTRL_DAC_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.APB_DAC_CTRL.Reg, volatile.LoadUint32(&o.APB_DAC_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *APB_SARADC_Type) GetAPB_DAC_CTRL_DAC_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.APB_DAC_CTRL.Reg) & 0x1000) >> 12 +} +func (o *APB_SARADC_Type) SetAPB_DAC_CTRL_APB_DAC_ALTER_MODE(value uint32) { + volatile.StoreUint32(&o.APB_DAC_CTRL.Reg, volatile.LoadUint32(&o.APB_DAC_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *APB_SARADC_Type) GetAPB_DAC_CTRL_APB_DAC_ALTER_MODE() uint32 { + return (volatile.LoadUint32(&o.APB_DAC_CTRL.Reg) & 0x2000) >> 13 +} +func (o *APB_SARADC_Type) SetAPB_DAC_CTRL_APB_DAC_TRANS(value uint32) { + volatile.StoreUint32(&o.APB_DAC_CTRL.Reg, volatile.LoadUint32(&o.APB_DAC_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *APB_SARADC_Type) GetAPB_DAC_CTRL_APB_DAC_TRANS() uint32 { + return (volatile.LoadUint32(&o.APB_DAC_CTRL.Reg) & 0x4000) >> 14 +} +func (o *APB_SARADC_Type) SetAPB_DAC_CTRL_DAC_RESET_FIFO(value uint32) { + volatile.StoreUint32(&o.APB_DAC_CTRL.Reg, volatile.LoadUint32(&o.APB_DAC_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *APB_SARADC_Type) GetAPB_DAC_CTRL_DAC_RESET_FIFO() uint32 { + return (volatile.LoadUint32(&o.APB_DAC_CTRL.Reg) & 0x8000) >> 15 +} +func (o *APB_SARADC_Type) SetAPB_DAC_CTRL_APB_DAC_RST(value uint32) { + volatile.StoreUint32(&o.APB_DAC_CTRL.Reg, volatile.LoadUint32(&o.APB_DAC_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *APB_SARADC_Type) GetAPB_DAC_CTRL_APB_DAC_RST() uint32 { + return (volatile.LoadUint32(&o.APB_DAC_CTRL.Reg) & 0x10000) >> 16 +} + +// APB_SARADC.APB_CTRL_DATE: Version control register +func (o *APB_SARADC_Type) SetAPB_CTRL_DATE(value uint32) { + volatile.StoreUint32(&o.APB_CTRL_DATE.Reg, value) +} +func (o *APB_SARADC_Type) GetAPB_CTRL_DATE() uint32 { + return volatile.LoadUint32(&o.APB_CTRL_DATE.Reg) +} + +// BB Peripheral +type BB_Type struct { + _ [84]byte + BBPD_CTRL volatile.Register32 // 0x54 +} + +// BB.BBPD_CTRL: Baseband control register +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x1)|value) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x1 +} +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x2) >> 1 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x4) >> 2 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x8) >> 3 +} + +// DEDICATED_GPIO Peripheral +type DEDIC_GPIO_Type struct { + OUT_DRT volatile.Register32 // 0x0 + OUT_MSK volatile.Register32 // 0x4 + OUT_IDV volatile.Register32 // 0x8 + OUT_SCAN volatile.Register32 // 0xC + OUT_CPU volatile.Register32 // 0x10 + IN_DLY volatile.Register32 // 0x14 + IN_SCAN volatile.Register32 // 0x18 + INTR_RCGN volatile.Register32 // 0x1C + INTR_RAW volatile.Register32 // 0x20 + INTR_RLS volatile.Register32 // 0x24 + INTR_ST volatile.Register32 // 0x28 + INTR_CLR volatile.Register32 // 0x2C +} + +// DEDIC_GPIO.OUT_DRT: Dedicated GPIO directive output register +func (o *DEDIC_GPIO_Type) SetOUT_DRT_VLAUE(value uint32) { + volatile.StoreUint32(&o.OUT_DRT.Reg, volatile.LoadUint32(&o.OUT_DRT.Reg)&^(0xff)|value) +} +func (o *DEDIC_GPIO_Type) GetOUT_DRT_VLAUE() uint32 { + return volatile.LoadUint32(&o.OUT_DRT.Reg) & 0xff +} + +// DEDIC_GPIO.OUT_MSK: Dedicated GPIO mask output register +func (o *DEDIC_GPIO_Type) SetOUT_MSK_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.OUT_MSK.Reg, volatile.LoadUint32(&o.OUT_MSK.Reg)&^(0xff)|value) +} +func (o *DEDIC_GPIO_Type) GetOUT_MSK_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.OUT_MSK.Reg) & 0xff +} +func (o *DEDIC_GPIO_Type) SetOUT_MSK(value uint32) { + volatile.StoreUint32(&o.OUT_MSK.Reg, volatile.LoadUint32(&o.OUT_MSK.Reg)&^(0xff00)|value<<8) +} +func (o *DEDIC_GPIO_Type) GetOUT_MSK() uint32 { + return (volatile.LoadUint32(&o.OUT_MSK.Reg) & 0xff00) >> 8 +} + +// DEDIC_GPIO.OUT_IDV: Dedicated GPIO individual output register +func (o *DEDIC_GPIO_Type) SetOUT_IDV_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_IDV.Reg, volatile.LoadUint32(&o.OUT_IDV.Reg)&^(0x3)|value) +} +func (o *DEDIC_GPIO_Type) GetOUT_IDV_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_IDV.Reg) & 0x3 +} +func (o *DEDIC_GPIO_Type) SetOUT_IDV_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_IDV.Reg, volatile.LoadUint32(&o.OUT_IDV.Reg)&^(0xc)|value<<2) +} +func (o *DEDIC_GPIO_Type) GetOUT_IDV_CH1() uint32 { + return (volatile.LoadUint32(&o.OUT_IDV.Reg) & 0xc) >> 2 +} +func (o *DEDIC_GPIO_Type) SetOUT_IDV_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_IDV.Reg, volatile.LoadUint32(&o.OUT_IDV.Reg)&^(0x30)|value<<4) +} +func (o *DEDIC_GPIO_Type) GetOUT_IDV_CH2() uint32 { + return (volatile.LoadUint32(&o.OUT_IDV.Reg) & 0x30) >> 4 +} +func (o *DEDIC_GPIO_Type) SetOUT_IDV_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_IDV.Reg, volatile.LoadUint32(&o.OUT_IDV.Reg)&^(0xc0)|value<<6) +} +func (o *DEDIC_GPIO_Type) GetOUT_IDV_CH3() uint32 { + return (volatile.LoadUint32(&o.OUT_IDV.Reg) & 0xc0) >> 6 +} +func (o *DEDIC_GPIO_Type) SetOUT_IDV_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_IDV.Reg, volatile.LoadUint32(&o.OUT_IDV.Reg)&^(0x300)|value<<8) +} +func (o *DEDIC_GPIO_Type) GetOUT_IDV_CH4() uint32 { + return (volatile.LoadUint32(&o.OUT_IDV.Reg) & 0x300) >> 8 +} +func (o *DEDIC_GPIO_Type) SetOUT_IDV_CH5(value uint32) { + volatile.StoreUint32(&o.OUT_IDV.Reg, volatile.LoadUint32(&o.OUT_IDV.Reg)&^(0xc00)|value<<10) +} +func (o *DEDIC_GPIO_Type) GetOUT_IDV_CH5() uint32 { + return (volatile.LoadUint32(&o.OUT_IDV.Reg) & 0xc00) >> 10 +} +func (o *DEDIC_GPIO_Type) SetOUT_IDV_CH6(value uint32) { + volatile.StoreUint32(&o.OUT_IDV.Reg, volatile.LoadUint32(&o.OUT_IDV.Reg)&^(0x3000)|value<<12) +} +func (o *DEDIC_GPIO_Type) GetOUT_IDV_CH6() uint32 { + return (volatile.LoadUint32(&o.OUT_IDV.Reg) & 0x3000) >> 12 +} +func (o *DEDIC_GPIO_Type) SetOUT_IDV_CH7(value uint32) { + volatile.StoreUint32(&o.OUT_IDV.Reg, volatile.LoadUint32(&o.OUT_IDV.Reg)&^(0xc000)|value<<14) +} +func (o *DEDIC_GPIO_Type) GetOUT_IDV_CH7() uint32 { + return (volatile.LoadUint32(&o.OUT_IDV.Reg) & 0xc000) >> 14 +} + +// DEDIC_GPIO.OUT_SCAN: Dedicated GPIO output status register +func (o *DEDIC_GPIO_Type) SetOUT_SCAN_OUT_STATUS(value uint32) { + volatile.StoreUint32(&o.OUT_SCAN.Reg, volatile.LoadUint32(&o.OUT_SCAN.Reg)&^(0xff)|value) +} +func (o *DEDIC_GPIO_Type) GetOUT_SCAN_OUT_STATUS() uint32 { + return volatile.LoadUint32(&o.OUT_SCAN.Reg) & 0xff +} + +// DEDIC_GPIO.OUT_CPU: Dedicated GPIO output mode selection register +func (o *DEDIC_GPIO_Type) SetOUT_CPU_SEL0(value uint32) { + volatile.StoreUint32(&o.OUT_CPU.Reg, volatile.LoadUint32(&o.OUT_CPU.Reg)&^(0x1)|value) +} +func (o *DEDIC_GPIO_Type) GetOUT_CPU_SEL0() uint32 { + return volatile.LoadUint32(&o.OUT_CPU.Reg) & 0x1 +} +func (o *DEDIC_GPIO_Type) SetOUT_CPU_SEL1(value uint32) { + volatile.StoreUint32(&o.OUT_CPU.Reg, volatile.LoadUint32(&o.OUT_CPU.Reg)&^(0x2)|value<<1) +} +func (o *DEDIC_GPIO_Type) GetOUT_CPU_SEL1() uint32 { + return (volatile.LoadUint32(&o.OUT_CPU.Reg) & 0x2) >> 1 +} +func (o *DEDIC_GPIO_Type) SetOUT_CPU_SEL2(value uint32) { + volatile.StoreUint32(&o.OUT_CPU.Reg, volatile.LoadUint32(&o.OUT_CPU.Reg)&^(0x4)|value<<2) +} +func (o *DEDIC_GPIO_Type) GetOUT_CPU_SEL2() uint32 { + return (volatile.LoadUint32(&o.OUT_CPU.Reg) & 0x4) >> 2 +} +func (o *DEDIC_GPIO_Type) SetOUT_CPU_SEL3(value uint32) { + volatile.StoreUint32(&o.OUT_CPU.Reg, volatile.LoadUint32(&o.OUT_CPU.Reg)&^(0x8)|value<<3) +} +func (o *DEDIC_GPIO_Type) GetOUT_CPU_SEL3() uint32 { + return (volatile.LoadUint32(&o.OUT_CPU.Reg) & 0x8) >> 3 +} +func (o *DEDIC_GPIO_Type) SetOUT_CPU_SEL4(value uint32) { + volatile.StoreUint32(&o.OUT_CPU.Reg, volatile.LoadUint32(&o.OUT_CPU.Reg)&^(0x10)|value<<4) +} +func (o *DEDIC_GPIO_Type) GetOUT_CPU_SEL4() uint32 { + return (volatile.LoadUint32(&o.OUT_CPU.Reg) & 0x10) >> 4 +} +func (o *DEDIC_GPIO_Type) SetOUT_CPU_SEL5(value uint32) { + volatile.StoreUint32(&o.OUT_CPU.Reg, volatile.LoadUint32(&o.OUT_CPU.Reg)&^(0x20)|value<<5) +} +func (o *DEDIC_GPIO_Type) GetOUT_CPU_SEL5() uint32 { + return (volatile.LoadUint32(&o.OUT_CPU.Reg) & 0x20) >> 5 +} +func (o *DEDIC_GPIO_Type) SetOUT_CPU_SEL6(value uint32) { + volatile.StoreUint32(&o.OUT_CPU.Reg, volatile.LoadUint32(&o.OUT_CPU.Reg)&^(0x40)|value<<6) +} +func (o *DEDIC_GPIO_Type) GetOUT_CPU_SEL6() uint32 { + return (volatile.LoadUint32(&o.OUT_CPU.Reg) & 0x40) >> 6 +} +func (o *DEDIC_GPIO_Type) SetOUT_CPU_SEL7(value uint32) { + volatile.StoreUint32(&o.OUT_CPU.Reg, volatile.LoadUint32(&o.OUT_CPU.Reg)&^(0x80)|value<<7) +} +func (o *DEDIC_GPIO_Type) GetOUT_CPU_SEL7() uint32 { + return (volatile.LoadUint32(&o.OUT_CPU.Reg) & 0x80) >> 7 +} + +// DEDIC_GPIO.IN_DLY: Dedicated GPIO input delay configuration register +func (o *DEDIC_GPIO_Type) SetIN_DLY_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DLY.Reg, volatile.LoadUint32(&o.IN_DLY.Reg)&^(0x3)|value) +} +func (o *DEDIC_GPIO_Type) GetIN_DLY_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DLY.Reg) & 0x3 +} +func (o *DEDIC_GPIO_Type) SetIN_DLY_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DLY.Reg, volatile.LoadUint32(&o.IN_DLY.Reg)&^(0xc)|value<<2) +} +func (o *DEDIC_GPIO_Type) GetIN_DLY_CH1() uint32 { + return (volatile.LoadUint32(&o.IN_DLY.Reg) & 0xc) >> 2 +} +func (o *DEDIC_GPIO_Type) SetIN_DLY_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DLY.Reg, volatile.LoadUint32(&o.IN_DLY.Reg)&^(0x30)|value<<4) +} +func (o *DEDIC_GPIO_Type) GetIN_DLY_CH2() uint32 { + return (volatile.LoadUint32(&o.IN_DLY.Reg) & 0x30) >> 4 +} +func (o *DEDIC_GPIO_Type) SetIN_DLY_CH3(value uint32) { + volatile.StoreUint32(&o.IN_DLY.Reg, volatile.LoadUint32(&o.IN_DLY.Reg)&^(0xc0)|value<<6) +} +func (o *DEDIC_GPIO_Type) GetIN_DLY_CH3() uint32 { + return (volatile.LoadUint32(&o.IN_DLY.Reg) & 0xc0) >> 6 +} +func (o *DEDIC_GPIO_Type) SetIN_DLY_CH4(value uint32) { + volatile.StoreUint32(&o.IN_DLY.Reg, volatile.LoadUint32(&o.IN_DLY.Reg)&^(0x300)|value<<8) +} +func (o *DEDIC_GPIO_Type) GetIN_DLY_CH4() uint32 { + return (volatile.LoadUint32(&o.IN_DLY.Reg) & 0x300) >> 8 +} +func (o *DEDIC_GPIO_Type) SetIN_DLY_CH5(value uint32) { + volatile.StoreUint32(&o.IN_DLY.Reg, volatile.LoadUint32(&o.IN_DLY.Reg)&^(0xc00)|value<<10) +} +func (o *DEDIC_GPIO_Type) GetIN_DLY_CH5() uint32 { + return (volatile.LoadUint32(&o.IN_DLY.Reg) & 0xc00) >> 10 +} +func (o *DEDIC_GPIO_Type) SetIN_DLY_CH6(value uint32) { + volatile.StoreUint32(&o.IN_DLY.Reg, volatile.LoadUint32(&o.IN_DLY.Reg)&^(0x3000)|value<<12) +} +func (o *DEDIC_GPIO_Type) GetIN_DLY_CH6() uint32 { + return (volatile.LoadUint32(&o.IN_DLY.Reg) & 0x3000) >> 12 +} +func (o *DEDIC_GPIO_Type) SetIN_DLY_CH7(value uint32) { + volatile.StoreUint32(&o.IN_DLY.Reg, volatile.LoadUint32(&o.IN_DLY.Reg)&^(0xc000)|value<<14) +} +func (o *DEDIC_GPIO_Type) GetIN_DLY_CH7() uint32 { + return (volatile.LoadUint32(&o.IN_DLY.Reg) & 0xc000) >> 14 +} + +// DEDIC_GPIO.IN_SCAN: Dedicated GPIO input status register +func (o *DEDIC_GPIO_Type) SetIN_SCAN_IN_STATUS(value uint32) { + volatile.StoreUint32(&o.IN_SCAN.Reg, volatile.LoadUint32(&o.IN_SCAN.Reg)&^(0xff)|value) +} +func (o *DEDIC_GPIO_Type) GetIN_SCAN_IN_STATUS() uint32 { + return volatile.LoadUint32(&o.IN_SCAN.Reg) & 0xff +} + +// DEDIC_GPIO.INTR_RCGN: Dedicated GPIO interrupts generation mode register +func (o *DEDIC_GPIO_Type) SetINTR_RCGN_INTR_MODE_CH0(value uint32) { + volatile.StoreUint32(&o.INTR_RCGN.Reg, volatile.LoadUint32(&o.INTR_RCGN.Reg)&^(0x7)|value) +} +func (o *DEDIC_GPIO_Type) GetINTR_RCGN_INTR_MODE_CH0() uint32 { + return volatile.LoadUint32(&o.INTR_RCGN.Reg) & 0x7 +} +func (o *DEDIC_GPIO_Type) SetINTR_RCGN_INTR_MODE_CH1(value uint32) { + volatile.StoreUint32(&o.INTR_RCGN.Reg, volatile.LoadUint32(&o.INTR_RCGN.Reg)&^(0x38)|value<<3) +} +func (o *DEDIC_GPIO_Type) GetINTR_RCGN_INTR_MODE_CH1() uint32 { + return (volatile.LoadUint32(&o.INTR_RCGN.Reg) & 0x38) >> 3 +} +func (o *DEDIC_GPIO_Type) SetINTR_RCGN_INTR_MODE_CH2(value uint32) { + volatile.StoreUint32(&o.INTR_RCGN.Reg, volatile.LoadUint32(&o.INTR_RCGN.Reg)&^(0x1c0)|value<<6) +} +func (o *DEDIC_GPIO_Type) GetINTR_RCGN_INTR_MODE_CH2() uint32 { + return (volatile.LoadUint32(&o.INTR_RCGN.Reg) & 0x1c0) >> 6 +} +func (o *DEDIC_GPIO_Type) SetINTR_RCGN_INTR_MODE_CH3(value uint32) { + volatile.StoreUint32(&o.INTR_RCGN.Reg, volatile.LoadUint32(&o.INTR_RCGN.Reg)&^(0xe00)|value<<9) +} +func (o *DEDIC_GPIO_Type) GetINTR_RCGN_INTR_MODE_CH3() uint32 { + return (volatile.LoadUint32(&o.INTR_RCGN.Reg) & 0xe00) >> 9 +} +func (o *DEDIC_GPIO_Type) SetINTR_RCGN_INTR_MODE_CH4(value uint32) { + volatile.StoreUint32(&o.INTR_RCGN.Reg, volatile.LoadUint32(&o.INTR_RCGN.Reg)&^(0x7000)|value<<12) +} +func (o *DEDIC_GPIO_Type) GetINTR_RCGN_INTR_MODE_CH4() uint32 { + return (volatile.LoadUint32(&o.INTR_RCGN.Reg) & 0x7000) >> 12 +} +func (o *DEDIC_GPIO_Type) SetINTR_RCGN_INTR_MODE_CH5(value uint32) { + volatile.StoreUint32(&o.INTR_RCGN.Reg, volatile.LoadUint32(&o.INTR_RCGN.Reg)&^(0x38000)|value<<15) +} +func (o *DEDIC_GPIO_Type) GetINTR_RCGN_INTR_MODE_CH5() uint32 { + return (volatile.LoadUint32(&o.INTR_RCGN.Reg) & 0x38000) >> 15 +} +func (o *DEDIC_GPIO_Type) SetINTR_RCGN_INTR_MODE_CH6(value uint32) { + volatile.StoreUint32(&o.INTR_RCGN.Reg, volatile.LoadUint32(&o.INTR_RCGN.Reg)&^(0x1c0000)|value<<18) +} +func (o *DEDIC_GPIO_Type) GetINTR_RCGN_INTR_MODE_CH6() uint32 { + return (volatile.LoadUint32(&o.INTR_RCGN.Reg) & 0x1c0000) >> 18 +} +func (o *DEDIC_GPIO_Type) SetINTR_RCGN_INTR_MODE_CH7(value uint32) { + volatile.StoreUint32(&o.INTR_RCGN.Reg, volatile.LoadUint32(&o.INTR_RCGN.Reg)&^(0xe00000)|value<<21) +} +func (o *DEDIC_GPIO_Type) GetINTR_RCGN_INTR_MODE_CH7() uint32 { + return (volatile.LoadUint32(&o.INTR_RCGN.Reg) & 0xe00000) >> 21 +} + +// DEDIC_GPIO.INTR_RAW: Raw interrupt status +func (o *DEDIC_GPIO_Type) SetINTR_RAW_GPIO0(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x1)|value) +} +func (o *DEDIC_GPIO_Type) GetINTR_RAW_GPIO0() uint32 { + return volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x1 +} +func (o *DEDIC_GPIO_Type) SetINTR_RAW_GPIO1(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *DEDIC_GPIO_Type) GetINTR_RAW_GPIO1() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x2) >> 1 +} +func (o *DEDIC_GPIO_Type) SetINTR_RAW_GPIO2(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x4)|value<<2) +} +func (o *DEDIC_GPIO_Type) GetINTR_RAW_GPIO2() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x4) >> 2 +} +func (o *DEDIC_GPIO_Type) SetINTR_RAW_GPIO3(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x8)|value<<3) +} +func (o *DEDIC_GPIO_Type) GetINTR_RAW_GPIO3() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x8) >> 3 +} +func (o *DEDIC_GPIO_Type) SetINTR_RAW_GPIO4(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x10)|value<<4) +} +func (o *DEDIC_GPIO_Type) GetINTR_RAW_GPIO4() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x10) >> 4 +} +func (o *DEDIC_GPIO_Type) SetINTR_RAW_GPIO5(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x20)|value<<5) +} +func (o *DEDIC_GPIO_Type) GetINTR_RAW_GPIO5() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x20) >> 5 +} +func (o *DEDIC_GPIO_Type) SetINTR_RAW_GPIO6(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x40)|value<<6) +} +func (o *DEDIC_GPIO_Type) GetINTR_RAW_GPIO6() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x40) >> 6 +} +func (o *DEDIC_GPIO_Type) SetINTR_RAW_GPIO7(value uint32) { + volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x80)|value<<7) +} +func (o *DEDIC_GPIO_Type) GetINTR_RAW_GPIO7() uint32 { + return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x80) >> 7 +} + +// DEDIC_GPIO.INTR_RLS: Interrupt enable bits +func (o *DEDIC_GPIO_Type) SetINTR_RLS_GPIO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_RLS.Reg, volatile.LoadUint32(&o.INTR_RLS.Reg)&^(0x1)|value) +} +func (o *DEDIC_GPIO_Type) GetINTR_RLS_GPIO0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INTR_RLS.Reg) & 0x1 +} +func (o *DEDIC_GPIO_Type) SetINTR_RLS_GPIO1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_RLS.Reg, volatile.LoadUint32(&o.INTR_RLS.Reg)&^(0x2)|value<<1) +} +func (o *DEDIC_GPIO_Type) GetINTR_RLS_GPIO1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_RLS.Reg) & 0x2) >> 1 +} +func (o *DEDIC_GPIO_Type) SetINTR_RLS_GPIO2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_RLS.Reg, volatile.LoadUint32(&o.INTR_RLS.Reg)&^(0x4)|value<<2) +} +func (o *DEDIC_GPIO_Type) GetINTR_RLS_GPIO2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_RLS.Reg) & 0x4) >> 2 +} +func (o *DEDIC_GPIO_Type) SetINTR_RLS_GPIO3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_RLS.Reg, volatile.LoadUint32(&o.INTR_RLS.Reg)&^(0x8)|value<<3) +} +func (o *DEDIC_GPIO_Type) GetINTR_RLS_GPIO3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_RLS.Reg) & 0x8) >> 3 +} +func (o *DEDIC_GPIO_Type) SetINTR_RLS_GPIO4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_RLS.Reg, volatile.LoadUint32(&o.INTR_RLS.Reg)&^(0x10)|value<<4) +} +func (o *DEDIC_GPIO_Type) GetINTR_RLS_GPIO4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_RLS.Reg) & 0x10) >> 4 +} +func (o *DEDIC_GPIO_Type) SetINTR_RLS_GPIO5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_RLS.Reg, volatile.LoadUint32(&o.INTR_RLS.Reg)&^(0x20)|value<<5) +} +func (o *DEDIC_GPIO_Type) GetINTR_RLS_GPIO5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_RLS.Reg) & 0x20) >> 5 +} +func (o *DEDIC_GPIO_Type) SetINTR_RLS_GPIO6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_RLS.Reg, volatile.LoadUint32(&o.INTR_RLS.Reg)&^(0x40)|value<<6) +} +func (o *DEDIC_GPIO_Type) GetINTR_RLS_GPIO6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_RLS.Reg) & 0x40) >> 6 +} +func (o *DEDIC_GPIO_Type) SetINTR_RLS_GPIO7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INTR_RLS.Reg, volatile.LoadUint32(&o.INTR_RLS.Reg)&^(0x80)|value<<7) +} +func (o *DEDIC_GPIO_Type) GetINTR_RLS_GPIO7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INTR_RLS.Reg) & 0x80) >> 7 +} + +// DEDIC_GPIO.INTR_ST: Masked interrupt status +func (o *DEDIC_GPIO_Type) SetINTR_ST_GPIO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTR_ST.Reg, volatile.LoadUint32(&o.INTR_ST.Reg)&^(0x1)|value) +} +func (o *DEDIC_GPIO_Type) GetINTR_ST_GPIO0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INTR_ST.Reg) & 0x1 +} +func (o *DEDIC_GPIO_Type) SetINTR_ST_GPIO1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTR_ST.Reg, volatile.LoadUint32(&o.INTR_ST.Reg)&^(0x2)|value<<1) +} +func (o *DEDIC_GPIO_Type) GetINTR_ST_GPIO1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTR_ST.Reg) & 0x2) >> 1 +} +func (o *DEDIC_GPIO_Type) SetINTR_ST_GPIO2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTR_ST.Reg, volatile.LoadUint32(&o.INTR_ST.Reg)&^(0x4)|value<<2) +} +func (o *DEDIC_GPIO_Type) GetINTR_ST_GPIO2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTR_ST.Reg) & 0x4) >> 2 +} +func (o *DEDIC_GPIO_Type) SetINTR_ST_GPIO3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTR_ST.Reg, volatile.LoadUint32(&o.INTR_ST.Reg)&^(0x8)|value<<3) +} +func (o *DEDIC_GPIO_Type) GetINTR_ST_GPIO3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTR_ST.Reg) & 0x8) >> 3 +} +func (o *DEDIC_GPIO_Type) SetINTR_ST_GPIO4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTR_ST.Reg, volatile.LoadUint32(&o.INTR_ST.Reg)&^(0x10)|value<<4) +} +func (o *DEDIC_GPIO_Type) GetINTR_ST_GPIO4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTR_ST.Reg) & 0x10) >> 4 +} +func (o *DEDIC_GPIO_Type) SetINTR_ST_GPIO5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTR_ST.Reg, volatile.LoadUint32(&o.INTR_ST.Reg)&^(0x20)|value<<5) +} +func (o *DEDIC_GPIO_Type) GetINTR_ST_GPIO5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTR_ST.Reg) & 0x20) >> 5 +} +func (o *DEDIC_GPIO_Type) SetINTR_ST_GPIO6_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTR_ST.Reg, volatile.LoadUint32(&o.INTR_ST.Reg)&^(0x40)|value<<6) +} +func (o *DEDIC_GPIO_Type) GetINTR_ST_GPIO6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTR_ST.Reg) & 0x40) >> 6 +} +func (o *DEDIC_GPIO_Type) SetINTR_ST_GPIO7_INT_ST(value uint32) { + volatile.StoreUint32(&o.INTR_ST.Reg, volatile.LoadUint32(&o.INTR_ST.Reg)&^(0x80)|value<<7) +} +func (o *DEDIC_GPIO_Type) GetINTR_ST_GPIO7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INTR_ST.Reg) & 0x80) >> 7 +} + +// DEDIC_GPIO.INTR_CLR: Interrupt clear bits +func (o *DEDIC_GPIO_Type) SetINTR_CLR_GPIO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x1)|value) +} +func (o *DEDIC_GPIO_Type) GetINTR_CLR_GPIO0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x1 +} +func (o *DEDIC_GPIO_Type) SetINTR_CLR_GPIO1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *DEDIC_GPIO_Type) GetINTR_CLR_GPIO1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x2) >> 1 +} +func (o *DEDIC_GPIO_Type) SetINTR_CLR_GPIO2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x4)|value<<2) +} +func (o *DEDIC_GPIO_Type) GetINTR_CLR_GPIO2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x4) >> 2 +} +func (o *DEDIC_GPIO_Type) SetINTR_CLR_GPIO3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x8)|value<<3) +} +func (o *DEDIC_GPIO_Type) GetINTR_CLR_GPIO3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x8) >> 3 +} +func (o *DEDIC_GPIO_Type) SetINTR_CLR_GPIO4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x10)|value<<4) +} +func (o *DEDIC_GPIO_Type) GetINTR_CLR_GPIO4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x10) >> 4 +} +func (o *DEDIC_GPIO_Type) SetINTR_CLR_GPIO5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x20)|value<<5) +} +func (o *DEDIC_GPIO_Type) GetINTR_CLR_GPIO5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x20) >> 5 +} +func (o *DEDIC_GPIO_Type) SetINTR_CLR_GPIO6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x40)|value<<6) +} +func (o *DEDIC_GPIO_Type) GetINTR_CLR_GPIO6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x40) >> 6 +} +func (o *DEDIC_GPIO_Type) SetINTR_CLR_GPIO7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x80)|value<<7) +} +func (o *DEDIC_GPIO_Type) GetINTR_CLR_GPIO7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x80) >> 7 +} + +// Digital Signature +type DS_Type struct { + C_MEM [1584]volatile.Register8 // 0x0 + IV_0 volatile.Register32 // 0x630 + IV_1 volatile.Register32 // 0x634 + IV_2 volatile.Register32 // 0x638 + IV_3 volatile.Register32 // 0x63C + _ [448]byte + X_MEM [512]volatile.Register8 // 0x800 + Z_MEM [512]volatile.Register8 // 0xA00 + _ [512]byte + SET_START volatile.Register32 // 0xE00 + SET_ME volatile.Register32 // 0xE04 + SET_FINISH volatile.Register32 // 0xE08 + QUERY_BUSY volatile.Register32 // 0xE0C + QUERY_KEY_WRONG volatile.Register32 // 0xE10 + QUERY_CHECK volatile.Register32 // 0xE14 + _ [8]byte + DATE volatile.Register32 // 0xE20 +} + +// DS.IV_0: IV block data. +func (o *DS_Type) SetIV_0(value uint32) { + volatile.StoreUint32(&o.IV_0.Reg, value) +} +func (o *DS_Type) GetIV_0() uint32 { + return volatile.LoadUint32(&o.IV_0.Reg) +} + +// DS.IV_1: IV block data. +func (o *DS_Type) SetIV_1(value uint32) { + volatile.StoreUint32(&o.IV_1.Reg, value) +} +func (o *DS_Type) GetIV_1() uint32 { + return volatile.LoadUint32(&o.IV_1.Reg) +} + +// DS.IV_2: IV block data. +func (o *DS_Type) SetIV_2(value uint32) { + volatile.StoreUint32(&o.IV_2.Reg, value) +} +func (o *DS_Type) GetIV_2() uint32 { + return volatile.LoadUint32(&o.IV_2.Reg) +} + +// DS.IV_3: IV block data. +func (o *DS_Type) SetIV_3(value uint32) { + volatile.StoreUint32(&o.IV_3.Reg, value) +} +func (o *DS_Type) GetIV_3() uint32 { + return volatile.LoadUint32(&o.IV_3.Reg) +} + +// DS.SET_START: Activates the DS peripheral +func (o *DS_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// DS.SET_ME: Starts DS operation +func (o *DS_Type) SetSET_ME(value uint32) { + volatile.StoreUint32(&o.SET_ME.Reg, volatile.LoadUint32(&o.SET_ME.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_ME() uint32 { + return volatile.LoadUint32(&o.SET_ME.Reg) & 0x1 +} + +// DS.SET_FINISH: Ends DS operation +func (o *DS_Type) SetSET_FINISH(value uint32) { + volatile.StoreUint32(&o.SET_FINISH.Reg, volatile.LoadUint32(&o.SET_FINISH.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_FINISH() uint32 { + return volatile.LoadUint32(&o.SET_FINISH.Reg) & 0x1 +} + +// DS.QUERY_BUSY: Status of the DS +func (o *DS_Type) SetQUERY_BUSY(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_BUSY() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// DS.QUERY_KEY_WRONG: Checks the reason why DS_KEY is not ready. +func (o *DS_Type) SetQUERY_KEY_WRONG(value uint32) { + volatile.StoreUint32(&o.QUERY_KEY_WRONG.Reg, volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg)&^(0xf)|value) +} +func (o *DS_Type) GetQUERY_KEY_WRONG() uint32 { + return volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg) & 0xf +} + +// DS.QUERY_CHECK: Queries DS check result +func (o *DS_Type) SetQUERY_CHECK_MD_ERROR(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_CHECK_MD_ERROR() uint32 { + return volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x1 +} +func (o *DS_Type) SetQUERY_CHECK_PADDING_BAD(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x2)|value<<1) +} +func (o *DS_Type) GetQUERY_CHECK_PADDING_BAD() uint32 { + return (volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x2) >> 1 +} + +// DS.DATE: Version control register +func (o *DS_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *DS_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// eFuse Controller +type EFUSE_Type struct { + PGM_DATA0 volatile.Register32 // 0x0 + PGM_DATA1 volatile.Register32 // 0x4 + PGM_DATA2 volatile.Register32 // 0x8 + PGM_DATA3 volatile.Register32 // 0xC + PGM_DATA4 volatile.Register32 // 0x10 + PGM_DATA5 volatile.Register32 // 0x14 + PGM_DATA6 volatile.Register32 // 0x18 + PGM_DATA7 volatile.Register32 // 0x1C + PGM_CHECK_VALUE0 volatile.Register32 // 0x20 + PGM_CHECK_VALUE1 volatile.Register32 // 0x24 + PGM_CHECK_VALUE2 volatile.Register32 // 0x28 + RD_WR_DIS volatile.Register32 // 0x2C + RD_REPEAT_DATA0 volatile.Register32 // 0x30 + RD_REPEAT_DATA1 volatile.Register32 // 0x34 + RD_REPEAT_DATA2 volatile.Register32 // 0x38 + RD_REPEAT_DATA3 volatile.Register32 // 0x3C + RD_REPEAT_DATA4 volatile.Register32 // 0x40 + RD_MAC_SPI_SYS_0 volatile.Register32 // 0x44 + RD_MAC_SPI_SYS_1 volatile.Register32 // 0x48 + RD_MAC_SPI_SYS_2 volatile.Register32 // 0x4C + RD_MAC_SPI_SYS_3 volatile.Register32 // 0x50 + RD_MAC_SPI_SYS_4 volatile.Register32 // 0x54 + RD_MAC_SPI_SYS_5 volatile.Register32 // 0x58 + RD_SYS_DATA_PART1_0 volatile.Register32 // 0x5C + RD_SYS_DATA_PART1_1 volatile.Register32 // 0x60 + RD_SYS_DATA_PART1_2 volatile.Register32 // 0x64 + RD_SYS_DATA_PART1_3 volatile.Register32 // 0x68 + RD_SYS_DATA_PART1_4 volatile.Register32 // 0x6C + RD_SYS_DATA_PART1_5 volatile.Register32 // 0x70 + RD_SYS_DATA_PART1_6 volatile.Register32 // 0x74 + RD_SYS_DATA_PART1_7 volatile.Register32 // 0x78 + RD_USR_DATA0 volatile.Register32 // 0x7C + RD_USR_DATA1 volatile.Register32 // 0x80 + RD_USR_DATA2 volatile.Register32 // 0x84 + RD_USR_DATA3 volatile.Register32 // 0x88 + RD_USR_DATA4 volatile.Register32 // 0x8C + RD_USR_DATA5 volatile.Register32 // 0x90 + RD_USR_DATA6 volatile.Register32 // 0x94 + RD_USR_DATA7 volatile.Register32 // 0x98 + RD_KEY0_DATA0 volatile.Register32 // 0x9C + RD_KEY0_DATA1 volatile.Register32 // 0xA0 + RD_KEY0_DATA2 volatile.Register32 // 0xA4 + RD_KEY0_DATA3 volatile.Register32 // 0xA8 + RD_KEY0_DATA4 volatile.Register32 // 0xAC + RD_KEY0_DATA5 volatile.Register32 // 0xB0 + RD_KEY0_DATA6 volatile.Register32 // 0xB4 + RD_KEY0_DATA7 volatile.Register32 // 0xB8 + RD_KEY1_DATA0 volatile.Register32 // 0xBC + RD_KEY1_DATA1 volatile.Register32 // 0xC0 + RD_KEY1_DATA2 volatile.Register32 // 0xC4 + RD_KEY1_DATA3 volatile.Register32 // 0xC8 + RD_KEY1_DATA4 volatile.Register32 // 0xCC + RD_KEY1_DATA5 volatile.Register32 // 0xD0 + RD_KEY1_DATA6 volatile.Register32 // 0xD4 + RD_KEY1_DATA7 volatile.Register32 // 0xD8 + RD_KEY2_DATA0 volatile.Register32 // 0xDC + RD_KEY2_DATA1 volatile.Register32 // 0xE0 + RD_KEY2_DATA2 volatile.Register32 // 0xE4 + RD_KEY2_DATA3 volatile.Register32 // 0xE8 + RD_KEY2_DATA4 volatile.Register32 // 0xEC + RD_KEY2_DATA5 volatile.Register32 // 0xF0 + RD_KEY2_DATA6 volatile.Register32 // 0xF4 + RD_KEY2_DATA7 volatile.Register32 // 0xF8 + RD_KEY3_DATA0 volatile.Register32 // 0xFC + RD_KEY3_DATA1 volatile.Register32 // 0x100 + RD_KEY3_DATA2 volatile.Register32 // 0x104 + RD_KEY3_DATA3 volatile.Register32 // 0x108 + RD_KEY3_DATA4 volatile.Register32 // 0x10C + RD_KEY3_DATA5 volatile.Register32 // 0x110 + RD_KEY3_DATA6 volatile.Register32 // 0x114 + RD_KEY3_DATA7 volatile.Register32 // 0x118 + RD_KEY4_DATA0 volatile.Register32 // 0x11C + RD_KEY4_DATA1 volatile.Register32 // 0x120 + RD_KEY4_DATA2 volatile.Register32 // 0x124 + RD_KEY4_DATA3 volatile.Register32 // 0x128 + RD_KEY4_DATA4 volatile.Register32 // 0x12C + RD_KEY4_DATA5 volatile.Register32 // 0x130 + RD_KEY4_DATA6 volatile.Register32 // 0x134 + RD_KEY4_DATA7 volatile.Register32 // 0x138 + RD_KEY5_DATA0 volatile.Register32 // 0x13C + RD_KEY5_DATA1 volatile.Register32 // 0x140 + RD_KEY5_DATA2 volatile.Register32 // 0x144 + RD_KEY5_DATA3 volatile.Register32 // 0x148 + RD_KEY5_DATA4 volatile.Register32 // 0x14C + RD_KEY5_DATA5 volatile.Register32 // 0x150 + RD_KEY5_DATA6 volatile.Register32 // 0x154 + RD_KEY5_DATA7 volatile.Register32 // 0x158 + RD_SYS_DATA_PART2_0 volatile.Register32 // 0x15C + RD_SYS_DATA_PART2_1 volatile.Register32 // 0x160 + RD_SYS_DATA_PART2_2 volatile.Register32 // 0x164 + RD_SYS_DATA_PART2_3 volatile.Register32 // 0x168 + RD_SYS_DATA_PART2_4 volatile.Register32 // 0x16C + RD_SYS_DATA_PART2_5 volatile.Register32 // 0x170 + RD_SYS_DATA_PART2_6 volatile.Register32 // 0x174 + RD_SYS_DATA_PART2_7 volatile.Register32 // 0x178 + RD_REPEAT_ERR0 volatile.Register32 // 0x17C + RD_REPEAT_ERR1 volatile.Register32 // 0x180 + RD_REPEAT_ERR2 volatile.Register32 // 0x184 + RD_REPEAT_ERR3 volatile.Register32 // 0x188 + _ [4]byte + RD_REPEAT_ERR4 volatile.Register32 // 0x190 + _ [44]byte + RD_RS_ERR0 volatile.Register32 // 0x1C0 + RD_RS_ERR1 volatile.Register32 // 0x1C4 + CLK volatile.Register32 // 0x1C8 + CONF volatile.Register32 // 0x1CC + STATUS volatile.Register32 // 0x1D0 + CMD volatile.Register32 // 0x1D4 + INT_RAW volatile.Register32 // 0x1D8 + INT_ST volatile.Register32 // 0x1DC + INT_ENA volatile.Register32 // 0x1E0 + INT_CLR volatile.Register32 // 0x1E4 + DAC_CONF volatile.Register32 // 0x1E8 + RD_TIM_CONF volatile.Register32 // 0x1EC + WR_TIM_CONF0 volatile.Register32 // 0x1F0 + WR_TIM_CONF1 volatile.Register32 // 0x1F4 + WR_TIM_CONF2 volatile.Register32 // 0x1F8 + DATE volatile.Register32 // 0x1FC +} + +// EFUSE.PGM_DATA0: Register %s that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA0(value uint32) { + volatile.StoreUint32(&o.PGM_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA0() uint32 { + return volatile.LoadUint32(&o.PGM_DATA0.Reg) +} + +// EFUSE.PGM_DATA1: Register %s that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA1(value uint32) { + volatile.StoreUint32(&o.PGM_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA1() uint32 { + return volatile.LoadUint32(&o.PGM_DATA1.Reg) +} + +// EFUSE.PGM_DATA2: Register %s that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA2(value uint32) { + volatile.StoreUint32(&o.PGM_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA2() uint32 { + return volatile.LoadUint32(&o.PGM_DATA2.Reg) +} + +// EFUSE.PGM_DATA3: Register %s that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA3(value uint32) { + volatile.StoreUint32(&o.PGM_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA3() uint32 { + return volatile.LoadUint32(&o.PGM_DATA3.Reg) +} + +// EFUSE.PGM_DATA4: Register %s that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA4(value uint32) { + volatile.StoreUint32(&o.PGM_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA4() uint32 { + return volatile.LoadUint32(&o.PGM_DATA4.Reg) +} + +// EFUSE.PGM_DATA5: Register %s that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA5(value uint32) { + volatile.StoreUint32(&o.PGM_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA5() uint32 { + return volatile.LoadUint32(&o.PGM_DATA5.Reg) +} + +// EFUSE.PGM_DATA6: Register %s that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA6(value uint32) { + volatile.StoreUint32(&o.PGM_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA6() uint32 { + return volatile.LoadUint32(&o.PGM_DATA6.Reg) +} + +// EFUSE.PGM_DATA7: Register %s that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA7(value uint32) { + volatile.StoreUint32(&o.PGM_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA7() uint32 { + return volatile.LoadUint32(&o.PGM_DATA7.Reg) +} + +// EFUSE.PGM_CHECK_VALUE0: Register %s that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE0(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE0() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE0.Reg) +} + +// EFUSE.PGM_CHECK_VALUE1: Register %s that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE1(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE1() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE1.Reg) +} + +// EFUSE.PGM_CHECK_VALUE2: Register %s that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE2(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE2() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE2.Reg) +} + +// EFUSE.RD_WR_DIS: Register 0 of BLOCK0. +func (o *EFUSE_Type) SetRD_WR_DIS(value uint32) { + volatile.StoreUint32(&o.RD_WR_DIS.Reg, value) +} +func (o *EFUSE_Type) GetRD_WR_DIS() uint32 { + return volatile.LoadUint32(&o.RD_WR_DIS.Reg) +} + +// EFUSE.RD_REPEAT_DATA0: Register 1 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RD_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RD_DIS() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_RTC_RAM_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_RTC_RAM_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DCACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DCACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_CAN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_CAN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_BOOT_REMAP(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_BOOT_REMAP() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x10000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SOFT_DIS_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x20000)|value<<17) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SOFT_DIS_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x20000) >> 17 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_HARD_DIS_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_HARD_DIS_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x300000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x300000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_EXT_PHY_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_EXT_PHY_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_FORCE_NOPERSIST(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_FORCE_NOPERSIST() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RPT4_RESERVED0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RPT4_RESERVED0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_VDD_SPI_MODECURLIM(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_VDD_SPI_MODECURLIM() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_VDD_SPI_DREFH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_VDD_SPI_DREFH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_DATA1: Register 2 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_DREFM(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_DREFM() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_DREFL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xc)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_DREFL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xc) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_XPD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_XPD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_TIEH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_TIEH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_FORCE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_FORCE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_EN_INIT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_EN_INIT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_ENCURLIM(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_ENCURLIM() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_DCURLIM(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xe00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_DCURLIM() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xe00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_INIT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x3000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_INIT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x3000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_DCAP(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_DCAP() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_WDT_DELAY_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_WDT_DELAY_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA2: Register 3 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_2() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_6(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_6() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_RPT4_RESERVED1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xfc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_RPT4_RESERVED1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xfc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_TPUW(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_TPUW() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA3: Register 4 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CHANNEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CHANNEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CONTROL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CONTROL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_PIN_POWER_SELECTION(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_PIN_POWER_SELECTION() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FLASH_TYPE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FLASH_TYPE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FORCE_SEND_RESUME(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FORCE_SEND_RESUME() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_VERSION(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x7fff800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_VERSION() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x7fff800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xf8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xf8000000) >> 27 +} + +// EFUSE.RD_REPEAT_DATA4: Register 5 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_RPT4_RESERVED4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_RPT4_RESERVED4() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xffffff +} + +// EFUSE.RD_MAC_SPI_SYS_0: Register 0 of BLOCK1. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_0.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_0() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_0.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_1: Register 1 of BLOCK1. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_1_MAC_1(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_1_MAC_1() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_1_SPI_PAD_CONF_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_1_SPI_PAD_CONF_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.RD_MAC_SPI_SYS_2: Register 2 of BLOCK1. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_2(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_2.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_2() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_2.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_3: Register 3 of BLOCK1. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_3_SPI_PAD_CONF_2(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg)&^(0x3ffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_3_SPI_PAD_CONF_2() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg) & 0x3ffff +} +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_3_SYS_DATA_PART0_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg)&^(0xfffc0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_3_SYS_DATA_PART0_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg) & 0xfffc0000) >> 18 +} + +// EFUSE.RD_MAC_SPI_SYS_4: Register 4 of BLOCK1. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_4(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_4.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_4() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_4.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_5: Register 5 of BLOCK1. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_5(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_5.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_5() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_5.Reg) +} + +// EFUSE.RD_SYS_DATA_PART1_0: Register %s of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART1_0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART1_0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART1_0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART1_0.Reg) +} + +// EFUSE.RD_SYS_DATA_PART1_1: Register %s of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART1_1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART1_1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART1_1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART1_1.Reg) +} + +// EFUSE.RD_SYS_DATA_PART1_2: Register %s of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART1_2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART1_2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART1_2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART1_2.Reg) +} + +// EFUSE.RD_SYS_DATA_PART1_3: Register %s of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART1_3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART1_3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART1_3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART1_3.Reg) +} + +// EFUSE.RD_SYS_DATA_PART1_4: Register %s of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART1_4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART1_4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART1_4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART1_4.Reg) +} + +// EFUSE.RD_SYS_DATA_PART1_5: Register %s of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART1_5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART1_5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART1_5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART1_5.Reg) +} + +// EFUSE.RD_SYS_DATA_PART1_6: Register %s of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART1_6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART1_6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART1_6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART1_6.Reg) +} + +// EFUSE.RD_SYS_DATA_PART1_7: Register %s of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART1_7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART1_7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART1_7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART1_7.Reg) +} + +// EFUSE.RD_USR_DATA0: Register %s of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA0.Reg) +} + +// EFUSE.RD_USR_DATA1: Register %s of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA1.Reg) +} + +// EFUSE.RD_USR_DATA2: Register %s of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA2.Reg) +} + +// EFUSE.RD_USR_DATA3: Register %s of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA3.Reg) +} + +// EFUSE.RD_USR_DATA4: Register %s of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA4.Reg) +} + +// EFUSE.RD_USR_DATA5: Register %s of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA5.Reg) +} + +// EFUSE.RD_USR_DATA6: Register %s of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA6.Reg) +} + +// EFUSE.RD_USR_DATA7: Register %s of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA7.Reg) +} + +// EFUSE.RD_KEY0_DATA0: Register %s of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA0.Reg) +} + +// EFUSE.RD_KEY0_DATA1: Register %s of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA1.Reg) +} + +// EFUSE.RD_KEY0_DATA2: Register %s of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA2.Reg) +} + +// EFUSE.RD_KEY0_DATA3: Register %s of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA3.Reg) +} + +// EFUSE.RD_KEY0_DATA4: Register %s of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA4.Reg) +} + +// EFUSE.RD_KEY0_DATA5: Register %s of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA5.Reg) +} + +// EFUSE.RD_KEY0_DATA6: Register %s of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA6.Reg) +} + +// EFUSE.RD_KEY0_DATA7: Register %s of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA7.Reg) +} + +// EFUSE.RD_KEY1_DATA0: Register %s of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA0.Reg) +} + +// EFUSE.RD_KEY1_DATA1: Register %s of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA1.Reg) +} + +// EFUSE.RD_KEY1_DATA2: Register %s of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA2.Reg) +} + +// EFUSE.RD_KEY1_DATA3: Register %s of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA3.Reg) +} + +// EFUSE.RD_KEY1_DATA4: Register %s of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA4.Reg) +} + +// EFUSE.RD_KEY1_DATA5: Register %s of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA5.Reg) +} + +// EFUSE.RD_KEY1_DATA6: Register %s of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA6.Reg) +} + +// EFUSE.RD_KEY1_DATA7: Register %s of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA7.Reg) +} + +// EFUSE.RD_KEY2_DATA0: Register %s of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA0.Reg) +} + +// EFUSE.RD_KEY2_DATA1: Register %s of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA1.Reg) +} + +// EFUSE.RD_KEY2_DATA2: Register %s of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA2.Reg) +} + +// EFUSE.RD_KEY2_DATA3: Register %s of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA3.Reg) +} + +// EFUSE.RD_KEY2_DATA4: Register %s of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA4.Reg) +} + +// EFUSE.RD_KEY2_DATA5: Register %s of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA5.Reg) +} + +// EFUSE.RD_KEY2_DATA6: Register %s of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA6.Reg) +} + +// EFUSE.RD_KEY2_DATA7: Register %s of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA7.Reg) +} + +// EFUSE.RD_KEY3_DATA0: Register %s of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA0.Reg) +} + +// EFUSE.RD_KEY3_DATA1: Register %s of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA1.Reg) +} + +// EFUSE.RD_KEY3_DATA2: Register %s of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA2.Reg) +} + +// EFUSE.RD_KEY3_DATA3: Register %s of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA3.Reg) +} + +// EFUSE.RD_KEY3_DATA4: Register %s of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA4.Reg) +} + +// EFUSE.RD_KEY3_DATA5: Register %s of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA5.Reg) +} + +// EFUSE.RD_KEY3_DATA6: Register %s of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA6.Reg) +} + +// EFUSE.RD_KEY3_DATA7: Register %s of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA7.Reg) +} + +// EFUSE.RD_KEY4_DATA0: Register %s of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA0.Reg) +} + +// EFUSE.RD_KEY4_DATA1: Register %s of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA1.Reg) +} + +// EFUSE.RD_KEY4_DATA2: Register %s of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA2.Reg) +} + +// EFUSE.RD_KEY4_DATA3: Register %s of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA3.Reg) +} + +// EFUSE.RD_KEY4_DATA4: Register %s of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA4.Reg) +} + +// EFUSE.RD_KEY4_DATA5: Register %s of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA5.Reg) +} + +// EFUSE.RD_KEY4_DATA6: Register %s of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA6.Reg) +} + +// EFUSE.RD_KEY4_DATA7: Register %s of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA7.Reg) +} + +// EFUSE.RD_KEY5_DATA0: Register %s of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA0.Reg) +} + +// EFUSE.RD_KEY5_DATA1: Register %s of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA1.Reg) +} + +// EFUSE.RD_KEY5_DATA2: Register %s of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA2.Reg) +} + +// EFUSE.RD_KEY5_DATA3: Register %s of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA3.Reg) +} + +// EFUSE.RD_KEY5_DATA4: Register %s of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA4.Reg) +} + +// EFUSE.RD_KEY5_DATA5: Register %s of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA5.Reg) +} + +// EFUSE.RD_KEY5_DATA6: Register %s of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA6.Reg) +} + +// EFUSE.RD_KEY5_DATA7: Register %s of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA7.Reg) +} + +// EFUSE.RD_SYS_DATA_PART2_0: Register %s of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART2_0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART2_0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART2_0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART2_0.Reg) +} + +// EFUSE.RD_SYS_DATA_PART2_1: Register %s of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART2_1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART2_1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART2_1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART2_1.Reg) +} + +// EFUSE.RD_SYS_DATA_PART2_2: Register %s of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART2_2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART2_2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART2_2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART2_2.Reg) +} + +// EFUSE.RD_SYS_DATA_PART2_3: Register %s of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART2_3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART2_3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART2_3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART2_3.Reg) +} + +// EFUSE.RD_SYS_DATA_PART2_4: Register %s of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART2_4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART2_4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART2_4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART2_4.Reg) +} + +// EFUSE.RD_SYS_DATA_PART2_5: Register %s of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART2_5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART2_5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART2_5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART2_5.Reg) +} + +// EFUSE.RD_SYS_DATA_PART2_6: Register %s of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART2_6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART2_6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART2_6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART2_6.Reg) +} + +// EFUSE.RD_SYS_DATA_PART2_7: Register %s of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_DATA_PART2_7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_DATA_PART2_7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_DATA_PART2_7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_DATA_PART2_7.Reg) +} + +// EFUSE.RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RD_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RD_DIS_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DCACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DCACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_CAN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_CAN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_BOOT_REMAP_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_BOOT_REMAP_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED5_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED5_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x10000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x20000)|value<<17) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x20000) >> 17 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_HARD_DIS_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x40000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_HARD_DIS_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x40000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x300000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x300000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0xc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0xc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_FORCE_NOPERSIST_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_FORCE_NOPERSIST_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RPT4_RESERVED0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_VDD_SPI_DREFH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_VDD_SPI_DREFH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_DREFM_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_DREFM_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_DREFL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xc)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_DREFL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xc) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_XPD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_XPD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_TIEH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_TIEH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_FORCE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_FORCE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_DCURLIM_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xe00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_DCURLIM_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xe00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_INIT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x3000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_INIT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x3000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_DCAP_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_DCAP_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_6_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_6_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_RPT4_RESERVED1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xfc00000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_RPT4_RESERVED1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xfc00000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_TPUW_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_TPUW_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED3_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FLASH_TYPE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FLASH_TYPE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_VERSION_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x7fff800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_VERSION_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x7fff800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xf8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED2_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xf8000000) >> 27 +} + +// EFUSE.RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_RPT4_RESERVED4_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xffffff +} + +// EFUSE.RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700)|value<<8) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700) >> 8 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000)|value<<12) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000) >> 12 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700000)|value<<20) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700000) >> 20 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000000) >> 24 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000000) >> 27 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000000) >> 28 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000000)|value<<31) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000000) >> 31 +} + +// EFUSE.RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x80) >> 7 +} + +// EFUSE.CLK: eFuse clock configuration register. +func (o *EFUSE_Type) SetCLK_EFUSE_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCLK_EFUSE_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCLK_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCLK_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCLK_EFUSE_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetCLK_EFUSE_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x10000) >> 16 +} + +// EFUSE.CONF: eFuse operation mode configuration register. +func (o *EFUSE_Type) SetCONF_OP_CODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetCONF_OP_CODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0xffff +} + +// EFUSE.STATUS: eFuse status register. +func (o *EFUSE_Type) SetSTATUS_STATE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetSTATUS_STATE() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xf +} +func (o *EFUSE_Type) SetSTATUS_OTP_LOAD_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetSTATUS_OTP_LOAD_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_C_SYNC2(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_C_SYNC2() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetSTATUS_OTP_STROBE_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetSTATUS_OTP_STROBE_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetSTATUS_OTP_CSB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetSTATUS_OTP_CSB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetSTATUS_OTP_PGENB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetSTATUS_OTP_PGENB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_IS_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_IS_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetSTATUS_REPEAT_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3fc00)|value<<10) +} +func (o *EFUSE_Type) GetSTATUS_REPEAT_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3fc00) >> 10 +} + +// EFUSE.CMD: eFuse command register. +func (o *EFUSE_Type) SetCMD_READ_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCMD_READ_CMD() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCMD_PGM_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCMD_PGM_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCMD_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3c)|value<<2) +} +func (o *EFUSE_Type) GetCMD_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x3c) >> 2 +} + +// EFUSE.INT_RAW: eFuse raw interrupt register. +func (o *EFUSE_Type) SetINT_RAW_READ_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_RAW_READ_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_RAW_PGM_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_RAW_PGM_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ST: eFuse interrupt status register. +func (o *EFUSE_Type) SetINT_ST_READ_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ST_READ_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ST_PGM_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ST_PGM_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ENA: eFuse interrupt enable register. +func (o *EFUSE_Type) SetINT_ENA_READ_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ENA_READ_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ENA_PGM_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ENA_PGM_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_CLR: eFuse interrupt clear register. +func (o *EFUSE_Type) SetINT_CLR_READ_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_CLR_READ_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_CLR_PGM_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_CLR_PGM_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// EFUSE.DAC_CONF: Controls the eFuse programming voltage. +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.DAC_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_PAD_SEL(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_PAD_SEL() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_NUM(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x1fe00)|value<<9) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_NUM() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x1fe00) >> 9 +} +func (o *EFUSE_Type) SetDAC_CONF_OE_CLR(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EFUSE_Type) GetDAC_CONF_OE_CLR() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x20000) >> 17 +} + +// EFUSE.RD_TIM_CONF: Configures read timing parameters. +func (o *EFUSE_Type) SetRD_TIM_CONF_THR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_THR_A() uint32 { + return volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TRD(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TRD() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff00) >> 8 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_TSUR_A(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_TSUR_A() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff0000) >> 16 +} +func (o *EFUSE_Type) SetRD_TIM_CONF_READ_INIT_NUM(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_READ_INIT_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF0: Configuration register 0 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF0_THP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_THP_A() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF0.Reg) & 0xff +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_TPGM_INACTIVE(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_TPGM_INACTIVE() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0.Reg) & 0xff00) >> 8 +} +func (o *EFUSE_Type) SetWR_TIM_CONF0_TPGM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF0.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetWR_TIM_CONF0_TPGM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF0.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.WR_TIM_CONF1: Configuration register 1 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF1_TSUP_A(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_TSUP_A() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff +} +func (o *EFUSE_Type) SetWR_TIM_CONF1_PWR_ON_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xffff00)|value<<8) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_PWR_ON_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xffff00) >> 8 +} + +// EFUSE.WR_TIM_CONF2: Configuration register 2 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF2_PWR_OFF_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_PWR_OFF_NUM() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff +} + +// EFUSE.DATE: Version control register. +func (o *EFUSE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *EFUSE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// External Memory +type EXTMEM_Type struct { + PRO_DCACHE_CTRL volatile.Register32 // 0x0 + PRO_DCACHE_CTRL1 volatile.Register32 // 0x4 + PRO_DCACHE_TAG_POWER_CTRL volatile.Register32 // 0x8 + PRO_DCACHE_LOCK0_ADDR volatile.Register32 // 0xC + PRO_DCACHE_LOCK0_SIZE volatile.Register32 // 0x10 + PRO_DCACHE_LOCK1_ADDR volatile.Register32 // 0x14 + PRO_DCACHE_LOCK1_SIZE volatile.Register32 // 0x18 + PRO_DCACHE_MEM_SYNC0 volatile.Register32 // 0x1C + PRO_DCACHE_MEM_SYNC1 volatile.Register32 // 0x20 + PRO_DCACHE_PRELOAD_ADDR volatile.Register32 // 0x24 + PRO_DCACHE_PRELOAD_SIZE volatile.Register32 // 0x28 + PRO_DCACHE_AUTOLOAD_CFG volatile.Register32 // 0x2C + PRO_DCACHE_AUTOLOAD_SECTION0_ADDR volatile.Register32 // 0x30 + PRO_DCACHE_AUTOLOAD_SECTION0_SIZE volatile.Register32 // 0x34 + PRO_DCACHE_AUTOLOAD_SECTION1_ADDR volatile.Register32 // 0x38 + PRO_DCACHE_AUTOLOAD_SECTION1_SIZE volatile.Register32 // 0x3C + PRO_ICACHE_CTRL volatile.Register32 // 0x40 + PRO_ICACHE_CTRL1 volatile.Register32 // 0x44 + PRO_ICACHE_TAG_POWER_CTRL volatile.Register32 // 0x48 + PRO_ICACHE_LOCK0_ADDR volatile.Register32 // 0x4C + PRO_ICACHE_LOCK0_SIZE volatile.Register32 // 0x50 + PRO_ICACHE_LOCK1_ADDR volatile.Register32 // 0x54 + PRO_ICACHE_LOCK1_SIZE volatile.Register32 // 0x58 + PRO_ICACHE_MEM_SYNC0 volatile.Register32 // 0x5C + PRO_ICACHE_MEM_SYNC1 volatile.Register32 // 0x60 + PRO_ICACHE_PRELOAD_ADDR volatile.Register32 // 0x64 + PRO_ICACHE_PRELOAD_SIZE volatile.Register32 // 0x68 + PRO_ICACHE_AUTOLOAD_CFG volatile.Register32 // 0x6C + PRO_ICACHE_AUTOLOAD_SECTION0_ADDR volatile.Register32 // 0x70 + PRO_ICACHE_AUTOLOAD_SECTION0_SIZE volatile.Register32 // 0x74 + PRO_ICACHE_AUTOLOAD_SECTION1_ADDR volatile.Register32 // 0x78 + PRO_ICACHE_AUTOLOAD_SECTION1_SIZE volatile.Register32 // 0x7C + IC_PRELOAD_CNT volatile.Register32 // 0x80 + IC_PRELOAD_MISS_CNT volatile.Register32 // 0x84 + IBUS2_ABANDON_CNT volatile.Register32 // 0x88 + IBUS1_ABANDON_CNT volatile.Register32 // 0x8C + IBUS0_ABANDON_CNT volatile.Register32 // 0x90 + IBUS2_ACS_MISS_CNT volatile.Register32 // 0x94 + IBUS1_ACS_MISS_CNT volatile.Register32 // 0x98 + IBUS0_ACS_MISS_CNT volatile.Register32 // 0x9C + IBUS2_ACS_CNT volatile.Register32 // 0xA0 + IBUS1_ACS_CNT volatile.Register32 // 0xA4 + IBUS0_ACS_CNT volatile.Register32 // 0xA8 + DC_PRELOAD_CNT volatile.Register32 // 0xAC + DC_PRELOAD_EVICT_CNT volatile.Register32 // 0xB0 + DC_PRELOAD_MISS_CNT volatile.Register32 // 0xB4 + DBUS2_ABANDON_CNT volatile.Register32 // 0xB8 + DBUS1_ABANDON_CNT volatile.Register32 // 0xBC + DBUS0_ABANDON_CNT volatile.Register32 // 0xC0 + DBUS2_ACS_WB_CNT volatile.Register32 // 0xC4 + DBUS1_ACS_WB_CNT volatile.Register32 // 0xC8 + DBUS0_ACS_WB_CNT volatile.Register32 // 0xCC + DBUS2_ACS_MISS_CNT volatile.Register32 // 0xD0 + DBUS1_ACS_MISS_CNT volatile.Register32 // 0xD4 + DBUS0_ACS_MISS_CNT volatile.Register32 // 0xD8 + DBUS2_ACS_CNT volatile.Register32 // 0xDC + DBUS1_ACS_CNT volatile.Register32 // 0xE0 + DBUS0_ACS_CNT volatile.Register32 // 0xE4 + CACHE_DBG_INT_ENA volatile.Register32 // 0xE8 + CACHE_DBG_INT_CLR volatile.Register32 // 0xEC + CACHE_DBG_STATUS0 volatile.Register32 // 0xF0 + CACHE_DBG_STATUS1 volatile.Register32 // 0xF4 + PRO_CACHE_ACS_CNT_CLR volatile.Register32 // 0xF8 + PRO_DCACHE_REJECT_ST volatile.Register32 // 0xFC + PRO_DCACHE_REJECT_VADDR volatile.Register32 // 0x100 + PRO_ICACHE_REJECT_ST volatile.Register32 // 0x104 + PRO_ICACHE_REJECT_VADDR volatile.Register32 // 0x108 + PRO_CACHE_MMU_FAULT_CONTENT volatile.Register32 // 0x10C + PRO_CACHE_MMU_FAULT_VADDR volatile.Register32 // 0x110 + PRO_CACHE_WRAP_AROUND_CTRL volatile.Register32 // 0x114 + PRO_CACHE_MMU_POWER_CTRL volatile.Register32 // 0x118 + PRO_CACHE_STATE volatile.Register32 // 0x11C + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE volatile.Register32 // 0x120 + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON volatile.Register32 // 0x124 + CACHE_BRIDGE_ARBITER_CTRL volatile.Register32 // 0x128 + CACHE_PRELOAD_INT_CTRL volatile.Register32 // 0x12C + CACHE_SYNC_INT_CTRL volatile.Register32 // 0x130 + CACHE_CONF_MISC volatile.Register32 // 0x134 + CLOCK_GATE volatile.Register32 // 0x138 + _ [704]byte + PRO_EXTMEM_REG_DATE volatile.Register32 // 0x3FC +} + +// EXTMEM.PRO_DCACHE_CTRL: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_ENABLE() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_SETSIZE_MODE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_SETSIZE_MODE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_BLOCKSIZE_MODE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_BLOCKSIZE_MODE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_LOCK0_EN(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_LOCK0_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_LOCK1_EN(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_LOCK1_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x8000) >> 15 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x40000) >> 18 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x80000) >> 19 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x200000) >> 21 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x400000) >> 22 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x800000) >> 23 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_LOCK_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_LOCK_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL_PRO_DCACHE_LOCK_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL_PRO_DCACHE_LOCK_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL.Reg) & 0x2000000) >> 25 +} + +// EXTMEM.PRO_DCACHE_CTRL1: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS0(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL1.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS0() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_CTRL1.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS1(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS1() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL1.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS2(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_DCACHE_CTRL1.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS2() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_CTRL1.Reg) & 0x4) >> 2 +} + +// EXTMEM.PRO_DCACHE_TAG_POWER_CTRL: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_TAG_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_TAG_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_TAG_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_TAG_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.PRO_DCACHE_TAG_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_TAG_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.PRO_DCACHE_LOCK0_ADDR: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_LOCK0_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_LOCK0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_LOCK0_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_LOCK0_ADDR.Reg) +} + +// EXTMEM.PRO_DCACHE_LOCK0_SIZE: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_LOCK0_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_LOCK0_SIZE.Reg, volatile.LoadUint32(&o.PRO_DCACHE_LOCK0_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_LOCK0_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_LOCK0_SIZE.Reg) & 0xffff +} + +// EXTMEM.PRO_DCACHE_LOCK1_ADDR: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_LOCK1_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_LOCK1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_LOCK1_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_LOCK1_ADDR.Reg) +} + +// EXTMEM.PRO_DCACHE_LOCK1_SIZE: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_LOCK1_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_LOCK1_SIZE.Reg, volatile.LoadUint32(&o.PRO_DCACHE_LOCK1_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_LOCK1_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_LOCK1_SIZE.Reg) & 0xffff +} + +// EXTMEM.PRO_DCACHE_MEM_SYNC0: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_MEM_SYNC0(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_MEM_SYNC0.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_MEM_SYNC0() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_MEM_SYNC0.Reg) +} + +// EXTMEM.PRO_DCACHE_MEM_SYNC1: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_MEM_SYNC1_PRO_DCACHE_MEMSYNC_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_MEM_SYNC1.Reg, volatile.LoadUint32(&o.PRO_DCACHE_MEM_SYNC1.Reg)&^(0x7ffff)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_MEM_SYNC1_PRO_DCACHE_MEMSYNC_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_MEM_SYNC1.Reg) & 0x7ffff +} + +// EXTMEM.PRO_DCACHE_PRELOAD_ADDR: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_PRELOAD_ADDR.Reg) +} + +// EXTMEM.PRO_DCACHE_PRELOAD_SIZE: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.PRO_DCACHE_PRELOAD_SIZE.Reg)&^(0x3ff)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_PRELOAD_SIZE.Reg) & 0x3ff +} +func (o *EXTMEM_Type) SetPRO_DCACHE_PRELOAD_SIZE_PRO_DCACHE_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.PRO_DCACHE_PRELOAD_SIZE.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_PRELOAD_SIZE_PRO_DCACHE_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_PRELOAD_SIZE.Reg) & 0x400) >> 10 +} + +// EXTMEM.PRO_DCACHE_AUTOLOAD_CFG: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_MODE() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_STEP(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg)&^(0x6)|value<<1) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_STEP() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg) & 0x6) >> 1 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_RQST(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg)&^(0x30)|value<<4) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_RQST() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg) & 0x30) >> 4 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg)&^(0xc0)|value<<6) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SIZE() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg) & 0xc0) >> 6 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_CFG.Reg) & 0x200) >> 9 +} + +// EXTMEM.PRO_DCACHE_AUTOLOAD_SECTION0_ADDR: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_SECTION0_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_SECTION0_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION0_ADDR.Reg) +} + +// EXTMEM.PRO_DCACHE_AUTOLOAD_SECTION0_SIZE: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_SECTION0_SIZE_PRO_DCACHE_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION0_SIZE.Reg, volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION0_SIZE.Reg)&^(0xffffff)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_SECTION0_SIZE_PRO_DCACHE_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION0_SIZE.Reg) & 0xffffff +} + +// EXTMEM.PRO_DCACHE_AUTOLOAD_SECTION1_ADDR: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_SECTION1_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_SECTION1_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION1_ADDR.Reg) +} + +// EXTMEM.PRO_DCACHE_AUTOLOAD_SECTION1_SIZE: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_AUTOLOAD_SECTION1_SIZE_PRO_DCACHE_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION1_SIZE.Reg, volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION1_SIZE.Reg)&^(0xffffff)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_AUTOLOAD_SECTION1_SIZE_PRO_DCACHE_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_AUTOLOAD_SECTION1_SIZE.Reg) & 0xffffff +} + +// EXTMEM.PRO_ICACHE_CTRL: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_ENABLE() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_SETSIZE_MODE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_SETSIZE_MODE() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_BLOCKSIZE_MODE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_BLOCKSIZE_MODE() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_LOCK0_EN(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_LOCK0_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_LOCK1_EN(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_LOCK1_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x8000) >> 15 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x40000) >> 18 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x80000) >> 19 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x200000) >> 21 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x400000) >> 22 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x800000) >> 23 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_LOCK_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_LOCK_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL_PRO_ICACHE_LOCK_DONE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL_PRO_ICACHE_LOCK_DONE() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL.Reg) & 0x2000000) >> 25 +} + +// EXTMEM.PRO_ICACHE_CTRL1: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS0(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL1.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS0() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_CTRL1.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS1(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS1() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL1.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS2(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_CTRL1.Reg, volatile.LoadUint32(&o.PRO_ICACHE_CTRL1.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS2() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_CTRL1.Reg) & 0x4) >> 2 +} + +// EXTMEM.PRO_ICACHE_TAG_POWER_CTRL: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_TAG_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_TAG_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_TAG_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_TAG_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.PRO_ICACHE_TAG_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_TAG_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.PRO_ICACHE_LOCK0_ADDR: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_LOCK0_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_LOCK0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_LOCK0_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_LOCK0_ADDR.Reg) +} + +// EXTMEM.PRO_ICACHE_LOCK0_SIZE: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_LOCK0_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_LOCK0_SIZE.Reg, volatile.LoadUint32(&o.PRO_ICACHE_LOCK0_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_LOCK0_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_LOCK0_SIZE.Reg) & 0xffff +} + +// EXTMEM.PRO_ICACHE_LOCK1_ADDR: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_LOCK1_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_LOCK1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_LOCK1_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_LOCK1_ADDR.Reg) +} + +// EXTMEM.PRO_ICACHE_LOCK1_SIZE: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_LOCK1_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_LOCK1_SIZE.Reg, volatile.LoadUint32(&o.PRO_ICACHE_LOCK1_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_LOCK1_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_LOCK1_SIZE.Reg) & 0xffff +} + +// EXTMEM.PRO_ICACHE_MEM_SYNC0: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_MEM_SYNC0(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_MEM_SYNC0.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_MEM_SYNC0() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_MEM_SYNC0.Reg) +} + +// EXTMEM.PRO_ICACHE_MEM_SYNC1: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_MEM_SYNC1_PRO_ICACHE_MEMSYNC_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_MEM_SYNC1.Reg, volatile.LoadUint32(&o.PRO_ICACHE_MEM_SYNC1.Reg)&^(0x7ffff)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_MEM_SYNC1_PRO_ICACHE_MEMSYNC_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_MEM_SYNC1.Reg) & 0x7ffff +} + +// EXTMEM.PRO_ICACHE_PRELOAD_ADDR: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_PRELOAD_ADDR.Reg) +} + +// EXTMEM.PRO_ICACHE_PRELOAD_SIZE: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.PRO_ICACHE_PRELOAD_SIZE.Reg)&^(0x3ff)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_PRELOAD_SIZE.Reg) & 0x3ff +} +func (o *EXTMEM_Type) SetPRO_ICACHE_PRELOAD_SIZE_PRO_ICACHE_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.PRO_ICACHE_PRELOAD_SIZE.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_PRELOAD_SIZE_PRO_ICACHE_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_PRELOAD_SIZE.Reg) & 0x400) >> 10 +} + +// EXTMEM.PRO_ICACHE_AUTOLOAD_CFG: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_MODE() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_STEP(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg)&^(0x6)|value<<1) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_STEP() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg) & 0x6) >> 1 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_RQST(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg)&^(0x30)|value<<4) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_RQST() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg) & 0x30) >> 4 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg)&^(0xc0)|value<<6) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SIZE() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg) & 0xc0) >> 6 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT0_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg, volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_CFG.Reg) & 0x200) >> 9 +} + +// EXTMEM.PRO_ICACHE_AUTOLOAD_SECTION0_ADDR: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_SECTION0_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_SECTION0_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION0_ADDR.Reg) +} + +// EXTMEM.PRO_ICACHE_AUTOLOAD_SECTION0_SIZE: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_SECTION0_SIZE_PRO_ICACHE_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION0_SIZE.Reg, volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION0_SIZE.Reg)&^(0xffffff)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_SECTION0_SIZE_PRO_ICACHE_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION0_SIZE.Reg) & 0xffffff +} + +// EXTMEM.PRO_ICACHE_AUTOLOAD_SECTION1_ADDR: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_SECTION1_ADDR(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_SECTION1_ADDR() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION1_ADDR.Reg) +} + +// EXTMEM.PRO_ICACHE_AUTOLOAD_SECTION1_SIZE: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_AUTOLOAD_SECTION1_SIZE_PRO_ICACHE_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION1_SIZE.Reg, volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION1_SIZE.Reg)&^(0xffffff)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_AUTOLOAD_SECTION1_SIZE_PRO_ICACHE_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_AUTOLOAD_SECTION1_SIZE.Reg) & 0xffffff +} + +// EXTMEM.IC_PRELOAD_CNT: register description +func (o *EXTMEM_Type) SetIC_PRELOAD_CNT(value uint32) { + volatile.StoreUint32(&o.IC_PRELOAD_CNT.Reg, volatile.LoadUint32(&o.IC_PRELOAD_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetIC_PRELOAD_CNT() uint32 { + return volatile.LoadUint32(&o.IC_PRELOAD_CNT.Reg) & 0xffff +} + +// EXTMEM.IC_PRELOAD_MISS_CNT: register description +func (o *EXTMEM_Type) SetIC_PRELOAD_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.IC_PRELOAD_MISS_CNT.Reg, volatile.LoadUint32(&o.IC_PRELOAD_MISS_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetIC_PRELOAD_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.IC_PRELOAD_MISS_CNT.Reg) & 0xffff +} + +// EXTMEM.IBUS2_ABANDON_CNT: register description +func (o *EXTMEM_Type) SetIBUS2_ABANDON_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS2_ABANDON_CNT.Reg, volatile.LoadUint32(&o.IBUS2_ABANDON_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetIBUS2_ABANDON_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS2_ABANDON_CNT.Reg) & 0xffff +} + +// EXTMEM.IBUS1_ABANDON_CNT: register description +func (o *EXTMEM_Type) SetIBUS1_ABANDON_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS1_ABANDON_CNT.Reg, volatile.LoadUint32(&o.IBUS1_ABANDON_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetIBUS1_ABANDON_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS1_ABANDON_CNT.Reg) & 0xffff +} + +// EXTMEM.IBUS0_ABANDON_CNT: register description +func (o *EXTMEM_Type) SetIBUS0_ABANDON_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS0_ABANDON_CNT.Reg, volatile.LoadUint32(&o.IBUS0_ABANDON_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetIBUS0_ABANDON_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS0_ABANDON_CNT.Reg) & 0xffff +} + +// EXTMEM.IBUS2_ACS_MISS_CNT: register description +func (o *EXTMEM_Type) SetIBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS2_ACS_MISS_CNT.Reg) +} + +// EXTMEM.IBUS1_ACS_MISS_CNT: register description +func (o *EXTMEM_Type) SetIBUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS1_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS1_ACS_MISS_CNT.Reg) +} + +// EXTMEM.IBUS0_ACS_MISS_CNT: register description +func (o *EXTMEM_Type) SetIBUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS0_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS0_ACS_MISS_CNT.Reg) +} + +// EXTMEM.IBUS2_ACS_CNT: register description +func (o *EXTMEM_Type) SetIBUS2_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS2_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS2_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS2_ACS_CNT.Reg) +} + +// EXTMEM.IBUS1_ACS_CNT: register description +func (o *EXTMEM_Type) SetIBUS1_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS1_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS1_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS1_ACS_CNT.Reg) +} + +// EXTMEM.IBUS0_ACS_CNT: register description +func (o *EXTMEM_Type) SetIBUS0_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS0_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS0_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS0_ACS_CNT.Reg) +} + +// EXTMEM.DC_PRELOAD_CNT: register description +func (o *EXTMEM_Type) SetDC_PRELOAD_CNT(value uint32) { + volatile.StoreUint32(&o.DC_PRELOAD_CNT.Reg, volatile.LoadUint32(&o.DC_PRELOAD_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDC_PRELOAD_CNT() uint32 { + return volatile.LoadUint32(&o.DC_PRELOAD_CNT.Reg) & 0xffff +} + +// EXTMEM.DC_PRELOAD_EVICT_CNT: register description +func (o *EXTMEM_Type) SetDC_PRELOAD_EVICT_CNT(value uint32) { + volatile.StoreUint32(&o.DC_PRELOAD_EVICT_CNT.Reg, volatile.LoadUint32(&o.DC_PRELOAD_EVICT_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDC_PRELOAD_EVICT_CNT() uint32 { + return volatile.LoadUint32(&o.DC_PRELOAD_EVICT_CNT.Reg) & 0xffff +} + +// EXTMEM.DC_PRELOAD_MISS_CNT: register description +func (o *EXTMEM_Type) SetDC_PRELOAD_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.DC_PRELOAD_MISS_CNT.Reg, volatile.LoadUint32(&o.DC_PRELOAD_MISS_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDC_PRELOAD_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.DC_PRELOAD_MISS_CNT.Reg) & 0xffff +} + +// EXTMEM.DBUS2_ABANDON_CNT: register description +func (o *EXTMEM_Type) SetDBUS2_ABANDON_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS2_ABANDON_CNT.Reg, volatile.LoadUint32(&o.DBUS2_ABANDON_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDBUS2_ABANDON_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS2_ABANDON_CNT.Reg) & 0xffff +} + +// EXTMEM.DBUS1_ABANDON_CNT: register description +func (o *EXTMEM_Type) SetDBUS1_ABANDON_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS1_ABANDON_CNT.Reg, volatile.LoadUint32(&o.DBUS1_ABANDON_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDBUS1_ABANDON_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS1_ABANDON_CNT.Reg) & 0xffff +} + +// EXTMEM.DBUS0_ABANDON_CNT: register description +func (o *EXTMEM_Type) SetDBUS0_ABANDON_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS0_ABANDON_CNT.Reg, volatile.LoadUint32(&o.DBUS0_ABANDON_CNT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDBUS0_ABANDON_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS0_ABANDON_CNT.Reg) & 0xffff +} + +// EXTMEM.DBUS2_ACS_WB_CNT: register description +func (o *EXTMEM_Type) SetDBUS2_ACS_WB_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS2_ACS_WB_CNT.Reg, volatile.LoadUint32(&o.DBUS2_ACS_WB_CNT.Reg)&^(0xfffff)|value) +} +func (o *EXTMEM_Type) GetDBUS2_ACS_WB_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS2_ACS_WB_CNT.Reg) & 0xfffff +} + +// EXTMEM.DBUS1_ACS_WB_CNT: register description +func (o *EXTMEM_Type) SetDBUS1_ACS_WB_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS1_ACS_WB_CNT.Reg, volatile.LoadUint32(&o.DBUS1_ACS_WB_CNT.Reg)&^(0xfffff)|value) +} +func (o *EXTMEM_Type) GetDBUS1_ACS_WB_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS1_ACS_WB_CNT.Reg) & 0xfffff +} + +// EXTMEM.DBUS0_ACS_WB_CNT: register description +func (o *EXTMEM_Type) SetDBUS0_ACS_WB_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS0_ACS_WB_CNT.Reg, volatile.LoadUint32(&o.DBUS0_ACS_WB_CNT.Reg)&^(0xfffff)|value) +} +func (o *EXTMEM_Type) GetDBUS0_ACS_WB_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS0_ACS_WB_CNT.Reg) & 0xfffff +} + +// EXTMEM.DBUS2_ACS_MISS_CNT: register description +func (o *EXTMEM_Type) SetDBUS2_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS2_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS2_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS2_ACS_MISS_CNT.Reg) +} + +// EXTMEM.DBUS1_ACS_MISS_CNT: register description +func (o *EXTMEM_Type) SetDBUS1_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS1_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS1_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS1_ACS_MISS_CNT.Reg) +} + +// EXTMEM.DBUS0_ACS_MISS_CNT: register description +func (o *EXTMEM_Type) SetDBUS0_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS0_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS0_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS0_ACS_MISS_CNT.Reg) +} + +// EXTMEM.DBUS2_ACS_CNT: register description +func (o *EXTMEM_Type) SetDBUS2_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS2_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS2_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS2_ACS_CNT.Reg) +} + +// EXTMEM.DBUS1_ACS_CNT: register description +func (o *EXTMEM_Type) SetDBUS1_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS1_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS1_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS1_ACS_CNT.Reg) +} + +// EXTMEM.DBUS0_ACS_CNT: register description +func (o *EXTMEM_Type) SetDBUS0_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS0_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS0_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS0_ACS_CNT.Reg) +} + +// EXTMEM.CACHE_DBG_INT_ENA: register description +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_CACHE_DBG_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_CACHE_DBG_EN() uint32 { + return volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_IBUS_ACS_MSK_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_IBUS_ACS_MSK_IC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_IBUS_CNT_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_IBUS_CNT_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_IC_SYNC_SIZE_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_IC_SYNC_SIZE_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_IC_PRELOAD_SIZE_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_IC_PRELOAD_SIZE_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_ICACHE_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_ICACHE_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_ICACHE_SET_PRELOAD_ILG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_ICACHE_SET_PRELOAD_ILG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_ICACHE_SET_SYNC_ILG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_ICACHE_SET_SYNC_ILG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_ICACHE_SET_LOCK_ILG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_ICACHE_SET_LOCK_ILG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_DBUS_ACS_MSK_DC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_DBUS_ACS_MSK_DC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_DBUS_CNT_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_DBUS_CNT_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_DC_SYNC_SIZE_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_DC_SYNC_SIZE_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_DC_PRELOAD_SIZE_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_DC_PRELOAD_SIZE_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_DCACHE_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_DCACHE_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_DCACHE_SET_PRELOAD_ILG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_DCACHE_SET_PRELOAD_ILG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_DCACHE_SET_SYNC_ILG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_DCACHE_SET_SYNC_ILG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_DCACHE_SET_LOCK_ILG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_DCACHE_SET_LOCK_ILG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_ENA.Reg) & 0x80000) >> 19 +} + +// EXTMEM.CACHE_DBG_INT_CLR: register description +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_IBUS_ACS_MSK_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_IBUS_ACS_MSK_IC_INT_CLR() uint32 { + return volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_IBUS_CNT_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_IBUS_CNT_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_IC_SYNC_SIZE_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_IC_SYNC_SIZE_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_IC_PRELOAD_SIZE_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_IC_PRELOAD_SIZE_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_ICACHE_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_ICACHE_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_ICACHE_SET_ILG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_ICACHE_SET_ILG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_DBUS_ACS_MSK_DC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_DBUS_ACS_MSK_DC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_DBUS_CNT_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_DBUS_CNT_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_DC_SYNC_SIZE_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_DC_SYNC_SIZE_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_DC_PRELOAD_SIZE_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_DC_PRELOAD_SIZE_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_DCACHE_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_DCACHE_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_DCACHE_SET_ILG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_DCACHE_SET_ILG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetCACHE_DBG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetCACHE_DBG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_INT_CLR.Reg) & 0x2000) >> 13 +} + +// EXTMEM.CACHE_DBG_STATUS0: register description +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS0_ACS_MSK_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS0_ACS_MSK_ICACHE_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS1_ACS_MSK_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS1_ACS_MSK_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS2_ACS_MSK_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS2_ACS_MSK_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS0_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS0_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS1_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS1_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS2_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS2_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS0_ACS_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS0_ACS_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS1_ACS_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS1_ACS_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS2_ACS_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS2_ACS_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS0_ABANDON_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS0_ABANDON_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS1_ABANDON_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS1_ABANDON_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IBUS2_ABANDON_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IBUS2_ABANDON_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IC_PRELOAD_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x10000)|value<<16) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IC_PRELOAD_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x10000) >> 16 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IC_PRELOAD_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x40000)|value<<18) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IC_PRELOAD_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x40000) >> 18 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IC_SYNC_SIZE_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x80000)|value<<19) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IC_SYNC_SIZE_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x80000) >> 19 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_IC_PRELOAD_SIZE_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_IC_PRELOAD_SIZE_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_ICACHE_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_ICACHE_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x200000) >> 21 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_ICACHE_SET_PRELOAD_ILG_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x400000)|value<<22) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_ICACHE_SET_PRELOAD_ILG_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x400000) >> 22 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_ICACHE_SET_SYNC_ILG_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x800000)|value<<23) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_ICACHE_SET_SYNC_ILG_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x800000) >> 23 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS0_ICACHE_SET_LOCK_ILG_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS0.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg)&^(0x1000000)|value<<24) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS0_ICACHE_SET_LOCK_ILG_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS0.Reg) & 0x1000000) >> 24 +} + +// EXTMEM.CACHE_DBG_STATUS1: register description +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS0_ACS_MSK_DCACHE_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS0_ACS_MSK_DCACHE_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS1_ACS_MSK_DCACHE_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS1_ACS_MSK_DCACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS2_ACS_MSK_DCACHE_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS2_ACS_MSK_DCACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS0_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS0_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS1_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS1_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS2_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS2_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS0_ACS_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS0_ACS_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS1_ACS_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS1_ACS_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS2_ACS_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS2_ACS_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS0_ACS_WB_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x1000)|value<<12) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS0_ACS_WB_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x1000) >> 12 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS1_ACS_WB_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x2000)|value<<13) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS1_ACS_WB_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x2000) >> 13 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS2_ACS_WB_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x4000)|value<<14) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS2_ACS_WB_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x4000) >> 14 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS0_ABANDON_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x10000)|value<<16) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS0_ABANDON_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x10000) >> 16 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS1_ABANDON_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x20000)|value<<17) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS1_ABANDON_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x20000) >> 17 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DBUS2_ABANDON_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x40000)|value<<18) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DBUS2_ABANDON_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x40000) >> 18 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DC_PRELOAD_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x100000)|value<<20) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DC_PRELOAD_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x100000) >> 20 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DC_PRELOAD_EVICT_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x200000)|value<<21) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DC_PRELOAD_EVICT_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x200000) >> 21 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DC_PRELOAD_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x400000)|value<<22) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DC_PRELOAD_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x400000) >> 22 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DC_SYNC_SIZE_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x800000)|value<<23) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DC_SYNC_SIZE_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x800000) >> 23 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DC_PRELOAD_SIZE_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x1000000)|value<<24) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DC_PRELOAD_SIZE_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x1000000) >> 24 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DCACHE_WRITE_FLASH_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x2000000)|value<<25) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DCACHE_WRITE_FLASH_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x2000000) >> 25 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DCACHE_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x4000000)|value<<26) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DCACHE_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x4000000) >> 26 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DCACHE_SET_PRELOAD_ILG_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x8000000)|value<<27) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DCACHE_SET_PRELOAD_ILG_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x8000000) >> 27 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DCACHE_SET_SYNC_ILG_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x10000000)|value<<28) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DCACHE_SET_SYNC_ILG_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x10000000) >> 28 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_DCACHE_SET_LOCK_ILG_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x20000000)|value<<29) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_DCACHE_SET_LOCK_ILG_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x20000000) >> 29 +} +func (o *EXTMEM_Type) SetCACHE_DBG_STATUS1_MMU_ENTRY_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_DBG_STATUS1.Reg, volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg)&^(0x40000000)|value<<30) +} +func (o *EXTMEM_Type) GetCACHE_DBG_STATUS1_MMU_ENTRY_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_DBG_STATUS1.Reg) & 0x40000000) >> 30 +} + +// EXTMEM.PRO_CACHE_ACS_CNT_CLR: register description +func (o *EXTMEM_Type) SetPRO_CACHE_ACS_CNT_CLR_PRO_DCACHE_ACS_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_ACS_CNT_CLR.Reg, volatile.LoadUint32(&o.PRO_CACHE_ACS_CNT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_CACHE_ACS_CNT_CLR_PRO_DCACHE_ACS_CNT_CLR() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_ACS_CNT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_CACHE_ACS_CNT_CLR_PRO_ICACHE_ACS_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_ACS_CNT_CLR.Reg, volatile.LoadUint32(&o.PRO_CACHE_ACS_CNT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetPRO_CACHE_ACS_CNT_CLR_PRO_ICACHE_ACS_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_ACS_CNT_CLR.Reg) & 0x2) >> 1 +} + +// EXTMEM.PRO_DCACHE_REJECT_ST: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_REJECT_ST_PRO_DCACHE_TAG_ATTR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_REJECT_ST.Reg, volatile.LoadUint32(&o.PRO_DCACHE_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_REJECT_ST_PRO_DCACHE_TAG_ATTR() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetPRO_DCACHE_REJECT_ST_PRO_DCACHE_CPU_ATTR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_REJECT_ST.Reg, volatile.LoadUint32(&o.PRO_DCACHE_REJECT_ST.Reg)&^(0x38)|value<<3) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_REJECT_ST_PRO_DCACHE_CPU_ATTR() uint32 { + return (volatile.LoadUint32(&o.PRO_DCACHE_REJECT_ST.Reg) & 0x38) >> 3 +} + +// EXTMEM.PRO_DCACHE_REJECT_VADDR: register description +func (o *EXTMEM_Type) SetPRO_DCACHE_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_DCACHE_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_REJECT_VADDR.Reg) +} + +// EXTMEM.PRO_ICACHE_REJECT_ST: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_REJECT_ST_PRO_ICACHE_TAG_ATTR(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_REJECT_ST.Reg, volatile.LoadUint32(&o.PRO_ICACHE_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_REJECT_ST_PRO_ICACHE_TAG_ATTR() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetPRO_ICACHE_REJECT_ST_PRO_ICACHE_CPU_ATTR(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_REJECT_ST.Reg, volatile.LoadUint32(&o.PRO_ICACHE_REJECT_ST.Reg)&^(0x38)|value<<3) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_REJECT_ST_PRO_ICACHE_CPU_ATTR() uint32 { + return (volatile.LoadUint32(&o.PRO_ICACHE_REJECT_ST.Reg) & 0x38) >> 3 +} + +// EXTMEM.PRO_ICACHE_REJECT_VADDR: register description +func (o *EXTMEM_Type) SetPRO_ICACHE_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_ICACHE_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_REJECT_VADDR.Reg) +} + +// EXTMEM.PRO_CACHE_MMU_FAULT_CONTENT: register description +func (o *EXTMEM_Type) SetPRO_CACHE_MMU_FAULT_CONTENT(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_MMU_FAULT_CONTENT.Reg, volatile.LoadUint32(&o.PRO_CACHE_MMU_FAULT_CONTENT.Reg)&^(0x1ffff)|value) +} +func (o *EXTMEM_Type) GetPRO_CACHE_MMU_FAULT_CONTENT() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_MMU_FAULT_CONTENT.Reg) & 0x1ffff +} +func (o *EXTMEM_Type) SetPRO_CACHE_MMU_FAULT_CONTENT_PRO_CACHE_MMU_FAULT_CODE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_MMU_FAULT_CONTENT.Reg, volatile.LoadUint32(&o.PRO_CACHE_MMU_FAULT_CONTENT.Reg)&^(0xe0000)|value<<17) +} +func (o *EXTMEM_Type) GetPRO_CACHE_MMU_FAULT_CONTENT_PRO_CACHE_MMU_FAULT_CODE() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_MMU_FAULT_CONTENT.Reg) & 0xe0000) >> 17 +} + +// EXTMEM.PRO_CACHE_MMU_FAULT_VADDR: register description +func (o *EXTMEM_Type) SetPRO_CACHE_MMU_FAULT_VADDR(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_MMU_FAULT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetPRO_CACHE_MMU_FAULT_VADDR() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_MMU_FAULT_VADDR.Reg) +} + +// EXTMEM.PRO_CACHE_WRAP_AROUND_CTRL: register description +func (o *EXTMEM_Type) SetPRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_FLASH_WRAP_AROUND(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_FLASH_WRAP_AROUND() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_WRAP_AROUND_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_SRAM_RD_WRAP_AROUND(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetPRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_SRAM_RD_WRAP_AROUND() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_WRAP_AROUND_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.PRO_CACHE_MMU_POWER_CTRL: register description +func (o *EXTMEM_Type) SetPRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_MMU_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetPRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_MMU_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetPRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_MMU_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetPRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_MMU_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetPRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.PRO_CACHE_MMU_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetPRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_MMU_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.PRO_CACHE_STATE: register description +func (o *EXTMEM_Type) SetPRO_CACHE_STATE_PRO_ICACHE_STATE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_STATE.Reg, volatile.LoadUint32(&o.PRO_CACHE_STATE.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetPRO_CACHE_STATE_PRO_ICACHE_STATE() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_STATE.Reg) & 0xfff +} +func (o *EXTMEM_Type) SetPRO_CACHE_STATE_PRO_DCACHE_STATE(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_STATE.Reg, volatile.LoadUint32(&o.PRO_CACHE_STATE.Reg)&^(0xfff000)|value<<12) +} +func (o *EXTMEM_Type) GetPRO_CACHE_STATE_PRO_DCACHE_STATE() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_STATE.Reg) & 0xfff000) >> 12 +} + +// EXTMEM.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: register description +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg) & 0x2) >> 1 +} + +// EXTMEM.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: register description +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_DB_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_BRIDGE_ARBITER_CTRL: register description +func (o *EXTMEM_Type) SetCACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER(value uint32) { + volatile.StoreUint32(&o.CACHE_BRIDGE_ARBITER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_BRIDGE_ARBITER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER() uint32 { + return volatile.LoadUint32(&o.CACHE_BRIDGE_ARBITER_CTRL.Reg) & 0x1 +} + +// EXTMEM.CACHE_PRELOAD_INT_CTRL: register description +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x20) >> 5 +} + +// EXTMEM.CACHE_SYNC_INT_CTRL: register description +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x20) >> 5 +} + +// EXTMEM.CACHE_CONF_MISC: register description +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT() uint32 { + return volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x2) >> 1 +} + +// EXTMEM.CLOCK_GATE: register description +func (o *EXTMEM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// EXTMEM.PRO_EXTMEM_REG_DATE: register description +func (o *EXTMEM_Type) SetPRO_EXTMEM_REG_DATE(value uint32) { + volatile.StoreUint32(&o.PRO_EXTMEM_REG_DATE.Reg, volatile.LoadUint32(&o.PRO_EXTMEM_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetPRO_EXTMEM_REG_DATE() uint32 { + return volatile.LoadUint32(&o.PRO_EXTMEM_REG_DATE.Reg) & 0xfffffff +} + +// General Purpose Input/Output +type GPIO_Type struct { + BT_SELECT volatile.Register32 // 0x0 + OUT volatile.Register32 // 0x4 + OUT_W1TS volatile.Register32 // 0x8 + OUT_W1TC volatile.Register32 // 0xC + OUT1 volatile.Register32 // 0x10 + OUT1_W1TS volatile.Register32 // 0x14 + OUT1_W1TC volatile.Register32 // 0x18 + SDIO_SELECT volatile.Register32 // 0x1C + ENABLE volatile.Register32 // 0x20 + ENABLE_W1TS volatile.Register32 // 0x24 + ENABLE_W1TC volatile.Register32 // 0x28 + ENABLE1 volatile.Register32 // 0x2C + ENABLE1_W1TS volatile.Register32 // 0x30 + ENABLE1_W1TC volatile.Register32 // 0x34 + STRAP volatile.Register32 // 0x38 + IN volatile.Register32 // 0x3C + IN1 volatile.Register32 // 0x40 + STATUS volatile.Register32 // 0x44 + STATUS_W1TS volatile.Register32 // 0x48 + STATUS_W1TC volatile.Register32 // 0x4C + STATUS1 volatile.Register32 // 0x50 + STATUS1_W1TS volatile.Register32 // 0x54 + STATUS1_W1TC volatile.Register32 // 0x58 + PCPU_INT volatile.Register32 // 0x5C + PCPU_NMI_INT volatile.Register32 // 0x60 + CPUSDIO_INT volatile.Register32 // 0x64 + PCPU_INT1 volatile.Register32 // 0x68 + PCPU_NMI_INT1 volatile.Register32 // 0x6C + CPUSDIO_INT1 volatile.Register32 // 0x70 + PIN0 volatile.Register32 // 0x74 + PIN1 volatile.Register32 // 0x78 + PIN2 volatile.Register32 // 0x7C + PIN3 volatile.Register32 // 0x80 + PIN4 volatile.Register32 // 0x84 + PIN5 volatile.Register32 // 0x88 + PIN6 volatile.Register32 // 0x8C + PIN7 volatile.Register32 // 0x90 + PIN8 volatile.Register32 // 0x94 + PIN9 volatile.Register32 // 0x98 + PIN10 volatile.Register32 // 0x9C + PIN11 volatile.Register32 // 0xA0 + PIN12 volatile.Register32 // 0xA4 + PIN13 volatile.Register32 // 0xA8 + PIN14 volatile.Register32 // 0xAC + PIN15 volatile.Register32 // 0xB0 + PIN16 volatile.Register32 // 0xB4 + PIN17 volatile.Register32 // 0xB8 + PIN18 volatile.Register32 // 0xBC + PIN19 volatile.Register32 // 0xC0 + PIN20 volatile.Register32 // 0xC4 + PIN21 volatile.Register32 // 0xC8 + PIN22 volatile.Register32 // 0xCC + PIN23 volatile.Register32 // 0xD0 + PIN24 volatile.Register32 // 0xD4 + PIN25 volatile.Register32 // 0xD8 + PIN26 volatile.Register32 // 0xDC + PIN27 volatile.Register32 // 0xE0 + PIN28 volatile.Register32 // 0xE4 + PIN29 volatile.Register32 // 0xE8 + PIN30 volatile.Register32 // 0xEC + PIN31 volatile.Register32 // 0xF0 + PIN32 volatile.Register32 // 0xF4 + PIN33 volatile.Register32 // 0xF8 + PIN34 volatile.Register32 // 0xFC + PIN35 volatile.Register32 // 0x100 + PIN36 volatile.Register32 // 0x104 + PIN37 volatile.Register32 // 0x108 + PIN38 volatile.Register32 // 0x10C + PIN39 volatile.Register32 // 0x110 + PIN40 volatile.Register32 // 0x114 + PIN41 volatile.Register32 // 0x118 + PIN42 volatile.Register32 // 0x11C + PIN43 volatile.Register32 // 0x120 + PIN44 volatile.Register32 // 0x124 + PIN45 volatile.Register32 // 0x128 + PIN46 volatile.Register32 // 0x12C + PIN47 volatile.Register32 // 0x130 + PIN48 volatile.Register32 // 0x134 + PIN49 volatile.Register32 // 0x138 + PIN50 volatile.Register32 // 0x13C + PIN51 volatile.Register32 // 0x140 + PIN52 volatile.Register32 // 0x144 + PIN53 volatile.Register32 // 0x148 + STATUS_NEXT volatile.Register32 // 0x14C + STATUS_NEXT1 volatile.Register32 // 0x150 + FUNC0_IN_SEL_CFG volatile.Register32 // 0x154 + FUNC1_IN_SEL_CFG volatile.Register32 // 0x158 + FUNC2_IN_SEL_CFG volatile.Register32 // 0x15C + FUNC3_IN_SEL_CFG volatile.Register32 // 0x160 + FUNC4_IN_SEL_CFG volatile.Register32 // 0x164 + FUNC5_IN_SEL_CFG volatile.Register32 // 0x168 + FUNC6_IN_SEL_CFG volatile.Register32 // 0x16C + FUNC7_IN_SEL_CFG volatile.Register32 // 0x170 + FUNC8_IN_SEL_CFG volatile.Register32 // 0x174 + FUNC9_IN_SEL_CFG volatile.Register32 // 0x178 + FUNC10_IN_SEL_CFG volatile.Register32 // 0x17C + FUNC11_IN_SEL_CFG volatile.Register32 // 0x180 + FUNC12_IN_SEL_CFG volatile.Register32 // 0x184 + FUNC13_IN_SEL_CFG volatile.Register32 // 0x188 + FUNC14_IN_SEL_CFG volatile.Register32 // 0x18C + FUNC15_IN_SEL_CFG volatile.Register32 // 0x190 + FUNC16_IN_SEL_CFG volatile.Register32 // 0x194 + FUNC17_IN_SEL_CFG volatile.Register32 // 0x198 + FUNC18_IN_SEL_CFG volatile.Register32 // 0x19C + FUNC19_IN_SEL_CFG volatile.Register32 // 0x1A0 + FUNC20_IN_SEL_CFG volatile.Register32 // 0x1A4 + FUNC21_IN_SEL_CFG volatile.Register32 // 0x1A8 + FUNC22_IN_SEL_CFG volatile.Register32 // 0x1AC + FUNC23_IN_SEL_CFG volatile.Register32 // 0x1B0 + FUNC24_IN_SEL_CFG volatile.Register32 // 0x1B4 + FUNC25_IN_SEL_CFG volatile.Register32 // 0x1B8 + FUNC26_IN_SEL_CFG volatile.Register32 // 0x1BC + FUNC27_IN_SEL_CFG volatile.Register32 // 0x1C0 + FUNC28_IN_SEL_CFG volatile.Register32 // 0x1C4 + FUNC29_IN_SEL_CFG volatile.Register32 // 0x1C8 + FUNC30_IN_SEL_CFG volatile.Register32 // 0x1CC + FUNC31_IN_SEL_CFG volatile.Register32 // 0x1D0 + FUNC32_IN_SEL_CFG volatile.Register32 // 0x1D4 + FUNC33_IN_SEL_CFG volatile.Register32 // 0x1D8 + FUNC34_IN_SEL_CFG volatile.Register32 // 0x1DC + FUNC35_IN_SEL_CFG volatile.Register32 // 0x1E0 + FUNC36_IN_SEL_CFG volatile.Register32 // 0x1E4 + FUNC37_IN_SEL_CFG volatile.Register32 // 0x1E8 + FUNC38_IN_SEL_CFG volatile.Register32 // 0x1EC + FUNC39_IN_SEL_CFG volatile.Register32 // 0x1F0 + FUNC40_IN_SEL_CFG volatile.Register32 // 0x1F4 + FUNC41_IN_SEL_CFG volatile.Register32 // 0x1F8 + FUNC42_IN_SEL_CFG volatile.Register32 // 0x1FC + FUNC43_IN_SEL_CFG volatile.Register32 // 0x200 + FUNC44_IN_SEL_CFG volatile.Register32 // 0x204 + FUNC45_IN_SEL_CFG volatile.Register32 // 0x208 + FUNC46_IN_SEL_CFG volatile.Register32 // 0x20C + FUNC47_IN_SEL_CFG volatile.Register32 // 0x210 + FUNC48_IN_SEL_CFG volatile.Register32 // 0x214 + FUNC49_IN_SEL_CFG volatile.Register32 // 0x218 + FUNC50_IN_SEL_CFG volatile.Register32 // 0x21C + FUNC51_IN_SEL_CFG volatile.Register32 // 0x220 + FUNC52_IN_SEL_CFG volatile.Register32 // 0x224 + FUNC53_IN_SEL_CFG volatile.Register32 // 0x228 + FUNC54_IN_SEL_CFG volatile.Register32 // 0x22C + FUNC55_IN_SEL_CFG volatile.Register32 // 0x230 + FUNC56_IN_SEL_CFG volatile.Register32 // 0x234 + FUNC57_IN_SEL_CFG volatile.Register32 // 0x238 + FUNC58_IN_SEL_CFG volatile.Register32 // 0x23C + FUNC59_IN_SEL_CFG volatile.Register32 // 0x240 + FUNC60_IN_SEL_CFG volatile.Register32 // 0x244 + FUNC61_IN_SEL_CFG volatile.Register32 // 0x248 + FUNC62_IN_SEL_CFG volatile.Register32 // 0x24C + FUNC63_IN_SEL_CFG volatile.Register32 // 0x250 + FUNC64_IN_SEL_CFG volatile.Register32 // 0x254 + FUNC65_IN_SEL_CFG volatile.Register32 // 0x258 + FUNC66_IN_SEL_CFG volatile.Register32 // 0x25C + FUNC67_IN_SEL_CFG volatile.Register32 // 0x260 + FUNC68_IN_SEL_CFG volatile.Register32 // 0x264 + FUNC69_IN_SEL_CFG volatile.Register32 // 0x268 + FUNC70_IN_SEL_CFG volatile.Register32 // 0x26C + FUNC71_IN_SEL_CFG volatile.Register32 // 0x270 + FUNC72_IN_SEL_CFG volatile.Register32 // 0x274 + FUNC73_IN_SEL_CFG volatile.Register32 // 0x278 + FUNC74_IN_SEL_CFG volatile.Register32 // 0x27C + FUNC75_IN_SEL_CFG volatile.Register32 // 0x280 + FUNC76_IN_SEL_CFG volatile.Register32 // 0x284 + FUNC77_IN_SEL_CFG volatile.Register32 // 0x288 + FUNC78_IN_SEL_CFG volatile.Register32 // 0x28C + FUNC79_IN_SEL_CFG volatile.Register32 // 0x290 + FUNC80_IN_SEL_CFG volatile.Register32 // 0x294 + FUNC81_IN_SEL_CFG volatile.Register32 // 0x298 + FUNC82_IN_SEL_CFG volatile.Register32 // 0x29C + FUNC83_IN_SEL_CFG volatile.Register32 // 0x2A0 + FUNC84_IN_SEL_CFG volatile.Register32 // 0x2A4 + FUNC85_IN_SEL_CFG volatile.Register32 // 0x2A8 + FUNC86_IN_SEL_CFG volatile.Register32 // 0x2AC + FUNC87_IN_SEL_CFG volatile.Register32 // 0x2B0 + FUNC88_IN_SEL_CFG volatile.Register32 // 0x2B4 + FUNC89_IN_SEL_CFG volatile.Register32 // 0x2B8 + FUNC90_IN_SEL_CFG volatile.Register32 // 0x2BC + FUNC91_IN_SEL_CFG volatile.Register32 // 0x2C0 + FUNC92_IN_SEL_CFG volatile.Register32 // 0x2C4 + FUNC93_IN_SEL_CFG volatile.Register32 // 0x2C8 + FUNC94_IN_SEL_CFG volatile.Register32 // 0x2CC + FUNC95_IN_SEL_CFG volatile.Register32 // 0x2D0 + FUNC96_IN_SEL_CFG volatile.Register32 // 0x2D4 + FUNC97_IN_SEL_CFG volatile.Register32 // 0x2D8 + FUNC98_IN_SEL_CFG volatile.Register32 // 0x2DC + FUNC99_IN_SEL_CFG volatile.Register32 // 0x2E0 + FUNC100_IN_SEL_CFG volatile.Register32 // 0x2E4 + FUNC101_IN_SEL_CFG volatile.Register32 // 0x2E8 + FUNC102_IN_SEL_CFG volatile.Register32 // 0x2EC + FUNC103_IN_SEL_CFG volatile.Register32 // 0x2F0 + FUNC104_IN_SEL_CFG volatile.Register32 // 0x2F4 + FUNC105_IN_SEL_CFG volatile.Register32 // 0x2F8 + FUNC106_IN_SEL_CFG volatile.Register32 // 0x2FC + FUNC107_IN_SEL_CFG volatile.Register32 // 0x300 + FUNC108_IN_SEL_CFG volatile.Register32 // 0x304 + FUNC109_IN_SEL_CFG volatile.Register32 // 0x308 + FUNC110_IN_SEL_CFG volatile.Register32 // 0x30C + FUNC111_IN_SEL_CFG volatile.Register32 // 0x310 + FUNC112_IN_SEL_CFG volatile.Register32 // 0x314 + FUNC113_IN_SEL_CFG volatile.Register32 // 0x318 + FUNC114_IN_SEL_CFG volatile.Register32 // 0x31C + FUNC115_IN_SEL_CFG volatile.Register32 // 0x320 + FUNC116_IN_SEL_CFG volatile.Register32 // 0x324 + FUNC117_IN_SEL_CFG volatile.Register32 // 0x328 + FUNC118_IN_SEL_CFG volatile.Register32 // 0x32C + FUNC119_IN_SEL_CFG volatile.Register32 // 0x330 + FUNC120_IN_SEL_CFG volatile.Register32 // 0x334 + FUNC121_IN_SEL_CFG volatile.Register32 // 0x338 + FUNC122_IN_SEL_CFG volatile.Register32 // 0x33C + FUNC123_IN_SEL_CFG volatile.Register32 // 0x340 + FUNC124_IN_SEL_CFG volatile.Register32 // 0x344 + FUNC125_IN_SEL_CFG volatile.Register32 // 0x348 + FUNC126_IN_SEL_CFG volatile.Register32 // 0x34C + FUNC127_IN_SEL_CFG volatile.Register32 // 0x350 + FUNC128_IN_SEL_CFG volatile.Register32 // 0x354 + FUNC129_IN_SEL_CFG volatile.Register32 // 0x358 + FUNC130_IN_SEL_CFG volatile.Register32 // 0x35C + FUNC131_IN_SEL_CFG volatile.Register32 // 0x360 + FUNC132_IN_SEL_CFG volatile.Register32 // 0x364 + FUNC133_IN_SEL_CFG volatile.Register32 // 0x368 + FUNC134_IN_SEL_CFG volatile.Register32 // 0x36C + FUNC135_IN_SEL_CFG volatile.Register32 // 0x370 + FUNC136_IN_SEL_CFG volatile.Register32 // 0x374 + FUNC137_IN_SEL_CFG volatile.Register32 // 0x378 + FUNC138_IN_SEL_CFG volatile.Register32 // 0x37C + FUNC139_IN_SEL_CFG volatile.Register32 // 0x380 + FUNC140_IN_SEL_CFG volatile.Register32 // 0x384 + FUNC141_IN_SEL_CFG volatile.Register32 // 0x388 + FUNC142_IN_SEL_CFG volatile.Register32 // 0x38C + FUNC143_IN_SEL_CFG volatile.Register32 // 0x390 + FUNC144_IN_SEL_CFG volatile.Register32 // 0x394 + FUNC145_IN_SEL_CFG volatile.Register32 // 0x398 + FUNC146_IN_SEL_CFG volatile.Register32 // 0x39C + FUNC147_IN_SEL_CFG volatile.Register32 // 0x3A0 + FUNC148_IN_SEL_CFG volatile.Register32 // 0x3A4 + FUNC149_IN_SEL_CFG volatile.Register32 // 0x3A8 + FUNC150_IN_SEL_CFG volatile.Register32 // 0x3AC + FUNC151_IN_SEL_CFG volatile.Register32 // 0x3B0 + FUNC152_IN_SEL_CFG volatile.Register32 // 0x3B4 + FUNC153_IN_SEL_CFG volatile.Register32 // 0x3B8 + FUNC154_IN_SEL_CFG volatile.Register32 // 0x3BC + FUNC155_IN_SEL_CFG volatile.Register32 // 0x3C0 + FUNC156_IN_SEL_CFG volatile.Register32 // 0x3C4 + FUNC157_IN_SEL_CFG volatile.Register32 // 0x3C8 + FUNC158_IN_SEL_CFG volatile.Register32 // 0x3CC + FUNC159_IN_SEL_CFG volatile.Register32 // 0x3D0 + FUNC160_IN_SEL_CFG volatile.Register32 // 0x3D4 + FUNC161_IN_SEL_CFG volatile.Register32 // 0x3D8 + FUNC162_IN_SEL_CFG volatile.Register32 // 0x3DC + FUNC163_IN_SEL_CFG volatile.Register32 // 0x3E0 + FUNC164_IN_SEL_CFG volatile.Register32 // 0x3E4 + FUNC165_IN_SEL_CFG volatile.Register32 // 0x3E8 + FUNC166_IN_SEL_CFG volatile.Register32 // 0x3EC + FUNC167_IN_SEL_CFG volatile.Register32 // 0x3F0 + FUNC168_IN_SEL_CFG volatile.Register32 // 0x3F4 + FUNC169_IN_SEL_CFG volatile.Register32 // 0x3F8 + FUNC170_IN_SEL_CFG volatile.Register32 // 0x3FC + FUNC171_IN_SEL_CFG volatile.Register32 // 0x400 + FUNC172_IN_SEL_CFG volatile.Register32 // 0x404 + FUNC173_IN_SEL_CFG volatile.Register32 // 0x408 + FUNC174_IN_SEL_CFG volatile.Register32 // 0x40C + FUNC175_IN_SEL_CFG volatile.Register32 // 0x410 + FUNC176_IN_SEL_CFG volatile.Register32 // 0x414 + FUNC177_IN_SEL_CFG volatile.Register32 // 0x418 + FUNC178_IN_SEL_CFG volatile.Register32 // 0x41C + FUNC179_IN_SEL_CFG volatile.Register32 // 0x420 + FUNC180_IN_SEL_CFG volatile.Register32 // 0x424 + FUNC181_IN_SEL_CFG volatile.Register32 // 0x428 + FUNC182_IN_SEL_CFG volatile.Register32 // 0x42C + FUNC183_IN_SEL_CFG volatile.Register32 // 0x430 + FUNC184_IN_SEL_CFG volatile.Register32 // 0x434 + FUNC185_IN_SEL_CFG volatile.Register32 // 0x438 + FUNC186_IN_SEL_CFG volatile.Register32 // 0x43C + FUNC187_IN_SEL_CFG volatile.Register32 // 0x440 + FUNC188_IN_SEL_CFG volatile.Register32 // 0x444 + FUNC189_IN_SEL_CFG volatile.Register32 // 0x448 + FUNC190_IN_SEL_CFG volatile.Register32 // 0x44C + FUNC191_IN_SEL_CFG volatile.Register32 // 0x450 + FUNC192_IN_SEL_CFG volatile.Register32 // 0x454 + FUNC193_IN_SEL_CFG volatile.Register32 // 0x458 + FUNC194_IN_SEL_CFG volatile.Register32 // 0x45C + FUNC195_IN_SEL_CFG volatile.Register32 // 0x460 + FUNC196_IN_SEL_CFG volatile.Register32 // 0x464 + FUNC197_IN_SEL_CFG volatile.Register32 // 0x468 + FUNC198_IN_SEL_CFG volatile.Register32 // 0x46C + FUNC199_IN_SEL_CFG volatile.Register32 // 0x470 + FUNC200_IN_SEL_CFG volatile.Register32 // 0x474 + FUNC201_IN_SEL_CFG volatile.Register32 // 0x478 + FUNC202_IN_SEL_CFG volatile.Register32 // 0x47C + FUNC203_IN_SEL_CFG volatile.Register32 // 0x480 + FUNC204_IN_SEL_CFG volatile.Register32 // 0x484 + FUNC205_IN_SEL_CFG volatile.Register32 // 0x488 + FUNC206_IN_SEL_CFG volatile.Register32 // 0x48C + FUNC207_IN_SEL_CFG volatile.Register32 // 0x490 + FUNC208_IN_SEL_CFG volatile.Register32 // 0x494 + FUNC209_IN_SEL_CFG volatile.Register32 // 0x498 + FUNC210_IN_SEL_CFG volatile.Register32 // 0x49C + FUNC211_IN_SEL_CFG volatile.Register32 // 0x4A0 + FUNC212_IN_SEL_CFG volatile.Register32 // 0x4A4 + FUNC213_IN_SEL_CFG volatile.Register32 // 0x4A8 + FUNC214_IN_SEL_CFG volatile.Register32 // 0x4AC + FUNC215_IN_SEL_CFG volatile.Register32 // 0x4B0 + FUNC216_IN_SEL_CFG volatile.Register32 // 0x4B4 + FUNC217_IN_SEL_CFG volatile.Register32 // 0x4B8 + FUNC218_IN_SEL_CFG volatile.Register32 // 0x4BC + FUNC219_IN_SEL_CFG volatile.Register32 // 0x4C0 + FUNC220_IN_SEL_CFG volatile.Register32 // 0x4C4 + FUNC221_IN_SEL_CFG volatile.Register32 // 0x4C8 + FUNC222_IN_SEL_CFG volatile.Register32 // 0x4CC + FUNC223_IN_SEL_CFG volatile.Register32 // 0x4D0 + FUNC224_IN_SEL_CFG volatile.Register32 // 0x4D4 + FUNC225_IN_SEL_CFG volatile.Register32 // 0x4D8 + FUNC226_IN_SEL_CFG volatile.Register32 // 0x4DC + FUNC227_IN_SEL_CFG volatile.Register32 // 0x4E0 + FUNC228_IN_SEL_CFG volatile.Register32 // 0x4E4 + FUNC229_IN_SEL_CFG volatile.Register32 // 0x4E8 + FUNC230_IN_SEL_CFG volatile.Register32 // 0x4EC + FUNC231_IN_SEL_CFG volatile.Register32 // 0x4F0 + FUNC232_IN_SEL_CFG volatile.Register32 // 0x4F4 + FUNC233_IN_SEL_CFG volatile.Register32 // 0x4F8 + FUNC234_IN_SEL_CFG volatile.Register32 // 0x4FC + FUNC235_IN_SEL_CFG volatile.Register32 // 0x500 + FUNC236_IN_SEL_CFG volatile.Register32 // 0x504 + FUNC237_IN_SEL_CFG volatile.Register32 // 0x508 + FUNC238_IN_SEL_CFG volatile.Register32 // 0x50C + FUNC239_IN_SEL_CFG volatile.Register32 // 0x510 + FUNC240_IN_SEL_CFG volatile.Register32 // 0x514 + FUNC241_IN_SEL_CFG volatile.Register32 // 0x518 + FUNC242_IN_SEL_CFG volatile.Register32 // 0x51C + FUNC243_IN_SEL_CFG volatile.Register32 // 0x520 + FUNC244_IN_SEL_CFG volatile.Register32 // 0x524 + FUNC245_IN_SEL_CFG volatile.Register32 // 0x528 + FUNC246_IN_SEL_CFG volatile.Register32 // 0x52C + FUNC247_IN_SEL_CFG volatile.Register32 // 0x530 + FUNC248_IN_SEL_CFG volatile.Register32 // 0x534 + FUNC249_IN_SEL_CFG volatile.Register32 // 0x538 + FUNC250_IN_SEL_CFG volatile.Register32 // 0x53C + FUNC251_IN_SEL_CFG volatile.Register32 // 0x540 + FUNC252_IN_SEL_CFG volatile.Register32 // 0x544 + FUNC253_IN_SEL_CFG volatile.Register32 // 0x548 + FUNC254_IN_SEL_CFG volatile.Register32 // 0x54C + FUNC255_IN_SEL_CFG volatile.Register32 // 0x550 + FUNC0_OUT_SEL_CFG volatile.Register32 // 0x554 + FUNC1_OUT_SEL_CFG volatile.Register32 // 0x558 + FUNC2_OUT_SEL_CFG volatile.Register32 // 0x55C + FUNC3_OUT_SEL_CFG volatile.Register32 // 0x560 + FUNC4_OUT_SEL_CFG volatile.Register32 // 0x564 + FUNC5_OUT_SEL_CFG volatile.Register32 // 0x568 + FUNC6_OUT_SEL_CFG volatile.Register32 // 0x56C + FUNC7_OUT_SEL_CFG volatile.Register32 // 0x570 + FUNC8_OUT_SEL_CFG volatile.Register32 // 0x574 + FUNC9_OUT_SEL_CFG volatile.Register32 // 0x578 + FUNC10_OUT_SEL_CFG volatile.Register32 // 0x57C + FUNC11_OUT_SEL_CFG volatile.Register32 // 0x580 + FUNC12_OUT_SEL_CFG volatile.Register32 // 0x584 + FUNC13_OUT_SEL_CFG volatile.Register32 // 0x588 + FUNC14_OUT_SEL_CFG volatile.Register32 // 0x58C + FUNC15_OUT_SEL_CFG volatile.Register32 // 0x590 + FUNC16_OUT_SEL_CFG volatile.Register32 // 0x594 + FUNC17_OUT_SEL_CFG volatile.Register32 // 0x598 + FUNC18_OUT_SEL_CFG volatile.Register32 // 0x59C + FUNC19_OUT_SEL_CFG volatile.Register32 // 0x5A0 + FUNC20_OUT_SEL_CFG volatile.Register32 // 0x5A4 + FUNC21_OUT_SEL_CFG volatile.Register32 // 0x5A8 + FUNC22_OUT_SEL_CFG volatile.Register32 // 0x5AC + FUNC23_OUT_SEL_CFG volatile.Register32 // 0x5B0 + FUNC24_OUT_SEL_CFG volatile.Register32 // 0x5B4 + FUNC25_OUT_SEL_CFG volatile.Register32 // 0x5B8 + FUNC26_OUT_SEL_CFG volatile.Register32 // 0x5BC + FUNC27_OUT_SEL_CFG volatile.Register32 // 0x5C0 + FUNC28_OUT_SEL_CFG volatile.Register32 // 0x5C4 + FUNC29_OUT_SEL_CFG volatile.Register32 // 0x5C8 + FUNC30_OUT_SEL_CFG volatile.Register32 // 0x5CC + FUNC31_OUT_SEL_CFG volatile.Register32 // 0x5D0 + FUNC32_OUT_SEL_CFG volatile.Register32 // 0x5D4 + FUNC33_OUT_SEL_CFG volatile.Register32 // 0x5D8 + FUNC34_OUT_SEL_CFG volatile.Register32 // 0x5DC + FUNC35_OUT_SEL_CFG volatile.Register32 // 0x5E0 + FUNC36_OUT_SEL_CFG volatile.Register32 // 0x5E4 + FUNC37_OUT_SEL_CFG volatile.Register32 // 0x5E8 + FUNC38_OUT_SEL_CFG volatile.Register32 // 0x5EC + FUNC39_OUT_SEL_CFG volatile.Register32 // 0x5F0 + FUNC40_OUT_SEL_CFG volatile.Register32 // 0x5F4 + FUNC41_OUT_SEL_CFG volatile.Register32 // 0x5F8 + FUNC42_OUT_SEL_CFG volatile.Register32 // 0x5FC + FUNC43_OUT_SEL_CFG volatile.Register32 // 0x600 + FUNC44_OUT_SEL_CFG volatile.Register32 // 0x604 + FUNC45_OUT_SEL_CFG volatile.Register32 // 0x608 + FUNC46_OUT_SEL_CFG volatile.Register32 // 0x60C + FUNC47_OUT_SEL_CFG volatile.Register32 // 0x610 + FUNC48_OUT_SEL_CFG volatile.Register32 // 0x614 + FUNC49_OUT_SEL_CFG volatile.Register32 // 0x618 + FUNC50_OUT_SEL_CFG volatile.Register32 // 0x61C + FUNC51_OUT_SEL_CFG volatile.Register32 // 0x620 + FUNC52_OUT_SEL_CFG volatile.Register32 // 0x624 + FUNC53_OUT_SEL_CFG volatile.Register32 // 0x628 + CLOCK_GATE volatile.Register32 // 0x62C + _ [204]byte + REG_DATE volatile.Register32 // 0x6FC +} + +// GPIO.BT_SELECT: GPIO bit select register +func (o *GPIO_Type) SetBT_SELECT(value uint32) { + volatile.StoreUint32(&o.BT_SELECT.Reg, value) +} +func (o *GPIO_Type) GetBT_SELECT() uint32 { + return volatile.LoadUint32(&o.BT_SELECT.Reg) +} + +// GPIO.OUT: GPIO0 ~ 31 output register +func (o *GPIO_Type) SetOUT(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, value) +} +func (o *GPIO_Type) GetOUT() uint32 { + return volatile.LoadUint32(&o.OUT.Reg) +} + +// GPIO.OUT_W1TS: GPIO0 ~ 31 output bit set register +func (o *GPIO_Type) SetOUT_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_W1TS.Reg) +} + +// GPIO.OUT_W1TC: GPIO0 ~ 31 output bit clear register +func (o *GPIO_Type) SetOUT_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_W1TC.Reg) +} + +// GPIO.OUT1: GPIO32 ~ 53 output register +func (o *GPIO_Type) SetOUT1_DATA_ORIG(value uint32) { + volatile.StoreUint32(&o.OUT1.Reg, volatile.LoadUint32(&o.OUT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetOUT1_DATA_ORIG() uint32 { + return volatile.LoadUint32(&o.OUT1.Reg) & 0x3fffff +} + +// GPIO.OUT1_W1TS: GPIO32 ~ 53 output bit set register +func (o *GPIO_Type) SetOUT1_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TS.Reg, volatile.LoadUint32(&o.OUT1_W1TS.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetOUT1_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TS.Reg) & 0x3fffff +} + +// GPIO.OUT1_W1TC: GPIO32 ~ 53 output bit clear register +func (o *GPIO_Type) SetOUT1_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TC.Reg, volatile.LoadUint32(&o.OUT1_W1TC.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetOUT1_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TC.Reg) & 0x3fffff +} + +// GPIO.SDIO_SELECT: GPIO SDIO selection register +func (o *GPIO_Type) SetSDIO_SELECT_SDIO_SEL(value uint32) { + volatile.StoreUint32(&o.SDIO_SELECT.Reg, volatile.LoadUint32(&o.SDIO_SELECT.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSDIO_SELECT_SDIO_SEL() uint32 { + return volatile.LoadUint32(&o.SDIO_SELECT.Reg) & 0xff +} + +// GPIO.ENABLE: GPIO0 ~ 31 output enable register +func (o *GPIO_Type) SetENABLE(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, value) +} +func (o *GPIO_Type) GetENABLE() uint32 { + return volatile.LoadUint32(&o.ENABLE.Reg) +} + +// GPIO.ENABLE_W1TS: GPIO0 ~ 31 output enable bit set register +func (o *GPIO_Type) SetENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) +} + +// GPIO.ENABLE_W1TC: GPIO0 ~ 31 output enable bit clear register +func (o *GPIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) +} + +// GPIO.ENABLE1: GPIO32 ~ 53 output enable register +func (o *GPIO_Type) SetENABLE1_DATA(value uint32) { + volatile.StoreUint32(&o.ENABLE1.Reg, volatile.LoadUint32(&o.ENABLE1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetENABLE1_DATA() uint32 { + return volatile.LoadUint32(&o.ENABLE1.Reg) & 0x3fffff +} + +// GPIO.ENABLE1_W1TS: GPIO32 ~ 53 output enable bit set register +func (o *GPIO_Type) SetENABLE1_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TS.Reg, volatile.LoadUint32(&o.ENABLE1_W1TS.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TS.Reg) & 0x3fffff +} + +// GPIO.ENABLE1_W1TC: GPIO32 ~ 53 output enable bit clear register +func (o *GPIO_Type) SetENABLE1_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TC.Reg, volatile.LoadUint32(&o.ENABLE1_W1TC.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TC.Reg) & 0x3fffff +} + +// GPIO.STRAP: Bootstrap pin value register +func (o *GPIO_Type) SetSTRAP_STRAPPING(value uint32) { + volatile.StoreUint32(&o.STRAP.Reg, volatile.LoadUint32(&o.STRAP.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetSTRAP_STRAPPING() uint32 { + return volatile.LoadUint32(&o.STRAP.Reg) & 0xffff +} + +// GPIO.IN: GPIO0 ~ 31 input register +func (o *GPIO_Type) SetIN(value uint32) { + volatile.StoreUint32(&o.IN.Reg, value) +} +func (o *GPIO_Type) GetIN() uint32 { + return volatile.LoadUint32(&o.IN.Reg) +} + +// GPIO.IN1: GPIO32 ~ 53 input register +func (o *GPIO_Type) SetIN1_IN_DATA1_NEXT(value uint32) { + volatile.StoreUint32(&o.IN1.Reg, volatile.LoadUint32(&o.IN1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetIN1_IN_DATA1_NEXT() uint32 { + return volatile.LoadUint32(&o.IN1.Reg) & 0x3fffff +} + +// GPIO.STATUS: GPIO0 ~ 31 interrupt status register +func (o *GPIO_Type) SetSTATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) +} + +// GPIO.STATUS_W1TS: GPIO0 ~ 31 interrupt status bit set register +func (o *GPIO_Type) SetSTATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) +} + +// GPIO.STATUS_W1TC: GPIO0 ~ 31 interrupt status bit clear register +func (o *GPIO_Type) SetSTATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) +} + +// GPIO.STATUS1: GPIO32 ~ 53 interrupt status register +func (o *GPIO_Type) SetSTATUS1_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.STATUS1.Reg, volatile.LoadUint32(&o.STATUS1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetSTATUS1_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.STATUS1.Reg) & 0x3fffff +} + +// GPIO.STATUS1_W1TS: GPIO32 ~ 53 interrupt status bit set register +func (o *GPIO_Type) SetSTATUS1_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TS.Reg, volatile.LoadUint32(&o.STATUS1_W1TS.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TS.Reg) & 0x3fffff +} + +// GPIO.STATUS1_W1TC: GPIO32 ~ 53 interrupt status bit clear register +func (o *GPIO_Type) SetSTATUS1_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TC.Reg, volatile.LoadUint32(&o.STATUS1_W1TC.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TC.Reg) & 0x3fffff +} + +// GPIO.PCPU_INT: GPIO0 ~ 31 PRO_CPU interrupt status register +func (o *GPIO_Type) SetPCPU_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_INT.Reg) +} + +// GPIO.PCPU_NMI_INT: GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register +func (o *GPIO_Type) SetPCPU_NMI_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT.Reg) +} + +// GPIO.CPUSDIO_INT: GPIO0 ~ 31 CPU SDIO interrupt status register +func (o *GPIO_Type) SetCPUSDIO_INT(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT.Reg, value) +} +func (o *GPIO_Type) GetCPUSDIO_INT() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT.Reg) +} + +// GPIO.PCPU_INT1: GPIO32 ~ 53 PRO_CPU interrupt status register +func (o *GPIO_Type) SetPCPU_INT1_PROCPU1_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_INT1.Reg, volatile.LoadUint32(&o.PCPU_INT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetPCPU_INT1_PROCPU1_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_INT1.Reg) & 0x3fffff +} + +// GPIO.PCPU_NMI_INT1: GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register +func (o *GPIO_Type) SetPCPU_NMI_INT1_PROCPU_NMI1_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT1.Reg, volatile.LoadUint32(&o.PCPU_NMI_INT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT1_PROCPU_NMI1_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT1.Reg) & 0x3fffff +} + +// GPIO.CPUSDIO_INT1: GPIO32 ~ 53 CPU SDIO interrupt status register +func (o *GPIO_Type) SetCPUSDIO_INT1_SDIO1_INT(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT1.Reg, volatile.LoadUint32(&o.CPUSDIO_INT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetCPUSDIO_INT1_SDIO1_INT() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT1.Reg) & 0x3fffff +} + +// GPIO.PIN0: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN0_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN0_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN0_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN0_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN0_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN0_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN1: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN1_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN1_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN1_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN1_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN1_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN1_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN2: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN2_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN2_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN2_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN2_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN2_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN2_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN3: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN3_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN3_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN3_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN3_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN3_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN3_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN4: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN4_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN4_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN4_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN4_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN4_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN4_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN5: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN5_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN5_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN5_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN5_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN5_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN5_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN6: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN6_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN6_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN6_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN6_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN6_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN6_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN7: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN7_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN7_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN7_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN7_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN7_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN7_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN8: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN8_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN8_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN8.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN8_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN8_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN8_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN8_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN9: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN9_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN9_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN9.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN9_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN9_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN9_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN9_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN10: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN10_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN10_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN10.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN10_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN10_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN10_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN10_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN10_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN10_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN11: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN11_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN11_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN11.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN11_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN11_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN11_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN11_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN11_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN11_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN12: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN12_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN12_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN12.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN12_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN12_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN12_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN12_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN12_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN12_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN13: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN13_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN13_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN13.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN13_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN13_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN13_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN13_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN13_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN13_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN14: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN14_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN14_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN14.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN14_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN14_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN14_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN14_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN14_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN14_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN15: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN15_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN15_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN15.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN15_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN15_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN15_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN15_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN15_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN15_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN16: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN16_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN16_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN16.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN16_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN16_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN16_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN16_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN16_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN16_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN17: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN17_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN17_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN17.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN17_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN17_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN17_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN17_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN17_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN17_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN18: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN18_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN18_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN18.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN18_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN18_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN18_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN18_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN18_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN18_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN19: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN19_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN19_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN19.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN19_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN19_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN19_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN19_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN19_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN19_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN20: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN20_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN20_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN20.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN20_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN20_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN20_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN20_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN20_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN20_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN21: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN21_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN21_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN21.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN21_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN21_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN21_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN21_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN21_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN21_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN22: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN22_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN22_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN22.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN22_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN22_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN22_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN22_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN22_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN22_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN22_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN22_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN22_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN22_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN22_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN22_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN23: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN23_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN23_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN23.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN23_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN23_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN23_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN23_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN23_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN23_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN23_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN23_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN23_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN23_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN23_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN23_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN24: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN24_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN24_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN24.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN24_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN24_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN24_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN24_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN24_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN24_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN24_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN24_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN24_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN24_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN24_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN24_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN25: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN25_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN25_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN25.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN25_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN25_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN25_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN25_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN25_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN25_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN25_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN25_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN25_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN25_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN25_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN25_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN26: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN26_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN26_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN26.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN26_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN26_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN26_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN26_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN26_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN26_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN26_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN26_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN26_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN26_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN26_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN26_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN27: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN27_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN27_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN27.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN27_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN27_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN27_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN27_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN27_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN27_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN27_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN27_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN27_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN27_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN27_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN27_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN28: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN28_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN28_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN28.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN28_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN28_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN28_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN28_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN28_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN28_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN28_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN28_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN28_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN28_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN28_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN28_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN29: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN29_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN29_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN29.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN29_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN29_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN29_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN29_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN29_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN29_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN29_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN29_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN29_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN29_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN29_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN29_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN30: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN30_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN30_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN30.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN30_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN30_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN30_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN30_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN30_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN30_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN30_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN30_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN30_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN30_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN30_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN30_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN31: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN31_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN31_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN31.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN31_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN31_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN31_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN31_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN31_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN31_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN31_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN31_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN31_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN31_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN31_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN31_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN32: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN32_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN32_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN32.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN32_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN32_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN32_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN32_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN32_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN32_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN32_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN32_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN32_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN32_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN32_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN32_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN33: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN33_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN33_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN33.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN33_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN33_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN33_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN33_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN33_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN33_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN33_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN33_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN33_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN33_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN33_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN33_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN34: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN34_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN34_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN34.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN34_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN34_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN34_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN34_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN34_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN34_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN34_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN34_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN34_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN34_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN34_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN34_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN35: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN35_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN35_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN35.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN35_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN35_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN35_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN35_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN35_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN35_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN35_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN35_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN35_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN35_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN35_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN35_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN36: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN36_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN36_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN36.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN36_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN36_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN36_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN36_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN36_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN36_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN36_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN36_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN36_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN36_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN36_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN36_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN37: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN37_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN37_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN37.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN37_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN37_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN37_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN37_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN37_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN37_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN37_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN37_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN37_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN37_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN37_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN37_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN38: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN38_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN38_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN38.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN38_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN38_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN38_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN38_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN38_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN38_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN38_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN38_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN38_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN38_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN38_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN38_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN39: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN39_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN39_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN39.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN39_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN39_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN39_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN39_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN39_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN39_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN39_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN39_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN39_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN39_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN39_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN39_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN40: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN40_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN40_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN40.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN40_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN40_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN40_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN40_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN40_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN40_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN40_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN40_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN40_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN40_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN40_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN40_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN41: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN41_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN41_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN41.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN41_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN41_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN41_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN41_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN41_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN41_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN41_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN41_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN41_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN41_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN41_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN41_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN42: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN42_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN42_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN42.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN42_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN42_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN42_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN42_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN42_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN42_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN42_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN42_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN42_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN42_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN42_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN42_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN43: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN43_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN43_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN43.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN43_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN43_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN43_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN43_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN43_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN43_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN43_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN43_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN43_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN43_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN43_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN43_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN44: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN44_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN44_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN44.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN44_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN44_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN44_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN44_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN44_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN44_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN44_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN44_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN44_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN44_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN44_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN44_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN45: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN45_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN45_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN45.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN45_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN45_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN45_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN45_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN45_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN45_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN45_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN45_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN45_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN45_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN45_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN45_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN46: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN46_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN46_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN46.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN46_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN46_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN46_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN46_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN46_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN46_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN46_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN46_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN46_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN46_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN46_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN46_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN47: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN47_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN47_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN47.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN47_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN47_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN47_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN47_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN47_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN47_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN47_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN47_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN47_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN47_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN47_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN47_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN48: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN48_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN48_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN48.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN48_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN48_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN48_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN48_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN48_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN48_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN48_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN48_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN48_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN48_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN48_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN48_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN49: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN49_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN49_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN49.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN49_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN49_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN49_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN49_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN49_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN49_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN49_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN49_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN49_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN49_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN49_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN49_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN50: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN50_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN50_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN50.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN50_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN50_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN50_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN50_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN50_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN50_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN50_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN50_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN50_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN50_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN50_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN50_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN51: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN51_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN51_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN51.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN51_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN51_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN51_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN51_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN51_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN51_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN51_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN51_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN51_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN51_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN51_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN51_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN52: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN52_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN52_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN52.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN52_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN52_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN52_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN52_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN52_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN52_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN52_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN52_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN52_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN52_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN52_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN52_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN53: Configuration for GPIO pin %s +func (o *GPIO_Type) SetPIN53_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN53_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN53.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN53_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN53_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN53_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN53_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN53_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN53_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN53_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN53_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN53_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN53_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN53_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN53_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x3e000) >> 13 +} + +// GPIO.STATUS_NEXT: GPIO0 ~ 31 interrupt source register +func (o *GPIO_Type) SetSTATUS_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT.Reg) +} + +// GPIO.STATUS_NEXT1: GPIO32 ~ 53 interrupt source register +func (o *GPIO_Type) SetSTATUS_NEXT1_STATUS1_INTERRUPT_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT1.Reg, volatile.LoadUint32(&o.STATUS_NEXT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetSTATUS_NEXT1_STATUS1_INTERRUPT_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT1.Reg) & 0x3fffff +} + +// GPIO.FUNC0_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC1_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC2_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC3_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC4_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC5_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC6_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC7_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC8_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC9_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC10_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC11_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC12_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC13_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC14_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC15_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC16_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC17_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC18_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC19_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC20_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC21_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC22_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC23_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC24_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC25_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC26_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC27_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC28_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC29_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC30_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC31_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC32_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC33_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC34_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC35_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC36_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC37_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC38_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC39_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC40_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC41_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC42_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC43_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC44_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC45_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC46_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC47_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC48_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC49_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC50_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC51_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC52_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC53_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC54_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC55_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC56_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC57_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC58_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC59_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC60_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC61_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC62_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC63_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC64_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC65_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC66_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC67_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC68_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC69_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC70_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC71_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC72_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC73_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC74_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC75_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC76_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC77_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC78_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC79_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC80_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC81_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC82_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC83_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC84_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC85_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC86_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC87_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC88_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC89_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC90_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC91_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC92_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC93_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC94_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC95_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC96_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC97_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC98_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC99_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC100_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC101_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC102_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC103_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC104_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC105_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC106_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC107_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC108_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC109_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC110_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC111_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC112_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC113_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC114_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC115_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC116_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC117_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC118_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC119_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC120_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC121_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC122_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC123_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC124_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC125_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC126_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC127_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC128_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC129_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC130_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC131_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC132_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC133_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC134_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC135_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC136_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC137_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC138_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC139_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC140_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC141_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC142_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC143_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC144_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC145_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC146_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC147_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC148_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC149_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC150_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC151_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC152_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC153_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC154_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC155_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC156_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC157_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC158_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC159_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC160_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC161_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC162_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC163_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC164_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC165_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC166_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC167_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC168_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC169_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC170_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC171_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC172_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC173_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC174_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC175_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC176_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC177_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC178_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC179_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC180_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC181_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC182_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC183_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC184_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC185_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC186_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC187_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC188_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC189_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC190_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC191_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC192_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC193_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC194_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC195_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC196_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC197_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC198_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC199_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC200_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC201_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC202_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC203_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC204_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC205_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC206_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC207_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC208_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC209_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC210_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC211_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC212_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC213_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC214_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC215_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC216_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC217_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC218_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC219_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC220_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC221_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC222_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC223_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC224_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC225_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC226_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC227_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC228_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC229_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC230_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC231_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC232_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC233_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC234_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC235_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC236_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC237_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC238_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC239_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC240_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC241_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC242_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC243_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC244_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC245_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC246_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC247_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC248_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC249_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC250_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC251_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC252_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC253_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC254_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC255_IN_SEL_CFG: Peripheral function %s input selection register +func (o *GPIO_Type) SetFUNC255_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC255_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC255_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC255_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC255_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC255_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC255_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC255_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC255_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC0_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC1_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC2_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC3_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC4_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC5_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC6_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC7_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC8_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC9_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC10_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC11_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC12_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC13_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC14_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC15_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC16_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC17_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC18_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC19_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC20_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC21_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC22_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC23_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC24_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC25_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC26_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC27_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC28_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC29_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC30_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC31_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC32_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC33_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC34_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC35_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC36_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC37_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC38_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC39_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC40_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC41_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC42_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC43_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC44_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC45_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC46_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC47_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC48_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC49_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC50_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC51_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC52_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC53_OUT_SEL_CFG: Peripheral output selection for GPIO %s +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.CLOCK_GATE: GPIO clock gating register +func (o *GPIO_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIO.REG_DATE: Version control register +func (o *GPIO_Type) SetREG_DATE_DATE(value uint32) { + volatile.StoreUint32(&o.REG_DATE.Reg, volatile.LoadUint32(&o.REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *GPIO_Type) GetREG_DATE_DATE() uint32 { + return volatile.LoadUint32(&o.REG_DATE.Reg) & 0xfffffff +} + +// Sigma-Delta Modulation +type GPIOSD_Type struct { + SIGMADELTA0 volatile.Register32 // 0x0 + SIGMADELTA1 volatile.Register32 // 0x4 + SIGMADELTA2 volatile.Register32 // 0x8 + SIGMADELTA3 volatile.Register32 // 0xC + SIGMADELTA4 volatile.Register32 // 0x10 + SIGMADELTA5 volatile.Register32 // 0x14 + SIGMADELTA6 volatile.Register32 // 0x18 + SIGMADELTA7 volatile.Register32 // 0x1C + SIGMADELTA_CG volatile.Register32 // 0x20 + SIGMADELTA_MISC volatile.Register32 // 0x24 + SIGMADELTA_VERSION volatile.Register32 // 0x28 +} + +// GPIOSD.SIGMADELTA0: Duty-cycle configuration register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA0_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA0_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA1: Duty-cycle configuration register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA1_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA1_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA2: Duty-cycle configuration register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA2_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA2_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA3: Duty-cycle configuration register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA3_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA3_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA4: Duty-cycle configuration register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA4_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA4_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA4_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA4_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA5: Duty-cycle configuration register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA5_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA5_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA5_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA5_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA6: Duty-cycle configuration register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA6_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA6_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA6_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA6_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA7: Duty-cycle configuration register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA7_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA7_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA7_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA7_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA_CG: Clock gating configuration register +func (o *GPIOSD_Type) SetSIGMADELTA_CG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_CG.Reg, volatile.LoadUint32(&o.SIGMADELTA_CG.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIOSD_Type) GetSIGMADELTA_CG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_CG.Reg) & 0x80000000) >> 31 +} + +// GPIOSD.SIGMADELTA_MISC: MISC register +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_FUNCTION_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_FUNCTION_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x40000000) >> 30 +} +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_SPI_SWAP(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_SPI_SWAP() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x80000000) >> 31 +} + +// GPIOSD.SIGMADELTA_VERSION: Version control register +func (o *GPIOSD_Type) SetSIGMADELTA_VERSION_GPIO_SD_DATE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_VERSION.Reg, volatile.LoadUint32(&o.SIGMADELTA_VERSION.Reg)&^(0xfffffff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA_VERSION_GPIO_SD_DATE() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA_VERSION.Reg) & 0xfffffff +} + +// HMAC (Hash-based Message Authentication Code) Accelerator +type HMAC_Type struct { + _ [64]byte + SET_START volatile.Register32 // 0x40 + SET_PARA_PURPOSE volatile.Register32 // 0x44 + SET_PARA_KEY volatile.Register32 // 0x48 + SET_PARA_FINISH volatile.Register32 // 0x4C + SET_MESSAGE_ONE volatile.Register32 // 0x50 + SET_MESSAGE_ING volatile.Register32 // 0x54 + SET_MESSAGE_END volatile.Register32 // 0x58 + SET_RESULT_FINISH volatile.Register32 // 0x5C + SET_INVALIDATE_JTAG volatile.Register32 // 0x60 + SET_INVALIDATE_DS volatile.Register32 // 0x64 + QUERY_ERROR volatile.Register32 // 0x68 + QUERY_BUSY volatile.Register32 // 0x6C + _ [16]byte + WR_MESSAGE_0 volatile.Register32 // 0x80 + WR_MESSAGE_1 volatile.Register32 // 0x84 + WR_MESSAGE_2 volatile.Register32 // 0x88 + WR_MESSAGE_3 volatile.Register32 // 0x8C + WR_MESSAGE_4 volatile.Register32 // 0x90 + WR_MESSAGE_5 volatile.Register32 // 0x94 + WR_MESSAGE_6 volatile.Register32 // 0x98 + WR_MESSAGE_7 volatile.Register32 // 0x9C + WR_MESSAGE_8 volatile.Register32 // 0xA0 + WR_MESSAGE_9 volatile.Register32 // 0xA4 + WR_MESSAGE_10 volatile.Register32 // 0xA8 + WR_MESSAGE_11 volatile.Register32 // 0xAC + WR_MESSAGE_12 volatile.Register32 // 0xB0 + WR_MESSAGE_13 volatile.Register32 // 0xB4 + WR_MESSAGE_14 volatile.Register32 // 0xB8 + WR_MESSAGE_15 volatile.Register32 // 0xBC + RD_RESULT_0 volatile.Register32 // 0xC0 + RD_RESULT_1 volatile.Register32 // 0xC4 + RD_RESULT_2 volatile.Register32 // 0xC8 + RD_RESULT_3 volatile.Register32 // 0xCC + RD_RESULT_4 volatile.Register32 // 0xD0 + RD_RESULT_5 volatile.Register32 // 0xD4 + RD_RESULT_6 volatile.Register32 // 0xD8 + RD_RESULT_7 volatile.Register32 // 0xDC + _ [16]byte + SET_MESSAGE_PAD volatile.Register32 // 0xF0 + ONE_BLOCK volatile.Register32 // 0xF4 + DATE volatile.Register32 // 0xF8 +} + +// HMAC.SET_START: HMAC start control register +func (o *HMAC_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// HMAC.SET_PARA_PURPOSE: HMAC parameter configuration register +func (o *HMAC_Type) SetSET_PARA_PURPOSE_PURPOSE_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_PURPOSE.Reg, volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg)&^(0xf)|value) +} +func (o *HMAC_Type) GetSET_PARA_PURPOSE_PURPOSE_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg) & 0xf +} + +// HMAC.SET_PARA_KEY: HMAC key configuration register +func (o *HMAC_Type) SetSET_PARA_KEY_KEY_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_KEY.Reg, volatile.LoadUint32(&o.SET_PARA_KEY.Reg)&^(0x7)|value) +} +func (o *HMAC_Type) GetSET_PARA_KEY_KEY_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_KEY.Reg) & 0x7 +} + +// HMAC.SET_PARA_FINISH: HMAC configuration completion register +func (o *HMAC_Type) SetSET_PARA_FINISH_SET_PARA_END(value uint32) { + volatile.StoreUint32(&o.SET_PARA_FINISH.Reg, volatile.LoadUint32(&o.SET_PARA_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_PARA_FINISH_SET_PARA_END() uint32 { + return volatile.LoadUint32(&o.SET_PARA_FINISH.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ONE: HMAC one message control register +func (o *HMAC_Type) SetSET_MESSAGE_ONE_SET_TEXT_ONE(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ONE.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ONE_SET_TEXT_ONE() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ING: HMAC message continue register +func (o *HMAC_Type) SetSET_MESSAGE_ING_SET_TEXT_ING(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ING.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ING_SET_TEXT_ING() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_END: HMAC message end register +func (o *HMAC_Type) SetSET_MESSAGE_END_SET_TEXT_END(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_END.Reg, volatile.LoadUint32(&o.SET_MESSAGE_END.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_END_SET_TEXT_END() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_END.Reg) & 0x1 +} + +// HMAC.SET_RESULT_FINISH: HMAC read result completion register +func (o *HMAC_Type) SetSET_RESULT_FINISH_SET_RESULT_END(value uint32) { + volatile.StoreUint32(&o.SET_RESULT_FINISH.Reg, volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_RESULT_FINISH_SET_RESULT_END() uint32 { + return volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_JTAG: Invalidate JTAG result register +func (o *HMAC_Type) SetSET_INVALIDATE_JTAG(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_JTAG.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_JTAG() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_DS: Invalidate digital signature result register +func (o *HMAC_Type) SetSET_INVALIDATE_DS(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_DS.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_DS() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg) & 0x1 +} + +// HMAC.QUERY_ERROR: The matching result between key and purpose user configured +func (o *HMAC_Type) SetQUERY_ERROR_QUERY_CHECK(value uint32) { + volatile.StoreUint32(&o.QUERY_ERROR.Reg, volatile.LoadUint32(&o.QUERY_ERROR.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_ERROR_QUERY_CHECK() uint32 { + return volatile.LoadUint32(&o.QUERY_ERROR.Reg) & 0x1 +} + +// HMAC.QUERY_BUSY: The busy state of HMAC module +func (o *HMAC_Type) SetQUERY_BUSY_BUSY_STATE(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_BUSY_BUSY_STATE() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// HMAC.WR_MESSAGE_0: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_0(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_0.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_0() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_0.Reg) +} + +// HMAC.WR_MESSAGE_1: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_1(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_1.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_1() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_1.Reg) +} + +// HMAC.WR_MESSAGE_2: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_2(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_2.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_2() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_2.Reg) +} + +// HMAC.WR_MESSAGE_3: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_3(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_3.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_3() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_3.Reg) +} + +// HMAC.WR_MESSAGE_4: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_4(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_4.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_4() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_4.Reg) +} + +// HMAC.WR_MESSAGE_5: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_5(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_5.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_5() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_5.Reg) +} + +// HMAC.WR_MESSAGE_6: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_6(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_6.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_6() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_6.Reg) +} + +// HMAC.WR_MESSAGE_7: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_7(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_7.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_7() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_7.Reg) +} + +// HMAC.WR_MESSAGE_8: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_8(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_8.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_8() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_8.Reg) +} + +// HMAC.WR_MESSAGE_9: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_9(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_9.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_9() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_9.Reg) +} + +// HMAC.WR_MESSAGE_10: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_10(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_10.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_10() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_10.Reg) +} + +// HMAC.WR_MESSAGE_11: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_11(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_11.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_11() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_11.Reg) +} + +// HMAC.WR_MESSAGE_12: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_12(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_12.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_12() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_12.Reg) +} + +// HMAC.WR_MESSAGE_13: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_13(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_13.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_13() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_13.Reg) +} + +// HMAC.WR_MESSAGE_14: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_14(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_14.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_14() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_14.Reg) +} + +// HMAC.WR_MESSAGE_15: Message register %s +func (o *HMAC_Type) SetWR_MESSAGE_15(value uint32) { + volatile.StoreUint32(&o.WR_MESSAGE_15.Reg, value) +} +func (o *HMAC_Type) GetWR_MESSAGE_15() uint32 { + return volatile.LoadUint32(&o.WR_MESSAGE_15.Reg) +} + +// HMAC.RD_RESULT_0: Hash result register %s +func (o *HMAC_Type) SetRD_RESULT_0(value uint32) { + volatile.StoreUint32(&o.RD_RESULT_0.Reg, value) +} +func (o *HMAC_Type) GetRD_RESULT_0() uint32 { + return volatile.LoadUint32(&o.RD_RESULT_0.Reg) +} + +// HMAC.RD_RESULT_1: Hash result register %s +func (o *HMAC_Type) SetRD_RESULT_1(value uint32) { + volatile.StoreUint32(&o.RD_RESULT_1.Reg, value) +} +func (o *HMAC_Type) GetRD_RESULT_1() uint32 { + return volatile.LoadUint32(&o.RD_RESULT_1.Reg) +} + +// HMAC.RD_RESULT_2: Hash result register %s +func (o *HMAC_Type) SetRD_RESULT_2(value uint32) { + volatile.StoreUint32(&o.RD_RESULT_2.Reg, value) +} +func (o *HMAC_Type) GetRD_RESULT_2() uint32 { + return volatile.LoadUint32(&o.RD_RESULT_2.Reg) +} + +// HMAC.RD_RESULT_3: Hash result register %s +func (o *HMAC_Type) SetRD_RESULT_3(value uint32) { + volatile.StoreUint32(&o.RD_RESULT_3.Reg, value) +} +func (o *HMAC_Type) GetRD_RESULT_3() uint32 { + return volatile.LoadUint32(&o.RD_RESULT_3.Reg) +} + +// HMAC.RD_RESULT_4: Hash result register %s +func (o *HMAC_Type) SetRD_RESULT_4(value uint32) { + volatile.StoreUint32(&o.RD_RESULT_4.Reg, value) +} +func (o *HMAC_Type) GetRD_RESULT_4() uint32 { + return volatile.LoadUint32(&o.RD_RESULT_4.Reg) +} + +// HMAC.RD_RESULT_5: Hash result register %s +func (o *HMAC_Type) SetRD_RESULT_5(value uint32) { + volatile.StoreUint32(&o.RD_RESULT_5.Reg, value) +} +func (o *HMAC_Type) GetRD_RESULT_5() uint32 { + return volatile.LoadUint32(&o.RD_RESULT_5.Reg) +} + +// HMAC.RD_RESULT_6: Hash result register %s +func (o *HMAC_Type) SetRD_RESULT_6(value uint32) { + volatile.StoreUint32(&o.RD_RESULT_6.Reg, value) +} +func (o *HMAC_Type) GetRD_RESULT_6() uint32 { + return volatile.LoadUint32(&o.RD_RESULT_6.Reg) +} + +// HMAC.RD_RESULT_7: Hash result register %s +func (o *HMAC_Type) SetRD_RESULT_7(value uint32) { + volatile.StoreUint32(&o.RD_RESULT_7.Reg, value) +} +func (o *HMAC_Type) GetRD_RESULT_7() uint32 { + return volatile.LoadUint32(&o.RD_RESULT_7.Reg) +} + +// HMAC.SET_MESSAGE_PAD: Software padding register +func (o *HMAC_Type) SetSET_MESSAGE_PAD_SET_TEXT_PAD(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_PAD.Reg, volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_PAD_SET_TEXT_PAD() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg) & 0x1 +} + +// HMAC.ONE_BLOCK: One block message register. +func (o *HMAC_Type) SetONE_BLOCK_SET_ONE_BLOCK(value uint32) { + volatile.StoreUint32(&o.ONE_BLOCK.Reg, volatile.LoadUint32(&o.ONE_BLOCK.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetONE_BLOCK_SET_ONE_BLOCK() uint32 { + return volatile.LoadUint32(&o.ONE_BLOCK.Reg) & 0x1 +} + +// HMAC.DATE: Version control register +func (o *HMAC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *HMAC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// I2C (Inter-Integrated Circuit) Controller 0 +type I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + SCL_FILTER_CFG volatile.Register32 // 0x50 + SDA_FILTER_CFG volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + COMD8 volatile.Register32 // 0x78 + COMD9 volatile.Register32 // 0x7C + COMD10 volatile.Register32 // 0x80 + COMD11 volatile.Register32 // 0x84 + COMD12 volatile.Register32 // 0x88 + COMD13 volatile.Register32 // 0x8C + COMD14 volatile.Register32 // 0x90 + COMD15 volatile.Register32 // 0x94 + SCL_ST_TIME_OUT volatile.Register32 // 0x98 + SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x9C + SCL_SP_CONF volatile.Register32 // 0xA0 + SCL_STRETCH_CONF volatile.Register32 // 0xA4 + _ [80]byte + DATE volatile.Register32 // 0xF8 +} + +// I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL clock +func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x3fff +} + +// I2C.CTR: Transmission setting +func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetCTR_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetCTR_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetCTR_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetCTR_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetCTR_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetCTR_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetCTR_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetCTR_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11 +} + +// I2C.SR: Describe I2C work status +func (o *I2C_Type) SetSR_RESP_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSR_RESP_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *I2C_Type) SetSR_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetSR_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetSR_TIME_OUT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetSR_TIME_OUT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetSR_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetSR_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetSR_BYTE_TRANS(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSR_BYTE_TRANS() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetSR_STRETCH_CAUSE(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xc000)|value<<14) +} +func (o *I2C_Type) GetSR_STRETCH_CAUSE() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xc000) >> 14 +} +func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xfc0000) >> 18 +} +func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// I2C.TO: Setting time out control for receiving data +func (o *I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0xffffff)|value) +} +func (o *I2C_Type) GetTO_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0xffffff +} +func (o *I2C_Type) SetTO_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1000000)|value<<24) +} +func (o *I2C_Type) GetTO_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TO.Reg) & 0x1000000) >> 24 +} + +// I2C.SLAVE_ADDR: Local slave address setting +func (o *I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// I2C.FIFO_ST: FIFO status register +func (o *I2C_Type) SetFIFO_ST_RXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_ST_RXFIFO_END_ADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_END_ADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x7c00)|value<<10) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_START_ADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x7c00) >> 10 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_END_ADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf8000)|value<<15) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_END_ADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf8000) >> 15 +} +func (o *I2C_Type) SetFIFO_ST_RX_UPDATE(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x100000)|value<<20) +} +func (o *I2C_Type) GetFIFO_ST_RX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x100000) >> 20 +} +func (o *I2C_Type) SetFIFO_ST_TX_UPDATE(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x200000)|value<<21) +} +func (o *I2C_Type) GetFIFO_ST_TX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x200000) >> 21 +} +func (o *I2C_Type) SetFIFO_ST_SLAVE_RW_POINT(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3fc00000)|value<<22) +} +func (o *I2C_Type) GetFIFO_ST_SLAVE_RW_POINT() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3fc00000) >> 22 +} + +// I2C.FIFO_CONF: FIFO configuration register +func (o *I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_ADDR_CFG_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_ADDR_CFG_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_RX_THRES(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_RX_THRES() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_TX_THRES(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3f00000)|value<<20) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_TX_THRES() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3f00000) >> 20 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000000) >> 26 +} + +// I2C.DATA: RX FIFO read data +func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// I2C.INT_RAW: Raw interrupt status +func (o *I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_STRETCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_STRETCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} + +// I2C.INT_CLR: Interrupt clear bits +func (o *I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_STRETCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_STRETCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} + +// I2C.INT_ENA: Interrupt enable bits +func (o *I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_STRETCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_STRETCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} + +// I2C.INT_STATUS: Status of captured I2C communication events +func (o *I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_STRETCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_STRETCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10000) >> 16 +} + +// I2C.SDA_HOLD: Configures the hold time after a negative SCL edge +func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x3ff +} + +// I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge +func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x3ff +} + +// I2C.SCL_HIGH_PERIOD: Configures the high level width of the SCL clock +func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x3fff +} +func (o *I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfffc000)|value<<14) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfffc000) >> 14 +} + +// I2C.SCL_START_HOLD: Configures the interval between pulling SDA low and pulling SCL low when the master generates a START condition +func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x3ff +} + +// I2C.SCL_RSTART_SETUP: Configures the interval between the positive edge of SCL and the negative edge of SDA +func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x3ff +} + +// I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x3fff +} + +// I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x3ff +} + +// I2C.SCL_FILTER_CFG: SCL filter configuration register +func (o *I2C_Type) SetSCL_FILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.SCL_FILTER_CFG.Reg, volatile.LoadUint32(&o.SCL_FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetSCL_FILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.SCL_FILTER_CFG.Reg) & 0xf +} +func (o *I2C_Type) SetSCL_FILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.SCL_FILTER_CFG.Reg, volatile.LoadUint32(&o.SCL_FILTER_CFG.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSCL_FILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_FILTER_CFG.Reg) & 0x10) >> 4 +} + +// I2C.SDA_FILTER_CFG: SDA filter configuration register +func (o *I2C_Type) SetSDA_FILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.SDA_FILTER_CFG.Reg, volatile.LoadUint32(&o.SDA_FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetSDA_FILTER_CFG_SDA_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.SDA_FILTER_CFG.Reg) & 0xf +} +func (o *I2C_Type) SetSDA_FILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.SDA_FILTER_CFG.Reg, volatile.LoadUint32(&o.SDA_FILTER_CFG.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSDA_FILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.SDA_FILTER_CFG.Reg) & 0x10) >> 4 +} + +// I2C.COMD0: I2C command register %s +func (o *I2C_Type) SetCOMD0_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD0_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD0_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD0_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD1: I2C command register %s +func (o *I2C_Type) SetCOMD1_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD1_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD1_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD1_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD2: I2C command register %s +func (o *I2C_Type) SetCOMD2_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD2_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD2_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD2_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD3: I2C command register %s +func (o *I2C_Type) SetCOMD3_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD3_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD3_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD3_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD4: I2C command register %s +func (o *I2C_Type) SetCOMD4_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD4_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD4_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD4_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD5: I2C command register %s +func (o *I2C_Type) SetCOMD5_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD5_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD5_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD5_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD6: I2C command register %s +func (o *I2C_Type) SetCOMD6_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD6_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD6_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD6_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD7: I2C command register %s +func (o *I2C_Type) SetCOMD7_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD7_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD7_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD7_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD8: I2C command register %s +func (o *I2C_Type) SetCOMD8_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD8.Reg, volatile.LoadUint32(&o.COMD8.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD8_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD8.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD8_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD8.Reg, volatile.LoadUint32(&o.COMD8.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD8_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD8.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD9: I2C command register %s +func (o *I2C_Type) SetCOMD9_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD9.Reg, volatile.LoadUint32(&o.COMD9.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD9_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD9.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD9_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD9.Reg, volatile.LoadUint32(&o.COMD9.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD9_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD9.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD10: I2C command register %s +func (o *I2C_Type) SetCOMD10_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD10.Reg, volatile.LoadUint32(&o.COMD10.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD10_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD10.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD10_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD10.Reg, volatile.LoadUint32(&o.COMD10.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD10_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD10.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD11: I2C command register %s +func (o *I2C_Type) SetCOMD11_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD11.Reg, volatile.LoadUint32(&o.COMD11.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD11_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD11.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD11_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD11.Reg, volatile.LoadUint32(&o.COMD11.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD11_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD11.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD12: I2C command register %s +func (o *I2C_Type) SetCOMD12_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD12.Reg, volatile.LoadUint32(&o.COMD12.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD12_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD12.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD12_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD12.Reg, volatile.LoadUint32(&o.COMD12.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD12_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD12.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD13: I2C command register %s +func (o *I2C_Type) SetCOMD13_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD13.Reg, volatile.LoadUint32(&o.COMD13.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD13_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD13.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD13_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD13.Reg, volatile.LoadUint32(&o.COMD13.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD13_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD13.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD14: I2C command register %s +func (o *I2C_Type) SetCOMD14_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD14.Reg, volatile.LoadUint32(&o.COMD14.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD14_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD14.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD14_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD14.Reg, volatile.LoadUint32(&o.COMD14.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD14_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD14.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD15: I2C command register %s +func (o *I2C_Type) SetCOMD15_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD15.Reg, volatile.LoadUint32(&o.COMD15.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD15_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD15.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD15_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD15.Reg, volatile.LoadUint32(&o.COMD15.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD15_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD15.Reg) & 0x80000000) >> 31 +} + +// I2C.SCL_ST_TIME_OUT: SCL status time out register +func (o *I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO(value uint32) { + volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0xffffff)|value) +} +func (o *I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO() uint32 { + return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0xffffff +} + +// I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register +func (o *I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO(value uint32) { + volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0xffffff)|value) +} +func (o *I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO() uint32 { + return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0xffffff +} + +// I2C.SCL_SP_CONF: Power configuration register +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// I2C.SCL_STRETCH_CONF: Set SCL stretch of I2C slave +func (o *I2C_Type) SetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM() uint32 { + return volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x3ff +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x800) >> 11 +} + +// I2C.DATE: Version control register +func (o *I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2S (Inter-IC Sound) Controller 0 +type I2S_Type struct { + _ [8]byte + CONF volatile.Register32 // 0x8 + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + TIMING volatile.Register32 // 0x1C + FIFO_CONF volatile.Register32 // 0x20 + RXEOF_NUM volatile.Register32 // 0x24 + CONF_SIGLE_DATA volatile.Register32 // 0x28 + CONF_CHAN volatile.Register32 // 0x2C + OUT_LINK volatile.Register32 // 0x30 + IN_LINK volatile.Register32 // 0x34 + OUT_EOF_DES_ADDR volatile.Register32 // 0x38 + IN_EOF_DES_ADDR volatile.Register32 // 0x3C + OUT_EOF_BFR_DES_ADDR volatile.Register32 // 0x40 + _ [4]byte + INLINK_DSCR volatile.Register32 // 0x48 + INLINK_DSCR_BF0 volatile.Register32 // 0x4C + INLINK_DSCR_BF1 volatile.Register32 // 0x50 + OUTLINK_DSCR volatile.Register32 // 0x54 + OUTLINK_DSCR_BF0 volatile.Register32 // 0x58 + OUTLINK_DSCR_BF1 volatile.Register32 // 0x5C + LC_CONF volatile.Register32 // 0x60 + OUTFIFO_PUSH volatile.Register32 // 0x64 + INFIFO_POP volatile.Register32 // 0x68 + LC_STATE0 volatile.Register32 // 0x6C + LC_STATE1 volatile.Register32 // 0x70 + LC_HUNG_CONF volatile.Register32 // 0x74 + _ [40]byte + CONF1 volatile.Register32 // 0xA0 + PD_CONF volatile.Register32 // 0xA4 + CONF2 volatile.Register32 // 0xA8 + CLKM_CONF volatile.Register32 // 0xAC + SAMPLE_RATE_CONF volatile.Register32 // 0xB0 + _ [8]byte + STATE volatile.Register32 // 0xBC + _ [60]byte + DATE volatile.Register32 // 0xFC +} + +// I2S.CONF: I2S configuration register +func (o *I2S_Type) SetCONF_TX_RESET(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetCONF_TX_RESET() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetCONF_RX_RESET(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetCONF_RX_RESET() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetCONF_TX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetCONF_TX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetCONF_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetCONF_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetCONF_TX_START(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetCONF_TX_START() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetCONF_RX_START(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetCONF_RX_START() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetCONF_TX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetCONF_TX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetCONF_RX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetCONF_RX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetCONF_TX_RIGHT_FIRST(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetCONF_TX_RIGHT_FIRST() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetCONF_RX_RIGHT_FIRST(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetCONF_RX_RIGHT_FIRST() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetCONF_TX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetCONF_TX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetCONF_RX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetCONF_RX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetCONF_TX_SHORT_SYNC(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetCONF_TX_SHORT_SYNC() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetCONF_RX_SHORT_SYNC(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetCONF_RX_SHORT_SYNC() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetCONF_TX_MONO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetCONF_TX_MONO() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetCONF_RX_MONO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetCONF_RX_MONO() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetCONF_TX_MSB_RIGHT(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetCONF_TX_MSB_RIGHT() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetCONF_RX_MSB_RIGHT(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetCONF_RX_MSB_RIGHT() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetCONF_TX_LSB_FIRST_DMA(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetCONF_TX_LSB_FIRST_DMA() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetCONF_RX_LSB_FIRST_DMA(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetCONF_RX_LSB_FIRST_DMA() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetCONF_SIG_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetCONF_SIG_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetCONF_TX_FIFO_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetCONF_TX_FIFO_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetCONF_RX_FIFO_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22) +} +func (o *I2S_Type) GetCONF_RX_FIFO_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22 +} +func (o *I2S_Type) SetCONF_TX_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23) +} +func (o *I2S_Type) GetCONF_TX_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23 +} +func (o *I2S_Type) SetCONF_TX_DMA_EQUAL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *I2S_Type) GetCONF_TX_DMA_EQUAL() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24 +} +func (o *I2S_Type) SetCONF_RX_DMA_EQUAL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *I2S_Type) GetCONF_RX_DMA_EQUAL() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25 +} +func (o *I2S_Type) SetCONF_PRE_REQ_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S_Type) GetCONF_PRE_REQ_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S_Type) SetCONF_TX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetCONF_TX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000000) >> 27 +} +func (o *I2S_Type) SetCONF_RX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *I2S_Type) GetCONF_RX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000000) >> 28 +} +func (o *I2S_Type) SetCONF_RX_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetCONF_RX_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000000) >> 29 +} + +// I2S.INT_RAW: Raw interrupt status +func (o *I2S_Type) SetINT_RAW_RX_TAKE_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_RAW_RX_TAKE_DATA_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_RAW_TX_PUT_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_RAW_TX_PUT_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_RAW_RX_WFULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_RAW_RX_WFULL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_RAW_RX_REMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_RAW_RX_REMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetINT_RAW_TX_WFULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetINT_RAW_TX_WFULL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetINT_RAW_TX_REMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetINT_RAW_TX_REMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetINT_RAW_IN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetINT_RAW_IN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetINT_RAW_IN_SUC_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetINT_RAW_IN_SUC_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetINT_RAW_IN_ERR_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetINT_RAW_IN_ERR_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetINT_RAW_OUT_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetINT_RAW_OUT_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetINT_RAW_IN_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetINT_RAW_IN_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetINT_RAW_OUT_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetINT_RAW_OUT_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetINT_RAW_IN_DSCR_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetINT_RAW_IN_DSCR_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetINT_RAW_OUT_TOTAL_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINT_RAW_OUT_TOTAL_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetINT_RAW_V_SYNC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetINT_RAW_V_SYNC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} + +// I2S.INT_ST: Masked interrupt status +func (o *I2S_Type) SetINT_ST_RX_TAKE_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ST_RX_TAKE_DATA_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ST_TX_PUT_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ST_TX_PUT_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ST_RX_WFULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ST_RX_WFULL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ST_RX_REMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ST_RX_REMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetINT_ST_TX_WFULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetINT_ST_TX_WFULL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetINT_ST_TX_REMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetINT_ST_TX_REMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetINT_ST_IN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetINT_ST_IN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetINT_ST_IN_SUC_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetINT_ST_IN_SUC_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetINT_ST_IN_ERR_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetINT_ST_IN_ERR_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetINT_ST_OUT_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetINT_ST_OUT_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetINT_ST_OUT_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetINT_ST_OUT_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetINT_ST_IN_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetINT_ST_IN_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetINT_ST_OUT_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetINT_ST_OUT_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetINT_ST_IN_DSCR_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetINT_ST_IN_DSCR_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetINT_ST_OUT_TOTAL_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINT_ST_OUT_TOTAL_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetINT_ST_V_SYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetINT_ST_V_SYNC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} + +// I2S.INT_ENA: Interrupt enable bits +func (o *I2S_Type) SetINT_ENA_RX_TAKE_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ENA_RX_TAKE_DATA_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ENA_TX_PUT_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ENA_TX_PUT_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ENA_RX_WFULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ENA_RX_WFULL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ENA_RX_REMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ENA_RX_REMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetINT_ENA_TX_WFULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetINT_ENA_TX_WFULL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetINT_ENA_TX_REMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetINT_ENA_TX_REMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetINT_ENA_IN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetINT_ENA_IN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetINT_ENA_IN_SUC_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetINT_ENA_IN_SUC_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetINT_ENA_IN_ERR_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetINT_ENA_IN_ERR_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetINT_ENA_OUT_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetINT_ENA_OUT_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetINT_ENA_OUT_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetINT_ENA_OUT_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetINT_ENA_IN_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetINT_ENA_IN_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetINT_ENA_OUT_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetINT_ENA_OUT_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetINT_ENA_IN_DSCR_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetINT_ENA_IN_DSCR_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetINT_ENA_OUT_TOTAL_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINT_ENA_OUT_TOTAL_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetINT_ENA_V_SYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetINT_ENA_V_SYNC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} + +// I2S.INT_CLR: Interrupt clear bits +func (o *I2S_Type) SetINT_CLR_TAKE_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_CLR_TAKE_DATA_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_CLR_PUT_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_CLR_PUT_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_CLR_RX_WFULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_CLR_RX_WFULL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_CLR_RX_REMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_CLR_RX_REMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetINT_CLR_TX_WFULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetINT_CLR_TX_WFULL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetINT_CLR_TX_REMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetINT_CLR_TX_REMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetINT_CLR_IN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetINT_CLR_IN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetINT_CLR_IN_SUC_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetINT_CLR_IN_SUC_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetINT_CLR_IN_ERR_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetINT_CLR_IN_ERR_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetINT_CLR_OUT_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetINT_CLR_OUT_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetINT_CLR_OUT_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetINT_CLR_OUT_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetINT_CLR_IN_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetINT_CLR_IN_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetINT_CLR_OUT_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetINT_CLR_OUT_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetINT_CLR_IN_DSCR_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetINT_CLR_IN_DSCR_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetINT_CLR_OUT_TOTAL_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINT_CLR_OUT_TOTAL_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetINT_CLR_V_SYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetINT_CLR_V_SYNC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} + +// I2S.TIMING: I2S timing register +func (o *I2S_Type) SetTIMING_TX_BCK_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetTIMING_TX_BCK_IN_DELAY() uint32 { + return volatile.LoadUint32(&o.TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetTIMING_TX_WS_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc)|value<<2) +} +func (o *I2S_Type) GetTIMING_TX_WS_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc) >> 2 +} +func (o *I2S_Type) SetTIMING_RX_BCK_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetTIMING_RX_BCK_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetTIMING_RX_WS_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc0)|value<<6) +} +func (o *I2S_Type) GetTIMING_RX_WS_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc0) >> 6 +} +func (o *I2S_Type) SetTIMING_RX_SD_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x300)|value<<8) +} +func (o *I2S_Type) GetTIMING_RX_SD_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x300) >> 8 +} +func (o *I2S_Type) SetTIMING_TX_BCK_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetTIMING_TX_BCK_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetTIMING_TX_WS_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x3000)|value<<12) +} +func (o *I2S_Type) GetTIMING_TX_WS_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x3000) >> 12 +} +func (o *I2S_Type) SetTIMING_TX_SD_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc000)|value<<14) +} +func (o *I2S_Type) GetTIMING_TX_SD_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc000) >> 14 +} +func (o *I2S_Type) SetTIMING_RX_WS_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetTIMING_RX_WS_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetTIMING_RX_BCK_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc0000)|value<<18) +} +func (o *I2S_Type) GetTIMING_RX_BCK_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc0000) >> 18 +} +func (o *I2S_Type) SetTIMING_TX_DSYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTIMING_TX_DSYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetTIMING_RX_DSYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetTIMING_RX_DSYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetTIMING_DATA_ENABLE_DELAY(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0xc00000)|value<<22) +} +func (o *I2S_Type) GetTIMING_DATA_ENABLE_DELAY() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0xc00000) >> 22 +} +func (o *I2S_Type) SetTIMING_TX_BCK_IN_INV(value uint32) { + volatile.StoreUint32(&o.TIMING.Reg, volatile.LoadUint32(&o.TIMING.Reg)&^(0x1000000)|value<<24) +} +func (o *I2S_Type) GetTIMING_TX_BCK_IN_INV() uint32 { + return (volatile.LoadUint32(&o.TIMING.Reg) & 0x1000000) >> 24 +} + +// I2S.FIFO_CONF: I2S FIFO configuration register +func (o *I2S_Type) SetFIFO_CONF_RX_DATA_NUM(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3f)|value) +} +func (o *I2S_Type) GetFIFO_CONF_RX_DATA_NUM() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3f +} +func (o *I2S_Type) SetFIFO_CONF_TX_DATA_NUM(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *I2S_Type) GetFIFO_CONF_TX_DATA_NUM() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xfc0) >> 6 +} +func (o *I2S_Type) SetFIFO_CONF_DSCR_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetFIFO_CONF_DSCR_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetFIFO_CONF_TX_FIFO_MOD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xe000)|value<<13) +} +func (o *I2S_Type) GetFIFO_CONF_TX_FIFO_MOD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xe000) >> 13 +} +func (o *I2S_Type) SetFIFO_CONF_RX_FIFO_MOD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x70000)|value<<16) +} +func (o *I2S_Type) GetFIFO_CONF_RX_FIFO_MOD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x70000) >> 16 +} +func (o *I2S_Type) SetFIFO_CONF_TX_FIFO_MOD_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetFIFO_CONF_TX_FIFO_MOD_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetFIFO_CONF_RX_FIFO_MOD_FORCE_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetFIFO_CONF_RX_FIFO_MOD_FORCE_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetFIFO_CONF_RX_FIFO_SYNC(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetFIFO_CONF_RX_FIFO_SYNC() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetFIFO_CONF_RX_24MSB_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *I2S_Type) GetFIFO_CONF_RX_24MSB_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400000) >> 22 +} +func (o *I2S_Type) SetFIFO_CONF_TX_24MSB_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *I2S_Type) GetFIFO_CONF_TX_24MSB_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x800000) >> 23 +} + +// I2S.RXEOF_NUM: I2S DMA RX EOF data length +func (o *I2S_Type) SetRXEOF_NUM(value uint32) { + volatile.StoreUint32(&o.RXEOF_NUM.Reg, value) +} +func (o *I2S_Type) GetRXEOF_NUM() uint32 { + return volatile.LoadUint32(&o.RXEOF_NUM.Reg) +} + +// I2S.CONF_SIGLE_DATA: Constant single channel data +func (o *I2S_Type) SetCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value) +} +func (o *I2S_Type) GetCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg) +} + +// I2S.CONF_CHAN: I2S channel configuration register +func (o *I2S_Type) SetCONF_CHAN_TX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.CONF_CHAN.Reg, volatile.LoadUint32(&o.CONF_CHAN.Reg)&^(0x7)|value) +} +func (o *I2S_Type) GetCONF_CHAN_TX_CHAN_MOD() uint32 { + return volatile.LoadUint32(&o.CONF_CHAN.Reg) & 0x7 +} +func (o *I2S_Type) SetCONF_CHAN_RX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.CONF_CHAN.Reg, volatile.LoadUint32(&o.CONF_CHAN.Reg)&^(0x18)|value<<3) +} +func (o *I2S_Type) GetCONF_CHAN_RX_CHAN_MOD() uint32 { + return (volatile.LoadUint32(&o.CONF_CHAN.Reg) & 0x18) >> 3 +} + +// I2S.OUT_LINK: I2S DMA TX configuration register +func (o *I2S_Type) SetOUT_LINK_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0xfffff)|value) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK.Reg) & 0xfffff +} +func (o *I2S_Type) SetOUT_LINK_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK.Reg) & 0x10000000) >> 28 +} +func (o *I2S_Type) SetOUT_LINK_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK.Reg) & 0x20000000) >> 29 +} +func (o *I2S_Type) SetOUT_LINK_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK.Reg) & 0x40000000) >> 30 +} +func (o *I2S_Type) SetOUT_LINK_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK.Reg, volatile.LoadUint32(&o.OUT_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *I2S_Type) GetOUT_LINK_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK.Reg) & 0x80000000) >> 31 +} + +// I2S.IN_LINK: I2S DMA RX configuration register +func (o *I2S_Type) SetIN_LINK_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0xfffff)|value) +} +func (o *I2S_Type) GetIN_LINK_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK.Reg) & 0xfffff +} +func (o *I2S_Type) SetIN_LINK_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *I2S_Type) GetIN_LINK_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK.Reg) & 0x10000000) >> 28 +} +func (o *I2S_Type) SetIN_LINK_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetIN_LINK_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK.Reg) & 0x20000000) >> 29 +} +func (o *I2S_Type) SetIN_LINK_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetIN_LINK_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK.Reg) & 0x40000000) >> 30 +} +func (o *I2S_Type) SetIN_LINK_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK.Reg, volatile.LoadUint32(&o.IN_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *I2S_Type) GetIN_LINK_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK.Reg) & 0x80000000) >> 31 +} + +// I2S.OUT_EOF_DES_ADDR: Address of outlink descriptor that produces EOF +func (o *I2S_Type) SetOUT_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR.Reg, value) +} +func (o *I2S_Type) GetOUT_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR.Reg) +} + +// I2S.IN_EOF_DES_ADDR: Address of inlink descriptor that produces EOF +func (o *I2S_Type) SetIN_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EOF_DES_ADDR.Reg, value) +} +func (o *I2S_Type) GetIN_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_EOF_DES_ADDR.Reg) +} + +// I2S.OUT_EOF_BFR_DES_ADDR: Address of buffer relative to the outlink descriptor that produces EOF +func (o *I2S_Type) SetOUT_EOF_BFR_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR.Reg, value) +} +func (o *I2S_Type) GetOUT_EOF_BFR_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR.Reg) +} + +// I2S.INLINK_DSCR: Address of current inlink descriptor +func (o *I2S_Type) SetINLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR.Reg, value) +} +func (o *I2S_Type) GetINLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR.Reg) +} + +// I2S.INLINK_DSCR_BF0: Address of next inlink descriptor +func (o *I2S_Type) SetINLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR_BF0.Reg, value) +} +func (o *I2S_Type) GetINLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR_BF0.Reg) +} + +// I2S.INLINK_DSCR_BF1: Address of next inlink data buffer +func (o *I2S_Type) SetINLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR_BF1.Reg, value) +} +func (o *I2S_Type) GetINLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR_BF1.Reg) +} + +// I2S.OUTLINK_DSCR: Address of current outlink descriptor +func (o *I2S_Type) SetOUTLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR.Reg, value) +} +func (o *I2S_Type) GetOUTLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR.Reg) +} + +// I2S.OUTLINK_DSCR_BF0: Address of next outlink descriptor +func (o *I2S_Type) SetOUTLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR_BF0.Reg, value) +} +func (o *I2S_Type) GetOUTLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR_BF0.Reg) +} + +// I2S.OUTLINK_DSCR_BF1: Address of next outlink data buffer +func (o *I2S_Type) SetOUTLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR_BF1.Reg, value) +} +func (o *I2S_Type) GetOUTLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR_BF1.Reg) +} + +// I2S.LC_CONF: I2S DMA configuration register +func (o *I2S_Type) SetLC_CONF_IN_RST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetLC_CONF_IN_RST() uint32 { + return volatile.LoadUint32(&o.LC_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetLC_CONF_OUT_RST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetLC_CONF_OUT_RST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetLC_CONF_AHBM_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetLC_CONF_AHBM_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetLC_CONF_AHBM_RST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetLC_CONF_AHBM_RST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetLC_CONF_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetLC_CONF_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetLC_CONF_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetLC_CONF_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetLC_CONF_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetLC_CONF_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetLC_CONF_OUT_NO_RESTART_CLR(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetLC_CONF_OUT_NO_RESTART_CLR() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetLC_CONF_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetLC_CONF_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetLC_CONF_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetLC_CONF_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetLC_CONF_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetLC_CONF_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetLC_CONF_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetLC_CONF_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetLC_CONF_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetLC_CONF_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetLC_CONF_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetLC_CONF_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetLC_CONF_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.LC_CONF.Reg, volatile.LoadUint32(&o.LC_CONF.Reg)&^(0xc000)|value<<14) +} +func (o *I2S_Type) GetLC_CONF_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.LC_CONF.Reg) & 0xc000) >> 14 +} + +// I2S.OUTFIFO_PUSH: APB out FIFO mode register +func (o *I2S_Type) SetOUTFIFO_PUSH_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_PUSH.Reg, volatile.LoadUint32(&o.OUTFIFO_PUSH.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetOUTFIFO_PUSH_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_PUSH.Reg) & 0x1ff +} +func (o *I2S_Type) SetOUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_PUSH.Reg, volatile.LoadUint32(&o.OUTFIFO_PUSH.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetOUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_PUSH.Reg) & 0x10000) >> 16 +} + +// I2S.INFIFO_POP: APB in FIFO mode register +func (o *I2S_Type) SetINFIFO_POP_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.INFIFO_POP.Reg, volatile.LoadUint32(&o.INFIFO_POP.Reg)&^(0xfff)|value) +} +func (o *I2S_Type) GetINFIFO_POP_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.INFIFO_POP.Reg) & 0xfff +} +func (o *I2S_Type) SetINFIFO_POP(value uint32) { + volatile.StoreUint32(&o.INFIFO_POP.Reg, volatile.LoadUint32(&o.INFIFO_POP.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetINFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.INFIFO_POP.Reg) & 0x10000) >> 16 +} + +// I2S.LC_STATE0: I2S DMA TX status +func (o *I2S_Type) SetLC_STATE0_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.LC_STATE0.Reg, volatile.LoadUint32(&o.LC_STATE0.Reg)&^(0x3ffff)|value) +} +func (o *I2S_Type) GetLC_STATE0_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.LC_STATE0.Reg) & 0x3ffff +} +func (o *I2S_Type) SetLC_STATE0_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.LC_STATE0.Reg, volatile.LoadUint32(&o.LC_STATE0.Reg)&^(0xc0000)|value<<18) +} +func (o *I2S_Type) GetLC_STATE0_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.LC_STATE0.Reg) & 0xc0000) >> 18 +} +func (o *I2S_Type) SetLC_STATE0_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.LC_STATE0.Reg, volatile.LoadUint32(&o.LC_STATE0.Reg)&^(0x700000)|value<<20) +} +func (o *I2S_Type) GetLC_STATE0_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.LC_STATE0.Reg) & 0x700000) >> 20 +} +func (o *I2S_Type) SetLC_STATE0_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.LC_STATE0.Reg, volatile.LoadUint32(&o.LC_STATE0.Reg)&^(0x3f800000)|value<<23) +} +func (o *I2S_Type) GetLC_STATE0_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.LC_STATE0.Reg) & 0x3f800000) >> 23 +} +func (o *I2S_Type) SetLC_STATE0_OUT_FULL(value uint32) { + volatile.StoreUint32(&o.LC_STATE0.Reg, volatile.LoadUint32(&o.LC_STATE0.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetLC_STATE0_OUT_FULL() uint32 { + return (volatile.LoadUint32(&o.LC_STATE0.Reg) & 0x40000000) >> 30 +} +func (o *I2S_Type) SetLC_STATE0_OUT_EMPTY(value uint32) { + volatile.StoreUint32(&o.LC_STATE0.Reg, volatile.LoadUint32(&o.LC_STATE0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2S_Type) GetLC_STATE0_OUT_EMPTY() uint32 { + return (volatile.LoadUint32(&o.LC_STATE0.Reg) & 0x80000000) >> 31 +} + +// I2S.LC_STATE1: I2S DMA RX status +func (o *I2S_Type) SetLC_STATE1_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.LC_STATE1.Reg, volatile.LoadUint32(&o.LC_STATE1.Reg)&^(0x3ffff)|value) +} +func (o *I2S_Type) GetLC_STATE1_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.LC_STATE1.Reg) & 0x3ffff +} +func (o *I2S_Type) SetLC_STATE1_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.LC_STATE1.Reg, volatile.LoadUint32(&o.LC_STATE1.Reg)&^(0xc0000)|value<<18) +} +func (o *I2S_Type) GetLC_STATE1_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.LC_STATE1.Reg) & 0xc0000) >> 18 +} +func (o *I2S_Type) SetLC_STATE1_IN_STATE(value uint32) { + volatile.StoreUint32(&o.LC_STATE1.Reg, volatile.LoadUint32(&o.LC_STATE1.Reg)&^(0x700000)|value<<20) +} +func (o *I2S_Type) GetLC_STATE1_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.LC_STATE1.Reg) & 0x700000) >> 20 +} +func (o *I2S_Type) SetLC_STATE1_INFIFO_CNT_DEBUG(value uint32) { + volatile.StoreUint32(&o.LC_STATE1.Reg, volatile.LoadUint32(&o.LC_STATE1.Reg)&^(0x3f800000)|value<<23) +} +func (o *I2S_Type) GetLC_STATE1_INFIFO_CNT_DEBUG() uint32 { + return (volatile.LoadUint32(&o.LC_STATE1.Reg) & 0x3f800000) >> 23 +} +func (o *I2S_Type) SetLC_STATE1_IN_FULL(value uint32) { + volatile.StoreUint32(&o.LC_STATE1.Reg, volatile.LoadUint32(&o.LC_STATE1.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetLC_STATE1_IN_FULL() uint32 { + return (volatile.LoadUint32(&o.LC_STATE1.Reg) & 0x40000000) >> 30 +} +func (o *I2S_Type) SetLC_STATE1_IN_EMPTY(value uint32) { + volatile.StoreUint32(&o.LC_STATE1.Reg, volatile.LoadUint32(&o.LC_STATE1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2S_Type) GetLC_STATE1_IN_EMPTY() uint32 { + return (volatile.LoadUint32(&o.LC_STATE1.Reg) & 0x80000000) >> 31 +} + +// I2S.LC_HUNG_CONF: I2S Hung configuration register +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11 +} + +// I2S.CONF1: I2S configuration register 1 +func (o *I2S_Type) SetCONF1_TX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x7)|value) +} +func (o *I2S_Type) GetCONF1_TX_PCM_CONF() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x7 +} +func (o *I2S_Type) SetCONF1_TX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetCONF1_TX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetCONF1_RX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x70)|value<<4) +} +func (o *I2S_Type) GetCONF1_RX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x70) >> 4 +} +func (o *I2S_Type) SetCONF1_RX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetCONF1_RX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetCONF1_TX_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetCONF1_TX_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetCONF1_TX_ZEROS_RM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetCONF1_TX_ZEROS_RM_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200) >> 9 +} + +// I2S.PD_CONF: I2S power-down configuration register +func (o *I2S_Type) SetPD_CONF_FIFO_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetPD_CONF_FIFO_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.PD_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetPD_CONF_FIFO_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetPD_CONF_FIFO_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetPD_CONF_PLC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetPD_CONF_PLC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetPD_CONF_PLC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetPD_CONF_PLC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetPD_CONF_DMA_RAM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetPD_CONF_DMA_RAM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetPD_CONF_DMA_RAM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetPD_CONF_DMA_RAM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetPD_CONF_DMA_RAM_CLK_FO(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetPD_CONF_DMA_RAM_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x40) >> 6 +} + +// I2S.CONF2: I2S configuration register 2 +func (o *I2S_Type) SetCONF2_CAMERA_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetCONF2_CAMERA_EN() uint32 { + return volatile.LoadUint32(&o.CONF2.Reg) & 0x1 +} +func (o *I2S_Type) SetCONF2_LCD_TX_WRX2_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetCONF2_LCD_TX_WRX2_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetCONF2_LCD_TX_SDX2_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetCONF2_LCD_TX_SDX2_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetCONF2_DATA_ENABLE_TEST_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetCONF2_DATA_ENABLE_TEST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetCONF2_DATA_ENABLE(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetCONF2_DATA_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetCONF2_LCD_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetCONF2_LCD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetCONF2_EXT_ADC_START_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetCONF2_EXT_ADC_START_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetCONF2_INTER_VALID_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetCONF2_INTER_VALID_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetCONF2_CAM_SYNC_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetCONF2_CAM_SYNC_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetCONF2_CAM_CLK_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetCONF2_CAM_CLK_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetCONF2_VSYNC_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetCONF2_VSYNC_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetCONF2_VSYNC_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CONF2.Reg, volatile.LoadUint32(&o.CONF2.Reg)&^(0x3800)|value<<11) +} +func (o *I2S_Type) GetCONF2_VSYNC_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CONF2.Reg) & 0x3800) >> 11 +} + +// I2S.CLKM_CONF: I2S module clock configuration register +func (o *I2S_Type) SetCLKM_CONF_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetCLKM_CONF_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetCLKM_CONF_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *I2S_Type) GetCLKM_CONF_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x3f00) >> 8 +} +func (o *I2S_Type) SetCLKM_CONF_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2S_Type) GetCLKM_CONF_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2S_Type) SetCLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetCLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetCLKM_CONF_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x600000)|value<<21) +} +func (o *I2S_Type) GetCLKM_CONF_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x600000) >> 21 +} + +// I2S.SAMPLE_RATE_CONF: I2S sample rate register +func (o *I2S_Type) SetSAMPLE_RATE_CONF_TX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SAMPLE_RATE_CONF.Reg, volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg)&^(0x3f)|value) +} +func (o *I2S_Type) GetSAMPLE_RATE_CONF_TX_BCK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg) & 0x3f +} +func (o *I2S_Type) SetSAMPLE_RATE_CONF_RX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SAMPLE_RATE_CONF.Reg, volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *I2S_Type) GetSAMPLE_RATE_CONF_RX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg) & 0xfc0) >> 6 +} +func (o *I2S_Type) SetSAMPLE_RATE_CONF_TX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.SAMPLE_RATE_CONF.Reg, volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg)&^(0x3f000)|value<<12) +} +func (o *I2S_Type) GetSAMPLE_RATE_CONF_TX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg) & 0x3f000) >> 12 +} +func (o *I2S_Type) SetSAMPLE_RATE_CONF_RX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.SAMPLE_RATE_CONF.Reg, volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S_Type) GetSAMPLE_RATE_CONF_RX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.SAMPLE_RATE_CONF.Reg) & 0xfc0000) >> 18 +} + +// I2S.STATE: I2S TX status register +func (o *I2S_Type) SetSTATE_TX_IDLE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetSTATE_TX_IDLE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x1 +} + +// I2S.DATE: Version control register +func (o *I2S_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2S_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Interrupt Controller (Core 0) +type INTERRUPT_CORE0_Type struct { + PRO_MAC_INTR_MAP volatile.Register32 // 0x0 + PRO_MAC_NMI_MAP volatile.Register32 // 0x4 + PRO_PWR_INTR_MAP volatile.Register32 // 0x8 + PRO_BB_INT_MAP volatile.Register32 // 0xC + PRO_BT_MAC_INT_MAP volatile.Register32 // 0x10 + PRO_BT_BB_INT_MAP volatile.Register32 // 0x14 + PRO_BT_BB_NMI_MAP volatile.Register32 // 0x18 + PRO_RWBT_IRQ_MAP volatile.Register32 // 0x1C + PRO_RWBLE_IRQ_MAP volatile.Register32 // 0x20 + PRO_RWBT_NMI_MAP volatile.Register32 // 0x24 + PRO_RWBLE_NMI_MAP volatile.Register32 // 0x28 + PRO_SLC0_INTR_MAP volatile.Register32 // 0x2C + PRO_SLC1_INTR_MAP volatile.Register32 // 0x30 + PRO_UHCI0_INTR_MAP volatile.Register32 // 0x34 + PRO_UHCI1_INTR_MAP volatile.Register32 // 0x38 + PRO_TG_T0_LEVEL_INT_MAP volatile.Register32 // 0x3C + PRO_TG_T1_LEVEL_INT_MAP volatile.Register32 // 0x40 + PRO_TG_WDT_LEVEL_INT_MAP volatile.Register32 // 0x44 + PRO_TG_LACT_LEVEL_INT_MAP volatile.Register32 // 0x48 + PRO_TG1_T0_LEVEL_INT_MAP volatile.Register32 // 0x4C + PRO_TG1_T1_LEVEL_INT_MAP volatile.Register32 // 0x50 + PRO_TG1_WDT_LEVEL_INT_MAP volatile.Register32 // 0x54 + PRO_TG1_LACT_LEVEL_INT_MAP volatile.Register32 // 0x58 + PRO_GPIO_INTERRUPT_PRO_MAP volatile.Register32 // 0x5C + PRO_GPIO_INTERRUPT_PRO_NMI_MAP volatile.Register32 // 0x60 + PRO_GPIO_INTERRUPT_APP_MAP volatile.Register32 // 0x64 + PRO_GPIO_INTERRUPT_APP_NMI_MAP volatile.Register32 // 0x68 + PRO_DEDICATED_GPIO_IN_INTR_MAP volatile.Register32 // 0x6C + PRO_CPU_INTR_FROM_CPU_0_MAP volatile.Register32 // 0x70 + PRO_CPU_INTR_FROM_CPU_1_MAP volatile.Register32 // 0x74 + PRO_CPU_INTR_FROM_CPU_2_MAP volatile.Register32 // 0x78 + PRO_CPU_INTR_FROM_CPU_3_MAP volatile.Register32 // 0x7C + PRO_SPI_INTR_1_MAP volatile.Register32 // 0x80 + PRO_SPI_INTR_2_MAP volatile.Register32 // 0x84 + PRO_SPI_INTR_3_MAP volatile.Register32 // 0x88 + PRO_I2S0_INT_MAP volatile.Register32 // 0x8C + PRO_I2S1_INT_MAP volatile.Register32 // 0x90 + PRO_UART_INTR_MAP volatile.Register32 // 0x94 + PRO_UART1_INTR_MAP volatile.Register32 // 0x98 + PRO_UART2_INTR_MAP volatile.Register32 // 0x9C + PRO_SDIO_HOST_INTERRUPT_MAP volatile.Register32 // 0xA0 + PRO_PWM0_INTR_MAP volatile.Register32 // 0xA4 + PRO_PWM1_INTR_MAP volatile.Register32 // 0xA8 + PRO_PWM2_INTR_MAP volatile.Register32 // 0xAC + PRO_PWM3_INTR_MAP volatile.Register32 // 0xB0 + PRO_LEDC_INT_MAP volatile.Register32 // 0xB4 + PRO_EFUSE_INT_MAP volatile.Register32 // 0xB8 + PRO_CAN_INT_MAP volatile.Register32 // 0xBC + PRO_USB_INTR_MAP volatile.Register32 // 0xC0 + PRO_RTC_CORE_INTR_MAP volatile.Register32 // 0xC4 + PRO_RMT_INTR_MAP volatile.Register32 // 0xC8 + PRO_PCNT_INTR_MAP volatile.Register32 // 0xCC + PRO_I2C_EXT0_INTR_MAP volatile.Register32 // 0xD0 + PRO_I2C_EXT1_INTR_MAP volatile.Register32 // 0xD4 + PRO_RSA_INTR_MAP volatile.Register32 // 0xD8 + PRO_SHA_INTR_MAP volatile.Register32 // 0xDC + PRO_AES_INTR_MAP volatile.Register32 // 0xE0 + PRO_SPI2_DMA_INT_MAP volatile.Register32 // 0xE4 + PRO_SPI3_DMA_INT_MAP volatile.Register32 // 0xE8 + PRO_WDG_INT_MAP volatile.Register32 // 0xEC + PRO_TIMER_INT1_MAP volatile.Register32 // 0xF0 + PRO_TIMER_INT2_MAP volatile.Register32 // 0xF4 + PRO_TG_T0_EDGE_INT_MAP volatile.Register32 // 0xF8 + PRO_TG_T1_EDGE_INT_MAP volatile.Register32 // 0xFC + PRO_TG_WDT_EDGE_INT_MAP volatile.Register32 // 0x100 + PRO_TG_LACT_EDGE_INT_MAP volatile.Register32 // 0x104 + PRO_TG1_T0_EDGE_INT_MAP volatile.Register32 // 0x108 + PRO_TG1_T1_EDGE_INT_MAP volatile.Register32 // 0x10C + PRO_TG1_WDT_EDGE_INT_MAP volatile.Register32 // 0x110 + PRO_TG1_LACT_EDGE_INT_MAP volatile.Register32 // 0x114 + PRO_CACHE_IA_INT_MAP volatile.Register32 // 0x118 + PRO_SYSTIMER_TARGET0_INT_MAP volatile.Register32 // 0x11C + PRO_SYSTIMER_TARGET1_INT_MAP volatile.Register32 // 0x120 + PRO_SYSTIMER_TARGET2_INT_MAP volatile.Register32 // 0x124 + PRO_ASSIST_DEBUG_INTR_MAP volatile.Register32 // 0x128 + PRO_PMS_PRO_IRAM0_ILG_INTR_MAP volatile.Register32 // 0x12C + PRO_PMS_PRO_DRAM0_ILG_INTR_MAP volatile.Register32 // 0x130 + PRO_PMS_PRO_DPORT_ILG_INTR_MAP volatile.Register32 // 0x134 + PRO_PMS_PRO_AHB_ILG_INTR_MAP volatile.Register32 // 0x138 + PRO_PMS_PRO_CACHE_ILG_INTR_MAP volatile.Register32 // 0x13C + PRO_PMS_DMA_APB_I_ILG_INTR_MAP volatile.Register32 // 0x140 + PRO_PMS_DMA_RX_I_ILG_INTR_MAP volatile.Register32 // 0x144 + PRO_PMS_DMA_TX_I_ILG_INTR_MAP volatile.Register32 // 0x148 + PRO_SPI_MEM_REJECT_INTR_MAP volatile.Register32 // 0x14C + PRO_DMA_COPY_INTR_MAP volatile.Register32 // 0x150 + PRO_SPI4_DMA_INT_MAP volatile.Register32 // 0x154 + PRO_SPI_INTR_4_MAP volatile.Register32 // 0x158 + PRO_DCACHE_PRELOAD_INT_MAP volatile.Register32 // 0x15C + PRO_ICACHE_PRELOAD_INT_MAP volatile.Register32 // 0x160 + PRO_APB_ADC_INT_MAP volatile.Register32 // 0x164 + PRO_CRYPTO_DMA_INT_MAP volatile.Register32 // 0x168 + PRO_CPU_PERI_ERROR_INT_MAP volatile.Register32 // 0x16C + PRO_APB_PERI_ERROR_INT_MAP volatile.Register32 // 0x170 + PRO_DCACHE_SYNC_INT_MAP volatile.Register32 // 0x174 + PRO_ICACHE_SYNC_INT_MAP volatile.Register32 // 0x178 + PRO_INTR_STATUS_0 volatile.Register32 // 0x17C + PRO_INTR_STATUS_1 volatile.Register32 // 0x180 + PRO_INTR_STATUS_2 volatile.Register32 // 0x184 + CLOCK_GATE volatile.Register32 // 0x188 + _ [3696]byte + REG_DATE volatile.Register32 // 0xFFC +} + +// INTERRUPT_CORE0.PRO_MAC_INTR_MAP: MAC_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_MAC_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_MAC_NMI_MAP: MAC_NMI interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_MAC_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_MAC_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_MAC_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_MAC_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_MAC_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PWR_INTR_MAP: PWR_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PWR_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PWR_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PWR_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PWR_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PWR_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_BB_INT_MAP: BB_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_BB_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_BT_MAC_INT_MAP: BT_MAC_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_BT_MAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_BT_MAC_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_BT_MAC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_BT_MAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_BT_MAC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_BT_BB_INT_MAP: BT_BB_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_BT_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_BT_BB_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_BT_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_BT_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_BT_BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_BT_BB_NMI_MAP: BT_BB_NMI interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_BT_BB_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_BT_BB_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_BT_BB_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_BT_BB_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_BT_BB_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_RWBT_IRQ_MAP: RWBT_IRQ interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_RWBT_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RWBT_IRQ_MAP.Reg, volatile.LoadUint32(&o.PRO_RWBT_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_RWBT_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RWBT_IRQ_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_RWBLE_IRQ_MAP: RWBLE_IRQ interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_RWBLE_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RWBLE_IRQ_MAP.Reg, volatile.LoadUint32(&o.PRO_RWBLE_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_RWBLE_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RWBLE_IRQ_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_RWBT_NMI_MAP: RWBT_NMI interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_RWBT_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RWBT_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_RWBT_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_RWBT_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RWBT_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_RWBLE_NMI_MAP: RWBLE_NMI interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_RWBLE_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RWBLE_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_RWBLE_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_RWBLE_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RWBLE_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SLC0_INTR_MAP: SLC0_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SLC0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SLC0_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_SLC0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SLC0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SLC0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SLC1_INTR_MAP: SLC1_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SLC1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SLC1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_SLC1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SLC1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SLC1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_UHCI0_INTR_MAP: UHCI0_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_UHCI0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UHCI0_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UHCI0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_UHCI0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UHCI0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_UHCI1_INTR_MAP: UHCI1_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_UHCI1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UHCI1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UHCI1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_UHCI1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UHCI1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG_T0_LEVEL_INT_MAP: TG_T0_LEVEL_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG_T0_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_T0_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_T0_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG_T0_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_T0_LEVEL_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG_T1_LEVEL_INT_MAP: TG_T1_LEVEL_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG_T1_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_T1_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_T1_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG_T1_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_T1_LEVEL_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG_WDT_LEVEL_INT_MAP: TG_WDT_LEVEL_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG_WDT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_WDT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_WDT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG_WDT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_WDT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG_LACT_LEVEL_INT_MAP: TG_LACT_LEVEL_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG_LACT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_LACT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_LACT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG_LACT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_LACT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG1_T0_LEVEL_INT_MAP: TG1_T0_LEVEL_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG1_T0_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_T0_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_T0_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG1_T0_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_T0_LEVEL_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG1_T1_LEVEL_INT_MAP: TG1_T1_LEVEL_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG1_T1_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_T1_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_T1_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG1_T1_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_T1_LEVEL_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG1_WDT_LEVEL_INT_MAP: TG1_WDT_LEVEL_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG1_WDT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_WDT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_WDT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG1_WDT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_WDT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG1_LACT_LEVEL_INT_MAP: TG1_LACT_LEVEL_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG1_LACT_LEVEL_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_LACT_LEVEL_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_LACT_LEVEL_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG1_LACT_LEVEL_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_LACT_LEVEL_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_GPIO_INTERRUPT_PRO_MAP: GPIO_INTERRUPT_PRO interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_GPIO_INTERRUPT_PRO_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_GPIO_INTERRUPT_PRO_MAP.Reg, volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_PRO_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_GPIO_INTERRUPT_PRO_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_PRO_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_GPIO_INTERRUPT_PRO_NMI_MAP: GPIO_INTERRUPT_PRO_NMI interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_GPIO_INTERRUPT_PRO_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_GPIO_INTERRUPT_PRO_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_PRO_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_GPIO_INTERRUPT_PRO_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_PRO_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_GPIO_INTERRUPT_APP_MAP: GPIO_INTERRUPT_APP interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_GPIO_INTERRUPT_APP_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_GPIO_INTERRUPT_APP_MAP.Reg, volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_APP_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_GPIO_INTERRUPT_APP_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_APP_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_GPIO_INTERRUPT_APP_NMI_MAP: GPIO_INTERRUPT_APP_NMI interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_GPIO_INTERRUPT_APP_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_GPIO_INTERRUPT_APP_NMI_MAP.Reg, volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_APP_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_GPIO_INTERRUPT_APP_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_GPIO_INTERRUPT_APP_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_DEDICATED_GPIO_IN_INTR_MAP: DEDICATED_GPIO_IN_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_DEDICATED_GPIO_IN_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_DEDICATED_GPIO_IN_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_DEDICATED_GPIO_IN_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_DEDICATED_GPIO_IN_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_DEDICATED_GPIO_IN_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_CPU_INTR_FROM_CPU_0_MAP: CPU_INTR_FROM_CPU_0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_CPU_INTR_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_INTR_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_0_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_CPU_INTR_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_0_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_CPU_INTR_FROM_CPU_1_MAP: CPU_INTR_FROM_CPU_1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_CPU_INTR_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_INTR_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_CPU_INTR_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_CPU_INTR_FROM_CPU_2_MAP: CPU_INTR_FROM_CPU_2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_CPU_INTR_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_INTR_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_CPU_INTR_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_CPU_INTR_FROM_CPU_3_MAP: CPU_INTR_FROM_CPU_3 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_CPU_INTR_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_INTR_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_CPU_INTR_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_INTR_FROM_CPU_3_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SPI_INTR_1_MAP: SPI_INTR_1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SPI_INTR_1_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI_INTR_1_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI_INTR_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SPI_INTR_1_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI_INTR_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SPI_INTR_2_MAP: SPI_INTR_2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SPI_INTR_2_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI_INTR_2_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI_INTR_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SPI_INTR_2_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI_INTR_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SPI_INTR_3_MAP: SPI_INTR_3 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SPI_INTR_3_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI_INTR_3_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI_INTR_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SPI_INTR_3_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI_INTR_3_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_I2S0_INT_MAP: I2S0_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_I2S0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_I2S0_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_I2S0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_I2S0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_I2S0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_I2S1_INT_MAP: I2S1_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_I2S1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_I2S1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_I2S1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_I2S1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_UART_INTR_MAP: UART_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_UART_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UART_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UART_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_UART_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UART_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_UART1_INTR_MAP: UART1_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_UART1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UART1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UART1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_UART1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UART1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_UART2_INTR_MAP: UART2_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_UART2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_UART2_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_UART2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_UART2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_UART2_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SDIO_HOST_INTERRUPT_MAP: SDIO_HOST_INTERRUPT configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SDIO_HOST_INTERRUPT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SDIO_HOST_INTERRUPT_MAP.Reg, volatile.LoadUint32(&o.PRO_SDIO_HOST_INTERRUPT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SDIO_HOST_INTERRUPT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SDIO_HOST_INTERRUPT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PWM0_INTR_MAP: PWM0_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PWM0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PWM0_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PWM0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PWM0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PWM0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PWM1_INTR_MAP: PWM1_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PWM1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PWM1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PWM1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PWM1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PWM1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PWM2_INTR_MAP: PWM2_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PWM2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PWM2_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PWM2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PWM2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PWM2_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PWM3_INTR_MAP: PWM3_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PWM3_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PWM3_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PWM3_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PWM3_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PWM3_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_LEDC_INT_MAP: LEDC_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_LEDC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_LEDC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_LEDC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_LEDC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_EFUSE_INT_MAP: EFUSE_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_EFUSE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_EFUSE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_EFUSE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_EFUSE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_CAN_INT_MAP: CAN_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_CAN_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CAN_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_CAN_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_CAN_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CAN_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_USB_INTR_MAP: USB_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_USB_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_USB_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_USB_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_USB_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_USB_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_RTC_CORE_INTR_MAP: RTC_CORE_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_RTC_CORE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RTC_CORE_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_RTC_CORE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_RTC_CORE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RTC_CORE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_RMT_INTR_MAP: RMT_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_RMT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RMT_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_RMT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_RMT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RMT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PCNT_INTR_MAP: PCNT_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PCNT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PCNT_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PCNT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PCNT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PCNT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_I2C_EXT0_INTR_MAP: I2C_EXT0_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_I2C_EXT0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_I2C_EXT0_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_I2C_EXT0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_I2C_EXT0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_I2C_EXT0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_I2C_EXT1_INTR_MAP: I2C_EXT1_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_I2C_EXT1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_I2C_EXT1_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_I2C_EXT1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_I2C_EXT1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_I2C_EXT1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_RSA_INTR_MAP: RSA_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_RSA_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_RSA_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_RSA_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_RSA_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_RSA_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SHA_INTR_MAP: SHA_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SHA_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SHA_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_SHA_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SHA_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SHA_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_AES_INTR_MAP: AES_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_AES_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_AES_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_AES_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_AES_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_AES_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SPI2_DMA_INT_MAP: SPI2_DMA_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SPI2_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI2_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI2_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SPI2_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI2_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SPI3_DMA_INT_MAP: SPI3_DMA_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SPI3_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI3_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI3_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SPI3_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI3_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_WDG_INT_MAP: WDG_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_WDG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_WDG_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_WDG_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_WDG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_WDG_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TIMER_INT1_MAP: TIMER_INT1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TIMER_INT1_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TIMER_INT1_MAP.Reg, volatile.LoadUint32(&o.PRO_TIMER_INT1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TIMER_INT1_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TIMER_INT1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TIMER_INT2_MAP: TIMER_INT2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TIMER_INT2_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TIMER_INT2_MAP.Reg, volatile.LoadUint32(&o.PRO_TIMER_INT2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TIMER_INT2_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TIMER_INT2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG_T0_EDGE_INT_MAP: TG_T0_EDGE_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG_T0_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_T0_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_T0_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG_T0_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_T0_EDGE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG_T1_EDGE_INT_MAP: TG_T1_EDGE_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG_T1_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_T1_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_T1_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG_T1_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_T1_EDGE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG_WDT_EDGE_INT_MAP: TG_WDT_EDGE_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG_WDT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_WDT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_WDT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG_WDT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_WDT_EDGE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG_LACT_EDGE_INT_MAP: TG_LACT_EDGE_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG_LACT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG_LACT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG_LACT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG_LACT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG_LACT_EDGE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG1_T0_EDGE_INT_MAP: TG1_T0_EDGE_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG1_T0_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_T0_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_T0_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG1_T0_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_T0_EDGE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG1_T1_EDGE_INT_MAP: TG1_T1_EDGE_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG1_T1_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_T1_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_T1_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG1_T1_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_T1_EDGE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG1_WDT_EDGE_INT_MAP: TG1_WDT_EDGE_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG1_WDT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_WDT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_WDT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG1_WDT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_WDT_EDGE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_TG1_LACT_EDGE_INT_MAP: TG1_LACT_EDGE_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_TG1_LACT_EDGE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_TG1_LACT_EDGE_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_TG1_LACT_EDGE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_TG1_LACT_EDGE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_TG1_LACT_EDGE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_CACHE_IA_INT_MAP: CACHE_IA_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_CACHE_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_IA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_CACHE_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_CACHE_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_IA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SYSTIMER_TARGET0_INT_MAP: SYSTIMER_TARGET0_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SYSTIMER_TARGET0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SYSTIMER_TARGET0_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_SYSTIMER_TARGET0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SYSTIMER_TARGET0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SYSTIMER_TARGET0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SYSTIMER_TARGET1_INT_MAP: SYSTIMER_TARGET1_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SYSTIMER_TARGET1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SYSTIMER_TARGET1_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_SYSTIMER_TARGET1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SYSTIMER_TARGET1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SYSTIMER_TARGET1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SYSTIMER_TARGET2_INT_MAP: SYSTIMER_TARGET2_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SYSTIMER_TARGET2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SYSTIMER_TARGET2_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_SYSTIMER_TARGET2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SYSTIMER_TARGET2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SYSTIMER_TARGET2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_ASSIST_DEBUG_INTR_MAP: ASSIST_DEBUG_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_ASSIST_DEBUG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_ASSIST_DEBUG_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_ASSIST_DEBUG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_ASSIST_DEBUG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_ASSIST_DEBUG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PMS_PRO_IRAM0_ILG_INTR_MAP: PMS_PRO_IRAM0_ILG interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PMS_PRO_IRAM0_ILG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PMS_PRO_IRAM0_ILG_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PMS_PRO_IRAM0_ILG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PMS_PRO_IRAM0_ILG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PMS_PRO_IRAM0_ILG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PMS_PRO_DRAM0_ILG_INTR_MAP: PMS_PRO_DRAM0_ILG interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PMS_PRO_DRAM0_ILG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PMS_PRO_DRAM0_ILG_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PMS_PRO_DRAM0_ILG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PMS_PRO_DRAM0_ILG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PMS_PRO_DRAM0_ILG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PMS_PRO_DPORT_ILG_INTR_MAP: PMS_PRO_DPORT_ILG interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PMS_PRO_DPORT_ILG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PMS_PRO_DPORT_ILG_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PMS_PRO_DPORT_ILG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PMS_PRO_DPORT_ILG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PMS_PRO_DPORT_ILG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PMS_PRO_AHB_ILG_INTR_MAP: PMS_PRO_AHB_ILG interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PMS_PRO_AHB_ILG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PMS_PRO_AHB_ILG_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PMS_PRO_AHB_ILG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PMS_PRO_AHB_ILG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PMS_PRO_AHB_ILG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PMS_PRO_CACHE_ILG_INTR_MAP: PMS_PRO_CACHE_ILG interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PMS_PRO_CACHE_ILG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PMS_PRO_CACHE_ILG_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PMS_PRO_CACHE_ILG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PMS_PRO_CACHE_ILG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PMS_PRO_CACHE_ILG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PMS_DMA_APB_I_ILG_INTR_MAP: PMS_DMA_APB_I_ILG interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PMS_DMA_APB_I_ILG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PMS_DMA_APB_I_ILG_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PMS_DMA_APB_I_ILG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PMS_DMA_APB_I_ILG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PMS_DMA_APB_I_ILG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PMS_DMA_RX_I_ILG_INTR_MAP: PMS_DMA_RX_I_ILG interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PMS_DMA_RX_I_ILG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PMS_DMA_RX_I_ILG_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PMS_DMA_RX_I_ILG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PMS_DMA_RX_I_ILG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PMS_DMA_RX_I_ILG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_PMS_DMA_TX_I_ILG_INTR_MAP: PMS_DMA_TX_I_ILG interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_PMS_DMA_TX_I_ILG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_PMS_DMA_TX_I_ILG_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_PMS_DMA_TX_I_ILG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_PMS_DMA_TX_I_ILG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_PMS_DMA_TX_I_ILG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SPI_MEM_REJECT_INTR_MAP: SPI_MEM_REJECT_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SPI_MEM_REJECT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI_MEM_REJECT_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI_MEM_REJECT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SPI_MEM_REJECT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI_MEM_REJECT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_DMA_COPY_INTR_MAP: DMA_COPY_INTR interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_DMA_COPY_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_DMA_COPY_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_DMA_COPY_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_DMA_COPY_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_DMA_COPY_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SPI4_DMA_INT_MAP: SPI4_DMA_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SPI4_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI4_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI4_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SPI4_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI4_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_SPI_INTR_4_MAP: SPI_INTR_4 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_SPI_INTR_4_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_SPI_INTR_4_MAP.Reg, volatile.LoadUint32(&o.PRO_SPI_INTR_4_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_SPI_INTR_4_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_SPI_INTR_4_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_DCACHE_PRELOAD_INT_MAP: DCACHE_PRELOAD_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_DCACHE_PRELOAD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_PRELOAD_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_DCACHE_PRELOAD_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_DCACHE_PRELOAD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_PRELOAD_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_ICACHE_PRELOAD_INT_MAP: ICACHE_PRELOAD_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_ICACHE_PRELOAD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_PRELOAD_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_ICACHE_PRELOAD_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_ICACHE_PRELOAD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_PRELOAD_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_APB_ADC_INT_MAP: APB_ADC_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_APB_ADC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_APB_ADC_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_APB_ADC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_APB_ADC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_APB_ADC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_CRYPTO_DMA_INT_MAP: CRYPTO_DMA_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_CRYPTO_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CRYPTO_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_CRYPTO_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_CRYPTO_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CRYPTO_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_CPU_PERI_ERROR_INT_MAP: CPU_PERI_ERROR_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_CPU_PERI_ERROR_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_CPU_PERI_ERROR_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_CPU_PERI_ERROR_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_CPU_PERI_ERROR_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_CPU_PERI_ERROR_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_APB_PERI_ERROR_INT_MAP: APB_PERI_ERROR_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_APB_PERI_ERROR_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_APB_PERI_ERROR_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_APB_PERI_ERROR_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_APB_PERI_ERROR_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_APB_PERI_ERROR_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_DCACHE_SYNC_INT_MAP: DCACHE_SYNC_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_DCACHE_SYNC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_DCACHE_SYNC_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_DCACHE_SYNC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_DCACHE_SYNC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_DCACHE_SYNC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_ICACHE_SYNC_INT_MAP: ICACHE_SYNC_INT interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_ICACHE_SYNC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_ICACHE_SYNC_INT_MAP.Reg, volatile.LoadUint32(&o.PRO_ICACHE_SYNC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_ICACHE_SYNC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_ICACHE_SYNC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_INTR_STATUS_0: Interrupt status register 0 +func (o *INTERRUPT_CORE0_Type) SetPRO_INTR_STATUS_0(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_0.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_INTR_STATUS_0() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_0.Reg) +} + +// INTERRUPT_CORE0.PRO_INTR_STATUS_1: Interrupt status register 1 +func (o *INTERRUPT_CORE0_Type) SetPRO_INTR_STATUS_1(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_1.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_INTR_STATUS_1() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_1.Reg) +} + +// INTERRUPT_CORE0.PRO_INTR_STATUS_2: Interrupt status register 2 +func (o *INTERRUPT_CORE0_Type) SetPRO_INTR_STATUS_2(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_2.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_INTR_STATUS_2() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_2.Reg) +} + +// INTERRUPT_CORE0.CLOCK_GATE: NMI interrupt signals mask register +func (o *INTERRUPT_CORE0_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} +func (o *INTERRUPT_CORE0_Type) SetCLOCK_GATE_PRO_NMI_MASK_HW(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x2)|value<<1) +} +func (o *INTERRUPT_CORE0_Type) GetCLOCK_GATE_PRO_NMI_MASK_HW() uint32 { + return (volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x2) >> 1 +} + +// INTERRUPT_CORE0.REG_DATE: Version control register +func (o *INTERRUPT_CORE0_Type) SetREG_DATE_INTERRUPT_REG_DATE(value uint32) { + volatile.StoreUint32(&o.REG_DATE.Reg, volatile.LoadUint32(&o.REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *INTERRUPT_CORE0_Type) GetREG_DATE_INTERRUPT_REG_DATE() uint32 { + return volatile.LoadUint32(&o.REG_DATE.Reg) & 0xfffffff +} + +// Input/Output Multiplexer +type IO_MUX_Type struct { + PIN_CTRL volatile.Register32 // 0x0 + GPIO0 volatile.Register32 // 0x4 + GPIO1 volatile.Register32 // 0x8 + GPIO2 volatile.Register32 // 0xC + GPIO3 volatile.Register32 // 0x10 + GPIO4 volatile.Register32 // 0x14 + GPIO5 volatile.Register32 // 0x18 + GPIO6 volatile.Register32 // 0x1C + GPIO7 volatile.Register32 // 0x20 + GPIO8 volatile.Register32 // 0x24 + GPIO9 volatile.Register32 // 0x28 + GPIO10 volatile.Register32 // 0x2C + GPIO11 volatile.Register32 // 0x30 + GPIO12 volatile.Register32 // 0x34 + GPIO13 volatile.Register32 // 0x38 + GPIO14 volatile.Register32 // 0x3C + GPIO15 volatile.Register32 // 0x40 + GPIO16 volatile.Register32 // 0x44 + GPIO17 volatile.Register32 // 0x48 + GPIO18 volatile.Register32 // 0x4C + GPIO19 volatile.Register32 // 0x50 + GPIO20 volatile.Register32 // 0x54 + GPIO21 volatile.Register32 // 0x58 + _ [16]byte + GPIO26 volatile.Register32 // 0x6C + GPIO27 volatile.Register32 // 0x70 + GPIO28 volatile.Register32 // 0x74 + GPIO29 volatile.Register32 // 0x78 + GPIO30 volatile.Register32 // 0x7C + GPIO31 volatile.Register32 // 0x80 + GPIO32 volatile.Register32 // 0x84 + GPIO33 volatile.Register32 // 0x88 + GPIO34 volatile.Register32 // 0x8C + GPIO35 volatile.Register32 // 0x90 + GPIO36 volatile.Register32 // 0x94 + GPIO37 volatile.Register32 // 0x98 + GPIO38 volatile.Register32 // 0x9C + GPIO39 volatile.Register32 // 0xA0 + GPIO40 volatile.Register32 // 0xA4 + GPIO41 volatile.Register32 // 0xA8 + GPIO42 volatile.Register32 // 0xAC + GPIO43 volatile.Register32 // 0xB0 + GPIO44 volatile.Register32 // 0xB4 + GPIO45 volatile.Register32 // 0xB8 + GPIO46 volatile.Register32 // 0xBC + _ [60]byte + DATE volatile.Register32 // 0xFC +} + +// IO_MUX.PIN_CTRL: Clock output configuration register +func (o *IO_MUX_Type) SetPIN_CTRL_PIN_CLK_OUT1(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf)|value) +} +func (o *IO_MUX_Type) GetPIN_CTRL_PIN_CLK_OUT1() uint32 { + return volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf +} +func (o *IO_MUX_Type) SetPIN_CTRL_PIN_CLK_OUT2(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf0)|value<<4) +} +func (o *IO_MUX_Type) GetPIN_CTRL_PIN_CLK_OUT2() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf0) >> 4 +} +func (o *IO_MUX_Type) SetPIN_CTRL_PIN_CLK_OUT3(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf00)|value<<8) +} +func (o *IO_MUX_Type) GetPIN_CTRL_PIN_CLK_OUT3() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf00) >> 8 +} +func (o *IO_MUX_Type) SetPIN_CTRL_SWITCH_PRT_NUM(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetPIN_CTRL_SWITCH_PRT_NUM() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetPIN_CTRL_PAD_POWER_CTRL(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetPIN_CTRL_PAD_POWER_CTRL() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO0: Configuration register for pin GPIO0 +func (o *IO_MUX_Type) SetGPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO1: Configuration register for pin GPIO1 +func (o *IO_MUX_Type) SetGPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO2: Configuration register for pin GPIO2 +func (o *IO_MUX_Type) SetGPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO3: Configuration register for pin GPIO3 +func (o *IO_MUX_Type) SetGPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO4: Configuration register for pin GPIO4 +func (o *IO_MUX_Type) SetGPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO5: Configuration register for pin GPIO5 +func (o *IO_MUX_Type) SetGPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO6: Configuration register for pin GPIO6 +func (o *IO_MUX_Type) SetGPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO7: Configuration register for pin GPIO7 +func (o *IO_MUX_Type) SetGPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO8: Configuration register for pin GPIO8 +func (o *IO_MUX_Type) SetGPIO8_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO8.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO8_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO8_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO9: Configuration register for pin GPIO9 +func (o *IO_MUX_Type) SetGPIO9_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO9.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO9_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO9_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO10: Configuration register for pin GPIO10 +func (o *IO_MUX_Type) SetGPIO10_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO10.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO10_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO10_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO11: Configuration register for pin GPIO11 +func (o *IO_MUX_Type) SetGPIO11_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO11.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO11_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO11_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO12: Configuration register for pin GPIO12 +func (o *IO_MUX_Type) SetGPIO12_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO12.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO12_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO12_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO13: Configuration register for pin GPIO13 +func (o *IO_MUX_Type) SetGPIO13_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO13.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO13_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO13_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO14: Configuration register for pin GPIO14 +func (o *IO_MUX_Type) SetGPIO14_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO14.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO14_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO14_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO15: Configuration register for pin GPIO15 +func (o *IO_MUX_Type) SetGPIO15_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO15.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO15_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO15_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO15_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO15_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO16: Configuration register for pin GPIO16 +func (o *IO_MUX_Type) SetGPIO16_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO16.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO16_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO16_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO16_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO16_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO17: Configuration register for pin GPIO17 +func (o *IO_MUX_Type) SetGPIO17_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO17.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO17_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO17_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO17_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO17_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO18: Configuration register for pin GPIO18 +func (o *IO_MUX_Type) SetGPIO18_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO18.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO18_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO18_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO18_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO18_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO19: Configuration register for pin GPIO19 +func (o *IO_MUX_Type) SetGPIO19_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO19.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO19_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO19_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO20: Configuration register for pin GPIO20 +func (o *IO_MUX_Type) SetGPIO20_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO20.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO20_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO20_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO21: Configuration register for pin GPIO21 +func (o *IO_MUX_Type) SetGPIO21_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO21.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO21_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO21_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO26: Configuration register for pin GPIO26 +func (o *IO_MUX_Type) SetGPIO26_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO26.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO26_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO26_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO26_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO26_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO27: Configuration register for pin GPIO27 +func (o *IO_MUX_Type) SetGPIO27_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO27.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO27_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO27_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO27_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO27_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO28: Configuration register for pin GPIO28 +func (o *IO_MUX_Type) SetGPIO28_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO28.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO28_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO28_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO28_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO28_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO29: Configuration register for pin GPIO29 +func (o *IO_MUX_Type) SetGPIO29_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO29.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO29_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO29_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO29_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO29_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO30: Configuration register for pin GPIO30 +func (o *IO_MUX_Type) SetGPIO30_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO30.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO30_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO30_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO30_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO30_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO31: Configuration register for pin GPIO31 +func (o *IO_MUX_Type) SetGPIO31_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO31.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO31_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO31_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO31_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO31_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO32: Configuration register for pin GPIO32 +func (o *IO_MUX_Type) SetGPIO32_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO32.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO32_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO32_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO32_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO32_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO33: Configuration register for pin GPIO33 +func (o *IO_MUX_Type) SetGPIO33_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO33.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO33_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO33_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO33_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO33_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO34: Configuration register for pin GPIO34 +func (o *IO_MUX_Type) SetGPIO34_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO34.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO34_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO34_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO34_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO34_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO35: Configuration register for pin GPIO35 +func (o *IO_MUX_Type) SetGPIO35_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO35.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO35_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO35_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO35_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO35_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO36: Configuration register for pin GPIO36 +func (o *IO_MUX_Type) SetGPIO36_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO36.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO36_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO36_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO36_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO36_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO37: Configuration register for pin GPIO37 +func (o *IO_MUX_Type) SetGPIO37_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO37.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO37_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO37_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO37_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO37_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO38: Configuration register for pin GPIO38 +func (o *IO_MUX_Type) SetGPIO38_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO38.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO38_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO38_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO38_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO38_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO39: Configuration register for pin GPIO39 +func (o *IO_MUX_Type) SetGPIO39_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO39.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO39_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO39_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO39_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO39_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO40: Configuration register for pin GPIO40 +func (o *IO_MUX_Type) SetGPIO40_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO40.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO40_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO40_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO40_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO40_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO41: Configuration register for pin GPIO41 +func (o *IO_MUX_Type) SetGPIO41_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO41.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO41_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO41_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO41_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO41_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO42: Configuration register for pin GPIO42 +func (o *IO_MUX_Type) SetGPIO42_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO42.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO42_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO42_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO42_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO42_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO43: Configuration register for pin GPIO43 +func (o *IO_MUX_Type) SetGPIO43_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO43.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO43_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO43_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO43_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO43_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO44: Configuration register for pin GPIO44 +func (o *IO_MUX_Type) SetGPIO44_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO44.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO44_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO44_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO44_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO44_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO45: Configuration register for pin GPIO45 +func (o *IO_MUX_Type) SetGPIO45_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO45.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO45_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO45_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO45_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO45_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO46: Configuration register for pin GPIO46 +func (o *IO_MUX_Type) SetGPIO46_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO46.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO46_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO46_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO46_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO46_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x8000) >> 15 +} + +// IO_MUX.DATE: Version control register +func (o *IO_MUX_Type) SetDATE_VERSION(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *IO_MUX_Type) GetDATE_VERSION() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// LED Control PWM (Pulse Width Modulation) +type LEDC_Type struct { + CH0_CONF0 volatile.Register32 // 0x0 + CH0_HPOINT volatile.Register32 // 0x4 + CH0_DUTY volatile.Register32 // 0x8 + CH0_CONF1 volatile.Register32 // 0xC + CH0_DUTY_R volatile.Register32 // 0x10 + CH1_CONF0 volatile.Register32 // 0x14 + CH1_HPOINT volatile.Register32 // 0x18 + CH1_DUTY volatile.Register32 // 0x1C + CH1_CONF1 volatile.Register32 // 0x20 + CH1_DUTY_R volatile.Register32 // 0x24 + CH2_CONF0 volatile.Register32 // 0x28 + CH2_HPOINT volatile.Register32 // 0x2C + CH2_DUTY volatile.Register32 // 0x30 + CH2_CONF1 volatile.Register32 // 0x34 + CH2_DUTY_R volatile.Register32 // 0x38 + CH3_CONF0 volatile.Register32 // 0x3C + CH3_HPOINT volatile.Register32 // 0x40 + CH3_DUTY volatile.Register32 // 0x44 + CH3_CONF1 volatile.Register32 // 0x48 + CH3_DUTY_R volatile.Register32 // 0x4C + CH4_CONF0 volatile.Register32 // 0x50 + CH4_HPOINT volatile.Register32 // 0x54 + CH4_DUTY volatile.Register32 // 0x58 + CH4_CONF1 volatile.Register32 // 0x5C + CH4_DUTY_R volatile.Register32 // 0x60 + CH5_CONF0 volatile.Register32 // 0x64 + CH5_HPOINT volatile.Register32 // 0x68 + CH5_DUTY volatile.Register32 // 0x6C + CH5_CONF1 volatile.Register32 // 0x70 + CH5_DUTY_R volatile.Register32 // 0x74 + CH6_CONF0 volatile.Register32 // 0x78 + CH6_HPOINT volatile.Register32 // 0x7C + CH6_DUTY volatile.Register32 // 0x80 + CH6_CONF1 volatile.Register32 // 0x84 + CH6_DUTY_R volatile.Register32 // 0x88 + CH7_CONF0 volatile.Register32 // 0x8C + CH7_HPOINT volatile.Register32 // 0x90 + CH7_DUTY volatile.Register32 // 0x94 + CH7_CONF1 volatile.Register32 // 0x98 + CH7_DUTY_R volatile.Register32 // 0x9C + TIMER0_CONF volatile.Register32 // 0xA0 + TIMER0_VALUE volatile.Register32 // 0xA4 + TIMER1_CONF volatile.Register32 // 0xA8 + TIMER1_VALUE volatile.Register32 // 0xAC + TIMER2_CONF volatile.Register32 // 0xB0 + TIMER2_VALUE volatile.Register32 // 0xB4 + TIMER3_CONF volatile.Register32 // 0xB8 + TIMER3_VALUE volatile.Register32 // 0xBC + INT_RAW volatile.Register32 // 0xC0 + INT_ST volatile.Register32 // 0xC4 + INT_ENA volatile.Register32 // 0xC8 + INT_CLR volatile.Register32 // 0xCC + CONF volatile.Register32 // 0xD0 + _ [40]byte + DATE volatile.Register32 // 0xFC +} + +// LEDC.CH0_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH0_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH0_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH0_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH0_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH0_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH0_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH0_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH0_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH0_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH0_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH0_HPOINT.Reg, volatile.LoadUint32(&o.CH0_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH0_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH0_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH0_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY.Reg, volatile.LoadUint32(&o.CH0_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH0_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH0_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH0_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY_R.Reg, volatile.LoadUint32(&o.CH0_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH1_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH1_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH1_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH1_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH1_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH1_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH1_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH1_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH1_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH1_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH1_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH1_HPOINT.Reg, volatile.LoadUint32(&o.CH1_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH1_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH1_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH1_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY.Reg, volatile.LoadUint32(&o.CH1_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH1_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH1_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH1_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY_R.Reg, volatile.LoadUint32(&o.CH1_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH2_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH2_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH2_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH2_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH2_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH2_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH2_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH2_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH2_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH2_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH2_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH2_HPOINT.Reg, volatile.LoadUint32(&o.CH2_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH2_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH2_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH2_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY.Reg, volatile.LoadUint32(&o.CH2_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH2_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH2_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH2_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY_R.Reg, volatile.LoadUint32(&o.CH2_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH3_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH3_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH3_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH3_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH3_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH3_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH3_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH3_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH3_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH3_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH3_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH3_HPOINT.Reg, volatile.LoadUint32(&o.CH3_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH3_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH3_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH3_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY.Reg, volatile.LoadUint32(&o.CH3_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH3_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH3_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH3_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY_R.Reg, volatile.LoadUint32(&o.CH3_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH4_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH4_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH4_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH4_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH4_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH4_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH4_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH4_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH4_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH4_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH4_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH4_HPOINT.Reg, volatile.LoadUint32(&o.CH4_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH4_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH4_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH4_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY.Reg, volatile.LoadUint32(&o.CH4_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH4_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH4_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH4_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY_R.Reg, volatile.LoadUint32(&o.CH4_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH5_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH5_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH5_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH5_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH5_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH5_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH5_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH5_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH5_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH5_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH5_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH5_HPOINT.Reg, volatile.LoadUint32(&o.CH5_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH5_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH5_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH5_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY.Reg, volatile.LoadUint32(&o.CH5_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH5_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH5_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH5_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY_R.Reg, volatile.LoadUint32(&o.CH5_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH6_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH6_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH6_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH6_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH6_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH6_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH6_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH6_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH6_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH6_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH6_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH6_HPOINT.Reg, volatile.LoadUint32(&o.CH6_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH6_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH6_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH6_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH6_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH6_DUTY.Reg, volatile.LoadUint32(&o.CH6_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH6_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH6_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH6_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH6_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH6_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH6_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH6_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH6_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH6_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH6_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH6_DUTY_R.Reg, volatile.LoadUint32(&o.CH6_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH6_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH6_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH7_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH7_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH7_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH7_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH7_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH7_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH7_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH7_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH7_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH7_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH7_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH7_HPOINT.Reg, volatile.LoadUint32(&o.CH7_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH7_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH7_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH7_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH7_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH7_DUTY.Reg, volatile.LoadUint32(&o.CH7_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH7_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH7_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH7_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH7_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH7_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH7_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH7_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH7_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH7_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH7_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH7_DUTY_R.Reg, volatile.LoadUint32(&o.CH7_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH7_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH7_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.TIMER0_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER0_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER0_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER0_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER0_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER0_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER0_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER0_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER0_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER0_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER0_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER0_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER0_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER0_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER0_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER0_VALUE.Reg, volatile.LoadUint32(&o.TIMER0_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER0_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER0_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER1_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER1_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER1_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER1_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER1_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER1_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER1_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER1_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER1_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER1_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER1_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER1_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER1_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER1_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER1_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER1_VALUE.Reg, volatile.LoadUint32(&o.TIMER1_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER1_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER1_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER2_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER2_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER2_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER2_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER2_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER2_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER2_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER2_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER2_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER2_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER2_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER2_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER2_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER2_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER2_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER2_VALUE.Reg, volatile.LoadUint32(&o.TIMER2_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER2_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER2_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER3_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER3_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER3_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER3_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER3_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER3_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER3_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER3_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER3_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER3_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER3_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER3_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER3_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER3_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER3_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER3_VALUE.Reg, volatile.LoadUint32(&o.TIMER3_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER3_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER3_VALUE.Reg) & 0x3fff +} + +// LEDC.INT_RAW: Raw interrupt status +func (o *LEDC_Type) SetINT_RAW_TIMER0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_RAW_TIMER0_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_RAW_TIMER1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_RAW_TIMER2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_RAW_TIMER3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_RAW_TIMER3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// LEDC.INT_ST: Masked interrupt status +func (o *LEDC_Type) SetINT_ST_TIMER0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ST_TIMER0_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ST_TIMER1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ST_TIMER1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ST_TIMER2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ST_TIMER2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ST_TIMER3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ST_TIMER3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH6_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH7_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH6_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH7_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// LEDC.INT_ENA: Interrupt enable bits +func (o *LEDC_Type) SetINT_ENA_TIMER0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ENA_TIMER0_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ENA_TIMER1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ENA_TIMER2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ENA_TIMER3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ENA_TIMER3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// LEDC.INT_CLR: Interrupt clear bits +func (o *LEDC_Type) SetINT_CLR_TIMER0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_CLR_TIMER0_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_CLR_TIMER1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_CLR_TIMER2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_CLR_TIMER3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_CLR_TIMER3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// LEDC.CONF: Global ledc configuration register +func (o *LEDC_Type) SetCONF_APB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCONF_APB_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x3 +} +func (o *LEDC_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// LEDC.DATE: Version control register +func (o *LEDC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *LEDC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Pulse Count Controller +type PCNT_Type struct { + U0_CONF0 volatile.Register32 // 0x0 + U0_CONF1 volatile.Register32 // 0x4 + U0_CONF2 volatile.Register32 // 0x8 + U1_CONF0 volatile.Register32 // 0xC + U1_CONF1 volatile.Register32 // 0x10 + U1_CONF2 volatile.Register32 // 0x14 + U2_CONF0 volatile.Register32 // 0x18 + U2_CONF1 volatile.Register32 // 0x1C + U2_CONF2 volatile.Register32 // 0x20 + U3_CONF0 volatile.Register32 // 0x24 + U3_CONF1 volatile.Register32 // 0x28 + U3_CONF2 volatile.Register32 // 0x2C + U0_CNT volatile.Register32 // 0x30 + U1_CNT volatile.Register32 // 0x34 + U2_CNT volatile.Register32 // 0x38 + U3_CNT volatile.Register32 // 0x3C + INT_RAW volatile.Register32 // 0x40 + INT_ST volatile.Register32 // 0x44 + INT_ENA volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + U0_STATUS volatile.Register32 // 0x50 + U1_STATUS volatile.Register32 // 0x54 + U2_STATUS volatile.Register32 // 0x58 + U3_STATUS volatile.Register32 // 0x5C + CTRL volatile.Register32 // 0x60 + _ [152]byte + DATE volatile.Register32 // 0xFC +} + +// PCNT.U0_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU0_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU0_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU0_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU0_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU0_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU0_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU0_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU0_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U0_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU0_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU1_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU1_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU1_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU1_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU1_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU1_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU1_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU1_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U1_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU1_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU2_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU2_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU2_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU2_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU2_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU2_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU2_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU2_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U2_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU2_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU3_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU3_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU3_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU3_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU3_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU3_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU3_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU3_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U3_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU3_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU0_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U0_CNT.Reg, volatile.LoadUint32(&o.U0_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U0_CNT.Reg) & 0xffff +} + +// PCNT.U1_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU1_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U1_CNT.Reg, volatile.LoadUint32(&o.U1_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U1_CNT.Reg) & 0xffff +} + +// PCNT.U2_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU2_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U2_CNT.Reg, volatile.LoadUint32(&o.U2_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U2_CNT.Reg) & 0xffff +} + +// PCNT.U3_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU3_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U3_CNT.Reg, volatile.LoadUint32(&o.U3_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U3_CNT.Reg) & 0xffff +} + +// PCNT.INT_RAW: Interrupt raw status register +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ST: Interrupt status register +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ENA: Interrupt enable register +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// PCNT.INT_CLR: Interrupt clear register +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// PCNT.U0_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU0_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU0_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU0_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU0_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU0_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU0_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU0_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU0_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU0_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU0_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U1_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU1_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU1_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU1_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU1_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU1_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU1_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU1_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU1_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU1_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU1_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U2_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU2_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU2_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU2_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU2_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU2_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU2_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU2_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU2_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU2_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU2_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U3_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU3_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU3_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU3_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU3_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU3_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU3_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU3_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU3_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU3_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU3_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.CTRL: Control register for all counters +func (o *PCNT_Type) SetCTRL_CNT_RST_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U0() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U0() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *PCNT_Type) SetCTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *PCNT_Type) GetCTRL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} + +// PCNT.DATE: PCNT version control register +func (o *PCNT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *PCNT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Permissions Controller +type PMS_Type struct { + SDIO_0 volatile.Register32 // 0x0 + SDIO_1 volatile.Register32 // 0x4 + MAC_DUMP_0 volatile.Register32 // 0x8 + MAC_DUMP_1 volatile.Register32 // 0xC + PRO_IRAM0_0 volatile.Register32 // 0x10 + PRO_IRAM0_1 volatile.Register32 // 0x14 + PRO_IRAM0_2 volatile.Register32 // 0x18 + PRO_IRAM0_3 volatile.Register32 // 0x1C + PRO_IRAM0_4 volatile.Register32 // 0x20 + PRO_IRAM0_5 volatile.Register32 // 0x24 + PRO_DRAM0_0 volatile.Register32 // 0x28 + PRO_DRAM0_1 volatile.Register32 // 0x2C + PRO_DRAM0_2 volatile.Register32 // 0x30 + PRO_DRAM0_3 volatile.Register32 // 0x34 + PRO_DRAM0_4 volatile.Register32 // 0x38 + PRO_DPORT_0 volatile.Register32 // 0x3C + PRO_DPORT_1 volatile.Register32 // 0x40 + PRO_DPORT_2 volatile.Register32 // 0x44 + PRO_DPORT_3 volatile.Register32 // 0x48 + PRO_DPORT_4 volatile.Register32 // 0x4C + PRO_DPORT_5 volatile.Register32 // 0x50 + PRO_DPORT_6 volatile.Register32 // 0x54 + PRO_DPORT_7 volatile.Register32 // 0x58 + PRO_AHB_0 volatile.Register32 // 0x5C + PRO_AHB_1 volatile.Register32 // 0x60 + PRO_AHB_2 volatile.Register32 // 0x64 + PRO_AHB_3 volatile.Register32 // 0x68 + PRO_AHB_4 volatile.Register32 // 0x6C + PRO_TRACE_0 volatile.Register32 // 0x70 + PRO_TRACE_1 volatile.Register32 // 0x74 + PRO_CACHE_0 volatile.Register32 // 0x78 + PRO_CACHE_1 volatile.Register32 // 0x7C + PRO_CACHE_2 volatile.Register32 // 0x80 + PRO_CACHE_3 volatile.Register32 // 0x84 + PRO_CACHE_4 volatile.Register32 // 0x88 + DMA_APB_I_0 volatile.Register32 // 0x8C + DMA_APB_I_1 volatile.Register32 // 0x90 + DMA_APB_I_2 volatile.Register32 // 0x94 + DMA_APB_I_3 volatile.Register32 // 0x98 + DMA_RX_I_0 volatile.Register32 // 0x9C + DMA_RX_I_1 volatile.Register32 // 0xA0 + DMA_RX_I_2 volatile.Register32 // 0xA4 + DMA_RX_I_3 volatile.Register32 // 0xA8 + DMA_TX_I_0 volatile.Register32 // 0xAC + DMA_TX_I_1 volatile.Register32 // 0xB0 + DMA_TX_I_2 volatile.Register32 // 0xB4 + DMA_TX_I_3 volatile.Register32 // 0xB8 + PRO_BOOT_LOCATION_0 volatile.Register32 // 0xBC + PRO_BOOT_LOCATION_1 volatile.Register32 // 0xC0 + CACHE_SOURCE_0 volatile.Register32 // 0xC4 + CACHE_SOURCE_1 volatile.Register32 // 0xC8 + APB_PERIPHERAL_0 volatile.Register32 // 0xCC + APB_PERIPHERAL_1 volatile.Register32 // 0xD0 + OCCUPY_0 volatile.Register32 // 0xD4 + OCCUPY_1 volatile.Register32 // 0xD8 + OCCUPY_2 volatile.Register32 // 0xDC + OCCUPY_3 volatile.Register32 // 0xE0 + CACHE_TAG_ACCESS_0 volatile.Register32 // 0xE4 + CACHE_TAG_ACCESS_1 volatile.Register32 // 0xE8 + CACHE_MMU_ACCESS_0 volatile.Register32 // 0xEC + CACHE_MMU_ACCESS_1 volatile.Register32 // 0xF0 + APB_PERIPHERAL_INTR volatile.Register32 // 0xF4 + APB_PERIPHERAL_STATUS volatile.Register32 // 0xF8 + CPU_PERIPHERAL_INTR volatile.Register32 // 0xFC + CPU_PERIPHERAL_STATUS volatile.Register32 // 0x100 + CLOCK_GATE volatile.Register32 // 0x104 + _ [3828]byte + DATE volatile.Register32 // 0xFFC +} + +// PMS.SDIO_0: SDIO permission control register 0. +func (o *PMS_Type) SetSDIO_0_SDIO_LOCK(value uint32) { + volatile.StoreUint32(&o.SDIO_0.Reg, volatile.LoadUint32(&o.SDIO_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetSDIO_0_SDIO_LOCK() uint32 { + return volatile.LoadUint32(&o.SDIO_0.Reg) & 0x1 +} + +// PMS.SDIO_1: SDIO permission control register 1. +func (o *PMS_Type) SetSDIO_1_SDIO_DISABLE(value uint32) { + volatile.StoreUint32(&o.SDIO_1.Reg, volatile.LoadUint32(&o.SDIO_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetSDIO_1_SDIO_DISABLE() uint32 { + return volatile.LoadUint32(&o.SDIO_1.Reg) & 0x1 +} + +// PMS.MAC_DUMP_0: MAC dump permission control register 0. +func (o *PMS_Type) SetMAC_DUMP_0_MAC_DUMP_LOCK(value uint32) { + volatile.StoreUint32(&o.MAC_DUMP_0.Reg, volatile.LoadUint32(&o.MAC_DUMP_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetMAC_DUMP_0_MAC_DUMP_LOCK() uint32 { + return volatile.LoadUint32(&o.MAC_DUMP_0.Reg) & 0x1 +} + +// PMS.MAC_DUMP_1: MAC dump permission control register 1. +func (o *PMS_Type) SetMAC_DUMP_1_MAC_DUMP_CONNECT(value uint32) { + volatile.StoreUint32(&o.MAC_DUMP_1.Reg, volatile.LoadUint32(&o.MAC_DUMP_1.Reg)&^(0xfff)|value) +} +func (o *PMS_Type) GetMAC_DUMP_1_MAC_DUMP_CONNECT() uint32 { + return volatile.LoadUint32(&o.MAC_DUMP_1.Reg) & 0xfff +} + +// PMS.PRO_IRAM0_0: IBUS permission control register 0. +func (o *PMS_Type) SetPRO_IRAM0_0_PRO_IRAM0_LOCK(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_0.Reg, volatile.LoadUint32(&o.PRO_IRAM0_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_IRAM0_0_PRO_IRAM0_LOCK() uint32 { + return volatile.LoadUint32(&o.PRO_IRAM0_0.Reg) & 0x1 +} + +// PMS.PRO_IRAM0_1: IBUS permission control register 1. +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_0_F(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_0_F() uint32 { + return volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x1 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_0_R(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_0_R() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_0_W(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_0_W() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x4) >> 2 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_1_F(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x8)|value<<3) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_1_F() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x8) >> 3 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_1_R(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x10)|value<<4) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_1_R() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x10) >> 4 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_1_W(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x20)|value<<5) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_1_W() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x20) >> 5 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_2_F(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x40)|value<<6) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_2_F() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x40) >> 6 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_2_R(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x80)|value<<7) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_2_R() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x80) >> 7 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_2_W(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x100)|value<<8) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_2_W() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x100) >> 8 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_3_F(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x200)|value<<9) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_3_F() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x200) >> 9 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_3_R(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x400)|value<<10) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_3_R() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x400) >> 10 +} +func (o *PMS_Type) SetPRO_IRAM0_1_PRO_IRAM0_SRAM_3_W(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_1.Reg, volatile.LoadUint32(&o.PRO_IRAM0_1.Reg)&^(0x800)|value<<11) +} +func (o *PMS_Type) GetPRO_IRAM0_1_PRO_IRAM0_SRAM_3_W() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_1.Reg) & 0x800) >> 11 +} + +// PMS.PRO_IRAM0_2: IBUS permission control register 2. +func (o *PMS_Type) SetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_2.Reg, volatile.LoadUint32(&o.PRO_IRAM0_2.Reg)&^(0x1ffff)|value) +} +func (o *PMS_Type) GetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_SPLTADDR() uint32 { + return volatile.LoadUint32(&o.PRO_IRAM0_2.Reg) & 0x1ffff +} +func (o *PMS_Type) SetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_F(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_2.Reg, volatile.LoadUint32(&o.PRO_IRAM0_2.Reg)&^(0x20000)|value<<17) +} +func (o *PMS_Type) GetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_F() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_2.Reg) & 0x20000) >> 17 +} +func (o *PMS_Type) SetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_R(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_2.Reg, volatile.LoadUint32(&o.PRO_IRAM0_2.Reg)&^(0x40000)|value<<18) +} +func (o *PMS_Type) GetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_R() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_2.Reg) & 0x40000) >> 18 +} +func (o *PMS_Type) SetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_W(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_2.Reg, volatile.LoadUint32(&o.PRO_IRAM0_2.Reg)&^(0x80000)|value<<19) +} +func (o *PMS_Type) GetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_W() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_2.Reg) & 0x80000) >> 19 +} +func (o *PMS_Type) SetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_F(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_2.Reg, volatile.LoadUint32(&o.PRO_IRAM0_2.Reg)&^(0x100000)|value<<20) +} +func (o *PMS_Type) GetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_F() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_2.Reg) & 0x100000) >> 20 +} +func (o *PMS_Type) SetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_R(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_2.Reg, volatile.LoadUint32(&o.PRO_IRAM0_2.Reg)&^(0x200000)|value<<21) +} +func (o *PMS_Type) GetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_R() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_2.Reg) & 0x200000) >> 21 +} +func (o *PMS_Type) SetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_W(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_2.Reg, volatile.LoadUint32(&o.PRO_IRAM0_2.Reg)&^(0x400000)|value<<22) +} +func (o *PMS_Type) GetPRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_W() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_2.Reg) & 0x400000) >> 22 +} + +// PMS.PRO_IRAM0_3: IBUS permission control register 3. +func (o *PMS_Type) SetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_3.Reg, volatile.LoadUint32(&o.PRO_IRAM0_3.Reg)&^(0x7ff)|value) +} +func (o *PMS_Type) GetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_SPLTADDR() uint32 { + return volatile.LoadUint32(&o.PRO_IRAM0_3.Reg) & 0x7ff +} +func (o *PMS_Type) SetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_F(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_3.Reg, volatile.LoadUint32(&o.PRO_IRAM0_3.Reg)&^(0x800)|value<<11) +} +func (o *PMS_Type) GetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_F() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_3.Reg) & 0x800) >> 11 +} +func (o *PMS_Type) SetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_R(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_3.Reg, volatile.LoadUint32(&o.PRO_IRAM0_3.Reg)&^(0x1000)|value<<12) +} +func (o *PMS_Type) GetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_R() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_3.Reg) & 0x1000) >> 12 +} +func (o *PMS_Type) SetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_W(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_3.Reg, volatile.LoadUint32(&o.PRO_IRAM0_3.Reg)&^(0x2000)|value<<13) +} +func (o *PMS_Type) GetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_W() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_3.Reg) & 0x2000) >> 13 +} +func (o *PMS_Type) SetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_F(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_3.Reg, volatile.LoadUint32(&o.PRO_IRAM0_3.Reg)&^(0x4000)|value<<14) +} +func (o *PMS_Type) GetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_F() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_3.Reg) & 0x4000) >> 14 +} +func (o *PMS_Type) SetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_R(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_3.Reg, volatile.LoadUint32(&o.PRO_IRAM0_3.Reg)&^(0x8000)|value<<15) +} +func (o *PMS_Type) GetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_R() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_3.Reg) & 0x8000) >> 15 +} +func (o *PMS_Type) SetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_W(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_3.Reg, volatile.LoadUint32(&o.PRO_IRAM0_3.Reg)&^(0x10000)|value<<16) +} +func (o *PMS_Type) GetPRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_W() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_3.Reg) & 0x10000) >> 16 +} + +// PMS.PRO_IRAM0_4: IBUS permission control register 4. +func (o *PMS_Type) SetPRO_IRAM0_4_PRO_IRAM0_ILG_CLR(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_4.Reg, volatile.LoadUint32(&o.PRO_IRAM0_4.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_IRAM0_4_PRO_IRAM0_ILG_CLR() uint32 { + return volatile.LoadUint32(&o.PRO_IRAM0_4.Reg) & 0x1 +} +func (o *PMS_Type) SetPRO_IRAM0_4_PRO_IRAM0_ILG_EN(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_4.Reg, volatile.LoadUint32(&o.PRO_IRAM0_4.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetPRO_IRAM0_4_PRO_IRAM0_ILG_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_4.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetPRO_IRAM0_4_PRO_IRAM0_ILG_INTR(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_4.Reg, volatile.LoadUint32(&o.PRO_IRAM0_4.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetPRO_IRAM0_4_PRO_IRAM0_ILG_INTR() uint32 { + return (volatile.LoadUint32(&o.PRO_IRAM0_4.Reg) & 0x4) >> 2 +} + +// PMS.PRO_IRAM0_5: IBUS status register. +func (o *PMS_Type) SetPRO_IRAM0_5_PRO_IRAM0_ILG_ST(value uint32) { + volatile.StoreUint32(&o.PRO_IRAM0_5.Reg, volatile.LoadUint32(&o.PRO_IRAM0_5.Reg)&^(0x3fffff)|value) +} +func (o *PMS_Type) GetPRO_IRAM0_5_PRO_IRAM0_ILG_ST() uint32 { + return volatile.LoadUint32(&o.PRO_IRAM0_5.Reg) & 0x3fffff +} + +// PMS.PRO_DRAM0_0: DBUS permission control register 0. +func (o *PMS_Type) SetPRO_DRAM0_0_PRO_DRAM0_LOCK(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_0.Reg, volatile.LoadUint32(&o.PRO_DRAM0_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_DRAM0_0_PRO_DRAM0_LOCK() uint32 { + return volatile.LoadUint32(&o.PRO_DRAM0_0.Reg) & 0x1 +} + +// PMS.PRO_DRAM0_1: DBUS permission control register 1. +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_0_R(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_0_R() uint32 { + return volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x1 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_0_W(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_0_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_1_R(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_1_R() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x4) >> 2 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_1_W(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x8)|value<<3) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_1_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x8) >> 3 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_2_R(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x10)|value<<4) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_2_R() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x10) >> 4 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_2_W(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x20)|value<<5) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_2_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x20) >> 5 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_3_R(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x40)|value<<6) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_3_R() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x40) >> 6 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_3_W(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x80)|value<<7) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_3_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x80) >> 7 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x1ffff00)|value<<8) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_SPLTADDR() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x1ffff00) >> 8 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_R(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x2000000)|value<<25) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_R() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x2000000) >> 25 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_W(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x4000000)|value<<26) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x4000000) >> 26 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_R(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x8000000)|value<<27) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_R() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x8000000) >> 27 +} +func (o *PMS_Type) SetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_W(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_1.Reg, volatile.LoadUint32(&o.PRO_DRAM0_1.Reg)&^(0x10000000)|value<<28) +} +func (o *PMS_Type) GetPRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_1.Reg) & 0x10000000) >> 28 +} + +// PMS.PRO_DRAM0_2: DBUS permission control register 2. +func (o *PMS_Type) SetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_2.Reg, volatile.LoadUint32(&o.PRO_DRAM0_2.Reg)&^(0x7ff)|value) +} +func (o *PMS_Type) GetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_SPLTADDR() uint32 { + return volatile.LoadUint32(&o.PRO_DRAM0_2.Reg) & 0x7ff +} +func (o *PMS_Type) SetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_R(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_2.Reg, volatile.LoadUint32(&o.PRO_DRAM0_2.Reg)&^(0x800)|value<<11) +} +func (o *PMS_Type) GetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_R() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_2.Reg) & 0x800) >> 11 +} +func (o *PMS_Type) SetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_W(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_2.Reg, volatile.LoadUint32(&o.PRO_DRAM0_2.Reg)&^(0x1000)|value<<12) +} +func (o *PMS_Type) GetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_2.Reg) & 0x1000) >> 12 +} +func (o *PMS_Type) SetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_R(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_2.Reg, volatile.LoadUint32(&o.PRO_DRAM0_2.Reg)&^(0x2000)|value<<13) +} +func (o *PMS_Type) GetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_R() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_2.Reg) & 0x2000) >> 13 +} +func (o *PMS_Type) SetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_W(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_2.Reg, volatile.LoadUint32(&o.PRO_DRAM0_2.Reg)&^(0x4000)|value<<14) +} +func (o *PMS_Type) GetPRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_2.Reg) & 0x4000) >> 14 +} + +// PMS.PRO_DRAM0_3: DBUS permission control register 3. +func (o *PMS_Type) SetPRO_DRAM0_3_PRO_DRAM0_ILG_CLR(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_3.Reg, volatile.LoadUint32(&o.PRO_DRAM0_3.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_DRAM0_3_PRO_DRAM0_ILG_CLR() uint32 { + return volatile.LoadUint32(&o.PRO_DRAM0_3.Reg) & 0x1 +} +func (o *PMS_Type) SetPRO_DRAM0_3_PRO_DRAM0_ILG_EN(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_3.Reg, volatile.LoadUint32(&o.PRO_DRAM0_3.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetPRO_DRAM0_3_PRO_DRAM0_ILG_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_3.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetPRO_DRAM0_3_PRO_DRAM0_ILG_INTR(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_3.Reg, volatile.LoadUint32(&o.PRO_DRAM0_3.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetPRO_DRAM0_3_PRO_DRAM0_ILG_INTR() uint32 { + return (volatile.LoadUint32(&o.PRO_DRAM0_3.Reg) & 0x4) >> 2 +} + +// PMS.PRO_DRAM0_4: DBUS status register. +func (o *PMS_Type) SetPRO_DRAM0_4_PRO_DRAM0_ILG_ST(value uint32) { + volatile.StoreUint32(&o.PRO_DRAM0_4.Reg, volatile.LoadUint32(&o.PRO_DRAM0_4.Reg)&^(0x3ffffff)|value) +} +func (o *PMS_Type) GetPRO_DRAM0_4_PRO_DRAM0_ILG_ST() uint32 { + return volatile.LoadUint32(&o.PRO_DRAM0_4.Reg) & 0x3ffffff +} + +// PMS.PRO_DPORT_0: PeriBus1 permission control register 0. +func (o *PMS_Type) SetPRO_DPORT_0_PRO_DPORT_LOCK(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_0.Reg, volatile.LoadUint32(&o.PRO_DPORT_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_DPORT_0_PRO_DPORT_LOCK() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_0.Reg) & 0x1 +} + +// PMS.PRO_DPORT_1: PeriBus1 permission control register 1. +func (o *PMS_Type) SetPRO_DPORT_1_PRO_DPORT_APB_PERIPHERAL_FORBID(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_1.Reg, volatile.LoadUint32(&o.PRO_DPORT_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_DPORT_1_PRO_DPORT_APB_PERIPHERAL_FORBID() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_1.Reg) & 0x1 +} +func (o *PMS_Type) SetPRO_DPORT_1_PRO_DPORT_RTCSLOW_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_1.Reg, volatile.LoadUint32(&o.PRO_DPORT_1.Reg)&^(0xffe)|value<<1) +} +func (o *PMS_Type) GetPRO_DPORT_1_PRO_DPORT_RTCSLOW_SPLTADDR() uint32 { + return (volatile.LoadUint32(&o.PRO_DPORT_1.Reg) & 0xffe) >> 1 +} +func (o *PMS_Type) SetPRO_DPORT_1_PRO_DPORT_RTCSLOW_L_R(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_1.Reg, volatile.LoadUint32(&o.PRO_DPORT_1.Reg)&^(0x1000)|value<<12) +} +func (o *PMS_Type) GetPRO_DPORT_1_PRO_DPORT_RTCSLOW_L_R() uint32 { + return (volatile.LoadUint32(&o.PRO_DPORT_1.Reg) & 0x1000) >> 12 +} +func (o *PMS_Type) SetPRO_DPORT_1_PRO_DPORT_RTCSLOW_L_W(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_1.Reg, volatile.LoadUint32(&o.PRO_DPORT_1.Reg)&^(0x2000)|value<<13) +} +func (o *PMS_Type) GetPRO_DPORT_1_PRO_DPORT_RTCSLOW_L_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DPORT_1.Reg) & 0x2000) >> 13 +} +func (o *PMS_Type) SetPRO_DPORT_1_PRO_DPORT_RTCSLOW_H_R(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_1.Reg, volatile.LoadUint32(&o.PRO_DPORT_1.Reg)&^(0x4000)|value<<14) +} +func (o *PMS_Type) GetPRO_DPORT_1_PRO_DPORT_RTCSLOW_H_R() uint32 { + return (volatile.LoadUint32(&o.PRO_DPORT_1.Reg) & 0x4000) >> 14 +} +func (o *PMS_Type) SetPRO_DPORT_1_PRO_DPORT_RTCSLOW_H_W(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_1.Reg, volatile.LoadUint32(&o.PRO_DPORT_1.Reg)&^(0x8000)|value<<15) +} +func (o *PMS_Type) GetPRO_DPORT_1_PRO_DPORT_RTCSLOW_H_W() uint32 { + return (volatile.LoadUint32(&o.PRO_DPORT_1.Reg) & 0x8000) >> 15 +} +func (o *PMS_Type) SetPRO_DPORT_1_PRO_DPORT_RESERVE_FIFO_VALID(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_1.Reg, volatile.LoadUint32(&o.PRO_DPORT_1.Reg)&^(0xf0000)|value<<16) +} +func (o *PMS_Type) GetPRO_DPORT_1_PRO_DPORT_RESERVE_FIFO_VALID() uint32 { + return (volatile.LoadUint32(&o.PRO_DPORT_1.Reg) & 0xf0000) >> 16 +} + +// PMS.PRO_DPORT_2: PeriBus1 permission control register 2. +func (o *PMS_Type) SetPRO_DPORT_2_PRO_DPORT_RESERVE_FIFO_0(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_2.Reg, volatile.LoadUint32(&o.PRO_DPORT_2.Reg)&^(0x3ffff)|value) +} +func (o *PMS_Type) GetPRO_DPORT_2_PRO_DPORT_RESERVE_FIFO_0() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_2.Reg) & 0x3ffff +} + +// PMS.PRO_DPORT_3: PeriBus1 permission control register 3. +func (o *PMS_Type) SetPRO_DPORT_3_PRO_DPORT_RESERVE_FIFO_1(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_3.Reg, volatile.LoadUint32(&o.PRO_DPORT_3.Reg)&^(0x3ffff)|value) +} +func (o *PMS_Type) GetPRO_DPORT_3_PRO_DPORT_RESERVE_FIFO_1() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_3.Reg) & 0x3ffff +} + +// PMS.PRO_DPORT_4: PeriBus1 permission control register 4. +func (o *PMS_Type) SetPRO_DPORT_4_PRO_DPORT_RESERVE_FIFO_2(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_4.Reg, volatile.LoadUint32(&o.PRO_DPORT_4.Reg)&^(0x3ffff)|value) +} +func (o *PMS_Type) GetPRO_DPORT_4_PRO_DPORT_RESERVE_FIFO_2() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_4.Reg) & 0x3ffff +} + +// PMS.PRO_DPORT_5: PeriBus1 permission control register 5. +func (o *PMS_Type) SetPRO_DPORT_5_PRO_DPORT_RESERVE_FIFO_3(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_5.Reg, volatile.LoadUint32(&o.PRO_DPORT_5.Reg)&^(0x3ffff)|value) +} +func (o *PMS_Type) GetPRO_DPORT_5_PRO_DPORT_RESERVE_FIFO_3() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_5.Reg) & 0x3ffff +} + +// PMS.PRO_DPORT_6: PeriBus1 permission control register 6. +func (o *PMS_Type) SetPRO_DPORT_6_PRO_DPORT_ILG_CLR(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_6.Reg, volatile.LoadUint32(&o.PRO_DPORT_6.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_DPORT_6_PRO_DPORT_ILG_CLR() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_6.Reg) & 0x1 +} +func (o *PMS_Type) SetPRO_DPORT_6_PRO_DPORT_ILG_EN(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_6.Reg, volatile.LoadUint32(&o.PRO_DPORT_6.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetPRO_DPORT_6_PRO_DPORT_ILG_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_DPORT_6.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetPRO_DPORT_6_PRO_DPORT_ILG_INTR(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_6.Reg, volatile.LoadUint32(&o.PRO_DPORT_6.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetPRO_DPORT_6_PRO_DPORT_ILG_INTR() uint32 { + return (volatile.LoadUint32(&o.PRO_DPORT_6.Reg) & 0x4) >> 2 +} + +// PMS.PRO_DPORT_7: PeriBus1 status register. +func (o *PMS_Type) SetPRO_DPORT_7_PRO_DPORT_ILG_ST(value uint32) { + volatile.StoreUint32(&o.PRO_DPORT_7.Reg, volatile.LoadUint32(&o.PRO_DPORT_7.Reg)&^(0x3ffffff)|value) +} +func (o *PMS_Type) GetPRO_DPORT_7_PRO_DPORT_ILG_ST() uint32 { + return volatile.LoadUint32(&o.PRO_DPORT_7.Reg) & 0x3ffffff +} + +// PMS.PRO_AHB_0: PeriBus2 permission control register 0. +func (o *PMS_Type) SetPRO_AHB_0_PRO_AHB_LOCK(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_0.Reg, volatile.LoadUint32(&o.PRO_AHB_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_AHB_0_PRO_AHB_LOCK() uint32 { + return volatile.LoadUint32(&o.PRO_AHB_0.Reg) & 0x1 +} + +// PMS.PRO_AHB_1: PeriBus2 permission control register 1. +func (o *PMS_Type) SetPRO_AHB_1_PRO_AHB_RTCSLOW_0_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_1.Reg, volatile.LoadUint32(&o.PRO_AHB_1.Reg)&^(0x7ff)|value) +} +func (o *PMS_Type) GetPRO_AHB_1_PRO_AHB_RTCSLOW_0_SPLTADDR() uint32 { + return volatile.LoadUint32(&o.PRO_AHB_1.Reg) & 0x7ff +} +func (o *PMS_Type) SetPRO_AHB_1_PRO_AHB_RTCSLOW_0_L_F(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_1.Reg, volatile.LoadUint32(&o.PRO_AHB_1.Reg)&^(0x800)|value<<11) +} +func (o *PMS_Type) GetPRO_AHB_1_PRO_AHB_RTCSLOW_0_L_F() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_1.Reg) & 0x800) >> 11 +} +func (o *PMS_Type) SetPRO_AHB_1_PRO_AHB_RTCSLOW_0_L_R(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_1.Reg, volatile.LoadUint32(&o.PRO_AHB_1.Reg)&^(0x1000)|value<<12) +} +func (o *PMS_Type) GetPRO_AHB_1_PRO_AHB_RTCSLOW_0_L_R() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_1.Reg) & 0x1000) >> 12 +} +func (o *PMS_Type) SetPRO_AHB_1_PRO_AHB_RTCSLOW_0_L_W(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_1.Reg, volatile.LoadUint32(&o.PRO_AHB_1.Reg)&^(0x2000)|value<<13) +} +func (o *PMS_Type) GetPRO_AHB_1_PRO_AHB_RTCSLOW_0_L_W() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_1.Reg) & 0x2000) >> 13 +} +func (o *PMS_Type) SetPRO_AHB_1_PRO_AHB_RTCSLOW_0_H_F(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_1.Reg, volatile.LoadUint32(&o.PRO_AHB_1.Reg)&^(0x4000)|value<<14) +} +func (o *PMS_Type) GetPRO_AHB_1_PRO_AHB_RTCSLOW_0_H_F() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_1.Reg) & 0x4000) >> 14 +} +func (o *PMS_Type) SetPRO_AHB_1_PRO_AHB_RTCSLOW_0_H_R(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_1.Reg, volatile.LoadUint32(&o.PRO_AHB_1.Reg)&^(0x8000)|value<<15) +} +func (o *PMS_Type) GetPRO_AHB_1_PRO_AHB_RTCSLOW_0_H_R() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_1.Reg) & 0x8000) >> 15 +} +func (o *PMS_Type) SetPRO_AHB_1_PRO_AHB_RTCSLOW_0_H_W(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_1.Reg, volatile.LoadUint32(&o.PRO_AHB_1.Reg)&^(0x10000)|value<<16) +} +func (o *PMS_Type) GetPRO_AHB_1_PRO_AHB_RTCSLOW_0_H_W() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_1.Reg) & 0x10000) >> 16 +} + +// PMS.PRO_AHB_2: PeriBus2 permission control register 2. +func (o *PMS_Type) SetPRO_AHB_2_PRO_AHB_RTCSLOW_1_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_2.Reg, volatile.LoadUint32(&o.PRO_AHB_2.Reg)&^(0x7ff)|value) +} +func (o *PMS_Type) GetPRO_AHB_2_PRO_AHB_RTCSLOW_1_SPLTADDR() uint32 { + return volatile.LoadUint32(&o.PRO_AHB_2.Reg) & 0x7ff +} +func (o *PMS_Type) SetPRO_AHB_2_PRO_AHB_RTCSLOW_1_L_F(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_2.Reg, volatile.LoadUint32(&o.PRO_AHB_2.Reg)&^(0x800)|value<<11) +} +func (o *PMS_Type) GetPRO_AHB_2_PRO_AHB_RTCSLOW_1_L_F() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_2.Reg) & 0x800) >> 11 +} +func (o *PMS_Type) SetPRO_AHB_2_PRO_AHB_RTCSLOW_1_L_R(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_2.Reg, volatile.LoadUint32(&o.PRO_AHB_2.Reg)&^(0x1000)|value<<12) +} +func (o *PMS_Type) GetPRO_AHB_2_PRO_AHB_RTCSLOW_1_L_R() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_2.Reg) & 0x1000) >> 12 +} +func (o *PMS_Type) SetPRO_AHB_2_PRO_AHB_RTCSLOW_1_L_W(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_2.Reg, volatile.LoadUint32(&o.PRO_AHB_2.Reg)&^(0x2000)|value<<13) +} +func (o *PMS_Type) GetPRO_AHB_2_PRO_AHB_RTCSLOW_1_L_W() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_2.Reg) & 0x2000) >> 13 +} +func (o *PMS_Type) SetPRO_AHB_2_PRO_AHB_RTCSLOW_1_H_F(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_2.Reg, volatile.LoadUint32(&o.PRO_AHB_2.Reg)&^(0x4000)|value<<14) +} +func (o *PMS_Type) GetPRO_AHB_2_PRO_AHB_RTCSLOW_1_H_F() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_2.Reg) & 0x4000) >> 14 +} +func (o *PMS_Type) SetPRO_AHB_2_PRO_AHB_RTCSLOW_1_H_R(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_2.Reg, volatile.LoadUint32(&o.PRO_AHB_2.Reg)&^(0x8000)|value<<15) +} +func (o *PMS_Type) GetPRO_AHB_2_PRO_AHB_RTCSLOW_1_H_R() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_2.Reg) & 0x8000) >> 15 +} +func (o *PMS_Type) SetPRO_AHB_2_PRO_AHB_RTCSLOW_1_H_W(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_2.Reg, volatile.LoadUint32(&o.PRO_AHB_2.Reg)&^(0x10000)|value<<16) +} +func (o *PMS_Type) GetPRO_AHB_2_PRO_AHB_RTCSLOW_1_H_W() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_2.Reg) & 0x10000) >> 16 +} + +// PMS.PRO_AHB_3: PeriBus2 permission control register 3. +func (o *PMS_Type) SetPRO_AHB_3_PRO_AHB_ILG_CLR(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_3.Reg, volatile.LoadUint32(&o.PRO_AHB_3.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_AHB_3_PRO_AHB_ILG_CLR() uint32 { + return volatile.LoadUint32(&o.PRO_AHB_3.Reg) & 0x1 +} +func (o *PMS_Type) SetPRO_AHB_3_PRO_AHB_ILG_EN(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_3.Reg, volatile.LoadUint32(&o.PRO_AHB_3.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetPRO_AHB_3_PRO_AHB_ILG_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_3.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetPRO_AHB_3_PRO_AHB_ILG_INTR(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_3.Reg, volatile.LoadUint32(&o.PRO_AHB_3.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetPRO_AHB_3_PRO_AHB_ILG_INTR() uint32 { + return (volatile.LoadUint32(&o.PRO_AHB_3.Reg) & 0x4) >> 2 +} + +// PMS.PRO_AHB_4: PeriBus2 status register. +func (o *PMS_Type) SetPRO_AHB_4(value uint32) { + volatile.StoreUint32(&o.PRO_AHB_4.Reg, value) +} +func (o *PMS_Type) GetPRO_AHB_4() uint32 { + return volatile.LoadUint32(&o.PRO_AHB_4.Reg) +} + +// PMS.PRO_TRACE_0: Trace memory permission control register 0. +func (o *PMS_Type) SetPRO_TRACE_0_PRO_TRACE_LOCK(value uint32) { + volatile.StoreUint32(&o.PRO_TRACE_0.Reg, volatile.LoadUint32(&o.PRO_TRACE_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_TRACE_0_PRO_TRACE_LOCK() uint32 { + return volatile.LoadUint32(&o.PRO_TRACE_0.Reg) & 0x1 +} + +// PMS.PRO_TRACE_1: Trace memory permission control register 1. +func (o *PMS_Type) SetPRO_TRACE_1_PRO_TRACE_DISABLE(value uint32) { + volatile.StoreUint32(&o.PRO_TRACE_1.Reg, volatile.LoadUint32(&o.PRO_TRACE_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_TRACE_1_PRO_TRACE_DISABLE() uint32 { + return volatile.LoadUint32(&o.PRO_TRACE_1.Reg) & 0x1 +} + +// PMS.PRO_CACHE_0: Cache permission control register 0. +func (o *PMS_Type) SetPRO_CACHE_0_PRO_CACHE_LOCK(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_0.Reg, volatile.LoadUint32(&o.PRO_CACHE_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_CACHE_0_PRO_CACHE_LOCK() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_0.Reg) & 0x1 +} + +// PMS.PRO_CACHE_1: Cache permission control register 1. +func (o *PMS_Type) SetPRO_CACHE_1_PRO_CACHE_CONNECT(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_1.Reg, volatile.LoadUint32(&o.PRO_CACHE_1.Reg)&^(0xffff)|value) +} +func (o *PMS_Type) GetPRO_CACHE_1_PRO_CACHE_CONNECT() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_1.Reg) & 0xffff +} + +// PMS.PRO_CACHE_2: Cache permission control register 2. +func (o *PMS_Type) SetPRO_CACHE_2_PRO_CACHE_ILG_CLR(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_2.Reg, volatile.LoadUint32(&o.PRO_CACHE_2.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_CACHE_2_PRO_CACHE_ILG_CLR() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_2.Reg) & 0x1 +} +func (o *PMS_Type) SetPRO_CACHE_2_PRO_CACHE_ILG_EN(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_2.Reg, volatile.LoadUint32(&o.PRO_CACHE_2.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetPRO_CACHE_2_PRO_CACHE_ILG_EN() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_2.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetPRO_CACHE_2_PRO_CACHE_ILG_INTR(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_2.Reg, volatile.LoadUint32(&o.PRO_CACHE_2.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetPRO_CACHE_2_PRO_CACHE_ILG_INTR() uint32 { + return (volatile.LoadUint32(&o.PRO_CACHE_2.Reg) & 0x4) >> 2 +} + +// PMS.PRO_CACHE_3: Icache status register. +func (o *PMS_Type) SetPRO_CACHE_3_PRO_CACHE_ILG_ST_I(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_3.Reg, volatile.LoadUint32(&o.PRO_CACHE_3.Reg)&^(0x1ffff)|value) +} +func (o *PMS_Type) GetPRO_CACHE_3_PRO_CACHE_ILG_ST_I() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_3.Reg) & 0x1ffff +} + +// PMS.PRO_CACHE_4: Dcache status register. +func (o *PMS_Type) SetPRO_CACHE_4_PRO_CACHE_ILG_ST_D(value uint32) { + volatile.StoreUint32(&o.PRO_CACHE_4.Reg, volatile.LoadUint32(&o.PRO_CACHE_4.Reg)&^(0x1ffff)|value) +} +func (o *PMS_Type) GetPRO_CACHE_4_PRO_CACHE_ILG_ST_D() uint32 { + return volatile.LoadUint32(&o.PRO_CACHE_4.Reg) & 0x1ffff +} + +// PMS.DMA_APB_I_0: Internal DMA permission control register 0. +func (o *PMS_Type) SetDMA_APB_I_0_DMA_APB_I_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_0.Reg, volatile.LoadUint32(&o.DMA_APB_I_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetDMA_APB_I_0_DMA_APB_I_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APB_I_0.Reg) & 0x1 +} + +// PMS.DMA_APB_I_1: Internal DMA permission control register 1. +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_0_R(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_0_R() uint32 { + return volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x1 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_0_W(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_0_W() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_1_R(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_1_R() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x4) >> 2 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_1_W(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x8)|value<<3) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_1_W() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x8) >> 3 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_2_R(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x10)|value<<4) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_2_R() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x10) >> 4 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_2_W(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x20)|value<<5) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_2_W() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x20) >> 5 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_3_R(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x40)|value<<6) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_3_R() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x40) >> 6 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_3_W(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x80)|value<<7) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_3_W() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x80) >> 7 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_4_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x1ffff00)|value<<8) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_4_SPLTADDR() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x1ffff00) >> 8 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_4_L_R(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x2000000)|value<<25) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_4_L_R() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x2000000) >> 25 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_4_L_W(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x4000000)|value<<26) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_4_L_W() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x4000000) >> 26 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_4_H_R(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x8000000)|value<<27) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_4_H_R() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x8000000) >> 27 +} +func (o *PMS_Type) SetDMA_APB_I_1_DMA_APB_I_SRAM_4_H_W(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_1.Reg, volatile.LoadUint32(&o.DMA_APB_I_1.Reg)&^(0x10000000)|value<<28) +} +func (o *PMS_Type) GetDMA_APB_I_1_DMA_APB_I_SRAM_4_H_W() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_1.Reg) & 0x10000000) >> 28 +} + +// PMS.DMA_APB_I_2: Internal DMA permission control register 2. +func (o *PMS_Type) SetDMA_APB_I_2_DMA_APB_I_ILG_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_2.Reg, volatile.LoadUint32(&o.DMA_APB_I_2.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetDMA_APB_I_2_DMA_APB_I_ILG_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_APB_I_2.Reg) & 0x1 +} +func (o *PMS_Type) SetDMA_APB_I_2_DMA_APB_I_ILG_EN(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_2.Reg, volatile.LoadUint32(&o.DMA_APB_I_2.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetDMA_APB_I_2_DMA_APB_I_ILG_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_2.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetDMA_APB_I_2_DMA_APB_I_ILG_INTR(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_2.Reg, volatile.LoadUint32(&o.DMA_APB_I_2.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetDMA_APB_I_2_DMA_APB_I_ILG_INTR() uint32 { + return (volatile.LoadUint32(&o.DMA_APB_I_2.Reg) & 0x4) >> 2 +} + +// PMS.DMA_APB_I_3: Internal DMA status register. +func (o *PMS_Type) SetDMA_APB_I_3_DMA_APB_I_ILG_ST(value uint32) { + volatile.StoreUint32(&o.DMA_APB_I_3.Reg, volatile.LoadUint32(&o.DMA_APB_I_3.Reg)&^(0x7fffff)|value) +} +func (o *PMS_Type) GetDMA_APB_I_3_DMA_APB_I_ILG_ST() uint32 { + return volatile.LoadUint32(&o.DMA_APB_I_3.Reg) & 0x7fffff +} + +// PMS.DMA_RX_I_0: RX Copy DMA permission control register 0. +func (o *PMS_Type) SetDMA_RX_I_0_DMA_RX_I_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_0.Reg, volatile.LoadUint32(&o.DMA_RX_I_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetDMA_RX_I_0_DMA_RX_I_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_RX_I_0.Reg) & 0x1 +} + +// PMS.DMA_RX_I_1: RX Copy DMA permission control register 1. +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_0_R(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_0_R() uint32 { + return volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x1 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_0_W(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_0_W() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_1_R(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_1_R() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x4) >> 2 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_1_W(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x8)|value<<3) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_1_W() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x8) >> 3 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_2_R(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x10)|value<<4) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_2_R() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x10) >> 4 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_2_W(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x20)|value<<5) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_2_W() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x20) >> 5 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_3_R(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x40)|value<<6) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_3_R() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x40) >> 6 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_3_W(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x80)|value<<7) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_3_W() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x80) >> 7 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_4_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x1ffff00)|value<<8) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_4_SPLTADDR() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x1ffff00) >> 8 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_4_L_R(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x2000000)|value<<25) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_4_L_R() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x2000000) >> 25 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_4_L_W(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x4000000)|value<<26) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_4_L_W() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x4000000) >> 26 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_4_H_R(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x8000000)|value<<27) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_4_H_R() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x8000000) >> 27 +} +func (o *PMS_Type) SetDMA_RX_I_1_DMA_RX_I_SRAM_4_H_W(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_1.Reg, volatile.LoadUint32(&o.DMA_RX_I_1.Reg)&^(0x10000000)|value<<28) +} +func (o *PMS_Type) GetDMA_RX_I_1_DMA_RX_I_SRAM_4_H_W() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_1.Reg) & 0x10000000) >> 28 +} + +// PMS.DMA_RX_I_2: RX Copy DMA permission control register 2. +func (o *PMS_Type) SetDMA_RX_I_2_DMA_RX_I_ILG_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_2.Reg, volatile.LoadUint32(&o.DMA_RX_I_2.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetDMA_RX_I_2_DMA_RX_I_ILG_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_RX_I_2.Reg) & 0x1 +} +func (o *PMS_Type) SetDMA_RX_I_2_DMA_RX_I_ILG_EN(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_2.Reg, volatile.LoadUint32(&o.DMA_RX_I_2.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetDMA_RX_I_2_DMA_RX_I_ILG_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_2.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetDMA_RX_I_2_DMA_RX_I_ILG_INTR(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_2.Reg, volatile.LoadUint32(&o.DMA_RX_I_2.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetDMA_RX_I_2_DMA_RX_I_ILG_INTR() uint32 { + return (volatile.LoadUint32(&o.DMA_RX_I_2.Reg) & 0x4) >> 2 +} + +// PMS.DMA_RX_I_3: RX Copy DMA status register. +func (o *PMS_Type) SetDMA_RX_I_3_DMA_RX_I_ILG_ST(value uint32) { + volatile.StoreUint32(&o.DMA_RX_I_3.Reg, volatile.LoadUint32(&o.DMA_RX_I_3.Reg)&^(0x7fffff)|value) +} +func (o *PMS_Type) GetDMA_RX_I_3_DMA_RX_I_ILG_ST() uint32 { + return volatile.LoadUint32(&o.DMA_RX_I_3.Reg) & 0x7fffff +} + +// PMS.DMA_TX_I_0: TX Copy DMA permission control register 0. +func (o *PMS_Type) SetDMA_TX_I_0_DMA_TX_I_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_0.Reg, volatile.LoadUint32(&o.DMA_TX_I_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetDMA_TX_I_0_DMA_TX_I_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_TX_I_0.Reg) & 0x1 +} + +// PMS.DMA_TX_I_1: TX Copy DMA permission control register 1. +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_0_R(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_0_R() uint32 { + return volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x1 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_0_W(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_0_W() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_1_R(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_1_R() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x4) >> 2 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_1_W(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x8)|value<<3) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_1_W() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x8) >> 3 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_2_R(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x10)|value<<4) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_2_R() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x10) >> 4 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_2_W(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x20)|value<<5) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_2_W() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x20) >> 5 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_3_R(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x40)|value<<6) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_3_R() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x40) >> 6 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_3_W(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x80)|value<<7) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_3_W() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x80) >> 7 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_4_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x1ffff00)|value<<8) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_4_SPLTADDR() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x1ffff00) >> 8 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_4_L_R(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x2000000)|value<<25) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_4_L_R() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x2000000) >> 25 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_4_L_W(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x4000000)|value<<26) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_4_L_W() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x4000000) >> 26 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_4_H_R(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x8000000)|value<<27) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_4_H_R() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x8000000) >> 27 +} +func (o *PMS_Type) SetDMA_TX_I_1_DMA_TX_I_SRAM_4_H_W(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_1.Reg, volatile.LoadUint32(&o.DMA_TX_I_1.Reg)&^(0x10000000)|value<<28) +} +func (o *PMS_Type) GetDMA_TX_I_1_DMA_TX_I_SRAM_4_H_W() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_1.Reg) & 0x10000000) >> 28 +} + +// PMS.DMA_TX_I_2: TX Copy DMA permission control register 2. +func (o *PMS_Type) SetDMA_TX_I_2_DMA_TX_I_ILG_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_2.Reg, volatile.LoadUint32(&o.DMA_TX_I_2.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetDMA_TX_I_2_DMA_TX_I_ILG_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_TX_I_2.Reg) & 0x1 +} +func (o *PMS_Type) SetDMA_TX_I_2_DMA_TX_I_ILG_EN(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_2.Reg, volatile.LoadUint32(&o.DMA_TX_I_2.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetDMA_TX_I_2_DMA_TX_I_ILG_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_2.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetDMA_TX_I_2_DMA_TX_I_ILG_INTR(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_2.Reg, volatile.LoadUint32(&o.DMA_TX_I_2.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetDMA_TX_I_2_DMA_TX_I_ILG_INTR() uint32 { + return (volatile.LoadUint32(&o.DMA_TX_I_2.Reg) & 0x4) >> 2 +} + +// PMS.DMA_TX_I_3: TX Copy DMA status register. +func (o *PMS_Type) SetDMA_TX_I_3_DMA_TX_I_ILG_ST(value uint32) { + volatile.StoreUint32(&o.DMA_TX_I_3.Reg, volatile.LoadUint32(&o.DMA_TX_I_3.Reg)&^(0x7fffff)|value) +} +func (o *PMS_Type) GetDMA_TX_I_3_DMA_TX_I_ILG_ST() uint32 { + return volatile.LoadUint32(&o.DMA_TX_I_3.Reg) & 0x7fffff +} + +// PMS.PRO_BOOT_LOCATION_0: Boot permission control register 0. +func (o *PMS_Type) SetPRO_BOOT_LOCATION_0_PRO_BOOT_LOCATION_LOCK(value uint32) { + volatile.StoreUint32(&o.PRO_BOOT_LOCATION_0.Reg, volatile.LoadUint32(&o.PRO_BOOT_LOCATION_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_BOOT_LOCATION_0_PRO_BOOT_LOCATION_LOCK() uint32 { + return volatile.LoadUint32(&o.PRO_BOOT_LOCATION_0.Reg) & 0x1 +} + +// PMS.PRO_BOOT_LOCATION_1: Boot permission control register 1. +func (o *PMS_Type) SetPRO_BOOT_LOCATION_1_PRO_BOOT_REMAP(value uint32) { + volatile.StoreUint32(&o.PRO_BOOT_LOCATION_1.Reg, volatile.LoadUint32(&o.PRO_BOOT_LOCATION_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetPRO_BOOT_LOCATION_1_PRO_BOOT_REMAP() uint32 { + return volatile.LoadUint32(&o.PRO_BOOT_LOCATION_1.Reg) & 0x1 +} + +// PMS.CACHE_SOURCE_0: Cache access permission control register 0. +func (o *PMS_Type) SetCACHE_SOURCE_0_CACHE_SOURCE_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_SOURCE_0.Reg, volatile.LoadUint32(&o.CACHE_SOURCE_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetCACHE_SOURCE_0_CACHE_SOURCE_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_SOURCE_0.Reg) & 0x1 +} + +// PMS.CACHE_SOURCE_1: Cache access permission control register 1. +func (o *PMS_Type) SetCACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IRAM1(value uint32) { + volatile.StoreUint32(&o.CACHE_SOURCE_1.Reg, volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetCACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IRAM1() uint32 { + return volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg) & 0x1 +} +func (o *PMS_Type) SetCACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IROM0(value uint32) { + volatile.StoreUint32(&o.CACHE_SOURCE_1.Reg, volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetCACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IROM0() uint32 { + return (volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetCACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_DROM0(value uint32) { + volatile.StoreUint32(&o.CACHE_SOURCE_1.Reg, volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetCACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_DROM0() uint32 { + return (volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg) & 0x4) >> 2 +} +func (o *PMS_Type) SetCACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DRAM0(value uint32) { + volatile.StoreUint32(&o.CACHE_SOURCE_1.Reg, volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg)&^(0x8)|value<<3) +} +func (o *PMS_Type) GetCACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DRAM0() uint32 { + return (volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg) & 0x8) >> 3 +} +func (o *PMS_Type) SetCACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DPORT(value uint32) { + volatile.StoreUint32(&o.CACHE_SOURCE_1.Reg, volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg)&^(0x10)|value<<4) +} +func (o *PMS_Type) GetCACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DPORT() uint32 { + return (volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg) & 0x10) >> 4 +} +func (o *PMS_Type) SetCACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DROM0(value uint32) { + volatile.StoreUint32(&o.CACHE_SOURCE_1.Reg, volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg)&^(0x20)|value<<5) +} +func (o *PMS_Type) GetCACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DROM0() uint32 { + return (volatile.LoadUint32(&o.CACHE_SOURCE_1.Reg) & 0x20) >> 5 +} + +// PMS.APB_PERIPHERAL_0: Peripheral access permission control register 0. +func (o *PMS_Type) SetAPB_PERIPHERAL_0_APB_PERIPHERAL_LOCK(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_0.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetAPB_PERIPHERAL_0_APB_PERIPHERAL_LOCK() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_0.Reg) & 0x1 +} + +// PMS.APB_PERIPHERAL_1: Peripheral access permission control register 1. +func (o *PMS_Type) SetAPB_PERIPHERAL_1_APB_PERIPHERAL_SPLIT_BURST(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_1.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetAPB_PERIPHERAL_1_APB_PERIPHERAL_SPLIT_BURST() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_1.Reg) & 0x1 +} + +// PMS.OCCUPY_0: Occupy permission control register 0. +func (o *PMS_Type) SetOCCUPY_0_OCCUPY_LOCK(value uint32) { + volatile.StoreUint32(&o.OCCUPY_0.Reg, volatile.LoadUint32(&o.OCCUPY_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetOCCUPY_0_OCCUPY_LOCK() uint32 { + return volatile.LoadUint32(&o.OCCUPY_0.Reg) & 0x1 +} + +// PMS.OCCUPY_1: Occupy permission control register 1. +func (o *PMS_Type) SetOCCUPY_1_OCCUPY_CACHE(value uint32) { + volatile.StoreUint32(&o.OCCUPY_1.Reg, volatile.LoadUint32(&o.OCCUPY_1.Reg)&^(0xf)|value) +} +func (o *PMS_Type) GetOCCUPY_1_OCCUPY_CACHE() uint32 { + return volatile.LoadUint32(&o.OCCUPY_1.Reg) & 0xf +} + +// PMS.OCCUPY_2: Occupy permission control register 2. +func (o *PMS_Type) SetOCCUPY_2_OCCUPY_MAC_DUMP(value uint32) { + volatile.StoreUint32(&o.OCCUPY_2.Reg, volatile.LoadUint32(&o.OCCUPY_2.Reg)&^(0xf)|value) +} +func (o *PMS_Type) GetOCCUPY_2_OCCUPY_MAC_DUMP() uint32 { + return volatile.LoadUint32(&o.OCCUPY_2.Reg) & 0xf +} + +// PMS.OCCUPY_3: Occupy permission control register 3. +func (o *PMS_Type) SetOCCUPY_3_OCCUPY_PRO_TRACE(value uint32) { + volatile.StoreUint32(&o.OCCUPY_3.Reg, volatile.LoadUint32(&o.OCCUPY_3.Reg)&^(0x3ffff)|value) +} +func (o *PMS_Type) GetOCCUPY_3_OCCUPY_PRO_TRACE() uint32 { + return volatile.LoadUint32(&o.OCCUPY_3.Reg) & 0x3ffff +} + +// PMS.CACHE_TAG_ACCESS_0: Cache tag permission control register 0. +func (o *PMS_Type) SetCACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_0.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetCACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_ACCESS_0.Reg) & 0x1 +} + +// PMS.CACHE_TAG_ACCESS_1: Cache tag permission control register 1. +func (o *PMS_Type) SetCACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetCACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x1 +} +func (o *PMS_Type) SetCACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetCACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetCACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetCACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x4) >> 2 +} +func (o *PMS_Type) SetCACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x8)|value<<3) +} +func (o *PMS_Type) GetCACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x8) >> 3 +} + +// PMS.CACHE_MMU_ACCESS_0: Cache MMU permission control register 0. +func (o *PMS_Type) SetCACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_0.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetCACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_ACCESS_0.Reg) & 0x1 +} + +// PMS.CACHE_MMU_ACCESS_1: Cache MMU permission control register 1. +func (o *PMS_Type) SetCACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetCACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg) & 0x1 +} +func (o *PMS_Type) SetCACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetCACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg) & 0x2) >> 1 +} + +// PMS.APB_PERIPHERAL_INTR: PeribBus2 permission control register. +func (o *PMS_Type) SetAPB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_CLR(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_INTR.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_INTR.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetAPB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_CLR() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_INTR.Reg) & 0x1 +} +func (o *PMS_Type) SetAPB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_EN(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_INTR.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_INTR.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetAPB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_EN() uint32 { + return (volatile.LoadUint32(&o.APB_PERIPHERAL_INTR.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetAPB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_INTR(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_INTR.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_INTR.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetAPB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_INTR() uint32 { + return (volatile.LoadUint32(&o.APB_PERIPHERAL_INTR.Reg) & 0x4) >> 2 +} + +// PMS.APB_PERIPHERAL_STATUS: PeribBus2 peripheral access status register. +func (o *PMS_Type) SetAPB_PERIPHERAL_STATUS(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_STATUS.Reg, value) +} +func (o *PMS_Type) GetAPB_PERIPHERAL_STATUS() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_STATUS.Reg) +} + +// PMS.CPU_PERIPHERAL_INTR: PeribBus1 permission control register. +func (o *PMS_Type) SetCPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_CLR(value uint32) { + volatile.StoreUint32(&o.CPU_PERIPHERAL_INTR.Reg, volatile.LoadUint32(&o.CPU_PERIPHERAL_INTR.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetCPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_CLR() uint32 { + return volatile.LoadUint32(&o.CPU_PERIPHERAL_INTR.Reg) & 0x1 +} +func (o *PMS_Type) SetCPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_EN(value uint32) { + volatile.StoreUint32(&o.CPU_PERIPHERAL_INTR.Reg, volatile.LoadUint32(&o.CPU_PERIPHERAL_INTR.Reg)&^(0x2)|value<<1) +} +func (o *PMS_Type) GetCPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_EN() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIPHERAL_INTR.Reg) & 0x2) >> 1 +} +func (o *PMS_Type) SetCPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_INTR(value uint32) { + volatile.StoreUint32(&o.CPU_PERIPHERAL_INTR.Reg, volatile.LoadUint32(&o.CPU_PERIPHERAL_INTR.Reg)&^(0x4)|value<<2) +} +func (o *PMS_Type) GetCPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_INTR() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIPHERAL_INTR.Reg) & 0x4) >> 2 +} + +// PMS.CPU_PERIPHERAL_STATUS: PeribBus1 peripheral access status register. +func (o *PMS_Type) SetCPU_PERIPHERAL_STATUS(value uint32) { + volatile.StoreUint32(&o.CPU_PERIPHERAL_STATUS.Reg, value) +} +func (o *PMS_Type) GetCPU_PERIPHERAL_STATUS() uint32 { + return volatile.LoadUint32(&o.CPU_PERIPHERAL_STATUS.Reg) +} + +// PMS.CLOCK_GATE: Clock gate register of permission control. +func (o *PMS_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *PMS_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// PMS.DATE: Version control register. +func (o *PMS_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *PMS_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Remote Control +type RMT_Type struct { + CH0DATA volatile.Register32 // 0x0 + CH1DATA volatile.Register32 // 0x4 + CH2DATA volatile.Register32 // 0x8 + CH3DATA volatile.Register32 // 0xC + CH0CONF0 volatile.Register32 // 0x10 + CH0CONF1 volatile.Register32 // 0x14 + CH1CONF0 volatile.Register32 // 0x18 + CH1CONF1 volatile.Register32 // 0x1C + CH2CONF0 volatile.Register32 // 0x20 + CH2CONF1 volatile.Register32 // 0x24 + CH3CONF0 volatile.Register32 // 0x28 + CH3CONF1 volatile.Register32 // 0x2C + CH0STATUS volatile.Register32 // 0x30 + CH1STATUS volatile.Register32 // 0x34 + CH2STATUS volatile.Register32 // 0x38 + CH3STATUS volatile.Register32 // 0x3C + CH0ADDR volatile.Register32 // 0x40 + CH1ADDR volatile.Register32 // 0x44 + CH2ADDR volatile.Register32 // 0x48 + CH3ADDR volatile.Register32 // 0x4C + INT_RAW volatile.Register32 // 0x50 + INT_ST volatile.Register32 // 0x54 + INT_ENA volatile.Register32 // 0x58 + INT_CLR volatile.Register32 // 0x5C + CH0CARRIER_DUTY volatile.Register32 // 0x60 + CH1CARRIER_DUTY volatile.Register32 // 0x64 + CH2CARRIER_DUTY volatile.Register32 // 0x68 + CH3CARRIER_DUTY volatile.Register32 // 0x6C + CH0_TX_LIM volatile.Register32 // 0x70 + CH1_TX_LIM volatile.Register32 // 0x74 + CH2_TX_LIM volatile.Register32 // 0x78 + CH3_TX_LIM volatile.Register32 // 0x7C + APB_CONF volatile.Register32 // 0x80 + TX_SIM volatile.Register32 // 0x84 + REF_CNT_RST volatile.Register32 // 0x88 + CH0_RX_CARRIER_RM volatile.Register32 // 0x8C + CH1_RX_CARRIER_RM volatile.Register32 // 0x90 + CH2_RX_CARRIER_RM volatile.Register32 // 0x94 + CH3_RX_CARRIER_RM volatile.Register32 // 0x98 + _ [96]byte + DATE volatile.Register32 // 0xFC +} + +// RMT.CH0DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH0DATA(value uint32) { + volatile.StoreUint32(&o.CH0DATA.Reg, value) +} +func (o *RMT_Type) GetCH0DATA() uint32 { + return volatile.LoadUint32(&o.CH0DATA.Reg) +} + +// RMT.CH1DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH1DATA(value uint32) { + volatile.StoreUint32(&o.CH1DATA.Reg, value) +} +func (o *RMT_Type) GetCH1DATA() uint32 { + return volatile.LoadUint32(&o.CH1DATA.Reg) +} + +// RMT.CH2DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH2DATA(value uint32) { + volatile.StoreUint32(&o.CH2DATA.Reg, value) +} +func (o *RMT_Type) GetCH2DATA() uint32 { + return volatile.LoadUint32(&o.CH2DATA.Reg) +} + +// RMT.CH3DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH3DATA(value uint32) { + volatile.StoreUint32(&o.CH3DATA.Reg, value) +} +func (o *RMT_Type) GetCH3DATA() uint32 { + return volatile.LoadUint32(&o.CH3DATA.Reg) +} + +// RMT.CH0CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH0CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH0CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH0CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH0CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH0CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH0CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH0CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH0CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH0CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH0CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH0CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH0CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0CONF0.Reg, volatile.LoadUint32(&o.CH0CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH0CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH0CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH0CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH0CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH0CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH0CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH0CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH0CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH0CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH0CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH0CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH0CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH0CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH0CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH0CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH0CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH0CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH0CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH0CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH0CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH0CONF1_CHK_RX_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH0CONF1_CHK_RX_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH0CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH0CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH0CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH0CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH0CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH0CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH0CONF1_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH0CONF1.Reg, volatile.LoadUint32(&o.CH0CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0CONF1_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH0CONF1.Reg) & 0x100000) >> 20 +} + +// RMT.CH1CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH1CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH1CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH1CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH1CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH1CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH1CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH1CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH1CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH1CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH1CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH1CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH1CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1CONF0.Reg, volatile.LoadUint32(&o.CH1CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH1CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH1CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH1CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH1CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH1CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH1CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH1CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH1CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH1CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH1CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH1CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH1CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH1CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH1CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH1CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH1CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH1CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH1CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH1CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH1CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH1CONF1_CHK_RX_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH1CONF1_CHK_RX_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH1CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH1CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH1CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH1CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH1CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH1CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH1CONF1_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH1CONF1.Reg, volatile.LoadUint32(&o.CH1CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1CONF1_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH1CONF1.Reg) & 0x100000) >> 20 +} + +// RMT.CH2CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH2CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH2CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH2CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH2CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH2CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH2CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH2CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH2CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH2CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH2CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH2CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH2CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH2CONF0.Reg, volatile.LoadUint32(&o.CH2CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH2CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH2CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH2CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH2CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH2CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH2CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH2CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH2CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH2CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH2CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH2CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH2CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH2CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH2CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH2CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH2CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH2CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH2CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH2CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH2CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH2CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH2CONF1_CHK_RX_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH2CONF1_CHK_RX_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH2CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH2CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH2CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH2CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH2CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH2CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH2CONF1_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH2CONF1.Reg, volatile.LoadUint32(&o.CH2CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH2CONF1_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH2CONF1.Reg) & 0x100000) >> 20 +} + +// RMT.CH3CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH3CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH3CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH3CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH3CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0xffff00)|value<<8) +} +func (o *RMT_Type) GetCH3CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0xffff00) >> 8 +} +func (o *RMT_Type) SetCH3CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0x7000000)|value<<24) +} +func (o *RMT_Type) GetCH3CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0x7000000) >> 24 +} +func (o *RMT_Type) SetCH3CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH3CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0x8000000) >> 27 +} +func (o *RMT_Type) SetCH3CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH3CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH3CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH3CONF0.Reg, volatile.LoadUint32(&o.CH3CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH3CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH3CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH3CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH3CONF1_TX_START(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH3CONF1_TX_START() uint32 { + return volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH3CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH3CONF1_RX_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH3CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH3CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH3CONF1_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH3CONF1_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH3CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH3CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH3CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH3CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH3CONF1_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH3CONF1_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH3CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH3CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH3CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH3CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH3CONF1_CHK_RX_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetCH3CONF1_CHK_RX_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetCH3CONF1_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x20000)|value<<17) +} +func (o *RMT_Type) GetCH3CONF1_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x20000) >> 17 +} +func (o *RMT_Type) SetCH3CONF1_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x40000)|value<<18) +} +func (o *RMT_Type) GetCH3CONF1_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x40000) >> 18 +} +func (o *RMT_Type) SetCH3CONF1_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH3CONF1_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH3CONF1_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH3CONF1.Reg, volatile.LoadUint32(&o.CH3CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH3CONF1_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH3CONF1.Reg) & 0x100000) >> 20 +} + +// RMT.CH0STATUS: Channel %s status register +func (o *RMT_Type) SetCH0STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x7fc00)|value<<10) +} +func (o *RMT_Type) GetCH0STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x7fc00) >> 10 +} +func (o *RMT_Type) SetCH0STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x700000)|value<<20) +} +func (o *RMT_Type) GetCH0STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x700000) >> 20 +} +func (o *RMT_Type) SetCH0STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH0STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH0STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH0STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetCH0STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH0STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH0STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH0STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH0STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH0STATUS.Reg, volatile.LoadUint32(&o.CH0STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH0STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH1STATUS: Channel %s status register +func (o *RMT_Type) SetCH1STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x7fc00)|value<<10) +} +func (o *RMT_Type) GetCH1STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x7fc00) >> 10 +} +func (o *RMT_Type) SetCH1STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x700000)|value<<20) +} +func (o *RMT_Type) GetCH1STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x700000) >> 20 +} +func (o *RMT_Type) SetCH1STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH1STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH1STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH1STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetCH1STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH1STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH1STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH1STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH1STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH1STATUS.Reg, volatile.LoadUint32(&o.CH1STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH1STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH2STATUS: Channel %s status register +func (o *RMT_Type) SetCH2STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH2STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x7fc00)|value<<10) +} +func (o *RMT_Type) GetCH2STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x7fc00) >> 10 +} +func (o *RMT_Type) SetCH2STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x700000)|value<<20) +} +func (o *RMT_Type) GetCH2STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x700000) >> 20 +} +func (o *RMT_Type) SetCH2STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH2STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH2STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH2STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetCH2STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH2STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH2STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH2STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH2STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH2STATUS.Reg, volatile.LoadUint32(&o.CH2STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH2STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH3STATUS: Channel %s status register +func (o *RMT_Type) SetCH3STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH3STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x7fc00)|value<<10) +} +func (o *RMT_Type) GetCH3STATUS_MEM_RADDR_EX() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x7fc00) >> 10 +} +func (o *RMT_Type) SetCH3STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x700000)|value<<20) +} +func (o *RMT_Type) GetCH3STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x700000) >> 20 +} +func (o *RMT_Type) SetCH3STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH3STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH3STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH3STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetCH3STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH3STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH3STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH3STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH3STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH3STATUS.Reg, volatile.LoadUint32(&o.CH3STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH3STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH0ADDR: Channel %s address register +func (o *RMT_Type) SetCH0ADDR_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH0ADDR.Reg, volatile.LoadUint32(&o.CH0ADDR.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0ADDR_APB_MEM_WADDR() uint32 { + return volatile.LoadUint32(&o.CH0ADDR.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0ADDR_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH0ADDR.Reg, volatile.LoadUint32(&o.CH0ADDR.Reg)&^(0x7fc00)|value<<10) +} +func (o *RMT_Type) GetCH0ADDR_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH0ADDR.Reg) & 0x7fc00) >> 10 +} + +// RMT.CH1ADDR: Channel %s address register +func (o *RMT_Type) SetCH1ADDR_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH1ADDR.Reg, volatile.LoadUint32(&o.CH1ADDR.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1ADDR_APB_MEM_WADDR() uint32 { + return volatile.LoadUint32(&o.CH1ADDR.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1ADDR_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH1ADDR.Reg, volatile.LoadUint32(&o.CH1ADDR.Reg)&^(0x7fc00)|value<<10) +} +func (o *RMT_Type) GetCH1ADDR_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH1ADDR.Reg) & 0x7fc00) >> 10 +} + +// RMT.CH2ADDR: Channel %s address register +func (o *RMT_Type) SetCH2ADDR_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH2ADDR.Reg, volatile.LoadUint32(&o.CH2ADDR.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2ADDR_APB_MEM_WADDR() uint32 { + return volatile.LoadUint32(&o.CH2ADDR.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH2ADDR_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH2ADDR.Reg, volatile.LoadUint32(&o.CH2ADDR.Reg)&^(0x7fc00)|value<<10) +} +func (o *RMT_Type) GetCH2ADDR_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH2ADDR.Reg) & 0x7fc00) >> 10 +} + +// RMT.CH3ADDR: Channel %s address register +func (o *RMT_Type) SetCH3ADDR_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH3ADDR.Reg, volatile.LoadUint32(&o.CH3ADDR.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3ADDR_APB_MEM_WADDR() uint32 { + return volatile.LoadUint32(&o.CH3ADDR.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH3ADDR_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH3ADDR.Reg, volatile.LoadUint32(&o.CH3ADDR.Reg)&^(0x7fc00)|value<<10) +} +func (o *RMT_Type) GetCH3ADDR_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH3ADDR.Reg) & 0x7fc00) >> 10 +} + +// RMT.INT_RAW: Raw interrupt status +func (o *RMT_Type) SetINT_RAW_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_RAW_CH_s_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_RAW_CH_s_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} + +// RMT.INT_ST: Masked interrupt status +func (o *RMT_Type) SetINT_ST_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_ST_CH_s_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ST_CH_s_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} + +// RMT.INT_ENA: Interrupt enable bits +func (o *RMT_Type) SetINT_ENA_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_ENA_CH_s_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_ENA_CH_s_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} + +// RMT.INT_CLR: Interrupt clear bits +func (o *RMT_Type) SetINT_CLR_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetINT_CLR_CH_s_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetINT_CLR_CH_s_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} + +// RMT.CH0CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH2CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH3CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH0_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x100000) >> 20 +} + +// RMT.CH1_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH1_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x100000) >> 20 +} + +// RMT.CH2_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH2_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH2_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH2_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH2_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH2_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x100000) >> 20 +} + +// RMT.CH3_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH3_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH3_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH3_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH3_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH3_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x100000) >> 20 +} + +// RMT.APB_CONF: RMT apb configuration register +func (o *RMT_Type) SetAPB_CONF_APB_FIFO_MASK(value uint32) { + volatile.StoreUint32(&o.APB_CONF.Reg, volatile.LoadUint32(&o.APB_CONF.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetAPB_CONF_APB_FIFO_MASK() uint32 { + return volatile.LoadUint32(&o.APB_CONF.Reg) & 0x1 +} +func (o *RMT_Type) SetAPB_CONF_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.APB_CONF.Reg, volatile.LoadUint32(&o.APB_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetAPB_CONF_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.APB_CONF.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetAPB_CONF_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.APB_CONF.Reg, volatile.LoadUint32(&o.APB_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetAPB_CONF_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.APB_CONF.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetAPB_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.APB_CONF.Reg, volatile.LoadUint32(&o.APB_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetAPB_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.APB_CONF.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetAPB_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.APB_CONF.Reg, volatile.LoadUint32(&o.APB_CONF.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetAPB_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.APB_CONF.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetAPB_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.APB_CONF.Reg, volatile.LoadUint32(&o.APB_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetAPB_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.APB_CONF.Reg) & 0x80000000) >> 31 +} + +// RMT.TX_SIM: RMT TX synchronous register +func (o *RMT_Type) SetTX_SIM_CH0(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_SIM_CH0() uint32 { + return volatile.LoadUint32(&o.TX_SIM.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_SIM_CH1(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_SIM_CH1() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_SIM_CH2(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_SIM_CH2() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetTX_SIM_CH3(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetTX_SIM_CH3() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetTX_SIM_EN(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetTX_SIM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x10) >> 4 +} + +// RMT.REF_CNT_RST: RMT clock divider reset register +func (o *RMT_Type) SetREF_CNT_RST_CH0(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetREF_CNT_RST_CH0() uint32 { + return volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x1 +} +func (o *RMT_Type) SetREF_CNT_RST_CH1(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetREF_CNT_RST_CH1() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetREF_CNT_RST_CH2(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetREF_CNT_RST_CH2() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetREF_CNT_RST_CH3(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetREF_CNT_RST_CH3() uint32 { + return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x8) >> 3 +} + +// RMT.CH0_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH2_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH3_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.DATE: RMT version register +func (o *RMT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *RMT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Hardware Random Number Generator +type RNG_Type struct { + _ [272]byte + DATA volatile.Register32 // 0x110 +} + +// RSA (Rivest Shamir Adleman) Accelerator +type RSA_Type struct { + M_MEM [512]volatile.Register8 // 0x0 + Z_MEM [512]volatile.Register8 // 0x200 + Y_MEM [512]volatile.Register8 // 0x400 + X_MEM [512]volatile.Register8 // 0x600 + M_PRIME volatile.Register32 // 0x800 + MODE volatile.Register32 // 0x804 + CLEAN volatile.Register32 // 0x808 + MODEXP_START volatile.Register32 // 0x80C + MODMULT_START volatile.Register32 // 0x810 + MULT_START volatile.Register32 // 0x814 + IDLE volatile.Register32 // 0x818 + CLEAR_INTERRUPT volatile.Register32 // 0x81C + CONSTANT_TIME volatile.Register32 // 0x820 + SEARCH_ENABLE volatile.Register32 // 0x824 + SEARCH_POS volatile.Register32 // 0x828 + INTERRUPT_ENA volatile.Register32 // 0x82C + DATE volatile.Register32 // 0x830 +} + +// RSA.M_PRIME: Register to store M' +func (o *RSA_Type) SetM_PRIME(value uint32) { + volatile.StoreUint32(&o.M_PRIME.Reg, value) +} +func (o *RSA_Type) GetM_PRIME() uint32 { + return volatile.LoadUint32(&o.M_PRIME.Reg) +} + +// RSA.MODE: RSA length mode +func (o *RSA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7f)|value) +} +func (o *RSA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7f +} + +// RSA.CLEAN: RSA clean register +func (o *RSA_Type) SetCLEAN(value uint32) { + volatile.StoreUint32(&o.CLEAN.Reg, volatile.LoadUint32(&o.CLEAN.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCLEAN() uint32 { + return volatile.LoadUint32(&o.CLEAN.Reg) & 0x1 +} + +// RSA.MODEXP_START: Modular exponentiation starting bit +func (o *RSA_Type) SetMODEXP_START(value uint32) { + volatile.StoreUint32(&o.MODEXP_START.Reg, volatile.LoadUint32(&o.MODEXP_START.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetMODEXP_START() uint32 { + return volatile.LoadUint32(&o.MODEXP_START.Reg) & 0x1 +} + +// RSA.MODMULT_START: Modular multiplication starting bit +func (o *RSA_Type) SetMODMULT_START(value uint32) { + volatile.StoreUint32(&o.MODMULT_START.Reg, volatile.LoadUint32(&o.MODMULT_START.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetMODMULT_START() uint32 { + return volatile.LoadUint32(&o.MODMULT_START.Reg) & 0x1 +} + +// RSA.MULT_START: Normal multiplication starting bit +func (o *RSA_Type) SetMULT_START(value uint32) { + volatile.StoreUint32(&o.MULT_START.Reg, volatile.LoadUint32(&o.MULT_START.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetMULT_START() uint32 { + return volatile.LoadUint32(&o.MULT_START.Reg) & 0x1 +} + +// RSA.IDLE: RSA idle register +func (o *RSA_Type) SetIDLE(value uint32) { + volatile.StoreUint32(&o.IDLE.Reg, volatile.LoadUint32(&o.IDLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetIDLE() uint32 { + return volatile.LoadUint32(&o.IDLE.Reg) & 0x1 +} + +// RSA.CLEAR_INTERRUPT: RSA clear interrupt register +func (o *RSA_Type) SetCLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CLEAR_INTERRUPT.Reg, volatile.LoadUint32(&o.CLEAR_INTERRUPT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.CLEAR_INTERRUPT.Reg) & 0x1 +} + +// RSA.CONSTANT_TIME: The constant_time option +func (o *RSA_Type) SetCONSTANT_TIME(value uint32) { + volatile.StoreUint32(&o.CONSTANT_TIME.Reg, volatile.LoadUint32(&o.CONSTANT_TIME.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCONSTANT_TIME() uint32 { + return volatile.LoadUint32(&o.CONSTANT_TIME.Reg) & 0x1 +} + +// RSA.SEARCH_ENABLE: The search option +func (o *RSA_Type) SetSEARCH_ENABLE(value uint32) { + volatile.StoreUint32(&o.SEARCH_ENABLE.Reg, volatile.LoadUint32(&o.SEARCH_ENABLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSEARCH_ENABLE() uint32 { + return volatile.LoadUint32(&o.SEARCH_ENABLE.Reg) & 0x1 +} + +// RSA.SEARCH_POS: The search position +func (o *RSA_Type) SetSEARCH_POS(value uint32) { + volatile.StoreUint32(&o.SEARCH_POS.Reg, volatile.LoadUint32(&o.SEARCH_POS.Reg)&^(0xfff)|value) +} +func (o *RSA_Type) GetSEARCH_POS() uint32 { + return volatile.LoadUint32(&o.SEARCH_POS.Reg) & 0xfff +} + +// RSA.INTERRUPT_ENA: RSA interrupt enable register +func (o *RSA_Type) SetINTERRUPT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENA.Reg, volatile.LoadUint32(&o.INTERRUPT_ENA.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINTERRUPT_ENA() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_ENA.Reg) & 0x1 +} + +// RSA.DATE: Version control register +func (o *RSA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *RSA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Low-power Input/Output +type RTCIO_Type struct { + RTC_GPIO_OUT volatile.Register32 // 0x0 + RTC_GPIO_OUT_W1TS volatile.Register32 // 0x4 + RTC_GPIO_OUT_W1TC volatile.Register32 // 0x8 + RTC_GPIO_ENABLE volatile.Register32 // 0xC + RTC_GPIO_ENABLE_W1TS volatile.Register32 // 0x10 + ENABLE_W1TC volatile.Register32 // 0x14 + RTC_GPIO_STATUS volatile.Register32 // 0x18 + RTC_GPIO_STATUS_W1TS volatile.Register32 // 0x1C + RTC_GPIO_STATUS_W1TC volatile.Register32 // 0x20 + RTC_GPIO_IN volatile.Register32 // 0x24 + PIN0 volatile.Register32 // 0x28 + PIN1 volatile.Register32 // 0x2C + PIN2 volatile.Register32 // 0x30 + PIN3 volatile.Register32 // 0x34 + PIN4 volatile.Register32 // 0x38 + PIN5 volatile.Register32 // 0x3C + PIN6 volatile.Register32 // 0x40 + PIN7 volatile.Register32 // 0x44 + PIN8 volatile.Register32 // 0x48 + PIN9 volatile.Register32 // 0x4C + PIN10 volatile.Register32 // 0x50 + PIN11 volatile.Register32 // 0x54 + PIN12 volatile.Register32 // 0x58 + PIN13 volatile.Register32 // 0x5C + PIN14 volatile.Register32 // 0x60 + PIN15 volatile.Register32 // 0x64 + PIN16 volatile.Register32 // 0x68 + PIN17 volatile.Register32 // 0x6C + PIN18 volatile.Register32 // 0x70 + PIN19 volatile.Register32 // 0x74 + PIN20 volatile.Register32 // 0x78 + PIN21 volatile.Register32 // 0x7C + RTC_DEBUG_SEL volatile.Register32 // 0x80 + TOUCH_PAD0 volatile.Register32 // 0x84 + TOUCH_PAD1 volatile.Register32 // 0x88 + TOUCH_PAD2 volatile.Register32 // 0x8C + TOUCH_PAD3 volatile.Register32 // 0x90 + TOUCH_PAD4 volatile.Register32 // 0x94 + TOUCH_PAD5 volatile.Register32 // 0x98 + TOUCH_PAD6 volatile.Register32 // 0x9C + TOUCH_PAD7 volatile.Register32 // 0xA0 + TOUCH_PAD8 volatile.Register32 // 0xA4 + TOUCH_PAD9 volatile.Register32 // 0xA8 + TOUCH_PAD10 volatile.Register32 // 0xAC + TOUCH_PAD11 volatile.Register32 // 0xB0 + TOUCH_PAD12 volatile.Register32 // 0xB4 + TOUCH_PAD13 volatile.Register32 // 0xB8 + TOUCH_PAD14 volatile.Register32 // 0xBC + XTAL_32P_PAD volatile.Register32 // 0xC0 + XTAL_32N_PAD volatile.Register32 // 0xC4 + PAD_DAC1 volatile.Register32 // 0xC8 + PAD_DAC2 volatile.Register32 // 0xCC + RTC_PAD19 volatile.Register32 // 0xD0 + RTC_PAD20 volatile.Register32 // 0xD4 + RTC_PAD21 volatile.Register32 // 0xD8 + EXT_WAKEUP0 volatile.Register32 // 0xDC + XTL_EXT_CTR volatile.Register32 // 0xE0 + SAR_I2C_IO volatile.Register32 // 0xE4 + RTC_IO_TOUCH_CTRL volatile.Register32 // 0xE8 + _ [272]byte + RTC_IO_DATE volatile.Register32 // 0x1FC +} + +// RTCIO.RTC_GPIO_OUT: RTC GPIO output register +func (o *RTCIO_Type) SetRTC_GPIO_OUT_GPIO_OUT_DATA(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_OUT_GPIO_OUT_DATA() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_OUT_W1TS: RTC GPIO output bit set register +func (o *RTCIO_Type) SetRTC_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_OUT_W1TC: RTC GPIO output bit clear register +func (o *RTCIO_Type) SetRTC_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_ENABLE: RTC GPIO output enable register +func (o *RTCIO_Type) SetRTC_GPIO_ENABLE_REG_RTCIO_REG_GPIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_ENABLE_REG_RTCIO_REG_GPIO_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_ENABLE_W1TS: RTC GPIO output enable bit set register +func (o *RTCIO_Type) SetRTC_GPIO_ENABLE_W1TS_REG_RTCIO_REG_GPIO_ENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_ENABLE_W1TS_REG_RTCIO_REG_GPIO_ENABLE_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.ENABLE_W1TC: RTC GPIO output enable bit clear register +func (o *RTCIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, volatile.LoadUint32(&o.ENABLE_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetENABLE_W1TC() uint32 { + return (volatile.LoadUint32(&o.ENABLE_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_STATUS: RTC GPIO interrupt status register +func (o *RTCIO_Type) SetRTC_GPIO_STATUS_GPIO_STATUS_INT(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_STATUS_GPIO_STATUS_INT() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_STATUS_W1TS: RTC GPIO interrupt status bit set register +func (o *RTCIO_Type) SetRTC_GPIO_STATUS_W1TS_GPIO_STATUS_INT_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_STATUS_W1TS_GPIO_STATUS_INT_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_STATUS_W1TC: RTC GPIO interrupt status bit clear register +func (o *RTCIO_Type) SetRTC_GPIO_STATUS_W1TC_GPIO_STATUS_INT_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_STATUS_W1TC_GPIO_STATUS_INT_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_IN: RTC GPIO input register +func (o *RTCIO_Type) SetRTC_GPIO_IN_GPIO_IN_NEXT(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_IN.Reg, volatile.LoadUint32(&o.RTC_GPIO_IN.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_IN_GPIO_IN_NEXT() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_IN.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.PIN0: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN0_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN0_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN0_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN0_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN1: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN1_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN1_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN1_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN1_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN2: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN2_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN2_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN2_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN2_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN3: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN3_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN3_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN3_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN3_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN4: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN4_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN4_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN4_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN4_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN5: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN5_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN5_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN5_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN5_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN6: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN6_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN6_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN6_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN6_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN7: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN7_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN7_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN7_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN7_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN8: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN8_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN8_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN8_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN8_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN9: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN9_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN9_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN9_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN9_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN10: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN10_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN10_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN10_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN10_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN11: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN11_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN11_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN11_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN11_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN12: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN12_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN12_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN12_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN12_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN13: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN13_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN13_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN13_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN13_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN14: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN14_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN14_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN14_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN14_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN15: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN15_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN15_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN15_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN15_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN16: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN16_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN16_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN16_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN16_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN17: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN17_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN17_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN17_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN17_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN18: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN18_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN18_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN18_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN18_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN19: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN19_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN19_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN19_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN19_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN20: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN20_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN20_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN20_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN20_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} + +// RTCIO.PIN21: RTC configuration for pin %s +func (o *RTCIO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetPIN21_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetPIN21_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetPIN21_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetPIN21_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_DEBUG_SEL: RTC debug select register +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f)|value) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL0() uint32 { + return volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x3e0)|value<<5) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x3e0) >> 5 +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x7c00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x7c00) >> 10 +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0xf8000)|value<<15) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0xf8000) >> 15 +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f00000)|value<<20) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL4() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f00000) >> 20 +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x2000000)|value<<25) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x2000000) >> 25 +} + +// RTCIO.TOUCH_PAD0: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD1: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD2: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD3: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD4: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD5: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD6: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD7: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD8: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD9: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD10: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD11: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD12: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD13: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD14: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x60000000) >> 29 +} + +// RTCIO.XTAL_32P_PAD: 32KHz crystal P-pad configuration register +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x60000000) >> 29 +} + +// RTCIO.XTAL_32N_PAD: 32KHz crystal N-pad configuration register +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x60000000) >> 29 +} + +// RTCIO.PAD_DAC1: DAC1 configuration register +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x7f8)|value<<3) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x7f8) >> 3 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x800)|value<<11) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x800) >> 11 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x1000)|value<<12) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x1000) >> 12 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x60000000) >> 29 +} + +// RTCIO.PAD_DAC2: DAC2 configuration register +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x7f8)|value<<3) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x7f8) >> 3 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x800)|value<<11) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x800) >> 11 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x1000)|value<<12) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x1000) >> 12 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x60000000) >> 29 +} + +// RTCIO.RTC_PAD19: Touch pad 19 configuration register +func (o *RTCIO_Type) SetRTC_PAD19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetRTC_PAD19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetRTC_PAD19_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetRTC_PAD19_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetRTC_PAD19_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetRTC_PAD19_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetRTC_PAD19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetRTC_PAD19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetRTC_PAD19_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetRTC_PAD19_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetRTC_PAD19_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetRTC_PAD19_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetRTC_PAD19_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetRTC_PAD19_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetRTC_PAD19_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetRTC_PAD19_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetRTC_PAD19_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetRTC_PAD19_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x60000000) >> 29 +} + +// RTCIO.RTC_PAD20: Touch pad 20 configuration register +func (o *RTCIO_Type) SetRTC_PAD20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetRTC_PAD20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetRTC_PAD20_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetRTC_PAD20_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetRTC_PAD20_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetRTC_PAD20_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetRTC_PAD20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetRTC_PAD20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetRTC_PAD20_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetRTC_PAD20_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetRTC_PAD20_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetRTC_PAD20_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetRTC_PAD20_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetRTC_PAD20_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetRTC_PAD20_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetRTC_PAD20_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetRTC_PAD20_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetRTC_PAD20_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x60000000) >> 29 +} + +// RTCIO.RTC_PAD21: Touch pad 21 configuration register +func (o *RTCIO_Type) SetRTC_PAD21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetRTC_PAD21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetRTC_PAD21_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetRTC_PAD21_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetRTC_PAD21_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetRTC_PAD21_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetRTC_PAD21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetRTC_PAD21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetRTC_PAD21_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetRTC_PAD21_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetRTC_PAD21_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetRTC_PAD21_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetRTC_PAD21_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetRTC_PAD21_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetRTC_PAD21_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetRTC_PAD21_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetRTC_PAD21_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetRTC_PAD21_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x60000000) >> 29 +} + +// RTCIO.EXT_WAKEUP0: External wake up configuration register +func (o *RTCIO_Type) SetEXT_WAKEUP0_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP0.Reg, volatile.LoadUint32(&o.EXT_WAKEUP0.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTCIO_Type) GetEXT_WAKEUP0_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP0.Reg) & 0xf8000000) >> 27 +} + +// RTCIO.XTL_EXT_CTR: Crystal power down enable GPIO source +func (o *RTCIO_Type) SetXTL_EXT_CTR_SEL(value uint32) { + volatile.StoreUint32(&o.XTL_EXT_CTR.Reg, volatile.LoadUint32(&o.XTL_EXT_CTR.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTCIO_Type) GetXTL_EXT_CTR_SEL() uint32 { + return (volatile.LoadUint32(&o.XTL_EXT_CTR.Reg) & 0xf8000000) >> 27 +} + +// RTCIO.SAR_I2C_IO: RTC I2C pad selection +func (o *RTCIO_Type) SetSAR_I2C_IO_SAR_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xf800000)|value<<23) +} +func (o *RTCIO_Type) GetSAR_I2C_IO_SAR_DEBUG_BIT_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xf800000) >> 23 +} +func (o *RTCIO_Type) SetSAR_I2C_IO_SAR_I2C_SCL_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0x30000000)|value<<28) +} +func (o *RTCIO_Type) GetSAR_I2C_IO_SAR_I2C_SCL_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0x30000000) >> 28 +} +func (o *RTCIO_Type) SetSAR_I2C_IO_SAR_I2C_SDA_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTCIO_Type) GetSAR_I2C_IO_SAR_I2C_SDA_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xc0000000) >> 30 +} + +// RTCIO.RTC_IO_TOUCH_CTRL: Touch control register +func (o *RTCIO_Type) SetRTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL(value uint32) { + volatile.StoreUint32(&o.RTC_IO_TOUCH_CTRL.Reg, volatile.LoadUint32(&o.RTC_IO_TOUCH_CTRL.Reg)&^(0xf)|value) +} +func (o *RTCIO_Type) GetRTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL() uint32 { + return volatile.LoadUint32(&o.RTC_IO_TOUCH_CTRL.Reg) & 0xf +} +func (o *RTCIO_Type) SetRTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE(value uint32) { + volatile.StoreUint32(&o.RTC_IO_TOUCH_CTRL.Reg, volatile.LoadUint32(&o.RTC_IO_TOUCH_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *RTCIO_Type) GetRTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE() uint32 { + return (volatile.LoadUint32(&o.RTC_IO_TOUCH_CTRL.Reg) & 0x10) >> 4 +} + +// RTCIO.RTC_IO_DATE: Version control register +func (o *RTCIO_Type) SetRTC_IO_DATE_IO_DATE(value uint32) { + volatile.StoreUint32(&o.RTC_IO_DATE.Reg, volatile.LoadUint32(&o.RTC_IO_DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTCIO_Type) GetRTC_IO_DATE_IO_DATE() uint32 { + return volatile.LoadUint32(&o.RTC_IO_DATE.Reg) & 0xfffffff +} + +// Real-Time Clock Control +type RTC_CNTL_Type struct { + OPTIONS0 volatile.Register32 // 0x0 + SLP_TIMER0 volatile.Register32 // 0x4 + SLP_TIMER1 volatile.Register32 // 0x8 + TIME_UPDATE volatile.Register32 // 0xC + TIME_LOW0 volatile.Register32 // 0x10 + TIME_HIGH0 volatile.Register32 // 0x14 + STATE0 volatile.Register32 // 0x18 + TIMER1 volatile.Register32 // 0x1C + TIMER2 volatile.Register32 // 0x20 + TIMER3 volatile.Register32 // 0x24 + TIMER4 volatile.Register32 // 0x28 + TIMER5 volatile.Register32 // 0x2C + TIMER6 volatile.Register32 // 0x30 + ANA_CONF volatile.Register32 // 0x34 + RESET_STATE volatile.Register32 // 0x38 + WAKEUP_STATE volatile.Register32 // 0x3C + INT_ENA_RTC volatile.Register32 // 0x40 + INT_RAW_RTC volatile.Register32 // 0x44 + INT_ST_RTC volatile.Register32 // 0x48 + INT_CLR_RTC volatile.Register32 // 0x4C + STORE0 volatile.Register32 // 0x50 + STORE1 volatile.Register32 // 0x54 + STORE2 volatile.Register32 // 0x58 + STORE3 volatile.Register32 // 0x5C + EXT_XTL_CONF volatile.Register32 // 0x60 + EXT_WAKEUP_CONF volatile.Register32 // 0x64 + SLP_REJECT_CONF volatile.Register32 // 0x68 + CPU_PERIOD_CONF volatile.Register32 // 0x6C + SDIO_ACT_CONF volatile.Register32 // 0x70 + CLK_CONF volatile.Register32 // 0x74 + SLOW_CLK_CONF volatile.Register32 // 0x78 + SDIO_CONF volatile.Register32 // 0x7C + BIAS_CONF volatile.Register32 // 0x80 + REG volatile.Register32 // 0x84 + PWC volatile.Register32 // 0x88 + DIG_PWC volatile.Register32 // 0x8C + DIG_ISO volatile.Register32 // 0x90 + WDTCONFIG0 volatile.Register32 // 0x94 + WDTCONFIG1 volatile.Register32 // 0x98 + WDTCONFIG2 volatile.Register32 // 0x9C + WDTCONFIG3 volatile.Register32 // 0xA0 + WDTCONFIG4 volatile.Register32 // 0xA4 + WDTFEED volatile.Register32 // 0xA8 + WDTWPROTECT volatile.Register32 // 0xAC + SWD_CONF volatile.Register32 // 0xB0 + SWD_WPROTECT volatile.Register32 // 0xB4 + SW_CPU_STALL volatile.Register32 // 0xB8 + STORE4 volatile.Register32 // 0xBC + STORE5 volatile.Register32 // 0xC0 + STORE6 volatile.Register32 // 0xC4 + STORE7 volatile.Register32 // 0xC8 + LOW_POWER_ST volatile.Register32 // 0xCC + DIAG0 volatile.Register32 // 0xD0 + PAD_HOLD volatile.Register32 // 0xD4 + DIG_PAD_HOLD volatile.Register32 // 0xD8 + EXT_WAKEUP1 volatile.Register32 // 0xDC + EXT_WAKEUP1_STATUS volatile.Register32 // 0xE0 + BROWN_OUT volatile.Register32 // 0xE4 + TIME_LOW1 volatile.Register32 // 0xE8 + TIME_HIGH1 volatile.Register32 // 0xEC + XTAL32K_CLK_FACTOR volatile.Register32 // 0xF0 + XTAL32K_CONF volatile.Register32 // 0xF4 + ULP_CP_TIMER volatile.Register32 // 0xF8 + ULP_CP_CTRL volatile.Register32 // 0xFC + COCPU_CTRL volatile.Register32 // 0x100 + TOUCH_CTRL1 volatile.Register32 // 0x104 + TOUCH_CTRL2 volatile.Register32 // 0x108 + TOUCH_SCAN_CTRL volatile.Register32 // 0x10C + TOUCH_SLP_THRES volatile.Register32 // 0x110 + TOUCH_APPROACH volatile.Register32 // 0x114 + TOUCH_FILTER_CTRL volatile.Register32 // 0x118 + USB_CONF volatile.Register32 // 0x11C + TOUCH_TIMEOUT_CTRL volatile.Register32 // 0x120 + SLP_REJECT_CAUSE volatile.Register32 // 0x124 + OPTIONS1 volatile.Register32 // 0x128 + SLP_WAKEUP_CAUSE volatile.Register32 // 0x12C + ULP_CP_TIMER_1 volatile.Register32 // 0x130 + _ [4]byte + DATE volatile.Register32 // 0x138 +} + +// RTC_CNTL.OPTIONS0: Sets the power options of crystal and PLL clocks, and initiates reset by software +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_STALL_APPCPU_C0(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_STALL_APPCPU_C0() uint32 { + return volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_STALL_PROCPU_C0(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0xc)|value<<2) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_STALL_PROCPU_C0() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0xc) >> 2 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_APPCPU_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_APPCPU_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_PROCPU_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_PROCPU_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_PLL_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_PLL_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_PLL_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_PLL_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_NORST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_NORST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_SYS_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_TIMER0: RTC timer threshold register 0 +func (o *RTC_CNTL_Type) SetSLP_TIMER0(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER0() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER0.Reg) +} + +// RTC_CNTL.SLP_TIMER1: RTC timer threshold register 1 +func (o *RTC_CNTL_Type) SetSLP_TIMER1_SLP_VAL_HI(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_SLP_VAL_HI() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0xffff +} +func (o *RTC_CNTL_Type) SetSLP_TIMER1_MAIN_TIMER_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_MAIN_TIMER_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0x10000) >> 16 +} + +// RTC_CNTL.TIME_UPDATE: RTC timer update control register +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_SYS_STALL(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_SYS_STALL() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_XTL_OFF(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_XTL_OFF() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_SYS_RST(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIME_LOW0: Stores the lower 32 bits of RTC timer 0. +func (o *RTC_CNTL_Type) SetTIME_LOW0(value uint32) { + volatile.StoreUint32(&o.TIME_LOW0.Reg, value) +} +func (o *RTC_CNTL_Type) GetTIME_LOW0() uint32 { + return volatile.LoadUint32(&o.TIME_LOW0.Reg) +} + +// RTC_CNTL.TIME_HIGH0: Stores the higher 16 bits of RTC timer 0 +func (o *RTC_CNTL_Type) SetTIME_HIGH0_TIMER_VALUE0_HIGH(value uint32) { + volatile.StoreUint32(&o.TIME_HIGH0.Reg, volatile.LoadUint32(&o.TIME_HIGH0.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTIME_HIGH0_TIMER_VALUE0_HIGH() uint32 { + return volatile.LoadUint32(&o.TIME_HIGH0.Reg) & 0xffff +} + +// RTC_CNTL.STATE0: Configures the sleep / reject / wakeup state +func (o *RTC_CNTL_Type) SetSTATE0_SW_CPU_INT(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetSTATE0_SW_CPU_INT() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_REJECT_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_REJECT_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetSTATE0_APB2RTC_BRIDGE_SEL(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSTATE0_APB2RTC_BRIDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSTATE0_SDIO_ACTIVE_IND(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSTATE0_SDIO_ACTIVE_IND() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_WAKEUP(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_REJECT(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_REJECT() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLEEP_EN(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLEEP_EN() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIMER1: Configures CPU stall options +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3e)|value<<1) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3e) >> 1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CK8M_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3fc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetTIMER1_CK8M_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3fc0) >> 6 +} +func (o *RTC_CNTL_Type) SetTIMER1_XTL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xffc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetTIMER1_XTL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xffc000) >> 14 +} +func (o *RTC_CNTL_Type) SetTIMER1_PLL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER1_PLL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER2: Configures RTC slow clock and touch controller +func (o *RTC_CNTL_Type) SetTIMER2_ULPCP_TOUCH_START_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER2.Reg, volatile.LoadUint32(&o.TIMER2.Reg)&^(0xff8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetTIMER2_ULPCP_TOUCH_START_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER2.Reg) & 0xff8000) >> 15 +} +func (o *RTC_CNTL_Type) SetTIMER2_MIN_TIME_CK8M_OFF(value uint32) { + volatile.StoreUint32(&o.TIMER2.Reg, volatile.LoadUint32(&o.TIMER2.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER2_MIN_TIME_CK8M_OFF() uint32 { + return (volatile.LoadUint32(&o.TIMER2.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER3: configure some wait time for power on +func (o *RTC_CNTL_Type) SetTIMER3_WIFI_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0x1ff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER3_WIFI_WAIT_TIMER() uint32 { + return volatile.LoadUint32(&o.TIMER3.Reg) & 0x1ff +} +func (o *RTC_CNTL_Type) SetTIMER3_WIFI_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0xfe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTIMER3_WIFI_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0xfe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTIMER3_ROM_RAM_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER3_ROM_RAM_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER3_ROM_RAM_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER3_ROM_RAM_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER4: configure some wait time for power on +func (o *RTC_CNTL_Type) SetTIMER4_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0x1ff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER4_WAIT_TIMER() uint32 { + return volatile.LoadUint32(&o.TIMER4.Reg) & 0x1ff +} +func (o *RTC_CNTL_Type) SetTIMER4_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0xfe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTIMER4_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0xfe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER5: Configures the minimal sleep cycles +func (o *RTC_CNTL_Type) SetTIMER5_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetTIMER5_MIN_SLP_VAL() uint32 { + return (volatile.LoadUint32(&o.TIMER5.Reg) & 0xff00) >> 8 +} +func (o *RTC_CNTL_Type) SetTIMER5_RTCMEM_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER5_RTCMEM_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER5.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER5_RTCMEM_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER5_RTCMEM_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER5.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER6: Configure minimal sleep cycles register +func (o *RTC_CNTL_Type) SetTIMER6_DG_DCDC_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER6.Reg, volatile.LoadUint32(&o.TIMER6.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER6_DG_DCDC_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER6.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER6_DG_DCDC_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER6.Reg, volatile.LoadUint32(&o.TIMER6.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER6_DG_DCDC_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER6.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.ANA_CONF: Configures the power options for I2C and PLLA +func (o *RTC_CNTL_Type) SetANA_CONF_I2C_RESET_POR_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetANA_CONF_I2C_RESET_POR_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetANA_CONF_I2C_RESET_POR_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetANA_CONF_I2C_RESET_POR_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetANA_CONF_GLITCH_RST_EN(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetANA_CONF_GLITCH_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetANA_CONF_SAR_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetANA_CONF_SAR_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetANA_CONF_SAR_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetANA_CONF_SAR_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLLA_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLLA_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLLA_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLLA_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetANA_CONF_BBPLL_CAL_SLP_START(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetANA_CONF_BBPLL_CAL_SLP_START() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PVTMON_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PVTMON_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetANA_CONF_TXRF_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetANA_CONF_TXRF_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetANA_CONF_RFRX_PBUS_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetANA_CONF_RFRX_PBUS_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetANA_CONF_CKGEN_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetANA_CONF_CKGEN_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLL_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLL_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.RESET_STATE: Indicates the CPU reset source. For more information about the reset cause, please refer to Table \ref{table:resetreasons} in Chapter \ref{module:ResetandClock} \textit{\nameref{module:ResetandClock}}. +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_CAUSE_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x3f)|value) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_CAUSE_PROCPU() uint32 { + return volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x3f +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_CAUSE_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0xfc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_CAUSE_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0xfc0) >> 6 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_APPCPU_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_APPCPU_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_PROCPU_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_PROCPU_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x2000) >> 13 +} + +// RTC_CNTL.WAKEUP_STATE: Wakeup bitmap enabling register +func (o *RTC_CNTL_Type) SetWAKEUP_STATE_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.WAKEUP_STATE.Reg, volatile.LoadUint32(&o.WAKEUP_STATE.Reg)&^(0xffff8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetWAKEUP_STATE_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_STATE.Reg) & 0xffff8000) >> 15 +} + +// RTC_CNTL.INT_ENA_RTC: RTC interrupt enabling register +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SLP_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SLP_WAKEUP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SLP_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SLP_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SDIO_IDLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SDIO_IDLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_ULP_CP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_ULP_CP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_ACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_ACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_INACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_INACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_MAIN_TIMER_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_MAIN_TIMER_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SARADC1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SARADC1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TSENS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TSENS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_COCPU_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_COCPU_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SARADC2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SARADC2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SWD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SWD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_XTAL32K_DEAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_XTAL32K_DEAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_COCPU_TRAP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_COCPU_TRAP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x80000) >> 19 +} + +// RTC_CNTL.INT_RAW_RTC: RTC interrupt raw register +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SLP_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SLP_WAKEUP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SLP_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SLP_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SDIO_IDLE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SDIO_IDLE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_ULP_CP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_ULP_CP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_ACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_ACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_INACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_INACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_MAIN_TIMER_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_MAIN_TIMER_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SARADC1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SARADC1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TSENS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TSENS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_COCPU_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_COCPU_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SARADC2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SARADC2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SWD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SWD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_XTAL32K_DEAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_XTAL32K_DEAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_COCPU_TRAP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_COCPU_TRAP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x80000) >> 19 +} + +// RTC_CNTL.INT_ST_RTC: RTC interrupt state register +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SLP_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SLP_WAKEUP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SLP_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SLP_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SDIO_IDLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SDIO_IDLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_SCAN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_SCAN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_ULP_CP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_ULP_CP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_ACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_ACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_INACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_INACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_MAIN_TIMER_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_MAIN_TIMER_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SARADC1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SARADC1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TSENS_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TSENS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_COCPU_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_COCPU_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SARADC2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SARADC2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SWD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SWD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_XTAL32K_DEAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_XTAL32K_DEAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_COCPU_TRAP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_COCPU_TRAP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x80000) >> 19 +} + +// RTC_CNTL.INT_CLR_RTC: RTC interrupt clear register +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SLP_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SLP_WAKEUP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SLP_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SLP_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SDIO_IDLE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SDIO_IDLE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_ULP_CP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_ULP_CP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_ACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_ACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_INACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_INACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_MAIN_TIMER_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_MAIN_TIMER_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SARADC1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SARADC1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TSENS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TSENS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_COCPU_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_COCPU_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SARADC2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SARADC2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SWD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SWD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_XTAL32K_DEAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_XTAL32K_DEAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_COCPU_TRAP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_COCPU_TRAP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x80000) >> 19 +} + +// RTC_CNTL.STORE0: Reservation register 0 +func (o *RTC_CNTL_Type) SetSTORE0(value uint32) { + volatile.StoreUint32(&o.STORE0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE0() uint32 { + return volatile.LoadUint32(&o.STORE0.Reg) +} + +// RTC_CNTL.STORE1: Reservation register 1 +func (o *RTC_CNTL_Type) SetSTORE1(value uint32) { + volatile.StoreUint32(&o.STORE1.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE1() uint32 { + return volatile.LoadUint32(&o.STORE1.Reg) +} + +// RTC_CNTL.STORE2: Reservation register 2 +func (o *RTC_CNTL_Type) SetSTORE2(value uint32) { + volatile.StoreUint32(&o.STORE2.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE2() uint32 { + return volatile.LoadUint32(&o.STORE2.Reg) +} + +// RTC_CNTL.STORE3: Reservation register 3 +func (o *RTC_CNTL_Type) SetSTORE3(value uint32) { + volatile.StoreUint32(&o.STORE3.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE3() uint32 { + return volatile.LoadUint32(&o.STORE3.Reg) +} + +// RTC_CNTL.EXT_XTL_CONF: 32 kHz crystal oscillator configuration register +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_WDT_EN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_WDT_EN() uint32 { + return volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_WDT_CLK_FO(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_WDT_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_WDT_RESET(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_WDT_RESET() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_EXT_CLK_FO(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_EXT_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_AUTO_BACKUP(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_AUTO_BACKUP() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_AUTO_RESTART(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_AUTO_RESTART() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_AUTO_RETURN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_AUTO_RETURN() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_ENCKINIT_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_ENCKINIT_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DBUF_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DBUF_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DGM_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x1c00)|value<<10) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DGM_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x1c00) >> 10 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DRES_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0xe000)|value<<13) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DRES_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0xe000) >> 13 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XPD_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XPD_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DAC_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0xe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DAC_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0xe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_WDT_STATE(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_WDT_STATE() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x700000) >> 20 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_GPIO_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_GPIO_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_LV(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_EN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_EN() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.EXT_WAKEUP_CONF: GPIO wakeup configuration register +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_EXT_WAKEUP0_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_EXT_WAKEUP0_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_EXT_WAKEUP1_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_EXT_WAKEUP1_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_REJECT_CONF: Configures sleep / reject options +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_SLEEP_REJECT_ENA(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x3fffe000)|value<<13) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_SLEEP_REJECT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x3fffe000) >> 13 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.CPU_PERIOD_CONF: CPU sel option +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUSEL_CONF(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUSEL_CONF() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUPERIOD_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.SDIO_ACT_CONF: configure sdio active register +func (o *RTC_CNTL_Type) SetSDIO_ACT_CONF_SDIO_ACT_DNUM(value uint32) { + volatile.StoreUint32(&o.SDIO_ACT_CONF.Reg, volatile.LoadUint32(&o.SDIO_ACT_CONF.Reg)&^(0xffc00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSDIO_ACT_CONF_SDIO_ACT_DNUM() uint32 { + return (volatile.LoadUint32(&o.SDIO_ACT_CONF.Reg) & 0xffc00000) >> 22 +} + +// RTC_CNTL.CLK_CONF: RTC clock configuration register +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV_SEL_VLD(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV_SEL_VLD() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x30)|value<<4) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x30) >> 4 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_XTAL32K_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_XTAL32K_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_D256_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_D256_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x7000)|value<<12) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x7000) >> 12 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DFREQ(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1fe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DFREQ() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1fe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_FAST_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_FAST_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ANA_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ANA_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.SLOW_CLK_CONF: RTC slow clock configuration register +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_ANA_CLK_DIV_VLD(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_ANA_CLK_DIV_VLD() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_ANA_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x7f800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_ANA_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x7f800000) >> 23 +} +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SDIO_CONF: configure vddsdio register +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_TIMER_TARGET() uint32 { + return volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_DTHDRV(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x600)|value<<9) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_DTHDRV() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x600) >> 9 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_DCAP(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x1800)|value<<11) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_DCAP() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x1800) >> 11 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_INITI(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_INITI() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x6000) >> 13 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_EN_INITI(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_EN_INITI() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_DCURLIM(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_DCURLIM() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x70000) >> 16 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_MODECURLIM(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_MODECURLIM() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_ENCURLIM(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_ENCURLIM() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_REG_PD_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_REG_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_FORCE(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_FORCE() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_TIEH(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_TIEH() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_REG1P8_READY(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_REG1P8_READY() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFL_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x6000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFL_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x6000000) >> 25 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFM_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFM_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x18000000) >> 27 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFH_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFH_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x60000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_XPD_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_XPD_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.BIAS_CONF: configure power register +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_IDLE(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_IDLE() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_WAKE(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_WAKE() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_PD_CUR_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_PD_CUR_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_PD_CUR_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_PD_CUR_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_SLEEP_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_SLEEP_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_SLEEP_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_SLEEP_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c0000)|value<<18) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c0000) >> 18 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_ENB_SCK_XTAL(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_ENB_SCK_XTAL() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_INC_HEARTBEAT_REFRESH(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_INC_HEARTBEAT_REFRESH() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DEC_HEARTBEAT_PERIOD(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DEC_HEARTBEAT_PERIOD() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_INC_HEARTBEAT_PERIOD(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_INC_HEARTBEAT_PERIOD() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DEC_HEARTBEAT_WIDTH(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DEC_HEARTBEAT_WIDTH() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_RST_BIAS_I2C(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_RST_BIAS_I2C() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.REG: RTC/DIG regulator configuration register +func (o *RTC_CNTL_Type) SetREG_DIG_REG_DBIAS_SLP(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x700)|value<<8) +} +func (o *RTC_CNTL_Type) GetREG_DIG_REG_DBIAS_SLP() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x700) >> 8 +} +func (o *RTC_CNTL_Type) SetREG_DIG_REG_DBIAS_WAK(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x3800)|value<<11) +} +func (o *RTC_CNTL_Type) GetREG_DIG_REG_DBIAS_WAK() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x3800) >> 11 +} +func (o *RTC_CNTL_Type) SetREG_SCK_DCAP(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x3fc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetREG_SCK_DCAP() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x3fc000) >> 14 +} +func (o *RTC_CNTL_Type) SetREG_DBIAS_SLP(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x1c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetREG_DBIAS_SLP() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x1c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetREG_DBIAS_WAK(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetREG_DBIAS_WAK() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetREG_DBOOST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetREG_DBOOST_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetREG_DBOOST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetREG_DBOOST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetREG_REGULATOR_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetREG_REGULATOR_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetREG_REGULATOR_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.REG.Reg, volatile.LoadUint32(&o.REG.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetREG_REGULATOR_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.REG.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.PWC: RTC power configuraiton register +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_NOISO() uint32 { + return volatile.LoadUint32(&o.PWC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FOLW_CPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FOLW_CPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_LPD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_LPD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_LPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_LPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FOLW_CPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FOLW_CPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_LPD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_LPD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_LPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_LPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_PD_EN(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_PD_EN() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetPWC_PD_EN(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetPWC_PD_EN() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetPWC_PAD_FORCE_HOLD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetPWC_PAD_FORCE_HOLD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x200000) >> 21 +} + +// RTC_CNTL.DIG_PWC: Digital system power configuraiton register +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_ROM0_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_ROM0_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_ROM0_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_ROM0_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM0_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM0_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM0_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM0_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM1_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM1_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM1_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM1_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM2_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM2_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM2_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM2_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM3_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM3_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM3_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM3_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM4_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM4_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM4_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM4_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_DCDC_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_DCDC_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_DCDC_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_DCDC_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_DCDC_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_DCDC_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_ROM0_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_ROM0_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM0_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM0_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM1_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM1_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM2_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM2_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM3_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM3_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_INTER_RAM4_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_INTER_RAM4_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.DIG_ISO: Digital system ISO configuration register +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_OFF(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_OFF() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_CLR_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_CLR_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_UNHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_UNHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_HOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_ROM0_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_ROM0_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_ROM0_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_ROM0_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM0_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM0_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM0_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM0_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM1_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM1_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM1_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM1_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM2_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM2_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM2_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM2_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM3_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM3_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM3_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM3_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM4_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM4_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_INTER_RAM4_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_INTER_RAM4_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_WIFI_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_WIFI_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_WIFI_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_WIFI_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG0: RTC watchdog configuration register +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CHIP_RESET_WIDTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CHIP_RESET_WIDTH() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CHIP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CHIP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PAUSE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PAUSE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000)|value<<13) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000) >> 13 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000) >> 16 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x380000)|value<<19) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x380000) >> 19 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000000) >> 28 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG1: Configures the hold time of RTC watchdog at level 1 +func (o *RTC_CNTL_Type) SetWDTCONFIG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG1() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) +} + +// RTC_CNTL.WDTCONFIG2: Configures the hold time of RTC watchdog at level 2 +func (o *RTC_CNTL_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// RTC_CNTL.WDTCONFIG3: Configures the hold time of RTC watchdog at level 3 +func (o *RTC_CNTL_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// RTC_CNTL.WDTCONFIG4: Configures the hold time of RTC watchdog at level 4 +func (o *RTC_CNTL_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// RTC_CNTL.WDTFEED: RTC watchdog SW feed configuration register +func (o *RTC_CNTL_Type) SetWDTFEED_WDT_FEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, volatile.LoadUint32(&o.WDTFEED.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTFEED_WDT_FEED() uint32 { + return (volatile.LoadUint32(&o.WDTFEED.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTWPROTECT: RTC watchdog write protection configuration register +func (o *RTC_CNTL_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// RTC_CNTL.SWD_CONF: Super watchdog configuration register +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_RESET_FLAG() uint32 { + return volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_FEED_INT(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_FEED_INT() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_SIGNAL_WIDTH(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0xffc0000)|value<<18) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_SIGNAL_WIDTH() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0xffc0000) >> 18 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_RST_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_RST_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_FEED(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_FEED() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_DISABLE(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_AUTO_FEED_EN(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_AUTO_FEED_EN() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SWD_WPROTECT: Super watchdog write protection configuration register +func (o *RTC_CNTL_Type) SetSWD_WPROTECT(value uint32) { + volatile.StoreUint32(&o.SWD_WPROTECT.Reg, value) +} +func (o *RTC_CNTL_Type) GetSWD_WPROTECT() uint32 { + return volatile.LoadUint32(&o.SWD_WPROTECT.Reg) +} + +// RTC_CNTL.SW_CPU_STALL: CPU stall configuration register +func (o *RTC_CNTL_Type) SetSW_CPU_STALL_SW_STALL_APPCPU_C1(value uint32) { + volatile.StoreUint32(&o.SW_CPU_STALL.Reg, volatile.LoadUint32(&o.SW_CPU_STALL.Reg)&^(0x3f00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetSW_CPU_STALL_SW_STALL_APPCPU_C1() uint32 { + return (volatile.LoadUint32(&o.SW_CPU_STALL.Reg) & 0x3f00000) >> 20 +} +func (o *RTC_CNTL_Type) SetSW_CPU_STALL_SW_STALL_PROCPU_C1(value uint32) { + volatile.StoreUint32(&o.SW_CPU_STALL.Reg, volatile.LoadUint32(&o.SW_CPU_STALL.Reg)&^(0xfc000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetSW_CPU_STALL_SW_STALL_PROCPU_C1() uint32 { + return (volatile.LoadUint32(&o.SW_CPU_STALL.Reg) & 0xfc000000) >> 26 +} + +// RTC_CNTL.STORE4: Reservation register 4 +func (o *RTC_CNTL_Type) SetSTORE4(value uint32) { + volatile.StoreUint32(&o.STORE4.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE4() uint32 { + return volatile.LoadUint32(&o.STORE4.Reg) +} + +// RTC_CNTL.STORE5: Reservation register 5 +func (o *RTC_CNTL_Type) SetSTORE5(value uint32) { + volatile.StoreUint32(&o.STORE5.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE5() uint32 { + return volatile.LoadUint32(&o.STORE5.Reg) +} + +// RTC_CNTL.STORE6: Reservation register 6 +func (o *RTC_CNTL_Type) SetSTORE6(value uint32) { + volatile.StoreUint32(&o.STORE6.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE6() uint32 { + return volatile.LoadUint32(&o.STORE6.Reg) +} + +// RTC_CNTL.STORE7: Reservation register 7 +func (o *RTC_CNTL_Type) SetSTORE7(value uint32) { + volatile.StoreUint32(&o.STORE7.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE7() uint32 { + return volatile.LoadUint32(&o.STORE7.Reg) +} + +// RTC_CNTL.LOW_POWER_ST: RTC main state machine status register +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_ROM0(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_ROM0() uint32 { + return volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_DIG_DCDC(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_DIG_DCDC() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_PERI_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_PERI_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_RTC_PERI(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_RTC_PERI() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_WIFI_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_WIFI_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_WIFI(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_WIFI() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_DIG_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_DIG_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_DIG(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_DIG() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_START(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_START() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_SWITCH(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_SWITCH() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_DONE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_DONE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_START(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_START() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_SWITCH(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_SWITCH() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_DONE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_DONE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_XTAL_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_XTAL_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_PLL_ON(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_PLL_ON() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_RDY_FOR_WAKEUP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_RDY_FOR_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_WAIT_END(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_WAIT_END() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_IN_WAKEUP_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_IN_WAKEUP_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_IN_LOW_POWER_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_IN_LOW_POWER_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_8M(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_8M() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_IDLE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_IDLE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.DIAG0: debug register +func (o *RTC_CNTL_Type) SetDIAG0(value uint32) { + volatile.StoreUint32(&o.DIAG0.Reg, value) +} +func (o *RTC_CNTL_Type) GetDIAG0() uint32 { + return volatile.LoadUint32(&o.DIAG0.Reg) +} + +// RTC_CNTL.PAD_HOLD: Configures the hold options for RTC GPIOs +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD0_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD0_HOLD() uint32 { + return volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD1_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD1_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD2_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD2_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD3_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD3_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD4_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD4_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD5_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD5_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD6_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD6_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD7_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD7_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD8_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD8_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD9_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD9_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD10_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD10_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD11_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD11_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD12_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD12_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD13_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD13_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD14_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD14_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_X32P_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_X32P_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_X32N_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_X32N_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PDAC1_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PDAC1_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PDAC2_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PDAC2_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PAD19_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PAD19_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PAD20_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PAD20_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PAD21_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PAD21_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x200000) >> 21 +} + +// RTC_CNTL.DIG_PAD_HOLD: Configures the hold option for digital GPIOs +func (o *RTC_CNTL_Type) SetDIG_PAD_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_PAD_HOLD.Reg, value) +} +func (o *RTC_CNTL_Type) GetDIG_PAD_HOLD() uint32 { + return volatile.LoadUint32(&o.DIG_PAD_HOLD.Reg) +} + +// RTC_CNTL.EXT_WAKEUP1: EXT1 wakeup configuration register +func (o *RTC_CNTL_Type) SetEXT_WAKEUP1_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0x3fffff)|value) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP1_SEL() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0x3fffff +} +func (o *RTC_CNTL_Type) SetEXT_WAKEUP1_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP1_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0x400000) >> 22 +} + +// RTC_CNTL.EXT_WAKEUP1_STATUS: EXT1 wakeup source register +func (o *RTC_CNTL_Type) SetEXT_WAKEUP1_STATUS(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1_STATUS.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg)&^(0x3fffff)|value) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP1_STATUS() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg) & 0x3fffff +} + +// RTC_CNTL.BROWN_OUT: Brownout configuration register +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT2_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT2_ENA() uint32 { + return volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_INT_WAIT(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x3ff0)|value<<4) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_INT_WAIT() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x3ff0) >> 4 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_CLOSE_FLASH_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_CLOSE_FLASH_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_PD_RF_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_PD_RF_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_RST_WAIT(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x3ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RST_WAIT() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x3ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_RST_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RST_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_RST_SEL(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_RST_SEL() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_DET(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_DET() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIME_LOW1: Stores the lower 32 bits of RTC timer 1 +func (o *RTC_CNTL_Type) SetTIME_LOW1(value uint32) { + volatile.StoreUint32(&o.TIME_LOW1.Reg, value) +} +func (o *RTC_CNTL_Type) GetTIME_LOW1() uint32 { + return volatile.LoadUint32(&o.TIME_LOW1.Reg) +} + +// RTC_CNTL.TIME_HIGH1: Stores the higher 16 bits of RTC timer 1 +func (o *RTC_CNTL_Type) SetTIME_HIGH1_TIMER_VALUE1_HIGH(value uint32) { + volatile.StoreUint32(&o.TIME_HIGH1.Reg, volatile.LoadUint32(&o.TIME_HIGH1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTIME_HIGH1_TIMER_VALUE1_HIGH() uint32 { + return volatile.LoadUint32(&o.TIME_HIGH1.Reg) & 0xffff +} + +// RTC_CNTL.XTAL32K_CLK_FACTOR: Configures the divider factor for the backup clock of 32 kHz crystal oscillator +func (o *RTC_CNTL_Type) SetXTAL32K_CLK_FACTOR(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CLK_FACTOR.Reg, value) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CLK_FACTOR() uint32 { + return volatile.LoadUint32(&o.XTAL32K_CLK_FACTOR.Reg) +} + +// RTC_CNTL.XTAL32K_CONF: 32 kHz crystal oscillator configuration register +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_RETURN_WAIT(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xf)|value) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_RETURN_WAIT() uint32 { + return volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xf +} +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_RESTART_WAIT(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xffff0)|value<<4) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_RESTART_WAIT() uint32 { + return (volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xffff0) >> 4 +} +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_WDT_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xff00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_WDT_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xff00000) >> 20 +} +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_STABLE_THRES(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_STABLE_THRES() uint32 { + return (volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.ULP_CP_TIMER: Configure coprocessor timer +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_PC_INIT(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x7ff)|value) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_PC_INIT() uint32 { + return volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x7ff +} +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_SLP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_SLP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.ULP_CP_CTRL: ULP-FSM configuration register +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x7ff)|value) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT() uint32 { + return volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x7ff +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x3ff800)|value<<11) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x3ff800) >> 11 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_CLK_FO(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_RESET(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_RESET() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_FORCE_START_TOP(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_FORCE_START_TOP() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_START_TOP(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_START_TOP() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.COCPU_CTRL: ULP-RISCV configuration register +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_CLK_FO(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_CLK_FO() uint32 { + return volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_START_2_RESET_DIS(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x7e)|value<<1) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_START_2_RESET_DIS() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x7e) >> 1 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_START_2_INTR_EN(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x1f80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_START_2_INTR_EN() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x1f80) >> 7 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SHUT(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SHUT() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SHUT_2_CLK_DIS(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SHUT_2_CLK_DIS() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SHUT_RESET_EN(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SHUT_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SEL(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SEL() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_DONE_FORCE(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_DONE_FORCE() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_DONE(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_DONE() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SW_INT_TRIGGER(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SW_INT_TRIGGER() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x4000000) >> 26 +} + +// RTC_CNTL.TOUCH_CTRL1: Touch control register +func (o *RTC_CNTL_Type) SetTOUCH_CTRL1_TOUCH_SLEEP_CYCLES(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.TOUCH_CTRL1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL1_TOUCH_SLEEP_CYCLES() uint32 { + return volatile.LoadUint32(&o.TOUCH_CTRL1.Reg) & 0xffff +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL1_TOUCH_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.TOUCH_CTRL1.Reg)&^(0xffff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL1_TOUCH_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL1.Reg) & 0xffff0000) >> 16 +} + +// RTC_CNTL.TOUCH_CTRL2: Touch control register +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_DRANGE(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0xc)|value<<2) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_DRANGE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0xc) >> 2 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_DREFL(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x30)|value<<4) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_DREFL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x30) >> 4 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_DREFH(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0xc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_DREFH() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0xc0) >> 6 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_REFC(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0xe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_REFC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0xe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_DBIAS(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_DBIAS() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_SLP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_SLP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_START_FSM_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_START_FSM_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_START_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_START_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_START_FORCE(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x1fe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_XPD_WAIT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x1fe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_SLP_CYC_DIV(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x6000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_SLP_CYC_DIV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x6000000) >> 25 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_TIMER_FORCE_DONE(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x18000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_TIMER_FORCE_DONE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x18000000) >> 27 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_RESET(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_RESET() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_CLK_FO(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_CLKGATE_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_CLKGATE_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TOUCH_SCAN_CTRL: Configure touch scan settings +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_DENOISE_RES(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_DENOISE_RES() uint32 { + return volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_DENOISE_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_DENOISE_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_SCAN_PAD_MAP(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x1fffc00)|value<<10) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_SCAN_PAD_MAP() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x1fffc00) >> 10 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_BUFDRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_BUFDRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_OUT_RING(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_OUT_RING() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.TOUCH_SLP_THRES: Configure the settings of touch sleep pad +func (o *RTC_CNTL_Type) SetTOUCH_SLP_THRES_TOUCH_SLP_TH(value uint32) { + volatile.StoreUint32(&o.TOUCH_SLP_THRES.Reg, volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg)&^(0x3fffff)|value) +} +func (o *RTC_CNTL_Type) GetTOUCH_SLP_THRES_TOUCH_SLP_TH() uint32 { + return volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg) & 0x3fffff +} +func (o *RTC_CNTL_Type) SetTOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_SLP_THRES.Reg, volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetTOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetTOUCH_SLP_THRES_TOUCH_SLP_PAD(value uint32) { + volatile.StoreUint32(&o.TOUCH_SLP_THRES.Reg, volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetTOUCH_SLP_THRES_TOUCH_SLP_PAD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg) & 0xf8000000) >> 27 +} + +// RTC_CNTL.TOUCH_APPROACH: Configure touch approach settings +func (o *RTC_CNTL_Type) SetTOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR(value uint32) { + volatile.StoreUint32(&o.TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.TOUCH_APPROACH.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetTOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR() uint32 { + return (volatile.LoadUint32(&o.TOUCH_APPROACH.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetTOUCH_APPROACH_MEAS_TIME(value uint32) { + volatile.StoreUint32(&o.TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.TOUCH_APPROACH.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTOUCH_APPROACH_MEAS_TIME() uint32 { + return (volatile.LoadUint32(&o.TOUCH_APPROACH.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TOUCH_FILTER_CTRL: Configure touch filter settings +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_SMOOTH_LVL(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x600)|value<<9) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_SMOOTH_LVL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x600) >> 9 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_JITTER_STEP(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x7800)|value<<11) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_JITTER_STEP() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x7800) >> 11 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_LIMIT(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x78000)|value<<15) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_LIMIT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x78000) >> 15 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x180000)|value<<19) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x180000) >> 19 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x600000)|value<<21) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x600000) >> 21 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_HYSTERESIS(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x1800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_HYSTERESIS() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x1800000) >> 23 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x70000000) >> 28 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.USB_CONF: configure usb control register +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_VREFH(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_VREFH() uint32 { + return volatile.LoadUint32(&o.USB_CONF.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_VREFL(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0xc)|value<<2) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_VREFL() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0xc) >> 2 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_PAD_ENABLE_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_PAD_ENABLE_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_TXM(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_TXM() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_TXP(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_TXP() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_TX_EN(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_TX_EN() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_TX_EN_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_TX_EN_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_IO_MUX_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_IO_MUX_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x40000) >> 18 +} + +// RTC_CNTL.TOUCH_TIMEOUT_CTRL: Configure touch timeout settings +func (o *RTC_CNTL_Type) SetTOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_NUM(value uint32) { + volatile.StoreUint32(&o.TOUCH_TIMEOUT_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_TIMEOUT_CTRL.Reg)&^(0x3fffff)|value) +} +func (o *RTC_CNTL_Type) GetTOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_NUM() uint32 { + return volatile.LoadUint32(&o.TOUCH_TIMEOUT_CTRL.Reg) & 0x3fffff +} +func (o *RTC_CNTL_Type) SetTOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_TIMEOUT_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_TIMEOUT_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetTOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_TIMEOUT_CTRL.Reg) & 0x400000) >> 22 +} + +// RTC_CNTL.SLP_REJECT_CAUSE: Stores the reject-to-sleep cause. +func (o *RTC_CNTL_Type) SetSLP_REJECT_CAUSE_REJECT_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CAUSE.Reg, volatile.LoadUint32(&o.SLP_REJECT_CAUSE.Reg)&^(0x1ffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CAUSE_REJECT_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_REJECT_CAUSE.Reg) & 0x1ffff +} + +// RTC_CNTL.OPTIONS1: RTC option register +func (o *RTC_CNTL_Type) SetOPTIONS1_FORCE_DOWNLOAD_BOOT(value uint32) { + volatile.StoreUint32(&o.OPTIONS1.Reg, volatile.LoadUint32(&o.OPTIONS1.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetOPTIONS1_FORCE_DOWNLOAD_BOOT() uint32 { + return volatile.LoadUint32(&o.OPTIONS1.Reg) & 0x1 +} + +// RTC_CNTL.SLP_WAKEUP_CAUSE: Stores the sleep-to-wakeup cause. +func (o *RTC_CNTL_Type) SetSLP_WAKEUP_CAUSE_WAKEUP_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CAUSE.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CAUSE.Reg)&^(0x1ffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_WAKEUP_CAUSE_WAKEUP_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CAUSE.Reg) & 0x1ffff +} + +// RTC_CNTL.ULP_CP_TIMER_1: Configure sleep cycle of the timer +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER_1.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg)&^(0xffffff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg) & 0xffffff00) >> 8 +} + +// RTC_CNTL.DATE +func (o *RTC_CNTL_Type) SetDATE_CNTL_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_CNTL_Type) GetDATE_CNTL_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power I2C (Inter-Integrated Circuit) Controller +type RTC_I2C_Type struct { + SCL_LOW volatile.Register32 // 0x0 + CTRL volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + SCL_HIGH volatile.Register32 // 0x14 + SDA_DUTY volatile.Register32 // 0x18 + SCL_START_PERIOD volatile.Register32 // 0x1C + SCL_STOP_PERIOD volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_RAW volatile.Register32 // 0x28 + INT_ST volatile.Register32 // 0x2C + INT_ENA volatile.Register32 // 0x30 + DATA volatile.Register32 // 0x34 + CMD0 volatile.Register32 // 0x38 + CMD1 volatile.Register32 // 0x3C + CMD2 volatile.Register32 // 0x40 + CMD3 volatile.Register32 // 0x44 + CMD4 volatile.Register32 // 0x48 + CMD5 volatile.Register32 // 0x4C + CMD6 volatile.Register32 // 0x50 + CMD7 volatile.Register32 // 0x54 + CMD8 volatile.Register32 // 0x58 + CMD9 volatile.Register32 // 0x5C + CMD10 volatile.Register32 // 0x60 + CMD11 volatile.Register32 // 0x64 + CMD12 volatile.Register32 // 0x68 + CMD13 volatile.Register32 // 0x6C + CMD14 volatile.Register32 // 0x70 + CMD15 volatile.Register32 // 0x74 + _ [132]byte + DATE volatile.Register32 // 0xFC +} + +// RTC_I2C.SCL_LOW: Configure the low level width of SCL +func (o *RTC_I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW.Reg, volatile.LoadUint32(&o.SCL_LOW.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW.Reg) & 0xfffff +} + +// RTC_I2C.CTRL: Transmission setting +func (o *RTC_I2C_Type) SetCTRL_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetCTRL_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetCTRL_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetCTRL_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetCTRL_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetCTRL_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetCTRL_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetCTRL_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetCTRL_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetCTRL_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetCTRL_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetCTRL_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetCTRL_CLK_GATE_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_I2C_Type) GetCTRL_CLK_GATE_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_I2C_Type) SetCTRL_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_I2C_Type) GetCTRL_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_I2C_Type) SetCTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCTRL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.STATUS: RTC I2C status +func (o *RTC_I2C_Type) SetSTATUS_ACK_REC(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetSTATUS_ACK_REC() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetSTATUS_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetSTATUS_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetSTATUS_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetSTATUS_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetSTATUS_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetSTATUS_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetSTATUS_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetSTATUS_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetSTATUS_BYTE_TRANS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetSTATUS_BYTE_TRANS() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetSTATUS_OP_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xc0)|value<<6) +} +func (o *RTC_I2C_Type) GetSTATUS_OP_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xc0) >> 6 +} +func (o *RTC_I2C_Type) SetSTATUS_SHIFT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *RTC_I2C_Type) GetSTATUS_SHIFT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xff0000) >> 16 +} +func (o *RTC_I2C_Type) SetSTATUS_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RTC_I2C_Type) GetSTATUS_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RTC_I2C_Type) SetSTATUS_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_I2C_Type) GetSTATUS_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x70000000) >> 28 +} + +// RTC_I2C.TO: Configure RTC I2C timeout +func (o *RTC_I2C_Type) SetTO_TIME_OUT(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetTO_TIME_OUT() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0xfffff +} + +// RTC_I2C.SLAVE_ADDR: Configure slave address +func (o *RTC_I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *RTC_I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.SCL_HIGH: Configure the high level width of SCL +func (o *RTC_I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH.Reg, volatile.LoadUint32(&o.SCL_HIGH.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH.Reg) & 0xfffff +} + +// RTC_I2C.SDA_DUTY: Configure the SDA hold time after a negative SCL edge +func (o *RTC_I2C_Type) SetSDA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.SDA_DUTY.Reg, volatile.LoadUint32(&o.SDA_DUTY.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSDA_DUTY_NUM() uint32 { + return volatile.LoadUint32(&o.SDA_DUTY.Reg) & 0xfffff +} + +// RTC_I2C.SCL_START_PERIOD: Configure the delay between the SDA and SCL negative edge for a start condition +func (o *RTC_I2C_Type) SetSCL_START_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_START_PERIOD.Reg, volatile.LoadUint32(&o.SCL_START_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_START_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_START_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.SCL_STOP_PERIOD: Configure the delay between SDA and SCL positive edge for a stop condition +func (o *RTC_I2C_Type) SetSCL_STOP_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_PERIOD.Reg, volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_STOP_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.INT_CLR: Clear RTC I2C interrupt +func (o *RTC_I2C_Type) SetINT_CLR_SLAVE_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_CLR_SLAVE_TRAN_COMP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_CLR_MASTER_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_CLR_MASTER_TRAN_COMP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_CLR_ACK_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_CLR_ACK_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_CLR_RX_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_CLR_RX_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_CLR_TX_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_CLR_TX_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_CLR_DETECT_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_CLR_DETECT_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_RAW: RTC I2C raw interrupt +func (o *RTC_I2C_Type) SetINT_RAW_SLAVE_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_RAW_SLAVE_TRAN_COMP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_RAW_MASTER_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_RAW_MASTER_TRAN_COMP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_RAW_ACK_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_RAW_ACK_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_RAW_RX_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_RAW_RX_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_RAW_TX_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_RAW_TX_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_RAW_DETECT_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_RAW_DETECT_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_ST: RTC I2C interrupt status +func (o *RTC_I2C_Type) SetINT_ST_SLAVE_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_ST_SLAVE_TRAN_COMP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_ST_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_ST_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_ST_MASTER_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_ST_MASTER_TRAN_COMP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_ST_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_ST_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_ST_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_ST_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_ST_ACK_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_ST_ACK_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_ST_RX_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_ST_RX_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_ST_TX_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_ST_TX_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_ST_DETECT_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_ST_DETECT_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_ENA: Enable RTC I2C interrupt +func (o *RTC_I2C_Type) SetINT_ENA_SLAVE_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_ENA_SLAVE_TRAN_COMP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_ENA_MASTER_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_ENA_MASTER_TRAN_COMP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_ENA_ACK_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_ENA_ACK_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_ENA_RX_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_ENA_RX_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_ENA_TX_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_ENA_TX_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_ENA_DETECT_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_ENA_DETECT_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// RTC_I2C.DATA: RTC I2C read data +func (o *RTC_I2C_Type) SetDATA_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *RTC_I2C_Type) GetDATA_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} +func (o *RTC_I2C_Type) SetDATA_SLAVE_TX_DATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_I2C_Type) GetDATA_SLAVE_TX_DATA() uint32 { + return (volatile.LoadUint32(&o.DATA.Reg) & 0xff00) >> 8 +} +func (o *RTC_I2C_Type) SetDATA_DONE(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetDATA_DONE() uint32 { + return (volatile.LoadUint32(&o.DATA.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD0: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD0_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD0.Reg, volatile.LoadUint32(&o.CMD0.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD0_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD0.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD0_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD0.Reg, volatile.LoadUint32(&o.CMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD0_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD0.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD1: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD1_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD1.Reg, volatile.LoadUint32(&o.CMD1.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD1_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD1.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD1_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD1.Reg, volatile.LoadUint32(&o.CMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD1_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD1.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD2: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD2_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD2.Reg, volatile.LoadUint32(&o.CMD2.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD2_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD2.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD2_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD2.Reg, volatile.LoadUint32(&o.CMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD2_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD2.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD3: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD3_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD3.Reg, volatile.LoadUint32(&o.CMD3.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD3_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD3.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD3_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD3.Reg, volatile.LoadUint32(&o.CMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD3_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD3.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD4: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD4_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD4.Reg, volatile.LoadUint32(&o.CMD4.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD4_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD4.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD4_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD4.Reg, volatile.LoadUint32(&o.CMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD4_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD4.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD5: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD5_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD5.Reg, volatile.LoadUint32(&o.CMD5.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD5_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD5.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD5_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD5.Reg, volatile.LoadUint32(&o.CMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD5_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD5.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD6: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD6_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD6.Reg, volatile.LoadUint32(&o.CMD6.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD6_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD6.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD6_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD6.Reg, volatile.LoadUint32(&o.CMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD6_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD6.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD7: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD7_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD7.Reg, volatile.LoadUint32(&o.CMD7.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD7_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD7.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD7_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD7.Reg, volatile.LoadUint32(&o.CMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD7_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD7.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD8: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD8_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD8.Reg, volatile.LoadUint32(&o.CMD8.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD8_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD8.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD8_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD8.Reg, volatile.LoadUint32(&o.CMD8.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD8_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD8.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD9: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD9_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD9.Reg, volatile.LoadUint32(&o.CMD9.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD9_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD9.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD9_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD9.Reg, volatile.LoadUint32(&o.CMD9.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD9_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD9.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD10: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD10_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD10.Reg, volatile.LoadUint32(&o.CMD10.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD10_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD10.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD10_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD10.Reg, volatile.LoadUint32(&o.CMD10.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD10_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD10.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD11: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD11_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD11.Reg, volatile.LoadUint32(&o.CMD11.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD11_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD11.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD11_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD11.Reg, volatile.LoadUint32(&o.CMD11.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD11_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD11.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD12: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD12_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD12.Reg, volatile.LoadUint32(&o.CMD12.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD12_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD12.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD12_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD12.Reg, volatile.LoadUint32(&o.CMD12.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD12_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD12.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD13: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD13_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD13.Reg, volatile.LoadUint32(&o.CMD13.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD13_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD13.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD13_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD13.Reg, volatile.LoadUint32(&o.CMD13.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD13_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD13.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD14: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD14_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD14.Reg, volatile.LoadUint32(&o.CMD14.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD14_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD14.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD14_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD14.Reg, volatile.LoadUint32(&o.CMD14.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD14_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD14.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD15: RTC I2C Command %s +func (o *RTC_I2C_Type) SetCMD15_COMMAND(value uint32) { + volatile.StoreUint32(&o.CMD15.Reg, volatile.LoadUint32(&o.CMD15.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD15_COMMAND() uint32 { + return volatile.LoadUint32(&o.CMD15.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD15_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.CMD15.Reg, volatile.LoadUint32(&o.CMD15.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD15_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD15.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.DATE: Version control register +func (o *RTC_I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SENS Peripheral +type SENS_Type struct { + SAR_READER1_CTRL volatile.Register32 // 0x0 + SAR_READER1_STATUS volatile.Register32 // 0x4 + SAR_MEAS1_CTRL1 volatile.Register32 // 0x8 + SAR_MEAS1_CTRL2 volatile.Register32 // 0xC + SAR_MEAS1_MUX volatile.Register32 // 0x10 + SAR_ATTEN1 volatile.Register32 // 0x14 + SAR_AMP_CTRL1 volatile.Register32 // 0x18 + SAR_AMP_CTRL2 volatile.Register32 // 0x1C + SAR_AMP_CTRL3 volatile.Register32 // 0x20 + SAR_READER2_CTRL volatile.Register32 // 0x24 + SAR_READER2_STATUS volatile.Register32 // 0x28 + SAR_MEAS2_CTRL1 volatile.Register32 // 0x2C + SAR_MEAS2_CTRL2 volatile.Register32 // 0x30 + SAR_MEAS2_MUX volatile.Register32 // 0x34 + SAR_ATTEN2 volatile.Register32 // 0x38 + SAR_POWER_XPD_SAR volatile.Register32 // 0x3C + SAR_SLAVE_ADDR1 volatile.Register32 // 0x40 + SAR_SLAVE_ADDR2 volatile.Register32 // 0x44 + SAR_SLAVE_ADDR3 volatile.Register32 // 0x48 + SAR_SLAVE_ADDR4 volatile.Register32 // 0x4C + SAR_TSENS_CTRL volatile.Register32 // 0x50 + SAR_TSENS_CTRL2 volatile.Register32 // 0x54 + SAR_I2C_CTRL volatile.Register32 // 0x58 + SAR_TOUCH_CONF volatile.Register32 // 0x5C + SAR_TOUCH_THRES1 volatile.Register32 // 0x60 + SAR_TOUCH_THRES2 volatile.Register32 // 0x64 + SAR_TOUCH_THRES3 volatile.Register32 // 0x68 + SAR_TOUCH_THRES4 volatile.Register32 // 0x6C + SAR_TOUCH_THRES5 volatile.Register32 // 0x70 + SAR_TOUCH_THRES6 volatile.Register32 // 0x74 + SAR_TOUCH_THRES7 volatile.Register32 // 0x78 + SAR_TOUCH_THRES8 volatile.Register32 // 0x7C + SAR_TOUCH_THRES9 volatile.Register32 // 0x80 + SAR_TOUCH_THRES10 volatile.Register32 // 0x84 + SAR_TOUCH_THRES11 volatile.Register32 // 0x88 + SAR_TOUCH_THRES12 volatile.Register32 // 0x8C + SAR_TOUCH_THRES13 volatile.Register32 // 0x90 + SAR_TOUCH_THRES14 volatile.Register32 // 0x94 + _ [60]byte + SAR_TOUCH_CHN_ST volatile.Register32 // 0xD4 + SAR_TOUCH_STATUS0 volatile.Register32 // 0xD8 + SAR_TOUCH_STATUS1 volatile.Register32 // 0xDC + SAR_TOUCH_STATUS2 volatile.Register32 // 0xE0 + SAR_TOUCH_STATUS3 volatile.Register32 // 0xE4 + SAR_TOUCH_STATUS4 volatile.Register32 // 0xE8 + SAR_TOUCH_STATUS5 volatile.Register32 // 0xEC + SAR_TOUCH_STATUS6 volatile.Register32 // 0xF0 + SAR_TOUCH_STATUS7 volatile.Register32 // 0xF4 + SAR_TOUCH_STATUS8 volatile.Register32 // 0xF8 + SAR_TOUCH_STATUS9 volatile.Register32 // 0xFC + SAR_TOUCH_STATUS10 volatile.Register32 // 0x100 + SAR_TOUCH_STATUS11 volatile.Register32 // 0x104 + SAR_TOUCH_STATUS12 volatile.Register32 // 0x108 + SAR_TOUCH_STATUS13 volatile.Register32 // 0x10C + SAR_TOUCH_STATUS14 volatile.Register32 // 0x110 + SAR_TOUCH_STATUS15 volatile.Register32 // 0x114 + SAR_TOUCH_STATUS16 volatile.Register32 // 0x118 + SAR_DAC_CTRL1 volatile.Register32 // 0x11C + SAR_DAC_CTRL2 volatile.Register32 // 0x120 + SAR_COCPU_STATE volatile.Register32 // 0x124 + SAR_COCPU_INT_RAW volatile.Register32 // 0x128 + SAR_COCPU_INT_ENA volatile.Register32 // 0x12C + SAR_COCPU_INT_ST volatile.Register32 // 0x130 + SAR_COCPU_INT_CLR volatile.Register32 // 0x134 + SAR_COCPU_DEBUG volatile.Register32 // 0x138 + SAR_HALL_CTRL volatile.Register32 // 0x13C + SAR_NOUSE volatile.Register32 // 0x140 + SAR_IO_MUX_CONF volatile.Register32 // 0x144 + SARDATE volatile.Register32 // 0x148 +} + +// SENS.SAR_READER1_CTRL: RTC ADC1 data and sampling control +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR1_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR1_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR1_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR1_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR1_SAMPLE_NUM(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0x7f80000)|value<<19) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR1_SAMPLE_NUM() uint32 { + return (volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0x7f80000) >> 19 +} +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR1_DATA_INV(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR1_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR1_INT_EN(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR1_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0x20000000) >> 29 +} + +// SENS.SAR_READER1_STATUS: saradc1 status for debug +func (o *SENS_Type) SetSAR_READER1_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_STATUS.Reg, value) +} +func (o *SENS_Type) GetSAR_READER1_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR_READER1_STATUS.Reg) +} + +// SENS.SAR_MEAS1_CTRL1: Configure RTC ADC1 controller +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_RTC_SARADC_RESET(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0x400000)|value<<22) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_RTC_SARADC_RESET() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0x400000) >> 22 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_RTC_SARADC_CLKGATE_EN(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0x800000)|value<<23) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_RTC_SARADC_CLKGATE_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0x800000) >> 23 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_FORCE_XPD_AMP(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0x3000000)|value<<24) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_FORCE_XPD_AMP() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0x3000000) >> 24 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_AMP_RST_FB_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0xc000000)|value<<26) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_AMP_RST_FB_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0xc000000) >> 26 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_AMP_SHORT_REF_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0x30000000)|value<<28) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_AMP_SHORT_REF_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0x30000000) >> 28 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0xc0000000) >> 30 +} + +// SENS.SAR_MEAS1_CTRL2: Control RTC ADC1 conversion and status +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_MEAS1_DATA_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_MEAS1_DATA_SAR() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_MEAS1_DONE_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_MEAS1_DONE_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x10000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_MEAS1_START_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x20000)|value<<17) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_MEAS1_START_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x20000) >> 17 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_MEAS1_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_MEAS1_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_SAR1_EN_PAD(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x7ff80000)|value<<19) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_SAR1_EN_PAD() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x7ff80000) >> 19 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_MEAS1_MUX: Select the controller for SAR ADC1 +func (o *SENS_Type) SetSAR_MEAS1_MUX_SAR1_DIG_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_MUX.Reg, volatile.LoadUint32(&o.SAR_MEAS1_MUX.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS1_MUX_SAR1_DIG_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_MUX.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_ATTEN1: Configure SAR ADC1 attenuation +func (o *SENS_Type) SetSAR_ATTEN1(value uint32) { + volatile.StoreUint32(&o.SAR_ATTEN1.Reg, value) +} +func (o *SENS_Type) GetSAR_ATTEN1() uint32 { + return volatile.LoadUint32(&o.SAR_ATTEN1.Reg) +} + +// SENS.SAR_AMP_CTRL1: AMP control +func (o *SENS_Type) SetSAR_AMP_CTRL1_SAR_AMP_WAIT1(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL1.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL1.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_AMP_CTRL1_SAR_AMP_WAIT1() uint32 { + return volatile.LoadUint32(&o.SAR_AMP_CTRL1.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_AMP_CTRL1_SAR_AMP_WAIT2(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL1.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL1.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_AMP_CTRL1_SAR_AMP_WAIT2() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL1.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_AMP_CTRL2: AMP control +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE() uint32 { + return volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_XPD_SAR_AMP_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_XPD_SAR_AMP_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_AMP_RST_FB_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_AMP_RST_FB_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_AMP_SHORT_REF_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_AMP_SHORT_REF_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_XPD_SAR_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_XPD_SAR_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_AMP_WAIT3(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_AMP_WAIT3() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_AMP_CTRL3: AMP control register +func (o *SENS_Type) SetSAR_AMP_CTRL3_SAR1_DAC_XPD_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf)|value) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_SAR1_DAC_XPD_FSM() uint32 { + return volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_XPD_SAR_AMP_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf0)|value<<4) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_XPD_SAR_AMP_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf0) >> 4 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_AMP_RST_FB_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf00)|value<<8) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_AMP_RST_FB_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf00) >> 8 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_AMP_SHORT_REF_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf000)|value<<12) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_AMP_SHORT_REF_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf000) >> 12 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_AMP_SHORT_REF_GND_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf0000)|value<<16) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_AMP_SHORT_REF_GND_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf0000) >> 16 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_XPD_SAR_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf00000)|value<<20) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_XPD_SAR_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf00000) >> 20 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_SAR_RSTB_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf000000)|value<<24) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_SAR_RSTB_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf000000) >> 24 +} + +// SENS.SAR_READER2_CTRL: RTC ADC2 data and sampling control +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR2_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR2_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR2_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x30000)|value<<16) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR2_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x30000) >> 16 +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR2_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR2_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR2_SAMPLE_NUM(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x7f80000)|value<<19) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR2_SAMPLE_NUM() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x7f80000) >> 19 +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR2_DATA_INV(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR2_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR2_INT_EN(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR2_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x40000000) >> 30 +} + +// SENS.SAR_READER2_STATUS: saradc2 status for debug +func (o *SENS_Type) SetSAR_READER2_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_STATUS.Reg, value) +} +func (o *SENS_Type) GetSAR_READER2_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR_READER2_STATUS.Reg) +} + +// SENS.SAR_MEAS2_CTRL1: configure rtc saradc2 +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR2_CNTL_STATE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0x7)|value) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR2_CNTL_STATE() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0x7 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR2_PWDET_CAL_EN(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR2_PWDET_CAL_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR2_PKDET_CAL_EN(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR2_PKDET_CAL_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR2_EN_TEST(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR2_EN_TEST() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR2_RSTB_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0xc0)|value<<6) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR2_RSTB_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0xc0) >> 6 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR2_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0xff00)|value<<8) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR2_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0xff00) >> 8 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR2_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0xff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR2_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0xff0000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR2_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0xff000000)|value<<24) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR2_XPD_WAIT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0xff000000) >> 24 +} + +// SENS.SAR_MEAS2_CTRL2: Control RTC ADC2 conversion and status +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_MEAS2_DATA_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_MEAS2_DATA_SAR() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_MEAS2_DONE_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_MEAS2_DONE_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x10000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_MEAS2_START_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x20000)|value<<17) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_MEAS2_START_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x20000) >> 17 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_MEAS2_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_MEAS2_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_SAR2_EN_PAD(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x7ff80000)|value<<19) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_SAR2_EN_PAD() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x7ff80000) >> 19 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_MEAS2_MUX: Select the controller for SAR ADC2 +func (o *SENS_Type) SetSAR_MEAS2_MUX_SAR2_PWDET_CCT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_MUX.Reg, volatile.LoadUint32(&o.SAR_MEAS2_MUX.Reg)&^(0x70000000)|value<<28) +} +func (o *SENS_Type) GetSAR_MEAS2_MUX_SAR2_PWDET_CCT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_MUX.Reg) & 0x70000000) >> 28 +} +func (o *SENS_Type) SetSAR_MEAS2_MUX_SAR2_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_MUX.Reg, volatile.LoadUint32(&o.SAR_MEAS2_MUX.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS2_MUX_SAR2_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_MUX.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_ATTEN2: Configure SAR ADC2 attenuation +func (o *SENS_Type) SetSAR_ATTEN2(value uint32) { + volatile.StoreUint32(&o.SAR_ATTEN2.Reg, value) +} +func (o *SENS_Type) GetSAR_ATTEN2() uint32 { + return volatile.LoadUint32(&o.SAR_ATTEN2.Reg) +} + +// SENS.SAR_POWER_XPD_SAR: configure saradc’s power by sw +func (o *SENS_Type) SetSAR_POWER_XPD_SAR_FORCE_XPD_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_POWER_XPD_SAR.Reg, volatile.LoadUint32(&o.SAR_POWER_XPD_SAR.Reg)&^(0x60000000)|value<<29) +} +func (o *SENS_Type) GetSAR_POWER_XPD_SAR_FORCE_XPD_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_POWER_XPD_SAR.Reg) & 0x60000000) >> 29 +} +func (o *SENS_Type) SetSAR_POWER_XPD_SAR_SARCLK_EN(value uint32) { + volatile.StoreUint32(&o.SAR_POWER_XPD_SAR.Reg, volatile.LoadUint32(&o.SAR_POWER_XPD_SAR.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_POWER_XPD_SAR_SARCLK_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_POWER_XPD_SAR.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_SLAVE_ADDR1: Configure slave addresses 0-1 of RTC I2C +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3ff800) >> 11 +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_MEAS_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3fc00000)|value<<22) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_MEAS_STATUS() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3fc00000) >> 22 +} + +// SENS.SAR_SLAVE_ADDR2: Configure slave addresses 2-3 of RTC I2C +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_SLAVE_ADDR3: Configure slave addresses 4-5 of RTC I2C +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_SLAVE_ADDR4: Configure slave addresses 6-7 of RTC I2C +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_TSENS_CTRL: Temperature sensor data control +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_OUT(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_OUT() uint32 { + return volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_READY(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_READY() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_INT_EN(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x1000) >> 12 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_IN_INV(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_IN_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x2000) >> 13 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_POWER_UP(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_POWER_UP() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_POWER_UP_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_POWER_UP_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_TSENS_DUMP_OUT(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_TSENS_DUMP_OUT() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x1000000) >> 24 +} + +// SENS.SAR_TSENS_CTRL2: Temperature sensor control +func (o *SENS_Type) SetSAR_TSENS_CTRL2_TSENS_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg)&^(0xfff)|value) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL2_TSENS_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg) & 0xfff +} +func (o *SENS_Type) SetSAR_TSENS_CTRL2_TSENS_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg)&^(0x3000)|value<<12) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL2_TSENS_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg) & 0x3000) >> 12 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL2_TSENS_CLK_INV(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL2_TSENS_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL2_TSENS_CLKGATE_EN(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg)&^(0x8000)|value<<15) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL2_TSENS_CLKGATE_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg) & 0x8000) >> 15 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL2_TSENS_RESET(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL2_TSENS_RESET() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg) & 0x10000) >> 16 +} + +// SENS.SAR_I2C_CTRL: Configure RTC I2C transmission +func (o *SENS_Type) SetSAR_I2C_CTRL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0xfffffff)|value) +} +func (o *SENS_Type) GetSAR_I2C_CTRL() uint32 { + return volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0xfffffff +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x20000000) >> 29 +} + +// SENS.SAR_TOUCH_CONF: Touch sensor configuration register +func (o *SENS_Type) SetSAR_TOUCH_CONF_TOUCH_OUTEN(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x7fff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_TOUCH_OUTEN() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x7fff +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_TOUCH_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_TOUCH_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x8000) >> 15 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_TOUCH_DATA_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x30000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_TOUCH_DATA_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x30000) >> 16 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_TOUCH_DENOISE_END(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_TOUCH_DENOISE_END() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_TOUCH_UNIT_END(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_TOUCH_UNIT_END() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x80000) >> 19 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_TOUCH_APPROACH_PAD2(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0xf00000)|value<<20) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_TOUCH_APPROACH_PAD2() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0xf00000) >> 20 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_TOUCH_APPROACH_PAD1(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0xf000000)|value<<24) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_TOUCH_APPROACH_PAD1() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0xf000000) >> 24 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_TOUCH_APPROACH_PAD0(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0xf0000000)|value<<28) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_TOUCH_APPROACH_PAD0() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0xf0000000) >> 28 +} + +// SENS.SAR_TOUCH_THRES1: Finger threshold for touch pad 1 +func (o *SENS_Type) SetSAR_TOUCH_THRES1_TOUCH_OUT_TH1(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES1.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES1_TOUCH_OUT_TH1() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES1.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES2: Finger threshold for touch pad 2 +func (o *SENS_Type) SetSAR_TOUCH_THRES2_TOUCH_OUT_TH2(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES2.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES2_TOUCH_OUT_TH2() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES2.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES3: Finger threshold for touch pad 3 +func (o *SENS_Type) SetSAR_TOUCH_THRES3_TOUCH_OUT_TH3(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES3.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES3_TOUCH_OUT_TH3() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES3.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES4: Finger threshold for touch pad 4 +func (o *SENS_Type) SetSAR_TOUCH_THRES4_TOUCH_OUT_TH4(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES4.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES4_TOUCH_OUT_TH4() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES4.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES5: Finger threshold for touch pad 5 +func (o *SENS_Type) SetSAR_TOUCH_THRES5_TOUCH_OUT_TH5(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES5.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES5_TOUCH_OUT_TH5() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES5.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES6: Finger threshold for touch pad 6 +func (o *SENS_Type) SetSAR_TOUCH_THRES6_TOUCH_OUT_TH6(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES6.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES6.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES6_TOUCH_OUT_TH6() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES6.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES7: Finger threshold for touch pad 7 +func (o *SENS_Type) SetSAR_TOUCH_THRES7_TOUCH_OUT_TH7(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES7.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES7.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES7_TOUCH_OUT_TH7() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES7.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES8: Finger threshold for touch pad 8 +func (o *SENS_Type) SetSAR_TOUCH_THRES8_TOUCH_OUT_TH8(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES8.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES8.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES8_TOUCH_OUT_TH8() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES8.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES9: Finger threshold for touch pad 9 +func (o *SENS_Type) SetSAR_TOUCH_THRES9_TOUCH_OUT_TH9(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES9.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES9.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES9_TOUCH_OUT_TH9() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES9.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES10: Finger threshold for touch pad 10 +func (o *SENS_Type) SetSAR_TOUCH_THRES10_TOUCH_OUT_TH10(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES10.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES10.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES10_TOUCH_OUT_TH10() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES10.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES11: Finger threshold for touch pad 11 +func (o *SENS_Type) SetSAR_TOUCH_THRES11_TOUCH_OUT_TH11(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES11.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES11.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES11_TOUCH_OUT_TH11() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES11.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES12: Finger threshold for touch pad 12 +func (o *SENS_Type) SetSAR_TOUCH_THRES12_TOUCH_OUT_TH12(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES12.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES12.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES12_TOUCH_OUT_TH12() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES12.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES13: Finger threshold for touch pad 13 +func (o *SENS_Type) SetSAR_TOUCH_THRES13_TOUCH_OUT_TH13(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES13.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES13.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES13_TOUCH_OUT_TH13() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES13.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES14: Finger threshold for touch pad 14 +func (o *SENS_Type) SetSAR_TOUCH_THRES14_TOUCH_OUT_TH14(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES14.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES14.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES14_TOUCH_OUT_TH14() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES14.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_CHN_ST: Touch channel status register +func (o *SENS_Type) SetSAR_TOUCH_CHN_ST_TOUCH_PAD_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CHN_ST.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg)&^(0x7fff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_CHN_ST_TOUCH_PAD_ACTIVE() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg) & 0x7fff +} +func (o *SENS_Type) SetSAR_TOUCH_CHN_ST_TOUCH_CHANNEL_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CHN_ST.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg)&^(0x3fff8000)|value<<15) +} +func (o *SENS_Type) GetSAR_TOUCH_CHN_ST_TOUCH_CHANNEL_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg) & 0x3fff8000) >> 15 +} +func (o *SENS_Type) SetSAR_TOUCH_CHN_ST_TOUCH_MEAS_DONE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CHN_ST.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_TOUCH_CHN_ST_TOUCH_MEAS_DONE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_TOUCH_STATUS0: Status of touch controller +func (o *SENS_Type) SetSAR_TOUCH_STATUS0_TOUCH_DENOISE_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS0.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS0.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS0_TOUCH_DENOISE_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS0.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS0_TOUCH_SCAN_CURR(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS0.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS0.Reg)&^(0x3c00000)|value<<22) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS0_TOUCH_SCAN_CURR() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS0.Reg) & 0x3c00000) >> 22 +} + +// SENS.SAR_TOUCH_STATUS1: Touch pad 1 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS1_TOUCH_PAD1_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS1.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS1_TOUCH_PAD1_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS1.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS1_TOUCH_PAD1_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS1.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS1_TOUCH_PAD1_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS1.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS2: Touch pad 2 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS2_TOUCH_PAD2_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS2.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS2_TOUCH_PAD2_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS2.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS2_TOUCH_PAD2_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS2.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS2_TOUCH_PAD2_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS2.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS3: Touch pad 3 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS3_TOUCH_PAD3_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS3.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS3_TOUCH_PAD3_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS3.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS3_TOUCH_PAD3_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS3.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS3_TOUCH_PAD3_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS3.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS4: Touch pad 4 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS4_TOUCH_PAD4_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS4.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS4_TOUCH_PAD4_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS4.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS4_TOUCH_PAD4_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS4.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS4_TOUCH_PAD4_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS4.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS5: Touch pad 5 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS5_TOUCH_PAD5_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS5.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS5_TOUCH_PAD5_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS5.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS5_TOUCH_PAD5_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS5.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS5_TOUCH_PAD5_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS5.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS6: Touch pad 6 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS6_TOUCH_PAD6_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS6.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS6.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS6_TOUCH_PAD6_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS6.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS6_TOUCH_PAD6_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS6.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS6.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS6_TOUCH_PAD6_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS6.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS7: Touch pad 7 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS7_TOUCH_PAD7_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS7.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS7.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS7_TOUCH_PAD7_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS7.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS7_TOUCH_PAD7_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS7.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS7.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS7_TOUCH_PAD7_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS7.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS8: Touch pad 8 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS8_TOUCH_PAD8_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS8.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS8.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS8_TOUCH_PAD8_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS8.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS8_TOUCH_PAD8_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS8.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS8.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS8_TOUCH_PAD8_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS8.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS9: Touch pad 9 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS9_TOUCH_PAD9_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS9.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS9.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS9_TOUCH_PAD9_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS9.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS9_TOUCH_PAD9_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS9.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS9.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS9_TOUCH_PAD9_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS9.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS10: Touch pad 10 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS10_TOUCH_PAD10_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS10.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS10.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS10_TOUCH_PAD10_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS10.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS10_TOUCH_PAD10_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS10.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS10.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS10_TOUCH_PAD10_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS10.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS11: Touch pad 11 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS11_TOUCH_PAD11_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS11.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS11.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS11_TOUCH_PAD11_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS11.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS11_TOUCH_PAD11_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS11.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS11.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS11_TOUCH_PAD11_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS11.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS12: Touch pad 12 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS12_TOUCH_PAD12_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS12.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS12.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS12_TOUCH_PAD12_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS12.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS12_TOUCH_PAD12_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS12.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS12.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS12_TOUCH_PAD12_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS12.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS13: Touch pad 13 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS13_TOUCH_PAD13_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS13.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS13.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS13_TOUCH_PAD13_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS13.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS13_TOUCH_PAD13_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS13.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS13.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS13_TOUCH_PAD13_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS13.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS14: Touch pad 14 status +func (o *SENS_Type) SetSAR_TOUCH_STATUS14_TOUCH_PAD14_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS14.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS14.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS14_TOUCH_PAD14_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS14.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS14_TOUCH_PAD14_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS14.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS14.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS14_TOUCH_PAD14_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS14.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS15: Touch sleep pad status +func (o *SENS_Type) SetSAR_TOUCH_STATUS15_TOUCH_SLP_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS15.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS15.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS15_TOUCH_SLP_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS15.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS15_TOUCH_SLP_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS15.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS15.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS15_TOUCH_SLP_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS15.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS16: Touch approach count status +func (o *SENS_Type) SetSAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD2_CNT(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS16.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD2_CNT() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD1_CNT(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS16.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg)&^(0xff00)|value<<8) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD1_CNT() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg) & 0xff00) >> 8 +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD0_CNT(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS16.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg)&^(0xff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD0_CNT() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg) & 0xff0000) >> 16 +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS16_TOUCH_SLP_APPROACH_CNT(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS16.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg)&^(0xff000000)|value<<24) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS16_TOUCH_SLP_APPROACH_CNT() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg) & 0xff000000) >> 24 +} + +// SENS.SAR_DAC_CTRL1: DAC control +func (o *SENS_Type) SetSAR_DAC_CTRL1_SW_FSTEP(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_SW_FSTEP() uint32 { + return volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_SW_TONE_EN(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x10000)|value<<16) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_SW_TONE_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x10000) >> 16 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x3e0000)|value<<17) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DEBUG_BIT_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x3e0000) >> 17 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_DIG_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x400000)|value<<22) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_DIG_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x400000) >> 22 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_CLK_FORCE_LOW(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x800000)|value<<23) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_CLK_FORCE_LOW() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x800000) >> 23 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_CLK_INV(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x2000000) >> 25 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_RESET(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x4000000)|value<<26) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_RESET() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x4000000) >> 26 +} +func (o *SENS_Type) SetSAR_DAC_CTRL1_DAC_CLKGATE_EN(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL1.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg)&^(0x8000000)|value<<27) +} +func (o *SENS_Type) GetSAR_DAC_CTRL1_DAC_CLKGATE_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL1.Reg) & 0x8000000) >> 27 +} + +// SENS.SAR_DAC_CTRL2: DAC output control +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_DC1(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_DC1() uint32 { + return volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_DC2(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0xff00)|value<<8) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_DC2() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0xff00) >> 8 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_SCALE1(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0x30000)|value<<16) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_SCALE1() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0x30000) >> 16 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_SCALE2(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0xc0000)|value<<18) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_SCALE2() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0xc0000) >> 18 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_INV1(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0x300000)|value<<20) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_INV1() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0x300000) >> 20 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_INV2(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0xc00000)|value<<22) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_INV2() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0xc00000) >> 22 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_CW_EN1(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_CW_EN1() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0x1000000) >> 24 +} +func (o *SENS_Type) SetSAR_DAC_CTRL2_DAC_CW_EN2(value uint32) { + volatile.StoreUint32(&o.SAR_DAC_CTRL2.Reg, volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg)&^(0x2000000)|value<<25) +} +func (o *SENS_Type) GetSAR_DAC_CTRL2_DAC_CW_EN2() uint32 { + return (volatile.LoadUint32(&o.SAR_DAC_CTRL2.Reg) & 0x2000000) >> 25 +} + +// SENS.SAR_COCPU_STATE: ULP-RISCV status +func (o *SENS_Type) SetSAR_COCPU_STATE_COCPU_DBG_TRIGGER(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x2000000)|value<<25) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_COCPU_DBG_TRIGGER() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x2000000) >> 25 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_COCPU_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x4000000)|value<<26) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_COCPU_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x4000000) >> 26 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_COCPU_RESET_N(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x8000000)|value<<27) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_COCPU_RESET_N() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x8000000) >> 27 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_COCPU_EOI(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_COCPU_EOI() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_COCPU_TRAP(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_COCPU_TRAP() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x20000000) >> 29 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_COCPU_EBREAK(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_COCPU_EBREAK() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x40000000) >> 30 +} + +// SENS.SAR_COCPU_INT_RAW: Interrupt raw bit of ULP-RISCV +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_SW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_SW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x100) >> 8 +} + +// SENS.SAR_COCPU_INT_ENA: Interrupt enable bit of ULP-RISCV +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_SW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_SW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x100) >> 8 +} + +// SENS.SAR_COCPU_INT_ST: Interrupt status bit of ULP-RISCV +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_TSENS_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_TSENS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_SW_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_SW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_SWD_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_SWD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x100) >> 8 +} + +// SENS.SAR_COCPU_INT_CLR: Interrupt clear bit of ULP-RISCV +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_SW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_SW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x100) >> 8 +} + +// SENS.SAR_COCPU_DEBUG: ULP-RISCV debug register +func (o *SENS_Type) SetSAR_COCPU_DEBUG_COCPU_PC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0x1fff)|value) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_COCPU_PC() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0x1fff +} +func (o *SENS_Type) SetSAR_COCPU_DEBUG_COCPU_MEM_VLD(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0x2000)|value<<13) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_COCPU_MEM_VLD() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0x2000) >> 13 +} +func (o *SENS_Type) SetSAR_COCPU_DEBUG_COCPU_MEM_RDY(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0x4000)|value<<14) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_COCPU_MEM_RDY() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0x4000) >> 14 +} +func (o *SENS_Type) SetSAR_COCPU_DEBUG_COCPU_MEM_WEN(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0x78000)|value<<15) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_COCPU_MEM_WEN() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0x78000) >> 15 +} +func (o *SENS_Type) SetSAR_COCPU_DEBUG_COCPU_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0xfff80000)|value<<19) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_COCPU_MEM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0xfff80000) >> 19 +} + +// SENS.SAR_HALL_CTRL: hall control +func (o *SENS_Type) SetSAR_HALL_CTRL_XPD_HALL(value uint32) { + volatile.StoreUint32(&o.SAR_HALL_CTRL.Reg, volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_HALL_CTRL_XPD_HALL() uint32 { + return (volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_HALL_CTRL_XPD_HALL_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_HALL_CTRL.Reg, volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_HALL_CTRL_XPD_HALL_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *SENS_Type) SetSAR_HALL_CTRL_HALL_PHASE(value uint32) { + volatile.StoreUint32(&o.SAR_HALL_CTRL.Reg, volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_HALL_CTRL_HALL_PHASE() uint32 { + return (volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *SENS_Type) SetSAR_HALL_CTRL_HALL_PHASE_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_HALL_CTRL.Reg, volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_HALL_CTRL_HALL_PHASE_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_NOUSE: sar nouse +func (o *SENS_Type) SetSAR_NOUSE(value uint32) { + volatile.StoreUint32(&o.SAR_NOUSE.Reg, value) +} +func (o *SENS_Type) GetSAR_NOUSE() uint32 { + return volatile.LoadUint32(&o.SAR_NOUSE.Reg) +} + +// SENS.SAR_IO_MUX_CONF: Configure and reset IO MUX +func (o *SENS_Type) SetSAR_IO_MUX_CONF_IOMUX_RESET(value uint32) { + volatile.StoreUint32(&o.SAR_IO_MUX_CONF.Reg, volatile.LoadUint32(&o.SAR_IO_MUX_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_IO_MUX_CONF_IOMUX_RESET() uint32 { + return (volatile.LoadUint32(&o.SAR_IO_MUX_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SENS_Type) SetSAR_IO_MUX_CONF_IOMUX_CLK_GATE_EN(value uint32) { + volatile.StoreUint32(&o.SAR_IO_MUX_CONF.Reg, volatile.LoadUint32(&o.SAR_IO_MUX_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_IO_MUX_CONF_IOMUX_CLK_GATE_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_IO_MUX_CONF.Reg) & 0x80000000) >> 31 +} + +// SENS.SARDATE: Version Control Register +func (o *SENS_Type) SetSARDATE_SAR_DATE(value uint32) { + volatile.StoreUint32(&o.SARDATE.Reg, volatile.LoadUint32(&o.SARDATE.Reg)&^(0xfffffff)|value) +} +func (o *SENS_Type) GetSARDATE_SAR_DATE() uint32 { + return volatile.LoadUint32(&o.SARDATE.Reg) & 0xfffffff +} + +// SHA (Secure Hash Algorithm) Accelerator +type SHA_Type struct { + MODE volatile.Register32 // 0x0 + T_STRING volatile.Register32 // 0x4 + T_LENGTH volatile.Register32 // 0x8 + DMA_BLOCK_NUM volatile.Register32 // 0xC + START volatile.Register32 // 0x10 + CONTINUE volatile.Register32 // 0x14 + BUSY volatile.Register32 // 0x18 + DMA_START volatile.Register32 // 0x1C + DMA_CONTINUE volatile.Register32 // 0x20 + INT_CLEAR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + DATE volatile.Register32 // 0x2C + _ [16]byte + H_MEM0 volatile.Register32 // 0x40 + H_MEM1 volatile.Register32 // 0x44 + H_MEM2 volatile.Register32 // 0x48 + H_MEM3 volatile.Register32 // 0x4C + H_MEM4 volatile.Register32 // 0x50 + H_MEM5 volatile.Register32 // 0x54 + H_MEM6 volatile.Register32 // 0x58 + H_MEM7 volatile.Register32 // 0x5C + H_MEM8 volatile.Register32 // 0x60 + H_MEM9 volatile.Register32 // 0x64 + H_MEM10 volatile.Register32 // 0x68 + H_MEM11 volatile.Register32 // 0x6C + H_MEM12 volatile.Register32 // 0x70 + H_MEM13 volatile.Register32 // 0x74 + H_MEM14 volatile.Register32 // 0x78 + H_MEM15 volatile.Register32 // 0x7C + M_MEM0 volatile.Register32 // 0x80 + M_MEM1 volatile.Register32 // 0x84 + M_MEM2 volatile.Register32 // 0x88 + M_MEM3 volatile.Register32 // 0x8C + M_MEM4 volatile.Register32 // 0x90 + M_MEM5 volatile.Register32 // 0x94 + M_MEM6 volatile.Register32 // 0x98 + M_MEM7 volatile.Register32 // 0x9C + M_MEM8 volatile.Register32 // 0xA0 + M_MEM9 volatile.Register32 // 0xA4 + M_MEM10 volatile.Register32 // 0xA8 + M_MEM11 volatile.Register32 // 0xAC + M_MEM12 volatile.Register32 // 0xB0 + M_MEM13 volatile.Register32 // 0xB4 + M_MEM14 volatile.Register32 // 0xB8 + M_MEM15 volatile.Register32 // 0xBC + M_MEM16 volatile.Register32 // 0xC0 + M_MEM17 volatile.Register32 // 0xC4 + M_MEM18 volatile.Register32 // 0xC8 + M_MEM19 volatile.Register32 // 0xCC + M_MEM20 volatile.Register32 // 0xD0 + M_MEM21 volatile.Register32 // 0xD4 + M_MEM22 volatile.Register32 // 0xD8 + M_MEM23 volatile.Register32 // 0xDC + M_MEM24 volatile.Register32 // 0xE0 + M_MEM25 volatile.Register32 // 0xE4 + M_MEM26 volatile.Register32 // 0xE8 + M_MEM27 volatile.Register32 // 0xEC + M_MEM28 volatile.Register32 // 0xF0 + M_MEM29 volatile.Register32 // 0xF4 + M_MEM30 volatile.Register32 // 0xF8 + M_MEM31 volatile.Register32 // 0xFC +} + +// SHA.MODE: Defines the algorithm of SHA accelerator +func (o *SHA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *SHA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// SHA.T_STRING: String content register for calculating initial Hash Value (only effective for SHA-512/t) +func (o *SHA_Type) SetT_STRING(value uint32) { + volatile.StoreUint32(&o.T_STRING.Reg, value) +} +func (o *SHA_Type) GetT_STRING() uint32 { + return volatile.LoadUint32(&o.T_STRING.Reg) +} + +// SHA.T_LENGTH: String length register for calculating initial Hash Value (only effective for SHA-512/t) +func (o *SHA_Type) SetT_LENGTH(value uint32) { + volatile.StoreUint32(&o.T_LENGTH.Reg, volatile.LoadUint32(&o.T_LENGTH.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetT_LENGTH() uint32 { + return volatile.LoadUint32(&o.T_LENGTH.Reg) & 0x3f +} + +// SHA.DMA_BLOCK_NUM: Block number register (only effective for DMA-SHA) +func (o *SHA_Type) SetDMA_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_NUM.Reg, volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetDMA_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg) & 0x3f +} + +// SHA.START: Starts the SHA accelerator for Typical SHA operation +func (o *SHA_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetSTART() uint32 { + return volatile.LoadUint32(&o.START.Reg) & 0x1 +} + +// SHA.CONTINUE: Continues SHA operation (only effective in Typical SHA mode) +func (o *SHA_Type) SetCONTINUE_CONTINUE_OP(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetCONTINUE_CONTINUE_OP() uint32 { + return volatile.LoadUint32(&o.CONTINUE.Reg) & 0x1 +} + +// SHA.BUSY: Indicates if SHA Accelerator is busy or not +func (o *SHA_Type) SetBUSY_STATE(value uint32) { + volatile.StoreUint32(&o.BUSY.Reg, volatile.LoadUint32(&o.BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetBUSY_STATE() uint32 { + return volatile.LoadUint32(&o.BUSY.Reg) & 0x1 +} + +// SHA.DMA_START: Starts the SHA accelerator for DMA-SHA operation +func (o *SHA_Type) SetDMA_START(value uint32) { + volatile.StoreUint32(&o.DMA_START.Reg, volatile.LoadUint32(&o.DMA_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_START() uint32 { + return volatile.LoadUint32(&o.DMA_START.Reg) & 0x1 +} + +// SHA.DMA_CONTINUE: Continues SHA operation (only effective in DMA-SHA mode) +func (o *SHA_Type) SetDMA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.DMA_CONTINUE.Reg, volatile.LoadUint32(&o.DMA_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_CONTINUE() uint32 { + return volatile.LoadUint32(&o.DMA_CONTINUE.Reg) & 0x1 +} + +// SHA.INT_CLEAR: DMA-SHA interrupt clear register +func (o *SHA_Type) SetINT_CLEAR_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.INT_CLEAR.Reg, volatile.LoadUint32(&o.INT_CLEAR.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetINT_CLEAR_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.INT_CLEAR.Reg) & 0x1 +} + +// SHA.INT_ENA: DMA-SHA interrupt enable register +func (o *SHA_Type) SetINT_ENA_INTERRUPT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetINT_ENA_INTERRUPT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// SHA.DATE: Version control register +func (o *SHA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SHA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// SHA.H_MEM0: Hash value +func (o *SHA_Type) SetH_MEM0(value uint32) { + volatile.StoreUint32(&o.H_MEM0.Reg, value) +} +func (o *SHA_Type) GetH_MEM0() uint32 { + return volatile.LoadUint32(&o.H_MEM0.Reg) +} + +// SHA.H_MEM1: Hash value +func (o *SHA_Type) SetH_MEM1(value uint32) { + volatile.StoreUint32(&o.H_MEM1.Reg, value) +} +func (o *SHA_Type) GetH_MEM1() uint32 { + return volatile.LoadUint32(&o.H_MEM1.Reg) +} + +// SHA.H_MEM2: Hash value +func (o *SHA_Type) SetH_MEM2(value uint32) { + volatile.StoreUint32(&o.H_MEM2.Reg, value) +} +func (o *SHA_Type) GetH_MEM2() uint32 { + return volatile.LoadUint32(&o.H_MEM2.Reg) +} + +// SHA.H_MEM3: Hash value +func (o *SHA_Type) SetH_MEM3(value uint32) { + volatile.StoreUint32(&o.H_MEM3.Reg, value) +} +func (o *SHA_Type) GetH_MEM3() uint32 { + return volatile.LoadUint32(&o.H_MEM3.Reg) +} + +// SHA.H_MEM4: Hash value +func (o *SHA_Type) SetH_MEM4(value uint32) { + volatile.StoreUint32(&o.H_MEM4.Reg, value) +} +func (o *SHA_Type) GetH_MEM4() uint32 { + return volatile.LoadUint32(&o.H_MEM4.Reg) +} + +// SHA.H_MEM5: Hash value +func (o *SHA_Type) SetH_MEM5(value uint32) { + volatile.StoreUint32(&o.H_MEM5.Reg, value) +} +func (o *SHA_Type) GetH_MEM5() uint32 { + return volatile.LoadUint32(&o.H_MEM5.Reg) +} + +// SHA.H_MEM6: Hash value +func (o *SHA_Type) SetH_MEM6(value uint32) { + volatile.StoreUint32(&o.H_MEM6.Reg, value) +} +func (o *SHA_Type) GetH_MEM6() uint32 { + return volatile.LoadUint32(&o.H_MEM6.Reg) +} + +// SHA.H_MEM7: Hash value +func (o *SHA_Type) SetH_MEM7(value uint32) { + volatile.StoreUint32(&o.H_MEM7.Reg, value) +} +func (o *SHA_Type) GetH_MEM7() uint32 { + return volatile.LoadUint32(&o.H_MEM7.Reg) +} + +// SHA.H_MEM8: Hash value +func (o *SHA_Type) SetH_MEM8(value uint32) { + volatile.StoreUint32(&o.H_MEM8.Reg, value) +} +func (o *SHA_Type) GetH_MEM8() uint32 { + return volatile.LoadUint32(&o.H_MEM8.Reg) +} + +// SHA.H_MEM9: Hash value +func (o *SHA_Type) SetH_MEM9(value uint32) { + volatile.StoreUint32(&o.H_MEM9.Reg, value) +} +func (o *SHA_Type) GetH_MEM9() uint32 { + return volatile.LoadUint32(&o.H_MEM9.Reg) +} + +// SHA.H_MEM10: Hash value +func (o *SHA_Type) SetH_MEM10(value uint32) { + volatile.StoreUint32(&o.H_MEM10.Reg, value) +} +func (o *SHA_Type) GetH_MEM10() uint32 { + return volatile.LoadUint32(&o.H_MEM10.Reg) +} + +// SHA.H_MEM11: Hash value +func (o *SHA_Type) SetH_MEM11(value uint32) { + volatile.StoreUint32(&o.H_MEM11.Reg, value) +} +func (o *SHA_Type) GetH_MEM11() uint32 { + return volatile.LoadUint32(&o.H_MEM11.Reg) +} + +// SHA.H_MEM12: Hash value +func (o *SHA_Type) SetH_MEM12(value uint32) { + volatile.StoreUint32(&o.H_MEM12.Reg, value) +} +func (o *SHA_Type) GetH_MEM12() uint32 { + return volatile.LoadUint32(&o.H_MEM12.Reg) +} + +// SHA.H_MEM13: Hash value +func (o *SHA_Type) SetH_MEM13(value uint32) { + volatile.StoreUint32(&o.H_MEM13.Reg, value) +} +func (o *SHA_Type) GetH_MEM13() uint32 { + return volatile.LoadUint32(&o.H_MEM13.Reg) +} + +// SHA.H_MEM14: Hash value +func (o *SHA_Type) SetH_MEM14(value uint32) { + volatile.StoreUint32(&o.H_MEM14.Reg, value) +} +func (o *SHA_Type) GetH_MEM14() uint32 { + return volatile.LoadUint32(&o.H_MEM14.Reg) +} + +// SHA.H_MEM15: Hash value +func (o *SHA_Type) SetH_MEM15(value uint32) { + volatile.StoreUint32(&o.H_MEM15.Reg, value) +} +func (o *SHA_Type) GetH_MEM15() uint32 { + return volatile.LoadUint32(&o.H_MEM15.Reg) +} + +// SHA.M_MEM0: Message +func (o *SHA_Type) SetM_MEM0(value uint32) { + volatile.StoreUint32(&o.M_MEM0.Reg, value) +} +func (o *SHA_Type) GetM_MEM0() uint32 { + return volatile.LoadUint32(&o.M_MEM0.Reg) +} + +// SHA.M_MEM1: Message +func (o *SHA_Type) SetM_MEM1(value uint32) { + volatile.StoreUint32(&o.M_MEM1.Reg, value) +} +func (o *SHA_Type) GetM_MEM1() uint32 { + return volatile.LoadUint32(&o.M_MEM1.Reg) +} + +// SHA.M_MEM2: Message +func (o *SHA_Type) SetM_MEM2(value uint32) { + volatile.StoreUint32(&o.M_MEM2.Reg, value) +} +func (o *SHA_Type) GetM_MEM2() uint32 { + return volatile.LoadUint32(&o.M_MEM2.Reg) +} + +// SHA.M_MEM3: Message +func (o *SHA_Type) SetM_MEM3(value uint32) { + volatile.StoreUint32(&o.M_MEM3.Reg, value) +} +func (o *SHA_Type) GetM_MEM3() uint32 { + return volatile.LoadUint32(&o.M_MEM3.Reg) +} + +// SHA.M_MEM4: Message +func (o *SHA_Type) SetM_MEM4(value uint32) { + volatile.StoreUint32(&o.M_MEM4.Reg, value) +} +func (o *SHA_Type) GetM_MEM4() uint32 { + return volatile.LoadUint32(&o.M_MEM4.Reg) +} + +// SHA.M_MEM5: Message +func (o *SHA_Type) SetM_MEM5(value uint32) { + volatile.StoreUint32(&o.M_MEM5.Reg, value) +} +func (o *SHA_Type) GetM_MEM5() uint32 { + return volatile.LoadUint32(&o.M_MEM5.Reg) +} + +// SHA.M_MEM6: Message +func (o *SHA_Type) SetM_MEM6(value uint32) { + volatile.StoreUint32(&o.M_MEM6.Reg, value) +} +func (o *SHA_Type) GetM_MEM6() uint32 { + return volatile.LoadUint32(&o.M_MEM6.Reg) +} + +// SHA.M_MEM7: Message +func (o *SHA_Type) SetM_MEM7(value uint32) { + volatile.StoreUint32(&o.M_MEM7.Reg, value) +} +func (o *SHA_Type) GetM_MEM7() uint32 { + return volatile.LoadUint32(&o.M_MEM7.Reg) +} + +// SHA.M_MEM8: Message +func (o *SHA_Type) SetM_MEM8(value uint32) { + volatile.StoreUint32(&o.M_MEM8.Reg, value) +} +func (o *SHA_Type) GetM_MEM8() uint32 { + return volatile.LoadUint32(&o.M_MEM8.Reg) +} + +// SHA.M_MEM9: Message +func (o *SHA_Type) SetM_MEM9(value uint32) { + volatile.StoreUint32(&o.M_MEM9.Reg, value) +} +func (o *SHA_Type) GetM_MEM9() uint32 { + return volatile.LoadUint32(&o.M_MEM9.Reg) +} + +// SHA.M_MEM10: Message +func (o *SHA_Type) SetM_MEM10(value uint32) { + volatile.StoreUint32(&o.M_MEM10.Reg, value) +} +func (o *SHA_Type) GetM_MEM10() uint32 { + return volatile.LoadUint32(&o.M_MEM10.Reg) +} + +// SHA.M_MEM11: Message +func (o *SHA_Type) SetM_MEM11(value uint32) { + volatile.StoreUint32(&o.M_MEM11.Reg, value) +} +func (o *SHA_Type) GetM_MEM11() uint32 { + return volatile.LoadUint32(&o.M_MEM11.Reg) +} + +// SHA.M_MEM12: Message +func (o *SHA_Type) SetM_MEM12(value uint32) { + volatile.StoreUint32(&o.M_MEM12.Reg, value) +} +func (o *SHA_Type) GetM_MEM12() uint32 { + return volatile.LoadUint32(&o.M_MEM12.Reg) +} + +// SHA.M_MEM13: Message +func (o *SHA_Type) SetM_MEM13(value uint32) { + volatile.StoreUint32(&o.M_MEM13.Reg, value) +} +func (o *SHA_Type) GetM_MEM13() uint32 { + return volatile.LoadUint32(&o.M_MEM13.Reg) +} + +// SHA.M_MEM14: Message +func (o *SHA_Type) SetM_MEM14(value uint32) { + volatile.StoreUint32(&o.M_MEM14.Reg, value) +} +func (o *SHA_Type) GetM_MEM14() uint32 { + return volatile.LoadUint32(&o.M_MEM14.Reg) +} + +// SHA.M_MEM15: Message +func (o *SHA_Type) SetM_MEM15(value uint32) { + volatile.StoreUint32(&o.M_MEM15.Reg, value) +} +func (o *SHA_Type) GetM_MEM15() uint32 { + return volatile.LoadUint32(&o.M_MEM15.Reg) +} + +// SHA.M_MEM16: Message +func (o *SHA_Type) SetM_MEM16(value uint32) { + volatile.StoreUint32(&o.M_MEM16.Reg, value) +} +func (o *SHA_Type) GetM_MEM16() uint32 { + return volatile.LoadUint32(&o.M_MEM16.Reg) +} + +// SHA.M_MEM17: Message +func (o *SHA_Type) SetM_MEM17(value uint32) { + volatile.StoreUint32(&o.M_MEM17.Reg, value) +} +func (o *SHA_Type) GetM_MEM17() uint32 { + return volatile.LoadUint32(&o.M_MEM17.Reg) +} + +// SHA.M_MEM18: Message +func (o *SHA_Type) SetM_MEM18(value uint32) { + volatile.StoreUint32(&o.M_MEM18.Reg, value) +} +func (o *SHA_Type) GetM_MEM18() uint32 { + return volatile.LoadUint32(&o.M_MEM18.Reg) +} + +// SHA.M_MEM19: Message +func (o *SHA_Type) SetM_MEM19(value uint32) { + volatile.StoreUint32(&o.M_MEM19.Reg, value) +} +func (o *SHA_Type) GetM_MEM19() uint32 { + return volatile.LoadUint32(&o.M_MEM19.Reg) +} + +// SHA.M_MEM20: Message +func (o *SHA_Type) SetM_MEM20(value uint32) { + volatile.StoreUint32(&o.M_MEM20.Reg, value) +} +func (o *SHA_Type) GetM_MEM20() uint32 { + return volatile.LoadUint32(&o.M_MEM20.Reg) +} + +// SHA.M_MEM21: Message +func (o *SHA_Type) SetM_MEM21(value uint32) { + volatile.StoreUint32(&o.M_MEM21.Reg, value) +} +func (o *SHA_Type) GetM_MEM21() uint32 { + return volatile.LoadUint32(&o.M_MEM21.Reg) +} + +// SHA.M_MEM22: Message +func (o *SHA_Type) SetM_MEM22(value uint32) { + volatile.StoreUint32(&o.M_MEM22.Reg, value) +} +func (o *SHA_Type) GetM_MEM22() uint32 { + return volatile.LoadUint32(&o.M_MEM22.Reg) +} + +// SHA.M_MEM23: Message +func (o *SHA_Type) SetM_MEM23(value uint32) { + volatile.StoreUint32(&o.M_MEM23.Reg, value) +} +func (o *SHA_Type) GetM_MEM23() uint32 { + return volatile.LoadUint32(&o.M_MEM23.Reg) +} + +// SHA.M_MEM24: Message +func (o *SHA_Type) SetM_MEM24(value uint32) { + volatile.StoreUint32(&o.M_MEM24.Reg, value) +} +func (o *SHA_Type) GetM_MEM24() uint32 { + return volatile.LoadUint32(&o.M_MEM24.Reg) +} + +// SHA.M_MEM25: Message +func (o *SHA_Type) SetM_MEM25(value uint32) { + volatile.StoreUint32(&o.M_MEM25.Reg, value) +} +func (o *SHA_Type) GetM_MEM25() uint32 { + return volatile.LoadUint32(&o.M_MEM25.Reg) +} + +// SHA.M_MEM26: Message +func (o *SHA_Type) SetM_MEM26(value uint32) { + volatile.StoreUint32(&o.M_MEM26.Reg, value) +} +func (o *SHA_Type) GetM_MEM26() uint32 { + return volatile.LoadUint32(&o.M_MEM26.Reg) +} + +// SHA.M_MEM27: Message +func (o *SHA_Type) SetM_MEM27(value uint32) { + volatile.StoreUint32(&o.M_MEM27.Reg, value) +} +func (o *SHA_Type) GetM_MEM27() uint32 { + return volatile.LoadUint32(&o.M_MEM27.Reg) +} + +// SHA.M_MEM28: Message +func (o *SHA_Type) SetM_MEM28(value uint32) { + volatile.StoreUint32(&o.M_MEM28.Reg, value) +} +func (o *SHA_Type) GetM_MEM28() uint32 { + return volatile.LoadUint32(&o.M_MEM28.Reg) +} + +// SHA.M_MEM29: Message +func (o *SHA_Type) SetM_MEM29(value uint32) { + volatile.StoreUint32(&o.M_MEM29.Reg, value) +} +func (o *SHA_Type) GetM_MEM29() uint32 { + return volatile.LoadUint32(&o.M_MEM29.Reg) +} + +// SHA.M_MEM30: Message +func (o *SHA_Type) SetM_MEM30(value uint32) { + volatile.StoreUint32(&o.M_MEM30.Reg, value) +} +func (o *SHA_Type) GetM_MEM30() uint32 { + return volatile.LoadUint32(&o.M_MEM30.Reg) +} + +// SHA.M_MEM31: Message +func (o *SHA_Type) SetM_MEM31(value uint32) { + volatile.StoreUint32(&o.M_MEM31.Reg, value) +} +func (o *SHA_Type) GetM_MEM31() uint32 { + return volatile.LoadUint32(&o.M_MEM31.Reg) +} + +// SPI (Serial Peripheral Interface) Controller 0 +type SPI_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CTRL1 volatile.Register32 // 0xC + CTRL2 volatile.Register32 // 0x10 + CLOCK volatile.Register32 // 0x14 + USER volatile.Register32 // 0x18 + USER1 volatile.Register32 // 0x1C + USER2 volatile.Register32 // 0x20 + MOSI_DLEN volatile.Register32 // 0x24 + MISO_DLEN volatile.Register32 // 0x28 + MISC volatile.Register32 // 0x2C + SLAVE volatile.Register32 // 0x30 + SLAVE1 volatile.Register32 // 0x34 + SLV_WRBUF_DLEN volatile.Register32 // 0x38 + SLV_RDBUF_DLEN volatile.Register32 // 0x3C + SLV_RD_BYTE volatile.Register32 // 0x40 + FSM volatile.Register32 // 0x44 + HOLD volatile.Register32 // 0x48 + DMA_CONF volatile.Register32 // 0x4C + DMA_OUT_LINK volatile.Register32 // 0x50 + DMA_IN_LINK volatile.Register32 // 0x54 + DMA_INT_ENA volatile.Register32 // 0x58 + DMA_INT_RAW volatile.Register32 // 0x5C + DMA_INT_ST volatile.Register32 // 0x60 + DMA_INT_CLR volatile.Register32 // 0x64 + IN_ERR_EOF_DES_ADDR volatile.Register32 // 0x68 + IN_SUC_EOF_DES_ADDR volatile.Register32 // 0x6C + INLINK_DSCR volatile.Register32 // 0x70 + INLINK_DSCR_BF0 volatile.Register32 // 0x74 + INLINK_DSCR_BF1 volatile.Register32 // 0x78 + OUT_EOF_BFR_DES_ADDR volatile.Register32 // 0x7C + OUT_EOF_DES_ADDR volatile.Register32 // 0x80 + OUTLINK_DSCR volatile.Register32 // 0x84 + OUTLINK_DSCR_BF0 volatile.Register32 // 0x88 + OUTLINK_DSCR_BF1 volatile.Register32 // 0x8C + DMA_OUTSTATUS volatile.Register32 // 0x90 + DMA_INSTATUS volatile.Register32 // 0x94 + W0 volatile.Register32 // 0x98 + W1 volatile.Register32 // 0x9C + W2 volatile.Register32 // 0xA0 + W3 volatile.Register32 // 0xA4 + W4 volatile.Register32 // 0xA8 + W5 volatile.Register32 // 0xAC + W6 volatile.Register32 // 0xB0 + W7 volatile.Register32 // 0xB4 + W8 volatile.Register32 // 0xB8 + W9 volatile.Register32 // 0xBC + W10 volatile.Register32 // 0xC0 + W11 volatile.Register32 // 0xC4 + W12 volatile.Register32 // 0xC8 + W13 volatile.Register32 // 0xCC + W14 volatile.Register32 // 0xD0 + W15 volatile.Register32 // 0xD4 + W16 volatile.Register32 // 0xD8 + W17 volatile.Register32 // 0xDC + DIN_MODE volatile.Register32 // 0xE0 + DIN_NUM volatile.Register32 // 0xE4 + DOUT_MODE volatile.Register32 // 0xE8 + DOUT_NUM volatile.Register32 // 0xEC + LCD_CTRL volatile.Register32 // 0xF0 + LCD_CTRL1 volatile.Register32 // 0xF4 + LCD_CTRL2 volatile.Register32 // 0xF8 + LCD_D_MODE volatile.Register32 // 0xFC + LCD_D_NUM volatile.Register32 // 0x100 + _ [760]byte + REG_DATE volatile.Register32 // 0x3FC +} + +// SPI.CMD: Command control register +func (o *SPI_Type) SetCMD_CONF_BITLEN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x7fffff)|value) +} +func (o *SPI_Type) GetCMD_CONF_BITLEN() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x7fffff +} +func (o *SPI_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} + +// SPI.ADDR: Address value +func (o *SPI_Type) SetADDR(value uint32) { + volatile.StoreUint32(&o.ADDR.Reg, value) +} +func (o *SPI_Type) GetADDR() uint32 { + return volatile.LoadUint32(&o.ADDR.Reg) +} + +// SPI.CTRL: SPI control register +func (o *SPI_Type) SetCTRL_EXT_HOLD_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetCTRL_EXT_HOLD_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetCTRL_DUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetCTRL_DUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetCTRL_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetCTRL_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI_Type) SetCTRL_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetCTRL_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI_Type) SetCTRL_FREAD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *SPI_Type) GetCTRL_FREAD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} +func (o *SPI_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI_Type) SetCTRL_WP(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI_Type) GetCTRL_WP() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI_Type) SetCTRL_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI_Type) GetCTRL_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000000) >> 25 +} +func (o *SPI_Type) SetCTRL_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI_Type) GetCTRL_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000000) >> 26 +} + +// SPI.CTRL1: SPI control register 1 +func (o *SPI_Type) SetCTRL1_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI_Type) GetCTRL1_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.CTRL1.Reg) & 0x3 +} +func (o *SPI_Type) SetCTRL1_CLK_MODE_13(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetCTRL1_CLK_MODE_13() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetCTRL1_RSCK_DATA_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetCTRL1_RSCK_DATA_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetCTRL1_W16_17_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetCTRL1_W16_17_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetCTRL1_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0xfc000)|value<<14) +} +func (o *SPI_Type) GetCTRL1_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0xfc000) >> 14 +} + +// SPI.CTRL2: SPI control register 2 +func (o *SPI_Type) SetCTRL2_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1fff)|value) +} +func (o *SPI_Type) GetCTRL2_CS_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1fff +} +func (o *SPI_Type) SetCTRL2_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x3ffe000)|value<<13) +} +func (o *SPI_Type) GetCTRL2_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x3ffe000) >> 13 +} +func (o *SPI_Type) SetCTRL2_CS_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1c000000)|value<<26) +} +func (o *SPI_Type) GetCTRL2_CS_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1c000000) >> 26 +} +func (o *SPI_Type) SetCTRL2_CS_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x60000000)|value<<29) +} +func (o *SPI_Type) GetCTRL2_CS_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x60000000) >> 29 +} + +// SPI.CLOCK: SPI clock control register +func (o *SPI_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f +} +func (o *SPI_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI_Type) SetCLOCK_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *SPI_Type) GetCLOCK_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x7ffc0000) >> 18 +} +func (o *SPI_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI.USER: SPI USER control register +func (o *SPI_Type) SetUSER_DOUTDIN(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetUSER_DOUTDIN() uint32 { + return volatile.LoadUint32(&o.USER.Reg) & 0x1 +} +func (o *SPI_Type) SetUSER_QPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetUSER_QPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetUSER_OPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetUSER_OPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetUSER_TSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetUSER_TSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetUSER_RSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetUSER_RSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x100) >> 8 +} +func (o *SPI_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI_Type) SetUSER_RD_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetUSER_RD_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetUSER_WR_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetUSER_WR_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI_Type) SetUSER_FWRITE_OCT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetUSER_FWRITE_OCT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetUSER_USR_CONF_NXT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetUSER_USR_CONF_NXT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI_Type) SetUSER_SIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000)|value<<16) +} +func (o *SPI_Type) GetUSER_SIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000) >> 16 +} +func (o *SPI_Type) SetUSER_USR_HOLD_POL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000)|value<<17) +} +func (o *SPI_Type) GetUSER_USR_HOLD_POL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000) >> 17 +} +func (o *SPI_Type) SetUSER_USR_DOUT_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000)|value<<18) +} +func (o *SPI_Type) GetUSER_USR_DOUT_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000) >> 18 +} +func (o *SPI_Type) SetUSER_USR_DIN_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000)|value<<19) +} +func (o *SPI_Type) GetUSER_USR_DIN_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000) >> 19 +} +func (o *SPI_Type) SetUSER_USR_DUMMY_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x100000)|value<<20) +} +func (o *SPI_Type) GetUSER_USR_DUMMY_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x100000) >> 20 +} +func (o *SPI_Type) SetUSER_USR_ADDR_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200000)|value<<21) +} +func (o *SPI_Type) GetUSER_USR_ADDR_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200000) >> 21 +} +func (o *SPI_Type) SetUSER_USR_CMD_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x400000)|value<<22) +} +func (o *SPI_Type) GetUSER_USR_CMD_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x400000) >> 22 +} +func (o *SPI_Type) SetUSER_USR_PREP_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x800000)|value<<23) +} +func (o *SPI_Type) GetUSER_USR_PREP_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x800000) >> 23 +} +func (o *SPI_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI.USER1: SPI USER control register 1 +func (o *SPI_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xff)|value) +} +func (o *SPI_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0xff +} +func (o *SPI_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xf8000000) >> 27 +} + +// SPI.USER2: SPI USER control register 2 +func (o *SPI_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI.MOSI_DLEN: MOSI length +func (o *SPI_Type) SetMOSI_DLEN_USR_MOSI_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MOSI_DLEN.Reg, volatile.LoadUint32(&o.MOSI_DLEN.Reg)&^(0x7fffff)|value) +} +func (o *SPI_Type) GetMOSI_DLEN_USR_MOSI_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MOSI_DLEN.Reg) & 0x7fffff +} + +// SPI.MISO_DLEN: MISO length +func (o *SPI_Type) SetMISO_DLEN_USR_MISO_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MISO_DLEN.Reg, volatile.LoadUint32(&o.MISO_DLEN.Reg)&^(0x7fffff)|value) +} +func (o *SPI_Type) GetMISO_DLEN_USR_MISO_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MISO_DLEN.Reg) & 0x7fffff +} + +// SPI.MISC: SPI misc register +func (o *SPI_Type) SetMISC_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetMISC_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.MISC.Reg) & 0x1 +} +func (o *SPI_Type) SetMISC_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetMISC_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetMISC_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetMISC_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetMISC_CS3_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetMISC_CS3_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetMISC_CS4_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetMISC_CS4_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetMISC_CS5_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetMISC_CS5_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetMISC_CK_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetMISC_CK_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetMISC_MASTER_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1f80)|value<<7) +} +func (o *SPI_Type) GetMISC_MASTER_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1f80) >> 7 +} +func (o *SPI_Type) SetMISC_CLK_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI_Type) GetMISC_CLK_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10000) >> 16 +} +func (o *SPI_Type) SetMISC_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000)|value<<17) +} +func (o *SPI_Type) GetMISC_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000) >> 17 +} +func (o *SPI_Type) SetMISC_ADDR_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000)|value<<18) +} +func (o *SPI_Type) GetMISC_ADDR_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000) >> 18 +} +func (o *SPI_Type) SetMISC_CMD_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000)|value<<19) +} +func (o *SPI_Type) GetMISC_CMD_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000) >> 19 +} +func (o *SPI_Type) SetMISC_CD_DATA_SET(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x100000)|value<<20) +} +func (o *SPI_Type) GetMISC_CD_DATA_SET() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x100000) >> 20 +} +func (o *SPI_Type) SetMISC_CD_DUMMY_SET(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x200000)|value<<21) +} +func (o *SPI_Type) GetMISC_CD_DUMMY_SET() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x200000) >> 21 +} +func (o *SPI_Type) SetMISC_CD_ADDR_SET(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x400000)|value<<22) +} +func (o *SPI_Type) GetMISC_CD_ADDR_SET() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x400000) >> 22 +} +func (o *SPI_Type) SetMISC_SLAVE_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x800000)|value<<23) +} +func (o *SPI_Type) GetMISC_SLAVE_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x800000) >> 23 +} +func (o *SPI_Type) SetMISC_DQS_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI_Type) GetMISC_DQS_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1000000) >> 24 +} +func (o *SPI_Type) SetMISC_CD_CMD_SET(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI_Type) GetMISC_CD_CMD_SET() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2000000) >> 25 +} +func (o *SPI_Type) SetMISC_CD_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI_Type) GetMISC_CD_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x4000000) >> 26 +} +func (o *SPI_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetMISC_QUAD_DIN_PIN_SWAP(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetMISC_QUAD_DIN_PIN_SWAP() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000000) >> 31 +} + +// SPI.SLAVE: SPI slave control register +func (o *SPI_Type) SetSLAVE_TRANS_DONE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetSLAVE_TRANS_DONE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetSLAVE_INT_RD_BUF_DONE_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetSLAVE_INT_RD_BUF_DONE_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetSLAVE_INT_WR_BUF_DONE_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetSLAVE_INT_WR_BUF_DONE_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetSLAVE_INT_RD_DMA_DONE_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetSLAVE_INT_RD_DMA_DONE_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetSLAVE_INT_WR_DMA_DONE_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetSLAVE_INT_WR_DMA_DONE_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x100) >> 8 +} +func (o *SPI_Type) SetSLAVE_INT_TRANS_DONE_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x200)|value<<9) +} +func (o *SPI_Type) GetSLAVE_INT_TRANS_DONE_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x200) >> 9 +} +func (o *SPI_Type) SetSLAVE_INT_DMA_SEG_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetSLAVE_INT_DMA_SEG_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetSLAVE_SEG_MAGIC_ERR_INT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetSLAVE_SEG_MAGIC_ERR_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetSLAVE_TRANS_CNT(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x7800000)|value<<23) +} +func (o *SPI_Type) GetSLAVE_TRANS_CNT() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x7800000) >> 23 +} +func (o *SPI_Type) SetSLAVE_TRANS_DONE_AUTO_CLR_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetSLAVE_TRANS_DONE_AUTO_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetSLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetSLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetSLAVE_SOFT_RESET(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetSLAVE_SOFT_RESET() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x80000000) >> 31 +} + +// SPI.SLAVE1: SPI slave control register 1 +func (o *SPI_Type) SetSLAVE1_SLV_ADDR_ERR_CLR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetSLAVE1_SLV_ADDR_ERR_CLR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetSLAVE1_SLV_CMD_ERR_CLR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetSLAVE1_SLV_CMD_ERR_CLR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetSLAVE1_SLV_NO_QPI_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetSLAVE1_SLV_NO_QPI_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetSLAVE1_SLV_ADDR_ERR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x2000)|value<<13) +} +func (o *SPI_Type) GetSLAVE1_SLV_ADDR_ERR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x2000) >> 13 +} +func (o *SPI_Type) SetSLAVE1_SLV_CMD_ERR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetSLAVE1_SLV_CMD_ERR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetSLAVE1_SLV_WR_DMA_DONE(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetSLAVE1_SLV_WR_DMA_DONE() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x8000) >> 15 +} +func (o *SPI_Type) SetSLAVE1_SLV_LAST_COMMAND(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI_Type) GetSLAVE1_SLV_LAST_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0xff0000) >> 16 +} +func (o *SPI_Type) SetSLAVE1_SLV_LAST_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI_Type) GetSLAVE1_SLV_LAST_ADDR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0xff000000) >> 24 +} + +// SPI.SLV_WRBUF_DLEN: SPI slave Wr_BUF interrupt and CONF control register +func (o *SPI_Type) SetSLV_WRBUF_DLEN_SLV_WR_BUF_DONE(value uint32) { + volatile.StoreUint32(&o.SLV_WRBUF_DLEN.Reg, volatile.LoadUint32(&o.SLV_WRBUF_DLEN.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI_Type) GetSLV_WRBUF_DLEN_SLV_WR_BUF_DONE() uint32 { + return (volatile.LoadUint32(&o.SLV_WRBUF_DLEN.Reg) & 0x1000000) >> 24 +} +func (o *SPI_Type) SetSLV_WRBUF_DLEN_CONF_BASE_BITLEN(value uint32) { + volatile.StoreUint32(&o.SLV_WRBUF_DLEN.Reg, volatile.LoadUint32(&o.SLV_WRBUF_DLEN.Reg)&^(0xfe000000)|value<<25) +} +func (o *SPI_Type) GetSLV_WRBUF_DLEN_CONF_BASE_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SLV_WRBUF_DLEN.Reg) & 0xfe000000) >> 25 +} + +// SPI.SLV_RDBUF_DLEN: SPI magic error and slave control register +func (o *SPI_Type) SetSLV_RDBUF_DLEN_SLV_DMA_RD_BYTELEN(value uint32) { + volatile.StoreUint32(&o.SLV_RDBUF_DLEN.Reg, volatile.LoadUint32(&o.SLV_RDBUF_DLEN.Reg)&^(0xfffff)|value) +} +func (o *SPI_Type) GetSLV_RDBUF_DLEN_SLV_DMA_RD_BYTELEN() uint32 { + return volatile.LoadUint32(&o.SLV_RDBUF_DLEN.Reg) & 0xfffff +} +func (o *SPI_Type) SetSLV_RDBUF_DLEN_SLV_RD_BUF_DONE(value uint32) { + volatile.StoreUint32(&o.SLV_RDBUF_DLEN.Reg, volatile.LoadUint32(&o.SLV_RDBUF_DLEN.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI_Type) GetSLV_RDBUF_DLEN_SLV_RD_BUF_DONE() uint32 { + return (volatile.LoadUint32(&o.SLV_RDBUF_DLEN.Reg) & 0x1000000) >> 24 +} +func (o *SPI_Type) SetSLV_RDBUF_DLEN_SEG_MAGIC_ERR(value uint32) { + volatile.StoreUint32(&o.SLV_RDBUF_DLEN.Reg, volatile.LoadUint32(&o.SLV_RDBUF_DLEN.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI_Type) GetSLV_RDBUF_DLEN_SEG_MAGIC_ERR() uint32 { + return (volatile.LoadUint32(&o.SLV_RDBUF_DLEN.Reg) & 0x2000000) >> 25 +} + +// SPI.SLV_RD_BYTE: SPI interrupt control register +func (o *SPI_Type) SetSLV_RD_BYTE_SLV_DATA_BYTELEN(value uint32) { + volatile.StoreUint32(&o.SLV_RD_BYTE.Reg, volatile.LoadUint32(&o.SLV_RD_BYTE.Reg)&^(0xfffff)|value) +} +func (o *SPI_Type) GetSLV_RD_BYTE_SLV_DATA_BYTELEN() uint32 { + return volatile.LoadUint32(&o.SLV_RD_BYTE.Reg) & 0xfffff +} +func (o *SPI_Type) SetSLV_RD_BYTE_SLV_RDDMA_BYTELEN_EN(value uint32) { + volatile.StoreUint32(&o.SLV_RD_BYTE.Reg, volatile.LoadUint32(&o.SLV_RD_BYTE.Reg)&^(0x100000)|value<<20) +} +func (o *SPI_Type) GetSLV_RD_BYTE_SLV_RDDMA_BYTELEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLV_RD_BYTE.Reg) & 0x100000) >> 20 +} +func (o *SPI_Type) SetSLV_RD_BYTE_SLV_WRDMA_BYTELEN_EN(value uint32) { + volatile.StoreUint32(&o.SLV_RD_BYTE.Reg, volatile.LoadUint32(&o.SLV_RD_BYTE.Reg)&^(0x200000)|value<<21) +} +func (o *SPI_Type) GetSLV_RD_BYTE_SLV_WRDMA_BYTELEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLV_RD_BYTE.Reg) & 0x200000) >> 21 +} +func (o *SPI_Type) SetSLV_RD_BYTE_SLV_RDBUF_BYTELEN_EN(value uint32) { + volatile.StoreUint32(&o.SLV_RD_BYTE.Reg, volatile.LoadUint32(&o.SLV_RD_BYTE.Reg)&^(0x400000)|value<<22) +} +func (o *SPI_Type) GetSLV_RD_BYTE_SLV_RDBUF_BYTELEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLV_RD_BYTE.Reg) & 0x400000) >> 22 +} +func (o *SPI_Type) SetSLV_RD_BYTE_SLV_WRBUF_BYTELEN_EN(value uint32) { + volatile.StoreUint32(&o.SLV_RD_BYTE.Reg, volatile.LoadUint32(&o.SLV_RD_BYTE.Reg)&^(0x800000)|value<<23) +} +func (o *SPI_Type) GetSLV_RD_BYTE_SLV_WRBUF_BYTELEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLV_RD_BYTE.Reg) & 0x800000) >> 23 +} +func (o *SPI_Type) SetSLV_RD_BYTE_DMA_SEG_MAGIC_VALUE(value uint32) { + volatile.StoreUint32(&o.SLV_RD_BYTE.Reg, volatile.LoadUint32(&o.SLV_RD_BYTE.Reg)&^(0xf000000)|value<<24) +} +func (o *SPI_Type) GetSLV_RD_BYTE_DMA_SEG_MAGIC_VALUE() uint32 { + return (volatile.LoadUint32(&o.SLV_RD_BYTE.Reg) & 0xf000000) >> 24 +} +func (o *SPI_Type) SetSLV_RD_BYTE_SLV_RD_DMA_DONE(value uint32) { + volatile.StoreUint32(&o.SLV_RD_BYTE.Reg, volatile.LoadUint32(&o.SLV_RD_BYTE.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetSLV_RD_BYTE_SLV_RD_DMA_DONE() uint32 { + return (volatile.LoadUint32(&o.SLV_RD_BYTE.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetSLV_RD_BYTE_USR_CONF(value uint32) { + volatile.StoreUint32(&o.SLV_RD_BYTE.Reg, volatile.LoadUint32(&o.SLV_RD_BYTE.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetSLV_RD_BYTE_USR_CONF() uint32 { + return (volatile.LoadUint32(&o.SLV_RD_BYTE.Reg) & 0x80000000) >> 31 +} + +// SPI.FSM: SPI master status and DMA read byte control register +func (o *SPI_Type) SetFSM_ST(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0xf)|value) +} +func (o *SPI_Type) GetFSM_ST() uint32 { + return volatile.LoadUint32(&o.FSM.Reg) & 0xf +} +func (o *SPI_Type) SetFSM_MST_DMA_RD_BYTELEN(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0xfffff000)|value<<12) +} +func (o *SPI_Type) GetFSM_MST_DMA_RD_BYTELEN() uint32 { + return (volatile.LoadUint32(&o.FSM.Reg) & 0xfffff000) >> 12 +} + +// SPI.HOLD: SPI hold register +func (o *SPI_Type) SetHOLD_INT_HOLD_ENA(value uint32) { + volatile.StoreUint32(&o.HOLD.Reg, volatile.LoadUint32(&o.HOLD.Reg)&^(0x3)|value) +} +func (o *SPI_Type) GetHOLD_INT_HOLD_ENA() uint32 { + return volatile.LoadUint32(&o.HOLD.Reg) & 0x3 +} +func (o *SPI_Type) SetHOLD_VAL(value uint32) { + volatile.StoreUint32(&o.HOLD.Reg, volatile.LoadUint32(&o.HOLD.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetHOLD_VAL() uint32 { + return (volatile.LoadUint32(&o.HOLD.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetHOLD_OUT_EN(value uint32) { + volatile.StoreUint32(&o.HOLD.Reg, volatile.LoadUint32(&o.HOLD.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetHOLD_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.HOLD.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetHOLD_OUT_TIME(value uint32) { + volatile.StoreUint32(&o.HOLD.Reg, volatile.LoadUint32(&o.HOLD.Reg)&^(0x70)|value<<4) +} +func (o *SPI_Type) GetHOLD_OUT_TIME() uint32 { + return (volatile.LoadUint32(&o.HOLD.Reg) & 0x70) >> 4 +} +func (o *SPI_Type) SetHOLD_DMA_SEG_TRANS_DONE(value uint32) { + volatile.StoreUint32(&o.HOLD.Reg, volatile.LoadUint32(&o.HOLD.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetHOLD_DMA_SEG_TRANS_DONE() uint32 { + return (volatile.LoadUint32(&o.HOLD.Reg) & 0x80) >> 7 +} + +// SPI.DMA_CONF: SPI DMA control register +func (o *SPI_Type) SetDMA_CONF_IN_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_CONF_IN_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_CONF_OUT_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_CONF_OUT_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_CONF_AHBM_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_CONF_AHBM_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_CONF_AHBM_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_CONF_AHBM_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_CONF_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_CONF_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_CONF_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_CONF_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_CONF_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_CONF_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x100) >> 8 +} +func (o *SPI_Type) SetDMA_CONF_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x200)|value<<9) +} +func (o *SPI_Type) GetDMA_CONF_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x200) >> 9 +} +func (o *SPI_Type) SetDMA_CONF_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetDMA_CONF_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetDMA_CONF_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetDMA_CONF_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetDMA_CONF_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetDMA_CONF_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetDMA_CONF_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *SPI_Type) GetDMA_CONF_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x2000) >> 13 +} +func (o *SPI_Type) SetDMA_CONF_DMA_RX_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetDMA_CONF_DMA_RX_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetDMA_CONF_DMA_TX_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetDMA_CONF_DMA_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x8000) >> 15 +} +func (o *SPI_Type) SetDMA_CONF_DMA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *SPI_Type) GetDMA_CONF_DMA_CONTINUE() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10000) >> 16 +} +func (o *SPI_Type) SetDMA_CONF_SLV_LAST_SEG_POP_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *SPI_Type) GetDMA_CONF_SLV_LAST_SEG_POP_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x20000) >> 17 +} +func (o *SPI_Type) SetDMA_CONF_DMA_SLV_SEG_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SPI_Type) GetDMA_CONF_DMA_SLV_SEG_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000) >> 18 +} +func (o *SPI_Type) SetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SPI_Type) GetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000) >> 19 +} +func (o *SPI_Type) SetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SPI_Type) GetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x100000) >> 20 +} +func (o *SPI_Type) SetDMA_CONF_RX_EOF_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *SPI_Type) GetDMA_CONF_RX_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x200000) >> 21 +} +func (o *SPI_Type) SetDMA_CONF_DMA_INFIFO_FULL_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *SPI_Type) GetDMA_CONF_DMA_INFIFO_FULL_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x400000) >> 22 +} +func (o *SPI_Type) SetDMA_CONF_DMA_OUTFIFO_EMPTY_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *SPI_Type) GetDMA_CONF_DMA_OUTFIFO_EMPTY_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x800000) >> 23 +} +func (o *SPI_Type) SetDMA_CONF_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0xc000000)|value<<26) +} +func (o *SPI_Type) GetDMA_CONF_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0xc000000) >> 26 +} +func (o *SPI_Type) SetDMA_CONF_DMA_SEG_TRANS_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetDMA_CONF_DMA_SEG_TRANS_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10000000) >> 28 +} + +// SPI.DMA_OUT_LINK: SPI DMA TX link configuration +func (o *SPI_Type) SetDMA_OUT_LINK_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0xfffff)|value) +} +func (o *SPI_Type) GetDMA_OUT_LINK_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0xfffff +} +func (o *SPI_Type) SetDMA_OUT_LINK_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetDMA_OUT_LINK_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SPI_Type) SetDMA_OUT_LINK_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetDMA_OUT_LINK_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetDMA_OUT_LINK_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetDMA_OUT_LINK_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetDMA_OUT_LINK_DMA_TX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetDMA_OUT_LINK_DMA_TX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x80000000) >> 31 +} + +// SPI.DMA_IN_LINK: SPI DMA RX link configuration +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0xfffff)|value) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0xfffff +} +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x100000)|value<<20) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x100000) >> 20 +} +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_START(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SPI_Type) SetDMA_IN_LINK_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetDMA_IN_LINK_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetDMA_IN_LINK_DMA_RX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetDMA_IN_LINK_DMA_RX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x80000000) >> 31 +} + +// SPI.DMA_INT_ENA: SPI DMA interrupt enable register +func (o *SPI_Type) SetDMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetDMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1 +} +func (o *SPI_Type) SetDMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetDMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetDMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_INT_ENA_IN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_INT_ENA_IN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_INT_ENA_IN_ERR_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_INT_ENA_IN_ERR_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_INT_ENA_IN_SUC_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_INT_ENA_IN_SUC_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_INT_ENA_OUT_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_INT_ENA_OUT_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_INT_ENA_OUT_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_INT_ENA_OUT_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI_Type) SetDMA_INT_ENA_INFIFO_FULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI_Type) GetDMA_INT_ENA_INFIFO_FULL_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SPI_Type) SetDMA_INT_ENA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetDMA_INT_ENA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetDMA_INT_ENA_SLV_CMD6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetDMA_INT_ENA_SLV_CMD6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetDMA_INT_ENA_SLV_CMD7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetDMA_INT_ENA_SLV_CMD7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetDMA_INT_ENA_SLV_CMD8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SPI_Type) GetDMA_INT_ENA_SLV_CMD8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SPI_Type) SetDMA_INT_ENA_SLV_CMD9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetDMA_INT_ENA_SLV_CMD9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetDMA_INT_ENA_SLV_CMDA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetDMA_INT_ENA_SLV_CMDA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8000) >> 15 +} + +// SPI.DMA_INT_RAW: SPI DMA interrupt raw register +func (o *SPI_Type) SetDMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetDMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW() uint32 { + return volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1 +} +func (o *SPI_Type) SetDMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetDMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetDMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_INT_RAW_IN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_INT_RAW_IN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_INT_RAW_IN_ERR_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_INT_RAW_IN_ERR_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_INT_RAW_IN_SUC_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_INT_RAW_IN_SUC_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_INT_RAW_OUT_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_INT_RAW_OUT_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_INT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_INT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI_Type) SetDMA_INT_RAW_INFIFO_FULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI_Type) GetDMA_INT_RAW_INFIFO_FULL_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SPI_Type) SetDMA_INT_RAW_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetDMA_INT_RAW_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetDMA_INT_RAW_SLV_CMD6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetDMA_INT_RAW_SLV_CMD6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetDMA_INT_RAW_SLV_CMD7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetDMA_INT_RAW_SLV_CMD7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetDMA_INT_RAW_SLV_CMD8_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SPI_Type) GetDMA_INT_RAW_SLV_CMD8_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SPI_Type) SetDMA_INT_RAW_SLV_CMD9_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetDMA_INT_RAW_SLV_CMD9_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetDMA_INT_RAW_SLV_CMDA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetDMA_INT_RAW_SLV_CMDA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8000) >> 15 +} + +// SPI.DMA_INT_ST: SPI DMA interrupt status register +func (o *SPI_Type) SetDMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetDMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1 +} +func (o *SPI_Type) SetDMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetDMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetDMA_INT_ST_INLINK_DSCR_ERROR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_INT_ST_INLINK_DSCR_ERROR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_INT_ST_IN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_INT_ST_IN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_INT_ST_IN_ERR_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_INT_ST_IN_ERR_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_INT_ST_IN_SUC_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_INT_ST_IN_SUC_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_INT_ST_OUT_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_INT_ST_OUT_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_INT_ST_OUT_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_INT_ST_OUT_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_INT_ST_OUT_TOTAL_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_INT_ST_OUT_TOTAL_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI_Type) SetDMA_INT_ST_INFIFO_FULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI_Type) GetDMA_INT_ST_INFIFO_FULL_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SPI_Type) SetDMA_INT_ST_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetDMA_INT_ST_OUTFIFO_EMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetDMA_INT_ST_SLV_CMD6_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetDMA_INT_ST_SLV_CMD6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetDMA_INT_ST_SLV_CMD7_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetDMA_INT_ST_SLV_CMD7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetDMA_INT_ST_SLV_CMD8_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SPI_Type) GetDMA_INT_ST_SLV_CMD8_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SPI_Type) SetDMA_INT_ST_SLV_CMD9_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetDMA_INT_ST_SLV_CMD9_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetDMA_INT_ST_SLV_CMDA_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetDMA_INT_ST_SLV_CMDA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8000) >> 15 +} + +// SPI.DMA_INT_CLR: SPI DMA interrupt clear register +func (o *SPI_Type) SetDMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI_Type) GetDMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1 +} +func (o *SPI_Type) SetDMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI_Type) GetDMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI_Type) SetDMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI_Type) GetDMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI_Type) SetDMA_INT_CLR_IN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI_Type) GetDMA_INT_CLR_IN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI_Type) SetDMA_INT_CLR_IN_ERR_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI_Type) GetDMA_INT_CLR_IN_ERR_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI_Type) SetDMA_INT_CLR_IN_SUC_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI_Type) GetDMA_INT_CLR_IN_SUC_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI_Type) SetDMA_INT_CLR_OUT_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI_Type) GetDMA_INT_CLR_OUT_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI_Type) SetDMA_INT_CLR_OUT_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetDMA_INT_CLR_OUT_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetDMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI_Type) GetDMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI_Type) SetDMA_INT_CLR_INFIFO_FULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI_Type) GetDMA_INT_CLR_INFIFO_FULL_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SPI_Type) SetDMA_INT_CLR_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI_Type) GetDMA_INT_CLR_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SPI_Type) SetDMA_INT_CLR_SLV_CMD6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SPI_Type) GetDMA_INT_CLR_SLV_CMD6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SPI_Type) SetDMA_INT_CLR_SLV_CMD7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI_Type) GetDMA_INT_CLR_SLV_CMD7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SPI_Type) SetDMA_INT_CLR_SLV_CMD8_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI_Type) GetDMA_INT_CLR_SLV_CMD8_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SPI_Type) SetDMA_INT_CLR_SLV_CMD9_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SPI_Type) GetDMA_INT_CLR_SLV_CMD9_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SPI_Type) SetDMA_INT_CLR_SLV_CMDA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetDMA_INT_CLR_SLV_CMDA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8000) >> 15 +} + +// SPI.IN_ERR_EOF_DES_ADDR: The latest SPI DMA RX descriptor address receiving error +func (o *SPI_Type) SetIN_ERR_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR.Reg, value) +} +func (o *SPI_Type) GetIN_ERR_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR.Reg) +} + +// SPI.IN_SUC_EOF_DES_ADDR: The latest SPI DMA eof RX descriptor address +func (o *SPI_Type) SetIN_SUC_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR.Reg, value) +} +func (o *SPI_Type) GetIN_SUC_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR.Reg) +} + +// SPI.INLINK_DSCR: Current SPI DMA RX descriptor pointer +func (o *SPI_Type) SetINLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR.Reg, value) +} +func (o *SPI_Type) GetINLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR.Reg) +} + +// SPI.INLINK_DSCR_BF0: Next SPI DMA RX descriptor pointer +func (o *SPI_Type) SetINLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR_BF0.Reg, value) +} +func (o *SPI_Type) GetINLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR_BF0.Reg) +} + +// SPI.INLINK_DSCR_BF1: Current SPI DMA RX buffer pointer +func (o *SPI_Type) SetINLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.INLINK_DSCR_BF1.Reg, value) +} +func (o *SPI_Type) GetINLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.INLINK_DSCR_BF1.Reg) +} + +// SPI.OUT_EOF_BFR_DES_ADDR: The latest SPI DMA eof TX buffer address +func (o *SPI_Type) SetOUT_EOF_BFR_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR.Reg, value) +} +func (o *SPI_Type) GetOUT_EOF_BFR_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR.Reg) +} + +// SPI.OUT_EOF_DES_ADDR: The latest SPI DMA eof TX descriptor address +func (o *SPI_Type) SetOUT_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR.Reg, value) +} +func (o *SPI_Type) GetOUT_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR.Reg) +} + +// SPI.OUTLINK_DSCR: Current SPI DMA TX descriptor pointer +func (o *SPI_Type) SetOUTLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR.Reg, value) +} +func (o *SPI_Type) GetOUTLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR.Reg) +} + +// SPI.OUTLINK_DSCR_BF0: Next SPI DMA TX descriptor pointer +func (o *SPI_Type) SetOUTLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR_BF0.Reg, value) +} +func (o *SPI_Type) GetOUTLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR_BF0.Reg) +} + +// SPI.OUTLINK_DSCR_BF1: Current SPI DMA TX buffer pointer +func (o *SPI_Type) SetOUTLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.OUTLINK_DSCR_BF1.Reg, value) +} +func (o *SPI_Type) GetOUTLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.OUTLINK_DSCR_BF1.Reg) +} + +// SPI.DMA_OUTSTATUS: SPI DMA TX status +func (o *SPI_Type) SetDMA_OUTSTATUS_DMA_OUTDSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_OUTSTATUS.Reg, volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg)&^(0x3ffff)|value) +} +func (o *SPI_Type) GetDMA_OUTSTATUS_DMA_OUTDSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg) & 0x3ffff +} +func (o *SPI_Type) SetDMA_OUTSTATUS_DMA_OUTDSCR_STATE(value uint32) { + volatile.StoreUint32(&o.DMA_OUTSTATUS.Reg, volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg)&^(0xc0000)|value<<18) +} +func (o *SPI_Type) GetDMA_OUTSTATUS_DMA_OUTDSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg) & 0xc0000) >> 18 +} +func (o *SPI_Type) SetDMA_OUTSTATUS_DMA_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.DMA_OUTSTATUS.Reg, volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg)&^(0x700000)|value<<20) +} +func (o *SPI_Type) GetDMA_OUTSTATUS_DMA_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg) & 0x700000) >> 20 +} +func (o *SPI_Type) SetDMA_OUTSTATUS_DMA_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.DMA_OUTSTATUS.Reg, volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg)&^(0x3f800000)|value<<23) +} +func (o *SPI_Type) GetDMA_OUTSTATUS_DMA_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg) & 0x3f800000) >> 23 +} +func (o *SPI_Type) SetDMA_OUTSTATUS_DMA_OUTFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_OUTSTATUS.Reg, volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetDMA_OUTSTATUS_DMA_OUTFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetDMA_OUTSTATUS_DMA_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_OUTSTATUS.Reg, volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetDMA_OUTSTATUS_DMA_OUTFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.DMA_OUTSTATUS.Reg) & 0x80000000) >> 31 +} + +// SPI.DMA_INSTATUS: SPI DMA RX status +func (o *SPI_Type) SetDMA_INSTATUS_DMA_INDSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_INSTATUS.Reg, volatile.LoadUint32(&o.DMA_INSTATUS.Reg)&^(0x3ffff)|value) +} +func (o *SPI_Type) GetDMA_INSTATUS_DMA_INDSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_INSTATUS.Reg) & 0x3ffff +} +func (o *SPI_Type) SetDMA_INSTATUS_DMA_INDSCR_STATE(value uint32) { + volatile.StoreUint32(&o.DMA_INSTATUS.Reg, volatile.LoadUint32(&o.DMA_INSTATUS.Reg)&^(0xc0000)|value<<18) +} +func (o *SPI_Type) GetDMA_INSTATUS_DMA_INDSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.DMA_INSTATUS.Reg) & 0xc0000) >> 18 +} +func (o *SPI_Type) SetDMA_INSTATUS_DMA_IN_STATE(value uint32) { + volatile.StoreUint32(&o.DMA_INSTATUS.Reg, volatile.LoadUint32(&o.DMA_INSTATUS.Reg)&^(0x700000)|value<<20) +} +func (o *SPI_Type) GetDMA_INSTATUS_DMA_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.DMA_INSTATUS.Reg) & 0x700000) >> 20 +} +func (o *SPI_Type) SetDMA_INSTATUS_DMA_INFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.DMA_INSTATUS.Reg, volatile.LoadUint32(&o.DMA_INSTATUS.Reg)&^(0x3f800000)|value<<23) +} +func (o *SPI_Type) GetDMA_INSTATUS_DMA_INFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.DMA_INSTATUS.Reg) & 0x3f800000) >> 23 +} +func (o *SPI_Type) SetDMA_INSTATUS_DMA_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_INSTATUS.Reg, volatile.LoadUint32(&o.DMA_INSTATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI_Type) GetDMA_INSTATUS_DMA_INFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.DMA_INSTATUS.Reg) & 0x40000000) >> 30 +} +func (o *SPI_Type) SetDMA_INSTATUS_DMA_INFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_INSTATUS.Reg, volatile.LoadUint32(&o.DMA_INSTATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetDMA_INSTATUS_DMA_INFIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.DMA_INSTATUS.Reg) & 0x80000000) >> 31 +} + +// SPI.W0: Data buffer 0 +func (o *SPI_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI.W1: Data buffer 1 +func (o *SPI_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI.W2: Data buffer 2 +func (o *SPI_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI.W3: Data buffer 3 +func (o *SPI_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI.W4: Data buffer 4 +func (o *SPI_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI.W5: Data buffer 5 +func (o *SPI_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI.W6: Data buffer 6 +func (o *SPI_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI.W7: Data buffer 7 +func (o *SPI_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI.W8: Data buffer 8 +func (o *SPI_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI.W9: Data buffer 9 +func (o *SPI_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI.W10: Data buffer 10 +func (o *SPI_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI.W11: Data buffer 11 +func (o *SPI_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI.W12: Data buffer 12 +func (o *SPI_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI.W13: Data buffer 13 +func (o *SPI_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI.W14: Data buffer 14 +func (o *SPI_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI.W15: Data buffer 15 +func (o *SPI_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI.W16: Data buffer 16 +func (o *SPI_Type) SetW16(value uint32) { + volatile.StoreUint32(&o.W16.Reg, value) +} +func (o *SPI_Type) GetW16() uint32 { + return volatile.LoadUint32(&o.W16.Reg) +} + +// SPI.W17: Data buffer 17 +func (o *SPI_Type) SetW17(value uint32) { + volatile.StoreUint32(&o.W17.Reg, value) +} +func (o *SPI_Type) GetW17() uint32 { + return volatile.LoadUint32(&o.W17.Reg) +} + +// SPI.DIN_MODE: SPI input delay mode configuration +func (o *SPI_Type) SetDIN_MODE_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x7)|value) +} +func (o *SPI_Type) GetDIN_MODE_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x7 +} +func (o *SPI_Type) SetDIN_MODE_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI_Type) GetDIN_MODE_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI_Type) SetDIN_MODE_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI_Type) GetDIN_MODE_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI_Type) SetDIN_MODE_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI_Type) GetDIN_MODE_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI_Type) SetDIN_MODE_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI_Type) GetDIN_MODE_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI_Type) SetDIN_MODE_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI_Type) GetDIN_MODE_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI_Type) SetDIN_MODE_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI_Type) GetDIN_MODE_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI_Type) SetDIN_MODE_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI_Type) GetDIN_MODE_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI_Type) SetDIN_MODE_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI_Type) GetDIN_MODE_TIMING_CLK_ENA() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x1000000) >> 24 +} + +// SPI.DIN_NUM: SPI input delay number configuration +func (o *SPI_Type) SetDIN_NUM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI_Type) GetDIN_NUM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3 +} +func (o *SPI_Type) SetDIN_NUM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI_Type) GetDIN_NUM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI_Type) SetDIN_NUM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI_Type) GetDIN_NUM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI_Type) SetDIN_NUM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI_Type) GetDIN_NUM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI_Type) SetDIN_NUM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI_Type) GetDIN_NUM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI_Type) SetDIN_NUM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI_Type) GetDIN_NUM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI_Type) SetDIN_NUM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI_Type) GetDIN_NUM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI_Type) SetDIN_NUM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI_Type) GetDIN_NUM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc000) >> 14 +} + +// SPI.DOUT_MODE: SPI output delay mode configuration +func (o *SPI_Type) SetDOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x7)|value) +} +func (o *SPI_Type) GetDOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x7 +} +func (o *SPI_Type) SetDOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI_Type) GetDOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI_Type) SetDOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI_Type) GetDOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI_Type) SetDOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI_Type) GetDOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI_Type) SetDOUT_MODE_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI_Type) GetDOUT_MODE_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI_Type) SetDOUT_MODE_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI_Type) GetDOUT_MODE_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI_Type) SetDOUT_MODE_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI_Type) GetDOUT_MODE_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI_Type) SetDOUT_MODE_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI_Type) GetDOUT_MODE_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0xe00000) >> 21 +} + +// SPI.DOUT_NUM: SPI output delay number configuration +func (o *SPI_Type) SetDOUT_NUM_DOUT0_NUM(value uint32) { + volatile.StoreUint32(&o.DOUT_NUM.Reg, volatile.LoadUint32(&o.DOUT_NUM.Reg)&^(0x3)|value) +} +func (o *SPI_Type) GetDOUT_NUM_DOUT0_NUM() uint32 { + return volatile.LoadUint32(&o.DOUT_NUM.Reg) & 0x3 +} +func (o *SPI_Type) SetDOUT_NUM_DOUT1_NUM(value uint32) { + volatile.StoreUint32(&o.DOUT_NUM.Reg, volatile.LoadUint32(&o.DOUT_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI_Type) GetDOUT_NUM_DOUT1_NUM() uint32 { + return (volatile.LoadUint32(&o.DOUT_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI_Type) SetDOUT_NUM_DOUT2_NUM(value uint32) { + volatile.StoreUint32(&o.DOUT_NUM.Reg, volatile.LoadUint32(&o.DOUT_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI_Type) GetDOUT_NUM_DOUT2_NUM() uint32 { + return (volatile.LoadUint32(&o.DOUT_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI_Type) SetDOUT_NUM_DOUT3_NUM(value uint32) { + volatile.StoreUint32(&o.DOUT_NUM.Reg, volatile.LoadUint32(&o.DOUT_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI_Type) GetDOUT_NUM_DOUT3_NUM() uint32 { + return (volatile.LoadUint32(&o.DOUT_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI_Type) SetDOUT_NUM_DOUT4_NUM(value uint32) { + volatile.StoreUint32(&o.DOUT_NUM.Reg, volatile.LoadUint32(&o.DOUT_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI_Type) GetDOUT_NUM_DOUT4_NUM() uint32 { + return (volatile.LoadUint32(&o.DOUT_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI_Type) SetDOUT_NUM_DOUT5_NUM(value uint32) { + volatile.StoreUint32(&o.DOUT_NUM.Reg, volatile.LoadUint32(&o.DOUT_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI_Type) GetDOUT_NUM_DOUT5_NUM() uint32 { + return (volatile.LoadUint32(&o.DOUT_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI_Type) SetDOUT_NUM_DOUT6_NUM(value uint32) { + volatile.StoreUint32(&o.DOUT_NUM.Reg, volatile.LoadUint32(&o.DOUT_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI_Type) GetDOUT_NUM_DOUT6_NUM() uint32 { + return (volatile.LoadUint32(&o.DOUT_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI_Type) SetDOUT_NUM_DOUT7_NUM(value uint32) { + volatile.StoreUint32(&o.DOUT_NUM.Reg, volatile.LoadUint32(&o.DOUT_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI_Type) GetDOUT_NUM_DOUT7_NUM() uint32 { + return (volatile.LoadUint32(&o.DOUT_NUM.Reg) & 0xc000) >> 14 +} + +// SPI.LCD_CTRL: LCD frame control register +func (o *SPI_Type) SetLCD_CTRL_LCD_HB_FRONT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x7ff)|value) +} +func (o *SPI_Type) GetLCD_CTRL_LCD_HB_FRONT() uint32 { + return volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x7ff +} +func (o *SPI_Type) SetLCD_CTRL_LCD_VA_HEIGHT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x1ff800)|value<<11) +} +func (o *SPI_Type) GetLCD_CTRL_LCD_VA_HEIGHT() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x1ff800) >> 11 +} +func (o *SPI_Type) SetLCD_CTRL_LCD_VT_HEIGHT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x7fe00000)|value<<21) +} +func (o *SPI_Type) GetLCD_CTRL_LCD_VT_HEIGHT() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x7fe00000) >> 21 +} +func (o *SPI_Type) SetLCD_CTRL_LCD_MODE_EN(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI_Type) GetLCD_CTRL_LCD_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x80000000) >> 31 +} + +// SPI.LCD_CTRL1: LCD frame control1 register +func (o *SPI_Type) SetLCD_CTRL1_LCD_VB_FRONT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xff)|value) +} +func (o *SPI_Type) GetLCD_CTRL1_LCD_VB_FRONT() uint32 { + return volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xff +} +func (o *SPI_Type) SetLCD_CTRL1_LCD_HA_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xfff00)|value<<8) +} +func (o *SPI_Type) GetLCD_CTRL1_LCD_HA_WIDTH() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xfff00) >> 8 +} +func (o *SPI_Type) SetLCD_CTRL1_LCD_HT_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xfff00000)|value<<20) +} +func (o *SPI_Type) GetLCD_CTRL1_LCD_HT_WIDTH() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xfff00000) >> 20 +} + +// SPI.LCD_CTRL2: LCD frame control2 register +func (o *SPI_Type) SetLCD_CTRL2_LCD_VSYNC_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x7f)|value) +} +func (o *SPI_Type) GetLCD_CTRL2_LCD_VSYNC_WIDTH() uint32 { + return volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x7f +} +func (o *SPI_Type) SetLCD_CTRL2_VSYNC_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x80)|value<<7) +} +func (o *SPI_Type) GetLCD_CTRL2_VSYNC_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x80) >> 7 +} +func (o *SPI_Type) SetLCD_CTRL2_LCD_HSYNC_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x7f0000)|value<<16) +} +func (o *SPI_Type) GetLCD_CTRL2_LCD_HSYNC_WIDTH() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x7f0000) >> 16 +} +func (o *SPI_Type) SetLCD_CTRL2_HSYNC_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x800000)|value<<23) +} +func (o *SPI_Type) GetLCD_CTRL2_HSYNC_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x800000) >> 23 +} +func (o *SPI_Type) SetLCD_CTRL2_LCD_HSYNC_POSITION(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI_Type) GetLCD_CTRL2_LCD_HSYNC_POSITION() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0xff000000) >> 24 +} + +// SPI.LCD_D_MODE: LCD delay number +func (o *SPI_Type) SetLCD_D_MODE_D_DQS_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_D_MODE.Reg, volatile.LoadUint32(&o.LCD_D_MODE.Reg)&^(0x7)|value) +} +func (o *SPI_Type) GetLCD_D_MODE_D_DQS_MODE() uint32 { + return volatile.LoadUint32(&o.LCD_D_MODE.Reg) & 0x7 +} +func (o *SPI_Type) SetLCD_D_MODE_D_CD_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_D_MODE.Reg, volatile.LoadUint32(&o.LCD_D_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI_Type) GetLCD_D_MODE_D_CD_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_D_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI_Type) SetLCD_D_MODE_D_DE_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_D_MODE.Reg, volatile.LoadUint32(&o.LCD_D_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI_Type) GetLCD_D_MODE_D_DE_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_D_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI_Type) SetLCD_D_MODE_D_HSYNC_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_D_MODE.Reg, volatile.LoadUint32(&o.LCD_D_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI_Type) GetLCD_D_MODE_D_HSYNC_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_D_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI_Type) SetLCD_D_MODE_D_VSYNC_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_D_MODE.Reg, volatile.LoadUint32(&o.LCD_D_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI_Type) GetLCD_D_MODE_D_VSYNC_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_D_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI_Type) SetLCD_D_MODE_DE_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.LCD_D_MODE.Reg, volatile.LoadUint32(&o.LCD_D_MODE.Reg)&^(0x8000)|value<<15) +} +func (o *SPI_Type) GetLCD_D_MODE_DE_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.LCD_D_MODE.Reg) & 0x8000) >> 15 +} +func (o *SPI_Type) SetLCD_D_MODE_HS_BLANK_EN(value uint32) { + volatile.StoreUint32(&o.LCD_D_MODE.Reg, volatile.LoadUint32(&o.LCD_D_MODE.Reg)&^(0x10000)|value<<16) +} +func (o *SPI_Type) GetLCD_D_MODE_HS_BLANK_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_D_MODE.Reg) & 0x10000) >> 16 +} + +// SPI.LCD_D_NUM: LCD delay mode +func (o *SPI_Type) SetLCD_D_NUM_D_DQS_NUM(value uint32) { + volatile.StoreUint32(&o.LCD_D_NUM.Reg, volatile.LoadUint32(&o.LCD_D_NUM.Reg)&^(0x3)|value) +} +func (o *SPI_Type) GetLCD_D_NUM_D_DQS_NUM() uint32 { + return volatile.LoadUint32(&o.LCD_D_NUM.Reg) & 0x3 +} +func (o *SPI_Type) SetLCD_D_NUM_D_CD_NUM(value uint32) { + volatile.StoreUint32(&o.LCD_D_NUM.Reg, volatile.LoadUint32(&o.LCD_D_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI_Type) GetLCD_D_NUM_D_CD_NUM() uint32 { + return (volatile.LoadUint32(&o.LCD_D_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI_Type) SetLCD_D_NUM_D_DE_NUM(value uint32) { + volatile.StoreUint32(&o.LCD_D_NUM.Reg, volatile.LoadUint32(&o.LCD_D_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI_Type) GetLCD_D_NUM_D_DE_NUM() uint32 { + return (volatile.LoadUint32(&o.LCD_D_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI_Type) SetLCD_D_NUM_D_HSYNC_NUM(value uint32) { + volatile.StoreUint32(&o.LCD_D_NUM.Reg, volatile.LoadUint32(&o.LCD_D_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI_Type) GetLCD_D_NUM_D_HSYNC_NUM() uint32 { + return (volatile.LoadUint32(&o.LCD_D_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI_Type) SetLCD_D_NUM_D_VSYNC_NUM(value uint32) { + volatile.StoreUint32(&o.LCD_D_NUM.Reg, volatile.LoadUint32(&o.LCD_D_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI_Type) GetLCD_D_NUM_D_VSYNC_NUM() uint32 { + return (volatile.LoadUint32(&o.LCD_D_NUM.Reg) & 0x300) >> 8 +} + +// SPI.REG_DATE: SPI version control +func (o *SPI_Type) SetREG_DATE_DATE(value uint32) { + volatile.StoreUint32(&o.REG_DATE.Reg, volatile.LoadUint32(&o.REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI_Type) GetREG_DATE_DATE() uint32 { + return volatile.LoadUint32(&o.REG_DATE.Reg) & 0xfffffff +} + +// SYSCON Peripheral +type SYSCON_Type struct { + SYSCLK_CONF volatile.Register32 // 0x0 + TICK_CONF volatile.Register32 // 0x4 + CLK_OUT_EN volatile.Register32 // 0x8 + HOST_INF_SEL volatile.Register32 // 0xC + EXT_MEM_PMS_LOCK volatile.Register32 // 0x10 + FLASH_ACE0_ATTR volatile.Register32 // 0x14 + FLASH_ACE1_ATTR volatile.Register32 // 0x18 + FLASH_ACE2_ATTR volatile.Register32 // 0x1C + FLASH_ACE3_ATTR volatile.Register32 // 0x20 + FLASH_ACE0_ADDR volatile.Register32 // 0x24 + FLASH_ACE1_ADDR volatile.Register32 // 0x28 + FLASH_ACE2_ADDR volatile.Register32 // 0x2C + FLASH_ACE3_ADDR volatile.Register32 // 0x30 + FLASH_ACE0_SIZE volatile.Register32 // 0x34 + FLASH_ACE1_SIZE volatile.Register32 // 0x38 + FLASH_ACE2_SIZE volatile.Register32 // 0x3C + FLASH_ACE3_SIZE volatile.Register32 // 0x40 + SRAM_ACE0_ATTR volatile.Register32 // 0x44 + SRAM_ACE1_ATTR volatile.Register32 // 0x48 + SRAM_ACE2_ATTR volatile.Register32 // 0x4C + SRAM_ACE3_ATTR volatile.Register32 // 0x50 + SRAM_ACE0_ADDR volatile.Register32 // 0x54 + SRAM_ACE1_ADDR volatile.Register32 // 0x58 + SRAM_ACE2_ADDR volatile.Register32 // 0x5C + SRAM_ACE3_ADDR volatile.Register32 // 0x60 + SRAM_ACE0_SIZE volatile.Register32 // 0x64 + SRAM_ACE1_SIZE volatile.Register32 // 0x68 + SRAM_ACE2_SIZE volatile.Register32 // 0x6C + SRAM_ACE3_SIZE volatile.Register32 // 0x70 + SPI_MEM_PMS_CTRL volatile.Register32 // 0x74 + SPI_MEM_REJECT_ADDR volatile.Register32 // 0x78 + SDIO_CTRL volatile.Register32 // 0x7C + REDCY_SIG0 volatile.Register32 // 0x80 + REDCY_SIG1 volatile.Register32 // 0x84 + WIFI_BB_CFG volatile.Register32 // 0x88 + WIFI_BB_CFG_2 volatile.Register32 // 0x8C + WIFI_CLK_EN volatile.Register32 // 0x90 + WIFI_RST_EN volatile.Register32 // 0x94 + FRONT_END_MEM_PD volatile.Register32 // 0x98 + _ [864]byte + DATE volatile.Register32 // 0x3FC +} + +// SYSCON.SYSCLK_CONF +func (o *SYSCON_Type) SetSYSCLK_CONF_CLK_320M_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *SYSCON_Type) GetSYSCLK_CONF_CLK_320M_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x400) >> 10 +} +func (o *SYSCON_Type) SetSYSCLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x800)|value<<11) +} +func (o *SYSCON_Type) GetSYSCLK_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x800) >> 11 +} +func (o *SYSCON_Type) SetSYSCLK_CONF_RST_TICK_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *SYSCON_Type) GetSYSCLK_CONF_RST_TICK_CNT() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x1000) >> 12 +} + +// SYSCON.TICK_CONF +func (o *SYSCON_Type) SetTICK_CONF_XTAL_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0xff)|value) +} +func (o *SYSCON_Type) GetTICK_CONF_XTAL_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.TICK_CONF.Reg) & 0xff +} +func (o *SYSCON_Type) SetTICK_CONF_CK8M_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *SYSCON_Type) GetTICK_CONF_CK8M_TICK_NUM() uint32 { + return (volatile.LoadUint32(&o.TICK_CONF.Reg) & 0xff00) >> 8 +} +func (o *SYSCON_Type) SetTICK_CONF_TICK_ENABLE(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *SYSCON_Type) GetTICK_CONF_TICK_ENABLE() uint32 { + return (volatile.LoadUint32(&o.TICK_CONF.Reg) & 0x10000) >> 16 +} + +// SYSCON.CLK_OUT_EN +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK20_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x1)|value) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK20_OEN() uint32 { + return volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x1 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK22_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x2)|value<<1) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK22_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x2) >> 1 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK44_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x4)|value<<2) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK44_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x4) >> 2 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x8)|value<<3) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x8) >> 3 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK80_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x10)|value<<4) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK80_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x10) >> 4 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK160_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x20)|value<<5) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK160_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x20) >> 5 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK_320M_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x40)|value<<6) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK_320M_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x40) >> 6 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK_ADC_INF_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x80)|value<<7) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK_ADC_INF_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x80) >> 7 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK_DAC_CPU_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x100)|value<<8) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK_DAC_CPU_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x100) >> 8 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK40X_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x200)|value<<9) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK40X_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x200) >> 9 +} +func (o *SYSCON_Type) SetCLK_OUT_EN_CLK_XTAL_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x400)|value<<10) +} +func (o *SYSCON_Type) GetCLK_OUT_EN_CLK_XTAL_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x400) >> 10 +} + +// SYSCON.HOST_INF_SEL +func (o *SYSCON_Type) SetHOST_INF_SEL_PERI_IO_SWAP(value uint32) { + volatile.StoreUint32(&o.HOST_INF_SEL.Reg, volatile.LoadUint32(&o.HOST_INF_SEL.Reg)&^(0xff)|value) +} +func (o *SYSCON_Type) GetHOST_INF_SEL_PERI_IO_SWAP() uint32 { + return volatile.LoadUint32(&o.HOST_INF_SEL.Reg) & 0xff +} + +// SYSCON.EXT_MEM_PMS_LOCK +func (o *SYSCON_Type) SetEXT_MEM_PMS_LOCK(value uint32) { + volatile.StoreUint32(&o.EXT_MEM_PMS_LOCK.Reg, volatile.LoadUint32(&o.EXT_MEM_PMS_LOCK.Reg)&^(0x1)|value) +} +func (o *SYSCON_Type) GetEXT_MEM_PMS_LOCK() uint32 { + return volatile.LoadUint32(&o.EXT_MEM_PMS_LOCK.Reg) & 0x1 +} + +// SYSCON.FLASH_ACE0_ATTR +func (o *SYSCON_Type) SetFLASH_ACE0_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE0_ATTR.Reg)&^(0x7)|value) +} +func (o *SYSCON_Type) GetFLASH_ACE0_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_ATTR.Reg) & 0x7 +} + +// SYSCON.FLASH_ACE1_ATTR +func (o *SYSCON_Type) SetFLASH_ACE1_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE1_ATTR.Reg)&^(0x7)|value) +} +func (o *SYSCON_Type) GetFLASH_ACE1_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_ATTR.Reg) & 0x7 +} + +// SYSCON.FLASH_ACE2_ATTR +func (o *SYSCON_Type) SetFLASH_ACE2_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE2_ATTR.Reg)&^(0x7)|value) +} +func (o *SYSCON_Type) GetFLASH_ACE2_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_ATTR.Reg) & 0x7 +} + +// SYSCON.FLASH_ACE3_ATTR +func (o *SYSCON_Type) SetFLASH_ACE3_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE3_ATTR.Reg)&^(0x7)|value) +} +func (o *SYSCON_Type) GetFLASH_ACE3_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_ATTR.Reg) & 0x7 +} + +// SYSCON.FLASH_ACE0_ADDR +func (o *SYSCON_Type) SetFLASH_ACE0_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_ADDR.Reg, value) +} +func (o *SYSCON_Type) GetFLASH_ACE0_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_ADDR.Reg) +} + +// SYSCON.FLASH_ACE1_ADDR +func (o *SYSCON_Type) SetFLASH_ACE1_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_ADDR.Reg, value) +} +func (o *SYSCON_Type) GetFLASH_ACE1_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_ADDR.Reg) +} + +// SYSCON.FLASH_ACE2_ADDR +func (o *SYSCON_Type) SetFLASH_ACE2_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_ADDR.Reg, value) +} +func (o *SYSCON_Type) GetFLASH_ACE2_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_ADDR.Reg) +} + +// SYSCON.FLASH_ACE3_ADDR +func (o *SYSCON_Type) SetFLASH_ACE3_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_ADDR.Reg, value) +} +func (o *SYSCON_Type) GetFLASH_ACE3_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_ADDR.Reg) +} + +// SYSCON.FLASH_ACE0_SIZE +func (o *SYSCON_Type) SetFLASH_ACE0_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE0_SIZE.Reg)&^(0xffff)|value) +} +func (o *SYSCON_Type) GetFLASH_ACE0_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_SIZE.Reg) & 0xffff +} + +// SYSCON.FLASH_ACE1_SIZE +func (o *SYSCON_Type) SetFLASH_ACE1_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE1_SIZE.Reg)&^(0xffff)|value) +} +func (o *SYSCON_Type) GetFLASH_ACE1_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_SIZE.Reg) & 0xffff +} + +// SYSCON.FLASH_ACE2_SIZE +func (o *SYSCON_Type) SetFLASH_ACE2_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE2_SIZE.Reg)&^(0xffff)|value) +} +func (o *SYSCON_Type) GetFLASH_ACE2_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_SIZE.Reg) & 0xffff +} + +// SYSCON.FLASH_ACE3_SIZE +func (o *SYSCON_Type) SetFLASH_ACE3_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE3_SIZE.Reg)&^(0xffff)|value) +} +func (o *SYSCON_Type) GetFLASH_ACE3_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_SIZE.Reg) & 0xffff +} + +// SYSCON.SRAM_ACE0_ATTR +func (o *SYSCON_Type) SetSRAM_ACE0_ATTR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE0_ATTR.Reg, volatile.LoadUint32(&o.SRAM_ACE0_ATTR.Reg)&^(0x7)|value) +} +func (o *SYSCON_Type) GetSRAM_ACE0_ATTR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE0_ATTR.Reg) & 0x7 +} + +// SYSCON.SRAM_ACE1_ATTR +func (o *SYSCON_Type) SetSRAM_ACE1_ATTR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE1_ATTR.Reg, volatile.LoadUint32(&o.SRAM_ACE1_ATTR.Reg)&^(0x7)|value) +} +func (o *SYSCON_Type) GetSRAM_ACE1_ATTR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE1_ATTR.Reg) & 0x7 +} + +// SYSCON.SRAM_ACE2_ATTR +func (o *SYSCON_Type) SetSRAM_ACE2_ATTR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE2_ATTR.Reg, volatile.LoadUint32(&o.SRAM_ACE2_ATTR.Reg)&^(0x7)|value) +} +func (o *SYSCON_Type) GetSRAM_ACE2_ATTR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE2_ATTR.Reg) & 0x7 +} + +// SYSCON.SRAM_ACE3_ATTR +func (o *SYSCON_Type) SetSRAM_ACE3_ATTR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE3_ATTR.Reg, volatile.LoadUint32(&o.SRAM_ACE3_ATTR.Reg)&^(0x7)|value) +} +func (o *SYSCON_Type) GetSRAM_ACE3_ATTR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE3_ATTR.Reg) & 0x7 +} + +// SYSCON.SRAM_ACE0_ADDR +func (o *SYSCON_Type) SetSRAM_ACE0_ADDR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE0_ADDR.Reg, value) +} +func (o *SYSCON_Type) GetSRAM_ACE0_ADDR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE0_ADDR.Reg) +} + +// SYSCON.SRAM_ACE1_ADDR +func (o *SYSCON_Type) SetSRAM_ACE1_ADDR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE1_ADDR.Reg, value) +} +func (o *SYSCON_Type) GetSRAM_ACE1_ADDR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE1_ADDR.Reg) +} + +// SYSCON.SRAM_ACE2_ADDR +func (o *SYSCON_Type) SetSRAM_ACE2_ADDR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE2_ADDR.Reg, value) +} +func (o *SYSCON_Type) GetSRAM_ACE2_ADDR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE2_ADDR.Reg) +} + +// SYSCON.SRAM_ACE3_ADDR +func (o *SYSCON_Type) SetSRAM_ACE3_ADDR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE3_ADDR.Reg, value) +} +func (o *SYSCON_Type) GetSRAM_ACE3_ADDR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE3_ADDR.Reg) +} + +// SYSCON.SRAM_ACE0_SIZE +func (o *SYSCON_Type) SetSRAM_ACE0_SIZE(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE0_SIZE.Reg, volatile.LoadUint32(&o.SRAM_ACE0_SIZE.Reg)&^(0xffff)|value) +} +func (o *SYSCON_Type) GetSRAM_ACE0_SIZE() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE0_SIZE.Reg) & 0xffff +} + +// SYSCON.SRAM_ACE1_SIZE +func (o *SYSCON_Type) SetSRAM_ACE1_SIZE(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE1_SIZE.Reg, volatile.LoadUint32(&o.SRAM_ACE1_SIZE.Reg)&^(0xffff)|value) +} +func (o *SYSCON_Type) GetSRAM_ACE1_SIZE() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE1_SIZE.Reg) & 0xffff +} + +// SYSCON.SRAM_ACE2_SIZE +func (o *SYSCON_Type) SetSRAM_ACE2_SIZE(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE2_SIZE.Reg, volatile.LoadUint32(&o.SRAM_ACE2_SIZE.Reg)&^(0xffff)|value) +} +func (o *SYSCON_Type) GetSRAM_ACE2_SIZE() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE2_SIZE.Reg) & 0xffff +} + +// SYSCON.SRAM_ACE3_SIZE +func (o *SYSCON_Type) SetSRAM_ACE3_SIZE(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE3_SIZE.Reg, volatile.LoadUint32(&o.SRAM_ACE3_SIZE.Reg)&^(0xffff)|value) +} +func (o *SYSCON_Type) GetSRAM_ACE3_SIZE() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE3_SIZE.Reg) & 0xffff +} + +// SYSCON.SPI_MEM_PMS_CTRL +func (o *SYSCON_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSCON_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x1 +} +func (o *SYSCON_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSCON_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x2) >> 1 +} +func (o *SYSCON_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x7c)|value<<2) +} +func (o *SYSCON_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x7c) >> 2 +} + +// SYSCON.SPI_MEM_REJECT_ADDR +func (o *SYSCON_Type) SetSPI_MEM_REJECT_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REJECT_ADDR.Reg, value) +} +func (o *SYSCON_Type) GetSPI_MEM_REJECT_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REJECT_ADDR.Reg) +} + +// SYSCON.SDIO_CTRL +func (o *SYSCON_Type) SetSDIO_CTRL_SDIO_WIN_ACCESS_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_CTRL.Reg, volatile.LoadUint32(&o.SDIO_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSCON_Type) GetSDIO_CTRL_SDIO_WIN_ACCESS_EN() uint32 { + return volatile.LoadUint32(&o.SDIO_CTRL.Reg) & 0x1 +} + +// SYSCON.REDCY_SIG0 +func (o *SYSCON_Type) SetREDCY_SIG0(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG0.Reg, volatile.LoadUint32(&o.REDCY_SIG0.Reg)&^(0x7fffffff)|value) +} +func (o *SYSCON_Type) GetREDCY_SIG0() uint32 { + return volatile.LoadUint32(&o.REDCY_SIG0.Reg) & 0x7fffffff +} +func (o *SYSCON_Type) SetREDCY_SIG0_REDCY_ANDOR(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG0.Reg, volatile.LoadUint32(&o.REDCY_SIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSCON_Type) GetREDCY_SIG0_REDCY_ANDOR() uint32 { + return (volatile.LoadUint32(&o.REDCY_SIG0.Reg) & 0x80000000) >> 31 +} + +// SYSCON.REDCY_SIG1 +func (o *SYSCON_Type) SetREDCY_SIG1(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG1.Reg, volatile.LoadUint32(&o.REDCY_SIG1.Reg)&^(0x7fffffff)|value) +} +func (o *SYSCON_Type) GetREDCY_SIG1() uint32 { + return volatile.LoadUint32(&o.REDCY_SIG1.Reg) & 0x7fffffff +} +func (o *SYSCON_Type) SetREDCY_SIG1_REDCY_NANDOR(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG1.Reg, volatile.LoadUint32(&o.REDCY_SIG1.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSCON_Type) GetREDCY_SIG1_REDCY_NANDOR() uint32 { + return (volatile.LoadUint32(&o.REDCY_SIG1.Reg) & 0x80000000) >> 31 +} + +// SYSCON.WIFI_BB_CFG +func (o *SYSCON_Type) SetWIFI_BB_CFG(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG.Reg, value) +} +func (o *SYSCON_Type) GetWIFI_BB_CFG() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG.Reg) +} + +// SYSCON.WIFI_BB_CFG_2 +func (o *SYSCON_Type) SetWIFI_BB_CFG_2(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG_2.Reg, value) +} +func (o *SYSCON_Type) GetWIFI_BB_CFG_2() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG_2.Reg) +} + +// SYSCON.WIFI_CLK_EN +func (o *SYSCON_Type) SetWIFI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_CLK_EN.Reg, value) +} +func (o *SYSCON_Type) GetWIFI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_CLK_EN.Reg) +} + +// SYSCON.WIFI_RST_EN +func (o *SYSCON_Type) SetWIFI_RST_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_RST_EN.Reg, value) +} +func (o *SYSCON_Type) GetWIFI_RST_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_RST_EN.Reg) +} + +// SYSCON.FRONT_END_MEM_PD +func (o *SYSCON_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x1)|value) +} +func (o *SYSCON_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU() uint32 { + return volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x1 +} +func (o *SYSCON_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x2)|value<<1) +} +func (o *SYSCON_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x2) >> 1 +} +func (o *SYSCON_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x4)|value<<2) +} +func (o *SYSCON_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x4) >> 2 +} +func (o *SYSCON_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x8)|value<<3) +} +func (o *SYSCON_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x8) >> 3 +} +func (o *SYSCON_Type) SetFRONT_END_MEM_PD_DC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x10)|value<<4) +} +func (o *SYSCON_Type) GetFRONT_END_MEM_PD_DC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x10) >> 4 +} +func (o *SYSCON_Type) SetFRONT_END_MEM_PD_DC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x20)|value<<5) +} +func (o *SYSCON_Type) GetFRONT_END_MEM_PD_DC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x20) >> 5 +} + +// SYSCON.DATE +func (o *SYSCON_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *SYSCON_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// System Configuration Registers +type SYSTEM_Type struct { + ROM_CTRL_0 volatile.Register32 // 0x0 + ROM_CTRL_1 volatile.Register32 // 0x4 + SRAM_CTRL_0 volatile.Register32 // 0x8 + SRAM_CTRL_1 volatile.Register32 // 0xC + CPU_PERI_CLK_EN volatile.Register32 // 0x10 + CPU_PERI_RST_EN volatile.Register32 // 0x14 + CPU_PER_CONF volatile.Register32 // 0x18 + JTAG_CTRL_0 volatile.Register32 // 0x1C + JTAG_CTRL_1 volatile.Register32 // 0x20 + JTAG_CTRL_2 volatile.Register32 // 0x24 + JTAG_CTRL_3 volatile.Register32 // 0x28 + JTAG_CTRL_4 volatile.Register32 // 0x2C + JTAG_CTRL_5 volatile.Register32 // 0x30 + JTAG_CTRL_6 volatile.Register32 // 0x34 + JTAG_CTRL_7 volatile.Register32 // 0x38 + MEM_PD_MASK volatile.Register32 // 0x3C + PERIP_CLK_EN0 volatile.Register32 // 0x40 + PERIP_CLK_EN1 volatile.Register32 // 0x44 + PERIP_RST_EN0 volatile.Register32 // 0x48 + PERIP_RST_EN1 volatile.Register32 // 0x4C + LPCK_DIV_INT volatile.Register32 // 0x50 + BT_LPCK_DIV_FRAC volatile.Register32 // 0x54 + CPU_INTR_FROM_CPU_0 volatile.Register32 // 0x58 + CPU_INTR_FROM_CPU_1 volatile.Register32 // 0x5C + CPU_INTR_FROM_CPU_2 volatile.Register32 // 0x60 + CPU_INTR_FROM_CPU_3 volatile.Register32 // 0x64 + RSA_PD_CTRL volatile.Register32 // 0x68 + BUSTOEXTMEM_ENA volatile.Register32 // 0x6C + CACHE_CONTROL volatile.Register32 // 0x70 + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL volatile.Register32 // 0x74 + RTC_FASTMEM_CONFIG volatile.Register32 // 0x78 + RTC_FASTMEM_CRC volatile.Register32 // 0x7C + Redundant_ECO_Ctrl volatile.Register32 // 0x80 + CLOCK_GATE volatile.Register32 // 0x84 + SRAM_CTRL_2 volatile.Register32 // 0x88 + SYSCLK_CONF volatile.Register32 // 0x8C + _ [3948]byte + DATE volatile.Register32 // 0xFFC +} + +// SYSTEM.ROM_CTRL_0: System ROM configuration register 0 +func (o *SYSTEM_Type) SetROM_CTRL_0_ROM_FO(value uint32) { + volatile.StoreUint32(&o.ROM_CTRL_0.Reg, volatile.LoadUint32(&o.ROM_CTRL_0.Reg)&^(0x3)|value) +} +func (o *SYSTEM_Type) GetROM_CTRL_0_ROM_FO() uint32 { + return volatile.LoadUint32(&o.ROM_CTRL_0.Reg) & 0x3 +} + +// SYSTEM.ROM_CTRL_1: System ROM configuration register 1 +func (o *SYSTEM_Type) SetROM_CTRL_1_ROM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ROM_CTRL_1.Reg, volatile.LoadUint32(&o.ROM_CTRL_1.Reg)&^(0x3)|value) +} +func (o *SYSTEM_Type) GetROM_CTRL_1_ROM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.ROM_CTRL_1.Reg) & 0x3 +} +func (o *SYSTEM_Type) SetROM_CTRL_1_ROM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ROM_CTRL_1.Reg, volatile.LoadUint32(&o.ROM_CTRL_1.Reg)&^(0xc)|value<<2) +} +func (o *SYSTEM_Type) GetROM_CTRL_1_ROM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ROM_CTRL_1.Reg) & 0xc) >> 2 +} + +// SYSTEM.SRAM_CTRL_0: System SRAM configuration register 0 +func (o *SYSTEM_Type) SetSRAM_CTRL_0_SRAM_FO(value uint32) { + volatile.StoreUint32(&o.SRAM_CTRL_0.Reg, volatile.LoadUint32(&o.SRAM_CTRL_0.Reg)&^(0x3fffff)|value) +} +func (o *SYSTEM_Type) GetSRAM_CTRL_0_SRAM_FO() uint32 { + return volatile.LoadUint32(&o.SRAM_CTRL_0.Reg) & 0x3fffff +} + +// SYSTEM.SRAM_CTRL_1: System SRAM configuration register 1 +func (o *SYSTEM_Type) SetSRAM_CTRL_1_SRAM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SRAM_CTRL_1.Reg, volatile.LoadUint32(&o.SRAM_CTRL_1.Reg)&^(0x3fffff)|value) +} +func (o *SYSTEM_Type) GetSRAM_CTRL_1_SRAM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.SRAM_CTRL_1.Reg) & 0x3fffff +} + +// SYSTEM.CPU_PERI_CLK_EN: CPU peripheral clock enable register +func (o *SYSTEM_Type) SetCPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_CLK_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg) & 0x80) >> 7 +} + +// SYSTEM.CPU_PERI_RST_EN: CPU peripheral reset register +func (o *SYSTEM_Type) SetCPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_RST_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg) & 0x80) >> 7 +} + +// SYSTEM.CPU_PER_CONF: CPU peripheral clock configuration register +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x3)|value) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPUPERIOD_SEL() uint32 { + return volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x3 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_PLL_FREQ_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_PLL_FREQ_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPU_WAITI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPU_WAITI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0xf0) >> 4 +} + +// SYSTEM.JTAG_CTRL_0: JTAG configuration register 0 +func (o *SYSTEM_Type) SetJTAG_CTRL_0(value uint32) { + volatile.StoreUint32(&o.JTAG_CTRL_0.Reg, value) +} +func (o *SYSTEM_Type) GetJTAG_CTRL_0() uint32 { + return volatile.LoadUint32(&o.JTAG_CTRL_0.Reg) +} + +// SYSTEM.JTAG_CTRL_1: JTAG configuration register 1 +func (o *SYSTEM_Type) SetJTAG_CTRL_1(value uint32) { + volatile.StoreUint32(&o.JTAG_CTRL_1.Reg, value) +} +func (o *SYSTEM_Type) GetJTAG_CTRL_1() uint32 { + return volatile.LoadUint32(&o.JTAG_CTRL_1.Reg) +} + +// SYSTEM.JTAG_CTRL_2: JTAG configuration register 2 +func (o *SYSTEM_Type) SetJTAG_CTRL_2(value uint32) { + volatile.StoreUint32(&o.JTAG_CTRL_2.Reg, value) +} +func (o *SYSTEM_Type) GetJTAG_CTRL_2() uint32 { + return volatile.LoadUint32(&o.JTAG_CTRL_2.Reg) +} + +// SYSTEM.JTAG_CTRL_3: JTAG configuration register 3 +func (o *SYSTEM_Type) SetJTAG_CTRL_3(value uint32) { + volatile.StoreUint32(&o.JTAG_CTRL_3.Reg, value) +} +func (o *SYSTEM_Type) GetJTAG_CTRL_3() uint32 { + return volatile.LoadUint32(&o.JTAG_CTRL_3.Reg) +} + +// SYSTEM.JTAG_CTRL_4: JTAG configuration register 4 +func (o *SYSTEM_Type) SetJTAG_CTRL_4(value uint32) { + volatile.StoreUint32(&o.JTAG_CTRL_4.Reg, value) +} +func (o *SYSTEM_Type) GetJTAG_CTRL_4() uint32 { + return volatile.LoadUint32(&o.JTAG_CTRL_4.Reg) +} + +// SYSTEM.JTAG_CTRL_5: JTAG configuration register 5 +func (o *SYSTEM_Type) SetJTAG_CTRL_5(value uint32) { + volatile.StoreUint32(&o.JTAG_CTRL_5.Reg, value) +} +func (o *SYSTEM_Type) GetJTAG_CTRL_5() uint32 { + return volatile.LoadUint32(&o.JTAG_CTRL_5.Reg) +} + +// SYSTEM.JTAG_CTRL_6: JTAG configuration register 6 +func (o *SYSTEM_Type) SetJTAG_CTRL_6(value uint32) { + volatile.StoreUint32(&o.JTAG_CTRL_6.Reg, value) +} +func (o *SYSTEM_Type) GetJTAG_CTRL_6() uint32 { + return volatile.LoadUint32(&o.JTAG_CTRL_6.Reg) +} + +// SYSTEM.JTAG_CTRL_7: JTAG configuration register 7 +func (o *SYSTEM_Type) SetJTAG_CTRL_7(value uint32) { + volatile.StoreUint32(&o.JTAG_CTRL_7.Reg, value) +} +func (o *SYSTEM_Type) GetJTAG_CTRL_7() uint32 { + return volatile.LoadUint32(&o.JTAG_CTRL_7.Reg) +} + +// SYSTEM.MEM_PD_MASK: Memory power-related controlling register (under low-sleep) +func (o *SYSTEM_Type) SetMEM_PD_MASK_LSLP_MEM_PD_MASK(value uint32) { + volatile.StoreUint32(&o.MEM_PD_MASK.Reg, volatile.LoadUint32(&o.MEM_PD_MASK.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetMEM_PD_MASK_LSLP_MEM_PD_MASK() uint32 { + return volatile.LoadUint32(&o.MEM_PD_MASK.Reg) & 0x1 +} + +// SYSTEM.PERIP_CLK_EN0: System peripheral clock (for hardware accelerators) enable register +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERS_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI01_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI01_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_WDG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_WDG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2S0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2S0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2C_EXT0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2C_EXT0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UHCI0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UHCI0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_RMT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_RMT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PCNT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PCNT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x400) >> 10 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_LEDC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x800)|value<<11) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_LEDC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x800) >> 11 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UHCI1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UHCI1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1000) >> 12 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERGROUP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERGROUP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2000) >> 13 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_EFUSE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4000)|value<<14) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_EFUSE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4000) >> 14 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERGROUP1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x8000)|value<<15) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERGROUP1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x8000) >> 15 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10000) >> 16 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20000) >> 17 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2C_EXT1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2C_EXT1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40000) >> 18 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TWAI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TWAI_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80000) >> 19 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x100000) >> 20 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2S1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2S1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x200000) >> 21 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI2_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI2_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x400000) >> 22 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_USB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_USB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x800000) >> 23 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI3_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI3_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_APB_SARADC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_APB_SARADC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10000000) >> 28 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SYSTIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SYSTIMER_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20000000) >> 29 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_ADC2_ARB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_ADC2_ARB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40000000) >> 30 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI4_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI4_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.PERIP_CLK_EN1: System peripheral clock (for hardware accelerators) enable register 1 +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_AES_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_AES_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_SHA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_SHA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_RSA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_RSA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_DS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_DS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x40) >> 6 +} + +// SYSTEM.PERIP_RST_EN0: System peripheral (hardware accelerators) reset register 0 +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERS_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERS_RST() uint32 { + return volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI01_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI01_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_WDG_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_WDG_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2S0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2S0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2C_EXT0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2C_EXT0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UHCI0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UHCI0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_RMT_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_RMT_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PCNT_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PCNT_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x400) >> 10 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_LEDC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x800)|value<<11) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_LEDC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x800) >> 11 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UHCI1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UHCI1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1000) >> 12 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERGROUP_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERGROUP_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2000) >> 13 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_EFUSE_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4000)|value<<14) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_EFUSE_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4000) >> 14 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERGROUP1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x8000)|value<<15) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERGROUP1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x8000) >> 15 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI3_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI3_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10000) >> 16 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20000) >> 17 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2C_EXT1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2C_EXT1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40000) >> 18 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TWAI_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TWAI_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80000) >> 19 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x100000) >> 20 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2S1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2S1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x200000) >> 21 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI2_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI2_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x400000) >> 22 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_USB_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_USB_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x800000) >> 23 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART_MEM_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM3_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM3_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI3_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI3_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_APB_SARADC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_APB_SARADC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10000000) >> 28 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SYSTIMER_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SYSTIMER_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20000000) >> 29 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_ADC2_ARB_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_ADC2_ARB_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40000000) >> 30 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI4_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI4_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.PERIP_RST_EN1: System peripheral (hardware accelerators) reset register 1 +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_AES_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_AES_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_SHA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_SHA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_RSA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_RSA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_DS_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_DS_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_HMAC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_HMAC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x40) >> 6 +} + +// SYSTEM.LPCK_DIV_INT: Low power clock divider integer register +func (o *SYSTEM_Type) SetLPCK_DIV_INT_LPCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LPCK_DIV_INT.Reg, volatile.LoadUint32(&o.LPCK_DIV_INT.Reg)&^(0xfff)|value) +} +func (o *SYSTEM_Type) GetLPCK_DIV_INT_LPCK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.LPCK_DIV_INT.Reg) & 0xfff +} + +// SYSTEM.BT_LPCK_DIV_FRAC: Divider fraction configuration register for low-power clock +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_RTC_EN(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_RTC_EN() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x10000000) >> 28 +} + +// SYSTEM.CPU_INTR_FROM_CPU_0: CPU interrupt controlling register 0 +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_0(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_0() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_1: CPU interrupt controlling register 1 +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_1(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_1() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_2: CPU interrupt controlling register 2 +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_2(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_2() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_3: CPU interrupt controlling register 3 +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_3(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_3() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg) & 0x1 +} + +// SYSTEM.RSA_PD_CTRL: RSA memory remapping register +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_PD() uint32 { + return volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x4) >> 2 +} + +// SYSTEM.BUSTOEXTMEM_ENA: EDMA enable register +func (o *SYSTEM_Type) SetBUSTOEXTMEM_ENA(value uint32) { + volatile.StoreUint32(&o.BUSTOEXTMEM_ENA.Reg, volatile.LoadUint32(&o.BUSTOEXTMEM_ENA.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetBUSTOEXTMEM_ENA() uint32 { + return volatile.LoadUint32(&o.BUSTOEXTMEM_ENA.Reg) & 0x1 +} + +// SYSTEM.CACHE_CONTROL: Cache control register +func (o *SYSTEM_Type) SetCACHE_CONTROL_PRO_ICACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_PRO_ICACHE_CLK_ON() uint32 { + return volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_PRO_DCACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_PRO_DCACHE_CLK_ON() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_PRO_CACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_PRO_CACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x4) >> 2 +} + +// SYSTEM.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: External memory encrypt and decrypt controlling register +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x8) >> 3 +} + +// SYSTEM.RTC_FASTMEM_CONFIG: RTC fast memory configuration register +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_START(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_START() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0xffe00)|value<<9) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0xffe00) >> 9 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x7ff00000)|value<<20) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x7ff00000) >> 20 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.RTC_FASTMEM_CRC: RTC fast memory CRC controlling register +func (o *SYSTEM_Type) SetRTC_FASTMEM_CRC(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CRC.Reg, value) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CRC() uint32 { + return volatile.LoadUint32(&o.RTC_FASTMEM_CRC.Reg) +} + +// SYSTEM.Redundant_ECO_Ctrl: Redundant ECO control register +func (o *SYSTEM_Type) SetRedundant_ECO_Ctrl_REDUNDANT_ECO_DRIVE(value uint32) { + volatile.StoreUint32(&o.Redundant_ECO_Ctrl.Reg, volatile.LoadUint32(&o.Redundant_ECO_Ctrl.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetRedundant_ECO_Ctrl_REDUNDANT_ECO_DRIVE() uint32 { + return volatile.LoadUint32(&o.Redundant_ECO_Ctrl.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetRedundant_ECO_Ctrl_REDUNDANT_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.Redundant_ECO_Ctrl.Reg, volatile.LoadUint32(&o.Redundant_ECO_Ctrl.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetRedundant_ECO_Ctrl_REDUNDANT_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.Redundant_ECO_Ctrl.Reg) & 0x2) >> 1 +} + +// SYSTEM.CLOCK_GATE: Clock gate control register +func (o *SYSTEM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SYSTEM.SRAM_CTRL_2: System SRAM configuration register 2 +func (o *SYSTEM_Type) SetSRAM_CTRL_2_SRAM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SRAM_CTRL_2.Reg, volatile.LoadUint32(&o.SRAM_CTRL_2.Reg)&^(0x3fffff)|value) +} +func (o *SYSTEM_Type) GetSRAM_CTRL_2_SRAM_FORCE_PU() uint32 { + return volatile.LoadUint32(&o.SRAM_CTRL_2.Reg) & 0x3fffff +} + +// SYSTEM.SYSCLK_CONF: SoC clock configuration register +func (o *SYSTEM_Type) SetSYSCLK_CONF_PRE_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x3ff)|value) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_PRE_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x3ff +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_SOC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_SOC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0xc00) >> 10 +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_CLK_XTAL_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x7f000)|value<<12) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_CLK_XTAL_FREQ() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x7f000) >> 12 +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_CLK_DIV_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_CLK_DIV_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x80000) >> 19 +} + +// SYSTEM.DATE: Version control register +func (o *SYSTEM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SYSTEM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// System Timer +type SYSTIMER_Type struct { + CONF volatile.Register32 // 0x0 + LOAD volatile.Register32 // 0x4 + LOAD_HI volatile.Register32 // 0x8 + LOAD_LO volatile.Register32 // 0xC + STEP volatile.Register32 // 0x10 + TARGET0_HI volatile.Register32 // 0x14 + TARGET0_LO volatile.Register32 // 0x18 + TARGET1_HI volatile.Register32 // 0x1C + TARGET1_LO volatile.Register32 // 0x20 + TARGET2_HI volatile.Register32 // 0x24 + TARGET2_LO volatile.Register32 // 0x28 + TARGET0_CONF volatile.Register32 // 0x2C + TARGET1_CONF volatile.Register32 // 0x30 + TARGET2_CONF volatile.Register32 // 0x34 + UNIT0_OP volatile.Register32 // 0x38 + UNIT0_VALUE_HI volatile.Register32 // 0x3C + UNIT0_VALUE_LO volatile.Register32 // 0x40 + INT_ENA volatile.Register32 // 0x44 + INT_RAW volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + _ [172]byte + DATE volatile.Register32 // 0xFC +} + +// SYSTIMER.CONF: Configure system timer clock +func (o *SYSTIMER_Type) SetCONF_CLK_FO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCONF_CLK_FO() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.LOAD: Load value to system timer +func (o *SYSTIMER_Type) SetLOAD_TIMER_LOAD(value uint32) { + volatile.StoreUint32(&o.LOAD.Reg, volatile.LoadUint32(&o.LOAD.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetLOAD_TIMER_LOAD() uint32 { + return (volatile.LoadUint32(&o.LOAD.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.LOAD_HI: High 32 bits to be loaded to system timer +func (o *SYSTIMER_Type) SetLOAD_HI(value uint32) { + volatile.StoreUint32(&o.LOAD_HI.Reg, value) +} +func (o *SYSTIMER_Type) GetLOAD_HI() uint32 { + return volatile.LoadUint32(&o.LOAD_HI.Reg) +} + +// SYSTIMER.LOAD_LO: Low 32 bits to be loaded to system timer +func (o *SYSTIMER_Type) SetLOAD_LO(value uint32) { + volatile.StoreUint32(&o.LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetLOAD_LO() uint32 { + return volatile.LoadUint32(&o.LOAD_LO.Reg) +} + +// SYSTIMER.STEP: System timer accumulation step +func (o *SYSTIMER_Type) SetSTEP_TIMER_XTAL_STEP(value uint32) { + volatile.StoreUint32(&o.STEP.Reg, volatile.LoadUint32(&o.STEP.Reg)&^(0x3ff)|value) +} +func (o *SYSTIMER_Type) GetSTEP_TIMER_XTAL_STEP() uint32 { + return volatile.LoadUint32(&o.STEP.Reg) & 0x3ff +} +func (o *SYSTIMER_Type) SetSTEP_TIMER_PLL_STEP(value uint32) { + volatile.StoreUint32(&o.STEP.Reg, volatile.LoadUint32(&o.STEP.Reg)&^(0xffc00)|value<<10) +} +func (o *SYSTIMER_Type) GetSTEP_TIMER_PLL_STEP() uint32 { + return (volatile.LoadUint32(&o.STEP.Reg) & 0xffc00) >> 10 +} + +// SYSTIMER.TARGET0_HI: System timer target 0, high 32 bits +func (o *SYSTIMER_Type) SetTARGET0_HI(value uint32) { + volatile.StoreUint32(&o.TARGET0_HI.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET0_HI() uint32 { + return volatile.LoadUint32(&o.TARGET0_HI.Reg) +} + +// SYSTIMER.TARGET0_LO: System timer target 0, low 32 bits +func (o *SYSTIMER_Type) SetTARGET0_LO(value uint32) { + volatile.StoreUint32(&o.TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET0_LO() uint32 { + return volatile.LoadUint32(&o.TARGET0_LO.Reg) +} + +// SYSTIMER.TARGET1_HI: System timer target 1, high 32 bits +func (o *SYSTIMER_Type) SetTARGET1_HI(value uint32) { + volatile.StoreUint32(&o.TARGET1_HI.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET1_HI() uint32 { + return volatile.LoadUint32(&o.TARGET1_HI.Reg) +} + +// SYSTIMER.TARGET1_LO: System timer target 1, low 32 bits +func (o *SYSTIMER_Type) SetTARGET1_LO(value uint32) { + volatile.StoreUint32(&o.TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET1_LO() uint32 { + return volatile.LoadUint32(&o.TARGET1_LO.Reg) +} + +// SYSTIMER.TARGET2_HI: System timer target 2, high 32 bits +func (o *SYSTIMER_Type) SetTARGET2_HI(value uint32) { + volatile.StoreUint32(&o.TARGET2_HI.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET2_HI() uint32 { + return volatile.LoadUint32(&o.TARGET2_HI.Reg) +} + +// SYSTIMER.TARGET2_LO: System timer target 2, low 32 bits +func (o *SYSTIMER_Type) SetTARGET2_LO(value uint32) { + volatile.StoreUint32(&o.TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET2_LO() uint32 { + return volatile.LoadUint32(&o.TARGET2_LO.Reg) +} + +// SYSTIMER.TARGET0_CONF: Configure work mode for system timer target 0 +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x3fffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x3fffffff +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET1_CONF: Configure work mode for system timer target 1 +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x3fffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x3fffffff +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET2_CONF: Configure work mode for system timer target 2 +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x3fffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x3fffffff +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_WORK_EN(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_OP: Read out system timer value +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_VALUE_HI: System timer value, high 32 bits +func (o *SYSTIMER_Type) SetUNIT0_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_HI.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg) +} + +// SYSTIMER.UNIT0_VALUE_LO: System timer value, low 32 bits +func (o *SYSTIMER_Type) SetUNIT0_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_LO.Reg) +} + +// SYSTIMER.INT_ENA: System timer interrupt enable +func (o *SYSTIMER_Type) SetINT_ENA_TARGET0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_RAW: System timer interrupt raw +func (o *SYSTIMER_Type) SetINT_RAW_INT0_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_RAW_INT0_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_RAW_INT1_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_RAW_INT1_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_RAW_INT2_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_RAW_INT2_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_CLR: System timer interrupt clear +func (o *SYSTIMER_Type) SetINT_CLR_TARGET0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// SYSTIMER.DATE: Version control register +func (o *SYSTIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *SYSTIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Timer Group 0 +type TIMG_Type struct { + T0CONFIG volatile.Register32 // 0x0 + T0LO volatile.Register32 // 0x4 + T0HI volatile.Register32 // 0x8 + T0UPDATE volatile.Register32 // 0xC + T0ALARMLO volatile.Register32 // 0x10 + T0ALARMHI volatile.Register32 // 0x14 + T0LOADLO volatile.Register32 // 0x18 + T0LOADHI volatile.Register32 // 0x1C + T0LOAD volatile.Register32 // 0x20 + T1CONFIG volatile.Register32 // 0x24 + T1LO volatile.Register32 // 0x28 + T1HI volatile.Register32 // 0x2C + T1UPDATE volatile.Register32 // 0x30 + T1ALARMLO volatile.Register32 // 0x34 + T1ALARMHI volatile.Register32 // 0x38 + T1LOADLO volatile.Register32 // 0x3C + T1LOADHI volatile.Register32 // 0x40 + T1LOAD volatile.Register32 // 0x44 + WDTCONFIG0 volatile.Register32 // 0x48 + WDTCONFIG1 volatile.Register32 // 0x4C + WDTCONFIG2 volatile.Register32 // 0x50 + WDTCONFIG3 volatile.Register32 // 0x54 + WDTCONFIG4 volatile.Register32 // 0x58 + WDTCONFIG5 volatile.Register32 // 0x5C + WDTFEED volatile.Register32 // 0x60 + WDTWPROTECT volatile.Register32 // 0x64 + RTCCALICFG volatile.Register32 // 0x68 + RTCCALICFG1 volatile.Register32 // 0x6C + LACTCONFIG volatile.Register32 // 0x70 + LACTRTC volatile.Register32 // 0x74 + LACTLO volatile.Register32 // 0x78 + LACTHI volatile.Register32 // 0x7C + LACTUPDATE volatile.Register32 // 0x80 + LACTALARMLO volatile.Register32 // 0x84 + LACTALARMHI volatile.Register32 // 0x88 + LACTLOADLO volatile.Register32 // 0x8C + LACTLOADHI volatile.Register32 // 0x90 + LACTLOAD volatile.Register32 // 0x94 + INT_ENA_TIMERS volatile.Register32 // 0x98 + INT_RAW_TIMERS volatile.Register32 // 0x9C + INT_ST_TIMERS volatile.Register32 // 0xA0 + INT_CLR_TIMERS volatile.Register32 // 0xA4 + RTCCALICFG2 volatile.Register32 // 0xA8 + _ [76]byte + TIMERS_DATE volatile.Register32 // 0xF8 + REGCLK volatile.Register32 // 0xFC +} + +// TIMG.T0CONFIG: Timer %s configuration register +func (o *TIMG_Type) SetT0CONFIG_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetT0CONFIG_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetT0CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT0CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT0CONFIG_LEVEL_INT_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x800)|value<<11) +} +func (o *TIMG_Type) GetT0CONFIG_LEVEL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x800) >> 11 +} +func (o *TIMG_Type) SetT0CONFIG_EDGE_INT_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetT0CONFIG_EDGE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetT0CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT0CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT0CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT0CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT0CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT0CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT0CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0LO: Timer %s current value, low 32 bits +func (o *TIMG_Type) SetT0LO(value uint32) { + volatile.StoreUint32(&o.T0LO.Reg, value) +} +func (o *TIMG_Type) GetT0LO() uint32 { + return volatile.LoadUint32(&o.T0LO.Reg) +} + +// TIMG.T0HI: Timer %s current value, high 32 bits +func (o *TIMG_Type) SetT0HI(value uint32) { + volatile.StoreUint32(&o.T0HI.Reg, value) +} +func (o *TIMG_Type) GetT0HI() uint32 { + return volatile.LoadUint32(&o.T0HI.Reg) +} + +// TIMG.T0UPDATE: Write to copy current timer value to TIMG_T%sLO_REG or TIMGn_T%sHI_REG +func (o *TIMG_Type) SetT0UPDATE_UPDATE(value uint32) { + volatile.StoreUint32(&o.T0UPDATE.Reg, volatile.LoadUint32(&o.T0UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0UPDATE_UPDATE() uint32 { + return (volatile.LoadUint32(&o.T0UPDATE.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0ALARMLO: Timer %s alarm value, low 32 bits +func (o *TIMG_Type) SetT0ALARMLO(value uint32) { + volatile.StoreUint32(&o.T0ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMLO() uint32 { + return volatile.LoadUint32(&o.T0ALARMLO.Reg) +} + +// TIMG.T0ALARMHI: Timer %s alarm value, high bits +func (o *TIMG_Type) SetT0ALARMHI(value uint32) { + volatile.StoreUint32(&o.T0ALARMHI.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMHI() uint32 { + return volatile.LoadUint32(&o.T0ALARMHI.Reg) +} + +// TIMG.T0LOADLO: Timer %s reload value, low 32 bits +func (o *TIMG_Type) SetT0LOADLO(value uint32) { + volatile.StoreUint32(&o.T0LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT0LOADLO() uint32 { + return volatile.LoadUint32(&o.T0LOADLO.Reg) +} + +// TIMG.T0LOADHI: Timer %s reload value, high 32 bits +func (o *TIMG_Type) SetT0LOADHI(value uint32) { + volatile.StoreUint32(&o.T0LOADHI.Reg, value) +} +func (o *TIMG_Type) GetT0LOADHI() uint32 { + return volatile.LoadUint32(&o.T0LOADHI.Reg) +} + +// TIMG.T0LOAD: Write to reload timer from TIMG_T%sLOADLO_REG or TIMG_T%sLOADHI_REG +func (o *TIMG_Type) SetT0LOAD(value uint32) { + volatile.StoreUint32(&o.T0LOAD.Reg, value) +} +func (o *TIMG_Type) GetT0LOAD() uint32 { + return volatile.LoadUint32(&o.T0LOAD.Reg) +} + +// TIMG.T1CONFIG: Timer %s configuration register +func (o *TIMG_Type) SetT1CONFIG_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetT1CONFIG_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetT1CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT1CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT1CONFIG_LEVEL_INT_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x800)|value<<11) +} +func (o *TIMG_Type) GetT1CONFIG_LEVEL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x800) >> 11 +} +func (o *TIMG_Type) SetT1CONFIG_EDGE_INT_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetT1CONFIG_EDGE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetT1CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT1CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT1CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT1CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT1CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT1CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT1CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT1CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T1LO: Timer %s current value, low 32 bits +func (o *TIMG_Type) SetT1LO(value uint32) { + volatile.StoreUint32(&o.T1LO.Reg, value) +} +func (o *TIMG_Type) GetT1LO() uint32 { + return volatile.LoadUint32(&o.T1LO.Reg) +} + +// TIMG.T1HI: Timer %s current value, high 32 bits +func (o *TIMG_Type) SetT1HI(value uint32) { + volatile.StoreUint32(&o.T1HI.Reg, value) +} +func (o *TIMG_Type) GetT1HI() uint32 { + return volatile.LoadUint32(&o.T1HI.Reg) +} + +// TIMG.T1UPDATE: Write to copy current timer value to TIMG_T%sLO_REG or TIMGn_T%sHI_REG +func (o *TIMG_Type) SetT1UPDATE_UPDATE(value uint32) { + volatile.StoreUint32(&o.T1UPDATE.Reg, volatile.LoadUint32(&o.T1UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT1UPDATE_UPDATE() uint32 { + return (volatile.LoadUint32(&o.T1UPDATE.Reg) & 0x80000000) >> 31 +} + +// TIMG.T1ALARMLO: Timer %s alarm value, low 32 bits +func (o *TIMG_Type) SetT1ALARMLO(value uint32) { + volatile.StoreUint32(&o.T1ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT1ALARMLO() uint32 { + return volatile.LoadUint32(&o.T1ALARMLO.Reg) +} + +// TIMG.T1ALARMHI: Timer %s alarm value, high bits +func (o *TIMG_Type) SetT1ALARMHI(value uint32) { + volatile.StoreUint32(&o.T1ALARMHI.Reg, value) +} +func (o *TIMG_Type) GetT1ALARMHI() uint32 { + return volatile.LoadUint32(&o.T1ALARMHI.Reg) +} + +// TIMG.T1LOADLO: Timer %s reload value, low 32 bits +func (o *TIMG_Type) SetT1LOADLO(value uint32) { + volatile.StoreUint32(&o.T1LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT1LOADLO() uint32 { + return volatile.LoadUint32(&o.T1LOADLO.Reg) +} + +// TIMG.T1LOADHI: Timer %s reload value, high 32 bits +func (o *TIMG_Type) SetT1LOADHI(value uint32) { + volatile.StoreUint32(&o.T1LOADHI.Reg, value) +} +func (o *TIMG_Type) GetT1LOADHI() uint32 { + return volatile.LoadUint32(&o.T1LOADHI.Reg) +} + +// TIMG.T1LOAD: Write to reload timer from TIMG_T%sLOADLO_REG or TIMG_T%sLOADHI_REG +func (o *TIMG_Type) SetT1LOAD(value uint32) { + volatile.StoreUint32(&o.T1LOAD.Reg, value) +} +func (o *TIMG_Type) GetT1LOAD() uint32 { + return volatile.LoadUint32(&o.T1LOAD.Reg) +} + +// TIMG.WDTCONFIG0: Watchdog timer configuration register +func (o *TIMG_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x2000)|value<<13) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x2000) >> 13 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x4000)|value<<14) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x4000) >> 14 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x38000)|value<<15) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x38000) >> 15 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c0000)|value<<18) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c0000) >> 18 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_LEVEL_INT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200000)|value<<21) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_LEVEL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200000) >> 21 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EDGE_INT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400000)|value<<22) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EDGE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400000) >> 22 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1800000)|value<<23) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1800000) >> 23 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x6000000)|value<<25) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x6000000) >> 25 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x18000000)|value<<27) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x18000000) >> 27 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x60000000)|value<<29) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x60000000) >> 29 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// TIMG.WDTCONFIG1: Watchdog timer prescaler register +func (o *TIMG_Type) SetWDTCONFIG1_WDT_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_CLK_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0xffff0000) >> 16 +} + +// TIMG.WDTCONFIG2: Watchdog timer stage 0 timeout value +func (o *TIMG_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// TIMG.WDTCONFIG3: Watchdog timer stage 1 timeout value +func (o *TIMG_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// TIMG.WDTCONFIG4: Watchdog timer stage 2 timeout value +func (o *TIMG_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// TIMG.WDTCONFIG5: Watchdog timer stage 3 timeout value +func (o *TIMG_Type) SetWDTCONFIG5(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG5.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG5() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG5.Reg) +} + +// TIMG.WDTFEED: Write to feed the watchdog timer +func (o *TIMG_Type) SetWDTFEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, value) +} +func (o *TIMG_Type) GetWDTFEED() uint32 { + return volatile.LoadUint32(&o.WDTFEED.Reg) +} + +// TIMG.WDTWPROTECT: Watchdog write protect register +func (o *TIMG_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *TIMG_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// TIMG.RTCCALICFG: RTC calibration configuration register +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START_CYCLING(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START_CYCLING() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x6000)|value<<13) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x6000) >> 13 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_RDY(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x8000)|value<<15) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_RDY() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x8000) >> 15 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_MAX(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x7fff0000)|value<<16) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_MAX() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x7fff0000) >> 16 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x80000000) >> 31 +} + +// TIMG.RTCCALICFG1: RTC calibration configuration register 1 +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_VALUE(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_VALUE() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0xffffff80) >> 7 +} + +// TIMG.LACTCONFIG: LACT configuration register +func (o *TIMG_Type) SetLACTCONFIG_LACT_USE_REFTICK(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x40)|value<<6) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_USE_REFTICK() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x40) >> 6 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_RTC_ONLY(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x80)|value<<7) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_RTC_ONLY() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x80) >> 7 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_CPST_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x100)|value<<8) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_CPST_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x100) >> 8 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_LAC_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_LAC_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_LEVEL_INT_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x800)|value<<11) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_LEVEL_INT_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x800) >> 11 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_EDGE_INT_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_EDGE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_DIVIDER(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_INCREASE(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_INCREASE() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetLACTCONFIG_LACT_EN(value uint32) { + volatile.StoreUint32(&o.LACTCONFIG.Reg, volatile.LoadUint32(&o.LACTCONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetLACTCONFIG_LACT_EN() uint32 { + return (volatile.LoadUint32(&o.LACTCONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.LACTRTC: LACT RTC register +func (o *TIMG_Type) SetLACTRTC_LACT_RTC_STEP_LEN(value uint32) { + volatile.StoreUint32(&o.LACTRTC.Reg, volatile.LoadUint32(&o.LACTRTC.Reg)&^(0xffffffc0)|value<<6) +} +func (o *TIMG_Type) GetLACTRTC_LACT_RTC_STEP_LEN() uint32 { + return (volatile.LoadUint32(&o.LACTRTC.Reg) & 0xffffffc0) >> 6 +} + +// TIMG.LACTLO: LACT low register +func (o *TIMG_Type) SetLACTLO(value uint32) { + volatile.StoreUint32(&o.LACTLO.Reg, value) +} +func (o *TIMG_Type) GetLACTLO() uint32 { + return volatile.LoadUint32(&o.LACTLO.Reg) +} + +// TIMG.LACTHI: LACT high register +func (o *TIMG_Type) SetLACTHI(value uint32) { + volatile.StoreUint32(&o.LACTHI.Reg, value) +} +func (o *TIMG_Type) GetLACTHI() uint32 { + return volatile.LoadUint32(&o.LACTHI.Reg) +} + +// TIMG.LACTUPDATE: LACT update register +func (o *TIMG_Type) SetLACTUPDATE(value uint32) { + volatile.StoreUint32(&o.LACTUPDATE.Reg, value) +} +func (o *TIMG_Type) GetLACTUPDATE() uint32 { + return volatile.LoadUint32(&o.LACTUPDATE.Reg) +} + +// TIMG.LACTALARMLO: LACT alarm low register +func (o *TIMG_Type) SetLACTALARMLO(value uint32) { + volatile.StoreUint32(&o.LACTALARMLO.Reg, value) +} +func (o *TIMG_Type) GetLACTALARMLO() uint32 { + return volatile.LoadUint32(&o.LACTALARMLO.Reg) +} + +// TIMG.LACTALARMHI: LACT alarm high register +func (o *TIMG_Type) SetLACTALARMHI(value uint32) { + volatile.StoreUint32(&o.LACTALARMHI.Reg, value) +} +func (o *TIMG_Type) GetLACTALARMHI() uint32 { + return volatile.LoadUint32(&o.LACTALARMHI.Reg) +} + +// TIMG.LACTLOADLO: LACT load low register +func (o *TIMG_Type) SetLACTLOADLO(value uint32) { + volatile.StoreUint32(&o.LACTLOADLO.Reg, value) +} +func (o *TIMG_Type) GetLACTLOADLO() uint32 { + return volatile.LoadUint32(&o.LACTLOADLO.Reg) +} + +// TIMG.LACTLOADHI: Timer LACT load high register +func (o *TIMG_Type) SetLACTLOADHI(value uint32) { + volatile.StoreUint32(&o.LACTLOADHI.Reg, value) +} +func (o *TIMG_Type) GetLACTLOADHI() uint32 { + return volatile.LoadUint32(&o.LACTLOADHI.Reg) +} + +// TIMG.LACTLOAD: Timer LACT load register +func (o *TIMG_Type) SetLACTLOAD(value uint32) { + volatile.StoreUint32(&o.LACTLOAD.Reg, value) +} +func (o *TIMG_Type) GetLACTLOAD() uint32 { + return volatile.LoadUint32(&o.LACTLOAD.Reg) +} + +// TIMG.INT_ENA_TIMERS: Interrupt enable bits +func (o *TIMG_Type) SetINT_ENA_TIMERS_T0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_T1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x4) >> 2 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_LACT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x8)|value<<3) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_LACT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x8) >> 3 +} + +// TIMG.INT_RAW_TIMERS: Raw interrupt status +func (o *TIMG_Type) SetINT_RAW_TIMERS_T0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_T1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x4) >> 2 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_LACT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x8)|value<<3) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_LACT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x8) >> 3 +} + +// TIMG.INT_ST_TIMERS: Masked interrupt status +func (o *TIMG_Type) SetINT_ST_TIMERS_T0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_T1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x4) >> 2 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_LACT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x8)|value<<3) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_LACT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x8) >> 3 +} + +// TIMG.INT_CLR_TIMERS: Interrupt clear bits +func (o *TIMG_Type) SetINT_CLR_TIMERS_T0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_T1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x4) >> 2 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_LACT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x8)|value<<3) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_LACT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x8) >> 3 +} + +// TIMG.RTCCALICFG2: Timer group calibration register +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x78)|value<<3) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x78) >> 3 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0xffffff80) >> 7 +} + +// TIMG.TIMERS_DATE: Version control register +func (o *TIMG_Type) SetTIMERS_DATE(value uint32) { + volatile.StoreUint32(&o.TIMERS_DATE.Reg, volatile.LoadUint32(&o.TIMERS_DATE.Reg)&^(0xfffffff)|value) +} +func (o *TIMG_Type) GetTIMERS_DATE() uint32 { + return volatile.LoadUint32(&o.TIMERS_DATE.Reg) & 0xfffffff +} + +// TIMG.REGCLK: Timer group clock gate register +func (o *TIMG_Type) SetREGCLK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetREGCLK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x80000000) >> 31 +} + +// Two-Wire Automotive Interface +type TWAI_Type struct { + MODE volatile.Register32 // 0x0 + CMD volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + INT_RAW volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + _ [4]byte + BUS_TIMING_0 volatile.Register32 // 0x18 + BUS_TIMING_1 volatile.Register32 // 0x1C + _ [12]byte + ARB_LOST_CAP volatile.Register32 // 0x2C + ERR_CODE_CAP volatile.Register32 // 0x30 + ERR_WARNING_LIMIT volatile.Register32 // 0x34 + RX_ERR_CNT volatile.Register32 // 0x38 + TX_ERR_CNT volatile.Register32 // 0x3C + DATA_0 volatile.Register32 // 0x40 + DATA_1 volatile.Register32 // 0x44 + DATA_2 volatile.Register32 // 0x48 + DATA_3 volatile.Register32 // 0x4C + DATA_4 volatile.Register32 // 0x50 + DATA_5 volatile.Register32 // 0x54 + DATA_6 volatile.Register32 // 0x58 + DATA_7 volatile.Register32 // 0x5C + DATA_8 volatile.Register32 // 0x60 + DATA_9 volatile.Register32 // 0x64 + DATA_10 volatile.Register32 // 0x68 + DATA_11 volatile.Register32 // 0x6C + DATA_12 volatile.Register32 // 0x70 + RX_MESSAGE_CNT volatile.Register32 // 0x74 + _ [4]byte + CLOCK_DIVIDER volatile.Register32 // 0x7C +} + +// TWAI.MODE: Mode Register +func (o *TWAI_Type) SetMODE_RESET_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetMODE_RESET_MODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x1 +} +func (o *TWAI_Type) SetMODE_LISTEN_ONLY_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetMODE_LISTEN_ONLY_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetMODE_SELF_TEST_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetMODE_SELF_TEST_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetMODE_RX_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetMODE_RX_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x8) >> 3 +} + +// TWAI.CMD: Command Register +func (o *TWAI_Type) SetCMD_TX_REQ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetCMD_TX_REQ() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *TWAI_Type) SetCMD_ABORT_TX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetCMD_ABORT_TX() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetCMD_RELEASE_BUF(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetCMD_RELEASE_BUF() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetCMD_CLR_OVERRUN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetCMD_CLR_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetCMD_SELF_RX_REQ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetCMD_SELF_RX_REQ() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10) >> 4 +} + +// TWAI.STATUS: Status register +func (o *TWAI_Type) SetSTATUS_RX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSTATUS_RX_BUF_ST() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *TWAI_Type) SetSTATUS_OVERRUN_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSTATUS_OVERRUN_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetSTATUS_TX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetSTATUS_TX_BUF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetSTATUS_TX_COMPLETE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetSTATUS_TX_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetSTATUS_RX_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetSTATUS_RX_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *TWAI_Type) SetSTATUS_TX_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetSTATUS_TX_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetSTATUS_ERR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetSTATUS_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetSTATUS_BUS_OFF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetSTATUS_BUS_OFF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetSTATUS_MISS_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetSTATUS_MISS_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} + +// TWAI.INT_RAW: Interrupt Register +func (o *TWAI_Type) SetINT_RAW_RX_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINT_RAW_RX_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *TWAI_Type) SetINT_RAW_TX_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINT_RAW_TX_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINT_RAW_ERR_WARN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINT_RAW_ERR_WARN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINT_RAW_OVERRUN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINT_RAW_OVERRUN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINT_RAW_ERR_PASSIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINT_RAW_ERR_PASSIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINT_RAW_ARB_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINT_RAW_ARB_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINT_RAW_BUS_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINT_RAW_BUS_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} + +// TWAI.INT_ENA: Interrupt Enable Register +func (o *TWAI_Type) SetINT_ENA_RX_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINT_ENA_RX_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *TWAI_Type) SetINT_ENA_TX_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINT_ENA_TX_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINT_ENA_ERR_WARN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINT_ENA_ERR_WARN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINT_ENA_OVERRUN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINT_ENA_OVERRUN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINT_ENA_ERR_PASSIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINT_ENA_ERR_PASSIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINT_ENA_ARB_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINT_ENA_ARB_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINT_ENA_BUS_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINT_ENA_BUS_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} + +// TWAI.BUS_TIMING_0: Bus Timing Register 0 +func (o *TWAI_Type) SetBUS_TIMING_0_BAUD_PRESC(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0x3fff)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_0_BAUD_PRESC() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0x3fff +} +func (o *TWAI_Type) SetBUS_TIMING_0_SYNC_JUMP_WIDTH(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0xc000)|value<<14) +} +func (o *TWAI_Type) GetBUS_TIMING_0_SYNC_JUMP_WIDTH() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0xc000) >> 14 +} + +// TWAI.BUS_TIMING_1: Bus Timing Register 1 +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG1(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0xf)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG1() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0xf +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG2(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x70)|value<<4) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG2() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x70) >> 4 +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SAMP(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SAMP() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x80) >> 7 +} + +// TWAI.ARB_LOST_CAP: Arbitration Lost Capture Register +func (o *TWAI_Type) SetARB_LOST_CAP(value uint32) { + volatile.StoreUint32(&o.ARB_LOST_CAP.Reg, volatile.LoadUint32(&o.ARB_LOST_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetARB_LOST_CAP() uint32 { + return volatile.LoadUint32(&o.ARB_LOST_CAP.Reg) & 0x1f +} + +// TWAI.ERR_CODE_CAP: Error Code Capture Register +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_SEGMENT(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_SEGMENT() uint32 { + return volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x1f +} +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_DIRECTION(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_TYPE(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0xc0)|value<<6) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_TYPE() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0xc0) >> 6 +} + +// TWAI.ERR_WARNING_LIMIT: Error Warning Limit Register +func (o *TWAI_Type) SetERR_WARNING_LIMIT(value uint32) { + volatile.StoreUint32(&o.ERR_WARNING_LIMIT.Reg, volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetERR_WARNING_LIMIT() uint32 { + return volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg) & 0xff +} + +// TWAI.RX_ERR_CNT: Receive Error Counter Register +func (o *TWAI_Type) SetRX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ERR_CNT.Reg, volatile.LoadUint32(&o.RX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetRX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.RX_ERR_CNT.Reg) & 0xff +} + +// TWAI.TX_ERR_CNT: Transmit Error Counter Register +func (o *TWAI_Type) SetTX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ERR_CNT.Reg, volatile.LoadUint32(&o.TX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetTX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.TX_ERR_CNT.Reg) & 0xff +} + +// TWAI.DATA_0: Data register 0 +func (o *TWAI_Type) SetDATA_0_TX_BYTE_0(value uint32) { + volatile.StoreUint32(&o.DATA_0.Reg, volatile.LoadUint32(&o.DATA_0.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_0_TX_BYTE_0() uint32 { + return volatile.LoadUint32(&o.DATA_0.Reg) & 0xff +} + +// TWAI.DATA_1: Data register 1 +func (o *TWAI_Type) SetDATA_1_TX_BYTE_1(value uint32) { + volatile.StoreUint32(&o.DATA_1.Reg, volatile.LoadUint32(&o.DATA_1.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_1_TX_BYTE_1() uint32 { + return volatile.LoadUint32(&o.DATA_1.Reg) & 0xff +} + +// TWAI.DATA_2: Data register 2 +func (o *TWAI_Type) SetDATA_2_TX_BYTE_2(value uint32) { + volatile.StoreUint32(&o.DATA_2.Reg, volatile.LoadUint32(&o.DATA_2.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_2_TX_BYTE_2() uint32 { + return volatile.LoadUint32(&o.DATA_2.Reg) & 0xff +} + +// TWAI.DATA_3: Data register 3 +func (o *TWAI_Type) SetDATA_3_TX_BYTE_3(value uint32) { + volatile.StoreUint32(&o.DATA_3.Reg, volatile.LoadUint32(&o.DATA_3.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_3_TX_BYTE_3() uint32 { + return volatile.LoadUint32(&o.DATA_3.Reg) & 0xff +} + +// TWAI.DATA_4: Data register 4 +func (o *TWAI_Type) SetDATA_4_TX_BYTE_4(value uint32) { + volatile.StoreUint32(&o.DATA_4.Reg, volatile.LoadUint32(&o.DATA_4.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_4_TX_BYTE_4() uint32 { + return volatile.LoadUint32(&o.DATA_4.Reg) & 0xff +} + +// TWAI.DATA_5: Data register 5 +func (o *TWAI_Type) SetDATA_5_TX_BYTE_5(value uint32) { + volatile.StoreUint32(&o.DATA_5.Reg, volatile.LoadUint32(&o.DATA_5.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_5_TX_BYTE_5() uint32 { + return volatile.LoadUint32(&o.DATA_5.Reg) & 0xff +} + +// TWAI.DATA_6: Data register 6 +func (o *TWAI_Type) SetDATA_6_TX_BYTE_6(value uint32) { + volatile.StoreUint32(&o.DATA_6.Reg, volatile.LoadUint32(&o.DATA_6.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_6_TX_BYTE_6() uint32 { + return volatile.LoadUint32(&o.DATA_6.Reg) & 0xff +} + +// TWAI.DATA_7: Data register 7 +func (o *TWAI_Type) SetDATA_7_TX_BYTE_7(value uint32) { + volatile.StoreUint32(&o.DATA_7.Reg, volatile.LoadUint32(&o.DATA_7.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_7_TX_BYTE_7() uint32 { + return volatile.LoadUint32(&o.DATA_7.Reg) & 0xff +} + +// TWAI.DATA_8: Data register 8 +func (o *TWAI_Type) SetDATA_8_TX_BYTE_8(value uint32) { + volatile.StoreUint32(&o.DATA_8.Reg, volatile.LoadUint32(&o.DATA_8.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_8_TX_BYTE_8() uint32 { + return volatile.LoadUint32(&o.DATA_8.Reg) & 0xff +} + +// TWAI.DATA_9: Data register 9 +func (o *TWAI_Type) SetDATA_9_TX_BYTE_9(value uint32) { + volatile.StoreUint32(&o.DATA_9.Reg, volatile.LoadUint32(&o.DATA_9.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_9_TX_BYTE_9() uint32 { + return volatile.LoadUint32(&o.DATA_9.Reg) & 0xff +} + +// TWAI.DATA_10: Data register 10 +func (o *TWAI_Type) SetDATA_10_TX_BYTE_10(value uint32) { + volatile.StoreUint32(&o.DATA_10.Reg, volatile.LoadUint32(&o.DATA_10.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_10_TX_BYTE_10() uint32 { + return volatile.LoadUint32(&o.DATA_10.Reg) & 0xff +} + +// TWAI.DATA_11: Data register 11 +func (o *TWAI_Type) SetDATA_11_TX_BYTE_11(value uint32) { + volatile.StoreUint32(&o.DATA_11.Reg, volatile.LoadUint32(&o.DATA_11.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_11_TX_BYTE_11() uint32 { + return volatile.LoadUint32(&o.DATA_11.Reg) & 0xff +} + +// TWAI.DATA_12: Data register 12 +func (o *TWAI_Type) SetDATA_12_TX_BYTE_12(value uint32) { + volatile.StoreUint32(&o.DATA_12.Reg, volatile.LoadUint32(&o.DATA_12.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_12_TX_BYTE_12() uint32 { + return volatile.LoadUint32(&o.DATA_12.Reg) & 0xff +} + +// TWAI.RX_MESSAGE_CNT: Receive Message Counter Register +func (o *TWAI_Type) SetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER(value uint32) { + volatile.StoreUint32(&o.RX_MESSAGE_CNT.Reg, volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg)&^(0x7f)|value) +} +func (o *TWAI_Type) GetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER() uint32 { + return volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg) & 0x7f +} + +// TWAI.CLOCK_DIVIDER: Clock Divider register +func (o *TWAI_Type) SetCLOCK_DIVIDER_CD(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CD() uint32 { + return volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0xff +} +func (o *TWAI_Type) SetCLOCK_DIVIDER_CLOCK_OFF(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CLOCK_OFF() uint32 { + return (volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0x100) >> 8 +} + +// UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +type UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV volatile.Register32 // 0x14 + AUTOBAUD volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0 volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + LOWPULSE volatile.Register32 // 0x28 + HIGHPULSE volatile.Register32 // 0x2C + RXD_CNT volatile.Register32 // 0x30 + FLOW_CONF volatile.Register32 // 0x34 + SLEEP_CONF volatile.Register32 // 0x38 + SWFC_CONF0 volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + IDLE_CONF volatile.Register32 // 0x44 + RS485_CONF volatile.Register32 // 0x48 + AT_CMD_PRECNT volatile.Register32 // 0x4C + AT_CMD_POSTCNT volatile.Register32 // 0x50 + AT_CMD_GAPTOUT volatile.Register32 // 0x54 + AT_CMD_CHAR volatile.Register32 // 0x58 + MEM_CONF volatile.Register32 // 0x5C + MEM_TX_STATUS volatile.Register32 // 0x60 + MEM_RX_STATUS volatile.Register32 // 0x64 + FSM_STATUS volatile.Register32 // 0x68 + POSPULSE volatile.Register32 // 0x6C + NEGPULSE volatile.Register32 // 0x70 + DATE volatile.Register32 // 0x74 + ID volatile.Register32 // 0x78 +} + +// UART.FIFO: FIFO data register +func (o *UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// UART.INT_RAW: Raw interrupt status +func (o *UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_RAW_RS485_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_RAW_RS485_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_RAW_RS485_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_RAW_RS485_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_RAW_RS485_CLASH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_RAW_RS485_CLASH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// UART.INT_ST: Masked interrupt status +func (o *UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ST_RS485_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ST_RS485_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ST_RS485_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ST_RS485_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ST_RS485_CLASH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ST_RS485_CLASH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// UART.INT_ENA: Interrupt enable bits +func (o *UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ENA_RS485_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ENA_RS485_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ENA_RS485_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ENA_RS485_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ENA_RS485_CLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ENA_RS485_CLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// UART.INT_CLR: Interrupt clear bits +func (o *UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_CLR_RS485_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_CLR_RS485_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_CLR_RS485_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_CLR_RS485_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_CLR_RS485_CLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_CLR_RS485_CLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// UART.CLKDIV: Clock divider configuration +func (o *UART_Type) SetCLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetCLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xfffff +} +func (o *UART_Type) SetCLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xf00000)|value<<20) +} +func (o *UART_Type) GetCLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xf00000) >> 20 +} + +// UART.AUTOBAUD: Autobaud configuration register +func (o *UART_Type) SetAUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.AUTOBAUD.Reg, volatile.LoadUint32(&o.AUTOBAUD.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetAUTOBAUD_EN() uint32 { + return volatile.LoadUint32(&o.AUTOBAUD.Reg) & 0x1 +} +func (o *UART_Type) SetAUTOBAUD_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.AUTOBAUD.Reg, volatile.LoadUint32(&o.AUTOBAUD.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAUTOBAUD_GLITCH_FILT() uint32 { + return (volatile.LoadUint32(&o.AUTOBAUD.Reg) & 0xff00) >> 8 +} + +// UART.STATUS: UART status register +func (o *UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ff0000)|value<<16) +} +func (o *UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3ff0000) >> 16 +} +func (o *UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// UART.CONF0: Configuration register 0 +func (o *UART_Type) SetCONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetCONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UART_Type) SetCONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetCONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetCONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0xc)|value<<2) +} +func (o *UART_Type) GetCONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0xc) >> 2 +} +func (o *UART_Type) SetCONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x30)|value<<4) +} +func (o *UART_Type) GetCONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x30) >> 4 +} +func (o *UART_Type) SetCONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetCONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetCONF0_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetCONF0_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetCONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetCONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetCONF0_IRDA_DPLX(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetCONF0_IRDA_DPLX() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetCONF0_IRDA_TX_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetCONF0_IRDA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetCONF0_IRDA_WCTL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetCONF0_IRDA_WCTL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetCONF0_IRDA_TX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetCONF0_IRDA_TX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetCONF0_IRDA_RX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetCONF0_IRDA_RX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetCONF0_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetCONF0_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetCONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetCONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetCONF0_IRDA_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF0_IRDA_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF0_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF0_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF0_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF0_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF0_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF0_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetCONF0_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCONF0_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCONF0_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF0_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCONF0_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCONF0_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCONF0_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCONF0_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCONF0_TICK_REF_ALWAYS_ON(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCONF0_TICK_REF_ALWAYS_ON() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000000) >> 27 +} +func (o *UART_Type) SetCONF0_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *UART_Type) GetCONF0_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000000) >> 28 +} + +// UART.CONF1: Configuration register 1 +func (o *UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1ff)|value) +} +func (o *UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1ff +} +func (o *UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x3fe00)|value<<9) +} +func (o *UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x3fe00) >> 9 +} +func (o *UART_Type) SetCONF1_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *UART_Type) GetCONF1_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000000) >> 29 +} +func (o *UART_Type) SetCONF1_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetCONF1_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetCONF1_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetCONF1_RX_TOUT_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000000) >> 31 +} + +// UART.LOWPULSE: Autobaud minimum low pulse duration register +func (o *UART_Type) SetLOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.LOWPULSE.Reg, volatile.LoadUint32(&o.LOWPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetLOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.LOWPULSE.Reg) & 0xfffff +} + +// UART.HIGHPULSE: Autobaud minimum high pulse duration register +func (o *UART_Type) SetHIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.HIGHPULSE.Reg, volatile.LoadUint32(&o.HIGHPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetHIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.HIGHPULSE.Reg) & 0xfffff +} + +// UART.RXD_CNT: Autobaud edge change count register +func (o *UART_Type) SetRXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.RXD_CNT.Reg, volatile.LoadUint32(&o.RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetRXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.RXD_CNT.Reg) & 0x3ff +} + +// UART.FLOW_CONF: Software flow control configuration +func (o *UART_Type) SetFLOW_CONF_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetFLOW_CONF_SW_FLOW_CON_EN() uint32 { + return volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetFLOW_CONF_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetFLOW_CONF_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x20) >> 5 +} + +// UART.SLEEP_CONF: Sleep mode configuration +func (o *UART_Type) SetSLEEP_CONF_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF.Reg, volatile.LoadUint32(&o.SLEEP_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSLEEP_CONF_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF.Reg) & 0x3ff +} + +// UART.SWFC_CONF0: Software flow control character configuration +func (o *UART_Type) SetSWFC_CONF0_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x1ff)|value) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x1ff +} +func (o *UART_Type) SetSWFC_CONF0_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x1fe00) >> 9 +} + +// UART.SWFC_CONF1: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0x1ff)|value) +} +func (o *UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0x1ff +} +func (o *UART_Type) SetSWFC_CONF1_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0x1fe00)|value<<9) +} +func (o *UART_Type) GetSWFC_CONF1_XON_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0x1fe00) >> 9 +} + +// UART.IDLE_CONF: Frame end idle time configuration +func (o *UART_Type) SetIDLE_CONF_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetIDLE_CONF_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0x3ff +} +func (o *UART_Type) SetIDLE_CONF_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *UART_Type) GetIDLE_CONF_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xffc00) >> 10 +} +func (o *UART_Type) SetIDLE_CONF_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xff00000)|value<<20) +} +func (o *UART_Type) GetIDLE_CONF_TX_BRK_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xff00000) >> 20 +} + +// UART.RS485_CONF: RS485 mode configuration +func (o *UART_Type) SetRS485_CONF_RS485_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetRS485_CONF_RS485_EN() uint32 { + return volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetRS485_CONF_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetRS485_CONF_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetRS485_CONF_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetRS485_CONF_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetRS485_CONF_RS485TX_RX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetRS485_CONF_RS485TX_RX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetRS485_CONF_RS485RXBY_TX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetRS485_CONF_RS485RXBY_TX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetRS485_CONF_RS485_RX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetRS485_CONF_RS485_RX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetRS485_CONF_RS485_TX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x3c0)|value<<6) +} +func (o *UART_Type) GetRS485_CONF_RS485_TX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x3c0) >> 6 +} + +// UART.AT_CMD_PRECNT: Pre-sequence timing configuration +func (o *UART_Type) SetAT_CMD_PRECNT_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_PRECNT_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg) & 0xffff +} + +// UART.AT_CMD_POSTCNT: Post-sequence timing configuration +func (o *UART_Type) SetAT_CMD_POSTCNT_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_POSTCNT_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg) & 0xffff +} + +// UART.AT_CMD_GAPTOUT: Timeout configuration +func (o *UART_Type) SetAT_CMD_GAPTOUT_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_GAPTOUT_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg) & 0xffff +} + +// UART.AT_CMD_CHAR: AT escape sequence selection configuration +func (o *UART_Type) SetAT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetAT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff +} +func (o *UART_Type) SetAT_CMD_CHAR_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAT_CMD_CHAR_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff00) >> 8 +} + +// UART.MEM_CONF: UART threshold and allocation configuration +func (o *UART_Type) SetMEM_CONF_RX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xe)|value<<1) +} +func (o *UART_Type) GetMEM_CONF_RX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xe) >> 1 +} +func (o *UART_Type) SetMEM_CONF_TX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x70)|value<<4) +} +func (o *UART_Type) GetMEM_CONF_TX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x70) >> 4 +} +func (o *UART_Type) SetMEM_CONF_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xff80)|value<<7) +} +func (o *UART_Type) GetMEM_CONF_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xff80) >> 7 +} +func (o *UART_Type) SetMEM_CONF_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x3ff0000)|value<<16) +} +func (o *UART_Type) GetMEM_CONF_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x3ff0000) >> 16 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x8000000) >> 27 +} + +// UART.MEM_TX_STATUS: TX FIFO write and read offset address +func (o *UART_Type) SetMEM_TX_STATUS_APB_TX_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetMEM_TX_STATUS_APB_TX_WADDR() uint32 { + return volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetMEM_TX_STATUS_TX_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1ff800) >> 11 +} + +// UART.MEM_RX_STATUS: RX FIFO write and read offset address +func (o *UART_Type) SetMEM_RX_STATUS_APB_RX_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetMEM_RX_STATUS_APB_RX_RADDR() uint32 { + return volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetMEM_RX_STATUS_RX_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1ff800) >> 11 +} + +// UART.FSM_STATUS: UART transmitter and receiver status +func (o *UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// UART.POSPULSE: Autobaud high pulse register +func (o *UART_Type) SetPOSPULSE_POSEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.POSPULSE.Reg, volatile.LoadUint32(&o.POSPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetPOSPULSE_POSEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.POSPULSE.Reg) & 0xfffff +} + +// UART.NEGPULSE: Autobaud low pulse register +func (o *UART_Type) SetNEGPULSE_NEGEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.NEGPULSE.Reg, volatile.LoadUint32(&o.NEGPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART_Type) GetNEGPULSE_NEGEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.NEGPULSE.Reg) & 0xfffff +} + +// UART.DATE: UART version control register +func (o *UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// UART.ID: UART ID register +func (o *UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, value) +} +func (o *UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) +} + +// Universal Host Controller Interface 0 +type UHCI_Type struct { + CONF0 volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + DMA_OUT_STATUS volatile.Register32 // 0x14 + DMA_OUT_PUSH volatile.Register32 // 0x18 + DMA_IN_STATUS volatile.Register32 // 0x1C + DMA_IN_POP volatile.Register32 // 0x20 + DMA_OUT_LINK volatile.Register32 // 0x24 + DMA_IN_LINK volatile.Register32 // 0x28 + CONF1 volatile.Register32 // 0x2C + STATE0 volatile.Register32 // 0x30 + STATE1 volatile.Register32 // 0x34 + DMA_OUT_EOF_DES_ADDR volatile.Register32 // 0x38 + DMA_IN_SUC_EOF_DES_ADDR volatile.Register32 // 0x3C + DMA_IN_ERR_EOF_DES_ADDR volatile.Register32 // 0x40 + DMA_OUT_EOF_BFR_DES_ADDR volatile.Register32 // 0x44 + AHB_TEST volatile.Register32 // 0x48 + DMA_IN_DSCR volatile.Register32 // 0x4C + DMA_IN_DSCR_BF0 volatile.Register32 // 0x50 + _ [4]byte + DMA_OUT_DSCR volatile.Register32 // 0x58 + DMA_OUT_DSCR_BF0 volatile.Register32 // 0x5C + _ [4]byte + ESCAPE_CONF volatile.Register32 // 0x64 + HUNG_CONF volatile.Register32 // 0x68 + _ [4]byte + RX_HEAD volatile.Register32 // 0x70 + QUICK_SENT volatile.Register32 // 0x74 + Q0_WORD0 volatile.Register32 // 0x78 + Q0_WORD1 volatile.Register32 // 0x7C + Q1_WORD0 volatile.Register32 // 0x80 + Q1_WORD1 volatile.Register32 // 0x84 + Q2_WORD0 volatile.Register32 // 0x88 + Q2_WORD1 volatile.Register32 // 0x8C + Q3_WORD0 volatile.Register32 // 0x90 + Q3_WORD1 volatile.Register32 // 0x94 + Q4_WORD0 volatile.Register32 // 0x98 + Q4_WORD1 volatile.Register32 // 0x9C + Q5_WORD0 volatile.Register32 // 0xA0 + Q5_WORD1 volatile.Register32 // 0xA4 + Q6_WORD0 volatile.Register32 // 0xA8 + Q6_WORD1 volatile.Register32 // 0xAC + ESC_CONF0 volatile.Register32 // 0xB0 + ESC_CONF1 volatile.Register32 // 0xB4 + ESC_CONF2 volatile.Register32 // 0xB8 + ESC_CONF3 volatile.Register32 // 0xBC + PKT_THRES volatile.Register32 // 0xC0 + _ [56]byte + DATE volatile.Register32 // 0xFC +} + +// UHCI.CONF0: UHCI configuration register +func (o *UHCI_Type) SetCONF0_IN_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF0_IN_RST() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF0_OUT_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF0_OUT_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF0_AHBM_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF0_AHBM_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF0_AHBM_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF0_AHBM_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF0_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF0_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF0_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF0_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF0_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetCONF0_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetCONF0_OUT_NO_RESTART_CLR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF0_OUT_NO_RESTART_CLR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF0_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF0_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetCONF0_UART0_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetCONF0_UART0_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetCONF0_UART1_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetCONF0_UART1_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetCONF0_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetCONF0_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetCONF0_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetCONF0_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetCONF0_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetCONF0_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetCONF0_SEPER_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetCONF0_SEPER_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *UHCI_Type) SetCONF0_HEAD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UHCI_Type) GetCONF0_HEAD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *UHCI_Type) SetCONF0_CRC_REC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UHCI_Type) GetCONF0_CRC_REC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *UHCI_Type) SetCONF0_UART_IDLE_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UHCI_Type) GetCONF0_UART_IDLE_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *UHCI_Type) SetCONF0_LEN_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UHCI_Type) GetCONF0_LEN_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *UHCI_Type) SetCONF0_ENCODE_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UHCI_Type) GetCONF0_ENCODE_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *UHCI_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UHCI_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *UHCI_Type) SetCONF0_UART_RX_BRK_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UHCI_Type) GetCONF0_UART_RX_BRK_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} + +// UHCI.INT_RAW: Raw interrupt status +func (o *UHCI_Type) SetINT_RAW_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_RAW_RX_START_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_RAW_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_RAW_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_RAW_IN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_RAW_IN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_RAW_IN_SUC_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_RAW_IN_SUC_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_RAW_IN_ERR_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_RAW_IN_ERR_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_RAW_OUT_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_RAW_OUT_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetINT_RAW_IN_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetINT_RAW_IN_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetINT_RAW_OUT_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetINT_RAW_OUT_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetINT_RAW_IN_DSCR_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetINT_RAW_IN_DSCR_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetINT_RAW_OUTLINK_EOF_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetINT_RAW_OUTLINK_EOF_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetINT_RAW_OUT_TOTAL_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetINT_RAW_OUT_TOTAL_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetINT_RAW_SEND_S_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UHCI_Type) GetINT_RAW_SEND_S_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UHCI_Type) SetINT_RAW_SEND_A_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetINT_RAW_SEND_A_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetINT_RAW_DMA_INFIFO_FULL_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetINT_RAW_DMA_INFIFO_FULL_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} + +// UHCI.INT_ST: Masked interrupt status +func (o *UHCI_Type) SetINT_ST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ST_RX_START_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ST_IN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ST_IN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ST_IN_SUC_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ST_IN_SUC_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ST_IN_ERR_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ST_IN_ERR_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ST_OUT_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ST_OUT_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ST_OUT_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ST_OUT_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetINT_ST_IN_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetINT_ST_IN_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetINT_ST_OUT_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetINT_ST_OUT_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetINT_ST_IN_DSCR_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetINT_ST_IN_DSCR_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetINT_ST_OUTLINK_EOF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetINT_ST_OUTLINK_EOF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetINT_ST_OUT_TOTAL_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetINT_ST_OUT_TOTAL_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetINT_ST_SEND_S_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UHCI_Type) GetINT_ST_SEND_S_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UHCI_Type) SetINT_ST_SEND_A_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetINT_ST_SEND_A_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetINT_ST_DMA_INFIFO_FULL_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetINT_ST_DMA_INFIFO_FULL_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} + +// UHCI.INT_ENA: Interrupt enable bits +func (o *UHCI_Type) SetINT_ENA_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ENA_RX_START_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ENA_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ENA_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ENA_IN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ENA_IN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ENA_IN_SUC_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ENA_IN_SUC_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ENA_IN_ERR_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ENA_IN_ERR_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ENA_OUT_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ENA_OUT_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ENA_OUT_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ENA_OUT_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetINT_ENA_IN_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetINT_ENA_IN_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetINT_ENA_OUT_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetINT_ENA_OUT_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetINT_ENA_IN_DSCR_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetINT_ENA_IN_DSCR_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetINT_ENA_OUTLINK_EOF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetINT_ENA_OUTLINK_EOF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetINT_ENA_OUT_TOTAL_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetINT_ENA_OUT_TOTAL_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetINT_ENA_SEND_S_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UHCI_Type) GetINT_ENA_SEND_S_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UHCI_Type) SetINT_ENA_SEND_A_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetINT_ENA_SEND_A_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetINT_ENA_DMA_INFIFO_FULL_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetINT_ENA_DMA_INFIFO_FULL_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} + +// UHCI.INT_CLR: Interrupt clear bits +func (o *UHCI_Type) SetINT_CLR_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_CLR_RX_START_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_CLR_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_CLR_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_CLR_IN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_CLR_IN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_CLR_IN_SUC_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_CLR_IN_SUC_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_CLR_IN_ERR_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_CLR_IN_ERR_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_CLR_OUT_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_CLR_OUT_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_CLR_OUT_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_CLR_OUT_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetINT_CLR_IN_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetINT_CLR_IN_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetINT_CLR_OUT_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetINT_CLR_OUT_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetINT_CLR_IN_DSCR_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetINT_CLR_IN_DSCR_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetINT_CLR_OUTLINK_EOF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetINT_CLR_OUTLINK_EOF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UHCI_Type) SetINT_CLR_OUT_TOTAL_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UHCI_Type) GetINT_CLR_OUT_TOTAL_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UHCI_Type) SetINT_CLR_SEND_S_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UHCI_Type) GetINT_CLR_SEND_S_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UHCI_Type) SetINT_CLR_SEND_A_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UHCI_Type) GetINT_CLR_SEND_A_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UHCI_Type) SetINT_CLR_DMA_INFIFO_FULL_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetINT_CLR_DMA_INFIFO_FULL_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} + +// UHCI.DMA_OUT_STATUS: DMA data-output status register +func (o *UHCI_Type) SetDMA_OUT_STATUS_OUT_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_STATUS.Reg, volatile.LoadUint32(&o.DMA_OUT_STATUS.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetDMA_OUT_STATUS_OUT_FULL() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_STATUS.Reg) & 0x1 +} +func (o *UHCI_Type) SetDMA_OUT_STATUS_OUT_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_STATUS.Reg, volatile.LoadUint32(&o.DMA_OUT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetDMA_OUT_STATUS_OUT_EMPTY() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_STATUS.Reg) & 0x2) >> 1 +} + +// UHCI.DMA_OUT_PUSH: Push control register of TX FIFO +func (o *UHCI_Type) SetDMA_OUT_PUSH_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_PUSH.Reg, volatile.LoadUint32(&o.DMA_OUT_PUSH.Reg)&^(0x1ff)|value) +} +func (o *UHCI_Type) GetDMA_OUT_PUSH_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_PUSH.Reg) & 0x1ff +} +func (o *UHCI_Type) SetDMA_OUT_PUSH_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_PUSH.Reg, volatile.LoadUint32(&o.DMA_OUT_PUSH.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetDMA_OUT_PUSH_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_PUSH.Reg) & 0x10000) >> 16 +} + +// UHCI.DMA_IN_STATUS: UHCI data-input status register +func (o *UHCI_Type) SetDMA_IN_STATUS_IN_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_IN_STATUS.Reg, volatile.LoadUint32(&o.DMA_IN_STATUS.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetDMA_IN_STATUS_IN_FULL() uint32 { + return volatile.LoadUint32(&o.DMA_IN_STATUS.Reg) & 0x1 +} +func (o *UHCI_Type) SetDMA_IN_STATUS_IN_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_IN_STATUS.Reg, volatile.LoadUint32(&o.DMA_IN_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetDMA_IN_STATUS_IN_EMPTY() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_STATUS.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetDMA_IN_STATUS_RX_ERR_CAUSE(value uint32) { + volatile.StoreUint32(&o.DMA_IN_STATUS.Reg, volatile.LoadUint32(&o.DMA_IN_STATUS.Reg)&^(0x70)|value<<4) +} +func (o *UHCI_Type) GetDMA_IN_STATUS_RX_ERR_CAUSE() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_STATUS.Reg) & 0x70) >> 4 +} + +// UHCI.DMA_IN_POP: Pop control register of RX FIFO +func (o *UHCI_Type) SetDMA_IN_POP_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DMA_IN_POP.Reg, volatile.LoadUint32(&o.DMA_IN_POP.Reg)&^(0xfff)|value) +} +func (o *UHCI_Type) GetDMA_IN_POP_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DMA_IN_POP.Reg) & 0xfff +} +func (o *UHCI_Type) SetDMA_IN_POP_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_POP.Reg, volatile.LoadUint32(&o.DMA_IN_POP.Reg)&^(0x10000)|value<<16) +} +func (o *UHCI_Type) GetDMA_IN_POP_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_POP.Reg) & 0x10000) >> 16 +} + +// UHCI.DMA_OUT_LINK: Link descriptor address and control +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0xfffff)|value) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0xfffff +} +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x10000000) >> 28 +} +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x20000000) >> 29 +} +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x40000000) >> 30 +} +func (o *UHCI_Type) SetDMA_OUT_LINK_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_LINK.Reg, volatile.LoadUint32(&o.DMA_OUT_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *UHCI_Type) GetDMA_OUT_LINK_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.DMA_OUT_LINK.Reg) & 0x80000000) >> 31 +} + +// UHCI.DMA_IN_LINK: Link descriptor address and control +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0xfffff)|value) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0xfffff +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x100000)|value<<20) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x100000) >> 20 +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x10000000) >> 28 +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_START(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x20000000) >> 29 +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x40000000) >> 30 +} +func (o *UHCI_Type) SetDMA_IN_LINK_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.DMA_IN_LINK.Reg, volatile.LoadUint32(&o.DMA_IN_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *UHCI_Type) GetDMA_IN_LINK_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.DMA_IN_LINK.Reg) & 0x80000000) >> 31 +} + +// UHCI.CONF1: UHCI configuration register +func (o *UHCI_Type) SetCONF1_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF1_CHECK_SUM_EN() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF1_CHECK_SEQ_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF1_CHECK_SEQ_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF1_CRC_DISABLE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF1_CRC_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF1_SAVE_HEAD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF1_SAVE_HEAD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF1_TX_CHECK_SUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF1_TX_CHECK_SUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF1_TX_ACK_NUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF1_TX_ACK_NUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF1_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetCONF1_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetCONF1_WAIT_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF1_WAIT_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF1_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF1_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetCONF1_DMA_INFIFO_FULL_THRS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1ffe00)|value<<9) +} +func (o *UHCI_Type) GetCONF1_DMA_INFIFO_FULL_THRS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x1ffe00) >> 9 +} + +// UHCI.STATE0: UHCI decoder status register +func (o *UHCI_Type) SetSTATE0_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x3ffff)|value) +} +func (o *UHCI_Type) GetSTATE0_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x3ffff +} +func (o *UHCI_Type) SetSTATE0_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0xc0000)|value<<18) +} +func (o *UHCI_Type) GetSTATE0_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0xc0000) >> 18 +} +func (o *UHCI_Type) SetSTATE0_IN_STATE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x700000)|value<<20) +} +func (o *UHCI_Type) GetSTATE0_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x700000) >> 20 +} +func (o *UHCI_Type) SetSTATE0_INFIFO_CNT_DEBUG(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0xf800000)|value<<23) +} +func (o *UHCI_Type) GetSTATE0_INFIFO_CNT_DEBUG() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0xf800000) >> 23 +} +func (o *UHCI_Type) SetSTATE0_DECODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x70000000)|value<<28) +} +func (o *UHCI_Type) GetSTATE0_DECODE_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x70000000) >> 28 +} + +// UHCI.STATE1: UHCI encoder status register +func (o *UHCI_Type) SetSTATE1_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0x3ffff)|value) +} +func (o *UHCI_Type) GetSTATE1_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.STATE1.Reg) & 0x3ffff +} +func (o *UHCI_Type) SetSTATE1_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0xc0000)|value<<18) +} +func (o *UHCI_Type) GetSTATE1_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE1.Reg) & 0xc0000) >> 18 +} +func (o *UHCI_Type) SetSTATE1_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0x700000)|value<<20) +} +func (o *UHCI_Type) GetSTATE1_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE1.Reg) & 0x700000) >> 20 +} +func (o *UHCI_Type) SetSTATE1_OUTFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0xf800000)|value<<23) +} +func (o *UHCI_Type) GetSTATE1_OUTFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATE1.Reg) & 0xf800000) >> 23 +} +func (o *UHCI_Type) SetSTATE1_ENCODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0x70000000)|value<<28) +} +func (o *UHCI_Type) GetSTATE1_ENCODE_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE1.Reg) & 0x70000000) >> 28 +} + +// UHCI.DMA_OUT_EOF_DES_ADDR: Outlink descriptor address when EOF occurs +func (o *UHCI_Type) SetDMA_OUT_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_EOF_DES_ADDR.Reg, value) +} +func (o *UHCI_Type) GetDMA_OUT_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_EOF_DES_ADDR.Reg) +} + +// UHCI.DMA_IN_SUC_EOF_DES_ADDR: Inlink descriptor address when EOF occurs +func (o *UHCI_Type) SetDMA_IN_SUC_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_SUC_EOF_DES_ADDR.Reg, value) +} +func (o *UHCI_Type) GetDMA_IN_SUC_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_SUC_EOF_DES_ADDR.Reg) +} + +// UHCI.DMA_IN_ERR_EOF_DES_ADDR: Inlink descriptor address when errors occur +func (o *UHCI_Type) SetDMA_IN_ERR_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_ERR_EOF_DES_ADDR.Reg, value) +} +func (o *UHCI_Type) GetDMA_IN_ERR_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_ERR_EOF_DES_ADDR.Reg) +} + +// UHCI.DMA_OUT_EOF_BFR_DES_ADDR: Outlink descriptor address before the last transmit descriptor +func (o *UHCI_Type) SetDMA_OUT_EOF_BFR_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_EOF_BFR_DES_ADDR.Reg, value) +} +func (o *UHCI_Type) GetDMA_OUT_EOF_BFR_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_EOF_BFR_DES_ADDR.Reg) +} + +// UHCI.AHB_TEST: AHB test register +func (o *UHCI_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *UHCI_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *UHCI_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// UHCI.DMA_IN_DSCR: The third word of the next receive descriptor +func (o *UHCI_Type) SetDMA_IN_DSCR(value uint32) { + volatile.StoreUint32(&o.DMA_IN_DSCR.Reg, value) +} +func (o *UHCI_Type) GetDMA_IN_DSCR() uint32 { + return volatile.LoadUint32(&o.DMA_IN_DSCR.Reg) +} + +// UHCI.DMA_IN_DSCR_BF0: The third word of current receive descriptor +func (o *UHCI_Type) SetDMA_IN_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.DMA_IN_DSCR_BF0.Reg, value) +} +func (o *UHCI_Type) GetDMA_IN_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.DMA_IN_DSCR_BF0.Reg) +} + +// UHCI.DMA_OUT_DSCR: The third word of the next transmit descriptor +func (o *UHCI_Type) SetDMA_OUT_DSCR(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_DSCR.Reg, value) +} +func (o *UHCI_Type) GetDMA_OUT_DSCR() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_DSCR.Reg) +} + +// UHCI.DMA_OUT_DSCR_BF0: The third word of current transmit descriptor +func (o *UHCI_Type) SetDMA_OUT_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_DSCR_BF0.Reg, value) +} +func (o *UHCI_Type) GetDMA_OUT_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_DSCR_BF0.Reg) +} + +// UHCI.ESCAPE_CONF: Escape character configuration +func (o *UHCI_Type) SetESCAPE_CONF_TX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_C0_ESC_EN() uint32 { + return volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_C0_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x80) >> 7 +} + +// UHCI.HUNG_CONF: Timeout configuration +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff000) >> 12 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700000) >> 20 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800000) >> 23 +} + +// UHCI.RX_HEAD: UHCI packet header register +func (o *UHCI_Type) SetRX_HEAD(value uint32) { + volatile.StoreUint32(&o.RX_HEAD.Reg, value) +} +func (o *UHCI_Type) GetRX_HEAD() uint32 { + return volatile.LoadUint32(&o.RX_HEAD.Reg) +} + +// UHCI.QUICK_SENT: UHCI quick_sent configuration register +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_NUM() uint32 { + return volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x7 +} +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x70)|value<<4) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_NUM() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x70) >> 4 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x80) >> 7 +} + +// UHCI.Q0_WORD0: Q0_WORD0 quick_sent register +func (o *UHCI_Type) SetQ0_WORD0(value uint32) { + volatile.StoreUint32(&o.Q0_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ0_WORD0() uint32 { + return volatile.LoadUint32(&o.Q0_WORD0.Reg) +} + +// UHCI.Q0_WORD1: Q0_WORD1 quick_sent register +func (o *UHCI_Type) SetQ0_WORD1(value uint32) { + volatile.StoreUint32(&o.Q0_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ0_WORD1() uint32 { + return volatile.LoadUint32(&o.Q0_WORD1.Reg) +} + +// UHCI.Q1_WORD0: Q1_WORD0 quick_sent register +func (o *UHCI_Type) SetQ1_WORD0(value uint32) { + volatile.StoreUint32(&o.Q1_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ1_WORD0() uint32 { + return volatile.LoadUint32(&o.Q1_WORD0.Reg) +} + +// UHCI.Q1_WORD1: Q1_WORD1 quick_sent register +func (o *UHCI_Type) SetQ1_WORD1(value uint32) { + volatile.StoreUint32(&o.Q1_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ1_WORD1() uint32 { + return volatile.LoadUint32(&o.Q1_WORD1.Reg) +} + +// UHCI.Q2_WORD0: Q2_WORD0 quick_sent register +func (o *UHCI_Type) SetQ2_WORD0(value uint32) { + volatile.StoreUint32(&o.Q2_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ2_WORD0() uint32 { + return volatile.LoadUint32(&o.Q2_WORD0.Reg) +} + +// UHCI.Q2_WORD1: Q2_WORD1 quick_sent register +func (o *UHCI_Type) SetQ2_WORD1(value uint32) { + volatile.StoreUint32(&o.Q2_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ2_WORD1() uint32 { + return volatile.LoadUint32(&o.Q2_WORD1.Reg) +} + +// UHCI.Q3_WORD0: Q3_WORD0 quick_sent register +func (o *UHCI_Type) SetQ3_WORD0(value uint32) { + volatile.StoreUint32(&o.Q3_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ3_WORD0() uint32 { + return volatile.LoadUint32(&o.Q3_WORD0.Reg) +} + +// UHCI.Q3_WORD1: Q3_WORD1 quick_sent register +func (o *UHCI_Type) SetQ3_WORD1(value uint32) { + volatile.StoreUint32(&o.Q3_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ3_WORD1() uint32 { + return volatile.LoadUint32(&o.Q3_WORD1.Reg) +} + +// UHCI.Q4_WORD0: Q4_WORD0 quick_sent register +func (o *UHCI_Type) SetQ4_WORD0(value uint32) { + volatile.StoreUint32(&o.Q4_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ4_WORD0() uint32 { + return volatile.LoadUint32(&o.Q4_WORD0.Reg) +} + +// UHCI.Q4_WORD1: Q4_WORD1 quick_sent register +func (o *UHCI_Type) SetQ4_WORD1(value uint32) { + volatile.StoreUint32(&o.Q4_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ4_WORD1() uint32 { + return volatile.LoadUint32(&o.Q4_WORD1.Reg) +} + +// UHCI.Q5_WORD0: Q5_WORD0 quick_sent register +func (o *UHCI_Type) SetQ5_WORD0(value uint32) { + volatile.StoreUint32(&o.Q5_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ5_WORD0() uint32 { + return volatile.LoadUint32(&o.Q5_WORD0.Reg) +} + +// UHCI.Q5_WORD1: Q5_WORD1 quick_sent register +func (o *UHCI_Type) SetQ5_WORD1(value uint32) { + volatile.StoreUint32(&o.Q5_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ5_WORD1() uint32 { + return volatile.LoadUint32(&o.Q5_WORD1.Reg) +} + +// UHCI.Q6_WORD0: Q6_WORD0 quick_sent register +func (o *UHCI_Type) SetQ6_WORD0(value uint32) { + volatile.StoreUint32(&o.Q6_WORD0.Reg, value) +} +func (o *UHCI_Type) GetQ6_WORD0() uint32 { + return volatile.LoadUint32(&o.Q6_WORD0.Reg) +} + +// UHCI.Q6_WORD1: Q6_WORD1 quick_sent register +func (o *UHCI_Type) SetQ6_WORD1(value uint32) { + volatile.StoreUint32(&o.Q6_WORD1.Reg, value) +} +func (o *UHCI_Type) GetQ6_WORD1() uint32 { + return volatile.LoadUint32(&o.Q6_WORD1.Reg) +} + +// UHCI.ESC_CONF0: Escape sequence configuration register 0 +func (o *UHCI_Type) SetESC_CONF0_SEPER_CHAR(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_CHAR() uint32 { + return volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF1: Escape sequence configuration register 1 +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0() uint32 { + return volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF2: Escape sequence configuration register 2 +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1() uint32 { + return volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF3: Escape sequence configuration register 3 +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2() uint32 { + return volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff0000) >> 16 +} + +// UHCI.PKT_THRES: Configure register for packet length +func (o *UHCI_Type) SetPKT_THRES_PKT_THRS(value uint32) { + volatile.StoreUint32(&o.PKT_THRES.Reg, volatile.LoadUint32(&o.PKT_THRES.Reg)&^(0x1fff)|value) +} +func (o *UHCI_Type) GetPKT_THRES_PKT_THRS() uint32 { + return volatile.LoadUint32(&o.PKT_THRES.Reg) & 0x1fff +} + +// UHCI.DATE: UHCI version control register +func (o *UHCI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UHCI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// USB OTG (On-The-Go) +type USB_Type struct { + GOTGCTL volatile.Register32 // 0x0 + GOTGINT volatile.Register32 // 0x4 + GAHBCFG volatile.Register32 // 0x8 + GUSBCFG volatile.Register32 // 0xC + GRSTCTL volatile.Register32 // 0x10 + GINTSTS volatile.Register32 // 0x14 + GINTMSK volatile.Register32 // 0x18 + GRXSTSR volatile.Register32 // 0x1C + GRXSTSP volatile.Register32 // 0x20 + GRXFSIZ volatile.Register32 // 0x24 + GNPTXFSIZ volatile.Register32 // 0x28 + GNPTXSTS volatile.Register32 // 0x2C + _ [16]byte + GSNPSID volatile.Register32 // 0x40 + GHWCFG1 volatile.Register32 // 0x44 + GHWCFG2 volatile.Register32 // 0x48 + GHWCFG3 volatile.Register32 // 0x4C + GHWCFG4 volatile.Register32 // 0x50 + _ [8]byte + GDFIFOCFG volatile.Register32 // 0x5C + _ [160]byte + HPTXFSIZ volatile.Register32 // 0x100 + DIEPTXF1 volatile.Register32 // 0x104 + DIEPTXF2 volatile.Register32 // 0x108 + DIEPTXF3 volatile.Register32 // 0x10C + DIEPTXF4 volatile.Register32 // 0x110 + _ [748]byte + HCFG volatile.Register32 // 0x400 + HFIR volatile.Register32 // 0x404 + HFNUM volatile.Register32 // 0x408 + _ [4]byte + HPTXSTS volatile.Register32 // 0x410 + HAINT volatile.Register32 // 0x414 + HAINTMSK volatile.Register32 // 0x418 + HFLBADDR volatile.Register32 // 0x41C + _ [32]byte + HPRT volatile.Register32 // 0x440 + _ [188]byte + HCCHAR0 volatile.Register32 // 0x500 + _ [4]byte + HCINT0 volatile.Register32 // 0x508 + HCINTMSK0 volatile.Register32 // 0x50C + HCTSIZ0 volatile.Register32 // 0x510 + HCDMA0 volatile.Register32 // 0x514 + _ [4]byte + HCDMAB0 volatile.Register32 // 0x51C + HCCHAR1 volatile.Register32 // 0x520 + _ [4]byte + HCINT1 volatile.Register32 // 0x528 + HCINTMSK1 volatile.Register32 // 0x52C + HCTSIZ1 volatile.Register32 // 0x530 + HCDMA1 volatile.Register32 // 0x534 + _ [4]byte + HCDMAB1 volatile.Register32 // 0x53C + HCCHAR2 volatile.Register32 // 0x540 + _ [4]byte + HCINT2 volatile.Register32 // 0x548 + HCINTMSK2 volatile.Register32 // 0x54C + HCTSIZ2 volatile.Register32 // 0x550 + HCDMA2 volatile.Register32 // 0x554 + _ [4]byte + HCDMAB2 volatile.Register32 // 0x55C + HCCHAR3 volatile.Register32 // 0x560 + _ [4]byte + HCINT3 volatile.Register32 // 0x568 + HCINTMSK3 volatile.Register32 // 0x56C + HCTSIZ3 volatile.Register32 // 0x570 + HCDMA3 volatile.Register32 // 0x574 + _ [4]byte + HCDMAB3 volatile.Register32 // 0x57C + HCCHAR4 volatile.Register32 // 0x580 + _ [4]byte + HCINT4 volatile.Register32 // 0x588 + HCINTMSK4 volatile.Register32 // 0x58C + HCTSIZ4 volatile.Register32 // 0x590 + HCDMA4 volatile.Register32 // 0x594 + _ [4]byte + HCDMAB4 volatile.Register32 // 0x59C + HCCHAR5 volatile.Register32 // 0x5A0 + _ [4]byte + HCINT5 volatile.Register32 // 0x5A8 + HCINTMSK5 volatile.Register32 // 0x5AC + HCTSIZ5 volatile.Register32 // 0x5B0 + HCDMA5 volatile.Register32 // 0x5B4 + _ [4]byte + HCDMAB5 volatile.Register32 // 0x5BC + HCCHAR6 volatile.Register32 // 0x5C0 + _ [4]byte + HCINT6 volatile.Register32 // 0x5C8 + HCINTMSK6 volatile.Register32 // 0x5CC + HCTSIZ6 volatile.Register32 // 0x5D0 + HCDMA6 volatile.Register32 // 0x5D4 + _ [4]byte + HCDMAB6 volatile.Register32 // 0x5DC + HCCHAR7 volatile.Register32 // 0x5E0 + _ [4]byte + HCINT7 volatile.Register32 // 0x5E8 + HCINTMSK7 volatile.Register32 // 0x5EC + HCTSIZ7 volatile.Register32 // 0x5F0 + HCDMA7 volatile.Register32 // 0x5F4 + _ [4]byte + HCDMAB7 volatile.Register32 // 0x5FC + _ [512]byte + DCFG volatile.Register32 // 0x800 + DCTL volatile.Register32 // 0x804 + DSTS volatile.Register32 // 0x808 + _ [4]byte + DIEPMSK volatile.Register32 // 0x810 + DOEPMSK volatile.Register32 // 0x814 + DAINT volatile.Register32 // 0x818 + DAINTMSK volatile.Register32 // 0x81C + _ [8]byte + DVBUSDIS volatile.Register32 // 0x828 + DVBUSPULSE volatile.Register32 // 0x82C + DTHRCTL volatile.Register32 // 0x830 + DIEPEMPMSK volatile.Register32 // 0x834 + _ [200]byte + DIEPCTL0 volatile.Register32 // 0x900 + _ [4]byte + DIEPINT0 volatile.Register32 // 0x908 + _ [4]byte + DIEPTSIZ0 volatile.Register32 // 0x910 + DIEPDMA0 volatile.Register32 // 0x914 + DTXFSTS0 volatile.Register32 // 0x918 + DIEPDMAB0 volatile.Register32 // 0x91C + DIEPCTL1 volatile.Register32 // 0x920 + _ [4]byte + DIEPINT1 volatile.Register32 // 0x928 + _ [4]byte + DIEPTSIZ1 volatile.Register32 // 0x930 + DIEPDMA1 volatile.Register32 // 0x934 + DTXFSTS1 volatile.Register32 // 0x938 + DIEPDMAB1 volatile.Register32 // 0x93C + DIEPCTL2 volatile.Register32 // 0x940 + _ [4]byte + DIEPINT2 volatile.Register32 // 0x948 + _ [4]byte + DIEPTSIZ2 volatile.Register32 // 0x950 + DIEPDMA2 volatile.Register32 // 0x954 + DTXFSTS2 volatile.Register32 // 0x958 + DIEPDMAB2 volatile.Register32 // 0x95C + DIEPCTL3 volatile.Register32 // 0x960 + _ [4]byte + DIEPINT3 volatile.Register32 // 0x968 + _ [4]byte + DIEPTSIZ3 volatile.Register32 // 0x970 + DIEPDMA3 volatile.Register32 // 0x974 + DTXFSTS3 volatile.Register32 // 0x978 + DIEPDMAB3 volatile.Register32 // 0x97C + DIEPCTL4 volatile.Register32 // 0x980 + _ [4]byte + DIEPINT4 volatile.Register32 // 0x988 + _ [4]byte + DIEPTSIZ4 volatile.Register32 // 0x990 + DIEPDMA4 volatile.Register32 // 0x994 + DTXFSTS4 volatile.Register32 // 0x998 + DIEPDMAB4 volatile.Register32 // 0x99C + DIEPCTL5 volatile.Register32 // 0x9A0 + _ [4]byte + DIEPINT5 volatile.Register32 // 0x9A8 + _ [4]byte + DIEPTSIZ5 volatile.Register32 // 0x9B0 + DIEPDMA5 volatile.Register32 // 0x9B4 + DTXFSTS5 volatile.Register32 // 0x9B8 + DIEPDMAB5 volatile.Register32 // 0x9BC + DIEPCTL6 volatile.Register32 // 0x9C0 + _ [4]byte + DIEPINT6 volatile.Register32 // 0x9C8 + _ [4]byte + DIEPTSIZ6 volatile.Register32 // 0x9D0 + DIEPDMA6 volatile.Register32 // 0x9D4 + DTXFSTS6 volatile.Register32 // 0x9D8 + DIEPDMAB6 volatile.Register32 // 0x9DC + _ [288]byte + DOEPCTL0 volatile.Register32 // 0xB00 + _ [4]byte + DOEPINT0 volatile.Register32 // 0xB08 + _ [4]byte + DOEPTSIZ0 volatile.Register32 // 0xB10 + DOEPDMA0 volatile.Register32 // 0xB14 + _ [4]byte + DOEPDMAB0 volatile.Register32 // 0xB1C + DOEPCTL1 volatile.Register32 // 0xB20 + _ [4]byte + DOEPINT1 volatile.Register32 // 0xB28 + _ [4]byte + DOEPTSIZ1 volatile.Register32 // 0xB30 + DOEPDMA1 volatile.Register32 // 0xB34 + _ [4]byte + DOEPDMAB1 volatile.Register32 // 0xB3C + DOEPCTL2 volatile.Register32 // 0xB40 + _ [4]byte + DOEPINT2 volatile.Register32 // 0xB48 + _ [4]byte + DOEPTSIZ2 volatile.Register32 // 0xB50 + DOEPDMA2 volatile.Register32 // 0xB54 + _ [4]byte + DOEPDMAB2 volatile.Register32 // 0xB5C + DOEPCTL3 volatile.Register32 // 0xB60 + _ [4]byte + DOEPINT3 volatile.Register32 // 0xB68 + _ [4]byte + DOEPTSIZ3 volatile.Register32 // 0xB70 + DOEPDMA3 volatile.Register32 // 0xB74 + _ [4]byte + DOEPDMAB3 volatile.Register32 // 0xB7C + DOEPCTL4 volatile.Register32 // 0xB80 + _ [4]byte + DOEPINT4 volatile.Register32 // 0xB88 + _ [4]byte + DOEPTSIZ4 volatile.Register32 // 0xB90 + DOEPDMA4 volatile.Register32 // 0xB94 + _ [4]byte + DOEPDMAB4 volatile.Register32 // 0xB9C + DOEPCTL5 volatile.Register32 // 0xBA0 + _ [4]byte + DOEPINT5 volatile.Register32 // 0xBA8 + _ [4]byte + DOEPTSIZ5 volatile.Register32 // 0xBB0 + DOEPDMA5 volatile.Register32 // 0xBB4 + _ [4]byte + DOEPDMAB5 volatile.Register32 // 0xBBC + DOEPCTL6 volatile.Register32 // 0xBC0 + _ [4]byte + DOEPINT6 volatile.Register32 // 0xBC8 + _ [4]byte + DOEPTSIZ6 volatile.Register32 // 0xBD0 + DOEPDMA6 volatile.Register32 // 0xBD4 + _ [4]byte + DOEPDMAB6 volatile.Register32 // 0xBDC + _ [544]byte + PCGCCTL volatile.Register32 // 0xE00 +} + +// USB.GOTGCTL +func (o *USB_Type) SetGOTGCTL_SESREQSCS(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetGOTGCTL_SESREQSCS() uint32 { + return volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x1 +} +func (o *USB_Type) SetGOTGCTL_SESREQ(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetGOTGCTL_SESREQ() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetGOTGCTL_VBVALIDOVEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGOTGCTL_VBVALIDOVEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGOTGCTL_VBVALIDOVVAL(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetGOTGCTL_VBVALIDOVVAL() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetGOTGCTL_AVALIDOVEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGOTGCTL_AVALIDOVEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGOTGCTL_AVALIDOVVAL(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGOTGCTL_AVALIDOVVAL() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGOTGCTL_BVALIDOVEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGOTGCTL_BVALIDOVEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGOTGCTL_BVALIDOVVAL(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGOTGCTL_BVALIDOVVAL() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGOTGCTL_HSTNEGSCS(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGOTGCTL_HSTNEGSCS() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGOTGCTL_HNPREQ(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetGOTGCTL_HNPREQ() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetGOTGCTL_HSTSETHNPEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetGOTGCTL_HSTSETHNPEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetGOTGCTL_DEVHNPEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetGOTGCTL_DEVHNPEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetGOTGCTL_EHEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGOTGCTL_EHEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGOTGCTL_DBNCEFLTRBYPASS(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetGOTGCTL_DBNCEFLTRBYPASS() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetGOTGCTL_CONIDSTS(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetGOTGCTL_CONIDSTS() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetGOTGCTL_DBNCTIME(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetGOTGCTL_DBNCTIME() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetGOTGCTL_ASESVLD(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGOTGCTL_ASESVLD() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGOTGCTL_BSESVLD(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGOTGCTL_BSESVLD() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetGOTGCTL_OTGVER(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGOTGCTL_OTGVER() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGOTGCTL_CURMOD(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGOTGCTL_CURMOD() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x200000) >> 21 +} + +// USB.GOTGINT +func (o *USB_Type) SetGOTGINT_SESENDDET(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGOTGINT_SESENDDET() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGOTGINT_SESREQSUCSTSCHNG(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGOTGINT_SESREQSUCSTSCHNG() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGOTGINT_HSTNEGSUCSTSCHNG(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetGOTGINT_HSTNEGSUCSTSCHNG() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetGOTGINT_HSTNEGDET(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetGOTGINT_HSTNEGDET() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetGOTGINT_ADEVTOUTCHG(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGOTGINT_ADEVTOUTCHG() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGOTGINT_DBNCEDONE(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGOTGINT_DBNCEDONE() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x80000) >> 19 +} + +// USB.GAHBCFG +func (o *USB_Type) SetGAHBCFG_GLBLLNTRMSK(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetGAHBCFG_GLBLLNTRMSK() uint32 { + return volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x1 +} +func (o *USB_Type) SetGAHBCFG_HBSTLEN(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x1e)|value<<1) +} +func (o *USB_Type) GetGAHBCFG_HBSTLEN() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x1e) >> 1 +} +func (o *USB_Type) SetGAHBCFG_DMAEN(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGAHBCFG_DMAEN() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGAHBCFG_NPTXFEMPLVL(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGAHBCFG_NPTXFEMPLVL() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGAHBCFG_PTXFEMPLVL(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGAHBCFG_PTXFEMPLVL() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGAHBCFG_REMMEMSUPP(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGAHBCFG_REMMEMSUPP() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetGAHBCFG_NOTIALLDMAWRIT(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGAHBCFG_NOTIALLDMAWRIT() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGAHBCFG_AHBSINGLE(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetGAHBCFG_AHBSINGLE() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetGAHBCFG_INVDESCENDIANESS(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x1000000)|value<<24) +} +func (o *USB_Type) GetGAHBCFG_INVDESCENDIANESS() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x1000000) >> 24 +} + +// USB.GUSBCFG +func (o *USB_Type) SetGUSBCFG_TOUTCAL(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x7)|value) +} +func (o *USB_Type) GetGUSBCFG_TOUTCAL() uint32 { + return volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x7 +} +func (o *USB_Type) SetGUSBCFG_PHYIF(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetGUSBCFG_PHYIF() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetGUSBCFG_ULPI_UTMI_SEL(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGUSBCFG_ULPI_UTMI_SEL() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGUSBCFG_FSINTF(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGUSBCFG_FSINTF() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGUSBCFG_PHYSEL(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGUSBCFG_PHYSEL() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGUSBCFG_SRPCAP(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGUSBCFG_SRPCAP() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGUSBCFG_HNPCAP(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetGUSBCFG_HNPCAP() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetGUSBCFG_USBTRDTIM(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x3c00)|value<<10) +} +func (o *USB_Type) GetGUSBCFG_USBTRDTIM() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x3c00) >> 10 +} +func (o *USB_Type) SetGUSBCFG_TERMSELDLPULSE(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGUSBCFG_TERMSELDLPULSE() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGUSBCFG_TXENDDELAY(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetGUSBCFG_TXENDDELAY() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetGUSBCFG_FORCEHSTMODE(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetGUSBCFG_FORCEHSTMODE() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetGUSBCFG_FORCEDEVMODE(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGUSBCFG_FORCEDEVMODE() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGUSBCFG_CORRUPTTXPKT(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGUSBCFG_CORRUPTTXPKT() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x80000000) >> 31 +} + +// USB.GRSTCTL +func (o *USB_Type) SetGRSTCTL_CSFTRST(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetGRSTCTL_CSFTRST() uint32 { + return volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x1 +} +func (o *USB_Type) SetGRSTCTL_PIUFSSFTRST(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetGRSTCTL_PIUFSSFTRST() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetGRSTCTL_FRMCNTRRST(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGRSTCTL_FRMCNTRRST() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGRSTCTL_RXFFLSH(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGRSTCTL_RXFFLSH() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGRSTCTL_TXFFLSH(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGRSTCTL_TXFFLSH() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGRSTCTL_TXFNUM(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x7c0)|value<<6) +} +func (o *USB_Type) GetGRSTCTL_TXFNUM() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x7c0) >> 6 +} +func (o *USB_Type) SetGRSTCTL_DMAREQ(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGRSTCTL_DMAREQ() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGRSTCTL_AHBIDLE(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGRSTCTL_AHBIDLE() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x80000000) >> 31 +} + +// USB.GINTSTS +func (o *USB_Type) SetGINTSTS_CURMOD_INT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetGINTSTS_CURMOD_INT() uint32 { + return volatile.LoadUint32(&o.GINTSTS.Reg) & 0x1 +} +func (o *USB_Type) SetGINTSTS_MODEMIS(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetGINTSTS_MODEMIS() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetGINTSTS_OTGINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGINTSTS_OTGINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGINTSTS_SOF(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetGINTSTS_SOF() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetGINTSTS_RXFLVI(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGINTSTS_RXFLVI() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGINTSTS_NPTXFEMP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGINTSTS_NPTXFEMP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGINTSTS_GINNAKEFF(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGINTSTS_GINNAKEFF() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGINTSTS_GOUTNAKEFF(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGINTSTS_GOUTNAKEFF() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGINTSTS_ERLYSUSP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetGINTSTS_ERLYSUSP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetGINTSTS_USBSUSP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetGINTSTS_USBSUSP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetGINTSTS_USBRST(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGINTSTS_USBRST() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGINTSTS_ENUMDONE(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetGINTSTS_ENUMDONE() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetGINTSTS_ISOOUTDROP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetGINTSTS_ISOOUTDROP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetGINTSTS_EOPF(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetGINTSTS_EOPF() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetGINTSTS_EPMIS(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetGINTSTS_EPMIS() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetGINTSTS_IEPINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGINTSTS_IEPINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGINTSTS_OEPINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGINTSTS_OEPINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetGINTSTS_INCOMPISOIN(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGINTSTS_INCOMPISOIN() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGINTSTS_INCOMPIP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGINTSTS_INCOMPIP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetGINTSTS_FETSUSP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGINTSTS_FETSUSP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGINTSTS_RESETDET(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetGINTSTS_RESETDET() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetGINTSTS_PRTLNT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x1000000)|value<<24) +} +func (o *USB_Type) GetGINTSTS_PRTLNT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x1000000) >> 24 +} +func (o *USB_Type) SetGINTSTS_HCHLNT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x2000000)|value<<25) +} +func (o *USB_Type) GetGINTSTS_HCHLNT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x2000000) >> 25 +} +func (o *USB_Type) SetGINTSTS_PTXFEMP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetGINTSTS_PTXFEMP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetGINTSTS_CONIDSTSCHNG(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetGINTSTS_CONIDSTSCHNG() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetGINTSTS_DISCONNINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetGINTSTS_DISCONNINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetGINTSTS_SESSREQINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGINTSTS_SESSREQINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGINTSTS_WKUPINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGINTSTS_WKUPINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x80000000) >> 31 +} + +// USB.GINTMSK +func (o *USB_Type) SetGINTMSK_MODEMISMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetGINTMSK_MODEMISMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetGINTMSK_OTGINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGINTMSK_OTGINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGINTMSK_SOFMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetGINTMSK_SOFMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetGINTMSK_RXFLVIMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGINTMSK_RXFLVIMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGINTMSK_NPTXFEMPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGINTMSK_NPTXFEMPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGINTMSK_GINNAKEFFMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGINTMSK_GINNAKEFFMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGINTMSK_GOUTNACKEFFMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGINTMSK_GOUTNACKEFFMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGINTMSK_ERLYSUSPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetGINTMSK_ERLYSUSPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetGINTMSK_USBSUSPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetGINTMSK_USBSUSPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetGINTMSK_USBRSTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGINTMSK_USBRSTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGINTMSK_ENUMDONEMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetGINTMSK_ENUMDONEMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetGINTMSK_ISOOUTDROPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetGINTMSK_ISOOUTDROPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetGINTMSK_EOPFMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetGINTMSK_EOPFMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetGINTMSK_EPMISMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetGINTMSK_EPMISMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetGINTMSK_IEPINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGINTMSK_IEPINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGINTMSK_OEPINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGINTMSK_OEPINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetGINTMSK_INCOMPISOINMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGINTMSK_INCOMPISOINMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGINTMSK_INCOMPIPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGINTMSK_INCOMPIPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetGINTMSK_FETSUSPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGINTMSK_FETSUSPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGINTMSK_RESETDETMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetGINTMSK_RESETDETMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetGINTMSK_PRTLNTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x1000000)|value<<24) +} +func (o *USB_Type) GetGINTMSK_PRTLNTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x1000000) >> 24 +} +func (o *USB_Type) SetGINTMSK_HCHINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x2000000)|value<<25) +} +func (o *USB_Type) GetGINTMSK_HCHINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x2000000) >> 25 +} +func (o *USB_Type) SetGINTMSK_PTXFEMPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetGINTMSK_PTXFEMPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetGINTMSK_CONIDSTSCHNGMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetGINTMSK_CONIDSTSCHNGMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetGINTMSK_DISCONNINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetGINTMSK_DISCONNINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetGINTMSK_SESSREQINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGINTMSK_SESSREQINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGINTMSK_WKUPINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGINTMSK_WKUPINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x80000000) >> 31 +} + +// USB.GRXSTSR +func (o *USB_Type) SetGRXSTSR_G_CHNUM(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0xf)|value) +} +func (o *USB_Type) GetGRXSTSR_G_CHNUM() uint32 { + return volatile.LoadUint32(&o.GRXSTSR.Reg) & 0xf +} +func (o *USB_Type) SetGRXSTSR_G_BCNT(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0x7ff0)|value<<4) +} +func (o *USB_Type) GetGRXSTSR_G_BCNT() uint32 { + return (volatile.LoadUint32(&o.GRXSTSR.Reg) & 0x7ff0) >> 4 +} +func (o *USB_Type) SetGRXSTSR_G_DPID(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0x18000)|value<<15) +} +func (o *USB_Type) GetGRXSTSR_G_DPID() uint32 { + return (volatile.LoadUint32(&o.GRXSTSR.Reg) & 0x18000) >> 15 +} +func (o *USB_Type) SetGRXSTSR_G_PKTSTS(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0x1e0000)|value<<17) +} +func (o *USB_Type) GetGRXSTSR_G_PKTSTS() uint32 { + return (volatile.LoadUint32(&o.GRXSTSR.Reg) & 0x1e0000) >> 17 +} +func (o *USB_Type) SetGRXSTSR_G_FN(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0x1e00000)|value<<21) +} +func (o *USB_Type) GetGRXSTSR_G_FN() uint32 { + return (volatile.LoadUint32(&o.GRXSTSR.Reg) & 0x1e00000) >> 21 +} + +// USB.GRXSTSP +func (o *USB_Type) SetGRXSTSP_CHNUM(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0xf)|value) +} +func (o *USB_Type) GetGRXSTSP_CHNUM() uint32 { + return volatile.LoadUint32(&o.GRXSTSP.Reg) & 0xf +} +func (o *USB_Type) SetGRXSTSP_BCNT(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0x7ff0)|value<<4) +} +func (o *USB_Type) GetGRXSTSP_BCNT() uint32 { + return (volatile.LoadUint32(&o.GRXSTSP.Reg) & 0x7ff0) >> 4 +} +func (o *USB_Type) SetGRXSTSP_DPID(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0x18000)|value<<15) +} +func (o *USB_Type) GetGRXSTSP_DPID() uint32 { + return (volatile.LoadUint32(&o.GRXSTSP.Reg) & 0x18000) >> 15 +} +func (o *USB_Type) SetGRXSTSP_PKTSTS(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0x1e0000)|value<<17) +} +func (o *USB_Type) GetGRXSTSP_PKTSTS() uint32 { + return (volatile.LoadUint32(&o.GRXSTSP.Reg) & 0x1e0000) >> 17 +} +func (o *USB_Type) SetGRXSTSP_FN(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0x1e00000)|value<<21) +} +func (o *USB_Type) GetGRXSTSP_FN() uint32 { + return (volatile.LoadUint32(&o.GRXSTSP.Reg) & 0x1e00000) >> 21 +} + +// USB.GRXFSIZ +func (o *USB_Type) SetGRXFSIZ_RXFDEP(value uint32) { + volatile.StoreUint32(&o.GRXFSIZ.Reg, volatile.LoadUint32(&o.GRXFSIZ.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetGRXFSIZ_RXFDEP() uint32 { + return volatile.LoadUint32(&o.GRXFSIZ.Reg) & 0xffff +} + +// USB.GNPTXFSIZ +func (o *USB_Type) SetGNPTXFSIZ_NPTXFSTADDR(value uint32) { + volatile.StoreUint32(&o.GNPTXFSIZ.Reg, volatile.LoadUint32(&o.GNPTXFSIZ.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetGNPTXFSIZ_NPTXFSTADDR() uint32 { + return volatile.LoadUint32(&o.GNPTXFSIZ.Reg) & 0xffff +} +func (o *USB_Type) SetGNPTXFSIZ_NPTXFDEP(value uint32) { + volatile.StoreUint32(&o.GNPTXFSIZ.Reg, volatile.LoadUint32(&o.GNPTXFSIZ.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetGNPTXFSIZ_NPTXFDEP() uint32 { + return (volatile.LoadUint32(&o.GNPTXFSIZ.Reg) & 0xffff0000) >> 16 +} + +// USB.GNPTXSTS +func (o *USB_Type) SetGNPTXSTS_NPTXFSPCAVAIL(value uint32) { + volatile.StoreUint32(&o.GNPTXSTS.Reg, volatile.LoadUint32(&o.GNPTXSTS.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetGNPTXSTS_NPTXFSPCAVAIL() uint32 { + return volatile.LoadUint32(&o.GNPTXSTS.Reg) & 0xffff +} +func (o *USB_Type) SetGNPTXSTS_NPTXQSPCAVAIL(value uint32) { + volatile.StoreUint32(&o.GNPTXSTS.Reg, volatile.LoadUint32(&o.GNPTXSTS.Reg)&^(0xf0000)|value<<16) +} +func (o *USB_Type) GetGNPTXSTS_NPTXQSPCAVAIL() uint32 { + return (volatile.LoadUint32(&o.GNPTXSTS.Reg) & 0xf0000) >> 16 +} +func (o *USB_Type) SetGNPTXSTS_NPTXQTOP(value uint32) { + volatile.StoreUint32(&o.GNPTXSTS.Reg, volatile.LoadUint32(&o.GNPTXSTS.Reg)&^(0x7f000000)|value<<24) +} +func (o *USB_Type) GetGNPTXSTS_NPTXQTOP() uint32 { + return (volatile.LoadUint32(&o.GNPTXSTS.Reg) & 0x7f000000) >> 24 +} + +// USB.GSNPSID +func (o *USB_Type) SetGSNPSID(value uint32) { + volatile.StoreUint32(&o.GSNPSID.Reg, value) +} +func (o *USB_Type) GetGSNPSID() uint32 { + return volatile.LoadUint32(&o.GSNPSID.Reg) +} + +// USB.GHWCFG1 +func (o *USB_Type) SetGHWCFG1(value uint32) { + volatile.StoreUint32(&o.GHWCFG1.Reg, value) +} +func (o *USB_Type) GetGHWCFG1() uint32 { + return volatile.LoadUint32(&o.GHWCFG1.Reg) +} + +// USB.GHWCFG2 +func (o *USB_Type) SetGHWCFG2_OTGMODE(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x7)|value) +} +func (o *USB_Type) GetGHWCFG2_OTGMODE() uint32 { + return volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x7 +} +func (o *USB_Type) SetGHWCFG2_OTGARCH(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x18)|value<<3) +} +func (o *USB_Type) GetGHWCFG2_OTGARCH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x18) >> 3 +} +func (o *USB_Type) SetGHWCFG2_SINGPNT(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGHWCFG2_SINGPNT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGHWCFG2_HSPHYTYPE(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0xc0)|value<<6) +} +func (o *USB_Type) GetGHWCFG2_HSPHYTYPE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0xc0) >> 6 +} +func (o *USB_Type) SetGHWCFG2_FSPHYTYPE(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x300)|value<<8) +} +func (o *USB_Type) GetGHWCFG2_FSPHYTYPE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x300) >> 8 +} +func (o *USB_Type) SetGHWCFG2_NUMDEVEPS(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x3c00)|value<<10) +} +func (o *USB_Type) GetGHWCFG2_NUMDEVEPS() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x3c00) >> 10 +} +func (o *USB_Type) SetGHWCFG2_NUMHSTCHNL(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x3c000)|value<<14) +} +func (o *USB_Type) GetGHWCFG2_NUMHSTCHNL() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x3c000) >> 14 +} +func (o *USB_Type) SetGHWCFG2_PERIOSUPPORT(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGHWCFG2_PERIOSUPPORT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGHWCFG2_DYNFIFOSIZING(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGHWCFG2_DYNFIFOSIZING() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetGHWCFG2_MULTIPROCINTRPT(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGHWCFG2_MULTIPROCINTRPT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGHWCFG2_NPTXQDEPTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0xc00000)|value<<22) +} +func (o *USB_Type) GetGHWCFG2_NPTXQDEPTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0xc00000) >> 22 +} +func (o *USB_Type) SetGHWCFG2_PTXQDEPTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x3000000)|value<<24) +} +func (o *USB_Type) GetGHWCFG2_PTXQDEPTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x3000000) >> 24 +} +func (o *USB_Type) SetGHWCFG2_TKNQDEPTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x7c000000)|value<<26) +} +func (o *USB_Type) GetGHWCFG2_TKNQDEPTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x7c000000) >> 26 +} +func (o *USB_Type) SetGHWCFG2_OTG_ENABLE_IC_USB(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGHWCFG2_OTG_ENABLE_IC_USB() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x80000000) >> 31 +} + +// USB.GHWCFG3 +func (o *USB_Type) SetGHWCFG3_XFERSIZEWIDTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0xf)|value) +} +func (o *USB_Type) GetGHWCFG3_XFERSIZEWIDTH() uint32 { + return volatile.LoadUint32(&o.GHWCFG3.Reg) & 0xf +} +func (o *USB_Type) SetGHWCFG3_PKTSIZEWIDTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x70)|value<<4) +} +func (o *USB_Type) GetGHWCFG3_PKTSIZEWIDTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x70) >> 4 +} +func (o *USB_Type) SetGHWCFG3_OTGEN(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGHWCFG3_OTGEN() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGHWCFG3_I2CINTSEL(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGHWCFG3_I2CINTSEL() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGHWCFG3_VNDCTLSUPT(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetGHWCFG3_VNDCTLSUPT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetGHWCFG3_OPTFEATURE(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetGHWCFG3_OPTFEATURE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetGHWCFG3_RSTTYPE(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetGHWCFG3_RSTTYPE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetGHWCFG3_ADPSUPPORT(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGHWCFG3_ADPSUPPORT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGHWCFG3_HSICMODE(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetGHWCFG3_HSICMODE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetGHWCFG3_BCSUPPORT(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetGHWCFG3_BCSUPPORT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetGHWCFG3_LPMMODE(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetGHWCFG3_LPMMODE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetGHWCFG3_DFIFODEPTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetGHWCFG3_DFIFODEPTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0xffff0000) >> 16 +} + +// USB.GHWCFG4 +func (o *USB_Type) SetGHWCFG4_G_NUMDEVPERIOEPS(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0xf)|value) +} +func (o *USB_Type) GetGHWCFG4_G_NUMDEVPERIOEPS() uint32 { + return volatile.LoadUint32(&o.GHWCFG4.Reg) & 0xf +} +func (o *USB_Type) SetGHWCFG4_G_PARTIALPWRDN(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGHWCFG4_G_PARTIALPWRDN() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGHWCFG4_G_AHBFREQ(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGHWCFG4_G_AHBFREQ() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGHWCFG4_G_HIBERNATION(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGHWCFG4_G_HIBERNATION() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGHWCFG4_G_EXTENDEDHIBERNATION(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGHWCFG4_G_EXTENDEDHIBERNATION() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGHWCFG4_G_ACGSUPT(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGHWCFG4_G_ACGSUPT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGHWCFG4_G_ENHANCEDLPMSUPT(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetGHWCFG4_G_ENHANCEDLPMSUPT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetGHWCFG4_G_PHYDATAWIDTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0xc000)|value<<14) +} +func (o *USB_Type) GetGHWCFG4_G_PHYDATAWIDTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0xc000) >> 14 +} +func (o *USB_Type) SetGHWCFG4_G_NUMCTLEPS(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0xf0000)|value<<16) +} +func (o *USB_Type) GetGHWCFG4_G_NUMCTLEPS() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0xf0000) >> 16 +} +func (o *USB_Type) SetGHWCFG4_G_IDDQFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGHWCFG4_G_IDDQFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGHWCFG4_G_VBUSVALIDFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGHWCFG4_G_VBUSVALIDFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetGHWCFG4_G_AVALIDFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGHWCFG4_G_AVALIDFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGHWCFG4_G_BVALIDFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetGHWCFG4_G_BVALIDFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetGHWCFG4_G_SESSENDFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x1000000)|value<<24) +} +func (o *USB_Type) GetGHWCFG4_G_SESSENDFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x1000000) >> 24 +} +func (o *USB_Type) SetGHWCFG4_G_DEDFIFOMODE(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x2000000)|value<<25) +} +func (o *USB_Type) GetGHWCFG4_G_DEDFIFOMODE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x2000000) >> 25 +} +func (o *USB_Type) SetGHWCFG4_G_INEPS(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x3c000000)|value<<26) +} +func (o *USB_Type) GetGHWCFG4_G_INEPS() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x3c000000) >> 26 +} +func (o *USB_Type) SetGHWCFG4_G_DESCDMAENABLED(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGHWCFG4_G_DESCDMAENABLED() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGHWCFG4_G_DESCDMA(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGHWCFG4_G_DESCDMA() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x80000000) >> 31 +} + +// USB.GDFIFOCFG +func (o *USB_Type) SetGDFIFOCFG(value uint32) { + volatile.StoreUint32(&o.GDFIFOCFG.Reg, volatile.LoadUint32(&o.GDFIFOCFG.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetGDFIFOCFG() uint32 { + return volatile.LoadUint32(&o.GDFIFOCFG.Reg) & 0xffff +} +func (o *USB_Type) SetGDFIFOCFG_EPINFOBASEADDR(value uint32) { + volatile.StoreUint32(&o.GDFIFOCFG.Reg, volatile.LoadUint32(&o.GDFIFOCFG.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetGDFIFOCFG_EPINFOBASEADDR() uint32 { + return (volatile.LoadUint32(&o.GDFIFOCFG.Reg) & 0xffff0000) >> 16 +} + +// USB.HPTXFSIZ +func (o *USB_Type) SetHPTXFSIZ_PTXFSTADDR(value uint32) { + volatile.StoreUint32(&o.HPTXFSIZ.Reg, volatile.LoadUint32(&o.HPTXFSIZ.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetHPTXFSIZ_PTXFSTADDR() uint32 { + return volatile.LoadUint32(&o.HPTXFSIZ.Reg) & 0xffff +} +func (o *USB_Type) SetHPTXFSIZ_PTXFSIZE(value uint32) { + volatile.StoreUint32(&o.HPTXFSIZ.Reg, volatile.LoadUint32(&o.HPTXFSIZ.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetHPTXFSIZ_PTXFSIZE() uint32 { + return (volatile.LoadUint32(&o.HPTXFSIZ.Reg) & 0xffff0000) >> 16 +} + +// USB.DIEPTXF1 +func (o *USB_Type) SetDIEPTXF1_INEP1TXFSTADDR(value uint32) { + volatile.StoreUint32(&o.DIEPTXF1.Reg, volatile.LoadUint32(&o.DIEPTXF1.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPTXF1_INEP1TXFSTADDR() uint32 { + return volatile.LoadUint32(&o.DIEPTXF1.Reg) & 0xffff +} +func (o *USB_Type) SetDIEPTXF1_INEP1TXFDEP(value uint32) { + volatile.StoreUint32(&o.DIEPTXF1.Reg, volatile.LoadUint32(&o.DIEPTXF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetDIEPTXF1_INEP1TXFDEP() uint32 { + return (volatile.LoadUint32(&o.DIEPTXF1.Reg) & 0xffff0000) >> 16 +} + +// USB.DIEPTXF2 +func (o *USB_Type) SetDIEPTXF2_INEP2TXFSTADDR(value uint32) { + volatile.StoreUint32(&o.DIEPTXF2.Reg, volatile.LoadUint32(&o.DIEPTXF2.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPTXF2_INEP2TXFSTADDR() uint32 { + return volatile.LoadUint32(&o.DIEPTXF2.Reg) & 0xffff +} +func (o *USB_Type) SetDIEPTXF2_INEP2TXFDEP(value uint32) { + volatile.StoreUint32(&o.DIEPTXF2.Reg, volatile.LoadUint32(&o.DIEPTXF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetDIEPTXF2_INEP2TXFDEP() uint32 { + return (volatile.LoadUint32(&o.DIEPTXF2.Reg) & 0xffff0000) >> 16 +} + +// USB.DIEPTXF3 +func (o *USB_Type) SetDIEPTXF3_INEP3TXFSTADDR(value uint32) { + volatile.StoreUint32(&o.DIEPTXF3.Reg, volatile.LoadUint32(&o.DIEPTXF3.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPTXF3_INEP3TXFSTADDR() uint32 { + return volatile.LoadUint32(&o.DIEPTXF3.Reg) & 0xffff +} +func (o *USB_Type) SetDIEPTXF3_INEP3TXFDEP(value uint32) { + volatile.StoreUint32(&o.DIEPTXF3.Reg, volatile.LoadUint32(&o.DIEPTXF3.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetDIEPTXF3_INEP3TXFDEP() uint32 { + return (volatile.LoadUint32(&o.DIEPTXF3.Reg) & 0xffff0000) >> 16 +} + +// USB.DIEPTXF4 +func (o *USB_Type) SetDIEPTXF4_INEP4TXFSTADDR(value uint32) { + volatile.StoreUint32(&o.DIEPTXF4.Reg, volatile.LoadUint32(&o.DIEPTXF4.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPTXF4_INEP4TXFSTADDR() uint32 { + return volatile.LoadUint32(&o.DIEPTXF4.Reg) & 0xffff +} +func (o *USB_Type) SetDIEPTXF4_INEP4TXFDEP(value uint32) { + volatile.StoreUint32(&o.DIEPTXF4.Reg, volatile.LoadUint32(&o.DIEPTXF4.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetDIEPTXF4_INEP4TXFDEP() uint32 { + return (volatile.LoadUint32(&o.DIEPTXF4.Reg) & 0xffff0000) >> 16 +} + +// USB.HCFG +func (o *USB_Type) SetHCFG_H_FSLSPCLKSEL(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetHCFG_H_FSLSPCLKSEL() uint32 { + return volatile.LoadUint32(&o.HCFG.Reg) & 0x3 +} +func (o *USB_Type) SetHCFG_H_FSLSSUPP(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCFG_H_FSLSSUPP() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCFG_H_ENA32KHZS(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCFG_H_ENA32KHZS() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCFG_H_DESCDMA(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetHCFG_H_DESCDMA() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetHCFG_H_FRLISTEN(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x3000000)|value<<24) +} +func (o *USB_Type) GetHCFG_H_FRLISTEN() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x3000000) >> 24 +} +func (o *USB_Type) SetHCFG_H_PERSCHEDENA(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetHCFG_H_PERSCHEDENA() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetHCFG_H_MODECHTIMEN(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCFG_H_MODECHTIMEN() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x80000000) >> 31 +} + +// USB.HFIR +func (o *USB_Type) SetHFIR_FRINT(value uint32) { + volatile.StoreUint32(&o.HFIR.Reg, volatile.LoadUint32(&o.HFIR.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetHFIR_FRINT() uint32 { + return volatile.LoadUint32(&o.HFIR.Reg) & 0xffff +} +func (o *USB_Type) SetHFIR_HFIRRLDCTRL(value uint32) { + volatile.StoreUint32(&o.HFIR.Reg, volatile.LoadUint32(&o.HFIR.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetHFIR_HFIRRLDCTRL() uint32 { + return (volatile.LoadUint32(&o.HFIR.Reg) & 0x10000) >> 16 +} + +// USB.HFNUM +func (o *USB_Type) SetHFNUM_FRNUM(value uint32) { + volatile.StoreUint32(&o.HFNUM.Reg, volatile.LoadUint32(&o.HFNUM.Reg)&^(0x3fff)|value) +} +func (o *USB_Type) GetHFNUM_FRNUM() uint32 { + return volatile.LoadUint32(&o.HFNUM.Reg) & 0x3fff +} +func (o *USB_Type) SetHFNUM_FRREM(value uint32) { + volatile.StoreUint32(&o.HFNUM.Reg, volatile.LoadUint32(&o.HFNUM.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetHFNUM_FRREM() uint32 { + return (volatile.LoadUint32(&o.HFNUM.Reg) & 0xffff0000) >> 16 +} + +// USB.HPTXSTS +func (o *USB_Type) SetHPTXSTS_PTXFSPCAVAIL(value uint32) { + volatile.StoreUint32(&o.HPTXSTS.Reg, volatile.LoadUint32(&o.HPTXSTS.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetHPTXSTS_PTXFSPCAVAIL() uint32 { + return volatile.LoadUint32(&o.HPTXSTS.Reg) & 0xffff +} +func (o *USB_Type) SetHPTXSTS_PTXQSPCAVAIL(value uint32) { + volatile.StoreUint32(&o.HPTXSTS.Reg, volatile.LoadUint32(&o.HPTXSTS.Reg)&^(0x1f0000)|value<<16) +} +func (o *USB_Type) GetHPTXSTS_PTXQSPCAVAIL() uint32 { + return (volatile.LoadUint32(&o.HPTXSTS.Reg) & 0x1f0000) >> 16 +} +func (o *USB_Type) SetHPTXSTS_PTXQTOP(value uint32) { + volatile.StoreUint32(&o.HPTXSTS.Reg, volatile.LoadUint32(&o.HPTXSTS.Reg)&^(0xff000000)|value<<24) +} +func (o *USB_Type) GetHPTXSTS_PTXQTOP() uint32 { + return (volatile.LoadUint32(&o.HPTXSTS.Reg) & 0xff000000) >> 24 +} + +// USB.HAINT +func (o *USB_Type) SetHAINT(value uint32) { + volatile.StoreUint32(&o.HAINT.Reg, volatile.LoadUint32(&o.HAINT.Reg)&^(0xff)|value) +} +func (o *USB_Type) GetHAINT() uint32 { + return volatile.LoadUint32(&o.HAINT.Reg) & 0xff +} + +// USB.HAINTMSK +func (o *USB_Type) SetHAINTMSK(value uint32) { + volatile.StoreUint32(&o.HAINTMSK.Reg, volatile.LoadUint32(&o.HAINTMSK.Reg)&^(0xff)|value) +} +func (o *USB_Type) GetHAINTMSK() uint32 { + return volatile.LoadUint32(&o.HAINTMSK.Reg) & 0xff +} + +// USB.HFLBADDR +func (o *USB_Type) SetHFLBADDR(value uint32) { + volatile.StoreUint32(&o.HFLBADDR.Reg, value) +} +func (o *USB_Type) GetHFLBADDR() uint32 { + return volatile.LoadUint32(&o.HFLBADDR.Reg) +} + +// USB.HPRT +func (o *USB_Type) SetHPRT_PRTCONNSTS(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHPRT_PRTCONNSTS() uint32 { + return volatile.LoadUint32(&o.HPRT.Reg) & 0x1 +} +func (o *USB_Type) SetHPRT_PRTCONNDET(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHPRT_PRTCONNDET() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHPRT_PRTENA(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHPRT_PRTENA() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHPRT_PRTENCHNG(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHPRT_PRTENCHNG() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHPRT_PRTOVRCURRACT(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHPRT_PRTOVRCURRACT() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHPRT_PRTOVRCURRCHNG(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHPRT_PRTOVRCURRCHNG() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHPRT_PRTRES(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHPRT_PRTRES() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHPRT_PRTSUSP(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHPRT_PRTSUSP() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHPRT_PRTRST(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHPRT_PRTRST() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHPRT_PRTLNSTS(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0xc00)|value<<10) +} +func (o *USB_Type) GetHPRT_PRTLNSTS() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0xc00) >> 10 +} +func (o *USB_Type) SetHPRT_PRTPWR(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHPRT_PRTPWR() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHPRT_PRTTSTCTL(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x1e000)|value<<13) +} +func (o *USB_Type) GetHPRT_PRTTSTCTL() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x1e000) >> 13 +} +func (o *USB_Type) SetHPRT_PRTSPD(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x60000)|value<<17) +} +func (o *USB_Type) GetHPRT_PRTSPD() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x60000) >> 17 +} + +// USB.HCCHAR0 +func (o *USB_Type) SetHCCHAR0_H_MPS0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR0_H_MPS0() uint32 { + return volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR0_H_EPNUM0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR0_H_EPNUM0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR0_H_EPDIR0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR0_H_EPDIR0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR0_H_LSPDDEV0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR0_H_LSPDDEV0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR0_H_EPTYPE0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR0_H_EPTYPE0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR0_H_EC0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR0_H_EC0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR0_H_DEVADDR0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR0_H_DEVADDR0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR0_H_ODDFRM0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR0_H_ODDFRM0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR0_H_CHDIS0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR0_H_CHDIS0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR0_H_CHENA0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR0_H_CHENA0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT0 +func (o *USB_Type) SetHCINT0_H_XFERCOMPL0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT0_H_XFERCOMPL0() uint32 { + return volatile.LoadUint32(&o.HCINT0.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT0_H_CHHLTD0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT0_H_CHHLTD0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT0_H_AHBERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT0_H_AHBERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT0_H_STALL0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT0_H_STALL0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT0_H_NACK0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT0_H_NACK0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT0_H_ACK0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT0_H_ACK0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT0_H_NYET0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT0_H_NYET0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT0_H_XACTERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT0_H_XACTERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT0_H_BBLERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT0_H_BBLERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT0_H_FRMOVRUN0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT0_H_FRMOVRUN0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT0_H_DATATGLERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT0_H_DATATGLERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT0_H_BNAINTR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT0_H_BNAINTR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT0_H_XCS_XACT_ERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT0_H_XCS_XACT_ERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT0_H_DESC_LST_ROLLINTR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT0_H_DESC_LST_ROLLINTR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK0 +func (o *USB_Type) SetHCINTMSK0_H_XFERCOMPLMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK0_H_XFERCOMPLMSK0() uint32 { + return volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK0_H_CHHLTDMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK0_H_CHHLTDMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK0_H_AHBERRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK0_H_AHBERRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK0_H_STALLMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK0_H_STALLMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK0_H_NAKMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK0_H_NAKMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK0_H_ACKMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK0_H_ACKMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK0_H_NYETMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK0_H_NYETMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK0_H_XACTERRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK0_H_XACTERRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK0_H_BBLERRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK0_H_BBLERRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK0_H_FRMOVRUNMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK0_H_FRMOVRUNMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK0_H_DATATGLERRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK0_H_DATATGLERRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK0_H_BNAINTRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK0_H_BNAINTRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK0_H_DESC_LST_ROLLINTRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK0_H_DESC_LST_ROLLINTRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ0 +func (o *USB_Type) SetHCTSIZ0_H_XFERSIZE0(value uint32) { + volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ0_H_XFERSIZE0() uint32 { + return volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ0_H_PKTCNT0(value uint32) { + volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ0_H_PKTCNT0() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ0_H_PID0(value uint32) { + volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ0_H_PID0() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ0_H_DOPNG0(value uint32) { + volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ0_H_DOPNG0() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA0 +func (o *USB_Type) SetHCDMA0(value uint32) { + volatile.StoreUint32(&o.HCDMA0.Reg, value) +} +func (o *USB_Type) GetHCDMA0() uint32 { + return volatile.LoadUint32(&o.HCDMA0.Reg) +} + +// USB.HCDMAB0 +func (o *USB_Type) SetHCDMAB0(value uint32) { + volatile.StoreUint32(&o.HCDMAB0.Reg, value) +} +func (o *USB_Type) GetHCDMAB0() uint32 { + return volatile.LoadUint32(&o.HCDMAB0.Reg) +} + +// USB.HCCHAR1 +func (o *USB_Type) SetHCCHAR1_H_MPS1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR1_H_MPS1() uint32 { + return volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR1_H_EPNUM1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR1_H_EPNUM1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR1_H_EPDIR1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR1_H_EPDIR1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR1_H_LSPDDEV1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR1_H_LSPDDEV1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR1_H_EPTYPE1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR1_H_EPTYPE1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR1_H_EC1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR1_H_EC1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR1_H_DEVADDR1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR1_H_DEVADDR1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR1_H_ODDFRM1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR1_H_ODDFRM1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR1_H_CHDIS1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR1_H_CHDIS1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR1_H_CHENA1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR1_H_CHENA1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT1 +func (o *USB_Type) SetHCINT1_H_XFERCOMPL1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT1_H_XFERCOMPL1() uint32 { + return volatile.LoadUint32(&o.HCINT1.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT1_H_CHHLTD1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT1_H_CHHLTD1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT1_H_AHBERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT1_H_AHBERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT1_H_STALL1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT1_H_STALL1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT1_H_NACK1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT1_H_NACK1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT1_H_ACK1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT1_H_ACK1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT1_H_NYET1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT1_H_NYET1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT1_H_XACTERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT1_H_XACTERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT1_H_BBLERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT1_H_BBLERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT1_H_FRMOVRUN1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT1_H_FRMOVRUN1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT1_H_DATATGLERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT1_H_DATATGLERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT1_H_BNAINTR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT1_H_BNAINTR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT1_H_XCS_XACT_ERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT1_H_XCS_XACT_ERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT1_H_DESC_LST_ROLLINTR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT1_H_DESC_LST_ROLLINTR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK1 +func (o *USB_Type) SetHCINTMSK1_H_XFERCOMPLMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK1_H_XFERCOMPLMSK1() uint32 { + return volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK1_H_CHHLTDMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK1_H_CHHLTDMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK1_H_AHBERRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK1_H_AHBERRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK1_H_STALLMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK1_H_STALLMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK1_H_NAKMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK1_H_NAKMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK1_H_ACKMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK1_H_ACKMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK1_H_NYETMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK1_H_NYETMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK1_H_XACTERRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK1_H_XACTERRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK1_H_BBLERRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK1_H_BBLERRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK1_H_FRMOVRUNMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK1_H_FRMOVRUNMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK1_H_DATATGLERRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK1_H_DATATGLERRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK1_H_BNAINTRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK1_H_BNAINTRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK1_H_DESC_LST_ROLLINTRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK1_H_DESC_LST_ROLLINTRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ1 +func (o *USB_Type) SetHCTSIZ1_H_XFERSIZE1(value uint32) { + volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ1_H_XFERSIZE1() uint32 { + return volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ1_H_PKTCNT1(value uint32) { + volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ1_H_PKTCNT1() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ1_H_PID1(value uint32) { + volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ1_H_PID1() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ1_H_DOPNG1(value uint32) { + volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ1_H_DOPNG1() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA1 +func (o *USB_Type) SetHCDMA1(value uint32) { + volatile.StoreUint32(&o.HCDMA1.Reg, value) +} +func (o *USB_Type) GetHCDMA1() uint32 { + return volatile.LoadUint32(&o.HCDMA1.Reg) +} + +// USB.HCDMAB1 +func (o *USB_Type) SetHCDMAB1(value uint32) { + volatile.StoreUint32(&o.HCDMAB1.Reg, value) +} +func (o *USB_Type) GetHCDMAB1() uint32 { + return volatile.LoadUint32(&o.HCDMAB1.Reg) +} + +// USB.HCCHAR2 +func (o *USB_Type) SetHCCHAR2_H_MPS2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR2_H_MPS2() uint32 { + return volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR2_H_EPNUM2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR2_H_EPNUM2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR2_H_EPDIR2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR2_H_EPDIR2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR2_H_LSPDDEV2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR2_H_LSPDDEV2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR2_H_EPTYPE2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR2_H_EPTYPE2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR2_H_EC2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR2_H_EC2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR2_H_DEVADDR2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR2_H_DEVADDR2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR2_H_ODDFRM2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR2_H_ODDFRM2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR2_H_CHDIS2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR2_H_CHDIS2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR2_H_CHENA2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR2_H_CHENA2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT2 +func (o *USB_Type) SetHCINT2_H_XFERCOMPL2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT2_H_XFERCOMPL2() uint32 { + return volatile.LoadUint32(&o.HCINT2.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT2_H_CHHLTD2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT2_H_CHHLTD2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT2_H_AHBERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT2_H_AHBERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT2_H_STALL2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT2_H_STALL2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT2_H_NACK2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT2_H_NACK2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT2_H_ACK2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT2_H_ACK2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT2_H_NYET2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT2_H_NYET2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT2_H_XACTERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT2_H_XACTERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT2_H_BBLERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT2_H_BBLERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT2_H_FRMOVRUN2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT2_H_FRMOVRUN2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT2_H_DATATGLERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT2_H_DATATGLERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT2_H_BNAINTR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT2_H_BNAINTR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT2_H_XCS_XACT_ERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT2_H_XCS_XACT_ERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT2_H_DESC_LST_ROLLINTR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT2_H_DESC_LST_ROLLINTR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK2 +func (o *USB_Type) SetHCINTMSK2_H_XFERCOMPLMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK2_H_XFERCOMPLMSK2() uint32 { + return volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK2_H_CHHLTDMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK2_H_CHHLTDMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK2_H_AHBERRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK2_H_AHBERRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK2_H_STALLMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK2_H_STALLMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK2_H_NAKMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK2_H_NAKMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK2_H_ACKMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK2_H_ACKMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK2_H_NYETMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK2_H_NYETMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK2_H_XACTERRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK2_H_XACTERRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK2_H_BBLERRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK2_H_BBLERRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK2_H_FRMOVRUNMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK2_H_FRMOVRUNMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK2_H_DATATGLERRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK2_H_DATATGLERRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK2_H_BNAINTRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK2_H_BNAINTRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK2_H_DESC_LST_ROLLINTRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK2_H_DESC_LST_ROLLINTRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ2 +func (o *USB_Type) SetHCTSIZ2_H_XFERSIZE2(value uint32) { + volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ2_H_XFERSIZE2() uint32 { + return volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ2_H_PKTCNT2(value uint32) { + volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ2_H_PKTCNT2() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ2_H_PID2(value uint32) { + volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ2_H_PID2() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ2_H_DOPNG2(value uint32) { + volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ2_H_DOPNG2() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA2 +func (o *USB_Type) SetHCDMA2(value uint32) { + volatile.StoreUint32(&o.HCDMA2.Reg, value) +} +func (o *USB_Type) GetHCDMA2() uint32 { + return volatile.LoadUint32(&o.HCDMA2.Reg) +} + +// USB.HCDMAB2 +func (o *USB_Type) SetHCDMAB2(value uint32) { + volatile.StoreUint32(&o.HCDMAB2.Reg, value) +} +func (o *USB_Type) GetHCDMAB2() uint32 { + return volatile.LoadUint32(&o.HCDMAB2.Reg) +} + +// USB.HCCHAR3 +func (o *USB_Type) SetHCCHAR3_H_MPS3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR3_H_MPS3() uint32 { + return volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR3_H_EPNUM3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR3_H_EPNUM3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR3_H_EPDIR3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR3_H_EPDIR3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR3_H_LSPDDEV3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR3_H_LSPDDEV3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR3_H_EPTYPE3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR3_H_EPTYPE3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR3_H_EC3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR3_H_EC3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR3_H_DEVADDR3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR3_H_DEVADDR3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR3_H_ODDFRM3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR3_H_ODDFRM3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR3_H_CHDIS3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR3_H_CHDIS3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR3_H_CHENA3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR3_H_CHENA3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT3 +func (o *USB_Type) SetHCINT3_H_XFERCOMPL3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT3_H_XFERCOMPL3() uint32 { + return volatile.LoadUint32(&o.HCINT3.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT3_H_CHHLTD3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT3_H_CHHLTD3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT3_H_AHBERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT3_H_AHBERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT3_H_STALL3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT3_H_STALL3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT3_H_NACK3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT3_H_NACK3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT3_H_ACK3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT3_H_ACK3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT3_H_NYET3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT3_H_NYET3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT3_H_XACTERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT3_H_XACTERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT3_H_BBLERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT3_H_BBLERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT3_H_FRMOVRUN3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT3_H_FRMOVRUN3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT3_H_DATATGLERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT3_H_DATATGLERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT3_H_BNAINTR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT3_H_BNAINTR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT3_H_XCS_XACT_ERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT3_H_XCS_XACT_ERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT3_H_DESC_LST_ROLLINTR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT3_H_DESC_LST_ROLLINTR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK3 +func (o *USB_Type) SetHCINTMSK3_H_XFERCOMPLMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK3_H_XFERCOMPLMSK3() uint32 { + return volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK3_H_CHHLTDMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK3_H_CHHLTDMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK3_H_AHBERRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK3_H_AHBERRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK3_H_STALLMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK3_H_STALLMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK3_H_NAKMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK3_H_NAKMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK3_H_ACKMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK3_H_ACKMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK3_H_NYETMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK3_H_NYETMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK3_H_XACTERRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK3_H_XACTERRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK3_H_BBLERRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK3_H_BBLERRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK3_H_FRMOVRUNMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK3_H_FRMOVRUNMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK3_H_DATATGLERRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK3_H_DATATGLERRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK3_H_BNAINTRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK3_H_BNAINTRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK3_H_DESC_LST_ROLLINTRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK3_H_DESC_LST_ROLLINTRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ3 +func (o *USB_Type) SetHCTSIZ3_H_XFERSIZE3(value uint32) { + volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ3_H_XFERSIZE3() uint32 { + return volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ3_H_PKTCNT3(value uint32) { + volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ3_H_PKTCNT3() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ3_H_PID3(value uint32) { + volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ3_H_PID3() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ3_H_DOPNG3(value uint32) { + volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ3_H_DOPNG3() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA3 +func (o *USB_Type) SetHCDMA3(value uint32) { + volatile.StoreUint32(&o.HCDMA3.Reg, value) +} +func (o *USB_Type) GetHCDMA3() uint32 { + return volatile.LoadUint32(&o.HCDMA3.Reg) +} + +// USB.HCDMAB3 +func (o *USB_Type) SetHCDMAB3(value uint32) { + volatile.StoreUint32(&o.HCDMAB3.Reg, value) +} +func (o *USB_Type) GetHCDMAB3() uint32 { + return volatile.LoadUint32(&o.HCDMAB3.Reg) +} + +// USB.HCCHAR4 +func (o *USB_Type) SetHCCHAR4_H_MPS4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR4_H_MPS4() uint32 { + return volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR4_H_EPNUM4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR4_H_EPNUM4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR4_H_EPDIR4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR4_H_EPDIR4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR4_H_LSPDDEV4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR4_H_LSPDDEV4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR4_H_EPTYPE4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR4_H_EPTYPE4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR4_H_EC4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR4_H_EC4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR4_H_DEVADDR4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR4_H_DEVADDR4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR4_H_ODDFRM4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR4_H_ODDFRM4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR4_H_CHDIS4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR4_H_CHDIS4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR4_H_CHENA4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR4_H_CHENA4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT4 +func (o *USB_Type) SetHCINT4_H_XFERCOMPL4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT4_H_XFERCOMPL4() uint32 { + return volatile.LoadUint32(&o.HCINT4.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT4_H_CHHLTD4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT4_H_CHHLTD4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT4_H_AHBERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT4_H_AHBERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT4_H_STALL4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT4_H_STALL4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT4_H_NACK4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT4_H_NACK4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT4_H_ACK4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT4_H_ACK4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT4_H_NYET4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT4_H_NYET4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT4_H_XACTERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT4_H_XACTERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT4_H_BBLERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT4_H_BBLERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT4_H_FRMOVRUN4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT4_H_FRMOVRUN4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT4_H_DATATGLERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT4_H_DATATGLERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT4_H_BNAINTR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT4_H_BNAINTR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT4_H_XCS_XACT_ERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT4_H_XCS_XACT_ERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT4_H_DESC_LST_ROLLINTR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT4_H_DESC_LST_ROLLINTR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK4 +func (o *USB_Type) SetHCINTMSK4_H_XFERCOMPLMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK4_H_XFERCOMPLMSK4() uint32 { + return volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK4_H_CHHLTDMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK4_H_CHHLTDMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK4_H_AHBERRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK4_H_AHBERRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK4_H_STALLMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK4_H_STALLMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK4_H_NAKMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK4_H_NAKMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK4_H_ACKMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK4_H_ACKMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK4_H_NYETMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK4_H_NYETMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK4_H_XACTERRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK4_H_XACTERRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK4_H_BBLERRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK4_H_BBLERRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK4_H_FRMOVRUNMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK4_H_FRMOVRUNMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK4_H_DATATGLERRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK4_H_DATATGLERRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK4_H_BNAINTRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK4_H_BNAINTRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK4_H_DESC_LST_ROLLINTRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK4_H_DESC_LST_ROLLINTRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ4 +func (o *USB_Type) SetHCTSIZ4_H_XFERSIZE4(value uint32) { + volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ4_H_XFERSIZE4() uint32 { + return volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ4_H_PKTCNT4(value uint32) { + volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ4_H_PKTCNT4() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ4_H_PID4(value uint32) { + volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ4_H_PID4() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ4_H_DOPNG4(value uint32) { + volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ4_H_DOPNG4() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA4 +func (o *USB_Type) SetHCDMA4(value uint32) { + volatile.StoreUint32(&o.HCDMA4.Reg, value) +} +func (o *USB_Type) GetHCDMA4() uint32 { + return volatile.LoadUint32(&o.HCDMA4.Reg) +} + +// USB.HCDMAB4 +func (o *USB_Type) SetHCDMAB4(value uint32) { + volatile.StoreUint32(&o.HCDMAB4.Reg, value) +} +func (o *USB_Type) GetHCDMAB4() uint32 { + return volatile.LoadUint32(&o.HCDMAB4.Reg) +} + +// USB.HCCHAR5 +func (o *USB_Type) SetHCCHAR5_H_MPS5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR5_H_MPS5() uint32 { + return volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR5_H_EPNUM5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR5_H_EPNUM5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR5_H_EPDIR5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR5_H_EPDIR5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR5_H_LSPDDEV5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR5_H_LSPDDEV5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR5_H_EPTYPE5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR5_H_EPTYPE5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR5_H_EC5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR5_H_EC5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR5_H_DEVADDR5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR5_H_DEVADDR5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR5_H_ODDFRM5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR5_H_ODDFRM5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR5_H_CHDIS5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR5_H_CHDIS5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR5_H_CHENA5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR5_H_CHENA5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT5 +func (o *USB_Type) SetHCINT5_H_XFERCOMPL5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT5_H_XFERCOMPL5() uint32 { + return volatile.LoadUint32(&o.HCINT5.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT5_H_CHHLTD5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT5_H_CHHLTD5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT5_H_AHBERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT5_H_AHBERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT5_H_STALL5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT5_H_STALL5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT5_H_NACK5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT5_H_NACK5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT5_H_ACK5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT5_H_ACK5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT5_H_NYET5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT5_H_NYET5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT5_H_XACTERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT5_H_XACTERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT5_H_BBLERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT5_H_BBLERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT5_H_FRMOVRUN5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT5_H_FRMOVRUN5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT5_H_DATATGLERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT5_H_DATATGLERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT5_H_BNAINTR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT5_H_BNAINTR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT5_H_XCS_XACT_ERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT5_H_XCS_XACT_ERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT5_H_DESC_LST_ROLLINTR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT5_H_DESC_LST_ROLLINTR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK5 +func (o *USB_Type) SetHCINTMSK5_H_XFERCOMPLMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK5_H_XFERCOMPLMSK5() uint32 { + return volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK5_H_CHHLTDMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK5_H_CHHLTDMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK5_H_AHBERRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK5_H_AHBERRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK5_H_STALLMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK5_H_STALLMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK5_H_NAKMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK5_H_NAKMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK5_H_ACKMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK5_H_ACKMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK5_H_NYETMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK5_H_NYETMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK5_H_XACTERRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK5_H_XACTERRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK5_H_BBLERRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK5_H_BBLERRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK5_H_FRMOVRUNMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK5_H_FRMOVRUNMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK5_H_DATATGLERRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK5_H_DATATGLERRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK5_H_BNAINTRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK5_H_BNAINTRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK5_H_DESC_LST_ROLLINTRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK5_H_DESC_LST_ROLLINTRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ5 +func (o *USB_Type) SetHCTSIZ5_H_XFERSIZE5(value uint32) { + volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ5_H_XFERSIZE5() uint32 { + return volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ5_H_PKTCNT5(value uint32) { + volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ5_H_PKTCNT5() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ5_H_PID5(value uint32) { + volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ5_H_PID5() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ5_H_DOPNG5(value uint32) { + volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ5_H_DOPNG5() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA5 +func (o *USB_Type) SetHCDMA5(value uint32) { + volatile.StoreUint32(&o.HCDMA5.Reg, value) +} +func (o *USB_Type) GetHCDMA5() uint32 { + return volatile.LoadUint32(&o.HCDMA5.Reg) +} + +// USB.HCDMAB5 +func (o *USB_Type) SetHCDMAB5(value uint32) { + volatile.StoreUint32(&o.HCDMAB5.Reg, value) +} +func (o *USB_Type) GetHCDMAB5() uint32 { + return volatile.LoadUint32(&o.HCDMAB5.Reg) +} + +// USB.HCCHAR6 +func (o *USB_Type) SetHCCHAR6_H_MPS6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR6_H_MPS6() uint32 { + return volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR6_H_EPNUM6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR6_H_EPNUM6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR6_H_EPDIR6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR6_H_EPDIR6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR6_H_LSPDDEV6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR6_H_LSPDDEV6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR6_H_EPTYPE6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR6_H_EPTYPE6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR6_H_EC6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR6_H_EC6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR6_H_DEVADDR6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR6_H_DEVADDR6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR6_H_ODDFRM6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR6_H_ODDFRM6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR6_H_CHDIS6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR6_H_CHDIS6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR6_H_CHENA6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR6_H_CHENA6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT6 +func (o *USB_Type) SetHCINT6_H_XFERCOMPL6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT6_H_XFERCOMPL6() uint32 { + return volatile.LoadUint32(&o.HCINT6.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT6_H_CHHLTD6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT6_H_CHHLTD6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT6_H_AHBERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT6_H_AHBERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT6_H_STALL6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT6_H_STALL6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT6_H_NACK6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT6_H_NACK6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT6_H_ACK6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT6_H_ACK6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT6_H_NYET6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT6_H_NYET6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT6_H_XACTERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT6_H_XACTERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT6_H_BBLERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT6_H_BBLERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT6_H_FRMOVRUN6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT6_H_FRMOVRUN6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT6_H_DATATGLERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT6_H_DATATGLERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT6_H_BNAINTR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT6_H_BNAINTR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT6_H_XCS_XACT_ERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT6_H_XCS_XACT_ERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT6_H_DESC_LST_ROLLINTR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT6_H_DESC_LST_ROLLINTR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK6 +func (o *USB_Type) SetHCINTMSK6_H_XFERCOMPLMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK6_H_XFERCOMPLMSK6() uint32 { + return volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK6_H_CHHLTDMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK6_H_CHHLTDMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK6_H_AHBERRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK6_H_AHBERRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK6_H_STALLMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK6_H_STALLMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK6_H_NAKMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK6_H_NAKMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK6_H_ACKMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK6_H_ACKMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK6_H_NYETMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK6_H_NYETMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK6_H_XACTERRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK6_H_XACTERRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK6_H_BBLERRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK6_H_BBLERRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK6_H_FRMOVRUNMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK6_H_FRMOVRUNMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK6_H_DATATGLERRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK6_H_DATATGLERRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK6_H_BNAINTRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK6_H_BNAINTRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK6_H_DESC_LST_ROLLINTRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK6_H_DESC_LST_ROLLINTRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ6 +func (o *USB_Type) SetHCTSIZ6_H_XFERSIZE6(value uint32) { + volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ6_H_XFERSIZE6() uint32 { + return volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ6_H_PKTCNT6(value uint32) { + volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ6_H_PKTCNT6() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ6_H_PID6(value uint32) { + volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ6_H_PID6() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ6_H_DOPNG6(value uint32) { + volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ6_H_DOPNG6() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA6 +func (o *USB_Type) SetHCDMA6(value uint32) { + volatile.StoreUint32(&o.HCDMA6.Reg, value) +} +func (o *USB_Type) GetHCDMA6() uint32 { + return volatile.LoadUint32(&o.HCDMA6.Reg) +} + +// USB.HCDMAB6 +func (o *USB_Type) SetHCDMAB6(value uint32) { + volatile.StoreUint32(&o.HCDMAB6.Reg, value) +} +func (o *USB_Type) GetHCDMAB6() uint32 { + return volatile.LoadUint32(&o.HCDMAB6.Reg) +} + +// USB.HCCHAR7 +func (o *USB_Type) SetHCCHAR7_H_MPS7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR7_H_MPS7() uint32 { + return volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR7_H_EPNUM7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR7_H_EPNUM7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR7_H_EPDIR7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR7_H_EPDIR7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR7_H_LSPDDEV7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR7_H_LSPDDEV7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR7_H_EPTYPE7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR7_H_EPTYPE7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR7_H_EC7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR7_H_EC7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR7_H_DEVADDR7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR7_H_DEVADDR7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR7_H_ODDFRM7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR7_H_ODDFRM7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR7_H_CHDIS7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR7_H_CHDIS7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR7_H_CHENA7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR7_H_CHENA7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT7 +func (o *USB_Type) SetHCINT7_H_XFERCOMPL7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT7_H_XFERCOMPL7() uint32 { + return volatile.LoadUint32(&o.HCINT7.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT7_H_CHHLTD7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT7_H_CHHLTD7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT7_H_AHBERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT7_H_AHBERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT7_H_STALL7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT7_H_STALL7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT7_H_NACK7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT7_H_NACK7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT7_H_ACK7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT7_H_ACK7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT7_H_NYET7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT7_H_NYET7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT7_H_XACTERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT7_H_XACTERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT7_H_BBLERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT7_H_BBLERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT7_H_FRMOVRUN7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT7_H_FRMOVRUN7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT7_H_DATATGLERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT7_H_DATATGLERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT7_H_BNAINTR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT7_H_BNAINTR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT7_H_XCS_XACT_ERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT7_H_XCS_XACT_ERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT7_H_DESC_LST_ROLLINTR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT7_H_DESC_LST_ROLLINTR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK7 +func (o *USB_Type) SetHCINTMSK7_H_XFERCOMPLMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK7_H_XFERCOMPLMSK7() uint32 { + return volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK7_H_CHHLTDMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK7_H_CHHLTDMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK7_H_AHBERRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK7_H_AHBERRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK7_H_STALLMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK7_H_STALLMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK7_H_NAKMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK7_H_NAKMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK7_H_ACKMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK7_H_ACKMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK7_H_NYETMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK7_H_NYETMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK7_H_XACTERRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK7_H_XACTERRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK7_H_BBLERRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK7_H_BBLERRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK7_H_FRMOVRUNMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK7_H_FRMOVRUNMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK7_H_DATATGLERRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK7_H_DATATGLERRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK7_H_BNAINTRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK7_H_BNAINTRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK7_H_DESC_LST_ROLLINTRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK7_H_DESC_LST_ROLLINTRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ7 +func (o *USB_Type) SetHCTSIZ7_H_XFERSIZE7(value uint32) { + volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ7_H_XFERSIZE7() uint32 { + return volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ7_H_PKTCNT7(value uint32) { + volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ7_H_PKTCNT7() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ7_H_PID7(value uint32) { + volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ7_H_PID7() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ7_H_DOPNG7(value uint32) { + volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ7_H_DOPNG7() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA7 +func (o *USB_Type) SetHCDMA7(value uint32) { + volatile.StoreUint32(&o.HCDMA7.Reg, value) +} +func (o *USB_Type) GetHCDMA7() uint32 { + return volatile.LoadUint32(&o.HCDMA7.Reg) +} + +// USB.HCDMAB7 +func (o *USB_Type) SetHCDMAB7(value uint32) { + volatile.StoreUint32(&o.HCDMAB7.Reg, value) +} +func (o *USB_Type) GetHCDMAB7() uint32 { + return volatile.LoadUint32(&o.HCDMAB7.Reg) +} + +// USB.DCFG +func (o *USB_Type) SetDCFG_NZSTSOUTHSHK(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDCFG_NZSTSOUTHSHK() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDCFG_ENA32KHZSUSP(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDCFG_ENA32KHZSUSP() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDCFG_DEVADDR(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x7f0)|value<<4) +} +func (o *USB_Type) GetDCFG_DEVADDR() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x7f0) >> 4 +} +func (o *USB_Type) SetDCFG_PERFRLINT(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x1800)|value<<11) +} +func (o *USB_Type) GetDCFG_PERFRLINT() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x1800) >> 11 +} +func (o *USB_Type) SetDCFG_ENDEVOUTNAK(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDCFG_ENDEVOUTNAK() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDCFG_XCVRDLY(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDCFG_XCVRDLY() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDCFG_ERRATICINTMSK(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDCFG_ERRATICINTMSK() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDCFG_EPMISCNT(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x7c0000)|value<<18) +} +func (o *USB_Type) GetDCFG_EPMISCNT() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x7c0000) >> 18 +} +func (o *USB_Type) SetDCFG_DESCDMA(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetDCFG_DESCDMA() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetDCFG_PERSCHINTVL(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x3000000)|value<<24) +} +func (o *USB_Type) GetDCFG_PERSCHINTVL() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x3000000) >> 24 +} +func (o *USB_Type) SetDCFG_RESVALID(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0xfc000000)|value<<26) +} +func (o *USB_Type) GetDCFG_RESVALID() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0xfc000000) >> 26 +} + +// USB.DCTL +func (o *USB_Type) SetDCTL_RMTWKUPSIG(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDCTL_RMTWKUPSIG() uint32 { + return volatile.LoadUint32(&o.DCTL.Reg) & 0x1 +} +func (o *USB_Type) SetDCTL_SFTDISCON(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDCTL_SFTDISCON() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDCTL_GNPINNAKSTS(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDCTL_GNPINNAKSTS() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDCTL_GOUTNAKSTS(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDCTL_GOUTNAKSTS() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDCTL_TSTCTL(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x70)|value<<4) +} +func (o *USB_Type) GetDCTL_TSTCTL() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x70) >> 4 +} +func (o *USB_Type) SetDCTL_SGNPINNAK(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDCTL_SGNPINNAK() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDCTL_CGNPINNAK(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDCTL_CGNPINNAK() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDCTL_SGOUTNAK(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDCTL_SGOUTNAK() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDCTL_CGOUTNAK(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetDCTL_CGOUTNAK() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetDCTL_PWRONPRGDONE(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDCTL_PWRONPRGDONE() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDCTL_GMC(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x6000)|value<<13) +} +func (o *USB_Type) GetDCTL_GMC() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x6000) >> 13 +} +func (o *USB_Type) SetDCTL_IGNRFRMNUM(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDCTL_IGNRFRMNUM() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDCTL_NAKONBBLE(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetDCTL_NAKONBBLE() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetDCTL_ENCOUNTONBNA(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDCTL_ENCOUNTONBNA() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDCTL_DEEPSLEEPBESLREJECT(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetDCTL_DEEPSLEEPBESLREJECT() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x40000) >> 18 +} + +// USB.DSTS +func (o *USB_Type) SetDSTS_SUSPSTS(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDSTS_SUSPSTS() uint32 { + return volatile.LoadUint32(&o.DSTS.Reg) & 0x1 +} +func (o *USB_Type) SetDSTS_ENUMSPD(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x6)|value<<1) +} +func (o *USB_Type) GetDSTS_ENUMSPD() uint32 { + return (volatile.LoadUint32(&o.DSTS.Reg) & 0x6) >> 1 +} +func (o *USB_Type) SetDSTS_ERRTICERR(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDSTS_ERRTICERR() uint32 { + return (volatile.LoadUint32(&o.DSTS.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDSTS_SOFFN(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x3fff00)|value<<8) +} +func (o *USB_Type) GetDSTS_SOFFN() uint32 { + return (volatile.LoadUint32(&o.DSTS.Reg) & 0x3fff00) >> 8 +} +func (o *USB_Type) SetDSTS_DEVLNSTS(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0xc00000)|value<<22) +} +func (o *USB_Type) GetDSTS_DEVLNSTS() uint32 { + return (volatile.LoadUint32(&o.DSTS.Reg) & 0xc00000) >> 22 +} + +// USB.DIEPMSK +func (o *USB_Type) SetDIEPMSK_DI_XFERCOMPLMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPMSK_DI_XFERCOMPLMSK() uint32 { + return volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPMSK_DI_EPDISBLDMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPMSK_DI_EPDISBLDMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPMSK_DI_AHBERMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPMSK_DI_AHBERMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPMSK_TIMEOUTMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPMSK_TIMEOUTMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPMSK_INTKNTXFEMPMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPMSK_INTKNTXFEMPMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPMSK_INTKNEPMISMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPMSK_INTKNEPMISMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPMSK_INEPNAKEFFMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPMSK_INEPNAKEFFMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPMSK_TXFIFOUNDRNMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPMSK_TXFIFOUNDRNMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPMSK_BNAININTRMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPMSK_BNAININTRMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPMSK_DI_NAKMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPMSK_DI_NAKMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x2000) >> 13 +} + +// USB.DOEPMSK +func (o *USB_Type) SetDOEPMSK_XFERCOMPLMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPMSK_XFERCOMPLMSK() uint32 { + return volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPMSK_EPDISBLDMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPMSK_EPDISBLDMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPMSK_AHBERMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPMSK_AHBERMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPMSK_SETUPMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPMSK_SETUPMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPMSK_OUTTKNEPDISMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPMSK_OUTTKNEPDISMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPMSK_STSPHSERCVDMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPMSK_STSPHSERCVDMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPMSK_BACK2BACKSETUP(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPMSK_BACK2BACKSETUP() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPMSK_OUTPKTERRMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPMSK_OUTPKTERRMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPMSK_BNAOUTINTRMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPMSK_BNAOUTINTRMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPMSK_BBLEERRMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPMSK_BBLEERRMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPMSK_NAKMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPMSK_NAKMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPMSK_NYETMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPMSK_NYETMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x4000) >> 14 +} + +// USB.DAINT +func (o *USB_Type) SetDAINT_INEPINT0(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDAINT_INEPINT0() uint32 { + return volatile.LoadUint32(&o.DAINT.Reg) & 0x1 +} +func (o *USB_Type) SetDAINT_INEPINT1(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDAINT_INEPINT1() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDAINT_INEPINT2(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDAINT_INEPINT2() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDAINT_INEPINT3(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDAINT_INEPINT3() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDAINT_INEPINT4(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDAINT_INEPINT4() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDAINT_INEPINT5(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDAINT_INEPINT5() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDAINT_INEPINT6(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDAINT_INEPINT6() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDAINT_OUTEPINT0(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetDAINT_OUTEPINT0() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetDAINT_OUTEPINT1(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDAINT_OUTEPINT1() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDAINT_OUTEPINT2(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetDAINT_OUTEPINT2() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetDAINT_OUTEPINT3(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDAINT_OUTEPINT3() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDAINT_OUTEPINT4(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDAINT_OUTEPINT4() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDAINT_OUTEPINT5(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDAINT_OUTEPINT5() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDAINT_OUTEPINT6(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetDAINT_OUTEPINT6() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x400000) >> 22 +} + +// USB.DAINTMSK +func (o *USB_Type) SetDAINTMSK_INEPMSK0(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK0() uint32 { + return volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x1 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK1(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK1() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK2(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK2() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK3(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK3() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK4(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK4() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK5(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK5() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK6(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK6() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK0(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK0() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK1(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK1() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK2(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK2() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK3(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK3() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK4(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK4() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK5(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK5() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK6(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK6() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x400000) >> 22 +} + +// USB.DVBUSDIS +func (o *USB_Type) SetDVBUSDIS(value uint32) { + volatile.StoreUint32(&o.DVBUSDIS.Reg, volatile.LoadUint32(&o.DVBUSDIS.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDVBUSDIS() uint32 { + return volatile.LoadUint32(&o.DVBUSDIS.Reg) & 0xffff +} + +// USB.DVBUSPULSE +func (o *USB_Type) SetDVBUSPULSE(value uint32) { + volatile.StoreUint32(&o.DVBUSPULSE.Reg, volatile.LoadUint32(&o.DVBUSPULSE.Reg)&^(0xfff)|value) +} +func (o *USB_Type) GetDVBUSPULSE() uint32 { + return volatile.LoadUint32(&o.DVBUSPULSE.Reg) & 0xfff +} + +// USB.DTHRCTL +func (o *USB_Type) SetDTHRCTL_NONISOTHREN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDTHRCTL_NONISOTHREN() uint32 { + return volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x1 +} +func (o *USB_Type) SetDTHRCTL_ISOTHREN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDTHRCTL_ISOTHREN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDTHRCTL_TXTHRLEN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x7fc)|value<<2) +} +func (o *USB_Type) GetDTHRCTL_TXTHRLEN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x7fc) >> 2 +} +func (o *USB_Type) SetDTHRCTL_AHBTHRRATIO(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x1800)|value<<11) +} +func (o *USB_Type) GetDTHRCTL_AHBTHRRATIO() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x1800) >> 11 +} +func (o *USB_Type) SetDTHRCTL_RXTHREN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetDTHRCTL_RXTHREN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetDTHRCTL_RXTHRLEN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x3fe0000)|value<<17) +} +func (o *USB_Type) GetDTHRCTL_RXTHRLEN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x3fe0000) >> 17 +} +func (o *USB_Type) SetDTHRCTL_ARBPRKEN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDTHRCTL_ARBPRKEN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x8000000) >> 27 +} + +// USB.DIEPEMPMSK +func (o *USB_Type) SetDIEPEMPMSK_D_INEPTXFEMPMSK(value uint32) { + volatile.StoreUint32(&o.DIEPEMPMSK.Reg, volatile.LoadUint32(&o.DIEPEMPMSK.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPEMPMSK_D_INEPTXFEMPMSK() uint32 { + return volatile.LoadUint32(&o.DIEPEMPMSK.Reg) & 0xffff +} + +// USB.DIEPCTL0 +func (o *USB_Type) SetDIEPCTL0_D_MPS0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL0_D_MPS0() uint32 { + return volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL0_D_USBACTEP0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL0_D_USBACTEP0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL0_D_NAKSTS0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL0_D_NAKSTS0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL0_D_EPTYPE0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL0_D_EPTYPE0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL0_D_STALL0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL0_D_STALL0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL0_D_TXFNUM0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL0_D_TXFNUM0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL0_D_CNAK0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL0_D_CNAK0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL0_DI_SNAK0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL0_DI_SNAK0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL0_D_EPDIS0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL0_D_EPDIS0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL0_D_EPENA0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL0_D_EPENA0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT0 +func (o *USB_Type) SetDIEPINT0_D_XFERCOMPL0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT0_D_XFERCOMPL0() uint32 { + return volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT0_D_EPDISBLD0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT0_D_EPDISBLD0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT0_D_AHBERR0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT0_D_AHBERR0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT0_D_TIMEOUT0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT0_D_TIMEOUT0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT0_D_INTKNTXFEMP0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT0_D_INTKNTXFEMP0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT0_D_INTKNEPMIS0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT0_D_INTKNEPMIS0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT0_D_INEPNAKEFF0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT0_D_INEPNAKEFF0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT0_D_TXFEMP0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT0_D_TXFEMP0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT0_D_TXFIFOUNDRN0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT0_D_TXFIFOUNDRN0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT0_D_BNAINTR0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT0_D_BNAINTR0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT0_D_PKTDRPSTS0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT0_D_PKTDRPSTS0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT0_D_BBLEERR0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT0_D_BBLEERR0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT0_D_NAKINTRPT0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT0_D_NAKINTRPT0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT0_D_NYETINTRPT0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT0_D_NYETINTRPT0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ0 +func (o *USB_Type) SetDIEPTSIZ0_D_XFERSIZE0(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ0.Reg, volatile.LoadUint32(&o.DIEPTSIZ0.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ0_D_XFERSIZE0() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ0.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ0_D_PKTCNT0(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ0.Reg, volatile.LoadUint32(&o.DIEPTSIZ0.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ0_D_PKTCNT0() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ0.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA0 +func (o *USB_Type) SetDIEPDMA0(value uint32) { + volatile.StoreUint32(&o.DIEPDMA0.Reg, value) +} +func (o *USB_Type) GetDIEPDMA0() uint32 { + return volatile.LoadUint32(&o.DIEPDMA0.Reg) +} + +// USB.DTXFSTS0 +func (o *USB_Type) SetDTXFSTS0_D_INEPTXFSPCAVAIL0(value uint32) { + volatile.StoreUint32(&o.DTXFSTS0.Reg, volatile.LoadUint32(&o.DTXFSTS0.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS0_D_INEPTXFSPCAVAIL0() uint32 { + return volatile.LoadUint32(&o.DTXFSTS0.Reg) & 0xffff +} + +// USB.DIEPDMAB0 +func (o *USB_Type) SetDIEPDMAB0(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB0.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB0() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB0.Reg) +} + +// USB.DIEPCTL1 +func (o *USB_Type) SetDIEPCTL1_D_MPS1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL1_D_MPS1() uint32 { + return volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL1_D_USBACTEP1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL1_D_USBACTEP1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL1_D_NAKSTS1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL1_D_NAKSTS1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL1_D_EPTYPE1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL1_D_EPTYPE1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL1_D_STALL1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL1_D_STALL1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL1_D_TXFNUM1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL1_D_TXFNUM1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL1_D_CNAK1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL1_D_CNAK1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL1_DI_SNAK1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL1_DI_SNAK1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL1_DI_SETD0PID1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL1_DI_SETD0PID1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL1_DI_SETD1PID1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL1_DI_SETD1PID1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL1_D_EPDIS1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL1_D_EPDIS1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL1_D_EPENA1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL1_D_EPENA1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT1 +func (o *USB_Type) SetDIEPINT1_D_XFERCOMPL1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT1_D_XFERCOMPL1() uint32 { + return volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT1_D_EPDISBLD1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT1_D_EPDISBLD1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT1_D_AHBERR1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT1_D_AHBERR1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT1_D_TIMEOUT1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT1_D_TIMEOUT1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT1_D_INTKNTXFEMP1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT1_D_INTKNTXFEMP1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT1_D_INTKNEPMIS1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT1_D_INTKNEPMIS1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT1_D_INEPNAKEFF1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT1_D_INEPNAKEFF1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT1_D_TXFEMP1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT1_D_TXFEMP1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT1_D_TXFIFOUNDRN1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT1_D_TXFIFOUNDRN1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT1_D_BNAINTR1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT1_D_BNAINTR1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT1_D_PKTDRPSTS1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT1_D_PKTDRPSTS1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT1_D_BBLEERR1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT1_D_BBLEERR1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT1_D_NAKINTRPT1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT1_D_NAKINTRPT1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT1_D_NYETINTRPT1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT1_D_NYETINTRPT1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ1 +func (o *USB_Type) SetDIEPTSIZ1_D_XFERSIZE1(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ1.Reg, volatile.LoadUint32(&o.DIEPTSIZ1.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ1_D_XFERSIZE1() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ1.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ1_D_PKTCNT1(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ1.Reg, volatile.LoadUint32(&o.DIEPTSIZ1.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ1_D_PKTCNT1() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ1.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA1 +func (o *USB_Type) SetDIEPDMA1(value uint32) { + volatile.StoreUint32(&o.DIEPDMA1.Reg, value) +} +func (o *USB_Type) GetDIEPDMA1() uint32 { + return volatile.LoadUint32(&o.DIEPDMA1.Reg) +} + +// USB.DTXFSTS1 +func (o *USB_Type) SetDTXFSTS1_D_INEPTXFSPCAVAIL1(value uint32) { + volatile.StoreUint32(&o.DTXFSTS1.Reg, volatile.LoadUint32(&o.DTXFSTS1.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS1_D_INEPTXFSPCAVAIL1() uint32 { + return volatile.LoadUint32(&o.DTXFSTS1.Reg) & 0xffff +} + +// USB.DIEPDMAB1 +func (o *USB_Type) SetDIEPDMAB1(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB1.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB1() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB1.Reg) +} + +// USB.DIEPCTL2 +func (o *USB_Type) SetDIEPCTL2_D_MPS2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL2_D_MPS2() uint32 { + return volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL2_D_USBACTEP2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL2_D_USBACTEP2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL2_D_NAKSTS2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL2_D_NAKSTS2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL2_D_EPTYPE2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL2_D_EPTYPE2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL2_D_STALL2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL2_D_STALL2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL2_D_TXFNUM2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL2_D_TXFNUM2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL2_D_CNAK2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL2_D_CNAK2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL2_DI_SNAK2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL2_DI_SNAK2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL2_DI_SETD0PID2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL2_DI_SETD0PID2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL2_DI_SETD1PID2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL2_DI_SETD1PID2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL2_D_EPDIS2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL2_D_EPDIS2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL2_D_EPENA2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL2_D_EPENA2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT2 +func (o *USB_Type) SetDIEPINT2_D_XFERCOMPL2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT2_D_XFERCOMPL2() uint32 { + return volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT2_D_EPDISBLD2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT2_D_EPDISBLD2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT2_D_AHBERR2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT2_D_AHBERR2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT2_D_TIMEOUT2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT2_D_TIMEOUT2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT2_D_INTKNTXFEMP2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT2_D_INTKNTXFEMP2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT2_D_INTKNEPMIS2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT2_D_INTKNEPMIS2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT2_D_INEPNAKEFF2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT2_D_INEPNAKEFF2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT2_D_TXFEMP2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT2_D_TXFEMP2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT2_D_TXFIFOUNDRN2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT2_D_TXFIFOUNDRN2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT2_D_BNAINTR2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT2_D_BNAINTR2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT2_D_PKTDRPSTS2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT2_D_PKTDRPSTS2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT2_D_BBLEERR2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT2_D_BBLEERR2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT2_D_NAKINTRPT2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT2_D_NAKINTRPT2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT2_D_NYETINTRPT2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT2_D_NYETINTRPT2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ2 +func (o *USB_Type) SetDIEPTSIZ2_D_XFERSIZE2(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ2.Reg, volatile.LoadUint32(&o.DIEPTSIZ2.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ2_D_XFERSIZE2() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ2.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ2_D_PKTCNT2(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ2.Reg, volatile.LoadUint32(&o.DIEPTSIZ2.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ2_D_PKTCNT2() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ2.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA2 +func (o *USB_Type) SetDIEPDMA2(value uint32) { + volatile.StoreUint32(&o.DIEPDMA2.Reg, value) +} +func (o *USB_Type) GetDIEPDMA2() uint32 { + return volatile.LoadUint32(&o.DIEPDMA2.Reg) +} + +// USB.DTXFSTS2 +func (o *USB_Type) SetDTXFSTS2_D_INEPTXFSPCAVAIL2(value uint32) { + volatile.StoreUint32(&o.DTXFSTS2.Reg, volatile.LoadUint32(&o.DTXFSTS2.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS2_D_INEPTXFSPCAVAIL2() uint32 { + return volatile.LoadUint32(&o.DTXFSTS2.Reg) & 0xffff +} + +// USB.DIEPDMAB2 +func (o *USB_Type) SetDIEPDMAB2(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB2.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB2() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB2.Reg) +} + +// USB.DIEPCTL3 +func (o *USB_Type) SetDIEPCTL3_DI_MPS3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL3_DI_MPS3() uint32 { + return volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL3_DI_USBACTEP3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL3_DI_USBACTEP3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL3_DI_NAKSTS3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL3_DI_NAKSTS3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL3_DI_EPTYPE3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL3_DI_EPTYPE3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL3_DI_STALL3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL3_DI_STALL3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL3_DI_TXFNUM3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL3_DI_TXFNUM3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL3_DI_CNAK3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL3_DI_CNAK3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL3_DI_SNAK3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL3_DI_SNAK3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL3_DI_SETD0PID3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL3_DI_SETD0PID3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL3_DI_SETD1PID3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL3_DI_SETD1PID3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL3_DI_EPDIS3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL3_DI_EPDIS3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL3_DI_EPENA3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL3_DI_EPENA3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT3 +func (o *USB_Type) SetDIEPINT3_D_XFERCOMPL3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT3_D_XFERCOMPL3() uint32 { + return volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT3_D_EPDISBLD3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT3_D_EPDISBLD3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT3_D_AHBERR3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT3_D_AHBERR3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT3_D_TIMEOUT3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT3_D_TIMEOUT3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT3_D_INTKNTXFEMP3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT3_D_INTKNTXFEMP3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT3_D_INTKNEPMIS3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT3_D_INTKNEPMIS3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT3_D_INEPNAKEFF3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT3_D_INEPNAKEFF3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT3_D_TXFEMP3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT3_D_TXFEMP3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT3_D_TXFIFOUNDRN3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT3_D_TXFIFOUNDRN3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT3_D_BNAINTR3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT3_D_BNAINTR3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT3_D_PKTDRPSTS3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT3_D_PKTDRPSTS3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT3_D_BBLEERR3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT3_D_BBLEERR3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT3_D_NAKINTRPT3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT3_D_NAKINTRPT3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT3_D_NYETINTRPT3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT3_D_NYETINTRPT3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ3 +func (o *USB_Type) SetDIEPTSIZ3_D_XFERSIZE3(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ3.Reg, volatile.LoadUint32(&o.DIEPTSIZ3.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ3_D_XFERSIZE3() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ3.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ3_D_PKTCNT3(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ3.Reg, volatile.LoadUint32(&o.DIEPTSIZ3.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ3_D_PKTCNT3() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ3.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA3 +func (o *USB_Type) SetDIEPDMA3(value uint32) { + volatile.StoreUint32(&o.DIEPDMA3.Reg, value) +} +func (o *USB_Type) GetDIEPDMA3() uint32 { + return volatile.LoadUint32(&o.DIEPDMA3.Reg) +} + +// USB.DTXFSTS3 +func (o *USB_Type) SetDTXFSTS3_D_INEPTXFSPCAVAIL3(value uint32) { + volatile.StoreUint32(&o.DTXFSTS3.Reg, volatile.LoadUint32(&o.DTXFSTS3.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS3_D_INEPTXFSPCAVAIL3() uint32 { + return volatile.LoadUint32(&o.DTXFSTS3.Reg) & 0xffff +} + +// USB.DIEPDMAB3 +func (o *USB_Type) SetDIEPDMAB3(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB3.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB3() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB3.Reg) +} + +// USB.DIEPCTL4 +func (o *USB_Type) SetDIEPCTL4_D_MPS4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL4_D_MPS4() uint32 { + return volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL4_D_USBACTEP4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL4_D_USBACTEP4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL4_D_NAKSTS4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL4_D_NAKSTS4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL4_D_EPTYPE4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL4_D_EPTYPE4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL4_D_STALL4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL4_D_STALL4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL4_D_TXFNUM4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL4_D_TXFNUM4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL4_D_CNAK4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL4_D_CNAK4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL4_DI_SNAK4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL4_DI_SNAK4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL4_DI_SETD0PID4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL4_DI_SETD0PID4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL4_DI_SETD1PID4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL4_DI_SETD1PID4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL4_D_EPDIS4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL4_D_EPDIS4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL4_D_EPENA4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL4_D_EPENA4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT4 +func (o *USB_Type) SetDIEPINT4_D_XFERCOMPL4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT4_D_XFERCOMPL4() uint32 { + return volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT4_D_EPDISBLD4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT4_D_EPDISBLD4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT4_D_AHBERR4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT4_D_AHBERR4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT4_D_TIMEOUT4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT4_D_TIMEOUT4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT4_D_INTKNTXFEMP4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT4_D_INTKNTXFEMP4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT4_D_INTKNEPMIS4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT4_D_INTKNEPMIS4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT4_D_INEPNAKEFF4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT4_D_INEPNAKEFF4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT4_D_TXFEMP4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT4_D_TXFEMP4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT4_D_TXFIFOUNDRN4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT4_D_TXFIFOUNDRN4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT4_D_BNAINTR4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT4_D_BNAINTR4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT4_D_PKTDRPSTS4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT4_D_PKTDRPSTS4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT4_D_BBLEERR4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT4_D_BBLEERR4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT4_D_NAKINTRPT4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT4_D_NAKINTRPT4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT4_D_NYETINTRPT4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT4_D_NYETINTRPT4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ4 +func (o *USB_Type) SetDIEPTSIZ4_D_XFERSIZE4(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ4.Reg, volatile.LoadUint32(&o.DIEPTSIZ4.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ4_D_XFERSIZE4() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ4.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ4_D_PKTCNT4(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ4.Reg, volatile.LoadUint32(&o.DIEPTSIZ4.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ4_D_PKTCNT4() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ4.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA4 +func (o *USB_Type) SetDIEPDMA4(value uint32) { + volatile.StoreUint32(&o.DIEPDMA4.Reg, value) +} +func (o *USB_Type) GetDIEPDMA4() uint32 { + return volatile.LoadUint32(&o.DIEPDMA4.Reg) +} + +// USB.DTXFSTS4 +func (o *USB_Type) SetDTXFSTS4_D_INEPTXFSPCAVAIL4(value uint32) { + volatile.StoreUint32(&o.DTXFSTS4.Reg, volatile.LoadUint32(&o.DTXFSTS4.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS4_D_INEPTXFSPCAVAIL4() uint32 { + return volatile.LoadUint32(&o.DTXFSTS4.Reg) & 0xffff +} + +// USB.DIEPDMAB4 +func (o *USB_Type) SetDIEPDMAB4(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB4.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB4() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB4.Reg) +} + +// USB.DIEPCTL5 +func (o *USB_Type) SetDIEPCTL5_DI_MPS5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL5_DI_MPS5() uint32 { + return volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL5_DI_USBACTEP5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL5_DI_USBACTEP5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL5_DI_NAKSTS5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL5_DI_NAKSTS5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL5_DI_EPTYPE5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL5_DI_EPTYPE5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL5_DI_STALL5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL5_DI_STALL5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL5_DI_TXFNUM5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL5_DI_TXFNUM5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL5_DI_CNAK5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL5_DI_CNAK5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL5_DI_SNAK5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL5_DI_SNAK5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL5_DI_SETD0PID5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL5_DI_SETD0PID5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL5_DI_SETD1PID5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL5_DI_SETD1PID5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL5_DI_EPDIS5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL5_DI_EPDIS5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL5_DI_EPENA5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL5_DI_EPENA5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT5 +func (o *USB_Type) SetDIEPINT5_D_XFERCOMPL5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT5_D_XFERCOMPL5() uint32 { + return volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT5_D_EPDISBLD5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT5_D_EPDISBLD5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT5_D_AHBERR5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT5_D_AHBERR5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT5_D_TIMEOUT5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT5_D_TIMEOUT5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT5_D_INTKNTXFEMP5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT5_D_INTKNTXFEMP5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT5_D_INTKNEPMIS5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT5_D_INTKNEPMIS5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT5_D_INEPNAKEFF5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT5_D_INEPNAKEFF5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT5_D_TXFEMP5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT5_D_TXFEMP5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT5_D_TXFIFOUNDRN5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT5_D_TXFIFOUNDRN5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT5_D_BNAINTR5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT5_D_BNAINTR5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT5_D_PKTDRPSTS5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT5_D_PKTDRPSTS5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT5_D_BBLEERR5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT5_D_BBLEERR5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT5_D_NAKINTRPT5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT5_D_NAKINTRPT5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT5_D_NYETINTRPT5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT5_D_NYETINTRPT5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ5 +func (o *USB_Type) SetDIEPTSIZ5_D_XFERSIZE5(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ5.Reg, volatile.LoadUint32(&o.DIEPTSIZ5.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ5_D_XFERSIZE5() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ5.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ5_D_PKTCNT5(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ5.Reg, volatile.LoadUint32(&o.DIEPTSIZ5.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ5_D_PKTCNT5() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ5.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA5 +func (o *USB_Type) SetDIEPDMA5(value uint32) { + volatile.StoreUint32(&o.DIEPDMA5.Reg, value) +} +func (o *USB_Type) GetDIEPDMA5() uint32 { + return volatile.LoadUint32(&o.DIEPDMA5.Reg) +} + +// USB.DTXFSTS5 +func (o *USB_Type) SetDTXFSTS5_D_INEPTXFSPCAVAIL5(value uint32) { + volatile.StoreUint32(&o.DTXFSTS5.Reg, volatile.LoadUint32(&o.DTXFSTS5.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS5_D_INEPTXFSPCAVAIL5() uint32 { + return volatile.LoadUint32(&o.DTXFSTS5.Reg) & 0xffff +} + +// USB.DIEPDMAB5 +func (o *USB_Type) SetDIEPDMAB5(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB5.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB5() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB5.Reg) +} + +// USB.DIEPCTL6 +func (o *USB_Type) SetDIEPCTL6_D_MPS6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL6_D_MPS6() uint32 { + return volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL6_D_USBACTEP6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL6_D_USBACTEP6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL6_D_NAKSTS6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL6_D_NAKSTS6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL6_D_EPTYPE6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL6_D_EPTYPE6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL6_D_STALL6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL6_D_STALL6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL6_D_TXFNUM6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL6_D_TXFNUM6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL6_D_CNAK6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL6_D_CNAK6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL6_DI_SNAK6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL6_DI_SNAK6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL6_DI_SETD0PID6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL6_DI_SETD0PID6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL6_DI_SETD1PID6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL6_DI_SETD1PID6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL6_D_EPDIS6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL6_D_EPDIS6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL6_D_EPENA6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL6_D_EPENA6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT6 +func (o *USB_Type) SetDIEPINT6_D_XFERCOMPL6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT6_D_XFERCOMPL6() uint32 { + return volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT6_D_EPDISBLD6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT6_D_EPDISBLD6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT6_D_AHBERR6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT6_D_AHBERR6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT6_D_TIMEOUT6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT6_D_TIMEOUT6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT6_D_INTKNTXFEMP6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT6_D_INTKNTXFEMP6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT6_D_INTKNEPMIS6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT6_D_INTKNEPMIS6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT6_D_INEPNAKEFF6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT6_D_INEPNAKEFF6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT6_D_TXFEMP6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT6_D_TXFEMP6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT6_D_TXFIFOUNDRN6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT6_D_TXFIFOUNDRN6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT6_D_BNAINTR6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT6_D_BNAINTR6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT6_D_PKTDRPSTS6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT6_D_PKTDRPSTS6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT6_D_BBLEERR6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT6_D_BBLEERR6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT6_D_NAKINTRPT6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT6_D_NAKINTRPT6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT6_D_NYETINTRPT6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT6_D_NYETINTRPT6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ6 +func (o *USB_Type) SetDIEPTSIZ6_D_XFERSIZE6(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ6.Reg, volatile.LoadUint32(&o.DIEPTSIZ6.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ6_D_XFERSIZE6() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ6.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ6_D_PKTCNT6(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ6.Reg, volatile.LoadUint32(&o.DIEPTSIZ6.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ6_D_PKTCNT6() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ6.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA6 +func (o *USB_Type) SetDIEPDMA6(value uint32) { + volatile.StoreUint32(&o.DIEPDMA6.Reg, value) +} +func (o *USB_Type) GetDIEPDMA6() uint32 { + return volatile.LoadUint32(&o.DIEPDMA6.Reg) +} + +// USB.DTXFSTS6 +func (o *USB_Type) SetDTXFSTS6_D_INEPTXFSPCAVAIL6(value uint32) { + volatile.StoreUint32(&o.DTXFSTS6.Reg, volatile.LoadUint32(&o.DTXFSTS6.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS6_D_INEPTXFSPCAVAIL6() uint32 { + return volatile.LoadUint32(&o.DTXFSTS6.Reg) & 0xffff +} + +// USB.DIEPDMAB6 +func (o *USB_Type) SetDIEPDMAB6(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB6.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB6() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB6.Reg) +} + +// USB.DOEPCTL0 +func (o *USB_Type) SetDOEPCTL0_MPS0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDOEPCTL0_MPS0() uint32 { + return volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x3 +} +func (o *USB_Type) SetDOEPCTL0_USBACTEP0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL0_USBACTEP0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL0_NAKSTS0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL0_NAKSTS0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL0_EPTYPE0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL0_EPTYPE0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL0_SNP0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL0_SNP0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL0_STALL0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL0_STALL0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL0_CNAK0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL0_CNAK0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL0_DO_SNAK0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL0_DO_SNAK0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL0_EPDIS0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL0_EPDIS0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL0_EPENA0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL0_EPENA0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT0 +func (o *USB_Type) SetDOEPINT0_XFERCOMPL0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT0_XFERCOMPL0() uint32 { + return volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT0_EPDISBLD0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT0_EPDISBLD0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT0_AHBERR0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT0_AHBERR0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT0_SETUP0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT0_SETUP0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT0_OUTTKNEPDIS0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT0_OUTTKNEPDIS0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT0_STSPHSERCVD0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT0_STSPHSERCVD0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT0_BACK2BACKSETUP0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT0_BACK2BACKSETUP0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT0_OUTPKTERR0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT0_OUTPKTERR0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT0_BNAINTR0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT0_BNAINTR0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT0_PKTDRPSTS0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT0_PKTDRPSTS0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT0_BBLEERR0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT0_BBLEERR0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT0_NAKINTRPT0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT0_NAKINTRPT0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT0_NYEPINTRPT0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT0_NYEPINTRPT0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT0_STUPPKTRCVD0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT0_STUPPKTRCVD0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ0 +func (o *USB_Type) SetDOEPTSIZ0_XFERSIZE0(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ0.Reg, volatile.LoadUint32(&o.DOEPTSIZ0.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ0_XFERSIZE0() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ0.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ0_PKTCNT0(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ0.Reg, volatile.LoadUint32(&o.DOEPTSIZ0.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ0_PKTCNT0() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ0.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ0_SUPCNT0(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ0.Reg, volatile.LoadUint32(&o.DOEPTSIZ0.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ0_SUPCNT0() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ0.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA0 +func (o *USB_Type) SetDOEPDMA0(value uint32) { + volatile.StoreUint32(&o.DOEPDMA0.Reg, value) +} +func (o *USB_Type) GetDOEPDMA0() uint32 { + return volatile.LoadUint32(&o.DOEPDMA0.Reg) +} + +// USB.DOEPDMAB0 +func (o *USB_Type) SetDOEPDMAB0(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB0.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB0() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB0.Reg) +} + +// USB.DOEPCTL1 +func (o *USB_Type) SetDOEPCTL1_MPS1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL1_MPS1() uint32 { + return volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL1_USBACTEP1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL1_USBACTEP1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL1_NAKSTS1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL1_NAKSTS1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL1_EPTYPE1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL1_EPTYPE1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL1_SNP1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL1_SNP1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL1_STALL1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL1_STALL1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL1_CNAK1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL1_CNAK1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL1_DO_SNAK1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL1_DO_SNAK1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL1_DO_SETD0PID1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL1_DO_SETD0PID1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL1_DO_SETD1PID1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL1_DO_SETD1PID1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL1_EPDIS1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL1_EPDIS1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL1_EPENA1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL1_EPENA1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT1 +func (o *USB_Type) SetDOEPINT1_XFERCOMPL1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT1_XFERCOMPL1() uint32 { + return volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT1_EPDISBLD1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT1_EPDISBLD1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT1_AHBERR1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT1_AHBERR1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT1_SETUP1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT1_SETUP1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT1_OUTTKNEPDIS1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT1_OUTTKNEPDIS1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT1_STSPHSERCVD1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT1_STSPHSERCVD1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT1_BACK2BACKSETUP1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT1_BACK2BACKSETUP1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT1_OUTPKTERR1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT1_OUTPKTERR1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT1_BNAINTR1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT1_BNAINTR1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT1_PKTDRPSTS1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT1_PKTDRPSTS1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT1_BBLEERR1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT1_BBLEERR1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT1_NAKINTRPT1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT1_NAKINTRPT1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT1_NYEPINTRPT1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT1_NYEPINTRPT1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT1_STUPPKTRCVD1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT1_STUPPKTRCVD1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ1 +func (o *USB_Type) SetDOEPTSIZ1_XFERSIZE1(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ1.Reg, volatile.LoadUint32(&o.DOEPTSIZ1.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ1_XFERSIZE1() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ1.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ1_PKTCNT1(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ1.Reg, volatile.LoadUint32(&o.DOEPTSIZ1.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ1_PKTCNT1() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ1.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ1_SUPCNT1(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ1.Reg, volatile.LoadUint32(&o.DOEPTSIZ1.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ1_SUPCNT1() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ1.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA1 +func (o *USB_Type) SetDOEPDMA1(value uint32) { + volatile.StoreUint32(&o.DOEPDMA1.Reg, value) +} +func (o *USB_Type) GetDOEPDMA1() uint32 { + return volatile.LoadUint32(&o.DOEPDMA1.Reg) +} + +// USB.DOEPDMAB1 +func (o *USB_Type) SetDOEPDMAB1(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB1.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB1() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB1.Reg) +} + +// USB.DOEPCTL2 +func (o *USB_Type) SetDOEPCTL2_MPS2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL2_MPS2() uint32 { + return volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL2_USBACTEP2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL2_USBACTEP2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL2_NAKSTS2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL2_NAKSTS2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL2_EPTYPE2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL2_EPTYPE2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL2_SNP2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL2_SNP2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL2_STALL2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL2_STALL2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL2_CNAK2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL2_CNAK2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL2_DO_SNAK2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL2_DO_SNAK2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL2_DO_SETD0PID2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL2_DO_SETD0PID2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL2_DO_SETD1PID2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL2_DO_SETD1PID2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL2_EPDIS2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL2_EPDIS2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL2_EPENA2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL2_EPENA2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT2 +func (o *USB_Type) SetDOEPINT2_XFERCOMPL2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT2_XFERCOMPL2() uint32 { + return volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT2_EPDISBLD2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT2_EPDISBLD2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT2_AHBERR2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT2_AHBERR2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT2_SETUP2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT2_SETUP2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT2_OUTTKNEPDIS2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT2_OUTTKNEPDIS2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT2_STSPHSERCVD2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT2_STSPHSERCVD2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT2_BACK2BACKSETUP2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT2_BACK2BACKSETUP2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT2_OUTPKTERR2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT2_OUTPKTERR2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT2_BNAINTR2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT2_BNAINTR2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT2_PKTDRPSTS2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT2_PKTDRPSTS2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT2_BBLEERR2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT2_BBLEERR2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT2_NAKINTRPT2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT2_NAKINTRPT2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT2_NYEPINTRPT2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT2_NYEPINTRPT2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT2_STUPPKTRCVD2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT2_STUPPKTRCVD2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ2 +func (o *USB_Type) SetDOEPTSIZ2_XFERSIZE2(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ2.Reg, volatile.LoadUint32(&o.DOEPTSIZ2.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ2_XFERSIZE2() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ2.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ2_PKTCNT2(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ2.Reg, volatile.LoadUint32(&o.DOEPTSIZ2.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ2_PKTCNT2() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ2.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ2_SUPCNT2(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ2.Reg, volatile.LoadUint32(&o.DOEPTSIZ2.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ2_SUPCNT2() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ2.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA2 +func (o *USB_Type) SetDOEPDMA2(value uint32) { + volatile.StoreUint32(&o.DOEPDMA2.Reg, value) +} +func (o *USB_Type) GetDOEPDMA2() uint32 { + return volatile.LoadUint32(&o.DOEPDMA2.Reg) +} + +// USB.DOEPDMAB2 +func (o *USB_Type) SetDOEPDMAB2(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB2.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB2() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB2.Reg) +} + +// USB.DOEPCTL3 +func (o *USB_Type) SetDOEPCTL3_MPS3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL3_MPS3() uint32 { + return volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL3_USBACTEP3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL3_USBACTEP3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL3_NAKSTS3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL3_NAKSTS3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL3_EPTYPE3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL3_EPTYPE3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL3_SNP3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL3_SNP3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL3_STALL3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL3_STALL3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL3_CNAK3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL3_CNAK3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL3_DO_SNAK3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL3_DO_SNAK3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL3_DO_SETD0PID3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL3_DO_SETD0PID3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL3_DO_SETD1PID3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL3_DO_SETD1PID3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL3_EPDIS3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL3_EPDIS3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL3_EPENA3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL3_EPENA3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT3 +func (o *USB_Type) SetDOEPINT3_XFERCOMPL3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT3_XFERCOMPL3() uint32 { + return volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT3_EPDISBLD3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT3_EPDISBLD3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT3_AHBERR3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT3_AHBERR3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT3_SETUP3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT3_SETUP3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT3_OUTTKNEPDIS3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT3_OUTTKNEPDIS3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT3_STSPHSERCVD3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT3_STSPHSERCVD3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT3_BACK2BACKSETUP3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT3_BACK2BACKSETUP3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT3_OUTPKTERR3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT3_OUTPKTERR3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT3_BNAINTR3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT3_BNAINTR3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT3_PKTDRPSTS3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT3_PKTDRPSTS3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT3_BBLEERR3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT3_BBLEERR3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT3_NAKINTRPT3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT3_NAKINTRPT3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT3_NYEPINTRPT3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT3_NYEPINTRPT3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT3_STUPPKTRCVD3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT3_STUPPKTRCVD3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ3 +func (o *USB_Type) SetDOEPTSIZ3_XFERSIZE3(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ3.Reg, volatile.LoadUint32(&o.DOEPTSIZ3.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ3_XFERSIZE3() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ3.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ3_PKTCNT3(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ3.Reg, volatile.LoadUint32(&o.DOEPTSIZ3.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ3_PKTCNT3() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ3.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ3_SUPCNT3(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ3.Reg, volatile.LoadUint32(&o.DOEPTSIZ3.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ3_SUPCNT3() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ3.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA3 +func (o *USB_Type) SetDOEPDMA3(value uint32) { + volatile.StoreUint32(&o.DOEPDMA3.Reg, value) +} +func (o *USB_Type) GetDOEPDMA3() uint32 { + return volatile.LoadUint32(&o.DOEPDMA3.Reg) +} + +// USB.DOEPDMAB3 +func (o *USB_Type) SetDOEPDMAB3(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB3.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB3() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB3.Reg) +} + +// USB.DOEPCTL4 +func (o *USB_Type) SetDOEPCTL4_MPS4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL4_MPS4() uint32 { + return volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL4_USBACTEP4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL4_USBACTEP4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL4_NAKSTS4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL4_NAKSTS4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL4_EPTYPE4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL4_EPTYPE4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL4_SNP4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL4_SNP4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL4_STALL4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL4_STALL4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL4_CNAK4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL4_CNAK4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL4_DO_SNAK4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL4_DO_SNAK4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL4_DO_SETD0PID4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL4_DO_SETD0PID4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL4_DO_SETD1PID4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL4_DO_SETD1PID4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL4_EPDIS4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL4_EPDIS4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL4_EPENA4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL4_EPENA4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT4 +func (o *USB_Type) SetDOEPINT4_XFERCOMPL4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT4_XFERCOMPL4() uint32 { + return volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT4_EPDISBLD4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT4_EPDISBLD4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT4_AHBERR4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT4_AHBERR4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT4_SETUP4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT4_SETUP4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT4_OUTTKNEPDIS4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT4_OUTTKNEPDIS4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT4_STSPHSERCVD4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT4_STSPHSERCVD4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT4_BACK2BACKSETUP4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT4_BACK2BACKSETUP4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT4_OUTPKTERR4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT4_OUTPKTERR4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT4_BNAINTR4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT4_BNAINTR4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT4_PKTDRPSTS4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT4_PKTDRPSTS4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT4_BBLEERR4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT4_BBLEERR4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT4_NAKINTRPT4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT4_NAKINTRPT4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT4_NYEPINTRPT4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT4_NYEPINTRPT4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT4_STUPPKTRCVD4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT4_STUPPKTRCVD4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ4 +func (o *USB_Type) SetDOEPTSIZ4_XFERSIZE4(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ4.Reg, volatile.LoadUint32(&o.DOEPTSIZ4.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ4_XFERSIZE4() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ4.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ4_PKTCNT4(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ4.Reg, volatile.LoadUint32(&o.DOEPTSIZ4.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ4_PKTCNT4() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ4.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ4_SUPCNT4(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ4.Reg, volatile.LoadUint32(&o.DOEPTSIZ4.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ4_SUPCNT4() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ4.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA4 +func (o *USB_Type) SetDOEPDMA4(value uint32) { + volatile.StoreUint32(&o.DOEPDMA4.Reg, value) +} +func (o *USB_Type) GetDOEPDMA4() uint32 { + return volatile.LoadUint32(&o.DOEPDMA4.Reg) +} + +// USB.DOEPDMAB4 +func (o *USB_Type) SetDOEPDMAB4(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB4.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB4() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB4.Reg) +} + +// USB.DOEPCTL5 +func (o *USB_Type) SetDOEPCTL5_MPS5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL5_MPS5() uint32 { + return volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL5_USBACTEP5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL5_USBACTEP5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL5_NAKSTS5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL5_NAKSTS5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL5_EPTYPE5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL5_EPTYPE5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL5_SNP5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL5_SNP5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL5_STALL5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL5_STALL5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL5_CNAK5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL5_CNAK5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL5_DO_SNAK5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL5_DO_SNAK5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL5_DO_SETD0PID5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL5_DO_SETD0PID5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL5_DO_SETD1PID5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL5_DO_SETD1PID5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL5_EPDIS5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL5_EPDIS5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL5_EPENA5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL5_EPENA5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT5 +func (o *USB_Type) SetDOEPINT5_XFERCOMPL5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT5_XFERCOMPL5() uint32 { + return volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT5_EPDISBLD5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT5_EPDISBLD5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT5_AHBERR5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT5_AHBERR5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT5_SETUP5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT5_SETUP5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT5_OUTTKNEPDIS5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT5_OUTTKNEPDIS5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT5_STSPHSERCVD5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT5_STSPHSERCVD5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT5_BACK2BACKSETUP5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT5_BACK2BACKSETUP5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT5_OUTPKTERR5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT5_OUTPKTERR5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT5_BNAINTR5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT5_BNAINTR5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT5_PKTDRPSTS5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT5_PKTDRPSTS5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT5_BBLEERR5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT5_BBLEERR5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT5_NAKINTRPT5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT5_NAKINTRPT5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT5_NYEPINTRPT5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT5_NYEPINTRPT5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT5_STUPPKTRCVD5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT5_STUPPKTRCVD5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ5 +func (o *USB_Type) SetDOEPTSIZ5_XFERSIZE5(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ5.Reg, volatile.LoadUint32(&o.DOEPTSIZ5.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ5_XFERSIZE5() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ5.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ5_PKTCNT5(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ5.Reg, volatile.LoadUint32(&o.DOEPTSIZ5.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ5_PKTCNT5() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ5.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ5_SUPCNT5(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ5.Reg, volatile.LoadUint32(&o.DOEPTSIZ5.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ5_SUPCNT5() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ5.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA5 +func (o *USB_Type) SetDOEPDMA5(value uint32) { + volatile.StoreUint32(&o.DOEPDMA5.Reg, value) +} +func (o *USB_Type) GetDOEPDMA5() uint32 { + return volatile.LoadUint32(&o.DOEPDMA5.Reg) +} + +// USB.DOEPDMAB5 +func (o *USB_Type) SetDOEPDMAB5(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB5.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB5() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB5.Reg) +} + +// USB.DOEPCTL6 +func (o *USB_Type) SetDOEPCTL6_MPS6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL6_MPS6() uint32 { + return volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL6_USBACTEP6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL6_USBACTEP6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL6_NAKSTS6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL6_NAKSTS6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL6_EPTYPE6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL6_EPTYPE6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL6_SNP6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL6_SNP6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL6_STALL6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL6_STALL6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL6_CNAK6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL6_CNAK6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL6_DO_SNAK6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL6_DO_SNAK6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL6_DO_SETD0PID6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL6_DO_SETD0PID6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL6_DO_SETD1PID6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL6_DO_SETD1PID6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL6_EPDIS6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL6_EPDIS6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL6_EPENA6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL6_EPENA6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT6 +func (o *USB_Type) SetDOEPINT6_XFERCOMPL6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT6_XFERCOMPL6() uint32 { + return volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT6_EPDISBLD6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT6_EPDISBLD6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT6_AHBERR6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT6_AHBERR6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT6_SETUP6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT6_SETUP6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT6_OUTTKNEPDIS6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT6_OUTTKNEPDIS6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT6_STSPHSERCVD6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT6_STSPHSERCVD6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT6_BACK2BACKSETUP6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT6_BACK2BACKSETUP6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT6_OUTPKTERR6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT6_OUTPKTERR6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT6_BNAINTR6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT6_BNAINTR6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT6_PKTDRPSTS6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT6_PKTDRPSTS6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT6_BBLEERR6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT6_BBLEERR6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT6_NAKINTRPT6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT6_NAKINTRPT6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT6_NYEPINTRPT6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT6_NYEPINTRPT6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT6_STUPPKTRCVD6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT6_STUPPKTRCVD6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ6 +func (o *USB_Type) SetDOEPTSIZ6_XFERSIZE6(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ6.Reg, volatile.LoadUint32(&o.DOEPTSIZ6.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ6_XFERSIZE6() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ6.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ6_PKTCNT6(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ6.Reg, volatile.LoadUint32(&o.DOEPTSIZ6.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ6_PKTCNT6() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ6.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ6_SUPCNT6(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ6.Reg, volatile.LoadUint32(&o.DOEPTSIZ6.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ6_SUPCNT6() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ6.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA6 +func (o *USB_Type) SetDOEPDMA6(value uint32) { + volatile.StoreUint32(&o.DOEPDMA6.Reg, value) +} +func (o *USB_Type) GetDOEPDMA6() uint32 { + return volatile.LoadUint32(&o.DOEPDMA6.Reg) +} + +// USB.DOEPDMAB6 +func (o *USB_Type) SetDOEPDMAB6(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB6.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB6() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB6.Reg) +} + +// USB.PCGCCTL +func (o *USB_Type) SetPCGCCTL_STOPPCLK(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetPCGCCTL_STOPPCLK() uint32 { + return volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x1 +} +func (o *USB_Type) SetPCGCCTL_GATEHCLK(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetPCGCCTL_GATEHCLK() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetPCGCCTL_PWRCLMP(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetPCGCCTL_PWRCLMP() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetPCGCCTL_RSTPDWNMODULE(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetPCGCCTL_RSTPDWNMODULE() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetPCGCCTL_PHYSLEEP(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetPCGCCTL_PHYSLEEP() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetPCGCCTL_L1SUSPENDED(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetPCGCCTL_L1SUSPENDED() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetPCGCCTL_RESETAFTERSUSP(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetPCGCCTL_RESETAFTERSUSP() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x100) >> 8 +} + +// USB_WRAP Peripheral +type USB_WRAP_Type struct { + OTG_CONF volatile.Register32 // 0x0 + TEST_CONF volatile.Register32 // 0x4 + _ [1012]byte + DATE volatile.Register32 // 0x3FC +} + +// USB_WRAP.OTG_CONF: USB OTG Wrapper Configure Register +func (o *USB_WRAP_Type) SetOTG_CONF_SRP_SESSEND_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x1)|value) +} +func (o *USB_WRAP_Type) GetOTG_CONF_SRP_SESSEND_OVERRIDE() uint32 { + return volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x1 +} +func (o *USB_WRAP_Type) SetOTG_CONF_SRP_SESSEND_VALUE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_WRAP_Type) GetOTG_CONF_SRP_SESSEND_VALUE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PHY_SEL() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x4) >> 2 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DFIFO_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x8)|value<<3) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DFIFO_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x8) >> 3 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DBNCE_FLTR_BYPASS(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x10)|value<<4) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DBNCE_FLTR_BYPASS() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x10) >> 4 +} +func (o *USB_WRAP_Type) SetOTG_CONF_EXCHG_PINS_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x20)|value<<5) +} +func (o *USB_WRAP_Type) GetOTG_CONF_EXCHG_PINS_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x20) >> 5 +} +func (o *USB_WRAP_Type) SetOTG_CONF_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x40)|value<<6) +} +func (o *USB_WRAP_Type) GetOTG_CONF_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x40) >> 6 +} +func (o *USB_WRAP_Type) SetOTG_CONF_VREFH(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x180)|value<<7) +} +func (o *USB_WRAP_Type) GetOTG_CONF_VREFH() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x180) >> 7 +} +func (o *USB_WRAP_Type) SetOTG_CONF_VREFL(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x600)|value<<9) +} +func (o *USB_WRAP_Type) GetOTG_CONF_VREFL() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x600) >> 9 +} +func (o *USB_WRAP_Type) SetOTG_CONF_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *USB_WRAP_Type) GetOTG_CONF_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x800) >> 11 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x1000) >> 12 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x2000) >> 13 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x4000) >> 14 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x8000) >> 15 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x10000) >> 16 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x20000) >> 17 +} +func (o *USB_WRAP_Type) SetOTG_CONF_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *USB_WRAP_Type) GetOTG_CONF_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x40000) >> 18 +} +func (o *USB_WRAP_Type) SetOTG_CONF_AHB_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *USB_WRAP_Type) GetOTG_CONF_AHB_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x80000) >> 19 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PHY_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PHY_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x100000) >> 20 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PHY_TX_EDGE_SEL(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PHY_TX_EDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x200000) >> 21 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DFIFO_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DFIFO_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x400000) >> 22 +} +func (o *USB_WRAP_Type) SetOTG_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_WRAP_Type) GetOTG_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x80000000) >> 31 +} + +// USB_WRAP.TEST_CONF: USB Internal PHY Testing Register +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_ENABLE(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x1)|value) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_ENABLE() uint32 { + return volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x1 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_USB_OE(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_USB_OE() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_TX_DP(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_TX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x4) >> 2 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_TX_DM(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x8)|value<<3) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_TX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x8) >> 3 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_RCV(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x10)|value<<4) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_RCV() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x10) >> 4 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_DP(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x20)|value<<5) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x20) >> 5 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_DM(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x40)|value<<6) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x40) >> 6 +} + +// USB_WRAP.DATE: Version Control Register +func (o *USB_WRAP_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *USB_WRAP_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// XTS-AES-128 Flash Encryption +type XTS_AES_Type struct { + _ [256]byte + PLAIN_0 volatile.Register32 // 0x100 + PLAIN_1 volatile.Register32 // 0x104 + PLAIN_2 volatile.Register32 // 0x108 + PLAIN_3 volatile.Register32 // 0x10C + PLAIN_4 volatile.Register32 // 0x110 + PLAIN_5 volatile.Register32 // 0x114 + PLAIN_6 volatile.Register32 // 0x118 + PLAIN_7 volatile.Register32 // 0x11C + PLAIN_8 volatile.Register32 // 0x120 + PLAIN_9 volatile.Register32 // 0x124 + PLAIN_10 volatile.Register32 // 0x128 + PLAIN_11 volatile.Register32 // 0x12C + PLAIN_12 volatile.Register32 // 0x130 + PLAIN_13 volatile.Register32 // 0x134 + PLAIN_14 volatile.Register32 // 0x138 + PLAIN_15 volatile.Register32 // 0x13C + LINESIZE volatile.Register32 // 0x140 + DESTINATION volatile.Register32 // 0x144 + PHYSICAL_ADDRESS volatile.Register32 // 0x148 + TRIGGER volatile.Register32 // 0x14C + RELEASE volatile.Register32 // 0x150 + DESTROY volatile.Register32 // 0x154 + STATE volatile.Register32 // 0x158 + DATE volatile.Register32 // 0x15C +} + +// XTS_AES.PLAIN_0: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_0(value uint32) { + volatile.StoreUint32(&o.PLAIN_0.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_0() uint32 { + return volatile.LoadUint32(&o.PLAIN_0.Reg) +} + +// XTS_AES.PLAIN_1: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_1(value uint32) { + volatile.StoreUint32(&o.PLAIN_1.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_1() uint32 { + return volatile.LoadUint32(&o.PLAIN_1.Reg) +} + +// XTS_AES.PLAIN_2: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_2(value uint32) { + volatile.StoreUint32(&o.PLAIN_2.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_2() uint32 { + return volatile.LoadUint32(&o.PLAIN_2.Reg) +} + +// XTS_AES.PLAIN_3: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_3(value uint32) { + volatile.StoreUint32(&o.PLAIN_3.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_3() uint32 { + return volatile.LoadUint32(&o.PLAIN_3.Reg) +} + +// XTS_AES.PLAIN_4: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_4(value uint32) { + volatile.StoreUint32(&o.PLAIN_4.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_4() uint32 { + return volatile.LoadUint32(&o.PLAIN_4.Reg) +} + +// XTS_AES.PLAIN_5: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_5(value uint32) { + volatile.StoreUint32(&o.PLAIN_5.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_5() uint32 { + return volatile.LoadUint32(&o.PLAIN_5.Reg) +} + +// XTS_AES.PLAIN_6: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_6(value uint32) { + volatile.StoreUint32(&o.PLAIN_6.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_6() uint32 { + return volatile.LoadUint32(&o.PLAIN_6.Reg) +} + +// XTS_AES.PLAIN_7: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_7(value uint32) { + volatile.StoreUint32(&o.PLAIN_7.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_7() uint32 { + return volatile.LoadUint32(&o.PLAIN_7.Reg) +} + +// XTS_AES.PLAIN_8: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_8(value uint32) { + volatile.StoreUint32(&o.PLAIN_8.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_8() uint32 { + return volatile.LoadUint32(&o.PLAIN_8.Reg) +} + +// XTS_AES.PLAIN_9: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_9(value uint32) { + volatile.StoreUint32(&o.PLAIN_9.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_9() uint32 { + return volatile.LoadUint32(&o.PLAIN_9.Reg) +} + +// XTS_AES.PLAIN_10: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_10(value uint32) { + volatile.StoreUint32(&o.PLAIN_10.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_10() uint32 { + return volatile.LoadUint32(&o.PLAIN_10.Reg) +} + +// XTS_AES.PLAIN_11: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_11(value uint32) { + volatile.StoreUint32(&o.PLAIN_11.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_11() uint32 { + return volatile.LoadUint32(&o.PLAIN_11.Reg) +} + +// XTS_AES.PLAIN_12: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_12(value uint32) { + volatile.StoreUint32(&o.PLAIN_12.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_12() uint32 { + return volatile.LoadUint32(&o.PLAIN_12.Reg) +} + +// XTS_AES.PLAIN_13: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_13(value uint32) { + volatile.StoreUint32(&o.PLAIN_13.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_13() uint32 { + return volatile.LoadUint32(&o.PLAIN_13.Reg) +} + +// XTS_AES.PLAIN_14: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_14(value uint32) { + volatile.StoreUint32(&o.PLAIN_14.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_14() uint32 { + return volatile.LoadUint32(&o.PLAIN_14.Reg) +} + +// XTS_AES.PLAIN_15: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_15(value uint32) { + volatile.StoreUint32(&o.PLAIN_15.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_15() uint32 { + return volatile.LoadUint32(&o.PLAIN_15.Reg) +} + +// XTS_AES.LINESIZE: Configures the size of target memory space +func (o *XTS_AES_Type) SetLINESIZE(value uint32) { + volatile.StoreUint32(&o.LINESIZE.Reg, volatile.LoadUint32(&o.LINESIZE.Reg)&^(0x3)|value) +} +func (o *XTS_AES_Type) GetLINESIZE() uint32 { + return volatile.LoadUint32(&o.LINESIZE.Reg) & 0x3 +} + +// XTS_AES.DESTINATION: Configures the type of the external memory +func (o *XTS_AES_Type) SetDESTINATION(value uint32) { + volatile.StoreUint32(&o.DESTINATION.Reg, volatile.LoadUint32(&o.DESTINATION.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetDESTINATION() uint32 { + return volatile.LoadUint32(&o.DESTINATION.Reg) & 0x1 +} + +// XTS_AES.PHYSICAL_ADDRESS: Physical address +func (o *XTS_AES_Type) SetPHYSICAL_ADDRESS(value uint32) { + volatile.StoreUint32(&o.PHYSICAL_ADDRESS.Reg, volatile.LoadUint32(&o.PHYSICAL_ADDRESS.Reg)&^(0x3fffffff)|value) +} +func (o *XTS_AES_Type) GetPHYSICAL_ADDRESS() uint32 { + return volatile.LoadUint32(&o.PHYSICAL_ADDRESS.Reg) & 0x3fffffff +} + +// XTS_AES.TRIGGER: Activates AES algorithm +func (o *XTS_AES_Type) SetTRIGGER(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetTRIGGER() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} + +// XTS_AES.RELEASE: Release control +func (o *XTS_AES_Type) SetRELEASE(value uint32) { + volatile.StoreUint32(&o.RELEASE.Reg, volatile.LoadUint32(&o.RELEASE.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetRELEASE() uint32 { + return volatile.LoadUint32(&o.RELEASE.Reg) & 0x1 +} + +// XTS_AES.DESTROY: Destroys control +func (o *XTS_AES_Type) SetDESTROY(value uint32) { + volatile.StoreUint32(&o.DESTROY.Reg, volatile.LoadUint32(&o.DESTROY.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetDESTROY() uint32 { + return volatile.LoadUint32(&o.DESTROY.Reg) & 0x1 +} + +// XTS_AES.STATE: Status register +func (o *XTS_AES_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *XTS_AES_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// XTS_AES.DATE: Version control register +func (o *XTS_AES_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *XTS_AES_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Constants for AES: AES (Advanced Encryption Standard) Accelerator +const ( + // KEY_0: AES key register %s + // Position of KEY field. + AES_KEY_KEY_Pos = 0x0 + // Bit mask of KEY field. + AES_KEY_KEY_Msk = 0xffffffff + + // TEXT_IN_0: Source data register %s + // Position of TEXT_IN field. + AES_TEXT_IN_TEXT_IN_Pos = 0x0 + // Bit mask of TEXT_IN field. + AES_TEXT_IN_TEXT_IN_Msk = 0xffffffff + + // TEXT_OUT_0: Result data register %s + // Position of TEXT_OUT field. + AES_TEXT_OUT_TEXT_OUT_Pos = 0x0 + // Bit mask of TEXT_OUT field. + AES_TEXT_OUT_TEXT_OUT_Msk = 0xffffffff + + // MODE: AES working mode configuration register + // Position of MODE field. + AES_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + AES_MODE_MODE_Msk = 0x7 + + // ENDIAN: Endian configuration register + // Position of ENDIAN field. + AES_ENDIAN_ENDIAN_Pos = 0x0 + // Bit mask of ENDIAN field. + AES_ENDIAN_ENDIAN_Msk = 0x3f + + // TRIGGER: Operation start controlling register + // Position of TRIGGER field. + AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + AES_TRIGGER_TRIGGER = 0x1 + + // STATE: Operation status register + // Position of STATE field. + AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + AES_STATE_STATE_Msk = 0x3 + + // IV_0: initialization vector + // Position of IV field. + AES_IV_IV_Pos = 0x0 + // Bit mask of IV field. + AES_IV_IV_Msk = 0xffffffff + + // H_0: GCM hash subkey + // Position of H field. + AES_H_H_Pos = 0x0 + // Bit mask of H field. + AES_H_H_Msk = 0xffffffff + + // J0_0: J0 + // Position of J0 field. + AES_J0_J0_Pos = 0x0 + // Bit mask of J0 field. + AES_J0_J0_Msk = 0xffffffff + + // T0_0: T0 + // Position of T0 field. + AES_T0_T0_Pos = 0x0 + // Bit mask of T0 field. + AES_T0_T0_Msk = 0xffffffff + + // DMA_ENABLE: DMA enable register + // Position of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Pos = 0x0 + // Bit mask of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Msk = 0x1 + // Bit DMA_ENABLE. + AES_DMA_ENABLE_DMA_ENABLE = 0x1 + + // BLOCK_MODE: Block operation type register + // Position of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Pos = 0x0 + // Bit mask of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Msk = 0x7 + + // BLOCK_NUM: Block number configuration register + // Position of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Pos = 0x0 + // Bit mask of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Msk = 0xffffffff + + // INC_SEL: Standard incrementing function register + // Position of INC_SEL field. + AES_INC_SEL_INC_SEL_Pos = 0x0 + // Bit mask of INC_SEL field. + AES_INC_SEL_INC_SEL_Msk = 0x1 + // Bit INC_SEL. + AES_INC_SEL_INC_SEL = 0x1 + + // AAD_BLOCK_NUM: AAD block number configuration register + // Position of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Pos = 0x0 + // Bit mask of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Msk = 0xffffffff + + // REMAINDER_BIT_NUM: Remainder bit number of plaintext/ciphertext + // Position of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Pos = 0x0 + // Bit mask of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Msk = 0x7f + + // CONTINUE_OP: Operation continue controlling register + // Position of CONTINUE_OP field. + AES_CONTINUE_OP_CONTINUE_OP_Pos = 0x0 + // Bit mask of CONTINUE_OP field. + AES_CONTINUE_OP_CONTINUE_OP_Msk = 0x1 + // Bit CONTINUE_OP. + AES_CONTINUE_OP_CONTINUE_OP = 0x1 + + // INT_CLR: DMA-AES interrupt clear register + // Position of INT_CLR field. + AES_INT_CLR_INT_CLR_Pos = 0x0 + // Bit mask of INT_CLR field. + AES_INT_CLR_INT_CLR_Msk = 0x1 + // Bit INT_CLR. + AES_INT_CLR_INT_CLR = 0x1 + + // INT_ENA: DMA-AES interrupt enable register + // Position of INT_ENA field. + AES_INT_ENA_INT_ENA_Pos = 0x0 + // Bit mask of INT_ENA field. + AES_INT_ENA_INT_ENA_Msk = 0x1 + // Bit INT_ENA. + AES_INT_ENA_INT_ENA = 0x1 + + // DATE: Version control register + // Position of DATE field. + AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + AES_DATE_DATE_Msk = 0x3fffffff + + // DMA_EXIT: Operation exit controlling register + // Position of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Pos = 0x0 + // Bit mask of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Msk = 0x1 + // Bit DMA_EXIT. + AES_DMA_EXIT_DMA_EXIT = 0x1 +) + +// Constants for APB_SARADC: SAR (Successive Approximation Register) Analog-to-Digital Converter +const ( + // CTRL: DIG ADC common configuration + // Position of START_FORCE field. + APB_SARADC_CTRL_START_FORCE_Pos = 0x0 + // Bit mask of START_FORCE field. + APB_SARADC_CTRL_START_FORCE_Msk = 0x1 + // Bit START_FORCE. + APB_SARADC_CTRL_START_FORCE = 0x1 + // Position of START field. + APB_SARADC_CTRL_START_Pos = 0x1 + // Bit mask of START field. + APB_SARADC_CTRL_START_Msk = 0x2 + // Bit START. + APB_SARADC_CTRL_START = 0x2 + // Position of WORK_MODE field. + APB_SARADC_CTRL_WORK_MODE_Pos = 0x3 + // Bit mask of WORK_MODE field. + APB_SARADC_CTRL_WORK_MODE_Msk = 0x18 + // Position of SAR_SEL field. + APB_SARADC_CTRL_SAR_SEL_Pos = 0x5 + // Bit mask of SAR_SEL field. + APB_SARADC_CTRL_SAR_SEL_Msk = 0x20 + // Bit SAR_SEL. + APB_SARADC_CTRL_SAR_SEL = 0x20 + // Position of SAR_CLK_GATED field. + APB_SARADC_CTRL_SAR_CLK_GATED_Pos = 0x6 + // Bit mask of SAR_CLK_GATED field. + APB_SARADC_CTRL_SAR_CLK_GATED_Msk = 0x40 + // Bit SAR_CLK_GATED. + APB_SARADC_CTRL_SAR_CLK_GATED = 0x40 + // Position of SAR_CLK_DIV field. + APB_SARADC_CTRL_SAR_CLK_DIV_Pos = 0x7 + // Bit mask of SAR_CLK_DIV field. + APB_SARADC_CTRL_SAR_CLK_DIV_Msk = 0x7f80 + // Position of SAR1_PATT_LEN field. + APB_SARADC_CTRL_SAR1_PATT_LEN_Pos = 0xf + // Bit mask of SAR1_PATT_LEN field. + APB_SARADC_CTRL_SAR1_PATT_LEN_Msk = 0x78000 + // Position of SAR2_PATT_LEN field. + APB_SARADC_CTRL_SAR2_PATT_LEN_Pos = 0x13 + // Bit mask of SAR2_PATT_LEN field. + APB_SARADC_CTRL_SAR2_PATT_LEN_Msk = 0x780000 + // Position of SAR1_PATT_P_CLEAR field. + APB_SARADC_CTRL_SAR1_PATT_P_CLEAR_Pos = 0x17 + // Bit mask of SAR1_PATT_P_CLEAR field. + APB_SARADC_CTRL_SAR1_PATT_P_CLEAR_Msk = 0x800000 + // Bit SAR1_PATT_P_CLEAR. + APB_SARADC_CTRL_SAR1_PATT_P_CLEAR = 0x800000 + // Position of SAR2_PATT_P_CLEAR field. + APB_SARADC_CTRL_SAR2_PATT_P_CLEAR_Pos = 0x18 + // Bit mask of SAR2_PATT_P_CLEAR field. + APB_SARADC_CTRL_SAR2_PATT_P_CLEAR_Msk = 0x1000000 + // Bit SAR2_PATT_P_CLEAR. + APB_SARADC_CTRL_SAR2_PATT_P_CLEAR = 0x1000000 + // Position of DATA_SAR_SEL field. + APB_SARADC_CTRL_DATA_SAR_SEL_Pos = 0x19 + // Bit mask of DATA_SAR_SEL field. + APB_SARADC_CTRL_DATA_SAR_SEL_Msk = 0x2000000 + // Bit DATA_SAR_SEL. + APB_SARADC_CTRL_DATA_SAR_SEL = 0x2000000 + // Position of DATA_TO_I2S field. + APB_SARADC_CTRL_DATA_TO_I2S_Pos = 0x1a + // Bit mask of DATA_TO_I2S field. + APB_SARADC_CTRL_DATA_TO_I2S_Msk = 0x4000000 + // Bit DATA_TO_I2S. + APB_SARADC_CTRL_DATA_TO_I2S = 0x4000000 + // Position of XPD_SAR_FORCE field. + APB_SARADC_CTRL_XPD_SAR_FORCE_Pos = 0x1b + // Bit mask of XPD_SAR_FORCE field. + APB_SARADC_CTRL_XPD_SAR_FORCE_Msk = 0x18000000 + // Position of WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_WAIT_ARB_CYCLE_Pos = 0x1e + // Bit mask of WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_WAIT_ARB_CYCLE_Msk = 0xc0000000 + + // CTRL2: DIG ADC common configuration + // Position of MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_MEAS_NUM_LIMIT_Pos = 0x0 + // Bit mask of MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_MEAS_NUM_LIMIT_Msk = 0x1 + // Bit MEAS_NUM_LIMIT. + APB_SARADC_CTRL2_MEAS_NUM_LIMIT = 0x1 + // Position of MAX_MEAS_NUM field. + APB_SARADC_CTRL2_MAX_MEAS_NUM_Pos = 0x1 + // Bit mask of MAX_MEAS_NUM field. + APB_SARADC_CTRL2_MAX_MEAS_NUM_Msk = 0x1fe + // Position of SAR1_INV field. + APB_SARADC_CTRL2_SAR1_INV_Pos = 0x9 + // Bit mask of SAR1_INV field. + APB_SARADC_CTRL2_SAR1_INV_Msk = 0x200 + // Bit SAR1_INV. + APB_SARADC_CTRL2_SAR1_INV = 0x200 + // Position of SAR2_INV field. + APB_SARADC_CTRL2_SAR2_INV_Pos = 0xa + // Bit mask of SAR2_INV field. + APB_SARADC_CTRL2_SAR2_INV_Msk = 0x400 + // Bit SAR2_INV. + APB_SARADC_CTRL2_SAR2_INV = 0x400 + // Position of TIMER_SEL field. + APB_SARADC_CTRL2_TIMER_SEL_Pos = 0xb + // Bit mask of TIMER_SEL field. + APB_SARADC_CTRL2_TIMER_SEL_Msk = 0x800 + // Bit TIMER_SEL. + APB_SARADC_CTRL2_TIMER_SEL = 0x800 + // Position of TIMER_TARGET field. + APB_SARADC_CTRL2_TIMER_TARGET_Pos = 0xc + // Bit mask of TIMER_TARGET field. + APB_SARADC_CTRL2_TIMER_TARGET_Msk = 0xfff000 + // Position of TIMER_EN field. + APB_SARADC_CTRL2_TIMER_EN_Pos = 0x18 + // Bit mask of TIMER_EN field. + APB_SARADC_CTRL2_TIMER_EN_Msk = 0x1000000 + // Bit TIMER_EN. + APB_SARADC_CTRL2_TIMER_EN = 0x1000000 + + // FSM: digital adc control register + // Position of SAMPLE_NUM field. + APB_SARADC_FSM_SAMPLE_NUM_Pos = 0x10 + // Bit mask of SAMPLE_NUM field. + APB_SARADC_FSM_SAMPLE_NUM_Msk = 0xff0000 + // Position of SAMPLE_CYCLE field. + APB_SARADC_FSM_SAMPLE_CYCLE_Pos = 0x18 + // Bit mask of SAMPLE_CYCLE field. + APB_SARADC_FSM_SAMPLE_CYCLE_Msk = 0xff000000 + + // FSM_WAIT: configure saradc fsm internal parameter base on test + // Position of XPD_WAIT field. + APB_SARADC_FSM_WAIT_XPD_WAIT_Pos = 0x0 + // Bit mask of XPD_WAIT field. + APB_SARADC_FSM_WAIT_XPD_WAIT_Msk = 0xff + // Position of RSTB_WAIT field. + APB_SARADC_FSM_WAIT_RSTB_WAIT_Pos = 0x8 + // Bit mask of RSTB_WAIT field. + APB_SARADC_FSM_WAIT_RSTB_WAIT_Msk = 0xff00 + // Position of STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_STANDBY_WAIT_Pos = 0x10 + // Bit mask of STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_STANDBY_WAIT_Msk = 0xff0000 + + // SAR1_STATUS: digital adc1 status + // Position of SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SAR1_STATUS_Pos = 0x0 + // Bit mask of SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SAR1_STATUS_Msk = 0xffffffff + + // SAR2_STATUS: digital adc2 status + // Position of SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SAR2_STATUS_Pos = 0x0 + // Bit mask of SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SAR2_STATUS_Msk = 0xffffffff + + // SAR1_PATT_TAB1: item 0 ~ 3 for pattern table 1 (each item one byte) + // Position of SAR1_PATT_TAB1 field. + APB_SARADC_SAR1_PATT_TAB1_SAR1_PATT_TAB1_Pos = 0x0 + // Bit mask of SAR1_PATT_TAB1 field. + APB_SARADC_SAR1_PATT_TAB1_SAR1_PATT_TAB1_Msk = 0xffffffff + + // SAR1_PATT_TAB2: Item 4 ~ 7 for pattern table 1 (each item one byte) + // Position of SAR1_PATT_TAB2 field. + APB_SARADC_SAR1_PATT_TAB2_SAR1_PATT_TAB2_Pos = 0x0 + // Bit mask of SAR1_PATT_TAB2 field. + APB_SARADC_SAR1_PATT_TAB2_SAR1_PATT_TAB2_Msk = 0xffffffff + + // SAR1_PATT_TAB3: Item 8 ~ 11 for pattern table 1 (each item one byte) + // Position of SAR1_PATT_TAB3 field. + APB_SARADC_SAR1_PATT_TAB3_SAR1_PATT_TAB3_Pos = 0x0 + // Bit mask of SAR1_PATT_TAB3 field. + APB_SARADC_SAR1_PATT_TAB3_SAR1_PATT_TAB3_Msk = 0xffffffff + + // SAR1_PATT_TAB4: Item 12 ~ 15 for pattern table 1 (each item one byte) + // Position of SAR1_PATT_TAB4 field. + APB_SARADC_SAR1_PATT_TAB4_SAR1_PATT_TAB4_Pos = 0x0 + // Bit mask of SAR1_PATT_TAB4 field. + APB_SARADC_SAR1_PATT_TAB4_SAR1_PATT_TAB4_Msk = 0xffffffff + + // SAR2_PATT_TAB1: item 0 ~ 3 for pattern table 2 (each item one byte) + // Position of SAR2_PATT_TAB1 field. + APB_SARADC_SAR2_PATT_TAB1_SAR2_PATT_TAB1_Pos = 0x0 + // Bit mask of SAR2_PATT_TAB1 field. + APB_SARADC_SAR2_PATT_TAB1_SAR2_PATT_TAB1_Msk = 0xffffffff + + // SAR2_PATT_TAB2: Item 4 ~ 7 for pattern table 2 (each item one byte) + // Position of SAR2_PATT_TAB2 field. + APB_SARADC_SAR2_PATT_TAB2_SAR2_PATT_TAB2_Pos = 0x0 + // Bit mask of SAR2_PATT_TAB2 field. + APB_SARADC_SAR2_PATT_TAB2_SAR2_PATT_TAB2_Msk = 0xffffffff + + // SAR2_PATT_TAB3: Item 8 ~ 11 for pattern table 2 (each item one byte) + // Position of SAR2_PATT_TAB3 field. + APB_SARADC_SAR2_PATT_TAB3_SAR2_PATT_TAB3_Pos = 0x0 + // Bit mask of SAR2_PATT_TAB3 field. + APB_SARADC_SAR2_PATT_TAB3_SAR2_PATT_TAB3_Msk = 0xffffffff + + // SAR2_PATT_TAB4: Item 12 ~ 15 for pattern table 2 (each item one byte) + // Position of SAR2_PATT_TAB4 field. + APB_SARADC_SAR2_PATT_TAB4_SAR2_PATT_TAB4_Pos = 0x0 + // Bit mask of SAR2_PATT_TAB4 field. + APB_SARADC_SAR2_PATT_TAB4_SAR2_PATT_TAB4_Msk = 0xffffffff + + // ARB_CTRL: Configure the settings of DIG ADC2 arbiter + // Position of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Pos = 0x2 + // Bit mask of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Msk = 0x4 + // Bit ADC_ARB_APB_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE = 0x4 + // Position of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Pos = 0x3 + // Bit mask of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Msk = 0x8 + // Bit ADC_ARB_RTC_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE = 0x8 + // Position of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Pos = 0x4 + // Bit mask of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Msk = 0x10 + // Bit ADC_ARB_WIFI_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE = 0x10 + // Position of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Pos = 0x5 + // Bit mask of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Msk = 0x20 + // Bit ADC_ARB_GRANT_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE = 0x20 + // Position of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Pos = 0x6 + // Bit mask of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Msk = 0xc0 + // Position of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Pos = 0x8 + // Bit mask of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Msk = 0x300 + // Position of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Pos = 0xa + // Bit mask of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Msk = 0xc00 + // Position of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Pos = 0xc + // Bit mask of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Msk = 0x1000 + // Bit ADC_ARB_FIX_PRIORITY. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY = 0x1000 + + // FILTER_CTRL: Configure the settings of DIG ADC2 filter + // Position of ADC2_FILTER_RESET field. + APB_SARADC_FILTER_CTRL_ADC2_FILTER_RESET_Pos = 0x0 + // Bit mask of ADC2_FILTER_RESET field. + APB_SARADC_FILTER_CTRL_ADC2_FILTER_RESET_Msk = 0x1 + // Bit ADC2_FILTER_RESET. + APB_SARADC_FILTER_CTRL_ADC2_FILTER_RESET = 0x1 + // Position of ADC1_FILTER_RESET field. + APB_SARADC_FILTER_CTRL_ADC1_FILTER_RESET_Pos = 0x1 + // Bit mask of ADC1_FILTER_RESET field. + APB_SARADC_FILTER_CTRL_ADC1_FILTER_RESET_Msk = 0x2 + // Bit ADC1_FILTER_RESET. + APB_SARADC_FILTER_CTRL_ADC1_FILTER_RESET = 0x2 + // Position of ADC2_FILTER_FACTOR field. + APB_SARADC_FILTER_CTRL_ADC2_FILTER_FACTOR_Pos = 0x10 + // Bit mask of ADC2_FILTER_FACTOR field. + APB_SARADC_FILTER_CTRL_ADC2_FILTER_FACTOR_Msk = 0x7f0000 + // Position of ADC1_FILTER_FACTOR field. + APB_SARADC_FILTER_CTRL_ADC1_FILTER_FACTOR_Pos = 0x17 + // Bit mask of ADC1_FILTER_FACTOR field. + APB_SARADC_FILTER_CTRL_ADC1_FILTER_FACTOR_Msk = 0x3f800000 + // Position of ADC2_FILTER_EN field. + APB_SARADC_FILTER_CTRL_ADC2_FILTER_EN_Pos = 0x1e + // Bit mask of ADC2_FILTER_EN field. + APB_SARADC_FILTER_CTRL_ADC2_FILTER_EN_Msk = 0x40000000 + // Bit ADC2_FILTER_EN. + APB_SARADC_FILTER_CTRL_ADC2_FILTER_EN = 0x40000000 + // Position of ADC1_FILTER_EN field. + APB_SARADC_FILTER_CTRL_ADC1_FILTER_EN_Pos = 0x1f + // Bit mask of ADC1_FILTER_EN field. + APB_SARADC_FILTER_CTRL_ADC1_FILTER_EN_Msk = 0x80000000 + // Bit ADC1_FILTER_EN. + APB_SARADC_FILTER_CTRL_ADC1_FILTER_EN = 0x80000000 + + // FILTER_STATUS: Data status of DIG ADC2 filter + // Position of ADC2_FILTER_DATA field. + APB_SARADC_FILTER_STATUS_ADC2_FILTER_DATA_Pos = 0x0 + // Bit mask of ADC2_FILTER_DATA field. + APB_SARADC_FILTER_STATUS_ADC2_FILTER_DATA_Msk = 0xffff + // Position of ADC1_FILTER_DATA field. + APB_SARADC_FILTER_STATUS_ADC1_FILTER_DATA_Pos = 0x10 + // Bit mask of ADC1_FILTER_DATA field. + APB_SARADC_FILTER_STATUS_ADC1_FILTER_DATA_Msk = 0xffff0000 + + // THRES_CTRL: Configure monitor threshold for DIG ADC2 + // Position of CLK_EN field. + APB_SARADC_THRES_CTRL_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + APB_SARADC_THRES_CTRL_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + APB_SARADC_THRES_CTRL_CLK_EN = 0x1 + // Position of ADC2_THRES_MODE field. + APB_SARADC_THRES_CTRL_ADC2_THRES_MODE_Pos = 0x2 + // Bit mask of ADC2_THRES_MODE field. + APB_SARADC_THRES_CTRL_ADC2_THRES_MODE_Msk = 0x4 + // Bit ADC2_THRES_MODE. + APB_SARADC_THRES_CTRL_ADC2_THRES_MODE = 0x4 + // Position of ADC1_THRES_MODE field. + APB_SARADC_THRES_CTRL_ADC1_THRES_MODE_Pos = 0x3 + // Bit mask of ADC1_THRES_MODE field. + APB_SARADC_THRES_CTRL_ADC1_THRES_MODE_Msk = 0x8 + // Bit ADC1_THRES_MODE. + APB_SARADC_THRES_CTRL_ADC1_THRES_MODE = 0x8 + // Position of ADC2_THRES field. + APB_SARADC_THRES_CTRL_ADC2_THRES_Pos = 0x4 + // Bit mask of ADC2_THRES field. + APB_SARADC_THRES_CTRL_ADC2_THRES_Msk = 0x1fff0 + // Position of ADC1_THRES field. + APB_SARADC_THRES_CTRL_ADC1_THRES_Pos = 0x11 + // Bit mask of ADC1_THRES field. + APB_SARADC_THRES_CTRL_ADC1_THRES_Msk = 0x3ffe0000 + // Position of ADC2_THRES_EN field. + APB_SARADC_THRES_CTRL_ADC2_THRES_EN_Pos = 0x1e + // Bit mask of ADC2_THRES_EN field. + APB_SARADC_THRES_CTRL_ADC2_THRES_EN_Msk = 0x40000000 + // Bit ADC2_THRES_EN. + APB_SARADC_THRES_CTRL_ADC2_THRES_EN = 0x40000000 + // Position of ADC1_THRES_EN field. + APB_SARADC_THRES_CTRL_ADC1_THRES_EN_Pos = 0x1f + // Bit mask of ADC1_THRES_EN field. + APB_SARADC_THRES_CTRL_ADC1_THRES_EN_Msk = 0x80000000 + // Bit ADC1_THRES_EN. + APB_SARADC_THRES_CTRL_ADC1_THRES_EN = 0x80000000 + + // INT_ENA: Enable DIG ADC interrupts + // Position of ADC2_THRES_INT_ENA field. + APB_SARADC_INT_ENA_ADC2_THRES_INT_ENA_Pos = 0x1c + // Bit mask of ADC2_THRES_INT_ENA field. + APB_SARADC_INT_ENA_ADC2_THRES_INT_ENA_Msk = 0x10000000 + // Bit ADC2_THRES_INT_ENA. + APB_SARADC_INT_ENA_ADC2_THRES_INT_ENA = 0x10000000 + // Position of ADC1_THRES_INT_ENA field. + APB_SARADC_INT_ENA_ADC1_THRES_INT_ENA_Pos = 0x1d + // Bit mask of ADC1_THRES_INT_ENA field. + APB_SARADC_INT_ENA_ADC1_THRES_INT_ENA_Msk = 0x20000000 + // Bit ADC1_THRES_INT_ENA. + APB_SARADC_INT_ENA_ADC1_THRES_INT_ENA = 0x20000000 + // Position of ADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_ADC2_DONE_INT_ENA_Pos = 0x1e + // Bit mask of ADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_ADC2_DONE_INT_ENA_Msk = 0x40000000 + // Bit ADC2_DONE_INT_ENA. + APB_SARADC_INT_ENA_ADC2_DONE_INT_ENA = 0x40000000 + // Position of ADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_ADC1_DONE_INT_ENA_Pos = 0x1f + // Bit mask of ADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_ADC1_DONE_INT_ENA_Msk = 0x80000000 + // Bit ADC1_DONE_INT_ENA. + APB_SARADC_INT_ENA_ADC1_DONE_INT_ENA = 0x80000000 + + // INT_RAW: DIG ADC interrupt raw bits + // Position of ADC2_THRES_INT_RAW field. + APB_SARADC_INT_RAW_ADC2_THRES_INT_RAW_Pos = 0x1c + // Bit mask of ADC2_THRES_INT_RAW field. + APB_SARADC_INT_RAW_ADC2_THRES_INT_RAW_Msk = 0x10000000 + // Bit ADC2_THRES_INT_RAW. + APB_SARADC_INT_RAW_ADC2_THRES_INT_RAW = 0x10000000 + // Position of ADC1_THRES_INT_RAW field. + APB_SARADC_INT_RAW_ADC1_THRES_INT_RAW_Pos = 0x1d + // Bit mask of ADC1_THRES_INT_RAW field. + APB_SARADC_INT_RAW_ADC1_THRES_INT_RAW_Msk = 0x20000000 + // Bit ADC1_THRES_INT_RAW. + APB_SARADC_INT_RAW_ADC1_THRES_INT_RAW = 0x20000000 + // Position of ADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_ADC2_DONE_INT_RAW_Pos = 0x1e + // Bit mask of ADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_ADC2_DONE_INT_RAW_Msk = 0x40000000 + // Bit ADC2_DONE_INT_RAW. + APB_SARADC_INT_RAW_ADC2_DONE_INT_RAW = 0x40000000 + // Position of ADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_ADC1_DONE_INT_RAW_Pos = 0x1f + // Bit mask of ADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_ADC1_DONE_INT_RAW_Msk = 0x80000000 + // Bit ADC1_DONE_INT_RAW. + APB_SARADC_INT_RAW_ADC1_DONE_INT_RAW = 0x80000000 + + // INT_ST: DIG ADC interrupt status + // Position of ADC2_THRES_INT_ST field. + APB_SARADC_INT_ST_ADC2_THRES_INT_ST_Pos = 0x1c + // Bit mask of ADC2_THRES_INT_ST field. + APB_SARADC_INT_ST_ADC2_THRES_INT_ST_Msk = 0x10000000 + // Bit ADC2_THRES_INT_ST. + APB_SARADC_INT_ST_ADC2_THRES_INT_ST = 0x10000000 + // Position of ADC1_THRES_INT_ST field. + APB_SARADC_INT_ST_ADC1_THRES_INT_ST_Pos = 0x1d + // Bit mask of ADC1_THRES_INT_ST field. + APB_SARADC_INT_ST_ADC1_THRES_INT_ST_Msk = 0x20000000 + // Bit ADC1_THRES_INT_ST. + APB_SARADC_INT_ST_ADC1_THRES_INT_ST = 0x20000000 + // Position of ADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_ADC2_DONE_INT_ST_Pos = 0x1e + // Bit mask of ADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_ADC2_DONE_INT_ST_Msk = 0x40000000 + // Bit ADC2_DONE_INT_ST. + APB_SARADC_INT_ST_ADC2_DONE_INT_ST = 0x40000000 + // Position of ADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_ADC1_DONE_INT_ST_Pos = 0x1f + // Bit mask of ADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_ADC1_DONE_INT_ST_Msk = 0x80000000 + // Bit ADC1_DONE_INT_ST. + APB_SARADC_INT_ST_ADC1_DONE_INT_ST = 0x80000000 + + // INT_CLR: Clear DIG ADC interrupts + // Position of ADC2_THRES_INT_CLR field. + APB_SARADC_INT_CLR_ADC2_THRES_INT_CLR_Pos = 0x1c + // Bit mask of ADC2_THRES_INT_CLR field. + APB_SARADC_INT_CLR_ADC2_THRES_INT_CLR_Msk = 0x10000000 + // Bit ADC2_THRES_INT_CLR. + APB_SARADC_INT_CLR_ADC2_THRES_INT_CLR = 0x10000000 + // Position of ADC1_THRES_INT_CLR field. + APB_SARADC_INT_CLR_ADC1_THRES_INT_CLR_Pos = 0x1d + // Bit mask of ADC1_THRES_INT_CLR field. + APB_SARADC_INT_CLR_ADC1_THRES_INT_CLR_Msk = 0x20000000 + // Bit ADC1_THRES_INT_CLR. + APB_SARADC_INT_CLR_ADC1_THRES_INT_CLR = 0x20000000 + // Position of ADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_ADC2_DONE_INT_CLR_Pos = 0x1e + // Bit mask of ADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_ADC2_DONE_INT_CLR_Msk = 0x40000000 + // Bit ADC2_DONE_INT_CLR. + APB_SARADC_INT_CLR_ADC2_DONE_INT_CLR = 0x40000000 + // Position of ADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_ADC1_DONE_INT_CLR_Pos = 0x1f + // Bit mask of ADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_ADC1_DONE_INT_CLR_Msk = 0x80000000 + // Bit ADC1_DONE_INT_CLR. + APB_SARADC_INT_CLR_ADC1_DONE_INT_CLR = 0x80000000 + + // DMA_CONF: Configure digital ADC DMA path + // Position of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Pos = 0x0 + // Bit mask of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Msk = 0xffff + // Position of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Pos = 0x1e + // Bit mask of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Msk = 0x40000000 + // Bit APB_ADC_RESET_FSM. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM = 0x40000000 + // Position of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Pos = 0x1f + // Bit mask of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Msk = 0x80000000 + // Bit APB_ADC_TRANS. + APB_SARADC_DMA_CONF_APB_ADC_TRANS = 0x80000000 + + // CLKM_CONF: Configure DIG ADC clock + // Position of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Msk = 0xff + // Position of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Pos = 0x8 + // Bit mask of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Msk = 0x3f00 + // Position of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Pos = 0xe + // Bit mask of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Msk = 0xfc000 + // Position of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Pos = 0x15 + // Bit mask of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Msk = 0x600000 + + // APB_DAC_CTRL: Configure DAC settings + // Position of DAC_TIMER_TARGET field. + APB_SARADC_APB_DAC_CTRL_DAC_TIMER_TARGET_Pos = 0x0 + // Bit mask of DAC_TIMER_TARGET field. + APB_SARADC_APB_DAC_CTRL_DAC_TIMER_TARGET_Msk = 0xfff + // Position of DAC_TIMER_EN field. + APB_SARADC_APB_DAC_CTRL_DAC_TIMER_EN_Pos = 0xc + // Bit mask of DAC_TIMER_EN field. + APB_SARADC_APB_DAC_CTRL_DAC_TIMER_EN_Msk = 0x1000 + // Bit DAC_TIMER_EN. + APB_SARADC_APB_DAC_CTRL_DAC_TIMER_EN = 0x1000 + // Position of APB_DAC_ALTER_MODE field. + APB_SARADC_APB_DAC_CTRL_APB_DAC_ALTER_MODE_Pos = 0xd + // Bit mask of APB_DAC_ALTER_MODE field. + APB_SARADC_APB_DAC_CTRL_APB_DAC_ALTER_MODE_Msk = 0x2000 + // Bit APB_DAC_ALTER_MODE. + APB_SARADC_APB_DAC_CTRL_APB_DAC_ALTER_MODE = 0x2000 + // Position of APB_DAC_TRANS field. + APB_SARADC_APB_DAC_CTRL_APB_DAC_TRANS_Pos = 0xe + // Bit mask of APB_DAC_TRANS field. + APB_SARADC_APB_DAC_CTRL_APB_DAC_TRANS_Msk = 0x4000 + // Bit APB_DAC_TRANS. + APB_SARADC_APB_DAC_CTRL_APB_DAC_TRANS = 0x4000 + // Position of DAC_RESET_FIFO field. + APB_SARADC_APB_DAC_CTRL_DAC_RESET_FIFO_Pos = 0xf + // Bit mask of DAC_RESET_FIFO field. + APB_SARADC_APB_DAC_CTRL_DAC_RESET_FIFO_Msk = 0x8000 + // Bit DAC_RESET_FIFO. + APB_SARADC_APB_DAC_CTRL_DAC_RESET_FIFO = 0x8000 + // Position of APB_DAC_RST field. + APB_SARADC_APB_DAC_CTRL_APB_DAC_RST_Pos = 0x10 + // Bit mask of APB_DAC_RST field. + APB_SARADC_APB_DAC_CTRL_APB_DAC_RST_Msk = 0x10000 + // Bit APB_DAC_RST. + APB_SARADC_APB_DAC_CTRL_APB_DAC_RST = 0x10000 + + // APB_CTRL_DATE: Version control register + // Position of APB_CTRL_DATE field. + APB_SARADC_APB_CTRL_DATE_APB_CTRL_DATE_Pos = 0x0 + // Bit mask of APB_CTRL_DATE field. + APB_SARADC_APB_CTRL_DATE_APB_CTRL_DATE_Msk = 0xffffffff +) + +// Constants for BB: BB Peripheral +const ( + // BBPD_CTRL: Baseband control register + // Position of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Pos = 0x0 + // Bit mask of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Msk = 0x1 + // Bit DC_EST_FORCE_PD. + BB_BBPD_CTRL_DC_EST_FORCE_PD = 0x1 + // Position of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Pos = 0x1 + // Bit mask of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Msk = 0x2 + // Bit DC_EST_FORCE_PU. + BB_BBPD_CTRL_DC_EST_FORCE_PU = 0x2 + // Position of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Pos = 0x2 + // Bit mask of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Msk = 0x4 + // Bit FFT_FORCE_PD. + BB_BBPD_CTRL_FFT_FORCE_PD = 0x4 + // Position of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Pos = 0x3 + // Bit mask of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Msk = 0x8 + // Bit FFT_FORCE_PU. + BB_BBPD_CTRL_FFT_FORCE_PU = 0x8 +) + +// Constants for DEDICATED_GPIO: DEDICATED_GPIO Peripheral +const ( + // OUT_DRT: Dedicated GPIO directive output register + // Position of VLAUE field. + DEDIC_GPIO_OUT_DRT_VLAUE_Pos = 0x0 + // Bit mask of VLAUE field. + DEDIC_GPIO_OUT_DRT_VLAUE_Msk = 0xff + + // OUT_MSK: Dedicated GPIO mask output register + // Position of OUT_VALUE field. + DEDIC_GPIO_OUT_MSK_OUT_VALUE_Pos = 0x0 + // Bit mask of OUT_VALUE field. + DEDIC_GPIO_OUT_MSK_OUT_VALUE_Msk = 0xff + // Position of OUT_MSK field. + DEDIC_GPIO_OUT_MSK_OUT_MSK_Pos = 0x8 + // Bit mask of OUT_MSK field. + DEDIC_GPIO_OUT_MSK_OUT_MSK_Msk = 0xff00 + + // OUT_IDV: Dedicated GPIO individual output register + // Position of CH0 field. + DEDIC_GPIO_OUT_IDV_CH0_Pos = 0x0 + // Bit mask of CH0 field. + DEDIC_GPIO_OUT_IDV_CH0_Msk = 0x3 + // Position of CH1 field. + DEDIC_GPIO_OUT_IDV_CH1_Pos = 0x2 + // Bit mask of CH1 field. + DEDIC_GPIO_OUT_IDV_CH1_Msk = 0xc + // Position of CH2 field. + DEDIC_GPIO_OUT_IDV_CH2_Pos = 0x4 + // Bit mask of CH2 field. + DEDIC_GPIO_OUT_IDV_CH2_Msk = 0x30 + // Position of CH3 field. + DEDIC_GPIO_OUT_IDV_CH3_Pos = 0x6 + // Bit mask of CH3 field. + DEDIC_GPIO_OUT_IDV_CH3_Msk = 0xc0 + // Position of CH4 field. + DEDIC_GPIO_OUT_IDV_CH4_Pos = 0x8 + // Bit mask of CH4 field. + DEDIC_GPIO_OUT_IDV_CH4_Msk = 0x300 + // Position of CH5 field. + DEDIC_GPIO_OUT_IDV_CH5_Pos = 0xa + // Bit mask of CH5 field. + DEDIC_GPIO_OUT_IDV_CH5_Msk = 0xc00 + // Position of CH6 field. + DEDIC_GPIO_OUT_IDV_CH6_Pos = 0xc + // Bit mask of CH6 field. + DEDIC_GPIO_OUT_IDV_CH6_Msk = 0x3000 + // Position of CH7 field. + DEDIC_GPIO_OUT_IDV_CH7_Pos = 0xe + // Bit mask of CH7 field. + DEDIC_GPIO_OUT_IDV_CH7_Msk = 0xc000 + + // OUT_SCAN: Dedicated GPIO output status register + // Position of OUT_STATUS field. + DEDIC_GPIO_OUT_SCAN_OUT_STATUS_Pos = 0x0 + // Bit mask of OUT_STATUS field. + DEDIC_GPIO_OUT_SCAN_OUT_STATUS_Msk = 0xff + + // OUT_CPU: Dedicated GPIO output mode selection register + // Position of SEL0 field. + DEDIC_GPIO_OUT_CPU_SEL0_Pos = 0x0 + // Bit mask of SEL0 field. + DEDIC_GPIO_OUT_CPU_SEL0_Msk = 0x1 + // Bit SEL0. + DEDIC_GPIO_OUT_CPU_SEL0 = 0x1 + // Position of SEL1 field. + DEDIC_GPIO_OUT_CPU_SEL1_Pos = 0x1 + // Bit mask of SEL1 field. + DEDIC_GPIO_OUT_CPU_SEL1_Msk = 0x2 + // Bit SEL1. + DEDIC_GPIO_OUT_CPU_SEL1 = 0x2 + // Position of SEL2 field. + DEDIC_GPIO_OUT_CPU_SEL2_Pos = 0x2 + // Bit mask of SEL2 field. + DEDIC_GPIO_OUT_CPU_SEL2_Msk = 0x4 + // Bit SEL2. + DEDIC_GPIO_OUT_CPU_SEL2 = 0x4 + // Position of SEL3 field. + DEDIC_GPIO_OUT_CPU_SEL3_Pos = 0x3 + // Bit mask of SEL3 field. + DEDIC_GPIO_OUT_CPU_SEL3_Msk = 0x8 + // Bit SEL3. + DEDIC_GPIO_OUT_CPU_SEL3 = 0x8 + // Position of SEL4 field. + DEDIC_GPIO_OUT_CPU_SEL4_Pos = 0x4 + // Bit mask of SEL4 field. + DEDIC_GPIO_OUT_CPU_SEL4_Msk = 0x10 + // Bit SEL4. + DEDIC_GPIO_OUT_CPU_SEL4 = 0x10 + // Position of SEL5 field. + DEDIC_GPIO_OUT_CPU_SEL5_Pos = 0x5 + // Bit mask of SEL5 field. + DEDIC_GPIO_OUT_CPU_SEL5_Msk = 0x20 + // Bit SEL5. + DEDIC_GPIO_OUT_CPU_SEL5 = 0x20 + // Position of SEL6 field. + DEDIC_GPIO_OUT_CPU_SEL6_Pos = 0x6 + // Bit mask of SEL6 field. + DEDIC_GPIO_OUT_CPU_SEL6_Msk = 0x40 + // Bit SEL6. + DEDIC_GPIO_OUT_CPU_SEL6 = 0x40 + // Position of SEL7 field. + DEDIC_GPIO_OUT_CPU_SEL7_Pos = 0x7 + // Bit mask of SEL7 field. + DEDIC_GPIO_OUT_CPU_SEL7_Msk = 0x80 + // Bit SEL7. + DEDIC_GPIO_OUT_CPU_SEL7 = 0x80 + + // IN_DLY: Dedicated GPIO input delay configuration register + // Position of CH0 field. + DEDIC_GPIO_IN_DLY_CH0_Pos = 0x0 + // Bit mask of CH0 field. + DEDIC_GPIO_IN_DLY_CH0_Msk = 0x3 + // Position of CH1 field. + DEDIC_GPIO_IN_DLY_CH1_Pos = 0x2 + // Bit mask of CH1 field. + DEDIC_GPIO_IN_DLY_CH1_Msk = 0xc + // Position of CH2 field. + DEDIC_GPIO_IN_DLY_CH2_Pos = 0x4 + // Bit mask of CH2 field. + DEDIC_GPIO_IN_DLY_CH2_Msk = 0x30 + // Position of CH3 field. + DEDIC_GPIO_IN_DLY_CH3_Pos = 0x6 + // Bit mask of CH3 field. + DEDIC_GPIO_IN_DLY_CH3_Msk = 0xc0 + // Position of CH4 field. + DEDIC_GPIO_IN_DLY_CH4_Pos = 0x8 + // Bit mask of CH4 field. + DEDIC_GPIO_IN_DLY_CH4_Msk = 0x300 + // Position of CH5 field. + DEDIC_GPIO_IN_DLY_CH5_Pos = 0xa + // Bit mask of CH5 field. + DEDIC_GPIO_IN_DLY_CH5_Msk = 0xc00 + // Position of CH6 field. + DEDIC_GPIO_IN_DLY_CH6_Pos = 0xc + // Bit mask of CH6 field. + DEDIC_GPIO_IN_DLY_CH6_Msk = 0x3000 + // Position of CH7 field. + DEDIC_GPIO_IN_DLY_CH7_Pos = 0xe + // Bit mask of CH7 field. + DEDIC_GPIO_IN_DLY_CH7_Msk = 0xc000 + + // IN_SCAN: Dedicated GPIO input status register + // Position of IN_STATUS field. + DEDIC_GPIO_IN_SCAN_IN_STATUS_Pos = 0x0 + // Bit mask of IN_STATUS field. + DEDIC_GPIO_IN_SCAN_IN_STATUS_Msk = 0xff + + // INTR_RCGN: Dedicated GPIO interrupts generation mode register + // Position of INTR_MODE_CH0 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH0_Pos = 0x0 + // Bit mask of INTR_MODE_CH0 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH0_Msk = 0x7 + // Position of INTR_MODE_CH1 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH1_Pos = 0x3 + // Bit mask of INTR_MODE_CH1 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH1_Msk = 0x38 + // Position of INTR_MODE_CH2 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH2_Pos = 0x6 + // Bit mask of INTR_MODE_CH2 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH2_Msk = 0x1c0 + // Position of INTR_MODE_CH3 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH3_Pos = 0x9 + // Bit mask of INTR_MODE_CH3 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH3_Msk = 0xe00 + // Position of INTR_MODE_CH4 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH4_Pos = 0xc + // Bit mask of INTR_MODE_CH4 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH4_Msk = 0x7000 + // Position of INTR_MODE_CH5 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH5_Pos = 0xf + // Bit mask of INTR_MODE_CH5 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH5_Msk = 0x38000 + // Position of INTR_MODE_CH6 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH6_Pos = 0x12 + // Bit mask of INTR_MODE_CH6 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH6_Msk = 0x1c0000 + // Position of INTR_MODE_CH7 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH7_Pos = 0x15 + // Bit mask of INTR_MODE_CH7 field. + DEDIC_GPIO_INTR_RCGN_INTR_MODE_CH7_Msk = 0xe00000 + + // INTR_RAW: Raw interrupt status + // Position of GPIO0 field. + DEDIC_GPIO_INTR_RAW_GPIO0_Pos = 0x0 + // Bit mask of GPIO0 field. + DEDIC_GPIO_INTR_RAW_GPIO0_Msk = 0x1 + // Bit GPIO0. + DEDIC_GPIO_INTR_RAW_GPIO0 = 0x1 + // Position of GPIO1 field. + DEDIC_GPIO_INTR_RAW_GPIO1_Pos = 0x1 + // Bit mask of GPIO1 field. + DEDIC_GPIO_INTR_RAW_GPIO1_Msk = 0x2 + // Bit GPIO1. + DEDIC_GPIO_INTR_RAW_GPIO1 = 0x2 + // Position of GPIO2 field. + DEDIC_GPIO_INTR_RAW_GPIO2_Pos = 0x2 + // Bit mask of GPIO2 field. + DEDIC_GPIO_INTR_RAW_GPIO2_Msk = 0x4 + // Bit GPIO2. + DEDIC_GPIO_INTR_RAW_GPIO2 = 0x4 + // Position of GPIO3 field. + DEDIC_GPIO_INTR_RAW_GPIO3_Pos = 0x3 + // Bit mask of GPIO3 field. + DEDIC_GPIO_INTR_RAW_GPIO3_Msk = 0x8 + // Bit GPIO3. + DEDIC_GPIO_INTR_RAW_GPIO3 = 0x8 + // Position of GPIO4 field. + DEDIC_GPIO_INTR_RAW_GPIO4_Pos = 0x4 + // Bit mask of GPIO4 field. + DEDIC_GPIO_INTR_RAW_GPIO4_Msk = 0x10 + // Bit GPIO4. + DEDIC_GPIO_INTR_RAW_GPIO4 = 0x10 + // Position of GPIO5 field. + DEDIC_GPIO_INTR_RAW_GPIO5_Pos = 0x5 + // Bit mask of GPIO5 field. + DEDIC_GPIO_INTR_RAW_GPIO5_Msk = 0x20 + // Bit GPIO5. + DEDIC_GPIO_INTR_RAW_GPIO5 = 0x20 + // Position of GPIO6 field. + DEDIC_GPIO_INTR_RAW_GPIO6_Pos = 0x6 + // Bit mask of GPIO6 field. + DEDIC_GPIO_INTR_RAW_GPIO6_Msk = 0x40 + // Bit GPIO6. + DEDIC_GPIO_INTR_RAW_GPIO6 = 0x40 + // Position of GPIO7 field. + DEDIC_GPIO_INTR_RAW_GPIO7_Pos = 0x7 + // Bit mask of GPIO7 field. + DEDIC_GPIO_INTR_RAW_GPIO7_Msk = 0x80 + // Bit GPIO7. + DEDIC_GPIO_INTR_RAW_GPIO7 = 0x80 + + // INTR_RLS: Interrupt enable bits + // Position of GPIO0_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO0_INT_ENA_Pos = 0x0 + // Bit mask of GPIO0_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO0_INT_ENA_Msk = 0x1 + // Bit GPIO0_INT_ENA. + DEDIC_GPIO_INTR_RLS_GPIO0_INT_ENA = 0x1 + // Position of GPIO1_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO1_INT_ENA_Pos = 0x1 + // Bit mask of GPIO1_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO1_INT_ENA_Msk = 0x2 + // Bit GPIO1_INT_ENA. + DEDIC_GPIO_INTR_RLS_GPIO1_INT_ENA = 0x2 + // Position of GPIO2_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO2_INT_ENA_Pos = 0x2 + // Bit mask of GPIO2_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO2_INT_ENA_Msk = 0x4 + // Bit GPIO2_INT_ENA. + DEDIC_GPIO_INTR_RLS_GPIO2_INT_ENA = 0x4 + // Position of GPIO3_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO3_INT_ENA_Pos = 0x3 + // Bit mask of GPIO3_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO3_INT_ENA_Msk = 0x8 + // Bit GPIO3_INT_ENA. + DEDIC_GPIO_INTR_RLS_GPIO3_INT_ENA = 0x8 + // Position of GPIO4_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO4_INT_ENA_Pos = 0x4 + // Bit mask of GPIO4_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO4_INT_ENA_Msk = 0x10 + // Bit GPIO4_INT_ENA. + DEDIC_GPIO_INTR_RLS_GPIO4_INT_ENA = 0x10 + // Position of GPIO5_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO5_INT_ENA_Pos = 0x5 + // Bit mask of GPIO5_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO5_INT_ENA_Msk = 0x20 + // Bit GPIO5_INT_ENA. + DEDIC_GPIO_INTR_RLS_GPIO5_INT_ENA = 0x20 + // Position of GPIO6_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO6_INT_ENA_Pos = 0x6 + // Bit mask of GPIO6_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO6_INT_ENA_Msk = 0x40 + // Bit GPIO6_INT_ENA. + DEDIC_GPIO_INTR_RLS_GPIO6_INT_ENA = 0x40 + // Position of GPIO7_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO7_INT_ENA_Pos = 0x7 + // Bit mask of GPIO7_INT_ENA field. + DEDIC_GPIO_INTR_RLS_GPIO7_INT_ENA_Msk = 0x80 + // Bit GPIO7_INT_ENA. + DEDIC_GPIO_INTR_RLS_GPIO7_INT_ENA = 0x80 + + // INTR_ST: Masked interrupt status + // Position of GPIO0_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO0_INT_ST_Pos = 0x0 + // Bit mask of GPIO0_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO0_INT_ST_Msk = 0x1 + // Bit GPIO0_INT_ST. + DEDIC_GPIO_INTR_ST_GPIO0_INT_ST = 0x1 + // Position of GPIO1_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO1_INT_ST_Pos = 0x1 + // Bit mask of GPIO1_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO1_INT_ST_Msk = 0x2 + // Bit GPIO1_INT_ST. + DEDIC_GPIO_INTR_ST_GPIO1_INT_ST = 0x2 + // Position of GPIO2_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO2_INT_ST_Pos = 0x2 + // Bit mask of GPIO2_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO2_INT_ST_Msk = 0x4 + // Bit GPIO2_INT_ST. + DEDIC_GPIO_INTR_ST_GPIO2_INT_ST = 0x4 + // Position of GPIO3_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO3_INT_ST_Pos = 0x3 + // Bit mask of GPIO3_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO3_INT_ST_Msk = 0x8 + // Bit GPIO3_INT_ST. + DEDIC_GPIO_INTR_ST_GPIO3_INT_ST = 0x8 + // Position of GPIO4_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO4_INT_ST_Pos = 0x4 + // Bit mask of GPIO4_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO4_INT_ST_Msk = 0x10 + // Bit GPIO4_INT_ST. + DEDIC_GPIO_INTR_ST_GPIO4_INT_ST = 0x10 + // Position of GPIO5_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO5_INT_ST_Pos = 0x5 + // Bit mask of GPIO5_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO5_INT_ST_Msk = 0x20 + // Bit GPIO5_INT_ST. + DEDIC_GPIO_INTR_ST_GPIO5_INT_ST = 0x20 + // Position of GPIO6_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO6_INT_ST_Pos = 0x6 + // Bit mask of GPIO6_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO6_INT_ST_Msk = 0x40 + // Bit GPIO6_INT_ST. + DEDIC_GPIO_INTR_ST_GPIO6_INT_ST = 0x40 + // Position of GPIO7_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO7_INT_ST_Pos = 0x7 + // Bit mask of GPIO7_INT_ST field. + DEDIC_GPIO_INTR_ST_GPIO7_INT_ST_Msk = 0x80 + // Bit GPIO7_INT_ST. + DEDIC_GPIO_INTR_ST_GPIO7_INT_ST = 0x80 + + // INTR_CLR: Interrupt clear bits + // Position of GPIO0_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO0_INT_CLR_Pos = 0x0 + // Bit mask of GPIO0_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO0_INT_CLR_Msk = 0x1 + // Bit GPIO0_INT_CLR. + DEDIC_GPIO_INTR_CLR_GPIO0_INT_CLR = 0x1 + // Position of GPIO1_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO1_INT_CLR_Pos = 0x1 + // Bit mask of GPIO1_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO1_INT_CLR_Msk = 0x2 + // Bit GPIO1_INT_CLR. + DEDIC_GPIO_INTR_CLR_GPIO1_INT_CLR = 0x2 + // Position of GPIO2_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO2_INT_CLR_Pos = 0x2 + // Bit mask of GPIO2_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO2_INT_CLR_Msk = 0x4 + // Bit GPIO2_INT_CLR. + DEDIC_GPIO_INTR_CLR_GPIO2_INT_CLR = 0x4 + // Position of GPIO3_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO3_INT_CLR_Pos = 0x3 + // Bit mask of GPIO3_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO3_INT_CLR_Msk = 0x8 + // Bit GPIO3_INT_CLR. + DEDIC_GPIO_INTR_CLR_GPIO3_INT_CLR = 0x8 + // Position of GPIO4_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO4_INT_CLR_Pos = 0x4 + // Bit mask of GPIO4_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO4_INT_CLR_Msk = 0x10 + // Bit GPIO4_INT_CLR. + DEDIC_GPIO_INTR_CLR_GPIO4_INT_CLR = 0x10 + // Position of GPIO5_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO5_INT_CLR_Pos = 0x5 + // Bit mask of GPIO5_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO5_INT_CLR_Msk = 0x20 + // Bit GPIO5_INT_CLR. + DEDIC_GPIO_INTR_CLR_GPIO5_INT_CLR = 0x20 + // Position of GPIO6_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO6_INT_CLR_Pos = 0x6 + // Bit mask of GPIO6_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO6_INT_CLR_Msk = 0x40 + // Bit GPIO6_INT_CLR. + DEDIC_GPIO_INTR_CLR_GPIO6_INT_CLR = 0x40 + // Position of GPIO7_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO7_INT_CLR_Pos = 0x7 + // Bit mask of GPIO7_INT_CLR field. + DEDIC_GPIO_INTR_CLR_GPIO7_INT_CLR_Msk = 0x80 + // Bit GPIO7_INT_CLR. + DEDIC_GPIO_INTR_CLR_GPIO7_INT_CLR = 0x80 +) + +// Constants for DS: Digital Signature +const ( + // IV_0: IV block data. + // Position of IV field. + DS_IV_IV_Pos = 0x0 + // Bit mask of IV field. + DS_IV_IV_Msk = 0xffffffff + + // SET_START: Activates the DS peripheral + // Position of SET_START field. + DS_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + DS_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + DS_SET_START_SET_START = 0x1 + + // SET_ME: Starts DS operation + // Position of SET_ME field. + DS_SET_ME_SET_ME_Pos = 0x0 + // Bit mask of SET_ME field. + DS_SET_ME_SET_ME_Msk = 0x1 + // Bit SET_ME. + DS_SET_ME_SET_ME = 0x1 + + // SET_FINISH: Ends DS operation + // Position of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Pos = 0x0 + // Bit mask of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Msk = 0x1 + // Bit SET_FINISH. + DS_SET_FINISH_SET_FINISH = 0x1 + + // QUERY_BUSY: Status of the DS + // Position of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Pos = 0x0 + // Bit mask of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Msk = 0x1 + // Bit QUERY_BUSY. + DS_QUERY_BUSY_QUERY_BUSY = 0x1 + + // QUERY_KEY_WRONG: Checks the reason why DS_KEY is not ready. + // Position of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Pos = 0x0 + // Bit mask of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Msk = 0xf + + // QUERY_CHECK: Queries DS check result + // Position of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Pos = 0x0 + // Bit mask of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Msk = 0x1 + // Bit MD_ERROR. + DS_QUERY_CHECK_MD_ERROR = 0x1 + // Position of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Pos = 0x1 + // Bit mask of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Msk = 0x2 + // Bit PADDING_BAD. + DS_QUERY_CHECK_PADDING_BAD = 0x2 + + // DATE: Version control register + // Position of DATE field. + DS_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DS_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for EFUSE: eFuse Controller +const ( + // PGM_DATA0: Register %s that stores data to be programmed. + // Position of PGM_DATA field. + EFUSE_PGM_DATA_PGM_DATA_Pos = 0x0 + // Bit mask of PGM_DATA field. + EFUSE_PGM_DATA_PGM_DATA_Msk = 0xffffffff + + // PGM_CHECK_VALUE0: Register %s that stores the RS code to be programmed. + // Position of PGM_RS_DATA field. + EFUSE_PGM_CHECK_VALUE_PGM_RS_DATA_Pos = 0x0 + // Bit mask of PGM_RS_DATA field. + EFUSE_PGM_CHECK_VALUE_PGM_RS_DATA_Msk = 0xffffffff + + // RD_WR_DIS: Register 0 of BLOCK0. + // Position of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Pos = 0x0 + // Bit mask of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Msk = 0xffffffff + + // RD_REPEAT_DATA0: Register 1 of BLOCK0. + // Position of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Pos = 0x0 + // Bit mask of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Msk = 0x7f + // Position of DIS_RTC_RAM_BOOT field. + EFUSE_RD_REPEAT_DATA0_DIS_RTC_RAM_BOOT_Pos = 0x7 + // Bit mask of DIS_RTC_RAM_BOOT field. + EFUSE_RD_REPEAT_DATA0_DIS_RTC_RAM_BOOT_Msk = 0x80 + // Bit DIS_RTC_RAM_BOOT. + EFUSE_RD_REPEAT_DATA0_DIS_RTC_RAM_BOOT = 0x80 + // Position of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Pos = 0x8 + // Bit mask of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Msk = 0x100 + // Bit DIS_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE = 0x100 + // Position of DIS_DCACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DCACHE_Pos = 0x9 + // Bit mask of DIS_DCACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DCACHE_Msk = 0x200 + // Bit DIS_DCACHE. + EFUSE_RD_REPEAT_DATA0_DIS_DCACHE = 0x200 + // Position of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Pos = 0xa + // Bit mask of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Msk = 0x400 + // Bit DIS_DOWNLOAD_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE = 0x400 + // Position of DIS_DOWNLOAD_DCACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE_Pos = 0xb + // Bit mask of DIS_DOWNLOAD_DCACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE_Msk = 0x800 + // Bit DIS_DOWNLOAD_DCACHE. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE = 0x800 + // Position of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD = 0x1000 + // Position of DIS_USB field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_Pos = 0xd + // Bit mask of DIS_USB field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_Msk = 0x2000 + // Bit DIS_USB. + EFUSE_RD_REPEAT_DATA0_DIS_USB = 0x2000 + // Position of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Pos = 0xe + // Bit mask of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Msk = 0x4000 + // Bit DIS_CAN. + EFUSE_RD_REPEAT_DATA0_DIS_CAN = 0x4000 + // Position of DIS_BOOT_REMAP field. + EFUSE_RD_REPEAT_DATA0_DIS_BOOT_REMAP_Pos = 0xf + // Bit mask of DIS_BOOT_REMAP field. + EFUSE_RD_REPEAT_DATA0_DIS_BOOT_REMAP_Msk = 0x8000 + // Bit DIS_BOOT_REMAP. + EFUSE_RD_REPEAT_DATA0_DIS_BOOT_REMAP = 0x8000 + // Position of RPT4_RESERVED5 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED5_Pos = 0x10 + // Bit mask of RPT4_RESERVED5 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED5_Msk = 0x10000 + // Bit RPT4_RESERVED5. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED5 = 0x10000 + // Position of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Pos = 0x11 + // Bit mask of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Msk = 0x20000 + // Bit SOFT_DIS_JTAG. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG = 0x20000 + // Position of HARD_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_HARD_DIS_JTAG_Pos = 0x12 + // Bit mask of HARD_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_HARD_DIS_JTAG_Msk = 0x40000 + // Bit HARD_DIS_JTAG. + EFUSE_RD_REPEAT_DATA0_HARD_DIS_JTAG = 0x40000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x13 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x80000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT = 0x80000 + // Position of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Pos = 0x14 + // Bit mask of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Msk = 0x300000 + // Position of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Pos = 0x16 + // Bit mask of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Msk = 0xc00000 + // Position of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Pos = 0x18 + // Bit mask of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Msk = 0x1000000 + // Bit USB_EXCHG_PINS. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS = 0x1000000 + // Position of EXT_PHY_ENABLE field. + EFUSE_RD_REPEAT_DATA0_EXT_PHY_ENABLE_Pos = 0x19 + // Bit mask of EXT_PHY_ENABLE field. + EFUSE_RD_REPEAT_DATA0_EXT_PHY_ENABLE_Msk = 0x2000000 + // Bit EXT_PHY_ENABLE. + EFUSE_RD_REPEAT_DATA0_EXT_PHY_ENABLE = 0x2000000 + // Position of USB_FORCE_NOPERSIST field. + EFUSE_RD_REPEAT_DATA0_USB_FORCE_NOPERSIST_Pos = 0x1a + // Bit mask of USB_FORCE_NOPERSIST field. + EFUSE_RD_REPEAT_DATA0_USB_FORCE_NOPERSIST_Msk = 0x4000000 + // Bit USB_FORCE_NOPERSIST. + EFUSE_RD_REPEAT_DATA0_USB_FORCE_NOPERSIST = 0x4000000 + // Position of RPT4_RESERVED0 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_Pos = 0x1b + // Bit mask of RPT4_RESERVED0 field. + EFUSE_RD_REPEAT_DATA0_RPT4_RESERVED0_Msk = 0x18000000 + // Position of VDD_SPI_MODECURLIM field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_MODECURLIM_Pos = 0x1d + // Bit mask of VDD_SPI_MODECURLIM field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_MODECURLIM_Msk = 0x20000000 + // Bit VDD_SPI_MODECURLIM. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_MODECURLIM = 0x20000000 + // Position of VDD_SPI_DREFH field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_DREFH_Pos = 0x1e + // Bit mask of VDD_SPI_DREFH field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_DREFH_Msk = 0xc0000000 + + // RD_REPEAT_DATA1: Register 2 of BLOCK0. + // Position of VDD_SPI_DREFM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DREFM_Pos = 0x0 + // Bit mask of VDD_SPI_DREFM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DREFM_Msk = 0x3 + // Position of VDD_SPI_DREFL field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DREFL_Pos = 0x2 + // Bit mask of VDD_SPI_DREFL field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DREFL_Msk = 0xc + // Position of VDD_SPI_XPD field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_XPD_Pos = 0x4 + // Bit mask of VDD_SPI_XPD field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_XPD_Msk = 0x10 + // Bit VDD_SPI_XPD. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_XPD = 0x10 + // Position of VDD_SPI_TIEH field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_TIEH_Pos = 0x5 + // Bit mask of VDD_SPI_TIEH field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_TIEH_Msk = 0x20 + // Bit VDD_SPI_TIEH. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_TIEH = 0x20 + // Position of VDD_SPI_FORCE field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_FORCE_Pos = 0x6 + // Bit mask of VDD_SPI_FORCE field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_FORCE_Msk = 0x40 + // Bit VDD_SPI_FORCE. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_FORCE = 0x40 + // Position of VDD_SPI_EN_INIT field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_EN_INIT_Pos = 0x7 + // Bit mask of VDD_SPI_EN_INIT field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_EN_INIT_Msk = 0x80 + // Bit VDD_SPI_EN_INIT. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_EN_INIT = 0x80 + // Position of VDD_SPI_ENCURLIM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_ENCURLIM_Pos = 0x8 + // Bit mask of VDD_SPI_ENCURLIM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_ENCURLIM_Msk = 0x100 + // Bit VDD_SPI_ENCURLIM. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_ENCURLIM = 0x100 + // Position of VDD_SPI_DCURLIM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DCURLIM_Pos = 0x9 + // Bit mask of VDD_SPI_DCURLIM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DCURLIM_Msk = 0xe00 + // Position of VDD_SPI_INIT field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_INIT_Pos = 0xc + // Bit mask of VDD_SPI_INIT field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_INIT_Msk = 0x3000 + // Position of VDD_SPI_DCAP field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DCAP_Pos = 0xe + // Bit mask of VDD_SPI_DCAP field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DCAP_Msk = 0xc000 + // Position of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0 = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1 = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2 = 0x800000 + // Position of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Msk = 0xf000000 + // Position of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Msk = 0xf0000000 + + // RD_REPEAT_DATA2: Register 3 of BLOCK0. + // Position of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Msk = 0xf + // Position of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Msk = 0xf0 + // Position of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Msk = 0xf00 + // Position of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Pos = 0xc + // Bit mask of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Msk = 0xf000 + // Position of KEY_PURPOSE_6 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_6_Pos = 0x10 + // Bit mask of KEY_PURPOSE_6 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_6_Msk = 0xf0000 + // Position of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Msk = 0x100000 + // Bit SECURE_BOOT_EN. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE = 0x200000 + // Position of RPT4_RESERVED1 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED1_Pos = 0x16 + // Bit mask of RPT4_RESERVED1 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED1_Msk = 0xfc00000 + // Position of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Pos = 0x1c + // Bit mask of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Msk = 0xf0000000 + + // RD_REPEAT_DATA3: Register 4 of BLOCK0. + // Position of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE = 0x1 + // Position of DIS_LEGACY_SPI_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT_Pos = 0x1 + // Bit mask of DIS_LEGACY_SPI_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT_Msk = 0x2 + // Bit DIS_LEGACY_SPI_BOOT. + EFUSE_RD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT = 0x2 + // Position of UART_PRINT_CHANNEL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CHANNEL_Pos = 0x2 + // Bit mask of UART_PRINT_CHANNEL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CHANNEL_Msk = 0x4 + // Bit UART_PRINT_CHANNEL. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CHANNEL = 0x4 + // Position of RPT4_RESERVED3 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_Pos = 0x3 + // Bit mask of RPT4_RESERVED3 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3_Msk = 0x8 + // Bit RPT4_RESERVED3. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED3 = 0x8 + // Position of DIS_USB_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE_Pos = 0x4 + // Bit mask of DIS_USB_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE_Msk = 0x10 + // Bit DIS_USB_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD = 0x20 + // Position of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Msk = 0xc0 + // Position of PIN_POWER_SELECTION field. + EFUSE_RD_REPEAT_DATA3_PIN_POWER_SELECTION_Pos = 0x8 + // Bit mask of PIN_POWER_SELECTION field. + EFUSE_RD_REPEAT_DATA3_PIN_POWER_SELECTION_Msk = 0x100 + // Bit PIN_POWER_SELECTION. + EFUSE_RD_REPEAT_DATA3_PIN_POWER_SELECTION = 0x100 + // Position of FLASH_TYPE field. + EFUSE_RD_REPEAT_DATA3_FLASH_TYPE_Pos = 0x9 + // Bit mask of FLASH_TYPE field. + EFUSE_RD_REPEAT_DATA3_FLASH_TYPE_Msk = 0x200 + // Bit FLASH_TYPE. + EFUSE_RD_REPEAT_DATA3_FLASH_TYPE = 0x200 + // Position of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Pos = 0xa + // Bit mask of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Msk = 0x400 + // Bit FORCE_SEND_RESUME. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME = 0x400 + // Position of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Pos = 0xb + // Bit mask of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Msk = 0x7fff800 + // Position of RPT4_RESERVED2 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED2_Pos = 0x1b + // Bit mask of RPT4_RESERVED2 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED2_Msk = 0xf8000000 + + // RD_REPEAT_DATA4: Register 5 of BLOCK0. + // Position of RPT4_RESERVED4 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_Pos = 0x0 + // Bit mask of RPT4_RESERVED4 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED4_Msk = 0xffffff + + // RD_MAC_SPI_SYS_0: Register 0 of BLOCK1. + // Position of MAC_0 field. + EFUSE_RD_MAC_SPI_SYS_0_MAC_0_Pos = 0x0 + // Bit mask of MAC_0 field. + EFUSE_RD_MAC_SPI_SYS_0_MAC_0_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_1: Register 1 of BLOCK1. + // Position of MAC_1 field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_1_Pos = 0x0 + // Bit mask of MAC_1 field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_1_Msk = 0xffff + // Position of SPI_PAD_CONF_0 field. + EFUSE_RD_MAC_SPI_SYS_1_SPI_PAD_CONF_0_Pos = 0x10 + // Bit mask of SPI_PAD_CONF_0 field. + EFUSE_RD_MAC_SPI_SYS_1_SPI_PAD_CONF_0_Msk = 0xffff0000 + + // RD_MAC_SPI_SYS_2: Register 2 of BLOCK1. + // Position of SPI_PAD_CONF_1 field. + EFUSE_RD_MAC_SPI_SYS_2_SPI_PAD_CONF_1_Pos = 0x0 + // Bit mask of SPI_PAD_CONF_1 field. + EFUSE_RD_MAC_SPI_SYS_2_SPI_PAD_CONF_1_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_3: Register 3 of BLOCK1. + // Position of SPI_PAD_CONF_2 field. + EFUSE_RD_MAC_SPI_SYS_3_SPI_PAD_CONF_2_Pos = 0x0 + // Bit mask of SPI_PAD_CONF_2 field. + EFUSE_RD_MAC_SPI_SYS_3_SPI_PAD_CONF_2_Msk = 0x3ffff + // Position of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SPI_SYS_3_SYS_DATA_PART0_0_Pos = 0x12 + // Bit mask of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SPI_SYS_3_SYS_DATA_PART0_0_Msk = 0xfffc0000 + + // RD_MAC_SPI_SYS_4: Register 4 of BLOCK1. + // Position of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SPI_SYS_4_SYS_DATA_PART0_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SPI_SYS_4_SYS_DATA_PART0_1_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_5: Register 5 of BLOCK1. + // Position of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SPI_SYS_5_SYS_DATA_PART0_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SPI_SYS_5_SYS_DATA_PART0_2_Msk = 0xffffffff + + // RD_SYS_DATA_PART1_0: Register %s of BLOCK2 (system). + // Position of SYS_DATA_PART1 field. + EFUSE_RD_SYS_DATA_PART1_SYS_DATA_PART1_Pos = 0x0 + // Bit mask of SYS_DATA_PART1 field. + EFUSE_RD_SYS_DATA_PART1_SYS_DATA_PART1_Msk = 0xffffffff + + // RD_USR_DATA0: Register %s of BLOCK3 (user). + // Position of USR_DATA field. + EFUSE_RD_USR_DATA_USR_DATA_Pos = 0x0 + // Bit mask of USR_DATA field. + EFUSE_RD_USR_DATA_USR_DATA_Msk = 0xffffffff + + // RD_KEY0_DATA0: Register %s of BLOCK4 (KEY0). + // Position of KEY0_DATA field. + EFUSE_RD_KEY0_DATA_KEY0_DATA_Pos = 0x0 + // Bit mask of KEY0_DATA field. + EFUSE_RD_KEY0_DATA_KEY0_DATA_Msk = 0xffffffff + + // RD_KEY1_DATA0: Register %s of BLOCK5 (KEY1). + // Position of KEY1_DATA field. + EFUSE_RD_KEY1_DATA_KEY1_DATA_Pos = 0x0 + // Bit mask of KEY1_DATA field. + EFUSE_RD_KEY1_DATA_KEY1_DATA_Msk = 0xffffffff + + // RD_KEY2_DATA0: Register %s of BLOCK6 (KEY2). + // Position of KEY2_DATA field. + EFUSE_RD_KEY2_DATA_KEY2_DATA_Pos = 0x0 + // Bit mask of KEY2_DATA field. + EFUSE_RD_KEY2_DATA_KEY2_DATA_Msk = 0xffffffff + + // RD_KEY3_DATA0: Register %s of BLOCK7 (KEY3). + // Position of KEY3_DATA field. + EFUSE_RD_KEY3_DATA_KEY3_DATA_Pos = 0x0 + // Bit mask of KEY3_DATA field. + EFUSE_RD_KEY3_DATA_KEY3_DATA_Msk = 0xffffffff + + // RD_KEY4_DATA0: Register %s of BLOCK8 (KEY4). + // Position of KEY4_DATA field. + EFUSE_RD_KEY4_DATA_KEY4_DATA_Pos = 0x0 + // Bit mask of KEY4_DATA field. + EFUSE_RD_KEY4_DATA_KEY4_DATA_Msk = 0xffffffff + + // RD_KEY5_DATA0: Register %s of BLOCK9 (KEY5). + // Position of KEY5_DATA field. + EFUSE_RD_KEY5_DATA_KEY5_DATA_Pos = 0x0 + // Bit mask of KEY5_DATA field. + EFUSE_RD_KEY5_DATA_KEY5_DATA_Msk = 0xffffffff + + // RD_SYS_DATA_PART2_0: Register %s of BLOCK10 (system). + // Position of SYS_DATA_PART2 field. + EFUSE_RD_SYS_DATA_PART2_SYS_DATA_PART2_Pos = 0x0 + // Bit mask of SYS_DATA_PART2 field. + EFUSE_RD_SYS_DATA_PART2_SYS_DATA_PART2_Msk = 0xffffffff + + // RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. + // Position of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Pos = 0x0 + // Bit mask of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Msk = 0x7f + // Position of DIS_RTC_RAM_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR_Pos = 0x7 + // Bit mask of DIS_RTC_RAM_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR_Msk = 0x80 + // Bit DIS_RTC_RAM_BOOT_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR = 0x80 + // Position of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Pos = 0x8 + // Bit mask of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Msk = 0x100 + // Bit DIS_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR = 0x100 + // Position of DIS_DCACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DCACHE_ERR_Pos = 0x9 + // Bit mask of DIS_DCACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DCACHE_ERR_Msk = 0x200 + // Bit DIS_DCACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DCACHE_ERR = 0x200 + // Position of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR_Pos = 0xa + // Bit mask of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR_Msk = 0x400 + // Bit DIS_DOWNLOAD_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR = 0x400 + // Position of DIS_DOWNLOAD_DCACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR_Pos = 0xb + // Bit mask of DIS_DOWNLOAD_DCACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR_Msk = 0x800 + // Bit DIS_DOWNLOAD_DCACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR = 0x800 + // Position of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR = 0x1000 + // Position of DIS_USB_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_ERR_Pos = 0xd + // Bit mask of DIS_USB_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_ERR_Msk = 0x2000 + // Bit DIS_USB_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_USB_ERR = 0x2000 + // Position of DIS_CAN_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_CAN_ERR_Pos = 0xe + // Bit mask of DIS_CAN_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_CAN_ERR_Msk = 0x4000 + // Bit DIS_CAN_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_CAN_ERR = 0x4000 + // Position of DIS_BOOT_REMAP_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_BOOT_REMAP_ERR_Pos = 0xf + // Bit mask of DIS_BOOT_REMAP_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_BOOT_REMAP_ERR_Msk = 0x8000 + // Bit DIS_BOOT_REMAP_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_BOOT_REMAP_ERR = 0x8000 + // Position of RPT4_RESERVED5_ERR field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED5_ERR_Pos = 0x10 + // Bit mask of RPT4_RESERVED5_ERR field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED5_ERR_Msk = 0x10000 + // Bit RPT4_RESERVED5_ERR. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED5_ERR = 0x10000 + // Position of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Pos = 0x11 + // Bit mask of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Msk = 0x20000 + // Bit SOFT_DIS_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR = 0x20000 + // Position of HARD_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_HARD_DIS_JTAG_ERR_Pos = 0x12 + // Bit mask of HARD_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_HARD_DIS_JTAG_ERR_Msk = 0x40000 + // Bit HARD_DIS_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_HARD_DIS_JTAG_ERR = 0x40000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Pos = 0x13 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Msk = 0x80000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR = 0x80000 + // Position of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Pos = 0x14 + // Bit mask of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Msk = 0x300000 + // Position of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Pos = 0x16 + // Bit mask of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Msk = 0xc00000 + // Position of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Pos = 0x18 + // Bit mask of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Msk = 0x1000000 + // Bit USB_EXCHG_PINS_ERR. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR = 0x1000000 + // Position of EXT_PHY_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR_Pos = 0x19 + // Bit mask of EXT_PHY_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR_Msk = 0x2000000 + // Bit EXT_PHY_ENABLE_ERR. + EFUSE_RD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR = 0x2000000 + // Position of USB_FORCE_NOPERSIST_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_FORCE_NOPERSIST_ERR_Pos = 0x1a + // Bit mask of USB_FORCE_NOPERSIST_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_FORCE_NOPERSIST_ERR_Msk = 0x4000000 + // Bit USB_FORCE_NOPERSIST_ERR. + EFUSE_RD_REPEAT_ERR0_USB_FORCE_NOPERSIST_ERR = 0x4000000 + // Position of RPT4_RESERVED0_ERR field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_Pos = 0x1b + // Bit mask of RPT4_RESERVED0_ERR field. + EFUSE_RD_REPEAT_ERR0_RPT4_RESERVED0_ERR_Msk = 0x18000000 + // Position of VDD_SPI_MODECURLIM_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR_Pos = 0x1d + // Bit mask of VDD_SPI_MODECURLIM_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR_Msk = 0x20000000 + // Bit VDD_SPI_MODECURLIM_ERR. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR = 0x20000000 + // Position of VDD_SPI_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_DREFH_ERR_Pos = 0x1e + // Bit mask of VDD_SPI_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_DREFH_ERR_Msk = 0xc0000000 + + // RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. + // Position of VDD_SPI_DREFM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DREFM_ERR_Pos = 0x0 + // Bit mask of VDD_SPI_DREFM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DREFM_ERR_Msk = 0x3 + // Position of VDD_SPI_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DREFL_ERR_Pos = 0x2 + // Bit mask of VDD_SPI_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DREFL_ERR_Msk = 0xc + // Position of VDD_SPI_XPD_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_XPD_ERR_Pos = 0x4 + // Bit mask of VDD_SPI_XPD_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_XPD_ERR_Msk = 0x10 + // Bit VDD_SPI_XPD_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_XPD_ERR = 0x10 + // Position of VDD_SPI_TIEH_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_TIEH_ERR_Pos = 0x5 + // Bit mask of VDD_SPI_TIEH_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_TIEH_ERR_Msk = 0x20 + // Bit VDD_SPI_TIEH_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_TIEH_ERR = 0x20 + // Position of VDD_SPI_FORCE_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_FORCE_ERR_Pos = 0x6 + // Bit mask of VDD_SPI_FORCE_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_FORCE_ERR_Msk = 0x40 + // Bit VDD_SPI_FORCE_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_FORCE_ERR = 0x40 + // Position of VDD_SPI_EN_INIT_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR_Pos = 0x7 + // Bit mask of VDD_SPI_EN_INIT_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR_Msk = 0x80 + // Bit VDD_SPI_EN_INIT_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR = 0x80 + // Position of VDD_SPI_ENCURLIM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR_Pos = 0x8 + // Bit mask of VDD_SPI_ENCURLIM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR_Msk = 0x100 + // Bit VDD_SPI_ENCURLIM_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR = 0x100 + // Position of VDD_SPI_DCURLIM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DCURLIM_ERR_Pos = 0x9 + // Bit mask of VDD_SPI_DCURLIM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DCURLIM_ERR_Msk = 0xe00 + // Position of VDD_SPI_INIT_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_INIT_ERR_Pos = 0xc + // Bit mask of VDD_SPI_INIT_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_INIT_ERR_Msk = 0x3000 + // Position of VDD_SPI_DCAP_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DCAP_ERR_Pos = 0xe + // Bit mask of VDD_SPI_DCAP_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DCAP_ERR_Msk = 0xc000 + // Position of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR = 0x800000 + // Position of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Msk = 0xf000000 + // Position of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. + // Position of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Msk = 0xf + // Position of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Msk = 0xf0 + // Position of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Msk = 0xf00 + // Position of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Pos = 0xc + // Bit mask of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Msk = 0xf000 + // Position of KEY_PURPOSE_6_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_6_ERR_Pos = 0x10 + // Bit mask of KEY_PURPOSE_6_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_6_ERR_Msk = 0xf0000 + // Position of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Msk = 0x100000 + // Bit SECURE_BOOT_EN_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR = 0x200000 + // Position of RPT4_RESERVED1_ERR field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED1_ERR_Pos = 0x16 + // Bit mask of RPT4_RESERVED1_ERR field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED1_ERR_Msk = 0xfc00000 + // Position of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Pos = 0x1c + // Bit mask of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. + // Position of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR = 0x1 + // Position of DIS_LEGACY_SPI_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR_Pos = 0x1 + // Bit mask of DIS_LEGACY_SPI_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR_Msk = 0x2 + // Bit DIS_LEGACY_SPI_BOOT_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR = 0x2 + // Position of UART_PRINT_CHANNEL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR_Pos = 0x2 + // Bit mask of UART_PRINT_CHANNEL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR_Msk = 0x4 + // Bit UART_PRINT_CHANNEL_ERR. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR = 0x4 + // Position of RPT4_RESERVED3_ERR field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_Pos = 0x3 + // Bit mask of RPT4_RESERVED3_ERR field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR_Msk = 0x8 + // Bit RPT4_RESERVED3_ERR. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED3_ERR = 0x8 + // Position of DIS_USB_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR_Pos = 0x4 + // Bit mask of DIS_USB_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR_Msk = 0x10 + // Bit DIS_USB_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR = 0x20 + // Position of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Msk = 0xc0 + // Position of PIN_POWER_SELECTION_ERR field. + EFUSE_RD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR_Pos = 0x8 + // Bit mask of PIN_POWER_SELECTION_ERR field. + EFUSE_RD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR_Msk = 0x100 + // Bit PIN_POWER_SELECTION_ERR. + EFUSE_RD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR = 0x100 + // Position of FLASH_TYPE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_TYPE_ERR_Pos = 0x9 + // Bit mask of FLASH_TYPE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_TYPE_ERR_Msk = 0x200 + // Bit FLASH_TYPE_ERR. + EFUSE_RD_REPEAT_ERR3_FLASH_TYPE_ERR = 0x200 + // Position of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Pos = 0xa + // Bit mask of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Msk = 0x400 + // Bit FORCE_SEND_RESUME_ERR. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR = 0x400 + // Position of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Pos = 0xb + // Bit mask of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Msk = 0x7fff800 + // Position of RPT4_RESERVED2_ERR field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED2_ERR_Pos = 0x1b + // Bit mask of RPT4_RESERVED2_ERR field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED2_ERR_Msk = 0xf8000000 + + // RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. + // Position of RPT4_RESERVED4_ERR field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_Pos = 0x0 + // Bit mask of RPT4_RESERVED4_ERR field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED4_ERR_Msk = 0xffffff + + // RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. + // Position of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Pos = 0x0 + // Bit mask of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Msk = 0x7 + // Position of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Pos = 0x3 + // Bit mask of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Msk = 0x8 + // Bit MAC_SPI_8M_FAIL. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL = 0x8 + // Position of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Pos = 0x4 + // Bit mask of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Msk = 0x70 + // Position of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Pos = 0x7 + // Bit mask of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Msk = 0x80 + // Bit SYS_PART1_FAIL. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL = 0x80 + // Position of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Pos = 0x8 + // Bit mask of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Msk = 0x700 + // Position of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Pos = 0xb + // Bit mask of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Msk = 0x800 + // Bit USR_DATA_FAIL. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL = 0x800 + // Position of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Pos = 0xc + // Bit mask of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Msk = 0x7000 + // Position of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Pos = 0xf + // Bit mask of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Msk = 0x8000 + // Bit KEY0_FAIL. + EFUSE_RD_RS_ERR0_KEY0_FAIL = 0x8000 + // Position of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Pos = 0x10 + // Bit mask of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Msk = 0x70000 + // Position of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Pos = 0x13 + // Bit mask of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Msk = 0x80000 + // Bit KEY1_FAIL. + EFUSE_RD_RS_ERR0_KEY1_FAIL = 0x80000 + // Position of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Pos = 0x14 + // Bit mask of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Msk = 0x700000 + // Position of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Pos = 0x17 + // Bit mask of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Msk = 0x800000 + // Bit KEY2_FAIL. + EFUSE_RD_RS_ERR0_KEY2_FAIL = 0x800000 + // Position of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Pos = 0x18 + // Bit mask of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Msk = 0x7000000 + // Position of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Pos = 0x1b + // Bit mask of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Msk = 0x8000000 + // Bit KEY3_FAIL. + EFUSE_RD_RS_ERR0_KEY3_FAIL = 0x8000000 + // Position of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Pos = 0x1c + // Bit mask of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Msk = 0x70000000 + // Position of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Pos = 0x1f + // Bit mask of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Msk = 0x80000000 + // Bit KEY4_FAIL. + EFUSE_RD_RS_ERR0_KEY4_FAIL = 0x80000000 + + // RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. + // Position of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Pos = 0x0 + // Bit mask of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Msk = 0x7 + // Position of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Pos = 0x3 + // Bit mask of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Msk = 0x8 + // Bit KEY5_FAIL. + EFUSE_RD_RS_ERR1_KEY5_FAIL = 0x8 + // Position of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Pos = 0x4 + // Bit mask of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Msk = 0x70 + // Position of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Pos = 0x7 + // Bit mask of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Msk = 0x80 + // Bit SYS_PART2_FAIL. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL = 0x80 + + // CLK: eFuse clock configuration register. + // Position of EFUSE_MEM_FORCE_PD field. + EFUSE_CLK_EFUSE_MEM_FORCE_PD_Pos = 0x0 + // Bit mask of EFUSE_MEM_FORCE_PD field. + EFUSE_CLK_EFUSE_MEM_FORCE_PD_Msk = 0x1 + // Bit EFUSE_MEM_FORCE_PD. + EFUSE_CLK_EFUSE_MEM_FORCE_PD = 0x1 + // Position of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + EFUSE_CLK_MEM_CLK_FORCE_ON = 0x2 + // Position of EFUSE_MEM_FORCE_PU field. + EFUSE_CLK_EFUSE_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of EFUSE_MEM_FORCE_PU field. + EFUSE_CLK_EFUSE_MEM_FORCE_PU_Msk = 0x4 + // Bit EFUSE_MEM_FORCE_PU. + EFUSE_CLK_EFUSE_MEM_FORCE_PU = 0x4 + // Position of EN field. + EFUSE_CLK_EN_Pos = 0x10 + // Bit mask of EN field. + EFUSE_CLK_EN_Msk = 0x10000 + // Bit EN. + EFUSE_CLK_EN = 0x10000 + + // CONF: eFuse operation mode configuration register. + // Position of OP_CODE field. + EFUSE_CONF_OP_CODE_Pos = 0x0 + // Bit mask of OP_CODE field. + EFUSE_CONF_OP_CODE_Msk = 0xffff + + // STATUS: eFuse status register. + // Position of STATE field. + EFUSE_STATUS_STATE_Pos = 0x0 + // Bit mask of STATE field. + EFUSE_STATUS_STATE_Msk = 0xf + // Position of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Pos = 0x4 + // Bit mask of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Msk = 0x10 + // Bit OTP_LOAD_SW. + EFUSE_STATUS_OTP_LOAD_SW = 0x10 + // Position of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Pos = 0x5 + // Bit mask of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Msk = 0x20 + // Bit OTP_VDDQ_C_SYNC2. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2 = 0x20 + // Position of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Pos = 0x6 + // Bit mask of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Msk = 0x40 + // Bit OTP_STROBE_SW. + EFUSE_STATUS_OTP_STROBE_SW = 0x40 + // Position of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Pos = 0x7 + // Bit mask of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Msk = 0x80 + // Bit OTP_CSB_SW. + EFUSE_STATUS_OTP_CSB_SW = 0x80 + // Position of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Pos = 0x8 + // Bit mask of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Msk = 0x100 + // Bit OTP_PGENB_SW. + EFUSE_STATUS_OTP_PGENB_SW = 0x100 + // Position of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Pos = 0x9 + // Bit mask of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Msk = 0x200 + // Bit OTP_VDDQ_IS_SW. + EFUSE_STATUS_OTP_VDDQ_IS_SW = 0x200 + // Position of REPEAT_ERR_CNT field. + EFUSE_STATUS_REPEAT_ERR_CNT_Pos = 0xa + // Bit mask of REPEAT_ERR_CNT field. + EFUSE_STATUS_REPEAT_ERR_CNT_Msk = 0x3fc00 + + // CMD: eFuse command register. + // Position of READ_CMD field. + EFUSE_CMD_READ_CMD_Pos = 0x0 + // Bit mask of READ_CMD field. + EFUSE_CMD_READ_CMD_Msk = 0x1 + // Bit READ_CMD. + EFUSE_CMD_READ_CMD = 0x1 + // Position of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Pos = 0x1 + // Bit mask of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Msk = 0x2 + // Bit PGM_CMD. + EFUSE_CMD_PGM_CMD = 0x2 + // Position of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Pos = 0x2 + // Bit mask of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Msk = 0x3c + + // INT_RAW: eFuse raw interrupt register. + // Position of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Pos = 0x0 + // Bit mask of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Msk = 0x1 + // Bit READ_DONE_INT_RAW. + EFUSE_INT_RAW_READ_DONE_INT_RAW = 0x1 + // Position of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Pos = 0x1 + // Bit mask of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Msk = 0x2 + // Bit PGM_DONE_INT_RAW. + EFUSE_INT_RAW_PGM_DONE_INT_RAW = 0x2 + + // INT_ST: eFuse interrupt status register. + // Position of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Pos = 0x0 + // Bit mask of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Msk = 0x1 + // Bit READ_DONE_INT_ST. + EFUSE_INT_ST_READ_DONE_INT_ST = 0x1 + // Position of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Msk = 0x2 + // Bit PGM_DONE_INT_ST. + EFUSE_INT_ST_PGM_DONE_INT_ST = 0x2 + + // INT_ENA: eFuse interrupt enable register. + // Position of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Pos = 0x0 + // Bit mask of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Msk = 0x1 + // Bit READ_DONE_INT_ENA. + EFUSE_INT_ENA_READ_DONE_INT_ENA = 0x1 + // Position of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Msk = 0x2 + // Bit PGM_DONE_INT_ENA. + EFUSE_INT_ENA_PGM_DONE_INT_ENA = 0x2 + + // INT_CLR: eFuse interrupt clear register. + // Position of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Pos = 0x0 + // Bit mask of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Msk = 0x1 + // Bit READ_DONE_INT_CLR. + EFUSE_INT_CLR_READ_DONE_INT_CLR = 0x1 + // Position of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Pos = 0x1 + // Bit mask of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Msk = 0x2 + // Bit PGM_DONE_INT_CLR. + EFUSE_INT_CLR_PGM_DONE_INT_CLR = 0x2 + + // DAC_CONF: Controls the eFuse programming voltage. + // Position of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Pos = 0x0 + // Bit mask of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Msk = 0xff + // Position of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Pos = 0x8 + // Bit mask of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Msk = 0x100 + // Bit DAC_CLK_PAD_SEL. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL = 0x100 + // Position of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Pos = 0x9 + // Bit mask of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Msk = 0x1fe00 + // Position of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Pos = 0x11 + // Bit mask of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Msk = 0x20000 + // Bit OE_CLR. + EFUSE_DAC_CONF_OE_CLR = 0x20000 + + // RD_TIM_CONF: Configures read timing parameters. + // Position of THR_A field. + EFUSE_RD_TIM_CONF_THR_A_Pos = 0x0 + // Bit mask of THR_A field. + EFUSE_RD_TIM_CONF_THR_A_Msk = 0xff + // Position of TRD field. + EFUSE_RD_TIM_CONF_TRD_Pos = 0x8 + // Bit mask of TRD field. + EFUSE_RD_TIM_CONF_TRD_Msk = 0xff00 + // Position of TSUR_A field. + EFUSE_RD_TIM_CONF_TSUR_A_Pos = 0x10 + // Bit mask of TSUR_A field. + EFUSE_RD_TIM_CONF_TSUR_A_Msk = 0xff0000 + // Position of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Pos = 0x18 + // Bit mask of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Msk = 0xff000000 + + // WR_TIM_CONF0: Configuration register 0 of eFuse programming timing parameters. + // Position of THP_A field. + EFUSE_WR_TIM_CONF0_THP_A_Pos = 0x0 + // Bit mask of THP_A field. + EFUSE_WR_TIM_CONF0_THP_A_Msk = 0xff + // Position of TPGM_INACTIVE field. + EFUSE_WR_TIM_CONF0_TPGM_INACTIVE_Pos = 0x8 + // Bit mask of TPGM_INACTIVE field. + EFUSE_WR_TIM_CONF0_TPGM_INACTIVE_Msk = 0xff00 + // Position of TPGM field. + EFUSE_WR_TIM_CONF0_TPGM_Pos = 0x10 + // Bit mask of TPGM field. + EFUSE_WR_TIM_CONF0_TPGM_Msk = 0xffff0000 + + // WR_TIM_CONF1: Configuration register 1 of eFuse programming timing parameters. + // Position of TSUP_A field. + EFUSE_WR_TIM_CONF1_TSUP_A_Pos = 0x0 + // Bit mask of TSUP_A field. + EFUSE_WR_TIM_CONF1_TSUP_A_Msk = 0xff + // Position of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Pos = 0x8 + // Bit mask of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Msk = 0xffff00 + + // WR_TIM_CONF2: Configuration register 2 of eFuse programming timing parameters. + // Position of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Pos = 0x0 + // Bit mask of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Msk = 0xffff + + // DATE: Version control register. + // Position of DATE field. + EFUSE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EFUSE_DATE_DATE_Msk = 0xffffffff +) + +// Constants for EXTMEM: External Memory +const ( + // PRO_DCACHE_CTRL: register description + // Position of PRO_DCACHE_ENABLE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_ENABLE_Pos = 0x0 + // Bit mask of PRO_DCACHE_ENABLE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_ENABLE_Msk = 0x1 + // Bit PRO_DCACHE_ENABLE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_ENABLE = 0x1 + // Position of PRO_DCACHE_SETSIZE_MODE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_SETSIZE_MODE_Pos = 0x2 + // Bit mask of PRO_DCACHE_SETSIZE_MODE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_SETSIZE_MODE_Msk = 0x4 + // Bit PRO_DCACHE_SETSIZE_MODE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_SETSIZE_MODE = 0x4 + // Position of PRO_DCACHE_BLOCKSIZE_MODE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_BLOCKSIZE_MODE_Pos = 0x3 + // Bit mask of PRO_DCACHE_BLOCKSIZE_MODE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_BLOCKSIZE_MODE_Msk = 0x8 + // Bit PRO_DCACHE_BLOCKSIZE_MODE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_BLOCKSIZE_MODE = 0x8 + // Position of PRO_DCACHE_INVALIDATE_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_ENA_Pos = 0x8 + // Bit mask of PRO_DCACHE_INVALIDATE_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_ENA_Msk = 0x100 + // Bit PRO_DCACHE_INVALIDATE_ENA. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_ENA = 0x100 + // Position of PRO_DCACHE_INVALIDATE_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_DONE_Pos = 0x9 + // Bit mask of PRO_DCACHE_INVALIDATE_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_DONE_Msk = 0x200 + // Bit PRO_DCACHE_INVALIDATE_DONE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_INVALIDATE_DONE = 0x200 + // Position of PRO_DCACHE_FLUSH_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_ENA_Pos = 0xa + // Bit mask of PRO_DCACHE_FLUSH_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_ENA_Msk = 0x400 + // Bit PRO_DCACHE_FLUSH_ENA. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_ENA = 0x400 + // Position of PRO_DCACHE_FLUSH_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_DONE_Pos = 0xb + // Bit mask of PRO_DCACHE_FLUSH_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_DONE_Msk = 0x800 + // Bit PRO_DCACHE_FLUSH_DONE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_FLUSH_DONE = 0x800 + // Position of PRO_DCACHE_CLEAN_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_ENA_Pos = 0xc + // Bit mask of PRO_DCACHE_CLEAN_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_ENA_Msk = 0x1000 + // Bit PRO_DCACHE_CLEAN_ENA. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_ENA = 0x1000 + // Position of PRO_DCACHE_CLEAN_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_DONE_Pos = 0xd + // Bit mask of PRO_DCACHE_CLEAN_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_DONE_Msk = 0x2000 + // Bit PRO_DCACHE_CLEAN_DONE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_CLEAN_DONE = 0x2000 + // Position of PRO_DCACHE_LOCK0_EN field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK0_EN_Pos = 0xe + // Bit mask of PRO_DCACHE_LOCK0_EN field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK0_EN_Msk = 0x4000 + // Bit PRO_DCACHE_LOCK0_EN. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK0_EN = 0x4000 + // Position of PRO_DCACHE_LOCK1_EN field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK1_EN_Pos = 0xf + // Bit mask of PRO_DCACHE_LOCK1_EN field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK1_EN_Msk = 0x8000 + // Bit PRO_DCACHE_LOCK1_EN. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK1_EN = 0x8000 + // Position of PRO_DCACHE_AUTOLOAD_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_ENA_Pos = 0x12 + // Bit mask of PRO_DCACHE_AUTOLOAD_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_ENA_Msk = 0x40000 + // Bit PRO_DCACHE_AUTOLOAD_ENA. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_ENA = 0x40000 + // Position of PRO_DCACHE_AUTOLOAD_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_DONE_Pos = 0x13 + // Bit mask of PRO_DCACHE_AUTOLOAD_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_DONE_Msk = 0x80000 + // Bit PRO_DCACHE_AUTOLOAD_DONE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_AUTOLOAD_DONE = 0x80000 + // Position of PRO_DCACHE_PRELOAD_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_ENA_Pos = 0x14 + // Bit mask of PRO_DCACHE_PRELOAD_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_ENA_Msk = 0x100000 + // Bit PRO_DCACHE_PRELOAD_ENA. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_ENA = 0x100000 + // Position of PRO_DCACHE_PRELOAD_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_DONE_Pos = 0x15 + // Bit mask of PRO_DCACHE_PRELOAD_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_DONE_Msk = 0x200000 + // Bit PRO_DCACHE_PRELOAD_DONE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_PRELOAD_DONE = 0x200000 + // Position of PRO_DCACHE_UNLOCK_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_ENA_Pos = 0x16 + // Bit mask of PRO_DCACHE_UNLOCK_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_ENA_Msk = 0x400000 + // Bit PRO_DCACHE_UNLOCK_ENA. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_ENA = 0x400000 + // Position of PRO_DCACHE_UNLOCK_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_DONE_Pos = 0x17 + // Bit mask of PRO_DCACHE_UNLOCK_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_DONE_Msk = 0x800000 + // Bit PRO_DCACHE_UNLOCK_DONE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_UNLOCK_DONE = 0x800000 + // Position of PRO_DCACHE_LOCK_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK_ENA_Pos = 0x18 + // Bit mask of PRO_DCACHE_LOCK_ENA field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK_ENA_Msk = 0x1000000 + // Bit PRO_DCACHE_LOCK_ENA. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK_ENA = 0x1000000 + // Position of PRO_DCACHE_LOCK_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK_DONE_Pos = 0x19 + // Bit mask of PRO_DCACHE_LOCK_DONE field. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK_DONE_Msk = 0x2000000 + // Bit PRO_DCACHE_LOCK_DONE. + EXTMEM_PRO_DCACHE_CTRL_PRO_DCACHE_LOCK_DONE = 0x2000000 + + // PRO_DCACHE_CTRL1: register description + // Position of PRO_DCACHE_MASK_BUS0 field. + EXTMEM_PRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS0_Pos = 0x0 + // Bit mask of PRO_DCACHE_MASK_BUS0 field. + EXTMEM_PRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS0_Msk = 0x1 + // Bit PRO_DCACHE_MASK_BUS0. + EXTMEM_PRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS0 = 0x1 + // Position of PRO_DCACHE_MASK_BUS1 field. + EXTMEM_PRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS1_Pos = 0x1 + // Bit mask of PRO_DCACHE_MASK_BUS1 field. + EXTMEM_PRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS1_Msk = 0x2 + // Bit PRO_DCACHE_MASK_BUS1. + EXTMEM_PRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS1 = 0x2 + // Position of PRO_DCACHE_MASK_BUS2 field. + EXTMEM_PRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS2_Pos = 0x2 + // Bit mask of PRO_DCACHE_MASK_BUS2 field. + EXTMEM_PRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS2_Msk = 0x4 + // Bit PRO_DCACHE_MASK_BUS2. + EXTMEM_PRO_DCACHE_CTRL1_PRO_DCACHE_MASK_BUS2 = 0x4 + + // PRO_DCACHE_TAG_POWER_CTRL: register description + // Position of PRO_DCACHE_TAG_MEM_FORCE_ON field. + EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of PRO_DCACHE_TAG_MEM_FORCE_ON field. + EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_ON_Msk = 0x1 + // Bit PRO_DCACHE_TAG_MEM_FORCE_ON. + EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_ON = 0x1 + // Position of PRO_DCACHE_TAG_MEM_FORCE_PD field. + EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of PRO_DCACHE_TAG_MEM_FORCE_PD field. + EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PD_Msk = 0x2 + // Bit PRO_DCACHE_TAG_MEM_FORCE_PD. + EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PD = 0x2 + // Position of PRO_DCACHE_TAG_MEM_FORCE_PU field. + EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of PRO_DCACHE_TAG_MEM_FORCE_PU field. + EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PU_Msk = 0x4 + // Bit PRO_DCACHE_TAG_MEM_FORCE_PU. + EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_PRO_DCACHE_TAG_MEM_FORCE_PU = 0x4 + + // PRO_DCACHE_LOCK0_ADDR: register description + // Position of PRO_DCACHE_LOCK0_ADDR field. + EXTMEM_PRO_DCACHE_LOCK0_ADDR_PRO_DCACHE_LOCK0_ADDR_Pos = 0x0 + // Bit mask of PRO_DCACHE_LOCK0_ADDR field. + EXTMEM_PRO_DCACHE_LOCK0_ADDR_PRO_DCACHE_LOCK0_ADDR_Msk = 0xffffffff + + // PRO_DCACHE_LOCK0_SIZE: register description + // Position of PRO_DCACHE_LOCK0_SIZE field. + EXTMEM_PRO_DCACHE_LOCK0_SIZE_PRO_DCACHE_LOCK0_SIZE_Pos = 0x0 + // Bit mask of PRO_DCACHE_LOCK0_SIZE field. + EXTMEM_PRO_DCACHE_LOCK0_SIZE_PRO_DCACHE_LOCK0_SIZE_Msk = 0xffff + + // PRO_DCACHE_LOCK1_ADDR: register description + // Position of PRO_DCACHE_LOCK1_ADDR field. + EXTMEM_PRO_DCACHE_LOCK1_ADDR_PRO_DCACHE_LOCK1_ADDR_Pos = 0x0 + // Bit mask of PRO_DCACHE_LOCK1_ADDR field. + EXTMEM_PRO_DCACHE_LOCK1_ADDR_PRO_DCACHE_LOCK1_ADDR_Msk = 0xffffffff + + // PRO_DCACHE_LOCK1_SIZE: register description + // Position of PRO_DCACHE_LOCK1_SIZE field. + EXTMEM_PRO_DCACHE_LOCK1_SIZE_PRO_DCACHE_LOCK1_SIZE_Pos = 0x0 + // Bit mask of PRO_DCACHE_LOCK1_SIZE field. + EXTMEM_PRO_DCACHE_LOCK1_SIZE_PRO_DCACHE_LOCK1_SIZE_Msk = 0xffff + + // PRO_DCACHE_MEM_SYNC0: register description + // Position of PRO_DCACHE_MEMSYNC_ADDR field. + EXTMEM_PRO_DCACHE_MEM_SYNC0_PRO_DCACHE_MEMSYNC_ADDR_Pos = 0x0 + // Bit mask of PRO_DCACHE_MEMSYNC_ADDR field. + EXTMEM_PRO_DCACHE_MEM_SYNC0_PRO_DCACHE_MEMSYNC_ADDR_Msk = 0xffffffff + + // PRO_DCACHE_MEM_SYNC1: register description + // Position of PRO_DCACHE_MEMSYNC_SIZE field. + EXTMEM_PRO_DCACHE_MEM_SYNC1_PRO_DCACHE_MEMSYNC_SIZE_Pos = 0x0 + // Bit mask of PRO_DCACHE_MEMSYNC_SIZE field. + EXTMEM_PRO_DCACHE_MEM_SYNC1_PRO_DCACHE_MEMSYNC_SIZE_Msk = 0x7ffff + + // PRO_DCACHE_PRELOAD_ADDR: register description + // Position of PRO_DCACHE_PRELOAD_ADDR field. + EXTMEM_PRO_DCACHE_PRELOAD_ADDR_PRO_DCACHE_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of PRO_DCACHE_PRELOAD_ADDR field. + EXTMEM_PRO_DCACHE_PRELOAD_ADDR_PRO_DCACHE_PRELOAD_ADDR_Msk = 0xffffffff + + // PRO_DCACHE_PRELOAD_SIZE: register description + // Position of PRO_DCACHE_PRELOAD_SIZE field. + EXTMEM_PRO_DCACHE_PRELOAD_SIZE_PRO_DCACHE_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of PRO_DCACHE_PRELOAD_SIZE field. + EXTMEM_PRO_DCACHE_PRELOAD_SIZE_PRO_DCACHE_PRELOAD_SIZE_Msk = 0x3ff + // Position of PRO_DCACHE_PRELOAD_ORDER field. + EXTMEM_PRO_DCACHE_PRELOAD_SIZE_PRO_DCACHE_PRELOAD_ORDER_Pos = 0xa + // Bit mask of PRO_DCACHE_PRELOAD_ORDER field. + EXTMEM_PRO_DCACHE_PRELOAD_SIZE_PRO_DCACHE_PRELOAD_ORDER_Msk = 0x400 + // Bit PRO_DCACHE_PRELOAD_ORDER. + EXTMEM_PRO_DCACHE_PRELOAD_SIZE_PRO_DCACHE_PRELOAD_ORDER = 0x400 + + // PRO_DCACHE_AUTOLOAD_CFG: register description + // Position of PRO_DCACHE_AUTOLOAD_MODE field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_MODE_Pos = 0x0 + // Bit mask of PRO_DCACHE_AUTOLOAD_MODE field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_MODE_Msk = 0x1 + // Bit PRO_DCACHE_AUTOLOAD_MODE. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_MODE = 0x1 + // Position of PRO_DCACHE_AUTOLOAD_STEP field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_STEP_Pos = 0x1 + // Bit mask of PRO_DCACHE_AUTOLOAD_STEP field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_STEP_Msk = 0x6 + // Position of PRO_DCACHE_AUTOLOAD_ORDER field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_ORDER_Pos = 0x3 + // Bit mask of PRO_DCACHE_AUTOLOAD_ORDER field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_ORDER_Msk = 0x8 + // Bit PRO_DCACHE_AUTOLOAD_ORDER. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_ORDER = 0x8 + // Position of PRO_DCACHE_AUTOLOAD_RQST field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_RQST_Pos = 0x4 + // Bit mask of PRO_DCACHE_AUTOLOAD_RQST field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_RQST_Msk = 0x30 + // Position of PRO_DCACHE_AUTOLOAD_SIZE field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SIZE_Pos = 0x6 + // Bit mask of PRO_DCACHE_AUTOLOAD_SIZE field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SIZE_Msk = 0xc0 + // Position of PRO_DCACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT0_ENA_Pos = 0x8 + // Bit mask of PRO_DCACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT0_ENA_Msk = 0x100 + // Bit PRO_DCACHE_AUTOLOAD_SCT0_ENA. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT0_ENA = 0x100 + // Position of PRO_DCACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT1_ENA_Pos = 0x9 + // Bit mask of PRO_DCACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT1_ENA_Msk = 0x200 + // Bit PRO_DCACHE_AUTOLOAD_SCT1_ENA. + EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_PRO_DCACHE_AUTOLOAD_SCT1_ENA = 0x200 + + // PRO_DCACHE_AUTOLOAD_SECTION0_ADDR: register description + // Position of PRO_DCACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of PRO_DCACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // PRO_DCACHE_AUTOLOAD_SECTION0_SIZE: register description + // Position of PRO_DCACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of PRO_DCACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_Msk = 0xffffff + + // PRO_DCACHE_AUTOLOAD_SECTION1_ADDR: register description + // Position of PRO_DCACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of PRO_DCACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // PRO_DCACHE_AUTOLOAD_SECTION1_SIZE: register description + // Position of PRO_DCACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of PRO_DCACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_Msk = 0xffffff + + // PRO_ICACHE_CTRL: register description + // Position of PRO_ICACHE_ENABLE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_ENABLE_Pos = 0x0 + // Bit mask of PRO_ICACHE_ENABLE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_ENABLE_Msk = 0x1 + // Bit PRO_ICACHE_ENABLE. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_ENABLE = 0x1 + // Position of PRO_ICACHE_SETSIZE_MODE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_SETSIZE_MODE_Pos = 0x2 + // Bit mask of PRO_ICACHE_SETSIZE_MODE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_SETSIZE_MODE_Msk = 0x4 + // Bit PRO_ICACHE_SETSIZE_MODE. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_SETSIZE_MODE = 0x4 + // Position of PRO_ICACHE_BLOCKSIZE_MODE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_BLOCKSIZE_MODE_Pos = 0x3 + // Bit mask of PRO_ICACHE_BLOCKSIZE_MODE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_BLOCKSIZE_MODE_Msk = 0x8 + // Bit PRO_ICACHE_BLOCKSIZE_MODE. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_BLOCKSIZE_MODE = 0x8 + // Position of PRO_ICACHE_INVALIDATE_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_ENA_Pos = 0x8 + // Bit mask of PRO_ICACHE_INVALIDATE_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_ENA_Msk = 0x100 + // Bit PRO_ICACHE_INVALIDATE_ENA. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_ENA = 0x100 + // Position of PRO_ICACHE_INVALIDATE_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_DONE_Pos = 0x9 + // Bit mask of PRO_ICACHE_INVALIDATE_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_DONE_Msk = 0x200 + // Bit PRO_ICACHE_INVALIDATE_DONE. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_INVALIDATE_DONE = 0x200 + // Position of PRO_ICACHE_LOCK0_EN field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK0_EN_Pos = 0xe + // Bit mask of PRO_ICACHE_LOCK0_EN field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK0_EN_Msk = 0x4000 + // Bit PRO_ICACHE_LOCK0_EN. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK0_EN = 0x4000 + // Position of PRO_ICACHE_LOCK1_EN field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK1_EN_Pos = 0xf + // Bit mask of PRO_ICACHE_LOCK1_EN field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK1_EN_Msk = 0x8000 + // Bit PRO_ICACHE_LOCK1_EN. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK1_EN = 0x8000 + // Position of PRO_ICACHE_AUTOLOAD_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_ENA_Pos = 0x12 + // Bit mask of PRO_ICACHE_AUTOLOAD_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_ENA_Msk = 0x40000 + // Bit PRO_ICACHE_AUTOLOAD_ENA. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_ENA = 0x40000 + // Position of PRO_ICACHE_AUTOLOAD_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_DONE_Pos = 0x13 + // Bit mask of PRO_ICACHE_AUTOLOAD_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_DONE_Msk = 0x80000 + // Bit PRO_ICACHE_AUTOLOAD_DONE. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_AUTOLOAD_DONE = 0x80000 + // Position of PRO_ICACHE_PRELOAD_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_ENA_Pos = 0x14 + // Bit mask of PRO_ICACHE_PRELOAD_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_ENA_Msk = 0x100000 + // Bit PRO_ICACHE_PRELOAD_ENA. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_ENA = 0x100000 + // Position of PRO_ICACHE_PRELOAD_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_DONE_Pos = 0x15 + // Bit mask of PRO_ICACHE_PRELOAD_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_DONE_Msk = 0x200000 + // Bit PRO_ICACHE_PRELOAD_DONE. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_PRELOAD_DONE = 0x200000 + // Position of PRO_ICACHE_UNLOCK_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_ENA_Pos = 0x16 + // Bit mask of PRO_ICACHE_UNLOCK_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_ENA_Msk = 0x400000 + // Bit PRO_ICACHE_UNLOCK_ENA. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_ENA = 0x400000 + // Position of PRO_ICACHE_UNLOCK_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_DONE_Pos = 0x17 + // Bit mask of PRO_ICACHE_UNLOCK_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_DONE_Msk = 0x800000 + // Bit PRO_ICACHE_UNLOCK_DONE. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_UNLOCK_DONE = 0x800000 + // Position of PRO_ICACHE_LOCK_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK_ENA_Pos = 0x18 + // Bit mask of PRO_ICACHE_LOCK_ENA field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK_ENA_Msk = 0x1000000 + // Bit PRO_ICACHE_LOCK_ENA. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK_ENA = 0x1000000 + // Position of PRO_ICACHE_LOCK_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK_DONE_Pos = 0x19 + // Bit mask of PRO_ICACHE_LOCK_DONE field. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK_DONE_Msk = 0x2000000 + // Bit PRO_ICACHE_LOCK_DONE. + EXTMEM_PRO_ICACHE_CTRL_PRO_ICACHE_LOCK_DONE = 0x2000000 + + // PRO_ICACHE_CTRL1: register description + // Position of PRO_ICACHE_MASK_BUS0 field. + EXTMEM_PRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS0_Pos = 0x0 + // Bit mask of PRO_ICACHE_MASK_BUS0 field. + EXTMEM_PRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS0_Msk = 0x1 + // Bit PRO_ICACHE_MASK_BUS0. + EXTMEM_PRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS0 = 0x1 + // Position of PRO_ICACHE_MASK_BUS1 field. + EXTMEM_PRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS1_Pos = 0x1 + // Bit mask of PRO_ICACHE_MASK_BUS1 field. + EXTMEM_PRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS1_Msk = 0x2 + // Bit PRO_ICACHE_MASK_BUS1. + EXTMEM_PRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS1 = 0x2 + // Position of PRO_ICACHE_MASK_BUS2 field. + EXTMEM_PRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS2_Pos = 0x2 + // Bit mask of PRO_ICACHE_MASK_BUS2 field. + EXTMEM_PRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS2_Msk = 0x4 + // Bit PRO_ICACHE_MASK_BUS2. + EXTMEM_PRO_ICACHE_CTRL1_PRO_ICACHE_MASK_BUS2 = 0x4 + + // PRO_ICACHE_TAG_POWER_CTRL: register description + // Position of PRO_ICACHE_TAG_MEM_FORCE_ON field. + EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of PRO_ICACHE_TAG_MEM_FORCE_ON field. + EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_ON_Msk = 0x1 + // Bit PRO_ICACHE_TAG_MEM_FORCE_ON. + EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_ON = 0x1 + // Position of PRO_ICACHE_TAG_MEM_FORCE_PD field. + EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of PRO_ICACHE_TAG_MEM_FORCE_PD field. + EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PD_Msk = 0x2 + // Bit PRO_ICACHE_TAG_MEM_FORCE_PD. + EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PD = 0x2 + // Position of PRO_ICACHE_TAG_MEM_FORCE_PU field. + EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of PRO_ICACHE_TAG_MEM_FORCE_PU field. + EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PU_Msk = 0x4 + // Bit PRO_ICACHE_TAG_MEM_FORCE_PU. + EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_PRO_ICACHE_TAG_MEM_FORCE_PU = 0x4 + + // PRO_ICACHE_LOCK0_ADDR: register description + // Position of PRO_ICACHE_LOCK0_ADDR field. + EXTMEM_PRO_ICACHE_LOCK0_ADDR_PRO_ICACHE_LOCK0_ADDR_Pos = 0x0 + // Bit mask of PRO_ICACHE_LOCK0_ADDR field. + EXTMEM_PRO_ICACHE_LOCK0_ADDR_PRO_ICACHE_LOCK0_ADDR_Msk = 0xffffffff + + // PRO_ICACHE_LOCK0_SIZE: register description + // Position of PRO_ICACHE_LOCK0_SIZE field. + EXTMEM_PRO_ICACHE_LOCK0_SIZE_PRO_ICACHE_LOCK0_SIZE_Pos = 0x0 + // Bit mask of PRO_ICACHE_LOCK0_SIZE field. + EXTMEM_PRO_ICACHE_LOCK0_SIZE_PRO_ICACHE_LOCK0_SIZE_Msk = 0xffff + + // PRO_ICACHE_LOCK1_ADDR: register description + // Position of PRO_ICACHE_LOCK1_ADDR field. + EXTMEM_PRO_ICACHE_LOCK1_ADDR_PRO_ICACHE_LOCK1_ADDR_Pos = 0x0 + // Bit mask of PRO_ICACHE_LOCK1_ADDR field. + EXTMEM_PRO_ICACHE_LOCK1_ADDR_PRO_ICACHE_LOCK1_ADDR_Msk = 0xffffffff + + // PRO_ICACHE_LOCK1_SIZE: register description + // Position of PRO_ICACHE_LOCK1_SIZE field. + EXTMEM_PRO_ICACHE_LOCK1_SIZE_PRO_ICACHE_LOCK1_SIZE_Pos = 0x0 + // Bit mask of PRO_ICACHE_LOCK1_SIZE field. + EXTMEM_PRO_ICACHE_LOCK1_SIZE_PRO_ICACHE_LOCK1_SIZE_Msk = 0xffff + + // PRO_ICACHE_MEM_SYNC0: register description + // Position of PRO_ICACHE_MEMSYNC_ADDR field. + EXTMEM_PRO_ICACHE_MEM_SYNC0_PRO_ICACHE_MEMSYNC_ADDR_Pos = 0x0 + // Bit mask of PRO_ICACHE_MEMSYNC_ADDR field. + EXTMEM_PRO_ICACHE_MEM_SYNC0_PRO_ICACHE_MEMSYNC_ADDR_Msk = 0xffffffff + + // PRO_ICACHE_MEM_SYNC1: register description + // Position of PRO_ICACHE_MEMSYNC_SIZE field. + EXTMEM_PRO_ICACHE_MEM_SYNC1_PRO_ICACHE_MEMSYNC_SIZE_Pos = 0x0 + // Bit mask of PRO_ICACHE_MEMSYNC_SIZE field. + EXTMEM_PRO_ICACHE_MEM_SYNC1_PRO_ICACHE_MEMSYNC_SIZE_Msk = 0x7ffff + + // PRO_ICACHE_PRELOAD_ADDR: register description + // Position of PRO_ICACHE_PRELOAD_ADDR field. + EXTMEM_PRO_ICACHE_PRELOAD_ADDR_PRO_ICACHE_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of PRO_ICACHE_PRELOAD_ADDR field. + EXTMEM_PRO_ICACHE_PRELOAD_ADDR_PRO_ICACHE_PRELOAD_ADDR_Msk = 0xffffffff + + // PRO_ICACHE_PRELOAD_SIZE: register description + // Position of PRO_ICACHE_PRELOAD_SIZE field. + EXTMEM_PRO_ICACHE_PRELOAD_SIZE_PRO_ICACHE_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of PRO_ICACHE_PRELOAD_SIZE field. + EXTMEM_PRO_ICACHE_PRELOAD_SIZE_PRO_ICACHE_PRELOAD_SIZE_Msk = 0x3ff + // Position of PRO_ICACHE_PRELOAD_ORDER field. + EXTMEM_PRO_ICACHE_PRELOAD_SIZE_PRO_ICACHE_PRELOAD_ORDER_Pos = 0xa + // Bit mask of PRO_ICACHE_PRELOAD_ORDER field. + EXTMEM_PRO_ICACHE_PRELOAD_SIZE_PRO_ICACHE_PRELOAD_ORDER_Msk = 0x400 + // Bit PRO_ICACHE_PRELOAD_ORDER. + EXTMEM_PRO_ICACHE_PRELOAD_SIZE_PRO_ICACHE_PRELOAD_ORDER = 0x400 + + // PRO_ICACHE_AUTOLOAD_CFG: register description + // Position of PRO_ICACHE_AUTOLOAD_MODE field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_MODE_Pos = 0x0 + // Bit mask of PRO_ICACHE_AUTOLOAD_MODE field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_MODE_Msk = 0x1 + // Bit PRO_ICACHE_AUTOLOAD_MODE. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_MODE = 0x1 + // Position of PRO_ICACHE_AUTOLOAD_STEP field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_STEP_Pos = 0x1 + // Bit mask of PRO_ICACHE_AUTOLOAD_STEP field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_STEP_Msk = 0x6 + // Position of PRO_ICACHE_AUTOLOAD_ORDER field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_ORDER_Pos = 0x3 + // Bit mask of PRO_ICACHE_AUTOLOAD_ORDER field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_ORDER_Msk = 0x8 + // Bit PRO_ICACHE_AUTOLOAD_ORDER. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_ORDER = 0x8 + // Position of PRO_ICACHE_AUTOLOAD_RQST field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_RQST_Pos = 0x4 + // Bit mask of PRO_ICACHE_AUTOLOAD_RQST field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_RQST_Msk = 0x30 + // Position of PRO_ICACHE_AUTOLOAD_SIZE field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SIZE_Pos = 0x6 + // Bit mask of PRO_ICACHE_AUTOLOAD_SIZE field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SIZE_Msk = 0xc0 + // Position of PRO_ICACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT0_ENA_Pos = 0x8 + // Bit mask of PRO_ICACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT0_ENA_Msk = 0x100 + // Bit PRO_ICACHE_AUTOLOAD_SCT0_ENA. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT0_ENA = 0x100 + // Position of PRO_ICACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT1_ENA_Pos = 0x9 + // Bit mask of PRO_ICACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT1_ENA_Msk = 0x200 + // Bit PRO_ICACHE_AUTOLOAD_SCT1_ENA. + EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_PRO_ICACHE_AUTOLOAD_SCT1_ENA = 0x200 + + // PRO_ICACHE_AUTOLOAD_SECTION0_ADDR: register description + // Position of PRO_ICACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of PRO_ICACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // PRO_ICACHE_AUTOLOAD_SECTION0_SIZE: register description + // Position of PRO_ICACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of PRO_ICACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_Msk = 0xffffff + + // PRO_ICACHE_AUTOLOAD_SECTION1_ADDR: register description + // Position of PRO_ICACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of PRO_ICACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // PRO_ICACHE_AUTOLOAD_SECTION1_SIZE: register description + // Position of PRO_ICACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of PRO_ICACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_Msk = 0xffffff + + // IC_PRELOAD_CNT: register description + // Position of IC_PRELOAD_CNT field. + EXTMEM_IC_PRELOAD_CNT_IC_PRELOAD_CNT_Pos = 0x0 + // Bit mask of IC_PRELOAD_CNT field. + EXTMEM_IC_PRELOAD_CNT_IC_PRELOAD_CNT_Msk = 0xffff + + // IC_PRELOAD_MISS_CNT: register description + // Position of IC_PRELOAD_MISS_CNT field. + EXTMEM_IC_PRELOAD_MISS_CNT_IC_PRELOAD_MISS_CNT_Pos = 0x0 + // Bit mask of IC_PRELOAD_MISS_CNT field. + EXTMEM_IC_PRELOAD_MISS_CNT_IC_PRELOAD_MISS_CNT_Msk = 0xffff + + // IBUS2_ABANDON_CNT: register description + // Position of IBUS2_ABANDON_CNT field. + EXTMEM_IBUS2_ABANDON_CNT_IBUS2_ABANDON_CNT_Pos = 0x0 + // Bit mask of IBUS2_ABANDON_CNT field. + EXTMEM_IBUS2_ABANDON_CNT_IBUS2_ABANDON_CNT_Msk = 0xffff + + // IBUS1_ABANDON_CNT: register description + // Position of IBUS1_ABANDON_CNT field. + EXTMEM_IBUS1_ABANDON_CNT_IBUS1_ABANDON_CNT_Pos = 0x0 + // Bit mask of IBUS1_ABANDON_CNT field. + EXTMEM_IBUS1_ABANDON_CNT_IBUS1_ABANDON_CNT_Msk = 0xffff + + // IBUS0_ABANDON_CNT: register description + // Position of IBUS0_ABANDON_CNT field. + EXTMEM_IBUS0_ABANDON_CNT_IBUS0_ABANDON_CNT_Pos = 0x0 + // Bit mask of IBUS0_ABANDON_CNT field. + EXTMEM_IBUS0_ABANDON_CNT_IBUS0_ABANDON_CNT_Msk = 0xffff + + // IBUS2_ACS_MISS_CNT: register description + // Position of IBUS2_ACS_MISS_CNT field. + EXTMEM_IBUS2_ACS_MISS_CNT_IBUS2_ACS_MISS_CNT_Pos = 0x0 + // Bit mask of IBUS2_ACS_MISS_CNT field. + EXTMEM_IBUS2_ACS_MISS_CNT_IBUS2_ACS_MISS_CNT_Msk = 0xffffffff + + // IBUS1_ACS_MISS_CNT: register description + // Position of IBUS1_ACS_MISS_CNT field. + EXTMEM_IBUS1_ACS_MISS_CNT_IBUS1_ACS_MISS_CNT_Pos = 0x0 + // Bit mask of IBUS1_ACS_MISS_CNT field. + EXTMEM_IBUS1_ACS_MISS_CNT_IBUS1_ACS_MISS_CNT_Msk = 0xffffffff + + // IBUS0_ACS_MISS_CNT: register description + // Position of IBUS0_ACS_MISS_CNT field. + EXTMEM_IBUS0_ACS_MISS_CNT_IBUS0_ACS_MISS_CNT_Pos = 0x0 + // Bit mask of IBUS0_ACS_MISS_CNT field. + EXTMEM_IBUS0_ACS_MISS_CNT_IBUS0_ACS_MISS_CNT_Msk = 0xffffffff + + // IBUS2_ACS_CNT: register description + // Position of IBUS2_ACS_CNT field. + EXTMEM_IBUS2_ACS_CNT_IBUS2_ACS_CNT_Pos = 0x0 + // Bit mask of IBUS2_ACS_CNT field. + EXTMEM_IBUS2_ACS_CNT_IBUS2_ACS_CNT_Msk = 0xffffffff + + // IBUS1_ACS_CNT: register description + // Position of IBUS1_ACS_CNT field. + EXTMEM_IBUS1_ACS_CNT_IBUS1_ACS_CNT_Pos = 0x0 + // Bit mask of IBUS1_ACS_CNT field. + EXTMEM_IBUS1_ACS_CNT_IBUS1_ACS_CNT_Msk = 0xffffffff + + // IBUS0_ACS_CNT: register description + // Position of IBUS0_ACS_CNT field. + EXTMEM_IBUS0_ACS_CNT_IBUS0_ACS_CNT_Pos = 0x0 + // Bit mask of IBUS0_ACS_CNT field. + EXTMEM_IBUS0_ACS_CNT_IBUS0_ACS_CNT_Msk = 0xffffffff + + // DC_PRELOAD_CNT: register description + // Position of DC_PRELOAD_CNT field. + EXTMEM_DC_PRELOAD_CNT_DC_PRELOAD_CNT_Pos = 0x0 + // Bit mask of DC_PRELOAD_CNT field. + EXTMEM_DC_PRELOAD_CNT_DC_PRELOAD_CNT_Msk = 0xffff + + // DC_PRELOAD_EVICT_CNT: register description + // Position of DC_PRELOAD_EVICT_CNT field. + EXTMEM_DC_PRELOAD_EVICT_CNT_DC_PRELOAD_EVICT_CNT_Pos = 0x0 + // Bit mask of DC_PRELOAD_EVICT_CNT field. + EXTMEM_DC_PRELOAD_EVICT_CNT_DC_PRELOAD_EVICT_CNT_Msk = 0xffff + + // DC_PRELOAD_MISS_CNT: register description + // Position of DC_PRELOAD_MISS_CNT field. + EXTMEM_DC_PRELOAD_MISS_CNT_DC_PRELOAD_MISS_CNT_Pos = 0x0 + // Bit mask of DC_PRELOAD_MISS_CNT field. + EXTMEM_DC_PRELOAD_MISS_CNT_DC_PRELOAD_MISS_CNT_Msk = 0xffff + + // DBUS2_ABANDON_CNT: register description + // Position of DBUS2_ABANDON_CNT field. + EXTMEM_DBUS2_ABANDON_CNT_DBUS2_ABANDON_CNT_Pos = 0x0 + // Bit mask of DBUS2_ABANDON_CNT field. + EXTMEM_DBUS2_ABANDON_CNT_DBUS2_ABANDON_CNT_Msk = 0xffff + + // DBUS1_ABANDON_CNT: register description + // Position of DBUS1_ABANDON_CNT field. + EXTMEM_DBUS1_ABANDON_CNT_DBUS1_ABANDON_CNT_Pos = 0x0 + // Bit mask of DBUS1_ABANDON_CNT field. + EXTMEM_DBUS1_ABANDON_CNT_DBUS1_ABANDON_CNT_Msk = 0xffff + + // DBUS0_ABANDON_CNT: register description + // Position of DBUS0_ABANDON_CNT field. + EXTMEM_DBUS0_ABANDON_CNT_DBUS0_ABANDON_CNT_Pos = 0x0 + // Bit mask of DBUS0_ABANDON_CNT field. + EXTMEM_DBUS0_ABANDON_CNT_DBUS0_ABANDON_CNT_Msk = 0xffff + + // DBUS2_ACS_WB_CNT: register description + // Position of DBUS2_ACS_WB_CNT field. + EXTMEM_DBUS2_ACS_WB_CNT_DBUS2_ACS_WB_CNT_Pos = 0x0 + // Bit mask of DBUS2_ACS_WB_CNT field. + EXTMEM_DBUS2_ACS_WB_CNT_DBUS2_ACS_WB_CNT_Msk = 0xfffff + + // DBUS1_ACS_WB_CNT: register description + // Position of DBUS1_ACS_WB_CNT field. + EXTMEM_DBUS1_ACS_WB_CNT_DBUS1_ACS_WB_CNT_Pos = 0x0 + // Bit mask of DBUS1_ACS_WB_CNT field. + EXTMEM_DBUS1_ACS_WB_CNT_DBUS1_ACS_WB_CNT_Msk = 0xfffff + + // DBUS0_ACS_WB_CNT: register description + // Position of DBUS0_ACS_WB_CNT field. + EXTMEM_DBUS0_ACS_WB_CNT_DBUS0_ACS_WB_CNT_Pos = 0x0 + // Bit mask of DBUS0_ACS_WB_CNT field. + EXTMEM_DBUS0_ACS_WB_CNT_DBUS0_ACS_WB_CNT_Msk = 0xfffff + + // DBUS2_ACS_MISS_CNT: register description + // Position of DBUS2_ACS_MISS_CNT field. + EXTMEM_DBUS2_ACS_MISS_CNT_DBUS2_ACS_MISS_CNT_Pos = 0x0 + // Bit mask of DBUS2_ACS_MISS_CNT field. + EXTMEM_DBUS2_ACS_MISS_CNT_DBUS2_ACS_MISS_CNT_Msk = 0xffffffff + + // DBUS1_ACS_MISS_CNT: register description + // Position of DBUS1_ACS_MISS_CNT field. + EXTMEM_DBUS1_ACS_MISS_CNT_DBUS1_ACS_MISS_CNT_Pos = 0x0 + // Bit mask of DBUS1_ACS_MISS_CNT field. + EXTMEM_DBUS1_ACS_MISS_CNT_DBUS1_ACS_MISS_CNT_Msk = 0xffffffff + + // DBUS0_ACS_MISS_CNT: register description + // Position of DBUS0_ACS_MISS_CNT field. + EXTMEM_DBUS0_ACS_MISS_CNT_DBUS0_ACS_MISS_CNT_Pos = 0x0 + // Bit mask of DBUS0_ACS_MISS_CNT field. + EXTMEM_DBUS0_ACS_MISS_CNT_DBUS0_ACS_MISS_CNT_Msk = 0xffffffff + + // DBUS2_ACS_CNT: register description + // Position of DBUS2_ACS_CNT field. + EXTMEM_DBUS2_ACS_CNT_DBUS2_ACS_CNT_Pos = 0x0 + // Bit mask of DBUS2_ACS_CNT field. + EXTMEM_DBUS2_ACS_CNT_DBUS2_ACS_CNT_Msk = 0xffffffff + + // DBUS1_ACS_CNT: register description + // Position of DBUS1_ACS_CNT field. + EXTMEM_DBUS1_ACS_CNT_DBUS1_ACS_CNT_Pos = 0x0 + // Bit mask of DBUS1_ACS_CNT field. + EXTMEM_DBUS1_ACS_CNT_DBUS1_ACS_CNT_Msk = 0xffffffff + + // DBUS0_ACS_CNT: register description + // Position of DBUS0_ACS_CNT field. + EXTMEM_DBUS0_ACS_CNT_DBUS0_ACS_CNT_Pos = 0x0 + // Bit mask of DBUS0_ACS_CNT field. + EXTMEM_DBUS0_ACS_CNT_DBUS0_ACS_CNT_Msk = 0xffffffff + + // CACHE_DBG_INT_ENA: register description + // Position of CACHE_DBG_EN field. + EXTMEM_CACHE_DBG_INT_ENA_CACHE_DBG_EN_Pos = 0x0 + // Bit mask of CACHE_DBG_EN field. + EXTMEM_CACHE_DBG_INT_ENA_CACHE_DBG_EN_Msk = 0x1 + // Bit CACHE_DBG_EN. + EXTMEM_CACHE_DBG_INT_ENA_CACHE_DBG_EN = 0x1 + // Position of IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_IBUS_ACS_MSK_IC_INT_ENA_Pos = 0x2 + // Bit mask of IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_IBUS_ACS_MSK_IC_INT_ENA_Msk = 0x4 + // Bit IBUS_ACS_MSK_IC_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_IBUS_ACS_MSK_IC_INT_ENA = 0x4 + // Position of IBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_IBUS_CNT_OVF_INT_ENA_Pos = 0x3 + // Bit mask of IBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_IBUS_CNT_OVF_INT_ENA_Msk = 0x8 + // Bit IBUS_CNT_OVF_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_IBUS_CNT_OVF_INT_ENA = 0x8 + // Position of IC_SYNC_SIZE_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_IC_SYNC_SIZE_FAULT_INT_ENA_Pos = 0x4 + // Bit mask of IC_SYNC_SIZE_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_IC_SYNC_SIZE_FAULT_INT_ENA_Msk = 0x10 + // Bit IC_SYNC_SIZE_FAULT_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_IC_SYNC_SIZE_FAULT_INT_ENA = 0x10 + // Position of IC_PRELOAD_SIZE_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_IC_PRELOAD_SIZE_FAULT_INT_ENA_Pos = 0x5 + // Bit mask of IC_PRELOAD_SIZE_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_IC_PRELOAD_SIZE_FAULT_INT_ENA_Msk = 0x20 + // Bit IC_PRELOAD_SIZE_FAULT_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_IC_PRELOAD_SIZE_FAULT_INT_ENA = 0x20 + // Position of ICACHE_REJECT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_REJECT_INT_ENA_Pos = 0x6 + // Bit mask of ICACHE_REJECT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_REJECT_INT_ENA_Msk = 0x40 + // Bit ICACHE_REJECT_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_REJECT_INT_ENA = 0x40 + // Position of ICACHE_SET_PRELOAD_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_SET_PRELOAD_ILG_INT_ENA_Pos = 0x7 + // Bit mask of ICACHE_SET_PRELOAD_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_SET_PRELOAD_ILG_INT_ENA_Msk = 0x80 + // Bit ICACHE_SET_PRELOAD_ILG_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_SET_PRELOAD_ILG_INT_ENA = 0x80 + // Position of ICACHE_SET_SYNC_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_SET_SYNC_ILG_INT_ENA_Pos = 0x8 + // Bit mask of ICACHE_SET_SYNC_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_SET_SYNC_ILG_INT_ENA_Msk = 0x100 + // Bit ICACHE_SET_SYNC_ILG_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_SET_SYNC_ILG_INT_ENA = 0x100 + // Position of ICACHE_SET_LOCK_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_SET_LOCK_ILG_INT_ENA_Pos = 0x9 + // Bit mask of ICACHE_SET_LOCK_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_SET_LOCK_ILG_INT_ENA_Msk = 0x200 + // Bit ICACHE_SET_LOCK_ILG_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_ICACHE_SET_LOCK_ILG_INT_ENA = 0x200 + // Position of DBUS_ACS_MSK_DC_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DBUS_ACS_MSK_DC_INT_ENA_Pos = 0xa + // Bit mask of DBUS_ACS_MSK_DC_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DBUS_ACS_MSK_DC_INT_ENA_Msk = 0x400 + // Bit DBUS_ACS_MSK_DC_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_DBUS_ACS_MSK_DC_INT_ENA = 0x400 + // Position of DBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DBUS_CNT_OVF_INT_ENA_Pos = 0xb + // Bit mask of DBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DBUS_CNT_OVF_INT_ENA_Msk = 0x800 + // Bit DBUS_CNT_OVF_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_DBUS_CNT_OVF_INT_ENA = 0x800 + // Position of DC_SYNC_SIZE_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DC_SYNC_SIZE_FAULT_INT_ENA_Pos = 0xc + // Bit mask of DC_SYNC_SIZE_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DC_SYNC_SIZE_FAULT_INT_ENA_Msk = 0x1000 + // Bit DC_SYNC_SIZE_FAULT_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_DC_SYNC_SIZE_FAULT_INT_ENA = 0x1000 + // Position of DC_PRELOAD_SIZE_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DC_PRELOAD_SIZE_FAULT_INT_ENA_Pos = 0xd + // Bit mask of DC_PRELOAD_SIZE_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DC_PRELOAD_SIZE_FAULT_INT_ENA_Msk = 0x2000 + // Bit DC_PRELOAD_SIZE_FAULT_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_DC_PRELOAD_SIZE_FAULT_INT_ENA = 0x2000 + // Position of DCACHE_WRITE_FLASH_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA_Pos = 0xe + // Bit mask of DCACHE_WRITE_FLASH_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA_Msk = 0x4000 + // Bit DCACHE_WRITE_FLASH_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA = 0x4000 + // Position of DCACHE_REJECT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_REJECT_INT_ENA_Pos = 0xf + // Bit mask of DCACHE_REJECT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_REJECT_INT_ENA_Msk = 0x8000 + // Bit DCACHE_REJECT_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_REJECT_INT_ENA = 0x8000 + // Position of DCACHE_SET_PRELOAD_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_SET_PRELOAD_ILG_INT_ENA_Pos = 0x10 + // Bit mask of DCACHE_SET_PRELOAD_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_SET_PRELOAD_ILG_INT_ENA_Msk = 0x10000 + // Bit DCACHE_SET_PRELOAD_ILG_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_SET_PRELOAD_ILG_INT_ENA = 0x10000 + // Position of DCACHE_SET_SYNC_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_SET_SYNC_ILG_INT_ENA_Pos = 0x11 + // Bit mask of DCACHE_SET_SYNC_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_SET_SYNC_ILG_INT_ENA_Msk = 0x20000 + // Bit DCACHE_SET_SYNC_ILG_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_SET_SYNC_ILG_INT_ENA = 0x20000 + // Position of DCACHE_SET_LOCK_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_SET_LOCK_ILG_INT_ENA_Pos = 0x12 + // Bit mask of DCACHE_SET_LOCK_ILG_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_SET_LOCK_ILG_INT_ENA_Msk = 0x40000 + // Bit DCACHE_SET_LOCK_ILG_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_DCACHE_SET_LOCK_ILG_INT_ENA = 0x40000 + // Position of MMU_ENTRY_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA_Pos = 0x13 + // Bit mask of MMU_ENTRY_FAULT_INT_ENA field. + EXTMEM_CACHE_DBG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA_Msk = 0x80000 + // Bit MMU_ENTRY_FAULT_INT_ENA. + EXTMEM_CACHE_DBG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA = 0x80000 + + // CACHE_DBG_INT_CLR: register description + // Position of IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_IBUS_ACS_MSK_IC_INT_CLR_Pos = 0x0 + // Bit mask of IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_IBUS_ACS_MSK_IC_INT_CLR_Msk = 0x1 + // Bit IBUS_ACS_MSK_IC_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_IBUS_ACS_MSK_IC_INT_CLR = 0x1 + // Position of IBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_IBUS_CNT_OVF_INT_CLR_Pos = 0x1 + // Bit mask of IBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_IBUS_CNT_OVF_INT_CLR_Msk = 0x2 + // Bit IBUS_CNT_OVF_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_IBUS_CNT_OVF_INT_CLR = 0x2 + // Position of IC_SYNC_SIZE_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_IC_SYNC_SIZE_FAULT_INT_CLR_Pos = 0x2 + // Bit mask of IC_SYNC_SIZE_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_IC_SYNC_SIZE_FAULT_INT_CLR_Msk = 0x4 + // Bit IC_SYNC_SIZE_FAULT_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_IC_SYNC_SIZE_FAULT_INT_CLR = 0x4 + // Position of IC_PRELOAD_SIZE_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_IC_PRELOAD_SIZE_FAULT_INT_CLR_Pos = 0x3 + // Bit mask of IC_PRELOAD_SIZE_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_IC_PRELOAD_SIZE_FAULT_INT_CLR_Msk = 0x8 + // Bit IC_PRELOAD_SIZE_FAULT_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_IC_PRELOAD_SIZE_FAULT_INT_CLR = 0x8 + // Position of ICACHE_REJECT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_ICACHE_REJECT_INT_CLR_Pos = 0x4 + // Bit mask of ICACHE_REJECT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_ICACHE_REJECT_INT_CLR_Msk = 0x10 + // Bit ICACHE_REJECT_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_ICACHE_REJECT_INT_CLR = 0x10 + // Position of ICACHE_SET_ILG_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_ICACHE_SET_ILG_INT_CLR_Pos = 0x5 + // Bit mask of ICACHE_SET_ILG_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_ICACHE_SET_ILG_INT_CLR_Msk = 0x20 + // Bit ICACHE_SET_ILG_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_ICACHE_SET_ILG_INT_CLR = 0x20 + // Position of DBUS_ACS_MSK_DC_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DBUS_ACS_MSK_DC_INT_CLR_Pos = 0x6 + // Bit mask of DBUS_ACS_MSK_DC_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DBUS_ACS_MSK_DC_INT_CLR_Msk = 0x40 + // Bit DBUS_ACS_MSK_DC_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_DBUS_ACS_MSK_DC_INT_CLR = 0x40 + // Position of DBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DBUS_CNT_OVF_INT_CLR_Pos = 0x7 + // Bit mask of DBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DBUS_CNT_OVF_INT_CLR_Msk = 0x80 + // Bit DBUS_CNT_OVF_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_DBUS_CNT_OVF_INT_CLR = 0x80 + // Position of DC_SYNC_SIZE_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DC_SYNC_SIZE_FAULT_INT_CLR_Pos = 0x8 + // Bit mask of DC_SYNC_SIZE_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DC_SYNC_SIZE_FAULT_INT_CLR_Msk = 0x100 + // Bit DC_SYNC_SIZE_FAULT_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_DC_SYNC_SIZE_FAULT_INT_CLR = 0x100 + // Position of DC_PRELOAD_SIZE_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DC_PRELOAD_SIZE_FAULT_INT_CLR_Pos = 0x9 + // Bit mask of DC_PRELOAD_SIZE_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DC_PRELOAD_SIZE_FAULT_INT_CLR_Msk = 0x200 + // Bit DC_PRELOAD_SIZE_FAULT_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_DC_PRELOAD_SIZE_FAULT_INT_CLR = 0x200 + // Position of DCACHE_WRITE_FLASH_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR_Pos = 0xa + // Bit mask of DCACHE_WRITE_FLASH_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR_Msk = 0x400 + // Bit DCACHE_WRITE_FLASH_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR = 0x400 + // Position of DCACHE_REJECT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DCACHE_REJECT_INT_CLR_Pos = 0xb + // Bit mask of DCACHE_REJECT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DCACHE_REJECT_INT_CLR_Msk = 0x800 + // Bit DCACHE_REJECT_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_DCACHE_REJECT_INT_CLR = 0x800 + // Position of DCACHE_SET_ILG_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DCACHE_SET_ILG_INT_CLR_Pos = 0xc + // Bit mask of DCACHE_SET_ILG_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_DCACHE_SET_ILG_INT_CLR_Msk = 0x1000 + // Bit DCACHE_SET_ILG_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_DCACHE_SET_ILG_INT_CLR = 0x1000 + // Position of MMU_ENTRY_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR_Pos = 0xd + // Bit mask of MMU_ENTRY_FAULT_INT_CLR field. + EXTMEM_CACHE_DBG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR_Msk = 0x2000 + // Bit MMU_ENTRY_FAULT_INT_CLR. + EXTMEM_CACHE_DBG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR = 0x2000 + + // CACHE_DBG_STATUS0: register description + // Position of IBUS0_ACS_MSK_ICACHE_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ACS_MSK_ICACHE_ST_Pos = 0x0 + // Bit mask of IBUS0_ACS_MSK_ICACHE_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ACS_MSK_ICACHE_ST_Msk = 0x1 + // Bit IBUS0_ACS_MSK_ICACHE_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ACS_MSK_ICACHE_ST = 0x1 + // Position of IBUS1_ACS_MSK_ICACHE_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ACS_MSK_ICACHE_ST_Pos = 0x1 + // Bit mask of IBUS1_ACS_MSK_ICACHE_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ACS_MSK_ICACHE_ST_Msk = 0x2 + // Bit IBUS1_ACS_MSK_ICACHE_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ACS_MSK_ICACHE_ST = 0x2 + // Position of IBUS2_ACS_MSK_ICACHE_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ACS_MSK_ICACHE_ST_Pos = 0x2 + // Bit mask of IBUS2_ACS_MSK_ICACHE_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ACS_MSK_ICACHE_ST_Msk = 0x4 + // Bit IBUS2_ACS_MSK_ICACHE_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ACS_MSK_ICACHE_ST = 0x4 + // Position of IBUS0_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ACS_CNT_OVF_ST_Pos = 0x4 + // Bit mask of IBUS0_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ACS_CNT_OVF_ST_Msk = 0x10 + // Bit IBUS0_ACS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ACS_CNT_OVF_ST = 0x10 + // Position of IBUS1_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ACS_CNT_OVF_ST_Pos = 0x5 + // Bit mask of IBUS1_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ACS_CNT_OVF_ST_Msk = 0x20 + // Bit IBUS1_ACS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ACS_CNT_OVF_ST = 0x20 + // Position of IBUS2_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ACS_CNT_OVF_ST_Pos = 0x6 + // Bit mask of IBUS2_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ACS_CNT_OVF_ST_Msk = 0x40 + // Bit IBUS2_ACS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ACS_CNT_OVF_ST = 0x40 + // Position of IBUS0_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ACS_MISS_CNT_OVF_ST_Pos = 0x8 + // Bit mask of IBUS0_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ACS_MISS_CNT_OVF_ST_Msk = 0x100 + // Bit IBUS0_ACS_MISS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ACS_MISS_CNT_OVF_ST = 0x100 + // Position of IBUS1_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ACS_MISS_CNT_OVF_ST_Pos = 0x9 + // Bit mask of IBUS1_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ACS_MISS_CNT_OVF_ST_Msk = 0x200 + // Bit IBUS1_ACS_MISS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ACS_MISS_CNT_OVF_ST = 0x200 + // Position of IBUS2_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ACS_MISS_CNT_OVF_ST_Pos = 0xa + // Bit mask of IBUS2_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ACS_MISS_CNT_OVF_ST_Msk = 0x400 + // Bit IBUS2_ACS_MISS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ACS_MISS_CNT_OVF_ST = 0x400 + // Position of IBUS0_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ABANDON_CNT_OVF_ST_Pos = 0xc + // Bit mask of IBUS0_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ABANDON_CNT_OVF_ST_Msk = 0x1000 + // Bit IBUS0_ABANDON_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS0_ABANDON_CNT_OVF_ST = 0x1000 + // Position of IBUS1_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ABANDON_CNT_OVF_ST_Pos = 0xd + // Bit mask of IBUS1_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ABANDON_CNT_OVF_ST_Msk = 0x2000 + // Bit IBUS1_ABANDON_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS1_ABANDON_CNT_OVF_ST = 0x2000 + // Position of IBUS2_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ABANDON_CNT_OVF_ST_Pos = 0xe + // Bit mask of IBUS2_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ABANDON_CNT_OVF_ST_Msk = 0x4000 + // Bit IBUS2_ABANDON_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IBUS2_ABANDON_CNT_OVF_ST = 0x4000 + // Position of IC_PRELOAD_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IC_PRELOAD_MISS_CNT_OVF_ST_Pos = 0x10 + // Bit mask of IC_PRELOAD_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IC_PRELOAD_MISS_CNT_OVF_ST_Msk = 0x10000 + // Bit IC_PRELOAD_MISS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IC_PRELOAD_MISS_CNT_OVF_ST = 0x10000 + // Position of IC_PRELOAD_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IC_PRELOAD_CNT_OVF_ST_Pos = 0x12 + // Bit mask of IC_PRELOAD_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS0_IC_PRELOAD_CNT_OVF_ST_Msk = 0x40000 + // Bit IC_PRELOAD_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS0_IC_PRELOAD_CNT_OVF_ST = 0x40000 + // Position of IC_SYNC_SIZE_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS0_IC_SYNC_SIZE_FAULT_ST_Pos = 0x13 + // Bit mask of IC_SYNC_SIZE_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS0_IC_SYNC_SIZE_FAULT_ST_Msk = 0x80000 + // Bit IC_SYNC_SIZE_FAULT_ST. + EXTMEM_CACHE_DBG_STATUS0_IC_SYNC_SIZE_FAULT_ST = 0x80000 + // Position of IC_PRELOAD_SIZE_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS0_IC_PRELOAD_SIZE_FAULT_ST_Pos = 0x14 + // Bit mask of IC_PRELOAD_SIZE_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS0_IC_PRELOAD_SIZE_FAULT_ST_Msk = 0x100000 + // Bit IC_PRELOAD_SIZE_FAULT_ST. + EXTMEM_CACHE_DBG_STATUS0_IC_PRELOAD_SIZE_FAULT_ST = 0x100000 + // Position of ICACHE_REJECT_ST field. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_REJECT_ST_Pos = 0x15 + // Bit mask of ICACHE_REJECT_ST field. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_REJECT_ST_Msk = 0x200000 + // Bit ICACHE_REJECT_ST. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_REJECT_ST = 0x200000 + // Position of ICACHE_SET_PRELOAD_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_SET_PRELOAD_ILG_ST_Pos = 0x16 + // Bit mask of ICACHE_SET_PRELOAD_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_SET_PRELOAD_ILG_ST_Msk = 0x400000 + // Bit ICACHE_SET_PRELOAD_ILG_ST. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_SET_PRELOAD_ILG_ST = 0x400000 + // Position of ICACHE_SET_SYNC_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_SET_SYNC_ILG_ST_Pos = 0x17 + // Bit mask of ICACHE_SET_SYNC_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_SET_SYNC_ILG_ST_Msk = 0x800000 + // Bit ICACHE_SET_SYNC_ILG_ST. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_SET_SYNC_ILG_ST = 0x800000 + // Position of ICACHE_SET_LOCK_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_SET_LOCK_ILG_ST_Pos = 0x18 + // Bit mask of ICACHE_SET_LOCK_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_SET_LOCK_ILG_ST_Msk = 0x1000000 + // Bit ICACHE_SET_LOCK_ILG_ST. + EXTMEM_CACHE_DBG_STATUS0_ICACHE_SET_LOCK_ILG_ST = 0x1000000 + + // CACHE_DBG_STATUS1: register description + // Position of DBUS0_ACS_MSK_DCACHE_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_MSK_DCACHE_ST_Pos = 0x0 + // Bit mask of DBUS0_ACS_MSK_DCACHE_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_MSK_DCACHE_ST_Msk = 0x1 + // Bit DBUS0_ACS_MSK_DCACHE_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_MSK_DCACHE_ST = 0x1 + // Position of DBUS1_ACS_MSK_DCACHE_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_MSK_DCACHE_ST_Pos = 0x1 + // Bit mask of DBUS1_ACS_MSK_DCACHE_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_MSK_DCACHE_ST_Msk = 0x2 + // Bit DBUS1_ACS_MSK_DCACHE_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_MSK_DCACHE_ST = 0x2 + // Position of DBUS2_ACS_MSK_DCACHE_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_MSK_DCACHE_ST_Pos = 0x2 + // Bit mask of DBUS2_ACS_MSK_DCACHE_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_MSK_DCACHE_ST_Msk = 0x4 + // Bit DBUS2_ACS_MSK_DCACHE_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_MSK_DCACHE_ST = 0x4 + // Position of DBUS0_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_CNT_OVF_ST_Pos = 0x4 + // Bit mask of DBUS0_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_CNT_OVF_ST_Msk = 0x10 + // Bit DBUS0_ACS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_CNT_OVF_ST = 0x10 + // Position of DBUS1_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_CNT_OVF_ST_Pos = 0x5 + // Bit mask of DBUS1_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_CNT_OVF_ST_Msk = 0x20 + // Bit DBUS1_ACS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_CNT_OVF_ST = 0x20 + // Position of DBUS2_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_CNT_OVF_ST_Pos = 0x6 + // Bit mask of DBUS2_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_CNT_OVF_ST_Msk = 0x40 + // Bit DBUS2_ACS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_CNT_OVF_ST = 0x40 + // Position of DBUS0_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_MISS_CNT_OVF_ST_Pos = 0x8 + // Bit mask of DBUS0_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_MISS_CNT_OVF_ST_Msk = 0x100 + // Bit DBUS0_ACS_MISS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_MISS_CNT_OVF_ST = 0x100 + // Position of DBUS1_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_MISS_CNT_OVF_ST_Pos = 0x9 + // Bit mask of DBUS1_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_MISS_CNT_OVF_ST_Msk = 0x200 + // Bit DBUS1_ACS_MISS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_MISS_CNT_OVF_ST = 0x200 + // Position of DBUS2_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_MISS_CNT_OVF_ST_Pos = 0xa + // Bit mask of DBUS2_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_MISS_CNT_OVF_ST_Msk = 0x400 + // Bit DBUS2_ACS_MISS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_MISS_CNT_OVF_ST = 0x400 + // Position of DBUS0_ACS_WB_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_WB_CNT_OVF_ST_Pos = 0xc + // Bit mask of DBUS0_ACS_WB_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_WB_CNT_OVF_ST_Msk = 0x1000 + // Bit DBUS0_ACS_WB_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ACS_WB_CNT_OVF_ST = 0x1000 + // Position of DBUS1_ACS_WB_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_WB_CNT_OVF_ST_Pos = 0xd + // Bit mask of DBUS1_ACS_WB_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_WB_CNT_OVF_ST_Msk = 0x2000 + // Bit DBUS1_ACS_WB_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ACS_WB_CNT_OVF_ST = 0x2000 + // Position of DBUS2_ACS_WB_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_WB_CNT_OVF_ST_Pos = 0xe + // Bit mask of DBUS2_ACS_WB_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_WB_CNT_OVF_ST_Msk = 0x4000 + // Bit DBUS2_ACS_WB_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ACS_WB_CNT_OVF_ST = 0x4000 + // Position of DBUS0_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ABANDON_CNT_OVF_ST_Pos = 0x10 + // Bit mask of DBUS0_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ABANDON_CNT_OVF_ST_Msk = 0x10000 + // Bit DBUS0_ABANDON_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS0_ABANDON_CNT_OVF_ST = 0x10000 + // Position of DBUS1_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ABANDON_CNT_OVF_ST_Pos = 0x11 + // Bit mask of DBUS1_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ABANDON_CNT_OVF_ST_Msk = 0x20000 + // Bit DBUS1_ABANDON_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS1_ABANDON_CNT_OVF_ST = 0x20000 + // Position of DBUS2_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ABANDON_CNT_OVF_ST_Pos = 0x12 + // Bit mask of DBUS2_ABANDON_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ABANDON_CNT_OVF_ST_Msk = 0x40000 + // Bit DBUS2_ABANDON_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DBUS2_ABANDON_CNT_OVF_ST = 0x40000 + // Position of DC_PRELOAD_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_MISS_CNT_OVF_ST_Pos = 0x14 + // Bit mask of DC_PRELOAD_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_MISS_CNT_OVF_ST_Msk = 0x100000 + // Bit DC_PRELOAD_MISS_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_MISS_CNT_OVF_ST = 0x100000 + // Position of DC_PRELOAD_EVICT_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_EVICT_CNT_OVF_ST_Pos = 0x15 + // Bit mask of DC_PRELOAD_EVICT_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_EVICT_CNT_OVF_ST_Msk = 0x200000 + // Bit DC_PRELOAD_EVICT_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_EVICT_CNT_OVF_ST = 0x200000 + // Position of DC_PRELOAD_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_CNT_OVF_ST_Pos = 0x16 + // Bit mask of DC_PRELOAD_CNT_OVF_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_CNT_OVF_ST_Msk = 0x400000 + // Bit DC_PRELOAD_CNT_OVF_ST. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_CNT_OVF_ST = 0x400000 + // Position of DC_SYNC_SIZE_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_SYNC_SIZE_FAULT_ST_Pos = 0x17 + // Bit mask of DC_SYNC_SIZE_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_SYNC_SIZE_FAULT_ST_Msk = 0x800000 + // Bit DC_SYNC_SIZE_FAULT_ST. + EXTMEM_CACHE_DBG_STATUS1_DC_SYNC_SIZE_FAULT_ST = 0x800000 + // Position of DC_PRELOAD_SIZE_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_SIZE_FAULT_ST_Pos = 0x18 + // Bit mask of DC_PRELOAD_SIZE_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_SIZE_FAULT_ST_Msk = 0x1000000 + // Bit DC_PRELOAD_SIZE_FAULT_ST. + EXTMEM_CACHE_DBG_STATUS1_DC_PRELOAD_SIZE_FAULT_ST = 0x1000000 + // Position of DCACHE_WRITE_FLASH_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_WRITE_FLASH_ST_Pos = 0x19 + // Bit mask of DCACHE_WRITE_FLASH_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_WRITE_FLASH_ST_Msk = 0x2000000 + // Bit DCACHE_WRITE_FLASH_ST. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_WRITE_FLASH_ST = 0x2000000 + // Position of DCACHE_REJECT_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_REJECT_ST_Pos = 0x1a + // Bit mask of DCACHE_REJECT_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_REJECT_ST_Msk = 0x4000000 + // Bit DCACHE_REJECT_ST. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_REJECT_ST = 0x4000000 + // Position of DCACHE_SET_PRELOAD_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_SET_PRELOAD_ILG_ST_Pos = 0x1b + // Bit mask of DCACHE_SET_PRELOAD_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_SET_PRELOAD_ILG_ST_Msk = 0x8000000 + // Bit DCACHE_SET_PRELOAD_ILG_ST. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_SET_PRELOAD_ILG_ST = 0x8000000 + // Position of DCACHE_SET_SYNC_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_SET_SYNC_ILG_ST_Pos = 0x1c + // Bit mask of DCACHE_SET_SYNC_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_SET_SYNC_ILG_ST_Msk = 0x10000000 + // Bit DCACHE_SET_SYNC_ILG_ST. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_SET_SYNC_ILG_ST = 0x10000000 + // Position of DCACHE_SET_LOCK_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_SET_LOCK_ILG_ST_Pos = 0x1d + // Bit mask of DCACHE_SET_LOCK_ILG_ST field. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_SET_LOCK_ILG_ST_Msk = 0x20000000 + // Bit DCACHE_SET_LOCK_ILG_ST. + EXTMEM_CACHE_DBG_STATUS1_DCACHE_SET_LOCK_ILG_ST = 0x20000000 + // Position of MMU_ENTRY_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS1_MMU_ENTRY_FAULT_ST_Pos = 0x1e + // Bit mask of MMU_ENTRY_FAULT_ST field. + EXTMEM_CACHE_DBG_STATUS1_MMU_ENTRY_FAULT_ST_Msk = 0x40000000 + // Bit MMU_ENTRY_FAULT_ST. + EXTMEM_CACHE_DBG_STATUS1_MMU_ENTRY_FAULT_ST = 0x40000000 + + // PRO_CACHE_ACS_CNT_CLR: register description + // Position of PRO_DCACHE_ACS_CNT_CLR field. + EXTMEM_PRO_CACHE_ACS_CNT_CLR_PRO_DCACHE_ACS_CNT_CLR_Pos = 0x0 + // Bit mask of PRO_DCACHE_ACS_CNT_CLR field. + EXTMEM_PRO_CACHE_ACS_CNT_CLR_PRO_DCACHE_ACS_CNT_CLR_Msk = 0x1 + // Bit PRO_DCACHE_ACS_CNT_CLR. + EXTMEM_PRO_CACHE_ACS_CNT_CLR_PRO_DCACHE_ACS_CNT_CLR = 0x1 + // Position of PRO_ICACHE_ACS_CNT_CLR field. + EXTMEM_PRO_CACHE_ACS_CNT_CLR_PRO_ICACHE_ACS_CNT_CLR_Pos = 0x1 + // Bit mask of PRO_ICACHE_ACS_CNT_CLR field. + EXTMEM_PRO_CACHE_ACS_CNT_CLR_PRO_ICACHE_ACS_CNT_CLR_Msk = 0x2 + // Bit PRO_ICACHE_ACS_CNT_CLR. + EXTMEM_PRO_CACHE_ACS_CNT_CLR_PRO_ICACHE_ACS_CNT_CLR = 0x2 + + // PRO_DCACHE_REJECT_ST: register description + // Position of PRO_DCACHE_TAG_ATTR field. + EXTMEM_PRO_DCACHE_REJECT_ST_PRO_DCACHE_TAG_ATTR_Pos = 0x0 + // Bit mask of PRO_DCACHE_TAG_ATTR field. + EXTMEM_PRO_DCACHE_REJECT_ST_PRO_DCACHE_TAG_ATTR_Msk = 0x7 + // Position of PRO_DCACHE_CPU_ATTR field. + EXTMEM_PRO_DCACHE_REJECT_ST_PRO_DCACHE_CPU_ATTR_Pos = 0x3 + // Bit mask of PRO_DCACHE_CPU_ATTR field. + EXTMEM_PRO_DCACHE_REJECT_ST_PRO_DCACHE_CPU_ATTR_Msk = 0x38 + + // PRO_DCACHE_REJECT_VADDR: register description + // Position of PRO_DCACHE_CPU_VADDR field. + EXTMEM_PRO_DCACHE_REJECT_VADDR_PRO_DCACHE_CPU_VADDR_Pos = 0x0 + // Bit mask of PRO_DCACHE_CPU_VADDR field. + EXTMEM_PRO_DCACHE_REJECT_VADDR_PRO_DCACHE_CPU_VADDR_Msk = 0xffffffff + + // PRO_ICACHE_REJECT_ST: register description + // Position of PRO_ICACHE_TAG_ATTR field. + EXTMEM_PRO_ICACHE_REJECT_ST_PRO_ICACHE_TAG_ATTR_Pos = 0x0 + // Bit mask of PRO_ICACHE_TAG_ATTR field. + EXTMEM_PRO_ICACHE_REJECT_ST_PRO_ICACHE_TAG_ATTR_Msk = 0x7 + // Position of PRO_ICACHE_CPU_ATTR field. + EXTMEM_PRO_ICACHE_REJECT_ST_PRO_ICACHE_CPU_ATTR_Pos = 0x3 + // Bit mask of PRO_ICACHE_CPU_ATTR field. + EXTMEM_PRO_ICACHE_REJECT_ST_PRO_ICACHE_CPU_ATTR_Msk = 0x38 + + // PRO_ICACHE_REJECT_VADDR: register description + // Position of PRO_ICACHE_CPU_VADDR field. + EXTMEM_PRO_ICACHE_REJECT_VADDR_PRO_ICACHE_CPU_VADDR_Pos = 0x0 + // Bit mask of PRO_ICACHE_CPU_VADDR field. + EXTMEM_PRO_ICACHE_REJECT_VADDR_PRO_ICACHE_CPU_VADDR_Msk = 0xffffffff + + // PRO_CACHE_MMU_FAULT_CONTENT: register description + // Position of PRO_CACHE_MMU_FAULT_CONTENT field. + EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_PRO_CACHE_MMU_FAULT_CONTENT_Pos = 0x0 + // Bit mask of PRO_CACHE_MMU_FAULT_CONTENT field. + EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_PRO_CACHE_MMU_FAULT_CONTENT_Msk = 0x1ffff + // Position of PRO_CACHE_MMU_FAULT_CODE field. + EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_PRO_CACHE_MMU_FAULT_CODE_Pos = 0x11 + // Bit mask of PRO_CACHE_MMU_FAULT_CODE field. + EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_PRO_CACHE_MMU_FAULT_CODE_Msk = 0xe0000 + + // PRO_CACHE_MMU_FAULT_VADDR: register description + // Position of PRO_CACHE_MMU_FAULT_VADDR field. + EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_PRO_CACHE_MMU_FAULT_VADDR_Pos = 0x0 + // Bit mask of PRO_CACHE_MMU_FAULT_VADDR field. + EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_PRO_CACHE_MMU_FAULT_VADDR_Msk = 0xffffffff + + // PRO_CACHE_WRAP_AROUND_CTRL: register description + // Position of PRO_CACHE_FLASH_WRAP_AROUND field. + EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_FLASH_WRAP_AROUND_Pos = 0x0 + // Bit mask of PRO_CACHE_FLASH_WRAP_AROUND field. + EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_FLASH_WRAP_AROUND_Msk = 0x1 + // Bit PRO_CACHE_FLASH_WRAP_AROUND. + EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_FLASH_WRAP_AROUND = 0x1 + // Position of PRO_CACHE_SRAM_RD_WRAP_AROUND field. + EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_SRAM_RD_WRAP_AROUND_Pos = 0x1 + // Bit mask of PRO_CACHE_SRAM_RD_WRAP_AROUND field. + EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_SRAM_RD_WRAP_AROUND_Msk = 0x2 + // Bit PRO_CACHE_SRAM_RD_WRAP_AROUND. + EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_PRO_CACHE_SRAM_RD_WRAP_AROUND = 0x2 + + // PRO_CACHE_MMU_POWER_CTRL: register description + // Position of PRO_CACHE_MMU_MEM_FORCE_ON field. + EXTMEM_PRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of PRO_CACHE_MMU_MEM_FORCE_ON field. + EXTMEM_PRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_ON_Msk = 0x1 + // Bit PRO_CACHE_MMU_MEM_FORCE_ON. + EXTMEM_PRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_ON = 0x1 + // Position of PRO_CACHE_MMU_MEM_FORCE_PD field. + EXTMEM_PRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of PRO_CACHE_MMU_MEM_FORCE_PD field. + EXTMEM_PRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PD_Msk = 0x2 + // Bit PRO_CACHE_MMU_MEM_FORCE_PD. + EXTMEM_PRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PD = 0x2 + // Position of PRO_CACHE_MMU_MEM_FORCE_PU field. + EXTMEM_PRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of PRO_CACHE_MMU_MEM_FORCE_PU field. + EXTMEM_PRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PU_Msk = 0x4 + // Bit PRO_CACHE_MMU_MEM_FORCE_PU. + EXTMEM_PRO_CACHE_MMU_POWER_CTRL_PRO_CACHE_MMU_MEM_FORCE_PU = 0x4 + + // PRO_CACHE_STATE: register description + // Position of PRO_ICACHE_STATE field. + EXTMEM_PRO_CACHE_STATE_PRO_ICACHE_STATE_Pos = 0x0 + // Bit mask of PRO_ICACHE_STATE field. + EXTMEM_PRO_CACHE_STATE_PRO_ICACHE_STATE_Msk = 0xfff + // Position of PRO_DCACHE_STATE field. + EXTMEM_PRO_CACHE_STATE_PRO_DCACHE_STATE_Pos = 0xc + // Bit mask of PRO_DCACHE_STATE field. + EXTMEM_PRO_CACHE_STATE_PRO_DCACHE_STATE_Msk = 0xfff000 + + // CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: register description + // Position of RECORD_DISABLE_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT_Pos = 0x0 + // Bit mask of RECORD_DISABLE_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT_Msk = 0x1 + // Bit RECORD_DISABLE_DB_ENCRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT = 0x1 + // Position of RECORD_DISABLE_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT_Pos = 0x1 + // Bit mask of RECORD_DISABLE_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT_Msk = 0x2 + // Bit RECORD_DISABLE_G0CB_DECRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT = 0x2 + + // CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: register description + // Position of CLK_FORCE_ON_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_DB_ENCRYPT_Pos = 0x0 + // Bit mask of CLK_FORCE_ON_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_DB_ENCRYPT_Msk = 0x1 + // Bit CLK_FORCE_ON_DB_ENCRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_DB_ENCRYPT = 0x1 + // Position of CLK_FORCE_ON_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_G0CB_DECRYPT_Pos = 0x1 + // Bit mask of CLK_FORCE_ON_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_G0CB_DECRYPT_Msk = 0x2 + // Bit CLK_FORCE_ON_G0CB_DECRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_G0CB_DECRYPT = 0x2 + // Position of CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_Pos = 0x2 + // Bit mask of CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_Msk = 0x4 + // Bit CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT = 0x4 + + // CACHE_BRIDGE_ARBITER_CTRL: register description + // Position of ALLOC_WB_HOLD_ARBITER field. + EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER_Pos = 0x0 + // Bit mask of ALLOC_WB_HOLD_ARBITER field. + EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER_Msk = 0x1 + // Bit ALLOC_WB_HOLD_ARBITER. + EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER = 0x1 + + // CACHE_PRELOAD_INT_CTRL: register description + // Position of PRO_ICACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ST_Pos = 0x0 + // Bit mask of PRO_ICACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ST_Msk = 0x1 + // Bit PRO_ICACHE_PRELOAD_INT_ST. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ST = 0x1 + // Position of PRO_ICACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ENA_Pos = 0x1 + // Bit mask of PRO_ICACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ENA_Msk = 0x2 + // Bit PRO_ICACHE_PRELOAD_INT_ENA. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_ENA = 0x2 + // Position of PRO_ICACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_CLR_Pos = 0x2 + // Bit mask of PRO_ICACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_CLR_Msk = 0x4 + // Bit PRO_ICACHE_PRELOAD_INT_CLR. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_ICACHE_PRELOAD_INT_CLR = 0x4 + // Position of PRO_DCACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ST_Pos = 0x3 + // Bit mask of PRO_DCACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ST_Msk = 0x8 + // Bit PRO_DCACHE_PRELOAD_INT_ST. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ST = 0x8 + // Position of PRO_DCACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ENA_Pos = 0x4 + // Bit mask of PRO_DCACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ENA_Msk = 0x10 + // Bit PRO_DCACHE_PRELOAD_INT_ENA. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_ENA = 0x10 + // Position of PRO_DCACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_CLR_Pos = 0x5 + // Bit mask of PRO_DCACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_CLR_Msk = 0x20 + // Bit PRO_DCACHE_PRELOAD_INT_CLR. + EXTMEM_CACHE_PRELOAD_INT_CTRL_PRO_DCACHE_PRELOAD_INT_CLR = 0x20 + + // CACHE_SYNC_INT_CTRL: register description + // Position of PRO_ICACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ST_Pos = 0x0 + // Bit mask of PRO_ICACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ST_Msk = 0x1 + // Bit PRO_ICACHE_SYNC_INT_ST. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ST = 0x1 + // Position of PRO_ICACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ENA_Pos = 0x1 + // Bit mask of PRO_ICACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ENA_Msk = 0x2 + // Bit PRO_ICACHE_SYNC_INT_ENA. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_ENA = 0x2 + // Position of PRO_ICACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_CLR_Pos = 0x2 + // Bit mask of PRO_ICACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_CLR_Msk = 0x4 + // Bit PRO_ICACHE_SYNC_INT_CLR. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_ICACHE_SYNC_INT_CLR = 0x4 + // Position of PRO_DCACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ST_Pos = 0x3 + // Bit mask of PRO_DCACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ST_Msk = 0x8 + // Bit PRO_DCACHE_SYNC_INT_ST. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ST = 0x8 + // Position of PRO_DCACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ENA_Pos = 0x4 + // Bit mask of PRO_DCACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ENA_Msk = 0x10 + // Bit PRO_DCACHE_SYNC_INT_ENA. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_ENA = 0x10 + // Position of PRO_DCACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_CLR_Pos = 0x5 + // Bit mask of PRO_DCACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_CLR_Msk = 0x20 + // Bit PRO_DCACHE_SYNC_INT_CLR. + EXTMEM_CACHE_SYNC_INT_CTRL_PRO_DCACHE_SYNC_INT_CLR = 0x20 + + // CACHE_CONF_MISC: register description + // Position of PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_Pos = 0x0 + // Bit mask of PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_Msk = 0x1 + // Bit PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT. + EXTMEM_CACHE_CONF_MISC_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT = 0x1 + // Position of PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_Pos = 0x1 + // Bit mask of PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_Msk = 0x2 + // Bit PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT. + EXTMEM_CACHE_CONF_MISC_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT = 0x2 + + // CLOCK_GATE: register description + // Position of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + EXTMEM_CLOCK_GATE_CLK_EN = 0x1 + + // PRO_EXTMEM_REG_DATE: register description + // Position of PRO_EXTMEM_REG_DATE field. + EXTMEM_PRO_EXTMEM_REG_DATE_PRO_EXTMEM_REG_DATE_Pos = 0x0 + // Bit mask of PRO_EXTMEM_REG_DATE field. + EXTMEM_PRO_EXTMEM_REG_DATE_PRO_EXTMEM_REG_DATE_Msk = 0xfffffff +) + +// Constants for GPIO: General Purpose Input/Output +const ( + // BT_SELECT: GPIO bit select register + // Position of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Pos = 0x0 + // Bit mask of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Msk = 0xffffffff + + // OUT: GPIO0 ~ 31 output register + // Position of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Pos = 0x0 + // Bit mask of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Msk = 0xffffffff + + // OUT_W1TS: GPIO0 ~ 31 output bit set register + // Position of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Pos = 0x0 + // Bit mask of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Msk = 0xffffffff + + // OUT_W1TC: GPIO0 ~ 31 output bit clear register + // Position of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Pos = 0x0 + // Bit mask of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Msk = 0xffffffff + + // OUT1: GPIO32 ~ 53 output register + // Position of DATA_ORIG field. + GPIO_OUT1_DATA_ORIG_Pos = 0x0 + // Bit mask of DATA_ORIG field. + GPIO_OUT1_DATA_ORIG_Msk = 0x3fffff + + // OUT1_W1TS: GPIO32 ~ 53 output bit set register + // Position of OUT1_W1TS field. + GPIO_OUT1_W1TS_OUT1_W1TS_Pos = 0x0 + // Bit mask of OUT1_W1TS field. + GPIO_OUT1_W1TS_OUT1_W1TS_Msk = 0x3fffff + + // OUT1_W1TC: GPIO32 ~ 53 output bit clear register + // Position of OUT1_W1TC field. + GPIO_OUT1_W1TC_OUT1_W1TC_Pos = 0x0 + // Bit mask of OUT1_W1TC field. + GPIO_OUT1_W1TC_OUT1_W1TC_Msk = 0x3fffff + + // SDIO_SELECT: GPIO SDIO selection register + // Position of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Pos = 0x0 + // Bit mask of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Msk = 0xff + + // ENABLE: GPIO0 ~ 31 output enable register + // Position of DATA field. + GPIO_ENABLE_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE_DATA_Msk = 0xffffffff + + // ENABLE_W1TS: GPIO0 ~ 31 output enable bit set register + // Position of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Pos = 0x0 + // Bit mask of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Msk = 0xffffffff + + // ENABLE_W1TC: GPIO0 ~ 31 output enable bit clear register + // Position of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0x0 + // Bit mask of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0xffffffff + + // ENABLE1: GPIO32 ~ 53 output enable register + // Position of DATA field. + GPIO_ENABLE1_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE1_DATA_Msk = 0x3fffff + + // ENABLE1_W1TS: GPIO32 ~ 53 output enable bit set register + // Position of ENABLE1_W1TS field. + GPIO_ENABLE1_W1TS_ENABLE1_W1TS_Pos = 0x0 + // Bit mask of ENABLE1_W1TS field. + GPIO_ENABLE1_W1TS_ENABLE1_W1TS_Msk = 0x3fffff + + // ENABLE1_W1TC: GPIO32 ~ 53 output enable bit clear register + // Position of ENABLE1_W1TC field. + GPIO_ENABLE1_W1TC_ENABLE1_W1TC_Pos = 0x0 + // Bit mask of ENABLE1_W1TC field. + GPIO_ENABLE1_W1TC_ENABLE1_W1TC_Msk = 0x3fffff + + // STRAP: Bootstrap pin value register + // Position of STRAPPING field. + GPIO_STRAP_STRAPPING_Pos = 0x0 + // Bit mask of STRAPPING field. + GPIO_STRAP_STRAPPING_Msk = 0xffff + + // IN: GPIO0 ~ 31 input register + // Position of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Msk = 0xffffffff + + // IN1: GPIO32 ~ 53 input register + // Position of IN_DATA1_NEXT field. + GPIO_IN1_IN_DATA1_NEXT_Pos = 0x0 + // Bit mask of IN_DATA1_NEXT field. + GPIO_IN1_IN_DATA1_NEXT_Msk = 0x3fffff + + // STATUS: GPIO0 ~ 31 interrupt status register + // Position of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Msk = 0xffffffff + + // STATUS_W1TS: GPIO0 ~ 31 interrupt status bit set register + // Position of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Pos = 0x0 + // Bit mask of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Msk = 0xffffffff + + // STATUS_W1TC: GPIO0 ~ 31 interrupt status bit clear register + // Position of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Pos = 0x0 + // Bit mask of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Msk = 0xffffffff + + // STATUS1: GPIO32 ~ 53 interrupt status register + // Position of INTERRUPT field. + GPIO_STATUS1_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + GPIO_STATUS1_INTERRUPT_Msk = 0x3fffff + + // STATUS1_W1TS: GPIO32 ~ 53 interrupt status bit set register + // Position of STATUS1_W1TS field. + GPIO_STATUS1_W1TS_STATUS1_W1TS_Pos = 0x0 + // Bit mask of STATUS1_W1TS field. + GPIO_STATUS1_W1TS_STATUS1_W1TS_Msk = 0x3fffff + + // STATUS1_W1TC: GPIO32 ~ 53 interrupt status bit clear register + // Position of STATUS1_W1TC field. + GPIO_STATUS1_W1TC_STATUS1_W1TC_Pos = 0x0 + // Bit mask of STATUS1_W1TC field. + GPIO_STATUS1_W1TC_STATUS1_W1TC_Msk = 0x3fffff + + // PCPU_INT: GPIO0 ~ 31 PRO_CPU interrupt status register + // Position of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Pos = 0x0 + // Bit mask of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Msk = 0xffffffff + + // PCPU_NMI_INT: GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register + // Position of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Msk = 0xffffffff + + // CPUSDIO_INT: GPIO0 ~ 31 CPU SDIO interrupt status register + // Position of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Pos = 0x0 + // Bit mask of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Msk = 0xffffffff + + // PCPU_INT1: GPIO32 ~ 53 PRO_CPU interrupt status register + // Position of PROCPU1_INT field. + GPIO_PCPU_INT1_PROCPU1_INT_Pos = 0x0 + // Bit mask of PROCPU1_INT field. + GPIO_PCPU_INT1_PROCPU1_INT_Msk = 0x3fffff + + // PCPU_NMI_INT1: GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register + // Position of PROCPU_NMI1_INT field. + GPIO_PCPU_NMI_INT1_PROCPU_NMI1_INT_Pos = 0x0 + // Bit mask of PROCPU_NMI1_INT field. + GPIO_PCPU_NMI_INT1_PROCPU_NMI1_INT_Msk = 0x3fffff + + // CPUSDIO_INT1: GPIO32 ~ 53 CPU SDIO interrupt status register + // Position of SDIO1_INT field. + GPIO_CPUSDIO_INT1_SDIO1_INT_Pos = 0x0 + // Bit mask of SDIO1_INT field. + GPIO_CPUSDIO_INT1_SDIO1_INT_Msk = 0x3fffff + + // PIN0: Configuration for GPIO pin %s + // Position of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Pos = 0x0 + // Bit mask of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Msk = 0x3 + // Position of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + GPIO_PIN_PAD_DRIVER = 0x4 + // Position of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Pos = 0x3 + // Bit mask of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Msk = 0x18 + // Position of INT_TYPE field. + GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + GPIO_PIN_WAKEUP_ENABLE = 0x400 + // Position of CONFIG field. + GPIO_PIN_CONFIG_Pos = 0xb + // Bit mask of CONFIG field. + GPIO_PIN_CONFIG_Msk = 0x1800 + // Position of INT_ENA field. + GPIO_PIN_INT_ENA_Pos = 0xd + // Bit mask of INT_ENA field. + GPIO_PIN_INT_ENA_Msk = 0x3e000 + + // STATUS_NEXT: GPIO0 ~ 31 interrupt source register + // Position of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Pos = 0x0 + // Bit mask of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Msk = 0xffffffff + + // STATUS_NEXT1: GPIO32 ~ 53 interrupt source register + // Position of STATUS1_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT1_STATUS1_INTERRUPT_NEXT_Pos = 0x0 + // Bit mask of STATUS1_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT1_STATUS1_INTERRUPT_NEXT_Msk = 0x3fffff + + // FUNC0_IN_SEL_CFG: Peripheral function %s input selection register + // Position of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Pos = 0x0 + // Bit mask of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Msk = 0x3f + // Position of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Pos = 0x6 + // Bit mask of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Msk = 0x40 + // Bit IN_INV_SEL. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL = 0x40 + // Position of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Pos = 0x7 + // Bit mask of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Msk = 0x80 + // Bit SEL. + GPIO_FUNC_IN_SEL_CFG_SEL = 0x80 + + // FUNC0_OUT_SEL_CFG: Peripheral output selection for GPIO %s + // Position of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Pos = 0x0 + // Bit mask of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Msk = 0x1ff + // Position of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Pos = 0x9 + // Bit mask of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Msk = 0x200 + // Bit INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL = 0x200 + // Position of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Pos = 0xa + // Bit mask of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Msk = 0x400 + // Bit OEN_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL = 0x400 + // Position of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Pos = 0xb + // Bit mask of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Msk = 0x800 + // Bit OEN_INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL = 0x800 + + // CLOCK_GATE: GPIO clock gating register + // Position of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + GPIO_CLOCK_GATE_CLK_EN = 0x1 + + // REG_DATE: Version control register + // Position of DATE field. + GPIO_REG_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + GPIO_REG_DATE_DATE_Msk = 0xfffffff +) + +// Constants for GPIO_SD: Sigma-Delta Modulation +const ( + // SIGMADELTA0: Duty-cycle configuration register of SDM%s + // Position of SD_IN field. + GPIOSD_SIGMADELTA_SD_IN_Pos = 0x0 + // Bit mask of SD_IN field. + GPIOSD_SIGMADELTA_SD_IN_Msk = 0xff + // Position of SD_PRESCALE field. + GPIOSD_SIGMADELTA_SD_PRESCALE_Pos = 0x8 + // Bit mask of SD_PRESCALE field. + GPIOSD_SIGMADELTA_SD_PRESCALE_Msk = 0xff00 + + // SIGMADELTA_CG: Clock gating configuration register + // Position of CLK_EN field. + GPIOSD_SIGMADELTA_CG_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + GPIOSD_SIGMADELTA_CG_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + GPIOSD_SIGMADELTA_CG_CLK_EN = 0x80000000 + + // SIGMADELTA_MISC: MISC register + // Position of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Pos = 0x1e + // Bit mask of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Msk = 0x40000000 + // Bit FUNCTION_CLK_EN. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN = 0x40000000 + // Position of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Pos = 0x1f + // Bit mask of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Msk = 0x80000000 + // Bit SPI_SWAP. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP = 0x80000000 + + // SIGMADELTA_VERSION: Version control register + // Position of GPIO_SD_DATE field. + GPIOSD_SIGMADELTA_VERSION_GPIO_SD_DATE_Pos = 0x0 + // Bit mask of GPIO_SD_DATE field. + GPIOSD_SIGMADELTA_VERSION_GPIO_SD_DATE_Msk = 0xfffffff +) + +// Constants for HMAC: HMAC (Hash-based Message Authentication Code) Accelerator +const ( + // SET_START: HMAC start control register + // Position of SET_START field. + HMAC_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + HMAC_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + HMAC_SET_START_SET_START = 0x1 + + // SET_PARA_PURPOSE: HMAC parameter configuration register + // Position of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Pos = 0x0 + // Bit mask of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Msk = 0xf + + // SET_PARA_KEY: HMAC key configuration register + // Position of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Pos = 0x0 + // Bit mask of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Msk = 0x7 + + // SET_PARA_FINISH: HMAC configuration completion register + // Position of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Pos = 0x0 + // Bit mask of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Msk = 0x1 + // Bit SET_PARA_END. + HMAC_SET_PARA_FINISH_SET_PARA_END = 0x1 + + // SET_MESSAGE_ONE: HMAC one message control register + // Position of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Pos = 0x0 + // Bit mask of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Msk = 0x1 + // Bit SET_TEXT_ONE. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE = 0x1 + + // SET_MESSAGE_ING: HMAC message continue register + // Position of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Pos = 0x0 + // Bit mask of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Msk = 0x1 + // Bit SET_TEXT_ING. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING = 0x1 + + // SET_MESSAGE_END: HMAC message end register + // Position of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Pos = 0x0 + // Bit mask of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Msk = 0x1 + // Bit SET_TEXT_END. + HMAC_SET_MESSAGE_END_SET_TEXT_END = 0x1 + + // SET_RESULT_FINISH: HMAC read result completion register + // Position of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Pos = 0x0 + // Bit mask of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Msk = 0x1 + // Bit SET_RESULT_END. + HMAC_SET_RESULT_FINISH_SET_RESULT_END = 0x1 + + // SET_INVALIDATE_JTAG: Invalidate JTAG result register + // Position of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Pos = 0x0 + // Bit mask of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Msk = 0x1 + // Bit SET_INVALIDATE_JTAG. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG = 0x1 + + // SET_INVALIDATE_DS: Invalidate digital signature result register + // Position of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Pos = 0x0 + // Bit mask of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Msk = 0x1 + // Bit SET_INVALIDATE_DS. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS = 0x1 + + // QUERY_ERROR: The matching result between key and purpose user configured + // Position of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Pos = 0x0 + // Bit mask of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Msk = 0x1 + // Bit QUERY_CHECK. + HMAC_QUERY_ERROR_QUERY_CHECK = 0x1 + + // QUERY_BUSY: The busy state of HMAC module + // Position of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Pos = 0x0 + // Bit mask of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Msk = 0x1 + // Bit BUSY_STATE. + HMAC_QUERY_BUSY_BUSY_STATE = 0x1 + + // WR_MESSAGE_0: Message register %s + // Position of WDATA field. + HMAC_WR_MESSAGE_WDATA_Pos = 0x0 + // Bit mask of WDATA field. + HMAC_WR_MESSAGE_WDATA_Msk = 0xffffffff + + // RD_RESULT_0: Hash result register %s + // Position of RDATA field. + HMAC_RD_RESULT_RDATA_Pos = 0x0 + // Bit mask of RDATA field. + HMAC_RD_RESULT_RDATA_Msk = 0xffffffff + + // SET_MESSAGE_PAD: Software padding register + // Position of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Pos = 0x0 + // Bit mask of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Msk = 0x1 + // Bit SET_TEXT_PAD. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD = 0x1 + + // ONE_BLOCK: One block message register. + // Position of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Pos = 0x0 + // Bit mask of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Msk = 0x1 + // Bit SET_ONE_BLOCK. + HMAC_ONE_BLOCK_SET_ONE_BLOCK = 0x1 + + // DATE: Version control register + // Position of DATE field. + HMAC_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + HMAC_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for I2C0: I2C (Inter-Integrated Circuit) Controller 0 +const ( + // SCL_LOW_PERIOD: Configures the low level width of the SCL clock + // Position of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x3fff + + // CTR: Transmission setting + // Position of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + I2C_CTR_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + I2C_CTR_SCL_FORCE_OUT = 0x2 + // Position of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2 + // Bit mask of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4 + // Bit SAMPLE_SCL_LEVEL. + I2C_CTR_SAMPLE_SCL_LEVEL = 0x4 + // Position of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Pos = 0x3 + // Bit mask of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Msk = 0x8 + // Bit RX_FULL_ACK_LEVEL. + I2C_CTR_RX_FULL_ACK_LEVEL = 0x8 + // Position of MS_MODE field. + I2C_CTR_MS_MODE_Pos = 0x4 + // Bit mask of MS_MODE field. + I2C_CTR_MS_MODE_Msk = 0x10 + // Bit MS_MODE. + I2C_CTR_MS_MODE = 0x10 + // Position of TRANS_START field. + I2C_CTR_TRANS_START_Pos = 0x5 + // Bit mask of TRANS_START field. + I2C_CTR_TRANS_START_Msk = 0x20 + // Bit TRANS_START. + I2C_CTR_TRANS_START = 0x20 + // Position of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Msk = 0x40 + // Bit TX_LSB_FIRST. + I2C_CTR_TX_LSB_FIRST = 0x40 + // Position of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Msk = 0x80 + // Bit RX_LSB_FIRST. + I2C_CTR_RX_LSB_FIRST = 0x80 + // Position of CLK_EN field. + I2C_CTR_CLK_EN_Pos = 0x8 + // Bit mask of CLK_EN field. + I2C_CTR_CLK_EN_Msk = 0x100 + // Bit CLK_EN. + I2C_CTR_CLK_EN = 0x100 + // Position of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Pos = 0x9 + // Bit mask of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Msk = 0x200 + // Bit ARBITRATION_EN. + I2C_CTR_ARBITRATION_EN = 0x200 + // Position of FSM_RST field. + I2C_CTR_FSM_RST_Pos = 0xa + // Bit mask of FSM_RST field. + I2C_CTR_FSM_RST_Msk = 0x400 + // Bit FSM_RST. + I2C_CTR_FSM_RST = 0x400 + // Position of REF_ALWAYS_ON field. + I2C_CTR_REF_ALWAYS_ON_Pos = 0xb + // Bit mask of REF_ALWAYS_ON field. + I2C_CTR_REF_ALWAYS_ON_Msk = 0x800 + // Bit REF_ALWAYS_ON. + I2C_CTR_REF_ALWAYS_ON = 0x800 + + // SR: Describe I2C work status + // Position of RESP_REC field. + I2C_SR_RESP_REC_Pos = 0x0 + // Bit mask of RESP_REC field. + I2C_SR_RESP_REC_Msk = 0x1 + // Bit RESP_REC. + I2C_SR_RESP_REC = 0x1 + // Position of SLAVE_RW field. + I2C_SR_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + I2C_SR_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + I2C_SR_SLAVE_RW = 0x2 + // Position of TIME_OUT field. + I2C_SR_TIME_OUT_Pos = 0x2 + // Bit mask of TIME_OUT field. + I2C_SR_TIME_OUT_Msk = 0x4 + // Bit TIME_OUT. + I2C_SR_TIME_OUT = 0x4 + // Position of ARB_LOST field. + I2C_SR_ARB_LOST_Pos = 0x3 + // Bit mask of ARB_LOST field. + I2C_SR_ARB_LOST_Msk = 0x8 + // Bit ARB_LOST. + I2C_SR_ARB_LOST = 0x8 + // Position of BUS_BUSY field. + I2C_SR_BUS_BUSY_Pos = 0x4 + // Bit mask of BUS_BUSY field. + I2C_SR_BUS_BUSY_Msk = 0x10 + // Bit BUS_BUSY. + I2C_SR_BUS_BUSY = 0x10 + // Position of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Pos = 0x5 + // Bit mask of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Msk = 0x20 + // Bit SLAVE_ADDRESSED. + I2C_SR_SLAVE_ADDRESSED = 0x20 + // Position of BYTE_TRANS field. + I2C_SR_BYTE_TRANS_Pos = 0x6 + // Bit mask of BYTE_TRANS field. + I2C_SR_BYTE_TRANS_Msk = 0x40 + // Bit BYTE_TRANS. + I2C_SR_BYTE_TRANS = 0x40 + // Position of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Pos = 0x8 + // Bit mask of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Msk = 0x3f00 + // Position of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Pos = 0xe + // Bit mask of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Msk = 0xc000 + // Position of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Pos = 0x12 + // Bit mask of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Msk = 0xfc0000 + // Position of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: Setting time out control for receiving data + // Position of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Pos = 0x0 + // Bit mask of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Msk = 0xffffff + // Position of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Pos = 0x18 + // Bit mask of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Msk = 0x1000000 + // Bit TIME_OUT_EN. + I2C_TO_TIME_OUT_EN = 0x1000000 + + // SLAVE_ADDR: Local slave address setting + // Position of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // FIFO_ST: FIFO status register + // Position of RXFIFO_START_ADDR field. + I2C_FIFO_ST_RXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of RXFIFO_START_ADDR field. + I2C_FIFO_ST_RXFIFO_START_ADDR_Msk = 0x1f + // Position of RXFIFO_END_ADDR field. + I2C_FIFO_ST_RXFIFO_END_ADDR_Pos = 0x5 + // Bit mask of RXFIFO_END_ADDR field. + I2C_FIFO_ST_RXFIFO_END_ADDR_Msk = 0x3e0 + // Position of TXFIFO_START_ADDR field. + I2C_FIFO_ST_TXFIFO_START_ADDR_Pos = 0xa + // Bit mask of TXFIFO_START_ADDR field. + I2C_FIFO_ST_TXFIFO_START_ADDR_Msk = 0x7c00 + // Position of TXFIFO_END_ADDR field. + I2C_FIFO_ST_TXFIFO_END_ADDR_Pos = 0xf + // Bit mask of TXFIFO_END_ADDR field. + I2C_FIFO_ST_TXFIFO_END_ADDR_Msk = 0xf8000 + // Position of RX_UPDATE field. + I2C_FIFO_ST_RX_UPDATE_Pos = 0x14 + // Bit mask of RX_UPDATE field. + I2C_FIFO_ST_RX_UPDATE_Msk = 0x100000 + // Bit RX_UPDATE. + I2C_FIFO_ST_RX_UPDATE = 0x100000 + // Position of TX_UPDATE field. + I2C_FIFO_ST_TX_UPDATE_Pos = 0x15 + // Bit mask of TX_UPDATE field. + I2C_FIFO_ST_TX_UPDATE_Msk = 0x200000 + // Bit TX_UPDATE. + I2C_FIFO_ST_TX_UPDATE = 0x200000 + // Position of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Pos = 0x16 + // Bit mask of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Msk = 0x3fc00000 + + // FIFO_CONF: FIFO configuration register + // Position of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0x1f + // Position of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5 + // Bit mask of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x3e0 + // Position of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa + // Bit mask of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400 + // Bit NONFIFO_EN. + I2C_FIFO_CONF_NONFIFO_EN = 0x400 + // Position of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Pos = 0xb + // Bit mask of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Msk = 0x800 + // Bit FIFO_ADDR_CFG_EN. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN = 0x800 + // Position of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc + // Bit mask of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000 + // Bit RX_FIFO_RST. + I2C_FIFO_CONF_RX_FIFO_RST = 0x1000 + // Position of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd + // Bit mask of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000 + // Bit TX_FIFO_RST. + I2C_FIFO_CONF_TX_FIFO_RST = 0x2000 + // Position of NONFIFO_RX_THRES field. + I2C_FIFO_CONF_NONFIFO_RX_THRES_Pos = 0xe + // Bit mask of NONFIFO_RX_THRES field. + I2C_FIFO_CONF_NONFIFO_RX_THRES_Msk = 0xfc000 + // Position of NONFIFO_TX_THRES field. + I2C_FIFO_CONF_NONFIFO_TX_THRES_Pos = 0x14 + // Bit mask of NONFIFO_TX_THRES field. + I2C_FIFO_CONF_NONFIFO_TX_THRES_Msk = 0x3f00000 + // Position of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Pos = 0x1a + // Bit mask of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000000 + // Bit FIFO_PRT_EN. + I2C_FIFO_CONF_FIFO_PRT_EN = 0x4000000 + + // DATA: RX FIFO read data + // Position of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Pos = 0x0 + // Bit mask of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Msk = 0x1 + // Bit RXFIFO_WM_INT_RAW. + I2C_INT_RAW_RXFIFO_WM_INT_RAW = 0x1 + // Position of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Msk = 0x2 + // Bit TXFIFO_WM_INT_RAW. + I2C_INT_RAW_TXFIFO_WM_INT_RAW = 0x2 + // Position of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4 + // Bit RXFIFO_OVF_INT_RAW. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4 + // Position of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3 + // Bit mask of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8 + // Bit END_DETECT_INT_RAW. + I2C_INT_RAW_END_DETECT_INT_RAW = 0x8 + // Position of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_RAW. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW = 0x10 + // Position of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_RAW. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20 + // Position of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_RAW. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW = 0x40 + // Position of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_RAW. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80 + // Position of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8 + // Bit mask of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100 + // Bit TIME_OUT_INT_RAW. + I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100 + // Position of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9 + // Bit mask of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200 + // Bit TRANS_START_INT_RAW. + I2C_INT_RAW_TRANS_START_INT_RAW = 0x200 + // Position of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Pos = 0xa + // Bit mask of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Msk = 0x400 + // Bit NACK_INT_RAW. + I2C_INT_RAW_NACK_INT_RAW = 0x400 + // Position of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Msk = 0x800 + // Bit TXFIFO_OVF_INT_RAW. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW = 0x800 + // Position of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_RAW. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW = 0x1000 + // Position of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Msk = 0x2000 + // Bit SCL_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_ST_TO_INT_RAW = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW = 0x4000 + // Position of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Pos = 0xf + // Bit mask of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Msk = 0x8000 + // Bit DET_START_INT_RAW. + I2C_INT_RAW_DET_START_INT_RAW = 0x8000 + // Position of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_RAW. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW = 0x10000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Msk = 0x1 + // Bit RXFIFO_WM_INT_CLR. + I2C_INT_CLR_RXFIFO_WM_INT_CLR = 0x1 + // Position of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Msk = 0x2 + // Bit TXFIFO_WM_INT_CLR. + I2C_INT_CLR_TXFIFO_WM_INT_CLR = 0x2 + // Position of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4 + // Bit RXFIFO_OVF_INT_CLR. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4 + // Position of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3 + // Bit mask of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8 + // Bit END_DETECT_INT_CLR. + I2C_INT_CLR_END_DETECT_INT_CLR = 0x8 + // Position of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_CLR. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR = 0x10 + // Position of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_CLR. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_CLR. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR = 0x40 + // Position of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_CLR. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit TIME_OUT_INT_CLR. + I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100 + // Position of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9 + // Bit mask of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200 + // Bit TRANS_START_INT_CLR. + I2C_INT_CLR_TRANS_START_INT_CLR = 0x200 + // Position of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Pos = 0xa + // Bit mask of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Msk = 0x400 + // Bit NACK_INT_CLR. + I2C_INT_CLR_NACK_INT_CLR = 0x400 + // Position of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Msk = 0x800 + // Bit TXFIFO_OVF_INT_CLR. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR = 0x800 + // Position of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_CLR. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR = 0x1000 + // Position of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Msk = 0x2000 + // Bit SCL_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_ST_TO_INT_CLR = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR = 0x4000 + // Position of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Pos = 0xf + // Bit mask of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Msk = 0x8000 + // Bit DET_START_INT_CLR. + I2C_INT_CLR_DET_START_INT_CLR = 0x8000 + // Position of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_CLR. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR = 0x10000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Msk = 0x1 + // Bit RXFIFO_WM_INT_ENA. + I2C_INT_ENA_RXFIFO_WM_INT_ENA = 0x1 + // Position of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Msk = 0x2 + // Bit TXFIFO_WM_INT_ENA. + I2C_INT_ENA_TXFIFO_WM_INT_ENA = 0x2 + // Position of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ENA. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4 + // Position of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3 + // Bit mask of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8 + // Bit END_DETECT_INT_ENA. + I2C_INT_ENA_END_DETECT_INT_ENA = 0x8 + // Position of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ENA. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA = 0x10 + // Position of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ENA. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20 + // Position of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ENA. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA = 0x40 + // Position of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ENA. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80 + // Position of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100 + // Bit TIME_OUT_INT_ENA. + I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100 + // Position of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9 + // Bit mask of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200 + // Bit TRANS_START_INT_ENA. + I2C_INT_ENA_TRANS_START_INT_ENA = 0x200 + // Position of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Pos = 0xa + // Bit mask of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Msk = 0x400 + // Bit NACK_INT_ENA. + I2C_INT_ENA_NACK_INT_ENA = 0x400 + // Position of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ENA. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA = 0x800 + // Position of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ENA. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA = 0x1000 + // Position of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_ST_TO_INT_ENA = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA = 0x4000 + // Position of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Pos = 0xf + // Bit mask of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Msk = 0x8000 + // Bit DET_START_INT_ENA. + I2C_INT_ENA_DET_START_INT_ENA = 0x8000 + // Position of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ENA. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA = 0x10000 + + // INT_STATUS: Status of captured I2C communication events + // Position of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Msk = 0x1 + // Bit RXFIFO_WM_INT_ST. + I2C_INT_STATUS_RXFIFO_WM_INT_ST = 0x1 + // Position of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Msk = 0x2 + // Bit TXFIFO_WM_INT_ST. + I2C_INT_STATUS_TXFIFO_WM_INT_ST = 0x2 + // Position of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ST. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4 + // Position of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3 + // Bit mask of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8 + // Bit END_DETECT_INT_ST. + I2C_INT_STATUS_END_DETECT_INT_ST = 0x8 + // Position of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ST. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST = 0x10 + // Position of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ST. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20 + // Position of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ST. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST = 0x40 + // Position of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ST. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80 + // Position of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100 + // Bit TIME_OUT_INT_ST. + I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100 + // Position of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9 + // Bit mask of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200 + // Bit TRANS_START_INT_ST. + I2C_INT_STATUS_TRANS_START_INT_ST = 0x200 + // Position of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Pos = 0xa + // Bit mask of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Msk = 0x400 + // Bit NACK_INT_ST. + I2C_INT_STATUS_NACK_INT_ST = 0x400 + // Position of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ST. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST = 0x800 + // Position of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ST. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST = 0x1000 + // Position of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_ST_TO_INT_ST = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST = 0x4000 + // Position of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Pos = 0xf + // Bit mask of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Msk = 0x8000 + // Bit DET_START_INT_ST. + I2C_INT_STATUS_DET_START_INT_ST = 0x8000 + // Position of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ST. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST = 0x10000 + + // SDA_HOLD: Configures the hold time after a negative SCL edge + // Position of TIME field. + I2C_SDA_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_HOLD_TIME_Msk = 0x3ff + + // SDA_SAMPLE: Configures the sample time after a positive SCL edge + // Position of TIME field. + I2C_SDA_SAMPLE_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_SAMPLE_TIME_Msk = 0x3ff + + // SCL_HIGH_PERIOD: Configures the high level width of the SCL clock + // Position of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x3fff + // Position of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Pos = 0xe + // Bit mask of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Msk = 0xfffc000 + + // SCL_START_HOLD: Configures the interval between pulling SDA low and pulling SCL low when the master generates a START condition + // Position of TIME field. + I2C_SCL_START_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_START_HOLD_TIME_Msk = 0x3ff + + // SCL_RSTART_SETUP: Configures the interval between the positive edge of SCL and the negative edge of SDA + // Position of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Msk = 0x3ff + + // SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_HOLD_TIME_Msk = 0x3fff + + // SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_SETUP_TIME_Msk = 0x3ff + + // SCL_FILTER_CFG: SCL filter configuration register + // Position of SCL_FILTER_THRES field. + I2C_SCL_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0 + // Bit mask of SCL_FILTER_THRES field. + I2C_SCL_FILTER_CFG_SCL_FILTER_THRES_Msk = 0xf + // Position of SCL_FILTER_EN field. + I2C_SCL_FILTER_CFG_SCL_FILTER_EN_Pos = 0x4 + // Bit mask of SCL_FILTER_EN field. + I2C_SCL_FILTER_CFG_SCL_FILTER_EN_Msk = 0x10 + // Bit SCL_FILTER_EN. + I2C_SCL_FILTER_CFG_SCL_FILTER_EN = 0x10 + + // SDA_FILTER_CFG: SDA filter configuration register + // Position of SDA_FILTER_THRES field. + I2C_SDA_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x0 + // Bit mask of SDA_FILTER_THRES field. + I2C_SDA_FILTER_CFG_SDA_FILTER_THRES_Msk = 0xf + // Position of SDA_FILTER_EN field. + I2C_SDA_FILTER_CFG_SDA_FILTER_EN_Pos = 0x4 + // Bit mask of SDA_FILTER_EN field. + I2C_SDA_FILTER_CFG_SDA_FILTER_EN_Msk = 0x10 + // Bit SDA_FILTER_EN. + I2C_SDA_FILTER_CFG_SDA_FILTER_EN = 0x10 + + // COMD0: I2C command register %s + // Position of COMMAND field. + I2C_COMD_COMMAND_Pos = 0x0 + // Bit mask of COMMAND field. + I2C_COMD_COMMAND_Msk = 0x3fff + // Position of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Pos = 0x1f + // Bit mask of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Msk = 0x80000000 + // Bit COMMAND_DONE. + I2C_COMD_COMMAND_DONE = 0x80000000 + + // SCL_ST_TIME_OUT: SCL status time out register + // Position of SCL_ST_TO field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_Pos = 0x0 + // Bit mask of SCL_ST_TO field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_Msk = 0xffffff + + // SCL_MAIN_ST_TIME_OUT: SCL main status time out register + // Position of SCL_MAIN_ST_TO field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_Pos = 0x0 + // Bit mask of SCL_MAIN_ST_TO field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_Msk = 0xffffff + + // SCL_SP_CONF: Power configuration register + // Position of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Pos = 0x0 + // Bit mask of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Msk = 0x1 + // Bit SCL_RST_SLV_EN. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN = 0x1 + // Position of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Pos = 0x1 + // Bit mask of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Msk = 0x3e + // Position of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Pos = 0x6 + // Bit mask of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Msk = 0x40 + // Bit SCL_PD_EN. + I2C_SCL_SP_CONF_SCL_PD_EN = 0x40 + // Position of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Pos = 0x7 + // Bit mask of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Msk = 0x80 + // Bit SDA_PD_EN. + I2C_SCL_SP_CONF_SDA_PD_EN = 0x80 + + // SCL_STRETCH_CONF: Set SCL stretch of I2C slave + // Position of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Pos = 0x0 + // Bit mask of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Msk = 0x3ff + // Position of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Pos = 0xa + // Bit mask of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Msk = 0x400 + // Bit SLAVE_SCL_STRETCH_EN. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN = 0x400 + // Position of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Pos = 0xb + // Bit mask of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Msk = 0x800 + // Bit SLAVE_SCL_STRETCH_CLR. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR = 0x800 + + // DATE: Version control register + // Position of DATE field. + I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2C_DATE_DATE_Msk = 0xffffffff +) + +// Constants for I2S0: I2S (Inter-IC Sound) Controller 0 +const ( + // CONF: I2S configuration register + // Position of TX_RESET field. + I2S_CONF_TX_RESET_Pos = 0x0 + // Bit mask of TX_RESET field. + I2S_CONF_TX_RESET_Msk = 0x1 + // Bit TX_RESET. + I2S_CONF_TX_RESET = 0x1 + // Position of RX_RESET field. + I2S_CONF_RX_RESET_Pos = 0x1 + // Bit mask of RX_RESET field. + I2S_CONF_RX_RESET_Msk = 0x2 + // Bit RX_RESET. + I2S_CONF_RX_RESET = 0x2 + // Position of TX_FIFO_RESET field. + I2S_CONF_TX_FIFO_RESET_Pos = 0x2 + // Bit mask of TX_FIFO_RESET field. + I2S_CONF_TX_FIFO_RESET_Msk = 0x4 + // Bit TX_FIFO_RESET. + I2S_CONF_TX_FIFO_RESET = 0x4 + // Position of RX_FIFO_RESET field. + I2S_CONF_RX_FIFO_RESET_Pos = 0x3 + // Bit mask of RX_FIFO_RESET field. + I2S_CONF_RX_FIFO_RESET_Msk = 0x8 + // Bit RX_FIFO_RESET. + I2S_CONF_RX_FIFO_RESET = 0x8 + // Position of TX_START field. + I2S_CONF_TX_START_Pos = 0x4 + // Bit mask of TX_START field. + I2S_CONF_TX_START_Msk = 0x10 + // Bit TX_START. + I2S_CONF_TX_START = 0x10 + // Position of RX_START field. + I2S_CONF_RX_START_Pos = 0x5 + // Bit mask of RX_START field. + I2S_CONF_RX_START_Msk = 0x20 + // Bit RX_START. + I2S_CONF_RX_START = 0x20 + // Position of TX_SLAVE_MOD field. + I2S_CONF_TX_SLAVE_MOD_Pos = 0x6 + // Bit mask of TX_SLAVE_MOD field. + I2S_CONF_TX_SLAVE_MOD_Msk = 0x40 + // Bit TX_SLAVE_MOD. + I2S_CONF_TX_SLAVE_MOD = 0x40 + // Position of RX_SLAVE_MOD field. + I2S_CONF_RX_SLAVE_MOD_Pos = 0x7 + // Bit mask of RX_SLAVE_MOD field. + I2S_CONF_RX_SLAVE_MOD_Msk = 0x80 + // Bit RX_SLAVE_MOD. + I2S_CONF_RX_SLAVE_MOD = 0x80 + // Position of TX_RIGHT_FIRST field. + I2S_CONF_TX_RIGHT_FIRST_Pos = 0x8 + // Bit mask of TX_RIGHT_FIRST field. + I2S_CONF_TX_RIGHT_FIRST_Msk = 0x100 + // Bit TX_RIGHT_FIRST. + I2S_CONF_TX_RIGHT_FIRST = 0x100 + // Position of RX_RIGHT_FIRST field. + I2S_CONF_RX_RIGHT_FIRST_Pos = 0x9 + // Bit mask of RX_RIGHT_FIRST field. + I2S_CONF_RX_RIGHT_FIRST_Msk = 0x200 + // Bit RX_RIGHT_FIRST. + I2S_CONF_RX_RIGHT_FIRST = 0x200 + // Position of TX_MSB_SHIFT field. + I2S_CONF_TX_MSB_SHIFT_Pos = 0xa + // Bit mask of TX_MSB_SHIFT field. + I2S_CONF_TX_MSB_SHIFT_Msk = 0x400 + // Bit TX_MSB_SHIFT. + I2S_CONF_TX_MSB_SHIFT = 0x400 + // Position of RX_MSB_SHIFT field. + I2S_CONF_RX_MSB_SHIFT_Pos = 0xb + // Bit mask of RX_MSB_SHIFT field. + I2S_CONF_RX_MSB_SHIFT_Msk = 0x800 + // Bit RX_MSB_SHIFT. + I2S_CONF_RX_MSB_SHIFT = 0x800 + // Position of TX_SHORT_SYNC field. + I2S_CONF_TX_SHORT_SYNC_Pos = 0xc + // Bit mask of TX_SHORT_SYNC field. + I2S_CONF_TX_SHORT_SYNC_Msk = 0x1000 + // Bit TX_SHORT_SYNC. + I2S_CONF_TX_SHORT_SYNC = 0x1000 + // Position of RX_SHORT_SYNC field. + I2S_CONF_RX_SHORT_SYNC_Pos = 0xd + // Bit mask of RX_SHORT_SYNC field. + I2S_CONF_RX_SHORT_SYNC_Msk = 0x2000 + // Bit RX_SHORT_SYNC. + I2S_CONF_RX_SHORT_SYNC = 0x2000 + // Position of TX_MONO field. + I2S_CONF_TX_MONO_Pos = 0xe + // Bit mask of TX_MONO field. + I2S_CONF_TX_MONO_Msk = 0x4000 + // Bit TX_MONO. + I2S_CONF_TX_MONO = 0x4000 + // Position of RX_MONO field. + I2S_CONF_RX_MONO_Pos = 0xf + // Bit mask of RX_MONO field. + I2S_CONF_RX_MONO_Msk = 0x8000 + // Bit RX_MONO. + I2S_CONF_RX_MONO = 0x8000 + // Position of TX_MSB_RIGHT field. + I2S_CONF_TX_MSB_RIGHT_Pos = 0x10 + // Bit mask of TX_MSB_RIGHT field. + I2S_CONF_TX_MSB_RIGHT_Msk = 0x10000 + // Bit TX_MSB_RIGHT. + I2S_CONF_TX_MSB_RIGHT = 0x10000 + // Position of RX_MSB_RIGHT field. + I2S_CONF_RX_MSB_RIGHT_Pos = 0x11 + // Bit mask of RX_MSB_RIGHT field. + I2S_CONF_RX_MSB_RIGHT_Msk = 0x20000 + // Bit RX_MSB_RIGHT. + I2S_CONF_RX_MSB_RIGHT = 0x20000 + // Position of TX_LSB_FIRST_DMA field. + I2S_CONF_TX_LSB_FIRST_DMA_Pos = 0x12 + // Bit mask of TX_LSB_FIRST_DMA field. + I2S_CONF_TX_LSB_FIRST_DMA_Msk = 0x40000 + // Bit TX_LSB_FIRST_DMA. + I2S_CONF_TX_LSB_FIRST_DMA = 0x40000 + // Position of RX_LSB_FIRST_DMA field. + I2S_CONF_RX_LSB_FIRST_DMA_Pos = 0x13 + // Bit mask of RX_LSB_FIRST_DMA field. + I2S_CONF_RX_LSB_FIRST_DMA_Msk = 0x80000 + // Bit RX_LSB_FIRST_DMA. + I2S_CONF_RX_LSB_FIRST_DMA = 0x80000 + // Position of SIG_LOOPBACK field. + I2S_CONF_SIG_LOOPBACK_Pos = 0x14 + // Bit mask of SIG_LOOPBACK field. + I2S_CONF_SIG_LOOPBACK_Msk = 0x100000 + // Bit SIG_LOOPBACK. + I2S_CONF_SIG_LOOPBACK = 0x100000 + // Position of TX_FIFO_RESET_ST field. + I2S_CONF_TX_FIFO_RESET_ST_Pos = 0x15 + // Bit mask of TX_FIFO_RESET_ST field. + I2S_CONF_TX_FIFO_RESET_ST_Msk = 0x200000 + // Bit TX_FIFO_RESET_ST. + I2S_CONF_TX_FIFO_RESET_ST = 0x200000 + // Position of RX_FIFO_RESET_ST field. + I2S_CONF_RX_FIFO_RESET_ST_Pos = 0x16 + // Bit mask of RX_FIFO_RESET_ST field. + I2S_CONF_RX_FIFO_RESET_ST_Msk = 0x400000 + // Bit RX_FIFO_RESET_ST. + I2S_CONF_RX_FIFO_RESET_ST = 0x400000 + // Position of TX_RESET_ST field. + I2S_CONF_TX_RESET_ST_Pos = 0x17 + // Bit mask of TX_RESET_ST field. + I2S_CONF_TX_RESET_ST_Msk = 0x800000 + // Bit TX_RESET_ST. + I2S_CONF_TX_RESET_ST = 0x800000 + // Position of TX_DMA_EQUAL field. + I2S_CONF_TX_DMA_EQUAL_Pos = 0x18 + // Bit mask of TX_DMA_EQUAL field. + I2S_CONF_TX_DMA_EQUAL_Msk = 0x1000000 + // Bit TX_DMA_EQUAL. + I2S_CONF_TX_DMA_EQUAL = 0x1000000 + // Position of RX_DMA_EQUAL field. + I2S_CONF_RX_DMA_EQUAL_Pos = 0x19 + // Bit mask of RX_DMA_EQUAL field. + I2S_CONF_RX_DMA_EQUAL_Msk = 0x2000000 + // Bit RX_DMA_EQUAL. + I2S_CONF_RX_DMA_EQUAL = 0x2000000 + // Position of PRE_REQ_EN field. + I2S_CONF_PRE_REQ_EN_Pos = 0x1a + // Bit mask of PRE_REQ_EN field. + I2S_CONF_PRE_REQ_EN_Msk = 0x4000000 + // Bit PRE_REQ_EN. + I2S_CONF_PRE_REQ_EN = 0x4000000 + // Position of TX_BIG_ENDIAN field. + I2S_CONF_TX_BIG_ENDIAN_Pos = 0x1b + // Bit mask of TX_BIG_ENDIAN field. + I2S_CONF_TX_BIG_ENDIAN_Msk = 0x8000000 + // Bit TX_BIG_ENDIAN. + I2S_CONF_TX_BIG_ENDIAN = 0x8000000 + // Position of RX_BIG_ENDIAN field. + I2S_CONF_RX_BIG_ENDIAN_Pos = 0x1c + // Bit mask of RX_BIG_ENDIAN field. + I2S_CONF_RX_BIG_ENDIAN_Msk = 0x10000000 + // Bit RX_BIG_ENDIAN. + I2S_CONF_RX_BIG_ENDIAN = 0x10000000 + // Position of RX_RESET_ST field. + I2S_CONF_RX_RESET_ST_Pos = 0x1d + // Bit mask of RX_RESET_ST field. + I2S_CONF_RX_RESET_ST_Msk = 0x20000000 + // Bit RX_RESET_ST. + I2S_CONF_RX_RESET_ST = 0x20000000 + + // INT_RAW: Raw interrupt status + // Position of RX_TAKE_DATA_INT_RAW field. + I2S_INT_RAW_RX_TAKE_DATA_INT_RAW_Pos = 0x0 + // Bit mask of RX_TAKE_DATA_INT_RAW field. + I2S_INT_RAW_RX_TAKE_DATA_INT_RAW_Msk = 0x1 + // Bit RX_TAKE_DATA_INT_RAW. + I2S_INT_RAW_RX_TAKE_DATA_INT_RAW = 0x1 + // Position of TX_PUT_DATA_INT_RAW field. + I2S_INT_RAW_TX_PUT_DATA_INT_RAW_Pos = 0x1 + // Bit mask of TX_PUT_DATA_INT_RAW field. + I2S_INT_RAW_TX_PUT_DATA_INT_RAW_Msk = 0x2 + // Bit TX_PUT_DATA_INT_RAW. + I2S_INT_RAW_TX_PUT_DATA_INT_RAW = 0x2 + // Position of RX_WFULL_INT_RAW field. + I2S_INT_RAW_RX_WFULL_INT_RAW_Pos = 0x2 + // Bit mask of RX_WFULL_INT_RAW field. + I2S_INT_RAW_RX_WFULL_INT_RAW_Msk = 0x4 + // Bit RX_WFULL_INT_RAW. + I2S_INT_RAW_RX_WFULL_INT_RAW = 0x4 + // Position of RX_REMPTY_INT_RAW field. + I2S_INT_RAW_RX_REMPTY_INT_RAW_Pos = 0x3 + // Bit mask of RX_REMPTY_INT_RAW field. + I2S_INT_RAW_RX_REMPTY_INT_RAW_Msk = 0x8 + // Bit RX_REMPTY_INT_RAW. + I2S_INT_RAW_RX_REMPTY_INT_RAW = 0x8 + // Position of TX_WFULL_INT_RAW field. + I2S_INT_RAW_TX_WFULL_INT_RAW_Pos = 0x4 + // Bit mask of TX_WFULL_INT_RAW field. + I2S_INT_RAW_TX_WFULL_INT_RAW_Msk = 0x10 + // Bit TX_WFULL_INT_RAW. + I2S_INT_RAW_TX_WFULL_INT_RAW = 0x10 + // Position of TX_REMPTY_INT_RAW field. + I2S_INT_RAW_TX_REMPTY_INT_RAW_Pos = 0x5 + // Bit mask of TX_REMPTY_INT_RAW field. + I2S_INT_RAW_TX_REMPTY_INT_RAW_Msk = 0x20 + // Bit TX_REMPTY_INT_RAW. + I2S_INT_RAW_TX_REMPTY_INT_RAW = 0x20 + // Position of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x6 + // Bit mask of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x40 + // Bit RX_HUNG_INT_RAW. + I2S_INT_RAW_RX_HUNG_INT_RAW = 0x40 + // Position of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x7 + // Bit mask of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x80 + // Bit TX_HUNG_INT_RAW. + I2S_INT_RAW_TX_HUNG_INT_RAW = 0x80 + // Position of IN_DONE_INT_RAW field. + I2S_INT_RAW_IN_DONE_INT_RAW_Pos = 0x8 + // Bit mask of IN_DONE_INT_RAW field. + I2S_INT_RAW_IN_DONE_INT_RAW_Msk = 0x100 + // Bit IN_DONE_INT_RAW. + I2S_INT_RAW_IN_DONE_INT_RAW = 0x100 + // Position of IN_SUC_EOF_INT_RAW field. + I2S_INT_RAW_IN_SUC_EOF_INT_RAW_Pos = 0x9 + // Bit mask of IN_SUC_EOF_INT_RAW field. + I2S_INT_RAW_IN_SUC_EOF_INT_RAW_Msk = 0x200 + // Bit IN_SUC_EOF_INT_RAW. + I2S_INT_RAW_IN_SUC_EOF_INT_RAW = 0x200 + // Position of IN_ERR_EOF_INT_RAW field. + I2S_INT_RAW_IN_ERR_EOF_INT_RAW_Pos = 0xa + // Bit mask of IN_ERR_EOF_INT_RAW field. + I2S_INT_RAW_IN_ERR_EOF_INT_RAW_Msk = 0x400 + // Bit IN_ERR_EOF_INT_RAW. + I2S_INT_RAW_IN_ERR_EOF_INT_RAW = 0x400 + // Position of OUT_DONE_INT_RAW field. + I2S_INT_RAW_OUT_DONE_INT_RAW_Pos = 0xb + // Bit mask of OUT_DONE_INT_RAW field. + I2S_INT_RAW_OUT_DONE_INT_RAW_Msk = 0x800 + // Bit OUT_DONE_INT_RAW. + I2S_INT_RAW_OUT_DONE_INT_RAW = 0x800 + // Position of OUT_EOF_INT_RAW field. + I2S_INT_RAW_OUT_EOF_INT_RAW_Pos = 0xc + // Bit mask of OUT_EOF_INT_RAW field. + I2S_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x1000 + // Bit OUT_EOF_INT_RAW. + I2S_INT_RAW_OUT_EOF_INT_RAW = 0x1000 + // Position of IN_DSCR_ERR_INT_RAW field. + I2S_INT_RAW_IN_DSCR_ERR_INT_RAW_Pos = 0xd + // Bit mask of IN_DSCR_ERR_INT_RAW field. + I2S_INT_RAW_IN_DSCR_ERR_INT_RAW_Msk = 0x2000 + // Bit IN_DSCR_ERR_INT_RAW. + I2S_INT_RAW_IN_DSCR_ERR_INT_RAW = 0x2000 + // Position of OUT_DSCR_ERR_INT_RAW field. + I2S_INT_RAW_OUT_DSCR_ERR_INT_RAW_Pos = 0xe + // Bit mask of OUT_DSCR_ERR_INT_RAW field. + I2S_INT_RAW_OUT_DSCR_ERR_INT_RAW_Msk = 0x4000 + // Bit OUT_DSCR_ERR_INT_RAW. + I2S_INT_RAW_OUT_DSCR_ERR_INT_RAW = 0x4000 + // Position of IN_DSCR_EMPTY_INT_RAW field. + I2S_INT_RAW_IN_DSCR_EMPTY_INT_RAW_Pos = 0xf + // Bit mask of IN_DSCR_EMPTY_INT_RAW field. + I2S_INT_RAW_IN_DSCR_EMPTY_INT_RAW_Msk = 0x8000 + // Bit IN_DSCR_EMPTY_INT_RAW. + I2S_INT_RAW_IN_DSCR_EMPTY_INT_RAW = 0x8000 + // Position of OUT_TOTAL_EOF_INT_RAW field. + I2S_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Pos = 0x10 + // Bit mask of OUT_TOTAL_EOF_INT_RAW field. + I2S_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Msk = 0x10000 + // Bit OUT_TOTAL_EOF_INT_RAW. + I2S_INT_RAW_OUT_TOTAL_EOF_INT_RAW = 0x10000 + // Position of V_SYNC_INT_RAW field. + I2S_INT_RAW_V_SYNC_INT_RAW_Pos = 0x11 + // Bit mask of V_SYNC_INT_RAW field. + I2S_INT_RAW_V_SYNC_INT_RAW_Msk = 0x20000 + // Bit V_SYNC_INT_RAW. + I2S_INT_RAW_V_SYNC_INT_RAW = 0x20000 + + // INT_ST: Masked interrupt status + // Position of RX_TAKE_DATA_INT_ST field. + I2S_INT_ST_RX_TAKE_DATA_INT_ST_Pos = 0x0 + // Bit mask of RX_TAKE_DATA_INT_ST field. + I2S_INT_ST_RX_TAKE_DATA_INT_ST_Msk = 0x1 + // Bit RX_TAKE_DATA_INT_ST. + I2S_INT_ST_RX_TAKE_DATA_INT_ST = 0x1 + // Position of TX_PUT_DATA_INT_ST field. + I2S_INT_ST_TX_PUT_DATA_INT_ST_Pos = 0x1 + // Bit mask of TX_PUT_DATA_INT_ST field. + I2S_INT_ST_TX_PUT_DATA_INT_ST_Msk = 0x2 + // Bit TX_PUT_DATA_INT_ST. + I2S_INT_ST_TX_PUT_DATA_INT_ST = 0x2 + // Position of RX_WFULL_INT_ST field. + I2S_INT_ST_RX_WFULL_INT_ST_Pos = 0x2 + // Bit mask of RX_WFULL_INT_ST field. + I2S_INT_ST_RX_WFULL_INT_ST_Msk = 0x4 + // Bit RX_WFULL_INT_ST. + I2S_INT_ST_RX_WFULL_INT_ST = 0x4 + // Position of RX_REMPTY_INT_ST field. + I2S_INT_ST_RX_REMPTY_INT_ST_Pos = 0x3 + // Bit mask of RX_REMPTY_INT_ST field. + I2S_INT_ST_RX_REMPTY_INT_ST_Msk = 0x8 + // Bit RX_REMPTY_INT_ST. + I2S_INT_ST_RX_REMPTY_INT_ST = 0x8 + // Position of TX_WFULL_INT_ST field. + I2S_INT_ST_TX_WFULL_INT_ST_Pos = 0x4 + // Bit mask of TX_WFULL_INT_ST field. + I2S_INT_ST_TX_WFULL_INT_ST_Msk = 0x10 + // Bit TX_WFULL_INT_ST. + I2S_INT_ST_TX_WFULL_INT_ST = 0x10 + // Position of TX_REMPTY_INT_ST field. + I2S_INT_ST_TX_REMPTY_INT_ST_Pos = 0x5 + // Bit mask of TX_REMPTY_INT_ST field. + I2S_INT_ST_TX_REMPTY_INT_ST_Msk = 0x20 + // Bit TX_REMPTY_INT_ST. + I2S_INT_ST_TX_REMPTY_INT_ST = 0x20 + // Position of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Pos = 0x6 + // Bit mask of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Msk = 0x40 + // Bit RX_HUNG_INT_ST. + I2S_INT_ST_RX_HUNG_INT_ST = 0x40 + // Position of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Pos = 0x7 + // Bit mask of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Msk = 0x80 + // Bit TX_HUNG_INT_ST. + I2S_INT_ST_TX_HUNG_INT_ST = 0x80 + // Position of IN_DONE_INT_ST field. + I2S_INT_ST_IN_DONE_INT_ST_Pos = 0x8 + // Bit mask of IN_DONE_INT_ST field. + I2S_INT_ST_IN_DONE_INT_ST_Msk = 0x100 + // Bit IN_DONE_INT_ST. + I2S_INT_ST_IN_DONE_INT_ST = 0x100 + // Position of IN_SUC_EOF_INT_ST field. + I2S_INT_ST_IN_SUC_EOF_INT_ST_Pos = 0x9 + // Bit mask of IN_SUC_EOF_INT_ST field. + I2S_INT_ST_IN_SUC_EOF_INT_ST_Msk = 0x200 + // Bit IN_SUC_EOF_INT_ST. + I2S_INT_ST_IN_SUC_EOF_INT_ST = 0x200 + // Position of IN_ERR_EOF_INT_ST field. + I2S_INT_ST_IN_ERR_EOF_INT_ST_Pos = 0xa + // Bit mask of IN_ERR_EOF_INT_ST field. + I2S_INT_ST_IN_ERR_EOF_INT_ST_Msk = 0x400 + // Bit IN_ERR_EOF_INT_ST. + I2S_INT_ST_IN_ERR_EOF_INT_ST = 0x400 + // Position of OUT_DONE_INT_ST field. + I2S_INT_ST_OUT_DONE_INT_ST_Pos = 0xb + // Bit mask of OUT_DONE_INT_ST field. + I2S_INT_ST_OUT_DONE_INT_ST_Msk = 0x800 + // Bit OUT_DONE_INT_ST. + I2S_INT_ST_OUT_DONE_INT_ST = 0x800 + // Position of OUT_EOF_INT_ST field. + I2S_INT_ST_OUT_EOF_INT_ST_Pos = 0xc + // Bit mask of OUT_EOF_INT_ST field. + I2S_INT_ST_OUT_EOF_INT_ST_Msk = 0x1000 + // Bit OUT_EOF_INT_ST. + I2S_INT_ST_OUT_EOF_INT_ST = 0x1000 + // Position of IN_DSCR_ERR_INT_ST field. + I2S_INT_ST_IN_DSCR_ERR_INT_ST_Pos = 0xd + // Bit mask of IN_DSCR_ERR_INT_ST field. + I2S_INT_ST_IN_DSCR_ERR_INT_ST_Msk = 0x2000 + // Bit IN_DSCR_ERR_INT_ST. + I2S_INT_ST_IN_DSCR_ERR_INT_ST = 0x2000 + // Position of OUT_DSCR_ERR_INT_ST field. + I2S_INT_ST_OUT_DSCR_ERR_INT_ST_Pos = 0xe + // Bit mask of OUT_DSCR_ERR_INT_ST field. + I2S_INT_ST_OUT_DSCR_ERR_INT_ST_Msk = 0x4000 + // Bit OUT_DSCR_ERR_INT_ST. + I2S_INT_ST_OUT_DSCR_ERR_INT_ST = 0x4000 + // Position of IN_DSCR_EMPTY_INT_ST field. + I2S_INT_ST_IN_DSCR_EMPTY_INT_ST_Pos = 0xf + // Bit mask of IN_DSCR_EMPTY_INT_ST field. + I2S_INT_ST_IN_DSCR_EMPTY_INT_ST_Msk = 0x8000 + // Bit IN_DSCR_EMPTY_INT_ST. + I2S_INT_ST_IN_DSCR_EMPTY_INT_ST = 0x8000 + // Position of OUT_TOTAL_EOF_INT_ST field. + I2S_INT_ST_OUT_TOTAL_EOF_INT_ST_Pos = 0x10 + // Bit mask of OUT_TOTAL_EOF_INT_ST field. + I2S_INT_ST_OUT_TOTAL_EOF_INT_ST_Msk = 0x10000 + // Bit OUT_TOTAL_EOF_INT_ST. + I2S_INT_ST_OUT_TOTAL_EOF_INT_ST = 0x10000 + // Position of V_SYNC_INT_ST field. + I2S_INT_ST_V_SYNC_INT_ST_Pos = 0x11 + // Bit mask of V_SYNC_INT_ST field. + I2S_INT_ST_V_SYNC_INT_ST_Msk = 0x20000 + // Bit V_SYNC_INT_ST. + I2S_INT_ST_V_SYNC_INT_ST = 0x20000 + + // INT_ENA: Interrupt enable bits + // Position of RX_TAKE_DATA_INT_ENA field. + I2S_INT_ENA_RX_TAKE_DATA_INT_ENA_Pos = 0x0 + // Bit mask of RX_TAKE_DATA_INT_ENA field. + I2S_INT_ENA_RX_TAKE_DATA_INT_ENA_Msk = 0x1 + // Bit RX_TAKE_DATA_INT_ENA. + I2S_INT_ENA_RX_TAKE_DATA_INT_ENA = 0x1 + // Position of TX_PUT_DATA_INT_ENA field. + I2S_INT_ENA_TX_PUT_DATA_INT_ENA_Pos = 0x1 + // Bit mask of TX_PUT_DATA_INT_ENA field. + I2S_INT_ENA_TX_PUT_DATA_INT_ENA_Msk = 0x2 + // Bit TX_PUT_DATA_INT_ENA. + I2S_INT_ENA_TX_PUT_DATA_INT_ENA = 0x2 + // Position of RX_WFULL_INT_ENA field. + I2S_INT_ENA_RX_WFULL_INT_ENA_Pos = 0x2 + // Bit mask of RX_WFULL_INT_ENA field. + I2S_INT_ENA_RX_WFULL_INT_ENA_Msk = 0x4 + // Bit RX_WFULL_INT_ENA. + I2S_INT_ENA_RX_WFULL_INT_ENA = 0x4 + // Position of RX_REMPTY_INT_ENA field. + I2S_INT_ENA_RX_REMPTY_INT_ENA_Pos = 0x3 + // Bit mask of RX_REMPTY_INT_ENA field. + I2S_INT_ENA_RX_REMPTY_INT_ENA_Msk = 0x8 + // Bit RX_REMPTY_INT_ENA. + I2S_INT_ENA_RX_REMPTY_INT_ENA = 0x8 + // Position of TX_WFULL_INT_ENA field. + I2S_INT_ENA_TX_WFULL_INT_ENA_Pos = 0x4 + // Bit mask of TX_WFULL_INT_ENA field. + I2S_INT_ENA_TX_WFULL_INT_ENA_Msk = 0x10 + // Bit TX_WFULL_INT_ENA. + I2S_INT_ENA_TX_WFULL_INT_ENA = 0x10 + // Position of TX_REMPTY_INT_ENA field. + I2S_INT_ENA_TX_REMPTY_INT_ENA_Pos = 0x5 + // Bit mask of TX_REMPTY_INT_ENA field. + I2S_INT_ENA_TX_REMPTY_INT_ENA_Msk = 0x20 + // Bit TX_REMPTY_INT_ENA. + I2S_INT_ENA_TX_REMPTY_INT_ENA = 0x20 + // Position of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x6 + // Bit mask of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x40 + // Bit RX_HUNG_INT_ENA. + I2S_INT_ENA_RX_HUNG_INT_ENA = 0x40 + // Position of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x7 + // Bit mask of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x80 + // Bit TX_HUNG_INT_ENA. + I2S_INT_ENA_TX_HUNG_INT_ENA = 0x80 + // Position of IN_DONE_INT_ENA field. + I2S_INT_ENA_IN_DONE_INT_ENA_Pos = 0x8 + // Bit mask of IN_DONE_INT_ENA field. + I2S_INT_ENA_IN_DONE_INT_ENA_Msk = 0x100 + // Bit IN_DONE_INT_ENA. + I2S_INT_ENA_IN_DONE_INT_ENA = 0x100 + // Position of IN_SUC_EOF_INT_ENA field. + I2S_INT_ENA_IN_SUC_EOF_INT_ENA_Pos = 0x9 + // Bit mask of IN_SUC_EOF_INT_ENA field. + I2S_INT_ENA_IN_SUC_EOF_INT_ENA_Msk = 0x200 + // Bit IN_SUC_EOF_INT_ENA. + I2S_INT_ENA_IN_SUC_EOF_INT_ENA = 0x200 + // Position of IN_ERR_EOF_INT_ENA field. + I2S_INT_ENA_IN_ERR_EOF_INT_ENA_Pos = 0xa + // Bit mask of IN_ERR_EOF_INT_ENA field. + I2S_INT_ENA_IN_ERR_EOF_INT_ENA_Msk = 0x400 + // Bit IN_ERR_EOF_INT_ENA. + I2S_INT_ENA_IN_ERR_EOF_INT_ENA = 0x400 + // Position of OUT_DONE_INT_ENA field. + I2S_INT_ENA_OUT_DONE_INT_ENA_Pos = 0xb + // Bit mask of OUT_DONE_INT_ENA field. + I2S_INT_ENA_OUT_DONE_INT_ENA_Msk = 0x800 + // Bit OUT_DONE_INT_ENA. + I2S_INT_ENA_OUT_DONE_INT_ENA = 0x800 + // Position of OUT_EOF_INT_ENA field. + I2S_INT_ENA_OUT_EOF_INT_ENA_Pos = 0xc + // Bit mask of OUT_EOF_INT_ENA field. + I2S_INT_ENA_OUT_EOF_INT_ENA_Msk = 0x1000 + // Bit OUT_EOF_INT_ENA. + I2S_INT_ENA_OUT_EOF_INT_ENA = 0x1000 + // Position of IN_DSCR_ERR_INT_ENA field. + I2S_INT_ENA_IN_DSCR_ERR_INT_ENA_Pos = 0xd + // Bit mask of IN_DSCR_ERR_INT_ENA field. + I2S_INT_ENA_IN_DSCR_ERR_INT_ENA_Msk = 0x2000 + // Bit IN_DSCR_ERR_INT_ENA. + I2S_INT_ENA_IN_DSCR_ERR_INT_ENA = 0x2000 + // Position of OUT_DSCR_ERR_INT_ENA field. + I2S_INT_ENA_OUT_DSCR_ERR_INT_ENA_Pos = 0xe + // Bit mask of OUT_DSCR_ERR_INT_ENA field. + I2S_INT_ENA_OUT_DSCR_ERR_INT_ENA_Msk = 0x4000 + // Bit OUT_DSCR_ERR_INT_ENA. + I2S_INT_ENA_OUT_DSCR_ERR_INT_ENA = 0x4000 + // Position of IN_DSCR_EMPTY_INT_ENA field. + I2S_INT_ENA_IN_DSCR_EMPTY_INT_ENA_Pos = 0xf + // Bit mask of IN_DSCR_EMPTY_INT_ENA field. + I2S_INT_ENA_IN_DSCR_EMPTY_INT_ENA_Msk = 0x8000 + // Bit IN_DSCR_EMPTY_INT_ENA. + I2S_INT_ENA_IN_DSCR_EMPTY_INT_ENA = 0x8000 + // Position of OUT_TOTAL_EOF_INT_ENA field. + I2S_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Pos = 0x10 + // Bit mask of OUT_TOTAL_EOF_INT_ENA field. + I2S_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Msk = 0x10000 + // Bit OUT_TOTAL_EOF_INT_ENA. + I2S_INT_ENA_OUT_TOTAL_EOF_INT_ENA = 0x10000 + // Position of V_SYNC_INT_ENA field. + I2S_INT_ENA_V_SYNC_INT_ENA_Pos = 0x11 + // Bit mask of V_SYNC_INT_ENA field. + I2S_INT_ENA_V_SYNC_INT_ENA_Msk = 0x20000 + // Bit V_SYNC_INT_ENA. + I2S_INT_ENA_V_SYNC_INT_ENA = 0x20000 + + // INT_CLR: Interrupt clear bits + // Position of TAKE_DATA_INT_CLR field. + I2S_INT_CLR_TAKE_DATA_INT_CLR_Pos = 0x0 + // Bit mask of TAKE_DATA_INT_CLR field. + I2S_INT_CLR_TAKE_DATA_INT_CLR_Msk = 0x1 + // Bit TAKE_DATA_INT_CLR. + I2S_INT_CLR_TAKE_DATA_INT_CLR = 0x1 + // Position of PUT_DATA_INT_CLR field. + I2S_INT_CLR_PUT_DATA_INT_CLR_Pos = 0x1 + // Bit mask of PUT_DATA_INT_CLR field. + I2S_INT_CLR_PUT_DATA_INT_CLR_Msk = 0x2 + // Bit PUT_DATA_INT_CLR. + I2S_INT_CLR_PUT_DATA_INT_CLR = 0x2 + // Position of RX_WFULL_INT_CLR field. + I2S_INT_CLR_RX_WFULL_INT_CLR_Pos = 0x2 + // Bit mask of RX_WFULL_INT_CLR field. + I2S_INT_CLR_RX_WFULL_INT_CLR_Msk = 0x4 + // Bit RX_WFULL_INT_CLR. + I2S_INT_CLR_RX_WFULL_INT_CLR = 0x4 + // Position of RX_REMPTY_INT_CLR field. + I2S_INT_CLR_RX_REMPTY_INT_CLR_Pos = 0x3 + // Bit mask of RX_REMPTY_INT_CLR field. + I2S_INT_CLR_RX_REMPTY_INT_CLR_Msk = 0x8 + // Bit RX_REMPTY_INT_CLR. + I2S_INT_CLR_RX_REMPTY_INT_CLR = 0x8 + // Position of TX_WFULL_INT_CLR field. + I2S_INT_CLR_TX_WFULL_INT_CLR_Pos = 0x4 + // Bit mask of TX_WFULL_INT_CLR field. + I2S_INT_CLR_TX_WFULL_INT_CLR_Msk = 0x10 + // Bit TX_WFULL_INT_CLR. + I2S_INT_CLR_TX_WFULL_INT_CLR = 0x10 + // Position of TX_REMPTY_INT_CLR field. + I2S_INT_CLR_TX_REMPTY_INT_CLR_Pos = 0x5 + // Bit mask of TX_REMPTY_INT_CLR field. + I2S_INT_CLR_TX_REMPTY_INT_CLR_Msk = 0x20 + // Bit TX_REMPTY_INT_CLR. + I2S_INT_CLR_TX_REMPTY_INT_CLR = 0x20 + // Position of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x6 + // Bit mask of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x40 + // Bit RX_HUNG_INT_CLR. + I2S_INT_CLR_RX_HUNG_INT_CLR = 0x40 + // Position of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x7 + // Bit mask of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x80 + // Bit TX_HUNG_INT_CLR. + I2S_INT_CLR_TX_HUNG_INT_CLR = 0x80 + // Position of IN_DONE_INT_CLR field. + I2S_INT_CLR_IN_DONE_INT_CLR_Pos = 0x8 + // Bit mask of IN_DONE_INT_CLR field. + I2S_INT_CLR_IN_DONE_INT_CLR_Msk = 0x100 + // Bit IN_DONE_INT_CLR. + I2S_INT_CLR_IN_DONE_INT_CLR = 0x100 + // Position of IN_SUC_EOF_INT_CLR field. + I2S_INT_CLR_IN_SUC_EOF_INT_CLR_Pos = 0x9 + // Bit mask of IN_SUC_EOF_INT_CLR field. + I2S_INT_CLR_IN_SUC_EOF_INT_CLR_Msk = 0x200 + // Bit IN_SUC_EOF_INT_CLR. + I2S_INT_CLR_IN_SUC_EOF_INT_CLR = 0x200 + // Position of IN_ERR_EOF_INT_CLR field. + I2S_INT_CLR_IN_ERR_EOF_INT_CLR_Pos = 0xa + // Bit mask of IN_ERR_EOF_INT_CLR field. + I2S_INT_CLR_IN_ERR_EOF_INT_CLR_Msk = 0x400 + // Bit IN_ERR_EOF_INT_CLR. + I2S_INT_CLR_IN_ERR_EOF_INT_CLR = 0x400 + // Position of OUT_DONE_INT_CLR field. + I2S_INT_CLR_OUT_DONE_INT_CLR_Pos = 0xb + // Bit mask of OUT_DONE_INT_CLR field. + I2S_INT_CLR_OUT_DONE_INT_CLR_Msk = 0x800 + // Bit OUT_DONE_INT_CLR. + I2S_INT_CLR_OUT_DONE_INT_CLR = 0x800 + // Position of OUT_EOF_INT_CLR field. + I2S_INT_CLR_OUT_EOF_INT_CLR_Pos = 0xc + // Bit mask of OUT_EOF_INT_CLR field. + I2S_INT_CLR_OUT_EOF_INT_CLR_Msk = 0x1000 + // Bit OUT_EOF_INT_CLR. + I2S_INT_CLR_OUT_EOF_INT_CLR = 0x1000 + // Position of IN_DSCR_ERR_INT_CLR field. + I2S_INT_CLR_IN_DSCR_ERR_INT_CLR_Pos = 0xd + // Bit mask of IN_DSCR_ERR_INT_CLR field. + I2S_INT_CLR_IN_DSCR_ERR_INT_CLR_Msk = 0x2000 + // Bit IN_DSCR_ERR_INT_CLR. + I2S_INT_CLR_IN_DSCR_ERR_INT_CLR = 0x2000 + // Position of OUT_DSCR_ERR_INT_CLR field. + I2S_INT_CLR_OUT_DSCR_ERR_INT_CLR_Pos = 0xe + // Bit mask of OUT_DSCR_ERR_INT_CLR field. + I2S_INT_CLR_OUT_DSCR_ERR_INT_CLR_Msk = 0x4000 + // Bit OUT_DSCR_ERR_INT_CLR. + I2S_INT_CLR_OUT_DSCR_ERR_INT_CLR = 0x4000 + // Position of IN_DSCR_EMPTY_INT_CLR field. + I2S_INT_CLR_IN_DSCR_EMPTY_INT_CLR_Pos = 0xf + // Bit mask of IN_DSCR_EMPTY_INT_CLR field. + I2S_INT_CLR_IN_DSCR_EMPTY_INT_CLR_Msk = 0x8000 + // Bit IN_DSCR_EMPTY_INT_CLR. + I2S_INT_CLR_IN_DSCR_EMPTY_INT_CLR = 0x8000 + // Position of OUT_TOTAL_EOF_INT_CLR field. + I2S_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Pos = 0x10 + // Bit mask of OUT_TOTAL_EOF_INT_CLR field. + I2S_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Msk = 0x10000 + // Bit OUT_TOTAL_EOF_INT_CLR. + I2S_INT_CLR_OUT_TOTAL_EOF_INT_CLR = 0x10000 + // Position of V_SYNC_INT_CLR field. + I2S_INT_CLR_V_SYNC_INT_CLR_Pos = 0x11 + // Bit mask of V_SYNC_INT_CLR field. + I2S_INT_CLR_V_SYNC_INT_CLR_Msk = 0x20000 + // Bit V_SYNC_INT_CLR. + I2S_INT_CLR_V_SYNC_INT_CLR = 0x20000 + + // TIMING: I2S timing register + // Position of TX_BCK_IN_DELAY field. + I2S_TIMING_TX_BCK_IN_DELAY_Pos = 0x0 + // Bit mask of TX_BCK_IN_DELAY field. + I2S_TIMING_TX_BCK_IN_DELAY_Msk = 0x3 + // Position of TX_WS_IN_DELAY field. + I2S_TIMING_TX_WS_IN_DELAY_Pos = 0x2 + // Bit mask of TX_WS_IN_DELAY field. + I2S_TIMING_TX_WS_IN_DELAY_Msk = 0xc + // Position of RX_BCK_IN_DELAY field. + I2S_TIMING_RX_BCK_IN_DELAY_Pos = 0x4 + // Bit mask of RX_BCK_IN_DELAY field. + I2S_TIMING_RX_BCK_IN_DELAY_Msk = 0x30 + // Position of RX_WS_IN_DELAY field. + I2S_TIMING_RX_WS_IN_DELAY_Pos = 0x6 + // Bit mask of RX_WS_IN_DELAY field. + I2S_TIMING_RX_WS_IN_DELAY_Msk = 0xc0 + // Position of RX_SD_IN_DELAY field. + I2S_TIMING_RX_SD_IN_DELAY_Pos = 0x8 + // Bit mask of RX_SD_IN_DELAY field. + I2S_TIMING_RX_SD_IN_DELAY_Msk = 0x300 + // Position of TX_BCK_OUT_DELAY field. + I2S_TIMING_TX_BCK_OUT_DELAY_Pos = 0xa + // Bit mask of TX_BCK_OUT_DELAY field. + I2S_TIMING_TX_BCK_OUT_DELAY_Msk = 0xc00 + // Position of TX_WS_OUT_DELAY field. + I2S_TIMING_TX_WS_OUT_DELAY_Pos = 0xc + // Bit mask of TX_WS_OUT_DELAY field. + I2S_TIMING_TX_WS_OUT_DELAY_Msk = 0x3000 + // Position of TX_SD_OUT_DELAY field. + I2S_TIMING_TX_SD_OUT_DELAY_Pos = 0xe + // Bit mask of TX_SD_OUT_DELAY field. + I2S_TIMING_TX_SD_OUT_DELAY_Msk = 0xc000 + // Position of RX_WS_OUT_DELAY field. + I2S_TIMING_RX_WS_OUT_DELAY_Pos = 0x10 + // Bit mask of RX_WS_OUT_DELAY field. + I2S_TIMING_RX_WS_OUT_DELAY_Msk = 0x30000 + // Position of RX_BCK_OUT_DELAY field. + I2S_TIMING_RX_BCK_OUT_DELAY_Pos = 0x12 + // Bit mask of RX_BCK_OUT_DELAY field. + I2S_TIMING_RX_BCK_OUT_DELAY_Msk = 0xc0000 + // Position of TX_DSYNC_SW field. + I2S_TIMING_TX_DSYNC_SW_Pos = 0x14 + // Bit mask of TX_DSYNC_SW field. + I2S_TIMING_TX_DSYNC_SW_Msk = 0x100000 + // Bit TX_DSYNC_SW. + I2S_TIMING_TX_DSYNC_SW = 0x100000 + // Position of RX_DSYNC_SW field. + I2S_TIMING_RX_DSYNC_SW_Pos = 0x15 + // Bit mask of RX_DSYNC_SW field. + I2S_TIMING_RX_DSYNC_SW_Msk = 0x200000 + // Bit RX_DSYNC_SW. + I2S_TIMING_RX_DSYNC_SW = 0x200000 + // Position of DATA_ENABLE_DELAY field. + I2S_TIMING_DATA_ENABLE_DELAY_Pos = 0x16 + // Bit mask of DATA_ENABLE_DELAY field. + I2S_TIMING_DATA_ENABLE_DELAY_Msk = 0xc00000 + // Position of TX_BCK_IN_INV field. + I2S_TIMING_TX_BCK_IN_INV_Pos = 0x18 + // Bit mask of TX_BCK_IN_INV field. + I2S_TIMING_TX_BCK_IN_INV_Msk = 0x1000000 + // Bit TX_BCK_IN_INV. + I2S_TIMING_TX_BCK_IN_INV = 0x1000000 + + // FIFO_CONF: I2S FIFO configuration register + // Position of RX_DATA_NUM field. + I2S_FIFO_CONF_RX_DATA_NUM_Pos = 0x0 + // Bit mask of RX_DATA_NUM field. + I2S_FIFO_CONF_RX_DATA_NUM_Msk = 0x3f + // Position of TX_DATA_NUM field. + I2S_FIFO_CONF_TX_DATA_NUM_Pos = 0x6 + // Bit mask of TX_DATA_NUM field. + I2S_FIFO_CONF_TX_DATA_NUM_Msk = 0xfc0 + // Position of DSCR_EN field. + I2S_FIFO_CONF_DSCR_EN_Pos = 0xc + // Bit mask of DSCR_EN field. + I2S_FIFO_CONF_DSCR_EN_Msk = 0x1000 + // Bit DSCR_EN. + I2S_FIFO_CONF_DSCR_EN = 0x1000 + // Position of TX_FIFO_MOD field. + I2S_FIFO_CONF_TX_FIFO_MOD_Pos = 0xd + // Bit mask of TX_FIFO_MOD field. + I2S_FIFO_CONF_TX_FIFO_MOD_Msk = 0xe000 + // Position of RX_FIFO_MOD field. + I2S_FIFO_CONF_RX_FIFO_MOD_Pos = 0x10 + // Bit mask of RX_FIFO_MOD field. + I2S_FIFO_CONF_RX_FIFO_MOD_Msk = 0x70000 + // Position of TX_FIFO_MOD_FORCE_EN field. + I2S_FIFO_CONF_TX_FIFO_MOD_FORCE_EN_Pos = 0x13 + // Bit mask of TX_FIFO_MOD_FORCE_EN field. + I2S_FIFO_CONF_TX_FIFO_MOD_FORCE_EN_Msk = 0x80000 + // Bit TX_FIFO_MOD_FORCE_EN. + I2S_FIFO_CONF_TX_FIFO_MOD_FORCE_EN = 0x80000 + // Position of RX_FIFO_MOD_FORCE_EN field. + I2S_FIFO_CONF_RX_FIFO_MOD_FORCE_EN_Pos = 0x14 + // Bit mask of RX_FIFO_MOD_FORCE_EN field. + I2S_FIFO_CONF_RX_FIFO_MOD_FORCE_EN_Msk = 0x100000 + // Bit RX_FIFO_MOD_FORCE_EN. + I2S_FIFO_CONF_RX_FIFO_MOD_FORCE_EN = 0x100000 + // Position of RX_FIFO_SYNC field. + I2S_FIFO_CONF_RX_FIFO_SYNC_Pos = 0x15 + // Bit mask of RX_FIFO_SYNC field. + I2S_FIFO_CONF_RX_FIFO_SYNC_Msk = 0x200000 + // Bit RX_FIFO_SYNC. + I2S_FIFO_CONF_RX_FIFO_SYNC = 0x200000 + // Position of RX_24MSB_EN field. + I2S_FIFO_CONF_RX_24MSB_EN_Pos = 0x16 + // Bit mask of RX_24MSB_EN field. + I2S_FIFO_CONF_RX_24MSB_EN_Msk = 0x400000 + // Bit RX_24MSB_EN. + I2S_FIFO_CONF_RX_24MSB_EN = 0x400000 + // Position of TX_24MSB_EN field. + I2S_FIFO_CONF_TX_24MSB_EN_Pos = 0x17 + // Bit mask of TX_24MSB_EN field. + I2S_FIFO_CONF_TX_24MSB_EN_Msk = 0x800000 + // Bit TX_24MSB_EN. + I2S_FIFO_CONF_TX_24MSB_EN = 0x800000 + + // RXEOF_NUM: I2S DMA RX EOF data length + // Position of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Pos = 0x0 + // Bit mask of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Msk = 0xffffffff + + // CONF_SIGLE_DATA: Constant single channel data + // Position of SIGLE_DATA field. + I2S_CONF_SIGLE_DATA_SIGLE_DATA_Pos = 0x0 + // Bit mask of SIGLE_DATA field. + I2S_CONF_SIGLE_DATA_SIGLE_DATA_Msk = 0xffffffff + + // CONF_CHAN: I2S channel configuration register + // Position of TX_CHAN_MOD field. + I2S_CONF_CHAN_TX_CHAN_MOD_Pos = 0x0 + // Bit mask of TX_CHAN_MOD field. + I2S_CONF_CHAN_TX_CHAN_MOD_Msk = 0x7 + // Position of RX_CHAN_MOD field. + I2S_CONF_CHAN_RX_CHAN_MOD_Pos = 0x3 + // Bit mask of RX_CHAN_MOD field. + I2S_CONF_CHAN_RX_CHAN_MOD_Msk = 0x18 + + // OUT_LINK: I2S DMA TX configuration register + // Position of OUTLINK_ADDR field. + I2S_OUT_LINK_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + I2S_OUT_LINK_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + I2S_OUT_LINK_OUTLINK_STOP_Pos = 0x1c + // Bit mask of OUTLINK_STOP field. + I2S_OUT_LINK_OUTLINK_STOP_Msk = 0x10000000 + // Bit OUTLINK_STOP. + I2S_OUT_LINK_OUTLINK_STOP = 0x10000000 + // Position of OUTLINK_START field. + I2S_OUT_LINK_OUTLINK_START_Pos = 0x1d + // Bit mask of OUTLINK_START field. + I2S_OUT_LINK_OUTLINK_START_Msk = 0x20000000 + // Bit OUTLINK_START. + I2S_OUT_LINK_OUTLINK_START = 0x20000000 + // Position of OUTLINK_RESTART field. + I2S_OUT_LINK_OUTLINK_RESTART_Pos = 0x1e + // Bit mask of OUTLINK_RESTART field. + I2S_OUT_LINK_OUTLINK_RESTART_Msk = 0x40000000 + // Bit OUTLINK_RESTART. + I2S_OUT_LINK_OUTLINK_RESTART = 0x40000000 + // Position of OUTLINK_PARK field. + I2S_OUT_LINK_OUTLINK_PARK_Pos = 0x1f + // Bit mask of OUTLINK_PARK field. + I2S_OUT_LINK_OUTLINK_PARK_Msk = 0x80000000 + // Bit OUTLINK_PARK. + I2S_OUT_LINK_OUTLINK_PARK = 0x80000000 + + // IN_LINK: I2S DMA RX configuration register + // Position of INLINK_ADDR field. + I2S_IN_LINK_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + I2S_IN_LINK_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_STOP field. + I2S_IN_LINK_INLINK_STOP_Pos = 0x1c + // Bit mask of INLINK_STOP field. + I2S_IN_LINK_INLINK_STOP_Msk = 0x10000000 + // Bit INLINK_STOP. + I2S_IN_LINK_INLINK_STOP = 0x10000000 + // Position of INLINK_START field. + I2S_IN_LINK_INLINK_START_Pos = 0x1d + // Bit mask of INLINK_START field. + I2S_IN_LINK_INLINK_START_Msk = 0x20000000 + // Bit INLINK_START. + I2S_IN_LINK_INLINK_START = 0x20000000 + // Position of INLINK_RESTART field. + I2S_IN_LINK_INLINK_RESTART_Pos = 0x1e + // Bit mask of INLINK_RESTART field. + I2S_IN_LINK_INLINK_RESTART_Msk = 0x40000000 + // Bit INLINK_RESTART. + I2S_IN_LINK_INLINK_RESTART = 0x40000000 + // Position of INLINK_PARK field. + I2S_IN_LINK_INLINK_PARK_Pos = 0x1f + // Bit mask of INLINK_PARK field. + I2S_IN_LINK_INLINK_PARK_Msk = 0x80000000 + // Bit INLINK_PARK. + I2S_IN_LINK_INLINK_PARK = 0x80000000 + + // OUT_EOF_DES_ADDR: Address of outlink descriptor that produces EOF + // Position of OUT_EOF_DES_ADDR field. + I2S_OUT_EOF_DES_ADDR_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + I2S_OUT_EOF_DES_ADDR_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_EOF_DES_ADDR: Address of inlink descriptor that produces EOF + // Position of IN_SUC_EOF_DES_ADDR field. + I2S_IN_EOF_DES_ADDR_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + I2S_IN_EOF_DES_ADDR_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR: Address of buffer relative to the outlink descriptor that produces EOF + // Position of OUT_EOF_BFR_DES_ADDR field. + I2S_OUT_EOF_BFR_DES_ADDR_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + I2S_OUT_EOF_BFR_DES_ADDR_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // INLINK_DSCR: Address of current inlink descriptor + // Position of INLINK_DSCR field. + I2S_INLINK_DSCR_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + I2S_INLINK_DSCR_INLINK_DSCR_Msk = 0xffffffff + + // INLINK_DSCR_BF0: Address of next inlink descriptor + // Position of INLINK_DSCR_BF0 field. + I2S_INLINK_DSCR_BF0_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + I2S_INLINK_DSCR_BF0_INLINK_DSCR_BF0_Msk = 0xffffffff + + // INLINK_DSCR_BF1: Address of next inlink data buffer + // Position of INLINK_DSCR_BF1 field. + I2S_INLINK_DSCR_BF1_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + I2S_INLINK_DSCR_BF1_INLINK_DSCR_BF1_Msk = 0xffffffff + + // OUTLINK_DSCR: Address of current outlink descriptor + // Position of OUTLINK_DSCR field. + I2S_OUTLINK_DSCR_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + I2S_OUTLINK_DSCR_OUTLINK_DSCR_Msk = 0xffffffff + + // OUTLINK_DSCR_BF0: Address of next outlink descriptor + // Position of OUTLINK_DSCR_BF0 field. + I2S_OUTLINK_DSCR_BF0_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + I2S_OUTLINK_DSCR_BF0_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUTLINK_DSCR_BF1: Address of next outlink data buffer + // Position of OUTLINK_DSCR_BF1 field. + I2S_OUTLINK_DSCR_BF1_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + I2S_OUTLINK_DSCR_BF1_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // LC_CONF: I2S DMA configuration register + // Position of IN_RST field. + I2S_LC_CONF_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + I2S_LC_CONF_IN_RST_Msk = 0x1 + // Bit IN_RST. + I2S_LC_CONF_IN_RST = 0x1 + // Position of OUT_RST field. + I2S_LC_CONF_OUT_RST_Pos = 0x1 + // Bit mask of OUT_RST field. + I2S_LC_CONF_OUT_RST_Msk = 0x2 + // Bit OUT_RST. + I2S_LC_CONF_OUT_RST = 0x2 + // Position of AHBM_FIFO_RST field. + I2S_LC_CONF_AHBM_FIFO_RST_Pos = 0x2 + // Bit mask of AHBM_FIFO_RST field. + I2S_LC_CONF_AHBM_FIFO_RST_Msk = 0x4 + // Bit AHBM_FIFO_RST. + I2S_LC_CONF_AHBM_FIFO_RST = 0x4 + // Position of AHBM_RST field. + I2S_LC_CONF_AHBM_RST_Pos = 0x3 + // Bit mask of AHBM_RST field. + I2S_LC_CONF_AHBM_RST_Msk = 0x8 + // Bit AHBM_RST. + I2S_LC_CONF_AHBM_RST = 0x8 + // Position of OUT_LOOP_TEST field. + I2S_LC_CONF_OUT_LOOP_TEST_Pos = 0x4 + // Bit mask of OUT_LOOP_TEST field. + I2S_LC_CONF_OUT_LOOP_TEST_Msk = 0x10 + // Bit OUT_LOOP_TEST. + I2S_LC_CONF_OUT_LOOP_TEST = 0x10 + // Position of IN_LOOP_TEST field. + I2S_LC_CONF_IN_LOOP_TEST_Pos = 0x5 + // Bit mask of IN_LOOP_TEST field. + I2S_LC_CONF_IN_LOOP_TEST_Msk = 0x20 + // Bit IN_LOOP_TEST. + I2S_LC_CONF_IN_LOOP_TEST = 0x20 + // Position of OUT_AUTO_WRBACK field. + I2S_LC_CONF_OUT_AUTO_WRBACK_Pos = 0x6 + // Bit mask of OUT_AUTO_WRBACK field. + I2S_LC_CONF_OUT_AUTO_WRBACK_Msk = 0x40 + // Bit OUT_AUTO_WRBACK. + I2S_LC_CONF_OUT_AUTO_WRBACK = 0x40 + // Position of OUT_NO_RESTART_CLR field. + I2S_LC_CONF_OUT_NO_RESTART_CLR_Pos = 0x7 + // Bit mask of OUT_NO_RESTART_CLR field. + I2S_LC_CONF_OUT_NO_RESTART_CLR_Msk = 0x80 + // Bit OUT_NO_RESTART_CLR. + I2S_LC_CONF_OUT_NO_RESTART_CLR = 0x80 + // Position of OUT_EOF_MODE field. + I2S_LC_CONF_OUT_EOF_MODE_Pos = 0x8 + // Bit mask of OUT_EOF_MODE field. + I2S_LC_CONF_OUT_EOF_MODE_Msk = 0x100 + // Bit OUT_EOF_MODE. + I2S_LC_CONF_OUT_EOF_MODE = 0x100 + // Position of OUTDSCR_BURST_EN field. + I2S_LC_CONF_OUTDSCR_BURST_EN_Pos = 0x9 + // Bit mask of OUTDSCR_BURST_EN field. + I2S_LC_CONF_OUTDSCR_BURST_EN_Msk = 0x200 + // Bit OUTDSCR_BURST_EN. + I2S_LC_CONF_OUTDSCR_BURST_EN = 0x200 + // Position of INDSCR_BURST_EN field. + I2S_LC_CONF_INDSCR_BURST_EN_Pos = 0xa + // Bit mask of INDSCR_BURST_EN field. + I2S_LC_CONF_INDSCR_BURST_EN_Msk = 0x400 + // Bit INDSCR_BURST_EN. + I2S_LC_CONF_INDSCR_BURST_EN = 0x400 + // Position of OUT_DATA_BURST_EN field. + I2S_LC_CONF_OUT_DATA_BURST_EN_Pos = 0xb + // Bit mask of OUT_DATA_BURST_EN field. + I2S_LC_CONF_OUT_DATA_BURST_EN_Msk = 0x800 + // Bit OUT_DATA_BURST_EN. + I2S_LC_CONF_OUT_DATA_BURST_EN = 0x800 + // Position of CHECK_OWNER field. + I2S_LC_CONF_CHECK_OWNER_Pos = 0xc + // Bit mask of CHECK_OWNER field. + I2S_LC_CONF_CHECK_OWNER_Msk = 0x1000 + // Bit CHECK_OWNER. + I2S_LC_CONF_CHECK_OWNER = 0x1000 + // Position of MEM_TRANS_EN field. + I2S_LC_CONF_MEM_TRANS_EN_Pos = 0xd + // Bit mask of MEM_TRANS_EN field. + I2S_LC_CONF_MEM_TRANS_EN_Msk = 0x2000 + // Bit MEM_TRANS_EN. + I2S_LC_CONF_MEM_TRANS_EN = 0x2000 + // Position of EXT_MEM_BK_SIZE field. + I2S_LC_CONF_EXT_MEM_BK_SIZE_Pos = 0xe + // Bit mask of EXT_MEM_BK_SIZE field. + I2S_LC_CONF_EXT_MEM_BK_SIZE_Msk = 0xc000 + + // OUTFIFO_PUSH: APB out FIFO mode register + // Position of OUTFIFO_WDATA field. + I2S_OUTFIFO_PUSH_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + I2S_OUTFIFO_PUSH_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + I2S_OUTFIFO_PUSH_OUTFIFO_PUSH_Pos = 0x10 + // Bit mask of OUTFIFO_PUSH field. + I2S_OUTFIFO_PUSH_OUTFIFO_PUSH_Msk = 0x10000 + // Bit OUTFIFO_PUSH. + I2S_OUTFIFO_PUSH_OUTFIFO_PUSH = 0x10000 + + // INFIFO_POP: APB in FIFO mode register + // Position of INFIFO_RDATA field. + I2S_INFIFO_POP_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + I2S_INFIFO_POP_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + I2S_INFIFO_POP_INFIFO_POP_Pos = 0x10 + // Bit mask of INFIFO_POP field. + I2S_INFIFO_POP_INFIFO_POP_Msk = 0x10000 + // Bit INFIFO_POP. + I2S_INFIFO_POP_INFIFO_POP = 0x10000 + + // LC_STATE0: I2S DMA TX status + // Position of OUTLINK_DSCR_ADDR field. + I2S_LC_STATE0_OUTLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR field. + I2S_LC_STATE0_OUTLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of OUT_DSCR_STATE field. + I2S_LC_STATE0_OUT_DSCR_STATE_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE field. + I2S_LC_STATE0_OUT_DSCR_STATE_Msk = 0xc0000 + // Position of OUT_STATE field. + I2S_LC_STATE0_OUT_STATE_Pos = 0x14 + // Bit mask of OUT_STATE field. + I2S_LC_STATE0_OUT_STATE_Msk = 0x700000 + // Position of OUTFIFO_CNT field. + I2S_LC_STATE0_OUTFIFO_CNT_Pos = 0x17 + // Bit mask of OUTFIFO_CNT field. + I2S_LC_STATE0_OUTFIFO_CNT_Msk = 0x3f800000 + // Position of OUT_FULL field. + I2S_LC_STATE0_OUT_FULL_Pos = 0x1e + // Bit mask of OUT_FULL field. + I2S_LC_STATE0_OUT_FULL_Msk = 0x40000000 + // Bit OUT_FULL. + I2S_LC_STATE0_OUT_FULL = 0x40000000 + // Position of OUT_EMPTY field. + I2S_LC_STATE0_OUT_EMPTY_Pos = 0x1f + // Bit mask of OUT_EMPTY field. + I2S_LC_STATE0_OUT_EMPTY_Msk = 0x80000000 + // Bit OUT_EMPTY. + I2S_LC_STATE0_OUT_EMPTY = 0x80000000 + + // LC_STATE1: I2S DMA RX status + // Position of INLINK_DSCR_ADDR field. + I2S_LC_STATE1_INLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR field. + I2S_LC_STATE1_INLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of IN_DSCR_STATE field. + I2S_LC_STATE1_IN_DSCR_STATE_Pos = 0x12 + // Bit mask of IN_DSCR_STATE field. + I2S_LC_STATE1_IN_DSCR_STATE_Msk = 0xc0000 + // Position of IN_STATE field. + I2S_LC_STATE1_IN_STATE_Pos = 0x14 + // Bit mask of IN_STATE field. + I2S_LC_STATE1_IN_STATE_Msk = 0x700000 + // Position of INFIFO_CNT_DEBUG field. + I2S_LC_STATE1_INFIFO_CNT_DEBUG_Pos = 0x17 + // Bit mask of INFIFO_CNT_DEBUG field. + I2S_LC_STATE1_INFIFO_CNT_DEBUG_Msk = 0x3f800000 + // Position of IN_FULL field. + I2S_LC_STATE1_IN_FULL_Pos = 0x1e + // Bit mask of IN_FULL field. + I2S_LC_STATE1_IN_FULL_Msk = 0x40000000 + // Bit IN_FULL. + I2S_LC_STATE1_IN_FULL = 0x40000000 + // Position of IN_EMPTY field. + I2S_LC_STATE1_IN_EMPTY_Pos = 0x1f + // Bit mask of IN_EMPTY field. + I2S_LC_STATE1_IN_EMPTY_Msk = 0x80000000 + // Bit IN_EMPTY. + I2S_LC_STATE1_IN_EMPTY = 0x80000000 + + // LC_HUNG_CONF: I2S Hung configuration register + // Position of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Pos = 0x0 + // Bit mask of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Msk = 0xff + // Position of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit LC_FIFO_TIMEOUT_ENA. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA = 0x800 + + // CONF1: I2S configuration register 1 + // Position of TX_PCM_CONF field. + I2S_CONF1_TX_PCM_CONF_Pos = 0x0 + // Bit mask of TX_PCM_CONF field. + I2S_CONF1_TX_PCM_CONF_Msk = 0x7 + // Position of TX_PCM_BYPASS field. + I2S_CONF1_TX_PCM_BYPASS_Pos = 0x3 + // Bit mask of TX_PCM_BYPASS field. + I2S_CONF1_TX_PCM_BYPASS_Msk = 0x8 + // Bit TX_PCM_BYPASS. + I2S_CONF1_TX_PCM_BYPASS = 0x8 + // Position of RX_PCM_CONF field. + I2S_CONF1_RX_PCM_CONF_Pos = 0x4 + // Bit mask of RX_PCM_CONF field. + I2S_CONF1_RX_PCM_CONF_Msk = 0x70 + // Position of RX_PCM_BYPASS field. + I2S_CONF1_RX_PCM_BYPASS_Pos = 0x7 + // Bit mask of RX_PCM_BYPASS field. + I2S_CONF1_RX_PCM_BYPASS_Msk = 0x80 + // Bit RX_PCM_BYPASS. + I2S_CONF1_RX_PCM_BYPASS = 0x80 + // Position of TX_STOP_EN field. + I2S_CONF1_TX_STOP_EN_Pos = 0x8 + // Bit mask of TX_STOP_EN field. + I2S_CONF1_TX_STOP_EN_Msk = 0x100 + // Bit TX_STOP_EN. + I2S_CONF1_TX_STOP_EN = 0x100 + // Position of TX_ZEROS_RM_EN field. + I2S_CONF1_TX_ZEROS_RM_EN_Pos = 0x9 + // Bit mask of TX_ZEROS_RM_EN field. + I2S_CONF1_TX_ZEROS_RM_EN_Msk = 0x200 + // Bit TX_ZEROS_RM_EN. + I2S_CONF1_TX_ZEROS_RM_EN = 0x200 + + // PD_CONF: I2S power-down configuration register + // Position of FIFO_FORCE_PD field. + I2S_PD_CONF_FIFO_FORCE_PD_Pos = 0x0 + // Bit mask of FIFO_FORCE_PD field. + I2S_PD_CONF_FIFO_FORCE_PD_Msk = 0x1 + // Bit FIFO_FORCE_PD. + I2S_PD_CONF_FIFO_FORCE_PD = 0x1 + // Position of FIFO_FORCE_PU field. + I2S_PD_CONF_FIFO_FORCE_PU_Pos = 0x1 + // Bit mask of FIFO_FORCE_PU field. + I2S_PD_CONF_FIFO_FORCE_PU_Msk = 0x2 + // Bit FIFO_FORCE_PU. + I2S_PD_CONF_FIFO_FORCE_PU = 0x2 + // Position of PLC_MEM_FORCE_PD field. + I2S_PD_CONF_PLC_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of PLC_MEM_FORCE_PD field. + I2S_PD_CONF_PLC_MEM_FORCE_PD_Msk = 0x4 + // Bit PLC_MEM_FORCE_PD. + I2S_PD_CONF_PLC_MEM_FORCE_PD = 0x4 + // Position of PLC_MEM_FORCE_PU field. + I2S_PD_CONF_PLC_MEM_FORCE_PU_Pos = 0x3 + // Bit mask of PLC_MEM_FORCE_PU field. + I2S_PD_CONF_PLC_MEM_FORCE_PU_Msk = 0x8 + // Bit PLC_MEM_FORCE_PU. + I2S_PD_CONF_PLC_MEM_FORCE_PU = 0x8 + // Position of DMA_RAM_FORCE_PD field. + I2S_PD_CONF_DMA_RAM_FORCE_PD_Pos = 0x4 + // Bit mask of DMA_RAM_FORCE_PD field. + I2S_PD_CONF_DMA_RAM_FORCE_PD_Msk = 0x10 + // Bit DMA_RAM_FORCE_PD. + I2S_PD_CONF_DMA_RAM_FORCE_PD = 0x10 + // Position of DMA_RAM_FORCE_PU field. + I2S_PD_CONF_DMA_RAM_FORCE_PU_Pos = 0x5 + // Bit mask of DMA_RAM_FORCE_PU field. + I2S_PD_CONF_DMA_RAM_FORCE_PU_Msk = 0x20 + // Bit DMA_RAM_FORCE_PU. + I2S_PD_CONF_DMA_RAM_FORCE_PU = 0x20 + // Position of DMA_RAM_CLK_FO field. + I2S_PD_CONF_DMA_RAM_CLK_FO_Pos = 0x6 + // Bit mask of DMA_RAM_CLK_FO field. + I2S_PD_CONF_DMA_RAM_CLK_FO_Msk = 0x40 + // Bit DMA_RAM_CLK_FO. + I2S_PD_CONF_DMA_RAM_CLK_FO = 0x40 + + // CONF2: I2S configuration register 2 + // Position of CAMERA_EN field. + I2S_CONF2_CAMERA_EN_Pos = 0x0 + // Bit mask of CAMERA_EN field. + I2S_CONF2_CAMERA_EN_Msk = 0x1 + // Bit CAMERA_EN. + I2S_CONF2_CAMERA_EN = 0x1 + // Position of LCD_TX_WRX2_EN field. + I2S_CONF2_LCD_TX_WRX2_EN_Pos = 0x1 + // Bit mask of LCD_TX_WRX2_EN field. + I2S_CONF2_LCD_TX_WRX2_EN_Msk = 0x2 + // Bit LCD_TX_WRX2_EN. + I2S_CONF2_LCD_TX_WRX2_EN = 0x2 + // Position of LCD_TX_SDX2_EN field. + I2S_CONF2_LCD_TX_SDX2_EN_Pos = 0x2 + // Bit mask of LCD_TX_SDX2_EN field. + I2S_CONF2_LCD_TX_SDX2_EN_Msk = 0x4 + // Bit LCD_TX_SDX2_EN. + I2S_CONF2_LCD_TX_SDX2_EN = 0x4 + // Position of DATA_ENABLE_TEST_EN field. + I2S_CONF2_DATA_ENABLE_TEST_EN_Pos = 0x3 + // Bit mask of DATA_ENABLE_TEST_EN field. + I2S_CONF2_DATA_ENABLE_TEST_EN_Msk = 0x8 + // Bit DATA_ENABLE_TEST_EN. + I2S_CONF2_DATA_ENABLE_TEST_EN = 0x8 + // Position of DATA_ENABLE field. + I2S_CONF2_DATA_ENABLE_Pos = 0x4 + // Bit mask of DATA_ENABLE field. + I2S_CONF2_DATA_ENABLE_Msk = 0x10 + // Bit DATA_ENABLE. + I2S_CONF2_DATA_ENABLE = 0x10 + // Position of LCD_EN field. + I2S_CONF2_LCD_EN_Pos = 0x5 + // Bit mask of LCD_EN field. + I2S_CONF2_LCD_EN_Msk = 0x20 + // Bit LCD_EN. + I2S_CONF2_LCD_EN = 0x20 + // Position of EXT_ADC_START_EN field. + I2S_CONF2_EXT_ADC_START_EN_Pos = 0x6 + // Bit mask of EXT_ADC_START_EN field. + I2S_CONF2_EXT_ADC_START_EN_Msk = 0x40 + // Bit EXT_ADC_START_EN. + I2S_CONF2_EXT_ADC_START_EN = 0x40 + // Position of INTER_VALID_EN field. + I2S_CONF2_INTER_VALID_EN_Pos = 0x7 + // Bit mask of INTER_VALID_EN field. + I2S_CONF2_INTER_VALID_EN_Msk = 0x80 + // Bit INTER_VALID_EN. + I2S_CONF2_INTER_VALID_EN = 0x80 + // Position of CAM_SYNC_FIFO_RESET field. + I2S_CONF2_CAM_SYNC_FIFO_RESET_Pos = 0x8 + // Bit mask of CAM_SYNC_FIFO_RESET field. + I2S_CONF2_CAM_SYNC_FIFO_RESET_Msk = 0x100 + // Bit CAM_SYNC_FIFO_RESET. + I2S_CONF2_CAM_SYNC_FIFO_RESET = 0x100 + // Position of CAM_CLK_LOOPBACK field. + I2S_CONF2_CAM_CLK_LOOPBACK_Pos = 0x9 + // Bit mask of CAM_CLK_LOOPBACK field. + I2S_CONF2_CAM_CLK_LOOPBACK_Msk = 0x200 + // Bit CAM_CLK_LOOPBACK. + I2S_CONF2_CAM_CLK_LOOPBACK = 0x200 + // Position of VSYNC_FILTER_EN field. + I2S_CONF2_VSYNC_FILTER_EN_Pos = 0xa + // Bit mask of VSYNC_FILTER_EN field. + I2S_CONF2_VSYNC_FILTER_EN_Msk = 0x400 + // Bit VSYNC_FILTER_EN. + I2S_CONF2_VSYNC_FILTER_EN = 0x400 + // Position of VSYNC_FILTER_THRES field. + I2S_CONF2_VSYNC_FILTER_THRES_Pos = 0xb + // Bit mask of VSYNC_FILTER_THRES field. + I2S_CONF2_VSYNC_FILTER_THRES_Msk = 0x3800 + + // CLKM_CONF: I2S module clock configuration register + // Position of CLKM_DIV_NUM field. + I2S_CLKM_CONF_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of CLKM_DIV_NUM field. + I2S_CLKM_CONF_CLKM_DIV_NUM_Msk = 0xff + // Position of CLKM_DIV_B field. + I2S_CLKM_CONF_CLKM_DIV_B_Pos = 0x8 + // Bit mask of CLKM_DIV_B field. + I2S_CLKM_CONF_CLKM_DIV_B_Msk = 0x3f00 + // Position of CLKM_DIV_A field. + I2S_CLKM_CONF_CLKM_DIV_A_Pos = 0xe + // Bit mask of CLKM_DIV_A field. + I2S_CLKM_CONF_CLKM_DIV_A_Msk = 0xfc000 + // Position of CLK_EN field. + I2S_CLKM_CONF_CLK_EN_Pos = 0x14 + // Bit mask of CLK_EN field. + I2S_CLKM_CONF_CLK_EN_Msk = 0x100000 + // Bit CLK_EN. + I2S_CLKM_CONF_CLK_EN = 0x100000 + // Position of CLK_SEL field. + I2S_CLKM_CONF_CLK_SEL_Pos = 0x15 + // Bit mask of CLK_SEL field. + I2S_CLKM_CONF_CLK_SEL_Msk = 0x600000 + + // SAMPLE_RATE_CONF: I2S sample rate register + // Position of TX_BCK_DIV_NUM field. + I2S_SAMPLE_RATE_CONF_TX_BCK_DIV_NUM_Pos = 0x0 + // Bit mask of TX_BCK_DIV_NUM field. + I2S_SAMPLE_RATE_CONF_TX_BCK_DIV_NUM_Msk = 0x3f + // Position of RX_BCK_DIV_NUM field. + I2S_SAMPLE_RATE_CONF_RX_BCK_DIV_NUM_Pos = 0x6 + // Bit mask of RX_BCK_DIV_NUM field. + I2S_SAMPLE_RATE_CONF_RX_BCK_DIV_NUM_Msk = 0xfc0 + // Position of TX_BITS_MOD field. + I2S_SAMPLE_RATE_CONF_TX_BITS_MOD_Pos = 0xc + // Bit mask of TX_BITS_MOD field. + I2S_SAMPLE_RATE_CONF_TX_BITS_MOD_Msk = 0x3f000 + // Position of RX_BITS_MOD field. + I2S_SAMPLE_RATE_CONF_RX_BITS_MOD_Pos = 0x12 + // Bit mask of RX_BITS_MOD field. + I2S_SAMPLE_RATE_CONF_RX_BITS_MOD_Msk = 0xfc0000 + + // STATE: I2S TX status register + // Position of TX_IDLE field. + I2S_STATE_TX_IDLE_Pos = 0x0 + // Bit mask of TX_IDLE field. + I2S_STATE_TX_IDLE_Msk = 0x1 + // Bit TX_IDLE. + I2S_STATE_TX_IDLE = 0x1 + + // DATE: Version control register + // Position of DATE field. + I2S_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2S_DATE_DATE_Msk = 0xffffffff +) + +// Constants for INTERRUPT_CORE0: Interrupt Controller (Core 0) +const ( + // PRO_MAC_INTR_MAP: MAC_INTR interrupt configuration register + // Position of PRO_MAC_INTR_MAP field. + INTERRUPT_CORE0_PRO_MAC_INTR_MAP_PRO_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_MAC_INTR_MAP field. + INTERRUPT_CORE0_PRO_MAC_INTR_MAP_PRO_MAC_INTR_MAP_Msk = 0x1f + + // PRO_MAC_NMI_MAP: MAC_NMI interrupt configuration register + // Position of PRO_MAC_NMI_MAP field. + INTERRUPT_CORE0_PRO_MAC_NMI_MAP_PRO_MAC_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_MAC_NMI_MAP field. + INTERRUPT_CORE0_PRO_MAC_NMI_MAP_PRO_MAC_NMI_MAP_Msk = 0x1f + + // PRO_PWR_INTR_MAP: PWR_INTR interrupt configuration register + // Position of PRO_PWR_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWR_INTR_MAP_PRO_PWR_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PWR_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWR_INTR_MAP_PRO_PWR_INTR_MAP_Msk = 0x1f + + // PRO_BB_INT_MAP: BB_INT interrupt configuration register + // Position of PRO_BB_INT_MAP field. + INTERRUPT_CORE0_PRO_BB_INT_MAP_PRO_BB_INT_MAP_Pos = 0x0 + // Bit mask of PRO_BB_INT_MAP field. + INTERRUPT_CORE0_PRO_BB_INT_MAP_PRO_BB_INT_MAP_Msk = 0x1f + + // PRO_BT_MAC_INT_MAP: BT_MAC_INT interrupt configuration register + // Position of PRO_BT_MAC_INT_MAP field. + INTERRUPT_CORE0_PRO_BT_MAC_INT_MAP_PRO_BT_MAC_INT_MAP_Pos = 0x0 + // Bit mask of PRO_BT_MAC_INT_MAP field. + INTERRUPT_CORE0_PRO_BT_MAC_INT_MAP_PRO_BT_MAC_INT_MAP_Msk = 0x1f + + // PRO_BT_BB_INT_MAP: BT_BB_INT interrupt configuration register + // Position of PRO_BT_BB_INT_MAP field. + INTERRUPT_CORE0_PRO_BT_BB_INT_MAP_PRO_BT_BB_INT_MAP_Pos = 0x0 + // Bit mask of PRO_BT_BB_INT_MAP field. + INTERRUPT_CORE0_PRO_BT_BB_INT_MAP_PRO_BT_BB_INT_MAP_Msk = 0x1f + + // PRO_BT_BB_NMI_MAP: BT_BB_NMI interrupt configuration register + // Position of PRO_BT_BB_NMI_MAP field. + INTERRUPT_CORE0_PRO_BT_BB_NMI_MAP_PRO_BT_BB_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_BT_BB_NMI_MAP field. + INTERRUPT_CORE0_PRO_BT_BB_NMI_MAP_PRO_BT_BB_NMI_MAP_Msk = 0x1f + + // PRO_RWBT_IRQ_MAP: RWBT_IRQ interrupt configuration register + // Position of PRO_RWBT_IRQ_MAP field. + INTERRUPT_CORE0_PRO_RWBT_IRQ_MAP_PRO_RWBT_IRQ_MAP_Pos = 0x0 + // Bit mask of PRO_RWBT_IRQ_MAP field. + INTERRUPT_CORE0_PRO_RWBT_IRQ_MAP_PRO_RWBT_IRQ_MAP_Msk = 0x1f + + // PRO_RWBLE_IRQ_MAP: RWBLE_IRQ interrupt configuration register + // Position of PRO_RWBLE_IRQ_MAP field. + INTERRUPT_CORE0_PRO_RWBLE_IRQ_MAP_PRO_RWBLE_IRQ_MAP_Pos = 0x0 + // Bit mask of PRO_RWBLE_IRQ_MAP field. + INTERRUPT_CORE0_PRO_RWBLE_IRQ_MAP_PRO_RWBLE_IRQ_MAP_Msk = 0x1f + + // PRO_RWBT_NMI_MAP: RWBT_NMI interrupt configuration register + // Position of PRO_RWBT_NMI_MAP field. + INTERRUPT_CORE0_PRO_RWBT_NMI_MAP_PRO_RWBT_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_RWBT_NMI_MAP field. + INTERRUPT_CORE0_PRO_RWBT_NMI_MAP_PRO_RWBT_NMI_MAP_Msk = 0x1f + + // PRO_RWBLE_NMI_MAP: RWBLE_NMI interrupt configuration register + // Position of PRO_RWBLE_NMI_MAP field. + INTERRUPT_CORE0_PRO_RWBLE_NMI_MAP_PRO_RWBLE_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_RWBLE_NMI_MAP field. + INTERRUPT_CORE0_PRO_RWBLE_NMI_MAP_PRO_RWBLE_NMI_MAP_Msk = 0x1f + + // PRO_SLC0_INTR_MAP: SLC0_INTR interrupt configuration register + // Position of PRO_SLC0_INTR_MAP field. + INTERRUPT_CORE0_PRO_SLC0_INTR_MAP_PRO_SLC0_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_SLC0_INTR_MAP field. + INTERRUPT_CORE0_PRO_SLC0_INTR_MAP_PRO_SLC0_INTR_MAP_Msk = 0x1f + + // PRO_SLC1_INTR_MAP: SLC1_INTR interrupt configuration register + // Position of PRO_SLC1_INTR_MAP field. + INTERRUPT_CORE0_PRO_SLC1_INTR_MAP_PRO_SLC1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_SLC1_INTR_MAP field. + INTERRUPT_CORE0_PRO_SLC1_INTR_MAP_PRO_SLC1_INTR_MAP_Msk = 0x1f + + // PRO_UHCI0_INTR_MAP: UHCI0_INTR interrupt configuration register + // Position of PRO_UHCI0_INTR_MAP field. + INTERRUPT_CORE0_PRO_UHCI0_INTR_MAP_PRO_UHCI0_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UHCI0_INTR_MAP field. + INTERRUPT_CORE0_PRO_UHCI0_INTR_MAP_PRO_UHCI0_INTR_MAP_Msk = 0x1f + + // PRO_UHCI1_INTR_MAP: UHCI1_INTR interrupt configuration register + // Position of PRO_UHCI1_INTR_MAP field. + INTERRUPT_CORE0_PRO_UHCI1_INTR_MAP_PRO_UHCI1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UHCI1_INTR_MAP field. + INTERRUPT_CORE0_PRO_UHCI1_INTR_MAP_PRO_UHCI1_INTR_MAP_Msk = 0x1f + + // PRO_TG_T0_LEVEL_INT_MAP: TG_T0_LEVEL_INT interrupt configuration register + // Position of PRO_TG_T0_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_T0_LEVEL_INT_MAP_PRO_TG_T0_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_T0_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_T0_LEVEL_INT_MAP_PRO_TG_T0_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG_T1_LEVEL_INT_MAP: TG_T1_LEVEL_INT interrupt configuration register + // Position of PRO_TG_T1_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_T1_LEVEL_INT_MAP_PRO_TG_T1_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_T1_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_T1_LEVEL_INT_MAP_PRO_TG_T1_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG_WDT_LEVEL_INT_MAP: TG_WDT_LEVEL_INT interrupt configuration register + // Position of PRO_TG_WDT_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_WDT_LEVEL_INT_MAP_PRO_TG_WDT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_WDT_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_WDT_LEVEL_INT_MAP_PRO_TG_WDT_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG_LACT_LEVEL_INT_MAP: TG_LACT_LEVEL_INT interrupt configuration register + // Position of PRO_TG_LACT_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_LACT_LEVEL_INT_MAP_PRO_TG_LACT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_LACT_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_LACT_LEVEL_INT_MAP_PRO_TG_LACT_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG1_T0_LEVEL_INT_MAP: TG1_T0_LEVEL_INT interrupt configuration register + // Position of PRO_TG1_T0_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_T0_LEVEL_INT_MAP_PRO_TG1_T0_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_T0_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_T0_LEVEL_INT_MAP_PRO_TG1_T0_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG1_T1_LEVEL_INT_MAP: TG1_T1_LEVEL_INT interrupt configuration register + // Position of PRO_TG1_T1_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_T1_LEVEL_INT_MAP_PRO_TG1_T1_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_T1_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_T1_LEVEL_INT_MAP_PRO_TG1_T1_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG1_WDT_LEVEL_INT_MAP: TG1_WDT_LEVEL_INT interrupt configuration register + // Position of PRO_TG1_WDT_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_WDT_LEVEL_INT_MAP_PRO_TG1_WDT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_WDT_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_WDT_LEVEL_INT_MAP_PRO_TG1_WDT_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_TG1_LACT_LEVEL_INT_MAP: TG1_LACT_LEVEL_INT interrupt configuration register + // Position of PRO_TG1_LACT_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_LACT_LEVEL_INT_MAP_PRO_TG1_LACT_LEVEL_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_LACT_LEVEL_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_LACT_LEVEL_INT_MAP_PRO_TG1_LACT_LEVEL_INT_MAP_Msk = 0x1f + + // PRO_GPIO_INTERRUPT_PRO_MAP: GPIO_INTERRUPT_PRO interrupt configuration register + // Position of PRO_GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE0_PRO_GPIO_INTERRUPT_PRO_MAP_PRO_GPIO_INTERRUPT_PRO_MAP_Pos = 0x0 + // Bit mask of PRO_GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE0_PRO_GPIO_INTERRUPT_PRO_MAP_PRO_GPIO_INTERRUPT_PRO_MAP_Msk = 0x1f + + // PRO_GPIO_INTERRUPT_PRO_NMI_MAP: GPIO_INTERRUPT_PRO_NMI interrupt configuration register + // Position of PRO_GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE0_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE0_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_Msk = 0x1f + + // PRO_GPIO_INTERRUPT_APP_MAP: GPIO_INTERRUPT_APP interrupt configuration register + // Position of PRO_GPIO_INTERRUPT_APP_MAP field. + INTERRUPT_CORE0_PRO_GPIO_INTERRUPT_APP_MAP_PRO_GPIO_INTERRUPT_APP_MAP_Pos = 0x0 + // Bit mask of PRO_GPIO_INTERRUPT_APP_MAP field. + INTERRUPT_CORE0_PRO_GPIO_INTERRUPT_APP_MAP_PRO_GPIO_INTERRUPT_APP_MAP_Msk = 0x1f + + // PRO_GPIO_INTERRUPT_APP_NMI_MAP: GPIO_INTERRUPT_APP_NMI interrupt configuration register + // Position of PRO_GPIO_INTERRUPT_APP_NMI_MAP field. + INTERRUPT_CORE0_PRO_GPIO_INTERRUPT_APP_NMI_MAP_PRO_GPIO_INTERRUPT_APP_NMI_MAP_Pos = 0x0 + // Bit mask of PRO_GPIO_INTERRUPT_APP_NMI_MAP field. + INTERRUPT_CORE0_PRO_GPIO_INTERRUPT_APP_NMI_MAP_PRO_GPIO_INTERRUPT_APP_NMI_MAP_Msk = 0x1f + + // PRO_DEDICATED_GPIO_IN_INTR_MAP: DEDICATED_GPIO_IN_INTR interrupt configuration register + // Position of PRO_DEDICATED_GPIO_IN_INTR_MAP field. + INTERRUPT_CORE0_PRO_DEDICATED_GPIO_IN_INTR_MAP_PRO_DEDICATED_GPIO_IN_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_DEDICATED_GPIO_IN_INTR_MAP field. + INTERRUPT_CORE0_PRO_DEDICATED_GPIO_IN_INTR_MAP_PRO_DEDICATED_GPIO_IN_INTR_MAP_Msk = 0x1f + + // PRO_CPU_INTR_FROM_CPU_0_MAP: CPU_INTR_FROM_CPU_0 interrupt configuration register + // Position of PRO_CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE0_PRO_CPU_INTR_FROM_CPU_0_MAP_PRO_CPU_INTR_FROM_CPU_0_MAP_Pos = 0x0 + // Bit mask of PRO_CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE0_PRO_CPU_INTR_FROM_CPU_0_MAP_PRO_CPU_INTR_FROM_CPU_0_MAP_Msk = 0x1f + + // PRO_CPU_INTR_FROM_CPU_1_MAP: CPU_INTR_FROM_CPU_1 interrupt configuration register + // Position of PRO_CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE0_PRO_CPU_INTR_FROM_CPU_1_MAP_PRO_CPU_INTR_FROM_CPU_1_MAP_Pos = 0x0 + // Bit mask of PRO_CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE0_PRO_CPU_INTR_FROM_CPU_1_MAP_PRO_CPU_INTR_FROM_CPU_1_MAP_Msk = 0x1f + + // PRO_CPU_INTR_FROM_CPU_2_MAP: CPU_INTR_FROM_CPU_2 interrupt configuration register + // Position of PRO_CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE0_PRO_CPU_INTR_FROM_CPU_2_MAP_PRO_CPU_INTR_FROM_CPU_2_MAP_Pos = 0x0 + // Bit mask of PRO_CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE0_PRO_CPU_INTR_FROM_CPU_2_MAP_PRO_CPU_INTR_FROM_CPU_2_MAP_Msk = 0x1f + + // PRO_CPU_INTR_FROM_CPU_3_MAP: CPU_INTR_FROM_CPU_3 interrupt configuration register + // Position of PRO_CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE0_PRO_CPU_INTR_FROM_CPU_3_MAP_PRO_CPU_INTR_FROM_CPU_3_MAP_Pos = 0x0 + // Bit mask of PRO_CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE0_PRO_CPU_INTR_FROM_CPU_3_MAP_PRO_CPU_INTR_FROM_CPU_3_MAP_Msk = 0x1f + + // PRO_SPI_INTR_1_MAP: SPI_INTR_1 interrupt configuration register + // Position of PRO_SPI_INTR_1_MAP field. + INTERRUPT_CORE0_PRO_SPI_INTR_1_MAP_PRO_SPI_INTR_1_MAP_Pos = 0x0 + // Bit mask of PRO_SPI_INTR_1_MAP field. + INTERRUPT_CORE0_PRO_SPI_INTR_1_MAP_PRO_SPI_INTR_1_MAP_Msk = 0x1f + + // PRO_SPI_INTR_2_MAP: SPI_INTR_2 interrupt configuration register + // Position of PRO_SPI_INTR_2_MAP field. + INTERRUPT_CORE0_PRO_SPI_INTR_2_MAP_PRO_SPI_INTR_2_MAP_Pos = 0x0 + // Bit mask of PRO_SPI_INTR_2_MAP field. + INTERRUPT_CORE0_PRO_SPI_INTR_2_MAP_PRO_SPI_INTR_2_MAP_Msk = 0x1f + + // PRO_SPI_INTR_3_MAP: SPI_INTR_3 interrupt configuration register + // Position of PRO_SPI_INTR_3_MAP field. + INTERRUPT_CORE0_PRO_SPI_INTR_3_MAP_PRO_SPI_INTR_3_MAP_Pos = 0x0 + // Bit mask of PRO_SPI_INTR_3_MAP field. + INTERRUPT_CORE0_PRO_SPI_INTR_3_MAP_PRO_SPI_INTR_3_MAP_Msk = 0x1f + + // PRO_I2S0_INT_MAP: I2S0_INT interrupt configuration register + // Position of PRO_I2S0_INT_MAP field. + INTERRUPT_CORE0_PRO_I2S0_INT_MAP_PRO_I2S0_INT_MAP_Pos = 0x0 + // Bit mask of PRO_I2S0_INT_MAP field. + INTERRUPT_CORE0_PRO_I2S0_INT_MAP_PRO_I2S0_INT_MAP_Msk = 0x1f + + // PRO_I2S1_INT_MAP: I2S1_INT interrupt configuration register + // Position of PRO_I2S1_INT_MAP field. + INTERRUPT_CORE0_PRO_I2S1_INT_MAP_PRO_I2S1_INT_MAP_Pos = 0x0 + // Bit mask of PRO_I2S1_INT_MAP field. + INTERRUPT_CORE0_PRO_I2S1_INT_MAP_PRO_I2S1_INT_MAP_Msk = 0x1f + + // PRO_UART_INTR_MAP: UART_INT interrupt configuration register + // Position of PRO_UART_INTR_MAP field. + INTERRUPT_CORE0_PRO_UART_INTR_MAP_PRO_UART_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UART_INTR_MAP field. + INTERRUPT_CORE0_PRO_UART_INTR_MAP_PRO_UART_INTR_MAP_Msk = 0x1f + + // PRO_UART1_INTR_MAP: UART1_INT interrupt configuration register + // Position of PRO_UART1_INTR_MAP field. + INTERRUPT_CORE0_PRO_UART1_INTR_MAP_PRO_UART1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UART1_INTR_MAP field. + INTERRUPT_CORE0_PRO_UART1_INTR_MAP_PRO_UART1_INTR_MAP_Msk = 0x1f + + // PRO_UART2_INTR_MAP: UART2_INT interrupt configuration register + // Position of PRO_UART2_INTR_MAP field. + INTERRUPT_CORE0_PRO_UART2_INTR_MAP_PRO_UART2_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_UART2_INTR_MAP field. + INTERRUPT_CORE0_PRO_UART2_INTR_MAP_PRO_UART2_INTR_MAP_Msk = 0x1f + + // PRO_SDIO_HOST_INTERRUPT_MAP: SDIO_HOST_INTERRUPT configuration register + // Position of PRO_SDIO_HOST_INTERRUPT_MAP field. + INTERRUPT_CORE0_PRO_SDIO_HOST_INTERRUPT_MAP_PRO_SDIO_HOST_INTERRUPT_MAP_Pos = 0x0 + // Bit mask of PRO_SDIO_HOST_INTERRUPT_MAP field. + INTERRUPT_CORE0_PRO_SDIO_HOST_INTERRUPT_MAP_PRO_SDIO_HOST_INTERRUPT_MAP_Msk = 0x1f + + // PRO_PWM0_INTR_MAP: PWM0_INTR interrupt configuration register + // Position of PRO_PWM0_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWM0_INTR_MAP_PRO_PWM0_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PWM0_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWM0_INTR_MAP_PRO_PWM0_INTR_MAP_Msk = 0x1f + + // PRO_PWM1_INTR_MAP: PWM1_INTR interrupt configuration register + // Position of PRO_PWM1_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWM1_INTR_MAP_PRO_PWM1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PWM1_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWM1_INTR_MAP_PRO_PWM1_INTR_MAP_Msk = 0x1f + + // PRO_PWM2_INTR_MAP: PWM2_INTR interrupt configuration register + // Position of PRO_PWM2_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWM2_INTR_MAP_PRO_PWM2_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PWM2_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWM2_INTR_MAP_PRO_PWM2_INTR_MAP_Msk = 0x1f + + // PRO_PWM3_INTR_MAP: PWM3_INTR interrupt configuration register + // Position of PRO_PWM3_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWM3_INTR_MAP_PRO_PWM3_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PWM3_INTR_MAP field. + INTERRUPT_CORE0_PRO_PWM3_INTR_MAP_PRO_PWM3_INTR_MAP_Msk = 0x1f + + // PRO_LEDC_INT_MAP: LEDC_INTR interrupt configuration register + // Position of PRO_LEDC_INT_MAP field. + INTERRUPT_CORE0_PRO_LEDC_INT_MAP_PRO_LEDC_INT_MAP_Pos = 0x0 + // Bit mask of PRO_LEDC_INT_MAP field. + INTERRUPT_CORE0_PRO_LEDC_INT_MAP_PRO_LEDC_INT_MAP_Msk = 0x1f + + // PRO_EFUSE_INT_MAP: EFUSE_INT interrupt configuration register + // Position of PRO_EFUSE_INT_MAP field. + INTERRUPT_CORE0_PRO_EFUSE_INT_MAP_PRO_EFUSE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_EFUSE_INT_MAP field. + INTERRUPT_CORE0_PRO_EFUSE_INT_MAP_PRO_EFUSE_INT_MAP_Msk = 0x1f + + // PRO_CAN_INT_MAP: CAN_INT interrupt configuration register + // Position of PRO_CAN_INT_MAP field. + INTERRUPT_CORE0_PRO_CAN_INT_MAP_PRO_CAN_INT_MAP_Pos = 0x0 + // Bit mask of PRO_CAN_INT_MAP field. + INTERRUPT_CORE0_PRO_CAN_INT_MAP_PRO_CAN_INT_MAP_Msk = 0x1f + + // PRO_USB_INTR_MAP: USB_INT interrupt configuration register + // Position of PRO_USB_INTR_MAP field. + INTERRUPT_CORE0_PRO_USB_INTR_MAP_PRO_USB_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_USB_INTR_MAP field. + INTERRUPT_CORE0_PRO_USB_INTR_MAP_PRO_USB_INTR_MAP_Msk = 0x1f + + // PRO_RTC_CORE_INTR_MAP: RTC_CORE_INTR interrupt configuration register + // Position of PRO_RTC_CORE_INTR_MAP field. + INTERRUPT_CORE0_PRO_RTC_CORE_INTR_MAP_PRO_RTC_CORE_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_RTC_CORE_INTR_MAP field. + INTERRUPT_CORE0_PRO_RTC_CORE_INTR_MAP_PRO_RTC_CORE_INTR_MAP_Msk = 0x1f + + // PRO_RMT_INTR_MAP: RMT_INTR interrupt configuration register + // Position of PRO_RMT_INTR_MAP field. + INTERRUPT_CORE0_PRO_RMT_INTR_MAP_PRO_RMT_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_RMT_INTR_MAP field. + INTERRUPT_CORE0_PRO_RMT_INTR_MAP_PRO_RMT_INTR_MAP_Msk = 0x1f + + // PRO_PCNT_INTR_MAP: PCNT_INTR interrupt configuration register + // Position of PRO_PCNT_INTR_MAP field. + INTERRUPT_CORE0_PRO_PCNT_INTR_MAP_PRO_PCNT_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PCNT_INTR_MAP field. + INTERRUPT_CORE0_PRO_PCNT_INTR_MAP_PRO_PCNT_INTR_MAP_Msk = 0x1f + + // PRO_I2C_EXT0_INTR_MAP: I2C_EXT0_INTR interrupt configuration register + // Position of PRO_I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE0_PRO_I2C_EXT0_INTR_MAP_PRO_I2C_EXT0_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE0_PRO_I2C_EXT0_INTR_MAP_PRO_I2C_EXT0_INTR_MAP_Msk = 0x1f + + // PRO_I2C_EXT1_INTR_MAP: I2C_EXT1_INTR interrupt configuration register + // Position of PRO_I2C_EXT1_INTR_MAP field. + INTERRUPT_CORE0_PRO_I2C_EXT1_INTR_MAP_PRO_I2C_EXT1_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_I2C_EXT1_INTR_MAP field. + INTERRUPT_CORE0_PRO_I2C_EXT1_INTR_MAP_PRO_I2C_EXT1_INTR_MAP_Msk = 0x1f + + // PRO_RSA_INTR_MAP: RSA_INTR interrupt configuration register + // Position of PRO_RSA_INTR_MAP field. + INTERRUPT_CORE0_PRO_RSA_INTR_MAP_PRO_RSA_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_RSA_INTR_MAP field. + INTERRUPT_CORE0_PRO_RSA_INTR_MAP_PRO_RSA_INTR_MAP_Msk = 0x1f + + // PRO_SHA_INTR_MAP: SHA_INTR interrupt configuration register + // Position of PRO_SHA_INTR_MAP field. + INTERRUPT_CORE0_PRO_SHA_INTR_MAP_PRO_SHA_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_SHA_INTR_MAP field. + INTERRUPT_CORE0_PRO_SHA_INTR_MAP_PRO_SHA_INTR_MAP_Msk = 0x1f + + // PRO_AES_INTR_MAP: AES_INTR interrupt configuration register + // Position of PRO_AES_INTR_MAP field. + INTERRUPT_CORE0_PRO_AES_INTR_MAP_PRO_AES_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_AES_INTR_MAP field. + INTERRUPT_CORE0_PRO_AES_INTR_MAP_PRO_AES_INTR_MAP_Msk = 0x1f + + // PRO_SPI2_DMA_INT_MAP: SPI2_DMA_INT interrupt configuration register + // Position of PRO_SPI2_DMA_INT_MAP field. + INTERRUPT_CORE0_PRO_SPI2_DMA_INT_MAP_PRO_SPI2_DMA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_SPI2_DMA_INT_MAP field. + INTERRUPT_CORE0_PRO_SPI2_DMA_INT_MAP_PRO_SPI2_DMA_INT_MAP_Msk = 0x1f + + // PRO_SPI3_DMA_INT_MAP: SPI3_DMA_INT interrupt configuration register + // Position of PRO_SPI3_DMA_INT_MAP field. + INTERRUPT_CORE0_PRO_SPI3_DMA_INT_MAP_PRO_SPI3_DMA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_SPI3_DMA_INT_MAP field. + INTERRUPT_CORE0_PRO_SPI3_DMA_INT_MAP_PRO_SPI3_DMA_INT_MAP_Msk = 0x1f + + // PRO_WDG_INT_MAP: WDG_INT interrupt configuration register + // Position of PRO_WDG_INT_MAP field. + INTERRUPT_CORE0_PRO_WDG_INT_MAP_PRO_WDG_INT_MAP_Pos = 0x0 + // Bit mask of PRO_WDG_INT_MAP field. + INTERRUPT_CORE0_PRO_WDG_INT_MAP_PRO_WDG_INT_MAP_Msk = 0x1f + + // PRO_TIMER_INT1_MAP: TIMER_INT1 interrupt configuration register + // Position of PRO_TIMER_INT1_MAP field. + INTERRUPT_CORE0_PRO_TIMER_INT1_MAP_PRO_TIMER_INT1_MAP_Pos = 0x0 + // Bit mask of PRO_TIMER_INT1_MAP field. + INTERRUPT_CORE0_PRO_TIMER_INT1_MAP_PRO_TIMER_INT1_MAP_Msk = 0x1f + + // PRO_TIMER_INT2_MAP: TIMER_INT2 interrupt configuration register + // Position of PRO_TIMER_INT2_MAP field. + INTERRUPT_CORE0_PRO_TIMER_INT2_MAP_PRO_TIMER_INT2_MAP_Pos = 0x0 + // Bit mask of PRO_TIMER_INT2_MAP field. + INTERRUPT_CORE0_PRO_TIMER_INT2_MAP_PRO_TIMER_INT2_MAP_Msk = 0x1f + + // PRO_TG_T0_EDGE_INT_MAP: TG_T0_EDGE_INT interrupt configuration register + // Position of PRO_TG_T0_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_T0_EDGE_INT_MAP_PRO_TG_T0_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_T0_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_T0_EDGE_INT_MAP_PRO_TG_T0_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG_T1_EDGE_INT_MAP: TG_T1_EDGE_INT interrupt configuration register + // Position of PRO_TG_T1_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_T1_EDGE_INT_MAP_PRO_TG_T1_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_T1_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_T1_EDGE_INT_MAP_PRO_TG_T1_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG_WDT_EDGE_INT_MAP: TG_WDT_EDGE_INT interrupt configuration register + // Position of PRO_TG_WDT_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_WDT_EDGE_INT_MAP_PRO_TG_WDT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_WDT_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_WDT_EDGE_INT_MAP_PRO_TG_WDT_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG_LACT_EDGE_INT_MAP: TG_LACT_EDGE_INT interrupt configuration register + // Position of PRO_TG_LACT_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_LACT_EDGE_INT_MAP_PRO_TG_LACT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG_LACT_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG_LACT_EDGE_INT_MAP_PRO_TG_LACT_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG1_T0_EDGE_INT_MAP: TG1_T0_EDGE_INT interrupt configuration register + // Position of PRO_TG1_T0_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_T0_EDGE_INT_MAP_PRO_TG1_T0_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_T0_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_T0_EDGE_INT_MAP_PRO_TG1_T0_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG1_T1_EDGE_INT_MAP: TG1_T1_EDGE_INT interrupt configuration register + // Position of PRO_TG1_T1_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_T1_EDGE_INT_MAP_PRO_TG1_T1_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_T1_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_T1_EDGE_INT_MAP_PRO_TG1_T1_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG1_WDT_EDGE_INT_MAP: TG1_WDT_EDGE_INT interrupt configuration register + // Position of PRO_TG1_WDT_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_WDT_EDGE_INT_MAP_PRO_TG1_WDT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_WDT_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_WDT_EDGE_INT_MAP_PRO_TG1_WDT_EDGE_INT_MAP_Msk = 0x1f + + // PRO_TG1_LACT_EDGE_INT_MAP: TG1_LACT_EDGE_INT interrupt configuration register + // Position of PRO_TG1_LACT_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_LACT_EDGE_INT_MAP_PRO_TG1_LACT_EDGE_INT_MAP_Pos = 0x0 + // Bit mask of PRO_TG1_LACT_EDGE_INT_MAP field. + INTERRUPT_CORE0_PRO_TG1_LACT_EDGE_INT_MAP_PRO_TG1_LACT_EDGE_INT_MAP_Msk = 0x1f + + // PRO_CACHE_IA_INT_MAP: CACHE_IA_INT interrupt configuration register + // Position of PRO_CACHE_IA_INT_MAP field. + INTERRUPT_CORE0_PRO_CACHE_IA_INT_MAP_PRO_CACHE_IA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_CACHE_IA_INT_MAP field. + INTERRUPT_CORE0_PRO_CACHE_IA_INT_MAP_PRO_CACHE_IA_INT_MAP_Msk = 0x1f + + // PRO_SYSTIMER_TARGET0_INT_MAP: SYSTIMER_TARGET0_INT interrupt configuration register + // Position of PRO_SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE0_PRO_SYSTIMER_TARGET0_INT_MAP_PRO_SYSTIMER_TARGET0_INT_MAP_Pos = 0x0 + // Bit mask of PRO_SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE0_PRO_SYSTIMER_TARGET0_INT_MAP_PRO_SYSTIMER_TARGET0_INT_MAP_Msk = 0x1f + + // PRO_SYSTIMER_TARGET1_INT_MAP: SYSTIMER_TARGET1_INT interrupt configuration register + // Position of PRO_SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE0_PRO_SYSTIMER_TARGET1_INT_MAP_PRO_SYSTIMER_TARGET1_INT_MAP_Pos = 0x0 + // Bit mask of PRO_SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE0_PRO_SYSTIMER_TARGET1_INT_MAP_PRO_SYSTIMER_TARGET1_INT_MAP_Msk = 0x1f + + // PRO_SYSTIMER_TARGET2_INT_MAP: SYSTIMER_TARGET2_INT interrupt configuration register + // Position of PRO_SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE0_PRO_SYSTIMER_TARGET2_INT_MAP_PRO_SYSTIMER_TARGET2_INT_MAP_Pos = 0x0 + // Bit mask of PRO_SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE0_PRO_SYSTIMER_TARGET2_INT_MAP_PRO_SYSTIMER_TARGET2_INT_MAP_Msk = 0x1f + + // PRO_ASSIST_DEBUG_INTR_MAP: ASSIST_DEBUG_INTR interrupt configuration register + // Position of PRO_ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE0_PRO_ASSIST_DEBUG_INTR_MAP_PRO_ASSIST_DEBUG_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE0_PRO_ASSIST_DEBUG_INTR_MAP_PRO_ASSIST_DEBUG_INTR_MAP_Msk = 0x1f + + // PRO_PMS_PRO_IRAM0_ILG_INTR_MAP: PMS_PRO_IRAM0_ILG interrupt configuration register + // Position of PRO_PMS_PRO_IRAM0_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PMS_PRO_IRAM0_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_Msk = 0x1f + + // PRO_PMS_PRO_DRAM0_ILG_INTR_MAP: PMS_PRO_DRAM0_ILG interrupt configuration register + // Position of PRO_PMS_PRO_DRAM0_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PMS_PRO_DRAM0_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_Msk = 0x1f + + // PRO_PMS_PRO_DPORT_ILG_INTR_MAP: PMS_PRO_DPORT_ILG interrupt configuration register + // Position of PRO_PMS_PRO_DPORT_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PMS_PRO_DPORT_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_Msk = 0x1f + + // PRO_PMS_PRO_AHB_ILG_INTR_MAP: PMS_PRO_AHB_ILG interrupt configuration register + // Position of PRO_PMS_PRO_AHB_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_AHB_ILG_INTR_MAP_PRO_PMS_PRO_AHB_ILG_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PMS_PRO_AHB_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_AHB_ILG_INTR_MAP_PRO_PMS_PRO_AHB_ILG_INTR_MAP_Msk = 0x1f + + // PRO_PMS_PRO_CACHE_ILG_INTR_MAP: PMS_PRO_CACHE_ILG interrupt configuration register + // Position of PRO_PMS_PRO_CACHE_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PMS_PRO_CACHE_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_Msk = 0x1f + + // PRO_PMS_DMA_APB_I_ILG_INTR_MAP: PMS_DMA_APB_I_ILG interrupt configuration register + // Position of PRO_PMS_DMA_APB_I_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PMS_DMA_APB_I_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_Msk = 0x1f + + // PRO_PMS_DMA_RX_I_ILG_INTR_MAP: PMS_DMA_RX_I_ILG interrupt configuration register + // Position of PRO_PMS_DMA_RX_I_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PMS_DMA_RX_I_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_Msk = 0x1f + + // PRO_PMS_DMA_TX_I_ILG_INTR_MAP: PMS_DMA_TX_I_ILG interrupt configuration register + // Position of PRO_PMS_DMA_TX_I_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_PMS_DMA_TX_I_ILG_INTR_MAP field. + INTERRUPT_CORE0_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_Msk = 0x1f + + // PRO_SPI_MEM_REJECT_INTR_MAP: SPI_MEM_REJECT_INTR interrupt configuration register + // Position of PRO_SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE0_PRO_SPI_MEM_REJECT_INTR_MAP_PRO_SPI_MEM_REJECT_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE0_PRO_SPI_MEM_REJECT_INTR_MAP_PRO_SPI_MEM_REJECT_INTR_MAP_Msk = 0x1f + + // PRO_DMA_COPY_INTR_MAP: DMA_COPY_INTR interrupt configuration register + // Position of PRO_DMA_COPY_INTR_MAP field. + INTERRUPT_CORE0_PRO_DMA_COPY_INTR_MAP_PRO_DMA_COPY_INTR_MAP_Pos = 0x0 + // Bit mask of PRO_DMA_COPY_INTR_MAP field. + INTERRUPT_CORE0_PRO_DMA_COPY_INTR_MAP_PRO_DMA_COPY_INTR_MAP_Msk = 0x1f + + // PRO_SPI4_DMA_INT_MAP: SPI4_DMA_INT interrupt configuration register + // Position of PRO_SPI4_DMA_INT_MAP field. + INTERRUPT_CORE0_PRO_SPI4_DMA_INT_MAP_PRO_SPI4_DMA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_SPI4_DMA_INT_MAP field. + INTERRUPT_CORE0_PRO_SPI4_DMA_INT_MAP_PRO_SPI4_DMA_INT_MAP_Msk = 0x1f + + // PRO_SPI_INTR_4_MAP: SPI_INTR_4 interrupt configuration register + // Position of PRO_SPI_INTR_4_MAP field. + INTERRUPT_CORE0_PRO_SPI_INTR_4_MAP_PRO_SPI_INTR_4_MAP_Pos = 0x0 + // Bit mask of PRO_SPI_INTR_4_MAP field. + INTERRUPT_CORE0_PRO_SPI_INTR_4_MAP_PRO_SPI_INTR_4_MAP_Msk = 0x1f + + // PRO_DCACHE_PRELOAD_INT_MAP: DCACHE_PRELOAD_INT interrupt configuration register + // Position of PRO_DCACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_PRO_DCACHE_PRELOAD_INT_MAP_PRO_DCACHE_PRELOAD_INT_MAP_Pos = 0x0 + // Bit mask of PRO_DCACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_PRO_DCACHE_PRELOAD_INT_MAP_PRO_DCACHE_PRELOAD_INT_MAP_Msk = 0x1f + + // PRO_ICACHE_PRELOAD_INT_MAP: ICACHE_PRELOAD_INT interrupt configuration register + // Position of PRO_ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_PRO_ICACHE_PRELOAD_INT_MAP_PRO_ICACHE_PRELOAD_INT_MAP_Pos = 0x0 + // Bit mask of PRO_ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_PRO_ICACHE_PRELOAD_INT_MAP_PRO_ICACHE_PRELOAD_INT_MAP_Msk = 0x1f + + // PRO_APB_ADC_INT_MAP: APB_ADC_INT interrupt configuration register + // Position of PRO_APB_ADC_INT_MAP field. + INTERRUPT_CORE0_PRO_APB_ADC_INT_MAP_PRO_APB_ADC_INT_MAP_Pos = 0x0 + // Bit mask of PRO_APB_ADC_INT_MAP field. + INTERRUPT_CORE0_PRO_APB_ADC_INT_MAP_PRO_APB_ADC_INT_MAP_Msk = 0x1f + + // PRO_CRYPTO_DMA_INT_MAP: CRYPTO_DMA_INT interrupt configuration register + // Position of PRO_CRYPTO_DMA_INT_MAP field. + INTERRUPT_CORE0_PRO_CRYPTO_DMA_INT_MAP_PRO_CRYPTO_DMA_INT_MAP_Pos = 0x0 + // Bit mask of PRO_CRYPTO_DMA_INT_MAP field. + INTERRUPT_CORE0_PRO_CRYPTO_DMA_INT_MAP_PRO_CRYPTO_DMA_INT_MAP_Msk = 0x1f + + // PRO_CPU_PERI_ERROR_INT_MAP: CPU_PERI_ERROR_INT interrupt configuration register + // Position of PRO_CPU_PERI_ERROR_INT_MAP field. + INTERRUPT_CORE0_PRO_CPU_PERI_ERROR_INT_MAP_PRO_CPU_PERI_ERROR_INT_MAP_Pos = 0x0 + // Bit mask of PRO_CPU_PERI_ERROR_INT_MAP field. + INTERRUPT_CORE0_PRO_CPU_PERI_ERROR_INT_MAP_PRO_CPU_PERI_ERROR_INT_MAP_Msk = 0x1f + + // PRO_APB_PERI_ERROR_INT_MAP: APB_PERI_ERROR_INT interrupt configuration register + // Position of PRO_APB_PERI_ERROR_INT_MAP field. + INTERRUPT_CORE0_PRO_APB_PERI_ERROR_INT_MAP_PRO_APB_PERI_ERROR_INT_MAP_Pos = 0x0 + // Bit mask of PRO_APB_PERI_ERROR_INT_MAP field. + INTERRUPT_CORE0_PRO_APB_PERI_ERROR_INT_MAP_PRO_APB_PERI_ERROR_INT_MAP_Msk = 0x1f + + // PRO_DCACHE_SYNC_INT_MAP: DCACHE_SYNC_INT interrupt configuration register + // Position of PRO_DCACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_PRO_DCACHE_SYNC_INT_MAP_PRO_DCACHE_SYNC_INT_MAP_Pos = 0x0 + // Bit mask of PRO_DCACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_PRO_DCACHE_SYNC_INT_MAP_PRO_DCACHE_SYNC_INT_MAP_Msk = 0x1f + + // PRO_ICACHE_SYNC_INT_MAP: ICACHE_SYNC_INT interrupt configuration register + // Position of PRO_ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_PRO_ICACHE_SYNC_INT_MAP_PRO_ICACHE_SYNC_INT_MAP_Pos = 0x0 + // Bit mask of PRO_ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_PRO_ICACHE_SYNC_INT_MAP_PRO_ICACHE_SYNC_INT_MAP_Msk = 0x1f + + // PRO_INTR_STATUS_0: Interrupt status register 0 + // Position of PRO_INTR_STATUS_0 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_0_PRO_INTR_STATUS_0_Pos = 0x0 + // Bit mask of PRO_INTR_STATUS_0 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_0_PRO_INTR_STATUS_0_Msk = 0xffffffff + + // PRO_INTR_STATUS_1: Interrupt status register 1 + // Position of PRO_INTR_STATUS_1 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_1_PRO_INTR_STATUS_1_Pos = 0x0 + // Bit mask of PRO_INTR_STATUS_1 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_1_PRO_INTR_STATUS_1_Msk = 0xffffffff + + // PRO_INTR_STATUS_2: Interrupt status register 2 + // Position of PRO_INTR_STATUS_2 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_2_PRO_INTR_STATUS_2_Pos = 0x0 + // Bit mask of PRO_INTR_STATUS_2 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_2_PRO_INTR_STATUS_2_Msk = 0xffffffff + + // CLOCK_GATE: NMI interrupt signals mask register + // Position of CLK_EN field. + INTERRUPT_CORE0_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + INTERRUPT_CORE0_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + INTERRUPT_CORE0_CLOCK_GATE_CLK_EN = 0x1 + // Position of PRO_NMI_MASK_HW field. + INTERRUPT_CORE0_CLOCK_GATE_PRO_NMI_MASK_HW_Pos = 0x1 + // Bit mask of PRO_NMI_MASK_HW field. + INTERRUPT_CORE0_CLOCK_GATE_PRO_NMI_MASK_HW_Msk = 0x2 + // Bit PRO_NMI_MASK_HW. + INTERRUPT_CORE0_CLOCK_GATE_PRO_NMI_MASK_HW = 0x2 + + // REG_DATE: Version control register + // Position of INTERRUPT_REG_DATE field. + INTERRUPT_CORE0_REG_DATE_INTERRUPT_REG_DATE_Pos = 0x0 + // Bit mask of INTERRUPT_REG_DATE field. + INTERRUPT_CORE0_REG_DATE_INTERRUPT_REG_DATE_Msk = 0xfffffff +) + +// Constants for IO_MUX: Input/Output Multiplexer +const ( + // PIN_CTRL: Clock output configuration register + // Position of PIN_CLK_OUT1 field. + IO_MUX_PIN_CTRL_PIN_CLK_OUT1_Pos = 0x0 + // Bit mask of PIN_CLK_OUT1 field. + IO_MUX_PIN_CTRL_PIN_CLK_OUT1_Msk = 0xf + // Position of PIN_CLK_OUT2 field. + IO_MUX_PIN_CTRL_PIN_CLK_OUT2_Pos = 0x4 + // Bit mask of PIN_CLK_OUT2 field. + IO_MUX_PIN_CTRL_PIN_CLK_OUT2_Msk = 0xf0 + // Position of PIN_CLK_OUT3 field. + IO_MUX_PIN_CTRL_PIN_CLK_OUT3_Pos = 0x8 + // Bit mask of PIN_CLK_OUT3 field. + IO_MUX_PIN_CTRL_PIN_CLK_OUT3_Msk = 0xf00 + // Position of SWITCH_PRT_NUM field. + IO_MUX_PIN_CTRL_SWITCH_PRT_NUM_Pos = 0xc + // Bit mask of SWITCH_PRT_NUM field. + IO_MUX_PIN_CTRL_SWITCH_PRT_NUM_Msk = 0x7000 + // Position of PAD_POWER_CTRL field. + IO_MUX_PIN_CTRL_PAD_POWER_CTRL_Pos = 0xf + // Bit mask of PAD_POWER_CTRL field. + IO_MUX_PIN_CTRL_PAD_POWER_CTRL_Msk = 0x8000 + // Bit PAD_POWER_CTRL. + IO_MUX_PIN_CTRL_PAD_POWER_CTRL = 0x8000 + + // GPIO0: Configuration register for pin GPIO0 + // Position of MCU_OE field. + IO_MUX_GPIO0_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO0_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO0_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO0_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO0_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO0_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO0_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO0_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO0_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO0_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO0_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO0_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO0_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO0_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO0_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO0_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO0_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO0_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO0_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO0_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO0_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO0_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO0_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO0_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO0_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO0_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO0_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO0_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO0_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO0_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO0_FILTER_EN = 0x8000 + + // GPIO1: Configuration register for pin GPIO1 + // Position of MCU_OE field. + IO_MUX_GPIO1_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO1_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO1_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO1_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO1_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO1_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO1_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO1_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO1_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO1_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO1_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO1_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO1_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO1_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO1_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO1_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO1_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO1_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO1_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO1_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO1_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO1_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO1_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO1_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO1_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO1_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO1_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO1_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO1_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO1_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO1_FILTER_EN = 0x8000 + + // GPIO2: Configuration register for pin GPIO2 + // Position of MCU_OE field. + IO_MUX_GPIO2_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO2_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO2_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO2_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO2_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO2_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO2_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO2_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO2_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO2_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO2_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO2_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO2_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO2_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO2_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO2_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO2_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO2_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO2_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO2_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO2_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO2_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO2_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO2_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO2_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO2_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO2_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO2_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO2_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO2_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO2_FILTER_EN = 0x8000 + + // GPIO3: Configuration register for pin GPIO3 + // Position of MCU_OE field. + IO_MUX_GPIO3_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO3_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO3_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO3_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO3_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO3_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO3_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO3_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO3_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO3_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO3_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO3_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO3_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO3_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO3_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO3_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO3_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO3_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO3_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO3_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO3_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO3_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO3_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO3_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO3_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO3_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO3_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO3_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO3_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO3_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO3_FILTER_EN = 0x8000 + + // GPIO4: Configuration register for pin GPIO4 + // Position of MCU_OE field. + IO_MUX_GPIO4_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO4_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO4_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO4_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO4_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO4_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO4_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO4_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO4_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO4_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO4_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO4_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO4_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO4_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO4_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO4_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO4_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO4_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO4_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO4_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO4_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO4_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO4_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO4_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO4_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO4_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO4_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO4_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO4_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO4_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO4_FILTER_EN = 0x8000 + + // GPIO5: Configuration register for pin GPIO5 + // Position of MCU_OE field. + IO_MUX_GPIO5_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO5_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO5_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO5_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO5_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO5_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO5_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO5_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO5_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO5_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO5_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO5_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO5_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO5_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO5_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO5_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO5_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO5_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO5_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO5_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO5_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO5_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO5_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO5_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO5_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO5_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO5_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO5_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO5_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO5_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO5_FILTER_EN = 0x8000 + + // GPIO6: Configuration register for pin GPIO6 + // Position of MCU_OE field. + IO_MUX_GPIO6_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO6_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO6_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO6_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO6_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO6_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO6_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO6_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO6_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO6_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO6_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO6_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO6_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO6_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO6_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO6_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO6_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO6_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO6_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO6_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO6_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO6_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO6_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO6_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO6_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO6_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO6_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO6_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO6_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO6_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO6_FILTER_EN = 0x8000 + + // GPIO7: Configuration register for pin GPIO7 + // Position of MCU_OE field. + IO_MUX_GPIO7_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO7_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO7_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO7_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO7_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO7_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO7_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO7_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO7_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO7_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO7_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO7_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO7_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO7_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO7_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO7_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO7_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO7_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO7_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO7_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO7_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO7_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO7_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO7_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO7_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO7_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO7_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO7_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO7_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO7_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO7_FILTER_EN = 0x8000 + + // GPIO8: Configuration register for pin GPIO8 + // Position of MCU_OE field. + IO_MUX_GPIO8_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO8_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO8_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO8_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO8_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO8_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO8_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO8_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO8_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO8_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO8_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO8_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO8_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO8_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO8_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO8_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO8_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO8_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO8_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO8_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO8_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO8_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO8_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO8_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO8_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO8_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO8_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO8_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO8_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO8_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO8_FILTER_EN = 0x8000 + + // GPIO9: Configuration register for pin GPIO9 + // Position of MCU_OE field. + IO_MUX_GPIO9_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO9_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO9_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO9_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO9_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO9_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO9_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO9_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO9_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO9_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO9_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO9_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO9_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO9_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO9_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO9_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO9_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO9_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO9_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO9_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO9_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO9_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO9_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO9_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO9_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO9_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO9_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO9_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO9_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO9_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO9_FILTER_EN = 0x8000 + + // GPIO10: Configuration register for pin GPIO10 + // Position of MCU_OE field. + IO_MUX_GPIO10_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO10_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO10_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO10_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO10_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO10_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO10_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO10_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO10_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO10_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO10_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO10_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO10_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO10_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO10_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO10_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO10_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO10_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO10_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO10_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO10_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO10_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO10_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO10_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO10_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO10_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO10_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO10_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO10_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO10_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO10_FILTER_EN = 0x8000 + + // GPIO11: Configuration register for pin GPIO11 + // Position of MCU_OE field. + IO_MUX_GPIO11_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO11_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO11_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO11_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO11_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO11_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO11_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO11_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO11_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO11_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO11_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO11_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO11_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO11_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO11_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO11_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO11_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO11_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO11_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO11_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO11_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO11_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO11_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO11_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO11_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO11_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO11_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO11_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO11_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO11_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO11_FILTER_EN = 0x8000 + + // GPIO12: Configuration register for pin GPIO12 + // Position of MCU_OE field. + IO_MUX_GPIO12_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO12_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO12_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO12_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO12_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO12_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO12_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO12_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO12_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO12_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO12_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO12_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO12_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO12_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO12_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO12_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO12_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO12_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO12_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO12_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO12_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO12_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO12_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO12_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO12_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO12_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO12_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO12_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO12_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO12_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO12_FILTER_EN = 0x8000 + + // GPIO13: Configuration register for pin GPIO13 + // Position of MCU_OE field. + IO_MUX_GPIO13_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO13_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO13_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO13_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO13_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO13_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO13_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO13_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO13_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO13_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO13_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO13_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO13_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO13_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO13_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO13_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO13_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO13_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO13_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO13_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO13_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO13_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO13_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO13_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO13_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO13_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO13_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO13_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO13_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO13_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO13_FILTER_EN = 0x8000 + + // GPIO14: Configuration register for pin GPIO14 + // Position of MCU_OE field. + IO_MUX_GPIO14_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO14_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO14_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO14_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO14_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO14_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO14_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO14_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO14_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO14_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO14_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO14_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO14_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO14_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO14_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO14_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO14_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO14_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO14_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO14_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO14_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO14_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO14_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO14_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO14_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO14_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO14_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO14_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO14_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO14_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO14_FILTER_EN = 0x8000 + + // GPIO15: Configuration register for pin GPIO15 + // Position of MCU_OE field. + IO_MUX_GPIO15_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO15_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO15_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO15_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO15_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO15_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO15_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO15_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO15_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO15_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO15_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO15_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO15_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO15_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO15_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO15_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO15_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO15_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO15_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO15_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO15_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO15_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO15_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO15_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO15_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO15_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO15_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO15_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO15_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO15_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO15_FILTER_EN = 0x8000 + + // GPIO16: Configuration register for pin GPIO16 + // Position of MCU_OE field. + IO_MUX_GPIO16_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO16_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO16_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO16_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO16_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO16_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO16_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO16_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO16_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO16_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO16_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO16_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO16_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO16_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO16_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO16_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO16_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO16_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO16_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO16_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO16_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO16_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO16_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO16_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO16_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO16_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO16_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO16_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO16_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO16_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO16_FILTER_EN = 0x8000 + + // GPIO17: Configuration register for pin GPIO17 + // Position of MCU_OE field. + IO_MUX_GPIO17_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO17_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO17_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO17_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO17_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO17_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO17_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO17_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO17_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO17_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO17_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO17_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO17_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO17_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO17_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO17_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO17_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO17_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO17_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO17_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO17_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO17_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO17_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO17_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO17_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO17_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO17_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO17_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO17_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO17_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO17_FILTER_EN = 0x8000 + + // GPIO18: Configuration register for pin GPIO18 + // Position of MCU_OE field. + IO_MUX_GPIO18_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO18_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO18_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO18_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO18_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO18_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO18_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO18_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO18_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO18_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO18_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO18_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO18_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO18_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO18_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO18_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO18_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO18_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO18_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO18_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO18_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO18_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO18_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO18_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO18_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO18_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO18_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO18_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO18_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO18_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO18_FILTER_EN = 0x8000 + + // GPIO19: Configuration register for pin GPIO19 + // Position of MCU_OE field. + IO_MUX_GPIO19_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO19_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO19_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO19_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO19_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO19_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO19_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO19_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO19_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO19_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO19_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO19_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO19_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO19_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO19_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO19_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO19_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO19_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO19_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO19_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO19_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO19_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO19_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO19_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO19_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO19_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO19_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO19_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO19_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO19_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO19_FILTER_EN = 0x8000 + + // GPIO20: Configuration register for pin GPIO20 + // Position of MCU_OE field. + IO_MUX_GPIO20_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO20_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO20_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO20_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO20_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO20_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO20_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO20_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO20_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO20_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO20_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO20_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO20_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO20_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO20_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO20_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO20_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO20_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO20_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO20_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO20_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO20_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO20_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO20_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO20_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO20_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO20_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO20_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO20_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO20_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO20_FILTER_EN = 0x8000 + + // GPIO21: Configuration register for pin GPIO21 + // Position of MCU_OE field. + IO_MUX_GPIO21_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO21_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO21_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO21_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO21_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO21_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO21_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO21_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO21_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO21_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO21_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO21_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO21_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO21_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO21_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO21_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO21_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO21_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO21_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO21_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO21_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO21_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO21_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO21_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO21_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO21_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO21_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO21_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO21_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO21_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO21_FILTER_EN = 0x8000 + + // GPIO26: Configuration register for pin GPIO26 + // Position of MCU_OE field. + IO_MUX_GPIO26_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO26_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO26_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO26_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO26_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO26_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO26_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO26_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO26_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO26_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO26_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO26_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO26_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO26_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO26_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO26_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO26_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO26_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO26_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO26_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO26_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO26_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO26_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO26_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO26_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO26_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO26_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO26_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO26_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO26_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO26_FILTER_EN = 0x8000 + + // GPIO27: Configuration register for pin GPIO27 + // Position of MCU_OE field. + IO_MUX_GPIO27_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO27_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO27_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO27_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO27_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO27_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO27_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO27_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO27_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO27_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO27_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO27_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO27_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO27_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO27_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO27_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO27_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO27_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO27_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO27_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO27_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO27_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO27_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO27_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO27_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO27_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO27_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO27_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO27_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO27_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO27_FILTER_EN = 0x8000 + + // GPIO28: Configuration register for pin GPIO28 + // Position of MCU_OE field. + IO_MUX_GPIO28_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO28_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO28_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO28_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO28_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO28_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO28_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO28_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO28_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO28_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO28_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO28_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO28_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO28_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO28_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO28_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO28_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO28_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO28_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO28_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO28_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO28_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO28_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO28_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO28_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO28_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO28_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO28_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO28_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO28_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO28_FILTER_EN = 0x8000 + + // GPIO29: Configuration register for pin GPIO29 + // Position of MCU_OE field. + IO_MUX_GPIO29_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO29_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO29_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO29_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO29_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO29_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO29_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO29_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO29_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO29_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO29_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO29_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO29_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO29_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO29_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO29_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO29_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO29_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO29_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO29_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO29_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO29_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO29_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO29_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO29_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO29_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO29_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO29_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO29_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO29_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO29_FILTER_EN = 0x8000 + + // GPIO30: Configuration register for pin GPIO30 + // Position of MCU_OE field. + IO_MUX_GPIO30_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO30_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO30_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO30_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO30_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO30_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO30_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO30_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO30_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO30_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO30_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO30_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO30_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO30_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO30_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO30_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO30_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO30_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO30_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO30_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO30_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO30_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO30_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO30_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO30_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO30_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO30_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO30_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO30_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO30_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO30_FILTER_EN = 0x8000 + + // GPIO31: Configuration register for pin GPIO31 + // Position of MCU_OE field. + IO_MUX_GPIO31_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO31_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO31_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO31_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO31_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO31_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO31_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO31_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO31_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO31_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO31_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO31_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO31_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO31_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO31_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO31_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO31_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO31_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO31_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO31_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO31_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO31_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO31_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO31_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO31_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO31_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO31_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO31_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO31_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO31_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO31_FILTER_EN = 0x8000 + + // GPIO32: Configuration register for pin GPIO32 + // Position of MCU_OE field. + IO_MUX_GPIO32_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO32_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO32_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO32_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO32_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO32_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO32_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO32_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO32_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO32_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO32_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO32_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO32_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO32_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO32_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO32_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO32_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO32_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO32_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO32_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO32_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO32_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO32_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO32_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO32_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO32_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO32_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO32_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO32_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO32_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO32_FILTER_EN = 0x8000 + + // GPIO33: Configuration register for pin GPIO33 + // Position of MCU_OE field. + IO_MUX_GPIO33_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO33_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO33_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO33_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO33_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO33_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO33_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO33_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO33_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO33_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO33_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO33_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO33_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO33_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO33_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO33_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO33_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO33_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO33_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO33_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO33_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO33_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO33_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO33_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO33_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO33_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO33_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO33_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO33_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO33_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO33_FILTER_EN = 0x8000 + + // GPIO34: Configuration register for pin GPIO34 + // Position of MCU_OE field. + IO_MUX_GPIO34_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO34_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO34_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO34_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO34_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO34_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO34_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO34_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO34_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO34_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO34_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO34_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO34_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO34_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO34_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO34_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO34_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO34_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO34_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO34_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO34_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO34_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO34_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO34_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO34_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO34_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO34_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO34_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO34_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO34_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO34_FILTER_EN = 0x8000 + + // GPIO35: Configuration register for pin GPIO35 + // Position of MCU_OE field. + IO_MUX_GPIO35_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO35_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO35_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO35_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO35_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO35_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO35_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO35_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO35_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO35_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO35_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO35_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO35_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO35_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO35_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO35_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO35_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO35_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO35_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO35_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO35_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO35_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO35_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO35_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO35_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO35_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO35_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO35_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO35_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO35_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO35_FILTER_EN = 0x8000 + + // GPIO36: Configuration register for pin GPIO36 + // Position of MCU_OE field. + IO_MUX_GPIO36_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO36_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO36_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO36_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO36_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO36_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO36_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO36_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO36_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO36_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO36_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO36_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO36_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO36_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO36_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO36_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO36_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO36_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO36_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO36_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO36_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO36_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO36_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO36_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO36_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO36_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO36_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO36_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO36_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO36_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO36_FILTER_EN = 0x8000 + + // GPIO37: Configuration register for pin GPIO37 + // Position of MCU_OE field. + IO_MUX_GPIO37_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO37_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO37_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO37_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO37_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO37_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO37_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO37_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO37_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO37_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO37_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO37_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO37_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO37_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO37_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO37_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO37_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO37_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO37_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO37_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO37_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO37_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO37_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO37_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO37_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO37_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO37_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO37_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO37_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO37_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO37_FILTER_EN = 0x8000 + + // GPIO38: Configuration register for pin GPIO38 + // Position of MCU_OE field. + IO_MUX_GPIO38_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO38_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO38_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO38_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO38_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO38_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO38_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO38_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO38_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO38_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO38_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO38_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO38_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO38_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO38_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO38_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO38_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO38_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO38_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO38_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO38_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO38_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO38_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO38_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO38_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO38_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO38_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO38_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO38_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO38_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO38_FILTER_EN = 0x8000 + + // GPIO39: Configuration register for pin GPIO39 + // Position of MCU_OE field. + IO_MUX_GPIO39_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO39_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO39_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO39_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO39_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO39_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO39_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO39_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO39_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO39_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO39_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO39_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO39_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO39_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO39_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO39_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO39_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO39_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO39_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO39_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO39_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO39_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO39_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO39_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO39_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO39_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO39_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO39_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO39_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO39_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO39_FILTER_EN = 0x8000 + + // GPIO40: Configuration register for pin GPIO40 + // Position of MCU_OE field. + IO_MUX_GPIO40_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO40_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO40_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO40_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO40_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO40_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO40_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO40_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO40_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO40_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO40_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO40_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO40_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO40_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO40_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO40_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO40_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO40_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO40_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO40_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO40_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO40_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO40_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO40_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO40_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO40_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO40_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO40_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO40_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO40_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO40_FILTER_EN = 0x8000 + + // GPIO41: Configuration register for pin GPIO41 + // Position of MCU_OE field. + IO_MUX_GPIO41_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO41_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO41_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO41_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO41_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO41_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO41_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO41_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO41_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO41_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO41_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO41_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO41_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO41_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO41_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO41_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO41_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO41_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO41_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO41_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO41_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO41_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO41_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO41_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO41_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO41_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO41_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO41_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO41_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO41_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO41_FILTER_EN = 0x8000 + + // GPIO42: Configuration register for pin GPIO42 + // Position of MCU_OE field. + IO_MUX_GPIO42_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO42_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO42_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO42_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO42_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO42_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO42_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO42_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO42_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO42_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO42_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO42_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO42_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO42_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO42_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO42_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO42_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO42_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO42_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO42_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO42_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO42_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO42_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO42_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO42_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO42_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO42_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO42_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO42_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO42_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO42_FILTER_EN = 0x8000 + + // GPIO43: Configuration register for pin GPIO43 + // Position of MCU_OE field. + IO_MUX_GPIO43_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO43_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO43_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO43_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO43_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO43_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO43_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO43_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO43_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO43_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO43_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO43_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO43_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO43_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO43_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO43_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO43_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO43_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO43_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO43_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO43_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO43_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO43_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO43_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO43_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO43_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO43_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO43_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO43_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO43_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO43_FILTER_EN = 0x8000 + + // GPIO44: Configuration register for pin GPIO44 + // Position of MCU_OE field. + IO_MUX_GPIO44_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO44_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO44_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO44_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO44_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO44_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO44_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO44_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO44_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO44_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO44_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO44_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO44_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO44_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO44_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO44_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO44_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO44_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO44_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO44_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO44_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO44_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO44_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO44_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO44_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO44_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO44_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO44_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO44_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO44_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO44_FILTER_EN = 0x8000 + + // GPIO45: Configuration register for pin GPIO45 + // Position of MCU_OE field. + IO_MUX_GPIO45_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO45_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO45_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO45_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO45_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO45_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO45_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO45_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO45_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO45_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO45_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO45_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO45_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO45_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO45_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO45_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO45_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO45_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO45_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO45_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO45_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO45_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO45_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO45_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO45_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO45_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO45_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO45_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO45_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO45_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO45_FILTER_EN = 0x8000 + + // GPIO46: Configuration register for pin GPIO46 + // Position of MCU_OE field. + IO_MUX_GPIO46_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO46_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO46_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO46_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO46_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO46_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO46_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO46_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO46_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO46_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO46_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO46_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO46_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO46_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO46_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO46_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO46_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO46_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO46_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO46_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO46_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO46_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO46_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO46_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO46_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO46_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO46_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO46_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO46_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO46_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO46_FILTER_EN = 0x8000 + + // DATE: Version control register + // Position of VERSION field. + IO_MUX_DATE_VERSION_Pos = 0x0 + // Bit mask of VERSION field. + IO_MUX_DATE_VERSION_Msk = 0xfffffff +) + +// Constants for LEDC: LED Control PWM (Pulse Width Modulation) +const ( + // CH0_CONF0: Configuration register 0 for channel %s + // Position of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Pos = 0x0 + // Bit mask of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Msk = 0x3 + // Position of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Pos = 0x2 + // Bit mask of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Msk = 0x4 + // Bit SIG_OUT_EN. + LEDC_CH_CONF0_SIG_OUT_EN = 0x4 + // Position of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Pos = 0x3 + // Bit mask of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Msk = 0x8 + // Bit IDLE_LV. + LEDC_CH_CONF0_IDLE_LV = 0x8 + // Position of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Pos = 0x4 + // Bit mask of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Msk = 0x10 + // Bit PARA_UP. + LEDC_CH_CONF0_PARA_UP = 0x10 + // Position of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Pos = 0x5 + // Bit mask of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Msk = 0x7fe0 + // Position of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Pos = 0xf + // Bit mask of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Msk = 0x8000 + // Bit OVF_CNT_EN. + LEDC_CH_CONF0_OVF_CNT_EN = 0x8000 + // Position of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Pos = 0x10 + // Bit mask of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Msk = 0x10000 + // Bit OVF_CNT_RESET. + LEDC_CH_CONF0_OVF_CNT_RESET = 0x10000 + // Position of OVF_CNT_RESET_ST field. + LEDC_CH_CONF0_OVF_CNT_RESET_ST_Pos = 0x11 + // Bit mask of OVF_CNT_RESET_ST field. + LEDC_CH_CONF0_OVF_CNT_RESET_ST_Msk = 0x20000 + // Bit OVF_CNT_RESET_ST. + LEDC_CH_CONF0_OVF_CNT_RESET_ST = 0x20000 + + // CH0_HPOINT: High point register for channel %s + // Position of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Pos = 0x0 + // Bit mask of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Msk = 0x3fff + + // CH0_DUTY: Initial duty cycle for channel %s + // Position of DUTY field. + LEDC_CH_DUTY_DUTY_Pos = 0x0 + // Bit mask of DUTY field. + LEDC_CH_DUTY_DUTY_Msk = 0x7ffff + + // CH0_CONF1: Configuration register 1 for channel %s + // Position of DUTY_SCALE field. + LEDC_CH_CONF1_DUTY_SCALE_Pos = 0x0 + // Bit mask of DUTY_SCALE field. + LEDC_CH_CONF1_DUTY_SCALE_Msk = 0x3ff + // Position of DUTY_CYCLE field. + LEDC_CH_CONF1_DUTY_CYCLE_Pos = 0xa + // Bit mask of DUTY_CYCLE field. + LEDC_CH_CONF1_DUTY_CYCLE_Msk = 0xffc00 + // Position of DUTY_NUM field. + LEDC_CH_CONF1_DUTY_NUM_Pos = 0x14 + // Bit mask of DUTY_NUM field. + LEDC_CH_CONF1_DUTY_NUM_Msk = 0x3ff00000 + // Position of DUTY_INC field. + LEDC_CH_CONF1_DUTY_INC_Pos = 0x1e + // Bit mask of DUTY_INC field. + LEDC_CH_CONF1_DUTY_INC_Msk = 0x40000000 + // Bit DUTY_INC. + LEDC_CH_CONF1_DUTY_INC = 0x40000000 + // Position of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Pos = 0x1f + // Bit mask of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Msk = 0x80000000 + // Bit DUTY_START. + LEDC_CH_CONF1_DUTY_START = 0x80000000 + + // CH0_DUTY_R: Current duty cycle for channel %s + // Position of DUTY_R field. + LEDC_CH_DUTY_R_DUTY_R_Pos = 0x0 + // Bit mask of DUTY_R field. + LEDC_CH_DUTY_R_DUTY_R_Msk = 0x7ffff + + // TIMER0_CONF: Timer %s configuration + // Position of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Pos = 0x0 + // Bit mask of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Msk = 0xf + // Position of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Pos = 0x4 + // Bit mask of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Msk = 0x3ffff0 + // Position of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Pos = 0x16 + // Bit mask of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Msk = 0x400000 + // Bit PAUSE. + LEDC_TIMER_CONF_PAUSE = 0x400000 + // Position of RST field. + LEDC_TIMER_CONF_RST_Pos = 0x17 + // Bit mask of RST field. + LEDC_TIMER_CONF_RST_Msk = 0x800000 + // Bit RST. + LEDC_TIMER_CONF_RST = 0x800000 + // Position of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Pos = 0x18 + // Bit mask of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Msk = 0x1000000 + // Bit TICK_SEL. + LEDC_TIMER_CONF_TICK_SEL = 0x1000000 + // Position of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Pos = 0x19 + // Bit mask of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Msk = 0x2000000 + // Bit PARA_UP. + LEDC_TIMER_CONF_PARA_UP = 0x2000000 + + // TIMER0_VALUE: Timer %s current counter value + // Position of CNT field. + LEDC_TIMER_VALUE_CNT_Pos = 0x0 + // Bit mask of CNT field. + LEDC_TIMER_VALUE_CNT_Msk = 0x3fff + + // INT_RAW: Raw interrupt status + // Position of TIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Msk = 0x1 + // Bit TIMER0_OVF_INT_RAW. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW = 0x1 + // Position of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Msk = 0x2 + // Bit TIMER1_OVF_INT_RAW. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW = 0x2 + // Position of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Msk = 0x4 + // Bit TIMER2_OVF_INT_RAW. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW = 0x4 + // Position of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Msk = 0x8 + // Bit TIMER3_OVF_INT_RAW. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW = 0x200 + // Position of DUTY_CHNG_END_CH6_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH6_INT_RAW_Pos = 0xa + // Bit mask of DUTY_CHNG_END_CH6_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH6_INT_RAW_Msk = 0x400 + // Bit DUTY_CHNG_END_CH6_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH6_INT_RAW = 0x400 + // Position of DUTY_CHNG_END_CH7_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH7_INT_RAW_Pos = 0xb + // Bit mask of DUTY_CHNG_END_CH7_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH7_INT_RAW_Msk = 0x800 + // Bit DUTY_CHNG_END_CH7_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH7_INT_RAW = 0x800 + // Position of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW = 0x1000 + // Position of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW = 0x2000 + // Position of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW = 0x4000 + // Position of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW = 0x8000 + // Position of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW = 0x10000 + // Position of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW = 0x20000 + // Position of OVF_CNT_CH6_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH6_INT_RAW_Pos = 0x12 + // Bit mask of OVF_CNT_CH6_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH6_INT_RAW_Msk = 0x40000 + // Bit OVF_CNT_CH6_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH6_INT_RAW = 0x40000 + // Position of OVF_CNT_CH7_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH7_INT_RAW_Pos = 0x13 + // Bit mask of OVF_CNT_CH7_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH7_INT_RAW_Msk = 0x80000 + // Bit OVF_CNT_CH7_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH7_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of TIMER0_OVF_INT_ST field. + LEDC_INT_ST_TIMER0_OVF_INT_ST_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_ST field. + LEDC_INT_ST_TIMER0_OVF_INT_ST_Msk = 0x1 + // Bit TIMER0_OVF_INT_ST. + LEDC_INT_ST_TIMER0_OVF_INT_ST = 0x1 + // Position of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Msk = 0x2 + // Bit TIMER1_OVF_INT_ST. + LEDC_INT_ST_TIMER1_OVF_INT_ST = 0x2 + // Position of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Msk = 0x4 + // Bit TIMER2_OVF_INT_ST. + LEDC_INT_ST_TIMER2_OVF_INT_ST = 0x4 + // Position of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Msk = 0x8 + // Bit TIMER3_OVF_INT_ST. + LEDC_INT_ST_TIMER3_OVF_INT_ST = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST = 0x200 + // Position of DUTY_CHNG_END_CH6_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH6_INT_ST_Pos = 0xa + // Bit mask of DUTY_CHNG_END_CH6_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH6_INT_ST_Msk = 0x400 + // Bit DUTY_CHNG_END_CH6_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH6_INT_ST = 0x400 + // Position of DUTY_CHNG_END_CH7_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH7_INT_ST_Pos = 0xb + // Bit mask of DUTY_CHNG_END_CH7_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH7_INT_ST_Msk = 0x800 + // Bit DUTY_CHNG_END_CH7_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH7_INT_ST = 0x800 + // Position of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_ST. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST = 0x1000 + // Position of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_ST. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST = 0x2000 + // Position of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_ST. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST = 0x4000 + // Position of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_ST. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST = 0x8000 + // Position of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_ST. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST = 0x10000 + // Position of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_ST. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST = 0x20000 + // Position of OVF_CNT_CH6_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH6_INT_ST_Pos = 0x12 + // Bit mask of OVF_CNT_CH6_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH6_INT_ST_Msk = 0x40000 + // Bit OVF_CNT_CH6_INT_ST. + LEDC_INT_ST_OVF_CNT_CH6_INT_ST = 0x40000 + // Position of OVF_CNT_CH7_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH7_INT_ST_Pos = 0x13 + // Bit mask of OVF_CNT_CH7_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH7_INT_ST_Msk = 0x80000 + // Bit OVF_CNT_CH7_INT_ST. + LEDC_INT_ST_OVF_CNT_CH7_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of TIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Msk = 0x1 + // Bit TIMER0_OVF_INT_ENA. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA = 0x1 + // Position of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Msk = 0x2 + // Bit TIMER1_OVF_INT_ENA. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA = 0x2 + // Position of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Msk = 0x4 + // Bit TIMER2_OVF_INT_ENA. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA = 0x4 + // Position of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Msk = 0x8 + // Bit TIMER3_OVF_INT_ENA. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA = 0x200 + // Position of DUTY_CHNG_END_CH6_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH6_INT_ENA_Pos = 0xa + // Bit mask of DUTY_CHNG_END_CH6_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH6_INT_ENA_Msk = 0x400 + // Bit DUTY_CHNG_END_CH6_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH6_INT_ENA = 0x400 + // Position of DUTY_CHNG_END_CH7_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH7_INT_ENA_Pos = 0xb + // Bit mask of DUTY_CHNG_END_CH7_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH7_INT_ENA_Msk = 0x800 + // Bit DUTY_CHNG_END_CH7_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH7_INT_ENA = 0x800 + // Position of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA = 0x1000 + // Position of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA = 0x2000 + // Position of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA = 0x4000 + // Position of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA = 0x8000 + // Position of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA = 0x10000 + // Position of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA = 0x20000 + // Position of OVF_CNT_CH6_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH6_INT_ENA_Pos = 0x12 + // Bit mask of OVF_CNT_CH6_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH6_INT_ENA_Msk = 0x40000 + // Bit OVF_CNT_CH6_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH6_INT_ENA = 0x40000 + // Position of OVF_CNT_CH7_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH7_INT_ENA_Pos = 0x13 + // Bit mask of OVF_CNT_CH7_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH7_INT_ENA_Msk = 0x80000 + // Bit OVF_CNT_CH7_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH7_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of TIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Msk = 0x1 + // Bit TIMER0_OVF_INT_CLR. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR = 0x1 + // Position of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Msk = 0x2 + // Bit TIMER1_OVF_INT_CLR. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR = 0x2 + // Position of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Msk = 0x4 + // Bit TIMER2_OVF_INT_CLR. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR = 0x4 + // Position of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Msk = 0x8 + // Bit TIMER3_OVF_INT_CLR. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR = 0x200 + // Position of DUTY_CHNG_END_CH6_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH6_INT_CLR_Pos = 0xa + // Bit mask of DUTY_CHNG_END_CH6_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH6_INT_CLR_Msk = 0x400 + // Bit DUTY_CHNG_END_CH6_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH6_INT_CLR = 0x400 + // Position of DUTY_CHNG_END_CH7_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH7_INT_CLR_Pos = 0xb + // Bit mask of DUTY_CHNG_END_CH7_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH7_INT_CLR_Msk = 0x800 + // Bit DUTY_CHNG_END_CH7_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH7_INT_CLR = 0x800 + // Position of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR = 0x1000 + // Position of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR = 0x2000 + // Position of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR = 0x4000 + // Position of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR = 0x8000 + // Position of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR = 0x10000 + // Position of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR = 0x20000 + // Position of OVF_CNT_CH6_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH6_INT_CLR_Pos = 0x12 + // Bit mask of OVF_CNT_CH6_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH6_INT_CLR_Msk = 0x40000 + // Bit OVF_CNT_CH6_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH6_INT_CLR = 0x40000 + // Position of OVF_CNT_CH7_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH7_INT_CLR_Pos = 0x13 + // Bit mask of OVF_CNT_CH7_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH7_INT_CLR_Msk = 0x80000 + // Bit OVF_CNT_CH7_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH7_INT_CLR = 0x80000 + + // CONF: Global ledc configuration register + // Position of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Pos = 0x0 + // Bit mask of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Msk = 0x3 + // Position of CLK_EN field. + LEDC_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LEDC_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LEDC_CONF_CLK_EN = 0x80000000 + + // DATE: Version control register + // Position of DATE field. + LEDC_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LEDC_DATE_DATE_Msk = 0xffffffff +) + +// Constants for PCNT: Pulse Count Controller +const ( + // U0_CONF0: Configuration register 0 for unit %s + // Position of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Pos = 0x0 + // Bit mask of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Msk = 0x3ff + // Position of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Pos = 0xa + // Bit mask of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Msk = 0x400 + // Bit FILTER_EN. + PCNT_U_CONF0_FILTER_EN = 0x400 + // Position of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Pos = 0xb + // Bit mask of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Msk = 0x800 + // Bit THR_ZERO_EN. + PCNT_U_CONF0_THR_ZERO_EN = 0x800 + // Position of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Pos = 0xc + // Bit mask of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Msk = 0x1000 + // Bit THR_H_LIM_EN. + PCNT_U_CONF0_THR_H_LIM_EN = 0x1000 + // Position of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Pos = 0xd + // Bit mask of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Msk = 0x2000 + // Bit THR_L_LIM_EN. + PCNT_U_CONF0_THR_L_LIM_EN = 0x2000 + // Position of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Pos = 0xe + // Bit mask of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Msk = 0x4000 + // Bit THR_THRES0_EN. + PCNT_U_CONF0_THR_THRES0_EN = 0x4000 + // Position of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Pos = 0xf + // Bit mask of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Msk = 0x8000 + // Bit THR_THRES1_EN. + PCNT_U_CONF0_THR_THRES1_EN = 0x8000 + // Position of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Pos = 0x10 + // Bit mask of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Msk = 0x30000 + // Position of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Pos = 0x12 + // Bit mask of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Msk = 0xc0000 + // Position of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Pos = 0x14 + // Bit mask of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Msk = 0x300000 + // Position of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Pos = 0x16 + // Bit mask of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Msk = 0xc00000 + // Position of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Pos = 0x18 + // Bit mask of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Msk = 0x3000000 + // Position of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Pos = 0x1a + // Bit mask of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Msk = 0xc000000 + // Position of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Pos = 0x1c + // Bit mask of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Msk = 0x30000000 + // Position of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Pos = 0x1e + // Bit mask of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Msk = 0xc0000000 + + // U0_CONF1: Configuration register 1 for unit %s + // Position of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Pos = 0x0 + // Bit mask of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Msk = 0xffff + // Position of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Pos = 0x10 + // Bit mask of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Msk = 0xffff0000 + + // U0_CONF2: Configuration register 2 for unit %s + // Position of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Pos = 0x0 + // Bit mask of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Msk = 0xffff + // Position of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Pos = 0x10 + // Bit mask of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Msk = 0xffff0000 + + // U0_CNT: Counter value for unit %s + // Position of CNT field. + PCNT_U_CNT_CNT_Pos = 0x0 + // Bit mask of CNT field. + PCNT_U_CNT_CNT_Msk = 0xffff + + // INT_RAW: Interrupt raw status register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_RAW_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_RAW_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_RAW_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_RAW_CNT_THR_EVENT_U3 = 0x8 + + // INT_ST: Interrupt status register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ST_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ST_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ST_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ST_CNT_THR_EVENT_U3 = 0x8 + + // INT_ENA: Interrupt enable register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ENA_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ENA_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ENA_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ENA_CNT_THR_EVENT_U3 = 0x8 + + // INT_CLR: Interrupt clear register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_CLR_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_CLR_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_CLR_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_CLR_CNT_THR_EVENT_U3 = 0x8 + + // U0_STATUS: PNCT UNIT%s status register + // Position of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Pos = 0x0 + // Bit mask of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Msk = 0x3 + // Position of THRES1 field. + PCNT_U_STATUS_THRES1_Pos = 0x2 + // Bit mask of THRES1 field. + PCNT_U_STATUS_THRES1_Msk = 0x4 + // Bit THRES1. + PCNT_U_STATUS_THRES1 = 0x4 + // Position of THRES0 field. + PCNT_U_STATUS_THRES0_Pos = 0x3 + // Bit mask of THRES0 field. + PCNT_U_STATUS_THRES0_Msk = 0x8 + // Bit THRES0. + PCNT_U_STATUS_THRES0 = 0x8 + // Position of L_LIM field. + PCNT_U_STATUS_L_LIM_Pos = 0x4 + // Bit mask of L_LIM field. + PCNT_U_STATUS_L_LIM_Msk = 0x10 + // Bit L_LIM. + PCNT_U_STATUS_L_LIM = 0x10 + // Position of H_LIM field. + PCNT_U_STATUS_H_LIM_Pos = 0x5 + // Bit mask of H_LIM field. + PCNT_U_STATUS_H_LIM_Msk = 0x20 + // Bit H_LIM. + PCNT_U_STATUS_H_LIM = 0x20 + // Position of ZERO field. + PCNT_U_STATUS_ZERO_Pos = 0x6 + // Bit mask of ZERO field. + PCNT_U_STATUS_ZERO_Msk = 0x40 + // Bit ZERO. + PCNT_U_STATUS_ZERO = 0x40 + + // CTRL: Control register for all counters + // Position of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Pos = 0x0 + // Bit mask of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Msk = 0x1 + // Bit CNT_RST_U0. + PCNT_CTRL_CNT_RST_U0 = 0x1 + // Position of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Pos = 0x1 + // Bit mask of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Msk = 0x2 + // Bit CNT_PAUSE_U0. + PCNT_CTRL_CNT_PAUSE_U0 = 0x2 + // Position of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Pos = 0x2 + // Bit mask of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Msk = 0x4 + // Bit CNT_RST_U1. + PCNT_CTRL_CNT_RST_U1 = 0x4 + // Position of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Pos = 0x3 + // Bit mask of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Msk = 0x8 + // Bit CNT_PAUSE_U1. + PCNT_CTRL_CNT_PAUSE_U1 = 0x8 + // Position of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Pos = 0x4 + // Bit mask of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Msk = 0x10 + // Bit CNT_RST_U2. + PCNT_CTRL_CNT_RST_U2 = 0x10 + // Position of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Pos = 0x5 + // Bit mask of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Msk = 0x20 + // Bit CNT_PAUSE_U2. + PCNT_CTRL_CNT_PAUSE_U2 = 0x20 + // Position of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Pos = 0x6 + // Bit mask of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Msk = 0x40 + // Bit CNT_RST_U3. + PCNT_CTRL_CNT_RST_U3 = 0x40 + // Position of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Pos = 0x7 + // Bit mask of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Msk = 0x80 + // Bit CNT_PAUSE_U3. + PCNT_CTRL_CNT_PAUSE_U3 = 0x80 + // Position of CLK_EN field. + PCNT_CTRL_CLK_EN_Pos = 0x10 + // Bit mask of CLK_EN field. + PCNT_CTRL_CLK_EN_Msk = 0x10000 + // Bit CLK_EN. + PCNT_CTRL_CLK_EN = 0x10000 + + // DATE: PCNT version control register + // Position of DATE field. + PCNT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PCNT_DATE_DATE_Msk = 0xffffffff +) + +// Constants for PMS: Permissions Controller +const ( + // SDIO_0: SDIO permission control register 0. + // Position of SDIO_LOCK field. + PMS_SDIO_0_SDIO_LOCK_Pos = 0x0 + // Bit mask of SDIO_LOCK field. + PMS_SDIO_0_SDIO_LOCK_Msk = 0x1 + // Bit SDIO_LOCK. + PMS_SDIO_0_SDIO_LOCK = 0x1 + + // SDIO_1: SDIO permission control register 1. + // Position of SDIO_DISABLE field. + PMS_SDIO_1_SDIO_DISABLE_Pos = 0x0 + // Bit mask of SDIO_DISABLE field. + PMS_SDIO_1_SDIO_DISABLE_Msk = 0x1 + // Bit SDIO_DISABLE. + PMS_SDIO_1_SDIO_DISABLE = 0x1 + + // MAC_DUMP_0: MAC dump permission control register 0. + // Position of MAC_DUMP_LOCK field. + PMS_MAC_DUMP_0_MAC_DUMP_LOCK_Pos = 0x0 + // Bit mask of MAC_DUMP_LOCK field. + PMS_MAC_DUMP_0_MAC_DUMP_LOCK_Msk = 0x1 + // Bit MAC_DUMP_LOCK. + PMS_MAC_DUMP_0_MAC_DUMP_LOCK = 0x1 + + // MAC_DUMP_1: MAC dump permission control register 1. + // Position of MAC_DUMP_CONNECT field. + PMS_MAC_DUMP_1_MAC_DUMP_CONNECT_Pos = 0x0 + // Bit mask of MAC_DUMP_CONNECT field. + PMS_MAC_DUMP_1_MAC_DUMP_CONNECT_Msk = 0xfff + + // PRO_IRAM0_0: IBUS permission control register 0. + // Position of PRO_IRAM0_LOCK field. + PMS_PRO_IRAM0_0_PRO_IRAM0_LOCK_Pos = 0x0 + // Bit mask of PRO_IRAM0_LOCK field. + PMS_PRO_IRAM0_0_PRO_IRAM0_LOCK_Msk = 0x1 + // Bit PRO_IRAM0_LOCK. + PMS_PRO_IRAM0_0_PRO_IRAM0_LOCK = 0x1 + + // PRO_IRAM0_1: IBUS permission control register 1. + // Position of PRO_IRAM0_SRAM_0_F field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_0_F_Pos = 0x0 + // Bit mask of PRO_IRAM0_SRAM_0_F field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_0_F_Msk = 0x1 + // Bit PRO_IRAM0_SRAM_0_F. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_0_F = 0x1 + // Position of PRO_IRAM0_SRAM_0_R field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_0_R_Pos = 0x1 + // Bit mask of PRO_IRAM0_SRAM_0_R field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_0_R_Msk = 0x2 + // Bit PRO_IRAM0_SRAM_0_R. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_0_R = 0x2 + // Position of PRO_IRAM0_SRAM_0_W field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_0_W_Pos = 0x2 + // Bit mask of PRO_IRAM0_SRAM_0_W field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_0_W_Msk = 0x4 + // Bit PRO_IRAM0_SRAM_0_W. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_0_W = 0x4 + // Position of PRO_IRAM0_SRAM_1_F field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_1_F_Pos = 0x3 + // Bit mask of PRO_IRAM0_SRAM_1_F field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_1_F_Msk = 0x8 + // Bit PRO_IRAM0_SRAM_1_F. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_1_F = 0x8 + // Position of PRO_IRAM0_SRAM_1_R field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_1_R_Pos = 0x4 + // Bit mask of PRO_IRAM0_SRAM_1_R field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_1_R_Msk = 0x10 + // Bit PRO_IRAM0_SRAM_1_R. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_1_R = 0x10 + // Position of PRO_IRAM0_SRAM_1_W field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_1_W_Pos = 0x5 + // Bit mask of PRO_IRAM0_SRAM_1_W field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_1_W_Msk = 0x20 + // Bit PRO_IRAM0_SRAM_1_W. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_1_W = 0x20 + // Position of PRO_IRAM0_SRAM_2_F field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_2_F_Pos = 0x6 + // Bit mask of PRO_IRAM0_SRAM_2_F field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_2_F_Msk = 0x40 + // Bit PRO_IRAM0_SRAM_2_F. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_2_F = 0x40 + // Position of PRO_IRAM0_SRAM_2_R field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_2_R_Pos = 0x7 + // Bit mask of PRO_IRAM0_SRAM_2_R field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_2_R_Msk = 0x80 + // Bit PRO_IRAM0_SRAM_2_R. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_2_R = 0x80 + // Position of PRO_IRAM0_SRAM_2_W field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_2_W_Pos = 0x8 + // Bit mask of PRO_IRAM0_SRAM_2_W field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_2_W_Msk = 0x100 + // Bit PRO_IRAM0_SRAM_2_W. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_2_W = 0x100 + // Position of PRO_IRAM0_SRAM_3_F field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_3_F_Pos = 0x9 + // Bit mask of PRO_IRAM0_SRAM_3_F field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_3_F_Msk = 0x200 + // Bit PRO_IRAM0_SRAM_3_F. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_3_F = 0x200 + // Position of PRO_IRAM0_SRAM_3_R field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_3_R_Pos = 0xa + // Bit mask of PRO_IRAM0_SRAM_3_R field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_3_R_Msk = 0x400 + // Bit PRO_IRAM0_SRAM_3_R. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_3_R = 0x400 + // Position of PRO_IRAM0_SRAM_3_W field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_3_W_Pos = 0xb + // Bit mask of PRO_IRAM0_SRAM_3_W field. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_3_W_Msk = 0x800 + // Bit PRO_IRAM0_SRAM_3_W. + PMS_PRO_IRAM0_1_PRO_IRAM0_SRAM_3_W = 0x800 + + // PRO_IRAM0_2: IBUS permission control register 2. + // Position of PRO_IRAM0_SRAM_4_SPLTADDR field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_SPLTADDR_Pos = 0x0 + // Bit mask of PRO_IRAM0_SRAM_4_SPLTADDR field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_SPLTADDR_Msk = 0x1ffff + // Position of PRO_IRAM0_SRAM_4_L_F field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_F_Pos = 0x11 + // Bit mask of PRO_IRAM0_SRAM_4_L_F field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_F_Msk = 0x20000 + // Bit PRO_IRAM0_SRAM_4_L_F. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_F = 0x20000 + // Position of PRO_IRAM0_SRAM_4_L_R field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_R_Pos = 0x12 + // Bit mask of PRO_IRAM0_SRAM_4_L_R field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_R_Msk = 0x40000 + // Bit PRO_IRAM0_SRAM_4_L_R. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_R = 0x40000 + // Position of PRO_IRAM0_SRAM_4_L_W field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_W_Pos = 0x13 + // Bit mask of PRO_IRAM0_SRAM_4_L_W field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_W_Msk = 0x80000 + // Bit PRO_IRAM0_SRAM_4_L_W. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_L_W = 0x80000 + // Position of PRO_IRAM0_SRAM_4_H_F field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_F_Pos = 0x14 + // Bit mask of PRO_IRAM0_SRAM_4_H_F field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_F_Msk = 0x100000 + // Bit PRO_IRAM0_SRAM_4_H_F. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_F = 0x100000 + // Position of PRO_IRAM0_SRAM_4_H_R field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_R_Pos = 0x15 + // Bit mask of PRO_IRAM0_SRAM_4_H_R field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_R_Msk = 0x200000 + // Bit PRO_IRAM0_SRAM_4_H_R. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_R = 0x200000 + // Position of PRO_IRAM0_SRAM_4_H_W field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_W_Pos = 0x16 + // Bit mask of PRO_IRAM0_SRAM_4_H_W field. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_W_Msk = 0x400000 + // Bit PRO_IRAM0_SRAM_4_H_W. + PMS_PRO_IRAM0_2_PRO_IRAM0_SRAM_4_H_W = 0x400000 + + // PRO_IRAM0_3: IBUS permission control register 3. + // Position of PRO_IRAM0_RTCFAST_SPLTADDR field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_SPLTADDR_Pos = 0x0 + // Bit mask of PRO_IRAM0_RTCFAST_SPLTADDR field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_SPLTADDR_Msk = 0x7ff + // Position of PRO_IRAM0_RTCFAST_L_F field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_F_Pos = 0xb + // Bit mask of PRO_IRAM0_RTCFAST_L_F field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_F_Msk = 0x800 + // Bit PRO_IRAM0_RTCFAST_L_F. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_F = 0x800 + // Position of PRO_IRAM0_RTCFAST_L_R field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_R_Pos = 0xc + // Bit mask of PRO_IRAM0_RTCFAST_L_R field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_R_Msk = 0x1000 + // Bit PRO_IRAM0_RTCFAST_L_R. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_R = 0x1000 + // Position of PRO_IRAM0_RTCFAST_L_W field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_W_Pos = 0xd + // Bit mask of PRO_IRAM0_RTCFAST_L_W field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_W_Msk = 0x2000 + // Bit PRO_IRAM0_RTCFAST_L_W. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_L_W = 0x2000 + // Position of PRO_IRAM0_RTCFAST_H_F field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_F_Pos = 0xe + // Bit mask of PRO_IRAM0_RTCFAST_H_F field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_F_Msk = 0x4000 + // Bit PRO_IRAM0_RTCFAST_H_F. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_F = 0x4000 + // Position of PRO_IRAM0_RTCFAST_H_R field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_R_Pos = 0xf + // Bit mask of PRO_IRAM0_RTCFAST_H_R field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_R_Msk = 0x8000 + // Bit PRO_IRAM0_RTCFAST_H_R. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_R = 0x8000 + // Position of PRO_IRAM0_RTCFAST_H_W field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_W_Pos = 0x10 + // Bit mask of PRO_IRAM0_RTCFAST_H_W field. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_W_Msk = 0x10000 + // Bit PRO_IRAM0_RTCFAST_H_W. + PMS_PRO_IRAM0_3_PRO_IRAM0_RTCFAST_H_W = 0x10000 + + // PRO_IRAM0_4: IBUS permission control register 4. + // Position of PRO_IRAM0_ILG_CLR field. + PMS_PRO_IRAM0_4_PRO_IRAM0_ILG_CLR_Pos = 0x0 + // Bit mask of PRO_IRAM0_ILG_CLR field. + PMS_PRO_IRAM0_4_PRO_IRAM0_ILG_CLR_Msk = 0x1 + // Bit PRO_IRAM0_ILG_CLR. + PMS_PRO_IRAM0_4_PRO_IRAM0_ILG_CLR = 0x1 + // Position of PRO_IRAM0_ILG_EN field. + PMS_PRO_IRAM0_4_PRO_IRAM0_ILG_EN_Pos = 0x1 + // Bit mask of PRO_IRAM0_ILG_EN field. + PMS_PRO_IRAM0_4_PRO_IRAM0_ILG_EN_Msk = 0x2 + // Bit PRO_IRAM0_ILG_EN. + PMS_PRO_IRAM0_4_PRO_IRAM0_ILG_EN = 0x2 + // Position of PRO_IRAM0_ILG_INTR field. + PMS_PRO_IRAM0_4_PRO_IRAM0_ILG_INTR_Pos = 0x2 + // Bit mask of PRO_IRAM0_ILG_INTR field. + PMS_PRO_IRAM0_4_PRO_IRAM0_ILG_INTR_Msk = 0x4 + // Bit PRO_IRAM0_ILG_INTR. + PMS_PRO_IRAM0_4_PRO_IRAM0_ILG_INTR = 0x4 + + // PRO_IRAM0_5: IBUS status register. + // Position of PRO_IRAM0_ILG_ST field. + PMS_PRO_IRAM0_5_PRO_IRAM0_ILG_ST_Pos = 0x0 + // Bit mask of PRO_IRAM0_ILG_ST field. + PMS_PRO_IRAM0_5_PRO_IRAM0_ILG_ST_Msk = 0x3fffff + + // PRO_DRAM0_0: DBUS permission control register 0. + // Position of PRO_DRAM0_LOCK field. + PMS_PRO_DRAM0_0_PRO_DRAM0_LOCK_Pos = 0x0 + // Bit mask of PRO_DRAM0_LOCK field. + PMS_PRO_DRAM0_0_PRO_DRAM0_LOCK_Msk = 0x1 + // Bit PRO_DRAM0_LOCK. + PMS_PRO_DRAM0_0_PRO_DRAM0_LOCK = 0x1 + + // PRO_DRAM0_1: DBUS permission control register 1. + // Position of PRO_DRAM0_SRAM_0_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_0_R_Pos = 0x0 + // Bit mask of PRO_DRAM0_SRAM_0_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_0_R_Msk = 0x1 + // Bit PRO_DRAM0_SRAM_0_R. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_0_R = 0x1 + // Position of PRO_DRAM0_SRAM_0_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_0_W_Pos = 0x1 + // Bit mask of PRO_DRAM0_SRAM_0_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_0_W_Msk = 0x2 + // Bit PRO_DRAM0_SRAM_0_W. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_0_W = 0x2 + // Position of PRO_DRAM0_SRAM_1_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_1_R_Pos = 0x2 + // Bit mask of PRO_DRAM0_SRAM_1_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_1_R_Msk = 0x4 + // Bit PRO_DRAM0_SRAM_1_R. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_1_R = 0x4 + // Position of PRO_DRAM0_SRAM_1_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_1_W_Pos = 0x3 + // Bit mask of PRO_DRAM0_SRAM_1_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_1_W_Msk = 0x8 + // Bit PRO_DRAM0_SRAM_1_W. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_1_W = 0x8 + // Position of PRO_DRAM0_SRAM_2_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_2_R_Pos = 0x4 + // Bit mask of PRO_DRAM0_SRAM_2_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_2_R_Msk = 0x10 + // Bit PRO_DRAM0_SRAM_2_R. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_2_R = 0x10 + // Position of PRO_DRAM0_SRAM_2_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_2_W_Pos = 0x5 + // Bit mask of PRO_DRAM0_SRAM_2_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_2_W_Msk = 0x20 + // Bit PRO_DRAM0_SRAM_2_W. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_2_W = 0x20 + // Position of PRO_DRAM0_SRAM_3_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_3_R_Pos = 0x6 + // Bit mask of PRO_DRAM0_SRAM_3_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_3_R_Msk = 0x40 + // Bit PRO_DRAM0_SRAM_3_R. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_3_R = 0x40 + // Position of PRO_DRAM0_SRAM_3_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_3_W_Pos = 0x7 + // Bit mask of PRO_DRAM0_SRAM_3_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_3_W_Msk = 0x80 + // Bit PRO_DRAM0_SRAM_3_W. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_3_W = 0x80 + // Position of PRO_DRAM0_SRAM_4_SPLTADDR field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_SPLTADDR_Pos = 0x8 + // Bit mask of PRO_DRAM0_SRAM_4_SPLTADDR field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_SPLTADDR_Msk = 0x1ffff00 + // Position of PRO_DRAM0_SRAM_4_L_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_R_Pos = 0x19 + // Bit mask of PRO_DRAM0_SRAM_4_L_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_R_Msk = 0x2000000 + // Bit PRO_DRAM0_SRAM_4_L_R. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_R = 0x2000000 + // Position of PRO_DRAM0_SRAM_4_L_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_W_Pos = 0x1a + // Bit mask of PRO_DRAM0_SRAM_4_L_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_W_Msk = 0x4000000 + // Bit PRO_DRAM0_SRAM_4_L_W. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_L_W = 0x4000000 + // Position of PRO_DRAM0_SRAM_4_H_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_R_Pos = 0x1b + // Bit mask of PRO_DRAM0_SRAM_4_H_R field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_R_Msk = 0x8000000 + // Bit PRO_DRAM0_SRAM_4_H_R. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_R = 0x8000000 + // Position of PRO_DRAM0_SRAM_4_H_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_W_Pos = 0x1c + // Bit mask of PRO_DRAM0_SRAM_4_H_W field. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_W_Msk = 0x10000000 + // Bit PRO_DRAM0_SRAM_4_H_W. + PMS_PRO_DRAM0_1_PRO_DRAM0_SRAM_4_H_W = 0x10000000 + + // PRO_DRAM0_2: DBUS permission control register 2. + // Position of PRO_DRAM0_RTCFAST_SPLTADDR field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_SPLTADDR_Pos = 0x0 + // Bit mask of PRO_DRAM0_RTCFAST_SPLTADDR field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_SPLTADDR_Msk = 0x7ff + // Position of PRO_DRAM0_RTCFAST_L_R field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_R_Pos = 0xb + // Bit mask of PRO_DRAM0_RTCFAST_L_R field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_R_Msk = 0x800 + // Bit PRO_DRAM0_RTCFAST_L_R. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_R = 0x800 + // Position of PRO_DRAM0_RTCFAST_L_W field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_W_Pos = 0xc + // Bit mask of PRO_DRAM0_RTCFAST_L_W field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_W_Msk = 0x1000 + // Bit PRO_DRAM0_RTCFAST_L_W. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_L_W = 0x1000 + // Position of PRO_DRAM0_RTCFAST_H_R field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_R_Pos = 0xd + // Bit mask of PRO_DRAM0_RTCFAST_H_R field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_R_Msk = 0x2000 + // Bit PRO_DRAM0_RTCFAST_H_R. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_R = 0x2000 + // Position of PRO_DRAM0_RTCFAST_H_W field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_W_Pos = 0xe + // Bit mask of PRO_DRAM0_RTCFAST_H_W field. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_W_Msk = 0x4000 + // Bit PRO_DRAM0_RTCFAST_H_W. + PMS_PRO_DRAM0_2_PRO_DRAM0_RTCFAST_H_W = 0x4000 + + // PRO_DRAM0_3: DBUS permission control register 3. + // Position of PRO_DRAM0_ILG_CLR field. + PMS_PRO_DRAM0_3_PRO_DRAM0_ILG_CLR_Pos = 0x0 + // Bit mask of PRO_DRAM0_ILG_CLR field. + PMS_PRO_DRAM0_3_PRO_DRAM0_ILG_CLR_Msk = 0x1 + // Bit PRO_DRAM0_ILG_CLR. + PMS_PRO_DRAM0_3_PRO_DRAM0_ILG_CLR = 0x1 + // Position of PRO_DRAM0_ILG_EN field. + PMS_PRO_DRAM0_3_PRO_DRAM0_ILG_EN_Pos = 0x1 + // Bit mask of PRO_DRAM0_ILG_EN field. + PMS_PRO_DRAM0_3_PRO_DRAM0_ILG_EN_Msk = 0x2 + // Bit PRO_DRAM0_ILG_EN. + PMS_PRO_DRAM0_3_PRO_DRAM0_ILG_EN = 0x2 + // Position of PRO_DRAM0_ILG_INTR field. + PMS_PRO_DRAM0_3_PRO_DRAM0_ILG_INTR_Pos = 0x2 + // Bit mask of PRO_DRAM0_ILG_INTR field. + PMS_PRO_DRAM0_3_PRO_DRAM0_ILG_INTR_Msk = 0x4 + // Bit PRO_DRAM0_ILG_INTR. + PMS_PRO_DRAM0_3_PRO_DRAM0_ILG_INTR = 0x4 + + // PRO_DRAM0_4: DBUS status register. + // Position of PRO_DRAM0_ILG_ST field. + PMS_PRO_DRAM0_4_PRO_DRAM0_ILG_ST_Pos = 0x0 + // Bit mask of PRO_DRAM0_ILG_ST field. + PMS_PRO_DRAM0_4_PRO_DRAM0_ILG_ST_Msk = 0x3ffffff + + // PRO_DPORT_0: PeriBus1 permission control register 0. + // Position of PRO_DPORT_LOCK field. + PMS_PRO_DPORT_0_PRO_DPORT_LOCK_Pos = 0x0 + // Bit mask of PRO_DPORT_LOCK field. + PMS_PRO_DPORT_0_PRO_DPORT_LOCK_Msk = 0x1 + // Bit PRO_DPORT_LOCK. + PMS_PRO_DPORT_0_PRO_DPORT_LOCK = 0x1 + + // PRO_DPORT_1: PeriBus1 permission control register 1. + // Position of PRO_DPORT_APB_PERIPHERAL_FORBID field. + PMS_PRO_DPORT_1_PRO_DPORT_APB_PERIPHERAL_FORBID_Pos = 0x0 + // Bit mask of PRO_DPORT_APB_PERIPHERAL_FORBID field. + PMS_PRO_DPORT_1_PRO_DPORT_APB_PERIPHERAL_FORBID_Msk = 0x1 + // Bit PRO_DPORT_APB_PERIPHERAL_FORBID. + PMS_PRO_DPORT_1_PRO_DPORT_APB_PERIPHERAL_FORBID = 0x1 + // Position of PRO_DPORT_RTCSLOW_SPLTADDR field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_SPLTADDR_Pos = 0x1 + // Bit mask of PRO_DPORT_RTCSLOW_SPLTADDR field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_SPLTADDR_Msk = 0xffe + // Position of PRO_DPORT_RTCSLOW_L_R field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_L_R_Pos = 0xc + // Bit mask of PRO_DPORT_RTCSLOW_L_R field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_L_R_Msk = 0x1000 + // Bit PRO_DPORT_RTCSLOW_L_R. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_L_R = 0x1000 + // Position of PRO_DPORT_RTCSLOW_L_W field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_L_W_Pos = 0xd + // Bit mask of PRO_DPORT_RTCSLOW_L_W field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_L_W_Msk = 0x2000 + // Bit PRO_DPORT_RTCSLOW_L_W. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_L_W = 0x2000 + // Position of PRO_DPORT_RTCSLOW_H_R field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_H_R_Pos = 0xe + // Bit mask of PRO_DPORT_RTCSLOW_H_R field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_H_R_Msk = 0x4000 + // Bit PRO_DPORT_RTCSLOW_H_R. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_H_R = 0x4000 + // Position of PRO_DPORT_RTCSLOW_H_W field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_H_W_Pos = 0xf + // Bit mask of PRO_DPORT_RTCSLOW_H_W field. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_H_W_Msk = 0x8000 + // Bit PRO_DPORT_RTCSLOW_H_W. + PMS_PRO_DPORT_1_PRO_DPORT_RTCSLOW_H_W = 0x8000 + // Position of PRO_DPORT_RESERVE_FIFO_VALID field. + PMS_PRO_DPORT_1_PRO_DPORT_RESERVE_FIFO_VALID_Pos = 0x10 + // Bit mask of PRO_DPORT_RESERVE_FIFO_VALID field. + PMS_PRO_DPORT_1_PRO_DPORT_RESERVE_FIFO_VALID_Msk = 0xf0000 + + // PRO_DPORT_2: PeriBus1 permission control register 2. + // Position of PRO_DPORT_RESERVE_FIFO_0 field. + PMS_PRO_DPORT_2_PRO_DPORT_RESERVE_FIFO_0_Pos = 0x0 + // Bit mask of PRO_DPORT_RESERVE_FIFO_0 field. + PMS_PRO_DPORT_2_PRO_DPORT_RESERVE_FIFO_0_Msk = 0x3ffff + + // PRO_DPORT_3: PeriBus1 permission control register 3. + // Position of PRO_DPORT_RESERVE_FIFO_1 field. + PMS_PRO_DPORT_3_PRO_DPORT_RESERVE_FIFO_1_Pos = 0x0 + // Bit mask of PRO_DPORT_RESERVE_FIFO_1 field. + PMS_PRO_DPORT_3_PRO_DPORT_RESERVE_FIFO_1_Msk = 0x3ffff + + // PRO_DPORT_4: PeriBus1 permission control register 4. + // Position of PRO_DPORT_RESERVE_FIFO_2 field. + PMS_PRO_DPORT_4_PRO_DPORT_RESERVE_FIFO_2_Pos = 0x0 + // Bit mask of PRO_DPORT_RESERVE_FIFO_2 field. + PMS_PRO_DPORT_4_PRO_DPORT_RESERVE_FIFO_2_Msk = 0x3ffff + + // PRO_DPORT_5: PeriBus1 permission control register 5. + // Position of PRO_DPORT_RESERVE_FIFO_3 field. + PMS_PRO_DPORT_5_PRO_DPORT_RESERVE_FIFO_3_Pos = 0x0 + // Bit mask of PRO_DPORT_RESERVE_FIFO_3 field. + PMS_PRO_DPORT_5_PRO_DPORT_RESERVE_FIFO_3_Msk = 0x3ffff + + // PRO_DPORT_6: PeriBus1 permission control register 6. + // Position of PRO_DPORT_ILG_CLR field. + PMS_PRO_DPORT_6_PRO_DPORT_ILG_CLR_Pos = 0x0 + // Bit mask of PRO_DPORT_ILG_CLR field. + PMS_PRO_DPORT_6_PRO_DPORT_ILG_CLR_Msk = 0x1 + // Bit PRO_DPORT_ILG_CLR. + PMS_PRO_DPORT_6_PRO_DPORT_ILG_CLR = 0x1 + // Position of PRO_DPORT_ILG_EN field. + PMS_PRO_DPORT_6_PRO_DPORT_ILG_EN_Pos = 0x1 + // Bit mask of PRO_DPORT_ILG_EN field. + PMS_PRO_DPORT_6_PRO_DPORT_ILG_EN_Msk = 0x2 + // Bit PRO_DPORT_ILG_EN. + PMS_PRO_DPORT_6_PRO_DPORT_ILG_EN = 0x2 + // Position of PRO_DPORT_ILG_INTR field. + PMS_PRO_DPORT_6_PRO_DPORT_ILG_INTR_Pos = 0x2 + // Bit mask of PRO_DPORT_ILG_INTR field. + PMS_PRO_DPORT_6_PRO_DPORT_ILG_INTR_Msk = 0x4 + // Bit PRO_DPORT_ILG_INTR. + PMS_PRO_DPORT_6_PRO_DPORT_ILG_INTR = 0x4 + + // PRO_DPORT_7: PeriBus1 status register. + // Position of PRO_DPORT_ILG_ST field. + PMS_PRO_DPORT_7_PRO_DPORT_ILG_ST_Pos = 0x0 + // Bit mask of PRO_DPORT_ILG_ST field. + PMS_PRO_DPORT_7_PRO_DPORT_ILG_ST_Msk = 0x3ffffff + + // PRO_AHB_0: PeriBus2 permission control register 0. + // Position of PRO_AHB_LOCK field. + PMS_PRO_AHB_0_PRO_AHB_LOCK_Pos = 0x0 + // Bit mask of PRO_AHB_LOCK field. + PMS_PRO_AHB_0_PRO_AHB_LOCK_Msk = 0x1 + // Bit PRO_AHB_LOCK. + PMS_PRO_AHB_0_PRO_AHB_LOCK = 0x1 + + // PRO_AHB_1: PeriBus2 permission control register 1. + // Position of PRO_AHB_RTCSLOW_0_SPLTADDR field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_SPLTADDR_Pos = 0x0 + // Bit mask of PRO_AHB_RTCSLOW_0_SPLTADDR field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_SPLTADDR_Msk = 0x7ff + // Position of PRO_AHB_RTCSLOW_0_L_F field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_L_F_Pos = 0xb + // Bit mask of PRO_AHB_RTCSLOW_0_L_F field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_L_F_Msk = 0x800 + // Bit PRO_AHB_RTCSLOW_0_L_F. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_L_F = 0x800 + // Position of PRO_AHB_RTCSLOW_0_L_R field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_L_R_Pos = 0xc + // Bit mask of PRO_AHB_RTCSLOW_0_L_R field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_L_R_Msk = 0x1000 + // Bit PRO_AHB_RTCSLOW_0_L_R. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_L_R = 0x1000 + // Position of PRO_AHB_RTCSLOW_0_L_W field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_L_W_Pos = 0xd + // Bit mask of PRO_AHB_RTCSLOW_0_L_W field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_L_W_Msk = 0x2000 + // Bit PRO_AHB_RTCSLOW_0_L_W. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_L_W = 0x2000 + // Position of PRO_AHB_RTCSLOW_0_H_F field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_H_F_Pos = 0xe + // Bit mask of PRO_AHB_RTCSLOW_0_H_F field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_H_F_Msk = 0x4000 + // Bit PRO_AHB_RTCSLOW_0_H_F. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_H_F = 0x4000 + // Position of PRO_AHB_RTCSLOW_0_H_R field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_H_R_Pos = 0xf + // Bit mask of PRO_AHB_RTCSLOW_0_H_R field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_H_R_Msk = 0x8000 + // Bit PRO_AHB_RTCSLOW_0_H_R. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_H_R = 0x8000 + // Position of PRO_AHB_RTCSLOW_0_H_W field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_H_W_Pos = 0x10 + // Bit mask of PRO_AHB_RTCSLOW_0_H_W field. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_H_W_Msk = 0x10000 + // Bit PRO_AHB_RTCSLOW_0_H_W. + PMS_PRO_AHB_1_PRO_AHB_RTCSLOW_0_H_W = 0x10000 + + // PRO_AHB_2: PeriBus2 permission control register 2. + // Position of PRO_AHB_RTCSLOW_1_SPLTADDR field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_SPLTADDR_Pos = 0x0 + // Bit mask of PRO_AHB_RTCSLOW_1_SPLTADDR field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_SPLTADDR_Msk = 0x7ff + // Position of PRO_AHB_RTCSLOW_1_L_F field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_L_F_Pos = 0xb + // Bit mask of PRO_AHB_RTCSLOW_1_L_F field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_L_F_Msk = 0x800 + // Bit PRO_AHB_RTCSLOW_1_L_F. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_L_F = 0x800 + // Position of PRO_AHB_RTCSLOW_1_L_R field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_L_R_Pos = 0xc + // Bit mask of PRO_AHB_RTCSLOW_1_L_R field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_L_R_Msk = 0x1000 + // Bit PRO_AHB_RTCSLOW_1_L_R. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_L_R = 0x1000 + // Position of PRO_AHB_RTCSLOW_1_L_W field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_L_W_Pos = 0xd + // Bit mask of PRO_AHB_RTCSLOW_1_L_W field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_L_W_Msk = 0x2000 + // Bit PRO_AHB_RTCSLOW_1_L_W. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_L_W = 0x2000 + // Position of PRO_AHB_RTCSLOW_1_H_F field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_H_F_Pos = 0xe + // Bit mask of PRO_AHB_RTCSLOW_1_H_F field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_H_F_Msk = 0x4000 + // Bit PRO_AHB_RTCSLOW_1_H_F. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_H_F = 0x4000 + // Position of PRO_AHB_RTCSLOW_1_H_R field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_H_R_Pos = 0xf + // Bit mask of PRO_AHB_RTCSLOW_1_H_R field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_H_R_Msk = 0x8000 + // Bit PRO_AHB_RTCSLOW_1_H_R. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_H_R = 0x8000 + // Position of PRO_AHB_RTCSLOW_1_H_W field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_H_W_Pos = 0x10 + // Bit mask of PRO_AHB_RTCSLOW_1_H_W field. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_H_W_Msk = 0x10000 + // Bit PRO_AHB_RTCSLOW_1_H_W. + PMS_PRO_AHB_2_PRO_AHB_RTCSLOW_1_H_W = 0x10000 + + // PRO_AHB_3: PeriBus2 permission control register 3. + // Position of PRO_AHB_ILG_CLR field. + PMS_PRO_AHB_3_PRO_AHB_ILG_CLR_Pos = 0x0 + // Bit mask of PRO_AHB_ILG_CLR field. + PMS_PRO_AHB_3_PRO_AHB_ILG_CLR_Msk = 0x1 + // Bit PRO_AHB_ILG_CLR. + PMS_PRO_AHB_3_PRO_AHB_ILG_CLR = 0x1 + // Position of PRO_AHB_ILG_EN field. + PMS_PRO_AHB_3_PRO_AHB_ILG_EN_Pos = 0x1 + // Bit mask of PRO_AHB_ILG_EN field. + PMS_PRO_AHB_3_PRO_AHB_ILG_EN_Msk = 0x2 + // Bit PRO_AHB_ILG_EN. + PMS_PRO_AHB_3_PRO_AHB_ILG_EN = 0x2 + // Position of PRO_AHB_ILG_INTR field. + PMS_PRO_AHB_3_PRO_AHB_ILG_INTR_Pos = 0x2 + // Bit mask of PRO_AHB_ILG_INTR field. + PMS_PRO_AHB_3_PRO_AHB_ILG_INTR_Msk = 0x4 + // Bit PRO_AHB_ILG_INTR. + PMS_PRO_AHB_3_PRO_AHB_ILG_INTR = 0x4 + + // PRO_AHB_4: PeriBus2 status register. + // Position of PRO_AHB_ILG_ST field. + PMS_PRO_AHB_4_PRO_AHB_ILG_ST_Pos = 0x0 + // Bit mask of PRO_AHB_ILG_ST field. + PMS_PRO_AHB_4_PRO_AHB_ILG_ST_Msk = 0xffffffff + + // PRO_TRACE_0: Trace memory permission control register 0. + // Position of PRO_TRACE_LOCK field. + PMS_PRO_TRACE_0_PRO_TRACE_LOCK_Pos = 0x0 + // Bit mask of PRO_TRACE_LOCK field. + PMS_PRO_TRACE_0_PRO_TRACE_LOCK_Msk = 0x1 + // Bit PRO_TRACE_LOCK. + PMS_PRO_TRACE_0_PRO_TRACE_LOCK = 0x1 + + // PRO_TRACE_1: Trace memory permission control register 1. + // Position of PRO_TRACE_DISABLE field. + PMS_PRO_TRACE_1_PRO_TRACE_DISABLE_Pos = 0x0 + // Bit mask of PRO_TRACE_DISABLE field. + PMS_PRO_TRACE_1_PRO_TRACE_DISABLE_Msk = 0x1 + // Bit PRO_TRACE_DISABLE. + PMS_PRO_TRACE_1_PRO_TRACE_DISABLE = 0x1 + + // PRO_CACHE_0: Cache permission control register 0. + // Position of PRO_CACHE_LOCK field. + PMS_PRO_CACHE_0_PRO_CACHE_LOCK_Pos = 0x0 + // Bit mask of PRO_CACHE_LOCK field. + PMS_PRO_CACHE_0_PRO_CACHE_LOCK_Msk = 0x1 + // Bit PRO_CACHE_LOCK. + PMS_PRO_CACHE_0_PRO_CACHE_LOCK = 0x1 + + // PRO_CACHE_1: Cache permission control register 1. + // Position of PRO_CACHE_CONNECT field. + PMS_PRO_CACHE_1_PRO_CACHE_CONNECT_Pos = 0x0 + // Bit mask of PRO_CACHE_CONNECT field. + PMS_PRO_CACHE_1_PRO_CACHE_CONNECT_Msk = 0xffff + + // PRO_CACHE_2: Cache permission control register 2. + // Position of PRO_CACHE_ILG_CLR field. + PMS_PRO_CACHE_2_PRO_CACHE_ILG_CLR_Pos = 0x0 + // Bit mask of PRO_CACHE_ILG_CLR field. + PMS_PRO_CACHE_2_PRO_CACHE_ILG_CLR_Msk = 0x1 + // Bit PRO_CACHE_ILG_CLR. + PMS_PRO_CACHE_2_PRO_CACHE_ILG_CLR = 0x1 + // Position of PRO_CACHE_ILG_EN field. + PMS_PRO_CACHE_2_PRO_CACHE_ILG_EN_Pos = 0x1 + // Bit mask of PRO_CACHE_ILG_EN field. + PMS_PRO_CACHE_2_PRO_CACHE_ILG_EN_Msk = 0x2 + // Bit PRO_CACHE_ILG_EN. + PMS_PRO_CACHE_2_PRO_CACHE_ILG_EN = 0x2 + // Position of PRO_CACHE_ILG_INTR field. + PMS_PRO_CACHE_2_PRO_CACHE_ILG_INTR_Pos = 0x2 + // Bit mask of PRO_CACHE_ILG_INTR field. + PMS_PRO_CACHE_2_PRO_CACHE_ILG_INTR_Msk = 0x4 + // Bit PRO_CACHE_ILG_INTR. + PMS_PRO_CACHE_2_PRO_CACHE_ILG_INTR = 0x4 + + // PRO_CACHE_3: Icache status register. + // Position of PRO_CACHE_ILG_ST_I field. + PMS_PRO_CACHE_3_PRO_CACHE_ILG_ST_I_Pos = 0x0 + // Bit mask of PRO_CACHE_ILG_ST_I field. + PMS_PRO_CACHE_3_PRO_CACHE_ILG_ST_I_Msk = 0x1ffff + + // PRO_CACHE_4: Dcache status register. + // Position of PRO_CACHE_ILG_ST_D field. + PMS_PRO_CACHE_4_PRO_CACHE_ILG_ST_D_Pos = 0x0 + // Bit mask of PRO_CACHE_ILG_ST_D field. + PMS_PRO_CACHE_4_PRO_CACHE_ILG_ST_D_Msk = 0x1ffff + + // DMA_APB_I_0: Internal DMA permission control register 0. + // Position of DMA_APB_I_LOCK field. + PMS_DMA_APB_I_0_DMA_APB_I_LOCK_Pos = 0x0 + // Bit mask of DMA_APB_I_LOCK field. + PMS_DMA_APB_I_0_DMA_APB_I_LOCK_Msk = 0x1 + // Bit DMA_APB_I_LOCK. + PMS_DMA_APB_I_0_DMA_APB_I_LOCK = 0x1 + + // DMA_APB_I_1: Internal DMA permission control register 1. + // Position of DMA_APB_I_SRAM_0_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_0_R_Pos = 0x0 + // Bit mask of DMA_APB_I_SRAM_0_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_0_R_Msk = 0x1 + // Bit DMA_APB_I_SRAM_0_R. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_0_R = 0x1 + // Position of DMA_APB_I_SRAM_0_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_0_W_Pos = 0x1 + // Bit mask of DMA_APB_I_SRAM_0_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_0_W_Msk = 0x2 + // Bit DMA_APB_I_SRAM_0_W. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_0_W = 0x2 + // Position of DMA_APB_I_SRAM_1_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_1_R_Pos = 0x2 + // Bit mask of DMA_APB_I_SRAM_1_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_1_R_Msk = 0x4 + // Bit DMA_APB_I_SRAM_1_R. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_1_R = 0x4 + // Position of DMA_APB_I_SRAM_1_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_1_W_Pos = 0x3 + // Bit mask of DMA_APB_I_SRAM_1_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_1_W_Msk = 0x8 + // Bit DMA_APB_I_SRAM_1_W. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_1_W = 0x8 + // Position of DMA_APB_I_SRAM_2_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_2_R_Pos = 0x4 + // Bit mask of DMA_APB_I_SRAM_2_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_2_R_Msk = 0x10 + // Bit DMA_APB_I_SRAM_2_R. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_2_R = 0x10 + // Position of DMA_APB_I_SRAM_2_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_2_W_Pos = 0x5 + // Bit mask of DMA_APB_I_SRAM_2_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_2_W_Msk = 0x20 + // Bit DMA_APB_I_SRAM_2_W. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_2_W = 0x20 + // Position of DMA_APB_I_SRAM_3_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_3_R_Pos = 0x6 + // Bit mask of DMA_APB_I_SRAM_3_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_3_R_Msk = 0x40 + // Bit DMA_APB_I_SRAM_3_R. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_3_R = 0x40 + // Position of DMA_APB_I_SRAM_3_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_3_W_Pos = 0x7 + // Bit mask of DMA_APB_I_SRAM_3_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_3_W_Msk = 0x80 + // Bit DMA_APB_I_SRAM_3_W. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_3_W = 0x80 + // Position of DMA_APB_I_SRAM_4_SPLTADDR field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_SPLTADDR_Pos = 0x8 + // Bit mask of DMA_APB_I_SRAM_4_SPLTADDR field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_SPLTADDR_Msk = 0x1ffff00 + // Position of DMA_APB_I_SRAM_4_L_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_L_R_Pos = 0x19 + // Bit mask of DMA_APB_I_SRAM_4_L_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_L_R_Msk = 0x2000000 + // Bit DMA_APB_I_SRAM_4_L_R. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_L_R = 0x2000000 + // Position of DMA_APB_I_SRAM_4_L_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_L_W_Pos = 0x1a + // Bit mask of DMA_APB_I_SRAM_4_L_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_L_W_Msk = 0x4000000 + // Bit DMA_APB_I_SRAM_4_L_W. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_L_W = 0x4000000 + // Position of DMA_APB_I_SRAM_4_H_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_H_R_Pos = 0x1b + // Bit mask of DMA_APB_I_SRAM_4_H_R field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_H_R_Msk = 0x8000000 + // Bit DMA_APB_I_SRAM_4_H_R. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_H_R = 0x8000000 + // Position of DMA_APB_I_SRAM_4_H_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_H_W_Pos = 0x1c + // Bit mask of DMA_APB_I_SRAM_4_H_W field. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_H_W_Msk = 0x10000000 + // Bit DMA_APB_I_SRAM_4_H_W. + PMS_DMA_APB_I_1_DMA_APB_I_SRAM_4_H_W = 0x10000000 + + // DMA_APB_I_2: Internal DMA permission control register 2. + // Position of DMA_APB_I_ILG_CLR field. + PMS_DMA_APB_I_2_DMA_APB_I_ILG_CLR_Pos = 0x0 + // Bit mask of DMA_APB_I_ILG_CLR field. + PMS_DMA_APB_I_2_DMA_APB_I_ILG_CLR_Msk = 0x1 + // Bit DMA_APB_I_ILG_CLR. + PMS_DMA_APB_I_2_DMA_APB_I_ILG_CLR = 0x1 + // Position of DMA_APB_I_ILG_EN field. + PMS_DMA_APB_I_2_DMA_APB_I_ILG_EN_Pos = 0x1 + // Bit mask of DMA_APB_I_ILG_EN field. + PMS_DMA_APB_I_2_DMA_APB_I_ILG_EN_Msk = 0x2 + // Bit DMA_APB_I_ILG_EN. + PMS_DMA_APB_I_2_DMA_APB_I_ILG_EN = 0x2 + // Position of DMA_APB_I_ILG_INTR field. + PMS_DMA_APB_I_2_DMA_APB_I_ILG_INTR_Pos = 0x2 + // Bit mask of DMA_APB_I_ILG_INTR field. + PMS_DMA_APB_I_2_DMA_APB_I_ILG_INTR_Msk = 0x4 + // Bit DMA_APB_I_ILG_INTR. + PMS_DMA_APB_I_2_DMA_APB_I_ILG_INTR = 0x4 + + // DMA_APB_I_3: Internal DMA status register. + // Position of DMA_APB_I_ILG_ST field. + PMS_DMA_APB_I_3_DMA_APB_I_ILG_ST_Pos = 0x0 + // Bit mask of DMA_APB_I_ILG_ST field. + PMS_DMA_APB_I_3_DMA_APB_I_ILG_ST_Msk = 0x7fffff + + // DMA_RX_I_0: RX Copy DMA permission control register 0. + // Position of DMA_RX_I_LOCK field. + PMS_DMA_RX_I_0_DMA_RX_I_LOCK_Pos = 0x0 + // Bit mask of DMA_RX_I_LOCK field. + PMS_DMA_RX_I_0_DMA_RX_I_LOCK_Msk = 0x1 + // Bit DMA_RX_I_LOCK. + PMS_DMA_RX_I_0_DMA_RX_I_LOCK = 0x1 + + // DMA_RX_I_1: RX Copy DMA permission control register 1. + // Position of DMA_RX_I_SRAM_0_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_0_R_Pos = 0x0 + // Bit mask of DMA_RX_I_SRAM_0_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_0_R_Msk = 0x1 + // Bit DMA_RX_I_SRAM_0_R. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_0_R = 0x1 + // Position of DMA_RX_I_SRAM_0_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_0_W_Pos = 0x1 + // Bit mask of DMA_RX_I_SRAM_0_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_0_W_Msk = 0x2 + // Bit DMA_RX_I_SRAM_0_W. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_0_W = 0x2 + // Position of DMA_RX_I_SRAM_1_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_1_R_Pos = 0x2 + // Bit mask of DMA_RX_I_SRAM_1_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_1_R_Msk = 0x4 + // Bit DMA_RX_I_SRAM_1_R. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_1_R = 0x4 + // Position of DMA_RX_I_SRAM_1_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_1_W_Pos = 0x3 + // Bit mask of DMA_RX_I_SRAM_1_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_1_W_Msk = 0x8 + // Bit DMA_RX_I_SRAM_1_W. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_1_W = 0x8 + // Position of DMA_RX_I_SRAM_2_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_2_R_Pos = 0x4 + // Bit mask of DMA_RX_I_SRAM_2_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_2_R_Msk = 0x10 + // Bit DMA_RX_I_SRAM_2_R. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_2_R = 0x10 + // Position of DMA_RX_I_SRAM_2_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_2_W_Pos = 0x5 + // Bit mask of DMA_RX_I_SRAM_2_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_2_W_Msk = 0x20 + // Bit DMA_RX_I_SRAM_2_W. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_2_W = 0x20 + // Position of DMA_RX_I_SRAM_3_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_3_R_Pos = 0x6 + // Bit mask of DMA_RX_I_SRAM_3_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_3_R_Msk = 0x40 + // Bit DMA_RX_I_SRAM_3_R. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_3_R = 0x40 + // Position of DMA_RX_I_SRAM_3_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_3_W_Pos = 0x7 + // Bit mask of DMA_RX_I_SRAM_3_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_3_W_Msk = 0x80 + // Bit DMA_RX_I_SRAM_3_W. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_3_W = 0x80 + // Position of DMA_RX_I_SRAM_4_SPLTADDR field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_SPLTADDR_Pos = 0x8 + // Bit mask of DMA_RX_I_SRAM_4_SPLTADDR field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_SPLTADDR_Msk = 0x1ffff00 + // Position of DMA_RX_I_SRAM_4_L_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_L_R_Pos = 0x19 + // Bit mask of DMA_RX_I_SRAM_4_L_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_L_R_Msk = 0x2000000 + // Bit DMA_RX_I_SRAM_4_L_R. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_L_R = 0x2000000 + // Position of DMA_RX_I_SRAM_4_L_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_L_W_Pos = 0x1a + // Bit mask of DMA_RX_I_SRAM_4_L_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_L_W_Msk = 0x4000000 + // Bit DMA_RX_I_SRAM_4_L_W. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_L_W = 0x4000000 + // Position of DMA_RX_I_SRAM_4_H_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_H_R_Pos = 0x1b + // Bit mask of DMA_RX_I_SRAM_4_H_R field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_H_R_Msk = 0x8000000 + // Bit DMA_RX_I_SRAM_4_H_R. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_H_R = 0x8000000 + // Position of DMA_RX_I_SRAM_4_H_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_H_W_Pos = 0x1c + // Bit mask of DMA_RX_I_SRAM_4_H_W field. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_H_W_Msk = 0x10000000 + // Bit DMA_RX_I_SRAM_4_H_W. + PMS_DMA_RX_I_1_DMA_RX_I_SRAM_4_H_W = 0x10000000 + + // DMA_RX_I_2: RX Copy DMA permission control register 2. + // Position of DMA_RX_I_ILG_CLR field. + PMS_DMA_RX_I_2_DMA_RX_I_ILG_CLR_Pos = 0x0 + // Bit mask of DMA_RX_I_ILG_CLR field. + PMS_DMA_RX_I_2_DMA_RX_I_ILG_CLR_Msk = 0x1 + // Bit DMA_RX_I_ILG_CLR. + PMS_DMA_RX_I_2_DMA_RX_I_ILG_CLR = 0x1 + // Position of DMA_RX_I_ILG_EN field. + PMS_DMA_RX_I_2_DMA_RX_I_ILG_EN_Pos = 0x1 + // Bit mask of DMA_RX_I_ILG_EN field. + PMS_DMA_RX_I_2_DMA_RX_I_ILG_EN_Msk = 0x2 + // Bit DMA_RX_I_ILG_EN. + PMS_DMA_RX_I_2_DMA_RX_I_ILG_EN = 0x2 + // Position of DMA_RX_I_ILG_INTR field. + PMS_DMA_RX_I_2_DMA_RX_I_ILG_INTR_Pos = 0x2 + // Bit mask of DMA_RX_I_ILG_INTR field. + PMS_DMA_RX_I_2_DMA_RX_I_ILG_INTR_Msk = 0x4 + // Bit DMA_RX_I_ILG_INTR. + PMS_DMA_RX_I_2_DMA_RX_I_ILG_INTR = 0x4 + + // DMA_RX_I_3: RX Copy DMA status register. + // Position of DMA_RX_I_ILG_ST field. + PMS_DMA_RX_I_3_DMA_RX_I_ILG_ST_Pos = 0x0 + // Bit mask of DMA_RX_I_ILG_ST field. + PMS_DMA_RX_I_3_DMA_RX_I_ILG_ST_Msk = 0x7fffff + + // DMA_TX_I_0: TX Copy DMA permission control register 0. + // Position of DMA_TX_I_LOCK field. + PMS_DMA_TX_I_0_DMA_TX_I_LOCK_Pos = 0x0 + // Bit mask of DMA_TX_I_LOCK field. + PMS_DMA_TX_I_0_DMA_TX_I_LOCK_Msk = 0x1 + // Bit DMA_TX_I_LOCK. + PMS_DMA_TX_I_0_DMA_TX_I_LOCK = 0x1 + + // DMA_TX_I_1: TX Copy DMA permission control register 1. + // Position of DMA_TX_I_SRAM_0_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_0_R_Pos = 0x0 + // Bit mask of DMA_TX_I_SRAM_0_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_0_R_Msk = 0x1 + // Bit DMA_TX_I_SRAM_0_R. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_0_R = 0x1 + // Position of DMA_TX_I_SRAM_0_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_0_W_Pos = 0x1 + // Bit mask of DMA_TX_I_SRAM_0_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_0_W_Msk = 0x2 + // Bit DMA_TX_I_SRAM_0_W. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_0_W = 0x2 + // Position of DMA_TX_I_SRAM_1_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_1_R_Pos = 0x2 + // Bit mask of DMA_TX_I_SRAM_1_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_1_R_Msk = 0x4 + // Bit DMA_TX_I_SRAM_1_R. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_1_R = 0x4 + // Position of DMA_TX_I_SRAM_1_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_1_W_Pos = 0x3 + // Bit mask of DMA_TX_I_SRAM_1_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_1_W_Msk = 0x8 + // Bit DMA_TX_I_SRAM_1_W. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_1_W = 0x8 + // Position of DMA_TX_I_SRAM_2_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_2_R_Pos = 0x4 + // Bit mask of DMA_TX_I_SRAM_2_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_2_R_Msk = 0x10 + // Bit DMA_TX_I_SRAM_2_R. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_2_R = 0x10 + // Position of DMA_TX_I_SRAM_2_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_2_W_Pos = 0x5 + // Bit mask of DMA_TX_I_SRAM_2_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_2_W_Msk = 0x20 + // Bit DMA_TX_I_SRAM_2_W. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_2_W = 0x20 + // Position of DMA_TX_I_SRAM_3_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_3_R_Pos = 0x6 + // Bit mask of DMA_TX_I_SRAM_3_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_3_R_Msk = 0x40 + // Bit DMA_TX_I_SRAM_3_R. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_3_R = 0x40 + // Position of DMA_TX_I_SRAM_3_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_3_W_Pos = 0x7 + // Bit mask of DMA_TX_I_SRAM_3_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_3_W_Msk = 0x80 + // Bit DMA_TX_I_SRAM_3_W. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_3_W = 0x80 + // Position of DMA_TX_I_SRAM_4_SPLTADDR field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_SPLTADDR_Pos = 0x8 + // Bit mask of DMA_TX_I_SRAM_4_SPLTADDR field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_SPLTADDR_Msk = 0x1ffff00 + // Position of DMA_TX_I_SRAM_4_L_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_L_R_Pos = 0x19 + // Bit mask of DMA_TX_I_SRAM_4_L_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_L_R_Msk = 0x2000000 + // Bit DMA_TX_I_SRAM_4_L_R. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_L_R = 0x2000000 + // Position of DMA_TX_I_SRAM_4_L_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_L_W_Pos = 0x1a + // Bit mask of DMA_TX_I_SRAM_4_L_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_L_W_Msk = 0x4000000 + // Bit DMA_TX_I_SRAM_4_L_W. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_L_W = 0x4000000 + // Position of DMA_TX_I_SRAM_4_H_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_H_R_Pos = 0x1b + // Bit mask of DMA_TX_I_SRAM_4_H_R field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_H_R_Msk = 0x8000000 + // Bit DMA_TX_I_SRAM_4_H_R. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_H_R = 0x8000000 + // Position of DMA_TX_I_SRAM_4_H_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_H_W_Pos = 0x1c + // Bit mask of DMA_TX_I_SRAM_4_H_W field. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_H_W_Msk = 0x10000000 + // Bit DMA_TX_I_SRAM_4_H_W. + PMS_DMA_TX_I_1_DMA_TX_I_SRAM_4_H_W = 0x10000000 + + // DMA_TX_I_2: TX Copy DMA permission control register 2. + // Position of DMA_TX_I_ILG_CLR field. + PMS_DMA_TX_I_2_DMA_TX_I_ILG_CLR_Pos = 0x0 + // Bit mask of DMA_TX_I_ILG_CLR field. + PMS_DMA_TX_I_2_DMA_TX_I_ILG_CLR_Msk = 0x1 + // Bit DMA_TX_I_ILG_CLR. + PMS_DMA_TX_I_2_DMA_TX_I_ILG_CLR = 0x1 + // Position of DMA_TX_I_ILG_EN field. + PMS_DMA_TX_I_2_DMA_TX_I_ILG_EN_Pos = 0x1 + // Bit mask of DMA_TX_I_ILG_EN field. + PMS_DMA_TX_I_2_DMA_TX_I_ILG_EN_Msk = 0x2 + // Bit DMA_TX_I_ILG_EN. + PMS_DMA_TX_I_2_DMA_TX_I_ILG_EN = 0x2 + // Position of DMA_TX_I_ILG_INTR field. + PMS_DMA_TX_I_2_DMA_TX_I_ILG_INTR_Pos = 0x2 + // Bit mask of DMA_TX_I_ILG_INTR field. + PMS_DMA_TX_I_2_DMA_TX_I_ILG_INTR_Msk = 0x4 + // Bit DMA_TX_I_ILG_INTR. + PMS_DMA_TX_I_2_DMA_TX_I_ILG_INTR = 0x4 + + // DMA_TX_I_3: TX Copy DMA status register. + // Position of DMA_TX_I_ILG_ST field. + PMS_DMA_TX_I_3_DMA_TX_I_ILG_ST_Pos = 0x0 + // Bit mask of DMA_TX_I_ILG_ST field. + PMS_DMA_TX_I_3_DMA_TX_I_ILG_ST_Msk = 0x7fffff + + // PRO_BOOT_LOCATION_0: Boot permission control register 0. + // Position of PRO_BOOT_LOCATION_LOCK field. + PMS_PRO_BOOT_LOCATION_0_PRO_BOOT_LOCATION_LOCK_Pos = 0x0 + // Bit mask of PRO_BOOT_LOCATION_LOCK field. + PMS_PRO_BOOT_LOCATION_0_PRO_BOOT_LOCATION_LOCK_Msk = 0x1 + // Bit PRO_BOOT_LOCATION_LOCK. + PMS_PRO_BOOT_LOCATION_0_PRO_BOOT_LOCATION_LOCK = 0x1 + + // PRO_BOOT_LOCATION_1: Boot permission control register 1. + // Position of PRO_BOOT_REMAP field. + PMS_PRO_BOOT_LOCATION_1_PRO_BOOT_REMAP_Pos = 0x0 + // Bit mask of PRO_BOOT_REMAP field. + PMS_PRO_BOOT_LOCATION_1_PRO_BOOT_REMAP_Msk = 0x1 + // Bit PRO_BOOT_REMAP. + PMS_PRO_BOOT_LOCATION_1_PRO_BOOT_REMAP = 0x1 + + // CACHE_SOURCE_0: Cache access permission control register 0. + // Position of CACHE_SOURCE_LOCK field. + PMS_CACHE_SOURCE_0_CACHE_SOURCE_LOCK_Pos = 0x0 + // Bit mask of CACHE_SOURCE_LOCK field. + PMS_CACHE_SOURCE_0_CACHE_SOURCE_LOCK_Msk = 0x1 + // Bit CACHE_SOURCE_LOCK. + PMS_CACHE_SOURCE_0_CACHE_SOURCE_LOCK = 0x1 + + // CACHE_SOURCE_1: Cache access permission control register 1. + // Position of PRO_CACHE_I_SOURCE_PRO_IRAM1 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IRAM1_Pos = 0x0 + // Bit mask of PRO_CACHE_I_SOURCE_PRO_IRAM1 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IRAM1_Msk = 0x1 + // Bit PRO_CACHE_I_SOURCE_PRO_IRAM1. + PMS_CACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IRAM1 = 0x1 + // Position of PRO_CACHE_I_SOURCE_PRO_IROM0 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IROM0_Pos = 0x1 + // Bit mask of PRO_CACHE_I_SOURCE_PRO_IROM0 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IROM0_Msk = 0x2 + // Bit PRO_CACHE_I_SOURCE_PRO_IROM0. + PMS_CACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_IROM0 = 0x2 + // Position of PRO_CACHE_I_SOURCE_PRO_DROM0 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_DROM0_Pos = 0x2 + // Bit mask of PRO_CACHE_I_SOURCE_PRO_DROM0 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_DROM0_Msk = 0x4 + // Bit PRO_CACHE_I_SOURCE_PRO_DROM0. + PMS_CACHE_SOURCE_1_PRO_CACHE_I_SOURCE_PRO_DROM0 = 0x4 + // Position of PRO_CACHE_D_SOURCE_PRO_DRAM0 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DRAM0_Pos = 0x3 + // Bit mask of PRO_CACHE_D_SOURCE_PRO_DRAM0 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DRAM0_Msk = 0x8 + // Bit PRO_CACHE_D_SOURCE_PRO_DRAM0. + PMS_CACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DRAM0 = 0x8 + // Position of PRO_CACHE_D_SOURCE_PRO_DPORT field. + PMS_CACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DPORT_Pos = 0x4 + // Bit mask of PRO_CACHE_D_SOURCE_PRO_DPORT field. + PMS_CACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DPORT_Msk = 0x10 + // Bit PRO_CACHE_D_SOURCE_PRO_DPORT. + PMS_CACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DPORT = 0x10 + // Position of PRO_CACHE_D_SOURCE_PRO_DROM0 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DROM0_Pos = 0x5 + // Bit mask of PRO_CACHE_D_SOURCE_PRO_DROM0 field. + PMS_CACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DROM0_Msk = 0x20 + // Bit PRO_CACHE_D_SOURCE_PRO_DROM0. + PMS_CACHE_SOURCE_1_PRO_CACHE_D_SOURCE_PRO_DROM0 = 0x20 + + // APB_PERIPHERAL_0: Peripheral access permission control register 0. + // Position of APB_PERIPHERAL_LOCK field. + PMS_APB_PERIPHERAL_0_APB_PERIPHERAL_LOCK_Pos = 0x0 + // Bit mask of APB_PERIPHERAL_LOCK field. + PMS_APB_PERIPHERAL_0_APB_PERIPHERAL_LOCK_Msk = 0x1 + // Bit APB_PERIPHERAL_LOCK. + PMS_APB_PERIPHERAL_0_APB_PERIPHERAL_LOCK = 0x1 + + // APB_PERIPHERAL_1: Peripheral access permission control register 1. + // Position of APB_PERIPHERAL_SPLIT_BURST field. + PMS_APB_PERIPHERAL_1_APB_PERIPHERAL_SPLIT_BURST_Pos = 0x0 + // Bit mask of APB_PERIPHERAL_SPLIT_BURST field. + PMS_APB_PERIPHERAL_1_APB_PERIPHERAL_SPLIT_BURST_Msk = 0x1 + // Bit APB_PERIPHERAL_SPLIT_BURST. + PMS_APB_PERIPHERAL_1_APB_PERIPHERAL_SPLIT_BURST = 0x1 + + // OCCUPY_0: Occupy permission control register 0. + // Position of OCCUPY_LOCK field. + PMS_OCCUPY_0_OCCUPY_LOCK_Pos = 0x0 + // Bit mask of OCCUPY_LOCK field. + PMS_OCCUPY_0_OCCUPY_LOCK_Msk = 0x1 + // Bit OCCUPY_LOCK. + PMS_OCCUPY_0_OCCUPY_LOCK = 0x1 + + // OCCUPY_1: Occupy permission control register 1. + // Position of OCCUPY_CACHE field. + PMS_OCCUPY_1_OCCUPY_CACHE_Pos = 0x0 + // Bit mask of OCCUPY_CACHE field. + PMS_OCCUPY_1_OCCUPY_CACHE_Msk = 0xf + + // OCCUPY_2: Occupy permission control register 2. + // Position of OCCUPY_MAC_DUMP field. + PMS_OCCUPY_2_OCCUPY_MAC_DUMP_Pos = 0x0 + // Bit mask of OCCUPY_MAC_DUMP field. + PMS_OCCUPY_2_OCCUPY_MAC_DUMP_Msk = 0xf + + // OCCUPY_3: Occupy permission control register 3. + // Position of OCCUPY_PRO_TRACE field. + PMS_OCCUPY_3_OCCUPY_PRO_TRACE_Pos = 0x0 + // Bit mask of OCCUPY_PRO_TRACE field. + PMS_OCCUPY_3_OCCUPY_PRO_TRACE_Msk = 0x3ffff + + // CACHE_TAG_ACCESS_0: Cache tag permission control register 0. + // Position of CACHE_TAG_ACCESS_LOCK field. + PMS_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK_Pos = 0x0 + // Bit mask of CACHE_TAG_ACCESS_LOCK field. + PMS_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK_Msk = 0x1 + // Bit CACHE_TAG_ACCESS_LOCK. + PMS_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK = 0x1 + + // CACHE_TAG_ACCESS_1: Cache tag permission control register 1. + // Position of PRO_I_TAG_RD_ACS field. + PMS_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS_Pos = 0x0 + // Bit mask of PRO_I_TAG_RD_ACS field. + PMS_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS_Msk = 0x1 + // Bit PRO_I_TAG_RD_ACS. + PMS_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS = 0x1 + // Position of PRO_I_TAG_WR_ACS field. + PMS_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS_Pos = 0x1 + // Bit mask of PRO_I_TAG_WR_ACS field. + PMS_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS_Msk = 0x2 + // Bit PRO_I_TAG_WR_ACS. + PMS_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS = 0x2 + // Position of PRO_D_TAG_RD_ACS field. + PMS_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS_Pos = 0x2 + // Bit mask of PRO_D_TAG_RD_ACS field. + PMS_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS_Msk = 0x4 + // Bit PRO_D_TAG_RD_ACS. + PMS_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS = 0x4 + // Position of PRO_D_TAG_WR_ACS field. + PMS_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS_Pos = 0x3 + // Bit mask of PRO_D_TAG_WR_ACS field. + PMS_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS_Msk = 0x8 + // Bit PRO_D_TAG_WR_ACS. + PMS_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS = 0x8 + + // CACHE_MMU_ACCESS_0: Cache MMU permission control register 0. + // Position of CACHE_MMU_ACCESS_LOCK field. + PMS_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK_Pos = 0x0 + // Bit mask of CACHE_MMU_ACCESS_LOCK field. + PMS_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK_Msk = 0x1 + // Bit CACHE_MMU_ACCESS_LOCK. + PMS_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK = 0x1 + + // CACHE_MMU_ACCESS_1: Cache MMU permission control register 1. + // Position of PRO_MMU_RD_ACS field. + PMS_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS_Pos = 0x0 + // Bit mask of PRO_MMU_RD_ACS field. + PMS_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS_Msk = 0x1 + // Bit PRO_MMU_RD_ACS. + PMS_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS = 0x1 + // Position of PRO_MMU_WR_ACS field. + PMS_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS_Pos = 0x1 + // Bit mask of PRO_MMU_WR_ACS field. + PMS_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS_Msk = 0x2 + // Bit PRO_MMU_WR_ACS. + PMS_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS = 0x2 + + // APB_PERIPHERAL_INTR: PeribBus2 permission control register. + // Position of APB_PERI_BYTE_ERROR_CLR field. + PMS_APB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_CLR_Pos = 0x0 + // Bit mask of APB_PERI_BYTE_ERROR_CLR field. + PMS_APB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_CLR_Msk = 0x1 + // Bit APB_PERI_BYTE_ERROR_CLR. + PMS_APB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_CLR = 0x1 + // Position of APB_PERI_BYTE_ERROR_EN field. + PMS_APB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_EN_Pos = 0x1 + // Bit mask of APB_PERI_BYTE_ERROR_EN field. + PMS_APB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_EN_Msk = 0x2 + // Bit APB_PERI_BYTE_ERROR_EN. + PMS_APB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_EN = 0x2 + // Position of APB_PERI_BYTE_ERROR_INTR field. + PMS_APB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_INTR_Pos = 0x2 + // Bit mask of APB_PERI_BYTE_ERROR_INTR field. + PMS_APB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_INTR_Msk = 0x4 + // Bit APB_PERI_BYTE_ERROR_INTR. + PMS_APB_PERIPHERAL_INTR_APB_PERI_BYTE_ERROR_INTR = 0x4 + + // APB_PERIPHERAL_STATUS: PeribBus2 peripheral access status register. + // Position of APB_PERI_BYTE_ERROR_ADDR field. + PMS_APB_PERIPHERAL_STATUS_APB_PERI_BYTE_ERROR_ADDR_Pos = 0x0 + // Bit mask of APB_PERI_BYTE_ERROR_ADDR field. + PMS_APB_PERIPHERAL_STATUS_APB_PERI_BYTE_ERROR_ADDR_Msk = 0xffffffff + + // CPU_PERIPHERAL_INTR: PeribBus1 permission control register. + // Position of CPU_PERI_BYTE_ERROR_CLR field. + PMS_CPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_CLR_Pos = 0x0 + // Bit mask of CPU_PERI_BYTE_ERROR_CLR field. + PMS_CPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_CLR_Msk = 0x1 + // Bit CPU_PERI_BYTE_ERROR_CLR. + PMS_CPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_CLR = 0x1 + // Position of CPU_PERI_BYTE_ERROR_EN field. + PMS_CPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_EN_Pos = 0x1 + // Bit mask of CPU_PERI_BYTE_ERROR_EN field. + PMS_CPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_EN_Msk = 0x2 + // Bit CPU_PERI_BYTE_ERROR_EN. + PMS_CPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_EN = 0x2 + // Position of CPU_PERI_BYTE_ERROR_INTR field. + PMS_CPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_INTR_Pos = 0x2 + // Bit mask of CPU_PERI_BYTE_ERROR_INTR field. + PMS_CPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_INTR_Msk = 0x4 + // Bit CPU_PERI_BYTE_ERROR_INTR. + PMS_CPU_PERIPHERAL_INTR_CPU_PERI_BYTE_ERROR_INTR = 0x4 + + // CPU_PERIPHERAL_STATUS: PeribBus1 peripheral access status register. + // Position of CPU_PERI_BYTE_ERROR_ADDR field. + PMS_CPU_PERIPHERAL_STATUS_CPU_PERI_BYTE_ERROR_ADDR_Pos = 0x0 + // Bit mask of CPU_PERI_BYTE_ERROR_ADDR field. + PMS_CPU_PERIPHERAL_STATUS_CPU_PERI_BYTE_ERROR_ADDR_Msk = 0xffffffff + + // CLOCK_GATE: Clock gate register of permission control. + // Position of CLK_EN field. + PMS_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + PMS_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + PMS_CLOCK_GATE_CLK_EN = 0x1 + + // DATE: Version control register. + // Position of DATE field. + PMS_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PMS_DATE_DATE_Msk = 0xfffffff +) + +// Constants for RMT: Remote Control +const ( + // CH0DATA: The read and write data register for CHANNEL%s by apb fifo access. + // Position of DATA field. + RMT_CHDATA_DATA_Pos = 0x0 + // Bit mask of DATA field. + RMT_CHDATA_DATA_Msk = 0xffffffff + + // CH0CONF0: Channel %s configure register 0 + // Position of DIV_CNT field. + RMT_CHCONF0_DIV_CNT_Pos = 0x0 + // Bit mask of DIV_CNT field. + RMT_CHCONF0_DIV_CNT_Msk = 0xff + // Position of IDLE_THRES field. + RMT_CHCONF0_IDLE_THRES_Pos = 0x8 + // Bit mask of IDLE_THRES field. + RMT_CHCONF0_IDLE_THRES_Msk = 0xffff00 + // Position of MEM_SIZE field. + RMT_CHCONF0_MEM_SIZE_Pos = 0x18 + // Bit mask of MEM_SIZE field. + RMT_CHCONF0_MEM_SIZE_Msk = 0x7000000 + // Position of CARRIER_EFF_EN field. + RMT_CHCONF0_CARRIER_EFF_EN_Pos = 0x1b + // Bit mask of CARRIER_EFF_EN field. + RMT_CHCONF0_CARRIER_EFF_EN_Msk = 0x8000000 + // Bit CARRIER_EFF_EN. + RMT_CHCONF0_CARRIER_EFF_EN = 0x8000000 + // Position of CARRIER_EN field. + RMT_CHCONF0_CARRIER_EN_Pos = 0x1c + // Bit mask of CARRIER_EN field. + RMT_CHCONF0_CARRIER_EN_Msk = 0x10000000 + // Bit CARRIER_EN. + RMT_CHCONF0_CARRIER_EN = 0x10000000 + // Position of CARRIER_OUT_LV field. + RMT_CHCONF0_CARRIER_OUT_LV_Pos = 0x1d + // Bit mask of CARRIER_OUT_LV field. + RMT_CHCONF0_CARRIER_OUT_LV_Msk = 0x20000000 + // Bit CARRIER_OUT_LV. + RMT_CHCONF0_CARRIER_OUT_LV = 0x20000000 + + // CH0CONF1: Channel %s configure register 1 + // Position of TX_START field. + RMT_CHCONF1_TX_START_Pos = 0x0 + // Bit mask of TX_START field. + RMT_CHCONF1_TX_START_Msk = 0x1 + // Bit TX_START. + RMT_CHCONF1_TX_START = 0x1 + // Position of RX_EN field. + RMT_CHCONF1_RX_EN_Pos = 0x1 + // Bit mask of RX_EN field. + RMT_CHCONF1_RX_EN_Msk = 0x2 + // Bit RX_EN. + RMT_CHCONF1_RX_EN = 0x2 + // Position of MEM_WR_RST field. + RMT_CHCONF1_MEM_WR_RST_Pos = 0x2 + // Bit mask of MEM_WR_RST field. + RMT_CHCONF1_MEM_WR_RST_Msk = 0x4 + // Bit MEM_WR_RST. + RMT_CHCONF1_MEM_WR_RST = 0x4 + // Position of MEM_RD_RST field. + RMT_CHCONF1_MEM_RD_RST_Pos = 0x3 + // Bit mask of MEM_RD_RST field. + RMT_CHCONF1_MEM_RD_RST_Msk = 0x8 + // Bit MEM_RD_RST. + RMT_CHCONF1_MEM_RD_RST = 0x8 + // Position of APB_MEM_RST field. + RMT_CHCONF1_APB_MEM_RST_Pos = 0x4 + // Bit mask of APB_MEM_RST field. + RMT_CHCONF1_APB_MEM_RST_Msk = 0x10 + // Bit APB_MEM_RST. + RMT_CHCONF1_APB_MEM_RST = 0x10 + // Position of MEM_OWNER field. + RMT_CHCONF1_MEM_OWNER_Pos = 0x5 + // Bit mask of MEM_OWNER field. + RMT_CHCONF1_MEM_OWNER_Msk = 0x20 + // Bit MEM_OWNER. + RMT_CHCONF1_MEM_OWNER = 0x20 + // Position of TX_CONTI_MODE field. + RMT_CHCONF1_TX_CONTI_MODE_Pos = 0x6 + // Bit mask of TX_CONTI_MODE field. + RMT_CHCONF1_TX_CONTI_MODE_Msk = 0x40 + // Bit TX_CONTI_MODE. + RMT_CHCONF1_TX_CONTI_MODE = 0x40 + // Position of RX_FILTER_EN field. + RMT_CHCONF1_RX_FILTER_EN_Pos = 0x7 + // Bit mask of RX_FILTER_EN field. + RMT_CHCONF1_RX_FILTER_EN_Msk = 0x80 + // Bit RX_FILTER_EN. + RMT_CHCONF1_RX_FILTER_EN = 0x80 + // Position of RX_FILTER_THRES field. + RMT_CHCONF1_RX_FILTER_THRES_Pos = 0x8 + // Bit mask of RX_FILTER_THRES field. + RMT_CHCONF1_RX_FILTER_THRES_Msk = 0xff00 + // Position of CHK_RX_CARRIER_EN field. + RMT_CHCONF1_CHK_RX_CARRIER_EN_Pos = 0x10 + // Bit mask of CHK_RX_CARRIER_EN field. + RMT_CHCONF1_CHK_RX_CARRIER_EN_Msk = 0x10000 + // Bit CHK_RX_CARRIER_EN. + RMT_CHCONF1_CHK_RX_CARRIER_EN = 0x10000 + // Position of REF_ALWAYS_ON field. + RMT_CHCONF1_REF_ALWAYS_ON_Pos = 0x11 + // Bit mask of REF_ALWAYS_ON field. + RMT_CHCONF1_REF_ALWAYS_ON_Msk = 0x20000 + // Bit REF_ALWAYS_ON. + RMT_CHCONF1_REF_ALWAYS_ON = 0x20000 + // Position of IDLE_OUT_LV field. + RMT_CHCONF1_IDLE_OUT_LV_Pos = 0x12 + // Bit mask of IDLE_OUT_LV field. + RMT_CHCONF1_IDLE_OUT_LV_Msk = 0x40000 + // Bit IDLE_OUT_LV. + RMT_CHCONF1_IDLE_OUT_LV = 0x40000 + // Position of IDLE_OUT_EN field. + RMT_CHCONF1_IDLE_OUT_EN_Pos = 0x13 + // Bit mask of IDLE_OUT_EN field. + RMT_CHCONF1_IDLE_OUT_EN_Msk = 0x80000 + // Bit IDLE_OUT_EN. + RMT_CHCONF1_IDLE_OUT_EN = 0x80000 + // Position of TX_STOP field. + RMT_CHCONF1_TX_STOP_Pos = 0x14 + // Bit mask of TX_STOP field. + RMT_CHCONF1_TX_STOP_Msk = 0x100000 + // Bit TX_STOP. + RMT_CHCONF1_TX_STOP = 0x100000 + + // CH0STATUS: Channel %s status register + // Position of MEM_WADDR_EX field. + RMT_CHSTATUS_MEM_WADDR_EX_Pos = 0x0 + // Bit mask of MEM_WADDR_EX field. + RMT_CHSTATUS_MEM_WADDR_EX_Msk = 0x1ff + // Position of MEM_RADDR_EX field. + RMT_CHSTATUS_MEM_RADDR_EX_Pos = 0xa + // Bit mask of MEM_RADDR_EX field. + RMT_CHSTATUS_MEM_RADDR_EX_Msk = 0x7fc00 + // Position of STATE field. + RMT_CHSTATUS_STATE_Pos = 0x14 + // Bit mask of STATE field. + RMT_CHSTATUS_STATE_Msk = 0x700000 + // Position of MEM_OWNER_ERR field. + RMT_CHSTATUS_MEM_OWNER_ERR_Pos = 0x17 + // Bit mask of MEM_OWNER_ERR field. + RMT_CHSTATUS_MEM_OWNER_ERR_Msk = 0x800000 + // Bit MEM_OWNER_ERR. + RMT_CHSTATUS_MEM_OWNER_ERR = 0x800000 + // Position of MEM_FULL field. + RMT_CHSTATUS_MEM_FULL_Pos = 0x18 + // Bit mask of MEM_FULL field. + RMT_CHSTATUS_MEM_FULL_Msk = 0x1000000 + // Bit MEM_FULL. + RMT_CHSTATUS_MEM_FULL = 0x1000000 + // Position of MEM_EMPTY field. + RMT_CHSTATUS_MEM_EMPTY_Pos = 0x19 + // Bit mask of MEM_EMPTY field. + RMT_CHSTATUS_MEM_EMPTY_Msk = 0x2000000 + // Bit MEM_EMPTY. + RMT_CHSTATUS_MEM_EMPTY = 0x2000000 + // Position of APB_MEM_WR_ERR field. + RMT_CHSTATUS_APB_MEM_WR_ERR_Pos = 0x1a + // Bit mask of APB_MEM_WR_ERR field. + RMT_CHSTATUS_APB_MEM_WR_ERR_Msk = 0x4000000 + // Bit APB_MEM_WR_ERR. + RMT_CHSTATUS_APB_MEM_WR_ERR = 0x4000000 + // Position of APB_MEM_RD_ERR field. + RMT_CHSTATUS_APB_MEM_RD_ERR_Pos = 0x1b + // Bit mask of APB_MEM_RD_ERR field. + RMT_CHSTATUS_APB_MEM_RD_ERR_Msk = 0x8000000 + // Bit APB_MEM_RD_ERR. + RMT_CHSTATUS_APB_MEM_RD_ERR = 0x8000000 + + // CH0ADDR: Channel %s address register + // Position of APB_MEM_WADDR field. + RMT_CHADDR_APB_MEM_WADDR_Pos = 0x0 + // Bit mask of APB_MEM_WADDR field. + RMT_CHADDR_APB_MEM_WADDR_Msk = 0x1ff + // Position of APB_MEM_RADDR field. + RMT_CHADDR_APB_MEM_RADDR_Pos = 0xa + // Bit mask of APB_MEM_RADDR field. + RMT_CHADDR_APB_MEM_RADDR_Msk = 0x7fc00 + + // INT_RAW: Raw interrupt status + // Position of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_RAW_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Pos = 0x1 + // Bit mask of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Msk = 0x2 + // Bit CH_s_RX_END. + RMT_INT_RAW_CH_s_RX_END = 0x2 + // Position of CH_s_ERR field. + RMT_INT_RAW_CH_s_ERR_Pos = 0x2 + // Bit mask of CH_s_ERR field. + RMT_INT_RAW_CH_s_ERR_Msk = 0x4 + // Bit CH_s_ERR. + RMT_INT_RAW_CH_s_ERR = 0x4 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Pos = 0xc + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Msk = 0x1000 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_RAW_CH_s_TX_THR_EVENT = 0x1000 + // Position of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Pos = 0x10 + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Msk = 0x10000 + // Bit CH_s_TX_LOOP. + RMT_INT_RAW_CH_s_TX_LOOP = 0x10000 + + // INT_ST: Masked interrupt status + // Position of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ST_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Pos = 0x1 + // Bit mask of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Msk = 0x2 + // Bit CH_s_RX_END. + RMT_INT_ST_CH_s_RX_END = 0x2 + // Position of CH_s_ERR field. + RMT_INT_ST_CH_s_ERR_Pos = 0x2 + // Bit mask of CH_s_ERR field. + RMT_INT_ST_CH_s_ERR_Msk = 0x4 + // Bit CH_s_ERR. + RMT_INT_ST_CH_s_ERR = 0x4 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Pos = 0xc + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Msk = 0x1000 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ST_CH_s_TX_THR_EVENT = 0x1000 + // Position of CH_s_TX_LOOP field. + RMT_INT_ST_CH_s_TX_LOOP_Pos = 0x10 + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_ST_CH_s_TX_LOOP_Msk = 0x10000 + // Bit CH_s_TX_LOOP. + RMT_INT_ST_CH_s_TX_LOOP = 0x10000 + + // INT_ENA: Interrupt enable bits + // Position of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ENA_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Pos = 0x1 + // Bit mask of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Msk = 0x2 + // Bit CH_s_RX_END. + RMT_INT_ENA_CH_s_RX_END = 0x2 + // Position of CH_s_ERR field. + RMT_INT_ENA_CH_s_ERR_Pos = 0x2 + // Bit mask of CH_s_ERR field. + RMT_INT_ENA_CH_s_ERR_Msk = 0x4 + // Bit CH_s_ERR. + RMT_INT_ENA_CH_s_ERR = 0x4 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Pos = 0xc + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Msk = 0x1000 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ENA_CH_s_TX_THR_EVENT = 0x1000 + // Position of CH_s_TX_LOOP field. + RMT_INT_ENA_CH_s_TX_LOOP_Pos = 0x10 + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_ENA_CH_s_TX_LOOP_Msk = 0x10000 + // Bit CH_s_TX_LOOP. + RMT_INT_ENA_CH_s_TX_LOOP = 0x10000 + + // INT_CLR: Interrupt clear bits + // Position of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_CLR_CH_s_TX_END = 0x1 + // Position of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Pos = 0x1 + // Bit mask of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Msk = 0x2 + // Bit CH_s_RX_END. + RMT_INT_CLR_CH_s_RX_END = 0x2 + // Position of CH_s_ERR field. + RMT_INT_CLR_CH_s_ERR_Pos = 0x2 + // Bit mask of CH_s_ERR field. + RMT_INT_CLR_CH_s_ERR_Msk = 0x4 + // Bit CH_s_ERR. + RMT_INT_CLR_CH_s_ERR = 0x4 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Pos = 0xc + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Msk = 0x1000 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_CLR_CH_s_TX_THR_EVENT = 0x1000 + // Position of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Pos = 0x10 + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Msk = 0x10000 + // Bit CH_s_TX_LOOP. + RMT_INT_CLR_CH_s_TX_LOOP = 0x10000 + + // CH0CARRIER_DUTY: Channel %s duty cycle configuration register + // Position of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Pos = 0x0 + // Bit mask of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Msk = 0xffff + // Position of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Pos = 0x10 + // Bit mask of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Msk = 0xffff0000 + + // CH0_TX_LIM: Channel %s Tx event configuration register + // Position of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Pos = 0x0 + // Bit mask of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Msk = 0x1ff + // Position of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Pos = 0x9 + // Bit mask of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Msk = 0x7fe00 + // Position of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Pos = 0x13 + // Bit mask of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Msk = 0x80000 + // Bit TX_LOOP_CNT_EN. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN = 0x80000 + // Position of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Pos = 0x14 + // Bit mask of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Msk = 0x100000 + // Bit LOOP_COUNT_RESET. + RMT_CH_TX_LIM_LOOP_COUNT_RESET = 0x100000 + + // APB_CONF: RMT apb configuration register + // Position of APB_FIFO_MASK field. + RMT_APB_CONF_APB_FIFO_MASK_Pos = 0x0 + // Bit mask of APB_FIFO_MASK field. + RMT_APB_CONF_APB_FIFO_MASK_Msk = 0x1 + // Bit APB_FIFO_MASK. + RMT_APB_CONF_APB_FIFO_MASK = 0x1 + // Position of MEM_TX_WRAP_EN field. + RMT_APB_CONF_MEM_TX_WRAP_EN_Pos = 0x1 + // Bit mask of MEM_TX_WRAP_EN field. + RMT_APB_CONF_MEM_TX_WRAP_EN_Msk = 0x2 + // Bit MEM_TX_WRAP_EN. + RMT_APB_CONF_MEM_TX_WRAP_EN = 0x2 + // Position of MEM_CLK_FORCE_ON field. + RMT_APB_CONF_MEM_CLK_FORCE_ON_Pos = 0x2 + // Bit mask of MEM_CLK_FORCE_ON field. + RMT_APB_CONF_MEM_CLK_FORCE_ON_Msk = 0x4 + // Bit MEM_CLK_FORCE_ON. + RMT_APB_CONF_MEM_CLK_FORCE_ON = 0x4 + // Position of MEM_FORCE_PD field. + RMT_APB_CONF_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of MEM_FORCE_PD field. + RMT_APB_CONF_MEM_FORCE_PD_Msk = 0x8 + // Bit MEM_FORCE_PD. + RMT_APB_CONF_MEM_FORCE_PD = 0x8 + // Position of MEM_FORCE_PU field. + RMT_APB_CONF_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of MEM_FORCE_PU field. + RMT_APB_CONF_MEM_FORCE_PU_Msk = 0x10 + // Bit MEM_FORCE_PU. + RMT_APB_CONF_MEM_FORCE_PU = 0x10 + // Position of CLK_EN field. + RMT_APB_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + RMT_APB_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + RMT_APB_CONF_CLK_EN = 0x80000000 + + // TX_SIM: RMT TX synchronous register + // Position of CH0 field. + RMT_TX_SIM_CH0_Pos = 0x0 + // Bit mask of CH0 field. + RMT_TX_SIM_CH0_Msk = 0x1 + // Bit CH0. + RMT_TX_SIM_CH0 = 0x1 + // Position of CH1 field. + RMT_TX_SIM_CH1_Pos = 0x1 + // Bit mask of CH1 field. + RMT_TX_SIM_CH1_Msk = 0x2 + // Bit CH1. + RMT_TX_SIM_CH1 = 0x2 + // Position of CH2 field. + RMT_TX_SIM_CH2_Pos = 0x2 + // Bit mask of CH2 field. + RMT_TX_SIM_CH2_Msk = 0x4 + // Bit CH2. + RMT_TX_SIM_CH2 = 0x4 + // Position of CH3 field. + RMT_TX_SIM_CH3_Pos = 0x3 + // Bit mask of CH3 field. + RMT_TX_SIM_CH3_Msk = 0x8 + // Bit CH3. + RMT_TX_SIM_CH3 = 0x8 + // Position of EN field. + RMT_TX_SIM_EN_Pos = 0x4 + // Bit mask of EN field. + RMT_TX_SIM_EN_Msk = 0x10 + // Bit EN. + RMT_TX_SIM_EN = 0x10 + + // REF_CNT_RST: RMT clock divider reset register + // Position of CH0 field. + RMT_REF_CNT_RST_CH0_Pos = 0x0 + // Bit mask of CH0 field. + RMT_REF_CNT_RST_CH0_Msk = 0x1 + // Bit CH0. + RMT_REF_CNT_RST_CH0 = 0x1 + // Position of CH1 field. + RMT_REF_CNT_RST_CH1_Pos = 0x1 + // Bit mask of CH1 field. + RMT_REF_CNT_RST_CH1_Msk = 0x2 + // Bit CH1. + RMT_REF_CNT_RST_CH1 = 0x2 + // Position of CH2 field. + RMT_REF_CNT_RST_CH2_Pos = 0x2 + // Bit mask of CH2 field. + RMT_REF_CNT_RST_CH2_Msk = 0x4 + // Bit CH2. + RMT_REF_CNT_RST_CH2 = 0x4 + // Position of CH3 field. + RMT_REF_CNT_RST_CH3_Pos = 0x3 + // Bit mask of CH3 field. + RMT_REF_CNT_RST_CH3_Msk = 0x8 + // Bit CH3. + RMT_REF_CNT_RST_CH3 = 0x8 + + // CH0_RX_CARRIER_RM: Channel %s carrier remove register + // Position of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Pos = 0x0 + // Bit mask of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Msk = 0xffff + // Position of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Pos = 0x10 + // Bit mask of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Msk = 0xffff0000 + + // DATE: RMT version register + // Position of DATE field. + RMT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RMT_DATE_DATE_Msk = 0xffffffff +) + +// Constants for RNG: Hardware Random Number Generator +const () + +// Constants for RSA: RSA (Rivest Shamir Adleman) Accelerator +const ( + // M_PRIME: Register to store M' + // Position of M_PRIME field. + RSA_M_PRIME_M_PRIME_Pos = 0x0 + // Bit mask of M_PRIME field. + RSA_M_PRIME_M_PRIME_Msk = 0xffffffff + + // MODE: RSA length mode + // Position of MODE field. + RSA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + RSA_MODE_MODE_Msk = 0x7f + + // CLEAN: RSA clean register + // Position of CLEAN field. + RSA_CLEAN_CLEAN_Pos = 0x0 + // Bit mask of CLEAN field. + RSA_CLEAN_CLEAN_Msk = 0x1 + // Bit CLEAN. + RSA_CLEAN_CLEAN = 0x1 + + // MODEXP_START: Modular exponentiation starting bit + // Position of MODEXP_START field. + RSA_MODEXP_START_MODEXP_START_Pos = 0x0 + // Bit mask of MODEXP_START field. + RSA_MODEXP_START_MODEXP_START_Msk = 0x1 + // Bit MODEXP_START. + RSA_MODEXP_START_MODEXP_START = 0x1 + + // MODMULT_START: Modular multiplication starting bit + // Position of MODMULT_START field. + RSA_MODMULT_START_MODMULT_START_Pos = 0x0 + // Bit mask of MODMULT_START field. + RSA_MODMULT_START_MODMULT_START_Msk = 0x1 + // Bit MODMULT_START. + RSA_MODMULT_START_MODMULT_START = 0x1 + + // MULT_START: Normal multiplication starting bit + // Position of MULT_START field. + RSA_MULT_START_MULT_START_Pos = 0x0 + // Bit mask of MULT_START field. + RSA_MULT_START_MULT_START_Msk = 0x1 + // Bit MULT_START. + RSA_MULT_START_MULT_START = 0x1 + + // IDLE: RSA idle register + // Position of IDLE field. + RSA_IDLE_IDLE_Pos = 0x0 + // Bit mask of IDLE field. + RSA_IDLE_IDLE_Msk = 0x1 + // Bit IDLE. + RSA_IDLE_IDLE = 0x1 + + // CLEAR_INTERRUPT: RSA clear interrupt register + // Position of CLEAR_INTERRUPT field. + RSA_CLEAR_INTERRUPT_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + RSA_CLEAR_INTERRUPT_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + RSA_CLEAR_INTERRUPT_CLEAR_INTERRUPT = 0x1 + + // CONSTANT_TIME: The constant_time option + // Position of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Pos = 0x0 + // Bit mask of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Msk = 0x1 + // Bit CONSTANT_TIME. + RSA_CONSTANT_TIME_CONSTANT_TIME = 0x1 + + // SEARCH_ENABLE: The search option + // Position of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Pos = 0x0 + // Bit mask of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Msk = 0x1 + // Bit SEARCH_ENABLE. + RSA_SEARCH_ENABLE_SEARCH_ENABLE = 0x1 + + // SEARCH_POS: The search position + // Position of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Pos = 0x0 + // Bit mask of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Msk = 0xfff + + // INTERRUPT_ENA: RSA interrupt enable register + // Position of INTERRUPT_ENA field. + RSA_INTERRUPT_ENA_INTERRUPT_ENA_Pos = 0x0 + // Bit mask of INTERRUPT_ENA field. + RSA_INTERRUPT_ENA_INTERRUPT_ENA_Msk = 0x1 + // Bit INTERRUPT_ENA. + RSA_INTERRUPT_ENA_INTERRUPT_ENA = 0x1 + + // DATE: Version control register + // Position of DATE field. + RSA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RSA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for RTC_IO: Low-power Input/Output +const ( + // RTC_GPIO_OUT: RTC GPIO output register + // Position of GPIO_OUT_DATA field. + RTCIO_RTC_GPIO_OUT_GPIO_OUT_DATA_Pos = 0xa + // Bit mask of GPIO_OUT_DATA field. + RTCIO_RTC_GPIO_OUT_GPIO_OUT_DATA_Msk = 0xfffffc00 + + // RTC_GPIO_OUT_W1TS: RTC GPIO output bit set register + // Position of GPIO_OUT_DATA_W1TS field. + RTCIO_RTC_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS_Pos = 0xa + // Bit mask of GPIO_OUT_DATA_W1TS field. + RTCIO_RTC_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_OUT_W1TC: RTC GPIO output bit clear register + // Position of GPIO_OUT_DATA_W1TC field. + RTCIO_RTC_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC_Pos = 0xa + // Bit mask of GPIO_OUT_DATA_W1TC field. + RTCIO_RTC_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE: RTC GPIO output enable register + // Position of REG_RTCIO_REG_GPIO_ENABLE field. + RTCIO_RTC_GPIO_ENABLE_REG_RTCIO_REG_GPIO_ENABLE_Pos = 0xa + // Bit mask of REG_RTCIO_REG_GPIO_ENABLE field. + RTCIO_RTC_GPIO_ENABLE_REG_RTCIO_REG_GPIO_ENABLE_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE_W1TS: RTC GPIO output enable bit set register + // Position of REG_RTCIO_REG_GPIO_ENABLE_W1TS field. + RTCIO_RTC_GPIO_ENABLE_W1TS_REG_RTCIO_REG_GPIO_ENABLE_W1TS_Pos = 0xa + // Bit mask of REG_RTCIO_REG_GPIO_ENABLE_W1TS field. + RTCIO_RTC_GPIO_ENABLE_W1TS_REG_RTCIO_REG_GPIO_ENABLE_W1TS_Msk = 0xfffffc00 + + // ENABLE_W1TC: RTC GPIO output enable bit clear register + // Position of ENABLE_W1TC field. + RTCIO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0xa + // Bit mask of ENABLE_W1TC field. + RTCIO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS: RTC GPIO interrupt status register + // Position of GPIO_STATUS_INT field. + RTCIO_RTC_GPIO_STATUS_GPIO_STATUS_INT_Pos = 0xa + // Bit mask of GPIO_STATUS_INT field. + RTCIO_RTC_GPIO_STATUS_GPIO_STATUS_INT_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS_W1TS: RTC GPIO interrupt status bit set register + // Position of GPIO_STATUS_INT_W1TS field. + RTCIO_RTC_GPIO_STATUS_W1TS_GPIO_STATUS_INT_W1TS_Pos = 0xa + // Bit mask of GPIO_STATUS_INT_W1TS field. + RTCIO_RTC_GPIO_STATUS_W1TS_GPIO_STATUS_INT_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS_W1TC: RTC GPIO interrupt status bit clear register + // Position of GPIO_STATUS_INT_W1TC field. + RTCIO_RTC_GPIO_STATUS_W1TC_GPIO_STATUS_INT_W1TC_Pos = 0xa + // Bit mask of GPIO_STATUS_INT_W1TC field. + RTCIO_RTC_GPIO_STATUS_W1TC_GPIO_STATUS_INT_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_IN: RTC GPIO input register + // Position of GPIO_IN_NEXT field. + RTCIO_RTC_GPIO_IN_GPIO_IN_NEXT_Pos = 0xa + // Bit mask of GPIO_IN_NEXT field. + RTCIO_RTC_GPIO_IN_GPIO_IN_NEXT_Msk = 0xfffffc00 + + // PIN0: RTC configuration for pin %s + // Position of PAD_DRIVER field. + RTCIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTCIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTCIO_PIN_PAD_DRIVER = 0x4 + // Position of GPIO_PIN_INT_TYPE field. + RTCIO_PIN_GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN_INT_TYPE field. + RTCIO_PIN_GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of GPIO_PIN_WAKEUP_ENABLE field. + RTCIO_PIN_GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN_WAKEUP_ENABLE field. + RTCIO_PIN_GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN_WAKEUP_ENABLE. + RTCIO_PIN_GPIO_PIN_WAKEUP_ENABLE = 0x400 + + // RTC_DEBUG_SEL: RTC debug select register + // Position of RTC_DEBUG_SEL0 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL0_Pos = 0x0 + // Bit mask of RTC_DEBUG_SEL0 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL0_Msk = 0x1f + // Position of RTC_DEBUG_SEL1 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL1_Pos = 0x5 + // Bit mask of RTC_DEBUG_SEL1 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL1_Msk = 0x3e0 + // Position of RTC_DEBUG_SEL2 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL2_Pos = 0xa + // Bit mask of RTC_DEBUG_SEL2 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL2_Msk = 0x7c00 + // Position of RTC_DEBUG_SEL3 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL3_Pos = 0xf + // Bit mask of RTC_DEBUG_SEL3 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL3_Msk = 0xf8000 + // Position of RTC_DEBUG_SEL4 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL4_Pos = 0x14 + // Bit mask of RTC_DEBUG_SEL4 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL4_Msk = 0x1f00000 + // Position of RTC_DEBUG_12M_NO_GATING field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING_Pos = 0x19 + // Bit mask of RTC_DEBUG_12M_NO_GATING field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING_Msk = 0x2000000 + // Bit RTC_DEBUG_12M_NO_GATING. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING = 0x2000000 + + // TOUCH_PAD0: Touch pad %s configuration register + // Position of FUN_IE field. + RTCIO_TOUCH_PAD_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTCIO_TOUCH_PAD_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTCIO_TOUCH_PAD_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTCIO_TOUCH_PAD_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTCIO_TOUCH_PAD_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTCIO_TOUCH_PAD_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTCIO_TOUCH_PAD_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTCIO_TOUCH_PAD_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTCIO_TOUCH_PAD_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTCIO_TOUCH_PAD_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTCIO_TOUCH_PAD_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTCIO_TOUCH_PAD_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTCIO_TOUCH_PAD_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTCIO_TOUCH_PAD_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTCIO_TOUCH_PAD_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTCIO_TOUCH_PAD_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTCIO_TOUCH_PAD_MUX_SEL = 0x80000 + // Position of XPD field. + RTCIO_TOUCH_PAD_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTCIO_TOUCH_PAD_XPD_Msk = 0x100000 + // Bit XPD. + RTCIO_TOUCH_PAD_XPD = 0x100000 + // Position of TIE_OPT field. + RTCIO_TOUCH_PAD_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTCIO_TOUCH_PAD_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTCIO_TOUCH_PAD_TIE_OPT = 0x200000 + // Position of START field. + RTCIO_TOUCH_PAD_START_Pos = 0x16 + // Bit mask of START field. + RTCIO_TOUCH_PAD_START_Msk = 0x400000 + // Bit START. + RTCIO_TOUCH_PAD_START = 0x400000 + // Position of DAC field. + RTCIO_TOUCH_PAD_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTCIO_TOUCH_PAD_DAC_Msk = 0x3800000 + // Position of RUE field. + RTCIO_TOUCH_PAD_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTCIO_TOUCH_PAD_RUE_Msk = 0x8000000 + // Bit RUE. + RTCIO_TOUCH_PAD_RUE = 0x8000000 + // Position of RDE field. + RTCIO_TOUCH_PAD_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTCIO_TOUCH_PAD_RDE_Msk = 0x10000000 + // Bit RDE. + RTCIO_TOUCH_PAD_RDE = 0x10000000 + // Position of DRV field. + RTCIO_TOUCH_PAD_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTCIO_TOUCH_PAD_DRV_Msk = 0x60000000 + + // XTAL_32P_PAD: 32KHz crystal P-pad configuration register + // Position of X32P_FUN_IE field. + RTCIO_XTAL_32P_PAD_X32P_FUN_IE_Pos = 0xd + // Bit mask of X32P_FUN_IE field. + RTCIO_XTAL_32P_PAD_X32P_FUN_IE_Msk = 0x2000 + // Bit X32P_FUN_IE. + RTCIO_XTAL_32P_PAD_X32P_FUN_IE = 0x2000 + // Position of X32P_SLP_OE field. + RTCIO_XTAL_32P_PAD_X32P_SLP_OE_Pos = 0xe + // Bit mask of X32P_SLP_OE field. + RTCIO_XTAL_32P_PAD_X32P_SLP_OE_Msk = 0x4000 + // Bit X32P_SLP_OE. + RTCIO_XTAL_32P_PAD_X32P_SLP_OE = 0x4000 + // Position of X32P_SLP_IE field. + RTCIO_XTAL_32P_PAD_X32P_SLP_IE_Pos = 0xf + // Bit mask of X32P_SLP_IE field. + RTCIO_XTAL_32P_PAD_X32P_SLP_IE_Msk = 0x8000 + // Bit X32P_SLP_IE. + RTCIO_XTAL_32P_PAD_X32P_SLP_IE = 0x8000 + // Position of X32P_SLP_SEL field. + RTCIO_XTAL_32P_PAD_X32P_SLP_SEL_Pos = 0x10 + // Bit mask of X32P_SLP_SEL field. + RTCIO_XTAL_32P_PAD_X32P_SLP_SEL_Msk = 0x10000 + // Bit X32P_SLP_SEL. + RTCIO_XTAL_32P_PAD_X32P_SLP_SEL = 0x10000 + // Position of X32P_FUN_SEL field. + RTCIO_XTAL_32P_PAD_X32P_FUN_SEL_Pos = 0x11 + // Bit mask of X32P_FUN_SEL field. + RTCIO_XTAL_32P_PAD_X32P_FUN_SEL_Msk = 0x60000 + // Position of X32P_MUX_SEL field. + RTCIO_XTAL_32P_PAD_X32P_MUX_SEL_Pos = 0x13 + // Bit mask of X32P_MUX_SEL field. + RTCIO_XTAL_32P_PAD_X32P_MUX_SEL_Msk = 0x80000 + // Bit X32P_MUX_SEL. + RTCIO_XTAL_32P_PAD_X32P_MUX_SEL = 0x80000 + // Position of X32P_RUE field. + RTCIO_XTAL_32P_PAD_X32P_RUE_Pos = 0x1b + // Bit mask of X32P_RUE field. + RTCIO_XTAL_32P_PAD_X32P_RUE_Msk = 0x8000000 + // Bit X32P_RUE. + RTCIO_XTAL_32P_PAD_X32P_RUE = 0x8000000 + // Position of X32P_RDE field. + RTCIO_XTAL_32P_PAD_X32P_RDE_Pos = 0x1c + // Bit mask of X32P_RDE field. + RTCIO_XTAL_32P_PAD_X32P_RDE_Msk = 0x10000000 + // Bit X32P_RDE. + RTCIO_XTAL_32P_PAD_X32P_RDE = 0x10000000 + // Position of X32P_DRV field. + RTCIO_XTAL_32P_PAD_X32P_DRV_Pos = 0x1d + // Bit mask of X32P_DRV field. + RTCIO_XTAL_32P_PAD_X32P_DRV_Msk = 0x60000000 + + // XTAL_32N_PAD: 32KHz crystal N-pad configuration register + // Position of X32N_FUN_IE field. + RTCIO_XTAL_32N_PAD_X32N_FUN_IE_Pos = 0xd + // Bit mask of X32N_FUN_IE field. + RTCIO_XTAL_32N_PAD_X32N_FUN_IE_Msk = 0x2000 + // Bit X32N_FUN_IE. + RTCIO_XTAL_32N_PAD_X32N_FUN_IE = 0x2000 + // Position of X32N_SLP_OE field. + RTCIO_XTAL_32N_PAD_X32N_SLP_OE_Pos = 0xe + // Bit mask of X32N_SLP_OE field. + RTCIO_XTAL_32N_PAD_X32N_SLP_OE_Msk = 0x4000 + // Bit X32N_SLP_OE. + RTCIO_XTAL_32N_PAD_X32N_SLP_OE = 0x4000 + // Position of X32N_SLP_IE field. + RTCIO_XTAL_32N_PAD_X32N_SLP_IE_Pos = 0xf + // Bit mask of X32N_SLP_IE field. + RTCIO_XTAL_32N_PAD_X32N_SLP_IE_Msk = 0x8000 + // Bit X32N_SLP_IE. + RTCIO_XTAL_32N_PAD_X32N_SLP_IE = 0x8000 + // Position of X32N_SLP_SEL field. + RTCIO_XTAL_32N_PAD_X32N_SLP_SEL_Pos = 0x10 + // Bit mask of X32N_SLP_SEL field. + RTCIO_XTAL_32N_PAD_X32N_SLP_SEL_Msk = 0x10000 + // Bit X32N_SLP_SEL. + RTCIO_XTAL_32N_PAD_X32N_SLP_SEL = 0x10000 + // Position of X32N_FUN_SEL field. + RTCIO_XTAL_32N_PAD_X32N_FUN_SEL_Pos = 0x11 + // Bit mask of X32N_FUN_SEL field. + RTCIO_XTAL_32N_PAD_X32N_FUN_SEL_Msk = 0x60000 + // Position of X32N_MUX_SEL field. + RTCIO_XTAL_32N_PAD_X32N_MUX_SEL_Pos = 0x13 + // Bit mask of X32N_MUX_SEL field. + RTCIO_XTAL_32N_PAD_X32N_MUX_SEL_Msk = 0x80000 + // Bit X32N_MUX_SEL. + RTCIO_XTAL_32N_PAD_X32N_MUX_SEL = 0x80000 + // Position of X32N_RUE field. + RTCIO_XTAL_32N_PAD_X32N_RUE_Pos = 0x1b + // Bit mask of X32N_RUE field. + RTCIO_XTAL_32N_PAD_X32N_RUE_Msk = 0x8000000 + // Bit X32N_RUE. + RTCIO_XTAL_32N_PAD_X32N_RUE = 0x8000000 + // Position of X32N_RDE field. + RTCIO_XTAL_32N_PAD_X32N_RDE_Pos = 0x1c + // Bit mask of X32N_RDE field. + RTCIO_XTAL_32N_PAD_X32N_RDE_Msk = 0x10000000 + // Bit X32N_RDE. + RTCIO_XTAL_32N_PAD_X32N_RDE = 0x10000000 + // Position of X32N_DRV field. + RTCIO_XTAL_32N_PAD_X32N_DRV_Pos = 0x1d + // Bit mask of X32N_DRV field. + RTCIO_XTAL_32N_PAD_X32N_DRV_Msk = 0x60000000 + + // PAD_DAC1: DAC1 configuration register + // Position of PDAC1_DAC field. + RTCIO_PAD_DAC1_PDAC1_DAC_Pos = 0x3 + // Bit mask of PDAC1_DAC field. + RTCIO_PAD_DAC1_PDAC1_DAC_Msk = 0x7f8 + // Position of PDAC1_XPD_DAC field. + RTCIO_PAD_DAC1_PDAC1_XPD_DAC_Pos = 0xb + // Bit mask of PDAC1_XPD_DAC field. + RTCIO_PAD_DAC1_PDAC1_XPD_DAC_Msk = 0x800 + // Bit PDAC1_XPD_DAC. + RTCIO_PAD_DAC1_PDAC1_XPD_DAC = 0x800 + // Position of PDAC1_DAC_XPD_FORCE field. + RTCIO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Pos = 0xc + // Bit mask of PDAC1_DAC_XPD_FORCE field. + RTCIO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Msk = 0x1000 + // Bit PDAC1_DAC_XPD_FORCE. + RTCIO_PAD_DAC1_PDAC1_DAC_XPD_FORCE = 0x1000 + // Position of PDAC1_FUN_IE field. + RTCIO_PAD_DAC1_PDAC1_FUN_IE_Pos = 0xd + // Bit mask of PDAC1_FUN_IE field. + RTCIO_PAD_DAC1_PDAC1_FUN_IE_Msk = 0x2000 + // Bit PDAC1_FUN_IE. + RTCIO_PAD_DAC1_PDAC1_FUN_IE = 0x2000 + // Position of PDAC1_SLP_OE field. + RTCIO_PAD_DAC1_PDAC1_SLP_OE_Pos = 0xe + // Bit mask of PDAC1_SLP_OE field. + RTCIO_PAD_DAC1_PDAC1_SLP_OE_Msk = 0x4000 + // Bit PDAC1_SLP_OE. + RTCIO_PAD_DAC1_PDAC1_SLP_OE = 0x4000 + // Position of PDAC1_SLP_IE field. + RTCIO_PAD_DAC1_PDAC1_SLP_IE_Pos = 0xf + // Bit mask of PDAC1_SLP_IE field. + RTCIO_PAD_DAC1_PDAC1_SLP_IE_Msk = 0x8000 + // Bit PDAC1_SLP_IE. + RTCIO_PAD_DAC1_PDAC1_SLP_IE = 0x8000 + // Position of PDAC1_SLP_SEL field. + RTCIO_PAD_DAC1_PDAC1_SLP_SEL_Pos = 0x10 + // Bit mask of PDAC1_SLP_SEL field. + RTCIO_PAD_DAC1_PDAC1_SLP_SEL_Msk = 0x10000 + // Bit PDAC1_SLP_SEL. + RTCIO_PAD_DAC1_PDAC1_SLP_SEL = 0x10000 + // Position of PDAC1_FUN_SEL field. + RTCIO_PAD_DAC1_PDAC1_FUN_SEL_Pos = 0x11 + // Bit mask of PDAC1_FUN_SEL field. + RTCIO_PAD_DAC1_PDAC1_FUN_SEL_Msk = 0x60000 + // Position of PDAC1_MUX_SEL field. + RTCIO_PAD_DAC1_PDAC1_MUX_SEL_Pos = 0x13 + // Bit mask of PDAC1_MUX_SEL field. + RTCIO_PAD_DAC1_PDAC1_MUX_SEL_Msk = 0x80000 + // Bit PDAC1_MUX_SEL. + RTCIO_PAD_DAC1_PDAC1_MUX_SEL = 0x80000 + // Position of PDAC1_RUE field. + RTCIO_PAD_DAC1_PDAC1_RUE_Pos = 0x1b + // Bit mask of PDAC1_RUE field. + RTCIO_PAD_DAC1_PDAC1_RUE_Msk = 0x8000000 + // Bit PDAC1_RUE. + RTCIO_PAD_DAC1_PDAC1_RUE = 0x8000000 + // Position of PDAC1_RDE field. + RTCIO_PAD_DAC1_PDAC1_RDE_Pos = 0x1c + // Bit mask of PDAC1_RDE field. + RTCIO_PAD_DAC1_PDAC1_RDE_Msk = 0x10000000 + // Bit PDAC1_RDE. + RTCIO_PAD_DAC1_PDAC1_RDE = 0x10000000 + // Position of PDAC1_DRV field. + RTCIO_PAD_DAC1_PDAC1_DRV_Pos = 0x1d + // Bit mask of PDAC1_DRV field. + RTCIO_PAD_DAC1_PDAC1_DRV_Msk = 0x60000000 + + // PAD_DAC2: DAC2 configuration register + // Position of PDAC2_DAC field. + RTCIO_PAD_DAC2_PDAC2_DAC_Pos = 0x3 + // Bit mask of PDAC2_DAC field. + RTCIO_PAD_DAC2_PDAC2_DAC_Msk = 0x7f8 + // Position of PDAC2_XPD_DAC field. + RTCIO_PAD_DAC2_PDAC2_XPD_DAC_Pos = 0xb + // Bit mask of PDAC2_XPD_DAC field. + RTCIO_PAD_DAC2_PDAC2_XPD_DAC_Msk = 0x800 + // Bit PDAC2_XPD_DAC. + RTCIO_PAD_DAC2_PDAC2_XPD_DAC = 0x800 + // Position of PDAC2_DAC_XPD_FORCE field. + RTCIO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Pos = 0xc + // Bit mask of PDAC2_DAC_XPD_FORCE field. + RTCIO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Msk = 0x1000 + // Bit PDAC2_DAC_XPD_FORCE. + RTCIO_PAD_DAC2_PDAC2_DAC_XPD_FORCE = 0x1000 + // Position of PDAC2_FUN_IE field. + RTCIO_PAD_DAC2_PDAC2_FUN_IE_Pos = 0xd + // Bit mask of PDAC2_FUN_IE field. + RTCIO_PAD_DAC2_PDAC2_FUN_IE_Msk = 0x2000 + // Bit PDAC2_FUN_IE. + RTCIO_PAD_DAC2_PDAC2_FUN_IE = 0x2000 + // Position of PDAC2_SLP_OE field. + RTCIO_PAD_DAC2_PDAC2_SLP_OE_Pos = 0xe + // Bit mask of PDAC2_SLP_OE field. + RTCIO_PAD_DAC2_PDAC2_SLP_OE_Msk = 0x4000 + // Bit PDAC2_SLP_OE. + RTCIO_PAD_DAC2_PDAC2_SLP_OE = 0x4000 + // Position of PDAC2_SLP_IE field. + RTCIO_PAD_DAC2_PDAC2_SLP_IE_Pos = 0xf + // Bit mask of PDAC2_SLP_IE field. + RTCIO_PAD_DAC2_PDAC2_SLP_IE_Msk = 0x8000 + // Bit PDAC2_SLP_IE. + RTCIO_PAD_DAC2_PDAC2_SLP_IE = 0x8000 + // Position of PDAC2_SLP_SEL field. + RTCIO_PAD_DAC2_PDAC2_SLP_SEL_Pos = 0x10 + // Bit mask of PDAC2_SLP_SEL field. + RTCIO_PAD_DAC2_PDAC2_SLP_SEL_Msk = 0x10000 + // Bit PDAC2_SLP_SEL. + RTCIO_PAD_DAC2_PDAC2_SLP_SEL = 0x10000 + // Position of PDAC2_FUN_SEL field. + RTCIO_PAD_DAC2_PDAC2_FUN_SEL_Pos = 0x11 + // Bit mask of PDAC2_FUN_SEL field. + RTCIO_PAD_DAC2_PDAC2_FUN_SEL_Msk = 0x60000 + // Position of PDAC2_MUX_SEL field. + RTCIO_PAD_DAC2_PDAC2_MUX_SEL_Pos = 0x13 + // Bit mask of PDAC2_MUX_SEL field. + RTCIO_PAD_DAC2_PDAC2_MUX_SEL_Msk = 0x80000 + // Bit PDAC2_MUX_SEL. + RTCIO_PAD_DAC2_PDAC2_MUX_SEL = 0x80000 + // Position of PDAC2_RUE field. + RTCIO_PAD_DAC2_PDAC2_RUE_Pos = 0x1b + // Bit mask of PDAC2_RUE field. + RTCIO_PAD_DAC2_PDAC2_RUE_Msk = 0x8000000 + // Bit PDAC2_RUE. + RTCIO_PAD_DAC2_PDAC2_RUE = 0x8000000 + // Position of PDAC2_RDE field. + RTCIO_PAD_DAC2_PDAC2_RDE_Pos = 0x1c + // Bit mask of PDAC2_RDE field. + RTCIO_PAD_DAC2_PDAC2_RDE_Msk = 0x10000000 + // Bit PDAC2_RDE. + RTCIO_PAD_DAC2_PDAC2_RDE = 0x10000000 + // Position of PDAC2_DRV field. + RTCIO_PAD_DAC2_PDAC2_DRV_Pos = 0x1d + // Bit mask of PDAC2_DRV field. + RTCIO_PAD_DAC2_PDAC2_DRV_Msk = 0x60000000 + + // RTC_PAD19: Touch pad 19 configuration register + // Position of FUN_IE field. + RTCIO_RTC_PAD19_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTCIO_RTC_PAD19_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTCIO_RTC_PAD19_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTCIO_RTC_PAD19_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTCIO_RTC_PAD19_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTCIO_RTC_PAD19_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTCIO_RTC_PAD19_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTCIO_RTC_PAD19_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTCIO_RTC_PAD19_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTCIO_RTC_PAD19_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTCIO_RTC_PAD19_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTCIO_RTC_PAD19_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTCIO_RTC_PAD19_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTCIO_RTC_PAD19_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTCIO_RTC_PAD19_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTCIO_RTC_PAD19_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTCIO_RTC_PAD19_MUX_SEL = 0x80000 + // Position of RUE field. + RTCIO_RTC_PAD19_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTCIO_RTC_PAD19_RUE_Msk = 0x8000000 + // Bit RUE. + RTCIO_RTC_PAD19_RUE = 0x8000000 + // Position of RDE field. + RTCIO_RTC_PAD19_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTCIO_RTC_PAD19_RDE_Msk = 0x10000000 + // Bit RDE. + RTCIO_RTC_PAD19_RDE = 0x10000000 + // Position of DRV field. + RTCIO_RTC_PAD19_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTCIO_RTC_PAD19_DRV_Msk = 0x60000000 + + // RTC_PAD20: Touch pad 20 configuration register + // Position of FUN_IE field. + RTCIO_RTC_PAD20_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTCIO_RTC_PAD20_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTCIO_RTC_PAD20_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTCIO_RTC_PAD20_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTCIO_RTC_PAD20_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTCIO_RTC_PAD20_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTCIO_RTC_PAD20_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTCIO_RTC_PAD20_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTCIO_RTC_PAD20_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTCIO_RTC_PAD20_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTCIO_RTC_PAD20_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTCIO_RTC_PAD20_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTCIO_RTC_PAD20_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTCIO_RTC_PAD20_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTCIO_RTC_PAD20_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTCIO_RTC_PAD20_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTCIO_RTC_PAD20_MUX_SEL = 0x80000 + // Position of RUE field. + RTCIO_RTC_PAD20_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTCIO_RTC_PAD20_RUE_Msk = 0x8000000 + // Bit RUE. + RTCIO_RTC_PAD20_RUE = 0x8000000 + // Position of RDE field. + RTCIO_RTC_PAD20_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTCIO_RTC_PAD20_RDE_Msk = 0x10000000 + // Bit RDE. + RTCIO_RTC_PAD20_RDE = 0x10000000 + // Position of DRV field. + RTCIO_RTC_PAD20_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTCIO_RTC_PAD20_DRV_Msk = 0x60000000 + + // RTC_PAD21: Touch pad 21 configuration register + // Position of FUN_IE field. + RTCIO_RTC_PAD21_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTCIO_RTC_PAD21_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTCIO_RTC_PAD21_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTCIO_RTC_PAD21_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTCIO_RTC_PAD21_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTCIO_RTC_PAD21_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTCIO_RTC_PAD21_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTCIO_RTC_PAD21_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTCIO_RTC_PAD21_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTCIO_RTC_PAD21_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTCIO_RTC_PAD21_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTCIO_RTC_PAD21_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTCIO_RTC_PAD21_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTCIO_RTC_PAD21_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTCIO_RTC_PAD21_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTCIO_RTC_PAD21_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTCIO_RTC_PAD21_MUX_SEL = 0x80000 + // Position of RUE field. + RTCIO_RTC_PAD21_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTCIO_RTC_PAD21_RUE_Msk = 0x8000000 + // Bit RUE. + RTCIO_RTC_PAD21_RUE = 0x8000000 + // Position of RDE field. + RTCIO_RTC_PAD21_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTCIO_RTC_PAD21_RDE_Msk = 0x10000000 + // Bit RDE. + RTCIO_RTC_PAD21_RDE = 0x10000000 + // Position of DRV field. + RTCIO_RTC_PAD21_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTCIO_RTC_PAD21_DRV_Msk = 0x60000000 + + // EXT_WAKEUP0: External wake up configuration register + // Position of SEL field. + RTCIO_EXT_WAKEUP0_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTCIO_EXT_WAKEUP0_SEL_Msk = 0xf8000000 + + // XTL_EXT_CTR: Crystal power down enable GPIO source + // Position of SEL field. + RTCIO_XTL_EXT_CTR_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTCIO_XTL_EXT_CTR_SEL_Msk = 0xf8000000 + + // SAR_I2C_IO: RTC I2C pad selection + // Position of SAR_DEBUG_BIT_SEL field. + RTCIO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Pos = 0x17 + // Bit mask of SAR_DEBUG_BIT_SEL field. + RTCIO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Msk = 0xf800000 + // Position of SAR_I2C_SCL_SEL field. + RTCIO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Pos = 0x1c + // Bit mask of SAR_I2C_SCL_SEL field. + RTCIO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Msk = 0x30000000 + // Position of SAR_I2C_SDA_SEL field. + RTCIO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Pos = 0x1e + // Bit mask of SAR_I2C_SDA_SEL field. + RTCIO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Msk = 0xc0000000 + + // RTC_IO_TOUCH_CTRL: Touch control register + // Position of IO_TOUCH_BUFSEL field. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL_Pos = 0x0 + // Bit mask of IO_TOUCH_BUFSEL field. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL_Msk = 0xf + // Position of IO_TOUCH_BUFMODE field. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE_Pos = 0x4 + // Bit mask of IO_TOUCH_BUFMODE field. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE_Msk = 0x10 + // Bit IO_TOUCH_BUFMODE. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE = 0x10 + + // RTC_IO_DATE: Version control register + // Position of IO_DATE field. + RTCIO_RTC_IO_DATE_IO_DATE_Pos = 0x0 + // Bit mask of IO_DATE field. + RTCIO_RTC_IO_DATE_IO_DATE_Msk = 0xfffffff +) + +// Constants for RTC_CNTL: Real-Time Clock Control +const ( + // OPTIONS0: Sets the power options of crystal and PLL clocks, and initiates reset by software + // Position of SW_STALL_APPCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_APPCPU_C0_Pos = 0x0 + // Bit mask of SW_STALL_APPCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_APPCPU_C0_Msk = 0x3 + // Position of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Pos = 0x2 + // Bit mask of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Msk = 0xc + // Position of SW_APPCPU_RST field. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST_Pos = 0x4 + // Bit mask of SW_APPCPU_RST field. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST_Msk = 0x10 + // Bit SW_APPCPU_RST. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST = 0x10 + // Position of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Pos = 0x5 + // Bit mask of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Msk = 0x20 + // Bit SW_PROCPU_RST. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST = 0x20 + // Position of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Pos = 0x6 + // Bit mask of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Msk = 0x40 + // Bit BB_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD = 0x40 + // Position of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Pos = 0x7 + // Bit mask of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Msk = 0x80 + // Bit BB_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU = 0x80 + // Position of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Pos = 0x8 + // Bit mask of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Msk = 0x100 + // Bit BBPLL_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD = 0x100 + // Position of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Pos = 0x9 + // Bit mask of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Msk = 0x200 + // Bit BBPLL_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU = 0x200 + // Position of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Pos = 0xa + // Bit mask of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Msk = 0x400 + // Bit BBPLL_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD = 0x400 + // Position of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Pos = 0xb + // Bit mask of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Msk = 0x800 + // Bit BBPLL_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU = 0x800 + // Position of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Pos = 0xc + // Bit mask of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Msk = 0x1000 + // Bit XTL_FORCE_PD. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD = 0x1000 + // Position of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Pos = 0xd + // Bit mask of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Msk = 0x2000 + // Bit XTL_FORCE_PU. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU = 0x2000 + // Position of XTL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO_Pos = 0x17 + // Bit mask of XTL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO_Msk = 0x800000 + // Bit XTL_FORCE_ISO. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO = 0x800000 + // Position of PLL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO_Pos = 0x18 + // Bit mask of PLL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO_Msk = 0x1000000 + // Bit PLL_FORCE_ISO. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO = 0x1000000 + // Position of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Pos = 0x19 + // Bit mask of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Msk = 0x2000000 + // Bit ANALOG_FORCE_ISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO = 0x2000000 + // Position of XTL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO_Pos = 0x1a + // Bit mask of XTL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO_Msk = 0x4000000 + // Bit XTL_FORCE_NOISO. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO = 0x4000000 + // Position of PLL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO_Pos = 0x1b + // Bit mask of PLL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO_Msk = 0x8000000 + // Bit PLL_FORCE_NOISO. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO = 0x8000000 + // Position of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Pos = 0x1c + // Bit mask of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Msk = 0x10000000 + // Bit ANALOG_FORCE_NOISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO = 0x10000000 + // Position of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Pos = 0x1d + // Bit mask of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Msk = 0x20000000 + // Bit DG_WRAP_FORCE_RST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST = 0x20000000 + // Position of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_NORST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST = 0x40000000 + // Position of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Pos = 0x1f + // Bit mask of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Msk = 0x80000000 + // Bit SW_SYS_RST. + RTC_CNTL_OPTIONS0_SW_SYS_RST = 0x80000000 + + // SLP_TIMER0: RTC timer threshold register 0 + // Position of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Pos = 0x0 + // Bit mask of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Msk = 0xffffffff + + // SLP_TIMER1: RTC timer threshold register 1 + // Position of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Pos = 0x0 + // Bit mask of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Msk = 0xffff + // Position of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Pos = 0x10 + // Bit mask of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Msk = 0x10000 + // Bit MAIN_TIMER_ALARM_EN. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN = 0x10000 + + // TIME_UPDATE: RTC timer update control register + // Position of TIMER_SYS_STALL field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL_Pos = 0x1b + // Bit mask of TIMER_SYS_STALL field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL_Msk = 0x8000000 + // Bit TIMER_SYS_STALL. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL = 0x8000000 + // Position of TIMER_XTL_OFF field. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF_Pos = 0x1c + // Bit mask of TIMER_XTL_OFF field. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF_Msk = 0x10000000 + // Bit TIMER_XTL_OFF. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF = 0x10000000 + // Position of TIMER_SYS_RST field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST_Pos = 0x1d + // Bit mask of TIMER_SYS_RST field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST_Msk = 0x20000000 + // Bit TIMER_SYS_RST. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST = 0x20000000 + // Position of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Pos = 0x1f + // Bit mask of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Msk = 0x80000000 + // Bit TIME_UPDATE. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE = 0x80000000 + + // TIME_LOW0: Stores the lower 32 bits of RTC timer 0. + // Position of TIMER_VALUE0_LOW field. + RTC_CNTL_TIME_LOW0_TIMER_VALUE0_LOW_Pos = 0x0 + // Bit mask of TIMER_VALUE0_LOW field. + RTC_CNTL_TIME_LOW0_TIMER_VALUE0_LOW_Msk = 0xffffffff + + // TIME_HIGH0: Stores the higher 16 bits of RTC timer 0 + // Position of TIMER_VALUE0_HIGH field. + RTC_CNTL_TIME_HIGH0_TIMER_VALUE0_HIGH_Pos = 0x0 + // Bit mask of TIMER_VALUE0_HIGH field. + RTC_CNTL_TIME_HIGH0_TIMER_VALUE0_HIGH_Msk = 0xffff + + // STATE0: Configures the sleep / reject / wakeup state + // Position of SW_CPU_INT field. + RTC_CNTL_STATE0_SW_CPU_INT_Pos = 0x0 + // Bit mask of SW_CPU_INT field. + RTC_CNTL_STATE0_SW_CPU_INT_Msk = 0x1 + // Bit SW_CPU_INT. + RTC_CNTL_STATE0_SW_CPU_INT = 0x1 + // Position of SLP_REJECT_CAUSE_CLR field. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR_Pos = 0x1 + // Bit mask of SLP_REJECT_CAUSE_CLR field. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR_Msk = 0x2 + // Bit SLP_REJECT_CAUSE_CLR. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR = 0x2 + // Position of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Pos = 0x16 + // Bit mask of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Msk = 0x400000 + // Bit APB2RTC_BRIDGE_SEL. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL = 0x400000 + // Position of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Pos = 0x1c + // Bit mask of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Msk = 0x10000000 + // Bit SDIO_ACTIVE_IND. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND = 0x10000000 + // Position of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Pos = 0x1d + // Bit mask of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Msk = 0x20000000 + // Bit SLP_WAKEUP. + RTC_CNTL_STATE0_SLP_WAKEUP = 0x20000000 + // Position of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Pos = 0x1e + // Bit mask of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Msk = 0x40000000 + // Bit SLP_REJECT. + RTC_CNTL_STATE0_SLP_REJECT = 0x40000000 + // Position of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Pos = 0x1f + // Bit mask of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Msk = 0x80000000 + // Bit SLEEP_EN. + RTC_CNTL_STATE0_SLEEP_EN = 0x80000000 + + // TIMER1: Configures CPU stall options + // Position of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Pos = 0x0 + // Bit mask of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Msk = 0x1 + // Bit CPU_STALL_EN. + RTC_CNTL_TIMER1_CPU_STALL_EN = 0x1 + // Position of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Pos = 0x1 + // Bit mask of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Msk = 0x3e + // Position of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Pos = 0x6 + // Bit mask of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Msk = 0x3fc0 + // Position of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Pos = 0xe + // Bit mask of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Msk = 0xffc000 + // Position of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Pos = 0x18 + // Bit mask of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Msk = 0xff000000 + + // TIMER2: Configures RTC slow clock and touch controller + // Position of ULPCP_TOUCH_START_WAIT field. + RTC_CNTL_TIMER2_ULPCP_TOUCH_START_WAIT_Pos = 0xf + // Bit mask of ULPCP_TOUCH_START_WAIT field. + RTC_CNTL_TIMER2_ULPCP_TOUCH_START_WAIT_Msk = 0xff8000 + // Position of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Pos = 0x18 + // Bit mask of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Msk = 0xff000000 + + // TIMER3: configure some wait time for power on + // Position of WIFI_WAIT_TIMER field. + RTC_CNTL_TIMER3_WIFI_WAIT_TIMER_Pos = 0x0 + // Bit mask of WIFI_WAIT_TIMER field. + RTC_CNTL_TIMER3_WIFI_WAIT_TIMER_Msk = 0x1ff + // Position of WIFI_POWERUP_TIMER field. + RTC_CNTL_TIMER3_WIFI_POWERUP_TIMER_Pos = 0x9 + // Bit mask of WIFI_POWERUP_TIMER field. + RTC_CNTL_TIMER3_WIFI_POWERUP_TIMER_Msk = 0xfe00 + // Position of ROM_RAM_WAIT_TIMER field. + RTC_CNTL_TIMER3_ROM_RAM_WAIT_TIMER_Pos = 0x10 + // Bit mask of ROM_RAM_WAIT_TIMER field. + RTC_CNTL_TIMER3_ROM_RAM_WAIT_TIMER_Msk = 0x1ff0000 + // Position of ROM_RAM_POWERUP_TIMER field. + RTC_CNTL_TIMER3_ROM_RAM_POWERUP_TIMER_Pos = 0x19 + // Bit mask of ROM_RAM_POWERUP_TIMER field. + RTC_CNTL_TIMER3_ROM_RAM_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER4: configure some wait time for power on + // Position of WAIT_TIMER field. + RTC_CNTL_TIMER4_WAIT_TIMER_Pos = 0x0 + // Bit mask of WAIT_TIMER field. + RTC_CNTL_TIMER4_WAIT_TIMER_Msk = 0x1ff + // Position of POWERUP_TIMER field. + RTC_CNTL_TIMER4_POWERUP_TIMER_Pos = 0x9 + // Bit mask of POWERUP_TIMER field. + RTC_CNTL_TIMER4_POWERUP_TIMER_Msk = 0xfe00 + // Position of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Pos = 0x10 + // Bit mask of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Msk = 0x1ff0000 + // Position of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Pos = 0x19 + // Bit mask of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER5: Configures the minimal sleep cycles + // Position of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Pos = 0x8 + // Bit mask of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Msk = 0xff00 + // Position of RTCMEM_WAIT_TIMER field. + RTC_CNTL_TIMER5_RTCMEM_WAIT_TIMER_Pos = 0x10 + // Bit mask of RTCMEM_WAIT_TIMER field. + RTC_CNTL_TIMER5_RTCMEM_WAIT_TIMER_Msk = 0x1ff0000 + // Position of RTCMEM_POWERUP_TIMER field. + RTC_CNTL_TIMER5_RTCMEM_POWERUP_TIMER_Pos = 0x19 + // Bit mask of RTCMEM_POWERUP_TIMER field. + RTC_CNTL_TIMER5_RTCMEM_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER6: Configure minimal sleep cycles register + // Position of DG_DCDC_WAIT_TIMER field. + RTC_CNTL_TIMER6_DG_DCDC_WAIT_TIMER_Pos = 0x10 + // Bit mask of DG_DCDC_WAIT_TIMER field. + RTC_CNTL_TIMER6_DG_DCDC_WAIT_TIMER_Msk = 0x1ff0000 + // Position of DG_DCDC_POWERUP_TIMER field. + RTC_CNTL_TIMER6_DG_DCDC_POWERUP_TIMER_Pos = 0x19 + // Bit mask of DG_DCDC_POWERUP_TIMER field. + RTC_CNTL_TIMER6_DG_DCDC_POWERUP_TIMER_Msk = 0xfe000000 + + // ANA_CONF: Configures the power options for I2C and PLLA + // Position of I2C_RESET_POR_FORCE_PD field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PD_Pos = 0x12 + // Bit mask of I2C_RESET_POR_FORCE_PD field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PD_Msk = 0x40000 + // Bit I2C_RESET_POR_FORCE_PD. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PD = 0x40000 + // Position of I2C_RESET_POR_FORCE_PU field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PU_Pos = 0x13 + // Bit mask of I2C_RESET_POR_FORCE_PU field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PU_Msk = 0x80000 + // Bit I2C_RESET_POR_FORCE_PU. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PU = 0x80000 + // Position of GLITCH_RST_EN field. + RTC_CNTL_ANA_CONF_GLITCH_RST_EN_Pos = 0x14 + // Bit mask of GLITCH_RST_EN field. + RTC_CNTL_ANA_CONF_GLITCH_RST_EN_Msk = 0x100000 + // Bit GLITCH_RST_EN. + RTC_CNTL_ANA_CONF_GLITCH_RST_EN = 0x100000 + // Position of SAR_I2C_FORCE_PD field. + RTC_CNTL_ANA_CONF_SAR_I2C_FORCE_PD_Pos = 0x15 + // Bit mask of SAR_I2C_FORCE_PD field. + RTC_CNTL_ANA_CONF_SAR_I2C_FORCE_PD_Msk = 0x200000 + // Bit SAR_I2C_FORCE_PD. + RTC_CNTL_ANA_CONF_SAR_I2C_FORCE_PD = 0x200000 + // Position of SAR_I2C_FORCE_PU field. + RTC_CNTL_ANA_CONF_SAR_I2C_FORCE_PU_Pos = 0x16 + // Bit mask of SAR_I2C_FORCE_PU field. + RTC_CNTL_ANA_CONF_SAR_I2C_FORCE_PU_Msk = 0x400000 + // Bit SAR_I2C_FORCE_PU. + RTC_CNTL_ANA_CONF_SAR_I2C_FORCE_PU = 0x400000 + // Position of PLLA_FORCE_PD field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD_Pos = 0x17 + // Bit mask of PLLA_FORCE_PD field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD_Msk = 0x800000 + // Bit PLLA_FORCE_PD. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PD = 0x800000 + // Position of PLLA_FORCE_PU field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU_Pos = 0x18 + // Bit mask of PLLA_FORCE_PU field. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU_Msk = 0x1000000 + // Bit PLLA_FORCE_PU. + RTC_CNTL_ANA_CONF_PLLA_FORCE_PU = 0x1000000 + // Position of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Pos = 0x19 + // Bit mask of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Msk = 0x2000000 + // Bit BBPLL_CAL_SLP_START. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START = 0x2000000 + // Position of PVTMON_PU field. + RTC_CNTL_ANA_CONF_PVTMON_PU_Pos = 0x1a + // Bit mask of PVTMON_PU field. + RTC_CNTL_ANA_CONF_PVTMON_PU_Msk = 0x4000000 + // Bit PVTMON_PU. + RTC_CNTL_ANA_CONF_PVTMON_PU = 0x4000000 + // Position of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Pos = 0x1b + // Bit mask of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Msk = 0x8000000 + // Bit TXRF_I2C_PU. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU = 0x8000000 + // Position of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Pos = 0x1c + // Bit mask of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Msk = 0x10000000 + // Bit RFRX_PBUS_PU. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU = 0x10000000 + // Position of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Pos = 0x1e + // Bit mask of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Msk = 0x40000000 + // Bit CKGEN_I2C_PU. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU = 0x40000000 + // Position of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Pos = 0x1f + // Bit mask of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Msk = 0x80000000 + // Bit PLL_I2C_PU. + RTC_CNTL_ANA_CONF_PLL_I2C_PU = 0x80000000 + + // RESET_STATE: Indicates the CPU reset source. For more information about the reset cause, please refer to Table \ref{table:resetreasons} in Chapter \ref{module:ResetandClock} \textit{\nameref{module:ResetandClock}}. + // Position of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Pos = 0x0 + // Bit mask of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Msk = 0x3f + // Position of RESET_CAUSE_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_APPCPU_Pos = 0x6 + // Bit mask of RESET_CAUSE_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_APPCPU_Msk = 0xfc0 + // Position of APPCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_APPCPU_STAT_VECTOR_SEL_Pos = 0xc + // Bit mask of APPCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_APPCPU_STAT_VECTOR_SEL_Msk = 0x1000 + // Bit APPCPU_STAT_VECTOR_SEL. + RTC_CNTL_RESET_STATE_APPCPU_STAT_VECTOR_SEL = 0x1000 + // Position of PROCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_PROCPU_STAT_VECTOR_SEL_Pos = 0xd + // Bit mask of PROCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_PROCPU_STAT_VECTOR_SEL_Msk = 0x2000 + // Bit PROCPU_STAT_VECTOR_SEL. + RTC_CNTL_RESET_STATE_PROCPU_STAT_VECTOR_SEL = 0x2000 + + // WAKEUP_STATE: Wakeup bitmap enabling register + // Position of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Pos = 0xf + // Bit mask of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Msk = 0xffff8000 + + // INT_ENA_RTC: RTC interrupt enabling register + // Position of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA = 0x1 + // Position of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA = 0x2 + // Position of SDIO_IDLE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SDIO_IDLE_INT_ENA_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SDIO_IDLE_INT_ENA_Msk = 0x4 + // Bit SDIO_IDLE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SDIO_IDLE_INT_ENA = 0x4 + // Position of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA_Pos = 0x3 + // Bit mask of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA_Msk = 0x8 + // Bit WDT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA = 0x8 + // Position of TOUCH_SCAN_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA = 0x10 + // Position of ULP_CP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_ULP_CP_INT_ENA_Pos = 0x5 + // Bit mask of ULP_CP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_ULP_CP_INT_ENA_Msk = 0x20 + // Bit ULP_CP_INT_ENA. + RTC_CNTL_INT_ENA_RTC_ULP_CP_INT_ENA = 0x20 + // Position of TOUCH_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_DONE_INT_ENA_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_DONE_INT_ENA_Msk = 0x40 + // Bit TOUCH_DONE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_DONE_INT_ENA = 0x40 + // Position of TOUCH_ACTIVE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_ACTIVE_INT_ENA_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_ACTIVE_INT_ENA_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_ACTIVE_INT_ENA = 0x80 + // Position of TOUCH_INACTIVE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_INACTIVE_INT_ENA_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_INACTIVE_INT_ENA_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_INACTIVE_INT_ENA = 0x100 + // Position of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA = 0x200 + // Position of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA = 0x400 + // Position of SARADC1_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SARADC1_INT_ENA_Pos = 0xb + // Bit mask of SARADC1_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SARADC1_INT_ENA_Msk = 0x800 + // Bit SARADC1_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SARADC1_INT_ENA = 0x800 + // Position of TSENS_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TSENS_INT_ENA_Pos = 0xc + // Bit mask of TSENS_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TSENS_INT_ENA_Msk = 0x1000 + // Bit TSENS_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TSENS_INT_ENA = 0x1000 + // Position of COCPU_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_COCPU_INT_ENA_Pos = 0xd + // Bit mask of COCPU_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_COCPU_INT_ENA_Msk = 0x2000 + // Bit COCPU_INT_ENA. + RTC_CNTL_INT_ENA_RTC_COCPU_INT_ENA = 0x2000 + // Position of SARADC2_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SARADC2_INT_ENA_Pos = 0xe + // Bit mask of SARADC2_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SARADC2_INT_ENA_Msk = 0x4000 + // Bit SARADC2_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SARADC2_INT_ENA = 0x4000 + // Position of SWD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA_Pos = 0xf + // Bit mask of SWD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA_Msk = 0x8000 + // Bit SWD_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA = 0x8000 + // Position of XTAL32K_DEAD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_XTAL32K_DEAD_INT_ENA_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_XTAL32K_DEAD_INT_ENA_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ENA. + RTC_CNTL_INT_ENA_RTC_XTAL32K_DEAD_INT_ENA = 0x10000 + // Position of COCPU_TRAP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_COCPU_TRAP_INT_ENA_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_COCPU_TRAP_INT_ENA_Msk = 0x20000 + // Bit COCPU_TRAP_INT_ENA. + RTC_CNTL_INT_ENA_RTC_COCPU_TRAP_INT_ENA = 0x20000 + // Position of TOUCH_TIMEOUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA = 0x40000 + // Position of GLITCH_DET_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_GLITCH_DET_INT_ENA_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_GLITCH_DET_INT_ENA_Msk = 0x80000 + // Bit GLITCH_DET_INT_ENA. + RTC_CNTL_INT_ENA_RTC_GLITCH_DET_INT_ENA = 0x80000 + + // INT_RAW_RTC: RTC interrupt raw register + // Position of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW_Msk = 0x1 + // Bit SLP_WAKEUP_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW = 0x1 + // Position of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW_Msk = 0x2 + // Bit SLP_REJECT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW = 0x2 + // Position of SDIO_IDLE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SDIO_IDLE_INT_RAW_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SDIO_IDLE_INT_RAW_Msk = 0x4 + // Bit SDIO_IDLE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SDIO_IDLE_INT_RAW = 0x4 + // Position of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW_Pos = 0x3 + // Bit mask of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW_Msk = 0x8 + // Bit WDT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW = 0x8 + // Position of TOUCH_SCAN_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW = 0x10 + // Position of ULP_CP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_ULP_CP_INT_RAW_Pos = 0x5 + // Bit mask of ULP_CP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_ULP_CP_INT_RAW_Msk = 0x20 + // Bit ULP_CP_INT_RAW. + RTC_CNTL_INT_RAW_RTC_ULP_CP_INT_RAW = 0x20 + // Position of TOUCH_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_DONE_INT_RAW_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_DONE_INT_RAW_Msk = 0x40 + // Bit TOUCH_DONE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_DONE_INT_RAW = 0x40 + // Position of TOUCH_ACTIVE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_ACTIVE_INT_RAW_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_ACTIVE_INT_RAW_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_ACTIVE_INT_RAW = 0x80 + // Position of TOUCH_INACTIVE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_INACTIVE_INT_RAW_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_INACTIVE_INT_RAW_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_INACTIVE_INT_RAW = 0x100 + // Position of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW_Msk = 0x200 + // Bit BROWN_OUT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW = 0x200 + // Position of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW_Msk = 0x400 + // Bit MAIN_TIMER_INT_RAW. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW = 0x400 + // Position of SARADC1_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SARADC1_INT_RAW_Pos = 0xb + // Bit mask of SARADC1_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SARADC1_INT_RAW_Msk = 0x800 + // Bit SARADC1_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SARADC1_INT_RAW = 0x800 + // Position of TSENS_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TSENS_INT_RAW_Pos = 0xc + // Bit mask of TSENS_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TSENS_INT_RAW_Msk = 0x1000 + // Bit TSENS_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TSENS_INT_RAW = 0x1000 + // Position of COCPU_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_COCPU_INT_RAW_Pos = 0xd + // Bit mask of COCPU_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_COCPU_INT_RAW_Msk = 0x2000 + // Bit COCPU_INT_RAW. + RTC_CNTL_INT_RAW_RTC_COCPU_INT_RAW = 0x2000 + // Position of SARADC2_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SARADC2_INT_RAW_Pos = 0xe + // Bit mask of SARADC2_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SARADC2_INT_RAW_Msk = 0x4000 + // Bit SARADC2_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SARADC2_INT_RAW = 0x4000 + // Position of SWD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW_Pos = 0xf + // Bit mask of SWD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW_Msk = 0x8000 + // Bit SWD_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW = 0x8000 + // Position of XTAL32K_DEAD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_XTAL32K_DEAD_INT_RAW_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_XTAL32K_DEAD_INT_RAW_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_RAW. + RTC_CNTL_INT_RAW_RTC_XTAL32K_DEAD_INT_RAW = 0x10000 + // Position of COCPU_TRAP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_COCPU_TRAP_INT_RAW_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_COCPU_TRAP_INT_RAW_Msk = 0x20000 + // Bit COCPU_TRAP_INT_RAW. + RTC_CNTL_INT_RAW_RTC_COCPU_TRAP_INT_RAW = 0x20000 + // Position of TOUCH_TIMEOUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW = 0x40000 + // Position of GLITCH_DET_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_GLITCH_DET_INT_RAW_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_GLITCH_DET_INT_RAW_Msk = 0x80000 + // Bit GLITCH_DET_INT_RAW. + RTC_CNTL_INT_RAW_RTC_GLITCH_DET_INT_RAW = 0x80000 + + // INT_ST_RTC: RTC interrupt state register + // Position of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ST. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST = 0x1 + // Position of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST_Msk = 0x2 + // Bit SLP_REJECT_INT_ST. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST = 0x2 + // Position of SDIO_IDLE_INT_ST field. + RTC_CNTL_INT_ST_RTC_SDIO_IDLE_INT_ST_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_ST field. + RTC_CNTL_INT_ST_RTC_SDIO_IDLE_INT_ST_Msk = 0x4 + // Bit SDIO_IDLE_INT_ST. + RTC_CNTL_INT_ST_RTC_SDIO_IDLE_INT_ST = 0x4 + // Position of WDT_INT_ST field. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST_Pos = 0x3 + // Bit mask of WDT_INT_ST field. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST_Msk = 0x8 + // Bit WDT_INT_ST. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST = 0x8 + // Position of TOUCH_SCAN_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_SCAN_DONE_INT_ST_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_SCAN_DONE_INT_ST_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_SCAN_DONE_INT_ST = 0x10 + // Position of ULP_CP_INT_ST field. + RTC_CNTL_INT_ST_RTC_ULP_CP_INT_ST_Pos = 0x5 + // Bit mask of ULP_CP_INT_ST field. + RTC_CNTL_INT_ST_RTC_ULP_CP_INT_ST_Msk = 0x20 + // Bit ULP_CP_INT_ST. + RTC_CNTL_INT_ST_RTC_ULP_CP_INT_ST = 0x20 + // Position of TOUCH_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_DONE_INT_ST_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_DONE_INT_ST_Msk = 0x40 + // Bit TOUCH_DONE_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_DONE_INT_ST = 0x40 + // Position of TOUCH_ACTIVE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_ACTIVE_INT_ST_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_ACTIVE_INT_ST_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_ACTIVE_INT_ST = 0x80 + // Position of TOUCH_INACTIVE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_INACTIVE_INT_ST_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_INACTIVE_INT_ST_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_INACTIVE_INT_ST = 0x100 + // Position of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST_Msk = 0x200 + // Bit BROWN_OUT_INT_ST. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST = 0x200 + // Position of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST_Msk = 0x400 + // Bit MAIN_TIMER_INT_ST. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST = 0x400 + // Position of SARADC1_INT_ST field. + RTC_CNTL_INT_ST_RTC_SARADC1_INT_ST_Pos = 0xb + // Bit mask of SARADC1_INT_ST field. + RTC_CNTL_INT_ST_RTC_SARADC1_INT_ST_Msk = 0x800 + // Bit SARADC1_INT_ST. + RTC_CNTL_INT_ST_RTC_SARADC1_INT_ST = 0x800 + // Position of TSENS_INT_ST field. + RTC_CNTL_INT_ST_RTC_TSENS_INT_ST_Pos = 0xc + // Bit mask of TSENS_INT_ST field. + RTC_CNTL_INT_ST_RTC_TSENS_INT_ST_Msk = 0x1000 + // Bit TSENS_INT_ST. + RTC_CNTL_INT_ST_RTC_TSENS_INT_ST = 0x1000 + // Position of COCPU_INT_ST field. + RTC_CNTL_INT_ST_RTC_COCPU_INT_ST_Pos = 0xd + // Bit mask of COCPU_INT_ST field. + RTC_CNTL_INT_ST_RTC_COCPU_INT_ST_Msk = 0x2000 + // Bit COCPU_INT_ST. + RTC_CNTL_INT_ST_RTC_COCPU_INT_ST = 0x2000 + // Position of SARADC2_INT_ST field. + RTC_CNTL_INT_ST_RTC_SARADC2_INT_ST_Pos = 0xe + // Bit mask of SARADC2_INT_ST field. + RTC_CNTL_INT_ST_RTC_SARADC2_INT_ST_Msk = 0x4000 + // Bit SARADC2_INT_ST. + RTC_CNTL_INT_ST_RTC_SARADC2_INT_ST = 0x4000 + // Position of SWD_INT_ST field. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST_Pos = 0xf + // Bit mask of SWD_INT_ST field. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST_Msk = 0x8000 + // Bit SWD_INT_ST. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST = 0x8000 + // Position of XTAL32K_DEAD_INT_ST field. + RTC_CNTL_INT_ST_RTC_XTAL32K_DEAD_INT_ST_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ST field. + RTC_CNTL_INT_ST_RTC_XTAL32K_DEAD_INT_ST_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ST. + RTC_CNTL_INT_ST_RTC_XTAL32K_DEAD_INT_ST = 0x10000 + // Position of COCPU_TRAP_INT_ST field. + RTC_CNTL_INT_ST_RTC_COCPU_TRAP_INT_ST_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_ST field. + RTC_CNTL_INT_ST_RTC_COCPU_TRAP_INT_ST_Msk = 0x20000 + // Bit COCPU_TRAP_INT_ST. + RTC_CNTL_INT_ST_RTC_COCPU_TRAP_INT_ST = 0x20000 + // Position of TOUCH_TIMEOUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_TIMEOUT_INT_ST_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_TIMEOUT_INT_ST_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_TIMEOUT_INT_ST = 0x40000 + // Position of GLITCH_DET_INT_ST field. + RTC_CNTL_INT_ST_RTC_GLITCH_DET_INT_ST_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ST field. + RTC_CNTL_INT_ST_RTC_GLITCH_DET_INT_ST_Msk = 0x80000 + // Bit GLITCH_DET_INT_ST. + RTC_CNTL_INT_ST_RTC_GLITCH_DET_INT_ST = 0x80000 + + // INT_CLR_RTC: RTC interrupt clear register + // Position of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR_Msk = 0x1 + // Bit SLP_WAKEUP_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR = 0x1 + // Position of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR_Msk = 0x2 + // Bit SLP_REJECT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR = 0x2 + // Position of SDIO_IDLE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SDIO_IDLE_INT_CLR_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SDIO_IDLE_INT_CLR_Msk = 0x4 + // Bit SDIO_IDLE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SDIO_IDLE_INT_CLR = 0x4 + // Position of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR_Pos = 0x3 + // Bit mask of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR_Msk = 0x8 + // Bit WDT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR = 0x8 + // Position of TOUCH_SCAN_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR = 0x10 + // Position of ULP_CP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_ULP_CP_INT_CLR_Pos = 0x5 + // Bit mask of ULP_CP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_ULP_CP_INT_CLR_Msk = 0x20 + // Bit ULP_CP_INT_CLR. + RTC_CNTL_INT_CLR_RTC_ULP_CP_INT_CLR = 0x20 + // Position of TOUCH_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_DONE_INT_CLR_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_DONE_INT_CLR_Msk = 0x40 + // Bit TOUCH_DONE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_DONE_INT_CLR = 0x40 + // Position of TOUCH_ACTIVE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_ACTIVE_INT_CLR_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_ACTIVE_INT_CLR_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_ACTIVE_INT_CLR = 0x80 + // Position of TOUCH_INACTIVE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_INACTIVE_INT_CLR_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_INACTIVE_INT_CLR_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_INACTIVE_INT_CLR = 0x100 + // Position of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR_Msk = 0x200 + // Bit BROWN_OUT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR = 0x200 + // Position of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR_Msk = 0x400 + // Bit MAIN_TIMER_INT_CLR. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR = 0x400 + // Position of SARADC1_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SARADC1_INT_CLR_Pos = 0xb + // Bit mask of SARADC1_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SARADC1_INT_CLR_Msk = 0x800 + // Bit SARADC1_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SARADC1_INT_CLR = 0x800 + // Position of TSENS_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TSENS_INT_CLR_Pos = 0xc + // Bit mask of TSENS_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TSENS_INT_CLR_Msk = 0x1000 + // Bit TSENS_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TSENS_INT_CLR = 0x1000 + // Position of COCPU_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_COCPU_INT_CLR_Pos = 0xd + // Bit mask of COCPU_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_COCPU_INT_CLR_Msk = 0x2000 + // Bit COCPU_INT_CLR. + RTC_CNTL_INT_CLR_RTC_COCPU_INT_CLR = 0x2000 + // Position of SARADC2_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SARADC2_INT_CLR_Pos = 0xe + // Bit mask of SARADC2_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SARADC2_INT_CLR_Msk = 0x4000 + // Bit SARADC2_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SARADC2_INT_CLR = 0x4000 + // Position of SWD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR_Pos = 0xf + // Bit mask of SWD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR_Msk = 0x8000 + // Bit SWD_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR = 0x8000 + // Position of XTAL32K_DEAD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_XTAL32K_DEAD_INT_CLR_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_XTAL32K_DEAD_INT_CLR_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_CLR. + RTC_CNTL_INT_CLR_RTC_XTAL32K_DEAD_INT_CLR = 0x10000 + // Position of COCPU_TRAP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_COCPU_TRAP_INT_CLR_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_COCPU_TRAP_INT_CLR_Msk = 0x20000 + // Bit COCPU_TRAP_INT_CLR. + RTC_CNTL_INT_CLR_RTC_COCPU_TRAP_INT_CLR = 0x20000 + // Position of TOUCH_TIMEOUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR = 0x40000 + // Position of GLITCH_DET_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_GLITCH_DET_INT_CLR_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_GLITCH_DET_INT_CLR_Msk = 0x80000 + // Bit GLITCH_DET_INT_CLR. + RTC_CNTL_INT_CLR_RTC_GLITCH_DET_INT_CLR = 0x80000 + + // STORE0: Reservation register 0 + // Position of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Pos = 0x0 + // Bit mask of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Msk = 0xffffffff + + // STORE1: Reservation register 1 + // Position of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Pos = 0x0 + // Bit mask of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Msk = 0xffffffff + + // STORE2: Reservation register 2 + // Position of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Pos = 0x0 + // Bit mask of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Msk = 0xffffffff + + // STORE3: Reservation register 3 + // Position of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Pos = 0x0 + // Bit mask of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Msk = 0xffffffff + + // EXT_XTL_CONF: 32 kHz crystal oscillator configuration register + // Position of XTAL32K_WDT_EN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_EN_Pos = 0x0 + // Bit mask of XTAL32K_WDT_EN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_EN_Msk = 0x1 + // Bit XTAL32K_WDT_EN. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_EN = 0x1 + // Position of XTAL32K_WDT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_CLK_FO_Pos = 0x1 + // Bit mask of XTAL32K_WDT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_CLK_FO_Msk = 0x2 + // Bit XTAL32K_WDT_CLK_FO. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_CLK_FO = 0x2 + // Position of XTAL32K_WDT_RESET field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_RESET_Pos = 0x2 + // Bit mask of XTAL32K_WDT_RESET field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_RESET_Msk = 0x4 + // Bit XTAL32K_WDT_RESET. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_RESET = 0x4 + // Position of XTAL32K_EXT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_EXT_CLK_FO_Pos = 0x3 + // Bit mask of XTAL32K_EXT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_EXT_CLK_FO_Msk = 0x8 + // Bit XTAL32K_EXT_CLK_FO. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_EXT_CLK_FO = 0x8 + // Position of XTAL32K_AUTO_BACKUP field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_BACKUP_Pos = 0x4 + // Bit mask of XTAL32K_AUTO_BACKUP field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_BACKUP_Msk = 0x10 + // Bit XTAL32K_AUTO_BACKUP. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_BACKUP = 0x10 + // Position of XTAL32K_AUTO_RESTART field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RESTART_Pos = 0x5 + // Bit mask of XTAL32K_AUTO_RESTART field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RESTART_Msk = 0x20 + // Bit XTAL32K_AUTO_RESTART. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RESTART = 0x20 + // Position of XTAL32K_AUTO_RETURN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RETURN_Pos = 0x6 + // Bit mask of XTAL32K_AUTO_RETURN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RETURN_Msk = 0x40 + // Bit XTAL32K_AUTO_RETURN. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RETURN = 0x40 + // Position of XTAL32K_XPD_FORCE field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_XPD_FORCE_Pos = 0x7 + // Bit mask of XTAL32K_XPD_FORCE field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_XPD_FORCE_Msk = 0x80 + // Bit XTAL32K_XPD_FORCE. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_XPD_FORCE = 0x80 + // Position of ENCKINIT_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_ENCKINIT_XTAL_32K_Pos = 0x8 + // Bit mask of ENCKINIT_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_ENCKINIT_XTAL_32K_Msk = 0x100 + // Bit ENCKINIT_XTAL_32K. + RTC_CNTL_EXT_XTL_CONF_ENCKINIT_XTAL_32K = 0x100 + // Position of DBUF_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DBUF_XTAL_32K_Pos = 0x9 + // Bit mask of DBUF_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DBUF_XTAL_32K_Msk = 0x200 + // Bit DBUF_XTAL_32K. + RTC_CNTL_EXT_XTL_CONF_DBUF_XTAL_32K = 0x200 + // Position of DGM_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DGM_XTAL_32K_Pos = 0xa + // Bit mask of DGM_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DGM_XTAL_32K_Msk = 0x1c00 + // Position of DRES_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DRES_XTAL_32K_Pos = 0xd + // Bit mask of DRES_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DRES_XTAL_32K_Msk = 0xe000 + // Position of XPD_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_XPD_XTAL_32K_Pos = 0x10 + // Bit mask of XPD_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_XPD_XTAL_32K_Msk = 0x10000 + // Bit XPD_XTAL_32K. + RTC_CNTL_EXT_XTL_CONF_XPD_XTAL_32K = 0x10000 + // Position of DAC_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DAC_XTAL_32K_Pos = 0x11 + // Bit mask of DAC_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DAC_XTAL_32K_Msk = 0xe0000 + // Position of WDT_STATE field. + RTC_CNTL_EXT_XTL_CONF_WDT_STATE_Pos = 0x14 + // Bit mask of WDT_STATE field. + RTC_CNTL_EXT_XTL_CONF_WDT_STATE_Msk = 0x700000 + // Position of XTAL32K_GPIO_SEL field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_GPIO_SEL_Pos = 0x17 + // Bit mask of XTAL32K_GPIO_SEL field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_GPIO_SEL_Msk = 0x800000 + // Bit XTAL32K_GPIO_SEL. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_GPIO_SEL = 0x800000 + // Position of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Pos = 0x1e + // Bit mask of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Msk = 0x40000000 + // Bit XTL_EXT_CTR_LV. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV = 0x40000000 + // Position of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Pos = 0x1f + // Bit mask of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Msk = 0x80000000 + // Bit XTL_EXT_CTR_EN. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN = 0x80000000 + + // EXT_WAKEUP_CONF: GPIO wakeup configuration register + // Position of GPIO_WAKEUP_FILTER field. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER_Pos = 0x1d + // Bit mask of GPIO_WAKEUP_FILTER field. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER_Msk = 0x20000000 + // Bit GPIO_WAKEUP_FILTER. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER = 0x20000000 + // Position of EXT_WAKEUP0_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP0_LV_Pos = 0x1e + // Bit mask of EXT_WAKEUP0_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP0_LV_Msk = 0x40000000 + // Bit EXT_WAKEUP0_LV. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP0_LV = 0x40000000 + // Position of EXT_WAKEUP1_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP1_LV_Pos = 0x1f + // Bit mask of EXT_WAKEUP1_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP1_LV_Msk = 0x80000000 + // Bit EXT_WAKEUP1_LV. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP1_LV = 0x80000000 + + // SLP_REJECT_CONF: Configures sleep / reject options + // Position of SLEEP_REJECT_ENA field. + RTC_CNTL_SLP_REJECT_CONF_SLEEP_REJECT_ENA_Pos = 0xd + // Bit mask of SLEEP_REJECT_ENA field. + RTC_CNTL_SLP_REJECT_CONF_SLEEP_REJECT_ENA_Msk = 0x3fffe000 + // Position of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Pos = 0x1e + // Bit mask of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Msk = 0x40000000 + // Bit LIGHT_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN = 0x40000000 + // Position of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Pos = 0x1f + // Bit mask of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Msk = 0x80000000 + // Bit DEEP_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN = 0x80000000 + + // CPU_PERIOD_CONF: CPU sel option + // Position of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Pos = 0x1d + // Bit mask of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Msk = 0x20000000 + // Bit CPUSEL_CONF. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF = 0x20000000 + // Position of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Pos = 0x1e + // Bit mask of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Msk = 0xc0000000 + + // SDIO_ACT_CONF: configure sdio active register + // Position of SDIO_ACT_DNUM field. + RTC_CNTL_SDIO_ACT_CONF_SDIO_ACT_DNUM_Pos = 0x16 + // Bit mask of SDIO_ACT_DNUM field. + RTC_CNTL_SDIO_ACT_CONF_SDIO_ACT_DNUM_Msk = 0xffc00000 + + // CLK_CONF: RTC clock configuration register + // Position of CK8M_DIV_SEL_VLD field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD_Pos = 0x3 + // Bit mask of CK8M_DIV_SEL_VLD field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD_Msk = 0x8 + // Bit CK8M_DIV_SEL_VLD. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD = 0x8 + // Position of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Pos = 0x4 + // Bit mask of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Msk = 0x30 + // Position of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Pos = 0x6 + // Bit mask of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Msk = 0x40 + // Bit ENB_CK8M. + RTC_CNTL_CLK_CONF_ENB_CK8M = 0x40 + // Position of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Pos = 0x7 + // Bit mask of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Msk = 0x80 + // Bit ENB_CK8M_DIV. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV = 0x80 + // Position of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Pos = 0x8 + // Bit mask of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Msk = 0x100 + // Bit DIG_XTAL32K_EN. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN = 0x100 + // Position of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Pos = 0x9 + // Bit mask of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Msk = 0x200 + // Bit DIG_CLK8M_D256_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN = 0x200 + // Position of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Pos = 0xa + // Bit mask of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Msk = 0x400 + // Bit DIG_CLK8M_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN = 0x400 + // Position of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Pos = 0xc + // Bit mask of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Msk = 0x7000 + // Position of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Pos = 0xf + // Bit mask of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Msk = 0x8000 + // Bit XTAL_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING = 0x8000 + // Position of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Pos = 0x10 + // Bit mask of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Msk = 0x10000 + // Bit CK8M_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING = 0x10000 + // Position of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Pos = 0x11 + // Bit mask of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Msk = 0x1fe0000 + // Position of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Pos = 0x19 + // Bit mask of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Msk = 0x2000000 + // Bit CK8M_FORCE_PD. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD = 0x2000000 + // Position of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Pos = 0x1a + // Bit mask of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Msk = 0x4000000 + // Bit CK8M_FORCE_PU. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU = 0x4000000 + // Position of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Pos = 0x1d + // Bit mask of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Msk = 0x20000000 + // Bit FAST_CLK_RTC_SEL. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL = 0x20000000 + // Position of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Pos = 0x1e + // Bit mask of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Msk = 0xc0000000 + + // SLOW_CLK_CONF: RTC slow clock configuration register + // Position of ANA_CLK_DIV_VLD field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD_Pos = 0x16 + // Bit mask of ANA_CLK_DIV_VLD field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD_Msk = 0x400000 + // Bit ANA_CLK_DIV_VLD. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD = 0x400000 + // Position of ANA_CLK_DIV field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_Pos = 0x17 + // Bit mask of ANA_CLK_DIV field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_Msk = 0x7f800000 + // Position of SLOW_CLK_NEXT_EDGE field. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE_Pos = 0x1f + // Bit mask of SLOW_CLK_NEXT_EDGE field. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE_Msk = 0x80000000 + // Bit SLOW_CLK_NEXT_EDGE. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE = 0x80000000 + + // SDIO_CONF: configure vddsdio register + // Position of SDIO_TIMER_TARGET field. + RTC_CNTL_SDIO_CONF_SDIO_TIMER_TARGET_Pos = 0x0 + // Bit mask of SDIO_TIMER_TARGET field. + RTC_CNTL_SDIO_CONF_SDIO_TIMER_TARGET_Msk = 0xff + // Position of SDIO_DTHDRV field. + RTC_CNTL_SDIO_CONF_SDIO_DTHDRV_Pos = 0x9 + // Bit mask of SDIO_DTHDRV field. + RTC_CNTL_SDIO_CONF_SDIO_DTHDRV_Msk = 0x600 + // Position of SDIO_DCAP field. + RTC_CNTL_SDIO_CONF_SDIO_DCAP_Pos = 0xb + // Bit mask of SDIO_DCAP field. + RTC_CNTL_SDIO_CONF_SDIO_DCAP_Msk = 0x1800 + // Position of SDIO_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_INITI_Pos = 0xd + // Bit mask of SDIO_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_INITI_Msk = 0x6000 + // Position of SDIO_EN_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_EN_INITI_Pos = 0xf + // Bit mask of SDIO_EN_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_EN_INITI_Msk = 0x8000 + // Bit SDIO_EN_INITI. + RTC_CNTL_SDIO_CONF_SDIO_EN_INITI = 0x8000 + // Position of SDIO_DCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_DCURLIM_Pos = 0x10 + // Bit mask of SDIO_DCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_DCURLIM_Msk = 0x70000 + // Position of SDIO_MODECURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_MODECURLIM_Pos = 0x13 + // Bit mask of SDIO_MODECURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_MODECURLIM_Msk = 0x80000 + // Bit SDIO_MODECURLIM. + RTC_CNTL_SDIO_CONF_SDIO_MODECURLIM = 0x80000 + // Position of SDIO_ENCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_ENCURLIM_Pos = 0x14 + // Bit mask of SDIO_ENCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_ENCURLIM_Msk = 0x100000 + // Bit SDIO_ENCURLIM. + RTC_CNTL_SDIO_CONF_SDIO_ENCURLIM = 0x100000 + // Position of SDIO_REG_PD_EN field. + RTC_CNTL_SDIO_CONF_SDIO_REG_PD_EN_Pos = 0x15 + // Bit mask of SDIO_REG_PD_EN field. + RTC_CNTL_SDIO_CONF_SDIO_REG_PD_EN_Msk = 0x200000 + // Bit SDIO_REG_PD_EN. + RTC_CNTL_SDIO_CONF_SDIO_REG_PD_EN = 0x200000 + // Position of SDIO_FORCE field. + RTC_CNTL_SDIO_CONF_SDIO_FORCE_Pos = 0x16 + // Bit mask of SDIO_FORCE field. + RTC_CNTL_SDIO_CONF_SDIO_FORCE_Msk = 0x400000 + // Bit SDIO_FORCE. + RTC_CNTL_SDIO_CONF_SDIO_FORCE = 0x400000 + // Position of SDIO_TIEH field. + RTC_CNTL_SDIO_CONF_SDIO_TIEH_Pos = 0x17 + // Bit mask of SDIO_TIEH field. + RTC_CNTL_SDIO_CONF_SDIO_TIEH_Msk = 0x800000 + // Bit SDIO_TIEH. + RTC_CNTL_SDIO_CONF_SDIO_TIEH = 0x800000 + // Position of REG1P8_READY field. + RTC_CNTL_SDIO_CONF_REG1P8_READY_Pos = 0x18 + // Bit mask of REG1P8_READY field. + RTC_CNTL_SDIO_CONF_REG1P8_READY_Msk = 0x1000000 + // Bit REG1P8_READY. + RTC_CNTL_SDIO_CONF_REG1P8_READY = 0x1000000 + // Position of DREFL_SDIO field. + RTC_CNTL_SDIO_CONF_DREFL_SDIO_Pos = 0x19 + // Bit mask of DREFL_SDIO field. + RTC_CNTL_SDIO_CONF_DREFL_SDIO_Msk = 0x6000000 + // Position of DREFM_SDIO field. + RTC_CNTL_SDIO_CONF_DREFM_SDIO_Pos = 0x1b + // Bit mask of DREFM_SDIO field. + RTC_CNTL_SDIO_CONF_DREFM_SDIO_Msk = 0x18000000 + // Position of DREFH_SDIO field. + RTC_CNTL_SDIO_CONF_DREFH_SDIO_Pos = 0x1d + // Bit mask of DREFH_SDIO field. + RTC_CNTL_SDIO_CONF_DREFH_SDIO_Msk = 0x60000000 + // Position of XPD_SDIO field. + RTC_CNTL_SDIO_CONF_XPD_SDIO_Pos = 0x1f + // Bit mask of XPD_SDIO field. + RTC_CNTL_SDIO_CONF_XPD_SDIO_Msk = 0x80000000 + // Bit XPD_SDIO. + RTC_CNTL_SDIO_CONF_XPD_SDIO = 0x80000000 + + // BIAS_CONF: configure power register + // Position of BIAS_BUF_IDLE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE_Pos = 0xa + // Bit mask of BIAS_BUF_IDLE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE_Msk = 0x400 + // Bit BIAS_BUF_IDLE. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE = 0x400 + // Position of BIAS_BUF_WAKE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE_Pos = 0xb + // Bit mask of BIAS_BUF_WAKE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE_Msk = 0x800 + // Bit BIAS_BUF_WAKE. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE = 0x800 + // Position of BIAS_BUF_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP_Pos = 0xc + // Bit mask of BIAS_BUF_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP_Msk = 0x1000 + // Bit BIAS_BUF_DEEP_SLP. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP = 0x1000 + // Position of BIAS_BUF_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR_Pos = 0xd + // Bit mask of BIAS_BUF_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR_Msk = 0x2000 + // Bit BIAS_BUF_MONITOR. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR = 0x2000 + // Position of PD_CUR_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP_Pos = 0xe + // Bit mask of PD_CUR_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP_Msk = 0x4000 + // Bit PD_CUR_DEEP_SLP. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP = 0x4000 + // Position of PD_CUR_MONITOR field. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR_Pos = 0xf + // Bit mask of PD_CUR_MONITOR field. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR_Msk = 0x8000 + // Bit PD_CUR_MONITOR. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR = 0x8000 + // Position of BIAS_SLEEP_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP_Pos = 0x10 + // Bit mask of BIAS_SLEEP_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP_Msk = 0x10000 + // Bit BIAS_SLEEP_DEEP_SLP. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP = 0x10000 + // Position of BIAS_SLEEP_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR_Pos = 0x11 + // Bit mask of BIAS_SLEEP_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR_Msk = 0x20000 + // Bit BIAS_SLEEP_MONITOR. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR = 0x20000 + // Position of DBG_ATTEN_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_DEEP_SLP_Pos = 0x12 + // Bit mask of DBG_ATTEN_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_DEEP_SLP_Msk = 0x3c0000 + // Position of DBG_ATTEN_MONITOR field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_MONITOR_Pos = 0x16 + // Bit mask of DBG_ATTEN_MONITOR field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_MONITOR_Msk = 0x3c00000 + // Position of ENB_SCK_XTAL field. + RTC_CNTL_BIAS_CONF_ENB_SCK_XTAL_Pos = 0x1a + // Bit mask of ENB_SCK_XTAL field. + RTC_CNTL_BIAS_CONF_ENB_SCK_XTAL_Msk = 0x4000000 + // Bit ENB_SCK_XTAL. + RTC_CNTL_BIAS_CONF_ENB_SCK_XTAL = 0x4000000 + // Position of INC_HEARTBEAT_REFRESH field. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_REFRESH_Pos = 0x1b + // Bit mask of INC_HEARTBEAT_REFRESH field. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_REFRESH_Msk = 0x8000000 + // Bit INC_HEARTBEAT_REFRESH. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_REFRESH = 0x8000000 + // Position of DEC_HEARTBEAT_PERIOD field. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_PERIOD_Pos = 0x1c + // Bit mask of DEC_HEARTBEAT_PERIOD field. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_PERIOD_Msk = 0x10000000 + // Bit DEC_HEARTBEAT_PERIOD. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_PERIOD = 0x10000000 + // Position of INC_HEARTBEAT_PERIOD field. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_PERIOD_Pos = 0x1d + // Bit mask of INC_HEARTBEAT_PERIOD field. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_PERIOD_Msk = 0x20000000 + // Bit INC_HEARTBEAT_PERIOD. + RTC_CNTL_BIAS_CONF_INC_HEARTBEAT_PERIOD = 0x20000000 + // Position of DEC_HEARTBEAT_WIDTH field. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_WIDTH_Pos = 0x1e + // Bit mask of DEC_HEARTBEAT_WIDTH field. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_WIDTH_Msk = 0x40000000 + // Bit DEC_HEARTBEAT_WIDTH. + RTC_CNTL_BIAS_CONF_DEC_HEARTBEAT_WIDTH = 0x40000000 + // Position of RST_BIAS_I2C field. + RTC_CNTL_BIAS_CONF_RST_BIAS_I2C_Pos = 0x1f + // Bit mask of RST_BIAS_I2C field. + RTC_CNTL_BIAS_CONF_RST_BIAS_I2C_Msk = 0x80000000 + // Bit RST_BIAS_I2C. + RTC_CNTL_BIAS_CONF_RST_BIAS_I2C = 0x80000000 + + // REG: RTC/DIG regulator configuration register + // Position of DIG_REG_DBIAS_SLP field. + RTC_CNTL_REG_DIG_REG_DBIAS_SLP_Pos = 0x8 + // Bit mask of DIG_REG_DBIAS_SLP field. + RTC_CNTL_REG_DIG_REG_DBIAS_SLP_Msk = 0x700 + // Position of DIG_REG_DBIAS_WAK field. + RTC_CNTL_REG_DIG_REG_DBIAS_WAK_Pos = 0xb + // Bit mask of DIG_REG_DBIAS_WAK field. + RTC_CNTL_REG_DIG_REG_DBIAS_WAK_Msk = 0x3800 + // Position of SCK_DCAP field. + RTC_CNTL_REG_SCK_DCAP_Pos = 0xe + // Bit mask of SCK_DCAP field. + RTC_CNTL_REG_SCK_DCAP_Msk = 0x3fc000 + // Position of DBIAS_SLP field. + RTC_CNTL_REG_DBIAS_SLP_Pos = 0x16 + // Bit mask of DBIAS_SLP field. + RTC_CNTL_REG_DBIAS_SLP_Msk = 0x1c00000 + // Position of DBIAS_WAK field. + RTC_CNTL_REG_DBIAS_WAK_Pos = 0x19 + // Bit mask of DBIAS_WAK field. + RTC_CNTL_REG_DBIAS_WAK_Msk = 0xe000000 + // Position of DBOOST_FORCE_PD field. + RTC_CNTL_REG_DBOOST_FORCE_PD_Pos = 0x1c + // Bit mask of DBOOST_FORCE_PD field. + RTC_CNTL_REG_DBOOST_FORCE_PD_Msk = 0x10000000 + // Bit DBOOST_FORCE_PD. + RTC_CNTL_REG_DBOOST_FORCE_PD = 0x10000000 + // Position of DBOOST_FORCE_PU field. + RTC_CNTL_REG_DBOOST_FORCE_PU_Pos = 0x1d + // Bit mask of DBOOST_FORCE_PU field. + RTC_CNTL_REG_DBOOST_FORCE_PU_Msk = 0x20000000 + // Bit DBOOST_FORCE_PU. + RTC_CNTL_REG_DBOOST_FORCE_PU = 0x20000000 + // Position of REGULATOR_FORCE_PD field. + RTC_CNTL_REG_REGULATOR_FORCE_PD_Pos = 0x1e + // Bit mask of REGULATOR_FORCE_PD field. + RTC_CNTL_REG_REGULATOR_FORCE_PD_Msk = 0x40000000 + // Bit REGULATOR_FORCE_PD. + RTC_CNTL_REG_REGULATOR_FORCE_PD = 0x40000000 + // Position of REGULATOR_FORCE_PU field. + RTC_CNTL_REG_REGULATOR_FORCE_PU_Pos = 0x1f + // Bit mask of REGULATOR_FORCE_PU field. + RTC_CNTL_REG_REGULATOR_FORCE_PU_Msk = 0x80000000 + // Bit REGULATOR_FORCE_PU. + RTC_CNTL_REG_REGULATOR_FORCE_PU = 0x80000000 + + // PWC: RTC power configuraiton register + // Position of FASTMEM_FORCE_NOISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_NOISO_Pos = 0x0 + // Bit mask of FASTMEM_FORCE_NOISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_NOISO_Msk = 0x1 + // Bit FASTMEM_FORCE_NOISO. + RTC_CNTL_PWC_FASTMEM_FORCE_NOISO = 0x1 + // Position of FASTMEM_FORCE_ISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_ISO_Pos = 0x1 + // Bit mask of FASTMEM_FORCE_ISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_ISO_Msk = 0x2 + // Bit FASTMEM_FORCE_ISO. + RTC_CNTL_PWC_FASTMEM_FORCE_ISO = 0x2 + // Position of SLOWMEM_FORCE_NOISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_NOISO_Pos = 0x2 + // Bit mask of SLOWMEM_FORCE_NOISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_NOISO_Msk = 0x4 + // Bit SLOWMEM_FORCE_NOISO. + RTC_CNTL_PWC_SLOWMEM_FORCE_NOISO = 0x4 + // Position of SLOWMEM_FORCE_ISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_ISO_Pos = 0x3 + // Bit mask of SLOWMEM_FORCE_ISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_ISO_Msk = 0x8 + // Bit SLOWMEM_FORCE_ISO. + RTC_CNTL_PWC_SLOWMEM_FORCE_ISO = 0x8 + // Position of FORCE_ISO field. + RTC_CNTL_PWC_FORCE_ISO_Pos = 0x4 + // Bit mask of FORCE_ISO field. + RTC_CNTL_PWC_FORCE_ISO_Msk = 0x10 + // Bit FORCE_ISO. + RTC_CNTL_PWC_FORCE_ISO = 0x10 + // Position of FORCE_NOISO field. + RTC_CNTL_PWC_FORCE_NOISO_Pos = 0x5 + // Bit mask of FORCE_NOISO field. + RTC_CNTL_PWC_FORCE_NOISO_Msk = 0x20 + // Bit FORCE_NOISO. + RTC_CNTL_PWC_FORCE_NOISO = 0x20 + // Position of FASTMEM_FOLW_CPU field. + RTC_CNTL_PWC_FASTMEM_FOLW_CPU_Pos = 0x6 + // Bit mask of FASTMEM_FOLW_CPU field. + RTC_CNTL_PWC_FASTMEM_FOLW_CPU_Msk = 0x40 + // Bit FASTMEM_FOLW_CPU. + RTC_CNTL_PWC_FASTMEM_FOLW_CPU = 0x40 + // Position of FASTMEM_FORCE_LPD field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPD_Pos = 0x7 + // Bit mask of FASTMEM_FORCE_LPD field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPD_Msk = 0x80 + // Bit FASTMEM_FORCE_LPD. + RTC_CNTL_PWC_FASTMEM_FORCE_LPD = 0x80 + // Position of FASTMEM_FORCE_LPU field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPU_Pos = 0x8 + // Bit mask of FASTMEM_FORCE_LPU field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPU_Msk = 0x100 + // Bit FASTMEM_FORCE_LPU. + RTC_CNTL_PWC_FASTMEM_FORCE_LPU = 0x100 + // Position of SLOWMEM_FOLW_CPU field. + RTC_CNTL_PWC_SLOWMEM_FOLW_CPU_Pos = 0x9 + // Bit mask of SLOWMEM_FOLW_CPU field. + RTC_CNTL_PWC_SLOWMEM_FOLW_CPU_Msk = 0x200 + // Bit SLOWMEM_FOLW_CPU. + RTC_CNTL_PWC_SLOWMEM_FOLW_CPU = 0x200 + // Position of SLOWMEM_FORCE_LPD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPD_Pos = 0xa + // Bit mask of SLOWMEM_FORCE_LPD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPD_Msk = 0x400 + // Bit SLOWMEM_FORCE_LPD. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPD = 0x400 + // Position of SLOWMEM_FORCE_LPU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPU_Pos = 0xb + // Bit mask of SLOWMEM_FORCE_LPU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPU_Msk = 0x800 + // Bit SLOWMEM_FORCE_LPU. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPU = 0x800 + // Position of FASTMEM_FORCE_PD field. + RTC_CNTL_PWC_FASTMEM_FORCE_PD_Pos = 0xc + // Bit mask of FASTMEM_FORCE_PD field. + RTC_CNTL_PWC_FASTMEM_FORCE_PD_Msk = 0x1000 + // Bit FASTMEM_FORCE_PD. + RTC_CNTL_PWC_FASTMEM_FORCE_PD = 0x1000 + // Position of FASTMEM_FORCE_PU field. + RTC_CNTL_PWC_FASTMEM_FORCE_PU_Pos = 0xd + // Bit mask of FASTMEM_FORCE_PU field. + RTC_CNTL_PWC_FASTMEM_FORCE_PU_Msk = 0x2000 + // Bit FASTMEM_FORCE_PU. + RTC_CNTL_PWC_FASTMEM_FORCE_PU = 0x2000 + // Position of FASTMEM_PD_EN field. + RTC_CNTL_PWC_FASTMEM_PD_EN_Pos = 0xe + // Bit mask of FASTMEM_PD_EN field. + RTC_CNTL_PWC_FASTMEM_PD_EN_Msk = 0x4000 + // Bit FASTMEM_PD_EN. + RTC_CNTL_PWC_FASTMEM_PD_EN = 0x4000 + // Position of SLOWMEM_FORCE_PD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_PD_Pos = 0xf + // Bit mask of SLOWMEM_FORCE_PD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_PD_Msk = 0x8000 + // Bit SLOWMEM_FORCE_PD. + RTC_CNTL_PWC_SLOWMEM_FORCE_PD = 0x8000 + // Position of SLOWMEM_FORCE_PU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_PU_Pos = 0x10 + // Bit mask of SLOWMEM_FORCE_PU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_PU_Msk = 0x10000 + // Bit SLOWMEM_FORCE_PU. + RTC_CNTL_PWC_SLOWMEM_FORCE_PU = 0x10000 + // Position of SLOWMEM_PD_EN field. + RTC_CNTL_PWC_SLOWMEM_PD_EN_Pos = 0x11 + // Bit mask of SLOWMEM_PD_EN field. + RTC_CNTL_PWC_SLOWMEM_PD_EN_Msk = 0x20000 + // Bit SLOWMEM_PD_EN. + RTC_CNTL_PWC_SLOWMEM_PD_EN = 0x20000 + // Position of FORCE_PD field. + RTC_CNTL_PWC_FORCE_PD_Pos = 0x12 + // Bit mask of FORCE_PD field. + RTC_CNTL_PWC_FORCE_PD_Msk = 0x40000 + // Bit FORCE_PD. + RTC_CNTL_PWC_FORCE_PD = 0x40000 + // Position of FORCE_PU field. + RTC_CNTL_PWC_FORCE_PU_Pos = 0x13 + // Bit mask of FORCE_PU field. + RTC_CNTL_PWC_FORCE_PU_Msk = 0x80000 + // Bit FORCE_PU. + RTC_CNTL_PWC_FORCE_PU = 0x80000 + // Position of PD_EN field. + RTC_CNTL_PWC_PD_EN_Pos = 0x14 + // Bit mask of PD_EN field. + RTC_CNTL_PWC_PD_EN_Msk = 0x100000 + // Bit PD_EN. + RTC_CNTL_PWC_PD_EN = 0x100000 + // Position of PAD_FORCE_HOLD field. + RTC_CNTL_PWC_PAD_FORCE_HOLD_Pos = 0x15 + // Bit mask of PAD_FORCE_HOLD field. + RTC_CNTL_PWC_PAD_FORCE_HOLD_Msk = 0x200000 + // Bit PAD_FORCE_HOLD. + RTC_CNTL_PWC_PAD_FORCE_HOLD = 0x200000 + + // DIG_PWC: Digital system power configuraiton register + // Position of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Msk = 0x8 + // Bit LSLP_MEM_FORCE_PD. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD = 0x8 + // Position of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Msk = 0x10 + // Bit LSLP_MEM_FORCE_PU. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU = 0x10 + // Position of ROM0_FORCE_PD field. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PD_Pos = 0x5 + // Bit mask of ROM0_FORCE_PD field. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PD_Msk = 0x20 + // Bit ROM0_FORCE_PD. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PD = 0x20 + // Position of ROM0_FORCE_PU field. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PU_Pos = 0x6 + // Bit mask of ROM0_FORCE_PU field. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PU_Msk = 0x40 + // Bit ROM0_FORCE_PU. + RTC_CNTL_DIG_PWC_ROM0_FORCE_PU = 0x40 + // Position of INTER_RAM0_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PD_Pos = 0x7 + // Bit mask of INTER_RAM0_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PD_Msk = 0x80 + // Bit INTER_RAM0_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PD = 0x80 + // Position of INTER_RAM0_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PU_Pos = 0x8 + // Bit mask of INTER_RAM0_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PU_Msk = 0x100 + // Bit INTER_RAM0_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM0_FORCE_PU = 0x100 + // Position of INTER_RAM1_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PD_Pos = 0x9 + // Bit mask of INTER_RAM1_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PD_Msk = 0x200 + // Bit INTER_RAM1_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PD = 0x200 + // Position of INTER_RAM1_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PU_Pos = 0xa + // Bit mask of INTER_RAM1_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PU_Msk = 0x400 + // Bit INTER_RAM1_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM1_FORCE_PU = 0x400 + // Position of INTER_RAM2_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PD_Pos = 0xb + // Bit mask of INTER_RAM2_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PD_Msk = 0x800 + // Bit INTER_RAM2_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PD = 0x800 + // Position of INTER_RAM2_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PU_Pos = 0xc + // Bit mask of INTER_RAM2_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PU_Msk = 0x1000 + // Bit INTER_RAM2_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM2_FORCE_PU = 0x1000 + // Position of INTER_RAM3_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PD_Pos = 0xd + // Bit mask of INTER_RAM3_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PD_Msk = 0x2000 + // Bit INTER_RAM3_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PD = 0x2000 + // Position of INTER_RAM3_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PU_Pos = 0xe + // Bit mask of INTER_RAM3_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PU_Msk = 0x4000 + // Bit INTER_RAM3_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM3_FORCE_PU = 0x4000 + // Position of INTER_RAM4_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PD_Pos = 0xf + // Bit mask of INTER_RAM4_FORCE_PD field. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PD_Msk = 0x8000 + // Bit INTER_RAM4_FORCE_PD. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PD = 0x8000 + // Position of INTER_RAM4_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PU_Pos = 0x10 + // Bit mask of INTER_RAM4_FORCE_PU field. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PU_Msk = 0x10000 + // Bit INTER_RAM4_FORCE_PU. + RTC_CNTL_DIG_PWC_INTER_RAM4_FORCE_PU = 0x10000 + // Position of WIFI_FORCE_PD field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD_Pos = 0x11 + // Bit mask of WIFI_FORCE_PD field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD_Msk = 0x20000 + // Bit WIFI_FORCE_PD. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD = 0x20000 + // Position of WIFI_FORCE_PU field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU_Pos = 0x12 + // Bit mask of WIFI_FORCE_PU field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU_Msk = 0x40000 + // Bit WIFI_FORCE_PU. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU = 0x40000 + // Position of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Pos = 0x13 + // Bit mask of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Msk = 0x80000 + // Bit DG_WRAP_FORCE_PD. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD = 0x80000 + // Position of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Pos = 0x14 + // Bit mask of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Msk = 0x100000 + // Bit DG_WRAP_FORCE_PU. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU = 0x100000 + // Position of DG_DCDC_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_DCDC_FORCE_PD_Pos = 0x15 + // Bit mask of DG_DCDC_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_DCDC_FORCE_PD_Msk = 0x200000 + // Bit DG_DCDC_FORCE_PD. + RTC_CNTL_DIG_PWC_DG_DCDC_FORCE_PD = 0x200000 + // Position of DG_DCDC_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_DCDC_FORCE_PU_Pos = 0x16 + // Bit mask of DG_DCDC_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_DCDC_FORCE_PU_Msk = 0x400000 + // Bit DG_DCDC_FORCE_PU. + RTC_CNTL_DIG_PWC_DG_DCDC_FORCE_PU = 0x400000 + // Position of DG_DCDC_PD_EN field. + RTC_CNTL_DIG_PWC_DG_DCDC_PD_EN_Pos = 0x17 + // Bit mask of DG_DCDC_PD_EN field. + RTC_CNTL_DIG_PWC_DG_DCDC_PD_EN_Msk = 0x800000 + // Bit DG_DCDC_PD_EN. + RTC_CNTL_DIG_PWC_DG_DCDC_PD_EN = 0x800000 + // Position of ROM0_PD_EN field. + RTC_CNTL_DIG_PWC_ROM0_PD_EN_Pos = 0x18 + // Bit mask of ROM0_PD_EN field. + RTC_CNTL_DIG_PWC_ROM0_PD_EN_Msk = 0x1000000 + // Bit ROM0_PD_EN. + RTC_CNTL_DIG_PWC_ROM0_PD_EN = 0x1000000 + // Position of INTER_RAM0_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM0_PD_EN_Pos = 0x19 + // Bit mask of INTER_RAM0_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM0_PD_EN_Msk = 0x2000000 + // Bit INTER_RAM0_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM0_PD_EN = 0x2000000 + // Position of INTER_RAM1_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM1_PD_EN_Pos = 0x1a + // Bit mask of INTER_RAM1_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM1_PD_EN_Msk = 0x4000000 + // Bit INTER_RAM1_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM1_PD_EN = 0x4000000 + // Position of INTER_RAM2_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM2_PD_EN_Pos = 0x1b + // Bit mask of INTER_RAM2_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM2_PD_EN_Msk = 0x8000000 + // Bit INTER_RAM2_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM2_PD_EN = 0x8000000 + // Position of INTER_RAM3_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM3_PD_EN_Pos = 0x1c + // Bit mask of INTER_RAM3_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM3_PD_EN_Msk = 0x10000000 + // Bit INTER_RAM3_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM3_PD_EN = 0x10000000 + // Position of INTER_RAM4_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM4_PD_EN_Pos = 0x1d + // Bit mask of INTER_RAM4_PD_EN field. + RTC_CNTL_DIG_PWC_INTER_RAM4_PD_EN_Msk = 0x20000000 + // Bit INTER_RAM4_PD_EN. + RTC_CNTL_DIG_PWC_INTER_RAM4_PD_EN = 0x20000000 + // Position of WIFI_PD_EN field. + RTC_CNTL_DIG_PWC_WIFI_PD_EN_Pos = 0x1e + // Bit mask of WIFI_PD_EN field. + RTC_CNTL_DIG_PWC_WIFI_PD_EN_Msk = 0x40000000 + // Bit WIFI_PD_EN. + RTC_CNTL_DIG_PWC_WIFI_PD_EN = 0x40000000 + // Position of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Pos = 0x1f + // Bit mask of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Msk = 0x80000000 + // Bit DG_WRAP_PD_EN. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN = 0x80000000 + + // DIG_ISO: Digital system ISO configuration register + // Position of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Pos = 0x7 + // Bit mask of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Msk = 0x80 + // Bit FORCE_OFF. + RTC_CNTL_DIG_ISO_FORCE_OFF = 0x80 + // Position of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Pos = 0x8 + // Bit mask of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Msk = 0x100 + // Bit FORCE_ON. + RTC_CNTL_DIG_ISO_FORCE_ON = 0x100 + // Position of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Pos = 0x9 + // Bit mask of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Msk = 0x200 + // Bit DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD = 0x200 + // Position of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Pos = 0xa + // Bit mask of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Msk = 0x400 + // Bit CLR_DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD = 0x400 + // Position of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Pos = 0xb + // Bit mask of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Msk = 0x800 + // Bit DG_PAD_AUTOHOLD_EN. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN = 0x800 + // Position of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Pos = 0xc + // Bit mask of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Msk = 0x1000 + // Bit DG_PAD_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO = 0x1000 + // Position of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Pos = 0xd + // Bit mask of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Msk = 0x2000 + // Bit DG_PAD_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO = 0x2000 + // Position of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Pos = 0xe + // Bit mask of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Msk = 0x4000 + // Bit DG_PAD_FORCE_UNHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD = 0x4000 + // Position of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Pos = 0xf + // Bit mask of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Msk = 0x8000 + // Bit DG_PAD_FORCE_HOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD = 0x8000 + // Position of ROM0_FORCE_ISO field. + RTC_CNTL_DIG_ISO_ROM0_FORCE_ISO_Pos = 0x10 + // Bit mask of ROM0_FORCE_ISO field. + RTC_CNTL_DIG_ISO_ROM0_FORCE_ISO_Msk = 0x10000 + // Bit ROM0_FORCE_ISO. + RTC_CNTL_DIG_ISO_ROM0_FORCE_ISO = 0x10000 + // Position of ROM0_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_ROM0_FORCE_NOISO_Pos = 0x11 + // Bit mask of ROM0_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_ROM0_FORCE_NOISO_Msk = 0x20000 + // Bit ROM0_FORCE_NOISO. + RTC_CNTL_DIG_ISO_ROM0_FORCE_NOISO = 0x20000 + // Position of INTER_RAM0_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_ISO_Pos = 0x12 + // Bit mask of INTER_RAM0_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_ISO_Msk = 0x40000 + // Bit INTER_RAM0_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_ISO = 0x40000 + // Position of INTER_RAM0_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_NOISO_Pos = 0x13 + // Bit mask of INTER_RAM0_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_NOISO_Msk = 0x80000 + // Bit INTER_RAM0_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM0_FORCE_NOISO = 0x80000 + // Position of INTER_RAM1_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_ISO_Pos = 0x14 + // Bit mask of INTER_RAM1_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_ISO_Msk = 0x100000 + // Bit INTER_RAM1_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_ISO = 0x100000 + // Position of INTER_RAM1_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_NOISO_Pos = 0x15 + // Bit mask of INTER_RAM1_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_NOISO_Msk = 0x200000 + // Bit INTER_RAM1_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM1_FORCE_NOISO = 0x200000 + // Position of INTER_RAM2_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_ISO_Pos = 0x16 + // Bit mask of INTER_RAM2_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_ISO_Msk = 0x400000 + // Bit INTER_RAM2_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_ISO = 0x400000 + // Position of INTER_RAM2_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_NOISO_Pos = 0x17 + // Bit mask of INTER_RAM2_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_NOISO_Msk = 0x800000 + // Bit INTER_RAM2_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM2_FORCE_NOISO = 0x800000 + // Position of INTER_RAM3_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_ISO_Pos = 0x18 + // Bit mask of INTER_RAM3_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_ISO_Msk = 0x1000000 + // Bit INTER_RAM3_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_ISO = 0x1000000 + // Position of INTER_RAM3_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_NOISO_Pos = 0x19 + // Bit mask of INTER_RAM3_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_NOISO_Msk = 0x2000000 + // Bit INTER_RAM3_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM3_FORCE_NOISO = 0x2000000 + // Position of INTER_RAM4_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_ISO_Pos = 0x1a + // Bit mask of INTER_RAM4_FORCE_ISO field. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_ISO_Msk = 0x4000000 + // Bit INTER_RAM4_FORCE_ISO. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_ISO = 0x4000000 + // Position of INTER_RAM4_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_NOISO_Pos = 0x1b + // Bit mask of INTER_RAM4_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_NOISO_Msk = 0x8000000 + // Bit INTER_RAM4_FORCE_NOISO. + RTC_CNTL_DIG_ISO_INTER_RAM4_FORCE_NOISO = 0x8000000 + // Position of WIFI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO_Pos = 0x1c + // Bit mask of WIFI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO_Msk = 0x10000000 + // Bit WIFI_FORCE_ISO. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO = 0x10000000 + // Position of WIFI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO_Pos = 0x1d + // Bit mask of WIFI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO_Msk = 0x20000000 + // Bit WIFI_FORCE_NOISO. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO = 0x20000000 + // Position of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO = 0x40000000 + // Position of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Pos = 0x1f + // Bit mask of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Msk = 0x80000000 + // Bit DG_WRAP_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO = 0x80000000 + + // WDTCONFIG0: RTC watchdog configuration register + // Position of WDT_CHIP_RESET_WIDTH field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Pos = 0x0 + // Bit mask of WDT_CHIP_RESET_WIDTH field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Msk = 0xff + // Position of WDT_CHIP_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN_Pos = 0x8 + // Bit mask of WDT_CHIP_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN_Msk = 0x100 + // Bit WDT_CHIP_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN = 0x100 + // Position of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Pos = 0x9 + // Bit mask of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Msk = 0x200 + // Bit WDT_PAUSE_IN_SLP. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP = 0x200 + // Position of WDT_APPCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xa + // Bit mask of WDT_APPCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x400 + // Bit WDT_APPCPU_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x400 + // Position of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xb + // Bit mask of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x800 + // Bit WDT_PROCPU_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x800 + // Position of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xc + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x1000 + // Bit WDT_FLASHBOOT_MOD_EN. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x1000 + // Position of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xd + // Bit mask of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0xe000 + // Position of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x10 + // Bit mask of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x70000 + // Position of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Pos = 0x13 + // Bit mask of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Msk = 0x380000 + // Position of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Pos = 0x16 + // Bit mask of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Msk = 0x1c00000 + // Position of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Pos = 0x19 + // Bit mask of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Msk = 0xe000000 + // Position of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Pos = 0x1c + // Bit mask of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Msk = 0x70000000 + // Position of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + RTC_CNTL_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: Configures the hold time of RTC watchdog at level 1 + // Position of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG2: Configures the hold time of RTC watchdog at level 2 + // Position of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: Configures the hold time of RTC watchdog at level 3 + // Position of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: Configures the hold time of RTC watchdog at level 4 + // Position of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: RTC watchdog SW feed configuration register + // Position of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Pos = 0x1f + // Bit mask of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Msk = 0x80000000 + // Bit WDT_FEED. + RTC_CNTL_WDTFEED_WDT_FEED = 0x80000000 + + // WDTWPROTECT: RTC watchdog write protection configuration register + // Position of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // SWD_CONF: Super watchdog configuration register + // Position of SWD_RESET_FLAG field. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG_Pos = 0x0 + // Bit mask of SWD_RESET_FLAG field. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG_Msk = 0x1 + // Bit SWD_RESET_FLAG. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG = 0x1 + // Position of SWD_FEED_INT field. + RTC_CNTL_SWD_CONF_SWD_FEED_INT_Pos = 0x1 + // Bit mask of SWD_FEED_INT field. + RTC_CNTL_SWD_CONF_SWD_FEED_INT_Msk = 0x2 + // Bit SWD_FEED_INT. + RTC_CNTL_SWD_CONF_SWD_FEED_INT = 0x2 + // Position of SWD_SIGNAL_WIDTH field. + RTC_CNTL_SWD_CONF_SWD_SIGNAL_WIDTH_Pos = 0x12 + // Bit mask of SWD_SIGNAL_WIDTH field. + RTC_CNTL_SWD_CONF_SWD_SIGNAL_WIDTH_Msk = 0xffc0000 + // Position of SWD_RST_FLAG_CLR field. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR_Pos = 0x1c + // Bit mask of SWD_RST_FLAG_CLR field. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR_Msk = 0x10000000 + // Bit SWD_RST_FLAG_CLR. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR = 0x10000000 + // Position of SWD_FEED field. + RTC_CNTL_SWD_CONF_SWD_FEED_Pos = 0x1d + // Bit mask of SWD_FEED field. + RTC_CNTL_SWD_CONF_SWD_FEED_Msk = 0x20000000 + // Bit SWD_FEED. + RTC_CNTL_SWD_CONF_SWD_FEED = 0x20000000 + // Position of SWD_DISABLE field. + RTC_CNTL_SWD_CONF_SWD_DISABLE_Pos = 0x1e + // Bit mask of SWD_DISABLE field. + RTC_CNTL_SWD_CONF_SWD_DISABLE_Msk = 0x40000000 + // Bit SWD_DISABLE. + RTC_CNTL_SWD_CONF_SWD_DISABLE = 0x40000000 + // Position of SWD_AUTO_FEED_EN field. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN_Pos = 0x1f + // Bit mask of SWD_AUTO_FEED_EN field. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN_Msk = 0x80000000 + // Bit SWD_AUTO_FEED_EN. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN = 0x80000000 + + // SWD_WPROTECT: Super watchdog write protection configuration register + // Position of SWD_WKEY field. + RTC_CNTL_SWD_WPROTECT_SWD_WKEY_Pos = 0x0 + // Bit mask of SWD_WKEY field. + RTC_CNTL_SWD_WPROTECT_SWD_WKEY_Msk = 0xffffffff + + // SW_CPU_STALL: CPU stall configuration register + // Position of SW_STALL_APPCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_APPCPU_C1_Pos = 0x14 + // Bit mask of SW_STALL_APPCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_APPCPU_C1_Msk = 0x3f00000 + // Position of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Pos = 0x1a + // Bit mask of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Msk = 0xfc000000 + + // STORE4: Reservation register 4 + // Position of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Pos = 0x0 + // Bit mask of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Msk = 0xffffffff + + // STORE5: Reservation register 5 + // Position of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Pos = 0x0 + // Bit mask of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Msk = 0xffffffff + + // STORE6: Reservation register 6 + // Position of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Pos = 0x0 + // Bit mask of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Msk = 0xffffffff + + // STORE7: Reservation register 7 + // Position of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Pos = 0x0 + // Bit mask of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Msk = 0xffffffff + + // LOW_POWER_ST: RTC main state machine status register + // Position of XPD_ROM0 field. + RTC_CNTL_LOW_POWER_ST_XPD_ROM0_Pos = 0x0 + // Bit mask of XPD_ROM0 field. + RTC_CNTL_LOW_POWER_ST_XPD_ROM0_Msk = 0x1 + // Bit XPD_ROM0. + RTC_CNTL_LOW_POWER_ST_XPD_ROM0 = 0x1 + // Position of XPD_DIG_DCDC field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_DCDC_Pos = 0x2 + // Bit mask of XPD_DIG_DCDC field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_DCDC_Msk = 0x4 + // Bit XPD_DIG_DCDC. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_DCDC = 0x4 + // Position of PERI_ISO field. + RTC_CNTL_LOW_POWER_ST_PERI_ISO_Pos = 0x3 + // Bit mask of PERI_ISO field. + RTC_CNTL_LOW_POWER_ST_PERI_ISO_Msk = 0x8 + // Bit PERI_ISO. + RTC_CNTL_LOW_POWER_ST_PERI_ISO = 0x8 + // Position of XPD_RTC_PERI field. + RTC_CNTL_LOW_POWER_ST_XPD_RTC_PERI_Pos = 0x4 + // Bit mask of XPD_RTC_PERI field. + RTC_CNTL_LOW_POWER_ST_XPD_RTC_PERI_Msk = 0x10 + // Bit XPD_RTC_PERI. + RTC_CNTL_LOW_POWER_ST_XPD_RTC_PERI = 0x10 + // Position of WIFI_ISO field. + RTC_CNTL_LOW_POWER_ST_WIFI_ISO_Pos = 0x5 + // Bit mask of WIFI_ISO field. + RTC_CNTL_LOW_POWER_ST_WIFI_ISO_Msk = 0x20 + // Bit WIFI_ISO. + RTC_CNTL_LOW_POWER_ST_WIFI_ISO = 0x20 + // Position of XPD_WIFI field. + RTC_CNTL_LOW_POWER_ST_XPD_WIFI_Pos = 0x6 + // Bit mask of XPD_WIFI field. + RTC_CNTL_LOW_POWER_ST_XPD_WIFI_Msk = 0x40 + // Bit XPD_WIFI. + RTC_CNTL_LOW_POWER_ST_XPD_WIFI = 0x40 + // Position of DIG_ISO field. + RTC_CNTL_LOW_POWER_ST_DIG_ISO_Pos = 0x7 + // Bit mask of DIG_ISO field. + RTC_CNTL_LOW_POWER_ST_DIG_ISO_Msk = 0x80 + // Bit DIG_ISO. + RTC_CNTL_LOW_POWER_ST_DIG_ISO = 0x80 + // Position of XPD_DIG field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_Pos = 0x8 + // Bit mask of XPD_DIG field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_Msk = 0x100 + // Bit XPD_DIG. + RTC_CNTL_LOW_POWER_ST_XPD_DIG = 0x100 + // Position of TOUCH_STATE_START field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START_Pos = 0x9 + // Bit mask of TOUCH_STATE_START field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START_Msk = 0x200 + // Bit TOUCH_STATE_START. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START = 0x200 + // Position of TOUCH_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH_Pos = 0xa + // Bit mask of TOUCH_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH_Msk = 0x400 + // Bit TOUCH_STATE_SWITCH. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH = 0x400 + // Position of TOUCH_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP_Pos = 0xb + // Bit mask of TOUCH_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP_Msk = 0x800 + // Bit TOUCH_STATE_SLP. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP = 0x800 + // Position of TOUCH_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE_Pos = 0xc + // Bit mask of TOUCH_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE_Msk = 0x1000 + // Bit TOUCH_STATE_DONE. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE = 0x1000 + // Position of COCPU_STATE_START field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START_Pos = 0xd + // Bit mask of COCPU_STATE_START field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START_Msk = 0x2000 + // Bit COCPU_STATE_START. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START = 0x2000 + // Position of COCPU_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH_Pos = 0xe + // Bit mask of COCPU_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH_Msk = 0x4000 + // Bit COCPU_STATE_SWITCH. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH = 0x4000 + // Position of COCPU_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP_Pos = 0xf + // Bit mask of COCPU_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP_Msk = 0x8000 + // Bit COCPU_STATE_SLP. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP = 0x8000 + // Position of COCPU_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE_Pos = 0x10 + // Bit mask of COCPU_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE_Msk = 0x10000 + // Bit COCPU_STATE_DONE. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE = 0x10000 + // Position of MAIN_STATE_XTAL_ISO field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO_Pos = 0x11 + // Bit mask of MAIN_STATE_XTAL_ISO field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO_Msk = 0x20000 + // Bit MAIN_STATE_XTAL_ISO. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO = 0x20000 + // Position of MAIN_STATE_PLL_ON field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON_Pos = 0x12 + // Bit mask of MAIN_STATE_PLL_ON field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON_Msk = 0x40000 + // Bit MAIN_STATE_PLL_ON. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON = 0x40000 + // Position of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Pos = 0x13 + // Bit mask of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Msk = 0x80000 + // Bit RDY_FOR_WAKEUP. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP = 0x80000 + // Position of MAIN_STATE_WAIT_END field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END_Pos = 0x14 + // Bit mask of MAIN_STATE_WAIT_END field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END_Msk = 0x100000 + // Bit MAIN_STATE_WAIT_END. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END = 0x100000 + // Position of IN_WAKEUP_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE_Pos = 0x15 + // Bit mask of IN_WAKEUP_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE_Msk = 0x200000 + // Bit IN_WAKEUP_STATE. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE = 0x200000 + // Position of IN_LOW_POWER_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE_Pos = 0x16 + // Bit mask of IN_LOW_POWER_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE_Msk = 0x400000 + // Bit IN_LOW_POWER_STATE. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE = 0x400000 + // Position of MAIN_STATE_IN_WAIT_8M field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M_Pos = 0x17 + // Bit mask of MAIN_STATE_IN_WAIT_8M field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M_Msk = 0x800000 + // Bit MAIN_STATE_IN_WAIT_8M. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M = 0x800000 + // Position of MAIN_STATE_IN_WAIT_PLL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL_Pos = 0x18 + // Bit mask of MAIN_STATE_IN_WAIT_PLL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL_Msk = 0x1000000 + // Bit MAIN_STATE_IN_WAIT_PLL. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL = 0x1000000 + // Position of MAIN_STATE_IN_WAIT_XTL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL_Pos = 0x19 + // Bit mask of MAIN_STATE_IN_WAIT_XTL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL_Msk = 0x2000000 + // Bit MAIN_STATE_IN_WAIT_XTL. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL = 0x2000000 + // Position of MAIN_STATE_IN_SLP field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP_Pos = 0x1a + // Bit mask of MAIN_STATE_IN_SLP field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP_Msk = 0x4000000 + // Bit MAIN_STATE_IN_SLP. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP = 0x4000000 + // Position of MAIN_STATE_IN_IDLE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE_Pos = 0x1b + // Bit mask of MAIN_STATE_IN_IDLE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE_Msk = 0x8000000 + // Bit MAIN_STATE_IN_IDLE. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE = 0x8000000 + // Position of MAIN_STATE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_Pos = 0x1c + // Bit mask of MAIN_STATE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_Msk = 0xf0000000 + + // DIAG0: debug register + // Position of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG0_LOW_POWER_DIAG1_Pos = 0x0 + // Bit mask of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG0_LOW_POWER_DIAG1_Msk = 0xffffffff + + // PAD_HOLD: Configures the hold options for RTC GPIOs + // Position of TOUCH_PAD0_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD0_HOLD_Pos = 0x0 + // Bit mask of TOUCH_PAD0_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD0_HOLD_Msk = 0x1 + // Bit TOUCH_PAD0_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD0_HOLD = 0x1 + // Position of TOUCH_PAD1_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD1_HOLD_Pos = 0x1 + // Bit mask of TOUCH_PAD1_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD1_HOLD_Msk = 0x2 + // Bit TOUCH_PAD1_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD1_HOLD = 0x2 + // Position of TOUCH_PAD2_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD2_HOLD_Pos = 0x2 + // Bit mask of TOUCH_PAD2_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD2_HOLD_Msk = 0x4 + // Bit TOUCH_PAD2_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD2_HOLD = 0x4 + // Position of TOUCH_PAD3_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD3_HOLD_Pos = 0x3 + // Bit mask of TOUCH_PAD3_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD3_HOLD_Msk = 0x8 + // Bit TOUCH_PAD3_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD3_HOLD = 0x8 + // Position of TOUCH_PAD4_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD4_HOLD_Pos = 0x4 + // Bit mask of TOUCH_PAD4_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD4_HOLD_Msk = 0x10 + // Bit TOUCH_PAD4_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD4_HOLD = 0x10 + // Position of TOUCH_PAD5_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD5_HOLD_Pos = 0x5 + // Bit mask of TOUCH_PAD5_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD5_HOLD_Msk = 0x20 + // Bit TOUCH_PAD5_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD5_HOLD = 0x20 + // Position of TOUCH_PAD6_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD6_HOLD_Pos = 0x6 + // Bit mask of TOUCH_PAD6_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD6_HOLD_Msk = 0x40 + // Bit TOUCH_PAD6_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD6_HOLD = 0x40 + // Position of TOUCH_PAD7_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD7_HOLD_Pos = 0x7 + // Bit mask of TOUCH_PAD7_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD7_HOLD_Msk = 0x80 + // Bit TOUCH_PAD7_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD7_HOLD = 0x80 + // Position of TOUCH_PAD8_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD8_HOLD_Pos = 0x8 + // Bit mask of TOUCH_PAD8_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD8_HOLD_Msk = 0x100 + // Bit TOUCH_PAD8_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD8_HOLD = 0x100 + // Position of TOUCH_PAD9_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD9_HOLD_Pos = 0x9 + // Bit mask of TOUCH_PAD9_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD9_HOLD_Msk = 0x200 + // Bit TOUCH_PAD9_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD9_HOLD = 0x200 + // Position of TOUCH_PAD10_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD10_HOLD_Pos = 0xa + // Bit mask of TOUCH_PAD10_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD10_HOLD_Msk = 0x400 + // Bit TOUCH_PAD10_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD10_HOLD = 0x400 + // Position of TOUCH_PAD11_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD11_HOLD_Pos = 0xb + // Bit mask of TOUCH_PAD11_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD11_HOLD_Msk = 0x800 + // Bit TOUCH_PAD11_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD11_HOLD = 0x800 + // Position of TOUCH_PAD12_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD12_HOLD_Pos = 0xc + // Bit mask of TOUCH_PAD12_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD12_HOLD_Msk = 0x1000 + // Bit TOUCH_PAD12_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD12_HOLD = 0x1000 + // Position of TOUCH_PAD13_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD13_HOLD_Pos = 0xd + // Bit mask of TOUCH_PAD13_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD13_HOLD_Msk = 0x2000 + // Bit TOUCH_PAD13_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD13_HOLD = 0x2000 + // Position of TOUCH_PAD14_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD14_HOLD_Pos = 0xe + // Bit mask of TOUCH_PAD14_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD14_HOLD_Msk = 0x4000 + // Bit TOUCH_PAD14_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD14_HOLD = 0x4000 + // Position of X32P_HOLD field. + RTC_CNTL_PAD_HOLD_X32P_HOLD_Pos = 0xf + // Bit mask of X32P_HOLD field. + RTC_CNTL_PAD_HOLD_X32P_HOLD_Msk = 0x8000 + // Bit X32P_HOLD. + RTC_CNTL_PAD_HOLD_X32P_HOLD = 0x8000 + // Position of X32N_HOLD field. + RTC_CNTL_PAD_HOLD_X32N_HOLD_Pos = 0x10 + // Bit mask of X32N_HOLD field. + RTC_CNTL_PAD_HOLD_X32N_HOLD_Msk = 0x10000 + // Bit X32N_HOLD. + RTC_CNTL_PAD_HOLD_X32N_HOLD = 0x10000 + // Position of PDAC1_HOLD field. + RTC_CNTL_PAD_HOLD_PDAC1_HOLD_Pos = 0x11 + // Bit mask of PDAC1_HOLD field. + RTC_CNTL_PAD_HOLD_PDAC1_HOLD_Msk = 0x20000 + // Bit PDAC1_HOLD. + RTC_CNTL_PAD_HOLD_PDAC1_HOLD = 0x20000 + // Position of PDAC2_HOLD field. + RTC_CNTL_PAD_HOLD_PDAC2_HOLD_Pos = 0x12 + // Bit mask of PDAC2_HOLD field. + RTC_CNTL_PAD_HOLD_PDAC2_HOLD_Msk = 0x40000 + // Bit PDAC2_HOLD. + RTC_CNTL_PAD_HOLD_PDAC2_HOLD = 0x40000 + // Position of PAD19_HOLD field. + RTC_CNTL_PAD_HOLD_PAD19_HOLD_Pos = 0x13 + // Bit mask of PAD19_HOLD field. + RTC_CNTL_PAD_HOLD_PAD19_HOLD_Msk = 0x80000 + // Bit PAD19_HOLD. + RTC_CNTL_PAD_HOLD_PAD19_HOLD = 0x80000 + // Position of PAD20_HOLD field. + RTC_CNTL_PAD_HOLD_PAD20_HOLD_Pos = 0x14 + // Bit mask of PAD20_HOLD field. + RTC_CNTL_PAD_HOLD_PAD20_HOLD_Msk = 0x100000 + // Bit PAD20_HOLD. + RTC_CNTL_PAD_HOLD_PAD20_HOLD = 0x100000 + // Position of PAD21_HOLD field. + RTC_CNTL_PAD_HOLD_PAD21_HOLD_Pos = 0x15 + // Bit mask of PAD21_HOLD field. + RTC_CNTL_PAD_HOLD_PAD21_HOLD_Msk = 0x200000 + // Bit PAD21_HOLD. + RTC_CNTL_PAD_HOLD_PAD21_HOLD = 0x200000 + + // DIG_PAD_HOLD: Configures the hold option for digital GPIOs + // Position of DIG_PAD_HOLD field. + RTC_CNTL_DIG_PAD_HOLD_DIG_PAD_HOLD_Pos = 0x0 + // Bit mask of DIG_PAD_HOLD field. + RTC_CNTL_DIG_PAD_HOLD_DIG_PAD_HOLD_Msk = 0xffffffff + + // EXT_WAKEUP1: EXT1 wakeup configuration register + // Position of SEL field. + RTC_CNTL_EXT_WAKEUP1_SEL_Pos = 0x0 + // Bit mask of SEL field. + RTC_CNTL_EXT_WAKEUP1_SEL_Msk = 0x3fffff + // Position of STATUS_CLR field. + RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_Pos = 0x16 + // Bit mask of STATUS_CLR field. + RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_Msk = 0x400000 + // Bit STATUS_CLR. + RTC_CNTL_EXT_WAKEUP1_STATUS_CLR = 0x400000 + + // EXT_WAKEUP1_STATUS: EXT1 wakeup source register + // Position of EXT_WAKEUP1_STATUS field. + RTC_CNTL_EXT_WAKEUP1_STATUS_EXT_WAKEUP1_STATUS_Pos = 0x0 + // Bit mask of EXT_WAKEUP1_STATUS field. + RTC_CNTL_EXT_WAKEUP1_STATUS_EXT_WAKEUP1_STATUS_Msk = 0x3fffff + + // BROWN_OUT: Brownout configuration register + // Position of BROWN_OUT2_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT2_ENA_Pos = 0x0 + // Bit mask of BROWN_OUT2_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT2_ENA_Msk = 0x1 + // Bit BROWN_OUT2_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT2_ENA = 0x1 + // Position of INT_WAIT field. + RTC_CNTL_BROWN_OUT_INT_WAIT_Pos = 0x4 + // Bit mask of INT_WAIT field. + RTC_CNTL_BROWN_OUT_INT_WAIT_Msk = 0x3ff0 + // Position of CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_Pos = 0xe + // Bit mask of CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_Msk = 0x4000 + // Bit CLOSE_FLASH_ENA. + RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA = 0x4000 + // Position of PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_PD_RF_ENA_Pos = 0xf + // Bit mask of PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_PD_RF_ENA_Msk = 0x8000 + // Bit PD_RF_ENA. + RTC_CNTL_BROWN_OUT_PD_RF_ENA = 0x8000 + // Position of RST_WAIT field. + RTC_CNTL_BROWN_OUT_RST_WAIT_Pos = 0x10 + // Bit mask of RST_WAIT field. + RTC_CNTL_BROWN_OUT_RST_WAIT_Msk = 0x3ff0000 + // Position of RST_ENA field. + RTC_CNTL_BROWN_OUT_RST_ENA_Pos = 0x1a + // Bit mask of RST_ENA field. + RTC_CNTL_BROWN_OUT_RST_ENA_Msk = 0x4000000 + // Bit RST_ENA. + RTC_CNTL_BROWN_OUT_RST_ENA = 0x4000000 + // Position of RST_SEL field. + RTC_CNTL_BROWN_OUT_RST_SEL_Pos = 0x1b + // Bit mask of RST_SEL field. + RTC_CNTL_BROWN_OUT_RST_SEL_Msk = 0x8000000 + // Bit RST_SEL. + RTC_CNTL_BROWN_OUT_RST_SEL = 0x8000000 + // Position of CNT_CLR field. + RTC_CNTL_BROWN_OUT_CNT_CLR_Pos = 0x1d + // Bit mask of CNT_CLR field. + RTC_CNTL_BROWN_OUT_CNT_CLR_Msk = 0x20000000 + // Bit CNT_CLR. + RTC_CNTL_BROWN_OUT_CNT_CLR = 0x20000000 + // Position of ENA field. + RTC_CNTL_BROWN_OUT_ENA_Pos = 0x1e + // Bit mask of ENA field. + RTC_CNTL_BROWN_OUT_ENA_Msk = 0x40000000 + // Bit ENA. + RTC_CNTL_BROWN_OUT_ENA = 0x40000000 + // Position of DET field. + RTC_CNTL_BROWN_OUT_DET_Pos = 0x1f + // Bit mask of DET field. + RTC_CNTL_BROWN_OUT_DET_Msk = 0x80000000 + // Bit DET. + RTC_CNTL_BROWN_OUT_DET = 0x80000000 + + // TIME_LOW1: Stores the lower 32 bits of RTC timer 1 + // Position of TIMER_VALUE1_LOW field. + RTC_CNTL_TIME_LOW1_TIMER_VALUE1_LOW_Pos = 0x0 + // Bit mask of TIMER_VALUE1_LOW field. + RTC_CNTL_TIME_LOW1_TIMER_VALUE1_LOW_Msk = 0xffffffff + + // TIME_HIGH1: Stores the higher 16 bits of RTC timer 1 + // Position of TIMER_VALUE1_HIGH field. + RTC_CNTL_TIME_HIGH1_TIMER_VALUE1_HIGH_Pos = 0x0 + // Bit mask of TIMER_VALUE1_HIGH field. + RTC_CNTL_TIME_HIGH1_TIMER_VALUE1_HIGH_Msk = 0xffff + + // XTAL32K_CLK_FACTOR: Configures the divider factor for the backup clock of 32 kHz crystal oscillator + // Position of XTAL32K_CLK_FACTOR field. + RTC_CNTL_XTAL32K_CLK_FACTOR_XTAL32K_CLK_FACTOR_Pos = 0x0 + // Bit mask of XTAL32K_CLK_FACTOR field. + RTC_CNTL_XTAL32K_CLK_FACTOR_XTAL32K_CLK_FACTOR_Msk = 0xffffffff + + // XTAL32K_CONF: 32 kHz crystal oscillator configuration register + // Position of XTAL32K_RETURN_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RETURN_WAIT_Pos = 0x0 + // Bit mask of XTAL32K_RETURN_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RETURN_WAIT_Msk = 0xf + // Position of XTAL32K_RESTART_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RESTART_WAIT_Pos = 0x4 + // Bit mask of XTAL32K_RESTART_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RESTART_WAIT_Msk = 0xffff0 + // Position of XTAL32K_WDT_TIMEOUT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_WDT_TIMEOUT_Pos = 0x14 + // Bit mask of XTAL32K_WDT_TIMEOUT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_WDT_TIMEOUT_Msk = 0xff00000 + // Position of XTAL32K_STABLE_THRES field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_STABLE_THRES_Pos = 0x1c + // Bit mask of XTAL32K_STABLE_THRES field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_STABLE_THRES_Msk = 0xf0000000 + + // ULP_CP_TIMER: Configure coprocessor timer + // Position of ULP_CP_PC_INIT field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_PC_INIT_Pos = 0x0 + // Bit mask of ULP_CP_PC_INIT field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_PC_INIT_Msk = 0x7ff + // Position of ULP_CP_GPIO_WAKEUP_ENA field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA_Pos = 0x1d + // Bit mask of ULP_CP_GPIO_WAKEUP_ENA field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA_Msk = 0x20000000 + // Bit ULP_CP_GPIO_WAKEUP_ENA. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA = 0x20000000 + // Position of ULP_CP_GPIO_WAKEUP_CLR field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR_Pos = 0x1e + // Bit mask of ULP_CP_GPIO_WAKEUP_CLR field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR_Msk = 0x40000000 + // Bit ULP_CP_GPIO_WAKEUP_CLR. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR = 0x40000000 + // Position of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN_Pos = 0x1f + // Bit mask of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN_Msk = 0x80000000 + // Bit ULP_CP_SLP_TIMER_EN. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN = 0x80000000 + + // ULP_CP_CTRL: ULP-FSM configuration register + // Position of ULP_CP_MEM_ADDR_INIT field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT_Pos = 0x0 + // Bit mask of ULP_CP_MEM_ADDR_INIT field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT_Msk = 0x7ff + // Position of ULP_CP_MEM_ADDR_SIZE field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE_Pos = 0xb + // Bit mask of ULP_CP_MEM_ADDR_SIZE field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE_Msk = 0x3ff800 + // Position of ULP_CP_MEM_OFFSET_CLR field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR_Pos = 0x16 + // Bit mask of ULP_CP_MEM_OFFSET_CLR field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR_Msk = 0x400000 + // Bit ULP_CP_MEM_OFFSET_CLR. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR = 0x400000 + // Position of ULP_CP_CLK_FO field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_CLK_FO_Pos = 0x1c + // Bit mask of ULP_CP_CLK_FO field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_CLK_FO_Msk = 0x10000000 + // Bit ULP_CP_CLK_FO. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_CLK_FO = 0x10000000 + // Position of ULP_CP_RESET field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_RESET_Pos = 0x1d + // Bit mask of ULP_CP_RESET field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_RESET_Msk = 0x20000000 + // Bit ULP_CP_RESET. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_RESET = 0x20000000 + // Position of ULP_CP_FORCE_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP_Pos = 0x1e + // Bit mask of ULP_CP_FORCE_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP_Msk = 0x40000000 + // Bit ULP_CP_FORCE_START_TOP. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP = 0x40000000 + // Position of ULP_CP_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_START_TOP_Pos = 0x1f + // Bit mask of ULP_CP_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_START_TOP_Msk = 0x80000000 + // Bit ULP_CP_START_TOP. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_START_TOP = 0x80000000 + + // COCPU_CTRL: ULP-RISCV configuration register + // Position of COCPU_CLK_FO field. + RTC_CNTL_COCPU_CTRL_COCPU_CLK_FO_Pos = 0x0 + // Bit mask of COCPU_CLK_FO field. + RTC_CNTL_COCPU_CTRL_COCPU_CLK_FO_Msk = 0x1 + // Bit COCPU_CLK_FO. + RTC_CNTL_COCPU_CTRL_COCPU_CLK_FO = 0x1 + // Position of COCPU_START_2_RESET_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_RESET_DIS_Pos = 0x1 + // Bit mask of COCPU_START_2_RESET_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_RESET_DIS_Msk = 0x7e + // Position of COCPU_START_2_INTR_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_INTR_EN_Pos = 0x7 + // Bit mask of COCPU_START_2_INTR_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_INTR_EN_Msk = 0x1f80 + // Position of COCPU_SHUT field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_Pos = 0xd + // Bit mask of COCPU_SHUT field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_Msk = 0x2000 + // Bit COCPU_SHUT. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT = 0x2000 + // Position of COCPU_SHUT_2_CLK_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS_Pos = 0xe + // Bit mask of COCPU_SHUT_2_CLK_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS_Msk = 0x3fc000 + // Position of COCPU_SHUT_RESET_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_RESET_EN_Pos = 0x16 + // Bit mask of COCPU_SHUT_RESET_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_RESET_EN_Msk = 0x400000 + // Bit COCPU_SHUT_RESET_EN. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_RESET_EN = 0x400000 + // Position of COCPU_SEL field. + RTC_CNTL_COCPU_CTRL_COCPU_SEL_Pos = 0x17 + // Bit mask of COCPU_SEL field. + RTC_CNTL_COCPU_CTRL_COCPU_SEL_Msk = 0x800000 + // Bit COCPU_SEL. + RTC_CNTL_COCPU_CTRL_COCPU_SEL = 0x800000 + // Position of COCPU_DONE_FORCE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_FORCE_Pos = 0x18 + // Bit mask of COCPU_DONE_FORCE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_FORCE_Msk = 0x1000000 + // Bit COCPU_DONE_FORCE. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_FORCE = 0x1000000 + // Position of COCPU_DONE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_Pos = 0x19 + // Bit mask of COCPU_DONE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_Msk = 0x2000000 + // Bit COCPU_DONE. + RTC_CNTL_COCPU_CTRL_COCPU_DONE = 0x2000000 + // Position of COCPU_SW_INT_TRIGGER field. + RTC_CNTL_COCPU_CTRL_COCPU_SW_INT_TRIGGER_Pos = 0x1a + // Bit mask of COCPU_SW_INT_TRIGGER field. + RTC_CNTL_COCPU_CTRL_COCPU_SW_INT_TRIGGER_Msk = 0x4000000 + // Bit COCPU_SW_INT_TRIGGER. + RTC_CNTL_COCPU_CTRL_COCPU_SW_INT_TRIGGER = 0x4000000 + + // TOUCH_CTRL1: Touch control register + // Position of TOUCH_SLEEP_CYCLES field. + RTC_CNTL_TOUCH_CTRL1_TOUCH_SLEEP_CYCLES_Pos = 0x0 + // Bit mask of TOUCH_SLEEP_CYCLES field. + RTC_CNTL_TOUCH_CTRL1_TOUCH_SLEEP_CYCLES_Msk = 0xffff + // Position of TOUCH_MEAS_NUM field. + RTC_CNTL_TOUCH_CTRL1_TOUCH_MEAS_NUM_Pos = 0x10 + // Bit mask of TOUCH_MEAS_NUM field. + RTC_CNTL_TOUCH_CTRL1_TOUCH_MEAS_NUM_Msk = 0xffff0000 + + // TOUCH_CTRL2: Touch control register + // Position of TOUCH_DRANGE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DRANGE_Pos = 0x2 + // Bit mask of TOUCH_DRANGE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DRANGE_Msk = 0xc + // Position of TOUCH_DREFL field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DREFL_Pos = 0x4 + // Bit mask of TOUCH_DREFL field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DREFL_Msk = 0x30 + // Position of TOUCH_DREFH field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DREFH_Pos = 0x6 + // Bit mask of TOUCH_DREFH field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DREFH_Msk = 0xc0 + // Position of TOUCH_XPD_BIAS field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_BIAS_Pos = 0x8 + // Bit mask of TOUCH_XPD_BIAS field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_BIAS_Msk = 0x100 + // Bit TOUCH_XPD_BIAS. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_BIAS = 0x100 + // Position of TOUCH_REFC field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_REFC_Pos = 0x9 + // Bit mask of TOUCH_REFC field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_REFC_Msk = 0xe00 + // Position of TOUCH_DBIAS field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DBIAS_Pos = 0xc + // Bit mask of TOUCH_DBIAS field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DBIAS_Msk = 0x1000 + // Bit TOUCH_DBIAS. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DBIAS = 0x1000 + // Position of TOUCH_SLP_TIMER_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_TIMER_EN_Pos = 0xd + // Bit mask of TOUCH_SLP_TIMER_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_TIMER_EN_Msk = 0x2000 + // Bit TOUCH_SLP_TIMER_EN. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_TIMER_EN = 0x2000 + // Position of TOUCH_START_FSM_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FSM_EN_Pos = 0xe + // Bit mask of TOUCH_START_FSM_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FSM_EN_Msk = 0x4000 + // Bit TOUCH_START_FSM_EN. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FSM_EN = 0x4000 + // Position of TOUCH_START_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_EN_Pos = 0xf + // Bit mask of TOUCH_START_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_EN_Msk = 0x8000 + // Bit TOUCH_START_EN. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_EN = 0x8000 + // Position of TOUCH_START_FORCE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FORCE_Pos = 0x10 + // Bit mask of TOUCH_START_FORCE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FORCE_Msk = 0x10000 + // Bit TOUCH_START_FORCE. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FORCE = 0x10000 + // Position of TOUCH_XPD_WAIT field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_WAIT_Pos = 0x11 + // Bit mask of TOUCH_XPD_WAIT field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_WAIT_Msk = 0x1fe0000 + // Position of TOUCH_SLP_CYC_DIV field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_CYC_DIV_Pos = 0x19 + // Bit mask of TOUCH_SLP_CYC_DIV field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_CYC_DIV_Msk = 0x6000000 + // Position of TOUCH_TIMER_FORCE_DONE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_TIMER_FORCE_DONE_Pos = 0x1b + // Bit mask of TOUCH_TIMER_FORCE_DONE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_TIMER_FORCE_DONE_Msk = 0x18000000 + // Position of TOUCH_RESET field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_RESET_Pos = 0x1d + // Bit mask of TOUCH_RESET field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_RESET_Msk = 0x20000000 + // Bit TOUCH_RESET. + RTC_CNTL_TOUCH_CTRL2_TOUCH_RESET = 0x20000000 + // Position of TOUCH_CLK_FO field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLK_FO_Pos = 0x1e + // Bit mask of TOUCH_CLK_FO field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLK_FO_Msk = 0x40000000 + // Bit TOUCH_CLK_FO. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLK_FO = 0x40000000 + // Position of TOUCH_CLKGATE_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLKGATE_EN_Pos = 0x1f + // Bit mask of TOUCH_CLKGATE_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLKGATE_EN_Msk = 0x80000000 + // Bit TOUCH_CLKGATE_EN. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLKGATE_EN = 0x80000000 + + // TOUCH_SCAN_CTRL: Configure touch scan settings + // Position of TOUCH_DENOISE_RES field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_RES_Pos = 0x0 + // Bit mask of TOUCH_DENOISE_RES field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_RES_Msk = 0x3 + // Position of TOUCH_DENOISE_EN field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_EN_Pos = 0x2 + // Bit mask of TOUCH_DENOISE_EN field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_EN_Msk = 0x4 + // Bit TOUCH_DENOISE_EN. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_EN = 0x4 + // Position of TOUCH_INACTIVE_CONNECTION field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_CONNECTION field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION_Msk = 0x100 + // Bit TOUCH_INACTIVE_CONNECTION. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION = 0x100 + // Position of TOUCH_SHIELD_PAD_EN field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN_Pos = 0x9 + // Bit mask of TOUCH_SHIELD_PAD_EN field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN_Msk = 0x200 + // Bit TOUCH_SHIELD_PAD_EN. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN = 0x200 + // Position of TOUCH_SCAN_PAD_MAP field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SCAN_PAD_MAP_Pos = 0xa + // Bit mask of TOUCH_SCAN_PAD_MAP field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SCAN_PAD_MAP_Msk = 0x1fffc00 + // Position of TOUCH_BUFDRV field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_BUFDRV_Pos = 0x19 + // Bit mask of TOUCH_BUFDRV field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_BUFDRV_Msk = 0xe000000 + // Position of TOUCH_OUT_RING field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_OUT_RING_Pos = 0x1c + // Bit mask of TOUCH_OUT_RING field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_OUT_RING_Msk = 0xf0000000 + + // TOUCH_SLP_THRES: Configure the settings of touch sleep pad + // Position of TOUCH_SLP_TH field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_TH_Pos = 0x0 + // Bit mask of TOUCH_SLP_TH field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_TH_Msk = 0x3fffff + // Position of TOUCH_SLP_APPROACH_EN field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN_Pos = 0x1a + // Bit mask of TOUCH_SLP_APPROACH_EN field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN_Msk = 0x4000000 + // Bit TOUCH_SLP_APPROACH_EN. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN = 0x4000000 + // Position of TOUCH_SLP_PAD field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_PAD_Pos = 0x1b + // Bit mask of TOUCH_SLP_PAD field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_PAD_Msk = 0xf8000000 + + // TOUCH_APPROACH: Configure touch approach settings + // Position of TOUCH_SLP_CHANNEL_CLR field. + RTC_CNTL_TOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR_Pos = 0x17 + // Bit mask of TOUCH_SLP_CHANNEL_CLR field. + RTC_CNTL_TOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR_Msk = 0x800000 + // Bit TOUCH_SLP_CHANNEL_CLR. + RTC_CNTL_TOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR = 0x800000 + // Position of MEAS_TIME field. + RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_Pos = 0x18 + // Bit mask of MEAS_TIME field. + RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_Msk = 0xff000000 + + // TOUCH_FILTER_CTRL: Configure touch filter settings + // Position of TOUCH_SMOOTH_LVL field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_SMOOTH_LVL_Pos = 0x9 + // Bit mask of TOUCH_SMOOTH_LVL field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_SMOOTH_LVL_Msk = 0x600 + // Position of TOUCH_JITTER_STEP field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_JITTER_STEP_Pos = 0xb + // Bit mask of TOUCH_JITTER_STEP field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_JITTER_STEP_Msk = 0x7800 + // Position of TOUCH_NEG_NOISE_LIMIT field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_LIMIT_Pos = 0xf + // Bit mask of TOUCH_NEG_NOISE_LIMIT field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_LIMIT_Msk = 0x78000 + // Position of TOUCH_NEG_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_THRES_Pos = 0x13 + // Bit mask of TOUCH_NEG_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_THRES_Msk = 0x180000 + // Position of TOUCH_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NOISE_THRES_Pos = 0x15 + // Bit mask of TOUCH_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NOISE_THRES_Msk = 0x600000 + // Position of TOUCH_HYSTERESIS field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_HYSTERESIS_Pos = 0x17 + // Bit mask of TOUCH_HYSTERESIS field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_HYSTERESIS_Msk = 0x1800000 + // Position of TOUCH_DEBOUNCE field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_DEBOUNCE_Pos = 0x19 + // Bit mask of TOUCH_DEBOUNCE field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_DEBOUNCE_Msk = 0xe000000 + // Position of TOUCH_FILTER_MODE field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_MODE_Pos = 0x1c + // Bit mask of TOUCH_FILTER_MODE field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_MODE_Msk = 0x70000000 + // Position of TOUCH_FILTER_EN field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_EN_Pos = 0x1f + // Bit mask of TOUCH_FILTER_EN field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_EN_Msk = 0x80000000 + // Bit TOUCH_FILTER_EN. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_EN = 0x80000000 + + // USB_CONF: configure usb control register + // Position of USB_VREFH field. + RTC_CNTL_USB_CONF_USB_VREFH_Pos = 0x0 + // Bit mask of USB_VREFH field. + RTC_CNTL_USB_CONF_USB_VREFH_Msk = 0x3 + // Position of USB_VREFL field. + RTC_CNTL_USB_CONF_USB_VREFL_Pos = 0x2 + // Bit mask of USB_VREFL field. + RTC_CNTL_USB_CONF_USB_VREFL_Msk = 0xc + // Position of USB_VREF_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_VREF_OVERRIDE_Pos = 0x4 + // Bit mask of USB_VREF_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_VREF_OVERRIDE_Msk = 0x10 + // Bit USB_VREF_OVERRIDE. + RTC_CNTL_USB_CONF_USB_VREF_OVERRIDE = 0x10 + // Position of USB_PAD_PULL_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_PAD_PULL_OVERRIDE_Pos = 0x5 + // Bit mask of USB_PAD_PULL_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_PAD_PULL_OVERRIDE_Msk = 0x20 + // Bit USB_PAD_PULL_OVERRIDE. + RTC_CNTL_USB_CONF_USB_PAD_PULL_OVERRIDE = 0x20 + // Position of USB_DP_PULLUP field. + RTC_CNTL_USB_CONF_USB_DP_PULLUP_Pos = 0x6 + // Bit mask of USB_DP_PULLUP field. + RTC_CNTL_USB_CONF_USB_DP_PULLUP_Msk = 0x40 + // Bit USB_DP_PULLUP. + RTC_CNTL_USB_CONF_USB_DP_PULLUP = 0x40 + // Position of USB_DP_PULLDOWN field. + RTC_CNTL_USB_CONF_USB_DP_PULLDOWN_Pos = 0x7 + // Bit mask of USB_DP_PULLDOWN field. + RTC_CNTL_USB_CONF_USB_DP_PULLDOWN_Msk = 0x80 + // Bit USB_DP_PULLDOWN. + RTC_CNTL_USB_CONF_USB_DP_PULLDOWN = 0x80 + // Position of USB_DM_PULLUP field. + RTC_CNTL_USB_CONF_USB_DM_PULLUP_Pos = 0x8 + // Bit mask of USB_DM_PULLUP field. + RTC_CNTL_USB_CONF_USB_DM_PULLUP_Msk = 0x100 + // Bit USB_DM_PULLUP. + RTC_CNTL_USB_CONF_USB_DM_PULLUP = 0x100 + // Position of USB_DM_PULLDOWN field. + RTC_CNTL_USB_CONF_USB_DM_PULLDOWN_Pos = 0x9 + // Bit mask of USB_DM_PULLDOWN field. + RTC_CNTL_USB_CONF_USB_DM_PULLDOWN_Msk = 0x200 + // Bit USB_DM_PULLDOWN. + RTC_CNTL_USB_CONF_USB_DM_PULLDOWN = 0x200 + // Position of USB_PULLUP_VALUE field. + RTC_CNTL_USB_CONF_USB_PULLUP_VALUE_Pos = 0xa + // Bit mask of USB_PULLUP_VALUE field. + RTC_CNTL_USB_CONF_USB_PULLUP_VALUE_Msk = 0x400 + // Bit USB_PULLUP_VALUE. + RTC_CNTL_USB_CONF_USB_PULLUP_VALUE = 0x400 + // Position of USB_PAD_ENABLE_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_OVERRIDE_Pos = 0xb + // Bit mask of USB_PAD_ENABLE_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_OVERRIDE_Msk = 0x800 + // Bit USB_PAD_ENABLE_OVERRIDE. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_OVERRIDE = 0x800 + // Position of USB_PAD_ENABLE field. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_Pos = 0xc + // Bit mask of USB_PAD_ENABLE field. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_Msk = 0x1000 + // Bit USB_PAD_ENABLE. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE = 0x1000 + // Position of USB_TXM field. + RTC_CNTL_USB_CONF_USB_TXM_Pos = 0xd + // Bit mask of USB_TXM field. + RTC_CNTL_USB_CONF_USB_TXM_Msk = 0x2000 + // Bit USB_TXM. + RTC_CNTL_USB_CONF_USB_TXM = 0x2000 + // Position of USB_TXP field. + RTC_CNTL_USB_CONF_USB_TXP_Pos = 0xe + // Bit mask of USB_TXP field. + RTC_CNTL_USB_CONF_USB_TXP_Msk = 0x4000 + // Bit USB_TXP. + RTC_CNTL_USB_CONF_USB_TXP = 0x4000 + // Position of USB_TX_EN field. + RTC_CNTL_USB_CONF_USB_TX_EN_Pos = 0xf + // Bit mask of USB_TX_EN field. + RTC_CNTL_USB_CONF_USB_TX_EN_Msk = 0x8000 + // Bit USB_TX_EN. + RTC_CNTL_USB_CONF_USB_TX_EN = 0x8000 + // Position of USB_TX_EN_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_TX_EN_OVERRIDE_Pos = 0x10 + // Bit mask of USB_TX_EN_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_TX_EN_OVERRIDE_Msk = 0x10000 + // Bit USB_TX_EN_OVERRIDE. + RTC_CNTL_USB_CONF_USB_TX_EN_OVERRIDE = 0x10000 + // Position of USB_RESET_DISABLE field. + RTC_CNTL_USB_CONF_USB_RESET_DISABLE_Pos = 0x11 + // Bit mask of USB_RESET_DISABLE field. + RTC_CNTL_USB_CONF_USB_RESET_DISABLE_Msk = 0x20000 + // Bit USB_RESET_DISABLE. + RTC_CNTL_USB_CONF_USB_RESET_DISABLE = 0x20000 + // Position of IO_MUX_RESET_DISABLE field. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE_Pos = 0x12 + // Bit mask of IO_MUX_RESET_DISABLE field. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE_Msk = 0x40000 + // Bit IO_MUX_RESET_DISABLE. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE = 0x40000 + + // TOUCH_TIMEOUT_CTRL: Configure touch timeout settings + // Position of TOUCH_TIMEOUT_NUM field. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_NUM_Pos = 0x0 + // Bit mask of TOUCH_TIMEOUT_NUM field. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_NUM_Msk = 0x3fffff + // Position of TOUCH_TIMEOUT_EN field. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN_Pos = 0x16 + // Bit mask of TOUCH_TIMEOUT_EN field. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN_Msk = 0x400000 + // Bit TOUCH_TIMEOUT_EN. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN = 0x400000 + + // SLP_REJECT_CAUSE: Stores the reject-to-sleep cause. + // Position of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CAUSE_REJECT_CAUSE_Pos = 0x0 + // Bit mask of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CAUSE_REJECT_CAUSE_Msk = 0x1ffff + + // OPTIONS1: RTC option register + // Position of FORCE_DOWNLOAD_BOOT field. + RTC_CNTL_OPTIONS1_FORCE_DOWNLOAD_BOOT_Pos = 0x0 + // Bit mask of FORCE_DOWNLOAD_BOOT field. + RTC_CNTL_OPTIONS1_FORCE_DOWNLOAD_BOOT_Msk = 0x1 + // Bit FORCE_DOWNLOAD_BOOT. + RTC_CNTL_OPTIONS1_FORCE_DOWNLOAD_BOOT = 0x1 + + // SLP_WAKEUP_CAUSE: Stores the sleep-to-wakeup cause. + // Position of WAKEUP_CAUSE field. + RTC_CNTL_SLP_WAKEUP_CAUSE_WAKEUP_CAUSE_Pos = 0x0 + // Bit mask of WAKEUP_CAUSE field. + RTC_CNTL_SLP_WAKEUP_CAUSE_WAKEUP_CAUSE_Msk = 0x1ffff + + // ULP_CP_TIMER_1: Configure sleep cycle of the timer + // Position of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Pos = 0x8 + // Bit mask of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Msk = 0xffffff00 + + // DATE + // Position of CNTL_DATE field. + RTC_CNTL_DATE_CNTL_DATE_Pos = 0x0 + // Bit mask of CNTL_DATE field. + RTC_CNTL_DATE_CNTL_DATE_Msk = 0xfffffff +) + +// Constants for RTC_I2C: Low-power I2C (Inter-Integrated Circuit) Controller +const ( + // SCL_LOW: Configure the low level width of SCL + // Position of PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_Msk = 0xfffff + + // CTRL: Transmission setting + // Position of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + RTC_I2C_CTRL_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + RTC_I2C_CTRL_SCL_FORCE_OUT = 0x2 + // Position of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Pos = 0x2 + // Bit mask of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Msk = 0x4 + // Bit MS_MODE. + RTC_I2C_CTRL_MS_MODE = 0x4 + // Position of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Pos = 0x3 + // Bit mask of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Msk = 0x8 + // Bit TRANS_START. + RTC_I2C_CTRL_TRANS_START = 0x8 + // Position of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Pos = 0x4 + // Bit mask of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Msk = 0x10 + // Bit TX_LSB_FIRST. + RTC_I2C_CTRL_TX_LSB_FIRST = 0x10 + // Position of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Pos = 0x5 + // Bit mask of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Msk = 0x20 + // Bit RX_LSB_FIRST. + RTC_I2C_CTRL_RX_LSB_FIRST = 0x20 + // Position of CLK_GATE_EN field. + RTC_I2C_CTRL_CLK_GATE_EN_Pos = 0x1d + // Bit mask of CLK_GATE_EN field. + RTC_I2C_CTRL_CLK_GATE_EN_Msk = 0x20000000 + // Bit CLK_GATE_EN. + RTC_I2C_CTRL_CLK_GATE_EN = 0x20000000 + // Position of RESET field. + RTC_I2C_CTRL_RESET_Pos = 0x1e + // Bit mask of RESET field. + RTC_I2C_CTRL_RESET_Msk = 0x40000000 + // Bit RESET. + RTC_I2C_CTRL_RESET = 0x40000000 + // Position of CLK_EN field. + RTC_I2C_CTRL_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + RTC_I2C_CTRL_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + RTC_I2C_CTRL_CLK_EN = 0x80000000 + + // STATUS: RTC I2C status + // Position of ACK_REC field. + RTC_I2C_STATUS_ACK_REC_Pos = 0x0 + // Bit mask of ACK_REC field. + RTC_I2C_STATUS_ACK_REC_Msk = 0x1 + // Bit ACK_REC. + RTC_I2C_STATUS_ACK_REC = 0x1 + // Position of SLAVE_RW field. + RTC_I2C_STATUS_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + RTC_I2C_STATUS_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + RTC_I2C_STATUS_SLAVE_RW = 0x2 + // Position of ARB_LOST field. + RTC_I2C_STATUS_ARB_LOST_Pos = 0x2 + // Bit mask of ARB_LOST field. + RTC_I2C_STATUS_ARB_LOST_Msk = 0x4 + // Bit ARB_LOST. + RTC_I2C_STATUS_ARB_LOST = 0x4 + // Position of BUS_BUSY field. + RTC_I2C_STATUS_BUS_BUSY_Pos = 0x3 + // Bit mask of BUS_BUSY field. + RTC_I2C_STATUS_BUS_BUSY_Msk = 0x8 + // Bit BUS_BUSY. + RTC_I2C_STATUS_BUS_BUSY = 0x8 + // Position of SLAVE_ADDRESSED field. + RTC_I2C_STATUS_SLAVE_ADDRESSED_Pos = 0x4 + // Bit mask of SLAVE_ADDRESSED field. + RTC_I2C_STATUS_SLAVE_ADDRESSED_Msk = 0x10 + // Bit SLAVE_ADDRESSED. + RTC_I2C_STATUS_SLAVE_ADDRESSED = 0x10 + // Position of BYTE_TRANS field. + RTC_I2C_STATUS_BYTE_TRANS_Pos = 0x5 + // Bit mask of BYTE_TRANS field. + RTC_I2C_STATUS_BYTE_TRANS_Msk = 0x20 + // Bit BYTE_TRANS. + RTC_I2C_STATUS_BYTE_TRANS = 0x20 + // Position of OP_CNT field. + RTC_I2C_STATUS_OP_CNT_Pos = 0x6 + // Bit mask of OP_CNT field. + RTC_I2C_STATUS_OP_CNT_Msk = 0xc0 + // Position of SHIFT field. + RTC_I2C_STATUS_SHIFT_Pos = 0x10 + // Bit mask of SHIFT field. + RTC_I2C_STATUS_SHIFT_Msk = 0xff0000 + // Position of SCL_MAIN_STATE_LAST field. + RTC_I2C_STATUS_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + RTC_I2C_STATUS_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + RTC_I2C_STATUS_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + RTC_I2C_STATUS_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: Configure RTC I2C timeout + // Position of TIME_OUT field. + RTC_I2C_TO_TIME_OUT_Pos = 0x0 + // Bit mask of TIME_OUT field. + RTC_I2C_TO_TIME_OUT_Msk = 0xfffff + + // SLAVE_ADDR: Configure slave address + // Position of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // SCL_HIGH: Configure the high level width of SCL + // Position of PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_Msk = 0xfffff + + // SDA_DUTY: Configure the SDA hold time after a negative SCL edge + // Position of NUM field. + RTC_I2C_SDA_DUTY_NUM_Pos = 0x0 + // Bit mask of NUM field. + RTC_I2C_SDA_DUTY_NUM_Msk = 0xfffff + + // SCL_START_PERIOD: Configure the delay between the SDA and SCL negative edge for a start condition + // Position of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Pos = 0x0 + // Bit mask of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Msk = 0xfffff + + // SCL_STOP_PERIOD: Configure the delay between SDA and SCL positive edge for a stop condition + // Position of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Pos = 0x0 + // Bit mask of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Msk = 0xfffff + + // INT_CLR: Clear RTC I2C interrupt + // Position of SLAVE_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_CLR. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR = 0x1 + // Position of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_CLR. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x2 + // Position of MASTER_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_CLR. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR = 0x4 + // Position of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_CLR. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x8 + // Position of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x4 + // Bit mask of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x10 + // Bit TIME_OUT_INT_CLR. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR = 0x10 + // Position of ACK_ERR_INT_CLR field. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR_Pos = 0x5 + // Bit mask of ACK_ERR_INT_CLR field. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR_Msk = 0x20 + // Bit ACK_ERR_INT_CLR. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR = 0x20 + // Position of RX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR_Pos = 0x6 + // Bit mask of RX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR_Msk = 0x40 + // Bit RX_DATA_INT_CLR. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR = 0x40 + // Position of TX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR_Pos = 0x7 + // Bit mask of TX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR_Msk = 0x80 + // Bit TX_DATA_INT_CLR. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR = 0x80 + // Position of DETECT_START_INT_CLR field. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR_Pos = 0x8 + // Bit mask of DETECT_START_INT_CLR field. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR_Msk = 0x100 + // Bit DETECT_START_INT_CLR. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR = 0x100 + + // INT_RAW: RTC I2C raw interrupt + // Position of SLAVE_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_RAW. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW = 0x1 + // Position of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_RAW. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x2 + // Position of MASTER_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_RAW. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW = 0x4 + // Position of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_RAW. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x8 + // Position of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x4 + // Bit mask of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x10 + // Bit TIME_OUT_INT_RAW. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW = 0x10 + // Position of ACK_ERR_INT_RAW field. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW_Pos = 0x5 + // Bit mask of ACK_ERR_INT_RAW field. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW_Msk = 0x20 + // Bit ACK_ERR_INT_RAW. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW = 0x20 + // Position of RX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW_Pos = 0x6 + // Bit mask of RX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW_Msk = 0x40 + // Bit RX_DATA_INT_RAW. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW = 0x40 + // Position of TX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW_Pos = 0x7 + // Bit mask of TX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW_Msk = 0x80 + // Bit TX_DATA_INT_RAW. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW = 0x80 + // Position of DETECT_START_INT_RAW field. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW_Pos = 0x8 + // Bit mask of DETECT_START_INT_RAW field. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW_Msk = 0x100 + // Bit DETECT_START_INT_RAW. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW = 0x100 + + // INT_ST: RTC I2C interrupt status + // Position of SLAVE_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_ST. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST = 0x1 + // Position of ARBITRATION_LOST_INT_ST field. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_ST field. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_ST. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST = 0x2 + // Position of MASTER_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_ST. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST = 0x4 + // Position of TRANS_COMPLETE_INT_ST field. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_ST field. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_ST. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST = 0x8 + // Position of TIME_OUT_INT_ST field. + RTC_I2C_INT_ST_TIME_OUT_INT_ST_Pos = 0x4 + // Bit mask of TIME_OUT_INT_ST field. + RTC_I2C_INT_ST_TIME_OUT_INT_ST_Msk = 0x10 + // Bit TIME_OUT_INT_ST. + RTC_I2C_INT_ST_TIME_OUT_INT_ST = 0x10 + // Position of ACK_ERR_INT_ST field. + RTC_I2C_INT_ST_ACK_ERR_INT_ST_Pos = 0x5 + // Bit mask of ACK_ERR_INT_ST field. + RTC_I2C_INT_ST_ACK_ERR_INT_ST_Msk = 0x20 + // Bit ACK_ERR_INT_ST. + RTC_I2C_INT_ST_ACK_ERR_INT_ST = 0x20 + // Position of RX_DATA_INT_ST field. + RTC_I2C_INT_ST_RX_DATA_INT_ST_Pos = 0x6 + // Bit mask of RX_DATA_INT_ST field. + RTC_I2C_INT_ST_RX_DATA_INT_ST_Msk = 0x40 + // Bit RX_DATA_INT_ST. + RTC_I2C_INT_ST_RX_DATA_INT_ST = 0x40 + // Position of TX_DATA_INT_ST field. + RTC_I2C_INT_ST_TX_DATA_INT_ST_Pos = 0x7 + // Bit mask of TX_DATA_INT_ST field. + RTC_I2C_INT_ST_TX_DATA_INT_ST_Msk = 0x80 + // Bit TX_DATA_INT_ST. + RTC_I2C_INT_ST_TX_DATA_INT_ST = 0x80 + // Position of DETECT_START_INT_ST field. + RTC_I2C_INT_ST_DETECT_START_INT_ST_Pos = 0x8 + // Bit mask of DETECT_START_INT_ST field. + RTC_I2C_INT_ST_DETECT_START_INT_ST_Msk = 0x100 + // Bit DETECT_START_INT_ST. + RTC_I2C_INT_ST_DETECT_START_INT_ST = 0x100 + + // INT_ENA: Enable RTC I2C interrupt + // Position of SLAVE_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_ENA. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA = 0x1 + // Position of ARBITRATION_LOST_INT_ENA field. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_ENA. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x2 + // Position of MASTER_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_ENA. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA = 0x4 + // Position of TRANS_COMPLETE_INT_ENA field. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_ENA. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x8 + // Position of TIME_OUT_INT_ENA field. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x4 + // Bit mask of TIME_OUT_INT_ENA field. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x10 + // Bit TIME_OUT_INT_ENA. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA = 0x10 + // Position of ACK_ERR_INT_ENA field. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA_Pos = 0x5 + // Bit mask of ACK_ERR_INT_ENA field. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA_Msk = 0x20 + // Bit ACK_ERR_INT_ENA. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA = 0x20 + // Position of RX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA_Pos = 0x6 + // Bit mask of RX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA_Msk = 0x40 + // Bit RX_DATA_INT_ENA. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA = 0x40 + // Position of TX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA_Pos = 0x7 + // Bit mask of TX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA_Msk = 0x80 + // Bit TX_DATA_INT_ENA. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA = 0x80 + // Position of DETECT_START_INT_ENA field. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA_Pos = 0x8 + // Bit mask of DETECT_START_INT_ENA field. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA_Msk = 0x100 + // Bit DETECT_START_INT_ENA. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA = 0x100 + + // DATA: RTC I2C read data + // Position of RDATA field. + RTC_I2C_DATA_RDATA_Pos = 0x0 + // Bit mask of RDATA field. + RTC_I2C_DATA_RDATA_Msk = 0xff + // Position of SLAVE_TX_DATA field. + RTC_I2C_DATA_SLAVE_TX_DATA_Pos = 0x8 + // Bit mask of SLAVE_TX_DATA field. + RTC_I2C_DATA_SLAVE_TX_DATA_Msk = 0xff00 + // Position of DONE field. + RTC_I2C_DATA_DONE_Pos = 0x1f + // Bit mask of DONE field. + RTC_I2C_DATA_DONE_Msk = 0x80000000 + // Bit DONE. + RTC_I2C_DATA_DONE = 0x80000000 + + // CMD0: RTC I2C Command %s + // Position of COMMAND field. + RTC_I2C_CMD_COMMAND_Pos = 0x0 + // Bit mask of COMMAND field. + RTC_I2C_CMD_COMMAND_Msk = 0x3fff + // Position of COMMAND_DONE field. + RTC_I2C_CMD_COMMAND_DONE_Pos = 0x1f + // Bit mask of COMMAND_DONE field. + RTC_I2C_CMD_COMMAND_DONE_Msk = 0x80000000 + // Bit COMMAND_DONE. + RTC_I2C_CMD_COMMAND_DONE = 0x80000000 + + // DATE: Version control register + // Position of DATE field. + RTC_I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RTC_I2C_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SENS: SENS Peripheral +const ( + // SAR_READER1_CTRL: RTC ADC1 data and sampling control + // Position of SAR1_CLK_DIV field. + SENS_SAR_READER1_CTRL_SAR1_CLK_DIV_Pos = 0x0 + // Bit mask of SAR1_CLK_DIV field. + SENS_SAR_READER1_CTRL_SAR1_CLK_DIV_Msk = 0xff + // Position of SAR1_CLK_GATED field. + SENS_SAR_READER1_CTRL_SAR1_CLK_GATED_Pos = 0x12 + // Bit mask of SAR1_CLK_GATED field. + SENS_SAR_READER1_CTRL_SAR1_CLK_GATED_Msk = 0x40000 + // Bit SAR1_CLK_GATED. + SENS_SAR_READER1_CTRL_SAR1_CLK_GATED = 0x40000 + // Position of SAR1_SAMPLE_NUM field. + SENS_SAR_READER1_CTRL_SAR1_SAMPLE_NUM_Pos = 0x13 + // Bit mask of SAR1_SAMPLE_NUM field. + SENS_SAR_READER1_CTRL_SAR1_SAMPLE_NUM_Msk = 0x7f80000 + // Position of SAR1_DATA_INV field. + SENS_SAR_READER1_CTRL_SAR1_DATA_INV_Pos = 0x1c + // Bit mask of SAR1_DATA_INV field. + SENS_SAR_READER1_CTRL_SAR1_DATA_INV_Msk = 0x10000000 + // Bit SAR1_DATA_INV. + SENS_SAR_READER1_CTRL_SAR1_DATA_INV = 0x10000000 + // Position of SAR1_INT_EN field. + SENS_SAR_READER1_CTRL_SAR1_INT_EN_Pos = 0x1d + // Bit mask of SAR1_INT_EN field. + SENS_SAR_READER1_CTRL_SAR1_INT_EN_Msk = 0x20000000 + // Bit SAR1_INT_EN. + SENS_SAR_READER1_CTRL_SAR1_INT_EN = 0x20000000 + + // SAR_READER1_STATUS: saradc1 status for debug + // Position of SAR1_READER_STATUS field. + SENS_SAR_READER1_STATUS_SAR1_READER_STATUS_Pos = 0x0 + // Bit mask of SAR1_READER_STATUS field. + SENS_SAR_READER1_STATUS_SAR1_READER_STATUS_Msk = 0xffffffff + + // SAR_MEAS1_CTRL1: Configure RTC ADC1 controller + // Position of RTC_SARADC_RESET field. + SENS_SAR_MEAS1_CTRL1_RTC_SARADC_RESET_Pos = 0x16 + // Bit mask of RTC_SARADC_RESET field. + SENS_SAR_MEAS1_CTRL1_RTC_SARADC_RESET_Msk = 0x400000 + // Bit RTC_SARADC_RESET. + SENS_SAR_MEAS1_CTRL1_RTC_SARADC_RESET = 0x400000 + // Position of RTC_SARADC_CLKGATE_EN field. + SENS_SAR_MEAS1_CTRL1_RTC_SARADC_CLKGATE_EN_Pos = 0x17 + // Bit mask of RTC_SARADC_CLKGATE_EN field. + SENS_SAR_MEAS1_CTRL1_RTC_SARADC_CLKGATE_EN_Msk = 0x800000 + // Bit RTC_SARADC_CLKGATE_EN. + SENS_SAR_MEAS1_CTRL1_RTC_SARADC_CLKGATE_EN = 0x800000 + // Position of FORCE_XPD_AMP field. + SENS_SAR_MEAS1_CTRL1_FORCE_XPD_AMP_Pos = 0x18 + // Bit mask of FORCE_XPD_AMP field. + SENS_SAR_MEAS1_CTRL1_FORCE_XPD_AMP_Msk = 0x3000000 + // Position of AMP_RST_FB_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_RST_FB_FORCE_Pos = 0x1a + // Bit mask of AMP_RST_FB_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_RST_FB_FORCE_Msk = 0xc000000 + // Position of AMP_SHORT_REF_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_SHORT_REF_FORCE_Pos = 0x1c + // Bit mask of AMP_SHORT_REF_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_SHORT_REF_FORCE_Msk = 0x30000000 + // Position of AMP_SHORT_REF_GND_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE_Pos = 0x1e + // Bit mask of AMP_SHORT_REF_GND_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE_Msk = 0xc0000000 + + // SAR_MEAS1_CTRL2: Control RTC ADC1 conversion and status + // Position of MEAS1_DATA_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_DATA_SAR_Pos = 0x0 + // Bit mask of MEAS1_DATA_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_DATA_SAR_Msk = 0xffff + // Position of MEAS1_DONE_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_DONE_SAR_Pos = 0x10 + // Bit mask of MEAS1_DONE_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_DONE_SAR_Msk = 0x10000 + // Bit MEAS1_DONE_SAR. + SENS_SAR_MEAS1_CTRL2_MEAS1_DONE_SAR = 0x10000 + // Position of MEAS1_START_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_SAR_Pos = 0x11 + // Bit mask of MEAS1_START_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_SAR_Msk = 0x20000 + // Bit MEAS1_START_SAR. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_SAR = 0x20000 + // Position of MEAS1_START_FORCE field. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_FORCE_Pos = 0x12 + // Bit mask of MEAS1_START_FORCE field. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_FORCE_Msk = 0x40000 + // Bit MEAS1_START_FORCE. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_FORCE = 0x40000 + // Position of SAR1_EN_PAD field. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_Pos = 0x13 + // Bit mask of SAR1_EN_PAD field. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_Msk = 0x7ff80000 + // Position of SAR1_EN_PAD_FORCE field. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE_Pos = 0x1f + // Bit mask of SAR1_EN_PAD_FORCE field. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE_Msk = 0x80000000 + // Bit SAR1_EN_PAD_FORCE. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE = 0x80000000 + + // SAR_MEAS1_MUX: Select the controller for SAR ADC1 + // Position of SAR1_DIG_FORCE field. + SENS_SAR_MEAS1_MUX_SAR1_DIG_FORCE_Pos = 0x1f + // Bit mask of SAR1_DIG_FORCE field. + SENS_SAR_MEAS1_MUX_SAR1_DIG_FORCE_Msk = 0x80000000 + // Bit SAR1_DIG_FORCE. + SENS_SAR_MEAS1_MUX_SAR1_DIG_FORCE = 0x80000000 + + // SAR_ATTEN1: Configure SAR ADC1 attenuation + // Position of SAR1_ATTEN field. + SENS_SAR_ATTEN1_SAR1_ATTEN_Pos = 0x0 + // Bit mask of SAR1_ATTEN field. + SENS_SAR_ATTEN1_SAR1_ATTEN_Msk = 0xffffffff + + // SAR_AMP_CTRL1: AMP control + // Position of SAR_AMP_WAIT1 field. + SENS_SAR_AMP_CTRL1_SAR_AMP_WAIT1_Pos = 0x0 + // Bit mask of SAR_AMP_WAIT1 field. + SENS_SAR_AMP_CTRL1_SAR_AMP_WAIT1_Msk = 0xffff + // Position of SAR_AMP_WAIT2 field. + SENS_SAR_AMP_CTRL1_SAR_AMP_WAIT2_Pos = 0x10 + // Bit mask of SAR_AMP_WAIT2 field. + SENS_SAR_AMP_CTRL1_SAR_AMP_WAIT2_Msk = 0xffff0000 + + // SAR_AMP_CTRL2: AMP control + // Position of SAR1_DAC_XPD_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE_Pos = 0x0 + // Bit mask of SAR1_DAC_XPD_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE_Msk = 0x1 + // Bit SAR1_DAC_XPD_FSM_IDLE. + SENS_SAR_AMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE = 0x1 + // Position of XPD_SAR_AMP_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_XPD_SAR_AMP_FSM_IDLE_Pos = 0x1 + // Bit mask of XPD_SAR_AMP_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_XPD_SAR_AMP_FSM_IDLE_Msk = 0x2 + // Bit XPD_SAR_AMP_FSM_IDLE. + SENS_SAR_AMP_CTRL2_XPD_SAR_AMP_FSM_IDLE = 0x2 + // Position of AMP_RST_FB_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_AMP_RST_FB_FSM_IDLE_Pos = 0x2 + // Bit mask of AMP_RST_FB_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_AMP_RST_FB_FSM_IDLE_Msk = 0x4 + // Bit AMP_RST_FB_FSM_IDLE. + SENS_SAR_AMP_CTRL2_AMP_RST_FB_FSM_IDLE = 0x4 + // Position of AMP_SHORT_REF_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_AMP_SHORT_REF_FSM_IDLE_Pos = 0x3 + // Bit mask of AMP_SHORT_REF_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_AMP_SHORT_REF_FSM_IDLE_Msk = 0x8 + // Bit AMP_SHORT_REF_FSM_IDLE. + SENS_SAR_AMP_CTRL2_AMP_SHORT_REF_FSM_IDLE = 0x8 + // Position of AMP_SHORT_REF_GND_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE_Pos = 0x4 + // Bit mask of AMP_SHORT_REF_GND_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE_Msk = 0x10 + // Bit AMP_SHORT_REF_GND_FSM_IDLE. + SENS_SAR_AMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE = 0x10 + // Position of XPD_SAR_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_XPD_SAR_FSM_IDLE_Pos = 0x5 + // Bit mask of XPD_SAR_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_XPD_SAR_FSM_IDLE_Msk = 0x20 + // Bit XPD_SAR_FSM_IDLE. + SENS_SAR_AMP_CTRL2_XPD_SAR_FSM_IDLE = 0x20 + // Position of SAR_RSTB_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE_Pos = 0x6 + // Bit mask of SAR_RSTB_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE_Msk = 0x40 + // Bit SAR_RSTB_FSM_IDLE. + SENS_SAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE = 0x40 + // Position of SAR_AMP_WAIT3 field. + SENS_SAR_AMP_CTRL2_SAR_AMP_WAIT3_Pos = 0x10 + // Bit mask of SAR_AMP_WAIT3 field. + SENS_SAR_AMP_CTRL2_SAR_AMP_WAIT3_Msk = 0xffff0000 + + // SAR_AMP_CTRL3: AMP control register + // Position of SAR1_DAC_XPD_FSM field. + SENS_SAR_AMP_CTRL3_SAR1_DAC_XPD_FSM_Pos = 0x0 + // Bit mask of SAR1_DAC_XPD_FSM field. + SENS_SAR_AMP_CTRL3_SAR1_DAC_XPD_FSM_Msk = 0xf + // Position of XPD_SAR_AMP_FSM field. + SENS_SAR_AMP_CTRL3_XPD_SAR_AMP_FSM_Pos = 0x4 + // Bit mask of XPD_SAR_AMP_FSM field. + SENS_SAR_AMP_CTRL3_XPD_SAR_AMP_FSM_Msk = 0xf0 + // Position of AMP_RST_FB_FSM field. + SENS_SAR_AMP_CTRL3_AMP_RST_FB_FSM_Pos = 0x8 + // Bit mask of AMP_RST_FB_FSM field. + SENS_SAR_AMP_CTRL3_AMP_RST_FB_FSM_Msk = 0xf00 + // Position of AMP_SHORT_REF_FSM field. + SENS_SAR_AMP_CTRL3_AMP_SHORT_REF_FSM_Pos = 0xc + // Bit mask of AMP_SHORT_REF_FSM field. + SENS_SAR_AMP_CTRL3_AMP_SHORT_REF_FSM_Msk = 0xf000 + // Position of AMP_SHORT_REF_GND_FSM field. + SENS_SAR_AMP_CTRL3_AMP_SHORT_REF_GND_FSM_Pos = 0x10 + // Bit mask of AMP_SHORT_REF_GND_FSM field. + SENS_SAR_AMP_CTRL3_AMP_SHORT_REF_GND_FSM_Msk = 0xf0000 + // Position of XPD_SAR_FSM field. + SENS_SAR_AMP_CTRL3_XPD_SAR_FSM_Pos = 0x14 + // Bit mask of XPD_SAR_FSM field. + SENS_SAR_AMP_CTRL3_XPD_SAR_FSM_Msk = 0xf00000 + // Position of SAR_RSTB_FSM field. + SENS_SAR_AMP_CTRL3_SAR_RSTB_FSM_Pos = 0x18 + // Bit mask of SAR_RSTB_FSM field. + SENS_SAR_AMP_CTRL3_SAR_RSTB_FSM_Msk = 0xf000000 + + // SAR_READER2_CTRL: RTC ADC2 data and sampling control + // Position of SAR2_CLK_DIV field. + SENS_SAR_READER2_CTRL_SAR2_CLK_DIV_Pos = 0x0 + // Bit mask of SAR2_CLK_DIV field. + SENS_SAR_READER2_CTRL_SAR2_CLK_DIV_Msk = 0xff + // Position of SAR2_WAIT_ARB_CYCLE field. + SENS_SAR_READER2_CTRL_SAR2_WAIT_ARB_CYCLE_Pos = 0x10 + // Bit mask of SAR2_WAIT_ARB_CYCLE field. + SENS_SAR_READER2_CTRL_SAR2_WAIT_ARB_CYCLE_Msk = 0x30000 + // Position of SAR2_CLK_GATED field. + SENS_SAR_READER2_CTRL_SAR2_CLK_GATED_Pos = 0x12 + // Bit mask of SAR2_CLK_GATED field. + SENS_SAR_READER2_CTRL_SAR2_CLK_GATED_Msk = 0x40000 + // Bit SAR2_CLK_GATED. + SENS_SAR_READER2_CTRL_SAR2_CLK_GATED = 0x40000 + // Position of SAR2_SAMPLE_NUM field. + SENS_SAR_READER2_CTRL_SAR2_SAMPLE_NUM_Pos = 0x13 + // Bit mask of SAR2_SAMPLE_NUM field. + SENS_SAR_READER2_CTRL_SAR2_SAMPLE_NUM_Msk = 0x7f80000 + // Position of SAR2_DATA_INV field. + SENS_SAR_READER2_CTRL_SAR2_DATA_INV_Pos = 0x1d + // Bit mask of SAR2_DATA_INV field. + SENS_SAR_READER2_CTRL_SAR2_DATA_INV_Msk = 0x20000000 + // Bit SAR2_DATA_INV. + SENS_SAR_READER2_CTRL_SAR2_DATA_INV = 0x20000000 + // Position of SAR2_INT_EN field. + SENS_SAR_READER2_CTRL_SAR2_INT_EN_Pos = 0x1e + // Bit mask of SAR2_INT_EN field. + SENS_SAR_READER2_CTRL_SAR2_INT_EN_Msk = 0x40000000 + // Bit SAR2_INT_EN. + SENS_SAR_READER2_CTRL_SAR2_INT_EN = 0x40000000 + + // SAR_READER2_STATUS: saradc2 status for debug + // Position of SAR2_READER_STATUS field. + SENS_SAR_READER2_STATUS_SAR2_READER_STATUS_Pos = 0x0 + // Bit mask of SAR2_READER_STATUS field. + SENS_SAR_READER2_STATUS_SAR2_READER_STATUS_Msk = 0xffffffff + + // SAR_MEAS2_CTRL1: configure rtc saradc2 + // Position of SAR2_CNTL_STATE field. + SENS_SAR_MEAS2_CTRL1_SAR2_CNTL_STATE_Pos = 0x0 + // Bit mask of SAR2_CNTL_STATE field. + SENS_SAR_MEAS2_CTRL1_SAR2_CNTL_STATE_Msk = 0x7 + // Position of SAR2_PWDET_CAL_EN field. + SENS_SAR_MEAS2_CTRL1_SAR2_PWDET_CAL_EN_Pos = 0x3 + // Bit mask of SAR2_PWDET_CAL_EN field. + SENS_SAR_MEAS2_CTRL1_SAR2_PWDET_CAL_EN_Msk = 0x8 + // Bit SAR2_PWDET_CAL_EN. + SENS_SAR_MEAS2_CTRL1_SAR2_PWDET_CAL_EN = 0x8 + // Position of SAR2_PKDET_CAL_EN field. + SENS_SAR_MEAS2_CTRL1_SAR2_PKDET_CAL_EN_Pos = 0x4 + // Bit mask of SAR2_PKDET_CAL_EN field. + SENS_SAR_MEAS2_CTRL1_SAR2_PKDET_CAL_EN_Msk = 0x10 + // Bit SAR2_PKDET_CAL_EN. + SENS_SAR_MEAS2_CTRL1_SAR2_PKDET_CAL_EN = 0x10 + // Position of SAR2_EN_TEST field. + SENS_SAR_MEAS2_CTRL1_SAR2_EN_TEST_Pos = 0x5 + // Bit mask of SAR2_EN_TEST field. + SENS_SAR_MEAS2_CTRL1_SAR2_EN_TEST_Msk = 0x20 + // Bit SAR2_EN_TEST. + SENS_SAR_MEAS2_CTRL1_SAR2_EN_TEST = 0x20 + // Position of SAR2_RSTB_FORCE field. + SENS_SAR_MEAS2_CTRL1_SAR2_RSTB_FORCE_Pos = 0x6 + // Bit mask of SAR2_RSTB_FORCE field. + SENS_SAR_MEAS2_CTRL1_SAR2_RSTB_FORCE_Msk = 0xc0 + // Position of SAR2_STANDBY_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR2_STANDBY_WAIT_Pos = 0x8 + // Bit mask of SAR2_STANDBY_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR2_STANDBY_WAIT_Msk = 0xff00 + // Position of SAR2_RSTB_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR2_RSTB_WAIT_Pos = 0x10 + // Bit mask of SAR2_RSTB_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR2_RSTB_WAIT_Msk = 0xff0000 + // Position of SAR2_XPD_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR2_XPD_WAIT_Pos = 0x18 + // Bit mask of SAR2_XPD_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR2_XPD_WAIT_Msk = 0xff000000 + + // SAR_MEAS2_CTRL2: Control RTC ADC2 conversion and status + // Position of MEAS2_DATA_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_DATA_SAR_Pos = 0x0 + // Bit mask of MEAS2_DATA_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_DATA_SAR_Msk = 0xffff + // Position of MEAS2_DONE_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_DONE_SAR_Pos = 0x10 + // Bit mask of MEAS2_DONE_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_DONE_SAR_Msk = 0x10000 + // Bit MEAS2_DONE_SAR. + SENS_SAR_MEAS2_CTRL2_MEAS2_DONE_SAR = 0x10000 + // Position of MEAS2_START_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_SAR_Pos = 0x11 + // Bit mask of MEAS2_START_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_SAR_Msk = 0x20000 + // Bit MEAS2_START_SAR. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_SAR = 0x20000 + // Position of MEAS2_START_FORCE field. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_FORCE_Pos = 0x12 + // Bit mask of MEAS2_START_FORCE field. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_FORCE_Msk = 0x40000 + // Bit MEAS2_START_FORCE. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_FORCE = 0x40000 + // Position of SAR2_EN_PAD field. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_Pos = 0x13 + // Bit mask of SAR2_EN_PAD field. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_Msk = 0x7ff80000 + // Position of SAR2_EN_PAD_FORCE field. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE_Pos = 0x1f + // Bit mask of SAR2_EN_PAD_FORCE field. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE_Msk = 0x80000000 + // Bit SAR2_EN_PAD_FORCE. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE = 0x80000000 + + // SAR_MEAS2_MUX: Select the controller for SAR ADC2 + // Position of SAR2_PWDET_CCT field. + SENS_SAR_MEAS2_MUX_SAR2_PWDET_CCT_Pos = 0x1c + // Bit mask of SAR2_PWDET_CCT field. + SENS_SAR_MEAS2_MUX_SAR2_PWDET_CCT_Msk = 0x70000000 + // Position of SAR2_RTC_FORCE field. + SENS_SAR_MEAS2_MUX_SAR2_RTC_FORCE_Pos = 0x1f + // Bit mask of SAR2_RTC_FORCE field. + SENS_SAR_MEAS2_MUX_SAR2_RTC_FORCE_Msk = 0x80000000 + // Bit SAR2_RTC_FORCE. + SENS_SAR_MEAS2_MUX_SAR2_RTC_FORCE = 0x80000000 + + // SAR_ATTEN2: Configure SAR ADC2 attenuation + // Position of SAR2_ATTEN field. + SENS_SAR_ATTEN2_SAR2_ATTEN_Pos = 0x0 + // Bit mask of SAR2_ATTEN field. + SENS_SAR_ATTEN2_SAR2_ATTEN_Msk = 0xffffffff + + // SAR_POWER_XPD_SAR: configure saradc’s power by sw + // Position of FORCE_XPD_SAR field. + SENS_SAR_POWER_XPD_SAR_FORCE_XPD_SAR_Pos = 0x1d + // Bit mask of FORCE_XPD_SAR field. + SENS_SAR_POWER_XPD_SAR_FORCE_XPD_SAR_Msk = 0x60000000 + // Position of SARCLK_EN field. + SENS_SAR_POWER_XPD_SAR_SARCLK_EN_Pos = 0x1f + // Bit mask of SARCLK_EN field. + SENS_SAR_POWER_XPD_SAR_SARCLK_EN_Msk = 0x80000000 + // Bit SARCLK_EN. + SENS_SAR_POWER_XPD_SAR_SARCLK_EN = 0x80000000 + + // SAR_SLAVE_ADDR1: Configure slave addresses 0-1 of RTC I2C + // Position of I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0_Msk = 0x3ff800 + // Position of MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_MEAS_STATUS_Pos = 0x16 + // Bit mask of MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_MEAS_STATUS_Msk = 0x3fc00000 + + // SAR_SLAVE_ADDR2: Configure slave addresses 2-3 of RTC I2C + // Position of I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2_Msk = 0x3ff800 + + // SAR_SLAVE_ADDR3: Configure slave addresses 4-5 of RTC I2C + // Position of I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4_Msk = 0x3ff800 + + // SAR_SLAVE_ADDR4: Configure slave addresses 6-7 of RTC I2C + // Position of I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6_Msk = 0x3ff800 + + // SAR_TSENS_CTRL: Temperature sensor data control + // Position of TSENS_OUT field. + SENS_SAR_TSENS_CTRL_TSENS_OUT_Pos = 0x0 + // Bit mask of TSENS_OUT field. + SENS_SAR_TSENS_CTRL_TSENS_OUT_Msk = 0xff + // Position of TSENS_READY field. + SENS_SAR_TSENS_CTRL_TSENS_READY_Pos = 0x8 + // Bit mask of TSENS_READY field. + SENS_SAR_TSENS_CTRL_TSENS_READY_Msk = 0x100 + // Bit TSENS_READY. + SENS_SAR_TSENS_CTRL_TSENS_READY = 0x100 + // Position of TSENS_INT_EN field. + SENS_SAR_TSENS_CTRL_TSENS_INT_EN_Pos = 0xc + // Bit mask of TSENS_INT_EN field. + SENS_SAR_TSENS_CTRL_TSENS_INT_EN_Msk = 0x1000 + // Bit TSENS_INT_EN. + SENS_SAR_TSENS_CTRL_TSENS_INT_EN = 0x1000 + // Position of TSENS_IN_INV field. + SENS_SAR_TSENS_CTRL_TSENS_IN_INV_Pos = 0xd + // Bit mask of TSENS_IN_INV field. + SENS_SAR_TSENS_CTRL_TSENS_IN_INV_Msk = 0x2000 + // Bit TSENS_IN_INV. + SENS_SAR_TSENS_CTRL_TSENS_IN_INV = 0x2000 + // Position of TSENS_CLK_DIV field. + SENS_SAR_TSENS_CTRL_TSENS_CLK_DIV_Pos = 0xe + // Bit mask of TSENS_CLK_DIV field. + SENS_SAR_TSENS_CTRL_TSENS_CLK_DIV_Msk = 0x3fc000 + // Position of TSENS_POWER_UP field. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_Pos = 0x16 + // Bit mask of TSENS_POWER_UP field. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_Msk = 0x400000 + // Bit TSENS_POWER_UP. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP = 0x400000 + // Position of TSENS_POWER_UP_FORCE field. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_FORCE_Pos = 0x17 + // Bit mask of TSENS_POWER_UP_FORCE field. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_FORCE_Msk = 0x800000 + // Bit TSENS_POWER_UP_FORCE. + SENS_SAR_TSENS_CTRL_TSENS_POWER_UP_FORCE = 0x800000 + // Position of TSENS_DUMP_OUT field. + SENS_SAR_TSENS_CTRL_TSENS_DUMP_OUT_Pos = 0x18 + // Bit mask of TSENS_DUMP_OUT field. + SENS_SAR_TSENS_CTRL_TSENS_DUMP_OUT_Msk = 0x1000000 + // Bit TSENS_DUMP_OUT. + SENS_SAR_TSENS_CTRL_TSENS_DUMP_OUT = 0x1000000 + + // SAR_TSENS_CTRL2: Temperature sensor control + // Position of TSENS_XPD_WAIT field. + SENS_SAR_TSENS_CTRL2_TSENS_XPD_WAIT_Pos = 0x0 + // Bit mask of TSENS_XPD_WAIT field. + SENS_SAR_TSENS_CTRL2_TSENS_XPD_WAIT_Msk = 0xfff + // Position of TSENS_XPD_FORCE field. + SENS_SAR_TSENS_CTRL2_TSENS_XPD_FORCE_Pos = 0xc + // Bit mask of TSENS_XPD_FORCE field. + SENS_SAR_TSENS_CTRL2_TSENS_XPD_FORCE_Msk = 0x3000 + // Position of TSENS_CLK_INV field. + SENS_SAR_TSENS_CTRL2_TSENS_CLK_INV_Pos = 0xe + // Bit mask of TSENS_CLK_INV field. + SENS_SAR_TSENS_CTRL2_TSENS_CLK_INV_Msk = 0x4000 + // Bit TSENS_CLK_INV. + SENS_SAR_TSENS_CTRL2_TSENS_CLK_INV = 0x4000 + // Position of TSENS_CLKGATE_EN field. + SENS_SAR_TSENS_CTRL2_TSENS_CLKGATE_EN_Pos = 0xf + // Bit mask of TSENS_CLKGATE_EN field. + SENS_SAR_TSENS_CTRL2_TSENS_CLKGATE_EN_Msk = 0x8000 + // Bit TSENS_CLKGATE_EN. + SENS_SAR_TSENS_CTRL2_TSENS_CLKGATE_EN = 0x8000 + // Position of TSENS_RESET field. + SENS_SAR_TSENS_CTRL2_TSENS_RESET_Pos = 0x10 + // Bit mask of TSENS_RESET field. + SENS_SAR_TSENS_CTRL2_TSENS_RESET_Msk = 0x10000 + // Bit TSENS_RESET. + SENS_SAR_TSENS_CTRL2_TSENS_RESET = 0x10000 + + // SAR_I2C_CTRL: Configure RTC I2C transmission + // Position of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Pos = 0x0 + // Bit mask of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Msk = 0xfffffff + // Position of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Pos = 0x1c + // Bit mask of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Msk = 0x10000000 + // Bit SAR_I2C_START. + SENS_SAR_I2C_CTRL_SAR_I2C_START = 0x10000000 + // Position of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Pos = 0x1d + // Bit mask of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Msk = 0x20000000 + // Bit SAR_I2C_START_FORCE. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE = 0x20000000 + + // SAR_TOUCH_CONF: Touch sensor configuration register + // Position of TOUCH_OUTEN field. + SENS_SAR_TOUCH_CONF_TOUCH_OUTEN_Pos = 0x0 + // Bit mask of TOUCH_OUTEN field. + SENS_SAR_TOUCH_CONF_TOUCH_OUTEN_Msk = 0x7fff + // Position of TOUCH_STATUS_CLR field. + SENS_SAR_TOUCH_CONF_TOUCH_STATUS_CLR_Pos = 0xf + // Bit mask of TOUCH_STATUS_CLR field. + SENS_SAR_TOUCH_CONF_TOUCH_STATUS_CLR_Msk = 0x8000 + // Bit TOUCH_STATUS_CLR. + SENS_SAR_TOUCH_CONF_TOUCH_STATUS_CLR = 0x8000 + // Position of TOUCH_DATA_SEL field. + SENS_SAR_TOUCH_CONF_TOUCH_DATA_SEL_Pos = 0x10 + // Bit mask of TOUCH_DATA_SEL field. + SENS_SAR_TOUCH_CONF_TOUCH_DATA_SEL_Msk = 0x30000 + // Position of TOUCH_DENOISE_END field. + SENS_SAR_TOUCH_CONF_TOUCH_DENOISE_END_Pos = 0x12 + // Bit mask of TOUCH_DENOISE_END field. + SENS_SAR_TOUCH_CONF_TOUCH_DENOISE_END_Msk = 0x40000 + // Bit TOUCH_DENOISE_END. + SENS_SAR_TOUCH_CONF_TOUCH_DENOISE_END = 0x40000 + // Position of TOUCH_UNIT_END field. + SENS_SAR_TOUCH_CONF_TOUCH_UNIT_END_Pos = 0x13 + // Bit mask of TOUCH_UNIT_END field. + SENS_SAR_TOUCH_CONF_TOUCH_UNIT_END_Msk = 0x80000 + // Bit TOUCH_UNIT_END. + SENS_SAR_TOUCH_CONF_TOUCH_UNIT_END = 0x80000 + // Position of TOUCH_APPROACH_PAD2 field. + SENS_SAR_TOUCH_CONF_TOUCH_APPROACH_PAD2_Pos = 0x14 + // Bit mask of TOUCH_APPROACH_PAD2 field. + SENS_SAR_TOUCH_CONF_TOUCH_APPROACH_PAD2_Msk = 0xf00000 + // Position of TOUCH_APPROACH_PAD1 field. + SENS_SAR_TOUCH_CONF_TOUCH_APPROACH_PAD1_Pos = 0x18 + // Bit mask of TOUCH_APPROACH_PAD1 field. + SENS_SAR_TOUCH_CONF_TOUCH_APPROACH_PAD1_Msk = 0xf000000 + // Position of TOUCH_APPROACH_PAD0 field. + SENS_SAR_TOUCH_CONF_TOUCH_APPROACH_PAD0_Pos = 0x1c + // Bit mask of TOUCH_APPROACH_PAD0 field. + SENS_SAR_TOUCH_CONF_TOUCH_APPROACH_PAD0_Msk = 0xf0000000 + + // SAR_TOUCH_THRES1: Finger threshold for touch pad 1 + // Position of TOUCH_OUT_TH1 field. + SENS_SAR_TOUCH_THRES1_TOUCH_OUT_TH1_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH1 field. + SENS_SAR_TOUCH_THRES1_TOUCH_OUT_TH1_Msk = 0x3fffff + + // SAR_TOUCH_THRES2: Finger threshold for touch pad 2 + // Position of TOUCH_OUT_TH2 field. + SENS_SAR_TOUCH_THRES2_TOUCH_OUT_TH2_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH2 field. + SENS_SAR_TOUCH_THRES2_TOUCH_OUT_TH2_Msk = 0x3fffff + + // SAR_TOUCH_THRES3: Finger threshold for touch pad 3 + // Position of TOUCH_OUT_TH3 field. + SENS_SAR_TOUCH_THRES3_TOUCH_OUT_TH3_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH3 field. + SENS_SAR_TOUCH_THRES3_TOUCH_OUT_TH3_Msk = 0x3fffff + + // SAR_TOUCH_THRES4: Finger threshold for touch pad 4 + // Position of TOUCH_OUT_TH4 field. + SENS_SAR_TOUCH_THRES4_TOUCH_OUT_TH4_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH4 field. + SENS_SAR_TOUCH_THRES4_TOUCH_OUT_TH4_Msk = 0x3fffff + + // SAR_TOUCH_THRES5: Finger threshold for touch pad 5 + // Position of TOUCH_OUT_TH5 field. + SENS_SAR_TOUCH_THRES5_TOUCH_OUT_TH5_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH5 field. + SENS_SAR_TOUCH_THRES5_TOUCH_OUT_TH5_Msk = 0x3fffff + + // SAR_TOUCH_THRES6: Finger threshold for touch pad 6 + // Position of TOUCH_OUT_TH6 field. + SENS_SAR_TOUCH_THRES6_TOUCH_OUT_TH6_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH6 field. + SENS_SAR_TOUCH_THRES6_TOUCH_OUT_TH6_Msk = 0x3fffff + + // SAR_TOUCH_THRES7: Finger threshold for touch pad 7 + // Position of TOUCH_OUT_TH7 field. + SENS_SAR_TOUCH_THRES7_TOUCH_OUT_TH7_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH7 field. + SENS_SAR_TOUCH_THRES7_TOUCH_OUT_TH7_Msk = 0x3fffff + + // SAR_TOUCH_THRES8: Finger threshold for touch pad 8 + // Position of TOUCH_OUT_TH8 field. + SENS_SAR_TOUCH_THRES8_TOUCH_OUT_TH8_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH8 field. + SENS_SAR_TOUCH_THRES8_TOUCH_OUT_TH8_Msk = 0x3fffff + + // SAR_TOUCH_THRES9: Finger threshold for touch pad 9 + // Position of TOUCH_OUT_TH9 field. + SENS_SAR_TOUCH_THRES9_TOUCH_OUT_TH9_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH9 field. + SENS_SAR_TOUCH_THRES9_TOUCH_OUT_TH9_Msk = 0x3fffff + + // SAR_TOUCH_THRES10: Finger threshold for touch pad 10 + // Position of TOUCH_OUT_TH10 field. + SENS_SAR_TOUCH_THRES10_TOUCH_OUT_TH10_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH10 field. + SENS_SAR_TOUCH_THRES10_TOUCH_OUT_TH10_Msk = 0x3fffff + + // SAR_TOUCH_THRES11: Finger threshold for touch pad 11 + // Position of TOUCH_OUT_TH11 field. + SENS_SAR_TOUCH_THRES11_TOUCH_OUT_TH11_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH11 field. + SENS_SAR_TOUCH_THRES11_TOUCH_OUT_TH11_Msk = 0x3fffff + + // SAR_TOUCH_THRES12: Finger threshold for touch pad 12 + // Position of TOUCH_OUT_TH12 field. + SENS_SAR_TOUCH_THRES12_TOUCH_OUT_TH12_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH12 field. + SENS_SAR_TOUCH_THRES12_TOUCH_OUT_TH12_Msk = 0x3fffff + + // SAR_TOUCH_THRES13: Finger threshold for touch pad 13 + // Position of TOUCH_OUT_TH13 field. + SENS_SAR_TOUCH_THRES13_TOUCH_OUT_TH13_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH13 field. + SENS_SAR_TOUCH_THRES13_TOUCH_OUT_TH13_Msk = 0x3fffff + + // SAR_TOUCH_THRES14: Finger threshold for touch pad 14 + // Position of TOUCH_OUT_TH14 field. + SENS_SAR_TOUCH_THRES14_TOUCH_OUT_TH14_Pos = 0x0 + // Bit mask of TOUCH_OUT_TH14 field. + SENS_SAR_TOUCH_THRES14_TOUCH_OUT_TH14_Msk = 0x3fffff + + // SAR_TOUCH_CHN_ST: Touch channel status register + // Position of TOUCH_PAD_ACTIVE field. + SENS_SAR_TOUCH_CHN_ST_TOUCH_PAD_ACTIVE_Pos = 0x0 + // Bit mask of TOUCH_PAD_ACTIVE field. + SENS_SAR_TOUCH_CHN_ST_TOUCH_PAD_ACTIVE_Msk = 0x7fff + // Position of TOUCH_CHANNEL_CLR field. + SENS_SAR_TOUCH_CHN_ST_TOUCH_CHANNEL_CLR_Pos = 0xf + // Bit mask of TOUCH_CHANNEL_CLR field. + SENS_SAR_TOUCH_CHN_ST_TOUCH_CHANNEL_CLR_Msk = 0x3fff8000 + // Position of TOUCH_MEAS_DONE field. + SENS_SAR_TOUCH_CHN_ST_TOUCH_MEAS_DONE_Pos = 0x1f + // Bit mask of TOUCH_MEAS_DONE field. + SENS_SAR_TOUCH_CHN_ST_TOUCH_MEAS_DONE_Msk = 0x80000000 + // Bit TOUCH_MEAS_DONE. + SENS_SAR_TOUCH_CHN_ST_TOUCH_MEAS_DONE = 0x80000000 + + // SAR_TOUCH_STATUS0: Status of touch controller + // Position of TOUCH_DENOISE_DATA field. + SENS_SAR_TOUCH_STATUS0_TOUCH_DENOISE_DATA_Pos = 0x0 + // Bit mask of TOUCH_DENOISE_DATA field. + SENS_SAR_TOUCH_STATUS0_TOUCH_DENOISE_DATA_Msk = 0x3fffff + // Position of TOUCH_SCAN_CURR field. + SENS_SAR_TOUCH_STATUS0_TOUCH_SCAN_CURR_Pos = 0x16 + // Bit mask of TOUCH_SCAN_CURR field. + SENS_SAR_TOUCH_STATUS0_TOUCH_SCAN_CURR_Msk = 0x3c00000 + + // SAR_TOUCH_STATUS1: Touch pad 1 status + // Position of TOUCH_PAD1_DATA field. + SENS_SAR_TOUCH_STATUS1_TOUCH_PAD1_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD1_DATA field. + SENS_SAR_TOUCH_STATUS1_TOUCH_PAD1_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD1_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS1_TOUCH_PAD1_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD1_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS1_TOUCH_PAD1_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS2: Touch pad 2 status + // Position of TOUCH_PAD2_DATA field. + SENS_SAR_TOUCH_STATUS2_TOUCH_PAD2_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD2_DATA field. + SENS_SAR_TOUCH_STATUS2_TOUCH_PAD2_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD2_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS2_TOUCH_PAD2_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD2_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS2_TOUCH_PAD2_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS3: Touch pad 3 status + // Position of TOUCH_PAD3_DATA field. + SENS_SAR_TOUCH_STATUS3_TOUCH_PAD3_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD3_DATA field. + SENS_SAR_TOUCH_STATUS3_TOUCH_PAD3_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD3_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS3_TOUCH_PAD3_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD3_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS3_TOUCH_PAD3_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS4: Touch pad 4 status + // Position of TOUCH_PAD4_DATA field. + SENS_SAR_TOUCH_STATUS4_TOUCH_PAD4_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD4_DATA field. + SENS_SAR_TOUCH_STATUS4_TOUCH_PAD4_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD4_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS4_TOUCH_PAD4_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD4_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS4_TOUCH_PAD4_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS5: Touch pad 5 status + // Position of TOUCH_PAD5_DATA field. + SENS_SAR_TOUCH_STATUS5_TOUCH_PAD5_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD5_DATA field. + SENS_SAR_TOUCH_STATUS5_TOUCH_PAD5_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD5_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS5_TOUCH_PAD5_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD5_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS5_TOUCH_PAD5_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS6: Touch pad 6 status + // Position of TOUCH_PAD6_DATA field. + SENS_SAR_TOUCH_STATUS6_TOUCH_PAD6_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD6_DATA field. + SENS_SAR_TOUCH_STATUS6_TOUCH_PAD6_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD6_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS6_TOUCH_PAD6_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD6_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS6_TOUCH_PAD6_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS7: Touch pad 7 status + // Position of TOUCH_PAD7_DATA field. + SENS_SAR_TOUCH_STATUS7_TOUCH_PAD7_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD7_DATA field. + SENS_SAR_TOUCH_STATUS7_TOUCH_PAD7_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD7_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS7_TOUCH_PAD7_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD7_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS7_TOUCH_PAD7_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS8: Touch pad 8 status + // Position of TOUCH_PAD8_DATA field. + SENS_SAR_TOUCH_STATUS8_TOUCH_PAD8_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD8_DATA field. + SENS_SAR_TOUCH_STATUS8_TOUCH_PAD8_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD8_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS8_TOUCH_PAD8_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD8_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS8_TOUCH_PAD8_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS9: Touch pad 9 status + // Position of TOUCH_PAD9_DATA field. + SENS_SAR_TOUCH_STATUS9_TOUCH_PAD9_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD9_DATA field. + SENS_SAR_TOUCH_STATUS9_TOUCH_PAD9_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD9_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS9_TOUCH_PAD9_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD9_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS9_TOUCH_PAD9_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS10: Touch pad 10 status + // Position of TOUCH_PAD10_DATA field. + SENS_SAR_TOUCH_STATUS10_TOUCH_PAD10_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD10_DATA field. + SENS_SAR_TOUCH_STATUS10_TOUCH_PAD10_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD10_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS10_TOUCH_PAD10_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD10_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS10_TOUCH_PAD10_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS11: Touch pad 11 status + // Position of TOUCH_PAD11_DATA field. + SENS_SAR_TOUCH_STATUS11_TOUCH_PAD11_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD11_DATA field. + SENS_SAR_TOUCH_STATUS11_TOUCH_PAD11_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD11_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS11_TOUCH_PAD11_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD11_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS11_TOUCH_PAD11_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS12: Touch pad 12 status + // Position of TOUCH_PAD12_DATA field. + SENS_SAR_TOUCH_STATUS12_TOUCH_PAD12_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD12_DATA field. + SENS_SAR_TOUCH_STATUS12_TOUCH_PAD12_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD12_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS12_TOUCH_PAD12_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD12_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS12_TOUCH_PAD12_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS13: Touch pad 13 status + // Position of TOUCH_PAD13_DATA field. + SENS_SAR_TOUCH_STATUS13_TOUCH_PAD13_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD13_DATA field. + SENS_SAR_TOUCH_STATUS13_TOUCH_PAD13_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD13_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS13_TOUCH_PAD13_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD13_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS13_TOUCH_PAD13_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS14: Touch pad 14 status + // Position of TOUCH_PAD14_DATA field. + SENS_SAR_TOUCH_STATUS14_TOUCH_PAD14_DATA_Pos = 0x0 + // Bit mask of TOUCH_PAD14_DATA field. + SENS_SAR_TOUCH_STATUS14_TOUCH_PAD14_DATA_Msk = 0x3fffff + // Position of TOUCH_PAD14_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS14_TOUCH_PAD14_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_PAD14_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS14_TOUCH_PAD14_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS15: Touch sleep pad status + // Position of TOUCH_SLP_DATA field. + SENS_SAR_TOUCH_STATUS15_TOUCH_SLP_DATA_Pos = 0x0 + // Bit mask of TOUCH_SLP_DATA field. + SENS_SAR_TOUCH_STATUS15_TOUCH_SLP_DATA_Msk = 0x3fffff + // Position of TOUCH_SLP_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS15_TOUCH_SLP_DEBOUNCE_Pos = 0x1d + // Bit mask of TOUCH_SLP_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS15_TOUCH_SLP_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS16: Touch approach count status + // Position of TOUCH_APPROACH_PAD2_CNT field. + SENS_SAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD2_CNT_Pos = 0x0 + // Bit mask of TOUCH_APPROACH_PAD2_CNT field. + SENS_SAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD2_CNT_Msk = 0xff + // Position of TOUCH_APPROACH_PAD1_CNT field. + SENS_SAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD1_CNT_Pos = 0x8 + // Bit mask of TOUCH_APPROACH_PAD1_CNT field. + SENS_SAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD1_CNT_Msk = 0xff00 + // Position of TOUCH_APPROACH_PAD0_CNT field. + SENS_SAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD0_CNT_Pos = 0x10 + // Bit mask of TOUCH_APPROACH_PAD0_CNT field. + SENS_SAR_TOUCH_STATUS16_TOUCH_APPROACH_PAD0_CNT_Msk = 0xff0000 + // Position of TOUCH_SLP_APPROACH_CNT field. + SENS_SAR_TOUCH_STATUS16_TOUCH_SLP_APPROACH_CNT_Pos = 0x18 + // Bit mask of TOUCH_SLP_APPROACH_CNT field. + SENS_SAR_TOUCH_STATUS16_TOUCH_SLP_APPROACH_CNT_Msk = 0xff000000 + + // SAR_DAC_CTRL1: DAC control + // Position of SW_FSTEP field. + SENS_SAR_DAC_CTRL1_SW_FSTEP_Pos = 0x0 + // Bit mask of SW_FSTEP field. + SENS_SAR_DAC_CTRL1_SW_FSTEP_Msk = 0xffff + // Position of SW_TONE_EN field. + SENS_SAR_DAC_CTRL1_SW_TONE_EN_Pos = 0x10 + // Bit mask of SW_TONE_EN field. + SENS_SAR_DAC_CTRL1_SW_TONE_EN_Msk = 0x10000 + // Bit SW_TONE_EN. + SENS_SAR_DAC_CTRL1_SW_TONE_EN = 0x10000 + // Position of DEBUG_BIT_SEL field. + SENS_SAR_DAC_CTRL1_DEBUG_BIT_SEL_Pos = 0x11 + // Bit mask of DEBUG_BIT_SEL field. + SENS_SAR_DAC_CTRL1_DEBUG_BIT_SEL_Msk = 0x3e0000 + // Position of DAC_DIG_FORCE field. + SENS_SAR_DAC_CTRL1_DAC_DIG_FORCE_Pos = 0x16 + // Bit mask of DAC_DIG_FORCE field. + SENS_SAR_DAC_CTRL1_DAC_DIG_FORCE_Msk = 0x400000 + // Bit DAC_DIG_FORCE. + SENS_SAR_DAC_CTRL1_DAC_DIG_FORCE = 0x400000 + // Position of DAC_CLK_FORCE_LOW field. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_LOW_Pos = 0x17 + // Bit mask of DAC_CLK_FORCE_LOW field. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_LOW_Msk = 0x800000 + // Bit DAC_CLK_FORCE_LOW. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_LOW = 0x800000 + // Position of DAC_CLK_FORCE_HIGH field. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH_Pos = 0x18 + // Bit mask of DAC_CLK_FORCE_HIGH field. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH_Msk = 0x1000000 + // Bit DAC_CLK_FORCE_HIGH. + SENS_SAR_DAC_CTRL1_DAC_CLK_FORCE_HIGH = 0x1000000 + // Position of DAC_CLK_INV field. + SENS_SAR_DAC_CTRL1_DAC_CLK_INV_Pos = 0x19 + // Bit mask of DAC_CLK_INV field. + SENS_SAR_DAC_CTRL1_DAC_CLK_INV_Msk = 0x2000000 + // Bit DAC_CLK_INV. + SENS_SAR_DAC_CTRL1_DAC_CLK_INV = 0x2000000 + // Position of DAC_RESET field. + SENS_SAR_DAC_CTRL1_DAC_RESET_Pos = 0x1a + // Bit mask of DAC_RESET field. + SENS_SAR_DAC_CTRL1_DAC_RESET_Msk = 0x4000000 + // Bit DAC_RESET. + SENS_SAR_DAC_CTRL1_DAC_RESET = 0x4000000 + // Position of DAC_CLKGATE_EN field. + SENS_SAR_DAC_CTRL1_DAC_CLKGATE_EN_Pos = 0x1b + // Bit mask of DAC_CLKGATE_EN field. + SENS_SAR_DAC_CTRL1_DAC_CLKGATE_EN_Msk = 0x8000000 + // Bit DAC_CLKGATE_EN. + SENS_SAR_DAC_CTRL1_DAC_CLKGATE_EN = 0x8000000 + + // SAR_DAC_CTRL2: DAC output control + // Position of DAC_DC1 field. + SENS_SAR_DAC_CTRL2_DAC_DC1_Pos = 0x0 + // Bit mask of DAC_DC1 field. + SENS_SAR_DAC_CTRL2_DAC_DC1_Msk = 0xff + // Position of DAC_DC2 field. + SENS_SAR_DAC_CTRL2_DAC_DC2_Pos = 0x8 + // Bit mask of DAC_DC2 field. + SENS_SAR_DAC_CTRL2_DAC_DC2_Msk = 0xff00 + // Position of DAC_SCALE1 field. + SENS_SAR_DAC_CTRL2_DAC_SCALE1_Pos = 0x10 + // Bit mask of DAC_SCALE1 field. + SENS_SAR_DAC_CTRL2_DAC_SCALE1_Msk = 0x30000 + // Position of DAC_SCALE2 field. + SENS_SAR_DAC_CTRL2_DAC_SCALE2_Pos = 0x12 + // Bit mask of DAC_SCALE2 field. + SENS_SAR_DAC_CTRL2_DAC_SCALE2_Msk = 0xc0000 + // Position of DAC_INV1 field. + SENS_SAR_DAC_CTRL2_DAC_INV1_Pos = 0x14 + // Bit mask of DAC_INV1 field. + SENS_SAR_DAC_CTRL2_DAC_INV1_Msk = 0x300000 + // Position of DAC_INV2 field. + SENS_SAR_DAC_CTRL2_DAC_INV2_Pos = 0x16 + // Bit mask of DAC_INV2 field. + SENS_SAR_DAC_CTRL2_DAC_INV2_Msk = 0xc00000 + // Position of DAC_CW_EN1 field. + SENS_SAR_DAC_CTRL2_DAC_CW_EN1_Pos = 0x18 + // Bit mask of DAC_CW_EN1 field. + SENS_SAR_DAC_CTRL2_DAC_CW_EN1_Msk = 0x1000000 + // Bit DAC_CW_EN1. + SENS_SAR_DAC_CTRL2_DAC_CW_EN1 = 0x1000000 + // Position of DAC_CW_EN2 field. + SENS_SAR_DAC_CTRL2_DAC_CW_EN2_Pos = 0x19 + // Bit mask of DAC_CW_EN2 field. + SENS_SAR_DAC_CTRL2_DAC_CW_EN2_Msk = 0x2000000 + // Bit DAC_CW_EN2. + SENS_SAR_DAC_CTRL2_DAC_CW_EN2 = 0x2000000 + + // SAR_COCPU_STATE: ULP-RISCV status + // Position of COCPU_DBG_TRIGGER field. + SENS_SAR_COCPU_STATE_COCPU_DBG_TRIGGER_Pos = 0x19 + // Bit mask of COCPU_DBG_TRIGGER field. + SENS_SAR_COCPU_STATE_COCPU_DBG_TRIGGER_Msk = 0x2000000 + // Bit COCPU_DBG_TRIGGER. + SENS_SAR_COCPU_STATE_COCPU_DBG_TRIGGER = 0x2000000 + // Position of COCPU_CLK_EN field. + SENS_SAR_COCPU_STATE_COCPU_CLK_EN_Pos = 0x1a + // Bit mask of COCPU_CLK_EN field. + SENS_SAR_COCPU_STATE_COCPU_CLK_EN_Msk = 0x4000000 + // Bit COCPU_CLK_EN. + SENS_SAR_COCPU_STATE_COCPU_CLK_EN = 0x4000000 + // Position of COCPU_RESET_N field. + SENS_SAR_COCPU_STATE_COCPU_RESET_N_Pos = 0x1b + // Bit mask of COCPU_RESET_N field. + SENS_SAR_COCPU_STATE_COCPU_RESET_N_Msk = 0x8000000 + // Bit COCPU_RESET_N. + SENS_SAR_COCPU_STATE_COCPU_RESET_N = 0x8000000 + // Position of COCPU_EOI field. + SENS_SAR_COCPU_STATE_COCPU_EOI_Pos = 0x1c + // Bit mask of COCPU_EOI field. + SENS_SAR_COCPU_STATE_COCPU_EOI_Msk = 0x10000000 + // Bit COCPU_EOI. + SENS_SAR_COCPU_STATE_COCPU_EOI = 0x10000000 + // Position of COCPU_TRAP field. + SENS_SAR_COCPU_STATE_COCPU_TRAP_Pos = 0x1d + // Bit mask of COCPU_TRAP field. + SENS_SAR_COCPU_STATE_COCPU_TRAP_Msk = 0x20000000 + // Bit COCPU_TRAP. + SENS_SAR_COCPU_STATE_COCPU_TRAP = 0x20000000 + // Position of COCPU_EBREAK field. + SENS_SAR_COCPU_STATE_COCPU_EBREAK_Pos = 0x1e + // Bit mask of COCPU_EBREAK field. + SENS_SAR_COCPU_STATE_COCPU_EBREAK_Msk = 0x40000000 + // Bit COCPU_EBREAK. + SENS_SAR_COCPU_STATE_COCPU_EBREAK = 0x40000000 + + // SAR_COCPU_INT_RAW: Interrupt raw bit of ULP-RISCV + // Position of COCPU_TOUCH_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW_Pos = 0x0 + // Bit mask of COCPU_TOUCH_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW_Msk = 0x1 + // Bit COCPU_TOUCH_DONE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW = 0x1 + // Position of COCPU_TOUCH_INACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW_Pos = 0x1 + // Bit mask of COCPU_TOUCH_INACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW_Msk = 0x2 + // Bit COCPU_TOUCH_INACTIVE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW = 0x2 + // Position of COCPU_TOUCH_ACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW_Pos = 0x2 + // Bit mask of COCPU_TOUCH_ACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW_Msk = 0x4 + // Bit COCPU_TOUCH_ACTIVE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW = 0x4 + // Position of COCPU_SARADC1_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW_Pos = 0x3 + // Bit mask of COCPU_SARADC1_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW_Msk = 0x8 + // Bit COCPU_SARADC1_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW = 0x8 + // Position of COCPU_SARADC2_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW_Pos = 0x4 + // Bit mask of COCPU_SARADC2_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW_Msk = 0x10 + // Bit COCPU_SARADC2_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW = 0x10 + // Position of COCPU_TSENS_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW_Pos = 0x5 + // Bit mask of COCPU_TSENS_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW_Msk = 0x20 + // Bit COCPU_TSENS_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW = 0x20 + // Position of COCPU_START_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_START_INT_RAW_Pos = 0x6 + // Bit mask of COCPU_START_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_START_INT_RAW_Msk = 0x40 + // Bit COCPU_START_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_START_INT_RAW = 0x40 + // Position of COCPU_SW_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SW_INT_RAW_Pos = 0x7 + // Bit mask of COCPU_SW_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SW_INT_RAW_Msk = 0x80 + // Bit COCPU_SW_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_SW_INT_RAW = 0x80 + // Position of COCPU_SWD_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW_Pos = 0x8 + // Bit mask of COCPU_SWD_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW_Msk = 0x100 + // Bit COCPU_SWD_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW = 0x100 + + // SAR_COCPU_INT_ENA: Interrupt enable bit of ULP-RISCV + // Position of COCPU_TOUCH_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA_Pos = 0x0 + // Bit mask of COCPU_TOUCH_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA_Msk = 0x1 + // Bit COCPU_TOUCH_DONE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA = 0x1 + // Position of COCPU_TOUCH_INACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA_Pos = 0x1 + // Bit mask of COCPU_TOUCH_INACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA_Msk = 0x2 + // Bit COCPU_TOUCH_INACTIVE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA = 0x2 + // Position of COCPU_TOUCH_ACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA_Pos = 0x2 + // Bit mask of COCPU_TOUCH_ACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA_Msk = 0x4 + // Bit COCPU_TOUCH_ACTIVE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA = 0x4 + // Position of COCPU_SARADC1_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA_Pos = 0x3 + // Bit mask of COCPU_SARADC1_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA_Msk = 0x8 + // Bit COCPU_SARADC1_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA = 0x8 + // Position of COCPU_SARADC2_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA_Pos = 0x4 + // Bit mask of COCPU_SARADC2_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA_Msk = 0x10 + // Bit COCPU_SARADC2_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA = 0x10 + // Position of COCPU_TSENS_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA_Pos = 0x5 + // Bit mask of COCPU_TSENS_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA_Msk = 0x20 + // Bit COCPU_TSENS_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA = 0x20 + // Position of COCPU_START_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_START_INT_ENA_Pos = 0x6 + // Bit mask of COCPU_START_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_START_INT_ENA_Msk = 0x40 + // Bit COCPU_START_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_START_INT_ENA = 0x40 + // Position of COCPU_SW_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SW_INT_ENA_Pos = 0x7 + // Bit mask of COCPU_SW_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SW_INT_ENA_Msk = 0x80 + // Bit COCPU_SW_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_SW_INT_ENA = 0x80 + // Position of COCPU_SWD_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA_Pos = 0x8 + // Bit mask of COCPU_SWD_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA_Msk = 0x100 + // Bit COCPU_SWD_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA = 0x100 + + // SAR_COCPU_INT_ST: Interrupt status bit of ULP-RISCV + // Position of COCPU_TOUCH_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST_Pos = 0x0 + // Bit mask of COCPU_TOUCH_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST_Msk = 0x1 + // Bit COCPU_TOUCH_DONE_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST = 0x1 + // Position of COCPU_TOUCH_INACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST_Pos = 0x1 + // Bit mask of COCPU_TOUCH_INACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST_Msk = 0x2 + // Bit COCPU_TOUCH_INACTIVE_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST = 0x2 + // Position of COCPU_TOUCH_ACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST_Pos = 0x2 + // Bit mask of COCPU_TOUCH_ACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST_Msk = 0x4 + // Bit COCPU_TOUCH_ACTIVE_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST = 0x4 + // Position of COCPU_SARADC1_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST_Pos = 0x3 + // Bit mask of COCPU_SARADC1_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST_Msk = 0x8 + // Bit COCPU_SARADC1_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST = 0x8 + // Position of COCPU_SARADC2_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST_Pos = 0x4 + // Bit mask of COCPU_SARADC2_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST_Msk = 0x10 + // Bit COCPU_SARADC2_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST = 0x10 + // Position of COCPU_TSENS_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TSENS_INT_ST_Pos = 0x5 + // Bit mask of COCPU_TSENS_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TSENS_INT_ST_Msk = 0x20 + // Bit COCPU_TSENS_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_TSENS_INT_ST = 0x20 + // Position of COCPU_START_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_START_INT_ST_Pos = 0x6 + // Bit mask of COCPU_START_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_START_INT_ST_Msk = 0x40 + // Bit COCPU_START_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_START_INT_ST = 0x40 + // Position of COCPU_SW_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SW_INT_ST_Pos = 0x7 + // Bit mask of COCPU_SW_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SW_INT_ST_Msk = 0x80 + // Bit COCPU_SW_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_SW_INT_ST = 0x80 + // Position of COCPU_SWD_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SWD_INT_ST_Pos = 0x8 + // Bit mask of COCPU_SWD_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SWD_INT_ST_Msk = 0x100 + // Bit COCPU_SWD_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_SWD_INT_ST = 0x100 + + // SAR_COCPU_INT_CLR: Interrupt clear bit of ULP-RISCV + // Position of COCPU_TOUCH_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR_Pos = 0x0 + // Bit mask of COCPU_TOUCH_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR_Msk = 0x1 + // Bit COCPU_TOUCH_DONE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR = 0x1 + // Position of COCPU_TOUCH_INACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR_Pos = 0x1 + // Bit mask of COCPU_TOUCH_INACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR_Msk = 0x2 + // Bit COCPU_TOUCH_INACTIVE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR = 0x2 + // Position of COCPU_TOUCH_ACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR_Pos = 0x2 + // Bit mask of COCPU_TOUCH_ACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR_Msk = 0x4 + // Bit COCPU_TOUCH_ACTIVE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR = 0x4 + // Position of COCPU_SARADC1_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR_Pos = 0x3 + // Bit mask of COCPU_SARADC1_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR_Msk = 0x8 + // Bit COCPU_SARADC1_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR = 0x8 + // Position of COCPU_SARADC2_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR_Pos = 0x4 + // Bit mask of COCPU_SARADC2_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR_Msk = 0x10 + // Bit COCPU_SARADC2_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR = 0x10 + // Position of COCPU_TSENS_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR_Pos = 0x5 + // Bit mask of COCPU_TSENS_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR_Msk = 0x20 + // Bit COCPU_TSENS_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR = 0x20 + // Position of COCPU_START_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_START_INT_CLR_Pos = 0x6 + // Bit mask of COCPU_START_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_START_INT_CLR_Msk = 0x40 + // Bit COCPU_START_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_START_INT_CLR = 0x40 + // Position of COCPU_SW_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SW_INT_CLR_Pos = 0x7 + // Bit mask of COCPU_SW_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SW_INT_CLR_Msk = 0x80 + // Bit COCPU_SW_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_SW_INT_CLR = 0x80 + // Position of COCPU_SWD_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR_Pos = 0x8 + // Bit mask of COCPU_SWD_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR_Msk = 0x100 + // Bit COCPU_SWD_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR = 0x100 + + // SAR_COCPU_DEBUG: ULP-RISCV debug register + // Position of COCPU_PC field. + SENS_SAR_COCPU_DEBUG_COCPU_PC_Pos = 0x0 + // Bit mask of COCPU_PC field. + SENS_SAR_COCPU_DEBUG_COCPU_PC_Msk = 0x1fff + // Position of COCPU_MEM_VLD field. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_VLD_Pos = 0xd + // Bit mask of COCPU_MEM_VLD field. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_VLD_Msk = 0x2000 + // Bit COCPU_MEM_VLD. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_VLD = 0x2000 + // Position of COCPU_MEM_RDY field. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_RDY_Pos = 0xe + // Bit mask of COCPU_MEM_RDY field. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_RDY_Msk = 0x4000 + // Bit COCPU_MEM_RDY. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_RDY = 0x4000 + // Position of COCPU_MEM_WEN field. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_WEN_Pos = 0xf + // Bit mask of COCPU_MEM_WEN field. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_WEN_Msk = 0x78000 + // Position of COCPU_MEM_ADDR field. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_ADDR_Pos = 0x13 + // Bit mask of COCPU_MEM_ADDR field. + SENS_SAR_COCPU_DEBUG_COCPU_MEM_ADDR_Msk = 0xfff80000 + + // SAR_HALL_CTRL: hall control + // Position of XPD_HALL field. + SENS_SAR_HALL_CTRL_XPD_HALL_Pos = 0x1c + // Bit mask of XPD_HALL field. + SENS_SAR_HALL_CTRL_XPD_HALL_Msk = 0x10000000 + // Bit XPD_HALL. + SENS_SAR_HALL_CTRL_XPD_HALL = 0x10000000 + // Position of XPD_HALL_FORCE field. + SENS_SAR_HALL_CTRL_XPD_HALL_FORCE_Pos = 0x1d + // Bit mask of XPD_HALL_FORCE field. + SENS_SAR_HALL_CTRL_XPD_HALL_FORCE_Msk = 0x20000000 + // Bit XPD_HALL_FORCE. + SENS_SAR_HALL_CTRL_XPD_HALL_FORCE = 0x20000000 + // Position of HALL_PHASE field. + SENS_SAR_HALL_CTRL_HALL_PHASE_Pos = 0x1e + // Bit mask of HALL_PHASE field. + SENS_SAR_HALL_CTRL_HALL_PHASE_Msk = 0x40000000 + // Bit HALL_PHASE. + SENS_SAR_HALL_CTRL_HALL_PHASE = 0x40000000 + // Position of HALL_PHASE_FORCE field. + SENS_SAR_HALL_CTRL_HALL_PHASE_FORCE_Pos = 0x1f + // Bit mask of HALL_PHASE_FORCE field. + SENS_SAR_HALL_CTRL_HALL_PHASE_FORCE_Msk = 0x80000000 + // Bit HALL_PHASE_FORCE. + SENS_SAR_HALL_CTRL_HALL_PHASE_FORCE = 0x80000000 + + // SAR_NOUSE: sar nouse + // Position of SAR_NOUSE field. + SENS_SAR_NOUSE_SAR_NOUSE_Pos = 0x0 + // Bit mask of SAR_NOUSE field. + SENS_SAR_NOUSE_SAR_NOUSE_Msk = 0xffffffff + + // SAR_IO_MUX_CONF: Configure and reset IO MUX + // Position of IOMUX_RESET field. + SENS_SAR_IO_MUX_CONF_IOMUX_RESET_Pos = 0x1e + // Bit mask of IOMUX_RESET field. + SENS_SAR_IO_MUX_CONF_IOMUX_RESET_Msk = 0x40000000 + // Bit IOMUX_RESET. + SENS_SAR_IO_MUX_CONF_IOMUX_RESET = 0x40000000 + // Position of IOMUX_CLK_GATE_EN field. + SENS_SAR_IO_MUX_CONF_IOMUX_CLK_GATE_EN_Pos = 0x1f + // Bit mask of IOMUX_CLK_GATE_EN field. + SENS_SAR_IO_MUX_CONF_IOMUX_CLK_GATE_EN_Msk = 0x80000000 + // Bit IOMUX_CLK_GATE_EN. + SENS_SAR_IO_MUX_CONF_IOMUX_CLK_GATE_EN = 0x80000000 + + // SARDATE: Version Control Register + // Position of SAR_DATE field. + SENS_SARDATE_SAR_DATE_Pos = 0x0 + // Bit mask of SAR_DATE field. + SENS_SARDATE_SAR_DATE_Msk = 0xfffffff +) + +// Constants for SHA: SHA (Secure Hash Algorithm) Accelerator +const ( + // MODE: Defines the algorithm of SHA accelerator + // Position of MODE field. + SHA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + SHA_MODE_MODE_Msk = 0x7 + + // T_STRING: String content register for calculating initial Hash Value (only effective for SHA-512/t) + // Position of T_STRING field. + SHA_T_STRING_T_STRING_Pos = 0x0 + // Bit mask of T_STRING field. + SHA_T_STRING_T_STRING_Msk = 0xffffffff + + // T_LENGTH: String length register for calculating initial Hash Value (only effective for SHA-512/t) + // Position of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Pos = 0x0 + // Bit mask of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Msk = 0x3f + + // DMA_BLOCK_NUM: Block number register (only effective for DMA-SHA) + // Position of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Pos = 0x0 + // Bit mask of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Msk = 0x3f + + // START: Starts the SHA accelerator for Typical SHA operation + // Position of START field. + SHA_START_START_Pos = 0x0 + // Bit mask of START field. + SHA_START_START_Msk = 0x1 + // Bit START. + SHA_START_START = 0x1 + + // CONTINUE: Continues SHA operation (only effective in Typical SHA mode) + // Position of CONTINUE_OP field. + SHA_CONTINUE_CONTINUE_OP_Pos = 0x0 + // Bit mask of CONTINUE_OP field. + SHA_CONTINUE_CONTINUE_OP_Msk = 0x1 + // Bit CONTINUE_OP. + SHA_CONTINUE_CONTINUE_OP = 0x1 + + // BUSY: Indicates if SHA Accelerator is busy or not + // Position of STATE field. + SHA_BUSY_STATE_Pos = 0x0 + // Bit mask of STATE field. + SHA_BUSY_STATE_Msk = 0x1 + // Bit STATE. + SHA_BUSY_STATE = 0x1 + + // DMA_START: Starts the SHA accelerator for DMA-SHA operation + // Position of DMA_START field. + SHA_DMA_START_DMA_START_Pos = 0x0 + // Bit mask of DMA_START field. + SHA_DMA_START_DMA_START_Msk = 0x1 + // Bit DMA_START. + SHA_DMA_START_DMA_START = 0x1 + + // DMA_CONTINUE: Continues SHA operation (only effective in DMA-SHA mode) + // Position of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Pos = 0x0 + // Bit mask of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Msk = 0x1 + // Bit DMA_CONTINUE. + SHA_DMA_CONTINUE_DMA_CONTINUE = 0x1 + + // INT_CLEAR: DMA-SHA interrupt clear register + // Position of CLEAR_INTERRUPT field. + SHA_INT_CLEAR_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + SHA_INT_CLEAR_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + SHA_INT_CLEAR_CLEAR_INTERRUPT = 0x1 + + // INT_ENA: DMA-SHA interrupt enable register + // Position of INTERRUPT_ENA field. + SHA_INT_ENA_INTERRUPT_ENA_Pos = 0x0 + // Bit mask of INTERRUPT_ENA field. + SHA_INT_ENA_INTERRUPT_ENA_Msk = 0x1 + // Bit INTERRUPT_ENA. + SHA_INT_ENA_INTERRUPT_ENA = 0x1 + + // DATE: Version control register + // Position of DATE field. + SHA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SHA_DATE_DATE_Msk = 0x3fffffff + + // H_MEM0: Hash value + // Position of H field. + SHA_H_MEM_H_Pos = 0x0 + // Bit mask of H field. + SHA_H_MEM_H_Msk = 0xffffffff + + // M_MEM0: Message + // Position of M field. + SHA_M_MEM_M_Pos = 0x0 + // Bit mask of M field. + SHA_M_MEM_M_Msk = 0xffffffff +) + +// Constants for SPI0: SPI (Serial Peripheral Interface) Controller 0 +const ( + // CMD: Command control register + // Position of CONF_BITLEN field. + SPI_CMD_CONF_BITLEN_Pos = 0x0 + // Bit mask of CONF_BITLEN field. + SPI_CMD_CONF_BITLEN_Msk = 0x7fffff + // Position of USR field. + SPI_CMD_USR_Pos = 0x18 + // Bit mask of USR field. + SPI_CMD_USR_Msk = 0x1000000 + // Bit USR. + SPI_CMD_USR = 0x1000000 + + // ADDR: Address value + // Position of USR_ADDR_VALUE field. + SPI_ADDR_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of USR_ADDR_VALUE field. + SPI_ADDR_USR_ADDR_VALUE_Msk = 0xffffffff + + // CTRL: SPI control register + // Position of EXT_HOLD_EN field. + SPI_CTRL_EXT_HOLD_EN_Pos = 0x2 + // Bit mask of EXT_HOLD_EN field. + SPI_CTRL_EXT_HOLD_EN_Msk = 0x4 + // Bit EXT_HOLD_EN. + SPI_CTRL_EXT_HOLD_EN = 0x4 + // Position of DUMMY_OUT field. + SPI_CTRL_DUMMY_OUT_Pos = 0x3 + // Bit mask of DUMMY_OUT field. + SPI_CTRL_DUMMY_OUT_Msk = 0x8 + // Bit DUMMY_OUT. + SPI_CTRL_DUMMY_OUT = 0x8 + // Position of FADDR_DUAL field. + SPI_CTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI_CTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI_CTRL_FADDR_DUAL = 0x20 + // Position of FADDR_QUAD field. + SPI_CTRL_FADDR_QUAD_Pos = 0x6 + // Bit mask of FADDR_QUAD field. + SPI_CTRL_FADDR_QUAD_Msk = 0x40 + // Bit FADDR_QUAD. + SPI_CTRL_FADDR_QUAD = 0x40 + // Position of FADDR_OCT field. + SPI_CTRL_FADDR_OCT_Pos = 0x7 + // Bit mask of FADDR_OCT field. + SPI_CTRL_FADDR_OCT_Msk = 0x80 + // Bit FADDR_OCT. + SPI_CTRL_FADDR_OCT = 0x80 + // Position of FCMD_DUAL field. + SPI_CTRL_FCMD_DUAL_Pos = 0x8 + // Bit mask of FCMD_DUAL field. + SPI_CTRL_FCMD_DUAL_Msk = 0x100 + // Bit FCMD_DUAL. + SPI_CTRL_FCMD_DUAL = 0x100 + // Position of FCMD_QUAD field. + SPI_CTRL_FCMD_QUAD_Pos = 0x9 + // Bit mask of FCMD_QUAD field. + SPI_CTRL_FCMD_QUAD_Msk = 0x200 + // Bit FCMD_QUAD. + SPI_CTRL_FCMD_QUAD = 0x200 + // Position of FCMD_OCT field. + SPI_CTRL_FCMD_OCT_Pos = 0xa + // Bit mask of FCMD_OCT field. + SPI_CTRL_FCMD_OCT_Msk = 0x400 + // Bit FCMD_OCT. + SPI_CTRL_FCMD_OCT = 0x400 + // Position of FREAD_DUAL field. + SPI_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI_CTRL_FREAD_DUAL = 0x4000 + // Position of FREAD_QUAD field. + SPI_CTRL_FREAD_QUAD_Pos = 0xf + // Bit mask of FREAD_QUAD field. + SPI_CTRL_FREAD_QUAD_Msk = 0x8000 + // Bit FREAD_QUAD. + SPI_CTRL_FREAD_QUAD = 0x8000 + // Position of FREAD_OCT field. + SPI_CTRL_FREAD_OCT_Pos = 0x10 + // Bit mask of FREAD_OCT field. + SPI_CTRL_FREAD_OCT_Msk = 0x10000 + // Bit FREAD_OCT. + SPI_CTRL_FREAD_OCT = 0x10000 + // Position of Q_POL field. + SPI_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI_CTRL_D_POL = 0x80000 + // Position of WP field. + SPI_CTRL_WP_Pos = 0x15 + // Bit mask of WP field. + SPI_CTRL_WP_Msk = 0x200000 + // Bit WP. + SPI_CTRL_WP = 0x200000 + // Position of RD_BIT_ORDER field. + SPI_CTRL_RD_BIT_ORDER_Pos = 0x19 + // Bit mask of RD_BIT_ORDER field. + SPI_CTRL_RD_BIT_ORDER_Msk = 0x2000000 + // Bit RD_BIT_ORDER. + SPI_CTRL_RD_BIT_ORDER = 0x2000000 + // Position of WR_BIT_ORDER field. + SPI_CTRL_WR_BIT_ORDER_Pos = 0x1a + // Bit mask of WR_BIT_ORDER field. + SPI_CTRL_WR_BIT_ORDER_Msk = 0x4000000 + // Bit WR_BIT_ORDER. + SPI_CTRL_WR_BIT_ORDER = 0x4000000 + + // CTRL1: SPI control register 1 + // Position of CLK_MODE field. + SPI_CTRL1_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI_CTRL1_CLK_MODE_Msk = 0x3 + // Position of CLK_MODE_13 field. + SPI_CTRL1_CLK_MODE_13_Pos = 0x2 + // Bit mask of CLK_MODE_13 field. + SPI_CTRL1_CLK_MODE_13_Msk = 0x4 + // Bit CLK_MODE_13. + SPI_CTRL1_CLK_MODE_13 = 0x4 + // Position of RSCK_DATA_OUT field. + SPI_CTRL1_RSCK_DATA_OUT_Pos = 0x3 + // Bit mask of RSCK_DATA_OUT field. + SPI_CTRL1_RSCK_DATA_OUT_Msk = 0x8 + // Bit RSCK_DATA_OUT. + SPI_CTRL1_RSCK_DATA_OUT = 0x8 + // Position of W16_17_WR_ENA field. + SPI_CTRL1_W16_17_WR_ENA_Pos = 0x4 + // Bit mask of W16_17_WR_ENA field. + SPI_CTRL1_W16_17_WR_ENA_Msk = 0x10 + // Bit W16_17_WR_ENA. + SPI_CTRL1_W16_17_WR_ENA = 0x10 + // Position of CS_HOLD_DELAY field. + SPI_CTRL1_CS_HOLD_DELAY_Pos = 0xe + // Bit mask of CS_HOLD_DELAY field. + SPI_CTRL1_CS_HOLD_DELAY_Msk = 0xfc000 + + // CTRL2: SPI control register 2 + // Position of CS_SETUP_TIME field. + SPI_CTRL2_CS_SETUP_TIME_Pos = 0x0 + // Bit mask of CS_SETUP_TIME field. + SPI_CTRL2_CS_SETUP_TIME_Msk = 0x1fff + // Position of CS_HOLD_TIME field. + SPI_CTRL2_CS_HOLD_TIME_Pos = 0xd + // Bit mask of CS_HOLD_TIME field. + SPI_CTRL2_CS_HOLD_TIME_Msk = 0x3ffe000 + // Position of CS_DELAY_MODE field. + SPI_CTRL2_CS_DELAY_MODE_Pos = 0x1a + // Bit mask of CS_DELAY_MODE field. + SPI_CTRL2_CS_DELAY_MODE_Msk = 0x1c000000 + // Position of CS_DELAY_NUM field. + SPI_CTRL2_CS_DELAY_NUM_Pos = 0x1d + // Bit mask of CS_DELAY_NUM field. + SPI_CTRL2_CS_DELAY_NUM_Msk = 0x60000000 + + // CLOCK: SPI clock control register + // Position of CLKCNT_L field. + SPI_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI_CLOCK_CLKCNT_L_Msk = 0x3f + // Position of CLKCNT_H field. + SPI_CLOCK_CLKCNT_H_Pos = 0x6 + // Bit mask of CLKCNT_H field. + SPI_CLOCK_CLKCNT_H_Msk = 0xfc0 + // Position of CLKCNT_N field. + SPI_CLOCK_CLKCNT_N_Pos = 0xc + // Bit mask of CLKCNT_N field. + SPI_CLOCK_CLKCNT_N_Msk = 0x3f000 + // Position of CLKDIV_PRE field. + SPI_CLOCK_CLKDIV_PRE_Pos = 0x12 + // Bit mask of CLKDIV_PRE field. + SPI_CLOCK_CLKDIV_PRE_Msk = 0x7ffc0000 + // Position of CLK_EQU_SYSCLK field. + SPI_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI USER control register + // Position of DOUTDIN field. + SPI_USER_DOUTDIN_Pos = 0x0 + // Bit mask of DOUTDIN field. + SPI_USER_DOUTDIN_Msk = 0x1 + // Bit DOUTDIN. + SPI_USER_DOUTDIN = 0x1 + // Position of QPI_MODE field. + SPI_USER_QPI_MODE_Pos = 0x3 + // Bit mask of QPI_MODE field. + SPI_USER_QPI_MODE_Msk = 0x8 + // Bit QPI_MODE. + SPI_USER_QPI_MODE = 0x8 + // Position of OPI_MODE field. + SPI_USER_OPI_MODE_Pos = 0x4 + // Bit mask of OPI_MODE field. + SPI_USER_OPI_MODE_Msk = 0x10 + // Bit OPI_MODE. + SPI_USER_OPI_MODE = 0x10 + // Position of TSCK_I_EDGE field. + SPI_USER_TSCK_I_EDGE_Pos = 0x5 + // Bit mask of TSCK_I_EDGE field. + SPI_USER_TSCK_I_EDGE_Msk = 0x20 + // Bit TSCK_I_EDGE. + SPI_USER_TSCK_I_EDGE = 0x20 + // Position of CS_HOLD field. + SPI_USER_CS_HOLD_Pos = 0x6 + // Bit mask of CS_HOLD field. + SPI_USER_CS_HOLD_Msk = 0x40 + // Bit CS_HOLD. + SPI_USER_CS_HOLD = 0x40 + // Position of CS_SETUP field. + SPI_USER_CS_SETUP_Pos = 0x7 + // Bit mask of CS_SETUP field. + SPI_USER_CS_SETUP_Msk = 0x80 + // Bit CS_SETUP. + SPI_USER_CS_SETUP = 0x80 + // Position of RSCK_I_EDGE field. + SPI_USER_RSCK_I_EDGE_Pos = 0x8 + // Bit mask of RSCK_I_EDGE field. + SPI_USER_RSCK_I_EDGE_Msk = 0x100 + // Bit RSCK_I_EDGE. + SPI_USER_RSCK_I_EDGE = 0x100 + // Position of CK_OUT_EDGE field. + SPI_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI_USER_CK_OUT_EDGE = 0x200 + // Position of RD_BYTE_ORDER field. + SPI_USER_RD_BYTE_ORDER_Pos = 0xa + // Bit mask of RD_BYTE_ORDER field. + SPI_USER_RD_BYTE_ORDER_Msk = 0x400 + // Bit RD_BYTE_ORDER. + SPI_USER_RD_BYTE_ORDER = 0x400 + // Position of WR_BYTE_ORDER field. + SPI_USER_WR_BYTE_ORDER_Pos = 0xb + // Bit mask of WR_BYTE_ORDER field. + SPI_USER_WR_BYTE_ORDER_Msk = 0x800 + // Bit WR_BYTE_ORDER. + SPI_USER_WR_BYTE_ORDER = 0x800 + // Position of FWRITE_DUAL field. + SPI_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI_USER_FWRITE_QUAD = 0x2000 + // Position of FWRITE_OCT field. + SPI_USER_FWRITE_OCT_Pos = 0xe + // Bit mask of FWRITE_OCT field. + SPI_USER_FWRITE_OCT_Msk = 0x4000 + // Bit FWRITE_OCT. + SPI_USER_FWRITE_OCT = 0x4000 + // Position of USR_CONF_NXT field. + SPI_USER_USR_CONF_NXT_Pos = 0xf + // Bit mask of USR_CONF_NXT field. + SPI_USER_USR_CONF_NXT_Msk = 0x8000 + // Bit USR_CONF_NXT. + SPI_USER_USR_CONF_NXT = 0x8000 + // Position of SIO field. + SPI_USER_SIO_Pos = 0x10 + // Bit mask of SIO field. + SPI_USER_SIO_Msk = 0x10000 + // Bit SIO. + SPI_USER_SIO = 0x10000 + // Position of USR_HOLD_POL field. + SPI_USER_USR_HOLD_POL_Pos = 0x11 + // Bit mask of USR_HOLD_POL field. + SPI_USER_USR_HOLD_POL_Msk = 0x20000 + // Bit USR_HOLD_POL. + SPI_USER_USR_HOLD_POL = 0x20000 + // Position of USR_DOUT_HOLD field. + SPI_USER_USR_DOUT_HOLD_Pos = 0x12 + // Bit mask of USR_DOUT_HOLD field. + SPI_USER_USR_DOUT_HOLD_Msk = 0x40000 + // Bit USR_DOUT_HOLD. + SPI_USER_USR_DOUT_HOLD = 0x40000 + // Position of USR_DIN_HOLD field. + SPI_USER_USR_DIN_HOLD_Pos = 0x13 + // Bit mask of USR_DIN_HOLD field. + SPI_USER_USR_DIN_HOLD_Msk = 0x80000 + // Bit USR_DIN_HOLD. + SPI_USER_USR_DIN_HOLD = 0x80000 + // Position of USR_DUMMY_HOLD field. + SPI_USER_USR_DUMMY_HOLD_Pos = 0x14 + // Bit mask of USR_DUMMY_HOLD field. + SPI_USER_USR_DUMMY_HOLD_Msk = 0x100000 + // Bit USR_DUMMY_HOLD. + SPI_USER_USR_DUMMY_HOLD = 0x100000 + // Position of USR_ADDR_HOLD field. + SPI_USER_USR_ADDR_HOLD_Pos = 0x15 + // Bit mask of USR_ADDR_HOLD field. + SPI_USER_USR_ADDR_HOLD_Msk = 0x200000 + // Bit USR_ADDR_HOLD. + SPI_USER_USR_ADDR_HOLD = 0x200000 + // Position of USR_CMD_HOLD field. + SPI_USER_USR_CMD_HOLD_Pos = 0x16 + // Bit mask of USR_CMD_HOLD field. + SPI_USER_USR_CMD_HOLD_Msk = 0x400000 + // Bit USR_CMD_HOLD. + SPI_USER_USR_CMD_HOLD = 0x400000 + // Position of USR_PREP_HOLD field. + SPI_USER_USR_PREP_HOLD_Pos = 0x17 + // Bit mask of USR_PREP_HOLD field. + SPI_USER_USR_PREP_HOLD_Msk = 0x800000 + // Bit USR_PREP_HOLD. + SPI_USER_USR_PREP_HOLD = 0x800000 + // Position of USR_MISO_HIGHPART field. + SPI_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI_USER_USR_COMMAND = 0x80000000 + + // USER1: SPI USER control register 1 + // Position of USR_DUMMY_CYCLELEN field. + SPI_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI_USER1_USR_DUMMY_CYCLELEN_Msk = 0xff + // Position of USR_ADDR_BITLEN field. + SPI_USER1_USR_ADDR_BITLEN_Pos = 0x1b + // Bit mask of USR_ADDR_BITLEN field. + SPI_USER1_USR_ADDR_BITLEN_Msk = 0xf8000000 + + // USER2: SPI USER control register 2 + // Position of USR_COMMAND_VALUE field. + SPI_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of USR_COMMAND_BITLEN field. + SPI_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MOSI_DLEN: MOSI length + // Position of USR_MOSI_DBITLEN field. + SPI_MOSI_DLEN_USR_MOSI_DBITLEN_Pos = 0x0 + // Bit mask of USR_MOSI_DBITLEN field. + SPI_MOSI_DLEN_USR_MOSI_DBITLEN_Msk = 0x7fffff + + // MISO_DLEN: MISO length + // Position of USR_MISO_DBITLEN field. + SPI_MISO_DLEN_USR_MISO_DBITLEN_Pos = 0x0 + // Bit mask of USR_MISO_DBITLEN field. + SPI_MISO_DLEN_USR_MISO_DBITLEN_Msk = 0x7fffff + + // MISC: SPI misc register + // Position of CS0_DIS field. + SPI_MISC_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI_MISC_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI_MISC_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI_MISC_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI_MISC_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI_MISC_CS1_DIS = 0x2 + // Position of CS2_DIS field. + SPI_MISC_CS2_DIS_Pos = 0x2 + // Bit mask of CS2_DIS field. + SPI_MISC_CS2_DIS_Msk = 0x4 + // Bit CS2_DIS. + SPI_MISC_CS2_DIS = 0x4 + // Position of CS3_DIS field. + SPI_MISC_CS3_DIS_Pos = 0x3 + // Bit mask of CS3_DIS field. + SPI_MISC_CS3_DIS_Msk = 0x8 + // Bit CS3_DIS. + SPI_MISC_CS3_DIS = 0x8 + // Position of CS4_DIS field. + SPI_MISC_CS4_DIS_Pos = 0x4 + // Bit mask of CS4_DIS field. + SPI_MISC_CS4_DIS_Msk = 0x10 + // Bit CS4_DIS. + SPI_MISC_CS4_DIS = 0x10 + // Position of CS5_DIS field. + SPI_MISC_CS5_DIS_Pos = 0x5 + // Bit mask of CS5_DIS field. + SPI_MISC_CS5_DIS_Msk = 0x20 + // Bit CS5_DIS. + SPI_MISC_CS5_DIS = 0x20 + // Position of CK_DIS field. + SPI_MISC_CK_DIS_Pos = 0x6 + // Bit mask of CK_DIS field. + SPI_MISC_CK_DIS_Msk = 0x40 + // Bit CK_DIS. + SPI_MISC_CK_DIS = 0x40 + // Position of MASTER_CS_POL field. + SPI_MISC_MASTER_CS_POL_Pos = 0x7 + // Bit mask of MASTER_CS_POL field. + SPI_MISC_MASTER_CS_POL_Msk = 0x1f80 + // Position of CLK_DATA_DTR_EN field. + SPI_MISC_CLK_DATA_DTR_EN_Pos = 0x10 + // Bit mask of CLK_DATA_DTR_EN field. + SPI_MISC_CLK_DATA_DTR_EN_Msk = 0x10000 + // Bit CLK_DATA_DTR_EN. + SPI_MISC_CLK_DATA_DTR_EN = 0x10000 + // Position of DATA_DTR_EN field. + SPI_MISC_DATA_DTR_EN_Pos = 0x11 + // Bit mask of DATA_DTR_EN field. + SPI_MISC_DATA_DTR_EN_Msk = 0x20000 + // Bit DATA_DTR_EN. + SPI_MISC_DATA_DTR_EN = 0x20000 + // Position of ADDR_DTR_EN field. + SPI_MISC_ADDR_DTR_EN_Pos = 0x12 + // Bit mask of ADDR_DTR_EN field. + SPI_MISC_ADDR_DTR_EN_Msk = 0x40000 + // Bit ADDR_DTR_EN. + SPI_MISC_ADDR_DTR_EN = 0x40000 + // Position of CMD_DTR_EN field. + SPI_MISC_CMD_DTR_EN_Pos = 0x13 + // Bit mask of CMD_DTR_EN field. + SPI_MISC_CMD_DTR_EN_Msk = 0x80000 + // Bit CMD_DTR_EN. + SPI_MISC_CMD_DTR_EN = 0x80000 + // Position of CD_DATA_SET field. + SPI_MISC_CD_DATA_SET_Pos = 0x14 + // Bit mask of CD_DATA_SET field. + SPI_MISC_CD_DATA_SET_Msk = 0x100000 + // Bit CD_DATA_SET. + SPI_MISC_CD_DATA_SET = 0x100000 + // Position of CD_DUMMY_SET field. + SPI_MISC_CD_DUMMY_SET_Pos = 0x15 + // Bit mask of CD_DUMMY_SET field. + SPI_MISC_CD_DUMMY_SET_Msk = 0x200000 + // Bit CD_DUMMY_SET. + SPI_MISC_CD_DUMMY_SET = 0x200000 + // Position of CD_ADDR_SET field. + SPI_MISC_CD_ADDR_SET_Pos = 0x16 + // Bit mask of CD_ADDR_SET field. + SPI_MISC_CD_ADDR_SET_Msk = 0x400000 + // Bit CD_ADDR_SET. + SPI_MISC_CD_ADDR_SET = 0x400000 + // Position of SLAVE_CS_POL field. + SPI_MISC_SLAVE_CS_POL_Pos = 0x17 + // Bit mask of SLAVE_CS_POL field. + SPI_MISC_SLAVE_CS_POL_Msk = 0x800000 + // Bit SLAVE_CS_POL. + SPI_MISC_SLAVE_CS_POL = 0x800000 + // Position of DQS_IDLE_EDGE field. + SPI_MISC_DQS_IDLE_EDGE_Pos = 0x18 + // Bit mask of DQS_IDLE_EDGE field. + SPI_MISC_DQS_IDLE_EDGE_Msk = 0x1000000 + // Bit DQS_IDLE_EDGE. + SPI_MISC_DQS_IDLE_EDGE = 0x1000000 + // Position of CD_CMD_SET field. + SPI_MISC_CD_CMD_SET_Pos = 0x19 + // Bit mask of CD_CMD_SET field. + SPI_MISC_CD_CMD_SET_Msk = 0x2000000 + // Bit CD_CMD_SET. + SPI_MISC_CD_CMD_SET = 0x2000000 + // Position of CD_IDLE_EDGE field. + SPI_MISC_CD_IDLE_EDGE_Pos = 0x1a + // Bit mask of CD_IDLE_EDGE field. + SPI_MISC_CD_IDLE_EDGE_Msk = 0x4000000 + // Bit CD_IDLE_EDGE. + SPI_MISC_CD_IDLE_EDGE = 0x4000000 + // Position of CK_IDLE_EDGE field. + SPI_MISC_CK_IDLE_EDGE_Pos = 0x1d + // Bit mask of CK_IDLE_EDGE field. + SPI_MISC_CK_IDLE_EDGE_Msk = 0x20000000 + // Bit CK_IDLE_EDGE. + SPI_MISC_CK_IDLE_EDGE = 0x20000000 + // Position of CS_KEEP_ACTIVE field. + SPI_MISC_CS_KEEP_ACTIVE_Pos = 0x1e + // Bit mask of CS_KEEP_ACTIVE field. + SPI_MISC_CS_KEEP_ACTIVE_Msk = 0x40000000 + // Bit CS_KEEP_ACTIVE. + SPI_MISC_CS_KEEP_ACTIVE = 0x40000000 + // Position of QUAD_DIN_PIN_SWAP field. + SPI_MISC_QUAD_DIN_PIN_SWAP_Pos = 0x1f + // Bit mask of QUAD_DIN_PIN_SWAP field. + SPI_MISC_QUAD_DIN_PIN_SWAP_Msk = 0x80000000 + // Bit QUAD_DIN_PIN_SWAP. + SPI_MISC_QUAD_DIN_PIN_SWAP = 0x80000000 + + // SLAVE: SPI slave control register + // Position of TRANS_DONE field. + SPI_SLAVE_TRANS_DONE_Pos = 0x4 + // Bit mask of TRANS_DONE field. + SPI_SLAVE_TRANS_DONE_Msk = 0x10 + // Bit TRANS_DONE. + SPI_SLAVE_TRANS_DONE = 0x10 + // Position of INT_RD_BUF_DONE_EN field. + SPI_SLAVE_INT_RD_BUF_DONE_EN_Pos = 0x5 + // Bit mask of INT_RD_BUF_DONE_EN field. + SPI_SLAVE_INT_RD_BUF_DONE_EN_Msk = 0x20 + // Bit INT_RD_BUF_DONE_EN. + SPI_SLAVE_INT_RD_BUF_DONE_EN = 0x20 + // Position of INT_WR_BUF_DONE_EN field. + SPI_SLAVE_INT_WR_BUF_DONE_EN_Pos = 0x6 + // Bit mask of INT_WR_BUF_DONE_EN field. + SPI_SLAVE_INT_WR_BUF_DONE_EN_Msk = 0x40 + // Bit INT_WR_BUF_DONE_EN. + SPI_SLAVE_INT_WR_BUF_DONE_EN = 0x40 + // Position of INT_RD_DMA_DONE_EN field. + SPI_SLAVE_INT_RD_DMA_DONE_EN_Pos = 0x7 + // Bit mask of INT_RD_DMA_DONE_EN field. + SPI_SLAVE_INT_RD_DMA_DONE_EN_Msk = 0x80 + // Bit INT_RD_DMA_DONE_EN. + SPI_SLAVE_INT_RD_DMA_DONE_EN = 0x80 + // Position of INT_WR_DMA_DONE_EN field. + SPI_SLAVE_INT_WR_DMA_DONE_EN_Pos = 0x8 + // Bit mask of INT_WR_DMA_DONE_EN field. + SPI_SLAVE_INT_WR_DMA_DONE_EN_Msk = 0x100 + // Bit INT_WR_DMA_DONE_EN. + SPI_SLAVE_INT_WR_DMA_DONE_EN = 0x100 + // Position of INT_TRANS_DONE_EN field. + SPI_SLAVE_INT_TRANS_DONE_EN_Pos = 0x9 + // Bit mask of INT_TRANS_DONE_EN field. + SPI_SLAVE_INT_TRANS_DONE_EN_Msk = 0x200 + // Bit INT_TRANS_DONE_EN. + SPI_SLAVE_INT_TRANS_DONE_EN = 0x200 + // Position of INT_DMA_SEG_TRANS_EN field. + SPI_SLAVE_INT_DMA_SEG_TRANS_EN_Pos = 0xa + // Bit mask of INT_DMA_SEG_TRANS_EN field. + SPI_SLAVE_INT_DMA_SEG_TRANS_EN_Msk = 0x400 + // Bit INT_DMA_SEG_TRANS_EN. + SPI_SLAVE_INT_DMA_SEG_TRANS_EN = 0x400 + // Position of SEG_MAGIC_ERR_INT_EN field. + SPI_SLAVE_SEG_MAGIC_ERR_INT_EN_Pos = 0xb + // Bit mask of SEG_MAGIC_ERR_INT_EN field. + SPI_SLAVE_SEG_MAGIC_ERR_INT_EN_Msk = 0x800 + // Bit SEG_MAGIC_ERR_INT_EN. + SPI_SLAVE_SEG_MAGIC_ERR_INT_EN = 0x800 + // Position of TRANS_CNT field. + SPI_SLAVE_TRANS_CNT_Pos = 0x17 + // Bit mask of TRANS_CNT field. + SPI_SLAVE_TRANS_CNT_Msk = 0x7800000 + // Position of TRANS_DONE_AUTO_CLR_EN field. + SPI_SLAVE_TRANS_DONE_AUTO_CLR_EN_Pos = 0x1d + // Bit mask of TRANS_DONE_AUTO_CLR_EN field. + SPI_SLAVE_TRANS_DONE_AUTO_CLR_EN_Msk = 0x20000000 + // Bit TRANS_DONE_AUTO_CLR_EN. + SPI_SLAVE_TRANS_DONE_AUTO_CLR_EN = 0x20000000 + // Position of MODE field. + SPI_SLAVE_MODE_Pos = 0x1e + // Bit mask of MODE field. + SPI_SLAVE_MODE_Msk = 0x40000000 + // Bit MODE. + SPI_SLAVE_MODE = 0x40000000 + // Position of SOFT_RESET field. + SPI_SLAVE_SOFT_RESET_Pos = 0x1f + // Bit mask of SOFT_RESET field. + SPI_SLAVE_SOFT_RESET_Msk = 0x80000000 + // Bit SOFT_RESET. + SPI_SLAVE_SOFT_RESET = 0x80000000 + + // SLAVE1: SPI slave control register 1 + // Position of SLV_ADDR_ERR_CLR field. + SPI_SLAVE1_SLV_ADDR_ERR_CLR_Pos = 0xa + // Bit mask of SLV_ADDR_ERR_CLR field. + SPI_SLAVE1_SLV_ADDR_ERR_CLR_Msk = 0x400 + // Bit SLV_ADDR_ERR_CLR. + SPI_SLAVE1_SLV_ADDR_ERR_CLR = 0x400 + // Position of SLV_CMD_ERR_CLR field. + SPI_SLAVE1_SLV_CMD_ERR_CLR_Pos = 0xb + // Bit mask of SLV_CMD_ERR_CLR field. + SPI_SLAVE1_SLV_CMD_ERR_CLR_Msk = 0x800 + // Bit SLV_CMD_ERR_CLR. + SPI_SLAVE1_SLV_CMD_ERR_CLR = 0x800 + // Position of SLV_NO_QPI_EN field. + SPI_SLAVE1_SLV_NO_QPI_EN_Pos = 0xc + // Bit mask of SLV_NO_QPI_EN field. + SPI_SLAVE1_SLV_NO_QPI_EN_Msk = 0x1000 + // Bit SLV_NO_QPI_EN. + SPI_SLAVE1_SLV_NO_QPI_EN = 0x1000 + // Position of SLV_ADDR_ERR field. + SPI_SLAVE1_SLV_ADDR_ERR_Pos = 0xd + // Bit mask of SLV_ADDR_ERR field. + SPI_SLAVE1_SLV_ADDR_ERR_Msk = 0x2000 + // Bit SLV_ADDR_ERR. + SPI_SLAVE1_SLV_ADDR_ERR = 0x2000 + // Position of SLV_CMD_ERR field. + SPI_SLAVE1_SLV_CMD_ERR_Pos = 0xe + // Bit mask of SLV_CMD_ERR field. + SPI_SLAVE1_SLV_CMD_ERR_Msk = 0x4000 + // Bit SLV_CMD_ERR. + SPI_SLAVE1_SLV_CMD_ERR = 0x4000 + // Position of SLV_WR_DMA_DONE field. + SPI_SLAVE1_SLV_WR_DMA_DONE_Pos = 0xf + // Bit mask of SLV_WR_DMA_DONE field. + SPI_SLAVE1_SLV_WR_DMA_DONE_Msk = 0x8000 + // Bit SLV_WR_DMA_DONE. + SPI_SLAVE1_SLV_WR_DMA_DONE = 0x8000 + // Position of SLV_LAST_COMMAND field. + SPI_SLAVE1_SLV_LAST_COMMAND_Pos = 0x10 + // Bit mask of SLV_LAST_COMMAND field. + SPI_SLAVE1_SLV_LAST_COMMAND_Msk = 0xff0000 + // Position of SLV_LAST_ADDR field. + SPI_SLAVE1_SLV_LAST_ADDR_Pos = 0x18 + // Bit mask of SLV_LAST_ADDR field. + SPI_SLAVE1_SLV_LAST_ADDR_Msk = 0xff000000 + + // SLV_WRBUF_DLEN: SPI slave Wr_BUF interrupt and CONF control register + // Position of SLV_WR_BUF_DONE field. + SPI_SLV_WRBUF_DLEN_SLV_WR_BUF_DONE_Pos = 0x18 + // Bit mask of SLV_WR_BUF_DONE field. + SPI_SLV_WRBUF_DLEN_SLV_WR_BUF_DONE_Msk = 0x1000000 + // Bit SLV_WR_BUF_DONE. + SPI_SLV_WRBUF_DLEN_SLV_WR_BUF_DONE = 0x1000000 + // Position of CONF_BASE_BITLEN field. + SPI_SLV_WRBUF_DLEN_CONF_BASE_BITLEN_Pos = 0x19 + // Bit mask of CONF_BASE_BITLEN field. + SPI_SLV_WRBUF_DLEN_CONF_BASE_BITLEN_Msk = 0xfe000000 + + // SLV_RDBUF_DLEN: SPI magic error and slave control register + // Position of SLV_DMA_RD_BYTELEN field. + SPI_SLV_RDBUF_DLEN_SLV_DMA_RD_BYTELEN_Pos = 0x0 + // Bit mask of SLV_DMA_RD_BYTELEN field. + SPI_SLV_RDBUF_DLEN_SLV_DMA_RD_BYTELEN_Msk = 0xfffff + // Position of SLV_RD_BUF_DONE field. + SPI_SLV_RDBUF_DLEN_SLV_RD_BUF_DONE_Pos = 0x18 + // Bit mask of SLV_RD_BUF_DONE field. + SPI_SLV_RDBUF_DLEN_SLV_RD_BUF_DONE_Msk = 0x1000000 + // Bit SLV_RD_BUF_DONE. + SPI_SLV_RDBUF_DLEN_SLV_RD_BUF_DONE = 0x1000000 + // Position of SEG_MAGIC_ERR field. + SPI_SLV_RDBUF_DLEN_SEG_MAGIC_ERR_Pos = 0x19 + // Bit mask of SEG_MAGIC_ERR field. + SPI_SLV_RDBUF_DLEN_SEG_MAGIC_ERR_Msk = 0x2000000 + // Bit SEG_MAGIC_ERR. + SPI_SLV_RDBUF_DLEN_SEG_MAGIC_ERR = 0x2000000 + + // SLV_RD_BYTE: SPI interrupt control register + // Position of SLV_DATA_BYTELEN field. + SPI_SLV_RD_BYTE_SLV_DATA_BYTELEN_Pos = 0x0 + // Bit mask of SLV_DATA_BYTELEN field. + SPI_SLV_RD_BYTE_SLV_DATA_BYTELEN_Msk = 0xfffff + // Position of SLV_RDDMA_BYTELEN_EN field. + SPI_SLV_RD_BYTE_SLV_RDDMA_BYTELEN_EN_Pos = 0x14 + // Bit mask of SLV_RDDMA_BYTELEN_EN field. + SPI_SLV_RD_BYTE_SLV_RDDMA_BYTELEN_EN_Msk = 0x100000 + // Bit SLV_RDDMA_BYTELEN_EN. + SPI_SLV_RD_BYTE_SLV_RDDMA_BYTELEN_EN = 0x100000 + // Position of SLV_WRDMA_BYTELEN_EN field. + SPI_SLV_RD_BYTE_SLV_WRDMA_BYTELEN_EN_Pos = 0x15 + // Bit mask of SLV_WRDMA_BYTELEN_EN field. + SPI_SLV_RD_BYTE_SLV_WRDMA_BYTELEN_EN_Msk = 0x200000 + // Bit SLV_WRDMA_BYTELEN_EN. + SPI_SLV_RD_BYTE_SLV_WRDMA_BYTELEN_EN = 0x200000 + // Position of SLV_RDBUF_BYTELEN_EN field. + SPI_SLV_RD_BYTE_SLV_RDBUF_BYTELEN_EN_Pos = 0x16 + // Bit mask of SLV_RDBUF_BYTELEN_EN field. + SPI_SLV_RD_BYTE_SLV_RDBUF_BYTELEN_EN_Msk = 0x400000 + // Bit SLV_RDBUF_BYTELEN_EN. + SPI_SLV_RD_BYTE_SLV_RDBUF_BYTELEN_EN = 0x400000 + // Position of SLV_WRBUF_BYTELEN_EN field. + SPI_SLV_RD_BYTE_SLV_WRBUF_BYTELEN_EN_Pos = 0x17 + // Bit mask of SLV_WRBUF_BYTELEN_EN field. + SPI_SLV_RD_BYTE_SLV_WRBUF_BYTELEN_EN_Msk = 0x800000 + // Bit SLV_WRBUF_BYTELEN_EN. + SPI_SLV_RD_BYTE_SLV_WRBUF_BYTELEN_EN = 0x800000 + // Position of DMA_SEG_MAGIC_VALUE field. + SPI_SLV_RD_BYTE_DMA_SEG_MAGIC_VALUE_Pos = 0x18 + // Bit mask of DMA_SEG_MAGIC_VALUE field. + SPI_SLV_RD_BYTE_DMA_SEG_MAGIC_VALUE_Msk = 0xf000000 + // Position of SLV_RD_DMA_DONE field. + SPI_SLV_RD_BYTE_SLV_RD_DMA_DONE_Pos = 0x1e + // Bit mask of SLV_RD_DMA_DONE field. + SPI_SLV_RD_BYTE_SLV_RD_DMA_DONE_Msk = 0x40000000 + // Bit SLV_RD_DMA_DONE. + SPI_SLV_RD_BYTE_SLV_RD_DMA_DONE = 0x40000000 + // Position of USR_CONF field. + SPI_SLV_RD_BYTE_USR_CONF_Pos = 0x1f + // Bit mask of USR_CONF field. + SPI_SLV_RD_BYTE_USR_CONF_Msk = 0x80000000 + // Bit USR_CONF. + SPI_SLV_RD_BYTE_USR_CONF = 0x80000000 + + // FSM: SPI master status and DMA read byte control register + // Position of ST field. + SPI_FSM_ST_Pos = 0x0 + // Bit mask of ST field. + SPI_FSM_ST_Msk = 0xf + // Position of MST_DMA_RD_BYTELEN field. + SPI_FSM_MST_DMA_RD_BYTELEN_Pos = 0xc + // Bit mask of MST_DMA_RD_BYTELEN field. + SPI_FSM_MST_DMA_RD_BYTELEN_Msk = 0xfffff000 + + // HOLD: SPI hold register + // Position of INT_HOLD_ENA field. + SPI_HOLD_INT_HOLD_ENA_Pos = 0x0 + // Bit mask of INT_HOLD_ENA field. + SPI_HOLD_INT_HOLD_ENA_Msk = 0x3 + // Position of VAL field. + SPI_HOLD_VAL_Pos = 0x2 + // Bit mask of VAL field. + SPI_HOLD_VAL_Msk = 0x4 + // Bit VAL. + SPI_HOLD_VAL = 0x4 + // Position of OUT_EN field. + SPI_HOLD_OUT_EN_Pos = 0x3 + // Bit mask of OUT_EN field. + SPI_HOLD_OUT_EN_Msk = 0x8 + // Bit OUT_EN. + SPI_HOLD_OUT_EN = 0x8 + // Position of OUT_TIME field. + SPI_HOLD_OUT_TIME_Pos = 0x4 + // Bit mask of OUT_TIME field. + SPI_HOLD_OUT_TIME_Msk = 0x70 + // Position of DMA_SEG_TRANS_DONE field. + SPI_HOLD_DMA_SEG_TRANS_DONE_Pos = 0x7 + // Bit mask of DMA_SEG_TRANS_DONE field. + SPI_HOLD_DMA_SEG_TRANS_DONE_Msk = 0x80 + // Bit DMA_SEG_TRANS_DONE. + SPI_HOLD_DMA_SEG_TRANS_DONE = 0x80 + + // DMA_CONF: SPI DMA control register + // Position of IN_RST field. + SPI_DMA_CONF_IN_RST_Pos = 0x2 + // Bit mask of IN_RST field. + SPI_DMA_CONF_IN_RST_Msk = 0x4 + // Bit IN_RST. + SPI_DMA_CONF_IN_RST = 0x4 + // Position of OUT_RST field. + SPI_DMA_CONF_OUT_RST_Pos = 0x3 + // Bit mask of OUT_RST field. + SPI_DMA_CONF_OUT_RST_Msk = 0x8 + // Bit OUT_RST. + SPI_DMA_CONF_OUT_RST = 0x8 + // Position of AHBM_FIFO_RST field. + SPI_DMA_CONF_AHBM_FIFO_RST_Pos = 0x4 + // Bit mask of AHBM_FIFO_RST field. + SPI_DMA_CONF_AHBM_FIFO_RST_Msk = 0x10 + // Bit AHBM_FIFO_RST. + SPI_DMA_CONF_AHBM_FIFO_RST = 0x10 + // Position of AHBM_RST field. + SPI_DMA_CONF_AHBM_RST_Pos = 0x5 + // Bit mask of AHBM_RST field. + SPI_DMA_CONF_AHBM_RST_Msk = 0x20 + // Bit AHBM_RST. + SPI_DMA_CONF_AHBM_RST = 0x20 + // Position of IN_LOOP_TEST field. + SPI_DMA_CONF_IN_LOOP_TEST_Pos = 0x6 + // Bit mask of IN_LOOP_TEST field. + SPI_DMA_CONF_IN_LOOP_TEST_Msk = 0x40 + // Bit IN_LOOP_TEST. + SPI_DMA_CONF_IN_LOOP_TEST = 0x40 + // Position of OUT_LOOP_TEST field. + SPI_DMA_CONF_OUT_LOOP_TEST_Pos = 0x7 + // Bit mask of OUT_LOOP_TEST field. + SPI_DMA_CONF_OUT_LOOP_TEST_Msk = 0x80 + // Bit OUT_LOOP_TEST. + SPI_DMA_CONF_OUT_LOOP_TEST = 0x80 + // Position of OUT_AUTO_WRBACK field. + SPI_DMA_CONF_OUT_AUTO_WRBACK_Pos = 0x8 + // Bit mask of OUT_AUTO_WRBACK field. + SPI_DMA_CONF_OUT_AUTO_WRBACK_Msk = 0x100 + // Bit OUT_AUTO_WRBACK. + SPI_DMA_CONF_OUT_AUTO_WRBACK = 0x100 + // Position of OUT_EOF_MODE field. + SPI_DMA_CONF_OUT_EOF_MODE_Pos = 0x9 + // Bit mask of OUT_EOF_MODE field. + SPI_DMA_CONF_OUT_EOF_MODE_Msk = 0x200 + // Bit OUT_EOF_MODE. + SPI_DMA_CONF_OUT_EOF_MODE = 0x200 + // Position of OUTDSCR_BURST_EN field. + SPI_DMA_CONF_OUTDSCR_BURST_EN_Pos = 0xa + // Bit mask of OUTDSCR_BURST_EN field. + SPI_DMA_CONF_OUTDSCR_BURST_EN_Msk = 0x400 + // Bit OUTDSCR_BURST_EN. + SPI_DMA_CONF_OUTDSCR_BURST_EN = 0x400 + // Position of INDSCR_BURST_EN field. + SPI_DMA_CONF_INDSCR_BURST_EN_Pos = 0xb + // Bit mask of INDSCR_BURST_EN field. + SPI_DMA_CONF_INDSCR_BURST_EN_Msk = 0x800 + // Bit INDSCR_BURST_EN. + SPI_DMA_CONF_INDSCR_BURST_EN = 0x800 + // Position of OUT_DATA_BURST_EN field. + SPI_DMA_CONF_OUT_DATA_BURST_EN_Pos = 0xc + // Bit mask of OUT_DATA_BURST_EN field. + SPI_DMA_CONF_OUT_DATA_BURST_EN_Msk = 0x1000 + // Bit OUT_DATA_BURST_EN. + SPI_DMA_CONF_OUT_DATA_BURST_EN = 0x1000 + // Position of MEM_TRANS_EN field. + SPI_DMA_CONF_MEM_TRANS_EN_Pos = 0xd + // Bit mask of MEM_TRANS_EN field. + SPI_DMA_CONF_MEM_TRANS_EN_Msk = 0x2000 + // Bit MEM_TRANS_EN. + SPI_DMA_CONF_MEM_TRANS_EN = 0x2000 + // Position of DMA_RX_STOP field. + SPI_DMA_CONF_DMA_RX_STOP_Pos = 0xe + // Bit mask of DMA_RX_STOP field. + SPI_DMA_CONF_DMA_RX_STOP_Msk = 0x4000 + // Bit DMA_RX_STOP. + SPI_DMA_CONF_DMA_RX_STOP = 0x4000 + // Position of DMA_TX_STOP field. + SPI_DMA_CONF_DMA_TX_STOP_Pos = 0xf + // Bit mask of DMA_TX_STOP field. + SPI_DMA_CONF_DMA_TX_STOP_Msk = 0x8000 + // Bit DMA_TX_STOP. + SPI_DMA_CONF_DMA_TX_STOP = 0x8000 + // Position of DMA_CONTINUE field. + SPI_DMA_CONF_DMA_CONTINUE_Pos = 0x10 + // Bit mask of DMA_CONTINUE field. + SPI_DMA_CONF_DMA_CONTINUE_Msk = 0x10000 + // Bit DMA_CONTINUE. + SPI_DMA_CONF_DMA_CONTINUE = 0x10000 + // Position of SLV_LAST_SEG_POP_CLR field. + SPI_DMA_CONF_SLV_LAST_SEG_POP_CLR_Pos = 0x11 + // Bit mask of SLV_LAST_SEG_POP_CLR field. + SPI_DMA_CONF_SLV_LAST_SEG_POP_CLR_Msk = 0x20000 + // Bit SLV_LAST_SEG_POP_CLR. + SPI_DMA_CONF_SLV_LAST_SEG_POP_CLR = 0x20000 + // Position of DMA_SLV_SEG_TRANS_EN field. + SPI_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Pos = 0x12 + // Bit mask of DMA_SLV_SEG_TRANS_EN field. + SPI_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Msk = 0x40000 + // Bit DMA_SLV_SEG_TRANS_EN. + SPI_DMA_CONF_DMA_SLV_SEG_TRANS_EN = 0x40000 + // Position of SLV_RX_SEG_TRANS_CLR_EN field. + SPI_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Pos = 0x13 + // Bit mask of SLV_RX_SEG_TRANS_CLR_EN field. + SPI_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Msk = 0x80000 + // Bit SLV_RX_SEG_TRANS_CLR_EN. + SPI_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN = 0x80000 + // Position of SLV_TX_SEG_TRANS_CLR_EN field. + SPI_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Pos = 0x14 + // Bit mask of SLV_TX_SEG_TRANS_CLR_EN field. + SPI_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Msk = 0x100000 + // Bit SLV_TX_SEG_TRANS_CLR_EN. + SPI_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN = 0x100000 + // Position of RX_EOF_EN field. + SPI_DMA_CONF_RX_EOF_EN_Pos = 0x15 + // Bit mask of RX_EOF_EN field. + SPI_DMA_CONF_RX_EOF_EN_Msk = 0x200000 + // Bit RX_EOF_EN. + SPI_DMA_CONF_RX_EOF_EN = 0x200000 + // Position of DMA_INFIFO_FULL_CLR field. + SPI_DMA_CONF_DMA_INFIFO_FULL_CLR_Pos = 0x16 + // Bit mask of DMA_INFIFO_FULL_CLR field. + SPI_DMA_CONF_DMA_INFIFO_FULL_CLR_Msk = 0x400000 + // Bit DMA_INFIFO_FULL_CLR. + SPI_DMA_CONF_DMA_INFIFO_FULL_CLR = 0x400000 + // Position of DMA_OUTFIFO_EMPTY_CLR field. + SPI_DMA_CONF_DMA_OUTFIFO_EMPTY_CLR_Pos = 0x17 + // Bit mask of DMA_OUTFIFO_EMPTY_CLR field. + SPI_DMA_CONF_DMA_OUTFIFO_EMPTY_CLR_Msk = 0x800000 + // Bit DMA_OUTFIFO_EMPTY_CLR. + SPI_DMA_CONF_DMA_OUTFIFO_EMPTY_CLR = 0x800000 + // Position of EXT_MEM_BK_SIZE field. + SPI_DMA_CONF_EXT_MEM_BK_SIZE_Pos = 0x1a + // Bit mask of EXT_MEM_BK_SIZE field. + SPI_DMA_CONF_EXT_MEM_BK_SIZE_Msk = 0xc000000 + // Position of DMA_SEG_TRANS_CLR field. + SPI_DMA_CONF_DMA_SEG_TRANS_CLR_Pos = 0x1c + // Bit mask of DMA_SEG_TRANS_CLR field. + SPI_DMA_CONF_DMA_SEG_TRANS_CLR_Msk = 0x10000000 + // Bit DMA_SEG_TRANS_CLR. + SPI_DMA_CONF_DMA_SEG_TRANS_CLR = 0x10000000 + + // DMA_OUT_LINK: SPI DMA TX link configuration + // Position of OUTLINK_ADDR field. + SPI_DMA_OUT_LINK_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + SPI_DMA_OUT_LINK_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + SPI_DMA_OUT_LINK_OUTLINK_STOP_Pos = 0x1c + // Bit mask of OUTLINK_STOP field. + SPI_DMA_OUT_LINK_OUTLINK_STOP_Msk = 0x10000000 + // Bit OUTLINK_STOP. + SPI_DMA_OUT_LINK_OUTLINK_STOP = 0x10000000 + // Position of OUTLINK_START field. + SPI_DMA_OUT_LINK_OUTLINK_START_Pos = 0x1d + // Bit mask of OUTLINK_START field. + SPI_DMA_OUT_LINK_OUTLINK_START_Msk = 0x20000000 + // Bit OUTLINK_START. + SPI_DMA_OUT_LINK_OUTLINK_START = 0x20000000 + // Position of OUTLINK_RESTART field. + SPI_DMA_OUT_LINK_OUTLINK_RESTART_Pos = 0x1e + // Bit mask of OUTLINK_RESTART field. + SPI_DMA_OUT_LINK_OUTLINK_RESTART_Msk = 0x40000000 + // Bit OUTLINK_RESTART. + SPI_DMA_OUT_LINK_OUTLINK_RESTART = 0x40000000 + // Position of DMA_TX_ENA field. + SPI_DMA_OUT_LINK_DMA_TX_ENA_Pos = 0x1f + // Bit mask of DMA_TX_ENA field. + SPI_DMA_OUT_LINK_DMA_TX_ENA_Msk = 0x80000000 + // Bit DMA_TX_ENA. + SPI_DMA_OUT_LINK_DMA_TX_ENA = 0x80000000 + + // DMA_IN_LINK: SPI DMA RX link configuration + // Position of INLINK_ADDR field. + SPI_DMA_IN_LINK_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + SPI_DMA_IN_LINK_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + SPI_DMA_IN_LINK_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + SPI_DMA_IN_LINK_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + SPI_DMA_IN_LINK_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + SPI_DMA_IN_LINK_INLINK_STOP_Pos = 0x1c + // Bit mask of INLINK_STOP field. + SPI_DMA_IN_LINK_INLINK_STOP_Msk = 0x10000000 + // Bit INLINK_STOP. + SPI_DMA_IN_LINK_INLINK_STOP = 0x10000000 + // Position of INLINK_START field. + SPI_DMA_IN_LINK_INLINK_START_Pos = 0x1d + // Bit mask of INLINK_START field. + SPI_DMA_IN_LINK_INLINK_START_Msk = 0x20000000 + // Bit INLINK_START. + SPI_DMA_IN_LINK_INLINK_START = 0x20000000 + // Position of INLINK_RESTART field. + SPI_DMA_IN_LINK_INLINK_RESTART_Pos = 0x1e + // Bit mask of INLINK_RESTART field. + SPI_DMA_IN_LINK_INLINK_RESTART_Msk = 0x40000000 + // Bit INLINK_RESTART. + SPI_DMA_IN_LINK_INLINK_RESTART = 0x40000000 + // Position of DMA_RX_ENA field. + SPI_DMA_IN_LINK_DMA_RX_ENA_Pos = 0x1f + // Bit mask of DMA_RX_ENA field. + SPI_DMA_IN_LINK_DMA_RX_ENA_Msk = 0x80000000 + // Bit DMA_RX_ENA. + SPI_DMA_IN_LINK_DMA_RX_ENA = 0x80000000 + + // DMA_INT_ENA: SPI DMA interrupt enable register + // Position of INLINK_DSCR_EMPTY_INT_ENA field. + SPI_DMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA_Pos = 0x0 + // Bit mask of INLINK_DSCR_EMPTY_INT_ENA field. + SPI_DMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA_Msk = 0x1 + // Bit INLINK_DSCR_EMPTY_INT_ENA. + SPI_DMA_INT_ENA_INLINK_DSCR_EMPTY_INT_ENA = 0x1 + // Position of OUTLINK_DSCR_ERROR_INT_ENA field. + SPI_DMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA_Pos = 0x1 + // Bit mask of OUTLINK_DSCR_ERROR_INT_ENA field. + SPI_DMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA_Msk = 0x2 + // Bit OUTLINK_DSCR_ERROR_INT_ENA. + SPI_DMA_INT_ENA_OUTLINK_DSCR_ERROR_INT_ENA = 0x2 + // Position of INLINK_DSCR_ERROR_INT_ENA field. + SPI_DMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA_Pos = 0x2 + // Bit mask of INLINK_DSCR_ERROR_INT_ENA field. + SPI_DMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA_Msk = 0x4 + // Bit INLINK_DSCR_ERROR_INT_ENA. + SPI_DMA_INT_ENA_INLINK_DSCR_ERROR_INT_ENA = 0x4 + // Position of IN_DONE_INT_ENA field. + SPI_DMA_INT_ENA_IN_DONE_INT_ENA_Pos = 0x3 + // Bit mask of IN_DONE_INT_ENA field. + SPI_DMA_INT_ENA_IN_DONE_INT_ENA_Msk = 0x8 + // Bit IN_DONE_INT_ENA. + SPI_DMA_INT_ENA_IN_DONE_INT_ENA = 0x8 + // Position of IN_ERR_EOF_INT_ENA field. + SPI_DMA_INT_ENA_IN_ERR_EOF_INT_ENA_Pos = 0x4 + // Bit mask of IN_ERR_EOF_INT_ENA field. + SPI_DMA_INT_ENA_IN_ERR_EOF_INT_ENA_Msk = 0x10 + // Bit IN_ERR_EOF_INT_ENA. + SPI_DMA_INT_ENA_IN_ERR_EOF_INT_ENA = 0x10 + // Position of IN_SUC_EOF_INT_ENA field. + SPI_DMA_INT_ENA_IN_SUC_EOF_INT_ENA_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_ENA field. + SPI_DMA_INT_ENA_IN_SUC_EOF_INT_ENA_Msk = 0x20 + // Bit IN_SUC_EOF_INT_ENA. + SPI_DMA_INT_ENA_IN_SUC_EOF_INT_ENA = 0x20 + // Position of OUT_DONE_INT_ENA field. + SPI_DMA_INT_ENA_OUT_DONE_INT_ENA_Pos = 0x6 + // Bit mask of OUT_DONE_INT_ENA field. + SPI_DMA_INT_ENA_OUT_DONE_INT_ENA_Msk = 0x40 + // Bit OUT_DONE_INT_ENA. + SPI_DMA_INT_ENA_OUT_DONE_INT_ENA = 0x40 + // Position of OUT_EOF_INT_ENA field. + SPI_DMA_INT_ENA_OUT_EOF_INT_ENA_Pos = 0x7 + // Bit mask of OUT_EOF_INT_ENA field. + SPI_DMA_INT_ENA_OUT_EOF_INT_ENA_Msk = 0x80 + // Bit OUT_EOF_INT_ENA. + SPI_DMA_INT_ENA_OUT_EOF_INT_ENA = 0x80 + // Position of OUT_TOTAL_EOF_INT_ENA field. + SPI_DMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF_INT_ENA field. + SPI_DMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Msk = 0x100 + // Bit OUT_TOTAL_EOF_INT_ENA. + SPI_DMA_INT_ENA_OUT_TOTAL_EOF_INT_ENA = 0x100 + // Position of INFIFO_FULL_ERR_INT_ENA field. + SPI_DMA_INT_ENA_INFIFO_FULL_ERR_INT_ENA_Pos = 0x9 + // Bit mask of INFIFO_FULL_ERR_INT_ENA field. + SPI_DMA_INT_ENA_INFIFO_FULL_ERR_INT_ENA_Msk = 0x200 + // Bit INFIFO_FULL_ERR_INT_ENA. + SPI_DMA_INT_ENA_INFIFO_FULL_ERR_INT_ENA = 0x200 + // Position of OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI_DMA_INT_ENA_OUTFIFO_EMPTY_ERR_INT_ENA_Pos = 0xa + // Bit mask of OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI_DMA_INT_ENA_OUTFIFO_EMPTY_ERR_INT_ENA_Msk = 0x400 + // Bit OUTFIFO_EMPTY_ERR_INT_ENA. + SPI_DMA_INT_ENA_OUTFIFO_EMPTY_ERR_INT_ENA = 0x400 + // Position of SLV_CMD6_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMD6_INT_ENA_Pos = 0xb + // Bit mask of SLV_CMD6_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMD6_INT_ENA_Msk = 0x800 + // Bit SLV_CMD6_INT_ENA. + SPI_DMA_INT_ENA_SLV_CMD6_INT_ENA = 0x800 + // Position of SLV_CMD7_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMD7_INT_ENA_Pos = 0xc + // Bit mask of SLV_CMD7_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMD7_INT_ENA_Msk = 0x1000 + // Bit SLV_CMD7_INT_ENA. + SPI_DMA_INT_ENA_SLV_CMD7_INT_ENA = 0x1000 + // Position of SLV_CMD8_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMD8_INT_ENA_Pos = 0xd + // Bit mask of SLV_CMD8_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMD8_INT_ENA_Msk = 0x2000 + // Bit SLV_CMD8_INT_ENA. + SPI_DMA_INT_ENA_SLV_CMD8_INT_ENA = 0x2000 + // Position of SLV_CMD9_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMD9_INT_ENA_Pos = 0xe + // Bit mask of SLV_CMD9_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMD9_INT_ENA_Msk = 0x4000 + // Bit SLV_CMD9_INT_ENA. + SPI_DMA_INT_ENA_SLV_CMD9_INT_ENA = 0x4000 + // Position of SLV_CMDA_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMDA_INT_ENA_Pos = 0xf + // Bit mask of SLV_CMDA_INT_ENA field. + SPI_DMA_INT_ENA_SLV_CMDA_INT_ENA_Msk = 0x8000 + // Bit SLV_CMDA_INT_ENA. + SPI_DMA_INT_ENA_SLV_CMDA_INT_ENA = 0x8000 + + // DMA_INT_RAW: SPI DMA interrupt raw register + // Position of INLINK_DSCR_EMPTY_INT_RAW field. + SPI_DMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW_Pos = 0x0 + // Bit mask of INLINK_DSCR_EMPTY_INT_RAW field. + SPI_DMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW_Msk = 0x1 + // Bit INLINK_DSCR_EMPTY_INT_RAW. + SPI_DMA_INT_RAW_INLINK_DSCR_EMPTY_INT_RAW = 0x1 + // Position of OUTLINK_DSCR_ERROR_INT_RAW field. + SPI_DMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW_Pos = 0x1 + // Bit mask of OUTLINK_DSCR_ERROR_INT_RAW field. + SPI_DMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW_Msk = 0x2 + // Bit OUTLINK_DSCR_ERROR_INT_RAW. + SPI_DMA_INT_RAW_OUTLINK_DSCR_ERROR_INT_RAW = 0x2 + // Position of INLINK_DSCR_ERROR_INT_RAW field. + SPI_DMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW_Pos = 0x2 + // Bit mask of INLINK_DSCR_ERROR_INT_RAW field. + SPI_DMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW_Msk = 0x4 + // Bit INLINK_DSCR_ERROR_INT_RAW. + SPI_DMA_INT_RAW_INLINK_DSCR_ERROR_INT_RAW = 0x4 + // Position of IN_DONE_INT_RAW field. + SPI_DMA_INT_RAW_IN_DONE_INT_RAW_Pos = 0x3 + // Bit mask of IN_DONE_INT_RAW field. + SPI_DMA_INT_RAW_IN_DONE_INT_RAW_Msk = 0x8 + // Bit IN_DONE_INT_RAW. + SPI_DMA_INT_RAW_IN_DONE_INT_RAW = 0x8 + // Position of IN_ERR_EOF_INT_RAW field. + SPI_DMA_INT_RAW_IN_ERR_EOF_INT_RAW_Pos = 0x4 + // Bit mask of IN_ERR_EOF_INT_RAW field. + SPI_DMA_INT_RAW_IN_ERR_EOF_INT_RAW_Msk = 0x10 + // Bit IN_ERR_EOF_INT_RAW. + SPI_DMA_INT_RAW_IN_ERR_EOF_INT_RAW = 0x10 + // Position of IN_SUC_EOF_INT_RAW field. + SPI_DMA_INT_RAW_IN_SUC_EOF_INT_RAW_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_RAW field. + SPI_DMA_INT_RAW_IN_SUC_EOF_INT_RAW_Msk = 0x20 + // Bit IN_SUC_EOF_INT_RAW. + SPI_DMA_INT_RAW_IN_SUC_EOF_INT_RAW = 0x20 + // Position of OUT_DONE_INT_RAW field. + SPI_DMA_INT_RAW_OUT_DONE_INT_RAW_Pos = 0x6 + // Bit mask of OUT_DONE_INT_RAW field. + SPI_DMA_INT_RAW_OUT_DONE_INT_RAW_Msk = 0x40 + // Bit OUT_DONE_INT_RAW. + SPI_DMA_INT_RAW_OUT_DONE_INT_RAW = 0x40 + // Position of OUT_EOF_INT_RAW field. + SPI_DMA_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x7 + // Bit mask of OUT_EOF_INT_RAW field. + SPI_DMA_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x80 + // Bit OUT_EOF_INT_RAW. + SPI_DMA_INT_RAW_OUT_EOF_INT_RAW = 0x80 + // Position of OUT_TOTAL_EOF_INT_RAW field. + SPI_DMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF_INT_RAW field. + SPI_DMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Msk = 0x100 + // Bit OUT_TOTAL_EOF_INT_RAW. + SPI_DMA_INT_RAW_OUT_TOTAL_EOF_INT_RAW = 0x100 + // Position of INFIFO_FULL_ERR_INT_RAW field. + SPI_DMA_INT_RAW_INFIFO_FULL_ERR_INT_RAW_Pos = 0x9 + // Bit mask of INFIFO_FULL_ERR_INT_RAW field. + SPI_DMA_INT_RAW_INFIFO_FULL_ERR_INT_RAW_Msk = 0x200 + // Bit INFIFO_FULL_ERR_INT_RAW. + SPI_DMA_INT_RAW_INFIFO_FULL_ERR_INT_RAW = 0x200 + // Position of OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI_DMA_INT_RAW_OUTFIFO_EMPTY_ERR_INT_RAW_Pos = 0xa + // Bit mask of OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI_DMA_INT_RAW_OUTFIFO_EMPTY_ERR_INT_RAW_Msk = 0x400 + // Bit OUTFIFO_EMPTY_ERR_INT_RAW. + SPI_DMA_INT_RAW_OUTFIFO_EMPTY_ERR_INT_RAW = 0x400 + // Position of SLV_CMD6_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMD6_INT_RAW_Pos = 0xb + // Bit mask of SLV_CMD6_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMD6_INT_RAW_Msk = 0x800 + // Bit SLV_CMD6_INT_RAW. + SPI_DMA_INT_RAW_SLV_CMD6_INT_RAW = 0x800 + // Position of SLV_CMD7_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMD7_INT_RAW_Pos = 0xc + // Bit mask of SLV_CMD7_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMD7_INT_RAW_Msk = 0x1000 + // Bit SLV_CMD7_INT_RAW. + SPI_DMA_INT_RAW_SLV_CMD7_INT_RAW = 0x1000 + // Position of SLV_CMD8_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMD8_INT_RAW_Pos = 0xd + // Bit mask of SLV_CMD8_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMD8_INT_RAW_Msk = 0x2000 + // Bit SLV_CMD8_INT_RAW. + SPI_DMA_INT_RAW_SLV_CMD8_INT_RAW = 0x2000 + // Position of SLV_CMD9_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMD9_INT_RAW_Pos = 0xe + // Bit mask of SLV_CMD9_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMD9_INT_RAW_Msk = 0x4000 + // Bit SLV_CMD9_INT_RAW. + SPI_DMA_INT_RAW_SLV_CMD9_INT_RAW = 0x4000 + // Position of SLV_CMDA_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMDA_INT_RAW_Pos = 0xf + // Bit mask of SLV_CMDA_INT_RAW field. + SPI_DMA_INT_RAW_SLV_CMDA_INT_RAW_Msk = 0x8000 + // Bit SLV_CMDA_INT_RAW. + SPI_DMA_INT_RAW_SLV_CMDA_INT_RAW = 0x8000 + + // DMA_INT_ST: SPI DMA interrupt status register + // Position of INLINK_DSCR_EMPTY_INT_ST field. + SPI_DMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST_Pos = 0x0 + // Bit mask of INLINK_DSCR_EMPTY_INT_ST field. + SPI_DMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST_Msk = 0x1 + // Bit INLINK_DSCR_EMPTY_INT_ST. + SPI_DMA_INT_ST_INLINK_DSCR_EMPTY_INT_ST = 0x1 + // Position of OUTLINK_DSCR_ERROR_INT_ST field. + SPI_DMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST_Pos = 0x1 + // Bit mask of OUTLINK_DSCR_ERROR_INT_ST field. + SPI_DMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST_Msk = 0x2 + // Bit OUTLINK_DSCR_ERROR_INT_ST. + SPI_DMA_INT_ST_OUTLINK_DSCR_ERROR_INT_ST = 0x2 + // Position of INLINK_DSCR_ERROR_INT_ST field. + SPI_DMA_INT_ST_INLINK_DSCR_ERROR_INT_ST_Pos = 0x2 + // Bit mask of INLINK_DSCR_ERROR_INT_ST field. + SPI_DMA_INT_ST_INLINK_DSCR_ERROR_INT_ST_Msk = 0x4 + // Bit INLINK_DSCR_ERROR_INT_ST. + SPI_DMA_INT_ST_INLINK_DSCR_ERROR_INT_ST = 0x4 + // Position of IN_DONE_INT_ST field. + SPI_DMA_INT_ST_IN_DONE_INT_ST_Pos = 0x3 + // Bit mask of IN_DONE_INT_ST field. + SPI_DMA_INT_ST_IN_DONE_INT_ST_Msk = 0x8 + // Bit IN_DONE_INT_ST. + SPI_DMA_INT_ST_IN_DONE_INT_ST = 0x8 + // Position of IN_ERR_EOF_INT_ST field. + SPI_DMA_INT_ST_IN_ERR_EOF_INT_ST_Pos = 0x4 + // Bit mask of IN_ERR_EOF_INT_ST field. + SPI_DMA_INT_ST_IN_ERR_EOF_INT_ST_Msk = 0x10 + // Bit IN_ERR_EOF_INT_ST. + SPI_DMA_INT_ST_IN_ERR_EOF_INT_ST = 0x10 + // Position of IN_SUC_EOF_INT_ST field. + SPI_DMA_INT_ST_IN_SUC_EOF_INT_ST_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_ST field. + SPI_DMA_INT_ST_IN_SUC_EOF_INT_ST_Msk = 0x20 + // Bit IN_SUC_EOF_INT_ST. + SPI_DMA_INT_ST_IN_SUC_EOF_INT_ST = 0x20 + // Position of OUT_DONE_INT_ST field. + SPI_DMA_INT_ST_OUT_DONE_INT_ST_Pos = 0x6 + // Bit mask of OUT_DONE_INT_ST field. + SPI_DMA_INT_ST_OUT_DONE_INT_ST_Msk = 0x40 + // Bit OUT_DONE_INT_ST. + SPI_DMA_INT_ST_OUT_DONE_INT_ST = 0x40 + // Position of OUT_EOF_INT_ST field. + SPI_DMA_INT_ST_OUT_EOF_INT_ST_Pos = 0x7 + // Bit mask of OUT_EOF_INT_ST field. + SPI_DMA_INT_ST_OUT_EOF_INT_ST_Msk = 0x80 + // Bit OUT_EOF_INT_ST. + SPI_DMA_INT_ST_OUT_EOF_INT_ST = 0x80 + // Position of OUT_TOTAL_EOF_INT_ST field. + SPI_DMA_INT_ST_OUT_TOTAL_EOF_INT_ST_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF_INT_ST field. + SPI_DMA_INT_ST_OUT_TOTAL_EOF_INT_ST_Msk = 0x100 + // Bit OUT_TOTAL_EOF_INT_ST. + SPI_DMA_INT_ST_OUT_TOTAL_EOF_INT_ST = 0x100 + // Position of INFIFO_FULL_ERR_INT_ST field. + SPI_DMA_INT_ST_INFIFO_FULL_ERR_INT_ST_Pos = 0x9 + // Bit mask of INFIFO_FULL_ERR_INT_ST field. + SPI_DMA_INT_ST_INFIFO_FULL_ERR_INT_ST_Msk = 0x200 + // Bit INFIFO_FULL_ERR_INT_ST. + SPI_DMA_INT_ST_INFIFO_FULL_ERR_INT_ST = 0x200 + // Position of OUTFIFO_EMPTY_ERR_INT_ST field. + SPI_DMA_INT_ST_OUTFIFO_EMPTY_ERR_INT_ST_Pos = 0xa + // Bit mask of OUTFIFO_EMPTY_ERR_INT_ST field. + SPI_DMA_INT_ST_OUTFIFO_EMPTY_ERR_INT_ST_Msk = 0x400 + // Bit OUTFIFO_EMPTY_ERR_INT_ST. + SPI_DMA_INT_ST_OUTFIFO_EMPTY_ERR_INT_ST = 0x400 + // Position of SLV_CMD6_INT_ST field. + SPI_DMA_INT_ST_SLV_CMD6_INT_ST_Pos = 0xb + // Bit mask of SLV_CMD6_INT_ST field. + SPI_DMA_INT_ST_SLV_CMD6_INT_ST_Msk = 0x800 + // Bit SLV_CMD6_INT_ST. + SPI_DMA_INT_ST_SLV_CMD6_INT_ST = 0x800 + // Position of SLV_CMD7_INT_ST field. + SPI_DMA_INT_ST_SLV_CMD7_INT_ST_Pos = 0xc + // Bit mask of SLV_CMD7_INT_ST field. + SPI_DMA_INT_ST_SLV_CMD7_INT_ST_Msk = 0x1000 + // Bit SLV_CMD7_INT_ST. + SPI_DMA_INT_ST_SLV_CMD7_INT_ST = 0x1000 + // Position of SLV_CMD8_INT_ST field. + SPI_DMA_INT_ST_SLV_CMD8_INT_ST_Pos = 0xd + // Bit mask of SLV_CMD8_INT_ST field. + SPI_DMA_INT_ST_SLV_CMD8_INT_ST_Msk = 0x2000 + // Bit SLV_CMD8_INT_ST. + SPI_DMA_INT_ST_SLV_CMD8_INT_ST = 0x2000 + // Position of SLV_CMD9_INT_ST field. + SPI_DMA_INT_ST_SLV_CMD9_INT_ST_Pos = 0xe + // Bit mask of SLV_CMD9_INT_ST field. + SPI_DMA_INT_ST_SLV_CMD9_INT_ST_Msk = 0x4000 + // Bit SLV_CMD9_INT_ST. + SPI_DMA_INT_ST_SLV_CMD9_INT_ST = 0x4000 + // Position of SLV_CMDA_INT_ST field. + SPI_DMA_INT_ST_SLV_CMDA_INT_ST_Pos = 0xf + // Bit mask of SLV_CMDA_INT_ST field. + SPI_DMA_INT_ST_SLV_CMDA_INT_ST_Msk = 0x8000 + // Bit SLV_CMDA_INT_ST. + SPI_DMA_INT_ST_SLV_CMDA_INT_ST = 0x8000 + + // DMA_INT_CLR: SPI DMA interrupt clear register + // Position of INLINK_DSCR_EMPTY_INT_CLR field. + SPI_DMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR_Pos = 0x0 + // Bit mask of INLINK_DSCR_EMPTY_INT_CLR field. + SPI_DMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR_Msk = 0x1 + // Bit INLINK_DSCR_EMPTY_INT_CLR. + SPI_DMA_INT_CLR_INLINK_DSCR_EMPTY_INT_CLR = 0x1 + // Position of OUTLINK_DSCR_ERROR_INT_CLR field. + SPI_DMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR_Pos = 0x1 + // Bit mask of OUTLINK_DSCR_ERROR_INT_CLR field. + SPI_DMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR_Msk = 0x2 + // Bit OUTLINK_DSCR_ERROR_INT_CLR. + SPI_DMA_INT_CLR_OUTLINK_DSCR_ERROR_INT_CLR = 0x2 + // Position of INLINK_DSCR_ERROR_INT_CLR field. + SPI_DMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR_Pos = 0x2 + // Bit mask of INLINK_DSCR_ERROR_INT_CLR field. + SPI_DMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR_Msk = 0x4 + // Bit INLINK_DSCR_ERROR_INT_CLR. + SPI_DMA_INT_CLR_INLINK_DSCR_ERROR_INT_CLR = 0x4 + // Position of IN_DONE_INT_CLR field. + SPI_DMA_INT_CLR_IN_DONE_INT_CLR_Pos = 0x3 + // Bit mask of IN_DONE_INT_CLR field. + SPI_DMA_INT_CLR_IN_DONE_INT_CLR_Msk = 0x8 + // Bit IN_DONE_INT_CLR. + SPI_DMA_INT_CLR_IN_DONE_INT_CLR = 0x8 + // Position of IN_ERR_EOF_INT_CLR field. + SPI_DMA_INT_CLR_IN_ERR_EOF_INT_CLR_Pos = 0x4 + // Bit mask of IN_ERR_EOF_INT_CLR field. + SPI_DMA_INT_CLR_IN_ERR_EOF_INT_CLR_Msk = 0x10 + // Bit IN_ERR_EOF_INT_CLR. + SPI_DMA_INT_CLR_IN_ERR_EOF_INT_CLR = 0x10 + // Position of IN_SUC_EOF_INT_CLR field. + SPI_DMA_INT_CLR_IN_SUC_EOF_INT_CLR_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_CLR field. + SPI_DMA_INT_CLR_IN_SUC_EOF_INT_CLR_Msk = 0x20 + // Bit IN_SUC_EOF_INT_CLR. + SPI_DMA_INT_CLR_IN_SUC_EOF_INT_CLR = 0x20 + // Position of OUT_DONE_INT_CLR field. + SPI_DMA_INT_CLR_OUT_DONE_INT_CLR_Pos = 0x6 + // Bit mask of OUT_DONE_INT_CLR field. + SPI_DMA_INT_CLR_OUT_DONE_INT_CLR_Msk = 0x40 + // Bit OUT_DONE_INT_CLR. + SPI_DMA_INT_CLR_OUT_DONE_INT_CLR = 0x40 + // Position of OUT_EOF_INT_CLR field. + SPI_DMA_INT_CLR_OUT_EOF_INT_CLR_Pos = 0x7 + // Bit mask of OUT_EOF_INT_CLR field. + SPI_DMA_INT_CLR_OUT_EOF_INT_CLR_Msk = 0x80 + // Bit OUT_EOF_INT_CLR. + SPI_DMA_INT_CLR_OUT_EOF_INT_CLR = 0x80 + // Position of OUT_TOTAL_EOF_INT_CLR field. + SPI_DMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Pos = 0x8 + // Bit mask of OUT_TOTAL_EOF_INT_CLR field. + SPI_DMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Msk = 0x100 + // Bit OUT_TOTAL_EOF_INT_CLR. + SPI_DMA_INT_CLR_OUT_TOTAL_EOF_INT_CLR = 0x100 + // Position of INFIFO_FULL_ERR_INT_CLR field. + SPI_DMA_INT_CLR_INFIFO_FULL_ERR_INT_CLR_Pos = 0x9 + // Bit mask of INFIFO_FULL_ERR_INT_CLR field. + SPI_DMA_INT_CLR_INFIFO_FULL_ERR_INT_CLR_Msk = 0x200 + // Bit INFIFO_FULL_ERR_INT_CLR. + SPI_DMA_INT_CLR_INFIFO_FULL_ERR_INT_CLR = 0x200 + // Position of OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI_DMA_INT_CLR_OUTFIFO_EMPTY_ERR_INT_CLR_Pos = 0xa + // Bit mask of OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI_DMA_INT_CLR_OUTFIFO_EMPTY_ERR_INT_CLR_Msk = 0x400 + // Bit OUTFIFO_EMPTY_ERR_INT_CLR. + SPI_DMA_INT_CLR_OUTFIFO_EMPTY_ERR_INT_CLR = 0x400 + // Position of SLV_CMD6_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMD6_INT_CLR_Pos = 0xb + // Bit mask of SLV_CMD6_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMD6_INT_CLR_Msk = 0x800 + // Bit SLV_CMD6_INT_CLR. + SPI_DMA_INT_CLR_SLV_CMD6_INT_CLR = 0x800 + // Position of SLV_CMD7_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMD7_INT_CLR_Pos = 0xc + // Bit mask of SLV_CMD7_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMD7_INT_CLR_Msk = 0x1000 + // Bit SLV_CMD7_INT_CLR. + SPI_DMA_INT_CLR_SLV_CMD7_INT_CLR = 0x1000 + // Position of SLV_CMD8_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMD8_INT_CLR_Pos = 0xd + // Bit mask of SLV_CMD8_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMD8_INT_CLR_Msk = 0x2000 + // Bit SLV_CMD8_INT_CLR. + SPI_DMA_INT_CLR_SLV_CMD8_INT_CLR = 0x2000 + // Position of SLV_CMD9_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMD9_INT_CLR_Pos = 0xe + // Bit mask of SLV_CMD9_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMD9_INT_CLR_Msk = 0x4000 + // Bit SLV_CMD9_INT_CLR. + SPI_DMA_INT_CLR_SLV_CMD9_INT_CLR = 0x4000 + // Position of SLV_CMDA_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMDA_INT_CLR_Pos = 0xf + // Bit mask of SLV_CMDA_INT_CLR field. + SPI_DMA_INT_CLR_SLV_CMDA_INT_CLR_Msk = 0x8000 + // Bit SLV_CMDA_INT_CLR. + SPI_DMA_INT_CLR_SLV_CMDA_INT_CLR = 0x8000 + + // IN_ERR_EOF_DES_ADDR: The latest SPI DMA RX descriptor address receiving error + // Position of DMA_IN_ERR_EOF_DES_ADDR field. + SPI_IN_ERR_EOF_DES_ADDR_DMA_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of DMA_IN_ERR_EOF_DES_ADDR field. + SPI_IN_ERR_EOF_DES_ADDR_DMA_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_SUC_EOF_DES_ADDR: The latest SPI DMA eof RX descriptor address + // Position of DMA_IN_SUC_EOF_DES_ADDR field. + SPI_IN_SUC_EOF_DES_ADDR_DMA_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of DMA_IN_SUC_EOF_DES_ADDR field. + SPI_IN_SUC_EOF_DES_ADDR_DMA_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // INLINK_DSCR: Current SPI DMA RX descriptor pointer + // Position of DMA_INLINK_DSCR field. + SPI_INLINK_DSCR_DMA_INLINK_DSCR_Pos = 0x0 + // Bit mask of DMA_INLINK_DSCR field. + SPI_INLINK_DSCR_DMA_INLINK_DSCR_Msk = 0xffffffff + + // INLINK_DSCR_BF0: Next SPI DMA RX descriptor pointer + // Position of DMA_INLINK_DSCR_BF0 field. + SPI_INLINK_DSCR_BF0_DMA_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of DMA_INLINK_DSCR_BF0 field. + SPI_INLINK_DSCR_BF0_DMA_INLINK_DSCR_BF0_Msk = 0xffffffff + + // INLINK_DSCR_BF1: Current SPI DMA RX buffer pointer + // Position of DMA_INLINK_DSCR_BF1 field. + SPI_INLINK_DSCR_BF1_DMA_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of DMA_INLINK_DSCR_BF1 field. + SPI_INLINK_DSCR_BF1_DMA_INLINK_DSCR_BF1_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR: The latest SPI DMA eof TX buffer address + // Position of DMA_OUT_EOF_BFR_DES_ADDR field. + SPI_OUT_EOF_BFR_DES_ADDR_DMA_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of DMA_OUT_EOF_BFR_DES_ADDR field. + SPI_OUT_EOF_BFR_DES_ADDR_DMA_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_DES_ADDR: The latest SPI DMA eof TX descriptor address + // Position of DMA_OUT_EOF_DES_ADDR field. + SPI_OUT_EOF_DES_ADDR_DMA_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of DMA_OUT_EOF_DES_ADDR field. + SPI_OUT_EOF_DES_ADDR_DMA_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // OUTLINK_DSCR: Current SPI DMA TX descriptor pointer + // Position of DMA_OUTLINK_DSCR field. + SPI_OUTLINK_DSCR_DMA_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of DMA_OUTLINK_DSCR field. + SPI_OUTLINK_DSCR_DMA_OUTLINK_DSCR_Msk = 0xffffffff + + // OUTLINK_DSCR_BF0: Next SPI DMA TX descriptor pointer + // Position of DMA_OUTLINK_DSCR_BF0 field. + SPI_OUTLINK_DSCR_BF0_DMA_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of DMA_OUTLINK_DSCR_BF0 field. + SPI_OUTLINK_DSCR_BF0_DMA_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUTLINK_DSCR_BF1: Current SPI DMA TX buffer pointer + // Position of DMA_OUTLINK_DSCR_BF1 field. + SPI_OUTLINK_DSCR_BF1_DMA_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of DMA_OUTLINK_DSCR_BF1 field. + SPI_OUTLINK_DSCR_BF1_DMA_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // DMA_OUTSTATUS: SPI DMA TX status + // Position of DMA_OUTDSCR_ADDR field. + SPI_DMA_OUTSTATUS_DMA_OUTDSCR_ADDR_Pos = 0x0 + // Bit mask of DMA_OUTDSCR_ADDR field. + SPI_DMA_OUTSTATUS_DMA_OUTDSCR_ADDR_Msk = 0x3ffff + // Position of DMA_OUTDSCR_STATE field. + SPI_DMA_OUTSTATUS_DMA_OUTDSCR_STATE_Pos = 0x12 + // Bit mask of DMA_OUTDSCR_STATE field. + SPI_DMA_OUTSTATUS_DMA_OUTDSCR_STATE_Msk = 0xc0000 + // Position of DMA_OUT_STATE field. + SPI_DMA_OUTSTATUS_DMA_OUT_STATE_Pos = 0x14 + // Bit mask of DMA_OUT_STATE field. + SPI_DMA_OUTSTATUS_DMA_OUT_STATE_Msk = 0x700000 + // Position of DMA_OUTFIFO_CNT field. + SPI_DMA_OUTSTATUS_DMA_OUTFIFO_CNT_Pos = 0x17 + // Bit mask of DMA_OUTFIFO_CNT field. + SPI_DMA_OUTSTATUS_DMA_OUTFIFO_CNT_Msk = 0x3f800000 + // Position of DMA_OUTFIFO_FULL field. + SPI_DMA_OUTSTATUS_DMA_OUTFIFO_FULL_Pos = 0x1e + // Bit mask of DMA_OUTFIFO_FULL field. + SPI_DMA_OUTSTATUS_DMA_OUTFIFO_FULL_Msk = 0x40000000 + // Bit DMA_OUTFIFO_FULL. + SPI_DMA_OUTSTATUS_DMA_OUTFIFO_FULL = 0x40000000 + // Position of DMA_OUTFIFO_EMPTY field. + SPI_DMA_OUTSTATUS_DMA_OUTFIFO_EMPTY_Pos = 0x1f + // Bit mask of DMA_OUTFIFO_EMPTY field. + SPI_DMA_OUTSTATUS_DMA_OUTFIFO_EMPTY_Msk = 0x80000000 + // Bit DMA_OUTFIFO_EMPTY. + SPI_DMA_OUTSTATUS_DMA_OUTFIFO_EMPTY = 0x80000000 + + // DMA_INSTATUS: SPI DMA RX status + // Position of DMA_INDSCR_ADDR field. + SPI_DMA_INSTATUS_DMA_INDSCR_ADDR_Pos = 0x0 + // Bit mask of DMA_INDSCR_ADDR field. + SPI_DMA_INSTATUS_DMA_INDSCR_ADDR_Msk = 0x3ffff + // Position of DMA_INDSCR_STATE field. + SPI_DMA_INSTATUS_DMA_INDSCR_STATE_Pos = 0x12 + // Bit mask of DMA_INDSCR_STATE field. + SPI_DMA_INSTATUS_DMA_INDSCR_STATE_Msk = 0xc0000 + // Position of DMA_IN_STATE field. + SPI_DMA_INSTATUS_DMA_IN_STATE_Pos = 0x14 + // Bit mask of DMA_IN_STATE field. + SPI_DMA_INSTATUS_DMA_IN_STATE_Msk = 0x700000 + // Position of DMA_INFIFO_CNT field. + SPI_DMA_INSTATUS_DMA_INFIFO_CNT_Pos = 0x17 + // Bit mask of DMA_INFIFO_CNT field. + SPI_DMA_INSTATUS_DMA_INFIFO_CNT_Msk = 0x3f800000 + // Position of DMA_INFIFO_FULL field. + SPI_DMA_INSTATUS_DMA_INFIFO_FULL_Pos = 0x1e + // Bit mask of DMA_INFIFO_FULL field. + SPI_DMA_INSTATUS_DMA_INFIFO_FULL_Msk = 0x40000000 + // Bit DMA_INFIFO_FULL. + SPI_DMA_INSTATUS_DMA_INFIFO_FULL = 0x40000000 + // Position of DMA_INFIFO_EMPTY field. + SPI_DMA_INSTATUS_DMA_INFIFO_EMPTY_Pos = 0x1f + // Bit mask of DMA_INFIFO_EMPTY field. + SPI_DMA_INSTATUS_DMA_INFIFO_EMPTY_Msk = 0x80000000 + // Bit DMA_INFIFO_EMPTY. + SPI_DMA_INSTATUS_DMA_INFIFO_EMPTY = 0x80000000 + + // W0: Data buffer 0 + // Position of BUF0 field. + SPI_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI_W0_BUF0_Msk = 0xffffffff + + // W1: Data buffer 1 + // Position of BUF1 field. + SPI_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI_W1_BUF1_Msk = 0xffffffff + + // W2: Data buffer 2 + // Position of BUF2 field. + SPI_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI_W2_BUF2_Msk = 0xffffffff + + // W3: Data buffer 3 + // Position of BUF3 field. + SPI_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI_W3_BUF3_Msk = 0xffffffff + + // W4: Data buffer 4 + // Position of BUF4 field. + SPI_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI_W4_BUF4_Msk = 0xffffffff + + // W5: Data buffer 5 + // Position of BUF5 field. + SPI_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI_W5_BUF5_Msk = 0xffffffff + + // W6: Data buffer 6 + // Position of BUF6 field. + SPI_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI_W6_BUF6_Msk = 0xffffffff + + // W7: Data buffer 7 + // Position of BUF7 field. + SPI_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI_W7_BUF7_Msk = 0xffffffff + + // W8: Data buffer 8 + // Position of BUF8 field. + SPI_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI_W8_BUF8_Msk = 0xffffffff + + // W9: Data buffer 9 + // Position of BUF9 field. + SPI_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI_W9_BUF9_Msk = 0xffffffff + + // W10: Data buffer 10 + // Position of BUF10 field. + SPI_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI_W10_BUF10_Msk = 0xffffffff + + // W11: Data buffer 11 + // Position of BUF11 field. + SPI_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI_W11_BUF11_Msk = 0xffffffff + + // W12: Data buffer 12 + // Position of BUF12 field. + SPI_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI_W12_BUF12_Msk = 0xffffffff + + // W13: Data buffer 13 + // Position of BUF13 field. + SPI_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI_W13_BUF13_Msk = 0xffffffff + + // W14: Data buffer 14 + // Position of BUF14 field. + SPI_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI_W14_BUF14_Msk = 0xffffffff + + // W15: Data buffer 15 + // Position of BUF15 field. + SPI_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI_W15_BUF15_Msk = 0xffffffff + + // W16: Data buffer 16 + // Position of BUF16 field. + SPI_W16_BUF16_Pos = 0x0 + // Bit mask of BUF16 field. + SPI_W16_BUF16_Msk = 0xffffffff + + // W17: Data buffer 17 + // Position of BUF17 field. + SPI_W17_BUF17_Pos = 0x0 + // Bit mask of BUF17 field. + SPI_W17_BUF17_Msk = 0xffffffff + + // DIN_MODE: SPI input delay mode configuration + // Position of DIN0_MODE field. + SPI_DIN_MODE_DIN0_MODE_Pos = 0x0 + // Bit mask of DIN0_MODE field. + SPI_DIN_MODE_DIN0_MODE_Msk = 0x7 + // Position of DIN1_MODE field. + SPI_DIN_MODE_DIN1_MODE_Pos = 0x3 + // Bit mask of DIN1_MODE field. + SPI_DIN_MODE_DIN1_MODE_Msk = 0x38 + // Position of DIN2_MODE field. + SPI_DIN_MODE_DIN2_MODE_Pos = 0x6 + // Bit mask of DIN2_MODE field. + SPI_DIN_MODE_DIN2_MODE_Msk = 0x1c0 + // Position of DIN3_MODE field. + SPI_DIN_MODE_DIN3_MODE_Pos = 0x9 + // Bit mask of DIN3_MODE field. + SPI_DIN_MODE_DIN3_MODE_Msk = 0xe00 + // Position of DIN4_MODE field. + SPI_DIN_MODE_DIN4_MODE_Pos = 0xc + // Bit mask of DIN4_MODE field. + SPI_DIN_MODE_DIN4_MODE_Msk = 0x7000 + // Position of DIN5_MODE field. + SPI_DIN_MODE_DIN5_MODE_Pos = 0xf + // Bit mask of DIN5_MODE field. + SPI_DIN_MODE_DIN5_MODE_Msk = 0x38000 + // Position of DIN6_MODE field. + SPI_DIN_MODE_DIN6_MODE_Pos = 0x12 + // Bit mask of DIN6_MODE field. + SPI_DIN_MODE_DIN6_MODE_Msk = 0x1c0000 + // Position of DIN7_MODE field. + SPI_DIN_MODE_DIN7_MODE_Pos = 0x15 + // Bit mask of DIN7_MODE field. + SPI_DIN_MODE_DIN7_MODE_Msk = 0xe00000 + // Position of TIMING_CLK_ENA field. + SPI_DIN_MODE_TIMING_CLK_ENA_Pos = 0x18 + // Bit mask of TIMING_CLK_ENA field. + SPI_DIN_MODE_TIMING_CLK_ENA_Msk = 0x1000000 + // Bit TIMING_CLK_ENA. + SPI_DIN_MODE_TIMING_CLK_ENA = 0x1000000 + + // DIN_NUM: SPI input delay number configuration + // Position of DIN0_NUM field. + SPI_DIN_NUM_DIN0_NUM_Pos = 0x0 + // Bit mask of DIN0_NUM field. + SPI_DIN_NUM_DIN0_NUM_Msk = 0x3 + // Position of DIN1_NUM field. + SPI_DIN_NUM_DIN1_NUM_Pos = 0x2 + // Bit mask of DIN1_NUM field. + SPI_DIN_NUM_DIN1_NUM_Msk = 0xc + // Position of DIN2_NUM field. + SPI_DIN_NUM_DIN2_NUM_Pos = 0x4 + // Bit mask of DIN2_NUM field. + SPI_DIN_NUM_DIN2_NUM_Msk = 0x30 + // Position of DIN3_NUM field. + SPI_DIN_NUM_DIN3_NUM_Pos = 0x6 + // Bit mask of DIN3_NUM field. + SPI_DIN_NUM_DIN3_NUM_Msk = 0xc0 + // Position of DIN4_NUM field. + SPI_DIN_NUM_DIN4_NUM_Pos = 0x8 + // Bit mask of DIN4_NUM field. + SPI_DIN_NUM_DIN4_NUM_Msk = 0x300 + // Position of DIN5_NUM field. + SPI_DIN_NUM_DIN5_NUM_Pos = 0xa + // Bit mask of DIN5_NUM field. + SPI_DIN_NUM_DIN5_NUM_Msk = 0xc00 + // Position of DIN6_NUM field. + SPI_DIN_NUM_DIN6_NUM_Pos = 0xc + // Bit mask of DIN6_NUM field. + SPI_DIN_NUM_DIN6_NUM_Msk = 0x3000 + // Position of DIN7_NUM field. + SPI_DIN_NUM_DIN7_NUM_Pos = 0xe + // Bit mask of DIN7_NUM field. + SPI_DIN_NUM_DIN7_NUM_Msk = 0xc000 + + // DOUT_MODE: SPI output delay mode configuration + // Position of DOUT0_MODE field. + SPI_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + SPI_DOUT_MODE_DOUT0_MODE_Msk = 0x7 + // Position of DOUT1_MODE field. + SPI_DOUT_MODE_DOUT1_MODE_Pos = 0x3 + // Bit mask of DOUT1_MODE field. + SPI_DOUT_MODE_DOUT1_MODE_Msk = 0x38 + // Position of DOUT2_MODE field. + SPI_DOUT_MODE_DOUT2_MODE_Pos = 0x6 + // Bit mask of DOUT2_MODE field. + SPI_DOUT_MODE_DOUT2_MODE_Msk = 0x1c0 + // Position of DOUT3_MODE field. + SPI_DOUT_MODE_DOUT3_MODE_Pos = 0x9 + // Bit mask of DOUT3_MODE field. + SPI_DOUT_MODE_DOUT3_MODE_Msk = 0xe00 + // Position of DOUT4_MODE field. + SPI_DOUT_MODE_DOUT4_MODE_Pos = 0xc + // Bit mask of DOUT4_MODE field. + SPI_DOUT_MODE_DOUT4_MODE_Msk = 0x7000 + // Position of DOUT5_MODE field. + SPI_DOUT_MODE_DOUT5_MODE_Pos = 0xf + // Bit mask of DOUT5_MODE field. + SPI_DOUT_MODE_DOUT5_MODE_Msk = 0x38000 + // Position of DOUT6_MODE field. + SPI_DOUT_MODE_DOUT6_MODE_Pos = 0x12 + // Bit mask of DOUT6_MODE field. + SPI_DOUT_MODE_DOUT6_MODE_Msk = 0x1c0000 + // Position of DOUT7_MODE field. + SPI_DOUT_MODE_DOUT7_MODE_Pos = 0x15 + // Bit mask of DOUT7_MODE field. + SPI_DOUT_MODE_DOUT7_MODE_Msk = 0xe00000 + + // DOUT_NUM: SPI output delay number configuration + // Position of DOUT0_NUM field. + SPI_DOUT_NUM_DOUT0_NUM_Pos = 0x0 + // Bit mask of DOUT0_NUM field. + SPI_DOUT_NUM_DOUT0_NUM_Msk = 0x3 + // Position of DOUT1_NUM field. + SPI_DOUT_NUM_DOUT1_NUM_Pos = 0x2 + // Bit mask of DOUT1_NUM field. + SPI_DOUT_NUM_DOUT1_NUM_Msk = 0xc + // Position of DOUT2_NUM field. + SPI_DOUT_NUM_DOUT2_NUM_Pos = 0x4 + // Bit mask of DOUT2_NUM field. + SPI_DOUT_NUM_DOUT2_NUM_Msk = 0x30 + // Position of DOUT3_NUM field. + SPI_DOUT_NUM_DOUT3_NUM_Pos = 0x6 + // Bit mask of DOUT3_NUM field. + SPI_DOUT_NUM_DOUT3_NUM_Msk = 0xc0 + // Position of DOUT4_NUM field. + SPI_DOUT_NUM_DOUT4_NUM_Pos = 0x8 + // Bit mask of DOUT4_NUM field. + SPI_DOUT_NUM_DOUT4_NUM_Msk = 0x300 + // Position of DOUT5_NUM field. + SPI_DOUT_NUM_DOUT5_NUM_Pos = 0xa + // Bit mask of DOUT5_NUM field. + SPI_DOUT_NUM_DOUT5_NUM_Msk = 0xc00 + // Position of DOUT6_NUM field. + SPI_DOUT_NUM_DOUT6_NUM_Pos = 0xc + // Bit mask of DOUT6_NUM field. + SPI_DOUT_NUM_DOUT6_NUM_Msk = 0x3000 + // Position of DOUT7_NUM field. + SPI_DOUT_NUM_DOUT7_NUM_Pos = 0xe + // Bit mask of DOUT7_NUM field. + SPI_DOUT_NUM_DOUT7_NUM_Msk = 0xc000 + + // LCD_CTRL: LCD frame control register + // Position of LCD_HB_FRONT field. + SPI_LCD_CTRL_LCD_HB_FRONT_Pos = 0x0 + // Bit mask of LCD_HB_FRONT field. + SPI_LCD_CTRL_LCD_HB_FRONT_Msk = 0x7ff + // Position of LCD_VA_HEIGHT field. + SPI_LCD_CTRL_LCD_VA_HEIGHT_Pos = 0xb + // Bit mask of LCD_VA_HEIGHT field. + SPI_LCD_CTRL_LCD_VA_HEIGHT_Msk = 0x1ff800 + // Position of LCD_VT_HEIGHT field. + SPI_LCD_CTRL_LCD_VT_HEIGHT_Pos = 0x15 + // Bit mask of LCD_VT_HEIGHT field. + SPI_LCD_CTRL_LCD_VT_HEIGHT_Msk = 0x7fe00000 + // Position of LCD_MODE_EN field. + SPI_LCD_CTRL_LCD_MODE_EN_Pos = 0x1f + // Bit mask of LCD_MODE_EN field. + SPI_LCD_CTRL_LCD_MODE_EN_Msk = 0x80000000 + // Bit LCD_MODE_EN. + SPI_LCD_CTRL_LCD_MODE_EN = 0x80000000 + + // LCD_CTRL1: LCD frame control1 register + // Position of LCD_VB_FRONT field. + SPI_LCD_CTRL1_LCD_VB_FRONT_Pos = 0x0 + // Bit mask of LCD_VB_FRONT field. + SPI_LCD_CTRL1_LCD_VB_FRONT_Msk = 0xff + // Position of LCD_HA_WIDTH field. + SPI_LCD_CTRL1_LCD_HA_WIDTH_Pos = 0x8 + // Bit mask of LCD_HA_WIDTH field. + SPI_LCD_CTRL1_LCD_HA_WIDTH_Msk = 0xfff00 + // Position of LCD_HT_WIDTH field. + SPI_LCD_CTRL1_LCD_HT_WIDTH_Pos = 0x14 + // Bit mask of LCD_HT_WIDTH field. + SPI_LCD_CTRL1_LCD_HT_WIDTH_Msk = 0xfff00000 + + // LCD_CTRL2: LCD frame control2 register + // Position of LCD_VSYNC_WIDTH field. + SPI_LCD_CTRL2_LCD_VSYNC_WIDTH_Pos = 0x0 + // Bit mask of LCD_VSYNC_WIDTH field. + SPI_LCD_CTRL2_LCD_VSYNC_WIDTH_Msk = 0x7f + // Position of VSYNC_IDLE_POL field. + SPI_LCD_CTRL2_VSYNC_IDLE_POL_Pos = 0x7 + // Bit mask of VSYNC_IDLE_POL field. + SPI_LCD_CTRL2_VSYNC_IDLE_POL_Msk = 0x80 + // Bit VSYNC_IDLE_POL. + SPI_LCD_CTRL2_VSYNC_IDLE_POL = 0x80 + // Position of LCD_HSYNC_WIDTH field. + SPI_LCD_CTRL2_LCD_HSYNC_WIDTH_Pos = 0x10 + // Bit mask of LCD_HSYNC_WIDTH field. + SPI_LCD_CTRL2_LCD_HSYNC_WIDTH_Msk = 0x7f0000 + // Position of HSYNC_IDLE_POL field. + SPI_LCD_CTRL2_HSYNC_IDLE_POL_Pos = 0x17 + // Bit mask of HSYNC_IDLE_POL field. + SPI_LCD_CTRL2_HSYNC_IDLE_POL_Msk = 0x800000 + // Bit HSYNC_IDLE_POL. + SPI_LCD_CTRL2_HSYNC_IDLE_POL = 0x800000 + // Position of LCD_HSYNC_POSITION field. + SPI_LCD_CTRL2_LCD_HSYNC_POSITION_Pos = 0x18 + // Bit mask of LCD_HSYNC_POSITION field. + SPI_LCD_CTRL2_LCD_HSYNC_POSITION_Msk = 0xff000000 + + // LCD_D_MODE: LCD delay number + // Position of D_DQS_MODE field. + SPI_LCD_D_MODE_D_DQS_MODE_Pos = 0x0 + // Bit mask of D_DQS_MODE field. + SPI_LCD_D_MODE_D_DQS_MODE_Msk = 0x7 + // Position of D_CD_MODE field. + SPI_LCD_D_MODE_D_CD_MODE_Pos = 0x3 + // Bit mask of D_CD_MODE field. + SPI_LCD_D_MODE_D_CD_MODE_Msk = 0x38 + // Position of D_DE_MODE field. + SPI_LCD_D_MODE_D_DE_MODE_Pos = 0x6 + // Bit mask of D_DE_MODE field. + SPI_LCD_D_MODE_D_DE_MODE_Msk = 0x1c0 + // Position of D_HSYNC_MODE field. + SPI_LCD_D_MODE_D_HSYNC_MODE_Pos = 0x9 + // Bit mask of D_HSYNC_MODE field. + SPI_LCD_D_MODE_D_HSYNC_MODE_Msk = 0xe00 + // Position of D_VSYNC_MODE field. + SPI_LCD_D_MODE_D_VSYNC_MODE_Pos = 0xc + // Bit mask of D_VSYNC_MODE field. + SPI_LCD_D_MODE_D_VSYNC_MODE_Msk = 0x7000 + // Position of DE_IDLE_POL field. + SPI_LCD_D_MODE_DE_IDLE_POL_Pos = 0xf + // Bit mask of DE_IDLE_POL field. + SPI_LCD_D_MODE_DE_IDLE_POL_Msk = 0x8000 + // Bit DE_IDLE_POL. + SPI_LCD_D_MODE_DE_IDLE_POL = 0x8000 + // Position of HS_BLANK_EN field. + SPI_LCD_D_MODE_HS_BLANK_EN_Pos = 0x10 + // Bit mask of HS_BLANK_EN field. + SPI_LCD_D_MODE_HS_BLANK_EN_Msk = 0x10000 + // Bit HS_BLANK_EN. + SPI_LCD_D_MODE_HS_BLANK_EN = 0x10000 + + // LCD_D_NUM: LCD delay mode + // Position of D_DQS_NUM field. + SPI_LCD_D_NUM_D_DQS_NUM_Pos = 0x0 + // Bit mask of D_DQS_NUM field. + SPI_LCD_D_NUM_D_DQS_NUM_Msk = 0x3 + // Position of D_CD_NUM field. + SPI_LCD_D_NUM_D_CD_NUM_Pos = 0x2 + // Bit mask of D_CD_NUM field. + SPI_LCD_D_NUM_D_CD_NUM_Msk = 0xc + // Position of D_DE_NUM field. + SPI_LCD_D_NUM_D_DE_NUM_Pos = 0x4 + // Bit mask of D_DE_NUM field. + SPI_LCD_D_NUM_D_DE_NUM_Msk = 0x30 + // Position of D_HSYNC_NUM field. + SPI_LCD_D_NUM_D_HSYNC_NUM_Pos = 0x6 + // Bit mask of D_HSYNC_NUM field. + SPI_LCD_D_NUM_D_HSYNC_NUM_Msk = 0xc0 + // Position of D_VSYNC_NUM field. + SPI_LCD_D_NUM_D_VSYNC_NUM_Pos = 0x8 + // Bit mask of D_VSYNC_NUM field. + SPI_LCD_D_NUM_D_VSYNC_NUM_Msk = 0x300 + + // REG_DATE: SPI version control + // Position of DATE field. + SPI_REG_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI_REG_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SYSCON: SYSCON Peripheral +const ( + // SYSCLK_CONF + // Position of CLK_320M_EN field. + SYSCON_SYSCLK_CONF_CLK_320M_EN_Pos = 0xa + // Bit mask of CLK_320M_EN field. + SYSCON_SYSCLK_CONF_CLK_320M_EN_Msk = 0x400 + // Bit CLK_320M_EN. + SYSCON_SYSCLK_CONF_CLK_320M_EN = 0x400 + // Position of CLK_EN field. + SYSCON_SYSCLK_CONF_CLK_EN_Pos = 0xb + // Bit mask of CLK_EN field. + SYSCON_SYSCLK_CONF_CLK_EN_Msk = 0x800 + // Bit CLK_EN. + SYSCON_SYSCLK_CONF_CLK_EN = 0x800 + // Position of RST_TICK_CNT field. + SYSCON_SYSCLK_CONF_RST_TICK_CNT_Pos = 0xc + // Bit mask of RST_TICK_CNT field. + SYSCON_SYSCLK_CONF_RST_TICK_CNT_Msk = 0x1000 + // Bit RST_TICK_CNT. + SYSCON_SYSCLK_CONF_RST_TICK_CNT = 0x1000 + + // TICK_CONF + // Position of XTAL_TICK_NUM field. + SYSCON_TICK_CONF_XTAL_TICK_NUM_Pos = 0x0 + // Bit mask of XTAL_TICK_NUM field. + SYSCON_TICK_CONF_XTAL_TICK_NUM_Msk = 0xff + // Position of CK8M_TICK_NUM field. + SYSCON_TICK_CONF_CK8M_TICK_NUM_Pos = 0x8 + // Bit mask of CK8M_TICK_NUM field. + SYSCON_TICK_CONF_CK8M_TICK_NUM_Msk = 0xff00 + // Position of TICK_ENABLE field. + SYSCON_TICK_CONF_TICK_ENABLE_Pos = 0x10 + // Bit mask of TICK_ENABLE field. + SYSCON_TICK_CONF_TICK_ENABLE_Msk = 0x10000 + // Bit TICK_ENABLE. + SYSCON_TICK_CONF_TICK_ENABLE = 0x10000 + + // CLK_OUT_EN + // Position of CLK20_OEN field. + SYSCON_CLK_OUT_EN_CLK20_OEN_Pos = 0x0 + // Bit mask of CLK20_OEN field. + SYSCON_CLK_OUT_EN_CLK20_OEN_Msk = 0x1 + // Bit CLK20_OEN. + SYSCON_CLK_OUT_EN_CLK20_OEN = 0x1 + // Position of CLK22_OEN field. + SYSCON_CLK_OUT_EN_CLK22_OEN_Pos = 0x1 + // Bit mask of CLK22_OEN field. + SYSCON_CLK_OUT_EN_CLK22_OEN_Msk = 0x2 + // Bit CLK22_OEN. + SYSCON_CLK_OUT_EN_CLK22_OEN = 0x2 + // Position of CLK44_OEN field. + SYSCON_CLK_OUT_EN_CLK44_OEN_Pos = 0x2 + // Bit mask of CLK44_OEN field. + SYSCON_CLK_OUT_EN_CLK44_OEN_Msk = 0x4 + // Bit CLK44_OEN. + SYSCON_CLK_OUT_EN_CLK44_OEN = 0x4 + // Position of CLK_BB_OEN field. + SYSCON_CLK_OUT_EN_CLK_BB_OEN_Pos = 0x3 + // Bit mask of CLK_BB_OEN field. + SYSCON_CLK_OUT_EN_CLK_BB_OEN_Msk = 0x8 + // Bit CLK_BB_OEN. + SYSCON_CLK_OUT_EN_CLK_BB_OEN = 0x8 + // Position of CLK80_OEN field. + SYSCON_CLK_OUT_EN_CLK80_OEN_Pos = 0x4 + // Bit mask of CLK80_OEN field. + SYSCON_CLK_OUT_EN_CLK80_OEN_Msk = 0x10 + // Bit CLK80_OEN. + SYSCON_CLK_OUT_EN_CLK80_OEN = 0x10 + // Position of CLK160_OEN field. + SYSCON_CLK_OUT_EN_CLK160_OEN_Pos = 0x5 + // Bit mask of CLK160_OEN field. + SYSCON_CLK_OUT_EN_CLK160_OEN_Msk = 0x20 + // Bit CLK160_OEN. + SYSCON_CLK_OUT_EN_CLK160_OEN = 0x20 + // Position of CLK_320M_OEN field. + SYSCON_CLK_OUT_EN_CLK_320M_OEN_Pos = 0x6 + // Bit mask of CLK_320M_OEN field. + SYSCON_CLK_OUT_EN_CLK_320M_OEN_Msk = 0x40 + // Bit CLK_320M_OEN. + SYSCON_CLK_OUT_EN_CLK_320M_OEN = 0x40 + // Position of CLK_ADC_INF_OEN field. + SYSCON_CLK_OUT_EN_CLK_ADC_INF_OEN_Pos = 0x7 + // Bit mask of CLK_ADC_INF_OEN field. + SYSCON_CLK_OUT_EN_CLK_ADC_INF_OEN_Msk = 0x80 + // Bit CLK_ADC_INF_OEN. + SYSCON_CLK_OUT_EN_CLK_ADC_INF_OEN = 0x80 + // Position of CLK_DAC_CPU_OEN field. + SYSCON_CLK_OUT_EN_CLK_DAC_CPU_OEN_Pos = 0x8 + // Bit mask of CLK_DAC_CPU_OEN field. + SYSCON_CLK_OUT_EN_CLK_DAC_CPU_OEN_Msk = 0x100 + // Bit CLK_DAC_CPU_OEN. + SYSCON_CLK_OUT_EN_CLK_DAC_CPU_OEN = 0x100 + // Position of CLK40X_BB_OEN field. + SYSCON_CLK_OUT_EN_CLK40X_BB_OEN_Pos = 0x9 + // Bit mask of CLK40X_BB_OEN field. + SYSCON_CLK_OUT_EN_CLK40X_BB_OEN_Msk = 0x200 + // Bit CLK40X_BB_OEN. + SYSCON_CLK_OUT_EN_CLK40X_BB_OEN = 0x200 + // Position of CLK_XTAL_OEN field. + SYSCON_CLK_OUT_EN_CLK_XTAL_OEN_Pos = 0xa + // Bit mask of CLK_XTAL_OEN field. + SYSCON_CLK_OUT_EN_CLK_XTAL_OEN_Msk = 0x400 + // Bit CLK_XTAL_OEN. + SYSCON_CLK_OUT_EN_CLK_XTAL_OEN = 0x400 + + // HOST_INF_SEL + // Position of PERI_IO_SWAP field. + SYSCON_HOST_INF_SEL_PERI_IO_SWAP_Pos = 0x0 + // Bit mask of PERI_IO_SWAP field. + SYSCON_HOST_INF_SEL_PERI_IO_SWAP_Msk = 0xff + + // EXT_MEM_PMS_LOCK + // Position of EXT_MEM_PMS_LOCK field. + SYSCON_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK_Pos = 0x0 + // Bit mask of EXT_MEM_PMS_LOCK field. + SYSCON_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK_Msk = 0x1 + // Bit EXT_MEM_PMS_LOCK. + SYSCON_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK = 0x1 + + // FLASH_ACE0_ATTR + // Position of FLASH_ACE0_ATTR field. + SYSCON_FLASH_ACE0_ATTR_FLASH_ACE0_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE0_ATTR field. + SYSCON_FLASH_ACE0_ATTR_FLASH_ACE0_ATTR_Msk = 0x7 + + // FLASH_ACE1_ATTR + // Position of FLASH_ACE1_ATTR field. + SYSCON_FLASH_ACE1_ATTR_FLASH_ACE1_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE1_ATTR field. + SYSCON_FLASH_ACE1_ATTR_FLASH_ACE1_ATTR_Msk = 0x7 + + // FLASH_ACE2_ATTR + // Position of FLASH_ACE2_ATTR field. + SYSCON_FLASH_ACE2_ATTR_FLASH_ACE2_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE2_ATTR field. + SYSCON_FLASH_ACE2_ATTR_FLASH_ACE2_ATTR_Msk = 0x7 + + // FLASH_ACE3_ATTR + // Position of FLASH_ACE3_ATTR field. + SYSCON_FLASH_ACE3_ATTR_FLASH_ACE3_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE3_ATTR field. + SYSCON_FLASH_ACE3_ATTR_FLASH_ACE3_ATTR_Msk = 0x7 + + // FLASH_ACE0_ADDR + // Position of S field. + SYSCON_FLASH_ACE0_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SYSCON_FLASH_ACE0_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE1_ADDR + // Position of S field. + SYSCON_FLASH_ACE1_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SYSCON_FLASH_ACE1_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE2_ADDR + // Position of S field. + SYSCON_FLASH_ACE2_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SYSCON_FLASH_ACE2_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE3_ADDR + // Position of S field. + SYSCON_FLASH_ACE3_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SYSCON_FLASH_ACE3_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE0_SIZE + // Position of FLASH_ACE0_SIZE field. + SYSCON_FLASH_ACE0_SIZE_FLASH_ACE0_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE0_SIZE field. + SYSCON_FLASH_ACE0_SIZE_FLASH_ACE0_SIZE_Msk = 0xffff + + // FLASH_ACE1_SIZE + // Position of FLASH_ACE1_SIZE field. + SYSCON_FLASH_ACE1_SIZE_FLASH_ACE1_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE1_SIZE field. + SYSCON_FLASH_ACE1_SIZE_FLASH_ACE1_SIZE_Msk = 0xffff + + // FLASH_ACE2_SIZE + // Position of FLASH_ACE2_SIZE field. + SYSCON_FLASH_ACE2_SIZE_FLASH_ACE2_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE2_SIZE field. + SYSCON_FLASH_ACE2_SIZE_FLASH_ACE2_SIZE_Msk = 0xffff + + // FLASH_ACE3_SIZE + // Position of FLASH_ACE3_SIZE field. + SYSCON_FLASH_ACE3_SIZE_FLASH_ACE3_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE3_SIZE field. + SYSCON_FLASH_ACE3_SIZE_FLASH_ACE3_SIZE_Msk = 0xffff + + // SRAM_ACE0_ATTR + // Position of SRAM_ACE0_ATTR field. + SYSCON_SRAM_ACE0_ATTR_SRAM_ACE0_ATTR_Pos = 0x0 + // Bit mask of SRAM_ACE0_ATTR field. + SYSCON_SRAM_ACE0_ATTR_SRAM_ACE0_ATTR_Msk = 0x7 + + // SRAM_ACE1_ATTR + // Position of SRAM_ACE1_ATTR field. + SYSCON_SRAM_ACE1_ATTR_SRAM_ACE1_ATTR_Pos = 0x0 + // Bit mask of SRAM_ACE1_ATTR field. + SYSCON_SRAM_ACE1_ATTR_SRAM_ACE1_ATTR_Msk = 0x7 + + // SRAM_ACE2_ATTR + // Position of SRAM_ACE2_ATTR field. + SYSCON_SRAM_ACE2_ATTR_SRAM_ACE2_ATTR_Pos = 0x0 + // Bit mask of SRAM_ACE2_ATTR field. + SYSCON_SRAM_ACE2_ATTR_SRAM_ACE2_ATTR_Msk = 0x7 + + // SRAM_ACE3_ATTR + // Position of SRAM_ACE3_ATTR field. + SYSCON_SRAM_ACE3_ATTR_SRAM_ACE3_ATTR_Pos = 0x0 + // Bit mask of SRAM_ACE3_ATTR field. + SYSCON_SRAM_ACE3_ATTR_SRAM_ACE3_ATTR_Msk = 0x7 + + // SRAM_ACE0_ADDR + // Position of S field. + SYSCON_SRAM_ACE0_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SYSCON_SRAM_ACE0_ADDR_S_Msk = 0xffffffff + + // SRAM_ACE1_ADDR + // Position of S field. + SYSCON_SRAM_ACE1_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SYSCON_SRAM_ACE1_ADDR_S_Msk = 0xffffffff + + // SRAM_ACE2_ADDR + // Position of S field. + SYSCON_SRAM_ACE2_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SYSCON_SRAM_ACE2_ADDR_S_Msk = 0xffffffff + + // SRAM_ACE3_ADDR + // Position of S field. + SYSCON_SRAM_ACE3_ADDR_S_Pos = 0x0 + // Bit mask of S field. + SYSCON_SRAM_ACE3_ADDR_S_Msk = 0xffffffff + + // SRAM_ACE0_SIZE + // Position of SRAM_ACE0_SIZE field. + SYSCON_SRAM_ACE0_SIZE_SRAM_ACE0_SIZE_Pos = 0x0 + // Bit mask of SRAM_ACE0_SIZE field. + SYSCON_SRAM_ACE0_SIZE_SRAM_ACE0_SIZE_Msk = 0xffff + + // SRAM_ACE1_SIZE + // Position of SRAM_ACE1_SIZE field. + SYSCON_SRAM_ACE1_SIZE_SRAM_ACE1_SIZE_Pos = 0x0 + // Bit mask of SRAM_ACE1_SIZE field. + SYSCON_SRAM_ACE1_SIZE_SRAM_ACE1_SIZE_Msk = 0xffff + + // SRAM_ACE2_SIZE + // Position of SRAM_ACE2_SIZE field. + SYSCON_SRAM_ACE2_SIZE_SRAM_ACE2_SIZE_Pos = 0x0 + // Bit mask of SRAM_ACE2_SIZE field. + SYSCON_SRAM_ACE2_SIZE_SRAM_ACE2_SIZE_Msk = 0xffff + + // SRAM_ACE3_SIZE + // Position of SRAM_ACE3_SIZE field. + SYSCON_SRAM_ACE3_SIZE_SRAM_ACE3_SIZE_Pos = 0x0 + // Bit mask of SRAM_ACE3_SIZE field. + SYSCON_SRAM_ACE3_SIZE_SRAM_ACE3_SIZE_Msk = 0xffff + + // SPI_MEM_PMS_CTRL + // Position of SPI_MEM_REJECT_INT field. + SYSCON_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_INT field. + SYSCON_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT_Msk = 0x1 + // Bit SPI_MEM_REJECT_INT. + SYSCON_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT = 0x1 + // Position of SPI_MEM_REJECT_CLR field. + SYSCON_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR_Pos = 0x1 + // Bit mask of SPI_MEM_REJECT_CLR field. + SYSCON_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR_Msk = 0x2 + // Bit SPI_MEM_REJECT_CLR. + SYSCON_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR = 0x2 + // Position of SPI_MEM_REJECT_CDE field. + SYSCON_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE_Pos = 0x2 + // Bit mask of SPI_MEM_REJECT_CDE field. + SYSCON_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE_Msk = 0x7c + + // SPI_MEM_REJECT_ADDR + // Position of SPI_MEM_REJECT_ADDR field. + SYSCON_SPI_MEM_REJECT_ADDR_SPI_MEM_REJECT_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_ADDR field. + SYSCON_SPI_MEM_REJECT_ADDR_SPI_MEM_REJECT_ADDR_Msk = 0xffffffff + + // SDIO_CTRL + // Position of SDIO_WIN_ACCESS_EN field. + SYSCON_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Pos = 0x0 + // Bit mask of SDIO_WIN_ACCESS_EN field. + SYSCON_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Msk = 0x1 + // Bit SDIO_WIN_ACCESS_EN. + SYSCON_SDIO_CTRL_SDIO_WIN_ACCESS_EN = 0x1 + + // REDCY_SIG0 + // Position of REDCY_SIG0 field. + SYSCON_REDCY_SIG0_REDCY_SIG0_Pos = 0x0 + // Bit mask of REDCY_SIG0 field. + SYSCON_REDCY_SIG0_REDCY_SIG0_Msk = 0x7fffffff + // Position of REDCY_ANDOR field. + SYSCON_REDCY_SIG0_REDCY_ANDOR_Pos = 0x1f + // Bit mask of REDCY_ANDOR field. + SYSCON_REDCY_SIG0_REDCY_ANDOR_Msk = 0x80000000 + // Bit REDCY_ANDOR. + SYSCON_REDCY_SIG0_REDCY_ANDOR = 0x80000000 + + // REDCY_SIG1 + // Position of REDCY_SIG1 field. + SYSCON_REDCY_SIG1_REDCY_SIG1_Pos = 0x0 + // Bit mask of REDCY_SIG1 field. + SYSCON_REDCY_SIG1_REDCY_SIG1_Msk = 0x7fffffff + // Position of REDCY_NANDOR field. + SYSCON_REDCY_SIG1_REDCY_NANDOR_Pos = 0x1f + // Bit mask of REDCY_NANDOR field. + SYSCON_REDCY_SIG1_REDCY_NANDOR_Msk = 0x80000000 + // Bit REDCY_NANDOR. + SYSCON_REDCY_SIG1_REDCY_NANDOR = 0x80000000 + + // WIFI_BB_CFG + // Position of WIFI_BB_CFG field. + SYSCON_WIFI_BB_CFG_WIFI_BB_CFG_Pos = 0x0 + // Bit mask of WIFI_BB_CFG field. + SYSCON_WIFI_BB_CFG_WIFI_BB_CFG_Msk = 0xffffffff + + // WIFI_BB_CFG_2 + // Position of WIFI_BB_CFG_2 field. + SYSCON_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Pos = 0x0 + // Bit mask of WIFI_BB_CFG_2 field. + SYSCON_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Msk = 0xffffffff + + // WIFI_CLK_EN + // Position of WIFI_CLK_EN field. + SYSCON_WIFI_CLK_EN_WIFI_CLK_EN_Pos = 0x0 + // Bit mask of WIFI_CLK_EN field. + SYSCON_WIFI_CLK_EN_WIFI_CLK_EN_Msk = 0xffffffff + + // WIFI_RST_EN + // Position of WIFI_RST field. + SYSCON_WIFI_RST_EN_WIFI_RST_Pos = 0x0 + // Bit mask of WIFI_RST field. + SYSCON_WIFI_RST_EN_WIFI_RST_Msk = 0xffffffff + + // FRONT_END_MEM_PD + // Position of AGC_MEM_FORCE_PU field. + SYSCON_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Pos = 0x0 + // Bit mask of AGC_MEM_FORCE_PU field. + SYSCON_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Msk = 0x1 + // Bit AGC_MEM_FORCE_PU. + SYSCON_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU = 0x1 + // Position of AGC_MEM_FORCE_PD field. + SYSCON_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of AGC_MEM_FORCE_PD field. + SYSCON_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Msk = 0x2 + // Bit AGC_MEM_FORCE_PD. + SYSCON_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD = 0x2 + // Position of PBUS_MEM_FORCE_PU field. + SYSCON_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of PBUS_MEM_FORCE_PU field. + SYSCON_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Msk = 0x4 + // Bit PBUS_MEM_FORCE_PU. + SYSCON_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU = 0x4 + // Position of PBUS_MEM_FORCE_PD field. + SYSCON_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of PBUS_MEM_FORCE_PD field. + SYSCON_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Msk = 0x8 + // Bit PBUS_MEM_FORCE_PD. + SYSCON_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD = 0x8 + // Position of DC_MEM_FORCE_PU field. + SYSCON_FRONT_END_MEM_PD_DC_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of DC_MEM_FORCE_PU field. + SYSCON_FRONT_END_MEM_PD_DC_MEM_FORCE_PU_Msk = 0x10 + // Bit DC_MEM_FORCE_PU. + SYSCON_FRONT_END_MEM_PD_DC_MEM_FORCE_PU = 0x10 + // Position of DC_MEM_FORCE_PD field. + SYSCON_FRONT_END_MEM_PD_DC_MEM_FORCE_PD_Pos = 0x5 + // Bit mask of DC_MEM_FORCE_PD field. + SYSCON_FRONT_END_MEM_PD_DC_MEM_FORCE_PD_Msk = 0x20 + // Bit DC_MEM_FORCE_PD. + SYSCON_FRONT_END_MEM_PD_DC_MEM_FORCE_PD = 0x20 + + // DATE + // Position of DATE field. + SYSCON_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SYSCON_DATE_DATE_Msk = 0xffffffff +) + +// Constants for SYSTEM: System Configuration Registers +const ( + // ROM_CTRL_0: System ROM configuration register 0 + // Position of ROM_FO field. + SYSTEM_ROM_CTRL_0_ROM_FO_Pos = 0x0 + // Bit mask of ROM_FO field. + SYSTEM_ROM_CTRL_0_ROM_FO_Msk = 0x3 + + // ROM_CTRL_1: System ROM configuration register 1 + // Position of ROM_FORCE_PD field. + SYSTEM_ROM_CTRL_1_ROM_FORCE_PD_Pos = 0x0 + // Bit mask of ROM_FORCE_PD field. + SYSTEM_ROM_CTRL_1_ROM_FORCE_PD_Msk = 0x3 + // Position of ROM_FORCE_PU field. + SYSTEM_ROM_CTRL_1_ROM_FORCE_PU_Pos = 0x2 + // Bit mask of ROM_FORCE_PU field. + SYSTEM_ROM_CTRL_1_ROM_FORCE_PU_Msk = 0xc + + // SRAM_CTRL_0: System SRAM configuration register 0 + // Position of SRAM_FO field. + SYSTEM_SRAM_CTRL_0_SRAM_FO_Pos = 0x0 + // Bit mask of SRAM_FO field. + SYSTEM_SRAM_CTRL_0_SRAM_FO_Msk = 0x3fffff + + // SRAM_CTRL_1: System SRAM configuration register 1 + // Position of SRAM_FORCE_PD field. + SYSTEM_SRAM_CTRL_1_SRAM_FORCE_PD_Pos = 0x0 + // Bit mask of SRAM_FORCE_PD field. + SYSTEM_SRAM_CTRL_1_SRAM_FORCE_PD_Msk = 0x3fffff + + // CPU_PERI_CLK_EN: CPU peripheral clock enable register + // Position of CLK_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO_Pos = 0x7 + // Bit mask of CLK_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO_Msk = 0x80 + // Bit CLK_EN_DEDICATED_GPIO. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO = 0x80 + + // CPU_PERI_RST_EN: CPU peripheral reset register + // Position of RST_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO_Pos = 0x7 + // Bit mask of RST_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO_Msk = 0x80 + // Bit RST_EN_DEDICATED_GPIO. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO = 0x80 + + // CPU_PER_CONF: CPU peripheral clock configuration register + // Position of CPUPERIOD_SEL field. + SYSTEM_CPU_PER_CONF_CPUPERIOD_SEL_Pos = 0x0 + // Bit mask of CPUPERIOD_SEL field. + SYSTEM_CPU_PER_CONF_CPUPERIOD_SEL_Msk = 0x3 + // Position of PLL_FREQ_SEL field. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL_Pos = 0x2 + // Bit mask of PLL_FREQ_SEL field. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL_Msk = 0x4 + // Bit PLL_FREQ_SEL. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL = 0x4 + // Position of CPU_WAIT_MODE_FORCE_ON field. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON_Pos = 0x3 + // Bit mask of CPU_WAIT_MODE_FORCE_ON field. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON_Msk = 0x8 + // Bit CPU_WAIT_MODE_FORCE_ON. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON = 0x8 + // Position of CPU_WAITI_DELAY_NUM field. + SYSTEM_CPU_PER_CONF_CPU_WAITI_DELAY_NUM_Pos = 0x4 + // Bit mask of CPU_WAITI_DELAY_NUM field. + SYSTEM_CPU_PER_CONF_CPU_WAITI_DELAY_NUM_Msk = 0xf0 + + // JTAG_CTRL_0: JTAG configuration register 0 + // Position of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 field. + SYSTEM_JTAG_CTRL_0_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_Pos = 0x0 + // Bit mask of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 field. + SYSTEM_JTAG_CTRL_0_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_Msk = 0xffffffff + + // JTAG_CTRL_1: JTAG configuration register 1 + // Position of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 field. + SYSTEM_JTAG_CTRL_1_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_Pos = 0x0 + // Bit mask of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 field. + SYSTEM_JTAG_CTRL_1_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_Msk = 0xffffffff + + // JTAG_CTRL_2: JTAG configuration register 2 + // Position of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 field. + SYSTEM_JTAG_CTRL_2_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_Pos = 0x0 + // Bit mask of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 field. + SYSTEM_JTAG_CTRL_2_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_Msk = 0xffffffff + + // JTAG_CTRL_3: JTAG configuration register 3 + // Position of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 field. + SYSTEM_JTAG_CTRL_3_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_Pos = 0x0 + // Bit mask of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 field. + SYSTEM_JTAG_CTRL_3_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_Msk = 0xffffffff + + // JTAG_CTRL_4: JTAG configuration register 4 + // Position of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 field. + SYSTEM_JTAG_CTRL_4_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_Pos = 0x0 + // Bit mask of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 field. + SYSTEM_JTAG_CTRL_4_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_Msk = 0xffffffff + + // JTAG_CTRL_5: JTAG configuration register 5 + // Position of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 field. + SYSTEM_JTAG_CTRL_5_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_Pos = 0x0 + // Bit mask of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 field. + SYSTEM_JTAG_CTRL_5_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_Msk = 0xffffffff + + // JTAG_CTRL_6: JTAG configuration register 6 + // Position of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 field. + SYSTEM_JTAG_CTRL_6_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_Pos = 0x0 + // Bit mask of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 field. + SYSTEM_JTAG_CTRL_6_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_Msk = 0xffffffff + + // JTAG_CTRL_7: JTAG configuration register 7 + // Position of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 field. + SYSTEM_JTAG_CTRL_7_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_Pos = 0x0 + // Bit mask of CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 field. + SYSTEM_JTAG_CTRL_7_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_Msk = 0xffffffff + + // MEM_PD_MASK: Memory power-related controlling register (under low-sleep) + // Position of LSLP_MEM_PD_MASK field. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK_Pos = 0x0 + // Bit mask of LSLP_MEM_PD_MASK field. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK_Msk = 0x1 + // Bit LSLP_MEM_PD_MASK. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK = 0x1 + + // PERIP_CLK_EN0: System peripheral clock (for hardware accelerators) enable register + // Position of TIMERS_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERS_CLK_EN_Pos = 0x0 + // Bit mask of TIMERS_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERS_CLK_EN_Msk = 0x1 + // Bit TIMERS_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERS_CLK_EN = 0x1 + // Position of SPI01_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN_Pos = 0x1 + // Bit mask of SPI01_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN_Msk = 0x2 + // Bit SPI01_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN = 0x2 + // Position of UART_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN_Pos = 0x2 + // Bit mask of UART_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN_Msk = 0x4 + // Bit UART_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN = 0x4 + // Position of WDG_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_WDG_CLK_EN_Pos = 0x3 + // Bit mask of WDG_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_WDG_CLK_EN_Msk = 0x8 + // Bit WDG_CLK_EN. + SYSTEM_PERIP_CLK_EN0_WDG_CLK_EN = 0x8 + // Position of I2S0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S0_CLK_EN_Pos = 0x4 + // Bit mask of I2S0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S0_CLK_EN_Msk = 0x10 + // Bit I2S0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2S0_CLK_EN = 0x10 + // Position of UART1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN_Pos = 0x5 + // Bit mask of UART1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN_Msk = 0x20 + // Bit UART1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN = 0x20 + // Position of SPI2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN_Pos = 0x6 + // Bit mask of SPI2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN_Msk = 0x40 + // Bit SPI2_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN = 0x40 + // Position of I2C_EXT0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN_Pos = 0x7 + // Bit mask of I2C_EXT0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN_Msk = 0x80 + // Bit I2C_EXT0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN = 0x80 + // Position of UHCI0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI0_CLK_EN_Pos = 0x8 + // Bit mask of UHCI0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI0_CLK_EN_Msk = 0x100 + // Bit UHCI0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UHCI0_CLK_EN = 0x100 + // Position of RMT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_RMT_CLK_EN_Pos = 0x9 + // Bit mask of RMT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_RMT_CLK_EN_Msk = 0x200 + // Bit RMT_CLK_EN. + SYSTEM_PERIP_CLK_EN0_RMT_CLK_EN = 0x200 + // Position of PCNT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PCNT_CLK_EN_Pos = 0xa + // Bit mask of PCNT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PCNT_CLK_EN_Msk = 0x400 + // Bit PCNT_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PCNT_CLK_EN = 0x400 + // Position of LEDC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN_Pos = 0xb + // Bit mask of LEDC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN_Msk = 0x800 + // Bit LEDC_CLK_EN. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN = 0x800 + // Position of UHCI1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI1_CLK_EN_Pos = 0xc + // Bit mask of UHCI1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI1_CLK_EN_Msk = 0x1000 + // Bit UHCI1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UHCI1_CLK_EN = 0x1000 + // Position of TIMERGROUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN_Pos = 0xd + // Bit mask of TIMERGROUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN_Msk = 0x2000 + // Bit TIMERGROUP_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN = 0x2000 + // Position of EFUSE_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_EFUSE_CLK_EN_Pos = 0xe + // Bit mask of EFUSE_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_EFUSE_CLK_EN_Msk = 0x4000 + // Bit EFUSE_CLK_EN. + SYSTEM_PERIP_CLK_EN0_EFUSE_CLK_EN = 0x4000 + // Position of TIMERGROUP1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP1_CLK_EN_Pos = 0xf + // Bit mask of TIMERGROUP1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP1_CLK_EN_Msk = 0x8000 + // Bit TIMERGROUP1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP1_CLK_EN = 0x8000 + // Position of SPI3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_CLK_EN_Pos = 0x10 + // Bit mask of SPI3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_CLK_EN_Msk = 0x10000 + // Bit SPI3_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI3_CLK_EN = 0x10000 + // Position of PWM0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM0_CLK_EN_Pos = 0x11 + // Bit mask of PWM0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM0_CLK_EN_Msk = 0x20000 + // Bit PWM0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM0_CLK_EN = 0x20000 + // Position of I2C_EXT1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT1_CLK_EN_Pos = 0x12 + // Bit mask of I2C_EXT1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT1_CLK_EN_Msk = 0x40000 + // Bit I2C_EXT1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2C_EXT1_CLK_EN = 0x40000 + // Position of TWAI_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TWAI_CLK_EN_Pos = 0x13 + // Bit mask of TWAI_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TWAI_CLK_EN_Msk = 0x80000 + // Bit TWAI_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TWAI_CLK_EN = 0x80000 + // Position of PWM1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM1_CLK_EN_Pos = 0x14 + // Bit mask of PWM1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM1_CLK_EN_Msk = 0x100000 + // Bit PWM1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM1_CLK_EN = 0x100000 + // Position of I2S1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S1_CLK_EN_Pos = 0x15 + // Bit mask of I2S1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S1_CLK_EN_Msk = 0x200000 + // Bit I2S1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2S1_CLK_EN = 0x200000 + // Position of SPI2_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_DMA_CLK_EN_Pos = 0x16 + // Bit mask of SPI2_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_DMA_CLK_EN_Msk = 0x400000 + // Bit SPI2_DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI2_DMA_CLK_EN = 0x400000 + // Position of USB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_USB_CLK_EN_Pos = 0x17 + // Bit mask of USB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_USB_CLK_EN_Msk = 0x800000 + // Bit USB_CLK_EN. + SYSTEM_PERIP_CLK_EN0_USB_CLK_EN = 0x800000 + // Position of UART_MEM_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN_Pos = 0x18 + // Bit mask of UART_MEM_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN_Msk = 0x1000000 + // Bit UART_MEM_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN = 0x1000000 + // Position of PWM2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM2_CLK_EN_Pos = 0x19 + // Bit mask of PWM2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM2_CLK_EN_Msk = 0x2000000 + // Bit PWM2_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM2_CLK_EN = 0x2000000 + // Position of PWM3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM3_CLK_EN_Pos = 0x1a + // Bit mask of PWM3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM3_CLK_EN_Msk = 0x4000000 + // Bit PWM3_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM3_CLK_EN = 0x4000000 + // Position of SPI3_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_DMA_CLK_EN_Pos = 0x1b + // Bit mask of SPI3_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_DMA_CLK_EN_Msk = 0x8000000 + // Bit SPI3_DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI3_DMA_CLK_EN = 0x8000000 + // Position of APB_SARADC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN_Pos = 0x1c + // Bit mask of APB_SARADC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN_Msk = 0x10000000 + // Bit APB_SARADC_CLK_EN. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN = 0x10000000 + // Position of SYSTIMER_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN_Pos = 0x1d + // Bit mask of SYSTIMER_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN_Msk = 0x20000000 + // Bit SYSTIMER_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN = 0x20000000 + // Position of ADC2_ARB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN_Pos = 0x1e + // Bit mask of ADC2_ARB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN_Msk = 0x40000000 + // Bit ADC2_ARB_CLK_EN. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN = 0x40000000 + // Position of SPI4_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI4_CLK_EN_Pos = 0x1f + // Bit mask of SPI4_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI4_CLK_EN_Msk = 0x80000000 + // Bit SPI4_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI4_CLK_EN = 0x80000000 + + // PERIP_CLK_EN1: System peripheral clock (for hardware accelerators) enable register 1 + // Position of CRYPTO_AES_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_AES_CLK_EN_Pos = 0x1 + // Bit mask of CRYPTO_AES_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_AES_CLK_EN_Msk = 0x2 + // Bit CRYPTO_AES_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_AES_CLK_EN = 0x2 + // Position of CRYPTO_SHA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN_Pos = 0x2 + // Bit mask of CRYPTO_SHA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN_Msk = 0x4 + // Bit CRYPTO_SHA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN = 0x4 + // Position of CRYPTO_RSA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_RSA_CLK_EN_Pos = 0x3 + // Bit mask of CRYPTO_RSA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_RSA_CLK_EN_Msk = 0x8 + // Bit CRYPTO_RSA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_RSA_CLK_EN = 0x8 + // Position of CRYPTO_DS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DS_CLK_EN_Pos = 0x4 + // Bit mask of CRYPTO_DS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DS_CLK_EN_Msk = 0x10 + // Bit CRYPTO_DS_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DS_CLK_EN = 0x10 + // Position of CRYPTO_HMAC_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN_Pos = 0x5 + // Bit mask of CRYPTO_HMAC_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN_Msk = 0x20 + // Bit CRYPTO_HMAC_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN = 0x20 + // Position of CRYPTO_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DMA_CLK_EN_Pos = 0x6 + // Bit mask of CRYPTO_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DMA_CLK_EN_Msk = 0x40 + // Bit CRYPTO_DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DMA_CLK_EN = 0x40 + + // PERIP_RST_EN0: System peripheral (hardware accelerators) reset register 0 + // Position of TIMERS_RST field. + SYSTEM_PERIP_RST_EN0_TIMERS_RST_Pos = 0x0 + // Bit mask of TIMERS_RST field. + SYSTEM_PERIP_RST_EN0_TIMERS_RST_Msk = 0x1 + // Bit TIMERS_RST. + SYSTEM_PERIP_RST_EN0_TIMERS_RST = 0x1 + // Position of SPI01_RST field. + SYSTEM_PERIP_RST_EN0_SPI01_RST_Pos = 0x1 + // Bit mask of SPI01_RST field. + SYSTEM_PERIP_RST_EN0_SPI01_RST_Msk = 0x2 + // Bit SPI01_RST. + SYSTEM_PERIP_RST_EN0_SPI01_RST = 0x2 + // Position of UART_RST field. + SYSTEM_PERIP_RST_EN0_UART_RST_Pos = 0x2 + // Bit mask of UART_RST field. + SYSTEM_PERIP_RST_EN0_UART_RST_Msk = 0x4 + // Bit UART_RST. + SYSTEM_PERIP_RST_EN0_UART_RST = 0x4 + // Position of WDG_RST field. + SYSTEM_PERIP_RST_EN0_WDG_RST_Pos = 0x3 + // Bit mask of WDG_RST field. + SYSTEM_PERIP_RST_EN0_WDG_RST_Msk = 0x8 + // Bit WDG_RST. + SYSTEM_PERIP_RST_EN0_WDG_RST = 0x8 + // Position of I2S0_RST field. + SYSTEM_PERIP_RST_EN0_I2S0_RST_Pos = 0x4 + // Bit mask of I2S0_RST field. + SYSTEM_PERIP_RST_EN0_I2S0_RST_Msk = 0x10 + // Bit I2S0_RST. + SYSTEM_PERIP_RST_EN0_I2S0_RST = 0x10 + // Position of UART1_RST field. + SYSTEM_PERIP_RST_EN0_UART1_RST_Pos = 0x5 + // Bit mask of UART1_RST field. + SYSTEM_PERIP_RST_EN0_UART1_RST_Msk = 0x20 + // Bit UART1_RST. + SYSTEM_PERIP_RST_EN0_UART1_RST = 0x20 + // Position of SPI2_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_RST_Pos = 0x6 + // Bit mask of SPI2_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_RST_Msk = 0x40 + // Bit SPI2_RST. + SYSTEM_PERIP_RST_EN0_SPI2_RST = 0x40 + // Position of I2C_EXT0_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST_Pos = 0x7 + // Bit mask of I2C_EXT0_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST_Msk = 0x80 + // Bit I2C_EXT0_RST. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST = 0x80 + // Position of UHCI0_RST field. + SYSTEM_PERIP_RST_EN0_UHCI0_RST_Pos = 0x8 + // Bit mask of UHCI0_RST field. + SYSTEM_PERIP_RST_EN0_UHCI0_RST_Msk = 0x100 + // Bit UHCI0_RST. + SYSTEM_PERIP_RST_EN0_UHCI0_RST = 0x100 + // Position of RMT_RST field. + SYSTEM_PERIP_RST_EN0_RMT_RST_Pos = 0x9 + // Bit mask of RMT_RST field. + SYSTEM_PERIP_RST_EN0_RMT_RST_Msk = 0x200 + // Bit RMT_RST. + SYSTEM_PERIP_RST_EN0_RMT_RST = 0x200 + // Position of PCNT_RST field. + SYSTEM_PERIP_RST_EN0_PCNT_RST_Pos = 0xa + // Bit mask of PCNT_RST field. + SYSTEM_PERIP_RST_EN0_PCNT_RST_Msk = 0x400 + // Bit PCNT_RST. + SYSTEM_PERIP_RST_EN0_PCNT_RST = 0x400 + // Position of LEDC_RST field. + SYSTEM_PERIP_RST_EN0_LEDC_RST_Pos = 0xb + // Bit mask of LEDC_RST field. + SYSTEM_PERIP_RST_EN0_LEDC_RST_Msk = 0x800 + // Bit LEDC_RST. + SYSTEM_PERIP_RST_EN0_LEDC_RST = 0x800 + // Position of UHCI1_RST field. + SYSTEM_PERIP_RST_EN0_UHCI1_RST_Pos = 0xc + // Bit mask of UHCI1_RST field. + SYSTEM_PERIP_RST_EN0_UHCI1_RST_Msk = 0x1000 + // Bit UHCI1_RST. + SYSTEM_PERIP_RST_EN0_UHCI1_RST = 0x1000 + // Position of TIMERGROUP_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST_Pos = 0xd + // Bit mask of TIMERGROUP_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST_Msk = 0x2000 + // Bit TIMERGROUP_RST. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST = 0x2000 + // Position of EFUSE_RST field. + SYSTEM_PERIP_RST_EN0_EFUSE_RST_Pos = 0xe + // Bit mask of EFUSE_RST field. + SYSTEM_PERIP_RST_EN0_EFUSE_RST_Msk = 0x4000 + // Bit EFUSE_RST. + SYSTEM_PERIP_RST_EN0_EFUSE_RST = 0x4000 + // Position of TIMERGROUP1_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP1_RST_Pos = 0xf + // Bit mask of TIMERGROUP1_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP1_RST_Msk = 0x8000 + // Bit TIMERGROUP1_RST. + SYSTEM_PERIP_RST_EN0_TIMERGROUP1_RST = 0x8000 + // Position of SPI3_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_RST_Pos = 0x10 + // Bit mask of SPI3_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_RST_Msk = 0x10000 + // Bit SPI3_RST. + SYSTEM_PERIP_RST_EN0_SPI3_RST = 0x10000 + // Position of PWM0_RST field. + SYSTEM_PERIP_RST_EN0_PWM0_RST_Pos = 0x11 + // Bit mask of PWM0_RST field. + SYSTEM_PERIP_RST_EN0_PWM0_RST_Msk = 0x20000 + // Bit PWM0_RST. + SYSTEM_PERIP_RST_EN0_PWM0_RST = 0x20000 + // Position of I2C_EXT1_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT1_RST_Pos = 0x12 + // Bit mask of I2C_EXT1_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT1_RST_Msk = 0x40000 + // Bit I2C_EXT1_RST. + SYSTEM_PERIP_RST_EN0_I2C_EXT1_RST = 0x40000 + // Position of TWAI_RST field. + SYSTEM_PERIP_RST_EN0_TWAI_RST_Pos = 0x13 + // Bit mask of TWAI_RST field. + SYSTEM_PERIP_RST_EN0_TWAI_RST_Msk = 0x80000 + // Bit TWAI_RST. + SYSTEM_PERIP_RST_EN0_TWAI_RST = 0x80000 + // Position of PWM1_RST field. + SYSTEM_PERIP_RST_EN0_PWM1_RST_Pos = 0x14 + // Bit mask of PWM1_RST field. + SYSTEM_PERIP_RST_EN0_PWM1_RST_Msk = 0x100000 + // Bit PWM1_RST. + SYSTEM_PERIP_RST_EN0_PWM1_RST = 0x100000 + // Position of I2S1_RST field. + SYSTEM_PERIP_RST_EN0_I2S1_RST_Pos = 0x15 + // Bit mask of I2S1_RST field. + SYSTEM_PERIP_RST_EN0_I2S1_RST_Msk = 0x200000 + // Bit I2S1_RST. + SYSTEM_PERIP_RST_EN0_I2S1_RST = 0x200000 + // Position of SPI2_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_DMA_RST_Pos = 0x16 + // Bit mask of SPI2_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_DMA_RST_Msk = 0x400000 + // Bit SPI2_DMA_RST. + SYSTEM_PERIP_RST_EN0_SPI2_DMA_RST = 0x400000 + // Position of USB_RST field. + SYSTEM_PERIP_RST_EN0_USB_RST_Pos = 0x17 + // Bit mask of USB_RST field. + SYSTEM_PERIP_RST_EN0_USB_RST_Msk = 0x800000 + // Bit USB_RST. + SYSTEM_PERIP_RST_EN0_USB_RST = 0x800000 + // Position of UART_MEM_RST field. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST_Pos = 0x18 + // Bit mask of UART_MEM_RST field. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST_Msk = 0x1000000 + // Bit UART_MEM_RST. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST = 0x1000000 + // Position of PWM2_RST field. + SYSTEM_PERIP_RST_EN0_PWM2_RST_Pos = 0x19 + // Bit mask of PWM2_RST field. + SYSTEM_PERIP_RST_EN0_PWM2_RST_Msk = 0x2000000 + // Bit PWM2_RST. + SYSTEM_PERIP_RST_EN0_PWM2_RST = 0x2000000 + // Position of PWM3_RST field. + SYSTEM_PERIP_RST_EN0_PWM3_RST_Pos = 0x1a + // Bit mask of PWM3_RST field. + SYSTEM_PERIP_RST_EN0_PWM3_RST_Msk = 0x4000000 + // Bit PWM3_RST. + SYSTEM_PERIP_RST_EN0_PWM3_RST = 0x4000000 + // Position of SPI3_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_DMA_RST_Pos = 0x1b + // Bit mask of SPI3_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_DMA_RST_Msk = 0x8000000 + // Bit SPI3_DMA_RST. + SYSTEM_PERIP_RST_EN0_SPI3_DMA_RST = 0x8000000 + // Position of APB_SARADC_RST field. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST_Pos = 0x1c + // Bit mask of APB_SARADC_RST field. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST_Msk = 0x10000000 + // Bit APB_SARADC_RST. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST = 0x10000000 + // Position of SYSTIMER_RST field. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST_Pos = 0x1d + // Bit mask of SYSTIMER_RST field. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST_Msk = 0x20000000 + // Bit SYSTIMER_RST. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST = 0x20000000 + // Position of ADC2_ARB_RST field. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST_Pos = 0x1e + // Bit mask of ADC2_ARB_RST field. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST_Msk = 0x40000000 + // Bit ADC2_ARB_RST. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST = 0x40000000 + // Position of SPI4_RST field. + SYSTEM_PERIP_RST_EN0_SPI4_RST_Pos = 0x1f + // Bit mask of SPI4_RST field. + SYSTEM_PERIP_RST_EN0_SPI4_RST_Msk = 0x80000000 + // Bit SPI4_RST. + SYSTEM_PERIP_RST_EN0_SPI4_RST = 0x80000000 + + // PERIP_RST_EN1: System peripheral (hardware accelerators) reset register 1 + // Position of CRYPTO_AES_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_AES_RST_Pos = 0x1 + // Bit mask of CRYPTO_AES_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_AES_RST_Msk = 0x2 + // Bit CRYPTO_AES_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_AES_RST = 0x2 + // Position of CRYPTO_SHA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST_Pos = 0x2 + // Bit mask of CRYPTO_SHA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST_Msk = 0x4 + // Bit CRYPTO_SHA_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST = 0x4 + // Position of CRYPTO_RSA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_RSA_RST_Pos = 0x3 + // Bit mask of CRYPTO_RSA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_RSA_RST_Msk = 0x8 + // Bit CRYPTO_RSA_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_RSA_RST = 0x8 + // Position of CRYPTO_DS_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_DS_RST_Pos = 0x4 + // Bit mask of CRYPTO_DS_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_DS_RST_Msk = 0x10 + // Bit CRYPTO_DS_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_DS_RST = 0x10 + // Position of CRYPTO_HMAC_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_HMAC_RST_Pos = 0x5 + // Bit mask of CRYPTO_HMAC_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_HMAC_RST_Msk = 0x20 + // Bit CRYPTO_HMAC_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_HMAC_RST = 0x20 + // Position of CRYPTO_DMA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_DMA_RST_Pos = 0x6 + // Bit mask of CRYPTO_DMA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_DMA_RST_Msk = 0x40 + // Bit CRYPTO_DMA_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_DMA_RST = 0x40 + + // LPCK_DIV_INT: Low power clock divider integer register + // Position of LPCK_DIV_NUM field. + SYSTEM_LPCK_DIV_INT_LPCK_DIV_NUM_Pos = 0x0 + // Bit mask of LPCK_DIV_NUM field. + SYSTEM_LPCK_DIV_INT_LPCK_DIV_NUM_Msk = 0xfff + + // BT_LPCK_DIV_FRAC: Divider fraction configuration register for low-power clock + // Position of LPCLK_SEL_RTC_SLOW field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Pos = 0x18 + // Bit mask of LPCLK_SEL_RTC_SLOW field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Msk = 0x1000000 + // Bit LPCLK_SEL_RTC_SLOW. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW = 0x1000000 + // Position of LPCLK_SEL_8M field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Pos = 0x19 + // Bit mask of LPCLK_SEL_8M field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Msk = 0x2000000 + // Bit LPCLK_SEL_8M. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M = 0x2000000 + // Position of LPCLK_SEL_XTAL field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Pos = 0x1a + // Bit mask of LPCLK_SEL_XTAL field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Msk = 0x4000000 + // Bit LPCLK_SEL_XTAL. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL = 0x4000000 + // Position of LPCLK_SEL_XTAL32K field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Pos = 0x1b + // Bit mask of LPCLK_SEL_XTAL32K field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Msk = 0x8000000 + // Bit LPCLK_SEL_XTAL32K. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K = 0x8000000 + // Position of LPCLK_RTC_EN field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN_Pos = 0x1c + // Bit mask of LPCLK_RTC_EN field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN_Msk = 0x10000000 + // Bit LPCLK_RTC_EN. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN = 0x10000000 + + // CPU_INTR_FROM_CPU_0: CPU interrupt controlling register 0 + // Position of CPU_INTR_FROM_CPU_0 field. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0 field. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_0. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0 = 0x1 + + // CPU_INTR_FROM_CPU_1: CPU interrupt controlling register 1 + // Position of CPU_INTR_FROM_CPU_1 field. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1 field. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_1. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1 = 0x1 + + // CPU_INTR_FROM_CPU_2: CPU interrupt controlling register 2 + // Position of CPU_INTR_FROM_CPU_2 field. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2 field. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_2. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2 = 0x1 + + // CPU_INTR_FROM_CPU_3: CPU interrupt controlling register 3 + // Position of CPU_INTR_FROM_CPU_3 field. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3 field. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_3. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3 = 0x1 + + // RSA_PD_CTRL: RSA memory remapping register + // Position of RSA_MEM_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD_Pos = 0x0 + // Bit mask of RSA_MEM_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD_Msk = 0x1 + // Bit RSA_MEM_PD. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD = 0x1 + // Position of RSA_MEM_FORCE_PU field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of RSA_MEM_FORCE_PU field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Msk = 0x2 + // Bit RSA_MEM_FORCE_PU. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU = 0x2 + // Position of RSA_MEM_FORCE_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of RSA_MEM_FORCE_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Msk = 0x4 + // Bit RSA_MEM_FORCE_PD. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD = 0x4 + + // BUSTOEXTMEM_ENA: EDMA enable register + // Position of BUSTOEXTMEM_ENA field. + SYSTEM_BUSTOEXTMEM_ENA_BUSTOEXTMEM_ENA_Pos = 0x0 + // Bit mask of BUSTOEXTMEM_ENA field. + SYSTEM_BUSTOEXTMEM_ENA_BUSTOEXTMEM_ENA_Msk = 0x1 + // Bit BUSTOEXTMEM_ENA. + SYSTEM_BUSTOEXTMEM_ENA_BUSTOEXTMEM_ENA = 0x1 + + // CACHE_CONTROL: Cache control register + // Position of PRO_ICACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_PRO_ICACHE_CLK_ON_Pos = 0x0 + // Bit mask of PRO_ICACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_PRO_ICACHE_CLK_ON_Msk = 0x1 + // Bit PRO_ICACHE_CLK_ON. + SYSTEM_CACHE_CONTROL_PRO_ICACHE_CLK_ON = 0x1 + // Position of PRO_DCACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_PRO_DCACHE_CLK_ON_Pos = 0x1 + // Bit mask of PRO_DCACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_PRO_DCACHE_CLK_ON_Msk = 0x2 + // Bit PRO_DCACHE_CLK_ON. + SYSTEM_CACHE_CONTROL_PRO_DCACHE_CLK_ON = 0x2 + // Position of PRO_CACHE_RESET field. + SYSTEM_CACHE_CONTROL_PRO_CACHE_RESET_Pos = 0x2 + // Bit mask of PRO_CACHE_RESET field. + SYSTEM_CACHE_CONTROL_PRO_CACHE_RESET_Msk = 0x4 + // Bit PRO_CACHE_RESET. + SYSTEM_CACHE_CONTROL_PRO_CACHE_RESET = 0x4 + + // EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: External memory encrypt and decrypt controlling register + // Position of ENABLE_SPI_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Pos = 0x0 + // Bit mask of ENABLE_SPI_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Msk = 0x1 + // Bit ENABLE_SPI_MANUAL_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT = 0x1 + // Position of ENABLE_DOWNLOAD_DB_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Pos = 0x1 + // Bit mask of ENABLE_DOWNLOAD_DB_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Msk = 0x2 + // Bit ENABLE_DOWNLOAD_DB_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT = 0x2 + // Position of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Pos = 0x2 + // Bit mask of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Msk = 0x4 + // Bit ENABLE_DOWNLOAD_G0CB_DECRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT = 0x4 + // Position of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x3 + // Bit mask of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x8 + // Bit ENABLE_DOWNLOAD_MANUAL_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT = 0x8 + + // RTC_FASTMEM_CONFIG: RTC fast memory configuration register + // Position of RTC_MEM_CRC_START field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START_Pos = 0x8 + // Bit mask of RTC_MEM_CRC_START field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START_Msk = 0x100 + // Bit RTC_MEM_CRC_START. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START = 0x100 + // Position of RTC_MEM_CRC_ADDR field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR_Pos = 0x9 + // Bit mask of RTC_MEM_CRC_ADDR field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR_Msk = 0xffe00 + // Position of RTC_MEM_CRC_LEN field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN_Pos = 0x14 + // Bit mask of RTC_MEM_CRC_LEN field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN_Msk = 0x7ff00000 + // Position of RTC_MEM_CRC_FINISH field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH_Pos = 0x1f + // Bit mask of RTC_MEM_CRC_FINISH field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH_Msk = 0x80000000 + // Bit RTC_MEM_CRC_FINISH. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH = 0x80000000 + + // RTC_FASTMEM_CRC: RTC fast memory CRC controlling register + // Position of RTC_MEM_CRC_RES field. + SYSTEM_RTC_FASTMEM_CRC_RTC_MEM_CRC_RES_Pos = 0x0 + // Bit mask of RTC_MEM_CRC_RES field. + SYSTEM_RTC_FASTMEM_CRC_RTC_MEM_CRC_RES_Msk = 0xffffffff + + // Redundant_ECO_Ctrl: Redundant ECO control register + // Position of REDUNDANT_ECO_DRIVE field. + SYSTEM_Redundant_ECO_Ctrl_REDUNDANT_ECO_DRIVE_Pos = 0x0 + // Bit mask of REDUNDANT_ECO_DRIVE field. + SYSTEM_Redundant_ECO_Ctrl_REDUNDANT_ECO_DRIVE_Msk = 0x1 + // Bit REDUNDANT_ECO_DRIVE. + SYSTEM_Redundant_ECO_Ctrl_REDUNDANT_ECO_DRIVE = 0x1 + // Position of REDUNDANT_ECO_RESULT field. + SYSTEM_Redundant_ECO_Ctrl_REDUNDANT_ECO_RESULT_Pos = 0x1 + // Bit mask of REDUNDANT_ECO_RESULT field. + SYSTEM_Redundant_ECO_Ctrl_REDUNDANT_ECO_RESULT_Msk = 0x2 + // Bit REDUNDANT_ECO_RESULT. + SYSTEM_Redundant_ECO_Ctrl_REDUNDANT_ECO_RESULT = 0x2 + + // CLOCK_GATE: Clock gate control register + // Position of CLK_EN field. + SYSTEM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SYSTEM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SYSTEM_CLOCK_GATE_CLK_EN = 0x1 + + // SRAM_CTRL_2: System SRAM configuration register 2 + // Position of SRAM_FORCE_PU field. + SYSTEM_SRAM_CTRL_2_SRAM_FORCE_PU_Pos = 0x0 + // Bit mask of SRAM_FORCE_PU field. + SYSTEM_SRAM_CTRL_2_SRAM_FORCE_PU_Msk = 0x3fffff + + // SYSCLK_CONF: SoC clock configuration register + // Position of PRE_DIV_CNT field. + SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_Pos = 0x0 + // Bit mask of PRE_DIV_CNT field. + SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_Msk = 0x3ff + // Position of SOC_CLK_SEL field. + SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_Pos = 0xa + // Bit mask of SOC_CLK_SEL field. + SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_Msk = 0xc00 + // Position of CLK_XTAL_FREQ field. + SYSTEM_SYSCLK_CONF_CLK_XTAL_FREQ_Pos = 0xc + // Bit mask of CLK_XTAL_FREQ field. + SYSTEM_SYSCLK_CONF_CLK_XTAL_FREQ_Msk = 0x7f000 + // Position of CLK_DIV_EN field. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN_Pos = 0x13 + // Bit mask of CLK_DIV_EN field. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN_Msk = 0x80000 + // Bit CLK_DIV_EN. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN = 0x80000 + + // DATE: Version control register + // Position of DATE field. + SYSTEM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SYSTEM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SYSTIMER: System Timer +const ( + // CONF: Configure system timer clock + // Position of CLK_FO field. + SYSTIMER_CONF_CLK_FO_Pos = 0x0 + // Bit mask of CLK_FO field. + SYSTIMER_CONF_CLK_FO_Msk = 0x1 + // Bit CLK_FO. + SYSTIMER_CONF_CLK_FO = 0x1 + // Position of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + SYSTIMER_CONF_CLK_EN = 0x80000000 + + // LOAD: Load value to system timer + // Position of TIMER_LOAD field. + SYSTIMER_LOAD_TIMER_LOAD_Pos = 0x1f + // Bit mask of TIMER_LOAD field. + SYSTIMER_LOAD_TIMER_LOAD_Msk = 0x80000000 + // Bit TIMER_LOAD. + SYSTIMER_LOAD_TIMER_LOAD = 0x80000000 + + // LOAD_HI: High 32 bits to be loaded to system timer + // Position of TIMER_LOAD_HI field. + SYSTIMER_LOAD_HI_TIMER_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_LOAD_HI field. + SYSTIMER_LOAD_HI_TIMER_LOAD_HI_Msk = 0xffffffff + + // LOAD_LO: Low 32 bits to be loaded to system timer + // Position of TIMER_LOAD_LO field. + SYSTIMER_LOAD_LO_TIMER_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_LOAD_LO field. + SYSTIMER_LOAD_LO_TIMER_LOAD_LO_Msk = 0xffffffff + + // STEP: System timer accumulation step + // Position of TIMER_XTAL_STEP field. + SYSTIMER_STEP_TIMER_XTAL_STEP_Pos = 0x0 + // Bit mask of TIMER_XTAL_STEP field. + SYSTIMER_STEP_TIMER_XTAL_STEP_Msk = 0x3ff + // Position of TIMER_PLL_STEP field. + SYSTIMER_STEP_TIMER_PLL_STEP_Pos = 0xa + // Bit mask of TIMER_PLL_STEP field. + SYSTIMER_STEP_TIMER_PLL_STEP_Msk = 0xffc00 + + // TARGET0_HI: System timer target 0, high 32 bits + // Position of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Msk = 0xffffffff + + // TARGET0_LO: System timer target 0, low 32 bits + // Position of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Msk = 0xffffffff + + // TARGET1_HI: System timer target 1, high 32 bits + // Position of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Msk = 0xffffffff + + // TARGET1_LO: System timer target 1, low 32 bits + // Position of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Msk = 0xffffffff + + // TARGET2_HI: System timer target 2, high 32 bits + // Position of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Msk = 0xffffffff + + // TARGET2_LO: System timer target 2, low 32 bits + // Position of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Msk = 0xffffffff + + // TARGET0_CONF: Configure work mode for system timer target 0 + // Position of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Pos = 0x0 + // Bit mask of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Msk = 0x3fffffff + // Position of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET0_PERIOD_MODE. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE = 0x40000000 + // Position of TARGET0_WORK_EN field. + SYSTIMER_TARGET0_CONF_TARGET0_WORK_EN_Pos = 0x1f + // Bit mask of TARGET0_WORK_EN field. + SYSTIMER_TARGET0_CONF_TARGET0_WORK_EN_Msk = 0x80000000 + // Bit TARGET0_WORK_EN. + SYSTIMER_TARGET0_CONF_TARGET0_WORK_EN = 0x80000000 + + // TARGET1_CONF: Configure work mode for system timer target 1 + // Position of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Pos = 0x0 + // Bit mask of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Msk = 0x3fffffff + // Position of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET1_PERIOD_MODE. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE = 0x40000000 + // Position of TARGET1_WORK_EN field. + SYSTIMER_TARGET1_CONF_TARGET1_WORK_EN_Pos = 0x1f + // Bit mask of TARGET1_WORK_EN field. + SYSTIMER_TARGET1_CONF_TARGET1_WORK_EN_Msk = 0x80000000 + // Bit TARGET1_WORK_EN. + SYSTIMER_TARGET1_CONF_TARGET1_WORK_EN = 0x80000000 + + // TARGET2_CONF: Configure work mode for system timer target 2 + // Position of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Pos = 0x0 + // Bit mask of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Msk = 0x3fffffff + // Position of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET2_PERIOD_MODE. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE = 0x40000000 + // Position of TARGET2_WORK_EN field. + SYSTIMER_TARGET2_CONF_TARGET2_WORK_EN_Pos = 0x1f + // Bit mask of TARGET2_WORK_EN field. + SYSTIMER_TARGET2_CONF_TARGET2_WORK_EN_Msk = 0x80000000 + // Bit TARGET2_WORK_EN. + SYSTIMER_TARGET2_CONF_TARGET2_WORK_EN = 0x80000000 + + // UNIT0_OP: Read out system timer value + // Position of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Pos = 0x1e + // Bit mask of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Msk = 0x40000000 + // Bit TIMER_UNIT0_VALUE_VALID. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID = 0x40000000 + // Position of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Pos = 0x1f + // Bit mask of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Msk = 0x80000000 + // Bit TIMER_UNIT0_UPDATE. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE = 0x80000000 + + // UNIT0_VALUE_HI: System timer value, high 32 bits + // Position of TIMER_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_VALUE_HI_Msk = 0xffffffff + + // UNIT0_VALUE_LO: System timer value, low 32 bits + // Position of TIMER_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_VALUE_LO_Msk = 0xffffffff + + // INT_ENA: System timer interrupt enable + // Position of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Pos = 0x0 + // Bit mask of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Msk = 0x1 + // Bit TARGET0_INT_ENA. + SYSTIMER_INT_ENA_TARGET0_INT_ENA = 0x1 + // Position of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Pos = 0x1 + // Bit mask of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Msk = 0x2 + // Bit TARGET1_INT_ENA. + SYSTIMER_INT_ENA_TARGET1_INT_ENA = 0x2 + // Position of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Pos = 0x2 + // Bit mask of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Msk = 0x4 + // Bit TARGET2_INT_ENA. + SYSTIMER_INT_ENA_TARGET2_INT_ENA = 0x4 + + // INT_RAW: System timer interrupt raw + // Position of INT0_RAW field. + SYSTIMER_INT_RAW_INT0_RAW_Pos = 0x0 + // Bit mask of INT0_RAW field. + SYSTIMER_INT_RAW_INT0_RAW_Msk = 0x1 + // Bit INT0_RAW. + SYSTIMER_INT_RAW_INT0_RAW = 0x1 + // Position of INT1_RAW field. + SYSTIMER_INT_RAW_INT1_RAW_Pos = 0x1 + // Bit mask of INT1_RAW field. + SYSTIMER_INT_RAW_INT1_RAW_Msk = 0x2 + // Bit INT1_RAW. + SYSTIMER_INT_RAW_INT1_RAW = 0x2 + // Position of INT2_RAW field. + SYSTIMER_INT_RAW_INT2_RAW_Pos = 0x2 + // Bit mask of INT2_RAW field. + SYSTIMER_INT_RAW_INT2_RAW_Msk = 0x4 + // Bit INT2_RAW. + SYSTIMER_INT_RAW_INT2_RAW = 0x4 + + // INT_CLR: System timer interrupt clear + // Position of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Pos = 0x0 + // Bit mask of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Msk = 0x1 + // Bit TARGET0_INT_CLR. + SYSTIMER_INT_CLR_TARGET0_INT_CLR = 0x1 + // Position of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Pos = 0x1 + // Bit mask of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Msk = 0x2 + // Bit TARGET1_INT_CLR. + SYSTIMER_INT_CLR_TARGET1_INT_CLR = 0x2 + // Position of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Pos = 0x2 + // Bit mask of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Msk = 0x4 + // Bit TARGET2_INT_CLR. + SYSTIMER_INT_CLR_TARGET2_INT_CLR = 0x4 + + // DATE: Version control register + // Position of DATE field. + SYSTIMER_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SYSTIMER_DATE_DATE_Msk = 0xffffffff +) + +// Constants for TIMG0: Timer Group 0 +const ( + // T0CONFIG: Timer %s configuration register + // Position of USE_XTAL field. + TIMG_TCONFIG_USE_XTAL_Pos = 0x9 + // Bit mask of USE_XTAL field. + TIMG_TCONFIG_USE_XTAL_Msk = 0x200 + // Bit USE_XTAL. + TIMG_TCONFIG_USE_XTAL = 0x200 + // Position of ALARM_EN field. + TIMG_TCONFIG_ALARM_EN_Pos = 0xa + // Bit mask of ALARM_EN field. + TIMG_TCONFIG_ALARM_EN_Msk = 0x400 + // Bit ALARM_EN. + TIMG_TCONFIG_ALARM_EN = 0x400 + // Position of LEVEL_INT_EN field. + TIMG_TCONFIG_LEVEL_INT_EN_Pos = 0xb + // Bit mask of LEVEL_INT_EN field. + TIMG_TCONFIG_LEVEL_INT_EN_Msk = 0x800 + // Bit LEVEL_INT_EN. + TIMG_TCONFIG_LEVEL_INT_EN = 0x800 + // Position of EDGE_INT_EN field. + TIMG_TCONFIG_EDGE_INT_EN_Pos = 0xc + // Bit mask of EDGE_INT_EN field. + TIMG_TCONFIG_EDGE_INT_EN_Msk = 0x1000 + // Bit EDGE_INT_EN. + TIMG_TCONFIG_EDGE_INT_EN = 0x1000 + // Position of DIVIDER field. + TIMG_TCONFIG_DIVIDER_Pos = 0xd + // Bit mask of DIVIDER field. + TIMG_TCONFIG_DIVIDER_Msk = 0x1fffe000 + // Position of AUTORELOAD field. + TIMG_TCONFIG_AUTORELOAD_Pos = 0x1d + // Bit mask of AUTORELOAD field. + TIMG_TCONFIG_AUTORELOAD_Msk = 0x20000000 + // Bit AUTORELOAD. + TIMG_TCONFIG_AUTORELOAD = 0x20000000 + // Position of INCREASE field. + TIMG_TCONFIG_INCREASE_Pos = 0x1e + // Bit mask of INCREASE field. + TIMG_TCONFIG_INCREASE_Msk = 0x40000000 + // Bit INCREASE. + TIMG_TCONFIG_INCREASE = 0x40000000 + // Position of EN field. + TIMG_TCONFIG_EN_Pos = 0x1f + // Bit mask of EN field. + TIMG_TCONFIG_EN_Msk = 0x80000000 + // Bit EN. + TIMG_TCONFIG_EN = 0x80000000 + + // T0LO: Timer %s current value, low 32 bits + // Position of LO field. + TIMG_TLO_LO_Pos = 0x0 + // Bit mask of LO field. + TIMG_TLO_LO_Msk = 0xffffffff + + // T0HI: Timer %s current value, high 32 bits + // Position of HI field. + TIMG_THI_HI_Pos = 0x0 + // Bit mask of HI field. + TIMG_THI_HI_Msk = 0xffffffff + + // T0UPDATE: Write to copy current timer value to TIMG_T%sLO_REG or TIMGn_T%sHI_REG + // Position of UPDATE field. + TIMG_TUPDATE_UPDATE_Pos = 0x1f + // Bit mask of UPDATE field. + TIMG_TUPDATE_UPDATE_Msk = 0x80000000 + // Bit UPDATE. + TIMG_TUPDATE_UPDATE = 0x80000000 + + // T0ALARMLO: Timer %s alarm value, low 32 bits + // Position of ALARM_LO field. + TIMG_TALARMLO_ALARM_LO_Pos = 0x0 + // Bit mask of ALARM_LO field. + TIMG_TALARMLO_ALARM_LO_Msk = 0xffffffff + + // T0ALARMHI: Timer %s alarm value, high bits + // Position of ALARM_HI field. + TIMG_TALARMHI_ALARM_HI_Pos = 0x0 + // Bit mask of ALARM_HI field. + TIMG_TALARMHI_ALARM_HI_Msk = 0xffffffff + + // T0LOADLO: Timer %s reload value, low 32 bits + // Position of LOAD_LO field. + TIMG_TLOADLO_LOAD_LO_Pos = 0x0 + // Bit mask of LOAD_LO field. + TIMG_TLOADLO_LOAD_LO_Msk = 0xffffffff + + // T0LOADHI: Timer %s reload value, high 32 bits + // Position of LOAD_HI field. + TIMG_TLOADHI_LOAD_HI_Pos = 0x0 + // Bit mask of LOAD_HI field. + TIMG_TLOADHI_LOAD_HI_Msk = 0xffffffff + + // T0LOAD: Write to reload timer from TIMG_T%sLOADLO_REG or TIMG_T%sLOADHI_REG + // Position of LOAD field. + TIMG_TLOAD_LOAD_Pos = 0x0 + // Bit mask of LOAD field. + TIMG_TLOAD_LOAD_Msk = 0xffffffff + + // WDTCONFIG0: Watchdog timer configuration register + // Position of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xc + // Bit mask of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x1000 + // Bit WDT_APPCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x1000 + // Position of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xd + // Bit mask of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x2000 + // Bit WDT_PROCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x2000 + // Position of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xe + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x4000 + // Bit WDT_FLASHBOOT_MOD_EN. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x4000 + // Position of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xf + // Bit mask of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0x38000 + // Position of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x12 + // Bit mask of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x1c0000 + // Position of WDT_LEVEL_INT_EN field. + TIMG_WDTCONFIG0_WDT_LEVEL_INT_EN_Pos = 0x15 + // Bit mask of WDT_LEVEL_INT_EN field. + TIMG_WDTCONFIG0_WDT_LEVEL_INT_EN_Msk = 0x200000 + // Bit WDT_LEVEL_INT_EN. + TIMG_WDTCONFIG0_WDT_LEVEL_INT_EN = 0x200000 + // Position of WDT_EDGE_INT_EN field. + TIMG_WDTCONFIG0_WDT_EDGE_INT_EN_Pos = 0x16 + // Bit mask of WDT_EDGE_INT_EN field. + TIMG_WDTCONFIG0_WDT_EDGE_INT_EN_Msk = 0x400000 + // Bit WDT_EDGE_INT_EN. + TIMG_WDTCONFIG0_WDT_EDGE_INT_EN = 0x400000 + // Position of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Pos = 0x17 + // Bit mask of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Msk = 0x1800000 + // Position of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Pos = 0x19 + // Bit mask of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Msk = 0x6000000 + // Position of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Pos = 0x1b + // Bit mask of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Msk = 0x18000000 + // Position of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Pos = 0x1d + // Bit mask of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Msk = 0x60000000 + // Position of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + TIMG_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: Watchdog timer prescaler register + // Position of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Pos = 0x10 + // Bit mask of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Msk = 0xffff0000 + + // WDTCONFIG2: Watchdog timer stage 0 timeout value + // Position of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: Watchdog timer stage 1 timeout value + // Position of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: Watchdog timer stage 2 timeout value + // Position of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG5: Watchdog timer stage 3 timeout value + // Position of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: Write to feed the watchdog timer + // Position of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Pos = 0x0 + // Bit mask of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Msk = 0xffffffff + + // WDTWPROTECT: Watchdog write protect register + // Position of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // RTCCALICFG: RTC calibration configuration register + // Position of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Pos = 0xc + // Bit mask of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Msk = 0x1000 + // Bit RTC_CALI_START_CYCLING. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING = 0x1000 + // Position of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Pos = 0xd + // Bit mask of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Msk = 0x6000 + // Position of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Pos = 0xf + // Bit mask of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Msk = 0x8000 + // Bit RTC_CALI_RDY. + TIMG_RTCCALICFG_RTC_CALI_RDY = 0x8000 + // Position of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Pos = 0x10 + // Bit mask of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Msk = 0x7fff0000 + // Position of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Pos = 0x1f + // Bit mask of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Msk = 0x80000000 + // Bit RTC_CALI_START. + TIMG_RTCCALICFG_RTC_CALI_START = 0x80000000 + + // RTCCALICFG1: RTC calibration configuration register 1 + // Position of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Pos = 0x0 + // Bit mask of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Msk = 0x1 + // Bit RTC_CALI_CYCLING_DATA_VLD. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD = 0x1 + // Position of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Pos = 0x7 + // Bit mask of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Msk = 0xffffff80 + + // LACTCONFIG: LACT configuration register + // Position of LACT_USE_REFTICK field. + TIMG_LACTCONFIG_LACT_USE_REFTICK_Pos = 0x6 + // Bit mask of LACT_USE_REFTICK field. + TIMG_LACTCONFIG_LACT_USE_REFTICK_Msk = 0x40 + // Bit LACT_USE_REFTICK. + TIMG_LACTCONFIG_LACT_USE_REFTICK = 0x40 + // Position of LACT_RTC_ONLY field. + TIMG_LACTCONFIG_LACT_RTC_ONLY_Pos = 0x7 + // Bit mask of LACT_RTC_ONLY field. + TIMG_LACTCONFIG_LACT_RTC_ONLY_Msk = 0x80 + // Bit LACT_RTC_ONLY. + TIMG_LACTCONFIG_LACT_RTC_ONLY = 0x80 + // Position of LACT_CPST_EN field. + TIMG_LACTCONFIG_LACT_CPST_EN_Pos = 0x8 + // Bit mask of LACT_CPST_EN field. + TIMG_LACTCONFIG_LACT_CPST_EN_Msk = 0x100 + // Bit LACT_CPST_EN. + TIMG_LACTCONFIG_LACT_CPST_EN = 0x100 + // Position of LACT_LAC_EN field. + TIMG_LACTCONFIG_LACT_LAC_EN_Pos = 0x9 + // Bit mask of LACT_LAC_EN field. + TIMG_LACTCONFIG_LACT_LAC_EN_Msk = 0x200 + // Bit LACT_LAC_EN. + TIMG_LACTCONFIG_LACT_LAC_EN = 0x200 + // Position of LACT_ALARM_EN field. + TIMG_LACTCONFIG_LACT_ALARM_EN_Pos = 0xa + // Bit mask of LACT_ALARM_EN field. + TIMG_LACTCONFIG_LACT_ALARM_EN_Msk = 0x400 + // Bit LACT_ALARM_EN. + TIMG_LACTCONFIG_LACT_ALARM_EN = 0x400 + // Position of LACT_LEVEL_INT_EN field. + TIMG_LACTCONFIG_LACT_LEVEL_INT_EN_Pos = 0xb + // Bit mask of LACT_LEVEL_INT_EN field. + TIMG_LACTCONFIG_LACT_LEVEL_INT_EN_Msk = 0x800 + // Bit LACT_LEVEL_INT_EN. + TIMG_LACTCONFIG_LACT_LEVEL_INT_EN = 0x800 + // Position of LACT_EDGE_INT_EN field. + TIMG_LACTCONFIG_LACT_EDGE_INT_EN_Pos = 0xc + // Bit mask of LACT_EDGE_INT_EN field. + TIMG_LACTCONFIG_LACT_EDGE_INT_EN_Msk = 0x1000 + // Bit LACT_EDGE_INT_EN. + TIMG_LACTCONFIG_LACT_EDGE_INT_EN = 0x1000 + // Position of LACT_DIVIDER field. + TIMG_LACTCONFIG_LACT_DIVIDER_Pos = 0xd + // Bit mask of LACT_DIVIDER field. + TIMG_LACTCONFIG_LACT_DIVIDER_Msk = 0x1fffe000 + // Position of LACT_AUTORELOAD field. + TIMG_LACTCONFIG_LACT_AUTORELOAD_Pos = 0x1d + // Bit mask of LACT_AUTORELOAD field. + TIMG_LACTCONFIG_LACT_AUTORELOAD_Msk = 0x20000000 + // Bit LACT_AUTORELOAD. + TIMG_LACTCONFIG_LACT_AUTORELOAD = 0x20000000 + // Position of LACT_INCREASE field. + TIMG_LACTCONFIG_LACT_INCREASE_Pos = 0x1e + // Bit mask of LACT_INCREASE field. + TIMG_LACTCONFIG_LACT_INCREASE_Msk = 0x40000000 + // Bit LACT_INCREASE. + TIMG_LACTCONFIG_LACT_INCREASE = 0x40000000 + // Position of LACT_EN field. + TIMG_LACTCONFIG_LACT_EN_Pos = 0x1f + // Bit mask of LACT_EN field. + TIMG_LACTCONFIG_LACT_EN_Msk = 0x80000000 + // Bit LACT_EN. + TIMG_LACTCONFIG_LACT_EN = 0x80000000 + + // LACTRTC: LACT RTC register + // Position of LACT_RTC_STEP_LEN field. + TIMG_LACTRTC_LACT_RTC_STEP_LEN_Pos = 0x6 + // Bit mask of LACT_RTC_STEP_LEN field. + TIMG_LACTRTC_LACT_RTC_STEP_LEN_Msk = 0xffffffc0 + + // LACTLO: LACT low register + // Position of LACT_LO field. + TIMG_LACTLO_LACT_LO_Pos = 0x0 + // Bit mask of LACT_LO field. + TIMG_LACTLO_LACT_LO_Msk = 0xffffffff + + // LACTHI: LACT high register + // Position of LACT_HI field. + TIMG_LACTHI_LACT_HI_Pos = 0x0 + // Bit mask of LACT_HI field. + TIMG_LACTHI_LACT_HI_Msk = 0xffffffff + + // LACTUPDATE: LACT update register + // Position of LACT_UPDATE field. + TIMG_LACTUPDATE_LACT_UPDATE_Pos = 0x0 + // Bit mask of LACT_UPDATE field. + TIMG_LACTUPDATE_LACT_UPDATE_Msk = 0xffffffff + + // LACTALARMLO: LACT alarm low register + // Position of LACT_ALARM_LO field. + TIMG_LACTALARMLO_LACT_ALARM_LO_Pos = 0x0 + // Bit mask of LACT_ALARM_LO field. + TIMG_LACTALARMLO_LACT_ALARM_LO_Msk = 0xffffffff + + // LACTALARMHI: LACT alarm high register + // Position of LACT_ALARM_HI field. + TIMG_LACTALARMHI_LACT_ALARM_HI_Pos = 0x0 + // Bit mask of LACT_ALARM_HI field. + TIMG_LACTALARMHI_LACT_ALARM_HI_Msk = 0xffffffff + + // LACTLOADLO: LACT load low register + // Position of LACT_LOAD_LO field. + TIMG_LACTLOADLO_LACT_LOAD_LO_Pos = 0x0 + // Bit mask of LACT_LOAD_LO field. + TIMG_LACTLOADLO_LACT_LOAD_LO_Msk = 0xffffffff + + // LACTLOADHI: Timer LACT load high register + // Position of LACT_LOAD_HI field. + TIMG_LACTLOADHI_LACT_LOAD_HI_Pos = 0x0 + // Bit mask of LACT_LOAD_HI field. + TIMG_LACTLOADHI_LACT_LOAD_HI_Msk = 0xffffffff + + // LACTLOAD: Timer LACT load register + // Position of LACT_LOAD field. + TIMG_LACTLOAD_LACT_LOAD_Pos = 0x0 + // Bit mask of LACT_LOAD field. + TIMG_LACTLOAD_LACT_LOAD_Msk = 0xffffffff + + // INT_ENA_TIMERS: Interrupt enable bits + // Position of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Pos = 0x0 + // Bit mask of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Msk = 0x1 + // Bit T0_INT_ENA. + TIMG_INT_ENA_TIMERS_T0_INT_ENA = 0x1 + // Position of T1_INT_ENA field. + TIMG_INT_ENA_TIMERS_T1_INT_ENA_Pos = 0x1 + // Bit mask of T1_INT_ENA field. + TIMG_INT_ENA_TIMERS_T1_INT_ENA_Msk = 0x2 + // Bit T1_INT_ENA. + TIMG_INT_ENA_TIMERS_T1_INT_ENA = 0x2 + // Position of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Pos = 0x2 + // Bit mask of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Msk = 0x4 + // Bit WDT_INT_ENA. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA = 0x4 + // Position of LACT_INT_ENA field. + TIMG_INT_ENA_TIMERS_LACT_INT_ENA_Pos = 0x3 + // Bit mask of LACT_INT_ENA field. + TIMG_INT_ENA_TIMERS_LACT_INT_ENA_Msk = 0x8 + // Bit LACT_INT_ENA. + TIMG_INT_ENA_TIMERS_LACT_INT_ENA = 0x8 + + // INT_RAW_TIMERS: Raw interrupt status + // Position of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Pos = 0x0 + // Bit mask of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Msk = 0x1 + // Bit T0_INT_RAW. + TIMG_INT_RAW_TIMERS_T0_INT_RAW = 0x1 + // Position of T1_INT_RAW field. + TIMG_INT_RAW_TIMERS_T1_INT_RAW_Pos = 0x1 + // Bit mask of T1_INT_RAW field. + TIMG_INT_RAW_TIMERS_T1_INT_RAW_Msk = 0x2 + // Bit T1_INT_RAW. + TIMG_INT_RAW_TIMERS_T1_INT_RAW = 0x2 + // Position of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Pos = 0x2 + // Bit mask of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Msk = 0x4 + // Bit WDT_INT_RAW. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW = 0x4 + // Position of LACT_INT_RAW field. + TIMG_INT_RAW_TIMERS_LACT_INT_RAW_Pos = 0x3 + // Bit mask of LACT_INT_RAW field. + TIMG_INT_RAW_TIMERS_LACT_INT_RAW_Msk = 0x8 + // Bit LACT_INT_RAW. + TIMG_INT_RAW_TIMERS_LACT_INT_RAW = 0x8 + + // INT_ST_TIMERS: Masked interrupt status + // Position of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Pos = 0x0 + // Bit mask of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Msk = 0x1 + // Bit T0_INT_ST. + TIMG_INT_ST_TIMERS_T0_INT_ST = 0x1 + // Position of T1_INT_ST field. + TIMG_INT_ST_TIMERS_T1_INT_ST_Pos = 0x1 + // Bit mask of T1_INT_ST field. + TIMG_INT_ST_TIMERS_T1_INT_ST_Msk = 0x2 + // Bit T1_INT_ST. + TIMG_INT_ST_TIMERS_T1_INT_ST = 0x2 + // Position of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Pos = 0x2 + // Bit mask of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Msk = 0x4 + // Bit WDT_INT_ST. + TIMG_INT_ST_TIMERS_WDT_INT_ST = 0x4 + // Position of LACT_INT_ST field. + TIMG_INT_ST_TIMERS_LACT_INT_ST_Pos = 0x3 + // Bit mask of LACT_INT_ST field. + TIMG_INT_ST_TIMERS_LACT_INT_ST_Msk = 0x8 + // Bit LACT_INT_ST. + TIMG_INT_ST_TIMERS_LACT_INT_ST = 0x8 + + // INT_CLR_TIMERS: Interrupt clear bits + // Position of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Pos = 0x0 + // Bit mask of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Msk = 0x1 + // Bit T0_INT_CLR. + TIMG_INT_CLR_TIMERS_T0_INT_CLR = 0x1 + // Position of T1_INT_CLR field. + TIMG_INT_CLR_TIMERS_T1_INT_CLR_Pos = 0x1 + // Bit mask of T1_INT_CLR field. + TIMG_INT_CLR_TIMERS_T1_INT_CLR_Msk = 0x2 + // Bit T1_INT_CLR. + TIMG_INT_CLR_TIMERS_T1_INT_CLR = 0x2 + // Position of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Pos = 0x2 + // Bit mask of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Msk = 0x4 + // Bit WDT_INT_CLR. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR = 0x4 + // Position of LACT_INT_CLR field. + TIMG_INT_CLR_TIMERS_LACT_INT_CLR_Pos = 0x3 + // Bit mask of LACT_INT_CLR field. + TIMG_INT_CLR_TIMERS_LACT_INT_CLR_Msk = 0x8 + // Bit LACT_INT_CLR. + TIMG_INT_CLR_TIMERS_LACT_INT_CLR = 0x8 + + // RTCCALICFG2: Timer group calibration register + // Position of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Pos = 0x0 + // Bit mask of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Msk = 0x1 + // Bit RTC_CALI_TIMEOUT. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT = 0x1 + // Position of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Pos = 0x3 + // Bit mask of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Msk = 0x78 + // Position of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Pos = 0x7 + // Bit mask of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Msk = 0xffffff80 + + // TIMERS_DATE: Version control register + // Position of TIMERS_DATE field. + TIMG_TIMERS_DATE_TIMERS_DATE_Pos = 0x0 + // Bit mask of TIMERS_DATE field. + TIMG_TIMERS_DATE_TIMERS_DATE_Msk = 0xfffffff + + // REGCLK: Timer group clock gate register + // Position of CLK_EN field. + TIMG_REGCLK_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + TIMG_REGCLK_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + TIMG_REGCLK_CLK_EN = 0x80000000 +) + +// Constants for TWAI0: Two-Wire Automotive Interface +const ( + // MODE: Mode Register + // Position of RESET_MODE field. + TWAI_MODE_RESET_MODE_Pos = 0x0 + // Bit mask of RESET_MODE field. + TWAI_MODE_RESET_MODE_Msk = 0x1 + // Bit RESET_MODE. + TWAI_MODE_RESET_MODE = 0x1 + // Position of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Pos = 0x1 + // Bit mask of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Msk = 0x2 + // Bit LISTEN_ONLY_MODE. + TWAI_MODE_LISTEN_ONLY_MODE = 0x2 + // Position of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Pos = 0x2 + // Bit mask of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Msk = 0x4 + // Bit SELF_TEST_MODE. + TWAI_MODE_SELF_TEST_MODE = 0x4 + // Position of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Pos = 0x3 + // Bit mask of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Msk = 0x8 + // Bit RX_FILTER_MODE. + TWAI_MODE_RX_FILTER_MODE = 0x8 + + // CMD: Command Register + // Position of TX_REQ field. + TWAI_CMD_TX_REQ_Pos = 0x0 + // Bit mask of TX_REQ field. + TWAI_CMD_TX_REQ_Msk = 0x1 + // Bit TX_REQ. + TWAI_CMD_TX_REQ = 0x1 + // Position of ABORT_TX field. + TWAI_CMD_ABORT_TX_Pos = 0x1 + // Bit mask of ABORT_TX field. + TWAI_CMD_ABORT_TX_Msk = 0x2 + // Bit ABORT_TX. + TWAI_CMD_ABORT_TX = 0x2 + // Position of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Pos = 0x2 + // Bit mask of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Msk = 0x4 + // Bit RELEASE_BUF. + TWAI_CMD_RELEASE_BUF = 0x4 + // Position of CLR_OVERRUN field. + TWAI_CMD_CLR_OVERRUN_Pos = 0x3 + // Bit mask of CLR_OVERRUN field. + TWAI_CMD_CLR_OVERRUN_Msk = 0x8 + // Bit CLR_OVERRUN. + TWAI_CMD_CLR_OVERRUN = 0x8 + // Position of SELF_RX_REQ field. + TWAI_CMD_SELF_RX_REQ_Pos = 0x4 + // Bit mask of SELF_RX_REQ field. + TWAI_CMD_SELF_RX_REQ_Msk = 0x10 + // Bit SELF_RX_REQ. + TWAI_CMD_SELF_RX_REQ = 0x10 + + // STATUS: Status register + // Position of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Pos = 0x0 + // Bit mask of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Msk = 0x1 + // Bit RX_BUF_ST. + TWAI_STATUS_RX_BUF_ST = 0x1 + // Position of OVERRUN_ST field. + TWAI_STATUS_OVERRUN_ST_Pos = 0x1 + // Bit mask of OVERRUN_ST field. + TWAI_STATUS_OVERRUN_ST_Msk = 0x2 + // Bit OVERRUN_ST. + TWAI_STATUS_OVERRUN_ST = 0x2 + // Position of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Pos = 0x2 + // Bit mask of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Msk = 0x4 + // Bit TX_BUF_ST. + TWAI_STATUS_TX_BUF_ST = 0x4 + // Position of TX_COMPLETE field. + TWAI_STATUS_TX_COMPLETE_Pos = 0x3 + // Bit mask of TX_COMPLETE field. + TWAI_STATUS_TX_COMPLETE_Msk = 0x8 + // Bit TX_COMPLETE. + TWAI_STATUS_TX_COMPLETE = 0x8 + // Position of RX_ST field. + TWAI_STATUS_RX_ST_Pos = 0x4 + // Bit mask of RX_ST field. + TWAI_STATUS_RX_ST_Msk = 0x10 + // Bit RX_ST. + TWAI_STATUS_RX_ST = 0x10 + // Position of TX_ST field. + TWAI_STATUS_TX_ST_Pos = 0x5 + // Bit mask of TX_ST field. + TWAI_STATUS_TX_ST_Msk = 0x20 + // Bit TX_ST. + TWAI_STATUS_TX_ST = 0x20 + // Position of ERR_ST field. + TWAI_STATUS_ERR_ST_Pos = 0x6 + // Bit mask of ERR_ST field. + TWAI_STATUS_ERR_ST_Msk = 0x40 + // Bit ERR_ST. + TWAI_STATUS_ERR_ST = 0x40 + // Position of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Pos = 0x7 + // Bit mask of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Msk = 0x80 + // Bit BUS_OFF_ST. + TWAI_STATUS_BUS_OFF_ST = 0x80 + // Position of MISS_ST field. + TWAI_STATUS_MISS_ST_Pos = 0x8 + // Bit mask of MISS_ST field. + TWAI_STATUS_MISS_ST_Msk = 0x100 + // Bit MISS_ST. + TWAI_STATUS_MISS_ST = 0x100 + + // INT_RAW: Interrupt Register + // Position of RX_INT_ST field. + TWAI_INT_RAW_RX_INT_ST_Pos = 0x0 + // Bit mask of RX_INT_ST field. + TWAI_INT_RAW_RX_INT_ST_Msk = 0x1 + // Bit RX_INT_ST. + TWAI_INT_RAW_RX_INT_ST = 0x1 + // Position of TX_INT_ST field. + TWAI_INT_RAW_TX_INT_ST_Pos = 0x1 + // Bit mask of TX_INT_ST field. + TWAI_INT_RAW_TX_INT_ST_Msk = 0x2 + // Bit TX_INT_ST. + TWAI_INT_RAW_TX_INT_ST = 0x2 + // Position of ERR_WARN_INT_ST field. + TWAI_INT_RAW_ERR_WARN_INT_ST_Pos = 0x2 + // Bit mask of ERR_WARN_INT_ST field. + TWAI_INT_RAW_ERR_WARN_INT_ST_Msk = 0x4 + // Bit ERR_WARN_INT_ST. + TWAI_INT_RAW_ERR_WARN_INT_ST = 0x4 + // Position of OVERRUN_INT_ST field. + TWAI_INT_RAW_OVERRUN_INT_ST_Pos = 0x3 + // Bit mask of OVERRUN_INT_ST field. + TWAI_INT_RAW_OVERRUN_INT_ST_Msk = 0x8 + // Bit OVERRUN_INT_ST. + TWAI_INT_RAW_OVERRUN_INT_ST = 0x8 + // Position of ERR_PASSIVE_INT_ST field. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ST field. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ST. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST = 0x20 + // Position of ARB_LOST_INT_ST field. + TWAI_INT_RAW_ARB_LOST_INT_ST_Pos = 0x6 + // Bit mask of ARB_LOST_INT_ST field. + TWAI_INT_RAW_ARB_LOST_INT_ST_Msk = 0x40 + // Bit ARB_LOST_INT_ST. + TWAI_INT_RAW_ARB_LOST_INT_ST = 0x40 + // Position of BUS_ERR_INT_ST field. + TWAI_INT_RAW_BUS_ERR_INT_ST_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ST field. + TWAI_INT_RAW_BUS_ERR_INT_ST_Msk = 0x80 + // Bit BUS_ERR_INT_ST. + TWAI_INT_RAW_BUS_ERR_INT_ST = 0x80 + + // INT_ENA: Interrupt Enable Register + // Position of RX_INT_ENA field. + TWAI_INT_ENA_RX_INT_ENA_Pos = 0x0 + // Bit mask of RX_INT_ENA field. + TWAI_INT_ENA_RX_INT_ENA_Msk = 0x1 + // Bit RX_INT_ENA. + TWAI_INT_ENA_RX_INT_ENA = 0x1 + // Position of TX_INT_ENA field. + TWAI_INT_ENA_TX_INT_ENA_Pos = 0x1 + // Bit mask of TX_INT_ENA field. + TWAI_INT_ENA_TX_INT_ENA_Msk = 0x2 + // Bit TX_INT_ENA. + TWAI_INT_ENA_TX_INT_ENA = 0x2 + // Position of ERR_WARN_INT_ENA field. + TWAI_INT_ENA_ERR_WARN_INT_ENA_Pos = 0x2 + // Bit mask of ERR_WARN_INT_ENA field. + TWAI_INT_ENA_ERR_WARN_INT_ENA_Msk = 0x4 + // Bit ERR_WARN_INT_ENA. + TWAI_INT_ENA_ERR_WARN_INT_ENA = 0x4 + // Position of OVERRUN_INT_ENA field. + TWAI_INT_ENA_OVERRUN_INT_ENA_Pos = 0x3 + // Bit mask of OVERRUN_INT_ENA field. + TWAI_INT_ENA_OVERRUN_INT_ENA_Msk = 0x8 + // Bit OVERRUN_INT_ENA. + TWAI_INT_ENA_OVERRUN_INT_ENA = 0x8 + // Position of ERR_PASSIVE_INT_ENA field. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ENA field. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ENA. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA = 0x20 + // Position of ARB_LOST_INT_ENA field. + TWAI_INT_ENA_ARB_LOST_INT_ENA_Pos = 0x6 + // Bit mask of ARB_LOST_INT_ENA field. + TWAI_INT_ENA_ARB_LOST_INT_ENA_Msk = 0x40 + // Bit ARB_LOST_INT_ENA. + TWAI_INT_ENA_ARB_LOST_INT_ENA = 0x40 + // Position of BUS_ERR_INT_ENA field. + TWAI_INT_ENA_BUS_ERR_INT_ENA_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ENA field. + TWAI_INT_ENA_BUS_ERR_INT_ENA_Msk = 0x80 + // Bit BUS_ERR_INT_ENA. + TWAI_INT_ENA_BUS_ERR_INT_ENA = 0x80 + + // BUS_TIMING_0: Bus Timing Register 0 + // Position of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Pos = 0x0 + // Bit mask of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Msk = 0x3fff + // Position of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Pos = 0xe + // Bit mask of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Msk = 0xc000 + + // BUS_TIMING_1: Bus Timing Register 1 + // Position of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Pos = 0x0 + // Bit mask of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Msk = 0xf + // Position of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Pos = 0x4 + // Bit mask of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Msk = 0x70 + // Position of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Pos = 0x7 + // Bit mask of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Msk = 0x80 + // Bit TIME_SAMP. + TWAI_BUS_TIMING_1_TIME_SAMP = 0x80 + + // ARB_LOST_CAP: Arbitration Lost Capture Register + // Position of ARB_LOST_CAP field. + TWAI_ARB_LOST_CAP_ARB_LOST_CAP_Pos = 0x0 + // Bit mask of ARB_LOST_CAP field. + TWAI_ARB_LOST_CAP_ARB_LOST_CAP_Msk = 0x1f + + // ERR_CODE_CAP: Error Code Capture Register + // Position of ECC_SEGMENT field. + TWAI_ERR_CODE_CAP_ECC_SEGMENT_Pos = 0x0 + // Bit mask of ECC_SEGMENT field. + TWAI_ERR_CODE_CAP_ECC_SEGMENT_Msk = 0x1f + // Position of ECC_DIRECTION field. + TWAI_ERR_CODE_CAP_ECC_DIRECTION_Pos = 0x5 + // Bit mask of ECC_DIRECTION field. + TWAI_ERR_CODE_CAP_ECC_DIRECTION_Msk = 0x20 + // Bit ECC_DIRECTION. + TWAI_ERR_CODE_CAP_ECC_DIRECTION = 0x20 + // Position of ECC_TYPE field. + TWAI_ERR_CODE_CAP_ECC_TYPE_Pos = 0x6 + // Bit mask of ECC_TYPE field. + TWAI_ERR_CODE_CAP_ECC_TYPE_Msk = 0xc0 + + // ERR_WARNING_LIMIT: Error Warning Limit Register + // Position of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Pos = 0x0 + // Bit mask of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Msk = 0xff + + // RX_ERR_CNT: Receive Error Counter Register + // Position of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Pos = 0x0 + // Bit mask of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Msk = 0xff + + // TX_ERR_CNT: Transmit Error Counter Register + // Position of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Pos = 0x0 + // Bit mask of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Msk = 0xff + + // DATA_0: Data register 0 + // Position of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Pos = 0x0 + // Bit mask of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Msk = 0xff + + // DATA_1: Data register 1 + // Position of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Pos = 0x0 + // Bit mask of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Msk = 0xff + + // DATA_2: Data register 2 + // Position of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Pos = 0x0 + // Bit mask of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Msk = 0xff + + // DATA_3: Data register 3 + // Position of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Pos = 0x0 + // Bit mask of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Msk = 0xff + + // DATA_4: Data register 4 + // Position of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Pos = 0x0 + // Bit mask of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Msk = 0xff + + // DATA_5: Data register 5 + // Position of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Pos = 0x0 + // Bit mask of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Msk = 0xff + + // DATA_6: Data register 6 + // Position of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Pos = 0x0 + // Bit mask of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Msk = 0xff + + // DATA_7: Data register 7 + // Position of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Pos = 0x0 + // Bit mask of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Msk = 0xff + + // DATA_8: Data register 8 + // Position of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Pos = 0x0 + // Bit mask of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Msk = 0xff + + // DATA_9: Data register 9 + // Position of TX_BYTE_9 field. + TWAI_DATA_9_TX_BYTE_9_Pos = 0x0 + // Bit mask of TX_BYTE_9 field. + TWAI_DATA_9_TX_BYTE_9_Msk = 0xff + + // DATA_10: Data register 10 + // Position of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Pos = 0x0 + // Bit mask of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Msk = 0xff + + // DATA_11: Data register 11 + // Position of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Pos = 0x0 + // Bit mask of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Msk = 0xff + + // DATA_12: Data register 12 + // Position of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Pos = 0x0 + // Bit mask of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Msk = 0xff + + // RX_MESSAGE_CNT: Receive Message Counter Register + // Position of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Pos = 0x0 + // Bit mask of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Msk = 0x7f + + // CLOCK_DIVIDER: Clock Divider register + // Position of CD field. + TWAI_CLOCK_DIVIDER_CD_Pos = 0x0 + // Bit mask of CD field. + TWAI_CLOCK_DIVIDER_CD_Msk = 0xff + // Position of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Pos = 0x8 + // Bit mask of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Msk = 0x100 + // Bit CLOCK_OFF. + TWAI_CLOCK_DIVIDER_CLOCK_OFF = 0x100 +) + +// Constants for UART0: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +const ( + // FIFO: FIFO data register + // Position of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9 + // Bit mask of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200 + // Bit SW_XON_INT_RAW. + UART_INT_RAW_SW_XON_INT_RAW = 0x200 + // Position of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa + // Bit mask of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400 + // Bit SW_XOFF_INT_RAW. + UART_INT_RAW_SW_XOFF_INT_RAW = 0x400 + // Position of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb + // Bit mask of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800 + // Bit GLITCH_DET_INT_RAW. + UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800 + // Position of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000 + // Position of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit TX_DONE_INT_RAW. + UART_INT_RAW_TX_DONE_INT_RAW = 0x4000 + // Position of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_RAW. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW = 0x8000 + // Position of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_RAW. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW = 0x10000 + // Position of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Msk = 0x20000 + // Bit RS485_CLASH_INT_RAW. + UART_INT_RAW_RS485_CLASH_INT_RAW = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_RAW. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000 + // Position of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13 + // Bit mask of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000 + // Bit WAKEUP_INT_RAW. + UART_INT_RAW_WAKEUP_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Pos = 0x9 + // Bit mask of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Msk = 0x200 + // Bit SW_XON_INT_ST. + UART_INT_ST_SW_XON_INT_ST = 0x200 + // Position of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa + // Bit mask of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400 + // Bit SW_XOFF_INT_ST. + UART_INT_ST_SW_XOFF_INT_ST = 0x400 + // Position of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800 + // Bit GLITCH_DET_INT_ST. + UART_INT_ST_GLITCH_DET_INT_ST = 0x800 + // Position of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ST. + UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ST. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000 + // Position of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000 + // Bit TX_DONE_INT_ST. + UART_INT_ST_TX_DONE_INT_ST = 0x4000 + // Position of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ST. + UART_INT_ST_RS485_PARITY_ERR_INT_ST = 0x8000 + // Position of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ST. + UART_INT_ST_RS485_FRM_ERR_INT_ST = 0x10000 + // Position of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Msk = 0x20000 + // Bit RS485_CLASH_INT_ST. + UART_INT_ST_RS485_CLASH_INT_ST = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ST. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000 + // Position of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13 + // Bit mask of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000 + // Bit WAKEUP_INT_ST. + UART_INT_ST_WAKEUP_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9 + // Bit mask of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200 + // Bit SW_XON_INT_ENA. + UART_INT_ENA_SW_XON_INT_ENA = 0x200 + // Position of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa + // Bit mask of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400 + // Bit SW_XOFF_INT_ENA. + UART_INT_ENA_SW_XOFF_INT_ENA = 0x400 + // Position of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800 + // Bit GLITCH_DET_INT_ENA. + UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800 + // Position of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000 + // Position of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit TX_DONE_INT_ENA. + UART_INT_ENA_TX_DONE_INT_ENA = 0x4000 + // Position of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ENA. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA = 0x8000 + // Position of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ENA. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA = 0x10000 + // Position of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Msk = 0x20000 + // Bit RS485_CLASH_INT_ENA. + UART_INT_ENA_RS485_CLASH_INT_ENA = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ENA. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000 + // Position of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13 + // Bit mask of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000 + // Bit WAKEUP_INT_ENA. + UART_INT_ENA_WAKEUP_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9 + // Bit mask of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200 + // Bit SW_XON_INT_CLR. + UART_INT_CLR_SW_XON_INT_CLR = 0x200 + // Position of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa + // Bit mask of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400 + // Bit SW_XOFF_INT_CLR. + UART_INT_CLR_SW_XOFF_INT_CLR = 0x400 + // Position of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb + // Bit mask of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800 + // Bit GLITCH_DET_INT_CLR. + UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800 + // Position of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000 + // Position of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit TX_DONE_INT_CLR. + UART_INT_CLR_TX_DONE_INT_CLR = 0x4000 + // Position of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_CLR. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR = 0x8000 + // Position of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_CLR. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR = 0x10000 + // Position of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Msk = 0x20000 + // Bit RS485_CLASH_INT_CLR. + UART_INT_CLR_RS485_CLASH_INT_CLR = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_CLR. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000 + // Position of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13 + // Bit mask of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000 + // Bit WAKEUP_INT_CLR. + UART_INT_CLR_WAKEUP_INT_CLR = 0x80000 + + // CLKDIV: Clock divider configuration + // Position of CLKDIV field. + UART_CLKDIV_CLKDIV_Pos = 0x0 + // Bit mask of CLKDIV field. + UART_CLKDIV_CLKDIV_Msk = 0xfffff + // Position of FRAG field. + UART_CLKDIV_FRAG_Pos = 0x14 + // Bit mask of FRAG field. + UART_CLKDIV_FRAG_Msk = 0xf00000 + + // AUTOBAUD: Autobaud configuration register + // Position of EN field. + UART_AUTOBAUD_EN_Pos = 0x0 + // Bit mask of EN field. + UART_AUTOBAUD_EN_Msk = 0x1 + // Bit EN. + UART_AUTOBAUD_EN = 0x1 + // Position of GLITCH_FILT field. + UART_AUTOBAUD_GLITCH_FILT_Pos = 0x8 + // Bit mask of GLITCH_FILT field. + UART_AUTOBAUD_GLITCH_FILT_Msk = 0xff00 + + // STATUS: UART status register + // Position of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Pos = 0x0 + // Bit mask of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Msk = 0x3ff + // Position of DSRN field. + UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + UART_STATUS_DSRN = 0x2000 + // Position of CTSN field. + UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + UART_STATUS_CTSN = 0x4000 + // Position of RXD field. + UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + UART_STATUS_RXD = 0x8000 + // Position of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Pos = 0x10 + // Bit mask of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Msk = 0x3ff0000 + // Position of DTRN field. + UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + UART_STATUS_DTRN = 0x20000000 + // Position of RTSN field. + UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + UART_STATUS_RTSN = 0x40000000 + // Position of TXD field. + UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + UART_STATUS_TXD = 0x80000000 + + // CONF0: Configuration register 0 + // Position of PARITY field. + UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + UART_CONF0_PARITY = 0x1 + // Position of PARITY_EN field. + UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + UART_CONF0_PARITY_EN = 0x2 + // Position of BIT_NUM field. + UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + UART_CONF0_BIT_NUM_Msk = 0xc + // Position of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of SW_RTS field. + UART_CONF0_SW_RTS_Pos = 0x6 + // Bit mask of SW_RTS field. + UART_CONF0_SW_RTS_Msk = 0x40 + // Bit SW_RTS. + UART_CONF0_SW_RTS = 0x40 + // Position of SW_DTR field. + UART_CONF0_SW_DTR_Pos = 0x7 + // Bit mask of SW_DTR field. + UART_CONF0_SW_DTR_Msk = 0x80 + // Bit SW_DTR. + UART_CONF0_SW_DTR = 0x80 + // Position of TXD_BRK field. + UART_CONF0_TXD_BRK_Pos = 0x8 + // Bit mask of TXD_BRK field. + UART_CONF0_TXD_BRK_Msk = 0x100 + // Bit TXD_BRK. + UART_CONF0_TXD_BRK = 0x100 + // Position of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Pos = 0x9 + // Bit mask of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Msk = 0x200 + // Bit IRDA_DPLX. + UART_CONF0_IRDA_DPLX = 0x200 + // Position of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Pos = 0xa + // Bit mask of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Msk = 0x400 + // Bit IRDA_TX_EN. + UART_CONF0_IRDA_TX_EN = 0x400 + // Position of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Pos = 0xb + // Bit mask of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Msk = 0x800 + // Bit IRDA_WCTL. + UART_CONF0_IRDA_WCTL = 0x800 + // Position of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Pos = 0xc + // Bit mask of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Msk = 0x1000 + // Bit IRDA_TX_INV. + UART_CONF0_IRDA_TX_INV = 0x1000 + // Position of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Pos = 0xd + // Bit mask of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Msk = 0x2000 + // Bit IRDA_RX_INV. + UART_CONF0_IRDA_RX_INV = 0x2000 + // Position of LOOPBACK field. + UART_CONF0_LOOPBACK_Pos = 0xe + // Bit mask of LOOPBACK field. + UART_CONF0_LOOPBACK_Msk = 0x4000 + // Bit LOOPBACK. + UART_CONF0_LOOPBACK = 0x4000 + // Position of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Pos = 0xf + // Bit mask of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Msk = 0x8000 + // Bit TX_FLOW_EN. + UART_CONF0_TX_FLOW_EN = 0x8000 + // Position of IRDA_EN field. + UART_CONF0_IRDA_EN_Pos = 0x10 + // Bit mask of IRDA_EN field. + UART_CONF0_IRDA_EN_Msk = 0x10000 + // Bit IRDA_EN. + UART_CONF0_IRDA_EN = 0x10000 + // Position of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Pos = 0x11 + // Bit mask of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Msk = 0x20000 + // Bit RXFIFO_RST. + UART_CONF0_RXFIFO_RST = 0x20000 + // Position of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Pos = 0x12 + // Bit mask of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Msk = 0x40000 + // Bit TXFIFO_RST. + UART_CONF0_TXFIFO_RST = 0x40000 + // Position of RXD_INV field. + UART_CONF0_RXD_INV_Pos = 0x13 + // Bit mask of RXD_INV field. + UART_CONF0_RXD_INV_Msk = 0x80000 + // Bit RXD_INV. + UART_CONF0_RXD_INV = 0x80000 + // Position of CTS_INV field. + UART_CONF0_CTS_INV_Pos = 0x14 + // Bit mask of CTS_INV field. + UART_CONF0_CTS_INV_Msk = 0x100000 + // Bit CTS_INV. + UART_CONF0_CTS_INV = 0x100000 + // Position of DSR_INV field. + UART_CONF0_DSR_INV_Pos = 0x15 + // Bit mask of DSR_INV field. + UART_CONF0_DSR_INV_Msk = 0x200000 + // Bit DSR_INV. + UART_CONF0_DSR_INV = 0x200000 + // Position of TXD_INV field. + UART_CONF0_TXD_INV_Pos = 0x16 + // Bit mask of TXD_INV field. + UART_CONF0_TXD_INV_Msk = 0x400000 + // Bit TXD_INV. + UART_CONF0_TXD_INV = 0x400000 + // Position of RTS_INV field. + UART_CONF0_RTS_INV_Pos = 0x17 + // Bit mask of RTS_INV field. + UART_CONF0_RTS_INV_Msk = 0x800000 + // Bit RTS_INV. + UART_CONF0_RTS_INV = 0x800000 + // Position of DTR_INV field. + UART_CONF0_DTR_INV_Pos = 0x18 + // Bit mask of DTR_INV field. + UART_CONF0_DTR_INV_Msk = 0x1000000 + // Bit DTR_INV. + UART_CONF0_DTR_INV = 0x1000000 + // Position of CLK_EN field. + UART_CONF0_CLK_EN_Pos = 0x19 + // Bit mask of CLK_EN field. + UART_CONF0_CLK_EN_Msk = 0x2000000 + // Bit CLK_EN. + UART_CONF0_CLK_EN = 0x2000000 + // Position of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Pos = 0x1a + // Bit mask of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Msk = 0x4000000 + // Bit ERR_WR_MASK. + UART_CONF0_ERR_WR_MASK = 0x4000000 + // Position of TICK_REF_ALWAYS_ON field. + UART_CONF0_TICK_REF_ALWAYS_ON_Pos = 0x1b + // Bit mask of TICK_REF_ALWAYS_ON field. + UART_CONF0_TICK_REF_ALWAYS_ON_Msk = 0x8000000 + // Bit TICK_REF_ALWAYS_ON. + UART_CONF0_TICK_REF_ALWAYS_ON = 0x8000000 + // Position of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Pos = 0x1c + // Bit mask of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Msk = 0x10000000 + // Bit MEM_CLK_EN. + UART_CONF0_MEM_CLK_EN = 0x10000000 + + // CONF1: Configuration register 1 + // Position of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0x1ff + // Position of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0x9 + // Bit mask of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0x3fe00 + // Position of RX_TOUT_FLOW_DIS field. + UART_CONF1_RX_TOUT_FLOW_DIS_Pos = 0x1d + // Bit mask of RX_TOUT_FLOW_DIS field. + UART_CONF1_RX_TOUT_FLOW_DIS_Msk = 0x20000000 + // Bit RX_TOUT_FLOW_DIS. + UART_CONF1_RX_TOUT_FLOW_DIS = 0x20000000 + // Position of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Pos = 0x1e + // Bit mask of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Msk = 0x40000000 + // Bit RX_FLOW_EN. + UART_CONF1_RX_FLOW_EN = 0x40000000 + // Position of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Pos = 0x1f + // Bit mask of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Msk = 0x80000000 + // Bit RX_TOUT_EN. + UART_CONF1_RX_TOUT_EN = 0x80000000 + + // LOWPULSE: Autobaud minimum low pulse duration register + // Position of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Msk = 0xfffff + + // HIGHPULSE: Autobaud minimum high pulse duration register + // Position of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Msk = 0xfffff + + // RXD_CNT: Autobaud edge change count register + // Position of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0 + // Bit mask of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff + + // FLOW_CONF: Software flow control configuration + // Position of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Pos = 0x0 + // Bit mask of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Msk = 0x1 + // Bit SW_FLOW_CON_EN. + UART_FLOW_CONF_SW_FLOW_CON_EN = 0x1 + // Position of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Pos = 0x1 + // Bit mask of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Msk = 0x2 + // Bit XONOFF_DEL. + UART_FLOW_CONF_XONOFF_DEL = 0x2 + // Position of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Pos = 0x2 + // Bit mask of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Msk = 0x4 + // Bit FORCE_XON. + UART_FLOW_CONF_FORCE_XON = 0x4 + // Position of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Pos = 0x3 + // Bit mask of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Msk = 0x8 + // Bit FORCE_XOFF. + UART_FLOW_CONF_FORCE_XOFF = 0x8 + // Position of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Pos = 0x4 + // Bit mask of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Msk = 0x10 + // Bit SEND_XON. + UART_FLOW_CONF_SEND_XON = 0x10 + // Position of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Pos = 0x5 + // Bit mask of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Msk = 0x20 + // Bit SEND_XOFF. + UART_FLOW_CONF_SEND_XOFF = 0x20 + + // SLEEP_CONF: Sleep mode configuration + // Position of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Pos = 0x0 + // Bit mask of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Msk = 0x3ff + + // SWFC_CONF0: Software flow control character configuration + // Position of XOFF_THRESHOLD field. + UART_SWFC_CONF0_XOFF_THRESHOLD_Pos = 0x0 + // Bit mask of XOFF_THRESHOLD field. + UART_SWFC_CONF0_XOFF_THRESHOLD_Msk = 0x1ff + // Position of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Pos = 0x9 + // Bit mask of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Msk = 0x1fe00 + + // SWFC_CONF1: Software flow-control character configuration + // Position of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x0 + // Bit mask of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0x1ff + // Position of XON_CHAR field. + UART_SWFC_CONF1_XON_CHAR_Pos = 0x9 + // Bit mask of XON_CHAR field. + UART_SWFC_CONF1_XON_CHAR_Msk = 0x1fe00 + + // IDLE_CONF: Frame end idle time configuration + // Position of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Pos = 0x0 + // Bit mask of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Msk = 0x3ff + // Position of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Pos = 0xa + // Bit mask of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Msk = 0xffc00 + // Position of TX_BRK_NUM field. + UART_IDLE_CONF_TX_BRK_NUM_Pos = 0x14 + // Bit mask of TX_BRK_NUM field. + UART_IDLE_CONF_TX_BRK_NUM_Msk = 0xff00000 + + // RS485_CONF: RS485 mode configuration + // Position of RS485_EN field. + UART_RS485_CONF_RS485_EN_Pos = 0x0 + // Bit mask of RS485_EN field. + UART_RS485_CONF_RS485_EN_Msk = 0x1 + // Bit RS485_EN. + UART_RS485_CONF_RS485_EN = 0x1 + // Position of DL0_EN field. + UART_RS485_CONF_DL0_EN_Pos = 0x1 + // Bit mask of DL0_EN field. + UART_RS485_CONF_DL0_EN_Msk = 0x2 + // Bit DL0_EN. + UART_RS485_CONF_DL0_EN = 0x2 + // Position of DL1_EN field. + UART_RS485_CONF_DL1_EN_Pos = 0x2 + // Bit mask of DL1_EN field. + UART_RS485_CONF_DL1_EN_Msk = 0x4 + // Bit DL1_EN. + UART_RS485_CONF_DL1_EN = 0x4 + // Position of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Pos = 0x3 + // Bit mask of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Msk = 0x8 + // Bit RS485TX_RX_EN. + UART_RS485_CONF_RS485TX_RX_EN = 0x8 + // Position of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Pos = 0x4 + // Bit mask of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Msk = 0x10 + // Bit RS485RXBY_TX_EN. + UART_RS485_CONF_RS485RXBY_TX_EN = 0x10 + // Position of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Pos = 0x5 + // Bit mask of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Msk = 0x20 + // Bit RS485_RX_DLY_NUM. + UART_RS485_CONF_RS485_RX_DLY_NUM = 0x20 + // Position of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Pos = 0x6 + // Bit mask of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Msk = 0x3c0 + + // AT_CMD_PRECNT: Pre-sequence timing configuration + // Position of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Pos = 0x0 + // Bit mask of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Msk = 0xffff + + // AT_CMD_POSTCNT: Post-sequence timing configuration + // Position of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Pos = 0x0 + // Bit mask of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Msk = 0xffff + + // AT_CMD_GAPTOUT: Timeout configuration + // Position of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Pos = 0x0 + // Bit mask of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Msk = 0xffff + + // AT_CMD_CHAR: AT escape sequence selection configuration + // Position of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Pos = 0x0 + // Bit mask of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Msk = 0xff + // Position of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Pos = 0x8 + // Bit mask of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Msk = 0xff00 + + // MEM_CONF: UART threshold and allocation configuration + // Position of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Pos = 0x1 + // Bit mask of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Msk = 0xe + // Position of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Pos = 0x4 + // Bit mask of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Msk = 0x70 + // Position of RX_FLOW_THRHD field. + UART_MEM_CONF_RX_FLOW_THRHD_Pos = 0x7 + // Bit mask of RX_FLOW_THRHD field. + UART_MEM_CONF_RX_FLOW_THRHD_Msk = 0xff80 + // Position of RX_TOUT_THRHD field. + UART_MEM_CONF_RX_TOUT_THRHD_Pos = 0x10 + // Bit mask of RX_TOUT_THRHD field. + UART_MEM_CONF_RX_TOUT_THRHD_Msk = 0x3ff0000 + // Position of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x1a + // Bit mask of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x4000000 + // Bit MEM_FORCE_PD. + UART_MEM_CONF_MEM_FORCE_PD = 0x4000000 + // Position of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1b + // Bit mask of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x8000000 + // Bit MEM_FORCE_PU. + UART_MEM_CONF_MEM_FORCE_PU = 0x8000000 + + // MEM_TX_STATUS: TX FIFO write and read offset address + // Position of APB_TX_WADDR field. + UART_MEM_TX_STATUS_APB_TX_WADDR_Pos = 0x0 + // Bit mask of APB_TX_WADDR field. + UART_MEM_TX_STATUS_APB_TX_WADDR_Msk = 0x3ff + // Position of TX_RADDR field. + UART_MEM_TX_STATUS_TX_RADDR_Pos = 0xb + // Bit mask of TX_RADDR field. + UART_MEM_TX_STATUS_TX_RADDR_Msk = 0x1ff800 + + // MEM_RX_STATUS: RX FIFO write and read offset address + // Position of APB_RX_RADDR field. + UART_MEM_RX_STATUS_APB_RX_RADDR_Pos = 0x0 + // Bit mask of APB_RX_RADDR field. + UART_MEM_RX_STATUS_APB_RX_RADDR_Msk = 0x3ff + // Position of RX_WADDR field. + UART_MEM_RX_STATUS_RX_WADDR_Pos = 0xb + // Bit mask of RX_WADDR field. + UART_MEM_RX_STATUS_RX_WADDR_Msk = 0x1ff800 + + // FSM_STATUS: UART transmitter and receiver status + // Position of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0 + // Bit mask of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf + // Position of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4 + // Bit mask of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0 + + // POSPULSE: Autobaud high pulse register + // Position of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Msk = 0xfffff + + // NEGPULSE: Autobaud low pulse register + // Position of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Msk = 0xfffff + + // DATE: UART version control register + // Position of DATE field. + UART_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UART_DATE_DATE_Msk = 0xffffffff + + // ID: UART ID register + // Position of ID field. + UART_ID_ID_Pos = 0x0 + // Bit mask of ID field. + UART_ID_ID_Msk = 0xffffffff +) + +// Constants for UHCI0: Universal Host Controller Interface 0 +const ( + // CONF0: UHCI configuration register + // Position of IN_RST field. + UHCI_CONF0_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + UHCI_CONF0_IN_RST_Msk = 0x1 + // Bit IN_RST. + UHCI_CONF0_IN_RST = 0x1 + // Position of OUT_RST field. + UHCI_CONF0_OUT_RST_Pos = 0x1 + // Bit mask of OUT_RST field. + UHCI_CONF0_OUT_RST_Msk = 0x2 + // Bit OUT_RST. + UHCI_CONF0_OUT_RST = 0x2 + // Position of AHBM_FIFO_RST field. + UHCI_CONF0_AHBM_FIFO_RST_Pos = 0x2 + // Bit mask of AHBM_FIFO_RST field. + UHCI_CONF0_AHBM_FIFO_RST_Msk = 0x4 + // Bit AHBM_FIFO_RST. + UHCI_CONF0_AHBM_FIFO_RST = 0x4 + // Position of AHBM_RST field. + UHCI_CONF0_AHBM_RST_Pos = 0x3 + // Bit mask of AHBM_RST field. + UHCI_CONF0_AHBM_RST_Msk = 0x8 + // Bit AHBM_RST. + UHCI_CONF0_AHBM_RST = 0x8 + // Position of IN_LOOP_TEST field. + UHCI_CONF0_IN_LOOP_TEST_Pos = 0x4 + // Bit mask of IN_LOOP_TEST field. + UHCI_CONF0_IN_LOOP_TEST_Msk = 0x10 + // Bit IN_LOOP_TEST. + UHCI_CONF0_IN_LOOP_TEST = 0x10 + // Position of OUT_LOOP_TEST field. + UHCI_CONF0_OUT_LOOP_TEST_Pos = 0x5 + // Bit mask of OUT_LOOP_TEST field. + UHCI_CONF0_OUT_LOOP_TEST_Msk = 0x20 + // Bit OUT_LOOP_TEST. + UHCI_CONF0_OUT_LOOP_TEST = 0x20 + // Position of OUT_AUTO_WRBACK field. + UHCI_CONF0_OUT_AUTO_WRBACK_Pos = 0x6 + // Bit mask of OUT_AUTO_WRBACK field. + UHCI_CONF0_OUT_AUTO_WRBACK_Msk = 0x40 + // Bit OUT_AUTO_WRBACK. + UHCI_CONF0_OUT_AUTO_WRBACK = 0x40 + // Position of OUT_NO_RESTART_CLR field. + UHCI_CONF0_OUT_NO_RESTART_CLR_Pos = 0x7 + // Bit mask of OUT_NO_RESTART_CLR field. + UHCI_CONF0_OUT_NO_RESTART_CLR_Msk = 0x80 + // Bit OUT_NO_RESTART_CLR. + UHCI_CONF0_OUT_NO_RESTART_CLR = 0x80 + // Position of OUT_EOF_MODE field. + UHCI_CONF0_OUT_EOF_MODE_Pos = 0x8 + // Bit mask of OUT_EOF_MODE field. + UHCI_CONF0_OUT_EOF_MODE_Msk = 0x100 + // Bit OUT_EOF_MODE. + UHCI_CONF0_OUT_EOF_MODE = 0x100 + // Position of UART0_CE field. + UHCI_CONF0_UART0_CE_Pos = 0x9 + // Bit mask of UART0_CE field. + UHCI_CONF0_UART0_CE_Msk = 0x200 + // Bit UART0_CE. + UHCI_CONF0_UART0_CE = 0x200 + // Position of UART1_CE field. + UHCI_CONF0_UART1_CE_Pos = 0xa + // Bit mask of UART1_CE field. + UHCI_CONF0_UART1_CE_Msk = 0x400 + // Bit UART1_CE. + UHCI_CONF0_UART1_CE = 0x400 + // Position of OUTDSCR_BURST_EN field. + UHCI_CONF0_OUTDSCR_BURST_EN_Pos = 0xc + // Bit mask of OUTDSCR_BURST_EN field. + UHCI_CONF0_OUTDSCR_BURST_EN_Msk = 0x1000 + // Bit OUTDSCR_BURST_EN. + UHCI_CONF0_OUTDSCR_BURST_EN = 0x1000 + // Position of INDSCR_BURST_EN field. + UHCI_CONF0_INDSCR_BURST_EN_Pos = 0xd + // Bit mask of INDSCR_BURST_EN field. + UHCI_CONF0_INDSCR_BURST_EN_Msk = 0x2000 + // Bit INDSCR_BURST_EN. + UHCI_CONF0_INDSCR_BURST_EN = 0x2000 + // Position of MEM_TRANS_EN field. + UHCI_CONF0_MEM_TRANS_EN_Pos = 0xf + // Bit mask of MEM_TRANS_EN field. + UHCI_CONF0_MEM_TRANS_EN_Msk = 0x8000 + // Bit MEM_TRANS_EN. + UHCI_CONF0_MEM_TRANS_EN = 0x8000 + // Position of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Pos = 0x10 + // Bit mask of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Msk = 0x10000 + // Bit SEPER_EN. + UHCI_CONF0_SEPER_EN = 0x10000 + // Position of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Pos = 0x11 + // Bit mask of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Msk = 0x20000 + // Bit HEAD_EN. + UHCI_CONF0_HEAD_EN = 0x20000 + // Position of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Pos = 0x12 + // Bit mask of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Msk = 0x40000 + // Bit CRC_REC_EN. + UHCI_CONF0_CRC_REC_EN = 0x40000 + // Position of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Pos = 0x13 + // Bit mask of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Msk = 0x80000 + // Bit UART_IDLE_EOF_EN. + UHCI_CONF0_UART_IDLE_EOF_EN = 0x80000 + // Position of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Pos = 0x14 + // Bit mask of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Msk = 0x100000 + // Bit LEN_EOF_EN. + UHCI_CONF0_LEN_EOF_EN = 0x100000 + // Position of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Pos = 0x15 + // Bit mask of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Msk = 0x200000 + // Bit ENCODE_CRC_EN. + UHCI_CONF0_ENCODE_CRC_EN = 0x200000 + // Position of CLK_EN field. + UHCI_CONF0_CLK_EN_Pos = 0x16 + // Bit mask of CLK_EN field. + UHCI_CONF0_CLK_EN_Msk = 0x400000 + // Bit CLK_EN. + UHCI_CONF0_CLK_EN = 0x400000 + // Position of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Pos = 0x17 + // Bit mask of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Msk = 0x800000 + // Bit UART_RX_BRK_EOF_EN. + UHCI_CONF0_UART_RX_BRK_EOF_EN = 0x800000 + + // INT_RAW: Raw interrupt status + // Position of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Pos = 0x0 + // Bit mask of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Msk = 0x1 + // Bit RX_START_INT_RAW. + UHCI_INT_RAW_RX_START_INT_RAW = 0x1 + // Position of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Pos = 0x1 + // Bit mask of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Msk = 0x2 + // Bit TX_START_INT_RAW. + UHCI_INT_RAW_TX_START_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + UHCI_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + UHCI_INT_RAW_TX_HUNG_INT_RAW = 0x8 + // Position of IN_DONE_INT_RAW field. + UHCI_INT_RAW_IN_DONE_INT_RAW_Pos = 0x4 + // Bit mask of IN_DONE_INT_RAW field. + UHCI_INT_RAW_IN_DONE_INT_RAW_Msk = 0x10 + // Bit IN_DONE_INT_RAW. + UHCI_INT_RAW_IN_DONE_INT_RAW = 0x10 + // Position of IN_SUC_EOF_INT_RAW field. + UHCI_INT_RAW_IN_SUC_EOF_INT_RAW_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_RAW field. + UHCI_INT_RAW_IN_SUC_EOF_INT_RAW_Msk = 0x20 + // Bit IN_SUC_EOF_INT_RAW. + UHCI_INT_RAW_IN_SUC_EOF_INT_RAW = 0x20 + // Position of IN_ERR_EOF_INT_RAW field. + UHCI_INT_RAW_IN_ERR_EOF_INT_RAW_Pos = 0x6 + // Bit mask of IN_ERR_EOF_INT_RAW field. + UHCI_INT_RAW_IN_ERR_EOF_INT_RAW_Msk = 0x40 + // Bit IN_ERR_EOF_INT_RAW. + UHCI_INT_RAW_IN_ERR_EOF_INT_RAW = 0x40 + // Position of OUT_DONE_INT_RAW field. + UHCI_INT_RAW_OUT_DONE_INT_RAW_Pos = 0x7 + // Bit mask of OUT_DONE_INT_RAW field. + UHCI_INT_RAW_OUT_DONE_INT_RAW_Msk = 0x80 + // Bit OUT_DONE_INT_RAW. + UHCI_INT_RAW_OUT_DONE_INT_RAW = 0x80 + // Position of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x8 + // Bit mask of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x100 + // Bit OUT_EOF_INT_RAW. + UHCI_INT_RAW_OUT_EOF_INT_RAW = 0x100 + // Position of IN_DSCR_ERR_INT_RAW field. + UHCI_INT_RAW_IN_DSCR_ERR_INT_RAW_Pos = 0x9 + // Bit mask of IN_DSCR_ERR_INT_RAW field. + UHCI_INT_RAW_IN_DSCR_ERR_INT_RAW_Msk = 0x200 + // Bit IN_DSCR_ERR_INT_RAW. + UHCI_INT_RAW_IN_DSCR_ERR_INT_RAW = 0x200 + // Position of OUT_DSCR_ERR_INT_RAW field. + UHCI_INT_RAW_OUT_DSCR_ERR_INT_RAW_Pos = 0xa + // Bit mask of OUT_DSCR_ERR_INT_RAW field. + UHCI_INT_RAW_OUT_DSCR_ERR_INT_RAW_Msk = 0x400 + // Bit OUT_DSCR_ERR_INT_RAW. + UHCI_INT_RAW_OUT_DSCR_ERR_INT_RAW = 0x400 + // Position of IN_DSCR_EMPTY_INT_RAW field. + UHCI_INT_RAW_IN_DSCR_EMPTY_INT_RAW_Pos = 0xb + // Bit mask of IN_DSCR_EMPTY_INT_RAW field. + UHCI_INT_RAW_IN_DSCR_EMPTY_INT_RAW_Msk = 0x800 + // Bit IN_DSCR_EMPTY_INT_RAW. + UHCI_INT_RAW_IN_DSCR_EMPTY_INT_RAW = 0x800 + // Position of OUTLINK_EOF_ERR_INT_RAW field. + UHCI_INT_RAW_OUTLINK_EOF_ERR_INT_RAW_Pos = 0xc + // Bit mask of OUTLINK_EOF_ERR_INT_RAW field. + UHCI_INT_RAW_OUTLINK_EOF_ERR_INT_RAW_Msk = 0x1000 + // Bit OUTLINK_EOF_ERR_INT_RAW. + UHCI_INT_RAW_OUTLINK_EOF_ERR_INT_RAW = 0x1000 + // Position of OUT_TOTAL_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Pos = 0xd + // Bit mask of OUT_TOTAL_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_TOTAL_EOF_INT_RAW_Msk = 0x2000 + // Bit OUT_TOTAL_EOF_INT_RAW. + UHCI_INT_RAW_OUT_TOTAL_EOF_INT_RAW = 0x2000 + // Position of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Pos = 0xe + // Bit mask of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Msk = 0x4000 + // Bit SEND_S_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW = 0x4000 + // Position of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Pos = 0xf + // Bit mask of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Msk = 0x8000 + // Bit SEND_A_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW = 0x8000 + // Position of DMA_INFIFO_FULL_WM_INT_RAW field. + UHCI_INT_RAW_DMA_INFIFO_FULL_WM_INT_RAW_Pos = 0x10 + // Bit mask of DMA_INFIFO_FULL_WM_INT_RAW field. + UHCI_INT_RAW_DMA_INFIFO_FULL_WM_INT_RAW_Msk = 0x10000 + // Bit DMA_INFIFO_FULL_WM_INT_RAW. + UHCI_INT_RAW_DMA_INFIFO_FULL_WM_INT_RAW = 0x10000 + + // INT_ST: Masked interrupt status + // Position of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Pos = 0x0 + // Bit mask of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Msk = 0x1 + // Bit RX_START_INT_ST. + UHCI_INT_ST_RX_START_INT_ST = 0x1 + // Position of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Pos = 0x1 + // Bit mask of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Msk = 0x2 + // Bit TX_START_INT_ST. + UHCI_INT_ST_TX_START_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + UHCI_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + UHCI_INT_ST_TX_HUNG_INT_ST = 0x8 + // Position of IN_DONE_INT_ST field. + UHCI_INT_ST_IN_DONE_INT_ST_Pos = 0x4 + // Bit mask of IN_DONE_INT_ST field. + UHCI_INT_ST_IN_DONE_INT_ST_Msk = 0x10 + // Bit IN_DONE_INT_ST. + UHCI_INT_ST_IN_DONE_INT_ST = 0x10 + // Position of IN_SUC_EOF_INT_ST field. + UHCI_INT_ST_IN_SUC_EOF_INT_ST_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_ST field. + UHCI_INT_ST_IN_SUC_EOF_INT_ST_Msk = 0x20 + // Bit IN_SUC_EOF_INT_ST. + UHCI_INT_ST_IN_SUC_EOF_INT_ST = 0x20 + // Position of IN_ERR_EOF_INT_ST field. + UHCI_INT_ST_IN_ERR_EOF_INT_ST_Pos = 0x6 + // Bit mask of IN_ERR_EOF_INT_ST field. + UHCI_INT_ST_IN_ERR_EOF_INT_ST_Msk = 0x40 + // Bit IN_ERR_EOF_INT_ST. + UHCI_INT_ST_IN_ERR_EOF_INT_ST = 0x40 + // Position of OUT_DONE_INT_ST field. + UHCI_INT_ST_OUT_DONE_INT_ST_Pos = 0x7 + // Bit mask of OUT_DONE_INT_ST field. + UHCI_INT_ST_OUT_DONE_INT_ST_Msk = 0x80 + // Bit OUT_DONE_INT_ST. + UHCI_INT_ST_OUT_DONE_INT_ST = 0x80 + // Position of OUT_EOF_INT_ST field. + UHCI_INT_ST_OUT_EOF_INT_ST_Pos = 0x8 + // Bit mask of OUT_EOF_INT_ST field. + UHCI_INT_ST_OUT_EOF_INT_ST_Msk = 0x100 + // Bit OUT_EOF_INT_ST. + UHCI_INT_ST_OUT_EOF_INT_ST = 0x100 + // Position of IN_DSCR_ERR_INT_ST field. + UHCI_INT_ST_IN_DSCR_ERR_INT_ST_Pos = 0x9 + // Bit mask of IN_DSCR_ERR_INT_ST field. + UHCI_INT_ST_IN_DSCR_ERR_INT_ST_Msk = 0x200 + // Bit IN_DSCR_ERR_INT_ST. + UHCI_INT_ST_IN_DSCR_ERR_INT_ST = 0x200 + // Position of OUT_DSCR_ERR_INT_ST field. + UHCI_INT_ST_OUT_DSCR_ERR_INT_ST_Pos = 0xa + // Bit mask of OUT_DSCR_ERR_INT_ST field. + UHCI_INT_ST_OUT_DSCR_ERR_INT_ST_Msk = 0x400 + // Bit OUT_DSCR_ERR_INT_ST. + UHCI_INT_ST_OUT_DSCR_ERR_INT_ST = 0x400 + // Position of IN_DSCR_EMPTY_INT_ST field. + UHCI_INT_ST_IN_DSCR_EMPTY_INT_ST_Pos = 0xb + // Bit mask of IN_DSCR_EMPTY_INT_ST field. + UHCI_INT_ST_IN_DSCR_EMPTY_INT_ST_Msk = 0x800 + // Bit IN_DSCR_EMPTY_INT_ST. + UHCI_INT_ST_IN_DSCR_EMPTY_INT_ST = 0x800 + // Position of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Pos = 0xc + // Bit mask of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Msk = 0x1000 + // Bit OUTLINK_EOF_ERR_INT_ST. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST = 0x1000 + // Position of OUT_TOTAL_EOF_INT_ST field. + UHCI_INT_ST_OUT_TOTAL_EOF_INT_ST_Pos = 0xd + // Bit mask of OUT_TOTAL_EOF_INT_ST field. + UHCI_INT_ST_OUT_TOTAL_EOF_INT_ST_Msk = 0x2000 + // Bit OUT_TOTAL_EOF_INT_ST. + UHCI_INT_ST_OUT_TOTAL_EOF_INT_ST = 0x2000 + // Position of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Pos = 0xe + // Bit mask of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Msk = 0x4000 + // Bit SEND_S_REG_Q_INT_ST. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST = 0x4000 + // Position of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Pos = 0xf + // Bit mask of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Msk = 0x8000 + // Bit SEND_A_REG_Q_INT_ST. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST = 0x8000 + // Position of DMA_INFIFO_FULL_WM_INT_ST field. + UHCI_INT_ST_DMA_INFIFO_FULL_WM_INT_ST_Pos = 0x10 + // Bit mask of DMA_INFIFO_FULL_WM_INT_ST field. + UHCI_INT_ST_DMA_INFIFO_FULL_WM_INT_ST_Msk = 0x10000 + // Bit DMA_INFIFO_FULL_WM_INT_ST. + UHCI_INT_ST_DMA_INFIFO_FULL_WM_INT_ST = 0x10000 + + // INT_ENA: Interrupt enable bits + // Position of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Pos = 0x0 + // Bit mask of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Msk = 0x1 + // Bit RX_START_INT_ENA. + UHCI_INT_ENA_RX_START_INT_ENA = 0x1 + // Position of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Pos = 0x1 + // Bit mask of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Msk = 0x2 + // Bit TX_START_INT_ENA. + UHCI_INT_ENA_TX_START_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + UHCI_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + UHCI_INT_ENA_TX_HUNG_INT_ENA = 0x8 + // Position of IN_DONE_INT_ENA field. + UHCI_INT_ENA_IN_DONE_INT_ENA_Pos = 0x4 + // Bit mask of IN_DONE_INT_ENA field. + UHCI_INT_ENA_IN_DONE_INT_ENA_Msk = 0x10 + // Bit IN_DONE_INT_ENA. + UHCI_INT_ENA_IN_DONE_INT_ENA = 0x10 + // Position of IN_SUC_EOF_INT_ENA field. + UHCI_INT_ENA_IN_SUC_EOF_INT_ENA_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_ENA field. + UHCI_INT_ENA_IN_SUC_EOF_INT_ENA_Msk = 0x20 + // Bit IN_SUC_EOF_INT_ENA. + UHCI_INT_ENA_IN_SUC_EOF_INT_ENA = 0x20 + // Position of IN_ERR_EOF_INT_ENA field. + UHCI_INT_ENA_IN_ERR_EOF_INT_ENA_Pos = 0x6 + // Bit mask of IN_ERR_EOF_INT_ENA field. + UHCI_INT_ENA_IN_ERR_EOF_INT_ENA_Msk = 0x40 + // Bit IN_ERR_EOF_INT_ENA. + UHCI_INT_ENA_IN_ERR_EOF_INT_ENA = 0x40 + // Position of OUT_DONE_INT_ENA field. + UHCI_INT_ENA_OUT_DONE_INT_ENA_Pos = 0x7 + // Bit mask of OUT_DONE_INT_ENA field. + UHCI_INT_ENA_OUT_DONE_INT_ENA_Msk = 0x80 + // Bit OUT_DONE_INT_ENA. + UHCI_INT_ENA_OUT_DONE_INT_ENA = 0x80 + // Position of OUT_EOF_INT_ENA field. + UHCI_INT_ENA_OUT_EOF_INT_ENA_Pos = 0x8 + // Bit mask of OUT_EOF_INT_ENA field. + UHCI_INT_ENA_OUT_EOF_INT_ENA_Msk = 0x100 + // Bit OUT_EOF_INT_ENA. + UHCI_INT_ENA_OUT_EOF_INT_ENA = 0x100 + // Position of IN_DSCR_ERR_INT_ENA field. + UHCI_INT_ENA_IN_DSCR_ERR_INT_ENA_Pos = 0x9 + // Bit mask of IN_DSCR_ERR_INT_ENA field. + UHCI_INT_ENA_IN_DSCR_ERR_INT_ENA_Msk = 0x200 + // Bit IN_DSCR_ERR_INT_ENA. + UHCI_INT_ENA_IN_DSCR_ERR_INT_ENA = 0x200 + // Position of OUT_DSCR_ERR_INT_ENA field. + UHCI_INT_ENA_OUT_DSCR_ERR_INT_ENA_Pos = 0xa + // Bit mask of OUT_DSCR_ERR_INT_ENA field. + UHCI_INT_ENA_OUT_DSCR_ERR_INT_ENA_Msk = 0x400 + // Bit OUT_DSCR_ERR_INT_ENA. + UHCI_INT_ENA_OUT_DSCR_ERR_INT_ENA = 0x400 + // Position of IN_DSCR_EMPTY_INT_ENA field. + UHCI_INT_ENA_IN_DSCR_EMPTY_INT_ENA_Pos = 0xb + // Bit mask of IN_DSCR_EMPTY_INT_ENA field. + UHCI_INT_ENA_IN_DSCR_EMPTY_INT_ENA_Msk = 0x800 + // Bit IN_DSCR_EMPTY_INT_ENA. + UHCI_INT_ENA_IN_DSCR_EMPTY_INT_ENA = 0x800 + // Position of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Pos = 0xc + // Bit mask of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Msk = 0x1000 + // Bit OUTLINK_EOF_ERR_INT_ENA. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA = 0x1000 + // Position of OUT_TOTAL_EOF_INT_ENA field. + UHCI_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Pos = 0xd + // Bit mask of OUT_TOTAL_EOF_INT_ENA field. + UHCI_INT_ENA_OUT_TOTAL_EOF_INT_ENA_Msk = 0x2000 + // Bit OUT_TOTAL_EOF_INT_ENA. + UHCI_INT_ENA_OUT_TOTAL_EOF_INT_ENA = 0x2000 + // Position of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Pos = 0xe + // Bit mask of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Msk = 0x4000 + // Bit SEND_S_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA = 0x4000 + // Position of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Pos = 0xf + // Bit mask of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Msk = 0x8000 + // Bit SEND_A_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA = 0x8000 + // Position of DMA_INFIFO_FULL_WM_INT_ENA field. + UHCI_INT_ENA_DMA_INFIFO_FULL_WM_INT_ENA_Pos = 0x10 + // Bit mask of DMA_INFIFO_FULL_WM_INT_ENA field. + UHCI_INT_ENA_DMA_INFIFO_FULL_WM_INT_ENA_Msk = 0x10000 + // Bit DMA_INFIFO_FULL_WM_INT_ENA. + UHCI_INT_ENA_DMA_INFIFO_FULL_WM_INT_ENA = 0x10000 + + // INT_CLR: Interrupt clear bits + // Position of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Pos = 0x0 + // Bit mask of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Msk = 0x1 + // Bit RX_START_INT_CLR. + UHCI_INT_CLR_RX_START_INT_CLR = 0x1 + // Position of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Pos = 0x1 + // Bit mask of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Msk = 0x2 + // Bit TX_START_INT_CLR. + UHCI_INT_CLR_TX_START_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + UHCI_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + UHCI_INT_CLR_TX_HUNG_INT_CLR = 0x8 + // Position of IN_DONE_INT_CLR field. + UHCI_INT_CLR_IN_DONE_INT_CLR_Pos = 0x4 + // Bit mask of IN_DONE_INT_CLR field. + UHCI_INT_CLR_IN_DONE_INT_CLR_Msk = 0x10 + // Bit IN_DONE_INT_CLR. + UHCI_INT_CLR_IN_DONE_INT_CLR = 0x10 + // Position of IN_SUC_EOF_INT_CLR field. + UHCI_INT_CLR_IN_SUC_EOF_INT_CLR_Pos = 0x5 + // Bit mask of IN_SUC_EOF_INT_CLR field. + UHCI_INT_CLR_IN_SUC_EOF_INT_CLR_Msk = 0x20 + // Bit IN_SUC_EOF_INT_CLR. + UHCI_INT_CLR_IN_SUC_EOF_INT_CLR = 0x20 + // Position of IN_ERR_EOF_INT_CLR field. + UHCI_INT_CLR_IN_ERR_EOF_INT_CLR_Pos = 0x6 + // Bit mask of IN_ERR_EOF_INT_CLR field. + UHCI_INT_CLR_IN_ERR_EOF_INT_CLR_Msk = 0x40 + // Bit IN_ERR_EOF_INT_CLR. + UHCI_INT_CLR_IN_ERR_EOF_INT_CLR = 0x40 + // Position of OUT_DONE_INT_CLR field. + UHCI_INT_CLR_OUT_DONE_INT_CLR_Pos = 0x7 + // Bit mask of OUT_DONE_INT_CLR field. + UHCI_INT_CLR_OUT_DONE_INT_CLR_Msk = 0x80 + // Bit OUT_DONE_INT_CLR. + UHCI_INT_CLR_OUT_DONE_INT_CLR = 0x80 + // Position of OUT_EOF_INT_CLR field. + UHCI_INT_CLR_OUT_EOF_INT_CLR_Pos = 0x8 + // Bit mask of OUT_EOF_INT_CLR field. + UHCI_INT_CLR_OUT_EOF_INT_CLR_Msk = 0x100 + // Bit OUT_EOF_INT_CLR. + UHCI_INT_CLR_OUT_EOF_INT_CLR = 0x100 + // Position of IN_DSCR_ERR_INT_CLR field. + UHCI_INT_CLR_IN_DSCR_ERR_INT_CLR_Pos = 0x9 + // Bit mask of IN_DSCR_ERR_INT_CLR field. + UHCI_INT_CLR_IN_DSCR_ERR_INT_CLR_Msk = 0x200 + // Bit IN_DSCR_ERR_INT_CLR. + UHCI_INT_CLR_IN_DSCR_ERR_INT_CLR = 0x200 + // Position of OUT_DSCR_ERR_INT_CLR field. + UHCI_INT_CLR_OUT_DSCR_ERR_INT_CLR_Pos = 0xa + // Bit mask of OUT_DSCR_ERR_INT_CLR field. + UHCI_INT_CLR_OUT_DSCR_ERR_INT_CLR_Msk = 0x400 + // Bit OUT_DSCR_ERR_INT_CLR. + UHCI_INT_CLR_OUT_DSCR_ERR_INT_CLR = 0x400 + // Position of IN_DSCR_EMPTY_INT_CLR field. + UHCI_INT_CLR_IN_DSCR_EMPTY_INT_CLR_Pos = 0xb + // Bit mask of IN_DSCR_EMPTY_INT_CLR field. + UHCI_INT_CLR_IN_DSCR_EMPTY_INT_CLR_Msk = 0x800 + // Bit IN_DSCR_EMPTY_INT_CLR. + UHCI_INT_CLR_IN_DSCR_EMPTY_INT_CLR = 0x800 + // Position of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Pos = 0xc + // Bit mask of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Msk = 0x1000 + // Bit OUTLINK_EOF_ERR_INT_CLR. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR = 0x1000 + // Position of OUT_TOTAL_EOF_INT_CLR field. + UHCI_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Pos = 0xd + // Bit mask of OUT_TOTAL_EOF_INT_CLR field. + UHCI_INT_CLR_OUT_TOTAL_EOF_INT_CLR_Msk = 0x2000 + // Bit OUT_TOTAL_EOF_INT_CLR. + UHCI_INT_CLR_OUT_TOTAL_EOF_INT_CLR = 0x2000 + // Position of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Pos = 0xe + // Bit mask of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Msk = 0x4000 + // Bit SEND_S_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR = 0x4000 + // Position of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Pos = 0xf + // Bit mask of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Msk = 0x8000 + // Bit SEND_A_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR = 0x8000 + // Position of DMA_INFIFO_FULL_WM_INT_CLR field. + UHCI_INT_CLR_DMA_INFIFO_FULL_WM_INT_CLR_Pos = 0x10 + // Bit mask of DMA_INFIFO_FULL_WM_INT_CLR field. + UHCI_INT_CLR_DMA_INFIFO_FULL_WM_INT_CLR_Msk = 0x10000 + // Bit DMA_INFIFO_FULL_WM_INT_CLR. + UHCI_INT_CLR_DMA_INFIFO_FULL_WM_INT_CLR = 0x10000 + + // DMA_OUT_STATUS: DMA data-output status register + // Position of OUT_FULL field. + UHCI_DMA_OUT_STATUS_OUT_FULL_Pos = 0x0 + // Bit mask of OUT_FULL field. + UHCI_DMA_OUT_STATUS_OUT_FULL_Msk = 0x1 + // Bit OUT_FULL. + UHCI_DMA_OUT_STATUS_OUT_FULL = 0x1 + // Position of OUT_EMPTY field. + UHCI_DMA_OUT_STATUS_OUT_EMPTY_Pos = 0x1 + // Bit mask of OUT_EMPTY field. + UHCI_DMA_OUT_STATUS_OUT_EMPTY_Msk = 0x2 + // Bit OUT_EMPTY. + UHCI_DMA_OUT_STATUS_OUT_EMPTY = 0x2 + + // DMA_OUT_PUSH: Push control register of TX FIFO + // Position of OUTFIFO_WDATA field. + UHCI_DMA_OUT_PUSH_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + UHCI_DMA_OUT_PUSH_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + UHCI_DMA_OUT_PUSH_OUTFIFO_PUSH_Pos = 0x10 + // Bit mask of OUTFIFO_PUSH field. + UHCI_DMA_OUT_PUSH_OUTFIFO_PUSH_Msk = 0x10000 + // Bit OUTFIFO_PUSH. + UHCI_DMA_OUT_PUSH_OUTFIFO_PUSH = 0x10000 + + // DMA_IN_STATUS: UHCI data-input status register + // Position of IN_FULL field. + UHCI_DMA_IN_STATUS_IN_FULL_Pos = 0x0 + // Bit mask of IN_FULL field. + UHCI_DMA_IN_STATUS_IN_FULL_Msk = 0x1 + // Bit IN_FULL. + UHCI_DMA_IN_STATUS_IN_FULL = 0x1 + // Position of IN_EMPTY field. + UHCI_DMA_IN_STATUS_IN_EMPTY_Pos = 0x1 + // Bit mask of IN_EMPTY field. + UHCI_DMA_IN_STATUS_IN_EMPTY_Msk = 0x2 + // Bit IN_EMPTY. + UHCI_DMA_IN_STATUS_IN_EMPTY = 0x2 + // Position of RX_ERR_CAUSE field. + UHCI_DMA_IN_STATUS_RX_ERR_CAUSE_Pos = 0x4 + // Bit mask of RX_ERR_CAUSE field. + UHCI_DMA_IN_STATUS_RX_ERR_CAUSE_Msk = 0x70 + + // DMA_IN_POP: Pop control register of RX FIFO + // Position of INFIFO_RDATA field. + UHCI_DMA_IN_POP_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + UHCI_DMA_IN_POP_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + UHCI_DMA_IN_POP_INFIFO_POP_Pos = 0x10 + // Bit mask of INFIFO_POP field. + UHCI_DMA_IN_POP_INFIFO_POP_Msk = 0x10000 + // Bit INFIFO_POP. + UHCI_DMA_IN_POP_INFIFO_POP = 0x10000 + + // DMA_OUT_LINK: Link descriptor address and control + // Position of OUTLINK_ADDR field. + UHCI_DMA_OUT_LINK_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + UHCI_DMA_OUT_LINK_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + UHCI_DMA_OUT_LINK_OUTLINK_STOP_Pos = 0x1c + // Bit mask of OUTLINK_STOP field. + UHCI_DMA_OUT_LINK_OUTLINK_STOP_Msk = 0x10000000 + // Bit OUTLINK_STOP. + UHCI_DMA_OUT_LINK_OUTLINK_STOP = 0x10000000 + // Position of OUTLINK_START field. + UHCI_DMA_OUT_LINK_OUTLINK_START_Pos = 0x1d + // Bit mask of OUTLINK_START field. + UHCI_DMA_OUT_LINK_OUTLINK_START_Msk = 0x20000000 + // Bit OUTLINK_START. + UHCI_DMA_OUT_LINK_OUTLINK_START = 0x20000000 + // Position of OUTLINK_RESTART field. + UHCI_DMA_OUT_LINK_OUTLINK_RESTART_Pos = 0x1e + // Bit mask of OUTLINK_RESTART field. + UHCI_DMA_OUT_LINK_OUTLINK_RESTART_Msk = 0x40000000 + // Bit OUTLINK_RESTART. + UHCI_DMA_OUT_LINK_OUTLINK_RESTART = 0x40000000 + // Position of OUTLINK_PARK field. + UHCI_DMA_OUT_LINK_OUTLINK_PARK_Pos = 0x1f + // Bit mask of OUTLINK_PARK field. + UHCI_DMA_OUT_LINK_OUTLINK_PARK_Msk = 0x80000000 + // Bit OUTLINK_PARK. + UHCI_DMA_OUT_LINK_OUTLINK_PARK = 0x80000000 + + // DMA_IN_LINK: Link descriptor address and control + // Position of INLINK_ADDR field. + UHCI_DMA_IN_LINK_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + UHCI_DMA_IN_LINK_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + UHCI_DMA_IN_LINK_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + UHCI_DMA_IN_LINK_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + UHCI_DMA_IN_LINK_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + UHCI_DMA_IN_LINK_INLINK_STOP_Pos = 0x1c + // Bit mask of INLINK_STOP field. + UHCI_DMA_IN_LINK_INLINK_STOP_Msk = 0x10000000 + // Bit INLINK_STOP. + UHCI_DMA_IN_LINK_INLINK_STOP = 0x10000000 + // Position of INLINK_START field. + UHCI_DMA_IN_LINK_INLINK_START_Pos = 0x1d + // Bit mask of INLINK_START field. + UHCI_DMA_IN_LINK_INLINK_START_Msk = 0x20000000 + // Bit INLINK_START. + UHCI_DMA_IN_LINK_INLINK_START = 0x20000000 + // Position of INLINK_RESTART field. + UHCI_DMA_IN_LINK_INLINK_RESTART_Pos = 0x1e + // Bit mask of INLINK_RESTART field. + UHCI_DMA_IN_LINK_INLINK_RESTART_Msk = 0x40000000 + // Bit INLINK_RESTART. + UHCI_DMA_IN_LINK_INLINK_RESTART = 0x40000000 + // Position of INLINK_PARK field. + UHCI_DMA_IN_LINK_INLINK_PARK_Pos = 0x1f + // Bit mask of INLINK_PARK field. + UHCI_DMA_IN_LINK_INLINK_PARK_Msk = 0x80000000 + // Bit INLINK_PARK. + UHCI_DMA_IN_LINK_INLINK_PARK = 0x80000000 + + // CONF1: UHCI configuration register + // Position of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Pos = 0x0 + // Bit mask of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Msk = 0x1 + // Bit CHECK_SUM_EN. + UHCI_CONF1_CHECK_SUM_EN = 0x1 + // Position of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Pos = 0x1 + // Bit mask of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Msk = 0x2 + // Bit CHECK_SEQ_EN. + UHCI_CONF1_CHECK_SEQ_EN = 0x2 + // Position of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Pos = 0x2 + // Bit mask of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Msk = 0x4 + // Bit CRC_DISABLE. + UHCI_CONF1_CRC_DISABLE = 0x4 + // Position of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Pos = 0x3 + // Bit mask of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Msk = 0x8 + // Bit SAVE_HEAD. + UHCI_CONF1_SAVE_HEAD = 0x8 + // Position of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Pos = 0x4 + // Bit mask of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Msk = 0x10 + // Bit TX_CHECK_SUM_RE. + UHCI_CONF1_TX_CHECK_SUM_RE = 0x10 + // Position of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Pos = 0x5 + // Bit mask of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Msk = 0x20 + // Bit TX_ACK_NUM_RE. + UHCI_CONF1_TX_ACK_NUM_RE = 0x20 + // Position of CHECK_OWNER field. + UHCI_CONF1_CHECK_OWNER_Pos = 0x6 + // Bit mask of CHECK_OWNER field. + UHCI_CONF1_CHECK_OWNER_Msk = 0x40 + // Bit CHECK_OWNER. + UHCI_CONF1_CHECK_OWNER = 0x40 + // Position of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Pos = 0x7 + // Bit mask of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Msk = 0x80 + // Bit WAIT_SW_START. + UHCI_CONF1_WAIT_SW_START = 0x80 + // Position of SW_START field. + UHCI_CONF1_SW_START_Pos = 0x8 + // Bit mask of SW_START field. + UHCI_CONF1_SW_START_Msk = 0x100 + // Bit SW_START. + UHCI_CONF1_SW_START = 0x100 + // Position of DMA_INFIFO_FULL_THRS field. + UHCI_CONF1_DMA_INFIFO_FULL_THRS_Pos = 0x9 + // Bit mask of DMA_INFIFO_FULL_THRS field. + UHCI_CONF1_DMA_INFIFO_FULL_THRS_Msk = 0x1ffe00 + + // STATE0: UHCI decoder status register + // Position of INLINK_DSCR_ADDR field. + UHCI_STATE0_INLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR field. + UHCI_STATE0_INLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of IN_DSCR_STATE field. + UHCI_STATE0_IN_DSCR_STATE_Pos = 0x12 + // Bit mask of IN_DSCR_STATE field. + UHCI_STATE0_IN_DSCR_STATE_Msk = 0xc0000 + // Position of IN_STATE field. + UHCI_STATE0_IN_STATE_Pos = 0x14 + // Bit mask of IN_STATE field. + UHCI_STATE0_IN_STATE_Msk = 0x700000 + // Position of INFIFO_CNT_DEBUG field. + UHCI_STATE0_INFIFO_CNT_DEBUG_Pos = 0x17 + // Bit mask of INFIFO_CNT_DEBUG field. + UHCI_STATE0_INFIFO_CNT_DEBUG_Msk = 0xf800000 + // Position of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Pos = 0x1c + // Bit mask of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Msk = 0x70000000 + + // STATE1: UHCI encoder status register + // Position of OUTLINK_DSCR_ADDR field. + UHCI_STATE1_OUTLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR field. + UHCI_STATE1_OUTLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of OUT_DSCR_STATE field. + UHCI_STATE1_OUT_DSCR_STATE_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE field. + UHCI_STATE1_OUT_DSCR_STATE_Msk = 0xc0000 + // Position of OUT_STATE field. + UHCI_STATE1_OUT_STATE_Pos = 0x14 + // Bit mask of OUT_STATE field. + UHCI_STATE1_OUT_STATE_Msk = 0x700000 + // Position of OUTFIFO_CNT field. + UHCI_STATE1_OUTFIFO_CNT_Pos = 0x17 + // Bit mask of OUTFIFO_CNT field. + UHCI_STATE1_OUTFIFO_CNT_Msk = 0xf800000 + // Position of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Pos = 0x1c + // Bit mask of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Msk = 0x70000000 + + // DMA_OUT_EOF_DES_ADDR: Outlink descriptor address when EOF occurs + // Position of OUT_EOF_DES_ADDR field. + UHCI_DMA_OUT_EOF_DES_ADDR_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + UHCI_DMA_OUT_EOF_DES_ADDR_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // DMA_IN_SUC_EOF_DES_ADDR: Inlink descriptor address when EOF occurs + // Position of IN_SUC_EOF_DES_ADDR field. + UHCI_DMA_IN_SUC_EOF_DES_ADDR_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + UHCI_DMA_IN_SUC_EOF_DES_ADDR_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // DMA_IN_ERR_EOF_DES_ADDR: Inlink descriptor address when errors occur + // Position of IN_ERR_EOF_DES_ADDR field. + UHCI_DMA_IN_ERR_EOF_DES_ADDR_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR field. + UHCI_DMA_IN_ERR_EOF_DES_ADDR_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // DMA_OUT_EOF_BFR_DES_ADDR: Outlink descriptor address before the last transmit descriptor + // Position of OUT_EOF_BFR_DES_ADDR field. + UHCI_DMA_OUT_EOF_BFR_DES_ADDR_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + UHCI_DMA_OUT_EOF_BFR_DES_ADDR_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // AHB_TEST: AHB test register + // Position of AHB_TESTMODE field. + UHCI_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + UHCI_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + UHCI_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + UHCI_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // DMA_IN_DSCR: The third word of the next receive descriptor + // Position of INLINK_DSCR field. + UHCI_DMA_IN_DSCR_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + UHCI_DMA_IN_DSCR_INLINK_DSCR_Msk = 0xffffffff + + // DMA_IN_DSCR_BF0: The third word of current receive descriptor + // Position of INLINK_DSCR_BF0 field. + UHCI_DMA_IN_DSCR_BF0_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + UHCI_DMA_IN_DSCR_BF0_INLINK_DSCR_BF0_Msk = 0xffffffff + + // DMA_OUT_DSCR: The third word of the next transmit descriptor + // Position of OUTLINK_DSCR field. + UHCI_DMA_OUT_DSCR_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + UHCI_DMA_OUT_DSCR_OUTLINK_DSCR_Msk = 0xffffffff + + // DMA_OUT_DSCR_BF0: The third word of current transmit descriptor + // Position of OUTLINK_DSCR_BF0 field. + UHCI_DMA_OUT_DSCR_BF0_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + UHCI_DMA_OUT_DSCR_BF0_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // ESCAPE_CONF: Escape character configuration + // Position of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Pos = 0x0 + // Bit mask of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Msk = 0x1 + // Bit TX_C0_ESC_EN. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN = 0x1 + // Position of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Pos = 0x1 + // Bit mask of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Msk = 0x2 + // Bit TX_DB_ESC_EN. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN = 0x2 + // Position of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Pos = 0x2 + // Bit mask of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Msk = 0x4 + // Bit TX_11_ESC_EN. + UHCI_ESCAPE_CONF_TX_11_ESC_EN = 0x4 + // Position of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Pos = 0x3 + // Bit mask of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Msk = 0x8 + // Bit TX_13_ESC_EN. + UHCI_ESCAPE_CONF_TX_13_ESC_EN = 0x8 + // Position of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Pos = 0x4 + // Bit mask of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Msk = 0x10 + // Bit RX_C0_ESC_EN. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN = 0x10 + // Position of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Pos = 0x5 + // Bit mask of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Msk = 0x20 + // Bit RX_DB_ESC_EN. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN = 0x20 + // Position of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Pos = 0x6 + // Bit mask of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Msk = 0x40 + // Bit RX_11_ESC_EN. + UHCI_ESCAPE_CONF_RX_11_ESC_EN = 0x40 + // Position of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Pos = 0x7 + // Bit mask of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Msk = 0x80 + // Bit RX_13_ESC_EN. + UHCI_ESCAPE_CONF_RX_13_ESC_EN = 0x80 + + // HUNG_CONF: Timeout configuration + // Position of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Pos = 0x0 + // Bit mask of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Msk = 0xff + // Position of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit TXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA = 0x800 + // Position of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Pos = 0xc + // Bit mask of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Msk = 0xff000 + // Position of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Pos = 0x14 + // Bit mask of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Msk = 0x700000 + // Position of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Pos = 0x17 + // Bit mask of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Msk = 0x800000 + // Bit RXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA = 0x800000 + + // RX_HEAD: UHCI packet header register + // Position of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Pos = 0x0 + // Bit mask of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Msk = 0xffffffff + + // QUICK_SENT: UHCI quick_sent configuration register + // Position of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Pos = 0x0 + // Bit mask of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Msk = 0x7 + // Position of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Pos = 0x3 + // Bit mask of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Msk = 0x8 + // Bit SINGLE_SEND_EN. + UHCI_QUICK_SENT_SINGLE_SEND_EN = 0x8 + // Position of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Pos = 0x4 + // Bit mask of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Msk = 0x70 + // Position of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Pos = 0x7 + // Bit mask of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Msk = 0x80 + // Bit ALWAYS_SEND_EN. + UHCI_QUICK_SENT_ALWAYS_SEND_EN = 0x80 + + // Q0_WORD0: Q0_WORD0 quick_sent register + // Position of SEND_Q0_WORD0 field. + UHCI_Q0_WORD0_SEND_Q0_WORD0_Pos = 0x0 + // Bit mask of SEND_Q0_WORD0 field. + UHCI_Q0_WORD0_SEND_Q0_WORD0_Msk = 0xffffffff + + // Q0_WORD1: Q0_WORD1 quick_sent register + // Position of SEND_Q0_WORD1 field. + UHCI_Q0_WORD1_SEND_Q0_WORD1_Pos = 0x0 + // Bit mask of SEND_Q0_WORD1 field. + UHCI_Q0_WORD1_SEND_Q0_WORD1_Msk = 0xffffffff + + // Q1_WORD0: Q1_WORD0 quick_sent register + // Position of SEND_Q1_WORD0 field. + UHCI_Q1_WORD0_SEND_Q1_WORD0_Pos = 0x0 + // Bit mask of SEND_Q1_WORD0 field. + UHCI_Q1_WORD0_SEND_Q1_WORD0_Msk = 0xffffffff + + // Q1_WORD1: Q1_WORD1 quick_sent register + // Position of SEND_Q1_WORD1 field. + UHCI_Q1_WORD1_SEND_Q1_WORD1_Pos = 0x0 + // Bit mask of SEND_Q1_WORD1 field. + UHCI_Q1_WORD1_SEND_Q1_WORD1_Msk = 0xffffffff + + // Q2_WORD0: Q2_WORD0 quick_sent register + // Position of SEND_Q2_WORD0 field. + UHCI_Q2_WORD0_SEND_Q2_WORD0_Pos = 0x0 + // Bit mask of SEND_Q2_WORD0 field. + UHCI_Q2_WORD0_SEND_Q2_WORD0_Msk = 0xffffffff + + // Q2_WORD1: Q2_WORD1 quick_sent register + // Position of SEND_Q2_WORD1 field. + UHCI_Q2_WORD1_SEND_Q2_WORD1_Pos = 0x0 + // Bit mask of SEND_Q2_WORD1 field. + UHCI_Q2_WORD1_SEND_Q2_WORD1_Msk = 0xffffffff + + // Q3_WORD0: Q3_WORD0 quick_sent register + // Position of SEND_Q3_WORD0 field. + UHCI_Q3_WORD0_SEND_Q3_WORD0_Pos = 0x0 + // Bit mask of SEND_Q3_WORD0 field. + UHCI_Q3_WORD0_SEND_Q3_WORD0_Msk = 0xffffffff + + // Q3_WORD1: Q3_WORD1 quick_sent register + // Position of SEND_Q3_WORD1 field. + UHCI_Q3_WORD1_SEND_Q3_WORD1_Pos = 0x0 + // Bit mask of SEND_Q3_WORD1 field. + UHCI_Q3_WORD1_SEND_Q3_WORD1_Msk = 0xffffffff + + // Q4_WORD0: Q4_WORD0 quick_sent register + // Position of SEND_Q4_WORD0 field. + UHCI_Q4_WORD0_SEND_Q4_WORD0_Pos = 0x0 + // Bit mask of SEND_Q4_WORD0 field. + UHCI_Q4_WORD0_SEND_Q4_WORD0_Msk = 0xffffffff + + // Q4_WORD1: Q4_WORD1 quick_sent register + // Position of SEND_Q4_WORD1 field. + UHCI_Q4_WORD1_SEND_Q4_WORD1_Pos = 0x0 + // Bit mask of SEND_Q4_WORD1 field. + UHCI_Q4_WORD1_SEND_Q4_WORD1_Msk = 0xffffffff + + // Q5_WORD0: Q5_WORD0 quick_sent register + // Position of SEND_Q5_WORD0 field. + UHCI_Q5_WORD0_SEND_Q5_WORD0_Pos = 0x0 + // Bit mask of SEND_Q5_WORD0 field. + UHCI_Q5_WORD0_SEND_Q5_WORD0_Msk = 0xffffffff + + // Q5_WORD1: Q5_WORD1 quick_sent register + // Position of SEND_Q5_WORD1 field. + UHCI_Q5_WORD1_SEND_Q5_WORD1_Pos = 0x0 + // Bit mask of SEND_Q5_WORD1 field. + UHCI_Q5_WORD1_SEND_Q5_WORD1_Msk = 0xffffffff + + // Q6_WORD0: Q6_WORD0 quick_sent register + // Position of SEND_Q6_WORD0 field. + UHCI_Q6_WORD0_SEND_Q6_WORD0_Pos = 0x0 + // Bit mask of SEND_Q6_WORD0 field. + UHCI_Q6_WORD0_SEND_Q6_WORD0_Msk = 0xffffffff + + // Q6_WORD1: Q6_WORD1 quick_sent register + // Position of SEND_Q6_WORD1 field. + UHCI_Q6_WORD1_SEND_Q6_WORD1_Pos = 0x0 + // Bit mask of SEND_Q6_WORD1 field. + UHCI_Q6_WORD1_SEND_Q6_WORD1_Msk = 0xffffffff + + // ESC_CONF0: Escape sequence configuration register 0 + // Position of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Pos = 0x0 + // Bit mask of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Msk = 0xff + // Position of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Pos = 0x8 + // Bit mask of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Msk = 0xff00 + // Position of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Pos = 0x10 + // Bit mask of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Msk = 0xff0000 + + // ESC_CONF1: Escape sequence configuration register 1 + // Position of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Pos = 0x0 + // Bit mask of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Msk = 0xff + // Position of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Msk = 0xff0000 + + // ESC_CONF2: Escape sequence configuration register 2 + // Position of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Pos = 0x0 + // Bit mask of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Msk = 0xff + // Position of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Msk = 0xff0000 + + // ESC_CONF3: Escape sequence configuration register 3 + // Position of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Pos = 0x0 + // Bit mask of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Msk = 0xff + // Position of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Msk = 0xff0000 + + // PKT_THRES: Configure register for packet length + // Position of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Pos = 0x0 + // Bit mask of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Msk = 0x1fff + + // DATE: UHCI version control register + // Position of DATE field. + UHCI_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UHCI_DATE_DATE_Msk = 0xffffffff +) + +// Constants for USB0: USB OTG (On-The-Go) +const ( + // GOTGCTL + // Position of SESREQSCS field. + USB_GOTGCTL_SESREQSCS_Pos = 0x0 + // Bit mask of SESREQSCS field. + USB_GOTGCTL_SESREQSCS_Msk = 0x1 + // Bit SESREQSCS. + USB_GOTGCTL_SESREQSCS = 0x1 + // Position of SESREQ field. + USB_GOTGCTL_SESREQ_Pos = 0x1 + // Bit mask of SESREQ field. + USB_GOTGCTL_SESREQ_Msk = 0x2 + // Bit SESREQ. + USB_GOTGCTL_SESREQ = 0x2 + // Position of VBVALIDOVEN field. + USB_GOTGCTL_VBVALIDOVEN_Pos = 0x2 + // Bit mask of VBVALIDOVEN field. + USB_GOTGCTL_VBVALIDOVEN_Msk = 0x4 + // Bit VBVALIDOVEN. + USB_GOTGCTL_VBVALIDOVEN = 0x4 + // Position of VBVALIDOVVAL field. + USB_GOTGCTL_VBVALIDOVVAL_Pos = 0x3 + // Bit mask of VBVALIDOVVAL field. + USB_GOTGCTL_VBVALIDOVVAL_Msk = 0x8 + // Bit VBVALIDOVVAL. + USB_GOTGCTL_VBVALIDOVVAL = 0x8 + // Position of AVALIDOVEN field. + USB_GOTGCTL_AVALIDOVEN_Pos = 0x4 + // Bit mask of AVALIDOVEN field. + USB_GOTGCTL_AVALIDOVEN_Msk = 0x10 + // Bit AVALIDOVEN. + USB_GOTGCTL_AVALIDOVEN = 0x10 + // Position of AVALIDOVVAL field. + USB_GOTGCTL_AVALIDOVVAL_Pos = 0x5 + // Bit mask of AVALIDOVVAL field. + USB_GOTGCTL_AVALIDOVVAL_Msk = 0x20 + // Bit AVALIDOVVAL. + USB_GOTGCTL_AVALIDOVVAL = 0x20 + // Position of BVALIDOVEN field. + USB_GOTGCTL_BVALIDOVEN_Pos = 0x6 + // Bit mask of BVALIDOVEN field. + USB_GOTGCTL_BVALIDOVEN_Msk = 0x40 + // Bit BVALIDOVEN. + USB_GOTGCTL_BVALIDOVEN = 0x40 + // Position of BVALIDOVVAL field. + USB_GOTGCTL_BVALIDOVVAL_Pos = 0x7 + // Bit mask of BVALIDOVVAL field. + USB_GOTGCTL_BVALIDOVVAL_Msk = 0x80 + // Bit BVALIDOVVAL. + USB_GOTGCTL_BVALIDOVVAL = 0x80 + // Position of HSTNEGSCS field. + USB_GOTGCTL_HSTNEGSCS_Pos = 0x8 + // Bit mask of HSTNEGSCS field. + USB_GOTGCTL_HSTNEGSCS_Msk = 0x100 + // Bit HSTNEGSCS. + USB_GOTGCTL_HSTNEGSCS = 0x100 + // Position of HNPREQ field. + USB_GOTGCTL_HNPREQ_Pos = 0x9 + // Bit mask of HNPREQ field. + USB_GOTGCTL_HNPREQ_Msk = 0x200 + // Bit HNPREQ. + USB_GOTGCTL_HNPREQ = 0x200 + // Position of HSTSETHNPEN field. + USB_GOTGCTL_HSTSETHNPEN_Pos = 0xa + // Bit mask of HSTSETHNPEN field. + USB_GOTGCTL_HSTSETHNPEN_Msk = 0x400 + // Bit HSTSETHNPEN. + USB_GOTGCTL_HSTSETHNPEN = 0x400 + // Position of DEVHNPEN field. + USB_GOTGCTL_DEVHNPEN_Pos = 0xb + // Bit mask of DEVHNPEN field. + USB_GOTGCTL_DEVHNPEN_Msk = 0x800 + // Bit DEVHNPEN. + USB_GOTGCTL_DEVHNPEN = 0x800 + // Position of EHEN field. + USB_GOTGCTL_EHEN_Pos = 0xc + // Bit mask of EHEN field. + USB_GOTGCTL_EHEN_Msk = 0x1000 + // Bit EHEN. + USB_GOTGCTL_EHEN = 0x1000 + // Position of DBNCEFLTRBYPASS field. + USB_GOTGCTL_DBNCEFLTRBYPASS_Pos = 0xf + // Bit mask of DBNCEFLTRBYPASS field. + USB_GOTGCTL_DBNCEFLTRBYPASS_Msk = 0x8000 + // Bit DBNCEFLTRBYPASS. + USB_GOTGCTL_DBNCEFLTRBYPASS = 0x8000 + // Position of CONIDSTS field. + USB_GOTGCTL_CONIDSTS_Pos = 0x10 + // Bit mask of CONIDSTS field. + USB_GOTGCTL_CONIDSTS_Msk = 0x10000 + // Bit CONIDSTS. + USB_GOTGCTL_CONIDSTS = 0x10000 + // Position of DBNCTIME field. + USB_GOTGCTL_DBNCTIME_Pos = 0x11 + // Bit mask of DBNCTIME field. + USB_GOTGCTL_DBNCTIME_Msk = 0x20000 + // Bit DBNCTIME. + USB_GOTGCTL_DBNCTIME = 0x20000 + // Position of ASESVLD field. + USB_GOTGCTL_ASESVLD_Pos = 0x12 + // Bit mask of ASESVLD field. + USB_GOTGCTL_ASESVLD_Msk = 0x40000 + // Bit ASESVLD. + USB_GOTGCTL_ASESVLD = 0x40000 + // Position of BSESVLD field. + USB_GOTGCTL_BSESVLD_Pos = 0x13 + // Bit mask of BSESVLD field. + USB_GOTGCTL_BSESVLD_Msk = 0x80000 + // Bit BSESVLD. + USB_GOTGCTL_BSESVLD = 0x80000 + // Position of OTGVER field. + USB_GOTGCTL_OTGVER_Pos = 0x14 + // Bit mask of OTGVER field. + USB_GOTGCTL_OTGVER_Msk = 0x100000 + // Bit OTGVER. + USB_GOTGCTL_OTGVER = 0x100000 + // Position of CURMOD field. + USB_GOTGCTL_CURMOD_Pos = 0x15 + // Bit mask of CURMOD field. + USB_GOTGCTL_CURMOD_Msk = 0x200000 + // Bit CURMOD. + USB_GOTGCTL_CURMOD = 0x200000 + + // GOTGINT + // Position of SESENDDET field. + USB_GOTGINT_SESENDDET_Pos = 0x2 + // Bit mask of SESENDDET field. + USB_GOTGINT_SESENDDET_Msk = 0x4 + // Bit SESENDDET. + USB_GOTGINT_SESENDDET = 0x4 + // Position of SESREQSUCSTSCHNG field. + USB_GOTGINT_SESREQSUCSTSCHNG_Pos = 0x8 + // Bit mask of SESREQSUCSTSCHNG field. + USB_GOTGINT_SESREQSUCSTSCHNG_Msk = 0x100 + // Bit SESREQSUCSTSCHNG. + USB_GOTGINT_SESREQSUCSTSCHNG = 0x100 + // Position of HSTNEGSUCSTSCHNG field. + USB_GOTGINT_HSTNEGSUCSTSCHNG_Pos = 0x9 + // Bit mask of HSTNEGSUCSTSCHNG field. + USB_GOTGINT_HSTNEGSUCSTSCHNG_Msk = 0x200 + // Bit HSTNEGSUCSTSCHNG. + USB_GOTGINT_HSTNEGSUCSTSCHNG = 0x200 + // Position of HSTNEGDET field. + USB_GOTGINT_HSTNEGDET_Pos = 0x11 + // Bit mask of HSTNEGDET field. + USB_GOTGINT_HSTNEGDET_Msk = 0x20000 + // Bit HSTNEGDET. + USB_GOTGINT_HSTNEGDET = 0x20000 + // Position of ADEVTOUTCHG field. + USB_GOTGINT_ADEVTOUTCHG_Pos = 0x12 + // Bit mask of ADEVTOUTCHG field. + USB_GOTGINT_ADEVTOUTCHG_Msk = 0x40000 + // Bit ADEVTOUTCHG. + USB_GOTGINT_ADEVTOUTCHG = 0x40000 + // Position of DBNCEDONE field. + USB_GOTGINT_DBNCEDONE_Pos = 0x13 + // Bit mask of DBNCEDONE field. + USB_GOTGINT_DBNCEDONE_Msk = 0x80000 + // Bit DBNCEDONE. + USB_GOTGINT_DBNCEDONE = 0x80000 + + // GAHBCFG + // Position of GLBLLNTRMSK field. + USB_GAHBCFG_GLBLLNTRMSK_Pos = 0x0 + // Bit mask of GLBLLNTRMSK field. + USB_GAHBCFG_GLBLLNTRMSK_Msk = 0x1 + // Bit GLBLLNTRMSK. + USB_GAHBCFG_GLBLLNTRMSK = 0x1 + // Position of HBSTLEN field. + USB_GAHBCFG_HBSTLEN_Pos = 0x1 + // Bit mask of HBSTLEN field. + USB_GAHBCFG_HBSTLEN_Msk = 0x1e + // Position of DMAEN field. + USB_GAHBCFG_DMAEN_Pos = 0x5 + // Bit mask of DMAEN field. + USB_GAHBCFG_DMAEN_Msk = 0x20 + // Bit DMAEN. + USB_GAHBCFG_DMAEN = 0x20 + // Position of NPTXFEMPLVL field. + USB_GAHBCFG_NPTXFEMPLVL_Pos = 0x7 + // Bit mask of NPTXFEMPLVL field. + USB_GAHBCFG_NPTXFEMPLVL_Msk = 0x80 + // Bit NPTXFEMPLVL. + USB_GAHBCFG_NPTXFEMPLVL = 0x80 + // Position of PTXFEMPLVL field. + USB_GAHBCFG_PTXFEMPLVL_Pos = 0x8 + // Bit mask of PTXFEMPLVL field. + USB_GAHBCFG_PTXFEMPLVL_Msk = 0x100 + // Bit PTXFEMPLVL. + USB_GAHBCFG_PTXFEMPLVL = 0x100 + // Position of REMMEMSUPP field. + USB_GAHBCFG_REMMEMSUPP_Pos = 0x15 + // Bit mask of REMMEMSUPP field. + USB_GAHBCFG_REMMEMSUPP_Msk = 0x200000 + // Bit REMMEMSUPP. + USB_GAHBCFG_REMMEMSUPP = 0x200000 + // Position of NOTIALLDMAWRIT field. + USB_GAHBCFG_NOTIALLDMAWRIT_Pos = 0x16 + // Bit mask of NOTIALLDMAWRIT field. + USB_GAHBCFG_NOTIALLDMAWRIT_Msk = 0x400000 + // Bit NOTIALLDMAWRIT. + USB_GAHBCFG_NOTIALLDMAWRIT = 0x400000 + // Position of AHBSINGLE field. + USB_GAHBCFG_AHBSINGLE_Pos = 0x17 + // Bit mask of AHBSINGLE field. + USB_GAHBCFG_AHBSINGLE_Msk = 0x800000 + // Bit AHBSINGLE. + USB_GAHBCFG_AHBSINGLE = 0x800000 + // Position of INVDESCENDIANESS field. + USB_GAHBCFG_INVDESCENDIANESS_Pos = 0x18 + // Bit mask of INVDESCENDIANESS field. + USB_GAHBCFG_INVDESCENDIANESS_Msk = 0x1000000 + // Bit INVDESCENDIANESS. + USB_GAHBCFG_INVDESCENDIANESS = 0x1000000 + + // GUSBCFG + // Position of TOUTCAL field. + USB_GUSBCFG_TOUTCAL_Pos = 0x0 + // Bit mask of TOUTCAL field. + USB_GUSBCFG_TOUTCAL_Msk = 0x7 + // Position of PHYIF field. + USB_GUSBCFG_PHYIF_Pos = 0x3 + // Bit mask of PHYIF field. + USB_GUSBCFG_PHYIF_Msk = 0x8 + // Bit PHYIF. + USB_GUSBCFG_PHYIF = 0x8 + // Position of ULPI_UTMI_SEL field. + USB_GUSBCFG_ULPI_UTMI_SEL_Pos = 0x4 + // Bit mask of ULPI_UTMI_SEL field. + USB_GUSBCFG_ULPI_UTMI_SEL_Msk = 0x10 + // Bit ULPI_UTMI_SEL. + USB_GUSBCFG_ULPI_UTMI_SEL = 0x10 + // Position of FSINTF field. + USB_GUSBCFG_FSINTF_Pos = 0x5 + // Bit mask of FSINTF field. + USB_GUSBCFG_FSINTF_Msk = 0x20 + // Bit FSINTF. + USB_GUSBCFG_FSINTF = 0x20 + // Position of PHYSEL field. + USB_GUSBCFG_PHYSEL_Pos = 0x6 + // Bit mask of PHYSEL field. + USB_GUSBCFG_PHYSEL_Msk = 0x40 + // Bit PHYSEL. + USB_GUSBCFG_PHYSEL = 0x40 + // Position of SRPCAP field. + USB_GUSBCFG_SRPCAP_Pos = 0x8 + // Bit mask of SRPCAP field. + USB_GUSBCFG_SRPCAP_Msk = 0x100 + // Bit SRPCAP. + USB_GUSBCFG_SRPCAP = 0x100 + // Position of HNPCAP field. + USB_GUSBCFG_HNPCAP_Pos = 0x9 + // Bit mask of HNPCAP field. + USB_GUSBCFG_HNPCAP_Msk = 0x200 + // Bit HNPCAP. + USB_GUSBCFG_HNPCAP = 0x200 + // Position of USBTRDTIM field. + USB_GUSBCFG_USBTRDTIM_Pos = 0xa + // Bit mask of USBTRDTIM field. + USB_GUSBCFG_USBTRDTIM_Msk = 0x3c00 + // Position of TERMSELDLPULSE field. + USB_GUSBCFG_TERMSELDLPULSE_Pos = 0x16 + // Bit mask of TERMSELDLPULSE field. + USB_GUSBCFG_TERMSELDLPULSE_Msk = 0x400000 + // Bit TERMSELDLPULSE. + USB_GUSBCFG_TERMSELDLPULSE = 0x400000 + // Position of TXENDDELAY field. + USB_GUSBCFG_TXENDDELAY_Pos = 0x1c + // Bit mask of TXENDDELAY field. + USB_GUSBCFG_TXENDDELAY_Msk = 0x10000000 + // Bit TXENDDELAY. + USB_GUSBCFG_TXENDDELAY = 0x10000000 + // Position of FORCEHSTMODE field. + USB_GUSBCFG_FORCEHSTMODE_Pos = 0x1d + // Bit mask of FORCEHSTMODE field. + USB_GUSBCFG_FORCEHSTMODE_Msk = 0x20000000 + // Bit FORCEHSTMODE. + USB_GUSBCFG_FORCEHSTMODE = 0x20000000 + // Position of FORCEDEVMODE field. + USB_GUSBCFG_FORCEDEVMODE_Pos = 0x1e + // Bit mask of FORCEDEVMODE field. + USB_GUSBCFG_FORCEDEVMODE_Msk = 0x40000000 + // Bit FORCEDEVMODE. + USB_GUSBCFG_FORCEDEVMODE = 0x40000000 + // Position of CORRUPTTXPKT field. + USB_GUSBCFG_CORRUPTTXPKT_Pos = 0x1f + // Bit mask of CORRUPTTXPKT field. + USB_GUSBCFG_CORRUPTTXPKT_Msk = 0x80000000 + // Bit CORRUPTTXPKT. + USB_GUSBCFG_CORRUPTTXPKT = 0x80000000 + + // GRSTCTL + // Position of CSFTRST field. + USB_GRSTCTL_CSFTRST_Pos = 0x0 + // Bit mask of CSFTRST field. + USB_GRSTCTL_CSFTRST_Msk = 0x1 + // Bit CSFTRST. + USB_GRSTCTL_CSFTRST = 0x1 + // Position of PIUFSSFTRST field. + USB_GRSTCTL_PIUFSSFTRST_Pos = 0x1 + // Bit mask of PIUFSSFTRST field. + USB_GRSTCTL_PIUFSSFTRST_Msk = 0x2 + // Bit PIUFSSFTRST. + USB_GRSTCTL_PIUFSSFTRST = 0x2 + // Position of FRMCNTRRST field. + USB_GRSTCTL_FRMCNTRRST_Pos = 0x2 + // Bit mask of FRMCNTRRST field. + USB_GRSTCTL_FRMCNTRRST_Msk = 0x4 + // Bit FRMCNTRRST. + USB_GRSTCTL_FRMCNTRRST = 0x4 + // Position of RXFFLSH field. + USB_GRSTCTL_RXFFLSH_Pos = 0x4 + // Bit mask of RXFFLSH field. + USB_GRSTCTL_RXFFLSH_Msk = 0x10 + // Bit RXFFLSH. + USB_GRSTCTL_RXFFLSH = 0x10 + // Position of TXFFLSH field. + USB_GRSTCTL_TXFFLSH_Pos = 0x5 + // Bit mask of TXFFLSH field. + USB_GRSTCTL_TXFFLSH_Msk = 0x20 + // Bit TXFFLSH. + USB_GRSTCTL_TXFFLSH = 0x20 + // Position of TXFNUM field. + USB_GRSTCTL_TXFNUM_Pos = 0x6 + // Bit mask of TXFNUM field. + USB_GRSTCTL_TXFNUM_Msk = 0x7c0 + // Position of DMAREQ field. + USB_GRSTCTL_DMAREQ_Pos = 0x1e + // Bit mask of DMAREQ field. + USB_GRSTCTL_DMAREQ_Msk = 0x40000000 + // Bit DMAREQ. + USB_GRSTCTL_DMAREQ = 0x40000000 + // Position of AHBIDLE field. + USB_GRSTCTL_AHBIDLE_Pos = 0x1f + // Bit mask of AHBIDLE field. + USB_GRSTCTL_AHBIDLE_Msk = 0x80000000 + // Bit AHBIDLE. + USB_GRSTCTL_AHBIDLE = 0x80000000 + + // GINTSTS + // Position of CURMOD_INT field. + USB_GINTSTS_CURMOD_INT_Pos = 0x0 + // Bit mask of CURMOD_INT field. + USB_GINTSTS_CURMOD_INT_Msk = 0x1 + // Bit CURMOD_INT. + USB_GINTSTS_CURMOD_INT = 0x1 + // Position of MODEMIS field. + USB_GINTSTS_MODEMIS_Pos = 0x1 + // Bit mask of MODEMIS field. + USB_GINTSTS_MODEMIS_Msk = 0x2 + // Bit MODEMIS. + USB_GINTSTS_MODEMIS = 0x2 + // Position of OTGINT field. + USB_GINTSTS_OTGINT_Pos = 0x2 + // Bit mask of OTGINT field. + USB_GINTSTS_OTGINT_Msk = 0x4 + // Bit OTGINT. + USB_GINTSTS_OTGINT = 0x4 + // Position of SOF field. + USB_GINTSTS_SOF_Pos = 0x3 + // Bit mask of SOF field. + USB_GINTSTS_SOF_Msk = 0x8 + // Bit SOF. + USB_GINTSTS_SOF = 0x8 + // Position of RXFLVI field. + USB_GINTSTS_RXFLVI_Pos = 0x4 + // Bit mask of RXFLVI field. + USB_GINTSTS_RXFLVI_Msk = 0x10 + // Bit RXFLVI. + USB_GINTSTS_RXFLVI = 0x10 + // Position of NPTXFEMP field. + USB_GINTSTS_NPTXFEMP_Pos = 0x5 + // Bit mask of NPTXFEMP field. + USB_GINTSTS_NPTXFEMP_Msk = 0x20 + // Bit NPTXFEMP. + USB_GINTSTS_NPTXFEMP = 0x20 + // Position of GINNAKEFF field. + USB_GINTSTS_GINNAKEFF_Pos = 0x6 + // Bit mask of GINNAKEFF field. + USB_GINTSTS_GINNAKEFF_Msk = 0x40 + // Bit GINNAKEFF. + USB_GINTSTS_GINNAKEFF = 0x40 + // Position of GOUTNAKEFF field. + USB_GINTSTS_GOUTNAKEFF_Pos = 0x7 + // Bit mask of GOUTNAKEFF field. + USB_GINTSTS_GOUTNAKEFF_Msk = 0x80 + // Bit GOUTNAKEFF. + USB_GINTSTS_GOUTNAKEFF = 0x80 + // Position of ERLYSUSP field. + USB_GINTSTS_ERLYSUSP_Pos = 0xa + // Bit mask of ERLYSUSP field. + USB_GINTSTS_ERLYSUSP_Msk = 0x400 + // Bit ERLYSUSP. + USB_GINTSTS_ERLYSUSP = 0x400 + // Position of USBSUSP field. + USB_GINTSTS_USBSUSP_Pos = 0xb + // Bit mask of USBSUSP field. + USB_GINTSTS_USBSUSP_Msk = 0x800 + // Bit USBSUSP. + USB_GINTSTS_USBSUSP = 0x800 + // Position of USBRST field. + USB_GINTSTS_USBRST_Pos = 0xc + // Bit mask of USBRST field. + USB_GINTSTS_USBRST_Msk = 0x1000 + // Bit USBRST. + USB_GINTSTS_USBRST = 0x1000 + // Position of ENUMDONE field. + USB_GINTSTS_ENUMDONE_Pos = 0xd + // Bit mask of ENUMDONE field. + USB_GINTSTS_ENUMDONE_Msk = 0x2000 + // Bit ENUMDONE. + USB_GINTSTS_ENUMDONE = 0x2000 + // Position of ISOOUTDROP field. + USB_GINTSTS_ISOOUTDROP_Pos = 0xe + // Bit mask of ISOOUTDROP field. + USB_GINTSTS_ISOOUTDROP_Msk = 0x4000 + // Bit ISOOUTDROP. + USB_GINTSTS_ISOOUTDROP = 0x4000 + // Position of EOPF field. + USB_GINTSTS_EOPF_Pos = 0xf + // Bit mask of EOPF field. + USB_GINTSTS_EOPF_Msk = 0x8000 + // Bit EOPF. + USB_GINTSTS_EOPF = 0x8000 + // Position of EPMIS field. + USB_GINTSTS_EPMIS_Pos = 0x11 + // Bit mask of EPMIS field. + USB_GINTSTS_EPMIS_Msk = 0x20000 + // Bit EPMIS. + USB_GINTSTS_EPMIS = 0x20000 + // Position of IEPINT field. + USB_GINTSTS_IEPINT_Pos = 0x12 + // Bit mask of IEPINT field. + USB_GINTSTS_IEPINT_Msk = 0x40000 + // Bit IEPINT. + USB_GINTSTS_IEPINT = 0x40000 + // Position of OEPINT field. + USB_GINTSTS_OEPINT_Pos = 0x13 + // Bit mask of OEPINT field. + USB_GINTSTS_OEPINT_Msk = 0x80000 + // Bit OEPINT. + USB_GINTSTS_OEPINT = 0x80000 + // Position of INCOMPISOIN field. + USB_GINTSTS_INCOMPISOIN_Pos = 0x14 + // Bit mask of INCOMPISOIN field. + USB_GINTSTS_INCOMPISOIN_Msk = 0x100000 + // Bit INCOMPISOIN. + USB_GINTSTS_INCOMPISOIN = 0x100000 + // Position of INCOMPIP field. + USB_GINTSTS_INCOMPIP_Pos = 0x15 + // Bit mask of INCOMPIP field. + USB_GINTSTS_INCOMPIP_Msk = 0x200000 + // Bit INCOMPIP. + USB_GINTSTS_INCOMPIP = 0x200000 + // Position of FETSUSP field. + USB_GINTSTS_FETSUSP_Pos = 0x16 + // Bit mask of FETSUSP field. + USB_GINTSTS_FETSUSP_Msk = 0x400000 + // Bit FETSUSP. + USB_GINTSTS_FETSUSP = 0x400000 + // Position of RESETDET field. + USB_GINTSTS_RESETDET_Pos = 0x17 + // Bit mask of RESETDET field. + USB_GINTSTS_RESETDET_Msk = 0x800000 + // Bit RESETDET. + USB_GINTSTS_RESETDET = 0x800000 + // Position of PRTLNT field. + USB_GINTSTS_PRTLNT_Pos = 0x18 + // Bit mask of PRTLNT field. + USB_GINTSTS_PRTLNT_Msk = 0x1000000 + // Bit PRTLNT. + USB_GINTSTS_PRTLNT = 0x1000000 + // Position of HCHLNT field. + USB_GINTSTS_HCHLNT_Pos = 0x19 + // Bit mask of HCHLNT field. + USB_GINTSTS_HCHLNT_Msk = 0x2000000 + // Bit HCHLNT. + USB_GINTSTS_HCHLNT = 0x2000000 + // Position of PTXFEMP field. + USB_GINTSTS_PTXFEMP_Pos = 0x1a + // Bit mask of PTXFEMP field. + USB_GINTSTS_PTXFEMP_Msk = 0x4000000 + // Bit PTXFEMP. + USB_GINTSTS_PTXFEMP = 0x4000000 + // Position of CONIDSTSCHNG field. + USB_GINTSTS_CONIDSTSCHNG_Pos = 0x1c + // Bit mask of CONIDSTSCHNG field. + USB_GINTSTS_CONIDSTSCHNG_Msk = 0x10000000 + // Bit CONIDSTSCHNG. + USB_GINTSTS_CONIDSTSCHNG = 0x10000000 + // Position of DISCONNINT field. + USB_GINTSTS_DISCONNINT_Pos = 0x1d + // Bit mask of DISCONNINT field. + USB_GINTSTS_DISCONNINT_Msk = 0x20000000 + // Bit DISCONNINT. + USB_GINTSTS_DISCONNINT = 0x20000000 + // Position of SESSREQINT field. + USB_GINTSTS_SESSREQINT_Pos = 0x1e + // Bit mask of SESSREQINT field. + USB_GINTSTS_SESSREQINT_Msk = 0x40000000 + // Bit SESSREQINT. + USB_GINTSTS_SESSREQINT = 0x40000000 + // Position of WKUPINT field. + USB_GINTSTS_WKUPINT_Pos = 0x1f + // Bit mask of WKUPINT field. + USB_GINTSTS_WKUPINT_Msk = 0x80000000 + // Bit WKUPINT. + USB_GINTSTS_WKUPINT = 0x80000000 + + // GINTMSK + // Position of MODEMISMSK field. + USB_GINTMSK_MODEMISMSK_Pos = 0x1 + // Bit mask of MODEMISMSK field. + USB_GINTMSK_MODEMISMSK_Msk = 0x2 + // Bit MODEMISMSK. + USB_GINTMSK_MODEMISMSK = 0x2 + // Position of OTGINTMSK field. + USB_GINTMSK_OTGINTMSK_Pos = 0x2 + // Bit mask of OTGINTMSK field. + USB_GINTMSK_OTGINTMSK_Msk = 0x4 + // Bit OTGINTMSK. + USB_GINTMSK_OTGINTMSK = 0x4 + // Position of SOFMSK field. + USB_GINTMSK_SOFMSK_Pos = 0x3 + // Bit mask of SOFMSK field. + USB_GINTMSK_SOFMSK_Msk = 0x8 + // Bit SOFMSK. + USB_GINTMSK_SOFMSK = 0x8 + // Position of RXFLVIMSK field. + USB_GINTMSK_RXFLVIMSK_Pos = 0x4 + // Bit mask of RXFLVIMSK field. + USB_GINTMSK_RXFLVIMSK_Msk = 0x10 + // Bit RXFLVIMSK. + USB_GINTMSK_RXFLVIMSK = 0x10 + // Position of NPTXFEMPMSK field. + USB_GINTMSK_NPTXFEMPMSK_Pos = 0x5 + // Bit mask of NPTXFEMPMSK field. + USB_GINTMSK_NPTXFEMPMSK_Msk = 0x20 + // Bit NPTXFEMPMSK. + USB_GINTMSK_NPTXFEMPMSK = 0x20 + // Position of GINNAKEFFMSK field. + USB_GINTMSK_GINNAKEFFMSK_Pos = 0x6 + // Bit mask of GINNAKEFFMSK field. + USB_GINTMSK_GINNAKEFFMSK_Msk = 0x40 + // Bit GINNAKEFFMSK. + USB_GINTMSK_GINNAKEFFMSK = 0x40 + // Position of GOUTNACKEFFMSK field. + USB_GINTMSK_GOUTNACKEFFMSK_Pos = 0x7 + // Bit mask of GOUTNACKEFFMSK field. + USB_GINTMSK_GOUTNACKEFFMSK_Msk = 0x80 + // Bit GOUTNACKEFFMSK. + USB_GINTMSK_GOUTNACKEFFMSK = 0x80 + // Position of ERLYSUSPMSK field. + USB_GINTMSK_ERLYSUSPMSK_Pos = 0xa + // Bit mask of ERLYSUSPMSK field. + USB_GINTMSK_ERLYSUSPMSK_Msk = 0x400 + // Bit ERLYSUSPMSK. + USB_GINTMSK_ERLYSUSPMSK = 0x400 + // Position of USBSUSPMSK field. + USB_GINTMSK_USBSUSPMSK_Pos = 0xb + // Bit mask of USBSUSPMSK field. + USB_GINTMSK_USBSUSPMSK_Msk = 0x800 + // Bit USBSUSPMSK. + USB_GINTMSK_USBSUSPMSK = 0x800 + // Position of USBRSTMSK field. + USB_GINTMSK_USBRSTMSK_Pos = 0xc + // Bit mask of USBRSTMSK field. + USB_GINTMSK_USBRSTMSK_Msk = 0x1000 + // Bit USBRSTMSK. + USB_GINTMSK_USBRSTMSK = 0x1000 + // Position of ENUMDONEMSK field. + USB_GINTMSK_ENUMDONEMSK_Pos = 0xd + // Bit mask of ENUMDONEMSK field. + USB_GINTMSK_ENUMDONEMSK_Msk = 0x2000 + // Bit ENUMDONEMSK. + USB_GINTMSK_ENUMDONEMSK = 0x2000 + // Position of ISOOUTDROPMSK field. + USB_GINTMSK_ISOOUTDROPMSK_Pos = 0xe + // Bit mask of ISOOUTDROPMSK field. + USB_GINTMSK_ISOOUTDROPMSK_Msk = 0x4000 + // Bit ISOOUTDROPMSK. + USB_GINTMSK_ISOOUTDROPMSK = 0x4000 + // Position of EOPFMSK field. + USB_GINTMSK_EOPFMSK_Pos = 0xf + // Bit mask of EOPFMSK field. + USB_GINTMSK_EOPFMSK_Msk = 0x8000 + // Bit EOPFMSK. + USB_GINTMSK_EOPFMSK = 0x8000 + // Position of EPMISMSK field. + USB_GINTMSK_EPMISMSK_Pos = 0x11 + // Bit mask of EPMISMSK field. + USB_GINTMSK_EPMISMSK_Msk = 0x20000 + // Bit EPMISMSK. + USB_GINTMSK_EPMISMSK = 0x20000 + // Position of IEPINTMSK field. + USB_GINTMSK_IEPINTMSK_Pos = 0x12 + // Bit mask of IEPINTMSK field. + USB_GINTMSK_IEPINTMSK_Msk = 0x40000 + // Bit IEPINTMSK. + USB_GINTMSK_IEPINTMSK = 0x40000 + // Position of OEPINTMSK field. + USB_GINTMSK_OEPINTMSK_Pos = 0x13 + // Bit mask of OEPINTMSK field. + USB_GINTMSK_OEPINTMSK_Msk = 0x80000 + // Bit OEPINTMSK. + USB_GINTMSK_OEPINTMSK = 0x80000 + // Position of INCOMPISOINMSK field. + USB_GINTMSK_INCOMPISOINMSK_Pos = 0x14 + // Bit mask of INCOMPISOINMSK field. + USB_GINTMSK_INCOMPISOINMSK_Msk = 0x100000 + // Bit INCOMPISOINMSK. + USB_GINTMSK_INCOMPISOINMSK = 0x100000 + // Position of INCOMPIPMSK field. + USB_GINTMSK_INCOMPIPMSK_Pos = 0x15 + // Bit mask of INCOMPIPMSK field. + USB_GINTMSK_INCOMPIPMSK_Msk = 0x200000 + // Bit INCOMPIPMSK. + USB_GINTMSK_INCOMPIPMSK = 0x200000 + // Position of FETSUSPMSK field. + USB_GINTMSK_FETSUSPMSK_Pos = 0x16 + // Bit mask of FETSUSPMSK field. + USB_GINTMSK_FETSUSPMSK_Msk = 0x400000 + // Bit FETSUSPMSK. + USB_GINTMSK_FETSUSPMSK = 0x400000 + // Position of RESETDETMSK field. + USB_GINTMSK_RESETDETMSK_Pos = 0x17 + // Bit mask of RESETDETMSK field. + USB_GINTMSK_RESETDETMSK_Msk = 0x800000 + // Bit RESETDETMSK. + USB_GINTMSK_RESETDETMSK = 0x800000 + // Position of PRTLNTMSK field. + USB_GINTMSK_PRTLNTMSK_Pos = 0x18 + // Bit mask of PRTLNTMSK field. + USB_GINTMSK_PRTLNTMSK_Msk = 0x1000000 + // Bit PRTLNTMSK. + USB_GINTMSK_PRTLNTMSK = 0x1000000 + // Position of HCHINTMSK field. + USB_GINTMSK_HCHINTMSK_Pos = 0x19 + // Bit mask of HCHINTMSK field. + USB_GINTMSK_HCHINTMSK_Msk = 0x2000000 + // Bit HCHINTMSK. + USB_GINTMSK_HCHINTMSK = 0x2000000 + // Position of PTXFEMPMSK field. + USB_GINTMSK_PTXFEMPMSK_Pos = 0x1a + // Bit mask of PTXFEMPMSK field. + USB_GINTMSK_PTXFEMPMSK_Msk = 0x4000000 + // Bit PTXFEMPMSK. + USB_GINTMSK_PTXFEMPMSK = 0x4000000 + // Position of CONIDSTSCHNGMSK field. + USB_GINTMSK_CONIDSTSCHNGMSK_Pos = 0x1c + // Bit mask of CONIDSTSCHNGMSK field. + USB_GINTMSK_CONIDSTSCHNGMSK_Msk = 0x10000000 + // Bit CONIDSTSCHNGMSK. + USB_GINTMSK_CONIDSTSCHNGMSK = 0x10000000 + // Position of DISCONNINTMSK field. + USB_GINTMSK_DISCONNINTMSK_Pos = 0x1d + // Bit mask of DISCONNINTMSK field. + USB_GINTMSK_DISCONNINTMSK_Msk = 0x20000000 + // Bit DISCONNINTMSK. + USB_GINTMSK_DISCONNINTMSK = 0x20000000 + // Position of SESSREQINTMSK field. + USB_GINTMSK_SESSREQINTMSK_Pos = 0x1e + // Bit mask of SESSREQINTMSK field. + USB_GINTMSK_SESSREQINTMSK_Msk = 0x40000000 + // Bit SESSREQINTMSK. + USB_GINTMSK_SESSREQINTMSK = 0x40000000 + // Position of WKUPINTMSK field. + USB_GINTMSK_WKUPINTMSK_Pos = 0x1f + // Bit mask of WKUPINTMSK field. + USB_GINTMSK_WKUPINTMSK_Msk = 0x80000000 + // Bit WKUPINTMSK. + USB_GINTMSK_WKUPINTMSK = 0x80000000 + + // GRXSTSR + // Position of G_CHNUM field. + USB_GRXSTSR_G_CHNUM_Pos = 0x0 + // Bit mask of G_CHNUM field. + USB_GRXSTSR_G_CHNUM_Msk = 0xf + // Position of G_BCNT field. + USB_GRXSTSR_G_BCNT_Pos = 0x4 + // Bit mask of G_BCNT field. + USB_GRXSTSR_G_BCNT_Msk = 0x7ff0 + // Position of G_DPID field. + USB_GRXSTSR_G_DPID_Pos = 0xf + // Bit mask of G_DPID field. + USB_GRXSTSR_G_DPID_Msk = 0x18000 + // Position of G_PKTSTS field. + USB_GRXSTSR_G_PKTSTS_Pos = 0x11 + // Bit mask of G_PKTSTS field. + USB_GRXSTSR_G_PKTSTS_Msk = 0x1e0000 + // Position of G_FN field. + USB_GRXSTSR_G_FN_Pos = 0x15 + // Bit mask of G_FN field. + USB_GRXSTSR_G_FN_Msk = 0x1e00000 + + // GRXSTSP + // Position of CHNUM field. + USB_GRXSTSP_CHNUM_Pos = 0x0 + // Bit mask of CHNUM field. + USB_GRXSTSP_CHNUM_Msk = 0xf + // Position of BCNT field. + USB_GRXSTSP_BCNT_Pos = 0x4 + // Bit mask of BCNT field. + USB_GRXSTSP_BCNT_Msk = 0x7ff0 + // Position of DPID field. + USB_GRXSTSP_DPID_Pos = 0xf + // Bit mask of DPID field. + USB_GRXSTSP_DPID_Msk = 0x18000 + // Position of PKTSTS field. + USB_GRXSTSP_PKTSTS_Pos = 0x11 + // Bit mask of PKTSTS field. + USB_GRXSTSP_PKTSTS_Msk = 0x1e0000 + // Position of FN field. + USB_GRXSTSP_FN_Pos = 0x15 + // Bit mask of FN field. + USB_GRXSTSP_FN_Msk = 0x1e00000 + + // GRXFSIZ + // Position of RXFDEP field. + USB_GRXFSIZ_RXFDEP_Pos = 0x0 + // Bit mask of RXFDEP field. + USB_GRXFSIZ_RXFDEP_Msk = 0xffff + + // GNPTXFSIZ + // Position of NPTXFSTADDR field. + USB_GNPTXFSIZ_NPTXFSTADDR_Pos = 0x0 + // Bit mask of NPTXFSTADDR field. + USB_GNPTXFSIZ_NPTXFSTADDR_Msk = 0xffff + // Position of NPTXFDEP field. + USB_GNPTXFSIZ_NPTXFDEP_Pos = 0x10 + // Bit mask of NPTXFDEP field. + USB_GNPTXFSIZ_NPTXFDEP_Msk = 0xffff0000 + + // GNPTXSTS + // Position of NPTXFSPCAVAIL field. + USB_GNPTXSTS_NPTXFSPCAVAIL_Pos = 0x0 + // Bit mask of NPTXFSPCAVAIL field. + USB_GNPTXSTS_NPTXFSPCAVAIL_Msk = 0xffff + // Position of NPTXQSPCAVAIL field. + USB_GNPTXSTS_NPTXQSPCAVAIL_Pos = 0x10 + // Bit mask of NPTXQSPCAVAIL field. + USB_GNPTXSTS_NPTXQSPCAVAIL_Msk = 0xf0000 + // Position of NPTXQTOP field. + USB_GNPTXSTS_NPTXQTOP_Pos = 0x18 + // Bit mask of NPTXQTOP field. + USB_GNPTXSTS_NPTXQTOP_Msk = 0x7f000000 + + // GSNPSID + // Position of SYNOPSYSID field. + USB_GSNPSID_SYNOPSYSID_Pos = 0x0 + // Bit mask of SYNOPSYSID field. + USB_GSNPSID_SYNOPSYSID_Msk = 0xffffffff + + // GHWCFG1 + // Position of EPDIR field. + USB_GHWCFG1_EPDIR_Pos = 0x0 + // Bit mask of EPDIR field. + USB_GHWCFG1_EPDIR_Msk = 0xffffffff + + // GHWCFG2 + // Position of OTGMODE field. + USB_GHWCFG2_OTGMODE_Pos = 0x0 + // Bit mask of OTGMODE field. + USB_GHWCFG2_OTGMODE_Msk = 0x7 + // Position of OTGARCH field. + USB_GHWCFG2_OTGARCH_Pos = 0x3 + // Bit mask of OTGARCH field. + USB_GHWCFG2_OTGARCH_Msk = 0x18 + // Position of SINGPNT field. + USB_GHWCFG2_SINGPNT_Pos = 0x5 + // Bit mask of SINGPNT field. + USB_GHWCFG2_SINGPNT_Msk = 0x20 + // Bit SINGPNT. + USB_GHWCFG2_SINGPNT = 0x20 + // Position of HSPHYTYPE field. + USB_GHWCFG2_HSPHYTYPE_Pos = 0x6 + // Bit mask of HSPHYTYPE field. + USB_GHWCFG2_HSPHYTYPE_Msk = 0xc0 + // Position of FSPHYTYPE field. + USB_GHWCFG2_FSPHYTYPE_Pos = 0x8 + // Bit mask of FSPHYTYPE field. + USB_GHWCFG2_FSPHYTYPE_Msk = 0x300 + // Position of NUMDEVEPS field. + USB_GHWCFG2_NUMDEVEPS_Pos = 0xa + // Bit mask of NUMDEVEPS field. + USB_GHWCFG2_NUMDEVEPS_Msk = 0x3c00 + // Position of NUMHSTCHNL field. + USB_GHWCFG2_NUMHSTCHNL_Pos = 0xe + // Bit mask of NUMHSTCHNL field. + USB_GHWCFG2_NUMHSTCHNL_Msk = 0x3c000 + // Position of PERIOSUPPORT field. + USB_GHWCFG2_PERIOSUPPORT_Pos = 0x12 + // Bit mask of PERIOSUPPORT field. + USB_GHWCFG2_PERIOSUPPORT_Msk = 0x40000 + // Bit PERIOSUPPORT. + USB_GHWCFG2_PERIOSUPPORT = 0x40000 + // Position of DYNFIFOSIZING field. + USB_GHWCFG2_DYNFIFOSIZING_Pos = 0x13 + // Bit mask of DYNFIFOSIZING field. + USB_GHWCFG2_DYNFIFOSIZING_Msk = 0x80000 + // Bit DYNFIFOSIZING. + USB_GHWCFG2_DYNFIFOSIZING = 0x80000 + // Position of MULTIPROCINTRPT field. + USB_GHWCFG2_MULTIPROCINTRPT_Pos = 0x14 + // Bit mask of MULTIPROCINTRPT field. + USB_GHWCFG2_MULTIPROCINTRPT_Msk = 0x100000 + // Bit MULTIPROCINTRPT. + USB_GHWCFG2_MULTIPROCINTRPT = 0x100000 + // Position of NPTXQDEPTH field. + USB_GHWCFG2_NPTXQDEPTH_Pos = 0x16 + // Bit mask of NPTXQDEPTH field. + USB_GHWCFG2_NPTXQDEPTH_Msk = 0xc00000 + // Position of PTXQDEPTH field. + USB_GHWCFG2_PTXQDEPTH_Pos = 0x18 + // Bit mask of PTXQDEPTH field. + USB_GHWCFG2_PTXQDEPTH_Msk = 0x3000000 + // Position of TKNQDEPTH field. + USB_GHWCFG2_TKNQDEPTH_Pos = 0x1a + // Bit mask of TKNQDEPTH field. + USB_GHWCFG2_TKNQDEPTH_Msk = 0x7c000000 + // Position of OTG_ENABLE_IC_USB field. + USB_GHWCFG2_OTG_ENABLE_IC_USB_Pos = 0x1f + // Bit mask of OTG_ENABLE_IC_USB field. + USB_GHWCFG2_OTG_ENABLE_IC_USB_Msk = 0x80000000 + // Bit OTG_ENABLE_IC_USB. + USB_GHWCFG2_OTG_ENABLE_IC_USB = 0x80000000 + + // GHWCFG3 + // Position of XFERSIZEWIDTH field. + USB_GHWCFG3_XFERSIZEWIDTH_Pos = 0x0 + // Bit mask of XFERSIZEWIDTH field. + USB_GHWCFG3_XFERSIZEWIDTH_Msk = 0xf + // Position of PKTSIZEWIDTH field. + USB_GHWCFG3_PKTSIZEWIDTH_Pos = 0x4 + // Bit mask of PKTSIZEWIDTH field. + USB_GHWCFG3_PKTSIZEWIDTH_Msk = 0x70 + // Position of OTGEN field. + USB_GHWCFG3_OTGEN_Pos = 0x7 + // Bit mask of OTGEN field. + USB_GHWCFG3_OTGEN_Msk = 0x80 + // Bit OTGEN. + USB_GHWCFG3_OTGEN = 0x80 + // Position of I2CINTSEL field. + USB_GHWCFG3_I2CINTSEL_Pos = 0x8 + // Bit mask of I2CINTSEL field. + USB_GHWCFG3_I2CINTSEL_Msk = 0x100 + // Bit I2CINTSEL. + USB_GHWCFG3_I2CINTSEL = 0x100 + // Position of VNDCTLSUPT field. + USB_GHWCFG3_VNDCTLSUPT_Pos = 0x9 + // Bit mask of VNDCTLSUPT field. + USB_GHWCFG3_VNDCTLSUPT_Msk = 0x200 + // Bit VNDCTLSUPT. + USB_GHWCFG3_VNDCTLSUPT = 0x200 + // Position of OPTFEATURE field. + USB_GHWCFG3_OPTFEATURE_Pos = 0xa + // Bit mask of OPTFEATURE field. + USB_GHWCFG3_OPTFEATURE_Msk = 0x400 + // Bit OPTFEATURE. + USB_GHWCFG3_OPTFEATURE = 0x400 + // Position of RSTTYPE field. + USB_GHWCFG3_RSTTYPE_Pos = 0xb + // Bit mask of RSTTYPE field. + USB_GHWCFG3_RSTTYPE_Msk = 0x800 + // Bit RSTTYPE. + USB_GHWCFG3_RSTTYPE = 0x800 + // Position of ADPSUPPORT field. + USB_GHWCFG3_ADPSUPPORT_Pos = 0xc + // Bit mask of ADPSUPPORT field. + USB_GHWCFG3_ADPSUPPORT_Msk = 0x1000 + // Bit ADPSUPPORT. + USB_GHWCFG3_ADPSUPPORT = 0x1000 + // Position of HSICMODE field. + USB_GHWCFG3_HSICMODE_Pos = 0xd + // Bit mask of HSICMODE field. + USB_GHWCFG3_HSICMODE_Msk = 0x2000 + // Bit HSICMODE. + USB_GHWCFG3_HSICMODE = 0x2000 + // Position of BCSUPPORT field. + USB_GHWCFG3_BCSUPPORT_Pos = 0xe + // Bit mask of BCSUPPORT field. + USB_GHWCFG3_BCSUPPORT_Msk = 0x4000 + // Bit BCSUPPORT. + USB_GHWCFG3_BCSUPPORT = 0x4000 + // Position of LPMMODE field. + USB_GHWCFG3_LPMMODE_Pos = 0xf + // Bit mask of LPMMODE field. + USB_GHWCFG3_LPMMODE_Msk = 0x8000 + // Bit LPMMODE. + USB_GHWCFG3_LPMMODE = 0x8000 + // Position of DFIFODEPTH field. + USB_GHWCFG3_DFIFODEPTH_Pos = 0x10 + // Bit mask of DFIFODEPTH field. + USB_GHWCFG3_DFIFODEPTH_Msk = 0xffff0000 + + // GHWCFG4 + // Position of G_NUMDEVPERIOEPS field. + USB_GHWCFG4_G_NUMDEVPERIOEPS_Pos = 0x0 + // Bit mask of G_NUMDEVPERIOEPS field. + USB_GHWCFG4_G_NUMDEVPERIOEPS_Msk = 0xf + // Position of G_PARTIALPWRDN field. + USB_GHWCFG4_G_PARTIALPWRDN_Pos = 0x4 + // Bit mask of G_PARTIALPWRDN field. + USB_GHWCFG4_G_PARTIALPWRDN_Msk = 0x10 + // Bit G_PARTIALPWRDN. + USB_GHWCFG4_G_PARTIALPWRDN = 0x10 + // Position of G_AHBFREQ field. + USB_GHWCFG4_G_AHBFREQ_Pos = 0x5 + // Bit mask of G_AHBFREQ field. + USB_GHWCFG4_G_AHBFREQ_Msk = 0x20 + // Bit G_AHBFREQ. + USB_GHWCFG4_G_AHBFREQ = 0x20 + // Position of G_HIBERNATION field. + USB_GHWCFG4_G_HIBERNATION_Pos = 0x6 + // Bit mask of G_HIBERNATION field. + USB_GHWCFG4_G_HIBERNATION_Msk = 0x40 + // Bit G_HIBERNATION. + USB_GHWCFG4_G_HIBERNATION = 0x40 + // Position of G_EXTENDEDHIBERNATION field. + USB_GHWCFG4_G_EXTENDEDHIBERNATION_Pos = 0x7 + // Bit mask of G_EXTENDEDHIBERNATION field. + USB_GHWCFG4_G_EXTENDEDHIBERNATION_Msk = 0x80 + // Bit G_EXTENDEDHIBERNATION. + USB_GHWCFG4_G_EXTENDEDHIBERNATION = 0x80 + // Position of G_ACGSUPT field. + USB_GHWCFG4_G_ACGSUPT_Pos = 0xc + // Bit mask of G_ACGSUPT field. + USB_GHWCFG4_G_ACGSUPT_Msk = 0x1000 + // Bit G_ACGSUPT. + USB_GHWCFG4_G_ACGSUPT = 0x1000 + // Position of G_ENHANCEDLPMSUPT field. + USB_GHWCFG4_G_ENHANCEDLPMSUPT_Pos = 0xd + // Bit mask of G_ENHANCEDLPMSUPT field. + USB_GHWCFG4_G_ENHANCEDLPMSUPT_Msk = 0x2000 + // Bit G_ENHANCEDLPMSUPT. + USB_GHWCFG4_G_ENHANCEDLPMSUPT = 0x2000 + // Position of G_PHYDATAWIDTH field. + USB_GHWCFG4_G_PHYDATAWIDTH_Pos = 0xe + // Bit mask of G_PHYDATAWIDTH field. + USB_GHWCFG4_G_PHYDATAWIDTH_Msk = 0xc000 + // Position of G_NUMCTLEPS field. + USB_GHWCFG4_G_NUMCTLEPS_Pos = 0x10 + // Bit mask of G_NUMCTLEPS field. + USB_GHWCFG4_G_NUMCTLEPS_Msk = 0xf0000 + // Position of G_IDDQFLTR field. + USB_GHWCFG4_G_IDDQFLTR_Pos = 0x14 + // Bit mask of G_IDDQFLTR field. + USB_GHWCFG4_G_IDDQFLTR_Msk = 0x100000 + // Bit G_IDDQFLTR. + USB_GHWCFG4_G_IDDQFLTR = 0x100000 + // Position of G_VBUSVALIDFLTR field. + USB_GHWCFG4_G_VBUSVALIDFLTR_Pos = 0x15 + // Bit mask of G_VBUSVALIDFLTR field. + USB_GHWCFG4_G_VBUSVALIDFLTR_Msk = 0x200000 + // Bit G_VBUSVALIDFLTR. + USB_GHWCFG4_G_VBUSVALIDFLTR = 0x200000 + // Position of G_AVALIDFLTR field. + USB_GHWCFG4_G_AVALIDFLTR_Pos = 0x16 + // Bit mask of G_AVALIDFLTR field. + USB_GHWCFG4_G_AVALIDFLTR_Msk = 0x400000 + // Bit G_AVALIDFLTR. + USB_GHWCFG4_G_AVALIDFLTR = 0x400000 + // Position of G_BVALIDFLTR field. + USB_GHWCFG4_G_BVALIDFLTR_Pos = 0x17 + // Bit mask of G_BVALIDFLTR field. + USB_GHWCFG4_G_BVALIDFLTR_Msk = 0x800000 + // Bit G_BVALIDFLTR. + USB_GHWCFG4_G_BVALIDFLTR = 0x800000 + // Position of G_SESSENDFLTR field. + USB_GHWCFG4_G_SESSENDFLTR_Pos = 0x18 + // Bit mask of G_SESSENDFLTR field. + USB_GHWCFG4_G_SESSENDFLTR_Msk = 0x1000000 + // Bit G_SESSENDFLTR. + USB_GHWCFG4_G_SESSENDFLTR = 0x1000000 + // Position of G_DEDFIFOMODE field. + USB_GHWCFG4_G_DEDFIFOMODE_Pos = 0x19 + // Bit mask of G_DEDFIFOMODE field. + USB_GHWCFG4_G_DEDFIFOMODE_Msk = 0x2000000 + // Bit G_DEDFIFOMODE. + USB_GHWCFG4_G_DEDFIFOMODE = 0x2000000 + // Position of G_INEPS field. + USB_GHWCFG4_G_INEPS_Pos = 0x1a + // Bit mask of G_INEPS field. + USB_GHWCFG4_G_INEPS_Msk = 0x3c000000 + // Position of G_DESCDMAENABLED field. + USB_GHWCFG4_G_DESCDMAENABLED_Pos = 0x1e + // Bit mask of G_DESCDMAENABLED field. + USB_GHWCFG4_G_DESCDMAENABLED_Msk = 0x40000000 + // Bit G_DESCDMAENABLED. + USB_GHWCFG4_G_DESCDMAENABLED = 0x40000000 + // Position of G_DESCDMA field. + USB_GHWCFG4_G_DESCDMA_Pos = 0x1f + // Bit mask of G_DESCDMA field. + USB_GHWCFG4_G_DESCDMA_Msk = 0x80000000 + // Bit G_DESCDMA. + USB_GHWCFG4_G_DESCDMA = 0x80000000 + + // GDFIFOCFG + // Position of GDFIFOCFG field. + USB_GDFIFOCFG_GDFIFOCFG_Pos = 0x0 + // Bit mask of GDFIFOCFG field. + USB_GDFIFOCFG_GDFIFOCFG_Msk = 0xffff + // Position of EPINFOBASEADDR field. + USB_GDFIFOCFG_EPINFOBASEADDR_Pos = 0x10 + // Bit mask of EPINFOBASEADDR field. + USB_GDFIFOCFG_EPINFOBASEADDR_Msk = 0xffff0000 + + // HPTXFSIZ + // Position of PTXFSTADDR field. + USB_HPTXFSIZ_PTXFSTADDR_Pos = 0x0 + // Bit mask of PTXFSTADDR field. + USB_HPTXFSIZ_PTXFSTADDR_Msk = 0xffff + // Position of PTXFSIZE field. + USB_HPTXFSIZ_PTXFSIZE_Pos = 0x10 + // Bit mask of PTXFSIZE field. + USB_HPTXFSIZ_PTXFSIZE_Msk = 0xffff0000 + + // DIEPTXF1 + // Position of INEP1TXFSTADDR field. + USB_DIEPTXF1_INEP1TXFSTADDR_Pos = 0x0 + // Bit mask of INEP1TXFSTADDR field. + USB_DIEPTXF1_INEP1TXFSTADDR_Msk = 0xffff + // Position of INEP1TXFDEP field. + USB_DIEPTXF1_INEP1TXFDEP_Pos = 0x10 + // Bit mask of INEP1TXFDEP field. + USB_DIEPTXF1_INEP1TXFDEP_Msk = 0xffff0000 + + // DIEPTXF2 + // Position of INEP2TXFSTADDR field. + USB_DIEPTXF2_INEP2TXFSTADDR_Pos = 0x0 + // Bit mask of INEP2TXFSTADDR field. + USB_DIEPTXF2_INEP2TXFSTADDR_Msk = 0xffff + // Position of INEP2TXFDEP field. + USB_DIEPTXF2_INEP2TXFDEP_Pos = 0x10 + // Bit mask of INEP2TXFDEP field. + USB_DIEPTXF2_INEP2TXFDEP_Msk = 0xffff0000 + + // DIEPTXF3 + // Position of INEP3TXFSTADDR field. + USB_DIEPTXF3_INEP3TXFSTADDR_Pos = 0x0 + // Bit mask of INEP3TXFSTADDR field. + USB_DIEPTXF3_INEP3TXFSTADDR_Msk = 0xffff + // Position of INEP3TXFDEP field. + USB_DIEPTXF3_INEP3TXFDEP_Pos = 0x10 + // Bit mask of INEP3TXFDEP field. + USB_DIEPTXF3_INEP3TXFDEP_Msk = 0xffff0000 + + // DIEPTXF4 + // Position of INEP4TXFSTADDR field. + USB_DIEPTXF4_INEP4TXFSTADDR_Pos = 0x0 + // Bit mask of INEP4TXFSTADDR field. + USB_DIEPTXF4_INEP4TXFSTADDR_Msk = 0xffff + // Position of INEP4TXFDEP field. + USB_DIEPTXF4_INEP4TXFDEP_Pos = 0x10 + // Bit mask of INEP4TXFDEP field. + USB_DIEPTXF4_INEP4TXFDEP_Msk = 0xffff0000 + + // HCFG + // Position of H_FSLSPCLKSEL field. + USB_HCFG_H_FSLSPCLKSEL_Pos = 0x0 + // Bit mask of H_FSLSPCLKSEL field. + USB_HCFG_H_FSLSPCLKSEL_Msk = 0x3 + // Position of H_FSLSSUPP field. + USB_HCFG_H_FSLSSUPP_Pos = 0x2 + // Bit mask of H_FSLSSUPP field. + USB_HCFG_H_FSLSSUPP_Msk = 0x4 + // Bit H_FSLSSUPP. + USB_HCFG_H_FSLSSUPP = 0x4 + // Position of H_ENA32KHZS field. + USB_HCFG_H_ENA32KHZS_Pos = 0x7 + // Bit mask of H_ENA32KHZS field. + USB_HCFG_H_ENA32KHZS_Msk = 0x80 + // Bit H_ENA32KHZS. + USB_HCFG_H_ENA32KHZS = 0x80 + // Position of H_DESCDMA field. + USB_HCFG_H_DESCDMA_Pos = 0x17 + // Bit mask of H_DESCDMA field. + USB_HCFG_H_DESCDMA_Msk = 0x800000 + // Bit H_DESCDMA. + USB_HCFG_H_DESCDMA = 0x800000 + // Position of H_FRLISTEN field. + USB_HCFG_H_FRLISTEN_Pos = 0x18 + // Bit mask of H_FRLISTEN field. + USB_HCFG_H_FRLISTEN_Msk = 0x3000000 + // Position of H_PERSCHEDENA field. + USB_HCFG_H_PERSCHEDENA_Pos = 0x1a + // Bit mask of H_PERSCHEDENA field. + USB_HCFG_H_PERSCHEDENA_Msk = 0x4000000 + // Bit H_PERSCHEDENA. + USB_HCFG_H_PERSCHEDENA = 0x4000000 + // Position of H_MODECHTIMEN field. + USB_HCFG_H_MODECHTIMEN_Pos = 0x1f + // Bit mask of H_MODECHTIMEN field. + USB_HCFG_H_MODECHTIMEN_Msk = 0x80000000 + // Bit H_MODECHTIMEN. + USB_HCFG_H_MODECHTIMEN = 0x80000000 + + // HFIR + // Position of FRINT field. + USB_HFIR_FRINT_Pos = 0x0 + // Bit mask of FRINT field. + USB_HFIR_FRINT_Msk = 0xffff + // Position of HFIRRLDCTRL field. + USB_HFIR_HFIRRLDCTRL_Pos = 0x10 + // Bit mask of HFIRRLDCTRL field. + USB_HFIR_HFIRRLDCTRL_Msk = 0x10000 + // Bit HFIRRLDCTRL. + USB_HFIR_HFIRRLDCTRL = 0x10000 + + // HFNUM + // Position of FRNUM field. + USB_HFNUM_FRNUM_Pos = 0x0 + // Bit mask of FRNUM field. + USB_HFNUM_FRNUM_Msk = 0x3fff + // Position of FRREM field. + USB_HFNUM_FRREM_Pos = 0x10 + // Bit mask of FRREM field. + USB_HFNUM_FRREM_Msk = 0xffff0000 + + // HPTXSTS + // Position of PTXFSPCAVAIL field. + USB_HPTXSTS_PTXFSPCAVAIL_Pos = 0x0 + // Bit mask of PTXFSPCAVAIL field. + USB_HPTXSTS_PTXFSPCAVAIL_Msk = 0xffff + // Position of PTXQSPCAVAIL field. + USB_HPTXSTS_PTXQSPCAVAIL_Pos = 0x10 + // Bit mask of PTXQSPCAVAIL field. + USB_HPTXSTS_PTXQSPCAVAIL_Msk = 0x1f0000 + // Position of PTXQTOP field. + USB_HPTXSTS_PTXQTOP_Pos = 0x18 + // Bit mask of PTXQTOP field. + USB_HPTXSTS_PTXQTOP_Msk = 0xff000000 + + // HAINT + // Position of HAINT field. + USB_HAINT_HAINT_Pos = 0x0 + // Bit mask of HAINT field. + USB_HAINT_HAINT_Msk = 0xff + + // HAINTMSK + // Position of HAINTMSK field. + USB_HAINTMSK_HAINTMSK_Pos = 0x0 + // Bit mask of HAINTMSK field. + USB_HAINTMSK_HAINTMSK_Msk = 0xff + + // HFLBADDR + // Position of HFLBADDR field. + USB_HFLBADDR_HFLBADDR_Pos = 0x0 + // Bit mask of HFLBADDR field. + USB_HFLBADDR_HFLBADDR_Msk = 0xffffffff + + // HPRT + // Position of PRTCONNSTS field. + USB_HPRT_PRTCONNSTS_Pos = 0x0 + // Bit mask of PRTCONNSTS field. + USB_HPRT_PRTCONNSTS_Msk = 0x1 + // Bit PRTCONNSTS. + USB_HPRT_PRTCONNSTS = 0x1 + // Position of PRTCONNDET field. + USB_HPRT_PRTCONNDET_Pos = 0x1 + // Bit mask of PRTCONNDET field. + USB_HPRT_PRTCONNDET_Msk = 0x2 + // Bit PRTCONNDET. + USB_HPRT_PRTCONNDET = 0x2 + // Position of PRTENA field. + USB_HPRT_PRTENA_Pos = 0x2 + // Bit mask of PRTENA field. + USB_HPRT_PRTENA_Msk = 0x4 + // Bit PRTENA. + USB_HPRT_PRTENA = 0x4 + // Position of PRTENCHNG field. + USB_HPRT_PRTENCHNG_Pos = 0x3 + // Bit mask of PRTENCHNG field. + USB_HPRT_PRTENCHNG_Msk = 0x8 + // Bit PRTENCHNG. + USB_HPRT_PRTENCHNG = 0x8 + // Position of PRTOVRCURRACT field. + USB_HPRT_PRTOVRCURRACT_Pos = 0x4 + // Bit mask of PRTOVRCURRACT field. + USB_HPRT_PRTOVRCURRACT_Msk = 0x10 + // Bit PRTOVRCURRACT. + USB_HPRT_PRTOVRCURRACT = 0x10 + // Position of PRTOVRCURRCHNG field. + USB_HPRT_PRTOVRCURRCHNG_Pos = 0x5 + // Bit mask of PRTOVRCURRCHNG field. + USB_HPRT_PRTOVRCURRCHNG_Msk = 0x20 + // Bit PRTOVRCURRCHNG. + USB_HPRT_PRTOVRCURRCHNG = 0x20 + // Position of PRTRES field. + USB_HPRT_PRTRES_Pos = 0x6 + // Bit mask of PRTRES field. + USB_HPRT_PRTRES_Msk = 0x40 + // Bit PRTRES. + USB_HPRT_PRTRES = 0x40 + // Position of PRTSUSP field. + USB_HPRT_PRTSUSP_Pos = 0x7 + // Bit mask of PRTSUSP field. + USB_HPRT_PRTSUSP_Msk = 0x80 + // Bit PRTSUSP. + USB_HPRT_PRTSUSP = 0x80 + // Position of PRTRST field. + USB_HPRT_PRTRST_Pos = 0x8 + // Bit mask of PRTRST field. + USB_HPRT_PRTRST_Msk = 0x100 + // Bit PRTRST. + USB_HPRT_PRTRST = 0x100 + // Position of PRTLNSTS field. + USB_HPRT_PRTLNSTS_Pos = 0xa + // Bit mask of PRTLNSTS field. + USB_HPRT_PRTLNSTS_Msk = 0xc00 + // Position of PRTPWR field. + USB_HPRT_PRTPWR_Pos = 0xc + // Bit mask of PRTPWR field. + USB_HPRT_PRTPWR_Msk = 0x1000 + // Bit PRTPWR. + USB_HPRT_PRTPWR = 0x1000 + // Position of PRTTSTCTL field. + USB_HPRT_PRTTSTCTL_Pos = 0xd + // Bit mask of PRTTSTCTL field. + USB_HPRT_PRTTSTCTL_Msk = 0x1e000 + // Position of PRTSPD field. + USB_HPRT_PRTSPD_Pos = 0x11 + // Bit mask of PRTSPD field. + USB_HPRT_PRTSPD_Msk = 0x60000 + + // HCCHAR0 + // Position of H_MPS0 field. + USB_HCCHAR0_H_MPS0_Pos = 0x0 + // Bit mask of H_MPS0 field. + USB_HCCHAR0_H_MPS0_Msk = 0x7ff + // Position of H_EPNUM0 field. + USB_HCCHAR0_H_EPNUM0_Pos = 0xb + // Bit mask of H_EPNUM0 field. + USB_HCCHAR0_H_EPNUM0_Msk = 0x7800 + // Position of H_EPDIR0 field. + USB_HCCHAR0_H_EPDIR0_Pos = 0xf + // Bit mask of H_EPDIR0 field. + USB_HCCHAR0_H_EPDIR0_Msk = 0x8000 + // Bit H_EPDIR0. + USB_HCCHAR0_H_EPDIR0 = 0x8000 + // Position of H_LSPDDEV0 field. + USB_HCCHAR0_H_LSPDDEV0_Pos = 0x11 + // Bit mask of H_LSPDDEV0 field. + USB_HCCHAR0_H_LSPDDEV0_Msk = 0x20000 + // Bit H_LSPDDEV0. + USB_HCCHAR0_H_LSPDDEV0 = 0x20000 + // Position of H_EPTYPE0 field. + USB_HCCHAR0_H_EPTYPE0_Pos = 0x12 + // Bit mask of H_EPTYPE0 field. + USB_HCCHAR0_H_EPTYPE0_Msk = 0xc0000 + // Position of H_EC0 field. + USB_HCCHAR0_H_EC0_Pos = 0x15 + // Bit mask of H_EC0 field. + USB_HCCHAR0_H_EC0_Msk = 0x200000 + // Bit H_EC0. + USB_HCCHAR0_H_EC0 = 0x200000 + // Position of H_DEVADDR0 field. + USB_HCCHAR0_H_DEVADDR0_Pos = 0x16 + // Bit mask of H_DEVADDR0 field. + USB_HCCHAR0_H_DEVADDR0_Msk = 0x1fc00000 + // Position of H_ODDFRM0 field. + USB_HCCHAR0_H_ODDFRM0_Pos = 0x1d + // Bit mask of H_ODDFRM0 field. + USB_HCCHAR0_H_ODDFRM0_Msk = 0x20000000 + // Bit H_ODDFRM0. + USB_HCCHAR0_H_ODDFRM0 = 0x20000000 + // Position of H_CHDIS0 field. + USB_HCCHAR0_H_CHDIS0_Pos = 0x1e + // Bit mask of H_CHDIS0 field. + USB_HCCHAR0_H_CHDIS0_Msk = 0x40000000 + // Bit H_CHDIS0. + USB_HCCHAR0_H_CHDIS0 = 0x40000000 + // Position of H_CHENA0 field. + USB_HCCHAR0_H_CHENA0_Pos = 0x1f + // Bit mask of H_CHENA0 field. + USB_HCCHAR0_H_CHENA0_Msk = 0x80000000 + // Bit H_CHENA0. + USB_HCCHAR0_H_CHENA0 = 0x80000000 + + // HCINT0 + // Position of H_XFERCOMPL0 field. + USB_HCINT0_H_XFERCOMPL0_Pos = 0x0 + // Bit mask of H_XFERCOMPL0 field. + USB_HCINT0_H_XFERCOMPL0_Msk = 0x1 + // Bit H_XFERCOMPL0. + USB_HCINT0_H_XFERCOMPL0 = 0x1 + // Position of H_CHHLTD0 field. + USB_HCINT0_H_CHHLTD0_Pos = 0x1 + // Bit mask of H_CHHLTD0 field. + USB_HCINT0_H_CHHLTD0_Msk = 0x2 + // Bit H_CHHLTD0. + USB_HCINT0_H_CHHLTD0 = 0x2 + // Position of H_AHBERR0 field. + USB_HCINT0_H_AHBERR0_Pos = 0x2 + // Bit mask of H_AHBERR0 field. + USB_HCINT0_H_AHBERR0_Msk = 0x4 + // Bit H_AHBERR0. + USB_HCINT0_H_AHBERR0 = 0x4 + // Position of H_STALL0 field. + USB_HCINT0_H_STALL0_Pos = 0x3 + // Bit mask of H_STALL0 field. + USB_HCINT0_H_STALL0_Msk = 0x8 + // Bit H_STALL0. + USB_HCINT0_H_STALL0 = 0x8 + // Position of H_NACK0 field. + USB_HCINT0_H_NACK0_Pos = 0x4 + // Bit mask of H_NACK0 field. + USB_HCINT0_H_NACK0_Msk = 0x10 + // Bit H_NACK0. + USB_HCINT0_H_NACK0 = 0x10 + // Position of H_ACK0 field. + USB_HCINT0_H_ACK0_Pos = 0x5 + // Bit mask of H_ACK0 field. + USB_HCINT0_H_ACK0_Msk = 0x20 + // Bit H_ACK0. + USB_HCINT0_H_ACK0 = 0x20 + // Position of H_NYET0 field. + USB_HCINT0_H_NYET0_Pos = 0x6 + // Bit mask of H_NYET0 field. + USB_HCINT0_H_NYET0_Msk = 0x40 + // Bit H_NYET0. + USB_HCINT0_H_NYET0 = 0x40 + // Position of H_XACTERR0 field. + USB_HCINT0_H_XACTERR0_Pos = 0x7 + // Bit mask of H_XACTERR0 field. + USB_HCINT0_H_XACTERR0_Msk = 0x80 + // Bit H_XACTERR0. + USB_HCINT0_H_XACTERR0 = 0x80 + // Position of H_BBLERR0 field. + USB_HCINT0_H_BBLERR0_Pos = 0x8 + // Bit mask of H_BBLERR0 field. + USB_HCINT0_H_BBLERR0_Msk = 0x100 + // Bit H_BBLERR0. + USB_HCINT0_H_BBLERR0 = 0x100 + // Position of H_FRMOVRUN0 field. + USB_HCINT0_H_FRMOVRUN0_Pos = 0x9 + // Bit mask of H_FRMOVRUN0 field. + USB_HCINT0_H_FRMOVRUN0_Msk = 0x200 + // Bit H_FRMOVRUN0. + USB_HCINT0_H_FRMOVRUN0 = 0x200 + // Position of H_DATATGLERR0 field. + USB_HCINT0_H_DATATGLERR0_Pos = 0xa + // Bit mask of H_DATATGLERR0 field. + USB_HCINT0_H_DATATGLERR0_Msk = 0x400 + // Bit H_DATATGLERR0. + USB_HCINT0_H_DATATGLERR0 = 0x400 + // Position of H_BNAINTR0 field. + USB_HCINT0_H_BNAINTR0_Pos = 0xb + // Bit mask of H_BNAINTR0 field. + USB_HCINT0_H_BNAINTR0_Msk = 0x800 + // Bit H_BNAINTR0. + USB_HCINT0_H_BNAINTR0 = 0x800 + // Position of H_XCS_XACT_ERR0 field. + USB_HCINT0_H_XCS_XACT_ERR0_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR0 field. + USB_HCINT0_H_XCS_XACT_ERR0_Msk = 0x1000 + // Bit H_XCS_XACT_ERR0. + USB_HCINT0_H_XCS_XACT_ERR0 = 0x1000 + // Position of H_DESC_LST_ROLLINTR0 field. + USB_HCINT0_H_DESC_LST_ROLLINTR0_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR0 field. + USB_HCINT0_H_DESC_LST_ROLLINTR0_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR0. + USB_HCINT0_H_DESC_LST_ROLLINTR0 = 0x2000 + + // HCINTMSK0 + // Position of H_XFERCOMPLMSK0 field. + USB_HCINTMSK0_H_XFERCOMPLMSK0_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK0 field. + USB_HCINTMSK0_H_XFERCOMPLMSK0_Msk = 0x1 + // Bit H_XFERCOMPLMSK0. + USB_HCINTMSK0_H_XFERCOMPLMSK0 = 0x1 + // Position of H_CHHLTDMSK0 field. + USB_HCINTMSK0_H_CHHLTDMSK0_Pos = 0x1 + // Bit mask of H_CHHLTDMSK0 field. + USB_HCINTMSK0_H_CHHLTDMSK0_Msk = 0x2 + // Bit H_CHHLTDMSK0. + USB_HCINTMSK0_H_CHHLTDMSK0 = 0x2 + // Position of H_AHBERRMSK0 field. + USB_HCINTMSK0_H_AHBERRMSK0_Pos = 0x2 + // Bit mask of H_AHBERRMSK0 field. + USB_HCINTMSK0_H_AHBERRMSK0_Msk = 0x4 + // Bit H_AHBERRMSK0. + USB_HCINTMSK0_H_AHBERRMSK0 = 0x4 + // Position of H_STALLMSK0 field. + USB_HCINTMSK0_H_STALLMSK0_Pos = 0x3 + // Bit mask of H_STALLMSK0 field. + USB_HCINTMSK0_H_STALLMSK0_Msk = 0x8 + // Bit H_STALLMSK0. + USB_HCINTMSK0_H_STALLMSK0 = 0x8 + // Position of H_NAKMSK0 field. + USB_HCINTMSK0_H_NAKMSK0_Pos = 0x4 + // Bit mask of H_NAKMSK0 field. + USB_HCINTMSK0_H_NAKMSK0_Msk = 0x10 + // Bit H_NAKMSK0. + USB_HCINTMSK0_H_NAKMSK0 = 0x10 + // Position of H_ACKMSK0 field. + USB_HCINTMSK0_H_ACKMSK0_Pos = 0x5 + // Bit mask of H_ACKMSK0 field. + USB_HCINTMSK0_H_ACKMSK0_Msk = 0x20 + // Bit H_ACKMSK0. + USB_HCINTMSK0_H_ACKMSK0 = 0x20 + // Position of H_NYETMSK0 field. + USB_HCINTMSK0_H_NYETMSK0_Pos = 0x6 + // Bit mask of H_NYETMSK0 field. + USB_HCINTMSK0_H_NYETMSK0_Msk = 0x40 + // Bit H_NYETMSK0. + USB_HCINTMSK0_H_NYETMSK0 = 0x40 + // Position of H_XACTERRMSK0 field. + USB_HCINTMSK0_H_XACTERRMSK0_Pos = 0x7 + // Bit mask of H_XACTERRMSK0 field. + USB_HCINTMSK0_H_XACTERRMSK0_Msk = 0x80 + // Bit H_XACTERRMSK0. + USB_HCINTMSK0_H_XACTERRMSK0 = 0x80 + // Position of H_BBLERRMSK0 field. + USB_HCINTMSK0_H_BBLERRMSK0_Pos = 0x8 + // Bit mask of H_BBLERRMSK0 field. + USB_HCINTMSK0_H_BBLERRMSK0_Msk = 0x100 + // Bit H_BBLERRMSK0. + USB_HCINTMSK0_H_BBLERRMSK0 = 0x100 + // Position of H_FRMOVRUNMSK0 field. + USB_HCINTMSK0_H_FRMOVRUNMSK0_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK0 field. + USB_HCINTMSK0_H_FRMOVRUNMSK0_Msk = 0x200 + // Bit H_FRMOVRUNMSK0. + USB_HCINTMSK0_H_FRMOVRUNMSK0 = 0x200 + // Position of H_DATATGLERRMSK0 field. + USB_HCINTMSK0_H_DATATGLERRMSK0_Pos = 0xa + // Bit mask of H_DATATGLERRMSK0 field. + USB_HCINTMSK0_H_DATATGLERRMSK0_Msk = 0x400 + // Bit H_DATATGLERRMSK0. + USB_HCINTMSK0_H_DATATGLERRMSK0 = 0x400 + // Position of H_BNAINTRMSK0 field. + USB_HCINTMSK0_H_BNAINTRMSK0_Pos = 0xb + // Bit mask of H_BNAINTRMSK0 field. + USB_HCINTMSK0_H_BNAINTRMSK0_Msk = 0x800 + // Bit H_BNAINTRMSK0. + USB_HCINTMSK0_H_BNAINTRMSK0 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK0 field. + USB_HCINTMSK0_H_DESC_LST_ROLLINTRMSK0_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK0 field. + USB_HCINTMSK0_H_DESC_LST_ROLLINTRMSK0_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK0. + USB_HCINTMSK0_H_DESC_LST_ROLLINTRMSK0 = 0x2000 + + // HCTSIZ0 + // Position of H_XFERSIZE0 field. + USB_HCTSIZ0_H_XFERSIZE0_Pos = 0x0 + // Bit mask of H_XFERSIZE0 field. + USB_HCTSIZ0_H_XFERSIZE0_Msk = 0x7ffff + // Position of H_PKTCNT0 field. + USB_HCTSIZ0_H_PKTCNT0_Pos = 0x13 + // Bit mask of H_PKTCNT0 field. + USB_HCTSIZ0_H_PKTCNT0_Msk = 0x1ff80000 + // Position of H_PID0 field. + USB_HCTSIZ0_H_PID0_Pos = 0x1d + // Bit mask of H_PID0 field. + USB_HCTSIZ0_H_PID0_Msk = 0x60000000 + // Position of H_DOPNG0 field. + USB_HCTSIZ0_H_DOPNG0_Pos = 0x1f + // Bit mask of H_DOPNG0 field. + USB_HCTSIZ0_H_DOPNG0_Msk = 0x80000000 + // Bit H_DOPNG0. + USB_HCTSIZ0_H_DOPNG0 = 0x80000000 + + // HCDMA0 + // Position of H_DMAADDR0 field. + USB_HCDMA0_H_DMAADDR0_Pos = 0x0 + // Bit mask of H_DMAADDR0 field. + USB_HCDMA0_H_DMAADDR0_Msk = 0xffffffff + + // HCDMAB0 + // Position of H_HCDMAB0 field. + USB_HCDMAB0_H_HCDMAB0_Pos = 0x0 + // Bit mask of H_HCDMAB0 field. + USB_HCDMAB0_H_HCDMAB0_Msk = 0xffffffff + + // HCCHAR1 + // Position of H_MPS1 field. + USB_HCCHAR1_H_MPS1_Pos = 0x0 + // Bit mask of H_MPS1 field. + USB_HCCHAR1_H_MPS1_Msk = 0x7ff + // Position of H_EPNUM1 field. + USB_HCCHAR1_H_EPNUM1_Pos = 0xb + // Bit mask of H_EPNUM1 field. + USB_HCCHAR1_H_EPNUM1_Msk = 0x7800 + // Position of H_EPDIR1 field. + USB_HCCHAR1_H_EPDIR1_Pos = 0xf + // Bit mask of H_EPDIR1 field. + USB_HCCHAR1_H_EPDIR1_Msk = 0x8000 + // Bit H_EPDIR1. + USB_HCCHAR1_H_EPDIR1 = 0x8000 + // Position of H_LSPDDEV1 field. + USB_HCCHAR1_H_LSPDDEV1_Pos = 0x11 + // Bit mask of H_LSPDDEV1 field. + USB_HCCHAR1_H_LSPDDEV1_Msk = 0x20000 + // Bit H_LSPDDEV1. + USB_HCCHAR1_H_LSPDDEV1 = 0x20000 + // Position of H_EPTYPE1 field. + USB_HCCHAR1_H_EPTYPE1_Pos = 0x12 + // Bit mask of H_EPTYPE1 field. + USB_HCCHAR1_H_EPTYPE1_Msk = 0xc0000 + // Position of H_EC1 field. + USB_HCCHAR1_H_EC1_Pos = 0x15 + // Bit mask of H_EC1 field. + USB_HCCHAR1_H_EC1_Msk = 0x200000 + // Bit H_EC1. + USB_HCCHAR1_H_EC1 = 0x200000 + // Position of H_DEVADDR1 field. + USB_HCCHAR1_H_DEVADDR1_Pos = 0x16 + // Bit mask of H_DEVADDR1 field. + USB_HCCHAR1_H_DEVADDR1_Msk = 0x1fc00000 + // Position of H_ODDFRM1 field. + USB_HCCHAR1_H_ODDFRM1_Pos = 0x1d + // Bit mask of H_ODDFRM1 field. + USB_HCCHAR1_H_ODDFRM1_Msk = 0x20000000 + // Bit H_ODDFRM1. + USB_HCCHAR1_H_ODDFRM1 = 0x20000000 + // Position of H_CHDIS1 field. + USB_HCCHAR1_H_CHDIS1_Pos = 0x1e + // Bit mask of H_CHDIS1 field. + USB_HCCHAR1_H_CHDIS1_Msk = 0x40000000 + // Bit H_CHDIS1. + USB_HCCHAR1_H_CHDIS1 = 0x40000000 + // Position of H_CHENA1 field. + USB_HCCHAR1_H_CHENA1_Pos = 0x1f + // Bit mask of H_CHENA1 field. + USB_HCCHAR1_H_CHENA1_Msk = 0x80000000 + // Bit H_CHENA1. + USB_HCCHAR1_H_CHENA1 = 0x80000000 + + // HCINT1 + // Position of H_XFERCOMPL1 field. + USB_HCINT1_H_XFERCOMPL1_Pos = 0x0 + // Bit mask of H_XFERCOMPL1 field. + USB_HCINT1_H_XFERCOMPL1_Msk = 0x1 + // Bit H_XFERCOMPL1. + USB_HCINT1_H_XFERCOMPL1 = 0x1 + // Position of H_CHHLTD1 field. + USB_HCINT1_H_CHHLTD1_Pos = 0x1 + // Bit mask of H_CHHLTD1 field. + USB_HCINT1_H_CHHLTD1_Msk = 0x2 + // Bit H_CHHLTD1. + USB_HCINT1_H_CHHLTD1 = 0x2 + // Position of H_AHBERR1 field. + USB_HCINT1_H_AHBERR1_Pos = 0x2 + // Bit mask of H_AHBERR1 field. + USB_HCINT1_H_AHBERR1_Msk = 0x4 + // Bit H_AHBERR1. + USB_HCINT1_H_AHBERR1 = 0x4 + // Position of H_STALL1 field. + USB_HCINT1_H_STALL1_Pos = 0x3 + // Bit mask of H_STALL1 field. + USB_HCINT1_H_STALL1_Msk = 0x8 + // Bit H_STALL1. + USB_HCINT1_H_STALL1 = 0x8 + // Position of H_NACK1 field. + USB_HCINT1_H_NACK1_Pos = 0x4 + // Bit mask of H_NACK1 field. + USB_HCINT1_H_NACK1_Msk = 0x10 + // Bit H_NACK1. + USB_HCINT1_H_NACK1 = 0x10 + // Position of H_ACK1 field. + USB_HCINT1_H_ACK1_Pos = 0x5 + // Bit mask of H_ACK1 field. + USB_HCINT1_H_ACK1_Msk = 0x20 + // Bit H_ACK1. + USB_HCINT1_H_ACK1 = 0x20 + // Position of H_NYET1 field. + USB_HCINT1_H_NYET1_Pos = 0x6 + // Bit mask of H_NYET1 field. + USB_HCINT1_H_NYET1_Msk = 0x40 + // Bit H_NYET1. + USB_HCINT1_H_NYET1 = 0x40 + // Position of H_XACTERR1 field. + USB_HCINT1_H_XACTERR1_Pos = 0x7 + // Bit mask of H_XACTERR1 field. + USB_HCINT1_H_XACTERR1_Msk = 0x80 + // Bit H_XACTERR1. + USB_HCINT1_H_XACTERR1 = 0x80 + // Position of H_BBLERR1 field. + USB_HCINT1_H_BBLERR1_Pos = 0x8 + // Bit mask of H_BBLERR1 field. + USB_HCINT1_H_BBLERR1_Msk = 0x100 + // Bit H_BBLERR1. + USB_HCINT1_H_BBLERR1 = 0x100 + // Position of H_FRMOVRUN1 field. + USB_HCINT1_H_FRMOVRUN1_Pos = 0x9 + // Bit mask of H_FRMOVRUN1 field. + USB_HCINT1_H_FRMOVRUN1_Msk = 0x200 + // Bit H_FRMOVRUN1. + USB_HCINT1_H_FRMOVRUN1 = 0x200 + // Position of H_DATATGLERR1 field. + USB_HCINT1_H_DATATGLERR1_Pos = 0xa + // Bit mask of H_DATATGLERR1 field. + USB_HCINT1_H_DATATGLERR1_Msk = 0x400 + // Bit H_DATATGLERR1. + USB_HCINT1_H_DATATGLERR1 = 0x400 + // Position of H_BNAINTR1 field. + USB_HCINT1_H_BNAINTR1_Pos = 0xb + // Bit mask of H_BNAINTR1 field. + USB_HCINT1_H_BNAINTR1_Msk = 0x800 + // Bit H_BNAINTR1. + USB_HCINT1_H_BNAINTR1 = 0x800 + // Position of H_XCS_XACT_ERR1 field. + USB_HCINT1_H_XCS_XACT_ERR1_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR1 field. + USB_HCINT1_H_XCS_XACT_ERR1_Msk = 0x1000 + // Bit H_XCS_XACT_ERR1. + USB_HCINT1_H_XCS_XACT_ERR1 = 0x1000 + // Position of H_DESC_LST_ROLLINTR1 field. + USB_HCINT1_H_DESC_LST_ROLLINTR1_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR1 field. + USB_HCINT1_H_DESC_LST_ROLLINTR1_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR1. + USB_HCINT1_H_DESC_LST_ROLLINTR1 = 0x2000 + + // HCINTMSK1 + // Position of H_XFERCOMPLMSK1 field. + USB_HCINTMSK1_H_XFERCOMPLMSK1_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK1 field. + USB_HCINTMSK1_H_XFERCOMPLMSK1_Msk = 0x1 + // Bit H_XFERCOMPLMSK1. + USB_HCINTMSK1_H_XFERCOMPLMSK1 = 0x1 + // Position of H_CHHLTDMSK1 field. + USB_HCINTMSK1_H_CHHLTDMSK1_Pos = 0x1 + // Bit mask of H_CHHLTDMSK1 field. + USB_HCINTMSK1_H_CHHLTDMSK1_Msk = 0x2 + // Bit H_CHHLTDMSK1. + USB_HCINTMSK1_H_CHHLTDMSK1 = 0x2 + // Position of H_AHBERRMSK1 field. + USB_HCINTMSK1_H_AHBERRMSK1_Pos = 0x2 + // Bit mask of H_AHBERRMSK1 field. + USB_HCINTMSK1_H_AHBERRMSK1_Msk = 0x4 + // Bit H_AHBERRMSK1. + USB_HCINTMSK1_H_AHBERRMSK1 = 0x4 + // Position of H_STALLMSK1 field. + USB_HCINTMSK1_H_STALLMSK1_Pos = 0x3 + // Bit mask of H_STALLMSK1 field. + USB_HCINTMSK1_H_STALLMSK1_Msk = 0x8 + // Bit H_STALLMSK1. + USB_HCINTMSK1_H_STALLMSK1 = 0x8 + // Position of H_NAKMSK1 field. + USB_HCINTMSK1_H_NAKMSK1_Pos = 0x4 + // Bit mask of H_NAKMSK1 field. + USB_HCINTMSK1_H_NAKMSK1_Msk = 0x10 + // Bit H_NAKMSK1. + USB_HCINTMSK1_H_NAKMSK1 = 0x10 + // Position of H_ACKMSK1 field. + USB_HCINTMSK1_H_ACKMSK1_Pos = 0x5 + // Bit mask of H_ACKMSK1 field. + USB_HCINTMSK1_H_ACKMSK1_Msk = 0x20 + // Bit H_ACKMSK1. + USB_HCINTMSK1_H_ACKMSK1 = 0x20 + // Position of H_NYETMSK1 field. + USB_HCINTMSK1_H_NYETMSK1_Pos = 0x6 + // Bit mask of H_NYETMSK1 field. + USB_HCINTMSK1_H_NYETMSK1_Msk = 0x40 + // Bit H_NYETMSK1. + USB_HCINTMSK1_H_NYETMSK1 = 0x40 + // Position of H_XACTERRMSK1 field. + USB_HCINTMSK1_H_XACTERRMSK1_Pos = 0x7 + // Bit mask of H_XACTERRMSK1 field. + USB_HCINTMSK1_H_XACTERRMSK1_Msk = 0x80 + // Bit H_XACTERRMSK1. + USB_HCINTMSK1_H_XACTERRMSK1 = 0x80 + // Position of H_BBLERRMSK1 field. + USB_HCINTMSK1_H_BBLERRMSK1_Pos = 0x8 + // Bit mask of H_BBLERRMSK1 field. + USB_HCINTMSK1_H_BBLERRMSK1_Msk = 0x100 + // Bit H_BBLERRMSK1. + USB_HCINTMSK1_H_BBLERRMSK1 = 0x100 + // Position of H_FRMOVRUNMSK1 field. + USB_HCINTMSK1_H_FRMOVRUNMSK1_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK1 field. + USB_HCINTMSK1_H_FRMOVRUNMSK1_Msk = 0x200 + // Bit H_FRMOVRUNMSK1. + USB_HCINTMSK1_H_FRMOVRUNMSK1 = 0x200 + // Position of H_DATATGLERRMSK1 field. + USB_HCINTMSK1_H_DATATGLERRMSK1_Pos = 0xa + // Bit mask of H_DATATGLERRMSK1 field. + USB_HCINTMSK1_H_DATATGLERRMSK1_Msk = 0x400 + // Bit H_DATATGLERRMSK1. + USB_HCINTMSK1_H_DATATGLERRMSK1 = 0x400 + // Position of H_BNAINTRMSK1 field. + USB_HCINTMSK1_H_BNAINTRMSK1_Pos = 0xb + // Bit mask of H_BNAINTRMSK1 field. + USB_HCINTMSK1_H_BNAINTRMSK1_Msk = 0x800 + // Bit H_BNAINTRMSK1. + USB_HCINTMSK1_H_BNAINTRMSK1 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK1 field. + USB_HCINTMSK1_H_DESC_LST_ROLLINTRMSK1_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK1 field. + USB_HCINTMSK1_H_DESC_LST_ROLLINTRMSK1_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK1. + USB_HCINTMSK1_H_DESC_LST_ROLLINTRMSK1 = 0x2000 + + // HCTSIZ1 + // Position of H_XFERSIZE1 field. + USB_HCTSIZ1_H_XFERSIZE1_Pos = 0x0 + // Bit mask of H_XFERSIZE1 field. + USB_HCTSIZ1_H_XFERSIZE1_Msk = 0x7ffff + // Position of H_PKTCNT1 field. + USB_HCTSIZ1_H_PKTCNT1_Pos = 0x13 + // Bit mask of H_PKTCNT1 field. + USB_HCTSIZ1_H_PKTCNT1_Msk = 0x1ff80000 + // Position of H_PID1 field. + USB_HCTSIZ1_H_PID1_Pos = 0x1d + // Bit mask of H_PID1 field. + USB_HCTSIZ1_H_PID1_Msk = 0x60000000 + // Position of H_DOPNG1 field. + USB_HCTSIZ1_H_DOPNG1_Pos = 0x1f + // Bit mask of H_DOPNG1 field. + USB_HCTSIZ1_H_DOPNG1_Msk = 0x80000000 + // Bit H_DOPNG1. + USB_HCTSIZ1_H_DOPNG1 = 0x80000000 + + // HCDMA1 + // Position of H_DMAADDR1 field. + USB_HCDMA1_H_DMAADDR1_Pos = 0x0 + // Bit mask of H_DMAADDR1 field. + USB_HCDMA1_H_DMAADDR1_Msk = 0xffffffff + + // HCDMAB1 + // Position of H_HCDMAB1 field. + USB_HCDMAB1_H_HCDMAB1_Pos = 0x0 + // Bit mask of H_HCDMAB1 field. + USB_HCDMAB1_H_HCDMAB1_Msk = 0xffffffff + + // HCCHAR2 + // Position of H_MPS2 field. + USB_HCCHAR2_H_MPS2_Pos = 0x0 + // Bit mask of H_MPS2 field. + USB_HCCHAR2_H_MPS2_Msk = 0x7ff + // Position of H_EPNUM2 field. + USB_HCCHAR2_H_EPNUM2_Pos = 0xb + // Bit mask of H_EPNUM2 field. + USB_HCCHAR2_H_EPNUM2_Msk = 0x7800 + // Position of H_EPDIR2 field. + USB_HCCHAR2_H_EPDIR2_Pos = 0xf + // Bit mask of H_EPDIR2 field. + USB_HCCHAR2_H_EPDIR2_Msk = 0x8000 + // Bit H_EPDIR2. + USB_HCCHAR2_H_EPDIR2 = 0x8000 + // Position of H_LSPDDEV2 field. + USB_HCCHAR2_H_LSPDDEV2_Pos = 0x11 + // Bit mask of H_LSPDDEV2 field. + USB_HCCHAR2_H_LSPDDEV2_Msk = 0x20000 + // Bit H_LSPDDEV2. + USB_HCCHAR2_H_LSPDDEV2 = 0x20000 + // Position of H_EPTYPE2 field. + USB_HCCHAR2_H_EPTYPE2_Pos = 0x12 + // Bit mask of H_EPTYPE2 field. + USB_HCCHAR2_H_EPTYPE2_Msk = 0xc0000 + // Position of H_EC2 field. + USB_HCCHAR2_H_EC2_Pos = 0x15 + // Bit mask of H_EC2 field. + USB_HCCHAR2_H_EC2_Msk = 0x200000 + // Bit H_EC2. + USB_HCCHAR2_H_EC2 = 0x200000 + // Position of H_DEVADDR2 field. + USB_HCCHAR2_H_DEVADDR2_Pos = 0x16 + // Bit mask of H_DEVADDR2 field. + USB_HCCHAR2_H_DEVADDR2_Msk = 0x1fc00000 + // Position of H_ODDFRM2 field. + USB_HCCHAR2_H_ODDFRM2_Pos = 0x1d + // Bit mask of H_ODDFRM2 field. + USB_HCCHAR2_H_ODDFRM2_Msk = 0x20000000 + // Bit H_ODDFRM2. + USB_HCCHAR2_H_ODDFRM2 = 0x20000000 + // Position of H_CHDIS2 field. + USB_HCCHAR2_H_CHDIS2_Pos = 0x1e + // Bit mask of H_CHDIS2 field. + USB_HCCHAR2_H_CHDIS2_Msk = 0x40000000 + // Bit H_CHDIS2. + USB_HCCHAR2_H_CHDIS2 = 0x40000000 + // Position of H_CHENA2 field. + USB_HCCHAR2_H_CHENA2_Pos = 0x1f + // Bit mask of H_CHENA2 field. + USB_HCCHAR2_H_CHENA2_Msk = 0x80000000 + // Bit H_CHENA2. + USB_HCCHAR2_H_CHENA2 = 0x80000000 + + // HCINT2 + // Position of H_XFERCOMPL2 field. + USB_HCINT2_H_XFERCOMPL2_Pos = 0x0 + // Bit mask of H_XFERCOMPL2 field. + USB_HCINT2_H_XFERCOMPL2_Msk = 0x1 + // Bit H_XFERCOMPL2. + USB_HCINT2_H_XFERCOMPL2 = 0x1 + // Position of H_CHHLTD2 field. + USB_HCINT2_H_CHHLTD2_Pos = 0x1 + // Bit mask of H_CHHLTD2 field. + USB_HCINT2_H_CHHLTD2_Msk = 0x2 + // Bit H_CHHLTD2. + USB_HCINT2_H_CHHLTD2 = 0x2 + // Position of H_AHBERR2 field. + USB_HCINT2_H_AHBERR2_Pos = 0x2 + // Bit mask of H_AHBERR2 field. + USB_HCINT2_H_AHBERR2_Msk = 0x4 + // Bit H_AHBERR2. + USB_HCINT2_H_AHBERR2 = 0x4 + // Position of H_STALL2 field. + USB_HCINT2_H_STALL2_Pos = 0x3 + // Bit mask of H_STALL2 field. + USB_HCINT2_H_STALL2_Msk = 0x8 + // Bit H_STALL2. + USB_HCINT2_H_STALL2 = 0x8 + // Position of H_NACK2 field. + USB_HCINT2_H_NACK2_Pos = 0x4 + // Bit mask of H_NACK2 field. + USB_HCINT2_H_NACK2_Msk = 0x10 + // Bit H_NACK2. + USB_HCINT2_H_NACK2 = 0x10 + // Position of H_ACK2 field. + USB_HCINT2_H_ACK2_Pos = 0x5 + // Bit mask of H_ACK2 field. + USB_HCINT2_H_ACK2_Msk = 0x20 + // Bit H_ACK2. + USB_HCINT2_H_ACK2 = 0x20 + // Position of H_NYET2 field. + USB_HCINT2_H_NYET2_Pos = 0x6 + // Bit mask of H_NYET2 field. + USB_HCINT2_H_NYET2_Msk = 0x40 + // Bit H_NYET2. + USB_HCINT2_H_NYET2 = 0x40 + // Position of H_XACTERR2 field. + USB_HCINT2_H_XACTERR2_Pos = 0x7 + // Bit mask of H_XACTERR2 field. + USB_HCINT2_H_XACTERR2_Msk = 0x80 + // Bit H_XACTERR2. + USB_HCINT2_H_XACTERR2 = 0x80 + // Position of H_BBLERR2 field. + USB_HCINT2_H_BBLERR2_Pos = 0x8 + // Bit mask of H_BBLERR2 field. + USB_HCINT2_H_BBLERR2_Msk = 0x100 + // Bit H_BBLERR2. + USB_HCINT2_H_BBLERR2 = 0x100 + // Position of H_FRMOVRUN2 field. + USB_HCINT2_H_FRMOVRUN2_Pos = 0x9 + // Bit mask of H_FRMOVRUN2 field. + USB_HCINT2_H_FRMOVRUN2_Msk = 0x200 + // Bit H_FRMOVRUN2. + USB_HCINT2_H_FRMOVRUN2 = 0x200 + // Position of H_DATATGLERR2 field. + USB_HCINT2_H_DATATGLERR2_Pos = 0xa + // Bit mask of H_DATATGLERR2 field. + USB_HCINT2_H_DATATGLERR2_Msk = 0x400 + // Bit H_DATATGLERR2. + USB_HCINT2_H_DATATGLERR2 = 0x400 + // Position of H_BNAINTR2 field. + USB_HCINT2_H_BNAINTR2_Pos = 0xb + // Bit mask of H_BNAINTR2 field. + USB_HCINT2_H_BNAINTR2_Msk = 0x800 + // Bit H_BNAINTR2. + USB_HCINT2_H_BNAINTR2 = 0x800 + // Position of H_XCS_XACT_ERR2 field. + USB_HCINT2_H_XCS_XACT_ERR2_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR2 field. + USB_HCINT2_H_XCS_XACT_ERR2_Msk = 0x1000 + // Bit H_XCS_XACT_ERR2. + USB_HCINT2_H_XCS_XACT_ERR2 = 0x1000 + // Position of H_DESC_LST_ROLLINTR2 field. + USB_HCINT2_H_DESC_LST_ROLLINTR2_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR2 field. + USB_HCINT2_H_DESC_LST_ROLLINTR2_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR2. + USB_HCINT2_H_DESC_LST_ROLLINTR2 = 0x2000 + + // HCINTMSK2 + // Position of H_XFERCOMPLMSK2 field. + USB_HCINTMSK2_H_XFERCOMPLMSK2_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK2 field. + USB_HCINTMSK2_H_XFERCOMPLMSK2_Msk = 0x1 + // Bit H_XFERCOMPLMSK2. + USB_HCINTMSK2_H_XFERCOMPLMSK2 = 0x1 + // Position of H_CHHLTDMSK2 field. + USB_HCINTMSK2_H_CHHLTDMSK2_Pos = 0x1 + // Bit mask of H_CHHLTDMSK2 field. + USB_HCINTMSK2_H_CHHLTDMSK2_Msk = 0x2 + // Bit H_CHHLTDMSK2. + USB_HCINTMSK2_H_CHHLTDMSK2 = 0x2 + // Position of H_AHBERRMSK2 field. + USB_HCINTMSK2_H_AHBERRMSK2_Pos = 0x2 + // Bit mask of H_AHBERRMSK2 field. + USB_HCINTMSK2_H_AHBERRMSK2_Msk = 0x4 + // Bit H_AHBERRMSK2. + USB_HCINTMSK2_H_AHBERRMSK2 = 0x4 + // Position of H_STALLMSK2 field. + USB_HCINTMSK2_H_STALLMSK2_Pos = 0x3 + // Bit mask of H_STALLMSK2 field. + USB_HCINTMSK2_H_STALLMSK2_Msk = 0x8 + // Bit H_STALLMSK2. + USB_HCINTMSK2_H_STALLMSK2 = 0x8 + // Position of H_NAKMSK2 field. + USB_HCINTMSK2_H_NAKMSK2_Pos = 0x4 + // Bit mask of H_NAKMSK2 field. + USB_HCINTMSK2_H_NAKMSK2_Msk = 0x10 + // Bit H_NAKMSK2. + USB_HCINTMSK2_H_NAKMSK2 = 0x10 + // Position of H_ACKMSK2 field. + USB_HCINTMSK2_H_ACKMSK2_Pos = 0x5 + // Bit mask of H_ACKMSK2 field. + USB_HCINTMSK2_H_ACKMSK2_Msk = 0x20 + // Bit H_ACKMSK2. + USB_HCINTMSK2_H_ACKMSK2 = 0x20 + // Position of H_NYETMSK2 field. + USB_HCINTMSK2_H_NYETMSK2_Pos = 0x6 + // Bit mask of H_NYETMSK2 field. + USB_HCINTMSK2_H_NYETMSK2_Msk = 0x40 + // Bit H_NYETMSK2. + USB_HCINTMSK2_H_NYETMSK2 = 0x40 + // Position of H_XACTERRMSK2 field. + USB_HCINTMSK2_H_XACTERRMSK2_Pos = 0x7 + // Bit mask of H_XACTERRMSK2 field. + USB_HCINTMSK2_H_XACTERRMSK2_Msk = 0x80 + // Bit H_XACTERRMSK2. + USB_HCINTMSK2_H_XACTERRMSK2 = 0x80 + // Position of H_BBLERRMSK2 field. + USB_HCINTMSK2_H_BBLERRMSK2_Pos = 0x8 + // Bit mask of H_BBLERRMSK2 field. + USB_HCINTMSK2_H_BBLERRMSK2_Msk = 0x100 + // Bit H_BBLERRMSK2. + USB_HCINTMSK2_H_BBLERRMSK2 = 0x100 + // Position of H_FRMOVRUNMSK2 field. + USB_HCINTMSK2_H_FRMOVRUNMSK2_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK2 field. + USB_HCINTMSK2_H_FRMOVRUNMSK2_Msk = 0x200 + // Bit H_FRMOVRUNMSK2. + USB_HCINTMSK2_H_FRMOVRUNMSK2 = 0x200 + // Position of H_DATATGLERRMSK2 field. + USB_HCINTMSK2_H_DATATGLERRMSK2_Pos = 0xa + // Bit mask of H_DATATGLERRMSK2 field. + USB_HCINTMSK2_H_DATATGLERRMSK2_Msk = 0x400 + // Bit H_DATATGLERRMSK2. + USB_HCINTMSK2_H_DATATGLERRMSK2 = 0x400 + // Position of H_BNAINTRMSK2 field. + USB_HCINTMSK2_H_BNAINTRMSK2_Pos = 0xb + // Bit mask of H_BNAINTRMSK2 field. + USB_HCINTMSK2_H_BNAINTRMSK2_Msk = 0x800 + // Bit H_BNAINTRMSK2. + USB_HCINTMSK2_H_BNAINTRMSK2 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK2 field. + USB_HCINTMSK2_H_DESC_LST_ROLLINTRMSK2_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK2 field. + USB_HCINTMSK2_H_DESC_LST_ROLLINTRMSK2_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK2. + USB_HCINTMSK2_H_DESC_LST_ROLLINTRMSK2 = 0x2000 + + // HCTSIZ2 + // Position of H_XFERSIZE2 field. + USB_HCTSIZ2_H_XFERSIZE2_Pos = 0x0 + // Bit mask of H_XFERSIZE2 field. + USB_HCTSIZ2_H_XFERSIZE2_Msk = 0x7ffff + // Position of H_PKTCNT2 field. + USB_HCTSIZ2_H_PKTCNT2_Pos = 0x13 + // Bit mask of H_PKTCNT2 field. + USB_HCTSIZ2_H_PKTCNT2_Msk = 0x1ff80000 + // Position of H_PID2 field. + USB_HCTSIZ2_H_PID2_Pos = 0x1d + // Bit mask of H_PID2 field. + USB_HCTSIZ2_H_PID2_Msk = 0x60000000 + // Position of H_DOPNG2 field. + USB_HCTSIZ2_H_DOPNG2_Pos = 0x1f + // Bit mask of H_DOPNG2 field. + USB_HCTSIZ2_H_DOPNG2_Msk = 0x80000000 + // Bit H_DOPNG2. + USB_HCTSIZ2_H_DOPNG2 = 0x80000000 + + // HCDMA2 + // Position of H_DMAADDR2 field. + USB_HCDMA2_H_DMAADDR2_Pos = 0x0 + // Bit mask of H_DMAADDR2 field. + USB_HCDMA2_H_DMAADDR2_Msk = 0xffffffff + + // HCDMAB2 + // Position of H_HCDMAB2 field. + USB_HCDMAB2_H_HCDMAB2_Pos = 0x0 + // Bit mask of H_HCDMAB2 field. + USB_HCDMAB2_H_HCDMAB2_Msk = 0xffffffff + + // HCCHAR3 + // Position of H_MPS3 field. + USB_HCCHAR3_H_MPS3_Pos = 0x0 + // Bit mask of H_MPS3 field. + USB_HCCHAR3_H_MPS3_Msk = 0x7ff + // Position of H_EPNUM3 field. + USB_HCCHAR3_H_EPNUM3_Pos = 0xb + // Bit mask of H_EPNUM3 field. + USB_HCCHAR3_H_EPNUM3_Msk = 0x7800 + // Position of H_EPDIR3 field. + USB_HCCHAR3_H_EPDIR3_Pos = 0xf + // Bit mask of H_EPDIR3 field. + USB_HCCHAR3_H_EPDIR3_Msk = 0x8000 + // Bit H_EPDIR3. + USB_HCCHAR3_H_EPDIR3 = 0x8000 + // Position of H_LSPDDEV3 field. + USB_HCCHAR3_H_LSPDDEV3_Pos = 0x11 + // Bit mask of H_LSPDDEV3 field. + USB_HCCHAR3_H_LSPDDEV3_Msk = 0x20000 + // Bit H_LSPDDEV3. + USB_HCCHAR3_H_LSPDDEV3 = 0x20000 + // Position of H_EPTYPE3 field. + USB_HCCHAR3_H_EPTYPE3_Pos = 0x12 + // Bit mask of H_EPTYPE3 field. + USB_HCCHAR3_H_EPTYPE3_Msk = 0xc0000 + // Position of H_EC3 field. + USB_HCCHAR3_H_EC3_Pos = 0x15 + // Bit mask of H_EC3 field. + USB_HCCHAR3_H_EC3_Msk = 0x200000 + // Bit H_EC3. + USB_HCCHAR3_H_EC3 = 0x200000 + // Position of H_DEVADDR3 field. + USB_HCCHAR3_H_DEVADDR3_Pos = 0x16 + // Bit mask of H_DEVADDR3 field. + USB_HCCHAR3_H_DEVADDR3_Msk = 0x1fc00000 + // Position of H_ODDFRM3 field. + USB_HCCHAR3_H_ODDFRM3_Pos = 0x1d + // Bit mask of H_ODDFRM3 field. + USB_HCCHAR3_H_ODDFRM3_Msk = 0x20000000 + // Bit H_ODDFRM3. + USB_HCCHAR3_H_ODDFRM3 = 0x20000000 + // Position of H_CHDIS3 field. + USB_HCCHAR3_H_CHDIS3_Pos = 0x1e + // Bit mask of H_CHDIS3 field. + USB_HCCHAR3_H_CHDIS3_Msk = 0x40000000 + // Bit H_CHDIS3. + USB_HCCHAR3_H_CHDIS3 = 0x40000000 + // Position of H_CHENA3 field. + USB_HCCHAR3_H_CHENA3_Pos = 0x1f + // Bit mask of H_CHENA3 field. + USB_HCCHAR3_H_CHENA3_Msk = 0x80000000 + // Bit H_CHENA3. + USB_HCCHAR3_H_CHENA3 = 0x80000000 + + // HCINT3 + // Position of H_XFERCOMPL3 field. + USB_HCINT3_H_XFERCOMPL3_Pos = 0x0 + // Bit mask of H_XFERCOMPL3 field. + USB_HCINT3_H_XFERCOMPL3_Msk = 0x1 + // Bit H_XFERCOMPL3. + USB_HCINT3_H_XFERCOMPL3 = 0x1 + // Position of H_CHHLTD3 field. + USB_HCINT3_H_CHHLTD3_Pos = 0x1 + // Bit mask of H_CHHLTD3 field. + USB_HCINT3_H_CHHLTD3_Msk = 0x2 + // Bit H_CHHLTD3. + USB_HCINT3_H_CHHLTD3 = 0x2 + // Position of H_AHBERR3 field. + USB_HCINT3_H_AHBERR3_Pos = 0x2 + // Bit mask of H_AHBERR3 field. + USB_HCINT3_H_AHBERR3_Msk = 0x4 + // Bit H_AHBERR3. + USB_HCINT3_H_AHBERR3 = 0x4 + // Position of H_STALL3 field. + USB_HCINT3_H_STALL3_Pos = 0x3 + // Bit mask of H_STALL3 field. + USB_HCINT3_H_STALL3_Msk = 0x8 + // Bit H_STALL3. + USB_HCINT3_H_STALL3 = 0x8 + // Position of H_NACK3 field. + USB_HCINT3_H_NACK3_Pos = 0x4 + // Bit mask of H_NACK3 field. + USB_HCINT3_H_NACK3_Msk = 0x10 + // Bit H_NACK3. + USB_HCINT3_H_NACK3 = 0x10 + // Position of H_ACK3 field. + USB_HCINT3_H_ACK3_Pos = 0x5 + // Bit mask of H_ACK3 field. + USB_HCINT3_H_ACK3_Msk = 0x20 + // Bit H_ACK3. + USB_HCINT3_H_ACK3 = 0x20 + // Position of H_NYET3 field. + USB_HCINT3_H_NYET3_Pos = 0x6 + // Bit mask of H_NYET3 field. + USB_HCINT3_H_NYET3_Msk = 0x40 + // Bit H_NYET3. + USB_HCINT3_H_NYET3 = 0x40 + // Position of H_XACTERR3 field. + USB_HCINT3_H_XACTERR3_Pos = 0x7 + // Bit mask of H_XACTERR3 field. + USB_HCINT3_H_XACTERR3_Msk = 0x80 + // Bit H_XACTERR3. + USB_HCINT3_H_XACTERR3 = 0x80 + // Position of H_BBLERR3 field. + USB_HCINT3_H_BBLERR3_Pos = 0x8 + // Bit mask of H_BBLERR3 field. + USB_HCINT3_H_BBLERR3_Msk = 0x100 + // Bit H_BBLERR3. + USB_HCINT3_H_BBLERR3 = 0x100 + // Position of H_FRMOVRUN3 field. + USB_HCINT3_H_FRMOVRUN3_Pos = 0x9 + // Bit mask of H_FRMOVRUN3 field. + USB_HCINT3_H_FRMOVRUN3_Msk = 0x200 + // Bit H_FRMOVRUN3. + USB_HCINT3_H_FRMOVRUN3 = 0x200 + // Position of H_DATATGLERR3 field. + USB_HCINT3_H_DATATGLERR3_Pos = 0xa + // Bit mask of H_DATATGLERR3 field. + USB_HCINT3_H_DATATGLERR3_Msk = 0x400 + // Bit H_DATATGLERR3. + USB_HCINT3_H_DATATGLERR3 = 0x400 + // Position of H_BNAINTR3 field. + USB_HCINT3_H_BNAINTR3_Pos = 0xb + // Bit mask of H_BNAINTR3 field. + USB_HCINT3_H_BNAINTR3_Msk = 0x800 + // Bit H_BNAINTR3. + USB_HCINT3_H_BNAINTR3 = 0x800 + // Position of H_XCS_XACT_ERR3 field. + USB_HCINT3_H_XCS_XACT_ERR3_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR3 field. + USB_HCINT3_H_XCS_XACT_ERR3_Msk = 0x1000 + // Bit H_XCS_XACT_ERR3. + USB_HCINT3_H_XCS_XACT_ERR3 = 0x1000 + // Position of H_DESC_LST_ROLLINTR3 field. + USB_HCINT3_H_DESC_LST_ROLLINTR3_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR3 field. + USB_HCINT3_H_DESC_LST_ROLLINTR3_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR3. + USB_HCINT3_H_DESC_LST_ROLLINTR3 = 0x2000 + + // HCINTMSK3 + // Position of H_XFERCOMPLMSK3 field. + USB_HCINTMSK3_H_XFERCOMPLMSK3_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK3 field. + USB_HCINTMSK3_H_XFERCOMPLMSK3_Msk = 0x1 + // Bit H_XFERCOMPLMSK3. + USB_HCINTMSK3_H_XFERCOMPLMSK3 = 0x1 + // Position of H_CHHLTDMSK3 field. + USB_HCINTMSK3_H_CHHLTDMSK3_Pos = 0x1 + // Bit mask of H_CHHLTDMSK3 field. + USB_HCINTMSK3_H_CHHLTDMSK3_Msk = 0x2 + // Bit H_CHHLTDMSK3. + USB_HCINTMSK3_H_CHHLTDMSK3 = 0x2 + // Position of H_AHBERRMSK3 field. + USB_HCINTMSK3_H_AHBERRMSK3_Pos = 0x2 + // Bit mask of H_AHBERRMSK3 field. + USB_HCINTMSK3_H_AHBERRMSK3_Msk = 0x4 + // Bit H_AHBERRMSK3. + USB_HCINTMSK3_H_AHBERRMSK3 = 0x4 + // Position of H_STALLMSK3 field. + USB_HCINTMSK3_H_STALLMSK3_Pos = 0x3 + // Bit mask of H_STALLMSK3 field. + USB_HCINTMSK3_H_STALLMSK3_Msk = 0x8 + // Bit H_STALLMSK3. + USB_HCINTMSK3_H_STALLMSK3 = 0x8 + // Position of H_NAKMSK3 field. + USB_HCINTMSK3_H_NAKMSK3_Pos = 0x4 + // Bit mask of H_NAKMSK3 field. + USB_HCINTMSK3_H_NAKMSK3_Msk = 0x10 + // Bit H_NAKMSK3. + USB_HCINTMSK3_H_NAKMSK3 = 0x10 + // Position of H_ACKMSK3 field. + USB_HCINTMSK3_H_ACKMSK3_Pos = 0x5 + // Bit mask of H_ACKMSK3 field. + USB_HCINTMSK3_H_ACKMSK3_Msk = 0x20 + // Bit H_ACKMSK3. + USB_HCINTMSK3_H_ACKMSK3 = 0x20 + // Position of H_NYETMSK3 field. + USB_HCINTMSK3_H_NYETMSK3_Pos = 0x6 + // Bit mask of H_NYETMSK3 field. + USB_HCINTMSK3_H_NYETMSK3_Msk = 0x40 + // Bit H_NYETMSK3. + USB_HCINTMSK3_H_NYETMSK3 = 0x40 + // Position of H_XACTERRMSK3 field. + USB_HCINTMSK3_H_XACTERRMSK3_Pos = 0x7 + // Bit mask of H_XACTERRMSK3 field. + USB_HCINTMSK3_H_XACTERRMSK3_Msk = 0x80 + // Bit H_XACTERRMSK3. + USB_HCINTMSK3_H_XACTERRMSK3 = 0x80 + // Position of H_BBLERRMSK3 field. + USB_HCINTMSK3_H_BBLERRMSK3_Pos = 0x8 + // Bit mask of H_BBLERRMSK3 field. + USB_HCINTMSK3_H_BBLERRMSK3_Msk = 0x100 + // Bit H_BBLERRMSK3. + USB_HCINTMSK3_H_BBLERRMSK3 = 0x100 + // Position of H_FRMOVRUNMSK3 field. + USB_HCINTMSK3_H_FRMOVRUNMSK3_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK3 field. + USB_HCINTMSK3_H_FRMOVRUNMSK3_Msk = 0x200 + // Bit H_FRMOVRUNMSK3. + USB_HCINTMSK3_H_FRMOVRUNMSK3 = 0x200 + // Position of H_DATATGLERRMSK3 field. + USB_HCINTMSK3_H_DATATGLERRMSK3_Pos = 0xa + // Bit mask of H_DATATGLERRMSK3 field. + USB_HCINTMSK3_H_DATATGLERRMSK3_Msk = 0x400 + // Bit H_DATATGLERRMSK3. + USB_HCINTMSK3_H_DATATGLERRMSK3 = 0x400 + // Position of H_BNAINTRMSK3 field. + USB_HCINTMSK3_H_BNAINTRMSK3_Pos = 0xb + // Bit mask of H_BNAINTRMSK3 field. + USB_HCINTMSK3_H_BNAINTRMSK3_Msk = 0x800 + // Bit H_BNAINTRMSK3. + USB_HCINTMSK3_H_BNAINTRMSK3 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK3 field. + USB_HCINTMSK3_H_DESC_LST_ROLLINTRMSK3_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK3 field. + USB_HCINTMSK3_H_DESC_LST_ROLLINTRMSK3_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK3. + USB_HCINTMSK3_H_DESC_LST_ROLLINTRMSK3 = 0x2000 + + // HCTSIZ3 + // Position of H_XFERSIZE3 field. + USB_HCTSIZ3_H_XFERSIZE3_Pos = 0x0 + // Bit mask of H_XFERSIZE3 field. + USB_HCTSIZ3_H_XFERSIZE3_Msk = 0x7ffff + // Position of H_PKTCNT3 field. + USB_HCTSIZ3_H_PKTCNT3_Pos = 0x13 + // Bit mask of H_PKTCNT3 field. + USB_HCTSIZ3_H_PKTCNT3_Msk = 0x1ff80000 + // Position of H_PID3 field. + USB_HCTSIZ3_H_PID3_Pos = 0x1d + // Bit mask of H_PID3 field. + USB_HCTSIZ3_H_PID3_Msk = 0x60000000 + // Position of H_DOPNG3 field. + USB_HCTSIZ3_H_DOPNG3_Pos = 0x1f + // Bit mask of H_DOPNG3 field. + USB_HCTSIZ3_H_DOPNG3_Msk = 0x80000000 + // Bit H_DOPNG3. + USB_HCTSIZ3_H_DOPNG3 = 0x80000000 + + // HCDMA3 + // Position of H_DMAADDR3 field. + USB_HCDMA3_H_DMAADDR3_Pos = 0x0 + // Bit mask of H_DMAADDR3 field. + USB_HCDMA3_H_DMAADDR3_Msk = 0xffffffff + + // HCDMAB3 + // Position of H_HCDMAB3 field. + USB_HCDMAB3_H_HCDMAB3_Pos = 0x0 + // Bit mask of H_HCDMAB3 field. + USB_HCDMAB3_H_HCDMAB3_Msk = 0xffffffff + + // HCCHAR4 + // Position of H_MPS4 field. + USB_HCCHAR4_H_MPS4_Pos = 0x0 + // Bit mask of H_MPS4 field. + USB_HCCHAR4_H_MPS4_Msk = 0x7ff + // Position of H_EPNUM4 field. + USB_HCCHAR4_H_EPNUM4_Pos = 0xb + // Bit mask of H_EPNUM4 field. + USB_HCCHAR4_H_EPNUM4_Msk = 0x7800 + // Position of H_EPDIR4 field. + USB_HCCHAR4_H_EPDIR4_Pos = 0xf + // Bit mask of H_EPDIR4 field. + USB_HCCHAR4_H_EPDIR4_Msk = 0x8000 + // Bit H_EPDIR4. + USB_HCCHAR4_H_EPDIR4 = 0x8000 + // Position of H_LSPDDEV4 field. + USB_HCCHAR4_H_LSPDDEV4_Pos = 0x11 + // Bit mask of H_LSPDDEV4 field. + USB_HCCHAR4_H_LSPDDEV4_Msk = 0x20000 + // Bit H_LSPDDEV4. + USB_HCCHAR4_H_LSPDDEV4 = 0x20000 + // Position of H_EPTYPE4 field. + USB_HCCHAR4_H_EPTYPE4_Pos = 0x12 + // Bit mask of H_EPTYPE4 field. + USB_HCCHAR4_H_EPTYPE4_Msk = 0xc0000 + // Position of H_EC4 field. + USB_HCCHAR4_H_EC4_Pos = 0x15 + // Bit mask of H_EC4 field. + USB_HCCHAR4_H_EC4_Msk = 0x200000 + // Bit H_EC4. + USB_HCCHAR4_H_EC4 = 0x200000 + // Position of H_DEVADDR4 field. + USB_HCCHAR4_H_DEVADDR4_Pos = 0x16 + // Bit mask of H_DEVADDR4 field. + USB_HCCHAR4_H_DEVADDR4_Msk = 0x1fc00000 + // Position of H_ODDFRM4 field. + USB_HCCHAR4_H_ODDFRM4_Pos = 0x1d + // Bit mask of H_ODDFRM4 field. + USB_HCCHAR4_H_ODDFRM4_Msk = 0x20000000 + // Bit H_ODDFRM4. + USB_HCCHAR4_H_ODDFRM4 = 0x20000000 + // Position of H_CHDIS4 field. + USB_HCCHAR4_H_CHDIS4_Pos = 0x1e + // Bit mask of H_CHDIS4 field. + USB_HCCHAR4_H_CHDIS4_Msk = 0x40000000 + // Bit H_CHDIS4. + USB_HCCHAR4_H_CHDIS4 = 0x40000000 + // Position of H_CHENA4 field. + USB_HCCHAR4_H_CHENA4_Pos = 0x1f + // Bit mask of H_CHENA4 field. + USB_HCCHAR4_H_CHENA4_Msk = 0x80000000 + // Bit H_CHENA4. + USB_HCCHAR4_H_CHENA4 = 0x80000000 + + // HCINT4 + // Position of H_XFERCOMPL4 field. + USB_HCINT4_H_XFERCOMPL4_Pos = 0x0 + // Bit mask of H_XFERCOMPL4 field. + USB_HCINT4_H_XFERCOMPL4_Msk = 0x1 + // Bit H_XFERCOMPL4. + USB_HCINT4_H_XFERCOMPL4 = 0x1 + // Position of H_CHHLTD4 field. + USB_HCINT4_H_CHHLTD4_Pos = 0x1 + // Bit mask of H_CHHLTD4 field. + USB_HCINT4_H_CHHLTD4_Msk = 0x2 + // Bit H_CHHLTD4. + USB_HCINT4_H_CHHLTD4 = 0x2 + // Position of H_AHBERR4 field. + USB_HCINT4_H_AHBERR4_Pos = 0x2 + // Bit mask of H_AHBERR4 field. + USB_HCINT4_H_AHBERR4_Msk = 0x4 + // Bit H_AHBERR4. + USB_HCINT4_H_AHBERR4 = 0x4 + // Position of H_STALL4 field. + USB_HCINT4_H_STALL4_Pos = 0x3 + // Bit mask of H_STALL4 field. + USB_HCINT4_H_STALL4_Msk = 0x8 + // Bit H_STALL4. + USB_HCINT4_H_STALL4 = 0x8 + // Position of H_NACK4 field. + USB_HCINT4_H_NACK4_Pos = 0x4 + // Bit mask of H_NACK4 field. + USB_HCINT4_H_NACK4_Msk = 0x10 + // Bit H_NACK4. + USB_HCINT4_H_NACK4 = 0x10 + // Position of H_ACK4 field. + USB_HCINT4_H_ACK4_Pos = 0x5 + // Bit mask of H_ACK4 field. + USB_HCINT4_H_ACK4_Msk = 0x20 + // Bit H_ACK4. + USB_HCINT4_H_ACK4 = 0x20 + // Position of H_NYET4 field. + USB_HCINT4_H_NYET4_Pos = 0x6 + // Bit mask of H_NYET4 field. + USB_HCINT4_H_NYET4_Msk = 0x40 + // Bit H_NYET4. + USB_HCINT4_H_NYET4 = 0x40 + // Position of H_XACTERR4 field. + USB_HCINT4_H_XACTERR4_Pos = 0x7 + // Bit mask of H_XACTERR4 field. + USB_HCINT4_H_XACTERR4_Msk = 0x80 + // Bit H_XACTERR4. + USB_HCINT4_H_XACTERR4 = 0x80 + // Position of H_BBLERR4 field. + USB_HCINT4_H_BBLERR4_Pos = 0x8 + // Bit mask of H_BBLERR4 field. + USB_HCINT4_H_BBLERR4_Msk = 0x100 + // Bit H_BBLERR4. + USB_HCINT4_H_BBLERR4 = 0x100 + // Position of H_FRMOVRUN4 field. + USB_HCINT4_H_FRMOVRUN4_Pos = 0x9 + // Bit mask of H_FRMOVRUN4 field. + USB_HCINT4_H_FRMOVRUN4_Msk = 0x200 + // Bit H_FRMOVRUN4. + USB_HCINT4_H_FRMOVRUN4 = 0x200 + // Position of H_DATATGLERR4 field. + USB_HCINT4_H_DATATGLERR4_Pos = 0xa + // Bit mask of H_DATATGLERR4 field. + USB_HCINT4_H_DATATGLERR4_Msk = 0x400 + // Bit H_DATATGLERR4. + USB_HCINT4_H_DATATGLERR4 = 0x400 + // Position of H_BNAINTR4 field. + USB_HCINT4_H_BNAINTR4_Pos = 0xb + // Bit mask of H_BNAINTR4 field. + USB_HCINT4_H_BNAINTR4_Msk = 0x800 + // Bit H_BNAINTR4. + USB_HCINT4_H_BNAINTR4 = 0x800 + // Position of H_XCS_XACT_ERR4 field. + USB_HCINT4_H_XCS_XACT_ERR4_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR4 field. + USB_HCINT4_H_XCS_XACT_ERR4_Msk = 0x1000 + // Bit H_XCS_XACT_ERR4. + USB_HCINT4_H_XCS_XACT_ERR4 = 0x1000 + // Position of H_DESC_LST_ROLLINTR4 field. + USB_HCINT4_H_DESC_LST_ROLLINTR4_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR4 field. + USB_HCINT4_H_DESC_LST_ROLLINTR4_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR4. + USB_HCINT4_H_DESC_LST_ROLLINTR4 = 0x2000 + + // HCINTMSK4 + // Position of H_XFERCOMPLMSK4 field. + USB_HCINTMSK4_H_XFERCOMPLMSK4_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK4 field. + USB_HCINTMSK4_H_XFERCOMPLMSK4_Msk = 0x1 + // Bit H_XFERCOMPLMSK4. + USB_HCINTMSK4_H_XFERCOMPLMSK4 = 0x1 + // Position of H_CHHLTDMSK4 field. + USB_HCINTMSK4_H_CHHLTDMSK4_Pos = 0x1 + // Bit mask of H_CHHLTDMSK4 field. + USB_HCINTMSK4_H_CHHLTDMSK4_Msk = 0x2 + // Bit H_CHHLTDMSK4. + USB_HCINTMSK4_H_CHHLTDMSK4 = 0x2 + // Position of H_AHBERRMSK4 field. + USB_HCINTMSK4_H_AHBERRMSK4_Pos = 0x2 + // Bit mask of H_AHBERRMSK4 field. + USB_HCINTMSK4_H_AHBERRMSK4_Msk = 0x4 + // Bit H_AHBERRMSK4. + USB_HCINTMSK4_H_AHBERRMSK4 = 0x4 + // Position of H_STALLMSK4 field. + USB_HCINTMSK4_H_STALLMSK4_Pos = 0x3 + // Bit mask of H_STALLMSK4 field. + USB_HCINTMSK4_H_STALLMSK4_Msk = 0x8 + // Bit H_STALLMSK4. + USB_HCINTMSK4_H_STALLMSK4 = 0x8 + // Position of H_NAKMSK4 field. + USB_HCINTMSK4_H_NAKMSK4_Pos = 0x4 + // Bit mask of H_NAKMSK4 field. + USB_HCINTMSK4_H_NAKMSK4_Msk = 0x10 + // Bit H_NAKMSK4. + USB_HCINTMSK4_H_NAKMSK4 = 0x10 + // Position of H_ACKMSK4 field. + USB_HCINTMSK4_H_ACKMSK4_Pos = 0x5 + // Bit mask of H_ACKMSK4 field. + USB_HCINTMSK4_H_ACKMSK4_Msk = 0x20 + // Bit H_ACKMSK4. + USB_HCINTMSK4_H_ACKMSK4 = 0x20 + // Position of H_NYETMSK4 field. + USB_HCINTMSK4_H_NYETMSK4_Pos = 0x6 + // Bit mask of H_NYETMSK4 field. + USB_HCINTMSK4_H_NYETMSK4_Msk = 0x40 + // Bit H_NYETMSK4. + USB_HCINTMSK4_H_NYETMSK4 = 0x40 + // Position of H_XACTERRMSK4 field. + USB_HCINTMSK4_H_XACTERRMSK4_Pos = 0x7 + // Bit mask of H_XACTERRMSK4 field. + USB_HCINTMSK4_H_XACTERRMSK4_Msk = 0x80 + // Bit H_XACTERRMSK4. + USB_HCINTMSK4_H_XACTERRMSK4 = 0x80 + // Position of H_BBLERRMSK4 field. + USB_HCINTMSK4_H_BBLERRMSK4_Pos = 0x8 + // Bit mask of H_BBLERRMSK4 field. + USB_HCINTMSK4_H_BBLERRMSK4_Msk = 0x100 + // Bit H_BBLERRMSK4. + USB_HCINTMSK4_H_BBLERRMSK4 = 0x100 + // Position of H_FRMOVRUNMSK4 field. + USB_HCINTMSK4_H_FRMOVRUNMSK4_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK4 field. + USB_HCINTMSK4_H_FRMOVRUNMSK4_Msk = 0x200 + // Bit H_FRMOVRUNMSK4. + USB_HCINTMSK4_H_FRMOVRUNMSK4 = 0x200 + // Position of H_DATATGLERRMSK4 field. + USB_HCINTMSK4_H_DATATGLERRMSK4_Pos = 0xa + // Bit mask of H_DATATGLERRMSK4 field. + USB_HCINTMSK4_H_DATATGLERRMSK4_Msk = 0x400 + // Bit H_DATATGLERRMSK4. + USB_HCINTMSK4_H_DATATGLERRMSK4 = 0x400 + // Position of H_BNAINTRMSK4 field. + USB_HCINTMSK4_H_BNAINTRMSK4_Pos = 0xb + // Bit mask of H_BNAINTRMSK4 field. + USB_HCINTMSK4_H_BNAINTRMSK4_Msk = 0x800 + // Bit H_BNAINTRMSK4. + USB_HCINTMSK4_H_BNAINTRMSK4 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK4 field. + USB_HCINTMSK4_H_DESC_LST_ROLLINTRMSK4_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK4 field. + USB_HCINTMSK4_H_DESC_LST_ROLLINTRMSK4_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK4. + USB_HCINTMSK4_H_DESC_LST_ROLLINTRMSK4 = 0x2000 + + // HCTSIZ4 + // Position of H_XFERSIZE4 field. + USB_HCTSIZ4_H_XFERSIZE4_Pos = 0x0 + // Bit mask of H_XFERSIZE4 field. + USB_HCTSIZ4_H_XFERSIZE4_Msk = 0x7ffff + // Position of H_PKTCNT4 field. + USB_HCTSIZ4_H_PKTCNT4_Pos = 0x13 + // Bit mask of H_PKTCNT4 field. + USB_HCTSIZ4_H_PKTCNT4_Msk = 0x1ff80000 + // Position of H_PID4 field. + USB_HCTSIZ4_H_PID4_Pos = 0x1d + // Bit mask of H_PID4 field. + USB_HCTSIZ4_H_PID4_Msk = 0x60000000 + // Position of H_DOPNG4 field. + USB_HCTSIZ4_H_DOPNG4_Pos = 0x1f + // Bit mask of H_DOPNG4 field. + USB_HCTSIZ4_H_DOPNG4_Msk = 0x80000000 + // Bit H_DOPNG4. + USB_HCTSIZ4_H_DOPNG4 = 0x80000000 + + // HCDMA4 + // Position of H_DMAADDR4 field. + USB_HCDMA4_H_DMAADDR4_Pos = 0x0 + // Bit mask of H_DMAADDR4 field. + USB_HCDMA4_H_DMAADDR4_Msk = 0xffffffff + + // HCDMAB4 + // Position of H_HCDMAB4 field. + USB_HCDMAB4_H_HCDMAB4_Pos = 0x0 + // Bit mask of H_HCDMAB4 field. + USB_HCDMAB4_H_HCDMAB4_Msk = 0xffffffff + + // HCCHAR5 + // Position of H_MPS5 field. + USB_HCCHAR5_H_MPS5_Pos = 0x0 + // Bit mask of H_MPS5 field. + USB_HCCHAR5_H_MPS5_Msk = 0x7ff + // Position of H_EPNUM5 field. + USB_HCCHAR5_H_EPNUM5_Pos = 0xb + // Bit mask of H_EPNUM5 field. + USB_HCCHAR5_H_EPNUM5_Msk = 0x7800 + // Position of H_EPDIR5 field. + USB_HCCHAR5_H_EPDIR5_Pos = 0xf + // Bit mask of H_EPDIR5 field. + USB_HCCHAR5_H_EPDIR5_Msk = 0x8000 + // Bit H_EPDIR5. + USB_HCCHAR5_H_EPDIR5 = 0x8000 + // Position of H_LSPDDEV5 field. + USB_HCCHAR5_H_LSPDDEV5_Pos = 0x11 + // Bit mask of H_LSPDDEV5 field. + USB_HCCHAR5_H_LSPDDEV5_Msk = 0x20000 + // Bit H_LSPDDEV5. + USB_HCCHAR5_H_LSPDDEV5 = 0x20000 + // Position of H_EPTYPE5 field. + USB_HCCHAR5_H_EPTYPE5_Pos = 0x12 + // Bit mask of H_EPTYPE5 field. + USB_HCCHAR5_H_EPTYPE5_Msk = 0xc0000 + // Position of H_EC5 field. + USB_HCCHAR5_H_EC5_Pos = 0x15 + // Bit mask of H_EC5 field. + USB_HCCHAR5_H_EC5_Msk = 0x200000 + // Bit H_EC5. + USB_HCCHAR5_H_EC5 = 0x200000 + // Position of H_DEVADDR5 field. + USB_HCCHAR5_H_DEVADDR5_Pos = 0x16 + // Bit mask of H_DEVADDR5 field. + USB_HCCHAR5_H_DEVADDR5_Msk = 0x1fc00000 + // Position of H_ODDFRM5 field. + USB_HCCHAR5_H_ODDFRM5_Pos = 0x1d + // Bit mask of H_ODDFRM5 field. + USB_HCCHAR5_H_ODDFRM5_Msk = 0x20000000 + // Bit H_ODDFRM5. + USB_HCCHAR5_H_ODDFRM5 = 0x20000000 + // Position of H_CHDIS5 field. + USB_HCCHAR5_H_CHDIS5_Pos = 0x1e + // Bit mask of H_CHDIS5 field. + USB_HCCHAR5_H_CHDIS5_Msk = 0x40000000 + // Bit H_CHDIS5. + USB_HCCHAR5_H_CHDIS5 = 0x40000000 + // Position of H_CHENA5 field. + USB_HCCHAR5_H_CHENA5_Pos = 0x1f + // Bit mask of H_CHENA5 field. + USB_HCCHAR5_H_CHENA5_Msk = 0x80000000 + // Bit H_CHENA5. + USB_HCCHAR5_H_CHENA5 = 0x80000000 + + // HCINT5 + // Position of H_XFERCOMPL5 field. + USB_HCINT5_H_XFERCOMPL5_Pos = 0x0 + // Bit mask of H_XFERCOMPL5 field. + USB_HCINT5_H_XFERCOMPL5_Msk = 0x1 + // Bit H_XFERCOMPL5. + USB_HCINT5_H_XFERCOMPL5 = 0x1 + // Position of H_CHHLTD5 field. + USB_HCINT5_H_CHHLTD5_Pos = 0x1 + // Bit mask of H_CHHLTD5 field. + USB_HCINT5_H_CHHLTD5_Msk = 0x2 + // Bit H_CHHLTD5. + USB_HCINT5_H_CHHLTD5 = 0x2 + // Position of H_AHBERR5 field. + USB_HCINT5_H_AHBERR5_Pos = 0x2 + // Bit mask of H_AHBERR5 field. + USB_HCINT5_H_AHBERR5_Msk = 0x4 + // Bit H_AHBERR5. + USB_HCINT5_H_AHBERR5 = 0x4 + // Position of H_STALL5 field. + USB_HCINT5_H_STALL5_Pos = 0x3 + // Bit mask of H_STALL5 field. + USB_HCINT5_H_STALL5_Msk = 0x8 + // Bit H_STALL5. + USB_HCINT5_H_STALL5 = 0x8 + // Position of H_NACK5 field. + USB_HCINT5_H_NACK5_Pos = 0x4 + // Bit mask of H_NACK5 field. + USB_HCINT5_H_NACK5_Msk = 0x10 + // Bit H_NACK5. + USB_HCINT5_H_NACK5 = 0x10 + // Position of H_ACK5 field. + USB_HCINT5_H_ACK5_Pos = 0x5 + // Bit mask of H_ACK5 field. + USB_HCINT5_H_ACK5_Msk = 0x20 + // Bit H_ACK5. + USB_HCINT5_H_ACK5 = 0x20 + // Position of H_NYET5 field. + USB_HCINT5_H_NYET5_Pos = 0x6 + // Bit mask of H_NYET5 field. + USB_HCINT5_H_NYET5_Msk = 0x40 + // Bit H_NYET5. + USB_HCINT5_H_NYET5 = 0x40 + // Position of H_XACTERR5 field. + USB_HCINT5_H_XACTERR5_Pos = 0x7 + // Bit mask of H_XACTERR5 field. + USB_HCINT5_H_XACTERR5_Msk = 0x80 + // Bit H_XACTERR5. + USB_HCINT5_H_XACTERR5 = 0x80 + // Position of H_BBLERR5 field. + USB_HCINT5_H_BBLERR5_Pos = 0x8 + // Bit mask of H_BBLERR5 field. + USB_HCINT5_H_BBLERR5_Msk = 0x100 + // Bit H_BBLERR5. + USB_HCINT5_H_BBLERR5 = 0x100 + // Position of H_FRMOVRUN5 field. + USB_HCINT5_H_FRMOVRUN5_Pos = 0x9 + // Bit mask of H_FRMOVRUN5 field. + USB_HCINT5_H_FRMOVRUN5_Msk = 0x200 + // Bit H_FRMOVRUN5. + USB_HCINT5_H_FRMOVRUN5 = 0x200 + // Position of H_DATATGLERR5 field. + USB_HCINT5_H_DATATGLERR5_Pos = 0xa + // Bit mask of H_DATATGLERR5 field. + USB_HCINT5_H_DATATGLERR5_Msk = 0x400 + // Bit H_DATATGLERR5. + USB_HCINT5_H_DATATGLERR5 = 0x400 + // Position of H_BNAINTR5 field. + USB_HCINT5_H_BNAINTR5_Pos = 0xb + // Bit mask of H_BNAINTR5 field. + USB_HCINT5_H_BNAINTR5_Msk = 0x800 + // Bit H_BNAINTR5. + USB_HCINT5_H_BNAINTR5 = 0x800 + // Position of H_XCS_XACT_ERR5 field. + USB_HCINT5_H_XCS_XACT_ERR5_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR5 field. + USB_HCINT5_H_XCS_XACT_ERR5_Msk = 0x1000 + // Bit H_XCS_XACT_ERR5. + USB_HCINT5_H_XCS_XACT_ERR5 = 0x1000 + // Position of H_DESC_LST_ROLLINTR5 field. + USB_HCINT5_H_DESC_LST_ROLLINTR5_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR5 field. + USB_HCINT5_H_DESC_LST_ROLLINTR5_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR5. + USB_HCINT5_H_DESC_LST_ROLLINTR5 = 0x2000 + + // HCINTMSK5 + // Position of H_XFERCOMPLMSK5 field. + USB_HCINTMSK5_H_XFERCOMPLMSK5_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK5 field. + USB_HCINTMSK5_H_XFERCOMPLMSK5_Msk = 0x1 + // Bit H_XFERCOMPLMSK5. + USB_HCINTMSK5_H_XFERCOMPLMSK5 = 0x1 + // Position of H_CHHLTDMSK5 field. + USB_HCINTMSK5_H_CHHLTDMSK5_Pos = 0x1 + // Bit mask of H_CHHLTDMSK5 field. + USB_HCINTMSK5_H_CHHLTDMSK5_Msk = 0x2 + // Bit H_CHHLTDMSK5. + USB_HCINTMSK5_H_CHHLTDMSK5 = 0x2 + // Position of H_AHBERRMSK5 field. + USB_HCINTMSK5_H_AHBERRMSK5_Pos = 0x2 + // Bit mask of H_AHBERRMSK5 field. + USB_HCINTMSK5_H_AHBERRMSK5_Msk = 0x4 + // Bit H_AHBERRMSK5. + USB_HCINTMSK5_H_AHBERRMSK5 = 0x4 + // Position of H_STALLMSK5 field. + USB_HCINTMSK5_H_STALLMSK5_Pos = 0x3 + // Bit mask of H_STALLMSK5 field. + USB_HCINTMSK5_H_STALLMSK5_Msk = 0x8 + // Bit H_STALLMSK5. + USB_HCINTMSK5_H_STALLMSK5 = 0x8 + // Position of H_NAKMSK5 field. + USB_HCINTMSK5_H_NAKMSK5_Pos = 0x4 + // Bit mask of H_NAKMSK5 field. + USB_HCINTMSK5_H_NAKMSK5_Msk = 0x10 + // Bit H_NAKMSK5. + USB_HCINTMSK5_H_NAKMSK5 = 0x10 + // Position of H_ACKMSK5 field. + USB_HCINTMSK5_H_ACKMSK5_Pos = 0x5 + // Bit mask of H_ACKMSK5 field. + USB_HCINTMSK5_H_ACKMSK5_Msk = 0x20 + // Bit H_ACKMSK5. + USB_HCINTMSK5_H_ACKMSK5 = 0x20 + // Position of H_NYETMSK5 field. + USB_HCINTMSK5_H_NYETMSK5_Pos = 0x6 + // Bit mask of H_NYETMSK5 field. + USB_HCINTMSK5_H_NYETMSK5_Msk = 0x40 + // Bit H_NYETMSK5. + USB_HCINTMSK5_H_NYETMSK5 = 0x40 + // Position of H_XACTERRMSK5 field. + USB_HCINTMSK5_H_XACTERRMSK5_Pos = 0x7 + // Bit mask of H_XACTERRMSK5 field. + USB_HCINTMSK5_H_XACTERRMSK5_Msk = 0x80 + // Bit H_XACTERRMSK5. + USB_HCINTMSK5_H_XACTERRMSK5 = 0x80 + // Position of H_BBLERRMSK5 field. + USB_HCINTMSK5_H_BBLERRMSK5_Pos = 0x8 + // Bit mask of H_BBLERRMSK5 field. + USB_HCINTMSK5_H_BBLERRMSK5_Msk = 0x100 + // Bit H_BBLERRMSK5. + USB_HCINTMSK5_H_BBLERRMSK5 = 0x100 + // Position of H_FRMOVRUNMSK5 field. + USB_HCINTMSK5_H_FRMOVRUNMSK5_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK5 field. + USB_HCINTMSK5_H_FRMOVRUNMSK5_Msk = 0x200 + // Bit H_FRMOVRUNMSK5. + USB_HCINTMSK5_H_FRMOVRUNMSK5 = 0x200 + // Position of H_DATATGLERRMSK5 field. + USB_HCINTMSK5_H_DATATGLERRMSK5_Pos = 0xa + // Bit mask of H_DATATGLERRMSK5 field. + USB_HCINTMSK5_H_DATATGLERRMSK5_Msk = 0x400 + // Bit H_DATATGLERRMSK5. + USB_HCINTMSK5_H_DATATGLERRMSK5 = 0x400 + // Position of H_BNAINTRMSK5 field. + USB_HCINTMSK5_H_BNAINTRMSK5_Pos = 0xb + // Bit mask of H_BNAINTRMSK5 field. + USB_HCINTMSK5_H_BNAINTRMSK5_Msk = 0x800 + // Bit H_BNAINTRMSK5. + USB_HCINTMSK5_H_BNAINTRMSK5 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK5 field. + USB_HCINTMSK5_H_DESC_LST_ROLLINTRMSK5_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK5 field. + USB_HCINTMSK5_H_DESC_LST_ROLLINTRMSK5_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK5. + USB_HCINTMSK5_H_DESC_LST_ROLLINTRMSK5 = 0x2000 + + // HCTSIZ5 + // Position of H_XFERSIZE5 field. + USB_HCTSIZ5_H_XFERSIZE5_Pos = 0x0 + // Bit mask of H_XFERSIZE5 field. + USB_HCTSIZ5_H_XFERSIZE5_Msk = 0x7ffff + // Position of H_PKTCNT5 field. + USB_HCTSIZ5_H_PKTCNT5_Pos = 0x13 + // Bit mask of H_PKTCNT5 field. + USB_HCTSIZ5_H_PKTCNT5_Msk = 0x1ff80000 + // Position of H_PID5 field. + USB_HCTSIZ5_H_PID5_Pos = 0x1d + // Bit mask of H_PID5 field. + USB_HCTSIZ5_H_PID5_Msk = 0x60000000 + // Position of H_DOPNG5 field. + USB_HCTSIZ5_H_DOPNG5_Pos = 0x1f + // Bit mask of H_DOPNG5 field. + USB_HCTSIZ5_H_DOPNG5_Msk = 0x80000000 + // Bit H_DOPNG5. + USB_HCTSIZ5_H_DOPNG5 = 0x80000000 + + // HCDMA5 + // Position of H_DMAADDR5 field. + USB_HCDMA5_H_DMAADDR5_Pos = 0x0 + // Bit mask of H_DMAADDR5 field. + USB_HCDMA5_H_DMAADDR5_Msk = 0xffffffff + + // HCDMAB5 + // Position of H_HCDMAB5 field. + USB_HCDMAB5_H_HCDMAB5_Pos = 0x0 + // Bit mask of H_HCDMAB5 field. + USB_HCDMAB5_H_HCDMAB5_Msk = 0xffffffff + + // HCCHAR6 + // Position of H_MPS6 field. + USB_HCCHAR6_H_MPS6_Pos = 0x0 + // Bit mask of H_MPS6 field. + USB_HCCHAR6_H_MPS6_Msk = 0x7ff + // Position of H_EPNUM6 field. + USB_HCCHAR6_H_EPNUM6_Pos = 0xb + // Bit mask of H_EPNUM6 field. + USB_HCCHAR6_H_EPNUM6_Msk = 0x7800 + // Position of H_EPDIR6 field. + USB_HCCHAR6_H_EPDIR6_Pos = 0xf + // Bit mask of H_EPDIR6 field. + USB_HCCHAR6_H_EPDIR6_Msk = 0x8000 + // Bit H_EPDIR6. + USB_HCCHAR6_H_EPDIR6 = 0x8000 + // Position of H_LSPDDEV6 field. + USB_HCCHAR6_H_LSPDDEV6_Pos = 0x11 + // Bit mask of H_LSPDDEV6 field. + USB_HCCHAR6_H_LSPDDEV6_Msk = 0x20000 + // Bit H_LSPDDEV6. + USB_HCCHAR6_H_LSPDDEV6 = 0x20000 + // Position of H_EPTYPE6 field. + USB_HCCHAR6_H_EPTYPE6_Pos = 0x12 + // Bit mask of H_EPTYPE6 field. + USB_HCCHAR6_H_EPTYPE6_Msk = 0xc0000 + // Position of H_EC6 field. + USB_HCCHAR6_H_EC6_Pos = 0x15 + // Bit mask of H_EC6 field. + USB_HCCHAR6_H_EC6_Msk = 0x200000 + // Bit H_EC6. + USB_HCCHAR6_H_EC6 = 0x200000 + // Position of H_DEVADDR6 field. + USB_HCCHAR6_H_DEVADDR6_Pos = 0x16 + // Bit mask of H_DEVADDR6 field. + USB_HCCHAR6_H_DEVADDR6_Msk = 0x1fc00000 + // Position of H_ODDFRM6 field. + USB_HCCHAR6_H_ODDFRM6_Pos = 0x1d + // Bit mask of H_ODDFRM6 field. + USB_HCCHAR6_H_ODDFRM6_Msk = 0x20000000 + // Bit H_ODDFRM6. + USB_HCCHAR6_H_ODDFRM6 = 0x20000000 + // Position of H_CHDIS6 field. + USB_HCCHAR6_H_CHDIS6_Pos = 0x1e + // Bit mask of H_CHDIS6 field. + USB_HCCHAR6_H_CHDIS6_Msk = 0x40000000 + // Bit H_CHDIS6. + USB_HCCHAR6_H_CHDIS6 = 0x40000000 + // Position of H_CHENA6 field. + USB_HCCHAR6_H_CHENA6_Pos = 0x1f + // Bit mask of H_CHENA6 field. + USB_HCCHAR6_H_CHENA6_Msk = 0x80000000 + // Bit H_CHENA6. + USB_HCCHAR6_H_CHENA6 = 0x80000000 + + // HCINT6 + // Position of H_XFERCOMPL6 field. + USB_HCINT6_H_XFERCOMPL6_Pos = 0x0 + // Bit mask of H_XFERCOMPL6 field. + USB_HCINT6_H_XFERCOMPL6_Msk = 0x1 + // Bit H_XFERCOMPL6. + USB_HCINT6_H_XFERCOMPL6 = 0x1 + // Position of H_CHHLTD6 field. + USB_HCINT6_H_CHHLTD6_Pos = 0x1 + // Bit mask of H_CHHLTD6 field. + USB_HCINT6_H_CHHLTD6_Msk = 0x2 + // Bit H_CHHLTD6. + USB_HCINT6_H_CHHLTD6 = 0x2 + // Position of H_AHBERR6 field. + USB_HCINT6_H_AHBERR6_Pos = 0x2 + // Bit mask of H_AHBERR6 field. + USB_HCINT6_H_AHBERR6_Msk = 0x4 + // Bit H_AHBERR6. + USB_HCINT6_H_AHBERR6 = 0x4 + // Position of H_STALL6 field. + USB_HCINT6_H_STALL6_Pos = 0x3 + // Bit mask of H_STALL6 field. + USB_HCINT6_H_STALL6_Msk = 0x8 + // Bit H_STALL6. + USB_HCINT6_H_STALL6 = 0x8 + // Position of H_NACK6 field. + USB_HCINT6_H_NACK6_Pos = 0x4 + // Bit mask of H_NACK6 field. + USB_HCINT6_H_NACK6_Msk = 0x10 + // Bit H_NACK6. + USB_HCINT6_H_NACK6 = 0x10 + // Position of H_ACK6 field. + USB_HCINT6_H_ACK6_Pos = 0x5 + // Bit mask of H_ACK6 field. + USB_HCINT6_H_ACK6_Msk = 0x20 + // Bit H_ACK6. + USB_HCINT6_H_ACK6 = 0x20 + // Position of H_NYET6 field. + USB_HCINT6_H_NYET6_Pos = 0x6 + // Bit mask of H_NYET6 field. + USB_HCINT6_H_NYET6_Msk = 0x40 + // Bit H_NYET6. + USB_HCINT6_H_NYET6 = 0x40 + // Position of H_XACTERR6 field. + USB_HCINT6_H_XACTERR6_Pos = 0x7 + // Bit mask of H_XACTERR6 field. + USB_HCINT6_H_XACTERR6_Msk = 0x80 + // Bit H_XACTERR6. + USB_HCINT6_H_XACTERR6 = 0x80 + // Position of H_BBLERR6 field. + USB_HCINT6_H_BBLERR6_Pos = 0x8 + // Bit mask of H_BBLERR6 field. + USB_HCINT6_H_BBLERR6_Msk = 0x100 + // Bit H_BBLERR6. + USB_HCINT6_H_BBLERR6 = 0x100 + // Position of H_FRMOVRUN6 field. + USB_HCINT6_H_FRMOVRUN6_Pos = 0x9 + // Bit mask of H_FRMOVRUN6 field. + USB_HCINT6_H_FRMOVRUN6_Msk = 0x200 + // Bit H_FRMOVRUN6. + USB_HCINT6_H_FRMOVRUN6 = 0x200 + // Position of H_DATATGLERR6 field. + USB_HCINT6_H_DATATGLERR6_Pos = 0xa + // Bit mask of H_DATATGLERR6 field. + USB_HCINT6_H_DATATGLERR6_Msk = 0x400 + // Bit H_DATATGLERR6. + USB_HCINT6_H_DATATGLERR6 = 0x400 + // Position of H_BNAINTR6 field. + USB_HCINT6_H_BNAINTR6_Pos = 0xb + // Bit mask of H_BNAINTR6 field. + USB_HCINT6_H_BNAINTR6_Msk = 0x800 + // Bit H_BNAINTR6. + USB_HCINT6_H_BNAINTR6 = 0x800 + // Position of H_XCS_XACT_ERR6 field. + USB_HCINT6_H_XCS_XACT_ERR6_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR6 field. + USB_HCINT6_H_XCS_XACT_ERR6_Msk = 0x1000 + // Bit H_XCS_XACT_ERR6. + USB_HCINT6_H_XCS_XACT_ERR6 = 0x1000 + // Position of H_DESC_LST_ROLLINTR6 field. + USB_HCINT6_H_DESC_LST_ROLLINTR6_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR6 field. + USB_HCINT6_H_DESC_LST_ROLLINTR6_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR6. + USB_HCINT6_H_DESC_LST_ROLLINTR6 = 0x2000 + + // HCINTMSK6 + // Position of H_XFERCOMPLMSK6 field. + USB_HCINTMSK6_H_XFERCOMPLMSK6_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK6 field. + USB_HCINTMSK6_H_XFERCOMPLMSK6_Msk = 0x1 + // Bit H_XFERCOMPLMSK6. + USB_HCINTMSK6_H_XFERCOMPLMSK6 = 0x1 + // Position of H_CHHLTDMSK6 field. + USB_HCINTMSK6_H_CHHLTDMSK6_Pos = 0x1 + // Bit mask of H_CHHLTDMSK6 field. + USB_HCINTMSK6_H_CHHLTDMSK6_Msk = 0x2 + // Bit H_CHHLTDMSK6. + USB_HCINTMSK6_H_CHHLTDMSK6 = 0x2 + // Position of H_AHBERRMSK6 field. + USB_HCINTMSK6_H_AHBERRMSK6_Pos = 0x2 + // Bit mask of H_AHBERRMSK6 field. + USB_HCINTMSK6_H_AHBERRMSK6_Msk = 0x4 + // Bit H_AHBERRMSK6. + USB_HCINTMSK6_H_AHBERRMSK6 = 0x4 + // Position of H_STALLMSK6 field. + USB_HCINTMSK6_H_STALLMSK6_Pos = 0x3 + // Bit mask of H_STALLMSK6 field. + USB_HCINTMSK6_H_STALLMSK6_Msk = 0x8 + // Bit H_STALLMSK6. + USB_HCINTMSK6_H_STALLMSK6 = 0x8 + // Position of H_NAKMSK6 field. + USB_HCINTMSK6_H_NAKMSK6_Pos = 0x4 + // Bit mask of H_NAKMSK6 field. + USB_HCINTMSK6_H_NAKMSK6_Msk = 0x10 + // Bit H_NAKMSK6. + USB_HCINTMSK6_H_NAKMSK6 = 0x10 + // Position of H_ACKMSK6 field. + USB_HCINTMSK6_H_ACKMSK6_Pos = 0x5 + // Bit mask of H_ACKMSK6 field. + USB_HCINTMSK6_H_ACKMSK6_Msk = 0x20 + // Bit H_ACKMSK6. + USB_HCINTMSK6_H_ACKMSK6 = 0x20 + // Position of H_NYETMSK6 field. + USB_HCINTMSK6_H_NYETMSK6_Pos = 0x6 + // Bit mask of H_NYETMSK6 field. + USB_HCINTMSK6_H_NYETMSK6_Msk = 0x40 + // Bit H_NYETMSK6. + USB_HCINTMSK6_H_NYETMSK6 = 0x40 + // Position of H_XACTERRMSK6 field. + USB_HCINTMSK6_H_XACTERRMSK6_Pos = 0x7 + // Bit mask of H_XACTERRMSK6 field. + USB_HCINTMSK6_H_XACTERRMSK6_Msk = 0x80 + // Bit H_XACTERRMSK6. + USB_HCINTMSK6_H_XACTERRMSK6 = 0x80 + // Position of H_BBLERRMSK6 field. + USB_HCINTMSK6_H_BBLERRMSK6_Pos = 0x8 + // Bit mask of H_BBLERRMSK6 field. + USB_HCINTMSK6_H_BBLERRMSK6_Msk = 0x100 + // Bit H_BBLERRMSK6. + USB_HCINTMSK6_H_BBLERRMSK6 = 0x100 + // Position of H_FRMOVRUNMSK6 field. + USB_HCINTMSK6_H_FRMOVRUNMSK6_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK6 field. + USB_HCINTMSK6_H_FRMOVRUNMSK6_Msk = 0x200 + // Bit H_FRMOVRUNMSK6. + USB_HCINTMSK6_H_FRMOVRUNMSK6 = 0x200 + // Position of H_DATATGLERRMSK6 field. + USB_HCINTMSK6_H_DATATGLERRMSK6_Pos = 0xa + // Bit mask of H_DATATGLERRMSK6 field. + USB_HCINTMSK6_H_DATATGLERRMSK6_Msk = 0x400 + // Bit H_DATATGLERRMSK6. + USB_HCINTMSK6_H_DATATGLERRMSK6 = 0x400 + // Position of H_BNAINTRMSK6 field. + USB_HCINTMSK6_H_BNAINTRMSK6_Pos = 0xb + // Bit mask of H_BNAINTRMSK6 field. + USB_HCINTMSK6_H_BNAINTRMSK6_Msk = 0x800 + // Bit H_BNAINTRMSK6. + USB_HCINTMSK6_H_BNAINTRMSK6 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK6 field. + USB_HCINTMSK6_H_DESC_LST_ROLLINTRMSK6_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK6 field. + USB_HCINTMSK6_H_DESC_LST_ROLLINTRMSK6_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK6. + USB_HCINTMSK6_H_DESC_LST_ROLLINTRMSK6 = 0x2000 + + // HCTSIZ6 + // Position of H_XFERSIZE6 field. + USB_HCTSIZ6_H_XFERSIZE6_Pos = 0x0 + // Bit mask of H_XFERSIZE6 field. + USB_HCTSIZ6_H_XFERSIZE6_Msk = 0x7ffff + // Position of H_PKTCNT6 field. + USB_HCTSIZ6_H_PKTCNT6_Pos = 0x13 + // Bit mask of H_PKTCNT6 field. + USB_HCTSIZ6_H_PKTCNT6_Msk = 0x1ff80000 + // Position of H_PID6 field. + USB_HCTSIZ6_H_PID6_Pos = 0x1d + // Bit mask of H_PID6 field. + USB_HCTSIZ6_H_PID6_Msk = 0x60000000 + // Position of H_DOPNG6 field. + USB_HCTSIZ6_H_DOPNG6_Pos = 0x1f + // Bit mask of H_DOPNG6 field. + USB_HCTSIZ6_H_DOPNG6_Msk = 0x80000000 + // Bit H_DOPNG6. + USB_HCTSIZ6_H_DOPNG6 = 0x80000000 + + // HCDMA6 + // Position of H_DMAADDR6 field. + USB_HCDMA6_H_DMAADDR6_Pos = 0x0 + // Bit mask of H_DMAADDR6 field. + USB_HCDMA6_H_DMAADDR6_Msk = 0xffffffff + + // HCDMAB6 + // Position of H_HCDMAB6 field. + USB_HCDMAB6_H_HCDMAB6_Pos = 0x0 + // Bit mask of H_HCDMAB6 field. + USB_HCDMAB6_H_HCDMAB6_Msk = 0xffffffff + + // HCCHAR7 + // Position of H_MPS7 field. + USB_HCCHAR7_H_MPS7_Pos = 0x0 + // Bit mask of H_MPS7 field. + USB_HCCHAR7_H_MPS7_Msk = 0x7ff + // Position of H_EPNUM7 field. + USB_HCCHAR7_H_EPNUM7_Pos = 0xb + // Bit mask of H_EPNUM7 field. + USB_HCCHAR7_H_EPNUM7_Msk = 0x7800 + // Position of H_EPDIR7 field. + USB_HCCHAR7_H_EPDIR7_Pos = 0xf + // Bit mask of H_EPDIR7 field. + USB_HCCHAR7_H_EPDIR7_Msk = 0x8000 + // Bit H_EPDIR7. + USB_HCCHAR7_H_EPDIR7 = 0x8000 + // Position of H_LSPDDEV7 field. + USB_HCCHAR7_H_LSPDDEV7_Pos = 0x11 + // Bit mask of H_LSPDDEV7 field. + USB_HCCHAR7_H_LSPDDEV7_Msk = 0x20000 + // Bit H_LSPDDEV7. + USB_HCCHAR7_H_LSPDDEV7 = 0x20000 + // Position of H_EPTYPE7 field. + USB_HCCHAR7_H_EPTYPE7_Pos = 0x12 + // Bit mask of H_EPTYPE7 field. + USB_HCCHAR7_H_EPTYPE7_Msk = 0xc0000 + // Position of H_EC7 field. + USB_HCCHAR7_H_EC7_Pos = 0x15 + // Bit mask of H_EC7 field. + USB_HCCHAR7_H_EC7_Msk = 0x200000 + // Bit H_EC7. + USB_HCCHAR7_H_EC7 = 0x200000 + // Position of H_DEVADDR7 field. + USB_HCCHAR7_H_DEVADDR7_Pos = 0x16 + // Bit mask of H_DEVADDR7 field. + USB_HCCHAR7_H_DEVADDR7_Msk = 0x1fc00000 + // Position of H_ODDFRM7 field. + USB_HCCHAR7_H_ODDFRM7_Pos = 0x1d + // Bit mask of H_ODDFRM7 field. + USB_HCCHAR7_H_ODDFRM7_Msk = 0x20000000 + // Bit H_ODDFRM7. + USB_HCCHAR7_H_ODDFRM7 = 0x20000000 + // Position of H_CHDIS7 field. + USB_HCCHAR7_H_CHDIS7_Pos = 0x1e + // Bit mask of H_CHDIS7 field. + USB_HCCHAR7_H_CHDIS7_Msk = 0x40000000 + // Bit H_CHDIS7. + USB_HCCHAR7_H_CHDIS7 = 0x40000000 + // Position of H_CHENA7 field. + USB_HCCHAR7_H_CHENA7_Pos = 0x1f + // Bit mask of H_CHENA7 field. + USB_HCCHAR7_H_CHENA7_Msk = 0x80000000 + // Bit H_CHENA7. + USB_HCCHAR7_H_CHENA7 = 0x80000000 + + // HCINT7 + // Position of H_XFERCOMPL7 field. + USB_HCINT7_H_XFERCOMPL7_Pos = 0x0 + // Bit mask of H_XFERCOMPL7 field. + USB_HCINT7_H_XFERCOMPL7_Msk = 0x1 + // Bit H_XFERCOMPL7. + USB_HCINT7_H_XFERCOMPL7 = 0x1 + // Position of H_CHHLTD7 field. + USB_HCINT7_H_CHHLTD7_Pos = 0x1 + // Bit mask of H_CHHLTD7 field. + USB_HCINT7_H_CHHLTD7_Msk = 0x2 + // Bit H_CHHLTD7. + USB_HCINT7_H_CHHLTD7 = 0x2 + // Position of H_AHBERR7 field. + USB_HCINT7_H_AHBERR7_Pos = 0x2 + // Bit mask of H_AHBERR7 field. + USB_HCINT7_H_AHBERR7_Msk = 0x4 + // Bit H_AHBERR7. + USB_HCINT7_H_AHBERR7 = 0x4 + // Position of H_STALL7 field. + USB_HCINT7_H_STALL7_Pos = 0x3 + // Bit mask of H_STALL7 field. + USB_HCINT7_H_STALL7_Msk = 0x8 + // Bit H_STALL7. + USB_HCINT7_H_STALL7 = 0x8 + // Position of H_NACK7 field. + USB_HCINT7_H_NACK7_Pos = 0x4 + // Bit mask of H_NACK7 field. + USB_HCINT7_H_NACK7_Msk = 0x10 + // Bit H_NACK7. + USB_HCINT7_H_NACK7 = 0x10 + // Position of H_ACK7 field. + USB_HCINT7_H_ACK7_Pos = 0x5 + // Bit mask of H_ACK7 field. + USB_HCINT7_H_ACK7_Msk = 0x20 + // Bit H_ACK7. + USB_HCINT7_H_ACK7 = 0x20 + // Position of H_NYET7 field. + USB_HCINT7_H_NYET7_Pos = 0x6 + // Bit mask of H_NYET7 field. + USB_HCINT7_H_NYET7_Msk = 0x40 + // Bit H_NYET7. + USB_HCINT7_H_NYET7 = 0x40 + // Position of H_XACTERR7 field. + USB_HCINT7_H_XACTERR7_Pos = 0x7 + // Bit mask of H_XACTERR7 field. + USB_HCINT7_H_XACTERR7_Msk = 0x80 + // Bit H_XACTERR7. + USB_HCINT7_H_XACTERR7 = 0x80 + // Position of H_BBLERR7 field. + USB_HCINT7_H_BBLERR7_Pos = 0x8 + // Bit mask of H_BBLERR7 field. + USB_HCINT7_H_BBLERR7_Msk = 0x100 + // Bit H_BBLERR7. + USB_HCINT7_H_BBLERR7 = 0x100 + // Position of H_FRMOVRUN7 field. + USB_HCINT7_H_FRMOVRUN7_Pos = 0x9 + // Bit mask of H_FRMOVRUN7 field. + USB_HCINT7_H_FRMOVRUN7_Msk = 0x200 + // Bit H_FRMOVRUN7. + USB_HCINT7_H_FRMOVRUN7 = 0x200 + // Position of H_DATATGLERR7 field. + USB_HCINT7_H_DATATGLERR7_Pos = 0xa + // Bit mask of H_DATATGLERR7 field. + USB_HCINT7_H_DATATGLERR7_Msk = 0x400 + // Bit H_DATATGLERR7. + USB_HCINT7_H_DATATGLERR7 = 0x400 + // Position of H_BNAINTR7 field. + USB_HCINT7_H_BNAINTR7_Pos = 0xb + // Bit mask of H_BNAINTR7 field. + USB_HCINT7_H_BNAINTR7_Msk = 0x800 + // Bit H_BNAINTR7. + USB_HCINT7_H_BNAINTR7 = 0x800 + // Position of H_XCS_XACT_ERR7 field. + USB_HCINT7_H_XCS_XACT_ERR7_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR7 field. + USB_HCINT7_H_XCS_XACT_ERR7_Msk = 0x1000 + // Bit H_XCS_XACT_ERR7. + USB_HCINT7_H_XCS_XACT_ERR7 = 0x1000 + // Position of H_DESC_LST_ROLLINTR7 field. + USB_HCINT7_H_DESC_LST_ROLLINTR7_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR7 field. + USB_HCINT7_H_DESC_LST_ROLLINTR7_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR7. + USB_HCINT7_H_DESC_LST_ROLLINTR7 = 0x2000 + + // HCINTMSK7 + // Position of H_XFERCOMPLMSK7 field. + USB_HCINTMSK7_H_XFERCOMPLMSK7_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK7 field. + USB_HCINTMSK7_H_XFERCOMPLMSK7_Msk = 0x1 + // Bit H_XFERCOMPLMSK7. + USB_HCINTMSK7_H_XFERCOMPLMSK7 = 0x1 + // Position of H_CHHLTDMSK7 field. + USB_HCINTMSK7_H_CHHLTDMSK7_Pos = 0x1 + // Bit mask of H_CHHLTDMSK7 field. + USB_HCINTMSK7_H_CHHLTDMSK7_Msk = 0x2 + // Bit H_CHHLTDMSK7. + USB_HCINTMSK7_H_CHHLTDMSK7 = 0x2 + // Position of H_AHBERRMSK7 field. + USB_HCINTMSK7_H_AHBERRMSK7_Pos = 0x2 + // Bit mask of H_AHBERRMSK7 field. + USB_HCINTMSK7_H_AHBERRMSK7_Msk = 0x4 + // Bit H_AHBERRMSK7. + USB_HCINTMSK7_H_AHBERRMSK7 = 0x4 + // Position of H_STALLMSK7 field. + USB_HCINTMSK7_H_STALLMSK7_Pos = 0x3 + // Bit mask of H_STALLMSK7 field. + USB_HCINTMSK7_H_STALLMSK7_Msk = 0x8 + // Bit H_STALLMSK7. + USB_HCINTMSK7_H_STALLMSK7 = 0x8 + // Position of H_NAKMSK7 field. + USB_HCINTMSK7_H_NAKMSK7_Pos = 0x4 + // Bit mask of H_NAKMSK7 field. + USB_HCINTMSK7_H_NAKMSK7_Msk = 0x10 + // Bit H_NAKMSK7. + USB_HCINTMSK7_H_NAKMSK7 = 0x10 + // Position of H_ACKMSK7 field. + USB_HCINTMSK7_H_ACKMSK7_Pos = 0x5 + // Bit mask of H_ACKMSK7 field. + USB_HCINTMSK7_H_ACKMSK7_Msk = 0x20 + // Bit H_ACKMSK7. + USB_HCINTMSK7_H_ACKMSK7 = 0x20 + // Position of H_NYETMSK7 field. + USB_HCINTMSK7_H_NYETMSK7_Pos = 0x6 + // Bit mask of H_NYETMSK7 field. + USB_HCINTMSK7_H_NYETMSK7_Msk = 0x40 + // Bit H_NYETMSK7. + USB_HCINTMSK7_H_NYETMSK7 = 0x40 + // Position of H_XACTERRMSK7 field. + USB_HCINTMSK7_H_XACTERRMSK7_Pos = 0x7 + // Bit mask of H_XACTERRMSK7 field. + USB_HCINTMSK7_H_XACTERRMSK7_Msk = 0x80 + // Bit H_XACTERRMSK7. + USB_HCINTMSK7_H_XACTERRMSK7 = 0x80 + // Position of H_BBLERRMSK7 field. + USB_HCINTMSK7_H_BBLERRMSK7_Pos = 0x8 + // Bit mask of H_BBLERRMSK7 field. + USB_HCINTMSK7_H_BBLERRMSK7_Msk = 0x100 + // Bit H_BBLERRMSK7. + USB_HCINTMSK7_H_BBLERRMSK7 = 0x100 + // Position of H_FRMOVRUNMSK7 field. + USB_HCINTMSK7_H_FRMOVRUNMSK7_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK7 field. + USB_HCINTMSK7_H_FRMOVRUNMSK7_Msk = 0x200 + // Bit H_FRMOVRUNMSK7. + USB_HCINTMSK7_H_FRMOVRUNMSK7 = 0x200 + // Position of H_DATATGLERRMSK7 field. + USB_HCINTMSK7_H_DATATGLERRMSK7_Pos = 0xa + // Bit mask of H_DATATGLERRMSK7 field. + USB_HCINTMSK7_H_DATATGLERRMSK7_Msk = 0x400 + // Bit H_DATATGLERRMSK7. + USB_HCINTMSK7_H_DATATGLERRMSK7 = 0x400 + // Position of H_BNAINTRMSK7 field. + USB_HCINTMSK7_H_BNAINTRMSK7_Pos = 0xb + // Bit mask of H_BNAINTRMSK7 field. + USB_HCINTMSK7_H_BNAINTRMSK7_Msk = 0x800 + // Bit H_BNAINTRMSK7. + USB_HCINTMSK7_H_BNAINTRMSK7 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK7 field. + USB_HCINTMSK7_H_DESC_LST_ROLLINTRMSK7_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK7 field. + USB_HCINTMSK7_H_DESC_LST_ROLLINTRMSK7_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK7. + USB_HCINTMSK7_H_DESC_LST_ROLLINTRMSK7 = 0x2000 + + // HCTSIZ7 + // Position of H_XFERSIZE7 field. + USB_HCTSIZ7_H_XFERSIZE7_Pos = 0x0 + // Bit mask of H_XFERSIZE7 field. + USB_HCTSIZ7_H_XFERSIZE7_Msk = 0x7ffff + // Position of H_PKTCNT7 field. + USB_HCTSIZ7_H_PKTCNT7_Pos = 0x13 + // Bit mask of H_PKTCNT7 field. + USB_HCTSIZ7_H_PKTCNT7_Msk = 0x1ff80000 + // Position of H_PID7 field. + USB_HCTSIZ7_H_PID7_Pos = 0x1d + // Bit mask of H_PID7 field. + USB_HCTSIZ7_H_PID7_Msk = 0x60000000 + // Position of H_DOPNG7 field. + USB_HCTSIZ7_H_DOPNG7_Pos = 0x1f + // Bit mask of H_DOPNG7 field. + USB_HCTSIZ7_H_DOPNG7_Msk = 0x80000000 + // Bit H_DOPNG7. + USB_HCTSIZ7_H_DOPNG7 = 0x80000000 + + // HCDMA7 + // Position of H_DMAADDR7 field. + USB_HCDMA7_H_DMAADDR7_Pos = 0x0 + // Bit mask of H_DMAADDR7 field. + USB_HCDMA7_H_DMAADDR7_Msk = 0xffffffff + + // HCDMAB7 + // Position of H_HCDMAB7 field. + USB_HCDMAB7_H_HCDMAB7_Pos = 0x0 + // Bit mask of H_HCDMAB7 field. + USB_HCDMAB7_H_HCDMAB7_Msk = 0xffffffff + + // DCFG + // Position of NZSTSOUTHSHK field. + USB_DCFG_NZSTSOUTHSHK_Pos = 0x2 + // Bit mask of NZSTSOUTHSHK field. + USB_DCFG_NZSTSOUTHSHK_Msk = 0x4 + // Bit NZSTSOUTHSHK. + USB_DCFG_NZSTSOUTHSHK = 0x4 + // Position of ENA32KHZSUSP field. + USB_DCFG_ENA32KHZSUSP_Pos = 0x3 + // Bit mask of ENA32KHZSUSP field. + USB_DCFG_ENA32KHZSUSP_Msk = 0x8 + // Bit ENA32KHZSUSP. + USB_DCFG_ENA32KHZSUSP = 0x8 + // Position of DEVADDR field. + USB_DCFG_DEVADDR_Pos = 0x4 + // Bit mask of DEVADDR field. + USB_DCFG_DEVADDR_Msk = 0x7f0 + // Position of PERFRLINT field. + USB_DCFG_PERFRLINT_Pos = 0xb + // Bit mask of PERFRLINT field. + USB_DCFG_PERFRLINT_Msk = 0x1800 + // Position of ENDEVOUTNAK field. + USB_DCFG_ENDEVOUTNAK_Pos = 0xd + // Bit mask of ENDEVOUTNAK field. + USB_DCFG_ENDEVOUTNAK_Msk = 0x2000 + // Bit ENDEVOUTNAK. + USB_DCFG_ENDEVOUTNAK = 0x2000 + // Position of XCVRDLY field. + USB_DCFG_XCVRDLY_Pos = 0xe + // Bit mask of XCVRDLY field. + USB_DCFG_XCVRDLY_Msk = 0x4000 + // Bit XCVRDLY. + USB_DCFG_XCVRDLY = 0x4000 + // Position of ERRATICINTMSK field. + USB_DCFG_ERRATICINTMSK_Pos = 0xf + // Bit mask of ERRATICINTMSK field. + USB_DCFG_ERRATICINTMSK_Msk = 0x8000 + // Bit ERRATICINTMSK. + USB_DCFG_ERRATICINTMSK = 0x8000 + // Position of EPMISCNT field. + USB_DCFG_EPMISCNT_Pos = 0x12 + // Bit mask of EPMISCNT field. + USB_DCFG_EPMISCNT_Msk = 0x7c0000 + // Position of DESCDMA field. + USB_DCFG_DESCDMA_Pos = 0x17 + // Bit mask of DESCDMA field. + USB_DCFG_DESCDMA_Msk = 0x800000 + // Bit DESCDMA. + USB_DCFG_DESCDMA = 0x800000 + // Position of PERSCHINTVL field. + USB_DCFG_PERSCHINTVL_Pos = 0x18 + // Bit mask of PERSCHINTVL field. + USB_DCFG_PERSCHINTVL_Msk = 0x3000000 + // Position of RESVALID field. + USB_DCFG_RESVALID_Pos = 0x1a + // Bit mask of RESVALID field. + USB_DCFG_RESVALID_Msk = 0xfc000000 + + // DCTL + // Position of RMTWKUPSIG field. + USB_DCTL_RMTWKUPSIG_Pos = 0x0 + // Bit mask of RMTWKUPSIG field. + USB_DCTL_RMTWKUPSIG_Msk = 0x1 + // Bit RMTWKUPSIG. + USB_DCTL_RMTWKUPSIG = 0x1 + // Position of SFTDISCON field. + USB_DCTL_SFTDISCON_Pos = 0x1 + // Bit mask of SFTDISCON field. + USB_DCTL_SFTDISCON_Msk = 0x2 + // Bit SFTDISCON. + USB_DCTL_SFTDISCON = 0x2 + // Position of GNPINNAKSTS field. + USB_DCTL_GNPINNAKSTS_Pos = 0x2 + // Bit mask of GNPINNAKSTS field. + USB_DCTL_GNPINNAKSTS_Msk = 0x4 + // Bit GNPINNAKSTS. + USB_DCTL_GNPINNAKSTS = 0x4 + // Position of GOUTNAKSTS field. + USB_DCTL_GOUTNAKSTS_Pos = 0x3 + // Bit mask of GOUTNAKSTS field. + USB_DCTL_GOUTNAKSTS_Msk = 0x8 + // Bit GOUTNAKSTS. + USB_DCTL_GOUTNAKSTS = 0x8 + // Position of TSTCTL field. + USB_DCTL_TSTCTL_Pos = 0x4 + // Bit mask of TSTCTL field. + USB_DCTL_TSTCTL_Msk = 0x70 + // Position of SGNPINNAK field. + USB_DCTL_SGNPINNAK_Pos = 0x7 + // Bit mask of SGNPINNAK field. + USB_DCTL_SGNPINNAK_Msk = 0x80 + // Bit SGNPINNAK. + USB_DCTL_SGNPINNAK = 0x80 + // Position of CGNPINNAK field. + USB_DCTL_CGNPINNAK_Pos = 0x8 + // Bit mask of CGNPINNAK field. + USB_DCTL_CGNPINNAK_Msk = 0x100 + // Bit CGNPINNAK. + USB_DCTL_CGNPINNAK = 0x100 + // Position of SGOUTNAK field. + USB_DCTL_SGOUTNAK_Pos = 0x9 + // Bit mask of SGOUTNAK field. + USB_DCTL_SGOUTNAK_Msk = 0x200 + // Bit SGOUTNAK. + USB_DCTL_SGOUTNAK = 0x200 + // Position of CGOUTNAK field. + USB_DCTL_CGOUTNAK_Pos = 0xa + // Bit mask of CGOUTNAK field. + USB_DCTL_CGOUTNAK_Msk = 0x400 + // Bit CGOUTNAK. + USB_DCTL_CGOUTNAK = 0x400 + // Position of PWRONPRGDONE field. + USB_DCTL_PWRONPRGDONE_Pos = 0xb + // Bit mask of PWRONPRGDONE field. + USB_DCTL_PWRONPRGDONE_Msk = 0x800 + // Bit PWRONPRGDONE. + USB_DCTL_PWRONPRGDONE = 0x800 + // Position of GMC field. + USB_DCTL_GMC_Pos = 0xd + // Bit mask of GMC field. + USB_DCTL_GMC_Msk = 0x6000 + // Position of IGNRFRMNUM field. + USB_DCTL_IGNRFRMNUM_Pos = 0xf + // Bit mask of IGNRFRMNUM field. + USB_DCTL_IGNRFRMNUM_Msk = 0x8000 + // Bit IGNRFRMNUM. + USB_DCTL_IGNRFRMNUM = 0x8000 + // Position of NAKONBBLE field. + USB_DCTL_NAKONBBLE_Pos = 0x10 + // Bit mask of NAKONBBLE field. + USB_DCTL_NAKONBBLE_Msk = 0x10000 + // Bit NAKONBBLE. + USB_DCTL_NAKONBBLE = 0x10000 + // Position of ENCOUNTONBNA field. + USB_DCTL_ENCOUNTONBNA_Pos = 0x11 + // Bit mask of ENCOUNTONBNA field. + USB_DCTL_ENCOUNTONBNA_Msk = 0x20000 + // Bit ENCOUNTONBNA. + USB_DCTL_ENCOUNTONBNA = 0x20000 + // Position of DEEPSLEEPBESLREJECT field. + USB_DCTL_DEEPSLEEPBESLREJECT_Pos = 0x12 + // Bit mask of DEEPSLEEPBESLREJECT field. + USB_DCTL_DEEPSLEEPBESLREJECT_Msk = 0x40000 + // Bit DEEPSLEEPBESLREJECT. + USB_DCTL_DEEPSLEEPBESLREJECT = 0x40000 + + // DSTS + // Position of SUSPSTS field. + USB_DSTS_SUSPSTS_Pos = 0x0 + // Bit mask of SUSPSTS field. + USB_DSTS_SUSPSTS_Msk = 0x1 + // Bit SUSPSTS. + USB_DSTS_SUSPSTS = 0x1 + // Position of ENUMSPD field. + USB_DSTS_ENUMSPD_Pos = 0x1 + // Bit mask of ENUMSPD field. + USB_DSTS_ENUMSPD_Msk = 0x6 + // Position of ERRTICERR field. + USB_DSTS_ERRTICERR_Pos = 0x3 + // Bit mask of ERRTICERR field. + USB_DSTS_ERRTICERR_Msk = 0x8 + // Bit ERRTICERR. + USB_DSTS_ERRTICERR = 0x8 + // Position of SOFFN field. + USB_DSTS_SOFFN_Pos = 0x8 + // Bit mask of SOFFN field. + USB_DSTS_SOFFN_Msk = 0x3fff00 + // Position of DEVLNSTS field. + USB_DSTS_DEVLNSTS_Pos = 0x16 + // Bit mask of DEVLNSTS field. + USB_DSTS_DEVLNSTS_Msk = 0xc00000 + + // DIEPMSK + // Position of DI_XFERCOMPLMSK field. + USB_DIEPMSK_DI_XFERCOMPLMSK_Pos = 0x0 + // Bit mask of DI_XFERCOMPLMSK field. + USB_DIEPMSK_DI_XFERCOMPLMSK_Msk = 0x1 + // Bit DI_XFERCOMPLMSK. + USB_DIEPMSK_DI_XFERCOMPLMSK = 0x1 + // Position of DI_EPDISBLDMSK field. + USB_DIEPMSK_DI_EPDISBLDMSK_Pos = 0x1 + // Bit mask of DI_EPDISBLDMSK field. + USB_DIEPMSK_DI_EPDISBLDMSK_Msk = 0x2 + // Bit DI_EPDISBLDMSK. + USB_DIEPMSK_DI_EPDISBLDMSK = 0x2 + // Position of DI_AHBERMSK field. + USB_DIEPMSK_DI_AHBERMSK_Pos = 0x2 + // Bit mask of DI_AHBERMSK field. + USB_DIEPMSK_DI_AHBERMSK_Msk = 0x4 + // Bit DI_AHBERMSK. + USB_DIEPMSK_DI_AHBERMSK = 0x4 + // Position of TIMEOUTMSK field. + USB_DIEPMSK_TIMEOUTMSK_Pos = 0x3 + // Bit mask of TIMEOUTMSK field. + USB_DIEPMSK_TIMEOUTMSK_Msk = 0x8 + // Bit TIMEOUTMSK. + USB_DIEPMSK_TIMEOUTMSK = 0x8 + // Position of INTKNTXFEMPMSK field. + USB_DIEPMSK_INTKNTXFEMPMSK_Pos = 0x4 + // Bit mask of INTKNTXFEMPMSK field. + USB_DIEPMSK_INTKNTXFEMPMSK_Msk = 0x10 + // Bit INTKNTXFEMPMSK. + USB_DIEPMSK_INTKNTXFEMPMSK = 0x10 + // Position of INTKNEPMISMSK field. + USB_DIEPMSK_INTKNEPMISMSK_Pos = 0x5 + // Bit mask of INTKNEPMISMSK field. + USB_DIEPMSK_INTKNEPMISMSK_Msk = 0x20 + // Bit INTKNEPMISMSK. + USB_DIEPMSK_INTKNEPMISMSK = 0x20 + // Position of INEPNAKEFFMSK field. + USB_DIEPMSK_INEPNAKEFFMSK_Pos = 0x6 + // Bit mask of INEPNAKEFFMSK field. + USB_DIEPMSK_INEPNAKEFFMSK_Msk = 0x40 + // Bit INEPNAKEFFMSK. + USB_DIEPMSK_INEPNAKEFFMSK = 0x40 + // Position of TXFIFOUNDRNMSK field. + USB_DIEPMSK_TXFIFOUNDRNMSK_Pos = 0x8 + // Bit mask of TXFIFOUNDRNMSK field. + USB_DIEPMSK_TXFIFOUNDRNMSK_Msk = 0x100 + // Bit TXFIFOUNDRNMSK. + USB_DIEPMSK_TXFIFOUNDRNMSK = 0x100 + // Position of BNAININTRMSK field. + USB_DIEPMSK_BNAININTRMSK_Pos = 0x9 + // Bit mask of BNAININTRMSK field. + USB_DIEPMSK_BNAININTRMSK_Msk = 0x200 + // Bit BNAININTRMSK. + USB_DIEPMSK_BNAININTRMSK = 0x200 + // Position of DI_NAKMSK field. + USB_DIEPMSK_DI_NAKMSK_Pos = 0xd + // Bit mask of DI_NAKMSK field. + USB_DIEPMSK_DI_NAKMSK_Msk = 0x2000 + // Bit DI_NAKMSK. + USB_DIEPMSK_DI_NAKMSK = 0x2000 + + // DOEPMSK + // Position of XFERCOMPLMSK field. + USB_DOEPMSK_XFERCOMPLMSK_Pos = 0x0 + // Bit mask of XFERCOMPLMSK field. + USB_DOEPMSK_XFERCOMPLMSK_Msk = 0x1 + // Bit XFERCOMPLMSK. + USB_DOEPMSK_XFERCOMPLMSK = 0x1 + // Position of EPDISBLDMSK field. + USB_DOEPMSK_EPDISBLDMSK_Pos = 0x1 + // Bit mask of EPDISBLDMSK field. + USB_DOEPMSK_EPDISBLDMSK_Msk = 0x2 + // Bit EPDISBLDMSK. + USB_DOEPMSK_EPDISBLDMSK = 0x2 + // Position of AHBERMSK field. + USB_DOEPMSK_AHBERMSK_Pos = 0x2 + // Bit mask of AHBERMSK field. + USB_DOEPMSK_AHBERMSK_Msk = 0x4 + // Bit AHBERMSK. + USB_DOEPMSK_AHBERMSK = 0x4 + // Position of SETUPMSK field. + USB_DOEPMSK_SETUPMSK_Pos = 0x3 + // Bit mask of SETUPMSK field. + USB_DOEPMSK_SETUPMSK_Msk = 0x8 + // Bit SETUPMSK. + USB_DOEPMSK_SETUPMSK = 0x8 + // Position of OUTTKNEPDISMSK field. + USB_DOEPMSK_OUTTKNEPDISMSK_Pos = 0x4 + // Bit mask of OUTTKNEPDISMSK field. + USB_DOEPMSK_OUTTKNEPDISMSK_Msk = 0x10 + // Bit OUTTKNEPDISMSK. + USB_DOEPMSK_OUTTKNEPDISMSK = 0x10 + // Position of STSPHSERCVDMSK field. + USB_DOEPMSK_STSPHSERCVDMSK_Pos = 0x5 + // Bit mask of STSPHSERCVDMSK field. + USB_DOEPMSK_STSPHSERCVDMSK_Msk = 0x20 + // Bit STSPHSERCVDMSK. + USB_DOEPMSK_STSPHSERCVDMSK = 0x20 + // Position of BACK2BACKSETUP field. + USB_DOEPMSK_BACK2BACKSETUP_Pos = 0x6 + // Bit mask of BACK2BACKSETUP field. + USB_DOEPMSK_BACK2BACKSETUP_Msk = 0x40 + // Bit BACK2BACKSETUP. + USB_DOEPMSK_BACK2BACKSETUP = 0x40 + // Position of OUTPKTERRMSK field. + USB_DOEPMSK_OUTPKTERRMSK_Pos = 0x8 + // Bit mask of OUTPKTERRMSK field. + USB_DOEPMSK_OUTPKTERRMSK_Msk = 0x100 + // Bit OUTPKTERRMSK. + USB_DOEPMSK_OUTPKTERRMSK = 0x100 + // Position of BNAOUTINTRMSK field. + USB_DOEPMSK_BNAOUTINTRMSK_Pos = 0x9 + // Bit mask of BNAOUTINTRMSK field. + USB_DOEPMSK_BNAOUTINTRMSK_Msk = 0x200 + // Bit BNAOUTINTRMSK. + USB_DOEPMSK_BNAOUTINTRMSK = 0x200 + // Position of BBLEERRMSK field. + USB_DOEPMSK_BBLEERRMSK_Pos = 0xc + // Bit mask of BBLEERRMSK field. + USB_DOEPMSK_BBLEERRMSK_Msk = 0x1000 + // Bit BBLEERRMSK. + USB_DOEPMSK_BBLEERRMSK = 0x1000 + // Position of NAKMSK field. + USB_DOEPMSK_NAKMSK_Pos = 0xd + // Bit mask of NAKMSK field. + USB_DOEPMSK_NAKMSK_Msk = 0x2000 + // Bit NAKMSK. + USB_DOEPMSK_NAKMSK = 0x2000 + // Position of NYETMSK field. + USB_DOEPMSK_NYETMSK_Pos = 0xe + // Bit mask of NYETMSK field. + USB_DOEPMSK_NYETMSK_Msk = 0x4000 + // Bit NYETMSK. + USB_DOEPMSK_NYETMSK = 0x4000 + + // DAINT + // Position of INEPINT0 field. + USB_DAINT_INEPINT0_Pos = 0x0 + // Bit mask of INEPINT0 field. + USB_DAINT_INEPINT0_Msk = 0x1 + // Bit INEPINT0. + USB_DAINT_INEPINT0 = 0x1 + // Position of INEPINT1 field. + USB_DAINT_INEPINT1_Pos = 0x1 + // Bit mask of INEPINT1 field. + USB_DAINT_INEPINT1_Msk = 0x2 + // Bit INEPINT1. + USB_DAINT_INEPINT1 = 0x2 + // Position of INEPINT2 field. + USB_DAINT_INEPINT2_Pos = 0x2 + // Bit mask of INEPINT2 field. + USB_DAINT_INEPINT2_Msk = 0x4 + // Bit INEPINT2. + USB_DAINT_INEPINT2 = 0x4 + // Position of INEPINT3 field. + USB_DAINT_INEPINT3_Pos = 0x3 + // Bit mask of INEPINT3 field. + USB_DAINT_INEPINT3_Msk = 0x8 + // Bit INEPINT3. + USB_DAINT_INEPINT3 = 0x8 + // Position of INEPINT4 field. + USB_DAINT_INEPINT4_Pos = 0x4 + // Bit mask of INEPINT4 field. + USB_DAINT_INEPINT4_Msk = 0x10 + // Bit INEPINT4. + USB_DAINT_INEPINT4 = 0x10 + // Position of INEPINT5 field. + USB_DAINT_INEPINT5_Pos = 0x5 + // Bit mask of INEPINT5 field. + USB_DAINT_INEPINT5_Msk = 0x20 + // Bit INEPINT5. + USB_DAINT_INEPINT5 = 0x20 + // Position of INEPINT6 field. + USB_DAINT_INEPINT6_Pos = 0x6 + // Bit mask of INEPINT6 field. + USB_DAINT_INEPINT6_Msk = 0x40 + // Bit INEPINT6. + USB_DAINT_INEPINT6 = 0x40 + // Position of OUTEPINT0 field. + USB_DAINT_OUTEPINT0_Pos = 0x10 + // Bit mask of OUTEPINT0 field. + USB_DAINT_OUTEPINT0_Msk = 0x10000 + // Bit OUTEPINT0. + USB_DAINT_OUTEPINT0 = 0x10000 + // Position of OUTEPINT1 field. + USB_DAINT_OUTEPINT1_Pos = 0x11 + // Bit mask of OUTEPINT1 field. + USB_DAINT_OUTEPINT1_Msk = 0x20000 + // Bit OUTEPINT1. + USB_DAINT_OUTEPINT1 = 0x20000 + // Position of OUTEPINT2 field. + USB_DAINT_OUTEPINT2_Pos = 0x12 + // Bit mask of OUTEPINT2 field. + USB_DAINT_OUTEPINT2_Msk = 0x40000 + // Bit OUTEPINT2. + USB_DAINT_OUTEPINT2 = 0x40000 + // Position of OUTEPINT3 field. + USB_DAINT_OUTEPINT3_Pos = 0x13 + // Bit mask of OUTEPINT3 field. + USB_DAINT_OUTEPINT3_Msk = 0x80000 + // Bit OUTEPINT3. + USB_DAINT_OUTEPINT3 = 0x80000 + // Position of OUTEPINT4 field. + USB_DAINT_OUTEPINT4_Pos = 0x14 + // Bit mask of OUTEPINT4 field. + USB_DAINT_OUTEPINT4_Msk = 0x100000 + // Bit OUTEPINT4. + USB_DAINT_OUTEPINT4 = 0x100000 + // Position of OUTEPINT5 field. + USB_DAINT_OUTEPINT5_Pos = 0x15 + // Bit mask of OUTEPINT5 field. + USB_DAINT_OUTEPINT5_Msk = 0x200000 + // Bit OUTEPINT5. + USB_DAINT_OUTEPINT5 = 0x200000 + // Position of OUTEPINT6 field. + USB_DAINT_OUTEPINT6_Pos = 0x16 + // Bit mask of OUTEPINT6 field. + USB_DAINT_OUTEPINT6_Msk = 0x400000 + // Bit OUTEPINT6. + USB_DAINT_OUTEPINT6 = 0x400000 + + // DAINTMSK + // Position of INEPMSK0 field. + USB_DAINTMSK_INEPMSK0_Pos = 0x0 + // Bit mask of INEPMSK0 field. + USB_DAINTMSK_INEPMSK0_Msk = 0x1 + // Bit INEPMSK0. + USB_DAINTMSK_INEPMSK0 = 0x1 + // Position of INEPMSK1 field. + USB_DAINTMSK_INEPMSK1_Pos = 0x1 + // Bit mask of INEPMSK1 field. + USB_DAINTMSK_INEPMSK1_Msk = 0x2 + // Bit INEPMSK1. + USB_DAINTMSK_INEPMSK1 = 0x2 + // Position of INEPMSK2 field. + USB_DAINTMSK_INEPMSK2_Pos = 0x2 + // Bit mask of INEPMSK2 field. + USB_DAINTMSK_INEPMSK2_Msk = 0x4 + // Bit INEPMSK2. + USB_DAINTMSK_INEPMSK2 = 0x4 + // Position of INEPMSK3 field. + USB_DAINTMSK_INEPMSK3_Pos = 0x3 + // Bit mask of INEPMSK3 field. + USB_DAINTMSK_INEPMSK3_Msk = 0x8 + // Bit INEPMSK3. + USB_DAINTMSK_INEPMSK3 = 0x8 + // Position of INEPMSK4 field. + USB_DAINTMSK_INEPMSK4_Pos = 0x4 + // Bit mask of INEPMSK4 field. + USB_DAINTMSK_INEPMSK4_Msk = 0x10 + // Bit INEPMSK4. + USB_DAINTMSK_INEPMSK4 = 0x10 + // Position of INEPMSK5 field. + USB_DAINTMSK_INEPMSK5_Pos = 0x5 + // Bit mask of INEPMSK5 field. + USB_DAINTMSK_INEPMSK5_Msk = 0x20 + // Bit INEPMSK5. + USB_DAINTMSK_INEPMSK5 = 0x20 + // Position of INEPMSK6 field. + USB_DAINTMSK_INEPMSK6_Pos = 0x6 + // Bit mask of INEPMSK6 field. + USB_DAINTMSK_INEPMSK6_Msk = 0x40 + // Bit INEPMSK6. + USB_DAINTMSK_INEPMSK6 = 0x40 + // Position of OUTEPMSK0 field. + USB_DAINTMSK_OUTEPMSK0_Pos = 0x10 + // Bit mask of OUTEPMSK0 field. + USB_DAINTMSK_OUTEPMSK0_Msk = 0x10000 + // Bit OUTEPMSK0. + USB_DAINTMSK_OUTEPMSK0 = 0x10000 + // Position of OUTEPMSK1 field. + USB_DAINTMSK_OUTEPMSK1_Pos = 0x11 + // Bit mask of OUTEPMSK1 field. + USB_DAINTMSK_OUTEPMSK1_Msk = 0x20000 + // Bit OUTEPMSK1. + USB_DAINTMSK_OUTEPMSK1 = 0x20000 + // Position of OUTEPMSK2 field. + USB_DAINTMSK_OUTEPMSK2_Pos = 0x12 + // Bit mask of OUTEPMSK2 field. + USB_DAINTMSK_OUTEPMSK2_Msk = 0x40000 + // Bit OUTEPMSK2. + USB_DAINTMSK_OUTEPMSK2 = 0x40000 + // Position of OUTEPMSK3 field. + USB_DAINTMSK_OUTEPMSK3_Pos = 0x13 + // Bit mask of OUTEPMSK3 field. + USB_DAINTMSK_OUTEPMSK3_Msk = 0x80000 + // Bit OUTEPMSK3. + USB_DAINTMSK_OUTEPMSK3 = 0x80000 + // Position of OUTEPMSK4 field. + USB_DAINTMSK_OUTEPMSK4_Pos = 0x14 + // Bit mask of OUTEPMSK4 field. + USB_DAINTMSK_OUTEPMSK4_Msk = 0x100000 + // Bit OUTEPMSK4. + USB_DAINTMSK_OUTEPMSK4 = 0x100000 + // Position of OUTEPMSK5 field. + USB_DAINTMSK_OUTEPMSK5_Pos = 0x15 + // Bit mask of OUTEPMSK5 field. + USB_DAINTMSK_OUTEPMSK5_Msk = 0x200000 + // Bit OUTEPMSK5. + USB_DAINTMSK_OUTEPMSK5 = 0x200000 + // Position of OUTEPMSK6 field. + USB_DAINTMSK_OUTEPMSK6_Pos = 0x16 + // Bit mask of OUTEPMSK6 field. + USB_DAINTMSK_OUTEPMSK6_Msk = 0x400000 + // Bit OUTEPMSK6. + USB_DAINTMSK_OUTEPMSK6 = 0x400000 + + // DVBUSDIS + // Position of DVBUSDIS field. + USB_DVBUSDIS_DVBUSDIS_Pos = 0x0 + // Bit mask of DVBUSDIS field. + USB_DVBUSDIS_DVBUSDIS_Msk = 0xffff + + // DVBUSPULSE + // Position of DVBUSPULSE field. + USB_DVBUSPULSE_DVBUSPULSE_Pos = 0x0 + // Bit mask of DVBUSPULSE field. + USB_DVBUSPULSE_DVBUSPULSE_Msk = 0xfff + + // DTHRCTL + // Position of NONISOTHREN field. + USB_DTHRCTL_NONISOTHREN_Pos = 0x0 + // Bit mask of NONISOTHREN field. + USB_DTHRCTL_NONISOTHREN_Msk = 0x1 + // Bit NONISOTHREN. + USB_DTHRCTL_NONISOTHREN = 0x1 + // Position of ISOTHREN field. + USB_DTHRCTL_ISOTHREN_Pos = 0x1 + // Bit mask of ISOTHREN field. + USB_DTHRCTL_ISOTHREN_Msk = 0x2 + // Bit ISOTHREN. + USB_DTHRCTL_ISOTHREN = 0x2 + // Position of TXTHRLEN field. + USB_DTHRCTL_TXTHRLEN_Pos = 0x2 + // Bit mask of TXTHRLEN field. + USB_DTHRCTL_TXTHRLEN_Msk = 0x7fc + // Position of AHBTHRRATIO field. + USB_DTHRCTL_AHBTHRRATIO_Pos = 0xb + // Bit mask of AHBTHRRATIO field. + USB_DTHRCTL_AHBTHRRATIO_Msk = 0x1800 + // Position of RXTHREN field. + USB_DTHRCTL_RXTHREN_Pos = 0x10 + // Bit mask of RXTHREN field. + USB_DTHRCTL_RXTHREN_Msk = 0x10000 + // Bit RXTHREN. + USB_DTHRCTL_RXTHREN = 0x10000 + // Position of RXTHRLEN field. + USB_DTHRCTL_RXTHRLEN_Pos = 0x11 + // Bit mask of RXTHRLEN field. + USB_DTHRCTL_RXTHRLEN_Msk = 0x3fe0000 + // Position of ARBPRKEN field. + USB_DTHRCTL_ARBPRKEN_Pos = 0x1b + // Bit mask of ARBPRKEN field. + USB_DTHRCTL_ARBPRKEN_Msk = 0x8000000 + // Bit ARBPRKEN. + USB_DTHRCTL_ARBPRKEN = 0x8000000 + + // DIEPEMPMSK + // Position of D_INEPTXFEMPMSK field. + USB_DIEPEMPMSK_D_INEPTXFEMPMSK_Pos = 0x0 + // Bit mask of D_INEPTXFEMPMSK field. + USB_DIEPEMPMSK_D_INEPTXFEMPMSK_Msk = 0xffff + + // DIEPCTL0 + // Position of D_MPS0 field. + USB_DIEPCTL0_D_MPS0_Pos = 0x0 + // Bit mask of D_MPS0 field. + USB_DIEPCTL0_D_MPS0_Msk = 0x3 + // Position of D_USBACTEP0 field. + USB_DIEPCTL0_D_USBACTEP0_Pos = 0xf + // Bit mask of D_USBACTEP0 field. + USB_DIEPCTL0_D_USBACTEP0_Msk = 0x8000 + // Bit D_USBACTEP0. + USB_DIEPCTL0_D_USBACTEP0 = 0x8000 + // Position of D_NAKSTS0 field. + USB_DIEPCTL0_D_NAKSTS0_Pos = 0x11 + // Bit mask of D_NAKSTS0 field. + USB_DIEPCTL0_D_NAKSTS0_Msk = 0x20000 + // Bit D_NAKSTS0. + USB_DIEPCTL0_D_NAKSTS0 = 0x20000 + // Position of D_EPTYPE0 field. + USB_DIEPCTL0_D_EPTYPE0_Pos = 0x12 + // Bit mask of D_EPTYPE0 field. + USB_DIEPCTL0_D_EPTYPE0_Msk = 0xc0000 + // Position of D_STALL0 field. + USB_DIEPCTL0_D_STALL0_Pos = 0x15 + // Bit mask of D_STALL0 field. + USB_DIEPCTL0_D_STALL0_Msk = 0x200000 + // Bit D_STALL0. + USB_DIEPCTL0_D_STALL0 = 0x200000 + // Position of D_TXFNUM0 field. + USB_DIEPCTL0_D_TXFNUM0_Pos = 0x16 + // Bit mask of D_TXFNUM0 field. + USB_DIEPCTL0_D_TXFNUM0_Msk = 0x3c00000 + // Position of D_CNAK0 field. + USB_DIEPCTL0_D_CNAK0_Pos = 0x1a + // Bit mask of D_CNAK0 field. + USB_DIEPCTL0_D_CNAK0_Msk = 0x4000000 + // Bit D_CNAK0. + USB_DIEPCTL0_D_CNAK0 = 0x4000000 + // Position of DI_SNAK0 field. + USB_DIEPCTL0_DI_SNAK0_Pos = 0x1b + // Bit mask of DI_SNAK0 field. + USB_DIEPCTL0_DI_SNAK0_Msk = 0x8000000 + // Bit DI_SNAK0. + USB_DIEPCTL0_DI_SNAK0 = 0x8000000 + // Position of D_EPDIS0 field. + USB_DIEPCTL0_D_EPDIS0_Pos = 0x1e + // Bit mask of D_EPDIS0 field. + USB_DIEPCTL0_D_EPDIS0_Msk = 0x40000000 + // Bit D_EPDIS0. + USB_DIEPCTL0_D_EPDIS0 = 0x40000000 + // Position of D_EPENA0 field. + USB_DIEPCTL0_D_EPENA0_Pos = 0x1f + // Bit mask of D_EPENA0 field. + USB_DIEPCTL0_D_EPENA0_Msk = 0x80000000 + // Bit D_EPENA0. + USB_DIEPCTL0_D_EPENA0 = 0x80000000 + + // DIEPINT0 + // Position of D_XFERCOMPL0 field. + USB_DIEPINT0_D_XFERCOMPL0_Pos = 0x0 + // Bit mask of D_XFERCOMPL0 field. + USB_DIEPINT0_D_XFERCOMPL0_Msk = 0x1 + // Bit D_XFERCOMPL0. + USB_DIEPINT0_D_XFERCOMPL0 = 0x1 + // Position of D_EPDISBLD0 field. + USB_DIEPINT0_D_EPDISBLD0_Pos = 0x1 + // Bit mask of D_EPDISBLD0 field. + USB_DIEPINT0_D_EPDISBLD0_Msk = 0x2 + // Bit D_EPDISBLD0. + USB_DIEPINT0_D_EPDISBLD0 = 0x2 + // Position of D_AHBERR0 field. + USB_DIEPINT0_D_AHBERR0_Pos = 0x2 + // Bit mask of D_AHBERR0 field. + USB_DIEPINT0_D_AHBERR0_Msk = 0x4 + // Bit D_AHBERR0. + USB_DIEPINT0_D_AHBERR0 = 0x4 + // Position of D_TIMEOUT0 field. + USB_DIEPINT0_D_TIMEOUT0_Pos = 0x3 + // Bit mask of D_TIMEOUT0 field. + USB_DIEPINT0_D_TIMEOUT0_Msk = 0x8 + // Bit D_TIMEOUT0. + USB_DIEPINT0_D_TIMEOUT0 = 0x8 + // Position of D_INTKNTXFEMP0 field. + USB_DIEPINT0_D_INTKNTXFEMP0_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP0 field. + USB_DIEPINT0_D_INTKNTXFEMP0_Msk = 0x10 + // Bit D_INTKNTXFEMP0. + USB_DIEPINT0_D_INTKNTXFEMP0 = 0x10 + // Position of D_INTKNEPMIS0 field. + USB_DIEPINT0_D_INTKNEPMIS0_Pos = 0x5 + // Bit mask of D_INTKNEPMIS0 field. + USB_DIEPINT0_D_INTKNEPMIS0_Msk = 0x20 + // Bit D_INTKNEPMIS0. + USB_DIEPINT0_D_INTKNEPMIS0 = 0x20 + // Position of D_INEPNAKEFF0 field. + USB_DIEPINT0_D_INEPNAKEFF0_Pos = 0x6 + // Bit mask of D_INEPNAKEFF0 field. + USB_DIEPINT0_D_INEPNAKEFF0_Msk = 0x40 + // Bit D_INEPNAKEFF0. + USB_DIEPINT0_D_INEPNAKEFF0 = 0x40 + // Position of D_TXFEMP0 field. + USB_DIEPINT0_D_TXFEMP0_Pos = 0x7 + // Bit mask of D_TXFEMP0 field. + USB_DIEPINT0_D_TXFEMP0_Msk = 0x80 + // Bit D_TXFEMP0. + USB_DIEPINT0_D_TXFEMP0 = 0x80 + // Position of D_TXFIFOUNDRN0 field. + USB_DIEPINT0_D_TXFIFOUNDRN0_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN0 field. + USB_DIEPINT0_D_TXFIFOUNDRN0_Msk = 0x100 + // Bit D_TXFIFOUNDRN0. + USB_DIEPINT0_D_TXFIFOUNDRN0 = 0x100 + // Position of D_BNAINTR0 field. + USB_DIEPINT0_D_BNAINTR0_Pos = 0x9 + // Bit mask of D_BNAINTR0 field. + USB_DIEPINT0_D_BNAINTR0_Msk = 0x200 + // Bit D_BNAINTR0. + USB_DIEPINT0_D_BNAINTR0 = 0x200 + // Position of D_PKTDRPSTS0 field. + USB_DIEPINT0_D_PKTDRPSTS0_Pos = 0xb + // Bit mask of D_PKTDRPSTS0 field. + USB_DIEPINT0_D_PKTDRPSTS0_Msk = 0x800 + // Bit D_PKTDRPSTS0. + USB_DIEPINT0_D_PKTDRPSTS0 = 0x800 + // Position of D_BBLEERR0 field. + USB_DIEPINT0_D_BBLEERR0_Pos = 0xc + // Bit mask of D_BBLEERR0 field. + USB_DIEPINT0_D_BBLEERR0_Msk = 0x1000 + // Bit D_BBLEERR0. + USB_DIEPINT0_D_BBLEERR0 = 0x1000 + // Position of D_NAKINTRPT0 field. + USB_DIEPINT0_D_NAKINTRPT0_Pos = 0xd + // Bit mask of D_NAKINTRPT0 field. + USB_DIEPINT0_D_NAKINTRPT0_Msk = 0x2000 + // Bit D_NAKINTRPT0. + USB_DIEPINT0_D_NAKINTRPT0 = 0x2000 + // Position of D_NYETINTRPT0 field. + USB_DIEPINT0_D_NYETINTRPT0_Pos = 0xe + // Bit mask of D_NYETINTRPT0 field. + USB_DIEPINT0_D_NYETINTRPT0_Msk = 0x4000 + // Bit D_NYETINTRPT0. + USB_DIEPINT0_D_NYETINTRPT0 = 0x4000 + + // DIEPTSIZ0 + // Position of D_XFERSIZE0 field. + USB_DIEPTSIZ0_D_XFERSIZE0_Pos = 0x0 + // Bit mask of D_XFERSIZE0 field. + USB_DIEPTSIZ0_D_XFERSIZE0_Msk = 0x7f + // Position of D_PKTCNT0 field. + USB_DIEPTSIZ0_D_PKTCNT0_Pos = 0x13 + // Bit mask of D_PKTCNT0 field. + USB_DIEPTSIZ0_D_PKTCNT0_Msk = 0x180000 + + // DIEPDMA0 + // Position of D_DMAADDR0 field. + USB_DIEPDMA0_D_DMAADDR0_Pos = 0x0 + // Bit mask of D_DMAADDR0 field. + USB_DIEPDMA0_D_DMAADDR0_Msk = 0xffffffff + + // DTXFSTS0 + // Position of D_INEPTXFSPCAVAIL0 field. + USB_DTXFSTS0_D_INEPTXFSPCAVAIL0_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL0 field. + USB_DTXFSTS0_D_INEPTXFSPCAVAIL0_Msk = 0xffff + + // DIEPDMAB0 + // Position of D_DMABUFFERADDR0 field. + USB_DIEPDMAB0_D_DMABUFFERADDR0_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR0 field. + USB_DIEPDMAB0_D_DMABUFFERADDR0_Msk = 0xffffffff + + // DIEPCTL1 + // Position of D_MPS1 field. + USB_DIEPCTL1_D_MPS1_Pos = 0x0 + // Bit mask of D_MPS1 field. + USB_DIEPCTL1_D_MPS1_Msk = 0x3 + // Position of D_USBACTEP1 field. + USB_DIEPCTL1_D_USBACTEP1_Pos = 0xf + // Bit mask of D_USBACTEP1 field. + USB_DIEPCTL1_D_USBACTEP1_Msk = 0x8000 + // Bit D_USBACTEP1. + USB_DIEPCTL1_D_USBACTEP1 = 0x8000 + // Position of D_NAKSTS1 field. + USB_DIEPCTL1_D_NAKSTS1_Pos = 0x11 + // Bit mask of D_NAKSTS1 field. + USB_DIEPCTL1_D_NAKSTS1_Msk = 0x20000 + // Bit D_NAKSTS1. + USB_DIEPCTL1_D_NAKSTS1 = 0x20000 + // Position of D_EPTYPE1 field. + USB_DIEPCTL1_D_EPTYPE1_Pos = 0x12 + // Bit mask of D_EPTYPE1 field. + USB_DIEPCTL1_D_EPTYPE1_Msk = 0xc0000 + // Position of D_STALL1 field. + USB_DIEPCTL1_D_STALL1_Pos = 0x15 + // Bit mask of D_STALL1 field. + USB_DIEPCTL1_D_STALL1_Msk = 0x200000 + // Bit D_STALL1. + USB_DIEPCTL1_D_STALL1 = 0x200000 + // Position of D_TXFNUM1 field. + USB_DIEPCTL1_D_TXFNUM1_Pos = 0x16 + // Bit mask of D_TXFNUM1 field. + USB_DIEPCTL1_D_TXFNUM1_Msk = 0x3c00000 + // Position of D_CNAK1 field. + USB_DIEPCTL1_D_CNAK1_Pos = 0x1a + // Bit mask of D_CNAK1 field. + USB_DIEPCTL1_D_CNAK1_Msk = 0x4000000 + // Bit D_CNAK1. + USB_DIEPCTL1_D_CNAK1 = 0x4000000 + // Position of DI_SNAK1 field. + USB_DIEPCTL1_DI_SNAK1_Pos = 0x1b + // Bit mask of DI_SNAK1 field. + USB_DIEPCTL1_DI_SNAK1_Msk = 0x8000000 + // Bit DI_SNAK1. + USB_DIEPCTL1_DI_SNAK1 = 0x8000000 + // Position of DI_SETD0PID1 field. + USB_DIEPCTL1_DI_SETD0PID1_Pos = 0x1c + // Bit mask of DI_SETD0PID1 field. + USB_DIEPCTL1_DI_SETD0PID1_Msk = 0x10000000 + // Bit DI_SETD0PID1. + USB_DIEPCTL1_DI_SETD0PID1 = 0x10000000 + // Position of DI_SETD1PID1 field. + USB_DIEPCTL1_DI_SETD1PID1_Pos = 0x1d + // Bit mask of DI_SETD1PID1 field. + USB_DIEPCTL1_DI_SETD1PID1_Msk = 0x20000000 + // Bit DI_SETD1PID1. + USB_DIEPCTL1_DI_SETD1PID1 = 0x20000000 + // Position of D_EPDIS1 field. + USB_DIEPCTL1_D_EPDIS1_Pos = 0x1e + // Bit mask of D_EPDIS1 field. + USB_DIEPCTL1_D_EPDIS1_Msk = 0x40000000 + // Bit D_EPDIS1. + USB_DIEPCTL1_D_EPDIS1 = 0x40000000 + // Position of D_EPENA1 field. + USB_DIEPCTL1_D_EPENA1_Pos = 0x1f + // Bit mask of D_EPENA1 field. + USB_DIEPCTL1_D_EPENA1_Msk = 0x80000000 + // Bit D_EPENA1. + USB_DIEPCTL1_D_EPENA1 = 0x80000000 + + // DIEPINT1 + // Position of D_XFERCOMPL1 field. + USB_DIEPINT1_D_XFERCOMPL1_Pos = 0x0 + // Bit mask of D_XFERCOMPL1 field. + USB_DIEPINT1_D_XFERCOMPL1_Msk = 0x1 + // Bit D_XFERCOMPL1. + USB_DIEPINT1_D_XFERCOMPL1 = 0x1 + // Position of D_EPDISBLD1 field. + USB_DIEPINT1_D_EPDISBLD1_Pos = 0x1 + // Bit mask of D_EPDISBLD1 field. + USB_DIEPINT1_D_EPDISBLD1_Msk = 0x2 + // Bit D_EPDISBLD1. + USB_DIEPINT1_D_EPDISBLD1 = 0x2 + // Position of D_AHBERR1 field. + USB_DIEPINT1_D_AHBERR1_Pos = 0x2 + // Bit mask of D_AHBERR1 field. + USB_DIEPINT1_D_AHBERR1_Msk = 0x4 + // Bit D_AHBERR1. + USB_DIEPINT1_D_AHBERR1 = 0x4 + // Position of D_TIMEOUT1 field. + USB_DIEPINT1_D_TIMEOUT1_Pos = 0x3 + // Bit mask of D_TIMEOUT1 field. + USB_DIEPINT1_D_TIMEOUT1_Msk = 0x8 + // Bit D_TIMEOUT1. + USB_DIEPINT1_D_TIMEOUT1 = 0x8 + // Position of D_INTKNTXFEMP1 field. + USB_DIEPINT1_D_INTKNTXFEMP1_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP1 field. + USB_DIEPINT1_D_INTKNTXFEMP1_Msk = 0x10 + // Bit D_INTKNTXFEMP1. + USB_DIEPINT1_D_INTKNTXFEMP1 = 0x10 + // Position of D_INTKNEPMIS1 field. + USB_DIEPINT1_D_INTKNEPMIS1_Pos = 0x5 + // Bit mask of D_INTKNEPMIS1 field. + USB_DIEPINT1_D_INTKNEPMIS1_Msk = 0x20 + // Bit D_INTKNEPMIS1. + USB_DIEPINT1_D_INTKNEPMIS1 = 0x20 + // Position of D_INEPNAKEFF1 field. + USB_DIEPINT1_D_INEPNAKEFF1_Pos = 0x6 + // Bit mask of D_INEPNAKEFF1 field. + USB_DIEPINT1_D_INEPNAKEFF1_Msk = 0x40 + // Bit D_INEPNAKEFF1. + USB_DIEPINT1_D_INEPNAKEFF1 = 0x40 + // Position of D_TXFEMP1 field. + USB_DIEPINT1_D_TXFEMP1_Pos = 0x7 + // Bit mask of D_TXFEMP1 field. + USB_DIEPINT1_D_TXFEMP1_Msk = 0x80 + // Bit D_TXFEMP1. + USB_DIEPINT1_D_TXFEMP1 = 0x80 + // Position of D_TXFIFOUNDRN1 field. + USB_DIEPINT1_D_TXFIFOUNDRN1_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN1 field. + USB_DIEPINT1_D_TXFIFOUNDRN1_Msk = 0x100 + // Bit D_TXFIFOUNDRN1. + USB_DIEPINT1_D_TXFIFOUNDRN1 = 0x100 + // Position of D_BNAINTR1 field. + USB_DIEPINT1_D_BNAINTR1_Pos = 0x9 + // Bit mask of D_BNAINTR1 field. + USB_DIEPINT1_D_BNAINTR1_Msk = 0x200 + // Bit D_BNAINTR1. + USB_DIEPINT1_D_BNAINTR1 = 0x200 + // Position of D_PKTDRPSTS1 field. + USB_DIEPINT1_D_PKTDRPSTS1_Pos = 0xb + // Bit mask of D_PKTDRPSTS1 field. + USB_DIEPINT1_D_PKTDRPSTS1_Msk = 0x800 + // Bit D_PKTDRPSTS1. + USB_DIEPINT1_D_PKTDRPSTS1 = 0x800 + // Position of D_BBLEERR1 field. + USB_DIEPINT1_D_BBLEERR1_Pos = 0xc + // Bit mask of D_BBLEERR1 field. + USB_DIEPINT1_D_BBLEERR1_Msk = 0x1000 + // Bit D_BBLEERR1. + USB_DIEPINT1_D_BBLEERR1 = 0x1000 + // Position of D_NAKINTRPT1 field. + USB_DIEPINT1_D_NAKINTRPT1_Pos = 0xd + // Bit mask of D_NAKINTRPT1 field. + USB_DIEPINT1_D_NAKINTRPT1_Msk = 0x2000 + // Bit D_NAKINTRPT1. + USB_DIEPINT1_D_NAKINTRPT1 = 0x2000 + // Position of D_NYETINTRPT1 field. + USB_DIEPINT1_D_NYETINTRPT1_Pos = 0xe + // Bit mask of D_NYETINTRPT1 field. + USB_DIEPINT1_D_NYETINTRPT1_Msk = 0x4000 + // Bit D_NYETINTRPT1. + USB_DIEPINT1_D_NYETINTRPT1 = 0x4000 + + // DIEPTSIZ1 + // Position of D_XFERSIZE1 field. + USB_DIEPTSIZ1_D_XFERSIZE1_Pos = 0x0 + // Bit mask of D_XFERSIZE1 field. + USB_DIEPTSIZ1_D_XFERSIZE1_Msk = 0x7f + // Position of D_PKTCNT1 field. + USB_DIEPTSIZ1_D_PKTCNT1_Pos = 0x13 + // Bit mask of D_PKTCNT1 field. + USB_DIEPTSIZ1_D_PKTCNT1_Msk = 0x180000 + + // DIEPDMA1 + // Position of D_DMAADDR1 field. + USB_DIEPDMA1_D_DMAADDR1_Pos = 0x0 + // Bit mask of D_DMAADDR1 field. + USB_DIEPDMA1_D_DMAADDR1_Msk = 0xffffffff + + // DTXFSTS1 + // Position of D_INEPTXFSPCAVAIL1 field. + USB_DTXFSTS1_D_INEPTXFSPCAVAIL1_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL1 field. + USB_DTXFSTS1_D_INEPTXFSPCAVAIL1_Msk = 0xffff + + // DIEPDMAB1 + // Position of D_DMABUFFERADDR1 field. + USB_DIEPDMAB1_D_DMABUFFERADDR1_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR1 field. + USB_DIEPDMAB1_D_DMABUFFERADDR1_Msk = 0xffffffff + + // DIEPCTL2 + // Position of D_MPS2 field. + USB_DIEPCTL2_D_MPS2_Pos = 0x0 + // Bit mask of D_MPS2 field. + USB_DIEPCTL2_D_MPS2_Msk = 0x3 + // Position of D_USBACTEP2 field. + USB_DIEPCTL2_D_USBACTEP2_Pos = 0xf + // Bit mask of D_USBACTEP2 field. + USB_DIEPCTL2_D_USBACTEP2_Msk = 0x8000 + // Bit D_USBACTEP2. + USB_DIEPCTL2_D_USBACTEP2 = 0x8000 + // Position of D_NAKSTS2 field. + USB_DIEPCTL2_D_NAKSTS2_Pos = 0x11 + // Bit mask of D_NAKSTS2 field. + USB_DIEPCTL2_D_NAKSTS2_Msk = 0x20000 + // Bit D_NAKSTS2. + USB_DIEPCTL2_D_NAKSTS2 = 0x20000 + // Position of D_EPTYPE2 field. + USB_DIEPCTL2_D_EPTYPE2_Pos = 0x12 + // Bit mask of D_EPTYPE2 field. + USB_DIEPCTL2_D_EPTYPE2_Msk = 0xc0000 + // Position of D_STALL2 field. + USB_DIEPCTL2_D_STALL2_Pos = 0x15 + // Bit mask of D_STALL2 field. + USB_DIEPCTL2_D_STALL2_Msk = 0x200000 + // Bit D_STALL2. + USB_DIEPCTL2_D_STALL2 = 0x200000 + // Position of D_TXFNUM2 field. + USB_DIEPCTL2_D_TXFNUM2_Pos = 0x16 + // Bit mask of D_TXFNUM2 field. + USB_DIEPCTL2_D_TXFNUM2_Msk = 0x3c00000 + // Position of D_CNAK2 field. + USB_DIEPCTL2_D_CNAK2_Pos = 0x1a + // Bit mask of D_CNAK2 field. + USB_DIEPCTL2_D_CNAK2_Msk = 0x4000000 + // Bit D_CNAK2. + USB_DIEPCTL2_D_CNAK2 = 0x4000000 + // Position of DI_SNAK2 field. + USB_DIEPCTL2_DI_SNAK2_Pos = 0x1b + // Bit mask of DI_SNAK2 field. + USB_DIEPCTL2_DI_SNAK2_Msk = 0x8000000 + // Bit DI_SNAK2. + USB_DIEPCTL2_DI_SNAK2 = 0x8000000 + // Position of DI_SETD0PID2 field. + USB_DIEPCTL2_DI_SETD0PID2_Pos = 0x1c + // Bit mask of DI_SETD0PID2 field. + USB_DIEPCTL2_DI_SETD0PID2_Msk = 0x10000000 + // Bit DI_SETD0PID2. + USB_DIEPCTL2_DI_SETD0PID2 = 0x10000000 + // Position of DI_SETD1PID2 field. + USB_DIEPCTL2_DI_SETD1PID2_Pos = 0x1d + // Bit mask of DI_SETD1PID2 field. + USB_DIEPCTL2_DI_SETD1PID2_Msk = 0x20000000 + // Bit DI_SETD1PID2. + USB_DIEPCTL2_DI_SETD1PID2 = 0x20000000 + // Position of D_EPDIS2 field. + USB_DIEPCTL2_D_EPDIS2_Pos = 0x1e + // Bit mask of D_EPDIS2 field. + USB_DIEPCTL2_D_EPDIS2_Msk = 0x40000000 + // Bit D_EPDIS2. + USB_DIEPCTL2_D_EPDIS2 = 0x40000000 + // Position of D_EPENA2 field. + USB_DIEPCTL2_D_EPENA2_Pos = 0x1f + // Bit mask of D_EPENA2 field. + USB_DIEPCTL2_D_EPENA2_Msk = 0x80000000 + // Bit D_EPENA2. + USB_DIEPCTL2_D_EPENA2 = 0x80000000 + + // DIEPINT2 + // Position of D_XFERCOMPL2 field. + USB_DIEPINT2_D_XFERCOMPL2_Pos = 0x0 + // Bit mask of D_XFERCOMPL2 field. + USB_DIEPINT2_D_XFERCOMPL2_Msk = 0x1 + // Bit D_XFERCOMPL2. + USB_DIEPINT2_D_XFERCOMPL2 = 0x1 + // Position of D_EPDISBLD2 field. + USB_DIEPINT2_D_EPDISBLD2_Pos = 0x1 + // Bit mask of D_EPDISBLD2 field. + USB_DIEPINT2_D_EPDISBLD2_Msk = 0x2 + // Bit D_EPDISBLD2. + USB_DIEPINT2_D_EPDISBLD2 = 0x2 + // Position of D_AHBERR2 field. + USB_DIEPINT2_D_AHBERR2_Pos = 0x2 + // Bit mask of D_AHBERR2 field. + USB_DIEPINT2_D_AHBERR2_Msk = 0x4 + // Bit D_AHBERR2. + USB_DIEPINT2_D_AHBERR2 = 0x4 + // Position of D_TIMEOUT2 field. + USB_DIEPINT2_D_TIMEOUT2_Pos = 0x3 + // Bit mask of D_TIMEOUT2 field. + USB_DIEPINT2_D_TIMEOUT2_Msk = 0x8 + // Bit D_TIMEOUT2. + USB_DIEPINT2_D_TIMEOUT2 = 0x8 + // Position of D_INTKNTXFEMP2 field. + USB_DIEPINT2_D_INTKNTXFEMP2_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP2 field. + USB_DIEPINT2_D_INTKNTXFEMP2_Msk = 0x10 + // Bit D_INTKNTXFEMP2. + USB_DIEPINT2_D_INTKNTXFEMP2 = 0x10 + // Position of D_INTKNEPMIS2 field. + USB_DIEPINT2_D_INTKNEPMIS2_Pos = 0x5 + // Bit mask of D_INTKNEPMIS2 field. + USB_DIEPINT2_D_INTKNEPMIS2_Msk = 0x20 + // Bit D_INTKNEPMIS2. + USB_DIEPINT2_D_INTKNEPMIS2 = 0x20 + // Position of D_INEPNAKEFF2 field. + USB_DIEPINT2_D_INEPNAKEFF2_Pos = 0x6 + // Bit mask of D_INEPNAKEFF2 field. + USB_DIEPINT2_D_INEPNAKEFF2_Msk = 0x40 + // Bit D_INEPNAKEFF2. + USB_DIEPINT2_D_INEPNAKEFF2 = 0x40 + // Position of D_TXFEMP2 field. + USB_DIEPINT2_D_TXFEMP2_Pos = 0x7 + // Bit mask of D_TXFEMP2 field. + USB_DIEPINT2_D_TXFEMP2_Msk = 0x80 + // Bit D_TXFEMP2. + USB_DIEPINT2_D_TXFEMP2 = 0x80 + // Position of D_TXFIFOUNDRN2 field. + USB_DIEPINT2_D_TXFIFOUNDRN2_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN2 field. + USB_DIEPINT2_D_TXFIFOUNDRN2_Msk = 0x100 + // Bit D_TXFIFOUNDRN2. + USB_DIEPINT2_D_TXFIFOUNDRN2 = 0x100 + // Position of D_BNAINTR2 field. + USB_DIEPINT2_D_BNAINTR2_Pos = 0x9 + // Bit mask of D_BNAINTR2 field. + USB_DIEPINT2_D_BNAINTR2_Msk = 0x200 + // Bit D_BNAINTR2. + USB_DIEPINT2_D_BNAINTR2 = 0x200 + // Position of D_PKTDRPSTS2 field. + USB_DIEPINT2_D_PKTDRPSTS2_Pos = 0xb + // Bit mask of D_PKTDRPSTS2 field. + USB_DIEPINT2_D_PKTDRPSTS2_Msk = 0x800 + // Bit D_PKTDRPSTS2. + USB_DIEPINT2_D_PKTDRPSTS2 = 0x800 + // Position of D_BBLEERR2 field. + USB_DIEPINT2_D_BBLEERR2_Pos = 0xc + // Bit mask of D_BBLEERR2 field. + USB_DIEPINT2_D_BBLEERR2_Msk = 0x1000 + // Bit D_BBLEERR2. + USB_DIEPINT2_D_BBLEERR2 = 0x1000 + // Position of D_NAKINTRPT2 field. + USB_DIEPINT2_D_NAKINTRPT2_Pos = 0xd + // Bit mask of D_NAKINTRPT2 field. + USB_DIEPINT2_D_NAKINTRPT2_Msk = 0x2000 + // Bit D_NAKINTRPT2. + USB_DIEPINT2_D_NAKINTRPT2 = 0x2000 + // Position of D_NYETINTRPT2 field. + USB_DIEPINT2_D_NYETINTRPT2_Pos = 0xe + // Bit mask of D_NYETINTRPT2 field. + USB_DIEPINT2_D_NYETINTRPT2_Msk = 0x4000 + // Bit D_NYETINTRPT2. + USB_DIEPINT2_D_NYETINTRPT2 = 0x4000 + + // DIEPTSIZ2 + // Position of D_XFERSIZE2 field. + USB_DIEPTSIZ2_D_XFERSIZE2_Pos = 0x0 + // Bit mask of D_XFERSIZE2 field. + USB_DIEPTSIZ2_D_XFERSIZE2_Msk = 0x7f + // Position of D_PKTCNT2 field. + USB_DIEPTSIZ2_D_PKTCNT2_Pos = 0x13 + // Bit mask of D_PKTCNT2 field. + USB_DIEPTSIZ2_D_PKTCNT2_Msk = 0x180000 + + // DIEPDMA2 + // Position of D_DMAADDR2 field. + USB_DIEPDMA2_D_DMAADDR2_Pos = 0x0 + // Bit mask of D_DMAADDR2 field. + USB_DIEPDMA2_D_DMAADDR2_Msk = 0xffffffff + + // DTXFSTS2 + // Position of D_INEPTXFSPCAVAIL2 field. + USB_DTXFSTS2_D_INEPTXFSPCAVAIL2_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL2 field. + USB_DTXFSTS2_D_INEPTXFSPCAVAIL2_Msk = 0xffff + + // DIEPDMAB2 + // Position of D_DMABUFFERADDR2 field. + USB_DIEPDMAB2_D_DMABUFFERADDR2_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR2 field. + USB_DIEPDMAB2_D_DMABUFFERADDR2_Msk = 0xffffffff + + // DIEPCTL3 + // Position of DI_MPS3 field. + USB_DIEPCTL3_DI_MPS3_Pos = 0x0 + // Bit mask of DI_MPS3 field. + USB_DIEPCTL3_DI_MPS3_Msk = 0x3 + // Position of DI_USBACTEP3 field. + USB_DIEPCTL3_DI_USBACTEP3_Pos = 0xf + // Bit mask of DI_USBACTEP3 field. + USB_DIEPCTL3_DI_USBACTEP3_Msk = 0x8000 + // Bit DI_USBACTEP3. + USB_DIEPCTL3_DI_USBACTEP3 = 0x8000 + // Position of DI_NAKSTS3 field. + USB_DIEPCTL3_DI_NAKSTS3_Pos = 0x11 + // Bit mask of DI_NAKSTS3 field. + USB_DIEPCTL3_DI_NAKSTS3_Msk = 0x20000 + // Bit DI_NAKSTS3. + USB_DIEPCTL3_DI_NAKSTS3 = 0x20000 + // Position of DI_EPTYPE3 field. + USB_DIEPCTL3_DI_EPTYPE3_Pos = 0x12 + // Bit mask of DI_EPTYPE3 field. + USB_DIEPCTL3_DI_EPTYPE3_Msk = 0xc0000 + // Position of DI_STALL3 field. + USB_DIEPCTL3_DI_STALL3_Pos = 0x15 + // Bit mask of DI_STALL3 field. + USB_DIEPCTL3_DI_STALL3_Msk = 0x200000 + // Bit DI_STALL3. + USB_DIEPCTL3_DI_STALL3 = 0x200000 + // Position of DI_TXFNUM3 field. + USB_DIEPCTL3_DI_TXFNUM3_Pos = 0x16 + // Bit mask of DI_TXFNUM3 field. + USB_DIEPCTL3_DI_TXFNUM3_Msk = 0x3c00000 + // Position of DI_CNAK3 field. + USB_DIEPCTL3_DI_CNAK3_Pos = 0x1a + // Bit mask of DI_CNAK3 field. + USB_DIEPCTL3_DI_CNAK3_Msk = 0x4000000 + // Bit DI_CNAK3. + USB_DIEPCTL3_DI_CNAK3 = 0x4000000 + // Position of DI_SNAK3 field. + USB_DIEPCTL3_DI_SNAK3_Pos = 0x1b + // Bit mask of DI_SNAK3 field. + USB_DIEPCTL3_DI_SNAK3_Msk = 0x8000000 + // Bit DI_SNAK3. + USB_DIEPCTL3_DI_SNAK3 = 0x8000000 + // Position of DI_SETD0PID3 field. + USB_DIEPCTL3_DI_SETD0PID3_Pos = 0x1c + // Bit mask of DI_SETD0PID3 field. + USB_DIEPCTL3_DI_SETD0PID3_Msk = 0x10000000 + // Bit DI_SETD0PID3. + USB_DIEPCTL3_DI_SETD0PID3 = 0x10000000 + // Position of DI_SETD1PID3 field. + USB_DIEPCTL3_DI_SETD1PID3_Pos = 0x1d + // Bit mask of DI_SETD1PID3 field. + USB_DIEPCTL3_DI_SETD1PID3_Msk = 0x20000000 + // Bit DI_SETD1PID3. + USB_DIEPCTL3_DI_SETD1PID3 = 0x20000000 + // Position of DI_EPDIS3 field. + USB_DIEPCTL3_DI_EPDIS3_Pos = 0x1e + // Bit mask of DI_EPDIS3 field. + USB_DIEPCTL3_DI_EPDIS3_Msk = 0x40000000 + // Bit DI_EPDIS3. + USB_DIEPCTL3_DI_EPDIS3 = 0x40000000 + // Position of DI_EPENA3 field. + USB_DIEPCTL3_DI_EPENA3_Pos = 0x1f + // Bit mask of DI_EPENA3 field. + USB_DIEPCTL3_DI_EPENA3_Msk = 0x80000000 + // Bit DI_EPENA3. + USB_DIEPCTL3_DI_EPENA3 = 0x80000000 + + // DIEPINT3 + // Position of D_XFERCOMPL3 field. + USB_DIEPINT3_D_XFERCOMPL3_Pos = 0x0 + // Bit mask of D_XFERCOMPL3 field. + USB_DIEPINT3_D_XFERCOMPL3_Msk = 0x1 + // Bit D_XFERCOMPL3. + USB_DIEPINT3_D_XFERCOMPL3 = 0x1 + // Position of D_EPDISBLD3 field. + USB_DIEPINT3_D_EPDISBLD3_Pos = 0x1 + // Bit mask of D_EPDISBLD3 field. + USB_DIEPINT3_D_EPDISBLD3_Msk = 0x2 + // Bit D_EPDISBLD3. + USB_DIEPINT3_D_EPDISBLD3 = 0x2 + // Position of D_AHBERR3 field. + USB_DIEPINT3_D_AHBERR3_Pos = 0x2 + // Bit mask of D_AHBERR3 field. + USB_DIEPINT3_D_AHBERR3_Msk = 0x4 + // Bit D_AHBERR3. + USB_DIEPINT3_D_AHBERR3 = 0x4 + // Position of D_TIMEOUT3 field. + USB_DIEPINT3_D_TIMEOUT3_Pos = 0x3 + // Bit mask of D_TIMEOUT3 field. + USB_DIEPINT3_D_TIMEOUT3_Msk = 0x8 + // Bit D_TIMEOUT3. + USB_DIEPINT3_D_TIMEOUT3 = 0x8 + // Position of D_INTKNTXFEMP3 field. + USB_DIEPINT3_D_INTKNTXFEMP3_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP3 field. + USB_DIEPINT3_D_INTKNTXFEMP3_Msk = 0x10 + // Bit D_INTKNTXFEMP3. + USB_DIEPINT3_D_INTKNTXFEMP3 = 0x10 + // Position of D_INTKNEPMIS3 field. + USB_DIEPINT3_D_INTKNEPMIS3_Pos = 0x5 + // Bit mask of D_INTKNEPMIS3 field. + USB_DIEPINT3_D_INTKNEPMIS3_Msk = 0x20 + // Bit D_INTKNEPMIS3. + USB_DIEPINT3_D_INTKNEPMIS3 = 0x20 + // Position of D_INEPNAKEFF3 field. + USB_DIEPINT3_D_INEPNAKEFF3_Pos = 0x6 + // Bit mask of D_INEPNAKEFF3 field. + USB_DIEPINT3_D_INEPNAKEFF3_Msk = 0x40 + // Bit D_INEPNAKEFF3. + USB_DIEPINT3_D_INEPNAKEFF3 = 0x40 + // Position of D_TXFEMP3 field. + USB_DIEPINT3_D_TXFEMP3_Pos = 0x7 + // Bit mask of D_TXFEMP3 field. + USB_DIEPINT3_D_TXFEMP3_Msk = 0x80 + // Bit D_TXFEMP3. + USB_DIEPINT3_D_TXFEMP3 = 0x80 + // Position of D_TXFIFOUNDRN3 field. + USB_DIEPINT3_D_TXFIFOUNDRN3_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN3 field. + USB_DIEPINT3_D_TXFIFOUNDRN3_Msk = 0x100 + // Bit D_TXFIFOUNDRN3. + USB_DIEPINT3_D_TXFIFOUNDRN3 = 0x100 + // Position of D_BNAINTR3 field. + USB_DIEPINT3_D_BNAINTR3_Pos = 0x9 + // Bit mask of D_BNAINTR3 field. + USB_DIEPINT3_D_BNAINTR3_Msk = 0x200 + // Bit D_BNAINTR3. + USB_DIEPINT3_D_BNAINTR3 = 0x200 + // Position of D_PKTDRPSTS3 field. + USB_DIEPINT3_D_PKTDRPSTS3_Pos = 0xb + // Bit mask of D_PKTDRPSTS3 field. + USB_DIEPINT3_D_PKTDRPSTS3_Msk = 0x800 + // Bit D_PKTDRPSTS3. + USB_DIEPINT3_D_PKTDRPSTS3 = 0x800 + // Position of D_BBLEERR3 field. + USB_DIEPINT3_D_BBLEERR3_Pos = 0xc + // Bit mask of D_BBLEERR3 field. + USB_DIEPINT3_D_BBLEERR3_Msk = 0x1000 + // Bit D_BBLEERR3. + USB_DIEPINT3_D_BBLEERR3 = 0x1000 + // Position of D_NAKINTRPT3 field. + USB_DIEPINT3_D_NAKINTRPT3_Pos = 0xd + // Bit mask of D_NAKINTRPT3 field. + USB_DIEPINT3_D_NAKINTRPT3_Msk = 0x2000 + // Bit D_NAKINTRPT3. + USB_DIEPINT3_D_NAKINTRPT3 = 0x2000 + // Position of D_NYETINTRPT3 field. + USB_DIEPINT3_D_NYETINTRPT3_Pos = 0xe + // Bit mask of D_NYETINTRPT3 field. + USB_DIEPINT3_D_NYETINTRPT3_Msk = 0x4000 + // Bit D_NYETINTRPT3. + USB_DIEPINT3_D_NYETINTRPT3 = 0x4000 + + // DIEPTSIZ3 + // Position of D_XFERSIZE3 field. + USB_DIEPTSIZ3_D_XFERSIZE3_Pos = 0x0 + // Bit mask of D_XFERSIZE3 field. + USB_DIEPTSIZ3_D_XFERSIZE3_Msk = 0x7f + // Position of D_PKTCNT3 field. + USB_DIEPTSIZ3_D_PKTCNT3_Pos = 0x13 + // Bit mask of D_PKTCNT3 field. + USB_DIEPTSIZ3_D_PKTCNT3_Msk = 0x180000 + + // DIEPDMA3 + // Position of D_DMAADDR3 field. + USB_DIEPDMA3_D_DMAADDR3_Pos = 0x0 + // Bit mask of D_DMAADDR3 field. + USB_DIEPDMA3_D_DMAADDR3_Msk = 0xffffffff + + // DTXFSTS3 + // Position of D_INEPTXFSPCAVAIL3 field. + USB_DTXFSTS3_D_INEPTXFSPCAVAIL3_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL3 field. + USB_DTXFSTS3_D_INEPTXFSPCAVAIL3_Msk = 0xffff + + // DIEPDMAB3 + // Position of D_DMABUFFERADDR3 field. + USB_DIEPDMAB3_D_DMABUFFERADDR3_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR3 field. + USB_DIEPDMAB3_D_DMABUFFERADDR3_Msk = 0xffffffff + + // DIEPCTL4 + // Position of D_MPS4 field. + USB_DIEPCTL4_D_MPS4_Pos = 0x0 + // Bit mask of D_MPS4 field. + USB_DIEPCTL4_D_MPS4_Msk = 0x3 + // Position of D_USBACTEP4 field. + USB_DIEPCTL4_D_USBACTEP4_Pos = 0xf + // Bit mask of D_USBACTEP4 field. + USB_DIEPCTL4_D_USBACTEP4_Msk = 0x8000 + // Bit D_USBACTEP4. + USB_DIEPCTL4_D_USBACTEP4 = 0x8000 + // Position of D_NAKSTS4 field. + USB_DIEPCTL4_D_NAKSTS4_Pos = 0x11 + // Bit mask of D_NAKSTS4 field. + USB_DIEPCTL4_D_NAKSTS4_Msk = 0x20000 + // Bit D_NAKSTS4. + USB_DIEPCTL4_D_NAKSTS4 = 0x20000 + // Position of D_EPTYPE4 field. + USB_DIEPCTL4_D_EPTYPE4_Pos = 0x12 + // Bit mask of D_EPTYPE4 field. + USB_DIEPCTL4_D_EPTYPE4_Msk = 0xc0000 + // Position of D_STALL4 field. + USB_DIEPCTL4_D_STALL4_Pos = 0x15 + // Bit mask of D_STALL4 field. + USB_DIEPCTL4_D_STALL4_Msk = 0x200000 + // Bit D_STALL4. + USB_DIEPCTL4_D_STALL4 = 0x200000 + // Position of D_TXFNUM4 field. + USB_DIEPCTL4_D_TXFNUM4_Pos = 0x16 + // Bit mask of D_TXFNUM4 field. + USB_DIEPCTL4_D_TXFNUM4_Msk = 0x3c00000 + // Position of D_CNAK4 field. + USB_DIEPCTL4_D_CNAK4_Pos = 0x1a + // Bit mask of D_CNAK4 field. + USB_DIEPCTL4_D_CNAK4_Msk = 0x4000000 + // Bit D_CNAK4. + USB_DIEPCTL4_D_CNAK4 = 0x4000000 + // Position of DI_SNAK4 field. + USB_DIEPCTL4_DI_SNAK4_Pos = 0x1b + // Bit mask of DI_SNAK4 field. + USB_DIEPCTL4_DI_SNAK4_Msk = 0x8000000 + // Bit DI_SNAK4. + USB_DIEPCTL4_DI_SNAK4 = 0x8000000 + // Position of DI_SETD0PID4 field. + USB_DIEPCTL4_DI_SETD0PID4_Pos = 0x1c + // Bit mask of DI_SETD0PID4 field. + USB_DIEPCTL4_DI_SETD0PID4_Msk = 0x10000000 + // Bit DI_SETD0PID4. + USB_DIEPCTL4_DI_SETD0PID4 = 0x10000000 + // Position of DI_SETD1PID4 field. + USB_DIEPCTL4_DI_SETD1PID4_Pos = 0x1d + // Bit mask of DI_SETD1PID4 field. + USB_DIEPCTL4_DI_SETD1PID4_Msk = 0x20000000 + // Bit DI_SETD1PID4. + USB_DIEPCTL4_DI_SETD1PID4 = 0x20000000 + // Position of D_EPDIS4 field. + USB_DIEPCTL4_D_EPDIS4_Pos = 0x1e + // Bit mask of D_EPDIS4 field. + USB_DIEPCTL4_D_EPDIS4_Msk = 0x40000000 + // Bit D_EPDIS4. + USB_DIEPCTL4_D_EPDIS4 = 0x40000000 + // Position of D_EPENA4 field. + USB_DIEPCTL4_D_EPENA4_Pos = 0x1f + // Bit mask of D_EPENA4 field. + USB_DIEPCTL4_D_EPENA4_Msk = 0x80000000 + // Bit D_EPENA4. + USB_DIEPCTL4_D_EPENA4 = 0x80000000 + + // DIEPINT4 + // Position of D_XFERCOMPL4 field. + USB_DIEPINT4_D_XFERCOMPL4_Pos = 0x0 + // Bit mask of D_XFERCOMPL4 field. + USB_DIEPINT4_D_XFERCOMPL4_Msk = 0x1 + // Bit D_XFERCOMPL4. + USB_DIEPINT4_D_XFERCOMPL4 = 0x1 + // Position of D_EPDISBLD4 field. + USB_DIEPINT4_D_EPDISBLD4_Pos = 0x1 + // Bit mask of D_EPDISBLD4 field. + USB_DIEPINT4_D_EPDISBLD4_Msk = 0x2 + // Bit D_EPDISBLD4. + USB_DIEPINT4_D_EPDISBLD4 = 0x2 + // Position of D_AHBERR4 field. + USB_DIEPINT4_D_AHBERR4_Pos = 0x2 + // Bit mask of D_AHBERR4 field. + USB_DIEPINT4_D_AHBERR4_Msk = 0x4 + // Bit D_AHBERR4. + USB_DIEPINT4_D_AHBERR4 = 0x4 + // Position of D_TIMEOUT4 field. + USB_DIEPINT4_D_TIMEOUT4_Pos = 0x3 + // Bit mask of D_TIMEOUT4 field. + USB_DIEPINT4_D_TIMEOUT4_Msk = 0x8 + // Bit D_TIMEOUT4. + USB_DIEPINT4_D_TIMEOUT4 = 0x8 + // Position of D_INTKNTXFEMP4 field. + USB_DIEPINT4_D_INTKNTXFEMP4_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP4 field. + USB_DIEPINT4_D_INTKNTXFEMP4_Msk = 0x10 + // Bit D_INTKNTXFEMP4. + USB_DIEPINT4_D_INTKNTXFEMP4 = 0x10 + // Position of D_INTKNEPMIS4 field. + USB_DIEPINT4_D_INTKNEPMIS4_Pos = 0x5 + // Bit mask of D_INTKNEPMIS4 field. + USB_DIEPINT4_D_INTKNEPMIS4_Msk = 0x20 + // Bit D_INTKNEPMIS4. + USB_DIEPINT4_D_INTKNEPMIS4 = 0x20 + // Position of D_INEPNAKEFF4 field. + USB_DIEPINT4_D_INEPNAKEFF4_Pos = 0x6 + // Bit mask of D_INEPNAKEFF4 field. + USB_DIEPINT4_D_INEPNAKEFF4_Msk = 0x40 + // Bit D_INEPNAKEFF4. + USB_DIEPINT4_D_INEPNAKEFF4 = 0x40 + // Position of D_TXFEMP4 field. + USB_DIEPINT4_D_TXFEMP4_Pos = 0x7 + // Bit mask of D_TXFEMP4 field. + USB_DIEPINT4_D_TXFEMP4_Msk = 0x80 + // Bit D_TXFEMP4. + USB_DIEPINT4_D_TXFEMP4 = 0x80 + // Position of D_TXFIFOUNDRN4 field. + USB_DIEPINT4_D_TXFIFOUNDRN4_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN4 field. + USB_DIEPINT4_D_TXFIFOUNDRN4_Msk = 0x100 + // Bit D_TXFIFOUNDRN4. + USB_DIEPINT4_D_TXFIFOUNDRN4 = 0x100 + // Position of D_BNAINTR4 field. + USB_DIEPINT4_D_BNAINTR4_Pos = 0x9 + // Bit mask of D_BNAINTR4 field. + USB_DIEPINT4_D_BNAINTR4_Msk = 0x200 + // Bit D_BNAINTR4. + USB_DIEPINT4_D_BNAINTR4 = 0x200 + // Position of D_PKTDRPSTS4 field. + USB_DIEPINT4_D_PKTDRPSTS4_Pos = 0xb + // Bit mask of D_PKTDRPSTS4 field. + USB_DIEPINT4_D_PKTDRPSTS4_Msk = 0x800 + // Bit D_PKTDRPSTS4. + USB_DIEPINT4_D_PKTDRPSTS4 = 0x800 + // Position of D_BBLEERR4 field. + USB_DIEPINT4_D_BBLEERR4_Pos = 0xc + // Bit mask of D_BBLEERR4 field. + USB_DIEPINT4_D_BBLEERR4_Msk = 0x1000 + // Bit D_BBLEERR4. + USB_DIEPINT4_D_BBLEERR4 = 0x1000 + // Position of D_NAKINTRPT4 field. + USB_DIEPINT4_D_NAKINTRPT4_Pos = 0xd + // Bit mask of D_NAKINTRPT4 field. + USB_DIEPINT4_D_NAKINTRPT4_Msk = 0x2000 + // Bit D_NAKINTRPT4. + USB_DIEPINT4_D_NAKINTRPT4 = 0x2000 + // Position of D_NYETINTRPT4 field. + USB_DIEPINT4_D_NYETINTRPT4_Pos = 0xe + // Bit mask of D_NYETINTRPT4 field. + USB_DIEPINT4_D_NYETINTRPT4_Msk = 0x4000 + // Bit D_NYETINTRPT4. + USB_DIEPINT4_D_NYETINTRPT4 = 0x4000 + + // DIEPTSIZ4 + // Position of D_XFERSIZE4 field. + USB_DIEPTSIZ4_D_XFERSIZE4_Pos = 0x0 + // Bit mask of D_XFERSIZE4 field. + USB_DIEPTSIZ4_D_XFERSIZE4_Msk = 0x7f + // Position of D_PKTCNT4 field. + USB_DIEPTSIZ4_D_PKTCNT4_Pos = 0x13 + // Bit mask of D_PKTCNT4 field. + USB_DIEPTSIZ4_D_PKTCNT4_Msk = 0x180000 + + // DIEPDMA4 + // Position of D_DMAADDR4 field. + USB_DIEPDMA4_D_DMAADDR4_Pos = 0x0 + // Bit mask of D_DMAADDR4 field. + USB_DIEPDMA4_D_DMAADDR4_Msk = 0xffffffff + + // DTXFSTS4 + // Position of D_INEPTXFSPCAVAIL4 field. + USB_DTXFSTS4_D_INEPTXFSPCAVAIL4_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL4 field. + USB_DTXFSTS4_D_INEPTXFSPCAVAIL4_Msk = 0xffff + + // DIEPDMAB4 + // Position of D_DMABUFFERADDR4 field. + USB_DIEPDMAB4_D_DMABUFFERADDR4_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR4 field. + USB_DIEPDMAB4_D_DMABUFFERADDR4_Msk = 0xffffffff + + // DIEPCTL5 + // Position of DI_MPS5 field. + USB_DIEPCTL5_DI_MPS5_Pos = 0x0 + // Bit mask of DI_MPS5 field. + USB_DIEPCTL5_DI_MPS5_Msk = 0x3 + // Position of DI_USBACTEP5 field. + USB_DIEPCTL5_DI_USBACTEP5_Pos = 0xf + // Bit mask of DI_USBACTEP5 field. + USB_DIEPCTL5_DI_USBACTEP5_Msk = 0x8000 + // Bit DI_USBACTEP5. + USB_DIEPCTL5_DI_USBACTEP5 = 0x8000 + // Position of DI_NAKSTS5 field. + USB_DIEPCTL5_DI_NAKSTS5_Pos = 0x11 + // Bit mask of DI_NAKSTS5 field. + USB_DIEPCTL5_DI_NAKSTS5_Msk = 0x20000 + // Bit DI_NAKSTS5. + USB_DIEPCTL5_DI_NAKSTS5 = 0x20000 + // Position of DI_EPTYPE5 field. + USB_DIEPCTL5_DI_EPTYPE5_Pos = 0x12 + // Bit mask of DI_EPTYPE5 field. + USB_DIEPCTL5_DI_EPTYPE5_Msk = 0xc0000 + // Position of DI_STALL5 field. + USB_DIEPCTL5_DI_STALL5_Pos = 0x15 + // Bit mask of DI_STALL5 field. + USB_DIEPCTL5_DI_STALL5_Msk = 0x200000 + // Bit DI_STALL5. + USB_DIEPCTL5_DI_STALL5 = 0x200000 + // Position of DI_TXFNUM5 field. + USB_DIEPCTL5_DI_TXFNUM5_Pos = 0x16 + // Bit mask of DI_TXFNUM5 field. + USB_DIEPCTL5_DI_TXFNUM5_Msk = 0x3c00000 + // Position of DI_CNAK5 field. + USB_DIEPCTL5_DI_CNAK5_Pos = 0x1a + // Bit mask of DI_CNAK5 field. + USB_DIEPCTL5_DI_CNAK5_Msk = 0x4000000 + // Bit DI_CNAK5. + USB_DIEPCTL5_DI_CNAK5 = 0x4000000 + // Position of DI_SNAK5 field. + USB_DIEPCTL5_DI_SNAK5_Pos = 0x1b + // Bit mask of DI_SNAK5 field. + USB_DIEPCTL5_DI_SNAK5_Msk = 0x8000000 + // Bit DI_SNAK5. + USB_DIEPCTL5_DI_SNAK5 = 0x8000000 + // Position of DI_SETD0PID5 field. + USB_DIEPCTL5_DI_SETD0PID5_Pos = 0x1c + // Bit mask of DI_SETD0PID5 field. + USB_DIEPCTL5_DI_SETD0PID5_Msk = 0x10000000 + // Bit DI_SETD0PID5. + USB_DIEPCTL5_DI_SETD0PID5 = 0x10000000 + // Position of DI_SETD1PID5 field. + USB_DIEPCTL5_DI_SETD1PID5_Pos = 0x1d + // Bit mask of DI_SETD1PID5 field. + USB_DIEPCTL5_DI_SETD1PID5_Msk = 0x20000000 + // Bit DI_SETD1PID5. + USB_DIEPCTL5_DI_SETD1PID5 = 0x20000000 + // Position of DI_EPDIS5 field. + USB_DIEPCTL5_DI_EPDIS5_Pos = 0x1e + // Bit mask of DI_EPDIS5 field. + USB_DIEPCTL5_DI_EPDIS5_Msk = 0x40000000 + // Bit DI_EPDIS5. + USB_DIEPCTL5_DI_EPDIS5 = 0x40000000 + // Position of DI_EPENA5 field. + USB_DIEPCTL5_DI_EPENA5_Pos = 0x1f + // Bit mask of DI_EPENA5 field. + USB_DIEPCTL5_DI_EPENA5_Msk = 0x80000000 + // Bit DI_EPENA5. + USB_DIEPCTL5_DI_EPENA5 = 0x80000000 + + // DIEPINT5 + // Position of D_XFERCOMPL5 field. + USB_DIEPINT5_D_XFERCOMPL5_Pos = 0x0 + // Bit mask of D_XFERCOMPL5 field. + USB_DIEPINT5_D_XFERCOMPL5_Msk = 0x1 + // Bit D_XFERCOMPL5. + USB_DIEPINT5_D_XFERCOMPL5 = 0x1 + // Position of D_EPDISBLD5 field. + USB_DIEPINT5_D_EPDISBLD5_Pos = 0x1 + // Bit mask of D_EPDISBLD5 field. + USB_DIEPINT5_D_EPDISBLD5_Msk = 0x2 + // Bit D_EPDISBLD5. + USB_DIEPINT5_D_EPDISBLD5 = 0x2 + // Position of D_AHBERR5 field. + USB_DIEPINT5_D_AHBERR5_Pos = 0x2 + // Bit mask of D_AHBERR5 field. + USB_DIEPINT5_D_AHBERR5_Msk = 0x4 + // Bit D_AHBERR5. + USB_DIEPINT5_D_AHBERR5 = 0x4 + // Position of D_TIMEOUT5 field. + USB_DIEPINT5_D_TIMEOUT5_Pos = 0x3 + // Bit mask of D_TIMEOUT5 field. + USB_DIEPINT5_D_TIMEOUT5_Msk = 0x8 + // Bit D_TIMEOUT5. + USB_DIEPINT5_D_TIMEOUT5 = 0x8 + // Position of D_INTKNTXFEMP5 field. + USB_DIEPINT5_D_INTKNTXFEMP5_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP5 field. + USB_DIEPINT5_D_INTKNTXFEMP5_Msk = 0x10 + // Bit D_INTKNTXFEMP5. + USB_DIEPINT5_D_INTKNTXFEMP5 = 0x10 + // Position of D_INTKNEPMIS5 field. + USB_DIEPINT5_D_INTKNEPMIS5_Pos = 0x5 + // Bit mask of D_INTKNEPMIS5 field. + USB_DIEPINT5_D_INTKNEPMIS5_Msk = 0x20 + // Bit D_INTKNEPMIS5. + USB_DIEPINT5_D_INTKNEPMIS5 = 0x20 + // Position of D_INEPNAKEFF5 field. + USB_DIEPINT5_D_INEPNAKEFF5_Pos = 0x6 + // Bit mask of D_INEPNAKEFF5 field. + USB_DIEPINT5_D_INEPNAKEFF5_Msk = 0x40 + // Bit D_INEPNAKEFF5. + USB_DIEPINT5_D_INEPNAKEFF5 = 0x40 + // Position of D_TXFEMP5 field. + USB_DIEPINT5_D_TXFEMP5_Pos = 0x7 + // Bit mask of D_TXFEMP5 field. + USB_DIEPINT5_D_TXFEMP5_Msk = 0x80 + // Bit D_TXFEMP5. + USB_DIEPINT5_D_TXFEMP5 = 0x80 + // Position of D_TXFIFOUNDRN5 field. + USB_DIEPINT5_D_TXFIFOUNDRN5_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN5 field. + USB_DIEPINT5_D_TXFIFOUNDRN5_Msk = 0x100 + // Bit D_TXFIFOUNDRN5. + USB_DIEPINT5_D_TXFIFOUNDRN5 = 0x100 + // Position of D_BNAINTR5 field. + USB_DIEPINT5_D_BNAINTR5_Pos = 0x9 + // Bit mask of D_BNAINTR5 field. + USB_DIEPINT5_D_BNAINTR5_Msk = 0x200 + // Bit D_BNAINTR5. + USB_DIEPINT5_D_BNAINTR5 = 0x200 + // Position of D_PKTDRPSTS5 field. + USB_DIEPINT5_D_PKTDRPSTS5_Pos = 0xb + // Bit mask of D_PKTDRPSTS5 field. + USB_DIEPINT5_D_PKTDRPSTS5_Msk = 0x800 + // Bit D_PKTDRPSTS5. + USB_DIEPINT5_D_PKTDRPSTS5 = 0x800 + // Position of D_BBLEERR5 field. + USB_DIEPINT5_D_BBLEERR5_Pos = 0xc + // Bit mask of D_BBLEERR5 field. + USB_DIEPINT5_D_BBLEERR5_Msk = 0x1000 + // Bit D_BBLEERR5. + USB_DIEPINT5_D_BBLEERR5 = 0x1000 + // Position of D_NAKINTRPT5 field. + USB_DIEPINT5_D_NAKINTRPT5_Pos = 0xd + // Bit mask of D_NAKINTRPT5 field. + USB_DIEPINT5_D_NAKINTRPT5_Msk = 0x2000 + // Bit D_NAKINTRPT5. + USB_DIEPINT5_D_NAKINTRPT5 = 0x2000 + // Position of D_NYETINTRPT5 field. + USB_DIEPINT5_D_NYETINTRPT5_Pos = 0xe + // Bit mask of D_NYETINTRPT5 field. + USB_DIEPINT5_D_NYETINTRPT5_Msk = 0x4000 + // Bit D_NYETINTRPT5. + USB_DIEPINT5_D_NYETINTRPT5 = 0x4000 + + // DIEPTSIZ5 + // Position of D_XFERSIZE5 field. + USB_DIEPTSIZ5_D_XFERSIZE5_Pos = 0x0 + // Bit mask of D_XFERSIZE5 field. + USB_DIEPTSIZ5_D_XFERSIZE5_Msk = 0x7f + // Position of D_PKTCNT5 field. + USB_DIEPTSIZ5_D_PKTCNT5_Pos = 0x13 + // Bit mask of D_PKTCNT5 field. + USB_DIEPTSIZ5_D_PKTCNT5_Msk = 0x180000 + + // DIEPDMA5 + // Position of D_DMAADDR5 field. + USB_DIEPDMA5_D_DMAADDR5_Pos = 0x0 + // Bit mask of D_DMAADDR5 field. + USB_DIEPDMA5_D_DMAADDR5_Msk = 0xffffffff + + // DTXFSTS5 + // Position of D_INEPTXFSPCAVAIL5 field. + USB_DTXFSTS5_D_INEPTXFSPCAVAIL5_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL5 field. + USB_DTXFSTS5_D_INEPTXFSPCAVAIL5_Msk = 0xffff + + // DIEPDMAB5 + // Position of D_DMABUFFERADDR5 field. + USB_DIEPDMAB5_D_DMABUFFERADDR5_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR5 field. + USB_DIEPDMAB5_D_DMABUFFERADDR5_Msk = 0xffffffff + + // DIEPCTL6 + // Position of D_MPS6 field. + USB_DIEPCTL6_D_MPS6_Pos = 0x0 + // Bit mask of D_MPS6 field. + USB_DIEPCTL6_D_MPS6_Msk = 0x3 + // Position of D_USBACTEP6 field. + USB_DIEPCTL6_D_USBACTEP6_Pos = 0xf + // Bit mask of D_USBACTEP6 field. + USB_DIEPCTL6_D_USBACTEP6_Msk = 0x8000 + // Bit D_USBACTEP6. + USB_DIEPCTL6_D_USBACTEP6 = 0x8000 + // Position of D_NAKSTS6 field. + USB_DIEPCTL6_D_NAKSTS6_Pos = 0x11 + // Bit mask of D_NAKSTS6 field. + USB_DIEPCTL6_D_NAKSTS6_Msk = 0x20000 + // Bit D_NAKSTS6. + USB_DIEPCTL6_D_NAKSTS6 = 0x20000 + // Position of D_EPTYPE6 field. + USB_DIEPCTL6_D_EPTYPE6_Pos = 0x12 + // Bit mask of D_EPTYPE6 field. + USB_DIEPCTL6_D_EPTYPE6_Msk = 0xc0000 + // Position of D_STALL6 field. + USB_DIEPCTL6_D_STALL6_Pos = 0x15 + // Bit mask of D_STALL6 field. + USB_DIEPCTL6_D_STALL6_Msk = 0x200000 + // Bit D_STALL6. + USB_DIEPCTL6_D_STALL6 = 0x200000 + // Position of D_TXFNUM6 field. + USB_DIEPCTL6_D_TXFNUM6_Pos = 0x16 + // Bit mask of D_TXFNUM6 field. + USB_DIEPCTL6_D_TXFNUM6_Msk = 0x3c00000 + // Position of D_CNAK6 field. + USB_DIEPCTL6_D_CNAK6_Pos = 0x1a + // Bit mask of D_CNAK6 field. + USB_DIEPCTL6_D_CNAK6_Msk = 0x4000000 + // Bit D_CNAK6. + USB_DIEPCTL6_D_CNAK6 = 0x4000000 + // Position of DI_SNAK6 field. + USB_DIEPCTL6_DI_SNAK6_Pos = 0x1b + // Bit mask of DI_SNAK6 field. + USB_DIEPCTL6_DI_SNAK6_Msk = 0x8000000 + // Bit DI_SNAK6. + USB_DIEPCTL6_DI_SNAK6 = 0x8000000 + // Position of DI_SETD0PID6 field. + USB_DIEPCTL6_DI_SETD0PID6_Pos = 0x1c + // Bit mask of DI_SETD0PID6 field. + USB_DIEPCTL6_DI_SETD0PID6_Msk = 0x10000000 + // Bit DI_SETD0PID6. + USB_DIEPCTL6_DI_SETD0PID6 = 0x10000000 + // Position of DI_SETD1PID6 field. + USB_DIEPCTL6_DI_SETD1PID6_Pos = 0x1d + // Bit mask of DI_SETD1PID6 field. + USB_DIEPCTL6_DI_SETD1PID6_Msk = 0x20000000 + // Bit DI_SETD1PID6. + USB_DIEPCTL6_DI_SETD1PID6 = 0x20000000 + // Position of D_EPDIS6 field. + USB_DIEPCTL6_D_EPDIS6_Pos = 0x1e + // Bit mask of D_EPDIS6 field. + USB_DIEPCTL6_D_EPDIS6_Msk = 0x40000000 + // Bit D_EPDIS6. + USB_DIEPCTL6_D_EPDIS6 = 0x40000000 + // Position of D_EPENA6 field. + USB_DIEPCTL6_D_EPENA6_Pos = 0x1f + // Bit mask of D_EPENA6 field. + USB_DIEPCTL6_D_EPENA6_Msk = 0x80000000 + // Bit D_EPENA6. + USB_DIEPCTL6_D_EPENA6 = 0x80000000 + + // DIEPINT6 + // Position of D_XFERCOMPL6 field. + USB_DIEPINT6_D_XFERCOMPL6_Pos = 0x0 + // Bit mask of D_XFERCOMPL6 field. + USB_DIEPINT6_D_XFERCOMPL6_Msk = 0x1 + // Bit D_XFERCOMPL6. + USB_DIEPINT6_D_XFERCOMPL6 = 0x1 + // Position of D_EPDISBLD6 field. + USB_DIEPINT6_D_EPDISBLD6_Pos = 0x1 + // Bit mask of D_EPDISBLD6 field. + USB_DIEPINT6_D_EPDISBLD6_Msk = 0x2 + // Bit D_EPDISBLD6. + USB_DIEPINT6_D_EPDISBLD6 = 0x2 + // Position of D_AHBERR6 field. + USB_DIEPINT6_D_AHBERR6_Pos = 0x2 + // Bit mask of D_AHBERR6 field. + USB_DIEPINT6_D_AHBERR6_Msk = 0x4 + // Bit D_AHBERR6. + USB_DIEPINT6_D_AHBERR6 = 0x4 + // Position of D_TIMEOUT6 field. + USB_DIEPINT6_D_TIMEOUT6_Pos = 0x3 + // Bit mask of D_TIMEOUT6 field. + USB_DIEPINT6_D_TIMEOUT6_Msk = 0x8 + // Bit D_TIMEOUT6. + USB_DIEPINT6_D_TIMEOUT6 = 0x8 + // Position of D_INTKNTXFEMP6 field. + USB_DIEPINT6_D_INTKNTXFEMP6_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP6 field. + USB_DIEPINT6_D_INTKNTXFEMP6_Msk = 0x10 + // Bit D_INTKNTXFEMP6. + USB_DIEPINT6_D_INTKNTXFEMP6 = 0x10 + // Position of D_INTKNEPMIS6 field. + USB_DIEPINT6_D_INTKNEPMIS6_Pos = 0x5 + // Bit mask of D_INTKNEPMIS6 field. + USB_DIEPINT6_D_INTKNEPMIS6_Msk = 0x20 + // Bit D_INTKNEPMIS6. + USB_DIEPINT6_D_INTKNEPMIS6 = 0x20 + // Position of D_INEPNAKEFF6 field. + USB_DIEPINT6_D_INEPNAKEFF6_Pos = 0x6 + // Bit mask of D_INEPNAKEFF6 field. + USB_DIEPINT6_D_INEPNAKEFF6_Msk = 0x40 + // Bit D_INEPNAKEFF6. + USB_DIEPINT6_D_INEPNAKEFF6 = 0x40 + // Position of D_TXFEMP6 field. + USB_DIEPINT6_D_TXFEMP6_Pos = 0x7 + // Bit mask of D_TXFEMP6 field. + USB_DIEPINT6_D_TXFEMP6_Msk = 0x80 + // Bit D_TXFEMP6. + USB_DIEPINT6_D_TXFEMP6 = 0x80 + // Position of D_TXFIFOUNDRN6 field. + USB_DIEPINT6_D_TXFIFOUNDRN6_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN6 field. + USB_DIEPINT6_D_TXFIFOUNDRN6_Msk = 0x100 + // Bit D_TXFIFOUNDRN6. + USB_DIEPINT6_D_TXFIFOUNDRN6 = 0x100 + // Position of D_BNAINTR6 field. + USB_DIEPINT6_D_BNAINTR6_Pos = 0x9 + // Bit mask of D_BNAINTR6 field. + USB_DIEPINT6_D_BNAINTR6_Msk = 0x200 + // Bit D_BNAINTR6. + USB_DIEPINT6_D_BNAINTR6 = 0x200 + // Position of D_PKTDRPSTS6 field. + USB_DIEPINT6_D_PKTDRPSTS6_Pos = 0xb + // Bit mask of D_PKTDRPSTS6 field. + USB_DIEPINT6_D_PKTDRPSTS6_Msk = 0x800 + // Bit D_PKTDRPSTS6. + USB_DIEPINT6_D_PKTDRPSTS6 = 0x800 + // Position of D_BBLEERR6 field. + USB_DIEPINT6_D_BBLEERR6_Pos = 0xc + // Bit mask of D_BBLEERR6 field. + USB_DIEPINT6_D_BBLEERR6_Msk = 0x1000 + // Bit D_BBLEERR6. + USB_DIEPINT6_D_BBLEERR6 = 0x1000 + // Position of D_NAKINTRPT6 field. + USB_DIEPINT6_D_NAKINTRPT6_Pos = 0xd + // Bit mask of D_NAKINTRPT6 field. + USB_DIEPINT6_D_NAKINTRPT6_Msk = 0x2000 + // Bit D_NAKINTRPT6. + USB_DIEPINT6_D_NAKINTRPT6 = 0x2000 + // Position of D_NYETINTRPT6 field. + USB_DIEPINT6_D_NYETINTRPT6_Pos = 0xe + // Bit mask of D_NYETINTRPT6 field. + USB_DIEPINT6_D_NYETINTRPT6_Msk = 0x4000 + // Bit D_NYETINTRPT6. + USB_DIEPINT6_D_NYETINTRPT6 = 0x4000 + + // DIEPTSIZ6 + // Position of D_XFERSIZE6 field. + USB_DIEPTSIZ6_D_XFERSIZE6_Pos = 0x0 + // Bit mask of D_XFERSIZE6 field. + USB_DIEPTSIZ6_D_XFERSIZE6_Msk = 0x7f + // Position of D_PKTCNT6 field. + USB_DIEPTSIZ6_D_PKTCNT6_Pos = 0x13 + // Bit mask of D_PKTCNT6 field. + USB_DIEPTSIZ6_D_PKTCNT6_Msk = 0x180000 + + // DIEPDMA6 + // Position of D_DMAADDR6 field. + USB_DIEPDMA6_D_DMAADDR6_Pos = 0x0 + // Bit mask of D_DMAADDR6 field. + USB_DIEPDMA6_D_DMAADDR6_Msk = 0xffffffff + + // DTXFSTS6 + // Position of D_INEPTXFSPCAVAIL6 field. + USB_DTXFSTS6_D_INEPTXFSPCAVAIL6_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL6 field. + USB_DTXFSTS6_D_INEPTXFSPCAVAIL6_Msk = 0xffff + + // DIEPDMAB6 + // Position of D_DMABUFFERADDR6 field. + USB_DIEPDMAB6_D_DMABUFFERADDR6_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR6 field. + USB_DIEPDMAB6_D_DMABUFFERADDR6_Msk = 0xffffffff + + // DOEPCTL0 + // Position of MPS0 field. + USB_DOEPCTL0_MPS0_Pos = 0x0 + // Bit mask of MPS0 field. + USB_DOEPCTL0_MPS0_Msk = 0x3 + // Position of USBACTEP0 field. + USB_DOEPCTL0_USBACTEP0_Pos = 0xf + // Bit mask of USBACTEP0 field. + USB_DOEPCTL0_USBACTEP0_Msk = 0x8000 + // Bit USBACTEP0. + USB_DOEPCTL0_USBACTEP0 = 0x8000 + // Position of NAKSTS0 field. + USB_DOEPCTL0_NAKSTS0_Pos = 0x11 + // Bit mask of NAKSTS0 field. + USB_DOEPCTL0_NAKSTS0_Msk = 0x20000 + // Bit NAKSTS0. + USB_DOEPCTL0_NAKSTS0 = 0x20000 + // Position of EPTYPE0 field. + USB_DOEPCTL0_EPTYPE0_Pos = 0x12 + // Bit mask of EPTYPE0 field. + USB_DOEPCTL0_EPTYPE0_Msk = 0xc0000 + // Position of SNP0 field. + USB_DOEPCTL0_SNP0_Pos = 0x14 + // Bit mask of SNP0 field. + USB_DOEPCTL0_SNP0_Msk = 0x100000 + // Bit SNP0. + USB_DOEPCTL0_SNP0 = 0x100000 + // Position of STALL0 field. + USB_DOEPCTL0_STALL0_Pos = 0x15 + // Bit mask of STALL0 field. + USB_DOEPCTL0_STALL0_Msk = 0x200000 + // Bit STALL0. + USB_DOEPCTL0_STALL0 = 0x200000 + // Position of CNAK0 field. + USB_DOEPCTL0_CNAK0_Pos = 0x1a + // Bit mask of CNAK0 field. + USB_DOEPCTL0_CNAK0_Msk = 0x4000000 + // Bit CNAK0. + USB_DOEPCTL0_CNAK0 = 0x4000000 + // Position of DO_SNAK0 field. + USB_DOEPCTL0_DO_SNAK0_Pos = 0x1b + // Bit mask of DO_SNAK0 field. + USB_DOEPCTL0_DO_SNAK0_Msk = 0x8000000 + // Bit DO_SNAK0. + USB_DOEPCTL0_DO_SNAK0 = 0x8000000 + // Position of EPDIS0 field. + USB_DOEPCTL0_EPDIS0_Pos = 0x1e + // Bit mask of EPDIS0 field. + USB_DOEPCTL0_EPDIS0_Msk = 0x40000000 + // Bit EPDIS0. + USB_DOEPCTL0_EPDIS0 = 0x40000000 + // Position of EPENA0 field. + USB_DOEPCTL0_EPENA0_Pos = 0x1f + // Bit mask of EPENA0 field. + USB_DOEPCTL0_EPENA0_Msk = 0x80000000 + // Bit EPENA0. + USB_DOEPCTL0_EPENA0 = 0x80000000 + + // DOEPINT0 + // Position of XFERCOMPL0 field. + USB_DOEPINT0_XFERCOMPL0_Pos = 0x0 + // Bit mask of XFERCOMPL0 field. + USB_DOEPINT0_XFERCOMPL0_Msk = 0x1 + // Bit XFERCOMPL0. + USB_DOEPINT0_XFERCOMPL0 = 0x1 + // Position of EPDISBLD0 field. + USB_DOEPINT0_EPDISBLD0_Pos = 0x1 + // Bit mask of EPDISBLD0 field. + USB_DOEPINT0_EPDISBLD0_Msk = 0x2 + // Bit EPDISBLD0. + USB_DOEPINT0_EPDISBLD0 = 0x2 + // Position of AHBERR0 field. + USB_DOEPINT0_AHBERR0_Pos = 0x2 + // Bit mask of AHBERR0 field. + USB_DOEPINT0_AHBERR0_Msk = 0x4 + // Bit AHBERR0. + USB_DOEPINT0_AHBERR0 = 0x4 + // Position of SETUP0 field. + USB_DOEPINT0_SETUP0_Pos = 0x3 + // Bit mask of SETUP0 field. + USB_DOEPINT0_SETUP0_Msk = 0x8 + // Bit SETUP0. + USB_DOEPINT0_SETUP0 = 0x8 + // Position of OUTTKNEPDIS0 field. + USB_DOEPINT0_OUTTKNEPDIS0_Pos = 0x4 + // Bit mask of OUTTKNEPDIS0 field. + USB_DOEPINT0_OUTTKNEPDIS0_Msk = 0x10 + // Bit OUTTKNEPDIS0. + USB_DOEPINT0_OUTTKNEPDIS0 = 0x10 + // Position of STSPHSERCVD0 field. + USB_DOEPINT0_STSPHSERCVD0_Pos = 0x5 + // Bit mask of STSPHSERCVD0 field. + USB_DOEPINT0_STSPHSERCVD0_Msk = 0x20 + // Bit STSPHSERCVD0. + USB_DOEPINT0_STSPHSERCVD0 = 0x20 + // Position of BACK2BACKSETUP0 field. + USB_DOEPINT0_BACK2BACKSETUP0_Pos = 0x6 + // Bit mask of BACK2BACKSETUP0 field. + USB_DOEPINT0_BACK2BACKSETUP0_Msk = 0x40 + // Bit BACK2BACKSETUP0. + USB_DOEPINT0_BACK2BACKSETUP0 = 0x40 + // Position of OUTPKTERR0 field. + USB_DOEPINT0_OUTPKTERR0_Pos = 0x8 + // Bit mask of OUTPKTERR0 field. + USB_DOEPINT0_OUTPKTERR0_Msk = 0x100 + // Bit OUTPKTERR0. + USB_DOEPINT0_OUTPKTERR0 = 0x100 + // Position of BNAINTR0 field. + USB_DOEPINT0_BNAINTR0_Pos = 0x9 + // Bit mask of BNAINTR0 field. + USB_DOEPINT0_BNAINTR0_Msk = 0x200 + // Bit BNAINTR0. + USB_DOEPINT0_BNAINTR0 = 0x200 + // Position of PKTDRPSTS0 field. + USB_DOEPINT0_PKTDRPSTS0_Pos = 0xb + // Bit mask of PKTDRPSTS0 field. + USB_DOEPINT0_PKTDRPSTS0_Msk = 0x800 + // Bit PKTDRPSTS0. + USB_DOEPINT0_PKTDRPSTS0 = 0x800 + // Position of BBLEERR0 field. + USB_DOEPINT0_BBLEERR0_Pos = 0xc + // Bit mask of BBLEERR0 field. + USB_DOEPINT0_BBLEERR0_Msk = 0x1000 + // Bit BBLEERR0. + USB_DOEPINT0_BBLEERR0 = 0x1000 + // Position of NAKINTRPT0 field. + USB_DOEPINT0_NAKINTRPT0_Pos = 0xd + // Bit mask of NAKINTRPT0 field. + USB_DOEPINT0_NAKINTRPT0_Msk = 0x2000 + // Bit NAKINTRPT0. + USB_DOEPINT0_NAKINTRPT0 = 0x2000 + // Position of NYEPINTRPT0 field. + USB_DOEPINT0_NYEPINTRPT0_Pos = 0xe + // Bit mask of NYEPINTRPT0 field. + USB_DOEPINT0_NYEPINTRPT0_Msk = 0x4000 + // Bit NYEPINTRPT0. + USB_DOEPINT0_NYEPINTRPT0 = 0x4000 + // Position of STUPPKTRCVD0 field. + USB_DOEPINT0_STUPPKTRCVD0_Pos = 0xf + // Bit mask of STUPPKTRCVD0 field. + USB_DOEPINT0_STUPPKTRCVD0_Msk = 0x8000 + // Bit STUPPKTRCVD0. + USB_DOEPINT0_STUPPKTRCVD0 = 0x8000 + + // DOEPTSIZ0 + // Position of XFERSIZE0 field. + USB_DOEPTSIZ0_XFERSIZE0_Pos = 0x0 + // Bit mask of XFERSIZE0 field. + USB_DOEPTSIZ0_XFERSIZE0_Msk = 0x7f + // Position of PKTCNT0 field. + USB_DOEPTSIZ0_PKTCNT0_Pos = 0x13 + // Bit mask of PKTCNT0 field. + USB_DOEPTSIZ0_PKTCNT0_Msk = 0x80000 + // Bit PKTCNT0. + USB_DOEPTSIZ0_PKTCNT0 = 0x80000 + // Position of SUPCNT0 field. + USB_DOEPTSIZ0_SUPCNT0_Pos = 0x1d + // Bit mask of SUPCNT0 field. + USB_DOEPTSIZ0_SUPCNT0_Msk = 0x60000000 + + // DOEPDMA0 + // Position of DMAADDR0 field. + USB_DOEPDMA0_DMAADDR0_Pos = 0x0 + // Bit mask of DMAADDR0 field. + USB_DOEPDMA0_DMAADDR0_Msk = 0xffffffff + + // DOEPDMAB0 + // Position of DMABUFFERADDR0 field. + USB_DOEPDMAB0_DMABUFFERADDR0_Pos = 0x0 + // Bit mask of DMABUFFERADDR0 field. + USB_DOEPDMAB0_DMABUFFERADDR0_Msk = 0xffffffff + + // DOEPCTL1 + // Position of MPS1 field. + USB_DOEPCTL1_MPS1_Pos = 0x0 + // Bit mask of MPS1 field. + USB_DOEPCTL1_MPS1_Msk = 0x7ff + // Position of USBACTEP1 field. + USB_DOEPCTL1_USBACTEP1_Pos = 0xf + // Bit mask of USBACTEP1 field. + USB_DOEPCTL1_USBACTEP1_Msk = 0x8000 + // Bit USBACTEP1. + USB_DOEPCTL1_USBACTEP1 = 0x8000 + // Position of NAKSTS1 field. + USB_DOEPCTL1_NAKSTS1_Pos = 0x11 + // Bit mask of NAKSTS1 field. + USB_DOEPCTL1_NAKSTS1_Msk = 0x20000 + // Bit NAKSTS1. + USB_DOEPCTL1_NAKSTS1 = 0x20000 + // Position of EPTYPE1 field. + USB_DOEPCTL1_EPTYPE1_Pos = 0x12 + // Bit mask of EPTYPE1 field. + USB_DOEPCTL1_EPTYPE1_Msk = 0xc0000 + // Position of SNP1 field. + USB_DOEPCTL1_SNP1_Pos = 0x14 + // Bit mask of SNP1 field. + USB_DOEPCTL1_SNP1_Msk = 0x100000 + // Bit SNP1. + USB_DOEPCTL1_SNP1 = 0x100000 + // Position of STALL1 field. + USB_DOEPCTL1_STALL1_Pos = 0x15 + // Bit mask of STALL1 field. + USB_DOEPCTL1_STALL1_Msk = 0x200000 + // Bit STALL1. + USB_DOEPCTL1_STALL1 = 0x200000 + // Position of CNAK1 field. + USB_DOEPCTL1_CNAK1_Pos = 0x1a + // Bit mask of CNAK1 field. + USB_DOEPCTL1_CNAK1_Msk = 0x4000000 + // Bit CNAK1. + USB_DOEPCTL1_CNAK1 = 0x4000000 + // Position of DO_SNAK1 field. + USB_DOEPCTL1_DO_SNAK1_Pos = 0x1b + // Bit mask of DO_SNAK1 field. + USB_DOEPCTL1_DO_SNAK1_Msk = 0x8000000 + // Bit DO_SNAK1. + USB_DOEPCTL1_DO_SNAK1 = 0x8000000 + // Position of DO_SETD0PID1 field. + USB_DOEPCTL1_DO_SETD0PID1_Pos = 0x1c + // Bit mask of DO_SETD0PID1 field. + USB_DOEPCTL1_DO_SETD0PID1_Msk = 0x10000000 + // Bit DO_SETD0PID1. + USB_DOEPCTL1_DO_SETD0PID1 = 0x10000000 + // Position of DO_SETD1PID1 field. + USB_DOEPCTL1_DO_SETD1PID1_Pos = 0x1d + // Bit mask of DO_SETD1PID1 field. + USB_DOEPCTL1_DO_SETD1PID1_Msk = 0x20000000 + // Bit DO_SETD1PID1. + USB_DOEPCTL1_DO_SETD1PID1 = 0x20000000 + // Position of EPDIS1 field. + USB_DOEPCTL1_EPDIS1_Pos = 0x1e + // Bit mask of EPDIS1 field. + USB_DOEPCTL1_EPDIS1_Msk = 0x40000000 + // Bit EPDIS1. + USB_DOEPCTL1_EPDIS1 = 0x40000000 + // Position of EPENA1 field. + USB_DOEPCTL1_EPENA1_Pos = 0x1f + // Bit mask of EPENA1 field. + USB_DOEPCTL1_EPENA1_Msk = 0x80000000 + // Bit EPENA1. + USB_DOEPCTL1_EPENA1 = 0x80000000 + + // DOEPINT1 + // Position of XFERCOMPL1 field. + USB_DOEPINT1_XFERCOMPL1_Pos = 0x0 + // Bit mask of XFERCOMPL1 field. + USB_DOEPINT1_XFERCOMPL1_Msk = 0x1 + // Bit XFERCOMPL1. + USB_DOEPINT1_XFERCOMPL1 = 0x1 + // Position of EPDISBLD1 field. + USB_DOEPINT1_EPDISBLD1_Pos = 0x1 + // Bit mask of EPDISBLD1 field. + USB_DOEPINT1_EPDISBLD1_Msk = 0x2 + // Bit EPDISBLD1. + USB_DOEPINT1_EPDISBLD1 = 0x2 + // Position of AHBERR1 field. + USB_DOEPINT1_AHBERR1_Pos = 0x2 + // Bit mask of AHBERR1 field. + USB_DOEPINT1_AHBERR1_Msk = 0x4 + // Bit AHBERR1. + USB_DOEPINT1_AHBERR1 = 0x4 + // Position of SETUP1 field. + USB_DOEPINT1_SETUP1_Pos = 0x3 + // Bit mask of SETUP1 field. + USB_DOEPINT1_SETUP1_Msk = 0x8 + // Bit SETUP1. + USB_DOEPINT1_SETUP1 = 0x8 + // Position of OUTTKNEPDIS1 field. + USB_DOEPINT1_OUTTKNEPDIS1_Pos = 0x4 + // Bit mask of OUTTKNEPDIS1 field. + USB_DOEPINT1_OUTTKNEPDIS1_Msk = 0x10 + // Bit OUTTKNEPDIS1. + USB_DOEPINT1_OUTTKNEPDIS1 = 0x10 + // Position of STSPHSERCVD1 field. + USB_DOEPINT1_STSPHSERCVD1_Pos = 0x5 + // Bit mask of STSPHSERCVD1 field. + USB_DOEPINT1_STSPHSERCVD1_Msk = 0x20 + // Bit STSPHSERCVD1. + USB_DOEPINT1_STSPHSERCVD1 = 0x20 + // Position of BACK2BACKSETUP1 field. + USB_DOEPINT1_BACK2BACKSETUP1_Pos = 0x6 + // Bit mask of BACK2BACKSETUP1 field. + USB_DOEPINT1_BACK2BACKSETUP1_Msk = 0x40 + // Bit BACK2BACKSETUP1. + USB_DOEPINT1_BACK2BACKSETUP1 = 0x40 + // Position of OUTPKTERR1 field. + USB_DOEPINT1_OUTPKTERR1_Pos = 0x8 + // Bit mask of OUTPKTERR1 field. + USB_DOEPINT1_OUTPKTERR1_Msk = 0x100 + // Bit OUTPKTERR1. + USB_DOEPINT1_OUTPKTERR1 = 0x100 + // Position of BNAINTR1 field. + USB_DOEPINT1_BNAINTR1_Pos = 0x9 + // Bit mask of BNAINTR1 field. + USB_DOEPINT1_BNAINTR1_Msk = 0x200 + // Bit BNAINTR1. + USB_DOEPINT1_BNAINTR1 = 0x200 + // Position of PKTDRPSTS1 field. + USB_DOEPINT1_PKTDRPSTS1_Pos = 0xb + // Bit mask of PKTDRPSTS1 field. + USB_DOEPINT1_PKTDRPSTS1_Msk = 0x800 + // Bit PKTDRPSTS1. + USB_DOEPINT1_PKTDRPSTS1 = 0x800 + // Position of BBLEERR1 field. + USB_DOEPINT1_BBLEERR1_Pos = 0xc + // Bit mask of BBLEERR1 field. + USB_DOEPINT1_BBLEERR1_Msk = 0x1000 + // Bit BBLEERR1. + USB_DOEPINT1_BBLEERR1 = 0x1000 + // Position of NAKINTRPT1 field. + USB_DOEPINT1_NAKINTRPT1_Pos = 0xd + // Bit mask of NAKINTRPT1 field. + USB_DOEPINT1_NAKINTRPT1_Msk = 0x2000 + // Bit NAKINTRPT1. + USB_DOEPINT1_NAKINTRPT1 = 0x2000 + // Position of NYEPINTRPT1 field. + USB_DOEPINT1_NYEPINTRPT1_Pos = 0xe + // Bit mask of NYEPINTRPT1 field. + USB_DOEPINT1_NYEPINTRPT1_Msk = 0x4000 + // Bit NYEPINTRPT1. + USB_DOEPINT1_NYEPINTRPT1 = 0x4000 + // Position of STUPPKTRCVD1 field. + USB_DOEPINT1_STUPPKTRCVD1_Pos = 0xf + // Bit mask of STUPPKTRCVD1 field. + USB_DOEPINT1_STUPPKTRCVD1_Msk = 0x8000 + // Bit STUPPKTRCVD1. + USB_DOEPINT1_STUPPKTRCVD1 = 0x8000 + + // DOEPTSIZ1 + // Position of XFERSIZE1 field. + USB_DOEPTSIZ1_XFERSIZE1_Pos = 0x0 + // Bit mask of XFERSIZE1 field. + USB_DOEPTSIZ1_XFERSIZE1_Msk = 0x7f + // Position of PKTCNT1 field. + USB_DOEPTSIZ1_PKTCNT1_Pos = 0x13 + // Bit mask of PKTCNT1 field. + USB_DOEPTSIZ1_PKTCNT1_Msk = 0x80000 + // Bit PKTCNT1. + USB_DOEPTSIZ1_PKTCNT1 = 0x80000 + // Position of SUPCNT1 field. + USB_DOEPTSIZ1_SUPCNT1_Pos = 0x1d + // Bit mask of SUPCNT1 field. + USB_DOEPTSIZ1_SUPCNT1_Msk = 0x60000000 + + // DOEPDMA1 + // Position of DMAADDR1 field. + USB_DOEPDMA1_DMAADDR1_Pos = 0x0 + // Bit mask of DMAADDR1 field. + USB_DOEPDMA1_DMAADDR1_Msk = 0xffffffff + + // DOEPDMAB1 + // Position of DMABUFFERADDR1 field. + USB_DOEPDMAB1_DMABUFFERADDR1_Pos = 0x0 + // Bit mask of DMABUFFERADDR1 field. + USB_DOEPDMAB1_DMABUFFERADDR1_Msk = 0xffffffff + + // DOEPCTL2 + // Position of MPS2 field. + USB_DOEPCTL2_MPS2_Pos = 0x0 + // Bit mask of MPS2 field. + USB_DOEPCTL2_MPS2_Msk = 0x7ff + // Position of USBACTEP2 field. + USB_DOEPCTL2_USBACTEP2_Pos = 0xf + // Bit mask of USBACTEP2 field. + USB_DOEPCTL2_USBACTEP2_Msk = 0x8000 + // Bit USBACTEP2. + USB_DOEPCTL2_USBACTEP2 = 0x8000 + // Position of NAKSTS2 field. + USB_DOEPCTL2_NAKSTS2_Pos = 0x11 + // Bit mask of NAKSTS2 field. + USB_DOEPCTL2_NAKSTS2_Msk = 0x20000 + // Bit NAKSTS2. + USB_DOEPCTL2_NAKSTS2 = 0x20000 + // Position of EPTYPE2 field. + USB_DOEPCTL2_EPTYPE2_Pos = 0x12 + // Bit mask of EPTYPE2 field. + USB_DOEPCTL2_EPTYPE2_Msk = 0xc0000 + // Position of SNP2 field. + USB_DOEPCTL2_SNP2_Pos = 0x14 + // Bit mask of SNP2 field. + USB_DOEPCTL2_SNP2_Msk = 0x100000 + // Bit SNP2. + USB_DOEPCTL2_SNP2 = 0x100000 + // Position of STALL2 field. + USB_DOEPCTL2_STALL2_Pos = 0x15 + // Bit mask of STALL2 field. + USB_DOEPCTL2_STALL2_Msk = 0x200000 + // Bit STALL2. + USB_DOEPCTL2_STALL2 = 0x200000 + // Position of CNAK2 field. + USB_DOEPCTL2_CNAK2_Pos = 0x1a + // Bit mask of CNAK2 field. + USB_DOEPCTL2_CNAK2_Msk = 0x4000000 + // Bit CNAK2. + USB_DOEPCTL2_CNAK2 = 0x4000000 + // Position of DO_SNAK2 field. + USB_DOEPCTL2_DO_SNAK2_Pos = 0x1b + // Bit mask of DO_SNAK2 field. + USB_DOEPCTL2_DO_SNAK2_Msk = 0x8000000 + // Bit DO_SNAK2. + USB_DOEPCTL2_DO_SNAK2 = 0x8000000 + // Position of DO_SETD0PID2 field. + USB_DOEPCTL2_DO_SETD0PID2_Pos = 0x1c + // Bit mask of DO_SETD0PID2 field. + USB_DOEPCTL2_DO_SETD0PID2_Msk = 0x10000000 + // Bit DO_SETD0PID2. + USB_DOEPCTL2_DO_SETD0PID2 = 0x10000000 + // Position of DO_SETD1PID2 field. + USB_DOEPCTL2_DO_SETD1PID2_Pos = 0x1d + // Bit mask of DO_SETD1PID2 field. + USB_DOEPCTL2_DO_SETD1PID2_Msk = 0x20000000 + // Bit DO_SETD1PID2. + USB_DOEPCTL2_DO_SETD1PID2 = 0x20000000 + // Position of EPDIS2 field. + USB_DOEPCTL2_EPDIS2_Pos = 0x1e + // Bit mask of EPDIS2 field. + USB_DOEPCTL2_EPDIS2_Msk = 0x40000000 + // Bit EPDIS2. + USB_DOEPCTL2_EPDIS2 = 0x40000000 + // Position of EPENA2 field. + USB_DOEPCTL2_EPENA2_Pos = 0x1f + // Bit mask of EPENA2 field. + USB_DOEPCTL2_EPENA2_Msk = 0x80000000 + // Bit EPENA2. + USB_DOEPCTL2_EPENA2 = 0x80000000 + + // DOEPINT2 + // Position of XFERCOMPL2 field. + USB_DOEPINT2_XFERCOMPL2_Pos = 0x0 + // Bit mask of XFERCOMPL2 field. + USB_DOEPINT2_XFERCOMPL2_Msk = 0x1 + // Bit XFERCOMPL2. + USB_DOEPINT2_XFERCOMPL2 = 0x1 + // Position of EPDISBLD2 field. + USB_DOEPINT2_EPDISBLD2_Pos = 0x1 + // Bit mask of EPDISBLD2 field. + USB_DOEPINT2_EPDISBLD2_Msk = 0x2 + // Bit EPDISBLD2. + USB_DOEPINT2_EPDISBLD2 = 0x2 + // Position of AHBERR2 field. + USB_DOEPINT2_AHBERR2_Pos = 0x2 + // Bit mask of AHBERR2 field. + USB_DOEPINT2_AHBERR2_Msk = 0x4 + // Bit AHBERR2. + USB_DOEPINT2_AHBERR2 = 0x4 + // Position of SETUP2 field. + USB_DOEPINT2_SETUP2_Pos = 0x3 + // Bit mask of SETUP2 field. + USB_DOEPINT2_SETUP2_Msk = 0x8 + // Bit SETUP2. + USB_DOEPINT2_SETUP2 = 0x8 + // Position of OUTTKNEPDIS2 field. + USB_DOEPINT2_OUTTKNEPDIS2_Pos = 0x4 + // Bit mask of OUTTKNEPDIS2 field. + USB_DOEPINT2_OUTTKNEPDIS2_Msk = 0x10 + // Bit OUTTKNEPDIS2. + USB_DOEPINT2_OUTTKNEPDIS2 = 0x10 + // Position of STSPHSERCVD2 field. + USB_DOEPINT2_STSPHSERCVD2_Pos = 0x5 + // Bit mask of STSPHSERCVD2 field. + USB_DOEPINT2_STSPHSERCVD2_Msk = 0x20 + // Bit STSPHSERCVD2. + USB_DOEPINT2_STSPHSERCVD2 = 0x20 + // Position of BACK2BACKSETUP2 field. + USB_DOEPINT2_BACK2BACKSETUP2_Pos = 0x6 + // Bit mask of BACK2BACKSETUP2 field. + USB_DOEPINT2_BACK2BACKSETUP2_Msk = 0x40 + // Bit BACK2BACKSETUP2. + USB_DOEPINT2_BACK2BACKSETUP2 = 0x40 + // Position of OUTPKTERR2 field. + USB_DOEPINT2_OUTPKTERR2_Pos = 0x8 + // Bit mask of OUTPKTERR2 field. + USB_DOEPINT2_OUTPKTERR2_Msk = 0x100 + // Bit OUTPKTERR2. + USB_DOEPINT2_OUTPKTERR2 = 0x100 + // Position of BNAINTR2 field. + USB_DOEPINT2_BNAINTR2_Pos = 0x9 + // Bit mask of BNAINTR2 field. + USB_DOEPINT2_BNAINTR2_Msk = 0x200 + // Bit BNAINTR2. + USB_DOEPINT2_BNAINTR2 = 0x200 + // Position of PKTDRPSTS2 field. + USB_DOEPINT2_PKTDRPSTS2_Pos = 0xb + // Bit mask of PKTDRPSTS2 field. + USB_DOEPINT2_PKTDRPSTS2_Msk = 0x800 + // Bit PKTDRPSTS2. + USB_DOEPINT2_PKTDRPSTS2 = 0x800 + // Position of BBLEERR2 field. + USB_DOEPINT2_BBLEERR2_Pos = 0xc + // Bit mask of BBLEERR2 field. + USB_DOEPINT2_BBLEERR2_Msk = 0x1000 + // Bit BBLEERR2. + USB_DOEPINT2_BBLEERR2 = 0x1000 + // Position of NAKINTRPT2 field. + USB_DOEPINT2_NAKINTRPT2_Pos = 0xd + // Bit mask of NAKINTRPT2 field. + USB_DOEPINT2_NAKINTRPT2_Msk = 0x2000 + // Bit NAKINTRPT2. + USB_DOEPINT2_NAKINTRPT2 = 0x2000 + // Position of NYEPINTRPT2 field. + USB_DOEPINT2_NYEPINTRPT2_Pos = 0xe + // Bit mask of NYEPINTRPT2 field. + USB_DOEPINT2_NYEPINTRPT2_Msk = 0x4000 + // Bit NYEPINTRPT2. + USB_DOEPINT2_NYEPINTRPT2 = 0x4000 + // Position of STUPPKTRCVD2 field. + USB_DOEPINT2_STUPPKTRCVD2_Pos = 0xf + // Bit mask of STUPPKTRCVD2 field. + USB_DOEPINT2_STUPPKTRCVD2_Msk = 0x8000 + // Bit STUPPKTRCVD2. + USB_DOEPINT2_STUPPKTRCVD2 = 0x8000 + + // DOEPTSIZ2 + // Position of XFERSIZE2 field. + USB_DOEPTSIZ2_XFERSIZE2_Pos = 0x0 + // Bit mask of XFERSIZE2 field. + USB_DOEPTSIZ2_XFERSIZE2_Msk = 0x7f + // Position of PKTCNT2 field. + USB_DOEPTSIZ2_PKTCNT2_Pos = 0x13 + // Bit mask of PKTCNT2 field. + USB_DOEPTSIZ2_PKTCNT2_Msk = 0x80000 + // Bit PKTCNT2. + USB_DOEPTSIZ2_PKTCNT2 = 0x80000 + // Position of SUPCNT2 field. + USB_DOEPTSIZ2_SUPCNT2_Pos = 0x1d + // Bit mask of SUPCNT2 field. + USB_DOEPTSIZ2_SUPCNT2_Msk = 0x60000000 + + // DOEPDMA2 + // Position of DMAADDR2 field. + USB_DOEPDMA2_DMAADDR2_Pos = 0x0 + // Bit mask of DMAADDR2 field. + USB_DOEPDMA2_DMAADDR2_Msk = 0xffffffff + + // DOEPDMAB2 + // Position of DMABUFFERADDR2 field. + USB_DOEPDMAB2_DMABUFFERADDR2_Pos = 0x0 + // Bit mask of DMABUFFERADDR2 field. + USB_DOEPDMAB2_DMABUFFERADDR2_Msk = 0xffffffff + + // DOEPCTL3 + // Position of MPS3 field. + USB_DOEPCTL3_MPS3_Pos = 0x0 + // Bit mask of MPS3 field. + USB_DOEPCTL3_MPS3_Msk = 0x7ff + // Position of USBACTEP3 field. + USB_DOEPCTL3_USBACTEP3_Pos = 0xf + // Bit mask of USBACTEP3 field. + USB_DOEPCTL3_USBACTEP3_Msk = 0x8000 + // Bit USBACTEP3. + USB_DOEPCTL3_USBACTEP3 = 0x8000 + // Position of NAKSTS3 field. + USB_DOEPCTL3_NAKSTS3_Pos = 0x11 + // Bit mask of NAKSTS3 field. + USB_DOEPCTL3_NAKSTS3_Msk = 0x20000 + // Bit NAKSTS3. + USB_DOEPCTL3_NAKSTS3 = 0x20000 + // Position of EPTYPE3 field. + USB_DOEPCTL3_EPTYPE3_Pos = 0x12 + // Bit mask of EPTYPE3 field. + USB_DOEPCTL3_EPTYPE3_Msk = 0xc0000 + // Position of SNP3 field. + USB_DOEPCTL3_SNP3_Pos = 0x14 + // Bit mask of SNP3 field. + USB_DOEPCTL3_SNP3_Msk = 0x100000 + // Bit SNP3. + USB_DOEPCTL3_SNP3 = 0x100000 + // Position of STALL3 field. + USB_DOEPCTL3_STALL3_Pos = 0x15 + // Bit mask of STALL3 field. + USB_DOEPCTL3_STALL3_Msk = 0x200000 + // Bit STALL3. + USB_DOEPCTL3_STALL3 = 0x200000 + // Position of CNAK3 field. + USB_DOEPCTL3_CNAK3_Pos = 0x1a + // Bit mask of CNAK3 field. + USB_DOEPCTL3_CNAK3_Msk = 0x4000000 + // Bit CNAK3. + USB_DOEPCTL3_CNAK3 = 0x4000000 + // Position of DO_SNAK3 field. + USB_DOEPCTL3_DO_SNAK3_Pos = 0x1b + // Bit mask of DO_SNAK3 field. + USB_DOEPCTL3_DO_SNAK3_Msk = 0x8000000 + // Bit DO_SNAK3. + USB_DOEPCTL3_DO_SNAK3 = 0x8000000 + // Position of DO_SETD0PID3 field. + USB_DOEPCTL3_DO_SETD0PID3_Pos = 0x1c + // Bit mask of DO_SETD0PID3 field. + USB_DOEPCTL3_DO_SETD0PID3_Msk = 0x10000000 + // Bit DO_SETD0PID3. + USB_DOEPCTL3_DO_SETD0PID3 = 0x10000000 + // Position of DO_SETD1PID3 field. + USB_DOEPCTL3_DO_SETD1PID3_Pos = 0x1d + // Bit mask of DO_SETD1PID3 field. + USB_DOEPCTL3_DO_SETD1PID3_Msk = 0x20000000 + // Bit DO_SETD1PID3. + USB_DOEPCTL3_DO_SETD1PID3 = 0x20000000 + // Position of EPDIS3 field. + USB_DOEPCTL3_EPDIS3_Pos = 0x1e + // Bit mask of EPDIS3 field. + USB_DOEPCTL3_EPDIS3_Msk = 0x40000000 + // Bit EPDIS3. + USB_DOEPCTL3_EPDIS3 = 0x40000000 + // Position of EPENA3 field. + USB_DOEPCTL3_EPENA3_Pos = 0x1f + // Bit mask of EPENA3 field. + USB_DOEPCTL3_EPENA3_Msk = 0x80000000 + // Bit EPENA3. + USB_DOEPCTL3_EPENA3 = 0x80000000 + + // DOEPINT3 + // Position of XFERCOMPL3 field. + USB_DOEPINT3_XFERCOMPL3_Pos = 0x0 + // Bit mask of XFERCOMPL3 field. + USB_DOEPINT3_XFERCOMPL3_Msk = 0x1 + // Bit XFERCOMPL3. + USB_DOEPINT3_XFERCOMPL3 = 0x1 + // Position of EPDISBLD3 field. + USB_DOEPINT3_EPDISBLD3_Pos = 0x1 + // Bit mask of EPDISBLD3 field. + USB_DOEPINT3_EPDISBLD3_Msk = 0x2 + // Bit EPDISBLD3. + USB_DOEPINT3_EPDISBLD3 = 0x2 + // Position of AHBERR3 field. + USB_DOEPINT3_AHBERR3_Pos = 0x2 + // Bit mask of AHBERR3 field. + USB_DOEPINT3_AHBERR3_Msk = 0x4 + // Bit AHBERR3. + USB_DOEPINT3_AHBERR3 = 0x4 + // Position of SETUP3 field. + USB_DOEPINT3_SETUP3_Pos = 0x3 + // Bit mask of SETUP3 field. + USB_DOEPINT3_SETUP3_Msk = 0x8 + // Bit SETUP3. + USB_DOEPINT3_SETUP3 = 0x8 + // Position of OUTTKNEPDIS3 field. + USB_DOEPINT3_OUTTKNEPDIS3_Pos = 0x4 + // Bit mask of OUTTKNEPDIS3 field. + USB_DOEPINT3_OUTTKNEPDIS3_Msk = 0x10 + // Bit OUTTKNEPDIS3. + USB_DOEPINT3_OUTTKNEPDIS3 = 0x10 + // Position of STSPHSERCVD3 field. + USB_DOEPINT3_STSPHSERCVD3_Pos = 0x5 + // Bit mask of STSPHSERCVD3 field. + USB_DOEPINT3_STSPHSERCVD3_Msk = 0x20 + // Bit STSPHSERCVD3. + USB_DOEPINT3_STSPHSERCVD3 = 0x20 + // Position of BACK2BACKSETUP3 field. + USB_DOEPINT3_BACK2BACKSETUP3_Pos = 0x6 + // Bit mask of BACK2BACKSETUP3 field. + USB_DOEPINT3_BACK2BACKSETUP3_Msk = 0x40 + // Bit BACK2BACKSETUP3. + USB_DOEPINT3_BACK2BACKSETUP3 = 0x40 + // Position of OUTPKTERR3 field. + USB_DOEPINT3_OUTPKTERR3_Pos = 0x8 + // Bit mask of OUTPKTERR3 field. + USB_DOEPINT3_OUTPKTERR3_Msk = 0x100 + // Bit OUTPKTERR3. + USB_DOEPINT3_OUTPKTERR3 = 0x100 + // Position of BNAINTR3 field. + USB_DOEPINT3_BNAINTR3_Pos = 0x9 + // Bit mask of BNAINTR3 field. + USB_DOEPINT3_BNAINTR3_Msk = 0x200 + // Bit BNAINTR3. + USB_DOEPINT3_BNAINTR3 = 0x200 + // Position of PKTDRPSTS3 field. + USB_DOEPINT3_PKTDRPSTS3_Pos = 0xb + // Bit mask of PKTDRPSTS3 field. + USB_DOEPINT3_PKTDRPSTS3_Msk = 0x800 + // Bit PKTDRPSTS3. + USB_DOEPINT3_PKTDRPSTS3 = 0x800 + // Position of BBLEERR3 field. + USB_DOEPINT3_BBLEERR3_Pos = 0xc + // Bit mask of BBLEERR3 field. + USB_DOEPINT3_BBLEERR3_Msk = 0x1000 + // Bit BBLEERR3. + USB_DOEPINT3_BBLEERR3 = 0x1000 + // Position of NAKINTRPT3 field. + USB_DOEPINT3_NAKINTRPT3_Pos = 0xd + // Bit mask of NAKINTRPT3 field. + USB_DOEPINT3_NAKINTRPT3_Msk = 0x2000 + // Bit NAKINTRPT3. + USB_DOEPINT3_NAKINTRPT3 = 0x2000 + // Position of NYEPINTRPT3 field. + USB_DOEPINT3_NYEPINTRPT3_Pos = 0xe + // Bit mask of NYEPINTRPT3 field. + USB_DOEPINT3_NYEPINTRPT3_Msk = 0x4000 + // Bit NYEPINTRPT3. + USB_DOEPINT3_NYEPINTRPT3 = 0x4000 + // Position of STUPPKTRCVD3 field. + USB_DOEPINT3_STUPPKTRCVD3_Pos = 0xf + // Bit mask of STUPPKTRCVD3 field. + USB_DOEPINT3_STUPPKTRCVD3_Msk = 0x8000 + // Bit STUPPKTRCVD3. + USB_DOEPINT3_STUPPKTRCVD3 = 0x8000 + + // DOEPTSIZ3 + // Position of XFERSIZE3 field. + USB_DOEPTSIZ3_XFERSIZE3_Pos = 0x0 + // Bit mask of XFERSIZE3 field. + USB_DOEPTSIZ3_XFERSIZE3_Msk = 0x7f + // Position of PKTCNT3 field. + USB_DOEPTSIZ3_PKTCNT3_Pos = 0x13 + // Bit mask of PKTCNT3 field. + USB_DOEPTSIZ3_PKTCNT3_Msk = 0x80000 + // Bit PKTCNT3. + USB_DOEPTSIZ3_PKTCNT3 = 0x80000 + // Position of SUPCNT3 field. + USB_DOEPTSIZ3_SUPCNT3_Pos = 0x1d + // Bit mask of SUPCNT3 field. + USB_DOEPTSIZ3_SUPCNT3_Msk = 0x60000000 + + // DOEPDMA3 + // Position of DMAADDR3 field. + USB_DOEPDMA3_DMAADDR3_Pos = 0x0 + // Bit mask of DMAADDR3 field. + USB_DOEPDMA3_DMAADDR3_Msk = 0xffffffff + + // DOEPDMAB3 + // Position of DMABUFFERADDR3 field. + USB_DOEPDMAB3_DMABUFFERADDR3_Pos = 0x0 + // Bit mask of DMABUFFERADDR3 field. + USB_DOEPDMAB3_DMABUFFERADDR3_Msk = 0xffffffff + + // DOEPCTL4 + // Position of MPS4 field. + USB_DOEPCTL4_MPS4_Pos = 0x0 + // Bit mask of MPS4 field. + USB_DOEPCTL4_MPS4_Msk = 0x7ff + // Position of USBACTEP4 field. + USB_DOEPCTL4_USBACTEP4_Pos = 0xf + // Bit mask of USBACTEP4 field. + USB_DOEPCTL4_USBACTEP4_Msk = 0x8000 + // Bit USBACTEP4. + USB_DOEPCTL4_USBACTEP4 = 0x8000 + // Position of NAKSTS4 field. + USB_DOEPCTL4_NAKSTS4_Pos = 0x11 + // Bit mask of NAKSTS4 field. + USB_DOEPCTL4_NAKSTS4_Msk = 0x20000 + // Bit NAKSTS4. + USB_DOEPCTL4_NAKSTS4 = 0x20000 + // Position of EPTYPE4 field. + USB_DOEPCTL4_EPTYPE4_Pos = 0x12 + // Bit mask of EPTYPE4 field. + USB_DOEPCTL4_EPTYPE4_Msk = 0xc0000 + // Position of SNP4 field. + USB_DOEPCTL4_SNP4_Pos = 0x14 + // Bit mask of SNP4 field. + USB_DOEPCTL4_SNP4_Msk = 0x100000 + // Bit SNP4. + USB_DOEPCTL4_SNP4 = 0x100000 + // Position of STALL4 field. + USB_DOEPCTL4_STALL4_Pos = 0x15 + // Bit mask of STALL4 field. + USB_DOEPCTL4_STALL4_Msk = 0x200000 + // Bit STALL4. + USB_DOEPCTL4_STALL4 = 0x200000 + // Position of CNAK4 field. + USB_DOEPCTL4_CNAK4_Pos = 0x1a + // Bit mask of CNAK4 field. + USB_DOEPCTL4_CNAK4_Msk = 0x4000000 + // Bit CNAK4. + USB_DOEPCTL4_CNAK4 = 0x4000000 + // Position of DO_SNAK4 field. + USB_DOEPCTL4_DO_SNAK4_Pos = 0x1b + // Bit mask of DO_SNAK4 field. + USB_DOEPCTL4_DO_SNAK4_Msk = 0x8000000 + // Bit DO_SNAK4. + USB_DOEPCTL4_DO_SNAK4 = 0x8000000 + // Position of DO_SETD0PID4 field. + USB_DOEPCTL4_DO_SETD0PID4_Pos = 0x1c + // Bit mask of DO_SETD0PID4 field. + USB_DOEPCTL4_DO_SETD0PID4_Msk = 0x10000000 + // Bit DO_SETD0PID4. + USB_DOEPCTL4_DO_SETD0PID4 = 0x10000000 + // Position of DO_SETD1PID4 field. + USB_DOEPCTL4_DO_SETD1PID4_Pos = 0x1d + // Bit mask of DO_SETD1PID4 field. + USB_DOEPCTL4_DO_SETD1PID4_Msk = 0x20000000 + // Bit DO_SETD1PID4. + USB_DOEPCTL4_DO_SETD1PID4 = 0x20000000 + // Position of EPDIS4 field. + USB_DOEPCTL4_EPDIS4_Pos = 0x1e + // Bit mask of EPDIS4 field. + USB_DOEPCTL4_EPDIS4_Msk = 0x40000000 + // Bit EPDIS4. + USB_DOEPCTL4_EPDIS4 = 0x40000000 + // Position of EPENA4 field. + USB_DOEPCTL4_EPENA4_Pos = 0x1f + // Bit mask of EPENA4 field. + USB_DOEPCTL4_EPENA4_Msk = 0x80000000 + // Bit EPENA4. + USB_DOEPCTL4_EPENA4 = 0x80000000 + + // DOEPINT4 + // Position of XFERCOMPL4 field. + USB_DOEPINT4_XFERCOMPL4_Pos = 0x0 + // Bit mask of XFERCOMPL4 field. + USB_DOEPINT4_XFERCOMPL4_Msk = 0x1 + // Bit XFERCOMPL4. + USB_DOEPINT4_XFERCOMPL4 = 0x1 + // Position of EPDISBLD4 field. + USB_DOEPINT4_EPDISBLD4_Pos = 0x1 + // Bit mask of EPDISBLD4 field. + USB_DOEPINT4_EPDISBLD4_Msk = 0x2 + // Bit EPDISBLD4. + USB_DOEPINT4_EPDISBLD4 = 0x2 + // Position of AHBERR4 field. + USB_DOEPINT4_AHBERR4_Pos = 0x2 + // Bit mask of AHBERR4 field. + USB_DOEPINT4_AHBERR4_Msk = 0x4 + // Bit AHBERR4. + USB_DOEPINT4_AHBERR4 = 0x4 + // Position of SETUP4 field. + USB_DOEPINT4_SETUP4_Pos = 0x3 + // Bit mask of SETUP4 field. + USB_DOEPINT4_SETUP4_Msk = 0x8 + // Bit SETUP4. + USB_DOEPINT4_SETUP4 = 0x8 + // Position of OUTTKNEPDIS4 field. + USB_DOEPINT4_OUTTKNEPDIS4_Pos = 0x4 + // Bit mask of OUTTKNEPDIS4 field. + USB_DOEPINT4_OUTTKNEPDIS4_Msk = 0x10 + // Bit OUTTKNEPDIS4. + USB_DOEPINT4_OUTTKNEPDIS4 = 0x10 + // Position of STSPHSERCVD4 field. + USB_DOEPINT4_STSPHSERCVD4_Pos = 0x5 + // Bit mask of STSPHSERCVD4 field. + USB_DOEPINT4_STSPHSERCVD4_Msk = 0x20 + // Bit STSPHSERCVD4. + USB_DOEPINT4_STSPHSERCVD4 = 0x20 + // Position of BACK2BACKSETUP4 field. + USB_DOEPINT4_BACK2BACKSETUP4_Pos = 0x6 + // Bit mask of BACK2BACKSETUP4 field. + USB_DOEPINT4_BACK2BACKSETUP4_Msk = 0x40 + // Bit BACK2BACKSETUP4. + USB_DOEPINT4_BACK2BACKSETUP4 = 0x40 + // Position of OUTPKTERR4 field. + USB_DOEPINT4_OUTPKTERR4_Pos = 0x8 + // Bit mask of OUTPKTERR4 field. + USB_DOEPINT4_OUTPKTERR4_Msk = 0x100 + // Bit OUTPKTERR4. + USB_DOEPINT4_OUTPKTERR4 = 0x100 + // Position of BNAINTR4 field. + USB_DOEPINT4_BNAINTR4_Pos = 0x9 + // Bit mask of BNAINTR4 field. + USB_DOEPINT4_BNAINTR4_Msk = 0x200 + // Bit BNAINTR4. + USB_DOEPINT4_BNAINTR4 = 0x200 + // Position of PKTDRPSTS4 field. + USB_DOEPINT4_PKTDRPSTS4_Pos = 0xb + // Bit mask of PKTDRPSTS4 field. + USB_DOEPINT4_PKTDRPSTS4_Msk = 0x800 + // Bit PKTDRPSTS4. + USB_DOEPINT4_PKTDRPSTS4 = 0x800 + // Position of BBLEERR4 field. + USB_DOEPINT4_BBLEERR4_Pos = 0xc + // Bit mask of BBLEERR4 field. + USB_DOEPINT4_BBLEERR4_Msk = 0x1000 + // Bit BBLEERR4. + USB_DOEPINT4_BBLEERR4 = 0x1000 + // Position of NAKINTRPT4 field. + USB_DOEPINT4_NAKINTRPT4_Pos = 0xd + // Bit mask of NAKINTRPT4 field. + USB_DOEPINT4_NAKINTRPT4_Msk = 0x2000 + // Bit NAKINTRPT4. + USB_DOEPINT4_NAKINTRPT4 = 0x2000 + // Position of NYEPINTRPT4 field. + USB_DOEPINT4_NYEPINTRPT4_Pos = 0xe + // Bit mask of NYEPINTRPT4 field. + USB_DOEPINT4_NYEPINTRPT4_Msk = 0x4000 + // Bit NYEPINTRPT4. + USB_DOEPINT4_NYEPINTRPT4 = 0x4000 + // Position of STUPPKTRCVD4 field. + USB_DOEPINT4_STUPPKTRCVD4_Pos = 0xf + // Bit mask of STUPPKTRCVD4 field. + USB_DOEPINT4_STUPPKTRCVD4_Msk = 0x8000 + // Bit STUPPKTRCVD4. + USB_DOEPINT4_STUPPKTRCVD4 = 0x8000 + + // DOEPTSIZ4 + // Position of XFERSIZE4 field. + USB_DOEPTSIZ4_XFERSIZE4_Pos = 0x0 + // Bit mask of XFERSIZE4 field. + USB_DOEPTSIZ4_XFERSIZE4_Msk = 0x7f + // Position of PKTCNT4 field. + USB_DOEPTSIZ4_PKTCNT4_Pos = 0x13 + // Bit mask of PKTCNT4 field. + USB_DOEPTSIZ4_PKTCNT4_Msk = 0x80000 + // Bit PKTCNT4. + USB_DOEPTSIZ4_PKTCNT4 = 0x80000 + // Position of SUPCNT4 field. + USB_DOEPTSIZ4_SUPCNT4_Pos = 0x1d + // Bit mask of SUPCNT4 field. + USB_DOEPTSIZ4_SUPCNT4_Msk = 0x60000000 + + // DOEPDMA4 + // Position of DMAADDR4 field. + USB_DOEPDMA4_DMAADDR4_Pos = 0x0 + // Bit mask of DMAADDR4 field. + USB_DOEPDMA4_DMAADDR4_Msk = 0xffffffff + + // DOEPDMAB4 + // Position of DMABUFFERADDR4 field. + USB_DOEPDMAB4_DMABUFFERADDR4_Pos = 0x0 + // Bit mask of DMABUFFERADDR4 field. + USB_DOEPDMAB4_DMABUFFERADDR4_Msk = 0xffffffff + + // DOEPCTL5 + // Position of MPS5 field. + USB_DOEPCTL5_MPS5_Pos = 0x0 + // Bit mask of MPS5 field. + USB_DOEPCTL5_MPS5_Msk = 0x7ff + // Position of USBACTEP5 field. + USB_DOEPCTL5_USBACTEP5_Pos = 0xf + // Bit mask of USBACTEP5 field. + USB_DOEPCTL5_USBACTEP5_Msk = 0x8000 + // Bit USBACTEP5. + USB_DOEPCTL5_USBACTEP5 = 0x8000 + // Position of NAKSTS5 field. + USB_DOEPCTL5_NAKSTS5_Pos = 0x11 + // Bit mask of NAKSTS5 field. + USB_DOEPCTL5_NAKSTS5_Msk = 0x20000 + // Bit NAKSTS5. + USB_DOEPCTL5_NAKSTS5 = 0x20000 + // Position of EPTYPE5 field. + USB_DOEPCTL5_EPTYPE5_Pos = 0x12 + // Bit mask of EPTYPE5 field. + USB_DOEPCTL5_EPTYPE5_Msk = 0xc0000 + // Position of SNP5 field. + USB_DOEPCTL5_SNP5_Pos = 0x14 + // Bit mask of SNP5 field. + USB_DOEPCTL5_SNP5_Msk = 0x100000 + // Bit SNP5. + USB_DOEPCTL5_SNP5 = 0x100000 + // Position of STALL5 field. + USB_DOEPCTL5_STALL5_Pos = 0x15 + // Bit mask of STALL5 field. + USB_DOEPCTL5_STALL5_Msk = 0x200000 + // Bit STALL5. + USB_DOEPCTL5_STALL5 = 0x200000 + // Position of CNAK5 field. + USB_DOEPCTL5_CNAK5_Pos = 0x1a + // Bit mask of CNAK5 field. + USB_DOEPCTL5_CNAK5_Msk = 0x4000000 + // Bit CNAK5. + USB_DOEPCTL5_CNAK5 = 0x4000000 + // Position of DO_SNAK5 field. + USB_DOEPCTL5_DO_SNAK5_Pos = 0x1b + // Bit mask of DO_SNAK5 field. + USB_DOEPCTL5_DO_SNAK5_Msk = 0x8000000 + // Bit DO_SNAK5. + USB_DOEPCTL5_DO_SNAK5 = 0x8000000 + // Position of DO_SETD0PID5 field. + USB_DOEPCTL5_DO_SETD0PID5_Pos = 0x1c + // Bit mask of DO_SETD0PID5 field. + USB_DOEPCTL5_DO_SETD0PID5_Msk = 0x10000000 + // Bit DO_SETD0PID5. + USB_DOEPCTL5_DO_SETD0PID5 = 0x10000000 + // Position of DO_SETD1PID5 field. + USB_DOEPCTL5_DO_SETD1PID5_Pos = 0x1d + // Bit mask of DO_SETD1PID5 field. + USB_DOEPCTL5_DO_SETD1PID5_Msk = 0x20000000 + // Bit DO_SETD1PID5. + USB_DOEPCTL5_DO_SETD1PID5 = 0x20000000 + // Position of EPDIS5 field. + USB_DOEPCTL5_EPDIS5_Pos = 0x1e + // Bit mask of EPDIS5 field. + USB_DOEPCTL5_EPDIS5_Msk = 0x40000000 + // Bit EPDIS5. + USB_DOEPCTL5_EPDIS5 = 0x40000000 + // Position of EPENA5 field. + USB_DOEPCTL5_EPENA5_Pos = 0x1f + // Bit mask of EPENA5 field. + USB_DOEPCTL5_EPENA5_Msk = 0x80000000 + // Bit EPENA5. + USB_DOEPCTL5_EPENA5 = 0x80000000 + + // DOEPINT5 + // Position of XFERCOMPL5 field. + USB_DOEPINT5_XFERCOMPL5_Pos = 0x0 + // Bit mask of XFERCOMPL5 field. + USB_DOEPINT5_XFERCOMPL5_Msk = 0x1 + // Bit XFERCOMPL5. + USB_DOEPINT5_XFERCOMPL5 = 0x1 + // Position of EPDISBLD5 field. + USB_DOEPINT5_EPDISBLD5_Pos = 0x1 + // Bit mask of EPDISBLD5 field. + USB_DOEPINT5_EPDISBLD5_Msk = 0x2 + // Bit EPDISBLD5. + USB_DOEPINT5_EPDISBLD5 = 0x2 + // Position of AHBERR5 field. + USB_DOEPINT5_AHBERR5_Pos = 0x2 + // Bit mask of AHBERR5 field. + USB_DOEPINT5_AHBERR5_Msk = 0x4 + // Bit AHBERR5. + USB_DOEPINT5_AHBERR5 = 0x4 + // Position of SETUP5 field. + USB_DOEPINT5_SETUP5_Pos = 0x3 + // Bit mask of SETUP5 field. + USB_DOEPINT5_SETUP5_Msk = 0x8 + // Bit SETUP5. + USB_DOEPINT5_SETUP5 = 0x8 + // Position of OUTTKNEPDIS5 field. + USB_DOEPINT5_OUTTKNEPDIS5_Pos = 0x4 + // Bit mask of OUTTKNEPDIS5 field. + USB_DOEPINT5_OUTTKNEPDIS5_Msk = 0x10 + // Bit OUTTKNEPDIS5. + USB_DOEPINT5_OUTTKNEPDIS5 = 0x10 + // Position of STSPHSERCVD5 field. + USB_DOEPINT5_STSPHSERCVD5_Pos = 0x5 + // Bit mask of STSPHSERCVD5 field. + USB_DOEPINT5_STSPHSERCVD5_Msk = 0x20 + // Bit STSPHSERCVD5. + USB_DOEPINT5_STSPHSERCVD5 = 0x20 + // Position of BACK2BACKSETUP5 field. + USB_DOEPINT5_BACK2BACKSETUP5_Pos = 0x6 + // Bit mask of BACK2BACKSETUP5 field. + USB_DOEPINT5_BACK2BACKSETUP5_Msk = 0x40 + // Bit BACK2BACKSETUP5. + USB_DOEPINT5_BACK2BACKSETUP5 = 0x40 + // Position of OUTPKTERR5 field. + USB_DOEPINT5_OUTPKTERR5_Pos = 0x8 + // Bit mask of OUTPKTERR5 field. + USB_DOEPINT5_OUTPKTERR5_Msk = 0x100 + // Bit OUTPKTERR5. + USB_DOEPINT5_OUTPKTERR5 = 0x100 + // Position of BNAINTR5 field. + USB_DOEPINT5_BNAINTR5_Pos = 0x9 + // Bit mask of BNAINTR5 field. + USB_DOEPINT5_BNAINTR5_Msk = 0x200 + // Bit BNAINTR5. + USB_DOEPINT5_BNAINTR5 = 0x200 + // Position of PKTDRPSTS5 field. + USB_DOEPINT5_PKTDRPSTS5_Pos = 0xb + // Bit mask of PKTDRPSTS5 field. + USB_DOEPINT5_PKTDRPSTS5_Msk = 0x800 + // Bit PKTDRPSTS5. + USB_DOEPINT5_PKTDRPSTS5 = 0x800 + // Position of BBLEERR5 field. + USB_DOEPINT5_BBLEERR5_Pos = 0xc + // Bit mask of BBLEERR5 field. + USB_DOEPINT5_BBLEERR5_Msk = 0x1000 + // Bit BBLEERR5. + USB_DOEPINT5_BBLEERR5 = 0x1000 + // Position of NAKINTRPT5 field. + USB_DOEPINT5_NAKINTRPT5_Pos = 0xd + // Bit mask of NAKINTRPT5 field. + USB_DOEPINT5_NAKINTRPT5_Msk = 0x2000 + // Bit NAKINTRPT5. + USB_DOEPINT5_NAKINTRPT5 = 0x2000 + // Position of NYEPINTRPT5 field. + USB_DOEPINT5_NYEPINTRPT5_Pos = 0xe + // Bit mask of NYEPINTRPT5 field. + USB_DOEPINT5_NYEPINTRPT5_Msk = 0x4000 + // Bit NYEPINTRPT5. + USB_DOEPINT5_NYEPINTRPT5 = 0x4000 + // Position of STUPPKTRCVD5 field. + USB_DOEPINT5_STUPPKTRCVD5_Pos = 0xf + // Bit mask of STUPPKTRCVD5 field. + USB_DOEPINT5_STUPPKTRCVD5_Msk = 0x8000 + // Bit STUPPKTRCVD5. + USB_DOEPINT5_STUPPKTRCVD5 = 0x8000 + + // DOEPTSIZ5 + // Position of XFERSIZE5 field. + USB_DOEPTSIZ5_XFERSIZE5_Pos = 0x0 + // Bit mask of XFERSIZE5 field. + USB_DOEPTSIZ5_XFERSIZE5_Msk = 0x7f + // Position of PKTCNT5 field. + USB_DOEPTSIZ5_PKTCNT5_Pos = 0x13 + // Bit mask of PKTCNT5 field. + USB_DOEPTSIZ5_PKTCNT5_Msk = 0x80000 + // Bit PKTCNT5. + USB_DOEPTSIZ5_PKTCNT5 = 0x80000 + // Position of SUPCNT5 field. + USB_DOEPTSIZ5_SUPCNT5_Pos = 0x1d + // Bit mask of SUPCNT5 field. + USB_DOEPTSIZ5_SUPCNT5_Msk = 0x60000000 + + // DOEPDMA5 + // Position of DMAADDR5 field. + USB_DOEPDMA5_DMAADDR5_Pos = 0x0 + // Bit mask of DMAADDR5 field. + USB_DOEPDMA5_DMAADDR5_Msk = 0xffffffff + + // DOEPDMAB5 + // Position of DMABUFFERADDR5 field. + USB_DOEPDMAB5_DMABUFFERADDR5_Pos = 0x0 + // Bit mask of DMABUFFERADDR5 field. + USB_DOEPDMAB5_DMABUFFERADDR5_Msk = 0xffffffff + + // DOEPCTL6 + // Position of MPS6 field. + USB_DOEPCTL6_MPS6_Pos = 0x0 + // Bit mask of MPS6 field. + USB_DOEPCTL6_MPS6_Msk = 0x7ff + // Position of USBACTEP6 field. + USB_DOEPCTL6_USBACTEP6_Pos = 0xf + // Bit mask of USBACTEP6 field. + USB_DOEPCTL6_USBACTEP6_Msk = 0x8000 + // Bit USBACTEP6. + USB_DOEPCTL6_USBACTEP6 = 0x8000 + // Position of NAKSTS6 field. + USB_DOEPCTL6_NAKSTS6_Pos = 0x11 + // Bit mask of NAKSTS6 field. + USB_DOEPCTL6_NAKSTS6_Msk = 0x20000 + // Bit NAKSTS6. + USB_DOEPCTL6_NAKSTS6 = 0x20000 + // Position of EPTYPE6 field. + USB_DOEPCTL6_EPTYPE6_Pos = 0x12 + // Bit mask of EPTYPE6 field. + USB_DOEPCTL6_EPTYPE6_Msk = 0xc0000 + // Position of SNP6 field. + USB_DOEPCTL6_SNP6_Pos = 0x14 + // Bit mask of SNP6 field. + USB_DOEPCTL6_SNP6_Msk = 0x100000 + // Bit SNP6. + USB_DOEPCTL6_SNP6 = 0x100000 + // Position of STALL6 field. + USB_DOEPCTL6_STALL6_Pos = 0x15 + // Bit mask of STALL6 field. + USB_DOEPCTL6_STALL6_Msk = 0x200000 + // Bit STALL6. + USB_DOEPCTL6_STALL6 = 0x200000 + // Position of CNAK6 field. + USB_DOEPCTL6_CNAK6_Pos = 0x1a + // Bit mask of CNAK6 field. + USB_DOEPCTL6_CNAK6_Msk = 0x4000000 + // Bit CNAK6. + USB_DOEPCTL6_CNAK6 = 0x4000000 + // Position of DO_SNAK6 field. + USB_DOEPCTL6_DO_SNAK6_Pos = 0x1b + // Bit mask of DO_SNAK6 field. + USB_DOEPCTL6_DO_SNAK6_Msk = 0x8000000 + // Bit DO_SNAK6. + USB_DOEPCTL6_DO_SNAK6 = 0x8000000 + // Position of DO_SETD0PID6 field. + USB_DOEPCTL6_DO_SETD0PID6_Pos = 0x1c + // Bit mask of DO_SETD0PID6 field. + USB_DOEPCTL6_DO_SETD0PID6_Msk = 0x10000000 + // Bit DO_SETD0PID6. + USB_DOEPCTL6_DO_SETD0PID6 = 0x10000000 + // Position of DO_SETD1PID6 field. + USB_DOEPCTL6_DO_SETD1PID6_Pos = 0x1d + // Bit mask of DO_SETD1PID6 field. + USB_DOEPCTL6_DO_SETD1PID6_Msk = 0x20000000 + // Bit DO_SETD1PID6. + USB_DOEPCTL6_DO_SETD1PID6 = 0x20000000 + // Position of EPDIS6 field. + USB_DOEPCTL6_EPDIS6_Pos = 0x1e + // Bit mask of EPDIS6 field. + USB_DOEPCTL6_EPDIS6_Msk = 0x40000000 + // Bit EPDIS6. + USB_DOEPCTL6_EPDIS6 = 0x40000000 + // Position of EPENA6 field. + USB_DOEPCTL6_EPENA6_Pos = 0x1f + // Bit mask of EPENA6 field. + USB_DOEPCTL6_EPENA6_Msk = 0x80000000 + // Bit EPENA6. + USB_DOEPCTL6_EPENA6 = 0x80000000 + + // DOEPINT6 + // Position of XFERCOMPL6 field. + USB_DOEPINT6_XFERCOMPL6_Pos = 0x0 + // Bit mask of XFERCOMPL6 field. + USB_DOEPINT6_XFERCOMPL6_Msk = 0x1 + // Bit XFERCOMPL6. + USB_DOEPINT6_XFERCOMPL6 = 0x1 + // Position of EPDISBLD6 field. + USB_DOEPINT6_EPDISBLD6_Pos = 0x1 + // Bit mask of EPDISBLD6 field. + USB_DOEPINT6_EPDISBLD6_Msk = 0x2 + // Bit EPDISBLD6. + USB_DOEPINT6_EPDISBLD6 = 0x2 + // Position of AHBERR6 field. + USB_DOEPINT6_AHBERR6_Pos = 0x2 + // Bit mask of AHBERR6 field. + USB_DOEPINT6_AHBERR6_Msk = 0x4 + // Bit AHBERR6. + USB_DOEPINT6_AHBERR6 = 0x4 + // Position of SETUP6 field. + USB_DOEPINT6_SETUP6_Pos = 0x3 + // Bit mask of SETUP6 field. + USB_DOEPINT6_SETUP6_Msk = 0x8 + // Bit SETUP6. + USB_DOEPINT6_SETUP6 = 0x8 + // Position of OUTTKNEPDIS6 field. + USB_DOEPINT6_OUTTKNEPDIS6_Pos = 0x4 + // Bit mask of OUTTKNEPDIS6 field. + USB_DOEPINT6_OUTTKNEPDIS6_Msk = 0x10 + // Bit OUTTKNEPDIS6. + USB_DOEPINT6_OUTTKNEPDIS6 = 0x10 + // Position of STSPHSERCVD6 field. + USB_DOEPINT6_STSPHSERCVD6_Pos = 0x5 + // Bit mask of STSPHSERCVD6 field. + USB_DOEPINT6_STSPHSERCVD6_Msk = 0x20 + // Bit STSPHSERCVD6. + USB_DOEPINT6_STSPHSERCVD6 = 0x20 + // Position of BACK2BACKSETUP6 field. + USB_DOEPINT6_BACK2BACKSETUP6_Pos = 0x6 + // Bit mask of BACK2BACKSETUP6 field. + USB_DOEPINT6_BACK2BACKSETUP6_Msk = 0x40 + // Bit BACK2BACKSETUP6. + USB_DOEPINT6_BACK2BACKSETUP6 = 0x40 + // Position of OUTPKTERR6 field. + USB_DOEPINT6_OUTPKTERR6_Pos = 0x8 + // Bit mask of OUTPKTERR6 field. + USB_DOEPINT6_OUTPKTERR6_Msk = 0x100 + // Bit OUTPKTERR6. + USB_DOEPINT6_OUTPKTERR6 = 0x100 + // Position of BNAINTR6 field. + USB_DOEPINT6_BNAINTR6_Pos = 0x9 + // Bit mask of BNAINTR6 field. + USB_DOEPINT6_BNAINTR6_Msk = 0x200 + // Bit BNAINTR6. + USB_DOEPINT6_BNAINTR6 = 0x200 + // Position of PKTDRPSTS6 field. + USB_DOEPINT6_PKTDRPSTS6_Pos = 0xb + // Bit mask of PKTDRPSTS6 field. + USB_DOEPINT6_PKTDRPSTS6_Msk = 0x800 + // Bit PKTDRPSTS6. + USB_DOEPINT6_PKTDRPSTS6 = 0x800 + // Position of BBLEERR6 field. + USB_DOEPINT6_BBLEERR6_Pos = 0xc + // Bit mask of BBLEERR6 field. + USB_DOEPINT6_BBLEERR6_Msk = 0x1000 + // Bit BBLEERR6. + USB_DOEPINT6_BBLEERR6 = 0x1000 + // Position of NAKINTRPT6 field. + USB_DOEPINT6_NAKINTRPT6_Pos = 0xd + // Bit mask of NAKINTRPT6 field. + USB_DOEPINT6_NAKINTRPT6_Msk = 0x2000 + // Bit NAKINTRPT6. + USB_DOEPINT6_NAKINTRPT6 = 0x2000 + // Position of NYEPINTRPT6 field. + USB_DOEPINT6_NYEPINTRPT6_Pos = 0xe + // Bit mask of NYEPINTRPT6 field. + USB_DOEPINT6_NYEPINTRPT6_Msk = 0x4000 + // Bit NYEPINTRPT6. + USB_DOEPINT6_NYEPINTRPT6 = 0x4000 + // Position of STUPPKTRCVD6 field. + USB_DOEPINT6_STUPPKTRCVD6_Pos = 0xf + // Bit mask of STUPPKTRCVD6 field. + USB_DOEPINT6_STUPPKTRCVD6_Msk = 0x8000 + // Bit STUPPKTRCVD6. + USB_DOEPINT6_STUPPKTRCVD6 = 0x8000 + + // DOEPTSIZ6 + // Position of XFERSIZE6 field. + USB_DOEPTSIZ6_XFERSIZE6_Pos = 0x0 + // Bit mask of XFERSIZE6 field. + USB_DOEPTSIZ6_XFERSIZE6_Msk = 0x7f + // Position of PKTCNT6 field. + USB_DOEPTSIZ6_PKTCNT6_Pos = 0x13 + // Bit mask of PKTCNT6 field. + USB_DOEPTSIZ6_PKTCNT6_Msk = 0x80000 + // Bit PKTCNT6. + USB_DOEPTSIZ6_PKTCNT6 = 0x80000 + // Position of SUPCNT6 field. + USB_DOEPTSIZ6_SUPCNT6_Pos = 0x1d + // Bit mask of SUPCNT6 field. + USB_DOEPTSIZ6_SUPCNT6_Msk = 0x60000000 + + // DOEPDMA6 + // Position of DMAADDR6 field. + USB_DOEPDMA6_DMAADDR6_Pos = 0x0 + // Bit mask of DMAADDR6 field. + USB_DOEPDMA6_DMAADDR6_Msk = 0xffffffff + + // DOEPDMAB6 + // Position of DMABUFFERADDR6 field. + USB_DOEPDMAB6_DMABUFFERADDR6_Pos = 0x0 + // Bit mask of DMABUFFERADDR6 field. + USB_DOEPDMAB6_DMABUFFERADDR6_Msk = 0xffffffff + + // PCGCCTL + // Position of STOPPCLK field. + USB_PCGCCTL_STOPPCLK_Pos = 0x0 + // Bit mask of STOPPCLK field. + USB_PCGCCTL_STOPPCLK_Msk = 0x1 + // Bit STOPPCLK. + USB_PCGCCTL_STOPPCLK = 0x1 + // Position of GATEHCLK field. + USB_PCGCCTL_GATEHCLK_Pos = 0x1 + // Bit mask of GATEHCLK field. + USB_PCGCCTL_GATEHCLK_Msk = 0x2 + // Bit GATEHCLK. + USB_PCGCCTL_GATEHCLK = 0x2 + // Position of PWRCLMP field. + USB_PCGCCTL_PWRCLMP_Pos = 0x2 + // Bit mask of PWRCLMP field. + USB_PCGCCTL_PWRCLMP_Msk = 0x4 + // Bit PWRCLMP. + USB_PCGCCTL_PWRCLMP = 0x4 + // Position of RSTPDWNMODULE field. + USB_PCGCCTL_RSTPDWNMODULE_Pos = 0x3 + // Bit mask of RSTPDWNMODULE field. + USB_PCGCCTL_RSTPDWNMODULE_Msk = 0x8 + // Bit RSTPDWNMODULE. + USB_PCGCCTL_RSTPDWNMODULE = 0x8 + // Position of PHYSLEEP field. + USB_PCGCCTL_PHYSLEEP_Pos = 0x6 + // Bit mask of PHYSLEEP field. + USB_PCGCCTL_PHYSLEEP_Msk = 0x40 + // Bit PHYSLEEP. + USB_PCGCCTL_PHYSLEEP = 0x40 + // Position of L1SUSPENDED field. + USB_PCGCCTL_L1SUSPENDED_Pos = 0x7 + // Bit mask of L1SUSPENDED field. + USB_PCGCCTL_L1SUSPENDED_Msk = 0x80 + // Bit L1SUSPENDED. + USB_PCGCCTL_L1SUSPENDED = 0x80 + // Position of RESETAFTERSUSP field. + USB_PCGCCTL_RESETAFTERSUSP_Pos = 0x8 + // Bit mask of RESETAFTERSUSP field. + USB_PCGCCTL_RESETAFTERSUSP_Msk = 0x100 + // Bit RESETAFTERSUSP. + USB_PCGCCTL_RESETAFTERSUSP = 0x100 +) + +// Constants for USB_WRAP: USB_WRAP Peripheral +const ( + // OTG_CONF: USB OTG Wrapper Configure Register + // Position of SRP_SESSEND_OVERRIDE field. + USB_WRAP_OTG_CONF_SRP_SESSEND_OVERRIDE_Pos = 0x0 + // Bit mask of SRP_SESSEND_OVERRIDE field. + USB_WRAP_OTG_CONF_SRP_SESSEND_OVERRIDE_Msk = 0x1 + // Bit SRP_SESSEND_OVERRIDE. + USB_WRAP_OTG_CONF_SRP_SESSEND_OVERRIDE = 0x1 + // Position of SRP_SESSEND_VALUE field. + USB_WRAP_OTG_CONF_SRP_SESSEND_VALUE_Pos = 0x1 + // Bit mask of SRP_SESSEND_VALUE field. + USB_WRAP_OTG_CONF_SRP_SESSEND_VALUE_Msk = 0x2 + // Bit SRP_SESSEND_VALUE. + USB_WRAP_OTG_CONF_SRP_SESSEND_VALUE = 0x2 + // Position of PHY_SEL field. + USB_WRAP_OTG_CONF_PHY_SEL_Pos = 0x2 + // Bit mask of PHY_SEL field. + USB_WRAP_OTG_CONF_PHY_SEL_Msk = 0x4 + // Bit PHY_SEL. + USB_WRAP_OTG_CONF_PHY_SEL = 0x4 + // Position of DFIFO_FORCE_PD field. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PD_Pos = 0x3 + // Bit mask of DFIFO_FORCE_PD field. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PD_Msk = 0x8 + // Bit DFIFO_FORCE_PD. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PD = 0x8 + // Position of DBNCE_FLTR_BYPASS field. + USB_WRAP_OTG_CONF_DBNCE_FLTR_BYPASS_Pos = 0x4 + // Bit mask of DBNCE_FLTR_BYPASS field. + USB_WRAP_OTG_CONF_DBNCE_FLTR_BYPASS_Msk = 0x10 + // Bit DBNCE_FLTR_BYPASS. + USB_WRAP_OTG_CONF_DBNCE_FLTR_BYPASS = 0x10 + // Position of EXCHG_PINS_OVERRIDE field. + USB_WRAP_OTG_CONF_EXCHG_PINS_OVERRIDE_Pos = 0x5 + // Bit mask of EXCHG_PINS_OVERRIDE field. + USB_WRAP_OTG_CONF_EXCHG_PINS_OVERRIDE_Msk = 0x20 + // Bit EXCHG_PINS_OVERRIDE. + USB_WRAP_OTG_CONF_EXCHG_PINS_OVERRIDE = 0x20 + // Position of EXCHG_PINS field. + USB_WRAP_OTG_CONF_EXCHG_PINS_Pos = 0x6 + // Bit mask of EXCHG_PINS field. + USB_WRAP_OTG_CONF_EXCHG_PINS_Msk = 0x40 + // Bit EXCHG_PINS. + USB_WRAP_OTG_CONF_EXCHG_PINS = 0x40 + // Position of VREFH field. + USB_WRAP_OTG_CONF_VREFH_Pos = 0x7 + // Bit mask of VREFH field. + USB_WRAP_OTG_CONF_VREFH_Msk = 0x180 + // Position of VREFL field. + USB_WRAP_OTG_CONF_VREFL_Pos = 0x9 + // Bit mask of VREFL field. + USB_WRAP_OTG_CONF_VREFL_Msk = 0x600 + // Position of VREF_OVERRIDE field. + USB_WRAP_OTG_CONF_VREF_OVERRIDE_Pos = 0xb + // Bit mask of VREF_OVERRIDE field. + USB_WRAP_OTG_CONF_VREF_OVERRIDE_Msk = 0x800 + // Bit VREF_OVERRIDE. + USB_WRAP_OTG_CONF_VREF_OVERRIDE = 0x800 + // Position of PAD_PULL_OVERRIDE field. + USB_WRAP_OTG_CONF_PAD_PULL_OVERRIDE_Pos = 0xc + // Bit mask of PAD_PULL_OVERRIDE field. + USB_WRAP_OTG_CONF_PAD_PULL_OVERRIDE_Msk = 0x1000 + // Bit PAD_PULL_OVERRIDE. + USB_WRAP_OTG_CONF_PAD_PULL_OVERRIDE = 0x1000 + // Position of DP_PULLUP field. + USB_WRAP_OTG_CONF_DP_PULLUP_Pos = 0xd + // Bit mask of DP_PULLUP field. + USB_WRAP_OTG_CONF_DP_PULLUP_Msk = 0x2000 + // Bit DP_PULLUP. + USB_WRAP_OTG_CONF_DP_PULLUP = 0x2000 + // Position of DP_PULLDOWN field. + USB_WRAP_OTG_CONF_DP_PULLDOWN_Pos = 0xe + // Bit mask of DP_PULLDOWN field. + USB_WRAP_OTG_CONF_DP_PULLDOWN_Msk = 0x4000 + // Bit DP_PULLDOWN. + USB_WRAP_OTG_CONF_DP_PULLDOWN = 0x4000 + // Position of DM_PULLUP field. + USB_WRAP_OTG_CONF_DM_PULLUP_Pos = 0xf + // Bit mask of DM_PULLUP field. + USB_WRAP_OTG_CONF_DM_PULLUP_Msk = 0x8000 + // Bit DM_PULLUP. + USB_WRAP_OTG_CONF_DM_PULLUP = 0x8000 + // Position of DM_PULLDOWN field. + USB_WRAP_OTG_CONF_DM_PULLDOWN_Pos = 0x10 + // Bit mask of DM_PULLDOWN field. + USB_WRAP_OTG_CONF_DM_PULLDOWN_Msk = 0x10000 + // Bit DM_PULLDOWN. + USB_WRAP_OTG_CONF_DM_PULLDOWN = 0x10000 + // Position of PULLUP_VALUE field. + USB_WRAP_OTG_CONF_PULLUP_VALUE_Pos = 0x11 + // Bit mask of PULLUP_VALUE field. + USB_WRAP_OTG_CONF_PULLUP_VALUE_Msk = 0x20000 + // Bit PULLUP_VALUE. + USB_WRAP_OTG_CONF_PULLUP_VALUE = 0x20000 + // Position of USB_PAD_ENABLE field. + USB_WRAP_OTG_CONF_USB_PAD_ENABLE_Pos = 0x12 + // Bit mask of USB_PAD_ENABLE field. + USB_WRAP_OTG_CONF_USB_PAD_ENABLE_Msk = 0x40000 + // Bit USB_PAD_ENABLE. + USB_WRAP_OTG_CONF_USB_PAD_ENABLE = 0x40000 + // Position of AHB_CLK_FORCE_ON field. + USB_WRAP_OTG_CONF_AHB_CLK_FORCE_ON_Pos = 0x13 + // Bit mask of AHB_CLK_FORCE_ON field. + USB_WRAP_OTG_CONF_AHB_CLK_FORCE_ON_Msk = 0x80000 + // Bit AHB_CLK_FORCE_ON. + USB_WRAP_OTG_CONF_AHB_CLK_FORCE_ON = 0x80000 + // Position of PHY_CLK_FORCE_ON field. + USB_WRAP_OTG_CONF_PHY_CLK_FORCE_ON_Pos = 0x14 + // Bit mask of PHY_CLK_FORCE_ON field. + USB_WRAP_OTG_CONF_PHY_CLK_FORCE_ON_Msk = 0x100000 + // Bit PHY_CLK_FORCE_ON. + USB_WRAP_OTG_CONF_PHY_CLK_FORCE_ON = 0x100000 + // Position of PHY_TX_EDGE_SEL field. + USB_WRAP_OTG_CONF_PHY_TX_EDGE_SEL_Pos = 0x15 + // Bit mask of PHY_TX_EDGE_SEL field. + USB_WRAP_OTG_CONF_PHY_TX_EDGE_SEL_Msk = 0x200000 + // Bit PHY_TX_EDGE_SEL. + USB_WRAP_OTG_CONF_PHY_TX_EDGE_SEL = 0x200000 + // Position of DFIFO_FORCE_PU field. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PU_Pos = 0x16 + // Bit mask of DFIFO_FORCE_PU field. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PU_Msk = 0x400000 + // Bit DFIFO_FORCE_PU. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PU = 0x400000 + // Position of CLK_EN field. + USB_WRAP_OTG_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + USB_WRAP_OTG_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + USB_WRAP_OTG_CONF_CLK_EN = 0x80000000 + + // TEST_CONF: USB Internal PHY Testing Register + // Position of TEST_ENABLE field. + USB_WRAP_TEST_CONF_TEST_ENABLE_Pos = 0x0 + // Bit mask of TEST_ENABLE field. + USB_WRAP_TEST_CONF_TEST_ENABLE_Msk = 0x1 + // Bit TEST_ENABLE. + USB_WRAP_TEST_CONF_TEST_ENABLE = 0x1 + // Position of TEST_USB_OE field. + USB_WRAP_TEST_CONF_TEST_USB_OE_Pos = 0x1 + // Bit mask of TEST_USB_OE field. + USB_WRAP_TEST_CONF_TEST_USB_OE_Msk = 0x2 + // Bit TEST_USB_OE. + USB_WRAP_TEST_CONF_TEST_USB_OE = 0x2 + // Position of TEST_TX_DP field. + USB_WRAP_TEST_CONF_TEST_TX_DP_Pos = 0x2 + // Bit mask of TEST_TX_DP field. + USB_WRAP_TEST_CONF_TEST_TX_DP_Msk = 0x4 + // Bit TEST_TX_DP. + USB_WRAP_TEST_CONF_TEST_TX_DP = 0x4 + // Position of TEST_TX_DM field. + USB_WRAP_TEST_CONF_TEST_TX_DM_Pos = 0x3 + // Bit mask of TEST_TX_DM field. + USB_WRAP_TEST_CONF_TEST_TX_DM_Msk = 0x8 + // Bit TEST_TX_DM. + USB_WRAP_TEST_CONF_TEST_TX_DM = 0x8 + // Position of TEST_RX_RCV field. + USB_WRAP_TEST_CONF_TEST_RX_RCV_Pos = 0x4 + // Bit mask of TEST_RX_RCV field. + USB_WRAP_TEST_CONF_TEST_RX_RCV_Msk = 0x10 + // Bit TEST_RX_RCV. + USB_WRAP_TEST_CONF_TEST_RX_RCV = 0x10 + // Position of TEST_RX_DP field. + USB_WRAP_TEST_CONF_TEST_RX_DP_Pos = 0x5 + // Bit mask of TEST_RX_DP field. + USB_WRAP_TEST_CONF_TEST_RX_DP_Msk = 0x20 + // Bit TEST_RX_DP. + USB_WRAP_TEST_CONF_TEST_RX_DP = 0x20 + // Position of TEST_RX_DM field. + USB_WRAP_TEST_CONF_TEST_RX_DM_Pos = 0x6 + // Bit mask of TEST_RX_DM field. + USB_WRAP_TEST_CONF_TEST_RX_DM_Msk = 0x40 + // Bit TEST_RX_DM. + USB_WRAP_TEST_CONF_TEST_RX_DM = 0x40 + + // DATE: Version Control Register + // Position of USB_WRAP_DATE field. + USB_WRAP_DATE_USB_WRAP_DATE_Pos = 0x0 + // Bit mask of USB_WRAP_DATE field. + USB_WRAP_DATE_USB_WRAP_DATE_Msk = 0xffffffff +) + +// Constants for XTS_AES: XTS-AES-128 Flash Encryption +const ( + // PLAIN_0: Plaintext register %s + // Position of PLAIN field. + XTS_AES_PLAIN_PLAIN_Pos = 0x0 + // Bit mask of PLAIN field. + XTS_AES_PLAIN_PLAIN_Msk = 0xffffffff + + // LINESIZE: Configures the size of target memory space + // Position of LINESIZE field. + XTS_AES_LINESIZE_LINESIZE_Pos = 0x0 + // Bit mask of LINESIZE field. + XTS_AES_LINESIZE_LINESIZE_Msk = 0x3 + + // DESTINATION: Configures the type of the external memory + // Position of DESTINATION field. + XTS_AES_DESTINATION_DESTINATION_Pos = 0x0 + // Bit mask of DESTINATION field. + XTS_AES_DESTINATION_DESTINATION_Msk = 0x1 + // Bit DESTINATION. + XTS_AES_DESTINATION_DESTINATION = 0x1 + + // PHYSICAL_ADDRESS: Physical address + // Position of PHYSICAL_ADDRESS field. + XTS_AES_PHYSICAL_ADDRESS_PHYSICAL_ADDRESS_Pos = 0x0 + // Bit mask of PHYSICAL_ADDRESS field. + XTS_AES_PHYSICAL_ADDRESS_PHYSICAL_ADDRESS_Msk = 0x3fffffff + + // TRIGGER: Activates AES algorithm + // Position of TRIGGER field. + XTS_AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + XTS_AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + XTS_AES_TRIGGER_TRIGGER = 0x1 + + // RELEASE: Release control + // Position of RELEASE field. + XTS_AES_RELEASE_RELEASE_Pos = 0x0 + // Bit mask of RELEASE field. + XTS_AES_RELEASE_RELEASE_Msk = 0x1 + // Bit RELEASE. + XTS_AES_RELEASE_RELEASE = 0x1 + + // DESTROY: Destroys control + // Position of DESTROY field. + XTS_AES_DESTROY_DESTROY_Pos = 0x0 + // Bit mask of DESTROY field. + XTS_AES_DESTROY_DESTROY_Msk = 0x1 + // Bit DESTROY. + XTS_AES_DESTROY_DESTROY = 0x1 + + // STATE: Status register + // Position of STATE field. + XTS_AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + XTS_AES_STATE_STATE_Msk = 0x3 + + // DATE: Version control register + // Position of DATE field. + XTS_AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + XTS_AES_DATE_DATE_Msk = 0x3fffffff +) diff --git a/emb/device/esp/esp32s2ulp.go b/emb/device/esp/esp32s2ulp.go new file mode 100644 index 0000000..9d53590 --- /dev/null +++ b/emb/device/esp/esp32s2ulp.go @@ -0,0 +1,5212 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32s2-ulp.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32s2ulp + +/* +// 32-bit RISC-V MCU +*/ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32-S2-ULP" + CPU = "RV32IMC" + FPUPresent = false + NVICPrioBits = 4 +) + +// Interrupt numbers. +const ( + // SENS Peripheral + IRQ_TOUCH_DONE_INT = 0 + + // SENS Peripheral + IRQ_TOUCH_INACTIVE_INT = 1 + + // SENS Peripheral + IRQ_TOUCH_ACTIVE_INT = 2 + + // SENS Peripheral + IRQ_SARADC1_DONE_INT = 3 + + // SENS Peripheral + IRQ_SARADC2_DONE_INT = 4 + + // SENS Peripheral + IRQ_TSENS_DONE_INT = 5 + + // Real-Time Clock Control + IRQ_RISCV_START_INT = 6 + + // Real-Time Clock Control + IRQ_SW_INT = 7 + + // Real-Time Clock Control + IRQ_SWD_INT = 8 + + // Highest interrupt number on this device. + IRQ_max = 8 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_TOUCH_DONE_INT: + callHandlers(IRQ_TOUCH_DONE_INT) + case IRQ_TOUCH_INACTIVE_INT: + callHandlers(IRQ_TOUCH_INACTIVE_INT) + case IRQ_TOUCH_ACTIVE_INT: + callHandlers(IRQ_TOUCH_ACTIVE_INT) + case IRQ_SARADC1_DONE_INT: + callHandlers(IRQ_SARADC1_DONE_INT) + case IRQ_SARADC2_DONE_INT: + callHandlers(IRQ_SARADC2_DONE_INT) + case IRQ_TSENS_DONE_INT: + callHandlers(IRQ_TSENS_DONE_INT) + case IRQ_RISCV_START_INT: + callHandlers(IRQ_RISCV_START_INT) + case IRQ_SW_INT: + callHandlers(IRQ_SW_INT) + case IRQ_SWD_INT: + callHandlers(IRQ_SWD_INT) + } +} + +// Peripherals. +var ( + // Low-power Input/Output + RTC_IO = (*RTCIO_Type)(unsafe.Pointer(uintptr(0xa400))) + + // Real-Time Clock Control + RTC_CNTL = (*RTC_CNTL_Type)(unsafe.Pointer(uintptr(0x8000))) + + // Low-power I2C (Inter-Integrated Circuit) Controller + RTC_I2C = (*RTC_I2C_Type)(unsafe.Pointer(uintptr(0xec00))) + + // SENS Peripheral + SENS = (*SENS_Type)(unsafe.Pointer(uintptr(0xc800))) +) + +// Low-power Input/Output +type RTCIO_Type struct { + RTC_GPIO_OUT volatile.Register32 // 0x0 + RTC_GPIO_OUT_W1TS volatile.Register32 // 0x4 + RTC_GPIO_OUT_W1TC volatile.Register32 // 0x8 + RTC_GPIO_ENABLE volatile.Register32 // 0xC + RTC_GPIO_ENABLE_W1TS volatile.Register32 // 0x10 + RTC_GPIO_ENABLE_W1TC volatile.Register32 // 0x14 + RTC_GPIO_STATUS volatile.Register32 // 0x18 + RTC_GPIO_STATUS_W1TS volatile.Register32 // 0x1C + RTC_GPIO_STATUS_W1TC volatile.Register32 // 0x20 + RTC_GPIO_IN volatile.Register32 // 0x24 + RTC_GPIO_PIN0 volatile.Register32 // 0x28 + RTC_GPIO_PIN1 volatile.Register32 // 0x2C + RTC_GPIO_PIN2 volatile.Register32 // 0x30 + RTC_GPIO_PIN3 volatile.Register32 // 0x34 + RTC_GPIO_PIN4 volatile.Register32 // 0x38 + RTC_GPIO_PIN5 volatile.Register32 // 0x3C + RTC_GPIO_PIN6 volatile.Register32 // 0x40 + RTC_GPIO_PIN7 volatile.Register32 // 0x44 + RTC_GPIO_PIN8 volatile.Register32 // 0x48 + RTC_GPIO_PIN9 volatile.Register32 // 0x4C + RTC_GPIO_PIN10 volatile.Register32 // 0x50 + RTC_GPIO_PIN11 volatile.Register32 // 0x54 + RTC_GPIO_PIN12 volatile.Register32 // 0x58 + RTC_GPIO_PIN13 volatile.Register32 // 0x5C + RTC_GPIO_PIN14 volatile.Register32 // 0x60 + RTC_GPIO_PIN15 volatile.Register32 // 0x64 + RTC_GPIO_PIN16 volatile.Register32 // 0x68 + RTC_GPIO_PIN17 volatile.Register32 // 0x6C + RTC_GPIO_PIN18 volatile.Register32 // 0x70 + RTC_GPIO_PIN19 volatile.Register32 // 0x74 + RTC_GPIO_PIN20 volatile.Register32 // 0x78 + RTC_GPIO_PIN21 volatile.Register32 // 0x7C + RTC_DEBUG_SEL volatile.Register32 // 0x80 + TOUCH_PAD0 volatile.Register32 // 0x84 + TOUCH_PAD1 volatile.Register32 // 0x88 + TOUCH_PAD2 volatile.Register32 // 0x8C + TOUCH_PAD3 volatile.Register32 // 0x90 + TOUCH_PAD4 volatile.Register32 // 0x94 + TOUCH_PAD5 volatile.Register32 // 0x98 + TOUCH_PAD6 volatile.Register32 // 0x9C + TOUCH_PAD7 volatile.Register32 // 0xA0 + TOUCH_PAD8 volatile.Register32 // 0xA4 + TOUCH_PAD9 volatile.Register32 // 0xA8 + TOUCH_PAD10 volatile.Register32 // 0xAC + TOUCH_PAD11 volatile.Register32 // 0xB0 + TOUCH_PAD12 volatile.Register32 // 0xB4 + TOUCH_PAD13 volatile.Register32 // 0xB8 + TOUCH_PAD14 volatile.Register32 // 0xBC + XTAL_32P_PAD volatile.Register32 // 0xC0 + XTAL_32N_PAD volatile.Register32 // 0xC4 + PAD_DAC1 volatile.Register32 // 0xC8 + PAD_DAC2 volatile.Register32 // 0xCC + RTC_PAD19 volatile.Register32 // 0xD0 + RTC_PAD20 volatile.Register32 // 0xD4 + RTC_PAD21 volatile.Register32 // 0xD8 + EXT_WAKEUP0 volatile.Register32 // 0xDC + XTL_EXT_CTR volatile.Register32 // 0xE0 + SAR_I2C_IO volatile.Register32 // 0xE4 + RTC_IO_TOUCH_CTRL volatile.Register32 // 0xE8 + _ [272]byte + RTC_IO_DATE volatile.Register32 // 0x1FC +} + +// RTCIO.RTC_GPIO_OUT: RTC GPIO output register +func (o *RTCIO_Type) SetRTC_GPIO_OUT_GPIO_OUT_DATA(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_OUT_GPIO_OUT_DATA() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_OUT_W1TS: RTC GPIO output bit set register +func (o *RTCIO_Type) SetRTC_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_OUT_W1TC: RTC GPIO output bit clear register +func (o *RTCIO_Type) SetRTC_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_ENABLE: RTC GPIO output enable register +func (o *RTCIO_Type) SetRTC_GPIO_ENABLE_REG_RTCIO_REG_GPIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_ENABLE_REG_RTCIO_REG_GPIO_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_ENABLE_W1TS: RTC GPIO output enable bit set register +func (o *RTCIO_Type) SetRTC_GPIO_ENABLE_W1TS_REG_RTCIO_REG_GPIO_ENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_ENABLE_W1TS_REG_RTCIO_REG_GPIO_ENABLE_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_ENABLE_W1TC: RTC GPIO output enable bit clear register +func (o *RTCIO_Type) SetRTC_GPIO_ENABLE_W1TC_REG_RTCIO_REG_GPIO_ENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_ENABLE_W1TC_REG_RTCIO_REG_GPIO_ENABLE_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_STATUS: RTC GPIO interrupt status register +func (o *RTCIO_Type) SetRTC_GPIO_STATUS_GPIO_STATUS_INT(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_STATUS_GPIO_STATUS_INT() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_STATUS_W1TS: RTC GPIO interrupt status bit set register +func (o *RTCIO_Type) SetRTC_GPIO_STATUS_W1TS_GPIO_STATUS_INT_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_STATUS_W1TS_GPIO_STATUS_INT_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_STATUS_W1TC: RTC GPIO interrupt status bit clear register +func (o *RTCIO_Type) SetRTC_GPIO_STATUS_W1TC_GPIO_STATUS_INT_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_STATUS_W1TC_GPIO_STATUS_INT_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_IN: RTC GPIO input register +func (o *RTCIO_Type) SetRTC_GPIO_IN_GPIO_IN_NEXT(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_IN.Reg, volatile.LoadUint32(&o.RTC_GPIO_IN.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_IN_GPIO_IN_NEXT() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_IN.Reg) & 0xfffffc00) >> 10 +} + +// RTCIO.RTC_GPIO_PIN0: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN0_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN0.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN0_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN0_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN0.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN0_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN0_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN0.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN0_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN1: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN1_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN1.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN1_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN1_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN1.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN1_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN1_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN1.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN1_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN2: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN2_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN2.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN2_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN2_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN2.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN2_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN2_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN2.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN2_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN3: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN3_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN3.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN3_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN3_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN3.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN3_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN3_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN3.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN3_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN4: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN4_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN4.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN4_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN4_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN4.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN4_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN4_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN4.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN4_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN5: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN5_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN5.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN5_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN5_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN5.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN5_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN5_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN5.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN5_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN6: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN6_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN6.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN6_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN6_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN6.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN6_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN6_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN6.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN6_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN7: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN7_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN7.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN7_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN7_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN7.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN7_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN7_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN7.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN7_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN8: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN8_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN8.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN8_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN8_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN8.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN8_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN8_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN8.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN8_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN9: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN9_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN9.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN9_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN9_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN9.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN9_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN9_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN9.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN9_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN10: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN10_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN10.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN10_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN10_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN10.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN10_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN10_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN10.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN10_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN11: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN11_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN11.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN11_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN11_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN11.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN11_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN11_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN11.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN11_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN12: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN12_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN12.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN12_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN12_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN12.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN12_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN12_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN12.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN12_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN13: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN13_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN13.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN13_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN13_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN13.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN13_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN13_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN13.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN13_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN14: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN14_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN14.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN14_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN14_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN14.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN14_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN14_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN14.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN14_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN15: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN15_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN15.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN15_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN15_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN15.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN15_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN15_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN15.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN15_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN16: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN16_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN16.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN16_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN16_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN16.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN16_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN16_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN16.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN16_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN17: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN17_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN17.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN17_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN17_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN17.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN17_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN17_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN17.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN17_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN18: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN18_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN18.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN18_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN18_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN18.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN18_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN18_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN18.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN18_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN19: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN19_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN19.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN19_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN19_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN19.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN19_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN19_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN19.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN19_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN20: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN20_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN20.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN20_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN20_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN20.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN20_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN20_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN20.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN20_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_GPIO_PIN21: RTC configuration for pin %s +func (o *RTCIO_Type) SetRTC_GPIO_PIN21_GPIO_PIN_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN21.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg)&^(0x4)|value<<2) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN21_GPIO_PIN_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg) & 0x4) >> 2 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN21_GPIO_PIN_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN21.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg)&^(0x380)|value<<7) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN21_GPIO_PIN_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg) & 0x380) >> 7 +} +func (o *RTCIO_Type) SetRTC_GPIO_PIN21_GPIO_PIN_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN21.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg)&^(0x400)|value<<10) +} +func (o *RTCIO_Type) GetRTC_GPIO_PIN21_GPIO_PIN_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg) & 0x400) >> 10 +} + +// RTCIO.RTC_DEBUG_SEL: RTC debug select register +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f)|value) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL0() uint32 { + return volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x3e0)|value<<5) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x3e0) >> 5 +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x7c00)|value<<10) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x7c00) >> 10 +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0xf8000)|value<<15) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0xf8000) >> 15 +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f00000)|value<<20) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL4() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f00000) >> 20 +} +func (o *RTCIO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x2000000)|value<<25) +} +func (o *RTCIO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x2000000) >> 25 +} + +// RTCIO.TOUCH_PAD0: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD0_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD0_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD1: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD1_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD1_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD2: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD2_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD2_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD3: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD3_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD3_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD4: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD4_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD4_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD5: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD5_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD5_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD6: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD6_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD6_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD7: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD7_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD7_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD8: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD8_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD8_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD9: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD9_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD9_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD10: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD10_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD10_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD11: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD11_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD11_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD12: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD12_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD12_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD13: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD13_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD13_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x60000000) >> 29 +} + +// RTCIO.TOUCH_PAD14: Touch pad %s configuration register +func (o *RTCIO_Type) SetTOUCH_PAD14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x100000)|value<<20) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x100000) >> 20 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x200000)|value<<21) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x200000) >> 21 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x400000)|value<<22) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x400000) >> 22 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x3800000)|value<<23) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x3800000) >> 23 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetTOUCH_PAD14_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetTOUCH_PAD14_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x60000000) >> 29 +} + +// RTCIO.XTAL_32P_PAD: 32KHz crystal P-pad configuration register +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetXTAL_32P_PAD_X32P_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetXTAL_32P_PAD_X32P_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x60000000) >> 29 +} + +// RTCIO.XTAL_32N_PAD: 32KHz crystal N-pad configuration register +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetXTAL_32N_PAD_X32N_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetXTAL_32N_PAD_X32N_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x60000000) >> 29 +} + +// RTCIO.PAD_DAC1: DAC1 configuration register +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x7f8)|value<<3) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x7f8) >> 3 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x800)|value<<11) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x800) >> 11 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x1000)|value<<12) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x1000) >> 12 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetPAD_DAC1_PDAC1_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetPAD_DAC1_PDAC1_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x60000000) >> 29 +} + +// RTCIO.PAD_DAC2: DAC2 configuration register +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x7f8)|value<<3) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x7f8) >> 3 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x800)|value<<11) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x800) >> 11 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x1000)|value<<12) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x1000) >> 12 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetPAD_DAC2_PDAC2_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetPAD_DAC2_PDAC2_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x60000000) >> 29 +} + +// RTCIO.RTC_PAD19: Touch pad 19 configuration register +func (o *RTCIO_Type) SetRTC_PAD19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetRTC_PAD19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetRTC_PAD19_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetRTC_PAD19_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetRTC_PAD19_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetRTC_PAD19_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetRTC_PAD19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetRTC_PAD19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetRTC_PAD19_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetRTC_PAD19_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetRTC_PAD19_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetRTC_PAD19_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetRTC_PAD19_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetRTC_PAD19_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetRTC_PAD19_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetRTC_PAD19_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetRTC_PAD19_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetRTC_PAD19_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x60000000) >> 29 +} + +// RTCIO.RTC_PAD20: Touch pad 20 configuration register +func (o *RTCIO_Type) SetRTC_PAD20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetRTC_PAD20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetRTC_PAD20_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetRTC_PAD20_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetRTC_PAD20_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetRTC_PAD20_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetRTC_PAD20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetRTC_PAD20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetRTC_PAD20_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetRTC_PAD20_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetRTC_PAD20_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetRTC_PAD20_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetRTC_PAD20_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetRTC_PAD20_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetRTC_PAD20_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetRTC_PAD20_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetRTC_PAD20_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetRTC_PAD20_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x60000000) >> 29 +} + +// RTCIO.RTC_PAD21: Touch pad 21 configuration register +func (o *RTCIO_Type) SetRTC_PAD21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x2000)|value<<13) +} +func (o *RTCIO_Type) GetRTC_PAD21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x2000) >> 13 +} +func (o *RTCIO_Type) SetRTC_PAD21_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x4000)|value<<14) +} +func (o *RTCIO_Type) GetRTC_PAD21_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x4000) >> 14 +} +func (o *RTCIO_Type) SetRTC_PAD21_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x8000)|value<<15) +} +func (o *RTCIO_Type) GetRTC_PAD21_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x8000) >> 15 +} +func (o *RTCIO_Type) SetRTC_PAD21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x10000)|value<<16) +} +func (o *RTCIO_Type) GetRTC_PAD21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x10000) >> 16 +} +func (o *RTCIO_Type) SetRTC_PAD21_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x60000)|value<<17) +} +func (o *RTCIO_Type) GetRTC_PAD21_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x60000) >> 17 +} +func (o *RTCIO_Type) SetRTC_PAD21_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x80000)|value<<19) +} +func (o *RTCIO_Type) GetRTC_PAD21_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x80000) >> 19 +} +func (o *RTCIO_Type) SetRTC_PAD21_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x8000000)|value<<27) +} +func (o *RTCIO_Type) GetRTC_PAD21_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x8000000) >> 27 +} +func (o *RTCIO_Type) SetRTC_PAD21_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x10000000)|value<<28) +} +func (o *RTCIO_Type) GetRTC_PAD21_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x10000000) >> 28 +} +func (o *RTCIO_Type) SetRTC_PAD21_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x60000000)|value<<29) +} +func (o *RTCIO_Type) GetRTC_PAD21_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x60000000) >> 29 +} + +// RTCIO.EXT_WAKEUP0: External wake up configuration register +func (o *RTCIO_Type) SetEXT_WAKEUP0_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP0.Reg, volatile.LoadUint32(&o.EXT_WAKEUP0.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTCIO_Type) GetEXT_WAKEUP0_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP0.Reg) & 0xf8000000) >> 27 +} + +// RTCIO.XTL_EXT_CTR: Crystal power down enable GPIO source +func (o *RTCIO_Type) SetXTL_EXT_CTR_SEL(value uint32) { + volatile.StoreUint32(&o.XTL_EXT_CTR.Reg, volatile.LoadUint32(&o.XTL_EXT_CTR.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTCIO_Type) GetXTL_EXT_CTR_SEL() uint32 { + return (volatile.LoadUint32(&o.XTL_EXT_CTR.Reg) & 0xf8000000) >> 27 +} + +// RTCIO.SAR_I2C_IO: RTC I2C pad selection +func (o *RTCIO_Type) SetSAR_I2C_IO_SAR_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xf800000)|value<<23) +} +func (o *RTCIO_Type) GetSAR_I2C_IO_SAR_DEBUG_BIT_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xf800000) >> 23 +} +func (o *RTCIO_Type) SetSAR_I2C_IO_SAR_I2C_SCL_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0x30000000)|value<<28) +} +func (o *RTCIO_Type) GetSAR_I2C_IO_SAR_I2C_SCL_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0x30000000) >> 28 +} +func (o *RTCIO_Type) SetSAR_I2C_IO_SAR_I2C_SDA_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTCIO_Type) GetSAR_I2C_IO_SAR_I2C_SDA_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xc0000000) >> 30 +} + +// RTCIO.RTC_IO_TOUCH_CTRL: Touch control register +func (o *RTCIO_Type) SetRTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL(value uint32) { + volatile.StoreUint32(&o.RTC_IO_TOUCH_CTRL.Reg, volatile.LoadUint32(&o.RTC_IO_TOUCH_CTRL.Reg)&^(0xf)|value) +} +func (o *RTCIO_Type) GetRTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL() uint32 { + return volatile.LoadUint32(&o.RTC_IO_TOUCH_CTRL.Reg) & 0xf +} +func (o *RTCIO_Type) SetRTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE(value uint32) { + volatile.StoreUint32(&o.RTC_IO_TOUCH_CTRL.Reg, volatile.LoadUint32(&o.RTC_IO_TOUCH_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *RTCIO_Type) GetRTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE() uint32 { + return (volatile.LoadUint32(&o.RTC_IO_TOUCH_CTRL.Reg) & 0x10) >> 4 +} + +// RTCIO.RTC_IO_DATE: Version control register +func (o *RTCIO_Type) SetRTC_IO_DATE_IO_DATE(value uint32) { + volatile.StoreUint32(&o.RTC_IO_DATE.Reg, volatile.LoadUint32(&o.RTC_IO_DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTCIO_Type) GetRTC_IO_DATE_IO_DATE() uint32 { + return volatile.LoadUint32(&o.RTC_IO_DATE.Reg) & 0xfffffff +} + +// Real-Time Clock Control +type RTC_CNTL_Type struct { + _ [248]byte + ULP_CP_TIMER volatile.Register32 // 0xF8 + ULP_CP_CTRL volatile.Register32 // 0xFC + COCPU_CTRL volatile.Register32 // 0x100 + _ [44]byte + ULP_CP_TIMER_1 volatile.Register32 // 0x130 +} + +// RTC_CNTL.ULP_CP_TIMER: Configure coprocessor timer +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_PC_INIT(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x7ff)|value) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_PC_INIT() uint32 { + return volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x7ff +} +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_SLP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_SLP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.ULP_CP_CTRL: ULP-FSM configuration register +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x7ff)|value) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT() uint32 { + return volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x7ff +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x3ff800)|value<<11) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x3ff800) >> 11 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_CLK_FO(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_RESET(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_RESET() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_FORCE_START_TOP(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_FORCE_START_TOP() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_START_TOP(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_START_TOP() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.COCPU_CTRL: ULP-RISCV configuration register +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_CLK_FO(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_CLK_FO() uint32 { + return volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_START_2_RESET_DIS(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x7e)|value<<1) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_START_2_RESET_DIS() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x7e) >> 1 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_START_2_INTR_EN(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x1f80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_START_2_INTR_EN() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x1f80) >> 7 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SHUT(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SHUT() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SHUT_2_CLK_DIS(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SHUT_2_CLK_DIS() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SHUT_RESET_EN(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SHUT_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SEL(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SEL() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_DONE_FORCE(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_DONE_FORCE() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_DONE(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_DONE() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SW_INT_TRIGGER(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SW_INT_TRIGGER() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x4000000) >> 26 +} + +// RTC_CNTL.ULP_CP_TIMER_1: Configure sleep cycle of the timer +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER_1.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg)&^(0xffffff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg) & 0xffffff00) >> 8 +} + +// Low-power I2C (Inter-Integrated Circuit) Controller +type RTC_I2C_Type struct { + SCL_LOW volatile.Register32 // 0x0 + CTRL volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + SCL_HIGH volatile.Register32 // 0x14 + SDA_DUTY volatile.Register32 // 0x18 + SCL_START_PERIOD volatile.Register32 // 0x1C + SCL_STOP_PERIOD volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_RAW volatile.Register32 // 0x28 + INT_ST volatile.Register32 // 0x2C + INT_ENA volatile.Register32 // 0x30 + DATA volatile.Register32 // 0x34 + CMD0 volatile.Register32 // 0x38 + CMD1 volatile.Register32 // 0x3C + CMD2 volatile.Register32 // 0x40 + CMD3 volatile.Register32 // 0x44 + CMD4 volatile.Register32 // 0x48 + CMD5 volatile.Register32 // 0x4C + CMD6 volatile.Register32 // 0x50 + CMD7 volatile.Register32 // 0x54 + CMD8 volatile.Register32 // 0x58 + CMD9 volatile.Register32 // 0x5C + CMD10 volatile.Register32 // 0x60 + CMD11 volatile.Register32 // 0x64 + CMD12 volatile.Register32 // 0x68 + CMD13 volatile.Register32 // 0x6C + CMD14 volatile.Register32 // 0x70 + CMD15 volatile.Register32 // 0x74 + _ [132]byte + DATE volatile.Register32 // 0xFC +} + +// RTC_I2C.SCL_LOW: Configure the low level width of SCL +func (o *RTC_I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW.Reg, volatile.LoadUint32(&o.SCL_LOW.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW.Reg) & 0xfffff +} + +// RTC_I2C.CTRL: Transmission setting +func (o *RTC_I2C_Type) SetCTRL_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetCTRL_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetCTRL_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetCTRL_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetCTRL_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetCTRL_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetCTRL_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetCTRL_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetCTRL_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetCTRL_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetCTRL_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetCTRL_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetCTRL_CLK_GATE_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_I2C_Type) GetCTRL_CLK_GATE_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_I2C_Type) SetCTRL_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_I2C_Type) GetCTRL_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_I2C_Type) SetCTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCTRL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.STATUS: RTC I2C status +func (o *RTC_I2C_Type) SetSTATUS_ACK_REC(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetSTATUS_ACK_REC() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetSTATUS_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetSTATUS_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetSTATUS_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetSTATUS_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetSTATUS_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetSTATUS_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetSTATUS_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetSTATUS_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetSTATUS_BYTE_TRANS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetSTATUS_BYTE_TRANS() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetSTATUS_OP_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xc0)|value<<6) +} +func (o *RTC_I2C_Type) GetSTATUS_OP_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xc0) >> 6 +} +func (o *RTC_I2C_Type) SetSTATUS_SHIFT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *RTC_I2C_Type) GetSTATUS_SHIFT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xff0000) >> 16 +} +func (o *RTC_I2C_Type) SetSTATUS_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RTC_I2C_Type) GetSTATUS_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RTC_I2C_Type) SetSTATUS_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_I2C_Type) GetSTATUS_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x70000000) >> 28 +} + +// RTC_I2C.TO: Configure RTC I2C timeout +func (o *RTC_I2C_Type) SetTO_TIME_OUT(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetTO_TIME_OUT() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0xfffff +} + +// RTC_I2C.SLAVE_ADDR: Configure slave address +func (o *RTC_I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *RTC_I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.SCL_HIGH: Configure the high level width of SCL +func (o *RTC_I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH.Reg, volatile.LoadUint32(&o.SCL_HIGH.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH.Reg) & 0xfffff +} + +// RTC_I2C.SDA_DUTY: Configure the SDA hold time after a negative SCL edge +func (o *RTC_I2C_Type) SetSDA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.SDA_DUTY.Reg, volatile.LoadUint32(&o.SDA_DUTY.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSDA_DUTY_NUM() uint32 { + return volatile.LoadUint32(&o.SDA_DUTY.Reg) & 0xfffff +} + +// RTC_I2C.SCL_START_PERIOD: Configure the delay between the SDA and SCL negative edge for a start condition +func (o *RTC_I2C_Type) SetSCL_START_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_START_PERIOD.Reg, volatile.LoadUint32(&o.SCL_START_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_START_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_START_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.SCL_STOP_PERIOD: Configure the delay between SDA and SCL positive edge for a stop condition +func (o *RTC_I2C_Type) SetSCL_STOP_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_PERIOD.Reg, volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_STOP_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.INT_CLR: Clear RTC I2C interrupt +func (o *RTC_I2C_Type) SetINT_CLR_SLAVE_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_CLR_SLAVE_TRAN_COMP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_CLR_MASTER_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_CLR_MASTER_TRAN_COMP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_CLR_ACK_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_CLR_ACK_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_CLR_RX_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_CLR_RX_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_CLR_TX_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_CLR_TX_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_CLR_DETECT_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_CLR_DETECT_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_RAW: RTC I2C raw interrupt +func (o *RTC_I2C_Type) SetINT_RAW_SLAVE_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_RAW_SLAVE_TRAN_COMP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_RAW_MASTER_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_RAW_MASTER_TRAN_COMP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_RAW_ACK_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_RAW_ACK_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_RAW_RX_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_RAW_RX_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_RAW_TX_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_RAW_TX_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_RAW_DETECT_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_RAW_DETECT_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_ST: RTC I2C interrupt status +func (o *RTC_I2C_Type) SetINT_ST_SLAVE_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_ST_SLAVE_TRAN_COMP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_ST_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_ST_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_ST_MASTER_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_ST_MASTER_TRAN_COMP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_ST_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_ST_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_ST_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_ST_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_ST_ACK_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_ST_ACK_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_ST_RX_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_ST_RX_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_ST_TX_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_ST_TX_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_ST_DETECT_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_ST_DETECT_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_ENA: Enable RTC I2C interrupt +func (o *RTC_I2C_Type) SetINT_ENA_SLAVE_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_ENA_SLAVE_TRAN_COMP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_ENA_MASTER_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_ENA_MASTER_TRAN_COMP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_ENA_ACK_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_ENA_ACK_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_ENA_RX_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_ENA_RX_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_ENA_TX_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_ENA_TX_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_ENA_DETECT_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_ENA_DETECT_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// RTC_I2C.DATA: RTC I2C read data +func (o *RTC_I2C_Type) SetDATA_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *RTC_I2C_Type) GetDATA_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} +func (o *RTC_I2C_Type) SetDATA_SLAVE_TX_DATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_I2C_Type) GetDATA_SLAVE_TX_DATA() uint32 { + return (volatile.LoadUint32(&o.DATA.Reg) & 0xff00) >> 8 +} +func (o *RTC_I2C_Type) SetDATA_DONE(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetDATA_DONE() uint32 { + return (volatile.LoadUint32(&o.DATA.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD0: RTC I2C Command 0 +func (o *RTC_I2C_Type) SetCMD0_COMMAND0(value uint32) { + volatile.StoreUint32(&o.CMD0.Reg, volatile.LoadUint32(&o.CMD0.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD0_COMMAND0() uint32 { + return volatile.LoadUint32(&o.CMD0.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD0_COMMAND0_DONE(value uint32) { + volatile.StoreUint32(&o.CMD0.Reg, volatile.LoadUint32(&o.CMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD0_COMMAND0_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD0.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD1: RTC I2C Command 1 +func (o *RTC_I2C_Type) SetCMD1_COMMAND1(value uint32) { + volatile.StoreUint32(&o.CMD1.Reg, volatile.LoadUint32(&o.CMD1.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD1_COMMAND1() uint32 { + return volatile.LoadUint32(&o.CMD1.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD1_COMMAND1_DONE(value uint32) { + volatile.StoreUint32(&o.CMD1.Reg, volatile.LoadUint32(&o.CMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD1_COMMAND1_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD1.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD2: RTC I2C Command 2 +func (o *RTC_I2C_Type) SetCMD2_COMMAND2(value uint32) { + volatile.StoreUint32(&o.CMD2.Reg, volatile.LoadUint32(&o.CMD2.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD2_COMMAND2() uint32 { + return volatile.LoadUint32(&o.CMD2.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD2_COMMAND2_DONE(value uint32) { + volatile.StoreUint32(&o.CMD2.Reg, volatile.LoadUint32(&o.CMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD2_COMMAND2_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD2.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD3: RTC I2C Command 3 +func (o *RTC_I2C_Type) SetCMD3_COMMAND3(value uint32) { + volatile.StoreUint32(&o.CMD3.Reg, volatile.LoadUint32(&o.CMD3.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD3_COMMAND3() uint32 { + return volatile.LoadUint32(&o.CMD3.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD3_COMMAND3_DONE(value uint32) { + volatile.StoreUint32(&o.CMD3.Reg, volatile.LoadUint32(&o.CMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD3_COMMAND3_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD3.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD4: RTC I2C Command 4 +func (o *RTC_I2C_Type) SetCMD4_COMMAND4(value uint32) { + volatile.StoreUint32(&o.CMD4.Reg, volatile.LoadUint32(&o.CMD4.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD4_COMMAND4() uint32 { + return volatile.LoadUint32(&o.CMD4.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD4_COMMAND4_DONE(value uint32) { + volatile.StoreUint32(&o.CMD4.Reg, volatile.LoadUint32(&o.CMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD4_COMMAND4_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD4.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD5: RTC I2C Command 5 +func (o *RTC_I2C_Type) SetCMD5_COMMAND5(value uint32) { + volatile.StoreUint32(&o.CMD5.Reg, volatile.LoadUint32(&o.CMD5.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD5_COMMAND5() uint32 { + return volatile.LoadUint32(&o.CMD5.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD5_COMMAND5_DONE(value uint32) { + volatile.StoreUint32(&o.CMD5.Reg, volatile.LoadUint32(&o.CMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD5_COMMAND5_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD5.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD6: RTC I2C Command 6 +func (o *RTC_I2C_Type) SetCMD6_COMMAND6(value uint32) { + volatile.StoreUint32(&o.CMD6.Reg, volatile.LoadUint32(&o.CMD6.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD6_COMMAND6() uint32 { + return volatile.LoadUint32(&o.CMD6.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD6_COMMAND6_DONE(value uint32) { + volatile.StoreUint32(&o.CMD6.Reg, volatile.LoadUint32(&o.CMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD6_COMMAND6_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD6.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD7: RTC I2C Command 7 +func (o *RTC_I2C_Type) SetCMD7_COMMAND7(value uint32) { + volatile.StoreUint32(&o.CMD7.Reg, volatile.LoadUint32(&o.CMD7.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD7_COMMAND7() uint32 { + return volatile.LoadUint32(&o.CMD7.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD7_COMMAND7_DONE(value uint32) { + volatile.StoreUint32(&o.CMD7.Reg, volatile.LoadUint32(&o.CMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD7_COMMAND7_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD7.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD8: RTC I2C Command 8 +func (o *RTC_I2C_Type) SetCMD8_COMMAND8(value uint32) { + volatile.StoreUint32(&o.CMD8.Reg, volatile.LoadUint32(&o.CMD8.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD8_COMMAND8() uint32 { + return volatile.LoadUint32(&o.CMD8.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD8_COMMAND8_DONE(value uint32) { + volatile.StoreUint32(&o.CMD8.Reg, volatile.LoadUint32(&o.CMD8.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD8_COMMAND8_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD8.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD9: RTC I2C Command 9 +func (o *RTC_I2C_Type) SetCMD9_COMMAND9(value uint32) { + volatile.StoreUint32(&o.CMD9.Reg, volatile.LoadUint32(&o.CMD9.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD9_COMMAND9() uint32 { + return volatile.LoadUint32(&o.CMD9.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD9_COMMAND9_DONE(value uint32) { + volatile.StoreUint32(&o.CMD9.Reg, volatile.LoadUint32(&o.CMD9.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD9_COMMAND9_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD9.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD10: RTC I2C Command 10 +func (o *RTC_I2C_Type) SetCMD10_COMMAND10(value uint32) { + volatile.StoreUint32(&o.CMD10.Reg, volatile.LoadUint32(&o.CMD10.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD10_COMMAND10() uint32 { + return volatile.LoadUint32(&o.CMD10.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD10_COMMAND10_DONE(value uint32) { + volatile.StoreUint32(&o.CMD10.Reg, volatile.LoadUint32(&o.CMD10.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD10_COMMAND10_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD10.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD11: RTC I2C Command 11 +func (o *RTC_I2C_Type) SetCMD11_COMMAND11(value uint32) { + volatile.StoreUint32(&o.CMD11.Reg, volatile.LoadUint32(&o.CMD11.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD11_COMMAND11() uint32 { + return volatile.LoadUint32(&o.CMD11.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD11_COMMAND11_DONE(value uint32) { + volatile.StoreUint32(&o.CMD11.Reg, volatile.LoadUint32(&o.CMD11.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD11_COMMAND11_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD11.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD12: RTC I2C Command 12 +func (o *RTC_I2C_Type) SetCMD12_COMMAND12(value uint32) { + volatile.StoreUint32(&o.CMD12.Reg, volatile.LoadUint32(&o.CMD12.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD12_COMMAND12() uint32 { + return volatile.LoadUint32(&o.CMD12.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD12_COMMAND12_DONE(value uint32) { + volatile.StoreUint32(&o.CMD12.Reg, volatile.LoadUint32(&o.CMD12.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD12_COMMAND12_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD12.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD13: RTC I2C Command 13 +func (o *RTC_I2C_Type) SetCMD13_COMMAND13(value uint32) { + volatile.StoreUint32(&o.CMD13.Reg, volatile.LoadUint32(&o.CMD13.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD13_COMMAND13() uint32 { + return volatile.LoadUint32(&o.CMD13.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD13_COMMAND13_DONE(value uint32) { + volatile.StoreUint32(&o.CMD13.Reg, volatile.LoadUint32(&o.CMD13.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD13_COMMAND13_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD13.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD14: RTC I2C Command 14 +func (o *RTC_I2C_Type) SetCMD14_COMMAND14(value uint32) { + volatile.StoreUint32(&o.CMD14.Reg, volatile.LoadUint32(&o.CMD14.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD14_COMMAND14() uint32 { + return volatile.LoadUint32(&o.CMD14.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD14_COMMAND14_DONE(value uint32) { + volatile.StoreUint32(&o.CMD14.Reg, volatile.LoadUint32(&o.CMD14.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD14_COMMAND14_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD14.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD15: RTC I2C Command 15 +func (o *RTC_I2C_Type) SetCMD15_COMMAND15(value uint32) { + volatile.StoreUint32(&o.CMD15.Reg, volatile.LoadUint32(&o.CMD15.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD15_COMMAND15() uint32 { + return volatile.LoadUint32(&o.CMD15.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD15_COMMAND15_DONE(value uint32) { + volatile.StoreUint32(&o.CMD15.Reg, volatile.LoadUint32(&o.CMD15.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD15_COMMAND15_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD15.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.DATE: Version control register +func (o *RTC_I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SENS Peripheral +type SENS_Type struct { + _ [64]byte + SAR_SLAVE_ADDR1 volatile.Register32 // 0x40 + SAR_SLAVE_ADDR2 volatile.Register32 // 0x44 + SAR_SLAVE_ADDR3 volatile.Register32 // 0x48 + SAR_SLAVE_ADDR4 volatile.Register32 // 0x4C + _ [8]byte + SAR_I2C_CTRL volatile.Register32 // 0x58 + _ [204]byte + SAR_COCPU_INT_RAW volatile.Register32 // 0x128 + SAR_COCPU_INT_ENA volatile.Register32 // 0x12C + SAR_COCPU_INT_ST volatile.Register32 // 0x130 + SAR_COCPU_INT_CLR volatile.Register32 // 0x134 +} + +// SENS.SAR_SLAVE_ADDR1: Configure slave addresses 0-1 of RTC I2C +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3ff800) >> 11 +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_MEAS_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3fc00000)|value<<22) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_MEAS_STATUS() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3fc00000) >> 22 +} + +// SENS.SAR_SLAVE_ADDR2: Configure slave addresses 2-3 of RTC I2C +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_SLAVE_ADDR3: Configure slave addresses 4-5 of RTC I2C +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_SLAVE_ADDR4: Configure slave addresses 6-7 of RTC I2C +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_I2C_CTRL: Configure RTC I2C transmission +func (o *SENS_Type) SetSAR_I2C_CTRL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0xfffffff)|value) +} +func (o *SENS_Type) GetSAR_I2C_CTRL() uint32 { + return volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0xfffffff +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x20000000) >> 29 +} + +// SENS.SAR_COCPU_INT_RAW: Interrupt raw bit of ULP-RISCV +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_SW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_SW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x100) >> 8 +} + +// SENS.SAR_COCPU_INT_ENA: Interrupt enable bit of ULP-RISCV +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_SW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_SW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x100) >> 8 +} + +// SENS.SAR_COCPU_INT_ST: Interrupt status bit of ULP-RISCV +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_TSENS_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_TSENS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_SW_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_SW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_COCPU_SWD_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_COCPU_SWD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x100) >> 8 +} + +// SENS.SAR_COCPU_INT_CLR: Interrupt clear bit of ULP-RISCV +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_SW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_SW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x100) >> 8 +} + +// Constants for RTC_IO: Low-power Input/Output +const ( + // RTC_GPIO_OUT: RTC GPIO output register + // Position of GPIO_OUT_DATA field. + RTCIO_RTC_GPIO_OUT_GPIO_OUT_DATA_Pos = 0xa + // Bit mask of GPIO_OUT_DATA field. + RTCIO_RTC_GPIO_OUT_GPIO_OUT_DATA_Msk = 0xfffffc00 + + // RTC_GPIO_OUT_W1TS: RTC GPIO output bit set register + // Position of GPIO_OUT_DATA_W1TS field. + RTCIO_RTC_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS_Pos = 0xa + // Bit mask of GPIO_OUT_DATA_W1TS field. + RTCIO_RTC_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_OUT_W1TC: RTC GPIO output bit clear register + // Position of GPIO_OUT_DATA_W1TC field. + RTCIO_RTC_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC_Pos = 0xa + // Bit mask of GPIO_OUT_DATA_W1TC field. + RTCIO_RTC_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE: RTC GPIO output enable register + // Position of REG_RTCIO_REG_GPIO_ENABLE field. + RTCIO_RTC_GPIO_ENABLE_REG_RTCIO_REG_GPIO_ENABLE_Pos = 0xa + // Bit mask of REG_RTCIO_REG_GPIO_ENABLE field. + RTCIO_RTC_GPIO_ENABLE_REG_RTCIO_REG_GPIO_ENABLE_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE_W1TS: RTC GPIO output enable bit set register + // Position of REG_RTCIO_REG_GPIO_ENABLE_W1TS field. + RTCIO_RTC_GPIO_ENABLE_W1TS_REG_RTCIO_REG_GPIO_ENABLE_W1TS_Pos = 0xa + // Bit mask of REG_RTCIO_REG_GPIO_ENABLE_W1TS field. + RTCIO_RTC_GPIO_ENABLE_W1TS_REG_RTCIO_REG_GPIO_ENABLE_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE_W1TC: RTC GPIO output enable bit clear register + // Position of REG_RTCIO_REG_GPIO_ENABLE_W1TC field. + RTCIO_RTC_GPIO_ENABLE_W1TC_REG_RTCIO_REG_GPIO_ENABLE_W1TC_Pos = 0xa + // Bit mask of REG_RTCIO_REG_GPIO_ENABLE_W1TC field. + RTCIO_RTC_GPIO_ENABLE_W1TC_REG_RTCIO_REG_GPIO_ENABLE_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS: RTC GPIO interrupt status register + // Position of GPIO_STATUS_INT field. + RTCIO_RTC_GPIO_STATUS_GPIO_STATUS_INT_Pos = 0xa + // Bit mask of GPIO_STATUS_INT field. + RTCIO_RTC_GPIO_STATUS_GPIO_STATUS_INT_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS_W1TS: RTC GPIO interrupt status bit set register + // Position of GPIO_STATUS_INT_W1TS field. + RTCIO_RTC_GPIO_STATUS_W1TS_GPIO_STATUS_INT_W1TS_Pos = 0xa + // Bit mask of GPIO_STATUS_INT_W1TS field. + RTCIO_RTC_GPIO_STATUS_W1TS_GPIO_STATUS_INT_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS_W1TC: RTC GPIO interrupt status bit clear register + // Position of GPIO_STATUS_INT_W1TC field. + RTCIO_RTC_GPIO_STATUS_W1TC_GPIO_STATUS_INT_W1TC_Pos = 0xa + // Bit mask of GPIO_STATUS_INT_W1TC field. + RTCIO_RTC_GPIO_STATUS_W1TC_GPIO_STATUS_INT_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_IN: RTC GPIO input register + // Position of GPIO_IN_NEXT field. + RTCIO_RTC_GPIO_IN_GPIO_IN_NEXT_Pos = 0xa + // Bit mask of GPIO_IN_NEXT field. + RTCIO_RTC_GPIO_IN_GPIO_IN_NEXT_Msk = 0xfffffc00 + + // RTC_GPIO_PIN0: RTC configuration for pin %s + // Position of GPIO_PIN_PAD_DRIVER field. + RTCIO_RTC_GPIO_PIN_GPIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN_PAD_DRIVER field. + RTCIO_RTC_GPIO_PIN_GPIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit GPIO_PIN_PAD_DRIVER. + RTCIO_RTC_GPIO_PIN_GPIO_PIN_PAD_DRIVER = 0x4 + // Position of GPIO_PIN_INT_TYPE field. + RTCIO_RTC_GPIO_PIN_GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN_INT_TYPE field. + RTCIO_RTC_GPIO_PIN_GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of GPIO_PIN_WAKEUP_ENABLE field. + RTCIO_RTC_GPIO_PIN_GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN_WAKEUP_ENABLE field. + RTCIO_RTC_GPIO_PIN_GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN_WAKEUP_ENABLE. + RTCIO_RTC_GPIO_PIN_GPIO_PIN_WAKEUP_ENABLE = 0x400 + + // RTC_DEBUG_SEL: RTC debug select register + // Position of RTC_DEBUG_SEL0 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL0_Pos = 0x0 + // Bit mask of RTC_DEBUG_SEL0 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL0_Msk = 0x1f + // Position of RTC_DEBUG_SEL1 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL1_Pos = 0x5 + // Bit mask of RTC_DEBUG_SEL1 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL1_Msk = 0x3e0 + // Position of RTC_DEBUG_SEL2 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL2_Pos = 0xa + // Bit mask of RTC_DEBUG_SEL2 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL2_Msk = 0x7c00 + // Position of RTC_DEBUG_SEL3 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL3_Pos = 0xf + // Bit mask of RTC_DEBUG_SEL3 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL3_Msk = 0xf8000 + // Position of RTC_DEBUG_SEL4 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL4_Pos = 0x14 + // Bit mask of RTC_DEBUG_SEL4 field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_SEL4_Msk = 0x1f00000 + // Position of RTC_DEBUG_12M_NO_GATING field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING_Pos = 0x19 + // Bit mask of RTC_DEBUG_12M_NO_GATING field. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING_Msk = 0x2000000 + // Bit RTC_DEBUG_12M_NO_GATING. + RTCIO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING = 0x2000000 + + // TOUCH_PAD0: Touch pad %s configuration register + // Position of FUN_IE field. + RTCIO_TOUCH_PAD_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTCIO_TOUCH_PAD_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTCIO_TOUCH_PAD_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTCIO_TOUCH_PAD_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTCIO_TOUCH_PAD_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTCIO_TOUCH_PAD_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTCIO_TOUCH_PAD_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTCIO_TOUCH_PAD_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTCIO_TOUCH_PAD_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTCIO_TOUCH_PAD_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTCIO_TOUCH_PAD_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTCIO_TOUCH_PAD_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTCIO_TOUCH_PAD_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTCIO_TOUCH_PAD_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTCIO_TOUCH_PAD_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTCIO_TOUCH_PAD_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTCIO_TOUCH_PAD_MUX_SEL = 0x80000 + // Position of XPD field. + RTCIO_TOUCH_PAD_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTCIO_TOUCH_PAD_XPD_Msk = 0x100000 + // Bit XPD. + RTCIO_TOUCH_PAD_XPD = 0x100000 + // Position of TIE_OPT field. + RTCIO_TOUCH_PAD_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTCIO_TOUCH_PAD_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTCIO_TOUCH_PAD_TIE_OPT = 0x200000 + // Position of START field. + RTCIO_TOUCH_PAD_START_Pos = 0x16 + // Bit mask of START field. + RTCIO_TOUCH_PAD_START_Msk = 0x400000 + // Bit START. + RTCIO_TOUCH_PAD_START = 0x400000 + // Position of DAC field. + RTCIO_TOUCH_PAD_DAC_Pos = 0x17 + // Bit mask of DAC field. + RTCIO_TOUCH_PAD_DAC_Msk = 0x3800000 + // Position of RUE field. + RTCIO_TOUCH_PAD_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTCIO_TOUCH_PAD_RUE_Msk = 0x8000000 + // Bit RUE. + RTCIO_TOUCH_PAD_RUE = 0x8000000 + // Position of RDE field. + RTCIO_TOUCH_PAD_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTCIO_TOUCH_PAD_RDE_Msk = 0x10000000 + // Bit RDE. + RTCIO_TOUCH_PAD_RDE = 0x10000000 + // Position of DRV field. + RTCIO_TOUCH_PAD_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTCIO_TOUCH_PAD_DRV_Msk = 0x60000000 + + // XTAL_32P_PAD: 32KHz crystal P-pad configuration register + // Position of X32P_FUN_IE field. + RTCIO_XTAL_32P_PAD_X32P_FUN_IE_Pos = 0xd + // Bit mask of X32P_FUN_IE field. + RTCIO_XTAL_32P_PAD_X32P_FUN_IE_Msk = 0x2000 + // Bit X32P_FUN_IE. + RTCIO_XTAL_32P_PAD_X32P_FUN_IE = 0x2000 + // Position of X32P_SLP_OE field. + RTCIO_XTAL_32P_PAD_X32P_SLP_OE_Pos = 0xe + // Bit mask of X32P_SLP_OE field. + RTCIO_XTAL_32P_PAD_X32P_SLP_OE_Msk = 0x4000 + // Bit X32P_SLP_OE. + RTCIO_XTAL_32P_PAD_X32P_SLP_OE = 0x4000 + // Position of X32P_SLP_IE field. + RTCIO_XTAL_32P_PAD_X32P_SLP_IE_Pos = 0xf + // Bit mask of X32P_SLP_IE field. + RTCIO_XTAL_32P_PAD_X32P_SLP_IE_Msk = 0x8000 + // Bit X32P_SLP_IE. + RTCIO_XTAL_32P_PAD_X32P_SLP_IE = 0x8000 + // Position of X32P_SLP_SEL field. + RTCIO_XTAL_32P_PAD_X32P_SLP_SEL_Pos = 0x10 + // Bit mask of X32P_SLP_SEL field. + RTCIO_XTAL_32P_PAD_X32P_SLP_SEL_Msk = 0x10000 + // Bit X32P_SLP_SEL. + RTCIO_XTAL_32P_PAD_X32P_SLP_SEL = 0x10000 + // Position of X32P_FUN_SEL field. + RTCIO_XTAL_32P_PAD_X32P_FUN_SEL_Pos = 0x11 + // Bit mask of X32P_FUN_SEL field. + RTCIO_XTAL_32P_PAD_X32P_FUN_SEL_Msk = 0x60000 + // Position of X32P_MUX_SEL field. + RTCIO_XTAL_32P_PAD_X32P_MUX_SEL_Pos = 0x13 + // Bit mask of X32P_MUX_SEL field. + RTCIO_XTAL_32P_PAD_X32P_MUX_SEL_Msk = 0x80000 + // Bit X32P_MUX_SEL. + RTCIO_XTAL_32P_PAD_X32P_MUX_SEL = 0x80000 + // Position of X32P_RUE field. + RTCIO_XTAL_32P_PAD_X32P_RUE_Pos = 0x1b + // Bit mask of X32P_RUE field. + RTCIO_XTAL_32P_PAD_X32P_RUE_Msk = 0x8000000 + // Bit X32P_RUE. + RTCIO_XTAL_32P_PAD_X32P_RUE = 0x8000000 + // Position of X32P_RDE field. + RTCIO_XTAL_32P_PAD_X32P_RDE_Pos = 0x1c + // Bit mask of X32P_RDE field. + RTCIO_XTAL_32P_PAD_X32P_RDE_Msk = 0x10000000 + // Bit X32P_RDE. + RTCIO_XTAL_32P_PAD_X32P_RDE = 0x10000000 + // Position of X32P_DRV field. + RTCIO_XTAL_32P_PAD_X32P_DRV_Pos = 0x1d + // Bit mask of X32P_DRV field. + RTCIO_XTAL_32P_PAD_X32P_DRV_Msk = 0x60000000 + + // XTAL_32N_PAD: 32KHz crystal N-pad configuration register + // Position of X32N_FUN_IE field. + RTCIO_XTAL_32N_PAD_X32N_FUN_IE_Pos = 0xd + // Bit mask of X32N_FUN_IE field. + RTCIO_XTAL_32N_PAD_X32N_FUN_IE_Msk = 0x2000 + // Bit X32N_FUN_IE. + RTCIO_XTAL_32N_PAD_X32N_FUN_IE = 0x2000 + // Position of X32N_SLP_OE field. + RTCIO_XTAL_32N_PAD_X32N_SLP_OE_Pos = 0xe + // Bit mask of X32N_SLP_OE field. + RTCIO_XTAL_32N_PAD_X32N_SLP_OE_Msk = 0x4000 + // Bit X32N_SLP_OE. + RTCIO_XTAL_32N_PAD_X32N_SLP_OE = 0x4000 + // Position of X32N_SLP_IE field. + RTCIO_XTAL_32N_PAD_X32N_SLP_IE_Pos = 0xf + // Bit mask of X32N_SLP_IE field. + RTCIO_XTAL_32N_PAD_X32N_SLP_IE_Msk = 0x8000 + // Bit X32N_SLP_IE. + RTCIO_XTAL_32N_PAD_X32N_SLP_IE = 0x8000 + // Position of X32N_SLP_SEL field. + RTCIO_XTAL_32N_PAD_X32N_SLP_SEL_Pos = 0x10 + // Bit mask of X32N_SLP_SEL field. + RTCIO_XTAL_32N_PAD_X32N_SLP_SEL_Msk = 0x10000 + // Bit X32N_SLP_SEL. + RTCIO_XTAL_32N_PAD_X32N_SLP_SEL = 0x10000 + // Position of X32N_FUN_SEL field. + RTCIO_XTAL_32N_PAD_X32N_FUN_SEL_Pos = 0x11 + // Bit mask of X32N_FUN_SEL field. + RTCIO_XTAL_32N_PAD_X32N_FUN_SEL_Msk = 0x60000 + // Position of X32N_MUX_SEL field. + RTCIO_XTAL_32N_PAD_X32N_MUX_SEL_Pos = 0x13 + // Bit mask of X32N_MUX_SEL field. + RTCIO_XTAL_32N_PAD_X32N_MUX_SEL_Msk = 0x80000 + // Bit X32N_MUX_SEL. + RTCIO_XTAL_32N_PAD_X32N_MUX_SEL = 0x80000 + // Position of X32N_RUE field. + RTCIO_XTAL_32N_PAD_X32N_RUE_Pos = 0x1b + // Bit mask of X32N_RUE field. + RTCIO_XTAL_32N_PAD_X32N_RUE_Msk = 0x8000000 + // Bit X32N_RUE. + RTCIO_XTAL_32N_PAD_X32N_RUE = 0x8000000 + // Position of X32N_RDE field. + RTCIO_XTAL_32N_PAD_X32N_RDE_Pos = 0x1c + // Bit mask of X32N_RDE field. + RTCIO_XTAL_32N_PAD_X32N_RDE_Msk = 0x10000000 + // Bit X32N_RDE. + RTCIO_XTAL_32N_PAD_X32N_RDE = 0x10000000 + // Position of X32N_DRV field. + RTCIO_XTAL_32N_PAD_X32N_DRV_Pos = 0x1d + // Bit mask of X32N_DRV field. + RTCIO_XTAL_32N_PAD_X32N_DRV_Msk = 0x60000000 + + // PAD_DAC1: DAC1 configuration register + // Position of PDAC1_DAC field. + RTCIO_PAD_DAC1_PDAC1_DAC_Pos = 0x3 + // Bit mask of PDAC1_DAC field. + RTCIO_PAD_DAC1_PDAC1_DAC_Msk = 0x7f8 + // Position of PDAC1_XPD_DAC field. + RTCIO_PAD_DAC1_PDAC1_XPD_DAC_Pos = 0xb + // Bit mask of PDAC1_XPD_DAC field. + RTCIO_PAD_DAC1_PDAC1_XPD_DAC_Msk = 0x800 + // Bit PDAC1_XPD_DAC. + RTCIO_PAD_DAC1_PDAC1_XPD_DAC = 0x800 + // Position of PDAC1_DAC_XPD_FORCE field. + RTCIO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Pos = 0xc + // Bit mask of PDAC1_DAC_XPD_FORCE field. + RTCIO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Msk = 0x1000 + // Bit PDAC1_DAC_XPD_FORCE. + RTCIO_PAD_DAC1_PDAC1_DAC_XPD_FORCE = 0x1000 + // Position of PDAC1_FUN_IE field. + RTCIO_PAD_DAC1_PDAC1_FUN_IE_Pos = 0xd + // Bit mask of PDAC1_FUN_IE field. + RTCIO_PAD_DAC1_PDAC1_FUN_IE_Msk = 0x2000 + // Bit PDAC1_FUN_IE. + RTCIO_PAD_DAC1_PDAC1_FUN_IE = 0x2000 + // Position of PDAC1_SLP_OE field. + RTCIO_PAD_DAC1_PDAC1_SLP_OE_Pos = 0xe + // Bit mask of PDAC1_SLP_OE field. + RTCIO_PAD_DAC1_PDAC1_SLP_OE_Msk = 0x4000 + // Bit PDAC1_SLP_OE. + RTCIO_PAD_DAC1_PDAC1_SLP_OE = 0x4000 + // Position of PDAC1_SLP_IE field. + RTCIO_PAD_DAC1_PDAC1_SLP_IE_Pos = 0xf + // Bit mask of PDAC1_SLP_IE field. + RTCIO_PAD_DAC1_PDAC1_SLP_IE_Msk = 0x8000 + // Bit PDAC1_SLP_IE. + RTCIO_PAD_DAC1_PDAC1_SLP_IE = 0x8000 + // Position of PDAC1_SLP_SEL field. + RTCIO_PAD_DAC1_PDAC1_SLP_SEL_Pos = 0x10 + // Bit mask of PDAC1_SLP_SEL field. + RTCIO_PAD_DAC1_PDAC1_SLP_SEL_Msk = 0x10000 + // Bit PDAC1_SLP_SEL. + RTCIO_PAD_DAC1_PDAC1_SLP_SEL = 0x10000 + // Position of PDAC1_FUN_SEL field. + RTCIO_PAD_DAC1_PDAC1_FUN_SEL_Pos = 0x11 + // Bit mask of PDAC1_FUN_SEL field. + RTCIO_PAD_DAC1_PDAC1_FUN_SEL_Msk = 0x60000 + // Position of PDAC1_MUX_SEL field. + RTCIO_PAD_DAC1_PDAC1_MUX_SEL_Pos = 0x13 + // Bit mask of PDAC1_MUX_SEL field. + RTCIO_PAD_DAC1_PDAC1_MUX_SEL_Msk = 0x80000 + // Bit PDAC1_MUX_SEL. + RTCIO_PAD_DAC1_PDAC1_MUX_SEL = 0x80000 + // Position of PDAC1_RUE field. + RTCIO_PAD_DAC1_PDAC1_RUE_Pos = 0x1b + // Bit mask of PDAC1_RUE field. + RTCIO_PAD_DAC1_PDAC1_RUE_Msk = 0x8000000 + // Bit PDAC1_RUE. + RTCIO_PAD_DAC1_PDAC1_RUE = 0x8000000 + // Position of PDAC1_RDE field. + RTCIO_PAD_DAC1_PDAC1_RDE_Pos = 0x1c + // Bit mask of PDAC1_RDE field. + RTCIO_PAD_DAC1_PDAC1_RDE_Msk = 0x10000000 + // Bit PDAC1_RDE. + RTCIO_PAD_DAC1_PDAC1_RDE = 0x10000000 + // Position of PDAC1_DRV field. + RTCIO_PAD_DAC1_PDAC1_DRV_Pos = 0x1d + // Bit mask of PDAC1_DRV field. + RTCIO_PAD_DAC1_PDAC1_DRV_Msk = 0x60000000 + + // PAD_DAC2: DAC2 configuration register + // Position of PDAC2_DAC field. + RTCIO_PAD_DAC2_PDAC2_DAC_Pos = 0x3 + // Bit mask of PDAC2_DAC field. + RTCIO_PAD_DAC2_PDAC2_DAC_Msk = 0x7f8 + // Position of PDAC2_XPD_DAC field. + RTCIO_PAD_DAC2_PDAC2_XPD_DAC_Pos = 0xb + // Bit mask of PDAC2_XPD_DAC field. + RTCIO_PAD_DAC2_PDAC2_XPD_DAC_Msk = 0x800 + // Bit PDAC2_XPD_DAC. + RTCIO_PAD_DAC2_PDAC2_XPD_DAC = 0x800 + // Position of PDAC2_DAC_XPD_FORCE field. + RTCIO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Pos = 0xc + // Bit mask of PDAC2_DAC_XPD_FORCE field. + RTCIO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Msk = 0x1000 + // Bit PDAC2_DAC_XPD_FORCE. + RTCIO_PAD_DAC2_PDAC2_DAC_XPD_FORCE = 0x1000 + // Position of PDAC2_FUN_IE field. + RTCIO_PAD_DAC2_PDAC2_FUN_IE_Pos = 0xd + // Bit mask of PDAC2_FUN_IE field. + RTCIO_PAD_DAC2_PDAC2_FUN_IE_Msk = 0x2000 + // Bit PDAC2_FUN_IE. + RTCIO_PAD_DAC2_PDAC2_FUN_IE = 0x2000 + // Position of PDAC2_SLP_OE field. + RTCIO_PAD_DAC2_PDAC2_SLP_OE_Pos = 0xe + // Bit mask of PDAC2_SLP_OE field. + RTCIO_PAD_DAC2_PDAC2_SLP_OE_Msk = 0x4000 + // Bit PDAC2_SLP_OE. + RTCIO_PAD_DAC2_PDAC2_SLP_OE = 0x4000 + // Position of PDAC2_SLP_IE field. + RTCIO_PAD_DAC2_PDAC2_SLP_IE_Pos = 0xf + // Bit mask of PDAC2_SLP_IE field. + RTCIO_PAD_DAC2_PDAC2_SLP_IE_Msk = 0x8000 + // Bit PDAC2_SLP_IE. + RTCIO_PAD_DAC2_PDAC2_SLP_IE = 0x8000 + // Position of PDAC2_SLP_SEL field. + RTCIO_PAD_DAC2_PDAC2_SLP_SEL_Pos = 0x10 + // Bit mask of PDAC2_SLP_SEL field. + RTCIO_PAD_DAC2_PDAC2_SLP_SEL_Msk = 0x10000 + // Bit PDAC2_SLP_SEL. + RTCIO_PAD_DAC2_PDAC2_SLP_SEL = 0x10000 + // Position of PDAC2_FUN_SEL field. + RTCIO_PAD_DAC2_PDAC2_FUN_SEL_Pos = 0x11 + // Bit mask of PDAC2_FUN_SEL field. + RTCIO_PAD_DAC2_PDAC2_FUN_SEL_Msk = 0x60000 + // Position of PDAC2_MUX_SEL field. + RTCIO_PAD_DAC2_PDAC2_MUX_SEL_Pos = 0x13 + // Bit mask of PDAC2_MUX_SEL field. + RTCIO_PAD_DAC2_PDAC2_MUX_SEL_Msk = 0x80000 + // Bit PDAC2_MUX_SEL. + RTCIO_PAD_DAC2_PDAC2_MUX_SEL = 0x80000 + // Position of PDAC2_RUE field. + RTCIO_PAD_DAC2_PDAC2_RUE_Pos = 0x1b + // Bit mask of PDAC2_RUE field. + RTCIO_PAD_DAC2_PDAC2_RUE_Msk = 0x8000000 + // Bit PDAC2_RUE. + RTCIO_PAD_DAC2_PDAC2_RUE = 0x8000000 + // Position of PDAC2_RDE field. + RTCIO_PAD_DAC2_PDAC2_RDE_Pos = 0x1c + // Bit mask of PDAC2_RDE field. + RTCIO_PAD_DAC2_PDAC2_RDE_Msk = 0x10000000 + // Bit PDAC2_RDE. + RTCIO_PAD_DAC2_PDAC2_RDE = 0x10000000 + // Position of PDAC2_DRV field. + RTCIO_PAD_DAC2_PDAC2_DRV_Pos = 0x1d + // Bit mask of PDAC2_DRV field. + RTCIO_PAD_DAC2_PDAC2_DRV_Msk = 0x60000000 + + // RTC_PAD19: Touch pad 19 configuration register + // Position of FUN_IE field. + RTCIO_RTC_PAD19_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTCIO_RTC_PAD19_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTCIO_RTC_PAD19_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTCIO_RTC_PAD19_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTCIO_RTC_PAD19_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTCIO_RTC_PAD19_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTCIO_RTC_PAD19_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTCIO_RTC_PAD19_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTCIO_RTC_PAD19_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTCIO_RTC_PAD19_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTCIO_RTC_PAD19_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTCIO_RTC_PAD19_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTCIO_RTC_PAD19_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTCIO_RTC_PAD19_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTCIO_RTC_PAD19_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTCIO_RTC_PAD19_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTCIO_RTC_PAD19_MUX_SEL = 0x80000 + // Position of RUE field. + RTCIO_RTC_PAD19_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTCIO_RTC_PAD19_RUE_Msk = 0x8000000 + // Bit RUE. + RTCIO_RTC_PAD19_RUE = 0x8000000 + // Position of RDE field. + RTCIO_RTC_PAD19_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTCIO_RTC_PAD19_RDE_Msk = 0x10000000 + // Bit RDE. + RTCIO_RTC_PAD19_RDE = 0x10000000 + // Position of DRV field. + RTCIO_RTC_PAD19_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTCIO_RTC_PAD19_DRV_Msk = 0x60000000 + + // RTC_PAD20: Touch pad 20 configuration register + // Position of FUN_IE field. + RTCIO_RTC_PAD20_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTCIO_RTC_PAD20_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTCIO_RTC_PAD20_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTCIO_RTC_PAD20_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTCIO_RTC_PAD20_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTCIO_RTC_PAD20_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTCIO_RTC_PAD20_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTCIO_RTC_PAD20_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTCIO_RTC_PAD20_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTCIO_RTC_PAD20_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTCIO_RTC_PAD20_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTCIO_RTC_PAD20_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTCIO_RTC_PAD20_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTCIO_RTC_PAD20_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTCIO_RTC_PAD20_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTCIO_RTC_PAD20_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTCIO_RTC_PAD20_MUX_SEL = 0x80000 + // Position of RUE field. + RTCIO_RTC_PAD20_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTCIO_RTC_PAD20_RUE_Msk = 0x8000000 + // Bit RUE. + RTCIO_RTC_PAD20_RUE = 0x8000000 + // Position of RDE field. + RTCIO_RTC_PAD20_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTCIO_RTC_PAD20_RDE_Msk = 0x10000000 + // Bit RDE. + RTCIO_RTC_PAD20_RDE = 0x10000000 + // Position of DRV field. + RTCIO_RTC_PAD20_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTCIO_RTC_PAD20_DRV_Msk = 0x60000000 + + // RTC_PAD21: Touch pad 21 configuration register + // Position of FUN_IE field. + RTCIO_RTC_PAD21_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTCIO_RTC_PAD21_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTCIO_RTC_PAD21_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTCIO_RTC_PAD21_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTCIO_RTC_PAD21_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTCIO_RTC_PAD21_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTCIO_RTC_PAD21_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTCIO_RTC_PAD21_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTCIO_RTC_PAD21_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTCIO_RTC_PAD21_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTCIO_RTC_PAD21_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTCIO_RTC_PAD21_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTCIO_RTC_PAD21_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTCIO_RTC_PAD21_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTCIO_RTC_PAD21_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTCIO_RTC_PAD21_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTCIO_RTC_PAD21_MUX_SEL = 0x80000 + // Position of RUE field. + RTCIO_RTC_PAD21_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTCIO_RTC_PAD21_RUE_Msk = 0x8000000 + // Bit RUE. + RTCIO_RTC_PAD21_RUE = 0x8000000 + // Position of RDE field. + RTCIO_RTC_PAD21_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTCIO_RTC_PAD21_RDE_Msk = 0x10000000 + // Bit RDE. + RTCIO_RTC_PAD21_RDE = 0x10000000 + // Position of DRV field. + RTCIO_RTC_PAD21_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTCIO_RTC_PAD21_DRV_Msk = 0x60000000 + + // EXT_WAKEUP0: External wake up configuration register + // Position of SEL field. + RTCIO_EXT_WAKEUP0_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTCIO_EXT_WAKEUP0_SEL_Msk = 0xf8000000 + + // XTL_EXT_CTR: Crystal power down enable GPIO source + // Position of SEL field. + RTCIO_XTL_EXT_CTR_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTCIO_XTL_EXT_CTR_SEL_Msk = 0xf8000000 + + // SAR_I2C_IO: RTC I2C pad selection + // Position of SAR_DEBUG_BIT_SEL field. + RTCIO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Pos = 0x17 + // Bit mask of SAR_DEBUG_BIT_SEL field. + RTCIO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Msk = 0xf800000 + // Position of SAR_I2C_SCL_SEL field. + RTCIO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Pos = 0x1c + // Bit mask of SAR_I2C_SCL_SEL field. + RTCIO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Msk = 0x30000000 + // Position of SAR_I2C_SDA_SEL field. + RTCIO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Pos = 0x1e + // Bit mask of SAR_I2C_SDA_SEL field. + RTCIO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Msk = 0xc0000000 + + // RTC_IO_TOUCH_CTRL: Touch control register + // Position of IO_TOUCH_BUFSEL field. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL_Pos = 0x0 + // Bit mask of IO_TOUCH_BUFSEL field. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL_Msk = 0xf + // Position of IO_TOUCH_BUFMODE field. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE_Pos = 0x4 + // Bit mask of IO_TOUCH_BUFMODE field. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE_Msk = 0x10 + // Bit IO_TOUCH_BUFMODE. + RTCIO_RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE = 0x10 + + // RTC_IO_DATE: Version control register + // Position of IO_DATE field. + RTCIO_RTC_IO_DATE_IO_DATE_Pos = 0x0 + // Bit mask of IO_DATE field. + RTCIO_RTC_IO_DATE_IO_DATE_Msk = 0xfffffff +) + +// Constants for RTC_CNTL: Real-Time Clock Control +const ( + // ULP_CP_TIMER: Configure coprocessor timer + // Position of ULP_CP_PC_INIT field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_PC_INIT_Pos = 0x0 + // Bit mask of ULP_CP_PC_INIT field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_PC_INIT_Msk = 0x7ff + // Position of ULP_CP_GPIO_WAKEUP_ENA field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA_Pos = 0x1d + // Bit mask of ULP_CP_GPIO_WAKEUP_ENA field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA_Msk = 0x20000000 + // Bit ULP_CP_GPIO_WAKEUP_ENA. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA = 0x20000000 + // Position of ULP_CP_GPIO_WAKEUP_CLR field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR_Pos = 0x1e + // Bit mask of ULP_CP_GPIO_WAKEUP_CLR field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR_Msk = 0x40000000 + // Bit ULP_CP_GPIO_WAKEUP_CLR. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR = 0x40000000 + // Position of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN_Pos = 0x1f + // Bit mask of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN_Msk = 0x80000000 + // Bit ULP_CP_SLP_TIMER_EN. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN = 0x80000000 + + // ULP_CP_CTRL: ULP-FSM configuration register + // Position of ULP_CP_MEM_ADDR_INIT field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT_Pos = 0x0 + // Bit mask of ULP_CP_MEM_ADDR_INIT field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT_Msk = 0x7ff + // Position of ULP_CP_MEM_ADDR_SIZE field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE_Pos = 0xb + // Bit mask of ULP_CP_MEM_ADDR_SIZE field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE_Msk = 0x3ff800 + // Position of ULP_CP_MEM_OFFSET_CLR field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR_Pos = 0x16 + // Bit mask of ULP_CP_MEM_OFFSET_CLR field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR_Msk = 0x400000 + // Bit ULP_CP_MEM_OFFSET_CLR. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_OFFSET_CLR = 0x400000 + // Position of ULP_CP_CLK_FO field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_CLK_FO_Pos = 0x1c + // Bit mask of ULP_CP_CLK_FO field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_CLK_FO_Msk = 0x10000000 + // Bit ULP_CP_CLK_FO. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_CLK_FO = 0x10000000 + // Position of ULP_CP_RESET field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_RESET_Pos = 0x1d + // Bit mask of ULP_CP_RESET field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_RESET_Msk = 0x20000000 + // Bit ULP_CP_RESET. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_RESET = 0x20000000 + // Position of ULP_CP_FORCE_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP_Pos = 0x1e + // Bit mask of ULP_CP_FORCE_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP_Msk = 0x40000000 + // Bit ULP_CP_FORCE_START_TOP. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP = 0x40000000 + // Position of ULP_CP_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_START_TOP_Pos = 0x1f + // Bit mask of ULP_CP_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_START_TOP_Msk = 0x80000000 + // Bit ULP_CP_START_TOP. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_START_TOP = 0x80000000 + + // COCPU_CTRL: ULP-RISCV configuration register + // Position of COCPU_CLK_FO field. + RTC_CNTL_COCPU_CTRL_COCPU_CLK_FO_Pos = 0x0 + // Bit mask of COCPU_CLK_FO field. + RTC_CNTL_COCPU_CTRL_COCPU_CLK_FO_Msk = 0x1 + // Bit COCPU_CLK_FO. + RTC_CNTL_COCPU_CTRL_COCPU_CLK_FO = 0x1 + // Position of COCPU_START_2_RESET_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_RESET_DIS_Pos = 0x1 + // Bit mask of COCPU_START_2_RESET_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_RESET_DIS_Msk = 0x7e + // Position of COCPU_START_2_INTR_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_INTR_EN_Pos = 0x7 + // Bit mask of COCPU_START_2_INTR_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_INTR_EN_Msk = 0x1f80 + // Position of COCPU_SHUT field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_Pos = 0xd + // Bit mask of COCPU_SHUT field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_Msk = 0x2000 + // Bit COCPU_SHUT. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT = 0x2000 + // Position of COCPU_SHUT_2_CLK_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS_Pos = 0xe + // Bit mask of COCPU_SHUT_2_CLK_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS_Msk = 0x3fc000 + // Position of COCPU_SHUT_RESET_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_RESET_EN_Pos = 0x16 + // Bit mask of COCPU_SHUT_RESET_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_RESET_EN_Msk = 0x400000 + // Bit COCPU_SHUT_RESET_EN. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_RESET_EN = 0x400000 + // Position of COCPU_SEL field. + RTC_CNTL_COCPU_CTRL_COCPU_SEL_Pos = 0x17 + // Bit mask of COCPU_SEL field. + RTC_CNTL_COCPU_CTRL_COCPU_SEL_Msk = 0x800000 + // Bit COCPU_SEL. + RTC_CNTL_COCPU_CTRL_COCPU_SEL = 0x800000 + // Position of COCPU_DONE_FORCE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_FORCE_Pos = 0x18 + // Bit mask of COCPU_DONE_FORCE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_FORCE_Msk = 0x1000000 + // Bit COCPU_DONE_FORCE. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_FORCE = 0x1000000 + // Position of COCPU_DONE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_Pos = 0x19 + // Bit mask of COCPU_DONE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_Msk = 0x2000000 + // Bit COCPU_DONE. + RTC_CNTL_COCPU_CTRL_COCPU_DONE = 0x2000000 + // Position of COCPU_SW_INT_TRIGGER field. + RTC_CNTL_COCPU_CTRL_COCPU_SW_INT_TRIGGER_Pos = 0x1a + // Bit mask of COCPU_SW_INT_TRIGGER field. + RTC_CNTL_COCPU_CTRL_COCPU_SW_INT_TRIGGER_Msk = 0x4000000 + // Bit COCPU_SW_INT_TRIGGER. + RTC_CNTL_COCPU_CTRL_COCPU_SW_INT_TRIGGER = 0x4000000 + + // ULP_CP_TIMER_1: Configure sleep cycle of the timer + // Position of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Pos = 0x8 + // Bit mask of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Msk = 0xffffff00 +) + +// Constants for RTC_I2C: Low-power I2C (Inter-Integrated Circuit) Controller +const ( + // SCL_LOW: Configure the low level width of SCL + // Position of PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_Msk = 0xfffff + + // CTRL: Transmission setting + // Position of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + RTC_I2C_CTRL_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + RTC_I2C_CTRL_SCL_FORCE_OUT = 0x2 + // Position of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Pos = 0x2 + // Bit mask of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Msk = 0x4 + // Bit MS_MODE. + RTC_I2C_CTRL_MS_MODE = 0x4 + // Position of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Pos = 0x3 + // Bit mask of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Msk = 0x8 + // Bit TRANS_START. + RTC_I2C_CTRL_TRANS_START = 0x8 + // Position of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Pos = 0x4 + // Bit mask of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Msk = 0x10 + // Bit TX_LSB_FIRST. + RTC_I2C_CTRL_TX_LSB_FIRST = 0x10 + // Position of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Pos = 0x5 + // Bit mask of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Msk = 0x20 + // Bit RX_LSB_FIRST. + RTC_I2C_CTRL_RX_LSB_FIRST = 0x20 + // Position of CLK_GATE_EN field. + RTC_I2C_CTRL_CLK_GATE_EN_Pos = 0x1d + // Bit mask of CLK_GATE_EN field. + RTC_I2C_CTRL_CLK_GATE_EN_Msk = 0x20000000 + // Bit CLK_GATE_EN. + RTC_I2C_CTRL_CLK_GATE_EN = 0x20000000 + // Position of RESET field. + RTC_I2C_CTRL_RESET_Pos = 0x1e + // Bit mask of RESET field. + RTC_I2C_CTRL_RESET_Msk = 0x40000000 + // Bit RESET. + RTC_I2C_CTRL_RESET = 0x40000000 + // Position of CLK_EN field. + RTC_I2C_CTRL_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + RTC_I2C_CTRL_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + RTC_I2C_CTRL_CLK_EN = 0x80000000 + + // STATUS: RTC I2C status + // Position of ACK_REC field. + RTC_I2C_STATUS_ACK_REC_Pos = 0x0 + // Bit mask of ACK_REC field. + RTC_I2C_STATUS_ACK_REC_Msk = 0x1 + // Bit ACK_REC. + RTC_I2C_STATUS_ACK_REC = 0x1 + // Position of SLAVE_RW field. + RTC_I2C_STATUS_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + RTC_I2C_STATUS_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + RTC_I2C_STATUS_SLAVE_RW = 0x2 + // Position of ARB_LOST field. + RTC_I2C_STATUS_ARB_LOST_Pos = 0x2 + // Bit mask of ARB_LOST field. + RTC_I2C_STATUS_ARB_LOST_Msk = 0x4 + // Bit ARB_LOST. + RTC_I2C_STATUS_ARB_LOST = 0x4 + // Position of BUS_BUSY field. + RTC_I2C_STATUS_BUS_BUSY_Pos = 0x3 + // Bit mask of BUS_BUSY field. + RTC_I2C_STATUS_BUS_BUSY_Msk = 0x8 + // Bit BUS_BUSY. + RTC_I2C_STATUS_BUS_BUSY = 0x8 + // Position of SLAVE_ADDRESSED field. + RTC_I2C_STATUS_SLAVE_ADDRESSED_Pos = 0x4 + // Bit mask of SLAVE_ADDRESSED field. + RTC_I2C_STATUS_SLAVE_ADDRESSED_Msk = 0x10 + // Bit SLAVE_ADDRESSED. + RTC_I2C_STATUS_SLAVE_ADDRESSED = 0x10 + // Position of BYTE_TRANS field. + RTC_I2C_STATUS_BYTE_TRANS_Pos = 0x5 + // Bit mask of BYTE_TRANS field. + RTC_I2C_STATUS_BYTE_TRANS_Msk = 0x20 + // Bit BYTE_TRANS. + RTC_I2C_STATUS_BYTE_TRANS = 0x20 + // Position of OP_CNT field. + RTC_I2C_STATUS_OP_CNT_Pos = 0x6 + // Bit mask of OP_CNT field. + RTC_I2C_STATUS_OP_CNT_Msk = 0xc0 + // Position of SHIFT field. + RTC_I2C_STATUS_SHIFT_Pos = 0x10 + // Bit mask of SHIFT field. + RTC_I2C_STATUS_SHIFT_Msk = 0xff0000 + // Position of SCL_MAIN_STATE_LAST field. + RTC_I2C_STATUS_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + RTC_I2C_STATUS_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + RTC_I2C_STATUS_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + RTC_I2C_STATUS_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: Configure RTC I2C timeout + // Position of TIME_OUT field. + RTC_I2C_TO_TIME_OUT_Pos = 0x0 + // Bit mask of TIME_OUT field. + RTC_I2C_TO_TIME_OUT_Msk = 0xfffff + + // SLAVE_ADDR: Configure slave address + // Position of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // SCL_HIGH: Configure the high level width of SCL + // Position of PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_Msk = 0xfffff + + // SDA_DUTY: Configure the SDA hold time after a negative SCL edge + // Position of NUM field. + RTC_I2C_SDA_DUTY_NUM_Pos = 0x0 + // Bit mask of NUM field. + RTC_I2C_SDA_DUTY_NUM_Msk = 0xfffff + + // SCL_START_PERIOD: Configure the delay between the SDA and SCL negative edge for a start condition + // Position of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Pos = 0x0 + // Bit mask of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Msk = 0xfffff + + // SCL_STOP_PERIOD: Configure the delay between SDA and SCL positive edge for a stop condition + // Position of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Pos = 0x0 + // Bit mask of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Msk = 0xfffff + + // INT_CLR: Clear RTC I2C interrupt + // Position of SLAVE_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_CLR. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR = 0x1 + // Position of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_CLR. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x2 + // Position of MASTER_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_CLR. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR = 0x4 + // Position of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_CLR. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x8 + // Position of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x4 + // Bit mask of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x10 + // Bit TIME_OUT_INT_CLR. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR = 0x10 + // Position of ACK_ERR_INT_CLR field. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR_Pos = 0x5 + // Bit mask of ACK_ERR_INT_CLR field. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR_Msk = 0x20 + // Bit ACK_ERR_INT_CLR. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR = 0x20 + // Position of RX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR_Pos = 0x6 + // Bit mask of RX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR_Msk = 0x40 + // Bit RX_DATA_INT_CLR. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR = 0x40 + // Position of TX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR_Pos = 0x7 + // Bit mask of TX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR_Msk = 0x80 + // Bit TX_DATA_INT_CLR. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR = 0x80 + // Position of DETECT_START_INT_CLR field. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR_Pos = 0x8 + // Bit mask of DETECT_START_INT_CLR field. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR_Msk = 0x100 + // Bit DETECT_START_INT_CLR. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR = 0x100 + + // INT_RAW: RTC I2C raw interrupt + // Position of SLAVE_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_RAW. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW = 0x1 + // Position of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_RAW. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x2 + // Position of MASTER_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_RAW. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW = 0x4 + // Position of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_RAW. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x8 + // Position of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x4 + // Bit mask of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x10 + // Bit TIME_OUT_INT_RAW. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW = 0x10 + // Position of ACK_ERR_INT_RAW field. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW_Pos = 0x5 + // Bit mask of ACK_ERR_INT_RAW field. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW_Msk = 0x20 + // Bit ACK_ERR_INT_RAW. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW = 0x20 + // Position of RX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW_Pos = 0x6 + // Bit mask of RX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW_Msk = 0x40 + // Bit RX_DATA_INT_RAW. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW = 0x40 + // Position of TX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW_Pos = 0x7 + // Bit mask of TX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW_Msk = 0x80 + // Bit TX_DATA_INT_RAW. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW = 0x80 + // Position of DETECT_START_INT_RAW field. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW_Pos = 0x8 + // Bit mask of DETECT_START_INT_RAW field. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW_Msk = 0x100 + // Bit DETECT_START_INT_RAW. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW = 0x100 + + // INT_ST: RTC I2C interrupt status + // Position of SLAVE_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_ST. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST = 0x1 + // Position of ARBITRATION_LOST_INT_ST field. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_ST field. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_ST. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST = 0x2 + // Position of MASTER_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_ST. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST = 0x4 + // Position of TRANS_COMPLETE_INT_ST field. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_ST field. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_ST. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST = 0x8 + // Position of TIME_OUT_INT_ST field. + RTC_I2C_INT_ST_TIME_OUT_INT_ST_Pos = 0x4 + // Bit mask of TIME_OUT_INT_ST field. + RTC_I2C_INT_ST_TIME_OUT_INT_ST_Msk = 0x10 + // Bit TIME_OUT_INT_ST. + RTC_I2C_INT_ST_TIME_OUT_INT_ST = 0x10 + // Position of ACK_ERR_INT_ST field. + RTC_I2C_INT_ST_ACK_ERR_INT_ST_Pos = 0x5 + // Bit mask of ACK_ERR_INT_ST field. + RTC_I2C_INT_ST_ACK_ERR_INT_ST_Msk = 0x20 + // Bit ACK_ERR_INT_ST. + RTC_I2C_INT_ST_ACK_ERR_INT_ST = 0x20 + // Position of RX_DATA_INT_ST field. + RTC_I2C_INT_ST_RX_DATA_INT_ST_Pos = 0x6 + // Bit mask of RX_DATA_INT_ST field. + RTC_I2C_INT_ST_RX_DATA_INT_ST_Msk = 0x40 + // Bit RX_DATA_INT_ST. + RTC_I2C_INT_ST_RX_DATA_INT_ST = 0x40 + // Position of TX_DATA_INT_ST field. + RTC_I2C_INT_ST_TX_DATA_INT_ST_Pos = 0x7 + // Bit mask of TX_DATA_INT_ST field. + RTC_I2C_INT_ST_TX_DATA_INT_ST_Msk = 0x80 + // Bit TX_DATA_INT_ST. + RTC_I2C_INT_ST_TX_DATA_INT_ST = 0x80 + // Position of DETECT_START_INT_ST field. + RTC_I2C_INT_ST_DETECT_START_INT_ST_Pos = 0x8 + // Bit mask of DETECT_START_INT_ST field. + RTC_I2C_INT_ST_DETECT_START_INT_ST_Msk = 0x100 + // Bit DETECT_START_INT_ST. + RTC_I2C_INT_ST_DETECT_START_INT_ST = 0x100 + + // INT_ENA: Enable RTC I2C interrupt + // Position of SLAVE_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_ENA. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA = 0x1 + // Position of ARBITRATION_LOST_INT_ENA field. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_ENA. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x2 + // Position of MASTER_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_ENA. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA = 0x4 + // Position of TRANS_COMPLETE_INT_ENA field. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_ENA. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x8 + // Position of TIME_OUT_INT_ENA field. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x4 + // Bit mask of TIME_OUT_INT_ENA field. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x10 + // Bit TIME_OUT_INT_ENA. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA = 0x10 + // Position of ACK_ERR_INT_ENA field. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA_Pos = 0x5 + // Bit mask of ACK_ERR_INT_ENA field. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA_Msk = 0x20 + // Bit ACK_ERR_INT_ENA. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA = 0x20 + // Position of RX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA_Pos = 0x6 + // Bit mask of RX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA_Msk = 0x40 + // Bit RX_DATA_INT_ENA. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA = 0x40 + // Position of TX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA_Pos = 0x7 + // Bit mask of TX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA_Msk = 0x80 + // Bit TX_DATA_INT_ENA. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA = 0x80 + // Position of DETECT_START_INT_ENA field. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA_Pos = 0x8 + // Bit mask of DETECT_START_INT_ENA field. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA_Msk = 0x100 + // Bit DETECT_START_INT_ENA. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA = 0x100 + + // DATA: RTC I2C read data + // Position of RDATA field. + RTC_I2C_DATA_RDATA_Pos = 0x0 + // Bit mask of RDATA field. + RTC_I2C_DATA_RDATA_Msk = 0xff + // Position of SLAVE_TX_DATA field. + RTC_I2C_DATA_SLAVE_TX_DATA_Pos = 0x8 + // Bit mask of SLAVE_TX_DATA field. + RTC_I2C_DATA_SLAVE_TX_DATA_Msk = 0xff00 + // Position of DONE field. + RTC_I2C_DATA_DONE_Pos = 0x1f + // Bit mask of DONE field. + RTC_I2C_DATA_DONE_Msk = 0x80000000 + // Bit DONE. + RTC_I2C_DATA_DONE = 0x80000000 + + // CMD0: RTC I2C Command 0 + // Position of COMMAND0 field. + RTC_I2C_CMD0_COMMAND0_Pos = 0x0 + // Bit mask of COMMAND0 field. + RTC_I2C_CMD0_COMMAND0_Msk = 0x3fff + // Position of COMMAND0_DONE field. + RTC_I2C_CMD0_COMMAND0_DONE_Pos = 0x1f + // Bit mask of COMMAND0_DONE field. + RTC_I2C_CMD0_COMMAND0_DONE_Msk = 0x80000000 + // Bit COMMAND0_DONE. + RTC_I2C_CMD0_COMMAND0_DONE = 0x80000000 + + // CMD1: RTC I2C Command 1 + // Position of COMMAND1 field. + RTC_I2C_CMD1_COMMAND1_Pos = 0x0 + // Bit mask of COMMAND1 field. + RTC_I2C_CMD1_COMMAND1_Msk = 0x3fff + // Position of COMMAND1_DONE field. + RTC_I2C_CMD1_COMMAND1_DONE_Pos = 0x1f + // Bit mask of COMMAND1_DONE field. + RTC_I2C_CMD1_COMMAND1_DONE_Msk = 0x80000000 + // Bit COMMAND1_DONE. + RTC_I2C_CMD1_COMMAND1_DONE = 0x80000000 + + // CMD2: RTC I2C Command 2 + // Position of COMMAND2 field. + RTC_I2C_CMD2_COMMAND2_Pos = 0x0 + // Bit mask of COMMAND2 field. + RTC_I2C_CMD2_COMMAND2_Msk = 0x3fff + // Position of COMMAND2_DONE field. + RTC_I2C_CMD2_COMMAND2_DONE_Pos = 0x1f + // Bit mask of COMMAND2_DONE field. + RTC_I2C_CMD2_COMMAND2_DONE_Msk = 0x80000000 + // Bit COMMAND2_DONE. + RTC_I2C_CMD2_COMMAND2_DONE = 0x80000000 + + // CMD3: RTC I2C Command 3 + // Position of COMMAND3 field. + RTC_I2C_CMD3_COMMAND3_Pos = 0x0 + // Bit mask of COMMAND3 field. + RTC_I2C_CMD3_COMMAND3_Msk = 0x3fff + // Position of COMMAND3_DONE field. + RTC_I2C_CMD3_COMMAND3_DONE_Pos = 0x1f + // Bit mask of COMMAND3_DONE field. + RTC_I2C_CMD3_COMMAND3_DONE_Msk = 0x80000000 + // Bit COMMAND3_DONE. + RTC_I2C_CMD3_COMMAND3_DONE = 0x80000000 + + // CMD4: RTC I2C Command 4 + // Position of COMMAND4 field. + RTC_I2C_CMD4_COMMAND4_Pos = 0x0 + // Bit mask of COMMAND4 field. + RTC_I2C_CMD4_COMMAND4_Msk = 0x3fff + // Position of COMMAND4_DONE field. + RTC_I2C_CMD4_COMMAND4_DONE_Pos = 0x1f + // Bit mask of COMMAND4_DONE field. + RTC_I2C_CMD4_COMMAND4_DONE_Msk = 0x80000000 + // Bit COMMAND4_DONE. + RTC_I2C_CMD4_COMMAND4_DONE = 0x80000000 + + // CMD5: RTC I2C Command 5 + // Position of COMMAND5 field. + RTC_I2C_CMD5_COMMAND5_Pos = 0x0 + // Bit mask of COMMAND5 field. + RTC_I2C_CMD5_COMMAND5_Msk = 0x3fff + // Position of COMMAND5_DONE field. + RTC_I2C_CMD5_COMMAND5_DONE_Pos = 0x1f + // Bit mask of COMMAND5_DONE field. + RTC_I2C_CMD5_COMMAND5_DONE_Msk = 0x80000000 + // Bit COMMAND5_DONE. + RTC_I2C_CMD5_COMMAND5_DONE = 0x80000000 + + // CMD6: RTC I2C Command 6 + // Position of COMMAND6 field. + RTC_I2C_CMD6_COMMAND6_Pos = 0x0 + // Bit mask of COMMAND6 field. + RTC_I2C_CMD6_COMMAND6_Msk = 0x3fff + // Position of COMMAND6_DONE field. + RTC_I2C_CMD6_COMMAND6_DONE_Pos = 0x1f + // Bit mask of COMMAND6_DONE field. + RTC_I2C_CMD6_COMMAND6_DONE_Msk = 0x80000000 + // Bit COMMAND6_DONE. + RTC_I2C_CMD6_COMMAND6_DONE = 0x80000000 + + // CMD7: RTC I2C Command 7 + // Position of COMMAND7 field. + RTC_I2C_CMD7_COMMAND7_Pos = 0x0 + // Bit mask of COMMAND7 field. + RTC_I2C_CMD7_COMMAND7_Msk = 0x3fff + // Position of COMMAND7_DONE field. + RTC_I2C_CMD7_COMMAND7_DONE_Pos = 0x1f + // Bit mask of COMMAND7_DONE field. + RTC_I2C_CMD7_COMMAND7_DONE_Msk = 0x80000000 + // Bit COMMAND7_DONE. + RTC_I2C_CMD7_COMMAND7_DONE = 0x80000000 + + // CMD8: RTC I2C Command 8 + // Position of COMMAND8 field. + RTC_I2C_CMD8_COMMAND8_Pos = 0x0 + // Bit mask of COMMAND8 field. + RTC_I2C_CMD8_COMMAND8_Msk = 0x3fff + // Position of COMMAND8_DONE field. + RTC_I2C_CMD8_COMMAND8_DONE_Pos = 0x1f + // Bit mask of COMMAND8_DONE field. + RTC_I2C_CMD8_COMMAND8_DONE_Msk = 0x80000000 + // Bit COMMAND8_DONE. + RTC_I2C_CMD8_COMMAND8_DONE = 0x80000000 + + // CMD9: RTC I2C Command 9 + // Position of COMMAND9 field. + RTC_I2C_CMD9_COMMAND9_Pos = 0x0 + // Bit mask of COMMAND9 field. + RTC_I2C_CMD9_COMMAND9_Msk = 0x3fff + // Position of COMMAND9_DONE field. + RTC_I2C_CMD9_COMMAND9_DONE_Pos = 0x1f + // Bit mask of COMMAND9_DONE field. + RTC_I2C_CMD9_COMMAND9_DONE_Msk = 0x80000000 + // Bit COMMAND9_DONE. + RTC_I2C_CMD9_COMMAND9_DONE = 0x80000000 + + // CMD10: RTC I2C Command 10 + // Position of COMMAND10 field. + RTC_I2C_CMD10_COMMAND10_Pos = 0x0 + // Bit mask of COMMAND10 field. + RTC_I2C_CMD10_COMMAND10_Msk = 0x3fff + // Position of COMMAND10_DONE field. + RTC_I2C_CMD10_COMMAND10_DONE_Pos = 0x1f + // Bit mask of COMMAND10_DONE field. + RTC_I2C_CMD10_COMMAND10_DONE_Msk = 0x80000000 + // Bit COMMAND10_DONE. + RTC_I2C_CMD10_COMMAND10_DONE = 0x80000000 + + // CMD11: RTC I2C Command 11 + // Position of COMMAND11 field. + RTC_I2C_CMD11_COMMAND11_Pos = 0x0 + // Bit mask of COMMAND11 field. + RTC_I2C_CMD11_COMMAND11_Msk = 0x3fff + // Position of COMMAND11_DONE field. + RTC_I2C_CMD11_COMMAND11_DONE_Pos = 0x1f + // Bit mask of COMMAND11_DONE field. + RTC_I2C_CMD11_COMMAND11_DONE_Msk = 0x80000000 + // Bit COMMAND11_DONE. + RTC_I2C_CMD11_COMMAND11_DONE = 0x80000000 + + // CMD12: RTC I2C Command 12 + // Position of COMMAND12 field. + RTC_I2C_CMD12_COMMAND12_Pos = 0x0 + // Bit mask of COMMAND12 field. + RTC_I2C_CMD12_COMMAND12_Msk = 0x3fff + // Position of COMMAND12_DONE field. + RTC_I2C_CMD12_COMMAND12_DONE_Pos = 0x1f + // Bit mask of COMMAND12_DONE field. + RTC_I2C_CMD12_COMMAND12_DONE_Msk = 0x80000000 + // Bit COMMAND12_DONE. + RTC_I2C_CMD12_COMMAND12_DONE = 0x80000000 + + // CMD13: RTC I2C Command 13 + // Position of COMMAND13 field. + RTC_I2C_CMD13_COMMAND13_Pos = 0x0 + // Bit mask of COMMAND13 field. + RTC_I2C_CMD13_COMMAND13_Msk = 0x3fff + // Position of COMMAND13_DONE field. + RTC_I2C_CMD13_COMMAND13_DONE_Pos = 0x1f + // Bit mask of COMMAND13_DONE field. + RTC_I2C_CMD13_COMMAND13_DONE_Msk = 0x80000000 + // Bit COMMAND13_DONE. + RTC_I2C_CMD13_COMMAND13_DONE = 0x80000000 + + // CMD14: RTC I2C Command 14 + // Position of COMMAND14 field. + RTC_I2C_CMD14_COMMAND14_Pos = 0x0 + // Bit mask of COMMAND14 field. + RTC_I2C_CMD14_COMMAND14_Msk = 0x3fff + // Position of COMMAND14_DONE field. + RTC_I2C_CMD14_COMMAND14_DONE_Pos = 0x1f + // Bit mask of COMMAND14_DONE field. + RTC_I2C_CMD14_COMMAND14_DONE_Msk = 0x80000000 + // Bit COMMAND14_DONE. + RTC_I2C_CMD14_COMMAND14_DONE = 0x80000000 + + // CMD15: RTC I2C Command 15 + // Position of COMMAND15 field. + RTC_I2C_CMD15_COMMAND15_Pos = 0x0 + // Bit mask of COMMAND15 field. + RTC_I2C_CMD15_COMMAND15_Msk = 0x3fff + // Position of COMMAND15_DONE field. + RTC_I2C_CMD15_COMMAND15_DONE_Pos = 0x1f + // Bit mask of COMMAND15_DONE field. + RTC_I2C_CMD15_COMMAND15_DONE_Msk = 0x80000000 + // Bit COMMAND15_DONE. + RTC_I2C_CMD15_COMMAND15_DONE = 0x80000000 + + // DATE: Version control register + // Position of DATE field. + RTC_I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RTC_I2C_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SENS: SENS Peripheral +const ( + // SAR_SLAVE_ADDR1: Configure slave addresses 0-1 of RTC I2C + // Position of I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR1_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_I2C_SLAVE_ADDR0_Msk = 0x3ff800 + // Position of MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_MEAS_STATUS_Pos = 0x16 + // Bit mask of MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_MEAS_STATUS_Msk = 0x3fc00000 + + // SAR_SLAVE_ADDR2: Configure slave addresses 2-3 of RTC I2C + // Position of I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR3_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_I2C_SLAVE_ADDR2_Msk = 0x3ff800 + + // SAR_SLAVE_ADDR3: Configure slave addresses 4-5 of RTC I2C + // Position of I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR5_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_I2C_SLAVE_ADDR4_Msk = 0x3ff800 + + // SAR_SLAVE_ADDR4: Configure slave addresses 6-7 of RTC I2C + // Position of I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7_Pos = 0x0 + // Bit mask of I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR7_Msk = 0x7ff + // Position of I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6_Pos = 0xb + // Bit mask of I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_I2C_SLAVE_ADDR6_Msk = 0x3ff800 + + // SAR_I2C_CTRL: Configure RTC I2C transmission + // Position of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Pos = 0x0 + // Bit mask of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Msk = 0xfffffff + // Position of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Pos = 0x1c + // Bit mask of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Msk = 0x10000000 + // Bit SAR_I2C_START. + SENS_SAR_I2C_CTRL_SAR_I2C_START = 0x10000000 + // Position of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Pos = 0x1d + // Bit mask of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Msk = 0x20000000 + // Bit SAR_I2C_START_FORCE. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE = 0x20000000 + + // SAR_COCPU_INT_RAW: Interrupt raw bit of ULP-RISCV + // Position of COCPU_TOUCH_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW_Pos = 0x0 + // Bit mask of COCPU_TOUCH_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW_Msk = 0x1 + // Bit COCPU_TOUCH_DONE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_DONE_INT_RAW = 0x1 + // Position of COCPU_TOUCH_INACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW_Pos = 0x1 + // Bit mask of COCPU_TOUCH_INACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW_Msk = 0x2 + // Bit COCPU_TOUCH_INACTIVE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_INACTIVE_INT_RAW = 0x2 + // Position of COCPU_TOUCH_ACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW_Pos = 0x2 + // Bit mask of COCPU_TOUCH_ACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW_Msk = 0x4 + // Bit COCPU_TOUCH_ACTIVE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_TOUCH_ACTIVE_INT_RAW = 0x4 + // Position of COCPU_SARADC1_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW_Pos = 0x3 + // Bit mask of COCPU_SARADC1_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW_Msk = 0x8 + // Bit COCPU_SARADC1_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW = 0x8 + // Position of COCPU_SARADC2_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW_Pos = 0x4 + // Bit mask of COCPU_SARADC2_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW_Msk = 0x10 + // Bit COCPU_SARADC2_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW = 0x10 + // Position of COCPU_TSENS_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW_Pos = 0x5 + // Bit mask of COCPU_TSENS_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW_Msk = 0x20 + // Bit COCPU_TSENS_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_TSENS_INT_RAW = 0x20 + // Position of COCPU_START_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_START_INT_RAW_Pos = 0x6 + // Bit mask of COCPU_START_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_START_INT_RAW_Msk = 0x40 + // Bit COCPU_START_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_START_INT_RAW = 0x40 + // Position of COCPU_SW_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SW_INT_RAW_Pos = 0x7 + // Bit mask of COCPU_SW_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SW_INT_RAW_Msk = 0x80 + // Bit COCPU_SW_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_SW_INT_RAW = 0x80 + // Position of COCPU_SWD_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW_Pos = 0x8 + // Bit mask of COCPU_SWD_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW_Msk = 0x100 + // Bit COCPU_SWD_INT_RAW. + SENS_SAR_COCPU_INT_RAW_COCPU_SWD_INT_RAW = 0x100 + + // SAR_COCPU_INT_ENA: Interrupt enable bit of ULP-RISCV + // Position of COCPU_TOUCH_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA_Pos = 0x0 + // Bit mask of COCPU_TOUCH_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA_Msk = 0x1 + // Bit COCPU_TOUCH_DONE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_DONE_INT_ENA = 0x1 + // Position of COCPU_TOUCH_INACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA_Pos = 0x1 + // Bit mask of COCPU_TOUCH_INACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA_Msk = 0x2 + // Bit COCPU_TOUCH_INACTIVE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_INACTIVE_INT_ENA = 0x2 + // Position of COCPU_TOUCH_ACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA_Pos = 0x2 + // Bit mask of COCPU_TOUCH_ACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA_Msk = 0x4 + // Bit COCPU_TOUCH_ACTIVE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_TOUCH_ACTIVE_INT_ENA = 0x4 + // Position of COCPU_SARADC1_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA_Pos = 0x3 + // Bit mask of COCPU_SARADC1_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA_Msk = 0x8 + // Bit COCPU_SARADC1_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC1_INT_ENA = 0x8 + // Position of COCPU_SARADC2_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA_Pos = 0x4 + // Bit mask of COCPU_SARADC2_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA_Msk = 0x10 + // Bit COCPU_SARADC2_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_SARADC2_INT_ENA = 0x10 + // Position of COCPU_TSENS_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA_Pos = 0x5 + // Bit mask of COCPU_TSENS_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA_Msk = 0x20 + // Bit COCPU_TSENS_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_TSENS_INT_ENA = 0x20 + // Position of COCPU_START_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_START_INT_ENA_Pos = 0x6 + // Bit mask of COCPU_START_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_START_INT_ENA_Msk = 0x40 + // Bit COCPU_START_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_START_INT_ENA = 0x40 + // Position of COCPU_SW_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SW_INT_ENA_Pos = 0x7 + // Bit mask of COCPU_SW_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SW_INT_ENA_Msk = 0x80 + // Bit COCPU_SW_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_SW_INT_ENA = 0x80 + // Position of COCPU_SWD_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA_Pos = 0x8 + // Bit mask of COCPU_SWD_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA_Msk = 0x100 + // Bit COCPU_SWD_INT_ENA. + SENS_SAR_COCPU_INT_ENA_COCPU_SWD_INT_ENA = 0x100 + + // SAR_COCPU_INT_ST: Interrupt status bit of ULP-RISCV + // Position of COCPU_TOUCH_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST_Pos = 0x0 + // Bit mask of COCPU_TOUCH_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST_Msk = 0x1 + // Bit COCPU_TOUCH_DONE_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_DONE_INT_ST = 0x1 + // Position of COCPU_TOUCH_INACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST_Pos = 0x1 + // Bit mask of COCPU_TOUCH_INACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST_Msk = 0x2 + // Bit COCPU_TOUCH_INACTIVE_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_INACTIVE_INT_ST = 0x2 + // Position of COCPU_TOUCH_ACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST_Pos = 0x2 + // Bit mask of COCPU_TOUCH_ACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST_Msk = 0x4 + // Bit COCPU_TOUCH_ACTIVE_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_TOUCH_ACTIVE_INT_ST = 0x4 + // Position of COCPU_SARADC1_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST_Pos = 0x3 + // Bit mask of COCPU_SARADC1_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST_Msk = 0x8 + // Bit COCPU_SARADC1_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC1_INT_ST = 0x8 + // Position of COCPU_SARADC2_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST_Pos = 0x4 + // Bit mask of COCPU_SARADC2_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST_Msk = 0x10 + // Bit COCPU_SARADC2_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_SARADC2_INT_ST = 0x10 + // Position of COCPU_TSENS_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TSENS_INT_ST_Pos = 0x5 + // Bit mask of COCPU_TSENS_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_TSENS_INT_ST_Msk = 0x20 + // Bit COCPU_TSENS_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_TSENS_INT_ST = 0x20 + // Position of COCPU_START_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_START_INT_ST_Pos = 0x6 + // Bit mask of COCPU_START_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_START_INT_ST_Msk = 0x40 + // Bit COCPU_START_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_START_INT_ST = 0x40 + // Position of COCPU_SW_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SW_INT_ST_Pos = 0x7 + // Bit mask of COCPU_SW_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SW_INT_ST_Msk = 0x80 + // Bit COCPU_SW_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_SW_INT_ST = 0x80 + // Position of COCPU_SWD_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SWD_INT_ST_Pos = 0x8 + // Bit mask of COCPU_SWD_INT_ST field. + SENS_SAR_COCPU_INT_ST_COCPU_SWD_INT_ST_Msk = 0x100 + // Bit COCPU_SWD_INT_ST. + SENS_SAR_COCPU_INT_ST_COCPU_SWD_INT_ST = 0x100 + + // SAR_COCPU_INT_CLR: Interrupt clear bit of ULP-RISCV + // Position of COCPU_TOUCH_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR_Pos = 0x0 + // Bit mask of COCPU_TOUCH_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR_Msk = 0x1 + // Bit COCPU_TOUCH_DONE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_DONE_INT_CLR = 0x1 + // Position of COCPU_TOUCH_INACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR_Pos = 0x1 + // Bit mask of COCPU_TOUCH_INACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR_Msk = 0x2 + // Bit COCPU_TOUCH_INACTIVE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_INACTIVE_INT_CLR = 0x2 + // Position of COCPU_TOUCH_ACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR_Pos = 0x2 + // Bit mask of COCPU_TOUCH_ACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR_Msk = 0x4 + // Bit COCPU_TOUCH_ACTIVE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_TOUCH_ACTIVE_INT_CLR = 0x4 + // Position of COCPU_SARADC1_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR_Pos = 0x3 + // Bit mask of COCPU_SARADC1_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR_Msk = 0x8 + // Bit COCPU_SARADC1_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC1_INT_CLR = 0x8 + // Position of COCPU_SARADC2_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR_Pos = 0x4 + // Bit mask of COCPU_SARADC2_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR_Msk = 0x10 + // Bit COCPU_SARADC2_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_SARADC2_INT_CLR = 0x10 + // Position of COCPU_TSENS_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR_Pos = 0x5 + // Bit mask of COCPU_TSENS_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR_Msk = 0x20 + // Bit COCPU_TSENS_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_TSENS_INT_CLR = 0x20 + // Position of COCPU_START_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_START_INT_CLR_Pos = 0x6 + // Bit mask of COCPU_START_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_START_INT_CLR_Msk = 0x40 + // Bit COCPU_START_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_START_INT_CLR = 0x40 + // Position of COCPU_SW_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SW_INT_CLR_Pos = 0x7 + // Bit mask of COCPU_SW_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SW_INT_CLR_Msk = 0x80 + // Bit COCPU_SW_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_SW_INT_CLR = 0x80 + // Position of COCPU_SWD_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR_Pos = 0x8 + // Bit mask of COCPU_SWD_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR_Msk = 0x100 + // Bit COCPU_SWD_INT_CLR. + SENS_SAR_COCPU_INT_CLR_COCPU_SWD_INT_CLR = 0x100 +) diff --git a/emb/device/esp/esp32s3.go b/emb/device/esp/esp32s3.go new file mode 100644 index 0000000..054c0fe --- /dev/null +++ b/emb/device/esp/esp32s3.go @@ -0,0 +1,113964 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32s3.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32s3 + +/* +// 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) +*/ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32-S3" + CPU = "Xtensa LX7" + FPUPresent = true + NVICPrioBits = 0 +) + +// Interrupt numbers. +const ( + // Interrupt Controller (Core 0) + IRQ_WIFI_MAC = 0 + + // Interrupt Controller (Core 0) + IRQ_WIFI_NMI = 1 + + // Interrupt Controller (Core 0) + IRQ_WIFI_PWR = 2 + + // Interrupt Controller (Core 0) + IRQ_WIFI_BB = 3 + + // Interrupt Controller (Core 0) + IRQ_BT_MAC = 4 + + // Interrupt Controller (Core 0) + IRQ_BT_BB = 5 + + // Interrupt Controller (Core 0) + IRQ_BT_BB_NMI = 6 + + // Interrupt Controller (Core 0) + IRQ_RWBT = 7 + + // Interrupt Controller (Core 0) + IRQ_RWBLE = 8 + + // Interrupt Controller (Core 0) + IRQ_RWBT_NMI = 9 + + // Interrupt Controller (Core 0) + IRQ_RWBLE_NMI = 10 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_MASTER = 11 + + // Interrupt Controller (Core 0) + IRQ_SLC0 = 12 + + // Interrupt Controller (Core 0) + IRQ_SLC1 = 13 + + // Universal Host Controller Interface 0 + IRQ_UHCI0 = 14 + + // Universal Host Controller Interface 1 + IRQ_UHCI1 = 15 + + // General Purpose Input/Output + IRQ_GPIO = 16 + + // General Purpose Input/Output + IRQ_GPIO_NMI = 17 + + // General Purpose Input/Output + IRQ_GPIO_INTR_2 = 18 + + // General Purpose Input/Output + IRQ_GPIO_NMI_2 = 19 + + // SPI (Serial Peripheral Interface) Controller 1 + IRQ_SPI1 = 20 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_SPI2 = 21 + + // SPI (Serial Peripheral Interface) Controller 3 + IRQ_SPI3 = 22 + + // Camera/LCD Controller + IRQ_LCD_CAM = 24 + + // I2S (Inter-IC Sound) Controller 0 + IRQ_I2S0 = 25 + + // I2S (Inter-IC Sound) Controller 1 + IRQ_I2S1 = 26 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + IRQ_UART0 = 27 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + IRQ_UART1 = 28 + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + IRQ_UART2 = 29 + + // Interrupt Controller (Core 0) + IRQ_SDIO_HOST = 30 + + // Motor Control Pulse-Width Modulation 0 + IRQ_MCPWM0 = 31 + + // Motor Control Pulse-Width Modulation 1 + IRQ_MCPWM1 = 32 + + // LED Control PWM (Pulse Width Modulation) + IRQ_LEDC = 35 + + // eFuse Controller + IRQ_EFUSE = 36 + + // Two-Wire Automotive Interface + IRQ_TWAI0 = 37 + + // USB OTG (On-The-Go) + IRQ_USB = 38 + + // Real-Time Clock Control + IRQ_RTC_CORE = 39 + + // Remote Control + IRQ_RMT = 40 + + // Pulse Count Controller + IRQ_PCNT = 41 + + // I2C (Inter-Integrated Circuit) Controller 0 + IRQ_I2C_EXT0 = 42 + + // I2C (Inter-Integrated Circuit) Controller 1 + IRQ_I2C_EXT1 = 43 + + // SPI (Serial Peripheral Interface) Controller 2 + IRQ_SPI2_DMA = 44 + + // SPI (Serial Peripheral Interface) Controller 3 + IRQ_SPI3_DMA = 45 + + // Interrupt Controller (Core 0) + IRQ_WDT = 47 + + // LED Control PWM (Pulse Width Modulation) + IRQ_TIMER1 = 48 + + // LED Control PWM (Pulse Width Modulation) + IRQ_TIMER2 = 49 + + // Timer Group 0 + IRQ_TG0_T0_LEVEL = 50 + + // Timer Group 0 + IRQ_TG0_T1_LEVEL = 51 + + // Timer Group 0 + IRQ_TG0_WDT_LEVEL = 52 + + // Timer Group 1 + IRQ_TG1_T0_LEVEL = 53 + + // Timer Group 1 + IRQ_TG1_T1_LEVEL = 54 + + // Timer Group 1 + IRQ_TG1_WDT_LEVEL = 55 + + // Interrupt Controller (Core 0) + IRQ_CACHE_IA = 56 + + // System Timer + IRQ_SYSTIMER_TARGET0 = 57 + + // System Timer + IRQ_SYSTIMER_TARGET1 = 58 + + // System Timer + IRQ_SYSTIMER_TARGET2 = 59 + + // SPI (Serial Peripheral Interface) Controller 0 + IRQ_SPI_MEM_REJECT_CACHE = 60 + + // Interrupt Controller (Core 0) + IRQ_DCACHE_PRELOAD0 = 61 + + // Interrupt Controller (Core 0) + IRQ_ICACHE_PRELOAD0 = 62 + + // Interrupt Controller (Core 0) + IRQ_DCACHE_SYNC0 = 63 + + // Interrupt Controller (Core 0) + IRQ_ICACHE_SYNC0 = 64 + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + IRQ_APB_ADC = 65 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH0 = 66 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH1 = 67 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH2 = 68 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH3 = 69 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_IN_CH4 = 70 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH0 = 71 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH1 = 72 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH2 = 73 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH3 = 74 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_OUT_CH4 = 75 + + // RSA (Rivest Shamir Adleman) Accelerator + IRQ_RSA = 76 + + // SHA (Secure Hash Algorithm) Accelerator + IRQ_SHA = 77 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR0 = 79 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR1 = 80 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR2 = 81 + + // Interrupt Controller (Core 0) + IRQ_FROM_CPU_INTR3 = 82 + + // Debug Assist + IRQ_ASSIST_DEBUG = 83 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_APBPERI_PMS = 84 + + // Interrupt Controller (Core 0) + IRQ_CORE0_IRAM0_PMS = 85 + + // Interrupt Controller (Core 0) + IRQ_CORE0_DRAM0_PMS = 86 + + // Interrupt Controller (Core 0) + IRQ_CORE0_PIF_PMS = 87 + + // Interrupt Controller (Core 0) + IRQ_CORE0_PIF_PMS_SIZE = 88 + + // Interrupt Controller (Core 1) + IRQ_CORE1_IRAM0_PMS = 89 + + // Interrupt Controller (Core 1) + IRQ_CORE1_DRAM0_PMS = 90 + + // Interrupt Controller (Core 1) + IRQ_CORE1_PIF_PMS = 91 + + // Interrupt Controller (Core 1) + IRQ_CORE1_PIF_PMS_SIZE = 92 + + // DMA (Direct Memory Access) Controller + IRQ_BACKUP_PMS_VIOLATE = 93 + + // Interrupt Controller (Core 0) + IRQ_CACHE_CORE0_ACS = 94 + + // Interrupt Controller (Core 1) + IRQ_CACHE_CORE1_ACS = 95 + + // Full-speed USB Serial/JTAG Controller + IRQ_USB_DEVICE = 96 + + // PERI_BACKUP Peripheral + IRQ_PERI_BACKUP = 97 + + // DMA (Direct Memory Access) Controller + IRQ_DMA_EXTMEM_REJECT = 98 + + // Highest interrupt number on this device. + IRQ_max = 98 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_WIFI_MAC: + callHandlers(IRQ_WIFI_MAC) + case IRQ_WIFI_NMI: + callHandlers(IRQ_WIFI_NMI) + case IRQ_WIFI_PWR: + callHandlers(IRQ_WIFI_PWR) + case IRQ_WIFI_BB: + callHandlers(IRQ_WIFI_BB) + case IRQ_BT_MAC: + callHandlers(IRQ_BT_MAC) + case IRQ_BT_BB: + callHandlers(IRQ_BT_BB) + case IRQ_BT_BB_NMI: + callHandlers(IRQ_BT_BB_NMI) + case IRQ_RWBT: + callHandlers(IRQ_RWBT) + case IRQ_RWBLE: + callHandlers(IRQ_RWBLE) + case IRQ_RWBT_NMI: + callHandlers(IRQ_RWBT_NMI) + case IRQ_RWBLE_NMI: + callHandlers(IRQ_RWBLE_NMI) + case IRQ_I2C_MASTER: + callHandlers(IRQ_I2C_MASTER) + case IRQ_SLC0: + callHandlers(IRQ_SLC0) + case IRQ_SLC1: + callHandlers(IRQ_SLC1) + case IRQ_UHCI0: + callHandlers(IRQ_UHCI0) + case IRQ_UHCI1: + callHandlers(IRQ_UHCI1) + case IRQ_GPIO: + callHandlers(IRQ_GPIO) + case IRQ_GPIO_NMI: + callHandlers(IRQ_GPIO_NMI) + case IRQ_GPIO_INTR_2: + callHandlers(IRQ_GPIO_INTR_2) + case IRQ_GPIO_NMI_2: + callHandlers(IRQ_GPIO_NMI_2) + case IRQ_SPI1: + callHandlers(IRQ_SPI1) + case IRQ_SPI2: + callHandlers(IRQ_SPI2) + case IRQ_SPI3: + callHandlers(IRQ_SPI3) + case IRQ_LCD_CAM: + callHandlers(IRQ_LCD_CAM) + case IRQ_I2S0: + callHandlers(IRQ_I2S0) + case IRQ_I2S1: + callHandlers(IRQ_I2S1) + case IRQ_UART0: + callHandlers(IRQ_UART0) + case IRQ_UART1: + callHandlers(IRQ_UART1) + case IRQ_UART2: + callHandlers(IRQ_UART2) + case IRQ_SDIO_HOST: + callHandlers(IRQ_SDIO_HOST) + case IRQ_MCPWM0: + callHandlers(IRQ_MCPWM0) + case IRQ_MCPWM1: + callHandlers(IRQ_MCPWM1) + case IRQ_LEDC: + callHandlers(IRQ_LEDC) + case IRQ_EFUSE: + callHandlers(IRQ_EFUSE) + case IRQ_TWAI0: + callHandlers(IRQ_TWAI0) + case IRQ_USB: + callHandlers(IRQ_USB) + case IRQ_RTC_CORE: + callHandlers(IRQ_RTC_CORE) + case IRQ_RMT: + callHandlers(IRQ_RMT) + case IRQ_PCNT: + callHandlers(IRQ_PCNT) + case IRQ_I2C_EXT0: + callHandlers(IRQ_I2C_EXT0) + case IRQ_I2C_EXT1: + callHandlers(IRQ_I2C_EXT1) + case IRQ_SPI2_DMA: + callHandlers(IRQ_SPI2_DMA) + case IRQ_SPI3_DMA: + callHandlers(IRQ_SPI3_DMA) + case IRQ_WDT: + callHandlers(IRQ_WDT) + case IRQ_TIMER1: + callHandlers(IRQ_TIMER1) + case IRQ_TIMER2: + callHandlers(IRQ_TIMER2) + case IRQ_TG0_T0_LEVEL: + callHandlers(IRQ_TG0_T0_LEVEL) + case IRQ_TG0_T1_LEVEL: + callHandlers(IRQ_TG0_T1_LEVEL) + case IRQ_TG0_WDT_LEVEL: + callHandlers(IRQ_TG0_WDT_LEVEL) + case IRQ_TG1_T0_LEVEL: + callHandlers(IRQ_TG1_T0_LEVEL) + case IRQ_TG1_T1_LEVEL: + callHandlers(IRQ_TG1_T1_LEVEL) + case IRQ_TG1_WDT_LEVEL: + callHandlers(IRQ_TG1_WDT_LEVEL) + case IRQ_CACHE_IA: + callHandlers(IRQ_CACHE_IA) + case IRQ_SYSTIMER_TARGET0: + callHandlers(IRQ_SYSTIMER_TARGET0) + case IRQ_SYSTIMER_TARGET1: + callHandlers(IRQ_SYSTIMER_TARGET1) + case IRQ_SYSTIMER_TARGET2: + callHandlers(IRQ_SYSTIMER_TARGET2) + case IRQ_SPI_MEM_REJECT_CACHE: + callHandlers(IRQ_SPI_MEM_REJECT_CACHE) + case IRQ_DCACHE_PRELOAD0: + callHandlers(IRQ_DCACHE_PRELOAD0) + case IRQ_ICACHE_PRELOAD0: + callHandlers(IRQ_ICACHE_PRELOAD0) + case IRQ_DCACHE_SYNC0: + callHandlers(IRQ_DCACHE_SYNC0) + case IRQ_ICACHE_SYNC0: + callHandlers(IRQ_ICACHE_SYNC0) + case IRQ_APB_ADC: + callHandlers(IRQ_APB_ADC) + case IRQ_DMA_IN_CH0: + callHandlers(IRQ_DMA_IN_CH0) + case IRQ_DMA_IN_CH1: + callHandlers(IRQ_DMA_IN_CH1) + case IRQ_DMA_IN_CH2: + callHandlers(IRQ_DMA_IN_CH2) + case IRQ_DMA_IN_CH3: + callHandlers(IRQ_DMA_IN_CH3) + case IRQ_DMA_IN_CH4: + callHandlers(IRQ_DMA_IN_CH4) + case IRQ_DMA_OUT_CH0: + callHandlers(IRQ_DMA_OUT_CH0) + case IRQ_DMA_OUT_CH1: + callHandlers(IRQ_DMA_OUT_CH1) + case IRQ_DMA_OUT_CH2: + callHandlers(IRQ_DMA_OUT_CH2) + case IRQ_DMA_OUT_CH3: + callHandlers(IRQ_DMA_OUT_CH3) + case IRQ_DMA_OUT_CH4: + callHandlers(IRQ_DMA_OUT_CH4) + case IRQ_RSA: + callHandlers(IRQ_RSA) + case IRQ_SHA: + callHandlers(IRQ_SHA) + case IRQ_FROM_CPU_INTR0: + callHandlers(IRQ_FROM_CPU_INTR0) + case IRQ_FROM_CPU_INTR1: + callHandlers(IRQ_FROM_CPU_INTR1) + case IRQ_FROM_CPU_INTR2: + callHandlers(IRQ_FROM_CPU_INTR2) + case IRQ_FROM_CPU_INTR3: + callHandlers(IRQ_FROM_CPU_INTR3) + case IRQ_ASSIST_DEBUG: + callHandlers(IRQ_ASSIST_DEBUG) + case IRQ_DMA_APBPERI_PMS: + callHandlers(IRQ_DMA_APBPERI_PMS) + case IRQ_CORE0_IRAM0_PMS: + callHandlers(IRQ_CORE0_IRAM0_PMS) + case IRQ_CORE0_DRAM0_PMS: + callHandlers(IRQ_CORE0_DRAM0_PMS) + case IRQ_CORE0_PIF_PMS: + callHandlers(IRQ_CORE0_PIF_PMS) + case IRQ_CORE0_PIF_PMS_SIZE: + callHandlers(IRQ_CORE0_PIF_PMS_SIZE) + case IRQ_CORE1_IRAM0_PMS: + callHandlers(IRQ_CORE1_IRAM0_PMS) + case IRQ_CORE1_DRAM0_PMS: + callHandlers(IRQ_CORE1_DRAM0_PMS) + case IRQ_CORE1_PIF_PMS: + callHandlers(IRQ_CORE1_PIF_PMS) + case IRQ_CORE1_PIF_PMS_SIZE: + callHandlers(IRQ_CORE1_PIF_PMS_SIZE) + case IRQ_BACKUP_PMS_VIOLATE: + callHandlers(IRQ_BACKUP_PMS_VIOLATE) + case IRQ_CACHE_CORE0_ACS: + callHandlers(IRQ_CACHE_CORE0_ACS) + case IRQ_CACHE_CORE1_ACS: + callHandlers(IRQ_CACHE_CORE1_ACS) + case IRQ_USB_DEVICE: + callHandlers(IRQ_USB_DEVICE) + case IRQ_PERI_BACKUP: + callHandlers(IRQ_PERI_BACKUP) + case IRQ_DMA_EXTMEM_REJECT: + callHandlers(IRQ_DMA_EXTMEM_REJECT) + } +} + +// Peripherals. +var ( + // AES (Advanced Encryption Standard) Accelerator + AES = (*AES_Type)(unsafe.Pointer(uintptr(0x6003a000))) + + // APB (Advanced Peripheral Bus) Controller + APB_CTRL = (*APB_CTRL_Type)(unsafe.Pointer(uintptr(0x60026000))) + + // SAR (Successive Approximation Register) Analog-to-Digital Converter + APB_SARADC = (*APB_SARADC_Type)(unsafe.Pointer(uintptr(0x60040000))) + + // BB Peripheral + BB = (*BB_Type)(unsafe.Pointer(uintptr(0x6001d000))) + + // Debug Assist + ASSIST_DEBUG = (*DEBUG_ASSIST_Type)(unsafe.Pointer(uintptr(0x600ce000))) + + // DMA (Direct Memory Access) Controller + DMA = (*DMA_Type)(unsafe.Pointer(uintptr(0x6003f000))) + + // Digital Signature + DS = (*DS_Type)(unsafe.Pointer(uintptr(0x6003d000))) + + // eFuse Controller + EFUSE = (*EFUSE_Type)(unsafe.Pointer(uintptr(0x60007000))) + + // External Memory + EXTMEM = (*EXTMEM_Type)(unsafe.Pointer(uintptr(0x600c4000))) + + // General Purpose Input/Output + GPIO = (*GPIO_Type)(unsafe.Pointer(uintptr(0x60004000))) + + // Sigma-Delta Modulation + GPIO_SD = (*GPIOSD_Type)(unsafe.Pointer(uintptr(0x60004f00))) + + // HMAC (Hash-based Message Authentication Code) Accelerator + HMAC = (*HMAC_Type)(unsafe.Pointer(uintptr(0x6003e000))) + + // I2C (Inter-Integrated Circuit) Controller 0 + I2C0 = (*I2C_Type)(unsafe.Pointer(uintptr(0x60013000))) + + // I2S (Inter-IC Sound) Controller 0 + I2S0 = (*I2S_Type)(unsafe.Pointer(uintptr(0x6000f000))) + + // I2S (Inter-IC Sound) Controller 1 + I2S1 = (*I2S1_Type)(unsafe.Pointer(uintptr(0x6002d000))) + + // Interrupt Controller (Core 0) + INTERRUPT_CORE0 = (*INTERRUPT_CORE0_Type)(unsafe.Pointer(uintptr(0x600c2000))) + + // Interrupt Controller (Core 1) + INTERRUPT_CORE1 = (*INTERRUPT_CORE1_Type)(unsafe.Pointer(uintptr(0x600c2000))) + + // Input/Output Multiplexer + IO_MUX = (*IO_MUX_Type)(unsafe.Pointer(uintptr(0x60009000))) + + // Camera/LCD Controller + LCD_CAM = (*LCD_CAM_Type)(unsafe.Pointer(uintptr(0x60041000))) + + // LED Control PWM (Pulse Width Modulation) + LEDC = (*LEDC_Type)(unsafe.Pointer(uintptr(0x60019000))) + + // Pulse Count Controller + PCNT = (*PCNT_Type)(unsafe.Pointer(uintptr(0x60017000))) + + // PERI_BACKUP Peripheral + PERI_BACKUP = (*PERI_BACKUP_Type)(unsafe.Pointer(uintptr(0x6002a000))) + + // Motor Control Pulse-Width Modulation 0 + MCPWM0 = (*PWM_Type)(unsafe.Pointer(uintptr(0x6001e000))) + + // Remote Control + RMT = (*RMT_Type)(unsafe.Pointer(uintptr(0x60016000))) + + // Hardware Random Number Generator + RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x60034f6c))) + + // RSA (Rivest Shamir Adleman) Accelerator + RSA = (*RSA_Type)(unsafe.Pointer(uintptr(0x6003c000))) + + // Real-Time Clock Control + RTC_CNTL = (*RTC_CNTL_Type)(unsafe.Pointer(uintptr(0x60008000))) + + // Low-power I2C (Inter-Integrated Circuit) Controller + RTC_I2C = (*RTC_I2C_Type)(unsafe.Pointer(uintptr(0x60008c00))) + + // Low-power Input/Output + RTC_IO = (*RTC_IO_Type)(unsafe.Pointer(uintptr(0x60008400))) + + // SD/MMC Host Controller + SDHOST = (*SDHOST_Type)(unsafe.Pointer(uintptr(0x60028000))) + + // SENS Peripheral + SENS = (*SENS_Type)(unsafe.Pointer(uintptr(0x60008800))) + + // SENSITIVE Peripheral + SENSITIVE = (*SENSITIVE_Type)(unsafe.Pointer(uintptr(0x600c1000))) + + // SHA (Secure Hash Algorithm) Accelerator + SHA = (*SHA_Type)(unsafe.Pointer(uintptr(0x6003b000))) + + // SPI (Serial Peripheral Interface) Controller 0 + SPI0 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x60003000))) + + // SPI (Serial Peripheral Interface) Controller 1 + SPI1 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x60002000))) + + // SPI (Serial Peripheral Interface) Controller 2 + SPI2 = (*SPI2_Type)(unsafe.Pointer(uintptr(0x60024000))) + + // SPI (Serial Peripheral Interface) Controller 3 + SPI3 = (*SPI2_Type)(unsafe.Pointer(uintptr(0x60025000))) + + // System Configuration Registers + SYSTEM = (*SYSTEM_Type)(unsafe.Pointer(uintptr(0x600c0000))) + + // System Timer + SYSTIMER = (*SYSTIMER_Type)(unsafe.Pointer(uintptr(0x60023000))) + + // Timer Group 0 + TIMG0 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x6001f000))) + + // Two-Wire Automotive Interface + TWAI0 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x6002b000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART0 = (*UART_Type)(unsafe.Pointer(uintptr(0x60000000))) + + // Universal Host Controller Interface 0 + UHCI0 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x60014000))) + + // USB OTG (On-The-Go) + USB0 = (*USB_Type)(unsafe.Pointer(uintptr(0x60080000))) + + // Full-speed USB Serial/JTAG Controller + USB_DEVICE = (*USB_DEVICE_Type)(unsafe.Pointer(uintptr(0x60038000))) + + // USB_WRAP Peripheral + USB_WRAP = (*USB_WRAP_Type)(unsafe.Pointer(uintptr(0x60039000))) + + // WCL Peripheral + WCL = (*WCL_Type)(unsafe.Pointer(uintptr(0x600d0000))) + + // XTS-AES-128 Flash Encryption + XTS_AES = (*XTS_AES_Type)(unsafe.Pointer(uintptr(0x600cc000))) + + // I2C (Inter-Integrated Circuit) Controller 1 + I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x60027000))) + + // Motor Control Pulse-Width Modulation 1 + MCPWM1 = (*PWM_Type)(unsafe.Pointer(uintptr(0x6002c000))) + + // Timer Group 1 + TIMG1 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x60020000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + UART1 = (*UART_Type)(unsafe.Pointer(uintptr(0x60010000))) + + // UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + UART2 = (*UART_Type)(unsafe.Pointer(uintptr(0x6002e000))) + + // Universal Host Controller Interface 1 + UHCI1 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x6000c000))) +) + +// AES (Advanced Encryption Standard) Accelerator +type AES_Type struct { + KEY_0 volatile.Register32 // 0x0 + KEY_1 volatile.Register32 // 0x4 + KEY_2 volatile.Register32 // 0x8 + KEY_3 volatile.Register32 // 0xC + KEY_4 volatile.Register32 // 0x10 + KEY_5 volatile.Register32 // 0x14 + KEY_6 volatile.Register32 // 0x18 + KEY_7 volatile.Register32 // 0x1C + TEXT_IN_0 volatile.Register32 // 0x20 + TEXT_IN_1 volatile.Register32 // 0x24 + TEXT_IN_2 volatile.Register32 // 0x28 + TEXT_IN_3 volatile.Register32 // 0x2C + TEXT_OUT_0 volatile.Register32 // 0x30 + TEXT_OUT_1 volatile.Register32 // 0x34 + TEXT_OUT_2 volatile.Register32 // 0x38 + TEXT_OUT_3 volatile.Register32 // 0x3C + MODE volatile.Register32 // 0x40 + _ [4]byte + TRIGGER volatile.Register32 // 0x48 + STATE volatile.Register32 // 0x4C + IV_MEM [16]volatile.Register8 // 0x50 + H_MEM [16]volatile.Register8 // 0x60 + J0_MEM [16]volatile.Register8 // 0x70 + T0_MEM [16]volatile.Register8 // 0x80 + DMA_ENABLE volatile.Register32 // 0x90 + BLOCK_MODE volatile.Register32 // 0x94 + BLOCK_NUM volatile.Register32 // 0x98 + INC_SEL volatile.Register32 // 0x9C + AAD_BLOCK_NUM volatile.Register32 // 0xA0 + REMAINDER_BIT_NUM volatile.Register32 // 0xA4 + CONTINUE volatile.Register32 // 0xA8 + INT_CLR volatile.Register32 // 0xAC + INT_ENA volatile.Register32 // 0xB0 + DATE volatile.Register32 // 0xB4 + DMA_EXIT volatile.Register32 // 0xB8 +} + +// AES.KEY_0: AES key register %s +func (o *AES_Type) SetKEY_0(value uint32) { + volatile.StoreUint32(&o.KEY_0.Reg, value) +} +func (o *AES_Type) GetKEY_0() uint32 { + return volatile.LoadUint32(&o.KEY_0.Reg) +} + +// AES.KEY_1: AES key register %s +func (o *AES_Type) SetKEY_1(value uint32) { + volatile.StoreUint32(&o.KEY_1.Reg, value) +} +func (o *AES_Type) GetKEY_1() uint32 { + return volatile.LoadUint32(&o.KEY_1.Reg) +} + +// AES.KEY_2: AES key register %s +func (o *AES_Type) SetKEY_2(value uint32) { + volatile.StoreUint32(&o.KEY_2.Reg, value) +} +func (o *AES_Type) GetKEY_2() uint32 { + return volatile.LoadUint32(&o.KEY_2.Reg) +} + +// AES.KEY_3: AES key register %s +func (o *AES_Type) SetKEY_3(value uint32) { + volatile.StoreUint32(&o.KEY_3.Reg, value) +} +func (o *AES_Type) GetKEY_3() uint32 { + return volatile.LoadUint32(&o.KEY_3.Reg) +} + +// AES.KEY_4: AES key register %s +func (o *AES_Type) SetKEY_4(value uint32) { + volatile.StoreUint32(&o.KEY_4.Reg, value) +} +func (o *AES_Type) GetKEY_4() uint32 { + return volatile.LoadUint32(&o.KEY_4.Reg) +} + +// AES.KEY_5: AES key register %s +func (o *AES_Type) SetKEY_5(value uint32) { + volatile.StoreUint32(&o.KEY_5.Reg, value) +} +func (o *AES_Type) GetKEY_5() uint32 { + return volatile.LoadUint32(&o.KEY_5.Reg) +} + +// AES.KEY_6: AES key register %s +func (o *AES_Type) SetKEY_6(value uint32) { + volatile.StoreUint32(&o.KEY_6.Reg, value) +} +func (o *AES_Type) GetKEY_6() uint32 { + return volatile.LoadUint32(&o.KEY_6.Reg) +} + +// AES.KEY_7: AES key register %s +func (o *AES_Type) SetKEY_7(value uint32) { + volatile.StoreUint32(&o.KEY_7.Reg, value) +} +func (o *AES_Type) GetKEY_7() uint32 { + return volatile.LoadUint32(&o.KEY_7.Reg) +} + +// AES.TEXT_IN_0: Source data register %s +func (o *AES_Type) SetTEXT_IN_0(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_0.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_0() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_0.Reg) +} + +// AES.TEXT_IN_1: Source data register %s +func (o *AES_Type) SetTEXT_IN_1(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_1.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_1() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_1.Reg) +} + +// AES.TEXT_IN_2: Source data register %s +func (o *AES_Type) SetTEXT_IN_2(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_2.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_2() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_2.Reg) +} + +// AES.TEXT_IN_3: Source data register %s +func (o *AES_Type) SetTEXT_IN_3(value uint32) { + volatile.StoreUint32(&o.TEXT_IN_3.Reg, value) +} +func (o *AES_Type) GetTEXT_IN_3() uint32 { + return volatile.LoadUint32(&o.TEXT_IN_3.Reg) +} + +// AES.TEXT_OUT_0: Result data register %s +func (o *AES_Type) SetTEXT_OUT_0(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_0.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_0() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_0.Reg) +} + +// AES.TEXT_OUT_1: Result data register %s +func (o *AES_Type) SetTEXT_OUT_1(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_1.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_1() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_1.Reg) +} + +// AES.TEXT_OUT_2: Result data register %s +func (o *AES_Type) SetTEXT_OUT_2(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_2.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_2() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_2.Reg) +} + +// AES.TEXT_OUT_3: Result data register %s +func (o *AES_Type) SetTEXT_OUT_3(value uint32) { + volatile.StoreUint32(&o.TEXT_OUT_3.Reg, value) +} +func (o *AES_Type) GetTEXT_OUT_3() uint32 { + return volatile.LoadUint32(&o.TEXT_OUT_3.Reg) +} + +// AES.MODE: AES Mode register +func (o *AES_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// AES.TRIGGER: AES trigger register +func (o *AES_Type) SetTRIGGER(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetTRIGGER() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} + +// AES.STATE: AES state register +func (o *AES_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *AES_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// AES.DMA_ENABLE: AES accelerator working mode register +func (o *AES_Type) SetDMA_ENABLE(value uint32) { + volatile.StoreUint32(&o.DMA_ENABLE.Reg, volatile.LoadUint32(&o.DMA_ENABLE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_ENABLE() uint32 { + return volatile.LoadUint32(&o.DMA_ENABLE.Reg) & 0x1 +} + +// AES.BLOCK_MODE: AES cipher block mode register +func (o *AES_Type) SetBLOCK_MODE(value uint32) { + volatile.StoreUint32(&o.BLOCK_MODE.Reg, volatile.LoadUint32(&o.BLOCK_MODE.Reg)&^(0x7)|value) +} +func (o *AES_Type) GetBLOCK_MODE() uint32 { + return volatile.LoadUint32(&o.BLOCK_MODE.Reg) & 0x7 +} + +// AES.BLOCK_NUM: AES block number register +func (o *AES_Type) SetBLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetBLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.BLOCK_NUM.Reg) +} + +// AES.INC_SEL: Standard incrementing function configure register +func (o *AES_Type) SetINC_SEL(value uint32) { + volatile.StoreUint32(&o.INC_SEL.Reg, volatile.LoadUint32(&o.INC_SEL.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINC_SEL() uint32 { + return volatile.LoadUint32(&o.INC_SEL.Reg) & 0x1 +} + +// AES.AAD_BLOCK_NUM: Additional Authential Data block number register +func (o *AES_Type) SetAAD_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.AAD_BLOCK_NUM.Reg, value) +} +func (o *AES_Type) GetAAD_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.AAD_BLOCK_NUM.Reg) +} + +// AES.REMAINDER_BIT_NUM: AES remainder bit number register +func (o *AES_Type) SetREMAINDER_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.REMAINDER_BIT_NUM.Reg, volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg)&^(0x7f)|value) +} +func (o *AES_Type) GetREMAINDER_BIT_NUM() uint32 { + return volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg) & 0x7f +} + +// AES.CONTINUE: AES continue register +func (o *AES_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetCONTINUE() uint32 { + return volatile.LoadUint32(&o.CONTINUE.Reg) & 0x1 +} + +// AES.INT_CLR: AES Interrupt clear register +func (o *AES_Type) SetINT_CLR_INT_CLEAR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_CLR_INT_CLEAR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} + +// AES.INT_ENA: DMA-AES Interrupt enable register +func (o *AES_Type) SetINT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetINT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} + +// AES.DATE: AES version control register +func (o *AES_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *AES_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// AES.DMA_EXIT: AES-DMA exit config +func (o *AES_Type) SetDMA_EXIT(value uint32) { + volatile.StoreUint32(&o.DMA_EXIT.Reg, volatile.LoadUint32(&o.DMA_EXIT.Reg)&^(0x1)|value) +} +func (o *AES_Type) GetDMA_EXIT() uint32 { + return volatile.LoadUint32(&o.DMA_EXIT.Reg) & 0x1 +} + +// APB (Advanced Peripheral Bus) Controller +type APB_CTRL_Type struct { + SYSCLK_CONF volatile.Register32 // 0x0 + TICK_CONF volatile.Register32 // 0x4 + CLK_OUT_EN volatile.Register32 // 0x8 + WIFI_BB_CFG volatile.Register32 // 0xC + WIFI_BB_CFG_2 volatile.Register32 // 0x10 + WIFI_CLK_EN volatile.Register32 // 0x14 + WIFI_RST_EN volatile.Register32 // 0x18 + HOST_INF_SEL volatile.Register32 // 0x1C + EXT_MEM_PMS_LOCK volatile.Register32 // 0x20 + EXT_MEM_WRITEBACK_BYPASS volatile.Register32 // 0x24 + FLASH_ACE0_ATTR volatile.Register32 // 0x28 + FLASH_ACE1_ATTR volatile.Register32 // 0x2C + FLASH_ACE2_ATTR volatile.Register32 // 0x30 + FLASH_ACE3_ATTR volatile.Register32 // 0x34 + FLASH_ACE0_ADDR volatile.Register32 // 0x38 + FLASH_ACE1_ADDR volatile.Register32 // 0x3C + FLASH_ACE2_ADDR volatile.Register32 // 0x40 + FLASH_ACE3_ADDR volatile.Register32 // 0x44 + FLASH_ACE0_SIZE volatile.Register32 // 0x48 + FLASH_ACE1_SIZE volatile.Register32 // 0x4C + FLASH_ACE2_SIZE volatile.Register32 // 0x50 + FLASH_ACE3_SIZE volatile.Register32 // 0x54 + SRAM_ACE0_ATTR volatile.Register32 // 0x58 + SRAM_ACE1_ATTR volatile.Register32 // 0x5C + SRAM_ACE2_ATTR volatile.Register32 // 0x60 + SRAM_ACE3_ATTR volatile.Register32 // 0x64 + SRAM_ACE0_ADDR volatile.Register32 // 0x68 + SRAM_ACE1_ADDR volatile.Register32 // 0x6C + SRAM_ACE2_ADDR volatile.Register32 // 0x70 + SRAM_ACE3_ADDR volatile.Register32 // 0x74 + SRAM_ACE0_SIZE volatile.Register32 // 0x78 + SRAM_ACE1_SIZE volatile.Register32 // 0x7C + SRAM_ACE2_SIZE volatile.Register32 // 0x80 + SRAM_ACE3_SIZE volatile.Register32 // 0x84 + SPI_MEM_PMS_CTRL volatile.Register32 // 0x88 + SPI_MEM_REJECT_ADDR volatile.Register32 // 0x8C + SDIO_CTRL volatile.Register32 // 0x90 + REDCY_SIG0 volatile.Register32 // 0x94 + REDCY_SIG1 volatile.Register32 // 0x98 + FRONT_END_MEM_PD volatile.Register32 // 0x9C + SPI_MEM_ECC_CTRL volatile.Register32 // 0xA0 + _ [4]byte + CLKGATE_FORCE_ON volatile.Register32 // 0xA8 + MEM_POWER_DOWN volatile.Register32 // 0xAC + MEM_POWER_UP volatile.Register32 // 0xB0 + RETENTION_CTRL volatile.Register32 // 0xB4 + RETENTION_CTRL1 volatile.Register32 // 0xB8 + RETENTION_CTRL2 volatile.Register32 // 0xBC + RETENTION_CTRL3 volatile.Register32 // 0xC0 + RETENTION_CTRL4 volatile.Register32 // 0xC4 + RETENTION_CTRL5 volatile.Register32 // 0xC8 + _ [816]byte + DATE volatile.Register32 // 0x3FC +} + +// APB_CTRL.SYSCLK_CONF: ******* Description *********** +func (o *APB_CTRL_Type) SetSYSCLK_CONF_PRE_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x3ff)|value) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_PRE_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x3ff +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_CLK_320M_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_CLK_320M_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x400) >> 10 +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x800)|value<<11) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x800) >> 11 +} +func (o *APB_CTRL_Type) SetSYSCLK_CONF_RST_TICK_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *APB_CTRL_Type) GetSYSCLK_CONF_RST_TICK_CNT() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x1000) >> 12 +} + +// APB_CTRL.TICK_CONF: ******* Description *********** +func (o *APB_CTRL_Type) SetTICK_CONF_XTAL_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetTICK_CONF_XTAL_TICK_NUM() uint32 { + return volatile.LoadUint32(&o.TICK_CONF.Reg) & 0xff +} +func (o *APB_CTRL_Type) SetTICK_CONF_CK8M_TICK_NUM(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0xff00)|value<<8) +} +func (o *APB_CTRL_Type) GetTICK_CONF_CK8M_TICK_NUM() uint32 { + return (volatile.LoadUint32(&o.TICK_CONF.Reg) & 0xff00) >> 8 +} +func (o *APB_CTRL_Type) SetTICK_CONF_TICK_ENABLE(value uint32) { + volatile.StoreUint32(&o.TICK_CONF.Reg, volatile.LoadUint32(&o.TICK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *APB_CTRL_Type) GetTICK_CONF_TICK_ENABLE() uint32 { + return (volatile.LoadUint32(&o.TICK_CONF.Reg) & 0x10000) >> 16 +} + +// APB_CTRL.CLK_OUT_EN: ******* Description *********** +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK20_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK20_OEN() uint32 { + return volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK22_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK22_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK44_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x4)|value<<2) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK44_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x4) >> 2 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x8)|value<<3) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x8) >> 3 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK80_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x10)|value<<4) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK80_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x10) >> 4 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK160_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x20)|value<<5) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK160_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x20) >> 5 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_320M_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x40)|value<<6) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_320M_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x40) >> 6 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_ADC_INF_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x80)|value<<7) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_ADC_INF_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x80) >> 7 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_DAC_CPU_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x100)|value<<8) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_DAC_CPU_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x100) >> 8 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK40X_BB_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x200)|value<<9) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK40X_BB_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x200) >> 9 +} +func (o *APB_CTRL_Type) SetCLK_OUT_EN_CLK_XTAL_OEN(value uint32) { + volatile.StoreUint32(&o.CLK_OUT_EN.Reg, volatile.LoadUint32(&o.CLK_OUT_EN.Reg)&^(0x400)|value<<10) +} +func (o *APB_CTRL_Type) GetCLK_OUT_EN_CLK_XTAL_OEN() uint32 { + return (volatile.LoadUint32(&o.CLK_OUT_EN.Reg) & 0x400) >> 10 +} + +// APB_CTRL.WIFI_BB_CFG: ******* Description *********** +func (o *APB_CTRL_Type) SetWIFI_BB_CFG(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_BB_CFG() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG.Reg) +} + +// APB_CTRL.WIFI_BB_CFG_2: ******* Description *********** +func (o *APB_CTRL_Type) SetWIFI_BB_CFG_2(value uint32) { + volatile.StoreUint32(&o.WIFI_BB_CFG_2.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_BB_CFG_2() uint32 { + return volatile.LoadUint32(&o.WIFI_BB_CFG_2.Reg) +} + +// APB_CTRL.WIFI_CLK_EN: ******* Description *********** +func (o *APB_CTRL_Type) SetWIFI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_CLK_EN.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_CLK_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_CLK_EN.Reg) +} + +// APB_CTRL.WIFI_RST_EN: ******* Description *********** +func (o *APB_CTRL_Type) SetWIFI_RST_EN(value uint32) { + volatile.StoreUint32(&o.WIFI_RST_EN.Reg, value) +} +func (o *APB_CTRL_Type) GetWIFI_RST_EN() uint32 { + return volatile.LoadUint32(&o.WIFI_RST_EN.Reg) +} + +// APB_CTRL.HOST_INF_SEL: ******* Description *********** +func (o *APB_CTRL_Type) SetHOST_INF_SEL_PERI_IO_SWAP(value uint32) { + volatile.StoreUint32(&o.HOST_INF_SEL.Reg, volatile.LoadUint32(&o.HOST_INF_SEL.Reg)&^(0xff)|value) +} +func (o *APB_CTRL_Type) GetHOST_INF_SEL_PERI_IO_SWAP() uint32 { + return volatile.LoadUint32(&o.HOST_INF_SEL.Reg) & 0xff +} + +// APB_CTRL.EXT_MEM_PMS_LOCK: ******* Description *********** +func (o *APB_CTRL_Type) SetEXT_MEM_PMS_LOCK(value uint32) { + volatile.StoreUint32(&o.EXT_MEM_PMS_LOCK.Reg, volatile.LoadUint32(&o.EXT_MEM_PMS_LOCK.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetEXT_MEM_PMS_LOCK() uint32 { + return volatile.LoadUint32(&o.EXT_MEM_PMS_LOCK.Reg) & 0x1 +} + +// APB_CTRL.EXT_MEM_WRITEBACK_BYPASS: ******* Description *********** +func (o *APB_CTRL_Type) SetEXT_MEM_WRITEBACK_BYPASS_WRITEBACK_BYPASS(value uint32) { + volatile.StoreUint32(&o.EXT_MEM_WRITEBACK_BYPASS.Reg, volatile.LoadUint32(&o.EXT_MEM_WRITEBACK_BYPASS.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetEXT_MEM_WRITEBACK_BYPASS_WRITEBACK_BYPASS() uint32 { + return volatile.LoadUint32(&o.EXT_MEM_WRITEBACK_BYPASS.Reg) & 0x1 +} + +// APB_CTRL.FLASH_ACE0_ATTR: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE0_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE0_ATTR.Reg)&^(0x1ff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE0_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_ATTR.Reg) & 0x1ff +} + +// APB_CTRL.FLASH_ACE1_ATTR: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE1_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE1_ATTR.Reg)&^(0x1ff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE1_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_ATTR.Reg) & 0x1ff +} + +// APB_CTRL.FLASH_ACE2_ATTR: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE2_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE2_ATTR.Reg)&^(0x1ff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE2_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_ATTR.Reg) & 0x1ff +} + +// APB_CTRL.FLASH_ACE3_ATTR: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE3_ATTR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_ATTR.Reg, volatile.LoadUint32(&o.FLASH_ACE3_ATTR.Reg)&^(0x1ff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE3_ATTR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_ATTR.Reg) & 0x1ff +} + +// APB_CTRL.FLASH_ACE0_ADDR: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE0_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE0_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE1_ADDR: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE1_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE1_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE2_ADDR: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE2_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE2_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE3_ADDR: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE3_ADDR(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE3_ADDR() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_ADDR.Reg) +} + +// APB_CTRL.FLASH_ACE0_SIZE: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE0_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE0_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE0_SIZE.Reg)&^(0xffff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE0_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE0_SIZE.Reg) & 0xffff +} + +// APB_CTRL.FLASH_ACE1_SIZE: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE1_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE1_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE1_SIZE.Reg)&^(0xffff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE1_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE1_SIZE.Reg) & 0xffff +} + +// APB_CTRL.FLASH_ACE2_SIZE: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE2_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE2_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE2_SIZE.Reg)&^(0xffff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE2_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE2_SIZE.Reg) & 0xffff +} + +// APB_CTRL.FLASH_ACE3_SIZE: ******* Description *********** +func (o *APB_CTRL_Type) SetFLASH_ACE3_SIZE(value uint32) { + volatile.StoreUint32(&o.FLASH_ACE3_SIZE.Reg, volatile.LoadUint32(&o.FLASH_ACE3_SIZE.Reg)&^(0xffff)|value) +} +func (o *APB_CTRL_Type) GetFLASH_ACE3_SIZE() uint32 { + return volatile.LoadUint32(&o.FLASH_ACE3_SIZE.Reg) & 0xffff +} + +// APB_CTRL.SRAM_ACE0_ATTR: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE0_ATTR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE0_ATTR.Reg, volatile.LoadUint32(&o.SRAM_ACE0_ATTR.Reg)&^(0x1ff)|value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE0_ATTR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE0_ATTR.Reg) & 0x1ff +} + +// APB_CTRL.SRAM_ACE1_ATTR: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE1_ATTR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE1_ATTR.Reg, volatile.LoadUint32(&o.SRAM_ACE1_ATTR.Reg)&^(0x1ff)|value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE1_ATTR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE1_ATTR.Reg) & 0x1ff +} + +// APB_CTRL.SRAM_ACE2_ATTR: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE2_ATTR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE2_ATTR.Reg, volatile.LoadUint32(&o.SRAM_ACE2_ATTR.Reg)&^(0x1ff)|value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE2_ATTR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE2_ATTR.Reg) & 0x1ff +} + +// APB_CTRL.SRAM_ACE3_ATTR: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE3_ATTR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE3_ATTR.Reg, volatile.LoadUint32(&o.SRAM_ACE3_ATTR.Reg)&^(0x1ff)|value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE3_ATTR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE3_ATTR.Reg) & 0x1ff +} + +// APB_CTRL.SRAM_ACE0_ADDR: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE0_ADDR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE0_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE0_ADDR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE0_ADDR.Reg) +} + +// APB_CTRL.SRAM_ACE1_ADDR: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE1_ADDR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE1_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE1_ADDR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE1_ADDR.Reg) +} + +// APB_CTRL.SRAM_ACE2_ADDR: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE2_ADDR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE2_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE2_ADDR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE2_ADDR.Reg) +} + +// APB_CTRL.SRAM_ACE3_ADDR: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE3_ADDR(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE3_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE3_ADDR() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE3_ADDR.Reg) +} + +// APB_CTRL.SRAM_ACE0_SIZE: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE0_SIZE(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE0_SIZE.Reg, volatile.LoadUint32(&o.SRAM_ACE0_SIZE.Reg)&^(0xffff)|value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE0_SIZE() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE0_SIZE.Reg) & 0xffff +} + +// APB_CTRL.SRAM_ACE1_SIZE: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE1_SIZE(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE1_SIZE.Reg, volatile.LoadUint32(&o.SRAM_ACE1_SIZE.Reg)&^(0xffff)|value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE1_SIZE() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE1_SIZE.Reg) & 0xffff +} + +// APB_CTRL.SRAM_ACE2_SIZE: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE2_SIZE(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE2_SIZE.Reg, volatile.LoadUint32(&o.SRAM_ACE2_SIZE.Reg)&^(0xffff)|value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE2_SIZE() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE2_SIZE.Reg) & 0xffff +} + +// APB_CTRL.SRAM_ACE3_SIZE: ******* Description *********** +func (o *APB_CTRL_Type) SetSRAM_ACE3_SIZE(value uint32) { + volatile.StoreUint32(&o.SRAM_ACE3_SIZE.Reg, volatile.LoadUint32(&o.SRAM_ACE3_SIZE.Reg)&^(0xffff)|value) +} +func (o *APB_CTRL_Type) GetSRAM_ACE3_SIZE() uint32 { + return volatile.LoadUint32(&o.SRAM_ACE3_SIZE.Reg) & 0xffff +} + +// APB_CTRL.SPI_MEM_PMS_CTRL: ******* Description *********** +func (o *APB_CTRL_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_PMS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg)&^(0x7c)|value<<2) +} +func (o *APB_CTRL_Type) GetSPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_PMS_CTRL.Reg) & 0x7c) >> 2 +} + +// APB_CTRL.SPI_MEM_REJECT_ADDR: ******* Description *********** +func (o *APB_CTRL_Type) SetSPI_MEM_REJECT_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REJECT_ADDR.Reg, value) +} +func (o *APB_CTRL_Type) GetSPI_MEM_REJECT_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REJECT_ADDR.Reg) +} + +// APB_CTRL.SDIO_CTRL: ******* Description *********** +func (o *APB_CTRL_Type) SetSDIO_CTRL_SDIO_WIN_ACCESS_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_CTRL.Reg, volatile.LoadUint32(&o.SDIO_CTRL.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetSDIO_CTRL_SDIO_WIN_ACCESS_EN() uint32 { + return volatile.LoadUint32(&o.SDIO_CTRL.Reg) & 0x1 +} + +// APB_CTRL.REDCY_SIG0: ******* Description *********** +func (o *APB_CTRL_Type) SetREDCY_SIG0(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG0.Reg, volatile.LoadUint32(&o.REDCY_SIG0.Reg)&^(0x7fffffff)|value) +} +func (o *APB_CTRL_Type) GetREDCY_SIG0() uint32 { + return volatile.LoadUint32(&o.REDCY_SIG0.Reg) & 0x7fffffff +} +func (o *APB_CTRL_Type) SetREDCY_SIG0_REDCY_ANDOR(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG0.Reg, volatile.LoadUint32(&o.REDCY_SIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetREDCY_SIG0_REDCY_ANDOR() uint32 { + return (volatile.LoadUint32(&o.REDCY_SIG0.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.REDCY_SIG1: ******* Description *********** +func (o *APB_CTRL_Type) SetREDCY_SIG1(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG1.Reg, volatile.LoadUint32(&o.REDCY_SIG1.Reg)&^(0x7fffffff)|value) +} +func (o *APB_CTRL_Type) GetREDCY_SIG1() uint32 { + return volatile.LoadUint32(&o.REDCY_SIG1.Reg) & 0x7fffffff +} +func (o *APB_CTRL_Type) SetREDCY_SIG1_REDCY_NANDOR(value uint32) { + volatile.StoreUint32(&o.REDCY_SIG1.Reg, volatile.LoadUint32(&o.REDCY_SIG1.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetREDCY_SIG1_REDCY_NANDOR() uint32 { + return (volatile.LoadUint32(&o.REDCY_SIG1.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.FRONT_END_MEM_PD: ******* Description *********** +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PU() uint32 { + return volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x1 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x2)|value<<1) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_AGC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x2) >> 1 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x4)|value<<2) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x4) >> 2 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x8)|value<<3) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_PBUS_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x8) >> 3 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_DC_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x10)|value<<4) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_DC_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x10) >> 4 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_DC_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x20)|value<<5) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_DC_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x20) >> 5 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_FREQ_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x40)|value<<6) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_FREQ_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x40) >> 6 +} +func (o *APB_CTRL_Type) SetFRONT_END_MEM_PD_FREQ_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.FRONT_END_MEM_PD.Reg, volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg)&^(0x80)|value<<7) +} +func (o *APB_CTRL_Type) GetFRONT_END_MEM_PD_FREQ_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.FRONT_END_MEM_PD.Reg) & 0x80) >> 7 +} + +// APB_CTRL.SPI_MEM_ECC_CTRL: ******* Description *********** +func (o *APB_CTRL_Type) SetSPI_MEM_ECC_CTRL_FLASH_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0xc0000)|value<<18) +} +func (o *APB_CTRL_Type) GetSPI_MEM_ECC_CTRL_FLASH_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0xc0000) >> 18 +} +func (o *APB_CTRL_Type) SetSPI_MEM_ECC_CTRL_SRAM_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x300000)|value<<20) +} +func (o *APB_CTRL_Type) GetSPI_MEM_ECC_CTRL_SRAM_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x300000) >> 20 +} + +// APB_CTRL.CLKGATE_FORCE_ON: ******* Description *********** +func (o *APB_CTRL_Type) SetCLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLKGATE_FORCE_ON.Reg, volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg)&^(0x7)|value) +} +func (o *APB_CTRL_Type) GetCLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg) & 0x7 +} +func (o *APB_CTRL_Type) SetCLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLKGATE_FORCE_ON.Reg, volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg)&^(0x3ff8)|value<<3) +} +func (o *APB_CTRL_Type) GetCLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLKGATE_FORCE_ON.Reg) & 0x3ff8) >> 3 +} + +// APB_CTRL.MEM_POWER_DOWN: ******* Description *********** +func (o *APB_CTRL_Type) SetMEM_POWER_DOWN_ROM_POWER_DOWN(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_DOWN.Reg, volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg)&^(0x7)|value) +} +func (o *APB_CTRL_Type) GetMEM_POWER_DOWN_ROM_POWER_DOWN() uint32 { + return volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg) & 0x7 +} +func (o *APB_CTRL_Type) SetMEM_POWER_DOWN_SRAM_POWER_DOWN(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_DOWN.Reg, volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg)&^(0x3ff8)|value<<3) +} +func (o *APB_CTRL_Type) GetMEM_POWER_DOWN_SRAM_POWER_DOWN() uint32 { + return (volatile.LoadUint32(&o.MEM_POWER_DOWN.Reg) & 0x3ff8) >> 3 +} + +// APB_CTRL.MEM_POWER_UP: ******* Description *********** +func (o *APB_CTRL_Type) SetMEM_POWER_UP_ROM_POWER_UP(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_UP.Reg, volatile.LoadUint32(&o.MEM_POWER_UP.Reg)&^(0x7)|value) +} +func (o *APB_CTRL_Type) GetMEM_POWER_UP_ROM_POWER_UP() uint32 { + return volatile.LoadUint32(&o.MEM_POWER_UP.Reg) & 0x7 +} +func (o *APB_CTRL_Type) SetMEM_POWER_UP_SRAM_POWER_UP(value uint32) { + volatile.StoreUint32(&o.MEM_POWER_UP.Reg, volatile.LoadUint32(&o.MEM_POWER_UP.Reg)&^(0x3ff8)|value<<3) +} +func (o *APB_CTRL_Type) GetMEM_POWER_UP_SRAM_POWER_UP() uint32 { + return (volatile.LoadUint32(&o.MEM_POWER_UP.Reg) & 0x3ff8) >> 3 +} + +// APB_CTRL.RETENTION_CTRL: ******* Description *********** +func (o *APB_CTRL_Type) SetRETENTION_CTRL_RETENTION_CPU_LINK_ADDR(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x7ffffff)|value) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL_RETENTION_CPU_LINK_ADDR() uint32 { + return volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x7ffffff +} +func (o *APB_CTRL_Type) SetRETENTION_CTRL_NOBYPASS_CPU_ISO_RST(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL_NOBYPASS_CPU_ISO_RST() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x8000000) >> 27 +} + +// APB_CTRL.RETENTION_CTRL1: ******* Description *********** +func (o *APB_CTRL_Type) SetRETENTION_CTRL1_RETENTION_TAG_LINK_ADDR(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL1.Reg, volatile.LoadUint32(&o.RETENTION_CTRL1.Reg)&^(0x7ffffff)|value) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL1_RETENTION_TAG_LINK_ADDR() uint32 { + return volatile.LoadUint32(&o.RETENTION_CTRL1.Reg) & 0x7ffffff +} + +// APB_CTRL.RETENTION_CTRL2: ******* Description *********** +func (o *APB_CTRL_Type) SetRETENTION_CTRL2_RET_ICACHE_SIZE(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL2.Reg, volatile.LoadUint32(&o.RETENTION_CTRL2.Reg)&^(0xff0)|value<<4) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL2_RET_ICACHE_SIZE() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL2.Reg) & 0xff0) >> 4 +} +func (o *APB_CTRL_Type) SetRETENTION_CTRL2_RET_ICACHE_VLD_SIZE(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL2.Reg, volatile.LoadUint32(&o.RETENTION_CTRL2.Reg)&^(0x1fe000)|value<<13) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL2_RET_ICACHE_VLD_SIZE() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL2.Reg) & 0x1fe000) >> 13 +} +func (o *APB_CTRL_Type) SetRETENTION_CTRL2_RET_ICACHE_START_POINT(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL2.Reg, volatile.LoadUint32(&o.RETENTION_CTRL2.Reg)&^(0x3fc00000)|value<<22) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL2_RET_ICACHE_START_POINT() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL2.Reg) & 0x3fc00000) >> 22 +} +func (o *APB_CTRL_Type) SetRETENTION_CTRL2_RET_ICACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL2.Reg, volatile.LoadUint32(&o.RETENTION_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL2_RET_ICACHE_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL2.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.RETENTION_CTRL3: ******* Description *********** +func (o *APB_CTRL_Type) SetRETENTION_CTRL3_RET_DCACHE_SIZE(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL3.Reg, volatile.LoadUint32(&o.RETENTION_CTRL3.Reg)&^(0x1ff0)|value<<4) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL3_RET_DCACHE_SIZE() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL3.Reg) & 0x1ff0) >> 4 +} +func (o *APB_CTRL_Type) SetRETENTION_CTRL3_RET_DCACHE_VLD_SIZE(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL3.Reg, volatile.LoadUint32(&o.RETENTION_CTRL3.Reg)&^(0x3fe000)|value<<13) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL3_RET_DCACHE_VLD_SIZE() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL3.Reg) & 0x3fe000) >> 13 +} +func (o *APB_CTRL_Type) SetRETENTION_CTRL3_RET_DCACHE_START_POINT(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL3.Reg, volatile.LoadUint32(&o.RETENTION_CTRL3.Reg)&^(0x7fc00000)|value<<22) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL3_RET_DCACHE_START_POINT() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL3.Reg) & 0x7fc00000) >> 22 +} +func (o *APB_CTRL_Type) SetRETENTION_CTRL3_RET_DCACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL3.Reg, volatile.LoadUint32(&o.RETENTION_CTRL3.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL3_RET_DCACHE_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL3.Reg) & 0x80000000) >> 31 +} + +// APB_CTRL.RETENTION_CTRL4: ******* Description *********** +func (o *APB_CTRL_Type) SetRETENTION_CTRL4(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL4.Reg, value) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL4() uint32 { + return volatile.LoadUint32(&o.RETENTION_CTRL4.Reg) +} + +// APB_CTRL.RETENTION_CTRL5: ******* Description *********** +func (o *APB_CTRL_Type) SetRETENTION_CTRL5_RETENTION_DISABLE(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL5.Reg, volatile.LoadUint32(&o.RETENTION_CTRL5.Reg)&^(0x1)|value) +} +func (o *APB_CTRL_Type) GetRETENTION_CTRL5_RETENTION_DISABLE() uint32 { + return volatile.LoadUint32(&o.RETENTION_CTRL5.Reg) & 0x1 +} + +// APB_CTRL.DATE: ******* Description *********** +func (o *APB_CTRL_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *APB_CTRL_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// SAR (Successive Approximation Register) Analog-to-Digital Converter +type APB_SARADC_Type struct { + CTRL volatile.Register32 // 0x0 + CTRL2 volatile.Register32 // 0x4 + FILTER_CTRL1 volatile.Register32 // 0x8 + FSM_WAIT volatile.Register32 // 0xC + SAR1_STATUS volatile.Register32 // 0x10 + SAR2_STATUS volatile.Register32 // 0x14 + SAR1_PATT_TAB1 volatile.Register32 // 0x18 + SAR1_PATT_TAB2 volatile.Register32 // 0x1C + SAR1_PATT_TAB3 volatile.Register32 // 0x20 + SAR1_PATT_TAB4 volatile.Register32 // 0x24 + SAR2_PATT_TAB1 volatile.Register32 // 0x28 + SAR2_PATT_TAB2 volatile.Register32 // 0x2C + SAR2_PATT_TAB3 volatile.Register32 // 0x30 + SAR2_PATT_TAB4 volatile.Register32 // 0x34 + ARB_CTRL volatile.Register32 // 0x38 + FILTER_CTRL0 volatile.Register32 // 0x3C + APB_SARADC1_DATA_STATUS volatile.Register32 // 0x40 + THRES0_CTRL volatile.Register32 // 0x44 + THRES1_CTRL volatile.Register32 // 0x48 + _ [12]byte + THRES_CTRL volatile.Register32 // 0x58 + INT_ENA volatile.Register32 // 0x5C + INT_RAW volatile.Register32 // 0x60 + INT_ST volatile.Register32 // 0x64 + INT_CLR volatile.Register32 // 0x68 + DMA_CONF volatile.Register32 // 0x6C + CLKM_CONF volatile.Register32 // 0x70 + _ [4]byte + APB_SARADC2_DATA_STATUS volatile.Register32 // 0x78 + _ [896]byte + APB_CTRL_DATE volatile.Register32 // 0x3FC +} + +// APB_SARADC.CTRL: configure apb saradc controller +func (o *APB_SARADC_Type) SetCTRL_SARADC_START_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START_FORCE() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_WORK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x18)|value<<3) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_WORK_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x18) >> 3 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x7f80)|value<<7) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x7f80) >> 7 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR1_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x78000)|value<<15) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR1_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x78000) >> 15 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR2_PATT_LEN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x780000)|value<<19) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR2_PATT_LEN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x780000) >> 19 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR1_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR1_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_SAR2_PATT_P_CLEAR(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_SAR2_PATT_P_CLEAR() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_DATA_SAR_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_DATA_SAR_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000000) >> 25 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_DATA_TO_I2S(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_DATA_TO_I2S() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_XPD_SAR_FORCE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x18000000)|value<<27) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_XPD_SAR_FORCE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x18000000) >> 27 +} +func (o *APB_SARADC_Type) SetCTRL_SARADC_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc0000000)|value<<30) +} +func (o *APB_SARADC_Type) GetCTRL_SARADC_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc0000000) >> 30 +} + +// APB_SARADC.CTRL2: configure apb saradc controller +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MEAS_NUM_LIMIT(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1)|value) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MEAS_NUM_LIMIT() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_MAX_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1fe)|value<<1) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_MAX_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1fe) >> 1 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR1_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR1_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x200) >> 9 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_SAR2_INV(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x400)|value<<10) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_SAR2_INV() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x400) >> 10 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x800)|value<<11) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_SEL() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x800) >> 11 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff000)|value<<12) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_TARGET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff000) >> 12 +} +func (o *APB_SARADC_Type) SetCTRL2_SARADC_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1000000)|value<<24) +} +func (o *APB_SARADC_Type) GetCTRL2_SARADC_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1000000) >> 24 +} + +// APB_SARADC.FILTER_CTRL1: configure saradc filter +func (o *APB_SARADC_Type) SetFILTER_CTRL1_FILTER_FACTOR1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0x1c000000)|value<<26) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_FILTER_FACTOR1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0x1c000000) >> 26 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL1_FILTER_FACTOR0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0xe0000000)|value<<29) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL1_FILTER_FACTOR0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0xe0000000) >> 29 +} + +// APB_SARADC.FSM_WAIT: configure apb saradc fsm +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff00)|value<<8) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff00) >> 8 +} +func (o *APB_SARADC_Type) SetFSM_WAIT_SARADC_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff0000)|value<<16) +} +func (o *APB_SARADC_Type) GetFSM_WAIT_SARADC_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff0000) >> 16 +} + +// APB_SARADC.SAR1_STATUS: saradc1 status for debug +func (o *APB_SARADC_Type) SetSAR1_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR1_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR1_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR1_STATUS.Reg) +} + +// APB_SARADC.SAR2_STATUS: saradc2 status for debug +func (o *APB_SARADC_Type) SetSAR2_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR2_STATUS.Reg, value) +} +func (o *APB_SARADC_Type) GetSAR2_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR2_STATUS.Reg) +} + +// APB_SARADC.SAR1_PATT_TAB1: configure apb saradc pattern table +func (o *APB_SARADC_Type) SetSAR1_PATT_TAB1_SARADC_SAR1_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB1.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR1_PATT_TAB1_SARADC_SAR1_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB1.Reg) & 0xffffff +} + +// APB_SARADC.SAR1_PATT_TAB2: configure apb saradc pattern table +func (o *APB_SARADC_Type) SetSAR1_PATT_TAB2_SARADC_SAR1_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB2.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR1_PATT_TAB2_SARADC_SAR1_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB2.Reg) & 0xffffff +} + +// APB_SARADC.SAR1_PATT_TAB3: configure apb saradc pattern table +func (o *APB_SARADC_Type) SetSAR1_PATT_TAB3_SARADC_SAR1_PATT_TAB3(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB3.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB3.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR1_PATT_TAB3_SARADC_SAR1_PATT_TAB3() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB3.Reg) & 0xffffff +} + +// APB_SARADC.SAR1_PATT_TAB4: configure apb saradc pattern table +func (o *APB_SARADC_Type) SetSAR1_PATT_TAB4_SARADC_SAR1_PATT_TAB4(value uint32) { + volatile.StoreUint32(&o.SAR1_PATT_TAB4.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB4.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR1_PATT_TAB4_SARADC_SAR1_PATT_TAB4() uint32 { + return volatile.LoadUint32(&o.SAR1_PATT_TAB4.Reg) & 0xffffff +} + +// APB_SARADC.SAR2_PATT_TAB1: configure apb saradc pattern table +func (o *APB_SARADC_Type) SetSAR2_PATT_TAB1_SARADC_SAR2_PATT_TAB1(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB1.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR2_PATT_TAB1_SARADC_SAR2_PATT_TAB1() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB1.Reg) & 0xffffff +} + +// APB_SARADC.SAR2_PATT_TAB2: configure apb saradc pattern table +func (o *APB_SARADC_Type) SetSAR2_PATT_TAB2_SARADC_SAR2_PATT_TAB2(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB2.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR2_PATT_TAB2_SARADC_SAR2_PATT_TAB2() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB2.Reg) & 0xffffff +} + +// APB_SARADC.SAR2_PATT_TAB3: configure apb saradc pattern table +func (o *APB_SARADC_Type) SetSAR2_PATT_TAB3_SARADC_SAR2_PATT_TAB3(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB3.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB3.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR2_PATT_TAB3_SARADC_SAR2_PATT_TAB3() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB3.Reg) & 0xffffff +} + +// APB_SARADC.SAR2_PATT_TAB4: configure apb saradc pattern table +func (o *APB_SARADC_Type) SetSAR2_PATT_TAB4_SARADC_SAR2_PATT_TAB4(value uint32) { + volatile.StoreUint32(&o.SAR2_PATT_TAB4.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB4.Reg)&^(0xffffff)|value) +} +func (o *APB_SARADC_Type) GetSAR2_PATT_TAB4_SARADC_SAR2_PATT_TAB4() uint32 { + return volatile.LoadUint32(&o.SAR2_PATT_TAB4.Reg) & 0xffffff +} + +// APB_SARADC.ARB_CTRL: configure apb saradc arbit +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x4) >> 2 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x8) >> 3 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x10) >> 4 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_GRANT_FORCE(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_GRANT_FORCE() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x20) >> 5 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_APB_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc0)|value<<6) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_APB_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc0) >> 6 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_RTC_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x300)|value<<8) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_RTC_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x300) >> 8 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_WIFI_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc00)|value<<10) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_WIFI_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc00) >> 10 +} +func (o *APB_SARADC_Type) SetARB_CTRL_ADC_ARB_FIX_PRIORITY(value uint32) { + volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *APB_SARADC_Type) GetARB_CTRL_ADC_ARB_FIX_PRIORITY() uint32 { + return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x1000) >> 12 +} + +// APB_SARADC.FILTER_CTRL0: configure apb saradc arbit +func (o *APB_SARADC_Type) SetFILTER_CTRL0_FILTER_CHANNEL1(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x7c000)|value<<14) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_FILTER_CHANNEL1() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x7c000) >> 14 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_FILTER_CHANNEL0(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0xf80000)|value<<19) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_FILTER_CHANNEL0() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0xf80000) >> 19 +} +func (o *APB_SARADC_Type) SetFILTER_CTRL0_FILTER_RESET(value uint32) { + volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetFILTER_CTRL0_FILTER_RESET() uint32 { + return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.APB_SARADC1_DATA_STATUS: get apb saradc sample data +func (o *APB_SARADC_Type) SetAPB_SARADC1_DATA_STATUS_APB_SARADC1_DATA(value uint32) { + volatile.StoreUint32(&o.APB_SARADC1_DATA_STATUS.Reg, volatile.LoadUint32(&o.APB_SARADC1_DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetAPB_SARADC1_DATA_STATUS_APB_SARADC1_DATA() uint32 { + return volatile.LoadUint32(&o.APB_SARADC1_DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.THRES0_CTRL: configure apb saradc thres monitor +func (o *APB_SARADC_Type) SetTHRES0_CTRL_THRES0_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x1f)|value) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_THRES0_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x1f +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_THRES0_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_THRES0_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES0_CTRL_THRES0_LOW(value uint32) { + volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES0_CTRL_THRES0_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES1_CTRL: configure apb saradc thres monitor +func (o *APB_SARADC_Type) SetTHRES1_CTRL_THRES1_CHANNEL(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x1f)|value) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_THRES1_CHANNEL() uint32 { + return volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x1f +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_THRES1_HIGH(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x3ffe0)|value<<5) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_THRES1_HIGH() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x3ffe0) >> 5 +} +func (o *APB_SARADC_Type) SetTHRES1_CTRL_THRES1_LOW(value uint32) { + volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *APB_SARADC_Type) GetTHRES1_CTRL_THRES1_LOW() uint32 { + return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x7ffc0000) >> 18 +} + +// APB_SARADC.THRES_CTRL: configure thres monitor enable +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES_ALL_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES_ALL_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES3_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES3_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES2_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES2_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetTHRES_CTRL_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetTHRES_CTRL_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ENA: enable interrupt +func (o *APB_SARADC_Type) SetINT_ENA_THRES1_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ENA_THRES1_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ENA_THRES0_LOW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ENA_THRES0_LOW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ENA_THRES1_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ENA_THRES1_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ENA_THRES0_HIGH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ENA_THRES0_HIGH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC2_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC2_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ENA_APB_SARADC1_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ENA_APB_SARADC1_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_RAW: raw of interrupt +func (o *APB_SARADC_Type) SetINT_RAW_THRES1_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_RAW_THRES1_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_RAW_THRES0_LOW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_RAW_THRES0_LOW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_RAW_THRES1_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_RAW_THRES1_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_RAW_THRES0_HIGH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_RAW_THRES0_HIGH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC2_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC2_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_RAW_APB_SARADC1_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_RAW_APB_SARADC1_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_ST: state of interrupt +func (o *APB_SARADC_Type) SetINT_ST_THRES1_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_ST_THRES1_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_ST_THRES0_LOW_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_ST_THRES0_LOW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_ST_THRES1_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_ST_THRES1_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_ST_THRES0_HIGH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_ST_THRES0_HIGH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC2_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC2_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_ST_APB_SARADC1_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_ST_APB_SARADC1_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.INT_CLR: clear interrupt +func (o *APB_SARADC_Type) SetINT_CLR_THRES1_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *APB_SARADC_Type) GetINT_CLR_THRES1_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *APB_SARADC_Type) SetINT_CLR_THRES0_LOW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *APB_SARADC_Type) GetINT_CLR_THRES0_LOW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *APB_SARADC_Type) SetINT_CLR_THRES1_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *APB_SARADC_Type) GetINT_CLR_THRES1_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *APB_SARADC_Type) SetINT_CLR_THRES0_HIGH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *APB_SARADC_Type) GetINT_CLR_THRES0_HIGH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC2_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC2_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetINT_CLR_APB_SARADC1_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetINT_CLR_APB_SARADC1_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.DMA_CONF: configure apb saradc dma +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0xffff)|value) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0xffff +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_RESET_FSM(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_RESET_FSM() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *APB_SARADC_Type) SetDMA_CONF_APB_ADC_TRANS(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *APB_SARADC_Type) GetDMA_CONF_APB_ADC_TRANS() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// APB_SARADC.CLKM_CONF: configure apb saradc clock +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xff +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x3f00) >> 8 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0xfc000) >> 14 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x100000) >> 20 +} +func (o *APB_SARADC_Type) SetCLKM_CONF_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLKM_CONF.Reg, volatile.LoadUint32(&o.CLKM_CONF.Reg)&^(0x600000)|value<<21) +} +func (o *APB_SARADC_Type) GetCLKM_CONF_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLKM_CONF.Reg) & 0x600000) >> 21 +} + +// APB_SARADC.APB_SARADC2_DATA_STATUS: get apb saradc2 sample data +func (o *APB_SARADC_Type) SetAPB_SARADC2_DATA_STATUS_APB_SARADC2_DATA(value uint32) { + volatile.StoreUint32(&o.APB_SARADC2_DATA_STATUS.Reg, volatile.LoadUint32(&o.APB_SARADC2_DATA_STATUS.Reg)&^(0x1ffff)|value) +} +func (o *APB_SARADC_Type) GetAPB_SARADC2_DATA_STATUS_APB_SARADC2_DATA() uint32 { + return volatile.LoadUint32(&o.APB_SARADC2_DATA_STATUS.Reg) & 0x1ffff +} + +// APB_SARADC.APB_CTRL_DATE: version +func (o *APB_SARADC_Type) SetAPB_CTRL_DATE(value uint32) { + volatile.StoreUint32(&o.APB_CTRL_DATE.Reg, value) +} +func (o *APB_SARADC_Type) GetAPB_CTRL_DATE() uint32 { + return volatile.LoadUint32(&o.APB_CTRL_DATE.Reg) +} + +// BB Peripheral +type BB_Type struct { + _ [84]byte + BBPD_CTRL volatile.Register32 // 0x54 +} + +// BB.BBPD_CTRL: Baseband control register +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x1)|value) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x1 +} +func (o *BB_Type) SetBBPD_CTRL_DC_EST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *BB_Type) GetBBPD_CTRL_DC_EST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x2) >> 1 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x4) >> 2 +} +func (o *BB_Type) SetBBPD_CTRL_FFT_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.BBPD_CTRL.Reg, volatile.LoadUint32(&o.BBPD_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *BB_Type) GetBBPD_CTRL_FFT_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.BBPD_CTRL.Reg) & 0x8) >> 3 +} + +// Debug Assist +type DEBUG_ASSIST_Type struct { + CORE_0_MONTR_ENA volatile.Register32 // 0x0 + CORE_0_INTR_RAW volatile.Register32 // 0x4 + CORE_0_INTR_ENA volatile.Register32 // 0x8 + CORE_0_INTR_CLR volatile.Register32 // 0xC + CORE_0_AREA_DRAM0_0_MIN volatile.Register32 // 0x10 + CORE_0_AREA_DRAM0_0_MAX volatile.Register32 // 0x14 + CORE_0_AREA_DRAM0_1_MIN volatile.Register32 // 0x18 + CORE_0_AREA_DRAM0_1_MAX volatile.Register32 // 0x1C + CORE_0_AREA_PIF_0_MIN volatile.Register32 // 0x20 + CORE_0_AREA_PIF_0_MAX volatile.Register32 // 0x24 + CORE_0_AREA_PIF_1_MIN volatile.Register32 // 0x28 + CORE_0_AREA_PIF_1_MAX volatile.Register32 // 0x2C + CORE_0_AREA_SP volatile.Register32 // 0x30 + CORE_0_AREA_PC volatile.Register32 // 0x34 + CORE_0_SP_UNSTABLE volatile.Register32 // 0x38 + CORE_0_SP_MIN volatile.Register32 // 0x3C + CORE_0_SP_MAX volatile.Register32 // 0x40 + CORE_0_SP_PC volatile.Register32 // 0x44 + CORE_0_RCD_PDEBUGENABLE volatile.Register32 // 0x48 + CORE_0_RCD_RECORDING volatile.Register32 // 0x4C + CORE_0_RCD_PDEBUGINST volatile.Register32 // 0x50 + CORE_0_RCD_PDEBUGSTATUS volatile.Register32 // 0x54 + CORE_0_RCD_PDEBUGDATA volatile.Register32 // 0x58 + CORE_0_RCD_PDEBUGPC volatile.Register32 // 0x5C + CORE_0_RCD_PDEBUGLS0STAT volatile.Register32 // 0x60 + CORE_0_RCD_PDEBUGLS0ADDR volatile.Register32 // 0x64 + CORE_0_RCD_PDEBUGLS0DATA volatile.Register32 // 0x68 + CORE_0_RCD_SP volatile.Register32 // 0x6C + CORE_0_IRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x70 + CORE_0_IRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x74 + CORE_0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x78 + CORE_0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x7C + CORE_0_DRAM0_EXCEPTION_MONITOR_2 volatile.Register32 // 0x80 + CORE_0_DRAM0_EXCEPTION_MONITOR_3 volatile.Register32 // 0x84 + CORE_0_DRAM0_EXCEPTION_MONITOR_4 volatile.Register32 // 0x88 + CORE_0_DRAM0_EXCEPTION_MONITOR_5 volatile.Register32 // 0x8C + CORE_1_MONTR_ENA volatile.Register32 // 0x90 + CORE_1_INTR_RAW volatile.Register32 // 0x94 + CORE_1_INTR_ENA volatile.Register32 // 0x98 + CORE_1_INTR_CLR volatile.Register32 // 0x9C + CORE_1_AREA_DRAM0_0_MIN volatile.Register32 // 0xA0 + CORE_1_AREA_DRAM0_0_MAX volatile.Register32 // 0xA4 + CORE_1_AREA_DRAM0_1_MIN volatile.Register32 // 0xA8 + CORE_1_AREA_DRAM0_1_MAX volatile.Register32 // 0xAC + CORE_1_AREA_PIF_0_MIN volatile.Register32 // 0xB0 + CORE_1_AREA_PIF_0_MAX volatile.Register32 // 0xB4 + CORE_1_AREA_PIF_1_MIN volatile.Register32 // 0xB8 + CORE_1_AREA_PIF_1_MAX volatile.Register32 // 0xBC + CORE_1_AREA_PC volatile.Register32 // 0xC0 + CORE_1_AREA_SP volatile.Register32 // 0xC4 + CORE_1_SP_UNSTABLE volatile.Register32 // 0xC8 + CORE_1_SP_MIN volatile.Register32 // 0xCC + CORE_1_SP_MAX volatile.Register32 // 0xD0 + CORE_1_SP_PC volatile.Register32 // 0xD4 + CORE_1_RCD_PDEBUGENABLE volatile.Register32 // 0xD8 + CORE_1_RCD_RECORDING volatile.Register32 // 0xDC + CORE_1_RCD_PDEBUGINST volatile.Register32 // 0xE0 + CORE_1_RCD_PDEBUGSTATUS volatile.Register32 // 0xE4 + CORE_1_RCD_PDEBUGDATA volatile.Register32 // 0xE8 + CORE_1_RCD_PDEBUGPC volatile.Register32 // 0xEC + CORE_1_RCD_PDEBUGLS0STAT volatile.Register32 // 0xF0 + CORE_1_RCD_PDEBUGLS0ADDR volatile.Register32 // 0xF4 + CORE_1_RCD_PDEBUGLS0DATA volatile.Register32 // 0xF8 + CORE_1_RCD_SP volatile.Register32 // 0xFC + CORE_1_IRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x100 + CORE_1_IRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x104 + CORE_1_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x108 + CORE_1_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x10C + CORE_1_DRAM0_EXCEPTION_MONITOR_2 volatile.Register32 // 0x110 + CORE_1_DRAM0_EXCEPTION_MONITOR_3 volatile.Register32 // 0x114 + CORE_1_DRAM0_EXCEPTION_MONITOR_4 volatile.Register32 // 0x118 + CORE_1_DRAM0_EXCEPTION_MONITOR_5 volatile.Register32 // 0x11C + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x120 + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x124 + LOG_SETTING volatile.Register32 // 0x128 + LOG_DATA_0 volatile.Register32 // 0x12C + LOG_DATA_1 volatile.Register32 // 0x130 + LOG_DATA_2 volatile.Register32 // 0x134 + LOG_DATA_3 volatile.Register32 // 0x138 + LOG_DATA_MASK volatile.Register32 // 0x13C + LOG_MIN volatile.Register32 // 0x140 + LOG_MAX volatile.Register32 // 0x144 + LOG_MEM_START volatile.Register32 // 0x148 + LOG_MEM_END volatile.Register32 // 0x14C + LOG_MEM_WRITING_ADDR volatile.Register32 // 0x150 + LOG_MEM_FULL_FLAG volatile.Register32 // 0x154 + _ [164]byte + DATE volatile.Register32 // 0x1FC +} + +// DEBUG_ASSIST.CORE_0_MONTR_ENA: core0 monitor enable configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x2) >> 1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x4) >> 2 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x8) >> 3 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x10) >> 4 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x20) >> 5 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x40) >> 6 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x80) >> 7 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x100) >> 8 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x200) >> 9 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x400) >> 10 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_MONTR_ENA.Reg) & 0x800) >> 11 +} + +// DEBUG_ASSIST.CORE_0_INTR_RAW: core0 monitor interrupt status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x2) >> 1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x4)|value<<2) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x4) >> 2 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x8)|value<<3) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x8) >> 3 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x10)|value<<4) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x10) >> 4 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x20)|value<<5) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x20) >> 5 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x40)|value<<6) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x40) >> 6 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x80)|value<<7) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x80) >> 7 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x100)|value<<8) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x100) >> 8 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x200)|value<<9) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x200) >> 9 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x400)|value<<10) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x400) >> 10 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x800)|value<<11) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x800) >> 11 +} + +// DEBUG_ASSIST.CORE_0_INTR_ENA: core0 monitor interrupt enable register +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x2) >> 1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x4) >> 2 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x8) >> 3 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x10) >> 4 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x20) >> 5 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x40) >> 6 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x80) >> 7 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x100) >> 8 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x200) >> 9 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x400) >> 10 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x800) >> 11 +} + +// DEBUG_ASSIST.CORE_0_INTR_CLR: core0 monitor interrupt clr register +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x2) >> 1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x4)|value<<2) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x4) >> 2 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x8)|value<<3) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x8) >> 3 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x10)|value<<4) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x10) >> 4 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x20)|value<<5) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x20) >> 5 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x40)|value<<6) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x40) >> 6 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x80)|value<<7) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x80) >> 7 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x100)|value<<8) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x100) >> 8 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x200)|value<<9) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x200) >> 9 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x400)|value<<10) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x400) >> 10 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x800)|value<<11) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x800) >> 11 +} + +// DEBUG_ASSIST.CORE_0_AREA_DRAM0_0_MIN: core0 dram0 region0 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_DRAM0_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_DRAM0_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_0_AREA_DRAM0_0_MAX: core0 dram0 region0 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_DRAM0_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_DRAM0_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_0_AREA_DRAM0_1_MIN: core0 dram0 region1 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_DRAM0_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_DRAM0_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_0_AREA_DRAM0_1_MAX: core0 dram0 region1 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_DRAM0_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_DRAM0_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_0_AREA_PIF_0_MIN: core0 PIF region0 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_PIF_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_PIF_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_0_AREA_PIF_0_MAX: core0 PIF region0 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_PIF_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_PIF_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_0_AREA_PIF_1_MIN: core0 PIF region1 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_PIF_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_PIF_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_0_AREA_PIF_1_MAX: core0 PIF region1 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_PIF_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_PIF_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_0_AREA_SP: core0 area sp status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_SP(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_SP.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_SP() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_SP.Reg) +} + +// DEBUG_ASSIST.CORE_0_AREA_PC: core0 area pc status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_AREA_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_AREA_PC.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_AREA_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_AREA_PC.Reg) +} + +// DEBUG_ASSIST.CORE_0_SP_UNSTABLE: core0 sp unstable configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_SP_UNSTABLE(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_UNSTABLE.Reg, volatile.LoadUint32(&o.CORE_0_SP_UNSTABLE.Reg)&^(0xff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_SP_UNSTABLE() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_UNSTABLE.Reg) & 0xff +} + +// DEBUG_ASSIST.CORE_0_SP_MIN: core0 sp region configuration regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_SP_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_SP_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_0_SP_MAX: core0 sp region configuration regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_SP_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_SP_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_0_SP_PC: core0 sp pc status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_SP_PC(value uint32) { + volatile.StoreUint32(&o.CORE_0_SP_PC.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_SP_PC() uint32 { + return volatile.LoadUint32(&o.CORE_0_SP_PC.Reg) +} + +// DEBUG_ASSIST.CORE_0_RCD_PDEBUGENABLE: core0 pdebug configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_PDEBUGENABLE(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGENABLE.Reg, volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGENABLE.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_PDEBUGENABLE() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGENABLE.Reg) & 0x1 +} + +// DEBUG_ASSIST.CORE_0_RCD_RECORDING: core0 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_RECORDING(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_RECORDING.Reg, volatile.LoadUint32(&o.CORE_0_RCD_RECORDING.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_RECORDING() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_RECORDING.Reg) & 0x1 +} + +// DEBUG_ASSIST.CORE_0_RCD_PDEBUGINST: core0 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_PDEBUGINST(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGINST.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_PDEBUGINST() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGINST.Reg) +} + +// DEBUG_ASSIST.CORE_0_RCD_PDEBUGSTATUS: core0 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_PDEBUGSTATUS(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGSTATUS.Reg, volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGSTATUS.Reg)&^(0xff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_PDEBUGSTATUS() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGSTATUS.Reg) & 0xff +} + +// DEBUG_ASSIST.CORE_0_RCD_PDEBUGDATA: core0 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_PDEBUGDATA(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGDATA.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_PDEBUGDATA() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGDATA.Reg) +} + +// DEBUG_ASSIST.CORE_0_RCD_PDEBUGPC: core0 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGPC.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGPC.Reg) +} + +// DEBUG_ASSIST.CORE_0_RCD_PDEBUGLS0STAT: core0 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_PDEBUGLS0STAT(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGLS0STAT.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_PDEBUGLS0STAT() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGLS0STAT.Reg) +} + +// DEBUG_ASSIST.CORE_0_RCD_PDEBUGLS0ADDR: core0 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_PDEBUGLS0ADDR(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGLS0ADDR.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_PDEBUGLS0ADDR() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGLS0ADDR.Reg) +} + +// DEBUG_ASSIST.CORE_0_RCD_PDEBUGLS0DATA: core0 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_PDEBUGLS0DATA(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGLS0DATA.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_PDEBUGLS0DATA() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGLS0DATA.Reg) +} + +// DEBUG_ASSIST.CORE_0_RCD_SP: core0 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_0_RCD_SP(value uint32) { + volatile.StoreUint32(&o.CORE_0_RCD_SP.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_RCD_SP() uint32 { + return volatile.LoadUint32(&o.CORE_0_RCD_SP.Reg) +} + +// DEBUG_ASSIST.CORE_0_IRAM0_EXCEPTION_MONITOR_0: core0 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x2000000)|value<<25) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x2000000) >> 25 +} + +// DEBUG_ASSIST.CORE_0_IRAM0_EXCEPTION_MONITOR_1: core0 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x1000000)|value<<24) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x1000000) >> 24 +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x2000000)|value<<25) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x2000000) >> 25 +} + +// DEBUG_ASSIST.CORE_0_DRAM0_EXCEPTION_MONITOR_0: core0 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x3fffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x3fffff +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x400000)|value<<22) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x400000) >> 22 +} + +// DEBUG_ASSIST.CORE_0_DRAM0_EXCEPTION_MONITOR_1: core0 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_BYTEEN_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_BYTEEN_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffff +} + +// DEBUG_ASSIST.CORE_0_DRAM0_EXCEPTION_MONITOR_2: core0 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg) +} + +// DEBUG_ASSIST.CORE_0_DRAM0_EXCEPTION_MONITOR_3: core0 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x3fffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x3fffff +} +func (o *DEBUG_ASSIST_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x400000)|value<<22) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x400000) >> 22 +} + +// DEBUG_ASSIST.CORE_0_DRAM0_EXCEPTION_MONITOR_4: core0 bus busy configuration regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_BYTEEN_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_4.Reg)&^(0xffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_BYTEEN_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_4.Reg) & 0xffff +} + +// DEBUG_ASSIST.CORE_0_DRAM0_EXCEPTION_MONITOR_5: core0 bus busy configuration regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_5(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_5.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_5() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_5.Reg) +} + +// DEBUG_ASSIST.CORE_1_MONTR_ENA: Core1 monitor enable configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x2) >> 1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x4) >> 2 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x8) >> 3 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x10) >> 4 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x20) >> 5 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_RD_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_RD_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x40) >> 6 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_WR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_WR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x80) >> 7 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_SP_SPILL_MIN_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_SP_SPILL_MIN_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x100) >> 8 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_SP_SPILL_MAX_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_SP_SPILL_MAX_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x200) >> 9 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x400) >> 10 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_MONTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_MONTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_MONTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_MONTR_ENA.Reg) & 0x800) >> 11 +} + +// DEBUG_ASSIST.CORE_1_INTR_RAW: Core1 monitor interrupt status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW() uint32 { + return volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x2)|value<<1) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x2) >> 1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x4)|value<<2) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x4) >> 2 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x8)|value<<3) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x8) >> 3 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x10)|value<<4) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x10) >> 4 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x20)|value<<5) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x20) >> 5 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x40)|value<<6) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x40) >> 6 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x80)|value<<7) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x80) >> 7 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x100)|value<<8) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x100) >> 8 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x200)|value<<9) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x200) >> 9 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x400)|value<<10) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x400) >> 10 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x800)|value<<11) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x800) >> 11 +} + +// DEBUG_ASSIST.CORE_1_INTR_ENA: Core1 monitor interrupt enable register +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_INTR_ENA() uint32 { + return volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x2)|value<<1) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x2) >> 1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x4)|value<<2) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x4) >> 2 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x8)|value<<3) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x8) >> 3 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x10)|value<<4) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x10) >> 4 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x20)|value<<5) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x20) >> 5 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x40)|value<<6) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x40) >> 6 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x80)|value<<7) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x80) >> 7 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x100)|value<<8) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x100) >> 8 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x200)|value<<9) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x200) >> 9 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x400)|value<<10) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x400) >> 10 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x800)|value<<11) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x800) >> 11 +} + +// DEBUG_ASSIST.CORE_1_INTR_CLR: Core1 monitor interrupt clr register +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x2)|value<<1) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x2) >> 1 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x4)|value<<2) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x4) >> 2 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x8)|value<<3) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x8) >> 3 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x10)|value<<4) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x10) >> 4 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x20)|value<<5) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x20) >> 5 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x40)|value<<6) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x40) >> 6 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x80)|value<<7) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x80) >> 7 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x100)|value<<8) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x100) >> 8 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x200)|value<<9) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x200) >> 9 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x400)|value<<10) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x400) >> 10 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x800)|value<<11) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x800) >> 11 +} + +// DEBUG_ASSIST.CORE_1_AREA_DRAM0_0_MIN: Core1 dram0 region0 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_DRAM0_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_0_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_DRAM0_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_0_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_1_AREA_DRAM0_0_MAX: Core1 dram0 region0 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_DRAM0_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_0_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_DRAM0_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_0_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_1_AREA_DRAM0_1_MIN: Core1 dram0 region1 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_DRAM0_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_1_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_DRAM0_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_1_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_1_AREA_DRAM0_1_MAX: Core1 dram0 region1 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_DRAM0_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_1_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_DRAM0_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_1_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_1_AREA_PIF_0_MIN: Core1 PIF region0 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_PIF_0_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PIF_0_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_PIF_0_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PIF_0_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_1_AREA_PIF_0_MAX: Core1 PIF region0 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_PIF_0_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PIF_0_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_PIF_0_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PIF_0_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_1_AREA_PIF_1_MIN: Core1 PIF region1 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_PIF_1_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PIF_1_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_PIF_1_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PIF_1_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_1_AREA_PIF_1_MAX: Core1 PIF region1 addr configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_PIF_1_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PIF_1_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_PIF_1_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PIF_1_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_1_AREA_PC: Core1 area sp status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_PC(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_PC.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_PC() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_PC.Reg) +} + +// DEBUG_ASSIST.CORE_1_AREA_SP: Core1 area pc status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_AREA_SP(value uint32) { + volatile.StoreUint32(&o.CORE_1_AREA_SP.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_AREA_SP() uint32 { + return volatile.LoadUint32(&o.CORE_1_AREA_SP.Reg) +} + +// DEBUG_ASSIST.CORE_1_SP_UNSTABLE: Core1 sp unstable configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_SP_UNSTABLE(value uint32) { + volatile.StoreUint32(&o.CORE_1_SP_UNSTABLE.Reg, volatile.LoadUint32(&o.CORE_1_SP_UNSTABLE.Reg)&^(0xff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_SP_UNSTABLE() uint32 { + return volatile.LoadUint32(&o.CORE_1_SP_UNSTABLE.Reg) & 0xff +} + +// DEBUG_ASSIST.CORE_1_SP_MIN: Core1 sp region configuration regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_SP_MIN(value uint32) { + volatile.StoreUint32(&o.CORE_1_SP_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_SP_MIN() uint32 { + return volatile.LoadUint32(&o.CORE_1_SP_MIN.Reg) +} + +// DEBUG_ASSIST.CORE_1_SP_MAX: Core1 sp region configuration regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_SP_MAX(value uint32) { + volatile.StoreUint32(&o.CORE_1_SP_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_SP_MAX() uint32 { + return volatile.LoadUint32(&o.CORE_1_SP_MAX.Reg) +} + +// DEBUG_ASSIST.CORE_1_SP_PC: Core1 sp pc status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_SP_PC(value uint32) { + volatile.StoreUint32(&o.CORE_1_SP_PC.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_SP_PC() uint32 { + return volatile.LoadUint32(&o.CORE_1_SP_PC.Reg) +} + +// DEBUG_ASSIST.CORE_1_RCD_PDEBUGENABLE: Core1 pdebug configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_PDEBUGENABLE(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGENABLE.Reg, volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGENABLE.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_PDEBUGENABLE() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGENABLE.Reg) & 0x1 +} + +// DEBUG_ASSIST.CORE_1_RCD_RECORDING: Core1 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_RECORDING(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_RECORDING.Reg, volatile.LoadUint32(&o.CORE_1_RCD_RECORDING.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_RECORDING() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_RECORDING.Reg) & 0x1 +} + +// DEBUG_ASSIST.CORE_1_RCD_PDEBUGINST: Core1 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_PDEBUGINST(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGINST.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_PDEBUGINST() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGINST.Reg) +} + +// DEBUG_ASSIST.CORE_1_RCD_PDEBUGSTATUS: Core1 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_PDEBUGSTATUS(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGSTATUS.Reg, volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGSTATUS.Reg)&^(0xff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_PDEBUGSTATUS() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGSTATUS.Reg) & 0xff +} + +// DEBUG_ASSIST.CORE_1_RCD_PDEBUGDATA: Core1 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_PDEBUGDATA(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGDATA.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_PDEBUGDATA() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGDATA.Reg) +} + +// DEBUG_ASSIST.CORE_1_RCD_PDEBUGPC: Core1 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_PDEBUGPC(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGPC.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_PDEBUGPC() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGPC.Reg) +} + +// DEBUG_ASSIST.CORE_1_RCD_PDEBUGLS0STAT: Core1 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_PDEBUGLS0STAT(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGLS0STAT.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_PDEBUGLS0STAT() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGLS0STAT.Reg) +} + +// DEBUG_ASSIST.CORE_1_RCD_PDEBUGLS0ADDR: Core1 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_PDEBUGLS0ADDR(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGLS0ADDR.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_PDEBUGLS0ADDR() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGLS0ADDR.Reg) +} + +// DEBUG_ASSIST.CORE_1_RCD_PDEBUGLS0DATA: Core1 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_PDEBUGLS0DATA(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGLS0DATA.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_PDEBUGLS0DATA() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGLS0DATA.Reg) +} + +// DEBUG_ASSIST.CORE_1_RCD_SP: Core1 pdebug status register +func (o *DEBUG_ASSIST_Type) SetCORE_1_RCD_SP(value uint32) { + volatile.StoreUint32(&o.CORE_1_RCD_SP.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_RCD_SP() uint32 { + return volatile.LoadUint32(&o.CORE_1_RCD_SP.Reg) +} + +// DEBUG_ASSIST.CORE_1_IRAM0_EXCEPTION_MONITOR_0: Core1 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x2000000)|value<<25) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x2000000) >> 25 +} + +// DEBUG_ASSIST.CORE_1_IRAM0_EXCEPTION_MONITOR_1: Core1 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x1000000)|value<<24) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x1000000) >> 24 +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x2000000)|value<<25) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x2000000) >> 25 +} + +// DEBUG_ASSIST.CORE_1_DRAM0_EXCEPTION_MONITOR_0: Core1 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x3fffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x3fffff +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x400000)|value<<22) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x400000) >> 22 +} + +// DEBUG_ASSIST.CORE_1_DRAM0_EXCEPTION_MONITOR_1: Core1 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_BYTEEN_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_BYTEEN_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffff +} + +// DEBUG_ASSIST.CORE_1_DRAM0_EXCEPTION_MONITOR_2: Core1 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_2(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_2.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_2() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_2.Reg) +} + +// DEBUG_ASSIST.CORE_1_DRAM0_EXCEPTION_MONITOR_3: Core1 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x3fffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x3fffff +} +func (o *DEBUG_ASSIST_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x400000)|value<<22) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x400000) >> 22 +} + +// DEBUG_ASSIST.CORE_1_DRAM0_EXCEPTION_MONITOR_4: Core1 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_BYTEEN_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_4.Reg)&^(0xffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_BYTEEN_1() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_4.Reg) & 0xffff +} + +// DEBUG_ASSIST.CORE_1_DRAM0_EXCEPTION_MONITOR_5: Core1 bus busy status regsiter +func (o *DEBUG_ASSIST_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_5(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_5.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_5() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_5.Reg) +} + +// DEBUG_ASSIST.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: bus busy configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xfffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0xfffff +} + +// DEBUG_ASSIST.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: bus busy configuration register +func (o *DEBUG_ASSIST_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xfffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xfffff +} + +// DEBUG_ASSIST.LOG_SETTING: log set register +func (o *DEBUG_ASSIST_Type) SetLOG_SETTING_LOG_ENA(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x7)|value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_SETTING_LOG_ENA() uint32 { + return volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x7 +} +func (o *DEBUG_ASSIST_Type) SetLOG_SETTING_LOG_MODE(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x38)|value<<3) +} +func (o *DEBUG_ASSIST_Type) GetLOG_SETTING_LOG_MODE() uint32 { + return (volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x38) >> 3 +} +func (o *DEBUG_ASSIST_Type) SetLOG_SETTING_LOG_MEM_LOOP_ENABLE(value uint32) { + volatile.StoreUint32(&o.LOG_SETTING.Reg, volatile.LoadUint32(&o.LOG_SETTING.Reg)&^(0x40)|value<<6) +} +func (o *DEBUG_ASSIST_Type) GetLOG_SETTING_LOG_MEM_LOOP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.LOG_SETTING.Reg) & 0x40) >> 6 +} + +// DEBUG_ASSIST.LOG_DATA_0: log check data register +func (o *DEBUG_ASSIST_Type) SetLOG_DATA_0(value uint32) { + volatile.StoreUint32(&o.LOG_DATA_0.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_DATA_0() uint32 { + return volatile.LoadUint32(&o.LOG_DATA_0.Reg) +} + +// DEBUG_ASSIST.LOG_DATA_1: log check data register +func (o *DEBUG_ASSIST_Type) SetLOG_DATA_1(value uint32) { + volatile.StoreUint32(&o.LOG_DATA_1.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_DATA_1() uint32 { + return volatile.LoadUint32(&o.LOG_DATA_1.Reg) +} + +// DEBUG_ASSIST.LOG_DATA_2: log check data register +func (o *DEBUG_ASSIST_Type) SetLOG_DATA_2(value uint32) { + volatile.StoreUint32(&o.LOG_DATA_2.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_DATA_2() uint32 { + return volatile.LoadUint32(&o.LOG_DATA_2.Reg) +} + +// DEBUG_ASSIST.LOG_DATA_3: log check data register +func (o *DEBUG_ASSIST_Type) SetLOG_DATA_3(value uint32) { + volatile.StoreUint32(&o.LOG_DATA_3.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_DATA_3() uint32 { + return volatile.LoadUint32(&o.LOG_DATA_3.Reg) +} + +// DEBUG_ASSIST.LOG_DATA_MASK: log check data mask register +func (o *DEBUG_ASSIST_Type) SetLOG_DATA_MASK_LOG_DATA_SIZE(value uint32) { + volatile.StoreUint32(&o.LOG_DATA_MASK.Reg, volatile.LoadUint32(&o.LOG_DATA_MASK.Reg)&^(0xffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_DATA_MASK_LOG_DATA_SIZE() uint32 { + return volatile.LoadUint32(&o.LOG_DATA_MASK.Reg) & 0xffff +} + +// DEBUG_ASSIST.LOG_MIN: log check region configuration register +func (o *DEBUG_ASSIST_Type) SetLOG_MIN(value uint32) { + volatile.StoreUint32(&o.LOG_MIN.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_MIN() uint32 { + return volatile.LoadUint32(&o.LOG_MIN.Reg) +} + +// DEBUG_ASSIST.LOG_MAX: log check region configuration register +func (o *DEBUG_ASSIST_Type) SetLOG_MAX(value uint32) { + volatile.StoreUint32(&o.LOG_MAX.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_MAX() uint32 { + return volatile.LoadUint32(&o.LOG_MAX.Reg) +} + +// DEBUG_ASSIST.LOG_MEM_START: log mem region configuration register +func (o *DEBUG_ASSIST_Type) SetLOG_MEM_START(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_START.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_MEM_START() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_START.Reg) +} + +// DEBUG_ASSIST.LOG_MEM_END: log mem region configuration register +func (o *DEBUG_ASSIST_Type) SetLOG_MEM_END(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_END.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_MEM_END() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_END.Reg) +} + +// DEBUG_ASSIST.LOG_MEM_WRITING_ADDR: log mem addr status register +func (o *DEBUG_ASSIST_Type) SetLOG_MEM_WRITING_ADDR(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_WRITING_ADDR.Reg, value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_MEM_WRITING_ADDR() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_WRITING_ADDR.Reg) +} + +// DEBUG_ASSIST.LOG_MEM_FULL_FLAG: log mem status register +func (o *DEBUG_ASSIST_Type) SetLOG_MEM_FULL_FLAG(value uint32) { + volatile.StoreUint32(&o.LOG_MEM_FULL_FLAG.Reg, volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg)&^(0x1)|value) +} +func (o *DEBUG_ASSIST_Type) GetLOG_MEM_FULL_FLAG() uint32 { + return volatile.LoadUint32(&o.LOG_MEM_FULL_FLAG.Reg) & 0x1 +} + +// DEBUG_ASSIST.DATE: version register +func (o *DEBUG_ASSIST_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *DEBUG_ASSIST_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// DMA (Direct Memory Access) Controller +type DMA_Type struct { + IN_CONF0_CH0 volatile.Register32 // 0x0 + IN_CONF1_CH0 volatile.Register32 // 0x4 + IN_INT_RAW_CH0 volatile.Register32 // 0x8 + IN_INT_ST_CH0 volatile.Register32 // 0xC + IN_INT_ENA_CH0 volatile.Register32 // 0x10 + IN_INT_CLR_CH0 volatile.Register32 // 0x14 + INFIFO_STATUS_CH0 volatile.Register32 // 0x18 + IN_POP_CH0 volatile.Register32 // 0x1C + IN_LINK_CH0 volatile.Register32 // 0x20 + IN_STATE_CH0 volatile.Register32 // 0x24 + IN_SUC_EOF_DES_ADDR_CH0 volatile.Register32 // 0x28 + IN_ERR_EOF_DES_ADDR_CH0 volatile.Register32 // 0x2C + IN_DSCR_CH0 volatile.Register32 // 0x30 + IN_DSCR_BF0_CH0 volatile.Register32 // 0x34 + IN_DSCR_BF1_CH0 volatile.Register32 // 0x38 + IN_WIGHT_CH0 volatile.Register32 // 0x3C + _ [4]byte + IN_PRI_CH0 volatile.Register32 // 0x44 + IN_PERI_SEL_CH0 volatile.Register32 // 0x48 + _ [20]byte + OUT_CONF0_CH0 volatile.Register32 // 0x60 + OUT_CONF1_CH0 volatile.Register32 // 0x64 + OUT_INT_RAW_CH0 volatile.Register32 // 0x68 + OUT_INT_ST_CH0 volatile.Register32 // 0x6C + OUT_INT_ENA_CH0 volatile.Register32 // 0x70 + OUT_INT_CLR_CH0 volatile.Register32 // 0x74 + OUTFIFO_STATUS_CH0 volatile.Register32 // 0x78 + OUT_PUSH_CH0 volatile.Register32 // 0x7C + OUT_LINK_CH0 volatile.Register32 // 0x80 + OUT_STATE_CH0 volatile.Register32 // 0x84 + OUT_EOF_DES_ADDR_CH0 volatile.Register32 // 0x88 + OUT_EOF_BFR_DES_ADDR_CH0 volatile.Register32 // 0x8C + OUT_DSCR_CH0 volatile.Register32 // 0x90 + OUT_DSCR_BF0_CH0 volatile.Register32 // 0x94 + OUT_DSCR_BF1_CH0 volatile.Register32 // 0x98 + OUT_WIGHT_CH0 volatile.Register32 // 0x9C + _ [4]byte + OUT_PRI_CH0 volatile.Register32 // 0xA4 + OUT_PERI_SEL_CH0 volatile.Register32 // 0xA8 + _ [20]byte + IN_CONF0_CH1 volatile.Register32 // 0xC0 + IN_CONF1_CH1 volatile.Register32 // 0xC4 + IN_INT_RAW_CH1 volatile.Register32 // 0xC8 + IN_INT_ST_CH1 volatile.Register32 // 0xCC + IN_INT_ENA_CH1 volatile.Register32 // 0xD0 + IN_INT_CLR_CH1 volatile.Register32 // 0xD4 + INFIFO_STATUS_CH1 volatile.Register32 // 0xD8 + IN_POP_CH1 volatile.Register32 // 0xDC + IN_LINK_CH1 volatile.Register32 // 0xE0 + IN_STATE_CH1 volatile.Register32 // 0xE4 + IN_SUC_EOF_DES_ADDR_CH1 volatile.Register32 // 0xE8 + IN_ERR_EOF_DES_ADDR_CH1 volatile.Register32 // 0xEC + IN_DSCR_CH1 volatile.Register32 // 0xF0 + IN_DSCR_BF0_CH1 volatile.Register32 // 0xF4 + IN_DSCR_BF1_CH1 volatile.Register32 // 0xF8 + IN_WIGHT_CH1 volatile.Register32 // 0xFC + _ [4]byte + IN_PRI_CH1 volatile.Register32 // 0x104 + IN_PERI_SEL_CH1 volatile.Register32 // 0x108 + _ [20]byte + OUT_CONF0_CH1 volatile.Register32 // 0x120 + OUT_CONF1_CH1 volatile.Register32 // 0x124 + OUT_INT_RAW_CH1 volatile.Register32 // 0x128 + OUT_INT_ST_CH1 volatile.Register32 // 0x12C + OUT_INT_ENA_CH1 volatile.Register32 // 0x130 + OUT_INT_CLR_CH1 volatile.Register32 // 0x134 + OUTFIFO_STATUS_CH1 volatile.Register32 // 0x138 + OUT_PUSH_CH1 volatile.Register32 // 0x13C + OUT_LINK_CH1 volatile.Register32 // 0x140 + OUT_STATE_CH1 volatile.Register32 // 0x144 + OUT_EOF_DES_ADDR_CH1 volatile.Register32 // 0x148 + OUT_EOF_BFR_DES_ADDR_CH1 volatile.Register32 // 0x14C + OUT_DSCR_CH1 volatile.Register32 // 0x150 + OUT_DSCR_BF0_CH1 volatile.Register32 // 0x154 + OUT_DSCR_BF1_CH1 volatile.Register32 // 0x158 + OUT_WIGHT_CH1 volatile.Register32 // 0x15C + _ [4]byte + OUT_PRI_CH1 volatile.Register32 // 0x164 + OUT_PERI_SEL_CH1 volatile.Register32 // 0x168 + _ [20]byte + IN_CONF0_CH2 volatile.Register32 // 0x180 + IN_CONF1_CH2 volatile.Register32 // 0x184 + IN_INT_RAW_CH2 volatile.Register32 // 0x188 + IN_INT_ST_CH2 volatile.Register32 // 0x18C + IN_INT_ENA_CH2 volatile.Register32 // 0x190 + IN_INT_CLR_CH2 volatile.Register32 // 0x194 + INFIFO_STATUS_CH2 volatile.Register32 // 0x198 + IN_POP_CH2 volatile.Register32 // 0x19C + IN_LINK_CH2 volatile.Register32 // 0x1A0 + IN_STATE_CH2 volatile.Register32 // 0x1A4 + IN_SUC_EOF_DES_ADDR_CH2 volatile.Register32 // 0x1A8 + IN_ERR_EOF_DES_ADDR_CH2 volatile.Register32 // 0x1AC + IN_DSCR_CH2 volatile.Register32 // 0x1B0 + IN_DSCR_BF0_CH2 volatile.Register32 // 0x1B4 + IN_DSCR_BF1_CH2 volatile.Register32 // 0x1B8 + IN_WIGHT_CH2 volatile.Register32 // 0x1BC + _ [4]byte + IN_PRI_CH2 volatile.Register32 // 0x1C4 + IN_PERI_SEL_CH2 volatile.Register32 // 0x1C8 + _ [20]byte + OUT_CONF0_CH2 volatile.Register32 // 0x1E0 + OUT_CONF1_CH2 volatile.Register32 // 0x1E4 + OUT_INT_RAW_CH2 volatile.Register32 // 0x1E8 + OUT_INT_ST_CH2 volatile.Register32 // 0x1EC + OUT_INT_ENA_CH2 volatile.Register32 // 0x1F0 + OUT_INT_CLR_CH2 volatile.Register32 // 0x1F4 + OUTFIFO_STATUS_CH2 volatile.Register32 // 0x1F8 + OUT_PUSH_CH2 volatile.Register32 // 0x1FC + OUT_LINK_CH2 volatile.Register32 // 0x200 + OUT_STATE_CH2 volatile.Register32 // 0x204 + OUT_EOF_DES_ADDR_CH2 volatile.Register32 // 0x208 + OUT_EOF_BFR_DES_ADDR_CH2 volatile.Register32 // 0x20C + OUT_DSCR_CH2 volatile.Register32 // 0x210 + OUT_DSCR_BF0_CH2 volatile.Register32 // 0x214 + OUT_DSCR_BF1_CH2 volatile.Register32 // 0x218 + OUT_WIGHT_CH2 volatile.Register32 // 0x21C + _ [4]byte + OUT_PRI_CH2 volatile.Register32 // 0x224 + OUT_PERI_SEL_CH2 volatile.Register32 // 0x228 + _ [20]byte + IN_CONF0_CH3 volatile.Register32 // 0x240 + IN_CONF1_CH3 volatile.Register32 // 0x244 + IN_INT_RAW_CH3 volatile.Register32 // 0x248 + IN_INT_ST_CH3 volatile.Register32 // 0x24C + IN_INT_ENA_CH3 volatile.Register32 // 0x250 + IN_INT_CLR_CH3 volatile.Register32 // 0x254 + INFIFO_STATUS_CH3 volatile.Register32 // 0x258 + IN_POP_CH3 volatile.Register32 // 0x25C + IN_LINK_CH3 volatile.Register32 // 0x260 + IN_STATE_CH3 volatile.Register32 // 0x264 + IN_SUC_EOF_DES_ADDR_CH3 volatile.Register32 // 0x268 + IN_ERR_EOF_DES_ADDR_CH3 volatile.Register32 // 0x26C + IN_DSCR_CH3 volatile.Register32 // 0x270 + IN_DSCR_BF0_CH3 volatile.Register32 // 0x274 + IN_DSCR_BF1_CH3 volatile.Register32 // 0x278 + IN_WIGHT_CH3 volatile.Register32 // 0x27C + _ [4]byte + IN_PRI_CH3 volatile.Register32 // 0x284 + IN_PERI_SEL_CH3 volatile.Register32 // 0x288 + _ [20]byte + OUT_CONF0_CH3 volatile.Register32 // 0x2A0 + OUT_CONF1_CH3 volatile.Register32 // 0x2A4 + OUT_INT_RAW_CH3 volatile.Register32 // 0x2A8 + OUT_INT_ST_CH3 volatile.Register32 // 0x2AC + OUT_INT_ENA_CH3 volatile.Register32 // 0x2B0 + OUT_INT_CLR_CH3 volatile.Register32 // 0x2B4 + OUTFIFO_STATUS_CH3 volatile.Register32 // 0x2B8 + OUT_PUSH_CH3 volatile.Register32 // 0x2BC + OUT_LINK_CH3 volatile.Register32 // 0x2C0 + OUT_STATE_CH3 volatile.Register32 // 0x2C4 + OUT_EOF_DES_ADDR_CH3 volatile.Register32 // 0x2C8 + OUT_EOF_BFR_DES_ADDR_CH3 volatile.Register32 // 0x2CC + OUT_DSCR_CH3 volatile.Register32 // 0x2D0 + OUT_DSCR_BF0_CH3 volatile.Register32 // 0x2D4 + OUT_DSCR_BF1_CH3 volatile.Register32 // 0x2D8 + OUT_WIGHT_CH3 volatile.Register32 // 0x2DC + _ [4]byte + OUT_PRI_CH3 volatile.Register32 // 0x2E4 + OUT_PERI_SEL_CH3 volatile.Register32 // 0x2E8 + _ [20]byte + IN_CONF0_CH4 volatile.Register32 // 0x300 + IN_CONF1_CH4 volatile.Register32 // 0x304 + IN_INT_RAW_CH4 volatile.Register32 // 0x308 + IN_INT_ST_CH4 volatile.Register32 // 0x30C + IN_INT_ENA_CH4 volatile.Register32 // 0x310 + IN_INT_CLR_CH4 volatile.Register32 // 0x314 + INFIFO_STATUS_CH4 volatile.Register32 // 0x318 + IN_POP_CH4 volatile.Register32 // 0x31C + IN_LINK_CH4 volatile.Register32 // 0x320 + IN_STATE_CH4 volatile.Register32 // 0x324 + IN_SUC_EOF_DES_ADDR_CH4 volatile.Register32 // 0x328 + IN_ERR_EOF_DES_ADDR_CH4 volatile.Register32 // 0x32C + IN_DSCR_CH4 volatile.Register32 // 0x330 + IN_DSCR_BF0_CH4 volatile.Register32 // 0x334 + IN_DSCR_BF1_CH4 volatile.Register32 // 0x338 + IN_WIGHT_CH4 volatile.Register32 // 0x33C + _ [4]byte + IN_PRI_CH4 volatile.Register32 // 0x344 + IN_PERI_SEL_CH4 volatile.Register32 // 0x348 + _ [20]byte + OUT_CONF0_CH4 volatile.Register32 // 0x360 + OUT_CONF1_CH4 volatile.Register32 // 0x364 + OUT_INT_RAW_CH4 volatile.Register32 // 0x368 + OUT_INT_ST_CH4 volatile.Register32 // 0x36C + OUT_INT_ENA_CH4 volatile.Register32 // 0x370 + OUT_INT_CLR_CH4 volatile.Register32 // 0x374 + OUTFIFO_STATUS_CH4 volatile.Register32 // 0x378 + OUT_PUSH_CH4 volatile.Register32 // 0x37C + OUT_LINK_CH4 volatile.Register32 // 0x380 + OUT_STATE_CH4 volatile.Register32 // 0x384 + OUT_EOF_DES_ADDR_CH4 volatile.Register32 // 0x388 + OUT_EOF_BFR_DES_ADDR_CH4 volatile.Register32 // 0x38C + OUT_DSCR_CH4 volatile.Register32 // 0x390 + OUT_DSCR_BF0_CH4 volatile.Register32 // 0x394 + OUT_DSCR_BF1_CH4 volatile.Register32 // 0x398 + OUT_WIGHT_CH4 volatile.Register32 // 0x39C + _ [4]byte + OUT_PRI_CH4 volatile.Register32 // 0x3A4 + OUT_PERI_SEL_CH4 volatile.Register32 // 0x3A8 + _ [20]byte + AHB_TEST volatile.Register32 // 0x3C0 + PD_CONF volatile.Register32 // 0x3C4 + MISC_CONF volatile.Register32 // 0x3C8 + IN_SRAM_SIZE_CH0 volatile.Register32 // 0x3CC + OUT_SRAM_SIZE_CH0 volatile.Register32 // 0x3D0 + IN_SRAM_SIZE_CH1 volatile.Register32 // 0x3D4 + OUT_SRAM_SIZE_CH1 volatile.Register32 // 0x3D8 + IN_SRAM_SIZE_CH2 volatile.Register32 // 0x3DC + OUT_SRAM_SIZE_CH2 volatile.Register32 // 0x3E0 + IN_SRAM_SIZE_CH3 volatile.Register32 // 0x3E4 + OUT_SRAM_SIZE_CH3 volatile.Register32 // 0x3E8 + IN_SRAM_SIZE_CH4 volatile.Register32 // 0x3EC + OUT_SRAM_SIZE_CH4 volatile.Register32 // 0x3F0 + EXTMEM_REJECT_ADDR volatile.Register32 // 0x3F4 + EXTMEM_REJECT_ST volatile.Register32 // 0x3F8 + EXTMEM_REJECT_INT_RAW volatile.Register32 // 0x3FC + EXTMEM_REJECT_INT_ST volatile.Register32 // 0x400 + EXTMEM_REJECT_INT_ENA volatile.Register32 // 0x404 + EXTMEM_REJECT_INT_CLR volatile.Register32 // 0x408 + DATE volatile.Register32 // 0x40C +} + +// DMA.IN_CONF0_CH0: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH0_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH0_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH0_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH0_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH0_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x10) >> 4 +} + +// DMA.IN_CONF1_CH0: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH0_DMA_INFIFO_FULL_THRS(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_CONF1_CH0_DMA_INFIFO_FULL_THRS() uint32 { + return volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_CONF1_CH0_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH0_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetIN_CONF1_CH0_IN_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetIN_CONF1_CH0_IN_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x6000) >> 13 +} + +// DMA.IN_INT_RAW_CH0: Raw status interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ST_CH0: Masked interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ENA_CH0: Interrupt enable bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_CLR_CH0: Interrupt clear bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_DMA_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_DMA_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x200) >> 9 +} + +// DMA.INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xfc0)|value<<6) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xfc0) >> 6 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x7f000)|value<<12) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x7f000) >> 12 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xf80000)|value<<19) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xf80000) >> 19 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH0_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x10000000)|value<<28) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH0_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x10000000) >> 28 +} + +// DMA.IN_POP_CH0: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH0_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH0_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH0_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH0_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH0: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH0_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH0_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg) +} + +// DMA.IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg) +} + +// DMA.IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg) +} + +// DMA.IN_WIGHT_CH0: Weight register of Rx channel 0 +func (o *DMA_Type) SetIN_WIGHT_CH0_RX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.IN_WIGHT_CH0.Reg, volatile.LoadUint32(&o.IN_WIGHT_CH0.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetIN_WIGHT_CH0_RX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.IN_WIGHT_CH0.Reg) & 0xf00) >> 8 +} + +// DMA.IN_PRI_CH0: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH0_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH0_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH0_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH0_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH0: Configure 0 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH0_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH0_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x20) >> 5 +} + +// DMA.OUT_CONF1_CH0: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH0_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH0_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetOUT_CONF1_CH0_OUT_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetOUT_CONF1_CH0_OUT_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x6000) >> 13 +} + +// DMA.OUT_INT_RAW_CH0: Raw status interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ST_CH0: Masked interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ENA_CH0: Interrupt enable bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_CLR_CH0: Interrupt clear bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x80) >> 7 +} + +// DMA.OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x7c0)|value<<6) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x7c0) >> 6 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x3f800)|value<<11) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x3f800) >> 11 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x7c0000)|value<<18) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x7c0000) >> 18 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH0: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH0_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH0_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH0: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH0_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH0_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg) +} + +// DMA.OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg) +} + +// DMA.OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg) +} + +// DMA.OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg) +} + +// DMA.OUT_WIGHT_CH0: Weight register of Rx channel 0 +func (o *DMA_Type) SetOUT_WIGHT_CH0_TX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.OUT_WIGHT_CH0.Reg, volatile.LoadUint32(&o.OUT_WIGHT_CH0.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetOUT_WIGHT_CH0_TX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.OUT_WIGHT_CH0.Reg) & 0xf00) >> 8 +} + +// DMA.OUT_PRI_CH0: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH0_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH0_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH0_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH0_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH1: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH1_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH1_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH1_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH1_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH1_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x10) >> 4 +} + +// DMA.IN_CONF1_CH1: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH1_DMA_INFIFO_FULL_THRS(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_CONF1_CH1_DMA_INFIFO_FULL_THRS() uint32 { + return volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_CONF1_CH1_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH1_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetIN_CONF1_CH1_IN_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetIN_CONF1_CH1_IN_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0x6000) >> 13 +} + +// DMA.IN_INT_RAW_CH1: Raw status interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ST_CH1: Masked interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ENA_CH1: Interrupt enable bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_CLR_CH1: Interrupt clear bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_DMA_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_DMA_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x200) >> 9 +} + +// DMA.INFIFO_STATUS_CH1: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xfc0)|value<<6) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xfc0) >> 6 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x7f000)|value<<12) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x7f000) >> 12 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xf80000)|value<<19) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xf80000) >> 19 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH1_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x10000000)|value<<28) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH1_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x10000000) >> 28 +} + +// DMA.IN_POP_CH1: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH1_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH1_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH1_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH1_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH1: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH1_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH1_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH1: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH1_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH1_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH1: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH1: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.IN_DSCR_CH1: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg) +} + +// DMA.IN_DSCR_BF0_CH1: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg) +} + +// DMA.IN_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg) +} + +// DMA.IN_WIGHT_CH1: Weight register of Rx channel 0 +func (o *DMA_Type) SetIN_WIGHT_CH1_RX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.IN_WIGHT_CH1.Reg, volatile.LoadUint32(&o.IN_WIGHT_CH1.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetIN_WIGHT_CH1_RX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.IN_WIGHT_CH1.Reg) & 0xf00) >> 8 +} + +// DMA.IN_PRI_CH1: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH1_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH1_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH1: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH1_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH1_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH1: Configure 0 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH1_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH1_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x20) >> 5 +} + +// DMA.OUT_CONF1_CH1: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH1_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH1_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetOUT_CONF1_CH1_OUT_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetOUT_CONF1_CH1_OUT_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg) & 0x6000) >> 13 +} + +// DMA.OUT_INT_RAW_CH1: Raw status interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ST_CH1: Masked interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ENA_CH1: Interrupt enable bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_CLR_CH1: Interrupt clear bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x80) >> 7 +} + +// DMA.OUTFIFO_STATUS_CH1: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x7c0)|value<<6) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x7c0) >> 6 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x3f800)|value<<11) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x3f800) >> 11 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x7c0000)|value<<18) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x7c0000) >> 18 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH1: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH1: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH1_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH1_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH1: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH1_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH1_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH1: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH1: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg) +} + +// DMA.OUT_DSCR_CH1: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg) +} + +// DMA.OUT_DSCR_BF0_CH1: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg) +} + +// DMA.OUT_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg) +} + +// DMA.OUT_WIGHT_CH1: Weight register of Rx channel 0 +func (o *DMA_Type) SetOUT_WIGHT_CH1_TX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.OUT_WIGHT_CH1.Reg, volatile.LoadUint32(&o.OUT_WIGHT_CH1.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetOUT_WIGHT_CH1_TX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.OUT_WIGHT_CH1.Reg) & 0xf00) >> 8 +} + +// DMA.OUT_PRI_CH1: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH1_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH1_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH1: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH1_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH1_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH2: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH2_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH2_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH2_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH2_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH2_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x10) >> 4 +} + +// DMA.IN_CONF1_CH2: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH2_DMA_INFIFO_FULL_THRS(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_CONF1_CH2_DMA_INFIFO_FULL_THRS() uint32 { + return volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_CONF1_CH2_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH2_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetIN_CONF1_CH2_IN_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetIN_CONF1_CH2_IN_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0x6000) >> 13 +} + +// DMA.IN_INT_RAW_CH2: Raw status interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ST_CH2: Masked interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ENA_CH2: Interrupt enable bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_CLR_CH2: Interrupt clear bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_DMA_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_DMA_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x200) >> 9 +} + +// DMA.INFIFO_STATUS_CH2: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xfc0)|value<<6) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xfc0) >> 6 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x7f000)|value<<12) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x7f000) >> 12 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xf80000)|value<<19) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xf80000) >> 19 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH2_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x10000000)|value<<28) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH2_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x10000000) >> 28 +} + +// DMA.IN_POP_CH2: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH2_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH2_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH2_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH2_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH2: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH2_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH2_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH2: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH2_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH2_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH2: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH2: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.IN_DSCR_CH2: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg) +} + +// DMA.IN_DSCR_BF0_CH2: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg) +} + +// DMA.IN_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg) +} + +// DMA.IN_WIGHT_CH2: Weight register of Rx channel 0 +func (o *DMA_Type) SetIN_WIGHT_CH2_RX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.IN_WIGHT_CH2.Reg, volatile.LoadUint32(&o.IN_WIGHT_CH2.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetIN_WIGHT_CH2_RX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.IN_WIGHT_CH2.Reg) & 0xf00) >> 8 +} + +// DMA.IN_PRI_CH2: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH2_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH2_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH2: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH2_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH2_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH2: Configure 0 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH2_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH2_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x20) >> 5 +} + +// DMA.OUT_CONF1_CH2: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH2_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH2_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetOUT_CONF1_CH2_OUT_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetOUT_CONF1_CH2_OUT_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg) & 0x6000) >> 13 +} + +// DMA.OUT_INT_RAW_CH2: Raw status interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ST_CH2: Masked interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ENA_CH2: Interrupt enable bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_CLR_CH2: Interrupt clear bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x80) >> 7 +} + +// DMA.OUTFIFO_STATUS_CH2: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x7c0)|value<<6) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x7c0) >> 6 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x3f800)|value<<11) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x3f800) >> 11 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x7c0000)|value<<18) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x7c0000) >> 18 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH2: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH2: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH2_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH2_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH2: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH2_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH2_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH2: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH2: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg) +} + +// DMA.OUT_DSCR_CH2: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg) +} + +// DMA.OUT_DSCR_BF0_CH2: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg) +} + +// DMA.OUT_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg) +} + +// DMA.OUT_WIGHT_CH2: Weight register of Rx channel 0 +func (o *DMA_Type) SetOUT_WIGHT_CH2_TX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.OUT_WIGHT_CH2.Reg, volatile.LoadUint32(&o.OUT_WIGHT_CH2.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetOUT_WIGHT_CH2_TX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.OUT_WIGHT_CH2.Reg) & 0xf00) >> 8 +} + +// DMA.OUT_PRI_CH2: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH2_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH2_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH2: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH2_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH2_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH3: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH3_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH3_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH3_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH3_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH3_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH3_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH3_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH3_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH3_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH3_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x10) >> 4 +} + +// DMA.IN_CONF1_CH3: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH3_DMA_INFIFO_FULL_THRS(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH3.Reg, volatile.LoadUint32(&o.IN_CONF1_CH3.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_CONF1_CH3_DMA_INFIFO_FULL_THRS() uint32 { + return volatile.LoadUint32(&o.IN_CONF1_CH3.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_CONF1_CH3_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH3.Reg, volatile.LoadUint32(&o.IN_CONF1_CH3.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH3_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH3.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetIN_CONF1_CH3_IN_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH3.Reg, volatile.LoadUint32(&o.IN_CONF1_CH3.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetIN_CONF1_CH3_IN_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH3.Reg) & 0x6000) >> 13 +} + +// DMA.IN_INT_RAW_CH3: Raw status interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH3_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH3_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH3_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH3_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH3_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH3_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH3_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_RAW_CH3_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_RAW_CH3_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_RAW_CH3_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_RAW_CH3_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ST_CH3: Masked interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH3_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH3_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH3_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH3_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH3_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH3_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH3_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ST_CH3_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ST_CH3_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ST_CH3_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ST_CH3_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ENA_CH3: Interrupt enable bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH3_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH3_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH3_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH3_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH3_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH3_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH3_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ENA_CH3_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ENA_CH3_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ENA_CH3_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ENA_CH3_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_CLR_CH3: Interrupt clear bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH3_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH3_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH3_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH3_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH3_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH3_DMA_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_DMA_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH3_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_CLR_CH3_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_CLR_CH3_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_CLR_CH3_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_CLR_CH3_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x200) >> 9 +} + +// DMA.INFIFO_STATUS_CH3: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0xfc0)|value<<6) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0xfc0) >> 6 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x7f000)|value<<12) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x7f000) >> 12 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0xf80000)|value<<19) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0xf80000) >> 19 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_IN_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_IN_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_IN_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_IN_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_IN_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_IN_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_IN_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_IN_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x8000000) >> 27 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH3_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x10000000)|value<<28) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH3_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x10000000) >> 28 +} + +// DMA.IN_POP_CH3: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH3_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH3.Reg, volatile.LoadUint32(&o.IN_POP_CH3.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH3_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH3.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH3_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH3.Reg, volatile.LoadUint32(&o.IN_POP_CH3.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH3_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH3.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH3: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH3_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CH3.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH3_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH3.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH3_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CH3.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH3_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH3.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH3_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CH3.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH3_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH3.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH3_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CH3.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH3_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH3.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH3_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CH3.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH3_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH3.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH3_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CH3.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH3_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH3.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH3: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH3_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH3_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH3_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH3_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH3_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH3_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH3: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH3.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH3.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH3: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH3.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH3.Reg) +} + +// DMA.IN_DSCR_CH3: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH3(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH3.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH3() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH3.Reg) +} + +// DMA.IN_DSCR_BF0_CH3: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH3(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH3.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH3() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH3.Reg) +} + +// DMA.IN_DSCR_BF1_CH3: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH3(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH3.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH3() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH3.Reg) +} + +// DMA.IN_WIGHT_CH3: Weight register of Rx channel 0 +func (o *DMA_Type) SetIN_WIGHT_CH3_RX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.IN_WIGHT_CH3.Reg, volatile.LoadUint32(&o.IN_WIGHT_CH3.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetIN_WIGHT_CH3_RX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.IN_WIGHT_CH3.Reg) & 0xf00) >> 8 +} + +// DMA.IN_PRI_CH3: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH3_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH3.Reg, volatile.LoadUint32(&o.IN_PRI_CH3.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH3_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH3.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH3: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH3_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH3.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH3.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH3_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH3.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH3: Configure 0 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF0_CH3_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH3_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH3_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH3_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH3_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH3_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH3_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH3_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH3_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH3_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH3_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH3_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x20) >> 5 +} + +// DMA.OUT_CONF1_CH3: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH3_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH3.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH3_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH3.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetOUT_CONF1_CH3_OUT_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH3.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetOUT_CONF1_CH3_OUT_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH3.Reg) & 0x6000) >> 13 +} + +// DMA.OUT_INT_RAW_CH3: Raw status interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH3_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH3_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH3_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH3_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH3_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH3_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH3_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH3_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ST_CH3: Masked interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH3_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH3_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH3_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH3_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH3_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH3_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH3_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH3_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ENA_CH3: Interrupt enable bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH3_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH3_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH3_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH3_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH3_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH3_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH3_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH3_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_CLR_CH3: Interrupt clear bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH3_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH3_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH3_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH3_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH3_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH3_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH3_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH3_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x80) >> 7 +} + +// DMA.OUTFIFO_STATUS_CH3: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x7c0)|value<<6) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x7c0) >> 6 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x3f800)|value<<11) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x3f800) >> 11 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x7c0000)|value<<18) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x7c0000) >> 18 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUT_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUT_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUT_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUT_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUT_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUT_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH3_OUT_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH3_OUT_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH3: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH3_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH3.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH3_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH3_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH3.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH3_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH3: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH3_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CH3.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH3_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH3.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH3_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CH3.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH3_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH3.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH3_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CH3.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH3_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH3.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH3_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CH3.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH3_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH3.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH3_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CH3.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH3_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH3.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH3: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH3_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH3.Reg, volatile.LoadUint32(&o.OUT_STATE_CH3.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH3_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH3.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH3_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH3.Reg, volatile.LoadUint32(&o.OUT_STATE_CH3.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH3_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH3.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH3_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH3.Reg, volatile.LoadUint32(&o.OUT_STATE_CH3.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH3_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH3.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH3: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH3.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH3.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH3: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH3.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH3.Reg) +} + +// DMA.OUT_DSCR_CH3: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH3.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH3.Reg) +} + +// DMA.OUT_DSCR_BF0_CH3: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH3.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH3.Reg) +} + +// DMA.OUT_DSCR_BF1_CH3: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH3(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH3.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH3() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH3.Reg) +} + +// DMA.OUT_WIGHT_CH3: Weight register of Rx channel 0 +func (o *DMA_Type) SetOUT_WIGHT_CH3_TX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.OUT_WIGHT_CH3.Reg, volatile.LoadUint32(&o.OUT_WIGHT_CH3.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetOUT_WIGHT_CH3_TX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.OUT_WIGHT_CH3.Reg) & 0xf00) >> 8 +} + +// DMA.OUT_PRI_CH3: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH3_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH3.Reg, volatile.LoadUint32(&o.OUT_PRI_CH3.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH3_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH3.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH3: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH3_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH3.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH3.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH3_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH3.Reg) & 0x3f +} + +// DMA.IN_CONF0_CH4: Configure 0 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF0_CH4_IN_RST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_CONF0_CH4_IN_RST() uint32 { + return volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_CONF0_CH4_IN_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_CONF0_CH4_IN_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_CONF0_CH4_INDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_CONF0_CH4_INDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_CONF0_CH4_IN_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_CONF0_CH4_IN_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_CONF0_CH4_MEM_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_CONF0_CH4_MEM_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x10) >> 4 +} + +// DMA.IN_CONF1_CH4: Configure 1 register of Rx channel 0 +func (o *DMA_Type) SetIN_CONF1_CH4_DMA_INFIFO_FULL_THRS(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH4.Reg, volatile.LoadUint32(&o.IN_CONF1_CH4.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_CONF1_CH4_DMA_INFIFO_FULL_THRS() uint32 { + return volatile.LoadUint32(&o.IN_CONF1_CH4.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_CONF1_CH4_IN_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH4.Reg, volatile.LoadUint32(&o.IN_CONF1_CH4.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_CONF1_CH4_IN_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH4.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetIN_CONF1_CH4_IN_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_CONF1_CH4.Reg, volatile.LoadUint32(&o.IN_CONF1_CH4.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetIN_CONF1_CH4_IN_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.IN_CONF1_CH4.Reg) & 0x6000) >> 13 +} + +// DMA.IN_INT_RAW_CH4: Raw status interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_RAW_CH4_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH4_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_RAW_CH4_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_RAW_CH4_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_RAW_CH4_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_RAW_CH4_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_RAW_CH4_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_RAW_CH4_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_RAW_CH4_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_RAW_CH4_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_RAW_CH4_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ST_CH4: Masked interrupt of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ST_CH4_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ST_CH4_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ST_CH4_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ST_CH4_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ST_CH4_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ST_CH4_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ST_CH4_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ST_CH4_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ST_CH4_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ST_CH4_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ST_CH4_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_ENA_CH4: Interrupt enable bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_ENA_CH4_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH4_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_ENA_CH4_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_ENA_CH4_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_ENA_CH4_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_ENA_CH4_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_ENA_CH4_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_ENA_CH4_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_ENA_CH4_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_ENA_CH4_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_ENA_CH4_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x200) >> 9 +} + +// DMA.IN_INT_CLR_CH4: Interrupt clear bits of Rx channel 0 +func (o *DMA_Type) SetIN_INT_CLR_CH4_IN_DONE(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_IN_DONE() uint32 { + return volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH4_IN_SUC_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_IN_SUC_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetIN_INT_CLR_CH4_IN_ERR_EOF(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_IN_ERR_EOF() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetIN_INT_CLR_CH4_IN_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_IN_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetIN_INT_CLR_CH4_IN_DSCR_EMPTY(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_IN_DSCR_EMPTY() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetIN_INT_CLR_CH4_DMA_INFIFO_FULL_WM(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_DMA_INFIFO_FULL_WM() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetIN_INT_CLR_CH4_INFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_INFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetIN_INT_CLR_CH4_INFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_INFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x80) >> 7 +} +func (o *DMA_Type) SetIN_INT_CLR_CH4_INFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x100)|value<<8) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_INFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x100) >> 8 +} +func (o *DMA_Type) SetIN_INT_CLR_CH4_INFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetIN_INT_CLR_CH4_INFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x200) >> 9 +} + +// DMA.INFIFO_STATUS_CH4: Receive FIFO status of Rx channel 0 +func (o *DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0xfc0)|value<<6) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0xfc0) >> 6 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x7f000)|value<<12) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x7f000) >> 12 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0xf80000)|value<<19) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0xf80000) >> 19 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_IN_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_IN_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_IN_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_IN_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_IN_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_IN_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x4000000) >> 26 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_IN_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x8000000)|value<<27) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_IN_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x8000000) >> 27 +} +func (o *DMA_Type) SetINFIFO_STATUS_CH4_IN_BUF_HUNGRY(value uint32) { + volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x10000000)|value<<28) +} +func (o *DMA_Type) GetINFIFO_STATUS_CH4_IN_BUF_HUNGRY() uint32 { + return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x10000000) >> 28 +} + +// DMA.IN_POP_CH4: Pop control register of Rx channel 0 +func (o *DMA_Type) SetIN_POP_CH4_INFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH4.Reg, volatile.LoadUint32(&o.IN_POP_CH4.Reg)&^(0xfff)|value) +} +func (o *DMA_Type) GetIN_POP_CH4_INFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.IN_POP_CH4.Reg) & 0xfff +} +func (o *DMA_Type) SetIN_POP_CH4_INFIFO_POP(value uint32) { + volatile.StoreUint32(&o.IN_POP_CH4.Reg, volatile.LoadUint32(&o.IN_POP_CH4.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetIN_POP_CH4_INFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.IN_POP_CH4.Reg) & 0x1000) >> 12 +} + +// DMA.IN_LINK_CH4: Link descriptor configure and control register of Rx channel 0 +func (o *DMA_Type) SetIN_LINK_CH4_INLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CH4.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetIN_LINK_CH4_INLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_LINK_CH4.Reg) & 0xfffff +} +func (o *DMA_Type) SetIN_LINK_CH4_INLINK_AUTO_RET(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CH4.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetIN_LINK_CH4_INLINK_AUTO_RET() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH4.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetIN_LINK_CH4_INLINK_STOP(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CH4.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetIN_LINK_CH4_INLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH4.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetIN_LINK_CH4_INLINK_START(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CH4.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetIN_LINK_CH4_INLINK_START() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH4.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetIN_LINK_CH4_INLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CH4.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetIN_LINK_CH4_INLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH4.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetIN_LINK_CH4_INLINK_PARK(value uint32) { + volatile.StoreUint32(&o.IN_LINK_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CH4.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetIN_LINK_CH4_INLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.IN_LINK_CH4.Reg) & 0x1000000) >> 24 +} + +// DMA.IN_STATE_CH4: Receive status of Rx channel 0 +func (o *DMA_Type) SetIN_STATE_CH4_INLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetIN_STATE_CH4_INLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0x3ffff +} +func (o *DMA_Type) SetIN_STATE_CH4_IN_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetIN_STATE_CH4_IN_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetIN_STATE_CH4_IN_STATE(value uint32) { + volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetIN_STATE_CH4_IN_STATE() uint32 { + return (volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0x700000) >> 20 +} + +// DMA.IN_SUC_EOF_DES_ADDR_CH4: Inlink descriptor address when EOF occurs of Rx channel 0 +func (o *DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH4.Reg, value) +} +func (o *DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH4.Reg) +} + +// DMA.IN_ERR_EOF_DES_ADDR_CH4: Inlink descriptor address when errors occur of Rx channel 0 +func (o *DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH4.Reg, value) +} +func (o *DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH4.Reg) +} + +// DMA.IN_DSCR_CH4: Current inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_CH4(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_CH4.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_CH4() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_CH4.Reg) +} + +// DMA.IN_DSCR_BF0_CH4: The last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF0_CH4(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF0_CH4.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF0_CH4() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF0_CH4.Reg) +} + +// DMA.IN_DSCR_BF1_CH4: The second-to-last inlink descriptor address of Rx channel 0 +func (o *DMA_Type) SetIN_DSCR_BF1_CH4(value uint32) { + volatile.StoreUint32(&o.IN_DSCR_BF1_CH4.Reg, value) +} +func (o *DMA_Type) GetIN_DSCR_BF1_CH4() uint32 { + return volatile.LoadUint32(&o.IN_DSCR_BF1_CH4.Reg) +} + +// DMA.IN_WIGHT_CH4: Weight register of Rx channel 0 +func (o *DMA_Type) SetIN_WIGHT_CH4_RX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.IN_WIGHT_CH4.Reg, volatile.LoadUint32(&o.IN_WIGHT_CH4.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetIN_WIGHT_CH4_RX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.IN_WIGHT_CH4.Reg) & 0xf00) >> 8 +} + +// DMA.IN_PRI_CH4: Priority register of Rx channel 0 +func (o *DMA_Type) SetIN_PRI_CH4_RX_PRI(value uint32) { + volatile.StoreUint32(&o.IN_PRI_CH4.Reg, volatile.LoadUint32(&o.IN_PRI_CH4.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetIN_PRI_CH4_RX_PRI() uint32 { + return volatile.LoadUint32(&o.IN_PRI_CH4.Reg) & 0xf +} + +// DMA.IN_PERI_SEL_CH4: Peripheral selection of Rx channel 0 +func (o *DMA_Type) SetIN_PERI_SEL_CH4_PERI_IN_SEL(value uint32) { + volatile.StoreUint32(&o.IN_PERI_SEL_CH4.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH4.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetIN_PERI_SEL_CH4_PERI_IN_SEL() uint32 { + return volatile.LoadUint32(&o.IN_PERI_SEL_CH4.Reg) & 0x3f +} + +// DMA.OUT_CONF0_CH4: Configure 0 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF0_CH4_OUT_RST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_CONF0_CH4_OUT_RST() uint32 { + return volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_CONF0_CH4_OUT_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_CONF0_CH4_OUT_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_CONF0_CH4_OUT_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_CONF0_CH4_OUT_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_CONF0_CH4_OUT_EOF_MODE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_CONF0_CH4_OUT_EOF_MODE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_CONF0_CH4_OUTDSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_CONF0_CH4_OUTDSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_CONF0_CH4_OUT_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_CONF0_CH4_OUT_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x20) >> 5 +} + +// DMA.OUT_CONF1_CH4: Configure 1 register of Tx channel 0 +func (o *DMA_Type) SetOUT_CONF1_CH4_OUT_CHECK_OWNER(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH4.Reg)&^(0x1000)|value<<12) +} +func (o *DMA_Type) GetOUT_CONF1_CH4_OUT_CHECK_OWNER() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH4.Reg) & 0x1000) >> 12 +} +func (o *DMA_Type) SetOUT_CONF1_CH4_OUT_EXT_MEM_BK_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_CONF1_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH4.Reg)&^(0x6000)|value<<13) +} +func (o *DMA_Type) GetOUT_CONF1_CH4_OUT_EXT_MEM_BK_SIZE() uint32 { + return (volatile.LoadUint32(&o.OUT_CONF1_CH4.Reg) & 0x6000) >> 13 +} + +// DMA.OUT_INT_RAW_CH4: Raw status interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_RAW_CH4_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH4_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH4_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH4_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH4_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH4_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH4_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH4_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ST_CH4: Masked interrupt of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ST_CH4_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ST_CH4_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH4_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ST_CH4_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ST_CH4_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ST_CH4_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ST_CH4_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ST_CH4_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_ENA_CH4: Interrupt enable bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_ENA_CH4_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH4_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH4_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH4_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH4_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH4_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH4_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH4_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x80) >> 7 +} + +// DMA.OUT_INT_CLR_CH4: Interrupt clear bits of Tx channel 0 +func (o *DMA_Type) SetOUT_INT_CLR_CH4_OUT_DONE(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH4_OUT_DONE() uint32 { + return volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH4_OUT_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH4_OUT_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH4_OUT_DSCR_ERR(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH4_OUT_DSCR_ERR() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH4_OUT_TOTAL_EOF(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH4_OUT_TOTAL_EOF() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_OVF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_OVF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_UDF_L1(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_UDF_L1() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_OVF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_OVF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x40) >> 6 +} +func (o *DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_UDF_L3(value uint32) { + volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x80)|value<<7) +} +func (o *DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_UDF_L3() uint32 { + return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x80) >> 7 +} + +// DMA.OUTFIFO_STATUS_CH4: Transmit FIFO status of Tx channel 0 +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L1() uint32 { + return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x8)|value<<3) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x8) >> 3 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L1(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x7c0)|value<<6) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L1() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x7c0) >> 6 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L2(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x3f800)|value<<11) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L2() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x3f800) >> 11 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x7c0000)|value<<18) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x7c0000) >> 18 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUT_REMAIN_UNDER_1B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUT_REMAIN_UNDER_1B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x800000) >> 23 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUT_REMAIN_UNDER_2B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x1000000)|value<<24) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUT_REMAIN_UNDER_2B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x1000000) >> 24 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUT_REMAIN_UNDER_3B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x2000000)|value<<25) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUT_REMAIN_UNDER_3B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x2000000) >> 25 +} +func (o *DMA_Type) SetOUTFIFO_STATUS_CH4_OUT_REMAIN_UNDER_4B_L3(value uint32) { + volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x4000000)|value<<26) +} +func (o *DMA_Type) GetOUTFIFO_STATUS_CH4_OUT_REMAIN_UNDER_4B_L3() uint32 { + return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x4000000) >> 26 +} + +// DMA.OUT_PUSH_CH4: Push control register of Rx channel 0 +func (o *DMA_Type) SetOUT_PUSH_CH4_OUTFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH4.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg)&^(0x1ff)|value) +} +func (o *DMA_Type) GetOUT_PUSH_CH4_OUTFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg) & 0x1ff +} +func (o *DMA_Type) SetOUT_PUSH_CH4_OUTFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.OUT_PUSH_CH4.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg)&^(0x200)|value<<9) +} +func (o *DMA_Type) GetOUT_PUSH_CH4_OUTFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg) & 0x200) >> 9 +} + +// DMA.OUT_LINK_CH4: Link descriptor configure and control register of Tx channel 0 +func (o *DMA_Type) SetOUT_LINK_CH4_OUTLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CH4.Reg)&^(0xfffff)|value) +} +func (o *DMA_Type) GetOUT_LINK_CH4_OUTLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_LINK_CH4.Reg) & 0xfffff +} +func (o *DMA_Type) SetOUT_LINK_CH4_OUTLINK_STOP(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CH4.Reg)&^(0x100000)|value<<20) +} +func (o *DMA_Type) GetOUT_LINK_CH4_OUTLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH4.Reg) & 0x100000) >> 20 +} +func (o *DMA_Type) SetOUT_LINK_CH4_OUTLINK_START(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CH4.Reg)&^(0x200000)|value<<21) +} +func (o *DMA_Type) GetOUT_LINK_CH4_OUTLINK_START() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH4.Reg) & 0x200000) >> 21 +} +func (o *DMA_Type) SetOUT_LINK_CH4_OUTLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CH4.Reg)&^(0x400000)|value<<22) +} +func (o *DMA_Type) GetOUT_LINK_CH4_OUTLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH4.Reg) & 0x400000) >> 22 +} +func (o *DMA_Type) SetOUT_LINK_CH4_OUTLINK_PARK(value uint32) { + volatile.StoreUint32(&o.OUT_LINK_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CH4.Reg)&^(0x800000)|value<<23) +} +func (o *DMA_Type) GetOUT_LINK_CH4_OUTLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.OUT_LINK_CH4.Reg) & 0x800000) >> 23 +} + +// DMA.OUT_STATE_CH4: Transmit status of Tx channel 0 +func (o *DMA_Type) SetOUT_STATE_CH4_OUTLINK_DSCR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH4.Reg, volatile.LoadUint32(&o.OUT_STATE_CH4.Reg)&^(0x3ffff)|value) +} +func (o *DMA_Type) GetOUT_STATE_CH4_OUTLINK_DSCR_ADDR() uint32 { + return volatile.LoadUint32(&o.OUT_STATE_CH4.Reg) & 0x3ffff +} +func (o *DMA_Type) SetOUT_STATE_CH4_OUT_DSCR_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH4.Reg, volatile.LoadUint32(&o.OUT_STATE_CH4.Reg)&^(0xc0000)|value<<18) +} +func (o *DMA_Type) GetOUT_STATE_CH4_OUT_DSCR_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH4.Reg) & 0xc0000) >> 18 +} +func (o *DMA_Type) SetOUT_STATE_CH4_OUT_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_STATE_CH4.Reg, volatile.LoadUint32(&o.OUT_STATE_CH4.Reg)&^(0x700000)|value<<20) +} +func (o *DMA_Type) GetOUT_STATE_CH4_OUT_STATE() uint32 { + return (volatile.LoadUint32(&o.OUT_STATE_CH4.Reg) & 0x700000) >> 20 +} + +// DMA.OUT_EOF_DES_ADDR_CH4: Outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_DES_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH4.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_DES_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH4.Reg) +} + +// DMA.OUT_EOF_BFR_DES_ADDR_CH4: The last outlink descriptor address when EOF occurs of Tx channel 0 +func (o *DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH4.Reg, value) +} +func (o *DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH4.Reg) +} + +// DMA.OUT_DSCR_CH4: Current inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_CH4.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_CH4.Reg) +} + +// DMA.OUT_DSCR_BF0_CH4: The last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF0_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF0_CH4.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF0_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH4.Reg) +} + +// DMA.OUT_DSCR_BF1_CH4: The second-to-last inlink descriptor address of Tx channel 0 +func (o *DMA_Type) SetOUT_DSCR_BF1_CH4(value uint32) { + volatile.StoreUint32(&o.OUT_DSCR_BF1_CH4.Reg, value) +} +func (o *DMA_Type) GetOUT_DSCR_BF1_CH4() uint32 { + return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH4.Reg) +} + +// DMA.OUT_WIGHT_CH4: Weight register of Rx channel 0 +func (o *DMA_Type) SetOUT_WIGHT_CH4_TX_WEIGHT(value uint32) { + volatile.StoreUint32(&o.OUT_WIGHT_CH4.Reg, volatile.LoadUint32(&o.OUT_WIGHT_CH4.Reg)&^(0xf00)|value<<8) +} +func (o *DMA_Type) GetOUT_WIGHT_CH4_TX_WEIGHT() uint32 { + return (volatile.LoadUint32(&o.OUT_WIGHT_CH4.Reg) & 0xf00) >> 8 +} + +// DMA.OUT_PRI_CH4: Priority register of Tx channel 0. +func (o *DMA_Type) SetOUT_PRI_CH4_TX_PRI(value uint32) { + volatile.StoreUint32(&o.OUT_PRI_CH4.Reg, volatile.LoadUint32(&o.OUT_PRI_CH4.Reg)&^(0xf)|value) +} +func (o *DMA_Type) GetOUT_PRI_CH4_TX_PRI() uint32 { + return volatile.LoadUint32(&o.OUT_PRI_CH4.Reg) & 0xf +} + +// DMA.OUT_PERI_SEL_CH4: Peripheral selection of Tx channel 0 +func (o *DMA_Type) SetOUT_PERI_SEL_CH4_PERI_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.OUT_PERI_SEL_CH4.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH4.Reg)&^(0x3f)|value) +} +func (o *DMA_Type) GetOUT_PERI_SEL_CH4_PERI_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.OUT_PERI_SEL_CH4.Reg) & 0x3f +} + +// DMA.AHB_TEST: reserved +func (o *DMA_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7 +} +func (o *DMA_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *DMA_Type) GetAHB_TEST_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4 +} + +// DMA.PD_CONF: reserved +func (o *DMA_Type) SetPD_CONF_DMA_RAM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetPD_CONF_DMA_RAM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x10) >> 4 +} +func (o *DMA_Type) SetPD_CONF_DMA_RAM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x20)|value<<5) +} +func (o *DMA_Type) GetPD_CONF_DMA_RAM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x20) >> 5 +} +func (o *DMA_Type) SetPD_CONF_DMA_RAM_CLK_FO(value uint32) { + volatile.StoreUint32(&o.PD_CONF.Reg, volatile.LoadUint32(&o.PD_CONF.Reg)&^(0x40)|value<<6) +} +func (o *DMA_Type) GetPD_CONF_DMA_RAM_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.PD_CONF.Reg) & 0x40) >> 6 +} + +// DMA.MISC_CONF: MISC register +func (o *DMA_Type) SetMISC_CONF_AHBM_RST_INTER(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetMISC_CONF_AHBM_RST_INTER() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} +func (o *DMA_Type) SetMISC_CONF_AHBM_RST_EXTER(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x2)|value<<1) +} +func (o *DMA_Type) GetMISC_CONF_AHBM_RST_EXTER() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x2) >> 1 +} +func (o *DMA_Type) SetMISC_CONF_ARB_PRI_DIS(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x4)|value<<2) +} +func (o *DMA_Type) GetMISC_CONF_ARB_PRI_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x4) >> 2 +} +func (o *DMA_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x10)|value<<4) +} +func (o *DMA_Type) GetMISC_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x10) >> 4 +} + +// DMA.IN_SRAM_SIZE_CH0: Receive L2 FIFO depth of Rx channel 0 +func (o *DMA_Type) SetIN_SRAM_SIZE_CH0_IN_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_SRAM_SIZE_CH0.Reg, volatile.LoadUint32(&o.IN_SRAM_SIZE_CH0.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetIN_SRAM_SIZE_CH0_IN_SIZE() uint32 { + return volatile.LoadUint32(&o.IN_SRAM_SIZE_CH0.Reg) & 0x7f +} + +// DMA.OUT_SRAM_SIZE_CH0: Transmit L2 FIFO depth of Tx channel 0 +func (o *DMA_Type) SetOUT_SRAM_SIZE_CH0_OUT_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_SRAM_SIZE_CH0.Reg, volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH0.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetOUT_SRAM_SIZE_CH0_OUT_SIZE() uint32 { + return volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH0.Reg) & 0x7f +} + +// DMA.IN_SRAM_SIZE_CH1: Receive L2 FIFO depth of Rx channel 0 +func (o *DMA_Type) SetIN_SRAM_SIZE_CH1_IN_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_SRAM_SIZE_CH1.Reg, volatile.LoadUint32(&o.IN_SRAM_SIZE_CH1.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetIN_SRAM_SIZE_CH1_IN_SIZE() uint32 { + return volatile.LoadUint32(&o.IN_SRAM_SIZE_CH1.Reg) & 0x7f +} + +// DMA.OUT_SRAM_SIZE_CH1: Transmit L2 FIFO depth of Tx channel 0 +func (o *DMA_Type) SetOUT_SRAM_SIZE_CH1_OUT_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_SRAM_SIZE_CH1.Reg, volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH1.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetOUT_SRAM_SIZE_CH1_OUT_SIZE() uint32 { + return volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH1.Reg) & 0x7f +} + +// DMA.IN_SRAM_SIZE_CH2: Receive L2 FIFO depth of Rx channel 0 +func (o *DMA_Type) SetIN_SRAM_SIZE_CH2_IN_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_SRAM_SIZE_CH2.Reg, volatile.LoadUint32(&o.IN_SRAM_SIZE_CH2.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetIN_SRAM_SIZE_CH2_IN_SIZE() uint32 { + return volatile.LoadUint32(&o.IN_SRAM_SIZE_CH2.Reg) & 0x7f +} + +// DMA.OUT_SRAM_SIZE_CH2: Transmit L2 FIFO depth of Tx channel 0 +func (o *DMA_Type) SetOUT_SRAM_SIZE_CH2_OUT_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_SRAM_SIZE_CH2.Reg, volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH2.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetOUT_SRAM_SIZE_CH2_OUT_SIZE() uint32 { + return volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH2.Reg) & 0x7f +} + +// DMA.IN_SRAM_SIZE_CH3: Receive L2 FIFO depth of Rx channel 0 +func (o *DMA_Type) SetIN_SRAM_SIZE_CH3_IN_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_SRAM_SIZE_CH3.Reg, volatile.LoadUint32(&o.IN_SRAM_SIZE_CH3.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetIN_SRAM_SIZE_CH3_IN_SIZE() uint32 { + return volatile.LoadUint32(&o.IN_SRAM_SIZE_CH3.Reg) & 0x7f +} + +// DMA.OUT_SRAM_SIZE_CH3: Transmit L2 FIFO depth of Tx channel 0 +func (o *DMA_Type) SetOUT_SRAM_SIZE_CH3_OUT_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_SRAM_SIZE_CH3.Reg, volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH3.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetOUT_SRAM_SIZE_CH3_OUT_SIZE() uint32 { + return volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH3.Reg) & 0x7f +} + +// DMA.IN_SRAM_SIZE_CH4: Receive L2 FIFO depth of Rx channel 0 +func (o *DMA_Type) SetIN_SRAM_SIZE_CH4_IN_SIZE(value uint32) { + volatile.StoreUint32(&o.IN_SRAM_SIZE_CH4.Reg, volatile.LoadUint32(&o.IN_SRAM_SIZE_CH4.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetIN_SRAM_SIZE_CH4_IN_SIZE() uint32 { + return volatile.LoadUint32(&o.IN_SRAM_SIZE_CH4.Reg) & 0x7f +} + +// DMA.OUT_SRAM_SIZE_CH4: Transmit L2 FIFO depth of Tx channel 0 +func (o *DMA_Type) SetOUT_SRAM_SIZE_CH4_OUT_SIZE(value uint32) { + volatile.StoreUint32(&o.OUT_SRAM_SIZE_CH4.Reg, volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH4.Reg)&^(0x7f)|value) +} +func (o *DMA_Type) GetOUT_SRAM_SIZE_CH4_OUT_SIZE() uint32 { + return volatile.LoadUint32(&o.OUT_SRAM_SIZE_CH4.Reg) & 0x7f +} + +// DMA.EXTMEM_REJECT_ADDR: Reject address accessing external RAM +func (o *DMA_Type) SetEXTMEM_REJECT_ADDR(value uint32) { + volatile.StoreUint32(&o.EXTMEM_REJECT_ADDR.Reg, value) +} +func (o *DMA_Type) GetEXTMEM_REJECT_ADDR() uint32 { + return volatile.LoadUint32(&o.EXTMEM_REJECT_ADDR.Reg) +} + +// DMA.EXTMEM_REJECT_ST: Reject status accessing external RAM +func (o *DMA_Type) SetEXTMEM_REJECT_ST_EXTMEM_REJECT_ATRR(value uint32) { + volatile.StoreUint32(&o.EXTMEM_REJECT_ST.Reg, volatile.LoadUint32(&o.EXTMEM_REJECT_ST.Reg)&^(0x3)|value) +} +func (o *DMA_Type) GetEXTMEM_REJECT_ST_EXTMEM_REJECT_ATRR() uint32 { + return volatile.LoadUint32(&o.EXTMEM_REJECT_ST.Reg) & 0x3 +} +func (o *DMA_Type) SetEXTMEM_REJECT_ST_EXTMEM_REJECT_CHANNEL_NUM(value uint32) { + volatile.StoreUint32(&o.EXTMEM_REJECT_ST.Reg, volatile.LoadUint32(&o.EXTMEM_REJECT_ST.Reg)&^(0x3c)|value<<2) +} +func (o *DMA_Type) GetEXTMEM_REJECT_ST_EXTMEM_REJECT_CHANNEL_NUM() uint32 { + return (volatile.LoadUint32(&o.EXTMEM_REJECT_ST.Reg) & 0x3c) >> 2 +} +func (o *DMA_Type) SetEXTMEM_REJECT_ST_EXTMEM_REJECT_PERI_NUM(value uint32) { + volatile.StoreUint32(&o.EXTMEM_REJECT_ST.Reg, volatile.LoadUint32(&o.EXTMEM_REJECT_ST.Reg)&^(0xfc0)|value<<6) +} +func (o *DMA_Type) GetEXTMEM_REJECT_ST_EXTMEM_REJECT_PERI_NUM() uint32 { + return (volatile.LoadUint32(&o.EXTMEM_REJECT_ST.Reg) & 0xfc0) >> 6 +} + +// DMA.EXTMEM_REJECT_INT_RAW: Raw interrupt status of external RAM permission +func (o *DMA_Type) SetEXTMEM_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.EXTMEM_REJECT_INT_RAW.Reg, volatile.LoadUint32(&o.EXTMEM_REJECT_INT_RAW.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetEXTMEM_REJECT_INT_RAW() uint32 { + return volatile.LoadUint32(&o.EXTMEM_REJECT_INT_RAW.Reg) & 0x1 +} + +// DMA.EXTMEM_REJECT_INT_ST: Masked interrupt status of external RAM permission +func (o *DMA_Type) SetEXTMEM_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.EXTMEM_REJECT_INT_ST.Reg, volatile.LoadUint32(&o.EXTMEM_REJECT_INT_ST.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetEXTMEM_REJECT_INT_ST() uint32 { + return volatile.LoadUint32(&o.EXTMEM_REJECT_INT_ST.Reg) & 0x1 +} + +// DMA.EXTMEM_REJECT_INT_ENA: Interrupt enable bits of external RAM permission +func (o *DMA_Type) SetEXTMEM_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.EXTMEM_REJECT_INT_ENA.Reg, volatile.LoadUint32(&o.EXTMEM_REJECT_INT_ENA.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetEXTMEM_REJECT_INT_ENA() uint32 { + return volatile.LoadUint32(&o.EXTMEM_REJECT_INT_ENA.Reg) & 0x1 +} + +// DMA.EXTMEM_REJECT_INT_CLR: Interrupt clear bits of external RAM permission +func (o *DMA_Type) SetEXTMEM_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.EXTMEM_REJECT_INT_CLR.Reg, volatile.LoadUint32(&o.EXTMEM_REJECT_INT_CLR.Reg)&^(0x1)|value) +} +func (o *DMA_Type) GetEXTMEM_REJECT_INT_CLR() uint32 { + return volatile.LoadUint32(&o.EXTMEM_REJECT_INT_CLR.Reg) & 0x1 +} + +// DMA.DATE: Version control register +func (o *DMA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *DMA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Digital Signature +type DS_Type struct { + C_MEM [1584]volatile.Register8 // 0x0 + IV_0 volatile.Register32 // 0x630 + IV_1 volatile.Register32 // 0x634 + IV_2 volatile.Register32 // 0x638 + IV_3 volatile.Register32 // 0x63C + _ [448]byte + X_MEM [512]volatile.Register8 // 0x800 + Z_MEM [512]volatile.Register8 // 0xA00 + _ [512]byte + SET_START volatile.Register32 // 0xE00 + SET_ME volatile.Register32 // 0xE04 + SET_FINISH volatile.Register32 // 0xE08 + QUERY_BUSY volatile.Register32 // 0xE0C + QUERY_KEY_WRONG volatile.Register32 // 0xE10 + QUERY_CHECK volatile.Register32 // 0xE14 + _ [8]byte + DATE volatile.Register32 // 0xE20 +} + +// DS.IV_0: IV block data +func (o *DS_Type) SetIV_0(value uint32) { + volatile.StoreUint32(&o.IV_0.Reg, value) +} +func (o *DS_Type) GetIV_0() uint32 { + return volatile.LoadUint32(&o.IV_0.Reg) +} + +// DS.IV_1: IV block data +func (o *DS_Type) SetIV_1(value uint32) { + volatile.StoreUint32(&o.IV_1.Reg, value) +} +func (o *DS_Type) GetIV_1() uint32 { + return volatile.LoadUint32(&o.IV_1.Reg) +} + +// DS.IV_2: IV block data +func (o *DS_Type) SetIV_2(value uint32) { + volatile.StoreUint32(&o.IV_2.Reg, value) +} +func (o *DS_Type) GetIV_2() uint32 { + return volatile.LoadUint32(&o.IV_2.Reg) +} + +// DS.IV_3: IV block data +func (o *DS_Type) SetIV_3(value uint32) { + volatile.StoreUint32(&o.IV_3.Reg, value) +} +func (o *DS_Type) GetIV_3() uint32 { + return volatile.LoadUint32(&o.IV_3.Reg) +} + +// DS.SET_START: Activates the DS peripheral +func (o *DS_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// DS.SET_ME: Starts DS operation +func (o *DS_Type) SetSET_ME(value uint32) { + volatile.StoreUint32(&o.SET_ME.Reg, volatile.LoadUint32(&o.SET_ME.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_ME() uint32 { + return volatile.LoadUint32(&o.SET_ME.Reg) & 0x1 +} + +// DS.SET_FINISH: Ends DS operation +func (o *DS_Type) SetSET_FINISH(value uint32) { + volatile.StoreUint32(&o.SET_FINISH.Reg, volatile.LoadUint32(&o.SET_FINISH.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetSET_FINISH() uint32 { + return volatile.LoadUint32(&o.SET_FINISH.Reg) & 0x1 +} + +// DS.QUERY_BUSY: Status of the DS perihperal +func (o *DS_Type) SetQUERY_BUSY(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_BUSY() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// DS.QUERY_KEY_WRONG: Checks the reason why DS_KEY is not ready +func (o *DS_Type) SetQUERY_KEY_WRONG(value uint32) { + volatile.StoreUint32(&o.QUERY_KEY_WRONG.Reg, volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg)&^(0xf)|value) +} +func (o *DS_Type) GetQUERY_KEY_WRONG() uint32 { + return volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg) & 0xf +} + +// DS.QUERY_CHECK: Queries DS check result +func (o *DS_Type) SetQUERY_CHECK_MD_ERROR(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x1)|value) +} +func (o *DS_Type) GetQUERY_CHECK_MD_ERROR() uint32 { + return volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x1 +} +func (o *DS_Type) SetQUERY_CHECK_PADDING_BAD(value uint32) { + volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x2)|value<<1) +} +func (o *DS_Type) GetQUERY_CHECK_PADDING_BAD() uint32 { + return (volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x2) >> 1 +} + +// DS.DATE: DS version control register +func (o *DS_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *DS_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// eFuse Controller +type EFUSE_Type struct { + PGM_DATA0 volatile.Register32 // 0x0 + PGM_DATA1 volatile.Register32 // 0x4 + PGM_DATA2 volatile.Register32 // 0x8 + PGM_DATA3 volatile.Register32 // 0xC + PGM_DATA4 volatile.Register32 // 0x10 + PGM_DATA5 volatile.Register32 // 0x14 + PGM_DATA6 volatile.Register32 // 0x18 + PGM_DATA7 volatile.Register32 // 0x1C + PGM_CHECK_VALUE0 volatile.Register32 // 0x20 + PGM_CHECK_VALUE1 volatile.Register32 // 0x24 + PGM_CHECK_VALUE2 volatile.Register32 // 0x28 + RD_WR_DIS volatile.Register32 // 0x2C + RD_REPEAT_DATA0 volatile.Register32 // 0x30 + RD_REPEAT_DATA1 volatile.Register32 // 0x34 + RD_REPEAT_DATA2 volatile.Register32 // 0x38 + RD_REPEAT_DATA3 volatile.Register32 // 0x3C + RD_REPEAT_DATA4 volatile.Register32 // 0x40 + RD_MAC_SPI_SYS_0 volatile.Register32 // 0x44 + RD_MAC_SPI_SYS_1 volatile.Register32 // 0x48 + RD_MAC_SPI_SYS_2 volatile.Register32 // 0x4C + RD_MAC_SPI_SYS_3 volatile.Register32 // 0x50 + RD_MAC_SPI_SYS_4 volatile.Register32 // 0x54 + RD_MAC_SPI_SYS_5 volatile.Register32 // 0x58 + RD_SYS_PART1_DATA0 volatile.Register32 // 0x5C + RD_SYS_PART1_DATA1 volatile.Register32 // 0x60 + RD_SYS_PART1_DATA2 volatile.Register32 // 0x64 + RD_SYS_PART1_DATA3 volatile.Register32 // 0x68 + RD_SYS_PART1_DATA4 volatile.Register32 // 0x6C + RD_SYS_PART1_DATA5 volatile.Register32 // 0x70 + RD_SYS_PART1_DATA6 volatile.Register32 // 0x74 + RD_SYS_PART1_DATA7 volatile.Register32 // 0x78 + RD_USR_DATA0 volatile.Register32 // 0x7C + RD_USR_DATA1 volatile.Register32 // 0x80 + RD_USR_DATA2 volatile.Register32 // 0x84 + RD_USR_DATA3 volatile.Register32 // 0x88 + RD_USR_DATA4 volatile.Register32 // 0x8C + RD_USR_DATA5 volatile.Register32 // 0x90 + RD_USR_DATA6 volatile.Register32 // 0x94 + RD_USR_DATA7 volatile.Register32 // 0x98 + RD_KEY0_DATA0 volatile.Register32 // 0x9C + RD_KEY0_DATA1 volatile.Register32 // 0xA0 + RD_KEY0_DATA2 volatile.Register32 // 0xA4 + RD_KEY0_DATA3 volatile.Register32 // 0xA8 + RD_KEY0_DATA4 volatile.Register32 // 0xAC + RD_KEY0_DATA5 volatile.Register32 // 0xB0 + RD_KEY0_DATA6 volatile.Register32 // 0xB4 + RD_KEY0_DATA7 volatile.Register32 // 0xB8 + RD_KEY1_DATA0 volatile.Register32 // 0xBC + RD_KEY1_DATA1 volatile.Register32 // 0xC0 + RD_KEY1_DATA2 volatile.Register32 // 0xC4 + RD_KEY1_DATA3 volatile.Register32 // 0xC8 + RD_KEY1_DATA4 volatile.Register32 // 0xCC + RD_KEY1_DATA5 volatile.Register32 // 0xD0 + RD_KEY1_DATA6 volatile.Register32 // 0xD4 + RD_KEY1_DATA7 volatile.Register32 // 0xD8 + RD_KEY2_DATA0 volatile.Register32 // 0xDC + RD_KEY2_DATA1 volatile.Register32 // 0xE0 + RD_KEY2_DATA2 volatile.Register32 // 0xE4 + RD_KEY2_DATA3 volatile.Register32 // 0xE8 + RD_KEY2_DATA4 volatile.Register32 // 0xEC + RD_KEY2_DATA5 volatile.Register32 // 0xF0 + RD_KEY2_DATA6 volatile.Register32 // 0xF4 + RD_KEY2_DATA7 volatile.Register32 // 0xF8 + RD_KEY3_DATA0 volatile.Register32 // 0xFC + RD_KEY3_DATA1 volatile.Register32 // 0x100 + RD_KEY3_DATA2 volatile.Register32 // 0x104 + RD_KEY3_DATA3 volatile.Register32 // 0x108 + RD_KEY3_DATA4 volatile.Register32 // 0x10C + RD_KEY3_DATA5 volatile.Register32 // 0x110 + RD_KEY3_DATA6 volatile.Register32 // 0x114 + RD_KEY3_DATA7 volatile.Register32 // 0x118 + RD_KEY4_DATA0 volatile.Register32 // 0x11C + RD_KEY4_DATA1 volatile.Register32 // 0x120 + RD_KEY4_DATA2 volatile.Register32 // 0x124 + RD_KEY4_DATA3 volatile.Register32 // 0x128 + RD_KEY4_DATA4 volatile.Register32 // 0x12C + RD_KEY4_DATA5 volatile.Register32 // 0x130 + RD_KEY4_DATA6 volatile.Register32 // 0x134 + RD_KEY4_DATA7 volatile.Register32 // 0x138 + RD_KEY5_DATA0 volatile.Register32 // 0x13C + RD_KEY5_DATA1 volatile.Register32 // 0x140 + RD_KEY5_DATA2 volatile.Register32 // 0x144 + RD_KEY5_DATA3 volatile.Register32 // 0x148 + RD_KEY5_DATA4 volatile.Register32 // 0x14C + RD_KEY5_DATA5 volatile.Register32 // 0x150 + RD_KEY5_DATA6 volatile.Register32 // 0x154 + RD_KEY5_DATA7 volatile.Register32 // 0x158 + RD_SYS_PART2_DATA0 volatile.Register32 // 0x15C + RD_SYS_PART2_DATA1 volatile.Register32 // 0x160 + RD_SYS_PART2_DATA2 volatile.Register32 // 0x164 + RD_SYS_PART2_DATA3 volatile.Register32 // 0x168 + RD_SYS_PART2_DATA4 volatile.Register32 // 0x16C + RD_SYS_PART2_DATA5 volatile.Register32 // 0x170 + RD_SYS_PART2_DATA6 volatile.Register32 // 0x174 + RD_SYS_PART2_DATA7 volatile.Register32 // 0x178 + RD_REPEAT_ERR0 volatile.Register32 // 0x17C + RD_REPEAT_ERR1 volatile.Register32 // 0x180 + RD_REPEAT_ERR2 volatile.Register32 // 0x184 + RD_REPEAT_ERR3 volatile.Register32 // 0x188 + _ [4]byte + RD_REPEAT_ERR4 volatile.Register32 // 0x190 + _ [44]byte + RD_RS_ERR0 volatile.Register32 // 0x1C0 + RD_RS_ERR1 volatile.Register32 // 0x1C4 + CLK volatile.Register32 // 0x1C8 + CONF volatile.Register32 // 0x1CC + STATUS volatile.Register32 // 0x1D0 + CMD volatile.Register32 // 0x1D4 + INT_RAW volatile.Register32 // 0x1D8 + INT_ST volatile.Register32 // 0x1DC + INT_ENA volatile.Register32 // 0x1E0 + INT_CLR volatile.Register32 // 0x1E4 + DAC_CONF volatile.Register32 // 0x1E8 + RD_TIM_CONF volatile.Register32 // 0x1EC + _ [4]byte + WR_TIM_CONF1 volatile.Register32 // 0x1F4 + WR_TIM_CONF2 volatile.Register32 // 0x1F8 + DATE volatile.Register32 // 0x1FC +} + +// EFUSE.PGM_DATA0: Register 0 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA0(value uint32) { + volatile.StoreUint32(&o.PGM_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA0() uint32 { + return volatile.LoadUint32(&o.PGM_DATA0.Reg) +} + +// EFUSE.PGM_DATA1: Register 1 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA1(value uint32) { + volatile.StoreUint32(&o.PGM_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA1() uint32 { + return volatile.LoadUint32(&o.PGM_DATA1.Reg) +} + +// EFUSE.PGM_DATA2: Register 2 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA2(value uint32) { + volatile.StoreUint32(&o.PGM_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA2() uint32 { + return volatile.LoadUint32(&o.PGM_DATA2.Reg) +} + +// EFUSE.PGM_DATA3: Register 3 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA3(value uint32) { + volatile.StoreUint32(&o.PGM_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA3() uint32 { + return volatile.LoadUint32(&o.PGM_DATA3.Reg) +} + +// EFUSE.PGM_DATA4: Register 4 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA4(value uint32) { + volatile.StoreUint32(&o.PGM_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA4() uint32 { + return volatile.LoadUint32(&o.PGM_DATA4.Reg) +} + +// EFUSE.PGM_DATA5: Register 5 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA5(value uint32) { + volatile.StoreUint32(&o.PGM_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA5() uint32 { + return volatile.LoadUint32(&o.PGM_DATA5.Reg) +} + +// EFUSE.PGM_DATA6: Register 6 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA6(value uint32) { + volatile.StoreUint32(&o.PGM_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA6() uint32 { + return volatile.LoadUint32(&o.PGM_DATA6.Reg) +} + +// EFUSE.PGM_DATA7: Register 7 that stores data to be programmed. +func (o *EFUSE_Type) SetPGM_DATA7(value uint32) { + volatile.StoreUint32(&o.PGM_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetPGM_DATA7() uint32 { + return volatile.LoadUint32(&o.PGM_DATA7.Reg) +} + +// EFUSE.PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE0(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE0.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE0() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE0.Reg) +} + +// EFUSE.PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE1(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE1.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE1() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE1.Reg) +} + +// EFUSE.PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. +func (o *EFUSE_Type) SetPGM_CHECK_VALUE2(value uint32) { + volatile.StoreUint32(&o.PGM_CHECK_VALUE2.Reg, value) +} +func (o *EFUSE_Type) GetPGM_CHECK_VALUE2() uint32 { + return volatile.LoadUint32(&o.PGM_CHECK_VALUE2.Reg) +} + +// EFUSE.RD_WR_DIS: BLOCK0 data register 0. +func (o *EFUSE_Type) SetRD_WR_DIS(value uint32) { + volatile.StoreUint32(&o.RD_WR_DIS.Reg, value) +} +func (o *EFUSE_Type) GetRD_WR_DIS() uint32 { + return volatile.LoadUint32(&o.RD_WR_DIS.Reg) +} + +// EFUSE.RD_REPEAT_DATA0: BLOCK0 data register 1. +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RD_DIS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RD_DIS() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_RTC_RAM_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_RTC_RAM_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DCACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DCACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_CAN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_CAN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_APP_CPU(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_APP_CPU() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SOFT_DIS_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SOFT_DIS_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_PAD_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_PAD_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DREFL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DREFL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_EXT_PHY_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_EXT_PHY_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_BTLC_GPIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_BTLC_GPIO_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_VDD_SPI_MODECURLIM(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_VDD_SPI_MODECURLIM() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA0_VDD_SPI_DREFH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA0_VDD_SPI_DREFH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_DATA1: BLOCK0 data register 2. +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_DREFM(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_DREFM() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_DREFL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xc)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_DREFL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xc) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_XPD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_XPD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_TIEH(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_TIEH() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_FORCE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_FORCE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_EN_INIT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_EN_INIT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_ENCURLIM(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_ENCURLIM() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_DCURLIM(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xe00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_DCURLIM() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xe00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_INIT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x3000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_INIT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x3000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_VDD_SPI_DCAP(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_VDD_SPI_DCAP() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_WDT_DELAY_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_WDT_DELAY_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA2: BLOCK0 data register 3. +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_2() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_3(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_3() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_4(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_4() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_5(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_5() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_RPT4_RESERVED0(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_RPT4_RESERVED0() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_DIS_USB_JTAG(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_DIS_USB_JTAG() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_DIS_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_DIS_USB_DEVICE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_STRAP_JTAG_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x1000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_STRAP_JTAG_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x1000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_USB_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_USB_PHY_SEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_POWER_GLITCH_DSENSE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xc000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_POWER_GLITCH_DSENSE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xc000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_TPUW(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_TPUW() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_DATA3: BLOCK0 data register 4. +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CHANNEL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CHANNEL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FLASH_ECC_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FLASH_ECC_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CONTROL(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CONTROL() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_PIN_POWER_SELECTION(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_PIN_POWER_SELECTION() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FLASH_TYPE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FLASH_TYPE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FLASH_PAGE_SIZE(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc00)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FLASH_PAGE_SIZE() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc00) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FLASH_ECC_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FLASH_ECC_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FORCE_SEND_RESUME(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FORCE_SEND_RESUME() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_VERSION(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x3fffc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_VERSION() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x3fffc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_POWERGLITCH_EN(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x40000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_POWERGLITCH_EN() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x40000000) >> 30 +} +func (o *EFUSE_Type) SetRD_REPEAT_DATA3_RPT4_RESERVED1(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x80000000)|value<<31) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA3_RPT4_RESERVED1() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x80000000) >> 31 +} + +// EFUSE.RD_REPEAT_DATA4: BLOCK0 data register 5. +func (o *EFUSE_Type) SetRD_REPEAT_DATA4_RPT4_RESERVED2(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_DATA4_RPT4_RESERVED2() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xffffff +} + +// EFUSE.RD_MAC_SPI_SYS_0: BLOCK1 data register 0. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_0.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_0() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_0.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_1: BLOCK1 data register 1. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_1_MAC_1(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_1_MAC_1() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg) & 0xffff +} +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_1_SPI_PAD_CONF_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg)&^(0xffff0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_1_SPI_PAD_CONF_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SPI_SYS_1.Reg) & 0xffff0000) >> 16 +} + +// EFUSE.RD_MAC_SPI_SYS_2: BLOCK1 data register 2. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_2(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_2.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_2() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_2.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_3: BLOCK1 data register 3. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_3_SPI_PAD_CONF_2(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg)&^(0x3ffff)|value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_3_SPI_PAD_CONF_2() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg) & 0x3ffff +} +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_3_SYS_DATA_PART0_0(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg)&^(0xfffc0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_3_SYS_DATA_PART0_0() uint32 { + return (volatile.LoadUint32(&o.RD_MAC_SPI_SYS_3.Reg) & 0xfffc0000) >> 18 +} + +// EFUSE.RD_MAC_SPI_SYS_4: BLOCK1 data register 4. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_4(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_4.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_4() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_4.Reg) +} + +// EFUSE.RD_MAC_SPI_SYS_5: BLOCK1 data register 5. +func (o *EFUSE_Type) SetRD_MAC_SPI_SYS_5(value uint32) { + volatile.StoreUint32(&o.RD_MAC_SPI_SYS_5.Reg, value) +} +func (o *EFUSE_Type) GetRD_MAC_SPI_SYS_5() uint32 { + return volatile.LoadUint32(&o.RD_MAC_SPI_SYS_5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA0: Register 0 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA1: Register 1 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA2: Register 2 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA3: Register 3 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA4: Register 4 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA5: Register 5 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA6: Register 6 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART1_DATA7: Register 7 of BLOCK2 (system). +func (o *EFUSE_Type) SetRD_SYS_PART1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART1_DATA7.Reg) +} + +// EFUSE.RD_USR_DATA0: Register 0 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA0.Reg) +} + +// EFUSE.RD_USR_DATA1: Register 1 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA1.Reg) +} + +// EFUSE.RD_USR_DATA2: Register 2 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA2.Reg) +} + +// EFUSE.RD_USR_DATA3: Register 3 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA3.Reg) +} + +// EFUSE.RD_USR_DATA4: Register 4 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA4.Reg) +} + +// EFUSE.RD_USR_DATA5: Register 5 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA5.Reg) +} + +// EFUSE.RD_USR_DATA6: Register 6 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA6.Reg) +} + +// EFUSE.RD_USR_DATA7: Register 7 of BLOCK3 (user). +func (o *EFUSE_Type) SetRD_USR_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_USR_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_USR_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_USR_DATA7.Reg) +} + +// EFUSE.RD_KEY0_DATA0: Register 0 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA0.Reg) +} + +// EFUSE.RD_KEY0_DATA1: Register 1 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA1.Reg) +} + +// EFUSE.RD_KEY0_DATA2: Register 2 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA2.Reg) +} + +// EFUSE.RD_KEY0_DATA3: Register 3 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA3.Reg) +} + +// EFUSE.RD_KEY0_DATA4: Register 4 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA4.Reg) +} + +// EFUSE.RD_KEY0_DATA5: Register 5 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA5.Reg) +} + +// EFUSE.RD_KEY0_DATA6: Register 6 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA6.Reg) +} + +// EFUSE.RD_KEY0_DATA7: Register 7 of BLOCK4 (KEY0). +func (o *EFUSE_Type) SetRD_KEY0_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY0_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY0_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY0_DATA7.Reg) +} + +// EFUSE.RD_KEY1_DATA0: Register 0 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA0.Reg) +} + +// EFUSE.RD_KEY1_DATA1: Register 1 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA1.Reg) +} + +// EFUSE.RD_KEY1_DATA2: Register 2 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA2.Reg) +} + +// EFUSE.RD_KEY1_DATA3: Register 3 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA3.Reg) +} + +// EFUSE.RD_KEY1_DATA4: Register 4 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA4.Reg) +} + +// EFUSE.RD_KEY1_DATA5: Register 5 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA5.Reg) +} + +// EFUSE.RD_KEY1_DATA6: Register 6 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA6.Reg) +} + +// EFUSE.RD_KEY1_DATA7: Register 7 of BLOCK5 (KEY1). +func (o *EFUSE_Type) SetRD_KEY1_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY1_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY1_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY1_DATA7.Reg) +} + +// EFUSE.RD_KEY2_DATA0: Register 0 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA0.Reg) +} + +// EFUSE.RD_KEY2_DATA1: Register 1 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA1.Reg) +} + +// EFUSE.RD_KEY2_DATA2: Register 2 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA2.Reg) +} + +// EFUSE.RD_KEY2_DATA3: Register 3 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA3.Reg) +} + +// EFUSE.RD_KEY2_DATA4: Register 4 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA4.Reg) +} + +// EFUSE.RD_KEY2_DATA5: Register 5 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA5.Reg) +} + +// EFUSE.RD_KEY2_DATA6: Register 6 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA6.Reg) +} + +// EFUSE.RD_KEY2_DATA7: Register 7 of BLOCK6 (KEY2). +func (o *EFUSE_Type) SetRD_KEY2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY2_DATA7.Reg) +} + +// EFUSE.RD_KEY3_DATA0: Register 0 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA0.Reg) +} + +// EFUSE.RD_KEY3_DATA1: Register 1 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA1.Reg) +} + +// EFUSE.RD_KEY3_DATA2: Register 2 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA2.Reg) +} + +// EFUSE.RD_KEY3_DATA3: Register 3 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA3.Reg) +} + +// EFUSE.RD_KEY3_DATA4: Register 4 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA4.Reg) +} + +// EFUSE.RD_KEY3_DATA5: Register 5 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA5.Reg) +} + +// EFUSE.RD_KEY3_DATA6: Register 6 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA6.Reg) +} + +// EFUSE.RD_KEY3_DATA7: Register 7 of BLOCK7 (KEY3). +func (o *EFUSE_Type) SetRD_KEY3_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY3_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY3_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY3_DATA7.Reg) +} + +// EFUSE.RD_KEY4_DATA0: Register 0 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA0.Reg) +} + +// EFUSE.RD_KEY4_DATA1: Register 1 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA1.Reg) +} + +// EFUSE.RD_KEY4_DATA2: Register 2 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA2.Reg) +} + +// EFUSE.RD_KEY4_DATA3: Register 3 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA3.Reg) +} + +// EFUSE.RD_KEY4_DATA4: Register 4 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA4.Reg) +} + +// EFUSE.RD_KEY4_DATA5: Register 5 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA5.Reg) +} + +// EFUSE.RD_KEY4_DATA6: Register 6 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA6.Reg) +} + +// EFUSE.RD_KEY4_DATA7: Register 7 of BLOCK8 (KEY4). +func (o *EFUSE_Type) SetRD_KEY4_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY4_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY4_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY4_DATA7.Reg) +} + +// EFUSE.RD_KEY5_DATA0: Register 0 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA0.Reg) +} + +// EFUSE.RD_KEY5_DATA1: Register 1 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA1.Reg) +} + +// EFUSE.RD_KEY5_DATA2: Register 2 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA2.Reg) +} + +// EFUSE.RD_KEY5_DATA3: Register 3 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA3.Reg) +} + +// EFUSE.RD_KEY5_DATA4: Register 4 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA4.Reg) +} + +// EFUSE.RD_KEY5_DATA5: Register 5 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA5.Reg) +} + +// EFUSE.RD_KEY5_DATA6: Register 6 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA6.Reg) +} + +// EFUSE.RD_KEY5_DATA7: Register 7 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_KEY5_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_KEY5_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_KEY5_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_KEY5_DATA7.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA0: Register 0 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA0(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA0() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA0.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA1: Register 1 of BLOCK9 (KEY5). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA1(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA1() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA1.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA2: Register 2 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA2(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA2() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA2.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA3: Register 3 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA3(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA3() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA3.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA4: Register 4 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA4(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA4.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA4() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA4.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA5: Register 5 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA5(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA5.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA5() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA5.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA6: Register 6 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA6(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA6.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA6() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA6.Reg) +} + +// EFUSE.RD_SYS_PART2_DATA7: Register 7 of BLOCK10 (system). +func (o *EFUSE_Type) SetRD_SYS_PART2_DATA7(value uint32) { + volatile.StoreUint32(&o.RD_SYS_PART2_DATA7.Reg, value) +} +func (o *EFUSE_Type) GetRD_SYS_PART2_DATA7() uint32 { + return volatile.LoadUint32(&o.RD_SYS_PART2_DATA7.Reg) +} + +// EFUSE.RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RD_DIS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x7f)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RD_DIS_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x7f +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DCACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DCACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x400)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x400) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_CAN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_CAN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_APP_CPU_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_APP_CPU_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x600000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x600000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DREFL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DREFL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_EXCHG_PINS_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_BTLC_GPIO_ENABLE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x18000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_BTLC_GPIO_ENABLE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x18000000) >> 27 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x20000000)|value<<29) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x20000000) >> 29 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR0_VDD_SPI_DREFH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0xc0000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR0_VDD_SPI_DREFH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0xc0000000) >> 30 +} + +// EFUSE.RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_DREFM_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x3)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_DREFM_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_DREFL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xc)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_DREFL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xc) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_XPD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_XPD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_TIEH_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_TIEH_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_FORCE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_FORCE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_DCURLIM_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xe00)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_DCURLIM_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xe00) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_INIT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x3000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_INIT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x3000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_VDD_SPI_DCAP_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_VDD_SPI_DCAP_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x30000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x30000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1c0000)|value<<18) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1c0000) >> 18 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf00)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf00) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_RPT4_RESERVED0_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000)|value<<16) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_RPT4_RESERVED0_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000) >> 16 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x100000)|value<<20) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x100000) >> 20 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x200000)|value<<21) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x200000) >> 21 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_DIS_USB_JTAG_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x400000)|value<<22) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_DIS_USB_JTAG_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x400000) >> 22 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_DIS_USB_DEVICE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_DIS_USB_DEVICE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_STRAP_JTAG_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x1000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_STRAP_JTAG_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x1000000) >> 24 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_USB_PHY_SEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x2000000)|value<<25) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_USB_PHY_SEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x2000000) >> 25 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_POWER_GLITCH_DSENSE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xc000000)|value<<26) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_POWER_GLITCH_DSENSE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xc000000) >> 26 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_TPUW_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_TPUW_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000000) >> 28 +} + +// EFUSE.RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FLASH_ECC_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FLASH_ECC_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc0)|value<<6) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc0) >> 6 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FLASH_TYPE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FLASH_TYPE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FLASH_PAGE_SIZE_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc00)|value<<10) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FLASH_PAGE_SIZE_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc00) >> 10 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FLASH_ECC_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1000)|value<<12) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FLASH_ECC_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1000) >> 12 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2000)|value<<13) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2000) >> 13 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_VERSION_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x3fffc000)|value<<14) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_VERSION_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x3fffc000) >> 14 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_POWERGLITCH_EN_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x40000000)|value<<30) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_POWERGLITCH_EN_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x40000000) >> 30 +} +func (o *EFUSE_Type) SetRD_REPEAT_ERR3_RPT4_RESERVED1_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x80000000)|value<<31) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR3_RPT4_RESERVED1_ERR() uint32 { + return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x80000000) >> 31 +} + +// EFUSE.RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. +func (o *EFUSE_Type) SetRD_REPEAT_ERR4_RPT4_RESERVED2_ERR(value uint32) { + volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xffffff)|value) +} +func (o *EFUSE_Type) GetRD_REPEAT_ERR4_RPT4_RESERVED2_ERR() uint32 { + return volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xffffff +} + +// EFUSE.RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SPI_8M_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SPI_8M_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700)|value<<8) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700) >> 8 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800)|value<<11) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800) >> 11 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000)|value<<12) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000) >> 12 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000)|value<<15) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000) >> 15 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000)|value<<16) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000) >> 16 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000)|value<<19) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000) >> 19 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700000)|value<<20) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700000) >> 20 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800000)|value<<23) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800000) >> 23 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000000) >> 24 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000000)|value<<27) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000000) >> 27 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000000)|value<<28) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000000) >> 28 +} +func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000000)|value<<31) +} +func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000000) >> 31 +} + +// EFUSE.RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x7)|value) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_ERR_NUM() uint32 { + return volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x7 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x8)|value<<3) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x8) >> 3 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_ERR_NUM(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x70)|value<<4) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_ERR_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x70) >> 4 +} +func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_FAIL(value uint32) { + volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_FAIL() uint32 { + return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x80) >> 7 +} + +// EFUSE.CLK: eFuse clcok configuration register. +func (o *EFUSE_Type) SetCLK_EFUSE_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCLK_EFUSE_MEM_FORCE_PD() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCLK_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCLK_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCLK_EFUSE_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x4)|value<<2) +} +func (o *EFUSE_Type) GetCLK_EFUSE_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x4) >> 2 +} +func (o *EFUSE_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x10000)|value<<16) +} +func (o *EFUSE_Type) GetCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK.Reg) & 0x10000) >> 16 +} + +// EFUSE.CONF: eFuse operation mode configuraiton register +func (o *EFUSE_Type) SetCONF_OP_CODE(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetCONF_OP_CODE() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0xffff +} + +// EFUSE.STATUS: eFuse status register. +func (o *EFUSE_Type) SetSTATUS_STATE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf)|value) +} +func (o *EFUSE_Type) GetSTATUS_STATE() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0xf +} +func (o *EFUSE_Type) SetSTATUS_OTP_LOAD_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *EFUSE_Type) GetSTATUS_OTP_LOAD_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_C_SYNC2(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_C_SYNC2() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *EFUSE_Type) SetSTATUS_OTP_STROBE_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *EFUSE_Type) GetSTATUS_OTP_STROBE_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *EFUSE_Type) SetSTATUS_OTP_CSB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *EFUSE_Type) GetSTATUS_OTP_CSB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *EFUSE_Type) SetSTATUS_OTP_PGENB_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetSTATUS_OTP_PGENB_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_IS_SW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_IS_SW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *EFUSE_Type) SetSTATUS_REPEAT_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3fc00)|value<<10) +} +func (o *EFUSE_Type) GetSTATUS_REPEAT_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3fc00) >> 10 +} + +// EFUSE.CMD: eFuse command register. +func (o *EFUSE_Type) SetCMD_READ_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetCMD_READ_CMD() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *EFUSE_Type) SetCMD_PGM_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetCMD_PGM_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *EFUSE_Type) SetCMD_BLK_NUM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3c)|value<<2) +} +func (o *EFUSE_Type) GetCMD_BLK_NUM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x3c) >> 2 +} + +// EFUSE.INT_RAW: eFuse raw interrupt register. +func (o *EFUSE_Type) SetINT_RAW_READ_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_RAW_READ_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_RAW_PGM_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_RAW_PGM_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ST: eFuse interrupt status register. +func (o *EFUSE_Type) SetINT_ST_READ_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ST_READ_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ST_PGM_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ST_PGM_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_ENA: eFuse interrupt enable register. +func (o *EFUSE_Type) SetINT_ENA_READ_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_ENA_READ_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_ENA_PGM_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_ENA_PGM_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// EFUSE.INT_CLR: eFuse interrupt clear register. +func (o *EFUSE_Type) SetINT_CLR_READ_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *EFUSE_Type) GetINT_CLR_READ_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *EFUSE_Type) SetINT_CLR_PGM_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EFUSE_Type) GetINT_CLR_PGM_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// EFUSE.DAC_CONF: Controls the eFuse programming voltage. +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0xff)|value) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.DAC_CONF.Reg) & 0xff +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_PAD_SEL(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x100)|value<<8) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_PAD_SEL() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x100) >> 8 +} +func (o *EFUSE_Type) SetDAC_CONF_DAC_NUM(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x1fe00)|value<<9) +} +func (o *EFUSE_Type) GetDAC_CONF_DAC_NUM() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x1fe00) >> 9 +} +func (o *EFUSE_Type) SetDAC_CONF_OE_CLR(value uint32) { + volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *EFUSE_Type) GetDAC_CONF_OE_CLR() uint32 { + return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x20000) >> 17 +} + +// EFUSE.RD_TIM_CONF: Configures read timing parameters. +func (o *EFUSE_Type) SetRD_TIM_CONF_READ_INIT_NUM(value uint32) { + volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff000000)|value<<24) +} +func (o *EFUSE_Type) GetRD_TIM_CONF_READ_INIT_NUM() uint32 { + return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff000000) >> 24 +} + +// EFUSE.WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF1_PWR_ON_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xffff00)|value<<8) +} +func (o *EFUSE_Type) GetWR_TIM_CONF1_PWR_ON_NUM() uint32 { + return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xffff00) >> 8 +} + +// EFUSE.WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters. +func (o *EFUSE_Type) SetWR_TIM_CONF2_PWR_OFF_NUM(value uint32) { + volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff)|value) +} +func (o *EFUSE_Type) GetWR_TIM_CONF2_PWR_OFF_NUM() uint32 { + return volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff +} + +// EFUSE.DATE: eFuse version register. +func (o *EFUSE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *EFUSE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// External Memory +type EXTMEM_Type struct { + DCACHE_CTRL volatile.Register32 // 0x0 + DCACHE_CTRL1 volatile.Register32 // 0x4 + DCACHE_TAG_POWER_CTRL volatile.Register32 // 0x8 + DCACHE_PRELOCK_CTRL volatile.Register32 // 0xC + DCACHE_PRELOCK_SCT0_ADDR volatile.Register32 // 0x10 + DCACHE_PRELOCK_SCT1_ADDR volatile.Register32 // 0x14 + DCACHE_PRELOCK_SCT_SIZE volatile.Register32 // 0x18 + DCACHE_LOCK_CTRL volatile.Register32 // 0x1C + DCACHE_LOCK_ADDR volatile.Register32 // 0x20 + DCACHE_LOCK_SIZE volatile.Register32 // 0x24 + DCACHE_SYNC_CTRL volatile.Register32 // 0x28 + DCACHE_SYNC_ADDR volatile.Register32 // 0x2C + DCACHE_SYNC_SIZE volatile.Register32 // 0x30 + DCACHE_OCCUPY_CTRL volatile.Register32 // 0x34 + DCACHE_OCCUPY_ADDR volatile.Register32 // 0x38 + DCACHE_OCCUPY_SIZE volatile.Register32 // 0x3C + DCACHE_PRELOAD_CTRL volatile.Register32 // 0x40 + DCACHE_PRELOAD_ADDR volatile.Register32 // 0x44 + DCACHE_PRELOAD_SIZE volatile.Register32 // 0x48 + DCACHE_AUTOLOAD_CTRL volatile.Register32 // 0x4C + DCACHE_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0x50 + DCACHE_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0x54 + DCACHE_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0x58 + DCACHE_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0x5C + ICACHE_CTRL volatile.Register32 // 0x60 + ICACHE_CTRL1 volatile.Register32 // 0x64 + ICACHE_TAG_POWER_CTRL volatile.Register32 // 0x68 + ICACHE_PRELOCK_CTRL volatile.Register32 // 0x6C + ICACHE_PRELOCK_SCT0_ADDR volatile.Register32 // 0x70 + ICACHE_PRELOCK_SCT1_ADDR volatile.Register32 // 0x74 + ICACHE_PRELOCK_SCT_SIZE volatile.Register32 // 0x78 + ICACHE_LOCK_CTRL volatile.Register32 // 0x7C + ICACHE_LOCK_ADDR volatile.Register32 // 0x80 + ICACHE_LOCK_SIZE volatile.Register32 // 0x84 + ICACHE_SYNC_CTRL volatile.Register32 // 0x88 + ICACHE_SYNC_ADDR volatile.Register32 // 0x8C + ICACHE_SYNC_SIZE volatile.Register32 // 0x90 + ICACHE_PRELOAD_CTRL volatile.Register32 // 0x94 + ICACHE_PRELOAD_ADDR volatile.Register32 // 0x98 + ICACHE_PRELOAD_SIZE volatile.Register32 // 0x9C + ICACHE_AUTOLOAD_CTRL volatile.Register32 // 0xA0 + ICACHE_AUTOLOAD_SCT0_ADDR volatile.Register32 // 0xA4 + ICACHE_AUTOLOAD_SCT0_SIZE volatile.Register32 // 0xA8 + ICACHE_AUTOLOAD_SCT1_ADDR volatile.Register32 // 0xAC + ICACHE_AUTOLOAD_SCT1_SIZE volatile.Register32 // 0xB0 + IBUS_TO_FLASH_START_VADDR volatile.Register32 // 0xB4 + IBUS_TO_FLASH_END_VADDR volatile.Register32 // 0xB8 + DBUS_TO_FLASH_START_VADDR volatile.Register32 // 0xBC + DBUS_TO_FLASH_END_VADDR volatile.Register32 // 0xC0 + CACHE_ACS_CNT_CLR volatile.Register32 // 0xC4 + IBUS_ACS_MISS_CNT volatile.Register32 // 0xC8 + IBUS_ACS_CNT volatile.Register32 // 0xCC + DBUS_ACS_FLASH_MISS_CNT volatile.Register32 // 0xD0 + DBUS_ACS_SPIRAM_MISS_CNT volatile.Register32 // 0xD4 + DBUS_ACS_CNT volatile.Register32 // 0xD8 + CACHE_ILG_INT_ENA volatile.Register32 // 0xDC + CACHE_ILG_INT_CLR volatile.Register32 // 0xE0 + CACHE_ILG_INT_ST volatile.Register32 // 0xE4 + CORE0_ACS_CACHE_INT_ENA volatile.Register32 // 0xE8 + CORE0_ACS_CACHE_INT_CLR volatile.Register32 // 0xEC + CORE0_ACS_CACHE_INT_ST volatile.Register32 // 0xF0 + CORE1_ACS_CACHE_INT_ENA volatile.Register32 // 0xF4 + CORE1_ACS_CACHE_INT_CLR volatile.Register32 // 0xF8 + CORE1_ACS_CACHE_INT_ST volatile.Register32 // 0xFC + CORE0_DBUS_REJECT_ST volatile.Register32 // 0x100 + CORE0_DBUS_REJECT_VADDR volatile.Register32 // 0x104 + CORE0_IBUS_REJECT_ST volatile.Register32 // 0x108 + CORE0_IBUS_REJECT_VADDR volatile.Register32 // 0x10C + CORE1_DBUS_REJECT_ST volatile.Register32 // 0x110 + CORE1_DBUS_REJECT_VADDR volatile.Register32 // 0x114 + CORE1_IBUS_REJECT_ST volatile.Register32 // 0x118 + CORE1_IBUS_REJECT_VADDR volatile.Register32 // 0x11C + CACHE_MMU_FAULT_CONTENT volatile.Register32 // 0x120 + CACHE_MMU_FAULT_VADDR volatile.Register32 // 0x124 + CACHE_WRAP_AROUND_CTRL volatile.Register32 // 0x128 + CACHE_MMU_POWER_CTRL volatile.Register32 // 0x12C + CACHE_STATE volatile.Register32 // 0x130 + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE volatile.Register32 // 0x134 + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON volatile.Register32 // 0x138 + CACHE_BRIDGE_ARBITER_CTRL volatile.Register32 // 0x13C + CACHE_PRELOAD_INT_CTRL volatile.Register32 // 0x140 + CACHE_SYNC_INT_CTRL volatile.Register32 // 0x144 + CACHE_MMU_OWNER volatile.Register32 // 0x148 + CACHE_CONF_MISC volatile.Register32 // 0x14C + DCACHE_FREEZE volatile.Register32 // 0x150 + ICACHE_FREEZE volatile.Register32 // 0x154 + ICACHE_ATOMIC_OPERATE_ENA volatile.Register32 // 0x158 + DCACHE_ATOMIC_OPERATE_ENA volatile.Register32 // 0x15C + CACHE_REQUEST volatile.Register32 // 0x160 + CLOCK_GATE volatile.Register32 // 0x164 + _ [24]byte + CACHE_TAG_OBJECT_CTRL volatile.Register32 // 0x180 + CACHE_TAG_WAY_OBJECT volatile.Register32 // 0x184 + CACHE_VADDR volatile.Register32 // 0x188 + CACHE_TAG_CONTENT volatile.Register32 // 0x18C + _ [620]byte + DATE volatile.Register32 // 0x3FC +} + +// EXTMEM.DCACHE_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_CTRL_DCACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.DCACHE_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_CTRL_DCACHE_ENABLE() uint32 { + return volatile.LoadUint32(&o.DCACHE_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_CTRL_DCACHE_SIZE_MODE(value uint32) { + volatile.StoreUint32(&o.DCACHE_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetDCACHE_CTRL_DCACHE_SIZE_MODE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetDCACHE_CTRL_DCACHE_BLOCKSIZE_MODE(value uint32) { + volatile.StoreUint32(&o.DCACHE_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_CTRL.Reg)&^(0x18)|value<<3) +} +func (o *EXTMEM_Type) GetDCACHE_CTRL_DCACHE_BLOCKSIZE_MODE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_CTRL.Reg) & 0x18) >> 3 +} + +// EXTMEM.DCACHE_CTRL1: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_CTRL1_DCACHE_SHUT_CORE0_BUS(value uint32) { + volatile.StoreUint32(&o.DCACHE_CTRL1.Reg, volatile.LoadUint32(&o.DCACHE_CTRL1.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_CTRL1_DCACHE_SHUT_CORE0_BUS() uint32 { + return volatile.LoadUint32(&o.DCACHE_CTRL1.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_CTRL1_DCACHE_SHUT_CORE1_BUS(value uint32) { + volatile.StoreUint32(&o.DCACHE_CTRL1.Reg, volatile.LoadUint32(&o.DCACHE_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetDCACHE_CTRL1_DCACHE_SHUT_CORE1_BUS() uint32 { + return (volatile.LoadUint32(&o.DCACHE_CTRL1.Reg) & 0x2) >> 1 +} + +// EXTMEM.DCACHE_TAG_POWER_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.DCACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_TAG_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.DCACHE_TAG_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DCACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_TAG_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetDCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DCACHE_TAG_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetDCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DCACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_TAG_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetDCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DCACHE_TAG_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.DCACHE_PRELOCK_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOCK_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_PRELOCK_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.DCACHE_PRELOCK_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOCK_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_PRELOCK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.DCACHE_PRELOCK_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.DCACHE_PRELOCK_SCT0_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.DCACHE_PRELOCK_SCT0_ADDR.Reg) +} + +// EXTMEM.DCACHE_PRELOCK_SCT1_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.DCACHE_PRELOCK_SCT1_ADDR.Reg) +} + +// EXTMEM.DCACHE_PRELOCK_SCT_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_PRELOCK_SCT_SIZE_DCACHE_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.DCACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOCK_SCT_SIZE_DCACHE_PRELOCK_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.DCACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetDCACHE_PRELOCK_SCT_SIZE_DCACHE_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.DCACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOCK_SCT_SIZE_DCACHE_PRELOCK_SCT0_SIZE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.DCACHE_LOCK_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_LOCK_CTRL_DCACHE_LOCK_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_LOCK_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_LOCK_CTRL_DCACHE_LOCK_ENA() uint32 { + return volatile.LoadUint32(&o.DCACHE_LOCK_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_LOCK_CTRL_DCACHE_UNLOCK_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_LOCK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetDCACHE_LOCK_CTRL_DCACHE_UNLOCK_ENA() uint32 { + return (volatile.LoadUint32(&o.DCACHE_LOCK_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetDCACHE_LOCK_CTRL_DCACHE_LOCK_DONE(value uint32) { + volatile.StoreUint32(&o.DCACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_LOCK_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetDCACHE_LOCK_CTRL_DCACHE_LOCK_DONE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_LOCK_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.DCACHE_LOCK_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_LOCK_ADDR(value uint32) { + volatile.StoreUint32(&o.DCACHE_LOCK_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDCACHE_LOCK_ADDR() uint32 { + return volatile.LoadUint32(&o.DCACHE_LOCK_ADDR.Reg) +} + +// EXTMEM.DCACHE_LOCK_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_LOCK_SIZE(value uint32) { + volatile.StoreUint32(&o.DCACHE_LOCK_SIZE.Reg, volatile.LoadUint32(&o.DCACHE_LOCK_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDCACHE_LOCK_SIZE() uint32 { + return volatile.LoadUint32(&o.DCACHE_LOCK_SIZE.Reg) & 0xffff +} + +// EXTMEM.DCACHE_SYNC_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_SYNC_CTRL_DCACHE_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_SYNC_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_SYNC_CTRL_DCACHE_INVALIDATE_ENA() uint32 { + return volatile.LoadUint32(&o.DCACHE_SYNC_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_SYNC_CTRL_DCACHE_WRITEBACK_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_SYNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetDCACHE_SYNC_CTRL_DCACHE_WRITEBACK_ENA() uint32 { + return (volatile.LoadUint32(&o.DCACHE_SYNC_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetDCACHE_SYNC_CTRL_DCACHE_CLEAN_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_SYNC_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetDCACHE_SYNC_CTRL_DCACHE_CLEAN_ENA() uint32 { + return (volatile.LoadUint32(&o.DCACHE_SYNC_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetDCACHE_SYNC_CTRL_DCACHE_SYNC_DONE(value uint32) { + volatile.StoreUint32(&o.DCACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_SYNC_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetDCACHE_SYNC_CTRL_DCACHE_SYNC_DONE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_SYNC_CTRL.Reg) & 0x8) >> 3 +} + +// EXTMEM.DCACHE_SYNC_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_SYNC_ADDR(value uint32) { + volatile.StoreUint32(&o.DCACHE_SYNC_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDCACHE_SYNC_ADDR() uint32 { + return volatile.LoadUint32(&o.DCACHE_SYNC_ADDR.Reg) +} + +// EXTMEM.DCACHE_SYNC_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_SYNC_SIZE(value uint32) { + volatile.StoreUint32(&o.DCACHE_SYNC_SIZE.Reg, volatile.LoadUint32(&o.DCACHE_SYNC_SIZE.Reg)&^(0x7fffff)|value) +} +func (o *EXTMEM_Type) GetDCACHE_SYNC_SIZE() uint32 { + return volatile.LoadUint32(&o.DCACHE_SYNC_SIZE.Reg) & 0x7fffff +} + +// EXTMEM.DCACHE_OCCUPY_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_OCCUPY_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_OCCUPY_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_ENA() uint32 { + return volatile.LoadUint32(&o.DCACHE_OCCUPY_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_DONE(value uint32) { + volatile.StoreUint32(&o.DCACHE_OCCUPY_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_OCCUPY_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetDCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_DONE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_OCCUPY_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.DCACHE_OCCUPY_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_OCCUPY_ADDR(value uint32) { + volatile.StoreUint32(&o.DCACHE_OCCUPY_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDCACHE_OCCUPY_ADDR() uint32 { + return volatile.LoadUint32(&o.DCACHE_OCCUPY_ADDR.Reg) +} + +// EXTMEM.DCACHE_OCCUPY_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_OCCUPY_SIZE(value uint32) { + volatile.StoreUint32(&o.DCACHE_OCCUPY_SIZE.Reg, volatile.LoadUint32(&o.DCACHE_OCCUPY_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDCACHE_OCCUPY_SIZE() uint32 { + return volatile.LoadUint32(&o.DCACHE_OCCUPY_SIZE.Reg) & 0xffff +} + +// EXTMEM.DCACHE_PRELOAD_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.DCACHE_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetDCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.DCACHE_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.DCACHE_PRELOAD_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.DCACHE_PRELOAD_ADDR.Reg) +} + +// EXTMEM.DCACHE_PRELOAD_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.DCACHE_PRELOAD_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetDCACHE_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.DCACHE_PRELOAD_SIZE.Reg) & 0xffff +} + +// EXTMEM.DCACHE_AUTOLOAD_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT0_ENA() uint32 { + return volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ENA() uint32 { + return (volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_RQST(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg)&^(0x60)|value<<5) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_RQST() uint32 { + return (volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg) & 0x60) >> 5 +} +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg)&^(0x180)|value<<7) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SIZE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg) & 0x180) >> 7 +} +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_BUFFER_CLEAR(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_BUFFER_CLEAR() uint32 { + return (volatile.LoadUint32(&o.DCACHE_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} + +// EXTMEM.DCACHE_AUTOLOAD_SCT0_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.DCACHE_AUTOLOAD_SCT0_ADDR.Reg) +} + +// EXTMEM.DCACHE_AUTOLOAD_SCT0_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_SCT0_SIZE.Reg)&^(0x7ffffff)|value) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.DCACHE_AUTOLOAD_SCT0_SIZE.Reg) & 0x7ffffff +} + +// EXTMEM.DCACHE_AUTOLOAD_SCT1_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.DCACHE_AUTOLOAD_SCT1_ADDR.Reg) +} + +// EXTMEM.DCACHE_AUTOLOAD_SCT1_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.DCACHE_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.DCACHE_AUTOLOAD_SCT1_SIZE.Reg)&^(0x7ffffff)|value) +} +func (o *EXTMEM_Type) GetDCACHE_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.DCACHE_AUTOLOAD_SCT1_SIZE.Reg) & 0x7ffffff +} + +// EXTMEM.ICACHE_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_CTRL_ICACHE_ENABLE(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_CTRL_ICACHE_ENABLE() uint32 { + return volatile.LoadUint32(&o.ICACHE_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_CTRL_ICACHE_WAY_MODE(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_CTRL_ICACHE_WAY_MODE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_CTRL_ICACHE_SIZE_MODE(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_CTRL_ICACHE_SIZE_MODE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetICACHE_CTRL_ICACHE_BLOCKSIZE_MODE(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetICACHE_CTRL_ICACHE_BLOCKSIZE_MODE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_CTRL.Reg) & 0x8) >> 3 +} + +// EXTMEM.ICACHE_CTRL1: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_CTRL1_ICACHE_SHUT_CORE0_BUS(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL1.Reg, volatile.LoadUint32(&o.ICACHE_CTRL1.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_CTRL1_ICACHE_SHUT_CORE0_BUS() uint32 { + return volatile.LoadUint32(&o.ICACHE_CTRL1.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_CTRL1_ICACHE_SHUT_CORE1_BUS(value uint32) { + volatile.StoreUint32(&o.ICACHE_CTRL1.Reg, volatile.LoadUint32(&o.ICACHE_CTRL1.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_CTRL1_ICACHE_SHUT_CORE1_BUS() uint32 { + return (volatile.LoadUint32(&o.ICACHE_CTRL1.Reg) & 0x2) >> 1 +} + +// EXTMEM.ICACHE_TAG_POWER_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ICACHE_TAG_POWER_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ICACHE_TAG_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_PRELOCK_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOCK_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOCK_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOCK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN() uint32 { + return (volatile.LoadUint32(&o.ICACHE_PRELOCK_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.ICACHE_PRELOCK_SCT0_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_PRELOCK_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT0_ADDR.Reg) +} + +// EXTMEM.ICACHE_PRELOCK_SCT1_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_PRELOCK_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT1_ADDR.Reg) +} + +// EXTMEM.ICACHE_PRELOCK_SCT_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff0000)|value<<16) +} +func (o *EXTMEM_Type) GetICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT0_SIZE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff0000) >> 16 +} + +// EXTMEM.ICACHE_LOCK_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_LOCK_CTRL_ICACHE_LOCK_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_CTRL_ICACHE_LOCK_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA() uint32 { + return (volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_LOCK_CTRL_ICACHE_LOCK_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_CTRL_ICACHE_LOCK_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_LOCK_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_LOCK_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_LOCK_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_LOCK_ADDR.Reg) +} + +// EXTMEM.ICACHE_LOCK_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_LOCK_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_LOCK_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_LOCK_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_LOCK_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_LOCK_SIZE.Reg) & 0xffff +} + +// EXTMEM.ICACHE_SYNC_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_SYNC_CTRL_ICACHE_SYNC_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_CTRL_ICACHE_SYNC_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_SYNC_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.ICACHE_SYNC_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_SYNC_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_ADDR.Reg) +} + +// EXTMEM.ICACHE_SYNC_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_SYNC_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_SIZE.Reg)&^(0x7fffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_SYNC_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_SIZE.Reg) & 0x7fffff +} + +// EXTMEM.ICACHE_PRELOAD_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.ICACHE_PRELOAD_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_PRELOAD_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_PRELOAD_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_ADDR.Reg) +} + +// EXTMEM.ICACHE_PRELOAD_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_PRELOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_SIZE.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_PRELOAD_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_SIZE.Reg) & 0xffff +} + +// EXTMEM.ICACHE_AUTOLOAD_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_RQST(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x60)|value<<5) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_RQST() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x60) >> 5 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x180)|value<<7) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SIZE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x180) >> 7 +} +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_BUFFER_CLEAR(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_BUFFER_CLEAR() uint32 { + return (volatile.LoadUint32(&o.ICACHE_AUTOLOAD_CTRL.Reg) & 0x200) >> 9 +} + +// EXTMEM.ICACHE_AUTOLOAD_SCT0_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_SCT0_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_SCT0_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_SCT0_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT0_ADDR.Reg) +} + +// EXTMEM.ICACHE_AUTOLOAD_SCT0_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_SCT0_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT0_SIZE.Reg)&^(0x7ffffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_SCT0_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT0_SIZE.Reg) & 0x7ffffff +} + +// EXTMEM.ICACHE_AUTOLOAD_SCT1_ADDR: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_SCT1_ADDR(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_SCT1_ADDR.Reg, value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_SCT1_ADDR() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT1_ADDR.Reg) +} + +// EXTMEM.ICACHE_AUTOLOAD_SCT1_SIZE: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_AUTOLOAD_SCT1_SIZE(value uint32) { + volatile.StoreUint32(&o.ICACHE_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT1_SIZE.Reg)&^(0x7ffffff)|value) +} +func (o *EXTMEM_Type) GetICACHE_AUTOLOAD_SCT1_SIZE() uint32 { + return volatile.LoadUint32(&o.ICACHE_AUTOLOAD_SCT1_SIZE.Reg) & 0x7ffffff +} + +// EXTMEM.IBUS_TO_FLASH_START_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetIBUS_TO_FLASH_START_VADDR(value uint32) { + volatile.StoreUint32(&o.IBUS_TO_FLASH_START_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_TO_FLASH_START_VADDR() uint32 { + return volatile.LoadUint32(&o.IBUS_TO_FLASH_START_VADDR.Reg) +} + +// EXTMEM.IBUS_TO_FLASH_END_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetIBUS_TO_FLASH_END_VADDR(value uint32) { + volatile.StoreUint32(&o.IBUS_TO_FLASH_END_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_TO_FLASH_END_VADDR() uint32 { + return volatile.LoadUint32(&o.IBUS_TO_FLASH_END_VADDR.Reg) +} + +// EXTMEM.DBUS_TO_FLASH_START_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDBUS_TO_FLASH_START_VADDR(value uint32) { + volatile.StoreUint32(&o.DBUS_TO_FLASH_START_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_TO_FLASH_START_VADDR() uint32 { + return volatile.LoadUint32(&o.DBUS_TO_FLASH_START_VADDR.Reg) +} + +// EXTMEM.DBUS_TO_FLASH_END_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetDBUS_TO_FLASH_END_VADDR(value uint32) { + volatile.StoreUint32(&o.DBUS_TO_FLASH_END_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_TO_FLASH_END_VADDR() uint32 { + return volatile.LoadUint32(&o.DBUS_TO_FLASH_END_VADDR.Reg) +} + +// EXTMEM.CACHE_ACS_CNT_CLR: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_ACS_CNT_CLR_DCACHE_ACS_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ACS_CNT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ACS_CNT_CLR_DCACHE_ACS_CNT_CLR() uint32 { + return volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ACS_CNT_CLR_ICACHE_ACS_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ACS_CNT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ACS_CNT_CLR_ICACHE_ACS_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ACS_CNT_CLR.Reg) & 0x2) >> 1 +} + +// EXTMEM.IBUS_ACS_MISS_CNT: ******* Description *********** +func (o *EXTMEM_Type) SetIBUS_ACS_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS_ACS_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_ACS_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS_ACS_MISS_CNT.Reg) +} + +// EXTMEM.IBUS_ACS_CNT: ******* Description *********** +func (o *EXTMEM_Type) SetIBUS_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.IBUS_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetIBUS_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.IBUS_ACS_CNT.Reg) +} + +// EXTMEM.DBUS_ACS_FLASH_MISS_CNT: ******* Description *********** +func (o *EXTMEM_Type) SetDBUS_ACS_FLASH_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS_ACS_FLASH_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_ACS_FLASH_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS_ACS_FLASH_MISS_CNT.Reg) +} + +// EXTMEM.DBUS_ACS_SPIRAM_MISS_CNT: ******* Description *********** +func (o *EXTMEM_Type) SetDBUS_ACS_SPIRAM_MISS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS_ACS_SPIRAM_MISS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_ACS_SPIRAM_MISS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS_ACS_SPIRAM_MISS_CNT.Reg) +} + +// EXTMEM.DBUS_ACS_CNT: ******* Description *********** +func (o *EXTMEM_Type) SetDBUS_ACS_CNT(value uint32) { + volatile.StoreUint32(&o.DBUS_ACS_CNT.Reg, value) +} +func (o *EXTMEM_Type) GetDBUS_ACS_CNT() uint32 { + return volatile.LoadUint32(&o.DBUS_ACS_CNT.Reg) +} + +// EXTMEM.CACHE_ILG_INT_ENA: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA() uint32 { + return volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_DCACHE_SYNC_OP_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_DCACHE_SYNC_OP_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_DCACHE_PRELOAD_OP_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_DCACHE_PRELOAD_OP_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_DCACHE_OCCUPY_EXC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_DCACHE_OCCUPY_EXC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ENA.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ENA.Reg) & 0x100) >> 8 +} + +// EXTMEM.CACHE_ILG_INT_CLR: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR() uint32 { + return volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_DCACHE_SYNC_OP_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_DCACHE_SYNC_OP_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_DCACHE_PRELOAD_OP_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_DCACHE_PRELOAD_OP_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_DCACHE_OCCUPY_EXC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_DCACHE_OCCUPY_EXC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_CLR.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_CLR.Reg) & 0x100) >> 8 +} + +// EXTMEM.CACHE_ILG_INT_ST: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DCACHE_SYNC_OP_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DCACHE_SYNC_OP_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DCACHE_PRELOAD_OP_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DCACHE_PRELOAD_OP_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DCACHE_WRITE_FLASH_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DCACHE_WRITE_FLASH_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x20) >> 5 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DCACHE_OCCUPY_EXC_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DCACHE_OCCUPY_EXC_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x40) >> 6 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x80) >> 7 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x100) >> 8 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x200) >> 9 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x400) >> 10 +} +func (o *EXTMEM_Type) SetCACHE_ILG_INT_ST_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_ILG_INT_ST.Reg, volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *EXTMEM_Type) GetCACHE_ILG_INT_ST_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_ILG_INT_ST.Reg) & 0x800) >> 11 +} + +// EXTMEM.CORE0_ACS_CACHE_INT_ENA: ******* Description *********** +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA() uint32 { + return volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_DC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_DC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ENA.Reg) & 0x10) >> 4 +} + +// EXTMEM.CORE0_ACS_CACHE_INT_CLR: ******* Description *********** +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR() uint32 { + return volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_DC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_DC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_CLR.Reg) & 0x10) >> 4 +} + +// EXTMEM.CORE0_ACS_CACHE_INT_ST: ******* Description *********** +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST() uint32 { + return volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_DCACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_DCACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE0_ACS_CACHE_INT_ST.Reg) & 0x10) >> 4 +} + +// EXTMEM.CORE1_ACS_CACHE_INT_ENA: ******* Description *********** +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_ACS_MSK_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_ACS_MSK_IC_INT_ENA() uint32 { + return volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_WR_IC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_WR_IC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_ACS_MSK_DC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_ACS_MSK_DC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ENA.Reg) & 0x10) >> 4 +} + +// EXTMEM.CORE1_ACS_CACHE_INT_CLR: ******* Description *********** +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_ACS_MSK_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_ACS_MSK_IC_INT_CLR() uint32 { + return volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_WR_IC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_WR_IC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_ACS_MSK_DC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_ACS_MSK_DC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_CLR.Reg) & 0x10) >> 4 +} + +// EXTMEM.CORE1_ACS_CACHE_INT_ST: ******* Description *********** +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ST_CORE1_IBUS_ACS_MSK_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ST_CORE1_IBUS_ACS_MSK_ICACHE_ST() uint32 { + return volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ST_CORE1_IBUS_WR_ICACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ST_CORE1_IBUS_WR_ICACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ST_CORE1_IBUS_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ST_CORE1_IBUS_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ST_CORE1_DBUS_ACS_MSK_DCACHE_ST(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ST_CORE1_DBUS_ACS_MSK_DCACHE_ST() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCORE1_ACS_CACHE_INT_ST_CORE1_DBUS_REJECT_ST(value uint32) { + volatile.StoreUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg, volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCORE1_ACS_CACHE_INT_ST_CORE1_DBUS_REJECT_ST() uint32 { + return (volatile.LoadUint32(&o.CORE1_ACS_CACHE_INT_ST.Reg) & 0x10) >> 4 +} + +// EXTMEM.CORE0_DBUS_REJECT_ST: ******* Description *********** +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_ST_CORE0_DBUS_TAG_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_ST_CORE0_DBUS_TAG_ATTR() uint32 { + return volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg)&^(0x38)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR() uint32 { + return (volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg) & 0x38) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE0_DBUS_REJECT_ST.Reg) & 0x40) >> 6 +} + +// EXTMEM.CORE0_DBUS_REJECT_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetCORE0_DBUS_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.CORE0_DBUS_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCORE0_DBUS_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.CORE0_DBUS_REJECT_VADDR.Reg) +} + +// EXTMEM.CORE0_IBUS_REJECT_ST: ******* Description *********** +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_ST_CORE0_IBUS_TAG_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_ST_CORE0_IBUS_TAG_ATTR() uint32 { + return volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg)&^(0x38)|value<<3) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR() uint32 { + return (volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg) & 0x38) >> 3 +} +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE0_IBUS_REJECT_ST.Reg) & 0x40) >> 6 +} + +// EXTMEM.CORE0_IBUS_REJECT_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetCORE0_IBUS_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.CORE0_IBUS_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCORE0_IBUS_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.CORE0_IBUS_REJECT_VADDR.Reg) +} + +// EXTMEM.CORE1_DBUS_REJECT_ST: ******* Description *********** +func (o *EXTMEM_Type) SetCORE1_DBUS_REJECT_ST_CORE1_DBUS_TAG_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE1_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE1_DBUS_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetCORE1_DBUS_REJECT_ST_CORE1_DBUS_TAG_ATTR() uint32 { + return volatile.LoadUint32(&o.CORE1_DBUS_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetCORE1_DBUS_REJECT_ST_CORE1_DBUS_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE1_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE1_DBUS_REJECT_ST.Reg)&^(0x38)|value<<3) +} +func (o *EXTMEM_Type) GetCORE1_DBUS_REJECT_ST_CORE1_DBUS_ATTR() uint32 { + return (volatile.LoadUint32(&o.CORE1_DBUS_REJECT_ST.Reg) & 0x38) >> 3 +} +func (o *EXTMEM_Type) SetCORE1_DBUS_REJECT_ST_CORE1_DBUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE1_DBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE1_DBUS_REJECT_ST.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCORE1_DBUS_REJECT_ST_CORE1_DBUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE1_DBUS_REJECT_ST.Reg) & 0x40) >> 6 +} + +// EXTMEM.CORE1_DBUS_REJECT_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetCORE1_DBUS_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.CORE1_DBUS_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCORE1_DBUS_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.CORE1_DBUS_REJECT_VADDR.Reg) +} + +// EXTMEM.CORE1_IBUS_REJECT_ST: ******* Description *********** +func (o *EXTMEM_Type) SetCORE1_IBUS_REJECT_ST_CORE1_IBUS_TAG_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE1_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE1_IBUS_REJECT_ST.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetCORE1_IBUS_REJECT_ST_CORE1_IBUS_TAG_ATTR() uint32 { + return volatile.LoadUint32(&o.CORE1_IBUS_REJECT_ST.Reg) & 0x7 +} +func (o *EXTMEM_Type) SetCORE1_IBUS_REJECT_ST_CORE1_IBUS_ATTR(value uint32) { + volatile.StoreUint32(&o.CORE1_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE1_IBUS_REJECT_ST.Reg)&^(0x38)|value<<3) +} +func (o *EXTMEM_Type) GetCORE1_IBUS_REJECT_ST_CORE1_IBUS_ATTR() uint32 { + return (volatile.LoadUint32(&o.CORE1_IBUS_REJECT_ST.Reg) & 0x38) >> 3 +} +func (o *EXTMEM_Type) SetCORE1_IBUS_REJECT_ST_CORE1_IBUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE1_IBUS_REJECT_ST.Reg, volatile.LoadUint32(&o.CORE1_IBUS_REJECT_ST.Reg)&^(0x40)|value<<6) +} +func (o *EXTMEM_Type) GetCORE1_IBUS_REJECT_ST_CORE1_IBUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE1_IBUS_REJECT_ST.Reg) & 0x40) >> 6 +} + +// EXTMEM.CORE1_IBUS_REJECT_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetCORE1_IBUS_REJECT_VADDR(value uint32) { + volatile.StoreUint32(&o.CORE1_IBUS_REJECT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCORE1_IBUS_REJECT_VADDR() uint32 { + return volatile.LoadUint32(&o.CORE1_IBUS_REJECT_VADDR.Reg) +} + +// EXTMEM.CACHE_MMU_FAULT_CONTENT: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_MMU_FAULT_CONTENT(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg, volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg)&^(0xffff)|value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_FAULT_CONTENT() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg) & 0xffff +} +func (o *EXTMEM_Type) SetCACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg, volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg)&^(0xf0000)|value<<16) +} +func (o *EXTMEM_Type) GetCACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_FAULT_CONTENT.Reg) & 0xf0000) >> 16 +} + +// EXTMEM.CACHE_MMU_FAULT_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_MMU_FAULT_VADDR(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_FAULT_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_FAULT_VADDR() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_FAULT_VADDR.Reg) +} + +// EXTMEM.CACHE_WRAP_AROUND_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND(value uint32) { + volatile.StoreUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND() uint32 { + return volatile.LoadUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_WRAP_AROUND_CTRL_CACHE_SRAM_RD_WRAP_AROUND(value uint32) { + volatile.StoreUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_WRAP_AROUND_CTRL_CACHE_SRAM_RD_WRAP_AROUND() uint32 { + return (volatile.LoadUint32(&o.CACHE_WRAP_AROUND_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.CACHE_MMU_POWER_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_POWER_CTRL.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_STATE: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_STATE_ICACHE_STATE(value uint32) { + volatile.StoreUint32(&o.CACHE_STATE.Reg, volatile.LoadUint32(&o.CACHE_STATE.Reg)&^(0xfff)|value) +} +func (o *EXTMEM_Type) GetCACHE_STATE_ICACHE_STATE() uint32 { + return volatile.LoadUint32(&o.CACHE_STATE.Reg) & 0xfff +} +func (o *EXTMEM_Type) SetCACHE_STATE_DCACHE_STATE(value uint32) { + volatile.StoreUint32(&o.CACHE_STATE.Reg, volatile.LoadUint32(&o.CACHE_STATE.Reg)&^(0xfff000)|value<<12) +} +func (o *EXTMEM_Type) GetCACHE_STATE_DCACHE_STATE() uint32 { + return (volatile.LoadUint32(&o.CACHE_STATE.Reg) & 0xfff000) >> 12 +} + +// EXTMEM.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE.Reg) & 0x2) >> 1 +} + +// EXTMEM.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT() uint32 { + return volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT(value uint32) { + volatile.StoreUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT() uint32 { + return (volatile.LoadUint32(&o.CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON.Reg) & 0x4) >> 2 +} + +// EXTMEM.CACHE_BRIDGE_ARBITER_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER(value uint32) { + volatile.StoreUint32(&o.CACHE_BRIDGE_ARBITER_CTRL.Reg, volatile.LoadUint32(&o.CACHE_BRIDGE_ARBITER_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER() uint32 { + return volatile.LoadUint32(&o.CACHE_BRIDGE_ARBITER_CTRL.Reg) & 0x1 +} + +// EXTMEM.CACHE_PRELOAD_INT_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_PRELOAD_INT_CTRL.Reg) & 0x20) >> 5 +} + +// EXTMEM.CACHE_SYNC_INT_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST() uint32 { + return volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x4) >> 2 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x8) >> 3 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x10) >> 4 +} +func (o *EXTMEM_Type) SetCACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.CACHE_SYNC_INT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *EXTMEM_Type) GetCACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.CACHE_SYNC_INT_CTRL.Reg) & 0x20) >> 5 +} + +// EXTMEM.CACHE_MMU_OWNER: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_MMU_OWNER(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_OWNER.Reg, volatile.LoadUint32(&o.CACHE_MMU_OWNER.Reg)&^(0xffffff)|value) +} +func (o *EXTMEM_Type) GetCACHE_MMU_OWNER() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_OWNER.Reg) & 0xffffff +} + +// EXTMEM.CACHE_CONF_MISC: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT() uint32 { + return volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetCACHE_CONF_MISC_CACHE_TRACE_ENA(value uint32) { + volatile.StoreUint32(&o.CACHE_CONF_MISC.Reg, volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetCACHE_CONF_MISC_CACHE_TRACE_ENA() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONF_MISC.Reg) & 0x4) >> 2 +} + +// EXTMEM.DCACHE_FREEZE: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_FREEZE_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_FREEZE.Reg, volatile.LoadUint32(&o.DCACHE_FREEZE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_FREEZE_ENA() uint32 { + return volatile.LoadUint32(&o.DCACHE_FREEZE.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetDCACHE_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.DCACHE_FREEZE.Reg, volatile.LoadUint32(&o.DCACHE_FREEZE.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetDCACHE_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_FREEZE.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetDCACHE_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.DCACHE_FREEZE.Reg, volatile.LoadUint32(&o.DCACHE_FREEZE.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetDCACHE_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.DCACHE_FREEZE.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_FREEZE: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_FREEZE_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_FREEZE.Reg, volatile.LoadUint32(&o.ICACHE_FREEZE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_FREEZE_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_FREEZE.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetICACHE_FREEZE_MODE(value uint32) { + volatile.StoreUint32(&o.ICACHE_FREEZE.Reg, volatile.LoadUint32(&o.ICACHE_FREEZE.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetICACHE_FREEZE_MODE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_FREEZE.Reg) & 0x2) >> 1 +} +func (o *EXTMEM_Type) SetICACHE_FREEZE_DONE(value uint32) { + volatile.StoreUint32(&o.ICACHE_FREEZE.Reg, volatile.LoadUint32(&o.ICACHE_FREEZE.Reg)&^(0x4)|value<<2) +} +func (o *EXTMEM_Type) GetICACHE_FREEZE_DONE() uint32 { + return (volatile.LoadUint32(&o.ICACHE_FREEZE.Reg) & 0x4) >> 2 +} + +// EXTMEM.ICACHE_ATOMIC_OPERATE_ENA: ******* Description *********** +func (o *EXTMEM_Type) SetICACHE_ATOMIC_OPERATE_ENA(value uint32) { + volatile.StoreUint32(&o.ICACHE_ATOMIC_OPERATE_ENA.Reg, volatile.LoadUint32(&o.ICACHE_ATOMIC_OPERATE_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetICACHE_ATOMIC_OPERATE_ENA() uint32 { + return volatile.LoadUint32(&o.ICACHE_ATOMIC_OPERATE_ENA.Reg) & 0x1 +} + +// EXTMEM.DCACHE_ATOMIC_OPERATE_ENA: ******* Description *********** +func (o *EXTMEM_Type) SetDCACHE_ATOMIC_OPERATE_ENA(value uint32) { + volatile.StoreUint32(&o.DCACHE_ATOMIC_OPERATE_ENA.Reg, volatile.LoadUint32(&o.DCACHE_ATOMIC_OPERATE_ENA.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetDCACHE_ATOMIC_OPERATE_ENA() uint32 { + return volatile.LoadUint32(&o.DCACHE_ATOMIC_OPERATE_ENA.Reg) & 0x1 +} + +// EXTMEM.CACHE_REQUEST: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_REQUEST_BYPASS(value uint32) { + volatile.StoreUint32(&o.CACHE_REQUEST.Reg, volatile.LoadUint32(&o.CACHE_REQUEST.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_REQUEST_BYPASS() uint32 { + return volatile.LoadUint32(&o.CACHE_REQUEST.Reg) & 0x1 +} + +// EXTMEM.CLOCK_GATE: ******* Description *********** +func (o *EXTMEM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// EXTMEM.CACHE_TAG_OBJECT_CTRL: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_TAG_OBJECT_CTRL_ICACHE_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_TAG_OBJECT_CTRL.Reg)&^(0x1)|value) +} +func (o *EXTMEM_Type) GetCACHE_TAG_OBJECT_CTRL_ICACHE_TAG_OBJECT() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_OBJECT_CTRL.Reg) & 0x1 +} +func (o *EXTMEM_Type) SetCACHE_TAG_OBJECT_CTRL_DCACHE_TAG_OBJECT(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.CACHE_TAG_OBJECT_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *EXTMEM_Type) GetCACHE_TAG_OBJECT_CTRL_DCACHE_TAG_OBJECT() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_OBJECT_CTRL.Reg) & 0x2) >> 1 +} + +// EXTMEM.CACHE_TAG_WAY_OBJECT: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_TAG_WAY_OBJECT(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_WAY_OBJECT.Reg, volatile.LoadUint32(&o.CACHE_TAG_WAY_OBJECT.Reg)&^(0x7)|value) +} +func (o *EXTMEM_Type) GetCACHE_TAG_WAY_OBJECT() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_WAY_OBJECT.Reg) & 0x7 +} + +// EXTMEM.CACHE_VADDR: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_VADDR(value uint32) { + volatile.StoreUint32(&o.CACHE_VADDR.Reg, value) +} +func (o *EXTMEM_Type) GetCACHE_VADDR() uint32 { + return volatile.LoadUint32(&o.CACHE_VADDR.Reg) +} + +// EXTMEM.CACHE_TAG_CONTENT: ******* Description *********** +func (o *EXTMEM_Type) SetCACHE_TAG_CONTENT(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_CONTENT.Reg, value) +} +func (o *EXTMEM_Type) GetCACHE_TAG_CONTENT() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_CONTENT.Reg) +} + +// EXTMEM.DATE: ******* Description *********** +func (o *EXTMEM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *EXTMEM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// General Purpose Input/Output +type GPIO_Type struct { + BT_SELECT volatile.Register32 // 0x0 + OUT volatile.Register32 // 0x4 + OUT_W1TS volatile.Register32 // 0x8 + OUT_W1TC volatile.Register32 // 0xC + OUT1 volatile.Register32 // 0x10 + OUT1_W1TS volatile.Register32 // 0x14 + OUT1_W1TC volatile.Register32 // 0x18 + SDIO_SELECT volatile.Register32 // 0x1C + ENABLE volatile.Register32 // 0x20 + ENABLE_W1TS volatile.Register32 // 0x24 + ENABLE_W1TC volatile.Register32 // 0x28 + ENABLE1 volatile.Register32 // 0x2C + ENABLE1_W1TS volatile.Register32 // 0x30 + ENABLE1_W1TC volatile.Register32 // 0x34 + STRAP volatile.Register32 // 0x38 + IN volatile.Register32 // 0x3C + IN1 volatile.Register32 // 0x40 + STATUS volatile.Register32 // 0x44 + STATUS_W1TS volatile.Register32 // 0x48 + STATUS_W1TC volatile.Register32 // 0x4C + STATUS1 volatile.Register32 // 0x50 + STATUS1_W1TS volatile.Register32 // 0x54 + STATUS1_W1TC volatile.Register32 // 0x58 + PCPU_INT volatile.Register32 // 0x5C + PCPU_NMI_INT volatile.Register32 // 0x60 + CPUSDIO_INT volatile.Register32 // 0x64 + PCPU_INT1 volatile.Register32 // 0x68 + PCPU_NMI_INT1 volatile.Register32 // 0x6C + CPUSDIO_INT1 volatile.Register32 // 0x70 + PIN0 volatile.Register32 // 0x74 + PIN1 volatile.Register32 // 0x78 + PIN2 volatile.Register32 // 0x7C + PIN3 volatile.Register32 // 0x80 + PIN4 volatile.Register32 // 0x84 + PIN5 volatile.Register32 // 0x88 + PIN6 volatile.Register32 // 0x8C + PIN7 volatile.Register32 // 0x90 + PIN8 volatile.Register32 // 0x94 + PIN9 volatile.Register32 // 0x98 + PIN10 volatile.Register32 // 0x9C + PIN11 volatile.Register32 // 0xA0 + PIN12 volatile.Register32 // 0xA4 + PIN13 volatile.Register32 // 0xA8 + PIN14 volatile.Register32 // 0xAC + PIN15 volatile.Register32 // 0xB0 + PIN16 volatile.Register32 // 0xB4 + PIN17 volatile.Register32 // 0xB8 + PIN18 volatile.Register32 // 0xBC + PIN19 volatile.Register32 // 0xC0 + PIN20 volatile.Register32 // 0xC4 + PIN21 volatile.Register32 // 0xC8 + PIN22 volatile.Register32 // 0xCC + PIN23 volatile.Register32 // 0xD0 + PIN24 volatile.Register32 // 0xD4 + PIN25 volatile.Register32 // 0xD8 + PIN26 volatile.Register32 // 0xDC + PIN27 volatile.Register32 // 0xE0 + PIN28 volatile.Register32 // 0xE4 + PIN29 volatile.Register32 // 0xE8 + PIN30 volatile.Register32 // 0xEC + PIN31 volatile.Register32 // 0xF0 + PIN32 volatile.Register32 // 0xF4 + PIN33 volatile.Register32 // 0xF8 + PIN34 volatile.Register32 // 0xFC + PIN35 volatile.Register32 // 0x100 + PIN36 volatile.Register32 // 0x104 + PIN37 volatile.Register32 // 0x108 + PIN38 volatile.Register32 // 0x10C + PIN39 volatile.Register32 // 0x110 + PIN40 volatile.Register32 // 0x114 + PIN41 volatile.Register32 // 0x118 + PIN42 volatile.Register32 // 0x11C + PIN43 volatile.Register32 // 0x120 + PIN44 volatile.Register32 // 0x124 + PIN45 volatile.Register32 // 0x128 + PIN46 volatile.Register32 // 0x12C + PIN47 volatile.Register32 // 0x130 + PIN48 volatile.Register32 // 0x134 + PIN49 volatile.Register32 // 0x138 + PIN50 volatile.Register32 // 0x13C + PIN51 volatile.Register32 // 0x140 + PIN52 volatile.Register32 // 0x144 + PIN53 volatile.Register32 // 0x148 + STATUS_NEXT volatile.Register32 // 0x14C + STATUS_NEXT1 volatile.Register32 // 0x150 + FUNC0_IN_SEL_CFG volatile.Register32 // 0x154 + FUNC1_IN_SEL_CFG volatile.Register32 // 0x158 + FUNC2_IN_SEL_CFG volatile.Register32 // 0x15C + FUNC3_IN_SEL_CFG volatile.Register32 // 0x160 + FUNC4_IN_SEL_CFG volatile.Register32 // 0x164 + FUNC5_IN_SEL_CFG volatile.Register32 // 0x168 + FUNC6_IN_SEL_CFG volatile.Register32 // 0x16C + FUNC7_IN_SEL_CFG volatile.Register32 // 0x170 + FUNC8_IN_SEL_CFG volatile.Register32 // 0x174 + FUNC9_IN_SEL_CFG volatile.Register32 // 0x178 + FUNC10_IN_SEL_CFG volatile.Register32 // 0x17C + FUNC11_IN_SEL_CFG volatile.Register32 // 0x180 + FUNC12_IN_SEL_CFG volatile.Register32 // 0x184 + FUNC13_IN_SEL_CFG volatile.Register32 // 0x188 + FUNC14_IN_SEL_CFG volatile.Register32 // 0x18C + FUNC15_IN_SEL_CFG volatile.Register32 // 0x190 + FUNC16_IN_SEL_CFG volatile.Register32 // 0x194 + FUNC17_IN_SEL_CFG volatile.Register32 // 0x198 + FUNC18_IN_SEL_CFG volatile.Register32 // 0x19C + FUNC19_IN_SEL_CFG volatile.Register32 // 0x1A0 + FUNC20_IN_SEL_CFG volatile.Register32 // 0x1A4 + FUNC21_IN_SEL_CFG volatile.Register32 // 0x1A8 + FUNC22_IN_SEL_CFG volatile.Register32 // 0x1AC + FUNC23_IN_SEL_CFG volatile.Register32 // 0x1B0 + FUNC24_IN_SEL_CFG volatile.Register32 // 0x1B4 + FUNC25_IN_SEL_CFG volatile.Register32 // 0x1B8 + FUNC26_IN_SEL_CFG volatile.Register32 // 0x1BC + FUNC27_IN_SEL_CFG volatile.Register32 // 0x1C0 + FUNC28_IN_SEL_CFG volatile.Register32 // 0x1C4 + FUNC29_IN_SEL_CFG volatile.Register32 // 0x1C8 + FUNC30_IN_SEL_CFG volatile.Register32 // 0x1CC + FUNC31_IN_SEL_CFG volatile.Register32 // 0x1D0 + FUNC32_IN_SEL_CFG volatile.Register32 // 0x1D4 + FUNC33_IN_SEL_CFG volatile.Register32 // 0x1D8 + FUNC34_IN_SEL_CFG volatile.Register32 // 0x1DC + FUNC35_IN_SEL_CFG volatile.Register32 // 0x1E0 + FUNC36_IN_SEL_CFG volatile.Register32 // 0x1E4 + FUNC37_IN_SEL_CFG volatile.Register32 // 0x1E8 + FUNC38_IN_SEL_CFG volatile.Register32 // 0x1EC + FUNC39_IN_SEL_CFG volatile.Register32 // 0x1F0 + FUNC40_IN_SEL_CFG volatile.Register32 // 0x1F4 + FUNC41_IN_SEL_CFG volatile.Register32 // 0x1F8 + FUNC42_IN_SEL_CFG volatile.Register32 // 0x1FC + FUNC43_IN_SEL_CFG volatile.Register32 // 0x200 + FUNC44_IN_SEL_CFG volatile.Register32 // 0x204 + FUNC45_IN_SEL_CFG volatile.Register32 // 0x208 + FUNC46_IN_SEL_CFG volatile.Register32 // 0x20C + FUNC47_IN_SEL_CFG volatile.Register32 // 0x210 + FUNC48_IN_SEL_CFG volatile.Register32 // 0x214 + FUNC49_IN_SEL_CFG volatile.Register32 // 0x218 + FUNC50_IN_SEL_CFG volatile.Register32 // 0x21C + FUNC51_IN_SEL_CFG volatile.Register32 // 0x220 + FUNC52_IN_SEL_CFG volatile.Register32 // 0x224 + FUNC53_IN_SEL_CFG volatile.Register32 // 0x228 + FUNC54_IN_SEL_CFG volatile.Register32 // 0x22C + FUNC55_IN_SEL_CFG volatile.Register32 // 0x230 + FUNC56_IN_SEL_CFG volatile.Register32 // 0x234 + FUNC57_IN_SEL_CFG volatile.Register32 // 0x238 + FUNC58_IN_SEL_CFG volatile.Register32 // 0x23C + FUNC59_IN_SEL_CFG volatile.Register32 // 0x240 + FUNC60_IN_SEL_CFG volatile.Register32 // 0x244 + FUNC61_IN_SEL_CFG volatile.Register32 // 0x248 + FUNC62_IN_SEL_CFG volatile.Register32 // 0x24C + FUNC63_IN_SEL_CFG volatile.Register32 // 0x250 + FUNC64_IN_SEL_CFG volatile.Register32 // 0x254 + FUNC65_IN_SEL_CFG volatile.Register32 // 0x258 + FUNC66_IN_SEL_CFG volatile.Register32 // 0x25C + FUNC67_IN_SEL_CFG volatile.Register32 // 0x260 + FUNC68_IN_SEL_CFG volatile.Register32 // 0x264 + FUNC69_IN_SEL_CFG volatile.Register32 // 0x268 + FUNC70_IN_SEL_CFG volatile.Register32 // 0x26C + FUNC71_IN_SEL_CFG volatile.Register32 // 0x270 + FUNC72_IN_SEL_CFG volatile.Register32 // 0x274 + FUNC73_IN_SEL_CFG volatile.Register32 // 0x278 + FUNC74_IN_SEL_CFG volatile.Register32 // 0x27C + FUNC75_IN_SEL_CFG volatile.Register32 // 0x280 + FUNC76_IN_SEL_CFG volatile.Register32 // 0x284 + FUNC77_IN_SEL_CFG volatile.Register32 // 0x288 + FUNC78_IN_SEL_CFG volatile.Register32 // 0x28C + FUNC79_IN_SEL_CFG volatile.Register32 // 0x290 + FUNC80_IN_SEL_CFG volatile.Register32 // 0x294 + FUNC81_IN_SEL_CFG volatile.Register32 // 0x298 + FUNC82_IN_SEL_CFG volatile.Register32 // 0x29C + FUNC83_IN_SEL_CFG volatile.Register32 // 0x2A0 + FUNC84_IN_SEL_CFG volatile.Register32 // 0x2A4 + FUNC85_IN_SEL_CFG volatile.Register32 // 0x2A8 + FUNC86_IN_SEL_CFG volatile.Register32 // 0x2AC + FUNC87_IN_SEL_CFG volatile.Register32 // 0x2B0 + FUNC88_IN_SEL_CFG volatile.Register32 // 0x2B4 + FUNC89_IN_SEL_CFG volatile.Register32 // 0x2B8 + FUNC90_IN_SEL_CFG volatile.Register32 // 0x2BC + FUNC91_IN_SEL_CFG volatile.Register32 // 0x2C0 + FUNC92_IN_SEL_CFG volatile.Register32 // 0x2C4 + FUNC93_IN_SEL_CFG volatile.Register32 // 0x2C8 + FUNC94_IN_SEL_CFG volatile.Register32 // 0x2CC + FUNC95_IN_SEL_CFG volatile.Register32 // 0x2D0 + FUNC96_IN_SEL_CFG volatile.Register32 // 0x2D4 + FUNC97_IN_SEL_CFG volatile.Register32 // 0x2D8 + FUNC98_IN_SEL_CFG volatile.Register32 // 0x2DC + FUNC99_IN_SEL_CFG volatile.Register32 // 0x2E0 + FUNC100_IN_SEL_CFG volatile.Register32 // 0x2E4 + FUNC101_IN_SEL_CFG volatile.Register32 // 0x2E8 + FUNC102_IN_SEL_CFG volatile.Register32 // 0x2EC + FUNC103_IN_SEL_CFG volatile.Register32 // 0x2F0 + FUNC104_IN_SEL_CFG volatile.Register32 // 0x2F4 + FUNC105_IN_SEL_CFG volatile.Register32 // 0x2F8 + FUNC106_IN_SEL_CFG volatile.Register32 // 0x2FC + FUNC107_IN_SEL_CFG volatile.Register32 // 0x300 + FUNC108_IN_SEL_CFG volatile.Register32 // 0x304 + FUNC109_IN_SEL_CFG volatile.Register32 // 0x308 + FUNC110_IN_SEL_CFG volatile.Register32 // 0x30C + FUNC111_IN_SEL_CFG volatile.Register32 // 0x310 + FUNC112_IN_SEL_CFG volatile.Register32 // 0x314 + FUNC113_IN_SEL_CFG volatile.Register32 // 0x318 + FUNC114_IN_SEL_CFG volatile.Register32 // 0x31C + FUNC115_IN_SEL_CFG volatile.Register32 // 0x320 + FUNC116_IN_SEL_CFG volatile.Register32 // 0x324 + FUNC117_IN_SEL_CFG volatile.Register32 // 0x328 + FUNC118_IN_SEL_CFG volatile.Register32 // 0x32C + FUNC119_IN_SEL_CFG volatile.Register32 // 0x330 + FUNC120_IN_SEL_CFG volatile.Register32 // 0x334 + FUNC121_IN_SEL_CFG volatile.Register32 // 0x338 + FUNC122_IN_SEL_CFG volatile.Register32 // 0x33C + FUNC123_IN_SEL_CFG volatile.Register32 // 0x340 + FUNC124_IN_SEL_CFG volatile.Register32 // 0x344 + FUNC125_IN_SEL_CFG volatile.Register32 // 0x348 + FUNC126_IN_SEL_CFG volatile.Register32 // 0x34C + FUNC127_IN_SEL_CFG volatile.Register32 // 0x350 + FUNC128_IN_SEL_CFG volatile.Register32 // 0x354 + FUNC129_IN_SEL_CFG volatile.Register32 // 0x358 + FUNC130_IN_SEL_CFG volatile.Register32 // 0x35C + FUNC131_IN_SEL_CFG volatile.Register32 // 0x360 + FUNC132_IN_SEL_CFG volatile.Register32 // 0x364 + FUNC133_IN_SEL_CFG volatile.Register32 // 0x368 + FUNC134_IN_SEL_CFG volatile.Register32 // 0x36C + FUNC135_IN_SEL_CFG volatile.Register32 // 0x370 + FUNC136_IN_SEL_CFG volatile.Register32 // 0x374 + FUNC137_IN_SEL_CFG volatile.Register32 // 0x378 + FUNC138_IN_SEL_CFG volatile.Register32 // 0x37C + FUNC139_IN_SEL_CFG volatile.Register32 // 0x380 + FUNC140_IN_SEL_CFG volatile.Register32 // 0x384 + FUNC141_IN_SEL_CFG volatile.Register32 // 0x388 + FUNC142_IN_SEL_CFG volatile.Register32 // 0x38C + FUNC143_IN_SEL_CFG volatile.Register32 // 0x390 + FUNC144_IN_SEL_CFG volatile.Register32 // 0x394 + FUNC145_IN_SEL_CFG volatile.Register32 // 0x398 + FUNC146_IN_SEL_CFG volatile.Register32 // 0x39C + FUNC147_IN_SEL_CFG volatile.Register32 // 0x3A0 + FUNC148_IN_SEL_CFG volatile.Register32 // 0x3A4 + FUNC149_IN_SEL_CFG volatile.Register32 // 0x3A8 + FUNC150_IN_SEL_CFG volatile.Register32 // 0x3AC + FUNC151_IN_SEL_CFG volatile.Register32 // 0x3B0 + FUNC152_IN_SEL_CFG volatile.Register32 // 0x3B4 + FUNC153_IN_SEL_CFG volatile.Register32 // 0x3B8 + FUNC154_IN_SEL_CFG volatile.Register32 // 0x3BC + FUNC155_IN_SEL_CFG volatile.Register32 // 0x3C0 + FUNC156_IN_SEL_CFG volatile.Register32 // 0x3C4 + FUNC157_IN_SEL_CFG volatile.Register32 // 0x3C8 + FUNC158_IN_SEL_CFG volatile.Register32 // 0x3CC + FUNC159_IN_SEL_CFG volatile.Register32 // 0x3D0 + FUNC160_IN_SEL_CFG volatile.Register32 // 0x3D4 + FUNC161_IN_SEL_CFG volatile.Register32 // 0x3D8 + FUNC162_IN_SEL_CFG volatile.Register32 // 0x3DC + FUNC163_IN_SEL_CFG volatile.Register32 // 0x3E0 + FUNC164_IN_SEL_CFG volatile.Register32 // 0x3E4 + FUNC165_IN_SEL_CFG volatile.Register32 // 0x3E8 + FUNC166_IN_SEL_CFG volatile.Register32 // 0x3EC + FUNC167_IN_SEL_CFG volatile.Register32 // 0x3F0 + FUNC168_IN_SEL_CFG volatile.Register32 // 0x3F4 + FUNC169_IN_SEL_CFG volatile.Register32 // 0x3F8 + FUNC170_IN_SEL_CFG volatile.Register32 // 0x3FC + FUNC171_IN_SEL_CFG volatile.Register32 // 0x400 + FUNC172_IN_SEL_CFG volatile.Register32 // 0x404 + FUNC173_IN_SEL_CFG volatile.Register32 // 0x408 + FUNC174_IN_SEL_CFG volatile.Register32 // 0x40C + FUNC175_IN_SEL_CFG volatile.Register32 // 0x410 + FUNC176_IN_SEL_CFG volatile.Register32 // 0x414 + FUNC177_IN_SEL_CFG volatile.Register32 // 0x418 + FUNC178_IN_SEL_CFG volatile.Register32 // 0x41C + FUNC179_IN_SEL_CFG volatile.Register32 // 0x420 + FUNC180_IN_SEL_CFG volatile.Register32 // 0x424 + FUNC181_IN_SEL_CFG volatile.Register32 // 0x428 + FUNC182_IN_SEL_CFG volatile.Register32 // 0x42C + FUNC183_IN_SEL_CFG volatile.Register32 // 0x430 + FUNC184_IN_SEL_CFG volatile.Register32 // 0x434 + FUNC185_IN_SEL_CFG volatile.Register32 // 0x438 + FUNC186_IN_SEL_CFG volatile.Register32 // 0x43C + FUNC187_IN_SEL_CFG volatile.Register32 // 0x440 + FUNC188_IN_SEL_CFG volatile.Register32 // 0x444 + FUNC189_IN_SEL_CFG volatile.Register32 // 0x448 + FUNC190_IN_SEL_CFG volatile.Register32 // 0x44C + FUNC191_IN_SEL_CFG volatile.Register32 // 0x450 + FUNC192_IN_SEL_CFG volatile.Register32 // 0x454 + FUNC193_IN_SEL_CFG volatile.Register32 // 0x458 + FUNC194_IN_SEL_CFG volatile.Register32 // 0x45C + FUNC195_IN_SEL_CFG volatile.Register32 // 0x460 + FUNC196_IN_SEL_CFG volatile.Register32 // 0x464 + FUNC197_IN_SEL_CFG volatile.Register32 // 0x468 + FUNC198_IN_SEL_CFG volatile.Register32 // 0x46C + FUNC199_IN_SEL_CFG volatile.Register32 // 0x470 + FUNC200_IN_SEL_CFG volatile.Register32 // 0x474 + FUNC201_IN_SEL_CFG volatile.Register32 // 0x478 + FUNC202_IN_SEL_CFG volatile.Register32 // 0x47C + FUNC203_IN_SEL_CFG volatile.Register32 // 0x480 + FUNC204_IN_SEL_CFG volatile.Register32 // 0x484 + FUNC205_IN_SEL_CFG volatile.Register32 // 0x488 + FUNC206_IN_SEL_CFG volatile.Register32 // 0x48C + FUNC207_IN_SEL_CFG volatile.Register32 // 0x490 + FUNC208_IN_SEL_CFG volatile.Register32 // 0x494 + FUNC209_IN_SEL_CFG volatile.Register32 // 0x498 + FUNC210_IN_SEL_CFG volatile.Register32 // 0x49C + FUNC211_IN_SEL_CFG volatile.Register32 // 0x4A0 + FUNC212_IN_SEL_CFG volatile.Register32 // 0x4A4 + FUNC213_IN_SEL_CFG volatile.Register32 // 0x4A8 + FUNC214_IN_SEL_CFG volatile.Register32 // 0x4AC + FUNC215_IN_SEL_CFG volatile.Register32 // 0x4B0 + FUNC216_IN_SEL_CFG volatile.Register32 // 0x4B4 + FUNC217_IN_SEL_CFG volatile.Register32 // 0x4B8 + FUNC218_IN_SEL_CFG volatile.Register32 // 0x4BC + FUNC219_IN_SEL_CFG volatile.Register32 // 0x4C0 + FUNC220_IN_SEL_CFG volatile.Register32 // 0x4C4 + FUNC221_IN_SEL_CFG volatile.Register32 // 0x4C8 + FUNC222_IN_SEL_CFG volatile.Register32 // 0x4CC + FUNC223_IN_SEL_CFG volatile.Register32 // 0x4D0 + FUNC224_IN_SEL_CFG volatile.Register32 // 0x4D4 + FUNC225_IN_SEL_CFG volatile.Register32 // 0x4D8 + FUNC226_IN_SEL_CFG volatile.Register32 // 0x4DC + FUNC227_IN_SEL_CFG volatile.Register32 // 0x4E0 + FUNC228_IN_SEL_CFG volatile.Register32 // 0x4E4 + FUNC229_IN_SEL_CFG volatile.Register32 // 0x4E8 + FUNC230_IN_SEL_CFG volatile.Register32 // 0x4EC + FUNC231_IN_SEL_CFG volatile.Register32 // 0x4F0 + FUNC232_IN_SEL_CFG volatile.Register32 // 0x4F4 + FUNC233_IN_SEL_CFG volatile.Register32 // 0x4F8 + FUNC234_IN_SEL_CFG volatile.Register32 // 0x4FC + FUNC235_IN_SEL_CFG volatile.Register32 // 0x500 + FUNC236_IN_SEL_CFG volatile.Register32 // 0x504 + FUNC237_IN_SEL_CFG volatile.Register32 // 0x508 + FUNC238_IN_SEL_CFG volatile.Register32 // 0x50C + FUNC239_IN_SEL_CFG volatile.Register32 // 0x510 + FUNC240_IN_SEL_CFG volatile.Register32 // 0x514 + FUNC241_IN_SEL_CFG volatile.Register32 // 0x518 + FUNC242_IN_SEL_CFG volatile.Register32 // 0x51C + FUNC243_IN_SEL_CFG volatile.Register32 // 0x520 + FUNC244_IN_SEL_CFG volatile.Register32 // 0x524 + FUNC245_IN_SEL_CFG volatile.Register32 // 0x528 + FUNC246_IN_SEL_CFG volatile.Register32 // 0x52C + FUNC247_IN_SEL_CFG volatile.Register32 // 0x530 + FUNC248_IN_SEL_CFG volatile.Register32 // 0x534 + FUNC249_IN_SEL_CFG volatile.Register32 // 0x538 + FUNC250_IN_SEL_CFG volatile.Register32 // 0x53C + FUNC251_IN_SEL_CFG volatile.Register32 // 0x540 + FUNC252_IN_SEL_CFG volatile.Register32 // 0x544 + FUNC253_IN_SEL_CFG volatile.Register32 // 0x548 + FUNC254_IN_SEL_CFG volatile.Register32 // 0x54C + FUNC255_IN_SEL_CFG volatile.Register32 // 0x550 + FUNC0_OUT_SEL_CFG volatile.Register32 // 0x554 + FUNC1_OUT_SEL_CFG volatile.Register32 // 0x558 + FUNC2_OUT_SEL_CFG volatile.Register32 // 0x55C + FUNC3_OUT_SEL_CFG volatile.Register32 // 0x560 + FUNC4_OUT_SEL_CFG volatile.Register32 // 0x564 + FUNC5_OUT_SEL_CFG volatile.Register32 // 0x568 + FUNC6_OUT_SEL_CFG volatile.Register32 // 0x56C + FUNC7_OUT_SEL_CFG volatile.Register32 // 0x570 + FUNC8_OUT_SEL_CFG volatile.Register32 // 0x574 + FUNC9_OUT_SEL_CFG volatile.Register32 // 0x578 + FUNC10_OUT_SEL_CFG volatile.Register32 // 0x57C + FUNC11_OUT_SEL_CFG volatile.Register32 // 0x580 + FUNC12_OUT_SEL_CFG volatile.Register32 // 0x584 + FUNC13_OUT_SEL_CFG volatile.Register32 // 0x588 + FUNC14_OUT_SEL_CFG volatile.Register32 // 0x58C + FUNC15_OUT_SEL_CFG volatile.Register32 // 0x590 + FUNC16_OUT_SEL_CFG volatile.Register32 // 0x594 + FUNC17_OUT_SEL_CFG volatile.Register32 // 0x598 + FUNC18_OUT_SEL_CFG volatile.Register32 // 0x59C + FUNC19_OUT_SEL_CFG volatile.Register32 // 0x5A0 + FUNC20_OUT_SEL_CFG volatile.Register32 // 0x5A4 + FUNC21_OUT_SEL_CFG volatile.Register32 // 0x5A8 + FUNC22_OUT_SEL_CFG volatile.Register32 // 0x5AC + FUNC23_OUT_SEL_CFG volatile.Register32 // 0x5B0 + FUNC24_OUT_SEL_CFG volatile.Register32 // 0x5B4 + FUNC25_OUT_SEL_CFG volatile.Register32 // 0x5B8 + FUNC26_OUT_SEL_CFG volatile.Register32 // 0x5BC + FUNC27_OUT_SEL_CFG volatile.Register32 // 0x5C0 + FUNC28_OUT_SEL_CFG volatile.Register32 // 0x5C4 + FUNC29_OUT_SEL_CFG volatile.Register32 // 0x5C8 + FUNC30_OUT_SEL_CFG volatile.Register32 // 0x5CC + FUNC31_OUT_SEL_CFG volatile.Register32 // 0x5D0 + FUNC32_OUT_SEL_CFG volatile.Register32 // 0x5D4 + FUNC33_OUT_SEL_CFG volatile.Register32 // 0x5D8 + FUNC34_OUT_SEL_CFG volatile.Register32 // 0x5DC + FUNC35_OUT_SEL_CFG volatile.Register32 // 0x5E0 + FUNC36_OUT_SEL_CFG volatile.Register32 // 0x5E4 + FUNC37_OUT_SEL_CFG volatile.Register32 // 0x5E8 + FUNC38_OUT_SEL_CFG volatile.Register32 // 0x5EC + FUNC39_OUT_SEL_CFG volatile.Register32 // 0x5F0 + FUNC40_OUT_SEL_CFG volatile.Register32 // 0x5F4 + FUNC41_OUT_SEL_CFG volatile.Register32 // 0x5F8 + FUNC42_OUT_SEL_CFG volatile.Register32 // 0x5FC + FUNC43_OUT_SEL_CFG volatile.Register32 // 0x600 + FUNC44_OUT_SEL_CFG volatile.Register32 // 0x604 + FUNC45_OUT_SEL_CFG volatile.Register32 // 0x608 + FUNC46_OUT_SEL_CFG volatile.Register32 // 0x60C + FUNC47_OUT_SEL_CFG volatile.Register32 // 0x610 + FUNC48_OUT_SEL_CFG volatile.Register32 // 0x614 + FUNC49_OUT_SEL_CFG volatile.Register32 // 0x618 + FUNC50_OUT_SEL_CFG volatile.Register32 // 0x61C + FUNC51_OUT_SEL_CFG volatile.Register32 // 0x620 + FUNC52_OUT_SEL_CFG volatile.Register32 // 0x624 + FUNC53_OUT_SEL_CFG volatile.Register32 // 0x628 + CLOCK_GATE volatile.Register32 // 0x62C + _ [204]byte + REG_DATE volatile.Register32 // 0x6FC +} + +// GPIO.BT_SELECT: GPIO bit select register +func (o *GPIO_Type) SetBT_SELECT(value uint32) { + volatile.StoreUint32(&o.BT_SELECT.Reg, value) +} +func (o *GPIO_Type) GetBT_SELECT() uint32 { + return volatile.LoadUint32(&o.BT_SELECT.Reg) +} + +// GPIO.OUT: GPIO output register for GPIO0-31 +func (o *GPIO_Type) SetOUT(value uint32) { + volatile.StoreUint32(&o.OUT.Reg, value) +} +func (o *GPIO_Type) GetOUT() uint32 { + return volatile.LoadUint32(&o.OUT.Reg) +} + +// GPIO.OUT_W1TS: GPIO output set register for GPIO0-31 +func (o *GPIO_Type) SetOUT_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT_W1TS.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT_W1TS.Reg) +} + +// GPIO.OUT_W1TC: GPIO output clear register for GPIO0-31 +func (o *GPIO_Type) SetOUT_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT_W1TC.Reg, value) +} +func (o *GPIO_Type) GetOUT_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT_W1TC.Reg) +} + +// GPIO.OUT1: GPIO output register for GPIO32-53 +func (o *GPIO_Type) SetOUT1_DATA_ORIG(value uint32) { + volatile.StoreUint32(&o.OUT1.Reg, volatile.LoadUint32(&o.OUT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetOUT1_DATA_ORIG() uint32 { + return volatile.LoadUint32(&o.OUT1.Reg) & 0x3fffff +} + +// GPIO.OUT1_W1TS: GPIO output set register for GPIO32-53 +func (o *GPIO_Type) SetOUT1_W1TS(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TS.Reg, volatile.LoadUint32(&o.OUT1_W1TS.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetOUT1_W1TS() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TS.Reg) & 0x3fffff +} + +// GPIO.OUT1_W1TC: GPIO output clear register for GPIO32-53 +func (o *GPIO_Type) SetOUT1_W1TC(value uint32) { + volatile.StoreUint32(&o.OUT1_W1TC.Reg, volatile.LoadUint32(&o.OUT1_W1TC.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetOUT1_W1TC() uint32 { + return volatile.LoadUint32(&o.OUT1_W1TC.Reg) & 0x3fffff +} + +// GPIO.SDIO_SELECT: GPIO sdio select register +func (o *GPIO_Type) SetSDIO_SELECT_SDIO_SEL(value uint32) { + volatile.StoreUint32(&o.SDIO_SELECT.Reg, volatile.LoadUint32(&o.SDIO_SELECT.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetSDIO_SELECT_SDIO_SEL() uint32 { + return volatile.LoadUint32(&o.SDIO_SELECT.Reg) & 0xff +} + +// GPIO.ENABLE: GPIO output enable register for GPIO0-31 +func (o *GPIO_Type) SetENABLE(value uint32) { + volatile.StoreUint32(&o.ENABLE.Reg, value) +} +func (o *GPIO_Type) GetENABLE() uint32 { + return volatile.LoadUint32(&o.ENABLE.Reg) +} + +// GPIO.ENABLE_W1TS: GPIO output enable set register for GPIO0-31 +func (o *GPIO_Type) SetENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TS.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) +} + +// GPIO.ENABLE_W1TC: GPIO output enable clear register for GPIO0-31 +func (o *GPIO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, value) +} +func (o *GPIO_Type) GetENABLE_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) +} + +// GPIO.ENABLE1: GPIO output enable register for GPIO32-53 +func (o *GPIO_Type) SetENABLE1_DATA(value uint32) { + volatile.StoreUint32(&o.ENABLE1.Reg, volatile.LoadUint32(&o.ENABLE1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetENABLE1_DATA() uint32 { + return volatile.LoadUint32(&o.ENABLE1.Reg) & 0x3fffff +} + +// GPIO.ENABLE1_W1TS: GPIO output enable set register for GPIO32-53 +func (o *GPIO_Type) SetENABLE1_W1TS(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TS.Reg, volatile.LoadUint32(&o.ENABLE1_W1TS.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TS() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TS.Reg) & 0x3fffff +} + +// GPIO.ENABLE1_W1TC: GPIO output enable clear register for GPIO32-53 +func (o *GPIO_Type) SetENABLE1_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE1_W1TC.Reg, volatile.LoadUint32(&o.ENABLE1_W1TC.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetENABLE1_W1TC() uint32 { + return volatile.LoadUint32(&o.ENABLE1_W1TC.Reg) & 0x3fffff +} + +// GPIO.STRAP: pad strapping register +func (o *GPIO_Type) SetSTRAP_STRAPPING(value uint32) { + volatile.StoreUint32(&o.STRAP.Reg, volatile.LoadUint32(&o.STRAP.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetSTRAP_STRAPPING() uint32 { + return volatile.LoadUint32(&o.STRAP.Reg) & 0xffff +} + +// GPIO.IN: GPIO input register for GPIO0-31 +func (o *GPIO_Type) SetIN(value uint32) { + volatile.StoreUint32(&o.IN.Reg, value) +} +func (o *GPIO_Type) GetIN() uint32 { + return volatile.LoadUint32(&o.IN.Reg) +} + +// GPIO.IN1: GPIO input register for GPIO32-53 +func (o *GPIO_Type) SetIN1_DATA_NEXT(value uint32) { + volatile.StoreUint32(&o.IN1.Reg, volatile.LoadUint32(&o.IN1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetIN1_DATA_NEXT() uint32 { + return volatile.LoadUint32(&o.IN1.Reg) & 0x3fffff +} + +// GPIO.STATUS: GPIO interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) +} + +// GPIO.STATUS_W1TS: GPIO interrupt status set register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TS.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TS.Reg) +} + +// GPIO.STATUS_W1TC: GPIO interrupt status clear register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS_W1TC.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS_W1TC.Reg) +} + +// GPIO.STATUS1: GPIO interrupt status register for GPIO32-53 +func (o *GPIO_Type) SetSTATUS1_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.STATUS1.Reg, volatile.LoadUint32(&o.STATUS1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetSTATUS1_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.STATUS1.Reg) & 0x3fffff +} + +// GPIO.STATUS1_W1TS: GPIO interrupt status set register for GPIO32-53 +func (o *GPIO_Type) SetSTATUS1_W1TS(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TS.Reg, volatile.LoadUint32(&o.STATUS1_W1TS.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TS() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TS.Reg) & 0x3fffff +} + +// GPIO.STATUS1_W1TC: GPIO interrupt status clear register for GPIO32-53 +func (o *GPIO_Type) SetSTATUS1_W1TC(value uint32) { + volatile.StoreUint32(&o.STATUS1_W1TC.Reg, volatile.LoadUint32(&o.STATUS1_W1TC.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetSTATUS1_W1TC() uint32 { + return volatile.LoadUint32(&o.STATUS1_W1TC.Reg) & 0x3fffff +} + +// GPIO.PCPU_INT: GPIO PRO_CPU interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetPCPU_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_INT.Reg) +} + +// GPIO.PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetPCPU_NMI_INT(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT.Reg, value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT.Reg) +} + +// GPIO.CPUSDIO_INT: GPIO CPUSDIO interrupt status register for GPIO0-31 +func (o *GPIO_Type) SetCPUSDIO_INT(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT.Reg, value) +} +func (o *GPIO_Type) GetCPUSDIO_INT() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT.Reg) +} + +// GPIO.PCPU_INT1: GPIO PRO_CPU interrupt status register for GPIO32-53 +func (o *GPIO_Type) SetPCPU_INT1_PROCPU_INT1(value uint32) { + volatile.StoreUint32(&o.PCPU_INT1.Reg, volatile.LoadUint32(&o.PCPU_INT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetPCPU_INT1_PROCPU_INT1() uint32 { + return volatile.LoadUint32(&o.PCPU_INT1.Reg) & 0x3fffff +} + +// GPIO.PCPU_NMI_INT1: GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 +func (o *GPIO_Type) SetPCPU_NMI_INT1_PROCPU_NMI_INT1(value uint32) { + volatile.StoreUint32(&o.PCPU_NMI_INT1.Reg, volatile.LoadUint32(&o.PCPU_NMI_INT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetPCPU_NMI_INT1_PROCPU_NMI_INT1() uint32 { + return volatile.LoadUint32(&o.PCPU_NMI_INT1.Reg) & 0x3fffff +} + +// GPIO.CPUSDIO_INT1: GPIO CPUSDIO interrupt status register for GPIO32-53 +func (o *GPIO_Type) SetCPUSDIO_INT1_SDIO_INT1(value uint32) { + volatile.StoreUint32(&o.CPUSDIO_INT1.Reg, volatile.LoadUint32(&o.CPUSDIO_INT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetCPUSDIO_INT1_SDIO_INT1() uint32 { + return volatile.LoadUint32(&o.CPUSDIO_INT1.Reg) & 0x3fffff +} + +// GPIO.PIN0: GPIO pin configuration register +func (o *GPIO_Type) SetPIN0_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN0_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN0.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN0_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN0_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN0_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN0_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN1: GPIO pin configuration register +func (o *GPIO_Type) SetPIN1_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN1_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN1.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN1_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN1_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN1_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN1_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN2: GPIO pin configuration register +func (o *GPIO_Type) SetPIN2_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN2_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN2.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN2_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN2_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN2_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN2_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN3: GPIO pin configuration register +func (o *GPIO_Type) SetPIN3_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN3_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN3.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN3_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN3_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN3_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN3_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN4: GPIO pin configuration register +func (o *GPIO_Type) SetPIN4_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN4_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN4.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN4_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN4_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN4_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN4_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN5: GPIO pin configuration register +func (o *GPIO_Type) SetPIN5_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN5_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN5.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN5_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN5_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN5_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN5_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN6: GPIO pin configuration register +func (o *GPIO_Type) SetPIN6_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN6_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN6.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN6_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN6_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN6_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN6_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN7: GPIO pin configuration register +func (o *GPIO_Type) SetPIN7_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN7_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN7.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN7_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN7_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN7_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN7_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN8: GPIO pin configuration register +func (o *GPIO_Type) SetPIN8_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN8_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN8.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN8_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN8_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN8_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN8_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN9: GPIO pin configuration register +func (o *GPIO_Type) SetPIN9_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN9_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN9.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN9_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN9_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN9_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN9_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN10: GPIO pin configuration register +func (o *GPIO_Type) SetPIN10_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN10_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN10.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN10_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN10_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN10_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN10_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN10_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN10_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN11: GPIO pin configuration register +func (o *GPIO_Type) SetPIN11_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN11_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN11.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN11_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN11_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN11_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN11_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN11_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN11_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN12: GPIO pin configuration register +func (o *GPIO_Type) SetPIN12_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN12_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN12.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN12_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN12_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN12_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN12_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN12_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN12_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN13: GPIO pin configuration register +func (o *GPIO_Type) SetPIN13_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN13_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN13.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN13_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN13_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN13_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN13_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN13_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN13_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN14: GPIO pin configuration register +func (o *GPIO_Type) SetPIN14_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN14_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN14.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN14_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN14_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN14_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN14_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN14_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN14_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN15: GPIO pin configuration register +func (o *GPIO_Type) SetPIN15_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN15_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN15.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN15_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN15_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN15_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN15_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN15_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN15_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN16: GPIO pin configuration register +func (o *GPIO_Type) SetPIN16_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN16_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN16.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN16_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN16_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN16_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN16_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN16_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN16_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN17: GPIO pin configuration register +func (o *GPIO_Type) SetPIN17_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN17_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN17.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN17_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN17_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN17_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN17_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN17_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN17_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN18: GPIO pin configuration register +func (o *GPIO_Type) SetPIN18_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN18_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN18.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN18_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN18_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN18_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN18_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN18_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN18_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN19: GPIO pin configuration register +func (o *GPIO_Type) SetPIN19_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN19_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN19.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN19_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN19_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN19_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN19_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN19_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN19_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN20: GPIO pin configuration register +func (o *GPIO_Type) SetPIN20_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN20_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN20.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN20_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN20_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN20_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN20_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN20_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN20_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN21: GPIO pin configuration register +func (o *GPIO_Type) SetPIN21_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN21_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN21.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN21_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN21_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN21_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN21_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN21_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN21_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN22: GPIO pin configuration register +func (o *GPIO_Type) SetPIN22_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN22_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN22.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN22_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN22_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN22_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN22_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN22_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN22_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN22_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN22_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN22_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN22_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN22_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN22_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN22.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN23: GPIO pin configuration register +func (o *GPIO_Type) SetPIN23_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN23_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN23.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN23_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN23_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN23_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN23_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN23_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN23_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN23_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN23_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN23_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN23_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN23_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN23_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN23.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN24: GPIO pin configuration register +func (o *GPIO_Type) SetPIN24_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN24_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN24.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN24_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN24_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN24_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN24_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN24_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN24_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN24_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN24_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN24_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN24_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN24_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN24_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN24.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN25: GPIO pin configuration register +func (o *GPIO_Type) SetPIN25_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN25_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN25.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN25_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN25_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN25_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN25_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN25_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN25_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN25_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN25_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN25_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN25_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN25_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN25_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN25.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN26: GPIO pin configuration register +func (o *GPIO_Type) SetPIN26_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN26_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN26.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN26_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN26_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN26_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN26_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN26_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN26_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN26_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN26_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN26_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN26_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN26_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN26_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN26.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN27: GPIO pin configuration register +func (o *GPIO_Type) SetPIN27_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN27_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN27.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN27_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN27_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN27_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN27_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN27_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN27_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN27_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN27_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN27_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN27_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN27_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN27_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN27.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN28: GPIO pin configuration register +func (o *GPIO_Type) SetPIN28_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN28_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN28.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN28_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN28_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN28_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN28_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN28_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN28_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN28_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN28_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN28_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN28_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN28_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN28_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN28.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN29: GPIO pin configuration register +func (o *GPIO_Type) SetPIN29_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN29_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN29.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN29_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN29_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN29_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN29_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN29_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN29_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN29_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN29_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN29_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN29_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN29_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN29_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN29.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN30: GPIO pin configuration register +func (o *GPIO_Type) SetPIN30_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN30_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN30.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN30_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN30_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN30_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN30_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN30_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN30_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN30_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN30_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN30_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN30_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN30_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN30_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN30.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN31: GPIO pin configuration register +func (o *GPIO_Type) SetPIN31_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN31_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN31.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN31_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN31_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN31_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN31_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN31_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN31_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN31_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN31_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN31_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN31_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN31_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN31_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN31.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN32: GPIO pin configuration register +func (o *GPIO_Type) SetPIN32_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN32_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN32.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN32_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN32_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN32_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN32_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN32_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN32_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN32_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN32_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN32_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN32_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN32_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN32_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN32.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN33: GPIO pin configuration register +func (o *GPIO_Type) SetPIN33_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN33_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN33.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN33_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN33_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN33_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN33_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN33_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN33_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN33_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN33_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN33_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN33_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN33_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN33_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN33.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN34: GPIO pin configuration register +func (o *GPIO_Type) SetPIN34_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN34_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN34.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN34_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN34_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN34_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN34_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN34_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN34_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN34_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN34_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN34_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN34_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN34_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN34_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN34.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN35: GPIO pin configuration register +func (o *GPIO_Type) SetPIN35_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN35_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN35.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN35_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN35_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN35_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN35_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN35_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN35_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN35_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN35_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN35_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN35_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN35_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN35_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN35.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN36: GPIO pin configuration register +func (o *GPIO_Type) SetPIN36_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN36_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN36.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN36_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN36_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN36_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN36_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN36_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN36_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN36_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN36_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN36_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN36_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN36_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN36_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN36.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN37: GPIO pin configuration register +func (o *GPIO_Type) SetPIN37_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN37_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN37.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN37_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN37_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN37_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN37_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN37_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN37_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN37_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN37_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN37_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN37_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN37_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN37_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN37.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN38: GPIO pin configuration register +func (o *GPIO_Type) SetPIN38_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN38_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN38.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN38_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN38_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN38_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN38_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN38_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN38_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN38_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN38_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN38_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN38_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN38_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN38_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN38.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN39: GPIO pin configuration register +func (o *GPIO_Type) SetPIN39_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN39_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN39.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN39_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN39_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN39_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN39_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN39_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN39_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN39_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN39_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN39_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN39_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN39_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN39_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN39.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN40: GPIO pin configuration register +func (o *GPIO_Type) SetPIN40_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN40_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN40.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN40_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN40_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN40_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN40_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN40_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN40_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN40_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN40_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN40_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN40_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN40_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN40_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN40.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN41: GPIO pin configuration register +func (o *GPIO_Type) SetPIN41_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN41_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN41.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN41_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN41_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN41_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN41_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN41_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN41_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN41_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN41_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN41_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN41_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN41_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN41_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN41.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN42: GPIO pin configuration register +func (o *GPIO_Type) SetPIN42_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN42_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN42.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN42_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN42_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN42_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN42_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN42_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN42_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN42_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN42_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN42_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN42_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN42_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN42_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN42.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN43: GPIO pin configuration register +func (o *GPIO_Type) SetPIN43_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN43_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN43.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN43_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN43_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN43_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN43_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN43_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN43_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN43_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN43_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN43_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN43_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN43_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN43_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN43.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN44: GPIO pin configuration register +func (o *GPIO_Type) SetPIN44_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN44_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN44.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN44_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN44_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN44_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN44_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN44_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN44_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN44_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN44_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN44_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN44_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN44_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN44_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN44.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN45: GPIO pin configuration register +func (o *GPIO_Type) SetPIN45_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN45_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN45.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN45_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN45_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN45_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN45_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN45_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN45_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN45_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN45_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN45_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN45_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN45_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN45_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN45.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN46: GPIO pin configuration register +func (o *GPIO_Type) SetPIN46_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN46_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN46.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN46_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN46_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN46_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN46_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN46_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN46_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN46_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN46_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN46_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN46_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN46_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN46_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN46.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN47: GPIO pin configuration register +func (o *GPIO_Type) SetPIN47_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN47_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN47.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN47_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN47_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN47_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN47_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN47_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN47_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN47_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN47_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN47_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN47_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN47_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN47_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN47.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN48: GPIO pin configuration register +func (o *GPIO_Type) SetPIN48_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN48_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN48.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN48_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN48_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN48_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN48_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN48_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN48_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN48_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN48_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN48_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN48_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN48_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN48_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN48.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN49: GPIO pin configuration register +func (o *GPIO_Type) SetPIN49_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN49_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN49.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN49_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN49_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN49_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN49_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN49_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN49_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN49_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN49_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN49_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN49_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN49_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN49_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN49.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN50: GPIO pin configuration register +func (o *GPIO_Type) SetPIN50_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN50_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN50.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN50_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN50_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN50_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN50_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN50_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN50_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN50_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN50_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN50_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN50_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN50_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN50_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN50.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN51: GPIO pin configuration register +func (o *GPIO_Type) SetPIN51_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN51_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN51.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN51_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN51_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN51_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN51_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN51_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN51_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN51_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN51_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN51_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN51_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN51_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN51_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN51.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN52: GPIO pin configuration register +func (o *GPIO_Type) SetPIN52_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN52_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN52.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN52_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN52_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN52_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN52_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN52_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN52_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN52_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN52_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN52_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN52_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN52_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN52_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN52.Reg) & 0x3e000) >> 13 +} + +// GPIO.PIN53: GPIO pin configuration register +func (o *GPIO_Type) SetPIN53_SYNC2_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x3)|value) +} +func (o *GPIO_Type) GetPIN53_SYNC2_BYPASS() uint32 { + return volatile.LoadUint32(&o.PIN53.Reg) & 0x3 +} +func (o *GPIO_Type) SetPIN53_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetPIN53_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetPIN53_SYNC1_BYPASS(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x18)|value<<3) +} +func (o *GPIO_Type) GetPIN53_SYNC1_BYPASS() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x18) >> 3 +} +func (o *GPIO_Type) SetPIN53_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetPIN53_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetPIN53_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetPIN53_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetPIN53_CONFIG(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x1800)|value<<11) +} +func (o *GPIO_Type) GetPIN53_CONFIG() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x1800) >> 11 +} +func (o *GPIO_Type) SetPIN53_INT_ENA(value uint32) { + volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x3e000)|value<<13) +} +func (o *GPIO_Type) GetPIN53_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.PIN53.Reg) & 0x3e000) >> 13 +} + +// GPIO.STATUS_NEXT: GPIO interrupt source register for GPIO0-31 +func (o *GPIO_Type) SetSTATUS_NEXT(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT.Reg, value) +} +func (o *GPIO_Type) GetSTATUS_NEXT() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT.Reg) +} + +// GPIO.STATUS_NEXT1: GPIO interrupt source register for GPIO32-53 +func (o *GPIO_Type) SetSTATUS_NEXT1_STATUS_INTERRUPT_NEXT1(value uint32) { + volatile.StoreUint32(&o.STATUS_NEXT1.Reg, volatile.LoadUint32(&o.STATUS_NEXT1.Reg)&^(0x3fffff)|value) +} +func (o *GPIO_Type) GetSTATUS_NEXT1_STATUS_INTERRUPT_NEXT1() uint32 { + return volatile.LoadUint32(&o.STATUS_NEXT1.Reg) & 0x3fffff +} + +// GPIO.FUNC0_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC0_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC0_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC1_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC2_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC3_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC4_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC5_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC6_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC7_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC8_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC9_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC10_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC11_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC12_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC13_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC14_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC15_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC16_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC17_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC18_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC19_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC20_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC21_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC22_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC23_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC24_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC25_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC26_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC27_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC28_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC29_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC30_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC31_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC32_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC33_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC34_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC35_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC36_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC37_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC38_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC39_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC40_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC41_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC42_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC43_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC44_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC45_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC46_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC47_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC48_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC49_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC50_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC51_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC52_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC53_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC54_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC55_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC56_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC57_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC58_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC59_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC60_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC61_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC62_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC63_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC64_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC65_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC66_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC67_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC68_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC69_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC70_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC71_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC72_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC73_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC74_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC75_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC76_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC77_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC78_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC79_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC80_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC81_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC82_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC83_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC84_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC85_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC86_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC87_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC88_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC89_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC90_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC91_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC92_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC93_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC94_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC95_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC96_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC97_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC98_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC99_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC100_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC101_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC102_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC103_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC104_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC105_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC106_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC107_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC108_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC109_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC110_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC111_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC112_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC113_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC114_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC115_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC116_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC117_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC118_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC119_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC120_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC121_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC122_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC123_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC124_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC125_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC126_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC127_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC128_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC129_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC130_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC131_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC132_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC133_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC134_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC135_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC136_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC137_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC138_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC139_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC140_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC141_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC142_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC143_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC144_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC145_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC146_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC147_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC148_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC149_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC150_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC151_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC152_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC153_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC154_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC155_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC156_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC157_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC158_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC159_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC160_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC161_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC162_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC163_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC164_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC165_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC166_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC167_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC168_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC169_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC170_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC171_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC172_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC173_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC174_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC175_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC176_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC177_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC178_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC179_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC180_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC181_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC182_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC183_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC184_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC185_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC186_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC187_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC188_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC189_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC190_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC191_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC192_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC193_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC194_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC195_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC196_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC197_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC198_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC199_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC200_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC201_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC202_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC203_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC204_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC205_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC206_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC207_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC208_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC209_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC210_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC211_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC212_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC213_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC214_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC215_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC216_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC217_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC218_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC219_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC220_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC221_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC222_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC223_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC224_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC225_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC226_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC227_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC228_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC229_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC230_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC231_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC232_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC233_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC234_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC235_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC236_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC237_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC238_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC239_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC240_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC241_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC242_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC243_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC244_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC245_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC246_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC247_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC248_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC249_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC250_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC251_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC252_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC253_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC254_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC255_IN_SEL_CFG: GPIO input function configuration register +func (o *GPIO_Type) SetFUNC255_IN_SEL_CFG_IN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC255_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg)&^(0x3f)|value) +} +func (o *GPIO_Type) GetFUNC255_IN_SEL_CFG_IN_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg) & 0x3f +} +func (o *GPIO_Type) SetFUNC255_IN_SEL_CFG_IN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC255_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg)&^(0x40)|value<<6) +} +func (o *GPIO_Type) GetFUNC255_IN_SEL_CFG_IN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg) & 0x40) >> 6 +} +func (o *GPIO_Type) SetFUNC255_IN_SEL_CFG_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC255_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg)&^(0x80)|value<<7) +} +func (o *GPIO_Type) GetFUNC255_IN_SEL_CFG_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC255_IN_SEL_CFG.Reg) & 0x80) >> 7 +} + +// GPIO.FUNC0_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC1_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC2_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC3_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC4_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC5_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC6_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC7_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC8_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC9_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC10_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC11_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC12_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC13_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC14_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC15_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC16_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC17_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC18_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC19_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC20_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC21_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC22_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC23_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC24_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC25_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC26_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC27_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC28_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC29_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC30_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC31_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC32_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC33_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC34_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC35_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC36_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC37_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC38_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC39_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC40_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC41_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC42_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC43_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC44_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC45_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC46_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC47_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC48_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC49_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC50_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC51_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC52_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.FUNC53_OUT_SEL_CFG: GPIO output function select register +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OUT_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x1ff)|value) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OUT_SEL() uint32 { + return volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x1ff +} +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x200)|value<<9) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x200) >> 9 +} +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OEN_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OEN_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OEN_INV_SEL(value uint32) { + volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x800)|value<<11) +} +func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OEN_INV_SEL() uint32 { + return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x800) >> 11 +} + +// GPIO.CLOCK_GATE: GPIO clock gate register +func (o *GPIO_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// GPIO.REG_DATE: GPIO version register +func (o *GPIO_Type) SetREG_DATE(value uint32) { + volatile.StoreUint32(&o.REG_DATE.Reg, volatile.LoadUint32(&o.REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *GPIO_Type) GetREG_DATE() uint32 { + return volatile.LoadUint32(&o.REG_DATE.Reg) & 0xfffffff +} + +// Sigma-Delta Modulation +type GPIOSD_Type struct { + SIGMADELTA0 volatile.Register32 // 0x0 + SIGMADELTA1 volatile.Register32 // 0x4 + SIGMADELTA2 volatile.Register32 // 0x8 + SIGMADELTA3 volatile.Register32 // 0xC + SIGMADELTA4 volatile.Register32 // 0x10 + SIGMADELTA5 volatile.Register32 // 0x14 + SIGMADELTA6 volatile.Register32 // 0x18 + SIGMADELTA7 volatile.Register32 // 0x1C + SIGMADELTA_CG volatile.Register32 // 0x20 + SIGMADELTA_MISC volatile.Register32 // 0x24 + SIGMADELTA_VERSION volatile.Register32 // 0x28 +} + +// GPIOSD.SIGMADELTA0: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA0_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA0_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA0_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA1: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA1_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA1_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA1_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA2: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA2_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA2_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA2_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA3: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA3_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA3_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA3_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA4: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA4_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA4_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA4_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA4_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA5: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA5_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA5_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA5_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA5_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA6: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA6_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA6_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA6_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA6_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA7: Duty Cycle Configure Register of SDM%s +func (o *GPIOSD_Type) SetSIGMADELTA7_SD_IN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA7_SD_IN() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff +} +func (o *GPIOSD_Type) SetSIGMADELTA7_SD_PRESCALE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff00)|value<<8) +} +func (o *GPIOSD_Type) GetSIGMADELTA7_SD_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff00) >> 8 +} + +// GPIOSD.SIGMADELTA_CG: Clock Gating Configure Register +func (o *GPIOSD_Type) SetSIGMADELTA_CG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_CG.Reg, volatile.LoadUint32(&o.SIGMADELTA_CG.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIOSD_Type) GetSIGMADELTA_CG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_CG.Reg) & 0x80000000) >> 31 +} + +// GPIOSD.SIGMADELTA_MISC: MISC Register +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_FUNCTION_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_FUNCTION_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x40000000) >> 30 +} +func (o *GPIOSD_Type) SetSIGMADELTA_MISC_SPI_SWAP(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIOSD_Type) GetSIGMADELTA_MISC_SPI_SWAP() uint32 { + return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x80000000) >> 31 +} + +// GPIOSD.SIGMADELTA_VERSION: Version Control Register +func (o *GPIOSD_Type) SetSIGMADELTA_VERSION_GPIO_SD_DATE(value uint32) { + volatile.StoreUint32(&o.SIGMADELTA_VERSION.Reg, volatile.LoadUint32(&o.SIGMADELTA_VERSION.Reg)&^(0xfffffff)|value) +} +func (o *GPIOSD_Type) GetSIGMADELTA_VERSION_GPIO_SD_DATE() uint32 { + return volatile.LoadUint32(&o.SIGMADELTA_VERSION.Reg) & 0xfffffff +} + +// HMAC (Hash-based Message Authentication Code) Accelerator +type HMAC_Type struct { + _ [64]byte + SET_START volatile.Register32 // 0x40 + SET_PARA_PURPOSE volatile.Register32 // 0x44 + SET_PARA_KEY volatile.Register32 // 0x48 + SET_PARA_FINISH volatile.Register32 // 0x4C + SET_MESSAGE_ONE volatile.Register32 // 0x50 + SET_MESSAGE_ING volatile.Register32 // 0x54 + SET_MESSAGE_END volatile.Register32 // 0x58 + SET_RESULT_FINISH volatile.Register32 // 0x5C + SET_INVALIDATE_JTAG volatile.Register32 // 0x60 + SET_INVALIDATE_DS volatile.Register32 // 0x64 + QUERY_ERROR volatile.Register32 // 0x68 + QUERY_BUSY volatile.Register32 // 0x6C + _ [16]byte + WR_MESSAGE_MEM [64]volatile.Register8 // 0x80 + RD_RESULT_MEM [32]volatile.Register8 // 0xC0 + _ [16]byte + SET_MESSAGE_PAD volatile.Register32 // 0xF0 + ONE_BLOCK volatile.Register32 // 0xF4 + SOFT_JTAG_CTRL volatile.Register32 // 0xF8 + WR_JTAG volatile.Register32 // 0xFC + _ [252]byte + DATE volatile.Register32 // 0x1FC +} + +// HMAC.SET_START: Process control register 0. +func (o *HMAC_Type) SetSET_START(value uint32) { + volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_START() uint32 { + return volatile.LoadUint32(&o.SET_START.Reg) & 0x1 +} + +// HMAC.SET_PARA_PURPOSE: Configure purpose. +func (o *HMAC_Type) SetSET_PARA_PURPOSE_PURPOSE_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_PURPOSE.Reg, volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg)&^(0xf)|value) +} +func (o *HMAC_Type) GetSET_PARA_PURPOSE_PURPOSE_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg) & 0xf +} + +// HMAC.SET_PARA_KEY: Configure key. +func (o *HMAC_Type) SetSET_PARA_KEY_KEY_SET(value uint32) { + volatile.StoreUint32(&o.SET_PARA_KEY.Reg, volatile.LoadUint32(&o.SET_PARA_KEY.Reg)&^(0x7)|value) +} +func (o *HMAC_Type) GetSET_PARA_KEY_KEY_SET() uint32 { + return volatile.LoadUint32(&o.SET_PARA_KEY.Reg) & 0x7 +} + +// HMAC.SET_PARA_FINISH: Finish initial configuration. +func (o *HMAC_Type) SetSET_PARA_FINISH_SET_PARA_END(value uint32) { + volatile.StoreUint32(&o.SET_PARA_FINISH.Reg, volatile.LoadUint32(&o.SET_PARA_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_PARA_FINISH_SET_PARA_END() uint32 { + return volatile.LoadUint32(&o.SET_PARA_FINISH.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ONE: Process control register 1. +func (o *HMAC_Type) SetSET_MESSAGE_ONE_SET_TEXT_ONE(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ONE.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ONE_SET_TEXT_ONE() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_ING: Process control register 2. +func (o *HMAC_Type) SetSET_MESSAGE_ING_SET_TEXT_ING(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_ING.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_ING_SET_TEXT_ING() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_END: Process control register 3. +func (o *HMAC_Type) SetSET_MESSAGE_END_SET_TEXT_END(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_END.Reg, volatile.LoadUint32(&o.SET_MESSAGE_END.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_END_SET_TEXT_END() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_END.Reg) & 0x1 +} + +// HMAC.SET_RESULT_FINISH: Process control register 4. +func (o *HMAC_Type) SetSET_RESULT_FINISH_SET_RESULT_END(value uint32) { + volatile.StoreUint32(&o.SET_RESULT_FINISH.Reg, volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_RESULT_FINISH_SET_RESULT_END() uint32 { + return volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_JTAG: Invalidate register 0. +func (o *HMAC_Type) SetSET_INVALIDATE_JTAG(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_JTAG.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_JTAG() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg) & 0x1 +} + +// HMAC.SET_INVALIDATE_DS: Invalidate register 1. +func (o *HMAC_Type) SetSET_INVALIDATE_DS(value uint32) { + volatile.StoreUint32(&o.SET_INVALIDATE_DS.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_INVALIDATE_DS() uint32 { + return volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg) & 0x1 +} + +// HMAC.QUERY_ERROR: Error register. +func (o *HMAC_Type) SetQUERY_ERROR_QUERY_CHECK(value uint32) { + volatile.StoreUint32(&o.QUERY_ERROR.Reg, volatile.LoadUint32(&o.QUERY_ERROR.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_ERROR_QUERY_CHECK() uint32 { + return volatile.LoadUint32(&o.QUERY_ERROR.Reg) & 0x1 +} + +// HMAC.QUERY_BUSY: Busy register. +func (o *HMAC_Type) SetQUERY_BUSY_BUSY_STATE(value uint32) { + volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetQUERY_BUSY_BUSY_STATE() uint32 { + return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1 +} + +// HMAC.SET_MESSAGE_PAD: Process control register 5. +func (o *HMAC_Type) SetSET_MESSAGE_PAD_SET_TEXT_PAD(value uint32) { + volatile.StoreUint32(&o.SET_MESSAGE_PAD.Reg, volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSET_MESSAGE_PAD_SET_TEXT_PAD() uint32 { + return volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg) & 0x1 +} + +// HMAC.ONE_BLOCK: Process control register 6. +func (o *HMAC_Type) SetONE_BLOCK_SET_ONE_BLOCK(value uint32) { + volatile.StoreUint32(&o.ONE_BLOCK.Reg, volatile.LoadUint32(&o.ONE_BLOCK.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetONE_BLOCK_SET_ONE_BLOCK() uint32 { + return volatile.LoadUint32(&o.ONE_BLOCK.Reg) & 0x1 +} + +// HMAC.SOFT_JTAG_CTRL: Jtag register 0. +func (o *HMAC_Type) SetSOFT_JTAG_CTRL(value uint32) { + volatile.StoreUint32(&o.SOFT_JTAG_CTRL.Reg, volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg)&^(0x1)|value) +} +func (o *HMAC_Type) GetSOFT_JTAG_CTRL() uint32 { + return volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg) & 0x1 +} + +// HMAC.WR_JTAG: Jtag register 1. +func (o *HMAC_Type) SetWR_JTAG(value uint32) { + volatile.StoreUint32(&o.WR_JTAG.Reg, value) +} +func (o *HMAC_Type) GetWR_JTAG() uint32 { + return volatile.LoadUint32(&o.WR_JTAG.Reg) +} + +// HMAC.DATE: Date register. +func (o *HMAC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *HMAC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// I2C (Inter-Integrated Circuit) Controller 0 +type I2C_Type struct { + SCL_LOW_PERIOD volatile.Register32 // 0x0 + CTR volatile.Register32 // 0x4 + SR volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + FIFO_ST volatile.Register32 // 0x14 + FIFO_CONF volatile.Register32 // 0x18 + DATA volatile.Register32 // 0x1C + INT_RAW volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_ENA volatile.Register32 // 0x28 + INT_STATUS volatile.Register32 // 0x2C + SDA_HOLD volatile.Register32 // 0x30 + SDA_SAMPLE volatile.Register32 // 0x34 + SCL_HIGH_PERIOD volatile.Register32 // 0x38 + _ [4]byte + SCL_START_HOLD volatile.Register32 // 0x40 + SCL_RSTART_SETUP volatile.Register32 // 0x44 + SCL_STOP_HOLD volatile.Register32 // 0x48 + SCL_STOP_SETUP volatile.Register32 // 0x4C + FILTER_CFG volatile.Register32 // 0x50 + CLK_CONF volatile.Register32 // 0x54 + COMD0 volatile.Register32 // 0x58 + COMD1 volatile.Register32 // 0x5C + COMD2 volatile.Register32 // 0x60 + COMD3 volatile.Register32 // 0x64 + COMD4 volatile.Register32 // 0x68 + COMD5 volatile.Register32 // 0x6C + COMD6 volatile.Register32 // 0x70 + COMD7 volatile.Register32 // 0x74 + SCL_ST_TIME_OUT volatile.Register32 // 0x78 + SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C + SCL_SP_CONF volatile.Register32 // 0x80 + SCL_STRETCH_CONF volatile.Register32 // 0x84 + _ [112]byte + DATE volatile.Register32 // 0xF8 + _ [4]byte + TXFIFO_START_ADDR volatile.Register32 // 0x100 + _ [124]byte + RXFIFO_START_ADDR volatile.Register32 // 0x180 +} + +// I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL Clock +func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff +} + +// I2C.CTR: Transmission setting +func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTR.Reg) & 0x1 +} +func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetCTR_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetCTR_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetCTR_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetCTR_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetCTR_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetCTR_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetCTR_ARBITRATION_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetCTR_ARBITRATION_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetCTR_FSM_RST(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetCTR_FSM_RST() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetCTR_CONF_UPGATE(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetCTR_CONF_UPGATE() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetCTR_SLV_TX_AUTO_START_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetCTR_SLV_TX_AUTO_START_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetCTR_ADDR_10BIT_RW_CHECK_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetCTR_ADDR_10BIT_RW_CHECK_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetCTR_ADDR_BROADCASTING_EN(value uint32) { + volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetCTR_ADDR_BROADCASTING_EN() uint32 { + return (volatile.LoadUint32(&o.CTR.Reg) & 0x4000) >> 14 +} + +// I2C.SR: Describe I2C work status. +func (o *I2C_Type) SetSR_RESP_REC(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSR_RESP_REC() uint32 { + return volatile.LoadUint32(&o.SR.Reg) & 0x1 +} +func (o *I2C_Type) SetSR_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetSR_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetSR_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetSR_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetSR_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetSR_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetSR_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetSR_STRETCH_CAUSE(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xc000)|value<<14) +} +func (o *I2C_Type) GetSR_STRETCH_CAUSE() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xc000) >> 14 +} +func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0xfc0000) >> 18 +} +func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24) +} +func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24 +} +func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28) +} +func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28 +} + +// I2C.TO: Setting time out control for receiving data. +func (o *I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetTO_TIME_OUT_VALUE() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0x1f +} +func (o *I2C_Type) SetTO_TIME_OUT_EN(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetTO_TIME_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5 +} + +// I2C.SLAVE_ADDR: Local slave address setting +func (o *I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// I2C.FIFO_ST: FIFO status register. +func (o *I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 { + return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x7c00)|value<<10) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x7c00) >> 10 +} +func (o *I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf8000)|value<<15) +} +func (o *I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf8000) >> 15 +} +func (o *I2C_Type) SetFIFO_ST_SLAVE_RW_POINT(value uint32) { + volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3fc00000)|value<<22) +} +func (o *I2C_Type) GetFIFO_ST_SLAVE_RW_POINT() uint32 { + return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3fc00000) >> 22 +} + +// I2C.FIFO_CONF: FIFO configuration register. +func (o *I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 { + return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1f +} +func (o *I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3e0)|value<<5) +} +func (o *I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3e0) >> 5 +} +func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_ADDR_CFG_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_ADDR_CFG_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) { + volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 { + return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14 +} + +// I2C.DATA: Rx FIFO read data. +func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} + +// I2C.INT_RAW: Raw interrupt status +func (o *I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_RAW_SLAVE_STRETCH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_RAW_SLAVE_STRETCH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_RAW_GENERAL_CALL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_RAW_GENERAL_CALL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} + +// I2C.INT_CLR: Interrupt clear bits +func (o *I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_CLR_SLAVE_STRETCH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_CLR_SLAVE_STRETCH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_CLR_GENERAL_CALL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_CLR_GENERAL_CALL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} + +// I2C.INT_ENA: Interrupt enable bits +func (o *I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_ENA_SLAVE_STRETCH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_ENA_SLAVE_STRETCH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_ENA_GENERAL_CALL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_ENA_GENERAL_CALL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} + +// I2C.INT_STATUS: Status of captured I2C communication events +func (o *I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15 +} +func (o *I2C_Type) SetINT_STATUS_SLAVE_STRETCH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *I2C_Type) GetINT_STATUS_SLAVE_STRETCH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10000) >> 16 +} +func (o *I2C_Type) SetINT_STATUS_GENERAL_CALL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *I2C_Type) GetINT_STATUS_GENERAL_CALL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20000) >> 17 +} + +// I2C.SDA_HOLD: Configures the hold time after a negative SCL edge. +func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff +} + +// I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge. +func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) { + volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 { + return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff +} + +// I2C.SCL_HIGH_PERIOD: Configures the high level width of SCL +func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff +} +func (o *I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9) +} +func (o *I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 { + return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9 +} + +// I2C.SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition +func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA +func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff +} + +// I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff +} + +// I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition +func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value) +} +func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff +} + +// I2C.FILTER_CFG: SCL and SDA filter configuration register +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4 +} +func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8) +} +func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8 +} +func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9) +} +func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9 +} + +// I2C.CLK_CONF: I2C CLK configuration register +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21 +} + +// I2C.COMD0: I2C command register %s +func (o *I2C_Type) SetCOMD0_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD0_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD0_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD0_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD1: I2C command register %s +func (o *I2C_Type) SetCOMD1_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD1_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD1_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD1_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD2: I2C command register %s +func (o *I2C_Type) SetCOMD2_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD2_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD2_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD2_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD3: I2C command register %s +func (o *I2C_Type) SetCOMD3_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD3_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD3_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD3_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD4: I2C command register %s +func (o *I2C_Type) SetCOMD4_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD4_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD4_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD4_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD5: I2C command register %s +func (o *I2C_Type) SetCOMD5_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD5_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD5_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD5_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD6: I2C command register %s +func (o *I2C_Type) SetCOMD6_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD6_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD6_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD6_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31 +} + +// I2C.COMD7: I2C command register %s +func (o *I2C_Type) SetCOMD7_COMMAND(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value) +} +func (o *I2C_Type) GetCOMD7_COMMAND() uint32 { + return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff +} +func (o *I2C_Type) SetCOMD7_COMMAND_DONE(value uint32) { + volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *I2C_Type) GetCOMD7_COMMAND_DONE() uint32 { + return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31 +} + +// I2C.SCL_ST_TIME_OUT: SCL status time out register +func (o *I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register +func (o *I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) { + volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value) +} +func (o *I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 { + return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f +} + +// I2C.SCL_SP_CONF: Power configuration register +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 { + return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1 +} +func (o *I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6 +} +func (o *I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) { + volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7 +} + +// I2C.SCL_STRETCH_CONF: Set SCL stretch of I2C slave +func (o *I2C_Type) SetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x3ff)|value) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM() uint32 { + return volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x3ff +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x400)|value<<10) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x400) >> 10 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x800) >> 11 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL(value uint32) { + volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL() uint32 { + return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x2000) >> 13 +} + +// I2C.DATE: Version register +func (o *I2C_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *I2C_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// I2C.TXFIFO_START_ADDR: I2C TXFIFO base address register +func (o *I2C_Type) SetTXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetTXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg) +} + +// I2C.RXFIFO_START_ADDR: I2C RXFIFO base address register +func (o *I2C_Type) SetRXFIFO_START_ADDR(value uint32) { + volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value) +} +func (o *I2C_Type) GetRXFIFO_START_ADDR() uint32 { + return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg) +} + +// I2S (Inter-IC Sound) Controller 0 +type I2S_Type struct { + _ [12]byte + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + _ [4]byte + RX_CONF volatile.Register32 // 0x20 + TX_CONF volatile.Register32 // 0x24 + RX_CONF1 volatile.Register32 // 0x28 + TX_CONF1 volatile.Register32 // 0x2C + RX_CLKM_CONF volatile.Register32 // 0x30 + TX_CLKM_CONF volatile.Register32 // 0x34 + RX_CLKM_DIV_CONF volatile.Register32 // 0x38 + TX_CLKM_DIV_CONF volatile.Register32 // 0x3C + TX_PCM2PDM_CONF volatile.Register32 // 0x40 + TX_PCM2PDM_CONF1 volatile.Register32 // 0x44 + _ [8]byte + RX_TDM_CTRL volatile.Register32 // 0x50 + TX_TDM_CTRL volatile.Register32 // 0x54 + RX_TIMING volatile.Register32 // 0x58 + TX_TIMING volatile.Register32 // 0x5C + LC_HUNG_CONF volatile.Register32 // 0x60 + RXEOF_NUM volatile.Register32 // 0x64 + CONF_SIGLE_DATA volatile.Register32 // 0x68 + STATE volatile.Register32 // 0x6C + _ [16]byte + DATE volatile.Register32 // 0x80 +} + +// I2S.INT_RAW: I2S interrupt raw register, valid in level. +func (o *I2S_Type) SetINT_RAW_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_RAW_RX_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// I2S.INT_ST: I2S interrupt status register. +func (o *I2S_Type) SetINT_ST_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ST_RX_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// I2S.INT_ENA: I2S interrupt enable register. +func (o *I2S_Type) SetINT_ENA_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_ENA_RX_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// I2S.INT_CLR: I2S interrupt clear register. +func (o *I2S_Type) SetINT_CLR_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetINT_CLR_RX_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2S_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// I2S.RX_CONF: I2S RX configure register +func (o *I2S_Type) SetRX_CONF_RX_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_CONF_RX_RESET() uint32 { + return volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_CONF_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_CONF_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_CONF_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_CONF_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_CONF_RX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_CONF_RX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetRX_CONF_RX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_CONF_RX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_CONF_RX_UPDATE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_CONF_RX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_CONF_RX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_CONF_RX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetRX_CONF_RX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_CONF_RX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_CONF_RX_STOP_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *I2S_Type) GetRX_CONF_RX_STOP_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x6000) >> 13 +} +func (o *I2S_Type) SetRX_CONF_RX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_CONF_RX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_CONF_RX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetRX_CONF_RX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetRX_CONF_RX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetRX_CONF_RX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetRX_CONF_RX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetRX_CONF_RX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetRX_CONF_RX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetRX_CONF_RX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetRX_CONF_RX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetRX_CONF_RX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetRX_CONF_RX_PDM2PCM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetRX_CONF_RX_PDM2PCM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetRX_CONF_RX_PDM_SINC_DSR_16_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *I2S_Type) GetRX_CONF_RX_PDM_SINC_DSR_16_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x400000) >> 22 +} + +// I2S.TX_CONF: I2S TX configure register +func (o *I2S_Type) SetTX_CONF_TX_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_CONF_TX_RESET() uint32 { + return volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_CONF_TX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_CONF_TX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_CONF_TX_START(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_CONF_TX_START() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_CONF_TX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_CONF_TX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_EQUAL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_EQUAL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_CONF_TX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_CONF_TX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_CONF_TX_UPDATE(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_CONF_TX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_CONF_TX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_CONF_TX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetTX_CONF_TX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_CONF_TX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_CONF_TX_STOP_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_CONF_TX_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_CONF_TX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_CONF_TX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_CONF_TX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S_Type) GetTX_CONF_TX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S_Type) SetTX_CONF_TX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S_Type) GetTX_CONF_TX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S_Type) SetTX_CONF_TX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S_Type) GetTX_CONF_TX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S_Type) SetTX_CONF_TX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S_Type) GetTX_CONF_TX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S_Type) SetTX_CONF_TX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_CONF_TX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetTX_CONF_TX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x7000000)|value<<24) +} +func (o *I2S_Type) GetTX_CONF_TX_CHAN_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x7000000) >> 24 +} +func (o *I2S_Type) SetTX_CONF_SIG_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetTX_CONF_SIG_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.RX_CONF1: I2S RX configure register 1 +func (o *I2S_Type) SetRX_CONF1_RX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7f)|value) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7f +} +func (o *I2S_Type) SetRX_CONF1_RX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *I2S_Type) GetRX_CONF1_RX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *I2S_Type) SetRX_CONF1_RX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x3e000)|value<<13) +} +func (o *I2S_Type) GetRX_CONF1_RX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x3e000) >> 13 +} +func (o *I2S_Type) SetRX_CONF1_RX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S_Type) GetRX_CONF1_RX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0xfc0000) >> 18 +} +func (o *I2S_Type) SetRX_CONF1_RX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f000000)|value<<24) +} +func (o *I2S_Type) GetRX_CONF1_RX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f000000) >> 24 +} +func (o *I2S_Type) SetRX_CONF1_RX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetRX_CONF1_RX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x20000000) >> 29 +} + +// I2S.TX_CONF1: I2S TX configure register 1 +func (o *I2S_Type) SetTX_CONF1_TX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7f)|value) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7f +} +func (o *I2S_Type) SetTX_CONF1_TX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *I2S_Type) GetTX_CONF1_TX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *I2S_Type) SetTX_CONF1_TX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x3e000)|value<<13) +} +func (o *I2S_Type) GetTX_CONF1_TX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x3e000) >> 13 +} +func (o *I2S_Type) SetTX_CONF1_TX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S_Type) GetTX_CONF1_TX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0xfc0000) >> 18 +} +func (o *I2S_Type) SetTX_CONF1_TX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1f000000)|value<<24) +} +func (o *I2S_Type) GetTX_CONF1_TX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1f000000) >> 24 +} +func (o *I2S_Type) SetTX_CONF1_TX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetTX_CONF1_TX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x20000000) >> 29 +} +func (o *I2S_Type) SetTX_CONF1_TX_BCK_NO_DLY(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S_Type) GetTX_CONF1_TX_BCK_NO_DLY() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x40000000) >> 30 +} + +// I2S.RX_CLKM_CONF: I2S RX clock configure register +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S_Type) SetRX_CLKM_CONF_RX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S_Type) GetRX_CLKM_CONF_RX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S_Type) SetRX_CLKM_CONF_MCLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetRX_CLKM_CONF_MCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S.TX_CLKM_CONF: I2S TX clock configure register +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S_Type) SetTX_CLKM_CONF_TX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S_Type) GetTX_CLKM_CONF_TX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S_Type) SetTX_CLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S_Type) GetTX_CLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S.RX_CLKM_DIV_CONF: I2S RX module clock divider configure register +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.TX_CLKM_DIV_CONF: I2S TX module clock divider configure register +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S.TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1e)|value<<1) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1e) >> 1 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1fe0)|value<<5) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1fe0) >> 5 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x6000) >> 13 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x18000)|value<<15) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x18000) >> 15 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x60000)|value<<17) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x60000) >> 17 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x180000)|value<<19) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x180000) >> 19 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x400000) >> 22 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x800000) >> 23 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1000000) >> 24 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x2000000) >> 25 +} + +// I2S.TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FP(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3ff)|value) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FP() uint32 { + return volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3ff +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FS(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FS() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x700000)|value<<20) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x700000) >> 20 +} +func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0(value uint32) { + volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3800000)|value<<23) +} +func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0() uint32 { + return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3800000) >> 23 +} + +// I2S.RX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} + +// I2S.TX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} +func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100000) >> 20 +} + +// I2S.RX_TIMING: I2S RX timing control register +func (o *I2S_Type) SetRX_TIMING_RX_SD_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD_IN_DM() uint32 { + return volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetRX_TIMING_RX_SD1_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD1_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetRX_TIMING_RX_SD2_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300)|value<<8) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD2_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300) >> 8 +} +func (o *I2S_Type) SetRX_TIMING_RX_SD3_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000)|value<<12) +} +func (o *I2S_Type) GetRX_TIMING_RX_SD3_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000) >> 12 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetRX_TIMING_RX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetRX_TIMING_RX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetRX_TIMING_RX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetRX_TIMING_RX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.TX_TIMING: I2S TX timing control register +func (o *I2S_Type) SetTX_TIMING_TX_SD_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD_OUT_DM() uint32 { + return volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3 +} +func (o *I2S_Type) SetTX_TIMING_TX_SD1_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetTX_TIMING_TX_SD1_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S_Type) SetTX_TIMING_TX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S_Type) GetTX_TIMING_TX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S_Type) SetTX_TIMING_TX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S_Type) GetTX_TIMING_TX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S.LC_HUNG_CONF: I2S HUNG configure register. +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11 +} + +// I2S.RXEOF_NUM: I2S RX data number control register. +func (o *I2S_Type) SetRXEOF_NUM_RX_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.RXEOF_NUM.Reg, volatile.LoadUint32(&o.RXEOF_NUM.Reg)&^(0xfff)|value) +} +func (o *I2S_Type) GetRXEOF_NUM_RX_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.RXEOF_NUM.Reg) & 0xfff +} + +// I2S.CONF_SIGLE_DATA: I2S signal data register +func (o *I2S_Type) SetCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value) +} +func (o *I2S_Type) GetCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg) +} + +// I2S.STATE: I2S TX status register +func (o *I2S_Type) SetSTATE_TX_IDLE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetSTATE_TX_IDLE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x1 +} + +// I2S.DATE: Version control register +func (o *I2S_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *I2S_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// I2S (Inter-IC Sound) Controller 1 +type I2S1_Type struct { + _ [12]byte + INT_RAW volatile.Register32 // 0xC + INT_ST volatile.Register32 // 0x10 + INT_ENA volatile.Register32 // 0x14 + INT_CLR volatile.Register32 // 0x18 + _ [4]byte + RX_CONF volatile.Register32 // 0x20 + TX_CONF volatile.Register32 // 0x24 + RX_CONF1 volatile.Register32 // 0x28 + TX_CONF1 volatile.Register32 // 0x2C + RX_CLKM_CONF volatile.Register32 // 0x30 + TX_CLKM_CONF volatile.Register32 // 0x34 + RX_CLKM_DIV_CONF volatile.Register32 // 0x38 + TX_CLKM_DIV_CONF volatile.Register32 // 0x3C + _ [16]byte + RX_TDM_CTRL volatile.Register32 // 0x50 + TX_TDM_CTRL volatile.Register32 // 0x54 + RX_TIMING volatile.Register32 // 0x58 + TX_TIMING volatile.Register32 // 0x5C + LC_HUNG_CONF volatile.Register32 // 0x60 + RXEOF_NUM volatile.Register32 // 0x64 + CONF_SIGLE_DATA volatile.Register32 // 0x68 + STATE volatile.Register32 // 0x6C + _ [16]byte + DATE volatile.Register32 // 0x80 +} + +// I2S1.INT_RAW: I2S interrupt raw register, valid in level. +func (o *I2S1_Type) SetINT_RAW_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *I2S1_Type) GetINT_RAW_RX_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *I2S1_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2S1_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2S1_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2S1_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2S1_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2S1_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// I2S1.INT_ST: I2S interrupt status register. +func (o *I2S1_Type) SetINT_ST_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *I2S1_Type) GetINT_ST_RX_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *I2S1_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I2S1_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *I2S1_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I2S1_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *I2S1_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I2S1_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// I2S1.INT_ENA: I2S interrupt enable register. +func (o *I2S1_Type) SetINT_ENA_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *I2S1_Type) GetINT_ENA_RX_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *I2S1_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2S1_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2S1_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2S1_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2S1_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2S1_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// I2S1.INT_CLR: I2S interrupt clear register. +func (o *I2S1_Type) SetINT_CLR_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *I2S1_Type) GetINT_CLR_RX_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *I2S1_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2S1_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2S1_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2S1_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2S1_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2S1_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// I2S1.RX_CONF: I2S RX configure register +func (o *I2S1_Type) SetRX_CONF_RX_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S1_Type) GetRX_CONF_RX_RESET() uint32 { + return volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1 +} +func (o *I2S1_Type) SetRX_CONF_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S1_Type) GetRX_CONF_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S1_Type) SetRX_CONF_RX_START(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S1_Type) GetRX_CONF_RX_START() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S1_Type) SetRX_CONF_RX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S1_Type) GetRX_CONF_RX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S1_Type) SetRX_CONF_RX_MONO(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S1_Type) GetRX_CONF_RX_MONO() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S1_Type) SetRX_CONF_RX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S1_Type) GetRX_CONF_RX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S1_Type) SetRX_CONF_RX_UPDATE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S1_Type) GetRX_CONF_RX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S1_Type) SetRX_CONF_RX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S1_Type) GetRX_CONF_RX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S1_Type) SetRX_CONF_RX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S1_Type) GetRX_CONF_RX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S1_Type) SetRX_CONF_RX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S1_Type) GetRX_CONF_RX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S1_Type) SetRX_CONF_RX_STOP_MODE(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *I2S1_Type) GetRX_CONF_RX_STOP_MODE() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x6000) >> 13 +} +func (o *I2S1_Type) SetRX_CONF_RX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S1_Type) GetRX_CONF_RX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S1_Type) SetRX_CONF_RX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S1_Type) GetRX_CONF_RX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S1_Type) SetRX_CONF_RX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S1_Type) GetRX_CONF_RX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S1_Type) SetRX_CONF_RX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S1_Type) GetRX_CONF_RX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S1_Type) SetRX_CONF_RX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S1_Type) GetRX_CONF_RX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S1_Type) SetRX_CONF_RX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S1_Type) GetRX_CONF_RX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100000) >> 20 +} + +// I2S1.TX_CONF: I2S TX configure register +func (o *I2S1_Type) SetTX_CONF_TX_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1)|value) +} +func (o *I2S1_Type) GetTX_CONF_TX_RESET() uint32 { + return volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1 +} +func (o *I2S1_Type) SetTX_CONF_TX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S1_Type) GetTX_CONF_TX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2) >> 1 +} +func (o *I2S1_Type) SetTX_CONF_TX_START(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S1_Type) GetTX_CONF_TX_START() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4) >> 2 +} +func (o *I2S1_Type) SetTX_CONF_TX_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S1_Type) GetTX_CONF_TX_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8) >> 3 +} +func (o *I2S1_Type) SetTX_CONF_TX_MONO(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S1_Type) GetTX_CONF_TX_MONO() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20) >> 5 +} +func (o *I2S1_Type) SetTX_CONF_TX_CHAN_EQUAL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S1_Type) GetTX_CONF_TX_CHAN_EQUAL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40) >> 6 +} +func (o *I2S1_Type) SetTX_CONF_TX_BIG_ENDIAN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S1_Type) GetTX_CONF_TX_BIG_ENDIAN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80) >> 7 +} +func (o *I2S1_Type) SetTX_CONF_TX_UPDATE(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S1_Type) GetTX_CONF_TX_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100) >> 8 +} +func (o *I2S1_Type) SetTX_CONF_TX_MONO_FST_VLD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S1_Type) GetTX_CONF_TX_MONO_FST_VLD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x200) >> 9 +} +func (o *I2S1_Type) SetTX_CONF_TX_PCM_CONF(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *I2S1_Type) GetTX_CONF_TX_PCM_CONF() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0xc00) >> 10 +} +func (o *I2S1_Type) SetTX_CONF_TX_PCM_BYPASS(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S1_Type) GetTX_CONF_TX_PCM_BYPASS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S1_Type) SetTX_CONF_TX_STOP_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *I2S1_Type) GetTX_CONF_TX_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2000) >> 13 +} +func (o *I2S1_Type) SetTX_CONF_TX_LEFT_ALIGN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *I2S1_Type) GetTX_CONF_TX_LEFT_ALIGN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000) >> 15 +} +func (o *I2S1_Type) SetTX_CONF_TX_24_FILL_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *I2S1_Type) GetTX_CONF_TX_24_FILL_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10000) >> 16 +} +func (o *I2S1_Type) SetTX_CONF_TX_WS_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *I2S1_Type) GetTX_CONF_TX_WS_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20000) >> 17 +} +func (o *I2S1_Type) SetTX_CONF_TX_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *I2S1_Type) GetTX_CONF_TX_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000) >> 18 +} +func (o *I2S1_Type) SetTX_CONF_TX_TDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *I2S1_Type) GetTX_CONF_TX_TDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80000) >> 19 +} +func (o *I2S1_Type) SetTX_CONF_TX_PDM_EN(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *I2S1_Type) GetTX_CONF_TX_PDM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100000) >> 20 +} +func (o *I2S1_Type) SetTX_CONF_TX_CHAN_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x7000000)|value<<24) +} +func (o *I2S1_Type) GetTX_CONF_TX_CHAN_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x7000000) >> 24 +} +func (o *I2S1_Type) SetTX_CONF_SIG_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S1_Type) GetTX_CONF_SIG_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S1.RX_CONF1: I2S RX configure register 1 +func (o *I2S1_Type) SetRX_CONF1_RX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7f)|value) +} +func (o *I2S1_Type) GetRX_CONF1_RX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7f +} +func (o *I2S1_Type) SetRX_CONF1_RX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *I2S1_Type) GetRX_CONF1_RX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *I2S1_Type) SetRX_CONF1_RX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x3e000)|value<<13) +} +func (o *I2S1_Type) GetRX_CONF1_RX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x3e000) >> 13 +} +func (o *I2S1_Type) SetRX_CONF1_RX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S1_Type) GetRX_CONF1_RX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0xfc0000) >> 18 +} +func (o *I2S1_Type) SetRX_CONF1_RX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f000000)|value<<24) +} +func (o *I2S1_Type) GetRX_CONF1_RX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f000000) >> 24 +} +func (o *I2S1_Type) SetRX_CONF1_RX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S1_Type) GetRX_CONF1_RX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x20000000) >> 29 +} + +// I2S1.TX_CONF1: I2S TX configure register 1 +func (o *I2S1_Type) SetTX_CONF1_TX_TDM_WS_WIDTH(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7f)|value) +} +func (o *I2S1_Type) GetTX_CONF1_TX_TDM_WS_WIDTH() uint32 { + return volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7f +} +func (o *I2S1_Type) SetTX_CONF1_TX_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1f80)|value<<7) +} +func (o *I2S1_Type) GetTX_CONF1_TX_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1f80) >> 7 +} +func (o *I2S1_Type) SetTX_CONF1_TX_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x3e000)|value<<13) +} +func (o *I2S1_Type) GetTX_CONF1_TX_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x3e000) >> 13 +} +func (o *I2S1_Type) SetTX_CONF1_TX_HALF_SAMPLE_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0xfc0000)|value<<18) +} +func (o *I2S1_Type) GetTX_CONF1_TX_HALF_SAMPLE_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0xfc0000) >> 18 +} +func (o *I2S1_Type) SetTX_CONF1_TX_TDM_CHAN_BITS(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1f000000)|value<<24) +} +func (o *I2S1_Type) GetTX_CONF1_TX_TDM_CHAN_BITS() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1f000000) >> 24 +} +func (o *I2S1_Type) SetTX_CONF1_TX_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S1_Type) GetTX_CONF1_TX_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x20000000) >> 29 +} +func (o *I2S1_Type) SetTX_CONF1_TX_BCK_NO_DLY(value uint32) { + volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *I2S1_Type) GetTX_CONF1_TX_BCK_NO_DLY() uint32 { + return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x40000000) >> 30 +} + +// I2S1.RX_CLKM_CONF: I2S RX clock configure register +func (o *I2S1_Type) SetRX_CLKM_CONF_RX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S1_Type) GetRX_CLKM_CONF_RX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S1_Type) SetRX_CLKM_CONF_RX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S1_Type) GetRX_CLKM_CONF_RX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S1_Type) SetRX_CLKM_CONF_RX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S1_Type) GetRX_CLKM_CONF_RX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S1_Type) SetRX_CLKM_CONF_MCLK_SEL(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S1_Type) GetRX_CLKM_CONF_MCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S1.TX_CLKM_CONF: I2S TX clock configure register +func (o *I2S1_Type) SetTX_CLKM_CONF_TX_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0xff)|value) +} +func (o *I2S1_Type) GetTX_CLKM_CONF_TX_CLKM_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0xff +} +func (o *I2S1_Type) SetTX_CLKM_CONF_TX_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *I2S1_Type) GetTX_CLKM_CONF_TX_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x4000000) >> 26 +} +func (o *I2S1_Type) SetTX_CLKM_CONF_TX_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *I2S1_Type) GetTX_CLKM_CONF_TX_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x18000000) >> 27 +} +func (o *I2S1_Type) SetTX_CLKM_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *I2S1_Type) GetTX_CLKM_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_CONF.Reg) & 0x20000000) >> 29 +} + +// I2S1.RX_CLKM_DIV_CONF: I2S RX module clock divider configure register +func (o *I2S1_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S1_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S1_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S1_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S1_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S1_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S1_Type) SetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.RX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S1_Type) GetRX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.RX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S1.TX_CLKM_DIV_CONF: I2S TX module clock divider configure register +func (o *I2S1_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x1ff)|value) +} +func (o *I2S1_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Z() uint32 { + return volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x1ff +} +func (o *I2S1_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x3fe00)|value<<9) +} +func (o *I2S1_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_Y() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x3fe00) >> 9 +} +func (o *I2S1_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x7fc0000)|value<<18) +} +func (o *I2S1_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_X() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x7fc0000) >> 18 +} +func (o *I2S1_Type) SetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1(value uint32) { + volatile.StoreUint32(&o.TX_CLKM_DIV_CONF.Reg, volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *I2S1_Type) GetTX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1() uint32 { + return (volatile.LoadUint32(&o.TX_CLKM_DIV_CONF.Reg) & 0x8000000) >> 27 +} + +// I2S1.RX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S1_Type) SetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S1_Type) GetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} + +// I2S1.TX_TDM_CTRL: I2S TX TDM mode control register +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN0_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1)|value) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN0_EN() uint32 { + return volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN1_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN1_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2) >> 1 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN2_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN2_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4) >> 2 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN3_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8)|value<<3) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN3_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8) >> 3 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN4_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN4_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x10) >> 4 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN5_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN5_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x20) >> 5 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN6_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN6_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x40) >> 6 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN7_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN7_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x80) >> 7 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN8_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN8_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100) >> 8 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN9_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN9_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x200) >> 9 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN10_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x400)|value<<10) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN10_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x400) >> 10 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN11_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x800)|value<<11) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN11_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x800) >> 11 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN12_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN12_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1000) >> 12 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN13_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN13_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2000) >> 13 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN14_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN14_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4000) >> 14 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_CHAN15_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_CHAN15_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8000) >> 15 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0xf0000)|value<<16) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0xf0000) >> 16 +} +func (o *I2S1_Type) SetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN(value uint32) { + volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *I2S1_Type) GetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100000) >> 20 +} + +// I2S1.RX_TIMING: I2S RX timing control register +func (o *I2S1_Type) SetRX_TIMING_RX_SD_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S1_Type) GetRX_TIMING_RX_SD_IN_DM() uint32 { + return volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3 +} +func (o *I2S1_Type) SetRX_TIMING_RX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S1_Type) GetRX_TIMING_RX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S1_Type) SetRX_TIMING_RX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S1_Type) GetRX_TIMING_RX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S1_Type) SetRX_TIMING_RX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S1_Type) GetRX_TIMING_RX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S1_Type) SetRX_TIMING_RX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S1_Type) GetRX_TIMING_RX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S1.TX_TIMING: I2S TX timing control register +func (o *I2S1_Type) SetTX_TIMING_TX_SD_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3)|value) +} +func (o *I2S1_Type) GetTX_TIMING_TX_SD_OUT_DM() uint32 { + return volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3 +} +func (o *I2S1_Type) SetTX_TIMING_TX_SD1_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S1_Type) GetTX_TIMING_TX_SD1_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30) >> 4 +} +func (o *I2S1_Type) SetTX_TIMING_TX_WS_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S1_Type) GetTX_TIMING_TX_WS_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S1_Type) SetTX_TIMING_TX_BCK_OUT_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x300000)|value<<20) +} +func (o *I2S1_Type) GetTX_TIMING_TX_BCK_OUT_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x300000) >> 20 +} +func (o *I2S1_Type) SetTX_TIMING_TX_WS_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3000000)|value<<24) +} +func (o *I2S1_Type) GetTX_TIMING_TX_WS_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3000000) >> 24 +} +func (o *I2S1_Type) SetTX_TIMING_TX_BCK_IN_DM(value uint32) { + volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000000)|value<<28) +} +func (o *I2S1_Type) GetTX_TIMING_TX_BCK_IN_DM() uint32 { + return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000000) >> 28 +} + +// I2S1.LC_HUNG_CONF: I2S HUNG configure register. +func (o *I2S1_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *I2S1_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff +} +func (o *I2S1_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *I2S1_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *I2S1_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S1_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11 +} + +// I2S1.RXEOF_NUM: I2S RX data number control register. +func (o *I2S1_Type) SetRXEOF_NUM_RX_EOF_NUM(value uint32) { + volatile.StoreUint32(&o.RXEOF_NUM.Reg, volatile.LoadUint32(&o.RXEOF_NUM.Reg)&^(0xfff)|value) +} +func (o *I2S1_Type) GetRXEOF_NUM_RX_EOF_NUM() uint32 { + return volatile.LoadUint32(&o.RXEOF_NUM.Reg) & 0xfff +} + +// I2S1.CONF_SIGLE_DATA: I2S signal data register +func (o *I2S1_Type) SetCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value) +} +func (o *I2S1_Type) GetCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg) +} + +// I2S1.STATE: I2S TX status register +func (o *I2S1_Type) SetSTATE_TX_IDLE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x1)|value) +} +func (o *I2S1_Type) GetSTATE_TX_IDLE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x1 +} + +// I2S1.DATE: Version control register +func (o *I2S1_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *I2S1_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Interrupt Controller (Core 0) +type INTERRUPT_CORE0_Type struct { + PRO_MAC_INTR_MAP volatile.Register32 // 0x0 + MAC_NMI_MAP volatile.Register32 // 0x4 + PWR_INTR_MAP volatile.Register32 // 0x8 + BB_INT_MAP volatile.Register32 // 0xC + BT_MAC_INT_MAP volatile.Register32 // 0x10 + BT_BB_INT_MAP volatile.Register32 // 0x14 + BT_BB_NMI_MAP volatile.Register32 // 0x18 + RWBT_IRQ_MAP volatile.Register32 // 0x1C + RWBLE_IRQ_MAP volatile.Register32 // 0x20 + RWBT_NMI_MAP volatile.Register32 // 0x24 + RWBLE_NMI_MAP volatile.Register32 // 0x28 + I2C_MST_INT_MAP volatile.Register32 // 0x2C + SLC0_INTR_MAP volatile.Register32 // 0x30 + SLC1_INTR_MAP volatile.Register32 // 0x34 + UHCI0_INTR_MAP volatile.Register32 // 0x38 + UHCI1_INTR_MAP volatile.Register32 // 0x3C + GPIO_INTERRUPT_PRO_MAP volatile.Register32 // 0x40 + GPIO_INTERRUPT_PRO_NMI_MAP volatile.Register32 // 0x44 + GPIO_INTERRUPT_APP_MAP volatile.Register32 // 0x48 + GPIO_INTERRUPT_APP_NMI_MAP volatile.Register32 // 0x4C + SPI_INTR_1_MAP volatile.Register32 // 0x50 + SPI_INTR_2_MAP volatile.Register32 // 0x54 + SPI_INTR_3_MAP volatile.Register32 // 0x58 + SPI_INTR_4_MAP volatile.Register32 // 0x5C + LCD_CAM_INT_MAP volatile.Register32 // 0x60 + I2S0_INT_MAP volatile.Register32 // 0x64 + I2S1_INT_MAP volatile.Register32 // 0x68 + UART_INTR_MAP volatile.Register32 // 0x6C + UART1_INTR_MAP volatile.Register32 // 0x70 + UART2_INTR_MAP volatile.Register32 // 0x74 + SDIO_HOST_INTERRUPT_MAP volatile.Register32 // 0x78 + PWM0_INTR_MAP volatile.Register32 // 0x7C + PWM1_INTR_MAP volatile.Register32 // 0x80 + PWM2_INTR_MAP volatile.Register32 // 0x84 + PWM3_INTR_MAP volatile.Register32 // 0x88 + LEDC_INT_MAP volatile.Register32 // 0x8C + EFUSE_INT_MAP volatile.Register32 // 0x90 + CAN_INT_MAP volatile.Register32 // 0x94 + USB_INTR_MAP volatile.Register32 // 0x98 + RTC_CORE_INTR_MAP volatile.Register32 // 0x9C + RMT_INTR_MAP volatile.Register32 // 0xA0 + PCNT_INTR_MAP volatile.Register32 // 0xA4 + I2C_EXT0_INTR_MAP volatile.Register32 // 0xA8 + I2C_EXT1_INTR_MAP volatile.Register32 // 0xAC + SPI2_DMA_INT_MAP volatile.Register32 // 0xB0 + SPI3_DMA_INT_MAP volatile.Register32 // 0xB4 + SPI4_DMA_INT_MAP volatile.Register32 // 0xB8 + WDG_INT_MAP volatile.Register32 // 0xBC + TIMER_INT1_MAP volatile.Register32 // 0xC0 + TIMER_INT2_MAP volatile.Register32 // 0xC4 + TG_T0_INT_MAP volatile.Register32 // 0xC8 + TG_T1_INT_MAP volatile.Register32 // 0xCC + TG_WDT_INT_MAP volatile.Register32 // 0xD0 + TG1_T0_INT_MAP volatile.Register32 // 0xD4 + TG1_T1_INT_MAP volatile.Register32 // 0xD8 + TG1_WDT_INT_MAP volatile.Register32 // 0xDC + CACHE_IA_INT_MAP volatile.Register32 // 0xE0 + SYSTIMER_TARGET0_INT_MAP volatile.Register32 // 0xE4 + SYSTIMER_TARGET1_INT_MAP volatile.Register32 // 0xE8 + SYSTIMER_TARGET2_INT_MAP volatile.Register32 // 0xEC + SPI_MEM_REJECT_INTR_MAP volatile.Register32 // 0xF0 + DCACHE_PRELOAD_INT_MAP volatile.Register32 // 0xF4 + ICACHE_PRELOAD_INT_MAP volatile.Register32 // 0xF8 + DCACHE_SYNC_INT_MAP volatile.Register32 // 0xFC + ICACHE_SYNC_INT_MAP volatile.Register32 // 0x100 + APB_ADC_INT_MAP volatile.Register32 // 0x104 + DMA_IN_CH0_INT_MAP volatile.Register32 // 0x108 + DMA_IN_CH1_INT_MAP volatile.Register32 // 0x10C + DMA_IN_CH2_INT_MAP volatile.Register32 // 0x110 + DMA_IN_CH3_INT_MAP volatile.Register32 // 0x114 + DMA_IN_CH4_INT_MAP volatile.Register32 // 0x118 + DMA_OUT_CH0_INT_MAP volatile.Register32 // 0x11C + DMA_OUT_CH1_INT_MAP volatile.Register32 // 0x120 + DMA_OUT_CH2_INT_MAP volatile.Register32 // 0x124 + DMA_OUT_CH3_INT_MAP volatile.Register32 // 0x128 + DMA_OUT_CH4_INT_MAP volatile.Register32 // 0x12C + RSA_INT_MAP volatile.Register32 // 0x130 + AES_INT_MAP volatile.Register32 // 0x134 + SHA_INT_MAP volatile.Register32 // 0x138 + CPU_INTR_FROM_CPU_0_MAP volatile.Register32 // 0x13C + CPU_INTR_FROM_CPU_1_MAP volatile.Register32 // 0x140 + CPU_INTR_FROM_CPU_2_MAP volatile.Register32 // 0x144 + CPU_INTR_FROM_CPU_3_MAP volatile.Register32 // 0x148 + ASSIST_DEBUG_INTR_MAP volatile.Register32 // 0x14C + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x150 + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x154 + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x158 + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x15C + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP volatile.Register32 // 0x160 + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x164 + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x168 + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x16C + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP volatile.Register32 // 0x170 + BACKUP_PMS_VIOLATE_INTR_MAP volatile.Register32 // 0x174 + CACHE_CORE0_ACS_INT_MAP volatile.Register32 // 0x178 + CACHE_CORE1_ACS_INT_MAP volatile.Register32 // 0x17C + USB_DEVICE_INT_MAP volatile.Register32 // 0x180 + PERI_BACKUP_INT_MAP volatile.Register32 // 0x184 + DMA_EXTMEM_REJECT_INT_MAP volatile.Register32 // 0x188 + PRO_INTR_STATUS_0 volatile.Register32 // 0x18C + PRO_INTR_STATUS_1 volatile.Register32 // 0x190 + PRO_INTR_STATUS_2 volatile.Register32 // 0x194 + PRO_INTR_STATUS_3 volatile.Register32 // 0x198 + CLOCK_GATE volatile.Register32 // 0x19C + _ [1628]byte + DATE volatile.Register32 // 0x7FC +} + +// INTERRUPT_CORE0.PRO_MAC_INTR_MAP: mac interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPRO_MAC_INTR_MAP_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PRO_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.PRO_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_MAC_INTR_MAP_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PRO_MAC_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.MAC_NMI_MAP: mac_nmi interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetMAC_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.MAC_NMI_MAP.Reg, volatile.LoadUint32(&o.MAC_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetMAC_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.MAC_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PWR_INTR_MAP: pwr interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPWR_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWR_INTR_MAP.Reg, volatile.LoadUint32(&o.PWR_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPWR_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWR_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BB_INT_MAP: bb interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetBB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BB_INT_MAP.Reg, volatile.LoadUint32(&o.BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BT_MAC_INT_MAP: bb_mac interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetBT_MAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BT_MAC_INT_MAP.Reg, volatile.LoadUint32(&o.BT_MAC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBT_MAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BT_MAC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BT_BB_INT_MAP: bt_bb interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetBT_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_INT_MAP.Reg, volatile.LoadUint32(&o.BT_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBT_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BT_BB_NMI_MAP: bt_bb_nmi interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetBT_BB_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_NMI_MAP.Reg, volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBT_BB_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RWBT_IRQ_MAP: rwbt_irq interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetRWBT_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.RWBT_IRQ_MAP.Reg, volatile.LoadUint32(&o.RWBT_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRWBT_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.RWBT_IRQ_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RWBLE_IRQ_MAP: rwble_irq interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetRWBLE_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.RWBLE_IRQ_MAP.Reg, volatile.LoadUint32(&o.RWBLE_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRWBLE_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.RWBLE_IRQ_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RWBT_NMI_MAP: rwbt_nmi interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetRWBT_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.RWBT_NMI_MAP.Reg, volatile.LoadUint32(&o.RWBT_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRWBT_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.RWBT_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RWBLE_NMI_MAP: rwble_nmi interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetRWBLE_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.RWBLE_NMI_MAP.Reg, volatile.LoadUint32(&o.RWBLE_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRWBLE_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.RWBLE_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2C_MST_INT_MAP: i2c_mst interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetI2C_MST_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_MST_INT_MAP.Reg, volatile.LoadUint32(&o.I2C_MST_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2C_MST_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_MST_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SLC0_INTR_MAP: slc0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSLC0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SLC0_INTR_MAP.Reg, volatile.LoadUint32(&o.SLC0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSLC0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SLC0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SLC1_INTR_MAP: slc1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSLC1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SLC1_INTR_MAP.Reg, volatile.LoadUint32(&o.SLC1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSLC1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SLC1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UHCI0_INTR_MAP: uhci0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetUHCI0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UHCI0_INTR_MAP.Reg, volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUHCI0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UHCI1_INTR_MAP: uhci1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetUHCI1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UHCI1_INTR_MAP.Reg, volatile.LoadUint32(&o.UHCI1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUHCI1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UHCI1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.GPIO_INTERRUPT_PRO_MAP: gpio_interrupt_pro interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetGPIO_INTERRUPT_PRO_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetGPIO_INTERRUPT_PRO_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.GPIO_INTERRUPT_PRO_NMI_MAP: gpio_interrupt_pro_nmi interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetGPIO_INTERRUPT_PRO_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetGPIO_INTERRUPT_PRO_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.GPIO_INTERRUPT_APP_MAP: gpio_interrupt_app interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetGPIO_INTERRUPT_APP_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_APP_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_APP_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetGPIO_INTERRUPT_APP_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_APP_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.GPIO_INTERRUPT_APP_NMI_MAP: gpio_interrupt_app_nmi interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetGPIO_INTERRUPT_APP_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_APP_NMI_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_APP_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetGPIO_INTERRUPT_APP_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_APP_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_INTR_1_MAP: spi_intr_1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSPI_INTR_1_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_1_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_INTR_1_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_INTR_2_MAP: spi_intr_2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSPI_INTR_2_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_2_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_INTR_2_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_INTR_3_MAP: spi_intr_3 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSPI_INTR_3_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_3_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_INTR_3_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_3_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_INTR_4_MAP: spi_intr_4 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSPI_INTR_4_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_4_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_4_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_INTR_4_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_4_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.LCD_CAM_INT_MAP: lcd_cam interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetLCD_CAM_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LCD_CAM_INT_MAP.Reg, volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetLCD_CAM_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2S0_INT_MAP: i2s0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetI2S0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S0_INT_MAP.Reg, volatile.LoadUint32(&o.I2S0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2S0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2S1_INT_MAP: i2s1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetI2S1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.I2S1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2S1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UART_INTR_MAP: uart interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetUART_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART_INTR_MAP.Reg, volatile.LoadUint32(&o.UART_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUART_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UART1_INTR_MAP: uart1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetUART1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART1_INTR_MAP.Reg, volatile.LoadUint32(&o.UART1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUART1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.UART2_INTR_MAP: uart2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetUART2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART2_INTR_MAP.Reg, volatile.LoadUint32(&o.UART2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUART2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART2_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SDIO_HOST_INTERRUPT_MAP: sdio_host interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSDIO_HOST_INTERRUPT_MAP(value uint32) { + volatile.StoreUint32(&o.SDIO_HOST_INTERRUPT_MAP.Reg, volatile.LoadUint32(&o.SDIO_HOST_INTERRUPT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSDIO_HOST_INTERRUPT_MAP() uint32 { + return volatile.LoadUint32(&o.SDIO_HOST_INTERRUPT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PWM0_INTR_MAP: pwm0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPWM0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM0_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPWM0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PWM1_INTR_MAP: pwm1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPWM1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM1_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPWM1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PWM2_INTR_MAP: pwm2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPWM2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM2_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPWM2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM2_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PWM3_INTR_MAP: pwm3 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPWM3_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM3_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM3_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPWM3_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM3_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.LEDC_INT_MAP: ledc interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetLEDC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.LEDC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetLEDC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LEDC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.EFUSE_INT_MAP: efuse interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetEFUSE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.EFUSE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetEFUSE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.EFUSE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CAN_INT_MAP: can interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCAN_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CAN_INT_MAP.Reg, volatile.LoadUint32(&o.CAN_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCAN_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CAN_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.USB_INTR_MAP: usb interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetUSB_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.USB_INTR_MAP.Reg, volatile.LoadUint32(&o.USB_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUSB_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.USB_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RTC_CORE_INTR_MAP: rtc_core interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetRTC_CORE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RTC_CORE_INTR_MAP.Reg, volatile.LoadUint32(&o.RTC_CORE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRTC_CORE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RTC_CORE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RMT_INTR_MAP: rmt interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetRMT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RMT_INTR_MAP.Reg, volatile.LoadUint32(&o.RMT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRMT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RMT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PCNT_INTR_MAP: pcnt interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPCNT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PCNT_INTR_MAP.Reg, volatile.LoadUint32(&o.PCNT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPCNT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PCNT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2C_EXT0_INTR_MAP: i2c_ext0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetI2C_EXT0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_EXT0_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2C_EXT0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.I2C_EXT1_INTR_MAP: i2c_ext1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetI2C_EXT1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_EXT1_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_EXT1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetI2C_EXT1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_EXT1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI2_DMA_INT_MAP: spi2_dma interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSPI2_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI2_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.SPI2_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI2_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI2_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI3_DMA_INT_MAP: spi3_dma interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSPI3_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI3_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.SPI3_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI3_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI3_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI4_DMA_INT_MAP: spi4_dma interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSPI4_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI4_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.SPI4_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI4_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI4_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.WDG_INT_MAP: wdg interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetWDG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.WDG_INT_MAP.Reg, volatile.LoadUint32(&o.WDG_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetWDG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.WDG_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TIMER_INT1_MAP: timer_int1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetTIMER_INT1_MAP(value uint32) { + volatile.StoreUint32(&o.TIMER_INT1_MAP.Reg, volatile.LoadUint32(&o.TIMER_INT1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTIMER_INT1_MAP() uint32 { + return volatile.LoadUint32(&o.TIMER_INT1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TIMER_INT2_MAP: timer_int2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetTIMER_INT2_MAP(value uint32) { + volatile.StoreUint32(&o.TIMER_INT2_MAP.Reg, volatile.LoadUint32(&o.TIMER_INT2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTIMER_INT2_MAP() uint32 { + return volatile.LoadUint32(&o.TIMER_INT2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG_T0_INT_MAP: tg_t0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetTG_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TG_T0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_T0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG_T1_INT_MAP: tg_t1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetTG_T1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TG_T1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG_T1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_T1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG_WDT_INT_MAP: tg_wdt interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetTG_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TG_WDT_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_WDT_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG1_T0_INT_MAP: tg1_t0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetTG1_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TG1_T0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG1_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_T0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG1_T1_INT_MAP: tg1_t1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetTG1_T1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TG1_T1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG1_T1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_T1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.TG1_WDT_INT_MAP: tg1_wdt interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetTG1_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TG1_WDT_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetTG1_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_WDT_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CACHE_IA_INT_MAP: cache_ia interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCACHE_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCACHE_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_IA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SYSTIMER_TARGET0_INT_MAP: systimer_target0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSYSTIMER_TARGET0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSYSTIMER_TARGET0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SYSTIMER_TARGET1_INT_MAP: systimer_target1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSYSTIMER_TARGET1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSYSTIMER_TARGET1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SYSTIMER_TARGET2_INT_MAP: systimer_target2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSYSTIMER_TARGET2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSYSTIMER_TARGET2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SPI_MEM_REJECT_INTR_MAP: spi_mem_reject interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSPI_MEM_REJECT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg, volatile.LoadUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSPI_MEM_REJECT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DCACHE_PRELOAD_INT_MAP: dcache_prelaod interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDCACHE_PRELOAD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOAD_INT_MAP.Reg, volatile.LoadUint32(&o.DCACHE_PRELOAD_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDCACHE_PRELOAD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DCACHE_PRELOAD_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ICACHE_PRELOAD_INT_MAP: icache_preload interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetICACHE_PRELOAD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetICACHE_PRELOAD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DCACHE_SYNC_INT_MAP: dcache_sync interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDCACHE_SYNC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DCACHE_SYNC_INT_MAP.Reg, volatile.LoadUint32(&o.DCACHE_SYNC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDCACHE_SYNC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DCACHE_SYNC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ICACHE_SYNC_INT_MAP: icache_sync interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetICACHE_SYNC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_INT_MAP.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetICACHE_SYNC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.APB_ADC_INT_MAP: apb_adc interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetAPB_ADC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APB_ADC_INT_MAP.Reg, volatile.LoadUint32(&o.APB_ADC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetAPB_ADC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APB_ADC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_IN_CH0_INT_MAP: dma_in_ch0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_IN_CH1_INT_MAP: dma_in_ch1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_IN_CH2_INT_MAP: dma_in_ch2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_IN_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_IN_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_IN_CH3_INT_MAP: dma_in_ch3 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_IN_CH3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH3_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_IN_CH3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH3_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_IN_CH4_INT_MAP: dma_in_ch4 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_IN_CH4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH4_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_IN_CH4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH4_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_OUT_CH0_INT_MAP: dma_out_ch0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_OUT_CH1_INT_MAP: dma_out_ch1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_OUT_CH2_INT_MAP: dma_out_ch2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_OUT_CH3_INT_MAP: dma_out_ch3 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_OUT_CH3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH3_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_OUT_CH3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH3_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_OUT_CH4_INT_MAP: dma_out_ch4 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_OUT_CH4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH4_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_OUT_CH4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH4_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.RSA_INT_MAP: rsa interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetRSA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.RSA_INT_MAP.Reg, volatile.LoadUint32(&o.RSA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetRSA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.RSA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.AES_INT_MAP: aes interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetAES_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AES_INT_MAP.Reg, volatile.LoadUint32(&o.AES_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetAES_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AES_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.SHA_INT_MAP: sha interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetSHA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SHA_INT_MAP.Reg, volatile.LoadUint32(&o.SHA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetSHA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SHA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_0_MAP: cpu_intr_from_cpu_0 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_1_MAP: cpu_intr_from_cpu_1 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_2_MAP: cpu_intr_from_cpu_2 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CPU_INTR_FROM_CPU_3_MAP: cpu_intr_from_cpu_3 interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCPU_INTR_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCPU_INTR_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.ASSIST_DEBUG_INTR_MAP: assist_debug interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetASSIST_DEBUG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetASSIST_DEBUG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: dma_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core0_IRam0_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core0_DRam0_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: core0_PIF_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: core0_PIF_pms_monitor_violatile_size interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core1_IRam0_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core1_DRam0_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: core1_PIF_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: core1_PIF_pms_monitor_violatile_size interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.BACKUP_PMS_VIOLATE_INTR_MAP: backup_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetBACKUP_PMS_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BACKUP_PMS_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.BACKUP_PMS_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetBACKUP_PMS_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BACKUP_PMS_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CACHE_CORE0_ACS_INT_MAP: cache_core0_acs interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCACHE_CORE0_ACS_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCACHE_CORE0_ACS_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.CACHE_CORE1_ACS_INT_MAP: cache_core1_acs interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetCACHE_CORE1_ACS_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_CORE1_ACS_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_CORE1_ACS_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCACHE_CORE1_ACS_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_CORE1_ACS_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.USB_DEVICE_INT_MAP: usb_device interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetUSB_DEVICE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_DEVICE_INT_MAP.Reg, volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetUSB_DEVICE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PERI_BACKUP_INT_MAP: peri_backup interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetPERI_BACKUP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_MAP.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetPERI_BACKUP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.DMA_EXTMEM_REJECT_INT_MAP: dma_extmem_reject interrupt configuration register +func (o *INTERRUPT_CORE0_Type) SetDMA_EXTMEM_REJECT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_EXTMEM_REJECT_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_EXTMEM_REJECT_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDMA_EXTMEM_REJECT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_EXTMEM_REJECT_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE0.PRO_INTR_STATUS_0: interrupt status register +func (o *INTERRUPT_CORE0_Type) SetPRO_INTR_STATUS_0(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_0.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_INTR_STATUS_0() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_0.Reg) +} + +// INTERRUPT_CORE0.PRO_INTR_STATUS_1: interrupt status register +func (o *INTERRUPT_CORE0_Type) SetPRO_INTR_STATUS_1(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_1.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_INTR_STATUS_1() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_1.Reg) +} + +// INTERRUPT_CORE0.PRO_INTR_STATUS_2: interrupt status register +func (o *INTERRUPT_CORE0_Type) SetPRO_INTR_STATUS_2(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_2.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_INTR_STATUS_2() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_2.Reg) +} + +// INTERRUPT_CORE0.PRO_INTR_STATUS_3: interrupt status register +func (o *INTERRUPT_CORE0_Type) SetPRO_INTR_STATUS_3(value uint32) { + volatile.StoreUint32(&o.PRO_INTR_STATUS_3.Reg, value) +} +func (o *INTERRUPT_CORE0_Type) GetPRO_INTR_STATUS_3() uint32 { + return volatile.LoadUint32(&o.PRO_INTR_STATUS_3.Reg) +} + +// INTERRUPT_CORE0.CLOCK_GATE: clock gate register +func (o *INTERRUPT_CORE0_Type) SetCLOCK_GATE_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *INTERRUPT_CORE0_Type) GetCLOCK_GATE_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// INTERRUPT_CORE0.DATE: version register +func (o *INTERRUPT_CORE0_Type) SetDATE_INTERRUPT_REG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *INTERRUPT_CORE0_Type) GetDATE_INTERRUPT_REG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Interrupt Controller (Core 1) +type INTERRUPT_CORE1_Type struct { + _ [2048]byte + APP_MAC_INTR_MAP volatile.Register32 // 0x800 + MAC_NMI_MAP volatile.Register32 // 0x804 + PWR_INTR_MAP volatile.Register32 // 0x808 + BB_INT_MAP volatile.Register32 // 0x80C + BT_MAC_INT_MAP volatile.Register32 // 0x810 + BT_BB_INT_MAP volatile.Register32 // 0x814 + BT_BB_NMI_MAP volatile.Register32 // 0x818 + RWBT_IRQ_MAP volatile.Register32 // 0x81C + RWBLE_IRQ_MAP volatile.Register32 // 0x820 + RWBT_NMI_MAP volatile.Register32 // 0x824 + RWBLE_NMI_MAP volatile.Register32 // 0x828 + I2C_MST_INT_MAP volatile.Register32 // 0x82C + SLC0_INTR_MAP volatile.Register32 // 0x830 + SLC1_INTR_MAP volatile.Register32 // 0x834 + UHCI0_INTR_MAP volatile.Register32 // 0x838 + UHCI1_INTR_MAP volatile.Register32 // 0x83C + GPIO_INTERRUPT_PRO_MAP volatile.Register32 // 0x840 + GPIO_INTERRUPT_PRO_NMI_MAP volatile.Register32 // 0x844 + GPIO_INTERRUPT_APP_MAP volatile.Register32 // 0x848 + GPIO_INTERRUPT_APP_NMI_MAP volatile.Register32 // 0x84C + SPI_INTR_1_MAP volatile.Register32 // 0x850 + SPI_INTR_2_MAP volatile.Register32 // 0x854 + SPI_INTR_3_MAP volatile.Register32 // 0x858 + SPI_INTR_4_MAP volatile.Register32 // 0x85C + LCD_CAM_INT_MAP volatile.Register32 // 0x860 + I2S0_INT_MAP volatile.Register32 // 0x864 + I2S1_INT_MAP volatile.Register32 // 0x868 + UART_INTR_MAP volatile.Register32 // 0x86C + UART1_INTR_MAP volatile.Register32 // 0x870 + UART2_INTR_MAP volatile.Register32 // 0x874 + SDIO_HOST_INTERRUPT_MAP volatile.Register32 // 0x878 + PWM0_INTR_MAP volatile.Register32 // 0x87C + PWM1_INTR_MAP volatile.Register32 // 0x880 + PWM2_INTR_MAP volatile.Register32 // 0x884 + PWM3_INTR_MAP volatile.Register32 // 0x888 + LEDC_INT_MAP volatile.Register32 // 0x88C + EFUSE_INT_MAP volatile.Register32 // 0x890 + CAN_INT_MAP volatile.Register32 // 0x894 + USB_INTR_MAP volatile.Register32 // 0x898 + RTC_CORE_INTR_MAP volatile.Register32 // 0x89C + RMT_INTR_MAP volatile.Register32 // 0x8A0 + PCNT_INTR_MAP volatile.Register32 // 0x8A4 + I2C_EXT0_INTR_MAP volatile.Register32 // 0x8A8 + I2C_EXT1_INTR_MAP volatile.Register32 // 0x8AC + SPI2_DMA_INT_MAP volatile.Register32 // 0x8B0 + SPI3_DMA_INT_MAP volatile.Register32 // 0x8B4 + SPI4_DMA_INT_MAP volatile.Register32 // 0x8B8 + WDG_INT_MAP volatile.Register32 // 0x8BC + TIMER_INT1_MAP volatile.Register32 // 0x8C0 + TIMER_INT2_MAP volatile.Register32 // 0x8C4 + TG_T0_INT_MAP volatile.Register32 // 0x8C8 + TG_T1_INT_MAP volatile.Register32 // 0x8CC + TG_WDT_INT_MAP volatile.Register32 // 0x8D0 + TG1_T0_INT_MAP volatile.Register32 // 0x8D4 + TG1_T1_INT_MAP volatile.Register32 // 0x8D8 + TG1_WDT_INT_MAP volatile.Register32 // 0x8DC + CACHE_IA_INT_MAP volatile.Register32 // 0x8E0 + SYSTIMER_TARGET0_INT_MAP volatile.Register32 // 0x8E4 + SYSTIMER_TARGET1_INT_MAP volatile.Register32 // 0x8E8 + SYSTIMER_TARGET2_INT_MAP volatile.Register32 // 0x8EC + SPI_MEM_REJECT_INTR_MAP volatile.Register32 // 0x8F0 + DCACHE_PRELOAD_INT_MAP volatile.Register32 // 0x8F4 + ICACHE_PRELOAD_INT_MAP volatile.Register32 // 0x8F8 + DCACHE_SYNC_INT_MAP volatile.Register32 // 0x8FC + ICACHE_SYNC_INT_MAP volatile.Register32 // 0x900 + APB_ADC_INT_MAP volatile.Register32 // 0x904 + DMA_IN_CH0_INT_MAP volatile.Register32 // 0x908 + DMA_IN_CH1_INT_MAP volatile.Register32 // 0x90C + DMA_IN_CH2_INT_MAP volatile.Register32 // 0x910 + DMA_IN_CH3_INT_MAP volatile.Register32 // 0x914 + DMA_IN_CH4_INT_MAP volatile.Register32 // 0x918 + DMA_OUT_CH0_INT_MAP volatile.Register32 // 0x91C + DMA_OUT_CH1_INT_MAP volatile.Register32 // 0x920 + DMA_OUT_CH2_INT_MAP volatile.Register32 // 0x924 + DMA_OUT_CH3_INT_MAP volatile.Register32 // 0x928 + DMA_OUT_CH4_INT_MAP volatile.Register32 // 0x92C + RSA_INT_MAP volatile.Register32 // 0x930 + AES_INT_MAP volatile.Register32 // 0x934 + SHA_INT_MAP volatile.Register32 // 0x938 + CPU_INTR_FROM_CPU_0_MAP volatile.Register32 // 0x93C + CPU_INTR_FROM_CPU_1_MAP volatile.Register32 // 0x940 + CPU_INTR_FROM_CPU_2_MAP volatile.Register32 // 0x944 + CPU_INTR_FROM_CPU_3_MAP volatile.Register32 // 0x948 + ASSIST_DEBUG_INTR_MAP volatile.Register32 // 0x94C + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x950 + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x954 + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x958 + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x95C + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP volatile.Register32 // 0x960 + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x964 + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x968 + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP volatile.Register32 // 0x96C + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP volatile.Register32 // 0x970 + BACKUP_PMS_VIOLATE_INTR_MAP volatile.Register32 // 0x974 + CACHE_CORE0_ACS_INT_MAP volatile.Register32 // 0x978 + CACHE_CORE1_ACS_INT_MAP volatile.Register32 // 0x97C + USB_DEVICE_INT_MAP volatile.Register32 // 0x980 + PERI_BACKUP_INT_MAP volatile.Register32 // 0x984 + DMA_EXTMEM_REJECT_INT_MAP volatile.Register32 // 0x988 + APP_INTR_STATUS_0 volatile.Register32 // 0x98C + APP_INTR_STATUS_1 volatile.Register32 // 0x990 + APP_INTR_STATUS_2 volatile.Register32 // 0x994 + APP_INTR_STATUS_3 volatile.Register32 // 0x998 + CLOCK_GATE volatile.Register32 // 0x99C + _ [1628]byte + DATE volatile.Register32 // 0xFFC +} + +// INTERRUPT_CORE1.APP_MAC_INTR_MAP: mac interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetAPP_MAC_INTR_MAP_MAC_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.APP_MAC_INTR_MAP.Reg, volatile.LoadUint32(&o.APP_MAC_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetAPP_MAC_INTR_MAP_MAC_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.APP_MAC_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.MAC_NMI_MAP: mac_nmi interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetMAC_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.MAC_NMI_MAP.Reg, volatile.LoadUint32(&o.MAC_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetMAC_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.MAC_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.PWR_INTR_MAP: pwr interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetPWR_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWR_INTR_MAP.Reg, volatile.LoadUint32(&o.PWR_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetPWR_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWR_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.BB_INT_MAP: bb interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetBB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BB_INT_MAP.Reg, volatile.LoadUint32(&o.BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetBB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.BT_MAC_INT_MAP: bb_mac interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetBT_MAC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BT_MAC_INT_MAP.Reg, volatile.LoadUint32(&o.BT_MAC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetBT_MAC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BT_MAC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.BT_BB_INT_MAP: bt_bb interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetBT_BB_INT_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_INT_MAP.Reg, volatile.LoadUint32(&o.BT_BB_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetBT_BB_INT_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.BT_BB_NMI_MAP: bt_bb_nmi interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetBT_BB_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.BT_BB_NMI_MAP.Reg, volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetBT_BB_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.BT_BB_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.RWBT_IRQ_MAP: rwbt_irq interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetRWBT_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.RWBT_IRQ_MAP.Reg, volatile.LoadUint32(&o.RWBT_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetRWBT_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.RWBT_IRQ_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.RWBLE_IRQ_MAP: rwble_irq interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetRWBLE_IRQ_MAP(value uint32) { + volatile.StoreUint32(&o.RWBLE_IRQ_MAP.Reg, volatile.LoadUint32(&o.RWBLE_IRQ_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetRWBLE_IRQ_MAP() uint32 { + return volatile.LoadUint32(&o.RWBLE_IRQ_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.RWBT_NMI_MAP: rwbt_nmi interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetRWBT_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.RWBT_NMI_MAP.Reg, volatile.LoadUint32(&o.RWBT_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetRWBT_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.RWBT_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.RWBLE_NMI_MAP: rwble_nmi interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetRWBLE_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.RWBLE_NMI_MAP.Reg, volatile.LoadUint32(&o.RWBLE_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetRWBLE_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.RWBLE_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.I2C_MST_INT_MAP: i2c_mst interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetI2C_MST_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_MST_INT_MAP.Reg, volatile.LoadUint32(&o.I2C_MST_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetI2C_MST_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_MST_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SLC0_INTR_MAP: slc0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSLC0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SLC0_INTR_MAP.Reg, volatile.LoadUint32(&o.SLC0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSLC0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SLC0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SLC1_INTR_MAP: slc1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSLC1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SLC1_INTR_MAP.Reg, volatile.LoadUint32(&o.SLC1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSLC1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SLC1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.UHCI0_INTR_MAP: uhci0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetUHCI0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UHCI0_INTR_MAP.Reg, volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetUHCI0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UHCI0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.UHCI1_INTR_MAP: uhci1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetUHCI1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UHCI1_INTR_MAP.Reg, volatile.LoadUint32(&o.UHCI1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetUHCI1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UHCI1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.GPIO_INTERRUPT_PRO_MAP: gpio_interrupt_pro interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetGPIO_INTERRUPT_PRO_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetGPIO_INTERRUPT_PRO_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.GPIO_INTERRUPT_PRO_NMI_MAP: gpio_interrupt_pro_nmi interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetGPIO_INTERRUPT_PRO_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetGPIO_INTERRUPT_PRO_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_PRO_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.GPIO_INTERRUPT_APP_MAP: gpio_interrupt_app interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetGPIO_INTERRUPT_APP_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_APP_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_APP_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetGPIO_INTERRUPT_APP_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_APP_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.GPIO_INTERRUPT_APP_NMI_MAP: gpio_interrupt_app_nmi interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetGPIO_INTERRUPT_APP_NMI_MAP(value uint32) { + volatile.StoreUint32(&o.GPIO_INTERRUPT_APP_NMI_MAP.Reg, volatile.LoadUint32(&o.GPIO_INTERRUPT_APP_NMI_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetGPIO_INTERRUPT_APP_NMI_MAP() uint32 { + return volatile.LoadUint32(&o.GPIO_INTERRUPT_APP_NMI_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SPI_INTR_1_MAP: spi_intr_1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSPI_INTR_1_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_1_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSPI_INTR_1_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SPI_INTR_2_MAP: spi_intr_2 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSPI_INTR_2_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_2_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSPI_INTR_2_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SPI_INTR_3_MAP: spi_intr_3 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSPI_INTR_3_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_3_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSPI_INTR_3_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_3_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SPI_INTR_4_MAP: spi_intr_4 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSPI_INTR_4_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_INTR_4_MAP.Reg, volatile.LoadUint32(&o.SPI_INTR_4_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSPI_INTR_4_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_INTR_4_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.LCD_CAM_INT_MAP: lcd_cam interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetLCD_CAM_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LCD_CAM_INT_MAP.Reg, volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetLCD_CAM_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.I2S0_INT_MAP: i2s0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetI2S0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S0_INT_MAP.Reg, volatile.LoadUint32(&o.I2S0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetI2S0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.I2S1_INT_MAP: i2s1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetI2S1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.I2S1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetI2S1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.I2S1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.UART_INTR_MAP: uart interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetUART_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART_INTR_MAP.Reg, volatile.LoadUint32(&o.UART_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetUART_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.UART1_INTR_MAP: uart1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetUART1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART1_INTR_MAP.Reg, volatile.LoadUint32(&o.UART1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetUART1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.UART2_INTR_MAP: uart2 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetUART2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.UART2_INTR_MAP.Reg, volatile.LoadUint32(&o.UART2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetUART2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.UART2_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SDIO_HOST_INTERRUPT_MAP: sdio_host interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSDIO_HOST_INTERRUPT_MAP(value uint32) { + volatile.StoreUint32(&o.SDIO_HOST_INTERRUPT_MAP.Reg, volatile.LoadUint32(&o.SDIO_HOST_INTERRUPT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSDIO_HOST_INTERRUPT_MAP() uint32 { + return volatile.LoadUint32(&o.SDIO_HOST_INTERRUPT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.PWM0_INTR_MAP: pwm0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetPWM0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM0_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetPWM0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.PWM1_INTR_MAP: pwm1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetPWM1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM1_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetPWM1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.PWM2_INTR_MAP: pwm2 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetPWM2_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM2_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM2_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetPWM2_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM2_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.PWM3_INTR_MAP: pwm3 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetPWM3_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PWM3_INTR_MAP.Reg, volatile.LoadUint32(&o.PWM3_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetPWM3_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PWM3_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.LEDC_INT_MAP: ledc interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetLEDC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.LEDC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetLEDC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.LEDC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.EFUSE_INT_MAP: efuse interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetEFUSE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.EFUSE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetEFUSE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.EFUSE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CAN_INT_MAP: can interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCAN_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CAN_INT_MAP.Reg, volatile.LoadUint32(&o.CAN_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCAN_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CAN_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.USB_INTR_MAP: usb interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetUSB_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.USB_INTR_MAP.Reg, volatile.LoadUint32(&o.USB_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetUSB_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.USB_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.RTC_CORE_INTR_MAP: rtc_core interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetRTC_CORE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RTC_CORE_INTR_MAP.Reg, volatile.LoadUint32(&o.RTC_CORE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetRTC_CORE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RTC_CORE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.RMT_INTR_MAP: rmt interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetRMT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.RMT_INTR_MAP.Reg, volatile.LoadUint32(&o.RMT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetRMT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.RMT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.PCNT_INTR_MAP: pcnt interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetPCNT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.PCNT_INTR_MAP.Reg, volatile.LoadUint32(&o.PCNT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetPCNT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.PCNT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.I2C_EXT0_INTR_MAP: i2c_ext0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetI2C_EXT0_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_EXT0_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetI2C_EXT0_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_EXT0_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.I2C_EXT1_INTR_MAP: i2c_ext1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetI2C_EXT1_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.I2C_EXT1_INTR_MAP.Reg, volatile.LoadUint32(&o.I2C_EXT1_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetI2C_EXT1_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.I2C_EXT1_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SPI2_DMA_INT_MAP: spi2_dma interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSPI2_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI2_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.SPI2_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSPI2_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI2_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SPI3_DMA_INT_MAP: spi3_dma interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSPI3_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI3_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.SPI3_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSPI3_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI3_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SPI4_DMA_INT_MAP: spi4_dma interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSPI4_DMA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SPI4_DMA_INT_MAP.Reg, volatile.LoadUint32(&o.SPI4_DMA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSPI4_DMA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SPI4_DMA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.WDG_INT_MAP: wdg interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetWDG_INT_MAP(value uint32) { + volatile.StoreUint32(&o.WDG_INT_MAP.Reg, volatile.LoadUint32(&o.WDG_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetWDG_INT_MAP() uint32 { + return volatile.LoadUint32(&o.WDG_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.TIMER_INT1_MAP: timer_int1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetTIMER_INT1_MAP(value uint32) { + volatile.StoreUint32(&o.TIMER_INT1_MAP.Reg, volatile.LoadUint32(&o.TIMER_INT1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetTIMER_INT1_MAP() uint32 { + return volatile.LoadUint32(&o.TIMER_INT1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.TIMER_INT2_MAP: timer_int2 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetTIMER_INT2_MAP(value uint32) { + volatile.StoreUint32(&o.TIMER_INT2_MAP.Reg, volatile.LoadUint32(&o.TIMER_INT2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetTIMER_INT2_MAP() uint32 { + return volatile.LoadUint32(&o.TIMER_INT2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.TG_T0_INT_MAP: tg_t0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetTG_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TG_T0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetTG_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_T0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.TG_T1_INT_MAP: tg_t1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetTG_T1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TG_T1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetTG_T1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_T1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.TG_WDT_INT_MAP: tg_wdt interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetTG_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TG_WDT_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetTG_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG_WDT_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.TG1_T0_INT_MAP: tg1_t0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetTG1_T0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TG1_T0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetTG1_T0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_T0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.TG1_T1_INT_MAP: tg1_t1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetTG1_T1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TG1_T1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetTG1_T1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_T1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.TG1_WDT_INT_MAP: tg1_wdt interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetTG1_WDT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.TG1_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TG1_WDT_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetTG1_WDT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.TG1_WDT_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CACHE_IA_INT_MAP: cache_ia interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCACHE_IA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_IA_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_IA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCACHE_IA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_IA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SYSTIMER_TARGET0_INT_MAP: systimer_target0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSYSTIMER_TARGET0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSYSTIMER_TARGET0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SYSTIMER_TARGET1_INT_MAP: systimer_target1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSYSTIMER_TARGET1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSYSTIMER_TARGET1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SYSTIMER_TARGET2_INT_MAP: systimer_target2 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSYSTIMER_TARGET2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSYSTIMER_TARGET2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SPI_MEM_REJECT_INTR_MAP: spi_mem_reject interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSPI_MEM_REJECT_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg, volatile.LoadUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSPI_MEM_REJECT_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.SPI_MEM_REJECT_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DCACHE_PRELOAD_INT_MAP: dcache_prelaod interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDCACHE_PRELOAD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DCACHE_PRELOAD_INT_MAP.Reg, volatile.LoadUint32(&o.DCACHE_PRELOAD_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDCACHE_PRELOAD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DCACHE_PRELOAD_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.ICACHE_PRELOAD_INT_MAP: icache_preload interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetICACHE_PRELOAD_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg, volatile.LoadUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetICACHE_PRELOAD_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ICACHE_PRELOAD_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DCACHE_SYNC_INT_MAP: dcache_sync interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDCACHE_SYNC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DCACHE_SYNC_INT_MAP.Reg, volatile.LoadUint32(&o.DCACHE_SYNC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDCACHE_SYNC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DCACHE_SYNC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.ICACHE_SYNC_INT_MAP: icache_sync interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetICACHE_SYNC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.ICACHE_SYNC_INT_MAP.Reg, volatile.LoadUint32(&o.ICACHE_SYNC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetICACHE_SYNC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.ICACHE_SYNC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.APB_ADC_INT_MAP: apb_adc interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetAPB_ADC_INT_MAP(value uint32) { + volatile.StoreUint32(&o.APB_ADC_INT_MAP.Reg, volatile.LoadUint32(&o.APB_ADC_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetAPB_ADC_INT_MAP() uint32 { + return volatile.LoadUint32(&o.APB_ADC_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_IN_CH0_INT_MAP: dma_in_ch0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_IN_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_IN_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_IN_CH1_INT_MAP: dma_in_ch1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_IN_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_IN_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_IN_CH2_INT_MAP: dma_in_ch2 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_IN_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_IN_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_IN_CH3_INT_MAP: dma_in_ch3 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_IN_CH3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH3_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_IN_CH3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH3_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_IN_CH4_INT_MAP: dma_in_ch4 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_IN_CH4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_IN_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_IN_CH4_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_IN_CH4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_IN_CH4_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_OUT_CH0_INT_MAP: dma_out_ch0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_OUT_CH0_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH0_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_OUT_CH0_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH0_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_OUT_CH1_INT_MAP: dma_out_ch1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_OUT_CH1_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH1_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_OUT_CH1_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH1_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_OUT_CH2_INT_MAP: dma_out_ch2 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_OUT_CH2_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH2_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_OUT_CH2_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH2_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_OUT_CH3_INT_MAP: dma_out_ch3 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_OUT_CH3_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH3_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_OUT_CH3_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH3_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_OUT_CH4_INT_MAP: dma_out_ch4 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_OUT_CH4_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_OUT_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_OUT_CH4_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_OUT_CH4_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_OUT_CH4_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.RSA_INT_MAP: rsa interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetRSA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.RSA_INT_MAP.Reg, volatile.LoadUint32(&o.RSA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetRSA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.RSA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.AES_INT_MAP: aes interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetAES_INT_MAP(value uint32) { + volatile.StoreUint32(&o.AES_INT_MAP.Reg, volatile.LoadUint32(&o.AES_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetAES_INT_MAP() uint32 { + return volatile.LoadUint32(&o.AES_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.SHA_INT_MAP: sha interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetSHA_INT_MAP(value uint32) { + volatile.StoreUint32(&o.SHA_INT_MAP.Reg, volatile.LoadUint32(&o.SHA_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetSHA_INT_MAP() uint32 { + return volatile.LoadUint32(&o.SHA_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CPU_INTR_FROM_CPU_0_MAP: cpu_intr_from_cpu_0 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCPU_INTR_FROM_CPU_0_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCPU_INTR_FROM_CPU_0_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CPU_INTR_FROM_CPU_1_MAP: cpu_intr_from_cpu_1 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCPU_INTR_FROM_CPU_1_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCPU_INTR_FROM_CPU_1_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CPU_INTR_FROM_CPU_2_MAP: cpu_intr_from_cpu_2 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCPU_INTR_FROM_CPU_2_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCPU_INTR_FROM_CPU_2_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CPU_INTR_FROM_CPU_3_MAP: cpu_intr_from_cpu_3 interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCPU_INTR_FROM_CPU_3_MAP(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCPU_INTR_FROM_CPU_3_MAP() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.ASSIST_DEBUG_INTR_MAP: assist_debug interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetASSIST_DEBUG_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetASSIST_DEBUG_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.ASSIST_DEBUG_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: dma_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core0_IRam0_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core0_DRam0_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: core0_PIF_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: core0_PIF_pms_monitor_violatile_size interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core1_IRam0_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core1_DRam0_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: core1_PIF_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: core1_PIF_pms_monitor_violatile_size interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.BACKUP_PMS_VIOLATE_INTR_MAP: backup_pms_monitor_violatile interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetBACKUP_PMS_VIOLATE_INTR_MAP(value uint32) { + volatile.StoreUint32(&o.BACKUP_PMS_VIOLATE_INTR_MAP.Reg, volatile.LoadUint32(&o.BACKUP_PMS_VIOLATE_INTR_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetBACKUP_PMS_VIOLATE_INTR_MAP() uint32 { + return volatile.LoadUint32(&o.BACKUP_PMS_VIOLATE_INTR_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CACHE_CORE0_ACS_INT_MAP: cache_core0_acs interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCACHE_CORE0_ACS_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCACHE_CORE0_ACS_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_CORE0_ACS_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.CACHE_CORE1_ACS_INT_MAP: cache_core1_acs interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetCACHE_CORE1_ACS_INT_MAP(value uint32) { + volatile.StoreUint32(&o.CACHE_CORE1_ACS_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_CORE1_ACS_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCACHE_CORE1_ACS_INT_MAP() uint32 { + return volatile.LoadUint32(&o.CACHE_CORE1_ACS_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.USB_DEVICE_INT_MAP: usb_device interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetUSB_DEVICE_INT_MAP(value uint32) { + volatile.StoreUint32(&o.USB_DEVICE_INT_MAP.Reg, volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetUSB_DEVICE_INT_MAP() uint32 { + return volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.PERI_BACKUP_INT_MAP: peri_backup interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetPERI_BACKUP_INT_MAP(value uint32) { + volatile.StoreUint32(&o.PERI_BACKUP_INT_MAP.Reg, volatile.LoadUint32(&o.PERI_BACKUP_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetPERI_BACKUP_INT_MAP() uint32 { + return volatile.LoadUint32(&o.PERI_BACKUP_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.DMA_EXTMEM_REJECT_INT_MAP: dma_extmem_reject interrupt configuration register +func (o *INTERRUPT_CORE1_Type) SetDMA_EXTMEM_REJECT_INT_MAP(value uint32) { + volatile.StoreUint32(&o.DMA_EXTMEM_REJECT_INT_MAP.Reg, volatile.LoadUint32(&o.DMA_EXTMEM_REJECT_INT_MAP.Reg)&^(0x1f)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDMA_EXTMEM_REJECT_INT_MAP() uint32 { + return volatile.LoadUint32(&o.DMA_EXTMEM_REJECT_INT_MAP.Reg) & 0x1f +} + +// INTERRUPT_CORE1.APP_INTR_STATUS_0: interrupt status register +func (o *INTERRUPT_CORE1_Type) SetAPP_INTR_STATUS_0(value uint32) { + volatile.StoreUint32(&o.APP_INTR_STATUS_0.Reg, value) +} +func (o *INTERRUPT_CORE1_Type) GetAPP_INTR_STATUS_0() uint32 { + return volatile.LoadUint32(&o.APP_INTR_STATUS_0.Reg) +} + +// INTERRUPT_CORE1.APP_INTR_STATUS_1: interrupt status register +func (o *INTERRUPT_CORE1_Type) SetAPP_INTR_STATUS_1(value uint32) { + volatile.StoreUint32(&o.APP_INTR_STATUS_1.Reg, value) +} +func (o *INTERRUPT_CORE1_Type) GetAPP_INTR_STATUS_1() uint32 { + return volatile.LoadUint32(&o.APP_INTR_STATUS_1.Reg) +} + +// INTERRUPT_CORE1.APP_INTR_STATUS_2: interrupt status register +func (o *INTERRUPT_CORE1_Type) SetAPP_INTR_STATUS_2(value uint32) { + volatile.StoreUint32(&o.APP_INTR_STATUS_2.Reg, value) +} +func (o *INTERRUPT_CORE1_Type) GetAPP_INTR_STATUS_2() uint32 { + return volatile.LoadUint32(&o.APP_INTR_STATUS_2.Reg) +} + +// INTERRUPT_CORE1.APP_INTR_STATUS_3: interrupt status register +func (o *INTERRUPT_CORE1_Type) SetAPP_INTR_STATUS_3(value uint32) { + volatile.StoreUint32(&o.APP_INTR_STATUS_3.Reg, value) +} +func (o *INTERRUPT_CORE1_Type) GetAPP_INTR_STATUS_3() uint32 { + return volatile.LoadUint32(&o.APP_INTR_STATUS_3.Reg) +} + +// INTERRUPT_CORE1.CLOCK_GATE: clock gate register +func (o *INTERRUPT_CORE1_Type) SetCLOCK_GATE_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *INTERRUPT_CORE1_Type) GetCLOCK_GATE_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// INTERRUPT_CORE1.DATE: version register +func (o *INTERRUPT_CORE1_Type) SetDATE_INTERRUPT_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *INTERRUPT_CORE1_Type) GetDATE_INTERRUPT_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Input/Output Multiplexer +type IO_MUX_Type struct { + PIN_CTRL volatile.Register32 // 0x0 + GPIO0 volatile.Register32 // 0x4 + GPIO1 volatile.Register32 // 0x8 + GPIO2 volatile.Register32 // 0xC + GPIO3 volatile.Register32 // 0x10 + GPIO4 volatile.Register32 // 0x14 + GPIO5 volatile.Register32 // 0x18 + GPIO6 volatile.Register32 // 0x1C + GPIO7 volatile.Register32 // 0x20 + GPIO8 volatile.Register32 // 0x24 + GPIO9 volatile.Register32 // 0x28 + GPIO10 volatile.Register32 // 0x2C + GPIO11 volatile.Register32 // 0x30 + GPIO12 volatile.Register32 // 0x34 + GPIO13 volatile.Register32 // 0x38 + GPIO14 volatile.Register32 // 0x3C + GPIO15 volatile.Register32 // 0x40 + GPIO16 volatile.Register32 // 0x44 + GPIO17 volatile.Register32 // 0x48 + GPIO18 volatile.Register32 // 0x4C + GPIO19 volatile.Register32 // 0x50 + GPIO20 volatile.Register32 // 0x54 + GPIO21 volatile.Register32 // 0x58 + GPIO22 volatile.Register32 // 0x5C + GPIO23 volatile.Register32 // 0x60 + GPIO24 volatile.Register32 // 0x64 + GPIO25 volatile.Register32 // 0x68 + GPIO26 volatile.Register32 // 0x6C + GPIO27 volatile.Register32 // 0x70 + GPIO28 volatile.Register32 // 0x74 + GPIO29 volatile.Register32 // 0x78 + GPIO30 volatile.Register32 // 0x7C + GPIO31 volatile.Register32 // 0x80 + GPIO32 volatile.Register32 // 0x84 + GPIO33 volatile.Register32 // 0x88 + GPIO34 volatile.Register32 // 0x8C + GPIO35 volatile.Register32 // 0x90 + GPIO36 volatile.Register32 // 0x94 + GPIO37 volatile.Register32 // 0x98 + GPIO38 volatile.Register32 // 0x9C + GPIO39 volatile.Register32 // 0xA0 + GPIO40 volatile.Register32 // 0xA4 + GPIO41 volatile.Register32 // 0xA8 + GPIO42 volatile.Register32 // 0xAC + GPIO43 volatile.Register32 // 0xB0 + GPIO44 volatile.Register32 // 0xB4 + GPIO45 volatile.Register32 // 0xB8 + GPIO46 volatile.Register32 // 0xBC + GPIO47 volatile.Register32 // 0xC0 + GPIO48 volatile.Register32 // 0xC4 + _ [52]byte + DATE volatile.Register32 // 0xFC +} + +// IO_MUX.PIN_CTRL: Clock Output Configuration Register +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT1(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf)|value) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT1() uint32 { + return volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT2(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf0)|value<<4) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT2() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf0) >> 4 +} +func (o *IO_MUX_Type) SetPIN_CTRL_CLK_OUT3(value uint32) { + volatile.StoreUint32(&o.PIN_CTRL.Reg, volatile.LoadUint32(&o.PIN_CTRL.Reg)&^(0xf00)|value<<8) +} +func (o *IO_MUX_Type) GetPIN_CTRL_CLK_OUT3() uint32 { + return (volatile.LoadUint32(&o.PIN_CTRL.Reg) & 0xf00) >> 8 +} + +// IO_MUX.GPIO0: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO0_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO0_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO0_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO0_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO0_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO1: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO1_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO1_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO1_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO1_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO1_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO1_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO1_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO2: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO2_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO2_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO2_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO2_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO2_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO2_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO2_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO3: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO3_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO3_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO3_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO3_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO3_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO3_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO3_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO4: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO4_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO4_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO4_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO4_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO4_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO4_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO4_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO5: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO5_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO5_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO5_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO5_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO5_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO5_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO5_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO6: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO6_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO6_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO6_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO6_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO6_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO6_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO6_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO7: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO7_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO7_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO7_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO7_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO7_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO7_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO7_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO8: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO8_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO8.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO8_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO8_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO8_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO8_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO8_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO8_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO9: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO9_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO9.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO9_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO9_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO9_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO9_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO9_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO9_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO10: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO10_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO10.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO10_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO10_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO10_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO10_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO10_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO10_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO11: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO11_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO11.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO11_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO11_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO11_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO11_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO11_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO11_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO12: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO12_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO12.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO12_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO12_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO12_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO12_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO12_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO12_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO13: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO13_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO13.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO13_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO13_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO13_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO13_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO13_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO13_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO14: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO14_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO14.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO14_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO14_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO14_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO14_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO14_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO14_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO15: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO15_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO15.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO15_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO15_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO15_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO15_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO15_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO15_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO15_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO15_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO16: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO16_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO16.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO16_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO16_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO16_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO16_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO16_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO16_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO16_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO16_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO17: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO17_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO17.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO17_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO17_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO17_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO17_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO17_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO17_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO17_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO17_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO18: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO18_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO18.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO18_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO18_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO18_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO18_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO18_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO18_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO18_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO18_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO19: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO19_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO19.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO19_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO19_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO19_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO19_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO19_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO19_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO20: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO20_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO20.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO20_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO20_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO20_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO20_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO20_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO20_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO21: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO21_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO21.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO21_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO21_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO21_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO21_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO21_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO21_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO22: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO22_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO22.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO22_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO22_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO22_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO22_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO22_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO22_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO22_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO22_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO23: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO23_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO23.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO23_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO23_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO23_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO23_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO23_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO23_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO23_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO23_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO24: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO24_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO24.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO24_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO24_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO24_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO24_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO24_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO24_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO24_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO24_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO25: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO25_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO25.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO25_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO25_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO25_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO25_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO25_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO25_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO25_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO25_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO26: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO26_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO26.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO26_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO26_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO26_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO26_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO26_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO26_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO26_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO26_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO27: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO27_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO27.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO27_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO27_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO27_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO27_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO27_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO27_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO27_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO27_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO28: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO28_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO28.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO28_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO28_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO28_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO28_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO28_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO28_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO28_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO28_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO29: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO29_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO29.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO29_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO29_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO29_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO29_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO29_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO29_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO29_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO29_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO30: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO30_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO30.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO30_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO30_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO30_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO30_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO30_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO30_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO30_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO30_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO31: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO31_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO31.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO31_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO31_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO31_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO31_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO31_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO31_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO31_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO31_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO32: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO32_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO32.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO32_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO32_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO32_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO32_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO32_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO32_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO32_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO32_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO33: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO33_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO33.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO33_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO33_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO33_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO33_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO33_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO33_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO33_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO33_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO34: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO34_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO34.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO34_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO34_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO34_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO34_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO34_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO34_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO34_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO34_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO35: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO35_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO35.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO35_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO35_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO35_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO35_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO35_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO35_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO35_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO35_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO36: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO36_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO36.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO36_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO36_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO36_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO36_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO36_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO36_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO36_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO36_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO37: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO37_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO37.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO37_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO37_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO37_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO37_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO37_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO37_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO37_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO37_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO38: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO38_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO38.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO38_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO38_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO38_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO38_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO38_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO38_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO38_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO38_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO39: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO39_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO39.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO39_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO39_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO39_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO39_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO39_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO39_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO39_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO39_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO40: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO40_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO40.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO40_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO40_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO40_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO40_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO40_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO40_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO40_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO40_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO41: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO41_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO41.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO41_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO41_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO41_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO41_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO41_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO41_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO41_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO41_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO42: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO42_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO42.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO42_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO42_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO42_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO42_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO42_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO42_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO42_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO42_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO43: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO43_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO43.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO43_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO43_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO43_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO43_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO43_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO43_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO43_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO43_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO44: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO44_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO44.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO44_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO44_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO44_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO44_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO44_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO44_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO44_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO44_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO45: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO45_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO45.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO45_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO45_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO45_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO45_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO45_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO45_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO45_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO45_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO46: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO46_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO46.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO46_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO46_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO46_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO46_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO46_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO46_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO46_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO46_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO47: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO47_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO47.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO47_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO47_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO47_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO47_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO47_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO47_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO47_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO47_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO47_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO47_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO47_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO47_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO47_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO47_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO47_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO47_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO47_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x8000) >> 15 +} + +// IO_MUX.GPIO48: IO MUX Configure Register for pad GPIO0 +func (o *IO_MUX_Type) SetGPIO48_MCU_OE(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_OE() uint32 { + return volatile.LoadUint32(&o.GPIO48.Reg) & 0x1 +} +func (o *IO_MUX_Type) SetGPIO48_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x2)|value<<1) +} +func (o *IO_MUX_Type) GetGPIO48_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x2) >> 1 +} +func (o *IO_MUX_Type) SetGPIO48_MCU_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x4)|value<<2) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x4) >> 2 +} +func (o *IO_MUX_Type) SetGPIO48_MCU_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetGPIO48_MCU_IE(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x10)|value<<4) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x10) >> 4 +} +func (o *IO_MUX_Type) SetGPIO48_FUN_WPD(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetGPIO48_FUN_WPD() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetGPIO48_FUN_WPU(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetGPIO48_FUN_WPU() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetGPIO48_FUN_IE(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetGPIO48_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x200) >> 9 +} +func (o *IO_MUX_Type) SetGPIO48_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0xc00)|value<<10) +} +func (o *IO_MUX_Type) GetGPIO48_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0xc00) >> 10 +} +func (o *IO_MUX_Type) SetGPIO48_MCU_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x7000)|value<<12) +} +func (o *IO_MUX_Type) GetGPIO48_MCU_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x7000) >> 12 +} +func (o *IO_MUX_Type) SetGPIO48_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x8000)|value<<15) +} +func (o *IO_MUX_Type) GetGPIO48_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x8000) >> 15 +} + +// IO_MUX.DATE: IO MUX Version Control Register +func (o *IO_MUX_Type) SetDATE_REG_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *IO_MUX_Type) GetDATE_REG_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Camera/LCD Controller +type LCD_CAM_Type struct { + LCD_CLOCK volatile.Register32 // 0x0 + CAM_CTRL volatile.Register32 // 0x4 + CAM_CTRL1 volatile.Register32 // 0x8 + CAM_RGB_YUV volatile.Register32 // 0xC + LCD_RGB_YUV volatile.Register32 // 0x10 + LCD_USER volatile.Register32 // 0x14 + LCD_MISC volatile.Register32 // 0x18 + LCD_CTRL volatile.Register32 // 0x1C + LCD_CTRL1 volatile.Register32 // 0x20 + LCD_CTRL2 volatile.Register32 // 0x24 + LCD_CMD_VAL volatile.Register32 // 0x28 + _ [4]byte + LCD_DLY_MODE volatile.Register32 // 0x30 + _ [4]byte + LCD_DATA_DOUT_MODE volatile.Register32 // 0x38 + _ [40]byte + LC_DMA_INT_ENA volatile.Register32 // 0x64 + LC_DMA_INT_RAW volatile.Register32 // 0x68 + LC_DMA_INT_ST volatile.Register32 // 0x6C + LC_DMA_INT_CLR volatile.Register32 // 0x70 + _ [136]byte + LC_REG_DATE volatile.Register32 // 0xFC +} + +// LCD_CAM.LCD_CLOCK: LCD clock register +func (o *LCD_CAM_Type) SetLCD_CLOCK_LCD_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x3f)|value) +} +func (o *LCD_CAM_Type) GetLCD_CLOCK_LCD_CLKCNT_N() uint32 { + return volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x3f +} +func (o *LCD_CAM_Type) SetLCD_CLOCK_LCD_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x40)|value<<6) +} +func (o *LCD_CAM_Type) GetLCD_CLOCK_LCD_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x40) >> 6 +} +func (o *LCD_CAM_Type) SetLCD_CLOCK_LCD_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x80)|value<<7) +} +func (o *LCD_CAM_Type) GetLCD_CLOCK_LCD_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x80) >> 7 +} +func (o *LCD_CAM_Type) SetLCD_CLOCK_LCD_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x100)|value<<8) +} +func (o *LCD_CAM_Type) GetLCD_CLOCK_LCD_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x100) >> 8 +} +func (o *LCD_CAM_Type) SetLCD_CLOCK_LCD_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x1fe00)|value<<9) +} +func (o *LCD_CAM_Type) GetLCD_CLOCK_LCD_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x1fe00) >> 9 +} +func (o *LCD_CAM_Type) SetLCD_CLOCK_LCD_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x7e0000)|value<<17) +} +func (o *LCD_CAM_Type) GetLCD_CLOCK_LCD_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x7e0000) >> 17 +} +func (o *LCD_CAM_Type) SetLCD_CLOCK_LCD_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x1f800000)|value<<23) +} +func (o *LCD_CAM_Type) GetLCD_CLOCK_LCD_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x1f800000) >> 23 +} +func (o *LCD_CAM_Type) SetLCD_CLOCK_LCD_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x60000000)|value<<29) +} +func (o *LCD_CAM_Type) GetLCD_CLOCK_LCD_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x60000000) >> 29 +} +func (o *LCD_CAM_Type) SetLCD_CLOCK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *LCD_CAM_Type) GetLCD_CLOCK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x80000000) >> 31 +} + +// LCD_CAM.CAM_CTRL: Camera configuration register +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x1)|value) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_STOP_EN() uint32 { + return volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x1 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_VSYNC_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0xe)|value<<1) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_VSYNC_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0xe) >> 1 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_UPDATE(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x10) >> 4 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x20)|value<<5) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x20) >> 5 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x40) >> 6 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_LINE_INT_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_LINE_INT_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x80) >> 7 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_VS_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_VS_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x100) >> 8 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x1fe00)|value<<9) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x1fe00) >> 9 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_CLKM_DIV_B(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x7e0000)|value<<17) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_CLKM_DIV_B() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x7e0000) >> 17 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_CLKM_DIV_A(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x1f800000)|value<<23) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_CLKM_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x1f800000) >> 23 +} +func (o *LCD_CAM_Type) SetCAM_CTRL_CAM_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x60000000)|value<<29) +} +func (o *LCD_CAM_Type) GetCAM_CTRL_CAM_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x60000000) >> 29 +} + +// LCD_CAM.CAM_CTRL1: Camera configuration register +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_REC_DATA_BYTELEN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0xffff)|value) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_REC_DATA_BYTELEN() uint32 { + return volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0xffff +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_LINE_INT_NUM(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x3f0000)|value<<16) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_LINE_INT_NUM() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x3f0000) >> 16 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_CLK_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x400000)|value<<22) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x400000) >> 22 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_VSYNC_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x800000)|value<<23) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_VSYNC_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x800000) >> 23 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_2BYTE_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x1000000)|value<<24) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_2BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x1000000) >> 24 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_DE_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x2000000)|value<<25) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_DE_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x2000000) >> 25 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_HSYNC_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x4000000)|value<<26) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_HSYNC_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x4000000) >> 26 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_VSYNC_INV(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x8000000)|value<<27) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_VSYNC_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x8000000) >> 27 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_VH_DE_MODE_EN(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x10000000)|value<<28) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_VH_DE_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x10000000) >> 28 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_START(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x20000000)|value<<29) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_START() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x20000000) >> 29 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_RESET(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_RESET() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x40000000) >> 30 +} +func (o *LCD_CAM_Type) SetCAM_CTRL1_CAM_AFIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x80000000)|value<<31) +} +func (o *LCD_CAM_Type) GetCAM_CTRL1_CAM_AFIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x80000000) >> 31 +} + +// LCD_CAM.CAM_RGB_YUV: Camera configuration register +func (o *LCD_CAM_Type) SetCAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x200000)|value<<21) +} +func (o *LCD_CAM_Type) GetCAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x200000) >> 21 +} +func (o *LCD_CAM_Type) SetCAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0xc00000)|value<<22) +} +func (o *LCD_CAM_Type) GetCAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0xc00000) >> 22 +} +func (o *LCD_CAM_Type) SetCAM_RGB_YUV_CAM_CONV_YUV_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x3000000)|value<<24) +} +func (o *LCD_CAM_Type) GetCAM_RGB_YUV_CAM_CONV_YUV_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x3000000) >> 24 +} +func (o *LCD_CAM_Type) SetCAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x4000000)|value<<26) +} +func (o *LCD_CAM_Type) GetCAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x4000000) >> 26 +} +func (o *LCD_CAM_Type) SetCAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x8000000)|value<<27) +} +func (o *LCD_CAM_Type) GetCAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x8000000) >> 27 +} +func (o *LCD_CAM_Type) SetCAM_RGB_YUV_CAM_CONV_DATA_IN_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x10000000)|value<<28) +} +func (o *LCD_CAM_Type) GetCAM_RGB_YUV_CAM_CONV_DATA_IN_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x10000000) >> 28 +} +func (o *LCD_CAM_Type) SetCAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x20000000)|value<<29) +} +func (o *LCD_CAM_Type) GetCAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x20000000) >> 29 +} +func (o *LCD_CAM_Type) SetCAM_RGB_YUV_CAM_CONV_TRANS_MODE(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x40000000)|value<<30) +} +func (o *LCD_CAM_Type) GetCAM_RGB_YUV_CAM_CONV_TRANS_MODE() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x40000000) >> 30 +} +func (o *LCD_CAM_Type) SetCAM_RGB_YUV_CAM_CONV_BYPASS(value uint32) { + volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x80000000)|value<<31) +} +func (o *LCD_CAM_Type) GetCAM_RGB_YUV_CAM_CONV_BYPASS() uint32 { + return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x80000000) >> 31 +} + +// LCD_CAM.LCD_RGB_YUV: LCD configuration register +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x100000)|value<<20) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x100000) >> 20 +} +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_TXTORX(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x200000)|value<<21) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_TXTORX() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x200000) >> 21 +} +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0xc00000)|value<<22) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0xc00000) >> 22 +} +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_YUV_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x3000000)|value<<24) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_YUV_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x3000000) >> 24 +} +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x4000000)|value<<26) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x4000000) >> 26 +} +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x8000000)|value<<27) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x8000000) >> 27 +} +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_DATA_IN_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x10000000)|value<<28) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_DATA_IN_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x10000000) >> 28 +} +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x20000000)|value<<29) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x20000000) >> 29 +} +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_TRANS_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x40000000)|value<<30) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_TRANS_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x40000000) >> 30 +} +func (o *LCD_CAM_Type) SetLCD_RGB_YUV_LCD_CONV_BYPASS(value uint32) { + volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x80000000)|value<<31) +} +func (o *LCD_CAM_Type) GetLCD_RGB_YUV_LCD_CONV_BYPASS() uint32 { + return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x80000000) >> 31 +} + +// LCD_CAM.LCD_USER: LCD configuration register +func (o *LCD_CAM_Type) SetLCD_USER_LCD_DOUT_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x1fff)|value) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_DOUT_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.LCD_USER.Reg) & 0x1fff +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_ALWAYS_OUT_EN(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x2000)|value<<13) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_ALWAYS_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x2000) >> 13 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_8BITS_ORDER(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x80000)|value<<19) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_8BITS_ORDER() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x80000) >> 19 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_UPDATE(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x100000)|value<<20) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_UPDATE() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x100000) >> 20 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x200000)|value<<21) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x200000) >> 21 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x400000)|value<<22) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x400000) >> 22 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_2BYTE_EN(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x800000)|value<<23) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_2BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x800000) >> 23 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_DOUT(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x1000000)|value<<24) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_DOUT() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x1000000) >> 24 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_DUMMY(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x2000000)|value<<25) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_DUMMY() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x2000000) >> 25 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_CMD(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x4000000)|value<<26) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_CMD() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x4000000) >> 26 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_START(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x8000000)|value<<27) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_START() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x8000000) >> 27 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_RESET(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x10000000)|value<<28) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_RESET() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x10000000) >> 28 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x60000000)|value<<29) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x60000000) >> 29 +} +func (o *LCD_CAM_Type) SetLCD_USER_LCD_CMD_2_CYCLE_EN(value uint32) { + volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x80000000)|value<<31) +} +func (o *LCD_CAM_Type) GetLCD_USER_LCD_CMD_2_CYCLE_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x80000000) >> 31 +} + +// LCD_CAM.LCD_MISC: LCD configuration register +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_AFIFO_THRESHOLD_NUM(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x3e)|value<<1) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_AFIFO_THRESHOLD_NUM() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x3e) >> 1 +} +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_VFK_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0xfc0)|value<<6) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_VFK_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0xfc0) >> 6 +} +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_VBK_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x1fff000)|value<<12) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_VBK_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x1fff000) >> 12 +} +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_NEXT_FRAME_EN(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x2000000)|value<<25) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_NEXT_FRAME_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x2000000) >> 25 +} +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_BK_EN(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x4000000)|value<<26) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_BK_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x4000000) >> 26 +} +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_AFIFO_RESET(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x8000000)|value<<27) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_AFIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x8000000) >> 27 +} +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_CD_DATA_SET(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x10000000)|value<<28) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_CD_DATA_SET() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x10000000) >> 28 +} +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_CD_DUMMY_SET(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_CD_DUMMY_SET() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x20000000) >> 29 +} +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_CD_CMD_SET(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_CD_CMD_SET() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x40000000) >> 30 +} +func (o *LCD_CAM_Type) SetLCD_MISC_LCD_CD_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *LCD_CAM_Type) GetLCD_MISC_LCD_CD_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x80000000) >> 31 +} + +// LCD_CAM.LCD_CTRL: LCD configuration register +func (o *LCD_CAM_Type) SetLCD_CTRL_LCD_HB_FRONT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x7ff)|value) +} +func (o *LCD_CAM_Type) GetLCD_CTRL_LCD_HB_FRONT() uint32 { + return volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x7ff +} +func (o *LCD_CAM_Type) SetLCD_CTRL_LCD_VA_HEIGHT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x1ff800)|value<<11) +} +func (o *LCD_CAM_Type) GetLCD_CTRL_LCD_VA_HEIGHT() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x1ff800) >> 11 +} +func (o *LCD_CAM_Type) SetLCD_CTRL_LCD_VT_HEIGHT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x7fe00000)|value<<21) +} +func (o *LCD_CAM_Type) GetLCD_CTRL_LCD_VT_HEIGHT() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x7fe00000) >> 21 +} +func (o *LCD_CAM_Type) SetLCD_CTRL_LCD_RGB_MODE_EN(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *LCD_CAM_Type) GetLCD_CTRL_LCD_RGB_MODE_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x80000000) >> 31 +} + +// LCD_CAM.LCD_CTRL1: LCD configuration register +func (o *LCD_CAM_Type) SetLCD_CTRL1_LCD_VB_FRONT(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xff)|value) +} +func (o *LCD_CAM_Type) GetLCD_CTRL1_LCD_VB_FRONT() uint32 { + return volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xff +} +func (o *LCD_CAM_Type) SetLCD_CTRL1_LCD_HA_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xfff00)|value<<8) +} +func (o *LCD_CAM_Type) GetLCD_CTRL1_LCD_HA_WIDTH() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xfff00) >> 8 +} +func (o *LCD_CAM_Type) SetLCD_CTRL1_LCD_HT_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xfff00000)|value<<20) +} +func (o *LCD_CAM_Type) GetLCD_CTRL1_LCD_HT_WIDTH() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xfff00000) >> 20 +} + +// LCD_CAM.LCD_CTRL2: LCD configuration register +func (o *LCD_CAM_Type) SetLCD_CTRL2_LCD_VSYNC_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x7f)|value) +} +func (o *LCD_CAM_Type) GetLCD_CTRL2_LCD_VSYNC_WIDTH() uint32 { + return volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x7f +} +func (o *LCD_CAM_Type) SetLCD_CTRL2_LCD_VSYNC_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x80)|value<<7) +} +func (o *LCD_CAM_Type) GetLCD_CTRL2_LCD_VSYNC_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x80) >> 7 +} +func (o *LCD_CAM_Type) SetLCD_CTRL2_LCD_DE_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x100)|value<<8) +} +func (o *LCD_CAM_Type) GetLCD_CTRL2_LCD_DE_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x100) >> 8 +} +func (o *LCD_CAM_Type) SetLCD_CTRL2_LCD_HS_BLANK_EN(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x200)|value<<9) +} +func (o *LCD_CAM_Type) GetLCD_CTRL2_LCD_HS_BLANK_EN() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x200) >> 9 +} +func (o *LCD_CAM_Type) SetLCD_CTRL2_LCD_HSYNC_WIDTH(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x7f0000)|value<<16) +} +func (o *LCD_CAM_Type) GetLCD_CTRL2_LCD_HSYNC_WIDTH() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x7f0000) >> 16 +} +func (o *LCD_CAM_Type) SetLCD_CTRL2_LCD_HSYNC_IDLE_POL(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x800000)|value<<23) +} +func (o *LCD_CAM_Type) GetLCD_CTRL2_LCD_HSYNC_IDLE_POL() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x800000) >> 23 +} +func (o *LCD_CAM_Type) SetLCD_CTRL2_LCD_HSYNC_POSITION(value uint32) { + volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0xff000000)|value<<24) +} +func (o *LCD_CAM_Type) GetLCD_CTRL2_LCD_HSYNC_POSITION() uint32 { + return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0xff000000) >> 24 +} + +// LCD_CAM.LCD_CMD_VAL: LCD configuration register +func (o *LCD_CAM_Type) SetLCD_CMD_VAL(value uint32) { + volatile.StoreUint32(&o.LCD_CMD_VAL.Reg, value) +} +func (o *LCD_CAM_Type) GetLCD_CMD_VAL() uint32 { + return volatile.LoadUint32(&o.LCD_CMD_VAL.Reg) +} + +// LCD_CAM.LCD_DLY_MODE: LCD configuration register +func (o *LCD_CAM_Type) SetLCD_DLY_MODE_LCD_CD_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE.Reg)&^(0x3)|value) +} +func (o *LCD_CAM_Type) GetLCD_DLY_MODE_LCD_CD_MODE() uint32 { + return volatile.LoadUint32(&o.LCD_DLY_MODE.Reg) & 0x3 +} +func (o *LCD_CAM_Type) SetLCD_DLY_MODE_LCD_DE_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE.Reg)&^(0xc)|value<<2) +} +func (o *LCD_CAM_Type) GetLCD_DLY_MODE_LCD_DE_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE.Reg) & 0xc) >> 2 +} +func (o *LCD_CAM_Type) SetLCD_DLY_MODE_LCD_HSYNC_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE.Reg)&^(0x30)|value<<4) +} +func (o *LCD_CAM_Type) GetLCD_DLY_MODE_LCD_HSYNC_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE.Reg) & 0x30) >> 4 +} +func (o *LCD_CAM_Type) SetLCD_DLY_MODE_LCD_VSYNC_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DLY_MODE.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *LCD_CAM_Type) GetLCD_DLY_MODE_LCD_VSYNC_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DLY_MODE.Reg) & 0xc0) >> 6 +} + +// LCD_CAM.LCD_DATA_DOUT_MODE: LCD configuration register +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0x3)|value) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0x3 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0xc)|value<<2) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0xc) >> 2 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0x30)|value<<4) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0x30) >> 4 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0xc0) >> 6 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0x300)|value<<8) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0x300) >> 8 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0xc00)|value<<10) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0xc00) >> 10 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0x3000)|value<<12) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0x3000) >> 12 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0xc000)|value<<14) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0xc000) >> 14 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT8_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0x30000)|value<<16) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT8_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0x30000) >> 16 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT9_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0xc0000)|value<<18) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT9_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0xc0000) >> 18 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT10_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0x300000)|value<<20) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT10_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0x300000) >> 20 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT11_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0xc00000)|value<<22) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT11_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0xc00000) >> 22 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT12_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0x3000000)|value<<24) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT12_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0x3000000) >> 24 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT13_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0xc000000)|value<<26) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT13_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0xc000000) >> 26 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT14_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0x30000000)|value<<28) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT14_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0x30000000) >> 28 +} +func (o *LCD_CAM_Type) SetLCD_DATA_DOUT_MODE_DOUT15_MODE(value uint32) { + volatile.StoreUint32(&o.LCD_DATA_DOUT_MODE.Reg, volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg)&^(0xc0000000)|value<<30) +} +func (o *LCD_CAM_Type) GetLCD_DATA_DOUT_MODE_DOUT15_MODE() uint32 { + return (volatile.LoadUint32(&o.LCD_DATA_DOUT_MODE.Reg) & 0xc0000000) >> 30 +} + +// LCD_CAM.LC_DMA_INT_ENA: LCD_camera DMA inturrupt enable register +func (o *LCD_CAM_Type) SetLC_DMA_INT_ENA_LCD_VSYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_ENA_LCD_VSYNC_INT_ENA() uint32 { + return volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x1 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_ENA_CAM_VSYNC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_ENA_CAM_VSYNC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_ENA_CAM_HS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_ENA_CAM_HS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x8) >> 3 +} + +// LCD_CAM.LC_DMA_INT_RAW: LCD_camera DMA raw inturrupt status register +func (o *LCD_CAM_Type) SetLC_DMA_INT_RAW_LCD_VSYNC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_RAW_LCD_VSYNC_INT_RAW() uint32 { + return volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x1 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_RAW_CAM_VSYNC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_RAW_CAM_VSYNC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_RAW_CAM_HS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_RAW_CAM_HS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x8) >> 3 +} + +// LCD_CAM.LC_DMA_INT_ST: LCD_camera DMA masked inturrupt status register +func (o *LCD_CAM_Type) SetLC_DMA_INT_ST_LCD_VSYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_ST_LCD_VSYNC_INT_ST() uint32 { + return volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x1 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_ST_CAM_VSYNC_INT_ST(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_ST_CAM_VSYNC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_ST_CAM_HS_INT_ST(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_ST_CAM_HS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x8) >> 3 +} + +// LCD_CAM.LC_DMA_INT_CLR: LCD_camera DMA inturrupt clear register +func (o *LCD_CAM_Type) SetLC_DMA_INT_CLR_LCD_VSYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_CLR_LCD_VSYNC_INT_CLR() uint32 { + return volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x1 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_CLR_CAM_VSYNC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_CLR_CAM_VSYNC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LCD_CAM_Type) SetLC_DMA_INT_CLR_CAM_HS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LCD_CAM_Type) GetLC_DMA_INT_CLR_CAM_HS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x8) >> 3 +} + +// LCD_CAM.LC_REG_DATE: Version register +func (o *LCD_CAM_Type) SetLC_REG_DATE_LC_DATE(value uint32) { + volatile.StoreUint32(&o.LC_REG_DATE.Reg, volatile.LoadUint32(&o.LC_REG_DATE.Reg)&^(0xfffffff)|value) +} +func (o *LCD_CAM_Type) GetLC_REG_DATE_LC_DATE() uint32 { + return volatile.LoadUint32(&o.LC_REG_DATE.Reg) & 0xfffffff +} + +// LED Control PWM (Pulse Width Modulation) +type LEDC_Type struct { + CH0_CONF0 volatile.Register32 // 0x0 + CH0_HPOINT volatile.Register32 // 0x4 + CH0_DUTY volatile.Register32 // 0x8 + CH0_CONF1 volatile.Register32 // 0xC + CH0_DUTY_R volatile.Register32 // 0x10 + CH1_CONF0 volatile.Register32 // 0x14 + CH1_HPOINT volatile.Register32 // 0x18 + CH1_DUTY volatile.Register32 // 0x1C + CH1_CONF1 volatile.Register32 // 0x20 + CH1_DUTY_R volatile.Register32 // 0x24 + CH2_CONF0 volatile.Register32 // 0x28 + CH2_HPOINT volatile.Register32 // 0x2C + CH2_DUTY volatile.Register32 // 0x30 + CH2_CONF1 volatile.Register32 // 0x34 + CH2_DUTY_R volatile.Register32 // 0x38 + CH3_CONF0 volatile.Register32 // 0x3C + CH3_HPOINT volatile.Register32 // 0x40 + CH3_DUTY volatile.Register32 // 0x44 + CH3_CONF1 volatile.Register32 // 0x48 + CH3_DUTY_R volatile.Register32 // 0x4C + CH4_CONF0 volatile.Register32 // 0x50 + CH4_HPOINT volatile.Register32 // 0x54 + CH4_DUTY volatile.Register32 // 0x58 + CH4_CONF1 volatile.Register32 // 0x5C + CH4_DUTY_R volatile.Register32 // 0x60 + CH5_CONF0 volatile.Register32 // 0x64 + CH5_HPOINT volatile.Register32 // 0x68 + CH5_DUTY volatile.Register32 // 0x6C + CH5_CONF1 volatile.Register32 // 0x70 + CH5_DUTY_R volatile.Register32 // 0x74 + CH6_CONF0 volatile.Register32 // 0x78 + CH6_HPOINT volatile.Register32 // 0x7C + CH6_DUTY volatile.Register32 // 0x80 + CH6_CONF1 volatile.Register32 // 0x84 + CH6_DUTY_R volatile.Register32 // 0x88 + CH7_CONF0 volatile.Register32 // 0x8C + CH7_HPOINT volatile.Register32 // 0x90 + CH7_DUTY volatile.Register32 // 0x94 + CH7_CONF1 volatile.Register32 // 0x98 + CH7_DUTY_R volatile.Register32 // 0x9C + TIMER0_CONF volatile.Register32 // 0xA0 + TIMER0_VALUE volatile.Register32 // 0xA4 + TIMER1_CONF volatile.Register32 // 0xA8 + TIMER1_VALUE volatile.Register32 // 0xAC + TIMER2_CONF volatile.Register32 // 0xB0 + TIMER2_VALUE volatile.Register32 // 0xB4 + TIMER3_CONF volatile.Register32 // 0xB8 + TIMER3_VALUE volatile.Register32 // 0xBC + INT_RAW volatile.Register32 // 0xC0 + INT_ST volatile.Register32 // 0xC4 + INT_ENA volatile.Register32 // 0xC8 + INT_CLR volatile.Register32 // 0xCC + CONF volatile.Register32 // 0xD0 + _ [40]byte + DATE volatile.Register32 // 0xFC +} + +// LEDC.CH0_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH0_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH0_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH0_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH0_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH0_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH0_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH0_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH0_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH0_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH0_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH0_HPOINT.Reg, volatile.LoadUint32(&o.CH0_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH0_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH0_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH0_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY.Reg, volatile.LoadUint32(&o.CH0_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH0_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH0_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH0_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH0_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH0_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH0_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH0_DUTY_R.Reg, volatile.LoadUint32(&o.CH0_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH0_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH0_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH1_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH1_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH1_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH1_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH1_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH1_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH1_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH1_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH1_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH1_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH1_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH1_HPOINT.Reg, volatile.LoadUint32(&o.CH1_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH1_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH1_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH1_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY.Reg, volatile.LoadUint32(&o.CH1_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH1_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH1_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH1_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH1_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH1_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH1_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH1_DUTY_R.Reg, volatile.LoadUint32(&o.CH1_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH1_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH1_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH2_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH2_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH2_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH2_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH2_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH2_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH2_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH2_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH2_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH2_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH2_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH2_HPOINT.Reg, volatile.LoadUint32(&o.CH2_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH2_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH2_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH2_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY.Reg, volatile.LoadUint32(&o.CH2_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH2_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH2_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH2_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH2_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH2_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH2_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH2_DUTY_R.Reg, volatile.LoadUint32(&o.CH2_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH2_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH2_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH3_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH3_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH3_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH3_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH3_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH3_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH3_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH3_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH3_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH3_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH3_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH3_HPOINT.Reg, volatile.LoadUint32(&o.CH3_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH3_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH3_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH3_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY.Reg, volatile.LoadUint32(&o.CH3_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH3_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH3_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH3_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH3_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH3_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH3_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH3_DUTY_R.Reg, volatile.LoadUint32(&o.CH3_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH3_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH3_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH4_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH4_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH4_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH4_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH4_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH4_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH4_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH4_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH4_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH4_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH4_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH4_HPOINT.Reg, volatile.LoadUint32(&o.CH4_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH4_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH4_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH4_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY.Reg, volatile.LoadUint32(&o.CH4_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH4_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH4_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH4_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH4_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH4_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH4_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH4_DUTY_R.Reg, volatile.LoadUint32(&o.CH4_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH4_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH4_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH5_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH5_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH5_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH5_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH5_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH5_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH5_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH5_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH5_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH5_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH5_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH5_HPOINT.Reg, volatile.LoadUint32(&o.CH5_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH5_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH5_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH5_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY.Reg, volatile.LoadUint32(&o.CH5_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH5_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH5_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH5_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH5_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH5_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH5_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH5_DUTY_R.Reg, volatile.LoadUint32(&o.CH5_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH5_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH5_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH6_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH6_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH6_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH6_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH6_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH6_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH6_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH6_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH6_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH6_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH6_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH6_HPOINT.Reg, volatile.LoadUint32(&o.CH6_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH6_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH6_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH6_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH6_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH6_DUTY.Reg, volatile.LoadUint32(&o.CH6_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH6_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH6_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH6_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH6_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH6_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH6_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH6_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH6_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH6_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH6_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH6_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH6_DUTY_R.Reg, volatile.LoadUint32(&o.CH6_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH6_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH6_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.CH7_CONF0: Configuration register 0 for channel %s +func (o *LEDC_Type) SetCH7_CONF0_TIMER_SEL(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCH7_CONF0_TIMER_SEL() uint32 { + return volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x3 +} +func (o *LEDC_Type) SetCH7_CONF0_SIG_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetCH7_CONF0_SIG_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetCH7_CONF0_IDLE_LV(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetCH7_CONF0_IDLE_LV() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetCH7_CONF0_PARA_UP(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetCH7_CONF0_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_NUM(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x7fe0)|value<<5) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_NUM() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x7fe0) >> 5 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_RESET_ST(value uint32) { + volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_RESET_ST() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x20000) >> 17 +} + +// LEDC.CH7_HPOINT: High point register for channel %s +func (o *LEDC_Type) SetCH7_HPOINT_HPOINT(value uint32) { + volatile.StoreUint32(&o.CH7_HPOINT.Reg, volatile.LoadUint32(&o.CH7_HPOINT.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetCH7_HPOINT_HPOINT() uint32 { + return volatile.LoadUint32(&o.CH7_HPOINT.Reg) & 0x3fff +} + +// LEDC.CH7_DUTY: Initial duty cycle for channel %s +func (o *LEDC_Type) SetCH7_DUTY_DUTY(value uint32) { + volatile.StoreUint32(&o.CH7_DUTY.Reg, volatile.LoadUint32(&o.CH7_DUTY.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH7_DUTY_DUTY() uint32 { + return volatile.LoadUint32(&o.CH7_DUTY.Reg) & 0x7ffff +} + +// LEDC.CH7_CONF1: Configuration register 1 for channel %s +func (o *LEDC_Type) SetCH7_CONF1_DUTY_SCALE(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x3ff)|value) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_SCALE() uint32 { + return volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x3ff +} +func (o *LEDC_Type) SetCH7_CONF1_DUTY_CYCLE(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_CYCLE() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0xffc00) >> 10 +} +func (o *LEDC_Type) SetCH7_CONF1_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x3ff00000)|value<<20) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_NUM() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x3ff00000) >> 20 +} +func (o *LEDC_Type) SetCH7_CONF1_DUTY_INC(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x40000000)|value<<30) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_INC() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x40000000) >> 30 +} +func (o *LEDC_Type) SetCH7_CONF1_DUTY_START(value uint32) { + volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCH7_CONF1_DUTY_START() uint32 { + return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x80000000) >> 31 +} + +// LEDC.CH7_DUTY_R: Current duty cycle for channel %s +func (o *LEDC_Type) SetCH7_DUTY_R_DUTY_R(value uint32) { + volatile.StoreUint32(&o.CH7_DUTY_R.Reg, volatile.LoadUint32(&o.CH7_DUTY_R.Reg)&^(0x7ffff)|value) +} +func (o *LEDC_Type) GetCH7_DUTY_R_DUTY_R() uint32 { + return volatile.LoadUint32(&o.CH7_DUTY_R.Reg) & 0x7ffff +} + +// LEDC.TIMER0_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER0_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER0_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER0_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER0_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER0_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER0_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER0_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER0_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER0_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER0_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER0_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER0_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER0_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER0_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER0_VALUE.Reg, volatile.LoadUint32(&o.TIMER0_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER0_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER0_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER1_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER1_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER1_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER1_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER1_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER1_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER1_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER1_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER1_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER1_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER1_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER1_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER1_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER1_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER1_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER1_VALUE.Reg, volatile.LoadUint32(&o.TIMER1_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER1_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER1_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER2_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER2_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER2_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER2_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER2_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER2_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER2_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER2_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER2_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER2_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER2_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER2_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER2_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER2_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER2_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER2_VALUE.Reg, volatile.LoadUint32(&o.TIMER2_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER2_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER2_VALUE.Reg) & 0x3fff +} + +// LEDC.TIMER3_CONF: Timer %s configuration +func (o *LEDC_Type) SetTIMER3_CONF_DUTY_RES(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0xf)|value) +} +func (o *LEDC_Type) GetTIMER3_CONF_DUTY_RES() uint32 { + return volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0xf +} +func (o *LEDC_Type) SetTIMER3_CONF_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x3ffff0)|value<<4) +} +func (o *LEDC_Type) GetTIMER3_CONF_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x3ffff0) >> 4 +} +func (o *LEDC_Type) SetTIMER3_CONF_PAUSE(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *LEDC_Type) GetTIMER3_CONF_PAUSE() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x400000) >> 22 +} +func (o *LEDC_Type) SetTIMER3_CONF_RST(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *LEDC_Type) GetTIMER3_CONF_RST() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x800000) >> 23 +} +func (o *LEDC_Type) SetTIMER3_CONF_TICK_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *LEDC_Type) GetTIMER3_CONF_TICK_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1000000) >> 24 +} +func (o *LEDC_Type) SetTIMER3_CONF_PARA_UP(value uint32) { + volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *LEDC_Type) GetTIMER3_CONF_PARA_UP() uint32 { + return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x2000000) >> 25 +} + +// LEDC.TIMER3_VALUE: Timer %s current counter value +func (o *LEDC_Type) SetTIMER3_VALUE_CNT(value uint32) { + volatile.StoreUint32(&o.TIMER3_VALUE.Reg, volatile.LoadUint32(&o.TIMER3_VALUE.Reg)&^(0x3fff)|value) +} +func (o *LEDC_Type) GetTIMER3_VALUE_CNT() uint32 { + return volatile.LoadUint32(&o.TIMER3_VALUE.Reg) & 0x3fff +} + +// LEDC.INT_RAW: Raw interrupt status +func (o *LEDC_Type) SetINT_RAW_TIMER0_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_RAW_TIMER0_OVF_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER1_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_RAW_TIMER1_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_RAW_TIMER2_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_RAW_TIMER2_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_RAW_TIMER3_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_RAW_TIMER3_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// LEDC.INT_ST: Masked interrupt status +func (o *LEDC_Type) SetINT_ST_TIMER0_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ST_TIMER0_OVF_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ST_TIMER1_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ST_TIMER1_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ST_TIMER2_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ST_TIMER2_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ST_TIMER3_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ST_TIMER3_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH6_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH7_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH3_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH4_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH5_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH6_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH7_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// LEDC.INT_ENA: Interrupt enable bits +func (o *LEDC_Type) SetINT_ENA_TIMER0_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_ENA_TIMER0_OVF_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER1_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_ENA_TIMER1_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_ENA_TIMER2_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_ENA_TIMER2_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_ENA_TIMER3_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_ENA_TIMER3_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// LEDC.INT_CLR: Interrupt clear bits +func (o *LEDC_Type) SetINT_CLR_TIMER0_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *LEDC_Type) GetINT_CLR_TIMER0_OVF_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER1_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *LEDC_Type) GetINT_CLR_TIMER1_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *LEDC_Type) SetINT_CLR_TIMER2_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *LEDC_Type) GetINT_CLR_TIMER2_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *LEDC_Type) SetINT_CLR_TIMER3_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *LEDC_Type) GetINT_CLR_TIMER3_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// LEDC.CONF: Global ledc configuration register +func (o *LEDC_Type) SetCONF_APB_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value) +} +func (o *LEDC_Type) GetCONF_APB_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x3 +} +func (o *LEDC_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *LEDC_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// LEDC.DATE: Version control register +func (o *LEDC_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *LEDC_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Pulse Count Controller +type PCNT_Type struct { + U0_CONF0 volatile.Register32 // 0x0 + U0_CONF1 volatile.Register32 // 0x4 + U0_CONF2 volatile.Register32 // 0x8 + U1_CONF0 volatile.Register32 // 0xC + U1_CONF1 volatile.Register32 // 0x10 + U1_CONF2 volatile.Register32 // 0x14 + U2_CONF0 volatile.Register32 // 0x18 + U2_CONF1 volatile.Register32 // 0x1C + U2_CONF2 volatile.Register32 // 0x20 + U3_CONF0 volatile.Register32 // 0x24 + U3_CONF1 volatile.Register32 // 0x28 + U3_CONF2 volatile.Register32 // 0x2C + U0_CNT volatile.Register32 // 0x30 + U1_CNT volatile.Register32 // 0x34 + U2_CNT volatile.Register32 // 0x38 + U3_CNT volatile.Register32 // 0x3C + INT_RAW volatile.Register32 // 0x40 + INT_ST volatile.Register32 // 0x44 + INT_ENA volatile.Register32 // 0x48 + INT_CLR volatile.Register32 // 0x4C + U0_STATUS volatile.Register32 // 0x50 + U1_STATUS volatile.Register32 // 0x54 + U2_STATUS volatile.Register32 // 0x58 + U3_STATUS volatile.Register32 // 0x5C + CTRL volatile.Register32 // 0x60 + _ [152]byte + DATE volatile.Register32 // 0xFC +} + +// PCNT.U0_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU0_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU0_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU0_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU0_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU0_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU0_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU0_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU0_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU0_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU0_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU0_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU0_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU0_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU0_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU0_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U0_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU0_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU0_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU0_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU1_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU1_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU1_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU1_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU1_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU1_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU1_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU1_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU1_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU1_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU1_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU1_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU1_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU1_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU1_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U1_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U1_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU1_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU1_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU1_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU2_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU2_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU2_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU2_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU2_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU2_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU2_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU2_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU2_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU2_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU2_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU2_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU2_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU2_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU2_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U2_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U2_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU2_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU2_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU2_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF0: Configuration register 0 for unit %s +func (o *PCNT_Type) SetU3_CONF0_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3ff)|value) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_THRES() uint32 { + return volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3ff +} +func (o *PCNT_Type) SetU3_CONF0_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x400)|value<<10) +} +func (o *PCNT_Type) GetU3_CONF0_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x400) >> 10 +} +func (o *PCNT_Type) SetU3_CONF0_THR_ZERO_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x800)|value<<11) +} +func (o *PCNT_Type) GetU3_CONF0_THR_ZERO_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x800) >> 11 +} +func (o *PCNT_Type) SetU3_CONF0_THR_H_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *PCNT_Type) GetU3_CONF0_THR_H_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x1000) >> 12 +} +func (o *PCNT_Type) SetU3_CONF0_THR_L_LIM_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *PCNT_Type) GetU3_CONF0_THR_L_LIM_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x2000) >> 13 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES0_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES0_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x4000) >> 14 +} +func (o *PCNT_Type) SetU3_CONF0_THR_THRES1_EN(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *PCNT_Type) GetU3_CONF0_THR_THRES1_EN() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x8000) >> 15 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000) >> 16 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000)|value<<18) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000) >> 18 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x300000)|value<<20) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x300000) >> 20 +} +func (o *PCNT_Type) SetU3_CONF0_CH0_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc00000)|value<<22) +} +func (o *PCNT_Type) GetU3_CONF0_CH0_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc00000) >> 22 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_NEG_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3000000)|value<<24) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_NEG_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3000000) >> 24 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_POS_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc000000)|value<<26) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_POS_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc000000) >> 26 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_HCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000000)|value<<28) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_HCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000000) >> 28 +} +func (o *PCNT_Type) SetU3_CONF0_CH1_LCTRL_MODE(value uint32) { + volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000000)|value<<30) +} +func (o *PCNT_Type) GetU3_CONF0_CH1_LCTRL_MODE() uint32 { + return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000000) >> 30 +} + +// PCNT.U3_CONF1: Configuration register 1 for unit %s +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES0() uint32 { + return volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF1_CNT_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF1_CNT_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U3_CONF2: Configuration register 2 for unit %s +func (o *PCNT_Type) SetU3_CONF2_CNT_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_H_LIM() uint32 { + return volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff +} +func (o *PCNT_Type) SetU3_CONF2_CNT_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *PCNT_Type) GetU3_CONF2_CNT_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff0000) >> 16 +} + +// PCNT.U0_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU0_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U0_CNT.Reg, volatile.LoadUint32(&o.U0_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU0_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U0_CNT.Reg) & 0xffff +} + +// PCNT.U1_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU1_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U1_CNT.Reg, volatile.LoadUint32(&o.U1_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU1_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U1_CNT.Reg) & 0xffff +} + +// PCNT.U2_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU2_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U2_CNT.Reg, volatile.LoadUint32(&o.U2_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU2_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U2_CNT.Reg) & 0xffff +} + +// PCNT.U3_CNT: Counter value for unit %s +func (o *PCNT_Type) SetU3_CNT_CNT(value uint32) { + volatile.StoreUint32(&o.U3_CNT.Reg, volatile.LoadUint32(&o.U3_CNT.Reg)&^(0xffff)|value) +} +func (o *PCNT_Type) GetU3_CNT_CNT() uint32 { + return volatile.LoadUint32(&o.U3_CNT.Reg) & 0xffff +} + +// PCNT.INT_RAW: Interrupt raw status register +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ST: Interrupt status register +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// PCNT.INT_ENA: Interrupt enable register +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// PCNT.INT_CLR: Interrupt clear register +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U0(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U0() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U1(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U1() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U2(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U2() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U3(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U3() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// PCNT.U0_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU0_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU0_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU0_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU0_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU0_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU0_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU0_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU0_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU0_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU0_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU0_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U1_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU1_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU1_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU1_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU1_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU1_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU1_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU1_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU1_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU1_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU1_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU1_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U2_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU2_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU2_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU2_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU2_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU2_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU2_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU2_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU2_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU2_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU2_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU2_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.U3_STATUS: PNCT UNIT%s status register +func (o *PCNT_Type) SetU3_STATUS_ZERO_MODE(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x3)|value) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO_MODE() uint32 { + return volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x3 +} +func (o *PCNT_Type) SetU3_STATUS_THRES1(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetU3_STATUS_THRES1() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetU3_STATUS_THRES0(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetU3_STATUS_THRES0() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetU3_STATUS_L_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetU3_STATUS_L_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetU3_STATUS_H_LIM(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetU3_STATUS_H_LIM() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetU3_STATUS_ZERO(value uint32) { + volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetU3_STATUS_ZERO() uint32 { + return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x40) >> 6 +} + +// PCNT.CTRL: Control register for all counters +func (o *PCNT_Type) SetCTRL_CNT_RST_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U0() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U0(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U0() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U1(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U1() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U2(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U2() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *PCNT_Type) SetCTRL_CNT_RST_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *PCNT_Type) GetCTRL_CNT_RST_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U3(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U3() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *PCNT_Type) SetCTRL_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *PCNT_Type) GetCTRL_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} + +// PCNT.DATE: PCNT version control register +func (o *PCNT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *PCNT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// PERI_BACKUP Peripheral +type PERI_BACKUP_Type struct { + CONFIG volatile.Register32 // 0x0 + APB_ADDR volatile.Register32 // 0x4 + MEM_ADDR volatile.Register32 // 0x8 + REG_MAP0 volatile.Register32 // 0xC + REG_MAP1 volatile.Register32 // 0x10 + REG_MAP2 volatile.Register32 // 0x14 + REG_MAP3 volatile.Register32 // 0x18 + INT_RAW volatile.Register32 // 0x1C + INT_ST volatile.Register32 // 0x20 + INT_ENA volatile.Register32 // 0x24 + INT_CLR volatile.Register32 // 0x28 + _ [208]byte + DATE volatile.Register32 // 0xFC +} + +// PERI_BACKUP.CONFIG: x +func (o *PERI_BACKUP_Type) SetCONFIG_FLOW_ERR(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x7)|value) +} +func (o *PERI_BACKUP_Type) GetCONFIG_FLOW_ERR() uint32 { + return volatile.LoadUint32(&o.CONFIG.Reg) & 0x7 +} +func (o *PERI_BACKUP_Type) SetCONFIG_ADDR_MAP_MODE(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8)|value<<3) +} +func (o *PERI_BACKUP_Type) GetCONFIG_ADDR_MAP_MODE() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8) >> 3 +} +func (o *PERI_BACKUP_Type) SetCONFIG_BURST_LIMIT(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1f0)|value<<4) +} +func (o *PERI_BACKUP_Type) GetCONFIG_BURST_LIMIT() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x1f0) >> 4 +} +func (o *PERI_BACKUP_Type) SetCONFIG_TOUT_THRES(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x7fe00)|value<<9) +} +func (o *PERI_BACKUP_Type) GetCONFIG_TOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x7fe00) >> 9 +} +func (o *PERI_BACKUP_Type) SetCONFIG_SIZE(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1ff80000)|value<<19) +} +func (o *PERI_BACKUP_Type) GetCONFIG_SIZE() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x1ff80000) >> 19 +} +func (o *PERI_BACKUP_Type) SetCONFIG_START(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *PERI_BACKUP_Type) GetCONFIG_START() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *PERI_BACKUP_Type) SetCONFIG_TO_MEM(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *PERI_BACKUP_Type) GetCONFIG_TO_MEM() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *PERI_BACKUP_Type) SetCONFIG_ENA(value uint32) { + volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *PERI_BACKUP_Type) GetCONFIG_ENA() uint32 { + return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x80000000) >> 31 +} + +// PERI_BACKUP.APB_ADDR: x +func (o *PERI_BACKUP_Type) SetAPB_ADDR(value uint32) { + volatile.StoreUint32(&o.APB_ADDR.Reg, value) +} +func (o *PERI_BACKUP_Type) GetAPB_ADDR() uint32 { + return volatile.LoadUint32(&o.APB_ADDR.Reg) +} + +// PERI_BACKUP.MEM_ADDR: x +func (o *PERI_BACKUP_Type) SetMEM_ADDR(value uint32) { + volatile.StoreUint32(&o.MEM_ADDR.Reg, value) +} +func (o *PERI_BACKUP_Type) GetMEM_ADDR() uint32 { + return volatile.LoadUint32(&o.MEM_ADDR.Reg) +} + +// PERI_BACKUP.REG_MAP0: x +func (o *PERI_BACKUP_Type) SetREG_MAP0(value uint32) { + volatile.StoreUint32(&o.REG_MAP0.Reg, value) +} +func (o *PERI_BACKUP_Type) GetREG_MAP0() uint32 { + return volatile.LoadUint32(&o.REG_MAP0.Reg) +} + +// PERI_BACKUP.REG_MAP1: x +func (o *PERI_BACKUP_Type) SetREG_MAP1(value uint32) { + volatile.StoreUint32(&o.REG_MAP1.Reg, value) +} +func (o *PERI_BACKUP_Type) GetREG_MAP1() uint32 { + return volatile.LoadUint32(&o.REG_MAP1.Reg) +} + +// PERI_BACKUP.REG_MAP2: x +func (o *PERI_BACKUP_Type) SetREG_MAP2(value uint32) { + volatile.StoreUint32(&o.REG_MAP2.Reg, value) +} +func (o *PERI_BACKUP_Type) GetREG_MAP2() uint32 { + return volatile.LoadUint32(&o.REG_MAP2.Reg) +} + +// PERI_BACKUP.REG_MAP3: x +func (o *PERI_BACKUP_Type) SetREG_MAP3(value uint32) { + volatile.StoreUint32(&o.REG_MAP3.Reg, value) +} +func (o *PERI_BACKUP_Type) GetREG_MAP3() uint32 { + return volatile.LoadUint32(&o.REG_MAP3.Reg) +} + +// PERI_BACKUP.INT_RAW: x +func (o *PERI_BACKUP_Type) SetINT_RAW_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PERI_BACKUP_Type) GetINT_RAW_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PERI_BACKUP_Type) SetINT_RAW_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PERI_BACKUP_Type) GetINT_RAW_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} + +// PERI_BACKUP.INT_ST: x +func (o *PERI_BACKUP_Type) SetINT_ST_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PERI_BACKUP_Type) GetINT_ST_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PERI_BACKUP_Type) SetINT_ST_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PERI_BACKUP_Type) GetINT_ST_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} + +// PERI_BACKUP.INT_ENA: x +func (o *PERI_BACKUP_Type) SetINT_ENA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PERI_BACKUP_Type) GetINT_ENA_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PERI_BACKUP_Type) SetINT_ENA_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PERI_BACKUP_Type) GetINT_ENA_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} + +// PERI_BACKUP.INT_CLR: x +func (o *PERI_BACKUP_Type) SetINT_CLR_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PERI_BACKUP_Type) GetINT_CLR_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PERI_BACKUP_Type) SetINT_CLR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PERI_BACKUP_Type) GetINT_CLR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} + +// PERI_BACKUP.DATE: x +func (o *PERI_BACKUP_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *PERI_BACKUP_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} +func (o *PERI_BACKUP_Type) SetDATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31) +} +func (o *PERI_BACKUP_Type) GetDATE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31 +} + +// Motor Control Pulse-Width Modulation 0 +type PWM_Type struct { + CLK_CFG volatile.Register32 // 0x0 + TIMER0_CFG0 volatile.Register32 // 0x4 + TIMER0_CFG1 volatile.Register32 // 0x8 + TIMER0_SYNC volatile.Register32 // 0xC + TIMER0_STATUS volatile.Register32 // 0x10 + TIMER1_CFG0 volatile.Register32 // 0x14 + TIMER1_CFG1 volatile.Register32 // 0x18 + TIMER1_SYNC volatile.Register32 // 0x1C + TIMER1_STATUS volatile.Register32 // 0x20 + TIMER2_CFG0 volatile.Register32 // 0x24 + TIMER2_CFG1 volatile.Register32 // 0x28 + TIMER2_SYNC volatile.Register32 // 0x2C + TIMER2_STATUS volatile.Register32 // 0x30 + TIMER_SYNCI_CFG volatile.Register32 // 0x34 + OPERATOR_TIMERSEL volatile.Register32 // 0x38 + CMPR0_CFG volatile.Register32 // 0x3C + CMPR0_VALUE0 volatile.Register32 // 0x40 + CMPR0_VALUE1 volatile.Register32 // 0x44 + GEN0_CFG0 volatile.Register32 // 0x48 + GEN0_FORCE volatile.Register32 // 0x4C + GEN0_A volatile.Register32 // 0x50 + GEN0_B volatile.Register32 // 0x54 + DB0_CFG volatile.Register32 // 0x58 + DB0_FED_CFG volatile.Register32 // 0x5C + DB0_RED_CFG volatile.Register32 // 0x60 + CHOPPER0_CFG volatile.Register32 // 0x64 + TZ0_CFG0 volatile.Register32 // 0x68 + TZ0_CFG1 volatile.Register32 // 0x6C + TZ0_STATUS volatile.Register32 // 0x70 + CMPR1_CFG volatile.Register32 // 0x74 + CMPR1_VALUE0 volatile.Register32 // 0x78 + CMPR1_VALUE1 volatile.Register32 // 0x7C + GEN1_CFG0 volatile.Register32 // 0x80 + GEN1_FORCE volatile.Register32 // 0x84 + GEN1_A volatile.Register32 // 0x88 + GEN1_B volatile.Register32 // 0x8C + DB1_CFG volatile.Register32 // 0x90 + DB1_FED_CFG volatile.Register32 // 0x94 + DB1_RED_CFG volatile.Register32 // 0x98 + CHOPPER1_CFG volatile.Register32 // 0x9C + TZ1_CFG0 volatile.Register32 // 0xA0 + TZ1_CFG1 volatile.Register32 // 0xA4 + TZ1_STATUS volatile.Register32 // 0xA8 + CMPR2_CFG volatile.Register32 // 0xAC + CMPR2_VALUE0 volatile.Register32 // 0xB0 + CMPR2_VALUE1 volatile.Register32 // 0xB4 + GEN2_CFG0 volatile.Register32 // 0xB8 + GEN2_FORCE volatile.Register32 // 0xBC + GEN2_A volatile.Register32 // 0xC0 + GEN2_B volatile.Register32 // 0xC4 + DB2_CFG volatile.Register32 // 0xC8 + DB2_FED_CFG volatile.Register32 // 0xCC + DB2_RED_CFG volatile.Register32 // 0xD0 + CHOPPER2_CFG volatile.Register32 // 0xD4 + TZ2_CFG0 volatile.Register32 // 0xD8 + TZ2_CFG1 volatile.Register32 // 0xDC + TZ2_STATUS volatile.Register32 // 0xE0 + FAULT_DETECT volatile.Register32 // 0xE4 + CAP_TIMER_CFG volatile.Register32 // 0xE8 + CAP_TIMER_PHASE volatile.Register32 // 0xEC + CAP_CH0_CFG volatile.Register32 // 0xF0 + CAP_CH1_CFG volatile.Register32 // 0xF4 + CAP_CH2_CFG volatile.Register32 // 0xF8 + CAP_CH0 volatile.Register32 // 0xFC + CAP_CH1 volatile.Register32 // 0x100 + CAP_CH2 volatile.Register32 // 0x104 + CAP_STATUS volatile.Register32 // 0x108 + UPDATE_CFG volatile.Register32 // 0x10C + INT_ENA volatile.Register32 // 0x110 + INT_RAW volatile.Register32 // 0x114 + INT_ST volatile.Register32 // 0x118 + INT_CLR volatile.Register32 // 0x11C + CLK volatile.Register32 // 0x120 + VERSION volatile.Register32 // 0x124 +} + +// PWM.CLK_CFG: PWM clock prescaler register. +func (o *PWM_Type) SetCLK_CFG_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0xff)|value) +} +func (o *PWM_Type) GetCLK_CFG_CLK_PRESCALE() uint32 { + return volatile.LoadUint32(&o.CLK_CFG.Reg) & 0xff +} + +// PWM.TIMER0_CFG0: PWM timer0 period and update method configuration register. +func (o *PWM_Type) SetTIMER0_CFG0_TIMER0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xff)|value) +} +func (o *PWM_Type) GetTIMER0_CFG0_TIMER0_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xff +} +func (o *PWM_Type) SetTIMER0_CFG0_TIMER0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *PWM_Type) GetTIMER0_CFG0_TIMER0_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *PWM_Type) SetTIMER0_CFG0_TIMER0_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *PWM_Type) GetTIMER0_CFG0_TIMER0_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0x3000000) >> 24 +} + +// PWM.TIMER0_CFG1: PWM timer0 working mode and start/stop control configuration register. +func (o *PWM_Type) SetTIMER0_CFG1_TIMER0_START(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x7)|value) +} +func (o *PWM_Type) GetTIMER0_CFG1_TIMER0_START() uint32 { + return volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x7 +} +func (o *PWM_Type) SetTIMER0_CFG1_TIMER0_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *PWM_Type) GetTIMER0_CFG1_TIMER0_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x18) >> 3 +} + +// PWM.TIMER0_SYNC: PWM timer0 sync function configuration register. +func (o *PWM_Type) SetTIMER0_SYNC_TIMER0_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTIMER0_SYNC_TIMER0_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x1 +} +func (o *PWM_Type) SetTIMER0_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetTIMER0_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetTIMER0_SYNC_TIMER0_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetTIMER0_SYNC_TIMER0_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetTIMER0_SYNC_TIMER0_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *PWM_Type) GetTIMER0_SYNC_TIMER0_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *PWM_Type) SetTIMER0_SYNC_TIMER0_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *PWM_Type) GetTIMER0_SYNC_TIMER0_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x100000) >> 20 +} + +// PWM.TIMER0_STATUS: PWM timer0 status register. +func (o *PWM_Type) SetTIMER0_STATUS_TIMER0_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetTIMER0_STATUS_TIMER0_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0xffff +} +func (o *PWM_Type) SetTIMER0_STATUS_TIMER0_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetTIMER0_STATUS_TIMER0_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0x10000) >> 16 +} + +// PWM.TIMER1_CFG0: PWM timer1 period and update method configuration register. +func (o *PWM_Type) SetTIMER1_CFG0_TIMER1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xff)|value) +} +func (o *PWM_Type) GetTIMER1_CFG0_TIMER1_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xff +} +func (o *PWM_Type) SetTIMER1_CFG0_TIMER1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *PWM_Type) GetTIMER1_CFG0_TIMER1_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *PWM_Type) SetTIMER1_CFG0_TIMER1_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *PWM_Type) GetTIMER1_CFG0_TIMER1_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0x3000000) >> 24 +} + +// PWM.TIMER1_CFG1: PWM timer1 working mode and start/stop control configuration register. +func (o *PWM_Type) SetTIMER1_CFG1_TIMER1_START(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x7)|value) +} +func (o *PWM_Type) GetTIMER1_CFG1_TIMER1_START() uint32 { + return volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x7 +} +func (o *PWM_Type) SetTIMER1_CFG1_TIMER1_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *PWM_Type) GetTIMER1_CFG1_TIMER1_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x18) >> 3 +} + +// PWM.TIMER1_SYNC: PWM timer1 sync function configuration register. +func (o *PWM_Type) SetTIMER1_SYNC_TIMER1_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTIMER1_SYNC_TIMER1_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x1 +} +func (o *PWM_Type) SetTIMER1_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetTIMER1_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetTIMER1_SYNC_TIMER1_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetTIMER1_SYNC_TIMER1_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetTIMER1_SYNC_TIMER1_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *PWM_Type) GetTIMER1_SYNC_TIMER1_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *PWM_Type) SetTIMER1_SYNC_TIMER1_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *PWM_Type) GetTIMER1_SYNC_TIMER1_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x100000) >> 20 +} + +// PWM.TIMER1_STATUS: PWM timer1 status register. +func (o *PWM_Type) SetTIMER1_STATUS_TIMER1_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetTIMER1_STATUS_TIMER1_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0xffff +} +func (o *PWM_Type) SetTIMER1_STATUS_TIMER1_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetTIMER1_STATUS_TIMER1_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0x10000) >> 16 +} + +// PWM.TIMER2_CFG0: PWM timer2 period and update method configuration register. +func (o *PWM_Type) SetTIMER2_CFG0_TIMER2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xff)|value) +} +func (o *PWM_Type) GetTIMER2_CFG0_TIMER2_PRESCALE() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xff +} +func (o *PWM_Type) SetTIMER2_CFG0_TIMER2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xffff00)|value<<8) +} +func (o *PWM_Type) GetTIMER2_CFG0_TIMER2_PERIOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xffff00) >> 8 +} +func (o *PWM_Type) SetTIMER2_CFG0_TIMER2_PERIOD_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0x3000000)|value<<24) +} +func (o *PWM_Type) GetTIMER2_CFG0_TIMER2_PERIOD_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0x3000000) >> 24 +} + +// PWM.TIMER2_CFG1: PWM timer2 working mode and start/stop control configuration register. +func (o *PWM_Type) SetTIMER2_CFG1_TIMER2_START(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x7)|value) +} +func (o *PWM_Type) GetTIMER2_CFG1_TIMER2_START() uint32 { + return volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x7 +} +func (o *PWM_Type) SetTIMER2_CFG1_TIMER2_MOD(value uint32) { + volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x18)|value<<3) +} +func (o *PWM_Type) GetTIMER2_CFG1_TIMER2_MOD() uint32 { + return (volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x18) >> 3 +} + +// PWM.TIMER2_SYNC: PWM timer2 sync function configuration register. +func (o *PWM_Type) SetTIMER2_SYNC_TIMER2_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTIMER2_SYNC_TIMER2_SYNCI_EN() uint32 { + return volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x1 +} +func (o *PWM_Type) SetTIMER2_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetTIMER2_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetTIMER2_SYNC_TIMER2_SYNCO_SEL(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetTIMER2_SYNC_TIMER2_SYNCO_SEL() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetTIMER2_SYNC_TIMER2_PHASE(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xffff0)|value<<4) +} +func (o *PWM_Type) GetTIMER2_SYNC_TIMER2_PHASE() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xffff0) >> 4 +} +func (o *PWM_Type) SetTIMER2_SYNC_TIMER2_PHASE_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x100000)|value<<20) +} +func (o *PWM_Type) GetTIMER2_SYNC_TIMER2_PHASE_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x100000) >> 20 +} + +// PWM.TIMER2_STATUS: PWM timer2 status register. +func (o *PWM_Type) SetTIMER2_STATUS_TIMER2_VALUE(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetTIMER2_STATUS_TIMER2_VALUE() uint32 { + return volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0xffff +} +func (o *PWM_Type) SetTIMER2_STATUS_TIMER2_DIRECTION(value uint32) { + volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetTIMER2_STATUS_TIMER2_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0x10000) >> 16 +} + +// PWM.TIMER_SYNCI_CFG: Synchronization input selection for three PWM timers. +func (o *PWM_Type) SetTIMER_SYNCI_CFG_TIMER0_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x7)|value) +} +func (o *PWM_Type) GetTIMER_SYNCI_CFG_TIMER0_SYNCISEL() uint32 { + return volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x7 +} +func (o *PWM_Type) SetTIMER_SYNCI_CFG_TIMER1_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x38)|value<<3) +} +func (o *PWM_Type) GetTIMER_SYNCI_CFG_TIMER1_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x38) >> 3 +} +func (o *PWM_Type) SetTIMER_SYNCI_CFG_TIMER2_SYNCISEL(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x1c0)|value<<6) +} +func (o *PWM_Type) GetTIMER_SYNCI_CFG_TIMER2_SYNCISEL() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x1c0) >> 6 +} +func (o *PWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x200) >> 9 +} +func (o *PWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT(value uint32) { + volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT() uint32 { + return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x800) >> 11 +} + +// PWM.OPERATOR_TIMERSEL: Select specific timer for PWM operators. +func (o *PWM_Type) SetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x3)|value) +} +func (o *PWM_Type) GetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL() uint32 { + return volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x3 +} +func (o *PWM_Type) SetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL(value uint32) { + volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x30)|value<<4) +} +func (o *PWM_Type) GetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL() uint32 { + return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x30) >> 4 +} + +// PWM.CMPR0_CFG: Transfer status and update method for time stamp registers A and B +func (o *PWM_Type) SetCMPR0_CFG_CMPR0_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.CMPR0_CFG.Reg, volatile.LoadUint32(&o.CMPR0_CFG.Reg)&^(0xf)|value) +} +func (o *PWM_Type) GetCMPR0_CFG_CMPR0_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.CMPR0_CFG.Reg) & 0xf +} +func (o *PWM_Type) SetCMPR0_CFG_CMPR0_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.CMPR0_CFG.Reg, volatile.LoadUint32(&o.CMPR0_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *PWM_Type) GetCMPR0_CFG_CMPR0_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.CMPR0_CFG.Reg) & 0xf0) >> 4 +} +func (o *PWM_Type) SetCMPR0_CFG_CMPR0_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.CMPR0_CFG.Reg, volatile.LoadUint32(&o.CMPR0_CFG.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetCMPR0_CFG_CMPR0_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.CMPR0_CFG.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetCMPR0_CFG_CMPR0_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.CMPR0_CFG.Reg, volatile.LoadUint32(&o.CMPR0_CFG.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetCMPR0_CFG_CMPR0_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.CMPR0_CFG.Reg) & 0x200) >> 9 +} + +// PWM.CMPR0_VALUE0: Shadow register for register A. +func (o *PWM_Type) SetCMPR0_VALUE0_CMPR0_A(value uint32) { + volatile.StoreUint32(&o.CMPR0_VALUE0.Reg, volatile.LoadUint32(&o.CMPR0_VALUE0.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetCMPR0_VALUE0_CMPR0_A() uint32 { + return volatile.LoadUint32(&o.CMPR0_VALUE0.Reg) & 0xffff +} + +// PWM.CMPR0_VALUE1: Shadow register for register B. +func (o *PWM_Type) SetCMPR0_VALUE1_CMPR0_B(value uint32) { + volatile.StoreUint32(&o.CMPR0_VALUE1.Reg, volatile.LoadUint32(&o.CMPR0_VALUE1.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetCMPR0_VALUE1_CMPR0_B() uint32 { + return volatile.LoadUint32(&o.CMPR0_VALUE1.Reg) & 0xffff +} + +// PWM.GEN0_CFG0: Fault event T0 and T1 handling +func (o *PWM_Type) SetGEN0_CFG0_GEN0_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0xf)|value) +} +func (o *PWM_Type) GetGEN0_CFG0_GEN0_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0xf +} +func (o *PWM_Type) SetGEN0_CFG0_GEN0_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *PWM_Type) GetGEN0_CFG0_GEN0_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x70) >> 4 +} +func (o *PWM_Type) SetGEN0_CFG0_GEN0_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *PWM_Type) GetGEN0_CFG0_GEN0_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x380) >> 7 +} + +// PWM.GEN0_FORCE: Permissives to force PWM0A and PWM0B outputs by software +func (o *PWM_Type) SetGEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x3f)|value) +} +func (o *PWM_Type) GetGEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x3f +} +func (o *PWM_Type) SetGEN0_FORCE_GEN0_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *PWM_Type) GetGEN0_FORCE_GEN0_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc0) >> 6 +} +func (o *PWM_Type) SetGEN0_FORCE_GEN0_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetGEN0_FORCE_GEN0_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetGEN0_FORCE_GEN0_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetGEN0_FORCE_GEN0_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetGEN0_FORCE_GEN0_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *PWM_Type) GetGEN0_FORCE_GEN0_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x1800) >> 11 +} +func (o *PWM_Type) SetGEN0_FORCE_GEN0_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetGEN0_FORCE_GEN0_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetGEN0_FORCE_GEN0_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetGEN0_FORCE_GEN0_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc000) >> 14 +} + +// PWM.GEN0_A: Actions triggered by events on PWM0A +func (o *PWM_Type) SetGEN0_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3)|value) +} +func (o *PWM_Type) GetGEN0_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3 +} +func (o *PWM_Type) SetGEN0_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetGEN0_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetGEN0_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30)|value<<4) +} +func (o *PWM_Type) GetGEN0_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30) >> 4 +} +func (o *PWM_Type) SetGEN0_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0)|value<<6) +} +func (o *PWM_Type) GetGEN0_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0) >> 6 +} +func (o *PWM_Type) SetGEN0_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetGEN0_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetGEN0_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00)|value<<10) +} +func (o *PWM_Type) GetGEN0_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00) >> 10 +} +func (o *PWM_Type) SetGEN0_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3000)|value<<12) +} +func (o *PWM_Type) GetGEN0_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3000) >> 12 +} +func (o *PWM_Type) SetGEN0_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetGEN0_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc000) >> 14 +} +func (o *PWM_Type) SetGEN0_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30000)|value<<16) +} +func (o *PWM_Type) GetGEN0_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30000) >> 16 +} +func (o *PWM_Type) SetGEN0_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0000)|value<<18) +} +func (o *PWM_Type) GetGEN0_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0000) >> 18 +} +func (o *PWM_Type) SetGEN0_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300000)|value<<20) +} +func (o *PWM_Type) GetGEN0_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300000) >> 20 +} +func (o *PWM_Type) SetGEN0_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00000)|value<<22) +} +func (o *PWM_Type) GetGEN0_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00000) >> 22 +} + +// PWM.GEN0_B: Actions triggered by events on PWM0B +func (o *PWM_Type) SetGEN0_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3)|value) +} +func (o *PWM_Type) GetGEN0_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3 +} +func (o *PWM_Type) SetGEN0_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetGEN0_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetGEN0_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30)|value<<4) +} +func (o *PWM_Type) GetGEN0_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30) >> 4 +} +func (o *PWM_Type) SetGEN0_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0)|value<<6) +} +func (o *PWM_Type) GetGEN0_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0) >> 6 +} +func (o *PWM_Type) SetGEN0_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetGEN0_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetGEN0_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00)|value<<10) +} +func (o *PWM_Type) GetGEN0_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00) >> 10 +} +func (o *PWM_Type) SetGEN0_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3000)|value<<12) +} +func (o *PWM_Type) GetGEN0_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3000) >> 12 +} +func (o *PWM_Type) SetGEN0_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetGEN0_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc000) >> 14 +} +func (o *PWM_Type) SetGEN0_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30000)|value<<16) +} +func (o *PWM_Type) GetGEN0_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30000) >> 16 +} +func (o *PWM_Type) SetGEN0_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0000)|value<<18) +} +func (o *PWM_Type) GetGEN0_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0000) >> 18 +} +func (o *PWM_Type) SetGEN0_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300000)|value<<20) +} +func (o *PWM_Type) GetGEN0_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300000) >> 20 +} +func (o *PWM_Type) SetGEN0_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00000)|value<<22) +} +func (o *PWM_Type) GetGEN0_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00000) >> 22 +} + +// PWM.DB0_CFG: dead time type selection and configuration +func (o *PWM_Type) SetDB0_CFG_DB0_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0xf)|value) +} +func (o *PWM_Type) GetDB0_CFG_DB0_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DB0_CFG.Reg) & 0xf +} +func (o *PWM_Type) SetDB0_CFG_DB0_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *PWM_Type) GetDB0_CFG_DB0_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0xf0) >> 4 +} +func (o *PWM_Type) SetDB0_CFG_DB0_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetDB0_CFG_DB0_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetDB0_CFG_DB0_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetDB0_CFG_DB0_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x200) >> 9 +} +func (o *PWM_Type) SetDB0_CFG_DB0_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetDB0_CFG_DB0_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetDB0_CFG_DB0_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetDB0_CFG_DB0_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetDB0_CFG_DB0_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetDB0_CFG_DB0_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetDB0_CFG_DB0_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetDB0_CFG_DB0_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetDB0_CFG_DB0_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *PWM_Type) GetDB0_CFG_DB0_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x4000) >> 14 +} +func (o *PWM_Type) SetDB0_CFG_DB0_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *PWM_Type) GetDB0_CFG_DB0_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x8000) >> 15 +} +func (o *PWM_Type) SetDB0_CFG_DB0_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetDB0_CFG_DB0_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x10000) >> 16 +} +func (o *PWM_Type) SetDB0_CFG_DB0_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DB0_CFG.Reg, volatile.LoadUint32(&o.DB0_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *PWM_Type) GetDB0_CFG_DB0_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DB0_CFG.Reg) & 0x20000) >> 17 +} + +// PWM.DB0_FED_CFG: Shadow register for falling edge delay (FED). +func (o *PWM_Type) SetDB0_FED_CFG_DB0_FED(value uint32) { + volatile.StoreUint32(&o.DB0_FED_CFG.Reg, volatile.LoadUint32(&o.DB0_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetDB0_FED_CFG_DB0_FED() uint32 { + return volatile.LoadUint32(&o.DB0_FED_CFG.Reg) & 0xffff +} + +// PWM.DB0_RED_CFG: Shadow register for rising edge delay (RED). +func (o *PWM_Type) SetDB0_RED_CFG_DB0_RED(value uint32) { + volatile.StoreUint32(&o.DB0_RED_CFG.Reg, volatile.LoadUint32(&o.DB0_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetDB0_RED_CFG_DB0_RED() uint32 { + return volatile.LoadUint32(&o.DB0_RED_CFG.Reg) & 0xffff +} + +// PWM.CHOPPER0_CFG: Carrier enable and configuratoin +func (o *PWM_Type) SetCHOPPER0_CFG_CHOPPER0_EN(value uint32) { + volatile.StoreUint32(&o.CHOPPER0_CFG.Reg, volatile.LoadUint32(&o.CHOPPER0_CFG.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetCHOPPER0_CFG_CHOPPER0_EN() uint32 { + return volatile.LoadUint32(&o.CHOPPER0_CFG.Reg) & 0x1 +} +func (o *PWM_Type) SetCHOPPER0_CFG_CHOPPER0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CHOPPER0_CFG.Reg, volatile.LoadUint32(&o.CHOPPER0_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *PWM_Type) GetCHOPPER0_CFG_CHOPPER0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CHOPPER0_CFG.Reg) & 0x1e) >> 1 +} +func (o *PWM_Type) SetCHOPPER0_CFG_CHOPPER0_DUTY(value uint32) { + volatile.StoreUint32(&o.CHOPPER0_CFG.Reg, volatile.LoadUint32(&o.CHOPPER0_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *PWM_Type) GetCHOPPER0_CFG_CHOPPER0_DUTY() uint32 { + return (volatile.LoadUint32(&o.CHOPPER0_CFG.Reg) & 0xe0) >> 5 +} +func (o *PWM_Type) SetCHOPPER0_CFG_CHOPPER0_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CHOPPER0_CFG.Reg, volatile.LoadUint32(&o.CHOPPER0_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *PWM_Type) GetCHOPPER0_CFG_CHOPPER0_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CHOPPER0_CFG.Reg) & 0xf00) >> 8 +} +func (o *PWM_Type) SetCHOPPER0_CFG_CHOPPER0_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CHOPPER0_CFG.Reg, volatile.LoadUint32(&o.CHOPPER0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetCHOPPER0_CFG_CHOPPER0_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CHOPPER0_CFG.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetCHOPPER0_CFG_CHOPPER0_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CHOPPER0_CFG.Reg, volatile.LoadUint32(&o.CHOPPER0_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetCHOPPER0_CFG_CHOPPER0_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CHOPPER0_CFG.Reg) & 0x2000) >> 13 +} + +// PWM.TZ0_CFG0: Actions on PWM0A and PWM0B trip events +func (o *PWM_Type) SetTZ0_CFG0_TZ0_SW_CBC(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_SW_CBC() uint32 { + return volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x1 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_F2_CBC(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_F1_CBC(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x4) >> 2 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_F0_CBC(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_SW_OST(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_SW_OST() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x10) >> 4 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_F2_OST(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_F2_OST() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x20) >> 5 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_F1_OST(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_F1_OST() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x40) >> 6 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_F0_OST(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_F0_OST() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x80) >> 7 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0xc00) >> 10 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_A_OST_D(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x3000) >> 12 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_A_OST_U(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0xc000) >> 14 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x30000) >> 16 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_B_OST_D(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0x300000) >> 20 +} +func (o *PWM_Type) SetTZ0_CFG0_TZ0_B_OST_U(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG0.Reg, volatile.LoadUint32(&o.TZ0_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *PWM_Type) GetTZ0_CFG0_TZ0_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG0.Reg) & 0xc00000) >> 22 +} + +// PWM.TZ0_CFG1: Software triggers for fault handler actions +func (o *PWM_Type) SetTZ0_CFG1_TZ0_CLR_OST(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG1.Reg, volatile.LoadUint32(&o.TZ0_CFG1.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTZ0_CFG1_TZ0_CLR_OST() uint32 { + return volatile.LoadUint32(&o.TZ0_CFG1.Reg) & 0x1 +} +func (o *PWM_Type) SetTZ0_CFG1_TZ0_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG1.Reg, volatile.LoadUint32(&o.TZ0_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *PWM_Type) GetTZ0_CFG1_TZ0_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG1.Reg) & 0x6) >> 1 +} +func (o *PWM_Type) SetTZ0_CFG1_TZ0_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG1.Reg, volatile.LoadUint32(&o.TZ0_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetTZ0_CFG1_TZ0_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG1.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetTZ0_CFG1_TZ0_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.TZ0_CFG1.Reg, volatile.LoadUint32(&o.TZ0_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetTZ0_CFG1_TZ0_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.TZ0_CFG1.Reg) & 0x10) >> 4 +} + +// PWM.TZ0_STATUS: Status of fault events. +func (o *PWM_Type) SetTZ0_STATUS_TZ0_CBC_ON(value uint32) { + volatile.StoreUint32(&o.TZ0_STATUS.Reg, volatile.LoadUint32(&o.TZ0_STATUS.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTZ0_STATUS_TZ0_CBC_ON() uint32 { + return volatile.LoadUint32(&o.TZ0_STATUS.Reg) & 0x1 +} +func (o *PWM_Type) SetTZ0_STATUS_TZ0_OST_ON(value uint32) { + volatile.StoreUint32(&o.TZ0_STATUS.Reg, volatile.LoadUint32(&o.TZ0_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetTZ0_STATUS_TZ0_OST_ON() uint32 { + return (volatile.LoadUint32(&o.TZ0_STATUS.Reg) & 0x2) >> 1 +} + +// PWM.CMPR1_CFG: Transfer status and update method for time stamp registers A and B +func (o *PWM_Type) SetCMPR1_CFG_CMPR1_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.CMPR1_CFG.Reg, volatile.LoadUint32(&o.CMPR1_CFG.Reg)&^(0xf)|value) +} +func (o *PWM_Type) GetCMPR1_CFG_CMPR1_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.CMPR1_CFG.Reg) & 0xf +} +func (o *PWM_Type) SetCMPR1_CFG_CMPR1_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.CMPR1_CFG.Reg, volatile.LoadUint32(&o.CMPR1_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *PWM_Type) GetCMPR1_CFG_CMPR1_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.CMPR1_CFG.Reg) & 0xf0) >> 4 +} +func (o *PWM_Type) SetCMPR1_CFG_CMPR1_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.CMPR1_CFG.Reg, volatile.LoadUint32(&o.CMPR1_CFG.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetCMPR1_CFG_CMPR1_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.CMPR1_CFG.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetCMPR1_CFG_CMPR1_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.CMPR1_CFG.Reg, volatile.LoadUint32(&o.CMPR1_CFG.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetCMPR1_CFG_CMPR1_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.CMPR1_CFG.Reg) & 0x200) >> 9 +} + +// PWM.CMPR1_VALUE0: Shadow register for register A. +func (o *PWM_Type) SetCMPR1_VALUE0_CMPR1_A(value uint32) { + volatile.StoreUint32(&o.CMPR1_VALUE0.Reg, volatile.LoadUint32(&o.CMPR1_VALUE0.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetCMPR1_VALUE0_CMPR1_A() uint32 { + return volatile.LoadUint32(&o.CMPR1_VALUE0.Reg) & 0xffff +} + +// PWM.CMPR1_VALUE1: Shadow register for register B. +func (o *PWM_Type) SetCMPR1_VALUE1_CMPR1_B(value uint32) { + volatile.StoreUint32(&o.CMPR1_VALUE1.Reg, volatile.LoadUint32(&o.CMPR1_VALUE1.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetCMPR1_VALUE1_CMPR1_B() uint32 { + return volatile.LoadUint32(&o.CMPR1_VALUE1.Reg) & 0xffff +} + +// PWM.GEN1_CFG0: Fault event T0 and T1 handling +func (o *PWM_Type) SetGEN1_CFG0_GEN1_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0xf)|value) +} +func (o *PWM_Type) GetGEN1_CFG0_GEN1_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0xf +} +func (o *PWM_Type) SetGEN1_CFG0_GEN1_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *PWM_Type) GetGEN1_CFG0_GEN1_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x70) >> 4 +} +func (o *PWM_Type) SetGEN1_CFG0_GEN1_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *PWM_Type) GetGEN1_CFG0_GEN1_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x380) >> 7 +} + +// PWM.GEN1_FORCE: Permissives to force PWM1A and PWM1B outputs by software +func (o *PWM_Type) SetGEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x3f)|value) +} +func (o *PWM_Type) GetGEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x3f +} +func (o *PWM_Type) SetGEN1_FORCE_GEN1_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *PWM_Type) GetGEN1_FORCE_GEN1_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc0) >> 6 +} +func (o *PWM_Type) SetGEN1_FORCE_GEN1_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetGEN1_FORCE_GEN1_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetGEN1_FORCE_GEN1_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetGEN1_FORCE_GEN1_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetGEN1_FORCE_GEN1_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *PWM_Type) GetGEN1_FORCE_GEN1_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x1800) >> 11 +} +func (o *PWM_Type) SetGEN1_FORCE_GEN1_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetGEN1_FORCE_GEN1_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetGEN1_FORCE_GEN1_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetGEN1_FORCE_GEN1_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc000) >> 14 +} + +// PWM.GEN1_A: Actions triggered by events on PWM1A +func (o *PWM_Type) SetGEN1_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3)|value) +} +func (o *PWM_Type) GetGEN1_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3 +} +func (o *PWM_Type) SetGEN1_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetGEN1_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetGEN1_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30)|value<<4) +} +func (o *PWM_Type) GetGEN1_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30) >> 4 +} +func (o *PWM_Type) SetGEN1_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0)|value<<6) +} +func (o *PWM_Type) GetGEN1_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0) >> 6 +} +func (o *PWM_Type) SetGEN1_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetGEN1_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetGEN1_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00)|value<<10) +} +func (o *PWM_Type) GetGEN1_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00) >> 10 +} +func (o *PWM_Type) SetGEN1_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3000)|value<<12) +} +func (o *PWM_Type) GetGEN1_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3000) >> 12 +} +func (o *PWM_Type) SetGEN1_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetGEN1_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc000) >> 14 +} +func (o *PWM_Type) SetGEN1_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30000)|value<<16) +} +func (o *PWM_Type) GetGEN1_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30000) >> 16 +} +func (o *PWM_Type) SetGEN1_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0000)|value<<18) +} +func (o *PWM_Type) GetGEN1_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0000) >> 18 +} +func (o *PWM_Type) SetGEN1_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300000)|value<<20) +} +func (o *PWM_Type) GetGEN1_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300000) >> 20 +} +func (o *PWM_Type) SetGEN1_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00000)|value<<22) +} +func (o *PWM_Type) GetGEN1_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00000) >> 22 +} + +// PWM.GEN1_B: Actions triggered by events on PWM1B +func (o *PWM_Type) SetGEN1_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3)|value) +} +func (o *PWM_Type) GetGEN1_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3 +} +func (o *PWM_Type) SetGEN1_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetGEN1_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetGEN1_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30)|value<<4) +} +func (o *PWM_Type) GetGEN1_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30) >> 4 +} +func (o *PWM_Type) SetGEN1_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0)|value<<6) +} +func (o *PWM_Type) GetGEN1_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0) >> 6 +} +func (o *PWM_Type) SetGEN1_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetGEN1_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetGEN1_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00)|value<<10) +} +func (o *PWM_Type) GetGEN1_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00) >> 10 +} +func (o *PWM_Type) SetGEN1_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3000)|value<<12) +} +func (o *PWM_Type) GetGEN1_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3000) >> 12 +} +func (o *PWM_Type) SetGEN1_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetGEN1_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc000) >> 14 +} +func (o *PWM_Type) SetGEN1_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30000)|value<<16) +} +func (o *PWM_Type) GetGEN1_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30000) >> 16 +} +func (o *PWM_Type) SetGEN1_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0000)|value<<18) +} +func (o *PWM_Type) GetGEN1_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0000) >> 18 +} +func (o *PWM_Type) SetGEN1_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300000)|value<<20) +} +func (o *PWM_Type) GetGEN1_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300000) >> 20 +} +func (o *PWM_Type) SetGEN1_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00000)|value<<22) +} +func (o *PWM_Type) GetGEN1_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00000) >> 22 +} + +// PWM.DB1_CFG: dead time type selection and configuration +func (o *PWM_Type) SetDB1_CFG_DB1_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0xf)|value) +} +func (o *PWM_Type) GetDB1_CFG_DB1_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DB1_CFG.Reg) & 0xf +} +func (o *PWM_Type) SetDB1_CFG_DB1_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *PWM_Type) GetDB1_CFG_DB1_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0xf0) >> 4 +} +func (o *PWM_Type) SetDB1_CFG_DB1_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetDB1_CFG_DB1_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetDB1_CFG_DB1_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetDB1_CFG_DB1_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x200) >> 9 +} +func (o *PWM_Type) SetDB1_CFG_DB1_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetDB1_CFG_DB1_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetDB1_CFG_DB1_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetDB1_CFG_DB1_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetDB1_CFG_DB1_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetDB1_CFG_DB1_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetDB1_CFG_DB1_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetDB1_CFG_DB1_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetDB1_CFG_DB1_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *PWM_Type) GetDB1_CFG_DB1_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x4000) >> 14 +} +func (o *PWM_Type) SetDB1_CFG_DB1_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *PWM_Type) GetDB1_CFG_DB1_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x8000) >> 15 +} +func (o *PWM_Type) SetDB1_CFG_DB1_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetDB1_CFG_DB1_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x10000) >> 16 +} +func (o *PWM_Type) SetDB1_CFG_DB1_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DB1_CFG.Reg, volatile.LoadUint32(&o.DB1_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *PWM_Type) GetDB1_CFG_DB1_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DB1_CFG.Reg) & 0x20000) >> 17 +} + +// PWM.DB1_FED_CFG: Shadow register for falling edge delay (FED). +func (o *PWM_Type) SetDB1_FED_CFG_DB1_FED(value uint32) { + volatile.StoreUint32(&o.DB1_FED_CFG.Reg, volatile.LoadUint32(&o.DB1_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetDB1_FED_CFG_DB1_FED() uint32 { + return volatile.LoadUint32(&o.DB1_FED_CFG.Reg) & 0xffff +} + +// PWM.DB1_RED_CFG: Shadow register for rising edge delay (RED). +func (o *PWM_Type) SetDB1_RED_CFG_DB1_RED(value uint32) { + volatile.StoreUint32(&o.DB1_RED_CFG.Reg, volatile.LoadUint32(&o.DB1_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetDB1_RED_CFG_DB1_RED() uint32 { + return volatile.LoadUint32(&o.DB1_RED_CFG.Reg) & 0xffff +} + +// PWM.CHOPPER1_CFG: Carrier enable and configuratoin +func (o *PWM_Type) SetCHOPPER1_CFG_CHOPPER1_EN(value uint32) { + volatile.StoreUint32(&o.CHOPPER1_CFG.Reg, volatile.LoadUint32(&o.CHOPPER1_CFG.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetCHOPPER1_CFG_CHOPPER1_EN() uint32 { + return volatile.LoadUint32(&o.CHOPPER1_CFG.Reg) & 0x1 +} +func (o *PWM_Type) SetCHOPPER1_CFG_CHOPPER1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CHOPPER1_CFG.Reg, volatile.LoadUint32(&o.CHOPPER1_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *PWM_Type) GetCHOPPER1_CFG_CHOPPER1_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CHOPPER1_CFG.Reg) & 0x1e) >> 1 +} +func (o *PWM_Type) SetCHOPPER1_CFG_CHOPPER1_DUTY(value uint32) { + volatile.StoreUint32(&o.CHOPPER1_CFG.Reg, volatile.LoadUint32(&o.CHOPPER1_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *PWM_Type) GetCHOPPER1_CFG_CHOPPER1_DUTY() uint32 { + return (volatile.LoadUint32(&o.CHOPPER1_CFG.Reg) & 0xe0) >> 5 +} +func (o *PWM_Type) SetCHOPPER1_CFG_CHOPPER1_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CHOPPER1_CFG.Reg, volatile.LoadUint32(&o.CHOPPER1_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *PWM_Type) GetCHOPPER1_CFG_CHOPPER1_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CHOPPER1_CFG.Reg) & 0xf00) >> 8 +} +func (o *PWM_Type) SetCHOPPER1_CFG_CHOPPER1_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CHOPPER1_CFG.Reg, volatile.LoadUint32(&o.CHOPPER1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetCHOPPER1_CFG_CHOPPER1_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CHOPPER1_CFG.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetCHOPPER1_CFG_CHOPPER1_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CHOPPER1_CFG.Reg, volatile.LoadUint32(&o.CHOPPER1_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetCHOPPER1_CFG_CHOPPER1_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CHOPPER1_CFG.Reg) & 0x2000) >> 13 +} + +// PWM.TZ1_CFG0: Actions on PWM1A and PWM1B trip events +func (o *PWM_Type) SetTZ1_CFG0_TZ1_SW_CBC(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_SW_CBC() uint32 { + return volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x1 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_F2_CBC(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_F1_CBC(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x4) >> 2 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_F0_CBC(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_SW_OST(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_SW_OST() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x10) >> 4 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_F2_OST(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_F2_OST() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x20) >> 5 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_F1_OST(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_F1_OST() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x40) >> 6 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_F0_OST(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_F0_OST() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x80) >> 7 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0xc00) >> 10 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_A_OST_D(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x3000) >> 12 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_A_OST_U(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0xc000) >> 14 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x30000) >> 16 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_B_OST_D(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0x300000) >> 20 +} +func (o *PWM_Type) SetTZ1_CFG0_TZ1_B_OST_U(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG0.Reg, volatile.LoadUint32(&o.TZ1_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *PWM_Type) GetTZ1_CFG0_TZ1_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG0.Reg) & 0xc00000) >> 22 +} + +// PWM.TZ1_CFG1: Software triggers for fault handler actions +func (o *PWM_Type) SetTZ1_CFG1_TZ1_CLR_OST(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG1.Reg, volatile.LoadUint32(&o.TZ1_CFG1.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTZ1_CFG1_TZ1_CLR_OST() uint32 { + return volatile.LoadUint32(&o.TZ1_CFG1.Reg) & 0x1 +} +func (o *PWM_Type) SetTZ1_CFG1_TZ1_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG1.Reg, volatile.LoadUint32(&o.TZ1_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *PWM_Type) GetTZ1_CFG1_TZ1_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG1.Reg) & 0x6) >> 1 +} +func (o *PWM_Type) SetTZ1_CFG1_TZ1_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG1.Reg, volatile.LoadUint32(&o.TZ1_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetTZ1_CFG1_TZ1_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG1.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetTZ1_CFG1_TZ1_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.TZ1_CFG1.Reg, volatile.LoadUint32(&o.TZ1_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetTZ1_CFG1_TZ1_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.TZ1_CFG1.Reg) & 0x10) >> 4 +} + +// PWM.TZ1_STATUS: Status of fault events. +func (o *PWM_Type) SetTZ1_STATUS_TZ1_CBC_ON(value uint32) { + volatile.StoreUint32(&o.TZ1_STATUS.Reg, volatile.LoadUint32(&o.TZ1_STATUS.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTZ1_STATUS_TZ1_CBC_ON() uint32 { + return volatile.LoadUint32(&o.TZ1_STATUS.Reg) & 0x1 +} +func (o *PWM_Type) SetTZ1_STATUS_TZ1_OST_ON(value uint32) { + volatile.StoreUint32(&o.TZ1_STATUS.Reg, volatile.LoadUint32(&o.TZ1_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetTZ1_STATUS_TZ1_OST_ON() uint32 { + return (volatile.LoadUint32(&o.TZ1_STATUS.Reg) & 0x2) >> 1 +} + +// PWM.CMPR2_CFG: Transfer status and update method for time stamp registers A and B +func (o *PWM_Type) SetCMPR2_CFG_CMPR2_A_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.CMPR2_CFG.Reg, volatile.LoadUint32(&o.CMPR2_CFG.Reg)&^(0xf)|value) +} +func (o *PWM_Type) GetCMPR2_CFG_CMPR2_A_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.CMPR2_CFG.Reg) & 0xf +} +func (o *PWM_Type) SetCMPR2_CFG_CMPR2_B_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.CMPR2_CFG.Reg, volatile.LoadUint32(&o.CMPR2_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *PWM_Type) GetCMPR2_CFG_CMPR2_B_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.CMPR2_CFG.Reg) & 0xf0) >> 4 +} +func (o *PWM_Type) SetCMPR2_CFG_CMPR2_A_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.CMPR2_CFG.Reg, volatile.LoadUint32(&o.CMPR2_CFG.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetCMPR2_CFG_CMPR2_A_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.CMPR2_CFG.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetCMPR2_CFG_CMPR2_B_SHDW_FULL(value uint32) { + volatile.StoreUint32(&o.CMPR2_CFG.Reg, volatile.LoadUint32(&o.CMPR2_CFG.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetCMPR2_CFG_CMPR2_B_SHDW_FULL() uint32 { + return (volatile.LoadUint32(&o.CMPR2_CFG.Reg) & 0x200) >> 9 +} + +// PWM.CMPR2_VALUE0: Shadow register for register A. +func (o *PWM_Type) SetCMPR2_VALUE0_CMPR2_A(value uint32) { + volatile.StoreUint32(&o.CMPR2_VALUE0.Reg, volatile.LoadUint32(&o.CMPR2_VALUE0.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetCMPR2_VALUE0_CMPR2_A() uint32 { + return volatile.LoadUint32(&o.CMPR2_VALUE0.Reg) & 0xffff +} + +// PWM.CMPR2_VALUE1: Shadow register for register B. +func (o *PWM_Type) SetCMPR2_VALUE1_CMPR2_B(value uint32) { + volatile.StoreUint32(&o.CMPR2_VALUE1.Reg, volatile.LoadUint32(&o.CMPR2_VALUE1.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetCMPR2_VALUE1_CMPR2_B() uint32 { + return volatile.LoadUint32(&o.CMPR2_VALUE1.Reg) & 0xffff +} + +// PWM.GEN2_CFG0: Fault event T0 and T1 handling +func (o *PWM_Type) SetGEN2_CFG0_GEN2_CFG_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0xf)|value) +} +func (o *PWM_Type) GetGEN2_CFG0_GEN2_CFG_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0xf +} +func (o *PWM_Type) SetGEN2_CFG0_GEN2_T0_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x70)|value<<4) +} +func (o *PWM_Type) GetGEN2_CFG0_GEN2_T0_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x70) >> 4 +} +func (o *PWM_Type) SetGEN2_CFG0_GEN2_T1_SEL(value uint32) { + volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x380)|value<<7) +} +func (o *PWM_Type) GetGEN2_CFG0_GEN2_T1_SEL() uint32 { + return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x380) >> 7 +} + +// PWM.GEN2_FORCE: Permissives to force PWM2A and PWM2B outputs by software +func (o *PWM_Type) SetGEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x3f)|value) +} +func (o *PWM_Type) GetGEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x3f +} +func (o *PWM_Type) SetGEN2_FORCE_GEN2_A_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc0)|value<<6) +} +func (o *PWM_Type) GetGEN2_FORCE_GEN2_A_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc0) >> 6 +} +func (o *PWM_Type) SetGEN2_FORCE_GEN2_B_CNTUFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetGEN2_FORCE_GEN2_B_CNTUFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetGEN2_FORCE_GEN2_A_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetGEN2_FORCE_GEN2_A_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetGEN2_FORCE_GEN2_A_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x1800)|value<<11) +} +func (o *PWM_Type) GetGEN2_FORCE_GEN2_A_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x1800) >> 11 +} +func (o *PWM_Type) SetGEN2_FORCE_GEN2_B_NCIFORCE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetGEN2_FORCE_GEN2_B_NCIFORCE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetGEN2_FORCE_GEN2_B_NCIFORCE_MODE(value uint32) { + volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetGEN2_FORCE_GEN2_B_NCIFORCE_MODE() uint32 { + return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc000) >> 14 +} + +// PWM.GEN2_A: Actions triggered by events on PWM2A +func (o *PWM_Type) SetGEN2_A_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3)|value) +} +func (o *PWM_Type) GetGEN2_A_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3 +} +func (o *PWM_Type) SetGEN2_A_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetGEN2_A_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetGEN2_A_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30)|value<<4) +} +func (o *PWM_Type) GetGEN2_A_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30) >> 4 +} +func (o *PWM_Type) SetGEN2_A_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0)|value<<6) +} +func (o *PWM_Type) GetGEN2_A_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0) >> 6 +} +func (o *PWM_Type) SetGEN2_A_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetGEN2_A_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetGEN2_A_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00)|value<<10) +} +func (o *PWM_Type) GetGEN2_A_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00) >> 10 +} +func (o *PWM_Type) SetGEN2_A_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3000)|value<<12) +} +func (o *PWM_Type) GetGEN2_A_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3000) >> 12 +} +func (o *PWM_Type) SetGEN2_A_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetGEN2_A_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc000) >> 14 +} +func (o *PWM_Type) SetGEN2_A_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30000)|value<<16) +} +func (o *PWM_Type) GetGEN2_A_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30000) >> 16 +} +func (o *PWM_Type) SetGEN2_A_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0000)|value<<18) +} +func (o *PWM_Type) GetGEN2_A_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0000) >> 18 +} +func (o *PWM_Type) SetGEN2_A_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300000)|value<<20) +} +func (o *PWM_Type) GetGEN2_A_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300000) >> 20 +} +func (o *PWM_Type) SetGEN2_A_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00000)|value<<22) +} +func (o *PWM_Type) GetGEN2_A_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00000) >> 22 +} + +// PWM.GEN2_B: Actions triggered by events on PWM2B +func (o *PWM_Type) SetGEN2_B_UTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3)|value) +} +func (o *PWM_Type) GetGEN2_B_UTEZ() uint32 { + return volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3 +} +func (o *PWM_Type) SetGEN2_B_UTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc)|value<<2) +} +func (o *PWM_Type) GetGEN2_B_UTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc) >> 2 +} +func (o *PWM_Type) SetGEN2_B_UTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30)|value<<4) +} +func (o *PWM_Type) GetGEN2_B_UTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30) >> 4 +} +func (o *PWM_Type) SetGEN2_B_UTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0)|value<<6) +} +func (o *PWM_Type) GetGEN2_B_UTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0) >> 6 +} +func (o *PWM_Type) SetGEN2_B_UT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetGEN2_B_UT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetGEN2_B_UT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00)|value<<10) +} +func (o *PWM_Type) GetGEN2_B_UT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00) >> 10 +} +func (o *PWM_Type) SetGEN2_B_DTEZ(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3000)|value<<12) +} +func (o *PWM_Type) GetGEN2_B_DTEZ() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3000) >> 12 +} +func (o *PWM_Type) SetGEN2_B_DTEP(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetGEN2_B_DTEP() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc000) >> 14 +} +func (o *PWM_Type) SetGEN2_B_DTEA(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30000)|value<<16) +} +func (o *PWM_Type) GetGEN2_B_DTEA() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30000) >> 16 +} +func (o *PWM_Type) SetGEN2_B_DTEB(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0000)|value<<18) +} +func (o *PWM_Type) GetGEN2_B_DTEB() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0000) >> 18 +} +func (o *PWM_Type) SetGEN2_B_DT0(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300000)|value<<20) +} +func (o *PWM_Type) GetGEN2_B_DT0() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300000) >> 20 +} +func (o *PWM_Type) SetGEN2_B_DT1(value uint32) { + volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00000)|value<<22) +} +func (o *PWM_Type) GetGEN2_B_DT1() uint32 { + return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00000) >> 22 +} + +// PWM.DB2_CFG: dead time type selection and configuration +func (o *PWM_Type) SetDB2_CFG_DB2_FED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0xf)|value) +} +func (o *PWM_Type) GetDB2_CFG_DB2_FED_UPMETHOD() uint32 { + return volatile.LoadUint32(&o.DB2_CFG.Reg) & 0xf +} +func (o *PWM_Type) SetDB2_CFG_DB2_RED_UPMETHOD(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0xf0)|value<<4) +} +func (o *PWM_Type) GetDB2_CFG_DB2_RED_UPMETHOD() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0xf0) >> 4 +} +func (o *PWM_Type) SetDB2_CFG_DB2_DEB_MODE(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetDB2_CFG_DB2_DEB_MODE() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetDB2_CFG_DB2_A_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetDB2_CFG_DB2_A_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x200) >> 9 +} +func (o *PWM_Type) SetDB2_CFG_DB2_B_OUTSWAP(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetDB2_CFG_DB2_B_OUTSWAP() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetDB2_CFG_DB2_RED_INSEL(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetDB2_CFG_DB2_RED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetDB2_CFG_DB2_FED_INSEL(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetDB2_CFG_DB2_FED_INSEL() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetDB2_CFG_DB2_RED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetDB2_CFG_DB2_RED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetDB2_CFG_DB2_FED_OUTINVERT(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x4000)|value<<14) +} +func (o *PWM_Type) GetDB2_CFG_DB2_FED_OUTINVERT() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x4000) >> 14 +} +func (o *PWM_Type) SetDB2_CFG_DB2_A_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x8000)|value<<15) +} +func (o *PWM_Type) GetDB2_CFG_DB2_A_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x8000) >> 15 +} +func (o *PWM_Type) SetDB2_CFG_DB2_B_OUTBYPASS(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetDB2_CFG_DB2_B_OUTBYPASS() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x10000) >> 16 +} +func (o *PWM_Type) SetDB2_CFG_DB2_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.DB2_CFG.Reg, volatile.LoadUint32(&o.DB2_CFG.Reg)&^(0x20000)|value<<17) +} +func (o *PWM_Type) GetDB2_CFG_DB2_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.DB2_CFG.Reg) & 0x20000) >> 17 +} + +// PWM.DB2_FED_CFG: Shadow register for falling edge delay (FED). +func (o *PWM_Type) SetDB2_FED_CFG_DB2_FED(value uint32) { + volatile.StoreUint32(&o.DB2_FED_CFG.Reg, volatile.LoadUint32(&o.DB2_FED_CFG.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetDB2_FED_CFG_DB2_FED() uint32 { + return volatile.LoadUint32(&o.DB2_FED_CFG.Reg) & 0xffff +} + +// PWM.DB2_RED_CFG: Shadow register for rising edge delay (RED). +func (o *PWM_Type) SetDB2_RED_CFG_DB2_RED(value uint32) { + volatile.StoreUint32(&o.DB2_RED_CFG.Reg, volatile.LoadUint32(&o.DB2_RED_CFG.Reg)&^(0xffff)|value) +} +func (o *PWM_Type) GetDB2_RED_CFG_DB2_RED() uint32 { + return volatile.LoadUint32(&o.DB2_RED_CFG.Reg) & 0xffff +} + +// PWM.CHOPPER2_CFG: Carrier enable and configuratoin +func (o *PWM_Type) SetCHOPPER2_CFG_CHOPPER2_EN(value uint32) { + volatile.StoreUint32(&o.CHOPPER2_CFG.Reg, volatile.LoadUint32(&o.CHOPPER2_CFG.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetCHOPPER2_CFG_CHOPPER2_EN() uint32 { + return volatile.LoadUint32(&o.CHOPPER2_CFG.Reg) & 0x1 +} +func (o *PWM_Type) SetCHOPPER2_CFG_CHOPPER2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CHOPPER2_CFG.Reg, volatile.LoadUint32(&o.CHOPPER2_CFG.Reg)&^(0x1e)|value<<1) +} +func (o *PWM_Type) GetCHOPPER2_CFG_CHOPPER2_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CHOPPER2_CFG.Reg) & 0x1e) >> 1 +} +func (o *PWM_Type) SetCHOPPER2_CFG_CHOPPER2_DUTY(value uint32) { + volatile.StoreUint32(&o.CHOPPER2_CFG.Reg, volatile.LoadUint32(&o.CHOPPER2_CFG.Reg)&^(0xe0)|value<<5) +} +func (o *PWM_Type) GetCHOPPER2_CFG_CHOPPER2_DUTY() uint32 { + return (volatile.LoadUint32(&o.CHOPPER2_CFG.Reg) & 0xe0) >> 5 +} +func (o *PWM_Type) SetCHOPPER2_CFG_CHOPPER2_OSHTWTH(value uint32) { + volatile.StoreUint32(&o.CHOPPER2_CFG.Reg, volatile.LoadUint32(&o.CHOPPER2_CFG.Reg)&^(0xf00)|value<<8) +} +func (o *PWM_Type) GetCHOPPER2_CFG_CHOPPER2_OSHTWTH() uint32 { + return (volatile.LoadUint32(&o.CHOPPER2_CFG.Reg) & 0xf00) >> 8 +} +func (o *PWM_Type) SetCHOPPER2_CFG_CHOPPER2_OUT_INVERT(value uint32) { + volatile.StoreUint32(&o.CHOPPER2_CFG.Reg, volatile.LoadUint32(&o.CHOPPER2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetCHOPPER2_CFG_CHOPPER2_OUT_INVERT() uint32 { + return (volatile.LoadUint32(&o.CHOPPER2_CFG.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetCHOPPER2_CFG_CHOPPER2_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CHOPPER2_CFG.Reg, volatile.LoadUint32(&o.CHOPPER2_CFG.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetCHOPPER2_CFG_CHOPPER2_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CHOPPER2_CFG.Reg) & 0x2000) >> 13 +} + +// PWM.TZ2_CFG0: Actions on PWM2A and PWM2B trip events +func (o *PWM_Type) SetTZ2_CFG0_TZ2_SW_CBC(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_SW_CBC() uint32 { + return volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x1 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_F2_CBC(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_F2_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_F1_CBC(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_F1_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x4) >> 2 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_F0_CBC(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_F0_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_SW_OST(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_SW_OST() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x10) >> 4 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_F2_OST(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_F2_OST() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x20) >> 5 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_F1_OST(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x40)|value<<6) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_F1_OST() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x40) >> 6 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_F0_OST(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x80)|value<<7) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_F0_OST() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x80) >> 7 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_A_CBC_D(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x300)|value<<8) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_A_CBC_D() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x300) >> 8 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_A_CBC_U(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0xc00)|value<<10) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_A_CBC_U() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0xc00) >> 10 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_A_OST_D(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x3000)|value<<12) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_A_OST_D() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x3000) >> 12 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_A_OST_U(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0xc000)|value<<14) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_A_OST_U() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0xc000) >> 14 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_B_CBC_D(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x30000)|value<<16) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_B_CBC_D() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x30000) >> 16 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_B_CBC_U(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0xc0000)|value<<18) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_B_CBC_U() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0xc0000) >> 18 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_B_OST_D(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0x300000)|value<<20) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_B_OST_D() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0x300000) >> 20 +} +func (o *PWM_Type) SetTZ2_CFG0_TZ2_B_OST_U(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG0.Reg, volatile.LoadUint32(&o.TZ2_CFG0.Reg)&^(0xc00000)|value<<22) +} +func (o *PWM_Type) GetTZ2_CFG0_TZ2_B_OST_U() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG0.Reg) & 0xc00000) >> 22 +} + +// PWM.TZ2_CFG1: Software triggers for fault handler actions +func (o *PWM_Type) SetTZ2_CFG1_TZ2_CLR_OST(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG1.Reg, volatile.LoadUint32(&o.TZ2_CFG1.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTZ2_CFG1_TZ2_CLR_OST() uint32 { + return volatile.LoadUint32(&o.TZ2_CFG1.Reg) & 0x1 +} +func (o *PWM_Type) SetTZ2_CFG1_TZ2_CBCPULSE(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG1.Reg, volatile.LoadUint32(&o.TZ2_CFG1.Reg)&^(0x6)|value<<1) +} +func (o *PWM_Type) GetTZ2_CFG1_TZ2_CBCPULSE() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG1.Reg) & 0x6) >> 1 +} +func (o *PWM_Type) SetTZ2_CFG1_TZ2_FORCE_CBC(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG1.Reg, volatile.LoadUint32(&o.TZ2_CFG1.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetTZ2_CFG1_TZ2_FORCE_CBC() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG1.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetTZ2_CFG1_TZ2_FORCE_OST(value uint32) { + volatile.StoreUint32(&o.TZ2_CFG1.Reg, volatile.LoadUint32(&o.TZ2_CFG1.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetTZ2_CFG1_TZ2_FORCE_OST() uint32 { + return (volatile.LoadUint32(&o.TZ2_CFG1.Reg) & 0x10) >> 4 +} + +// PWM.TZ2_STATUS: Status of fault events. +func (o *PWM_Type) SetTZ2_STATUS_TZ2_CBC_ON(value uint32) { + volatile.StoreUint32(&o.TZ2_STATUS.Reg, volatile.LoadUint32(&o.TZ2_STATUS.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetTZ2_STATUS_TZ2_CBC_ON() uint32 { + return volatile.LoadUint32(&o.TZ2_STATUS.Reg) & 0x1 +} +func (o *PWM_Type) SetTZ2_STATUS_TZ2_OST_ON(value uint32) { + volatile.StoreUint32(&o.TZ2_STATUS.Reg, volatile.LoadUint32(&o.TZ2_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetTZ2_STATUS_TZ2_OST_ON() uint32 { + return (volatile.LoadUint32(&o.TZ2_STATUS.Reg) & 0x2) >> 1 +} + +// PWM.FAULT_DETECT: Fault detection configuration and status +func (o *PWM_Type) SetFAULT_DETECT_F0_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetFAULT_DETECT_F0_EN() uint32 { + return volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x1 +} +func (o *PWM_Type) SetFAULT_DETECT_F1_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetFAULT_DETECT_F1_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetFAULT_DETECT_F2_EN(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetFAULT_DETECT_F2_EN() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x4) >> 2 +} +func (o *PWM_Type) SetFAULT_DETECT_F0_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetFAULT_DETECT_F0_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetFAULT_DETECT_F1_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetFAULT_DETECT_F1_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x10) >> 4 +} +func (o *PWM_Type) SetFAULT_DETECT_F2_POLE(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetFAULT_DETECT_F2_POLE() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x20) >> 5 +} +func (o *PWM_Type) SetFAULT_DETECT_EVENT_F0(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x40)|value<<6) +} +func (o *PWM_Type) GetFAULT_DETECT_EVENT_F0() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x40) >> 6 +} +func (o *PWM_Type) SetFAULT_DETECT_EVENT_F1(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x80)|value<<7) +} +func (o *PWM_Type) GetFAULT_DETECT_EVENT_F1() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x80) >> 7 +} +func (o *PWM_Type) SetFAULT_DETECT_EVENT_F2(value uint32) { + volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetFAULT_DETECT_EVENT_F2() uint32 { + return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x100) >> 8 +} + +// PWM.CAP_TIMER_CFG: Configure capture timer +func (o *PWM_Type) SetCAP_TIMER_CFG_CAP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetCAP_TIMER_CFG_CAP_TIMER_EN() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1 +} +func (o *PWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_EN(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_EN() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_SEL(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1c)|value<<2) +} +func (o *PWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_SEL() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1c) >> 2 +} +func (o *PWM_Type) SetCAP_TIMER_CFG_CAP_SYNC_SW(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetCAP_TIMER_CFG_CAP_SYNC_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x20) >> 5 +} + +// PWM.CAP_TIMER_PHASE: Phase for capture timer sync +func (o *PWM_Type) SetCAP_TIMER_PHASE(value uint32) { + volatile.StoreUint32(&o.CAP_TIMER_PHASE.Reg, value) +} +func (o *PWM_Type) GetCAP_TIMER_PHASE() uint32 { + return volatile.LoadUint32(&o.CAP_TIMER_PHASE.Reg) +} + +// PWM.CAP_CH0_CFG: Capture channel 0 configuration and enable +func (o *PWM_Type) SetCAP_CH0_CFG_CAP0_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetCAP_CH0_CFG_CAP0_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1 +} +func (o *PWM_Type) SetCAP_CH0_CFG_CAP0_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x6)|value<<1) +} +func (o *PWM_Type) GetCAP_CH0_CFG_CAP0_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x6) >> 1 +} +func (o *PWM_Type) SetCAP_CH0_CFG_CAP0_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *PWM_Type) GetCAP_CH0_CFG_CAP0_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x7f8) >> 3 +} +func (o *PWM_Type) SetCAP_CH0_CFG_CAP0_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetCAP_CH0_CFG_CAP0_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetCAP_CH0_CFG_CAP0_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetCAP_CH0_CFG_CAP0_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1000) >> 12 +} + +// PWM.CAP_CH1_CFG: Capture channel 1 configuration and enable +func (o *PWM_Type) SetCAP_CH1_CFG_CAP1_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetCAP_CH1_CFG_CAP1_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1 +} +func (o *PWM_Type) SetCAP_CH1_CFG_CAP1_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x6)|value<<1) +} +func (o *PWM_Type) GetCAP_CH1_CFG_CAP1_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x6) >> 1 +} +func (o *PWM_Type) SetCAP_CH1_CFG_CAP1_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *PWM_Type) GetCAP_CH1_CFG_CAP1_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x7f8) >> 3 +} +func (o *PWM_Type) SetCAP_CH1_CFG_CAP1_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetCAP_CH1_CFG_CAP1_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetCAP_CH1_CFG_CAP1_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetCAP_CH1_CFG_CAP1_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1000) >> 12 +} + +// PWM.CAP_CH2_CFG: Capture channel 2 configuration and enable +func (o *PWM_Type) SetCAP_CH2_CFG_CAP2_EN(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetCAP_CH2_CFG_CAP2_EN() uint32 { + return volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1 +} +func (o *PWM_Type) SetCAP_CH2_CFG_CAP2_MODE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x6)|value<<1) +} +func (o *PWM_Type) GetCAP_CH2_CFG_CAP2_MODE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x6) >> 1 +} +func (o *PWM_Type) SetCAP_CH2_CFG_CAP2_PRESCALE(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x7f8)|value<<3) +} +func (o *PWM_Type) GetCAP_CH2_CFG_CAP2_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x7f8) >> 3 +} +func (o *PWM_Type) SetCAP_CH2_CFG_CAP2_IN_INVERT(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetCAP_CH2_CFG_CAP2_IN_INVERT() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetCAP_CH2_CFG_CAP2_SW(value uint32) { + volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetCAP_CH2_CFG_CAP2_SW() uint32 { + return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1000) >> 12 +} + +// PWM.CAP_CH0: Value of last capture on channel 0 +func (o *PWM_Type) SetCAP_CH0(value uint32) { + volatile.StoreUint32(&o.CAP_CH0.Reg, value) +} +func (o *PWM_Type) GetCAP_CH0() uint32 { + return volatile.LoadUint32(&o.CAP_CH0.Reg) +} + +// PWM.CAP_CH1: Value of last capture on channel 1 +func (o *PWM_Type) SetCAP_CH1(value uint32) { + volatile.StoreUint32(&o.CAP_CH1.Reg, value) +} +func (o *PWM_Type) GetCAP_CH1() uint32 { + return volatile.LoadUint32(&o.CAP_CH1.Reg) +} + +// PWM.CAP_CH2: Value of last capture on channel 2 +func (o *PWM_Type) SetCAP_CH2(value uint32) { + volatile.StoreUint32(&o.CAP_CH2.Reg, value) +} +func (o *PWM_Type) GetCAP_CH2() uint32 { + return volatile.LoadUint32(&o.CAP_CH2.Reg) +} + +// PWM.CAP_STATUS: Edge of last capture trigger +func (o *PWM_Type) SetCAP_STATUS_CAP0_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetCAP_STATUS_CAP0_EDGE() uint32 { + return volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x1 +} +func (o *PWM_Type) SetCAP_STATUS_CAP1_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetCAP_STATUS_CAP1_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetCAP_STATUS_CAP2_EDGE(value uint32) { + volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetCAP_STATUS_CAP2_EDGE() uint32 { + return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x4) >> 2 +} + +// PWM.UPDATE_CFG: Enable update. +func (o *PWM_Type) SetUPDATE_CFG_GLOBAL_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetUPDATE_CFG_GLOBAL_UP_EN() uint32 { + return volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x1 +} +func (o *PWM_Type) SetUPDATE_CFG_GLOBAL_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetUPDATE_CFG_GLOBAL_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetUPDATE_CFG_OP0_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetUPDATE_CFG_OP0_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x4) >> 2 +} +func (o *PWM_Type) SetUPDATE_CFG_OP0_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetUPDATE_CFG_OP0_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetUPDATE_CFG_OP1_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetUPDATE_CFG_OP1_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x10) >> 4 +} +func (o *PWM_Type) SetUPDATE_CFG_OP1_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetUPDATE_CFG_OP1_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x20) >> 5 +} +func (o *PWM_Type) SetUPDATE_CFG_OP2_UP_EN(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x40)|value<<6) +} +func (o *PWM_Type) GetUPDATE_CFG_OP2_UP_EN() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x40) >> 6 +} +func (o *PWM_Type) SetUPDATE_CFG_OP2_FORCE_UP(value uint32) { + volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x80)|value<<7) +} +func (o *PWM_Type) GetUPDATE_CFG_OP2_FORCE_UP() uint32 { + return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x80) >> 7 +} + +// PWM.INT_ENA: Interrupt enable bits +func (o *PWM_Type) SetINT_ENA_TIMER0_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetINT_ENA_TIMER0_STOP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *PWM_Type) SetINT_ENA_TIMER1_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetINT_ENA_TIMER1_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetINT_ENA_TIMER2_STOP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetINT_ENA_TIMER2_STOP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *PWM_Type) SetINT_ENA_TIMER0_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetINT_ENA_TIMER0_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetINT_ENA_TIMER1_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetINT_ENA_TIMER1_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *PWM_Type) SetINT_ENA_TIMER2_TEZ_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetINT_ENA_TIMER2_TEZ_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *PWM_Type) SetINT_ENA_TIMER0_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *PWM_Type) GetINT_ENA_TIMER0_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *PWM_Type) SetINT_ENA_TIMER1_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *PWM_Type) GetINT_ENA_TIMER1_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *PWM_Type) SetINT_ENA_TIMER2_TEP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetINT_ENA_TIMER2_TEP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetINT_ENA_FAULT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetINT_ENA_FAULT0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *PWM_Type) SetINT_ENA_FAULT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetINT_ENA_FAULT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetINT_ENA_FAULT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetINT_ENA_FAULT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetINT_ENA_FAULT0_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetINT_ENA_FAULT0_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetINT_ENA_FAULT1_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetINT_ENA_FAULT1_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetINT_ENA_FAULT2_CLR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *PWM_Type) GetINT_ENA_FAULT2_CLR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *PWM_Type) SetINT_ENA_CMPR0_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *PWM_Type) GetINT_ENA_CMPR0_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *PWM_Type) SetINT_ENA_CMPR1_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetINT_ENA_CMPR1_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *PWM_Type) SetINT_ENA_CMPR2_TEA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *PWM_Type) GetINT_ENA_CMPR2_TEA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *PWM_Type) SetINT_ENA_CMPR0_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *PWM_Type) GetINT_ENA_CMPR0_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *PWM_Type) SetINT_ENA_CMPR1_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *PWM_Type) GetINT_ENA_CMPR1_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *PWM_Type) SetINT_ENA_CMPR2_TEB_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *PWM_Type) GetINT_ENA_CMPR2_TEB_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *PWM_Type) SetINT_ENA_TZ0_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *PWM_Type) GetINT_ENA_TZ0_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *PWM_Type) SetINT_ENA_TZ1_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22) +} +func (o *PWM_Type) GetINT_ENA_TZ1_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22 +} +func (o *PWM_Type) SetINT_ENA_TZ2_CBC_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23) +} +func (o *PWM_Type) GetINT_ENA_TZ2_CBC_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23 +} +func (o *PWM_Type) SetINT_ENA_TZ0_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *PWM_Type) GetINT_ENA_TZ0_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *PWM_Type) SetINT_ENA_TZ1_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25) +} +func (o *PWM_Type) GetINT_ENA_TZ1_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25 +} +func (o *PWM_Type) SetINT_ENA_TZ2_OST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26) +} +func (o *PWM_Type) GetINT_ENA_TZ2_OST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26 +} +func (o *PWM_Type) SetINT_ENA_CAP0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27) +} +func (o *PWM_Type) GetINT_ENA_CAP0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27 +} +func (o *PWM_Type) SetINT_ENA_CAP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *PWM_Type) GetINT_ENA_CAP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *PWM_Type) SetINT_ENA_CAP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *PWM_Type) GetINT_ENA_CAP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} + +// PWM.INT_RAW: Raw interrupt status +func (o *PWM_Type) SetINT_RAW_TIMER0_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetINT_RAW_TIMER0_STOP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *PWM_Type) SetINT_RAW_TIMER1_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetINT_RAW_TIMER1_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetINT_RAW_TIMER2_STOP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetINT_RAW_TIMER2_STOP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *PWM_Type) SetINT_RAW_TIMER0_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetINT_RAW_TIMER0_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetINT_RAW_TIMER1_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetINT_RAW_TIMER1_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *PWM_Type) SetINT_RAW_TIMER2_TEZ_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetINT_RAW_TIMER2_TEZ_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *PWM_Type) SetINT_RAW_TIMER0_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *PWM_Type) GetINT_RAW_TIMER0_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *PWM_Type) SetINT_RAW_TIMER1_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *PWM_Type) GetINT_RAW_TIMER1_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *PWM_Type) SetINT_RAW_TIMER2_TEP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetINT_RAW_TIMER2_TEP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetINT_RAW_FAULT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetINT_RAW_FAULT0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *PWM_Type) SetINT_RAW_FAULT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetINT_RAW_FAULT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetINT_RAW_FAULT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetINT_RAW_FAULT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetINT_RAW_FAULT0_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetINT_RAW_FAULT0_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetINT_RAW_FAULT1_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetINT_RAW_FAULT1_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetINT_RAW_FAULT2_CLR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *PWM_Type) GetINT_RAW_FAULT2_CLR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *PWM_Type) SetINT_RAW_CMPR0_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *PWM_Type) GetINT_RAW_CMPR0_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *PWM_Type) SetINT_RAW_CMPR1_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetINT_RAW_CMPR1_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *PWM_Type) SetINT_RAW_CMPR2_TEA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *PWM_Type) GetINT_RAW_CMPR2_TEA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *PWM_Type) SetINT_RAW_CMPR0_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *PWM_Type) GetINT_RAW_CMPR0_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *PWM_Type) SetINT_RAW_CMPR1_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *PWM_Type) GetINT_RAW_CMPR1_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *PWM_Type) SetINT_RAW_CMPR2_TEB_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *PWM_Type) GetINT_RAW_CMPR2_TEB_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *PWM_Type) SetINT_RAW_TZ0_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *PWM_Type) GetINT_RAW_TZ0_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *PWM_Type) SetINT_RAW_TZ1_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22) +} +func (o *PWM_Type) GetINT_RAW_TZ1_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22 +} +func (o *PWM_Type) SetINT_RAW_TZ2_CBC_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23) +} +func (o *PWM_Type) GetINT_RAW_TZ2_CBC_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23 +} +func (o *PWM_Type) SetINT_RAW_TZ0_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *PWM_Type) GetINT_RAW_TZ0_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *PWM_Type) SetINT_RAW_TZ1_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25) +} +func (o *PWM_Type) GetINT_RAW_TZ1_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25 +} +func (o *PWM_Type) SetINT_RAW_TZ2_OST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26) +} +func (o *PWM_Type) GetINT_RAW_TZ2_OST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26 +} +func (o *PWM_Type) SetINT_RAW_CAP0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27) +} +func (o *PWM_Type) GetINT_RAW_CAP0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27 +} +func (o *PWM_Type) SetINT_RAW_CAP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *PWM_Type) GetINT_RAW_CAP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *PWM_Type) SetINT_RAW_CAP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *PWM_Type) GetINT_RAW_CAP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} + +// PWM.INT_ST: Masked interrupt status +func (o *PWM_Type) SetINT_ST_TIMER0_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetINT_ST_TIMER0_STOP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *PWM_Type) SetINT_ST_TIMER1_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetINT_ST_TIMER1_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetINT_ST_TIMER2_STOP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetINT_ST_TIMER2_STOP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *PWM_Type) SetINT_ST_TIMER0_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetINT_ST_TIMER0_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetINT_ST_TIMER1_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetINT_ST_TIMER1_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *PWM_Type) SetINT_ST_TIMER2_TEZ_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetINT_ST_TIMER2_TEZ_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *PWM_Type) SetINT_ST_TIMER0_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *PWM_Type) GetINT_ST_TIMER0_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *PWM_Type) SetINT_ST_TIMER1_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *PWM_Type) GetINT_ST_TIMER1_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *PWM_Type) SetINT_ST_TIMER2_TEP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetINT_ST_TIMER2_TEP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetINT_ST_FAULT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetINT_ST_FAULT0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *PWM_Type) SetINT_ST_FAULT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetINT_ST_FAULT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetINT_ST_FAULT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetINT_ST_FAULT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetINT_ST_FAULT0_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetINT_ST_FAULT0_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetINT_ST_FAULT1_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetINT_ST_FAULT1_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetINT_ST_FAULT2_CLR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *PWM_Type) GetINT_ST_FAULT2_CLR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *PWM_Type) SetINT_ST_CMPR0_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *PWM_Type) GetINT_ST_CMPR0_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *PWM_Type) SetINT_ST_CMPR1_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetINT_ST_CMPR1_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *PWM_Type) SetINT_ST_CMPR2_TEA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *PWM_Type) GetINT_ST_CMPR2_TEA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *PWM_Type) SetINT_ST_CMPR0_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *PWM_Type) GetINT_ST_CMPR0_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *PWM_Type) SetINT_ST_CMPR1_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *PWM_Type) GetINT_ST_CMPR1_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} +func (o *PWM_Type) SetINT_ST_CMPR2_TEB_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *PWM_Type) GetINT_ST_CMPR2_TEB_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *PWM_Type) SetINT_ST_TZ0_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21) +} +func (o *PWM_Type) GetINT_ST_TZ0_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21 +} +func (o *PWM_Type) SetINT_ST_TZ1_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22) +} +func (o *PWM_Type) GetINT_ST_TZ1_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22 +} +func (o *PWM_Type) SetINT_ST_TZ2_CBC_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23) +} +func (o *PWM_Type) GetINT_ST_TZ2_CBC_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23 +} +func (o *PWM_Type) SetINT_ST_TZ0_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *PWM_Type) GetINT_ST_TZ0_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *PWM_Type) SetINT_ST_TZ1_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *PWM_Type) GetINT_ST_TZ1_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25 +} +func (o *PWM_Type) SetINT_ST_TZ2_OST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *PWM_Type) GetINT_ST_TZ2_OST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26 +} +func (o *PWM_Type) SetINT_ST_CAP0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *PWM_Type) GetINT_ST_CAP0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27 +} +func (o *PWM_Type) SetINT_ST_CAP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *PWM_Type) GetINT_ST_CAP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *PWM_Type) SetINT_ST_CAP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *PWM_Type) GetINT_ST_CAP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} + +// PWM.INT_CLR: Interrupt clear bits +func (o *PWM_Type) SetINT_CLR_TIMER0_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetINT_CLR_TIMER0_STOP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *PWM_Type) SetINT_CLR_TIMER1_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *PWM_Type) GetINT_CLR_TIMER1_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *PWM_Type) SetINT_CLR_TIMER2_STOP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *PWM_Type) GetINT_CLR_TIMER2_STOP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *PWM_Type) SetINT_CLR_TIMER0_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *PWM_Type) GetINT_CLR_TIMER0_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *PWM_Type) SetINT_CLR_TIMER1_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *PWM_Type) GetINT_CLR_TIMER1_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *PWM_Type) SetINT_CLR_TIMER2_TEZ_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *PWM_Type) GetINT_CLR_TIMER2_TEZ_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *PWM_Type) SetINT_CLR_TIMER0_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *PWM_Type) GetINT_CLR_TIMER0_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *PWM_Type) SetINT_CLR_TIMER1_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *PWM_Type) GetINT_CLR_TIMER1_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *PWM_Type) SetINT_CLR_TIMER2_TEP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *PWM_Type) GetINT_CLR_TIMER2_TEP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *PWM_Type) SetINT_CLR_FAULT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *PWM_Type) GetINT_CLR_FAULT0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *PWM_Type) SetINT_CLR_FAULT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *PWM_Type) GetINT_CLR_FAULT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *PWM_Type) SetINT_CLR_FAULT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *PWM_Type) GetINT_CLR_FAULT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *PWM_Type) SetINT_CLR_FAULT0_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *PWM_Type) GetINT_CLR_FAULT0_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *PWM_Type) SetINT_CLR_FAULT1_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *PWM_Type) GetINT_CLR_FAULT1_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *PWM_Type) SetINT_CLR_FAULT2_CLR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *PWM_Type) GetINT_CLR_FAULT2_CLR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *PWM_Type) SetINT_CLR_CMPR0_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *PWM_Type) GetINT_CLR_CMPR0_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *PWM_Type) SetINT_CLR_CMPR1_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *PWM_Type) GetINT_CLR_CMPR1_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *PWM_Type) SetINT_CLR_CMPR2_TEA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *PWM_Type) GetINT_CLR_CMPR2_TEA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *PWM_Type) SetINT_CLR_CMPR0_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *PWM_Type) GetINT_CLR_CMPR0_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *PWM_Type) SetINT_CLR_CMPR1_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *PWM_Type) GetINT_CLR_CMPR1_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *PWM_Type) SetINT_CLR_CMPR2_TEB_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *PWM_Type) GetINT_CLR_CMPR2_TEB_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *PWM_Type) SetINT_CLR_TZ0_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *PWM_Type) GetINT_CLR_TZ0_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *PWM_Type) SetINT_CLR_TZ1_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22) +} +func (o *PWM_Type) GetINT_CLR_TZ1_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22 +} +func (o *PWM_Type) SetINT_CLR_TZ2_CBC_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23) +} +func (o *PWM_Type) GetINT_CLR_TZ2_CBC_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23 +} +func (o *PWM_Type) SetINT_CLR_TZ0_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *PWM_Type) GetINT_CLR_TZ0_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *PWM_Type) SetINT_CLR_TZ1_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25) +} +func (o *PWM_Type) GetINT_CLR_TZ1_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25 +} +func (o *PWM_Type) SetINT_CLR_TZ2_OST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26) +} +func (o *PWM_Type) GetINT_CLR_TZ2_OST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26 +} +func (o *PWM_Type) SetINT_CLR_CAP0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27) +} +func (o *PWM_Type) GetINT_CLR_CAP0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27 +} +func (o *PWM_Type) SetINT_CLR_CAP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *PWM_Type) GetINT_CLR_CAP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *PWM_Type) SetINT_CLR_CAP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *PWM_Type) GetINT_CLR_CAP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} + +// PWM.CLK: MCPWM APB configuration register +func (o *PWM_Type) SetCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value) +} +func (o *PWM_Type) GetCLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK.Reg) & 0x1 +} + +// PWM.VERSION: Version register. +func (o *PWM_Type) SetVERSION_DATE(value uint32) { + volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value) +} +func (o *PWM_Type) GetVERSION_DATE() uint32 { + return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff +} + +// Remote Control +type RMT_Type struct { + CH0DATA volatile.Register32 // 0x0 + CH1DATA volatile.Register32 // 0x4 + CH2DATA volatile.Register32 // 0x8 + CH3DATA volatile.Register32 // 0xC + CH4DATA volatile.Register32 // 0x10 + CH5DATA volatile.Register32 // 0x14 + CH6DATA volatile.Register32 // 0x18 + CH7DATA volatile.Register32 // 0x1C + CH0_TX_CONF0 volatile.Register32 // 0x20 + CH1_TX_CONF0 volatile.Register32 // 0x24 + CH2_TX_CONF0 volatile.Register32 // 0x28 + CH3_TX_CONF0 volatile.Register32 // 0x2C + CH4_RX_CONF0 volatile.Register32 // 0x30 + CH4_RX_CONF1 volatile.Register32 // 0x34 + CH5_RX_CONF0 volatile.Register32 // 0x38 + CH5_RX_CONF1 volatile.Register32 // 0x3C + CH6_RX_CONF0 volatile.Register32 // 0x40 + CH6_RX_CONF1 volatile.Register32 // 0x44 + CH7_RX_CONF0 volatile.Register32 // 0x48 + CH7_RX_CONF1 volatile.Register32 // 0x4C + CH0_TX_STATUS volatile.Register32 // 0x50 + CH1_TX_STATUS volatile.Register32 // 0x54 + CH2_TX_STATUS volatile.Register32 // 0x58 + CH3_TX_STATUS volatile.Register32 // 0x5C + CH0_RX_STATUS volatile.Register32 // 0x60 + CH1_RX_STATUS volatile.Register32 // 0x64 + CH2_RX_STATUS volatile.Register32 // 0x68 + CH3_RX_STATUS volatile.Register32 // 0x6C + INT_RAW volatile.Register32 // 0x70 + INT_ST volatile.Register32 // 0x74 + INT_ENA volatile.Register32 // 0x78 + INT_CLR volatile.Register32 // 0x7C + CH0CARRIER_DUTY volatile.Register32 // 0x80 + CH1CARRIER_DUTY volatile.Register32 // 0x84 + CH2CARRIER_DUTY volatile.Register32 // 0x88 + CH3CARRIER_DUTY volatile.Register32 // 0x8C + CH0_RX_CARRIER_RM volatile.Register32 // 0x90 + CH1_RX_CARRIER_RM volatile.Register32 // 0x94 + CH2_RX_CARRIER_RM volatile.Register32 // 0x98 + CH3_RX_CARRIER_RM volatile.Register32 // 0x9C + CH0_TX_LIM volatile.Register32 // 0xA0 + CH1_TX_LIM volatile.Register32 // 0xA4 + CH2_TX_LIM volatile.Register32 // 0xA8 + CH3_TX_LIM volatile.Register32 // 0xAC + CH0_RX_LIM volatile.Register32 // 0xB0 + CH1_RX_LIM volatile.Register32 // 0xB4 + CH2_RX_LIM volatile.Register32 // 0xB8 + CH3_RX_LIM volatile.Register32 // 0xBC + SYS_CONF volatile.Register32 // 0xC0 + TX_SIM volatile.Register32 // 0xC4 + REF_CNT_RST volatile.Register32 // 0xC8 + DATE volatile.Register32 // 0xCC +} + +// RMT.CH0DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH0DATA(value uint32) { + volatile.StoreUint32(&o.CH0DATA.Reg, value) +} +func (o *RMT_Type) GetCH0DATA() uint32 { + return volatile.LoadUint32(&o.CH0DATA.Reg) +} + +// RMT.CH1DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH1DATA(value uint32) { + volatile.StoreUint32(&o.CH1DATA.Reg, value) +} +func (o *RMT_Type) GetCH1DATA() uint32 { + return volatile.LoadUint32(&o.CH1DATA.Reg) +} + +// RMT.CH2DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH2DATA(value uint32) { + volatile.StoreUint32(&o.CH2DATA.Reg, value) +} +func (o *RMT_Type) GetCH2DATA() uint32 { + return volatile.LoadUint32(&o.CH2DATA.Reg) +} + +// RMT.CH3DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH3DATA(value uint32) { + volatile.StoreUint32(&o.CH3DATA.Reg, value) +} +func (o *RMT_Type) GetCH3DATA() uint32 { + return volatile.LoadUint32(&o.CH3DATA.Reg) +} + +// RMT.CH4DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH4DATA(value uint32) { + volatile.StoreUint32(&o.CH4DATA.Reg, value) +} +func (o *RMT_Type) GetCH4DATA() uint32 { + return volatile.LoadUint32(&o.CH4DATA.Reg) +} + +// RMT.CH5DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH5DATA(value uint32) { + volatile.StoreUint32(&o.CH5DATA.Reg, value) +} +func (o *RMT_Type) GetCH5DATA() uint32 { + return volatile.LoadUint32(&o.CH5DATA.Reg) +} + +// RMT.CH6DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH6DATA(value uint32) { + volatile.StoreUint32(&o.CH6DATA.Reg, value) +} +func (o *RMT_Type) GetCH6DATA() uint32 { + return volatile.LoadUint32(&o.CH6DATA.Reg) +} + +// RMT.CH7DATA: The read and write data register for CHANNEL%s by apb fifo access. +func (o *RMT_Type) SetCH7DATA(value uint32) { + volatile.StoreUint32(&o.CH7DATA.Reg, value) +} +func (o *RMT_Type) GetCH7DATA() uint32 { + return volatile.LoadUint32(&o.CH7DATA.Reg) +} + +// RMT.CH0_TX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH0_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH0_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH0_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH0_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH0_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH0_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH0_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH0_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH0_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH0_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH0_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH0_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH0_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0xf0000)|value<<16) +} +func (o *RMT_Type) GetCH0_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0xf0000) >> 16 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH0_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH0_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH0_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_CONF0.Reg, volatile.LoadUint32(&o.CH0_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH0_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH1_TX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH1_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH1_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH1_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH1_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH1_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH1_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH1_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH1_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH1_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH1_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH1_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH1_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH1_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0xf0000)|value<<16) +} +func (o *RMT_Type) GetCH1_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0xf0000) >> 16 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH1_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH1_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH1_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_CONF0.Reg, volatile.LoadUint32(&o.CH1_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH1_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH2_TX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH2_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH2_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH2_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH2_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH2_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH2_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH2_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH2_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH2_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH2_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH2_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH2_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH2_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH2_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH2_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH2_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH2_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH2_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH2_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0xf0000)|value<<16) +} +func (o *RMT_Type) GetCH2_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0xf0000) >> 16 +} +func (o *RMT_Type) SetCH2_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH2_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH2_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH2_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH2_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH2_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH2_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH2_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH2_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH2_TX_CONF0.Reg, volatile.LoadUint32(&o.CH2_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH2_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH3_TX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH3_TX_CONF0_TX_START(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH3_TX_CONF0_TX_START() uint32 { + return volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x1 +} +func (o *RMT_Type) SetCH3_TX_CONF0_MEM_RD_RST(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH3_TX_CONF0_MEM_RD_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH3_TX_CONF0_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH3_TX_CONF0_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH3_TX_CONF0_TX_CONTI_MODE(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH3_TX_CONF0_TX_CONTI_MODE() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH3_TX_CONF0_MEM_TX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH3_TX_CONF0_MEM_TX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH3_TX_CONF0_IDLE_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *RMT_Type) GetCH3_TX_CONF0_IDLE_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x20) >> 5 +} +func (o *RMT_Type) SetCH3_TX_CONF0_IDLE_OUT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *RMT_Type) GetCH3_TX_CONF0_IDLE_OUT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x40) >> 6 +} +func (o *RMT_Type) SetCH3_TX_CONF0_TX_STOP(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *RMT_Type) GetCH3_TX_CONF0_TX_STOP() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x80) >> 7 +} +func (o *RMT_Type) SetCH3_TX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *RMT_Type) GetCH3_TX_CONF0_DIV_CNT() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0xff00) >> 8 +} +func (o *RMT_Type) SetCH3_TX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0xf0000)|value<<16) +} +func (o *RMT_Type) GetCH3_TX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0xf0000) >> 16 +} +func (o *RMT_Type) SetCH3_TX_CONF0_CARRIER_EFF_EN(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH3_TX_CONF0_CARRIER_EFF_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH3_TX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH3_TX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x200000) >> 21 +} +func (o *RMT_Type) SetCH3_TX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *RMT_Type) GetCH3_TX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x400000) >> 22 +} +func (o *RMT_Type) SetCH3_TX_CONF0_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *RMT_Type) GetCH3_TX_CONF0_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x800000) >> 23 +} +func (o *RMT_Type) SetCH3_TX_CONF0_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH3_TX_CONF0.Reg, volatile.LoadUint32(&o.CH3_TX_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetCH3_TX_CONF0_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_CONF0.Reg) & 0x1000000) >> 24 +} + +// RMT.CH4_RX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH4_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF0.Reg, volatile.LoadUint32(&o.CH4_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH4_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH4_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH4_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF0.Reg, volatile.LoadUint32(&o.CH4_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH4_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH4_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF0.Reg, volatile.LoadUint32(&o.CH4_RX_CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH4_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH4_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF0.Reg, volatile.LoadUint32(&o.CH4_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH4_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH4_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF0.Reg, volatile.LoadUint32(&o.CH4_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH4_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH4_RX_CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH4_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF1.Reg, volatile.LoadUint32(&o.CH4_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH4_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH4_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH4_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF1.Reg, volatile.LoadUint32(&o.CH4_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH4_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH4_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF1.Reg, volatile.LoadUint32(&o.CH4_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH4_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH4_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF1.Reg, volatile.LoadUint32(&o.CH4_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH4_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH4_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF1.Reg, volatile.LoadUint32(&o.CH4_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH4_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH4_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF1.Reg, volatile.LoadUint32(&o.CH4_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH4_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH4_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF1.Reg, volatile.LoadUint32(&o.CH4_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH4_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH4_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF1.Reg, volatile.LoadUint32(&o.CH4_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH4_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH4_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH4_RX_CONF1.Reg, volatile.LoadUint32(&o.CH4_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH4_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH4_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH5_RX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH5_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF0.Reg, volatile.LoadUint32(&o.CH5_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH5_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH5_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH5_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF0.Reg, volatile.LoadUint32(&o.CH5_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH5_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH5_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF0.Reg, volatile.LoadUint32(&o.CH5_RX_CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH5_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH5_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF0.Reg, volatile.LoadUint32(&o.CH5_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH5_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH5_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF0.Reg, volatile.LoadUint32(&o.CH5_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH5_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH5_RX_CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH5_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF1.Reg, volatile.LoadUint32(&o.CH5_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH5_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH5_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH5_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF1.Reg, volatile.LoadUint32(&o.CH5_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH5_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH5_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF1.Reg, volatile.LoadUint32(&o.CH5_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH5_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH5_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF1.Reg, volatile.LoadUint32(&o.CH5_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH5_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH5_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF1.Reg, volatile.LoadUint32(&o.CH5_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH5_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH5_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF1.Reg, volatile.LoadUint32(&o.CH5_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH5_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH5_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF1.Reg, volatile.LoadUint32(&o.CH5_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH5_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH5_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF1.Reg, volatile.LoadUint32(&o.CH5_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH5_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH5_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH5_RX_CONF1.Reg, volatile.LoadUint32(&o.CH5_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH5_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH5_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH6_RX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH6_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF0.Reg, volatile.LoadUint32(&o.CH6_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH6_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH6_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH6_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF0.Reg, volatile.LoadUint32(&o.CH6_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH6_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH6_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF0.Reg, volatile.LoadUint32(&o.CH6_RX_CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH6_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH6_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF0.Reg, volatile.LoadUint32(&o.CH6_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH6_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH6_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF0.Reg, volatile.LoadUint32(&o.CH6_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH6_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH6_RX_CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH6_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF1.Reg, volatile.LoadUint32(&o.CH6_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH6_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH6_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH6_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF1.Reg, volatile.LoadUint32(&o.CH6_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH6_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH6_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF1.Reg, volatile.LoadUint32(&o.CH6_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH6_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH6_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF1.Reg, volatile.LoadUint32(&o.CH6_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH6_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH6_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF1.Reg, volatile.LoadUint32(&o.CH6_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH6_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH6_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF1.Reg, volatile.LoadUint32(&o.CH6_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH6_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH6_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF1.Reg, volatile.LoadUint32(&o.CH6_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH6_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH6_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF1.Reg, volatile.LoadUint32(&o.CH6_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH6_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH6_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH6_RX_CONF1.Reg, volatile.LoadUint32(&o.CH6_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH6_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH6_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH7_RX_CONF0: Channel %s configure register 0 +func (o *RMT_Type) SetCH7_RX_CONF0_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF0.Reg, volatile.LoadUint32(&o.CH7_RX_CONF0.Reg)&^(0xff)|value) +} +func (o *RMT_Type) GetCH7_RX_CONF0_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.CH7_RX_CONF0.Reg) & 0xff +} +func (o *RMT_Type) SetCH7_RX_CONF0_IDLE_THRES(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF0.Reg, volatile.LoadUint32(&o.CH7_RX_CONF0.Reg)&^(0x7fff00)|value<<8) +} +func (o *RMT_Type) GetCH7_RX_CONF0_IDLE_THRES() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF0.Reg) & 0x7fff00) >> 8 +} +func (o *RMT_Type) SetCH7_RX_CONF0_MEM_SIZE(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF0.Reg, volatile.LoadUint32(&o.CH7_RX_CONF0.Reg)&^(0xf000000)|value<<24) +} +func (o *RMT_Type) GetCH7_RX_CONF0_MEM_SIZE() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF0.Reg) & 0xf000000) >> 24 +} +func (o *RMT_Type) SetCH7_RX_CONF0_CARRIER_EN(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF0.Reg, volatile.LoadUint32(&o.CH7_RX_CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetCH7_RX_CONF0_CARRIER_EN() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF0.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetCH7_RX_CONF0_CARRIER_OUT_LV(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF0.Reg, volatile.LoadUint32(&o.CH7_RX_CONF0.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetCH7_RX_CONF0_CARRIER_OUT_LV() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF0.Reg) & 0x20000000) >> 29 +} + +// RMT.CH7_RX_CONF1: Channel %s configure register 1 +func (o *RMT_Type) SetCH7_RX_CONF1_RX_EN(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF1.Reg, volatile.LoadUint32(&o.CH7_RX_CONF1.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetCH7_RX_CONF1_RX_EN() uint32 { + return volatile.LoadUint32(&o.CH7_RX_CONF1.Reg) & 0x1 +} +func (o *RMT_Type) SetCH7_RX_CONF1_MEM_WR_RST(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF1.Reg, volatile.LoadUint32(&o.CH7_RX_CONF1.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetCH7_RX_CONF1_MEM_WR_RST() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF1.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetCH7_RX_CONF1_APB_MEM_RST(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF1.Reg, volatile.LoadUint32(&o.CH7_RX_CONF1.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetCH7_RX_CONF1_APB_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF1.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetCH7_RX_CONF1_MEM_OWNER(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF1.Reg, volatile.LoadUint32(&o.CH7_RX_CONF1.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetCH7_RX_CONF1_MEM_OWNER() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF1.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetCH7_RX_CONF1_RX_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF1.Reg, volatile.LoadUint32(&o.CH7_RX_CONF1.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetCH7_RX_CONF1_RX_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF1.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetCH7_RX_CONF1_RX_FILTER_THRES(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF1.Reg, volatile.LoadUint32(&o.CH7_RX_CONF1.Reg)&^(0x1fe0)|value<<5) +} +func (o *RMT_Type) GetCH7_RX_CONF1_RX_FILTER_THRES() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF1.Reg) & 0x1fe0) >> 5 +} +func (o *RMT_Type) SetCH7_RX_CONF1_MEM_RX_WRAP_EN(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF1.Reg, volatile.LoadUint32(&o.CH7_RX_CONF1.Reg)&^(0x2000)|value<<13) +} +func (o *RMT_Type) GetCH7_RX_CONF1_MEM_RX_WRAP_EN() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF1.Reg) & 0x2000) >> 13 +} +func (o *RMT_Type) SetCH7_RX_CONF1_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF1.Reg, volatile.LoadUint32(&o.CH7_RX_CONF1.Reg)&^(0x4000)|value<<14) +} +func (o *RMT_Type) GetCH7_RX_CONF1_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF1.Reg) & 0x4000) >> 14 +} +func (o *RMT_Type) SetCH7_RX_CONF1_CONF_UPDATE(value uint32) { + volatile.StoreUint32(&o.CH7_RX_CONF1.Reg, volatile.LoadUint32(&o.CH7_RX_CONF1.Reg)&^(0x8000)|value<<15) +} +func (o *RMT_Type) GetCH7_RX_CONF1_CONF_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CH7_RX_CONF1.Reg) & 0x8000) >> 15 +} + +// RMT.CH0_TX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH0_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH0_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetCH0_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH0_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH0_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH0_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH0_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_TX_STATUS.Reg, volatile.LoadUint32(&o.CH0_TX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH0_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_STATUS.Reg) & 0x4000000) >> 26 +} + +// RMT.CH1_TX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH1_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH1_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetCH1_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH1_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH1_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH1_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH1_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_TX_STATUS.Reg, volatile.LoadUint32(&o.CH1_TX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH1_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_STATUS.Reg) & 0x4000000) >> 26 +} + +// RMT.CH2_TX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH2_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH2_TX_STATUS.Reg, volatile.LoadUint32(&o.CH2_TX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH2_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH2_TX_STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH2_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH2_TX_STATUS.Reg, volatile.LoadUint32(&o.CH2_TX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetCH2_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetCH2_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH2_TX_STATUS.Reg, volatile.LoadUint32(&o.CH2_TX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH2_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH2_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH2_TX_STATUS.Reg, volatile.LoadUint32(&o.CH2_TX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH2_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH2_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH2_TX_STATUS.Reg, volatile.LoadUint32(&o.CH2_TX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH2_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_STATUS.Reg) & 0x4000000) >> 26 +} + +// RMT.CH3_TX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH3_TX_STATUS_MEM_RADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH3_TX_STATUS.Reg, volatile.LoadUint32(&o.CH3_TX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH3_TX_STATUS_MEM_RADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH3_TX_STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH3_TX_STATUS_APB_MEM_WADDR(value uint32) { + volatile.StoreUint32(&o.CH3_TX_STATUS.Reg, volatile.LoadUint32(&o.CH3_TX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetCH3_TX_STATUS_APB_MEM_WADDR() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetCH3_TX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH3_TX_STATUS.Reg, volatile.LoadUint32(&o.CH3_TX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH3_TX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH3_TX_STATUS_MEM_EMPTY(value uint32) { + volatile.StoreUint32(&o.CH3_TX_STATUS.Reg, volatile.LoadUint32(&o.CH3_TX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH3_TX_STATUS_MEM_EMPTY() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH3_TX_STATUS_APB_MEM_WR_ERR(value uint32) { + volatile.StoreUint32(&o.CH3_TX_STATUS.Reg, volatile.LoadUint32(&o.CH3_TX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH3_TX_STATUS_APB_MEM_WR_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_STATUS.Reg) & 0x4000000) >> 26 +} + +// RMT.CH0_RX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH0_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH0_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH0_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetCH0_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetCH0_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH0_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH0_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH0_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH0_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH0_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH0_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH0_RX_STATUS.Reg, volatile.LoadUint32(&o.CH0_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH0_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH1_RX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH1_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH1_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH1_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetCH1_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetCH1_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH1_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH1_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH1_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH1_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH1_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH1_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH1_RX_STATUS.Reg, volatile.LoadUint32(&o.CH1_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH1_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH2_RX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH2_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH2_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH2_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetCH2_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetCH2_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH2_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH2_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH2_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH2_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH2_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH2_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH2_RX_STATUS.Reg, volatile.LoadUint32(&o.CH2_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH2_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.CH3_RX_STATUS: Channel %s status register +func (o *RMT_Type) SetCH3_RX_STATUS_MEM_WADDR_EX(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *RMT_Type) GetCH3_RX_STATUS_MEM_WADDR_EX() uint32 { + return volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x3ff +} +func (o *RMT_Type) SetCH3_RX_STATUS_APB_MEM_RADDR(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *RMT_Type) GetCH3_RX_STATUS_APB_MEM_RADDR() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x1ff800) >> 11 +} +func (o *RMT_Type) SetCH3_RX_STATUS_STATE(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x1c00000)|value<<22) +} +func (o *RMT_Type) GetCH3_RX_STATUS_STATE() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x1c00000) >> 22 +} +func (o *RMT_Type) SetCH3_RX_STATUS_MEM_OWNER_ERR(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x2000000)|value<<25) +} +func (o *RMT_Type) GetCH3_RX_STATUS_MEM_OWNER_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x2000000) >> 25 +} +func (o *RMT_Type) SetCH3_RX_STATUS_MEM_FULL(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetCH3_RX_STATUS_MEM_FULL() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetCH3_RX_STATUS_APB_MEM_RD_ERR(value uint32) { + volatile.StoreUint32(&o.CH3_RX_STATUS.Reg, volatile.LoadUint32(&o.CH3_RX_STATUS.Reg)&^(0x8000000)|value<<27) +} +func (o *RMT_Type) GetCH3_RX_STATUS_APB_MEM_RD_ERR() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_STATUS.Reg) & 0x8000000) >> 27 +} + +// RMT.INT_RAW: Raw interrupt status +func (o *RMT_Type) SetINT_RAW_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_RAW_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_RAW_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetINT_RAW_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_RAW_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetINT_RAW_TX_CH3_DMA_ACCESS_FAIL(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetINT_RAW_TX_CH3_DMA_ACCESS_FAIL() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetINT_RAW_RX_CH7_DMA_ACCESS_FAIL(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetINT_RAW_RX_CH7_DMA_ACCESS_FAIL() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29 +} + +// RMT.INT_ST: Masked interrupt status +func (o *RMT_Type) SetINT_ST_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ST_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ST_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetINT_ST_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_ST_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetINT_ST_TX_CH3_DMA_ACCESS_FAIL(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetINT_ST_TX_CH3_DMA_ACCESS_FAIL() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetINT_ST_RX_CH7_DMA_ACCESS_FAIL(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetINT_ST_RX_CH7_DMA_ACCESS_FAIL() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29 +} + +// RMT.INT_ENA: Interrupt enable bits +func (o *RMT_Type) SetINT_ENA_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_ENA_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_ENA_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetINT_ENA_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_ENA_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetINT_ENA_TX_CH3_DMA_ACCESS_FAIL(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetINT_ENA_TX_CH3_DMA_ACCESS_FAIL() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetINT_ENA_RX_CH7_DMA_ACCESS_FAIL(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetINT_ENA_RX_CH7_DMA_ACCESS_FAIL() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29 +} + +// RMT.INT_CLR: Interrupt clear bits +func (o *RMT_Type) SetINT_CLR_CH_s_TX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_END() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *RMT_Type) SetINT_CLR_CH_s_TX_LOOP(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *RMT_Type) GetINT_CLR_CH_s_TX_LOOP() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_END(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_END() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_ERR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_ERR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetINT_CLR_CH_s_RX_THR_EVENT(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24) +} +func (o *RMT_Type) GetINT_CLR_CH_s_RX_THR_EVENT() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24 +} +func (o *RMT_Type) SetINT_CLR_TX_CH3_DMA_ACCESS_FAIL(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28) +} +func (o *RMT_Type) GetINT_CLR_TX_CH3_DMA_ACCESS_FAIL() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28 +} +func (o *RMT_Type) SetINT_CLR_RX_CH7_DMA_ACCESS_FAIL(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29) +} +func (o *RMT_Type) GetINT_CLR_RX_CH7_DMA_ACCESS_FAIL() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29 +} + +// RMT.CH0CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH2CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH3CARRIER_DUTY: Channel %s duty cycle configuration register +func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_LOW(value uint32) { + volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_LOW() uint32 { + return volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff +} +func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_HIGH(value uint32) { + volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_HIGH() uint32 { + return (volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH1_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH2_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH3_RX_CARRIER_RM: Channel %s carrier remove register +func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff)|value) +} +func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES() uint32 { + return volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff +} +func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES(value uint32) { + volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16) +} +func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES() uint32 { + return (volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16 +} + +// RMT.CH0_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH0_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH0_TX_LIM_LOOP_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH0_TX_LIM_LOOP_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH1_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH1_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH1_TX_LIM_LOOP_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH1_TX_LIM_LOOP_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH2_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH2_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH2_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH2_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH2_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH2_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH2_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH2_TX_LIM_LOOP_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH2_TX_LIM_LOOP_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH3_TX_LIM: Channel %s Tx event configuration register +func (o *RMT_Type) SetCH3_TX_LIM_TX_LIM(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LIM() uint32 { + return volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x1ff +} +func (o *RMT_Type) SetCH3_TX_LIM_TX_LOOP_NUM(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x7fe00)|value<<9) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LOOP_NUM() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x7fe00) >> 9 +} +func (o *RMT_Type) SetCH3_TX_LIM_TX_LOOP_CNT_EN(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x80000)|value<<19) +} +func (o *RMT_Type) GetCH3_TX_LIM_TX_LOOP_CNT_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x80000) >> 19 +} +func (o *RMT_Type) SetCH3_TX_LIM_LOOP_COUNT_RESET(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x100000)|value<<20) +} +func (o *RMT_Type) GetCH3_TX_LIM_LOOP_COUNT_RESET() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x100000) >> 20 +} +func (o *RMT_Type) SetCH3_TX_LIM_LOOP_STOP_EN(value uint32) { + volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x200000)|value<<21) +} +func (o *RMT_Type) GetCH3_TX_LIM_LOOP_STOP_EN() uint32 { + return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x200000) >> 21 +} + +// RMT.CH0_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH0_RX_LIM_RX_LIM_CH4(value uint32) { + volatile.StoreUint32(&o.CH0_RX_LIM.Reg, volatile.LoadUint32(&o.CH0_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH0_RX_LIM_RX_LIM_CH4() uint32 { + return volatile.LoadUint32(&o.CH0_RX_LIM.Reg) & 0x1ff +} + +// RMT.CH1_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH1_RX_LIM_RX_LIM_CH4(value uint32) { + volatile.StoreUint32(&o.CH1_RX_LIM.Reg, volatile.LoadUint32(&o.CH1_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH1_RX_LIM_RX_LIM_CH4() uint32 { + return volatile.LoadUint32(&o.CH1_RX_LIM.Reg) & 0x1ff +} + +// RMT.CH2_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH2_RX_LIM_RX_LIM_CH4(value uint32) { + volatile.StoreUint32(&o.CH2_RX_LIM.Reg, volatile.LoadUint32(&o.CH2_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH2_RX_LIM_RX_LIM_CH4() uint32 { + return volatile.LoadUint32(&o.CH2_RX_LIM.Reg) & 0x1ff +} + +// RMT.CH3_RX_LIM: Channel %s Rx event configuration register +func (o *RMT_Type) SetCH3_RX_LIM_RX_LIM_CH4(value uint32) { + volatile.StoreUint32(&o.CH3_RX_LIM.Reg, volatile.LoadUint32(&o.CH3_RX_LIM.Reg)&^(0x1ff)|value) +} +func (o *RMT_Type) GetCH3_RX_LIM_RX_LIM_CH4() uint32 { + return volatile.LoadUint32(&o.CH3_RX_LIM.Reg) & 0x1ff +} + +// RMT.SYS_CONF: RMT apb configuration register +func (o *RMT_Type) SetSYS_CONF_APB_FIFO_MASK(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetSYS_CONF_APB_FIFO_MASK() uint32 { + return volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetSYS_CONF_MEM_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xff0)|value<<4) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xff0) >> 4 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3f000)|value<<12) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3f000) >> 12 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xfc0000)|value<<18) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_B() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xfc0000) >> 18 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3000000)|value<<24) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3000000) >> 24 +} +func (o *RMT_Type) SetSYS_CONF_SCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RMT_Type) GetSYS_CONF_SCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RMT_Type) SetSYS_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RMT_Type) GetSYS_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x80000000) >> 31 +} + +// RMT.TX_SIM: RMT TX synchronous register +func (o *RMT_Type) SetTX_SIM_CH0(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetTX_SIM_CH0() uint32 { + return volatile.LoadUint32(&o.TX_SIM.Reg) & 0x1 +} +func (o *RMT_Type) SetTX_SIM_CH1(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x2)|value<<1) +} +func (o *RMT_Type) GetTX_SIM_CH1() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x2) >> 1 +} +func (o *RMT_Type) SetTX_SIM_CH2(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x4)|value<<2) +} +func (o *RMT_Type) GetTX_SIM_CH2() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x4) >> 2 +} +func (o *RMT_Type) SetTX_SIM_CH3(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x8)|value<<3) +} +func (o *RMT_Type) GetTX_SIM_CH3() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x8) >> 3 +} +func (o *RMT_Type) SetTX_SIM_EN(value uint32) { + volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x10)|value<<4) +} +func (o *RMT_Type) GetTX_SIM_EN() uint32 { + return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x10) >> 4 +} + +// RMT.REF_CNT_RST: RMT clock divider reset register +func (o *RMT_Type) SetREF_CNT_RST_CH_s(value uint32) { + volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x1)|value) +} +func (o *RMT_Type) GetREF_CNT_RST_CH_s() uint32 { + return volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x1 +} + +// RMT.DATE: RMT version register +func (o *RMT_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RMT_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Hardware Random Number Generator +type RNG_Type struct { + _ [272]byte + DATA volatile.Register32 // 0x110 +} + +// RSA (Rivest Shamir Adleman) Accelerator +type RSA_Type struct { + M_MEM [512]volatile.Register8 // 0x0 + Z_MEM [512]volatile.Register8 // 0x200 + Y_MEM [512]volatile.Register8 // 0x400 + X_MEM [512]volatile.Register8 // 0x600 + M_PRIME volatile.Register32 // 0x800 + MODE volatile.Register32 // 0x804 + CLEAN volatile.Register32 // 0x808 + MODEXP_START volatile.Register32 // 0x80C + MODMULT_START volatile.Register32 // 0x810 + MULT_START volatile.Register32 // 0x814 + IDLE volatile.Register32 // 0x818 + CLEAR_INTERRUPT volatile.Register32 // 0x81C + CONSTANT_TIME volatile.Register32 // 0x820 + SEARCH_ENABLE volatile.Register32 // 0x824 + SEARCH_POS volatile.Register32 // 0x828 + INTERRUPT_ENA volatile.Register32 // 0x82C + DATE volatile.Register32 // 0x830 +} + +// RSA.M_PRIME: RSA M' register +func (o *RSA_Type) SetM_PRIME(value uint32) { + volatile.StoreUint32(&o.M_PRIME.Reg, value) +} +func (o *RSA_Type) GetM_PRIME() uint32 { + return volatile.LoadUint32(&o.M_PRIME.Reg) +} + +// RSA.MODE: RSA length mode register +func (o *RSA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7f)|value) +} +func (o *RSA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7f +} + +// RSA.CLEAN: RSA clean register +func (o *RSA_Type) SetCLEAN(value uint32) { + volatile.StoreUint32(&o.CLEAN.Reg, volatile.LoadUint32(&o.CLEAN.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCLEAN() uint32 { + return volatile.LoadUint32(&o.CLEAN.Reg) & 0x1 +} + +// RSA.MODEXP_START: Modular exponentiation trigger register. +func (o *RSA_Type) SetMODEXP_START(value uint32) { + volatile.StoreUint32(&o.MODEXP_START.Reg, volatile.LoadUint32(&o.MODEXP_START.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetMODEXP_START() uint32 { + return volatile.LoadUint32(&o.MODEXP_START.Reg) & 0x1 +} + +// RSA.MODMULT_START: Modular multiplication trigger register. +func (o *RSA_Type) SetMODMULT_START(value uint32) { + volatile.StoreUint32(&o.MODMULT_START.Reg, volatile.LoadUint32(&o.MODMULT_START.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetMODMULT_START() uint32 { + return volatile.LoadUint32(&o.MODMULT_START.Reg) & 0x1 +} + +// RSA.MULT_START: Normal multiplication trigger register. +func (o *RSA_Type) SetMULT_START(value uint32) { + volatile.StoreUint32(&o.MULT_START.Reg, volatile.LoadUint32(&o.MULT_START.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetMULT_START() uint32 { + return volatile.LoadUint32(&o.MULT_START.Reg) & 0x1 +} + +// RSA.IDLE: RSA idle register +func (o *RSA_Type) SetIDLE(value uint32) { + volatile.StoreUint32(&o.IDLE.Reg, volatile.LoadUint32(&o.IDLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetIDLE() uint32 { + return volatile.LoadUint32(&o.IDLE.Reg) & 0x1 +} + +// RSA.CLEAR_INTERRUPT: RSA interrupt clear register +func (o *RSA_Type) SetCLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CLEAR_INTERRUPT.Reg, volatile.LoadUint32(&o.CLEAR_INTERRUPT.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.CLEAR_INTERRUPT.Reg) & 0x1 +} + +// RSA.CONSTANT_TIME: CONSTANT_TIME option control register +func (o *RSA_Type) SetCONSTANT_TIME(value uint32) { + volatile.StoreUint32(&o.CONSTANT_TIME.Reg, volatile.LoadUint32(&o.CONSTANT_TIME.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetCONSTANT_TIME() uint32 { + return volatile.LoadUint32(&o.CONSTANT_TIME.Reg) & 0x1 +} + +// RSA.SEARCH_ENABLE: SEARCH option enable register +func (o *RSA_Type) SetSEARCH_ENABLE(value uint32) { + volatile.StoreUint32(&o.SEARCH_ENABLE.Reg, volatile.LoadUint32(&o.SEARCH_ENABLE.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetSEARCH_ENABLE() uint32 { + return volatile.LoadUint32(&o.SEARCH_ENABLE.Reg) & 0x1 +} + +// RSA.SEARCH_POS: RSA search position configure register +func (o *RSA_Type) SetSEARCH_POS(value uint32) { + volatile.StoreUint32(&o.SEARCH_POS.Reg, volatile.LoadUint32(&o.SEARCH_POS.Reg)&^(0xfff)|value) +} +func (o *RSA_Type) GetSEARCH_POS() uint32 { + return volatile.LoadUint32(&o.SEARCH_POS.Reg) & 0xfff +} + +// RSA.INTERRUPT_ENA: RSA interrupt enable register +func (o *RSA_Type) SetINTERRUPT_ENA(value uint32) { + volatile.StoreUint32(&o.INTERRUPT_ENA.Reg, volatile.LoadUint32(&o.INTERRUPT_ENA.Reg)&^(0x1)|value) +} +func (o *RSA_Type) GetINTERRUPT_ENA() uint32 { + return volatile.LoadUint32(&o.INTERRUPT_ENA.Reg) & 0x1 +} + +// RSA.DATE: RSA version control register +func (o *RSA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *RSA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Real-Time Clock Control +type RTC_CNTL_Type struct { + OPTIONS0 volatile.Register32 // 0x0 + SLP_TIMER0 volatile.Register32 // 0x4 + SLP_TIMER1 volatile.Register32 // 0x8 + TIME_UPDATE volatile.Register32 // 0xC + TIME_LOW0 volatile.Register32 // 0x10 + TIME_HIGH0 volatile.Register32 // 0x14 + STATE0 volatile.Register32 // 0x18 + TIMER1 volatile.Register32 // 0x1C + TIMER2 volatile.Register32 // 0x20 + TIMER3 volatile.Register32 // 0x24 + TIMER4 volatile.Register32 // 0x28 + TIMER5 volatile.Register32 // 0x2C + TIMER6 volatile.Register32 // 0x30 + ANA_CONF volatile.Register32 // 0x34 + RESET_STATE volatile.Register32 // 0x38 + WAKEUP_STATE volatile.Register32 // 0x3C + INT_ENA_RTC volatile.Register32 // 0x40 + INT_RAW_RTC volatile.Register32 // 0x44 + INT_ST_RTC volatile.Register32 // 0x48 + INT_CLR_RTC volatile.Register32 // 0x4C + STORE0 volatile.Register32 // 0x50 + STORE1 volatile.Register32 // 0x54 + STORE2 volatile.Register32 // 0x58 + STORE3 volatile.Register32 // 0x5C + EXT_XTL_CONF volatile.Register32 // 0x60 + EXT_WAKEUP_CONF volatile.Register32 // 0x64 + SLP_REJECT_CONF volatile.Register32 // 0x68 + CPU_PERIOD_CONF volatile.Register32 // 0x6C + SDIO_ACT_CONF volatile.Register32 // 0x70 + CLK_CONF volatile.Register32 // 0x74 + SLOW_CLK_CONF volatile.Register32 // 0x78 + SDIO_CONF volatile.Register32 // 0x7C + BIAS_CONF volatile.Register32 // 0x80 + RTC volatile.Register32 // 0x84 + PWC volatile.Register32 // 0x88 + REGULATOR_DRV_CTRL volatile.Register32 // 0x8C + DIG_PWC volatile.Register32 // 0x90 + DIG_ISO volatile.Register32 // 0x94 + WDTCONFIG0 volatile.Register32 // 0x98 + WDTCONFIG1 volatile.Register32 // 0x9C + WDTCONFIG2 volatile.Register32 // 0xA0 + WDTCONFIG3 volatile.Register32 // 0xA4 + WDTCONFIG4 volatile.Register32 // 0xA8 + WDTFEED volatile.Register32 // 0xAC + WDTWPROTECT volatile.Register32 // 0xB0 + SWD_CONF volatile.Register32 // 0xB4 + SWD_WPROTECT volatile.Register32 // 0xB8 + SW_CPU_STALL volatile.Register32 // 0xBC + STORE4 volatile.Register32 // 0xC0 + STORE5 volatile.Register32 // 0xC4 + STORE6 volatile.Register32 // 0xC8 + STORE7 volatile.Register32 // 0xCC + LOW_POWER_ST volatile.Register32 // 0xD0 + DIAG0 volatile.Register32 // 0xD4 + PAD_HOLD volatile.Register32 // 0xD8 + DIG_PAD_HOLD volatile.Register32 // 0xDC + EXT_WAKEUP1 volatile.Register32 // 0xE0 + EXT_WAKEUP1_STATUS volatile.Register32 // 0xE4 + BROWN_OUT volatile.Register32 // 0xE8 + TIME_LOW1 volatile.Register32 // 0xEC + TIME_HIGH1 volatile.Register32 // 0xF0 + XTAL32K_CLK_FACTOR volatile.Register32 // 0xF4 + XTAL32K_CONF volatile.Register32 // 0xF8 + ULP_CP_TIMER volatile.Register32 // 0xFC + ULP_CP_CTRL volatile.Register32 // 0x100 + COCPU_CTRL volatile.Register32 // 0x104 + TOUCH_CTRL1 volatile.Register32 // 0x108 + TOUCH_CTRL2 volatile.Register32 // 0x10C + TOUCH_SCAN_CTRL volatile.Register32 // 0x110 + TOUCH_SLP_THRES volatile.Register32 // 0x114 + TOUCH_APPROACH volatile.Register32 // 0x118 + TOUCH_FILTER_CTRL volatile.Register32 // 0x11C + USB_CONF volatile.Register32 // 0x120 + TOUCH_TIMEOUT_CTRL volatile.Register32 // 0x124 + SLP_REJECT_CAUSE volatile.Register32 // 0x128 + OPTION1 volatile.Register32 // 0x12C + SLP_WAKEUP_CAUSE volatile.Register32 // 0x130 + ULP_CP_TIMER_1 volatile.Register32 // 0x134 + INT_ENA_RTC_W1TS volatile.Register32 // 0x138 + INT_ENA_RTC_W1TC volatile.Register32 // 0x13C + RETENTION_CTRL volatile.Register32 // 0x140 + PG_CTRL volatile.Register32 // 0x144 + FIB_SEL volatile.Register32 // 0x148 + TOUCH_DAC volatile.Register32 // 0x14C + TOUCH_DAC1 volatile.Register32 // 0x150 + COCPU_DISABLE volatile.Register32 // 0x154 + _ [164]byte + DATE volatile.Register32 // 0x1FC +} + +// RTC_CNTL.OPTIONS0: RTC common configure register +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_STALL_APPCPU_C0(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_STALL_APPCPU_C0() uint32 { + return volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_STALL_PROCPU_C0(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0xc)|value<<2) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_STALL_PROCPU_C0() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0xc) >> 2 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_APPCPU_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_APPCPU_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_PROCPU_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_PROCPU_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BB_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BB_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_I2C_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_I2C_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_BBPLL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_BBPLL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_EN_WAIT(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x3c000)|value<<14) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_EN_WAIT() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x3c000) >> 14 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_PLL_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_PLL_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_XTL_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_XTL_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_PLL_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_PLL_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_ANALOG_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_ANALOG_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_DG_WRAP_FORCE_NORST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_DG_WRAP_FORCE_NORST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetOPTIONS0_SW_SYS_RST(value uint32) { + volatile.StoreUint32(&o.OPTIONS0.Reg, volatile.LoadUint32(&o.OPTIONS0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetOPTIONS0_SW_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.OPTIONS0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_TIMER0: configure min sleep time +func (o *RTC_CNTL_Type) SetSLP_TIMER0(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER0() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER0.Reg) +} + +// RTC_CNTL.SLP_TIMER1: configure sleep time hi +func (o *RTC_CNTL_Type) SetSLP_TIMER1_SLP_VAL_HI(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_SLP_VAL_HI() uint32 { + return volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0xffff +} +func (o *RTC_CNTL_Type) SetSLP_TIMER1_MAIN_TIMER_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.SLP_TIMER1.Reg, volatile.LoadUint32(&o.SLP_TIMER1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetSLP_TIMER1_MAIN_TIMER_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_TIMER1.Reg) & 0x10000) >> 16 +} + +// RTC_CNTL.TIME_UPDATE: update rtc main timer +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_SYS_STALL(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_SYS_STALL() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_XTL_OFF(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_XTL_OFF() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE_TIMER_SYS_RST(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE_TIMER_SYS_RST() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetTIME_UPDATE(value uint32) { + volatile.StoreUint32(&o.TIME_UPDATE.Reg, volatile.LoadUint32(&o.TIME_UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetTIME_UPDATE() uint32 { + return (volatile.LoadUint32(&o.TIME_UPDATE.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIME_LOW0: read rtc_main timer low bits +func (o *RTC_CNTL_Type) SetTIME_LOW0(value uint32) { + volatile.StoreUint32(&o.TIME_LOW0.Reg, value) +} +func (o *RTC_CNTL_Type) GetTIME_LOW0() uint32 { + return volatile.LoadUint32(&o.TIME_LOW0.Reg) +} + +// RTC_CNTL.TIME_HIGH0: read rtc_main timer high bits +func (o *RTC_CNTL_Type) SetTIME_HIGH0_TIMER_VALUE0_HIGH(value uint32) { + volatile.StoreUint32(&o.TIME_HIGH0.Reg, volatile.LoadUint32(&o.TIME_HIGH0.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTIME_HIGH0_TIMER_VALUE0_HIGH() uint32 { + return volatile.LoadUint32(&o.TIME_HIGH0.Reg) & 0xffff +} + +// RTC_CNTL.STATE0: configure chip sleep +func (o *RTC_CNTL_Type) SetSTATE0_SW_CPU_INT(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetSTATE0_SW_CPU_INT() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_REJECT_CAUSE_CLR(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_REJECT_CAUSE_CLR() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetSTATE0_APB2RTC_BRIDGE_SEL(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSTATE0_APB2RTC_BRIDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSTATE0_SDIO_ACTIVE_IND(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSTATE0_SDIO_ACTIVE_IND() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_WAKEUP(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLP_REJECT(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLP_REJECT() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSTATE0_SLEEP_EN(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSTATE0_SLEEP_EN() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIMER1: rtc state wait time +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_EN(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_EN() uint32 { + return volatile.LoadUint32(&o.TIMER1.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CPU_STALL_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3e)|value<<1) +} +func (o *RTC_CNTL_Type) GetTIMER1_CPU_STALL_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3e) >> 1 +} +func (o *RTC_CNTL_Type) SetTIMER1_CK8M_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0x3fc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetTIMER1_CK8M_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0x3fc0) >> 6 +} +func (o *RTC_CNTL_Type) SetTIMER1_XTL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xffc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetTIMER1_XTL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xffc000) >> 14 +} +func (o *RTC_CNTL_Type) SetTIMER1_PLL_BUF_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER1.Reg, volatile.LoadUint32(&o.TIMER1.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER1_PLL_BUF_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER1.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER2: rtc monitor state delay time +func (o *RTC_CNTL_Type) SetTIMER2_ULPCP_TOUCH_START_WAIT(value uint32) { + volatile.StoreUint32(&o.TIMER2.Reg, volatile.LoadUint32(&o.TIMER2.Reg)&^(0xff8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetTIMER2_ULPCP_TOUCH_START_WAIT() uint32 { + return (volatile.LoadUint32(&o.TIMER2.Reg) & 0xff8000) >> 15 +} +func (o *RTC_CNTL_Type) SetTIMER2_MIN_TIME_CK8M_OFF(value uint32) { + volatile.StoreUint32(&o.TIMER2.Reg, volatile.LoadUint32(&o.TIMER2.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTIMER2_MIN_TIME_CK8M_OFF() uint32 { + return (volatile.LoadUint32(&o.TIMER2.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TIMER3: No public +func (o *RTC_CNTL_Type) SetTIMER3_WIFI_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0x1ff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER3_WIFI_WAIT_TIMER() uint32 { + return volatile.LoadUint32(&o.TIMER3.Reg) & 0x1ff +} +func (o *RTC_CNTL_Type) SetTIMER3_WIFI_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0xfe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTIMER3_WIFI_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0xfe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTIMER3_BT_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER3_BT_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER3_BT_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER3.Reg, volatile.LoadUint32(&o.TIMER3.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER3_BT_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER3.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER4: No public +func (o *RTC_CNTL_Type) SetTIMER4_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0x1ff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER4_WAIT_TIMER() uint32 { + return volatile.LoadUint32(&o.TIMER4.Reg) & 0x1ff +} +func (o *RTC_CNTL_Type) SetTIMER4_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0xfe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTIMER4_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0xfe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER4_DG_WRAP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER4.Reg, volatile.LoadUint32(&o.TIMER4.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER4_DG_WRAP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER4.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.TIMER5: configure min sleep time +func (o *RTC_CNTL_Type) SetTIMER5_MIN_SLP_VAL(value uint32) { + volatile.StoreUint32(&o.TIMER5.Reg, volatile.LoadUint32(&o.TIMER5.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetTIMER5_MIN_SLP_VAL() uint32 { + return (volatile.LoadUint32(&o.TIMER5.Reg) & 0xff00) >> 8 +} + +// RTC_CNTL.TIMER6: No public +func (o *RTC_CNTL_Type) SetTIMER6_CPU_TOP_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER6.Reg, volatile.LoadUint32(&o.TIMER6.Reg)&^(0x1ff)|value) +} +func (o *RTC_CNTL_Type) GetTIMER6_CPU_TOP_WAIT_TIMER() uint32 { + return volatile.LoadUint32(&o.TIMER6.Reg) & 0x1ff +} +func (o *RTC_CNTL_Type) SetTIMER6_CPU_TOP_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER6.Reg, volatile.LoadUint32(&o.TIMER6.Reg)&^(0xfe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTIMER6_CPU_TOP_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER6.Reg) & 0xfe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTIMER6_DG_PERI_WAIT_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER6.Reg, volatile.LoadUint32(&o.TIMER6.Reg)&^(0x1ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTIMER6_DG_PERI_WAIT_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER6.Reg) & 0x1ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetTIMER6_DG_PERI_POWERUP_TIMER(value uint32) { + volatile.StoreUint32(&o.TIMER6.Reg, volatile.LoadUint32(&o.TIMER6.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTIMER6_DG_PERI_POWERUP_TIMER() uint32 { + return (volatile.LoadUint32(&o.TIMER6.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.ANA_CONF: analog configure register +func (o *RTC_CNTL_Type) SetANA_CONF_I2C_RESET_POR_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetANA_CONF_I2C_RESET_POR_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetANA_CONF_I2C_RESET_POR_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetANA_CONF_I2C_RESET_POR_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetANA_CONF_GLITCH_RST_EN(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetANA_CONF_GLITCH_RST_EN() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetANA_CONF_SAR_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetANA_CONF_SAR_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetANA_CONF_ANALOG_TOP_ISO_SLEEP(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetANA_CONF_ANALOG_TOP_ISO_SLEEP() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetANA_CONF_ANALOG_TOP_ISO_MONITOR(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetANA_CONF_ANALOG_TOP_ISO_MONITOR() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetANA_CONF_BBPLL_CAL_SLP_START(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetANA_CONF_BBPLL_CAL_SLP_START() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PVTMON_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PVTMON_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetANA_CONF_TXRF_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetANA_CONF_TXRF_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetANA_CONF_RFRX_PBUS_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetANA_CONF_RFRX_PBUS_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetANA_CONF_CKGEN_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetANA_CONF_CKGEN_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetANA_CONF_PLL_I2C_PU(value uint32) { + volatile.StoreUint32(&o.ANA_CONF.Reg, volatile.LoadUint32(&o.ANA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetANA_CONF_PLL_I2C_PU() uint32 { + return (volatile.LoadUint32(&o.ANA_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.RESET_STATE: get reset state +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_CAUSE_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x3f)|value) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_CAUSE_PROCPU() uint32 { + return volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x3f +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_CAUSE_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0xfc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_CAUSE_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0xfc0) >> 6 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_APPCPU_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_APPCPU_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_PROCPU_STAT_VECTOR_SEL(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_PROCPU_STAT_VECTOR_SEL() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_FLAG_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_FLAG_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_FLAG_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_FLAG_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_FLAG_PROCPU_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_FLAG_PROCPU_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_FLAG_APPCPU_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_FLAG_APPCPU_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_APPCPU_OCD_HALT_ON_RESET(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_APPCPU_OCD_HALT_ON_RESET() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_PROCPU_OCD_HALT_ON_RESET(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_PROCPU_OCD_HALT_ON_RESET() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_FLAG_JTAG_PROCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_FLAG_JTAG_PROCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_FLAG_JTAG_APPCPU(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_FLAG_JTAG_APPCPU() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_FLAG_JTAG_PROCPU_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_FLAG_JTAG_PROCPU_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_RESET_FLAG_JTAG_APPCPU_CLR(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_RESET_FLAG_JTAG_APPCPU_CLR() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_APP_DRESET_MASK(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_APP_DRESET_MASK() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetRESET_STATE_PRO_DRESET_MASK(value uint32) { + volatile.StoreUint32(&o.RESET_STATE.Reg, volatile.LoadUint32(&o.RESET_STATE.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetRESET_STATE_PRO_DRESET_MASK() uint32 { + return (volatile.LoadUint32(&o.RESET_STATE.Reg) & 0x2000000) >> 25 +} + +// RTC_CNTL.WAKEUP_STATE: configure wakeup state +func (o *RTC_CNTL_Type) SetWAKEUP_STATE_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.WAKEUP_STATE.Reg, volatile.LoadUint32(&o.WAKEUP_STATE.Reg)&^(0xffff8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetWAKEUP_STATE_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.WAKEUP_STATE.Reg) & 0xffff8000) >> 15 +} + +// RTC_CNTL.INT_ENA_RTC: configure rtc interrupt register +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SLP_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SLP_WAKEUP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SLP_REJECT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SLP_REJECT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SDIO_IDLE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SDIO_IDLE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_ULP_CP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_ULP_CP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_ACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_ACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_INACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_INACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_MAIN_TIMER_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_MAIN_TIMER_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SARADC1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SARADC1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TSENS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TSENS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_COCPU_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_COCPU_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SARADC2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SARADC2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_SWD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_SWD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_XTAL32K_DEAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_XTAL32K_DEAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_COCPU_TRAP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_COCPU_TRAP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_RAW_RTC: rtc interrupt register +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SLP_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SLP_WAKEUP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SLP_REJECT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SLP_REJECT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SDIO_IDLE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SDIO_IDLE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_ULP_CP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_ULP_CP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_ACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_ACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_INACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_INACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_MAIN_TIMER_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_MAIN_TIMER_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SARADC1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SARADC1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TSENS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TSENS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_COCPU_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_COCPU_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SARADC2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SARADC2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_SWD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_SWD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_XTAL32K_DEAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_XTAL32K_DEAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_COCPU_TRAP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_COCPU_TRAP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_RAW_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_RTC.Reg, volatile.LoadUint32(&o.INT_RAW_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_RAW_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_ST_RTC: rtc interrupt register +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SLP_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SLP_WAKEUP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SLP_REJECT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SLP_REJECT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SDIO_IDLE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SDIO_IDLE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_SCAN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_SCAN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_ULP_CP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_ULP_CP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_ACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_ACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_INACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_INACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_MAIN_TIMER_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_MAIN_TIMER_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SARADC1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SARADC1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TSENS_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TSENS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_COCPU_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_COCPU_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SARADC2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SARADC2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_SWD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_SWD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_XTAL32K_DEAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_XTAL32K_DEAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_COCPU_TRAP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_COCPU_TRAP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_ST_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_RTC.Reg, volatile.LoadUint32(&o.INT_ST_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ST_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_CLR_RTC: rtc interrupt register +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SLP_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SLP_WAKEUP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SLP_REJECT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SLP_REJECT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SDIO_IDLE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SDIO_IDLE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_ULP_CP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_ULP_CP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_ACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_ACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_INACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_INACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_MAIN_TIMER_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_MAIN_TIMER_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SARADC1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SARADC1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TSENS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TSENS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_COCPU_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_COCPU_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SARADC2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SARADC2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_SWD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_SWD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_XTAL32K_DEAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_XTAL32K_DEAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_COCPU_TRAP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_COCPU_TRAP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_CLR_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_RTC.Reg, volatile.LoadUint32(&o.INT_CLR_RTC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_CLR_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_RTC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.STORE0: Reserved register +func (o *RTC_CNTL_Type) SetSTORE0(value uint32) { + volatile.StoreUint32(&o.STORE0.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE0() uint32 { + return volatile.LoadUint32(&o.STORE0.Reg) +} + +// RTC_CNTL.STORE1: Reserved register +func (o *RTC_CNTL_Type) SetSTORE1(value uint32) { + volatile.StoreUint32(&o.STORE1.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE1() uint32 { + return volatile.LoadUint32(&o.STORE1.Reg) +} + +// RTC_CNTL.STORE2: Reserved register +func (o *RTC_CNTL_Type) SetSTORE2(value uint32) { + volatile.StoreUint32(&o.STORE2.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE2() uint32 { + return volatile.LoadUint32(&o.STORE2.Reg) +} + +// RTC_CNTL.STORE3: Reserved register +func (o *RTC_CNTL_Type) SetSTORE3(value uint32) { + volatile.StoreUint32(&o.STORE3.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE3() uint32 { + return volatile.LoadUint32(&o.STORE3.Reg) +} + +// RTC_CNTL.EXT_XTL_CONF: Reserved register +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_WDT_EN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_WDT_EN() uint32 { + return volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_WDT_CLK_FO(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_WDT_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_WDT_RESET(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_WDT_RESET() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_EXT_CLK_FO(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_EXT_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_AUTO_BACKUP(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_AUTO_BACKUP() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_AUTO_RESTART(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_AUTO_RESTART() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_AUTO_RETURN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_AUTO_RETURN() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_ENCKINIT_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_ENCKINIT_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DBUF_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DBUF_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DGM_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x1c00)|value<<10) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DGM_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x1c00) >> 10 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DRES_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0xe000)|value<<13) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DRES_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0xe000) >> 13 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XPD_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XPD_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_DAC_XTAL_32K(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0xe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_DAC_XTAL_32K() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0xe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_WDT_STATE(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_WDT_STATE() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x700000) >> 20 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTAL32K_GPIO_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTAL32K_GPIO_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_LV(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetEXT_XTL_CONF_XTL_EXT_CTR_EN(value uint32) { + volatile.StoreUint32(&o.EXT_XTL_CONF.Reg, volatile.LoadUint32(&o.EXT_XTL_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_XTL_CONF_XTL_EXT_CTR_EN() uint32 { + return (volatile.LoadUint32(&o.EXT_XTL_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.EXT_WAKEUP_CONF: ext wakeup configure +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_EXT_WAKEUP0_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_EXT_WAKEUP0_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetEXT_WAKEUP_CONF_EXT_WAKEUP1_LV(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP_CONF.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP_CONF_EXT_WAKEUP1_LV() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SLP_REJECT_CONF: reject sleep register +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_SLEEP_REJECT_ENA(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x3ffff000)|value<<12) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_SLEEP_REJECT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x3ffff000) >> 12 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_LIGHT_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CONF.Reg, volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CONF_DEEP_SLP_REJECT_EN() uint32 { + return (volatile.LoadUint32(&o.SLP_REJECT_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.CPU_PERIOD_CONF: conigure cpu freq +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUSEL_CONF(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUSEL_CONF() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCPU_PERIOD_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PERIOD_CONF.Reg, volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCPU_PERIOD_CONF_CPUPERIOD_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PERIOD_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.SDIO_ACT_CONF: No public +func (o *RTC_CNTL_Type) SetSDIO_ACT_CONF_SDIO_ACT_DNUM(value uint32) { + volatile.StoreUint32(&o.SDIO_ACT_CONF.Reg, volatile.LoadUint32(&o.SDIO_ACT_CONF.Reg)&^(0xffc00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSDIO_ACT_CONF_SDIO_ACT_DNUM() uint32 { + return (volatile.LoadUint32(&o.SDIO_ACT_CONF.Reg) & 0xffc00000) >> 22 +} + +// RTC_CNTL.CLK_CONF: configure clock register +func (o *RTC_CNTL_Type) SetCLK_CONF_EFUSE_CLK_FORCE_GATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_EFUSE_CLK_FORCE_GATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_EFUSE_CLK_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_EFUSE_CLK_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV_SEL_VLD(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV_SEL_VLD() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x30)|value<<4) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x30) >> 4 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ENB_CK8M_DIV(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ENB_CK8M_DIV() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_XTAL32K_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_XTAL32K_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_D256_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_D256_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_DIG_CLK8M_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_DIG_CLK8M_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DIV_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x7000)|value<<12) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DIV_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x7000) >> 12 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_DFREQ(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1fe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_DFREQ() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1fe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_CK8M_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_CK8M_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_GLOBAL_FORCE_GATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_GLOBAL_FORCE_GATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_XTAL_GLOBAL_FORCE_NOGATING(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_XTAL_GLOBAL_FORCE_NOGATING() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_FAST_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_FAST_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetCLK_CONF_ANA_CLK_RTC_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetCLK_CONF_ANA_CLK_RTC_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xc0000000) >> 30 +} + +// RTC_CNTL.SLOW_CLK_CONF: configure slow clk +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_ANA_CLK_DIV_VLD(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_ANA_CLK_DIV_VLD() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_ANA_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x7f800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_ANA_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x7f800000) >> 23 +} +func (o *RTC_CNTL_Type) SetSLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE(value uint32) { + volatile.StoreUint32(&o.SLOW_CLK_CONF.Reg, volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE() uint32 { + return (volatile.LoadUint32(&o.SLOW_CLK_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SDIO_CONF: configure flash power +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_TIMER_TARGET(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_TIMER_TARGET() uint32 { + return volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_DTHDRV(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x600)|value<<9) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_DTHDRV() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x600) >> 9 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_DCAP(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x1800)|value<<11) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_DCAP() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x1800) >> 11 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_INITI(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x6000)|value<<13) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_INITI() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x6000) >> 13 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_EN_INITI(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_EN_INITI() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_DCURLIM(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_DCURLIM() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x70000) >> 16 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_MODECURLIM(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_MODECURLIM() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_ENCURLIM(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_ENCURLIM() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_REG_PD_EN(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_REG_PD_EN() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_FORCE(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_FORCE() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_SDIO_TIEH(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_SDIO_TIEH() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_REG1P8_READY(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_REG1P8_READY() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFL_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x6000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFL_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x6000000) >> 25 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFM_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x18000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFM_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x18000000) >> 27 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_DREFH_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_DREFH_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x60000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSDIO_CONF_XPD_SDIO(value uint32) { + volatile.StoreUint32(&o.SDIO_CONF.Reg, volatile.LoadUint32(&o.SDIO_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSDIO_CONF_XPD_SDIO() uint32 { + return (volatile.LoadUint32(&o.SDIO_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.BIAS_CONF: No public +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_IDLE(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_IDLE() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_WAKE(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_WAKE() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_BUF_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_BUF_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_PD_CUR_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_PD_CUR_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_PD_CUR_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_PD_CUR_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_SLEEP_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_SLEEP_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_BIAS_SLEEP_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_BIAS_SLEEP_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_DEEP_SLP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c0000)|value<<18) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_DEEP_SLP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c0000) >> 18 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_MONITOR(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_MONITOR() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetBIAS_CONF_DBG_ATTEN_WAKEUP(value uint32) { + volatile.StoreUint32(&o.BIAS_CONF.Reg, volatile.LoadUint32(&o.BIAS_CONF.Reg)&^(0x3c000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetBIAS_CONF_DBG_ATTEN_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.BIAS_CONF.Reg) & 0x3c000000) >> 26 +} + +// RTC_CNTL.RTC: configure rtc regulator +func (o *RTC_CNTL_Type) SetRTC_DIG_REG_CAL_EN(value uint32) { + volatile.StoreUint32(&o.RTC.Reg, volatile.LoadUint32(&o.RTC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetRTC_DIG_REG_CAL_EN() uint32 { + return (volatile.LoadUint32(&o.RTC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetRTC_SCK_DCAP(value uint32) { + volatile.StoreUint32(&o.RTC.Reg, volatile.LoadUint32(&o.RTC.Reg)&^(0x3fc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetRTC_SCK_DCAP() uint32 { + return (volatile.LoadUint32(&o.RTC.Reg) & 0x3fc000) >> 14 +} +func (o *RTC_CNTL_Type) SetRTC_DBOOST_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RTC.Reg, volatile.LoadUint32(&o.RTC.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetRTC_DBOOST_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RTC.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetRTC_DBOOST_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RTC.Reg, volatile.LoadUint32(&o.RTC.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetRTC_DBOOST_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RTC.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetRTC_REGULATOR_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RTC.Reg, volatile.LoadUint32(&o.RTC.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetRTC_REGULATOR_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RTC.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetRTC_REGULATOR_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RTC.Reg, volatile.LoadUint32(&o.RTC.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetRTC_REGULATOR_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RTC.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.PWC: configure rtc power +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_NOISO() uint32 { + return volatile.LoadUint32(&o.PWC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FOLW_CPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FOLW_CPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_LPD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_LPD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetPWC_FASTMEM_FORCE_LPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetPWC_FASTMEM_FORCE_LPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FOLW_CPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FOLW_CPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_LPD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_LPD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetPWC_SLOWMEM_FORCE_LPU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetPWC_SLOWMEM_FORCE_LPU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetPWC_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetPWC_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetPWC_PD_EN(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetPWC_PD_EN() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetPWC_PAD_FORCE_HOLD(value uint32) { + volatile.StoreUint32(&o.PWC.Reg, volatile.LoadUint32(&o.PWC.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetPWC_PAD_FORCE_HOLD() uint32 { + return (volatile.LoadUint32(&o.PWC.Reg) & 0x200000) >> 21 +} + +// RTC_CNTL.REGULATOR_DRV_CTRL: No public +func (o *RTC_CNTL_Type) SetREGULATOR_DRV_CTRL_REGULATOR_DRV_B_MONITOR(value uint32) { + volatile.StoreUint32(&o.REGULATOR_DRV_CTRL.Reg, volatile.LoadUint32(&o.REGULATOR_DRV_CTRL.Reg)&^(0x3f)|value) +} +func (o *RTC_CNTL_Type) GetREGULATOR_DRV_CTRL_REGULATOR_DRV_B_MONITOR() uint32 { + return volatile.LoadUint32(&o.REGULATOR_DRV_CTRL.Reg) & 0x3f +} +func (o *RTC_CNTL_Type) SetREGULATOR_DRV_CTRL_REGULATOR_DRV_B_SLP(value uint32) { + volatile.StoreUint32(&o.REGULATOR_DRV_CTRL.Reg, volatile.LoadUint32(&o.REGULATOR_DRV_CTRL.Reg)&^(0xfc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetREGULATOR_DRV_CTRL_REGULATOR_DRV_B_SLP() uint32 { + return (volatile.LoadUint32(&o.REGULATOR_DRV_CTRL.Reg) & 0xfc0) >> 6 +} +func (o *RTC_CNTL_Type) SetREGULATOR_DRV_CTRL_DG_VDD_DRV_B_SLP(value uint32) { + volatile.StoreUint32(&o.REGULATOR_DRV_CTRL.Reg, volatile.LoadUint32(&o.REGULATOR_DRV_CTRL.Reg)&^(0xff000)|value<<12) +} +func (o *RTC_CNTL_Type) GetREGULATOR_DRV_CTRL_DG_VDD_DRV_B_SLP() uint32 { + return (volatile.LoadUint32(&o.REGULATOR_DRV_CTRL.Reg) & 0xff000) >> 12 +} +func (o *RTC_CNTL_Type) SetREGULATOR_DRV_CTRL_DG_VDD_DRV_B_MONITOR(value uint32) { + volatile.StoreUint32(&o.REGULATOR_DRV_CTRL.Reg, volatile.LoadUint32(&o.REGULATOR_DRV_CTRL.Reg)&^(0xff00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetREGULATOR_DRV_CTRL_DG_VDD_DRV_B_MONITOR() uint32 { + return (volatile.LoadUint32(&o.REGULATOR_DRV_CTRL.Reg) & 0xff00000) >> 20 +} + +// RTC_CNTL.DIG_PWC: configure digital power +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_LSLP_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_LSLP_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_BT_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_BT_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_BT_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_BT_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_PERI_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_PERI_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_PERI_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_PERI_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_CPU_TOP_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_CPU_TOP_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_CPU_TOP_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_CPU_TOP_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_BT_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_BT_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_PERI_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_PERI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_CPU_TOP_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_CPU_TOP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_WIFI_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_WIFI_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetDIG_PWC_DG_WRAP_PD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_PWC.Reg, volatile.LoadUint32(&o.DIG_PWC.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_PWC_DG_WRAP_PD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_PWC.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.DIG_ISO: congigure digital power isolation +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_OFF(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_OFF() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_CLR_DG_PAD_AUTOHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_CLR_DG_PAD_AUTOHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_AUTOHOLD_EN(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_AUTOHOLD_EN() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_UNHOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_UNHOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PAD_FORCE_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PAD_FORCE_HOLD() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_BT_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_BT_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_BT_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_BT_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PERI_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PERI_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_PERI_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_PERI_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_CPU_TOP_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_CPU_TOP_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_CPU_TOP_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_CPU_TOP_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_WIFI_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_WIFI_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_WIFI_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_WIFI_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_ISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_ISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetDIG_ISO_DG_WRAP_FORCE_NOISO(value uint32) { + volatile.StoreUint32(&o.DIG_ISO.Reg, volatile.LoadUint32(&o.DIG_ISO.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetDIG_ISO_DG_WRAP_FORCE_NOISO() uint32 { + return (volatile.LoadUint32(&o.DIG_ISO.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG0: configure rtc watch dog +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CHIP_RESET_WIDTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xff)|value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CHIP_RESET_WIDTH() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xff +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CHIP_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CHIP_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PAUSE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PAUSE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000)|value<<13) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000) >> 13 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000)|value<<16) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000) >> 16 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x380000)|value<<19) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x380000) >> 19 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c00000)|value<<22) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c00000) >> 22 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x70000000) >> 28 +} +func (o *RTC_CNTL_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTCONFIG1: stage0 hold time +func (o *RTC_CNTL_Type) SetWDTCONFIG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG1() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG1.Reg) +} + +// RTC_CNTL.WDTCONFIG2: stage1 hold time +func (o *RTC_CNTL_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// RTC_CNTL.WDTCONFIG3: stage2 hold time +func (o *RTC_CNTL_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// RTC_CNTL.WDTCONFIG4: stage3 hold time +func (o *RTC_CNTL_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// RTC_CNTL.WDTFEED: rtc wdt feed +func (o *RTC_CNTL_Type) SetWDTFEED_WDT_FEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, volatile.LoadUint32(&o.WDTFEED.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetWDTFEED_WDT_FEED() uint32 { + return (volatile.LoadUint32(&o.WDTFEED.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.WDTWPROTECT: configure rtc watch dog +func (o *RTC_CNTL_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *RTC_CNTL_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// RTC_CNTL.SWD_CONF: congfigure super watch dog +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_RESET_FLAG(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_RESET_FLAG() uint32 { + return volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_FEED_INT(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_FEED_INT() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_BYPASS_RST(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_BYPASS_RST() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_SIGNAL_WIDTH(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0xffc0000)|value<<18) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_SIGNAL_WIDTH() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0xffc0000) >> 18 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_RST_FLAG_CLR(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_RST_FLAG_CLR() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_FEED(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_FEED() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_DISABLE(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetSWD_CONF_SWD_AUTO_FEED_EN(value uint32) { + volatile.StoreUint32(&o.SWD_CONF.Reg, volatile.LoadUint32(&o.SWD_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetSWD_CONF_SWD_AUTO_FEED_EN() uint32 { + return (volatile.LoadUint32(&o.SWD_CONF.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.SWD_WPROTECT: super watch dog key +func (o *RTC_CNTL_Type) SetSWD_WPROTECT(value uint32) { + volatile.StoreUint32(&o.SWD_WPROTECT.Reg, value) +} +func (o *RTC_CNTL_Type) GetSWD_WPROTECT() uint32 { + return volatile.LoadUint32(&o.SWD_WPROTECT.Reg) +} + +// RTC_CNTL.SW_CPU_STALL: configure cpu stall by sw +func (o *RTC_CNTL_Type) SetSW_CPU_STALL_SW_STALL_APPCPU_C1(value uint32) { + volatile.StoreUint32(&o.SW_CPU_STALL.Reg, volatile.LoadUint32(&o.SW_CPU_STALL.Reg)&^(0x3f00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetSW_CPU_STALL_SW_STALL_APPCPU_C1() uint32 { + return (volatile.LoadUint32(&o.SW_CPU_STALL.Reg) & 0x3f00000) >> 20 +} +func (o *RTC_CNTL_Type) SetSW_CPU_STALL_SW_STALL_PROCPU_C1(value uint32) { + volatile.StoreUint32(&o.SW_CPU_STALL.Reg, volatile.LoadUint32(&o.SW_CPU_STALL.Reg)&^(0xfc000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetSW_CPU_STALL_SW_STALL_PROCPU_C1() uint32 { + return (volatile.LoadUint32(&o.SW_CPU_STALL.Reg) & 0xfc000000) >> 26 +} + +// RTC_CNTL.STORE4: reserved register +func (o *RTC_CNTL_Type) SetSTORE4(value uint32) { + volatile.StoreUint32(&o.STORE4.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE4() uint32 { + return volatile.LoadUint32(&o.STORE4.Reg) +} + +// RTC_CNTL.STORE5: reserved register +func (o *RTC_CNTL_Type) SetSTORE5(value uint32) { + volatile.StoreUint32(&o.STORE5.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE5() uint32 { + return volatile.LoadUint32(&o.STORE5.Reg) +} + +// RTC_CNTL.STORE6: reserved register +func (o *RTC_CNTL_Type) SetSTORE6(value uint32) { + volatile.StoreUint32(&o.STORE6.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE6() uint32 { + return volatile.LoadUint32(&o.STORE6.Reg) +} + +// RTC_CNTL.STORE7: reserved register +func (o *RTC_CNTL_Type) SetSTORE7(value uint32) { + volatile.StoreUint32(&o.STORE7.Reg, value) +} +func (o *RTC_CNTL_Type) GetSTORE7() uint32 { + return volatile.LoadUint32(&o.STORE7.Reg) +} + +// RTC_CNTL.LOW_POWER_ST: reserved register +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_ROM0(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_ROM0() uint32 { + return volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_DIG_DCDC(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_DIG_DCDC() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_PERI_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_PERI_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_RTC_PERI(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_RTC_PERI() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_WIFI_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_WIFI_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_WIFI(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_WIFI() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_DIG_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_DIG_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_XPD_DIG(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_XPD_DIG() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_START(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_START() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_SWITCH(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_SWITCH() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_TOUCH_STATE_DONE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_TOUCH_STATE_DONE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_START(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_START() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_SWITCH(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_SWITCH() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_COCPU_STATE_DONE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_COCPU_STATE_DONE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_XTAL_ISO(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_XTAL_ISO() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_PLL_ON(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_PLL_ON() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_RDY_FOR_WAKEUP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_RDY_FOR_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_WAIT_END(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_WAIT_END() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_IN_WAKEUP_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_IN_WAKEUP_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x200000) >> 21 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_IN_LOW_POWER_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_IN_LOW_POWER_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_8M(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_8M() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_SLP(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_SLP() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE_IN_IDLE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE_IN_IDLE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetLOW_POWER_ST_MAIN_STATE(value uint32) { + volatile.StoreUint32(&o.LOW_POWER_ST.Reg, volatile.LoadUint32(&o.LOW_POWER_ST.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetLOW_POWER_ST_MAIN_STATE() uint32 { + return (volatile.LoadUint32(&o.LOW_POWER_ST.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.DIAG0: No public +func (o *RTC_CNTL_Type) SetDIAG0(value uint32) { + volatile.StoreUint32(&o.DIAG0.Reg, value) +} +func (o *RTC_CNTL_Type) GetDIAG0() uint32 { + return volatile.LoadUint32(&o.DIAG0.Reg) +} + +// RTC_CNTL.PAD_HOLD: rtc pad hold configure +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD0_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD0_HOLD() uint32 { + return volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD1_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD1_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD2_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD2_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD3_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD3_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD4_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD4_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD5_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD5_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD6_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD6_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD7_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD7_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD8_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD8_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD9_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD9_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD10_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD10_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD11_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD11_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD12_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD12_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD13_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD13_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_TOUCH_PAD14_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_TOUCH_PAD14_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_X32P_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_X32P_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_X32N_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_X32N_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PDAC1_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PDAC1_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PDAC2_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PDAC2_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PAD19_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PAD19_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PAD20_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PAD20_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x100000) >> 20 +} +func (o *RTC_CNTL_Type) SetPAD_HOLD_PAD21_HOLD(value uint32) { + volatile.StoreUint32(&o.PAD_HOLD.Reg, volatile.LoadUint32(&o.PAD_HOLD.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_CNTL_Type) GetPAD_HOLD_PAD21_HOLD() uint32 { + return (volatile.LoadUint32(&o.PAD_HOLD.Reg) & 0x200000) >> 21 +} + +// RTC_CNTL.DIG_PAD_HOLD: configure digtal pad hold +func (o *RTC_CNTL_Type) SetDIG_PAD_HOLD(value uint32) { + volatile.StoreUint32(&o.DIG_PAD_HOLD.Reg, value) +} +func (o *RTC_CNTL_Type) GetDIG_PAD_HOLD() uint32 { + return volatile.LoadUint32(&o.DIG_PAD_HOLD.Reg) +} + +// RTC_CNTL.EXT_WAKEUP1: configure ext1 wakeup +func (o *RTC_CNTL_Type) SetEXT_WAKEUP1_EXT_WAKEUP1_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0x3fffff)|value) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP1_EXT_WAKEUP1_SEL() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0x3fffff +} +func (o *RTC_CNTL_Type) SetEXT_WAKEUP1_EXT_WAKEUP1_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP1_EXT_WAKEUP1_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0x400000) >> 22 +} + +// RTC_CNTL.EXT_WAKEUP1_STATUS: check ext wakeup1 status +func (o *RTC_CNTL_Type) SetEXT_WAKEUP1_STATUS(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP1_STATUS.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg)&^(0x3fffff)|value) +} +func (o *RTC_CNTL_Type) GetEXT_WAKEUP1_STATUS() uint32 { + return volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg) & 0x3fffff +} + +// RTC_CNTL.BROWN_OUT: congfigure brownout +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_INT_WAIT(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x3ff0)|value<<4) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_INT_WAIT() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x3ff0) >> 4 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_PD_RF_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_PD_RF_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_RST_WAIT(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x3ff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_RST_WAIT() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x3ff0000) >> 16 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_RST_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_RST_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_RST_SEL(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_RST_SEL() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x8000000) >> 27 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_ANA_RST_EN(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_ANA_RST_EN() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_BROWN_OUT_ENA(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_BROWN_OUT_ENA() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetBROWN_OUT_DET(value uint32) { + volatile.StoreUint32(&o.BROWN_OUT.Reg, volatile.LoadUint32(&o.BROWN_OUT.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetBROWN_OUT_DET() uint32 { + return (volatile.LoadUint32(&o.BROWN_OUT.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TIME_LOW1: RTC timer low 32 bits +func (o *RTC_CNTL_Type) SetTIME_LOW1(value uint32) { + volatile.StoreUint32(&o.TIME_LOW1.Reg, value) +} +func (o *RTC_CNTL_Type) GetTIME_LOW1() uint32 { + return volatile.LoadUint32(&o.TIME_LOW1.Reg) +} + +// RTC_CNTL.TIME_HIGH1: RTC timer high 16 bits +func (o *RTC_CNTL_Type) SetTIME_HIGH1_TIMER_VALUE1_HIGH(value uint32) { + volatile.StoreUint32(&o.TIME_HIGH1.Reg, volatile.LoadUint32(&o.TIME_HIGH1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTIME_HIGH1_TIMER_VALUE1_HIGH() uint32 { + return volatile.LoadUint32(&o.TIME_HIGH1.Reg) & 0xffff +} + +// RTC_CNTL.XTAL32K_CLK_FACTOR: xtal 32k watch dog backup clock factor +func (o *RTC_CNTL_Type) SetXTAL32K_CLK_FACTOR(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CLK_FACTOR.Reg, value) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CLK_FACTOR() uint32 { + return volatile.LoadUint32(&o.XTAL32K_CLK_FACTOR.Reg) +} + +// RTC_CNTL.XTAL32K_CONF: configure xtal32k +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_RETURN_WAIT(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xf)|value) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_RETURN_WAIT() uint32 { + return volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xf +} +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_RESTART_WAIT(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xffff0)|value<<4) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_RESTART_WAIT() uint32 { + return (volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xffff0) >> 4 +} +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_WDT_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xff00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_WDT_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xff00000) >> 20 +} +func (o *RTC_CNTL_Type) SetXTAL32K_CONF_XTAL32K_STABLE_THRES(value uint32) { + volatile.StoreUint32(&o.XTAL32K_CONF.Reg, volatile.LoadUint32(&o.XTAL32K_CONF.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetXTAL32K_CONF_XTAL32K_STABLE_THRES() uint32 { + return (volatile.LoadUint32(&o.XTAL32K_CONF.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.ULP_CP_TIMER: configure ulp +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_PC_INIT(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x7ff)|value) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_PC_INIT() uint32 { + return volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x7ff +} +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_ULP_CP_SLP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_ULP_CP_SLP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.ULP_CP_CTRL: configure ulp +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x7ff)|value) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT() uint32 { + return volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x7ff +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x3ff800)|value<<11) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x3ff800) >> 11 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_CLK_FO(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_RESET(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_RESET() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_FORCE_START_TOP(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_FORCE_START_TOP() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetULP_CP_CTRL_ULP_CP_START_TOP(value uint32) { + volatile.StoreUint32(&o.ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.ULP_CP_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetULP_CP_CTRL_ULP_CP_START_TOP() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.COCPU_CTRL: configure ulp-riscv +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_CLK_FO(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_CLK_FO() uint32 { + return volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_START_2_RESET_DIS(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x7e)|value<<1) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_START_2_RESET_DIS() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x7e) >> 1 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_START_2_INTR_EN(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x1f80)|value<<7) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_START_2_INTR_EN() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x1f80) >> 7 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SHUT(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SHUT() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SHUT_2_CLK_DIS(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SHUT_2_CLK_DIS() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SHUT_RESET_EN(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SHUT_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SEL(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SEL() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_DONE_FORCE(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_DONE_FORCE() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_DONE(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_DONE() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_SW_INT_TRIGGER(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_SW_INT_TRIGGER() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetCOCPU_CTRL_COCPU_CLKGATE_EN(value uint32) { + volatile.StoreUint32(&o.COCPU_CTRL.Reg, volatile.LoadUint32(&o.COCPU_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetCOCPU_CTRL_COCPU_CLKGATE_EN() uint32 { + return (volatile.LoadUint32(&o.COCPU_CTRL.Reg) & 0x8000000) >> 27 +} + +// RTC_CNTL.TOUCH_CTRL1: configure touch controller +func (o *RTC_CNTL_Type) SetTOUCH_CTRL1_TOUCH_SLEEP_CYCLES(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.TOUCH_CTRL1.Reg)&^(0xffff)|value) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL1_TOUCH_SLEEP_CYCLES() uint32 { + return volatile.LoadUint32(&o.TOUCH_CTRL1.Reg) & 0xffff +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL1_TOUCH_MEAS_NUM(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL1.Reg, volatile.LoadUint32(&o.TOUCH_CTRL1.Reg)&^(0xffff0000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL1_TOUCH_MEAS_NUM() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL1.Reg) & 0xffff0000) >> 16 +} + +// RTC_CNTL.TOUCH_CTRL2: configure touch controller +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_DRANGE(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0xc)|value<<2) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_DRANGE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0xc) >> 2 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_DREFL(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x30)|value<<4) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_DREFL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x30) >> 4 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_DREFH(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0xc0)|value<<6) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_DREFH() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0xc0) >> 6 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_XPD_BIAS(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_XPD_BIAS() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_REFC(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0xe00)|value<<9) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_REFC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0xe00) >> 9 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_DBIAS(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_DBIAS() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_SLP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_SLP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_START_FSM_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_START_FSM_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_START_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_START_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_START_FORCE(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x1fe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_XPD_WAIT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x1fe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_SLP_CYC_DIV(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x6000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_SLP_CYC_DIV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x6000000) >> 25 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_TIMER_FORCE_DONE(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x18000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_TIMER_FORCE_DONE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x18000000) >> 27 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_RESET(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_RESET() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_CLK_FO(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetTOUCH_CTRL2_TOUCH_CLKGATE_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL2.Reg, volatile.LoadUint32(&o.TOUCH_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetTOUCH_CTRL2_TOUCH_CLKGATE_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL2.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.TOUCH_SCAN_CTRL: configure touch controller +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_DENOISE_RES(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_DENOISE_RES() uint32 { + return volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_DENOISE_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_DENOISE_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_SCAN_PAD_MAP(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0x1fffc00)|value<<10) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_SCAN_PAD_MAP() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0x1fffc00) >> 10 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_BUFDRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_BUFDRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetTOUCH_SCAN_CTRL_TOUCH_OUT_RING(value uint32) { + volatile.StoreUint32(&o.TOUCH_SCAN_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg)&^(0xf0000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetTOUCH_SCAN_CTRL_TOUCH_OUT_RING() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SCAN_CTRL.Reg) & 0xf0000000) >> 28 +} + +// RTC_CNTL.TOUCH_SLP_THRES: configure touch controller +func (o *RTC_CNTL_Type) SetTOUCH_SLP_THRES_TOUCH_SLP_TH(value uint32) { + volatile.StoreUint32(&o.TOUCH_SLP_THRES.Reg, volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg)&^(0x3fffff)|value) +} +func (o *RTC_CNTL_Type) GetTOUCH_SLP_THRES_TOUCH_SLP_TH() uint32 { + return volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg) & 0x3fffff +} +func (o *RTC_CNTL_Type) SetTOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_SLP_THRES.Reg, volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetTOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetTOUCH_SLP_THRES_TOUCH_SLP_PAD(value uint32) { + volatile.StoreUint32(&o.TOUCH_SLP_THRES.Reg, volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetTOUCH_SLP_THRES_TOUCH_SLP_PAD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_SLP_THRES.Reg) & 0xf8000000) >> 27 +} + +// RTC_CNTL.TOUCH_APPROACH: configure touch controller +func (o *RTC_CNTL_Type) SetTOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR(value uint32) { + volatile.StoreUint32(&o.TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.TOUCH_APPROACH.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetTOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR() uint32 { + return (volatile.LoadUint32(&o.TOUCH_APPROACH.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetTOUCH_APPROACH_TOUCH_APPROACH_MEAS_TIME(value uint32) { + volatile.StoreUint32(&o.TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.TOUCH_APPROACH.Reg)&^(0xff000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetTOUCH_APPROACH_TOUCH_APPROACH_MEAS_TIME() uint32 { + return (volatile.LoadUint32(&o.TOUCH_APPROACH.Reg) & 0xff000000) >> 24 +} + +// RTC_CNTL.TOUCH_FILTER_CTRL: configure touch controller +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_BYPASS_NEG_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_BYPASS_NEG_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_BYPASS_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_BYPASS_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_SMOOTH_LVL(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x600)|value<<9) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_SMOOTH_LVL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x600) >> 9 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_JITTER_STEP(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x7800)|value<<11) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_JITTER_STEP() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x7800) >> 11 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_LIMIT(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x78000)|value<<15) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_LIMIT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x78000) >> 15 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x180000)|value<<19) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x180000) >> 19 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_NOISE_THRES(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x600000)|value<<21) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_NOISE_THRES() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x600000) >> 21 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_HYSTERESIS(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x1800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_HYSTERESIS() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x1800000) >> 23 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0xe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0xe000000) >> 25 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x70000000) >> 28 +} +func (o *RTC_CNTL_Type) SetTOUCH_FILTER_CTRL_TOUCH_FILTER_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_FILTER_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetTOUCH_FILTER_CTRL_TOUCH_FILTER_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_FILTER_CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.USB_CONF: usb configure +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_VREFH(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x3)|value) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_VREFH() uint32 { + return volatile.LoadUint32(&o.USB_CONF.Reg) & 0x3 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_VREFL(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0xc)|value<<2) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_VREFL() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0xc) >> 2 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_PAD_ENABLE_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_PAD_ENABLE_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_TXM(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_TXM() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_TXP(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_TXP() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_TX_EN(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_TX_EN() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_TX_EN_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_TX_EN_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_USB_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_USB_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_IO_MUX_RESET_DISABLE(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_IO_MUX_RESET_DISABLE() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_SW_USB_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_SW_USB_PHY_SEL() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetUSB_CONF_SW_HW_USB_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.USB_CONF.Reg, volatile.LoadUint32(&o.USB_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetUSB_CONF_SW_HW_USB_PHY_SEL() uint32 { + return (volatile.LoadUint32(&o.USB_CONF.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.TOUCH_TIMEOUT_CTRL: configure touch controller +func (o *RTC_CNTL_Type) SetTOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_NUM(value uint32) { + volatile.StoreUint32(&o.TOUCH_TIMEOUT_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_TIMEOUT_CTRL.Reg)&^(0x3fffff)|value) +} +func (o *RTC_CNTL_Type) GetTOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_NUM() uint32 { + return volatile.LoadUint32(&o.TOUCH_TIMEOUT_CTRL.Reg) & 0x3fffff +} +func (o *RTC_CNTL_Type) SetTOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN(value uint32) { + volatile.StoreUint32(&o.TOUCH_TIMEOUT_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_TIMEOUT_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetTOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN() uint32 { + return (volatile.LoadUint32(&o.TOUCH_TIMEOUT_CTRL.Reg) & 0x400000) >> 22 +} + +// RTC_CNTL.SLP_REJECT_CAUSE: get reject casue +func (o *RTC_CNTL_Type) SetSLP_REJECT_CAUSE_REJECT_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_REJECT_CAUSE.Reg, volatile.LoadUint32(&o.SLP_REJECT_CAUSE.Reg)&^(0x3ffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_REJECT_CAUSE_REJECT_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_REJECT_CAUSE.Reg) & 0x3ffff +} + +// RTC_CNTL.OPTION1: rtc common configure +func (o *RTC_CNTL_Type) SetOPTION1_FORCE_DOWNLOAD_BOOT(value uint32) { + volatile.StoreUint32(&o.OPTION1.Reg, volatile.LoadUint32(&o.OPTION1.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetOPTION1_FORCE_DOWNLOAD_BOOT() uint32 { + return volatile.LoadUint32(&o.OPTION1.Reg) & 0x1 +} + +// RTC_CNTL.SLP_WAKEUP_CAUSE: get wakeup cause +func (o *RTC_CNTL_Type) SetSLP_WAKEUP_CAUSE_WAKEUP_CAUSE(value uint32) { + volatile.StoreUint32(&o.SLP_WAKEUP_CAUSE.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CAUSE.Reg)&^(0x1ffff)|value) +} +func (o *RTC_CNTL_Type) GetSLP_WAKEUP_CAUSE_WAKEUP_CAUSE() uint32 { + return volatile.LoadUint32(&o.SLP_WAKEUP_CAUSE.Reg) & 0x1ffff +} + +// RTC_CNTL.ULP_CP_TIMER_1: configure ulp sleep time +func (o *RTC_CNTL_Type) SetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE(value uint32) { + volatile.StoreUint32(&o.ULP_CP_TIMER_1.Reg, volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg)&^(0xffffff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE() uint32 { + return (volatile.LoadUint32(&o.ULP_CP_TIMER_1.Reg) & 0xffffff00) >> 8 +} + +// RTC_CNTL.INT_ENA_RTC_W1TS: oneset rtc interrupt +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SDIO_IDLE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SDIO_IDLE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_TOUCH_SCAN_DONE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_TOUCH_SCAN_DONE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_ULP_CP_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_ULP_CP_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_TOUCH_DONE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_TOUCH_DONE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_TOUCH_ACTIVE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_TOUCH_ACTIVE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_TOUCH_INACTIVE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_TOUCH_INACTIVE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SARADC1_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SARADC1_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_TSENS_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_TSENS_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_COCPU_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_COCPU_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SARADC2_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SARADC2_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_COCPU_TRAP_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_COCPU_TRAP_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_TOUCH_TIMEOUT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_TOUCH_TIMEOUT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TS_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TS_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TS.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.INT_ENA_RTC_W1TC: oneset clr rtc interrupt enable +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC() uint32 { + return volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x2)|value<<1) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x2) >> 1 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SDIO_IDLE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x4)|value<<2) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SDIO_IDLE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x4) >> 2 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x8)|value<<3) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x8) >> 3 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_TOUCH_SCAN_DONE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x10)|value<<4) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_TOUCH_SCAN_DONE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x10) >> 4 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_ULP_CP_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x20)|value<<5) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_ULP_CP_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x20) >> 5 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_TOUCH_DONE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x40)|value<<6) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_TOUCH_DONE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x40) >> 6 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_TOUCH_ACTIVE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x80)|value<<7) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_TOUCH_ACTIVE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x80) >> 7 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_TOUCH_INACTIVE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x100)|value<<8) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_TOUCH_INACTIVE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x100) >> 8 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x200)|value<<9) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x200) >> 9 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x400)|value<<10) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x400) >> 10 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SARADC1_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x800)|value<<11) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SARADC1_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x800) >> 11 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_TSENS_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_TSENS_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x1000) >> 12 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_COCPU_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_COCPU_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SARADC2_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SARADC2_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x4000) >> 14 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x8000) >> 15 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_COCPU_TRAP_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x20000)|value<<17) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_COCPU_TRAP_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x20000) >> 17 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_TOUCH_TIMEOUT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x40000)|value<<18) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_TOUCH_TIMEOUT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x40000) >> 18 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x80000) >> 19 +} +func (o *RTC_CNTL_Type) SetINT_ENA_RTC_W1TC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.INT_ENA_RTC_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_CNTL_Type) GetINT_ENA_RTC_W1TC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_RTC_W1TC.Reg) & 0x100000) >> 20 +} + +// RTC_CNTL.RETENTION_CTRL: configure retention +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_TAG_MODE(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x3c00)|value<<10) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_TAG_MODE() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x3c00) >> 10 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_TARGET(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0xc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_TARGET() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0xc000) >> 14 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x10000) >> 16 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_DONE_WAIT(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0xe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_DONE_WAIT() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0xe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_CLKOFF_WAIT(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0xf00000)|value<<20) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_CLKOFF_WAIT() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0xf00000) >> 20 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_EN(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_EN() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetRETENTION_CTRL_RETENTION_WAIT(value uint32) { + volatile.StoreUint32(&o.RETENTION_CTRL.Reg, volatile.LoadUint32(&o.RETENTION_CTRL.Reg)&^(0xfe000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetRETENTION_CTRL_RETENTION_WAIT() uint32 { + return (volatile.LoadUint32(&o.RETENTION_CTRL.Reg) & 0xfe000000) >> 25 +} + +// RTC_CNTL.PG_CTRL: configure power glitch +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_DSENSE(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0xc000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_DSENSE() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0xc000000) >> 26 +} +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_EFUSE_SEL(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_EFUSE_SEL() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetPG_CTRL_POWER_GLITCH_EN(value uint32) { + volatile.StoreUint32(&o.PG_CTRL.Reg, volatile.LoadUint32(&o.PG_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetPG_CTRL_POWER_GLITCH_EN() uint32 { + return (volatile.LoadUint32(&o.PG_CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.FIB_SEL: No public +func (o *RTC_CNTL_Type) SetFIB_SEL(value uint32) { + volatile.StoreUint32(&o.FIB_SEL.Reg, volatile.LoadUint32(&o.FIB_SEL.Reg)&^(0x7)|value) +} +func (o *RTC_CNTL_Type) GetFIB_SEL() uint32 { + return volatile.LoadUint32(&o.FIB_SEL.Reg) & 0x7 +} + +// RTC_CNTL.TOUCH_DAC: configure touch dac +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD9_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0x1c)|value<<2) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD9_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0x1c) >> 2 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD8_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0xe0)|value<<5) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD8_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0xe0) >> 5 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD7_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0x700)|value<<8) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD7_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0x700) >> 8 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD6_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0x3800)|value<<11) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD6_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0x3800) >> 11 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD5_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0x1c000)|value<<14) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD5_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0x1c000) >> 14 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD4_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0xe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD4_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0xe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD3_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0x700000)|value<<20) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD3_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0x700000) >> 20 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD2_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD2_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0x3800000) >> 23 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD1_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0x1c000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD1_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0x1c000000) >> 26 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC_TOUCH_PAD0_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC.Reg, volatile.LoadUint32(&o.TOUCH_DAC.Reg)&^(0xe0000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC_TOUCH_PAD0_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC.Reg) & 0xe0000000) >> 29 +} + +// RTC_CNTL.TOUCH_DAC1: configure touch dac +func (o *RTC_CNTL_Type) SetTOUCH_DAC1_TOUCH_PAD14_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC1.Reg, volatile.LoadUint32(&o.TOUCH_DAC1.Reg)&^(0xe0000)|value<<17) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC1_TOUCH_PAD14_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC1.Reg) & 0xe0000) >> 17 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC1_TOUCH_PAD13_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC1.Reg, volatile.LoadUint32(&o.TOUCH_DAC1.Reg)&^(0x700000)|value<<20) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC1_TOUCH_PAD13_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC1.Reg) & 0x700000) >> 20 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC1_TOUCH_PAD12_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC1.Reg, volatile.LoadUint32(&o.TOUCH_DAC1.Reg)&^(0x3800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC1_TOUCH_PAD12_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC1.Reg) & 0x3800000) >> 23 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC1_TOUCH_PAD11_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC1.Reg, volatile.LoadUint32(&o.TOUCH_DAC1.Reg)&^(0x1c000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC1_TOUCH_PAD11_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC1.Reg) & 0x1c000000) >> 26 +} +func (o *RTC_CNTL_Type) SetTOUCH_DAC1_TOUCH_PAD10_DAC(value uint32) { + volatile.StoreUint32(&o.TOUCH_DAC1.Reg, volatile.LoadUint32(&o.TOUCH_DAC1.Reg)&^(0xe0000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetTOUCH_DAC1_TOUCH_PAD10_DAC() uint32 { + return (volatile.LoadUint32(&o.TOUCH_DAC1.Reg) & 0xe0000000) >> 29 +} + +// RTC_CNTL.COCPU_DISABLE: configure ulp diable +func (o *RTC_CNTL_Type) SetCOCPU_DISABLE_DISABLE_RTC_CPU(value uint32) { + volatile.StoreUint32(&o.COCPU_DISABLE.Reg, volatile.LoadUint32(&o.COCPU_DISABLE.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetCOCPU_DISABLE_DISABLE_RTC_CPU() uint32 { + return (volatile.LoadUint32(&o.COCPU_DISABLE.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.DATE: version register +func (o *RTC_CNTL_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_CNTL_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power I2C (Inter-Integrated Circuit) Controller +type RTC_I2C_Type struct { + SCL_LOW volatile.Register32 // 0x0 + CTRL volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + SCL_HIGH volatile.Register32 // 0x14 + SDA_DUTY volatile.Register32 // 0x18 + SCL_START_PERIOD volatile.Register32 // 0x1C + SCL_STOP_PERIOD volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_RAW volatile.Register32 // 0x28 + INT_ST volatile.Register32 // 0x2C + INT_ENA volatile.Register32 // 0x30 + DATA volatile.Register32 // 0x34 + CMD0 volatile.Register32 // 0x38 + CMD1 volatile.Register32 // 0x3C + CMD2 volatile.Register32 // 0x40 + CMD3 volatile.Register32 // 0x44 + CMD4 volatile.Register32 // 0x48 + CMD5 volatile.Register32 // 0x4C + CMD6 volatile.Register32 // 0x50 + CMD7 volatile.Register32 // 0x54 + CMD8 volatile.Register32 // 0x58 + CMD9 volatile.Register32 // 0x5C + CMD10 volatile.Register32 // 0x60 + CMD11 volatile.Register32 // 0x64 + CMD12 volatile.Register32 // 0x68 + CMD13 volatile.Register32 // 0x6C + CMD14 volatile.Register32 // 0x70 + CMD15 volatile.Register32 // 0x74 + _ [132]byte + DATE volatile.Register32 // 0xFC +} + +// RTC_I2C.SCL_LOW: configure low scl period +func (o *RTC_I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW.Reg, volatile.LoadUint32(&o.SCL_LOW.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW.Reg) & 0xfffff +} + +// RTC_I2C.CTRL: configure i2c ctrl +func (o *RTC_I2C_Type) SetCTRL_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetCTRL_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetCTRL_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetCTRL_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetCTRL_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetCTRL_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetCTRL_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetCTRL_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetCTRL_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetCTRL_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetCTRL_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetCTRL_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetCTRL_I2C_CTRL_CLK_GATE_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_I2C_Type) GetCTRL_I2C_CTRL_CLK_GATE_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_I2C_Type) SetCTRL_I2C_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_I2C_Type) GetCTRL_I2C_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_I2C_Type) SetCTRL_I2CCLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCTRL_I2CCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.STATUS: get i2c status +func (o *RTC_I2C_Type) SetSTATUS_ACK_REC(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetSTATUS_ACK_REC() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetSTATUS_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetSTATUS_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetSTATUS_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetSTATUS_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetSTATUS_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetSTATUS_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetSTATUS_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetSTATUS_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetSTATUS_BYTE_TRANS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetSTATUS_BYTE_TRANS() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetSTATUS_OP_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xc0)|value<<6) +} +func (o *RTC_I2C_Type) GetSTATUS_OP_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xc0) >> 6 +} +func (o *RTC_I2C_Type) SetSTATUS_SHIFT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *RTC_I2C_Type) GetSTATUS_SHIFT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xff0000) >> 16 +} +func (o *RTC_I2C_Type) SetSTATUS_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RTC_I2C_Type) GetSTATUS_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RTC_I2C_Type) SetSTATUS_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_I2C_Type) GetSTATUS_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x70000000) >> 28 +} + +// RTC_I2C.TO: configure time out +func (o *RTC_I2C_Type) SetTO_TIME_OUT(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetTO_TIME_OUT() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0xfffff +} + +// RTC_I2C.SLAVE_ADDR: configure slave id +func (o *RTC_I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *RTC_I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.SCL_HIGH: configure high scl period +func (o *RTC_I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH.Reg, volatile.LoadUint32(&o.SCL_HIGH.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH.Reg) & 0xfffff +} + +// RTC_I2C.SDA_DUTY: configure sda duty +func (o *RTC_I2C_Type) SetSDA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.SDA_DUTY.Reg, volatile.LoadUint32(&o.SDA_DUTY.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSDA_DUTY_NUM() uint32 { + return volatile.LoadUint32(&o.SDA_DUTY.Reg) & 0xfffff +} + +// RTC_I2C.SCL_START_PERIOD: configure scl start period +func (o *RTC_I2C_Type) SetSCL_START_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_START_PERIOD.Reg, volatile.LoadUint32(&o.SCL_START_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_START_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_START_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.SCL_STOP_PERIOD: configure scl stop period +func (o *RTC_I2C_Type) SetSCL_STOP_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_PERIOD.Reg, volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_STOP_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.INT_CLR: interrupt clear register +func (o *RTC_I2C_Type) SetINT_CLR_SLAVE_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_CLR_SLAVE_TRAN_COMP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_CLR_MASTER_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_CLR_MASTER_TRAN_COMP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_CLR_ACK_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_CLR_ACK_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_CLR_RX_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_CLR_RX_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_CLR_TX_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_CLR_TX_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_CLR_DETECT_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_CLR_DETECT_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_RAW: interrupt raw register +func (o *RTC_I2C_Type) SetINT_RAW_SLAVE_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_RAW_SLAVE_TRAN_COMP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_RAW_MASTER_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_RAW_MASTER_TRAN_COMP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_RAW_ACK_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_RAW_ACK_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_RAW_RX_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_RAW_RX_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_RAW_TX_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_RAW_TX_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_RAW_DETECT_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_RAW_DETECT_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_ST: interrupt state register +func (o *RTC_I2C_Type) SetINT_ST_SLAVE_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_ST_SLAVE_TRAN_COMP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_ST_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_ST_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_ST_MASTER_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_ST_MASTER_TRAN_COMP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_ST_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_ST_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_ST_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_ST_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_ST_ACK_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_ST_ACK_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_ST_RX_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_ST_RX_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_ST_TX_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_ST_TX_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_ST_DETECT_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_ST_DETECT_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_ENA: interrupt enable register +func (o *RTC_I2C_Type) SetINT_ENA_SLAVE_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_ENA_SLAVE_TRAN_COMP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_ENA_MASTER_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_ENA_MASTER_TRAN_COMP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_ENA_ACK_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_ENA_ACK_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_ENA_RX_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_ENA_RX_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_ENA_TX_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_ENA_TX_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_ENA_DETECT_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_ENA_DETECT_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// RTC_I2C.DATA: get i2c data status +func (o *RTC_I2C_Type) SetDATA_I2C_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *RTC_I2C_Type) GetDATA_I2C_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} +func (o *RTC_I2C_Type) SetDATA_SLAVE_TX_DATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_I2C_Type) GetDATA_SLAVE_TX_DATA() uint32 { + return (volatile.LoadUint32(&o.DATA.Reg) & 0xff00) >> 8 +} +func (o *RTC_I2C_Type) SetDATA_I2C_DONE(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetDATA_I2C_DONE() uint32 { + return (volatile.LoadUint32(&o.DATA.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD0: i2c commond0 register +func (o *RTC_I2C_Type) SetCMD0_COMMAND0(value uint32) { + volatile.StoreUint32(&o.CMD0.Reg, volatile.LoadUint32(&o.CMD0.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD0_COMMAND0() uint32 { + return volatile.LoadUint32(&o.CMD0.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD0_COMMAND0_DONE(value uint32) { + volatile.StoreUint32(&o.CMD0.Reg, volatile.LoadUint32(&o.CMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD0_COMMAND0_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD0.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD1: i2c commond1 register +func (o *RTC_I2C_Type) SetCMD1_COMMAND1(value uint32) { + volatile.StoreUint32(&o.CMD1.Reg, volatile.LoadUint32(&o.CMD1.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD1_COMMAND1() uint32 { + return volatile.LoadUint32(&o.CMD1.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD1_COMMAND1_DONE(value uint32) { + volatile.StoreUint32(&o.CMD1.Reg, volatile.LoadUint32(&o.CMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD1_COMMAND1_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD1.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD2: i2c commond2 register +func (o *RTC_I2C_Type) SetCMD2_COMMAND2(value uint32) { + volatile.StoreUint32(&o.CMD2.Reg, volatile.LoadUint32(&o.CMD2.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD2_COMMAND2() uint32 { + return volatile.LoadUint32(&o.CMD2.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD2_COMMAND2_DONE(value uint32) { + volatile.StoreUint32(&o.CMD2.Reg, volatile.LoadUint32(&o.CMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD2_COMMAND2_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD2.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD3: i2c commond3 register +func (o *RTC_I2C_Type) SetCMD3_COMMAND3(value uint32) { + volatile.StoreUint32(&o.CMD3.Reg, volatile.LoadUint32(&o.CMD3.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD3_COMMAND3() uint32 { + return volatile.LoadUint32(&o.CMD3.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD3_COMMAND3_DONE(value uint32) { + volatile.StoreUint32(&o.CMD3.Reg, volatile.LoadUint32(&o.CMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD3_COMMAND3_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD3.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD4: i2c commond4 register +func (o *RTC_I2C_Type) SetCMD4_COMMAND4(value uint32) { + volatile.StoreUint32(&o.CMD4.Reg, volatile.LoadUint32(&o.CMD4.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD4_COMMAND4() uint32 { + return volatile.LoadUint32(&o.CMD4.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD4_COMMAND4_DONE(value uint32) { + volatile.StoreUint32(&o.CMD4.Reg, volatile.LoadUint32(&o.CMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD4_COMMAND4_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD4.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD5: i2c commond5_register +func (o *RTC_I2C_Type) SetCMD5_COMMAND5(value uint32) { + volatile.StoreUint32(&o.CMD5.Reg, volatile.LoadUint32(&o.CMD5.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD5_COMMAND5() uint32 { + return volatile.LoadUint32(&o.CMD5.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD5_COMMAND5_DONE(value uint32) { + volatile.StoreUint32(&o.CMD5.Reg, volatile.LoadUint32(&o.CMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD5_COMMAND5_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD5.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD6: i2c commond6 register +func (o *RTC_I2C_Type) SetCMD6_COMMAND6(value uint32) { + volatile.StoreUint32(&o.CMD6.Reg, volatile.LoadUint32(&o.CMD6.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD6_COMMAND6() uint32 { + return volatile.LoadUint32(&o.CMD6.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD6_COMMAND6_DONE(value uint32) { + volatile.StoreUint32(&o.CMD6.Reg, volatile.LoadUint32(&o.CMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD6_COMMAND6_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD6.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD7: i2c commond7 register +func (o *RTC_I2C_Type) SetCMD7_COMMAND7(value uint32) { + volatile.StoreUint32(&o.CMD7.Reg, volatile.LoadUint32(&o.CMD7.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD7_COMMAND7() uint32 { + return volatile.LoadUint32(&o.CMD7.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD7_COMMAND7_DONE(value uint32) { + volatile.StoreUint32(&o.CMD7.Reg, volatile.LoadUint32(&o.CMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD7_COMMAND7_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD7.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD8: i2c commond8 register +func (o *RTC_I2C_Type) SetCMD8_COMMAND8(value uint32) { + volatile.StoreUint32(&o.CMD8.Reg, volatile.LoadUint32(&o.CMD8.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD8_COMMAND8() uint32 { + return volatile.LoadUint32(&o.CMD8.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD8_COMMAND8_DONE(value uint32) { + volatile.StoreUint32(&o.CMD8.Reg, volatile.LoadUint32(&o.CMD8.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD8_COMMAND8_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD8.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD9: i2c commond9 register +func (o *RTC_I2C_Type) SetCMD9_COMMAND9(value uint32) { + volatile.StoreUint32(&o.CMD9.Reg, volatile.LoadUint32(&o.CMD9.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD9_COMMAND9() uint32 { + return volatile.LoadUint32(&o.CMD9.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD9_COMMAND9_DONE(value uint32) { + volatile.StoreUint32(&o.CMD9.Reg, volatile.LoadUint32(&o.CMD9.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD9_COMMAND9_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD9.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD10: i2c commond10 register +func (o *RTC_I2C_Type) SetCMD10_COMMAND10(value uint32) { + volatile.StoreUint32(&o.CMD10.Reg, volatile.LoadUint32(&o.CMD10.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD10_COMMAND10() uint32 { + return volatile.LoadUint32(&o.CMD10.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD10_COMMAND10_DONE(value uint32) { + volatile.StoreUint32(&o.CMD10.Reg, volatile.LoadUint32(&o.CMD10.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD10_COMMAND10_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD10.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD11: i2c commond11 register +func (o *RTC_I2C_Type) SetCMD11_COMMAND11(value uint32) { + volatile.StoreUint32(&o.CMD11.Reg, volatile.LoadUint32(&o.CMD11.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD11_COMMAND11() uint32 { + return volatile.LoadUint32(&o.CMD11.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD11_COMMAND11_DONE(value uint32) { + volatile.StoreUint32(&o.CMD11.Reg, volatile.LoadUint32(&o.CMD11.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD11_COMMAND11_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD11.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD12: i2c commond12 register +func (o *RTC_I2C_Type) SetCMD12_COMMAND12(value uint32) { + volatile.StoreUint32(&o.CMD12.Reg, volatile.LoadUint32(&o.CMD12.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD12_COMMAND12() uint32 { + return volatile.LoadUint32(&o.CMD12.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD12_COMMAND12_DONE(value uint32) { + volatile.StoreUint32(&o.CMD12.Reg, volatile.LoadUint32(&o.CMD12.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD12_COMMAND12_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD12.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD13: i2c commond13 register +func (o *RTC_I2C_Type) SetCMD13_COMMAND13(value uint32) { + volatile.StoreUint32(&o.CMD13.Reg, volatile.LoadUint32(&o.CMD13.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD13_COMMAND13() uint32 { + return volatile.LoadUint32(&o.CMD13.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD13_COMMAND13_DONE(value uint32) { + volatile.StoreUint32(&o.CMD13.Reg, volatile.LoadUint32(&o.CMD13.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD13_COMMAND13_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD13.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD14: i2c commond14 register +func (o *RTC_I2C_Type) SetCMD14_COMMAND14(value uint32) { + volatile.StoreUint32(&o.CMD14.Reg, volatile.LoadUint32(&o.CMD14.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD14_COMMAND14() uint32 { + return volatile.LoadUint32(&o.CMD14.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD14_COMMAND14_DONE(value uint32) { + volatile.StoreUint32(&o.CMD14.Reg, volatile.LoadUint32(&o.CMD14.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD14_COMMAND14_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD14.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD15: i2c commond15 register +func (o *RTC_I2C_Type) SetCMD15_COMMAND15(value uint32) { + volatile.StoreUint32(&o.CMD15.Reg, volatile.LoadUint32(&o.CMD15.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD15_COMMAND15() uint32 { + return volatile.LoadUint32(&o.CMD15.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD15_COMMAND15_DONE(value uint32) { + volatile.StoreUint32(&o.CMD15.Reg, volatile.LoadUint32(&o.CMD15.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD15_COMMAND15_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD15.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.DATE: version register +func (o *RTC_I2C_Type) SetDATE_I2C_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_I2C_Type) GetDATE_I2C_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power Input/Output +type RTC_IO_Type struct { + RTC_GPIO_OUT volatile.Register32 // 0x0 + RTC_GPIO_OUT_W1TS volatile.Register32 // 0x4 + RTC_GPIO_OUT_W1TC volatile.Register32 // 0x8 + RTC_GPIO_ENABLE volatile.Register32 // 0xC + RTC_GPIO_ENABLE_W1TS volatile.Register32 // 0x10 + ENABLE_W1TC volatile.Register32 // 0x14 + RTC_GPIO_STATUS volatile.Register32 // 0x18 + RTC_GPIO_STATUS_W1TS volatile.Register32 // 0x1C + RTC_GPIO_STATUS_W1TC volatile.Register32 // 0x20 + RTC_GPIO_IN volatile.Register32 // 0x24 + PIN0 volatile.Register32 // 0x28 + PIN1 volatile.Register32 // 0x2C + PIN2 volatile.Register32 // 0x30 + PIN3 volatile.Register32 // 0x34 + PIN4 volatile.Register32 // 0x38 + PIN5 volatile.Register32 // 0x3C + PIN6 volatile.Register32 // 0x40 + PIN7 volatile.Register32 // 0x44 + PIN8 volatile.Register32 // 0x48 + PIN9 volatile.Register32 // 0x4C + PIN10 volatile.Register32 // 0x50 + PIN11 volatile.Register32 // 0x54 + PIN12 volatile.Register32 // 0x58 + PIN13 volatile.Register32 // 0x5C + PIN14 volatile.Register32 // 0x60 + PIN15 volatile.Register32 // 0x64 + PIN16 volatile.Register32 // 0x68 + PIN17 volatile.Register32 // 0x6C + PIN18 volatile.Register32 // 0x70 + PIN19 volatile.Register32 // 0x74 + PIN20 volatile.Register32 // 0x78 + PIN21 volatile.Register32 // 0x7C + RTC_DEBUG_SEL volatile.Register32 // 0x80 + TOUCH_PAD0 volatile.Register32 // 0x84 + TOUCH_PAD1 volatile.Register32 // 0x88 + TOUCH_PAD2 volatile.Register32 // 0x8C + TOUCH_PAD3 volatile.Register32 // 0x90 + TOUCH_PAD4 volatile.Register32 // 0x94 + TOUCH_PAD5 volatile.Register32 // 0x98 + TOUCH_PAD6 volatile.Register32 // 0x9C + TOUCH_PAD7 volatile.Register32 // 0xA0 + TOUCH_PAD8 volatile.Register32 // 0xA4 + TOUCH_PAD9 volatile.Register32 // 0xA8 + TOUCH_PAD10 volatile.Register32 // 0xAC + TOUCH_PAD11 volatile.Register32 // 0xB0 + TOUCH_PAD12 volatile.Register32 // 0xB4 + TOUCH_PAD13 volatile.Register32 // 0xB8 + TOUCH_PAD14 volatile.Register32 // 0xBC + XTAL_32P_PAD volatile.Register32 // 0xC0 + XTAL_32N_PAD volatile.Register32 // 0xC4 + PAD_DAC1 volatile.Register32 // 0xC8 + PAD_DAC2 volatile.Register32 // 0xCC + RTC_PAD19 volatile.Register32 // 0xD0 + RTC_PAD20 volatile.Register32 // 0xD4 + RTC_PAD21 volatile.Register32 // 0xD8 + EXT_WAKEUP0 volatile.Register32 // 0xDC + XTL_EXT_CTR volatile.Register32 // 0xE0 + SAR_I2C_IO volatile.Register32 // 0xE4 + TOUCH_CTRL volatile.Register32 // 0xE8 + _ [272]byte + DATE volatile.Register32 // 0x1FC +} + +// RTC_IO.RTC_GPIO_OUT: RTC GPIO 0 ~ 21 output data register +func (o *RTC_IO_Type) SetRTC_GPIO_OUT_DATA(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_OUT_DATA() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_OUT_W1TS: one set RTC GPIO output data +func (o *RTC_IO_Type) SetRTC_GPIO_OUT_W1TS_RTC_GPIO_OUT_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_OUT_W1TS_RTC_GPIO_OUT_DATA_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_OUT_W1TC: one clear RTC GPIO output data +func (o *RTC_IO_Type) SetRTC_GPIO_OUT_W1TC_RTC_GPIO_OUT_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_OUT_W1TC_RTC_GPIO_OUT_DATA_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_ENABLE: Configure RTC GPIO output enable +func (o *RTC_IO_Type) SetRTC_GPIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_ENABLE_W1TS: one set RTC GPIO output enable +func (o *RTC_IO_Type) SetRTC_GPIO_ENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_ENABLE_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.ENABLE_W1TC: one clear RTC GPIO output enable +func (o *RTC_IO_Type) SetENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.ENABLE_W1TC.Reg, volatile.LoadUint32(&o.ENABLE_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetENABLE_W1TC() uint32 { + return (volatile.LoadUint32(&o.ENABLE_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_STATUS: RTC GPIO 0 ~ 21 interrupt status +func (o *RTC_IO_Type) SetRTC_GPIO_STATUS_INT(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_STATUS_INT() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_STATUS_W1TS: One set RTC GPIO 0 ~ 21 interrupt status +func (o *RTC_IO_Type) SetRTC_GPIO_STATUS_W1TS_RTC_GPIO_STATUS_INT_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_STATUS_W1TS_RTC_GPIO_STATUS_INT_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_STATUS_W1TC: One clear RTC GPIO 0 ~ 21 interrupt status +func (o *RTC_IO_Type) SetRTC_GPIO_STATUS_W1TC_RTC_GPIO_STATUS_INT_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_STATUS_W1TC_RTC_GPIO_STATUS_INT_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_IN: RTC GPIO input data +func (o *RTC_IO_Type) SetRTC_GPIO_IN_NEXT(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_IN.Reg, volatile.LoadUint32(&o.RTC_GPIO_IN.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_IN_NEXT() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_IN.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.PIN0: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN1: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN2: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN3: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN4: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN5: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN6: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN7: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN8: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN9: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN10: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN11: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN12: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN13: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN14: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN15: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN16: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN17: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN18: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN19: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN20: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10 +} + +// RTC_IO.PIN21: configure RTC GPIO%s +func (o *RTC_IO_Type) SetPIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetPIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetPIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetPIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetPIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_DEBUG_SEL: configure rtc debug +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f)|value) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL0() uint32 { + return volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x3e0)|value<<5) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x3e0) >> 5 +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x7c00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x7c00) >> 10 +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0xf8000)|value<<15) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0xf8000) >> 15 +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f00000)|value<<20) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL4() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f00000) >> 20 +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x2000000) >> 25 +} + +// RTC_IO.TOUCH_PAD0: configure RTC PAD0 +func (o *RTC_IO_Type) SetTOUCH_PAD0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD1: configure RTC PAD1 +func (o *RTC_IO_Type) SetTOUCH_PAD1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD2: configure RTC PAD2 +func (o *RTC_IO_Type) SetTOUCH_PAD2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD3: configure RTC PAD3 +func (o *RTC_IO_Type) SetTOUCH_PAD3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD4: configure RTC PAD4 +func (o *RTC_IO_Type) SetTOUCH_PAD4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD5: configure RTC PAD5 +func (o *RTC_IO_Type) SetTOUCH_PAD5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD6: configure RTC PAD6 +func (o *RTC_IO_Type) SetTOUCH_PAD6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD7: configure RTC PAD7 +func (o *RTC_IO_Type) SetTOUCH_PAD7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD8: configure RTC PAD8 +func (o *RTC_IO_Type) SetTOUCH_PAD8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD9: configure RTC PAD9 +func (o *RTC_IO_Type) SetTOUCH_PAD9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD10: configure RTC PAD10 +func (o *RTC_IO_Type) SetTOUCH_PAD10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD11: configure RTC PAD11 +func (o *RTC_IO_Type) SetTOUCH_PAD11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD12: configure RTC PAD12 +func (o *RTC_IO_Type) SetTOUCH_PAD12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD13: configure RTC PAD13 +func (o *RTC_IO_Type) SetTOUCH_PAD13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD14: configure RTC PAD14 +func (o *RTC_IO_Type) SetTOUCH_PAD14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.XTAL_32P_PAD: configure RTC PAD15 +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.XTAL_32N_PAD: configure RTC PAD16 +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.PAD_DAC1: configure RTC PAD17 +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x7f8)|value<<3) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x7f8) >> 3 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x800)|value<<11) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x800) >> 11 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x1000) >> 12 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.PAD_DAC2: configure RTC PAD18 +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x7f8)|value<<3) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x7f8) >> 3 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x800)|value<<11) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x800) >> 11 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x1000) >> 12 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.RTC_PAD19: configure RTC PAD19 +func (o *RTC_IO_Type) SetRTC_PAD19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetRTC_PAD19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetRTC_PAD19_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetRTC_PAD19_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetRTC_PAD19_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetRTC_PAD19_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetRTC_PAD19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetRTC_PAD19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetRTC_PAD19_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetRTC_PAD19_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetRTC_PAD19_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetRTC_PAD19_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetRTC_PAD19_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetRTC_PAD19_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetRTC_PAD19_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetRTC_PAD19_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetRTC_PAD19_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetRTC_PAD19_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.RTC_PAD20: configure RTC PAD20 +func (o *RTC_IO_Type) SetRTC_PAD20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetRTC_PAD20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetRTC_PAD20_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetRTC_PAD20_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetRTC_PAD20_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetRTC_PAD20_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetRTC_PAD20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetRTC_PAD20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetRTC_PAD20_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetRTC_PAD20_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetRTC_PAD20_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetRTC_PAD20_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetRTC_PAD20_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetRTC_PAD20_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetRTC_PAD20_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetRTC_PAD20_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetRTC_PAD20_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetRTC_PAD20_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.RTC_PAD21: configure RTC PAD21 +func (o *RTC_IO_Type) SetRTC_PAD21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetRTC_PAD21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetRTC_PAD21_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetRTC_PAD21_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetRTC_PAD21_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetRTC_PAD21_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetRTC_PAD21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetRTC_PAD21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetRTC_PAD21_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetRTC_PAD21_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetRTC_PAD21_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetRTC_PAD21_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetRTC_PAD21_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetRTC_PAD21_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetRTC_PAD21_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetRTC_PAD21_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetRTC_PAD21_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetRTC_PAD21_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.EXT_WAKEUP0: configure EXT0 wakeup +func (o *RTC_IO_Type) SetEXT_WAKEUP0_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP0.Reg, volatile.LoadUint32(&o.EXT_WAKEUP0.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_IO_Type) GetEXT_WAKEUP0_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP0.Reg) & 0xf8000000) >> 27 +} + +// RTC_IO.XTL_EXT_CTR: configure gpio pd XTAL +func (o *RTC_IO_Type) SetXTL_EXT_CTR_SEL(value uint32) { + volatile.StoreUint32(&o.XTL_EXT_CTR.Reg, volatile.LoadUint32(&o.XTL_EXT_CTR.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_IO_Type) GetXTL_EXT_CTR_SEL() uint32 { + return (volatile.LoadUint32(&o.XTL_EXT_CTR.Reg) & 0xf8000000) >> 27 +} + +// RTC_IO.SAR_I2C_IO: configure rtc i2c mux +func (o *RTC_IO_Type) SetSAR_I2C_IO_SAR_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xf800000)|value<<23) +} +func (o *RTC_IO_Type) GetSAR_I2C_IO_SAR_DEBUG_BIT_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xf800000) >> 23 +} +func (o *RTC_IO_Type) SetSAR_I2C_IO_SAR_I2C_SCL_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0x30000000)|value<<28) +} +func (o *RTC_IO_Type) GetSAR_I2C_IO_SAR_I2C_SCL_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0x30000000) >> 28 +} +func (o *RTC_IO_Type) SetSAR_I2C_IO_SAR_I2C_SDA_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_IO_Type) GetSAR_I2C_IO_SAR_I2C_SDA_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xc0000000) >> 30 +} + +// RTC_IO.TOUCH_CTRL: configure touch pad bufmode +func (o *RTC_IO_Type) SetTOUCH_CTRL_IO_TOUCH_BUFSEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_CTRL.Reg)&^(0xf)|value) +} +func (o *RTC_IO_Type) GetTOUCH_CTRL_IO_TOUCH_BUFSEL() uint32 { + return volatile.LoadUint32(&o.TOUCH_CTRL.Reg) & 0xf +} +func (o *RTC_IO_Type) SetTOUCH_CTRL_IO_TOUCH_BUFMODE(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *RTC_IO_Type) GetTOUCH_CTRL_IO_TOUCH_BUFMODE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL.Reg) & 0x10) >> 4 +} + +// RTC_IO.DATE: version +func (o *RTC_IO_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_IO_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SD/MMC Host Controller +type SDHOST_Type struct { + CTRL volatile.Register32 // 0x0 + _ [4]byte + CLKDIV volatile.Register32 // 0x8 + CLKSRC volatile.Register32 // 0xC + CLKENA volatile.Register32 // 0x10 + TMOUT volatile.Register32 // 0x14 + CTYPE volatile.Register32 // 0x18 + BLKSIZ volatile.Register32 // 0x1C + BYTCNT volatile.Register32 // 0x20 + INTMASK volatile.Register32 // 0x24 + CMDARG volatile.Register32 // 0x28 + CMD volatile.Register32 // 0x2C + RESP0 volatile.Register32 // 0x30 + RESP1 volatile.Register32 // 0x34 + RESP2 volatile.Register32 // 0x38 + RESP3 volatile.Register32 // 0x3C + MINTSTS volatile.Register32 // 0x40 + RINTSTS volatile.Register32 // 0x44 + STATUS volatile.Register32 // 0x48 + FIFOTH volatile.Register32 // 0x4C + CDETECT volatile.Register32 // 0x50 + WRTPRT volatile.Register32 // 0x54 + _ [4]byte + TCBCNT volatile.Register32 // 0x5C + TBBCNT volatile.Register32 // 0x60 + DEBNCE volatile.Register32 // 0x64 + USRID volatile.Register32 // 0x68 + VERID volatile.Register32 // 0x6C + HCON volatile.Register32 // 0x70 + UHS volatile.Register32 // 0x74 + RST_N volatile.Register32 // 0x78 + _ [4]byte + BMOD volatile.Register32 // 0x80 + PLDMND volatile.Register32 // 0x84 + DBADDR volatile.Register32 // 0x88 + IDSTS volatile.Register32 // 0x8C + IDINTEN volatile.Register32 // 0x90 + DSCADDR volatile.Register32 // 0x94 + BUFADDR volatile.Register32 // 0x98 + _ [100]byte + CARDTHRCTL volatile.Register32 // 0x100 + _ [8]byte + EMMCDDR volatile.Register32 // 0x10C + ENSHIFT volatile.Register32 // 0x110 + _ [236]byte + BUFFIFO volatile.Register32 // 0x200 + _ [1532]byte + CLK_EDGE_SEL volatile.Register32 // 0x800 +} + +// SDHOST.CTRL: Control register +func (o *SDHOST_Type) SetCTRL_CONTROLLER_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetCTRL_CONTROLLER_RESET() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *SDHOST_Type) SetCTRL_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetCTRL_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetCTRL_DMA_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetCTRL_DMA_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetCTRL_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SDHOST_Type) GetCTRL_INT_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *SDHOST_Type) SetCTRL_READ_WAIT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SDHOST_Type) GetCTRL_READ_WAIT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SDHOST_Type) SetCTRL_SEND_IRQ_RESPONSE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SDHOST_Type) GetCTRL_SEND_IRQ_RESPONSE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SDHOST_Type) SetCTRL_ABORT_READ_DATA(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetCTRL_ABORT_READ_DATA() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetCTRL_SEND_CCSD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetCTRL_SEND_CCSD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetCTRL_SEND_AUTO_STOP_CCSD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SDHOST_Type) GetCTRL_SEND_AUTO_STOP_CCSD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SDHOST_Type) SetCTRL_CEATA_DEVICE_INTERRUPT_STATUS(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SDHOST_Type) GetCTRL_CEATA_DEVICE_INTERRUPT_STATUS() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11 +} + +// SDHOST.CLKDIV: Clock divider configuration register +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER0(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff)|value) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER0() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff +} +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER1(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff00)|value<<8) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER1() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff00) >> 8 +} +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER2(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff0000)|value<<16) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER2() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff0000) >> 16 +} +func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER3(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff000000)|value<<24) +} +func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER3() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff000000) >> 24 +} + +// SDHOST.CLKSRC: Clock source selection register +func (o *SDHOST_Type) SetCLKSRC(value uint32) { + volatile.StoreUint32(&o.CLKSRC.Reg, volatile.LoadUint32(&o.CLKSRC.Reg)&^(0xf)|value) +} +func (o *SDHOST_Type) GetCLKSRC() uint32 { + return volatile.LoadUint32(&o.CLKSRC.Reg) & 0xf +} + +// SDHOST.CLKENA: Clock enable register +func (o *SDHOST_Type) SetCLKENA_CCLK_ENABLE(value uint32) { + volatile.StoreUint32(&o.CLKENA.Reg, volatile.LoadUint32(&o.CLKENA.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetCLKENA_CCLK_ENABLE() uint32 { + return volatile.LoadUint32(&o.CLKENA.Reg) & 0x3 +} +func (o *SDHOST_Type) SetCLKENA_LP_ENABLE(value uint32) { + volatile.StoreUint32(&o.CLKENA.Reg, volatile.LoadUint32(&o.CLKENA.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetCLKENA_LP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CLKENA.Reg) & 0x30000) >> 16 +} + +// SDHOST.TMOUT: Data and response timeout configuration register +func (o *SDHOST_Type) SetTMOUT_RESPONSE_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.TMOUT.Reg, volatile.LoadUint32(&o.TMOUT.Reg)&^(0xff)|value) +} +func (o *SDHOST_Type) GetTMOUT_RESPONSE_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.TMOUT.Reg) & 0xff +} +func (o *SDHOST_Type) SetTMOUT_DATA_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.TMOUT.Reg, volatile.LoadUint32(&o.TMOUT.Reg)&^(0xffffff00)|value<<8) +} +func (o *SDHOST_Type) GetTMOUT_DATA_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.TMOUT.Reg) & 0xffffff00) >> 8 +} + +// SDHOST.CTYPE: Card bus width configuration register +func (o *SDHOST_Type) SetCTYPE_CARD_WIDTH4(value uint32) { + volatile.StoreUint32(&o.CTYPE.Reg, volatile.LoadUint32(&o.CTYPE.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetCTYPE_CARD_WIDTH4() uint32 { + return volatile.LoadUint32(&o.CTYPE.Reg) & 0x3 +} +func (o *SDHOST_Type) SetCTYPE_CARD_WIDTH8(value uint32) { + volatile.StoreUint32(&o.CTYPE.Reg, volatile.LoadUint32(&o.CTYPE.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetCTYPE_CARD_WIDTH8() uint32 { + return (volatile.LoadUint32(&o.CTYPE.Reg) & 0x30000) >> 16 +} + +// SDHOST.BLKSIZ: Card data block size configuration register +func (o *SDHOST_Type) SetBLKSIZ_BLOCK_SIZE(value uint32) { + volatile.StoreUint32(&o.BLKSIZ.Reg, volatile.LoadUint32(&o.BLKSIZ.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetBLKSIZ_BLOCK_SIZE() uint32 { + return volatile.LoadUint32(&o.BLKSIZ.Reg) & 0xffff +} + +// SDHOST.BYTCNT: Data transfer length configuration register +func (o *SDHOST_Type) SetBYTCNT(value uint32) { + volatile.StoreUint32(&o.BYTCNT.Reg, value) +} +func (o *SDHOST_Type) GetBYTCNT() uint32 { + return volatile.LoadUint32(&o.BYTCNT.Reg) +} + +// SDHOST.INTMASK: SDIO interrupt mask register +func (o *SDHOST_Type) SetINTMASK_INT_MASK(value uint32) { + volatile.StoreUint32(&o.INTMASK.Reg, volatile.LoadUint32(&o.INTMASK.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetINTMASK_INT_MASK() uint32 { + return volatile.LoadUint32(&o.INTMASK.Reg) & 0xffff +} +func (o *SDHOST_Type) SetINTMASK_SDIO_INT_MASK(value uint32) { + volatile.StoreUint32(&o.INTMASK.Reg, volatile.LoadUint32(&o.INTMASK.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetINTMASK_SDIO_INT_MASK() uint32 { + return (volatile.LoadUint32(&o.INTMASK.Reg) & 0x30000) >> 16 +} + +// SDHOST.CMDARG: Command argument data register +func (o *SDHOST_Type) SetCMDARG(value uint32) { + volatile.StoreUint32(&o.CMDARG.Reg, value) +} +func (o *SDHOST_Type) GetCMDARG() uint32 { + return volatile.LoadUint32(&o.CMDARG.Reg) +} + +// SDHOST.CMD: Command and boot configuration register +func (o *SDHOST_Type) SetCMD_INDEX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3f)|value) +} +func (o *SDHOST_Type) GetCMD_INDEX() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x3f +} +func (o *SDHOST_Type) SetCMD_RESPONSE_EXPECT(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40)|value<<6) +} +func (o *SDHOST_Type) GetCMD_RESPONSE_EXPECT() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40) >> 6 +} +func (o *SDHOST_Type) SetCMD_RESPONSE_LENGTH(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80)|value<<7) +} +func (o *SDHOST_Type) GetCMD_RESPONSE_LENGTH() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80) >> 7 +} +func (o *SDHOST_Type) SetCMD_CHECK_RESPONSE_CRC(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetCMD_CHECK_RESPONSE_CRC() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetCMD_DATA_EXPECTED(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetCMD_DATA_EXPECTED() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetCMD_READ_WRITE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400)|value<<10) +} +func (o *SDHOST_Type) GetCMD_READ_WRITE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400) >> 10 +} +func (o *SDHOST_Type) SetCMD_TRANSFER_MODE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800)|value<<11) +} +func (o *SDHOST_Type) GetCMD_TRANSFER_MODE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800) >> 11 +} +func (o *SDHOST_Type) SetCMD_SEND_AUTO_STOP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000)|value<<12) +} +func (o *SDHOST_Type) GetCMD_SEND_AUTO_STOP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000) >> 12 +} +func (o *SDHOST_Type) SetCMD_WAIT_PRVDATA_COMPLETE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2000)|value<<13) +} +func (o *SDHOST_Type) GetCMD_WAIT_PRVDATA_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2000) >> 13 +} +func (o *SDHOST_Type) SetCMD_STOP_ABORT_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4000)|value<<14) +} +func (o *SDHOST_Type) GetCMD_STOP_ABORT_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4000) >> 14 +} +func (o *SDHOST_Type) SetCMD_SEND_INITIALIZATION(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8000)|value<<15) +} +func (o *SDHOST_Type) GetCMD_SEND_INITIALIZATION() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8000) >> 15 +} +func (o *SDHOST_Type) SetCMD_CARD_NUMBER(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1f0000)|value<<16) +} +func (o *SDHOST_Type) GetCMD_CARD_NUMBER() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1f0000) >> 16 +} +func (o *SDHOST_Type) SetCMD_UPDATE_CLOCK_REGISTERS_ONLY(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SDHOST_Type) GetCMD_UPDATE_CLOCK_REGISTERS_ONLY() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200000) >> 21 +} +func (o *SDHOST_Type) SetCMD_READ_CEATA_DEVICE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SDHOST_Type) GetCMD_READ_CEATA_DEVICE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400000) >> 22 +} +func (o *SDHOST_Type) SetCMD_CCS_EXPECTED(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SDHOST_Type) GetCMD_CCS_EXPECTED() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SDHOST_Type) SetCMD_USE_HOLE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SDHOST_Type) GetCMD_USE_HOLE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29 +} +func (o *SDHOST_Type) SetCMD_START_CMD(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SDHOST_Type) GetCMD_START_CMD() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31 +} + +// SDHOST.RESP0: Response data register +func (o *SDHOST_Type) SetRESP0(value uint32) { + volatile.StoreUint32(&o.RESP0.Reg, value) +} +func (o *SDHOST_Type) GetRESP0() uint32 { + return volatile.LoadUint32(&o.RESP0.Reg) +} + +// SDHOST.RESP1: Long response data register +func (o *SDHOST_Type) SetRESP1(value uint32) { + volatile.StoreUint32(&o.RESP1.Reg, value) +} +func (o *SDHOST_Type) GetRESP1() uint32 { + return volatile.LoadUint32(&o.RESP1.Reg) +} + +// SDHOST.RESP2: Long response data register +func (o *SDHOST_Type) SetRESP2(value uint32) { + volatile.StoreUint32(&o.RESP2.Reg, value) +} +func (o *SDHOST_Type) GetRESP2() uint32 { + return volatile.LoadUint32(&o.RESP2.Reg) +} + +// SDHOST.RESP3: Long response data register +func (o *SDHOST_Type) SetRESP3(value uint32) { + volatile.StoreUint32(&o.RESP3.Reg, value) +} +func (o *SDHOST_Type) GetRESP3() uint32 { + return volatile.LoadUint32(&o.RESP3.Reg) +} + +// SDHOST.MINTSTS: Masked interrupt status register +func (o *SDHOST_Type) SetMINTSTS_INT_STATUS_MSK(value uint32) { + volatile.StoreUint32(&o.MINTSTS.Reg, volatile.LoadUint32(&o.MINTSTS.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetMINTSTS_INT_STATUS_MSK() uint32 { + return volatile.LoadUint32(&o.MINTSTS.Reg) & 0xffff +} +func (o *SDHOST_Type) SetMINTSTS_SDIO_INTERRUPT_MSK(value uint32) { + volatile.StoreUint32(&o.MINTSTS.Reg, volatile.LoadUint32(&o.MINTSTS.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetMINTSTS_SDIO_INTERRUPT_MSK() uint32 { + return (volatile.LoadUint32(&o.MINTSTS.Reg) & 0x30000) >> 16 +} + +// SDHOST.RINTSTS: Raw interrupt status register +func (o *SDHOST_Type) SetRINTSTS_INT_STATUS_RAW(value uint32) { + volatile.StoreUint32(&o.RINTSTS.Reg, volatile.LoadUint32(&o.RINTSTS.Reg)&^(0xffff)|value) +} +func (o *SDHOST_Type) GetRINTSTS_INT_STATUS_RAW() uint32 { + return volatile.LoadUint32(&o.RINTSTS.Reg) & 0xffff +} +func (o *SDHOST_Type) SetRINTSTS_SDIO_INTERRUPT_RAW(value uint32) { + volatile.StoreUint32(&o.RINTSTS.Reg, volatile.LoadUint32(&o.RINTSTS.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetRINTSTS_SDIO_INTERRUPT_RAW() uint32 { + return (volatile.LoadUint32(&o.RINTSTS.Reg) & 0x30000) >> 16 +} + +// SDHOST.STATUS: SD/MMC status register +func (o *SDHOST_Type) SetSTATUS_FIFO_RX_WATERMARK(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_RX_WATERMARK() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_TX_WATERMARK(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_TX_WATERMARK() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *SDHOST_Type) SetSTATUS_COMMAND_FSM_STATES(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *SDHOST_Type) GetSTATUS_COMMAND_FSM_STATES() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf0) >> 4 +} +func (o *SDHOST_Type) SetSTATUS_DATA_3_STATUS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetSTATUS_DATA_3_STATUS() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetSTATUS_DATA_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetSTATUS_DATA_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetSTATUS_DATA_STATE_MC_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400)|value<<10) +} +func (o *SDHOST_Type) GetSTATUS_DATA_STATE_MC_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400) >> 10 +} +func (o *SDHOST_Type) SetSTATUS_RESPONSE_INDEX(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1f800)|value<<11) +} +func (o *SDHOST_Type) GetSTATUS_RESPONSE_INDEX() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1f800) >> 11 +} +func (o *SDHOST_Type) SetSTATUS_FIFO_COUNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ffe0000)|value<<17) +} +func (o *SDHOST_Type) GetSTATUS_FIFO_COUNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3ffe0000) >> 17 +} + +// SDHOST.FIFOTH: FIFO configuration register +func (o *SDHOST_Type) SetFIFOTH_TX_WMARK(value uint32) { + volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0xfff)|value) +} +func (o *SDHOST_Type) GetFIFOTH_TX_WMARK() uint32 { + return volatile.LoadUint32(&o.FIFOTH.Reg) & 0xfff +} +func (o *SDHOST_Type) SetFIFOTH_RX_WMARK(value uint32) { + volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0x7ff0000)|value<<16) +} +func (o *SDHOST_Type) GetFIFOTH_RX_WMARK() uint32 { + return (volatile.LoadUint32(&o.FIFOTH.Reg) & 0x7ff0000) >> 16 +} +func (o *SDHOST_Type) SetFIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE(value uint32) { + volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0x70000000)|value<<28) +} +func (o *SDHOST_Type) GetFIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE() uint32 { + return (volatile.LoadUint32(&o.FIFOTH.Reg) & 0x70000000) >> 28 +} + +// SDHOST.CDETECT: Card detect register +func (o *SDHOST_Type) SetCDETECT_CARD_DETECT_N(value uint32) { + volatile.StoreUint32(&o.CDETECT.Reg, volatile.LoadUint32(&o.CDETECT.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetCDETECT_CARD_DETECT_N() uint32 { + return volatile.LoadUint32(&o.CDETECT.Reg) & 0x3 +} + +// SDHOST.WRTPRT: Card write protection (WP) status register +func (o *SDHOST_Type) SetWRTPRT_WRITE_PROTECT(value uint32) { + volatile.StoreUint32(&o.WRTPRT.Reg, volatile.LoadUint32(&o.WRTPRT.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetWRTPRT_WRITE_PROTECT() uint32 { + return volatile.LoadUint32(&o.WRTPRT.Reg) & 0x3 +} + +// SDHOST.TCBCNT: Transferred byte count register +func (o *SDHOST_Type) SetTCBCNT(value uint32) { + volatile.StoreUint32(&o.TCBCNT.Reg, value) +} +func (o *SDHOST_Type) GetTCBCNT() uint32 { + return volatile.LoadUint32(&o.TCBCNT.Reg) +} + +// SDHOST.TBBCNT: Transferred byte count register +func (o *SDHOST_Type) SetTBBCNT(value uint32) { + volatile.StoreUint32(&o.TBBCNT.Reg, value) +} +func (o *SDHOST_Type) GetTBBCNT() uint32 { + return volatile.LoadUint32(&o.TBBCNT.Reg) +} + +// SDHOST.DEBNCE: Debounce filter time configuration register +func (o *SDHOST_Type) SetDEBNCE_DEBOUNCE_COUNT(value uint32) { + volatile.StoreUint32(&o.DEBNCE.Reg, volatile.LoadUint32(&o.DEBNCE.Reg)&^(0xffffff)|value) +} +func (o *SDHOST_Type) GetDEBNCE_DEBOUNCE_COUNT() uint32 { + return volatile.LoadUint32(&o.DEBNCE.Reg) & 0xffffff +} + +// SDHOST.USRID: User ID (scratchpad) register +func (o *SDHOST_Type) SetUSRID(value uint32) { + volatile.StoreUint32(&o.USRID.Reg, value) +} +func (o *SDHOST_Type) GetUSRID() uint32 { + return volatile.LoadUint32(&o.USRID.Reg) +} + +// SDHOST.VERID: Version ID (scratchpad) register +func (o *SDHOST_Type) SetVERID(value uint32) { + volatile.StoreUint32(&o.VERID.Reg, value) +} +func (o *SDHOST_Type) GetVERID() uint32 { + return volatile.LoadUint32(&o.VERID.Reg) +} + +// SDHOST.HCON: Hardware feature register +func (o *SDHOST_Type) SetHCON_CARD_TYPE(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetHCON_CARD_TYPE() uint32 { + return volatile.LoadUint32(&o.HCON.Reg) & 0x1 +} +func (o *SDHOST_Type) SetHCON_CARD_NUM(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x3e)|value<<1) +} +func (o *SDHOST_Type) GetHCON_CARD_NUM() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x3e) >> 1 +} +func (o *SDHOST_Type) SetHCON_BUS_TYPE(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x40)|value<<6) +} +func (o *SDHOST_Type) GetHCON_BUS_TYPE() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x40) >> 6 +} +func (o *SDHOST_Type) SetHCON_DATA_WIDTH(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x380)|value<<7) +} +func (o *SDHOST_Type) GetHCON_DATA_WIDTH() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x380) >> 7 +} +func (o *SDHOST_Type) SetHCON_ADDR_WIDTH(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0xfc00)|value<<10) +} +func (o *SDHOST_Type) GetHCON_ADDR_WIDTH() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0xfc00) >> 10 +} +func (o *SDHOST_Type) SetHCON_DMA_WIDTH(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x1c0000)|value<<18) +} +func (o *SDHOST_Type) GetHCON_DMA_WIDTH() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x1c0000) >> 18 +} +func (o *SDHOST_Type) SetHCON_RAM_INDISE(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x200000)|value<<21) +} +func (o *SDHOST_Type) GetHCON_RAM_INDISE() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x200000) >> 21 +} +func (o *SDHOST_Type) SetHCON_HOLD(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x400000)|value<<22) +} +func (o *SDHOST_Type) GetHCON_HOLD() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x400000) >> 22 +} +func (o *SDHOST_Type) SetHCON_NUM_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x3000000)|value<<24) +} +func (o *SDHOST_Type) GetHCON_NUM_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.HCON.Reg) & 0x3000000) >> 24 +} + +// SDHOST.UHS: UHS-1 register +func (o *SDHOST_Type) SetUHS_DDR(value uint32) { + volatile.StoreUint32(&o.UHS.Reg, volatile.LoadUint32(&o.UHS.Reg)&^(0x30000)|value<<16) +} +func (o *SDHOST_Type) GetUHS_DDR() uint32 { + return (volatile.LoadUint32(&o.UHS.Reg) & 0x30000) >> 16 +} + +// SDHOST.RST_N: Card reset register +func (o *SDHOST_Type) SetRST_N_CARD_RESET(value uint32) { + volatile.StoreUint32(&o.RST_N.Reg, volatile.LoadUint32(&o.RST_N.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetRST_N_CARD_RESET() uint32 { + return volatile.LoadUint32(&o.RST_N.Reg) & 0x3 +} + +// SDHOST.BMOD: Burst mode transfer configuration register +func (o *SDHOST_Type) SetBMOD_SWR(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetBMOD_SWR() uint32 { + return volatile.LoadUint32(&o.BMOD.Reg) & 0x1 +} +func (o *SDHOST_Type) SetBMOD_FB(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetBMOD_FB() uint32 { + return (volatile.LoadUint32(&o.BMOD.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetBMOD_DE(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x80)|value<<7) +} +func (o *SDHOST_Type) GetBMOD_DE() uint32 { + return (volatile.LoadUint32(&o.BMOD.Reg) & 0x80) >> 7 +} +func (o *SDHOST_Type) SetBMOD_PBL(value uint32) { + volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x700)|value<<8) +} +func (o *SDHOST_Type) GetBMOD_PBL() uint32 { + return (volatile.LoadUint32(&o.BMOD.Reg) & 0x700) >> 8 +} + +// SDHOST.PLDMND: Poll demand configuration register +func (o *SDHOST_Type) SetPLDMND(value uint32) { + volatile.StoreUint32(&o.PLDMND.Reg, value) +} +func (o *SDHOST_Type) GetPLDMND() uint32 { + return volatile.LoadUint32(&o.PLDMND.Reg) +} + +// SDHOST.DBADDR: Descriptor base address register +func (o *SDHOST_Type) SetDBADDR(value uint32) { + volatile.StoreUint32(&o.DBADDR.Reg, value) +} +func (o *SDHOST_Type) GetDBADDR() uint32 { + return volatile.LoadUint32(&o.DBADDR.Reg) +} + +// SDHOST.IDSTS: IDMAC status register +func (o *SDHOST_Type) SetIDSTS_TI(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetIDSTS_TI() uint32 { + return volatile.LoadUint32(&o.IDSTS.Reg) & 0x1 +} +func (o *SDHOST_Type) SetIDSTS_RI(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetIDSTS_RI() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetIDSTS_FBE(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetIDSTS_FBE() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetIDSTS_DU(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x10)|value<<4) +} +func (o *SDHOST_Type) GetIDSTS_DU() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x10) >> 4 +} +func (o *SDHOST_Type) SetIDSTS_CES(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x20)|value<<5) +} +func (o *SDHOST_Type) GetIDSTS_CES() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x20) >> 5 +} +func (o *SDHOST_Type) SetIDSTS_NIS(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetIDSTS_NIS() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetIDSTS_AIS(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetIDSTS_AIS() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x200) >> 9 +} +func (o *SDHOST_Type) SetIDSTS_FBE_CODE(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1c00)|value<<10) +} +func (o *SDHOST_Type) GetIDSTS_FBE_CODE() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x1c00) >> 10 +} +func (o *SDHOST_Type) SetIDSTS_FSM(value uint32) { + volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1e000)|value<<13) +} +func (o *SDHOST_Type) GetIDSTS_FSM() uint32 { + return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x1e000) >> 13 +} + +// SDHOST.IDINTEN: IDMAC interrupt enable register +func (o *SDHOST_Type) SetIDINTEN_TI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetIDINTEN_TI() uint32 { + return volatile.LoadUint32(&o.IDINTEN.Reg) & 0x1 +} +func (o *SDHOST_Type) SetIDINTEN_RI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetIDINTEN_RI() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetIDINTEN_FBE(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetIDINTEN_FBE() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetIDINTEN_DU(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x10)|value<<4) +} +func (o *SDHOST_Type) GetIDINTEN_DU() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x10) >> 4 +} +func (o *SDHOST_Type) SetIDINTEN_CES(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x20)|value<<5) +} +func (o *SDHOST_Type) GetIDINTEN_CES() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x20) >> 5 +} +func (o *SDHOST_Type) SetIDINTEN_NI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x100)|value<<8) +} +func (o *SDHOST_Type) GetIDINTEN_NI() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x100) >> 8 +} +func (o *SDHOST_Type) SetIDINTEN_AI(value uint32) { + volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x200)|value<<9) +} +func (o *SDHOST_Type) GetIDINTEN_AI() uint32 { + return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x200) >> 9 +} + +// SDHOST.DSCADDR: Host descriptor address pointer +func (o *SDHOST_Type) SetDSCADDR(value uint32) { + volatile.StoreUint32(&o.DSCADDR.Reg, value) +} +func (o *SDHOST_Type) GetDSCADDR() uint32 { + return volatile.LoadUint32(&o.DSCADDR.Reg) +} + +// SDHOST.BUFADDR: Host buffer address pointer register +func (o *SDHOST_Type) SetBUFADDR(value uint32) { + volatile.StoreUint32(&o.BUFADDR.Reg, value) +} +func (o *SDHOST_Type) GetBUFADDR() uint32 { + return volatile.LoadUint32(&o.BUFADDR.Reg) +} + +// SDHOST.CARDTHRCTL: Card Threshold Control register +func (o *SDHOST_Type) SetCARDTHRCTL_CARDRDTHREN(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x1)|value) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDRDTHREN() uint32 { + return volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x1 +} +func (o *SDHOST_Type) SetCARDTHRCTL_CARDCLRINTEN(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x2)|value<<1) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDCLRINTEN() uint32 { + return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x2) >> 1 +} +func (o *SDHOST_Type) SetCARDTHRCTL_CARDWRTHREN(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x4)|value<<2) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDWRTHREN() uint32 { + return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x4) >> 2 +} +func (o *SDHOST_Type) SetCARDTHRCTL_CARDTHRESHOLD(value uint32) { + volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0xffff0000)|value<<16) +} +func (o *SDHOST_Type) GetCARDTHRCTL_CARDTHRESHOLD() uint32 { + return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0xffff0000) >> 16 +} + +// SDHOST.EMMCDDR: eMMC DDR register +func (o *SDHOST_Type) SetEMMCDDR_HALFSTARTBIT(value uint32) { + volatile.StoreUint32(&o.EMMCDDR.Reg, volatile.LoadUint32(&o.EMMCDDR.Reg)&^(0x3)|value) +} +func (o *SDHOST_Type) GetEMMCDDR_HALFSTARTBIT() uint32 { + return volatile.LoadUint32(&o.EMMCDDR.Reg) & 0x3 +} +func (o *SDHOST_Type) SetEMMCDDR_HS400_MODE(value uint32) { + volatile.StoreUint32(&o.EMMCDDR.Reg, volatile.LoadUint32(&o.EMMCDDR.Reg)&^(0x80000000)|value<<31) +} +func (o *SDHOST_Type) GetEMMCDDR_HS400_MODE() uint32 { + return (volatile.LoadUint32(&o.EMMCDDR.Reg) & 0x80000000) >> 31 +} + +// SDHOST.ENSHIFT: Enable Phase Shift register +func (o *SDHOST_Type) SetENSHIFT_ENABLE_SHIFT(value uint32) { + volatile.StoreUint32(&o.ENSHIFT.Reg, volatile.LoadUint32(&o.ENSHIFT.Reg)&^(0xf)|value) +} +func (o *SDHOST_Type) GetENSHIFT_ENABLE_SHIFT() uint32 { + return volatile.LoadUint32(&o.ENSHIFT.Reg) & 0xf +} + +// SDHOST.BUFFIFO: CPU write and read transmit data by FIFO +func (o *SDHOST_Type) SetBUFFIFO(value uint32) { + volatile.StoreUint32(&o.BUFFIFO.Reg, value) +} +func (o *SDHOST_Type) GetBUFFIFO() uint32 { + return volatile.LoadUint32(&o.BUFFIFO.Reg) +} + +// SDHOST.CLK_EDGE_SEL: SDIO control register. +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x7)|value) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL() uint32 { + return volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x7 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x38)|value<<3) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x38) >> 3 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1c0)|value<<6) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1c0) >> 6 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_H(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e00)|value<<9) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_H() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e00) >> 9 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_L(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e000)|value<<13) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_L() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e000) >> 13 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_N(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e0000)|value<<17) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_N() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e0000) >> 17 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_ESDIO_MODE(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x200000)|value<<21) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_ESDIO_MODE() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x200000) >> 21 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_ESD_MODE(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x400000)|value<<22) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_ESD_MODE() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x400000) >> 22 +} +func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x800000)|value<<23) +} +func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x800000) >> 23 +} + +// SENS Peripheral +type SENS_Type struct { + SAR_READER1_CTRL volatile.Register32 // 0x0 + SAR_READER1_STATUS volatile.Register32 // 0x4 + SAR_MEAS1_CTRL1 volatile.Register32 // 0x8 + SAR_MEAS1_CTRL2 volatile.Register32 // 0xC + SAR_MEAS1_MUX volatile.Register32 // 0x10 + SAR_ATTEN1 volatile.Register32 // 0x14 + SAR_AMP_CTRL1 volatile.Register32 // 0x18 + SAR_AMP_CTRL2 volatile.Register32 // 0x1C + SAR_AMP_CTRL3 volatile.Register32 // 0x20 + SAR_READER2_CTRL volatile.Register32 // 0x24 + SAR_READER2_STATUS volatile.Register32 // 0x28 + SAR_MEAS2_CTRL1 volatile.Register32 // 0x2C + SAR_MEAS2_CTRL2 volatile.Register32 // 0x30 + SAR_MEAS2_MUX volatile.Register32 // 0x34 + SAR_ATTEN2 volatile.Register32 // 0x38 + SAR_POWER_XPD_SAR volatile.Register32 // 0x3C + SAR_SLAVE_ADDR1 volatile.Register32 // 0x40 + SAR_SLAVE_ADDR2 volatile.Register32 // 0x44 + SAR_SLAVE_ADDR3 volatile.Register32 // 0x48 + SAR_SLAVE_ADDR4 volatile.Register32 // 0x4C + SAR_TSENS_CTRL volatile.Register32 // 0x50 + SAR_TSENS_CTRL2 volatile.Register32 // 0x54 + SAR_I2C_CTRL volatile.Register32 // 0x58 + SAR_TOUCH_CONF volatile.Register32 // 0x5C + SAR_TOUCH_DENOISE volatile.Register32 // 0x60 + SAR_TOUCH_THRES1 volatile.Register32 // 0x64 + SAR_TOUCH_THRES2 volatile.Register32 // 0x68 + SAR_TOUCH_THRES3 volatile.Register32 // 0x6C + SAR_TOUCH_THRES4 volatile.Register32 // 0x70 + SAR_TOUCH_THRES5 volatile.Register32 // 0x74 + SAR_TOUCH_THRES6 volatile.Register32 // 0x78 + SAR_TOUCH_THRES7 volatile.Register32 // 0x7C + SAR_TOUCH_THRES8 volatile.Register32 // 0x80 + SAR_TOUCH_THRES9 volatile.Register32 // 0x84 + SAR_TOUCH_THRES10 volatile.Register32 // 0x88 + SAR_TOUCH_THRES11 volatile.Register32 // 0x8C + SAR_TOUCH_THRES12 volatile.Register32 // 0x90 + SAR_TOUCH_THRES13 volatile.Register32 // 0x94 + SAR_TOUCH_THRES14 volatile.Register32 // 0x98 + SAR_TOUCH_CHN_ST volatile.Register32 // 0x9C + SAR_TOUCH_STATUS0 volatile.Register32 // 0xA0 + SAR_TOUCH_STATUS1 volatile.Register32 // 0xA4 + SAR_TOUCH_STATUS2 volatile.Register32 // 0xA8 + SAR_TOUCH_STATUS3 volatile.Register32 // 0xAC + SAR_TOUCH_STATUS4 volatile.Register32 // 0xB0 + SAR_TOUCH_STATUS5 volatile.Register32 // 0xB4 + SAR_TOUCH_STATUS6 volatile.Register32 // 0xB8 + SAR_TOUCH_STATUS7 volatile.Register32 // 0xBC + SAR_TOUCH_STATUS8 volatile.Register32 // 0xC0 + SAR_TOUCH_STATUS9 volatile.Register32 // 0xC4 + SAR_TOUCH_STATUS10 volatile.Register32 // 0xC8 + SAR_TOUCH_STATUS11 volatile.Register32 // 0xCC + SAR_TOUCH_STATUS12 volatile.Register32 // 0xD0 + SAR_TOUCH_STATUS13 volatile.Register32 // 0xD4 + SAR_TOUCH_STATUS14 volatile.Register32 // 0xD8 + SAR_TOUCH_STATUS15 volatile.Register32 // 0xDC + SAR_TOUCH_STATUS16 volatile.Register32 // 0xE0 + SAR_COCPU_STATE volatile.Register32 // 0xE4 + SAR_COCPU_INT_RAW volatile.Register32 // 0xE8 + SAR_COCPU_INT_ENA volatile.Register32 // 0xEC + SAR_COCPU_INT_ST volatile.Register32 // 0xF0 + SAR_COCPU_INT_CLR volatile.Register32 // 0xF4 + SAR_COCPU_DEBUG volatile.Register32 // 0xF8 + SAR_HALL_CTRL volatile.Register32 // 0xFC + SAR_NOUSE volatile.Register32 // 0x100 + SAR_PERI_CLK_GATE_CONF volatile.Register32 // 0x104 + SAR_PERI_RESET_CONF volatile.Register32 // 0x108 + SAR_COCPU_INT_ENA_W1TS volatile.Register32 // 0x10C + SAR_COCPU_INT_ENA_W1TC volatile.Register32 // 0x110 + SAR_DEBUG_CONF volatile.Register32 // 0x114 + _ [228]byte + SAR_SARDATE volatile.Register32 // 0x1FC +} + +// SENS.SAR_READER1_CTRL: configure saradc1 reader +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR_SAR1_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR_SAR1_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR_SAR1_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR_SAR1_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR_SAR1_SAMPLE_NUM(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0x7f80000)|value<<19) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR_SAR1_SAMPLE_NUM() uint32 { + return (volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0x7f80000) >> 19 +} +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR_SAR1_DATA_INV(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR_SAR1_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_READER1_CTRL_SAR_SAR1_INT_EN(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_READER1_CTRL_SAR_SAR1_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_READER1_CTRL.Reg) & 0x20000000) >> 29 +} + +// SENS.SAR_READER1_STATUS: get saradc1 reader controller status +func (o *SENS_Type) SetSAR_READER1_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR_READER1_STATUS.Reg, value) +} +func (o *SENS_Type) GetSAR_READER1_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR_READER1_STATUS.Reg) +} + +// SENS.SAR_MEAS1_CTRL1: no public +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_FORCE_XPD_AMP(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0x3000000)|value<<24) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_FORCE_XPD_AMP() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0x3000000) >> 24 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_AMP_RST_FB_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0xc000000)|value<<26) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_AMP_RST_FB_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0xc000000) >> 26 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_AMP_SHORT_REF_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0x30000000)|value<<28) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_AMP_SHORT_REF_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0x30000000) >> 28 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL1.Reg) & 0xc0000000) >> 30 +} + +// SENS.SAR_MEAS1_CTRL2: configure saradc1 controller +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_MEAS1_DATA_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_MEAS1_DATA_SAR() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_MEAS1_DONE_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_MEAS1_DONE_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x10000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_MEAS1_START_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x20000)|value<<17) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_MEAS1_START_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x20000) >> 17 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_MEAS1_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_MEAS1_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_SAR1_EN_PAD(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x7ff80000)|value<<19) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_SAR1_EN_PAD() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x7ff80000) >> 19 +} +func (o *SENS_Type) SetSAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_MEAS1_MUX: configure saradc1 controller +func (o *SENS_Type) SetSAR_MEAS1_MUX_SAR1_DIG_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS1_MUX.Reg, volatile.LoadUint32(&o.SAR_MEAS1_MUX.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS1_MUX_SAR1_DIG_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS1_MUX.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_ATTEN1: configure saradc1 controller +func (o *SENS_Type) SetSAR_ATTEN1(value uint32) { + volatile.StoreUint32(&o.SAR_ATTEN1.Reg, value) +} +func (o *SENS_Type) GetSAR_ATTEN1() uint32 { + return volatile.LoadUint32(&o.SAR_ATTEN1.Reg) +} + +// SENS.SAR_AMP_CTRL1: no public +func (o *SENS_Type) SetSAR_AMP_CTRL1_SAR_AMP_WAIT1(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL1.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL1.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_AMP_CTRL1_SAR_AMP_WAIT1() uint32 { + return volatile.LoadUint32(&o.SAR_AMP_CTRL1.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_AMP_CTRL1_SAR_AMP_WAIT2(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL1.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL1.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_AMP_CTRL1_SAR_AMP_WAIT2() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL1.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_AMP_CTRL2: no public +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_SAR1_DAC_XPD_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_SAR1_DAC_XPD_FSM_IDLE() uint32 { + return volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_XPD_SAR_AMP_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_XPD_SAR_AMP_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_AMP_RST_FB_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_AMP_RST_FB_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_AMP_SHORT_REF_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_AMP_SHORT_REF_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_AMP_SHORT_REF_GND_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_AMP_SHORT_REF_GND_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_XPD_SAR_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_XPD_SAR_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_AMP_CTRL2_SAR_AMP_WAIT3(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL2.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg)&^(0xffff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_AMP_CTRL2_SAR_AMP_WAIT3() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL2.Reg) & 0xffff0000) >> 16 +} + +// SENS.SAR_AMP_CTRL3: no public +func (o *SENS_Type) SetSAR_AMP_CTRL3_SAR1_DAC_XPD_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf)|value) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_SAR1_DAC_XPD_FSM() uint32 { + return volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_XPD_SAR_AMP_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf0)|value<<4) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_XPD_SAR_AMP_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf0) >> 4 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_AMP_RST_FB_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf00)|value<<8) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_AMP_RST_FB_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf00) >> 8 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_AMP_SHORT_REF_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf000)|value<<12) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_AMP_SHORT_REF_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf000) >> 12 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_AMP_SHORT_REF_GND_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf0000)|value<<16) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_AMP_SHORT_REF_GND_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf0000) >> 16 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_XPD_SAR_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf00000)|value<<20) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_XPD_SAR_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf00000) >> 20 +} +func (o *SENS_Type) SetSAR_AMP_CTRL3_RSTB_FSM(value uint32) { + volatile.StoreUint32(&o.SAR_AMP_CTRL3.Reg, volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg)&^(0xf000000)|value<<24) +} +func (o *SENS_Type) GetSAR_AMP_CTRL3_RSTB_FSM() uint32 { + return (volatile.LoadUint32(&o.SAR_AMP_CTRL3.Reg) & 0xf000000) >> 24 +} + +// SENS.SAR_READER2_CTRL: configure saradc2 reader +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR_SAR2_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR_SAR2_CLK_DIV() uint32 { + return volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR_SAR2_WAIT_ARB_CYCLE(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x30000)|value<<16) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR_SAR2_WAIT_ARB_CYCLE() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x30000) >> 16 +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR_SAR2_CLK_GATED(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR_SAR2_CLK_GATED() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR_SAR2_SAMPLE_NUM(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x7f80000)|value<<19) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR_SAR2_SAMPLE_NUM() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x7f80000) >> 19 +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR_SAR2_DATA_INV(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR_SAR2_DATA_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *SENS_Type) SetSAR_READER2_CTRL_SAR_SAR2_INT_EN(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_CTRL.Reg, volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_READER2_CTRL_SAR_SAR2_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_READER2_CTRL.Reg) & 0x40000000) >> 30 +} + +// SENS.SAR_READER2_STATUS: get saradc1 reader controller status +func (o *SENS_Type) SetSAR_READER2_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR_READER2_STATUS.Reg, value) +} +func (o *SENS_Type) GetSAR_READER2_STATUS() uint32 { + return volatile.LoadUint32(&o.SAR_READER2_STATUS.Reg) +} + +// SENS.SAR_MEAS2_CTRL1: configure saradc2 controller +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR_SAR2_CNTL_STATE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0x7)|value) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR_SAR2_CNTL_STATE() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0x7 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR_SAR2_PWDET_CAL_EN(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR_SAR2_PWDET_CAL_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR_SAR2_PKDET_CAL_EN(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR_SAR2_PKDET_CAL_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR_SAR2_EN_TEST(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR_SAR2_EN_TEST() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR_SAR2_RSTB_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0xc0)|value<<6) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR_SAR2_RSTB_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0xc0) >> 6 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR_SAR2_STANDBY_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0xff00)|value<<8) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR_SAR2_STANDBY_WAIT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0xff00) >> 8 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR_SAR2_RSTB_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0xff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR_SAR2_RSTB_WAIT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0xff0000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL1_SAR_SAR2_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg)&^(0xff000000)|value<<24) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL1_SAR_SAR2_XPD_WAIT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL1.Reg) & 0xff000000) >> 24 +} + +// SENS.SAR_MEAS2_CTRL2: configure saradc2 controller +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_MEAS2_DATA_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0xffff)|value) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_MEAS2_DATA_SAR() uint32 { + return volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0xffff +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_MEAS2_DONE_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x10000)|value<<16) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_MEAS2_DONE_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x10000) >> 16 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_MEAS2_START_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x20000)|value<<17) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_MEAS2_START_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x20000) >> 17 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_MEAS2_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_MEAS2_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_SAR2_EN_PAD(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x7ff80000)|value<<19) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_SAR2_EN_PAD() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x7ff80000) >> 19 +} +func (o *SENS_Type) SetSAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_CTRL2.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_MEAS2_MUX: configure saradc2 controller +func (o *SENS_Type) SetSAR_MEAS2_MUX_SAR2_PWDET_CCT(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_MUX.Reg, volatile.LoadUint32(&o.SAR_MEAS2_MUX.Reg)&^(0x70000000)|value<<28) +} +func (o *SENS_Type) GetSAR_MEAS2_MUX_SAR2_PWDET_CCT() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_MUX.Reg) & 0x70000000) >> 28 +} +func (o *SENS_Type) SetSAR_MEAS2_MUX_SAR2_RTC_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_MEAS2_MUX.Reg, volatile.LoadUint32(&o.SAR_MEAS2_MUX.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_MEAS2_MUX_SAR2_RTC_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_MEAS2_MUX.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_ATTEN2: configure saradc2 controller +func (o *SENS_Type) SetSAR_ATTEN2(value uint32) { + volatile.StoreUint32(&o.SAR_ATTEN2.Reg, value) +} +func (o *SENS_Type) GetSAR_ATTEN2() uint32 { + return volatile.LoadUint32(&o.SAR_ATTEN2.Reg) +} + +// SENS.SAR_POWER_XPD_SAR: configure power of saradc +func (o *SENS_Type) SetSAR_POWER_XPD_SAR_FORCE_XPD_SAR(value uint32) { + volatile.StoreUint32(&o.SAR_POWER_XPD_SAR.Reg, volatile.LoadUint32(&o.SAR_POWER_XPD_SAR.Reg)&^(0x60000000)|value<<29) +} +func (o *SENS_Type) GetSAR_POWER_XPD_SAR_FORCE_XPD_SAR() uint32 { + return (volatile.LoadUint32(&o.SAR_POWER_XPD_SAR.Reg) & 0x60000000) >> 29 +} +func (o *SENS_Type) SetSAR_POWER_XPD_SAR_SARCLK_EN(value uint32) { + volatile.StoreUint32(&o.SAR_POWER_XPD_SAR.Reg, volatile.LoadUint32(&o.SAR_POWER_XPD_SAR.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_POWER_XPD_SAR_SARCLK_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_POWER_XPD_SAR.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_SLAVE_ADDR1: configure i2c slave address +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR1(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR1() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR0(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR0() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3ff800) >> 11 +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_SAR_SARADC_MEAS_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3fc00000)|value<<22) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_SAR_SARADC_MEAS_STATUS() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3fc00000) >> 22 +} + +// SENS.SAR_SLAVE_ADDR2: configure i2c slave address +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR3(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR3() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR2(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR2() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_SLAVE_ADDR3: configure i2c slave address +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR5(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR5() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR4(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR4() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_SLAVE_ADDR4: configure i2c slave address +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR7(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR7() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR6(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR6() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_TSENS_CTRL: configure tsens controller +func (o *SENS_Type) SetSAR_TSENS_CTRL_SAR_TSENS_OUT(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_SAR_TSENS_OUT() uint32 { + return volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_SAR_TSENS_READY(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_SAR_TSENS_READY() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_SAR_TSENS_INT_EN(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x1000)|value<<12) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_SAR_TSENS_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x1000) >> 12 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_SAR_TSENS_IN_INV(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_SAR_TSENS_IN_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x2000) >> 13 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_SAR_TSENS_CLK_DIV(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_SAR_TSENS_CLK_DIV() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_SAR_TSENS_POWER_UP(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_SAR_TSENS_POWER_UP() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x400000) >> 22 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_SAR_TSENS_POWER_UP_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_SAR_TSENS_POWER_UP_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL_SAR_TSENS_DUMP_OUT(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL_SAR_TSENS_DUMP_OUT() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL.Reg) & 0x1000000) >> 24 +} + +// SENS.SAR_TSENS_CTRL2: configure tsens controller +func (o *SENS_Type) SetSAR_TSENS_CTRL2_SAR_TSENS_XPD_WAIT(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg)&^(0xfff)|value) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL2_SAR_TSENS_XPD_WAIT() uint32 { + return volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg) & 0xfff +} +func (o *SENS_Type) SetSAR_TSENS_CTRL2_SAR_TSENS_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg)&^(0x3000)|value<<12) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL2_SAR_TSENS_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg) & 0x3000) >> 12 +} +func (o *SENS_Type) SetSAR_TSENS_CTRL2_SAR_TSENS_CLK_INV(value uint32) { + volatile.StoreUint32(&o.SAR_TSENS_CTRL2.Reg, volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *SENS_Type) GetSAR_TSENS_CTRL2_SAR_TSENS_CLK_INV() uint32 { + return (volatile.LoadUint32(&o.SAR_TSENS_CTRL2.Reg) & 0x4000) >> 14 +} + +// SENS.SAR_I2C_CTRL: configure rtc i2c controller by sw +func (o *SENS_Type) SetSAR_I2C_CTRL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0xfffffff)|value) +} +func (o *SENS_Type) GetSAR_I2C_CTRL() uint32 { + return volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0xfffffff +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x20000000) >> 29 +} + +// SENS.SAR_TOUCH_CONF: configure touch controller +func (o *SENS_Type) SetSAR_TOUCH_CONF_SAR_TOUCH_OUTEN(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x7fff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_SAR_TOUCH_OUTEN() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x7fff +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_SAR_TOUCH_STATUS_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_SAR_TOUCH_STATUS_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x8000) >> 15 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_SAR_TOUCH_DATA_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x30000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_SAR_TOUCH_DATA_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x30000) >> 16 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_SAR_TOUCH_DENOISE_END(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_SAR_TOUCH_DENOISE_END() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x40000) >> 18 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_SAR_TOUCH_UNIT_END(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_SAR_TOUCH_UNIT_END() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0x80000) >> 19 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD2(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0xf00000)|value<<20) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD2() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0xf00000) >> 20 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD1(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0xf000000)|value<<24) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD1() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0xf000000) >> 24 +} +func (o *SENS_Type) SetSAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD0(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CONF.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg)&^(0xf0000000)|value<<28) +} +func (o *SENS_Type) GetSAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD0() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CONF.Reg) & 0xf0000000) >> 28 +} + +// SENS.SAR_TOUCH_DENOISE: configure touch controller +func (o *SENS_Type) SetSAR_TOUCH_DENOISE_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_DENOISE.Reg, volatile.LoadUint32(&o.SAR_TOUCH_DENOISE.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_DENOISE_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_DENOISE.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES1: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES1_SAR_TOUCH_OUT_TH1(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES1.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES1_SAR_TOUCH_OUT_TH1() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES1.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES2: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES2_SAR_TOUCH_OUT_TH2(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES2.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES2_SAR_TOUCH_OUT_TH2() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES2.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES3: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES3_SAR_TOUCH_OUT_TH3(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES3.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES3_SAR_TOUCH_OUT_TH3() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES3.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES4: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES4_SAR_TOUCH_OUT_TH4(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES4.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES4_SAR_TOUCH_OUT_TH4() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES4.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES5: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES5_SAR_TOUCH_OUT_TH5(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES5.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES5_SAR_TOUCH_OUT_TH5() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES5.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES6: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES6_SAR_TOUCH_OUT_TH6(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES6.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES6.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES6_SAR_TOUCH_OUT_TH6() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES6.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES7: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES7_SAR_TOUCH_OUT_TH7(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES7.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES7.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES7_SAR_TOUCH_OUT_TH7() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES7.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES8: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES8_SAR_TOUCH_OUT_TH8(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES8.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES8.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES8_SAR_TOUCH_OUT_TH8() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES8.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES9: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES9_SAR_TOUCH_OUT_TH9(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES9.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES9.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES9_SAR_TOUCH_OUT_TH9() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES9.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES10: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES10_SAR_TOUCH_OUT_TH10(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES10.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES10.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES10_SAR_TOUCH_OUT_TH10() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES10.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES11: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES11_SAR_TOUCH_OUT_TH11(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES11.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES11.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES11_SAR_TOUCH_OUT_TH11() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES11.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES12: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES12_SAR_TOUCH_OUT_TH12(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES12.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES12.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES12_SAR_TOUCH_OUT_TH12() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES12.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES13: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES13_SAR_TOUCH_OUT_TH13(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES13.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES13.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES13_SAR_TOUCH_OUT_TH13() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES13.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_THRES14: configure touch thres of touch pad +func (o *SENS_Type) SetSAR_TOUCH_THRES14_SAR_TOUCH_OUT_TH14(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_THRES14.Reg, volatile.LoadUint32(&o.SAR_TOUCH_THRES14.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_THRES14_SAR_TOUCH_OUT_TH14() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_THRES14.Reg) & 0x3fffff +} + +// SENS.SAR_TOUCH_CHN_ST: Get touch channel status +func (o *SENS_Type) SetSAR_TOUCH_CHN_ST_SAR_TOUCH_PAD_ACTIVE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CHN_ST.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg)&^(0x7fff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_CHN_ST_SAR_TOUCH_PAD_ACTIVE() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg) & 0x7fff +} +func (o *SENS_Type) SetSAR_TOUCH_CHN_ST_SAR_TOUCH_CHANNEL_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CHN_ST.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg)&^(0x3fff8000)|value<<15) +} +func (o *SENS_Type) GetSAR_TOUCH_CHN_ST_SAR_TOUCH_CHANNEL_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg) & 0x3fff8000) >> 15 +} +func (o *SENS_Type) SetSAR_TOUCH_CHN_ST_SAR_TOUCH_MEAS_DONE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_CHN_ST.Reg, volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_TOUCH_CHN_ST_SAR_TOUCH_MEAS_DONE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_CHN_ST.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_TOUCH_STATUS0: get touch scan status +func (o *SENS_Type) SetSAR_TOUCH_STATUS0_SAR_TOUCH_SCAN_CURR(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS0.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS0.Reg)&^(0x3c00000)|value<<22) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS0_SAR_TOUCH_SCAN_CURR() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS0.Reg) & 0x3c00000) >> 22 +} + +// SENS.SAR_TOUCH_STATUS1: touch channel status of touch pad 1 +func (o *SENS_Type) SetSAR_TOUCH_STATUS1_SAR_TOUCH_PAD1_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS1.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS1_SAR_TOUCH_PAD1_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS1.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS1_SAR_TOUCH_PAD1_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS1.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS1.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS1_SAR_TOUCH_PAD1_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS1.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS2: touch channel status of touch pad 2 +func (o *SENS_Type) SetSAR_TOUCH_STATUS2_SAR_TOUCH_PAD2_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS2.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS2_SAR_TOUCH_PAD2_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS2.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS2_SAR_TOUCH_PAD2_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS2.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS2.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS2_SAR_TOUCH_PAD2_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS2.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS3: touch channel status of touch pad 3 +func (o *SENS_Type) SetSAR_TOUCH_STATUS3_SAR_TOUCH_PAD3_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS3.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS3_SAR_TOUCH_PAD3_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS3.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS3_SAR_TOUCH_PAD3_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS3.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS3.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS3_SAR_TOUCH_PAD3_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS3.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS4: touch channel status of touch pad 4 +func (o *SENS_Type) SetSAR_TOUCH_STATUS4_SAR_TOUCH_PAD4_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS4.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS4_SAR_TOUCH_PAD4_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS4.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS4_SAR_TOUCH_PAD4_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS4.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS4.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS4_SAR_TOUCH_PAD4_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS4.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS5: touch channel status of touch pad 5 +func (o *SENS_Type) SetSAR_TOUCH_STATUS5_SAR_TOUCH_PAD5_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS5.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS5_SAR_TOUCH_PAD5_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS5.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS5_SAR_TOUCH_PAD5_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS5.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS5.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS5_SAR_TOUCH_PAD5_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS5.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS6: touch channel status of touch pad 6 +func (o *SENS_Type) SetSAR_TOUCH_STATUS6_SAR_TOUCH_PAD6_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS6.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS6.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS6_SAR_TOUCH_PAD6_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS6.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS6_SAR_TOUCH_PAD6_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS6.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS6.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS6_SAR_TOUCH_PAD6_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS6.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS7: touch channel status of touch pad 7 +func (o *SENS_Type) SetSAR_TOUCH_STATUS7_SAR_TOUCH_PAD7_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS7.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS7.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS7_SAR_TOUCH_PAD7_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS7.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS7_SAR_TOUCH_PAD7_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS7.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS7.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS7_SAR_TOUCH_PAD7_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS7.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS8: touch channel status of touch pad 8 +func (o *SENS_Type) SetSAR_TOUCH_STATUS8_SAR_TOUCH_PAD8_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS8.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS8.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS8_SAR_TOUCH_PAD8_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS8.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS8_SAR_TOUCH_PAD8_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS8.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS8.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS8_SAR_TOUCH_PAD8_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS8.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS9: touch channel status of touch pad 9 +func (o *SENS_Type) SetSAR_TOUCH_STATUS9_SAR_TOUCH_PAD9_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS9.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS9.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS9_SAR_TOUCH_PAD9_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS9.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS9_SAR_TOUCH_PAD9_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS9.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS9.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS9_SAR_TOUCH_PAD9_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS9.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS10: touch channel status of touch pad 10 +func (o *SENS_Type) SetSAR_TOUCH_STATUS10_SAR_TOUCH_PAD10_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS10.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS10.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS10_SAR_TOUCH_PAD10_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS10.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS10_SAR_TOUCH_PAD10_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS10.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS10.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS10_SAR_TOUCH_PAD10_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS10.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS11: touch channel status of touch pad 11 +func (o *SENS_Type) SetSAR_TOUCH_STATUS11_SAR_TOUCH_PAD11_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS11.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS11.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS11_SAR_TOUCH_PAD11_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS11.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS11_SAR_TOUCH_PAD11_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS11.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS11.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS11_SAR_TOUCH_PAD11_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS11.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS12: touch channel status of touch pad 12 +func (o *SENS_Type) SetSAR_TOUCH_STATUS12_SAR_TOUCH_PAD12_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS12.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS12.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS12_SAR_TOUCH_PAD12_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS12.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS12_SAR_TOUCH_PAD12_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS12.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS12.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS12_SAR_TOUCH_PAD12_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS12.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS13: touch channel status of touch pad 13 +func (o *SENS_Type) SetSAR_TOUCH_STATUS13_SAR_TOUCH_PAD13_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS13.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS13.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS13_SAR_TOUCH_PAD13_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS13.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS13_SAR_TOUCH_PAD13_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS13.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS13.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS13_SAR_TOUCH_PAD13_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS13.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS14: touch channel status of touch pad 14 +func (o *SENS_Type) SetSAR_TOUCH_STATUS14_SAR_TOUCH_PAD14_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS14.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS14.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS14_SAR_TOUCH_PAD14_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS14.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS14_SAR_TOUCH_PAD14_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS14.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS14.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS14_SAR_TOUCH_PAD14_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS14.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS15: touch channel status of sleep pad +func (o *SENS_Type) SetSAR_TOUCH_STATUS15_SAR_TOUCH_SLP_DATA(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS15.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS15.Reg)&^(0x3fffff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS15_SAR_TOUCH_SLP_DATA() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS15.Reg) & 0x3fffff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS15_SAR_TOUCH_SLP_DEBOUNCE(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS15.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS15.Reg)&^(0xe0000000)|value<<29) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS15_SAR_TOUCH_SLP_DEBOUNCE() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS15.Reg) & 0xe0000000) >> 29 +} + +// SENS.SAR_TOUCH_STATUS16: touch channel status of approach mode +func (o *SENS_Type) SetSAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD2_CNT(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS16.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg)&^(0xff)|value) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD2_CNT() uint32 { + return volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg) & 0xff +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD1_CNT(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS16.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg)&^(0xff00)|value<<8) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD1_CNT() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg) & 0xff00) >> 8 +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD0_CNT(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS16.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg)&^(0xff0000)|value<<16) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD0_CNT() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg) & 0xff0000) >> 16 +} +func (o *SENS_Type) SetSAR_TOUCH_STATUS16_SAR_TOUCH_SLP_APPROACH_CNT(value uint32) { + volatile.StoreUint32(&o.SAR_TOUCH_STATUS16.Reg, volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg)&^(0xff000000)|value<<24) +} +func (o *SENS_Type) GetSAR_TOUCH_STATUS16_SAR_TOUCH_SLP_APPROACH_CNT() uint32 { + return (volatile.LoadUint32(&o.SAR_TOUCH_STATUS16.Reg) & 0xff000000) >> 24 +} + +// SENS.SAR_COCPU_STATE: get cocpu status +func (o *SENS_Type) SetSAR_COCPU_STATE_SAR_COCPU_DBG_TRIGGER(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x2000000)|value<<25) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_SAR_COCPU_DBG_TRIGGER() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x2000000) >> 25 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_SAR_COCPU_CLK_EN_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x4000000)|value<<26) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_SAR_COCPU_CLK_EN_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x4000000) >> 26 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_SAR_COCPU_RESET_N(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x8000000)|value<<27) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_SAR_COCPU_RESET_N() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x8000000) >> 27 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_SAR_COCPU_EOI(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_SAR_COCPU_EOI() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_SAR_COCPU_TRAP(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_SAR_COCPU_TRAP() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x20000000) >> 29 +} +func (o *SENS_Type) SetSAR_COCPU_STATE_SAR_COCPU_EBREAK(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_STATE.Reg, volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_COCPU_STATE_SAR_COCPU_EBREAK() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_STATE.Reg) & 0x40000000) >> 30 +} + +// SENS.SAR_COCPU_INT_RAW: the interrupt raw of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x800) >> 11 +} + +// SENS.SAR_COCPU_INT_ENA: the interrupt enable of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x800) >> 11 +} + +// SENS.SAR_COCPU_INT_ST: the interrupt state of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x800) >> 11 +} + +// SENS.SAR_COCPU_INT_CLR: the interrupt clear of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x800) >> 11 +} + +// SENS.SAR_COCPU_DEBUG: Ulp-riscv debug signal +func (o *SENS_Type) SetSAR_COCPU_DEBUG_SAR_COCPU_PC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0x1fff)|value) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_SAR_COCPU_PC() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0x1fff +} +func (o *SENS_Type) SetSAR_COCPU_DEBUG_SAR_COCPU_MEM_VLD(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0x2000)|value<<13) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_SAR_COCPU_MEM_VLD() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0x2000) >> 13 +} +func (o *SENS_Type) SetSAR_COCPU_DEBUG_SAR_COCPU_MEM_RDY(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0x4000)|value<<14) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_SAR_COCPU_MEM_RDY() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0x4000) >> 14 +} +func (o *SENS_Type) SetSAR_COCPU_DEBUG_SAR_COCPU_MEM_WEN(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0x78000)|value<<15) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_SAR_COCPU_MEM_WEN() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0x78000) >> 15 +} +func (o *SENS_Type) SetSAR_COCPU_DEBUG_SAR_COCPU_MEM_ADDR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_DEBUG.Reg, volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg)&^(0xfff80000)|value<<19) +} +func (o *SENS_Type) GetSAR_COCPU_DEBUG_SAR_COCPU_MEM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_DEBUG.Reg) & 0xfff80000) >> 19 +} + +// SENS.SAR_HALL_CTRL: no public +func (o *SENS_Type) SetSAR_HALL_CTRL_XPD_HALL(value uint32) { + volatile.StoreUint32(&o.SAR_HALL_CTRL.Reg, volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_HALL_CTRL_XPD_HALL() uint32 { + return (volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_HALL_CTRL_XPD_HALL_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_HALL_CTRL.Reg, volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_HALL_CTRL_XPD_HALL_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *SENS_Type) SetSAR_HALL_CTRL_HALL_PHASE(value uint32) { + volatile.StoreUint32(&o.SAR_HALL_CTRL.Reg, volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_HALL_CTRL_HALL_PHASE() uint32 { + return (volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *SENS_Type) SetSAR_HALL_CTRL_HALL_PHASE_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_HALL_CTRL.Reg, volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_HALL_CTRL_HALL_PHASE_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_HALL_CTRL.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_NOUSE: no public +func (o *SENS_Type) SetSAR_NOUSE(value uint32) { + volatile.StoreUint32(&o.SAR_NOUSE.Reg, value) +} +func (o *SENS_Type) GetSAR_NOUSE() uint32 { + return volatile.LoadUint32(&o.SAR_NOUSE.Reg) +} + +// SENS.SAR_PERI_CLK_GATE_CONF: the peri clock gate of rtc peri +func (o *SENS_Type) SetSAR_PERI_CLK_GATE_CONF_RTC_I2C_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg, volatile.LoadUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SENS_Type) GetSAR_PERI_CLK_GATE_CONF_RTC_I2C_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SENS_Type) SetSAR_PERI_CLK_GATE_CONF_TSENS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg, volatile.LoadUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_PERI_CLK_GATE_CONF_TSENS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg) & 0x20000000) >> 29 +} +func (o *SENS_Type) SetSAR_PERI_CLK_GATE_CONF_SARADC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg, volatile.LoadUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_PERI_CLK_GATE_CONF_SARADC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SENS_Type) SetSAR_PERI_CLK_GATE_CONF_IOMUX_CLK_EN(value uint32) { + volatile.StoreUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg, volatile.LoadUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SENS_Type) GetSAR_PERI_CLK_GATE_CONF_IOMUX_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.SAR_PERI_CLK_GATE_CONF.Reg) & 0x80000000) >> 31 +} + +// SENS.SAR_PERI_RESET_CONF: the peri reset of rtc peri +func (o *SENS_Type) SetSAR_PERI_RESET_CONF_SAR_COCPU_RESET(value uint32) { + volatile.StoreUint32(&o.SAR_PERI_RESET_CONF.Reg, volatile.LoadUint32(&o.SAR_PERI_RESET_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SENS_Type) GetSAR_PERI_RESET_CONF_SAR_COCPU_RESET() uint32 { + return (volatile.LoadUint32(&o.SAR_PERI_RESET_CONF.Reg) & 0x2000000) >> 25 +} +func (o *SENS_Type) SetSAR_PERI_RESET_CONF_SAR_RTC_I2C_RESET(value uint32) { + volatile.StoreUint32(&o.SAR_PERI_RESET_CONF.Reg, volatile.LoadUint32(&o.SAR_PERI_RESET_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SENS_Type) GetSAR_PERI_RESET_CONF_SAR_RTC_I2C_RESET() uint32 { + return (volatile.LoadUint32(&o.SAR_PERI_RESET_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SENS_Type) SetSAR_PERI_RESET_CONF_SAR_TSENS_RESET(value uint32) { + volatile.StoreUint32(&o.SAR_PERI_RESET_CONF.Reg, volatile.LoadUint32(&o.SAR_PERI_RESET_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_PERI_RESET_CONF_SAR_TSENS_RESET() uint32 { + return (volatile.LoadUint32(&o.SAR_PERI_RESET_CONF.Reg) & 0x20000000) >> 29 +} +func (o *SENS_Type) SetSAR_PERI_RESET_CONF_SAR_SARADC_RESET(value uint32) { + volatile.StoreUint32(&o.SAR_PERI_RESET_CONF.Reg, volatile.LoadUint32(&o.SAR_PERI_RESET_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SENS_Type) GetSAR_PERI_RESET_CONF_SAR_SARADC_RESET() uint32 { + return (volatile.LoadUint32(&o.SAR_PERI_RESET_CONF.Reg) & 0x40000000) >> 30 +} + +// SENS.SAR_COCPU_INT_ENA_W1TS: the interrupt enable of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC1_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC1_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC2_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC2_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TSENS_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TSENS_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_START_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_START_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SW_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SW_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SWD_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SWD_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TS.Reg) & 0x800) >> 11 +} + +// SENS.SAR_COCPU_INT_ENA_W1TC: the interrupt enable clear of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC1_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC1_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC2_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC2_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TSENS_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TSENS_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_START_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_START_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SW_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SW_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SWD_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SWD_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA_W1TC.Reg) & 0x800) >> 11 +} + +// SENS.SAR_DEBUG_CONF: rtc peri debug configure +func (o *SENS_Type) SetSAR_DEBUG_CONF_SAR_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_DEBUG_CONF.Reg, volatile.LoadUint32(&o.SAR_DEBUG_CONF.Reg)&^(0x1f)|value) +} +func (o *SENS_Type) GetSAR_DEBUG_CONF_SAR_DEBUG_BIT_SEL() uint32 { + return volatile.LoadUint32(&o.SAR_DEBUG_CONF.Reg) & 0x1f +} + +// SENS.SAR_SARDATE: version +func (o *SENS_Type) SetSAR_SARDATE_SAR_DATE(value uint32) { + volatile.StoreUint32(&o.SAR_SARDATE.Reg, volatile.LoadUint32(&o.SAR_SARDATE.Reg)&^(0xfffffff)|value) +} +func (o *SENS_Type) GetSAR_SARDATE_SAR_DATE() uint32 { + return volatile.LoadUint32(&o.SAR_SARDATE.Reg) & 0xfffffff +} + +// SENSITIVE Peripheral +type SENSITIVE_Type struct { + CACHE_DATAARRAY_CONNECT_0 volatile.Register32 // 0x0 + CACHE_DATAARRAY_CONNECT_1 volatile.Register32 // 0x4 + APB_PERIPHERAL_ACCESS_0 volatile.Register32 // 0x8 + APB_PERIPHERAL_ACCESS_1 volatile.Register32 // 0xC + INTERNAL_SRAM_USAGE_0 volatile.Register32 // 0x10 + INTERNAL_SRAM_USAGE_1 volatile.Register32 // 0x14 + INTERNAL_SRAM_USAGE_2 volatile.Register32 // 0x18 + INTERNAL_SRAM_USAGE_3 volatile.Register32 // 0x1C + INTERNAL_SRAM_USAGE_4 volatile.Register32 // 0x20 + RETENTION_DISABLE volatile.Register32 // 0x24 + CACHE_TAG_ACCESS_0 volatile.Register32 // 0x28 + CACHE_TAG_ACCESS_1 volatile.Register32 // 0x2C + CACHE_MMU_ACCESS_0 volatile.Register32 // 0x30 + CACHE_MMU_ACCESS_1 volatile.Register32 // 0x34 + DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 volatile.Register32 // 0x38 + DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 volatile.Register32 // 0x3C + DMA_APBPERI_SPI3_PMS_CONSTRAIN_0 volatile.Register32 // 0x40 + DMA_APBPERI_SPI3_PMS_CONSTRAIN_1 volatile.Register32 // 0x44 + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0 volatile.Register32 // 0x48 + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1 volatile.Register32 // 0x4C + DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 volatile.Register32 // 0x50 + DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 volatile.Register32 // 0x54 + DMA_APBPERI_I2S1_PMS_CONSTRAIN_0 volatile.Register32 // 0x58 + DMA_APBPERI_I2S1_PMS_CONSTRAIN_1 volatile.Register32 // 0x5C + DMA_APBPERI_MAC_PMS_CONSTRAIN_0 volatile.Register32 // 0x60 + DMA_APBPERI_MAC_PMS_CONSTRAIN_1 volatile.Register32 // 0x64 + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 volatile.Register32 // 0x68 + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 volatile.Register32 // 0x6C + DMA_APBPERI_AES_PMS_CONSTRAIN_0 volatile.Register32 // 0x70 + DMA_APBPERI_AES_PMS_CONSTRAIN_1 volatile.Register32 // 0x74 + DMA_APBPERI_SHA_PMS_CONSTRAIN_0 volatile.Register32 // 0x78 + DMA_APBPERI_SHA_PMS_CONSTRAIN_1 volatile.Register32 // 0x7C + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 volatile.Register32 // 0x80 + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 volatile.Register32 // 0x84 + DMA_APBPERI_RMT_PMS_CONSTRAIN_0 volatile.Register32 // 0x88 + DMA_APBPERI_RMT_PMS_CONSTRAIN_1 volatile.Register32 // 0x8C + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0 volatile.Register32 // 0x90 + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1 volatile.Register32 // 0x94 + DMA_APBPERI_USB_PMS_CONSTRAIN_0 volatile.Register32 // 0x98 + DMA_APBPERI_USB_PMS_CONSTRAIN_1 volatile.Register32 // 0x9C + DMA_APBPERI_LC_PMS_CONSTRAIN_0 volatile.Register32 // 0xA0 + DMA_APBPERI_LC_PMS_CONSTRAIN_1 volatile.Register32 // 0xA4 + DMA_APBPERI_SDIO_PMS_CONSTRAIN_0 volatile.Register32 // 0xA8 + DMA_APBPERI_SDIO_PMS_CONSTRAIN_1 volatile.Register32 // 0xAC + DMA_APBPERI_PMS_MONITOR_0 volatile.Register32 // 0xB0 + DMA_APBPERI_PMS_MONITOR_1 volatile.Register32 // 0xB4 + DMA_APBPERI_PMS_MONITOR_2 volatile.Register32 // 0xB8 + DMA_APBPERI_PMS_MONITOR_3 volatile.Register32 // 0xBC + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 volatile.Register32 // 0xC0 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 volatile.Register32 // 0xC4 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 volatile.Register32 // 0xC8 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 volatile.Register32 // 0xCC + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 volatile.Register32 // 0xD0 + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 volatile.Register32 // 0xD4 + CORE_X_IRAM0_PMS_CONSTRAIN_0 volatile.Register32 // 0xD8 + CORE_X_IRAM0_PMS_CONSTRAIN_1 volatile.Register32 // 0xDC + CORE_X_IRAM0_PMS_CONSTRAIN_2 volatile.Register32 // 0xE0 + CORE_0_IRAM0_PMS_MONITOR_0 volatile.Register32 // 0xE4 + CORE_0_IRAM0_PMS_MONITOR_1 volatile.Register32 // 0xE8 + CORE_0_IRAM0_PMS_MONITOR_2 volatile.Register32 // 0xEC + CORE_1_IRAM0_PMS_MONITOR_0 volatile.Register32 // 0xF0 + CORE_1_IRAM0_PMS_MONITOR_1 volatile.Register32 // 0xF4 + CORE_1_IRAM0_PMS_MONITOR_2 volatile.Register32 // 0xF8 + CORE_X_DRAM0_PMS_CONSTRAIN_0 volatile.Register32 // 0xFC + CORE_X_DRAM0_PMS_CONSTRAIN_1 volatile.Register32 // 0x100 + CORE_0_DRAM0_PMS_MONITOR_0 volatile.Register32 // 0x104 + CORE_0_DRAM0_PMS_MONITOR_1 volatile.Register32 // 0x108 + CORE_0_DRAM0_PMS_MONITOR_2 volatile.Register32 // 0x10C + CORE_0_DRAM0_PMS_MONITOR_3 volatile.Register32 // 0x110 + CORE_1_DRAM0_PMS_MONITOR_0 volatile.Register32 // 0x114 + CORE_1_DRAM0_PMS_MONITOR_1 volatile.Register32 // 0x118 + CORE_1_DRAM0_PMS_MONITOR_2 volatile.Register32 // 0x11C + CORE_1_DRAM0_PMS_MONITOR_3 volatile.Register32 // 0x120 + CORE_0_PIF_PMS_CONSTRAIN_0 volatile.Register32 // 0x124 + CORE_0_PIF_PMS_CONSTRAIN_1 volatile.Register32 // 0x128 + CORE_0_PIF_PMS_CONSTRAIN_2 volatile.Register32 // 0x12C + CORE_0_PIF_PMS_CONSTRAIN_3 volatile.Register32 // 0x130 + CORE_0_PIF_PMS_CONSTRAIN_4 volatile.Register32 // 0x134 + CORE_0_PIF_PMS_CONSTRAIN_5 volatile.Register32 // 0x138 + CORE_0_PIF_PMS_CONSTRAIN_6 volatile.Register32 // 0x13C + CORE_0_PIF_PMS_CONSTRAIN_7 volatile.Register32 // 0x140 + CORE_0_PIF_PMS_CONSTRAIN_8 volatile.Register32 // 0x144 + CORE_0_PIF_PMS_CONSTRAIN_9 volatile.Register32 // 0x148 + CORE_0_PIF_PMS_CONSTRAIN_10 volatile.Register32 // 0x14C + CORE_0_PIF_PMS_CONSTRAIN_11 volatile.Register32 // 0x150 + CORE_0_PIF_PMS_CONSTRAIN_12 volatile.Register32 // 0x154 + CORE_0_PIF_PMS_CONSTRAIN_13 volatile.Register32 // 0x158 + CORE_0_PIF_PMS_CONSTRAIN_14 volatile.Register32 // 0x15C + CORE_0_REGION_PMS_CONSTRAIN_0 volatile.Register32 // 0x160 + CORE_0_REGION_PMS_CONSTRAIN_1 volatile.Register32 // 0x164 + CORE_0_REGION_PMS_CONSTRAIN_2 volatile.Register32 // 0x168 + CORE_0_REGION_PMS_CONSTRAIN_3 volatile.Register32 // 0x16C + CORE_0_REGION_PMS_CONSTRAIN_4 volatile.Register32 // 0x170 + CORE_0_REGION_PMS_CONSTRAIN_5 volatile.Register32 // 0x174 + CORE_0_REGION_PMS_CONSTRAIN_6 volatile.Register32 // 0x178 + CORE_0_REGION_PMS_CONSTRAIN_7 volatile.Register32 // 0x17C + CORE_0_REGION_PMS_CONSTRAIN_8 volatile.Register32 // 0x180 + CORE_0_REGION_PMS_CONSTRAIN_9 volatile.Register32 // 0x184 + CORE_0_REGION_PMS_CONSTRAIN_10 volatile.Register32 // 0x188 + CORE_0_REGION_PMS_CONSTRAIN_11 volatile.Register32 // 0x18C + CORE_0_REGION_PMS_CONSTRAIN_12 volatile.Register32 // 0x190 + CORE_0_REGION_PMS_CONSTRAIN_13 volatile.Register32 // 0x194 + CORE_0_REGION_PMS_CONSTRAIN_14 volatile.Register32 // 0x198 + CORE_0_PIF_PMS_MONITOR_0 volatile.Register32 // 0x19C + CORE_0_PIF_PMS_MONITOR_1 volatile.Register32 // 0x1A0 + CORE_0_PIF_PMS_MONITOR_2 volatile.Register32 // 0x1A4 + CORE_0_PIF_PMS_MONITOR_3 volatile.Register32 // 0x1A8 + CORE_0_PIF_PMS_MONITOR_4 volatile.Register32 // 0x1AC + CORE_0_PIF_PMS_MONITOR_5 volatile.Register32 // 0x1B0 + CORE_0_PIF_PMS_MONITOR_6 volatile.Register32 // 0x1B4 + CORE_0_VECBASE_OVERRIDE_LOCK volatile.Register32 // 0x1B8 + CORE_0_VECBASE_OVERRIDE_0 volatile.Register32 // 0x1BC + CORE_0_VECBASE_OVERRIDE_1 volatile.Register32 // 0x1C0 + CORE_0_VECBASE_OVERRIDE_2 volatile.Register32 // 0x1C4 + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0 volatile.Register32 // 0x1C8 + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1 volatile.Register32 // 0x1CC + CORE_1_PIF_PMS_CONSTRAIN_0 volatile.Register32 // 0x1D0 + CORE_1_PIF_PMS_CONSTRAIN_1 volatile.Register32 // 0x1D4 + CORE_1_PIF_PMS_CONSTRAIN_2 volatile.Register32 // 0x1D8 + CORE_1_PIF_PMS_CONSTRAIN_3 volatile.Register32 // 0x1DC + CORE_1_PIF_PMS_CONSTRAIN_4 volatile.Register32 // 0x1E0 + CORE_1_PIF_PMS_CONSTRAIN_5 volatile.Register32 // 0x1E4 + CORE_1_PIF_PMS_CONSTRAIN_6 volatile.Register32 // 0x1E8 + CORE_1_PIF_PMS_CONSTRAIN_7 volatile.Register32 // 0x1EC + CORE_1_PIF_PMS_CONSTRAIN_8 volatile.Register32 // 0x1F0 + CORE_1_PIF_PMS_CONSTRAIN_9 volatile.Register32 // 0x1F4 + CORE_1_PIF_PMS_CONSTRAIN_10 volatile.Register32 // 0x1F8 + CORE_1_PIF_PMS_CONSTRAIN_11 volatile.Register32 // 0x1FC + CORE_1_PIF_PMS_CONSTRAIN_12 volatile.Register32 // 0x200 + CORE_1_PIF_PMS_CONSTRAIN_13 volatile.Register32 // 0x204 + CORE_1_PIF_PMS_CONSTRAIN_14 volatile.Register32 // 0x208 + CORE_1_REGION_PMS_CONSTRAIN_0 volatile.Register32 // 0x20C + CORE_1_REGION_PMS_CONSTRAIN_1 volatile.Register32 // 0x210 + CORE_1_REGION_PMS_CONSTRAIN_2 volatile.Register32 // 0x214 + CORE_1_REGION_PMS_CONSTRAIN_3 volatile.Register32 // 0x218 + CORE_1_REGION_PMS_CONSTRAIN_4 volatile.Register32 // 0x21C + CORE_1_REGION_PMS_CONSTRAIN_5 volatile.Register32 // 0x220 + CORE_1_REGION_PMS_CONSTRAIN_6 volatile.Register32 // 0x224 + CORE_1_REGION_PMS_CONSTRAIN_7 volatile.Register32 // 0x228 + CORE_1_REGION_PMS_CONSTRAIN_8 volatile.Register32 // 0x22C + CORE_1_REGION_PMS_CONSTRAIN_9 volatile.Register32 // 0x230 + CORE_1_REGION_PMS_CONSTRAIN_10 volatile.Register32 // 0x234 + CORE_1_REGION_PMS_CONSTRAIN_11 volatile.Register32 // 0x238 + CORE_1_REGION_PMS_CONSTRAIN_12 volatile.Register32 // 0x23C + CORE_1_REGION_PMS_CONSTRAIN_13 volatile.Register32 // 0x240 + CORE_1_REGION_PMS_CONSTRAIN_14 volatile.Register32 // 0x244 + CORE_1_PIF_PMS_MONITOR_0 volatile.Register32 // 0x248 + CORE_1_PIF_PMS_MONITOR_1 volatile.Register32 // 0x24C + CORE_1_PIF_PMS_MONITOR_2 volatile.Register32 // 0x250 + CORE_1_PIF_PMS_MONITOR_3 volatile.Register32 // 0x254 + CORE_1_PIF_PMS_MONITOR_4 volatile.Register32 // 0x258 + CORE_1_PIF_PMS_MONITOR_5 volatile.Register32 // 0x25C + CORE_1_PIF_PMS_MONITOR_6 volatile.Register32 // 0x260 + CORE_1_VECBASE_OVERRIDE_LOCK volatile.Register32 // 0x264 + CORE_1_VECBASE_OVERRIDE_0 volatile.Register32 // 0x268 + CORE_1_VECBASE_OVERRIDE_1 volatile.Register32 // 0x26C + CORE_1_VECBASE_OVERRIDE_2 volatile.Register32 // 0x270 + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0 volatile.Register32 // 0x274 + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1 volatile.Register32 // 0x278 + BACKUP_BUS_PMS_CONSTRAIN_0 volatile.Register32 // 0x27C + BACKUP_BUS_PMS_CONSTRAIN_1 volatile.Register32 // 0x280 + BACKUP_BUS_PMS_CONSTRAIN_2 volatile.Register32 // 0x284 + BACKUP_BUS_PMS_CONSTRAIN_3 volatile.Register32 // 0x288 + BACKUP_BUS_PMS_CONSTRAIN_4 volatile.Register32 // 0x28C + BACKUP_BUS_PMS_CONSTRAIN_5 volatile.Register32 // 0x290 + BACKUP_BUS_PMS_CONSTRAIN_6 volatile.Register32 // 0x294 + BACKUP_BUS_PMS_MONITOR_0 volatile.Register32 // 0x298 + BACKUP_BUS_PMS_MONITOR_1 volatile.Register32 // 0x29C + BACKUP_BUS_PMS_MONITOR_2 volatile.Register32 // 0x2A0 + BACKUP_BUS_PMS_MONITOR_3 volatile.Register32 // 0x2A4 + EDMA_BOUNDARY_LOCK volatile.Register32 // 0x2A8 + EDMA_BOUNDARY_0 volatile.Register32 // 0x2AC + EDMA_BOUNDARY_1 volatile.Register32 // 0x2B0 + EDMA_BOUNDARY_2 volatile.Register32 // 0x2B4 + EDMA_PMS_SPI2_LOCK volatile.Register32 // 0x2B8 + EDMA_PMS_SPI2 volatile.Register32 // 0x2BC + EDMA_PMS_SPI3_LOCK volatile.Register32 // 0x2C0 + EDMA_PMS_SPI3 volatile.Register32 // 0x2C4 + EDMA_PMS_UHCI0_LOCK volatile.Register32 // 0x2C8 + EDMA_PMS_UHCI0 volatile.Register32 // 0x2CC + EDMA_PMS_I2S0_LOCK volatile.Register32 // 0x2D0 + EDMA_PMS_I2S0 volatile.Register32 // 0x2D4 + EDMA_PMS_I2S1_LOCK volatile.Register32 // 0x2D8 + EDMA_PMS_I2S1 volatile.Register32 // 0x2DC + EDMA_PMS_LCD_CAM_LOCK volatile.Register32 // 0x2E0 + EDMA_PMS_LCD_CAM volatile.Register32 // 0x2E4 + EDMA_PMS_AES_LOCK volatile.Register32 // 0x2E8 + EDMA_PMS_AES volatile.Register32 // 0x2EC + EDMA_PMS_SHA_LOCK volatile.Register32 // 0x2F0 + EDMA_PMS_SHA volatile.Register32 // 0x2F4 + EDMA_PMS_ADC_DAC_LOCK volatile.Register32 // 0x2F8 + EDMA_PMS_ADC_DAC volatile.Register32 // 0x2FC + EDMA_PMS_RMT_LOCK volatile.Register32 // 0x300 + EDMA_PMS_RMT volatile.Register32 // 0x304 + CLOCK_GATE volatile.Register32 // 0x308 + RTC_PMS volatile.Register32 // 0x30C + _ [3308]byte + DATE volatile.Register32 // 0xFFC +} + +// SENSITIVE.CACHE_DATAARRAY_CONNECT_0: Cache data array configuration register 0. +func (o *SENSITIVE_Type) SetCACHE_DATAARRAY_CONNECT_0_CACHE_DATAARRAY_CONNECT_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_DATAARRAY_CONNECT_0.Reg, volatile.LoadUint32(&o.CACHE_DATAARRAY_CONNECT_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_DATAARRAY_CONNECT_0_CACHE_DATAARRAY_CONNECT_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_DATAARRAY_CONNECT_0.Reg) & 0x1 +} + +// SENSITIVE.CACHE_DATAARRAY_CONNECT_1: Cache data array configuration register 1. +func (o *SENSITIVE_Type) SetCACHE_DATAARRAY_CONNECT_1_CACHE_DATAARRAY_CONNECT_FLATTEN(value uint32) { + volatile.StoreUint32(&o.CACHE_DATAARRAY_CONNECT_1.Reg, volatile.LoadUint32(&o.CACHE_DATAARRAY_CONNECT_1.Reg)&^(0xff)|value) +} +func (o *SENSITIVE_Type) GetCACHE_DATAARRAY_CONNECT_1_CACHE_DATAARRAY_CONNECT_FLATTEN() uint32 { + return volatile.LoadUint32(&o.CACHE_DATAARRAY_CONNECT_1.Reg) & 0xff +} + +// SENSITIVE.APB_PERIPHERAL_ACCESS_0: APB peripheral configuration register 0. +func (o *SENSITIVE_Type) SetAPB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_ACCESS_0.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetAPB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_0.Reg) & 0x1 +} + +// SENSITIVE.APB_PERIPHERAL_ACCESS_1: APB peripheral configuration register 1. +func (o *SENSITIVE_Type) SetAPB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST(value uint32) { + volatile.StoreUint32(&o.APB_PERIPHERAL_ACCESS_1.Reg, volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetAPB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST() uint32 { + return volatile.LoadUint32(&o.APB_PERIPHERAL_ACCESS_1.Reg) & 0x1 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_0: Internal SRAM configuration register 0. +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_0.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_0.Reg) & 0x1 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_1: Internal SRAM configuration register 1. +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_ICACHE_USAGE(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_1.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_ICACHE_USAGE() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_DCACHE_USAGE(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_1.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_DCACHE_USAGE() uint32 { + return (volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_CPU_USAGE(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_1.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg)&^(0x7f0)|value<<4) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_CPU_USAGE() uint32 { + return (volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_1.Reg) & 0x7f0) >> 4 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_2: Internal SRAM configuration register 2. +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE0_TRACE_USAGE(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_2.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_2.Reg)&^(0x7f)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE0_TRACE_USAGE() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_2.Reg) & 0x7f +} +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE1_TRACE_USAGE(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_2.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_2.Reg)&^(0x3f80)|value<<7) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE1_TRACE_USAGE() uint32 { + return (volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_2.Reg) & 0x3f80) >> 7 +} +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE0_TRACE_ALLOC(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_2.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_2.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE0_TRACE_ALLOC() uint32 { + return (volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_2.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE1_TRACE_ALLOC(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_2.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_2.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE1_TRACE_ALLOC() uint32 { + return (volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_2.Reg) & 0x30000) >> 16 +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_3: Internal SRAM configuration register 3. +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_MAC_DUMP_USAGE(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_3.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg)&^(0xf)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_MAC_DUMP_USAGE() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_3.Reg) & 0xf +} + +// SENSITIVE.INTERNAL_SRAM_USAGE_4: Internal SRAM configuration register 4. +func (o *SENSITIVE_Type) SetINTERNAL_SRAM_USAGE_4_INTERNAL_SRAM_LOG_USAGE(value uint32) { + volatile.StoreUint32(&o.INTERNAL_SRAM_USAGE_4.Reg, volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_4.Reg)&^(0x7f)|value) +} +func (o *SENSITIVE_Type) GetINTERNAL_SRAM_USAGE_4_INTERNAL_SRAM_LOG_USAGE() uint32 { + return volatile.LoadUint32(&o.INTERNAL_SRAM_USAGE_4.Reg) & 0x7f +} + +// SENSITIVE.RETENTION_DISABLE: Retention configuration register. +func (o *SENSITIVE_Type) SetRETENTION_DISABLE(value uint32) { + volatile.StoreUint32(&o.RETENTION_DISABLE.Reg, volatile.LoadUint32(&o.RETENTION_DISABLE.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetRETENTION_DISABLE() uint32 { + return volatile.LoadUint32(&o.RETENTION_DISABLE.Reg) & 0x1 +} + +// SENSITIVE.CACHE_TAG_ACCESS_0: Cache tag configuration register 0. +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_0.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_ACCESS_0.Reg) & 0x1 +} + +// SENSITIVE.CACHE_TAG_ACCESS_1: Cache tag configuration register 1. +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS() uint32 { + return volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x4)|value<<2) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x4) >> 2 +} +func (o *SENSITIVE_Type) SetCACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_TAG_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg)&^(0x8)|value<<3) +} +func (o *SENSITIVE_Type) GetCACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_TAG_ACCESS_1.Reg) & 0x8) >> 3 +} + +// SENSITIVE.CACHE_MMU_ACCESS_0: Cache MMU configuration register 0. +func (o *SENSITIVE_Type) SetCACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_0.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_ACCESS_0.Reg) & 0x1 +} + +// SENSITIVE.CACHE_MMU_ACCESS_1: Cache MMU configuration register 1. +func (o *SENSITIVE_Type) SetCACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS() uint32 { + return volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS(value uint32) { + volatile.StoreUint32(&o.CACHE_MMU_ACCESS_1.Reg, volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS() uint32 { + return (volatile.LoadUint32(&o.CACHE_MMU_ACCESS_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.DMA_APBPERI_SPI2_PMS_CONSTRAIN_0: spi2 dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1: spi2 dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI2_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_SPI3_PMS_CONSTRAIN_0: spi3 dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI3_PMS_CONSTRAIN_0_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI3_PMS_CONSTRAIN_0_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1: spi3 dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SPI3_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0: uhci0 dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1: uhci0 dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_I2S0_PMS_CONSTRAIN_0: i2s0 dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1: i2s0 dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S0_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_I2S1_PMS_CONSTRAIN_0: i2s1 dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S1_PMS_CONSTRAIN_0_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S1_PMS_CONSTRAIN_0_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1: i2s1 dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_I2S1_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_MAC_PMS_CONSTRAIN_0: mac dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_MAC_PMS_CONSTRAIN_1: mac dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_MAC_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0: backup dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1: backup dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_AES_PMS_CONSTRAIN_0: aes dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_AES_PMS_CONSTRAIN_1: aes dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_AES_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_SHA_PMS_CONSTRAIN_0: sha dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_SHA_PMS_CONSTRAIN_1: sha dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SHA_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0: adc_dac dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1: adc_dac dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_RMT_PMS_CONSTRAIN_0: rmt dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_RMT_PMS_CONSTRAIN_0_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_RMT_PMS_CONSTRAIN_0_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_RMT_PMS_CONSTRAIN_1: rmt dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_RMT_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0: lcd_cam dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1: lcd_cam dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_USB_PMS_CONSTRAIN_0: usb dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_USB_PMS_CONSTRAIN_0_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_USB_PMS_CONSTRAIN_0_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_USB_PMS_CONSTRAIN_1: usb dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_USB_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_LC_PMS_CONSTRAIN_0: lc dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_LC_PMS_CONSTRAIN_1: lc dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_LC_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_SDIO_PMS_CONSTRAIN_0: sdio dma permission configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_SDIO_PMS_CONSTRAIN_0_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SDIO_PMS_CONSTRAIN_0_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1: sdio dma permission configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_SDIO_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} + +// SENSITIVE.DMA_APBPERI_PMS_MONITOR_0: dma permission monitor configuration register 0. +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.DMA_APBPERI_PMS_MONITOR_1: dma permission monitor configuration register 1. +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.DMA_APBPERI_PMS_MONITOR_2: dma permission monitor configuration register 2. +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg)&^(0x6)|value<<1) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg) & 0x6) >> 1 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg)&^(0x1fffff8)|value<<3) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_2.Reg) & 0x1fffff8) >> 3 +} + +// SENSITIVE.DMA_APBPERI_PMS_MONITOR_3: dma permission monitor configuration register 3. +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR() uint32 { + return volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetDMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN(value uint32) { + volatile.StoreUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg)&^(0x1fffe)|value<<1) +} +func (o *SENSITIVE_Type) GetDMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN() uint32 { + return (volatile.LoadUint32(&o.DMA_APBPERI_PMS_MONITOR_3.Reg) & 0x1fffe) >> 1 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0: sram split line configuration register 0 +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1: sram split line configuration register 1 +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2: sram split line configuration register 1 +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3: sram split line configuration register 1 +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4: sram split line configuration register 1 +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5: sram split line configuration register 1 +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg)&^(0x3fc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5.Reg) & 0x3fc000) >> 14 +} + +// SENSITIVE.CORE_X_IRAM0_PMS_CONSTRAIN_0: corex iram0 permission configuration register 0 +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_X_IRAM0_PMS_CONSTRAIN_1: corex iram0 permission configuration register 0 +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0xe00) >> 9 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x7000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x7000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x38000)|value<<15) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x38000) >> 15 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg)&^(0x1c0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_1.Reg) & 0x1c0000) >> 18 +} + +// SENSITIVE.CORE_X_IRAM0_PMS_CONSTRAIN_2: corex iram0 permission configuration register 1 +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0xe00) >> 9 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x7000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x7000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x38000)|value<<15) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x38000) >> 15 +} +func (o *SENSITIVE_Type) SetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS(value uint32) { + volatile.StoreUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg)&^(0x1c0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS() uint32 { + return (volatile.LoadUint32(&o.CORE_X_IRAM0_PMS_CONSTRAIN_2.Reg) & 0x1c0000) >> 18 +} + +// SENSITIVE.CORE_0_IRAM0_PMS_MONITOR_0: core0 iram0 permission monitor configuration register 0 +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_IRAM0_PMS_MONITOR_1: core0 iram0 permission monitor configuration register 1 +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_0_IRAM0_PMS_MONITOR_2: core0 iram0 permission monitor configuration register 2 +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x4)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x4) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x18)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x18) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR(value uint32) { + volatile.StoreUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg)&^(0x1fffffe0)|value<<5) +} +func (o *SENSITIVE_Type) GetCORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_IRAM0_PMS_MONITOR_2.Reg) & 0x1fffffe0) >> 5 +} + +// SENSITIVE.CORE_1_IRAM0_PMS_MONITOR_0: core1 iram0 permission monitor configuration register 0 +func (o *SENSITIVE_Type) SetCORE_1_IRAM0_PMS_MONITOR_0_CORE_1_IRAM0_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_IRAM0_PMS_MONITOR_0_CORE_1_IRAM0_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_1_IRAM0_PMS_MONITOR_1: core1 iram0 permission monitor configuration register 1 +func (o *SENSITIVE_Type) SetCORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_1_IRAM0_PMS_MONITOR_2: core1 iram0 permission monitor configuration register 2 +func (o *SENSITIVE_Type) SetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg)&^(0x4)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg) & 0x4) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg)&^(0x18)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg) & 0x18) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR(value uint32) { + volatile.StoreUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg)&^(0x1fffffe0)|value<<5) +} +func (o *SENSITIVE_Type) GetCORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_IRAM0_PMS_MONITOR_2.Reg) & 0x1fffffe0) >> 5 +} + +// SENSITIVE.CORE_X_DRAM0_PMS_CONSTRAIN_0: corex dram0 permission configuration register 0 +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_X_DRAM0_PMS_CONSTRAIN_1: corex dram0 permission configuration register 1 +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0() uint32 { + return volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS(value uint32) { + volatile.StoreUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS() uint32 { + return (volatile.LoadUint32(&o.CORE_X_DRAM0_PMS_CONSTRAIN_1.Reg) & 0xc000000) >> 26 +} + +// SENSITIVE.CORE_0_DRAM0_PMS_MONITOR_0: core0 dram0 permission monitor configuration register 0 +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_DRAM0_PMS_MONITOR_1: core0 dram0 permission monitor configuration register 1 +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_0_DRAM0_PMS_MONITOR_2: core0 dram0 permission monitor configuration register 2. +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg)&^(0x3fffff0)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_2.Reg) & 0x3fffff0) >> 4 +} + +// SENSITIVE.CORE_0_DRAM0_PMS_MONITOR_3: core0 dram0 permission monitor configuration register 3. +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR() uint32 { + return volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN(value uint32) { + volatile.StoreUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg)&^(0x1fffe)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_DRAM0_PMS_MONITOR_3.Reg) & 0x1fffe) >> 1 +} + +// SENSITIVE.CORE_1_DRAM0_PMS_MONITOR_0: core1 dram0 permission monitor configuration register 0 +func (o *SENSITIVE_Type) SetCORE_1_DRAM0_PMS_MONITOR_0_CORE_1_DRAM0_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_DRAM0_PMS_MONITOR_0_CORE_1_DRAM0_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_1_DRAM0_PMS_MONITOR_1: core1 dram0 permission monitor configuration register 1 +func (o *SENSITIVE_Type) SetCORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_1_DRAM0_PMS_MONITOR_2: core1 dram0 permission monitor configuration register 2. +func (o *SENSITIVE_Type) SetCORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg)&^(0x3fffff0)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_2.Reg) & 0x3fffff0) >> 4 +} + +// SENSITIVE.CORE_1_DRAM0_PMS_MONITOR_3: core1 dram0 permission monitor configuration register 3. +func (o *SENSITIVE_Type) SetCORE_1_DRAM0_PMS_MONITOR_3_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_3.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_DRAM0_PMS_MONITOR_3_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR() uint32 { + return volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_3.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_1_DRAM0_PMS_MONITOR_3_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN(value uint32) { + volatile.StoreUint32(&o.CORE_1_DRAM0_PMS_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_3.Reg)&^(0x1fffe)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_1_DRAM0_PMS_MONITOR_3_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN() uint32 { + return (volatile.LoadUint32(&o.CORE_1_DRAM0_PMS_MONITOR_3.Reg) & 0x1fffe) >> 1 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_0: Core0 access peripherals permission configuration register 0. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_1: Core0 access peripherals permission configuration register 1. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_1.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_2: Core0 access peripherals permission configuration register 2. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_2.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_3: Core0 access peripherals permission configuration register 3. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_3.Reg) & 0x30000000) >> 28 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_4: Core0 access peripherals permission configuration register 4. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_4.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_5: Core0 access peripherals permission configuration register 5. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_5.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_6: Core0 access peripherals permission configuration register 6. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_6.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_7: Core0 access peripherals permission configuration register 7. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_7.Reg) & 0x30000000) >> 28 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_8: Core0 access peripherals permission configuration register 8. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_8.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_9: Core0 access peripherals permission configuration register 9. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg)&^(0x7ff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg) & 0x7ff +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_9.Reg) & 0x3ff800) >> 11 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_10: Core0 access peripherals permission configuration register 10. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_10.Reg) & 0xe00) >> 9 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_11: Core0 access peripherals permission configuration register 11. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_11_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_11.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_11.Reg)&^(0x7ff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_11_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_11.Reg) & 0x7ff +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_11_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_11.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_11.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_11_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_11.Reg) & 0x3ff800) >> 11 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_12: Core0 access peripherals permission configuration register 12. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_12.Reg) & 0xe00) >> 9 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_13: Core0 access peripherals permission configuration register 13. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_13_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_13.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_13.Reg)&^(0x7ff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_13_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_13.Reg) & 0x7ff +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_13_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_13.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_13.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_13_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_13.Reg) & 0x3ff800) >> 11 +} + +// SENSITIVE.CORE_0_PIF_PMS_CONSTRAIN_14: Core0 access peripherals permission configuration register 14. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_CONSTRAIN_14.Reg) & 0xe00) >> 9 +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_0: Core0 region permission register 0. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_0_CORE_0_REGION_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_0_CORE_0_REGION_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_1: Core0 region permission register 1. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_1.Reg) & 0x300000) >> 20 +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_2: Core0 region permission register 2. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10() uint32 { + return (volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_2.Reg) & 0x300000) >> 20 +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_3: Core0 region permission register 3. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_3_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_3.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_3_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_3.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_4: Core0 region permission register 4. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_4_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_4.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_4_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_4.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_5: Core0 region permission register 5. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_5_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_5.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_5_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_5.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_6: Core0 region permission register 6. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_6_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_6.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_6_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_6.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_7: Core0 region permission register 7. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_7_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_7.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_7_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_7.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_8: Core0 region permission register 8. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_8_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_8.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_8_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_8.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_9: Core0 region permission register 9. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_9_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_9.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_9.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_9_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_9.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_10: Core0 region permission register 10. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_10_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_10.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_10_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_10.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_11: Core0 region permission register 11. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_11_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_11.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_11.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_11_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_11.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_12: Core0 region permission register 12. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_12_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_12.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_12_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_12.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_13: Core0 region permission register 13. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_13_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_13.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_13.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_13_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_13.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_REGION_PMS_CONSTRAIN_14: Core0 region permission register 14. +func (o *SENSITIVE_Type) SetCORE_0_REGION_PMS_CONSTRAIN_14_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11(value uint32) { + volatile.StoreUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_14.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_REGION_PMS_CONSTRAIN_14_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11() uint32 { + return volatile.LoadUint32(&o.CORE_0_REGION_PMS_CONSTRAIN_14.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_0: Core0 permission report register 0. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_1: Core0 permission report register 1. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_2: Core0 permission report register 2. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0x1c)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0x1c) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0x20)|value<<5) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0x20) >> 5 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_2.Reg) & 0xc0) >> 6 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_3: Core0 permission report register 3. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_3(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_3.Reg, value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_3() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_3.Reg) +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_4: Core0 permission report register 4. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_4.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_5: Core0 permission report register 5. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg)&^(0x6)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg) & 0x6) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg, volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg)&^(0x18)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_5.Reg) & 0x18) >> 3 +} + +// SENSITIVE.CORE_0_PIF_PMS_MONITOR_6: Core0 permission report register 6. +func (o *SENSITIVE_Type) SetCORE_0_PIF_PMS_MONITOR_6(value uint32) { + volatile.StoreUint32(&o.CORE_0_PIF_PMS_MONITOR_6.Reg, value) +} +func (o *SENSITIVE_Type) GetCORE_0_PIF_PMS_MONITOR_6() uint32 { + return volatile.LoadUint32(&o.CORE_0_PIF_PMS_MONITOR_6.Reg) +} + +// SENSITIVE.CORE_0_VECBASE_OVERRIDE_LOCK: core0 vecbase override configuration register 0 +func (o *SENSITIVE_Type) SetCORE_0_VECBASE_OVERRIDE_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_VECBASE_OVERRIDE_LOCK.Reg, volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_VECBASE_OVERRIDE_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_LOCK.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_VECBASE_OVERRIDE_0: core0 vecbase override configuration register 0 +func (o *SENSITIVE_Type) SetCORE_0_VECBASE_OVERRIDE_0_CORE_0_VECBASE_WORLD_MASK(value uint32) { + volatile.StoreUint32(&o.CORE_0_VECBASE_OVERRIDE_0.Reg, volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_VECBASE_OVERRIDE_0_CORE_0_VECBASE_WORLD_MASK() uint32 { + return volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_VECBASE_OVERRIDE_1: core0 vecbase override configuration register 1 +func (o *SENSITIVE_Type) SetCORE_0_VECBASE_OVERRIDE_1_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE(value uint32) { + volatile.StoreUint32(&o.CORE_0_VECBASE_OVERRIDE_1.Reg, volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_1.Reg)&^(0x3fffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_VECBASE_OVERRIDE_1_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE() uint32 { + return volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_1.Reg) & 0x3fffff +} +func (o *SENSITIVE_Type) SetCORE_0_VECBASE_OVERRIDE_1_CORE_0_VECBASE_OVERRIDE_SEL(value uint32) { + volatile.StoreUint32(&o.CORE_0_VECBASE_OVERRIDE_1.Reg, volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_1.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_0_VECBASE_OVERRIDE_1_CORE_0_VECBASE_OVERRIDE_SEL() uint32 { + return (volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_1.Reg) & 0xc00000) >> 22 +} + +// SENSITIVE.CORE_0_VECBASE_OVERRIDE_2: core0 vecbase override configuration register 1 +func (o *SENSITIVE_Type) SetCORE_0_VECBASE_OVERRIDE_2_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE(value uint32) { + volatile.StoreUint32(&o.CORE_0_VECBASE_OVERRIDE_2.Reg, volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_2.Reg)&^(0x3fffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_VECBASE_OVERRIDE_2_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE() uint32 { + return volatile.LoadUint32(&o.CORE_0_VECBASE_OVERRIDE_2.Reg) & 0x3fffff +} + +// SENSITIVE.CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0: core0 toomanyexception override configuration register 0. +func (o *SENSITIVE_Type) SetCORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0.Reg, volatile.LoadUint32(&o.CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1: core0 toomanyexception override configuration register 1. +func (o *SENSITIVE_Type) SetCORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1.Reg, volatile.LoadUint32(&o.CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE() uint32 { + return volatile.LoadUint32(&o.CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1.Reg) & 0x1 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_0: Core1 access peripherals permission configuration register 0. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_0_CORE_1_PIF_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_0_CORE_1_PIF_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_1: Core1 access peripherals permission configuration register 1. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_1.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_2: Core1 access peripherals permission configuration register 2. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_2.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_3: Core1 access peripherals permission configuration register 3. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_3.Reg) & 0x30000000) >> 28 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_4: Core1 access peripherals permission configuration register 4. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_4.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_5: Core1 access peripherals permission configuration register 5. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_5.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_6: Core1 access peripherals permission configuration register 6. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_6.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_7: Core1 access peripherals permission configuration register 7. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_7.Reg) & 0x30000000) >> 28 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_8: Core1 access peripherals permission configuration register 8. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_8.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_9: Core1 access peripherals permission configuration register 9. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_9_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_9.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_9.Reg)&^(0x7ff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_9_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_9.Reg) & 0x7ff +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_9_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_9.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_9.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_9_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_9.Reg) & 0x3ff800) >> 11 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_10: core1 access peripherals permission configuration register 10. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_10.Reg) & 0xe00) >> 9 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_11: core1 access peripherals permission configuration register 11. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_11_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_11.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_11.Reg)&^(0x7ff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_11_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_11.Reg) & 0x7ff +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_11_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_11.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_11.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_11_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_11.Reg) & 0x3ff800) >> 11 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_12: core1 access peripherals permission configuration register 12. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_12.Reg) & 0xe00) >> 9 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_13: core1 access peripherals permission configuration register 13. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_13_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_13.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_13.Reg)&^(0x7ff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_13_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_13.Reg) & 0x7ff +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_13_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_13.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_13.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_13_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_13.Reg) & 0x3ff800) >> 11 +} + +// SENSITIVE.CORE_1_PIF_PMS_CONSTRAIN_14: core1 access peripherals permission configuration register 14. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg)&^(0x1c0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg) & 0x1c0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg)&^(0xe00)|value<<9) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_CONSTRAIN_14.Reg) & 0xe00) >> 9 +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_0: core1 region permission register 0. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_0_CORE_1_REGION_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_0_CORE_1_REGION_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_1: core1 region permission register 1. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_1.Reg) & 0x300000) >> 20 +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_2: core1 region permission register 2. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10() uint32 { + return (volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_2.Reg) & 0x300000) >> 20 +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_3: core1 region permission register 3. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_3_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_3.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_3_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_3.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_4: core1 region permission register 4. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_4_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_4.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_4_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_4.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_5: core1 region permission register 5. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_5_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_5.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_5_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_5.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_6: core1 region permission register 6. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_6_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_6.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_6_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_6.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_7: core1 region permission register 7. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_7_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_7.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_7.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_7_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_7.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_8: core1 region permission register 8. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_8_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_8.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_8.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_8_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_8.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_9: core1 region permission register 9. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_9_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_9.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_9.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_9_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_9.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_10: core1 region permission register 10. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_10_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_10.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_10.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_10_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_10.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_11: core1 region permission register 11. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_11_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_11.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_11.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_11_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_11.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_12: core1 region permission register 12. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_12_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_12.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_12.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_12_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_12.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_13: core1 region permission register 13. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_13_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_13.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_13.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_13_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_13.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_REGION_PMS_CONSTRAIN_14: core1 region permission register 14. +func (o *SENSITIVE_Type) SetCORE_1_REGION_PMS_CONSTRAIN_14_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11(value uint32) { + volatile.StoreUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_14.Reg, volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_14.Reg)&^(0x3fffffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_REGION_PMS_CONSTRAIN_14_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11() uint32 { + return volatile.LoadUint32(&o.CORE_1_REGION_PMS_CONSTRAIN_14.Reg) & 0x3fffffff +} + +// SENSITIVE.CORE_1_PIF_PMS_MONITOR_0: core1 permission report register 0. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_0_CORE_1_PIF_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_0_CORE_1_PIF_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_1_PIF_PMS_MONITOR_1: core1 permission report register 1. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_1_PIF_PMS_MONITOR_2: core1 permission report register 2. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg) & 0x2) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg)&^(0x1c)|value<<2) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg) & 0x1c) >> 2 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg)&^(0x20)|value<<5) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg) & 0x20) >> 5 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_2.Reg) & 0xc0) >> 6 +} + +// SENSITIVE.CORE_1_PIF_PMS_MONITOR_3: core1 permission report register 3. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_3(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_3.Reg, value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_3() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_3.Reg) +} + +// SENSITIVE.CORE_1_PIF_PMS_MONITOR_4: core1 permission report register 4. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_4.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_4.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_4.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_4.Reg) & 0x2) >> 1 +} + +// SENSITIVE.CORE_1_PIF_PMS_MONITOR_5: core1 permission report register 5. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_5.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_5.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_5.Reg)&^(0x6)|value<<1) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_5.Reg) & 0x6) >> 1 +} +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_5.Reg, volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_5.Reg)&^(0x18)|value<<3) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD() uint32 { + return (volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_5.Reg) & 0x18) >> 3 +} + +// SENSITIVE.CORE_1_PIF_PMS_MONITOR_6: core1 permission report register 6. +func (o *SENSITIVE_Type) SetCORE_1_PIF_PMS_MONITOR_6(value uint32) { + volatile.StoreUint32(&o.CORE_1_PIF_PMS_MONITOR_6.Reg, value) +} +func (o *SENSITIVE_Type) GetCORE_1_PIF_PMS_MONITOR_6() uint32 { + return volatile.LoadUint32(&o.CORE_1_PIF_PMS_MONITOR_6.Reg) +} + +// SENSITIVE.CORE_1_VECBASE_OVERRIDE_LOCK: core1 vecbase override configuration register 0 +func (o *SENSITIVE_Type) SetCORE_1_VECBASE_OVERRIDE_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_1_VECBASE_OVERRIDE_LOCK.Reg, volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_VECBASE_OVERRIDE_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_LOCK.Reg) & 0x1 +} + +// SENSITIVE.CORE_1_VECBASE_OVERRIDE_0: core1 vecbase override configuration register 0 +func (o *SENSITIVE_Type) SetCORE_1_VECBASE_OVERRIDE_0_CORE_1_VECBASE_WORLD_MASK(value uint32) { + volatile.StoreUint32(&o.CORE_1_VECBASE_OVERRIDE_0.Reg, volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_VECBASE_OVERRIDE_0_CORE_1_VECBASE_WORLD_MASK() uint32 { + return volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_1_VECBASE_OVERRIDE_1: core1 vecbase override configuration register 1 +func (o *SENSITIVE_Type) SetCORE_1_VECBASE_OVERRIDE_1_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE(value uint32) { + volatile.StoreUint32(&o.CORE_1_VECBASE_OVERRIDE_1.Reg, volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_1.Reg)&^(0x3fffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_VECBASE_OVERRIDE_1_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE() uint32 { + return volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_1.Reg) & 0x3fffff +} +func (o *SENSITIVE_Type) SetCORE_1_VECBASE_OVERRIDE_1_CORE_1_VECBASE_OVERRIDE_SEL(value uint32) { + volatile.StoreUint32(&o.CORE_1_VECBASE_OVERRIDE_1.Reg, volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_1.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetCORE_1_VECBASE_OVERRIDE_1_CORE_1_VECBASE_OVERRIDE_SEL() uint32 { + return (volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_1.Reg) & 0xc00000) >> 22 +} + +// SENSITIVE.CORE_1_VECBASE_OVERRIDE_2: core1 vecbase override configuration register 1 +func (o *SENSITIVE_Type) SetCORE_1_VECBASE_OVERRIDE_2_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE(value uint32) { + volatile.StoreUint32(&o.CORE_1_VECBASE_OVERRIDE_2.Reg, volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_2.Reg)&^(0x3fffff)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_VECBASE_OVERRIDE_2_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE() uint32 { + return volatile.LoadUint32(&o.CORE_1_VECBASE_OVERRIDE_2.Reg) & 0x3fffff +} + +// SENSITIVE.CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0: core1 toomanyexception override configuration register 0. +func (o *SENSITIVE_Type) SetCORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK(value uint32) { + volatile.StoreUint32(&o.CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0.Reg, volatile.LoadUint32(&o.CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK() uint32 { + return volatile.LoadUint32(&o.CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0.Reg) & 0x1 +} + +// SENSITIVE.CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1: core1 toomanyexception override configuration register 1. +func (o *SENSITIVE_Type) SetCORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1.Reg, volatile.LoadUint32(&o.CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE() uint32 { + return volatile.LoadUint32(&o.CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1.Reg) & 0x1 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_0: BackUp access peripherals permission configuration register 0. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_0.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_0.Reg) & 0x1 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_1: BackUp access peripherals permission configuration register 1. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_GPIO(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_GPIO() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE2(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE2() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_RTC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_RTC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_HINF(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_HINF() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_MISC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_MISC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2C(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2C() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2S0(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2S0() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_1.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_2: BackUp access peripherals permission configuration register 2. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BT(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BT() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_UHCI0(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_UHCI0() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_RMT(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_RMT() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_PCNT(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_PCNT() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SLC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SLC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_LEDC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_LEDC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BACKUP(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BACKUP() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BB(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BB() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_PWM0(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_PWM0() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_2.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_3: BackUp access peripherals permission configuration register 3. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_2(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_2() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_3(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_3() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_CAN(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_CAN() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWM1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWM1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2S1(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2S1() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_UART2(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_UART2() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_RWBT(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_RWBT() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWR(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWR() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_3.Reg) & 0x30000000) >> 28 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_4: BackUp access peripherals permission configuration register 4. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc) >> 2 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x30)|value<<4) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x30) >> 4 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc0)|value<<6) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc0) >> 6 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x300)|value<<8) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x300) >> 8 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc00)|value<<10) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc00) >> 10 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x3000)|value<<12) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x3000) >> 12 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc000)|value<<14) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc000) >> 14 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x30000)|value<<16) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x30000) >> 16 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc0000)|value<<18) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc0000) >> 18 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x300000)|value<<20) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x300000) >> 20 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc00000)|value<<22) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc00000) >> 22 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x3000000)|value<<24) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x3000000) >> 24 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_AD(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc000000)|value<<26) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_AD() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc000000) >> 26 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_DIO(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0x30000000)|value<<28) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_DIO() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0x30000000) >> 28 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg)&^(0xc0000000)|value<<30) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_4.Reg) & 0xc0000000) >> 30 +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_5: BackUp access peripherals permission configuration register 5. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_5_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_5.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_5.Reg)&^(0x7ff)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_5_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_5.Reg) & 0x7ff +} + +// SENSITIVE.BACKUP_BUS_PMS_CONSTRAIN_6: BackUp access peripherals permission configuration register 6. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_6_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_6.Reg)&^(0x7)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_6_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_6.Reg) & 0x7 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_CONSTRAIN_6_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_6.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_6.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_CONSTRAIN_6_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_CONSTRAIN_6.Reg) & 0x38) >> 3 +} + +// SENSITIVE.BACKUP_BUS_PMS_MONITOR_0: BackUp permission report register 0. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_0.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_0.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_0.Reg) & 0x1 +} + +// SENSITIVE.BACKUP_BUS_PMS_MONITOR_1: BackUp permission report register 1. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg)&^(0x2)|value<<1) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_1.Reg) & 0x2) >> 1 +} + +// SENSITIVE.BACKUP_BUS_PMS_MONITOR_2: BackUp permission report register 2. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg) & 0x1 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg)&^(0x6)|value<<1) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg) & 0x6) >> 1 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg)&^(0x38)|value<<3) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg) & 0x38) >> 3 +} +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg, volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg)&^(0x40)|value<<6) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE() uint32 { + return (volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_2.Reg) & 0x40) >> 6 +} + +// SENSITIVE.BACKUP_BUS_PMS_MONITOR_3: BackUp permission report register 3. +func (o *SENSITIVE_Type) SetBACKUP_BUS_PMS_MONITOR_3(value uint32) { + volatile.StoreUint32(&o.BACKUP_BUS_PMS_MONITOR_3.Reg, value) +} +func (o *SENSITIVE_Type) GetBACKUP_BUS_PMS_MONITOR_3() uint32 { + return volatile.LoadUint32(&o.BACKUP_BUS_PMS_MONITOR_3.Reg) +} + +// SENSITIVE.EDMA_BOUNDARY_LOCK: EDMA boundary lock register. +func (o *SENSITIVE_Type) SetEDMA_BOUNDARY_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_BOUNDARY_LOCK.Reg, volatile.LoadUint32(&o.EDMA_BOUNDARY_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_BOUNDARY_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_BOUNDARY_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_BOUNDARY_0: EDMA boundary 0 configuration +func (o *SENSITIVE_Type) SetEDMA_BOUNDARY_0(value uint32) { + volatile.StoreUint32(&o.EDMA_BOUNDARY_0.Reg, volatile.LoadUint32(&o.EDMA_BOUNDARY_0.Reg)&^(0x3fff)|value) +} +func (o *SENSITIVE_Type) GetEDMA_BOUNDARY_0() uint32 { + return volatile.LoadUint32(&o.EDMA_BOUNDARY_0.Reg) & 0x3fff +} + +// SENSITIVE.EDMA_BOUNDARY_1: EDMA boundary 1 configuration +func (o *SENSITIVE_Type) SetEDMA_BOUNDARY_1(value uint32) { + volatile.StoreUint32(&o.EDMA_BOUNDARY_1.Reg, volatile.LoadUint32(&o.EDMA_BOUNDARY_1.Reg)&^(0x3fff)|value) +} +func (o *SENSITIVE_Type) GetEDMA_BOUNDARY_1() uint32 { + return volatile.LoadUint32(&o.EDMA_BOUNDARY_1.Reg) & 0x3fff +} + +// SENSITIVE.EDMA_BOUNDARY_2: EDMA boundary 2 configuration +func (o *SENSITIVE_Type) SetEDMA_BOUNDARY_2(value uint32) { + volatile.StoreUint32(&o.EDMA_BOUNDARY_2.Reg, volatile.LoadUint32(&o.EDMA_BOUNDARY_2.Reg)&^(0x3fff)|value) +} +func (o *SENSITIVE_Type) GetEDMA_BOUNDARY_2() uint32 { + return volatile.LoadUint32(&o.EDMA_BOUNDARY_2.Reg) & 0x3fff +} + +// SENSITIVE.EDMA_PMS_SPI2_LOCK: EDMA-SPI2 permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_SPI2_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_SPI2_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_SPI2_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_SPI2_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_SPI2_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_SPI2: EDMA-SPI2 permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_SPI2_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_SPI2.Reg, volatile.LoadUint32(&o.EDMA_PMS_SPI2.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_SPI2_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_SPI2.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_SPI2_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_SPI2.Reg, volatile.LoadUint32(&o.EDMA_PMS_SPI2.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_SPI2_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_SPI2.Reg) & 0xc) >> 2 +} + +// SENSITIVE.EDMA_PMS_SPI3_LOCK: EDMA-SPI3 permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_SPI3_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_SPI3_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_SPI3_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_SPI3_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_SPI3_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_SPI3: EDMA-SPI3 permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_SPI3_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_SPI3.Reg, volatile.LoadUint32(&o.EDMA_PMS_SPI3.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_SPI3_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_SPI3.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_SPI3_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_SPI3.Reg, volatile.LoadUint32(&o.EDMA_PMS_SPI3.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_SPI3_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_SPI3.Reg) & 0xc) >> 2 +} + +// SENSITIVE.EDMA_PMS_UHCI0_LOCK: EDMA-UHCI0 permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_UHCI0_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_UHCI0_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_UHCI0_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_UHCI0_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_UHCI0_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_UHCI0: EDMA-UHCI0 permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_UHCI0_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_UHCI0.Reg, volatile.LoadUint32(&o.EDMA_PMS_UHCI0.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_UHCI0_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_UHCI0.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_UHCI0_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_UHCI0.Reg, volatile.LoadUint32(&o.EDMA_PMS_UHCI0.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_UHCI0_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_UHCI0.Reg) & 0xc) >> 2 +} + +// SENSITIVE.EDMA_PMS_I2S0_LOCK: EDMA-I2S0 permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_I2S0_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_I2S0_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_I2S0_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_I2S0_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_I2S0_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_I2S0: EDMA-I2S0 permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_I2S0_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_I2S0.Reg, volatile.LoadUint32(&o.EDMA_PMS_I2S0.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_I2S0_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_I2S0.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_I2S0_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_I2S0.Reg, volatile.LoadUint32(&o.EDMA_PMS_I2S0.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_I2S0_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_I2S0.Reg) & 0xc) >> 2 +} + +// SENSITIVE.EDMA_PMS_I2S1_LOCK: EDMA-I2S1 permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_I2S1_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_I2S1_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_I2S1_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_I2S1_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_I2S1_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_I2S1: EDMA-I2S1 permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_I2S1_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_I2S1.Reg, volatile.LoadUint32(&o.EDMA_PMS_I2S1.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_I2S1_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_I2S1.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_I2S1_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_I2S1.Reg, volatile.LoadUint32(&o.EDMA_PMS_I2S1.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_I2S1_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_I2S1.Reg) & 0xc) >> 2 +} + +// SENSITIVE.EDMA_PMS_LCD_CAM_LOCK: EDMA-LCD/CAM permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_LCD_CAM_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_LCD_CAM_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_LCD_CAM_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_LCD_CAM_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_LCD_CAM_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_LCD_CAM: EDMA-LCD/CAM permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_LCD_CAM_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_LCD_CAM.Reg, volatile.LoadUint32(&o.EDMA_PMS_LCD_CAM.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_LCD_CAM_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_LCD_CAM.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_LCD_CAM_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_LCD_CAM.Reg, volatile.LoadUint32(&o.EDMA_PMS_LCD_CAM.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_LCD_CAM_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_LCD_CAM.Reg) & 0xc) >> 2 +} + +// SENSITIVE.EDMA_PMS_AES_LOCK: EDMA-AES permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_AES_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_AES_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_AES_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_AES_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_AES_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_AES: EDMA-AES permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_AES_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_AES.Reg, volatile.LoadUint32(&o.EDMA_PMS_AES.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_AES_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_AES.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_AES_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_AES.Reg, volatile.LoadUint32(&o.EDMA_PMS_AES.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_AES_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_AES.Reg) & 0xc) >> 2 +} + +// SENSITIVE.EDMA_PMS_SHA_LOCK: EDMA-SHA permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_SHA_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_SHA_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_SHA_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_SHA_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_SHA_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_SHA: EDMA-SHA permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_SHA_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_SHA.Reg, volatile.LoadUint32(&o.EDMA_PMS_SHA.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_SHA_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_SHA.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_SHA_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_SHA.Reg, volatile.LoadUint32(&o.EDMA_PMS_SHA.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_SHA_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_SHA.Reg) & 0xc) >> 2 +} + +// SENSITIVE.EDMA_PMS_ADC_DAC_LOCK: EDMA-ADC/DAC permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_ADC_DAC_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_ADC_DAC_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_ADC_DAC_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_ADC_DAC_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_ADC_DAC_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_ADC_DAC: EDMA-ADC/DAC permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_ADC_DAC_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_ADC_DAC.Reg, volatile.LoadUint32(&o.EDMA_PMS_ADC_DAC.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_ADC_DAC_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_ADC_DAC.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_ADC_DAC_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_ADC_DAC.Reg, volatile.LoadUint32(&o.EDMA_PMS_ADC_DAC.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_ADC_DAC_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_ADC_DAC.Reg) & 0xc) >> 2 +} + +// SENSITIVE.EDMA_PMS_RMT_LOCK: EDMA-RMT permission lock register. +func (o *SENSITIVE_Type) SetEDMA_PMS_RMT_LOCK(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_RMT_LOCK.Reg, volatile.LoadUint32(&o.EDMA_PMS_RMT_LOCK.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_RMT_LOCK() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_RMT_LOCK.Reg) & 0x1 +} + +// SENSITIVE.EDMA_PMS_RMT: EDMA-RMT permission control register. +func (o *SENSITIVE_Type) SetEDMA_PMS_RMT_ATTR1(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_RMT.Reg, volatile.LoadUint32(&o.EDMA_PMS_RMT.Reg)&^(0x3)|value) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_RMT_ATTR1() uint32 { + return volatile.LoadUint32(&o.EDMA_PMS_RMT.Reg) & 0x3 +} +func (o *SENSITIVE_Type) SetEDMA_PMS_RMT_ATTR2(value uint32) { + volatile.StoreUint32(&o.EDMA_PMS_RMT.Reg, volatile.LoadUint32(&o.EDMA_PMS_RMT.Reg)&^(0xc)|value<<2) +} +func (o *SENSITIVE_Type) GetEDMA_PMS_RMT_ATTR2() uint32 { + return (volatile.LoadUint32(&o.EDMA_PMS_RMT.Reg) & 0xc) >> 2 +} + +// SENSITIVE.CLOCK_GATE: Sensitive module clock gate configuration register. +func (o *SENSITIVE_Type) SetCLOCK_GATE_REG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetCLOCK_GATE_REG_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SENSITIVE.RTC_PMS: RTC coprocessor permission register. +func (o *SENSITIVE_Type) SetRTC_PMS_DIS_RTC_CPU(value uint32) { + volatile.StoreUint32(&o.RTC_PMS.Reg, volatile.LoadUint32(&o.RTC_PMS.Reg)&^(0x1)|value) +} +func (o *SENSITIVE_Type) GetRTC_PMS_DIS_RTC_CPU() uint32 { + return volatile.LoadUint32(&o.RTC_PMS.Reg) & 0x1 +} + +// SENSITIVE.DATE: Sensitive version register. +func (o *SENSITIVE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SENSITIVE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SHA (Secure Hash Algorithm) Accelerator +type SHA_Type struct { + MODE volatile.Register32 // 0x0 + T_STRING volatile.Register32 // 0x4 + T_LENGTH volatile.Register32 // 0x8 + DMA_BLOCK_NUM volatile.Register32 // 0xC + START volatile.Register32 // 0x10 + CONTINUE volatile.Register32 // 0x14 + BUSY volatile.Register32 // 0x18 + DMA_START volatile.Register32 // 0x1C + DMA_CONTINUE volatile.Register32 // 0x20 + CLEAR_IRQ volatile.Register32 // 0x24 + IRQ_ENA volatile.Register32 // 0x28 + DATE volatile.Register32 // 0x2C + _ [16]byte + H_MEM [64]volatile.Register8 // 0x40 + M_MEM [64]volatile.Register8 // 0x80 +} + +// SHA.MODE: Initial configuration register. +func (o *SHA_Type) SetMODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value) +} +func (o *SHA_Type) GetMODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x7 +} + +// SHA.T_STRING: SHA 512/t configuration register 0. +func (o *SHA_Type) SetT_STRING(value uint32) { + volatile.StoreUint32(&o.T_STRING.Reg, value) +} +func (o *SHA_Type) GetT_STRING() uint32 { + return volatile.LoadUint32(&o.T_STRING.Reg) +} + +// SHA.T_LENGTH: SHA 512/t configuration register 1. +func (o *SHA_Type) SetT_LENGTH(value uint32) { + volatile.StoreUint32(&o.T_LENGTH.Reg, volatile.LoadUint32(&o.T_LENGTH.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetT_LENGTH() uint32 { + return volatile.LoadUint32(&o.T_LENGTH.Reg) & 0x3f +} + +// SHA.DMA_BLOCK_NUM: DMA configuration register 0. +func (o *SHA_Type) SetDMA_BLOCK_NUM(value uint32) { + volatile.StoreUint32(&o.DMA_BLOCK_NUM.Reg, volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg)&^(0x3f)|value) +} +func (o *SHA_Type) GetDMA_BLOCK_NUM() uint32 { + return volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg) & 0x3f +} + +// SHA.START: Typical SHA configuration register 0. +func (o *SHA_Type) SetSTART(value uint32) { + volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetSTART() uint32 { + return (volatile.LoadUint32(&o.START.Reg) & 0xfffffffe) >> 1 +} + +// SHA.CONTINUE: Typical SHA configuration register 1. +func (o *SHA_Type) SetCONTINUE(value uint32) { + volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0xfffffffe)|value<<1) +} +func (o *SHA_Type) GetCONTINUE() uint32 { + return (volatile.LoadUint32(&o.CONTINUE.Reg) & 0xfffffffe) >> 1 +} + +// SHA.BUSY: Busy register. +func (o *SHA_Type) SetBUSY_STATE(value uint32) { + volatile.StoreUint32(&o.BUSY.Reg, volatile.LoadUint32(&o.BUSY.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetBUSY_STATE() uint32 { + return volatile.LoadUint32(&o.BUSY.Reg) & 0x1 +} + +// SHA.DMA_START: DMA configuration register 1. +func (o *SHA_Type) SetDMA_START(value uint32) { + volatile.StoreUint32(&o.DMA_START.Reg, volatile.LoadUint32(&o.DMA_START.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_START() uint32 { + return volatile.LoadUint32(&o.DMA_START.Reg) & 0x1 +} + +// SHA.DMA_CONTINUE: DMA configuration register 2. +func (o *SHA_Type) SetDMA_CONTINUE(value uint32) { + volatile.StoreUint32(&o.DMA_CONTINUE.Reg, volatile.LoadUint32(&o.DMA_CONTINUE.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetDMA_CONTINUE() uint32 { + return volatile.LoadUint32(&o.DMA_CONTINUE.Reg) & 0x1 +} + +// SHA.CLEAR_IRQ: Interrupt clear register. +func (o *SHA_Type) SetCLEAR_IRQ_CLEAR_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.CLEAR_IRQ.Reg, volatile.LoadUint32(&o.CLEAR_IRQ.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetCLEAR_IRQ_CLEAR_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.CLEAR_IRQ.Reg) & 0x1 +} + +// SHA.IRQ_ENA: Interrupt enable register. +func (o *SHA_Type) SetIRQ_ENA_INTERRUPT_ENA(value uint32) { + volatile.StoreUint32(&o.IRQ_ENA.Reg, volatile.LoadUint32(&o.IRQ_ENA.Reg)&^(0x1)|value) +} +func (o *SHA_Type) GetIRQ_ENA_INTERRUPT_ENA() uint32 { + return volatile.LoadUint32(&o.IRQ_ENA.Reg) & 0x1 +} + +// SHA.DATE: Date register. +func (o *SHA_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *SHA_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// SPI (Serial Peripheral Interface) Controller 0 +type SPI0_Type struct { + _ [8]byte + CTRL volatile.Register32 // 0x8 + CTRL1 volatile.Register32 // 0xC + CTRL2 volatile.Register32 // 0x10 + CLOCK volatile.Register32 // 0x14 + USER volatile.Register32 // 0x18 + USER1 volatile.Register32 // 0x1C + USER2 volatile.Register32 // 0x20 + _ [8]byte + RD_STATUS volatile.Register32 // 0x2C + EXT_ADDR volatile.Register32 // 0x30 + MISC volatile.Register32 // 0x34 + _ [4]byte + CACHE_FCTRL volatile.Register32 // 0x3C + CACHE_SCTRL volatile.Register32 // 0x40 + SRAM_CMD volatile.Register32 // 0x44 + SRAM_DRD_CMD volatile.Register32 // 0x48 + SRAM_DWR_CMD volatile.Register32 // 0x4C + SRAM_CLK volatile.Register32 // 0x50 + FSM volatile.Register32 // 0x54 + _ [80]byte + TIMING_CALI volatile.Register32 // 0xA8 + DIN_MODE volatile.Register32 // 0xAC + DIN_NUM volatile.Register32 // 0xB0 + DOUT_MODE volatile.Register32 // 0xB4 + _ [4]byte + SPI_SMEM_TIMING_CALI volatile.Register32 // 0xBC + SPI_SMEM_DIN_MODE volatile.Register32 // 0xC0 + SPI_SMEM_DIN_NUM volatile.Register32 // 0xC4 + SPI_SMEM_DOUT_MODE volatile.Register32 // 0xC8 + ECC_CTRL volatile.Register32 // 0xCC + ECC_ERR_ADDR volatile.Register32 // 0xD0 + ECC_ERR_BIT volatile.Register32 // 0xD4 + _ [4]byte + SPI_SMEM_AC volatile.Register32 // 0xDC + DDR volatile.Register32 // 0xE0 + SPI_SMEM_DDR volatile.Register32 // 0xE4 + CLOCK_GATE volatile.Register32 // 0xE8 + CORE_CLK_SEL volatile.Register32 // 0xEC + INT_ENA volatile.Register32 // 0xF0 + INT_CLR volatile.Register32 // 0xF4 + INT_RAW volatile.Register32 // 0xF8 + INT_ST volatile.Register32 // 0xFC + _ [764]byte + DATE volatile.Register32 // 0x3FC +} + +// SPI0.CTRL: SPI0 control register. +func (o *SPI0_Type) SetCTRL_FDUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetCTRL_FDUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetCTRL_FDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetCTRL_FDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetCTRL_FDIN_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetCTRL_FDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetCTRL_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetCTRL_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetCTRL_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetCTRL_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetCTRL_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetCTRL_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetCTRL_WP(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetCTRL_WP() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetCTRL_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetCTRL_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetCTRL_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetCTRL_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} + +// SPI0.CTRL1: SPI0 control 1 register. +func (o *SPI0_Type) SetCTRL1_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetCTRL1_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.CTRL1.Reg) & 0x3 +} +func (o *SPI0_Type) SetCTRL1_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetCTRL1_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0x40000000) >> 30 +} + +// SPI0.CTRL2: SPI0 control 2 register. +func (o *SPI0_Type) SetCTRL2_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1f)|value) +} +func (o *SPI0_Type) GetCTRL2_CS_SETUP_TIME() uint32 { + return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1f +} +func (o *SPI0_Type) SetCTRL2_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x3e0)|value<<5) +} +func (o *SPI0_Type) GetCTRL2_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x3e0) >> 5 +} +func (o *SPI0_Type) SetCTRL2_ECC_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1c00)|value<<10) +} +func (o *SPI0_Type) GetCTRL2_ECC_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1c00) >> 10 +} +func (o *SPI0_Type) SetCTRL2_ECC_SKIP_PAGE_CORNER(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetCTRL2_ECC_SKIP_PAGE_CORNER() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetCTRL2_ECC_16TO18_BYTE_EN(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetCTRL2_ECC_16TO18_BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetCTRL2_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetCTRL2_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x7e000000) >> 25 +} +func (o *SPI0_Type) SetCTRL2_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetCTRL2_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI0.CLOCK: SPI_CLK clock division register when SPI0 accesses to flash. +func (o *SPI0_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0xff +} +func (o *SPI0_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI0.USER: SPI0 user register. +func (o *SPI0_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} + +// SPI0.USER1: SPI0 user1 register. +func (o *SPI0_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3f)|value) +} +func (o *SPI0_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0x3f +} +func (o *SPI0_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI0_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI0.USER2: SPI0 user2 register. +func (o *SPI0_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI0_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI0.RD_STATUS: SPI0 read control register. +func (o *SPI0_Type) SetRD_STATUS_WB_MODE(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetRD_STATUS_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI0.EXT_ADDR: SPI0 extended address register. +func (o *SPI0_Type) SetEXT_ADDR(value uint32) { + volatile.StoreUint32(&o.EXT_ADDR.Reg, value) +} +func (o *SPI0_Type) GetEXT_ADDR() uint32 { + return volatile.LoadUint32(&o.EXT_ADDR.Reg) +} + +// SPI0.MISC: SPI0 misc register +func (o *SPI0_Type) SetMISC_FSUB_PIN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetMISC_FSUB_PIN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetMISC_SSUB_PIN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetMISC_SSUB_PIN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x100) >> 8 +} +func (o *SPI0_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI0_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x200) >> 9 +} +func (o *SPI0_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x400) >> 10 +} + +// SPI0.CACHE_FCTRL: SPI0 external RAM bit mode control register. +func (o *SPI0_Type) SetCACHE_FCTRL_CACHE_REQ_EN(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetCACHE_FCTRL_CACHE_REQ_EN() uint32 { + return volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetCACHE_FCTRL_CACHE_USR_CMD_4BYTE(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetCACHE_FCTRL_CACHE_USR_CMD_4BYTE() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetCACHE_FCTRL_CACHE_FLASH_USR_CMD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetCACHE_FCTRL_CACHE_FLASH_USR_CMD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetCACHE_FCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetCACHE_FCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x100) >> 8 +} + +// SPI0.CACHE_SCTRL: SPI0 external RAM control register +func (o *SPI0_Type) SetCACHE_SCTRL_CACHE_USR_SCMD_4BYTE(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetCACHE_SCTRL_CACHE_USR_SCMD_4BYTE() uint32 { + return volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x1 +} +func (o *SPI0_Type) SetCACHE_SCTRL_USR_SRAM_DIO(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetCACHE_SCTRL_USR_SRAM_DIO() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetCACHE_SCTRL_USR_SRAM_QIO(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetCACHE_SCTRL_USR_SRAM_QIO() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetCACHE_SCTRL_USR_WR_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetCACHE_SCTRL_USR_WR_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetCACHE_SCTRL_USR_RD_SRAM_DUMMY(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetCACHE_SCTRL_USR_RD_SRAM_DUMMY() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetCACHE_SCTRL_CACHE_SRAM_USR_RCMD(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetCACHE_SCTRL_CACHE_SRAM_USR_RCMD() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetCACHE_SCTRL_SRAM_RDUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI0_Type) GetCACHE_SCTRL_SRAM_RDUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0xfc0) >> 6 +} +func (o *SPI0_Type) SetCACHE_SCTRL_SRAM_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0xfc000)|value<<14) +} +func (o *SPI0_Type) GetCACHE_SCTRL_SRAM_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0xfc000) >> 14 +} +func (o *SPI0_Type) SetCACHE_SCTRL_CACHE_SRAM_USR_WCMD(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetCACHE_SCTRL_CACHE_SRAM_USR_WCMD() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetCACHE_SCTRL_SRAM_OCT(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetCACHE_SCTRL_SRAM_OCT() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetCACHE_SCTRL_SRAM_WDUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.CACHE_SCTRL.Reg, volatile.LoadUint32(&o.CACHE_SCTRL.Reg)&^(0xfc00000)|value<<22) +} +func (o *SPI0_Type) GetCACHE_SCTRL_SRAM_WDUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.CACHE_SCTRL.Reg) & 0xfc00000) >> 22 +} + +// SPI0.SRAM_CMD: SPI0 external RAM mode control register +func (o *SPI0_Type) SetSRAM_CMD_SCLK_MODE(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSRAM_CMD_SCLK_MODE() uint32 { + return volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x3 +} +func (o *SPI0_Type) SetSRAM_CMD_SWB_MODE(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x3fc)|value<<2) +} +func (o *SPI0_Type) GetSRAM_CMD_SWB_MODE() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x3fc) >> 2 +} +func (o *SPI0_Type) SetSRAM_CMD_SDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetSRAM_CMD_SDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x400) >> 10 +} +func (o *SPI0_Type) SetSRAM_CMD_SDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x800)|value<<11) +} +func (o *SPI0_Type) GetSRAM_CMD_SDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x800) >> 11 +} +func (o *SPI0_Type) SetSRAM_CMD_SADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSRAM_CMD_SADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSRAM_CMD_SCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSRAM_CMD_SCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSRAM_CMD_SDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSRAM_CMD_SDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSRAM_CMD_SDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x8000)|value<<15) +} +func (o *SPI0_Type) GetSRAM_CMD_SDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x8000) >> 15 +} +func (o *SPI0_Type) SetSRAM_CMD_SADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetSRAM_CMD_SADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetSRAM_CMD_SCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI0_Type) GetSRAM_CMD_SCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI0_Type) SetSRAM_CMD_SDIN_OCT(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSRAM_CMD_SDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetSRAM_CMD_SDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetSRAM_CMD_SDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI0_Type) SetSRAM_CMD_SADDR_OCT(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSRAM_CMD_SADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSRAM_CMD_SCMD_OCT(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSRAM_CMD_SCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSRAM_CMD_SDUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.SRAM_CMD.Reg, volatile.LoadUint32(&o.SRAM_CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetSRAM_CMD_SDUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.SRAM_CMD.Reg) & 0x400000) >> 22 +} + +// SPI0.SRAM_DRD_CMD: SPI0 external RAM DDR read command control register +func (o *SPI0_Type) SetSRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SRAM_DRD_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SRAM_DRD_CMD.Reg) & 0xffff +} +func (o *SPI0_Type) SetSRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SRAM_DRD_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SRAM_DRD_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SRAM_DWR_CMD: SPI0 external RAM DDR write command control register +func (o *SPI0_Type) SetSRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SRAM_DWR_CMD.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SRAM_DWR_CMD.Reg) & 0xffff +} +func (o *SPI0_Type) SetSRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_BITLEN(value uint32) { + volatile.StoreUint32(&o.SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SRAM_DWR_CMD.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SRAM_DWR_CMD.Reg) & 0xf0000000) >> 28 +} + +// SPI0.SRAM_CLK: SPI_CLK clock division register when SPI0 accesses to Ext_RAM. +func (o *SPI0_Type) SetSRAM_CLK_SCLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SRAM_CLK.Reg, volatile.LoadUint32(&o.SRAM_CLK.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSRAM_CLK_SCLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SRAM_CLK.Reg) & 0xff +} +func (o *SPI0_Type) SetSRAM_CLK_SCLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SRAM_CLK.Reg, volatile.LoadUint32(&o.SRAM_CLK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetSRAM_CLK_SCLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SRAM_CLK.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetSRAM_CLK_SCLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SRAM_CLK.Reg, volatile.LoadUint32(&o.SRAM_CLK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSRAM_CLK_SCLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SRAM_CLK.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSRAM_CLK_SCLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SRAM_CLK.Reg, volatile.LoadUint32(&o.SRAM_CLK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSRAM_CLK_SCLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SRAM_CLK.Reg) & 0x80000000) >> 31 +} + +// SPI0.FSM: SPI0 state machine(FSM) status register. +func (o *SPI0_Type) SetFSM_ST(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetFSM_ST() uint32 { + return volatile.LoadUint32(&o.FSM.Reg) & 0x7 +} + +// SPI0.TIMING_CALI: SPI0 timing compensation register when accesses to flash. +func (o *SPI0_Type) SetTIMING_CALI_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetTIMING_CALI_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetTIMING_CALI(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetTIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetTIMING_CALI_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetTIMING_CALI_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI0.DIN_MODE: MSPI input timing delay mode control register when accesses to flash. +func (o *SPI0_Type) SetDIN_MODE_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetDIN_MODE_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x7 +} +func (o *SPI0_Type) SetDIN_MODE_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI0_Type) GetDIN_MODE_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI0_Type) SetDIN_MODE_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetDIN_MODE_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetDIN_MODE_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI0_Type) GetDIN_MODE_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI0_Type) SetDIN_MODE_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetDIN_MODE_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetDIN_MODE_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI0_Type) GetDIN_MODE_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI0_Type) SetDIN_MODE_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetDIN_MODE_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetDIN_MODE_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI0_Type) GetDIN_MODE_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI0_Type) SetDIN_MODE_DINS_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x7000000)|value<<24) +} +func (o *SPI0_Type) GetDIN_MODE_DINS_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x7000000) >> 24 +} + +// SPI0.DIN_NUM: MSPI input timing delay number control register when accesses to flash. +func (o *SPI0_Type) SetDIN_NUM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetDIN_NUM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetDIN_NUM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetDIN_NUM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetDIN_NUM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetDIN_NUM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetDIN_NUM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetDIN_NUM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI0_Type) SetDIN_NUM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI0_Type) GetDIN_NUM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI0_Type) SetDIN_NUM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI0_Type) GetDIN_NUM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI0_Type) SetDIN_NUM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI0_Type) GetDIN_NUM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI0_Type) SetDIN_NUM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI0_Type) GetDIN_NUM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc000) >> 14 +} +func (o *SPI0_Type) SetDIN_NUM_DINS_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetDIN_NUM_DINS_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x30000) >> 16 +} + +// SPI0.DOUT_MODE: MSPI output timing delay mode control register when accesses to flash. +func (o *SPI0_Type) SetDOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetDOUT_MODE_DOUTS_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetDOUT_MODE_DOUTS_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI0.SPI_SMEM_TIMING_CALI: SPI0 Ext_RAM timing compensation register. +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI0.SPI_SMEM_DIN_MODE: MSPI input timing delay mode control register when accesses to Ext_RAM. +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00)|value<<9) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00) >> 9 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38000)|value<<15) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38000) >> 15 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00000)|value<<21) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00000) >> 21 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000000) >> 24 +} + +// SPI0.SPI_SMEM_DIN_NUM: MSPI input timing delay number control register when accesses to Ext_RAM. +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc000) >> 14 +} +func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30000) >> 16 +} + +// SPI0.SPI_SMEM_DOUT_MODE: MSPI output timing delay mode control register when accesses to Ext_RAM. +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI0.ECC_CTRL: MSPI ECC control register +func (o *SPI0_Type) SetECC_CTRL_ECC_ERR_INT_NUM(value uint32) { + volatile.StoreUint32(&o.ECC_CTRL.Reg, volatile.LoadUint32(&o.ECC_CTRL.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetECC_CTRL_ECC_ERR_INT_NUM() uint32 { + return volatile.LoadUint32(&o.ECC_CTRL.Reg) & 0xff +} +func (o *SPI0_Type) SetECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN(value uint32) { + volatile.StoreUint32(&o.ECC_CTRL.Reg, volatile.LoadUint32(&o.ECC_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI0_Type) GetECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN() uint32 { + return (volatile.LoadUint32(&o.ECC_CTRL.Reg) & 0x100) >> 8 +} + +// SPI0.ECC_ERR_ADDR: MSPI ECC error address register +func (o *SPI0_Type) SetECC_ERR_ADDR(value uint32) { + volatile.StoreUint32(&o.ECC_ERR_ADDR.Reg, value) +} +func (o *SPI0_Type) GetECC_ERR_ADDR() uint32 { + return volatile.LoadUint32(&o.ECC_ERR_ADDR.Reg) +} + +// SPI0.ECC_ERR_BIT: MSPI ECC error bits register +func (o *SPI0_Type) SetECC_ERR_BIT_ECC_DATA_ERR_BIT(value uint32) { + volatile.StoreUint32(&o.ECC_ERR_BIT.Reg, volatile.LoadUint32(&o.ECC_ERR_BIT.Reg)&^(0x1fc0)|value<<6) +} +func (o *SPI0_Type) GetECC_ERR_BIT_ECC_DATA_ERR_BIT() uint32 { + return (volatile.LoadUint32(&o.ECC_ERR_BIT.Reg) & 0x1fc0) >> 6 +} +func (o *SPI0_Type) SetECC_ERR_BIT_ECC_CHK_ERR_BIT(value uint32) { + volatile.StoreUint32(&o.ECC_ERR_BIT.Reg, volatile.LoadUint32(&o.ECC_ERR_BIT.Reg)&^(0xe000)|value<<13) +} +func (o *SPI0_Type) GetECC_ERR_BIT_ECC_CHK_ERR_BIT() uint32 { + return (volatile.LoadUint32(&o.ECC_ERR_BIT.Reg) & 0xe000) >> 13 +} +func (o *SPI0_Type) SetECC_ERR_BIT_ECC_BYTE_ERR(value uint32) { + volatile.StoreUint32(&o.ECC_ERR_BIT.Reg, volatile.LoadUint32(&o.ECC_ERR_BIT.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetECC_ERR_BIT_ECC_BYTE_ERR() uint32 { + return (volatile.LoadUint32(&o.ECC_ERR_BIT.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetECC_ERR_BIT_ECC_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.ECC_ERR_BIT.Reg, volatile.LoadUint32(&o.ECC_ERR_BIT.Reg)&^(0x1fe0000)|value<<17) +} +func (o *SPI0_Type) GetECC_ERR_BIT_ECC_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.ECC_ERR_BIT.Reg) & 0x1fe0000) >> 17 +} + +// SPI0.SPI_SMEM_AC: MSPI external RAM ECC and SPI CS timing control register +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7c)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7c) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0xf80)|value<<7) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0xf80) >> 7 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x8000)|value<<15) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x8000) >> 15 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_ERR_INT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_ERR_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7e000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7e000000) >> 25 +} + +// SPI0.DDR: SPI0 flash DDR mode control register +func (o *SPI0_Type) SetDDR_SPI_FMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.DDR.Reg) & 0x1 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_TX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_TX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_RX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_RX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_DDR_DQS_LOOP_MODE(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_DDR_DQS_LOOP_MODE() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x400000) >> 22 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_HYPERBUS_MODE(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_HYPERBUS_MODE() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetDDR_SPI_FMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetDDR_SPI_FMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x40000000) >> 30 +} + +// SPI0.SPI_SMEM_DDR: SPI0 external RAM DDR mode control register +func (o *SPI0_Type) SetSPI_SMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_DQS_LOOP_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_DQS_LOOP_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x400000) >> 22 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x40000000) >> 30 +} + +// SPI0.CLOCK_GATE: SPI0 clk_gate register +func (o *SPI0_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SPI0.CORE_CLK_SEL: SPI0 module clock select register +func (o *SPI0_Type) SetCORE_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetCORE_CLK_SEL() uint32 { + return volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0x3 +} + +// SPI0.INT_ENA: SPI1 interrupt enable register +func (o *SPI0_Type) SetINT_ENA_TOTAL_TRANS_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetINT_ENA_TOTAL_TRANS_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetINT_ENA_ECC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetINT_ENA_ECC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} + +// SPI0.INT_CLR: SPI1 interrupt clear register +func (o *SPI0_Type) SetINT_CLR_TOTAL_TRANS_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetINT_CLR_TOTAL_TRANS_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetINT_CLR_ECC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetINT_CLR_ECC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} + +// SPI0.INT_RAW: SPI1 interrupt raw register +func (o *SPI0_Type) SetINT_RAW_TOTAL_TRANS_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetINT_RAW_TOTAL_TRANS_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetINT_RAW_ECC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetINT_RAW_ECC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} + +// SPI0.INT_ST: SPI1 interrupt status register +func (o *SPI0_Type) SetINT_ST_TOTAL_TRANS_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetINT_ST_TOTAL_TRANS_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetINT_ST_ECC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetINT_ST_ECC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} + +// SPI0.DATE: SPI0 version control register +func (o *SPI0_Type) SetDATE_SPI_SMEM_SPICLK_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetDATE_SPI_SMEM_SPICLK_FUN_DRV() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3 +} +func (o *SPI0_Type) SetDATE_SPI_FMEM_SPICLK_FUN_DRV(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xc)|value<<2) +} +func (o *SPI0_Type) GetDATE_SPI_FMEM_SPICLK_FUN_DRV() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0xc) >> 2 +} +func (o *SPI0_Type) SetDATE_SPI_SPICLK_PAD_DRV_CTL_EN(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetDATE_SPI_SPICLK_PAD_DRV_CTL_EN() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffe0)|value<<5) +} +func (o *SPI0_Type) GetDATE() uint32 { + return (volatile.LoadUint32(&o.DATE.Reg) & 0xfffffe0) >> 5 +} + +// SPI (Serial Peripheral Interface) Controller 1 +type SPI1_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CTRL1 volatile.Register32 // 0xC + CTRL2 volatile.Register32 // 0x10 + CLOCK volatile.Register32 // 0x14 + USER volatile.Register32 // 0x18 + USER1 volatile.Register32 // 0x1C + USER2 volatile.Register32 // 0x20 + MOSI_DLEN volatile.Register32 // 0x24 + MISO_DLEN volatile.Register32 // 0x28 + RD_STATUS volatile.Register32 // 0x2C + EXT_ADDR volatile.Register32 // 0x30 + MISC volatile.Register32 // 0x34 + TX_CRC volatile.Register32 // 0x38 + CACHE_FCTRL volatile.Register32 // 0x3C + _ [20]byte + FSM volatile.Register32 // 0x54 + W0 volatile.Register32 // 0x58 + W1 volatile.Register32 // 0x5C + W2 volatile.Register32 // 0x60 + W3 volatile.Register32 // 0x64 + W4 volatile.Register32 // 0x68 + W5 volatile.Register32 // 0x6C + W6 volatile.Register32 // 0x70 + W7 volatile.Register32 // 0x74 + W8 volatile.Register32 // 0x78 + W9 volatile.Register32 // 0x7C + W10 volatile.Register32 // 0x80 + W11 volatile.Register32 // 0x84 + W12 volatile.Register32 // 0x88 + W13 volatile.Register32 // 0x8C + W14 volatile.Register32 // 0x90 + W15 volatile.Register32 // 0x94 + FLASH_WAITI_CTRL volatile.Register32 // 0x98 + FLASH_SUS_CMD volatile.Register32 // 0x9C + FLASH_SUS_CTRL volatile.Register32 // 0xA0 + SUS_STATUS volatile.Register32 // 0xA4 + TIMING_CALI volatile.Register32 // 0xA8 + _ [52]byte + DDR volatile.Register32 // 0xE0 + _ [4]byte + CLOCK_GATE volatile.Register32 // 0xE8 + _ [4]byte + INT_ENA volatile.Register32 // 0xF0 + INT_CLR volatile.Register32 // 0xF4 + INT_RAW volatile.Register32 // 0xF8 + INT_ST volatile.Register32 // 0xFC + _ [764]byte + DATE volatile.Register32 // 0x3FC +} + +// SPI1.CMD: SPI1 memory command register +func (o *SPI1_Type) SetCMD_FLASH_PE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000)|value<<17) +} +func (o *SPI1_Type) GetCMD_FLASH_PE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000) >> 17 +} +func (o *SPI1_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetCMD_FLASH_HPM(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetCMD_FLASH_HPM() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetCMD_FLASH_RES(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetCMD_FLASH_RES() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetCMD_FLASH_DP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetCMD_FLASH_DP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetCMD_FLASH_CE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetCMD_FLASH_CE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetCMD_FLASH_BE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetCMD_FLASH_BE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetCMD_FLASH_SE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetCMD_FLASH_SE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetCMD_FLASH_PP(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetCMD_FLASH_PP() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetCMD_FLASH_WRSR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetCMD_FLASH_WRSR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetCMD_FLASH_RDSR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetCMD_FLASH_RDSR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetCMD_FLASH_RDID(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetCMD_FLASH_RDID() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetCMD_FLASH_WRDI(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetCMD_FLASH_WRDI() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetCMD_FLASH_WREN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetCMD_FLASH_WREN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetCMD_FLASH_READ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetCMD_FLASH_READ() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31 +} + +// SPI1.ADDR: SPI1 address register +func (o *SPI1_Type) SetADDR(value uint32) { + volatile.StoreUint32(&o.ADDR.Reg, value) +} +func (o *SPI1_Type) GetADDR() uint32 { + return volatile.LoadUint32(&o.ADDR.Reg) +} + +// SPI1.CTRL: SPI1 control register +func (o *SPI1_Type) SetCTRL_FDUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetCTRL_FDUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetCTRL_FDOUT_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetCTRL_FDOUT_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetCTRL_FDIN_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetCTRL_FDIN_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetCTRL_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetCTRL_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI1_Type) SetCTRL_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetCTRL_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetCTRL_FCS_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetCTRL_FCS_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI1_Type) SetCTRL_TX_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11) +} +func (o *SPI1_Type) GetCTRL_TX_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11 +} +func (o *SPI1_Type) SetCTRL_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetCTRL_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetCTRL_RESANDRES(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetCTRL_RESANDRES() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI1_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetCTRL_WP(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetCTRL_WP() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetCTRL_WRSR_2B(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetCTRL_WRSR_2B() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetCTRL_FREAD_DIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetCTRL_FREAD_DIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetCTRL_FREAD_QIO(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetCTRL_FREAD_QIO() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24 +} + +// SPI1.CTRL1: SPI1 control1 register +func (o *SPI1_Type) SetCTRL1_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0x3)|value) +} +func (o *SPI1_Type) GetCTRL1_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.CTRL1.Reg) & 0x3 +} +func (o *SPI1_Type) SetCTRL1_CS_HOLD_DLY_RES(value uint32) { + volatile.StoreUint32(&o.CTRL1.Reg, volatile.LoadUint32(&o.CTRL1.Reg)&^(0xffc)|value<<2) +} +func (o *SPI1_Type) GetCTRL1_CS_HOLD_DLY_RES() uint32 { + return (volatile.LoadUint32(&o.CTRL1.Reg) & 0xffc) >> 2 +} + +// SPI1.CTRL2: SPI1 control2 register +func (o *SPI1_Type) SetCTRL2_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetCTRL2_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x80000000) >> 31 +} + +// SPI1.CLOCK: SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM. +func (o *SPI1_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0xff +} +func (o *SPI1_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xff0000) >> 16 +} +func (o *SPI1_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI1.USER: SPI1 user register. +func (o *SPI1_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI1_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI1_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetUSER_FWRITE_DIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetUSER_FWRITE_DIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetUSER_FWRITE_QIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetUSER_FWRITE_QIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI1.USER1: SPI1 user1 register. +func (o *SPI1_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3f)|value) +} +func (o *SPI1_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0x3f +} +func (o *SPI1_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI1_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xfc000000) >> 26 +} + +// SPI1.USER2: SPI1 user2 register. +func (o *SPI1_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI1_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI1_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI1.MOSI_DLEN: SPI1 write-data bit length register. +func (o *SPI1_Type) SetMOSI_DLEN_USR_MOSI_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MOSI_DLEN.Reg, volatile.LoadUint32(&o.MOSI_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetMOSI_DLEN_USR_MOSI_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MOSI_DLEN.Reg) & 0x3ff +} + +// SPI1.MISO_DLEN: SPI1 read-data bit length register. +func (o *SPI1_Type) SetMISO_DLEN_USR_MISO_DBITLEN(value uint32) { + volatile.StoreUint32(&o.MISO_DLEN.Reg, volatile.LoadUint32(&o.MISO_DLEN.Reg)&^(0x3ff)|value) +} +func (o *SPI1_Type) GetMISO_DLEN_USR_MISO_DBITLEN() uint32 { + return volatile.LoadUint32(&o.MISO_DLEN.Reg) & 0x3ff +} + +// SPI1.RD_STATUS: SPI1 read control register. +func (o *SPI1_Type) SetRD_STATUS_STATUS(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetRD_STATUS_STATUS() uint32 { + return volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xffff +} +func (o *SPI1_Type) SetRD_STATUS_WB_MODE(value uint32) { + volatile.StoreUint32(&o.RD_STATUS.Reg, volatile.LoadUint32(&o.RD_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetRD_STATUS_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.RD_STATUS.Reg) & 0xff0000) >> 16 +} + +// SPI1.EXT_ADDR: SPI1 extended address register. +func (o *SPI1_Type) SetEXT_ADDR(value uint32) { + volatile.StoreUint32(&o.EXT_ADDR.Reg, value) +} +func (o *SPI1_Type) GetEXT_ADDR() uint32 { + return volatile.LoadUint32(&o.EXT_ADDR.Reg) +} + +// SPI1.MISC: SPI1 misc register. +func (o *SPI1_Type) SetMISC_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetMISC_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.MISC.Reg) & 0x1 +} +func (o *SPI1_Type) SetMISC_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetMISC_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x200)|value<<9) +} +func (o *SPI1_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x200) >> 9 +} +func (o *SPI1_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x400) >> 10 +} +func (o *SPI1_Type) SetMISC_AUTO_PER(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x800)|value<<11) +} +func (o *SPI1_Type) GetMISC_AUTO_PER() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x800) >> 11 +} + +// SPI1.TX_CRC: SPI1 CRC data register. +func (o *SPI1_Type) SetTX_CRC(value uint32) { + volatile.StoreUint32(&o.TX_CRC.Reg, value) +} +func (o *SPI1_Type) GetTX_CRC() uint32 { + return volatile.LoadUint32(&o.TX_CRC.Reg) +} + +// SPI1.CACHE_FCTRL: SPI1 bit mode control register. +func (o *SPI1_Type) SetCACHE_FCTRL_CACHE_USR_CMD_4BYTE(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetCACHE_FCTRL_CACHE_USR_CMD_4BYTE() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDIN_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDIN_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDOUT_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDOUT_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDIN_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDIN_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FDOUT_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FDOUT_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetCACHE_FCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CACHE_FCTRL.Reg, volatile.LoadUint32(&o.CACHE_FCTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI1_Type) GetCACHE_FCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CACHE_FCTRL.Reg) & 0x100) >> 8 +} + +// SPI1.FSM: SPI1 state machine(FSM) status register. +func (o *SPI1_Type) SetFSM_ST(value uint32) { + volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0x7)|value) +} +func (o *SPI1_Type) GetFSM_ST() uint32 { + return volatile.LoadUint32(&o.FSM.Reg) & 0x7 +} + +// SPI1.W0: SPI1 memory data buffer0 +func (o *SPI1_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI1_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI1.W1: SPI1 memory data buffer1 +func (o *SPI1_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI1_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI1.W2: SPI1 memory data buffer2 +func (o *SPI1_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI1_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI1.W3: SPI1 memory data buffer3 +func (o *SPI1_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI1_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI1.W4: SPI1 memory data buffer4 +func (o *SPI1_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI1_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI1.W5: SPI1 memory data buffer5 +func (o *SPI1_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI1_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI1.W6: SPI1 memory data buffer6 +func (o *SPI1_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI1_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI1.W7: SPI1 memory data buffer7 +func (o *SPI1_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI1_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI1.W8: SPI1 memory data buffer8 +func (o *SPI1_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI1_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI1.W9: SPI1 memory data buffer9 +func (o *SPI1_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI1_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI1.W10: SPI1 memory data buffer10 +func (o *SPI1_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI1_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI1.W11: SPI1 memory data buffer11 +func (o *SPI1_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI1_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI1.W12: SPI1 memory data buffer12 +func (o *SPI1_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI1_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI1.W13: SPI1 memory data buffer13 +func (o *SPI1_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI1_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI1.W14: SPI1 memory data buffer14 +func (o *SPI1_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI1_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI1.W15: SPI1 memory data buffer15 +func (o *SPI1_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI1_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI1.FLASH_WAITI_CTRL: SPI1 wait idle control register +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_EN() uint32 { + return volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_DUMMY(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_DUMMY() uint32 { + return (volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_CMD(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0x3fc)|value<<2) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_CMD() uint32 { + return (volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0x3fc) >> 2 +} +func (o *SPI1_Type) SetFLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg)&^(0xfc00)|value<<10) +} +func (o *SPI1_Type) GetFLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.FLASH_WAITI_CTRL.Reg) & 0xfc00) >> 10 +} + +// SPI1.FLASH_SUS_CMD: SPI1 flash suspend control register +func (o *SPI1_Type) SetFLASH_SUS_CMD_FLASH_PER(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_FLASH_PER() uint32 { + return volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0x1 +} +func (o *SPI1_Type) SetFLASH_SUS_CMD_FLASH_PES(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_FLASH_PES() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetFLASH_SUS_CMD_FLASH_PER_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_FLASH_PER_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetFLASH_SUS_CMD_FLASH_PES_WAIT_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_FLASH_PES_WAIT_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetFLASH_SUS_CMD_PES_PER_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_PES_PER_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetFLASH_SUS_CMD_PESR_IDLE_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetFLASH_SUS_CMD_PESR_IDLE_EN() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CMD.Reg) & 0x20) >> 5 +} + +// SPI1.FLASH_SUS_CTRL: SPI1 flash suspend command register +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PES_EN(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PES_EN() uint32 { + return volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x1 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PER_COMMAND(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x1fe)|value<<1) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PER_COMMAND() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x1fe) >> 1 +} +func (o *SPI1_Type) SetFLASH_SUS_CTRL_FLASH_PES_COMMAND(value uint32) { + volatile.StoreUint32(&o.FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg)&^(0x1fe00)|value<<9) +} +func (o *SPI1_Type) GetFLASH_SUS_CTRL_FLASH_PES_COMMAND() uint32 { + return (volatile.LoadUint32(&o.FLASH_SUS_CTRL.Reg) & 0x1fe00) >> 9 +} + +// SPI1.SUS_STATUS: SPI1 flash suspend status register +func (o *SPI1_Type) SetSUS_STATUS_FLASH_SUS(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_SUS() uint32 { + return volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x1 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_HPM_DLY_256(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_HPM_DLY_256() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_RES_DLY_256(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_RES_DLY_256() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_DP_DLY_256(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_DP_DLY_256() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_PER_DLY_256(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_PER_DLY_256() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSUS_STATUS_FLASH_PES_DLY_256(value uint32) { + volatile.StoreUint32(&o.SUS_STATUS.Reg, volatile.LoadUint32(&o.SUS_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSUS_STATUS_FLASH_PES_DLY_256() uint32 { + return (volatile.LoadUint32(&o.SUS_STATUS.Reg) & 0x40) >> 6 +} + +// SPI1.TIMING_CALI: SPI1 timing compensation register when accesses to flash or Ext_RAM. +func (o *SPI1_Type) SetTIMING_CALI(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetTIMING_CALI() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetTIMING_CALI_EXTRA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.TIMING_CALI.Reg, volatile.LoadUint32(&o.TIMING_CALI.Reg)&^(0x1c)|value<<2) +} +func (o *SPI1_Type) GetTIMING_CALI_EXTRA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.TIMING_CALI.Reg) & 0x1c) >> 2 +} + +// SPI1.DDR: SPI1 DDR control register +func (o *SPI1_Type) SetDDR_SPI_FMEM_DDR_EN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_DDR_EN() uint32 { + return volatile.LoadUint32(&o.DDR.Reg) & 0x1 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_VAR_DUMMY(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_VAR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_DDR_RDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_DDR_WDAT_SWP() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_DDR_CMD_DIS(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_DDR_CMD_DIS() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_OUTMINBYTELEN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0xfe0)|value<<5) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_OUTMINBYTELEN() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0xfe0) >> 5 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x1fc000)|value<<14) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x1fc000) >> 14 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_DDR_DQS_LOOP() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_DDR_DQS_LOOP_MODE(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_DDR_DQS_LOOP_MODE() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_CLK_DIFF_EN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_CLK_DIFF_EN() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_HYPERBUS_MODE(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_HYPERBUS_MODE() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_DQS_CA_IN(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_DQS_CA_IN() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_CLK_DIFF_INV(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_CLK_DIFF_INV() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetDDR_SPI_FMEM_HYPERBUS_CA(value uint32) { + volatile.StoreUint32(&o.DDR.Reg, volatile.LoadUint32(&o.DDR.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetDDR_SPI_FMEM_HYPERBUS_CA() uint32 { + return (volatile.LoadUint32(&o.DDR.Reg) & 0x40000000) >> 30 +} + +// SPI1.CLOCK_GATE: SPI1 clk_gate register +func (o *SPI1_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SPI1.INT_ENA: SPI1 interrupt enable register +func (o *SPI1_Type) SetINT_ENA_PER_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_ENA_PER_END_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_ENA_PES_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_ENA_PES_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_ENA_TOTAL_TRANS_END_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_ENA_TOTAL_TRANS_END_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_ENA_BROWN_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_ENA_BROWN_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} + +// SPI1.INT_CLR: SPI1 interrupt clear register +func (o *SPI1_Type) SetINT_CLR_PER_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_CLR_PER_END_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_CLR_PES_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_CLR_PES_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_CLR_TOTAL_TRANS_END_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_CLR_TOTAL_TRANS_END_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_CLR_BROWN_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_CLR_BROWN_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} + +// SPI1.INT_RAW: SPI1 interrupt raw register +func (o *SPI1_Type) SetINT_RAW_PER_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_RAW_PER_END_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_RAW_PES_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_RAW_PES_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_RAW_TOTAL_TRANS_END_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_RAW_TOTAL_TRANS_END_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_RAW_BROWN_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_RAW_BROWN_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} + +// SPI1.INT_ST: SPI1 interrupt status register +func (o *SPI1_Type) SetINT_ST_PER_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetINT_ST_PER_END_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *SPI1_Type) SetINT_ST_PES_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetINT_ST_PES_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetINT_ST_TOTAL_TRANS_END_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetINT_ST_TOTAL_TRANS_END_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetINT_ST_BROWN_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetINT_ST_BROWN_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} + +// SPI1.DATE: SPI0 version control register +func (o *SPI1_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI1_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SPI (Serial Peripheral Interface) Controller 2 +type SPI2_Type struct { + CMD volatile.Register32 // 0x0 + ADDR volatile.Register32 // 0x4 + CTRL volatile.Register32 // 0x8 + CLOCK volatile.Register32 // 0xC + USER volatile.Register32 // 0x10 + USER1 volatile.Register32 // 0x14 + USER2 volatile.Register32 // 0x18 + MS_DLEN volatile.Register32 // 0x1C + MISC volatile.Register32 // 0x20 + DIN_MODE volatile.Register32 // 0x24 + DIN_NUM volatile.Register32 // 0x28 + DOUT_MODE volatile.Register32 // 0x2C + DMA_CONF volatile.Register32 // 0x30 + DMA_INT_ENA volatile.Register32 // 0x34 + DMA_INT_CLR volatile.Register32 // 0x38 + DMA_INT_RAW volatile.Register32 // 0x3C + DMA_INT_ST volatile.Register32 // 0x40 + DMA_INT_SET volatile.Register32 // 0x44 + _ [80]byte + W0 volatile.Register32 // 0x98 + W1 volatile.Register32 // 0x9C + W2 volatile.Register32 // 0xA0 + W3 volatile.Register32 // 0xA4 + W4 volatile.Register32 // 0xA8 + W5 volatile.Register32 // 0xAC + W6 volatile.Register32 // 0xB0 + W7 volatile.Register32 // 0xB4 + W8 volatile.Register32 // 0xB8 + W9 volatile.Register32 // 0xBC + W10 volatile.Register32 // 0xC0 + W11 volatile.Register32 // 0xC4 + W12 volatile.Register32 // 0xC8 + W13 volatile.Register32 // 0xCC + W14 volatile.Register32 // 0xD0 + W15 volatile.Register32 // 0xD4 + _ [8]byte + SLAVE volatile.Register32 // 0xE0 + SLAVE1 volatile.Register32 // 0xE4 + CLK_GATE volatile.Register32 // 0xE8 + _ [4]byte + DATE volatile.Register32 // 0xF0 +} + +// SPI2.CMD: Command control register +func (o *SPI2_Type) SetCMD_CONF_BITLEN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetCMD_CONF_BITLEN() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetCMD_UPDATE(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetCMD_UPDATE() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetCMD_USR(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetCMD_USR() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000000) >> 24 +} + +// SPI2.ADDR: Address value register +func (o *SPI2_Type) SetADDR(value uint32) { + volatile.StoreUint32(&o.ADDR.Reg, value) +} +func (o *SPI2_Type) GetADDR() uint32 { + return volatile.LoadUint32(&o.ADDR.Reg) +} + +// SPI2.CTRL: SPI control register +func (o *SPI2_Type) SetCTRL_DUMMY_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetCTRL_DUMMY_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetCTRL_FADDR_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetCTRL_FADDR_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetCTRL_FADDR_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetCTRL_FADDR_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetCTRL_FADDR_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetCTRL_FADDR_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetCTRL_FCMD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetCTRL_FCMD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetCTRL_FCMD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetCTRL_FCMD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetCTRL_FCMD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetCTRL_FCMD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetCTRL_FREAD_DUAL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetCTRL_FREAD_DUAL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetCTRL_FREAD_QUAD(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetCTRL_FREAD_QUAD() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetCTRL_FREAD_OCT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetCTRL_FREAD_OCT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetCTRL_Q_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetCTRL_Q_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetCTRL_D_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetCTRL_D_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetCTRL_HOLD_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetCTRL_HOLD_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetCTRL_WP_POL(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetCTRL_WP_POL() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetCTRL_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1800000)|value<<23) +} +func (o *SPI2_Type) GetCTRL_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1800000) >> 23 +} +func (o *SPI2_Type) SetCTRL_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x6000000)|value<<25) +} +func (o *SPI2_Type) GetCTRL_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x6000000) >> 25 +} + +// SPI2.CLOCK: SPI clock control register +func (o *SPI2_Type) SetCLOCK_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI2_Type) SetCLOCK_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI2_Type) GetCLOCK_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI2_Type) SetCLOCK_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x3c0000)|value<<18) +} +func (o *SPI2_Type) GetCLOCK_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x3c0000) >> 18 +} +func (o *SPI2_Type) SetCLOCK_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.CLOCK.Reg, volatile.LoadUint32(&o.CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetCLOCK_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.CLOCK.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER: SPI USER control register +func (o *SPI2_Type) SetUSER_DOUTDIN(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetUSER_DOUTDIN() uint32 { + return volatile.LoadUint32(&o.USER.Reg) & 0x1 +} +func (o *SPI2_Type) SetUSER_QPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetUSER_QPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetUSER_OPI_MODE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetUSER_OPI_MODE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetUSER_TSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetUSER_TSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetUSER_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetUSER_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetUSER_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetUSER_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetUSER_RSCK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetUSER_RSCK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetUSER_CK_OUT_EDGE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetUSER_CK_OUT_EDGE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetUSER_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetUSER_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetUSER_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetUSER_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetUSER_FWRITE_OCT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetUSER_FWRITE_OCT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetUSER_USR_CONF_NXT(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetUSER_USR_CONF_NXT() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetUSER_SIO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetUSER_SIO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetUSER_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetUSER_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetUSER_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI2_Type) GetUSER_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY_IDLE(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY_IDLE() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetUSER_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER_USR_MISO(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetUSER_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetUSER_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetUSER_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetUSER_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetUSER_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetUSER_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.USER.Reg, volatile.LoadUint32(&o.USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetUSER_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.USER.Reg) & 0x80000000) >> 31 +} + +// SPI2.USER1: SPI USER control register 1 +func (o *SPI2_Type) SetUSER1_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xff)|value) +} +func (o *SPI2_Type) GetUSER1_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.USER1.Reg) & 0xff +} +func (o *SPI2_Type) SetUSER1_MST_WFULL_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetUSER1_MST_WFULL_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetUSER1_CS_SETUP_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x3e0000)|value<<17) +} +func (o *SPI2_Type) GetUSER1_CS_SETUP_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x3e0000) >> 17 +} +func (o *SPI2_Type) SetUSER1_CS_HOLD_TIME(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0x7c00000)|value<<22) +} +func (o *SPI2_Type) GetUSER1_CS_HOLD_TIME() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0x7c00000) >> 22 +} +func (o *SPI2_Type) SetUSER1_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER1.Reg, volatile.LoadUint32(&o.USER1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER1_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER1.Reg) & 0xf8000000) >> 27 +} + +// SPI2.USER2: SPI USER control register 2 +func (o *SPI2_Type) SetUSER2_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xffff)|value) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.USER2.Reg) & 0xffff +} +func (o *SPI2_Type) SetUSER2_MST_REMPTY_ERR_END_EN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetUSER2_MST_REMPTY_ERR_END_EN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetUSER2_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.USER2.Reg, volatile.LoadUint32(&o.USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI2_Type) GetUSER2_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.USER2.Reg) & 0xf0000000) >> 28 +} + +// SPI2.MS_DLEN: SPI data bit length control register +func (o *SPI2_Type) SetMS_DLEN_MS_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.MS_DLEN.Reg, volatile.LoadUint32(&o.MS_DLEN.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetMS_DLEN_MS_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.MS_DLEN.Reg) & 0x3ffff +} + +// SPI2.MISC: SPI misc register +func (o *SPI2_Type) SetMISC_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetMISC_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.MISC.Reg) & 0x1 +} +func (o *SPI2_Type) SetMISC_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetMISC_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetMISC_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetMISC_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetMISC_CS3_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetMISC_CS3_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetMISC_CS4_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetMISC_CS4_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetMISC_CS5_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetMISC_CS5_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetMISC_CK_DIS(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetMISC_CK_DIS() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetMISC_MASTER_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1f80)|value<<7) +} +func (o *SPI2_Type) GetMISC_MASTER_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1f80) >> 7 +} +func (o *SPI2_Type) SetMISC_CLK_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetMISC_CLK_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetMISC_DATA_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetMISC_DATA_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetMISC_ADDR_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetMISC_ADDR_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetMISC_CMD_DTR_EN(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetMISC_CMD_DTR_EN() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetMISC_SLAVE_CS_POL(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x800000)|value<<23) +} +func (o *SPI2_Type) GetMISC_SLAVE_CS_POL() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x800000) >> 23 +} +func (o *SPI2_Type) SetMISC_DQS_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI2_Type) GetMISC_DQS_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x1000000) >> 24 +} +func (o *SPI2_Type) SetMISC_CK_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetMISC_CK_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetMISC_CS_KEEP_ACTIVE(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetMISC_CS_KEEP_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetMISC_QUAD_DIN_PIN_SWAP(value uint32) { + volatile.StoreUint32(&o.MISC.Reg, volatile.LoadUint32(&o.MISC.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetMISC_QUAD_DIN_PIN_SWAP() uint32 { + return (volatile.LoadUint32(&o.MISC.Reg) & 0x80000000) >> 31 +} + +// SPI2.DIN_MODE: SPI input delay mode configuration +func (o *SPI2_Type) SetDIN_MODE_DIN0_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_MODE_DIN0_MODE() uint32 { + return volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_MODE_DIN1_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_MODE_DIN1_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_MODE_DIN2_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_MODE_DIN2_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_MODE_DIN3_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_MODE_DIN3_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetDIN_MODE_DIN4_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetDIN_MODE_DIN4_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetDIN_MODE_DIN5_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetDIN_MODE_DIN5_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetDIN_MODE_DIN6_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetDIN_MODE_DIN6_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetDIN_MODE_DIN7_MODE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetDIN_MODE_DIN7_MODE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0xc000) >> 14 +} +func (o *SPI2_Type) SetDIN_MODE_TIMING_HCLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.DIN_MODE.Reg, volatile.LoadUint32(&o.DIN_MODE.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDIN_MODE_TIMING_HCLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.DIN_MODE.Reg) & 0x10000) >> 16 +} + +// SPI2.DIN_NUM: SPI input delay number configuration +func (o *SPI2_Type) SetDIN_NUM_DIN0_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetDIN_NUM_DIN0_NUM() uint32 { + return volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3 +} +func (o *SPI2_Type) SetDIN_NUM_DIN1_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc)|value<<2) +} +func (o *SPI2_Type) GetDIN_NUM_DIN1_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc) >> 2 +} +func (o *SPI2_Type) SetDIN_NUM_DIN2_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x30)|value<<4) +} +func (o *SPI2_Type) GetDIN_NUM_DIN2_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x30) >> 4 +} +func (o *SPI2_Type) SetDIN_NUM_DIN3_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc0)|value<<6) +} +func (o *SPI2_Type) GetDIN_NUM_DIN3_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc0) >> 6 +} +func (o *SPI2_Type) SetDIN_NUM_DIN4_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x300)|value<<8) +} +func (o *SPI2_Type) GetDIN_NUM_DIN4_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x300) >> 8 +} +func (o *SPI2_Type) SetDIN_NUM_DIN5_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc00)|value<<10) +} +func (o *SPI2_Type) GetDIN_NUM_DIN5_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc00) >> 10 +} +func (o *SPI2_Type) SetDIN_NUM_DIN6_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0x3000)|value<<12) +} +func (o *SPI2_Type) GetDIN_NUM_DIN6_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0x3000) >> 12 +} +func (o *SPI2_Type) SetDIN_NUM_DIN7_NUM(value uint32) { + volatile.StoreUint32(&o.DIN_NUM.Reg, volatile.LoadUint32(&o.DIN_NUM.Reg)&^(0xc000)|value<<14) +} +func (o *SPI2_Type) GetDIN_NUM_DIN7_NUM() uint32 { + return (volatile.LoadUint32(&o.DIN_NUM.Reg) & 0xc000) >> 14 +} + +// SPI2.DOUT_MODE: SPI output delay mode configuration +func (o *SPI2_Type) SetDOUT_MODE_DOUT0_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT0_MODE() uint32 { + return volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT1_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT1_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT2_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT2_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT3_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT3_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT4_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT4_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT5_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT5_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT6_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT6_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDOUT_MODE_DOUT7_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDOUT_MODE_DOUT7_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDOUT_MODE_D_DQS_MODE(value uint32) { + volatile.StoreUint32(&o.DOUT_MODE.Reg, volatile.LoadUint32(&o.DOUT_MODE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDOUT_MODE_D_DQS_MODE() uint32 { + return (volatile.LoadUint32(&o.DOUT_MODE.Reg) & 0x100) >> 8 +} + +// SPI2.DMA_CONF: SPI DMA control register +func (o *SPI2_Type) SetDMA_CONF_DMA_OUTFIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_OUTFIFO_EMPTY() uint32 { + return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_INFIFO_FULL(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_INFIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_SLV_SEG_TRANS_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_SLV_SEG_TRANS_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_RX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_CONF_SLV_TX_SEG_TRANS_CLR_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x100000) >> 20 +} +func (o *SPI2_Type) SetDMA_CONF_RX_EOF_EN(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *SPI2_Type) GetDMA_CONF_RX_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x200000) >> 21 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_RX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_RX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_TX_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_TX_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x10000000) >> 28 +} +func (o *SPI2_Type) SetDMA_CONF_RX_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI2_Type) GetDMA_CONF_RX_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x20000000) >> 29 +} +func (o *SPI2_Type) SetDMA_CONF_BUF_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI2_Type) GetDMA_CONF_BUF_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SPI2_Type) SetDMA_CONF_DMA_AFIFO_RST(value uint32) { + volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI2_Type) GetDMA_CONF_DMA_AFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31 +} + +// SPI2.DMA_INT_ENA: SPI interrupt enable register +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EX_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EX_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_EN_QPI_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_EN_QPI_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD8_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD8_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD9_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD9_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMDA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMDA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ENA_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ENA_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ENA_SLV_CMD_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ENA_APP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ENA.Reg, volatile.LoadUint32(&o.DMA_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ENA_APP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ENA.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_CLR: SPI interrupt clear register +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR() uint32 { + return volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EX_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EX_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_EN_QPI_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_EN_QPI_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD8_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD8_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD9_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD9_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMDA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMDA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_CLR_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_CLR_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_CLR_SLV_CMD_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_CLR_APP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.DMA_INT_CLR.Reg, volatile.LoadUint32(&o.DMA_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_CLR_APP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_CLR.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_RAW: SPI interrupt raw register +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW() uint32 { + return volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EX_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EX_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_EN_QPI_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_EN_QPI_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD8_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD8_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD9_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD9_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMDA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMDA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_RAW_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_RAW_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_RAW_SLV_CMD_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_RAW_APP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.DMA_INT_RAW.Reg, volatile.LoadUint32(&o.DMA_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_RAW_APP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_RAW.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_ST: SPI interrupt status register +func (o *SPI2_Type) SetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST() uint32 { + return volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EX_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EX_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_EN_QPI_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_EN_QPI_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD7_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD8_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD8_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD9_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD9_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMDA_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMDA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_DMA_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_RD_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_WR_BUF_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_ST_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_ST_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_ST_SEG_MAGIC_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_ST_SLV_CMD_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_ST_SLV_CMD_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP2_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_ST_APP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.DMA_INT_ST.Reg, volatile.LoadUint32(&o.DMA_INT_ST.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_ST_APP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_ST.Reg) & 0x100000) >> 20 +} + +// SPI2.DMA_INT_SET: SPI interrupt software set register +func (o *SPI2_Type) SetDMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET() uint32 { + return volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x1 +} +func (o *SPI2_Type) SetDMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_EX_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_EX_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_EN_QPI_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_EN_QPI_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD7_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x10)|value<<4) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD7_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x10) >> 4 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD8_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x20)|value<<5) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD8_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x20) >> 5 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD9_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x40)|value<<6) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD9_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x40) >> 6 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMDA_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x80)|value<<7) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMDA_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x80) >> 7 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_RD_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_RD_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_WR_DMA_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_WR_DMA_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_RD_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_RD_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_WR_BUF_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_WR_BUF_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetDMA_INT_SET_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x1000)|value<<12) +} +func (o *SPI2_Type) GetDMA_INT_SET_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x1000) >> 12 +} +func (o *SPI2_Type) SetDMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x2000)|value<<13) +} +func (o *SPI2_Type) GetDMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x2000) >> 13 +} +func (o *SPI2_Type) SetDMA_INT_SET_SEG_MAGIC_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x4000)|value<<14) +} +func (o *SPI2_Type) GetDMA_INT_SET_SEG_MAGIC_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x4000) >> 14 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x8000)|value<<15) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x8000) >> 15 +} +func (o *SPI2_Type) SetDMA_INT_SET_SLV_CMD_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x10000)|value<<16) +} +func (o *SPI2_Type) GetDMA_INT_SET_SLV_CMD_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x10000) >> 16 +} +func (o *SPI2_Type) SetDMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x20000)|value<<17) +} +func (o *SPI2_Type) GetDMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x20000) >> 17 +} +func (o *SPI2_Type) SetDMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x40000)|value<<18) +} +func (o *SPI2_Type) GetDMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x40000) >> 18 +} +func (o *SPI2_Type) SetDMA_INT_SET_APP2_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x80000)|value<<19) +} +func (o *SPI2_Type) GetDMA_INT_SET_APP2_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x80000) >> 19 +} +func (o *SPI2_Type) SetDMA_INT_SET_APP1_INT_SET(value uint32) { + volatile.StoreUint32(&o.DMA_INT_SET.Reg, volatile.LoadUint32(&o.DMA_INT_SET.Reg)&^(0x100000)|value<<20) +} +func (o *SPI2_Type) GetDMA_INT_SET_APP1_INT_SET() uint32 { + return (volatile.LoadUint32(&o.DMA_INT_SET.Reg) & 0x100000) >> 20 +} + +// SPI2.W0: SPI CPU-controlled buffer0 +func (o *SPI2_Type) SetW0(value uint32) { + volatile.StoreUint32(&o.W0.Reg, value) +} +func (o *SPI2_Type) GetW0() uint32 { + return volatile.LoadUint32(&o.W0.Reg) +} + +// SPI2.W1: SPI CPU-controlled buffer1 +func (o *SPI2_Type) SetW1(value uint32) { + volatile.StoreUint32(&o.W1.Reg, value) +} +func (o *SPI2_Type) GetW1() uint32 { + return volatile.LoadUint32(&o.W1.Reg) +} + +// SPI2.W2: SPI CPU-controlled buffer2 +func (o *SPI2_Type) SetW2(value uint32) { + volatile.StoreUint32(&o.W2.Reg, value) +} +func (o *SPI2_Type) GetW2() uint32 { + return volatile.LoadUint32(&o.W2.Reg) +} + +// SPI2.W3: SPI CPU-controlled buffer3 +func (o *SPI2_Type) SetW3(value uint32) { + volatile.StoreUint32(&o.W3.Reg, value) +} +func (o *SPI2_Type) GetW3() uint32 { + return volatile.LoadUint32(&o.W3.Reg) +} + +// SPI2.W4: SPI CPU-controlled buffer4 +func (o *SPI2_Type) SetW4(value uint32) { + volatile.StoreUint32(&o.W4.Reg, value) +} +func (o *SPI2_Type) GetW4() uint32 { + return volatile.LoadUint32(&o.W4.Reg) +} + +// SPI2.W5: SPI CPU-controlled buffer5 +func (o *SPI2_Type) SetW5(value uint32) { + volatile.StoreUint32(&o.W5.Reg, value) +} +func (o *SPI2_Type) GetW5() uint32 { + return volatile.LoadUint32(&o.W5.Reg) +} + +// SPI2.W6: SPI CPU-controlled buffer6 +func (o *SPI2_Type) SetW6(value uint32) { + volatile.StoreUint32(&o.W6.Reg, value) +} +func (o *SPI2_Type) GetW6() uint32 { + return volatile.LoadUint32(&o.W6.Reg) +} + +// SPI2.W7: SPI CPU-controlled buffer7 +func (o *SPI2_Type) SetW7(value uint32) { + volatile.StoreUint32(&o.W7.Reg, value) +} +func (o *SPI2_Type) GetW7() uint32 { + return volatile.LoadUint32(&o.W7.Reg) +} + +// SPI2.W8: SPI CPU-controlled buffer8 +func (o *SPI2_Type) SetW8(value uint32) { + volatile.StoreUint32(&o.W8.Reg, value) +} +func (o *SPI2_Type) GetW8() uint32 { + return volatile.LoadUint32(&o.W8.Reg) +} + +// SPI2.W9: SPI CPU-controlled buffer9 +func (o *SPI2_Type) SetW9(value uint32) { + volatile.StoreUint32(&o.W9.Reg, value) +} +func (o *SPI2_Type) GetW9() uint32 { + return volatile.LoadUint32(&o.W9.Reg) +} + +// SPI2.W10: SPI CPU-controlled buffer10 +func (o *SPI2_Type) SetW10(value uint32) { + volatile.StoreUint32(&o.W10.Reg, value) +} +func (o *SPI2_Type) GetW10() uint32 { + return volatile.LoadUint32(&o.W10.Reg) +} + +// SPI2.W11: SPI CPU-controlled buffer11 +func (o *SPI2_Type) SetW11(value uint32) { + volatile.StoreUint32(&o.W11.Reg, value) +} +func (o *SPI2_Type) GetW11() uint32 { + return volatile.LoadUint32(&o.W11.Reg) +} + +// SPI2.W12: SPI CPU-controlled buffer12 +func (o *SPI2_Type) SetW12(value uint32) { + volatile.StoreUint32(&o.W12.Reg, value) +} +func (o *SPI2_Type) GetW12() uint32 { + return volatile.LoadUint32(&o.W12.Reg) +} + +// SPI2.W13: SPI CPU-controlled buffer13 +func (o *SPI2_Type) SetW13(value uint32) { + volatile.StoreUint32(&o.W13.Reg, value) +} +func (o *SPI2_Type) GetW13() uint32 { + return volatile.LoadUint32(&o.W13.Reg) +} + +// SPI2.W14: SPI CPU-controlled buffer14 +func (o *SPI2_Type) SetW14(value uint32) { + volatile.StoreUint32(&o.W14.Reg, value) +} +func (o *SPI2_Type) GetW14() uint32 { + return volatile.LoadUint32(&o.W14.Reg) +} + +// SPI2.W15: SPI CPU-controlled buffer15 +func (o *SPI2_Type) SetW15(value uint32) { + volatile.StoreUint32(&o.W15.Reg, value) +} +func (o *SPI2_Type) GetW15() uint32 { + return volatile.LoadUint32(&o.W15.Reg) +} + +// SPI2.SLAVE: SPI slave control register +func (o *SPI2_Type) SetSLAVE_CLK_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3)|value) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE() uint32 { + return volatile.LoadUint32(&o.SLAVE.Reg) & 0x3 +} +func (o *SPI2_Type) SetSLAVE_CLK_MODE_13(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetSLAVE_CLK_MODE_13() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI2_Type) SetSLAVE_RSCK_DATA_OUT(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI2_Type) GetSLAVE_RSCK_DATA_OUT() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x100)|value<<8) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x100) >> 8 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRDMA_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x200)|value<<9) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRDMA_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x200) >> 9 +} +func (o *SPI2_Type) SetSLAVE_SLV_RDBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x400)|value<<10) +} +func (o *SPI2_Type) GetSLAVE_SLV_RDBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x400) >> 10 +} +func (o *SPI2_Type) SetSLAVE_SLV_WRBUF_BITLEN_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x800)|value<<11) +} +func (o *SPI2_Type) GetSLAVE_SLV_WRBUF_BITLEN_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x800) >> 11 +} +func (o *SPI2_Type) SetSLAVE_DMA_SEG_MAGIC_VALUE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x3c00000)|value<<22) +} +func (o *SPI2_Type) GetSLAVE_DMA_SEG_MAGIC_VALUE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x3c00000) >> 22 +} +func (o *SPI2_Type) SetSLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x4000000) >> 26 +} +func (o *SPI2_Type) SetSLAVE_SOFT_RESET(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI2_Type) GetSLAVE_SOFT_RESET() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI2_Type) SetSLAVE_USR_CONF(value uint32) { + volatile.StoreUint32(&o.SLAVE.Reg, volatile.LoadUint32(&o.SLAVE.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI2_Type) GetSLAVE_USR_CONF() uint32 { + return (volatile.LoadUint32(&o.SLAVE.Reg) & 0x10000000) >> 28 +} + +// SPI2.SLAVE1: SPI slave control register 1 +func (o *SPI2_Type) SetSLAVE1_SLV_DATA_BITLEN(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3ffff)|value) +} +func (o *SPI2_Type) GetSLAVE1_SLV_DATA_BITLEN() uint32 { + return volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3ffff +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_COMMAND(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0x3fc0000)|value<<18) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0x3fc0000) >> 18 +} +func (o *SPI2_Type) SetSLAVE1_SLV_LAST_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE1.Reg, volatile.LoadUint32(&o.SLAVE1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI2_Type) GetSLAVE1_SLV_LAST_ADDR() uint32 { + return (volatile.LoadUint32(&o.SLAVE1.Reg) & 0xfc000000) >> 26 +} + +// SPI2.CLK_GATE: SPI module clock and register clock control +func (o *SPI2_Type) SetCLK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x1)|value) +} +func (o *SPI2_Type) GetCLK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_ACTIVE(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x2)|value<<1) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_ACTIVE() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x2) >> 1 +} +func (o *SPI2_Type) SetCLK_GATE_MST_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x4)|value<<2) +} +func (o *SPI2_Type) GetCLK_GATE_MST_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x4) >> 2 +} + +// SPI2.DATE: Version control +func (o *SPI2_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SPI2_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// System Configuration Registers +type SYSTEM_Type struct { + CORE_1_CONTROL_0 volatile.Register32 // 0x0 + CORE_1_CONTROL_1 volatile.Register32 // 0x4 + CPU_PERI_CLK_EN volatile.Register32 // 0x8 + CPU_PERI_RST_EN volatile.Register32 // 0xC + CPU_PER_CONF volatile.Register32 // 0x10 + MEM_PD_MASK volatile.Register32 // 0x14 + PERIP_CLK_EN0 volatile.Register32 // 0x18 + PERIP_CLK_EN1 volatile.Register32 // 0x1C + PERIP_RST_EN0 volatile.Register32 // 0x20 + PERIP_RST_EN1 volatile.Register32 // 0x24 + BT_LPCK_DIV_INT volatile.Register32 // 0x28 + BT_LPCK_DIV_FRAC volatile.Register32 // 0x2C + CPU_INTR_FROM_CPU_0 volatile.Register32 // 0x30 + CPU_INTR_FROM_CPU_1 volatile.Register32 // 0x34 + CPU_INTR_FROM_CPU_2 volatile.Register32 // 0x38 + CPU_INTR_FROM_CPU_3 volatile.Register32 // 0x3C + RSA_PD_CTRL volatile.Register32 // 0x40 + EDMA_CTRL volatile.Register32 // 0x44 + CACHE_CONTROL volatile.Register32 // 0x48 + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL volatile.Register32 // 0x4C + RTC_FASTMEM_CONFIG volatile.Register32 // 0x50 + RTC_FASTMEM_CRC volatile.Register32 // 0x54 + REDUNDANT_ECO_CTRL volatile.Register32 // 0x58 + CLOCK_GATE volatile.Register32 // 0x5C + SYSCLK_CONF volatile.Register32 // 0x60 + MEM_PVT volatile.Register32 // 0x64 + COMB_PVT_LVT_CONF volatile.Register32 // 0x68 + COMB_PVT_NVT_CONF volatile.Register32 // 0x6C + COMB_PVT_HVT_CONF volatile.Register32 // 0x70 + COMB_PVT_ERR_LVT_SITE0 volatile.Register32 // 0x74 + COMB_PVT_ERR_NVT_SITE0 volatile.Register32 // 0x78 + COMB_PVT_ERR_HVT_SITE0 volatile.Register32 // 0x7C + COMB_PVT_ERR_LVT_SITE1 volatile.Register32 // 0x80 + COMB_PVT_ERR_NVT_SITE1 volatile.Register32 // 0x84 + COMB_PVT_ERR_HVT_SITE1 volatile.Register32 // 0x88 + COMB_PVT_ERR_LVT_SITE2 volatile.Register32 // 0x8C + COMB_PVT_ERR_NVT_SITE2 volatile.Register32 // 0x90 + COMB_PVT_ERR_HVT_SITE2 volatile.Register32 // 0x94 + COMB_PVT_ERR_LVT_SITE3 volatile.Register32 // 0x98 + COMB_PVT_ERR_NVT_SITE3 volatile.Register32 // 0x9C + COMB_PVT_ERR_HVT_SITE3 volatile.Register32 // 0xA0 + _ [3928]byte + DATE volatile.Register32 // 0xFFC +} + +// SYSTEM.CORE_1_CONTROL_0: Core0 control regiter 0 +func (o *SYSTEM_Type) SetCORE_1_CONTROL_0_CONTROL_CORE_1_RUNSTALL(value uint32) { + volatile.StoreUint32(&o.CORE_1_CONTROL_0.Reg, volatile.LoadUint32(&o.CORE_1_CONTROL_0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCORE_1_CONTROL_0_CONTROL_CORE_1_RUNSTALL() uint32 { + return volatile.LoadUint32(&o.CORE_1_CONTROL_0.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetCORE_1_CONTROL_0_CONTROL_CORE_1_CLKGATE_EN(value uint32) { + volatile.StoreUint32(&o.CORE_1_CONTROL_0.Reg, volatile.LoadUint32(&o.CORE_1_CONTROL_0.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetCORE_1_CONTROL_0_CONTROL_CORE_1_CLKGATE_EN() uint32 { + return (volatile.LoadUint32(&o.CORE_1_CONTROL_0.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetCORE_1_CONTROL_0_CONTROL_CORE_1_RESETING(value uint32) { + volatile.StoreUint32(&o.CORE_1_CONTROL_0.Reg, volatile.LoadUint32(&o.CORE_1_CONTROL_0.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetCORE_1_CONTROL_0_CONTROL_CORE_1_RESETING() uint32 { + return (volatile.LoadUint32(&o.CORE_1_CONTROL_0.Reg) & 0x4) >> 2 +} + +// SYSTEM.CORE_1_CONTROL_1: Core0 control regiter 1 +func (o *SYSTEM_Type) SetCORE_1_CONTROL_1(value uint32) { + volatile.StoreUint32(&o.CORE_1_CONTROL_1.Reg, value) +} +func (o *SYSTEM_Type) GetCORE_1_CONTROL_1() uint32 { + return volatile.LoadUint32(&o.CORE_1_CONTROL_1.Reg) +} + +// SYSTEM.CPU_PERI_CLK_EN: cpu_peripheral clock configuration register +func (o *SYSTEM_Type) SetCPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_CLK_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetCPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_CLK_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_CLK_EN.Reg) & 0x80) >> 7 +} + +// SYSTEM.CPU_PERI_RST_EN: cpu_peripheral reset configuration regsiter +func (o *SYSTEM_Type) SetCPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_RST_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetCPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO(value uint32) { + volatile.StoreUint32(&o.CPU_PERI_RST_EN.Reg, volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetCPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO() uint32 { + return (volatile.LoadUint32(&o.CPU_PERI_RST_EN.Reg) & 0x80) >> 7 +} + +// SYSTEM.CPU_PER_CONF: cpu peripheral clock configuration register +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPUPERIOD_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x3)|value) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPUPERIOD_SEL() uint32 { + return volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x3 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_PLL_FREQ_SEL(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_PLL_FREQ_SEL() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetCPU_PER_CONF_CPU_WAITI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.CPU_PER_CONF.Reg, volatile.LoadUint32(&o.CPU_PER_CONF.Reg)&^(0xf0)|value<<4) +} +func (o *SYSTEM_Type) GetCPU_PER_CONF_CPU_WAITI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.CPU_PER_CONF.Reg) & 0xf0) >> 4 +} + +// SYSTEM.MEM_PD_MASK: memory power down mask configuration register +func (o *SYSTEM_Type) SetMEM_PD_MASK_LSLP_MEM_PD_MASK(value uint32) { + volatile.StoreUint32(&o.MEM_PD_MASK.Reg, volatile.LoadUint32(&o.MEM_PD_MASK.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetMEM_PD_MASK_LSLP_MEM_PD_MASK() uint32 { + return volatile.LoadUint32(&o.MEM_PD_MASK.Reg) & 0x1 +} + +// SYSTEM.PERIP_CLK_EN0: peripheral clock configuration regsiter 0 +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERS_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI01_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI01_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_WDG_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_WDG_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2S0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2S0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2C_EXT0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2C_EXT0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UHCI0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UHCI0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_RMT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_RMT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PCNT_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PCNT_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x400) >> 10 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_LEDC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x800)|value<<11) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_LEDC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x800) >> 11 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UHCI1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UHCI1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1000) >> 12 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERGROUP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERGROUP_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2000) >> 13 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_EFUSE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4000)|value<<14) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_EFUSE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4000) >> 14 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TIMERGROUP1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x8000)|value<<15) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TIMERGROUP1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x8000) >> 15 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10000) >> 16 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20000) >> 17 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2C_EXT1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2C_EXT1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40000) >> 18 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_TWAI_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_TWAI_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80000) >> 19 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x100000) >> 20 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_I2S1_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_I2S1_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x200000) >> 21 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI2_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI2_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x400000) >> 22 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_USB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_USB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x800000) >> 23 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_UART_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_UART_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_PWM3_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_PWM3_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI3_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI3_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_APB_SARADC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_APB_SARADC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x10000000) >> 28 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SYSTIMER_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SYSTIMER_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x20000000) >> 29 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_ADC2_ARB_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_ADC2_ARB_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x40000000) >> 30 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN0_SPI4_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN0.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN0_SPI4_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN0.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.PERIP_CLK_EN1: peripheral clock configuration regsiter 1 +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_PERI_BACKUP_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_PERI_BACKUP_CLK_EN() uint32 { + return volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_AES_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_AES_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_SHA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_SHA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_RSA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_RSA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_DS_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_DS_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_DMA_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_DMA_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_SDIO_HOST_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_SDIO_HOST_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_LCD_CAM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_LCD_CAM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_UART2_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_UART2_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_CLK_EN1_USB_DEVICE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.PERIP_CLK_EN1.Reg, volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_CLK_EN1_USB_DEVICE_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.PERIP_CLK_EN1.Reg) & 0x400) >> 10 +} + +// SYSTEM.PERIP_RST_EN0: peripheral reset configuration register0 +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERS_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERS_RST() uint32 { + return volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI01_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI01_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_WDG_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_WDG_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2S0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2S0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2C_EXT0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2C_EXT0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UHCI0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UHCI0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_RMT_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_RMT_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PCNT_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PCNT_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x400) >> 10 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_LEDC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x800)|value<<11) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_LEDC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x800) >> 11 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UHCI1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1000)|value<<12) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UHCI1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1000) >> 12 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERGROUP_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2000)|value<<13) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERGROUP_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2000) >> 13 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_EFUSE_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4000)|value<<14) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_EFUSE_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4000) >> 14 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TIMERGROUP1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x8000)|value<<15) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TIMERGROUP1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x8000) >> 15 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI3_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10000)|value<<16) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI3_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10000) >> 16 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM0_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20000)|value<<17) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM0_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20000) >> 17 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2C_EXT1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40000)|value<<18) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2C_EXT1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40000) >> 18 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_TWAI_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_TWAI_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80000) >> 19 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x100000)|value<<20) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x100000) >> 20 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_I2S1_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x200000)|value<<21) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_I2S1_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x200000) >> 21 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI2_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI2_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x400000) >> 22 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_USB_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_USB_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x800000) >> 23 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_UART_MEM_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_UART_MEM_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_PWM3_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_PWM3_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI3_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI3_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_APB_SARADC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_APB_SARADC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x10000000) >> 28 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SYSTIMER_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SYSTIMER_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x20000000) >> 29 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_ADC2_ARB_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_ADC2_ARB_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x40000000) >> 30 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN0_SPI4_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN0.Reg, volatile.LoadUint32(&o.PERIP_RST_EN0.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN0_SPI4_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN0.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.PERIP_RST_EN1: peripheral reset configuration regsiter 1 +func (o *SYSTEM_Type) SetPERIP_RST_EN1_PERI_BACKUP_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_PERI_BACKUP_RST() uint32 { + return volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_AES_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_AES_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_SHA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_SHA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_RSA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_RSA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x8) >> 3 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_DS_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_DS_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_CRYPTO_HMAC_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_CRYPTO_HMAC_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_DMA_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_DMA_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x40) >> 6 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_SDIO_HOST_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x80)|value<<7) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_SDIO_HOST_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x80) >> 7 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_LCD_CAM_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_LCD_CAM_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_UART2_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x200)|value<<9) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_UART2_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x200) >> 9 +} +func (o *SYSTEM_Type) SetPERIP_RST_EN1_USB_DEVICE_RST(value uint32) { + volatile.StoreUint32(&o.PERIP_RST_EN1.Reg, volatile.LoadUint32(&o.PERIP_RST_EN1.Reg)&^(0x400)|value<<10) +} +func (o *SYSTEM_Type) GetPERIP_RST_EN1_USB_DEVICE_RST() uint32 { + return (volatile.LoadUint32(&o.PERIP_RST_EN1.Reg) & 0x400) >> 10 +} + +// SYSTEM.BT_LPCK_DIV_INT: low power clock frequent division factor configuration regsiter +func (o *SYSTEM_Type) SetBT_LPCK_DIV_INT_BT_LPCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_INT.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg)&^(0xfff)|value) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_INT_BT_LPCK_DIV_NUM() uint32 { + return volatile.LoadUint32(&o.BT_LPCK_DIV_INT.Reg) & 0xfff +} + +// SYSTEM.BT_LPCK_DIV_FRAC: low power clock configuration register +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_B(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0xfff)|value) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_B() uint32 { + return volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0xfff +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_A(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0xfff000)|value<<12) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_BT_LPCK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0xfff000) >> 12 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x1000000) >> 24 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_8M() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x2000000) >> 25 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x4000000) >> 26 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x8000000) >> 27 +} +func (o *SYSTEM_Type) SetBT_LPCK_DIV_FRAC_LPCLK_RTC_EN(value uint32) { + volatile.StoreUint32(&o.BT_LPCK_DIV_FRAC.Reg, volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTEM_Type) GetBT_LPCK_DIV_FRAC_LPCLK_RTC_EN() uint32 { + return (volatile.LoadUint32(&o.BT_LPCK_DIV_FRAC.Reg) & 0x10000000) >> 28 +} + +// SYSTEM.CPU_INTR_FROM_CPU_0: interrupt source register 0 +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_0(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_0() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_1: interrupt source register 1 +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_1(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_1() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_2: interrupt source register 2 +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_2(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_2() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg) & 0x1 +} + +// SYSTEM.CPU_INTR_FROM_CPU_3: interrupt source register 3 +func (o *SYSTEM_Type) SetCPU_INTR_FROM_CPU_3(value uint32) { + volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCPU_INTR_FROM_CPU_3() uint32 { + return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg) & 0x1 +} + +// SYSTEM.RSA_PD_CTRL: rsa memory power control register +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_PD() uint32 { + return volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x4) >> 2 +} + +// SYSTEM.EDMA_CTRL: EDMA control register +func (o *SYSTEM_Type) SetEDMA_CTRL_EDMA_CLK_ON(value uint32) { + volatile.StoreUint32(&o.EDMA_CTRL.Reg, volatile.LoadUint32(&o.EDMA_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetEDMA_CTRL_EDMA_CLK_ON() uint32 { + return volatile.LoadUint32(&o.EDMA_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetEDMA_CTRL_EDMA_RESET(value uint32) { + volatile.StoreUint32(&o.EDMA_CTRL.Reg, volatile.LoadUint32(&o.EDMA_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetEDMA_CTRL_EDMA_RESET() uint32 { + return (volatile.LoadUint32(&o.EDMA_CTRL.Reg) & 0x2) >> 1 +} + +// SYSTEM.CACHE_CONTROL: Cache control register +func (o *SYSTEM_Type) SetCACHE_CONTROL_ICACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_ICACHE_CLK_ON() uint32 { + return volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_ICACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_ICACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_DCACHE_CLK_ON(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_DCACHE_CLK_ON() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetCACHE_CONTROL_DCACHE_RESET(value uint32) { + volatile.StoreUint32(&o.CACHE_CONTROL.Reg, volatile.LoadUint32(&o.CACHE_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetCACHE_CONTROL_DCACHE_RESET() uint32 { + return (volatile.LoadUint32(&o.CACHE_CONTROL.Reg) & 0x8) >> 3 +} + +// SYSTEM.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: External memory encrypt and decrypt control register +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT() uint32 { + return volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x2) >> 1 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x4)|value<<2) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x4) >> 2 +} +func (o *SYSTEM_Type) SetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT(value uint32) { + volatile.StoreUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg, volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg)&^(0x8)|value<<3) +} +func (o *SYSTEM_Type) GetEXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT() uint32 { + return (volatile.LoadUint32(&o.EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL.Reg) & 0x8) >> 3 +} + +// SYSTEM.RTC_FASTMEM_CONFIG: RTC fast memory configuration register +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_START(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x100)|value<<8) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_START() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x100) >> 8 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0xffe00)|value<<9) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0xffe00) >> 9 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x7ff00000)|value<<20) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x7ff00000) >> 20 +} +func (o *SYSTEM_Type) SetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CONFIG.Reg, volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH() uint32 { + return (volatile.LoadUint32(&o.RTC_FASTMEM_CONFIG.Reg) & 0x80000000) >> 31 +} + +// SYSTEM.RTC_FASTMEM_CRC: RTC fast memory CRC control register +func (o *SYSTEM_Type) SetRTC_FASTMEM_CRC(value uint32) { + volatile.StoreUint32(&o.RTC_FASTMEM_CRC.Reg, value) +} +func (o *SYSTEM_Type) GetRTC_FASTMEM_CRC() uint32 { + return volatile.LoadUint32(&o.RTC_FASTMEM_CRC.Reg) +} + +// SYSTEM.REDUNDANT_ECO_CTRL: ******* Description *********** +func (o *SYSTEM_Type) SetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE(value uint32) { + volatile.StoreUint32(&o.REDUNDANT_ECO_CTRL.Reg, volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE() uint32 { + return volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg) & 0x1 +} +func (o *SYSTEM_Type) SetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT(value uint32) { + volatile.StoreUint32(&o.REDUNDANT_ECO_CTRL.Reg, volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg)&^(0x2)|value<<1) +} +func (o *SYSTEM_Type) GetREDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT() uint32 { + return (volatile.LoadUint32(&o.REDUNDANT_ECO_CTRL.Reg) & 0x2) >> 1 +} + +// SYSTEM.CLOCK_GATE: ******* Description *********** +func (o *SYSTEM_Type) SetCLOCK_GATE_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value) +} +func (o *SYSTEM_Type) GetCLOCK_GATE_CLK_EN() uint32 { + return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1 +} + +// SYSTEM.SYSCLK_CONF: System clock configuration register. +func (o *SYSTEM_Type) SetSYSCLK_CONF_PRE_DIV_CNT(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x3ff)|value) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_PRE_DIV_CNT() uint32 { + return volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x3ff +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_SOC_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0xc00)|value<<10) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_SOC_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0xc00) >> 10 +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_CLK_XTAL_FREQ(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x7f000)|value<<12) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_CLK_XTAL_FREQ() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x7f000) >> 12 +} +func (o *SYSTEM_Type) SetSYSCLK_CONF_CLK_DIV_EN(value uint32) { + volatile.StoreUint32(&o.SYSCLK_CONF.Reg, volatile.LoadUint32(&o.SYSCLK_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *SYSTEM_Type) GetSYSCLK_CONF_CLK_DIV_EN() uint32 { + return (volatile.LoadUint32(&o.SYSCLK_CONF.Reg) & 0x80000) >> 19 +} + +// SYSTEM.MEM_PVT: ******* Description *********** +func (o *SYSTEM_Type) SetMEM_PVT_MEM_PATH_LEN(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0xf)|value) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_PATH_LEN() uint32 { + return volatile.LoadUint32(&o.MEM_PVT.Reg) & 0xf +} +func (o *SYSTEM_Type) SetMEM_PVT_MEM_ERR_CNT_CLR(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0x10)|value<<4) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_ERR_CNT_CLR() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0x10) >> 4 +} +func (o *SYSTEM_Type) SetMEM_PVT_MONITOR_EN(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetMEM_PVT_MONITOR_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetMEM_PVT_MEM_TIMING_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0x3fffc0)|value<<6) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_TIMING_ERR_CNT() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0x3fffc0) >> 6 +} +func (o *SYSTEM_Type) SetMEM_PVT_MEM_VT_SEL(value uint32) { + volatile.StoreUint32(&o.MEM_PVT.Reg, volatile.LoadUint32(&o.MEM_PVT.Reg)&^(0xc00000)|value<<22) +} +func (o *SYSTEM_Type) GetMEM_PVT_MEM_VT_SEL() uint32 { + return (volatile.LoadUint32(&o.MEM_PVT.Reg) & 0xc00000) >> 22 +} + +// SYSTEM.COMB_PVT_LVT_CONF: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_LVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg)&^(0x1f)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg) & 0x1f +} +func (o *SYSTEM_Type) SetCOMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_LVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetCOMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetCOMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_LVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCOMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_LVT_CONF.Reg) & 0x40) >> 6 +} + +// SYSTEM.COMB_PVT_NVT_CONF: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_NVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg)&^(0x1f)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg) & 0x1f +} +func (o *SYSTEM_Type) SetCOMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_NVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetCOMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetCOMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_NVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCOMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_NVT_CONF.Reg) & 0x40) >> 6 +} + +// SYSTEM.COMB_PVT_HVT_CONF: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_HVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg)&^(0x1f)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg) & 0x1f +} +func (o *SYSTEM_Type) SetCOMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_HVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg)&^(0x20)|value<<5) +} +func (o *SYSTEM_Type) GetCOMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg) & 0x20) >> 5 +} +func (o *SYSTEM_Type) SetCOMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_HVT_CONF.Reg, volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg)&^(0x40)|value<<6) +} +func (o *SYSTEM_Type) GetCOMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT() uint32 { + return (volatile.LoadUint32(&o.COMB_PVT_HVT_CONF.Reg) & 0x40) >> 6 +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE0: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE0.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE0.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE0.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE0: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE0.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE0.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE0.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE0: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE0.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE0.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE0.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE1: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE1.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE1.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE1.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE1: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE1.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE1.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE1.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE1: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE1.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE1.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE1.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE2: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE2.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE2.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE2.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE2: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE2.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE2.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE2.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE2: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE2.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE2.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE2.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_LVT_SITE3: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_LVT_SITE3.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE3.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_LVT_SITE3.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_NVT_SITE3: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_NVT_SITE3.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE3.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_NVT_SITE3.Reg) & 0xffff +} + +// SYSTEM.COMB_PVT_ERR_HVT_SITE3: ******* Description *********** +func (o *SYSTEM_Type) SetCOMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3(value uint32) { + volatile.StoreUint32(&o.COMB_PVT_ERR_HVT_SITE3.Reg, volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE3.Reg)&^(0xffff)|value) +} +func (o *SYSTEM_Type) GetCOMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3() uint32 { + return volatile.LoadUint32(&o.COMB_PVT_ERR_HVT_SITE3.Reg) & 0xffff +} + +// SYSTEM.DATE: version register +func (o *SYSTEM_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *SYSTEM_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// System Timer +type SYSTIMER_Type struct { + CONF volatile.Register32 // 0x0 + UNIT0_OP volatile.Register32 // 0x4 + UNIT1_OP volatile.Register32 // 0x8 + UNIT0_LOAD_HI volatile.Register32 // 0xC + UNIT0_LOAD_LO volatile.Register32 // 0x10 + UNIT1_LOAD_HI volatile.Register32 // 0x14 + UNIT1_LOAD_LO volatile.Register32 // 0x18 + TARGET0_HI volatile.Register32 // 0x1C + TARGET0_LO volatile.Register32 // 0x20 + TARGET1_HI volatile.Register32 // 0x24 + TARGET1_LO volatile.Register32 // 0x28 + TARGET2_HI volatile.Register32 // 0x2C + TARGET2_LO volatile.Register32 // 0x30 + TARGET0_CONF volatile.Register32 // 0x34 + TARGET1_CONF volatile.Register32 // 0x38 + TARGET2_CONF volatile.Register32 // 0x3C + UNIT0_VALUE_HI volatile.Register32 // 0x40 + UNIT0_VALUE_LO volatile.Register32 // 0x44 + UNIT1_VALUE_HI volatile.Register32 // 0x48 + UNIT1_VALUE_LO volatile.Register32 // 0x4C + COMP0_LOAD volatile.Register32 // 0x50 + COMP1_LOAD volatile.Register32 // 0x54 + COMP2_LOAD volatile.Register32 // 0x58 + UNIT0_LOAD volatile.Register32 // 0x5C + UNIT1_LOAD volatile.Register32 // 0x60 + INT_ENA volatile.Register32 // 0x64 + INT_RAW volatile.Register32 // 0x68 + INT_CLR volatile.Register32 // 0x6C + INT_ST volatile.Register32 // 0x70 + REAL_TARGET0_LO volatile.Register32 // 0x74 + REAL_TARGET0_HI volatile.Register32 // 0x78 + REAL_TARGET1_LO volatile.Register32 // 0x7C + REAL_TARGET1_HI volatile.Register32 // 0x80 + REAL_TARGET2_LO volatile.Register32 // 0x84 + REAL_TARGET2_HI volatile.Register32 // 0x88 + _ [112]byte + DATE volatile.Register32 // 0xFC +} + +// SYSTIMER.CONF: Configure system timer clock +func (o *SYSTIMER_Type) SetCONF_SYSTIMER_CLK_FO(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCONF_SYSTIMER_CLK_FO() uint32 { + return volatile.LoadUint32(&o.CONF.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetCONF_TARGET2_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22) +} +func (o *SYSTIMER_Type) GetCONF_TARGET2_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22 +} +func (o *SYSTIMER_Type) SetCONF_TARGET1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23) +} +func (o *SYSTIMER_Type) GetCONF_TARGET1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23 +} +func (o *SYSTIMER_Type) SetCONF_TARGET0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *SYSTIMER_Type) GetCONF_TARGET0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000000) >> 26 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE1_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE1_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000000) >> 27 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE0_STALL_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE0_STALL_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000000) >> 28 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_WORK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_WORK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetCONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetCONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_OP: system timer unit0 value update register +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT1_OP: system timer unit1 value update register +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_VALUE_VALID(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x20000000)|value<<29) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_VALUE_VALID() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x20000000) >> 29 +} +func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_UPDATE(value uint32) { + volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_UPDATE() uint32 { + return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x40000000) >> 30 +} + +// SYSTIMER.UNIT0_LOAD_HI: system timer unit0 value high load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_LOAD_LO: system timer unit0 value low load register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD_LO.Reg) +} + +// SYSTIMER.UNIT1_LOAD_HI: system timer unit1 value high load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_LOAD_LO: system timer unit1 value low load register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD_LO.Reg) +} + +// SYSTIMER.TARGET0_HI: system timer comp0 value high register +func (o *SYSTIMER_Type) SetTARGET0_HI_TIMER_TARGET0_HI(value uint32) { + volatile.StoreUint32(&o.TARGET0_HI.Reg, volatile.LoadUint32(&o.TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_HI_TIMER_TARGET0_HI() uint32 { + return volatile.LoadUint32(&o.TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET0_LO: system timer comp0 value low register +func (o *SYSTIMER_Type) SetTARGET0_LO(value uint32) { + volatile.StoreUint32(&o.TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET0_LO() uint32 { + return volatile.LoadUint32(&o.TARGET0_LO.Reg) +} + +// SYSTIMER.TARGET1_HI: system timer comp1 value high register +func (o *SYSTIMER_Type) SetTARGET1_HI_TIMER_TARGET1_HI(value uint32) { + volatile.StoreUint32(&o.TARGET1_HI.Reg, volatile.LoadUint32(&o.TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_HI_TIMER_TARGET1_HI() uint32 { + return volatile.LoadUint32(&o.TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET1_LO: system timer comp1 value low register +func (o *SYSTIMER_Type) SetTARGET1_LO(value uint32) { + volatile.StoreUint32(&o.TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET1_LO() uint32 { + return volatile.LoadUint32(&o.TARGET1_LO.Reg) +} + +// SYSTIMER.TARGET2_HI: system timer comp2 value high register +func (o *SYSTIMER_Type) SetTARGET2_HI_TIMER_TARGET2_HI(value uint32) { + volatile.StoreUint32(&o.TARGET2_HI.Reg, volatile.LoadUint32(&o.TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_HI_TIMER_TARGET2_HI() uint32 { + return volatile.LoadUint32(&o.TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.TARGET2_LO: system timer comp2 value low register +func (o *SYSTIMER_Type) SetTARGET2_LO(value uint32) { + volatile.StoreUint32(&o.TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetTARGET2_LO() uint32 { + return volatile.LoadUint32(&o.TARGET2_LO.Reg) +} + +// SYSTIMER.TARGET0_CONF: system timer comp0 target mode register +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET1_CONF: system timer comp1 target mode register +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.TARGET2_CONF: system timer comp2 target mode register +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x3ffffff)|value) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD() uint32 { + return volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x3ffffff +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD_MODE(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x40000000)|value<<30) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD_MODE() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x40000000) >> 30 +} +func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL(value uint32) { + volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL() uint32 { + return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x80000000) >> 31 +} + +// SYSTIMER.UNIT0_VALUE_HI: system timer unit0 value high register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT0_VALUE_LO: system timer unit0 value low register +func (o *SYSTIMER_Type) SetUNIT0_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT0_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT0_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT0_VALUE_LO.Reg) +} + +// SYSTIMER.UNIT1_VALUE_HI: system timer unit1 value high register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg) & 0xfffff +} + +// SYSTIMER.UNIT1_VALUE_LO: system timer unit1 value low register +func (o *SYSTIMER_Type) SetUNIT1_VALUE_LO(value uint32) { + volatile.StoreUint32(&o.UNIT1_VALUE_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetUNIT1_VALUE_LO() uint32 { + return volatile.LoadUint32(&o.UNIT1_VALUE_LO.Reg) +} + +// SYSTIMER.COMP0_LOAD: system timer comp0 conf sync register +func (o *SYSTIMER_Type) SetCOMP0_LOAD_TIMER_COMP0_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP0_LOAD.Reg, volatile.LoadUint32(&o.COMP0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP0_LOAD_TIMER_COMP0_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP1_LOAD: system timer comp1 conf sync register +func (o *SYSTIMER_Type) SetCOMP1_LOAD_TIMER_COMP1_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP1_LOAD.Reg, volatile.LoadUint32(&o.COMP1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP1_LOAD_TIMER_COMP1_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.COMP2_LOAD: system timer comp2 conf sync register +func (o *SYSTIMER_Type) SetCOMP2_LOAD_TIMER_COMP2_LOAD(value uint32) { + volatile.StoreUint32(&o.COMP2_LOAD.Reg, volatile.LoadUint32(&o.COMP2_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetCOMP2_LOAD_TIMER_COMP2_LOAD() uint32 { + return volatile.LoadUint32(&o.COMP2_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT0_LOAD: system timer unit0 conf sync register +func (o *SYSTIMER_Type) SetUNIT0_LOAD_TIMER_UNIT0_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT0_LOAD.Reg, volatile.LoadUint32(&o.UNIT0_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT0_LOAD_TIMER_UNIT0_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT0_LOAD.Reg) & 0x1 +} + +// SYSTIMER.UNIT1_LOAD: system timer unit1 conf sync register +func (o *SYSTIMER_Type) SetUNIT1_LOAD_TIMER_UNIT1_LOAD(value uint32) { + volatile.StoreUint32(&o.UNIT1_LOAD.Reg, volatile.LoadUint32(&o.UNIT1_LOAD.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetUNIT1_LOAD_TIMER_UNIT1_LOAD() uint32 { + return volatile.LoadUint32(&o.UNIT1_LOAD.Reg) & 0x1 +} + +// SYSTIMER.INT_ENA: systimer interrupt enable register +func (o *SYSTIMER_Type) SetINT_ENA_TARGET0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ENA_TARGET2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ENA_TARGET2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_RAW: systimer interrupt raw register +func (o *SYSTIMER_Type) SetINT_RAW_TARGET0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_RAW_TARGET2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_RAW_TARGET2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_CLR: systimer interrupt clear register +func (o *SYSTIMER_Type) SetINT_CLR_TARGET0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_CLR_TARGET2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_CLR_TARGET2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} + +// SYSTIMER.INT_ST: systimer interrupt status register +func (o *SYSTIMER_Type) SetINT_ST_TARGET0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *SYSTIMER_Type) SetINT_ST_TARGET2_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SYSTIMER_Type) GetINT_ST_TARGET2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} + +// SYSTIMER.REAL_TARGET0_LO: system timer comp0 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET0_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET0_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET0_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET0_LO.Reg) +} + +// SYSTIMER.REAL_TARGET0_HI: system timer comp0 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET0_HI_TARGET0_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET0_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET0_HI_TARGET0_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg) & 0xfffff +} + +// SYSTIMER.REAL_TARGET1_LO: system timer comp1 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET1_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET1_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET1_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET1_LO.Reg) +} + +// SYSTIMER.REAL_TARGET1_HI: system timer comp1 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET1_HI_TARGET1_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET1_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET1_HI_TARGET1_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg) & 0xfffff +} + +// SYSTIMER.REAL_TARGET2_LO: system timer comp2 actual target value low register +func (o *SYSTIMER_Type) SetREAL_TARGET2_LO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET2_LO.Reg, value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET2_LO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET2_LO.Reg) +} + +// SYSTIMER.REAL_TARGET2_HI: system timer comp2 actual target value high register +func (o *SYSTIMER_Type) SetREAL_TARGET2_HI_TARGET2_HI_RO(value uint32) { + volatile.StoreUint32(&o.REAL_TARGET2_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg)&^(0xfffff)|value) +} +func (o *SYSTIMER_Type) GetREAL_TARGET2_HI_TARGET2_HI_RO() uint32 { + return volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg) & 0xfffff +} + +// SYSTIMER.DATE: system timer version control register +func (o *SYSTIMER_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *SYSTIMER_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// Timer Group 0 +type TIMG_Type struct { + T0CONFIG volatile.Register32 // 0x0 + T0LO volatile.Register32 // 0x4 + T0HI volatile.Register32 // 0x8 + T0UPDATE volatile.Register32 // 0xC + T0ALARMLO volatile.Register32 // 0x10 + T0ALARMHI volatile.Register32 // 0x14 + T0LOADLO volatile.Register32 // 0x18 + T0LOADHI volatile.Register32 // 0x1C + T0LOAD volatile.Register32 // 0x20 + T1CONFIG volatile.Register32 // 0x24 + T1LO volatile.Register32 // 0x28 + T1HI volatile.Register32 // 0x2C + T1UPDATE volatile.Register32 // 0x30 + T1ALARMLO volatile.Register32 // 0x34 + T1ALARMHI volatile.Register32 // 0x38 + T1LOADLO volatile.Register32 // 0x3C + T1LOADHI volatile.Register32 // 0x40 + T1LOAD volatile.Register32 // 0x44 + WDTCONFIG0 volatile.Register32 // 0x48 + WDTCONFIG1 volatile.Register32 // 0x4C + WDTCONFIG2 volatile.Register32 // 0x50 + WDTCONFIG3 volatile.Register32 // 0x54 + WDTCONFIG4 volatile.Register32 // 0x58 + WDTCONFIG5 volatile.Register32 // 0x5C + WDTFEED volatile.Register32 // 0x60 + WDTWPROTECT volatile.Register32 // 0x64 + RTCCALICFG volatile.Register32 // 0x68 + RTCCALICFG1 volatile.Register32 // 0x6C + INT_ENA_TIMERS volatile.Register32 // 0x70 + INT_RAW_TIMERS volatile.Register32 // 0x74 + INT_ST_TIMERS volatile.Register32 // 0x78 + INT_CLR_TIMERS volatile.Register32 // 0x7C + RTCCALICFG2 volatile.Register32 // 0x80 + _ [116]byte + NTIMERS_DATE volatile.Register32 // 0xF8 + REGCLK volatile.Register32 // 0xFC +} + +// TIMG.T0CONFIG: Timer %s configuration register +func (o *TIMG_Type) SetT0CONFIG_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetT0CONFIG_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetT0CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT0CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT0CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT0CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT0CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT0CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT0CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT0CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT0CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0LO: Timer %s current value, low 32 bits +func (o *TIMG_Type) SetT0LO(value uint32) { + volatile.StoreUint32(&o.T0LO.Reg, value) +} +func (o *TIMG_Type) GetT0LO() uint32 { + return volatile.LoadUint32(&o.T0LO.Reg) +} + +// TIMG.T0HI: Timer %s current value, high 22 bits +func (o *TIMG_Type) SetT0HI_HI(value uint32) { + volatile.StoreUint32(&o.T0HI.Reg, volatile.LoadUint32(&o.T0HI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0HI_HI() uint32 { + return volatile.LoadUint32(&o.T0HI.Reg) & 0x3fffff +} + +// TIMG.T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG +func (o *TIMG_Type) SetT0UPDATE_UPDATE(value uint32) { + volatile.StoreUint32(&o.T0UPDATE.Reg, volatile.LoadUint32(&o.T0UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT0UPDATE_UPDATE() uint32 { + return (volatile.LoadUint32(&o.T0UPDATE.Reg) & 0x80000000) >> 31 +} + +// TIMG.T0ALARMLO: Timer %s alarm value, low 32 bits +func (o *TIMG_Type) SetT0ALARMLO(value uint32) { + volatile.StoreUint32(&o.T0ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT0ALARMLO() uint32 { + return volatile.LoadUint32(&o.T0ALARMLO.Reg) +} + +// TIMG.T0ALARMHI: Timer %s alarm value, high bits +func (o *TIMG_Type) SetT0ALARMHI_ALARM_HI(value uint32) { + volatile.StoreUint32(&o.T0ALARMHI.Reg, volatile.LoadUint32(&o.T0ALARMHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0ALARMHI_ALARM_HI() uint32 { + return volatile.LoadUint32(&o.T0ALARMHI.Reg) & 0x3fffff +} + +// TIMG.T0LOADLO: Timer %s reload value, low 32 bits +func (o *TIMG_Type) SetT0LOADLO(value uint32) { + volatile.StoreUint32(&o.T0LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT0LOADLO() uint32 { + return volatile.LoadUint32(&o.T0LOADLO.Reg) +} + +// TIMG.T0LOADHI: Timer %s reload value, high 22 bits +func (o *TIMG_Type) SetT0LOADHI_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.T0LOADHI.Reg, volatile.LoadUint32(&o.T0LOADHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT0LOADHI_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.T0LOADHI.Reg) & 0x3fffff +} + +// TIMG.T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG +func (o *TIMG_Type) SetT0LOAD(value uint32) { + volatile.StoreUint32(&o.T0LOAD.Reg, value) +} +func (o *TIMG_Type) GetT0LOAD() uint32 { + return volatile.LoadUint32(&o.T0LOAD.Reg) +} + +// TIMG.T1CONFIG: Timer %s configuration register +func (o *TIMG_Type) SetT1CONFIG_USE_XTAL(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x200)|value<<9) +} +func (o *TIMG_Type) GetT1CONFIG_USE_XTAL() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x200) >> 9 +} +func (o *TIMG_Type) SetT1CONFIG_ALARM_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x400)|value<<10) +} +func (o *TIMG_Type) GetT1CONFIG_ALARM_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x400) >> 10 +} +func (o *TIMG_Type) SetT1CONFIG_DIVIDER(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x1fffe000)|value<<13) +} +func (o *TIMG_Type) GetT1CONFIG_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x1fffe000) >> 13 +} +func (o *TIMG_Type) SetT1CONFIG_AUTORELOAD(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x20000000)|value<<29) +} +func (o *TIMG_Type) GetT1CONFIG_AUTORELOAD() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x20000000) >> 29 +} +func (o *TIMG_Type) SetT1CONFIG_INCREASE(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x40000000)|value<<30) +} +func (o *TIMG_Type) GetT1CONFIG_INCREASE() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x40000000) >> 30 +} +func (o *TIMG_Type) SetT1CONFIG_EN(value uint32) { + volatile.StoreUint32(&o.T1CONFIG.Reg, volatile.LoadUint32(&o.T1CONFIG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT1CONFIG_EN() uint32 { + return (volatile.LoadUint32(&o.T1CONFIG.Reg) & 0x80000000) >> 31 +} + +// TIMG.T1LO: Timer %s current value, low 32 bits +func (o *TIMG_Type) SetT1LO(value uint32) { + volatile.StoreUint32(&o.T1LO.Reg, value) +} +func (o *TIMG_Type) GetT1LO() uint32 { + return volatile.LoadUint32(&o.T1LO.Reg) +} + +// TIMG.T1HI: Timer %s current value, high 22 bits +func (o *TIMG_Type) SetT1HI_HI(value uint32) { + volatile.StoreUint32(&o.T1HI.Reg, volatile.LoadUint32(&o.T1HI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT1HI_HI() uint32 { + return volatile.LoadUint32(&o.T1HI.Reg) & 0x3fffff +} + +// TIMG.T1UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG +func (o *TIMG_Type) SetT1UPDATE_UPDATE(value uint32) { + volatile.StoreUint32(&o.T1UPDATE.Reg, volatile.LoadUint32(&o.T1UPDATE.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetT1UPDATE_UPDATE() uint32 { + return (volatile.LoadUint32(&o.T1UPDATE.Reg) & 0x80000000) >> 31 +} + +// TIMG.T1ALARMLO: Timer %s alarm value, low 32 bits +func (o *TIMG_Type) SetT1ALARMLO(value uint32) { + volatile.StoreUint32(&o.T1ALARMLO.Reg, value) +} +func (o *TIMG_Type) GetT1ALARMLO() uint32 { + return volatile.LoadUint32(&o.T1ALARMLO.Reg) +} + +// TIMG.T1ALARMHI: Timer %s alarm value, high bits +func (o *TIMG_Type) SetT1ALARMHI_ALARM_HI(value uint32) { + volatile.StoreUint32(&o.T1ALARMHI.Reg, volatile.LoadUint32(&o.T1ALARMHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT1ALARMHI_ALARM_HI() uint32 { + return volatile.LoadUint32(&o.T1ALARMHI.Reg) & 0x3fffff +} + +// TIMG.T1LOADLO: Timer %s reload value, low 32 bits +func (o *TIMG_Type) SetT1LOADLO(value uint32) { + volatile.StoreUint32(&o.T1LOADLO.Reg, value) +} +func (o *TIMG_Type) GetT1LOADLO() uint32 { + return volatile.LoadUint32(&o.T1LOADLO.Reg) +} + +// TIMG.T1LOADHI: Timer %s reload value, high 22 bits +func (o *TIMG_Type) SetT1LOADHI_LOAD_HI(value uint32) { + volatile.StoreUint32(&o.T1LOADHI.Reg, volatile.LoadUint32(&o.T1LOADHI.Reg)&^(0x3fffff)|value) +} +func (o *TIMG_Type) GetT1LOADHI_LOAD_HI() uint32 { + return volatile.LoadUint32(&o.T1LOADHI.Reg) & 0x3fffff +} + +// TIMG.T1LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG +func (o *TIMG_Type) SetT1LOAD(value uint32) { + volatile.StoreUint32(&o.T1LOAD.Reg, value) +} +func (o *TIMG_Type) GetT1LOAD() uint32 { + return volatile.LoadUint32(&o.T1LOAD.Reg) +} + +// TIMG.WDTCONFIG0: Watchdog timer configuration register +func (o *TIMG_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x2000)|value<<13) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x2000) >> 13 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x4000)|value<<14) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x4000) >> 14 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x38000)|value<<15) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x38000) >> 15 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c0000)|value<<18) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c0000) >> 18 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1800000)|value<<23) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG3() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1800000) >> 23 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x6000000)|value<<25) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG2() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x6000000) >> 25 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG1(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x18000000)|value<<27) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG1() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x18000000) >> 27 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG0(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x60000000)|value<<29) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG0() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x60000000) >> 29 +} +func (o *TIMG_Type) SetWDTCONFIG0_WDT_EN(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetWDTCONFIG0_WDT_EN() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31 +} + +// TIMG.WDTCONFIG1: Watchdog timer prescaler register +func (o *TIMG_Type) SetWDTCONFIG1_WDT_CLK_PRESCALE(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0xffff0000)|value<<16) +} +func (o *TIMG_Type) GetWDTCONFIG1_WDT_CLK_PRESCALE() uint32 { + return (volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0xffff0000) >> 16 +} + +// TIMG.WDTCONFIG2: Watchdog timer stage 0 timeout value +func (o *TIMG_Type) SetWDTCONFIG2(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG2.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG2() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG2.Reg) +} + +// TIMG.WDTCONFIG3: Watchdog timer stage 1 timeout value +func (o *TIMG_Type) SetWDTCONFIG3(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG3.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG3() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG3.Reg) +} + +// TIMG.WDTCONFIG4: Watchdog timer stage 2 timeout value +func (o *TIMG_Type) SetWDTCONFIG4(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG4.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG4() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG4.Reg) +} + +// TIMG.WDTCONFIG5: Watchdog timer stage 3 timeout value +func (o *TIMG_Type) SetWDTCONFIG5(value uint32) { + volatile.StoreUint32(&o.WDTCONFIG5.Reg, value) +} +func (o *TIMG_Type) GetWDTCONFIG5() uint32 { + return volatile.LoadUint32(&o.WDTCONFIG5.Reg) +} + +// TIMG.WDTFEED: Write to feed the watchdog timer +func (o *TIMG_Type) SetWDTFEED(value uint32) { + volatile.StoreUint32(&o.WDTFEED.Reg, value) +} +func (o *TIMG_Type) GetWDTFEED() uint32 { + return volatile.LoadUint32(&o.WDTFEED.Reg) +} + +// TIMG.WDTWPROTECT: Watchdog write protect register +func (o *TIMG_Type) SetWDTWPROTECT(value uint32) { + volatile.StoreUint32(&o.WDTWPROTECT.Reg, value) +} +func (o *TIMG_Type) GetWDTWPROTECT() uint32 { + return volatile.LoadUint32(&o.WDTWPROTECT.Reg) +} + +// TIMG.RTCCALICFG: RTC calibration configure register +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START_CYCLING(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x1000)|value<<12) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START_CYCLING() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x1000) >> 12 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_CLK_SEL(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x6000)|value<<13) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_CLK_SEL() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x6000) >> 13 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_RDY(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x8000)|value<<15) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_RDY() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x8000) >> 15 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_MAX(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x7fff0000)|value<<16) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_MAX() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x7fff0000) >> 16 +} +func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x80000000) >> 31 +} + +// TIMG.RTCCALICFG1: RTC calibration configure1 register +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_VALUE(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_VALUE() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0xffffff80) >> 7 +} + +// TIMG.INT_ENA_TIMERS: Interrupt enable bits +func (o *TIMG_Type) SetINT_ENA_TIMERS_T0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_T1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_T1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_ENA_TIMERS_WDT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_ENA_TIMERS_WDT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x4) >> 2 +} + +// TIMG.INT_RAW_TIMERS: Raw interrupt status +func (o *TIMG_Type) SetINT_RAW_TIMERS_T0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_T1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_T1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_RAW_TIMERS_WDT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_RAW_TIMERS_WDT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x4) >> 2 +} + +// TIMG.INT_ST_TIMERS: Masked interrupt status +func (o *TIMG_Type) SetINT_ST_TIMERS_T0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T0_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_T1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_T1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_ST_TIMERS_WDT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_ST_TIMERS_WDT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x4) >> 2 +} + +// TIMG.INT_CLR_TIMERS: Interrupt clear bits +func (o *TIMG_Type) SetINT_CLR_TIMERS_T0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_T1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x2)|value<<1) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_T1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x2) >> 1 +} +func (o *TIMG_Type) SetINT_CLR_TIMERS_WDT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x4)|value<<2) +} +func (o *TIMG_Type) GetINT_CLR_TIMERS_WDT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x4) >> 2 +} + +// TIMG.RTCCALICFG2: Timer group calibration register +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x1)|value) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x1 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x78)|value<<3) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x78) >> 3 +} +func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES(value uint32) { + volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0xffffff80)|value<<7) +} +func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES() uint32 { + return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0xffffff80) >> 7 +} + +// TIMG.NTIMERS_DATE: Timer version control register +func (o *TIMG_Type) SetNTIMERS_DATE(value uint32) { + volatile.StoreUint32(&o.NTIMERS_DATE.Reg, volatile.LoadUint32(&o.NTIMERS_DATE.Reg)&^(0xfffffff)|value) +} +func (o *TIMG_Type) GetNTIMERS_DATE() uint32 { + return volatile.LoadUint32(&o.NTIMERS_DATE.Reg) & 0xfffffff +} + +// TIMG.REGCLK: Timer group clock gate register +func (o *TIMG_Type) SetREGCLK_CLK_EN(value uint32) { + volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x80000000)|value<<31) +} +func (o *TIMG_Type) GetREGCLK_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x80000000) >> 31 +} + +// Two-Wire Automotive Interface +type TWAI_Type struct { + MODE volatile.Register32 // 0x0 + CMD volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + INT_RAW volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + _ [4]byte + BUS_TIMING_0 volatile.Register32 // 0x18 + BUS_TIMING_1 volatile.Register32 // 0x1C + _ [12]byte + ARB_LOST_CAP volatile.Register32 // 0x2C + ERR_CODE_CAP volatile.Register32 // 0x30 + ERR_WARNING_LIMIT volatile.Register32 // 0x34 + RX_ERR_CNT volatile.Register32 // 0x38 + TX_ERR_CNT volatile.Register32 // 0x3C + DATA_0 volatile.Register32 // 0x40 + DATA_1 volatile.Register32 // 0x44 + DATA_2 volatile.Register32 // 0x48 + DATA_3 volatile.Register32 // 0x4C + DATA_4 volatile.Register32 // 0x50 + DATA_5 volatile.Register32 // 0x54 + DATA_6 volatile.Register32 // 0x58 + DATA_7 volatile.Register32 // 0x5C + DATA_8 volatile.Register32 // 0x60 + DATA_9 volatile.Register32 // 0x64 + DATA_10 volatile.Register32 // 0x68 + DATA_11 volatile.Register32 // 0x6C + DATA_12 volatile.Register32 // 0x70 + RX_MESSAGE_CNT volatile.Register32 // 0x74 + _ [4]byte + CLOCK_DIVIDER volatile.Register32 // 0x7C +} + +// TWAI.MODE: Mode Register +func (o *TWAI_Type) SetMODE_RESET_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetMODE_RESET_MODE() uint32 { + return volatile.LoadUint32(&o.MODE.Reg) & 0x1 +} +func (o *TWAI_Type) SetMODE_LISTEN_ONLY_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetMODE_LISTEN_ONLY_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetMODE_SELF_TEST_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetMODE_SELF_TEST_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetMODE_RX_FILTER_MODE(value uint32) { + volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetMODE_RX_FILTER_MODE() uint32 { + return (volatile.LoadUint32(&o.MODE.Reg) & 0x8) >> 3 +} + +// TWAI.CMD: Command Register +func (o *TWAI_Type) SetCMD_TX_REQ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetCMD_TX_REQ() uint32 { + return volatile.LoadUint32(&o.CMD.Reg) & 0x1 +} +func (o *TWAI_Type) SetCMD_ABORT_TX(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetCMD_ABORT_TX() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetCMD_RELEASE_BUF(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetCMD_RELEASE_BUF() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetCMD_CLR_OVERRUN(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetCMD_CLR_OVERRUN() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetCMD_SELF_RX_REQ(value uint32) { + volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetCMD_SELF_RX_REQ() uint32 { + return (volatile.LoadUint32(&o.CMD.Reg) & 0x10) >> 4 +} + +// TWAI.STATUS: Status register +func (o *TWAI_Type) SetSTATUS_RX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetSTATUS_RX_BUF_ST() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *TWAI_Type) SetSTATUS_OVERRUN_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetSTATUS_OVERRUN_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetSTATUS_TX_BUF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetSTATUS_TX_BUF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetSTATUS_TX_COMPLETE(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetSTATUS_TX_COMPLETE() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetSTATUS_RX_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *TWAI_Type) GetSTATUS_RX_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *TWAI_Type) SetSTATUS_TX_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetSTATUS_TX_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetSTATUS_ERR_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetSTATUS_ERR_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetSTATUS_BUS_OFF_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetSTATUS_BUS_OFF_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7 +} +func (o *TWAI_Type) SetSTATUS_MISS_ST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetSTATUS_MISS_ST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8 +} + +// TWAI.INT_RAW: Interrupt Register +func (o *TWAI_Type) SetINT_RAW_RX_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINT_RAW_RX_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *TWAI_Type) SetINT_RAW_TX_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINT_RAW_TX_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINT_RAW_ERR_WARN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINT_RAW_ERR_WARN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINT_RAW_OVERRUN_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINT_RAW_OVERRUN_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINT_RAW_ERR_PASSIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINT_RAW_ERR_PASSIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINT_RAW_ARB_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINT_RAW_ARB_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINT_RAW_BUS_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINT_RAW_BUS_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} + +// TWAI.INT_ENA: Interrupt Enable Register +func (o *TWAI_Type) SetINT_ENA_RX_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *TWAI_Type) GetINT_ENA_RX_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *TWAI_Type) SetINT_ENA_TX_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *TWAI_Type) GetINT_ENA_TX_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *TWAI_Type) SetINT_ENA_ERR_WARN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *TWAI_Type) GetINT_ENA_ERR_WARN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *TWAI_Type) SetINT_ENA_OVERRUN_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *TWAI_Type) GetINT_ENA_OVERRUN_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *TWAI_Type) SetINT_ENA_ERR_PASSIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetINT_ENA_ERR_PASSIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetINT_ENA_ARB_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *TWAI_Type) GetINT_ENA_ARB_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *TWAI_Type) SetINT_ENA_BUS_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetINT_ENA_BUS_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} + +// TWAI.BUS_TIMING_0: Bus Timing Register 0 +func (o *TWAI_Type) SetBUS_TIMING_0_BAUD_PRESC(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0x3fff)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_0_BAUD_PRESC() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0x3fff +} +func (o *TWAI_Type) SetBUS_TIMING_0_SYNC_JUMP_WIDTH(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0xc000)|value<<14) +} +func (o *TWAI_Type) GetBUS_TIMING_0_SYNC_JUMP_WIDTH() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0xc000) >> 14 +} + +// TWAI.BUS_TIMING_1: Bus Timing Register 1 +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG1(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0xf)|value) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG1() uint32 { + return volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0xf +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEG2(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x70)|value<<4) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEG2() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x70) >> 4 +} +func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SAMP(value uint32) { + volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x80)|value<<7) +} +func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SAMP() uint32 { + return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x80) >> 7 +} + +// TWAI.ARB_LOST_CAP: Arbitration Lost Capture Register +func (o *TWAI_Type) SetARB_LOST_CAP(value uint32) { + volatile.StoreUint32(&o.ARB_LOST_CAP.Reg, volatile.LoadUint32(&o.ARB_LOST_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetARB_LOST_CAP() uint32 { + return volatile.LoadUint32(&o.ARB_LOST_CAP.Reg) & 0x1f +} + +// TWAI.ERR_CODE_CAP: Error Code Capture Register +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_SEGMENT(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x1f)|value) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_SEGMENT() uint32 { + return volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x1f +} +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_DIRECTION(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x20)|value<<5) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_DIRECTION() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x20) >> 5 +} +func (o *TWAI_Type) SetERR_CODE_CAP_ECC_TYPE(value uint32) { + volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0xc0)|value<<6) +} +func (o *TWAI_Type) GetERR_CODE_CAP_ECC_TYPE() uint32 { + return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0xc0) >> 6 +} + +// TWAI.ERR_WARNING_LIMIT: Error Warning Limit Register +func (o *TWAI_Type) SetERR_WARNING_LIMIT(value uint32) { + volatile.StoreUint32(&o.ERR_WARNING_LIMIT.Reg, volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetERR_WARNING_LIMIT() uint32 { + return volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg) & 0xff +} + +// TWAI.RX_ERR_CNT: Receive Error Counter Register +func (o *TWAI_Type) SetRX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.RX_ERR_CNT.Reg, volatile.LoadUint32(&o.RX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetRX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.RX_ERR_CNT.Reg) & 0xff +} + +// TWAI.TX_ERR_CNT: Transmit Error Counter Register +func (o *TWAI_Type) SetTX_ERR_CNT(value uint32) { + volatile.StoreUint32(&o.TX_ERR_CNT.Reg, volatile.LoadUint32(&o.TX_ERR_CNT.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetTX_ERR_CNT() uint32 { + return volatile.LoadUint32(&o.TX_ERR_CNT.Reg) & 0xff +} + +// TWAI.DATA_0: Data register 0 +func (o *TWAI_Type) SetDATA_0_TX_BYTE_0(value uint32) { + volatile.StoreUint32(&o.DATA_0.Reg, volatile.LoadUint32(&o.DATA_0.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_0_TX_BYTE_0() uint32 { + return volatile.LoadUint32(&o.DATA_0.Reg) & 0xff +} + +// TWAI.DATA_1: Data register 1 +func (o *TWAI_Type) SetDATA_1_TX_BYTE_1(value uint32) { + volatile.StoreUint32(&o.DATA_1.Reg, volatile.LoadUint32(&o.DATA_1.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_1_TX_BYTE_1() uint32 { + return volatile.LoadUint32(&o.DATA_1.Reg) & 0xff +} + +// TWAI.DATA_2: Data register 2 +func (o *TWAI_Type) SetDATA_2_TX_BYTE_2(value uint32) { + volatile.StoreUint32(&o.DATA_2.Reg, volatile.LoadUint32(&o.DATA_2.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_2_TX_BYTE_2() uint32 { + return volatile.LoadUint32(&o.DATA_2.Reg) & 0xff +} + +// TWAI.DATA_3: Data register 3 +func (o *TWAI_Type) SetDATA_3_TX_BYTE_3(value uint32) { + volatile.StoreUint32(&o.DATA_3.Reg, volatile.LoadUint32(&o.DATA_3.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_3_TX_BYTE_3() uint32 { + return volatile.LoadUint32(&o.DATA_3.Reg) & 0xff +} + +// TWAI.DATA_4: Data register 4 +func (o *TWAI_Type) SetDATA_4_TX_BYTE_4(value uint32) { + volatile.StoreUint32(&o.DATA_4.Reg, volatile.LoadUint32(&o.DATA_4.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_4_TX_BYTE_4() uint32 { + return volatile.LoadUint32(&o.DATA_4.Reg) & 0xff +} + +// TWAI.DATA_5: Data register 5 +func (o *TWAI_Type) SetDATA_5_TX_BYTE_5(value uint32) { + volatile.StoreUint32(&o.DATA_5.Reg, volatile.LoadUint32(&o.DATA_5.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_5_TX_BYTE_5() uint32 { + return volatile.LoadUint32(&o.DATA_5.Reg) & 0xff +} + +// TWAI.DATA_6: Data register 6 +func (o *TWAI_Type) SetDATA_6_TX_BYTE_6(value uint32) { + volatile.StoreUint32(&o.DATA_6.Reg, volatile.LoadUint32(&o.DATA_6.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_6_TX_BYTE_6() uint32 { + return volatile.LoadUint32(&o.DATA_6.Reg) & 0xff +} + +// TWAI.DATA_7: Data register 7 +func (o *TWAI_Type) SetDATA_7_TX_BYTE_7(value uint32) { + volatile.StoreUint32(&o.DATA_7.Reg, volatile.LoadUint32(&o.DATA_7.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_7_TX_BYTE_7() uint32 { + return volatile.LoadUint32(&o.DATA_7.Reg) & 0xff +} + +// TWAI.DATA_8: Data register 8 +func (o *TWAI_Type) SetDATA_8_TX_BYTE_8(value uint32) { + volatile.StoreUint32(&o.DATA_8.Reg, volatile.LoadUint32(&o.DATA_8.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_8_TX_BYTE_8() uint32 { + return volatile.LoadUint32(&o.DATA_8.Reg) & 0xff +} + +// TWAI.DATA_9: Data register 9 +func (o *TWAI_Type) SetDATA_9_TX_BYTE_9(value uint32) { + volatile.StoreUint32(&o.DATA_9.Reg, volatile.LoadUint32(&o.DATA_9.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_9_TX_BYTE_9() uint32 { + return volatile.LoadUint32(&o.DATA_9.Reg) & 0xff +} + +// TWAI.DATA_10: Data register 10 +func (o *TWAI_Type) SetDATA_10_TX_BYTE_10(value uint32) { + volatile.StoreUint32(&o.DATA_10.Reg, volatile.LoadUint32(&o.DATA_10.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_10_TX_BYTE_10() uint32 { + return volatile.LoadUint32(&o.DATA_10.Reg) & 0xff +} + +// TWAI.DATA_11: Data register 11 +func (o *TWAI_Type) SetDATA_11_TX_BYTE_11(value uint32) { + volatile.StoreUint32(&o.DATA_11.Reg, volatile.LoadUint32(&o.DATA_11.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_11_TX_BYTE_11() uint32 { + return volatile.LoadUint32(&o.DATA_11.Reg) & 0xff +} + +// TWAI.DATA_12: Data register 12 +func (o *TWAI_Type) SetDATA_12_TX_BYTE_12(value uint32) { + volatile.StoreUint32(&o.DATA_12.Reg, volatile.LoadUint32(&o.DATA_12.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetDATA_12_TX_BYTE_12() uint32 { + return volatile.LoadUint32(&o.DATA_12.Reg) & 0xff +} + +// TWAI.RX_MESSAGE_CNT: Receive Message Counter Register +func (o *TWAI_Type) SetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER(value uint32) { + volatile.StoreUint32(&o.RX_MESSAGE_CNT.Reg, volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg)&^(0x7f)|value) +} +func (o *TWAI_Type) GetRX_MESSAGE_CNT_RX_MESSAGE_COUNTER() uint32 { + return volatile.LoadUint32(&o.RX_MESSAGE_CNT.Reg) & 0x7f +} + +// TWAI.CLOCK_DIVIDER: Clock Divider register +func (o *TWAI_Type) SetCLOCK_DIVIDER_CD(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0xff)|value) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CD() uint32 { + return volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0xff +} +func (o *TWAI_Type) SetCLOCK_DIVIDER_CLOCK_OFF(value uint32) { + volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0x100)|value<<8) +} +func (o *TWAI_Type) GetCLOCK_DIVIDER_CLOCK_OFF() uint32 { + return (volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0x100) >> 8 +} + +// UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +type UART_Type struct { + FIFO volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + CLKDIV volatile.Register32 // 0x14 + RX_FILT volatile.Register32 // 0x18 + STATUS volatile.Register32 // 0x1C + CONF0 volatile.Register32 // 0x20 + CONF1 volatile.Register32 // 0x24 + LOWPULSE volatile.Register32 // 0x28 + HIGHPULSE volatile.Register32 // 0x2C + RXD_CNT volatile.Register32 // 0x30 + FLOW_CONF volatile.Register32 // 0x34 + SLEEP_CONF volatile.Register32 // 0x38 + SWFC_CONF0 volatile.Register32 // 0x3C + SWFC_CONF1 volatile.Register32 // 0x40 + TXBRK_CONF volatile.Register32 // 0x44 + IDLE_CONF volatile.Register32 // 0x48 + RS485_CONF volatile.Register32 // 0x4C + AT_CMD_PRECNT volatile.Register32 // 0x50 + AT_CMD_POSTCNT volatile.Register32 // 0x54 + AT_CMD_GAPTOUT volatile.Register32 // 0x58 + AT_CMD_CHAR volatile.Register32 // 0x5C + MEM_CONF volatile.Register32 // 0x60 + MEM_TX_STATUS volatile.Register32 // 0x64 + MEM_RX_STATUS volatile.Register32 // 0x68 + FSM_STATUS volatile.Register32 // 0x6C + POSPULSE volatile.Register32 // 0x70 + NEGPULSE volatile.Register32 // 0x74 + CLK_CONF volatile.Register32 // 0x78 + DATE volatile.Register32 // 0x7C + ID volatile.Register32 // 0x80 +} + +// UART.FIFO: FIFO data register +func (o *UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.FIFO.Reg) & 0xff +} + +// UART.INT_RAW: Raw interrupt status +func (o *UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_RAW_RS485_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_RAW_RS485_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_RAW_RS485_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_RAW_RS485_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_RAW_RS485_CLASH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_RAW_RS485_CLASH_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19 +} + +// UART.INT_ST: Masked interrupt status +func (o *UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ST_RS485_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ST_RS485_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ST_RS485_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ST_RS485_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ST_RS485_CLASH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ST_RS485_CLASH_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19 +} + +// UART.INT_ENA: Interrupt enable bits +func (o *UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_ENA_RS485_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_ENA_RS485_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_ENA_RS485_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_ENA_RS485_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_ENA_RS485_CLASH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_ENA_RS485_CLASH_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19 +} + +// UART.INT_CLR: Interrupt clear bits +func (o *UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetINT_CLR_RS485_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetINT_CLR_RS485_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetINT_CLR_RS485_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetINT_CLR_RS485_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetINT_CLR_RS485_CLASH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetINT_CLR_RS485_CLASH_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19 +} + +// UART.CLKDIV: Clock divider configuration +func (o *UART_Type) SetCLKDIV(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetCLKDIV() uint32 { + return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xfff +} +func (o *UART_Type) SetCLKDIV_FRAG(value uint32) { + volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xf00000)|value<<20) +} +func (o *UART_Type) GetCLKDIV_FRAG() uint32 { + return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xf00000) >> 20 +} + +// UART.RX_FILT: Rx Filter configuration +func (o *UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT() uint32 { + return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff +} +func (o *UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) { + volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 { + return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8 +} + +// UART.STATUS: UART status register +func (o *UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSTATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetSTATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetSTATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetSTATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetSTATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetSTATUS_RXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetSTATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ff0000)|value<<16) +} +func (o *UART_Type) GetSTATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3ff0000) >> 16 +} +func (o *UART_Type) SetSTATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART_Type) GetSTATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART_Type) SetSTATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetSTATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetSTATUS_TXD(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetSTATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31 +} + +// UART.CONF0: a +func (o *UART_Type) SetCONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetCONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UART_Type) SetCONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetCONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetCONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0xc)|value<<2) +} +func (o *UART_Type) GetCONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0xc) >> 2 +} +func (o *UART_Type) SetCONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x30)|value<<4) +} +func (o *UART_Type) GetCONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x30) >> 4 +} +func (o *UART_Type) SetCONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UART_Type) GetCONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UART_Type) SetCONF0_SW_DTR(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UART_Type) GetCONF0_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UART_Type) SetCONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UART_Type) GetCONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UART_Type) SetCONF0_IRDA_DPLX(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UART_Type) GetCONF0_IRDA_DPLX() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UART_Type) SetCONF0_IRDA_TX_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UART_Type) GetCONF0_IRDA_TX_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UART_Type) SetCONF0_IRDA_WCTL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UART_Type) GetCONF0_IRDA_WCTL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UART_Type) SetCONF0_IRDA_TX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UART_Type) GetCONF0_IRDA_TX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *UART_Type) SetCONF0_IRDA_RX_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *UART_Type) GetCONF0_IRDA_RX_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *UART_Type) SetCONF0_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UART_Type) GetCONF0_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *UART_Type) SetCONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UART_Type) GetCONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *UART_Type) SetCONF0_IRDA_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *UART_Type) GetCONF0_IRDA_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} +func (o *UART_Type) SetCONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART_Type) GetCONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART_Type) SetCONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART_Type) GetCONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART_Type) SetCONF0_RXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART_Type) GetCONF0_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART_Type) SetCONF0_CTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF0_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF0_DSR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF0_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetCONF0_TXD_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCONF0_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCONF0_RTS_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF0_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCONF0_DTR_INV(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCONF0_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCONF0_ERR_WR_MASK(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCONF0_ERR_WR_MASK() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCONF0_AUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCONF0_AUTOBAUD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000000) >> 27 +} +func (o *UART_Type) SetCONF0_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000000)|value<<28) +} +func (o *UART_Type) GetCONF0_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000000) >> 28 +} + +// UART.CONF1: Configuration register 1 +func (o *UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x3ff +} +func (o *UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xffc00)|value<<10) +} +func (o *UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0xffc00) >> 10 +} +func (o *UART_Type) SetCONF1_DIS_RX_DAT_OVF(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20) +} +func (o *UART_Type) GetCONF1_DIS_RX_DAT_OVF() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20 +} +func (o *UART_Type) SetCONF1_RX_TOUT_FLOW_DIS(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21) +} +func (o *UART_Type) GetCONF1_RX_TOUT_FLOW_DIS() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21 +} +func (o *UART_Type) SetCONF1_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCONF1_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCONF1_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCONF1_RX_TOUT_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x800000) >> 23 +} + +// UART.LOWPULSE: Autobaud minimum low pulse duration register +func (o *UART_Type) SetLOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.LOWPULSE.Reg, volatile.LoadUint32(&o.LOWPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetLOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.LOWPULSE.Reg) & 0xfff +} + +// UART.HIGHPULSE: Autobaud minimum high pulse duration register +func (o *UART_Type) SetHIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.HIGHPULSE.Reg, volatile.LoadUint32(&o.HIGHPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetHIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.HIGHPULSE.Reg) & 0xfff +} + +// UART.RXD_CNT: Autobaud edge change count register +func (o *UART_Type) SetRXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.RXD_CNT.Reg, volatile.LoadUint32(&o.RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetRXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.RXD_CNT.Reg) & 0x3ff +} + +// UART.FLOW_CONF: Software flow-control configuration +func (o *UART_Type) SetFLOW_CONF_SW_FLOW_CON_EN(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetFLOW_CONF_SW_FLOW_CON_EN() uint32 { + return volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetFLOW_CONF_XONOFF_DEL(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetFLOW_CONF_XONOFF_DEL() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetFLOW_CONF_FORCE_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetFLOW_CONF_FORCE_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XON(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XON() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetFLOW_CONF_SEND_XOFF(value uint32) { + volatile.StoreUint32(&o.FLOW_CONF.Reg, volatile.LoadUint32(&o.FLOW_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetFLOW_CONF_SEND_XOFF() uint32 { + return (volatile.LoadUint32(&o.FLOW_CONF.Reg) & 0x20) >> 5 +} + +// UART.SLEEP_CONF: Sleep-mode configuration +func (o *UART_Type) SetSLEEP_CONF_ACTIVE_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SLEEP_CONF.Reg, volatile.LoadUint32(&o.SLEEP_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSLEEP_CONF_ACTIVE_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SLEEP_CONF.Reg) & 0x3ff +} + +// UART.SWFC_CONF0: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF0_XOFF_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x3ff +} +func (o *UART_Type) SetSWFC_CONF0_XOFF_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF0.Reg, volatile.LoadUint32(&o.SWFC_CONF0.Reg)&^(0x3fc00)|value<<10) +} +func (o *UART_Type) GetSWFC_CONF0_XOFF_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF0.Reg) & 0x3fc00) >> 10 +} + +// UART.SWFC_CONF1: Software flow-control character configuration +func (o *UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 { + return volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0x3ff +} +func (o *UART_Type) SetSWFC_CONF1_XON_CHAR(value uint32) { + volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0x3fc00)|value<<10) +} +func (o *UART_Type) GetSWFC_CONF1_XON_CHAR() uint32 { + return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0x3fc00) >> 10 +} + +// UART.TXBRK_CONF: Tx Break character configuration +func (o *UART_Type) SetTXBRK_CONF_TX_BRK_NUM(value uint32) { + volatile.StoreUint32(&o.TXBRK_CONF.Reg, volatile.LoadUint32(&o.TXBRK_CONF.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetTXBRK_CONF_TX_BRK_NUM() uint32 { + return volatile.LoadUint32(&o.TXBRK_CONF.Reg) & 0xff +} + +// UART.IDLE_CONF: Frame-end idle configuration +func (o *UART_Type) SetIDLE_CONF_RX_IDLE_THRHD(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetIDLE_CONF_RX_IDLE_THRHD() uint32 { + return volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0x3ff +} +func (o *UART_Type) SetIDLE_CONF_TX_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.IDLE_CONF.Reg, volatile.LoadUint32(&o.IDLE_CONF.Reg)&^(0xffc00)|value<<10) +} +func (o *UART_Type) GetIDLE_CONF_TX_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.IDLE_CONF.Reg) & 0xffc00) >> 10 +} + +// UART.RS485_CONF: RS485 mode configuration +func (o *UART_Type) SetRS485_CONF_RS485_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x1)|value) +} +func (o *UART_Type) GetRS485_CONF_RS485_EN() uint32 { + return volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x1 +} +func (o *UART_Type) SetRS485_CONF_DL0_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UART_Type) GetRS485_CONF_DL0_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x2) >> 1 +} +func (o *UART_Type) SetRS485_CONF_DL1_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UART_Type) GetRS485_CONF_DL1_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x4) >> 2 +} +func (o *UART_Type) SetRS485_CONF_RS485TX_RX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UART_Type) GetRS485_CONF_RS485TX_RX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x8) >> 3 +} +func (o *UART_Type) SetRS485_CONF_RS485RXBY_TX_EN(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UART_Type) GetRS485_CONF_RS485RXBY_TX_EN() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x10) >> 4 +} +func (o *UART_Type) SetRS485_CONF_RS485_RX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UART_Type) GetRS485_CONF_RS485_RX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x20) >> 5 +} +func (o *UART_Type) SetRS485_CONF_RS485_TX_DLY_NUM(value uint32) { + volatile.StoreUint32(&o.RS485_CONF.Reg, volatile.LoadUint32(&o.RS485_CONF.Reg)&^(0x3c0)|value<<6) +} +func (o *UART_Type) GetRS485_CONF_RS485_TX_DLY_NUM() uint32 { + return (volatile.LoadUint32(&o.RS485_CONF.Reg) & 0x3c0) >> 6 +} + +// UART.AT_CMD_PRECNT: Pre-sequence timing configuration +func (o *UART_Type) SetAT_CMD_PRECNT_PRE_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_PRECNT.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_PRECNT_PRE_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_PRECNT.Reg) & 0xffff +} + +// UART.AT_CMD_POSTCNT: Post-sequence timing configuration +func (o *UART_Type) SetAT_CMD_POSTCNT_POST_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_POSTCNT.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_POSTCNT_POST_IDLE_NUM() uint32 { + return volatile.LoadUint32(&o.AT_CMD_POSTCNT.Reg) & 0xffff +} + +// UART.AT_CMD_GAPTOUT: Timeout configuration +func (o *UART_Type) SetAT_CMD_GAPTOUT_RX_GAP_TOUT(value uint32) { + volatile.StoreUint32(&o.AT_CMD_GAPTOUT.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg)&^(0xffff)|value) +} +func (o *UART_Type) GetAT_CMD_GAPTOUT_RX_GAP_TOUT() uint32 { + return volatile.LoadUint32(&o.AT_CMD_GAPTOUT.Reg) & 0xffff +} + +// UART.AT_CMD_CHAR: AT escape sequence detection configuration +func (o *UART_Type) SetAT_CMD_CHAR(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff)|value) +} +func (o *UART_Type) GetAT_CMD_CHAR() uint32 { + return volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff +} +func (o *UART_Type) SetAT_CMD_CHAR_CHAR_NUM(value uint32) { + volatile.StoreUint32(&o.AT_CMD_CHAR.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR.Reg)&^(0xff00)|value<<8) +} +func (o *UART_Type) GetAT_CMD_CHAR_CHAR_NUM() uint32 { + return (volatile.LoadUint32(&o.AT_CMD_CHAR.Reg) & 0xff00) >> 8 +} + +// UART.MEM_CONF: UART threshold and allocation configuration +func (o *UART_Type) SetMEM_CONF_RX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0xe)|value<<1) +} +func (o *UART_Type) GetMEM_CONF_RX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0xe) >> 1 +} +func (o *UART_Type) SetMEM_CONF_TX_SIZE(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x70)|value<<4) +} +func (o *UART_Type) GetMEM_CONF_TX_SIZE() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x70) >> 4 +} +func (o *UART_Type) SetMEM_CONF_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1ff80)|value<<7) +} +func (o *UART_Type) GetMEM_CONF_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1ff80) >> 7 +} +func (o *UART_Type) SetMEM_CONF_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x7fe0000)|value<<17) +} +func (o *UART_Type) GetMEM_CONF_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x7fe0000) >> 17 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x8000000) >> 27 +} +func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x10000000)|value<<28) +} +func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x10000000) >> 28 +} + +// UART.MEM_TX_STATUS: Tx-FIFO write and read offset address. +func (o *UART_Type) SetMEM_TX_STATUS_APB_TX_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetMEM_TX_STATUS_APB_TX_WADDR() uint32 { + return volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetMEM_TX_STATUS_TX_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *UART_Type) GetMEM_TX_STATUS_TX_RADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1ff800) >> 11 +} + +// UART.MEM_RX_STATUS: Rx-FIFO write and read offset address. +func (o *UART_Type) SetMEM_RX_STATUS_APB_RX_RADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x3ff)|value) +} +func (o *UART_Type) GetMEM_RX_STATUS_APB_RX_RADDR() uint32 { + return volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x3ff +} +func (o *UART_Type) SetMEM_RX_STATUS_RX_WADDR(value uint32) { + volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1ff800)|value<<11) +} +func (o *UART_Type) GetMEM_RX_STATUS_RX_WADDR() uint32 { + return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1ff800) >> 11 +} + +// UART.FSM_STATUS: UART transmit and receive status. +func (o *UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value) +} +func (o *UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 { + return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf +} +func (o *UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) { + volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4) +} +func (o *UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 { + return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4 +} + +// UART.POSPULSE: Autobaud high pulse register +func (o *UART_Type) SetPOSPULSE_POSEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.POSPULSE.Reg, volatile.LoadUint32(&o.POSPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetPOSPULSE_POSEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.POSPULSE.Reg) & 0xfff +} + +// UART.NEGPULSE: Autobaud low pulse register +func (o *UART_Type) SetNEGPULSE_NEGEDGE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.NEGPULSE.Reg, volatile.LoadUint32(&o.NEGPULSE.Reg)&^(0xfff)|value) +} +func (o *UART_Type) GetNEGPULSE_NEGEDGE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.NEGPULSE.Reg) & 0xfff +} + +// UART.CLK_CONF: UART core clock configuration +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f)|value) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_B() uint32 { + return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f +} +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_A() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc0) >> 6 +} +func (o *UART_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UART_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff000) >> 12 +} +func (o *UART_Type) SetCLK_CONF_SCLK_SEL(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x300000)|value<<20) +} +func (o *UART_Type) GetCLK_CONF_SCLK_SEL() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x300000) >> 20 +} +func (o *UART_Type) SetCLK_CONF_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *UART_Type) GetCLK_CONF_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x400000) >> 22 +} +func (o *UART_Type) SetCLK_CONF_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UART_Type) GetCLK_CONF_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x800000) >> 23 +} +func (o *UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24) +} +func (o *UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24 +} +func (o *UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25) +} +func (o *UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25 +} +func (o *UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26) +} +func (o *UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26 +} +func (o *UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) { + volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27) +} +func (o *UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 { + return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27 +} + +// UART.DATE: UART Version register +func (o *UART_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UART_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// UART.ID: UART ID register +func (o *UART_Type) SetID(value uint32) { + volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0x3fffffff)|value) +} +func (o *UART_Type) GetID() uint32 { + return volatile.LoadUint32(&o.ID.Reg) & 0x3fffffff +} +func (o *UART_Type) SetID_HIGH_SPEED(value uint32) { + volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0x40000000)|value<<30) +} +func (o *UART_Type) GetID_HIGH_SPEED() uint32 { + return (volatile.LoadUint32(&o.ID.Reg) & 0x40000000) >> 30 +} +func (o *UART_Type) SetID_REG_UPDATE(value uint32) { + volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0x80000000)|value<<31) +} +func (o *UART_Type) GetID_REG_UPDATE() uint32 { + return (volatile.LoadUint32(&o.ID.Reg) & 0x80000000) >> 31 +} + +// Universal Host Controller Interface 0 +type UHCI_Type struct { + CONF0 volatile.Register32 // 0x0 + INT_RAW volatile.Register32 // 0x4 + INT_ST volatile.Register32 // 0x8 + INT_ENA volatile.Register32 // 0xC + INT_CLR volatile.Register32 // 0x10 + APP_INT_SET volatile.Register32 // 0x14 + CONF1 volatile.Register32 // 0x18 + STATE0 volatile.Register32 // 0x1C + STATE1 volatile.Register32 // 0x20 + ESCAPE_CONF volatile.Register32 // 0x24 + HUNG_CONF volatile.Register32 // 0x28 + ACK_NUM volatile.Register32 // 0x2C + RX_HEAD volatile.Register32 // 0x30 + QUICK_SENT volatile.Register32 // 0x34 + REG_Q0_WORD0 volatile.Register32 // 0x38 + REG_Q0_WORD1 volatile.Register32 // 0x3C + REG_Q1_WORD0 volatile.Register32 // 0x40 + REG_Q1_WORD1 volatile.Register32 // 0x44 + REG_Q2_WORD0 volatile.Register32 // 0x48 + REG_Q2_WORD1 volatile.Register32 // 0x4C + REG_Q3_WORD0 volatile.Register32 // 0x50 + REG_Q3_WORD1 volatile.Register32 // 0x54 + REG_Q4_WORD0 volatile.Register32 // 0x58 + REG_Q4_WORD1 volatile.Register32 // 0x5C + REG_Q5_WORD0 volatile.Register32 // 0x60 + REG_Q5_WORD1 volatile.Register32 // 0x64 + REG_Q6_WORD0 volatile.Register32 // 0x68 + REG_Q6_WORD1 volatile.Register32 // 0x6C + ESC_CONF0 volatile.Register32 // 0x70 + ESC_CONF1 volatile.Register32 // 0x74 + ESC_CONF2 volatile.Register32 // 0x78 + ESC_CONF3 volatile.Register32 // 0x7C + PKT_THRES volatile.Register32 // 0x80 + DATE volatile.Register32 // 0x84 +} + +// UHCI.CONF0: UHCI configuration register +func (o *UHCI_Type) SetCONF0_TX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF0_TX_RST() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF0_RX_RST(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF0_RX_RST() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF0_UART0_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF0_UART0_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF0_UART1_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF0_UART1_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF0_UART2_CE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF0_UART2_CE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF0_SEPER_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF0_SEPER_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF0_HEAD_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetCONF0_HEAD_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetCONF0_CRC_REC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF0_CRC_REC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF0_UART_IDLE_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF0_UART_IDLE_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *UHCI_Type) SetCONF0_LEN_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *UHCI_Type) GetCONF0_LEN_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *UHCI_Type) SetCONF0_ENCODE_CRC_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *UHCI_Type) GetCONF0_ENCODE_CRC_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *UHCI_Type) SetCONF0_CLK_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetCONF0_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetCONF0_UART_RX_BRK_EOF_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *UHCI_Type) GetCONF0_UART_RX_BRK_EOF_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} + +// UHCI.INT_RAW: Raw interrupt status +func (o *UHCI_Type) SetINT_RAW_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_RAW_RX_START_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_RAW_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_RAW_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_RAW_SEND_S_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_RAW_SEND_S_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_RAW_SEND_A_REG_Q_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_RAW_SEND_A_REG_Q_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_RAW_APP_CTRL1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_RAW_APP_CTRL1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ST: Masked interrupt status +func (o *UHCI_Type) SetINT_ST_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ST_RX_START_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ST_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ST_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ST_SEND_S_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ST_SEND_S_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ST_SEND_A_REG_Q_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ST_SEND_A_REG_Q_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ST_OUTLINK_EOF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ST_OUTLINK_EOF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL0_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ST_APP_CTRL1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ST_APP_CTRL1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// UHCI.INT_ENA: Interrupt enable bits +func (o *UHCI_Type) SetINT_ENA_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_ENA_RX_START_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_ENA_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_ENA_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_ENA_SEND_S_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_ENA_SEND_S_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_ENA_SEND_A_REG_Q_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_ENA_SEND_A_REG_Q_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_ENA_OUTLINK_EOF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_ENA_OUTLINK_EOF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_ENA_APP_CTRL1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_ENA_APP_CTRL1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// UHCI.INT_CLR: Interrupt clear bits +func (o *UHCI_Type) SetINT_CLR_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetINT_CLR_RX_START_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *UHCI_Type) SetINT_CLR_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetINT_CLR_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetINT_CLR_SEND_S_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetINT_CLR_SEND_S_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetINT_CLR_SEND_A_REG_Q_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetINT_CLR_SEND_A_REG_Q_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetINT_CLR_OUTLINK_EOF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetINT_CLR_OUTLINK_EOF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetINT_CLR_APP_CTRL1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetINT_CLR_APP_CTRL1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// UHCI.APP_INT_SET: Software interrupt trigger source +func (o *UHCI_Type) SetAPP_INT_SET_APP_CTRL0_INT_SET(value uint32) { + volatile.StoreUint32(&o.APP_INT_SET.Reg, volatile.LoadUint32(&o.APP_INT_SET.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetAPP_INT_SET_APP_CTRL0_INT_SET() uint32 { + return volatile.LoadUint32(&o.APP_INT_SET.Reg) & 0x1 +} +func (o *UHCI_Type) SetAPP_INT_SET_APP_CTRL1_INT_SET(value uint32) { + volatile.StoreUint32(&o.APP_INT_SET.Reg, volatile.LoadUint32(&o.APP_INT_SET.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetAPP_INT_SET_APP_CTRL1_INT_SET() uint32 { + return (volatile.LoadUint32(&o.APP_INT_SET.Reg) & 0x2) >> 1 +} + +// UHCI.CONF1: UHCI configuration register +func (o *UHCI_Type) SetCONF1_CHECK_SUM_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetCONF1_CHECK_SUM_EN() uint32 { + return volatile.LoadUint32(&o.CONF1.Reg) & 0x1 +} +func (o *UHCI_Type) SetCONF1_CHECK_SEQ_EN(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetCONF1_CHECK_SEQ_EN() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetCONF1_CRC_DISABLE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetCONF1_CRC_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetCONF1_SAVE_HEAD(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetCONF1_SAVE_HEAD() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetCONF1_TX_CHECK_SUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetCONF1_TX_CHECK_SUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetCONF1_TX_ACK_NUM_RE(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetCONF1_TX_ACK_NUM_RE() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetCONF1_WAIT_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetCONF1_WAIT_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7 +} +func (o *UHCI_Type) SetCONF1_SW_START(value uint32) { + volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8) +} +func (o *UHCI_Type) GetCONF1_SW_START() uint32 { + return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8 +} + +// UHCI.STATE0: UHCI receive status +func (o *UHCI_Type) SetSTATE0_RX_ERR_CAUSE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE0_RX_ERR_CAUSE() uint32 { + return volatile.LoadUint32(&o.STATE0.Reg) & 0x7 +} +func (o *UHCI_Type) SetSTATE0_DECODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x38)|value<<3) +} +func (o *UHCI_Type) GetSTATE0_DECODE_STATE() uint32 { + return (volatile.LoadUint32(&o.STATE0.Reg) & 0x38) >> 3 +} + +// UHCI.STATE1: UHCI transmit status +func (o *UHCI_Type) SetSTATE1_ENCODE_STATE(value uint32) { + volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetSTATE1_ENCODE_STATE() uint32 { + return volatile.LoadUint32(&o.STATE1.Reg) & 0x7 +} + +// UHCI.ESCAPE_CONF: Escape character configuration +func (o *UHCI_Type) SetESCAPE_CONF_TX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x1)|value) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_C0_ESC_EN() uint32 { + return volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x2)|value<<1) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x2) >> 1 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x4)|value<<2) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x4) >> 2 +} +func (o *UHCI_Type) SetESCAPE_CONF_TX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetESCAPE_CONF_TX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_C0_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x10)|value<<4) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_C0_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x10) >> 4 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_DB_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x20)|value<<5) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_DB_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x20) >> 5 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_11_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x40)|value<<6) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_11_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x40) >> 6 +} +func (o *UHCI_Type) SetESCAPE_CONF_RX_13_ESC_EN(value uint32) { + volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetESCAPE_CONF_RX_13_ESC_EN() uint32 { + return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x80) >> 7 +} + +// UHCI.HUNG_CONF: Timeout configuration +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT() uint32 { + return volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700)|value<<8) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700) >> 8 +} +func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800) >> 11 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff000)|value<<12) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff000) >> 12 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700000)|value<<20) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700000) >> 20 +} +func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_ENA(value uint32) { + volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800000)|value<<23) +} +func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_ENA() uint32 { + return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800000) >> 23 +} + +// UHCI.ACK_NUM: UHCI ACK number configuration +func (o *UHCI_Type) SetACK_NUM(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetACK_NUM() uint32 { + return volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x7 +} +func (o *UHCI_Type) SetACK_NUM_LOAD(value uint32) { + volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetACK_NUM_LOAD() uint32 { + return (volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x8) >> 3 +} + +// UHCI.RX_HEAD: UHCI packet header register +func (o *UHCI_Type) SetRX_HEAD(value uint32) { + volatile.StoreUint32(&o.RX_HEAD.Reg, value) +} +func (o *UHCI_Type) GetRX_HEAD() uint32 { + return volatile.LoadUint32(&o.RX_HEAD.Reg) +} + +// UHCI.QUICK_SENT: UHCI quick send configuration register +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x7)|value) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_NUM() uint32 { + return volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x7 +} +func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x8)|value<<3) +} +func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x8) >> 3 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_NUM(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x70)|value<<4) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_NUM() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x70) >> 4 +} +func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_EN(value uint32) { + volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x80)|value<<7) +} +func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_EN() uint32 { + return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x80) >> 7 +} + +// UHCI.REG_Q0_WORD0: Q0_WORD0 quick_sent register +func (o *UHCI_Type) SetREG_Q0_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD0.Reg) +} + +// UHCI.REG_Q0_WORD1: Q0_WORD1 quick_sent register +func (o *UHCI_Type) SetREG_Q0_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q0_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q0_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q0_WORD1.Reg) +} + +// UHCI.REG_Q1_WORD0: Q1_WORD0 quick_sent register +func (o *UHCI_Type) SetREG_Q1_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD0.Reg) +} + +// UHCI.REG_Q1_WORD1: Q1_WORD1 quick_sent register +func (o *UHCI_Type) SetREG_Q1_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q1_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q1_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q1_WORD1.Reg) +} + +// UHCI.REG_Q2_WORD0: Q2_WORD0 quick_sent register +func (o *UHCI_Type) SetREG_Q2_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD0.Reg) +} + +// UHCI.REG_Q2_WORD1: Q2_WORD1 quick_sent register +func (o *UHCI_Type) SetREG_Q2_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q2_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q2_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q2_WORD1.Reg) +} + +// UHCI.REG_Q3_WORD0: Q3_WORD0 quick_sent register +func (o *UHCI_Type) SetREG_Q3_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD0.Reg) +} + +// UHCI.REG_Q3_WORD1: Q3_WORD1 quick_sent register +func (o *UHCI_Type) SetREG_Q3_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q3_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q3_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q3_WORD1.Reg) +} + +// UHCI.REG_Q4_WORD0: Q4_WORD0 quick_sent register +func (o *UHCI_Type) SetREG_Q4_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD0.Reg) +} + +// UHCI.REG_Q4_WORD1: Q4_WORD1 quick_sent register +func (o *UHCI_Type) SetREG_Q4_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q4_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q4_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q4_WORD1.Reg) +} + +// UHCI.REG_Q5_WORD0: Q5_WORD0 quick_sent register +func (o *UHCI_Type) SetREG_Q5_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD0.Reg) +} + +// UHCI.REG_Q5_WORD1: Q5_WORD1 quick_sent register +func (o *UHCI_Type) SetREG_Q5_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q5_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q5_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q5_WORD1.Reg) +} + +// UHCI.REG_Q6_WORD0: Q6_WORD0 quick_sent register +func (o *UHCI_Type) SetREG_Q6_WORD0(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD0.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD0() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD0.Reg) +} + +// UHCI.REG_Q6_WORD1: Q6_WORD1 quick_sent register +func (o *UHCI_Type) SetREG_Q6_WORD1(value uint32) { + volatile.StoreUint32(&o.REG_Q6_WORD1.Reg, value) +} +func (o *UHCI_Type) GetREG_Q6_WORD1() uint32 { + return volatile.LoadUint32(&o.REG_Q6_WORD1.Reg) +} + +// UHCI.ESC_CONF0: Escape sequence configuration register 0 +func (o *UHCI_Type) SetESC_CONF0_SEPER_CHAR(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_CHAR() uint32 { + return volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF1: Escape sequence configuration register 1 +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0() uint32 { + return volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF2: Escape sequence configuration register 2 +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1() uint32 { + return volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff0000) >> 16 +} + +// UHCI.ESC_CONF3: Escape sequence configuration register 3 +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff)|value) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2() uint32 { + return volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR0(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff00)|value<<8) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR0() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff00) >> 8 +} +func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR1(value uint32) { + volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff0000)|value<<16) +} +func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR1() uint32 { + return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff0000) >> 16 +} + +// UHCI.PKT_THRES: Configure register for packet length +func (o *UHCI_Type) SetPKT_THRES_PKT_THRS(value uint32) { + volatile.StoreUint32(&o.PKT_THRES.Reg, volatile.LoadUint32(&o.PKT_THRES.Reg)&^(0x1fff)|value) +} +func (o *UHCI_Type) GetPKT_THRES_PKT_THRS() uint32 { + return volatile.LoadUint32(&o.PKT_THRES.Reg) & 0x1fff +} + +// UHCI.DATE: UHCI version control register +func (o *UHCI_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *UHCI_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// USB OTG (On-The-Go) +type USB_Type struct { + GOTGCTL volatile.Register32 // 0x0 + GOTGINT volatile.Register32 // 0x4 + GAHBCFG volatile.Register32 // 0x8 + GUSBCFG volatile.Register32 // 0xC + GRSTCTL volatile.Register32 // 0x10 + GINTSTS volatile.Register32 // 0x14 + GINTMSK volatile.Register32 // 0x18 + GRXSTSR volatile.Register32 // 0x1C + GRXSTSP volatile.Register32 // 0x20 + GRXFSIZ volatile.Register32 // 0x24 + GNPTXFSIZ volatile.Register32 // 0x28 + GNPTXSTS volatile.Register32 // 0x2C + _ [16]byte + GSNPSID volatile.Register32 // 0x40 + GHWCFG1 volatile.Register32 // 0x44 + GHWCFG2 volatile.Register32 // 0x48 + GHWCFG3 volatile.Register32 // 0x4C + GHWCFG4 volatile.Register32 // 0x50 + _ [8]byte + GDFIFOCFG volatile.Register32 // 0x5C + _ [160]byte + HPTXFSIZ volatile.Register32 // 0x100 + DIEPTXF1 volatile.Register32 // 0x104 + DIEPTXF2 volatile.Register32 // 0x108 + DIEPTXF3 volatile.Register32 // 0x10C + DIEPTXF4 volatile.Register32 // 0x110 + _ [748]byte + HCFG volatile.Register32 // 0x400 + HFIR volatile.Register32 // 0x404 + HFNUM volatile.Register32 // 0x408 + _ [4]byte + HPTXSTS volatile.Register32 // 0x410 + HAINT volatile.Register32 // 0x414 + HAINTMSK volatile.Register32 // 0x418 + HFLBADDR volatile.Register32 // 0x41C + _ [32]byte + HPRT volatile.Register32 // 0x440 + _ [188]byte + HCCHAR0 volatile.Register32 // 0x500 + _ [4]byte + HCINT0 volatile.Register32 // 0x508 + HCINTMSK0 volatile.Register32 // 0x50C + HCTSIZ0 volatile.Register32 // 0x510 + HCDMA0 volatile.Register32 // 0x514 + _ [4]byte + HCDMAB0 volatile.Register32 // 0x51C + HCCHAR1 volatile.Register32 // 0x520 + _ [4]byte + HCINT1 volatile.Register32 // 0x528 + HCINTMSK1 volatile.Register32 // 0x52C + HCTSIZ1 volatile.Register32 // 0x530 + HCDMA1 volatile.Register32 // 0x534 + _ [4]byte + HCDMAB1 volatile.Register32 // 0x53C + HCCHAR2 volatile.Register32 // 0x540 + _ [4]byte + HCINT2 volatile.Register32 // 0x548 + HCINTMSK2 volatile.Register32 // 0x54C + HCTSIZ2 volatile.Register32 // 0x550 + HCDMA2 volatile.Register32 // 0x554 + _ [4]byte + HCDMAB2 volatile.Register32 // 0x55C + HCCHAR3 volatile.Register32 // 0x560 + _ [4]byte + HCINT3 volatile.Register32 // 0x568 + HCINTMSK3 volatile.Register32 // 0x56C + HCTSIZ3 volatile.Register32 // 0x570 + HCDMA3 volatile.Register32 // 0x574 + _ [4]byte + HCDMAB3 volatile.Register32 // 0x57C + HCCHAR4 volatile.Register32 // 0x580 + _ [4]byte + HCINT4 volatile.Register32 // 0x588 + HCINTMSK4 volatile.Register32 // 0x58C + HCTSIZ4 volatile.Register32 // 0x590 + HCDMA4 volatile.Register32 // 0x594 + _ [4]byte + HCDMAB4 volatile.Register32 // 0x59C + HCCHAR5 volatile.Register32 // 0x5A0 + _ [4]byte + HCINT5 volatile.Register32 // 0x5A8 + HCINTMSK5 volatile.Register32 // 0x5AC + HCTSIZ5 volatile.Register32 // 0x5B0 + HCDMA5 volatile.Register32 // 0x5B4 + _ [4]byte + HCDMAB5 volatile.Register32 // 0x5BC + HCCHAR6 volatile.Register32 // 0x5C0 + _ [4]byte + HCINT6 volatile.Register32 // 0x5C8 + HCINTMSK6 volatile.Register32 // 0x5CC + HCTSIZ6 volatile.Register32 // 0x5D0 + HCDMA6 volatile.Register32 // 0x5D4 + _ [4]byte + HCDMAB6 volatile.Register32 // 0x5DC + HCCHAR7 volatile.Register32 // 0x5E0 + _ [4]byte + HCINT7 volatile.Register32 // 0x5E8 + HCINTMSK7 volatile.Register32 // 0x5EC + HCTSIZ7 volatile.Register32 // 0x5F0 + HCDMA7 volatile.Register32 // 0x5F4 + _ [4]byte + HCDMAB7 volatile.Register32 // 0x5FC + _ [512]byte + DCFG volatile.Register32 // 0x800 + DCTL volatile.Register32 // 0x804 + DSTS volatile.Register32 // 0x808 + _ [4]byte + DIEPMSK volatile.Register32 // 0x810 + DOEPMSK volatile.Register32 // 0x814 + DAINT volatile.Register32 // 0x818 + DAINTMSK volatile.Register32 // 0x81C + _ [8]byte + DVBUSDIS volatile.Register32 // 0x828 + DVBUSPULSE volatile.Register32 // 0x82C + DTHRCTL volatile.Register32 // 0x830 + DIEPEMPMSK volatile.Register32 // 0x834 + _ [200]byte + DIEPCTL0 volatile.Register32 // 0x900 + _ [4]byte + DIEPINT0 volatile.Register32 // 0x908 + _ [4]byte + DIEPTSIZ0 volatile.Register32 // 0x910 + DIEPDMA0 volatile.Register32 // 0x914 + DTXFSTS0 volatile.Register32 // 0x918 + DIEPDMAB0 volatile.Register32 // 0x91C + DIEPCTL1 volatile.Register32 // 0x920 + _ [4]byte + DIEPINT1 volatile.Register32 // 0x928 + _ [4]byte + DIEPTSIZ1 volatile.Register32 // 0x930 + DIEPDMA1 volatile.Register32 // 0x934 + DTXFSTS1 volatile.Register32 // 0x938 + DIEPDMAB1 volatile.Register32 // 0x93C + DIEPCTL2 volatile.Register32 // 0x940 + _ [4]byte + DIEPINT2 volatile.Register32 // 0x948 + _ [4]byte + DIEPTSIZ2 volatile.Register32 // 0x950 + DIEPDMA2 volatile.Register32 // 0x954 + DTXFSTS2 volatile.Register32 // 0x958 + DIEPDMAB2 volatile.Register32 // 0x95C + DIEPCTL3 volatile.Register32 // 0x960 + _ [4]byte + DIEPINT3 volatile.Register32 // 0x968 + _ [4]byte + DIEPTSIZ3 volatile.Register32 // 0x970 + DIEPDMA3 volatile.Register32 // 0x974 + DTXFSTS3 volatile.Register32 // 0x978 + DIEPDMAB3 volatile.Register32 // 0x97C + DIEPCTL4 volatile.Register32 // 0x980 + _ [4]byte + DIEPINT4 volatile.Register32 // 0x988 + _ [4]byte + DIEPTSIZ4 volatile.Register32 // 0x990 + DIEPDMA4 volatile.Register32 // 0x994 + DTXFSTS4 volatile.Register32 // 0x998 + DIEPDMAB4 volatile.Register32 // 0x99C + DIEPCTL5 volatile.Register32 // 0x9A0 + _ [4]byte + DIEPINT5 volatile.Register32 // 0x9A8 + _ [4]byte + DIEPTSIZ5 volatile.Register32 // 0x9B0 + DIEPDMA5 volatile.Register32 // 0x9B4 + DTXFSTS5 volatile.Register32 // 0x9B8 + DIEPDMAB5 volatile.Register32 // 0x9BC + DIEPCTL6 volatile.Register32 // 0x9C0 + _ [4]byte + DIEPINT6 volatile.Register32 // 0x9C8 + _ [4]byte + DIEPTSIZ6 volatile.Register32 // 0x9D0 + DIEPDMA6 volatile.Register32 // 0x9D4 + DTXFSTS6 volatile.Register32 // 0x9D8 + DIEPDMAB6 volatile.Register32 // 0x9DC + _ [288]byte + DOEPCTL0 volatile.Register32 // 0xB00 + _ [4]byte + DOEPINT0 volatile.Register32 // 0xB08 + _ [4]byte + DOEPTSIZ0 volatile.Register32 // 0xB10 + DOEPDMA0 volatile.Register32 // 0xB14 + _ [4]byte + DOEPDMAB0 volatile.Register32 // 0xB1C + DOEPCTL1 volatile.Register32 // 0xB20 + _ [4]byte + DOEPINT1 volatile.Register32 // 0xB28 + _ [4]byte + DOEPTSIZ1 volatile.Register32 // 0xB30 + DOEPDMA1 volatile.Register32 // 0xB34 + _ [4]byte + DOEPDMAB1 volatile.Register32 // 0xB3C + DOEPCTL2 volatile.Register32 // 0xB40 + _ [4]byte + DOEPINT2 volatile.Register32 // 0xB48 + _ [4]byte + DOEPTSIZ2 volatile.Register32 // 0xB50 + DOEPDMA2 volatile.Register32 // 0xB54 + _ [4]byte + DOEPDMAB2 volatile.Register32 // 0xB5C + DOEPCTL3 volatile.Register32 // 0xB60 + _ [4]byte + DOEPINT3 volatile.Register32 // 0xB68 + _ [4]byte + DOEPTSIZ3 volatile.Register32 // 0xB70 + DOEPDMA3 volatile.Register32 // 0xB74 + _ [4]byte + DOEPDMAB3 volatile.Register32 // 0xB7C + DOEPCTL4 volatile.Register32 // 0xB80 + _ [4]byte + DOEPINT4 volatile.Register32 // 0xB88 + _ [4]byte + DOEPTSIZ4 volatile.Register32 // 0xB90 + DOEPDMA4 volatile.Register32 // 0xB94 + _ [4]byte + DOEPDMAB4 volatile.Register32 // 0xB9C + DOEPCTL5 volatile.Register32 // 0xBA0 + _ [4]byte + DOEPINT5 volatile.Register32 // 0xBA8 + _ [4]byte + DOEPTSIZ5 volatile.Register32 // 0xBB0 + DOEPDMA5 volatile.Register32 // 0xBB4 + _ [4]byte + DOEPDMAB5 volatile.Register32 // 0xBBC + DOEPCTL6 volatile.Register32 // 0xBC0 + _ [4]byte + DOEPINT6 volatile.Register32 // 0xBC8 + _ [4]byte + DOEPTSIZ6 volatile.Register32 // 0xBD0 + DOEPDMA6 volatile.Register32 // 0xBD4 + _ [4]byte + DOEPDMAB6 volatile.Register32 // 0xBDC + _ [544]byte + PCGCCTL volatile.Register32 // 0xE00 +} + +// USB.GOTGCTL +func (o *USB_Type) SetGOTGCTL_SESREQSCS(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetGOTGCTL_SESREQSCS() uint32 { + return volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x1 +} +func (o *USB_Type) SetGOTGCTL_SESREQ(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetGOTGCTL_SESREQ() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetGOTGCTL_VBVALIDOVEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGOTGCTL_VBVALIDOVEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGOTGCTL_VBVALIDOVVAL(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetGOTGCTL_VBVALIDOVVAL() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetGOTGCTL_AVALIDOVEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGOTGCTL_AVALIDOVEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGOTGCTL_AVALIDOVVAL(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGOTGCTL_AVALIDOVVAL() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGOTGCTL_BVALIDOVEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGOTGCTL_BVALIDOVEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGOTGCTL_BVALIDOVVAL(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGOTGCTL_BVALIDOVVAL() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGOTGCTL_HSTNEGSCS(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGOTGCTL_HSTNEGSCS() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGOTGCTL_HNPREQ(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetGOTGCTL_HNPREQ() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetGOTGCTL_HSTSETHNPEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetGOTGCTL_HSTSETHNPEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetGOTGCTL_DEVHNPEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetGOTGCTL_DEVHNPEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetGOTGCTL_EHEN(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGOTGCTL_EHEN() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGOTGCTL_DBNCEFLTRBYPASS(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetGOTGCTL_DBNCEFLTRBYPASS() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetGOTGCTL_CONIDSTS(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetGOTGCTL_CONIDSTS() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetGOTGCTL_DBNCTIME(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetGOTGCTL_DBNCTIME() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetGOTGCTL_ASESVLD(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGOTGCTL_ASESVLD() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGOTGCTL_BSESVLD(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGOTGCTL_BSESVLD() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetGOTGCTL_OTGVER(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGOTGCTL_OTGVER() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGOTGCTL_CURMOD(value uint32) { + volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGOTGCTL_CURMOD() uint32 { + return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x200000) >> 21 +} + +// USB.GOTGINT +func (o *USB_Type) SetGOTGINT_SESENDDET(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGOTGINT_SESENDDET() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGOTGINT_SESREQSUCSTSCHNG(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGOTGINT_SESREQSUCSTSCHNG() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGOTGINT_HSTNEGSUCSTSCHNG(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetGOTGINT_HSTNEGSUCSTSCHNG() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetGOTGINT_HSTNEGDET(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetGOTGINT_HSTNEGDET() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetGOTGINT_ADEVTOUTCHG(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGOTGINT_ADEVTOUTCHG() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGOTGINT_DBNCEDONE(value uint32) { + volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGOTGINT_DBNCEDONE() uint32 { + return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x80000) >> 19 +} + +// USB.GAHBCFG +func (o *USB_Type) SetGAHBCFG_GLBLLNTRMSK(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetGAHBCFG_GLBLLNTRMSK() uint32 { + return volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x1 +} +func (o *USB_Type) SetGAHBCFG_HBSTLEN(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x1e)|value<<1) +} +func (o *USB_Type) GetGAHBCFG_HBSTLEN() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x1e) >> 1 +} +func (o *USB_Type) SetGAHBCFG_DMAEN(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGAHBCFG_DMAEN() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGAHBCFG_NPTXFEMPLVL(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGAHBCFG_NPTXFEMPLVL() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGAHBCFG_PTXFEMPLVL(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGAHBCFG_PTXFEMPLVL() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGAHBCFG_REMMEMSUPP(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGAHBCFG_REMMEMSUPP() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetGAHBCFG_NOTIALLDMAWRIT(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGAHBCFG_NOTIALLDMAWRIT() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGAHBCFG_AHBSINGLE(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetGAHBCFG_AHBSINGLE() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetGAHBCFG_INVDESCENDIANESS(value uint32) { + volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x1000000)|value<<24) +} +func (o *USB_Type) GetGAHBCFG_INVDESCENDIANESS() uint32 { + return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x1000000) >> 24 +} + +// USB.GUSBCFG +func (o *USB_Type) SetGUSBCFG_TOUTCAL(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x7)|value) +} +func (o *USB_Type) GetGUSBCFG_TOUTCAL() uint32 { + return volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x7 +} +func (o *USB_Type) SetGUSBCFG_PHYIF(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetGUSBCFG_PHYIF() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetGUSBCFG_ULPI_UTMI_SEL(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGUSBCFG_ULPI_UTMI_SEL() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGUSBCFG_FSINTF(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGUSBCFG_FSINTF() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGUSBCFG_PHYSEL(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGUSBCFG_PHYSEL() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGUSBCFG_SRPCAP(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGUSBCFG_SRPCAP() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGUSBCFG_HNPCAP(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetGUSBCFG_HNPCAP() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetGUSBCFG_USBTRDTIM(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x3c00)|value<<10) +} +func (o *USB_Type) GetGUSBCFG_USBTRDTIM() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x3c00) >> 10 +} +func (o *USB_Type) SetGUSBCFG_TERMSELDLPULSE(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGUSBCFG_TERMSELDLPULSE() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGUSBCFG_TXENDDELAY(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetGUSBCFG_TXENDDELAY() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetGUSBCFG_FORCEHSTMODE(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetGUSBCFG_FORCEHSTMODE() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetGUSBCFG_FORCEDEVMODE(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGUSBCFG_FORCEDEVMODE() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGUSBCFG_CORRUPTTXPKT(value uint32) { + volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGUSBCFG_CORRUPTTXPKT() uint32 { + return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x80000000) >> 31 +} + +// USB.GRSTCTL +func (o *USB_Type) SetGRSTCTL_CSFTRST(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetGRSTCTL_CSFTRST() uint32 { + return volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x1 +} +func (o *USB_Type) SetGRSTCTL_PIUFSSFTRST(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetGRSTCTL_PIUFSSFTRST() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetGRSTCTL_FRMCNTRRST(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGRSTCTL_FRMCNTRRST() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGRSTCTL_RXFFLSH(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGRSTCTL_RXFFLSH() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGRSTCTL_TXFFLSH(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGRSTCTL_TXFFLSH() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGRSTCTL_TXFNUM(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x7c0)|value<<6) +} +func (o *USB_Type) GetGRSTCTL_TXFNUM() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x7c0) >> 6 +} +func (o *USB_Type) SetGRSTCTL_DMAREQ(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGRSTCTL_DMAREQ() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGRSTCTL_AHBIDLE(value uint32) { + volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGRSTCTL_AHBIDLE() uint32 { + return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x80000000) >> 31 +} + +// USB.GINTSTS +func (o *USB_Type) SetGINTSTS_CURMOD_INT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetGINTSTS_CURMOD_INT() uint32 { + return volatile.LoadUint32(&o.GINTSTS.Reg) & 0x1 +} +func (o *USB_Type) SetGINTSTS_MODEMIS(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetGINTSTS_MODEMIS() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetGINTSTS_OTGINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGINTSTS_OTGINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGINTSTS_SOF(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetGINTSTS_SOF() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetGINTSTS_RXFLVI(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGINTSTS_RXFLVI() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGINTSTS_NPTXFEMP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGINTSTS_NPTXFEMP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGINTSTS_GINNAKEFF(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGINTSTS_GINNAKEFF() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGINTSTS_GOUTNAKEFF(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGINTSTS_GOUTNAKEFF() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGINTSTS_ERLYSUSP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetGINTSTS_ERLYSUSP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetGINTSTS_USBSUSP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetGINTSTS_USBSUSP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetGINTSTS_USBRST(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGINTSTS_USBRST() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGINTSTS_ENUMDONE(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetGINTSTS_ENUMDONE() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetGINTSTS_ISOOUTDROP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetGINTSTS_ISOOUTDROP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetGINTSTS_EOPF(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetGINTSTS_EOPF() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetGINTSTS_EPMIS(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetGINTSTS_EPMIS() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetGINTSTS_IEPINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGINTSTS_IEPINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGINTSTS_OEPINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGINTSTS_OEPINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetGINTSTS_INCOMPISOIN(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGINTSTS_INCOMPISOIN() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGINTSTS_INCOMPIP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGINTSTS_INCOMPIP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetGINTSTS_FETSUSP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGINTSTS_FETSUSP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGINTSTS_RESETDET(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetGINTSTS_RESETDET() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetGINTSTS_PRTLNT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x1000000)|value<<24) +} +func (o *USB_Type) GetGINTSTS_PRTLNT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x1000000) >> 24 +} +func (o *USB_Type) SetGINTSTS_HCHLNT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x2000000)|value<<25) +} +func (o *USB_Type) GetGINTSTS_HCHLNT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x2000000) >> 25 +} +func (o *USB_Type) SetGINTSTS_PTXFEMP(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetGINTSTS_PTXFEMP() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetGINTSTS_CONIDSTSCHNG(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetGINTSTS_CONIDSTSCHNG() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetGINTSTS_DISCONNINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetGINTSTS_DISCONNINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetGINTSTS_SESSREQINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGINTSTS_SESSREQINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGINTSTS_WKUPINT(value uint32) { + volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGINTSTS_WKUPINT() uint32 { + return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x80000000) >> 31 +} + +// USB.GINTMSK +func (o *USB_Type) SetGINTMSK_MODEMISMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetGINTMSK_MODEMISMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetGINTMSK_OTGINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetGINTMSK_OTGINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetGINTMSK_SOFMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetGINTMSK_SOFMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetGINTMSK_RXFLVIMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGINTMSK_RXFLVIMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGINTMSK_NPTXFEMPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGINTMSK_NPTXFEMPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGINTMSK_GINNAKEFFMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGINTMSK_GINNAKEFFMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGINTMSK_GOUTNACKEFFMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGINTMSK_GOUTNACKEFFMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGINTMSK_ERLYSUSPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetGINTMSK_ERLYSUSPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetGINTMSK_USBSUSPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetGINTMSK_USBSUSPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetGINTMSK_USBRSTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGINTMSK_USBRSTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGINTMSK_ENUMDONEMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetGINTMSK_ENUMDONEMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetGINTMSK_ISOOUTDROPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetGINTMSK_ISOOUTDROPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetGINTMSK_EOPFMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetGINTMSK_EOPFMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetGINTMSK_EPMISMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetGINTMSK_EPMISMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetGINTMSK_IEPINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGINTMSK_IEPINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGINTMSK_OEPINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGINTMSK_OEPINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetGINTMSK_INCOMPISOINMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGINTMSK_INCOMPISOINMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGINTMSK_INCOMPIPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGINTMSK_INCOMPIPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetGINTMSK_FETSUSPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGINTMSK_FETSUSPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGINTMSK_RESETDETMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetGINTMSK_RESETDETMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetGINTMSK_PRTLNTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x1000000)|value<<24) +} +func (o *USB_Type) GetGINTMSK_PRTLNTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x1000000) >> 24 +} +func (o *USB_Type) SetGINTMSK_HCHINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x2000000)|value<<25) +} +func (o *USB_Type) GetGINTMSK_HCHINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x2000000) >> 25 +} +func (o *USB_Type) SetGINTMSK_PTXFEMPMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetGINTMSK_PTXFEMPMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetGINTMSK_CONIDSTSCHNGMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetGINTMSK_CONIDSTSCHNGMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetGINTMSK_DISCONNINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetGINTMSK_DISCONNINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetGINTMSK_SESSREQINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGINTMSK_SESSREQINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGINTMSK_WKUPINTMSK(value uint32) { + volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGINTMSK_WKUPINTMSK() uint32 { + return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x80000000) >> 31 +} + +// USB.GRXSTSR +func (o *USB_Type) SetGRXSTSR_G_CHNUM(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0xf)|value) +} +func (o *USB_Type) GetGRXSTSR_G_CHNUM() uint32 { + return volatile.LoadUint32(&o.GRXSTSR.Reg) & 0xf +} +func (o *USB_Type) SetGRXSTSR_G_BCNT(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0x7ff0)|value<<4) +} +func (o *USB_Type) GetGRXSTSR_G_BCNT() uint32 { + return (volatile.LoadUint32(&o.GRXSTSR.Reg) & 0x7ff0) >> 4 +} +func (o *USB_Type) SetGRXSTSR_G_DPID(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0x18000)|value<<15) +} +func (o *USB_Type) GetGRXSTSR_G_DPID() uint32 { + return (volatile.LoadUint32(&o.GRXSTSR.Reg) & 0x18000) >> 15 +} +func (o *USB_Type) SetGRXSTSR_G_PKTSTS(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0x1e0000)|value<<17) +} +func (o *USB_Type) GetGRXSTSR_G_PKTSTS() uint32 { + return (volatile.LoadUint32(&o.GRXSTSR.Reg) & 0x1e0000) >> 17 +} +func (o *USB_Type) SetGRXSTSR_G_FN(value uint32) { + volatile.StoreUint32(&o.GRXSTSR.Reg, volatile.LoadUint32(&o.GRXSTSR.Reg)&^(0x1e00000)|value<<21) +} +func (o *USB_Type) GetGRXSTSR_G_FN() uint32 { + return (volatile.LoadUint32(&o.GRXSTSR.Reg) & 0x1e00000) >> 21 +} + +// USB.GRXSTSP +func (o *USB_Type) SetGRXSTSP_CHNUM(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0xf)|value) +} +func (o *USB_Type) GetGRXSTSP_CHNUM() uint32 { + return volatile.LoadUint32(&o.GRXSTSP.Reg) & 0xf +} +func (o *USB_Type) SetGRXSTSP_BCNT(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0x7ff0)|value<<4) +} +func (o *USB_Type) GetGRXSTSP_BCNT() uint32 { + return (volatile.LoadUint32(&o.GRXSTSP.Reg) & 0x7ff0) >> 4 +} +func (o *USB_Type) SetGRXSTSP_DPID(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0x18000)|value<<15) +} +func (o *USB_Type) GetGRXSTSP_DPID() uint32 { + return (volatile.LoadUint32(&o.GRXSTSP.Reg) & 0x18000) >> 15 +} +func (o *USB_Type) SetGRXSTSP_PKTSTS(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0x1e0000)|value<<17) +} +func (o *USB_Type) GetGRXSTSP_PKTSTS() uint32 { + return (volatile.LoadUint32(&o.GRXSTSP.Reg) & 0x1e0000) >> 17 +} +func (o *USB_Type) SetGRXSTSP_FN(value uint32) { + volatile.StoreUint32(&o.GRXSTSP.Reg, volatile.LoadUint32(&o.GRXSTSP.Reg)&^(0x1e00000)|value<<21) +} +func (o *USB_Type) GetGRXSTSP_FN() uint32 { + return (volatile.LoadUint32(&o.GRXSTSP.Reg) & 0x1e00000) >> 21 +} + +// USB.GRXFSIZ +func (o *USB_Type) SetGRXFSIZ_RXFDEP(value uint32) { + volatile.StoreUint32(&o.GRXFSIZ.Reg, volatile.LoadUint32(&o.GRXFSIZ.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetGRXFSIZ_RXFDEP() uint32 { + return volatile.LoadUint32(&o.GRXFSIZ.Reg) & 0xffff +} + +// USB.GNPTXFSIZ +func (o *USB_Type) SetGNPTXFSIZ_NPTXFSTADDR(value uint32) { + volatile.StoreUint32(&o.GNPTXFSIZ.Reg, volatile.LoadUint32(&o.GNPTXFSIZ.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetGNPTXFSIZ_NPTXFSTADDR() uint32 { + return volatile.LoadUint32(&o.GNPTXFSIZ.Reg) & 0xffff +} +func (o *USB_Type) SetGNPTXFSIZ_NPTXFDEP(value uint32) { + volatile.StoreUint32(&o.GNPTXFSIZ.Reg, volatile.LoadUint32(&o.GNPTXFSIZ.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetGNPTXFSIZ_NPTXFDEP() uint32 { + return (volatile.LoadUint32(&o.GNPTXFSIZ.Reg) & 0xffff0000) >> 16 +} + +// USB.GNPTXSTS +func (o *USB_Type) SetGNPTXSTS_NPTXFSPCAVAIL(value uint32) { + volatile.StoreUint32(&o.GNPTXSTS.Reg, volatile.LoadUint32(&o.GNPTXSTS.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetGNPTXSTS_NPTXFSPCAVAIL() uint32 { + return volatile.LoadUint32(&o.GNPTXSTS.Reg) & 0xffff +} +func (o *USB_Type) SetGNPTXSTS_NPTXQSPCAVAIL(value uint32) { + volatile.StoreUint32(&o.GNPTXSTS.Reg, volatile.LoadUint32(&o.GNPTXSTS.Reg)&^(0xf0000)|value<<16) +} +func (o *USB_Type) GetGNPTXSTS_NPTXQSPCAVAIL() uint32 { + return (volatile.LoadUint32(&o.GNPTXSTS.Reg) & 0xf0000) >> 16 +} +func (o *USB_Type) SetGNPTXSTS_NPTXQTOP(value uint32) { + volatile.StoreUint32(&o.GNPTXSTS.Reg, volatile.LoadUint32(&o.GNPTXSTS.Reg)&^(0x7f000000)|value<<24) +} +func (o *USB_Type) GetGNPTXSTS_NPTXQTOP() uint32 { + return (volatile.LoadUint32(&o.GNPTXSTS.Reg) & 0x7f000000) >> 24 +} + +// USB.GSNPSID +func (o *USB_Type) SetGSNPSID(value uint32) { + volatile.StoreUint32(&o.GSNPSID.Reg, value) +} +func (o *USB_Type) GetGSNPSID() uint32 { + return volatile.LoadUint32(&o.GSNPSID.Reg) +} + +// USB.GHWCFG1 +func (o *USB_Type) SetGHWCFG1(value uint32) { + volatile.StoreUint32(&o.GHWCFG1.Reg, value) +} +func (o *USB_Type) GetGHWCFG1() uint32 { + return volatile.LoadUint32(&o.GHWCFG1.Reg) +} + +// USB.GHWCFG2 +func (o *USB_Type) SetGHWCFG2_OTGMODE(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x7)|value) +} +func (o *USB_Type) GetGHWCFG2_OTGMODE() uint32 { + return volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x7 +} +func (o *USB_Type) SetGHWCFG2_OTGARCH(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x18)|value<<3) +} +func (o *USB_Type) GetGHWCFG2_OTGARCH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x18) >> 3 +} +func (o *USB_Type) SetGHWCFG2_SINGPNT(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGHWCFG2_SINGPNT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGHWCFG2_HSPHYTYPE(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0xc0)|value<<6) +} +func (o *USB_Type) GetGHWCFG2_HSPHYTYPE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0xc0) >> 6 +} +func (o *USB_Type) SetGHWCFG2_FSPHYTYPE(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x300)|value<<8) +} +func (o *USB_Type) GetGHWCFG2_FSPHYTYPE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x300) >> 8 +} +func (o *USB_Type) SetGHWCFG2_NUMDEVEPS(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x3c00)|value<<10) +} +func (o *USB_Type) GetGHWCFG2_NUMDEVEPS() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x3c00) >> 10 +} +func (o *USB_Type) SetGHWCFG2_NUMHSTCHNL(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x3c000)|value<<14) +} +func (o *USB_Type) GetGHWCFG2_NUMHSTCHNL() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x3c000) >> 14 +} +func (o *USB_Type) SetGHWCFG2_PERIOSUPPORT(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetGHWCFG2_PERIOSUPPORT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetGHWCFG2_DYNFIFOSIZING(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetGHWCFG2_DYNFIFOSIZING() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetGHWCFG2_MULTIPROCINTRPT(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGHWCFG2_MULTIPROCINTRPT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGHWCFG2_NPTXQDEPTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0xc00000)|value<<22) +} +func (o *USB_Type) GetGHWCFG2_NPTXQDEPTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0xc00000) >> 22 +} +func (o *USB_Type) SetGHWCFG2_PTXQDEPTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x3000000)|value<<24) +} +func (o *USB_Type) GetGHWCFG2_PTXQDEPTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x3000000) >> 24 +} +func (o *USB_Type) SetGHWCFG2_TKNQDEPTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x7c000000)|value<<26) +} +func (o *USB_Type) GetGHWCFG2_TKNQDEPTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x7c000000) >> 26 +} +func (o *USB_Type) SetGHWCFG2_OTG_ENABLE_IC_USB(value uint32) { + volatile.StoreUint32(&o.GHWCFG2.Reg, volatile.LoadUint32(&o.GHWCFG2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGHWCFG2_OTG_ENABLE_IC_USB() uint32 { + return (volatile.LoadUint32(&o.GHWCFG2.Reg) & 0x80000000) >> 31 +} + +// USB.GHWCFG3 +func (o *USB_Type) SetGHWCFG3_XFERSIZEWIDTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0xf)|value) +} +func (o *USB_Type) GetGHWCFG3_XFERSIZEWIDTH() uint32 { + return volatile.LoadUint32(&o.GHWCFG3.Reg) & 0xf +} +func (o *USB_Type) SetGHWCFG3_PKTSIZEWIDTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x70)|value<<4) +} +func (o *USB_Type) GetGHWCFG3_PKTSIZEWIDTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x70) >> 4 +} +func (o *USB_Type) SetGHWCFG3_OTGEN(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGHWCFG3_OTGEN() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGHWCFG3_I2CINTSEL(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetGHWCFG3_I2CINTSEL() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetGHWCFG3_VNDCTLSUPT(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetGHWCFG3_VNDCTLSUPT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetGHWCFG3_OPTFEATURE(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetGHWCFG3_OPTFEATURE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetGHWCFG3_RSTTYPE(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetGHWCFG3_RSTTYPE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetGHWCFG3_ADPSUPPORT(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGHWCFG3_ADPSUPPORT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGHWCFG3_HSICMODE(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetGHWCFG3_HSICMODE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetGHWCFG3_BCSUPPORT(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetGHWCFG3_BCSUPPORT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetGHWCFG3_LPMMODE(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetGHWCFG3_LPMMODE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetGHWCFG3_DFIFODEPTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG3.Reg, volatile.LoadUint32(&o.GHWCFG3.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetGHWCFG3_DFIFODEPTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG3.Reg) & 0xffff0000) >> 16 +} + +// USB.GHWCFG4 +func (o *USB_Type) SetGHWCFG4_G_NUMDEVPERIOEPS(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0xf)|value) +} +func (o *USB_Type) GetGHWCFG4_G_NUMDEVPERIOEPS() uint32 { + return volatile.LoadUint32(&o.GHWCFG4.Reg) & 0xf +} +func (o *USB_Type) SetGHWCFG4_G_PARTIALPWRDN(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetGHWCFG4_G_PARTIALPWRDN() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetGHWCFG4_G_AHBFREQ(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetGHWCFG4_G_AHBFREQ() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetGHWCFG4_G_HIBERNATION(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetGHWCFG4_G_HIBERNATION() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetGHWCFG4_G_EXTENDEDHIBERNATION(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetGHWCFG4_G_EXTENDEDHIBERNATION() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetGHWCFG4_G_ACGSUPT(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetGHWCFG4_G_ACGSUPT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetGHWCFG4_G_ENHANCEDLPMSUPT(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetGHWCFG4_G_ENHANCEDLPMSUPT() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetGHWCFG4_G_PHYDATAWIDTH(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0xc000)|value<<14) +} +func (o *USB_Type) GetGHWCFG4_G_PHYDATAWIDTH() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0xc000) >> 14 +} +func (o *USB_Type) SetGHWCFG4_G_NUMCTLEPS(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0xf0000)|value<<16) +} +func (o *USB_Type) GetGHWCFG4_G_NUMCTLEPS() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0xf0000) >> 16 +} +func (o *USB_Type) SetGHWCFG4_G_IDDQFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetGHWCFG4_G_IDDQFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetGHWCFG4_G_VBUSVALIDFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetGHWCFG4_G_VBUSVALIDFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetGHWCFG4_G_AVALIDFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetGHWCFG4_G_AVALIDFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x400000) >> 22 +} +func (o *USB_Type) SetGHWCFG4_G_BVALIDFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetGHWCFG4_G_BVALIDFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetGHWCFG4_G_SESSENDFLTR(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x1000000)|value<<24) +} +func (o *USB_Type) GetGHWCFG4_G_SESSENDFLTR() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x1000000) >> 24 +} +func (o *USB_Type) SetGHWCFG4_G_DEDFIFOMODE(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x2000000)|value<<25) +} +func (o *USB_Type) GetGHWCFG4_G_DEDFIFOMODE() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x2000000) >> 25 +} +func (o *USB_Type) SetGHWCFG4_G_INEPS(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x3c000000)|value<<26) +} +func (o *USB_Type) GetGHWCFG4_G_INEPS() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x3c000000) >> 26 +} +func (o *USB_Type) SetGHWCFG4_G_DESCDMAENABLED(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetGHWCFG4_G_DESCDMAENABLED() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetGHWCFG4_G_DESCDMA(value uint32) { + volatile.StoreUint32(&o.GHWCFG4.Reg, volatile.LoadUint32(&o.GHWCFG4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetGHWCFG4_G_DESCDMA() uint32 { + return (volatile.LoadUint32(&o.GHWCFG4.Reg) & 0x80000000) >> 31 +} + +// USB.GDFIFOCFG +func (o *USB_Type) SetGDFIFOCFG(value uint32) { + volatile.StoreUint32(&o.GDFIFOCFG.Reg, volatile.LoadUint32(&o.GDFIFOCFG.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetGDFIFOCFG() uint32 { + return volatile.LoadUint32(&o.GDFIFOCFG.Reg) & 0xffff +} +func (o *USB_Type) SetGDFIFOCFG_EPINFOBASEADDR(value uint32) { + volatile.StoreUint32(&o.GDFIFOCFG.Reg, volatile.LoadUint32(&o.GDFIFOCFG.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetGDFIFOCFG_EPINFOBASEADDR() uint32 { + return (volatile.LoadUint32(&o.GDFIFOCFG.Reg) & 0xffff0000) >> 16 +} + +// USB.HPTXFSIZ +func (o *USB_Type) SetHPTXFSIZ_PTXFSTADDR(value uint32) { + volatile.StoreUint32(&o.HPTXFSIZ.Reg, volatile.LoadUint32(&o.HPTXFSIZ.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetHPTXFSIZ_PTXFSTADDR() uint32 { + return volatile.LoadUint32(&o.HPTXFSIZ.Reg) & 0xffff +} +func (o *USB_Type) SetHPTXFSIZ_PTXFSIZE(value uint32) { + volatile.StoreUint32(&o.HPTXFSIZ.Reg, volatile.LoadUint32(&o.HPTXFSIZ.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetHPTXFSIZ_PTXFSIZE() uint32 { + return (volatile.LoadUint32(&o.HPTXFSIZ.Reg) & 0xffff0000) >> 16 +} + +// USB.DIEPTXF1 +func (o *USB_Type) SetDIEPTXF1_INEP1TXFSTADDR(value uint32) { + volatile.StoreUint32(&o.DIEPTXF1.Reg, volatile.LoadUint32(&o.DIEPTXF1.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPTXF1_INEP1TXFSTADDR() uint32 { + return volatile.LoadUint32(&o.DIEPTXF1.Reg) & 0xffff +} +func (o *USB_Type) SetDIEPTXF1_INEP1TXFDEP(value uint32) { + volatile.StoreUint32(&o.DIEPTXF1.Reg, volatile.LoadUint32(&o.DIEPTXF1.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetDIEPTXF1_INEP1TXFDEP() uint32 { + return (volatile.LoadUint32(&o.DIEPTXF1.Reg) & 0xffff0000) >> 16 +} + +// USB.DIEPTXF2 +func (o *USB_Type) SetDIEPTXF2_INEP2TXFSTADDR(value uint32) { + volatile.StoreUint32(&o.DIEPTXF2.Reg, volatile.LoadUint32(&o.DIEPTXF2.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPTXF2_INEP2TXFSTADDR() uint32 { + return volatile.LoadUint32(&o.DIEPTXF2.Reg) & 0xffff +} +func (o *USB_Type) SetDIEPTXF2_INEP2TXFDEP(value uint32) { + volatile.StoreUint32(&o.DIEPTXF2.Reg, volatile.LoadUint32(&o.DIEPTXF2.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetDIEPTXF2_INEP2TXFDEP() uint32 { + return (volatile.LoadUint32(&o.DIEPTXF2.Reg) & 0xffff0000) >> 16 +} + +// USB.DIEPTXF3 +func (o *USB_Type) SetDIEPTXF3_INEP3TXFSTADDR(value uint32) { + volatile.StoreUint32(&o.DIEPTXF3.Reg, volatile.LoadUint32(&o.DIEPTXF3.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPTXF3_INEP3TXFSTADDR() uint32 { + return volatile.LoadUint32(&o.DIEPTXF3.Reg) & 0xffff +} +func (o *USB_Type) SetDIEPTXF3_INEP3TXFDEP(value uint32) { + volatile.StoreUint32(&o.DIEPTXF3.Reg, volatile.LoadUint32(&o.DIEPTXF3.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetDIEPTXF3_INEP3TXFDEP() uint32 { + return (volatile.LoadUint32(&o.DIEPTXF3.Reg) & 0xffff0000) >> 16 +} + +// USB.DIEPTXF4 +func (o *USB_Type) SetDIEPTXF4_INEP4TXFSTADDR(value uint32) { + volatile.StoreUint32(&o.DIEPTXF4.Reg, volatile.LoadUint32(&o.DIEPTXF4.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPTXF4_INEP4TXFSTADDR() uint32 { + return volatile.LoadUint32(&o.DIEPTXF4.Reg) & 0xffff +} +func (o *USB_Type) SetDIEPTXF4_INEP4TXFDEP(value uint32) { + volatile.StoreUint32(&o.DIEPTXF4.Reg, volatile.LoadUint32(&o.DIEPTXF4.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetDIEPTXF4_INEP4TXFDEP() uint32 { + return (volatile.LoadUint32(&o.DIEPTXF4.Reg) & 0xffff0000) >> 16 +} + +// USB.HCFG +func (o *USB_Type) SetHCFG_H_FSLSPCLKSEL(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetHCFG_H_FSLSPCLKSEL() uint32 { + return volatile.LoadUint32(&o.HCFG.Reg) & 0x3 +} +func (o *USB_Type) SetHCFG_H_FSLSSUPP(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCFG_H_FSLSSUPP() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCFG_H_ENA32KHZS(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCFG_H_ENA32KHZS() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCFG_H_DESCDMA(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetHCFG_H_DESCDMA() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetHCFG_H_FRLISTEN(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x3000000)|value<<24) +} +func (o *USB_Type) GetHCFG_H_FRLISTEN() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x3000000) >> 24 +} +func (o *USB_Type) SetHCFG_H_PERSCHEDENA(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetHCFG_H_PERSCHEDENA() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetHCFG_H_MODECHTIMEN(value uint32) { + volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCFG_H_MODECHTIMEN() uint32 { + return (volatile.LoadUint32(&o.HCFG.Reg) & 0x80000000) >> 31 +} + +// USB.HFIR +func (o *USB_Type) SetHFIR_FRINT(value uint32) { + volatile.StoreUint32(&o.HFIR.Reg, volatile.LoadUint32(&o.HFIR.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetHFIR_FRINT() uint32 { + return volatile.LoadUint32(&o.HFIR.Reg) & 0xffff +} +func (o *USB_Type) SetHFIR_HFIRRLDCTRL(value uint32) { + volatile.StoreUint32(&o.HFIR.Reg, volatile.LoadUint32(&o.HFIR.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetHFIR_HFIRRLDCTRL() uint32 { + return (volatile.LoadUint32(&o.HFIR.Reg) & 0x10000) >> 16 +} + +// USB.HFNUM +func (o *USB_Type) SetHFNUM_FRNUM(value uint32) { + volatile.StoreUint32(&o.HFNUM.Reg, volatile.LoadUint32(&o.HFNUM.Reg)&^(0x3fff)|value) +} +func (o *USB_Type) GetHFNUM_FRNUM() uint32 { + return volatile.LoadUint32(&o.HFNUM.Reg) & 0x3fff +} +func (o *USB_Type) SetHFNUM_FRREM(value uint32) { + volatile.StoreUint32(&o.HFNUM.Reg, volatile.LoadUint32(&o.HFNUM.Reg)&^(0xffff0000)|value<<16) +} +func (o *USB_Type) GetHFNUM_FRREM() uint32 { + return (volatile.LoadUint32(&o.HFNUM.Reg) & 0xffff0000) >> 16 +} + +// USB.HPTXSTS +func (o *USB_Type) SetHPTXSTS_PTXFSPCAVAIL(value uint32) { + volatile.StoreUint32(&o.HPTXSTS.Reg, volatile.LoadUint32(&o.HPTXSTS.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetHPTXSTS_PTXFSPCAVAIL() uint32 { + return volatile.LoadUint32(&o.HPTXSTS.Reg) & 0xffff +} +func (o *USB_Type) SetHPTXSTS_PTXQSPCAVAIL(value uint32) { + volatile.StoreUint32(&o.HPTXSTS.Reg, volatile.LoadUint32(&o.HPTXSTS.Reg)&^(0x1f0000)|value<<16) +} +func (o *USB_Type) GetHPTXSTS_PTXQSPCAVAIL() uint32 { + return (volatile.LoadUint32(&o.HPTXSTS.Reg) & 0x1f0000) >> 16 +} +func (o *USB_Type) SetHPTXSTS_PTXQTOP(value uint32) { + volatile.StoreUint32(&o.HPTXSTS.Reg, volatile.LoadUint32(&o.HPTXSTS.Reg)&^(0xff000000)|value<<24) +} +func (o *USB_Type) GetHPTXSTS_PTXQTOP() uint32 { + return (volatile.LoadUint32(&o.HPTXSTS.Reg) & 0xff000000) >> 24 +} + +// USB.HAINT +func (o *USB_Type) SetHAINT(value uint32) { + volatile.StoreUint32(&o.HAINT.Reg, volatile.LoadUint32(&o.HAINT.Reg)&^(0xff)|value) +} +func (o *USB_Type) GetHAINT() uint32 { + return volatile.LoadUint32(&o.HAINT.Reg) & 0xff +} + +// USB.HAINTMSK +func (o *USB_Type) SetHAINTMSK(value uint32) { + volatile.StoreUint32(&o.HAINTMSK.Reg, volatile.LoadUint32(&o.HAINTMSK.Reg)&^(0xff)|value) +} +func (o *USB_Type) GetHAINTMSK() uint32 { + return volatile.LoadUint32(&o.HAINTMSK.Reg) & 0xff +} + +// USB.HFLBADDR +func (o *USB_Type) SetHFLBADDR(value uint32) { + volatile.StoreUint32(&o.HFLBADDR.Reg, value) +} +func (o *USB_Type) GetHFLBADDR() uint32 { + return volatile.LoadUint32(&o.HFLBADDR.Reg) +} + +// USB.HPRT +func (o *USB_Type) SetHPRT_PRTCONNSTS(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHPRT_PRTCONNSTS() uint32 { + return volatile.LoadUint32(&o.HPRT.Reg) & 0x1 +} +func (o *USB_Type) SetHPRT_PRTCONNDET(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHPRT_PRTCONNDET() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHPRT_PRTENA(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHPRT_PRTENA() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHPRT_PRTENCHNG(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHPRT_PRTENCHNG() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHPRT_PRTOVRCURRACT(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHPRT_PRTOVRCURRACT() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHPRT_PRTOVRCURRCHNG(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHPRT_PRTOVRCURRCHNG() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHPRT_PRTRES(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHPRT_PRTRES() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHPRT_PRTSUSP(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHPRT_PRTSUSP() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHPRT_PRTRST(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHPRT_PRTRST() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHPRT_PRTLNSTS(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0xc00)|value<<10) +} +func (o *USB_Type) GetHPRT_PRTLNSTS() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0xc00) >> 10 +} +func (o *USB_Type) SetHPRT_PRTPWR(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHPRT_PRTPWR() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHPRT_PRTTSTCTL(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x1e000)|value<<13) +} +func (o *USB_Type) GetHPRT_PRTTSTCTL() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x1e000) >> 13 +} +func (o *USB_Type) SetHPRT_PRTSPD(value uint32) { + volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x60000)|value<<17) +} +func (o *USB_Type) GetHPRT_PRTSPD() uint32 { + return (volatile.LoadUint32(&o.HPRT.Reg) & 0x60000) >> 17 +} + +// USB.HCCHAR0 +func (o *USB_Type) SetHCCHAR0_H_MPS0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR0_H_MPS0() uint32 { + return volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR0_H_EPNUM0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR0_H_EPNUM0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR0_H_EPDIR0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR0_H_EPDIR0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR0_H_LSPDDEV0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR0_H_LSPDDEV0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR0_H_EPTYPE0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR0_H_EPTYPE0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR0_H_EC0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR0_H_EC0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR0_H_DEVADDR0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR0_H_DEVADDR0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR0_H_ODDFRM0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR0_H_ODDFRM0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR0_H_CHDIS0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR0_H_CHDIS0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR0_H_CHENA0(value uint32) { + volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR0_H_CHENA0() uint32 { + return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT0 +func (o *USB_Type) SetHCINT0_H_XFERCOMPL0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT0_H_XFERCOMPL0() uint32 { + return volatile.LoadUint32(&o.HCINT0.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT0_H_CHHLTD0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT0_H_CHHLTD0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT0_H_AHBERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT0_H_AHBERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT0_H_STALL0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT0_H_STALL0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT0_H_NACK0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT0_H_NACK0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT0_H_ACK0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT0_H_ACK0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT0_H_NYET0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT0_H_NYET0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT0_H_XACTERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT0_H_XACTERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT0_H_BBLERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT0_H_BBLERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT0_H_FRMOVRUN0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT0_H_FRMOVRUN0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT0_H_DATATGLERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT0_H_DATATGLERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT0_H_BNAINTR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT0_H_BNAINTR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT0_H_XCS_XACT_ERR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT0_H_XCS_XACT_ERR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT0_H_DESC_LST_ROLLINTR0(value uint32) { + volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT0_H_DESC_LST_ROLLINTR0() uint32 { + return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK0 +func (o *USB_Type) SetHCINTMSK0_H_XFERCOMPLMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK0_H_XFERCOMPLMSK0() uint32 { + return volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK0_H_CHHLTDMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK0_H_CHHLTDMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK0_H_AHBERRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK0_H_AHBERRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK0_H_STALLMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK0_H_STALLMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK0_H_NAKMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK0_H_NAKMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK0_H_ACKMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK0_H_ACKMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK0_H_NYETMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK0_H_NYETMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK0_H_XACTERRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK0_H_XACTERRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK0_H_BBLERRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK0_H_BBLERRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK0_H_FRMOVRUNMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK0_H_FRMOVRUNMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK0_H_DATATGLERRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK0_H_DATATGLERRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK0_H_BNAINTRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK0_H_BNAINTRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK0_H_DESC_LST_ROLLINTRMSK0(value uint32) { + volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK0_H_DESC_LST_ROLLINTRMSK0() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ0 +func (o *USB_Type) SetHCTSIZ0_H_XFERSIZE0(value uint32) { + volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ0_H_XFERSIZE0() uint32 { + return volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ0_H_PKTCNT0(value uint32) { + volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ0_H_PKTCNT0() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ0_H_PID0(value uint32) { + volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ0_H_PID0() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ0_H_DOPNG0(value uint32) { + volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ0_H_DOPNG0() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA0 +func (o *USB_Type) SetHCDMA0(value uint32) { + volatile.StoreUint32(&o.HCDMA0.Reg, value) +} +func (o *USB_Type) GetHCDMA0() uint32 { + return volatile.LoadUint32(&o.HCDMA0.Reg) +} + +// USB.HCDMAB0 +func (o *USB_Type) SetHCDMAB0(value uint32) { + volatile.StoreUint32(&o.HCDMAB0.Reg, value) +} +func (o *USB_Type) GetHCDMAB0() uint32 { + return volatile.LoadUint32(&o.HCDMAB0.Reg) +} + +// USB.HCCHAR1 +func (o *USB_Type) SetHCCHAR1_H_MPS1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR1_H_MPS1() uint32 { + return volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR1_H_EPNUM1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR1_H_EPNUM1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR1_H_EPDIR1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR1_H_EPDIR1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR1_H_LSPDDEV1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR1_H_LSPDDEV1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR1_H_EPTYPE1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR1_H_EPTYPE1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR1_H_EC1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR1_H_EC1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR1_H_DEVADDR1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR1_H_DEVADDR1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR1_H_ODDFRM1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR1_H_ODDFRM1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR1_H_CHDIS1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR1_H_CHDIS1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR1_H_CHENA1(value uint32) { + volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR1_H_CHENA1() uint32 { + return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT1 +func (o *USB_Type) SetHCINT1_H_XFERCOMPL1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT1_H_XFERCOMPL1() uint32 { + return volatile.LoadUint32(&o.HCINT1.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT1_H_CHHLTD1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT1_H_CHHLTD1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT1_H_AHBERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT1_H_AHBERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT1_H_STALL1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT1_H_STALL1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT1_H_NACK1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT1_H_NACK1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT1_H_ACK1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT1_H_ACK1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT1_H_NYET1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT1_H_NYET1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT1_H_XACTERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT1_H_XACTERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT1_H_BBLERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT1_H_BBLERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT1_H_FRMOVRUN1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT1_H_FRMOVRUN1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT1_H_DATATGLERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT1_H_DATATGLERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT1_H_BNAINTR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT1_H_BNAINTR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT1_H_XCS_XACT_ERR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT1_H_XCS_XACT_ERR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT1_H_DESC_LST_ROLLINTR1(value uint32) { + volatile.StoreUint32(&o.HCINT1.Reg, volatile.LoadUint32(&o.HCINT1.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT1_H_DESC_LST_ROLLINTR1() uint32 { + return (volatile.LoadUint32(&o.HCINT1.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK1 +func (o *USB_Type) SetHCINTMSK1_H_XFERCOMPLMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK1_H_XFERCOMPLMSK1() uint32 { + return volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK1_H_CHHLTDMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK1_H_CHHLTDMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK1_H_AHBERRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK1_H_AHBERRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK1_H_STALLMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK1_H_STALLMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK1_H_NAKMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK1_H_NAKMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK1_H_ACKMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK1_H_ACKMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK1_H_NYETMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK1_H_NYETMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK1_H_XACTERRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK1_H_XACTERRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK1_H_BBLERRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK1_H_BBLERRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK1_H_FRMOVRUNMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK1_H_FRMOVRUNMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK1_H_DATATGLERRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK1_H_DATATGLERRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK1_H_BNAINTRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK1_H_BNAINTRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK1_H_DESC_LST_ROLLINTRMSK1(value uint32) { + volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK1_H_DESC_LST_ROLLINTRMSK1() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ1 +func (o *USB_Type) SetHCTSIZ1_H_XFERSIZE1(value uint32) { + volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ1_H_XFERSIZE1() uint32 { + return volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ1_H_PKTCNT1(value uint32) { + volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ1_H_PKTCNT1() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ1_H_PID1(value uint32) { + volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ1_H_PID1() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ1_H_DOPNG1(value uint32) { + volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ1_H_DOPNG1() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA1 +func (o *USB_Type) SetHCDMA1(value uint32) { + volatile.StoreUint32(&o.HCDMA1.Reg, value) +} +func (o *USB_Type) GetHCDMA1() uint32 { + return volatile.LoadUint32(&o.HCDMA1.Reg) +} + +// USB.HCDMAB1 +func (o *USB_Type) SetHCDMAB1(value uint32) { + volatile.StoreUint32(&o.HCDMAB1.Reg, value) +} +func (o *USB_Type) GetHCDMAB1() uint32 { + return volatile.LoadUint32(&o.HCDMAB1.Reg) +} + +// USB.HCCHAR2 +func (o *USB_Type) SetHCCHAR2_H_MPS2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR2_H_MPS2() uint32 { + return volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR2_H_EPNUM2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR2_H_EPNUM2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR2_H_EPDIR2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR2_H_EPDIR2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR2_H_LSPDDEV2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR2_H_LSPDDEV2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR2_H_EPTYPE2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR2_H_EPTYPE2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR2_H_EC2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR2_H_EC2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR2_H_DEVADDR2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR2_H_DEVADDR2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR2_H_ODDFRM2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR2_H_ODDFRM2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR2_H_CHDIS2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR2_H_CHDIS2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR2_H_CHENA2(value uint32) { + volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR2_H_CHENA2() uint32 { + return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT2 +func (o *USB_Type) SetHCINT2_H_XFERCOMPL2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT2_H_XFERCOMPL2() uint32 { + return volatile.LoadUint32(&o.HCINT2.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT2_H_CHHLTD2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT2_H_CHHLTD2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT2_H_AHBERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT2_H_AHBERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT2_H_STALL2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT2_H_STALL2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT2_H_NACK2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT2_H_NACK2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT2_H_ACK2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT2_H_ACK2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT2_H_NYET2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT2_H_NYET2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT2_H_XACTERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT2_H_XACTERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT2_H_BBLERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT2_H_BBLERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT2_H_FRMOVRUN2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT2_H_FRMOVRUN2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT2_H_DATATGLERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT2_H_DATATGLERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT2_H_BNAINTR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT2_H_BNAINTR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT2_H_XCS_XACT_ERR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT2_H_XCS_XACT_ERR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT2_H_DESC_LST_ROLLINTR2(value uint32) { + volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT2_H_DESC_LST_ROLLINTR2() uint32 { + return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK2 +func (o *USB_Type) SetHCINTMSK2_H_XFERCOMPLMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK2_H_XFERCOMPLMSK2() uint32 { + return volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK2_H_CHHLTDMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK2_H_CHHLTDMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK2_H_AHBERRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK2_H_AHBERRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK2_H_STALLMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK2_H_STALLMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK2_H_NAKMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK2_H_NAKMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK2_H_ACKMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK2_H_ACKMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK2_H_NYETMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK2_H_NYETMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK2_H_XACTERRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK2_H_XACTERRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK2_H_BBLERRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK2_H_BBLERRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK2_H_FRMOVRUNMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK2_H_FRMOVRUNMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK2_H_DATATGLERRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK2_H_DATATGLERRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK2_H_BNAINTRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK2_H_BNAINTRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK2_H_DESC_LST_ROLLINTRMSK2(value uint32) { + volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK2_H_DESC_LST_ROLLINTRMSK2() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ2 +func (o *USB_Type) SetHCTSIZ2_H_XFERSIZE2(value uint32) { + volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ2_H_XFERSIZE2() uint32 { + return volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ2_H_PKTCNT2(value uint32) { + volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ2_H_PKTCNT2() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ2_H_PID2(value uint32) { + volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ2_H_PID2() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ2_H_DOPNG2(value uint32) { + volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ2_H_DOPNG2() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA2 +func (o *USB_Type) SetHCDMA2(value uint32) { + volatile.StoreUint32(&o.HCDMA2.Reg, value) +} +func (o *USB_Type) GetHCDMA2() uint32 { + return volatile.LoadUint32(&o.HCDMA2.Reg) +} + +// USB.HCDMAB2 +func (o *USB_Type) SetHCDMAB2(value uint32) { + volatile.StoreUint32(&o.HCDMAB2.Reg, value) +} +func (o *USB_Type) GetHCDMAB2() uint32 { + return volatile.LoadUint32(&o.HCDMAB2.Reg) +} + +// USB.HCCHAR3 +func (o *USB_Type) SetHCCHAR3_H_MPS3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR3_H_MPS3() uint32 { + return volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR3_H_EPNUM3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR3_H_EPNUM3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR3_H_EPDIR3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR3_H_EPDIR3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR3_H_LSPDDEV3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR3_H_LSPDDEV3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR3_H_EPTYPE3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR3_H_EPTYPE3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR3_H_EC3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR3_H_EC3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR3_H_DEVADDR3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR3_H_DEVADDR3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR3_H_ODDFRM3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR3_H_ODDFRM3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR3_H_CHDIS3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR3_H_CHDIS3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR3_H_CHENA3(value uint32) { + volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR3_H_CHENA3() uint32 { + return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT3 +func (o *USB_Type) SetHCINT3_H_XFERCOMPL3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT3_H_XFERCOMPL3() uint32 { + return volatile.LoadUint32(&o.HCINT3.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT3_H_CHHLTD3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT3_H_CHHLTD3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT3_H_AHBERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT3_H_AHBERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT3_H_STALL3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT3_H_STALL3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT3_H_NACK3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT3_H_NACK3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT3_H_ACK3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT3_H_ACK3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT3_H_NYET3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT3_H_NYET3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT3_H_XACTERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT3_H_XACTERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT3_H_BBLERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT3_H_BBLERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT3_H_FRMOVRUN3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT3_H_FRMOVRUN3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT3_H_DATATGLERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT3_H_DATATGLERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT3_H_BNAINTR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT3_H_BNAINTR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT3_H_XCS_XACT_ERR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT3_H_XCS_XACT_ERR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT3_H_DESC_LST_ROLLINTR3(value uint32) { + volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT3_H_DESC_LST_ROLLINTR3() uint32 { + return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK3 +func (o *USB_Type) SetHCINTMSK3_H_XFERCOMPLMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK3_H_XFERCOMPLMSK3() uint32 { + return volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK3_H_CHHLTDMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK3_H_CHHLTDMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK3_H_AHBERRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK3_H_AHBERRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK3_H_STALLMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK3_H_STALLMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK3_H_NAKMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK3_H_NAKMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK3_H_ACKMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK3_H_ACKMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK3_H_NYETMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK3_H_NYETMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK3_H_XACTERRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK3_H_XACTERRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK3_H_BBLERRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK3_H_BBLERRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK3_H_FRMOVRUNMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK3_H_FRMOVRUNMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK3_H_DATATGLERRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK3_H_DATATGLERRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK3_H_BNAINTRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK3_H_BNAINTRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK3_H_DESC_LST_ROLLINTRMSK3(value uint32) { + volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK3_H_DESC_LST_ROLLINTRMSK3() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ3 +func (o *USB_Type) SetHCTSIZ3_H_XFERSIZE3(value uint32) { + volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ3_H_XFERSIZE3() uint32 { + return volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ3_H_PKTCNT3(value uint32) { + volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ3_H_PKTCNT3() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ3_H_PID3(value uint32) { + volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ3_H_PID3() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ3_H_DOPNG3(value uint32) { + volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ3_H_DOPNG3() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA3 +func (o *USB_Type) SetHCDMA3(value uint32) { + volatile.StoreUint32(&o.HCDMA3.Reg, value) +} +func (o *USB_Type) GetHCDMA3() uint32 { + return volatile.LoadUint32(&o.HCDMA3.Reg) +} + +// USB.HCDMAB3 +func (o *USB_Type) SetHCDMAB3(value uint32) { + volatile.StoreUint32(&o.HCDMAB3.Reg, value) +} +func (o *USB_Type) GetHCDMAB3() uint32 { + return volatile.LoadUint32(&o.HCDMAB3.Reg) +} + +// USB.HCCHAR4 +func (o *USB_Type) SetHCCHAR4_H_MPS4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR4_H_MPS4() uint32 { + return volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR4_H_EPNUM4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR4_H_EPNUM4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR4_H_EPDIR4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR4_H_EPDIR4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR4_H_LSPDDEV4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR4_H_LSPDDEV4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR4_H_EPTYPE4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR4_H_EPTYPE4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR4_H_EC4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR4_H_EC4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR4_H_DEVADDR4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR4_H_DEVADDR4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR4_H_ODDFRM4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR4_H_ODDFRM4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR4_H_CHDIS4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR4_H_CHDIS4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR4_H_CHENA4(value uint32) { + volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR4_H_CHENA4() uint32 { + return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT4 +func (o *USB_Type) SetHCINT4_H_XFERCOMPL4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT4_H_XFERCOMPL4() uint32 { + return volatile.LoadUint32(&o.HCINT4.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT4_H_CHHLTD4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT4_H_CHHLTD4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT4_H_AHBERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT4_H_AHBERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT4_H_STALL4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT4_H_STALL4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT4_H_NACK4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT4_H_NACK4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT4_H_ACK4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT4_H_ACK4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT4_H_NYET4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT4_H_NYET4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT4_H_XACTERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT4_H_XACTERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT4_H_BBLERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT4_H_BBLERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT4_H_FRMOVRUN4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT4_H_FRMOVRUN4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT4_H_DATATGLERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT4_H_DATATGLERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT4_H_BNAINTR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT4_H_BNAINTR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT4_H_XCS_XACT_ERR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT4_H_XCS_XACT_ERR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT4_H_DESC_LST_ROLLINTR4(value uint32) { + volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT4_H_DESC_LST_ROLLINTR4() uint32 { + return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK4 +func (o *USB_Type) SetHCINTMSK4_H_XFERCOMPLMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK4_H_XFERCOMPLMSK4() uint32 { + return volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK4_H_CHHLTDMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK4_H_CHHLTDMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK4_H_AHBERRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK4_H_AHBERRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK4_H_STALLMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK4_H_STALLMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK4_H_NAKMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK4_H_NAKMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK4_H_ACKMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK4_H_ACKMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK4_H_NYETMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK4_H_NYETMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK4_H_XACTERRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK4_H_XACTERRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK4_H_BBLERRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK4_H_BBLERRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK4_H_FRMOVRUNMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK4_H_FRMOVRUNMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK4_H_DATATGLERRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK4_H_DATATGLERRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK4_H_BNAINTRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK4_H_BNAINTRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK4_H_DESC_LST_ROLLINTRMSK4(value uint32) { + volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK4_H_DESC_LST_ROLLINTRMSK4() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ4 +func (o *USB_Type) SetHCTSIZ4_H_XFERSIZE4(value uint32) { + volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ4_H_XFERSIZE4() uint32 { + return volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ4_H_PKTCNT4(value uint32) { + volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ4_H_PKTCNT4() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ4_H_PID4(value uint32) { + volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ4_H_PID4() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ4_H_DOPNG4(value uint32) { + volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ4_H_DOPNG4() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA4 +func (o *USB_Type) SetHCDMA4(value uint32) { + volatile.StoreUint32(&o.HCDMA4.Reg, value) +} +func (o *USB_Type) GetHCDMA4() uint32 { + return volatile.LoadUint32(&o.HCDMA4.Reg) +} + +// USB.HCDMAB4 +func (o *USB_Type) SetHCDMAB4(value uint32) { + volatile.StoreUint32(&o.HCDMAB4.Reg, value) +} +func (o *USB_Type) GetHCDMAB4() uint32 { + return volatile.LoadUint32(&o.HCDMAB4.Reg) +} + +// USB.HCCHAR5 +func (o *USB_Type) SetHCCHAR5_H_MPS5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR5_H_MPS5() uint32 { + return volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR5_H_EPNUM5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR5_H_EPNUM5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR5_H_EPDIR5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR5_H_EPDIR5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR5_H_LSPDDEV5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR5_H_LSPDDEV5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR5_H_EPTYPE5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR5_H_EPTYPE5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR5_H_EC5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR5_H_EC5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR5_H_DEVADDR5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR5_H_DEVADDR5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR5_H_ODDFRM5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR5_H_ODDFRM5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR5_H_CHDIS5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR5_H_CHDIS5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR5_H_CHENA5(value uint32) { + volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR5_H_CHENA5() uint32 { + return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT5 +func (o *USB_Type) SetHCINT5_H_XFERCOMPL5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT5_H_XFERCOMPL5() uint32 { + return volatile.LoadUint32(&o.HCINT5.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT5_H_CHHLTD5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT5_H_CHHLTD5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT5_H_AHBERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT5_H_AHBERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT5_H_STALL5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT5_H_STALL5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT5_H_NACK5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT5_H_NACK5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT5_H_ACK5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT5_H_ACK5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT5_H_NYET5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT5_H_NYET5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT5_H_XACTERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT5_H_XACTERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT5_H_BBLERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT5_H_BBLERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT5_H_FRMOVRUN5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT5_H_FRMOVRUN5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT5_H_DATATGLERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT5_H_DATATGLERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT5_H_BNAINTR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT5_H_BNAINTR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT5_H_XCS_XACT_ERR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT5_H_XCS_XACT_ERR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT5_H_DESC_LST_ROLLINTR5(value uint32) { + volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT5_H_DESC_LST_ROLLINTR5() uint32 { + return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK5 +func (o *USB_Type) SetHCINTMSK5_H_XFERCOMPLMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK5_H_XFERCOMPLMSK5() uint32 { + return volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK5_H_CHHLTDMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK5_H_CHHLTDMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK5_H_AHBERRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK5_H_AHBERRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK5_H_STALLMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK5_H_STALLMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK5_H_NAKMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK5_H_NAKMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK5_H_ACKMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK5_H_ACKMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK5_H_NYETMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK5_H_NYETMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK5_H_XACTERRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK5_H_XACTERRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK5_H_BBLERRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK5_H_BBLERRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK5_H_FRMOVRUNMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK5_H_FRMOVRUNMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK5_H_DATATGLERRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK5_H_DATATGLERRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK5_H_BNAINTRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK5_H_BNAINTRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK5_H_DESC_LST_ROLLINTRMSK5(value uint32) { + volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK5_H_DESC_LST_ROLLINTRMSK5() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ5 +func (o *USB_Type) SetHCTSIZ5_H_XFERSIZE5(value uint32) { + volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ5_H_XFERSIZE5() uint32 { + return volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ5_H_PKTCNT5(value uint32) { + volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ5_H_PKTCNT5() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ5_H_PID5(value uint32) { + volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ5_H_PID5() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ5_H_DOPNG5(value uint32) { + volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ5_H_DOPNG5() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA5 +func (o *USB_Type) SetHCDMA5(value uint32) { + volatile.StoreUint32(&o.HCDMA5.Reg, value) +} +func (o *USB_Type) GetHCDMA5() uint32 { + return volatile.LoadUint32(&o.HCDMA5.Reg) +} + +// USB.HCDMAB5 +func (o *USB_Type) SetHCDMAB5(value uint32) { + volatile.StoreUint32(&o.HCDMAB5.Reg, value) +} +func (o *USB_Type) GetHCDMAB5() uint32 { + return volatile.LoadUint32(&o.HCDMAB5.Reg) +} + +// USB.HCCHAR6 +func (o *USB_Type) SetHCCHAR6_H_MPS6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR6_H_MPS6() uint32 { + return volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR6_H_EPNUM6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR6_H_EPNUM6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR6_H_EPDIR6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR6_H_EPDIR6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR6_H_LSPDDEV6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR6_H_LSPDDEV6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR6_H_EPTYPE6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR6_H_EPTYPE6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR6_H_EC6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR6_H_EC6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR6_H_DEVADDR6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR6_H_DEVADDR6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR6_H_ODDFRM6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR6_H_ODDFRM6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR6_H_CHDIS6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR6_H_CHDIS6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR6_H_CHENA6(value uint32) { + volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR6_H_CHENA6() uint32 { + return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT6 +func (o *USB_Type) SetHCINT6_H_XFERCOMPL6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT6_H_XFERCOMPL6() uint32 { + return volatile.LoadUint32(&o.HCINT6.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT6_H_CHHLTD6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT6_H_CHHLTD6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT6_H_AHBERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT6_H_AHBERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT6_H_STALL6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT6_H_STALL6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT6_H_NACK6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT6_H_NACK6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT6_H_ACK6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT6_H_ACK6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT6_H_NYET6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT6_H_NYET6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT6_H_XACTERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT6_H_XACTERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT6_H_BBLERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT6_H_BBLERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT6_H_FRMOVRUN6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT6_H_FRMOVRUN6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT6_H_DATATGLERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT6_H_DATATGLERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT6_H_BNAINTR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT6_H_BNAINTR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT6_H_XCS_XACT_ERR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT6_H_XCS_XACT_ERR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT6_H_DESC_LST_ROLLINTR6(value uint32) { + volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT6_H_DESC_LST_ROLLINTR6() uint32 { + return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK6 +func (o *USB_Type) SetHCINTMSK6_H_XFERCOMPLMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK6_H_XFERCOMPLMSK6() uint32 { + return volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK6_H_CHHLTDMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK6_H_CHHLTDMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK6_H_AHBERRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK6_H_AHBERRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK6_H_STALLMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK6_H_STALLMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK6_H_NAKMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK6_H_NAKMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK6_H_ACKMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK6_H_ACKMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK6_H_NYETMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK6_H_NYETMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK6_H_XACTERRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK6_H_XACTERRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK6_H_BBLERRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK6_H_BBLERRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK6_H_FRMOVRUNMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK6_H_FRMOVRUNMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK6_H_DATATGLERRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK6_H_DATATGLERRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK6_H_BNAINTRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK6_H_BNAINTRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK6_H_DESC_LST_ROLLINTRMSK6(value uint32) { + volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK6_H_DESC_LST_ROLLINTRMSK6() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ6 +func (o *USB_Type) SetHCTSIZ6_H_XFERSIZE6(value uint32) { + volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ6_H_XFERSIZE6() uint32 { + return volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ6_H_PKTCNT6(value uint32) { + volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ6_H_PKTCNT6() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ6_H_PID6(value uint32) { + volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ6_H_PID6() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ6_H_DOPNG6(value uint32) { + volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ6_H_DOPNG6() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA6 +func (o *USB_Type) SetHCDMA6(value uint32) { + volatile.StoreUint32(&o.HCDMA6.Reg, value) +} +func (o *USB_Type) GetHCDMA6() uint32 { + return volatile.LoadUint32(&o.HCDMA6.Reg) +} + +// USB.HCDMAB6 +func (o *USB_Type) SetHCDMAB6(value uint32) { + volatile.StoreUint32(&o.HCDMAB6.Reg, value) +} +func (o *USB_Type) GetHCDMAB6() uint32 { + return volatile.LoadUint32(&o.HCDMAB6.Reg) +} + +// USB.HCCHAR7 +func (o *USB_Type) SetHCCHAR7_H_MPS7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetHCCHAR7_H_MPS7() uint32 { + return volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x7ff +} +func (o *USB_Type) SetHCCHAR7_H_EPNUM7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x7800)|value<<11) +} +func (o *USB_Type) GetHCCHAR7_H_EPNUM7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x7800) >> 11 +} +func (o *USB_Type) SetHCCHAR7_H_EPDIR7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetHCCHAR7_H_EPDIR7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetHCCHAR7_H_LSPDDEV7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetHCCHAR7_H_LSPDDEV7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetHCCHAR7_H_EPTYPE7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetHCCHAR7_H_EPTYPE7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetHCCHAR7_H_EC7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetHCCHAR7_H_EC7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetHCCHAR7_H_DEVADDR7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x1fc00000)|value<<22) +} +func (o *USB_Type) GetHCCHAR7_H_DEVADDR7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x1fc00000) >> 22 +} +func (o *USB_Type) SetHCCHAR7_H_ODDFRM7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetHCCHAR7_H_ODDFRM7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetHCCHAR7_H_CHDIS7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetHCCHAR7_H_CHDIS7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetHCCHAR7_H_CHENA7(value uint32) { + volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCCHAR7_H_CHENA7() uint32 { + return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x80000000) >> 31 +} + +// USB.HCINT7 +func (o *USB_Type) SetHCINT7_H_XFERCOMPL7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINT7_H_XFERCOMPL7() uint32 { + return volatile.LoadUint32(&o.HCINT7.Reg) & 0x1 +} +func (o *USB_Type) SetHCINT7_H_CHHLTD7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINT7_H_CHHLTD7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINT7_H_AHBERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINT7_H_AHBERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINT7_H_STALL7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINT7_H_STALL7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINT7_H_NACK7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINT7_H_NACK7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINT7_H_ACK7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINT7_H_ACK7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINT7_H_NYET7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINT7_H_NYET7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINT7_H_XACTERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINT7_H_XACTERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINT7_H_BBLERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINT7_H_BBLERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINT7_H_FRMOVRUN7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINT7_H_FRMOVRUN7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINT7_H_DATATGLERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINT7_H_DATATGLERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINT7_H_BNAINTR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINT7_H_BNAINTR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINT7_H_XCS_XACT_ERR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetHCINT7_H_XCS_XACT_ERR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetHCINT7_H_DESC_LST_ROLLINTR7(value uint32) { + volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINT7_H_DESC_LST_ROLLINTR7() uint32 { + return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x2000) >> 13 +} + +// USB.HCINTMSK7 +func (o *USB_Type) SetHCINTMSK7_H_XFERCOMPLMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetHCINTMSK7_H_XFERCOMPLMSK7() uint32 { + return volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x1 +} +func (o *USB_Type) SetHCINTMSK7_H_CHHLTDMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetHCINTMSK7_H_CHHLTDMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetHCINTMSK7_H_AHBERRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetHCINTMSK7_H_AHBERRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetHCINTMSK7_H_STALLMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetHCINTMSK7_H_STALLMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetHCINTMSK7_H_NAKMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetHCINTMSK7_H_NAKMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetHCINTMSK7_H_ACKMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetHCINTMSK7_H_ACKMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetHCINTMSK7_H_NYETMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetHCINTMSK7_H_NYETMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetHCINTMSK7_H_XACTERRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetHCINTMSK7_H_XACTERRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetHCINTMSK7_H_BBLERRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetHCINTMSK7_H_BBLERRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetHCINTMSK7_H_FRMOVRUNMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetHCINTMSK7_H_FRMOVRUNMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetHCINTMSK7_H_DATATGLERRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetHCINTMSK7_H_DATATGLERRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetHCINTMSK7_H_BNAINTRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetHCINTMSK7_H_BNAINTRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetHCINTMSK7_H_DESC_LST_ROLLINTRMSK7(value uint32) { + volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetHCINTMSK7_H_DESC_LST_ROLLINTRMSK7() uint32 { + return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x2000) >> 13 +} + +// USB.HCTSIZ7 +func (o *USB_Type) SetHCTSIZ7_H_XFERSIZE7(value uint32) { + volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x7ffff)|value) +} +func (o *USB_Type) GetHCTSIZ7_H_XFERSIZE7() uint32 { + return volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x7ffff +} +func (o *USB_Type) SetHCTSIZ7_H_PKTCNT7(value uint32) { + volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x1ff80000)|value<<19) +} +func (o *USB_Type) GetHCTSIZ7_H_PKTCNT7() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x1ff80000) >> 19 +} +func (o *USB_Type) SetHCTSIZ7_H_PID7(value uint32) { + volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetHCTSIZ7_H_PID7() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x60000000) >> 29 +} +func (o *USB_Type) SetHCTSIZ7_H_DOPNG7(value uint32) { + volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetHCTSIZ7_H_DOPNG7() uint32 { + return (volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x80000000) >> 31 +} + +// USB.HCDMA7 +func (o *USB_Type) SetHCDMA7(value uint32) { + volatile.StoreUint32(&o.HCDMA7.Reg, value) +} +func (o *USB_Type) GetHCDMA7() uint32 { + return volatile.LoadUint32(&o.HCDMA7.Reg) +} + +// USB.HCDMAB7 +func (o *USB_Type) SetHCDMAB7(value uint32) { + volatile.StoreUint32(&o.HCDMAB7.Reg, value) +} +func (o *USB_Type) GetHCDMAB7() uint32 { + return volatile.LoadUint32(&o.HCDMAB7.Reg) +} + +// USB.DCFG +func (o *USB_Type) SetDCFG_NZSTSOUTHSHK(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDCFG_NZSTSOUTHSHK() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDCFG_ENA32KHZSUSP(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDCFG_ENA32KHZSUSP() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDCFG_DEVADDR(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x7f0)|value<<4) +} +func (o *USB_Type) GetDCFG_DEVADDR() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x7f0) >> 4 +} +func (o *USB_Type) SetDCFG_PERFRLINT(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x1800)|value<<11) +} +func (o *USB_Type) GetDCFG_PERFRLINT() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x1800) >> 11 +} +func (o *USB_Type) SetDCFG_ENDEVOUTNAK(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDCFG_ENDEVOUTNAK() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDCFG_XCVRDLY(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDCFG_XCVRDLY() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDCFG_ERRATICINTMSK(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDCFG_ERRATICINTMSK() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDCFG_EPMISCNT(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x7c0000)|value<<18) +} +func (o *USB_Type) GetDCFG_EPMISCNT() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x7c0000) >> 18 +} +func (o *USB_Type) SetDCFG_DESCDMA(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x800000)|value<<23) +} +func (o *USB_Type) GetDCFG_DESCDMA() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x800000) >> 23 +} +func (o *USB_Type) SetDCFG_PERSCHINTVL(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x3000000)|value<<24) +} +func (o *USB_Type) GetDCFG_PERSCHINTVL() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0x3000000) >> 24 +} +func (o *USB_Type) SetDCFG_RESVALID(value uint32) { + volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0xfc000000)|value<<26) +} +func (o *USB_Type) GetDCFG_RESVALID() uint32 { + return (volatile.LoadUint32(&o.DCFG.Reg) & 0xfc000000) >> 26 +} + +// USB.DCTL +func (o *USB_Type) SetDCTL_RMTWKUPSIG(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDCTL_RMTWKUPSIG() uint32 { + return volatile.LoadUint32(&o.DCTL.Reg) & 0x1 +} +func (o *USB_Type) SetDCTL_SFTDISCON(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDCTL_SFTDISCON() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDCTL_GNPINNAKSTS(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDCTL_GNPINNAKSTS() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDCTL_GOUTNAKSTS(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDCTL_GOUTNAKSTS() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDCTL_TSTCTL(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x70)|value<<4) +} +func (o *USB_Type) GetDCTL_TSTCTL() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x70) >> 4 +} +func (o *USB_Type) SetDCTL_SGNPINNAK(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDCTL_SGNPINNAK() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDCTL_CGNPINNAK(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDCTL_CGNPINNAK() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDCTL_SGOUTNAK(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDCTL_SGOUTNAK() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDCTL_CGOUTNAK(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x400)|value<<10) +} +func (o *USB_Type) GetDCTL_CGOUTNAK() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x400) >> 10 +} +func (o *USB_Type) SetDCTL_PWRONPRGDONE(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDCTL_PWRONPRGDONE() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDCTL_GMC(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x6000)|value<<13) +} +func (o *USB_Type) GetDCTL_GMC() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x6000) >> 13 +} +func (o *USB_Type) SetDCTL_IGNRFRMNUM(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDCTL_IGNRFRMNUM() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDCTL_NAKONBBLE(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetDCTL_NAKONBBLE() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetDCTL_ENCOUNTONBNA(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDCTL_ENCOUNTONBNA() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDCTL_DEEPSLEEPBESLREJECT(value uint32) { + volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetDCTL_DEEPSLEEPBESLREJECT() uint32 { + return (volatile.LoadUint32(&o.DCTL.Reg) & 0x40000) >> 18 +} + +// USB.DSTS +func (o *USB_Type) SetDSTS_SUSPSTS(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDSTS_SUSPSTS() uint32 { + return volatile.LoadUint32(&o.DSTS.Reg) & 0x1 +} +func (o *USB_Type) SetDSTS_ENUMSPD(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x6)|value<<1) +} +func (o *USB_Type) GetDSTS_ENUMSPD() uint32 { + return (volatile.LoadUint32(&o.DSTS.Reg) & 0x6) >> 1 +} +func (o *USB_Type) SetDSTS_ERRTICERR(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDSTS_ERRTICERR() uint32 { + return (volatile.LoadUint32(&o.DSTS.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDSTS_SOFFN(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x3fff00)|value<<8) +} +func (o *USB_Type) GetDSTS_SOFFN() uint32 { + return (volatile.LoadUint32(&o.DSTS.Reg) & 0x3fff00) >> 8 +} +func (o *USB_Type) SetDSTS_DEVLNSTS(value uint32) { + volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0xc00000)|value<<22) +} +func (o *USB_Type) GetDSTS_DEVLNSTS() uint32 { + return (volatile.LoadUint32(&o.DSTS.Reg) & 0xc00000) >> 22 +} + +// USB.DIEPMSK +func (o *USB_Type) SetDIEPMSK_DI_XFERCOMPLMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPMSK_DI_XFERCOMPLMSK() uint32 { + return volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPMSK_DI_EPDISBLDMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPMSK_DI_EPDISBLDMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPMSK_DI_AHBERMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPMSK_DI_AHBERMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPMSK_TIMEOUTMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPMSK_TIMEOUTMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPMSK_INTKNTXFEMPMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPMSK_INTKNTXFEMPMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPMSK_INTKNEPMISMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPMSK_INTKNEPMISMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPMSK_INEPNAKEFFMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPMSK_INEPNAKEFFMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPMSK_TXFIFOUNDRNMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPMSK_TXFIFOUNDRNMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPMSK_BNAININTRMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPMSK_BNAININTRMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPMSK_DI_NAKMSK(value uint32) { + volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPMSK_DI_NAKMSK() uint32 { + return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x2000) >> 13 +} + +// USB.DOEPMSK +func (o *USB_Type) SetDOEPMSK_XFERCOMPLMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPMSK_XFERCOMPLMSK() uint32 { + return volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPMSK_EPDISBLDMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPMSK_EPDISBLDMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPMSK_AHBERMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPMSK_AHBERMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPMSK_SETUPMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPMSK_SETUPMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPMSK_OUTTKNEPDISMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPMSK_OUTTKNEPDISMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPMSK_STSPHSERCVDMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPMSK_STSPHSERCVDMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPMSK_BACK2BACKSETUP(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPMSK_BACK2BACKSETUP() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPMSK_OUTPKTERRMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPMSK_OUTPKTERRMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPMSK_BNAOUTINTRMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPMSK_BNAOUTINTRMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPMSK_BBLEERRMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPMSK_BBLEERRMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPMSK_NAKMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPMSK_NAKMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPMSK_NYETMSK(value uint32) { + volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPMSK_NYETMSK() uint32 { + return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x4000) >> 14 +} + +// USB.DAINT +func (o *USB_Type) SetDAINT_INEPINT0(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDAINT_INEPINT0() uint32 { + return volatile.LoadUint32(&o.DAINT.Reg) & 0x1 +} +func (o *USB_Type) SetDAINT_INEPINT1(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDAINT_INEPINT1() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDAINT_INEPINT2(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDAINT_INEPINT2() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDAINT_INEPINT3(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDAINT_INEPINT3() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDAINT_INEPINT4(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDAINT_INEPINT4() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDAINT_INEPINT5(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDAINT_INEPINT5() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDAINT_INEPINT6(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDAINT_INEPINT6() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDAINT_OUTEPINT0(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetDAINT_OUTEPINT0() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetDAINT_OUTEPINT1(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDAINT_OUTEPINT1() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDAINT_OUTEPINT2(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetDAINT_OUTEPINT2() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetDAINT_OUTEPINT3(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDAINT_OUTEPINT3() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDAINT_OUTEPINT4(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDAINT_OUTEPINT4() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDAINT_OUTEPINT5(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDAINT_OUTEPINT5() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDAINT_OUTEPINT6(value uint32) { + volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetDAINT_OUTEPINT6() uint32 { + return (volatile.LoadUint32(&o.DAINT.Reg) & 0x400000) >> 22 +} + +// USB.DAINTMSK +func (o *USB_Type) SetDAINTMSK_INEPMSK0(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK0() uint32 { + return volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x1 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK1(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK1() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK2(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK2() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK3(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK3() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK4(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK4() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK5(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK5() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDAINTMSK_INEPMSK6(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDAINTMSK_INEPMSK6() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK0(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK0() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK1(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK1() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK2(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x40000)|value<<18) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK2() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x40000) >> 18 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK3(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK3() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK4(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK4() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK5(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK5() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDAINTMSK_OUTEPMSK6(value uint32) { + volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0x400000)|value<<22) +} +func (o *USB_Type) GetDAINTMSK_OUTEPMSK6() uint32 { + return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0x400000) >> 22 +} + +// USB.DVBUSDIS +func (o *USB_Type) SetDVBUSDIS(value uint32) { + volatile.StoreUint32(&o.DVBUSDIS.Reg, volatile.LoadUint32(&o.DVBUSDIS.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDVBUSDIS() uint32 { + return volatile.LoadUint32(&o.DVBUSDIS.Reg) & 0xffff +} + +// USB.DVBUSPULSE +func (o *USB_Type) SetDVBUSPULSE(value uint32) { + volatile.StoreUint32(&o.DVBUSPULSE.Reg, volatile.LoadUint32(&o.DVBUSPULSE.Reg)&^(0xfff)|value) +} +func (o *USB_Type) GetDVBUSPULSE() uint32 { + return volatile.LoadUint32(&o.DVBUSPULSE.Reg) & 0xfff +} + +// USB.DTHRCTL +func (o *USB_Type) SetDTHRCTL_NONISOTHREN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDTHRCTL_NONISOTHREN() uint32 { + return volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x1 +} +func (o *USB_Type) SetDTHRCTL_ISOTHREN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDTHRCTL_ISOTHREN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDTHRCTL_TXTHRLEN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x7fc)|value<<2) +} +func (o *USB_Type) GetDTHRCTL_TXTHRLEN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x7fc) >> 2 +} +func (o *USB_Type) SetDTHRCTL_AHBTHRRATIO(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x1800)|value<<11) +} +func (o *USB_Type) GetDTHRCTL_AHBTHRRATIO() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x1800) >> 11 +} +func (o *USB_Type) SetDTHRCTL_RXTHREN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x10000)|value<<16) +} +func (o *USB_Type) GetDTHRCTL_RXTHREN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x10000) >> 16 +} +func (o *USB_Type) SetDTHRCTL_RXTHRLEN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x3fe0000)|value<<17) +} +func (o *USB_Type) GetDTHRCTL_RXTHRLEN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x3fe0000) >> 17 +} +func (o *USB_Type) SetDTHRCTL_ARBPRKEN(value uint32) { + volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDTHRCTL_ARBPRKEN() uint32 { + return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x8000000) >> 27 +} + +// USB.DIEPEMPMSK +func (o *USB_Type) SetDIEPEMPMSK_D_INEPTXFEMPMSK(value uint32) { + volatile.StoreUint32(&o.DIEPEMPMSK.Reg, volatile.LoadUint32(&o.DIEPEMPMSK.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDIEPEMPMSK_D_INEPTXFEMPMSK() uint32 { + return volatile.LoadUint32(&o.DIEPEMPMSK.Reg) & 0xffff +} + +// USB.DIEPCTL0 +func (o *USB_Type) SetDIEPCTL0_D_MPS0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL0_D_MPS0() uint32 { + return volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL0_D_USBACTEP0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL0_D_USBACTEP0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL0_D_NAKSTS0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL0_D_NAKSTS0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL0_D_EPTYPE0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL0_D_EPTYPE0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL0_D_STALL0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL0_D_STALL0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL0_D_TXFNUM0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL0_D_TXFNUM0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL0_D_CNAK0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL0_D_CNAK0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL0_DI_SNAK0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL0_DI_SNAK0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL0_D_EPDIS0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL0_D_EPDIS0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL0_D_EPENA0(value uint32) { + volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL0_D_EPENA0() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT0 +func (o *USB_Type) SetDIEPINT0_D_XFERCOMPL0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT0_D_XFERCOMPL0() uint32 { + return volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT0_D_EPDISBLD0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT0_D_EPDISBLD0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT0_D_AHBERR0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT0_D_AHBERR0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT0_D_TIMEOUT0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT0_D_TIMEOUT0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT0_D_INTKNTXFEMP0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT0_D_INTKNTXFEMP0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT0_D_INTKNEPMIS0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT0_D_INTKNEPMIS0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT0_D_INEPNAKEFF0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT0_D_INEPNAKEFF0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT0_D_TXFEMP0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT0_D_TXFEMP0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT0_D_TXFIFOUNDRN0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT0_D_TXFIFOUNDRN0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT0_D_BNAINTR0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT0_D_BNAINTR0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT0_D_PKTDRPSTS0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT0_D_PKTDRPSTS0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT0_D_BBLEERR0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT0_D_BBLEERR0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT0_D_NAKINTRPT0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT0_D_NAKINTRPT0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT0_D_NYETINTRPT0(value uint32) { + volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT0_D_NYETINTRPT0() uint32 { + return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ0 +func (o *USB_Type) SetDIEPTSIZ0_D_XFERSIZE0(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ0.Reg, volatile.LoadUint32(&o.DIEPTSIZ0.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ0_D_XFERSIZE0() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ0.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ0_D_PKTCNT0(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ0.Reg, volatile.LoadUint32(&o.DIEPTSIZ0.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ0_D_PKTCNT0() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ0.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA0 +func (o *USB_Type) SetDIEPDMA0(value uint32) { + volatile.StoreUint32(&o.DIEPDMA0.Reg, value) +} +func (o *USB_Type) GetDIEPDMA0() uint32 { + return volatile.LoadUint32(&o.DIEPDMA0.Reg) +} + +// USB.DTXFSTS0 +func (o *USB_Type) SetDTXFSTS0_D_INEPTXFSPCAVAIL0(value uint32) { + volatile.StoreUint32(&o.DTXFSTS0.Reg, volatile.LoadUint32(&o.DTXFSTS0.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS0_D_INEPTXFSPCAVAIL0() uint32 { + return volatile.LoadUint32(&o.DTXFSTS0.Reg) & 0xffff +} + +// USB.DIEPDMAB0 +func (o *USB_Type) SetDIEPDMAB0(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB0.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB0() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB0.Reg) +} + +// USB.DIEPCTL1 +func (o *USB_Type) SetDIEPCTL1_D_MPS1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL1_D_MPS1() uint32 { + return volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL1_D_USBACTEP1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL1_D_USBACTEP1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL1_D_NAKSTS1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL1_D_NAKSTS1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL1_D_EPTYPE1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL1_D_EPTYPE1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL1_D_STALL1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL1_D_STALL1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL1_D_TXFNUM1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL1_D_TXFNUM1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL1_D_CNAK1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL1_D_CNAK1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL1_DI_SNAK1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL1_DI_SNAK1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL1_DI_SETD0PID1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL1_DI_SETD0PID1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL1_DI_SETD1PID1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL1_DI_SETD1PID1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL1_D_EPDIS1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL1_D_EPDIS1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL1_D_EPENA1(value uint32) { + volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL1_D_EPENA1() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT1 +func (o *USB_Type) SetDIEPINT1_D_XFERCOMPL1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT1_D_XFERCOMPL1() uint32 { + return volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT1_D_EPDISBLD1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT1_D_EPDISBLD1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT1_D_AHBERR1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT1_D_AHBERR1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT1_D_TIMEOUT1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT1_D_TIMEOUT1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT1_D_INTKNTXFEMP1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT1_D_INTKNTXFEMP1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT1_D_INTKNEPMIS1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT1_D_INTKNEPMIS1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT1_D_INEPNAKEFF1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT1_D_INEPNAKEFF1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT1_D_TXFEMP1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT1_D_TXFEMP1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT1_D_TXFIFOUNDRN1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT1_D_TXFIFOUNDRN1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT1_D_BNAINTR1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT1_D_BNAINTR1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT1_D_PKTDRPSTS1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT1_D_PKTDRPSTS1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT1_D_BBLEERR1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT1_D_BBLEERR1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT1_D_NAKINTRPT1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT1_D_NAKINTRPT1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT1_D_NYETINTRPT1(value uint32) { + volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT1_D_NYETINTRPT1() uint32 { + return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ1 +func (o *USB_Type) SetDIEPTSIZ1_D_XFERSIZE1(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ1.Reg, volatile.LoadUint32(&o.DIEPTSIZ1.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ1_D_XFERSIZE1() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ1.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ1_D_PKTCNT1(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ1.Reg, volatile.LoadUint32(&o.DIEPTSIZ1.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ1_D_PKTCNT1() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ1.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA1 +func (o *USB_Type) SetDIEPDMA1(value uint32) { + volatile.StoreUint32(&o.DIEPDMA1.Reg, value) +} +func (o *USB_Type) GetDIEPDMA1() uint32 { + return volatile.LoadUint32(&o.DIEPDMA1.Reg) +} + +// USB.DTXFSTS1 +func (o *USB_Type) SetDTXFSTS1_D_INEPTXFSPCAVAIL1(value uint32) { + volatile.StoreUint32(&o.DTXFSTS1.Reg, volatile.LoadUint32(&o.DTXFSTS1.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS1_D_INEPTXFSPCAVAIL1() uint32 { + return volatile.LoadUint32(&o.DTXFSTS1.Reg) & 0xffff +} + +// USB.DIEPDMAB1 +func (o *USB_Type) SetDIEPDMAB1(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB1.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB1() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB1.Reg) +} + +// USB.DIEPCTL2 +func (o *USB_Type) SetDIEPCTL2_D_MPS2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL2_D_MPS2() uint32 { + return volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL2_D_USBACTEP2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL2_D_USBACTEP2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL2_D_NAKSTS2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL2_D_NAKSTS2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL2_D_EPTYPE2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL2_D_EPTYPE2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL2_D_STALL2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL2_D_STALL2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL2_D_TXFNUM2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL2_D_TXFNUM2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL2_D_CNAK2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL2_D_CNAK2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL2_DI_SNAK2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL2_DI_SNAK2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL2_DI_SETD0PID2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL2_DI_SETD0PID2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL2_DI_SETD1PID2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL2_DI_SETD1PID2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL2_D_EPDIS2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL2_D_EPDIS2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL2_D_EPENA2(value uint32) { + volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL2_D_EPENA2() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT2 +func (o *USB_Type) SetDIEPINT2_D_XFERCOMPL2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT2_D_XFERCOMPL2() uint32 { + return volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT2_D_EPDISBLD2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT2_D_EPDISBLD2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT2_D_AHBERR2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT2_D_AHBERR2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT2_D_TIMEOUT2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT2_D_TIMEOUT2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT2_D_INTKNTXFEMP2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT2_D_INTKNTXFEMP2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT2_D_INTKNEPMIS2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT2_D_INTKNEPMIS2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT2_D_INEPNAKEFF2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT2_D_INEPNAKEFF2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT2_D_TXFEMP2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT2_D_TXFEMP2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT2_D_TXFIFOUNDRN2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT2_D_TXFIFOUNDRN2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT2_D_BNAINTR2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT2_D_BNAINTR2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT2_D_PKTDRPSTS2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT2_D_PKTDRPSTS2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT2_D_BBLEERR2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT2_D_BBLEERR2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT2_D_NAKINTRPT2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT2_D_NAKINTRPT2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT2_D_NYETINTRPT2(value uint32) { + volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT2_D_NYETINTRPT2() uint32 { + return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ2 +func (o *USB_Type) SetDIEPTSIZ2_D_XFERSIZE2(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ2.Reg, volatile.LoadUint32(&o.DIEPTSIZ2.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ2_D_XFERSIZE2() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ2.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ2_D_PKTCNT2(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ2.Reg, volatile.LoadUint32(&o.DIEPTSIZ2.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ2_D_PKTCNT2() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ2.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA2 +func (o *USB_Type) SetDIEPDMA2(value uint32) { + volatile.StoreUint32(&o.DIEPDMA2.Reg, value) +} +func (o *USB_Type) GetDIEPDMA2() uint32 { + return volatile.LoadUint32(&o.DIEPDMA2.Reg) +} + +// USB.DTXFSTS2 +func (o *USB_Type) SetDTXFSTS2_D_INEPTXFSPCAVAIL2(value uint32) { + volatile.StoreUint32(&o.DTXFSTS2.Reg, volatile.LoadUint32(&o.DTXFSTS2.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS2_D_INEPTXFSPCAVAIL2() uint32 { + return volatile.LoadUint32(&o.DTXFSTS2.Reg) & 0xffff +} + +// USB.DIEPDMAB2 +func (o *USB_Type) SetDIEPDMAB2(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB2.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB2() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB2.Reg) +} + +// USB.DIEPCTL3 +func (o *USB_Type) SetDIEPCTL3_DI_MPS3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL3_DI_MPS3() uint32 { + return volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL3_DI_USBACTEP3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL3_DI_USBACTEP3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL3_DI_NAKSTS3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL3_DI_NAKSTS3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL3_DI_EPTYPE3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL3_DI_EPTYPE3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL3_DI_STALL3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL3_DI_STALL3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL3_DI_TXFNUM3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL3_DI_TXFNUM3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL3_DI_CNAK3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL3_DI_CNAK3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL3_DI_SNAK3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL3_DI_SNAK3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL3_DI_SETD0PID3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL3_DI_SETD0PID3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL3_DI_SETD1PID3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL3_DI_SETD1PID3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL3_DI_EPDIS3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL3_DI_EPDIS3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL3_DI_EPENA3(value uint32) { + volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL3_DI_EPENA3() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT3 +func (o *USB_Type) SetDIEPINT3_D_XFERCOMPL3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT3_D_XFERCOMPL3() uint32 { + return volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT3_D_EPDISBLD3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT3_D_EPDISBLD3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT3_D_AHBERR3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT3_D_AHBERR3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT3_D_TIMEOUT3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT3_D_TIMEOUT3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT3_D_INTKNTXFEMP3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT3_D_INTKNTXFEMP3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT3_D_INTKNEPMIS3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT3_D_INTKNEPMIS3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT3_D_INEPNAKEFF3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT3_D_INEPNAKEFF3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT3_D_TXFEMP3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT3_D_TXFEMP3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT3_D_TXFIFOUNDRN3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT3_D_TXFIFOUNDRN3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT3_D_BNAINTR3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT3_D_BNAINTR3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT3_D_PKTDRPSTS3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT3_D_PKTDRPSTS3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT3_D_BBLEERR3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT3_D_BBLEERR3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT3_D_NAKINTRPT3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT3_D_NAKINTRPT3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT3_D_NYETINTRPT3(value uint32) { + volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT3_D_NYETINTRPT3() uint32 { + return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ3 +func (o *USB_Type) SetDIEPTSIZ3_D_XFERSIZE3(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ3.Reg, volatile.LoadUint32(&o.DIEPTSIZ3.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ3_D_XFERSIZE3() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ3.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ3_D_PKTCNT3(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ3.Reg, volatile.LoadUint32(&o.DIEPTSIZ3.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ3_D_PKTCNT3() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ3.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA3 +func (o *USB_Type) SetDIEPDMA3(value uint32) { + volatile.StoreUint32(&o.DIEPDMA3.Reg, value) +} +func (o *USB_Type) GetDIEPDMA3() uint32 { + return volatile.LoadUint32(&o.DIEPDMA3.Reg) +} + +// USB.DTXFSTS3 +func (o *USB_Type) SetDTXFSTS3_D_INEPTXFSPCAVAIL3(value uint32) { + volatile.StoreUint32(&o.DTXFSTS3.Reg, volatile.LoadUint32(&o.DTXFSTS3.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS3_D_INEPTXFSPCAVAIL3() uint32 { + return volatile.LoadUint32(&o.DTXFSTS3.Reg) & 0xffff +} + +// USB.DIEPDMAB3 +func (o *USB_Type) SetDIEPDMAB3(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB3.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB3() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB3.Reg) +} + +// USB.DIEPCTL4 +func (o *USB_Type) SetDIEPCTL4_D_MPS4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL4_D_MPS4() uint32 { + return volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL4_D_USBACTEP4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL4_D_USBACTEP4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL4_D_NAKSTS4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL4_D_NAKSTS4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL4_D_EPTYPE4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL4_D_EPTYPE4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL4_D_STALL4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL4_D_STALL4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL4_D_TXFNUM4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL4_D_TXFNUM4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL4_D_CNAK4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL4_D_CNAK4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL4_DI_SNAK4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL4_DI_SNAK4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL4_DI_SETD0PID4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL4_DI_SETD0PID4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL4_DI_SETD1PID4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL4_DI_SETD1PID4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL4_D_EPDIS4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL4_D_EPDIS4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL4_D_EPENA4(value uint32) { + volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL4_D_EPENA4() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT4 +func (o *USB_Type) SetDIEPINT4_D_XFERCOMPL4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT4_D_XFERCOMPL4() uint32 { + return volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT4_D_EPDISBLD4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT4_D_EPDISBLD4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT4_D_AHBERR4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT4_D_AHBERR4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT4_D_TIMEOUT4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT4_D_TIMEOUT4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT4_D_INTKNTXFEMP4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT4_D_INTKNTXFEMP4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT4_D_INTKNEPMIS4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT4_D_INTKNEPMIS4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT4_D_INEPNAKEFF4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT4_D_INEPNAKEFF4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT4_D_TXFEMP4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT4_D_TXFEMP4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT4_D_TXFIFOUNDRN4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT4_D_TXFIFOUNDRN4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT4_D_BNAINTR4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT4_D_BNAINTR4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT4_D_PKTDRPSTS4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT4_D_PKTDRPSTS4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT4_D_BBLEERR4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT4_D_BBLEERR4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT4_D_NAKINTRPT4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT4_D_NAKINTRPT4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT4_D_NYETINTRPT4(value uint32) { + volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT4_D_NYETINTRPT4() uint32 { + return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ4 +func (o *USB_Type) SetDIEPTSIZ4_D_XFERSIZE4(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ4.Reg, volatile.LoadUint32(&o.DIEPTSIZ4.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ4_D_XFERSIZE4() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ4.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ4_D_PKTCNT4(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ4.Reg, volatile.LoadUint32(&o.DIEPTSIZ4.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ4_D_PKTCNT4() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ4.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA4 +func (o *USB_Type) SetDIEPDMA4(value uint32) { + volatile.StoreUint32(&o.DIEPDMA4.Reg, value) +} +func (o *USB_Type) GetDIEPDMA4() uint32 { + return volatile.LoadUint32(&o.DIEPDMA4.Reg) +} + +// USB.DTXFSTS4 +func (o *USB_Type) SetDTXFSTS4_D_INEPTXFSPCAVAIL4(value uint32) { + volatile.StoreUint32(&o.DTXFSTS4.Reg, volatile.LoadUint32(&o.DTXFSTS4.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS4_D_INEPTXFSPCAVAIL4() uint32 { + return volatile.LoadUint32(&o.DTXFSTS4.Reg) & 0xffff +} + +// USB.DIEPDMAB4 +func (o *USB_Type) SetDIEPDMAB4(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB4.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB4() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB4.Reg) +} + +// USB.DIEPCTL5 +func (o *USB_Type) SetDIEPCTL5_DI_MPS5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL5_DI_MPS5() uint32 { + return volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL5_DI_USBACTEP5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL5_DI_USBACTEP5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL5_DI_NAKSTS5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL5_DI_NAKSTS5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL5_DI_EPTYPE5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL5_DI_EPTYPE5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL5_DI_STALL5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL5_DI_STALL5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL5_DI_TXFNUM5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL5_DI_TXFNUM5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL5_DI_CNAK5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL5_DI_CNAK5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL5_DI_SNAK5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL5_DI_SNAK5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL5_DI_SETD0PID5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL5_DI_SETD0PID5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL5_DI_SETD1PID5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL5_DI_SETD1PID5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL5_DI_EPDIS5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL5_DI_EPDIS5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL5_DI_EPENA5(value uint32) { + volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL5_DI_EPENA5() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT5 +func (o *USB_Type) SetDIEPINT5_D_XFERCOMPL5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT5_D_XFERCOMPL5() uint32 { + return volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT5_D_EPDISBLD5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT5_D_EPDISBLD5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT5_D_AHBERR5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT5_D_AHBERR5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT5_D_TIMEOUT5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT5_D_TIMEOUT5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT5_D_INTKNTXFEMP5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT5_D_INTKNTXFEMP5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT5_D_INTKNEPMIS5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT5_D_INTKNEPMIS5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT5_D_INEPNAKEFF5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT5_D_INEPNAKEFF5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT5_D_TXFEMP5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT5_D_TXFEMP5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT5_D_TXFIFOUNDRN5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT5_D_TXFIFOUNDRN5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT5_D_BNAINTR5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT5_D_BNAINTR5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT5_D_PKTDRPSTS5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT5_D_PKTDRPSTS5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT5_D_BBLEERR5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT5_D_BBLEERR5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT5_D_NAKINTRPT5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT5_D_NAKINTRPT5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT5_D_NYETINTRPT5(value uint32) { + volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT5_D_NYETINTRPT5() uint32 { + return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ5 +func (o *USB_Type) SetDIEPTSIZ5_D_XFERSIZE5(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ5.Reg, volatile.LoadUint32(&o.DIEPTSIZ5.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ5_D_XFERSIZE5() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ5.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ5_D_PKTCNT5(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ5.Reg, volatile.LoadUint32(&o.DIEPTSIZ5.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ5_D_PKTCNT5() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ5.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA5 +func (o *USB_Type) SetDIEPDMA5(value uint32) { + volatile.StoreUint32(&o.DIEPDMA5.Reg, value) +} +func (o *USB_Type) GetDIEPDMA5() uint32 { + return volatile.LoadUint32(&o.DIEPDMA5.Reg) +} + +// USB.DTXFSTS5 +func (o *USB_Type) SetDTXFSTS5_D_INEPTXFSPCAVAIL5(value uint32) { + volatile.StoreUint32(&o.DTXFSTS5.Reg, volatile.LoadUint32(&o.DTXFSTS5.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS5_D_INEPTXFSPCAVAIL5() uint32 { + return volatile.LoadUint32(&o.DTXFSTS5.Reg) & 0xffff +} + +// USB.DIEPDMAB5 +func (o *USB_Type) SetDIEPDMAB5(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB5.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB5() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB5.Reg) +} + +// USB.DIEPCTL6 +func (o *USB_Type) SetDIEPCTL6_D_MPS6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDIEPCTL6_D_MPS6() uint32 { + return volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x3 +} +func (o *USB_Type) SetDIEPCTL6_D_USBACTEP6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDIEPCTL6_D_USBACTEP6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDIEPCTL6_D_NAKSTS6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDIEPCTL6_D_NAKSTS6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDIEPCTL6_D_EPTYPE6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDIEPCTL6_D_EPTYPE6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDIEPCTL6_D_STALL6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDIEPCTL6_D_STALL6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDIEPCTL6_D_TXFNUM6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x3c00000)|value<<22) +} +func (o *USB_Type) GetDIEPCTL6_D_TXFNUM6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x3c00000) >> 22 +} +func (o *USB_Type) SetDIEPCTL6_D_CNAK6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDIEPCTL6_D_CNAK6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDIEPCTL6_DI_SNAK6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDIEPCTL6_DI_SNAK6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDIEPCTL6_DI_SETD0PID6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDIEPCTL6_DI_SETD0PID6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDIEPCTL6_DI_SETD1PID6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDIEPCTL6_DI_SETD1PID6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDIEPCTL6_D_EPDIS6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDIEPCTL6_D_EPDIS6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDIEPCTL6_D_EPENA6(value uint32) { + volatile.StoreUint32(&o.DIEPCTL6.Reg, volatile.LoadUint32(&o.DIEPCTL6.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDIEPCTL6_D_EPENA6() uint32 { + return (volatile.LoadUint32(&o.DIEPCTL6.Reg) & 0x80000000) >> 31 +} + +// USB.DIEPINT6 +func (o *USB_Type) SetDIEPINT6_D_XFERCOMPL6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDIEPINT6_D_XFERCOMPL6() uint32 { + return volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x1 +} +func (o *USB_Type) SetDIEPINT6_D_EPDISBLD6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDIEPINT6_D_EPDISBLD6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDIEPINT6_D_AHBERR6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDIEPINT6_D_AHBERR6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDIEPINT6_D_TIMEOUT6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDIEPINT6_D_TIMEOUT6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDIEPINT6_D_INTKNTXFEMP6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDIEPINT6_D_INTKNTXFEMP6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDIEPINT6_D_INTKNEPMIS6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDIEPINT6_D_INTKNEPMIS6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDIEPINT6_D_INEPNAKEFF6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDIEPINT6_D_INEPNAKEFF6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDIEPINT6_D_TXFEMP6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetDIEPINT6_D_TXFEMP6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetDIEPINT6_D_TXFIFOUNDRN6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDIEPINT6_D_TXFIFOUNDRN6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDIEPINT6_D_BNAINTR6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDIEPINT6_D_BNAINTR6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDIEPINT6_D_PKTDRPSTS6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDIEPINT6_D_PKTDRPSTS6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDIEPINT6_D_BBLEERR6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDIEPINT6_D_BBLEERR6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDIEPINT6_D_NAKINTRPT6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDIEPINT6_D_NAKINTRPT6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDIEPINT6_D_NYETINTRPT6(value uint32) { + volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDIEPINT6_D_NYETINTRPT6() uint32 { + return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x4000) >> 14 +} + +// USB.DIEPTSIZ6 +func (o *USB_Type) SetDIEPTSIZ6_D_XFERSIZE6(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ6.Reg, volatile.LoadUint32(&o.DIEPTSIZ6.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDIEPTSIZ6_D_XFERSIZE6() uint32 { + return volatile.LoadUint32(&o.DIEPTSIZ6.Reg) & 0x7f +} +func (o *USB_Type) SetDIEPTSIZ6_D_PKTCNT6(value uint32) { + volatile.StoreUint32(&o.DIEPTSIZ6.Reg, volatile.LoadUint32(&o.DIEPTSIZ6.Reg)&^(0x180000)|value<<19) +} +func (o *USB_Type) GetDIEPTSIZ6_D_PKTCNT6() uint32 { + return (volatile.LoadUint32(&o.DIEPTSIZ6.Reg) & 0x180000) >> 19 +} + +// USB.DIEPDMA6 +func (o *USB_Type) SetDIEPDMA6(value uint32) { + volatile.StoreUint32(&o.DIEPDMA6.Reg, value) +} +func (o *USB_Type) GetDIEPDMA6() uint32 { + return volatile.LoadUint32(&o.DIEPDMA6.Reg) +} + +// USB.DTXFSTS6 +func (o *USB_Type) SetDTXFSTS6_D_INEPTXFSPCAVAIL6(value uint32) { + volatile.StoreUint32(&o.DTXFSTS6.Reg, volatile.LoadUint32(&o.DTXFSTS6.Reg)&^(0xffff)|value) +} +func (o *USB_Type) GetDTXFSTS6_D_INEPTXFSPCAVAIL6() uint32 { + return volatile.LoadUint32(&o.DTXFSTS6.Reg) & 0xffff +} + +// USB.DIEPDMAB6 +func (o *USB_Type) SetDIEPDMAB6(value uint32) { + volatile.StoreUint32(&o.DIEPDMAB6.Reg, value) +} +func (o *USB_Type) GetDIEPDMAB6() uint32 { + return volatile.LoadUint32(&o.DIEPDMAB6.Reg) +} + +// USB.DOEPCTL0 +func (o *USB_Type) SetDOEPCTL0_MPS0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x3)|value) +} +func (o *USB_Type) GetDOEPCTL0_MPS0() uint32 { + return volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x3 +} +func (o *USB_Type) SetDOEPCTL0_USBACTEP0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL0_USBACTEP0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL0_NAKSTS0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL0_NAKSTS0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL0_EPTYPE0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL0_EPTYPE0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL0_SNP0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL0_SNP0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL0_STALL0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL0_STALL0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL0_CNAK0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL0_CNAK0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL0_DO_SNAK0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL0_DO_SNAK0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL0_EPDIS0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL0_EPDIS0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL0_EPENA0(value uint32) { + volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL0_EPENA0() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT0 +func (o *USB_Type) SetDOEPINT0_XFERCOMPL0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT0_XFERCOMPL0() uint32 { + return volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT0_EPDISBLD0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT0_EPDISBLD0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT0_AHBERR0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT0_AHBERR0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT0_SETUP0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT0_SETUP0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT0_OUTTKNEPDIS0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT0_OUTTKNEPDIS0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT0_STSPHSERCVD0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT0_STSPHSERCVD0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT0_BACK2BACKSETUP0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT0_BACK2BACKSETUP0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT0_OUTPKTERR0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT0_OUTPKTERR0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT0_BNAINTR0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT0_BNAINTR0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT0_PKTDRPSTS0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT0_PKTDRPSTS0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT0_BBLEERR0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT0_BBLEERR0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT0_NAKINTRPT0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT0_NAKINTRPT0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT0_NYEPINTRPT0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT0_NYEPINTRPT0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT0_STUPPKTRCVD0(value uint32) { + volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT0_STUPPKTRCVD0() uint32 { + return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ0 +func (o *USB_Type) SetDOEPTSIZ0_XFERSIZE0(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ0.Reg, volatile.LoadUint32(&o.DOEPTSIZ0.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ0_XFERSIZE0() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ0.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ0_PKTCNT0(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ0.Reg, volatile.LoadUint32(&o.DOEPTSIZ0.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ0_PKTCNT0() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ0.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ0_SUPCNT0(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ0.Reg, volatile.LoadUint32(&o.DOEPTSIZ0.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ0_SUPCNT0() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ0.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA0 +func (o *USB_Type) SetDOEPDMA0(value uint32) { + volatile.StoreUint32(&o.DOEPDMA0.Reg, value) +} +func (o *USB_Type) GetDOEPDMA0() uint32 { + return volatile.LoadUint32(&o.DOEPDMA0.Reg) +} + +// USB.DOEPDMAB0 +func (o *USB_Type) SetDOEPDMAB0(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB0.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB0() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB0.Reg) +} + +// USB.DOEPCTL1 +func (o *USB_Type) SetDOEPCTL1_MPS1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL1_MPS1() uint32 { + return volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL1_USBACTEP1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL1_USBACTEP1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL1_NAKSTS1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL1_NAKSTS1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL1_EPTYPE1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL1_EPTYPE1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL1_SNP1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL1_SNP1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL1_STALL1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL1_STALL1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL1_CNAK1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL1_CNAK1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL1_DO_SNAK1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL1_DO_SNAK1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL1_DO_SETD0PID1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL1_DO_SETD0PID1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL1_DO_SETD1PID1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL1_DO_SETD1PID1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL1_EPDIS1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL1_EPDIS1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL1_EPENA1(value uint32) { + volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL1_EPENA1() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT1 +func (o *USB_Type) SetDOEPINT1_XFERCOMPL1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT1_XFERCOMPL1() uint32 { + return volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT1_EPDISBLD1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT1_EPDISBLD1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT1_AHBERR1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT1_AHBERR1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT1_SETUP1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT1_SETUP1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT1_OUTTKNEPDIS1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT1_OUTTKNEPDIS1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT1_STSPHSERCVD1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT1_STSPHSERCVD1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT1_BACK2BACKSETUP1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT1_BACK2BACKSETUP1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT1_OUTPKTERR1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT1_OUTPKTERR1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT1_BNAINTR1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT1_BNAINTR1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT1_PKTDRPSTS1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT1_PKTDRPSTS1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT1_BBLEERR1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT1_BBLEERR1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT1_NAKINTRPT1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT1_NAKINTRPT1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT1_NYEPINTRPT1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT1_NYEPINTRPT1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT1_STUPPKTRCVD1(value uint32) { + volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT1_STUPPKTRCVD1() uint32 { + return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ1 +func (o *USB_Type) SetDOEPTSIZ1_XFERSIZE1(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ1.Reg, volatile.LoadUint32(&o.DOEPTSIZ1.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ1_XFERSIZE1() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ1.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ1_PKTCNT1(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ1.Reg, volatile.LoadUint32(&o.DOEPTSIZ1.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ1_PKTCNT1() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ1.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ1_SUPCNT1(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ1.Reg, volatile.LoadUint32(&o.DOEPTSIZ1.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ1_SUPCNT1() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ1.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA1 +func (o *USB_Type) SetDOEPDMA1(value uint32) { + volatile.StoreUint32(&o.DOEPDMA1.Reg, value) +} +func (o *USB_Type) GetDOEPDMA1() uint32 { + return volatile.LoadUint32(&o.DOEPDMA1.Reg) +} + +// USB.DOEPDMAB1 +func (o *USB_Type) SetDOEPDMAB1(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB1.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB1() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB1.Reg) +} + +// USB.DOEPCTL2 +func (o *USB_Type) SetDOEPCTL2_MPS2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL2_MPS2() uint32 { + return volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL2_USBACTEP2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL2_USBACTEP2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL2_NAKSTS2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL2_NAKSTS2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL2_EPTYPE2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL2_EPTYPE2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL2_SNP2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL2_SNP2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL2_STALL2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL2_STALL2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL2_CNAK2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL2_CNAK2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL2_DO_SNAK2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL2_DO_SNAK2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL2_DO_SETD0PID2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL2_DO_SETD0PID2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL2_DO_SETD1PID2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL2_DO_SETD1PID2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL2_EPDIS2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL2_EPDIS2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL2_EPENA2(value uint32) { + volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL2_EPENA2() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT2 +func (o *USB_Type) SetDOEPINT2_XFERCOMPL2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT2_XFERCOMPL2() uint32 { + return volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT2_EPDISBLD2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT2_EPDISBLD2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT2_AHBERR2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT2_AHBERR2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT2_SETUP2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT2_SETUP2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT2_OUTTKNEPDIS2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT2_OUTTKNEPDIS2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT2_STSPHSERCVD2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT2_STSPHSERCVD2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT2_BACK2BACKSETUP2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT2_BACK2BACKSETUP2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT2_OUTPKTERR2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT2_OUTPKTERR2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT2_BNAINTR2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT2_BNAINTR2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT2_PKTDRPSTS2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT2_PKTDRPSTS2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT2_BBLEERR2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT2_BBLEERR2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT2_NAKINTRPT2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT2_NAKINTRPT2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT2_NYEPINTRPT2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT2_NYEPINTRPT2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT2_STUPPKTRCVD2(value uint32) { + volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT2_STUPPKTRCVD2() uint32 { + return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ2 +func (o *USB_Type) SetDOEPTSIZ2_XFERSIZE2(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ2.Reg, volatile.LoadUint32(&o.DOEPTSIZ2.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ2_XFERSIZE2() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ2.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ2_PKTCNT2(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ2.Reg, volatile.LoadUint32(&o.DOEPTSIZ2.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ2_PKTCNT2() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ2.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ2_SUPCNT2(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ2.Reg, volatile.LoadUint32(&o.DOEPTSIZ2.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ2_SUPCNT2() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ2.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA2 +func (o *USB_Type) SetDOEPDMA2(value uint32) { + volatile.StoreUint32(&o.DOEPDMA2.Reg, value) +} +func (o *USB_Type) GetDOEPDMA2() uint32 { + return volatile.LoadUint32(&o.DOEPDMA2.Reg) +} + +// USB.DOEPDMAB2 +func (o *USB_Type) SetDOEPDMAB2(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB2.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB2() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB2.Reg) +} + +// USB.DOEPCTL3 +func (o *USB_Type) SetDOEPCTL3_MPS3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL3_MPS3() uint32 { + return volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL3_USBACTEP3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL3_USBACTEP3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL3_NAKSTS3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL3_NAKSTS3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL3_EPTYPE3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL3_EPTYPE3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL3_SNP3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL3_SNP3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL3_STALL3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL3_STALL3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL3_CNAK3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL3_CNAK3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL3_DO_SNAK3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL3_DO_SNAK3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL3_DO_SETD0PID3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL3_DO_SETD0PID3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL3_DO_SETD1PID3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL3_DO_SETD1PID3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL3_EPDIS3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL3_EPDIS3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL3_EPENA3(value uint32) { + volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL3_EPENA3() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT3 +func (o *USB_Type) SetDOEPINT3_XFERCOMPL3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT3_XFERCOMPL3() uint32 { + return volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT3_EPDISBLD3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT3_EPDISBLD3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT3_AHBERR3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT3_AHBERR3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT3_SETUP3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT3_SETUP3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT3_OUTTKNEPDIS3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT3_OUTTKNEPDIS3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT3_STSPHSERCVD3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT3_STSPHSERCVD3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT3_BACK2BACKSETUP3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT3_BACK2BACKSETUP3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT3_OUTPKTERR3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT3_OUTPKTERR3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT3_BNAINTR3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT3_BNAINTR3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT3_PKTDRPSTS3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT3_PKTDRPSTS3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT3_BBLEERR3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT3_BBLEERR3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT3_NAKINTRPT3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT3_NAKINTRPT3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT3_NYEPINTRPT3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT3_NYEPINTRPT3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT3_STUPPKTRCVD3(value uint32) { + volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT3_STUPPKTRCVD3() uint32 { + return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ3 +func (o *USB_Type) SetDOEPTSIZ3_XFERSIZE3(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ3.Reg, volatile.LoadUint32(&o.DOEPTSIZ3.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ3_XFERSIZE3() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ3.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ3_PKTCNT3(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ3.Reg, volatile.LoadUint32(&o.DOEPTSIZ3.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ3_PKTCNT3() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ3.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ3_SUPCNT3(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ3.Reg, volatile.LoadUint32(&o.DOEPTSIZ3.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ3_SUPCNT3() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ3.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA3 +func (o *USB_Type) SetDOEPDMA3(value uint32) { + volatile.StoreUint32(&o.DOEPDMA3.Reg, value) +} +func (o *USB_Type) GetDOEPDMA3() uint32 { + return volatile.LoadUint32(&o.DOEPDMA3.Reg) +} + +// USB.DOEPDMAB3 +func (o *USB_Type) SetDOEPDMAB3(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB3.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB3() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB3.Reg) +} + +// USB.DOEPCTL4 +func (o *USB_Type) SetDOEPCTL4_MPS4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL4_MPS4() uint32 { + return volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL4_USBACTEP4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL4_USBACTEP4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL4_NAKSTS4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL4_NAKSTS4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL4_EPTYPE4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL4_EPTYPE4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL4_SNP4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL4_SNP4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL4_STALL4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL4_STALL4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL4_CNAK4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL4_CNAK4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL4_DO_SNAK4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL4_DO_SNAK4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL4_DO_SETD0PID4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL4_DO_SETD0PID4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL4_DO_SETD1PID4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL4_DO_SETD1PID4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL4_EPDIS4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL4_EPDIS4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL4_EPENA4(value uint32) { + volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL4_EPENA4() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT4 +func (o *USB_Type) SetDOEPINT4_XFERCOMPL4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT4_XFERCOMPL4() uint32 { + return volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT4_EPDISBLD4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT4_EPDISBLD4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT4_AHBERR4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT4_AHBERR4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT4_SETUP4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT4_SETUP4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT4_OUTTKNEPDIS4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT4_OUTTKNEPDIS4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT4_STSPHSERCVD4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT4_STSPHSERCVD4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT4_BACK2BACKSETUP4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT4_BACK2BACKSETUP4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT4_OUTPKTERR4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT4_OUTPKTERR4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT4_BNAINTR4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT4_BNAINTR4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT4_PKTDRPSTS4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT4_PKTDRPSTS4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT4_BBLEERR4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT4_BBLEERR4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT4_NAKINTRPT4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT4_NAKINTRPT4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT4_NYEPINTRPT4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT4_NYEPINTRPT4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT4_STUPPKTRCVD4(value uint32) { + volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT4_STUPPKTRCVD4() uint32 { + return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ4 +func (o *USB_Type) SetDOEPTSIZ4_XFERSIZE4(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ4.Reg, volatile.LoadUint32(&o.DOEPTSIZ4.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ4_XFERSIZE4() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ4.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ4_PKTCNT4(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ4.Reg, volatile.LoadUint32(&o.DOEPTSIZ4.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ4_PKTCNT4() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ4.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ4_SUPCNT4(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ4.Reg, volatile.LoadUint32(&o.DOEPTSIZ4.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ4_SUPCNT4() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ4.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA4 +func (o *USB_Type) SetDOEPDMA4(value uint32) { + volatile.StoreUint32(&o.DOEPDMA4.Reg, value) +} +func (o *USB_Type) GetDOEPDMA4() uint32 { + return volatile.LoadUint32(&o.DOEPDMA4.Reg) +} + +// USB.DOEPDMAB4 +func (o *USB_Type) SetDOEPDMAB4(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB4.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB4() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB4.Reg) +} + +// USB.DOEPCTL5 +func (o *USB_Type) SetDOEPCTL5_MPS5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL5_MPS5() uint32 { + return volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL5_USBACTEP5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL5_USBACTEP5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL5_NAKSTS5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL5_NAKSTS5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL5_EPTYPE5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL5_EPTYPE5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL5_SNP5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL5_SNP5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL5_STALL5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL5_STALL5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL5_CNAK5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL5_CNAK5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL5_DO_SNAK5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL5_DO_SNAK5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL5_DO_SETD0PID5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL5_DO_SETD0PID5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL5_DO_SETD1PID5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL5_DO_SETD1PID5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL5_EPDIS5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL5_EPDIS5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL5_EPENA5(value uint32) { + volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL5_EPENA5() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT5 +func (o *USB_Type) SetDOEPINT5_XFERCOMPL5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT5_XFERCOMPL5() uint32 { + return volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT5_EPDISBLD5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT5_EPDISBLD5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT5_AHBERR5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT5_AHBERR5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT5_SETUP5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT5_SETUP5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT5_OUTTKNEPDIS5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT5_OUTTKNEPDIS5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT5_STSPHSERCVD5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT5_STSPHSERCVD5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT5_BACK2BACKSETUP5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT5_BACK2BACKSETUP5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT5_OUTPKTERR5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT5_OUTPKTERR5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT5_BNAINTR5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT5_BNAINTR5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT5_PKTDRPSTS5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT5_PKTDRPSTS5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT5_BBLEERR5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT5_BBLEERR5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT5_NAKINTRPT5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT5_NAKINTRPT5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT5_NYEPINTRPT5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT5_NYEPINTRPT5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT5_STUPPKTRCVD5(value uint32) { + volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT5_STUPPKTRCVD5() uint32 { + return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ5 +func (o *USB_Type) SetDOEPTSIZ5_XFERSIZE5(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ5.Reg, volatile.LoadUint32(&o.DOEPTSIZ5.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ5_XFERSIZE5() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ5.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ5_PKTCNT5(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ5.Reg, volatile.LoadUint32(&o.DOEPTSIZ5.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ5_PKTCNT5() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ5.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ5_SUPCNT5(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ5.Reg, volatile.LoadUint32(&o.DOEPTSIZ5.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ5_SUPCNT5() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ5.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA5 +func (o *USB_Type) SetDOEPDMA5(value uint32) { + volatile.StoreUint32(&o.DOEPDMA5.Reg, value) +} +func (o *USB_Type) GetDOEPDMA5() uint32 { + return volatile.LoadUint32(&o.DOEPDMA5.Reg) +} + +// USB.DOEPDMAB5 +func (o *USB_Type) SetDOEPDMAB5(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB5.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB5() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB5.Reg) +} + +// USB.DOEPCTL6 +func (o *USB_Type) SetDOEPCTL6_MPS6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x7ff)|value) +} +func (o *USB_Type) GetDOEPCTL6_MPS6() uint32 { + return volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x7ff +} +func (o *USB_Type) SetDOEPCTL6_USBACTEP6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPCTL6_USBACTEP6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x8000) >> 15 +} +func (o *USB_Type) SetDOEPCTL6_NAKSTS6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x20000)|value<<17) +} +func (o *USB_Type) GetDOEPCTL6_NAKSTS6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x20000) >> 17 +} +func (o *USB_Type) SetDOEPCTL6_EPTYPE6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0xc0000)|value<<18) +} +func (o *USB_Type) GetDOEPCTL6_EPTYPE6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0xc0000) >> 18 +} +func (o *USB_Type) SetDOEPCTL6_SNP6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x100000)|value<<20) +} +func (o *USB_Type) GetDOEPCTL6_SNP6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x100000) >> 20 +} +func (o *USB_Type) SetDOEPCTL6_STALL6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x200000)|value<<21) +} +func (o *USB_Type) GetDOEPCTL6_STALL6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x200000) >> 21 +} +func (o *USB_Type) SetDOEPCTL6_CNAK6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x4000000)|value<<26) +} +func (o *USB_Type) GetDOEPCTL6_CNAK6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x4000000) >> 26 +} +func (o *USB_Type) SetDOEPCTL6_DO_SNAK6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x8000000)|value<<27) +} +func (o *USB_Type) GetDOEPCTL6_DO_SNAK6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x8000000) >> 27 +} +func (o *USB_Type) SetDOEPCTL6_DO_SETD0PID6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x10000000)|value<<28) +} +func (o *USB_Type) GetDOEPCTL6_DO_SETD0PID6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x10000000) >> 28 +} +func (o *USB_Type) SetDOEPCTL6_DO_SETD1PID6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x20000000)|value<<29) +} +func (o *USB_Type) GetDOEPCTL6_DO_SETD1PID6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x20000000) >> 29 +} +func (o *USB_Type) SetDOEPCTL6_EPDIS6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x40000000)|value<<30) +} +func (o *USB_Type) GetDOEPCTL6_EPDIS6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x40000000) >> 30 +} +func (o *USB_Type) SetDOEPCTL6_EPENA6(value uint32) { + volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_Type) GetDOEPCTL6_EPENA6() uint32 { + return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x80000000) >> 31 +} + +// USB.DOEPINT6 +func (o *USB_Type) SetDOEPINT6_XFERCOMPL6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetDOEPINT6_XFERCOMPL6() uint32 { + return volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x1 +} +func (o *USB_Type) SetDOEPINT6_EPDISBLD6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetDOEPINT6_EPDISBLD6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetDOEPINT6_AHBERR6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetDOEPINT6_AHBERR6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetDOEPINT6_SETUP6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetDOEPINT6_SETUP6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetDOEPINT6_OUTTKNEPDIS6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x10)|value<<4) +} +func (o *USB_Type) GetDOEPINT6_OUTTKNEPDIS6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x10) >> 4 +} +func (o *USB_Type) SetDOEPINT6_STSPHSERCVD6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x20)|value<<5) +} +func (o *USB_Type) GetDOEPINT6_STSPHSERCVD6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x20) >> 5 +} +func (o *USB_Type) SetDOEPINT6_BACK2BACKSETUP6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetDOEPINT6_BACK2BACKSETUP6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetDOEPINT6_OUTPKTERR6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetDOEPINT6_OUTPKTERR6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x100) >> 8 +} +func (o *USB_Type) SetDOEPINT6_BNAINTR6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x200)|value<<9) +} +func (o *USB_Type) GetDOEPINT6_BNAINTR6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x200) >> 9 +} +func (o *USB_Type) SetDOEPINT6_PKTDRPSTS6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x800)|value<<11) +} +func (o *USB_Type) GetDOEPINT6_PKTDRPSTS6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x800) >> 11 +} +func (o *USB_Type) SetDOEPINT6_BBLEERR6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x1000)|value<<12) +} +func (o *USB_Type) GetDOEPINT6_BBLEERR6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x1000) >> 12 +} +func (o *USB_Type) SetDOEPINT6_NAKINTRPT6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x2000)|value<<13) +} +func (o *USB_Type) GetDOEPINT6_NAKINTRPT6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x2000) >> 13 +} +func (o *USB_Type) SetDOEPINT6_NYEPINTRPT6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x4000)|value<<14) +} +func (o *USB_Type) GetDOEPINT6_NYEPINTRPT6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x4000) >> 14 +} +func (o *USB_Type) SetDOEPINT6_STUPPKTRCVD6(value uint32) { + volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x8000)|value<<15) +} +func (o *USB_Type) GetDOEPINT6_STUPPKTRCVD6() uint32 { + return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x8000) >> 15 +} + +// USB.DOEPTSIZ6 +func (o *USB_Type) SetDOEPTSIZ6_XFERSIZE6(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ6.Reg, volatile.LoadUint32(&o.DOEPTSIZ6.Reg)&^(0x7f)|value) +} +func (o *USB_Type) GetDOEPTSIZ6_XFERSIZE6() uint32 { + return volatile.LoadUint32(&o.DOEPTSIZ6.Reg) & 0x7f +} +func (o *USB_Type) SetDOEPTSIZ6_PKTCNT6(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ6.Reg, volatile.LoadUint32(&o.DOEPTSIZ6.Reg)&^(0x80000)|value<<19) +} +func (o *USB_Type) GetDOEPTSIZ6_PKTCNT6() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ6.Reg) & 0x80000) >> 19 +} +func (o *USB_Type) SetDOEPTSIZ6_SUPCNT6(value uint32) { + volatile.StoreUint32(&o.DOEPTSIZ6.Reg, volatile.LoadUint32(&o.DOEPTSIZ6.Reg)&^(0x60000000)|value<<29) +} +func (o *USB_Type) GetDOEPTSIZ6_SUPCNT6() uint32 { + return (volatile.LoadUint32(&o.DOEPTSIZ6.Reg) & 0x60000000) >> 29 +} + +// USB.DOEPDMA6 +func (o *USB_Type) SetDOEPDMA6(value uint32) { + volatile.StoreUint32(&o.DOEPDMA6.Reg, value) +} +func (o *USB_Type) GetDOEPDMA6() uint32 { + return volatile.LoadUint32(&o.DOEPDMA6.Reg) +} + +// USB.DOEPDMAB6 +func (o *USB_Type) SetDOEPDMAB6(value uint32) { + volatile.StoreUint32(&o.DOEPDMAB6.Reg, value) +} +func (o *USB_Type) GetDOEPDMAB6() uint32 { + return volatile.LoadUint32(&o.DOEPDMAB6.Reg) +} + +// USB.PCGCCTL +func (o *USB_Type) SetPCGCCTL_STOPPCLK(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x1)|value) +} +func (o *USB_Type) GetPCGCCTL_STOPPCLK() uint32 { + return volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x1 +} +func (o *USB_Type) SetPCGCCTL_GATEHCLK(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x2)|value<<1) +} +func (o *USB_Type) GetPCGCCTL_GATEHCLK() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x2) >> 1 +} +func (o *USB_Type) SetPCGCCTL_PWRCLMP(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x4)|value<<2) +} +func (o *USB_Type) GetPCGCCTL_PWRCLMP() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x4) >> 2 +} +func (o *USB_Type) SetPCGCCTL_RSTPDWNMODULE(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x8)|value<<3) +} +func (o *USB_Type) GetPCGCCTL_RSTPDWNMODULE() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x8) >> 3 +} +func (o *USB_Type) SetPCGCCTL_PHYSLEEP(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x40)|value<<6) +} +func (o *USB_Type) GetPCGCCTL_PHYSLEEP() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x40) >> 6 +} +func (o *USB_Type) SetPCGCCTL_L1SUSPENDED(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x80)|value<<7) +} +func (o *USB_Type) GetPCGCCTL_L1SUSPENDED() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x80) >> 7 +} +func (o *USB_Type) SetPCGCCTL_RESETAFTERSUSP(value uint32) { + volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x100)|value<<8) +} +func (o *USB_Type) GetPCGCCTL_RESETAFTERSUSP() uint32 { + return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x100) >> 8 +} + +// Full-speed USB Serial/JTAG Controller +type USB_DEVICE_Type struct { + EP1 volatile.Register32 // 0x0 + EP1_CONF volatile.Register32 // 0x4 + INT_RAW volatile.Register32 // 0x8 + INT_ST volatile.Register32 // 0xC + INT_ENA volatile.Register32 // 0x10 + INT_CLR volatile.Register32 // 0x14 + CONF0 volatile.Register32 // 0x18 + TEST volatile.Register32 // 0x1C + JFIFO_ST volatile.Register32 // 0x20 + FRAM_NUM volatile.Register32 // 0x24 + IN_EP0_ST volatile.Register32 // 0x28 + IN_EP1_ST volatile.Register32 // 0x2C + IN_EP2_ST volatile.Register32 // 0x30 + IN_EP3_ST volatile.Register32 // 0x34 + OUT_EP0_ST volatile.Register32 // 0x38 + OUT_EP1_ST volatile.Register32 // 0x3C + OUT_EP2_ST volatile.Register32 // 0x40 + MISC_CONF volatile.Register32 // 0x44 + MEM_CONF volatile.Register32 // 0x48 + _ [52]byte + DATE volatile.Register32 // 0x80 +} + +// USB_DEVICE.EP1: Endpoint 1 FIFO register +func (o *USB_DEVICE_Type) SetEP1_RDWR_BYTE(value uint32) { + volatile.StoreUint32(&o.EP1.Reg, volatile.LoadUint32(&o.EP1.Reg)&^(0xff)|value) +} +func (o *USB_DEVICE_Type) GetEP1_RDWR_BYTE() uint32 { + return volatile.LoadUint32(&o.EP1.Reg) & 0xff +} + +// USB_DEVICE.EP1_CONF: Endpoint 1 configure and status register +func (o *USB_DEVICE_Type) SetEP1_CONF_WR_DONE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_WR_DONE() uint32 { + return volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_SERIAL_IN_EP_DATA_FREE(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_SERIAL_IN_EP_DATA_FREE() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetEP1_CONF_SERIAL_OUT_EP_DATA_AVAIL(value uint32) { + volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetEP1_CONF_SERIAL_OUT_EP_DATA_AVAIL() uint32 { + return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x4) >> 2 +} + +// USB_DEVICE.INT_RAW: Raw status interrupt +func (o *USB_DEVICE_Type) SetINT_RAW_JTAG_IN_FLUSH_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_RAW_JTAG_IN_FLUSH_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_RAW_SERIAL_IN_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_RAW_SERIAL_IN_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_RAW_PID_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_RAW_PID_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_RAW_CRC5_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_RAW_CRC5_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_RAW_CRC16_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_RAW_CRC16_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_RAW_STUFF_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_RAW_STUFF_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_RAW_USB_BUS_RESET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_RAW_USB_BUS_RESET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11 +} + +// USB_DEVICE.INT_ST: Masked interrupt +func (o *USB_DEVICE_Type) SetINT_ST_JTAG_IN_FLUSH_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ST_JTAG_IN_FLUSH_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ST_SOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ST_SOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ST_SERIAL_OUT_RECV_PKT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ST_SERIAL_OUT_RECV_PKT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ST_SERIAL_IN_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ST_SERIAL_IN_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ST_PID_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ST_PID_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ST_CRC5_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ST_CRC5_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ST_CRC16_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ST_CRC16_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ST_STUFF_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ST_STUFF_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ST_IN_TOKEN_REC_IN_EP1_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ST_IN_TOKEN_REC_IN_EP1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ST_USB_BUS_RESET_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ST_USB_BUS_RESET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11 +} + +// USB_DEVICE.INT_ENA: Interrupt enable bits +func (o *USB_DEVICE_Type) SetINT_ENA_JTAG_IN_FLUSH_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_ENA_JTAG_IN_FLUSH_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_ENA_SERIAL_IN_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_ENA_SERIAL_IN_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_ENA_PID_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_ENA_PID_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_ENA_CRC5_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_ENA_CRC5_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_ENA_CRC16_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_ENA_CRC16_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_ENA_STUFF_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_ENA_STUFF_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_ENA_USB_BUS_RESET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_ENA_USB_BUS_RESET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11 +} + +// USB_DEVICE.INT_CLR: Interrupt clear bits +func (o *USB_DEVICE_Type) SetINT_CLR_JTAG_IN_FLUSH_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetINT_CLR_JTAG_IN_FLUSH_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetINT_CLR_SERIAL_IN_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetINT_CLR_SERIAL_IN_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetINT_CLR_PID_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetINT_CLR_PID_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetINT_CLR_CRC5_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetINT_CLR_CRC5_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetINT_CLR_CRC16_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetINT_CLR_CRC16_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetINT_CLR_STUFF_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetINT_CLR_STUFF_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetINT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetINT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetINT_CLR_USB_BUS_RESET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetINT_CLR_USB_BUS_RESET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetINT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetINT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetINT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetINT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11 +} + +// USB_DEVICE.CONF0: Configure 0 register +func (o *USB_DEVICE_Type) SetCONF0_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetCONF0_PHY_SEL() uint32 { + return volatile.LoadUint32(&o.CONF0.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetCONF0_EXCHG_PINS_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetCONF0_EXCHG_PINS_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetCONF0_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetCONF0_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetCONF0_VREFH(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x18)|value<<3) +} +func (o *USB_DEVICE_Type) GetCONF0_VREFH() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x18) >> 3 +} +func (o *USB_DEVICE_Type) SetCONF0_VREFL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x60)|value<<5) +} +func (o *USB_DEVICE_Type) GetCONF0_VREFL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x60) >> 5 +} +func (o *USB_DEVICE_Type) SetCONF0_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetCONF0_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetCONF0_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetCONF0_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetCONF0_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetCONF0_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9 +} +func (o *USB_DEVICE_Type) SetCONF0_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10) +} +func (o *USB_DEVICE_Type) GetCONF0_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10 +} +func (o *USB_DEVICE_Type) SetCONF0_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11) +} +func (o *USB_DEVICE_Type) GetCONF0_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11 +} +func (o *USB_DEVICE_Type) SetCONF0_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12) +} +func (o *USB_DEVICE_Type) GetCONF0_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12 +} +func (o *USB_DEVICE_Type) SetCONF0_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13) +} +func (o *USB_DEVICE_Type) GetCONF0_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14 +} +func (o *USB_DEVICE_Type) SetCONF0_PHY_TX_EDGE_SEL(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *USB_DEVICE_Type) GetCONF0_PHY_TX_EDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15 +} +func (o *USB_DEVICE_Type) SetCONF0_USB_JTAG_BRIDGE_EN(value uint32) { + volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x10000)|value<<16) +} +func (o *USB_DEVICE_Type) GetCONF0_USB_JTAG_BRIDGE_EN() uint32 { + return (volatile.LoadUint32(&o.CONF0.Reg) & 0x10000) >> 16 +} + +// USB_DEVICE.TEST: USB Internal PHY test register +func (o *USB_DEVICE_Type) SetTEST_ENABLE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetTEST_ENABLE() uint32 { + return volatile.LoadUint32(&o.TEST.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetTEST_USB_OE(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetTEST_USB_OE() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x2) >> 1 +} +func (o *USB_DEVICE_Type) SetTEST_TX_DP(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetTEST_TX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetTEST_TX_DM(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetTEST_TX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetTEST_RX_RCV(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x10)|value<<4) +} +func (o *USB_DEVICE_Type) GetTEST_RX_RCV() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x10) >> 4 +} +func (o *USB_DEVICE_Type) SetTEST_RX_DP(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x20)|value<<5) +} +func (o *USB_DEVICE_Type) GetTEST_RX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x20) >> 5 +} +func (o *USB_DEVICE_Type) SetTEST_RX_DM(value uint32) { + volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetTEST_RX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST.Reg) & 0x40) >> 6 +} + +// USB_DEVICE.JFIFO_ST: USB-JTAG FIFO status +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_CNT() uint32 { + return volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x4)|value<<2) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x4) >> 2 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x8)|value<<3) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x8) >> 3 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_CNT(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x30)|value<<4) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x30) >> 4 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_EMPTY(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x40)|value<<6) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_EMPTY() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x40) >> 6 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_FULL(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x80)|value<<7) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_FULL() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x80) >> 7 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_IN_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x100)|value<<8) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_IN_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x100) >> 8 +} +func (o *USB_DEVICE_Type) SetJFIFO_ST_OUT_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x200)|value<<9) +} +func (o *USB_DEVICE_Type) GetJFIFO_ST_OUT_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x200) >> 9 +} + +// USB_DEVICE.FRAM_NUM: SOF frame number +func (o *USB_DEVICE_Type) SetFRAM_NUM_SOF_FRAME_INDEX(value uint32) { + volatile.StoreUint32(&o.FRAM_NUM.Reg, volatile.LoadUint32(&o.FRAM_NUM.Reg)&^(0x7ff)|value) +} +func (o *USB_DEVICE_Type) GetFRAM_NUM_SOF_FRAME_INDEX() uint32 { + return volatile.LoadUint32(&o.FRAM_NUM.Reg) & 0x7ff +} + +// USB_DEVICE.IN_EP0_ST: IN Endpoint 0 status +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP0_ST_IN_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP0_ST_IN_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP1_ST: IN Endpoint 1 status +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP1_ST_IN_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP1_ST_IN_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP2_ST: IN Endpoint 2 status +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP2_ST_IN_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP2_ST_IN_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.IN_EP3_ST: IN Endpoint 3 status +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_STATE(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_STATE() uint32 { + return volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetIN_EP3_ST_IN_EP3_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetIN_EP3_ST_IN_EP3_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP0_ST: OUT Endpoint 0 status +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP0_ST_OUT_EP0_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP0_ST_OUT_EP0_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.OUT_EP1_ST: OUT Endpoint 1 status +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0xfe00) >> 9 +} +func (o *USB_DEVICE_Type) SetOUT_EP1_ST_OUT_EP1_REC_DATA_CNT(value uint32) { + volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x7f0000)|value<<16) +} +func (o *USB_DEVICE_Type) GetOUT_EP1_ST_OUT_EP1_REC_DATA_CNT() uint32 { + return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x7f0000) >> 16 +} + +// USB_DEVICE.OUT_EP2_ST: OUT Endpoint 2 status +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_STATE(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x3)|value) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_STATE() uint32 { + return volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x3 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_WR_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x1fc)|value<<2) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_WR_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x1fc) >> 2 +} +func (o *USB_DEVICE_Type) SetOUT_EP2_ST_OUT_EP2_RD_ADDR(value uint32) { + volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0xfe00)|value<<9) +} +func (o *USB_DEVICE_Type) GetOUT_EP2_ST_OUT_EP2_RD_ADDR() uint32 { + return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0xfe00) >> 9 +} + +// USB_DEVICE.MISC_CONF: MISC register +func (o *USB_DEVICE_Type) SetMISC_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMISC_CONF_CLK_EN() uint32 { + return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1 +} + +// USB_DEVICE.MEM_CONF: Power control +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_MEM_PD(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1)|value) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_MEM_PD() uint32 { + return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1 +} +func (o *USB_DEVICE_Type) SetMEM_CONF_USB_MEM_CLK_EN(value uint32) { + volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_DEVICE_Type) GetMEM_CONF_USB_MEM_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2) >> 1 +} + +// USB_DEVICE.DATE: Version control register +func (o *USB_DEVICE_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *USB_DEVICE_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// USB_WRAP Peripheral +type USB_WRAP_Type struct { + OTG_CONF volatile.Register32 // 0x0 + TEST_CONF volatile.Register32 // 0x4 + _ [1012]byte + DATE volatile.Register32 // 0x3FC +} + +// USB_WRAP.OTG_CONF: USB OTG Wrapper Configure Register +func (o *USB_WRAP_Type) SetOTG_CONF_SRP_SESSEND_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x1)|value) +} +func (o *USB_WRAP_Type) GetOTG_CONF_SRP_SESSEND_OVERRIDE() uint32 { + return volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x1 +} +func (o *USB_WRAP_Type) SetOTG_CONF_SRP_SESSEND_VALUE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_WRAP_Type) GetOTG_CONF_SRP_SESSEND_VALUE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PHY_SEL(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PHY_SEL() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x4) >> 2 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DFIFO_FORCE_PD(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x8)|value<<3) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DFIFO_FORCE_PD() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x8) >> 3 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DBNCE_FLTR_BYPASS(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x10)|value<<4) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DBNCE_FLTR_BYPASS() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x10) >> 4 +} +func (o *USB_WRAP_Type) SetOTG_CONF_EXCHG_PINS_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x20)|value<<5) +} +func (o *USB_WRAP_Type) GetOTG_CONF_EXCHG_PINS_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x20) >> 5 +} +func (o *USB_WRAP_Type) SetOTG_CONF_EXCHG_PINS(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x40)|value<<6) +} +func (o *USB_WRAP_Type) GetOTG_CONF_EXCHG_PINS() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x40) >> 6 +} +func (o *USB_WRAP_Type) SetOTG_CONF_VREFH(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x180)|value<<7) +} +func (o *USB_WRAP_Type) GetOTG_CONF_VREFH() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x180) >> 7 +} +func (o *USB_WRAP_Type) SetOTG_CONF_VREFL(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x600)|value<<9) +} +func (o *USB_WRAP_Type) GetOTG_CONF_VREFL() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x600) >> 9 +} +func (o *USB_WRAP_Type) SetOTG_CONF_VREF_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x800)|value<<11) +} +func (o *USB_WRAP_Type) GetOTG_CONF_VREF_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x800) >> 11 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PAD_PULL_OVERRIDE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PAD_PULL_OVERRIDE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x1000) >> 12 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DP_PULLUP(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x2000)|value<<13) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x2000) >> 13 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DP_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x4000)|value<<14) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DP_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x4000) >> 14 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DM_PULLUP(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x8000)|value<<15) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DM_PULLUP() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x8000) >> 15 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DM_PULLDOWN(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x10000)|value<<16) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DM_PULLDOWN() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x10000) >> 16 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PULLUP_VALUE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x20000)|value<<17) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PULLUP_VALUE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x20000) >> 17 +} +func (o *USB_WRAP_Type) SetOTG_CONF_USB_PAD_ENABLE(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x40000)|value<<18) +} +func (o *USB_WRAP_Type) GetOTG_CONF_USB_PAD_ENABLE() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x40000) >> 18 +} +func (o *USB_WRAP_Type) SetOTG_CONF_AHB_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x80000)|value<<19) +} +func (o *USB_WRAP_Type) GetOTG_CONF_AHB_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x80000) >> 19 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PHY_CLK_FORCE_ON(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x100000)|value<<20) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PHY_CLK_FORCE_ON() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x100000) >> 20 +} +func (o *USB_WRAP_Type) SetOTG_CONF_PHY_TX_EDGE_SEL(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x200000)|value<<21) +} +func (o *USB_WRAP_Type) GetOTG_CONF_PHY_TX_EDGE_SEL() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x200000) >> 21 +} +func (o *USB_WRAP_Type) SetOTG_CONF_DFIFO_FORCE_PU(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x400000)|value<<22) +} +func (o *USB_WRAP_Type) GetOTG_CONF_DFIFO_FORCE_PU() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x400000) >> 22 +} +func (o *USB_WRAP_Type) SetOTG_CONF_CLK_EN(value uint32) { + volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x80000000)|value<<31) +} +func (o *USB_WRAP_Type) GetOTG_CONF_CLK_EN() uint32 { + return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x80000000) >> 31 +} + +// USB_WRAP.TEST_CONF: USB Internal PHY Testing Register +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_ENABLE(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x1)|value) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_ENABLE() uint32 { + return volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x1 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_USB_OE(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x2)|value<<1) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_USB_OE() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x2) >> 1 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_TX_DP(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x4)|value<<2) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_TX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x4) >> 2 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_TX_DM(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x8)|value<<3) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_TX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x8) >> 3 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_RCV(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x10)|value<<4) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_RCV() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x10) >> 4 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_DP(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x20)|value<<5) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_DP() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x20) >> 5 +} +func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_DM(value uint32) { + volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x40)|value<<6) +} +func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_DM() uint32 { + return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x40) >> 6 +} + +// USB_WRAP.DATE: Version Control Register +func (o *USB_WRAP_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, value) +} +func (o *USB_WRAP_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) +} + +// WCL Peripheral +type WCL_Type struct { + Core_0_ENTRY_1_ADDR volatile.Register32 // 0x0 + Core_0_ENTRY_2_ADDR volatile.Register32 // 0x4 + Core_0_ENTRY_3_ADDR volatile.Register32 // 0x8 + Core_0_ENTRY_4_ADDR volatile.Register32 // 0xC + Core_0_ENTRY_5_ADDR volatile.Register32 // 0x10 + Core_0_ENTRY_6_ADDR volatile.Register32 // 0x14 + Core_0_ENTRY_7_ADDR volatile.Register32 // 0x18 + Core_0_ENTRY_8_ADDR volatile.Register32 // 0x1C + Core_0_ENTRY_9_ADDR volatile.Register32 // 0x20 + Core_0_ENTRY_10_ADDR volatile.Register32 // 0x24 + Core_0_ENTRY_11_ADDR volatile.Register32 // 0x28 + Core_0_ENTRY_12_ADDR volatile.Register32 // 0x2C + Core_0_ENTRY_13_ADDR volatile.Register32 // 0x30 + _ [72]byte + Core_0_ENTRY_CHECK volatile.Register32 // 0x7C + Core_0_STATUSTABLE1 volatile.Register32 // 0x80 + Core_0_STATUSTABLE2 volatile.Register32 // 0x84 + Core_0_STATUSTABLE3 volatile.Register32 // 0x88 + Core_0_STATUSTABLE4 volatile.Register32 // 0x8C + Core_0_STATUSTABLE5 volatile.Register32 // 0x90 + Core_0_STATUSTABLE6 volatile.Register32 // 0x94 + Core_0_STATUSTABLE7 volatile.Register32 // 0x98 + Core_0_STATUSTABLE8 volatile.Register32 // 0x9C + Core_0_STATUSTABLE9 volatile.Register32 // 0xA0 + Core_0_STATUSTABLE10 volatile.Register32 // 0xA4 + Core_0_STATUSTABLE11 volatile.Register32 // 0xA8 + Core_0_STATUSTABLE12 volatile.Register32 // 0xAC + Core_0_STATUSTABLE13 volatile.Register32 // 0xB0 + _ [72]byte + Core_0_STATUSTABLE_CURRENT volatile.Register32 // 0xFC + Core_0_MESSAGE_ADDR volatile.Register32 // 0x100 + Core_0_MESSAGE_MAX volatile.Register32 // 0x104 + Core_0_MESSAGE_PHASE volatile.Register32 // 0x108 + _ [52]byte + Core_0_World_TRIGGER_ADDR volatile.Register32 // 0x140 + Core_0_World_PREPARE volatile.Register32 // 0x144 + Core_0_World_UPDATE volatile.Register32 // 0x148 + Core_0_World_Cancel volatile.Register32 // 0x14C + Core_0_World_IRam0 volatile.Register32 // 0x150 + Core_0_World_DRam0_PIF volatile.Register32 // 0x154 + Core_0_World_Phase volatile.Register32 // 0x158 + _ [36]byte + Core_0_NMI_MASK_ENABLE volatile.Register32 // 0x180 + Core_0_NMI_MASK_TRIGGER_ADDR volatile.Register32 // 0x184 + Core_0_NMI_MASK_DISABLE volatile.Register32 // 0x188 + Core_0_NMI_MASK_CANCLE volatile.Register32 // 0x18C + Core_0_NMI_MASK volatile.Register32 // 0x190 + Core_0_NMI_MASK_PHASE volatile.Register32 // 0x194 + _ [616]byte + Core_1_ENTRY_1_ADDR volatile.Register32 // 0x400 + Core_1_ENTRY_2_ADDR volatile.Register32 // 0x404 + Core_1_ENTRY_3_ADDR volatile.Register32 // 0x408 + Core_1_ENTRY_4_ADDR volatile.Register32 // 0x40C + Core_1_ENTRY_5_ADDR volatile.Register32 // 0x410 + Core_1_ENTRY_6_ADDR volatile.Register32 // 0x414 + Core_1_ENTRY_7_ADDR volatile.Register32 // 0x418 + Core_1_ENTRY_8_ADDR volatile.Register32 // 0x41C + Core_1_ENTRY_9_ADDR volatile.Register32 // 0x420 + Core_1_ENTRY_10_ADDR volatile.Register32 // 0x424 + Core_1_ENTRY_11_ADDR volatile.Register32 // 0x428 + Core_1_ENTRY_12_ADDR volatile.Register32 // 0x42C + Core_1_ENTRY_13_ADDR volatile.Register32 // 0x430 + _ [72]byte + Core_1_ENTRY_CHECK volatile.Register32 // 0x47C + Core_1_STATUSTABLE1 volatile.Register32 // 0x480 + Core_1_STATUSTABLE2 volatile.Register32 // 0x484 + Core_1_STATUSTABLE3 volatile.Register32 // 0x488 + Core_1_STATUSTABLE4 volatile.Register32 // 0x48C + Core_1_STATUSTABLE5 volatile.Register32 // 0x490 + Core_1_STATUSTABLE6 volatile.Register32 // 0x494 + Core_1_STATUSTABLE7 volatile.Register32 // 0x498 + Core_1_STATUSTABLE8 volatile.Register32 // 0x49C + Core_1_STATUSTABLE9 volatile.Register32 // 0x4A0 + Core_1_STATUSTABLE10 volatile.Register32 // 0x4A4 + Core_1_STATUSTABLE11 volatile.Register32 // 0x4A8 + Core_1_STATUSTABLE12 volatile.Register32 // 0x4AC + Core_1_STATUSTABLE13 volatile.Register32 // 0x4B0 + _ [72]byte + Core_1_STATUSTABLE_CURRENT volatile.Register32 // 0x4FC + Core_1_MESSAGE_ADDR volatile.Register32 // 0x500 + Core_1_MESSAGE_MAX volatile.Register32 // 0x504 + Core_1_MESSAGE_PHASE volatile.Register32 // 0x508 + _ [52]byte + Core_1_World_TRIGGER_ADDR volatile.Register32 // 0x540 + Core_1_World_PREPARE volatile.Register32 // 0x544 + Core_1_World_UPDATE volatile.Register32 // 0x548 + Core_1_World_Cancel volatile.Register32 // 0x54C + Core_1_World_IRam0 volatile.Register32 // 0x550 + Core_1_World_DRam0_PIF volatile.Register32 // 0x554 + Core_1_World_Phase volatile.Register32 // 0x558 + _ [36]byte + Core_1_NMI_MASK_ENABLE volatile.Register32 // 0x580 + Core_1_NMI_MASK_TRIGGER_ADDR volatile.Register32 // 0x584 + Core_1_NMI_MASK_DISABLE volatile.Register32 // 0x588 + Core_1_NMI_MASK_CANCLE volatile.Register32 // 0x58C + Core_1_NMI_MASK volatile.Register32 // 0x590 + Core_1_NMI_MASK_PHASE volatile.Register32 // 0x594 +} + +// WCL.Core_0_ENTRY_1_ADDR: Core_0 Entry 1 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_1_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_1_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_1_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_1_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_2_ADDR: Core_0 Entry 2 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_2_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_2_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_2_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_2_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_3_ADDR: Core_0 Entry 3 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_3_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_3_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_3_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_3_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_4_ADDR: Core_0 Entry 4 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_4_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_4_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_4_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_4_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_5_ADDR: Core_0 Entry 5 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_5_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_5_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_5_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_5_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_6_ADDR: Core_0 Entry 6 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_6_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_6_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_6_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_6_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_7_ADDR: Core_0 Entry 7 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_7_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_7_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_7_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_7_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_8_ADDR: Core_0 Entry 8 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_8_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_8_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_8_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_8_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_9_ADDR: Core_0 Entry 9 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_9_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_9_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_9_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_9_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_10_ADDR: Core_0 Entry 10 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_10_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_10_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_10_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_10_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_11_ADDR: Core_0 Entry 11 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_11_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_11_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_11_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_11_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_12_ADDR: Core_0 Entry 12 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_12_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_12_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_12_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_12_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_13_ADDR: Core_0 Entry 13 address configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_13_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_13_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_ENTRY_13_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_ENTRY_13_ADDR.Reg) +} + +// WCL.Core_0_ENTRY_CHECK: Core_0 Entry check configuration Register +func (o *WCL_Type) SetCore_0_ENTRY_CHECK_CORE_0_ENTRY_CHECK(value uint32) { + volatile.StoreUint32(&o.Core_0_ENTRY_CHECK.Reg, volatile.LoadUint32(&o.Core_0_ENTRY_CHECK.Reg)&^(0x3ffe)|value<<1) +} +func (o *WCL_Type) GetCore_0_ENTRY_CHECK_CORE_0_ENTRY_CHECK() uint32 { + return (volatile.LoadUint32(&o.Core_0_ENTRY_CHECK.Reg) & 0x3ffe) >> 1 +} + +// WCL.Core_0_STATUSTABLE1: Status register of world switch of entry 1 +func (o *WCL_Type) SetCore_0_STATUSTABLE1_CORE_0_FROM_WORLD_1(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE1.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE1.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE1_CORE_0_FROM_WORLD_1() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE1.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE1_CORE_0_FROM_ENTRY_1(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE1.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE1.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE1_CORE_0_FROM_ENTRY_1() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE1.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE1_CORE_0_CURRENT_1(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE1.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE1.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE1_CORE_0_CURRENT_1() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE1.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE2: Status register of world switch of entry 2 +func (o *WCL_Type) SetCore_0_STATUSTABLE2_CORE_0_FROM_WORLD_2(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE2.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE2.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE2_CORE_0_FROM_WORLD_2() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE2.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE2_CORE_0_FROM_ENTRY_2(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE2.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE2.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE2_CORE_0_FROM_ENTRY_2() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE2.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE2_CORE_0_CURRENT_2(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE2.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE2.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE2_CORE_0_CURRENT_2() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE2.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE3: Status register of world switch of entry 3 +func (o *WCL_Type) SetCore_0_STATUSTABLE3_CORE_0_FROM_WORLD_3(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE3.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE3.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE3_CORE_0_FROM_WORLD_3() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE3.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE3_CORE_0_FROM_ENTRY_3(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE3.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE3.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE3_CORE_0_FROM_ENTRY_3() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE3.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE3_CORE_0_CURRENT_3(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE3.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE3.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE3_CORE_0_CURRENT_3() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE3.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE4: Status register of world switch of entry 4 +func (o *WCL_Type) SetCore_0_STATUSTABLE4_CORE_0_FROM_WORLD_4(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE4.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE4.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE4_CORE_0_FROM_WORLD_4() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE4.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE4_CORE_0_FROM_ENTRY_4(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE4.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE4.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE4_CORE_0_FROM_ENTRY_4() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE4.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE4_CORE_0_CURRENT_4(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE4.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE4.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE4_CORE_0_CURRENT_4() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE4.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE5: Status register of world switch of entry 5 +func (o *WCL_Type) SetCore_0_STATUSTABLE5_CORE_0_FROM_WORLD_5(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE5.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE5.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE5_CORE_0_FROM_WORLD_5() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE5.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE5_CORE_0_FROM_ENTRY_5(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE5.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE5.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE5_CORE_0_FROM_ENTRY_5() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE5.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE5_CORE_0_CURRENT_5(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE5.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE5.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE5_CORE_0_CURRENT_5() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE5.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE6: Status register of world switch of entry 6 +func (o *WCL_Type) SetCore_0_STATUSTABLE6_CORE_0_FROM_WORLD_6(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE6.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE6.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE6_CORE_0_FROM_WORLD_6() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE6.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE6_CORE_0_FROM_ENTRY_6(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE6.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE6.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE6_CORE_0_FROM_ENTRY_6() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE6.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE6_CORE_0_CURRENT_6(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE6.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE6.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE6_CORE_0_CURRENT_6() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE6.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE7: Status register of world switch of entry 7 +func (o *WCL_Type) SetCore_0_STATUSTABLE7_CORE_0_FROM_WORLD_7(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE7.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE7.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE7_CORE_0_FROM_WORLD_7() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE7.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE7_CORE_0_FROM_ENTRY_7(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE7.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE7.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE7_CORE_0_FROM_ENTRY_7() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE7.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE7_CORE_0_CURRENT_7(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE7.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE7.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE7_CORE_0_CURRENT_7() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE7.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE8: Status register of world switch of entry 8 +func (o *WCL_Type) SetCore_0_STATUSTABLE8_CORE_0_FROM_WORLD_8(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE8.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE8.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE8_CORE_0_FROM_WORLD_8() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE8.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE8_CORE_0_FROM_ENTRY_8(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE8.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE8.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE8_CORE_0_FROM_ENTRY_8() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE8.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE8_CORE_0_CURRENT_8(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE8.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE8.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE8_CORE_0_CURRENT_8() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE8.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE9: Status register of world switch of entry 9 +func (o *WCL_Type) SetCore_0_STATUSTABLE9_CORE_0_FROM_WORLD_9(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE9.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE9.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE9_CORE_0_FROM_WORLD_9() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE9.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE9_CORE_0_FROM_ENTRY_9(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE9.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE9.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE9_CORE_0_FROM_ENTRY_9() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE9.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE9_CORE_0_CURRENT_9(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE9.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE9.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE9_CORE_0_CURRENT_9() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE9.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE10: Status register of world switch of entry 10 +func (o *WCL_Type) SetCore_0_STATUSTABLE10_CORE_0_FROM_WORLD_10(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE10.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE10.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE10_CORE_0_FROM_WORLD_10() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE10.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE10_CORE_0_FROM_ENTRY_10(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE10.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE10.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE10_CORE_0_FROM_ENTRY_10() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE10.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE10_CORE_0_CURRENT_10(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE10.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE10.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE10_CORE_0_CURRENT_10() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE10.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE11: Status register of world switch of entry 11 +func (o *WCL_Type) SetCore_0_STATUSTABLE11_CORE_0_FROM_WORLD_11(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE11.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE11.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE11_CORE_0_FROM_WORLD_11() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE11.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE11_CORE_0_FROM_ENTRY_11(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE11.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE11.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE11_CORE_0_FROM_ENTRY_11() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE11.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE11_CORE_0_CURRENT_11(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE11.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE11.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE11_CORE_0_CURRENT_11() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE11.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE12: Status register of world switch of entry 12 +func (o *WCL_Type) SetCore_0_STATUSTABLE12_CORE_0_FROM_WORLD_12(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE12.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE12.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE12_CORE_0_FROM_WORLD_12() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE12.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE12_CORE_0_FROM_ENTRY_12(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE12.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE12.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE12_CORE_0_FROM_ENTRY_12() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE12.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE12_CORE_0_CURRENT_12(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE12.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE12.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE12_CORE_0_CURRENT_12() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE12.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE13: Status register of world switch of entry 13 +func (o *WCL_Type) SetCore_0_STATUSTABLE13_CORE_0_FROM_WORLD_13(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE13.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE13.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE13_CORE_0_FROM_WORLD_13() uint32 { + return volatile.LoadUint32(&o.Core_0_STATUSTABLE13.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE13_CORE_0_FROM_ENTRY_13(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE13.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE13.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE13_CORE_0_FROM_ENTRY_13() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE13.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_STATUSTABLE13_CORE_0_CURRENT_13(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE13.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE13.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE13_CORE_0_CURRENT_13() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE13.Reg) & 0x20) >> 5 +} + +// WCL.Core_0_STATUSTABLE_CURRENT: Status register of statustable current +func (o *WCL_Type) SetCore_0_STATUSTABLE_CURRENT_CORE_0_STATUSTABLE_CURRENT(value uint32) { + volatile.StoreUint32(&o.Core_0_STATUSTABLE_CURRENT.Reg, volatile.LoadUint32(&o.Core_0_STATUSTABLE_CURRENT.Reg)&^(0x3ffe)|value<<1) +} +func (o *WCL_Type) GetCore_0_STATUSTABLE_CURRENT_CORE_0_STATUSTABLE_CURRENT() uint32 { + return (volatile.LoadUint32(&o.Core_0_STATUSTABLE_CURRENT.Reg) & 0x3ffe) >> 1 +} + +// WCL.Core_0_MESSAGE_ADDR: Clear writer_buffer write address configuration register +func (o *WCL_Type) SetCore_0_MESSAGE_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_MESSAGE_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_MESSAGE_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_MESSAGE_ADDR.Reg) +} + +// WCL.Core_0_MESSAGE_MAX: Clear writer_buffer write number configuration register +func (o *WCL_Type) SetCore_0_MESSAGE_MAX_CORE_0_MESSAGE_MAX(value uint32) { + volatile.StoreUint32(&o.Core_0_MESSAGE_MAX.Reg, volatile.LoadUint32(&o.Core_0_MESSAGE_MAX.Reg)&^(0xf)|value) +} +func (o *WCL_Type) GetCore_0_MESSAGE_MAX_CORE_0_MESSAGE_MAX() uint32 { + return volatile.LoadUint32(&o.Core_0_MESSAGE_MAX.Reg) & 0xf +} + +// WCL.Core_0_MESSAGE_PHASE: Clear writer_buffer status register +func (o *WCL_Type) SetCore_0_MESSAGE_PHASE_CORE_0_MESSAGE_MATCH(value uint32) { + volatile.StoreUint32(&o.Core_0_MESSAGE_PHASE.Reg, volatile.LoadUint32(&o.Core_0_MESSAGE_PHASE.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_MESSAGE_PHASE_CORE_0_MESSAGE_MATCH() uint32 { + return volatile.LoadUint32(&o.Core_0_MESSAGE_PHASE.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_0_MESSAGE_PHASE_CORE_0_MESSAGE_EXPECT(value uint32) { + volatile.StoreUint32(&o.Core_0_MESSAGE_PHASE.Reg, volatile.LoadUint32(&o.Core_0_MESSAGE_PHASE.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_0_MESSAGE_PHASE_CORE_0_MESSAGE_EXPECT() uint32 { + return (volatile.LoadUint32(&o.Core_0_MESSAGE_PHASE.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_0_MESSAGE_PHASE_CORE_0_MESSAGE_DATAPHASE(value uint32) { + volatile.StoreUint32(&o.Core_0_MESSAGE_PHASE.Reg, volatile.LoadUint32(&o.Core_0_MESSAGE_PHASE.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_0_MESSAGE_PHASE_CORE_0_MESSAGE_DATAPHASE() uint32 { + return (volatile.LoadUint32(&o.Core_0_MESSAGE_PHASE.Reg) & 0x20) >> 5 +} +func (o *WCL_Type) SetCore_0_MESSAGE_PHASE_CORE_0_MESSAGE_ADDRESSPHASE(value uint32) { + volatile.StoreUint32(&o.Core_0_MESSAGE_PHASE.Reg, volatile.LoadUint32(&o.Core_0_MESSAGE_PHASE.Reg)&^(0x40)|value<<6) +} +func (o *WCL_Type) GetCore_0_MESSAGE_PHASE_CORE_0_MESSAGE_ADDRESSPHASE() uint32 { + return (volatile.LoadUint32(&o.Core_0_MESSAGE_PHASE.Reg) & 0x40) >> 6 +} + +// WCL.Core_0_World_TRIGGER_ADDR: Core_0 trigger address configuration Register +func (o *WCL_Type) SetCore_0_World_TRIGGER_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_World_TRIGGER_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_World_TRIGGER_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_World_TRIGGER_ADDR.Reg) +} + +// WCL.Core_0_World_PREPARE: Core_0 prepare world configuration Register +func (o *WCL_Type) SetCore_0_World_PREPARE_CORE_0_WORLD_PREPARE(value uint32) { + volatile.StoreUint32(&o.Core_0_World_PREPARE.Reg, volatile.LoadUint32(&o.Core_0_World_PREPARE.Reg)&^(0x3)|value) +} +func (o *WCL_Type) GetCore_0_World_PREPARE_CORE_0_WORLD_PREPARE() uint32 { + return volatile.LoadUint32(&o.Core_0_World_PREPARE.Reg) & 0x3 +} + +// WCL.Core_0_World_UPDATE: Core_0 configuration update register +func (o *WCL_Type) SetCore_0_World_UPDATE(value uint32) { + volatile.StoreUint32(&o.Core_0_World_UPDATE.Reg, value) +} +func (o *WCL_Type) GetCore_0_World_UPDATE() uint32 { + return volatile.LoadUint32(&o.Core_0_World_UPDATE.Reg) +} + +// WCL.Core_0_World_Cancel: Core_0 configuration cancel register +func (o *WCL_Type) SetCore_0_World_Cancel(value uint32) { + volatile.StoreUint32(&o.Core_0_World_Cancel.Reg, value) +} +func (o *WCL_Type) GetCore_0_World_Cancel() uint32 { + return volatile.LoadUint32(&o.Core_0_World_Cancel.Reg) +} + +// WCL.Core_0_World_IRam0: Core_0 Iram0 world register +func (o *WCL_Type) SetCore_0_World_IRam0_CORE_0_WORLD_IRAM0(value uint32) { + volatile.StoreUint32(&o.Core_0_World_IRam0.Reg, volatile.LoadUint32(&o.Core_0_World_IRam0.Reg)&^(0x3)|value) +} +func (o *WCL_Type) GetCore_0_World_IRam0_CORE_0_WORLD_IRAM0() uint32 { + return volatile.LoadUint32(&o.Core_0_World_IRam0.Reg) & 0x3 +} + +// WCL.Core_0_World_DRam0_PIF: Core_0 dram0 and PIF world register +func (o *WCL_Type) SetCore_0_World_DRam0_PIF_CORE_0_WORLD_DRAM0_PIF(value uint32) { + volatile.StoreUint32(&o.Core_0_World_DRam0_PIF.Reg, volatile.LoadUint32(&o.Core_0_World_DRam0_PIF.Reg)&^(0x3)|value) +} +func (o *WCL_Type) GetCore_0_World_DRam0_PIF_CORE_0_WORLD_DRAM0_PIF() uint32 { + return volatile.LoadUint32(&o.Core_0_World_DRam0_PIF.Reg) & 0x3 +} + +// WCL.Core_0_World_Phase: Core_0 world status register +func (o *WCL_Type) SetCore_0_World_Phase_CORE_0_WORLD_PHASE(value uint32) { + volatile.StoreUint32(&o.Core_0_World_Phase.Reg, volatile.LoadUint32(&o.Core_0_World_Phase.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_World_Phase_CORE_0_WORLD_PHASE() uint32 { + return volatile.LoadUint32(&o.Core_0_World_Phase.Reg) & 0x1 +} + +// WCL.Core_0_NMI_MASK_ENABLE: Core_0 NMI mask enable register +func (o *WCL_Type) SetCore_0_NMI_MASK_ENABLE(value uint32) { + volatile.StoreUint32(&o.Core_0_NMI_MASK_ENABLE.Reg, value) +} +func (o *WCL_Type) GetCore_0_NMI_MASK_ENABLE() uint32 { + return volatile.LoadUint32(&o.Core_0_NMI_MASK_ENABLE.Reg) +} + +// WCL.Core_0_NMI_MASK_TRIGGER_ADDR: Core_0 NMI mask trigger address register +func (o *WCL_Type) SetCore_0_NMI_MASK_TRIGGER_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_0_NMI_MASK_TRIGGER_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_0_NMI_MASK_TRIGGER_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_0_NMI_MASK_TRIGGER_ADDR.Reg) +} + +// WCL.Core_0_NMI_MASK_DISABLE: Core_0 NMI mask disable register +func (o *WCL_Type) SetCore_0_NMI_MASK_DISABLE(value uint32) { + volatile.StoreUint32(&o.Core_0_NMI_MASK_DISABLE.Reg, value) +} +func (o *WCL_Type) GetCore_0_NMI_MASK_DISABLE() uint32 { + return volatile.LoadUint32(&o.Core_0_NMI_MASK_DISABLE.Reg) +} + +// WCL.Core_0_NMI_MASK_CANCLE: Core_0 NMI mask disable register +func (o *WCL_Type) SetCore_0_NMI_MASK_CANCLE(value uint32) { + volatile.StoreUint32(&o.Core_0_NMI_MASK_CANCLE.Reg, value) +} +func (o *WCL_Type) GetCore_0_NMI_MASK_CANCLE() uint32 { + return volatile.LoadUint32(&o.Core_0_NMI_MASK_CANCLE.Reg) +} + +// WCL.Core_0_NMI_MASK: Core_0 NMI mask register +func (o *WCL_Type) SetCore_0_NMI_MASK_CORE_0_NMI_MASK(value uint32) { + volatile.StoreUint32(&o.Core_0_NMI_MASK.Reg, volatile.LoadUint32(&o.Core_0_NMI_MASK.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_NMI_MASK_CORE_0_NMI_MASK() uint32 { + return volatile.LoadUint32(&o.Core_0_NMI_MASK.Reg) & 0x1 +} + +// WCL.Core_0_NMI_MASK_PHASE: Core_0 NMI mask phase register +func (o *WCL_Type) SetCore_0_NMI_MASK_PHASE_CORE_0_NMI_MASK_PHASE(value uint32) { + volatile.StoreUint32(&o.Core_0_NMI_MASK_PHASE.Reg, volatile.LoadUint32(&o.Core_0_NMI_MASK_PHASE.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_0_NMI_MASK_PHASE_CORE_0_NMI_MASK_PHASE() uint32 { + return volatile.LoadUint32(&o.Core_0_NMI_MASK_PHASE.Reg) & 0x1 +} + +// WCL.Core_1_ENTRY_1_ADDR: Core_1 Entry 1 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_1_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_1_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_1_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_1_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_2_ADDR: Core_1 Entry 2 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_2_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_2_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_2_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_2_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_3_ADDR: Core_1 Entry 3 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_3_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_3_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_3_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_3_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_4_ADDR: Core_1 Entry 4 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_4_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_4_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_4_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_4_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_5_ADDR: Core_1 Entry 5 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_5_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_5_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_5_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_5_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_6_ADDR: Core_1 Entry 6 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_6_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_6_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_6_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_6_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_7_ADDR: Core_1 Entry 7 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_7_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_7_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_7_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_7_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_8_ADDR: Core_1 Entry 8 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_8_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_8_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_8_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_8_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_9_ADDR: Core_1 Entry 9 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_9_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_9_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_9_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_9_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_10_ADDR: Core_1 Entry 10 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_10_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_10_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_10_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_10_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_11_ADDR: Core_1 Entry 11 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_11_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_11_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_11_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_11_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_12_ADDR: Core_1 Entry 12 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_12_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_12_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_12_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_12_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_13_ADDR: Core_1 Entry 13 address configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_13_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_13_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_ENTRY_13_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_ENTRY_13_ADDR.Reg) +} + +// WCL.Core_1_ENTRY_CHECK: Core_1 Entry check configuration Register +func (o *WCL_Type) SetCore_1_ENTRY_CHECK_CORE_1_ENTRY_CHECK(value uint32) { + volatile.StoreUint32(&o.Core_1_ENTRY_CHECK.Reg, volatile.LoadUint32(&o.Core_1_ENTRY_CHECK.Reg)&^(0x3ffe)|value<<1) +} +func (o *WCL_Type) GetCore_1_ENTRY_CHECK_CORE_1_ENTRY_CHECK() uint32 { + return (volatile.LoadUint32(&o.Core_1_ENTRY_CHECK.Reg) & 0x3ffe) >> 1 +} + +// WCL.Core_1_STATUSTABLE1: Status register of world switch of entry 1 +func (o *WCL_Type) SetCore_1_STATUSTABLE1_CORE_1_FROM_WORLD_1(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE1.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE1.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE1_CORE_1_FROM_WORLD_1() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE1.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE1_CORE_1_FROM_ENTRY_1(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE1.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE1.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE1_CORE_1_FROM_ENTRY_1() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE1.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE1_CORE_1_CURRENT_1(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE1.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE1.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE1_CORE_1_CURRENT_1() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE1.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE2: Status register of world switch of entry 2 +func (o *WCL_Type) SetCore_1_STATUSTABLE2_CORE_1_FROM_WORLD_2(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE2.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE2.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE2_CORE_1_FROM_WORLD_2() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE2.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE2_CORE_1_FROM_ENTRY_2(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE2.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE2.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE2_CORE_1_FROM_ENTRY_2() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE2.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE2_CORE_1_CURRENT_2(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE2.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE2.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE2_CORE_1_CURRENT_2() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE2.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE3: Status register of world switch of entry 3 +func (o *WCL_Type) SetCore_1_STATUSTABLE3_CORE_1_FROM_WORLD_3(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE3.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE3.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE3_CORE_1_FROM_WORLD_3() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE3.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE3_CORE_1_FROM_ENTRY_3(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE3.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE3.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE3_CORE_1_FROM_ENTRY_3() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE3.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE3_CORE_1_CURRENT_3(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE3.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE3.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE3_CORE_1_CURRENT_3() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE3.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE4: Status register of world switch of entry 4 +func (o *WCL_Type) SetCore_1_STATUSTABLE4_CORE_1_FROM_WORLD_4(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE4.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE4.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE4_CORE_1_FROM_WORLD_4() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE4.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE4_CORE_1_FROM_ENTRY_4(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE4.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE4.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE4_CORE_1_FROM_ENTRY_4() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE4.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE4_CORE_1_CURRENT_4(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE4.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE4.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE4_CORE_1_CURRENT_4() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE4.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE5: Status register of world switch of entry 5 +func (o *WCL_Type) SetCore_1_STATUSTABLE5_CORE_1_FROM_WORLD_5(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE5.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE5.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE5_CORE_1_FROM_WORLD_5() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE5.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE5_CORE_1_FROM_ENTRY_5(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE5.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE5.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE5_CORE_1_FROM_ENTRY_5() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE5.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE5_CORE_1_CURRENT_5(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE5.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE5.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE5_CORE_1_CURRENT_5() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE5.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE6: Status register of world switch of entry 6 +func (o *WCL_Type) SetCore_1_STATUSTABLE6_CORE_1_FROM_WORLD_6(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE6.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE6.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE6_CORE_1_FROM_WORLD_6() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE6.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE6_CORE_1_FROM_ENTRY_6(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE6.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE6.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE6_CORE_1_FROM_ENTRY_6() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE6.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE6_CORE_1_CURRENT_6(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE6.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE6.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE6_CORE_1_CURRENT_6() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE6.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE7: Status register of world switch of entry 7 +func (o *WCL_Type) SetCore_1_STATUSTABLE7_CORE_1_FROM_WORLD_7(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE7.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE7.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE7_CORE_1_FROM_WORLD_7() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE7.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE7_CORE_1_FROM_ENTRY_7(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE7.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE7.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE7_CORE_1_FROM_ENTRY_7() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE7.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE7_CORE_1_CURRENT_7(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE7.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE7.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE7_CORE_1_CURRENT_7() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE7.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE8: Status register of world switch of entry 8 +func (o *WCL_Type) SetCore_1_STATUSTABLE8_CORE_1_FROM_WORLD_8(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE8.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE8.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE8_CORE_1_FROM_WORLD_8() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE8.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE8_CORE_1_FROM_ENTRY_8(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE8.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE8.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE8_CORE_1_FROM_ENTRY_8() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE8.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE8_CORE_1_CURRENT_8(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE8.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE8.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE8_CORE_1_CURRENT_8() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE8.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE9: Status register of world switch of entry 9 +func (o *WCL_Type) SetCore_1_STATUSTABLE9_CORE_1_FROM_WORLD_9(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE9.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE9.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE9_CORE_1_FROM_WORLD_9() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE9.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE9_CORE_1_FROM_ENTRY_9(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE9.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE9.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE9_CORE_1_FROM_ENTRY_9() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE9.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE9_CORE_1_CURRENT_9(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE9.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE9.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE9_CORE_1_CURRENT_9() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE9.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE10: Status register of world switch of entry 10 +func (o *WCL_Type) SetCore_1_STATUSTABLE10_CORE_1_FROM_WORLD_10(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE10.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE10.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE10_CORE_1_FROM_WORLD_10() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE10.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE10_CORE_1_FROM_ENTRY_10(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE10.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE10.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE10_CORE_1_FROM_ENTRY_10() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE10.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE10_CORE_1_CURRENT_10(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE10.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE10.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE10_CORE_1_CURRENT_10() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE10.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE11: Status register of world switch of entry 11 +func (o *WCL_Type) SetCore_1_STATUSTABLE11_CORE_1_FROM_WORLD_11(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE11.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE11.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE11_CORE_1_FROM_WORLD_11() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE11.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE11_CORE_1_FROM_ENTRY_11(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE11.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE11.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE11_CORE_1_FROM_ENTRY_11() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE11.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE11_CORE_1_CURRENT_11(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE11.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE11.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE11_CORE_1_CURRENT_11() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE11.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE12: Status register of world switch of entry 12 +func (o *WCL_Type) SetCore_1_STATUSTABLE12_CORE_1_FROM_WORLD_12(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE12.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE12.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE12_CORE_1_FROM_WORLD_12() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE12.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE12_CORE_1_FROM_ENTRY_12(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE12.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE12.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE12_CORE_1_FROM_ENTRY_12() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE12.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE12_CORE_1_CURRENT_12(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE12.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE12.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE12_CORE_1_CURRENT_12() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE12.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE13: Status register of world switch of entry 13 +func (o *WCL_Type) SetCore_1_STATUSTABLE13_CORE_1_FROM_WORLD_13(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE13.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE13.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE13_CORE_1_FROM_WORLD_13() uint32 { + return volatile.LoadUint32(&o.Core_1_STATUSTABLE13.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE13_CORE_1_FROM_ENTRY_13(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE13.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE13.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE13_CORE_1_FROM_ENTRY_13() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE13.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_STATUSTABLE13_CORE_1_CURRENT_13(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE13.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE13.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE13_CORE_1_CURRENT_13() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE13.Reg) & 0x20) >> 5 +} + +// WCL.Core_1_STATUSTABLE_CURRENT: Status register of statustable current +func (o *WCL_Type) SetCore_1_STATUSTABLE_CURRENT_CORE_1_STATUSTABLE_CURRENT(value uint32) { + volatile.StoreUint32(&o.Core_1_STATUSTABLE_CURRENT.Reg, volatile.LoadUint32(&o.Core_1_STATUSTABLE_CURRENT.Reg)&^(0x3ffe)|value<<1) +} +func (o *WCL_Type) GetCore_1_STATUSTABLE_CURRENT_CORE_1_STATUSTABLE_CURRENT() uint32 { + return (volatile.LoadUint32(&o.Core_1_STATUSTABLE_CURRENT.Reg) & 0x3ffe) >> 1 +} + +// WCL.Core_1_MESSAGE_ADDR: Clear writer_buffer write address configuration register +func (o *WCL_Type) SetCore_1_MESSAGE_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_MESSAGE_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_MESSAGE_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_MESSAGE_ADDR.Reg) +} + +// WCL.Core_1_MESSAGE_MAX: Clear writer_buffer write number configuration register +func (o *WCL_Type) SetCore_1_MESSAGE_MAX_CORE_1_MESSAGE_MAX(value uint32) { + volatile.StoreUint32(&o.Core_1_MESSAGE_MAX.Reg, volatile.LoadUint32(&o.Core_1_MESSAGE_MAX.Reg)&^(0xf)|value) +} +func (o *WCL_Type) GetCore_1_MESSAGE_MAX_CORE_1_MESSAGE_MAX() uint32 { + return volatile.LoadUint32(&o.Core_1_MESSAGE_MAX.Reg) & 0xf +} + +// WCL.Core_1_MESSAGE_PHASE: Clear writer_buffer status register +func (o *WCL_Type) SetCore_1_MESSAGE_PHASE_CORE_1_MESSAGE_MATCH(value uint32) { + volatile.StoreUint32(&o.Core_1_MESSAGE_PHASE.Reg, volatile.LoadUint32(&o.Core_1_MESSAGE_PHASE.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_MESSAGE_PHASE_CORE_1_MESSAGE_MATCH() uint32 { + return volatile.LoadUint32(&o.Core_1_MESSAGE_PHASE.Reg) & 0x1 +} +func (o *WCL_Type) SetCore_1_MESSAGE_PHASE_CORE_1_MESSAGE_EXPECT(value uint32) { + volatile.StoreUint32(&o.Core_1_MESSAGE_PHASE.Reg, volatile.LoadUint32(&o.Core_1_MESSAGE_PHASE.Reg)&^(0x1e)|value<<1) +} +func (o *WCL_Type) GetCore_1_MESSAGE_PHASE_CORE_1_MESSAGE_EXPECT() uint32 { + return (volatile.LoadUint32(&o.Core_1_MESSAGE_PHASE.Reg) & 0x1e) >> 1 +} +func (o *WCL_Type) SetCore_1_MESSAGE_PHASE_CORE_1_MESSAGE_DATAPHASE(value uint32) { + volatile.StoreUint32(&o.Core_1_MESSAGE_PHASE.Reg, volatile.LoadUint32(&o.Core_1_MESSAGE_PHASE.Reg)&^(0x20)|value<<5) +} +func (o *WCL_Type) GetCore_1_MESSAGE_PHASE_CORE_1_MESSAGE_DATAPHASE() uint32 { + return (volatile.LoadUint32(&o.Core_1_MESSAGE_PHASE.Reg) & 0x20) >> 5 +} +func (o *WCL_Type) SetCore_1_MESSAGE_PHASE_CORE_1_MESSAGE_ADDRESSPHASE(value uint32) { + volatile.StoreUint32(&o.Core_1_MESSAGE_PHASE.Reg, volatile.LoadUint32(&o.Core_1_MESSAGE_PHASE.Reg)&^(0x40)|value<<6) +} +func (o *WCL_Type) GetCore_1_MESSAGE_PHASE_CORE_1_MESSAGE_ADDRESSPHASE() uint32 { + return (volatile.LoadUint32(&o.Core_1_MESSAGE_PHASE.Reg) & 0x40) >> 6 +} + +// WCL.Core_1_World_TRIGGER_ADDR: Core_1 trigger address configuration Register +func (o *WCL_Type) SetCore_1_World_TRIGGER_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_World_TRIGGER_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_World_TRIGGER_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_World_TRIGGER_ADDR.Reg) +} + +// WCL.Core_1_World_PREPARE: Core_1 prepare world configuration Register +func (o *WCL_Type) SetCore_1_World_PREPARE_CORE_1_WORLD_PREPARE(value uint32) { + volatile.StoreUint32(&o.Core_1_World_PREPARE.Reg, volatile.LoadUint32(&o.Core_1_World_PREPARE.Reg)&^(0x3)|value) +} +func (o *WCL_Type) GetCore_1_World_PREPARE_CORE_1_WORLD_PREPARE() uint32 { + return volatile.LoadUint32(&o.Core_1_World_PREPARE.Reg) & 0x3 +} + +// WCL.Core_1_World_UPDATE: Core_1 configuration update register +func (o *WCL_Type) SetCore_1_World_UPDATE(value uint32) { + volatile.StoreUint32(&o.Core_1_World_UPDATE.Reg, value) +} +func (o *WCL_Type) GetCore_1_World_UPDATE() uint32 { + return volatile.LoadUint32(&o.Core_1_World_UPDATE.Reg) +} + +// WCL.Core_1_World_Cancel: Core_1 configuration cancel register +func (o *WCL_Type) SetCore_1_World_Cancel(value uint32) { + volatile.StoreUint32(&o.Core_1_World_Cancel.Reg, value) +} +func (o *WCL_Type) GetCore_1_World_Cancel() uint32 { + return volatile.LoadUint32(&o.Core_1_World_Cancel.Reg) +} + +// WCL.Core_1_World_IRam0: Core_1 Iram0 world register +func (o *WCL_Type) SetCore_1_World_IRam0_CORE_1_WORLD_IRAM0(value uint32) { + volatile.StoreUint32(&o.Core_1_World_IRam0.Reg, volatile.LoadUint32(&o.Core_1_World_IRam0.Reg)&^(0x3)|value) +} +func (o *WCL_Type) GetCore_1_World_IRam0_CORE_1_WORLD_IRAM0() uint32 { + return volatile.LoadUint32(&o.Core_1_World_IRam0.Reg) & 0x3 +} + +// WCL.Core_1_World_DRam0_PIF: Core_1 dram0 and PIF world register +func (o *WCL_Type) SetCore_1_World_DRam0_PIF_CORE_1_WORLD_DRAM0_PIF(value uint32) { + volatile.StoreUint32(&o.Core_1_World_DRam0_PIF.Reg, volatile.LoadUint32(&o.Core_1_World_DRam0_PIF.Reg)&^(0x3)|value) +} +func (o *WCL_Type) GetCore_1_World_DRam0_PIF_CORE_1_WORLD_DRAM0_PIF() uint32 { + return volatile.LoadUint32(&o.Core_1_World_DRam0_PIF.Reg) & 0x3 +} + +// WCL.Core_1_World_Phase: Core_0 world status register +func (o *WCL_Type) SetCore_1_World_Phase_CORE_1_WORLD_PHASE(value uint32) { + volatile.StoreUint32(&o.Core_1_World_Phase.Reg, volatile.LoadUint32(&o.Core_1_World_Phase.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_World_Phase_CORE_1_WORLD_PHASE() uint32 { + return volatile.LoadUint32(&o.Core_1_World_Phase.Reg) & 0x1 +} + +// WCL.Core_1_NMI_MASK_ENABLE: Core_1 NMI mask enable register +func (o *WCL_Type) SetCore_1_NMI_MASK_ENABLE(value uint32) { + volatile.StoreUint32(&o.Core_1_NMI_MASK_ENABLE.Reg, value) +} +func (o *WCL_Type) GetCore_1_NMI_MASK_ENABLE() uint32 { + return volatile.LoadUint32(&o.Core_1_NMI_MASK_ENABLE.Reg) +} + +// WCL.Core_1_NMI_MASK_TRIGGER_ADDR: Core_1 NMI mask trigger addr register +func (o *WCL_Type) SetCore_1_NMI_MASK_TRIGGER_ADDR(value uint32) { + volatile.StoreUint32(&o.Core_1_NMI_MASK_TRIGGER_ADDR.Reg, value) +} +func (o *WCL_Type) GetCore_1_NMI_MASK_TRIGGER_ADDR() uint32 { + return volatile.LoadUint32(&o.Core_1_NMI_MASK_TRIGGER_ADDR.Reg) +} + +// WCL.Core_1_NMI_MASK_DISABLE: Core_1 NMI mask disable register +func (o *WCL_Type) SetCore_1_NMI_MASK_DISABLE(value uint32) { + volatile.StoreUint32(&o.Core_1_NMI_MASK_DISABLE.Reg, value) +} +func (o *WCL_Type) GetCore_1_NMI_MASK_DISABLE() uint32 { + return volatile.LoadUint32(&o.Core_1_NMI_MASK_DISABLE.Reg) +} + +// WCL.Core_1_NMI_MASK_CANCLE: Core_1 NMI mask disable register +func (o *WCL_Type) SetCore_1_NMI_MASK_CANCLE(value uint32) { + volatile.StoreUint32(&o.Core_1_NMI_MASK_CANCLE.Reg, value) +} +func (o *WCL_Type) GetCore_1_NMI_MASK_CANCLE() uint32 { + return volatile.LoadUint32(&o.Core_1_NMI_MASK_CANCLE.Reg) +} + +// WCL.Core_1_NMI_MASK: Core_1 NMI mask register +func (o *WCL_Type) SetCore_1_NMI_MASK_CORE_1_NMI_MASK(value uint32) { + volatile.StoreUint32(&o.Core_1_NMI_MASK.Reg, volatile.LoadUint32(&o.Core_1_NMI_MASK.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_NMI_MASK_CORE_1_NMI_MASK() uint32 { + return volatile.LoadUint32(&o.Core_1_NMI_MASK.Reg) & 0x1 +} + +// WCL.Core_1_NMI_MASK_PHASE: Core_1 NMI mask phase register +func (o *WCL_Type) SetCore_1_NMI_MASK_PHASE_CORE_1_NMI_MASK_PHASE(value uint32) { + volatile.StoreUint32(&o.Core_1_NMI_MASK_PHASE.Reg, volatile.LoadUint32(&o.Core_1_NMI_MASK_PHASE.Reg)&^(0x1)|value) +} +func (o *WCL_Type) GetCore_1_NMI_MASK_PHASE_CORE_1_NMI_MASK_PHASE() uint32 { + return volatile.LoadUint32(&o.Core_1_NMI_MASK_PHASE.Reg) & 0x1 +} + +// XTS-AES-128 Flash Encryption +type XTS_AES_Type struct { + PLAIN_0 volatile.Register32 // 0x0 + PLAIN_1 volatile.Register32 // 0x4 + PLAIN_2 volatile.Register32 // 0x8 + PLAIN_3 volatile.Register32 // 0xC + PLAIN_4 volatile.Register32 // 0x10 + PLAIN_5 volatile.Register32 // 0x14 + PLAIN_6 volatile.Register32 // 0x18 + PLAIN_7 volatile.Register32 // 0x1C + PLAIN_8 volatile.Register32 // 0x20 + PLAIN_9 volatile.Register32 // 0x24 + PLAIN_10 volatile.Register32 // 0x28 + PLAIN_11 volatile.Register32 // 0x2C + PLAIN_12 volatile.Register32 // 0x30 + PLAIN_13 volatile.Register32 // 0x34 + PLAIN_14 volatile.Register32 // 0x38 + PLAIN_15 volatile.Register32 // 0x3C + LINESIZE volatile.Register32 // 0x40 + DESTINATION volatile.Register32 // 0x44 + PHYSICAL_ADDRESS volatile.Register32 // 0x48 + TRIGGER volatile.Register32 // 0x4C + RELEASE volatile.Register32 // 0x50 + DESTROY volatile.Register32 // 0x54 + STATE volatile.Register32 // 0x58 + DATE volatile.Register32 // 0x5C +} + +// XTS_AES.PLAIN_0: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_0(value uint32) { + volatile.StoreUint32(&o.PLAIN_0.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_0() uint32 { + return volatile.LoadUint32(&o.PLAIN_0.Reg) +} + +// XTS_AES.PLAIN_1: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_1(value uint32) { + volatile.StoreUint32(&o.PLAIN_1.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_1() uint32 { + return volatile.LoadUint32(&o.PLAIN_1.Reg) +} + +// XTS_AES.PLAIN_2: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_2(value uint32) { + volatile.StoreUint32(&o.PLAIN_2.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_2() uint32 { + return volatile.LoadUint32(&o.PLAIN_2.Reg) +} + +// XTS_AES.PLAIN_3: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_3(value uint32) { + volatile.StoreUint32(&o.PLAIN_3.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_3() uint32 { + return volatile.LoadUint32(&o.PLAIN_3.Reg) +} + +// XTS_AES.PLAIN_4: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_4(value uint32) { + volatile.StoreUint32(&o.PLAIN_4.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_4() uint32 { + return volatile.LoadUint32(&o.PLAIN_4.Reg) +} + +// XTS_AES.PLAIN_5: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_5(value uint32) { + volatile.StoreUint32(&o.PLAIN_5.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_5() uint32 { + return volatile.LoadUint32(&o.PLAIN_5.Reg) +} + +// XTS_AES.PLAIN_6: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_6(value uint32) { + volatile.StoreUint32(&o.PLAIN_6.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_6() uint32 { + return volatile.LoadUint32(&o.PLAIN_6.Reg) +} + +// XTS_AES.PLAIN_7: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_7(value uint32) { + volatile.StoreUint32(&o.PLAIN_7.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_7() uint32 { + return volatile.LoadUint32(&o.PLAIN_7.Reg) +} + +// XTS_AES.PLAIN_8: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_8(value uint32) { + volatile.StoreUint32(&o.PLAIN_8.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_8() uint32 { + return volatile.LoadUint32(&o.PLAIN_8.Reg) +} + +// XTS_AES.PLAIN_9: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_9(value uint32) { + volatile.StoreUint32(&o.PLAIN_9.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_9() uint32 { + return volatile.LoadUint32(&o.PLAIN_9.Reg) +} + +// XTS_AES.PLAIN_10: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_10(value uint32) { + volatile.StoreUint32(&o.PLAIN_10.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_10() uint32 { + return volatile.LoadUint32(&o.PLAIN_10.Reg) +} + +// XTS_AES.PLAIN_11: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_11(value uint32) { + volatile.StoreUint32(&o.PLAIN_11.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_11() uint32 { + return volatile.LoadUint32(&o.PLAIN_11.Reg) +} + +// XTS_AES.PLAIN_12: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_12(value uint32) { + volatile.StoreUint32(&o.PLAIN_12.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_12() uint32 { + return volatile.LoadUint32(&o.PLAIN_12.Reg) +} + +// XTS_AES.PLAIN_13: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_13(value uint32) { + volatile.StoreUint32(&o.PLAIN_13.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_13() uint32 { + return volatile.LoadUint32(&o.PLAIN_13.Reg) +} + +// XTS_AES.PLAIN_14: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_14(value uint32) { + volatile.StoreUint32(&o.PLAIN_14.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_14() uint32 { + return volatile.LoadUint32(&o.PLAIN_14.Reg) +} + +// XTS_AES.PLAIN_15: Plaintext register %s +func (o *XTS_AES_Type) SetPLAIN_15(value uint32) { + volatile.StoreUint32(&o.PLAIN_15.Reg, value) +} +func (o *XTS_AES_Type) GetPLAIN_15() uint32 { + return volatile.LoadUint32(&o.PLAIN_15.Reg) +} + +// XTS_AES.LINESIZE: XTS-AES line-size register +func (o *XTS_AES_Type) SetLINESIZE(value uint32) { + volatile.StoreUint32(&o.LINESIZE.Reg, volatile.LoadUint32(&o.LINESIZE.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetLINESIZE() uint32 { + return volatile.LoadUint32(&o.LINESIZE.Reg) & 0x1 +} + +// XTS_AES.DESTINATION: XTS-AES destination register +func (o *XTS_AES_Type) SetDESTINATION(value uint32) { + volatile.StoreUint32(&o.DESTINATION.Reg, volatile.LoadUint32(&o.DESTINATION.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetDESTINATION() uint32 { + return volatile.LoadUint32(&o.DESTINATION.Reg) & 0x1 +} + +// XTS_AES.PHYSICAL_ADDRESS: physical address +func (o *XTS_AES_Type) SetPHYSICAL_ADDRESS(value uint32) { + volatile.StoreUint32(&o.PHYSICAL_ADDRESS.Reg, volatile.LoadUint32(&o.PHYSICAL_ADDRESS.Reg)&^(0x3fffffff)|value) +} +func (o *XTS_AES_Type) GetPHYSICAL_ADDRESS() uint32 { + return volatile.LoadUint32(&o.PHYSICAL_ADDRESS.Reg) & 0x3fffffff +} + +// XTS_AES.TRIGGER: XTS-AES trigger register +func (o *XTS_AES_Type) SetTRIGGER(value uint32) { + volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetTRIGGER() uint32 { + return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1 +} + +// XTS_AES.RELEASE: XTS-AES release control register +func (o *XTS_AES_Type) SetRELEASE(value uint32) { + volatile.StoreUint32(&o.RELEASE.Reg, volatile.LoadUint32(&o.RELEASE.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetRELEASE() uint32 { + return volatile.LoadUint32(&o.RELEASE.Reg) & 0x1 +} + +// XTS_AES.DESTROY: XTS-AES destroy control register +func (o *XTS_AES_Type) SetDESTROY(value uint32) { + volatile.StoreUint32(&o.DESTROY.Reg, volatile.LoadUint32(&o.DESTROY.Reg)&^(0x1)|value) +} +func (o *XTS_AES_Type) GetDESTROY() uint32 { + return volatile.LoadUint32(&o.DESTROY.Reg) & 0x1 +} + +// XTS_AES.STATE: XTS-AES status register +func (o *XTS_AES_Type) SetSTATE(value uint32) { + volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value) +} +func (o *XTS_AES_Type) GetSTATE() uint32 { + return volatile.LoadUint32(&o.STATE.Reg) & 0x3 +} + +// XTS_AES.DATE: XTS-AES version control register +func (o *XTS_AES_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value) +} +func (o *XTS_AES_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff +} + +// Constants for AES: AES (Advanced Encryption Standard) Accelerator +const ( + // KEY_0: AES key register %s + // Position of KEY field. + AES_KEY_KEY_Pos = 0x0 + // Bit mask of KEY field. + AES_KEY_KEY_Msk = 0xffffffff + + // TEXT_IN_0: Source data register %s + // Position of TEXT_IN field. + AES_TEXT_IN_TEXT_IN_Pos = 0x0 + // Bit mask of TEXT_IN field. + AES_TEXT_IN_TEXT_IN_Msk = 0xffffffff + + // TEXT_OUT_0: Result data register %s + // Position of TEXT_OUT field. + AES_TEXT_OUT_TEXT_OUT_Pos = 0x0 + // Bit mask of TEXT_OUT field. + AES_TEXT_OUT_TEXT_OUT_Msk = 0xffffffff + + // MODE: AES Mode register + // Position of MODE field. + AES_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + AES_MODE_MODE_Msk = 0x7 + + // TRIGGER: AES trigger register + // Position of TRIGGER field. + AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + AES_TRIGGER_TRIGGER = 0x1 + + // STATE: AES state register + // Position of STATE field. + AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + AES_STATE_STATE_Msk = 0x3 + + // DMA_ENABLE: AES accelerator working mode register + // Position of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Pos = 0x0 + // Bit mask of DMA_ENABLE field. + AES_DMA_ENABLE_DMA_ENABLE_Msk = 0x1 + // Bit DMA_ENABLE. + AES_DMA_ENABLE_DMA_ENABLE = 0x1 + + // BLOCK_MODE: AES cipher block mode register + // Position of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Pos = 0x0 + // Bit mask of BLOCK_MODE field. + AES_BLOCK_MODE_BLOCK_MODE_Msk = 0x7 + + // BLOCK_NUM: AES block number register + // Position of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Pos = 0x0 + // Bit mask of BLOCK_NUM field. + AES_BLOCK_NUM_BLOCK_NUM_Msk = 0xffffffff + + // INC_SEL: Standard incrementing function configure register + // Position of INC_SEL field. + AES_INC_SEL_INC_SEL_Pos = 0x0 + // Bit mask of INC_SEL field. + AES_INC_SEL_INC_SEL_Msk = 0x1 + // Bit INC_SEL. + AES_INC_SEL_INC_SEL = 0x1 + + // AAD_BLOCK_NUM: Additional Authential Data block number register + // Position of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Pos = 0x0 + // Bit mask of AAD_BLOCK_NUM field. + AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Msk = 0xffffffff + + // REMAINDER_BIT_NUM: AES remainder bit number register + // Position of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Pos = 0x0 + // Bit mask of REMAINDER_BIT_NUM field. + AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Msk = 0x7f + + // CONTINUE: AES continue register + // Position of CONTINUE field. + AES_CONTINUE_CONTINUE_Pos = 0x0 + // Bit mask of CONTINUE field. + AES_CONTINUE_CONTINUE_Msk = 0x1 + // Bit CONTINUE. + AES_CONTINUE_CONTINUE = 0x1 + + // INT_CLR: AES Interrupt clear register + // Position of INT_CLEAR field. + AES_INT_CLR_INT_CLEAR_Pos = 0x0 + // Bit mask of INT_CLEAR field. + AES_INT_CLR_INT_CLEAR_Msk = 0x1 + // Bit INT_CLEAR. + AES_INT_CLR_INT_CLEAR = 0x1 + + // INT_ENA: DMA-AES Interrupt enable register + // Position of INT_ENA field. + AES_INT_ENA_INT_ENA_Pos = 0x0 + // Bit mask of INT_ENA field. + AES_INT_ENA_INT_ENA_Msk = 0x1 + // Bit INT_ENA. + AES_INT_ENA_INT_ENA = 0x1 + + // DATE: AES version control register + // Position of DATE field. + AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + AES_DATE_DATE_Msk = 0x3fffffff + + // DMA_EXIT: AES-DMA exit config + // Position of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Pos = 0x0 + // Bit mask of DMA_EXIT field. + AES_DMA_EXIT_DMA_EXIT_Msk = 0x1 + // Bit DMA_EXIT. + AES_DMA_EXIT_DMA_EXIT = 0x1 +) + +// Constants for APB_CTRL: APB (Advanced Peripheral Bus) Controller +const ( + // SYSCLK_CONF: ******* Description *********** + // Position of PRE_DIV_CNT field. + APB_CTRL_SYSCLK_CONF_PRE_DIV_CNT_Pos = 0x0 + // Bit mask of PRE_DIV_CNT field. + APB_CTRL_SYSCLK_CONF_PRE_DIV_CNT_Msk = 0x3ff + // Position of CLK_320M_EN field. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN_Pos = 0xa + // Bit mask of CLK_320M_EN field. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN_Msk = 0x400 + // Bit CLK_320M_EN. + APB_CTRL_SYSCLK_CONF_CLK_320M_EN = 0x400 + // Position of CLK_EN field. + APB_CTRL_SYSCLK_CONF_CLK_EN_Pos = 0xb + // Bit mask of CLK_EN field. + APB_CTRL_SYSCLK_CONF_CLK_EN_Msk = 0x800 + // Bit CLK_EN. + APB_CTRL_SYSCLK_CONF_CLK_EN = 0x800 + // Position of RST_TICK_CNT field. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT_Pos = 0xc + // Bit mask of RST_TICK_CNT field. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT_Msk = 0x1000 + // Bit RST_TICK_CNT. + APB_CTRL_SYSCLK_CONF_RST_TICK_CNT = 0x1000 + + // TICK_CONF: ******* Description *********** + // Position of XTAL_TICK_NUM field. + APB_CTRL_TICK_CONF_XTAL_TICK_NUM_Pos = 0x0 + // Bit mask of XTAL_TICK_NUM field. + APB_CTRL_TICK_CONF_XTAL_TICK_NUM_Msk = 0xff + // Position of CK8M_TICK_NUM field. + APB_CTRL_TICK_CONF_CK8M_TICK_NUM_Pos = 0x8 + // Bit mask of CK8M_TICK_NUM field. + APB_CTRL_TICK_CONF_CK8M_TICK_NUM_Msk = 0xff00 + // Position of TICK_ENABLE field. + APB_CTRL_TICK_CONF_TICK_ENABLE_Pos = 0x10 + // Bit mask of TICK_ENABLE field. + APB_CTRL_TICK_CONF_TICK_ENABLE_Msk = 0x10000 + // Bit TICK_ENABLE. + APB_CTRL_TICK_CONF_TICK_ENABLE = 0x10000 + + // CLK_OUT_EN: ******* Description *********** + // Position of CLK20_OEN field. + APB_CTRL_CLK_OUT_EN_CLK20_OEN_Pos = 0x0 + // Bit mask of CLK20_OEN field. + APB_CTRL_CLK_OUT_EN_CLK20_OEN_Msk = 0x1 + // Bit CLK20_OEN. + APB_CTRL_CLK_OUT_EN_CLK20_OEN = 0x1 + // Position of CLK22_OEN field. + APB_CTRL_CLK_OUT_EN_CLK22_OEN_Pos = 0x1 + // Bit mask of CLK22_OEN field. + APB_CTRL_CLK_OUT_EN_CLK22_OEN_Msk = 0x2 + // Bit CLK22_OEN. + APB_CTRL_CLK_OUT_EN_CLK22_OEN = 0x2 + // Position of CLK44_OEN field. + APB_CTRL_CLK_OUT_EN_CLK44_OEN_Pos = 0x2 + // Bit mask of CLK44_OEN field. + APB_CTRL_CLK_OUT_EN_CLK44_OEN_Msk = 0x4 + // Bit CLK44_OEN. + APB_CTRL_CLK_OUT_EN_CLK44_OEN = 0x4 + // Position of CLK_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_BB_OEN_Pos = 0x3 + // Bit mask of CLK_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_BB_OEN_Msk = 0x8 + // Bit CLK_BB_OEN. + APB_CTRL_CLK_OUT_EN_CLK_BB_OEN = 0x8 + // Position of CLK80_OEN field. + APB_CTRL_CLK_OUT_EN_CLK80_OEN_Pos = 0x4 + // Bit mask of CLK80_OEN field. + APB_CTRL_CLK_OUT_EN_CLK80_OEN_Msk = 0x10 + // Bit CLK80_OEN. + APB_CTRL_CLK_OUT_EN_CLK80_OEN = 0x10 + // Position of CLK160_OEN field. + APB_CTRL_CLK_OUT_EN_CLK160_OEN_Pos = 0x5 + // Bit mask of CLK160_OEN field. + APB_CTRL_CLK_OUT_EN_CLK160_OEN_Msk = 0x20 + // Bit CLK160_OEN. + APB_CTRL_CLK_OUT_EN_CLK160_OEN = 0x20 + // Position of CLK_320M_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_320M_OEN_Pos = 0x6 + // Bit mask of CLK_320M_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_320M_OEN_Msk = 0x40 + // Bit CLK_320M_OEN. + APB_CTRL_CLK_OUT_EN_CLK_320M_OEN = 0x40 + // Position of CLK_ADC_INF_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Pos = 0x7 + // Bit mask of CLK_ADC_INF_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN_Msk = 0x80 + // Bit CLK_ADC_INF_OEN. + APB_CTRL_CLK_OUT_EN_CLK_ADC_INF_OEN = 0x80 + // Position of CLK_DAC_CPU_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN_Pos = 0x8 + // Bit mask of CLK_DAC_CPU_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN_Msk = 0x100 + // Bit CLK_DAC_CPU_OEN. + APB_CTRL_CLK_OUT_EN_CLK_DAC_CPU_OEN = 0x100 + // Position of CLK40X_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK40X_BB_OEN_Pos = 0x9 + // Bit mask of CLK40X_BB_OEN field. + APB_CTRL_CLK_OUT_EN_CLK40X_BB_OEN_Msk = 0x200 + // Bit CLK40X_BB_OEN. + APB_CTRL_CLK_OUT_EN_CLK40X_BB_OEN = 0x200 + // Position of CLK_XTAL_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Pos = 0xa + // Bit mask of CLK_XTAL_OEN field. + APB_CTRL_CLK_OUT_EN_CLK_XTAL_OEN_Msk = 0x400 + // Bit CLK_XTAL_OEN. + APB_CTRL_CLK_OUT_EN_CLK_XTAL_OEN = 0x400 + + // WIFI_BB_CFG: ******* Description *********** + // Position of WIFI_BB_CFG field. + APB_CTRL_WIFI_BB_CFG_WIFI_BB_CFG_Pos = 0x0 + // Bit mask of WIFI_BB_CFG field. + APB_CTRL_WIFI_BB_CFG_WIFI_BB_CFG_Msk = 0xffffffff + + // WIFI_BB_CFG_2: ******* Description *********** + // Position of WIFI_BB_CFG_2 field. + APB_CTRL_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Pos = 0x0 + // Bit mask of WIFI_BB_CFG_2 field. + APB_CTRL_WIFI_BB_CFG_2_WIFI_BB_CFG_2_Msk = 0xffffffff + + // WIFI_CLK_EN: ******* Description *********** + // Position of WIFI_CLK_EN field. + APB_CTRL_WIFI_CLK_EN_WIFI_CLK_EN_Pos = 0x0 + // Bit mask of WIFI_CLK_EN field. + APB_CTRL_WIFI_CLK_EN_WIFI_CLK_EN_Msk = 0xffffffff + + // WIFI_RST_EN: ******* Description *********** + // Position of WIFI_RST field. + APB_CTRL_WIFI_RST_EN_WIFI_RST_Pos = 0x0 + // Bit mask of WIFI_RST field. + APB_CTRL_WIFI_RST_EN_WIFI_RST_Msk = 0xffffffff + + // HOST_INF_SEL: ******* Description *********** + // Position of PERI_IO_SWAP field. + APB_CTRL_HOST_INF_SEL_PERI_IO_SWAP_Pos = 0x0 + // Bit mask of PERI_IO_SWAP field. + APB_CTRL_HOST_INF_SEL_PERI_IO_SWAP_Msk = 0xff + + // EXT_MEM_PMS_LOCK: ******* Description *********** + // Position of EXT_MEM_PMS_LOCK field. + APB_CTRL_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK_Pos = 0x0 + // Bit mask of EXT_MEM_PMS_LOCK field. + APB_CTRL_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK_Msk = 0x1 + // Bit EXT_MEM_PMS_LOCK. + APB_CTRL_EXT_MEM_PMS_LOCK_EXT_MEM_PMS_LOCK = 0x1 + + // EXT_MEM_WRITEBACK_BYPASS: ******* Description *********** + // Position of WRITEBACK_BYPASS field. + APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_WRITEBACK_BYPASS_Pos = 0x0 + // Bit mask of WRITEBACK_BYPASS field. + APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_WRITEBACK_BYPASS_Msk = 0x1 + // Bit WRITEBACK_BYPASS. + APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_WRITEBACK_BYPASS = 0x1 + + // FLASH_ACE0_ATTR: ******* Description *********** + // Position of FLASH_ACE0_ATTR field. + APB_CTRL_FLASH_ACE0_ATTR_FLASH_ACE0_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE0_ATTR field. + APB_CTRL_FLASH_ACE0_ATTR_FLASH_ACE0_ATTR_Msk = 0x1ff + + // FLASH_ACE1_ATTR: ******* Description *********** + // Position of FLASH_ACE1_ATTR field. + APB_CTRL_FLASH_ACE1_ATTR_FLASH_ACE1_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE1_ATTR field. + APB_CTRL_FLASH_ACE1_ATTR_FLASH_ACE1_ATTR_Msk = 0x1ff + + // FLASH_ACE2_ATTR: ******* Description *********** + // Position of FLASH_ACE2_ATTR field. + APB_CTRL_FLASH_ACE2_ATTR_FLASH_ACE2_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE2_ATTR field. + APB_CTRL_FLASH_ACE2_ATTR_FLASH_ACE2_ATTR_Msk = 0x1ff + + // FLASH_ACE3_ATTR: ******* Description *********** + // Position of FLASH_ACE3_ATTR field. + APB_CTRL_FLASH_ACE3_ATTR_FLASH_ACE3_ATTR_Pos = 0x0 + // Bit mask of FLASH_ACE3_ATTR field. + APB_CTRL_FLASH_ACE3_ATTR_FLASH_ACE3_ATTR_Msk = 0x1ff + + // FLASH_ACE0_ADDR: ******* Description *********** + // Position of S field. + APB_CTRL_FLASH_ACE0_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE0_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE1_ADDR: ******* Description *********** + // Position of S field. + APB_CTRL_FLASH_ACE1_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE1_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE2_ADDR: ******* Description *********** + // Position of S field. + APB_CTRL_FLASH_ACE2_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE2_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE3_ADDR: ******* Description *********** + // Position of S field. + APB_CTRL_FLASH_ACE3_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_FLASH_ACE3_ADDR_S_Msk = 0xffffffff + + // FLASH_ACE0_SIZE: ******* Description *********** + // Position of FLASH_ACE0_SIZE field. + APB_CTRL_FLASH_ACE0_SIZE_FLASH_ACE0_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE0_SIZE field. + APB_CTRL_FLASH_ACE0_SIZE_FLASH_ACE0_SIZE_Msk = 0xffff + + // FLASH_ACE1_SIZE: ******* Description *********** + // Position of FLASH_ACE1_SIZE field. + APB_CTRL_FLASH_ACE1_SIZE_FLASH_ACE1_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE1_SIZE field. + APB_CTRL_FLASH_ACE1_SIZE_FLASH_ACE1_SIZE_Msk = 0xffff + + // FLASH_ACE2_SIZE: ******* Description *********** + // Position of FLASH_ACE2_SIZE field. + APB_CTRL_FLASH_ACE2_SIZE_FLASH_ACE2_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE2_SIZE field. + APB_CTRL_FLASH_ACE2_SIZE_FLASH_ACE2_SIZE_Msk = 0xffff + + // FLASH_ACE3_SIZE: ******* Description *********** + // Position of FLASH_ACE3_SIZE field. + APB_CTRL_FLASH_ACE3_SIZE_FLASH_ACE3_SIZE_Pos = 0x0 + // Bit mask of FLASH_ACE3_SIZE field. + APB_CTRL_FLASH_ACE3_SIZE_FLASH_ACE3_SIZE_Msk = 0xffff + + // SRAM_ACE0_ATTR: ******* Description *********** + // Position of SRAM_ACE0_ATTR field. + APB_CTRL_SRAM_ACE0_ATTR_SRAM_ACE0_ATTR_Pos = 0x0 + // Bit mask of SRAM_ACE0_ATTR field. + APB_CTRL_SRAM_ACE0_ATTR_SRAM_ACE0_ATTR_Msk = 0x1ff + + // SRAM_ACE1_ATTR: ******* Description *********** + // Position of SRAM_ACE1_ATTR field. + APB_CTRL_SRAM_ACE1_ATTR_SRAM_ACE1_ATTR_Pos = 0x0 + // Bit mask of SRAM_ACE1_ATTR field. + APB_CTRL_SRAM_ACE1_ATTR_SRAM_ACE1_ATTR_Msk = 0x1ff + + // SRAM_ACE2_ATTR: ******* Description *********** + // Position of SRAM_ACE2_ATTR field. + APB_CTRL_SRAM_ACE2_ATTR_SRAM_ACE2_ATTR_Pos = 0x0 + // Bit mask of SRAM_ACE2_ATTR field. + APB_CTRL_SRAM_ACE2_ATTR_SRAM_ACE2_ATTR_Msk = 0x1ff + + // SRAM_ACE3_ATTR: ******* Description *********** + // Position of SRAM_ACE3_ATTR field. + APB_CTRL_SRAM_ACE3_ATTR_SRAM_ACE3_ATTR_Pos = 0x0 + // Bit mask of SRAM_ACE3_ATTR field. + APB_CTRL_SRAM_ACE3_ATTR_SRAM_ACE3_ATTR_Msk = 0x1ff + + // SRAM_ACE0_ADDR: ******* Description *********** + // Position of S field. + APB_CTRL_SRAM_ACE0_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_SRAM_ACE0_ADDR_S_Msk = 0xffffffff + + // SRAM_ACE1_ADDR: ******* Description *********** + // Position of S field. + APB_CTRL_SRAM_ACE1_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_SRAM_ACE1_ADDR_S_Msk = 0xffffffff + + // SRAM_ACE2_ADDR: ******* Description *********** + // Position of S field. + APB_CTRL_SRAM_ACE2_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_SRAM_ACE2_ADDR_S_Msk = 0xffffffff + + // SRAM_ACE3_ADDR: ******* Description *********** + // Position of S field. + APB_CTRL_SRAM_ACE3_ADDR_S_Pos = 0x0 + // Bit mask of S field. + APB_CTRL_SRAM_ACE3_ADDR_S_Msk = 0xffffffff + + // SRAM_ACE0_SIZE: ******* Description *********** + // Position of SRAM_ACE0_SIZE field. + APB_CTRL_SRAM_ACE0_SIZE_SRAM_ACE0_SIZE_Pos = 0x0 + // Bit mask of SRAM_ACE0_SIZE field. + APB_CTRL_SRAM_ACE0_SIZE_SRAM_ACE0_SIZE_Msk = 0xffff + + // SRAM_ACE1_SIZE: ******* Description *********** + // Position of SRAM_ACE1_SIZE field. + APB_CTRL_SRAM_ACE1_SIZE_SRAM_ACE1_SIZE_Pos = 0x0 + // Bit mask of SRAM_ACE1_SIZE field. + APB_CTRL_SRAM_ACE1_SIZE_SRAM_ACE1_SIZE_Msk = 0xffff + + // SRAM_ACE2_SIZE: ******* Description *********** + // Position of SRAM_ACE2_SIZE field. + APB_CTRL_SRAM_ACE2_SIZE_SRAM_ACE2_SIZE_Pos = 0x0 + // Bit mask of SRAM_ACE2_SIZE field. + APB_CTRL_SRAM_ACE2_SIZE_SRAM_ACE2_SIZE_Msk = 0xffff + + // SRAM_ACE3_SIZE: ******* Description *********** + // Position of SRAM_ACE3_SIZE field. + APB_CTRL_SRAM_ACE3_SIZE_SRAM_ACE3_SIZE_Pos = 0x0 + // Bit mask of SRAM_ACE3_SIZE field. + APB_CTRL_SRAM_ACE3_SIZE_SRAM_ACE3_SIZE_Msk = 0xffff + + // SPI_MEM_PMS_CTRL: ******* Description *********** + // Position of SPI_MEM_REJECT_INT field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_INT field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT_Msk = 0x1 + // Bit SPI_MEM_REJECT_INT. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_INT = 0x1 + // Position of SPI_MEM_REJECT_CLR field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR_Pos = 0x1 + // Bit mask of SPI_MEM_REJECT_CLR field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR_Msk = 0x2 + // Bit SPI_MEM_REJECT_CLR. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CLR = 0x2 + // Position of SPI_MEM_REJECT_CDE field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE_Pos = 0x2 + // Bit mask of SPI_MEM_REJECT_CDE field. + APB_CTRL_SPI_MEM_PMS_CTRL_SPI_MEM_REJECT_CDE_Msk = 0x7c + + // SPI_MEM_REJECT_ADDR: ******* Description *********** + // Position of SPI_MEM_REJECT_ADDR field. + APB_CTRL_SPI_MEM_REJECT_ADDR_SPI_MEM_REJECT_ADDR_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_ADDR field. + APB_CTRL_SPI_MEM_REJECT_ADDR_SPI_MEM_REJECT_ADDR_Msk = 0xffffffff + + // SDIO_CTRL: ******* Description *********** + // Position of SDIO_WIN_ACCESS_EN field. + APB_CTRL_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Pos = 0x0 + // Bit mask of SDIO_WIN_ACCESS_EN field. + APB_CTRL_SDIO_CTRL_SDIO_WIN_ACCESS_EN_Msk = 0x1 + // Bit SDIO_WIN_ACCESS_EN. + APB_CTRL_SDIO_CTRL_SDIO_WIN_ACCESS_EN = 0x1 + + // REDCY_SIG0: ******* Description *********** + // Position of REDCY_SIG0 field. + APB_CTRL_REDCY_SIG0_REDCY_SIG0_Pos = 0x0 + // Bit mask of REDCY_SIG0 field. + APB_CTRL_REDCY_SIG0_REDCY_SIG0_Msk = 0x7fffffff + // Position of REDCY_ANDOR field. + APB_CTRL_REDCY_SIG0_REDCY_ANDOR_Pos = 0x1f + // Bit mask of REDCY_ANDOR field. + APB_CTRL_REDCY_SIG0_REDCY_ANDOR_Msk = 0x80000000 + // Bit REDCY_ANDOR. + APB_CTRL_REDCY_SIG0_REDCY_ANDOR = 0x80000000 + + // REDCY_SIG1: ******* Description *********** + // Position of REDCY_SIG1 field. + APB_CTRL_REDCY_SIG1_REDCY_SIG1_Pos = 0x0 + // Bit mask of REDCY_SIG1 field. + APB_CTRL_REDCY_SIG1_REDCY_SIG1_Msk = 0x7fffffff + // Position of REDCY_NANDOR field. + APB_CTRL_REDCY_SIG1_REDCY_NANDOR_Pos = 0x1f + // Bit mask of REDCY_NANDOR field. + APB_CTRL_REDCY_SIG1_REDCY_NANDOR_Msk = 0x80000000 + // Bit REDCY_NANDOR. + APB_CTRL_REDCY_SIG1_REDCY_NANDOR = 0x80000000 + + // FRONT_END_MEM_PD: ******* Description *********** + // Position of AGC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Pos = 0x0 + // Bit mask of AGC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU_Msk = 0x1 + // Bit AGC_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PU = 0x1 + // Position of AGC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of AGC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD_Msk = 0x2 + // Bit AGC_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_AGC_MEM_FORCE_PD = 0x2 + // Position of PBUS_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of PBUS_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU_Msk = 0x4 + // Bit PBUS_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PU = 0x4 + // Position of PBUS_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of PBUS_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD_Msk = 0x8 + // Bit PBUS_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_PBUS_MEM_FORCE_PD = 0x8 + // Position of DC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of DC_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PU_Msk = 0x10 + // Bit DC_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PU = 0x10 + // Position of DC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PD_Pos = 0x5 + // Bit mask of DC_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PD_Msk = 0x20 + // Bit DC_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_DC_MEM_FORCE_PD = 0x20 + // Position of FREQ_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PU_Pos = 0x6 + // Bit mask of FREQ_MEM_FORCE_PU field. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PU_Msk = 0x40 + // Bit FREQ_MEM_FORCE_PU. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PU = 0x40 + // Position of FREQ_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PD_Pos = 0x7 + // Bit mask of FREQ_MEM_FORCE_PD field. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PD_Msk = 0x80 + // Bit FREQ_MEM_FORCE_PD. + APB_CTRL_FRONT_END_MEM_PD_FREQ_MEM_FORCE_PD = 0x80 + + // SPI_MEM_ECC_CTRL: ******* Description *********** + // Position of FLASH_PAGE_SIZE field. + APB_CTRL_SPI_MEM_ECC_CTRL_FLASH_PAGE_SIZE_Pos = 0x12 + // Bit mask of FLASH_PAGE_SIZE field. + APB_CTRL_SPI_MEM_ECC_CTRL_FLASH_PAGE_SIZE_Msk = 0xc0000 + // Position of SRAM_PAGE_SIZE field. + APB_CTRL_SPI_MEM_ECC_CTRL_SRAM_PAGE_SIZE_Pos = 0x14 + // Bit mask of SRAM_PAGE_SIZE field. + APB_CTRL_SPI_MEM_ECC_CTRL_SRAM_PAGE_SIZE_Msk = 0x300000 + + // CLKGATE_FORCE_ON: ******* Description *********** + // Position of ROM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON_Pos = 0x0 + // Bit mask of ROM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_ROM_CLKGATE_FORCE_ON_Msk = 0x7 + // Position of SRAM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON_Pos = 0x3 + // Bit mask of SRAM_CLKGATE_FORCE_ON field. + APB_CTRL_CLKGATE_FORCE_ON_SRAM_CLKGATE_FORCE_ON_Msk = 0x3ff8 + + // MEM_POWER_DOWN: ******* Description *********** + // Position of ROM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_ROM_POWER_DOWN_Pos = 0x0 + // Bit mask of ROM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_ROM_POWER_DOWN_Msk = 0x7 + // Position of SRAM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_SRAM_POWER_DOWN_Pos = 0x3 + // Bit mask of SRAM_POWER_DOWN field. + APB_CTRL_MEM_POWER_DOWN_SRAM_POWER_DOWN_Msk = 0x3ff8 + + // MEM_POWER_UP: ******* Description *********** + // Position of ROM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_ROM_POWER_UP_Pos = 0x0 + // Bit mask of ROM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_ROM_POWER_UP_Msk = 0x7 + // Position of SRAM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_SRAM_POWER_UP_Pos = 0x3 + // Bit mask of SRAM_POWER_UP field. + APB_CTRL_MEM_POWER_UP_SRAM_POWER_UP_Msk = 0x3ff8 + + // RETENTION_CTRL: ******* Description *********** + // Position of RETENTION_CPU_LINK_ADDR field. + APB_CTRL_RETENTION_CTRL_RETENTION_CPU_LINK_ADDR_Pos = 0x0 + // Bit mask of RETENTION_CPU_LINK_ADDR field. + APB_CTRL_RETENTION_CTRL_RETENTION_CPU_LINK_ADDR_Msk = 0x7ffffff + // Position of NOBYPASS_CPU_ISO_RST field. + APB_CTRL_RETENTION_CTRL_NOBYPASS_CPU_ISO_RST_Pos = 0x1b + // Bit mask of NOBYPASS_CPU_ISO_RST field. + APB_CTRL_RETENTION_CTRL_NOBYPASS_CPU_ISO_RST_Msk = 0x8000000 + // Bit NOBYPASS_CPU_ISO_RST. + APB_CTRL_RETENTION_CTRL_NOBYPASS_CPU_ISO_RST = 0x8000000 + + // RETENTION_CTRL1: ******* Description *********** + // Position of RETENTION_TAG_LINK_ADDR field. + APB_CTRL_RETENTION_CTRL1_RETENTION_TAG_LINK_ADDR_Pos = 0x0 + // Bit mask of RETENTION_TAG_LINK_ADDR field. + APB_CTRL_RETENTION_CTRL1_RETENTION_TAG_LINK_ADDR_Msk = 0x7ffffff + + // RETENTION_CTRL2: ******* Description *********** + // Position of RET_ICACHE_SIZE field. + APB_CTRL_RETENTION_CTRL2_RET_ICACHE_SIZE_Pos = 0x4 + // Bit mask of RET_ICACHE_SIZE field. + APB_CTRL_RETENTION_CTRL2_RET_ICACHE_SIZE_Msk = 0xff0 + // Position of RET_ICACHE_VLD_SIZE field. + APB_CTRL_RETENTION_CTRL2_RET_ICACHE_VLD_SIZE_Pos = 0xd + // Bit mask of RET_ICACHE_VLD_SIZE field. + APB_CTRL_RETENTION_CTRL2_RET_ICACHE_VLD_SIZE_Msk = 0x1fe000 + // Position of RET_ICACHE_START_POINT field. + APB_CTRL_RETENTION_CTRL2_RET_ICACHE_START_POINT_Pos = 0x16 + // Bit mask of RET_ICACHE_START_POINT field. + APB_CTRL_RETENTION_CTRL2_RET_ICACHE_START_POINT_Msk = 0x3fc00000 + // Position of RET_ICACHE_ENABLE field. + APB_CTRL_RETENTION_CTRL2_RET_ICACHE_ENABLE_Pos = 0x1f + // Bit mask of RET_ICACHE_ENABLE field. + APB_CTRL_RETENTION_CTRL2_RET_ICACHE_ENABLE_Msk = 0x80000000 + // Bit RET_ICACHE_ENABLE. + APB_CTRL_RETENTION_CTRL2_RET_ICACHE_ENABLE = 0x80000000 + + // RETENTION_CTRL3: ******* Description *********** + // Position of RET_DCACHE_SIZE field. + APB_CTRL_RETENTION_CTRL3_RET_DCACHE_SIZE_Pos = 0x4 + // Bit mask of RET_DCACHE_SIZE field. + APB_CTRL_RETENTION_CTRL3_RET_DCACHE_SIZE_Msk = 0x1ff0 + // Position of RET_DCACHE_VLD_SIZE field. + APB_CTRL_RETENTION_CTRL3_RET_DCACHE_VLD_SIZE_Pos = 0xd + // Bit mask of RET_DCACHE_VLD_SIZE field. + APB_CTRL_RETENTION_CTRL3_RET_DCACHE_VLD_SIZE_Msk = 0x3fe000 + // Position of RET_DCACHE_START_POINT field. + APB_CTRL_RETENTION_CTRL3_RET_DCACHE_START_POINT_Pos = 0x16 + // Bit mask of RET_DCACHE_START_POINT field. + APB_CTRL_RETENTION_CTRL3_RET_DCACHE_START_POINT_Msk = 0x7fc00000 + // Position of RET_DCACHE_ENABLE field. + APB_CTRL_RETENTION_CTRL3_RET_DCACHE_ENABLE_Pos = 0x1f + // Bit mask of RET_DCACHE_ENABLE field. + APB_CTRL_RETENTION_CTRL3_RET_DCACHE_ENABLE_Msk = 0x80000000 + // Bit RET_DCACHE_ENABLE. + APB_CTRL_RETENTION_CTRL3_RET_DCACHE_ENABLE = 0x80000000 + + // RETENTION_CTRL4: ******* Description *********** + // Position of RETENTION_INV_CFG field. + APB_CTRL_RETENTION_CTRL4_RETENTION_INV_CFG_Pos = 0x0 + // Bit mask of RETENTION_INV_CFG field. + APB_CTRL_RETENTION_CTRL4_RETENTION_INV_CFG_Msk = 0xffffffff + + // RETENTION_CTRL5: ******* Description *********** + // Position of RETENTION_DISABLE field. + APB_CTRL_RETENTION_CTRL5_RETENTION_DISABLE_Pos = 0x0 + // Bit mask of RETENTION_DISABLE field. + APB_CTRL_RETENTION_CTRL5_RETENTION_DISABLE_Msk = 0x1 + // Bit RETENTION_DISABLE. + APB_CTRL_RETENTION_CTRL5_RETENTION_DISABLE = 0x1 + + // DATE: ******* Description *********** + // Position of DATE field. + APB_CTRL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + APB_CTRL_DATE_DATE_Msk = 0xffffffff +) + +// Constants for APB_SARADC: SAR (Successive Approximation Register) Analog-to-Digital Converter +const ( + // CTRL: configure apb saradc controller + // Position of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Pos = 0x0 + // Bit mask of SARADC_START_FORCE field. + APB_SARADC_CTRL_SARADC_START_FORCE_Msk = 0x1 + // Bit SARADC_START_FORCE. + APB_SARADC_CTRL_SARADC_START_FORCE = 0x1 + // Position of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Pos = 0x1 + // Bit mask of SARADC_START field. + APB_SARADC_CTRL_SARADC_START_Msk = 0x2 + // Bit SARADC_START. + APB_SARADC_CTRL_SARADC_START = 0x2 + // Position of SARADC_WORK_MODE field. + APB_SARADC_CTRL_SARADC_WORK_MODE_Pos = 0x3 + // Bit mask of SARADC_WORK_MODE field. + APB_SARADC_CTRL_SARADC_WORK_MODE_Msk = 0x18 + // Position of SARADC_SAR_SEL field. + APB_SARADC_CTRL_SARADC_SAR_SEL_Pos = 0x5 + // Bit mask of SARADC_SAR_SEL field. + APB_SARADC_CTRL_SARADC_SAR_SEL_Msk = 0x20 + // Bit SARADC_SAR_SEL. + APB_SARADC_CTRL_SARADC_SAR_SEL = 0x20 + // Position of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Pos = 0x6 + // Bit mask of SARADC_SAR_CLK_GATED field. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED_Msk = 0x40 + // Bit SARADC_SAR_CLK_GATED. + APB_SARADC_CTRL_SARADC_SAR_CLK_GATED = 0x40 + // Position of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Pos = 0x7 + // Bit mask of SARADC_SAR_CLK_DIV field. + APB_SARADC_CTRL_SARADC_SAR_CLK_DIV_Msk = 0x7f80 + // Position of SARADC_SAR1_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR1_PATT_LEN_Pos = 0xf + // Bit mask of SARADC_SAR1_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR1_PATT_LEN_Msk = 0x78000 + // Position of SARADC_SAR2_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR2_PATT_LEN_Pos = 0x13 + // Bit mask of SARADC_SAR2_PATT_LEN field. + APB_SARADC_CTRL_SARADC_SAR2_PATT_LEN_Msk = 0x780000 + // Position of SARADC_SAR1_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR1_PATT_P_CLEAR_Pos = 0x17 + // Bit mask of SARADC_SAR1_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR1_PATT_P_CLEAR_Msk = 0x800000 + // Bit SARADC_SAR1_PATT_P_CLEAR. + APB_SARADC_CTRL_SARADC_SAR1_PATT_P_CLEAR = 0x800000 + // Position of SARADC_SAR2_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR2_PATT_P_CLEAR_Pos = 0x18 + // Bit mask of SARADC_SAR2_PATT_P_CLEAR field. + APB_SARADC_CTRL_SARADC_SAR2_PATT_P_CLEAR_Msk = 0x1000000 + // Bit SARADC_SAR2_PATT_P_CLEAR. + APB_SARADC_CTRL_SARADC_SAR2_PATT_P_CLEAR = 0x1000000 + // Position of SARADC_DATA_SAR_SEL field. + APB_SARADC_CTRL_SARADC_DATA_SAR_SEL_Pos = 0x19 + // Bit mask of SARADC_DATA_SAR_SEL field. + APB_SARADC_CTRL_SARADC_DATA_SAR_SEL_Msk = 0x2000000 + // Bit SARADC_DATA_SAR_SEL. + APB_SARADC_CTRL_SARADC_DATA_SAR_SEL = 0x2000000 + // Position of SARADC_DATA_TO_I2S field. + APB_SARADC_CTRL_SARADC_DATA_TO_I2S_Pos = 0x1a + // Bit mask of SARADC_DATA_TO_I2S field. + APB_SARADC_CTRL_SARADC_DATA_TO_I2S_Msk = 0x4000000 + // Bit SARADC_DATA_TO_I2S. + APB_SARADC_CTRL_SARADC_DATA_TO_I2S = 0x4000000 + // Position of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Pos = 0x1b + // Bit mask of SARADC_XPD_SAR_FORCE field. + APB_SARADC_CTRL_SARADC_XPD_SAR_FORCE_Msk = 0x18000000 + // Position of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Pos = 0x1e + // Bit mask of SARADC_WAIT_ARB_CYCLE field. + APB_SARADC_CTRL_SARADC_WAIT_ARB_CYCLE_Msk = 0xc0000000 + + // CTRL2: configure apb saradc controller + // Position of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Pos = 0x0 + // Bit mask of SARADC_MEAS_NUM_LIMIT field. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT_Msk = 0x1 + // Bit SARADC_MEAS_NUM_LIMIT. + APB_SARADC_CTRL2_SARADC_MEAS_NUM_LIMIT = 0x1 + // Position of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Pos = 0x1 + // Bit mask of SARADC_MAX_MEAS_NUM field. + APB_SARADC_CTRL2_SARADC_MAX_MEAS_NUM_Msk = 0x1fe + // Position of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Pos = 0x9 + // Bit mask of SARADC_SAR1_INV field. + APB_SARADC_CTRL2_SARADC_SAR1_INV_Msk = 0x200 + // Bit SARADC_SAR1_INV. + APB_SARADC_CTRL2_SARADC_SAR1_INV = 0x200 + // Position of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Pos = 0xa + // Bit mask of SARADC_SAR2_INV field. + APB_SARADC_CTRL2_SARADC_SAR2_INV_Msk = 0x400 + // Bit SARADC_SAR2_INV. + APB_SARADC_CTRL2_SARADC_SAR2_INV = 0x400 + // Position of SARADC_TIMER_SEL field. + APB_SARADC_CTRL2_SARADC_TIMER_SEL_Pos = 0xb + // Bit mask of SARADC_TIMER_SEL field. + APB_SARADC_CTRL2_SARADC_TIMER_SEL_Msk = 0x800 + // Bit SARADC_TIMER_SEL. + APB_SARADC_CTRL2_SARADC_TIMER_SEL = 0x800 + // Position of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Pos = 0xc + // Bit mask of SARADC_TIMER_TARGET field. + APB_SARADC_CTRL2_SARADC_TIMER_TARGET_Msk = 0xfff000 + // Position of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Pos = 0x18 + // Bit mask of SARADC_TIMER_EN field. + APB_SARADC_CTRL2_SARADC_TIMER_EN_Msk = 0x1000000 + // Bit SARADC_TIMER_EN. + APB_SARADC_CTRL2_SARADC_TIMER_EN = 0x1000000 + + // FILTER_CTRL1: configure saradc filter + // Position of FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_FILTER_FACTOR1_Pos = 0x1a + // Bit mask of FILTER_FACTOR1 field. + APB_SARADC_FILTER_CTRL1_FILTER_FACTOR1_Msk = 0x1c000000 + // Position of FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_FILTER_FACTOR0_Pos = 0x1d + // Bit mask of FILTER_FACTOR0 field. + APB_SARADC_FILTER_CTRL1_FILTER_FACTOR0_Msk = 0xe0000000 + + // FSM_WAIT: configure apb saradc fsm + // Position of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Pos = 0x0 + // Bit mask of SARADC_XPD_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_XPD_WAIT_Msk = 0xff + // Position of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Pos = 0x8 + // Bit mask of SARADC_RSTB_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_RSTB_WAIT_Msk = 0xff00 + // Position of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Pos = 0x10 + // Bit mask of SARADC_STANDBY_WAIT field. + APB_SARADC_FSM_WAIT_SARADC_STANDBY_WAIT_Msk = 0xff0000 + + // SAR1_STATUS: saradc1 status for debug + // Position of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR1_STATUS field. + APB_SARADC_SAR1_STATUS_SARADC_SAR1_STATUS_Msk = 0xffffffff + + // SAR2_STATUS: saradc2 status for debug + // Position of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Pos = 0x0 + // Bit mask of SARADC_SAR2_STATUS field. + APB_SARADC_SAR2_STATUS_SARADC_SAR2_STATUS_Msk = 0xffffffff + + // SAR1_PATT_TAB1: configure apb saradc pattern table + // Position of SARADC_SAR1_PATT_TAB1 field. + APB_SARADC_SAR1_PATT_TAB1_SARADC_SAR1_PATT_TAB1_Pos = 0x0 + // Bit mask of SARADC_SAR1_PATT_TAB1 field. + APB_SARADC_SAR1_PATT_TAB1_SARADC_SAR1_PATT_TAB1_Msk = 0xffffff + + // SAR1_PATT_TAB2: configure apb saradc pattern table + // Position of SARADC_SAR1_PATT_TAB2 field. + APB_SARADC_SAR1_PATT_TAB2_SARADC_SAR1_PATT_TAB2_Pos = 0x0 + // Bit mask of SARADC_SAR1_PATT_TAB2 field. + APB_SARADC_SAR1_PATT_TAB2_SARADC_SAR1_PATT_TAB2_Msk = 0xffffff + + // SAR1_PATT_TAB3: configure apb saradc pattern table + // Position of SARADC_SAR1_PATT_TAB3 field. + APB_SARADC_SAR1_PATT_TAB3_SARADC_SAR1_PATT_TAB3_Pos = 0x0 + // Bit mask of SARADC_SAR1_PATT_TAB3 field. + APB_SARADC_SAR1_PATT_TAB3_SARADC_SAR1_PATT_TAB3_Msk = 0xffffff + + // SAR1_PATT_TAB4: configure apb saradc pattern table + // Position of SARADC_SAR1_PATT_TAB4 field. + APB_SARADC_SAR1_PATT_TAB4_SARADC_SAR1_PATT_TAB4_Pos = 0x0 + // Bit mask of SARADC_SAR1_PATT_TAB4 field. + APB_SARADC_SAR1_PATT_TAB4_SARADC_SAR1_PATT_TAB4_Msk = 0xffffff + + // SAR2_PATT_TAB1: configure apb saradc pattern table + // Position of SARADC_SAR2_PATT_TAB1 field. + APB_SARADC_SAR2_PATT_TAB1_SARADC_SAR2_PATT_TAB1_Pos = 0x0 + // Bit mask of SARADC_SAR2_PATT_TAB1 field. + APB_SARADC_SAR2_PATT_TAB1_SARADC_SAR2_PATT_TAB1_Msk = 0xffffff + + // SAR2_PATT_TAB2: configure apb saradc pattern table + // Position of SARADC_SAR2_PATT_TAB2 field. + APB_SARADC_SAR2_PATT_TAB2_SARADC_SAR2_PATT_TAB2_Pos = 0x0 + // Bit mask of SARADC_SAR2_PATT_TAB2 field. + APB_SARADC_SAR2_PATT_TAB2_SARADC_SAR2_PATT_TAB2_Msk = 0xffffff + + // SAR2_PATT_TAB3: configure apb saradc pattern table + // Position of SARADC_SAR2_PATT_TAB3 field. + APB_SARADC_SAR2_PATT_TAB3_SARADC_SAR2_PATT_TAB3_Pos = 0x0 + // Bit mask of SARADC_SAR2_PATT_TAB3 field. + APB_SARADC_SAR2_PATT_TAB3_SARADC_SAR2_PATT_TAB3_Msk = 0xffffff + + // SAR2_PATT_TAB4: configure apb saradc pattern table + // Position of SARADC_SAR2_PATT_TAB4 field. + APB_SARADC_SAR2_PATT_TAB4_SARADC_SAR2_PATT_TAB4_Pos = 0x0 + // Bit mask of SARADC_SAR2_PATT_TAB4 field. + APB_SARADC_SAR2_PATT_TAB4_SARADC_SAR2_PATT_TAB4_Msk = 0xffffff + + // ARB_CTRL: configure apb saradc arbit + // Position of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Pos = 0x2 + // Bit mask of ADC_ARB_APB_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE_Msk = 0x4 + // Bit ADC_ARB_APB_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_FORCE = 0x4 + // Position of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Pos = 0x3 + // Bit mask of ADC_ARB_RTC_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE_Msk = 0x8 + // Bit ADC_ARB_RTC_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_FORCE = 0x8 + // Position of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Pos = 0x4 + // Bit mask of ADC_ARB_WIFI_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE_Msk = 0x10 + // Bit ADC_ARB_WIFI_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_FORCE = 0x10 + // Position of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Pos = 0x5 + // Bit mask of ADC_ARB_GRANT_FORCE field. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE_Msk = 0x20 + // Bit ADC_ARB_GRANT_FORCE. + APB_SARADC_ARB_CTRL_ADC_ARB_GRANT_FORCE = 0x20 + // Position of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Pos = 0x6 + // Bit mask of ADC_ARB_APB_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_APB_PRIORITY_Msk = 0xc0 + // Position of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Pos = 0x8 + // Bit mask of ADC_ARB_RTC_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_RTC_PRIORITY_Msk = 0x300 + // Position of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Pos = 0xa + // Bit mask of ADC_ARB_WIFI_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_WIFI_PRIORITY_Msk = 0xc00 + // Position of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Pos = 0xc + // Bit mask of ADC_ARB_FIX_PRIORITY field. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY_Msk = 0x1000 + // Bit ADC_ARB_FIX_PRIORITY. + APB_SARADC_ARB_CTRL_ADC_ARB_FIX_PRIORITY = 0x1000 + + // FILTER_CTRL0: configure apb saradc arbit + // Position of FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_FILTER_CHANNEL1_Pos = 0xe + // Bit mask of FILTER_CHANNEL1 field. + APB_SARADC_FILTER_CTRL0_FILTER_CHANNEL1_Msk = 0x7c000 + // Position of FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_FILTER_CHANNEL0_Pos = 0x13 + // Bit mask of FILTER_CHANNEL0 field. + APB_SARADC_FILTER_CTRL0_FILTER_CHANNEL0_Msk = 0xf80000 + // Position of FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_FILTER_RESET_Pos = 0x1f + // Bit mask of FILTER_RESET field. + APB_SARADC_FILTER_CTRL0_FILTER_RESET_Msk = 0x80000000 + // Bit FILTER_RESET. + APB_SARADC_FILTER_CTRL0_FILTER_RESET = 0x80000000 + + // APB_SARADC1_DATA_STATUS: get apb saradc sample data + // Position of APB_SARADC1_DATA field. + APB_SARADC_APB_SARADC1_DATA_STATUS_APB_SARADC1_DATA_Pos = 0x0 + // Bit mask of APB_SARADC1_DATA field. + APB_SARADC_APB_SARADC1_DATA_STATUS_APB_SARADC1_DATA_Msk = 0x1ffff + + // THRES0_CTRL: configure apb saradc thres monitor + // Position of THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_THRES0_CHANNEL_Pos = 0x0 + // Bit mask of THRES0_CHANNEL field. + APB_SARADC_THRES0_CTRL_THRES0_CHANNEL_Msk = 0x1f + // Position of THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_THRES0_HIGH_Pos = 0x5 + // Bit mask of THRES0_HIGH field. + APB_SARADC_THRES0_CTRL_THRES0_HIGH_Msk = 0x3ffe0 + // Position of THRES0_LOW field. + APB_SARADC_THRES0_CTRL_THRES0_LOW_Pos = 0x12 + // Bit mask of THRES0_LOW field. + APB_SARADC_THRES0_CTRL_THRES0_LOW_Msk = 0x7ffc0000 + + // THRES1_CTRL: configure apb saradc thres monitor + // Position of THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_THRES1_CHANNEL_Pos = 0x0 + // Bit mask of THRES1_CHANNEL field. + APB_SARADC_THRES1_CTRL_THRES1_CHANNEL_Msk = 0x1f + // Position of THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_THRES1_HIGH_Pos = 0x5 + // Bit mask of THRES1_HIGH field. + APB_SARADC_THRES1_CTRL_THRES1_HIGH_Msk = 0x3ffe0 + // Position of THRES1_LOW field. + APB_SARADC_THRES1_CTRL_THRES1_LOW_Pos = 0x12 + // Bit mask of THRES1_LOW field. + APB_SARADC_THRES1_CTRL_THRES1_LOW_Msk = 0x7ffc0000 + + // THRES_CTRL: configure thres monitor enable + // Position of THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_THRES_ALL_EN_Pos = 0x1b + // Bit mask of THRES_ALL_EN field. + APB_SARADC_THRES_CTRL_THRES_ALL_EN_Msk = 0x8000000 + // Bit THRES_ALL_EN. + APB_SARADC_THRES_CTRL_THRES_ALL_EN = 0x8000000 + // Position of THRES3_EN field. + APB_SARADC_THRES_CTRL_THRES3_EN_Pos = 0x1c + // Bit mask of THRES3_EN field. + APB_SARADC_THRES_CTRL_THRES3_EN_Msk = 0x10000000 + // Bit THRES3_EN. + APB_SARADC_THRES_CTRL_THRES3_EN = 0x10000000 + // Position of THRES2_EN field. + APB_SARADC_THRES_CTRL_THRES2_EN_Pos = 0x1d + // Bit mask of THRES2_EN field. + APB_SARADC_THRES_CTRL_THRES2_EN_Msk = 0x20000000 + // Bit THRES2_EN. + APB_SARADC_THRES_CTRL_THRES2_EN = 0x20000000 + // Position of THRES1_EN field. + APB_SARADC_THRES_CTRL_THRES1_EN_Pos = 0x1e + // Bit mask of THRES1_EN field. + APB_SARADC_THRES_CTRL_THRES1_EN_Msk = 0x40000000 + // Bit THRES1_EN. + APB_SARADC_THRES_CTRL_THRES1_EN = 0x40000000 + // Position of THRES0_EN field. + APB_SARADC_THRES_CTRL_THRES0_EN_Pos = 0x1f + // Bit mask of THRES0_EN field. + APB_SARADC_THRES_CTRL_THRES0_EN_Msk = 0x80000000 + // Bit THRES0_EN. + APB_SARADC_THRES_CTRL_THRES0_EN = 0x80000000 + + // INT_ENA: enable interrupt + // Position of THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_THRES1_LOW_INT_ENA_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_ENA field. + APB_SARADC_INT_ENA_THRES1_LOW_INT_ENA_Msk = 0x4000000 + // Bit THRES1_LOW_INT_ENA. + APB_SARADC_INT_ENA_THRES1_LOW_INT_ENA = 0x4000000 + // Position of THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_THRES0_LOW_INT_ENA_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_ENA field. + APB_SARADC_INT_ENA_THRES0_LOW_INT_ENA_Msk = 0x8000000 + // Bit THRES0_LOW_INT_ENA. + APB_SARADC_INT_ENA_THRES0_LOW_INT_ENA = 0x8000000 + // Position of THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_THRES1_HIGH_INT_ENA_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_THRES1_HIGH_INT_ENA_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_ENA. + APB_SARADC_INT_ENA_THRES1_HIGH_INT_ENA = 0x10000000 + // Position of THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_THRES0_HIGH_INT_ENA_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_ENA field. + APB_SARADC_INT_ENA_THRES0_HIGH_INT_ENA_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_ENA. + APB_SARADC_INT_ENA_THRES0_HIGH_INT_ENA = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC2_DONE_INT_ENA = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ENA field. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ENA. + APB_SARADC_INT_ENA_APB_SARADC1_DONE_INT_ENA = 0x80000000 + + // INT_RAW: raw of interrupt + // Position of THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_THRES1_LOW_INT_RAW_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_RAW field. + APB_SARADC_INT_RAW_THRES1_LOW_INT_RAW_Msk = 0x4000000 + // Bit THRES1_LOW_INT_RAW. + APB_SARADC_INT_RAW_THRES1_LOW_INT_RAW = 0x4000000 + // Position of THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_THRES0_LOW_INT_RAW_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_RAW field. + APB_SARADC_INT_RAW_THRES0_LOW_INT_RAW_Msk = 0x8000000 + // Bit THRES0_LOW_INT_RAW. + APB_SARADC_INT_RAW_THRES0_LOW_INT_RAW = 0x8000000 + // Position of THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_THRES1_HIGH_INT_RAW_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_THRES1_HIGH_INT_RAW_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_RAW. + APB_SARADC_INT_RAW_THRES1_HIGH_INT_RAW = 0x10000000 + // Position of THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_THRES0_HIGH_INT_RAW_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_RAW field. + APB_SARADC_INT_RAW_THRES0_HIGH_INT_RAW_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_RAW. + APB_SARADC_INT_RAW_THRES0_HIGH_INT_RAW = 0x20000000 + // Position of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC2_DONE_INT_RAW = 0x40000000 + // Position of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_RAW field. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_RAW. + APB_SARADC_INT_RAW_APB_SARADC1_DONE_INT_RAW = 0x80000000 + + // INT_ST: state of interrupt + // Position of THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_THRES1_LOW_INT_ST_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_ST field. + APB_SARADC_INT_ST_THRES1_LOW_INT_ST_Msk = 0x4000000 + // Bit THRES1_LOW_INT_ST. + APB_SARADC_INT_ST_THRES1_LOW_INT_ST = 0x4000000 + // Position of THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_THRES0_LOW_INT_ST_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_ST field. + APB_SARADC_INT_ST_THRES0_LOW_INT_ST_Msk = 0x8000000 + // Bit THRES0_LOW_INT_ST. + APB_SARADC_INT_ST_THRES0_LOW_INT_ST = 0x8000000 + // Position of THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_THRES1_HIGH_INT_ST_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_ST field. + APB_SARADC_INT_ST_THRES1_HIGH_INT_ST_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_ST. + APB_SARADC_INT_ST_THRES1_HIGH_INT_ST = 0x10000000 + // Position of THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_THRES0_HIGH_INT_ST_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_ST field. + APB_SARADC_INT_ST_THRES0_HIGH_INT_ST_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_ST. + APB_SARADC_INT_ST_THRES0_HIGH_INT_ST = 0x20000000 + // Position of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC2_DONE_INT_ST = 0x40000000 + // Position of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_ST field. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_ST. + APB_SARADC_INT_ST_APB_SARADC1_DONE_INT_ST = 0x80000000 + + // INT_CLR: clear interrupt + // Position of THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_THRES1_LOW_INT_CLR_Pos = 0x1a + // Bit mask of THRES1_LOW_INT_CLR field. + APB_SARADC_INT_CLR_THRES1_LOW_INT_CLR_Msk = 0x4000000 + // Bit THRES1_LOW_INT_CLR. + APB_SARADC_INT_CLR_THRES1_LOW_INT_CLR = 0x4000000 + // Position of THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_THRES0_LOW_INT_CLR_Pos = 0x1b + // Bit mask of THRES0_LOW_INT_CLR field. + APB_SARADC_INT_CLR_THRES0_LOW_INT_CLR_Msk = 0x8000000 + // Bit THRES0_LOW_INT_CLR. + APB_SARADC_INT_CLR_THRES0_LOW_INT_CLR = 0x8000000 + // Position of THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_THRES1_HIGH_INT_CLR_Pos = 0x1c + // Bit mask of THRES1_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_THRES1_HIGH_INT_CLR_Msk = 0x10000000 + // Bit THRES1_HIGH_INT_CLR. + APB_SARADC_INT_CLR_THRES1_HIGH_INT_CLR = 0x10000000 + // Position of THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_THRES0_HIGH_INT_CLR_Pos = 0x1d + // Bit mask of THRES0_HIGH_INT_CLR field. + APB_SARADC_INT_CLR_THRES0_HIGH_INT_CLR_Msk = 0x20000000 + // Bit THRES0_HIGH_INT_CLR. + APB_SARADC_INT_CLR_THRES0_HIGH_INT_CLR = 0x20000000 + // Position of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Pos = 0x1e + // Bit mask of APB_SARADC2_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Msk = 0x40000000 + // Bit APB_SARADC2_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC2_DONE_INT_CLR = 0x40000000 + // Position of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Pos = 0x1f + // Bit mask of APB_SARADC1_DONE_INT_CLR field. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Msk = 0x80000000 + // Bit APB_SARADC1_DONE_INT_CLR. + APB_SARADC_INT_CLR_APB_SARADC1_DONE_INT_CLR = 0x80000000 + + // DMA_CONF: configure apb saradc dma + // Position of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Pos = 0x0 + // Bit mask of APB_ADC_EOF_NUM field. + APB_SARADC_DMA_CONF_APB_ADC_EOF_NUM_Msk = 0xffff + // Position of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Pos = 0x1e + // Bit mask of APB_ADC_RESET_FSM field. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM_Msk = 0x40000000 + // Bit APB_ADC_RESET_FSM. + APB_SARADC_DMA_CONF_APB_ADC_RESET_FSM = 0x40000000 + // Position of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Pos = 0x1f + // Bit mask of APB_ADC_TRANS field. + APB_SARADC_DMA_CONF_APB_ADC_TRANS_Msk = 0x80000000 + // Bit APB_ADC_TRANS. + APB_SARADC_DMA_CONF_APB_ADC_TRANS = 0x80000000 + + // CLKM_CONF: configure apb saradc clock + // Position of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of CLKM_DIV_NUM field. + APB_SARADC_CLKM_CONF_CLKM_DIV_NUM_Msk = 0xff + // Position of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Pos = 0x8 + // Bit mask of CLKM_DIV_B field. + APB_SARADC_CLKM_CONF_CLKM_DIV_B_Msk = 0x3f00 + // Position of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Pos = 0xe + // Bit mask of CLKM_DIV_A field. + APB_SARADC_CLKM_CONF_CLKM_DIV_A_Msk = 0xfc000 + // Position of CLK_EN field. + APB_SARADC_CLKM_CONF_CLK_EN_Pos = 0x14 + // Bit mask of CLK_EN field. + APB_SARADC_CLKM_CONF_CLK_EN_Msk = 0x100000 + // Bit CLK_EN. + APB_SARADC_CLKM_CONF_CLK_EN = 0x100000 + // Position of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Pos = 0x15 + // Bit mask of CLK_SEL field. + APB_SARADC_CLKM_CONF_CLK_SEL_Msk = 0x600000 + + // APB_SARADC2_DATA_STATUS: get apb saradc2 sample data + // Position of APB_SARADC2_DATA field. + APB_SARADC_APB_SARADC2_DATA_STATUS_APB_SARADC2_DATA_Pos = 0x0 + // Bit mask of APB_SARADC2_DATA field. + APB_SARADC_APB_SARADC2_DATA_STATUS_APB_SARADC2_DATA_Msk = 0x1ffff + + // APB_CTRL_DATE: version + // Position of APB_CTRL_DATE field. + APB_SARADC_APB_CTRL_DATE_APB_CTRL_DATE_Pos = 0x0 + // Bit mask of APB_CTRL_DATE field. + APB_SARADC_APB_CTRL_DATE_APB_CTRL_DATE_Msk = 0xffffffff +) + +// Constants for BB: BB Peripheral +const ( + // BBPD_CTRL: Baseband control register + // Position of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Pos = 0x0 + // Bit mask of DC_EST_FORCE_PD field. + BB_BBPD_CTRL_DC_EST_FORCE_PD_Msk = 0x1 + // Bit DC_EST_FORCE_PD. + BB_BBPD_CTRL_DC_EST_FORCE_PD = 0x1 + // Position of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Pos = 0x1 + // Bit mask of DC_EST_FORCE_PU field. + BB_BBPD_CTRL_DC_EST_FORCE_PU_Msk = 0x2 + // Bit DC_EST_FORCE_PU. + BB_BBPD_CTRL_DC_EST_FORCE_PU = 0x2 + // Position of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Pos = 0x2 + // Bit mask of FFT_FORCE_PD field. + BB_BBPD_CTRL_FFT_FORCE_PD_Msk = 0x4 + // Bit FFT_FORCE_PD. + BB_BBPD_CTRL_FFT_FORCE_PD = 0x4 + // Position of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Pos = 0x3 + // Bit mask of FFT_FORCE_PU field. + BB_BBPD_CTRL_FFT_FORCE_PU_Msk = 0x8 + // Bit FFT_FORCE_PU. + BB_BBPD_CTRL_FFT_FORCE_PU = 0x8 +) + +// Constants for ASSIST_DEBUG: Debug Assist +const ( + // CORE_0_MONTR_ENA: core0 monitor enable configuration register + // Position of CORE_0_AREA_DRAM0_0_RD_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_RD_ENA = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_0_WR_ENA = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_RD_ENA = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_AREA_PIF_1_WR_ENA = 0x80 + // Position of CORE_0_SP_SPILL_MIN_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MIN_ENA = 0x100 + // Position of CORE_0_SP_SPILL_MAX_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_SP_SPILL_MAX_ENA = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_ENA. + DEBUG_ASSIST_CORE_0_MONTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA = 0x800 + + // CORE_0_INTR_RAW: core0 monitor interrupt status register + // Position of CORE_0_AREA_DRAM0_0_RD_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW = 0x80 + // Position of CORE_0_SP_SPILL_MIN_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW = 0x100 + // Position of CORE_0_SP_SPILL_MAX_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_RAW. + DEBUG_ASSIST_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW = 0x800 + + // CORE_0_INTR_ENA: core0 monitor interrupt enable register + // Position of CORE_0_AREA_DRAM0_0_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_INTR_ENA = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_INTR_ENA = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_INTR_ENA = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_INTR_ENA = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_INTR_ENA = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_INTR_ENA = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_INTR_ENA = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_INTR_ENA = 0x80 + // Position of CORE_0_SP_SPILL_MIN_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_INTR_ENA = 0x100 + // Position of CORE_0_SP_SPILL_MAX_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_INTR_ENA = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA field. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA. + DEBUG_ASSIST_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA = 0x800 + + // CORE_0_INTR_CLR: core0 monitor interrupt clr register + // Position of CORE_0_AREA_DRAM0_0_RD_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_RD_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Msk = 0x1 + // Bit CORE_0_AREA_DRAM0_0_RD_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR = 0x1 + // Position of CORE_0_AREA_DRAM0_0_WR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Pos = 0x1 + // Bit mask of CORE_0_AREA_DRAM0_0_WR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Msk = 0x2 + // Bit CORE_0_AREA_DRAM0_0_WR_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR = 0x2 + // Position of CORE_0_AREA_DRAM0_1_RD_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Pos = 0x2 + // Bit mask of CORE_0_AREA_DRAM0_1_RD_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Msk = 0x4 + // Bit CORE_0_AREA_DRAM0_1_RD_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR = 0x4 + // Position of CORE_0_AREA_DRAM0_1_WR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Pos = 0x3 + // Bit mask of CORE_0_AREA_DRAM0_1_WR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Msk = 0x8 + // Bit CORE_0_AREA_DRAM0_1_WR_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR = 0x8 + // Position of CORE_0_AREA_PIF_0_RD_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Pos = 0x4 + // Bit mask of CORE_0_AREA_PIF_0_RD_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Msk = 0x10 + // Bit CORE_0_AREA_PIF_0_RD_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR = 0x10 + // Position of CORE_0_AREA_PIF_0_WR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Pos = 0x5 + // Bit mask of CORE_0_AREA_PIF_0_WR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Msk = 0x20 + // Bit CORE_0_AREA_PIF_0_WR_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR = 0x20 + // Position of CORE_0_AREA_PIF_1_RD_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Pos = 0x6 + // Bit mask of CORE_0_AREA_PIF_1_RD_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Msk = 0x40 + // Bit CORE_0_AREA_PIF_1_RD_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR = 0x40 + // Position of CORE_0_AREA_PIF_1_WR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Pos = 0x7 + // Bit mask of CORE_0_AREA_PIF_1_WR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Msk = 0x80 + // Bit CORE_0_AREA_PIF_1_WR_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR = 0x80 + // Position of CORE_0_SP_SPILL_MIN_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Pos = 0x8 + // Bit mask of CORE_0_SP_SPILL_MIN_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Msk = 0x100 + // Bit CORE_0_SP_SPILL_MIN_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR = 0x100 + // Position of CORE_0_SP_SPILL_MAX_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Pos = 0x9 + // Bit mask of CORE_0_SP_SPILL_MAX_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Msk = 0x200 + // Bit CORE_0_SP_SPILL_MAX_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR = 0x200 + // Position of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xa + // Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x400 + // Bit CORE_0_IRAM0_EXCEPTION_MONITOR_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR = 0x400 + // Position of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xb + // Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x800 + // Bit CORE_0_DRAM0_EXCEPTION_MONITOR_CLR. + DEBUG_ASSIST_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR = 0x800 + + // CORE_0_AREA_DRAM0_0_MIN: core0 dram0 region0 addr configuration register + // Position of CORE_0_AREA_DRAM0_0_MIN field. + DEBUG_ASSIST_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_MIN field. + DEBUG_ASSIST_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_0_MAX: core0 dram0 region0 addr configuration register + // Position of CORE_0_AREA_DRAM0_0_MAX field. + DEBUG_ASSIST_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_0_MAX field. + DEBUG_ASSIST_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_1_MIN: core0 dram0 region1 addr configuration register + // Position of CORE_0_AREA_DRAM0_1_MIN field. + DEBUG_ASSIST_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_1_MIN field. + DEBUG_ASSIST_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Msk = 0xffffffff + + // CORE_0_AREA_DRAM0_1_MAX: core0 dram0 region1 addr configuration register + // Position of CORE_0_AREA_DRAM0_1_MAX field. + DEBUG_ASSIST_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_DRAM0_1_MAX field. + DEBUG_ASSIST_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PIF_0_MIN: core0 PIF region0 addr configuration register + // Position of CORE_0_AREA_PIF_0_MIN field. + DEBUG_ASSIST_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_0_MIN field. + DEBUG_ASSIST_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Msk = 0xffffffff + + // CORE_0_AREA_PIF_0_MAX: core0 PIF region0 addr configuration register + // Position of CORE_0_AREA_PIF_0_MAX field. + DEBUG_ASSIST_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_0_MAX field. + DEBUG_ASSIST_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Msk = 0xffffffff + + // CORE_0_AREA_PIF_1_MIN: core0 PIF region1 addr configuration register + // Position of CORE_0_AREA_PIF_1_MIN field. + DEBUG_ASSIST_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_1_MIN field. + DEBUG_ASSIST_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Msk = 0xffffffff + + // CORE_0_AREA_PIF_1_MAX: core0 PIF region1 addr configuration register + // Position of CORE_0_AREA_PIF_1_MAX field. + DEBUG_ASSIST_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Pos = 0x0 + // Bit mask of CORE_0_AREA_PIF_1_MAX field. + DEBUG_ASSIST_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Msk = 0xffffffff + + // CORE_0_AREA_SP: core0 area sp status register + // Position of CORE_0_AREA_SP field. + DEBUG_ASSIST_CORE_0_AREA_SP_CORE_0_AREA_SP_Pos = 0x0 + // Bit mask of CORE_0_AREA_SP field. + DEBUG_ASSIST_CORE_0_AREA_SP_CORE_0_AREA_SP_Msk = 0xffffffff + + // CORE_0_AREA_PC: core0 area pc status register + // Position of CORE_0_AREA_PC field. + DEBUG_ASSIST_CORE_0_AREA_PC_CORE_0_AREA_PC_Pos = 0x0 + // Bit mask of CORE_0_AREA_PC field. + DEBUG_ASSIST_CORE_0_AREA_PC_CORE_0_AREA_PC_Msk = 0xffffffff + + // CORE_0_SP_UNSTABLE: core0 sp unstable configuration register + // Position of CORE_0_SP_UNSTABLE field. + DEBUG_ASSIST_CORE_0_SP_UNSTABLE_CORE_0_SP_UNSTABLE_Pos = 0x0 + // Bit mask of CORE_0_SP_UNSTABLE field. + DEBUG_ASSIST_CORE_0_SP_UNSTABLE_CORE_0_SP_UNSTABLE_Msk = 0xff + + // CORE_0_SP_MIN: core0 sp region configuration regsiter + // Position of CORE_0_SP_MIN field. + DEBUG_ASSIST_CORE_0_SP_MIN_CORE_0_SP_MIN_Pos = 0x0 + // Bit mask of CORE_0_SP_MIN field. + DEBUG_ASSIST_CORE_0_SP_MIN_CORE_0_SP_MIN_Msk = 0xffffffff + + // CORE_0_SP_MAX: core0 sp region configuration regsiter + // Position of CORE_0_SP_MAX field. + DEBUG_ASSIST_CORE_0_SP_MAX_CORE_0_SP_MAX_Pos = 0x0 + // Bit mask of CORE_0_SP_MAX field. + DEBUG_ASSIST_CORE_0_SP_MAX_CORE_0_SP_MAX_Msk = 0xffffffff + + // CORE_0_SP_PC: core0 sp pc status register + // Position of CORE_0_SP_PC field. + DEBUG_ASSIST_CORE_0_SP_PC_CORE_0_SP_PC_Pos = 0x0 + // Bit mask of CORE_0_SP_PC field. + DEBUG_ASSIST_CORE_0_SP_PC_CORE_0_SP_PC_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGENABLE: core0 pdebug configuration register + // Position of CORE_0_RCD_PDEBUGENABLE field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGENABLE_CORE_0_RCD_PDEBUGENABLE_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGENABLE field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGENABLE_CORE_0_RCD_PDEBUGENABLE_Msk = 0x1 + // Bit CORE_0_RCD_PDEBUGENABLE. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGENABLE_CORE_0_RCD_PDEBUGENABLE = 0x1 + + // CORE_0_RCD_RECORDING: core0 pdebug status register + // Position of CORE_0_RCD_RECORDING field. + DEBUG_ASSIST_CORE_0_RCD_RECORDING_CORE_0_RCD_RECORDING_Pos = 0x0 + // Bit mask of CORE_0_RCD_RECORDING field. + DEBUG_ASSIST_CORE_0_RCD_RECORDING_CORE_0_RCD_RECORDING_Msk = 0x1 + // Bit CORE_0_RCD_RECORDING. + DEBUG_ASSIST_CORE_0_RCD_RECORDING_CORE_0_RCD_RECORDING = 0x1 + + // CORE_0_RCD_PDEBUGINST: core0 pdebug status register + // Position of CORE_0_RCD_PDEBUGINST field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGINST_CORE_0_RCD_PDEBUGINST_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGINST field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGINST_CORE_0_RCD_PDEBUGINST_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGSTATUS: core0 pdebug status register + // Position of CORE_0_RCD_PDEBUGSTATUS field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGSTATUS_CORE_0_RCD_PDEBUGSTATUS_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGSTATUS field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGSTATUS_CORE_0_RCD_PDEBUGSTATUS_Msk = 0xff + + // CORE_0_RCD_PDEBUGDATA: core0 pdebug status register + // Position of CORE_0_RCD_PDEBUGDATA field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGDATA_CORE_0_RCD_PDEBUGDATA_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGDATA field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGDATA_CORE_0_RCD_PDEBUGDATA_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGPC: core0 pdebug status register + // Position of CORE_0_RCD_PDEBUGPC field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGPC field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGLS0STAT: core0 pdebug status register + // Position of CORE_0_RCD_PDEBUGLS0STAT field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGLS0STAT_CORE_0_RCD_PDEBUGLS0STAT_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGLS0STAT field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGLS0STAT_CORE_0_RCD_PDEBUGLS0STAT_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGLS0ADDR: core0 pdebug status register + // Position of CORE_0_RCD_PDEBUGLS0ADDR field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGLS0ADDR_CORE_0_RCD_PDEBUGLS0ADDR_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGLS0ADDR field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGLS0ADDR_CORE_0_RCD_PDEBUGLS0ADDR_Msk = 0xffffffff + + // CORE_0_RCD_PDEBUGLS0DATA: core0 pdebug status register + // Position of CORE_0_RCD_PDEBUGLS0DATA field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGLS0DATA_CORE_0_RCD_PDEBUGLS0DATA_Pos = 0x0 + // Bit mask of CORE_0_RCD_PDEBUGLS0DATA field. + DEBUG_ASSIST_CORE_0_RCD_PDEBUGLS0DATA_CORE_0_RCD_PDEBUGLS0DATA_Msk = 0xffffffff + + // CORE_0_RCD_SP: core0 pdebug status register + // Position of CORE_0_RCD_SP field. + DEBUG_ASSIST_CORE_0_RCD_SP_CORE_0_RCD_SP_Pos = 0x0 + // Bit mask of CORE_0_RCD_SP field. + DEBUG_ASSIST_CORE_0_RCD_SP_CORE_0_RCD_SP_Msk = 0xffffffff + + // CORE_0_IRAM0_EXCEPTION_MONITOR_0: core0 bus busy status regsiter + // Position of CORE_0_IRAM0_RECORDING_ADDR_0 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_RECORDING_ADDR_0 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Msk = 0xffffff + // Position of CORE_0_IRAM0_RECORDING_WR_0 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Pos = 0x18 + // Bit mask of CORE_0_IRAM0_RECORDING_WR_0 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Msk = 0x1000000 + // Bit CORE_0_IRAM0_RECORDING_WR_0. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0 = 0x1000000 + // Position of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Pos = 0x19 + // Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Msk = 0x2000000 + // Bit CORE_0_IRAM0_RECORDING_LOADSTORE_0. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0 = 0x2000000 + + // CORE_0_IRAM0_EXCEPTION_MONITOR_1: core0 bus busy status regsiter + // Position of CORE_0_IRAM0_RECORDING_ADDR_1 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_RECORDING_ADDR_1 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Msk = 0xffffff + // Position of CORE_0_IRAM0_RECORDING_WR_1 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Pos = 0x18 + // Bit mask of CORE_0_IRAM0_RECORDING_WR_1 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Msk = 0x1000000 + // Bit CORE_0_IRAM0_RECORDING_WR_1. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1 = 0x1000000 + // Position of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Pos = 0x19 + // Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Msk = 0x2000000 + // Bit CORE_0_IRAM0_RECORDING_LOADSTORE_1. + DEBUG_ASSIST_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1 = 0x2000000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_0: core0 bus busy status regsiter + // Position of CORE_0_DRAM0_RECORDING_ADDR_0 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_ADDR_0 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_ADDR_0_Msk = 0x3fffff + // Position of CORE_0_DRAM0_RECORDING_WR_0 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Pos = 0x16 + // Bit mask of CORE_0_DRAM0_RECORDING_WR_0 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Msk = 0x400000 + // Bit CORE_0_DRAM0_RECORDING_WR_0. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0 = 0x400000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_1: core0 bus busy status regsiter + // Position of CORE_0_DRAM0_RECORDING_BYTEEN_0 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_BYTEEN_0_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_0 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_BYTEEN_0_Msk = 0xffff + + // CORE_0_DRAM0_EXCEPTION_MONITOR_2: core0 bus busy status regsiter + // Position of CORE_0_DRAM0_RECORDING_PC_0 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_PC_0_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_PC_0 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_PC_0_Msk = 0xffffffff + + // CORE_0_DRAM0_EXCEPTION_MONITOR_3: core0 bus busy status regsiter + // Position of CORE_0_DRAM0_RECORDING_ADDR_1 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_ADDR_1 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_ADDR_1_Msk = 0x3fffff + // Position of CORE_0_DRAM0_RECORDING_WR_1 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1_Pos = 0x16 + // Bit mask of CORE_0_DRAM0_RECORDING_WR_1 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1_Msk = 0x400000 + // Bit CORE_0_DRAM0_RECORDING_WR_1. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1 = 0x400000 + + // CORE_0_DRAM0_EXCEPTION_MONITOR_4: core0 bus busy configuration regsiter + // Position of CORE_0_DRAM0_RECORDING_BYTEEN_1 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_BYTEEN_1_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_1 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_BYTEEN_1_Msk = 0xffff + + // CORE_0_DRAM0_EXCEPTION_MONITOR_5: core0 bus busy configuration regsiter + // Position of CORE_0_DRAM0_RECORDING_PC_1 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_5_CORE_0_DRAM0_RECORDING_PC_1_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_RECORDING_PC_1 field. + DEBUG_ASSIST_CORE_0_DRAM0_EXCEPTION_MONITOR_5_CORE_0_DRAM0_RECORDING_PC_1_Msk = 0xffffffff + + // CORE_1_MONTR_ENA: Core1 monitor enable configuration register + // Position of CORE_1_AREA_DRAM0_0_RD_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA_Pos = 0x0 + // Bit mask of CORE_1_AREA_DRAM0_0_RD_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA_Msk = 0x1 + // Bit CORE_1_AREA_DRAM0_0_RD_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA = 0x1 + // Position of CORE_1_AREA_DRAM0_0_WR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA_Pos = 0x1 + // Bit mask of CORE_1_AREA_DRAM0_0_WR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA_Msk = 0x2 + // Bit CORE_1_AREA_DRAM0_0_WR_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA = 0x2 + // Position of CORE_1_AREA_DRAM0_1_RD_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA_Pos = 0x2 + // Bit mask of CORE_1_AREA_DRAM0_1_RD_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA_Msk = 0x4 + // Bit CORE_1_AREA_DRAM0_1_RD_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA = 0x4 + // Position of CORE_1_AREA_DRAM0_1_WR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA_Pos = 0x3 + // Bit mask of CORE_1_AREA_DRAM0_1_WR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA_Msk = 0x8 + // Bit CORE_1_AREA_DRAM0_1_WR_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA = 0x8 + // Position of CORE_1_AREA_PIF_0_RD_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_RD_ENA_Pos = 0x4 + // Bit mask of CORE_1_AREA_PIF_0_RD_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_RD_ENA_Msk = 0x10 + // Bit CORE_1_AREA_PIF_0_RD_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_RD_ENA = 0x10 + // Position of CORE_1_AREA_PIF_0_WR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_WR_ENA_Pos = 0x5 + // Bit mask of CORE_1_AREA_PIF_0_WR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_WR_ENA_Msk = 0x20 + // Bit CORE_1_AREA_PIF_0_WR_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_0_WR_ENA = 0x20 + // Position of CORE_1_AREA_PIF_1_RD_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_RD_ENA_Pos = 0x6 + // Bit mask of CORE_1_AREA_PIF_1_RD_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_RD_ENA_Msk = 0x40 + // Bit CORE_1_AREA_PIF_1_RD_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_RD_ENA = 0x40 + // Position of CORE_1_AREA_PIF_1_WR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_WR_ENA_Pos = 0x7 + // Bit mask of CORE_1_AREA_PIF_1_WR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_WR_ENA_Msk = 0x80 + // Bit CORE_1_AREA_PIF_1_WR_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_AREA_PIF_1_WR_ENA = 0x80 + // Position of CORE_1_SP_SPILL_MIN_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_SP_SPILL_MIN_ENA_Pos = 0x8 + // Bit mask of CORE_1_SP_SPILL_MIN_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_SP_SPILL_MIN_ENA_Msk = 0x100 + // Bit CORE_1_SP_SPILL_MIN_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_SP_SPILL_MIN_ENA = 0x100 + // Position of CORE_1_SP_SPILL_MAX_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_SP_SPILL_MAX_ENA_Pos = 0x9 + // Bit mask of CORE_1_SP_SPILL_MAX_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_SP_SPILL_MAX_ENA_Msk = 0x200 + // Bit CORE_1_SP_SPILL_MAX_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_SP_SPILL_MAX_ENA = 0x200 + // Position of CORE_1_IRAM0_EXCEPTION_MONITOR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xa + // Bit mask of CORE_1_IRAM0_EXCEPTION_MONITOR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x400 + // Bit CORE_1_IRAM0_EXCEPTION_MONITOR_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA = 0x400 + // Position of CORE_1_DRAM0_EXCEPTION_MONITOR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xb + // Bit mask of CORE_1_DRAM0_EXCEPTION_MONITOR_ENA field. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x800 + // Bit CORE_1_DRAM0_EXCEPTION_MONITOR_ENA. + DEBUG_ASSIST_CORE_1_MONTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA = 0x800 + + // CORE_1_INTR_RAW: Core1 monitor interrupt status register + // Position of CORE_1_AREA_DRAM0_0_RD_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW_Pos = 0x0 + // Bit mask of CORE_1_AREA_DRAM0_0_RD_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW_Msk = 0x1 + // Bit CORE_1_AREA_DRAM0_0_RD_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW = 0x1 + // Position of CORE_1_AREA_DRAM0_0_WR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW_Pos = 0x1 + // Bit mask of CORE_1_AREA_DRAM0_0_WR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW_Msk = 0x2 + // Bit CORE_1_AREA_DRAM0_0_WR_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW = 0x2 + // Position of CORE_1_AREA_DRAM0_1_RD_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW_Pos = 0x2 + // Bit mask of CORE_1_AREA_DRAM0_1_RD_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW_Msk = 0x4 + // Bit CORE_1_AREA_DRAM0_1_RD_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW = 0x4 + // Position of CORE_1_AREA_DRAM0_1_WR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW_Pos = 0x3 + // Bit mask of CORE_1_AREA_DRAM0_1_WR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW_Msk = 0x8 + // Bit CORE_1_AREA_DRAM0_1_WR_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW = 0x8 + // Position of CORE_1_AREA_PIF_0_RD_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW_Pos = 0x4 + // Bit mask of CORE_1_AREA_PIF_0_RD_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW_Msk = 0x10 + // Bit CORE_1_AREA_PIF_0_RD_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW = 0x10 + // Position of CORE_1_AREA_PIF_0_WR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW_Pos = 0x5 + // Bit mask of CORE_1_AREA_PIF_0_WR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW_Msk = 0x20 + // Bit CORE_1_AREA_PIF_0_WR_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW = 0x20 + // Position of CORE_1_AREA_PIF_1_RD_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW_Pos = 0x6 + // Bit mask of CORE_1_AREA_PIF_1_RD_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW_Msk = 0x40 + // Bit CORE_1_AREA_PIF_1_RD_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW = 0x40 + // Position of CORE_1_AREA_PIF_1_WR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW_Pos = 0x7 + // Bit mask of CORE_1_AREA_PIF_1_WR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW_Msk = 0x80 + // Bit CORE_1_AREA_PIF_1_WR_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW = 0x80 + // Position of CORE_1_SP_SPILL_MIN_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW_Pos = 0x8 + // Bit mask of CORE_1_SP_SPILL_MIN_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW_Msk = 0x100 + // Bit CORE_1_SP_SPILL_MIN_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW = 0x100 + // Position of CORE_1_SP_SPILL_MAX_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW_Pos = 0x9 + // Bit mask of CORE_1_SP_SPILL_MAX_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW_Msk = 0x200 + // Bit CORE_1_SP_SPILL_MAX_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW = 0x200 + // Position of CORE_1_IRAM0_EXCEPTION_MONITOR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xa + // Bit mask of CORE_1_IRAM0_EXCEPTION_MONITOR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x400 + // Bit CORE_1_IRAM0_EXCEPTION_MONITOR_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW = 0x400 + // Position of CORE_1_DRAM0_EXCEPTION_MONITOR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xb + // Bit mask of CORE_1_DRAM0_EXCEPTION_MONITOR_RAW field. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x800 + // Bit CORE_1_DRAM0_EXCEPTION_MONITOR_RAW. + DEBUG_ASSIST_CORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW = 0x800 + + // CORE_1_INTR_ENA: Core1 monitor interrupt enable register + // Position of CORE_1_AREA_DRAM0_0_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_INTR_ENA_Pos = 0x0 + // Bit mask of CORE_1_AREA_DRAM0_0_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_INTR_ENA_Msk = 0x1 + // Bit CORE_1_AREA_DRAM0_0_RD_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_INTR_ENA = 0x1 + // Position of CORE_1_AREA_DRAM0_0_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_INTR_ENA_Pos = 0x1 + // Bit mask of CORE_1_AREA_DRAM0_0_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_INTR_ENA_Msk = 0x2 + // Bit CORE_1_AREA_DRAM0_0_WR_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_INTR_ENA = 0x2 + // Position of CORE_1_AREA_DRAM0_1_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_INTR_ENA_Pos = 0x2 + // Bit mask of CORE_1_AREA_DRAM0_1_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_INTR_ENA_Msk = 0x4 + // Bit CORE_1_AREA_DRAM0_1_RD_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_INTR_ENA = 0x4 + // Position of CORE_1_AREA_DRAM0_1_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_INTR_ENA_Pos = 0x3 + // Bit mask of CORE_1_AREA_DRAM0_1_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_INTR_ENA_Msk = 0x8 + // Bit CORE_1_AREA_DRAM0_1_WR_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_INTR_ENA = 0x8 + // Position of CORE_1_AREA_PIF_0_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_INTR_ENA_Pos = 0x4 + // Bit mask of CORE_1_AREA_PIF_0_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_INTR_ENA_Msk = 0x10 + // Bit CORE_1_AREA_PIF_0_RD_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_INTR_ENA = 0x10 + // Position of CORE_1_AREA_PIF_0_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_INTR_ENA_Pos = 0x5 + // Bit mask of CORE_1_AREA_PIF_0_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_INTR_ENA_Msk = 0x20 + // Bit CORE_1_AREA_PIF_0_WR_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_INTR_ENA = 0x20 + // Position of CORE_1_AREA_PIF_1_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_INTR_ENA_Pos = 0x6 + // Bit mask of CORE_1_AREA_PIF_1_RD_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_INTR_ENA_Msk = 0x40 + // Bit CORE_1_AREA_PIF_1_RD_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_INTR_ENA = 0x40 + // Position of CORE_1_AREA_PIF_1_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_INTR_ENA_Pos = 0x7 + // Bit mask of CORE_1_AREA_PIF_1_WR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_INTR_ENA_Msk = 0x80 + // Bit CORE_1_AREA_PIF_1_WR_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_INTR_ENA = 0x80 + // Position of CORE_1_SP_SPILL_MIN_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_INTR_ENA_Pos = 0x8 + // Bit mask of CORE_1_SP_SPILL_MIN_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_INTR_ENA_Msk = 0x100 + // Bit CORE_1_SP_SPILL_MIN_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_INTR_ENA = 0x100 + // Position of CORE_1_SP_SPILL_MAX_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_INTR_ENA_Pos = 0x9 + // Bit mask of CORE_1_SP_SPILL_MAX_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_INTR_ENA_Msk = 0x200 + // Bit CORE_1_SP_SPILL_MAX_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_INTR_ENA = 0x200 + // Position of CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA_Pos = 0xa + // Bit mask of CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA_Msk = 0x400 + // Bit CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA = 0x400 + // Position of CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA_Pos = 0xb + // Bit mask of CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA field. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA_Msk = 0x800 + // Bit CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA. + DEBUG_ASSIST_CORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA = 0x800 + + // CORE_1_INTR_CLR: Core1 monitor interrupt clr register + // Position of CORE_1_AREA_DRAM0_0_RD_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR_Pos = 0x0 + // Bit mask of CORE_1_AREA_DRAM0_0_RD_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR_Msk = 0x1 + // Bit CORE_1_AREA_DRAM0_0_RD_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR = 0x1 + // Position of CORE_1_AREA_DRAM0_0_WR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR_Pos = 0x1 + // Bit mask of CORE_1_AREA_DRAM0_0_WR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR_Msk = 0x2 + // Bit CORE_1_AREA_DRAM0_0_WR_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR = 0x2 + // Position of CORE_1_AREA_DRAM0_1_RD_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR_Pos = 0x2 + // Bit mask of CORE_1_AREA_DRAM0_1_RD_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR_Msk = 0x4 + // Bit CORE_1_AREA_DRAM0_1_RD_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR = 0x4 + // Position of CORE_1_AREA_DRAM0_1_WR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR_Pos = 0x3 + // Bit mask of CORE_1_AREA_DRAM0_1_WR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR_Msk = 0x8 + // Bit CORE_1_AREA_DRAM0_1_WR_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR = 0x8 + // Position of CORE_1_AREA_PIF_0_RD_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR_Pos = 0x4 + // Bit mask of CORE_1_AREA_PIF_0_RD_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR_Msk = 0x10 + // Bit CORE_1_AREA_PIF_0_RD_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR = 0x10 + // Position of CORE_1_AREA_PIF_0_WR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR_Pos = 0x5 + // Bit mask of CORE_1_AREA_PIF_0_WR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR_Msk = 0x20 + // Bit CORE_1_AREA_PIF_0_WR_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR = 0x20 + // Position of CORE_1_AREA_PIF_1_RD_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR_Pos = 0x6 + // Bit mask of CORE_1_AREA_PIF_1_RD_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR_Msk = 0x40 + // Bit CORE_1_AREA_PIF_1_RD_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR = 0x40 + // Position of CORE_1_AREA_PIF_1_WR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR_Pos = 0x7 + // Bit mask of CORE_1_AREA_PIF_1_WR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR_Msk = 0x80 + // Bit CORE_1_AREA_PIF_1_WR_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR = 0x80 + // Position of CORE_1_SP_SPILL_MIN_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR_Pos = 0x8 + // Bit mask of CORE_1_SP_SPILL_MIN_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR_Msk = 0x100 + // Bit CORE_1_SP_SPILL_MIN_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR = 0x100 + // Position of CORE_1_SP_SPILL_MAX_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR_Pos = 0x9 + // Bit mask of CORE_1_SP_SPILL_MAX_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR_Msk = 0x200 + // Bit CORE_1_SP_SPILL_MAX_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR = 0x200 + // Position of CORE_1_IRAM0_EXCEPTION_MONITOR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xa + // Bit mask of CORE_1_IRAM0_EXCEPTION_MONITOR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x400 + // Bit CORE_1_IRAM0_EXCEPTION_MONITOR_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR = 0x400 + // Position of CORE_1_DRAM0_EXCEPTION_MONITOR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xb + // Bit mask of CORE_1_DRAM0_EXCEPTION_MONITOR_CLR field. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x800 + // Bit CORE_1_DRAM0_EXCEPTION_MONITOR_CLR. + DEBUG_ASSIST_CORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR = 0x800 + + // CORE_1_AREA_DRAM0_0_MIN: Core1 dram0 region0 addr configuration register + // Position of CORE_1_AREA_DRAM0_0_MIN field. + DEBUG_ASSIST_CORE_1_AREA_DRAM0_0_MIN_CORE_1_AREA_DRAM0_0_MIN_Pos = 0x0 + // Bit mask of CORE_1_AREA_DRAM0_0_MIN field. + DEBUG_ASSIST_CORE_1_AREA_DRAM0_0_MIN_CORE_1_AREA_DRAM0_0_MIN_Msk = 0xffffffff + + // CORE_1_AREA_DRAM0_0_MAX: Core1 dram0 region0 addr configuration register + // Position of CORE_1_AREA_DRAM0_0_MAX field. + DEBUG_ASSIST_CORE_1_AREA_DRAM0_0_MAX_CORE_1_AREA_DRAM0_0_MAX_Pos = 0x0 + // Bit mask of CORE_1_AREA_DRAM0_0_MAX field. + DEBUG_ASSIST_CORE_1_AREA_DRAM0_0_MAX_CORE_1_AREA_DRAM0_0_MAX_Msk = 0xffffffff + + // CORE_1_AREA_DRAM0_1_MIN: Core1 dram0 region1 addr configuration register + // Position of CORE_1_AREA_DRAM0_1_MIN field. + DEBUG_ASSIST_CORE_1_AREA_DRAM0_1_MIN_CORE_1_AREA_DRAM0_1_MIN_Pos = 0x0 + // Bit mask of CORE_1_AREA_DRAM0_1_MIN field. + DEBUG_ASSIST_CORE_1_AREA_DRAM0_1_MIN_CORE_1_AREA_DRAM0_1_MIN_Msk = 0xffffffff + + // CORE_1_AREA_DRAM0_1_MAX: Core1 dram0 region1 addr configuration register + // Position of CORE_1_AREA_DRAM0_1_MAX field. + DEBUG_ASSIST_CORE_1_AREA_DRAM0_1_MAX_CORE_1_AREA_DRAM0_1_MAX_Pos = 0x0 + // Bit mask of CORE_1_AREA_DRAM0_1_MAX field. + DEBUG_ASSIST_CORE_1_AREA_DRAM0_1_MAX_CORE_1_AREA_DRAM0_1_MAX_Msk = 0xffffffff + + // CORE_1_AREA_PIF_0_MIN: Core1 PIF region0 addr configuration register + // Position of CORE_1_AREA_PIF_0_MIN field. + DEBUG_ASSIST_CORE_1_AREA_PIF_0_MIN_CORE_1_AREA_PIF_0_MIN_Pos = 0x0 + // Bit mask of CORE_1_AREA_PIF_0_MIN field. + DEBUG_ASSIST_CORE_1_AREA_PIF_0_MIN_CORE_1_AREA_PIF_0_MIN_Msk = 0xffffffff + + // CORE_1_AREA_PIF_0_MAX: Core1 PIF region0 addr configuration register + // Position of CORE_1_AREA_PIF_0_MAX field. + DEBUG_ASSIST_CORE_1_AREA_PIF_0_MAX_CORE_1_AREA_PIF_0_MAX_Pos = 0x0 + // Bit mask of CORE_1_AREA_PIF_0_MAX field. + DEBUG_ASSIST_CORE_1_AREA_PIF_0_MAX_CORE_1_AREA_PIF_0_MAX_Msk = 0xffffffff + + // CORE_1_AREA_PIF_1_MIN: Core1 PIF region1 addr configuration register + // Position of CORE_1_AREA_PIF_1_MIN field. + DEBUG_ASSIST_CORE_1_AREA_PIF_1_MIN_CORE_1_AREA_PIF_1_MIN_Pos = 0x0 + // Bit mask of CORE_1_AREA_PIF_1_MIN field. + DEBUG_ASSIST_CORE_1_AREA_PIF_1_MIN_CORE_1_AREA_PIF_1_MIN_Msk = 0xffffffff + + // CORE_1_AREA_PIF_1_MAX: Core1 PIF region1 addr configuration register + // Position of CORE_1_AREA_PIF_1_MAX field. + DEBUG_ASSIST_CORE_1_AREA_PIF_1_MAX_CORE_1_AREA_PIF_1_MAX_Pos = 0x0 + // Bit mask of CORE_1_AREA_PIF_1_MAX field. + DEBUG_ASSIST_CORE_1_AREA_PIF_1_MAX_CORE_1_AREA_PIF_1_MAX_Msk = 0xffffffff + + // CORE_1_AREA_PC: Core1 area sp status register + // Position of CORE_1_AREA_PC field. + DEBUG_ASSIST_CORE_1_AREA_PC_CORE_1_AREA_PC_Pos = 0x0 + // Bit mask of CORE_1_AREA_PC field. + DEBUG_ASSIST_CORE_1_AREA_PC_CORE_1_AREA_PC_Msk = 0xffffffff + + // CORE_1_AREA_SP: Core1 area pc status register + // Position of CORE_1_AREA_SP field. + DEBUG_ASSIST_CORE_1_AREA_SP_CORE_1_AREA_SP_Pos = 0x0 + // Bit mask of CORE_1_AREA_SP field. + DEBUG_ASSIST_CORE_1_AREA_SP_CORE_1_AREA_SP_Msk = 0xffffffff + + // CORE_1_SP_UNSTABLE: Core1 sp unstable configuration register + // Position of CORE_1_SP_UNSTABLE field. + DEBUG_ASSIST_CORE_1_SP_UNSTABLE_CORE_1_SP_UNSTABLE_Pos = 0x0 + // Bit mask of CORE_1_SP_UNSTABLE field. + DEBUG_ASSIST_CORE_1_SP_UNSTABLE_CORE_1_SP_UNSTABLE_Msk = 0xff + + // CORE_1_SP_MIN: Core1 sp region configuration regsiter + // Position of CORE_1_SP_MIN field. + DEBUG_ASSIST_CORE_1_SP_MIN_CORE_1_SP_MIN_Pos = 0x0 + // Bit mask of CORE_1_SP_MIN field. + DEBUG_ASSIST_CORE_1_SP_MIN_CORE_1_SP_MIN_Msk = 0xffffffff + + // CORE_1_SP_MAX: Core1 sp region configuration regsiter + // Position of CORE_1_SP_MAX field. + DEBUG_ASSIST_CORE_1_SP_MAX_CORE_1_SP_MAX_Pos = 0x0 + // Bit mask of CORE_1_SP_MAX field. + DEBUG_ASSIST_CORE_1_SP_MAX_CORE_1_SP_MAX_Msk = 0xffffffff + + // CORE_1_SP_PC: Core1 sp pc status register + // Position of CORE_1_SP_PC field. + DEBUG_ASSIST_CORE_1_SP_PC_CORE_1_SP_PC_Pos = 0x0 + // Bit mask of CORE_1_SP_PC field. + DEBUG_ASSIST_CORE_1_SP_PC_CORE_1_SP_PC_Msk = 0xffffffff + + // CORE_1_RCD_PDEBUGENABLE: Core1 pdebug configuration register + // Position of CORE_1_RCD_PDEBUGENABLE field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGENABLE_CORE_1_RCD_PDEBUGENABLE_Pos = 0x0 + // Bit mask of CORE_1_RCD_PDEBUGENABLE field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGENABLE_CORE_1_RCD_PDEBUGENABLE_Msk = 0x1 + // Bit CORE_1_RCD_PDEBUGENABLE. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGENABLE_CORE_1_RCD_PDEBUGENABLE = 0x1 + + // CORE_1_RCD_RECORDING: Core1 pdebug status register + // Position of CORE_1_RCD_RECORDING field. + DEBUG_ASSIST_CORE_1_RCD_RECORDING_CORE_1_RCD_RECORDING_Pos = 0x0 + // Bit mask of CORE_1_RCD_RECORDING field. + DEBUG_ASSIST_CORE_1_RCD_RECORDING_CORE_1_RCD_RECORDING_Msk = 0x1 + // Bit CORE_1_RCD_RECORDING. + DEBUG_ASSIST_CORE_1_RCD_RECORDING_CORE_1_RCD_RECORDING = 0x1 + + // CORE_1_RCD_PDEBUGINST: Core1 pdebug status register + // Position of CORE_1_RCD_PDEBUGINST field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGINST_CORE_1_RCD_PDEBUGINST_Pos = 0x0 + // Bit mask of CORE_1_RCD_PDEBUGINST field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGINST_CORE_1_RCD_PDEBUGINST_Msk = 0xffffffff + + // CORE_1_RCD_PDEBUGSTATUS: Core1 pdebug status register + // Position of CORE_1_RCD_PDEBUGSTATUS field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGSTATUS_CORE_1_RCD_PDEBUGSTATUS_Pos = 0x0 + // Bit mask of CORE_1_RCD_PDEBUGSTATUS field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGSTATUS_CORE_1_RCD_PDEBUGSTATUS_Msk = 0xff + + // CORE_1_RCD_PDEBUGDATA: Core1 pdebug status register + // Position of CORE_1_RCD_PDEBUGDATA field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGDATA_CORE_1_RCD_PDEBUGDATA_Pos = 0x0 + // Bit mask of CORE_1_RCD_PDEBUGDATA field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGDATA_CORE_1_RCD_PDEBUGDATA_Msk = 0xffffffff + + // CORE_1_RCD_PDEBUGPC: Core1 pdebug status register + // Position of CORE_1_RCD_PDEBUGPC field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGPC_CORE_1_RCD_PDEBUGPC_Pos = 0x0 + // Bit mask of CORE_1_RCD_PDEBUGPC field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGPC_CORE_1_RCD_PDEBUGPC_Msk = 0xffffffff + + // CORE_1_RCD_PDEBUGLS0STAT: Core1 pdebug status register + // Position of CORE_1_RCD_PDEBUGLS0STAT field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGLS0STAT_CORE_1_RCD_PDEBUGLS0STAT_Pos = 0x0 + // Bit mask of CORE_1_RCD_PDEBUGLS0STAT field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGLS0STAT_CORE_1_RCD_PDEBUGLS0STAT_Msk = 0xffffffff + + // CORE_1_RCD_PDEBUGLS0ADDR: Core1 pdebug status register + // Position of CORE_1_RCD_PDEBUGLS0ADDR field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGLS0ADDR_CORE_1_RCD_PDEBUGLS0ADDR_Pos = 0x0 + // Bit mask of CORE_1_RCD_PDEBUGLS0ADDR field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGLS0ADDR_CORE_1_RCD_PDEBUGLS0ADDR_Msk = 0xffffffff + + // CORE_1_RCD_PDEBUGLS0DATA: Core1 pdebug status register + // Position of CORE_1_RCD_PDEBUGLS0DATA field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGLS0DATA_CORE_1_RCD_PDEBUGLS0DATA_Pos = 0x0 + // Bit mask of CORE_1_RCD_PDEBUGLS0DATA field. + DEBUG_ASSIST_CORE_1_RCD_PDEBUGLS0DATA_CORE_1_RCD_PDEBUGLS0DATA_Msk = 0xffffffff + + // CORE_1_RCD_SP: Core1 pdebug status register + // Position of CORE_1_RCD_SP field. + DEBUG_ASSIST_CORE_1_RCD_SP_CORE_1_RCD_SP_Pos = 0x0 + // Bit mask of CORE_1_RCD_SP field. + DEBUG_ASSIST_CORE_1_RCD_SP_CORE_1_RCD_SP_Msk = 0xffffffff + + // CORE_1_IRAM0_EXCEPTION_MONITOR_0: Core1 bus busy status regsiter + // Position of CORE_1_IRAM0_RECORDING_ADDR_0 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_1_IRAM0_RECORDING_ADDR_0 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0_Msk = 0xffffff + // Position of CORE_1_IRAM0_RECORDING_WR_0 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0_Pos = 0x18 + // Bit mask of CORE_1_IRAM0_RECORDING_WR_0 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0_Msk = 0x1000000 + // Bit CORE_1_IRAM0_RECORDING_WR_0. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0 = 0x1000000 + // Position of CORE_1_IRAM0_RECORDING_LOADSTORE_0 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0_Pos = 0x19 + // Bit mask of CORE_1_IRAM0_RECORDING_LOADSTORE_0 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0_Msk = 0x2000000 + // Bit CORE_1_IRAM0_RECORDING_LOADSTORE_0. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0 = 0x2000000 + + // CORE_1_IRAM0_EXCEPTION_MONITOR_1: Core1 bus busy status regsiter + // Position of CORE_1_IRAM0_RECORDING_ADDR_1 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_1_IRAM0_RECORDING_ADDR_1 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1_Msk = 0xffffff + // Position of CORE_1_IRAM0_RECORDING_WR_1 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1_Pos = 0x18 + // Bit mask of CORE_1_IRAM0_RECORDING_WR_1 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1_Msk = 0x1000000 + // Bit CORE_1_IRAM0_RECORDING_WR_1. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1 = 0x1000000 + // Position of CORE_1_IRAM0_RECORDING_LOADSTORE_1 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1_Pos = 0x19 + // Bit mask of CORE_1_IRAM0_RECORDING_LOADSTORE_1 field. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1_Msk = 0x2000000 + // Bit CORE_1_IRAM0_RECORDING_LOADSTORE_1. + DEBUG_ASSIST_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1 = 0x2000000 + + // CORE_1_DRAM0_EXCEPTION_MONITOR_0: Core1 bus busy status regsiter + // Position of CORE_1_DRAM0_RECORDING_ADDR_0 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_ADDR_0_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_RECORDING_ADDR_0 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_ADDR_0_Msk = 0x3fffff + // Position of CORE_1_DRAM0_RECORDING_WR_0 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0_Pos = 0x16 + // Bit mask of CORE_1_DRAM0_RECORDING_WR_0 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0_Msk = 0x400000 + // Bit CORE_1_DRAM0_RECORDING_WR_0. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0 = 0x400000 + + // CORE_1_DRAM0_EXCEPTION_MONITOR_1: Core1 bus busy status regsiter + // Position of CORE_1_DRAM0_RECORDING_BYTEEN_0 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_BYTEEN_0_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_RECORDING_BYTEEN_0 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_BYTEEN_0_Msk = 0xffff + + // CORE_1_DRAM0_EXCEPTION_MONITOR_2: Core1 bus busy status regsiter + // Position of CORE_1_DRAM0_RECORDING_PC_0 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_2_CORE_1_DRAM0_RECORDING_PC_0_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_RECORDING_PC_0 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_2_CORE_1_DRAM0_RECORDING_PC_0_Msk = 0xffffffff + + // CORE_1_DRAM0_EXCEPTION_MONITOR_3: Core1 bus busy status regsiter + // Position of CORE_1_DRAM0_RECORDING_ADDR_1 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_ADDR_1_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_RECORDING_ADDR_1 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_ADDR_1_Msk = 0x3fffff + // Position of CORE_1_DRAM0_RECORDING_WR_1 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1_Pos = 0x16 + // Bit mask of CORE_1_DRAM0_RECORDING_WR_1 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1_Msk = 0x400000 + // Bit CORE_1_DRAM0_RECORDING_WR_1. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1 = 0x400000 + + // CORE_1_DRAM0_EXCEPTION_MONITOR_4: Core1 bus busy status regsiter + // Position of CORE_1_DRAM0_RECORDING_BYTEEN_1 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_BYTEEN_1_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_RECORDING_BYTEEN_1 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_BYTEEN_1_Msk = 0xffff + + // CORE_1_DRAM0_EXCEPTION_MONITOR_5: Core1 bus busy status regsiter + // Position of CORE_1_DRAM0_RECORDING_PC_1 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_5_CORE_1_DRAM0_RECORDING_PC_1_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_RECORDING_PC_1 field. + DEBUG_ASSIST_CORE_1_DRAM0_EXCEPTION_MONITOR_5_CORE_1_DRAM0_RECORDING_PC_1_Msk = 0xffffffff + + // CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: bus busy configuration register + // Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field. + DEBUG_ASSIST_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field. + DEBUG_ASSIST_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Msk = 0xfffff + + // CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: bus busy configuration register + // Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field. + DEBUG_ASSIST_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field. + DEBUG_ASSIST_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Msk = 0xfffff + + // LOG_SETTING: log set register + // Position of LOG_ENA field. + DEBUG_ASSIST_LOG_SETTING_LOG_ENA_Pos = 0x0 + // Bit mask of LOG_ENA field. + DEBUG_ASSIST_LOG_SETTING_LOG_ENA_Msk = 0x7 + // Position of LOG_MODE field. + DEBUG_ASSIST_LOG_SETTING_LOG_MODE_Pos = 0x3 + // Bit mask of LOG_MODE field. + DEBUG_ASSIST_LOG_SETTING_LOG_MODE_Msk = 0x38 + // Position of LOG_MEM_LOOP_ENABLE field. + DEBUG_ASSIST_LOG_SETTING_LOG_MEM_LOOP_ENABLE_Pos = 0x6 + // Bit mask of LOG_MEM_LOOP_ENABLE field. + DEBUG_ASSIST_LOG_SETTING_LOG_MEM_LOOP_ENABLE_Msk = 0x40 + // Bit LOG_MEM_LOOP_ENABLE. + DEBUG_ASSIST_LOG_SETTING_LOG_MEM_LOOP_ENABLE = 0x40 + + // LOG_DATA_0: log check data register + // Position of LOG_DATA_0 field. + DEBUG_ASSIST_LOG_DATA_0_LOG_DATA_0_Pos = 0x0 + // Bit mask of LOG_DATA_0 field. + DEBUG_ASSIST_LOG_DATA_0_LOG_DATA_0_Msk = 0xffffffff + + // LOG_DATA_1: log check data register + // Position of LOG_DATA_1 field. + DEBUG_ASSIST_LOG_DATA_1_LOG_DATA_1_Pos = 0x0 + // Bit mask of LOG_DATA_1 field. + DEBUG_ASSIST_LOG_DATA_1_LOG_DATA_1_Msk = 0xffffffff + + // LOG_DATA_2: log check data register + // Position of LOG_DATA_2 field. + DEBUG_ASSIST_LOG_DATA_2_LOG_DATA_2_Pos = 0x0 + // Bit mask of LOG_DATA_2 field. + DEBUG_ASSIST_LOG_DATA_2_LOG_DATA_2_Msk = 0xffffffff + + // LOG_DATA_3: log check data register + // Position of LOG_DATA_3 field. + DEBUG_ASSIST_LOG_DATA_3_LOG_DATA_3_Pos = 0x0 + // Bit mask of LOG_DATA_3 field. + DEBUG_ASSIST_LOG_DATA_3_LOG_DATA_3_Msk = 0xffffffff + + // LOG_DATA_MASK: log check data mask register + // Position of LOG_DATA_SIZE field. + DEBUG_ASSIST_LOG_DATA_MASK_LOG_DATA_SIZE_Pos = 0x0 + // Bit mask of LOG_DATA_SIZE field. + DEBUG_ASSIST_LOG_DATA_MASK_LOG_DATA_SIZE_Msk = 0xffff + + // LOG_MIN: log check region configuration register + // Position of LOG_MIN field. + DEBUG_ASSIST_LOG_MIN_LOG_MIN_Pos = 0x0 + // Bit mask of LOG_MIN field. + DEBUG_ASSIST_LOG_MIN_LOG_MIN_Msk = 0xffffffff + + // LOG_MAX: log check region configuration register + // Position of LOG_MAX field. + DEBUG_ASSIST_LOG_MAX_LOG_MAX_Pos = 0x0 + // Bit mask of LOG_MAX field. + DEBUG_ASSIST_LOG_MAX_LOG_MAX_Msk = 0xffffffff + + // LOG_MEM_START: log mem region configuration register + // Position of LOG_MEM_START field. + DEBUG_ASSIST_LOG_MEM_START_LOG_MEM_START_Pos = 0x0 + // Bit mask of LOG_MEM_START field. + DEBUG_ASSIST_LOG_MEM_START_LOG_MEM_START_Msk = 0xffffffff + + // LOG_MEM_END: log mem region configuration register + // Position of LOG_MEM_END field. + DEBUG_ASSIST_LOG_MEM_END_LOG_MEM_END_Pos = 0x0 + // Bit mask of LOG_MEM_END field. + DEBUG_ASSIST_LOG_MEM_END_LOG_MEM_END_Msk = 0xffffffff + + // LOG_MEM_WRITING_ADDR: log mem addr status register + // Position of LOG_MEM_WRITING_ADDR field. + DEBUG_ASSIST_LOG_MEM_WRITING_ADDR_LOG_MEM_WRITING_ADDR_Pos = 0x0 + // Bit mask of LOG_MEM_WRITING_ADDR field. + DEBUG_ASSIST_LOG_MEM_WRITING_ADDR_LOG_MEM_WRITING_ADDR_Msk = 0xffffffff + + // LOG_MEM_FULL_FLAG: log mem status register + // Position of LOG_MEM_FULL_FLAG field. + DEBUG_ASSIST_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG_Pos = 0x0 + // Bit mask of LOG_MEM_FULL_FLAG field. + DEBUG_ASSIST_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG_Msk = 0x1 + // Bit LOG_MEM_FULL_FLAG. + DEBUG_ASSIST_LOG_MEM_FULL_FLAG_LOG_MEM_FULL_FLAG = 0x1 + + // DATE: version register + // Position of DATE field. + DEBUG_ASSIST_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DEBUG_ASSIST_DATE_DATE_Msk = 0xfffffff +) + +// Constants for DMA: DMA (Direct Memory Access) Controller +const ( + // IN_CONF0_CH0: Configure 0 register of Rx channel 0 + // Position of IN_RST field. + DMA_IN_CONF0_CH_IN_RST_Pos = 0x0 + // Bit mask of IN_RST field. + DMA_IN_CONF0_CH_IN_RST_Msk = 0x1 + // Bit IN_RST. + DMA_IN_CONF0_CH_IN_RST = 0x1 + // Position of IN_LOOP_TEST field. + DMA_IN_CONF0_CH_IN_LOOP_TEST_Pos = 0x1 + // Bit mask of IN_LOOP_TEST field. + DMA_IN_CONF0_CH_IN_LOOP_TEST_Msk = 0x2 + // Bit IN_LOOP_TEST. + DMA_IN_CONF0_CH_IN_LOOP_TEST = 0x2 + // Position of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH_INDSCR_BURST_EN_Pos = 0x2 + // Bit mask of INDSCR_BURST_EN field. + DMA_IN_CONF0_CH_INDSCR_BURST_EN_Msk = 0x4 + // Bit INDSCR_BURST_EN. + DMA_IN_CONF0_CH_INDSCR_BURST_EN = 0x4 + // Position of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH_IN_DATA_BURST_EN_Pos = 0x3 + // Bit mask of IN_DATA_BURST_EN field. + DMA_IN_CONF0_CH_IN_DATA_BURST_EN_Msk = 0x8 + // Bit IN_DATA_BURST_EN. + DMA_IN_CONF0_CH_IN_DATA_BURST_EN = 0x8 + // Position of MEM_TRANS_EN field. + DMA_IN_CONF0_CH_MEM_TRANS_EN_Pos = 0x4 + // Bit mask of MEM_TRANS_EN field. + DMA_IN_CONF0_CH_MEM_TRANS_EN_Msk = 0x10 + // Bit MEM_TRANS_EN. + DMA_IN_CONF0_CH_MEM_TRANS_EN = 0x10 + + // IN_CONF1_CH0: Configure 1 register of Rx channel 0 + // Position of DMA_INFIFO_FULL_THRS field. + DMA_IN_CONF1_CH_DMA_INFIFO_FULL_THRS_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_THRS field. + DMA_IN_CONF1_CH_DMA_INFIFO_FULL_THRS_Msk = 0xfff + // Position of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH_IN_CHECK_OWNER_Pos = 0xc + // Bit mask of IN_CHECK_OWNER field. + DMA_IN_CONF1_CH_IN_CHECK_OWNER_Msk = 0x1000 + // Bit IN_CHECK_OWNER. + DMA_IN_CONF1_CH_IN_CHECK_OWNER = 0x1000 + // Position of IN_EXT_MEM_BK_SIZE field. + DMA_IN_CONF1_CH_IN_EXT_MEM_BK_SIZE_Pos = 0xd + // Bit mask of IN_EXT_MEM_BK_SIZE field. + DMA_IN_CONF1_CH_IN_EXT_MEM_BK_SIZE_Msk = 0x6000 + + // IN_INT_RAW_CH0: Raw status interrupt of Rx channel 0 + // Position of IN_DONE field. + DMA_IN_INT_RAW_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_RAW_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_RAW_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_RAW_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_RAW_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_RAW_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_RAW_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_RAW_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_RAW_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_RAW_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_RAW_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_RAW_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_FULL_WM field. + DMA_IN_INT_RAW_CH_INFIFO_FULL_WM_Pos = 0x5 + // Bit mask of INFIFO_FULL_WM field. + DMA_IN_INT_RAW_CH_INFIFO_FULL_WM_Msk = 0x20 + // Bit INFIFO_FULL_WM. + DMA_IN_INT_RAW_CH_INFIFO_FULL_WM = 0x20 + // Position of INFIFO_OVF_L1 field. + DMA_IN_INT_RAW_CH_INFIFO_OVF_L1_Pos = 0x6 + // Bit mask of INFIFO_OVF_L1 field. + DMA_IN_INT_RAW_CH_INFIFO_OVF_L1_Msk = 0x40 + // Bit INFIFO_OVF_L1. + DMA_IN_INT_RAW_CH_INFIFO_OVF_L1 = 0x40 + // Position of INFIFO_UDF_L1 field. + DMA_IN_INT_RAW_CH_INFIFO_UDF_L1_Pos = 0x7 + // Bit mask of INFIFO_UDF_L1 field. + DMA_IN_INT_RAW_CH_INFIFO_UDF_L1_Msk = 0x80 + // Bit INFIFO_UDF_L1. + DMA_IN_INT_RAW_CH_INFIFO_UDF_L1 = 0x80 + // Position of INFIFO_OVF_L3 field. + DMA_IN_INT_RAW_CH_INFIFO_OVF_L3_Pos = 0x8 + // Bit mask of INFIFO_OVF_L3 field. + DMA_IN_INT_RAW_CH_INFIFO_OVF_L3_Msk = 0x100 + // Bit INFIFO_OVF_L3. + DMA_IN_INT_RAW_CH_INFIFO_OVF_L3 = 0x100 + // Position of INFIFO_UDF_L3 field. + DMA_IN_INT_RAW_CH_INFIFO_UDF_L3_Pos = 0x9 + // Bit mask of INFIFO_UDF_L3 field. + DMA_IN_INT_RAW_CH_INFIFO_UDF_L3_Msk = 0x200 + // Bit INFIFO_UDF_L3. + DMA_IN_INT_RAW_CH_INFIFO_UDF_L3 = 0x200 + + // IN_INT_ST_CH0: Masked interrupt of Rx channel 0 + // Position of IN_DONE field. + DMA_IN_INT_ST_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_ST_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_ST_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_ST_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_ST_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_ST_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_ST_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_ST_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_ST_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_ST_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_ST_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_ST_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_ST_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_FULL_WM field. + DMA_IN_INT_ST_CH_INFIFO_FULL_WM_Pos = 0x5 + // Bit mask of INFIFO_FULL_WM field. + DMA_IN_INT_ST_CH_INFIFO_FULL_WM_Msk = 0x20 + // Bit INFIFO_FULL_WM. + DMA_IN_INT_ST_CH_INFIFO_FULL_WM = 0x20 + // Position of INFIFO_OVF_L1 field. + DMA_IN_INT_ST_CH_INFIFO_OVF_L1_Pos = 0x6 + // Bit mask of INFIFO_OVF_L1 field. + DMA_IN_INT_ST_CH_INFIFO_OVF_L1_Msk = 0x40 + // Bit INFIFO_OVF_L1. + DMA_IN_INT_ST_CH_INFIFO_OVF_L1 = 0x40 + // Position of INFIFO_UDF_L1 field. + DMA_IN_INT_ST_CH_INFIFO_UDF_L1_Pos = 0x7 + // Bit mask of INFIFO_UDF_L1 field. + DMA_IN_INT_ST_CH_INFIFO_UDF_L1_Msk = 0x80 + // Bit INFIFO_UDF_L1. + DMA_IN_INT_ST_CH_INFIFO_UDF_L1 = 0x80 + // Position of INFIFO_OVF_L3 field. + DMA_IN_INT_ST_CH_INFIFO_OVF_L3_Pos = 0x8 + // Bit mask of INFIFO_OVF_L3 field. + DMA_IN_INT_ST_CH_INFIFO_OVF_L3_Msk = 0x100 + // Bit INFIFO_OVF_L3. + DMA_IN_INT_ST_CH_INFIFO_OVF_L3 = 0x100 + // Position of INFIFO_UDF_L3 field. + DMA_IN_INT_ST_CH_INFIFO_UDF_L3_Pos = 0x9 + // Bit mask of INFIFO_UDF_L3 field. + DMA_IN_INT_ST_CH_INFIFO_UDF_L3_Msk = 0x200 + // Bit INFIFO_UDF_L3. + DMA_IN_INT_ST_CH_INFIFO_UDF_L3 = 0x200 + + // IN_INT_ENA_CH0: Interrupt enable bits of Rx channel 0 + // Position of IN_DONE field. + DMA_IN_INT_ENA_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_ENA_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_ENA_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_ENA_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_ENA_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_ENA_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_ENA_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_ENA_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_ENA_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_ENA_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_ENA_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_ENA_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY = 0x10 + // Position of INFIFO_FULL_WM field. + DMA_IN_INT_ENA_CH_INFIFO_FULL_WM_Pos = 0x5 + // Bit mask of INFIFO_FULL_WM field. + DMA_IN_INT_ENA_CH_INFIFO_FULL_WM_Msk = 0x20 + // Bit INFIFO_FULL_WM. + DMA_IN_INT_ENA_CH_INFIFO_FULL_WM = 0x20 + // Position of INFIFO_OVF_L1 field. + DMA_IN_INT_ENA_CH_INFIFO_OVF_L1_Pos = 0x6 + // Bit mask of INFIFO_OVF_L1 field. + DMA_IN_INT_ENA_CH_INFIFO_OVF_L1_Msk = 0x40 + // Bit INFIFO_OVF_L1. + DMA_IN_INT_ENA_CH_INFIFO_OVF_L1 = 0x40 + // Position of INFIFO_UDF_L1 field. + DMA_IN_INT_ENA_CH_INFIFO_UDF_L1_Pos = 0x7 + // Bit mask of INFIFO_UDF_L1 field. + DMA_IN_INT_ENA_CH_INFIFO_UDF_L1_Msk = 0x80 + // Bit INFIFO_UDF_L1. + DMA_IN_INT_ENA_CH_INFIFO_UDF_L1 = 0x80 + // Position of INFIFO_OVF_L3 field. + DMA_IN_INT_ENA_CH_INFIFO_OVF_L3_Pos = 0x8 + // Bit mask of INFIFO_OVF_L3 field. + DMA_IN_INT_ENA_CH_INFIFO_OVF_L3_Msk = 0x100 + // Bit INFIFO_OVF_L3. + DMA_IN_INT_ENA_CH_INFIFO_OVF_L3 = 0x100 + // Position of INFIFO_UDF_L3 field. + DMA_IN_INT_ENA_CH_INFIFO_UDF_L3_Pos = 0x9 + // Bit mask of INFIFO_UDF_L3 field. + DMA_IN_INT_ENA_CH_INFIFO_UDF_L3_Msk = 0x200 + // Bit INFIFO_UDF_L3. + DMA_IN_INT_ENA_CH_INFIFO_UDF_L3 = 0x200 + + // IN_INT_CLR_CH0: Interrupt clear bits of Rx channel 0 + // Position of IN_DONE field. + DMA_IN_INT_CLR_CH_IN_DONE_Pos = 0x0 + // Bit mask of IN_DONE field. + DMA_IN_INT_CLR_CH_IN_DONE_Msk = 0x1 + // Bit IN_DONE. + DMA_IN_INT_CLR_CH_IN_DONE = 0x1 + // Position of IN_SUC_EOF field. + DMA_IN_INT_CLR_CH_IN_SUC_EOF_Pos = 0x1 + // Bit mask of IN_SUC_EOF field. + DMA_IN_INT_CLR_CH_IN_SUC_EOF_Msk = 0x2 + // Bit IN_SUC_EOF. + DMA_IN_INT_CLR_CH_IN_SUC_EOF = 0x2 + // Position of IN_ERR_EOF field. + DMA_IN_INT_CLR_CH_IN_ERR_EOF_Pos = 0x2 + // Bit mask of IN_ERR_EOF field. + DMA_IN_INT_CLR_CH_IN_ERR_EOF_Msk = 0x4 + // Bit IN_ERR_EOF. + DMA_IN_INT_CLR_CH_IN_ERR_EOF = 0x4 + // Position of IN_DSCR_ERR field. + DMA_IN_INT_CLR_CH_IN_DSCR_ERR_Pos = 0x3 + // Bit mask of IN_DSCR_ERR field. + DMA_IN_INT_CLR_CH_IN_DSCR_ERR_Msk = 0x8 + // Bit IN_DSCR_ERR. + DMA_IN_INT_CLR_CH_IN_DSCR_ERR = 0x8 + // Position of IN_DSCR_EMPTY field. + DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_Pos = 0x4 + // Bit mask of IN_DSCR_EMPTY field. + DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_Msk = 0x10 + // Bit IN_DSCR_EMPTY. + DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY = 0x10 + // Position of DMA_INFIFO_FULL_WM field. + DMA_IN_INT_CLR_CH_DMA_INFIFO_FULL_WM_Pos = 0x5 + // Bit mask of DMA_INFIFO_FULL_WM field. + DMA_IN_INT_CLR_CH_DMA_INFIFO_FULL_WM_Msk = 0x20 + // Bit DMA_INFIFO_FULL_WM. + DMA_IN_INT_CLR_CH_DMA_INFIFO_FULL_WM = 0x20 + // Position of INFIFO_OVF_L1 field. + DMA_IN_INT_CLR_CH_INFIFO_OVF_L1_Pos = 0x6 + // Bit mask of INFIFO_OVF_L1 field. + DMA_IN_INT_CLR_CH_INFIFO_OVF_L1_Msk = 0x40 + // Bit INFIFO_OVF_L1. + DMA_IN_INT_CLR_CH_INFIFO_OVF_L1 = 0x40 + // Position of INFIFO_UDF_L1 field. + DMA_IN_INT_CLR_CH_INFIFO_UDF_L1_Pos = 0x7 + // Bit mask of INFIFO_UDF_L1 field. + DMA_IN_INT_CLR_CH_INFIFO_UDF_L1_Msk = 0x80 + // Bit INFIFO_UDF_L1. + DMA_IN_INT_CLR_CH_INFIFO_UDF_L1 = 0x80 + // Position of INFIFO_OVF_L3 field. + DMA_IN_INT_CLR_CH_INFIFO_OVF_L3_Pos = 0x8 + // Bit mask of INFIFO_OVF_L3 field. + DMA_IN_INT_CLR_CH_INFIFO_OVF_L3_Msk = 0x100 + // Bit INFIFO_OVF_L3. + DMA_IN_INT_CLR_CH_INFIFO_OVF_L3 = 0x100 + // Position of INFIFO_UDF_L3 field. + DMA_IN_INT_CLR_CH_INFIFO_UDF_L3_Pos = 0x9 + // Bit mask of INFIFO_UDF_L3 field. + DMA_IN_INT_CLR_CH_INFIFO_UDF_L3_Msk = 0x200 + // Bit INFIFO_UDF_L3. + DMA_IN_INT_CLR_CH_INFIFO_UDF_L3 = 0x200 + + // INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0 + // Position of INFIFO_FULL_L1 field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_L1_Pos = 0x0 + // Bit mask of INFIFO_FULL_L1 field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_L1_Msk = 0x1 + // Bit INFIFO_FULL_L1. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_L1 = 0x1 + // Position of INFIFO_EMPTY_L1 field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_L1_Pos = 0x1 + // Bit mask of INFIFO_EMPTY_L1 field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_L1_Msk = 0x2 + // Bit INFIFO_EMPTY_L1. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_L1 = 0x2 + // Position of INFIFO_FULL_L2 field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_L2_Pos = 0x2 + // Bit mask of INFIFO_FULL_L2 field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_L2_Msk = 0x4 + // Bit INFIFO_FULL_L2. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_L2 = 0x4 + // Position of INFIFO_EMPTY_L2 field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_L2_Pos = 0x3 + // Bit mask of INFIFO_EMPTY_L2 field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_L2_Msk = 0x8 + // Bit INFIFO_EMPTY_L2. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_L2 = 0x8 + // Position of INFIFO_FULL_L3 field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_L3_Pos = 0x4 + // Bit mask of INFIFO_FULL_L3 field. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_L3_Msk = 0x10 + // Bit INFIFO_FULL_L3. + DMA_INFIFO_STATUS_CH_INFIFO_FULL_L3 = 0x10 + // Position of INFIFO_EMPTY_L3 field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_L3_Pos = 0x5 + // Bit mask of INFIFO_EMPTY_L3 field. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_L3_Msk = 0x20 + // Bit INFIFO_EMPTY_L3. + DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_L3 = 0x20 + // Position of INFIFO_CNT_L1 field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_L1_Pos = 0x6 + // Bit mask of INFIFO_CNT_L1 field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_L1_Msk = 0xfc0 + // Position of INFIFO_CNT_L2 field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_L2_Pos = 0xc + // Bit mask of INFIFO_CNT_L2 field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_L2_Msk = 0x7f000 + // Position of INFIFO_CNT_L3 field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_L3_Pos = 0x13 + // Bit mask of INFIFO_CNT_L3 field. + DMA_INFIFO_STATUS_CH_INFIFO_CNT_L3_Msk = 0xf80000 + // Position of IN_REMAIN_UNDER_1B_L3 field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_L3_Pos = 0x18 + // Bit mask of IN_REMAIN_UNDER_1B_L3 field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_L3_Msk = 0x1000000 + // Bit IN_REMAIN_UNDER_1B_L3. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_L3 = 0x1000000 + // Position of IN_REMAIN_UNDER_2B_L3 field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_L3_Pos = 0x19 + // Bit mask of IN_REMAIN_UNDER_2B_L3 field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_L3_Msk = 0x2000000 + // Bit IN_REMAIN_UNDER_2B_L3. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_L3 = 0x2000000 + // Position of IN_REMAIN_UNDER_3B_L3 field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_L3_Pos = 0x1a + // Bit mask of IN_REMAIN_UNDER_3B_L3 field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_L3_Msk = 0x4000000 + // Bit IN_REMAIN_UNDER_3B_L3. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_L3 = 0x4000000 + // Position of IN_REMAIN_UNDER_4B_L3 field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_L3_Pos = 0x1b + // Bit mask of IN_REMAIN_UNDER_4B_L3 field. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_L3_Msk = 0x8000000 + // Bit IN_REMAIN_UNDER_4B_L3. + DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_L3 = 0x8000000 + // Position of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_Pos = 0x1c + // Bit mask of IN_BUF_HUNGRY field. + DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_Msk = 0x10000000 + // Bit IN_BUF_HUNGRY. + DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY = 0x10000000 + + // IN_POP_CH0: Pop control register of Rx channel 0 + // Position of INFIFO_RDATA field. + DMA_IN_POP_CH_INFIFO_RDATA_Pos = 0x0 + // Bit mask of INFIFO_RDATA field. + DMA_IN_POP_CH_INFIFO_RDATA_Msk = 0xfff + // Position of INFIFO_POP field. + DMA_IN_POP_CH_INFIFO_POP_Pos = 0xc + // Bit mask of INFIFO_POP field. + DMA_IN_POP_CH_INFIFO_POP_Msk = 0x1000 + // Bit INFIFO_POP. + DMA_IN_POP_CH_INFIFO_POP = 0x1000 + + // IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0 + // Position of INLINK_ADDR field. + DMA_IN_LINK_CH_INLINK_ADDR_Pos = 0x0 + // Bit mask of INLINK_ADDR field. + DMA_IN_LINK_CH_INLINK_ADDR_Msk = 0xfffff + // Position of INLINK_AUTO_RET field. + DMA_IN_LINK_CH_INLINK_AUTO_RET_Pos = 0x14 + // Bit mask of INLINK_AUTO_RET field. + DMA_IN_LINK_CH_INLINK_AUTO_RET_Msk = 0x100000 + // Bit INLINK_AUTO_RET. + DMA_IN_LINK_CH_INLINK_AUTO_RET = 0x100000 + // Position of INLINK_STOP field. + DMA_IN_LINK_CH_INLINK_STOP_Pos = 0x15 + // Bit mask of INLINK_STOP field. + DMA_IN_LINK_CH_INLINK_STOP_Msk = 0x200000 + // Bit INLINK_STOP. + DMA_IN_LINK_CH_INLINK_STOP = 0x200000 + // Position of INLINK_START field. + DMA_IN_LINK_CH_INLINK_START_Pos = 0x16 + // Bit mask of INLINK_START field. + DMA_IN_LINK_CH_INLINK_START_Msk = 0x400000 + // Bit INLINK_START. + DMA_IN_LINK_CH_INLINK_START = 0x400000 + // Position of INLINK_RESTART field. + DMA_IN_LINK_CH_INLINK_RESTART_Pos = 0x17 + // Bit mask of INLINK_RESTART field. + DMA_IN_LINK_CH_INLINK_RESTART_Msk = 0x800000 + // Bit INLINK_RESTART. + DMA_IN_LINK_CH_INLINK_RESTART = 0x800000 + // Position of INLINK_PARK field. + DMA_IN_LINK_CH_INLINK_PARK_Pos = 0x18 + // Bit mask of INLINK_PARK field. + DMA_IN_LINK_CH_INLINK_PARK_Msk = 0x1000000 + // Bit INLINK_PARK. + DMA_IN_LINK_CH_INLINK_PARK = 0x1000000 + + // IN_STATE_CH0: Receive status of Rx channel 0 + // Position of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH_INLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of INLINK_DSCR_ADDR field. + DMA_IN_STATE_CH_INLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of IN_DSCR_STATE field. + DMA_IN_STATE_CH_IN_DSCR_STATE_Pos = 0x12 + // Bit mask of IN_DSCR_STATE field. + DMA_IN_STATE_CH_IN_DSCR_STATE_Msk = 0xc0000 + // Position of IN_STATE field. + DMA_IN_STATE_CH_IN_STATE_Pos = 0x14 + // Bit mask of IN_STATE field. + DMA_IN_STATE_CH_IN_STATE_Msk = 0x700000 + + // IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0 + // Position of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_SUC_EOF_DES_ADDR field. + DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0 + // Position of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of IN_ERR_EOF_DES_ADDR field. + DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_Msk = 0xffffffff + + // IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR field. + DMA_IN_DSCR_CH_INLINK_DSCR_Pos = 0x0 + // Bit mask of INLINK_DSCR field. + DMA_IN_DSCR_CH_INLINK_DSCR_Msk = 0xffffffff + + // IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF0 field. + DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_Msk = 0xffffffff + + // IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0 + // Position of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of INLINK_DSCR_BF1 field. + DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_Msk = 0xffffffff + + // IN_WIGHT_CH0: Weight register of Rx channel 0 + // Position of RX_WEIGHT field. + DMA_IN_WIGHT_CH_RX_WEIGHT_Pos = 0x8 + // Bit mask of RX_WEIGHT field. + DMA_IN_WIGHT_CH_RX_WEIGHT_Msk = 0xf00 + + // IN_PRI_CH0: Priority register of Rx channel 0 + // Position of RX_PRI field. + DMA_IN_PRI_CH_RX_PRI_Pos = 0x0 + // Bit mask of RX_PRI field. + DMA_IN_PRI_CH_RX_PRI_Msk = 0xf + + // IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0 + // Position of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH_PERI_IN_SEL_Pos = 0x0 + // Bit mask of PERI_IN_SEL field. + DMA_IN_PERI_SEL_CH_PERI_IN_SEL_Msk = 0x3f + + // OUT_CONF0_CH0: Configure 0 register of Tx channel 0 + // Position of OUT_RST field. + DMA_OUT_CONF0_CH_OUT_RST_Pos = 0x0 + // Bit mask of OUT_RST field. + DMA_OUT_CONF0_CH_OUT_RST_Msk = 0x1 + // Bit OUT_RST. + DMA_OUT_CONF0_CH_OUT_RST = 0x1 + // Position of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH_OUT_LOOP_TEST_Pos = 0x1 + // Bit mask of OUT_LOOP_TEST field. + DMA_OUT_CONF0_CH_OUT_LOOP_TEST_Msk = 0x2 + // Bit OUT_LOOP_TEST. + DMA_OUT_CONF0_CH_OUT_LOOP_TEST = 0x2 + // Position of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_Pos = 0x2 + // Bit mask of OUT_AUTO_WRBACK field. + DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_Msk = 0x4 + // Bit OUT_AUTO_WRBACK. + DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK = 0x4 + // Position of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH_OUT_EOF_MODE_Pos = 0x3 + // Bit mask of OUT_EOF_MODE field. + DMA_OUT_CONF0_CH_OUT_EOF_MODE_Msk = 0x8 + // Bit OUT_EOF_MODE. + DMA_OUT_CONF0_CH_OUT_EOF_MODE = 0x8 + // Position of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_Pos = 0x4 + // Bit mask of OUTDSCR_BURST_EN field. + DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_Msk = 0x10 + // Bit OUTDSCR_BURST_EN. + DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN = 0x10 + // Position of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_Pos = 0x5 + // Bit mask of OUT_DATA_BURST_EN field. + DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_Msk = 0x20 + // Bit OUT_DATA_BURST_EN. + DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN = 0x20 + + // OUT_CONF1_CH0: Configure 1 register of Tx channel 0 + // Position of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_Pos = 0xc + // Bit mask of OUT_CHECK_OWNER field. + DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_Msk = 0x1000 + // Bit OUT_CHECK_OWNER. + DMA_OUT_CONF1_CH_OUT_CHECK_OWNER = 0x1000 + // Position of OUT_EXT_MEM_BK_SIZE field. + DMA_OUT_CONF1_CH_OUT_EXT_MEM_BK_SIZE_Pos = 0xd + // Bit mask of OUT_EXT_MEM_BK_SIZE field. + DMA_OUT_CONF1_CH_OUT_EXT_MEM_BK_SIZE_Msk = 0x6000 + + // OUT_INT_RAW_CH0: Raw status interrupt of Tx channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_RAW_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_RAW_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_RAW_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_RAW_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_RAW_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_RAW_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF_L1 field. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_L1_Pos = 0x4 + // Bit mask of OUTFIFO_OVF_L1 field. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_L1_Msk = 0x10 + // Bit OUTFIFO_OVF_L1. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_L1 = 0x10 + // Position of OUTFIFO_UDF_L1 field. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_L1_Pos = 0x5 + // Bit mask of OUTFIFO_UDF_L1 field. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_L1_Msk = 0x20 + // Bit OUTFIFO_UDF_L1. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_L1 = 0x20 + // Position of OUTFIFO_OVF_L3 field. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_L3_Pos = 0x6 + // Bit mask of OUTFIFO_OVF_L3 field. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_L3_Msk = 0x40 + // Bit OUTFIFO_OVF_L3. + DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_L3 = 0x40 + // Position of OUTFIFO_UDF_L3 field. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_L3_Pos = 0x7 + // Bit mask of OUTFIFO_UDF_L3 field. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_L3_Msk = 0x80 + // Bit OUTFIFO_UDF_L3. + DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_L3 = 0x80 + + // OUT_INT_ST_CH0: Masked interrupt of Tx channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_ST_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_ST_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_ST_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_ST_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_ST_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_ST_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_ST_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF_L1 field. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_L1_Pos = 0x4 + // Bit mask of OUTFIFO_OVF_L1 field. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_L1_Msk = 0x10 + // Bit OUTFIFO_OVF_L1. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_L1 = 0x10 + // Position of OUTFIFO_UDF_L1 field. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_L1_Pos = 0x5 + // Bit mask of OUTFIFO_UDF_L1 field. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_L1_Msk = 0x20 + // Bit OUTFIFO_UDF_L1. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_L1 = 0x20 + // Position of OUTFIFO_OVF_L3 field. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_L3_Pos = 0x6 + // Bit mask of OUTFIFO_OVF_L3 field. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_L3_Msk = 0x40 + // Bit OUTFIFO_OVF_L3. + DMA_OUT_INT_ST_CH_OUTFIFO_OVF_L3 = 0x40 + // Position of OUTFIFO_UDF_L3 field. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_L3_Pos = 0x7 + // Bit mask of OUTFIFO_UDF_L3 field. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_L3_Msk = 0x80 + // Bit OUTFIFO_UDF_L3. + DMA_OUT_INT_ST_CH_OUTFIFO_UDF_L3 = 0x80 + + // OUT_INT_ENA_CH0: Interrupt enable bits of Tx channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_ENA_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_ENA_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_ENA_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_ENA_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_ENA_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_ENA_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF_L1 field. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_L1_Pos = 0x4 + // Bit mask of OUTFIFO_OVF_L1 field. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_L1_Msk = 0x10 + // Bit OUTFIFO_OVF_L1. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_L1 = 0x10 + // Position of OUTFIFO_UDF_L1 field. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_L1_Pos = 0x5 + // Bit mask of OUTFIFO_UDF_L1 field. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_L1_Msk = 0x20 + // Bit OUTFIFO_UDF_L1. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_L1 = 0x20 + // Position of OUTFIFO_OVF_L3 field. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_L3_Pos = 0x6 + // Bit mask of OUTFIFO_OVF_L3 field. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_L3_Msk = 0x40 + // Bit OUTFIFO_OVF_L3. + DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_L3 = 0x40 + // Position of OUTFIFO_UDF_L3 field. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_L3_Pos = 0x7 + // Bit mask of OUTFIFO_UDF_L3 field. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_L3_Msk = 0x80 + // Bit OUTFIFO_UDF_L3. + DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_L3 = 0x80 + + // OUT_INT_CLR_CH0: Interrupt clear bits of Tx channel 0 + // Position of OUT_DONE field. + DMA_OUT_INT_CLR_CH_OUT_DONE_Pos = 0x0 + // Bit mask of OUT_DONE field. + DMA_OUT_INT_CLR_CH_OUT_DONE_Msk = 0x1 + // Bit OUT_DONE. + DMA_OUT_INT_CLR_CH_OUT_DONE = 0x1 + // Position of OUT_EOF field. + DMA_OUT_INT_CLR_CH_OUT_EOF_Pos = 0x1 + // Bit mask of OUT_EOF field. + DMA_OUT_INT_CLR_CH_OUT_EOF_Msk = 0x2 + // Bit OUT_EOF. + DMA_OUT_INT_CLR_CH_OUT_EOF = 0x2 + // Position of OUT_DSCR_ERR field. + DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_Pos = 0x2 + // Bit mask of OUT_DSCR_ERR field. + DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_Msk = 0x4 + // Bit OUT_DSCR_ERR. + DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR = 0x4 + // Position of OUT_TOTAL_EOF field. + DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_Pos = 0x3 + // Bit mask of OUT_TOTAL_EOF field. + DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_Msk = 0x8 + // Bit OUT_TOTAL_EOF. + DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF = 0x8 + // Position of OUTFIFO_OVF_L1 field. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_L1_Pos = 0x4 + // Bit mask of OUTFIFO_OVF_L1 field. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_L1_Msk = 0x10 + // Bit OUTFIFO_OVF_L1. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_L1 = 0x10 + // Position of OUTFIFO_UDF_L1 field. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_L1_Pos = 0x5 + // Bit mask of OUTFIFO_UDF_L1 field. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_L1_Msk = 0x20 + // Bit OUTFIFO_UDF_L1. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_L1 = 0x20 + // Position of OUTFIFO_OVF_L3 field. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_L3_Pos = 0x6 + // Bit mask of OUTFIFO_OVF_L3 field. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_L3_Msk = 0x40 + // Bit OUTFIFO_OVF_L3. + DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_L3 = 0x40 + // Position of OUTFIFO_UDF_L3 field. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_L3_Pos = 0x7 + // Bit mask of OUTFIFO_UDF_L3 field. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_L3_Msk = 0x80 + // Bit OUTFIFO_UDF_L3. + DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_L3 = 0x80 + + // OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0 + // Position of OUTFIFO_FULL_L1 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_L1_Pos = 0x0 + // Bit mask of OUTFIFO_FULL_L1 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_L1_Msk = 0x1 + // Bit OUTFIFO_FULL_L1. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_L1 = 0x1 + // Position of OUTFIFO_EMPTY_L1 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_L1_Pos = 0x1 + // Bit mask of OUTFIFO_EMPTY_L1 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_L1_Msk = 0x2 + // Bit OUTFIFO_EMPTY_L1. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_L1 = 0x2 + // Position of OUTFIFO_FULL_L2 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_L2_Pos = 0x2 + // Bit mask of OUTFIFO_FULL_L2 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_L2_Msk = 0x4 + // Bit OUTFIFO_FULL_L2. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_L2 = 0x4 + // Position of OUTFIFO_EMPTY_L2 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_L2_Pos = 0x3 + // Bit mask of OUTFIFO_EMPTY_L2 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_L2_Msk = 0x8 + // Bit OUTFIFO_EMPTY_L2. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_L2 = 0x8 + // Position of OUTFIFO_FULL_L3 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_L3_Pos = 0x4 + // Bit mask of OUTFIFO_FULL_L3 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_L3_Msk = 0x10 + // Bit OUTFIFO_FULL_L3. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_L3 = 0x10 + // Position of OUTFIFO_EMPTY_L3 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_L3_Pos = 0x5 + // Bit mask of OUTFIFO_EMPTY_L3 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_L3_Msk = 0x20 + // Bit OUTFIFO_EMPTY_L3. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_L3 = 0x20 + // Position of OUTFIFO_CNT_L1 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_L1_Pos = 0x6 + // Bit mask of OUTFIFO_CNT_L1 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_L1_Msk = 0x7c0 + // Position of OUTFIFO_CNT_L2 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_L2_Pos = 0xb + // Bit mask of OUTFIFO_CNT_L2 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_L2_Msk = 0x3f800 + // Position of OUTFIFO_CNT_L3 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_L3_Pos = 0x12 + // Bit mask of OUTFIFO_CNT_L3 field. + DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_L3_Msk = 0x7c0000 + // Position of OUT_REMAIN_UNDER_1B_L3 field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_L3_Pos = 0x17 + // Bit mask of OUT_REMAIN_UNDER_1B_L3 field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_L3_Msk = 0x800000 + // Bit OUT_REMAIN_UNDER_1B_L3. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_L3 = 0x800000 + // Position of OUT_REMAIN_UNDER_2B_L3 field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_L3_Pos = 0x18 + // Bit mask of OUT_REMAIN_UNDER_2B_L3 field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_L3_Msk = 0x1000000 + // Bit OUT_REMAIN_UNDER_2B_L3. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_L3 = 0x1000000 + // Position of OUT_REMAIN_UNDER_3B_L3 field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_L3_Pos = 0x19 + // Bit mask of OUT_REMAIN_UNDER_3B_L3 field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_L3_Msk = 0x2000000 + // Bit OUT_REMAIN_UNDER_3B_L3. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_L3 = 0x2000000 + // Position of OUT_REMAIN_UNDER_4B_L3 field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_L3_Pos = 0x1a + // Bit mask of OUT_REMAIN_UNDER_4B_L3 field. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_L3_Msk = 0x4000000 + // Bit OUT_REMAIN_UNDER_4B_L3. + DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_L3 = 0x4000000 + + // OUT_PUSH_CH0: Push control register of Rx channel 0 + // Position of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH_OUTFIFO_WDATA_Pos = 0x0 + // Bit mask of OUTFIFO_WDATA field. + DMA_OUT_PUSH_CH_OUTFIFO_WDATA_Msk = 0x1ff + // Position of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH_OUTFIFO_PUSH_Pos = 0x9 + // Bit mask of OUTFIFO_PUSH field. + DMA_OUT_PUSH_CH_OUTFIFO_PUSH_Msk = 0x200 + // Bit OUTFIFO_PUSH. + DMA_OUT_PUSH_CH_OUTFIFO_PUSH = 0x200 + + // OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0 + // Position of OUTLINK_ADDR field. + DMA_OUT_LINK_CH_OUTLINK_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_ADDR field. + DMA_OUT_LINK_CH_OUTLINK_ADDR_Msk = 0xfffff + // Position of OUTLINK_STOP field. + DMA_OUT_LINK_CH_OUTLINK_STOP_Pos = 0x14 + // Bit mask of OUTLINK_STOP field. + DMA_OUT_LINK_CH_OUTLINK_STOP_Msk = 0x100000 + // Bit OUTLINK_STOP. + DMA_OUT_LINK_CH_OUTLINK_STOP = 0x100000 + // Position of OUTLINK_START field. + DMA_OUT_LINK_CH_OUTLINK_START_Pos = 0x15 + // Bit mask of OUTLINK_START field. + DMA_OUT_LINK_CH_OUTLINK_START_Msk = 0x200000 + // Bit OUTLINK_START. + DMA_OUT_LINK_CH_OUTLINK_START = 0x200000 + // Position of OUTLINK_RESTART field. + DMA_OUT_LINK_CH_OUTLINK_RESTART_Pos = 0x16 + // Bit mask of OUTLINK_RESTART field. + DMA_OUT_LINK_CH_OUTLINK_RESTART_Msk = 0x400000 + // Bit OUTLINK_RESTART. + DMA_OUT_LINK_CH_OUTLINK_RESTART = 0x400000 + // Position of OUTLINK_PARK field. + DMA_OUT_LINK_CH_OUTLINK_PARK_Pos = 0x17 + // Bit mask of OUTLINK_PARK field. + DMA_OUT_LINK_CH_OUTLINK_PARK_Msk = 0x800000 + // Bit OUTLINK_PARK. + DMA_OUT_LINK_CH_OUTLINK_PARK = 0x800000 + + // OUT_STATE_CH0: Transmit status of Tx channel 0 + // Position of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_ADDR field. + DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_Msk = 0x3ffff + // Position of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH_OUT_DSCR_STATE_Pos = 0x12 + // Bit mask of OUT_DSCR_STATE field. + DMA_OUT_STATE_CH_OUT_DSCR_STATE_Msk = 0xc0000 + // Position of OUT_STATE field. + DMA_OUT_STATE_CH_OUT_STATE_Pos = 0x14 + // Bit mask of OUT_STATE field. + DMA_OUT_STATE_CH_OUT_STATE_Msk = 0x700000 + + // OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0 + // Position of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_DES_ADDR field. + DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_Msk = 0xffffffff + + // OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0 + // Position of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_Pos = 0x0 + // Bit mask of OUT_EOF_BFR_DES_ADDR field. + DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_Msk = 0xffffffff + + // OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH_OUTLINK_DSCR_Pos = 0x0 + // Bit mask of OUTLINK_DSCR field. + DMA_OUT_DSCR_CH_OUTLINK_DSCR_Msk = 0xffffffff + + // OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF0 field. + DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_Msk = 0xffffffff + + // OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0 + // Position of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_Pos = 0x0 + // Bit mask of OUTLINK_DSCR_BF1 field. + DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_Msk = 0xffffffff + + // OUT_WIGHT_CH0: Weight register of Rx channel 0 + // Position of TX_WEIGHT field. + DMA_OUT_WIGHT_CH_TX_WEIGHT_Pos = 0x8 + // Bit mask of TX_WEIGHT field. + DMA_OUT_WIGHT_CH_TX_WEIGHT_Msk = 0xf00 + + // OUT_PRI_CH0: Priority register of Tx channel 0. + // Position of TX_PRI field. + DMA_OUT_PRI_CH_TX_PRI_Pos = 0x0 + // Bit mask of TX_PRI field. + DMA_OUT_PRI_CH_TX_PRI_Msk = 0xf + + // OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0 + // Position of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_Pos = 0x0 + // Bit mask of PERI_OUT_SEL field. + DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_Msk = 0x3f + + // AHB_TEST: reserved + // Position of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Pos = 0x0 + // Bit mask of AHB_TESTMODE field. + DMA_AHB_TEST_AHB_TESTMODE_Msk = 0x7 + // Position of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Pos = 0x4 + // Bit mask of AHB_TESTADDR field. + DMA_AHB_TEST_AHB_TESTADDR_Msk = 0x30 + + // PD_CONF: reserved + // Position of DMA_RAM_FORCE_PD field. + DMA_PD_CONF_DMA_RAM_FORCE_PD_Pos = 0x4 + // Bit mask of DMA_RAM_FORCE_PD field. + DMA_PD_CONF_DMA_RAM_FORCE_PD_Msk = 0x10 + // Bit DMA_RAM_FORCE_PD. + DMA_PD_CONF_DMA_RAM_FORCE_PD = 0x10 + // Position of DMA_RAM_FORCE_PU field. + DMA_PD_CONF_DMA_RAM_FORCE_PU_Pos = 0x5 + // Bit mask of DMA_RAM_FORCE_PU field. + DMA_PD_CONF_DMA_RAM_FORCE_PU_Msk = 0x20 + // Bit DMA_RAM_FORCE_PU. + DMA_PD_CONF_DMA_RAM_FORCE_PU = 0x20 + // Position of DMA_RAM_CLK_FO field. + DMA_PD_CONF_DMA_RAM_CLK_FO_Pos = 0x6 + // Bit mask of DMA_RAM_CLK_FO field. + DMA_PD_CONF_DMA_RAM_CLK_FO_Msk = 0x40 + // Bit DMA_RAM_CLK_FO. + DMA_PD_CONF_DMA_RAM_CLK_FO = 0x40 + + // MISC_CONF: MISC register + // Position of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Pos = 0x0 + // Bit mask of AHBM_RST_INTER field. + DMA_MISC_CONF_AHBM_RST_INTER_Msk = 0x1 + // Bit AHBM_RST_INTER. + DMA_MISC_CONF_AHBM_RST_INTER = 0x1 + // Position of AHBM_RST_EXTER field. + DMA_MISC_CONF_AHBM_RST_EXTER_Pos = 0x1 + // Bit mask of AHBM_RST_EXTER field. + DMA_MISC_CONF_AHBM_RST_EXTER_Msk = 0x2 + // Bit AHBM_RST_EXTER. + DMA_MISC_CONF_AHBM_RST_EXTER = 0x2 + // Position of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Pos = 0x2 + // Bit mask of ARB_PRI_DIS field. + DMA_MISC_CONF_ARB_PRI_DIS_Msk = 0x4 + // Bit ARB_PRI_DIS. + DMA_MISC_CONF_ARB_PRI_DIS = 0x4 + // Position of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Pos = 0x4 + // Bit mask of CLK_EN field. + DMA_MISC_CONF_CLK_EN_Msk = 0x10 + // Bit CLK_EN. + DMA_MISC_CONF_CLK_EN = 0x10 + + // IN_SRAM_SIZE_CH0: Receive L2 FIFO depth of Rx channel 0 + // Position of IN_SIZE field. + DMA_IN_SRAM_SIZE_CH_IN_SIZE_Pos = 0x0 + // Bit mask of IN_SIZE field. + DMA_IN_SRAM_SIZE_CH_IN_SIZE_Msk = 0x7f + + // OUT_SRAM_SIZE_CH0: Transmit L2 FIFO depth of Tx channel 0 + // Position of OUT_SIZE field. + DMA_OUT_SRAM_SIZE_CH_OUT_SIZE_Pos = 0x0 + // Bit mask of OUT_SIZE field. + DMA_OUT_SRAM_SIZE_CH_OUT_SIZE_Msk = 0x7f + + // EXTMEM_REJECT_ADDR: Reject address accessing external RAM + // Position of EXTMEM_REJECT_ADDR field. + DMA_EXTMEM_REJECT_ADDR_EXTMEM_REJECT_ADDR_Pos = 0x0 + // Bit mask of EXTMEM_REJECT_ADDR field. + DMA_EXTMEM_REJECT_ADDR_EXTMEM_REJECT_ADDR_Msk = 0xffffffff + + // EXTMEM_REJECT_ST: Reject status accessing external RAM + // Position of EXTMEM_REJECT_ATRR field. + DMA_EXTMEM_REJECT_ST_EXTMEM_REJECT_ATRR_Pos = 0x0 + // Bit mask of EXTMEM_REJECT_ATRR field. + DMA_EXTMEM_REJECT_ST_EXTMEM_REJECT_ATRR_Msk = 0x3 + // Position of EXTMEM_REJECT_CHANNEL_NUM field. + DMA_EXTMEM_REJECT_ST_EXTMEM_REJECT_CHANNEL_NUM_Pos = 0x2 + // Bit mask of EXTMEM_REJECT_CHANNEL_NUM field. + DMA_EXTMEM_REJECT_ST_EXTMEM_REJECT_CHANNEL_NUM_Msk = 0x3c + // Position of EXTMEM_REJECT_PERI_NUM field. + DMA_EXTMEM_REJECT_ST_EXTMEM_REJECT_PERI_NUM_Pos = 0x6 + // Bit mask of EXTMEM_REJECT_PERI_NUM field. + DMA_EXTMEM_REJECT_ST_EXTMEM_REJECT_PERI_NUM_Msk = 0xfc0 + + // EXTMEM_REJECT_INT_RAW: Raw interrupt status of external RAM permission + // Position of EXTMEM_REJECT_INT_RAW field. + DMA_EXTMEM_REJECT_INT_RAW_EXTMEM_REJECT_INT_RAW_Pos = 0x0 + // Bit mask of EXTMEM_REJECT_INT_RAW field. + DMA_EXTMEM_REJECT_INT_RAW_EXTMEM_REJECT_INT_RAW_Msk = 0x1 + // Bit EXTMEM_REJECT_INT_RAW. + DMA_EXTMEM_REJECT_INT_RAW_EXTMEM_REJECT_INT_RAW = 0x1 + + // EXTMEM_REJECT_INT_ST: Masked interrupt status of external RAM permission + // Position of EXTMEM_REJECT_INT_ST field. + DMA_EXTMEM_REJECT_INT_ST_EXTMEM_REJECT_INT_ST_Pos = 0x0 + // Bit mask of EXTMEM_REJECT_INT_ST field. + DMA_EXTMEM_REJECT_INT_ST_EXTMEM_REJECT_INT_ST_Msk = 0x1 + // Bit EXTMEM_REJECT_INT_ST. + DMA_EXTMEM_REJECT_INT_ST_EXTMEM_REJECT_INT_ST = 0x1 + + // EXTMEM_REJECT_INT_ENA: Interrupt enable bits of external RAM permission + // Position of EXTMEM_REJECT_INT_ENA field. + DMA_EXTMEM_REJECT_INT_ENA_EXTMEM_REJECT_INT_ENA_Pos = 0x0 + // Bit mask of EXTMEM_REJECT_INT_ENA field. + DMA_EXTMEM_REJECT_INT_ENA_EXTMEM_REJECT_INT_ENA_Msk = 0x1 + // Bit EXTMEM_REJECT_INT_ENA. + DMA_EXTMEM_REJECT_INT_ENA_EXTMEM_REJECT_INT_ENA = 0x1 + + // EXTMEM_REJECT_INT_CLR: Interrupt clear bits of external RAM permission + // Position of EXTMEM_REJECT_INT_CLR field. + DMA_EXTMEM_REJECT_INT_CLR_EXTMEM_REJECT_INT_CLR_Pos = 0x0 + // Bit mask of EXTMEM_REJECT_INT_CLR field. + DMA_EXTMEM_REJECT_INT_CLR_EXTMEM_REJECT_INT_CLR_Msk = 0x1 + // Bit EXTMEM_REJECT_INT_CLR. + DMA_EXTMEM_REJECT_INT_CLR_EXTMEM_REJECT_INT_CLR = 0x1 + + // DATE: Version control register + // Position of DATE field. + DMA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DMA_DATE_DATE_Msk = 0xffffffff +) + +// Constants for DS: Digital Signature +const ( + // IV_0: IV block data + // Position of IV field. + DS_IV_IV_Pos = 0x0 + // Bit mask of IV field. + DS_IV_IV_Msk = 0xffffffff + + // SET_START: Activates the DS peripheral + // Position of SET_START field. + DS_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + DS_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + DS_SET_START_SET_START = 0x1 + + // SET_ME: Starts DS operation + // Position of SET_ME field. + DS_SET_ME_SET_ME_Pos = 0x0 + // Bit mask of SET_ME field. + DS_SET_ME_SET_ME_Msk = 0x1 + // Bit SET_ME. + DS_SET_ME_SET_ME = 0x1 + + // SET_FINISH: Ends DS operation + // Position of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Pos = 0x0 + // Bit mask of SET_FINISH field. + DS_SET_FINISH_SET_FINISH_Msk = 0x1 + // Bit SET_FINISH. + DS_SET_FINISH_SET_FINISH = 0x1 + + // QUERY_BUSY: Status of the DS perihperal + // Position of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Pos = 0x0 + // Bit mask of QUERY_BUSY field. + DS_QUERY_BUSY_QUERY_BUSY_Msk = 0x1 + // Bit QUERY_BUSY. + DS_QUERY_BUSY_QUERY_BUSY = 0x1 + + // QUERY_KEY_WRONG: Checks the reason why DS_KEY is not ready + // Position of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Pos = 0x0 + // Bit mask of QUERY_KEY_WRONG field. + DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Msk = 0xf + + // QUERY_CHECK: Queries DS check result + // Position of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Pos = 0x0 + // Bit mask of MD_ERROR field. + DS_QUERY_CHECK_MD_ERROR_Msk = 0x1 + // Bit MD_ERROR. + DS_QUERY_CHECK_MD_ERROR = 0x1 + // Position of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Pos = 0x1 + // Bit mask of PADDING_BAD field. + DS_QUERY_CHECK_PADDING_BAD_Msk = 0x2 + // Bit PADDING_BAD. + DS_QUERY_CHECK_PADDING_BAD = 0x2 + + // DATE: DS version control register + // Position of DATE field. + DS_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + DS_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for EFUSE: eFuse Controller +const ( + // PGM_DATA0: Register 0 that stores data to be programmed. + // Position of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Pos = 0x0 + // Bit mask of PGM_DATA_0 field. + EFUSE_PGM_DATA0_PGM_DATA_0_Msk = 0xffffffff + + // PGM_DATA1: Register 1 that stores data to be programmed. + // Position of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Pos = 0x0 + // Bit mask of PGM_DATA_1 field. + EFUSE_PGM_DATA1_PGM_DATA_1_Msk = 0xffffffff + + // PGM_DATA2: Register 2 that stores data to be programmed. + // Position of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Pos = 0x0 + // Bit mask of PGM_DATA_2 field. + EFUSE_PGM_DATA2_PGM_DATA_2_Msk = 0xffffffff + + // PGM_DATA3: Register 3 that stores data to be programmed. + // Position of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Pos = 0x0 + // Bit mask of PGM_DATA_3 field. + EFUSE_PGM_DATA3_PGM_DATA_3_Msk = 0xffffffff + + // PGM_DATA4: Register 4 that stores data to be programmed. + // Position of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Pos = 0x0 + // Bit mask of PGM_DATA_4 field. + EFUSE_PGM_DATA4_PGM_DATA_4_Msk = 0xffffffff + + // PGM_DATA5: Register 5 that stores data to be programmed. + // Position of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Pos = 0x0 + // Bit mask of PGM_DATA_5 field. + EFUSE_PGM_DATA5_PGM_DATA_5_Msk = 0xffffffff + + // PGM_DATA6: Register 6 that stores data to be programmed. + // Position of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Pos = 0x0 + // Bit mask of PGM_DATA_6 field. + EFUSE_PGM_DATA6_PGM_DATA_6_Msk = 0xffffffff + + // PGM_DATA7: Register 7 that stores data to be programmed. + // Position of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Pos = 0x0 + // Bit mask of PGM_DATA_7 field. + EFUSE_PGM_DATA7_PGM_DATA_7_Msk = 0xffffffff + + // PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Pos = 0x0 + // Bit mask of PGM_RS_DATA_0 field. + EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Msk = 0xffffffff + + // PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Pos = 0x0 + // Bit mask of PGM_RS_DATA_1 field. + EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Msk = 0xffffffff + + // PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed. + // Position of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Pos = 0x0 + // Bit mask of PGM_RS_DATA_2 field. + EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Msk = 0xffffffff + + // RD_WR_DIS: BLOCK0 data register 0. + // Position of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Pos = 0x0 + // Bit mask of WR_DIS field. + EFUSE_RD_WR_DIS_WR_DIS_Msk = 0xffffffff + + // RD_REPEAT_DATA0: BLOCK0 data register 1. + // Position of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Pos = 0x0 + // Bit mask of RD_DIS field. + EFUSE_RD_REPEAT_DATA0_RD_DIS_Msk = 0x7f + // Position of DIS_RTC_RAM_BOOT field. + EFUSE_RD_REPEAT_DATA0_DIS_RTC_RAM_BOOT_Pos = 0x7 + // Bit mask of DIS_RTC_RAM_BOOT field. + EFUSE_RD_REPEAT_DATA0_DIS_RTC_RAM_BOOT_Msk = 0x80 + // Bit DIS_RTC_RAM_BOOT. + EFUSE_RD_REPEAT_DATA0_DIS_RTC_RAM_BOOT = 0x80 + // Position of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Pos = 0x8 + // Bit mask of DIS_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE_Msk = 0x100 + // Bit DIS_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_ICACHE = 0x100 + // Position of DIS_DCACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DCACHE_Pos = 0x9 + // Bit mask of DIS_DCACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DCACHE_Msk = 0x200 + // Bit DIS_DCACHE. + EFUSE_RD_REPEAT_DATA0_DIS_DCACHE = 0x200 + // Position of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Pos = 0xa + // Bit mask of DIS_DOWNLOAD_ICACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE_Msk = 0x400 + // Bit DIS_DOWNLOAD_ICACHE. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_ICACHE = 0x400 + // Position of DIS_DOWNLOAD_DCACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE_Pos = 0xb + // Bit mask of DIS_DOWNLOAD_DCACHE field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE_Msk = 0x800 + // Bit DIS_DOWNLOAD_DCACHE. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_DCACHE = 0x800 + // Position of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD. + EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD = 0x1000 + // Position of DIS_USB field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_Pos = 0xd + // Bit mask of DIS_USB field. + EFUSE_RD_REPEAT_DATA0_DIS_USB_Msk = 0x2000 + // Bit DIS_USB. + EFUSE_RD_REPEAT_DATA0_DIS_USB = 0x2000 + // Position of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Pos = 0xe + // Bit mask of DIS_CAN field. + EFUSE_RD_REPEAT_DATA0_DIS_CAN_Msk = 0x4000 + // Bit DIS_CAN. + EFUSE_RD_REPEAT_DATA0_DIS_CAN = 0x4000 + // Position of DIS_APP_CPU field. + EFUSE_RD_REPEAT_DATA0_DIS_APP_CPU_Pos = 0xf + // Bit mask of DIS_APP_CPU field. + EFUSE_RD_REPEAT_DATA0_DIS_APP_CPU_Msk = 0x8000 + // Bit DIS_APP_CPU. + EFUSE_RD_REPEAT_DATA0_DIS_APP_CPU = 0x8000 + // Position of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Pos = 0x10 + // Bit mask of SOFT_DIS_JTAG field. + EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Msk = 0x70000 + // Position of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Pos = 0x13 + // Bit mask of DIS_PAD_JTAG field. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Msk = 0x80000 + // Bit DIS_PAD_JTAG. + EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG = 0x80000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x14 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT field. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x100000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT. + EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT = 0x100000 + // Position of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Pos = 0x15 + // Bit mask of USB_DREFH field. + EFUSE_RD_REPEAT_DATA0_USB_DREFH_Msk = 0x600000 + // Position of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Pos = 0x17 + // Bit mask of USB_DREFL field. + EFUSE_RD_REPEAT_DATA0_USB_DREFL_Msk = 0x1800000 + // Position of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Pos = 0x19 + // Bit mask of USB_EXCHG_PINS field. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS_Msk = 0x2000000 + // Bit USB_EXCHG_PINS. + EFUSE_RD_REPEAT_DATA0_USB_EXCHG_PINS = 0x2000000 + // Position of EXT_PHY_ENABLE field. + EFUSE_RD_REPEAT_DATA0_EXT_PHY_ENABLE_Pos = 0x1a + // Bit mask of EXT_PHY_ENABLE field. + EFUSE_RD_REPEAT_DATA0_EXT_PHY_ENABLE_Msk = 0x4000000 + // Bit EXT_PHY_ENABLE. + EFUSE_RD_REPEAT_DATA0_EXT_PHY_ENABLE = 0x4000000 + // Position of BTLC_GPIO_ENABLE field. + EFUSE_RD_REPEAT_DATA0_BTLC_GPIO_ENABLE_Pos = 0x1b + // Bit mask of BTLC_GPIO_ENABLE field. + EFUSE_RD_REPEAT_DATA0_BTLC_GPIO_ENABLE_Msk = 0x18000000 + // Position of VDD_SPI_MODECURLIM field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_MODECURLIM_Pos = 0x1d + // Bit mask of VDD_SPI_MODECURLIM field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_MODECURLIM_Msk = 0x20000000 + // Bit VDD_SPI_MODECURLIM. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_MODECURLIM = 0x20000000 + // Position of VDD_SPI_DREFH field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_DREFH_Pos = 0x1e + // Bit mask of VDD_SPI_DREFH field. + EFUSE_RD_REPEAT_DATA0_VDD_SPI_DREFH_Msk = 0xc0000000 + + // RD_REPEAT_DATA1: BLOCK0 data register 2. + // Position of VDD_SPI_DREFM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DREFM_Pos = 0x0 + // Bit mask of VDD_SPI_DREFM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DREFM_Msk = 0x3 + // Position of VDD_SPI_DREFL field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DREFL_Pos = 0x2 + // Bit mask of VDD_SPI_DREFL field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DREFL_Msk = 0xc + // Position of VDD_SPI_XPD field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_XPD_Pos = 0x4 + // Bit mask of VDD_SPI_XPD field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_XPD_Msk = 0x10 + // Bit VDD_SPI_XPD. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_XPD = 0x10 + // Position of VDD_SPI_TIEH field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_TIEH_Pos = 0x5 + // Bit mask of VDD_SPI_TIEH field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_TIEH_Msk = 0x20 + // Bit VDD_SPI_TIEH. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_TIEH = 0x20 + // Position of VDD_SPI_FORCE field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_FORCE_Pos = 0x6 + // Bit mask of VDD_SPI_FORCE field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_FORCE_Msk = 0x40 + // Bit VDD_SPI_FORCE. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_FORCE = 0x40 + // Position of VDD_SPI_EN_INIT field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_EN_INIT_Pos = 0x7 + // Bit mask of VDD_SPI_EN_INIT field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_EN_INIT_Msk = 0x80 + // Bit VDD_SPI_EN_INIT. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_EN_INIT = 0x80 + // Position of VDD_SPI_ENCURLIM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_ENCURLIM_Pos = 0x8 + // Bit mask of VDD_SPI_ENCURLIM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_ENCURLIM_Msk = 0x100 + // Bit VDD_SPI_ENCURLIM. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_ENCURLIM = 0x100 + // Position of VDD_SPI_DCURLIM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DCURLIM_Pos = 0x9 + // Bit mask of VDD_SPI_DCURLIM field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DCURLIM_Msk = 0xe00 + // Position of VDD_SPI_INIT field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_INIT_Pos = 0xc + // Bit mask of VDD_SPI_INIT field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_INIT_Msk = 0x3000 + // Position of VDD_SPI_DCAP field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DCAP_Pos = 0xe + // Bit mask of VDD_SPI_DCAP field. + EFUSE_RD_REPEAT_DATA1_VDD_SPI_DCAP_Msk = 0xc000 + // Position of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL field. + EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT field. + EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0 = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1 = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2 field. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2. + EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2 = 0x800000 + // Position of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Msk = 0xf000000 + // Position of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1 field. + EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Msk = 0xf0000000 + + // RD_REPEAT_DATA2: BLOCK0 data register 3. + // Position of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Msk = 0xf + // Position of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Msk = 0xf0 + // Position of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Msk = 0xf00 + // Position of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Pos = 0xc + // Bit mask of KEY_PURPOSE_5 field. + EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Msk = 0xf000 + // Position of RPT4_RESERVED0 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED0_Pos = 0x10 + // Bit mask of RPT4_RESERVED0 field. + EFUSE_RD_REPEAT_DATA2_RPT4_RESERVED0_Msk = 0xf0000 + // Position of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Msk = 0x100000 + // Bit SECURE_BOOT_EN. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE field. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE. + EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE = 0x200000 + // Position of DIS_USB_JTAG field. + EFUSE_RD_REPEAT_DATA2_DIS_USB_JTAG_Pos = 0x16 + // Bit mask of DIS_USB_JTAG field. + EFUSE_RD_REPEAT_DATA2_DIS_USB_JTAG_Msk = 0x400000 + // Bit DIS_USB_JTAG. + EFUSE_RD_REPEAT_DATA2_DIS_USB_JTAG = 0x400000 + // Position of DIS_USB_DEVICE field. + EFUSE_RD_REPEAT_DATA2_DIS_USB_DEVICE_Pos = 0x17 + // Bit mask of DIS_USB_DEVICE field. + EFUSE_RD_REPEAT_DATA2_DIS_USB_DEVICE_Msk = 0x800000 + // Bit DIS_USB_DEVICE. + EFUSE_RD_REPEAT_DATA2_DIS_USB_DEVICE = 0x800000 + // Position of STRAP_JTAG_SEL field. + EFUSE_RD_REPEAT_DATA2_STRAP_JTAG_SEL_Pos = 0x18 + // Bit mask of STRAP_JTAG_SEL field. + EFUSE_RD_REPEAT_DATA2_STRAP_JTAG_SEL_Msk = 0x1000000 + // Bit STRAP_JTAG_SEL. + EFUSE_RD_REPEAT_DATA2_STRAP_JTAG_SEL = 0x1000000 + // Position of USB_PHY_SEL field. + EFUSE_RD_REPEAT_DATA2_USB_PHY_SEL_Pos = 0x19 + // Bit mask of USB_PHY_SEL field. + EFUSE_RD_REPEAT_DATA2_USB_PHY_SEL_Msk = 0x2000000 + // Bit USB_PHY_SEL. + EFUSE_RD_REPEAT_DATA2_USB_PHY_SEL = 0x2000000 + // Position of POWER_GLITCH_DSENSE field. + EFUSE_RD_REPEAT_DATA2_POWER_GLITCH_DSENSE_Pos = 0x1a + // Bit mask of POWER_GLITCH_DSENSE field. + EFUSE_RD_REPEAT_DATA2_POWER_GLITCH_DSENSE_Msk = 0xc000000 + // Position of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Pos = 0x1c + // Bit mask of FLASH_TPUW field. + EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Msk = 0xf0000000 + + // RD_REPEAT_DATA3: BLOCK0 data register 4. + // Position of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE = 0x1 + // Position of DIS_LEGACY_SPI_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT_Pos = 0x1 + // Bit mask of DIS_LEGACY_SPI_BOOT field. + EFUSE_RD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT_Msk = 0x2 + // Bit DIS_LEGACY_SPI_BOOT. + EFUSE_RD_REPEAT_DATA3_DIS_LEGACY_SPI_BOOT = 0x2 + // Position of UART_PRINT_CHANNEL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CHANNEL_Pos = 0x2 + // Bit mask of UART_PRINT_CHANNEL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CHANNEL_Msk = 0x4 + // Bit UART_PRINT_CHANNEL. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CHANNEL = 0x4 + // Position of FLASH_ECC_MODE field. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_MODE_Pos = 0x3 + // Bit mask of FLASH_ECC_MODE field. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_MODE_Msk = 0x8 + // Bit FLASH_ECC_MODE. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_MODE = 0x8 + // Position of DIS_USB_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE_Pos = 0x4 + // Bit mask of DIS_USB_DOWNLOAD_MODE field. + EFUSE_RD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE_Msk = 0x10 + // Bit DIS_USB_DOWNLOAD_MODE. + EFUSE_RD_REPEAT_DATA3_DIS_USB_DOWNLOAD_MODE = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD field. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD. + EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD = 0x20 + // Position of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL field. + EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Msk = 0xc0 + // Position of PIN_POWER_SELECTION field. + EFUSE_RD_REPEAT_DATA3_PIN_POWER_SELECTION_Pos = 0x8 + // Bit mask of PIN_POWER_SELECTION field. + EFUSE_RD_REPEAT_DATA3_PIN_POWER_SELECTION_Msk = 0x100 + // Bit PIN_POWER_SELECTION. + EFUSE_RD_REPEAT_DATA3_PIN_POWER_SELECTION = 0x100 + // Position of FLASH_TYPE field. + EFUSE_RD_REPEAT_DATA3_FLASH_TYPE_Pos = 0x9 + // Bit mask of FLASH_TYPE field. + EFUSE_RD_REPEAT_DATA3_FLASH_TYPE_Msk = 0x200 + // Bit FLASH_TYPE. + EFUSE_RD_REPEAT_DATA3_FLASH_TYPE = 0x200 + // Position of FLASH_PAGE_SIZE field. + EFUSE_RD_REPEAT_DATA3_FLASH_PAGE_SIZE_Pos = 0xa + // Bit mask of FLASH_PAGE_SIZE field. + EFUSE_RD_REPEAT_DATA3_FLASH_PAGE_SIZE_Msk = 0xc00 + // Position of FLASH_ECC_EN field. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_EN_Pos = 0xc + // Bit mask of FLASH_ECC_EN field. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_EN_Msk = 0x1000 + // Bit FLASH_ECC_EN. + EFUSE_RD_REPEAT_DATA3_FLASH_ECC_EN = 0x1000 + // Position of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Pos = 0xd + // Bit mask of FORCE_SEND_RESUME field. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Msk = 0x2000 + // Bit FORCE_SEND_RESUME. + EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME = 0x2000 + // Position of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Pos = 0xe + // Bit mask of SECURE_VERSION field. + EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Msk = 0x3fffc000 + // Position of POWERGLITCH_EN field. + EFUSE_RD_REPEAT_DATA3_POWERGLITCH_EN_Pos = 0x1e + // Bit mask of POWERGLITCH_EN field. + EFUSE_RD_REPEAT_DATA3_POWERGLITCH_EN_Msk = 0x40000000 + // Bit POWERGLITCH_EN. + EFUSE_RD_REPEAT_DATA3_POWERGLITCH_EN = 0x40000000 + // Position of RPT4_RESERVED1 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED1_Pos = 0x1f + // Bit mask of RPT4_RESERVED1 field. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED1_Msk = 0x80000000 + // Bit RPT4_RESERVED1. + EFUSE_RD_REPEAT_DATA3_RPT4_RESERVED1 = 0x80000000 + + // RD_REPEAT_DATA4: BLOCK0 data register 5. + // Position of RPT4_RESERVED2 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED2_Pos = 0x0 + // Bit mask of RPT4_RESERVED2 field. + EFUSE_RD_REPEAT_DATA4_RPT4_RESERVED2_Msk = 0xffffff + + // RD_MAC_SPI_SYS_0: BLOCK1 data register 0. + // Position of MAC_0 field. + EFUSE_RD_MAC_SPI_SYS_0_MAC_0_Pos = 0x0 + // Bit mask of MAC_0 field. + EFUSE_RD_MAC_SPI_SYS_0_MAC_0_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_1: BLOCK1 data register 1. + // Position of MAC_1 field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_1_Pos = 0x0 + // Bit mask of MAC_1 field. + EFUSE_RD_MAC_SPI_SYS_1_MAC_1_Msk = 0xffff + // Position of SPI_PAD_CONF_0 field. + EFUSE_RD_MAC_SPI_SYS_1_SPI_PAD_CONF_0_Pos = 0x10 + // Bit mask of SPI_PAD_CONF_0 field. + EFUSE_RD_MAC_SPI_SYS_1_SPI_PAD_CONF_0_Msk = 0xffff0000 + + // RD_MAC_SPI_SYS_2: BLOCK1 data register 2. + // Position of SPI_PAD_CONF_1 field. + EFUSE_RD_MAC_SPI_SYS_2_SPI_PAD_CONF_1_Pos = 0x0 + // Bit mask of SPI_PAD_CONF_1 field. + EFUSE_RD_MAC_SPI_SYS_2_SPI_PAD_CONF_1_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_3: BLOCK1 data register 3. + // Position of SPI_PAD_CONF_2 field. + EFUSE_RD_MAC_SPI_SYS_3_SPI_PAD_CONF_2_Pos = 0x0 + // Bit mask of SPI_PAD_CONF_2 field. + EFUSE_RD_MAC_SPI_SYS_3_SPI_PAD_CONF_2_Msk = 0x3ffff + // Position of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SPI_SYS_3_SYS_DATA_PART0_0_Pos = 0x12 + // Bit mask of SYS_DATA_PART0_0 field. + EFUSE_RD_MAC_SPI_SYS_3_SYS_DATA_PART0_0_Msk = 0xfffc0000 + + // RD_MAC_SPI_SYS_4: BLOCK1 data register 4. + // Position of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SPI_SYS_4_SYS_DATA_PART0_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_1 field. + EFUSE_RD_MAC_SPI_SYS_4_SYS_DATA_PART0_1_Msk = 0xffffffff + + // RD_MAC_SPI_SYS_5: BLOCK1 data register 5. + // Position of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SPI_SYS_5_SYS_DATA_PART0_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART0_2 field. + EFUSE_RD_MAC_SPI_SYS_5_SYS_DATA_PART0_2_Msk = 0xffffffff + + // RD_SYS_PART1_DATA0: Register 0 of BLOCK2 (system). + // Position of SYS_DATA_PART1_0 field. + EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_0 field. + EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Msk = 0xffffffff + + // RD_SYS_PART1_DATA1: Register 1 of BLOCK2 (system). + // Position of SYS_DATA_PART1_1 field. + EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_1 field. + EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Msk = 0xffffffff + + // RD_SYS_PART1_DATA2: Register 2 of BLOCK2 (system). + // Position of SYS_DATA_PART1_2 field. + EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_2 field. + EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Msk = 0xffffffff + + // RD_SYS_PART1_DATA3: Register 3 of BLOCK2 (system). + // Position of SYS_DATA_PART1_3 field. + EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_3 field. + EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Msk = 0xffffffff + + // RD_SYS_PART1_DATA4: Register 4 of BLOCK2 (system). + // Position of SYS_DATA_PART1_4 field. + EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_4 field. + EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Msk = 0xffffffff + + // RD_SYS_PART1_DATA5: Register 5 of BLOCK2 (system). + // Position of SYS_DATA_PART1_5 field. + EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_5 field. + EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Msk = 0xffffffff + + // RD_SYS_PART1_DATA6: Register 6 of BLOCK2 (system). + // Position of SYS_DATA_PART1_6 field. + EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_6 field. + EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Msk = 0xffffffff + + // RD_SYS_PART1_DATA7: Register 7 of BLOCK2 (system). + // Position of SYS_DATA_PART1_7 field. + EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Pos = 0x0 + // Bit mask of SYS_DATA_PART1_7 field. + EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Msk = 0xffffffff + + // RD_USR_DATA0: Register 0 of BLOCK3 (user). + // Position of USR_DATA0 field. + EFUSE_RD_USR_DATA0_USR_DATA0_Pos = 0x0 + // Bit mask of USR_DATA0 field. + EFUSE_RD_USR_DATA0_USR_DATA0_Msk = 0xffffffff + + // RD_USR_DATA1: Register 1 of BLOCK3 (user). + // Position of USR_DATA1 field. + EFUSE_RD_USR_DATA1_USR_DATA1_Pos = 0x0 + // Bit mask of USR_DATA1 field. + EFUSE_RD_USR_DATA1_USR_DATA1_Msk = 0xffffffff + + // RD_USR_DATA2: Register 2 of BLOCK3 (user). + // Position of USR_DATA2 field. + EFUSE_RD_USR_DATA2_USR_DATA2_Pos = 0x0 + // Bit mask of USR_DATA2 field. + EFUSE_RD_USR_DATA2_USR_DATA2_Msk = 0xffffffff + + // RD_USR_DATA3: Register 3 of BLOCK3 (user). + // Position of USR_DATA3 field. + EFUSE_RD_USR_DATA3_USR_DATA3_Pos = 0x0 + // Bit mask of USR_DATA3 field. + EFUSE_RD_USR_DATA3_USR_DATA3_Msk = 0xffffffff + + // RD_USR_DATA4: Register 4 of BLOCK3 (user). + // Position of USR_DATA4 field. + EFUSE_RD_USR_DATA4_USR_DATA4_Pos = 0x0 + // Bit mask of USR_DATA4 field. + EFUSE_RD_USR_DATA4_USR_DATA4_Msk = 0xffffffff + + // RD_USR_DATA5: Register 5 of BLOCK3 (user). + // Position of USR_DATA5 field. + EFUSE_RD_USR_DATA5_USR_DATA5_Pos = 0x0 + // Bit mask of USR_DATA5 field. + EFUSE_RD_USR_DATA5_USR_DATA5_Msk = 0xffffffff + + // RD_USR_DATA6: Register 6 of BLOCK3 (user). + // Position of USR_DATA6 field. + EFUSE_RD_USR_DATA6_USR_DATA6_Pos = 0x0 + // Bit mask of USR_DATA6 field. + EFUSE_RD_USR_DATA6_USR_DATA6_Msk = 0xffffffff + + // RD_USR_DATA7: Register 7 of BLOCK3 (user). + // Position of USR_DATA7 field. + EFUSE_RD_USR_DATA7_USR_DATA7_Pos = 0x0 + // Bit mask of USR_DATA7 field. + EFUSE_RD_USR_DATA7_USR_DATA7_Msk = 0xffffffff + + // RD_KEY0_DATA0: Register 0 of BLOCK4 (KEY0). + // Position of KEY0_DATA0 field. + EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Pos = 0x0 + // Bit mask of KEY0_DATA0 field. + EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Msk = 0xffffffff + + // RD_KEY0_DATA1: Register 1 of BLOCK4 (KEY0). + // Position of KEY0_DATA1 field. + EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Pos = 0x0 + // Bit mask of KEY0_DATA1 field. + EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Msk = 0xffffffff + + // RD_KEY0_DATA2: Register 2 of BLOCK4 (KEY0). + // Position of KEY0_DATA2 field. + EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Pos = 0x0 + // Bit mask of KEY0_DATA2 field. + EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Msk = 0xffffffff + + // RD_KEY0_DATA3: Register 3 of BLOCK4 (KEY0). + // Position of KEY0_DATA3 field. + EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Pos = 0x0 + // Bit mask of KEY0_DATA3 field. + EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Msk = 0xffffffff + + // RD_KEY0_DATA4: Register 4 of BLOCK4 (KEY0). + // Position of KEY0_DATA4 field. + EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Pos = 0x0 + // Bit mask of KEY0_DATA4 field. + EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Msk = 0xffffffff + + // RD_KEY0_DATA5: Register 5 of BLOCK4 (KEY0). + // Position of KEY0_DATA5 field. + EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Pos = 0x0 + // Bit mask of KEY0_DATA5 field. + EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Msk = 0xffffffff + + // RD_KEY0_DATA6: Register 6 of BLOCK4 (KEY0). + // Position of KEY0_DATA6 field. + EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Pos = 0x0 + // Bit mask of KEY0_DATA6 field. + EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Msk = 0xffffffff + + // RD_KEY0_DATA7: Register 7 of BLOCK4 (KEY0). + // Position of KEY0_DATA7 field. + EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Pos = 0x0 + // Bit mask of KEY0_DATA7 field. + EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Msk = 0xffffffff + + // RD_KEY1_DATA0: Register 0 of BLOCK5 (KEY1). + // Position of KEY1_DATA0 field. + EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Pos = 0x0 + // Bit mask of KEY1_DATA0 field. + EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Msk = 0xffffffff + + // RD_KEY1_DATA1: Register 1 of BLOCK5 (KEY1). + // Position of KEY1_DATA1 field. + EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Pos = 0x0 + // Bit mask of KEY1_DATA1 field. + EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Msk = 0xffffffff + + // RD_KEY1_DATA2: Register 2 of BLOCK5 (KEY1). + // Position of KEY1_DATA2 field. + EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Pos = 0x0 + // Bit mask of KEY1_DATA2 field. + EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Msk = 0xffffffff + + // RD_KEY1_DATA3: Register 3 of BLOCK5 (KEY1). + // Position of KEY1_DATA3 field. + EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Pos = 0x0 + // Bit mask of KEY1_DATA3 field. + EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Msk = 0xffffffff + + // RD_KEY1_DATA4: Register 4 of BLOCK5 (KEY1). + // Position of KEY1_DATA4 field. + EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Pos = 0x0 + // Bit mask of KEY1_DATA4 field. + EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Msk = 0xffffffff + + // RD_KEY1_DATA5: Register 5 of BLOCK5 (KEY1). + // Position of KEY1_DATA5 field. + EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Pos = 0x0 + // Bit mask of KEY1_DATA5 field. + EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Msk = 0xffffffff + + // RD_KEY1_DATA6: Register 6 of BLOCK5 (KEY1). + // Position of KEY1_DATA6 field. + EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Pos = 0x0 + // Bit mask of KEY1_DATA6 field. + EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Msk = 0xffffffff + + // RD_KEY1_DATA7: Register 7 of BLOCK5 (KEY1). + // Position of KEY1_DATA7 field. + EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Pos = 0x0 + // Bit mask of KEY1_DATA7 field. + EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Msk = 0xffffffff + + // RD_KEY2_DATA0: Register 0 of BLOCK6 (KEY2). + // Position of KEY2_DATA0 field. + EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Pos = 0x0 + // Bit mask of KEY2_DATA0 field. + EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Msk = 0xffffffff + + // RD_KEY2_DATA1: Register 1 of BLOCK6 (KEY2). + // Position of KEY2_DATA1 field. + EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Pos = 0x0 + // Bit mask of KEY2_DATA1 field. + EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Msk = 0xffffffff + + // RD_KEY2_DATA2: Register 2 of BLOCK6 (KEY2). + // Position of KEY2_DATA2 field. + EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Pos = 0x0 + // Bit mask of KEY2_DATA2 field. + EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Msk = 0xffffffff + + // RD_KEY2_DATA3: Register 3 of BLOCK6 (KEY2). + // Position of KEY2_DATA3 field. + EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Pos = 0x0 + // Bit mask of KEY2_DATA3 field. + EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Msk = 0xffffffff + + // RD_KEY2_DATA4: Register 4 of BLOCK6 (KEY2). + // Position of KEY2_DATA4 field. + EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Pos = 0x0 + // Bit mask of KEY2_DATA4 field. + EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Msk = 0xffffffff + + // RD_KEY2_DATA5: Register 5 of BLOCK6 (KEY2). + // Position of KEY2_DATA5 field. + EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Pos = 0x0 + // Bit mask of KEY2_DATA5 field. + EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Msk = 0xffffffff + + // RD_KEY2_DATA6: Register 6 of BLOCK6 (KEY2). + // Position of KEY2_DATA6 field. + EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Pos = 0x0 + // Bit mask of KEY2_DATA6 field. + EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Msk = 0xffffffff + + // RD_KEY2_DATA7: Register 7 of BLOCK6 (KEY2). + // Position of KEY2_DATA7 field. + EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Pos = 0x0 + // Bit mask of KEY2_DATA7 field. + EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Msk = 0xffffffff + + // RD_KEY3_DATA0: Register 0 of BLOCK7 (KEY3). + // Position of KEY3_DATA0 field. + EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Pos = 0x0 + // Bit mask of KEY3_DATA0 field. + EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Msk = 0xffffffff + + // RD_KEY3_DATA1: Register 1 of BLOCK7 (KEY3). + // Position of KEY3_DATA1 field. + EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Pos = 0x0 + // Bit mask of KEY3_DATA1 field. + EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Msk = 0xffffffff + + // RD_KEY3_DATA2: Register 2 of BLOCK7 (KEY3). + // Position of KEY3_DATA2 field. + EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Pos = 0x0 + // Bit mask of KEY3_DATA2 field. + EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Msk = 0xffffffff + + // RD_KEY3_DATA3: Register 3 of BLOCK7 (KEY3). + // Position of KEY3_DATA3 field. + EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Pos = 0x0 + // Bit mask of KEY3_DATA3 field. + EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Msk = 0xffffffff + + // RD_KEY3_DATA4: Register 4 of BLOCK7 (KEY3). + // Position of KEY3_DATA4 field. + EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Pos = 0x0 + // Bit mask of KEY3_DATA4 field. + EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Msk = 0xffffffff + + // RD_KEY3_DATA5: Register 5 of BLOCK7 (KEY3). + // Position of KEY3_DATA5 field. + EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Pos = 0x0 + // Bit mask of KEY3_DATA5 field. + EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Msk = 0xffffffff + + // RD_KEY3_DATA6: Register 6 of BLOCK7 (KEY3). + // Position of KEY3_DATA6 field. + EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Pos = 0x0 + // Bit mask of KEY3_DATA6 field. + EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Msk = 0xffffffff + + // RD_KEY3_DATA7: Register 7 of BLOCK7 (KEY3). + // Position of KEY3_DATA7 field. + EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Pos = 0x0 + // Bit mask of KEY3_DATA7 field. + EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Msk = 0xffffffff + + // RD_KEY4_DATA0: Register 0 of BLOCK8 (KEY4). + // Position of KEY4_DATA0 field. + EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Pos = 0x0 + // Bit mask of KEY4_DATA0 field. + EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Msk = 0xffffffff + + // RD_KEY4_DATA1: Register 1 of BLOCK8 (KEY4). + // Position of KEY4_DATA1 field. + EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Pos = 0x0 + // Bit mask of KEY4_DATA1 field. + EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Msk = 0xffffffff + + // RD_KEY4_DATA2: Register 2 of BLOCK8 (KEY4). + // Position of KEY4_DATA2 field. + EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Pos = 0x0 + // Bit mask of KEY4_DATA2 field. + EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Msk = 0xffffffff + + // RD_KEY4_DATA3: Register 3 of BLOCK8 (KEY4). + // Position of KEY4_DATA3 field. + EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Pos = 0x0 + // Bit mask of KEY4_DATA3 field. + EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Msk = 0xffffffff + + // RD_KEY4_DATA4: Register 4 of BLOCK8 (KEY4). + // Position of KEY4_DATA4 field. + EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Pos = 0x0 + // Bit mask of KEY4_DATA4 field. + EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Msk = 0xffffffff + + // RD_KEY4_DATA5: Register 5 of BLOCK8 (KEY4). + // Position of KEY4_DATA5 field. + EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Pos = 0x0 + // Bit mask of KEY4_DATA5 field. + EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Msk = 0xffffffff + + // RD_KEY4_DATA6: Register 6 of BLOCK8 (KEY4). + // Position of KEY4_DATA6 field. + EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Pos = 0x0 + // Bit mask of KEY4_DATA6 field. + EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Msk = 0xffffffff + + // RD_KEY4_DATA7: Register 7 of BLOCK8 (KEY4). + // Position of KEY4_DATA7 field. + EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Pos = 0x0 + // Bit mask of KEY4_DATA7 field. + EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Msk = 0xffffffff + + // RD_KEY5_DATA0: Register 0 of BLOCK9 (KEY5). + // Position of KEY5_DATA0 field. + EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Pos = 0x0 + // Bit mask of KEY5_DATA0 field. + EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Msk = 0xffffffff + + // RD_KEY5_DATA1: Register 1 of BLOCK9 (KEY5). + // Position of KEY5_DATA1 field. + EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Pos = 0x0 + // Bit mask of KEY5_DATA1 field. + EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Msk = 0xffffffff + + // RD_KEY5_DATA2: Register 2 of BLOCK9 (KEY5). + // Position of KEY5_DATA2 field. + EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Pos = 0x0 + // Bit mask of KEY5_DATA2 field. + EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Msk = 0xffffffff + + // RD_KEY5_DATA3: Register 3 of BLOCK9 (KEY5). + // Position of KEY5_DATA3 field. + EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Pos = 0x0 + // Bit mask of KEY5_DATA3 field. + EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Msk = 0xffffffff + + // RD_KEY5_DATA4: Register 4 of BLOCK9 (KEY5). + // Position of KEY5_DATA4 field. + EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Pos = 0x0 + // Bit mask of KEY5_DATA4 field. + EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Msk = 0xffffffff + + // RD_KEY5_DATA5: Register 5 of BLOCK9 (KEY5). + // Position of KEY5_DATA5 field. + EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Pos = 0x0 + // Bit mask of KEY5_DATA5 field. + EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Msk = 0xffffffff + + // RD_KEY5_DATA6: Register 6 of BLOCK9 (KEY5). + // Position of KEY5_DATA6 field. + EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Pos = 0x0 + // Bit mask of KEY5_DATA6 field. + EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Msk = 0xffffffff + + // RD_KEY5_DATA7: Register 7 of BLOCK9 (KEY5). + // Position of KEY5_DATA7 field. + EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Pos = 0x0 + // Bit mask of KEY5_DATA7 field. + EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Msk = 0xffffffff + + // RD_SYS_PART2_DATA0: Register 0 of BLOCK10 (system). + // Position of SYS_DATA_PART2_0 field. + EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_0 field. + EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Msk = 0xffffffff + + // RD_SYS_PART2_DATA1: Register 1 of BLOCK9 (KEY5). + // Position of SYS_DATA_PART2_1 field. + EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_1 field. + EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Msk = 0xffffffff + + // RD_SYS_PART2_DATA2: Register 2 of BLOCK10 (system). + // Position of SYS_DATA_PART2_2 field. + EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_2 field. + EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Msk = 0xffffffff + + // RD_SYS_PART2_DATA3: Register 3 of BLOCK10 (system). + // Position of SYS_DATA_PART2_3 field. + EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_3 field. + EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Msk = 0xffffffff + + // RD_SYS_PART2_DATA4: Register 4 of BLOCK10 (system). + // Position of SYS_DATA_PART2_4 field. + EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_4 field. + EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Msk = 0xffffffff + + // RD_SYS_PART2_DATA5: Register 5 of BLOCK10 (system). + // Position of SYS_DATA_PART2_5 field. + EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_5 field. + EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Msk = 0xffffffff + + // RD_SYS_PART2_DATA6: Register 6 of BLOCK10 (system). + // Position of SYS_DATA_PART2_6 field. + EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_6 field. + EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Msk = 0xffffffff + + // RD_SYS_PART2_DATA7: Register 7 of BLOCK10 (system). + // Position of SYS_DATA_PART2_7 field. + EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Pos = 0x0 + // Bit mask of SYS_DATA_PART2_7 field. + EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Msk = 0xffffffff + + // RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0. + // Position of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Pos = 0x0 + // Bit mask of RD_DIS_ERR field. + EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Msk = 0x7f + // Position of DIS_RTC_RAM_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR_Pos = 0x7 + // Bit mask of DIS_RTC_RAM_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR_Msk = 0x80 + // Bit DIS_RTC_RAM_BOOT_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_RTC_RAM_BOOT_ERR = 0x80 + // Position of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Pos = 0x8 + // Bit mask of DIS_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR_Msk = 0x100 + // Bit DIS_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_ICACHE_ERR = 0x100 + // Position of DIS_DCACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DCACHE_ERR_Pos = 0x9 + // Bit mask of DIS_DCACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DCACHE_ERR_Msk = 0x200 + // Bit DIS_DCACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DCACHE_ERR = 0x200 + // Position of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR_Pos = 0xa + // Bit mask of DIS_DOWNLOAD_ICACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR_Msk = 0x400 + // Bit DIS_DOWNLOAD_ICACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_ICACHE_ERR = 0x400 + // Position of DIS_DOWNLOAD_DCACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR_Pos = 0xb + // Bit mask of DIS_DOWNLOAD_DCACHE_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR_Msk = 0x800 + // Bit DIS_DOWNLOAD_DCACHE_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_DCACHE_ERR = 0x800 + // Position of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Pos = 0xc + // Bit mask of DIS_FORCE_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Msk = 0x1000 + // Bit DIS_FORCE_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR = 0x1000 + // Position of DIS_USB_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_ERR_Pos = 0xd + // Bit mask of DIS_USB_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_USB_ERR_Msk = 0x2000 + // Bit DIS_USB_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_USB_ERR = 0x2000 + // Position of DIS_CAN_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_CAN_ERR_Pos = 0xe + // Bit mask of DIS_CAN_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_CAN_ERR_Msk = 0x4000 + // Bit DIS_CAN_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_CAN_ERR = 0x4000 + // Position of DIS_APP_CPU_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_APP_CPU_ERR_Pos = 0xf + // Bit mask of DIS_APP_CPU_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_APP_CPU_ERR_Msk = 0x8000 + // Bit DIS_APP_CPU_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_APP_CPU_ERR = 0x8000 + // Position of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Pos = 0x10 + // Bit mask of SOFT_DIS_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Msk = 0x70000 + // Position of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Pos = 0x13 + // Bit mask of DIS_PAD_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Msk = 0x80000 + // Bit DIS_PAD_JTAG_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR = 0x80000 + // Position of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Pos = 0x14 + // Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Msk = 0x100000 + // Bit DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR. + EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR = 0x100000 + // Position of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Pos = 0x15 + // Bit mask of USB_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFH_ERR_Msk = 0x600000 + // Position of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Pos = 0x17 + // Bit mask of USB_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_DREFL_ERR_Msk = 0x1800000 + // Position of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Pos = 0x19 + // Bit mask of USB_EXCHG_PINS_ERR field. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR_Msk = 0x2000000 + // Bit USB_EXCHG_PINS_ERR. + EFUSE_RD_REPEAT_ERR0_USB_EXCHG_PINS_ERR = 0x2000000 + // Position of EXT_PHY_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR_Pos = 0x1a + // Bit mask of EXT_PHY_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR_Msk = 0x4000000 + // Bit EXT_PHY_ENABLE_ERR. + EFUSE_RD_REPEAT_ERR0_EXT_PHY_ENABLE_ERR = 0x4000000 + // Position of BTLC_GPIO_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_BTLC_GPIO_ENABLE_ERR_Pos = 0x1b + // Bit mask of BTLC_GPIO_ENABLE_ERR field. + EFUSE_RD_REPEAT_ERR0_BTLC_GPIO_ENABLE_ERR_Msk = 0x18000000 + // Position of VDD_SPI_MODECURLIM_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR_Pos = 0x1d + // Bit mask of VDD_SPI_MODECURLIM_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR_Msk = 0x20000000 + // Bit VDD_SPI_MODECURLIM_ERR. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_MODECURLIM_ERR = 0x20000000 + // Position of VDD_SPI_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_DREFH_ERR_Pos = 0x1e + // Bit mask of VDD_SPI_DREFH_ERR field. + EFUSE_RD_REPEAT_ERR0_VDD_SPI_DREFH_ERR_Msk = 0xc0000000 + + // RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0. + // Position of VDD_SPI_DREFM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DREFM_ERR_Pos = 0x0 + // Bit mask of VDD_SPI_DREFM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DREFM_ERR_Msk = 0x3 + // Position of VDD_SPI_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DREFL_ERR_Pos = 0x2 + // Bit mask of VDD_SPI_DREFL_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DREFL_ERR_Msk = 0xc + // Position of VDD_SPI_XPD_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_XPD_ERR_Pos = 0x4 + // Bit mask of VDD_SPI_XPD_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_XPD_ERR_Msk = 0x10 + // Bit VDD_SPI_XPD_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_XPD_ERR = 0x10 + // Position of VDD_SPI_TIEH_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_TIEH_ERR_Pos = 0x5 + // Bit mask of VDD_SPI_TIEH_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_TIEH_ERR_Msk = 0x20 + // Bit VDD_SPI_TIEH_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_TIEH_ERR = 0x20 + // Position of VDD_SPI_FORCE_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_FORCE_ERR_Pos = 0x6 + // Bit mask of VDD_SPI_FORCE_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_FORCE_ERR_Msk = 0x40 + // Bit VDD_SPI_FORCE_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_FORCE_ERR = 0x40 + // Position of VDD_SPI_EN_INIT_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR_Pos = 0x7 + // Bit mask of VDD_SPI_EN_INIT_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR_Msk = 0x80 + // Bit VDD_SPI_EN_INIT_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_EN_INIT_ERR = 0x80 + // Position of VDD_SPI_ENCURLIM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR_Pos = 0x8 + // Bit mask of VDD_SPI_ENCURLIM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR_Msk = 0x100 + // Bit VDD_SPI_ENCURLIM_ERR. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_ENCURLIM_ERR = 0x100 + // Position of VDD_SPI_DCURLIM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DCURLIM_ERR_Pos = 0x9 + // Bit mask of VDD_SPI_DCURLIM_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DCURLIM_ERR_Msk = 0xe00 + // Position of VDD_SPI_INIT_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_INIT_ERR_Pos = 0xc + // Bit mask of VDD_SPI_INIT_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_INIT_ERR_Msk = 0x3000 + // Position of VDD_SPI_DCAP_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DCAP_ERR_Pos = 0xe + // Bit mask of VDD_SPI_DCAP_ERR field. + EFUSE_RD_REPEAT_ERR1_VDD_SPI_DCAP_ERR_Msk = 0xc000 + // Position of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Pos = 0x10 + // Bit mask of WDT_DELAY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Msk = 0x30000 + // Position of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Pos = 0x12 + // Bit mask of SPI_BOOT_CRYPT_CNT_ERR field. + EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Msk = 0x1c0000 + // Position of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_KEY_REVOKE0_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_KEY_REVOKE0_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR = 0x200000 + // Position of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Pos = 0x16 + // Bit mask of SECURE_BOOT_KEY_REVOKE1_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Msk = 0x400000 + // Bit SECURE_BOOT_KEY_REVOKE1_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR = 0x400000 + // Position of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Pos = 0x17 + // Bit mask of SECURE_BOOT_KEY_REVOKE2_ERR field. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Msk = 0x800000 + // Bit SECURE_BOOT_KEY_REVOKE2_ERR. + EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR = 0x800000 + // Position of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Pos = 0x18 + // Bit mask of KEY_PURPOSE_0_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Msk = 0xf000000 + // Position of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Pos = 0x1c + // Bit mask of KEY_PURPOSE_1_ERR field. + EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0. + // Position of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Pos = 0x0 + // Bit mask of KEY_PURPOSE_2_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Msk = 0xf + // Position of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Pos = 0x4 + // Bit mask of KEY_PURPOSE_3_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Msk = 0xf0 + // Position of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Pos = 0x8 + // Bit mask of KEY_PURPOSE_4_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Msk = 0xf00 + // Position of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Pos = 0xc + // Bit mask of KEY_PURPOSE_5_ERR field. + EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Msk = 0xf000 + // Position of RPT4_RESERVED0_ERR field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED0_ERR_Pos = 0x10 + // Bit mask of RPT4_RESERVED0_ERR field. + EFUSE_RD_REPEAT_ERR2_RPT4_RESERVED0_ERR_Msk = 0xf0000 + // Position of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Pos = 0x14 + // Bit mask of SECURE_BOOT_EN_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Msk = 0x100000 + // Bit SECURE_BOOT_EN_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR = 0x100000 + // Position of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Pos = 0x15 + // Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Msk = 0x200000 + // Bit SECURE_BOOT_AGGRESSIVE_REVOKE_ERR. + EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR = 0x200000 + // Position of DIS_USB_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR2_DIS_USB_JTAG_ERR_Pos = 0x16 + // Bit mask of DIS_USB_JTAG_ERR field. + EFUSE_RD_REPEAT_ERR2_DIS_USB_JTAG_ERR_Msk = 0x400000 + // Bit DIS_USB_JTAG_ERR. + EFUSE_RD_REPEAT_ERR2_DIS_USB_JTAG_ERR = 0x400000 + // Position of DIS_USB_DEVICE_ERR field. + EFUSE_RD_REPEAT_ERR2_DIS_USB_DEVICE_ERR_Pos = 0x17 + // Bit mask of DIS_USB_DEVICE_ERR field. + EFUSE_RD_REPEAT_ERR2_DIS_USB_DEVICE_ERR_Msk = 0x800000 + // Bit DIS_USB_DEVICE_ERR. + EFUSE_RD_REPEAT_ERR2_DIS_USB_DEVICE_ERR = 0x800000 + // Position of STRAP_JTAG_SEL_ERR field. + EFUSE_RD_REPEAT_ERR2_STRAP_JTAG_SEL_ERR_Pos = 0x18 + // Bit mask of STRAP_JTAG_SEL_ERR field. + EFUSE_RD_REPEAT_ERR2_STRAP_JTAG_SEL_ERR_Msk = 0x1000000 + // Bit STRAP_JTAG_SEL_ERR. + EFUSE_RD_REPEAT_ERR2_STRAP_JTAG_SEL_ERR = 0x1000000 + // Position of USB_PHY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR2_USB_PHY_SEL_ERR_Pos = 0x19 + // Bit mask of USB_PHY_SEL_ERR field. + EFUSE_RD_REPEAT_ERR2_USB_PHY_SEL_ERR_Msk = 0x2000000 + // Bit USB_PHY_SEL_ERR. + EFUSE_RD_REPEAT_ERR2_USB_PHY_SEL_ERR = 0x2000000 + // Position of POWER_GLITCH_DSENSE_ERR field. + EFUSE_RD_REPEAT_ERR2_POWER_GLITCH_DSENSE_ERR_Pos = 0x1a + // Bit mask of POWER_GLITCH_DSENSE_ERR field. + EFUSE_RD_REPEAT_ERR2_POWER_GLITCH_DSENSE_ERR_Msk = 0xc000000 + // Position of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Pos = 0x1c + // Bit mask of FLASH_TPUW_ERR field. + EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Msk = 0xf0000000 + + // RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0. + // Position of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Pos = 0x0 + // Bit mask of DIS_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Msk = 0x1 + // Bit DIS_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR = 0x1 + // Position of DIS_LEGACY_SPI_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR_Pos = 0x1 + // Bit mask of DIS_LEGACY_SPI_BOOT_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR_Msk = 0x2 + // Bit DIS_LEGACY_SPI_BOOT_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_LEGACY_SPI_BOOT_ERR = 0x2 + // Position of UART_PRINT_CHANNEL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR_Pos = 0x2 + // Bit mask of UART_PRINT_CHANNEL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR_Msk = 0x4 + // Bit UART_PRINT_CHANNEL_ERR. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CHANNEL_ERR = 0x4 + // Position of FLASH_ECC_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_MODE_ERR_Pos = 0x3 + // Bit mask of FLASH_ECC_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_MODE_ERR_Msk = 0x8 + // Bit FLASH_ECC_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_MODE_ERR = 0x8 + // Position of DIS_USB_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR_Pos = 0x4 + // Bit mask of DIS_USB_DOWNLOAD_MODE_ERR field. + EFUSE_RD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR_Msk = 0x10 + // Bit DIS_USB_DOWNLOAD_MODE_ERR. + EFUSE_RD_REPEAT_ERR3_DIS_USB_DOWNLOAD_MODE_ERR = 0x10 + // Position of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Pos = 0x5 + // Bit mask of ENABLE_SECURITY_DOWNLOAD_ERR field. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Msk = 0x20 + // Bit ENABLE_SECURITY_DOWNLOAD_ERR. + EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR = 0x20 + // Position of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Pos = 0x6 + // Bit mask of UART_PRINT_CONTROL_ERR field. + EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Msk = 0xc0 + // Position of PIN_POWER_SELECTION_ERR field. + EFUSE_RD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR_Pos = 0x8 + // Bit mask of PIN_POWER_SELECTION_ERR field. + EFUSE_RD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR_Msk = 0x100 + // Bit PIN_POWER_SELECTION_ERR. + EFUSE_RD_REPEAT_ERR3_PIN_POWER_SELECTION_ERR = 0x100 + // Position of FLASH_TYPE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_TYPE_ERR_Pos = 0x9 + // Bit mask of FLASH_TYPE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_TYPE_ERR_Msk = 0x200 + // Bit FLASH_TYPE_ERR. + EFUSE_RD_REPEAT_ERR3_FLASH_TYPE_ERR = 0x200 + // Position of FLASH_PAGE_SIZE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_PAGE_SIZE_ERR_Pos = 0xa + // Bit mask of FLASH_PAGE_SIZE_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_PAGE_SIZE_ERR_Msk = 0xc00 + // Position of FLASH_ECC_EN_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_EN_ERR_Pos = 0xc + // Bit mask of FLASH_ECC_EN_ERR field. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_EN_ERR_Msk = 0x1000 + // Bit FLASH_ECC_EN_ERR. + EFUSE_RD_REPEAT_ERR3_FLASH_ECC_EN_ERR = 0x1000 + // Position of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Pos = 0xd + // Bit mask of FORCE_SEND_RESUME_ERR field. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Msk = 0x2000 + // Bit FORCE_SEND_RESUME_ERR. + EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR = 0x2000 + // Position of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Pos = 0xe + // Bit mask of SECURE_VERSION_ERR field. + EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Msk = 0x3fffc000 + // Position of POWERGLITCH_EN_ERR field. + EFUSE_RD_REPEAT_ERR3_POWERGLITCH_EN_ERR_Pos = 0x1e + // Bit mask of POWERGLITCH_EN_ERR field. + EFUSE_RD_REPEAT_ERR3_POWERGLITCH_EN_ERR_Msk = 0x40000000 + // Bit POWERGLITCH_EN_ERR. + EFUSE_RD_REPEAT_ERR3_POWERGLITCH_EN_ERR = 0x40000000 + // Position of RPT4_RESERVED1_ERR field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED1_ERR_Pos = 0x1f + // Bit mask of RPT4_RESERVED1_ERR field. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED1_ERR_Msk = 0x80000000 + // Bit RPT4_RESERVED1_ERR. + EFUSE_RD_REPEAT_ERR3_RPT4_RESERVED1_ERR = 0x80000000 + + // RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0. + // Position of RPT4_RESERVED2_ERR field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED2_ERR_Pos = 0x0 + // Bit mask of RPT4_RESERVED2_ERR field. + EFUSE_RD_REPEAT_ERR4_RPT4_RESERVED2_ERR_Msk = 0xffffff + + // RD_RS_ERR0: Programming error record register 0 of BLOCK1-10. + // Position of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Pos = 0x0 + // Bit mask of MAC_SPI_8M_ERR_NUM field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_ERR_NUM_Msk = 0x7 + // Position of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Pos = 0x3 + // Bit mask of MAC_SPI_8M_FAIL field. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL_Msk = 0x8 + // Bit MAC_SPI_8M_FAIL. + EFUSE_RD_RS_ERR0_MAC_SPI_8M_FAIL = 0x8 + // Position of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Pos = 0x4 + // Bit mask of SYS_PART1_NUM field. + EFUSE_RD_RS_ERR0_SYS_PART1_NUM_Msk = 0x70 + // Position of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Pos = 0x7 + // Bit mask of SYS_PART1_FAIL field. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Msk = 0x80 + // Bit SYS_PART1_FAIL. + EFUSE_RD_RS_ERR0_SYS_PART1_FAIL = 0x80 + // Position of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Pos = 0x8 + // Bit mask of USR_DATA_ERR_NUM field. + EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Msk = 0x700 + // Position of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Pos = 0xb + // Bit mask of USR_DATA_FAIL field. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Msk = 0x800 + // Bit USR_DATA_FAIL. + EFUSE_RD_RS_ERR0_USR_DATA_FAIL = 0x800 + // Position of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Pos = 0xc + // Bit mask of KEY0_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Msk = 0x7000 + // Position of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Pos = 0xf + // Bit mask of KEY0_FAIL field. + EFUSE_RD_RS_ERR0_KEY0_FAIL_Msk = 0x8000 + // Bit KEY0_FAIL. + EFUSE_RD_RS_ERR0_KEY0_FAIL = 0x8000 + // Position of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Pos = 0x10 + // Bit mask of KEY1_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Msk = 0x70000 + // Position of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Pos = 0x13 + // Bit mask of KEY1_FAIL field. + EFUSE_RD_RS_ERR0_KEY1_FAIL_Msk = 0x80000 + // Bit KEY1_FAIL. + EFUSE_RD_RS_ERR0_KEY1_FAIL = 0x80000 + // Position of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Pos = 0x14 + // Bit mask of KEY2_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Msk = 0x700000 + // Position of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Pos = 0x17 + // Bit mask of KEY2_FAIL field. + EFUSE_RD_RS_ERR0_KEY2_FAIL_Msk = 0x800000 + // Bit KEY2_FAIL. + EFUSE_RD_RS_ERR0_KEY2_FAIL = 0x800000 + // Position of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Pos = 0x18 + // Bit mask of KEY3_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Msk = 0x7000000 + // Position of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Pos = 0x1b + // Bit mask of KEY3_FAIL field. + EFUSE_RD_RS_ERR0_KEY3_FAIL_Msk = 0x8000000 + // Bit KEY3_FAIL. + EFUSE_RD_RS_ERR0_KEY3_FAIL = 0x8000000 + // Position of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Pos = 0x1c + // Bit mask of KEY4_ERR_NUM field. + EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Msk = 0x70000000 + // Position of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Pos = 0x1f + // Bit mask of KEY4_FAIL field. + EFUSE_RD_RS_ERR0_KEY4_FAIL_Msk = 0x80000000 + // Bit KEY4_FAIL. + EFUSE_RD_RS_ERR0_KEY4_FAIL = 0x80000000 + + // RD_RS_ERR1: Programming error record register 1 of BLOCK1-10. + // Position of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Pos = 0x0 + // Bit mask of KEY5_ERR_NUM field. + EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Msk = 0x7 + // Position of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Pos = 0x3 + // Bit mask of KEY5_FAIL field. + EFUSE_RD_RS_ERR1_KEY5_FAIL_Msk = 0x8 + // Bit KEY5_FAIL. + EFUSE_RD_RS_ERR1_KEY5_FAIL = 0x8 + // Position of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Pos = 0x4 + // Bit mask of SYS_PART2_ERR_NUM field. + EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Msk = 0x70 + // Position of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Pos = 0x7 + // Bit mask of SYS_PART2_FAIL field. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Msk = 0x80 + // Bit SYS_PART2_FAIL. + EFUSE_RD_RS_ERR1_SYS_PART2_FAIL = 0x80 + + // CLK: eFuse clcok configuration register. + // Position of EFUSE_MEM_FORCE_PD field. + EFUSE_CLK_EFUSE_MEM_FORCE_PD_Pos = 0x0 + // Bit mask of EFUSE_MEM_FORCE_PD field. + EFUSE_CLK_EFUSE_MEM_FORCE_PD_Msk = 0x1 + // Bit EFUSE_MEM_FORCE_PD. + EFUSE_CLK_EFUSE_MEM_FORCE_PD = 0x1 + // Position of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + EFUSE_CLK_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + EFUSE_CLK_MEM_CLK_FORCE_ON = 0x2 + // Position of EFUSE_MEM_FORCE_PU field. + EFUSE_CLK_EFUSE_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of EFUSE_MEM_FORCE_PU field. + EFUSE_CLK_EFUSE_MEM_FORCE_PU_Msk = 0x4 + // Bit EFUSE_MEM_FORCE_PU. + EFUSE_CLK_EFUSE_MEM_FORCE_PU = 0x4 + // Position of EN field. + EFUSE_CLK_EN_Pos = 0x10 + // Bit mask of EN field. + EFUSE_CLK_EN_Msk = 0x10000 + // Bit EN. + EFUSE_CLK_EN = 0x10000 + + // CONF: eFuse operation mode configuraiton register + // Position of OP_CODE field. + EFUSE_CONF_OP_CODE_Pos = 0x0 + // Bit mask of OP_CODE field. + EFUSE_CONF_OP_CODE_Msk = 0xffff + + // STATUS: eFuse status register. + // Position of STATE field. + EFUSE_STATUS_STATE_Pos = 0x0 + // Bit mask of STATE field. + EFUSE_STATUS_STATE_Msk = 0xf + // Position of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Pos = 0x4 + // Bit mask of OTP_LOAD_SW field. + EFUSE_STATUS_OTP_LOAD_SW_Msk = 0x10 + // Bit OTP_LOAD_SW. + EFUSE_STATUS_OTP_LOAD_SW = 0x10 + // Position of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Pos = 0x5 + // Bit mask of OTP_VDDQ_C_SYNC2 field. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Msk = 0x20 + // Bit OTP_VDDQ_C_SYNC2. + EFUSE_STATUS_OTP_VDDQ_C_SYNC2 = 0x20 + // Position of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Pos = 0x6 + // Bit mask of OTP_STROBE_SW field. + EFUSE_STATUS_OTP_STROBE_SW_Msk = 0x40 + // Bit OTP_STROBE_SW. + EFUSE_STATUS_OTP_STROBE_SW = 0x40 + // Position of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Pos = 0x7 + // Bit mask of OTP_CSB_SW field. + EFUSE_STATUS_OTP_CSB_SW_Msk = 0x80 + // Bit OTP_CSB_SW. + EFUSE_STATUS_OTP_CSB_SW = 0x80 + // Position of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Pos = 0x8 + // Bit mask of OTP_PGENB_SW field. + EFUSE_STATUS_OTP_PGENB_SW_Msk = 0x100 + // Bit OTP_PGENB_SW. + EFUSE_STATUS_OTP_PGENB_SW = 0x100 + // Position of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Pos = 0x9 + // Bit mask of OTP_VDDQ_IS_SW field. + EFUSE_STATUS_OTP_VDDQ_IS_SW_Msk = 0x200 + // Bit OTP_VDDQ_IS_SW. + EFUSE_STATUS_OTP_VDDQ_IS_SW = 0x200 + // Position of REPEAT_ERR_CNT field. + EFUSE_STATUS_REPEAT_ERR_CNT_Pos = 0xa + // Bit mask of REPEAT_ERR_CNT field. + EFUSE_STATUS_REPEAT_ERR_CNT_Msk = 0x3fc00 + + // CMD: eFuse command register. + // Position of READ_CMD field. + EFUSE_CMD_READ_CMD_Pos = 0x0 + // Bit mask of READ_CMD field. + EFUSE_CMD_READ_CMD_Msk = 0x1 + // Bit READ_CMD. + EFUSE_CMD_READ_CMD = 0x1 + // Position of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Pos = 0x1 + // Bit mask of PGM_CMD field. + EFUSE_CMD_PGM_CMD_Msk = 0x2 + // Bit PGM_CMD. + EFUSE_CMD_PGM_CMD = 0x2 + // Position of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Pos = 0x2 + // Bit mask of BLK_NUM field. + EFUSE_CMD_BLK_NUM_Msk = 0x3c + + // INT_RAW: eFuse raw interrupt register. + // Position of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Pos = 0x0 + // Bit mask of READ_DONE_INT_RAW field. + EFUSE_INT_RAW_READ_DONE_INT_RAW_Msk = 0x1 + // Bit READ_DONE_INT_RAW. + EFUSE_INT_RAW_READ_DONE_INT_RAW = 0x1 + // Position of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Pos = 0x1 + // Bit mask of PGM_DONE_INT_RAW field. + EFUSE_INT_RAW_PGM_DONE_INT_RAW_Msk = 0x2 + // Bit PGM_DONE_INT_RAW. + EFUSE_INT_RAW_PGM_DONE_INT_RAW = 0x2 + + // INT_ST: eFuse interrupt status register. + // Position of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Pos = 0x0 + // Bit mask of READ_DONE_INT_ST field. + EFUSE_INT_ST_READ_DONE_INT_ST_Msk = 0x1 + // Bit READ_DONE_INT_ST. + EFUSE_INT_ST_READ_DONE_INT_ST = 0x1 + // Position of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ST field. + EFUSE_INT_ST_PGM_DONE_INT_ST_Msk = 0x2 + // Bit PGM_DONE_INT_ST. + EFUSE_INT_ST_PGM_DONE_INT_ST = 0x2 + + // INT_ENA: eFuse interrupt enable register. + // Position of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Pos = 0x0 + // Bit mask of READ_DONE_INT_ENA field. + EFUSE_INT_ENA_READ_DONE_INT_ENA_Msk = 0x1 + // Bit READ_DONE_INT_ENA. + EFUSE_INT_ENA_READ_DONE_INT_ENA = 0x1 + // Position of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Pos = 0x1 + // Bit mask of PGM_DONE_INT_ENA field. + EFUSE_INT_ENA_PGM_DONE_INT_ENA_Msk = 0x2 + // Bit PGM_DONE_INT_ENA. + EFUSE_INT_ENA_PGM_DONE_INT_ENA = 0x2 + + // INT_CLR: eFuse interrupt clear register. + // Position of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Pos = 0x0 + // Bit mask of READ_DONE_INT_CLR field. + EFUSE_INT_CLR_READ_DONE_INT_CLR_Msk = 0x1 + // Bit READ_DONE_INT_CLR. + EFUSE_INT_CLR_READ_DONE_INT_CLR = 0x1 + // Position of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Pos = 0x1 + // Bit mask of PGM_DONE_INT_CLR field. + EFUSE_INT_CLR_PGM_DONE_INT_CLR_Msk = 0x2 + // Bit PGM_DONE_INT_CLR. + EFUSE_INT_CLR_PGM_DONE_INT_CLR = 0x2 + + // DAC_CONF: Controls the eFuse programming voltage. + // Position of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Pos = 0x0 + // Bit mask of DAC_CLK_DIV field. + EFUSE_DAC_CONF_DAC_CLK_DIV_Msk = 0xff + // Position of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Pos = 0x8 + // Bit mask of DAC_CLK_PAD_SEL field. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Msk = 0x100 + // Bit DAC_CLK_PAD_SEL. + EFUSE_DAC_CONF_DAC_CLK_PAD_SEL = 0x100 + // Position of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Pos = 0x9 + // Bit mask of DAC_NUM field. + EFUSE_DAC_CONF_DAC_NUM_Msk = 0x1fe00 + // Position of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Pos = 0x11 + // Bit mask of OE_CLR field. + EFUSE_DAC_CONF_OE_CLR_Msk = 0x20000 + // Bit OE_CLR. + EFUSE_DAC_CONF_OE_CLR = 0x20000 + + // RD_TIM_CONF: Configures read timing parameters. + // Position of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Pos = 0x18 + // Bit mask of READ_INIT_NUM field. + EFUSE_RD_TIM_CONF_READ_INIT_NUM_Msk = 0xff000000 + + // WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters. + // Position of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Pos = 0x8 + // Bit mask of PWR_ON_NUM field. + EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Msk = 0xffff00 + + // WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters. + // Position of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Pos = 0x0 + // Bit mask of PWR_OFF_NUM field. + EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Msk = 0xffff + + // DATE: eFuse version register. + // Position of DATE field. + EFUSE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EFUSE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for EXTMEM: External Memory +const ( + // DCACHE_CTRL: ******* Description *********** + // Position of DCACHE_ENABLE field. + EXTMEM_DCACHE_CTRL_DCACHE_ENABLE_Pos = 0x0 + // Bit mask of DCACHE_ENABLE field. + EXTMEM_DCACHE_CTRL_DCACHE_ENABLE_Msk = 0x1 + // Bit DCACHE_ENABLE. + EXTMEM_DCACHE_CTRL_DCACHE_ENABLE = 0x1 + // Position of DCACHE_SIZE_MODE field. + EXTMEM_DCACHE_CTRL_DCACHE_SIZE_MODE_Pos = 0x2 + // Bit mask of DCACHE_SIZE_MODE field. + EXTMEM_DCACHE_CTRL_DCACHE_SIZE_MODE_Msk = 0x4 + // Bit DCACHE_SIZE_MODE. + EXTMEM_DCACHE_CTRL_DCACHE_SIZE_MODE = 0x4 + // Position of DCACHE_BLOCKSIZE_MODE field. + EXTMEM_DCACHE_CTRL_DCACHE_BLOCKSIZE_MODE_Pos = 0x3 + // Bit mask of DCACHE_BLOCKSIZE_MODE field. + EXTMEM_DCACHE_CTRL_DCACHE_BLOCKSIZE_MODE_Msk = 0x18 + + // DCACHE_CTRL1: ******* Description *********** + // Position of DCACHE_SHUT_CORE0_BUS field. + EXTMEM_DCACHE_CTRL1_DCACHE_SHUT_CORE0_BUS_Pos = 0x0 + // Bit mask of DCACHE_SHUT_CORE0_BUS field. + EXTMEM_DCACHE_CTRL1_DCACHE_SHUT_CORE0_BUS_Msk = 0x1 + // Bit DCACHE_SHUT_CORE0_BUS. + EXTMEM_DCACHE_CTRL1_DCACHE_SHUT_CORE0_BUS = 0x1 + // Position of DCACHE_SHUT_CORE1_BUS field. + EXTMEM_DCACHE_CTRL1_DCACHE_SHUT_CORE1_BUS_Pos = 0x1 + // Bit mask of DCACHE_SHUT_CORE1_BUS field. + EXTMEM_DCACHE_CTRL1_DCACHE_SHUT_CORE1_BUS_Msk = 0x2 + // Bit DCACHE_SHUT_CORE1_BUS. + EXTMEM_DCACHE_CTRL1_DCACHE_SHUT_CORE1_BUS = 0x2 + + // DCACHE_TAG_POWER_CTRL: ******* Description *********** + // Position of DCACHE_TAG_MEM_FORCE_ON field. + EXTMEM_DCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of DCACHE_TAG_MEM_FORCE_ON field. + EXTMEM_DCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_ON_Msk = 0x1 + // Bit DCACHE_TAG_MEM_FORCE_ON. + EXTMEM_DCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_ON = 0x1 + // Position of DCACHE_TAG_MEM_FORCE_PD field. + EXTMEM_DCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of DCACHE_TAG_MEM_FORCE_PD field. + EXTMEM_DCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PD_Msk = 0x2 + // Bit DCACHE_TAG_MEM_FORCE_PD. + EXTMEM_DCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PD = 0x2 + // Position of DCACHE_TAG_MEM_FORCE_PU field. + EXTMEM_DCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of DCACHE_TAG_MEM_FORCE_PU field. + EXTMEM_DCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PU_Msk = 0x4 + // Bit DCACHE_TAG_MEM_FORCE_PU. + EXTMEM_DCACHE_TAG_POWER_CTRL_DCACHE_TAG_MEM_FORCE_PU = 0x4 + + // DCACHE_PRELOCK_CTRL: ******* Description *********** + // Position of DCACHE_PRELOCK_SCT0_EN field. + EXTMEM_DCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT0_EN_Pos = 0x0 + // Bit mask of DCACHE_PRELOCK_SCT0_EN field. + EXTMEM_DCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT0_EN_Msk = 0x1 + // Bit DCACHE_PRELOCK_SCT0_EN. + EXTMEM_DCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT0_EN = 0x1 + // Position of DCACHE_PRELOCK_SCT1_EN field. + EXTMEM_DCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT1_EN_Pos = 0x1 + // Bit mask of DCACHE_PRELOCK_SCT1_EN field. + EXTMEM_DCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT1_EN_Msk = 0x2 + // Bit DCACHE_PRELOCK_SCT1_EN. + EXTMEM_DCACHE_PRELOCK_CTRL_DCACHE_PRELOCK_SCT1_EN = 0x2 + + // DCACHE_PRELOCK_SCT0_ADDR: ******* Description *********** + // Position of DCACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_DCACHE_PRELOCK_SCT0_ADDR_Pos = 0x0 + // Bit mask of DCACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_DCACHE_PRELOCK_SCT0_ADDR_Msk = 0xffffffff + + // DCACHE_PRELOCK_SCT1_ADDR: ******* Description *********** + // Position of DCACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_DCACHE_PRELOCK_SCT1_ADDR_Pos = 0x0 + // Bit mask of DCACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_DCACHE_PRELOCK_SCT1_ADDR_Msk = 0xffffffff + + // DCACHE_PRELOCK_SCT_SIZE: ******* Description *********** + // Position of DCACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_DCACHE_PRELOCK_SCT_SIZE_DCACHE_PRELOCK_SCT1_SIZE_Pos = 0x0 + // Bit mask of DCACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_DCACHE_PRELOCK_SCT_SIZE_DCACHE_PRELOCK_SCT1_SIZE_Msk = 0xffff + // Position of DCACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_DCACHE_PRELOCK_SCT_SIZE_DCACHE_PRELOCK_SCT0_SIZE_Pos = 0x10 + // Bit mask of DCACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_DCACHE_PRELOCK_SCT_SIZE_DCACHE_PRELOCK_SCT0_SIZE_Msk = 0xffff0000 + + // DCACHE_LOCK_CTRL: ******* Description *********** + // Position of DCACHE_LOCK_ENA field. + EXTMEM_DCACHE_LOCK_CTRL_DCACHE_LOCK_ENA_Pos = 0x0 + // Bit mask of DCACHE_LOCK_ENA field. + EXTMEM_DCACHE_LOCK_CTRL_DCACHE_LOCK_ENA_Msk = 0x1 + // Bit DCACHE_LOCK_ENA. + EXTMEM_DCACHE_LOCK_CTRL_DCACHE_LOCK_ENA = 0x1 + // Position of DCACHE_UNLOCK_ENA field. + EXTMEM_DCACHE_LOCK_CTRL_DCACHE_UNLOCK_ENA_Pos = 0x1 + // Bit mask of DCACHE_UNLOCK_ENA field. + EXTMEM_DCACHE_LOCK_CTRL_DCACHE_UNLOCK_ENA_Msk = 0x2 + // Bit DCACHE_UNLOCK_ENA. + EXTMEM_DCACHE_LOCK_CTRL_DCACHE_UNLOCK_ENA = 0x2 + // Position of DCACHE_LOCK_DONE field. + EXTMEM_DCACHE_LOCK_CTRL_DCACHE_LOCK_DONE_Pos = 0x2 + // Bit mask of DCACHE_LOCK_DONE field. + EXTMEM_DCACHE_LOCK_CTRL_DCACHE_LOCK_DONE_Msk = 0x4 + // Bit DCACHE_LOCK_DONE. + EXTMEM_DCACHE_LOCK_CTRL_DCACHE_LOCK_DONE = 0x4 + + // DCACHE_LOCK_ADDR: ******* Description *********** + // Position of DCACHE_LOCK_ADDR field. + EXTMEM_DCACHE_LOCK_ADDR_DCACHE_LOCK_ADDR_Pos = 0x0 + // Bit mask of DCACHE_LOCK_ADDR field. + EXTMEM_DCACHE_LOCK_ADDR_DCACHE_LOCK_ADDR_Msk = 0xffffffff + + // DCACHE_LOCK_SIZE: ******* Description *********** + // Position of DCACHE_LOCK_SIZE field. + EXTMEM_DCACHE_LOCK_SIZE_DCACHE_LOCK_SIZE_Pos = 0x0 + // Bit mask of DCACHE_LOCK_SIZE field. + EXTMEM_DCACHE_LOCK_SIZE_DCACHE_LOCK_SIZE_Msk = 0xffff + + // DCACHE_SYNC_CTRL: ******* Description *********** + // Position of DCACHE_INVALIDATE_ENA field. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_INVALIDATE_ENA_Pos = 0x0 + // Bit mask of DCACHE_INVALIDATE_ENA field. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_INVALIDATE_ENA_Msk = 0x1 + // Bit DCACHE_INVALIDATE_ENA. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_INVALIDATE_ENA = 0x1 + // Position of DCACHE_WRITEBACK_ENA field. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_WRITEBACK_ENA_Pos = 0x1 + // Bit mask of DCACHE_WRITEBACK_ENA field. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_WRITEBACK_ENA_Msk = 0x2 + // Bit DCACHE_WRITEBACK_ENA. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_WRITEBACK_ENA = 0x2 + // Position of DCACHE_CLEAN_ENA field. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_CLEAN_ENA_Pos = 0x2 + // Bit mask of DCACHE_CLEAN_ENA field. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_CLEAN_ENA_Msk = 0x4 + // Bit DCACHE_CLEAN_ENA. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_CLEAN_ENA = 0x4 + // Position of DCACHE_SYNC_DONE field. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_SYNC_DONE_Pos = 0x3 + // Bit mask of DCACHE_SYNC_DONE field. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_SYNC_DONE_Msk = 0x8 + // Bit DCACHE_SYNC_DONE. + EXTMEM_DCACHE_SYNC_CTRL_DCACHE_SYNC_DONE = 0x8 + + // DCACHE_SYNC_ADDR: ******* Description *********** + // Position of DCACHE_SYNC_ADDR field. + EXTMEM_DCACHE_SYNC_ADDR_DCACHE_SYNC_ADDR_Pos = 0x0 + // Bit mask of DCACHE_SYNC_ADDR field. + EXTMEM_DCACHE_SYNC_ADDR_DCACHE_SYNC_ADDR_Msk = 0xffffffff + + // DCACHE_SYNC_SIZE: ******* Description *********** + // Position of DCACHE_SYNC_SIZE field. + EXTMEM_DCACHE_SYNC_SIZE_DCACHE_SYNC_SIZE_Pos = 0x0 + // Bit mask of DCACHE_SYNC_SIZE field. + EXTMEM_DCACHE_SYNC_SIZE_DCACHE_SYNC_SIZE_Msk = 0x7fffff + + // DCACHE_OCCUPY_CTRL: ******* Description *********** + // Position of DCACHE_OCCUPY_ENA field. + EXTMEM_DCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_ENA_Pos = 0x0 + // Bit mask of DCACHE_OCCUPY_ENA field. + EXTMEM_DCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_ENA_Msk = 0x1 + // Bit DCACHE_OCCUPY_ENA. + EXTMEM_DCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_ENA = 0x1 + // Position of DCACHE_OCCUPY_DONE field. + EXTMEM_DCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_DONE_Pos = 0x1 + // Bit mask of DCACHE_OCCUPY_DONE field. + EXTMEM_DCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_DONE_Msk = 0x2 + // Bit DCACHE_OCCUPY_DONE. + EXTMEM_DCACHE_OCCUPY_CTRL_DCACHE_OCCUPY_DONE = 0x2 + + // DCACHE_OCCUPY_ADDR: ******* Description *********** + // Position of DCACHE_OCCUPY_ADDR field. + EXTMEM_DCACHE_OCCUPY_ADDR_DCACHE_OCCUPY_ADDR_Pos = 0x0 + // Bit mask of DCACHE_OCCUPY_ADDR field. + EXTMEM_DCACHE_OCCUPY_ADDR_DCACHE_OCCUPY_ADDR_Msk = 0xffffffff + + // DCACHE_OCCUPY_SIZE: ******* Description *********** + // Position of DCACHE_OCCUPY_SIZE field. + EXTMEM_DCACHE_OCCUPY_SIZE_DCACHE_OCCUPY_SIZE_Pos = 0x0 + // Bit mask of DCACHE_OCCUPY_SIZE field. + EXTMEM_DCACHE_OCCUPY_SIZE_DCACHE_OCCUPY_SIZE_Msk = 0xffff + + // DCACHE_PRELOAD_CTRL: ******* Description *********** + // Position of DCACHE_PRELOAD_ENA field. + EXTMEM_DCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ENA_Pos = 0x0 + // Bit mask of DCACHE_PRELOAD_ENA field. + EXTMEM_DCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ENA_Msk = 0x1 + // Bit DCACHE_PRELOAD_ENA. + EXTMEM_DCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ENA = 0x1 + // Position of DCACHE_PRELOAD_DONE field. + EXTMEM_DCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_DONE_Pos = 0x1 + // Bit mask of DCACHE_PRELOAD_DONE field. + EXTMEM_DCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_DONE_Msk = 0x2 + // Bit DCACHE_PRELOAD_DONE. + EXTMEM_DCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_DONE = 0x2 + // Position of DCACHE_PRELOAD_ORDER field. + EXTMEM_DCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ORDER_Pos = 0x2 + // Bit mask of DCACHE_PRELOAD_ORDER field. + EXTMEM_DCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ORDER_Msk = 0x4 + // Bit DCACHE_PRELOAD_ORDER. + EXTMEM_DCACHE_PRELOAD_CTRL_DCACHE_PRELOAD_ORDER = 0x4 + + // DCACHE_PRELOAD_ADDR: ******* Description *********** + // Position of DCACHE_PRELOAD_ADDR field. + EXTMEM_DCACHE_PRELOAD_ADDR_DCACHE_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of DCACHE_PRELOAD_ADDR field. + EXTMEM_DCACHE_PRELOAD_ADDR_DCACHE_PRELOAD_ADDR_Msk = 0xffffffff + + // DCACHE_PRELOAD_SIZE: ******* Description *********** + // Position of DCACHE_PRELOAD_SIZE field. + EXTMEM_DCACHE_PRELOAD_SIZE_DCACHE_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of DCACHE_PRELOAD_SIZE field. + EXTMEM_DCACHE_PRELOAD_SIZE_DCACHE_PRELOAD_SIZE_Msk = 0xffff + + // DCACHE_AUTOLOAD_CTRL: ******* Description *********** + // Position of DCACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT0_ENA_Pos = 0x0 + // Bit mask of DCACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT0_ENA_Msk = 0x1 + // Bit DCACHE_AUTOLOAD_SCT0_ENA. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT0_ENA = 0x1 + // Position of DCACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT1_ENA_Pos = 0x1 + // Bit mask of DCACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT1_ENA_Msk = 0x2 + // Bit DCACHE_AUTOLOAD_SCT1_ENA. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SCT1_ENA = 0x2 + // Position of DCACHE_AUTOLOAD_ENA field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ENA_Pos = 0x2 + // Bit mask of DCACHE_AUTOLOAD_ENA field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ENA_Msk = 0x4 + // Bit DCACHE_AUTOLOAD_ENA. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ENA = 0x4 + // Position of DCACHE_AUTOLOAD_DONE field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_DONE_Pos = 0x3 + // Bit mask of DCACHE_AUTOLOAD_DONE field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_DONE_Msk = 0x8 + // Bit DCACHE_AUTOLOAD_DONE. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_DONE = 0x8 + // Position of DCACHE_AUTOLOAD_ORDER field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ORDER_Pos = 0x4 + // Bit mask of DCACHE_AUTOLOAD_ORDER field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ORDER_Msk = 0x10 + // Bit DCACHE_AUTOLOAD_ORDER. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_ORDER = 0x10 + // Position of DCACHE_AUTOLOAD_RQST field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_RQST_Pos = 0x5 + // Bit mask of DCACHE_AUTOLOAD_RQST field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_RQST_Msk = 0x60 + // Position of DCACHE_AUTOLOAD_SIZE field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SIZE_Pos = 0x7 + // Bit mask of DCACHE_AUTOLOAD_SIZE field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_SIZE_Msk = 0x180 + // Position of DCACHE_AUTOLOAD_BUFFER_CLEAR field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_BUFFER_CLEAR_Pos = 0x9 + // Bit mask of DCACHE_AUTOLOAD_BUFFER_CLEAR field. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_BUFFER_CLEAR_Msk = 0x200 + // Bit DCACHE_AUTOLOAD_BUFFER_CLEAR. + EXTMEM_DCACHE_AUTOLOAD_CTRL_DCACHE_AUTOLOAD_BUFFER_CLEAR = 0x200 + + // DCACHE_AUTOLOAD_SCT0_ADDR: ******* Description *********** + // Position of DCACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_DCACHE_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of DCACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_DCACHE_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // DCACHE_AUTOLOAD_SCT0_SIZE: ******* Description *********** + // Position of DCACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_DCACHE_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of DCACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_DCACHE_AUTOLOAD_SCT0_SIZE_Msk = 0x7ffffff + + // DCACHE_AUTOLOAD_SCT1_ADDR: ******* Description *********** + // Position of DCACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_DCACHE_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of DCACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_DCACHE_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // DCACHE_AUTOLOAD_SCT1_SIZE: ******* Description *********** + // Position of DCACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_DCACHE_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of DCACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_DCACHE_AUTOLOAD_SCT1_SIZE_Msk = 0x7ffffff + + // ICACHE_CTRL: ******* Description *********** + // Position of ICACHE_ENABLE field. + EXTMEM_ICACHE_CTRL_ICACHE_ENABLE_Pos = 0x0 + // Bit mask of ICACHE_ENABLE field. + EXTMEM_ICACHE_CTRL_ICACHE_ENABLE_Msk = 0x1 + // Bit ICACHE_ENABLE. + EXTMEM_ICACHE_CTRL_ICACHE_ENABLE = 0x1 + // Position of ICACHE_WAY_MODE field. + EXTMEM_ICACHE_CTRL_ICACHE_WAY_MODE_Pos = 0x1 + // Bit mask of ICACHE_WAY_MODE field. + EXTMEM_ICACHE_CTRL_ICACHE_WAY_MODE_Msk = 0x2 + // Bit ICACHE_WAY_MODE. + EXTMEM_ICACHE_CTRL_ICACHE_WAY_MODE = 0x2 + // Position of ICACHE_SIZE_MODE field. + EXTMEM_ICACHE_CTRL_ICACHE_SIZE_MODE_Pos = 0x2 + // Bit mask of ICACHE_SIZE_MODE field. + EXTMEM_ICACHE_CTRL_ICACHE_SIZE_MODE_Msk = 0x4 + // Bit ICACHE_SIZE_MODE. + EXTMEM_ICACHE_CTRL_ICACHE_SIZE_MODE = 0x4 + // Position of ICACHE_BLOCKSIZE_MODE field. + EXTMEM_ICACHE_CTRL_ICACHE_BLOCKSIZE_MODE_Pos = 0x3 + // Bit mask of ICACHE_BLOCKSIZE_MODE field. + EXTMEM_ICACHE_CTRL_ICACHE_BLOCKSIZE_MODE_Msk = 0x8 + // Bit ICACHE_BLOCKSIZE_MODE. + EXTMEM_ICACHE_CTRL_ICACHE_BLOCKSIZE_MODE = 0x8 + + // ICACHE_CTRL1: ******* Description *********** + // Position of ICACHE_SHUT_CORE0_BUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_CORE0_BUS_Pos = 0x0 + // Bit mask of ICACHE_SHUT_CORE0_BUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_CORE0_BUS_Msk = 0x1 + // Bit ICACHE_SHUT_CORE0_BUS. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_CORE0_BUS = 0x1 + // Position of ICACHE_SHUT_CORE1_BUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_CORE1_BUS_Pos = 0x1 + // Bit mask of ICACHE_SHUT_CORE1_BUS field. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_CORE1_BUS_Msk = 0x2 + // Bit ICACHE_SHUT_CORE1_BUS. + EXTMEM_ICACHE_CTRL1_ICACHE_SHUT_CORE1_BUS = 0x2 + + // ICACHE_TAG_POWER_CTRL: ******* Description *********** + // Position of ICACHE_TAG_MEM_FORCE_ON field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of ICACHE_TAG_MEM_FORCE_ON field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON_Msk = 0x1 + // Bit ICACHE_TAG_MEM_FORCE_ON. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_ON = 0x1 + // Position of ICACHE_TAG_MEM_FORCE_PD field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of ICACHE_TAG_MEM_FORCE_PD field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD_Msk = 0x2 + // Bit ICACHE_TAG_MEM_FORCE_PD. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PD = 0x2 + // Position of ICACHE_TAG_MEM_FORCE_PU field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of ICACHE_TAG_MEM_FORCE_PU field. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU_Msk = 0x4 + // Bit ICACHE_TAG_MEM_FORCE_PU. + EXTMEM_ICACHE_TAG_POWER_CTRL_ICACHE_TAG_MEM_FORCE_PU = 0x4 + + // ICACHE_PRELOCK_CTRL: ******* Description *********** + // Position of ICACHE_PRELOCK_SCT0_EN field. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN_Pos = 0x0 + // Bit mask of ICACHE_PRELOCK_SCT0_EN field. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN_Msk = 0x1 + // Bit ICACHE_PRELOCK_SCT0_EN. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT0_EN = 0x1 + // Position of ICACHE_PRELOCK_SCT1_EN field. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN_Pos = 0x1 + // Bit mask of ICACHE_PRELOCK_SCT1_EN field. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN_Msk = 0x2 + // Bit ICACHE_PRELOCK_SCT1_EN. + EXTMEM_ICACHE_PRELOCK_CTRL_ICACHE_PRELOCK_SCT1_EN = 0x2 + + // ICACHE_PRELOCK_SCT0_ADDR: ******* Description *********** + // Position of ICACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_ICACHE_PRELOCK_SCT0_ADDR_Pos = 0x0 + // Bit mask of ICACHE_PRELOCK_SCT0_ADDR field. + EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_ICACHE_PRELOCK_SCT0_ADDR_Msk = 0xffffffff + + // ICACHE_PRELOCK_SCT1_ADDR: ******* Description *********** + // Position of ICACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_ICACHE_PRELOCK_SCT1_ADDR_Pos = 0x0 + // Bit mask of ICACHE_PRELOCK_SCT1_ADDR field. + EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_ICACHE_PRELOCK_SCT1_ADDR_Msk = 0xffffffff + + // ICACHE_PRELOCK_SCT_SIZE: ******* Description *********** + // Position of ICACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_ICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT1_SIZE_Pos = 0x0 + // Bit mask of ICACHE_PRELOCK_SCT1_SIZE field. + EXTMEM_ICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT1_SIZE_Msk = 0xffff + // Position of ICACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_ICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT0_SIZE_Pos = 0x10 + // Bit mask of ICACHE_PRELOCK_SCT0_SIZE field. + EXTMEM_ICACHE_PRELOCK_SCT_SIZE_ICACHE_PRELOCK_SCT0_SIZE_Msk = 0xffff0000 + + // ICACHE_LOCK_CTRL: ******* Description *********** + // Position of ICACHE_LOCK_ENA field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_ENA_Pos = 0x0 + // Bit mask of ICACHE_LOCK_ENA field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_ENA_Msk = 0x1 + // Bit ICACHE_LOCK_ENA. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_ENA = 0x1 + // Position of ICACHE_UNLOCK_ENA field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA_Pos = 0x1 + // Bit mask of ICACHE_UNLOCK_ENA field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA_Msk = 0x2 + // Bit ICACHE_UNLOCK_ENA. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_UNLOCK_ENA = 0x2 + // Position of ICACHE_LOCK_DONE field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_DONE_Pos = 0x2 + // Bit mask of ICACHE_LOCK_DONE field. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_DONE_Msk = 0x4 + // Bit ICACHE_LOCK_DONE. + EXTMEM_ICACHE_LOCK_CTRL_ICACHE_LOCK_DONE = 0x4 + + // ICACHE_LOCK_ADDR: ******* Description *********** + // Position of ICACHE_LOCK_ADDR field. + EXTMEM_ICACHE_LOCK_ADDR_ICACHE_LOCK_ADDR_Pos = 0x0 + // Bit mask of ICACHE_LOCK_ADDR field. + EXTMEM_ICACHE_LOCK_ADDR_ICACHE_LOCK_ADDR_Msk = 0xffffffff + + // ICACHE_LOCK_SIZE: ******* Description *********** + // Position of ICACHE_LOCK_SIZE field. + EXTMEM_ICACHE_LOCK_SIZE_ICACHE_LOCK_SIZE_Pos = 0x0 + // Bit mask of ICACHE_LOCK_SIZE field. + EXTMEM_ICACHE_LOCK_SIZE_ICACHE_LOCK_SIZE_Msk = 0xffff + + // ICACHE_SYNC_CTRL: ******* Description *********** + // Position of ICACHE_INVALIDATE_ENA field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA_Pos = 0x0 + // Bit mask of ICACHE_INVALIDATE_ENA field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA_Msk = 0x1 + // Bit ICACHE_INVALIDATE_ENA. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_INVALIDATE_ENA = 0x1 + // Position of ICACHE_SYNC_DONE field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_SYNC_DONE_Pos = 0x1 + // Bit mask of ICACHE_SYNC_DONE field. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_SYNC_DONE_Msk = 0x2 + // Bit ICACHE_SYNC_DONE. + EXTMEM_ICACHE_SYNC_CTRL_ICACHE_SYNC_DONE = 0x2 + + // ICACHE_SYNC_ADDR: ******* Description *********** + // Position of ICACHE_SYNC_ADDR field. + EXTMEM_ICACHE_SYNC_ADDR_ICACHE_SYNC_ADDR_Pos = 0x0 + // Bit mask of ICACHE_SYNC_ADDR field. + EXTMEM_ICACHE_SYNC_ADDR_ICACHE_SYNC_ADDR_Msk = 0xffffffff + + // ICACHE_SYNC_SIZE: ******* Description *********** + // Position of ICACHE_SYNC_SIZE field. + EXTMEM_ICACHE_SYNC_SIZE_ICACHE_SYNC_SIZE_Pos = 0x0 + // Bit mask of ICACHE_SYNC_SIZE field. + EXTMEM_ICACHE_SYNC_SIZE_ICACHE_SYNC_SIZE_Msk = 0x7fffff + + // ICACHE_PRELOAD_CTRL: ******* Description *********** + // Position of ICACHE_PRELOAD_ENA field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_ENA field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA_Msk = 0x1 + // Bit ICACHE_PRELOAD_ENA. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ENA = 0x1 + // Position of ICACHE_PRELOAD_DONE field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_DONE field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE_Msk = 0x2 + // Bit ICACHE_PRELOAD_DONE. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_DONE = 0x2 + // Position of ICACHE_PRELOAD_ORDER field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER_Pos = 0x2 + // Bit mask of ICACHE_PRELOAD_ORDER field. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER_Msk = 0x4 + // Bit ICACHE_PRELOAD_ORDER. + EXTMEM_ICACHE_PRELOAD_CTRL_ICACHE_PRELOAD_ORDER = 0x4 + + // ICACHE_PRELOAD_ADDR: ******* Description *********** + // Position of ICACHE_PRELOAD_ADDR field. + EXTMEM_ICACHE_PRELOAD_ADDR_ICACHE_PRELOAD_ADDR_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_ADDR field. + EXTMEM_ICACHE_PRELOAD_ADDR_ICACHE_PRELOAD_ADDR_Msk = 0xffffffff + + // ICACHE_PRELOAD_SIZE: ******* Description *********** + // Position of ICACHE_PRELOAD_SIZE field. + EXTMEM_ICACHE_PRELOAD_SIZE_ICACHE_PRELOAD_SIZE_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_SIZE field. + EXTMEM_ICACHE_PRELOAD_SIZE_ICACHE_PRELOAD_SIZE_Msk = 0xffff + + // ICACHE_AUTOLOAD_CTRL: ******* Description *********** + // Position of ICACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT0_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA_Msk = 0x1 + // Bit ICACHE_AUTOLOAD_SCT0_ENA. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT0_ENA = 0x1 + // Position of ICACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA_Pos = 0x1 + // Bit mask of ICACHE_AUTOLOAD_SCT1_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA_Msk = 0x2 + // Bit ICACHE_AUTOLOAD_SCT1_ENA. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SCT1_ENA = 0x2 + // Position of ICACHE_AUTOLOAD_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA_Pos = 0x2 + // Bit mask of ICACHE_AUTOLOAD_ENA field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA_Msk = 0x4 + // Bit ICACHE_AUTOLOAD_ENA. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ENA = 0x4 + // Position of ICACHE_AUTOLOAD_DONE field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE_Pos = 0x3 + // Bit mask of ICACHE_AUTOLOAD_DONE field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE_Msk = 0x8 + // Bit ICACHE_AUTOLOAD_DONE. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_DONE = 0x8 + // Position of ICACHE_AUTOLOAD_ORDER field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER_Pos = 0x4 + // Bit mask of ICACHE_AUTOLOAD_ORDER field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER_Msk = 0x10 + // Bit ICACHE_AUTOLOAD_ORDER. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_ORDER = 0x10 + // Position of ICACHE_AUTOLOAD_RQST field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_RQST_Pos = 0x5 + // Bit mask of ICACHE_AUTOLOAD_RQST field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_RQST_Msk = 0x60 + // Position of ICACHE_AUTOLOAD_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SIZE_Pos = 0x7 + // Bit mask of ICACHE_AUTOLOAD_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_SIZE_Msk = 0x180 + // Position of ICACHE_AUTOLOAD_BUFFER_CLEAR field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_BUFFER_CLEAR_Pos = 0x9 + // Bit mask of ICACHE_AUTOLOAD_BUFFER_CLEAR field. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_BUFFER_CLEAR_Msk = 0x200 + // Bit ICACHE_AUTOLOAD_BUFFER_CLEAR. + EXTMEM_ICACHE_AUTOLOAD_CTRL_ICACHE_AUTOLOAD_BUFFER_CLEAR = 0x200 + + // ICACHE_AUTOLOAD_SCT0_ADDR: ******* Description *********** + // Position of ICACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_ICACHE_AUTOLOAD_SCT0_ADDR_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT0_ADDR field. + EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_ICACHE_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff + + // ICACHE_AUTOLOAD_SCT0_SIZE: ******* Description *********** + // Position of ICACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_ICACHE_AUTOLOAD_SCT0_SIZE_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT0_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_ICACHE_AUTOLOAD_SCT0_SIZE_Msk = 0x7ffffff + + // ICACHE_AUTOLOAD_SCT1_ADDR: ******* Description *********** + // Position of ICACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_ICACHE_AUTOLOAD_SCT1_ADDR_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT1_ADDR field. + EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_ICACHE_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff + + // ICACHE_AUTOLOAD_SCT1_SIZE: ******* Description *********** + // Position of ICACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_ICACHE_AUTOLOAD_SCT1_SIZE_Pos = 0x0 + // Bit mask of ICACHE_AUTOLOAD_SCT1_SIZE field. + EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_ICACHE_AUTOLOAD_SCT1_SIZE_Msk = 0x7ffffff + + // IBUS_TO_FLASH_START_VADDR: ******* Description *********** + // Position of IBUS_TO_FLASH_START_VADDR field. + EXTMEM_IBUS_TO_FLASH_START_VADDR_IBUS_TO_FLASH_START_VADDR_Pos = 0x0 + // Bit mask of IBUS_TO_FLASH_START_VADDR field. + EXTMEM_IBUS_TO_FLASH_START_VADDR_IBUS_TO_FLASH_START_VADDR_Msk = 0xffffffff + + // IBUS_TO_FLASH_END_VADDR: ******* Description *********** + // Position of IBUS_TO_FLASH_END_VADDR field. + EXTMEM_IBUS_TO_FLASH_END_VADDR_IBUS_TO_FLASH_END_VADDR_Pos = 0x0 + // Bit mask of IBUS_TO_FLASH_END_VADDR field. + EXTMEM_IBUS_TO_FLASH_END_VADDR_IBUS_TO_FLASH_END_VADDR_Msk = 0xffffffff + + // DBUS_TO_FLASH_START_VADDR: ******* Description *********** + // Position of DBUS_TO_FLASH_START_VADDR field. + EXTMEM_DBUS_TO_FLASH_START_VADDR_DBUS_TO_FLASH_START_VADDR_Pos = 0x0 + // Bit mask of DBUS_TO_FLASH_START_VADDR field. + EXTMEM_DBUS_TO_FLASH_START_VADDR_DBUS_TO_FLASH_START_VADDR_Msk = 0xffffffff + + // DBUS_TO_FLASH_END_VADDR: ******* Description *********** + // Position of DBUS_TO_FLASH_END_VADDR field. + EXTMEM_DBUS_TO_FLASH_END_VADDR_DBUS_TO_FLASH_END_VADDR_Pos = 0x0 + // Bit mask of DBUS_TO_FLASH_END_VADDR field. + EXTMEM_DBUS_TO_FLASH_END_VADDR_DBUS_TO_FLASH_END_VADDR_Msk = 0xffffffff + + // CACHE_ACS_CNT_CLR: ******* Description *********** + // Position of DCACHE_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_DCACHE_ACS_CNT_CLR_Pos = 0x0 + // Bit mask of DCACHE_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_DCACHE_ACS_CNT_CLR_Msk = 0x1 + // Bit DCACHE_ACS_CNT_CLR. + EXTMEM_CACHE_ACS_CNT_CLR_DCACHE_ACS_CNT_CLR = 0x1 + // Position of ICACHE_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_ICACHE_ACS_CNT_CLR_Pos = 0x1 + // Bit mask of ICACHE_ACS_CNT_CLR field. + EXTMEM_CACHE_ACS_CNT_CLR_ICACHE_ACS_CNT_CLR_Msk = 0x2 + // Bit ICACHE_ACS_CNT_CLR. + EXTMEM_CACHE_ACS_CNT_CLR_ICACHE_ACS_CNT_CLR = 0x2 + + // IBUS_ACS_MISS_CNT: ******* Description *********** + // Position of IBUS_ACS_MISS_CNT field. + EXTMEM_IBUS_ACS_MISS_CNT_IBUS_ACS_MISS_CNT_Pos = 0x0 + // Bit mask of IBUS_ACS_MISS_CNT field. + EXTMEM_IBUS_ACS_MISS_CNT_IBUS_ACS_MISS_CNT_Msk = 0xffffffff + + // IBUS_ACS_CNT: ******* Description *********** + // Position of IBUS_ACS_CNT field. + EXTMEM_IBUS_ACS_CNT_IBUS_ACS_CNT_Pos = 0x0 + // Bit mask of IBUS_ACS_CNT field. + EXTMEM_IBUS_ACS_CNT_IBUS_ACS_CNT_Msk = 0xffffffff + + // DBUS_ACS_FLASH_MISS_CNT: ******* Description *********** + // Position of DBUS_ACS_FLASH_MISS_CNT field. + EXTMEM_DBUS_ACS_FLASH_MISS_CNT_DBUS_ACS_FLASH_MISS_CNT_Pos = 0x0 + // Bit mask of DBUS_ACS_FLASH_MISS_CNT field. + EXTMEM_DBUS_ACS_FLASH_MISS_CNT_DBUS_ACS_FLASH_MISS_CNT_Msk = 0xffffffff + + // DBUS_ACS_SPIRAM_MISS_CNT: ******* Description *********** + // Position of DBUS_ACS_SPIRAM_MISS_CNT field. + EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_DBUS_ACS_SPIRAM_MISS_CNT_Pos = 0x0 + // Bit mask of DBUS_ACS_SPIRAM_MISS_CNT field. + EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_DBUS_ACS_SPIRAM_MISS_CNT_Msk = 0xffffffff + + // DBUS_ACS_CNT: ******* Description *********** + // Position of DBUS_ACS_CNT field. + EXTMEM_DBUS_ACS_CNT_DBUS_ACS_CNT_Pos = 0x0 + // Bit mask of DBUS_ACS_CNT field. + EXTMEM_DBUS_ACS_CNT_DBUS_ACS_CNT_Msk = 0xffffffff + + // CACHE_ILG_INT_ENA: ******* Description *********** + // Position of ICACHE_SYNC_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA_Pos = 0x0 + // Bit mask of ICACHE_SYNC_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA_Msk = 0x1 + // Bit ICACHE_SYNC_OP_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_SYNC_OP_FAULT_INT_ENA = 0x1 + // Position of ICACHE_PRELOAD_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA_Msk = 0x2 + // Bit ICACHE_PRELOAD_OP_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_ICACHE_PRELOAD_OP_FAULT_INT_ENA = 0x2 + // Position of DCACHE_SYNC_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_SYNC_OP_FAULT_INT_ENA_Pos = 0x2 + // Bit mask of DCACHE_SYNC_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_SYNC_OP_FAULT_INT_ENA_Msk = 0x4 + // Bit DCACHE_SYNC_OP_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_SYNC_OP_FAULT_INT_ENA = 0x4 + // Position of DCACHE_PRELOAD_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_PRELOAD_OP_FAULT_INT_ENA_Pos = 0x3 + // Bit mask of DCACHE_PRELOAD_OP_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_PRELOAD_OP_FAULT_INT_ENA_Msk = 0x8 + // Bit DCACHE_PRELOAD_OP_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_PRELOAD_OP_FAULT_INT_ENA = 0x8 + // Position of DCACHE_WRITE_FLASH_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA_Pos = 0x4 + // Bit mask of DCACHE_WRITE_FLASH_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA_Msk = 0x10 + // Bit DCACHE_WRITE_FLASH_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_WRITE_FLASH_INT_ENA = 0x10 + // Position of MMU_ENTRY_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA_Pos = 0x5 + // Bit mask of MMU_ENTRY_FAULT_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA_Msk = 0x20 + // Bit MMU_ENTRY_FAULT_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_MMU_ENTRY_FAULT_INT_ENA = 0x20 + // Position of DCACHE_OCCUPY_EXC_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_OCCUPY_EXC_INT_ENA_Pos = 0x6 + // Bit mask of DCACHE_OCCUPY_EXC_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_OCCUPY_EXC_INT_ENA_Msk = 0x40 + // Bit DCACHE_OCCUPY_EXC_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_DCACHE_OCCUPY_EXC_INT_ENA = 0x40 + // Position of IBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA_Pos = 0x7 + // Bit mask of IBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA_Msk = 0x80 + // Bit IBUS_CNT_OVF_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_IBUS_CNT_OVF_INT_ENA = 0x80 + // Position of DBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA_Pos = 0x8 + // Bit mask of DBUS_CNT_OVF_INT_ENA field. + EXTMEM_CACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA_Msk = 0x100 + // Bit DBUS_CNT_OVF_INT_ENA. + EXTMEM_CACHE_ILG_INT_ENA_DBUS_CNT_OVF_INT_ENA = 0x100 + + // CACHE_ILG_INT_CLR: ******* Description *********** + // Position of ICACHE_SYNC_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR_Pos = 0x0 + // Bit mask of ICACHE_SYNC_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR_Msk = 0x1 + // Bit ICACHE_SYNC_OP_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_SYNC_OP_FAULT_INT_CLR = 0x1 + // Position of ICACHE_PRELOAD_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR_Msk = 0x2 + // Bit ICACHE_PRELOAD_OP_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_ICACHE_PRELOAD_OP_FAULT_INT_CLR = 0x2 + // Position of DCACHE_SYNC_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_SYNC_OP_FAULT_INT_CLR_Pos = 0x2 + // Bit mask of DCACHE_SYNC_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_SYNC_OP_FAULT_INT_CLR_Msk = 0x4 + // Bit DCACHE_SYNC_OP_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_SYNC_OP_FAULT_INT_CLR = 0x4 + // Position of DCACHE_PRELOAD_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_PRELOAD_OP_FAULT_INT_CLR_Pos = 0x3 + // Bit mask of DCACHE_PRELOAD_OP_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_PRELOAD_OP_FAULT_INT_CLR_Msk = 0x8 + // Bit DCACHE_PRELOAD_OP_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_PRELOAD_OP_FAULT_INT_CLR = 0x8 + // Position of DCACHE_WRITE_FLASH_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR_Pos = 0x4 + // Bit mask of DCACHE_WRITE_FLASH_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR_Msk = 0x10 + // Bit DCACHE_WRITE_FLASH_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_WRITE_FLASH_INT_CLR = 0x10 + // Position of MMU_ENTRY_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR_Pos = 0x5 + // Bit mask of MMU_ENTRY_FAULT_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR_Msk = 0x20 + // Bit MMU_ENTRY_FAULT_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_MMU_ENTRY_FAULT_INT_CLR = 0x20 + // Position of DCACHE_OCCUPY_EXC_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_OCCUPY_EXC_INT_CLR_Pos = 0x6 + // Bit mask of DCACHE_OCCUPY_EXC_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_OCCUPY_EXC_INT_CLR_Msk = 0x40 + // Bit DCACHE_OCCUPY_EXC_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_DCACHE_OCCUPY_EXC_INT_CLR = 0x40 + // Position of IBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR_Pos = 0x7 + // Bit mask of IBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR_Msk = 0x80 + // Bit IBUS_CNT_OVF_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_IBUS_CNT_OVF_INT_CLR = 0x80 + // Position of DBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR_Pos = 0x8 + // Bit mask of DBUS_CNT_OVF_INT_CLR field. + EXTMEM_CACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR_Msk = 0x100 + // Bit DBUS_CNT_OVF_INT_CLR. + EXTMEM_CACHE_ILG_INT_CLR_DBUS_CNT_OVF_INT_CLR = 0x100 + + // CACHE_ILG_INT_ST: ******* Description *********** + // Position of ICACHE_SYNC_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST_Pos = 0x0 + // Bit mask of ICACHE_SYNC_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST_Msk = 0x1 + // Bit ICACHE_SYNC_OP_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_SYNC_OP_FAULT_ST = 0x1 + // Position of ICACHE_PRELOAD_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST_Msk = 0x2 + // Bit ICACHE_PRELOAD_OP_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_ICACHE_PRELOAD_OP_FAULT_ST = 0x2 + // Position of DCACHE_SYNC_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_SYNC_OP_FAULT_ST_Pos = 0x2 + // Bit mask of DCACHE_SYNC_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_SYNC_OP_FAULT_ST_Msk = 0x4 + // Bit DCACHE_SYNC_OP_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_SYNC_OP_FAULT_ST = 0x4 + // Position of DCACHE_PRELOAD_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_PRELOAD_OP_FAULT_ST_Pos = 0x3 + // Bit mask of DCACHE_PRELOAD_OP_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_PRELOAD_OP_FAULT_ST_Msk = 0x8 + // Bit DCACHE_PRELOAD_OP_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_PRELOAD_OP_FAULT_ST = 0x8 + // Position of DCACHE_WRITE_FLASH_ST field. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_WRITE_FLASH_ST_Pos = 0x4 + // Bit mask of DCACHE_WRITE_FLASH_ST field. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_WRITE_FLASH_ST_Msk = 0x10 + // Bit DCACHE_WRITE_FLASH_ST. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_WRITE_FLASH_ST = 0x10 + // Position of MMU_ENTRY_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST_Pos = 0x5 + // Bit mask of MMU_ENTRY_FAULT_ST field. + EXTMEM_CACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST_Msk = 0x20 + // Bit MMU_ENTRY_FAULT_ST. + EXTMEM_CACHE_ILG_INT_ST_MMU_ENTRY_FAULT_ST = 0x20 + // Position of DCACHE_OCCUPY_EXC_ST field. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_OCCUPY_EXC_ST_Pos = 0x6 + // Bit mask of DCACHE_OCCUPY_EXC_ST field. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_OCCUPY_EXC_ST_Msk = 0x40 + // Bit DCACHE_OCCUPY_EXC_ST. + EXTMEM_CACHE_ILG_INT_ST_DCACHE_OCCUPY_EXC_ST = 0x40 + // Position of IBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST_Pos = 0x7 + // Bit mask of IBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST_Msk = 0x80 + // Bit IBUS_ACS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_CNT_OVF_ST = 0x80 + // Position of IBUS_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST_Pos = 0x8 + // Bit mask of IBUS_ACS_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST_Msk = 0x100 + // Bit IBUS_ACS_MISS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_IBUS_ACS_MISS_CNT_OVF_ST = 0x100 + // Position of DBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST_Pos = 0x9 + // Bit mask of DBUS_ACS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST_Msk = 0x200 + // Bit DBUS_ACS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_CNT_OVF_ST = 0x200 + // Position of DBUS_ACS_FLASH_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_Pos = 0xa + // Bit mask of DBUS_ACS_FLASH_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_Msk = 0x400 + // Bit DBUS_ACS_FLASH_MISS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_FLASH_MISS_CNT_OVF_ST = 0x400 + // Position of DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_Pos = 0xb + // Bit mask of DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST field. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_Msk = 0x800 + // Bit DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST. + EXTMEM_CACHE_ILG_INT_ST_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST = 0x800 + + // CORE0_ACS_CACHE_INT_ENA: ******* Description *********** + // Position of CORE0_IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA_Pos = 0x0 + // Bit mask of CORE0_IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA_Msk = 0x1 + // Bit CORE0_IBUS_ACS_MSK_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_ACS_MSK_IC_INT_ENA = 0x1 + // Position of CORE0_IBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA_Pos = 0x1 + // Bit mask of CORE0_IBUS_WR_IC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA_Msk = 0x2 + // Bit CORE0_IBUS_WR_IC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_WR_IC_INT_ENA = 0x2 + // Position of CORE0_IBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA_Pos = 0x2 + // Bit mask of CORE0_IBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA_Msk = 0x4 + // Bit CORE0_IBUS_REJECT_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_IBUS_REJECT_INT_ENA = 0x4 + // Position of CORE0_DBUS_ACS_MSK_DC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_DC_INT_ENA_Pos = 0x3 + // Bit mask of CORE0_DBUS_ACS_MSK_DC_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_DC_INT_ENA_Msk = 0x8 + // Bit CORE0_DBUS_ACS_MSK_DC_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_ACS_MSK_DC_INT_ENA = 0x8 + // Position of CORE0_DBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA_Pos = 0x4 + // Bit mask of CORE0_DBUS_REJECT_INT_ENA field. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA_Msk = 0x10 + // Bit CORE0_DBUS_REJECT_INT_ENA. + EXTMEM_CORE0_ACS_CACHE_INT_ENA_CORE0_DBUS_REJECT_INT_ENA = 0x10 + + // CORE0_ACS_CACHE_INT_CLR: ******* Description *********** + // Position of CORE0_IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR_Pos = 0x0 + // Bit mask of CORE0_IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR_Msk = 0x1 + // Bit CORE0_IBUS_ACS_MSK_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_ACS_MSK_IC_INT_CLR = 0x1 + // Position of CORE0_IBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR_Pos = 0x1 + // Bit mask of CORE0_IBUS_WR_IC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR_Msk = 0x2 + // Bit CORE0_IBUS_WR_IC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_WR_IC_INT_CLR = 0x2 + // Position of CORE0_IBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR_Pos = 0x2 + // Bit mask of CORE0_IBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR_Msk = 0x4 + // Bit CORE0_IBUS_REJECT_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_IBUS_REJECT_INT_CLR = 0x4 + // Position of CORE0_DBUS_ACS_MSK_DC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_DC_INT_CLR_Pos = 0x3 + // Bit mask of CORE0_DBUS_ACS_MSK_DC_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_DC_INT_CLR_Msk = 0x8 + // Bit CORE0_DBUS_ACS_MSK_DC_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_ACS_MSK_DC_INT_CLR = 0x8 + // Position of CORE0_DBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR_Pos = 0x4 + // Bit mask of CORE0_DBUS_REJECT_INT_CLR field. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR_Msk = 0x10 + // Bit CORE0_DBUS_REJECT_INT_CLR. + EXTMEM_CORE0_ACS_CACHE_INT_CLR_CORE0_DBUS_REJECT_INT_CLR = 0x10 + + // CORE0_ACS_CACHE_INT_ST: ******* Description *********** + // Position of CORE0_IBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST_Pos = 0x0 + // Bit mask of CORE0_IBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST_Msk = 0x1 + // Bit CORE0_IBUS_ACS_MSK_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_ACS_MSK_ICACHE_ST = 0x1 + // Position of CORE0_IBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST_Pos = 0x1 + // Bit mask of CORE0_IBUS_WR_ICACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST_Msk = 0x2 + // Bit CORE0_IBUS_WR_ICACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_WR_ICACHE_ST = 0x2 + // Position of CORE0_IBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST_Pos = 0x2 + // Bit mask of CORE0_IBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST_Msk = 0x4 + // Bit CORE0_IBUS_REJECT_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_IBUS_REJECT_ST = 0x4 + // Position of CORE0_DBUS_ACS_MSK_DCACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_DCACHE_ST_Pos = 0x3 + // Bit mask of CORE0_DBUS_ACS_MSK_DCACHE_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_DCACHE_ST_Msk = 0x8 + // Bit CORE0_DBUS_ACS_MSK_DCACHE_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_ACS_MSK_DCACHE_ST = 0x8 + // Position of CORE0_DBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST_Pos = 0x4 + // Bit mask of CORE0_DBUS_REJECT_ST field. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST_Msk = 0x10 + // Bit CORE0_DBUS_REJECT_ST. + EXTMEM_CORE0_ACS_CACHE_INT_ST_CORE0_DBUS_REJECT_ST = 0x10 + + // CORE1_ACS_CACHE_INT_ENA: ******* Description *********** + // Position of CORE1_IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_ACS_MSK_IC_INT_ENA_Pos = 0x0 + // Bit mask of CORE1_IBUS_ACS_MSK_IC_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_ACS_MSK_IC_INT_ENA_Msk = 0x1 + // Bit CORE1_IBUS_ACS_MSK_IC_INT_ENA. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_ACS_MSK_IC_INT_ENA = 0x1 + // Position of CORE1_IBUS_WR_IC_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_WR_IC_INT_ENA_Pos = 0x1 + // Bit mask of CORE1_IBUS_WR_IC_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_WR_IC_INT_ENA_Msk = 0x2 + // Bit CORE1_IBUS_WR_IC_INT_ENA. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_WR_IC_INT_ENA = 0x2 + // Position of CORE1_IBUS_REJECT_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_REJECT_INT_ENA_Pos = 0x2 + // Bit mask of CORE1_IBUS_REJECT_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_REJECT_INT_ENA_Msk = 0x4 + // Bit CORE1_IBUS_REJECT_INT_ENA. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_IBUS_REJECT_INT_ENA = 0x4 + // Position of CORE1_DBUS_ACS_MSK_DC_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_ACS_MSK_DC_INT_ENA_Pos = 0x3 + // Bit mask of CORE1_DBUS_ACS_MSK_DC_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_ACS_MSK_DC_INT_ENA_Msk = 0x8 + // Bit CORE1_DBUS_ACS_MSK_DC_INT_ENA. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_ACS_MSK_DC_INT_ENA = 0x8 + // Position of CORE1_DBUS_REJECT_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_REJECT_INT_ENA_Pos = 0x4 + // Bit mask of CORE1_DBUS_REJECT_INT_ENA field. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_REJECT_INT_ENA_Msk = 0x10 + // Bit CORE1_DBUS_REJECT_INT_ENA. + EXTMEM_CORE1_ACS_CACHE_INT_ENA_CORE1_DBUS_REJECT_INT_ENA = 0x10 + + // CORE1_ACS_CACHE_INT_CLR: ******* Description *********** + // Position of CORE1_IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_ACS_MSK_IC_INT_CLR_Pos = 0x0 + // Bit mask of CORE1_IBUS_ACS_MSK_IC_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_ACS_MSK_IC_INT_CLR_Msk = 0x1 + // Bit CORE1_IBUS_ACS_MSK_IC_INT_CLR. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_ACS_MSK_IC_INT_CLR = 0x1 + // Position of CORE1_IBUS_WR_IC_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_WR_IC_INT_CLR_Pos = 0x1 + // Bit mask of CORE1_IBUS_WR_IC_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_WR_IC_INT_CLR_Msk = 0x2 + // Bit CORE1_IBUS_WR_IC_INT_CLR. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_WR_IC_INT_CLR = 0x2 + // Position of CORE1_IBUS_REJECT_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_REJECT_INT_CLR_Pos = 0x2 + // Bit mask of CORE1_IBUS_REJECT_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_REJECT_INT_CLR_Msk = 0x4 + // Bit CORE1_IBUS_REJECT_INT_CLR. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_IBUS_REJECT_INT_CLR = 0x4 + // Position of CORE1_DBUS_ACS_MSK_DC_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_ACS_MSK_DC_INT_CLR_Pos = 0x3 + // Bit mask of CORE1_DBUS_ACS_MSK_DC_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_ACS_MSK_DC_INT_CLR_Msk = 0x8 + // Bit CORE1_DBUS_ACS_MSK_DC_INT_CLR. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_ACS_MSK_DC_INT_CLR = 0x8 + // Position of CORE1_DBUS_REJECT_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_REJECT_INT_CLR_Pos = 0x4 + // Bit mask of CORE1_DBUS_REJECT_INT_CLR field. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_REJECT_INT_CLR_Msk = 0x10 + // Bit CORE1_DBUS_REJECT_INT_CLR. + EXTMEM_CORE1_ACS_CACHE_INT_CLR_CORE1_DBUS_REJECT_INT_CLR = 0x10 + + // CORE1_ACS_CACHE_INT_ST: ******* Description *********** + // Position of CORE1_IBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_IBUS_ACS_MSK_ICACHE_ST_Pos = 0x0 + // Bit mask of CORE1_IBUS_ACS_MSK_ICACHE_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_IBUS_ACS_MSK_ICACHE_ST_Msk = 0x1 + // Bit CORE1_IBUS_ACS_MSK_ICACHE_ST. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_IBUS_ACS_MSK_ICACHE_ST = 0x1 + // Position of CORE1_IBUS_WR_ICACHE_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_IBUS_WR_ICACHE_ST_Pos = 0x1 + // Bit mask of CORE1_IBUS_WR_ICACHE_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_IBUS_WR_ICACHE_ST_Msk = 0x2 + // Bit CORE1_IBUS_WR_ICACHE_ST. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_IBUS_WR_ICACHE_ST = 0x2 + // Position of CORE1_IBUS_REJECT_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_IBUS_REJECT_ST_Pos = 0x2 + // Bit mask of CORE1_IBUS_REJECT_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_IBUS_REJECT_ST_Msk = 0x4 + // Bit CORE1_IBUS_REJECT_ST. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_IBUS_REJECT_ST = 0x4 + // Position of CORE1_DBUS_ACS_MSK_DCACHE_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_DBUS_ACS_MSK_DCACHE_ST_Pos = 0x3 + // Bit mask of CORE1_DBUS_ACS_MSK_DCACHE_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_DBUS_ACS_MSK_DCACHE_ST_Msk = 0x8 + // Bit CORE1_DBUS_ACS_MSK_DCACHE_ST. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_DBUS_ACS_MSK_DCACHE_ST = 0x8 + // Position of CORE1_DBUS_REJECT_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_DBUS_REJECT_ST_Pos = 0x4 + // Bit mask of CORE1_DBUS_REJECT_ST field. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_DBUS_REJECT_ST_Msk = 0x10 + // Bit CORE1_DBUS_REJECT_ST. + EXTMEM_CORE1_ACS_CACHE_INT_ST_CORE1_DBUS_REJECT_ST = 0x10 + + // CORE0_DBUS_REJECT_ST: ******* Description *********** + // Position of CORE0_DBUS_TAG_ATTR field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_TAG_ATTR_Pos = 0x0 + // Bit mask of CORE0_DBUS_TAG_ATTR field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_TAG_ATTR_Msk = 0x7 + // Position of CORE0_DBUS_ATTR field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR_Pos = 0x3 + // Bit mask of CORE0_DBUS_ATTR field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_ATTR_Msk = 0x38 + // Position of CORE0_DBUS_WORLD field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD_Pos = 0x6 + // Bit mask of CORE0_DBUS_WORLD field. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD_Msk = 0x40 + // Bit CORE0_DBUS_WORLD. + EXTMEM_CORE0_DBUS_REJECT_ST_CORE0_DBUS_WORLD = 0x40 + + // CORE0_DBUS_REJECT_VADDR: ******* Description *********** + // Position of CORE0_DBUS_VADDR field. + EXTMEM_CORE0_DBUS_REJECT_VADDR_CORE0_DBUS_VADDR_Pos = 0x0 + // Bit mask of CORE0_DBUS_VADDR field. + EXTMEM_CORE0_DBUS_REJECT_VADDR_CORE0_DBUS_VADDR_Msk = 0xffffffff + + // CORE0_IBUS_REJECT_ST: ******* Description *********** + // Position of CORE0_IBUS_TAG_ATTR field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_TAG_ATTR_Pos = 0x0 + // Bit mask of CORE0_IBUS_TAG_ATTR field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_TAG_ATTR_Msk = 0x7 + // Position of CORE0_IBUS_ATTR field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR_Pos = 0x3 + // Bit mask of CORE0_IBUS_ATTR field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_ATTR_Msk = 0x38 + // Position of CORE0_IBUS_WORLD field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD_Pos = 0x6 + // Bit mask of CORE0_IBUS_WORLD field. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD_Msk = 0x40 + // Bit CORE0_IBUS_WORLD. + EXTMEM_CORE0_IBUS_REJECT_ST_CORE0_IBUS_WORLD = 0x40 + + // CORE0_IBUS_REJECT_VADDR: ******* Description *********** + // Position of CORE0_IBUS_VADDR field. + EXTMEM_CORE0_IBUS_REJECT_VADDR_CORE0_IBUS_VADDR_Pos = 0x0 + // Bit mask of CORE0_IBUS_VADDR field. + EXTMEM_CORE0_IBUS_REJECT_VADDR_CORE0_IBUS_VADDR_Msk = 0xffffffff + + // CORE1_DBUS_REJECT_ST: ******* Description *********** + // Position of CORE1_DBUS_TAG_ATTR field. + EXTMEM_CORE1_DBUS_REJECT_ST_CORE1_DBUS_TAG_ATTR_Pos = 0x0 + // Bit mask of CORE1_DBUS_TAG_ATTR field. + EXTMEM_CORE1_DBUS_REJECT_ST_CORE1_DBUS_TAG_ATTR_Msk = 0x7 + // Position of CORE1_DBUS_ATTR field. + EXTMEM_CORE1_DBUS_REJECT_ST_CORE1_DBUS_ATTR_Pos = 0x3 + // Bit mask of CORE1_DBUS_ATTR field. + EXTMEM_CORE1_DBUS_REJECT_ST_CORE1_DBUS_ATTR_Msk = 0x38 + // Position of CORE1_DBUS_WORLD field. + EXTMEM_CORE1_DBUS_REJECT_ST_CORE1_DBUS_WORLD_Pos = 0x6 + // Bit mask of CORE1_DBUS_WORLD field. + EXTMEM_CORE1_DBUS_REJECT_ST_CORE1_DBUS_WORLD_Msk = 0x40 + // Bit CORE1_DBUS_WORLD. + EXTMEM_CORE1_DBUS_REJECT_ST_CORE1_DBUS_WORLD = 0x40 + + // CORE1_DBUS_REJECT_VADDR: ******* Description *********** + // Position of CORE1_DBUS_VADDR field. + EXTMEM_CORE1_DBUS_REJECT_VADDR_CORE1_DBUS_VADDR_Pos = 0x0 + // Bit mask of CORE1_DBUS_VADDR field. + EXTMEM_CORE1_DBUS_REJECT_VADDR_CORE1_DBUS_VADDR_Msk = 0xffffffff + + // CORE1_IBUS_REJECT_ST: ******* Description *********** + // Position of CORE1_IBUS_TAG_ATTR field. + EXTMEM_CORE1_IBUS_REJECT_ST_CORE1_IBUS_TAG_ATTR_Pos = 0x0 + // Bit mask of CORE1_IBUS_TAG_ATTR field. + EXTMEM_CORE1_IBUS_REJECT_ST_CORE1_IBUS_TAG_ATTR_Msk = 0x7 + // Position of CORE1_IBUS_ATTR field. + EXTMEM_CORE1_IBUS_REJECT_ST_CORE1_IBUS_ATTR_Pos = 0x3 + // Bit mask of CORE1_IBUS_ATTR field. + EXTMEM_CORE1_IBUS_REJECT_ST_CORE1_IBUS_ATTR_Msk = 0x38 + // Position of CORE1_IBUS_WORLD field. + EXTMEM_CORE1_IBUS_REJECT_ST_CORE1_IBUS_WORLD_Pos = 0x6 + // Bit mask of CORE1_IBUS_WORLD field. + EXTMEM_CORE1_IBUS_REJECT_ST_CORE1_IBUS_WORLD_Msk = 0x40 + // Bit CORE1_IBUS_WORLD. + EXTMEM_CORE1_IBUS_REJECT_ST_CORE1_IBUS_WORLD = 0x40 + + // CORE1_IBUS_REJECT_VADDR: ******* Description *********** + // Position of CORE1_IBUS_VADDR field. + EXTMEM_CORE1_IBUS_REJECT_VADDR_CORE1_IBUS_VADDR_Pos = 0x0 + // Bit mask of CORE1_IBUS_VADDR field. + EXTMEM_CORE1_IBUS_REJECT_VADDR_CORE1_IBUS_VADDR_Msk = 0xffffffff + + // CACHE_MMU_FAULT_CONTENT: ******* Description *********** + // Position of CACHE_MMU_FAULT_CONTENT field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CONTENT_Pos = 0x0 + // Bit mask of CACHE_MMU_FAULT_CONTENT field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CONTENT_Msk = 0xffff + // Position of CACHE_MMU_FAULT_CODE field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE_Pos = 0x10 + // Bit mask of CACHE_MMU_FAULT_CODE field. + EXTMEM_CACHE_MMU_FAULT_CONTENT_CACHE_MMU_FAULT_CODE_Msk = 0xf0000 + + // CACHE_MMU_FAULT_VADDR: ******* Description *********** + // Position of CACHE_MMU_FAULT_VADDR field. + EXTMEM_CACHE_MMU_FAULT_VADDR_CACHE_MMU_FAULT_VADDR_Pos = 0x0 + // Bit mask of CACHE_MMU_FAULT_VADDR field. + EXTMEM_CACHE_MMU_FAULT_VADDR_CACHE_MMU_FAULT_VADDR_Msk = 0xffffffff + + // CACHE_WRAP_AROUND_CTRL: ******* Description *********** + // Position of CACHE_FLASH_WRAP_AROUND field. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND_Pos = 0x0 + // Bit mask of CACHE_FLASH_WRAP_AROUND field. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND_Msk = 0x1 + // Bit CACHE_FLASH_WRAP_AROUND. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_FLASH_WRAP_AROUND = 0x1 + // Position of CACHE_SRAM_RD_WRAP_AROUND field. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_SRAM_RD_WRAP_AROUND_Pos = 0x1 + // Bit mask of CACHE_SRAM_RD_WRAP_AROUND field. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_SRAM_RD_WRAP_AROUND_Msk = 0x2 + // Bit CACHE_SRAM_RD_WRAP_AROUND. + EXTMEM_CACHE_WRAP_AROUND_CTRL_CACHE_SRAM_RD_WRAP_AROUND = 0x2 + + // CACHE_MMU_POWER_CTRL: ******* Description *********** + // Position of CACHE_MMU_MEM_FORCE_ON field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON_Pos = 0x0 + // Bit mask of CACHE_MMU_MEM_FORCE_ON field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON_Msk = 0x1 + // Bit CACHE_MMU_MEM_FORCE_ON. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_ON = 0x1 + // Position of CACHE_MMU_MEM_FORCE_PD field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD_Pos = 0x1 + // Bit mask of CACHE_MMU_MEM_FORCE_PD field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD_Msk = 0x2 + // Bit CACHE_MMU_MEM_FORCE_PD. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PD = 0x2 + // Position of CACHE_MMU_MEM_FORCE_PU field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU_Pos = 0x2 + // Bit mask of CACHE_MMU_MEM_FORCE_PU field. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU_Msk = 0x4 + // Bit CACHE_MMU_MEM_FORCE_PU. + EXTMEM_CACHE_MMU_POWER_CTRL_CACHE_MMU_MEM_FORCE_PU = 0x4 + + // CACHE_STATE: ******* Description *********** + // Position of ICACHE_STATE field. + EXTMEM_CACHE_STATE_ICACHE_STATE_Pos = 0x0 + // Bit mask of ICACHE_STATE field. + EXTMEM_CACHE_STATE_ICACHE_STATE_Msk = 0xfff + // Position of DCACHE_STATE field. + EXTMEM_CACHE_STATE_DCACHE_STATE_Pos = 0xc + // Bit mask of DCACHE_STATE field. + EXTMEM_CACHE_STATE_DCACHE_STATE_Msk = 0xfff000 + + // CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: ******* Description *********** + // Position of RECORD_DISABLE_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT_Pos = 0x0 + // Bit mask of RECORD_DISABLE_DB_ENCRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT_Msk = 0x1 + // Bit RECORD_DISABLE_DB_ENCRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_DB_ENCRYPT = 0x1 + // Position of RECORD_DISABLE_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT_Pos = 0x1 + // Bit mask of RECORD_DISABLE_G0CB_DECRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT_Msk = 0x2 + // Bit RECORD_DISABLE_G0CB_DECRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_RECORD_DISABLE_G0CB_DECRYPT = 0x2 + + // CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: ******* Description *********** + // Position of CLK_FORCE_ON_MANUAL_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT_Pos = 0x0 + // Bit mask of CLK_FORCE_ON_MANUAL_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT_Msk = 0x1 + // Bit CLK_FORCE_ON_MANUAL_CRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_MANUAL_CRYPT = 0x1 + // Position of CLK_FORCE_ON_AUTO_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT_Pos = 0x1 + // Bit mask of CLK_FORCE_ON_AUTO_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT_Msk = 0x2 + // Bit CLK_FORCE_ON_AUTO_CRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_AUTO_CRYPT = 0x2 + // Position of CLK_FORCE_ON_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT_Pos = 0x2 + // Bit mask of CLK_FORCE_ON_CRYPT field. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT_Msk = 0x4 + // Bit CLK_FORCE_ON_CRYPT. + EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_CLK_FORCE_ON_CRYPT = 0x4 + + // CACHE_BRIDGE_ARBITER_CTRL: ******* Description *********** + // Position of ALLOC_WB_HOLD_ARBITER field. + EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER_Pos = 0x0 + // Bit mask of ALLOC_WB_HOLD_ARBITER field. + EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER_Msk = 0x1 + // Bit ALLOC_WB_HOLD_ARBITER. + EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_ALLOC_WB_HOLD_ARBITER = 0x1 + + // CACHE_PRELOAD_INT_CTRL: ******* Description *********** + // Position of ICACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST_Msk = 0x1 + // Bit ICACHE_PRELOAD_INT_ST. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ST = 0x1 + // Position of ICACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA_Pos = 0x1 + // Bit mask of ICACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA_Msk = 0x2 + // Bit ICACHE_PRELOAD_INT_ENA. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_ENA = 0x2 + // Position of ICACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR_Pos = 0x2 + // Bit mask of ICACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR_Msk = 0x4 + // Bit ICACHE_PRELOAD_INT_CLR. + EXTMEM_CACHE_PRELOAD_INT_CTRL_ICACHE_PRELOAD_INT_CLR = 0x4 + // Position of DCACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ST_Pos = 0x3 + // Bit mask of DCACHE_PRELOAD_INT_ST field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ST_Msk = 0x8 + // Bit DCACHE_PRELOAD_INT_ST. + EXTMEM_CACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ST = 0x8 + // Position of DCACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ENA_Pos = 0x4 + // Bit mask of DCACHE_PRELOAD_INT_ENA field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ENA_Msk = 0x10 + // Bit DCACHE_PRELOAD_INT_ENA. + EXTMEM_CACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_ENA = 0x10 + // Position of DCACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_CLR_Pos = 0x5 + // Bit mask of DCACHE_PRELOAD_INT_CLR field. + EXTMEM_CACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_CLR_Msk = 0x20 + // Bit DCACHE_PRELOAD_INT_CLR. + EXTMEM_CACHE_PRELOAD_INT_CTRL_DCACHE_PRELOAD_INT_CLR = 0x20 + + // CACHE_SYNC_INT_CTRL: ******* Description *********** + // Position of ICACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST_Pos = 0x0 + // Bit mask of ICACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST_Msk = 0x1 + // Bit ICACHE_SYNC_INT_ST. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ST = 0x1 + // Position of ICACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA_Pos = 0x1 + // Bit mask of ICACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA_Msk = 0x2 + // Bit ICACHE_SYNC_INT_ENA. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_ENA = 0x2 + // Position of ICACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR_Pos = 0x2 + // Bit mask of ICACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR_Msk = 0x4 + // Bit ICACHE_SYNC_INT_CLR. + EXTMEM_CACHE_SYNC_INT_CTRL_ICACHE_SYNC_INT_CLR = 0x4 + // Position of DCACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ST_Pos = 0x3 + // Bit mask of DCACHE_SYNC_INT_ST field. + EXTMEM_CACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ST_Msk = 0x8 + // Bit DCACHE_SYNC_INT_ST. + EXTMEM_CACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ST = 0x8 + // Position of DCACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ENA_Pos = 0x4 + // Bit mask of DCACHE_SYNC_INT_ENA field. + EXTMEM_CACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ENA_Msk = 0x10 + // Bit DCACHE_SYNC_INT_ENA. + EXTMEM_CACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_ENA = 0x10 + // Position of DCACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_CLR_Pos = 0x5 + // Bit mask of DCACHE_SYNC_INT_CLR field. + EXTMEM_CACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_CLR_Msk = 0x20 + // Bit DCACHE_SYNC_INT_CLR. + EXTMEM_CACHE_SYNC_INT_CTRL_DCACHE_SYNC_INT_CLR = 0x20 + + // CACHE_MMU_OWNER: ******* Description *********** + // Position of CACHE_MMU_OWNER field. + EXTMEM_CACHE_MMU_OWNER_CACHE_MMU_OWNER_Pos = 0x0 + // Bit mask of CACHE_MMU_OWNER field. + EXTMEM_CACHE_MMU_OWNER_CACHE_MMU_OWNER_Msk = 0xffffff + + // CACHE_CONF_MISC: ******* Description *********** + // Position of CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_Pos = 0x0 + // Bit mask of CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_Msk = 0x1 + // Bit CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT = 0x1 + // Position of CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_Pos = 0x1 + // Bit mask of CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT field. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_Msk = 0x2 + // Bit CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT. + EXTMEM_CACHE_CONF_MISC_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT = 0x2 + // Position of CACHE_TRACE_ENA field. + EXTMEM_CACHE_CONF_MISC_CACHE_TRACE_ENA_Pos = 0x2 + // Bit mask of CACHE_TRACE_ENA field. + EXTMEM_CACHE_CONF_MISC_CACHE_TRACE_ENA_Msk = 0x4 + // Bit CACHE_TRACE_ENA. + EXTMEM_CACHE_CONF_MISC_CACHE_TRACE_ENA = 0x4 + + // DCACHE_FREEZE: ******* Description *********** + // Position of ENA field. + EXTMEM_DCACHE_FREEZE_ENA_Pos = 0x0 + // Bit mask of ENA field. + EXTMEM_DCACHE_FREEZE_ENA_Msk = 0x1 + // Bit ENA. + EXTMEM_DCACHE_FREEZE_ENA = 0x1 + // Position of MODE field. + EXTMEM_DCACHE_FREEZE_MODE_Pos = 0x1 + // Bit mask of MODE field. + EXTMEM_DCACHE_FREEZE_MODE_Msk = 0x2 + // Bit MODE. + EXTMEM_DCACHE_FREEZE_MODE = 0x2 + // Position of DONE field. + EXTMEM_DCACHE_FREEZE_DONE_Pos = 0x2 + // Bit mask of DONE field. + EXTMEM_DCACHE_FREEZE_DONE_Msk = 0x4 + // Bit DONE. + EXTMEM_DCACHE_FREEZE_DONE = 0x4 + + // ICACHE_FREEZE: ******* Description *********** + // Position of ENA field. + EXTMEM_ICACHE_FREEZE_ENA_Pos = 0x0 + // Bit mask of ENA field. + EXTMEM_ICACHE_FREEZE_ENA_Msk = 0x1 + // Bit ENA. + EXTMEM_ICACHE_FREEZE_ENA = 0x1 + // Position of MODE field. + EXTMEM_ICACHE_FREEZE_MODE_Pos = 0x1 + // Bit mask of MODE field. + EXTMEM_ICACHE_FREEZE_MODE_Msk = 0x2 + // Bit MODE. + EXTMEM_ICACHE_FREEZE_MODE = 0x2 + // Position of DONE field. + EXTMEM_ICACHE_FREEZE_DONE_Pos = 0x2 + // Bit mask of DONE field. + EXTMEM_ICACHE_FREEZE_DONE_Msk = 0x4 + // Bit DONE. + EXTMEM_ICACHE_FREEZE_DONE = 0x4 + + // ICACHE_ATOMIC_OPERATE_ENA: ******* Description *********** + // Position of ICACHE_ATOMIC_OPERATE_ENA field. + EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_ICACHE_ATOMIC_OPERATE_ENA_Pos = 0x0 + // Bit mask of ICACHE_ATOMIC_OPERATE_ENA field. + EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_ICACHE_ATOMIC_OPERATE_ENA_Msk = 0x1 + // Bit ICACHE_ATOMIC_OPERATE_ENA. + EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_ICACHE_ATOMIC_OPERATE_ENA = 0x1 + + // DCACHE_ATOMIC_OPERATE_ENA: ******* Description *********** + // Position of DCACHE_ATOMIC_OPERATE_ENA field. + EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_DCACHE_ATOMIC_OPERATE_ENA_Pos = 0x0 + // Bit mask of DCACHE_ATOMIC_OPERATE_ENA field. + EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_DCACHE_ATOMIC_OPERATE_ENA_Msk = 0x1 + // Bit DCACHE_ATOMIC_OPERATE_ENA. + EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_DCACHE_ATOMIC_OPERATE_ENA = 0x1 + + // CACHE_REQUEST: ******* Description *********** + // Position of BYPASS field. + EXTMEM_CACHE_REQUEST_BYPASS_Pos = 0x0 + // Bit mask of BYPASS field. + EXTMEM_CACHE_REQUEST_BYPASS_Msk = 0x1 + // Bit BYPASS. + EXTMEM_CACHE_REQUEST_BYPASS = 0x1 + + // CLOCK_GATE: ******* Description *********** + // Position of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + EXTMEM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + EXTMEM_CLOCK_GATE_CLK_EN = 0x1 + + // CACHE_TAG_OBJECT_CTRL: ******* Description *********** + // Position of ICACHE_TAG_OBJECT field. + EXTMEM_CACHE_TAG_OBJECT_CTRL_ICACHE_TAG_OBJECT_Pos = 0x0 + // Bit mask of ICACHE_TAG_OBJECT field. + EXTMEM_CACHE_TAG_OBJECT_CTRL_ICACHE_TAG_OBJECT_Msk = 0x1 + // Bit ICACHE_TAG_OBJECT. + EXTMEM_CACHE_TAG_OBJECT_CTRL_ICACHE_TAG_OBJECT = 0x1 + // Position of DCACHE_TAG_OBJECT field. + EXTMEM_CACHE_TAG_OBJECT_CTRL_DCACHE_TAG_OBJECT_Pos = 0x1 + // Bit mask of DCACHE_TAG_OBJECT field. + EXTMEM_CACHE_TAG_OBJECT_CTRL_DCACHE_TAG_OBJECT_Msk = 0x2 + // Bit DCACHE_TAG_OBJECT. + EXTMEM_CACHE_TAG_OBJECT_CTRL_DCACHE_TAG_OBJECT = 0x2 + + // CACHE_TAG_WAY_OBJECT: ******* Description *********** + // Position of CACHE_TAG_WAY_OBJECT field. + EXTMEM_CACHE_TAG_WAY_OBJECT_CACHE_TAG_WAY_OBJECT_Pos = 0x0 + // Bit mask of CACHE_TAG_WAY_OBJECT field. + EXTMEM_CACHE_TAG_WAY_OBJECT_CACHE_TAG_WAY_OBJECT_Msk = 0x7 + + // CACHE_VADDR: ******* Description *********** + // Position of CACHE_VADDR field. + EXTMEM_CACHE_VADDR_CACHE_VADDR_Pos = 0x0 + // Bit mask of CACHE_VADDR field. + EXTMEM_CACHE_VADDR_CACHE_VADDR_Msk = 0xffffffff + + // CACHE_TAG_CONTENT: ******* Description *********** + // Position of CACHE_TAG_CONTENT field. + EXTMEM_CACHE_TAG_CONTENT_CACHE_TAG_CONTENT_Pos = 0x0 + // Bit mask of CACHE_TAG_CONTENT field. + EXTMEM_CACHE_TAG_CONTENT_CACHE_TAG_CONTENT_Msk = 0xffffffff + + // DATE: ******* Description *********** + // Position of DATE field. + EXTMEM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + EXTMEM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for GPIO: General Purpose Input/Output +const ( + // BT_SELECT: GPIO bit select register + // Position of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Pos = 0x0 + // Bit mask of BT_SEL field. + GPIO_BT_SELECT_BT_SEL_Msk = 0xffffffff + + // OUT: GPIO output register for GPIO0-31 + // Position of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Pos = 0x0 + // Bit mask of DATA_ORIG field. + GPIO_OUT_DATA_ORIG_Msk = 0xffffffff + + // OUT_W1TS: GPIO output set register for GPIO0-31 + // Position of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Pos = 0x0 + // Bit mask of OUT_W1TS field. + GPIO_OUT_W1TS_OUT_W1TS_Msk = 0xffffffff + + // OUT_W1TC: GPIO output clear register for GPIO0-31 + // Position of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Pos = 0x0 + // Bit mask of OUT_W1TC field. + GPIO_OUT_W1TC_OUT_W1TC_Msk = 0xffffffff + + // OUT1: GPIO output register for GPIO32-53 + // Position of DATA_ORIG field. + GPIO_OUT1_DATA_ORIG_Pos = 0x0 + // Bit mask of DATA_ORIG field. + GPIO_OUT1_DATA_ORIG_Msk = 0x3fffff + + // OUT1_W1TS: GPIO output set register for GPIO32-53 + // Position of OUT1_W1TS field. + GPIO_OUT1_W1TS_OUT1_W1TS_Pos = 0x0 + // Bit mask of OUT1_W1TS field. + GPIO_OUT1_W1TS_OUT1_W1TS_Msk = 0x3fffff + + // OUT1_W1TC: GPIO output clear register for GPIO32-53 + // Position of OUT1_W1TC field. + GPIO_OUT1_W1TC_OUT1_W1TC_Pos = 0x0 + // Bit mask of OUT1_W1TC field. + GPIO_OUT1_W1TC_OUT1_W1TC_Msk = 0x3fffff + + // SDIO_SELECT: GPIO sdio select register + // Position of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Pos = 0x0 + // Bit mask of SDIO_SEL field. + GPIO_SDIO_SELECT_SDIO_SEL_Msk = 0xff + + // ENABLE: GPIO output enable register for GPIO0-31 + // Position of DATA field. + GPIO_ENABLE_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE_DATA_Msk = 0xffffffff + + // ENABLE_W1TS: GPIO output enable set register for GPIO0-31 + // Position of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Pos = 0x0 + // Bit mask of ENABLE_W1TS field. + GPIO_ENABLE_W1TS_ENABLE_W1TS_Msk = 0xffffffff + + // ENABLE_W1TC: GPIO output enable clear register for GPIO0-31 + // Position of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0x0 + // Bit mask of ENABLE_W1TC field. + GPIO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0xffffffff + + // ENABLE1: GPIO output enable register for GPIO32-53 + // Position of DATA field. + GPIO_ENABLE1_DATA_Pos = 0x0 + // Bit mask of DATA field. + GPIO_ENABLE1_DATA_Msk = 0x3fffff + + // ENABLE1_W1TS: GPIO output enable set register for GPIO32-53 + // Position of ENABLE1_W1TS field. + GPIO_ENABLE1_W1TS_ENABLE1_W1TS_Pos = 0x0 + // Bit mask of ENABLE1_W1TS field. + GPIO_ENABLE1_W1TS_ENABLE1_W1TS_Msk = 0x3fffff + + // ENABLE1_W1TC: GPIO output enable clear register for GPIO32-53 + // Position of ENABLE1_W1TC field. + GPIO_ENABLE1_W1TC_ENABLE1_W1TC_Pos = 0x0 + // Bit mask of ENABLE1_W1TC field. + GPIO_ENABLE1_W1TC_ENABLE1_W1TC_Msk = 0x3fffff + + // STRAP: pad strapping register + // Position of STRAPPING field. + GPIO_STRAP_STRAPPING_Pos = 0x0 + // Bit mask of STRAPPING field. + GPIO_STRAP_STRAPPING_Msk = 0xffff + + // IN: GPIO input register for GPIO0-31 + // Position of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN_DATA_NEXT_Msk = 0xffffffff + + // IN1: GPIO input register for GPIO32-53 + // Position of DATA_NEXT field. + GPIO_IN1_DATA_NEXT_Pos = 0x0 + // Bit mask of DATA_NEXT field. + GPIO_IN1_DATA_NEXT_Msk = 0x3fffff + + // STATUS: GPIO interrupt status register for GPIO0-31 + // Position of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + GPIO_STATUS_INTERRUPT_Msk = 0xffffffff + + // STATUS_W1TS: GPIO interrupt status set register for GPIO0-31 + // Position of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Pos = 0x0 + // Bit mask of STATUS_W1TS field. + GPIO_STATUS_W1TS_STATUS_W1TS_Msk = 0xffffffff + + // STATUS_W1TC: GPIO interrupt status clear register for GPIO0-31 + // Position of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Pos = 0x0 + // Bit mask of STATUS_W1TC field. + GPIO_STATUS_W1TC_STATUS_W1TC_Msk = 0xffffffff + + // STATUS1: GPIO interrupt status register for GPIO32-53 + // Position of INTERRUPT field. + GPIO_STATUS1_INTERRUPT_Pos = 0x0 + // Bit mask of INTERRUPT field. + GPIO_STATUS1_INTERRUPT_Msk = 0x3fffff + + // STATUS1_W1TS: GPIO interrupt status set register for GPIO32-53 + // Position of STATUS1_W1TS field. + GPIO_STATUS1_W1TS_STATUS1_W1TS_Pos = 0x0 + // Bit mask of STATUS1_W1TS field. + GPIO_STATUS1_W1TS_STATUS1_W1TS_Msk = 0x3fffff + + // STATUS1_W1TC: GPIO interrupt status clear register for GPIO32-53 + // Position of STATUS1_W1TC field. + GPIO_STATUS1_W1TC_STATUS1_W1TC_Pos = 0x0 + // Bit mask of STATUS1_W1TC field. + GPIO_STATUS1_W1TC_STATUS1_W1TC_Msk = 0x3fffff + + // PCPU_INT: GPIO PRO_CPU interrupt status register for GPIO0-31 + // Position of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Pos = 0x0 + // Bit mask of PROCPU_INT field. + GPIO_PCPU_INT_PROCPU_INT_Msk = 0xffffffff + + // PCPU_NMI_INT: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + // Position of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT field. + GPIO_PCPU_NMI_INT_PROCPU_NMI_INT_Msk = 0xffffffff + + // CPUSDIO_INT: GPIO CPUSDIO interrupt status register for GPIO0-31 + // Position of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Pos = 0x0 + // Bit mask of SDIO_INT field. + GPIO_CPUSDIO_INT_SDIO_INT_Msk = 0xffffffff + + // PCPU_INT1: GPIO PRO_CPU interrupt status register for GPIO32-53 + // Position of PROCPU_INT1 field. + GPIO_PCPU_INT1_PROCPU_INT1_Pos = 0x0 + // Bit mask of PROCPU_INT1 field. + GPIO_PCPU_INT1_PROCPU_INT1_Msk = 0x3fffff + + // PCPU_NMI_INT1: GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 + // Position of PROCPU_NMI_INT1 field. + GPIO_PCPU_NMI_INT1_PROCPU_NMI_INT1_Pos = 0x0 + // Bit mask of PROCPU_NMI_INT1 field. + GPIO_PCPU_NMI_INT1_PROCPU_NMI_INT1_Msk = 0x3fffff + + // CPUSDIO_INT1: GPIO CPUSDIO interrupt status register for GPIO32-53 + // Position of SDIO_INT1 field. + GPIO_CPUSDIO_INT1_SDIO_INT1_Pos = 0x0 + // Bit mask of SDIO_INT1 field. + GPIO_CPUSDIO_INT1_SDIO_INT1_Msk = 0x3fffff + + // PIN0: GPIO pin configuration register + // Position of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Pos = 0x0 + // Bit mask of SYNC2_BYPASS field. + GPIO_PIN_SYNC2_BYPASS_Msk = 0x3 + // Position of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + GPIO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + GPIO_PIN_PAD_DRIVER = 0x4 + // Position of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Pos = 0x3 + // Bit mask of SYNC1_BYPASS field. + GPIO_PIN_SYNC1_BYPASS_Msk = 0x18 + // Position of INT_TYPE field. + GPIO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + GPIO_PIN_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + GPIO_PIN_WAKEUP_ENABLE = 0x400 + // Position of CONFIG field. + GPIO_PIN_CONFIG_Pos = 0xb + // Bit mask of CONFIG field. + GPIO_PIN_CONFIG_Msk = 0x1800 + // Position of INT_ENA field. + GPIO_PIN_INT_ENA_Pos = 0xd + // Bit mask of INT_ENA field. + GPIO_PIN_INT_ENA_Msk = 0x3e000 + + // STATUS_NEXT: GPIO interrupt source register for GPIO0-31 + // Position of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Pos = 0x0 + // Bit mask of STATUS_INTERRUPT_NEXT field. + GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Msk = 0xffffffff + + // STATUS_NEXT1: GPIO interrupt source register for GPIO32-53 + // Position of STATUS_INTERRUPT_NEXT1 field. + GPIO_STATUS_NEXT1_STATUS_INTERRUPT_NEXT1_Pos = 0x0 + // Bit mask of STATUS_INTERRUPT_NEXT1 field. + GPIO_STATUS_NEXT1_STATUS_INTERRUPT_NEXT1_Msk = 0x3fffff + + // FUNC0_IN_SEL_CFG: GPIO input function configuration register + // Position of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Pos = 0x0 + // Bit mask of IN_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_SEL_Msk = 0x3f + // Position of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Pos = 0x6 + // Bit mask of IN_INV_SEL field. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Msk = 0x40 + // Bit IN_INV_SEL. + GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL = 0x40 + // Position of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Pos = 0x7 + // Bit mask of SEL field. + GPIO_FUNC_IN_SEL_CFG_SEL_Msk = 0x80 + // Bit SEL. + GPIO_FUNC_IN_SEL_CFG_SEL = 0x80 + + // FUNC0_OUT_SEL_CFG: GPIO output function select register + // Position of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Pos = 0x0 + // Bit mask of OUT_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Msk = 0x1ff + // Position of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Pos = 0x9 + // Bit mask of INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Msk = 0x200 + // Bit INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_INV_SEL = 0x200 + // Position of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Pos = 0xa + // Bit mask of OEN_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Msk = 0x400 + // Bit OEN_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_SEL = 0x400 + // Position of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Pos = 0xb + // Bit mask of OEN_INV_SEL field. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Msk = 0x800 + // Bit OEN_INV_SEL. + GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL = 0x800 + + // CLOCK_GATE: GPIO clock gate register + // Position of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + GPIO_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + GPIO_CLOCK_GATE_CLK_EN = 0x1 + + // REG_DATE: GPIO version register + // Position of REG_DATE field. + GPIO_REG_DATE_REG_DATE_Pos = 0x0 + // Bit mask of REG_DATE field. + GPIO_REG_DATE_REG_DATE_Msk = 0xfffffff +) + +// Constants for GPIO_SD: Sigma-Delta Modulation +const ( + // SIGMADELTA0: Duty Cycle Configure Register of SDM%s + // Position of SD_IN field. + GPIOSD_SIGMADELTA_SD_IN_Pos = 0x0 + // Bit mask of SD_IN field. + GPIOSD_SIGMADELTA_SD_IN_Msk = 0xff + // Position of SD_PRESCALE field. + GPIOSD_SIGMADELTA_SD_PRESCALE_Pos = 0x8 + // Bit mask of SD_PRESCALE field. + GPIOSD_SIGMADELTA_SD_PRESCALE_Msk = 0xff00 + + // SIGMADELTA_CG: Clock Gating Configure Register + // Position of CLK_EN field. + GPIOSD_SIGMADELTA_CG_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + GPIOSD_SIGMADELTA_CG_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + GPIOSD_SIGMADELTA_CG_CLK_EN = 0x80000000 + + // SIGMADELTA_MISC: MISC Register + // Position of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Pos = 0x1e + // Bit mask of FUNCTION_CLK_EN field. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Msk = 0x40000000 + // Bit FUNCTION_CLK_EN. + GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN = 0x40000000 + // Position of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Pos = 0x1f + // Bit mask of SPI_SWAP field. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Msk = 0x80000000 + // Bit SPI_SWAP. + GPIOSD_SIGMADELTA_MISC_SPI_SWAP = 0x80000000 + + // SIGMADELTA_VERSION: Version Control Register + // Position of GPIO_SD_DATE field. + GPIOSD_SIGMADELTA_VERSION_GPIO_SD_DATE_Pos = 0x0 + // Bit mask of GPIO_SD_DATE field. + GPIOSD_SIGMADELTA_VERSION_GPIO_SD_DATE_Msk = 0xfffffff +) + +// Constants for HMAC: HMAC (Hash-based Message Authentication Code) Accelerator +const ( + // SET_START: Process control register 0. + // Position of SET_START field. + HMAC_SET_START_SET_START_Pos = 0x0 + // Bit mask of SET_START field. + HMAC_SET_START_SET_START_Msk = 0x1 + // Bit SET_START. + HMAC_SET_START_SET_START = 0x1 + + // SET_PARA_PURPOSE: Configure purpose. + // Position of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Pos = 0x0 + // Bit mask of PURPOSE_SET field. + HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Msk = 0xf + + // SET_PARA_KEY: Configure key. + // Position of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Pos = 0x0 + // Bit mask of KEY_SET field. + HMAC_SET_PARA_KEY_KEY_SET_Msk = 0x7 + + // SET_PARA_FINISH: Finish initial configuration. + // Position of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Pos = 0x0 + // Bit mask of SET_PARA_END field. + HMAC_SET_PARA_FINISH_SET_PARA_END_Msk = 0x1 + // Bit SET_PARA_END. + HMAC_SET_PARA_FINISH_SET_PARA_END = 0x1 + + // SET_MESSAGE_ONE: Process control register 1. + // Position of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Pos = 0x0 + // Bit mask of SET_TEXT_ONE field. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Msk = 0x1 + // Bit SET_TEXT_ONE. + HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE = 0x1 + + // SET_MESSAGE_ING: Process control register 2. + // Position of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Pos = 0x0 + // Bit mask of SET_TEXT_ING field. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Msk = 0x1 + // Bit SET_TEXT_ING. + HMAC_SET_MESSAGE_ING_SET_TEXT_ING = 0x1 + + // SET_MESSAGE_END: Process control register 3. + // Position of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Pos = 0x0 + // Bit mask of SET_TEXT_END field. + HMAC_SET_MESSAGE_END_SET_TEXT_END_Msk = 0x1 + // Bit SET_TEXT_END. + HMAC_SET_MESSAGE_END_SET_TEXT_END = 0x1 + + // SET_RESULT_FINISH: Process control register 4. + // Position of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Pos = 0x0 + // Bit mask of SET_RESULT_END field. + HMAC_SET_RESULT_FINISH_SET_RESULT_END_Msk = 0x1 + // Bit SET_RESULT_END. + HMAC_SET_RESULT_FINISH_SET_RESULT_END = 0x1 + + // SET_INVALIDATE_JTAG: Invalidate register 0. + // Position of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Pos = 0x0 + // Bit mask of SET_INVALIDATE_JTAG field. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Msk = 0x1 + // Bit SET_INVALIDATE_JTAG. + HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG = 0x1 + + // SET_INVALIDATE_DS: Invalidate register 1. + // Position of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Pos = 0x0 + // Bit mask of SET_INVALIDATE_DS field. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Msk = 0x1 + // Bit SET_INVALIDATE_DS. + HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS = 0x1 + + // QUERY_ERROR: Error register. + // Position of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Pos = 0x0 + // Bit mask of QUERY_CHECK field. + HMAC_QUERY_ERROR_QUERY_CHECK_Msk = 0x1 + // Bit QUERY_CHECK. + HMAC_QUERY_ERROR_QUERY_CHECK = 0x1 + + // QUERY_BUSY: Busy register. + // Position of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Pos = 0x0 + // Bit mask of BUSY_STATE field. + HMAC_QUERY_BUSY_BUSY_STATE_Msk = 0x1 + // Bit BUSY_STATE. + HMAC_QUERY_BUSY_BUSY_STATE = 0x1 + + // SET_MESSAGE_PAD: Process control register 5. + // Position of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Pos = 0x0 + // Bit mask of SET_TEXT_PAD field. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Msk = 0x1 + // Bit SET_TEXT_PAD. + HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD = 0x1 + + // ONE_BLOCK: Process control register 6. + // Position of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Pos = 0x0 + // Bit mask of SET_ONE_BLOCK field. + HMAC_ONE_BLOCK_SET_ONE_BLOCK_Msk = 0x1 + // Bit SET_ONE_BLOCK. + HMAC_ONE_BLOCK_SET_ONE_BLOCK = 0x1 + + // SOFT_JTAG_CTRL: Jtag register 0. + // Position of SOFT_JTAG_CTRL field. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Pos = 0x0 + // Bit mask of SOFT_JTAG_CTRL field. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Msk = 0x1 + // Bit SOFT_JTAG_CTRL. + HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL = 0x1 + + // WR_JTAG: Jtag register 1. + // Position of WR_JTAG field. + HMAC_WR_JTAG_WR_JTAG_Pos = 0x0 + // Bit mask of WR_JTAG field. + HMAC_WR_JTAG_WR_JTAG_Msk = 0xffffffff + + // DATE: Date register. + // Position of DATE field. + HMAC_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + HMAC_DATE_DATE_Msk = 0xfffffff +) + +// Constants for I2C0: I2C (Inter-Integrated Circuit) Controller 0 +const ( + // SCL_LOW_PERIOD: Configures the low level width of the SCL Clock + // Position of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of SCL_LOW_PERIOD field. + I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x1ff + + // CTR: Transmission setting + // Position of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + I2C_CTR_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + I2C_CTR_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + I2C_CTR_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + I2C_CTR_SCL_FORCE_OUT = 0x2 + // Position of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2 + // Bit mask of SAMPLE_SCL_LEVEL field. + I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4 + // Bit SAMPLE_SCL_LEVEL. + I2C_CTR_SAMPLE_SCL_LEVEL = 0x4 + // Position of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Pos = 0x3 + // Bit mask of RX_FULL_ACK_LEVEL field. + I2C_CTR_RX_FULL_ACK_LEVEL_Msk = 0x8 + // Bit RX_FULL_ACK_LEVEL. + I2C_CTR_RX_FULL_ACK_LEVEL = 0x8 + // Position of MS_MODE field. + I2C_CTR_MS_MODE_Pos = 0x4 + // Bit mask of MS_MODE field. + I2C_CTR_MS_MODE_Msk = 0x10 + // Bit MS_MODE. + I2C_CTR_MS_MODE = 0x10 + // Position of TRANS_START field. + I2C_CTR_TRANS_START_Pos = 0x5 + // Bit mask of TRANS_START field. + I2C_CTR_TRANS_START_Msk = 0x20 + // Bit TRANS_START. + I2C_CTR_TRANS_START = 0x20 + // Position of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Pos = 0x6 + // Bit mask of TX_LSB_FIRST field. + I2C_CTR_TX_LSB_FIRST_Msk = 0x40 + // Bit TX_LSB_FIRST. + I2C_CTR_TX_LSB_FIRST = 0x40 + // Position of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Pos = 0x7 + // Bit mask of RX_LSB_FIRST field. + I2C_CTR_RX_LSB_FIRST_Msk = 0x80 + // Bit RX_LSB_FIRST. + I2C_CTR_RX_LSB_FIRST = 0x80 + // Position of CLK_EN field. + I2C_CTR_CLK_EN_Pos = 0x8 + // Bit mask of CLK_EN field. + I2C_CTR_CLK_EN_Msk = 0x100 + // Bit CLK_EN. + I2C_CTR_CLK_EN = 0x100 + // Position of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Pos = 0x9 + // Bit mask of ARBITRATION_EN field. + I2C_CTR_ARBITRATION_EN_Msk = 0x200 + // Bit ARBITRATION_EN. + I2C_CTR_ARBITRATION_EN = 0x200 + // Position of FSM_RST field. + I2C_CTR_FSM_RST_Pos = 0xa + // Bit mask of FSM_RST field. + I2C_CTR_FSM_RST_Msk = 0x400 + // Bit FSM_RST. + I2C_CTR_FSM_RST = 0x400 + // Position of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Pos = 0xb + // Bit mask of CONF_UPGATE field. + I2C_CTR_CONF_UPGATE_Msk = 0x800 + // Bit CONF_UPGATE. + I2C_CTR_CONF_UPGATE = 0x800 + // Position of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Pos = 0xc + // Bit mask of SLV_TX_AUTO_START_EN field. + I2C_CTR_SLV_TX_AUTO_START_EN_Msk = 0x1000 + // Bit SLV_TX_AUTO_START_EN. + I2C_CTR_SLV_TX_AUTO_START_EN = 0x1000 + // Position of ADDR_10BIT_RW_CHECK_EN field. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Pos = 0xd + // Bit mask of ADDR_10BIT_RW_CHECK_EN field. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Msk = 0x2000 + // Bit ADDR_10BIT_RW_CHECK_EN. + I2C_CTR_ADDR_10BIT_RW_CHECK_EN = 0x2000 + // Position of ADDR_BROADCASTING_EN field. + I2C_CTR_ADDR_BROADCASTING_EN_Pos = 0xe + // Bit mask of ADDR_BROADCASTING_EN field. + I2C_CTR_ADDR_BROADCASTING_EN_Msk = 0x4000 + // Bit ADDR_BROADCASTING_EN. + I2C_CTR_ADDR_BROADCASTING_EN = 0x4000 + + // SR: Describe I2C work status. + // Position of RESP_REC field. + I2C_SR_RESP_REC_Pos = 0x0 + // Bit mask of RESP_REC field. + I2C_SR_RESP_REC_Msk = 0x1 + // Bit RESP_REC. + I2C_SR_RESP_REC = 0x1 + // Position of SLAVE_RW field. + I2C_SR_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + I2C_SR_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + I2C_SR_SLAVE_RW = 0x2 + // Position of ARB_LOST field. + I2C_SR_ARB_LOST_Pos = 0x3 + // Bit mask of ARB_LOST field. + I2C_SR_ARB_LOST_Msk = 0x8 + // Bit ARB_LOST. + I2C_SR_ARB_LOST = 0x8 + // Position of BUS_BUSY field. + I2C_SR_BUS_BUSY_Pos = 0x4 + // Bit mask of BUS_BUSY field. + I2C_SR_BUS_BUSY_Msk = 0x10 + // Bit BUS_BUSY. + I2C_SR_BUS_BUSY = 0x10 + // Position of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Pos = 0x5 + // Bit mask of SLAVE_ADDRESSED field. + I2C_SR_SLAVE_ADDRESSED_Msk = 0x20 + // Bit SLAVE_ADDRESSED. + I2C_SR_SLAVE_ADDRESSED = 0x20 + // Position of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Pos = 0x8 + // Bit mask of RXFIFO_CNT field. + I2C_SR_RXFIFO_CNT_Msk = 0x3f00 + // Position of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Pos = 0xe + // Bit mask of STRETCH_CAUSE field. + I2C_SR_STRETCH_CAUSE_Msk = 0xc000 + // Position of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Pos = 0x12 + // Bit mask of TXFIFO_CNT field. + I2C_SR_TXFIFO_CNT_Msk = 0xfc0000 + // Position of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + I2C_SR_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: Setting time out control for receiving data. + // Position of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Pos = 0x0 + // Bit mask of TIME_OUT_VALUE field. + I2C_TO_TIME_OUT_VALUE_Msk = 0x1f + // Position of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Pos = 0x5 + // Bit mask of TIME_OUT_EN field. + I2C_TO_TIME_OUT_EN_Msk = 0x20 + // Bit TIME_OUT_EN. + I2C_TO_TIME_OUT_EN = 0x20 + + // SLAVE_ADDR: Local slave address setting + // Position of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // FIFO_ST: FIFO status register. + // Position of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Pos = 0x0 + // Bit mask of RXFIFO_RADDR field. + I2C_FIFO_ST_RXFIFO_RADDR_Msk = 0x1f + // Position of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Pos = 0x5 + // Bit mask of RXFIFO_WADDR field. + I2C_FIFO_ST_RXFIFO_WADDR_Msk = 0x3e0 + // Position of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Pos = 0xa + // Bit mask of TXFIFO_RADDR field. + I2C_FIFO_ST_TXFIFO_RADDR_Msk = 0x7c00 + // Position of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Pos = 0xf + // Bit mask of TXFIFO_WADDR field. + I2C_FIFO_ST_TXFIFO_WADDR_Msk = 0xf8000 + // Position of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Pos = 0x16 + // Bit mask of SLAVE_RW_POINT field. + I2C_FIFO_ST_SLAVE_RW_POINT_Msk = 0x3fc00000 + + // FIFO_CONF: FIFO configuration register. + // Position of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_WM_THRHD field. + I2C_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0x1f + // Position of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5 + // Bit mask of TXFIFO_WM_THRHD field. + I2C_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x3e0 + // Position of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa + // Bit mask of NONFIFO_EN field. + I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400 + // Bit NONFIFO_EN. + I2C_FIFO_CONF_NONFIFO_EN = 0x400 + // Position of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Pos = 0xb + // Bit mask of FIFO_ADDR_CFG_EN field. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Msk = 0x800 + // Bit FIFO_ADDR_CFG_EN. + I2C_FIFO_CONF_FIFO_ADDR_CFG_EN = 0x800 + // Position of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc + // Bit mask of RX_FIFO_RST field. + I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000 + // Bit RX_FIFO_RST. + I2C_FIFO_CONF_RX_FIFO_RST = 0x1000 + // Position of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd + // Bit mask of TX_FIFO_RST field. + I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000 + // Bit TX_FIFO_RST. + I2C_FIFO_CONF_TX_FIFO_RST = 0x2000 + // Position of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Pos = 0xe + // Bit mask of FIFO_PRT_EN field. + I2C_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000 + // Bit FIFO_PRT_EN. + I2C_FIFO_CONF_FIFO_PRT_EN = 0x4000 + + // DATA: Rx FIFO read data. + // Position of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Pos = 0x0 + // Bit mask of FIFO_RDATA field. + I2C_DATA_FIFO_RDATA_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_RAW field. + I2C_INT_RAW_RXFIFO_WM_INT_RAW_Msk = 0x1 + // Bit RXFIFO_WM_INT_RAW. + I2C_INT_RAW_RXFIFO_WM_INT_RAW = 0x1 + // Position of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_RAW field. + I2C_INT_RAW_TXFIFO_WM_INT_RAW_Msk = 0x2 + // Bit TXFIFO_WM_INT_RAW. + I2C_INT_RAW_TXFIFO_WM_INT_RAW = 0x2 + // Position of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4 + // Bit RXFIFO_OVF_INT_RAW. + I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4 + // Position of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3 + // Bit mask of END_DETECT_INT_RAW field. + I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8 + // Bit END_DETECT_INT_RAW. + I2C_INT_RAW_END_DETECT_INT_RAW = 0x8 + // Position of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_RAW field. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_RAW. + I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW = 0x10 + // Position of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_RAW. + I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20 + // Position of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_RAW. + I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW = 0x40 + // Position of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_RAW. + I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80 + // Position of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8 + // Bit mask of TIME_OUT_INT_RAW field. + I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100 + // Bit TIME_OUT_INT_RAW. + I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100 + // Position of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9 + // Bit mask of TRANS_START_INT_RAW field. + I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200 + // Bit TRANS_START_INT_RAW. + I2C_INT_RAW_TRANS_START_INT_RAW = 0x200 + // Position of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Pos = 0xa + // Bit mask of NACK_INT_RAW field. + I2C_INT_RAW_NACK_INT_RAW_Msk = 0x400 + // Bit NACK_INT_RAW. + I2C_INT_RAW_NACK_INT_RAW = 0x400 + // Position of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_RAW field. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Msk = 0x800 + // Bit TXFIFO_OVF_INT_RAW. + I2C_INT_RAW_TXFIFO_OVF_INT_RAW = 0x800 + // Position of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_RAW field. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_RAW. + I2C_INT_RAW_RXFIFO_UDF_INT_RAW = 0x1000 + // Position of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_ST_TO_INT_RAW_Msk = 0x2000 + // Bit SCL_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_ST_TO_INT_RAW = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_RAW field. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_RAW. + I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW = 0x4000 + // Position of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Pos = 0xf + // Bit mask of DET_START_INT_RAW field. + I2C_INT_RAW_DET_START_INT_RAW_Msk = 0x8000 + // Bit DET_START_INT_RAW. + I2C_INT_RAW_DET_START_INT_RAW = 0x8000 + // Position of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_RAW field. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_RAW. + I2C_INT_RAW_SLAVE_STRETCH_INT_RAW = 0x10000 + // Position of GENERAL_CALL_INT_RAW field. + I2C_INT_RAW_GENERAL_CALL_INT_RAW_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_RAW field. + I2C_INT_RAW_GENERAL_CALL_INT_RAW_Msk = 0x20000 + // Bit GENERAL_CALL_INT_RAW. + I2C_INT_RAW_GENERAL_CALL_INT_RAW = 0x20000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_CLR field. + I2C_INT_CLR_RXFIFO_WM_INT_CLR_Msk = 0x1 + // Bit RXFIFO_WM_INT_CLR. + I2C_INT_CLR_RXFIFO_WM_INT_CLR = 0x1 + // Position of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_CLR field. + I2C_INT_CLR_TXFIFO_WM_INT_CLR_Msk = 0x2 + // Bit TXFIFO_WM_INT_CLR. + I2C_INT_CLR_TXFIFO_WM_INT_CLR = 0x2 + // Position of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4 + // Bit RXFIFO_OVF_INT_CLR. + I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4 + // Position of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3 + // Bit mask of END_DETECT_INT_CLR field. + I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8 + // Bit END_DETECT_INT_CLR. + I2C_INT_CLR_END_DETECT_INT_CLR = 0x8 + // Position of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_CLR field. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_CLR. + I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR = 0x10 + // Position of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_CLR. + I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20 + // Position of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_CLR. + I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR = 0x40 + // Position of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_CLR. + I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80 + // Position of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8 + // Bit mask of TIME_OUT_INT_CLR field. + I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100 + // Bit TIME_OUT_INT_CLR. + I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100 + // Position of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9 + // Bit mask of TRANS_START_INT_CLR field. + I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200 + // Bit TRANS_START_INT_CLR. + I2C_INT_CLR_TRANS_START_INT_CLR = 0x200 + // Position of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Pos = 0xa + // Bit mask of NACK_INT_CLR field. + I2C_INT_CLR_NACK_INT_CLR_Msk = 0x400 + // Bit NACK_INT_CLR. + I2C_INT_CLR_NACK_INT_CLR = 0x400 + // Position of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_CLR field. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Msk = 0x800 + // Bit TXFIFO_OVF_INT_CLR. + I2C_INT_CLR_TXFIFO_OVF_INT_CLR = 0x800 + // Position of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_CLR field. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_CLR. + I2C_INT_CLR_RXFIFO_UDF_INT_CLR = 0x1000 + // Position of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_ST_TO_INT_CLR_Msk = 0x2000 + // Bit SCL_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_ST_TO_INT_CLR = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_CLR field. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_CLR. + I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR = 0x4000 + // Position of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Pos = 0xf + // Bit mask of DET_START_INT_CLR field. + I2C_INT_CLR_DET_START_INT_CLR_Msk = 0x8000 + // Bit DET_START_INT_CLR. + I2C_INT_CLR_DET_START_INT_CLR = 0x8000 + // Position of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_CLR field. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_CLR. + I2C_INT_CLR_SLAVE_STRETCH_INT_CLR = 0x10000 + // Position of GENERAL_CALL_INT_CLR field. + I2C_INT_CLR_GENERAL_CALL_INT_CLR_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_CLR field. + I2C_INT_CLR_GENERAL_CALL_INT_CLR_Msk = 0x20000 + // Bit GENERAL_CALL_INT_CLR. + I2C_INT_CLR_GENERAL_CALL_INT_CLR = 0x20000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ENA field. + I2C_INT_ENA_RXFIFO_WM_INT_ENA_Msk = 0x1 + // Bit RXFIFO_WM_INT_ENA. + I2C_INT_ENA_RXFIFO_WM_INT_ENA = 0x1 + // Position of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ENA field. + I2C_INT_ENA_TXFIFO_WM_INT_ENA_Msk = 0x2 + // Bit TXFIFO_WM_INT_ENA. + I2C_INT_ENA_TXFIFO_WM_INT_ENA = 0x2 + // Position of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ENA. + I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4 + // Position of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3 + // Bit mask of END_DETECT_INT_ENA field. + I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8 + // Bit END_DETECT_INT_ENA. + I2C_INT_ENA_END_DETECT_INT_ENA = 0x8 + // Position of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ENA field. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ENA. + I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA = 0x10 + // Position of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ENA. + I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20 + // Position of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ENA. + I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA = 0x40 + // Position of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ENA. + I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80 + // Position of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ENA field. + I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100 + // Bit TIME_OUT_INT_ENA. + I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100 + // Position of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9 + // Bit mask of TRANS_START_INT_ENA field. + I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200 + // Bit TRANS_START_INT_ENA. + I2C_INT_ENA_TRANS_START_INT_ENA = 0x200 + // Position of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Pos = 0xa + // Bit mask of NACK_INT_ENA field. + I2C_INT_ENA_NACK_INT_ENA_Msk = 0x400 + // Bit NACK_INT_ENA. + I2C_INT_ENA_NACK_INT_ENA = 0x400 + // Position of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ENA field. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ENA. + I2C_INT_ENA_TXFIFO_OVF_INT_ENA = 0x800 + // Position of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ENA field. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ENA. + I2C_INT_ENA_RXFIFO_UDF_INT_ENA = 0x1000 + // Position of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_ST_TO_INT_ENA_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_ST_TO_INT_ENA = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ENA field. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ENA. + I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA = 0x4000 + // Position of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Pos = 0xf + // Bit mask of DET_START_INT_ENA field. + I2C_INT_ENA_DET_START_INT_ENA_Msk = 0x8000 + // Bit DET_START_INT_ENA. + I2C_INT_ENA_DET_START_INT_ENA = 0x8000 + // Position of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ENA field. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ENA. + I2C_INT_ENA_SLAVE_STRETCH_INT_ENA = 0x10000 + // Position of GENERAL_CALL_INT_ENA field. + I2C_INT_ENA_GENERAL_CALL_INT_ENA_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_ENA field. + I2C_INT_ENA_GENERAL_CALL_INT_ENA_Msk = 0x20000 + // Bit GENERAL_CALL_INT_ENA. + I2C_INT_ENA_GENERAL_CALL_INT_ENA = 0x20000 + + // INT_STATUS: Status of captured I2C communication events + // Position of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_WM_INT_ST field. + I2C_INT_STATUS_RXFIFO_WM_INT_ST_Msk = 0x1 + // Bit RXFIFO_WM_INT_ST. + I2C_INT_STATUS_RXFIFO_WM_INT_ST = 0x1 + // Position of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_WM_INT_ST field. + I2C_INT_STATUS_TXFIFO_WM_INT_ST_Msk = 0x2 + // Bit TXFIFO_WM_INT_ST. + I2C_INT_STATUS_TXFIFO_WM_INT_ST = 0x2 + // Position of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2 + // Bit mask of RXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4 + // Bit RXFIFO_OVF_INT_ST. + I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4 + // Position of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3 + // Bit mask of END_DETECT_INT_ST field. + I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8 + // Bit END_DETECT_INT_ST. + I2C_INT_STATUS_END_DETECT_INT_ST = 0x8 + // Position of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Pos = 0x4 + // Bit mask of BYTE_TRANS_DONE_INT_ST field. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Msk = 0x10 + // Bit BYTE_TRANS_DONE_INT_ST. + I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST = 0x10 + // Position of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5 + // Bit mask of ARBITRATION_LOST_INT_ST field. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20 + // Bit ARBITRATION_LOST_INT_ST. + I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20 + // Position of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Pos = 0x6 + // Bit mask of MST_TXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Msk = 0x40 + // Bit MST_TXFIFO_UDF_INT_ST. + I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST = 0x40 + // Position of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7 + // Bit mask of TRANS_COMPLETE_INT_ST field. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80 + // Bit TRANS_COMPLETE_INT_ST. + I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80 + // Position of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8 + // Bit mask of TIME_OUT_INT_ST field. + I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100 + // Bit TIME_OUT_INT_ST. + I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100 + // Position of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9 + // Bit mask of TRANS_START_INT_ST field. + I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200 + // Bit TRANS_START_INT_ST. + I2C_INT_STATUS_TRANS_START_INT_ST = 0x200 + // Position of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Pos = 0xa + // Bit mask of NACK_INT_ST field. + I2C_INT_STATUS_NACK_INT_ST_Msk = 0x400 + // Bit NACK_INT_ST. + I2C_INT_STATUS_NACK_INT_ST = 0x400 + // Position of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Pos = 0xb + // Bit mask of TXFIFO_OVF_INT_ST field. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Msk = 0x800 + // Bit TXFIFO_OVF_INT_ST. + I2C_INT_STATUS_TXFIFO_OVF_INT_ST = 0x800 + // Position of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Pos = 0xc + // Bit mask of RXFIFO_UDF_INT_ST field. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Msk = 0x1000 + // Bit RXFIFO_UDF_INT_ST. + I2C_INT_STATUS_RXFIFO_UDF_INT_ST = 0x1000 + // Position of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Pos = 0xd + // Bit mask of SCL_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_ST_TO_INT_ST_Msk = 0x2000 + // Bit SCL_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_ST_TO_INT_ST = 0x2000 + // Position of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe + // Bit mask of SCL_MAIN_ST_TO_INT_ST field. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000 + // Bit SCL_MAIN_ST_TO_INT_ST. + I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST = 0x4000 + // Position of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Pos = 0xf + // Bit mask of DET_START_INT_ST field. + I2C_INT_STATUS_DET_START_INT_ST_Msk = 0x8000 + // Bit DET_START_INT_ST. + I2C_INT_STATUS_DET_START_INT_ST = 0x8000 + // Position of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Pos = 0x10 + // Bit mask of SLAVE_STRETCH_INT_ST field. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Msk = 0x10000 + // Bit SLAVE_STRETCH_INT_ST. + I2C_INT_STATUS_SLAVE_STRETCH_INT_ST = 0x10000 + // Position of GENERAL_CALL_INT_ST field. + I2C_INT_STATUS_GENERAL_CALL_INT_ST_Pos = 0x11 + // Bit mask of GENERAL_CALL_INT_ST field. + I2C_INT_STATUS_GENERAL_CALL_INT_ST_Msk = 0x20000 + // Bit GENERAL_CALL_INT_ST. + I2C_INT_STATUS_GENERAL_CALL_INT_ST = 0x20000 + + // SDA_HOLD: Configures the hold time after a negative SCL edge. + // Position of TIME field. + I2C_SDA_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_HOLD_TIME_Msk = 0x1ff + + // SDA_SAMPLE: Configures the sample time after a positive SCL edge. + // Position of TIME field. + I2C_SDA_SAMPLE_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SDA_SAMPLE_TIME_Msk = 0x1ff + + // SCL_HIGH_PERIOD: Configures the high level width of SCL + // Position of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of SCL_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x1ff + // Position of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Pos = 0x9 + // Bit mask of SCL_WAIT_HIGH_PERIOD field. + I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Msk = 0xfe00 + + // SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition + // Position of TIME field. + I2C_SCL_START_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_START_HOLD_TIME_Msk = 0x1ff + + // SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA + // Position of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_RSTART_SETUP_TIME_Msk = 0x1ff + + // SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_HOLD_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_HOLD_TIME_Msk = 0x1ff + + // SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition + // Position of TIME field. + I2C_SCL_STOP_SETUP_TIME_Pos = 0x0 + // Bit mask of TIME field. + I2C_SCL_STOP_SETUP_TIME_Msk = 0x1ff + + // FILTER_CFG: SCL and SDA filter configuration register + // Position of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0 + // Bit mask of SCL_FILTER_THRES field. + I2C_FILTER_CFG_SCL_FILTER_THRES_Msk = 0xf + // Position of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x4 + // Bit mask of SDA_FILTER_THRES field. + I2C_FILTER_CFG_SDA_FILTER_THRES_Msk = 0xf0 + // Position of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Pos = 0x8 + // Bit mask of SCL_FILTER_EN field. + I2C_FILTER_CFG_SCL_FILTER_EN_Msk = 0x100 + // Bit SCL_FILTER_EN. + I2C_FILTER_CFG_SCL_FILTER_EN = 0x100 + // Position of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Pos = 0x9 + // Bit mask of SDA_FILTER_EN field. + I2C_FILTER_CFG_SDA_FILTER_EN_Msk = 0x200 + // Bit SDA_FILTER_EN. + I2C_FILTER_CFG_SDA_FILTER_EN = 0x200 + + // CLK_CONF: I2C CLK configuration register + // Position of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Pos = 0x0 + // Bit mask of SCLK_DIV_NUM field. + I2C_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff + // Position of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Pos = 0x8 + // Bit mask of SCLK_DIV_A field. + I2C_CLK_CONF_SCLK_DIV_A_Msk = 0x3f00 + // Position of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Pos = 0xe + // Bit mask of SCLK_DIV_B field. + I2C_CLK_CONF_SCLK_DIV_B_Msk = 0xfc000 + // Position of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + I2C_CLK_CONF_SCLK_SEL_Msk = 0x100000 + // Bit SCLK_SEL. + I2C_CLK_CONF_SCLK_SEL = 0x100000 + // Position of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Pos = 0x15 + // Bit mask of SCLK_ACTIVE field. + I2C_CLK_CONF_SCLK_ACTIVE_Msk = 0x200000 + // Bit SCLK_ACTIVE. + I2C_CLK_CONF_SCLK_ACTIVE = 0x200000 + + // COMD0: I2C command register %s + // Position of COMMAND field. + I2C_COMD_COMMAND_Pos = 0x0 + // Bit mask of COMMAND field. + I2C_COMD_COMMAND_Msk = 0x3fff + // Position of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Pos = 0x1f + // Bit mask of COMMAND_DONE field. + I2C_COMD_COMMAND_DONE_Msk = 0x80000000 + // Bit COMMAND_DONE. + I2C_COMD_COMMAND_DONE = 0x80000000 + + // SCL_ST_TIME_OUT: SCL status time out register + // Position of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_ST_TO_I2C field. + I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Msk = 0x1f + + // SCL_MAIN_ST_TIME_OUT: SCL main status time out register + // Position of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Pos = 0x0 + // Bit mask of SCL_MAIN_ST_TO_I2C field. + I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Msk = 0x1f + + // SCL_SP_CONF: Power configuration register + // Position of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Pos = 0x0 + // Bit mask of SCL_RST_SLV_EN field. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Msk = 0x1 + // Bit SCL_RST_SLV_EN. + I2C_SCL_SP_CONF_SCL_RST_SLV_EN = 0x1 + // Position of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Pos = 0x1 + // Bit mask of SCL_RST_SLV_NUM field. + I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Msk = 0x3e + // Position of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Pos = 0x6 + // Bit mask of SCL_PD_EN field. + I2C_SCL_SP_CONF_SCL_PD_EN_Msk = 0x40 + // Bit SCL_PD_EN. + I2C_SCL_SP_CONF_SCL_PD_EN = 0x40 + // Position of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Pos = 0x7 + // Bit mask of SDA_PD_EN field. + I2C_SCL_SP_CONF_SDA_PD_EN_Msk = 0x80 + // Bit SDA_PD_EN. + I2C_SCL_SP_CONF_SDA_PD_EN = 0x80 + + // SCL_STRETCH_CONF: Set SCL stretch of I2C slave + // Position of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Pos = 0x0 + // Bit mask of STRETCH_PROTECT_NUM field. + I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Msk = 0x3ff + // Position of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Pos = 0xa + // Bit mask of SLAVE_SCL_STRETCH_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Msk = 0x400 + // Bit SLAVE_SCL_STRETCH_EN. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN = 0x400 + // Position of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Pos = 0xb + // Bit mask of SLAVE_SCL_STRETCH_CLR field. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Msk = 0x800 + // Bit SLAVE_SCL_STRETCH_CLR. + I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR = 0x800 + // Position of SLAVE_BYTE_ACK_CTL_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Pos = 0xc + // Bit mask of SLAVE_BYTE_ACK_CTL_EN field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Msk = 0x1000 + // Bit SLAVE_BYTE_ACK_CTL_EN. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN = 0x1000 + // Position of SLAVE_BYTE_ACK_LVL field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Pos = 0xd + // Bit mask of SLAVE_BYTE_ACK_LVL field. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Msk = 0x2000 + // Bit SLAVE_BYTE_ACK_LVL. + I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL = 0x2000 + + // DATE: Version register + // Position of DATE field. + I2C_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2C_DATE_DATE_Msk = 0xffffffff + + // TXFIFO_START_ADDR: I2C TXFIFO base address register + // Position of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of TXFIFO_START_ADDR field. + I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Msk = 0xffffffff + + // RXFIFO_START_ADDR: I2C RXFIFO base address register + // Position of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Pos = 0x0 + // Bit mask of RXFIFO_START_ADDR field. + I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Msk = 0xffffffff +) + +// Constants for I2S0: I2S (Inter-IC Sound) Controller 0 +const ( + // INT_RAW: I2S interrupt raw register, valid in level. + // Position of RX_DONE_INT_RAW field. + I2S_INT_RAW_RX_DONE_INT_RAW_Pos = 0x0 + // Bit mask of RX_DONE_INT_RAW field. + I2S_INT_RAW_RX_DONE_INT_RAW_Msk = 0x1 + // Bit RX_DONE_INT_RAW. + I2S_INT_RAW_RX_DONE_INT_RAW = 0x1 + // Position of TX_DONE_INT_RAW field. + I2S_INT_RAW_TX_DONE_INT_RAW_Pos = 0x1 + // Bit mask of TX_DONE_INT_RAW field. + I2S_INT_RAW_TX_DONE_INT_RAW_Msk = 0x2 + // Bit TX_DONE_INT_RAW. + I2S_INT_RAW_TX_DONE_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + I2S_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + I2S_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + I2S_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + I2S_INT_RAW_TX_HUNG_INT_RAW = 0x8 + + // INT_ST: I2S interrupt status register. + // Position of RX_DONE_INT_ST field. + I2S_INT_ST_RX_DONE_INT_ST_Pos = 0x0 + // Bit mask of RX_DONE_INT_ST field. + I2S_INT_ST_RX_DONE_INT_ST_Msk = 0x1 + // Bit RX_DONE_INT_ST. + I2S_INT_ST_RX_DONE_INT_ST = 0x1 + // Position of TX_DONE_INT_ST field. + I2S_INT_ST_TX_DONE_INT_ST_Pos = 0x1 + // Bit mask of TX_DONE_INT_ST field. + I2S_INT_ST_TX_DONE_INT_ST_Msk = 0x2 + // Bit TX_DONE_INT_ST. + I2S_INT_ST_TX_DONE_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + I2S_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + I2S_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + I2S_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + I2S_INT_ST_TX_HUNG_INT_ST = 0x8 + + // INT_ENA: I2S interrupt enable register. + // Position of RX_DONE_INT_ENA field. + I2S_INT_ENA_RX_DONE_INT_ENA_Pos = 0x0 + // Bit mask of RX_DONE_INT_ENA field. + I2S_INT_ENA_RX_DONE_INT_ENA_Msk = 0x1 + // Bit RX_DONE_INT_ENA. + I2S_INT_ENA_RX_DONE_INT_ENA = 0x1 + // Position of TX_DONE_INT_ENA field. + I2S_INT_ENA_TX_DONE_INT_ENA_Pos = 0x1 + // Bit mask of TX_DONE_INT_ENA field. + I2S_INT_ENA_TX_DONE_INT_ENA_Msk = 0x2 + // Bit TX_DONE_INT_ENA. + I2S_INT_ENA_TX_DONE_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + I2S_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + I2S_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + I2S_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + I2S_INT_ENA_TX_HUNG_INT_ENA = 0x8 + + // INT_CLR: I2S interrupt clear register. + // Position of RX_DONE_INT_CLR field. + I2S_INT_CLR_RX_DONE_INT_CLR_Pos = 0x0 + // Bit mask of RX_DONE_INT_CLR field. + I2S_INT_CLR_RX_DONE_INT_CLR_Msk = 0x1 + // Bit RX_DONE_INT_CLR. + I2S_INT_CLR_RX_DONE_INT_CLR = 0x1 + // Position of TX_DONE_INT_CLR field. + I2S_INT_CLR_TX_DONE_INT_CLR_Pos = 0x1 + // Bit mask of TX_DONE_INT_CLR field. + I2S_INT_CLR_TX_DONE_INT_CLR_Msk = 0x2 + // Bit TX_DONE_INT_CLR. + I2S_INT_CLR_TX_DONE_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + I2S_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + I2S_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + I2S_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + I2S_INT_CLR_TX_HUNG_INT_CLR = 0x8 + + // RX_CONF: I2S RX configure register + // Position of RX_RESET field. + I2S_RX_CONF_RX_RESET_Pos = 0x0 + // Bit mask of RX_RESET field. + I2S_RX_CONF_RX_RESET_Msk = 0x1 + // Bit RX_RESET. + I2S_RX_CONF_RX_RESET = 0x1 + // Position of RX_FIFO_RESET field. + I2S_RX_CONF_RX_FIFO_RESET_Pos = 0x1 + // Bit mask of RX_FIFO_RESET field. + I2S_RX_CONF_RX_FIFO_RESET_Msk = 0x2 + // Bit RX_FIFO_RESET. + I2S_RX_CONF_RX_FIFO_RESET = 0x2 + // Position of RX_START field. + I2S_RX_CONF_RX_START_Pos = 0x2 + // Bit mask of RX_START field. + I2S_RX_CONF_RX_START_Msk = 0x4 + // Bit RX_START. + I2S_RX_CONF_RX_START = 0x4 + // Position of RX_SLAVE_MOD field. + I2S_RX_CONF_RX_SLAVE_MOD_Pos = 0x3 + // Bit mask of RX_SLAVE_MOD field. + I2S_RX_CONF_RX_SLAVE_MOD_Msk = 0x8 + // Bit RX_SLAVE_MOD. + I2S_RX_CONF_RX_SLAVE_MOD = 0x8 + // Position of RX_MONO field. + I2S_RX_CONF_RX_MONO_Pos = 0x5 + // Bit mask of RX_MONO field. + I2S_RX_CONF_RX_MONO_Msk = 0x20 + // Bit RX_MONO. + I2S_RX_CONF_RX_MONO = 0x20 + // Position of RX_BIG_ENDIAN field. + I2S_RX_CONF_RX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of RX_BIG_ENDIAN field. + I2S_RX_CONF_RX_BIG_ENDIAN_Msk = 0x80 + // Bit RX_BIG_ENDIAN. + I2S_RX_CONF_RX_BIG_ENDIAN = 0x80 + // Position of RX_UPDATE field. + I2S_RX_CONF_RX_UPDATE_Pos = 0x8 + // Bit mask of RX_UPDATE field. + I2S_RX_CONF_RX_UPDATE_Msk = 0x100 + // Bit RX_UPDATE. + I2S_RX_CONF_RX_UPDATE = 0x100 + // Position of RX_MONO_FST_VLD field. + I2S_RX_CONF_RX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of RX_MONO_FST_VLD field. + I2S_RX_CONF_RX_MONO_FST_VLD_Msk = 0x200 + // Bit RX_MONO_FST_VLD. + I2S_RX_CONF_RX_MONO_FST_VLD = 0x200 + // Position of RX_PCM_CONF field. + I2S_RX_CONF_RX_PCM_CONF_Pos = 0xa + // Bit mask of RX_PCM_CONF field. + I2S_RX_CONF_RX_PCM_CONF_Msk = 0xc00 + // Position of RX_PCM_BYPASS field. + I2S_RX_CONF_RX_PCM_BYPASS_Pos = 0xc + // Bit mask of RX_PCM_BYPASS field. + I2S_RX_CONF_RX_PCM_BYPASS_Msk = 0x1000 + // Bit RX_PCM_BYPASS. + I2S_RX_CONF_RX_PCM_BYPASS = 0x1000 + // Position of RX_STOP_MODE field. + I2S_RX_CONF_RX_STOP_MODE_Pos = 0xd + // Bit mask of RX_STOP_MODE field. + I2S_RX_CONF_RX_STOP_MODE_Msk = 0x6000 + // Position of RX_LEFT_ALIGN field. + I2S_RX_CONF_RX_LEFT_ALIGN_Pos = 0xf + // Bit mask of RX_LEFT_ALIGN field. + I2S_RX_CONF_RX_LEFT_ALIGN_Msk = 0x8000 + // Bit RX_LEFT_ALIGN. + I2S_RX_CONF_RX_LEFT_ALIGN = 0x8000 + // Position of RX_24_FILL_EN field. + I2S_RX_CONF_RX_24_FILL_EN_Pos = 0x10 + // Bit mask of RX_24_FILL_EN field. + I2S_RX_CONF_RX_24_FILL_EN_Msk = 0x10000 + // Bit RX_24_FILL_EN. + I2S_RX_CONF_RX_24_FILL_EN = 0x10000 + // Position of RX_WS_IDLE_POL field. + I2S_RX_CONF_RX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of RX_WS_IDLE_POL field. + I2S_RX_CONF_RX_WS_IDLE_POL_Msk = 0x20000 + // Bit RX_WS_IDLE_POL. + I2S_RX_CONF_RX_WS_IDLE_POL = 0x20000 + // Position of RX_BIT_ORDER field. + I2S_RX_CONF_RX_BIT_ORDER_Pos = 0x12 + // Bit mask of RX_BIT_ORDER field. + I2S_RX_CONF_RX_BIT_ORDER_Msk = 0x40000 + // Bit RX_BIT_ORDER. + I2S_RX_CONF_RX_BIT_ORDER = 0x40000 + // Position of RX_TDM_EN field. + I2S_RX_CONF_RX_TDM_EN_Pos = 0x13 + // Bit mask of RX_TDM_EN field. + I2S_RX_CONF_RX_TDM_EN_Msk = 0x80000 + // Bit RX_TDM_EN. + I2S_RX_CONF_RX_TDM_EN = 0x80000 + // Position of RX_PDM_EN field. + I2S_RX_CONF_RX_PDM_EN_Pos = 0x14 + // Bit mask of RX_PDM_EN field. + I2S_RX_CONF_RX_PDM_EN_Msk = 0x100000 + // Bit RX_PDM_EN. + I2S_RX_CONF_RX_PDM_EN = 0x100000 + // Position of RX_PDM2PCM_EN field. + I2S_RX_CONF_RX_PDM2PCM_EN_Pos = 0x15 + // Bit mask of RX_PDM2PCM_EN field. + I2S_RX_CONF_RX_PDM2PCM_EN_Msk = 0x200000 + // Bit RX_PDM2PCM_EN. + I2S_RX_CONF_RX_PDM2PCM_EN = 0x200000 + // Position of RX_PDM_SINC_DSR_16_EN field. + I2S_RX_CONF_RX_PDM_SINC_DSR_16_EN_Pos = 0x16 + // Bit mask of RX_PDM_SINC_DSR_16_EN field. + I2S_RX_CONF_RX_PDM_SINC_DSR_16_EN_Msk = 0x400000 + // Bit RX_PDM_SINC_DSR_16_EN. + I2S_RX_CONF_RX_PDM_SINC_DSR_16_EN = 0x400000 + + // TX_CONF: I2S TX configure register + // Position of TX_RESET field. + I2S_TX_CONF_TX_RESET_Pos = 0x0 + // Bit mask of TX_RESET field. + I2S_TX_CONF_TX_RESET_Msk = 0x1 + // Bit TX_RESET. + I2S_TX_CONF_TX_RESET = 0x1 + // Position of TX_FIFO_RESET field. + I2S_TX_CONF_TX_FIFO_RESET_Pos = 0x1 + // Bit mask of TX_FIFO_RESET field. + I2S_TX_CONF_TX_FIFO_RESET_Msk = 0x2 + // Bit TX_FIFO_RESET. + I2S_TX_CONF_TX_FIFO_RESET = 0x2 + // Position of TX_START field. + I2S_TX_CONF_TX_START_Pos = 0x2 + // Bit mask of TX_START field. + I2S_TX_CONF_TX_START_Msk = 0x4 + // Bit TX_START. + I2S_TX_CONF_TX_START = 0x4 + // Position of TX_SLAVE_MOD field. + I2S_TX_CONF_TX_SLAVE_MOD_Pos = 0x3 + // Bit mask of TX_SLAVE_MOD field. + I2S_TX_CONF_TX_SLAVE_MOD_Msk = 0x8 + // Bit TX_SLAVE_MOD. + I2S_TX_CONF_TX_SLAVE_MOD = 0x8 + // Position of TX_MONO field. + I2S_TX_CONF_TX_MONO_Pos = 0x5 + // Bit mask of TX_MONO field. + I2S_TX_CONF_TX_MONO_Msk = 0x20 + // Bit TX_MONO. + I2S_TX_CONF_TX_MONO = 0x20 + // Position of TX_CHAN_EQUAL field. + I2S_TX_CONF_TX_CHAN_EQUAL_Pos = 0x6 + // Bit mask of TX_CHAN_EQUAL field. + I2S_TX_CONF_TX_CHAN_EQUAL_Msk = 0x40 + // Bit TX_CHAN_EQUAL. + I2S_TX_CONF_TX_CHAN_EQUAL = 0x40 + // Position of TX_BIG_ENDIAN field. + I2S_TX_CONF_TX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of TX_BIG_ENDIAN field. + I2S_TX_CONF_TX_BIG_ENDIAN_Msk = 0x80 + // Bit TX_BIG_ENDIAN. + I2S_TX_CONF_TX_BIG_ENDIAN = 0x80 + // Position of TX_UPDATE field. + I2S_TX_CONF_TX_UPDATE_Pos = 0x8 + // Bit mask of TX_UPDATE field. + I2S_TX_CONF_TX_UPDATE_Msk = 0x100 + // Bit TX_UPDATE. + I2S_TX_CONF_TX_UPDATE = 0x100 + // Position of TX_MONO_FST_VLD field. + I2S_TX_CONF_TX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of TX_MONO_FST_VLD field. + I2S_TX_CONF_TX_MONO_FST_VLD_Msk = 0x200 + // Bit TX_MONO_FST_VLD. + I2S_TX_CONF_TX_MONO_FST_VLD = 0x200 + // Position of TX_PCM_CONF field. + I2S_TX_CONF_TX_PCM_CONF_Pos = 0xa + // Bit mask of TX_PCM_CONF field. + I2S_TX_CONF_TX_PCM_CONF_Msk = 0xc00 + // Position of TX_PCM_BYPASS field. + I2S_TX_CONF_TX_PCM_BYPASS_Pos = 0xc + // Bit mask of TX_PCM_BYPASS field. + I2S_TX_CONF_TX_PCM_BYPASS_Msk = 0x1000 + // Bit TX_PCM_BYPASS. + I2S_TX_CONF_TX_PCM_BYPASS = 0x1000 + // Position of TX_STOP_EN field. + I2S_TX_CONF_TX_STOP_EN_Pos = 0xd + // Bit mask of TX_STOP_EN field. + I2S_TX_CONF_TX_STOP_EN_Msk = 0x2000 + // Bit TX_STOP_EN. + I2S_TX_CONF_TX_STOP_EN = 0x2000 + // Position of TX_LEFT_ALIGN field. + I2S_TX_CONF_TX_LEFT_ALIGN_Pos = 0xf + // Bit mask of TX_LEFT_ALIGN field. + I2S_TX_CONF_TX_LEFT_ALIGN_Msk = 0x8000 + // Bit TX_LEFT_ALIGN. + I2S_TX_CONF_TX_LEFT_ALIGN = 0x8000 + // Position of TX_24_FILL_EN field. + I2S_TX_CONF_TX_24_FILL_EN_Pos = 0x10 + // Bit mask of TX_24_FILL_EN field. + I2S_TX_CONF_TX_24_FILL_EN_Msk = 0x10000 + // Bit TX_24_FILL_EN. + I2S_TX_CONF_TX_24_FILL_EN = 0x10000 + // Position of TX_WS_IDLE_POL field. + I2S_TX_CONF_TX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of TX_WS_IDLE_POL field. + I2S_TX_CONF_TX_WS_IDLE_POL_Msk = 0x20000 + // Bit TX_WS_IDLE_POL. + I2S_TX_CONF_TX_WS_IDLE_POL = 0x20000 + // Position of TX_BIT_ORDER field. + I2S_TX_CONF_TX_BIT_ORDER_Pos = 0x12 + // Bit mask of TX_BIT_ORDER field. + I2S_TX_CONF_TX_BIT_ORDER_Msk = 0x40000 + // Bit TX_BIT_ORDER. + I2S_TX_CONF_TX_BIT_ORDER = 0x40000 + // Position of TX_TDM_EN field. + I2S_TX_CONF_TX_TDM_EN_Pos = 0x13 + // Bit mask of TX_TDM_EN field. + I2S_TX_CONF_TX_TDM_EN_Msk = 0x80000 + // Bit TX_TDM_EN. + I2S_TX_CONF_TX_TDM_EN = 0x80000 + // Position of TX_PDM_EN field. + I2S_TX_CONF_TX_PDM_EN_Pos = 0x14 + // Bit mask of TX_PDM_EN field. + I2S_TX_CONF_TX_PDM_EN_Msk = 0x100000 + // Bit TX_PDM_EN. + I2S_TX_CONF_TX_PDM_EN = 0x100000 + // Position of TX_CHAN_MOD field. + I2S_TX_CONF_TX_CHAN_MOD_Pos = 0x18 + // Bit mask of TX_CHAN_MOD field. + I2S_TX_CONF_TX_CHAN_MOD_Msk = 0x7000000 + // Position of SIG_LOOPBACK field. + I2S_TX_CONF_SIG_LOOPBACK_Pos = 0x1b + // Bit mask of SIG_LOOPBACK field. + I2S_TX_CONF_SIG_LOOPBACK_Msk = 0x8000000 + // Bit SIG_LOOPBACK. + I2S_TX_CONF_SIG_LOOPBACK = 0x8000000 + + // RX_CONF1: I2S RX configure register 1 + // Position of RX_TDM_WS_WIDTH field. + I2S_RX_CONF1_RX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of RX_TDM_WS_WIDTH field. + I2S_RX_CONF1_RX_TDM_WS_WIDTH_Msk = 0x7f + // Position of RX_BCK_DIV_NUM field. + I2S_RX_CONF1_RX_BCK_DIV_NUM_Pos = 0x7 + // Bit mask of RX_BCK_DIV_NUM field. + I2S_RX_CONF1_RX_BCK_DIV_NUM_Msk = 0x1f80 + // Position of RX_BITS_MOD field. + I2S_RX_CONF1_RX_BITS_MOD_Pos = 0xd + // Bit mask of RX_BITS_MOD field. + I2S_RX_CONF1_RX_BITS_MOD_Msk = 0x3e000 + // Position of RX_HALF_SAMPLE_BITS field. + I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Pos = 0x12 + // Bit mask of RX_HALF_SAMPLE_BITS field. + I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Msk = 0xfc0000 + // Position of RX_TDM_CHAN_BITS field. + I2S_RX_CONF1_RX_TDM_CHAN_BITS_Pos = 0x18 + // Bit mask of RX_TDM_CHAN_BITS field. + I2S_RX_CONF1_RX_TDM_CHAN_BITS_Msk = 0x1f000000 + // Position of RX_MSB_SHIFT field. + I2S_RX_CONF1_RX_MSB_SHIFT_Pos = 0x1d + // Bit mask of RX_MSB_SHIFT field. + I2S_RX_CONF1_RX_MSB_SHIFT_Msk = 0x20000000 + // Bit RX_MSB_SHIFT. + I2S_RX_CONF1_RX_MSB_SHIFT = 0x20000000 + + // TX_CONF1: I2S TX configure register 1 + // Position of TX_TDM_WS_WIDTH field. + I2S_TX_CONF1_TX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of TX_TDM_WS_WIDTH field. + I2S_TX_CONF1_TX_TDM_WS_WIDTH_Msk = 0x7f + // Position of TX_BCK_DIV_NUM field. + I2S_TX_CONF1_TX_BCK_DIV_NUM_Pos = 0x7 + // Bit mask of TX_BCK_DIV_NUM field. + I2S_TX_CONF1_TX_BCK_DIV_NUM_Msk = 0x1f80 + // Position of TX_BITS_MOD field. + I2S_TX_CONF1_TX_BITS_MOD_Pos = 0xd + // Bit mask of TX_BITS_MOD field. + I2S_TX_CONF1_TX_BITS_MOD_Msk = 0x3e000 + // Position of TX_HALF_SAMPLE_BITS field. + I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Pos = 0x12 + // Bit mask of TX_HALF_SAMPLE_BITS field. + I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Msk = 0xfc0000 + // Position of TX_TDM_CHAN_BITS field. + I2S_TX_CONF1_TX_TDM_CHAN_BITS_Pos = 0x18 + // Bit mask of TX_TDM_CHAN_BITS field. + I2S_TX_CONF1_TX_TDM_CHAN_BITS_Msk = 0x1f000000 + // Position of TX_MSB_SHIFT field. + I2S_TX_CONF1_TX_MSB_SHIFT_Pos = 0x1d + // Bit mask of TX_MSB_SHIFT field. + I2S_TX_CONF1_TX_MSB_SHIFT_Msk = 0x20000000 + // Bit TX_MSB_SHIFT. + I2S_TX_CONF1_TX_MSB_SHIFT = 0x20000000 + // Position of TX_BCK_NO_DLY field. + I2S_TX_CONF1_TX_BCK_NO_DLY_Pos = 0x1e + // Bit mask of TX_BCK_NO_DLY field. + I2S_TX_CONF1_TX_BCK_NO_DLY_Msk = 0x40000000 + // Bit TX_BCK_NO_DLY. + I2S_TX_CONF1_TX_BCK_NO_DLY = 0x40000000 + + // RX_CLKM_CONF: I2S RX clock configure register + // Position of RX_CLKM_DIV_NUM field. + I2S_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_NUM field. + I2S_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Msk = 0xff + // Position of RX_CLK_ACTIVE field. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of RX_CLK_ACTIVE field. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE_Msk = 0x4000000 + // Bit RX_CLK_ACTIVE. + I2S_RX_CLKM_CONF_RX_CLK_ACTIVE = 0x4000000 + // Position of RX_CLK_SEL field. + I2S_RX_CLKM_CONF_RX_CLK_SEL_Pos = 0x1b + // Bit mask of RX_CLK_SEL field. + I2S_RX_CLKM_CONF_RX_CLK_SEL_Msk = 0x18000000 + // Position of MCLK_SEL field. + I2S_RX_CLKM_CONF_MCLK_SEL_Pos = 0x1d + // Bit mask of MCLK_SEL field. + I2S_RX_CLKM_CONF_MCLK_SEL_Msk = 0x20000000 + // Bit MCLK_SEL. + I2S_RX_CLKM_CONF_MCLK_SEL = 0x20000000 + + // TX_CLKM_CONF: I2S TX clock configure register + // Position of TX_CLKM_DIV_NUM field. + I2S_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_NUM field. + I2S_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Msk = 0xff + // Position of TX_CLK_ACTIVE field. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of TX_CLK_ACTIVE field. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE_Msk = 0x4000000 + // Bit TX_CLK_ACTIVE. + I2S_TX_CLKM_CONF_TX_CLK_ACTIVE = 0x4000000 + // Position of TX_CLK_SEL field. + I2S_TX_CLKM_CONF_TX_CLK_SEL_Pos = 0x1b + // Bit mask of TX_CLK_SEL field. + I2S_TX_CLKM_CONF_TX_CLK_SEL_Msk = 0x18000000 + // Position of CLK_EN field. + I2S_TX_CLKM_CONF_CLK_EN_Pos = 0x1d + // Bit mask of CLK_EN field. + I2S_TX_CLKM_CONF_CLK_EN_Msk = 0x20000000 + // Bit CLK_EN. + I2S_TX_CLKM_CONF_CLK_EN = 0x20000000 + + // RX_CLKM_DIV_CONF: I2S RX module clock divider configure register + // Position of RX_CLKM_DIV_Z field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_Z field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Msk = 0x1ff + // Position of RX_CLKM_DIV_Y field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of RX_CLKM_DIV_Y field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of RX_CLKM_DIV_X field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of RX_CLKM_DIV_X field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of RX_CLKM_DIV_YN1 field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of RX_CLKM_DIV_YN1 field. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit RX_CLKM_DIV_YN1. + I2S_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1 = 0x8000000 + + // TX_CLKM_DIV_CONF: I2S TX module clock divider configure register + // Position of TX_CLKM_DIV_Z field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_Z field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Msk = 0x1ff + // Position of TX_CLKM_DIV_Y field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of TX_CLKM_DIV_Y field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of TX_CLKM_DIV_X field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of TX_CLKM_DIV_X field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of TX_CLKM_DIV_YN1 field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of TX_CLKM_DIV_YN1 field. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit TX_CLKM_DIV_YN1. + I2S_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1 = 0x8000000 + + // TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register + // Position of TX_PDM_HP_BYPASS field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Pos = 0x0 + // Bit mask of TX_PDM_HP_BYPASS field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Msk = 0x1 + // Bit TX_PDM_HP_BYPASS. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS = 0x1 + // Position of TX_PDM_SINC_OSR2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Pos = 0x1 + // Bit mask of TX_PDM_SINC_OSR2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Msk = 0x1e + // Position of TX_PDM_PRESCALE field. + I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Pos = 0x5 + // Bit mask of TX_PDM_PRESCALE field. + I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Msk = 0x1fe0 + // Position of TX_PDM_HP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Pos = 0xd + // Bit mask of TX_PDM_HP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Msk = 0x6000 + // Position of TX_PDM_LP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Pos = 0xf + // Bit mask of TX_PDM_LP_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Msk = 0x18000 + // Position of TX_PDM_SINC_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Pos = 0x11 + // Bit mask of TX_PDM_SINC_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Msk = 0x60000 + // Position of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Pos = 0x13 + // Bit mask of TX_PDM_SIGMADELTA_IN_SHIFT field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Msk = 0x180000 + // Position of TX_PDM_SIGMADELTA_DITHER2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Pos = 0x15 + // Bit mask of TX_PDM_SIGMADELTA_DITHER2 field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Msk = 0x200000 + // Bit TX_PDM_SIGMADELTA_DITHER2. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2 = 0x200000 + // Position of TX_PDM_SIGMADELTA_DITHER field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Pos = 0x16 + // Bit mask of TX_PDM_SIGMADELTA_DITHER field. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Msk = 0x400000 + // Bit TX_PDM_SIGMADELTA_DITHER. + I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER = 0x400000 + // Position of TX_PDM_DAC_2OUT_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Pos = 0x17 + // Bit mask of TX_PDM_DAC_2OUT_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Msk = 0x800000 + // Bit TX_PDM_DAC_2OUT_EN. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN = 0x800000 + // Position of TX_PDM_DAC_MODE_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Pos = 0x18 + // Bit mask of TX_PDM_DAC_MODE_EN field. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Msk = 0x1000000 + // Bit TX_PDM_DAC_MODE_EN. + I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN = 0x1000000 + // Position of PCM2PDM_CONV_EN field. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Pos = 0x19 + // Bit mask of PCM2PDM_CONV_EN field. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Msk = 0x2000000 + // Bit PCM2PDM_CONV_EN. + I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN = 0x2000000 + + // TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register + // Position of TX_PDM_FP field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Pos = 0x0 + // Bit mask of TX_PDM_FP field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Msk = 0x3ff + // Position of TX_PDM_FS field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Pos = 0xa + // Bit mask of TX_PDM_FS field. + I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Msk = 0xffc00 + // Position of TX_IIR_HP_MULT12_5 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Pos = 0x14 + // Bit mask of TX_IIR_HP_MULT12_5 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Msk = 0x700000 + // Position of TX_IIR_HP_MULT12_0 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Pos = 0x17 + // Bit mask of TX_IIR_HP_MULT12_0 field. + I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Msk = 0x3800000 + + // RX_TDM_CTRL: I2S TX TDM mode control register + // Position of RX_TDM_PDM_CHAN0_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Pos = 0x0 + // Bit mask of RX_TDM_PDM_CHAN0_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Msk = 0x1 + // Bit RX_TDM_PDM_CHAN0_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN = 0x1 + // Position of RX_TDM_PDM_CHAN1_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Pos = 0x1 + // Bit mask of RX_TDM_PDM_CHAN1_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Msk = 0x2 + // Bit RX_TDM_PDM_CHAN1_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN = 0x2 + // Position of RX_TDM_PDM_CHAN2_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Pos = 0x2 + // Bit mask of RX_TDM_PDM_CHAN2_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Msk = 0x4 + // Bit RX_TDM_PDM_CHAN2_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN = 0x4 + // Position of RX_TDM_PDM_CHAN3_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Pos = 0x3 + // Bit mask of RX_TDM_PDM_CHAN3_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Msk = 0x8 + // Bit RX_TDM_PDM_CHAN3_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN = 0x8 + // Position of RX_TDM_PDM_CHAN4_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Pos = 0x4 + // Bit mask of RX_TDM_PDM_CHAN4_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Msk = 0x10 + // Bit RX_TDM_PDM_CHAN4_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN = 0x10 + // Position of RX_TDM_PDM_CHAN5_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Pos = 0x5 + // Bit mask of RX_TDM_PDM_CHAN5_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Msk = 0x20 + // Bit RX_TDM_PDM_CHAN5_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN = 0x20 + // Position of RX_TDM_PDM_CHAN6_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Pos = 0x6 + // Bit mask of RX_TDM_PDM_CHAN6_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Msk = 0x40 + // Bit RX_TDM_PDM_CHAN6_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN = 0x40 + // Position of RX_TDM_PDM_CHAN7_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Pos = 0x7 + // Bit mask of RX_TDM_PDM_CHAN7_EN field. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Msk = 0x80 + // Bit RX_TDM_PDM_CHAN7_EN. + I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN = 0x80 + // Position of RX_TDM_CHAN8_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of RX_TDM_CHAN8_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Msk = 0x100 + // Bit RX_TDM_CHAN8_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN = 0x100 + // Position of RX_TDM_CHAN9_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of RX_TDM_CHAN9_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Msk = 0x200 + // Bit RX_TDM_CHAN9_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN = 0x200 + // Position of RX_TDM_CHAN10_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of RX_TDM_CHAN10_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Msk = 0x400 + // Bit RX_TDM_CHAN10_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN = 0x400 + // Position of RX_TDM_CHAN11_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of RX_TDM_CHAN11_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Msk = 0x800 + // Bit RX_TDM_CHAN11_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN = 0x800 + // Position of RX_TDM_CHAN12_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of RX_TDM_CHAN12_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit RX_TDM_CHAN12_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN = 0x1000 + // Position of RX_TDM_CHAN13_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of RX_TDM_CHAN13_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit RX_TDM_CHAN13_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN = 0x2000 + // Position of RX_TDM_CHAN14_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of RX_TDM_CHAN14_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit RX_TDM_CHAN14_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN = 0x4000 + // Position of RX_TDM_CHAN15_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of RX_TDM_CHAN15_EN field. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit RX_TDM_CHAN15_EN. + I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN = 0x8000 + // Position of RX_TDM_TOT_CHAN_NUM field. + I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of RX_TDM_TOT_CHAN_NUM field. + I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + + // TX_TDM_CTRL: I2S TX TDM mode control register + // Position of TX_TDM_CHAN0_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Pos = 0x0 + // Bit mask of TX_TDM_CHAN0_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Msk = 0x1 + // Bit TX_TDM_CHAN0_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN = 0x1 + // Position of TX_TDM_CHAN1_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Pos = 0x1 + // Bit mask of TX_TDM_CHAN1_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Msk = 0x2 + // Bit TX_TDM_CHAN1_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN = 0x2 + // Position of TX_TDM_CHAN2_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Pos = 0x2 + // Bit mask of TX_TDM_CHAN2_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Msk = 0x4 + // Bit TX_TDM_CHAN2_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN = 0x4 + // Position of TX_TDM_CHAN3_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Pos = 0x3 + // Bit mask of TX_TDM_CHAN3_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Msk = 0x8 + // Bit TX_TDM_CHAN3_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN = 0x8 + // Position of TX_TDM_CHAN4_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Pos = 0x4 + // Bit mask of TX_TDM_CHAN4_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Msk = 0x10 + // Bit TX_TDM_CHAN4_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN = 0x10 + // Position of TX_TDM_CHAN5_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Pos = 0x5 + // Bit mask of TX_TDM_CHAN5_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Msk = 0x20 + // Bit TX_TDM_CHAN5_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN = 0x20 + // Position of TX_TDM_CHAN6_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Pos = 0x6 + // Bit mask of TX_TDM_CHAN6_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Msk = 0x40 + // Bit TX_TDM_CHAN6_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN = 0x40 + // Position of TX_TDM_CHAN7_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Pos = 0x7 + // Bit mask of TX_TDM_CHAN7_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Msk = 0x80 + // Bit TX_TDM_CHAN7_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN = 0x80 + // Position of TX_TDM_CHAN8_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of TX_TDM_CHAN8_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Msk = 0x100 + // Bit TX_TDM_CHAN8_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN = 0x100 + // Position of TX_TDM_CHAN9_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of TX_TDM_CHAN9_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Msk = 0x200 + // Bit TX_TDM_CHAN9_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN = 0x200 + // Position of TX_TDM_CHAN10_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of TX_TDM_CHAN10_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Msk = 0x400 + // Bit TX_TDM_CHAN10_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN = 0x400 + // Position of TX_TDM_CHAN11_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of TX_TDM_CHAN11_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Msk = 0x800 + // Bit TX_TDM_CHAN11_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN = 0x800 + // Position of TX_TDM_CHAN12_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of TX_TDM_CHAN12_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit TX_TDM_CHAN12_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN = 0x1000 + // Position of TX_TDM_CHAN13_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of TX_TDM_CHAN13_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit TX_TDM_CHAN13_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN = 0x2000 + // Position of TX_TDM_CHAN14_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of TX_TDM_CHAN14_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit TX_TDM_CHAN14_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN = 0x4000 + // Position of TX_TDM_CHAN15_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of TX_TDM_CHAN15_EN field. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit TX_TDM_CHAN15_EN. + I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN = 0x8000 + // Position of TX_TDM_TOT_CHAN_NUM field. + I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of TX_TDM_TOT_CHAN_NUM field. + I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + // Position of TX_TDM_SKIP_MSK_EN field. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Pos = 0x14 + // Bit mask of TX_TDM_SKIP_MSK_EN field. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Msk = 0x100000 + // Bit TX_TDM_SKIP_MSK_EN. + I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN = 0x100000 + + // RX_TIMING: I2S RX timing control register + // Position of RX_SD_IN_DM field. + I2S_RX_TIMING_RX_SD_IN_DM_Pos = 0x0 + // Bit mask of RX_SD_IN_DM field. + I2S_RX_TIMING_RX_SD_IN_DM_Msk = 0x3 + // Position of RX_SD1_IN_DM field. + I2S_RX_TIMING_RX_SD1_IN_DM_Pos = 0x4 + // Bit mask of RX_SD1_IN_DM field. + I2S_RX_TIMING_RX_SD1_IN_DM_Msk = 0x30 + // Position of RX_SD2_IN_DM field. + I2S_RX_TIMING_RX_SD2_IN_DM_Pos = 0x8 + // Bit mask of RX_SD2_IN_DM field. + I2S_RX_TIMING_RX_SD2_IN_DM_Msk = 0x300 + // Position of RX_SD3_IN_DM field. + I2S_RX_TIMING_RX_SD3_IN_DM_Pos = 0xc + // Bit mask of RX_SD3_IN_DM field. + I2S_RX_TIMING_RX_SD3_IN_DM_Msk = 0x3000 + // Position of RX_WS_OUT_DM field. + I2S_RX_TIMING_RX_WS_OUT_DM_Pos = 0x10 + // Bit mask of RX_WS_OUT_DM field. + I2S_RX_TIMING_RX_WS_OUT_DM_Msk = 0x30000 + // Position of RX_BCK_OUT_DM field. + I2S_RX_TIMING_RX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of RX_BCK_OUT_DM field. + I2S_RX_TIMING_RX_BCK_OUT_DM_Msk = 0x300000 + // Position of RX_WS_IN_DM field. + I2S_RX_TIMING_RX_WS_IN_DM_Pos = 0x18 + // Bit mask of RX_WS_IN_DM field. + I2S_RX_TIMING_RX_WS_IN_DM_Msk = 0x3000000 + // Position of RX_BCK_IN_DM field. + I2S_RX_TIMING_RX_BCK_IN_DM_Pos = 0x1c + // Bit mask of RX_BCK_IN_DM field. + I2S_RX_TIMING_RX_BCK_IN_DM_Msk = 0x30000000 + + // TX_TIMING: I2S TX timing control register + // Position of TX_SD_OUT_DM field. + I2S_TX_TIMING_TX_SD_OUT_DM_Pos = 0x0 + // Bit mask of TX_SD_OUT_DM field. + I2S_TX_TIMING_TX_SD_OUT_DM_Msk = 0x3 + // Position of TX_SD1_OUT_DM field. + I2S_TX_TIMING_TX_SD1_OUT_DM_Pos = 0x4 + // Bit mask of TX_SD1_OUT_DM field. + I2S_TX_TIMING_TX_SD1_OUT_DM_Msk = 0x30 + // Position of TX_WS_OUT_DM field. + I2S_TX_TIMING_TX_WS_OUT_DM_Pos = 0x10 + // Bit mask of TX_WS_OUT_DM field. + I2S_TX_TIMING_TX_WS_OUT_DM_Msk = 0x30000 + // Position of TX_BCK_OUT_DM field. + I2S_TX_TIMING_TX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of TX_BCK_OUT_DM field. + I2S_TX_TIMING_TX_BCK_OUT_DM_Msk = 0x300000 + // Position of TX_WS_IN_DM field. + I2S_TX_TIMING_TX_WS_IN_DM_Pos = 0x18 + // Bit mask of TX_WS_IN_DM field. + I2S_TX_TIMING_TX_WS_IN_DM_Msk = 0x3000000 + // Position of TX_BCK_IN_DM field. + I2S_TX_TIMING_TX_BCK_IN_DM_Pos = 0x1c + // Bit mask of TX_BCK_IN_DM field. + I2S_TX_TIMING_TX_BCK_IN_DM_Msk = 0x30000000 + + // LC_HUNG_CONF: I2S HUNG configure register. + // Position of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Pos = 0x0 + // Bit mask of LC_FIFO_TIMEOUT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Msk = 0xff + // Position of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of LC_FIFO_TIMEOUT_SHIFT field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of LC_FIFO_TIMEOUT_ENA field. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit LC_FIFO_TIMEOUT_ENA. + I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA = 0x800 + + // RXEOF_NUM: I2S RX data number control register. + // Position of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Pos = 0x0 + // Bit mask of RX_EOF_NUM field. + I2S_RXEOF_NUM_RX_EOF_NUM_Msk = 0xfff + + // CONF_SIGLE_DATA: I2S signal data register + // Position of SINGLE_DATA field. + I2S_CONF_SIGLE_DATA_SINGLE_DATA_Pos = 0x0 + // Bit mask of SINGLE_DATA field. + I2S_CONF_SIGLE_DATA_SINGLE_DATA_Msk = 0xffffffff + + // STATE: I2S TX status register + // Position of TX_IDLE field. + I2S_STATE_TX_IDLE_Pos = 0x0 + // Bit mask of TX_IDLE field. + I2S_STATE_TX_IDLE_Msk = 0x1 + // Bit TX_IDLE. + I2S_STATE_TX_IDLE = 0x1 + + // DATE: Version control register + // Position of DATE field. + I2S_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2S_DATE_DATE_Msk = 0xfffffff +) + +// Constants for I2S1: I2S (Inter-IC Sound) Controller 1 +const ( + // INT_RAW: I2S interrupt raw register, valid in level. + // Position of RX_DONE_INT_RAW field. + I2S1_INT_RAW_RX_DONE_INT_RAW_Pos = 0x0 + // Bit mask of RX_DONE_INT_RAW field. + I2S1_INT_RAW_RX_DONE_INT_RAW_Msk = 0x1 + // Bit RX_DONE_INT_RAW. + I2S1_INT_RAW_RX_DONE_INT_RAW = 0x1 + // Position of TX_DONE_INT_RAW field. + I2S1_INT_RAW_TX_DONE_INT_RAW_Pos = 0x1 + // Bit mask of TX_DONE_INT_RAW field. + I2S1_INT_RAW_TX_DONE_INT_RAW_Msk = 0x2 + // Bit TX_DONE_INT_RAW. + I2S1_INT_RAW_TX_DONE_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + I2S1_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + I2S1_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + I2S1_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + I2S1_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + I2S1_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + I2S1_INT_RAW_TX_HUNG_INT_RAW = 0x8 + + // INT_ST: I2S interrupt status register. + // Position of RX_DONE_INT_ST field. + I2S1_INT_ST_RX_DONE_INT_ST_Pos = 0x0 + // Bit mask of RX_DONE_INT_ST field. + I2S1_INT_ST_RX_DONE_INT_ST_Msk = 0x1 + // Bit RX_DONE_INT_ST. + I2S1_INT_ST_RX_DONE_INT_ST = 0x1 + // Position of TX_DONE_INT_ST field. + I2S1_INT_ST_TX_DONE_INT_ST_Pos = 0x1 + // Bit mask of TX_DONE_INT_ST field. + I2S1_INT_ST_TX_DONE_INT_ST_Msk = 0x2 + // Bit TX_DONE_INT_ST. + I2S1_INT_ST_TX_DONE_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + I2S1_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + I2S1_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + I2S1_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + I2S1_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + I2S1_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + I2S1_INT_ST_TX_HUNG_INT_ST = 0x8 + + // INT_ENA: I2S interrupt enable register. + // Position of RX_DONE_INT_ENA field. + I2S1_INT_ENA_RX_DONE_INT_ENA_Pos = 0x0 + // Bit mask of RX_DONE_INT_ENA field. + I2S1_INT_ENA_RX_DONE_INT_ENA_Msk = 0x1 + // Bit RX_DONE_INT_ENA. + I2S1_INT_ENA_RX_DONE_INT_ENA = 0x1 + // Position of TX_DONE_INT_ENA field. + I2S1_INT_ENA_TX_DONE_INT_ENA_Pos = 0x1 + // Bit mask of TX_DONE_INT_ENA field. + I2S1_INT_ENA_TX_DONE_INT_ENA_Msk = 0x2 + // Bit TX_DONE_INT_ENA. + I2S1_INT_ENA_TX_DONE_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + I2S1_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + I2S1_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + I2S1_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + I2S1_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + I2S1_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + I2S1_INT_ENA_TX_HUNG_INT_ENA = 0x8 + + // INT_CLR: I2S interrupt clear register. + // Position of RX_DONE_INT_CLR field. + I2S1_INT_CLR_RX_DONE_INT_CLR_Pos = 0x0 + // Bit mask of RX_DONE_INT_CLR field. + I2S1_INT_CLR_RX_DONE_INT_CLR_Msk = 0x1 + // Bit RX_DONE_INT_CLR. + I2S1_INT_CLR_RX_DONE_INT_CLR = 0x1 + // Position of TX_DONE_INT_CLR field. + I2S1_INT_CLR_TX_DONE_INT_CLR_Pos = 0x1 + // Bit mask of TX_DONE_INT_CLR field. + I2S1_INT_CLR_TX_DONE_INT_CLR_Msk = 0x2 + // Bit TX_DONE_INT_CLR. + I2S1_INT_CLR_TX_DONE_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + I2S1_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + I2S1_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + I2S1_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + I2S1_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + I2S1_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + I2S1_INT_CLR_TX_HUNG_INT_CLR = 0x8 + + // RX_CONF: I2S RX configure register + // Position of RX_RESET field. + I2S1_RX_CONF_RX_RESET_Pos = 0x0 + // Bit mask of RX_RESET field. + I2S1_RX_CONF_RX_RESET_Msk = 0x1 + // Bit RX_RESET. + I2S1_RX_CONF_RX_RESET = 0x1 + // Position of RX_FIFO_RESET field. + I2S1_RX_CONF_RX_FIFO_RESET_Pos = 0x1 + // Bit mask of RX_FIFO_RESET field. + I2S1_RX_CONF_RX_FIFO_RESET_Msk = 0x2 + // Bit RX_FIFO_RESET. + I2S1_RX_CONF_RX_FIFO_RESET = 0x2 + // Position of RX_START field. + I2S1_RX_CONF_RX_START_Pos = 0x2 + // Bit mask of RX_START field. + I2S1_RX_CONF_RX_START_Msk = 0x4 + // Bit RX_START. + I2S1_RX_CONF_RX_START = 0x4 + // Position of RX_SLAVE_MOD field. + I2S1_RX_CONF_RX_SLAVE_MOD_Pos = 0x3 + // Bit mask of RX_SLAVE_MOD field. + I2S1_RX_CONF_RX_SLAVE_MOD_Msk = 0x8 + // Bit RX_SLAVE_MOD. + I2S1_RX_CONF_RX_SLAVE_MOD = 0x8 + // Position of RX_MONO field. + I2S1_RX_CONF_RX_MONO_Pos = 0x5 + // Bit mask of RX_MONO field. + I2S1_RX_CONF_RX_MONO_Msk = 0x20 + // Bit RX_MONO. + I2S1_RX_CONF_RX_MONO = 0x20 + // Position of RX_BIG_ENDIAN field. + I2S1_RX_CONF_RX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of RX_BIG_ENDIAN field. + I2S1_RX_CONF_RX_BIG_ENDIAN_Msk = 0x80 + // Bit RX_BIG_ENDIAN. + I2S1_RX_CONF_RX_BIG_ENDIAN = 0x80 + // Position of RX_UPDATE field. + I2S1_RX_CONF_RX_UPDATE_Pos = 0x8 + // Bit mask of RX_UPDATE field. + I2S1_RX_CONF_RX_UPDATE_Msk = 0x100 + // Bit RX_UPDATE. + I2S1_RX_CONF_RX_UPDATE = 0x100 + // Position of RX_MONO_FST_VLD field. + I2S1_RX_CONF_RX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of RX_MONO_FST_VLD field. + I2S1_RX_CONF_RX_MONO_FST_VLD_Msk = 0x200 + // Bit RX_MONO_FST_VLD. + I2S1_RX_CONF_RX_MONO_FST_VLD = 0x200 + // Position of RX_PCM_CONF field. + I2S1_RX_CONF_RX_PCM_CONF_Pos = 0xa + // Bit mask of RX_PCM_CONF field. + I2S1_RX_CONF_RX_PCM_CONF_Msk = 0xc00 + // Position of RX_PCM_BYPASS field. + I2S1_RX_CONF_RX_PCM_BYPASS_Pos = 0xc + // Bit mask of RX_PCM_BYPASS field. + I2S1_RX_CONF_RX_PCM_BYPASS_Msk = 0x1000 + // Bit RX_PCM_BYPASS. + I2S1_RX_CONF_RX_PCM_BYPASS = 0x1000 + // Position of RX_STOP_MODE field. + I2S1_RX_CONF_RX_STOP_MODE_Pos = 0xd + // Bit mask of RX_STOP_MODE field. + I2S1_RX_CONF_RX_STOP_MODE_Msk = 0x6000 + // Position of RX_LEFT_ALIGN field. + I2S1_RX_CONF_RX_LEFT_ALIGN_Pos = 0xf + // Bit mask of RX_LEFT_ALIGN field. + I2S1_RX_CONF_RX_LEFT_ALIGN_Msk = 0x8000 + // Bit RX_LEFT_ALIGN. + I2S1_RX_CONF_RX_LEFT_ALIGN = 0x8000 + // Position of RX_24_FILL_EN field. + I2S1_RX_CONF_RX_24_FILL_EN_Pos = 0x10 + // Bit mask of RX_24_FILL_EN field. + I2S1_RX_CONF_RX_24_FILL_EN_Msk = 0x10000 + // Bit RX_24_FILL_EN. + I2S1_RX_CONF_RX_24_FILL_EN = 0x10000 + // Position of RX_WS_IDLE_POL field. + I2S1_RX_CONF_RX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of RX_WS_IDLE_POL field. + I2S1_RX_CONF_RX_WS_IDLE_POL_Msk = 0x20000 + // Bit RX_WS_IDLE_POL. + I2S1_RX_CONF_RX_WS_IDLE_POL = 0x20000 + // Position of RX_BIT_ORDER field. + I2S1_RX_CONF_RX_BIT_ORDER_Pos = 0x12 + // Bit mask of RX_BIT_ORDER field. + I2S1_RX_CONF_RX_BIT_ORDER_Msk = 0x40000 + // Bit RX_BIT_ORDER. + I2S1_RX_CONF_RX_BIT_ORDER = 0x40000 + // Position of RX_TDM_EN field. + I2S1_RX_CONF_RX_TDM_EN_Pos = 0x13 + // Bit mask of RX_TDM_EN field. + I2S1_RX_CONF_RX_TDM_EN_Msk = 0x80000 + // Bit RX_TDM_EN. + I2S1_RX_CONF_RX_TDM_EN = 0x80000 + // Position of RX_PDM_EN field. + I2S1_RX_CONF_RX_PDM_EN_Pos = 0x14 + // Bit mask of RX_PDM_EN field. + I2S1_RX_CONF_RX_PDM_EN_Msk = 0x100000 + // Bit RX_PDM_EN. + I2S1_RX_CONF_RX_PDM_EN = 0x100000 + + // TX_CONF: I2S TX configure register + // Position of TX_RESET field. + I2S1_TX_CONF_TX_RESET_Pos = 0x0 + // Bit mask of TX_RESET field. + I2S1_TX_CONF_TX_RESET_Msk = 0x1 + // Bit TX_RESET. + I2S1_TX_CONF_TX_RESET = 0x1 + // Position of TX_FIFO_RESET field. + I2S1_TX_CONF_TX_FIFO_RESET_Pos = 0x1 + // Bit mask of TX_FIFO_RESET field. + I2S1_TX_CONF_TX_FIFO_RESET_Msk = 0x2 + // Bit TX_FIFO_RESET. + I2S1_TX_CONF_TX_FIFO_RESET = 0x2 + // Position of TX_START field. + I2S1_TX_CONF_TX_START_Pos = 0x2 + // Bit mask of TX_START field. + I2S1_TX_CONF_TX_START_Msk = 0x4 + // Bit TX_START. + I2S1_TX_CONF_TX_START = 0x4 + // Position of TX_SLAVE_MOD field. + I2S1_TX_CONF_TX_SLAVE_MOD_Pos = 0x3 + // Bit mask of TX_SLAVE_MOD field. + I2S1_TX_CONF_TX_SLAVE_MOD_Msk = 0x8 + // Bit TX_SLAVE_MOD. + I2S1_TX_CONF_TX_SLAVE_MOD = 0x8 + // Position of TX_MONO field. + I2S1_TX_CONF_TX_MONO_Pos = 0x5 + // Bit mask of TX_MONO field. + I2S1_TX_CONF_TX_MONO_Msk = 0x20 + // Bit TX_MONO. + I2S1_TX_CONF_TX_MONO = 0x20 + // Position of TX_CHAN_EQUAL field. + I2S1_TX_CONF_TX_CHAN_EQUAL_Pos = 0x6 + // Bit mask of TX_CHAN_EQUAL field. + I2S1_TX_CONF_TX_CHAN_EQUAL_Msk = 0x40 + // Bit TX_CHAN_EQUAL. + I2S1_TX_CONF_TX_CHAN_EQUAL = 0x40 + // Position of TX_BIG_ENDIAN field. + I2S1_TX_CONF_TX_BIG_ENDIAN_Pos = 0x7 + // Bit mask of TX_BIG_ENDIAN field. + I2S1_TX_CONF_TX_BIG_ENDIAN_Msk = 0x80 + // Bit TX_BIG_ENDIAN. + I2S1_TX_CONF_TX_BIG_ENDIAN = 0x80 + // Position of TX_UPDATE field. + I2S1_TX_CONF_TX_UPDATE_Pos = 0x8 + // Bit mask of TX_UPDATE field. + I2S1_TX_CONF_TX_UPDATE_Msk = 0x100 + // Bit TX_UPDATE. + I2S1_TX_CONF_TX_UPDATE = 0x100 + // Position of TX_MONO_FST_VLD field. + I2S1_TX_CONF_TX_MONO_FST_VLD_Pos = 0x9 + // Bit mask of TX_MONO_FST_VLD field. + I2S1_TX_CONF_TX_MONO_FST_VLD_Msk = 0x200 + // Bit TX_MONO_FST_VLD. + I2S1_TX_CONF_TX_MONO_FST_VLD = 0x200 + // Position of TX_PCM_CONF field. + I2S1_TX_CONF_TX_PCM_CONF_Pos = 0xa + // Bit mask of TX_PCM_CONF field. + I2S1_TX_CONF_TX_PCM_CONF_Msk = 0xc00 + // Position of TX_PCM_BYPASS field. + I2S1_TX_CONF_TX_PCM_BYPASS_Pos = 0xc + // Bit mask of TX_PCM_BYPASS field. + I2S1_TX_CONF_TX_PCM_BYPASS_Msk = 0x1000 + // Bit TX_PCM_BYPASS. + I2S1_TX_CONF_TX_PCM_BYPASS = 0x1000 + // Position of TX_STOP_EN field. + I2S1_TX_CONF_TX_STOP_EN_Pos = 0xd + // Bit mask of TX_STOP_EN field. + I2S1_TX_CONF_TX_STOP_EN_Msk = 0x2000 + // Bit TX_STOP_EN. + I2S1_TX_CONF_TX_STOP_EN = 0x2000 + // Position of TX_LEFT_ALIGN field. + I2S1_TX_CONF_TX_LEFT_ALIGN_Pos = 0xf + // Bit mask of TX_LEFT_ALIGN field. + I2S1_TX_CONF_TX_LEFT_ALIGN_Msk = 0x8000 + // Bit TX_LEFT_ALIGN. + I2S1_TX_CONF_TX_LEFT_ALIGN = 0x8000 + // Position of TX_24_FILL_EN field. + I2S1_TX_CONF_TX_24_FILL_EN_Pos = 0x10 + // Bit mask of TX_24_FILL_EN field. + I2S1_TX_CONF_TX_24_FILL_EN_Msk = 0x10000 + // Bit TX_24_FILL_EN. + I2S1_TX_CONF_TX_24_FILL_EN = 0x10000 + // Position of TX_WS_IDLE_POL field. + I2S1_TX_CONF_TX_WS_IDLE_POL_Pos = 0x11 + // Bit mask of TX_WS_IDLE_POL field. + I2S1_TX_CONF_TX_WS_IDLE_POL_Msk = 0x20000 + // Bit TX_WS_IDLE_POL. + I2S1_TX_CONF_TX_WS_IDLE_POL = 0x20000 + // Position of TX_BIT_ORDER field. + I2S1_TX_CONF_TX_BIT_ORDER_Pos = 0x12 + // Bit mask of TX_BIT_ORDER field. + I2S1_TX_CONF_TX_BIT_ORDER_Msk = 0x40000 + // Bit TX_BIT_ORDER. + I2S1_TX_CONF_TX_BIT_ORDER = 0x40000 + // Position of TX_TDM_EN field. + I2S1_TX_CONF_TX_TDM_EN_Pos = 0x13 + // Bit mask of TX_TDM_EN field. + I2S1_TX_CONF_TX_TDM_EN_Msk = 0x80000 + // Bit TX_TDM_EN. + I2S1_TX_CONF_TX_TDM_EN = 0x80000 + // Position of TX_PDM_EN field. + I2S1_TX_CONF_TX_PDM_EN_Pos = 0x14 + // Bit mask of TX_PDM_EN field. + I2S1_TX_CONF_TX_PDM_EN_Msk = 0x100000 + // Bit TX_PDM_EN. + I2S1_TX_CONF_TX_PDM_EN = 0x100000 + // Position of TX_CHAN_MOD field. + I2S1_TX_CONF_TX_CHAN_MOD_Pos = 0x18 + // Bit mask of TX_CHAN_MOD field. + I2S1_TX_CONF_TX_CHAN_MOD_Msk = 0x7000000 + // Position of SIG_LOOPBACK field. + I2S1_TX_CONF_SIG_LOOPBACK_Pos = 0x1b + // Bit mask of SIG_LOOPBACK field. + I2S1_TX_CONF_SIG_LOOPBACK_Msk = 0x8000000 + // Bit SIG_LOOPBACK. + I2S1_TX_CONF_SIG_LOOPBACK = 0x8000000 + + // RX_CONF1: I2S RX configure register 1 + // Position of RX_TDM_WS_WIDTH field. + I2S1_RX_CONF1_RX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of RX_TDM_WS_WIDTH field. + I2S1_RX_CONF1_RX_TDM_WS_WIDTH_Msk = 0x7f + // Position of RX_BCK_DIV_NUM field. + I2S1_RX_CONF1_RX_BCK_DIV_NUM_Pos = 0x7 + // Bit mask of RX_BCK_DIV_NUM field. + I2S1_RX_CONF1_RX_BCK_DIV_NUM_Msk = 0x1f80 + // Position of RX_BITS_MOD field. + I2S1_RX_CONF1_RX_BITS_MOD_Pos = 0xd + // Bit mask of RX_BITS_MOD field. + I2S1_RX_CONF1_RX_BITS_MOD_Msk = 0x3e000 + // Position of RX_HALF_SAMPLE_BITS field. + I2S1_RX_CONF1_RX_HALF_SAMPLE_BITS_Pos = 0x12 + // Bit mask of RX_HALF_SAMPLE_BITS field. + I2S1_RX_CONF1_RX_HALF_SAMPLE_BITS_Msk = 0xfc0000 + // Position of RX_TDM_CHAN_BITS field. + I2S1_RX_CONF1_RX_TDM_CHAN_BITS_Pos = 0x18 + // Bit mask of RX_TDM_CHAN_BITS field. + I2S1_RX_CONF1_RX_TDM_CHAN_BITS_Msk = 0x1f000000 + // Position of RX_MSB_SHIFT field. + I2S1_RX_CONF1_RX_MSB_SHIFT_Pos = 0x1d + // Bit mask of RX_MSB_SHIFT field. + I2S1_RX_CONF1_RX_MSB_SHIFT_Msk = 0x20000000 + // Bit RX_MSB_SHIFT. + I2S1_RX_CONF1_RX_MSB_SHIFT = 0x20000000 + + // TX_CONF1: I2S TX configure register 1 + // Position of TX_TDM_WS_WIDTH field. + I2S1_TX_CONF1_TX_TDM_WS_WIDTH_Pos = 0x0 + // Bit mask of TX_TDM_WS_WIDTH field. + I2S1_TX_CONF1_TX_TDM_WS_WIDTH_Msk = 0x7f + // Position of TX_BCK_DIV_NUM field. + I2S1_TX_CONF1_TX_BCK_DIV_NUM_Pos = 0x7 + // Bit mask of TX_BCK_DIV_NUM field. + I2S1_TX_CONF1_TX_BCK_DIV_NUM_Msk = 0x1f80 + // Position of TX_BITS_MOD field. + I2S1_TX_CONF1_TX_BITS_MOD_Pos = 0xd + // Bit mask of TX_BITS_MOD field. + I2S1_TX_CONF1_TX_BITS_MOD_Msk = 0x3e000 + // Position of TX_HALF_SAMPLE_BITS field. + I2S1_TX_CONF1_TX_HALF_SAMPLE_BITS_Pos = 0x12 + // Bit mask of TX_HALF_SAMPLE_BITS field. + I2S1_TX_CONF1_TX_HALF_SAMPLE_BITS_Msk = 0xfc0000 + // Position of TX_TDM_CHAN_BITS field. + I2S1_TX_CONF1_TX_TDM_CHAN_BITS_Pos = 0x18 + // Bit mask of TX_TDM_CHAN_BITS field. + I2S1_TX_CONF1_TX_TDM_CHAN_BITS_Msk = 0x1f000000 + // Position of TX_MSB_SHIFT field. + I2S1_TX_CONF1_TX_MSB_SHIFT_Pos = 0x1d + // Bit mask of TX_MSB_SHIFT field. + I2S1_TX_CONF1_TX_MSB_SHIFT_Msk = 0x20000000 + // Bit TX_MSB_SHIFT. + I2S1_TX_CONF1_TX_MSB_SHIFT = 0x20000000 + // Position of TX_BCK_NO_DLY field. + I2S1_TX_CONF1_TX_BCK_NO_DLY_Pos = 0x1e + // Bit mask of TX_BCK_NO_DLY field. + I2S1_TX_CONF1_TX_BCK_NO_DLY_Msk = 0x40000000 + // Bit TX_BCK_NO_DLY. + I2S1_TX_CONF1_TX_BCK_NO_DLY = 0x40000000 + + // RX_CLKM_CONF: I2S RX clock configure register + // Position of RX_CLKM_DIV_NUM field. + I2S1_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_NUM field. + I2S1_RX_CLKM_CONF_RX_CLKM_DIV_NUM_Msk = 0xff + // Position of RX_CLK_ACTIVE field. + I2S1_RX_CLKM_CONF_RX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of RX_CLK_ACTIVE field. + I2S1_RX_CLKM_CONF_RX_CLK_ACTIVE_Msk = 0x4000000 + // Bit RX_CLK_ACTIVE. + I2S1_RX_CLKM_CONF_RX_CLK_ACTIVE = 0x4000000 + // Position of RX_CLK_SEL field. + I2S1_RX_CLKM_CONF_RX_CLK_SEL_Pos = 0x1b + // Bit mask of RX_CLK_SEL field. + I2S1_RX_CLKM_CONF_RX_CLK_SEL_Msk = 0x18000000 + // Position of MCLK_SEL field. + I2S1_RX_CLKM_CONF_MCLK_SEL_Pos = 0x1d + // Bit mask of MCLK_SEL field. + I2S1_RX_CLKM_CONF_MCLK_SEL_Msk = 0x20000000 + // Bit MCLK_SEL. + I2S1_RX_CLKM_CONF_MCLK_SEL = 0x20000000 + + // TX_CLKM_CONF: I2S TX clock configure register + // Position of TX_CLKM_DIV_NUM field. + I2S1_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_NUM field. + I2S1_TX_CLKM_CONF_TX_CLKM_DIV_NUM_Msk = 0xff + // Position of TX_CLK_ACTIVE field. + I2S1_TX_CLKM_CONF_TX_CLK_ACTIVE_Pos = 0x1a + // Bit mask of TX_CLK_ACTIVE field. + I2S1_TX_CLKM_CONF_TX_CLK_ACTIVE_Msk = 0x4000000 + // Bit TX_CLK_ACTIVE. + I2S1_TX_CLKM_CONF_TX_CLK_ACTIVE = 0x4000000 + // Position of TX_CLK_SEL field. + I2S1_TX_CLKM_CONF_TX_CLK_SEL_Pos = 0x1b + // Bit mask of TX_CLK_SEL field. + I2S1_TX_CLKM_CONF_TX_CLK_SEL_Msk = 0x18000000 + // Position of CLK_EN field. + I2S1_TX_CLKM_CONF_CLK_EN_Pos = 0x1d + // Bit mask of CLK_EN field. + I2S1_TX_CLKM_CONF_CLK_EN_Msk = 0x20000000 + // Bit CLK_EN. + I2S1_TX_CLKM_CONF_CLK_EN = 0x20000000 + + // RX_CLKM_DIV_CONF: I2S RX module clock divider configure register + // Position of RX_CLKM_DIV_Z field. + I2S1_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of RX_CLKM_DIV_Z field. + I2S1_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Z_Msk = 0x1ff + // Position of RX_CLKM_DIV_Y field. + I2S1_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of RX_CLKM_DIV_Y field. + I2S1_RX_CLKM_DIV_CONF_RX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of RX_CLKM_DIV_X field. + I2S1_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of RX_CLKM_DIV_X field. + I2S1_RX_CLKM_DIV_CONF_RX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of RX_CLKM_DIV_YN1 field. + I2S1_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of RX_CLKM_DIV_YN1 field. + I2S1_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit RX_CLKM_DIV_YN1. + I2S1_RX_CLKM_DIV_CONF_RX_CLKM_DIV_YN1 = 0x8000000 + + // TX_CLKM_DIV_CONF: I2S TX module clock divider configure register + // Position of TX_CLKM_DIV_Z field. + I2S1_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Pos = 0x0 + // Bit mask of TX_CLKM_DIV_Z field. + I2S1_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Z_Msk = 0x1ff + // Position of TX_CLKM_DIV_Y field. + I2S1_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Pos = 0x9 + // Bit mask of TX_CLKM_DIV_Y field. + I2S1_TX_CLKM_DIV_CONF_TX_CLKM_DIV_Y_Msk = 0x3fe00 + // Position of TX_CLKM_DIV_X field. + I2S1_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Pos = 0x12 + // Bit mask of TX_CLKM_DIV_X field. + I2S1_TX_CLKM_DIV_CONF_TX_CLKM_DIV_X_Msk = 0x7fc0000 + // Position of TX_CLKM_DIV_YN1 field. + I2S1_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Pos = 0x1b + // Bit mask of TX_CLKM_DIV_YN1 field. + I2S1_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1_Msk = 0x8000000 + // Bit TX_CLKM_DIV_YN1. + I2S1_TX_CLKM_DIV_CONF_TX_CLKM_DIV_YN1 = 0x8000000 + + // RX_TDM_CTRL: I2S TX TDM mode control register + // Position of RX_TDM_PDM_CHAN0_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Pos = 0x0 + // Bit mask of RX_TDM_PDM_CHAN0_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Msk = 0x1 + // Bit RX_TDM_PDM_CHAN0_EN. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN = 0x1 + // Position of RX_TDM_PDM_CHAN1_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Pos = 0x1 + // Bit mask of RX_TDM_PDM_CHAN1_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Msk = 0x2 + // Bit RX_TDM_PDM_CHAN1_EN. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN = 0x2 + // Position of RX_TDM_PDM_CHAN2_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Pos = 0x2 + // Bit mask of RX_TDM_PDM_CHAN2_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Msk = 0x4 + // Bit RX_TDM_PDM_CHAN2_EN. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN = 0x4 + // Position of RX_TDM_PDM_CHAN3_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Pos = 0x3 + // Bit mask of RX_TDM_PDM_CHAN3_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Msk = 0x8 + // Bit RX_TDM_PDM_CHAN3_EN. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN = 0x8 + // Position of RX_TDM_PDM_CHAN4_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Pos = 0x4 + // Bit mask of RX_TDM_PDM_CHAN4_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Msk = 0x10 + // Bit RX_TDM_PDM_CHAN4_EN. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN = 0x10 + // Position of RX_TDM_PDM_CHAN5_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Pos = 0x5 + // Bit mask of RX_TDM_PDM_CHAN5_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Msk = 0x20 + // Bit RX_TDM_PDM_CHAN5_EN. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN = 0x20 + // Position of RX_TDM_PDM_CHAN6_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Pos = 0x6 + // Bit mask of RX_TDM_PDM_CHAN6_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Msk = 0x40 + // Bit RX_TDM_PDM_CHAN6_EN. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN = 0x40 + // Position of RX_TDM_PDM_CHAN7_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Pos = 0x7 + // Bit mask of RX_TDM_PDM_CHAN7_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Msk = 0x80 + // Bit RX_TDM_PDM_CHAN7_EN. + I2S1_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN = 0x80 + // Position of RX_TDM_CHAN8_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of RX_TDM_CHAN8_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Msk = 0x100 + // Bit RX_TDM_CHAN8_EN. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN8_EN = 0x100 + // Position of RX_TDM_CHAN9_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of RX_TDM_CHAN9_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Msk = 0x200 + // Bit RX_TDM_CHAN9_EN. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN9_EN = 0x200 + // Position of RX_TDM_CHAN10_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of RX_TDM_CHAN10_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Msk = 0x400 + // Bit RX_TDM_CHAN10_EN. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN10_EN = 0x400 + // Position of RX_TDM_CHAN11_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of RX_TDM_CHAN11_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Msk = 0x800 + // Bit RX_TDM_CHAN11_EN. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN11_EN = 0x800 + // Position of RX_TDM_CHAN12_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of RX_TDM_CHAN12_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit RX_TDM_CHAN12_EN. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN12_EN = 0x1000 + // Position of RX_TDM_CHAN13_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of RX_TDM_CHAN13_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit RX_TDM_CHAN13_EN. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN13_EN = 0x2000 + // Position of RX_TDM_CHAN14_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of RX_TDM_CHAN14_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit RX_TDM_CHAN14_EN. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN14_EN = 0x4000 + // Position of RX_TDM_CHAN15_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of RX_TDM_CHAN15_EN field. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit RX_TDM_CHAN15_EN. + I2S1_RX_TDM_CTRL_RX_TDM_CHAN15_EN = 0x8000 + // Position of RX_TDM_TOT_CHAN_NUM field. + I2S1_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of RX_TDM_TOT_CHAN_NUM field. + I2S1_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + + // TX_TDM_CTRL: I2S TX TDM mode control register + // Position of TX_TDM_CHAN0_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Pos = 0x0 + // Bit mask of TX_TDM_CHAN0_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Msk = 0x1 + // Bit TX_TDM_CHAN0_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN0_EN = 0x1 + // Position of TX_TDM_CHAN1_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Pos = 0x1 + // Bit mask of TX_TDM_CHAN1_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Msk = 0x2 + // Bit TX_TDM_CHAN1_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN1_EN = 0x2 + // Position of TX_TDM_CHAN2_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Pos = 0x2 + // Bit mask of TX_TDM_CHAN2_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Msk = 0x4 + // Bit TX_TDM_CHAN2_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN2_EN = 0x4 + // Position of TX_TDM_CHAN3_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Pos = 0x3 + // Bit mask of TX_TDM_CHAN3_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Msk = 0x8 + // Bit TX_TDM_CHAN3_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN3_EN = 0x8 + // Position of TX_TDM_CHAN4_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Pos = 0x4 + // Bit mask of TX_TDM_CHAN4_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Msk = 0x10 + // Bit TX_TDM_CHAN4_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN4_EN = 0x10 + // Position of TX_TDM_CHAN5_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Pos = 0x5 + // Bit mask of TX_TDM_CHAN5_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Msk = 0x20 + // Bit TX_TDM_CHAN5_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN5_EN = 0x20 + // Position of TX_TDM_CHAN6_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Pos = 0x6 + // Bit mask of TX_TDM_CHAN6_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Msk = 0x40 + // Bit TX_TDM_CHAN6_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN6_EN = 0x40 + // Position of TX_TDM_CHAN7_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Pos = 0x7 + // Bit mask of TX_TDM_CHAN7_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Msk = 0x80 + // Bit TX_TDM_CHAN7_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN7_EN = 0x80 + // Position of TX_TDM_CHAN8_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Pos = 0x8 + // Bit mask of TX_TDM_CHAN8_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Msk = 0x100 + // Bit TX_TDM_CHAN8_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN8_EN = 0x100 + // Position of TX_TDM_CHAN9_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Pos = 0x9 + // Bit mask of TX_TDM_CHAN9_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Msk = 0x200 + // Bit TX_TDM_CHAN9_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN9_EN = 0x200 + // Position of TX_TDM_CHAN10_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Pos = 0xa + // Bit mask of TX_TDM_CHAN10_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Msk = 0x400 + // Bit TX_TDM_CHAN10_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN10_EN = 0x400 + // Position of TX_TDM_CHAN11_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Pos = 0xb + // Bit mask of TX_TDM_CHAN11_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Msk = 0x800 + // Bit TX_TDM_CHAN11_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN11_EN = 0x800 + // Position of TX_TDM_CHAN12_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Pos = 0xc + // Bit mask of TX_TDM_CHAN12_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Msk = 0x1000 + // Bit TX_TDM_CHAN12_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN12_EN = 0x1000 + // Position of TX_TDM_CHAN13_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Pos = 0xd + // Bit mask of TX_TDM_CHAN13_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Msk = 0x2000 + // Bit TX_TDM_CHAN13_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN13_EN = 0x2000 + // Position of TX_TDM_CHAN14_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Pos = 0xe + // Bit mask of TX_TDM_CHAN14_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Msk = 0x4000 + // Bit TX_TDM_CHAN14_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN14_EN = 0x4000 + // Position of TX_TDM_CHAN15_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Pos = 0xf + // Bit mask of TX_TDM_CHAN15_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Msk = 0x8000 + // Bit TX_TDM_CHAN15_EN. + I2S1_TX_TDM_CTRL_TX_TDM_CHAN15_EN = 0x8000 + // Position of TX_TDM_TOT_CHAN_NUM field. + I2S1_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Pos = 0x10 + // Bit mask of TX_TDM_TOT_CHAN_NUM field. + I2S1_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Msk = 0xf0000 + // Position of TX_TDM_SKIP_MSK_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Pos = 0x14 + // Bit mask of TX_TDM_SKIP_MSK_EN field. + I2S1_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Msk = 0x100000 + // Bit TX_TDM_SKIP_MSK_EN. + I2S1_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN = 0x100000 + + // RX_TIMING: I2S RX timing control register + // Position of RX_SD_IN_DM field. + I2S1_RX_TIMING_RX_SD_IN_DM_Pos = 0x0 + // Bit mask of RX_SD_IN_DM field. + I2S1_RX_TIMING_RX_SD_IN_DM_Msk = 0x3 + // Position of RX_WS_OUT_DM field. + I2S1_RX_TIMING_RX_WS_OUT_DM_Pos = 0x10 + // Bit mask of RX_WS_OUT_DM field. + I2S1_RX_TIMING_RX_WS_OUT_DM_Msk = 0x30000 + // Position of RX_BCK_OUT_DM field. + I2S1_RX_TIMING_RX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of RX_BCK_OUT_DM field. + I2S1_RX_TIMING_RX_BCK_OUT_DM_Msk = 0x300000 + // Position of RX_WS_IN_DM field. + I2S1_RX_TIMING_RX_WS_IN_DM_Pos = 0x18 + // Bit mask of RX_WS_IN_DM field. + I2S1_RX_TIMING_RX_WS_IN_DM_Msk = 0x3000000 + // Position of RX_BCK_IN_DM field. + I2S1_RX_TIMING_RX_BCK_IN_DM_Pos = 0x1c + // Bit mask of RX_BCK_IN_DM field. + I2S1_RX_TIMING_RX_BCK_IN_DM_Msk = 0x30000000 + + // TX_TIMING: I2S TX timing control register + // Position of TX_SD_OUT_DM field. + I2S1_TX_TIMING_TX_SD_OUT_DM_Pos = 0x0 + // Bit mask of TX_SD_OUT_DM field. + I2S1_TX_TIMING_TX_SD_OUT_DM_Msk = 0x3 + // Position of TX_SD1_OUT_DM field. + I2S1_TX_TIMING_TX_SD1_OUT_DM_Pos = 0x4 + // Bit mask of TX_SD1_OUT_DM field. + I2S1_TX_TIMING_TX_SD1_OUT_DM_Msk = 0x30 + // Position of TX_WS_OUT_DM field. + I2S1_TX_TIMING_TX_WS_OUT_DM_Pos = 0x10 + // Bit mask of TX_WS_OUT_DM field. + I2S1_TX_TIMING_TX_WS_OUT_DM_Msk = 0x30000 + // Position of TX_BCK_OUT_DM field. + I2S1_TX_TIMING_TX_BCK_OUT_DM_Pos = 0x14 + // Bit mask of TX_BCK_OUT_DM field. + I2S1_TX_TIMING_TX_BCK_OUT_DM_Msk = 0x300000 + // Position of TX_WS_IN_DM field. + I2S1_TX_TIMING_TX_WS_IN_DM_Pos = 0x18 + // Bit mask of TX_WS_IN_DM field. + I2S1_TX_TIMING_TX_WS_IN_DM_Msk = 0x3000000 + // Position of TX_BCK_IN_DM field. + I2S1_TX_TIMING_TX_BCK_IN_DM_Pos = 0x1c + // Bit mask of TX_BCK_IN_DM field. + I2S1_TX_TIMING_TX_BCK_IN_DM_Msk = 0x30000000 + + // LC_HUNG_CONF: I2S HUNG configure register. + // Position of LC_FIFO_TIMEOUT field. + I2S1_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Pos = 0x0 + // Bit mask of LC_FIFO_TIMEOUT field. + I2S1_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Msk = 0xff + // Position of LC_FIFO_TIMEOUT_SHIFT field. + I2S1_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of LC_FIFO_TIMEOUT_SHIFT field. + I2S1_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of LC_FIFO_TIMEOUT_ENA field. + I2S1_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of LC_FIFO_TIMEOUT_ENA field. + I2S1_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit LC_FIFO_TIMEOUT_ENA. + I2S1_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA = 0x800 + + // RXEOF_NUM: I2S RX data number control register. + // Position of RX_EOF_NUM field. + I2S1_RXEOF_NUM_RX_EOF_NUM_Pos = 0x0 + // Bit mask of RX_EOF_NUM field. + I2S1_RXEOF_NUM_RX_EOF_NUM_Msk = 0xfff + + // CONF_SIGLE_DATA: I2S signal data register + // Position of SINGLE_DATA field. + I2S1_CONF_SIGLE_DATA_SINGLE_DATA_Pos = 0x0 + // Bit mask of SINGLE_DATA field. + I2S1_CONF_SIGLE_DATA_SINGLE_DATA_Msk = 0xffffffff + + // STATE: I2S TX status register + // Position of TX_IDLE field. + I2S1_STATE_TX_IDLE_Pos = 0x0 + // Bit mask of TX_IDLE field. + I2S1_STATE_TX_IDLE_Msk = 0x1 + // Bit TX_IDLE. + I2S1_STATE_TX_IDLE = 0x1 + + // DATE: Version control register + // Position of DATE field. + I2S1_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + I2S1_DATE_DATE_Msk = 0xfffffff +) + +// Constants for INTERRUPT_CORE0: Interrupt Controller (Core 0) +const ( + // PRO_MAC_INTR_MAP: mac interrupt configuration register + // Position of MAC_INTR_MAP field. + INTERRUPT_CORE0_PRO_MAC_INTR_MAP_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of MAC_INTR_MAP field. + INTERRUPT_CORE0_PRO_MAC_INTR_MAP_MAC_INTR_MAP_Msk = 0x1f + + // MAC_NMI_MAP: mac_nmi interrupt configuration register + // Position of MAC_NMI_MAP field. + INTERRUPT_CORE0_MAC_NMI_MAP_MAC_NMI_MAP_Pos = 0x0 + // Bit mask of MAC_NMI_MAP field. + INTERRUPT_CORE0_MAC_NMI_MAP_MAC_NMI_MAP_Msk = 0x1f + + // PWR_INTR_MAP: pwr interrupt configuration register + // Position of PWR_INTR_MAP field. + INTERRUPT_CORE0_PWR_INTR_MAP_PWR_INTR_MAP_Pos = 0x0 + // Bit mask of PWR_INTR_MAP field. + INTERRUPT_CORE0_PWR_INTR_MAP_PWR_INTR_MAP_Msk = 0x1f + + // BB_INT_MAP: bb interrupt configuration register + // Position of BB_INT_MAP field. + INTERRUPT_CORE0_BB_INT_MAP_BB_INT_MAP_Pos = 0x0 + // Bit mask of BB_INT_MAP field. + INTERRUPT_CORE0_BB_INT_MAP_BB_INT_MAP_Msk = 0x1f + + // BT_MAC_INT_MAP: bb_mac interrupt configuration register + // Position of BT_MAC_INT_MAP field. + INTERRUPT_CORE0_BT_MAC_INT_MAP_BT_MAC_INT_MAP_Pos = 0x0 + // Bit mask of BT_MAC_INT_MAP field. + INTERRUPT_CORE0_BT_MAC_INT_MAP_BT_MAC_INT_MAP_Msk = 0x1f + + // BT_BB_INT_MAP: bt_bb interrupt configuration register + // Position of BT_BB_INT_MAP field. + INTERRUPT_CORE0_BT_BB_INT_MAP_BT_BB_INT_MAP_Pos = 0x0 + // Bit mask of BT_BB_INT_MAP field. + INTERRUPT_CORE0_BT_BB_INT_MAP_BT_BB_INT_MAP_Msk = 0x1f + + // BT_BB_NMI_MAP: bt_bb_nmi interrupt configuration register + // Position of BT_BB_NMI_MAP field. + INTERRUPT_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Pos = 0x0 + // Bit mask of BT_BB_NMI_MAP field. + INTERRUPT_CORE0_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Msk = 0x1f + + // RWBT_IRQ_MAP: rwbt_irq interrupt configuration register + // Position of RWBT_IRQ_MAP field. + INTERRUPT_CORE0_RWBT_IRQ_MAP_RWBT_IRQ_MAP_Pos = 0x0 + // Bit mask of RWBT_IRQ_MAP field. + INTERRUPT_CORE0_RWBT_IRQ_MAP_RWBT_IRQ_MAP_Msk = 0x1f + + // RWBLE_IRQ_MAP: rwble_irq interrupt configuration register + // Position of RWBLE_IRQ_MAP field. + INTERRUPT_CORE0_RWBLE_IRQ_MAP_RWBLE_IRQ_MAP_Pos = 0x0 + // Bit mask of RWBLE_IRQ_MAP field. + INTERRUPT_CORE0_RWBLE_IRQ_MAP_RWBLE_IRQ_MAP_Msk = 0x1f + + // RWBT_NMI_MAP: rwbt_nmi interrupt configuration register + // Position of RWBT_NMI_MAP field. + INTERRUPT_CORE0_RWBT_NMI_MAP_RWBT_NMI_MAP_Pos = 0x0 + // Bit mask of RWBT_NMI_MAP field. + INTERRUPT_CORE0_RWBT_NMI_MAP_RWBT_NMI_MAP_Msk = 0x1f + + // RWBLE_NMI_MAP: rwble_nmi interrupt configuration register + // Position of RWBLE_NMI_MAP field. + INTERRUPT_CORE0_RWBLE_NMI_MAP_RWBLE_NMI_MAP_Pos = 0x0 + // Bit mask of RWBLE_NMI_MAP field. + INTERRUPT_CORE0_RWBLE_NMI_MAP_RWBLE_NMI_MAP_Msk = 0x1f + + // I2C_MST_INT_MAP: i2c_mst interrupt configuration register + // Position of I2C_MST_INT_MAP field. + INTERRUPT_CORE0_I2C_MST_INT_MAP_I2C_MST_INT_MAP_Pos = 0x0 + // Bit mask of I2C_MST_INT_MAP field. + INTERRUPT_CORE0_I2C_MST_INT_MAP_I2C_MST_INT_MAP_Msk = 0x1f + + // SLC0_INTR_MAP: slc0 interrupt configuration register + // Position of SLC0_INTR_MAP field. + INTERRUPT_CORE0_SLC0_INTR_MAP_SLC0_INTR_MAP_Pos = 0x0 + // Bit mask of SLC0_INTR_MAP field. + INTERRUPT_CORE0_SLC0_INTR_MAP_SLC0_INTR_MAP_Msk = 0x1f + + // SLC1_INTR_MAP: slc1 interrupt configuration register + // Position of SLC1_INTR_MAP field. + INTERRUPT_CORE0_SLC1_INTR_MAP_SLC1_INTR_MAP_Pos = 0x0 + // Bit mask of SLC1_INTR_MAP field. + INTERRUPT_CORE0_SLC1_INTR_MAP_SLC1_INTR_MAP_Msk = 0x1f + + // UHCI0_INTR_MAP: uhci0 interrupt configuration register + // Position of UHCI0_INTR_MAP field. + INTERRUPT_CORE0_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Pos = 0x0 + // Bit mask of UHCI0_INTR_MAP field. + INTERRUPT_CORE0_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Msk = 0x1f + + // UHCI1_INTR_MAP: uhci1 interrupt configuration register + // Position of UHCI1_INTR_MAP field. + INTERRUPT_CORE0_UHCI1_INTR_MAP_UHCI1_INTR_MAP_Pos = 0x0 + // Bit mask of UHCI1_INTR_MAP field. + INTERRUPT_CORE0_UHCI1_INTR_MAP_UHCI1_INTR_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_MAP: gpio_interrupt_pro interrupt configuration register + // Position of GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_NMI_MAP: gpio_interrupt_pro_nmi interrupt configuration register + // Position of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_APP_MAP: gpio_interrupt_app interrupt configuration register + // Position of GPIO_INTERRUPT_APP_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_GPIO_INTERRUPT_APP_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_APP_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_GPIO_INTERRUPT_APP_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_APP_NMI_MAP: gpio_interrupt_app_nmi interrupt configuration register + // Position of GPIO_INTERRUPT_APP_NMI_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_GPIO_INTERRUPT_APP_NMI_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_APP_NMI_MAP field. + INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_GPIO_INTERRUPT_APP_NMI_MAP_Msk = 0x1f + + // SPI_INTR_1_MAP: spi_intr_1 interrupt configuration register + // Position of SPI_INTR_1_MAP field. + INTERRUPT_CORE0_SPI_INTR_1_MAP_SPI_INTR_1_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_1_MAP field. + INTERRUPT_CORE0_SPI_INTR_1_MAP_SPI_INTR_1_MAP_Msk = 0x1f + + // SPI_INTR_2_MAP: spi_intr_2 interrupt configuration register + // Position of SPI_INTR_2_MAP field. + INTERRUPT_CORE0_SPI_INTR_2_MAP_SPI_INTR_2_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_2_MAP field. + INTERRUPT_CORE0_SPI_INTR_2_MAP_SPI_INTR_2_MAP_Msk = 0x1f + + // SPI_INTR_3_MAP: spi_intr_3 interrupt configuration register + // Position of SPI_INTR_3_MAP field. + INTERRUPT_CORE0_SPI_INTR_3_MAP_SPI_INTR_3_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_3_MAP field. + INTERRUPT_CORE0_SPI_INTR_3_MAP_SPI_INTR_3_MAP_Msk = 0x1f + + // SPI_INTR_4_MAP: spi_intr_4 interrupt configuration register + // Position of SPI_INTR_4_MAP field. + INTERRUPT_CORE0_SPI_INTR_4_MAP_SPI_INTR_4_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_4_MAP field. + INTERRUPT_CORE0_SPI_INTR_4_MAP_SPI_INTR_4_MAP_Msk = 0x1f + + // LCD_CAM_INT_MAP: lcd_cam interrupt configuration register + // Position of LCD_CAM_INT_MAP field. + INTERRUPT_CORE0_LCD_CAM_INT_MAP_LCD_CAM_INT_MAP_Pos = 0x0 + // Bit mask of LCD_CAM_INT_MAP field. + INTERRUPT_CORE0_LCD_CAM_INT_MAP_LCD_CAM_INT_MAP_Msk = 0x1f + + // I2S0_INT_MAP: i2s0 interrupt configuration register + // Position of I2S0_INT_MAP field. + INTERRUPT_CORE0_I2S0_INT_MAP_I2S0_INT_MAP_Pos = 0x0 + // Bit mask of I2S0_INT_MAP field. + INTERRUPT_CORE0_I2S0_INT_MAP_I2S0_INT_MAP_Msk = 0x1f + + // I2S1_INT_MAP: i2s1 interrupt configuration register + // Position of I2S1_INT_MAP field. + INTERRUPT_CORE0_I2S1_INT_MAP_I2S1_INT_MAP_Pos = 0x0 + // Bit mask of I2S1_INT_MAP field. + INTERRUPT_CORE0_I2S1_INT_MAP_I2S1_INT_MAP_Msk = 0x1f + + // UART_INTR_MAP: uart interrupt configuration register + // Position of UART_INTR_MAP field. + INTERRUPT_CORE0_UART_INTR_MAP_UART_INTR_MAP_Pos = 0x0 + // Bit mask of UART_INTR_MAP field. + INTERRUPT_CORE0_UART_INTR_MAP_UART_INTR_MAP_Msk = 0x1f + + // UART1_INTR_MAP: uart1 interrupt configuration register + // Position of UART1_INTR_MAP field. + INTERRUPT_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Pos = 0x0 + // Bit mask of UART1_INTR_MAP field. + INTERRUPT_CORE0_UART1_INTR_MAP_UART1_INTR_MAP_Msk = 0x1f + + // UART2_INTR_MAP: uart2 interrupt configuration register + // Position of UART2_INTR_MAP field. + INTERRUPT_CORE0_UART2_INTR_MAP_UART2_INTR_MAP_Pos = 0x0 + // Bit mask of UART2_INTR_MAP field. + INTERRUPT_CORE0_UART2_INTR_MAP_UART2_INTR_MAP_Msk = 0x1f + + // SDIO_HOST_INTERRUPT_MAP: sdio_host interrupt configuration register + // Position of SDIO_HOST_INTERRUPT_MAP field. + INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_SDIO_HOST_INTERRUPT_MAP_Pos = 0x0 + // Bit mask of SDIO_HOST_INTERRUPT_MAP field. + INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_SDIO_HOST_INTERRUPT_MAP_Msk = 0x1f + + // PWM0_INTR_MAP: pwm0 interrupt configuration register + // Position of PWM0_INTR_MAP field. + INTERRUPT_CORE0_PWM0_INTR_MAP_PWM0_INTR_MAP_Pos = 0x0 + // Bit mask of PWM0_INTR_MAP field. + INTERRUPT_CORE0_PWM0_INTR_MAP_PWM0_INTR_MAP_Msk = 0x1f + + // PWM1_INTR_MAP: pwm1 interrupt configuration register + // Position of PWM1_INTR_MAP field. + INTERRUPT_CORE0_PWM1_INTR_MAP_PWM1_INTR_MAP_Pos = 0x0 + // Bit mask of PWM1_INTR_MAP field. + INTERRUPT_CORE0_PWM1_INTR_MAP_PWM1_INTR_MAP_Msk = 0x1f + + // PWM2_INTR_MAP: pwm2 interrupt configuration register + // Position of PWM2_INTR_MAP field. + INTERRUPT_CORE0_PWM2_INTR_MAP_PWM2_INTR_MAP_Pos = 0x0 + // Bit mask of PWM2_INTR_MAP field. + INTERRUPT_CORE0_PWM2_INTR_MAP_PWM2_INTR_MAP_Msk = 0x1f + + // PWM3_INTR_MAP: pwm3 interrupt configuration register + // Position of PWM3_INTR_MAP field. + INTERRUPT_CORE0_PWM3_INTR_MAP_PWM3_INTR_MAP_Pos = 0x0 + // Bit mask of PWM3_INTR_MAP field. + INTERRUPT_CORE0_PWM3_INTR_MAP_PWM3_INTR_MAP_Msk = 0x1f + + // LEDC_INT_MAP: ledc interrupt configuration register + // Position of LEDC_INT_MAP field. + INTERRUPT_CORE0_LEDC_INT_MAP_LEDC_INT_MAP_Pos = 0x0 + // Bit mask of LEDC_INT_MAP field. + INTERRUPT_CORE0_LEDC_INT_MAP_LEDC_INT_MAP_Msk = 0x1f + + // EFUSE_INT_MAP: efuse interrupt configuration register + // Position of EFUSE_INT_MAP field. + INTERRUPT_CORE0_EFUSE_INT_MAP_EFUSE_INT_MAP_Pos = 0x0 + // Bit mask of EFUSE_INT_MAP field. + INTERRUPT_CORE0_EFUSE_INT_MAP_EFUSE_INT_MAP_Msk = 0x1f + + // CAN_INT_MAP: can interrupt configuration register + // Position of CAN_INT_MAP field. + INTERRUPT_CORE0_CAN_INT_MAP_CAN_INT_MAP_Pos = 0x0 + // Bit mask of CAN_INT_MAP field. + INTERRUPT_CORE0_CAN_INT_MAP_CAN_INT_MAP_Msk = 0x1f + + // USB_INTR_MAP: usb interrupt configuration register + // Position of USB_INTR_MAP field. + INTERRUPT_CORE0_USB_INTR_MAP_USB_INTR_MAP_Pos = 0x0 + // Bit mask of USB_INTR_MAP field. + INTERRUPT_CORE0_USB_INTR_MAP_USB_INTR_MAP_Msk = 0x1f + + // RTC_CORE_INTR_MAP: rtc_core interrupt configuration register + // Position of RTC_CORE_INTR_MAP field. + INTERRUPT_CORE0_RTC_CORE_INTR_MAP_RTC_CORE_INTR_MAP_Pos = 0x0 + // Bit mask of RTC_CORE_INTR_MAP field. + INTERRUPT_CORE0_RTC_CORE_INTR_MAP_RTC_CORE_INTR_MAP_Msk = 0x1f + + // RMT_INTR_MAP: rmt interrupt configuration register + // Position of RMT_INTR_MAP field. + INTERRUPT_CORE0_RMT_INTR_MAP_RMT_INTR_MAP_Pos = 0x0 + // Bit mask of RMT_INTR_MAP field. + INTERRUPT_CORE0_RMT_INTR_MAP_RMT_INTR_MAP_Msk = 0x1f + + // PCNT_INTR_MAP: pcnt interrupt configuration register + // Position of PCNT_INTR_MAP field. + INTERRUPT_CORE0_PCNT_INTR_MAP_PCNT_INTR_MAP_Pos = 0x0 + // Bit mask of PCNT_INTR_MAP field. + INTERRUPT_CORE0_PCNT_INTR_MAP_PCNT_INTR_MAP_Msk = 0x1f + + // I2C_EXT0_INTR_MAP: i2c_ext0 interrupt configuration register + // Position of I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Msk = 0x1f + + // I2C_EXT1_INTR_MAP: i2c_ext1 interrupt configuration register + // Position of I2C_EXT1_INTR_MAP field. + INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_I2C_EXT1_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_EXT1_INTR_MAP field. + INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_I2C_EXT1_INTR_MAP_Msk = 0x1f + + // SPI2_DMA_INT_MAP: spi2_dma interrupt configuration register + // Position of SPI2_DMA_INT_MAP field. + INTERRUPT_CORE0_SPI2_DMA_INT_MAP_SPI2_DMA_INT_MAP_Pos = 0x0 + // Bit mask of SPI2_DMA_INT_MAP field. + INTERRUPT_CORE0_SPI2_DMA_INT_MAP_SPI2_DMA_INT_MAP_Msk = 0x1f + + // SPI3_DMA_INT_MAP: spi3_dma interrupt configuration register + // Position of SPI3_DMA_INT_MAP field. + INTERRUPT_CORE0_SPI3_DMA_INT_MAP_SPI3_DMA_INT_MAP_Pos = 0x0 + // Bit mask of SPI3_DMA_INT_MAP field. + INTERRUPT_CORE0_SPI3_DMA_INT_MAP_SPI3_DMA_INT_MAP_Msk = 0x1f + + // SPI4_DMA_INT_MAP: spi4_dma interrupt configuration register + // Position of SPI4_DMA_INT_MAP field. + INTERRUPT_CORE0_SPI4_DMA_INT_MAP_SPI4_DMA_INT_MAP_Pos = 0x0 + // Bit mask of SPI4_DMA_INT_MAP field. + INTERRUPT_CORE0_SPI4_DMA_INT_MAP_SPI4_DMA_INT_MAP_Msk = 0x1f + + // WDG_INT_MAP: wdg interrupt configuration register + // Position of WDG_INT_MAP field. + INTERRUPT_CORE0_WDG_INT_MAP_WDG_INT_MAP_Pos = 0x0 + // Bit mask of WDG_INT_MAP field. + INTERRUPT_CORE0_WDG_INT_MAP_WDG_INT_MAP_Msk = 0x1f + + // TIMER_INT1_MAP: timer_int1 interrupt configuration register + // Position of TIMER_INT1_MAP field. + INTERRUPT_CORE0_TIMER_INT1_MAP_TIMER_INT1_MAP_Pos = 0x0 + // Bit mask of TIMER_INT1_MAP field. + INTERRUPT_CORE0_TIMER_INT1_MAP_TIMER_INT1_MAP_Msk = 0x1f + + // TIMER_INT2_MAP: timer_int2 interrupt configuration register + // Position of TIMER_INT2_MAP field. + INTERRUPT_CORE0_TIMER_INT2_MAP_TIMER_INT2_MAP_Pos = 0x0 + // Bit mask of TIMER_INT2_MAP field. + INTERRUPT_CORE0_TIMER_INT2_MAP_TIMER_INT2_MAP_Msk = 0x1f + + // TG_T0_INT_MAP: tg_t0 interrupt configuration register + // Position of TG_T0_INT_MAP field. + INTERRUPT_CORE0_TG_T0_INT_MAP_TG_T0_INT_MAP_Pos = 0x0 + // Bit mask of TG_T0_INT_MAP field. + INTERRUPT_CORE0_TG_T0_INT_MAP_TG_T0_INT_MAP_Msk = 0x1f + + // TG_T1_INT_MAP: tg_t1 interrupt configuration register + // Position of TG_T1_INT_MAP field. + INTERRUPT_CORE0_TG_T1_INT_MAP_TG_T1_INT_MAP_Pos = 0x0 + // Bit mask of TG_T1_INT_MAP field. + INTERRUPT_CORE0_TG_T1_INT_MAP_TG_T1_INT_MAP_Msk = 0x1f + + // TG_WDT_INT_MAP: tg_wdt interrupt configuration register + // Position of TG_WDT_INT_MAP field. + INTERRUPT_CORE0_TG_WDT_INT_MAP_TG_WDT_INT_MAP_Pos = 0x0 + // Bit mask of TG_WDT_INT_MAP field. + INTERRUPT_CORE0_TG_WDT_INT_MAP_TG_WDT_INT_MAP_Msk = 0x1f + + // TG1_T0_INT_MAP: tg1_t0 interrupt configuration register + // Position of TG1_T0_INT_MAP field. + INTERRUPT_CORE0_TG1_T0_INT_MAP_TG1_T0_INT_MAP_Pos = 0x0 + // Bit mask of TG1_T0_INT_MAP field. + INTERRUPT_CORE0_TG1_T0_INT_MAP_TG1_T0_INT_MAP_Msk = 0x1f + + // TG1_T1_INT_MAP: tg1_t1 interrupt configuration register + // Position of TG1_T1_INT_MAP field. + INTERRUPT_CORE0_TG1_T1_INT_MAP_TG1_T1_INT_MAP_Pos = 0x0 + // Bit mask of TG1_T1_INT_MAP field. + INTERRUPT_CORE0_TG1_T1_INT_MAP_TG1_T1_INT_MAP_Msk = 0x1f + + // TG1_WDT_INT_MAP: tg1_wdt interrupt configuration register + // Position of TG1_WDT_INT_MAP field. + INTERRUPT_CORE0_TG1_WDT_INT_MAP_TG1_WDT_INT_MAP_Pos = 0x0 + // Bit mask of TG1_WDT_INT_MAP field. + INTERRUPT_CORE0_TG1_WDT_INT_MAP_TG1_WDT_INT_MAP_Msk = 0x1f + + // CACHE_IA_INT_MAP: cache_ia interrupt configuration register + // Position of CACHE_IA_INT_MAP field. + INTERRUPT_CORE0_CACHE_IA_INT_MAP_CACHE_IA_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_IA_INT_MAP field. + INTERRUPT_CORE0_CACHE_IA_INT_MAP_CACHE_IA_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET0_INT_MAP: systimer_target0 interrupt configuration register + // Position of SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_SYSTIMER_TARGET0_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_SYSTIMER_TARGET0_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET1_INT_MAP: systimer_target1 interrupt configuration register + // Position of SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_SYSTIMER_TARGET1_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_SYSTIMER_TARGET1_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET2_INT_MAP: systimer_target2 interrupt configuration register + // Position of SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_SYSTIMER_TARGET2_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_SYSTIMER_TARGET2_INT_MAP_Msk = 0x1f + + // SPI_MEM_REJECT_INTR_MAP: spi_mem_reject interrupt configuration register + // Position of SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_SPI_MEM_REJECT_INTR_MAP_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_SPI_MEM_REJECT_INTR_MAP_Msk = 0x1f + + // DCACHE_PRELOAD_INT_MAP: dcache_prelaod interrupt configuration register + // Position of DCACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_DCACHE_PRELOAD_INT_MAP_Pos = 0x0 + // Bit mask of DCACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_DCACHE_PRELOAD_INT_MAP_Msk = 0x1f + + // ICACHE_PRELOAD_INT_MAP: icache_preload interrupt configuration register + // Position of ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_ICACHE_PRELOAD_INT_MAP_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_ICACHE_PRELOAD_INT_MAP_Msk = 0x1f + + // DCACHE_SYNC_INT_MAP: dcache_sync interrupt configuration register + // Position of DCACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_DCACHE_SYNC_INT_MAP_Pos = 0x0 + // Bit mask of DCACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_DCACHE_SYNC_INT_MAP_Msk = 0x1f + + // ICACHE_SYNC_INT_MAP: icache_sync interrupt configuration register + // Position of ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_ICACHE_SYNC_INT_MAP_Pos = 0x0 + // Bit mask of ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_ICACHE_SYNC_INT_MAP_Msk = 0x1f + + // APB_ADC_INT_MAP: apb_adc interrupt configuration register + // Position of APB_ADC_INT_MAP field. + INTERRUPT_CORE0_APB_ADC_INT_MAP_APB_ADC_INT_MAP_Pos = 0x0 + // Bit mask of APB_ADC_INT_MAP field. + INTERRUPT_CORE0_APB_ADC_INT_MAP_APB_ADC_INT_MAP_Msk = 0x1f + + // DMA_IN_CH0_INT_MAP: dma_in_ch0 interrupt configuration register + // Position of DMA_IN_CH0_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_DMA_IN_CH0_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH0_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_DMA_IN_CH0_INT_MAP_Msk = 0x1f + + // DMA_IN_CH1_INT_MAP: dma_in_ch1 interrupt configuration register + // Position of DMA_IN_CH1_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_DMA_IN_CH1_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH1_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_DMA_IN_CH1_INT_MAP_Msk = 0x1f + + // DMA_IN_CH2_INT_MAP: dma_in_ch2 interrupt configuration register + // Position of DMA_IN_CH2_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_DMA_IN_CH2_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH2_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_DMA_IN_CH2_INT_MAP_Msk = 0x1f + + // DMA_IN_CH3_INT_MAP: dma_in_ch3 interrupt configuration register + // Position of DMA_IN_CH3_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_DMA_IN_CH3_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH3_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_DMA_IN_CH3_INT_MAP_Msk = 0x1f + + // DMA_IN_CH4_INT_MAP: dma_in_ch4 interrupt configuration register + // Position of DMA_IN_CH4_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_DMA_IN_CH4_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH4_INT_MAP field. + INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_DMA_IN_CH4_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH0_INT_MAP: dma_out_ch0 interrupt configuration register + // Position of DMA_OUT_CH0_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_DMA_OUT_CH0_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH0_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_DMA_OUT_CH0_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH1_INT_MAP: dma_out_ch1 interrupt configuration register + // Position of DMA_OUT_CH1_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_DMA_OUT_CH1_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH1_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_DMA_OUT_CH1_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH2_INT_MAP: dma_out_ch2 interrupt configuration register + // Position of DMA_OUT_CH2_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_DMA_OUT_CH2_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH2_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_DMA_OUT_CH2_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH3_INT_MAP: dma_out_ch3 interrupt configuration register + // Position of DMA_OUT_CH3_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_DMA_OUT_CH3_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH3_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_DMA_OUT_CH3_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH4_INT_MAP: dma_out_ch4 interrupt configuration register + // Position of DMA_OUT_CH4_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_DMA_OUT_CH4_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH4_INT_MAP field. + INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_DMA_OUT_CH4_INT_MAP_Msk = 0x1f + + // RSA_INT_MAP: rsa interrupt configuration register + // Position of RSA_INT_MAP field. + INTERRUPT_CORE0_RSA_INT_MAP_RSA_INT_MAP_Pos = 0x0 + // Bit mask of RSA_INT_MAP field. + INTERRUPT_CORE0_RSA_INT_MAP_RSA_INT_MAP_Msk = 0x1f + + // AES_INT_MAP: aes interrupt configuration register + // Position of AES_INT_MAP field. + INTERRUPT_CORE0_AES_INT_MAP_AES_INT_MAP_Pos = 0x0 + // Bit mask of AES_INT_MAP field. + INTERRUPT_CORE0_AES_INT_MAP_AES_INT_MAP_Msk = 0x1f + + // SHA_INT_MAP: sha interrupt configuration register + // Position of SHA_INT_MAP field. + INTERRUPT_CORE0_SHA_INT_MAP_SHA_INT_MAP_Pos = 0x0 + // Bit mask of SHA_INT_MAP field. + INTERRUPT_CORE0_SHA_INT_MAP_SHA_INT_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_0_MAP: cpu_intr_from_cpu_0 interrupt configuration register + // Position of CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_1_MAP: cpu_intr_from_cpu_1 interrupt configuration register + // Position of CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_2_MAP: cpu_intr_from_cpu_2 interrupt configuration register + // Position of CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_3_MAP: cpu_intr_from_cpu_3 interrupt configuration register + // Position of CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Msk = 0x1f + + // ASSIST_DEBUG_INTR_MAP: assist_debug interrupt configuration register + // Position of ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Pos = 0x0 + // Bit mask of ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Msk = 0x1f + + // DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: dma_pms_monitor_violatile interrupt configuration register + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core0_IRam0_pms_monitor_violatile interrupt configuration register + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core0_DRam0_pms_monitor_violatile interrupt configuration register + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: core0_PIF_pms_monitor_violatile interrupt configuration register + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: core0_PIF_pms_monitor_violatile_size interrupt configuration register + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Msk = 0x1f + + // CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core1_IRam0_pms_monitor_violatile interrupt configuration register + // Position of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core1_DRam0_pms_monitor_violatile interrupt configuration register + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: core1_PIF_pms_monitor_violatile interrupt configuration register + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: core1_PIF_pms_monitor_violatile_size interrupt configuration register + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Msk = 0x1f + + // BACKUP_PMS_VIOLATE_INTR_MAP: backup_pms_monitor_violatile interrupt configuration register + // Position of BACKUP_PMS_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_BACKUP_PMS_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of BACKUP_PMS_VIOLATE_INTR_MAP field. + INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_BACKUP_PMS_VIOLATE_INTR_MAP_Msk = 0x1f + + // CACHE_CORE0_ACS_INT_MAP: cache_core0_acs interrupt configuration register + // Position of CACHE_CORE0_ACS_INT_MAP field. + INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_CACHE_CORE0_ACS_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_CORE0_ACS_INT_MAP field. + INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_CACHE_CORE0_ACS_INT_MAP_Msk = 0x1f + + // CACHE_CORE1_ACS_INT_MAP: cache_core1_acs interrupt configuration register + // Position of CACHE_CORE1_ACS_INT_MAP field. + INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_CACHE_CORE1_ACS_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_CORE1_ACS_INT_MAP field. + INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_CACHE_CORE1_ACS_INT_MAP_Msk = 0x1f + + // USB_DEVICE_INT_MAP: usb_device interrupt configuration register + // Position of USB_DEVICE_INT_MAP field. + INTERRUPT_CORE0_USB_DEVICE_INT_MAP_USB_DEVICE_INT_MAP_Pos = 0x0 + // Bit mask of USB_DEVICE_INT_MAP field. + INTERRUPT_CORE0_USB_DEVICE_INT_MAP_USB_DEVICE_INT_MAP_Msk = 0x1f + + // PERI_BACKUP_INT_MAP: peri_backup interrupt configuration register + // Position of PERI_BACKUP_INT_MAP field. + INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_PERI_BACKUP_INT_MAP_Pos = 0x0 + // Bit mask of PERI_BACKUP_INT_MAP field. + INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_PERI_BACKUP_INT_MAP_Msk = 0x1f + + // DMA_EXTMEM_REJECT_INT_MAP: dma_extmem_reject interrupt configuration register + // Position of DMA_EXTMEM_REJECT_INT_MAP field. + INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_DMA_EXTMEM_REJECT_INT_MAP_Pos = 0x0 + // Bit mask of DMA_EXTMEM_REJECT_INT_MAP field. + INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_DMA_EXTMEM_REJECT_INT_MAP_Msk = 0x1f + + // PRO_INTR_STATUS_0: interrupt status register + // Position of INTR_STATUS_0 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_0_INTR_STATUS_0_Pos = 0x0 + // Bit mask of INTR_STATUS_0 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_0_INTR_STATUS_0_Msk = 0xffffffff + + // PRO_INTR_STATUS_1: interrupt status register + // Position of INTR_STATUS_1 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_1_INTR_STATUS_1_Pos = 0x0 + // Bit mask of INTR_STATUS_1 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_1_INTR_STATUS_1_Msk = 0xffffffff + + // PRO_INTR_STATUS_2: interrupt status register + // Position of INTR_STATUS_2 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_2_INTR_STATUS_2_Pos = 0x0 + // Bit mask of INTR_STATUS_2 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_2_INTR_STATUS_2_Msk = 0xffffffff + + // PRO_INTR_STATUS_3: interrupt status register + // Position of INTR_STATUS_3 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_3_INTR_STATUS_3_Pos = 0x0 + // Bit mask of INTR_STATUS_3 field. + INTERRUPT_CORE0_PRO_INTR_STATUS_3_INTR_STATUS_3_Msk = 0xffffffff + + // CLOCK_GATE: clock gate register + // Position of REG_CLK_EN field. + INTERRUPT_CORE0_CLOCK_GATE_REG_CLK_EN_Pos = 0x0 + // Bit mask of REG_CLK_EN field. + INTERRUPT_CORE0_CLOCK_GATE_REG_CLK_EN_Msk = 0x1 + // Bit REG_CLK_EN. + INTERRUPT_CORE0_CLOCK_GATE_REG_CLK_EN = 0x1 + + // DATE: version register + // Position of INTERRUPT_REG_DATE field. + INTERRUPT_CORE0_DATE_INTERRUPT_REG_DATE_Pos = 0x0 + // Bit mask of INTERRUPT_REG_DATE field. + INTERRUPT_CORE0_DATE_INTERRUPT_REG_DATE_Msk = 0xfffffff +) + +// Constants for INTERRUPT_CORE1: Interrupt Controller (Core 1) +const ( + // APP_MAC_INTR_MAP: mac interrupt configuration register + // Position of MAC_INTR_MAP field. + INTERRUPT_CORE1_APP_MAC_INTR_MAP_MAC_INTR_MAP_Pos = 0x0 + // Bit mask of MAC_INTR_MAP field. + INTERRUPT_CORE1_APP_MAC_INTR_MAP_MAC_INTR_MAP_Msk = 0x1f + + // MAC_NMI_MAP: mac_nmi interrupt configuration register + // Position of MAC_NMI_MAP field. + INTERRUPT_CORE1_MAC_NMI_MAP_MAC_NMI_MAP_Pos = 0x0 + // Bit mask of MAC_NMI_MAP field. + INTERRUPT_CORE1_MAC_NMI_MAP_MAC_NMI_MAP_Msk = 0x1f + + // PWR_INTR_MAP: pwr interrupt configuration register + // Position of PWR_INTR_MAP field. + INTERRUPT_CORE1_PWR_INTR_MAP_PWR_INTR_MAP_Pos = 0x0 + // Bit mask of PWR_INTR_MAP field. + INTERRUPT_CORE1_PWR_INTR_MAP_PWR_INTR_MAP_Msk = 0x1f + + // BB_INT_MAP: bb interrupt configuration register + // Position of BB_INT_MAP field. + INTERRUPT_CORE1_BB_INT_MAP_BB_INT_MAP_Pos = 0x0 + // Bit mask of BB_INT_MAP field. + INTERRUPT_CORE1_BB_INT_MAP_BB_INT_MAP_Msk = 0x1f + + // BT_MAC_INT_MAP: bb_mac interrupt configuration register + // Position of BT_MAC_INT_MAP field. + INTERRUPT_CORE1_BT_MAC_INT_MAP_BT_MAC_INT_MAP_Pos = 0x0 + // Bit mask of BT_MAC_INT_MAP field. + INTERRUPT_CORE1_BT_MAC_INT_MAP_BT_MAC_INT_MAP_Msk = 0x1f + + // BT_BB_INT_MAP: bt_bb interrupt configuration register + // Position of BT_BB_INT_MAP field. + INTERRUPT_CORE1_BT_BB_INT_MAP_BT_BB_INT_MAP_Pos = 0x0 + // Bit mask of BT_BB_INT_MAP field. + INTERRUPT_CORE1_BT_BB_INT_MAP_BT_BB_INT_MAP_Msk = 0x1f + + // BT_BB_NMI_MAP: bt_bb_nmi interrupt configuration register + // Position of BT_BB_NMI_MAP field. + INTERRUPT_CORE1_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Pos = 0x0 + // Bit mask of BT_BB_NMI_MAP field. + INTERRUPT_CORE1_BT_BB_NMI_MAP_BT_BB_NMI_MAP_Msk = 0x1f + + // RWBT_IRQ_MAP: rwbt_irq interrupt configuration register + // Position of RWBT_IRQ_MAP field. + INTERRUPT_CORE1_RWBT_IRQ_MAP_RWBT_IRQ_MAP_Pos = 0x0 + // Bit mask of RWBT_IRQ_MAP field. + INTERRUPT_CORE1_RWBT_IRQ_MAP_RWBT_IRQ_MAP_Msk = 0x1f + + // RWBLE_IRQ_MAP: rwble_irq interrupt configuration register + // Position of RWBLE_IRQ_MAP field. + INTERRUPT_CORE1_RWBLE_IRQ_MAP_RWBLE_IRQ_MAP_Pos = 0x0 + // Bit mask of RWBLE_IRQ_MAP field. + INTERRUPT_CORE1_RWBLE_IRQ_MAP_RWBLE_IRQ_MAP_Msk = 0x1f + + // RWBT_NMI_MAP: rwbt_nmi interrupt configuration register + // Position of RWBT_NMI_MAP field. + INTERRUPT_CORE1_RWBT_NMI_MAP_RWBT_NMI_MAP_Pos = 0x0 + // Bit mask of RWBT_NMI_MAP field. + INTERRUPT_CORE1_RWBT_NMI_MAP_RWBT_NMI_MAP_Msk = 0x1f + + // RWBLE_NMI_MAP: rwble_nmi interrupt configuration register + // Position of RWBLE_NMI_MAP field. + INTERRUPT_CORE1_RWBLE_NMI_MAP_RWBLE_NMI_MAP_Pos = 0x0 + // Bit mask of RWBLE_NMI_MAP field. + INTERRUPT_CORE1_RWBLE_NMI_MAP_RWBLE_NMI_MAP_Msk = 0x1f + + // I2C_MST_INT_MAP: i2c_mst interrupt configuration register + // Position of I2C_MST_INT_MAP field. + INTERRUPT_CORE1_I2C_MST_INT_MAP_I2C_MST_INT_MAP_Pos = 0x0 + // Bit mask of I2C_MST_INT_MAP field. + INTERRUPT_CORE1_I2C_MST_INT_MAP_I2C_MST_INT_MAP_Msk = 0x1f + + // SLC0_INTR_MAP: slc0 interrupt configuration register + // Position of SLC0_INTR_MAP field. + INTERRUPT_CORE1_SLC0_INTR_MAP_SLC0_INTR_MAP_Pos = 0x0 + // Bit mask of SLC0_INTR_MAP field. + INTERRUPT_CORE1_SLC0_INTR_MAP_SLC0_INTR_MAP_Msk = 0x1f + + // SLC1_INTR_MAP: slc1 interrupt configuration register + // Position of SLC1_INTR_MAP field. + INTERRUPT_CORE1_SLC1_INTR_MAP_SLC1_INTR_MAP_Pos = 0x0 + // Bit mask of SLC1_INTR_MAP field. + INTERRUPT_CORE1_SLC1_INTR_MAP_SLC1_INTR_MAP_Msk = 0x1f + + // UHCI0_INTR_MAP: uhci0 interrupt configuration register + // Position of UHCI0_INTR_MAP field. + INTERRUPT_CORE1_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Pos = 0x0 + // Bit mask of UHCI0_INTR_MAP field. + INTERRUPT_CORE1_UHCI0_INTR_MAP_UHCI0_INTR_MAP_Msk = 0x1f + + // UHCI1_INTR_MAP: uhci1 interrupt configuration register + // Position of UHCI1_INTR_MAP field. + INTERRUPT_CORE1_UHCI1_INTR_MAP_UHCI1_INTR_MAP_Pos = 0x0 + // Bit mask of UHCI1_INTR_MAP field. + INTERRUPT_CORE1_UHCI1_INTR_MAP_UHCI1_INTR_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_MAP: gpio_interrupt_pro interrupt configuration register + // Position of GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_MAP field. + INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_GPIO_INTERRUPT_PRO_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_PRO_NMI_MAP: gpio_interrupt_pro_nmi interrupt configuration register + // Position of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_PRO_NMI_MAP field. + INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_GPIO_INTERRUPT_PRO_NMI_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_APP_MAP: gpio_interrupt_app interrupt configuration register + // Position of GPIO_INTERRUPT_APP_MAP field. + INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_GPIO_INTERRUPT_APP_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_APP_MAP field. + INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_GPIO_INTERRUPT_APP_MAP_Msk = 0x1f + + // GPIO_INTERRUPT_APP_NMI_MAP: gpio_interrupt_app_nmi interrupt configuration register + // Position of GPIO_INTERRUPT_APP_NMI_MAP field. + INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_GPIO_INTERRUPT_APP_NMI_MAP_Pos = 0x0 + // Bit mask of GPIO_INTERRUPT_APP_NMI_MAP field. + INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_GPIO_INTERRUPT_APP_NMI_MAP_Msk = 0x1f + + // SPI_INTR_1_MAP: spi_intr_1 interrupt configuration register + // Position of SPI_INTR_1_MAP field. + INTERRUPT_CORE1_SPI_INTR_1_MAP_SPI_INTR_1_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_1_MAP field. + INTERRUPT_CORE1_SPI_INTR_1_MAP_SPI_INTR_1_MAP_Msk = 0x1f + + // SPI_INTR_2_MAP: spi_intr_2 interrupt configuration register + // Position of SPI_INTR_2_MAP field. + INTERRUPT_CORE1_SPI_INTR_2_MAP_SPI_INTR_2_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_2_MAP field. + INTERRUPT_CORE1_SPI_INTR_2_MAP_SPI_INTR_2_MAP_Msk = 0x1f + + // SPI_INTR_3_MAP: spi_intr_3 interrupt configuration register + // Position of SPI_INTR_3_MAP field. + INTERRUPT_CORE1_SPI_INTR_3_MAP_SPI_INTR_3_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_3_MAP field. + INTERRUPT_CORE1_SPI_INTR_3_MAP_SPI_INTR_3_MAP_Msk = 0x1f + + // SPI_INTR_4_MAP: spi_intr_4 interrupt configuration register + // Position of SPI_INTR_4_MAP field. + INTERRUPT_CORE1_SPI_INTR_4_MAP_SPI_INTR_4_MAP_Pos = 0x0 + // Bit mask of SPI_INTR_4_MAP field. + INTERRUPT_CORE1_SPI_INTR_4_MAP_SPI_INTR_4_MAP_Msk = 0x1f + + // LCD_CAM_INT_MAP: lcd_cam interrupt configuration register + // Position of LCD_CAM_INT_MAP field. + INTERRUPT_CORE1_LCD_CAM_INT_MAP_LCD_CAM_INT_MAP_Pos = 0x0 + // Bit mask of LCD_CAM_INT_MAP field. + INTERRUPT_CORE1_LCD_CAM_INT_MAP_LCD_CAM_INT_MAP_Msk = 0x1f + + // I2S0_INT_MAP: i2s0 interrupt configuration register + // Position of I2S0_INT_MAP field. + INTERRUPT_CORE1_I2S0_INT_MAP_I2S0_INT_MAP_Pos = 0x0 + // Bit mask of I2S0_INT_MAP field. + INTERRUPT_CORE1_I2S0_INT_MAP_I2S0_INT_MAP_Msk = 0x1f + + // I2S1_INT_MAP: i2s1 interrupt configuration register + // Position of I2S1_INT_MAP field. + INTERRUPT_CORE1_I2S1_INT_MAP_I2S1_INT_MAP_Pos = 0x0 + // Bit mask of I2S1_INT_MAP field. + INTERRUPT_CORE1_I2S1_INT_MAP_I2S1_INT_MAP_Msk = 0x1f + + // UART_INTR_MAP: uart interrupt configuration register + // Position of UART_INTR_MAP field. + INTERRUPT_CORE1_UART_INTR_MAP_UART_INTR_MAP_Pos = 0x0 + // Bit mask of UART_INTR_MAP field. + INTERRUPT_CORE1_UART_INTR_MAP_UART_INTR_MAP_Msk = 0x1f + + // UART1_INTR_MAP: uart1 interrupt configuration register + // Position of UART1_INTR_MAP field. + INTERRUPT_CORE1_UART1_INTR_MAP_UART1_INTR_MAP_Pos = 0x0 + // Bit mask of UART1_INTR_MAP field. + INTERRUPT_CORE1_UART1_INTR_MAP_UART1_INTR_MAP_Msk = 0x1f + + // UART2_INTR_MAP: uart2 interrupt configuration register + // Position of UART2_INTR_MAP field. + INTERRUPT_CORE1_UART2_INTR_MAP_UART2_INTR_MAP_Pos = 0x0 + // Bit mask of UART2_INTR_MAP field. + INTERRUPT_CORE1_UART2_INTR_MAP_UART2_INTR_MAP_Msk = 0x1f + + // SDIO_HOST_INTERRUPT_MAP: sdio_host interrupt configuration register + // Position of SDIO_HOST_INTERRUPT_MAP field. + INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_SDIO_HOST_INTERRUPT_MAP_Pos = 0x0 + // Bit mask of SDIO_HOST_INTERRUPT_MAP field. + INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_SDIO_HOST_INTERRUPT_MAP_Msk = 0x1f + + // PWM0_INTR_MAP: pwm0 interrupt configuration register + // Position of PWM0_INTR_MAP field. + INTERRUPT_CORE1_PWM0_INTR_MAP_PWM0_INTR_MAP_Pos = 0x0 + // Bit mask of PWM0_INTR_MAP field. + INTERRUPT_CORE1_PWM0_INTR_MAP_PWM0_INTR_MAP_Msk = 0x1f + + // PWM1_INTR_MAP: pwm1 interrupt configuration register + // Position of PWM1_INTR_MAP field. + INTERRUPT_CORE1_PWM1_INTR_MAP_PWM1_INTR_MAP_Pos = 0x0 + // Bit mask of PWM1_INTR_MAP field. + INTERRUPT_CORE1_PWM1_INTR_MAP_PWM1_INTR_MAP_Msk = 0x1f + + // PWM2_INTR_MAP: pwm2 interrupt configuration register + // Position of PWM2_INTR_MAP field. + INTERRUPT_CORE1_PWM2_INTR_MAP_PWM2_INTR_MAP_Pos = 0x0 + // Bit mask of PWM2_INTR_MAP field. + INTERRUPT_CORE1_PWM2_INTR_MAP_PWM2_INTR_MAP_Msk = 0x1f + + // PWM3_INTR_MAP: pwm3 interrupt configuration register + // Position of PWM3_INTR_MAP field. + INTERRUPT_CORE1_PWM3_INTR_MAP_PWM3_INTR_MAP_Pos = 0x0 + // Bit mask of PWM3_INTR_MAP field. + INTERRUPT_CORE1_PWM3_INTR_MAP_PWM3_INTR_MAP_Msk = 0x1f + + // LEDC_INT_MAP: ledc interrupt configuration register + // Position of LEDC_INT_MAP field. + INTERRUPT_CORE1_LEDC_INT_MAP_LEDC_INT_MAP_Pos = 0x0 + // Bit mask of LEDC_INT_MAP field. + INTERRUPT_CORE1_LEDC_INT_MAP_LEDC_INT_MAP_Msk = 0x1f + + // EFUSE_INT_MAP: efuse interrupt configuration register + // Position of EFUSE_INT_MAP field. + INTERRUPT_CORE1_EFUSE_INT_MAP_EFUSE_INT_MAP_Pos = 0x0 + // Bit mask of EFUSE_INT_MAP field. + INTERRUPT_CORE1_EFUSE_INT_MAP_EFUSE_INT_MAP_Msk = 0x1f + + // CAN_INT_MAP: can interrupt configuration register + // Position of CAN_INT_MAP field. + INTERRUPT_CORE1_CAN_INT_MAP_CAN_INT_MAP_Pos = 0x0 + // Bit mask of CAN_INT_MAP field. + INTERRUPT_CORE1_CAN_INT_MAP_CAN_INT_MAP_Msk = 0x1f + + // USB_INTR_MAP: usb interrupt configuration register + // Position of USB_INTR_MAP field. + INTERRUPT_CORE1_USB_INTR_MAP_USB_INTR_MAP_Pos = 0x0 + // Bit mask of USB_INTR_MAP field. + INTERRUPT_CORE1_USB_INTR_MAP_USB_INTR_MAP_Msk = 0x1f + + // RTC_CORE_INTR_MAP: rtc_core interrupt configuration register + // Position of RTC_CORE_INTR_MAP field. + INTERRUPT_CORE1_RTC_CORE_INTR_MAP_RTC_CORE_INTR_MAP_Pos = 0x0 + // Bit mask of RTC_CORE_INTR_MAP field. + INTERRUPT_CORE1_RTC_CORE_INTR_MAP_RTC_CORE_INTR_MAP_Msk = 0x1f + + // RMT_INTR_MAP: rmt interrupt configuration register + // Position of RMT_INTR_MAP field. + INTERRUPT_CORE1_RMT_INTR_MAP_RMT_INTR_MAP_Pos = 0x0 + // Bit mask of RMT_INTR_MAP field. + INTERRUPT_CORE1_RMT_INTR_MAP_RMT_INTR_MAP_Msk = 0x1f + + // PCNT_INTR_MAP: pcnt interrupt configuration register + // Position of PCNT_INTR_MAP field. + INTERRUPT_CORE1_PCNT_INTR_MAP_PCNT_INTR_MAP_Pos = 0x0 + // Bit mask of PCNT_INTR_MAP field. + INTERRUPT_CORE1_PCNT_INTR_MAP_PCNT_INTR_MAP_Msk = 0x1f + + // I2C_EXT0_INTR_MAP: i2c_ext0 interrupt configuration register + // Position of I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_EXT0_INTR_MAP field. + INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_I2C_EXT0_INTR_MAP_Msk = 0x1f + + // I2C_EXT1_INTR_MAP: i2c_ext1 interrupt configuration register + // Position of I2C_EXT1_INTR_MAP field. + INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_I2C_EXT1_INTR_MAP_Pos = 0x0 + // Bit mask of I2C_EXT1_INTR_MAP field. + INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_I2C_EXT1_INTR_MAP_Msk = 0x1f + + // SPI2_DMA_INT_MAP: spi2_dma interrupt configuration register + // Position of SPI2_DMA_INT_MAP field. + INTERRUPT_CORE1_SPI2_DMA_INT_MAP_SPI2_DMA_INT_MAP_Pos = 0x0 + // Bit mask of SPI2_DMA_INT_MAP field. + INTERRUPT_CORE1_SPI2_DMA_INT_MAP_SPI2_DMA_INT_MAP_Msk = 0x1f + + // SPI3_DMA_INT_MAP: spi3_dma interrupt configuration register + // Position of SPI3_DMA_INT_MAP field. + INTERRUPT_CORE1_SPI3_DMA_INT_MAP_SPI3_DMA_INT_MAP_Pos = 0x0 + // Bit mask of SPI3_DMA_INT_MAP field. + INTERRUPT_CORE1_SPI3_DMA_INT_MAP_SPI3_DMA_INT_MAP_Msk = 0x1f + + // SPI4_DMA_INT_MAP: spi4_dma interrupt configuration register + // Position of SPI4_DMA_INT_MAP field. + INTERRUPT_CORE1_SPI4_DMA_INT_MAP_SPI4_DMA_INT_MAP_Pos = 0x0 + // Bit mask of SPI4_DMA_INT_MAP field. + INTERRUPT_CORE1_SPI4_DMA_INT_MAP_SPI4_DMA_INT_MAP_Msk = 0x1f + + // WDG_INT_MAP: wdg interrupt configuration register + // Position of WDG_INT_MAP field. + INTERRUPT_CORE1_WDG_INT_MAP_WDG_INT_MAP_Pos = 0x0 + // Bit mask of WDG_INT_MAP field. + INTERRUPT_CORE1_WDG_INT_MAP_WDG_INT_MAP_Msk = 0x1f + + // TIMER_INT1_MAP: timer_int1 interrupt configuration register + // Position of TIMER_INT1_MAP field. + INTERRUPT_CORE1_TIMER_INT1_MAP_TIMER_INT1_MAP_Pos = 0x0 + // Bit mask of TIMER_INT1_MAP field. + INTERRUPT_CORE1_TIMER_INT1_MAP_TIMER_INT1_MAP_Msk = 0x1f + + // TIMER_INT2_MAP: timer_int2 interrupt configuration register + // Position of TIMER_INT2_MAP field. + INTERRUPT_CORE1_TIMER_INT2_MAP_TIMER_INT2_MAP_Pos = 0x0 + // Bit mask of TIMER_INT2_MAP field. + INTERRUPT_CORE1_TIMER_INT2_MAP_TIMER_INT2_MAP_Msk = 0x1f + + // TG_T0_INT_MAP: tg_t0 interrupt configuration register + // Position of TG_T0_INT_MAP field. + INTERRUPT_CORE1_TG_T0_INT_MAP_TG_T0_INT_MAP_Pos = 0x0 + // Bit mask of TG_T0_INT_MAP field. + INTERRUPT_CORE1_TG_T0_INT_MAP_TG_T0_INT_MAP_Msk = 0x1f + + // TG_T1_INT_MAP: tg_t1 interrupt configuration register + // Position of TG_T1_INT_MAP field. + INTERRUPT_CORE1_TG_T1_INT_MAP_TG_T1_INT_MAP_Pos = 0x0 + // Bit mask of TG_T1_INT_MAP field. + INTERRUPT_CORE1_TG_T1_INT_MAP_TG_T1_INT_MAP_Msk = 0x1f + + // TG_WDT_INT_MAP: tg_wdt interrupt configuration register + // Position of TG_WDT_INT_MAP field. + INTERRUPT_CORE1_TG_WDT_INT_MAP_TG_WDT_INT_MAP_Pos = 0x0 + // Bit mask of TG_WDT_INT_MAP field. + INTERRUPT_CORE1_TG_WDT_INT_MAP_TG_WDT_INT_MAP_Msk = 0x1f + + // TG1_T0_INT_MAP: tg1_t0 interrupt configuration register + // Position of TG1_T0_INT_MAP field. + INTERRUPT_CORE1_TG1_T0_INT_MAP_TG1_T0_INT_MAP_Pos = 0x0 + // Bit mask of TG1_T0_INT_MAP field. + INTERRUPT_CORE1_TG1_T0_INT_MAP_TG1_T0_INT_MAP_Msk = 0x1f + + // TG1_T1_INT_MAP: tg1_t1 interrupt configuration register + // Position of TG1_T1_INT_MAP field. + INTERRUPT_CORE1_TG1_T1_INT_MAP_TG1_T1_INT_MAP_Pos = 0x0 + // Bit mask of TG1_T1_INT_MAP field. + INTERRUPT_CORE1_TG1_T1_INT_MAP_TG1_T1_INT_MAP_Msk = 0x1f + + // TG1_WDT_INT_MAP: tg1_wdt interrupt configuration register + // Position of TG1_WDT_INT_MAP field. + INTERRUPT_CORE1_TG1_WDT_INT_MAP_TG1_WDT_INT_MAP_Pos = 0x0 + // Bit mask of TG1_WDT_INT_MAP field. + INTERRUPT_CORE1_TG1_WDT_INT_MAP_TG1_WDT_INT_MAP_Msk = 0x1f + + // CACHE_IA_INT_MAP: cache_ia interrupt configuration register + // Position of CACHE_IA_INT_MAP field. + INTERRUPT_CORE1_CACHE_IA_INT_MAP_CACHE_IA_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_IA_INT_MAP field. + INTERRUPT_CORE1_CACHE_IA_INT_MAP_CACHE_IA_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET0_INT_MAP: systimer_target0 interrupt configuration register + // Position of SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_SYSTIMER_TARGET0_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET0_INT_MAP field. + INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_SYSTIMER_TARGET0_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET1_INT_MAP: systimer_target1 interrupt configuration register + // Position of SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_SYSTIMER_TARGET1_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET1_INT_MAP field. + INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_SYSTIMER_TARGET1_INT_MAP_Msk = 0x1f + + // SYSTIMER_TARGET2_INT_MAP: systimer_target2 interrupt configuration register + // Position of SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_SYSTIMER_TARGET2_INT_MAP_Pos = 0x0 + // Bit mask of SYSTIMER_TARGET2_INT_MAP field. + INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_SYSTIMER_TARGET2_INT_MAP_Msk = 0x1f + + // SPI_MEM_REJECT_INTR_MAP: spi_mem_reject interrupt configuration register + // Position of SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_SPI_MEM_REJECT_INTR_MAP_Pos = 0x0 + // Bit mask of SPI_MEM_REJECT_INTR_MAP field. + INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_SPI_MEM_REJECT_INTR_MAP_Msk = 0x1f + + // DCACHE_PRELOAD_INT_MAP: dcache_prelaod interrupt configuration register + // Position of DCACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_DCACHE_PRELOAD_INT_MAP_Pos = 0x0 + // Bit mask of DCACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_DCACHE_PRELOAD_INT_MAP_Msk = 0x1f + + // ICACHE_PRELOAD_INT_MAP: icache_preload interrupt configuration register + // Position of ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_ICACHE_PRELOAD_INT_MAP_Pos = 0x0 + // Bit mask of ICACHE_PRELOAD_INT_MAP field. + INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_ICACHE_PRELOAD_INT_MAP_Msk = 0x1f + + // DCACHE_SYNC_INT_MAP: dcache_sync interrupt configuration register + // Position of DCACHE_SYNC_INT_MAP field. + INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_DCACHE_SYNC_INT_MAP_Pos = 0x0 + // Bit mask of DCACHE_SYNC_INT_MAP field. + INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_DCACHE_SYNC_INT_MAP_Msk = 0x1f + + // ICACHE_SYNC_INT_MAP: icache_sync interrupt configuration register + // Position of ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_ICACHE_SYNC_INT_MAP_Pos = 0x0 + // Bit mask of ICACHE_SYNC_INT_MAP field. + INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_ICACHE_SYNC_INT_MAP_Msk = 0x1f + + // APB_ADC_INT_MAP: apb_adc interrupt configuration register + // Position of APB_ADC_INT_MAP field. + INTERRUPT_CORE1_APB_ADC_INT_MAP_APB_ADC_INT_MAP_Pos = 0x0 + // Bit mask of APB_ADC_INT_MAP field. + INTERRUPT_CORE1_APB_ADC_INT_MAP_APB_ADC_INT_MAP_Msk = 0x1f + + // DMA_IN_CH0_INT_MAP: dma_in_ch0 interrupt configuration register + // Position of DMA_IN_CH0_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_DMA_IN_CH0_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH0_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_DMA_IN_CH0_INT_MAP_Msk = 0x1f + + // DMA_IN_CH1_INT_MAP: dma_in_ch1 interrupt configuration register + // Position of DMA_IN_CH1_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_DMA_IN_CH1_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH1_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_DMA_IN_CH1_INT_MAP_Msk = 0x1f + + // DMA_IN_CH2_INT_MAP: dma_in_ch2 interrupt configuration register + // Position of DMA_IN_CH2_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_DMA_IN_CH2_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH2_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_DMA_IN_CH2_INT_MAP_Msk = 0x1f + + // DMA_IN_CH3_INT_MAP: dma_in_ch3 interrupt configuration register + // Position of DMA_IN_CH3_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_DMA_IN_CH3_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH3_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_DMA_IN_CH3_INT_MAP_Msk = 0x1f + + // DMA_IN_CH4_INT_MAP: dma_in_ch4 interrupt configuration register + // Position of DMA_IN_CH4_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_DMA_IN_CH4_INT_MAP_Pos = 0x0 + // Bit mask of DMA_IN_CH4_INT_MAP field. + INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_DMA_IN_CH4_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH0_INT_MAP: dma_out_ch0 interrupt configuration register + // Position of DMA_OUT_CH0_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_DMA_OUT_CH0_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH0_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_DMA_OUT_CH0_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH1_INT_MAP: dma_out_ch1 interrupt configuration register + // Position of DMA_OUT_CH1_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_DMA_OUT_CH1_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH1_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_DMA_OUT_CH1_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH2_INT_MAP: dma_out_ch2 interrupt configuration register + // Position of DMA_OUT_CH2_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_DMA_OUT_CH2_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH2_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_DMA_OUT_CH2_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH3_INT_MAP: dma_out_ch3 interrupt configuration register + // Position of DMA_OUT_CH3_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_DMA_OUT_CH3_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH3_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_DMA_OUT_CH3_INT_MAP_Msk = 0x1f + + // DMA_OUT_CH4_INT_MAP: dma_out_ch4 interrupt configuration register + // Position of DMA_OUT_CH4_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_DMA_OUT_CH4_INT_MAP_Pos = 0x0 + // Bit mask of DMA_OUT_CH4_INT_MAP field. + INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_DMA_OUT_CH4_INT_MAP_Msk = 0x1f + + // RSA_INT_MAP: rsa interrupt configuration register + // Position of RSA_INT_MAP field. + INTERRUPT_CORE1_RSA_INT_MAP_RSA_INT_MAP_Pos = 0x0 + // Bit mask of RSA_INT_MAP field. + INTERRUPT_CORE1_RSA_INT_MAP_RSA_INT_MAP_Msk = 0x1f + + // AES_INT_MAP: aes interrupt configuration register + // Position of AES_INT_MAP field. + INTERRUPT_CORE1_AES_INT_MAP_AES_INT_MAP_Pos = 0x0 + // Bit mask of AES_INT_MAP field. + INTERRUPT_CORE1_AES_INT_MAP_AES_INT_MAP_Msk = 0x1f + + // SHA_INT_MAP: sha interrupt configuration register + // Position of SHA_INT_MAP field. + INTERRUPT_CORE1_SHA_INT_MAP_SHA_INT_MAP_Pos = 0x0 + // Bit mask of SHA_INT_MAP field. + INTERRUPT_CORE1_SHA_INT_MAP_SHA_INT_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_0_MAP: cpu_intr_from_cpu_0 interrupt configuration register + // Position of CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0_MAP field. + INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_CPU_INTR_FROM_CPU_0_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_1_MAP: cpu_intr_from_cpu_1 interrupt configuration register + // Position of CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1_MAP field. + INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_CPU_INTR_FROM_CPU_1_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_2_MAP: cpu_intr_from_cpu_2 interrupt configuration register + // Position of CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2_MAP field. + INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_CPU_INTR_FROM_CPU_2_MAP_Msk = 0x1f + + // CPU_INTR_FROM_CPU_3_MAP: cpu_intr_from_cpu_3 interrupt configuration register + // Position of CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3_MAP field. + INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_CPU_INTR_FROM_CPU_3_MAP_Msk = 0x1f + + // ASSIST_DEBUG_INTR_MAP: assist_debug interrupt configuration register + // Position of ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Pos = 0x0 + // Bit mask of ASSIST_DEBUG_INTR_MAP field. + INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_ASSIST_DEBUG_INTR_MAP_Msk = 0x1f + + // DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: dma_pms_monitor_violatile interrupt configuration register + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core0_IRam0_pms_monitor_violatile interrupt configuration register + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core0_DRam0_pms_monitor_violatile interrupt configuration register + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: core0_PIF_pms_monitor_violatile interrupt configuration register + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: core0_PIF_pms_monitor_violatile_size interrupt configuration register + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Msk = 0x1f + + // CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core1_IRam0_pms_monitor_violatile interrupt configuration register + // Position of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: core1_DRam0_pms_monitor_violatile interrupt configuration register + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: core1_PIF_pms_monitor_violatile interrupt configuration register + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_Msk = 0x1f + + // CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: core1_PIF_pms_monitor_violatile_size interrupt configuration register + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP field. + INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_Msk = 0x1f + + // BACKUP_PMS_VIOLATE_INTR_MAP: backup_pms_monitor_violatile interrupt configuration register + // Position of BACKUP_PMS_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_BACKUP_PMS_VIOLATE_INTR_MAP_Pos = 0x0 + // Bit mask of BACKUP_PMS_VIOLATE_INTR_MAP field. + INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_BACKUP_PMS_VIOLATE_INTR_MAP_Msk = 0x1f + + // CACHE_CORE0_ACS_INT_MAP: cache_core0_acs interrupt configuration register + // Position of CACHE_CORE0_ACS_INT_MAP field. + INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_CACHE_CORE0_ACS_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_CORE0_ACS_INT_MAP field. + INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_CACHE_CORE0_ACS_INT_MAP_Msk = 0x1f + + // CACHE_CORE1_ACS_INT_MAP: cache_core1_acs interrupt configuration register + // Position of CACHE_CORE1_ACS_INT_MAP field. + INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_CACHE_CORE1_ACS_INT_MAP_Pos = 0x0 + // Bit mask of CACHE_CORE1_ACS_INT_MAP field. + INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_CACHE_CORE1_ACS_INT_MAP_Msk = 0x1f + + // USB_DEVICE_INT_MAP: usb_device interrupt configuration register + // Position of USB_DEVICE_INT_MAP field. + INTERRUPT_CORE1_USB_DEVICE_INT_MAP_USB_DEVICE_INT_MAP_Pos = 0x0 + // Bit mask of USB_DEVICE_INT_MAP field. + INTERRUPT_CORE1_USB_DEVICE_INT_MAP_USB_DEVICE_INT_MAP_Msk = 0x1f + + // PERI_BACKUP_INT_MAP: peri_backup interrupt configuration register + // Position of PERI_BACKUP_INT_MAP field. + INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_PERI_BACKUP_INT_MAP_Pos = 0x0 + // Bit mask of PERI_BACKUP_INT_MAP field. + INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_PERI_BACKUP_INT_MAP_Msk = 0x1f + + // DMA_EXTMEM_REJECT_INT_MAP: dma_extmem_reject interrupt configuration register + // Position of DMA_EXTMEM_REJECT_INT_MAP field. + INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_DMA_EXTMEM_REJECT_INT_MAP_Pos = 0x0 + // Bit mask of DMA_EXTMEM_REJECT_INT_MAP field. + INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_DMA_EXTMEM_REJECT_INT_MAP_Msk = 0x1f + + // APP_INTR_STATUS_0: interrupt status register + // Position of INTR_STATUS_0 field. + INTERRUPT_CORE1_APP_INTR_STATUS_0_INTR_STATUS_0_Pos = 0x0 + // Bit mask of INTR_STATUS_0 field. + INTERRUPT_CORE1_APP_INTR_STATUS_0_INTR_STATUS_0_Msk = 0xffffffff + + // APP_INTR_STATUS_1: interrupt status register + // Position of INTR_STATUS_1 field. + INTERRUPT_CORE1_APP_INTR_STATUS_1_INTR_STATUS_1_Pos = 0x0 + // Bit mask of INTR_STATUS_1 field. + INTERRUPT_CORE1_APP_INTR_STATUS_1_INTR_STATUS_1_Msk = 0xffffffff + + // APP_INTR_STATUS_2: interrupt status register + // Position of INTR_STATUS_2 field. + INTERRUPT_CORE1_APP_INTR_STATUS_2_INTR_STATUS_2_Pos = 0x0 + // Bit mask of INTR_STATUS_2 field. + INTERRUPT_CORE1_APP_INTR_STATUS_2_INTR_STATUS_2_Msk = 0xffffffff + + // APP_INTR_STATUS_3: interrupt status register + // Position of INTR_STATUS_3 field. + INTERRUPT_CORE1_APP_INTR_STATUS_3_INTR_STATUS_3_Pos = 0x0 + // Bit mask of INTR_STATUS_3 field. + INTERRUPT_CORE1_APP_INTR_STATUS_3_INTR_STATUS_3_Msk = 0xffffffff + + // CLOCK_GATE: clock gate register + // Position of REG_CLK_EN field. + INTERRUPT_CORE1_CLOCK_GATE_REG_CLK_EN_Pos = 0x0 + // Bit mask of REG_CLK_EN field. + INTERRUPT_CORE1_CLOCK_GATE_REG_CLK_EN_Msk = 0x1 + // Bit REG_CLK_EN. + INTERRUPT_CORE1_CLOCK_GATE_REG_CLK_EN = 0x1 + + // DATE: version register + // Position of INTERRUPT_DATE field. + INTERRUPT_CORE1_DATE_INTERRUPT_DATE_Pos = 0x0 + // Bit mask of INTERRUPT_DATE field. + INTERRUPT_CORE1_DATE_INTERRUPT_DATE_Msk = 0xfffffff +) + +// Constants for IO_MUX: Input/Output Multiplexer +const ( + // PIN_CTRL: Clock Output Configuration Register + // Position of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Pos = 0x0 + // Bit mask of CLK_OUT1 field. + IO_MUX_PIN_CTRL_CLK_OUT1_Msk = 0xf + // Position of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Pos = 0x4 + // Bit mask of CLK_OUT2 field. + IO_MUX_PIN_CTRL_CLK_OUT2_Msk = 0xf0 + // Position of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Pos = 0x8 + // Bit mask of CLK_OUT3 field. + IO_MUX_PIN_CTRL_CLK_OUT3_Msk = 0xf00 + + // GPIO0: IO MUX Configure Register for pad GPIO0 + // Position of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Pos = 0x0 + // Bit mask of MCU_OE field. + IO_MUX_GPIO_MCU_OE_Msk = 0x1 + // Bit MCU_OE. + IO_MUX_GPIO_MCU_OE = 0x1 + // Position of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Pos = 0x1 + // Bit mask of SLP_SEL field. + IO_MUX_GPIO_SLP_SEL_Msk = 0x2 + // Bit SLP_SEL. + IO_MUX_GPIO_SLP_SEL = 0x2 + // Position of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Pos = 0x2 + // Bit mask of MCU_WPD field. + IO_MUX_GPIO_MCU_WPD_Msk = 0x4 + // Bit MCU_WPD. + IO_MUX_GPIO_MCU_WPD = 0x4 + // Position of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Pos = 0x3 + // Bit mask of MCU_WPU field. + IO_MUX_GPIO_MCU_WPU_Msk = 0x8 + // Bit MCU_WPU. + IO_MUX_GPIO_MCU_WPU = 0x8 + // Position of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Pos = 0x4 + // Bit mask of MCU_IE field. + IO_MUX_GPIO_MCU_IE_Msk = 0x10 + // Bit MCU_IE. + IO_MUX_GPIO_MCU_IE = 0x10 + // Position of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Pos = 0x7 + // Bit mask of FUN_WPD field. + IO_MUX_GPIO_FUN_WPD_Msk = 0x80 + // Bit FUN_WPD. + IO_MUX_GPIO_FUN_WPD = 0x80 + // Position of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Pos = 0x8 + // Bit mask of FUN_WPU field. + IO_MUX_GPIO_FUN_WPU_Msk = 0x100 + // Bit FUN_WPU. + IO_MUX_GPIO_FUN_WPU = 0x100 + // Position of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Pos = 0x9 + // Bit mask of FUN_IE field. + IO_MUX_GPIO_FUN_IE_Msk = 0x200 + // Bit FUN_IE. + IO_MUX_GPIO_FUN_IE = 0x200 + // Position of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Pos = 0xa + // Bit mask of FUN_DRV field. + IO_MUX_GPIO_FUN_DRV_Msk = 0xc00 + // Position of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Pos = 0xc + // Bit mask of MCU_SEL field. + IO_MUX_GPIO_MCU_SEL_Msk = 0x7000 + // Position of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Pos = 0xf + // Bit mask of FILTER_EN field. + IO_MUX_GPIO_FILTER_EN_Msk = 0x8000 + // Bit FILTER_EN. + IO_MUX_GPIO_FILTER_EN = 0x8000 + + // DATE: IO MUX Version Control Register + // Position of REG_DATE field. + IO_MUX_DATE_REG_DATE_Pos = 0x0 + // Bit mask of REG_DATE field. + IO_MUX_DATE_REG_DATE_Msk = 0xfffffff +) + +// Constants for LCD_CAM: Camera/LCD Controller +const ( + // LCD_CLOCK: LCD clock register + // Position of LCD_CLKCNT_N field. + LCD_CAM_LCD_CLOCK_LCD_CLKCNT_N_Pos = 0x0 + // Bit mask of LCD_CLKCNT_N field. + LCD_CAM_LCD_CLOCK_LCD_CLKCNT_N_Msk = 0x3f + // Position of LCD_CLK_EQU_SYSCLK field. + LCD_CAM_LCD_CLOCK_LCD_CLK_EQU_SYSCLK_Pos = 0x6 + // Bit mask of LCD_CLK_EQU_SYSCLK field. + LCD_CAM_LCD_CLOCK_LCD_CLK_EQU_SYSCLK_Msk = 0x40 + // Bit LCD_CLK_EQU_SYSCLK. + LCD_CAM_LCD_CLOCK_LCD_CLK_EQU_SYSCLK = 0x40 + // Position of LCD_CK_IDLE_EDGE field. + LCD_CAM_LCD_CLOCK_LCD_CK_IDLE_EDGE_Pos = 0x7 + // Bit mask of LCD_CK_IDLE_EDGE field. + LCD_CAM_LCD_CLOCK_LCD_CK_IDLE_EDGE_Msk = 0x80 + // Bit LCD_CK_IDLE_EDGE. + LCD_CAM_LCD_CLOCK_LCD_CK_IDLE_EDGE = 0x80 + // Position of LCD_CK_OUT_EDGE field. + LCD_CAM_LCD_CLOCK_LCD_CK_OUT_EDGE_Pos = 0x8 + // Bit mask of LCD_CK_OUT_EDGE field. + LCD_CAM_LCD_CLOCK_LCD_CK_OUT_EDGE_Msk = 0x100 + // Bit LCD_CK_OUT_EDGE. + LCD_CAM_LCD_CLOCK_LCD_CK_OUT_EDGE = 0x100 + // Position of LCD_CLKM_DIV_NUM field. + LCD_CAM_LCD_CLOCK_LCD_CLKM_DIV_NUM_Pos = 0x9 + // Bit mask of LCD_CLKM_DIV_NUM field. + LCD_CAM_LCD_CLOCK_LCD_CLKM_DIV_NUM_Msk = 0x1fe00 + // Position of LCD_CLKM_DIV_B field. + LCD_CAM_LCD_CLOCK_LCD_CLKM_DIV_B_Pos = 0x11 + // Bit mask of LCD_CLKM_DIV_B field. + LCD_CAM_LCD_CLOCK_LCD_CLKM_DIV_B_Msk = 0x7e0000 + // Position of LCD_CLKM_DIV_A field. + LCD_CAM_LCD_CLOCK_LCD_CLKM_DIV_A_Pos = 0x17 + // Bit mask of LCD_CLKM_DIV_A field. + LCD_CAM_LCD_CLOCK_LCD_CLKM_DIV_A_Msk = 0x1f800000 + // Position of LCD_CLK_SEL field. + LCD_CAM_LCD_CLOCK_LCD_CLK_SEL_Pos = 0x1d + // Bit mask of LCD_CLK_SEL field. + LCD_CAM_LCD_CLOCK_LCD_CLK_SEL_Msk = 0x60000000 + // Position of CLK_EN field. + LCD_CAM_LCD_CLOCK_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LCD_CAM_LCD_CLOCK_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LCD_CAM_LCD_CLOCK_CLK_EN = 0x80000000 + + // CAM_CTRL: Camera configuration register + // Position of CAM_STOP_EN field. + LCD_CAM_CAM_CTRL_CAM_STOP_EN_Pos = 0x0 + // Bit mask of CAM_STOP_EN field. + LCD_CAM_CAM_CTRL_CAM_STOP_EN_Msk = 0x1 + // Bit CAM_STOP_EN. + LCD_CAM_CAM_CTRL_CAM_STOP_EN = 0x1 + // Position of CAM_VSYNC_FILTER_THRES field. + LCD_CAM_CAM_CTRL_CAM_VSYNC_FILTER_THRES_Pos = 0x1 + // Bit mask of CAM_VSYNC_FILTER_THRES field. + LCD_CAM_CAM_CTRL_CAM_VSYNC_FILTER_THRES_Msk = 0xe + // Position of CAM_UPDATE field. + LCD_CAM_CAM_CTRL_CAM_UPDATE_Pos = 0x4 + // Bit mask of CAM_UPDATE field. + LCD_CAM_CAM_CTRL_CAM_UPDATE_Msk = 0x10 + // Bit CAM_UPDATE. + LCD_CAM_CAM_CTRL_CAM_UPDATE = 0x10 + // Position of CAM_BYTE_ORDER field. + LCD_CAM_CAM_CTRL_CAM_BYTE_ORDER_Pos = 0x5 + // Bit mask of CAM_BYTE_ORDER field. + LCD_CAM_CAM_CTRL_CAM_BYTE_ORDER_Msk = 0x20 + // Bit CAM_BYTE_ORDER. + LCD_CAM_CAM_CTRL_CAM_BYTE_ORDER = 0x20 + // Position of CAM_BIT_ORDER field. + LCD_CAM_CAM_CTRL_CAM_BIT_ORDER_Pos = 0x6 + // Bit mask of CAM_BIT_ORDER field. + LCD_CAM_CAM_CTRL_CAM_BIT_ORDER_Msk = 0x40 + // Bit CAM_BIT_ORDER. + LCD_CAM_CAM_CTRL_CAM_BIT_ORDER = 0x40 + // Position of CAM_LINE_INT_EN field. + LCD_CAM_CAM_CTRL_CAM_LINE_INT_EN_Pos = 0x7 + // Bit mask of CAM_LINE_INT_EN field. + LCD_CAM_CAM_CTRL_CAM_LINE_INT_EN_Msk = 0x80 + // Bit CAM_LINE_INT_EN. + LCD_CAM_CAM_CTRL_CAM_LINE_INT_EN = 0x80 + // Position of CAM_VS_EOF_EN field. + LCD_CAM_CAM_CTRL_CAM_VS_EOF_EN_Pos = 0x8 + // Bit mask of CAM_VS_EOF_EN field. + LCD_CAM_CAM_CTRL_CAM_VS_EOF_EN_Msk = 0x100 + // Bit CAM_VS_EOF_EN. + LCD_CAM_CAM_CTRL_CAM_VS_EOF_EN = 0x100 + // Position of CAM_CLKM_DIV_NUM field. + LCD_CAM_CAM_CTRL_CAM_CLKM_DIV_NUM_Pos = 0x9 + // Bit mask of CAM_CLKM_DIV_NUM field. + LCD_CAM_CAM_CTRL_CAM_CLKM_DIV_NUM_Msk = 0x1fe00 + // Position of CAM_CLKM_DIV_B field. + LCD_CAM_CAM_CTRL_CAM_CLKM_DIV_B_Pos = 0x11 + // Bit mask of CAM_CLKM_DIV_B field. + LCD_CAM_CAM_CTRL_CAM_CLKM_DIV_B_Msk = 0x7e0000 + // Position of CAM_CLKM_DIV_A field. + LCD_CAM_CAM_CTRL_CAM_CLKM_DIV_A_Pos = 0x17 + // Bit mask of CAM_CLKM_DIV_A field. + LCD_CAM_CAM_CTRL_CAM_CLKM_DIV_A_Msk = 0x1f800000 + // Position of CAM_CLK_SEL field. + LCD_CAM_CAM_CTRL_CAM_CLK_SEL_Pos = 0x1d + // Bit mask of CAM_CLK_SEL field. + LCD_CAM_CAM_CTRL_CAM_CLK_SEL_Msk = 0x60000000 + + // CAM_CTRL1: Camera configuration register + // Position of CAM_REC_DATA_BYTELEN field. + LCD_CAM_CAM_CTRL1_CAM_REC_DATA_BYTELEN_Pos = 0x0 + // Bit mask of CAM_REC_DATA_BYTELEN field. + LCD_CAM_CAM_CTRL1_CAM_REC_DATA_BYTELEN_Msk = 0xffff + // Position of CAM_LINE_INT_NUM field. + LCD_CAM_CAM_CTRL1_CAM_LINE_INT_NUM_Pos = 0x10 + // Bit mask of CAM_LINE_INT_NUM field. + LCD_CAM_CAM_CTRL1_CAM_LINE_INT_NUM_Msk = 0x3f0000 + // Position of CAM_CLK_INV field. + LCD_CAM_CAM_CTRL1_CAM_CLK_INV_Pos = 0x16 + // Bit mask of CAM_CLK_INV field. + LCD_CAM_CAM_CTRL1_CAM_CLK_INV_Msk = 0x400000 + // Bit CAM_CLK_INV. + LCD_CAM_CAM_CTRL1_CAM_CLK_INV = 0x400000 + // Position of CAM_VSYNC_FILTER_EN field. + LCD_CAM_CAM_CTRL1_CAM_VSYNC_FILTER_EN_Pos = 0x17 + // Bit mask of CAM_VSYNC_FILTER_EN field. + LCD_CAM_CAM_CTRL1_CAM_VSYNC_FILTER_EN_Msk = 0x800000 + // Bit CAM_VSYNC_FILTER_EN. + LCD_CAM_CAM_CTRL1_CAM_VSYNC_FILTER_EN = 0x800000 + // Position of CAM_2BYTE_EN field. + LCD_CAM_CAM_CTRL1_CAM_2BYTE_EN_Pos = 0x18 + // Bit mask of CAM_2BYTE_EN field. + LCD_CAM_CAM_CTRL1_CAM_2BYTE_EN_Msk = 0x1000000 + // Bit CAM_2BYTE_EN. + LCD_CAM_CAM_CTRL1_CAM_2BYTE_EN = 0x1000000 + // Position of CAM_DE_INV field. + LCD_CAM_CAM_CTRL1_CAM_DE_INV_Pos = 0x19 + // Bit mask of CAM_DE_INV field. + LCD_CAM_CAM_CTRL1_CAM_DE_INV_Msk = 0x2000000 + // Bit CAM_DE_INV. + LCD_CAM_CAM_CTRL1_CAM_DE_INV = 0x2000000 + // Position of CAM_HSYNC_INV field. + LCD_CAM_CAM_CTRL1_CAM_HSYNC_INV_Pos = 0x1a + // Bit mask of CAM_HSYNC_INV field. + LCD_CAM_CAM_CTRL1_CAM_HSYNC_INV_Msk = 0x4000000 + // Bit CAM_HSYNC_INV. + LCD_CAM_CAM_CTRL1_CAM_HSYNC_INV = 0x4000000 + // Position of CAM_VSYNC_INV field. + LCD_CAM_CAM_CTRL1_CAM_VSYNC_INV_Pos = 0x1b + // Bit mask of CAM_VSYNC_INV field. + LCD_CAM_CAM_CTRL1_CAM_VSYNC_INV_Msk = 0x8000000 + // Bit CAM_VSYNC_INV. + LCD_CAM_CAM_CTRL1_CAM_VSYNC_INV = 0x8000000 + // Position of CAM_VH_DE_MODE_EN field. + LCD_CAM_CAM_CTRL1_CAM_VH_DE_MODE_EN_Pos = 0x1c + // Bit mask of CAM_VH_DE_MODE_EN field. + LCD_CAM_CAM_CTRL1_CAM_VH_DE_MODE_EN_Msk = 0x10000000 + // Bit CAM_VH_DE_MODE_EN. + LCD_CAM_CAM_CTRL1_CAM_VH_DE_MODE_EN = 0x10000000 + // Position of CAM_START field. + LCD_CAM_CAM_CTRL1_CAM_START_Pos = 0x1d + // Bit mask of CAM_START field. + LCD_CAM_CAM_CTRL1_CAM_START_Msk = 0x20000000 + // Bit CAM_START. + LCD_CAM_CAM_CTRL1_CAM_START = 0x20000000 + // Position of CAM_RESET field. + LCD_CAM_CAM_CTRL1_CAM_RESET_Pos = 0x1e + // Bit mask of CAM_RESET field. + LCD_CAM_CAM_CTRL1_CAM_RESET_Msk = 0x40000000 + // Bit CAM_RESET. + LCD_CAM_CAM_CTRL1_CAM_RESET = 0x40000000 + // Position of CAM_AFIFO_RESET field. + LCD_CAM_CAM_CTRL1_CAM_AFIFO_RESET_Pos = 0x1f + // Bit mask of CAM_AFIFO_RESET field. + LCD_CAM_CAM_CTRL1_CAM_AFIFO_RESET_Msk = 0x80000000 + // Bit CAM_AFIFO_RESET. + LCD_CAM_CAM_CTRL1_CAM_AFIFO_RESET = 0x80000000 + + // CAM_RGB_YUV: Camera configuration register + // Position of CAM_CONV_8BITS_DATA_INV field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV_Pos = 0x15 + // Bit mask of CAM_CONV_8BITS_DATA_INV field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV_Msk = 0x200000 + // Bit CAM_CONV_8BITS_DATA_INV. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV = 0x200000 + // Position of CAM_CONV_YUV2YUV_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE_Pos = 0x16 + // Bit mask of CAM_CONV_YUV2YUV_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE_Msk = 0xc00000 + // Position of CAM_CONV_YUV_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_YUV_MODE_Pos = 0x18 + // Bit mask of CAM_CONV_YUV_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_YUV_MODE_Msk = 0x3000000 + // Position of CAM_CONV_PROTOCOL_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE_Pos = 0x1a + // Bit mask of CAM_CONV_PROTOCOL_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE_Msk = 0x4000000 + // Bit CAM_CONV_PROTOCOL_MODE. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE = 0x4000000 + // Position of CAM_CONV_DATA_OUT_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE_Pos = 0x1b + // Bit mask of CAM_CONV_DATA_OUT_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE_Msk = 0x8000000 + // Bit CAM_CONV_DATA_OUT_MODE. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE = 0x8000000 + // Position of CAM_CONV_DATA_IN_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_DATA_IN_MODE_Pos = 0x1c + // Bit mask of CAM_CONV_DATA_IN_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_DATA_IN_MODE_Msk = 0x10000000 + // Bit CAM_CONV_DATA_IN_MODE. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_DATA_IN_MODE = 0x10000000 + // Position of CAM_CONV_MODE_8BITS_ON field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON_Pos = 0x1d + // Bit mask of CAM_CONV_MODE_8BITS_ON field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON_Msk = 0x20000000 + // Bit CAM_CONV_MODE_8BITS_ON. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON = 0x20000000 + // Position of CAM_CONV_TRANS_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_TRANS_MODE_Pos = 0x1e + // Bit mask of CAM_CONV_TRANS_MODE field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_TRANS_MODE_Msk = 0x40000000 + // Bit CAM_CONV_TRANS_MODE. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_TRANS_MODE = 0x40000000 + // Position of CAM_CONV_BYPASS field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_BYPASS_Pos = 0x1f + // Bit mask of CAM_CONV_BYPASS field. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_BYPASS_Msk = 0x80000000 + // Bit CAM_CONV_BYPASS. + LCD_CAM_CAM_RGB_YUV_CAM_CONV_BYPASS = 0x80000000 + + // LCD_RGB_YUV: LCD configuration register + // Position of LCD_CONV_8BITS_DATA_INV field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV_Pos = 0x14 + // Bit mask of LCD_CONV_8BITS_DATA_INV field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV_Msk = 0x100000 + // Bit LCD_CONV_8BITS_DATA_INV. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV = 0x100000 + // Position of LCD_CONV_TXTORX field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_TXTORX_Pos = 0x15 + // Bit mask of LCD_CONV_TXTORX field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_TXTORX_Msk = 0x200000 + // Bit LCD_CONV_TXTORX. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_TXTORX = 0x200000 + // Position of LCD_CONV_YUV2YUV_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE_Pos = 0x16 + // Bit mask of LCD_CONV_YUV2YUV_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE_Msk = 0xc00000 + // Position of LCD_CONV_YUV_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_YUV_MODE_Pos = 0x18 + // Bit mask of LCD_CONV_YUV_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_YUV_MODE_Msk = 0x3000000 + // Position of LCD_CONV_PROTOCOL_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE_Pos = 0x1a + // Bit mask of LCD_CONV_PROTOCOL_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE_Msk = 0x4000000 + // Bit LCD_CONV_PROTOCOL_MODE. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE = 0x4000000 + // Position of LCD_CONV_DATA_OUT_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE_Pos = 0x1b + // Bit mask of LCD_CONV_DATA_OUT_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE_Msk = 0x8000000 + // Bit LCD_CONV_DATA_OUT_MODE. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE = 0x8000000 + // Position of LCD_CONV_DATA_IN_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_DATA_IN_MODE_Pos = 0x1c + // Bit mask of LCD_CONV_DATA_IN_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_DATA_IN_MODE_Msk = 0x10000000 + // Bit LCD_CONV_DATA_IN_MODE. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_DATA_IN_MODE = 0x10000000 + // Position of LCD_CONV_MODE_8BITS_ON field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON_Pos = 0x1d + // Bit mask of LCD_CONV_MODE_8BITS_ON field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON_Msk = 0x20000000 + // Bit LCD_CONV_MODE_8BITS_ON. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON = 0x20000000 + // Position of LCD_CONV_TRANS_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_TRANS_MODE_Pos = 0x1e + // Bit mask of LCD_CONV_TRANS_MODE field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_TRANS_MODE_Msk = 0x40000000 + // Bit LCD_CONV_TRANS_MODE. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_TRANS_MODE = 0x40000000 + // Position of LCD_CONV_BYPASS field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_BYPASS_Pos = 0x1f + // Bit mask of LCD_CONV_BYPASS field. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_BYPASS_Msk = 0x80000000 + // Bit LCD_CONV_BYPASS. + LCD_CAM_LCD_RGB_YUV_LCD_CONV_BYPASS = 0x80000000 + + // LCD_USER: LCD configuration register + // Position of LCD_DOUT_CYCLELEN field. + LCD_CAM_LCD_USER_LCD_DOUT_CYCLELEN_Pos = 0x0 + // Bit mask of LCD_DOUT_CYCLELEN field. + LCD_CAM_LCD_USER_LCD_DOUT_CYCLELEN_Msk = 0x1fff + // Position of LCD_ALWAYS_OUT_EN field. + LCD_CAM_LCD_USER_LCD_ALWAYS_OUT_EN_Pos = 0xd + // Bit mask of LCD_ALWAYS_OUT_EN field. + LCD_CAM_LCD_USER_LCD_ALWAYS_OUT_EN_Msk = 0x2000 + // Bit LCD_ALWAYS_OUT_EN. + LCD_CAM_LCD_USER_LCD_ALWAYS_OUT_EN = 0x2000 + // Position of LCD_8BITS_ORDER field. + LCD_CAM_LCD_USER_LCD_8BITS_ORDER_Pos = 0x13 + // Bit mask of LCD_8BITS_ORDER field. + LCD_CAM_LCD_USER_LCD_8BITS_ORDER_Msk = 0x80000 + // Bit LCD_8BITS_ORDER. + LCD_CAM_LCD_USER_LCD_8BITS_ORDER = 0x80000 + // Position of LCD_UPDATE field. + LCD_CAM_LCD_USER_LCD_UPDATE_Pos = 0x14 + // Bit mask of LCD_UPDATE field. + LCD_CAM_LCD_USER_LCD_UPDATE_Msk = 0x100000 + // Bit LCD_UPDATE. + LCD_CAM_LCD_USER_LCD_UPDATE = 0x100000 + // Position of LCD_BIT_ORDER field. + LCD_CAM_LCD_USER_LCD_BIT_ORDER_Pos = 0x15 + // Bit mask of LCD_BIT_ORDER field. + LCD_CAM_LCD_USER_LCD_BIT_ORDER_Msk = 0x200000 + // Bit LCD_BIT_ORDER. + LCD_CAM_LCD_USER_LCD_BIT_ORDER = 0x200000 + // Position of LCD_BYTE_ORDER field. + LCD_CAM_LCD_USER_LCD_BYTE_ORDER_Pos = 0x16 + // Bit mask of LCD_BYTE_ORDER field. + LCD_CAM_LCD_USER_LCD_BYTE_ORDER_Msk = 0x400000 + // Bit LCD_BYTE_ORDER. + LCD_CAM_LCD_USER_LCD_BYTE_ORDER = 0x400000 + // Position of LCD_2BYTE_EN field. + LCD_CAM_LCD_USER_LCD_2BYTE_EN_Pos = 0x17 + // Bit mask of LCD_2BYTE_EN field. + LCD_CAM_LCD_USER_LCD_2BYTE_EN_Msk = 0x800000 + // Bit LCD_2BYTE_EN. + LCD_CAM_LCD_USER_LCD_2BYTE_EN = 0x800000 + // Position of LCD_DOUT field. + LCD_CAM_LCD_USER_LCD_DOUT_Pos = 0x18 + // Bit mask of LCD_DOUT field. + LCD_CAM_LCD_USER_LCD_DOUT_Msk = 0x1000000 + // Bit LCD_DOUT. + LCD_CAM_LCD_USER_LCD_DOUT = 0x1000000 + // Position of LCD_DUMMY field. + LCD_CAM_LCD_USER_LCD_DUMMY_Pos = 0x19 + // Bit mask of LCD_DUMMY field. + LCD_CAM_LCD_USER_LCD_DUMMY_Msk = 0x2000000 + // Bit LCD_DUMMY. + LCD_CAM_LCD_USER_LCD_DUMMY = 0x2000000 + // Position of LCD_CMD field. + LCD_CAM_LCD_USER_LCD_CMD_Pos = 0x1a + // Bit mask of LCD_CMD field. + LCD_CAM_LCD_USER_LCD_CMD_Msk = 0x4000000 + // Bit LCD_CMD. + LCD_CAM_LCD_USER_LCD_CMD = 0x4000000 + // Position of LCD_START field. + LCD_CAM_LCD_USER_LCD_START_Pos = 0x1b + // Bit mask of LCD_START field. + LCD_CAM_LCD_USER_LCD_START_Msk = 0x8000000 + // Bit LCD_START. + LCD_CAM_LCD_USER_LCD_START = 0x8000000 + // Position of LCD_RESET field. + LCD_CAM_LCD_USER_LCD_RESET_Pos = 0x1c + // Bit mask of LCD_RESET field. + LCD_CAM_LCD_USER_LCD_RESET_Msk = 0x10000000 + // Bit LCD_RESET. + LCD_CAM_LCD_USER_LCD_RESET = 0x10000000 + // Position of LCD_DUMMY_CYCLELEN field. + LCD_CAM_LCD_USER_LCD_DUMMY_CYCLELEN_Pos = 0x1d + // Bit mask of LCD_DUMMY_CYCLELEN field. + LCD_CAM_LCD_USER_LCD_DUMMY_CYCLELEN_Msk = 0x60000000 + // Position of LCD_CMD_2_CYCLE_EN field. + LCD_CAM_LCD_USER_LCD_CMD_2_CYCLE_EN_Pos = 0x1f + // Bit mask of LCD_CMD_2_CYCLE_EN field. + LCD_CAM_LCD_USER_LCD_CMD_2_CYCLE_EN_Msk = 0x80000000 + // Bit LCD_CMD_2_CYCLE_EN. + LCD_CAM_LCD_USER_LCD_CMD_2_CYCLE_EN = 0x80000000 + + // LCD_MISC: LCD configuration register + // Position of LCD_AFIFO_THRESHOLD_NUM field. + LCD_CAM_LCD_MISC_LCD_AFIFO_THRESHOLD_NUM_Pos = 0x1 + // Bit mask of LCD_AFIFO_THRESHOLD_NUM field. + LCD_CAM_LCD_MISC_LCD_AFIFO_THRESHOLD_NUM_Msk = 0x3e + // Position of LCD_VFK_CYCLELEN field. + LCD_CAM_LCD_MISC_LCD_VFK_CYCLELEN_Pos = 0x6 + // Bit mask of LCD_VFK_CYCLELEN field. + LCD_CAM_LCD_MISC_LCD_VFK_CYCLELEN_Msk = 0xfc0 + // Position of LCD_VBK_CYCLELEN field. + LCD_CAM_LCD_MISC_LCD_VBK_CYCLELEN_Pos = 0xc + // Bit mask of LCD_VBK_CYCLELEN field. + LCD_CAM_LCD_MISC_LCD_VBK_CYCLELEN_Msk = 0x1fff000 + // Position of LCD_NEXT_FRAME_EN field. + LCD_CAM_LCD_MISC_LCD_NEXT_FRAME_EN_Pos = 0x19 + // Bit mask of LCD_NEXT_FRAME_EN field. + LCD_CAM_LCD_MISC_LCD_NEXT_FRAME_EN_Msk = 0x2000000 + // Bit LCD_NEXT_FRAME_EN. + LCD_CAM_LCD_MISC_LCD_NEXT_FRAME_EN = 0x2000000 + // Position of LCD_BK_EN field. + LCD_CAM_LCD_MISC_LCD_BK_EN_Pos = 0x1a + // Bit mask of LCD_BK_EN field. + LCD_CAM_LCD_MISC_LCD_BK_EN_Msk = 0x4000000 + // Bit LCD_BK_EN. + LCD_CAM_LCD_MISC_LCD_BK_EN = 0x4000000 + // Position of LCD_AFIFO_RESET field. + LCD_CAM_LCD_MISC_LCD_AFIFO_RESET_Pos = 0x1b + // Bit mask of LCD_AFIFO_RESET field. + LCD_CAM_LCD_MISC_LCD_AFIFO_RESET_Msk = 0x8000000 + // Bit LCD_AFIFO_RESET. + LCD_CAM_LCD_MISC_LCD_AFIFO_RESET = 0x8000000 + // Position of LCD_CD_DATA_SET field. + LCD_CAM_LCD_MISC_LCD_CD_DATA_SET_Pos = 0x1c + // Bit mask of LCD_CD_DATA_SET field. + LCD_CAM_LCD_MISC_LCD_CD_DATA_SET_Msk = 0x10000000 + // Bit LCD_CD_DATA_SET. + LCD_CAM_LCD_MISC_LCD_CD_DATA_SET = 0x10000000 + // Position of LCD_CD_DUMMY_SET field. + LCD_CAM_LCD_MISC_LCD_CD_DUMMY_SET_Pos = 0x1d + // Bit mask of LCD_CD_DUMMY_SET field. + LCD_CAM_LCD_MISC_LCD_CD_DUMMY_SET_Msk = 0x20000000 + // Bit LCD_CD_DUMMY_SET. + LCD_CAM_LCD_MISC_LCD_CD_DUMMY_SET = 0x20000000 + // Position of LCD_CD_CMD_SET field. + LCD_CAM_LCD_MISC_LCD_CD_CMD_SET_Pos = 0x1e + // Bit mask of LCD_CD_CMD_SET field. + LCD_CAM_LCD_MISC_LCD_CD_CMD_SET_Msk = 0x40000000 + // Bit LCD_CD_CMD_SET. + LCD_CAM_LCD_MISC_LCD_CD_CMD_SET = 0x40000000 + // Position of LCD_CD_IDLE_EDGE field. + LCD_CAM_LCD_MISC_LCD_CD_IDLE_EDGE_Pos = 0x1f + // Bit mask of LCD_CD_IDLE_EDGE field. + LCD_CAM_LCD_MISC_LCD_CD_IDLE_EDGE_Msk = 0x80000000 + // Bit LCD_CD_IDLE_EDGE. + LCD_CAM_LCD_MISC_LCD_CD_IDLE_EDGE = 0x80000000 + + // LCD_CTRL: LCD configuration register + // Position of LCD_HB_FRONT field. + LCD_CAM_LCD_CTRL_LCD_HB_FRONT_Pos = 0x0 + // Bit mask of LCD_HB_FRONT field. + LCD_CAM_LCD_CTRL_LCD_HB_FRONT_Msk = 0x7ff + // Position of LCD_VA_HEIGHT field. + LCD_CAM_LCD_CTRL_LCD_VA_HEIGHT_Pos = 0xb + // Bit mask of LCD_VA_HEIGHT field. + LCD_CAM_LCD_CTRL_LCD_VA_HEIGHT_Msk = 0x1ff800 + // Position of LCD_VT_HEIGHT field. + LCD_CAM_LCD_CTRL_LCD_VT_HEIGHT_Pos = 0x15 + // Bit mask of LCD_VT_HEIGHT field. + LCD_CAM_LCD_CTRL_LCD_VT_HEIGHT_Msk = 0x7fe00000 + // Position of LCD_RGB_MODE_EN field. + LCD_CAM_LCD_CTRL_LCD_RGB_MODE_EN_Pos = 0x1f + // Bit mask of LCD_RGB_MODE_EN field. + LCD_CAM_LCD_CTRL_LCD_RGB_MODE_EN_Msk = 0x80000000 + // Bit LCD_RGB_MODE_EN. + LCD_CAM_LCD_CTRL_LCD_RGB_MODE_EN = 0x80000000 + + // LCD_CTRL1: LCD configuration register + // Position of LCD_VB_FRONT field. + LCD_CAM_LCD_CTRL1_LCD_VB_FRONT_Pos = 0x0 + // Bit mask of LCD_VB_FRONT field. + LCD_CAM_LCD_CTRL1_LCD_VB_FRONT_Msk = 0xff + // Position of LCD_HA_WIDTH field. + LCD_CAM_LCD_CTRL1_LCD_HA_WIDTH_Pos = 0x8 + // Bit mask of LCD_HA_WIDTH field. + LCD_CAM_LCD_CTRL1_LCD_HA_WIDTH_Msk = 0xfff00 + // Position of LCD_HT_WIDTH field. + LCD_CAM_LCD_CTRL1_LCD_HT_WIDTH_Pos = 0x14 + // Bit mask of LCD_HT_WIDTH field. + LCD_CAM_LCD_CTRL1_LCD_HT_WIDTH_Msk = 0xfff00000 + + // LCD_CTRL2: LCD configuration register + // Position of LCD_VSYNC_WIDTH field. + LCD_CAM_LCD_CTRL2_LCD_VSYNC_WIDTH_Pos = 0x0 + // Bit mask of LCD_VSYNC_WIDTH field. + LCD_CAM_LCD_CTRL2_LCD_VSYNC_WIDTH_Msk = 0x7f + // Position of LCD_VSYNC_IDLE_POL field. + LCD_CAM_LCD_CTRL2_LCD_VSYNC_IDLE_POL_Pos = 0x7 + // Bit mask of LCD_VSYNC_IDLE_POL field. + LCD_CAM_LCD_CTRL2_LCD_VSYNC_IDLE_POL_Msk = 0x80 + // Bit LCD_VSYNC_IDLE_POL. + LCD_CAM_LCD_CTRL2_LCD_VSYNC_IDLE_POL = 0x80 + // Position of LCD_DE_IDLE_POL field. + LCD_CAM_LCD_CTRL2_LCD_DE_IDLE_POL_Pos = 0x8 + // Bit mask of LCD_DE_IDLE_POL field. + LCD_CAM_LCD_CTRL2_LCD_DE_IDLE_POL_Msk = 0x100 + // Bit LCD_DE_IDLE_POL. + LCD_CAM_LCD_CTRL2_LCD_DE_IDLE_POL = 0x100 + // Position of LCD_HS_BLANK_EN field. + LCD_CAM_LCD_CTRL2_LCD_HS_BLANK_EN_Pos = 0x9 + // Bit mask of LCD_HS_BLANK_EN field. + LCD_CAM_LCD_CTRL2_LCD_HS_BLANK_EN_Msk = 0x200 + // Bit LCD_HS_BLANK_EN. + LCD_CAM_LCD_CTRL2_LCD_HS_BLANK_EN = 0x200 + // Position of LCD_HSYNC_WIDTH field. + LCD_CAM_LCD_CTRL2_LCD_HSYNC_WIDTH_Pos = 0x10 + // Bit mask of LCD_HSYNC_WIDTH field. + LCD_CAM_LCD_CTRL2_LCD_HSYNC_WIDTH_Msk = 0x7f0000 + // Position of LCD_HSYNC_IDLE_POL field. + LCD_CAM_LCD_CTRL2_LCD_HSYNC_IDLE_POL_Pos = 0x17 + // Bit mask of LCD_HSYNC_IDLE_POL field. + LCD_CAM_LCD_CTRL2_LCD_HSYNC_IDLE_POL_Msk = 0x800000 + // Bit LCD_HSYNC_IDLE_POL. + LCD_CAM_LCD_CTRL2_LCD_HSYNC_IDLE_POL = 0x800000 + // Position of LCD_HSYNC_POSITION field. + LCD_CAM_LCD_CTRL2_LCD_HSYNC_POSITION_Pos = 0x18 + // Bit mask of LCD_HSYNC_POSITION field. + LCD_CAM_LCD_CTRL2_LCD_HSYNC_POSITION_Msk = 0xff000000 + + // LCD_CMD_VAL: LCD configuration register + // Position of LCD_CMD_VALUE field. + LCD_CAM_LCD_CMD_VAL_LCD_CMD_VALUE_Pos = 0x0 + // Bit mask of LCD_CMD_VALUE field. + LCD_CAM_LCD_CMD_VAL_LCD_CMD_VALUE_Msk = 0xffffffff + + // LCD_DLY_MODE: LCD configuration register + // Position of LCD_CD_MODE field. + LCD_CAM_LCD_DLY_MODE_LCD_CD_MODE_Pos = 0x0 + // Bit mask of LCD_CD_MODE field. + LCD_CAM_LCD_DLY_MODE_LCD_CD_MODE_Msk = 0x3 + // Position of LCD_DE_MODE field. + LCD_CAM_LCD_DLY_MODE_LCD_DE_MODE_Pos = 0x2 + // Bit mask of LCD_DE_MODE field. + LCD_CAM_LCD_DLY_MODE_LCD_DE_MODE_Msk = 0xc + // Position of LCD_HSYNC_MODE field. + LCD_CAM_LCD_DLY_MODE_LCD_HSYNC_MODE_Pos = 0x4 + // Bit mask of LCD_HSYNC_MODE field. + LCD_CAM_LCD_DLY_MODE_LCD_HSYNC_MODE_Msk = 0x30 + // Position of LCD_VSYNC_MODE field. + LCD_CAM_LCD_DLY_MODE_LCD_VSYNC_MODE_Pos = 0x6 + // Bit mask of LCD_VSYNC_MODE field. + LCD_CAM_LCD_DLY_MODE_LCD_VSYNC_MODE_Msk = 0xc0 + + // LCD_DATA_DOUT_MODE: LCD configuration register + // Position of DOUT0_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT0_MODE_Msk = 0x3 + // Position of DOUT1_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT1_MODE_Pos = 0x2 + // Bit mask of DOUT1_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT1_MODE_Msk = 0xc + // Position of DOUT2_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT2_MODE_Pos = 0x4 + // Bit mask of DOUT2_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT2_MODE_Msk = 0x30 + // Position of DOUT3_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT3_MODE_Pos = 0x6 + // Bit mask of DOUT3_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT3_MODE_Msk = 0xc0 + // Position of DOUT4_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT4_MODE_Pos = 0x8 + // Bit mask of DOUT4_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT4_MODE_Msk = 0x300 + // Position of DOUT5_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT5_MODE_Pos = 0xa + // Bit mask of DOUT5_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT5_MODE_Msk = 0xc00 + // Position of DOUT6_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT6_MODE_Pos = 0xc + // Bit mask of DOUT6_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT6_MODE_Msk = 0x3000 + // Position of DOUT7_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT7_MODE_Pos = 0xe + // Bit mask of DOUT7_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT7_MODE_Msk = 0xc000 + // Position of DOUT8_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT8_MODE_Pos = 0x10 + // Bit mask of DOUT8_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT8_MODE_Msk = 0x30000 + // Position of DOUT9_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT9_MODE_Pos = 0x12 + // Bit mask of DOUT9_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT9_MODE_Msk = 0xc0000 + // Position of DOUT10_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT10_MODE_Pos = 0x14 + // Bit mask of DOUT10_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT10_MODE_Msk = 0x300000 + // Position of DOUT11_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT11_MODE_Pos = 0x16 + // Bit mask of DOUT11_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT11_MODE_Msk = 0xc00000 + // Position of DOUT12_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT12_MODE_Pos = 0x18 + // Bit mask of DOUT12_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT12_MODE_Msk = 0x3000000 + // Position of DOUT13_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT13_MODE_Pos = 0x1a + // Bit mask of DOUT13_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT13_MODE_Msk = 0xc000000 + // Position of DOUT14_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT14_MODE_Pos = 0x1c + // Bit mask of DOUT14_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT14_MODE_Msk = 0x30000000 + // Position of DOUT15_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT15_MODE_Pos = 0x1e + // Bit mask of DOUT15_MODE field. + LCD_CAM_LCD_DATA_DOUT_MODE_DOUT15_MODE_Msk = 0xc0000000 + + // LC_DMA_INT_ENA: LCD_camera DMA inturrupt enable register + // Position of LCD_VSYNC_INT_ENA field. + LCD_CAM_LC_DMA_INT_ENA_LCD_VSYNC_INT_ENA_Pos = 0x0 + // Bit mask of LCD_VSYNC_INT_ENA field. + LCD_CAM_LC_DMA_INT_ENA_LCD_VSYNC_INT_ENA_Msk = 0x1 + // Bit LCD_VSYNC_INT_ENA. + LCD_CAM_LC_DMA_INT_ENA_LCD_VSYNC_INT_ENA = 0x1 + // Position of LCD_TRANS_DONE_INT_ENA field. + LCD_CAM_LC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA_Pos = 0x1 + // Bit mask of LCD_TRANS_DONE_INT_ENA field. + LCD_CAM_LC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA_Msk = 0x2 + // Bit LCD_TRANS_DONE_INT_ENA. + LCD_CAM_LC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA = 0x2 + // Position of CAM_VSYNC_INT_ENA field. + LCD_CAM_LC_DMA_INT_ENA_CAM_VSYNC_INT_ENA_Pos = 0x2 + // Bit mask of CAM_VSYNC_INT_ENA field. + LCD_CAM_LC_DMA_INT_ENA_CAM_VSYNC_INT_ENA_Msk = 0x4 + // Bit CAM_VSYNC_INT_ENA. + LCD_CAM_LC_DMA_INT_ENA_CAM_VSYNC_INT_ENA = 0x4 + // Position of CAM_HS_INT_ENA field. + LCD_CAM_LC_DMA_INT_ENA_CAM_HS_INT_ENA_Pos = 0x3 + // Bit mask of CAM_HS_INT_ENA field. + LCD_CAM_LC_DMA_INT_ENA_CAM_HS_INT_ENA_Msk = 0x8 + // Bit CAM_HS_INT_ENA. + LCD_CAM_LC_DMA_INT_ENA_CAM_HS_INT_ENA = 0x8 + + // LC_DMA_INT_RAW: LCD_camera DMA raw inturrupt status register + // Position of LCD_VSYNC_INT_RAW field. + LCD_CAM_LC_DMA_INT_RAW_LCD_VSYNC_INT_RAW_Pos = 0x0 + // Bit mask of LCD_VSYNC_INT_RAW field. + LCD_CAM_LC_DMA_INT_RAW_LCD_VSYNC_INT_RAW_Msk = 0x1 + // Bit LCD_VSYNC_INT_RAW. + LCD_CAM_LC_DMA_INT_RAW_LCD_VSYNC_INT_RAW = 0x1 + // Position of LCD_TRANS_DONE_INT_RAW field. + LCD_CAM_LC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW_Pos = 0x1 + // Bit mask of LCD_TRANS_DONE_INT_RAW field. + LCD_CAM_LC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW_Msk = 0x2 + // Bit LCD_TRANS_DONE_INT_RAW. + LCD_CAM_LC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW = 0x2 + // Position of CAM_VSYNC_INT_RAW field. + LCD_CAM_LC_DMA_INT_RAW_CAM_VSYNC_INT_RAW_Pos = 0x2 + // Bit mask of CAM_VSYNC_INT_RAW field. + LCD_CAM_LC_DMA_INT_RAW_CAM_VSYNC_INT_RAW_Msk = 0x4 + // Bit CAM_VSYNC_INT_RAW. + LCD_CAM_LC_DMA_INT_RAW_CAM_VSYNC_INT_RAW = 0x4 + // Position of CAM_HS_INT_RAW field. + LCD_CAM_LC_DMA_INT_RAW_CAM_HS_INT_RAW_Pos = 0x3 + // Bit mask of CAM_HS_INT_RAW field. + LCD_CAM_LC_DMA_INT_RAW_CAM_HS_INT_RAW_Msk = 0x8 + // Bit CAM_HS_INT_RAW. + LCD_CAM_LC_DMA_INT_RAW_CAM_HS_INT_RAW = 0x8 + + // LC_DMA_INT_ST: LCD_camera DMA masked inturrupt status register + // Position of LCD_VSYNC_INT_ST field. + LCD_CAM_LC_DMA_INT_ST_LCD_VSYNC_INT_ST_Pos = 0x0 + // Bit mask of LCD_VSYNC_INT_ST field. + LCD_CAM_LC_DMA_INT_ST_LCD_VSYNC_INT_ST_Msk = 0x1 + // Bit LCD_VSYNC_INT_ST. + LCD_CAM_LC_DMA_INT_ST_LCD_VSYNC_INT_ST = 0x1 + // Position of LCD_TRANS_DONE_INT_ST field. + LCD_CAM_LC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST_Pos = 0x1 + // Bit mask of LCD_TRANS_DONE_INT_ST field. + LCD_CAM_LC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST_Msk = 0x2 + // Bit LCD_TRANS_DONE_INT_ST. + LCD_CAM_LC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST = 0x2 + // Position of CAM_VSYNC_INT_ST field. + LCD_CAM_LC_DMA_INT_ST_CAM_VSYNC_INT_ST_Pos = 0x2 + // Bit mask of CAM_VSYNC_INT_ST field. + LCD_CAM_LC_DMA_INT_ST_CAM_VSYNC_INT_ST_Msk = 0x4 + // Bit CAM_VSYNC_INT_ST. + LCD_CAM_LC_DMA_INT_ST_CAM_VSYNC_INT_ST = 0x4 + // Position of CAM_HS_INT_ST field. + LCD_CAM_LC_DMA_INT_ST_CAM_HS_INT_ST_Pos = 0x3 + // Bit mask of CAM_HS_INT_ST field. + LCD_CAM_LC_DMA_INT_ST_CAM_HS_INT_ST_Msk = 0x8 + // Bit CAM_HS_INT_ST. + LCD_CAM_LC_DMA_INT_ST_CAM_HS_INT_ST = 0x8 + + // LC_DMA_INT_CLR: LCD_camera DMA inturrupt clear register + // Position of LCD_VSYNC_INT_CLR field. + LCD_CAM_LC_DMA_INT_CLR_LCD_VSYNC_INT_CLR_Pos = 0x0 + // Bit mask of LCD_VSYNC_INT_CLR field. + LCD_CAM_LC_DMA_INT_CLR_LCD_VSYNC_INT_CLR_Msk = 0x1 + // Bit LCD_VSYNC_INT_CLR. + LCD_CAM_LC_DMA_INT_CLR_LCD_VSYNC_INT_CLR = 0x1 + // Position of LCD_TRANS_DONE_INT_CLR field. + LCD_CAM_LC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR_Pos = 0x1 + // Bit mask of LCD_TRANS_DONE_INT_CLR field. + LCD_CAM_LC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR_Msk = 0x2 + // Bit LCD_TRANS_DONE_INT_CLR. + LCD_CAM_LC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR = 0x2 + // Position of CAM_VSYNC_INT_CLR field. + LCD_CAM_LC_DMA_INT_CLR_CAM_VSYNC_INT_CLR_Pos = 0x2 + // Bit mask of CAM_VSYNC_INT_CLR field. + LCD_CAM_LC_DMA_INT_CLR_CAM_VSYNC_INT_CLR_Msk = 0x4 + // Bit CAM_VSYNC_INT_CLR. + LCD_CAM_LC_DMA_INT_CLR_CAM_VSYNC_INT_CLR = 0x4 + // Position of CAM_HS_INT_CLR field. + LCD_CAM_LC_DMA_INT_CLR_CAM_HS_INT_CLR_Pos = 0x3 + // Bit mask of CAM_HS_INT_CLR field. + LCD_CAM_LC_DMA_INT_CLR_CAM_HS_INT_CLR_Msk = 0x8 + // Bit CAM_HS_INT_CLR. + LCD_CAM_LC_DMA_INT_CLR_CAM_HS_INT_CLR = 0x8 + + // LC_REG_DATE: Version register + // Position of LC_DATE field. + LCD_CAM_LC_REG_DATE_LC_DATE_Pos = 0x0 + // Bit mask of LC_DATE field. + LCD_CAM_LC_REG_DATE_LC_DATE_Msk = 0xfffffff +) + +// Constants for LEDC: LED Control PWM (Pulse Width Modulation) +const ( + // CH0_CONF0: Configuration register 0 for channel %s + // Position of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Pos = 0x0 + // Bit mask of TIMER_SEL field. + LEDC_CH_CONF0_TIMER_SEL_Msk = 0x3 + // Position of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Pos = 0x2 + // Bit mask of SIG_OUT_EN field. + LEDC_CH_CONF0_SIG_OUT_EN_Msk = 0x4 + // Bit SIG_OUT_EN. + LEDC_CH_CONF0_SIG_OUT_EN = 0x4 + // Position of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Pos = 0x3 + // Bit mask of IDLE_LV field. + LEDC_CH_CONF0_IDLE_LV_Msk = 0x8 + // Bit IDLE_LV. + LEDC_CH_CONF0_IDLE_LV = 0x8 + // Position of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Pos = 0x4 + // Bit mask of PARA_UP field. + LEDC_CH_CONF0_PARA_UP_Msk = 0x10 + // Bit PARA_UP. + LEDC_CH_CONF0_PARA_UP = 0x10 + // Position of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Pos = 0x5 + // Bit mask of OVF_NUM field. + LEDC_CH_CONF0_OVF_NUM_Msk = 0x7fe0 + // Position of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Pos = 0xf + // Bit mask of OVF_CNT_EN field. + LEDC_CH_CONF0_OVF_CNT_EN_Msk = 0x8000 + // Bit OVF_CNT_EN. + LEDC_CH_CONF0_OVF_CNT_EN = 0x8000 + // Position of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Pos = 0x10 + // Bit mask of OVF_CNT_RESET field. + LEDC_CH_CONF0_OVF_CNT_RESET_Msk = 0x10000 + // Bit OVF_CNT_RESET. + LEDC_CH_CONF0_OVF_CNT_RESET = 0x10000 + // Position of OVF_CNT_RESET_ST field. + LEDC_CH_CONF0_OVF_CNT_RESET_ST_Pos = 0x11 + // Bit mask of OVF_CNT_RESET_ST field. + LEDC_CH_CONF0_OVF_CNT_RESET_ST_Msk = 0x20000 + // Bit OVF_CNT_RESET_ST. + LEDC_CH_CONF0_OVF_CNT_RESET_ST = 0x20000 + + // CH0_HPOINT: High point register for channel %s + // Position of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Pos = 0x0 + // Bit mask of HPOINT field. + LEDC_CH_HPOINT_HPOINT_Msk = 0x3fff + + // CH0_DUTY: Initial duty cycle for channel %s + // Position of DUTY field. + LEDC_CH_DUTY_DUTY_Pos = 0x0 + // Bit mask of DUTY field. + LEDC_CH_DUTY_DUTY_Msk = 0x7ffff + + // CH0_CONF1: Configuration register 1 for channel %s + // Position of DUTY_SCALE field. + LEDC_CH_CONF1_DUTY_SCALE_Pos = 0x0 + // Bit mask of DUTY_SCALE field. + LEDC_CH_CONF1_DUTY_SCALE_Msk = 0x3ff + // Position of DUTY_CYCLE field. + LEDC_CH_CONF1_DUTY_CYCLE_Pos = 0xa + // Bit mask of DUTY_CYCLE field. + LEDC_CH_CONF1_DUTY_CYCLE_Msk = 0xffc00 + // Position of DUTY_NUM field. + LEDC_CH_CONF1_DUTY_NUM_Pos = 0x14 + // Bit mask of DUTY_NUM field. + LEDC_CH_CONF1_DUTY_NUM_Msk = 0x3ff00000 + // Position of DUTY_INC field. + LEDC_CH_CONF1_DUTY_INC_Pos = 0x1e + // Bit mask of DUTY_INC field. + LEDC_CH_CONF1_DUTY_INC_Msk = 0x40000000 + // Bit DUTY_INC. + LEDC_CH_CONF1_DUTY_INC = 0x40000000 + // Position of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Pos = 0x1f + // Bit mask of DUTY_START field. + LEDC_CH_CONF1_DUTY_START_Msk = 0x80000000 + // Bit DUTY_START. + LEDC_CH_CONF1_DUTY_START = 0x80000000 + + // CH0_DUTY_R: Current duty cycle for channel %s + // Position of DUTY_R field. + LEDC_CH_DUTY_R_DUTY_R_Pos = 0x0 + // Bit mask of DUTY_R field. + LEDC_CH_DUTY_R_DUTY_R_Msk = 0x7ffff + + // TIMER0_CONF: Timer %s configuration + // Position of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Pos = 0x0 + // Bit mask of DUTY_RES field. + LEDC_TIMER_CONF_DUTY_RES_Msk = 0xf + // Position of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Pos = 0x4 + // Bit mask of CLK_DIV field. + LEDC_TIMER_CONF_CLK_DIV_Msk = 0x3ffff0 + // Position of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Pos = 0x16 + // Bit mask of PAUSE field. + LEDC_TIMER_CONF_PAUSE_Msk = 0x400000 + // Bit PAUSE. + LEDC_TIMER_CONF_PAUSE = 0x400000 + // Position of RST field. + LEDC_TIMER_CONF_RST_Pos = 0x17 + // Bit mask of RST field. + LEDC_TIMER_CONF_RST_Msk = 0x800000 + // Bit RST. + LEDC_TIMER_CONF_RST = 0x800000 + // Position of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Pos = 0x18 + // Bit mask of TICK_SEL field. + LEDC_TIMER_CONF_TICK_SEL_Msk = 0x1000000 + // Bit TICK_SEL. + LEDC_TIMER_CONF_TICK_SEL = 0x1000000 + // Position of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Pos = 0x19 + // Bit mask of PARA_UP field. + LEDC_TIMER_CONF_PARA_UP_Msk = 0x2000000 + // Bit PARA_UP. + LEDC_TIMER_CONF_PARA_UP = 0x2000000 + + // TIMER0_VALUE: Timer %s current counter value + // Position of CNT field. + LEDC_TIMER_VALUE_CNT_Pos = 0x0 + // Bit mask of CNT field. + LEDC_TIMER_VALUE_CNT_Msk = 0x3fff + + // INT_RAW: Raw interrupt status + // Position of TIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Msk = 0x1 + // Bit TIMER0_OVF_INT_RAW. + LEDC_INT_RAW_TIMER0_OVF_INT_RAW = 0x1 + // Position of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Msk = 0x2 + // Bit TIMER1_OVF_INT_RAW. + LEDC_INT_RAW_TIMER1_OVF_INT_RAW = 0x2 + // Position of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Msk = 0x4 + // Bit TIMER2_OVF_INT_RAW. + LEDC_INT_RAW_TIMER2_OVF_INT_RAW = 0x4 + // Position of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_RAW field. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Msk = 0x8 + // Bit TIMER3_OVF_INT_RAW. + LEDC_INT_RAW_TIMER3_OVF_INT_RAW = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW = 0x200 + // Position of DUTY_CHNG_END_CH6_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH6_INT_RAW_Pos = 0xa + // Bit mask of DUTY_CHNG_END_CH6_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH6_INT_RAW_Msk = 0x400 + // Bit DUTY_CHNG_END_CH6_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH6_INT_RAW = 0x400 + // Position of DUTY_CHNG_END_CH7_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH7_INT_RAW_Pos = 0xb + // Bit mask of DUTY_CHNG_END_CH7_INT_RAW field. + LEDC_INT_RAW_DUTY_CHNG_END_CH7_INT_RAW_Msk = 0x800 + // Bit DUTY_CHNG_END_CH7_INT_RAW. + LEDC_INT_RAW_DUTY_CHNG_END_CH7_INT_RAW = 0x800 + // Position of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW = 0x1000 + // Position of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW = 0x2000 + // Position of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW = 0x4000 + // Position of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW = 0x8000 + // Position of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW = 0x10000 + // Position of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW = 0x20000 + // Position of OVF_CNT_CH6_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH6_INT_RAW_Pos = 0x12 + // Bit mask of OVF_CNT_CH6_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH6_INT_RAW_Msk = 0x40000 + // Bit OVF_CNT_CH6_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH6_INT_RAW = 0x40000 + // Position of OVF_CNT_CH7_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH7_INT_RAW_Pos = 0x13 + // Bit mask of OVF_CNT_CH7_INT_RAW field. + LEDC_INT_RAW_OVF_CNT_CH7_INT_RAW_Msk = 0x80000 + // Bit OVF_CNT_CH7_INT_RAW. + LEDC_INT_RAW_OVF_CNT_CH7_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of TIMER0_OVF_INT_ST field. + LEDC_INT_ST_TIMER0_OVF_INT_ST_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_ST field. + LEDC_INT_ST_TIMER0_OVF_INT_ST_Msk = 0x1 + // Bit TIMER0_OVF_INT_ST. + LEDC_INT_ST_TIMER0_OVF_INT_ST = 0x1 + // Position of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ST field. + LEDC_INT_ST_TIMER1_OVF_INT_ST_Msk = 0x2 + // Bit TIMER1_OVF_INT_ST. + LEDC_INT_ST_TIMER1_OVF_INT_ST = 0x2 + // Position of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ST field. + LEDC_INT_ST_TIMER2_OVF_INT_ST_Msk = 0x4 + // Bit TIMER2_OVF_INT_ST. + LEDC_INT_ST_TIMER2_OVF_INT_ST = 0x4 + // Position of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ST field. + LEDC_INT_ST_TIMER3_OVF_INT_ST_Msk = 0x8 + // Bit TIMER3_OVF_INT_ST. + LEDC_INT_ST_TIMER3_OVF_INT_ST = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST = 0x200 + // Position of DUTY_CHNG_END_CH6_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH6_INT_ST_Pos = 0xa + // Bit mask of DUTY_CHNG_END_CH6_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH6_INT_ST_Msk = 0x400 + // Bit DUTY_CHNG_END_CH6_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH6_INT_ST = 0x400 + // Position of DUTY_CHNG_END_CH7_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH7_INT_ST_Pos = 0xb + // Bit mask of DUTY_CHNG_END_CH7_INT_ST field. + LEDC_INT_ST_DUTY_CHNG_END_CH7_INT_ST_Msk = 0x800 + // Bit DUTY_CHNG_END_CH7_INT_ST. + LEDC_INT_ST_DUTY_CHNG_END_CH7_INT_ST = 0x800 + // Position of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_ST. + LEDC_INT_ST_OVF_CNT_CH0_INT_ST = 0x1000 + // Position of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_ST. + LEDC_INT_ST_OVF_CNT_CH1_INT_ST = 0x2000 + // Position of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_ST. + LEDC_INT_ST_OVF_CNT_CH2_INT_ST = 0x4000 + // Position of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_ST. + LEDC_INT_ST_OVF_CNT_CH3_INT_ST = 0x8000 + // Position of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_ST. + LEDC_INT_ST_OVF_CNT_CH4_INT_ST = 0x10000 + // Position of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_ST. + LEDC_INT_ST_OVF_CNT_CH5_INT_ST = 0x20000 + // Position of OVF_CNT_CH6_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH6_INT_ST_Pos = 0x12 + // Bit mask of OVF_CNT_CH6_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH6_INT_ST_Msk = 0x40000 + // Bit OVF_CNT_CH6_INT_ST. + LEDC_INT_ST_OVF_CNT_CH6_INT_ST = 0x40000 + // Position of OVF_CNT_CH7_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH7_INT_ST_Pos = 0x13 + // Bit mask of OVF_CNT_CH7_INT_ST field. + LEDC_INT_ST_OVF_CNT_CH7_INT_ST_Msk = 0x80000 + // Bit OVF_CNT_CH7_INT_ST. + LEDC_INT_ST_OVF_CNT_CH7_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of TIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Msk = 0x1 + // Bit TIMER0_OVF_INT_ENA. + LEDC_INT_ENA_TIMER0_OVF_INT_ENA = 0x1 + // Position of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Msk = 0x2 + // Bit TIMER1_OVF_INT_ENA. + LEDC_INT_ENA_TIMER1_OVF_INT_ENA = 0x2 + // Position of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Msk = 0x4 + // Bit TIMER2_OVF_INT_ENA. + LEDC_INT_ENA_TIMER2_OVF_INT_ENA = 0x4 + // Position of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_ENA field. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Msk = 0x8 + // Bit TIMER3_OVF_INT_ENA. + LEDC_INT_ENA_TIMER3_OVF_INT_ENA = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA = 0x200 + // Position of DUTY_CHNG_END_CH6_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH6_INT_ENA_Pos = 0xa + // Bit mask of DUTY_CHNG_END_CH6_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH6_INT_ENA_Msk = 0x400 + // Bit DUTY_CHNG_END_CH6_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH6_INT_ENA = 0x400 + // Position of DUTY_CHNG_END_CH7_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH7_INT_ENA_Pos = 0xb + // Bit mask of DUTY_CHNG_END_CH7_INT_ENA field. + LEDC_INT_ENA_DUTY_CHNG_END_CH7_INT_ENA_Msk = 0x800 + // Bit DUTY_CHNG_END_CH7_INT_ENA. + LEDC_INT_ENA_DUTY_CHNG_END_CH7_INT_ENA = 0x800 + // Position of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA = 0x1000 + // Position of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA = 0x2000 + // Position of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA = 0x4000 + // Position of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA = 0x8000 + // Position of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA = 0x10000 + // Position of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA = 0x20000 + // Position of OVF_CNT_CH6_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH6_INT_ENA_Pos = 0x12 + // Bit mask of OVF_CNT_CH6_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH6_INT_ENA_Msk = 0x40000 + // Bit OVF_CNT_CH6_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH6_INT_ENA = 0x40000 + // Position of OVF_CNT_CH7_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH7_INT_ENA_Pos = 0x13 + // Bit mask of OVF_CNT_CH7_INT_ENA field. + LEDC_INT_ENA_OVF_CNT_CH7_INT_ENA_Msk = 0x80000 + // Bit OVF_CNT_CH7_INT_ENA. + LEDC_INT_ENA_OVF_CNT_CH7_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of TIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Pos = 0x0 + // Bit mask of TIMER0_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Msk = 0x1 + // Bit TIMER0_OVF_INT_CLR. + LEDC_INT_CLR_TIMER0_OVF_INT_CLR = 0x1 + // Position of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Pos = 0x1 + // Bit mask of TIMER1_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Msk = 0x2 + // Bit TIMER1_OVF_INT_CLR. + LEDC_INT_CLR_TIMER1_OVF_INT_CLR = 0x2 + // Position of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Pos = 0x2 + // Bit mask of TIMER2_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Msk = 0x4 + // Bit TIMER2_OVF_INT_CLR. + LEDC_INT_CLR_TIMER2_OVF_INT_CLR = 0x4 + // Position of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Pos = 0x3 + // Bit mask of TIMER3_OVF_INT_CLR field. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Msk = 0x8 + // Bit TIMER3_OVF_INT_CLR. + LEDC_INT_CLR_TIMER3_OVF_INT_CLR = 0x8 + // Position of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Pos = 0x4 + // Bit mask of DUTY_CHNG_END_CH0_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Msk = 0x10 + // Bit DUTY_CHNG_END_CH0_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR = 0x10 + // Position of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Pos = 0x5 + // Bit mask of DUTY_CHNG_END_CH1_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Msk = 0x20 + // Bit DUTY_CHNG_END_CH1_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR = 0x20 + // Position of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Pos = 0x6 + // Bit mask of DUTY_CHNG_END_CH2_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Msk = 0x40 + // Bit DUTY_CHNG_END_CH2_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR = 0x40 + // Position of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Pos = 0x7 + // Bit mask of DUTY_CHNG_END_CH3_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Msk = 0x80 + // Bit DUTY_CHNG_END_CH3_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR = 0x80 + // Position of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Pos = 0x8 + // Bit mask of DUTY_CHNG_END_CH4_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Msk = 0x100 + // Bit DUTY_CHNG_END_CH4_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR = 0x100 + // Position of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Pos = 0x9 + // Bit mask of DUTY_CHNG_END_CH5_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Msk = 0x200 + // Bit DUTY_CHNG_END_CH5_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR = 0x200 + // Position of DUTY_CHNG_END_CH6_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH6_INT_CLR_Pos = 0xa + // Bit mask of DUTY_CHNG_END_CH6_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH6_INT_CLR_Msk = 0x400 + // Bit DUTY_CHNG_END_CH6_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH6_INT_CLR = 0x400 + // Position of DUTY_CHNG_END_CH7_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH7_INT_CLR_Pos = 0xb + // Bit mask of DUTY_CHNG_END_CH7_INT_CLR field. + LEDC_INT_CLR_DUTY_CHNG_END_CH7_INT_CLR_Msk = 0x800 + // Bit DUTY_CHNG_END_CH7_INT_CLR. + LEDC_INT_CLR_DUTY_CHNG_END_CH7_INT_CLR = 0x800 + // Position of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Pos = 0xc + // Bit mask of OVF_CNT_CH0_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Msk = 0x1000 + // Bit OVF_CNT_CH0_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR = 0x1000 + // Position of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Pos = 0xd + // Bit mask of OVF_CNT_CH1_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Msk = 0x2000 + // Bit OVF_CNT_CH1_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR = 0x2000 + // Position of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Pos = 0xe + // Bit mask of OVF_CNT_CH2_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Msk = 0x4000 + // Bit OVF_CNT_CH2_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR = 0x4000 + // Position of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Pos = 0xf + // Bit mask of OVF_CNT_CH3_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Msk = 0x8000 + // Bit OVF_CNT_CH3_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR = 0x8000 + // Position of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Pos = 0x10 + // Bit mask of OVF_CNT_CH4_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Msk = 0x10000 + // Bit OVF_CNT_CH4_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR = 0x10000 + // Position of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Pos = 0x11 + // Bit mask of OVF_CNT_CH5_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Msk = 0x20000 + // Bit OVF_CNT_CH5_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR = 0x20000 + // Position of OVF_CNT_CH6_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH6_INT_CLR_Pos = 0x12 + // Bit mask of OVF_CNT_CH6_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH6_INT_CLR_Msk = 0x40000 + // Bit OVF_CNT_CH6_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH6_INT_CLR = 0x40000 + // Position of OVF_CNT_CH7_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH7_INT_CLR_Pos = 0x13 + // Bit mask of OVF_CNT_CH7_INT_CLR field. + LEDC_INT_CLR_OVF_CNT_CH7_INT_CLR_Msk = 0x80000 + // Bit OVF_CNT_CH7_INT_CLR. + LEDC_INT_CLR_OVF_CNT_CH7_INT_CLR = 0x80000 + + // CONF: Global ledc configuration register + // Position of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Pos = 0x0 + // Bit mask of APB_CLK_SEL field. + LEDC_CONF_APB_CLK_SEL_Msk = 0x3 + // Position of CLK_EN field. + LEDC_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + LEDC_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + LEDC_CONF_CLK_EN = 0x80000000 + + // DATE: Version control register + // Position of DATE field. + LEDC_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + LEDC_DATE_DATE_Msk = 0xffffffff +) + +// Constants for PCNT: Pulse Count Controller +const ( + // U0_CONF0: Configuration register 0 for unit %s + // Position of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Pos = 0x0 + // Bit mask of FILTER_THRES field. + PCNT_U_CONF0_FILTER_THRES_Msk = 0x3ff + // Position of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Pos = 0xa + // Bit mask of FILTER_EN field. + PCNT_U_CONF0_FILTER_EN_Msk = 0x400 + // Bit FILTER_EN. + PCNT_U_CONF0_FILTER_EN = 0x400 + // Position of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Pos = 0xb + // Bit mask of THR_ZERO_EN field. + PCNT_U_CONF0_THR_ZERO_EN_Msk = 0x800 + // Bit THR_ZERO_EN. + PCNT_U_CONF0_THR_ZERO_EN = 0x800 + // Position of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Pos = 0xc + // Bit mask of THR_H_LIM_EN field. + PCNT_U_CONF0_THR_H_LIM_EN_Msk = 0x1000 + // Bit THR_H_LIM_EN. + PCNT_U_CONF0_THR_H_LIM_EN = 0x1000 + // Position of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Pos = 0xd + // Bit mask of THR_L_LIM_EN field. + PCNT_U_CONF0_THR_L_LIM_EN_Msk = 0x2000 + // Bit THR_L_LIM_EN. + PCNT_U_CONF0_THR_L_LIM_EN = 0x2000 + // Position of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Pos = 0xe + // Bit mask of THR_THRES0_EN field. + PCNT_U_CONF0_THR_THRES0_EN_Msk = 0x4000 + // Bit THR_THRES0_EN. + PCNT_U_CONF0_THR_THRES0_EN = 0x4000 + // Position of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Pos = 0xf + // Bit mask of THR_THRES1_EN field. + PCNT_U_CONF0_THR_THRES1_EN_Msk = 0x8000 + // Bit THR_THRES1_EN. + PCNT_U_CONF0_THR_THRES1_EN = 0x8000 + // Position of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Pos = 0x10 + // Bit mask of CH0_NEG_MODE field. + PCNT_U_CONF0_CH0_NEG_MODE_Msk = 0x30000 + // Position of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Pos = 0x12 + // Bit mask of CH0_POS_MODE field. + PCNT_U_CONF0_CH0_POS_MODE_Msk = 0xc0000 + // Position of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Pos = 0x14 + // Bit mask of CH0_HCTRL_MODE field. + PCNT_U_CONF0_CH0_HCTRL_MODE_Msk = 0x300000 + // Position of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Pos = 0x16 + // Bit mask of CH0_LCTRL_MODE field. + PCNT_U_CONF0_CH0_LCTRL_MODE_Msk = 0xc00000 + // Position of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Pos = 0x18 + // Bit mask of CH1_NEG_MODE field. + PCNT_U_CONF0_CH1_NEG_MODE_Msk = 0x3000000 + // Position of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Pos = 0x1a + // Bit mask of CH1_POS_MODE field. + PCNT_U_CONF0_CH1_POS_MODE_Msk = 0xc000000 + // Position of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Pos = 0x1c + // Bit mask of CH1_HCTRL_MODE field. + PCNT_U_CONF0_CH1_HCTRL_MODE_Msk = 0x30000000 + // Position of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Pos = 0x1e + // Bit mask of CH1_LCTRL_MODE field. + PCNT_U_CONF0_CH1_LCTRL_MODE_Msk = 0xc0000000 + + // U0_CONF1: Configuration register 1 for unit %s + // Position of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Pos = 0x0 + // Bit mask of CNT_THRES0 field. + PCNT_U_CONF1_CNT_THRES0_Msk = 0xffff + // Position of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Pos = 0x10 + // Bit mask of CNT_THRES1 field. + PCNT_U_CONF1_CNT_THRES1_Msk = 0xffff0000 + + // U0_CONF2: Configuration register 2 for unit %s + // Position of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Pos = 0x0 + // Bit mask of CNT_H_LIM field. + PCNT_U_CONF2_CNT_H_LIM_Msk = 0xffff + // Position of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Pos = 0x10 + // Bit mask of CNT_L_LIM field. + PCNT_U_CONF2_CNT_L_LIM_Msk = 0xffff0000 + + // U0_CNT: Counter value for unit %s + // Position of CNT field. + PCNT_U_CNT_CNT_Pos = 0x0 + // Bit mask of CNT field. + PCNT_U_CNT_CNT_Msk = 0xffff + + // INT_RAW: Interrupt raw status register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_RAW_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_RAW_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_RAW_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_RAW_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_RAW_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_RAW_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_RAW_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_RAW_CNT_THR_EVENT_U3 = 0x8 + + // INT_ST: Interrupt status register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ST_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ST_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ST_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ST_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ST_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ST_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ST_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ST_CNT_THR_EVENT_U3 = 0x8 + + // INT_ENA: Interrupt enable register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_ENA_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_ENA_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_ENA_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_ENA_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_ENA_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_ENA_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_ENA_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_ENA_CNT_THR_EVENT_U3 = 0x8 + + // INT_CLR: Interrupt clear register + // Position of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Pos = 0x0 + // Bit mask of CNT_THR_EVENT_U0 field. + PCNT_INT_CLR_CNT_THR_EVENT_U0_Msk = 0x1 + // Bit CNT_THR_EVENT_U0. + PCNT_INT_CLR_CNT_THR_EVENT_U0 = 0x1 + // Position of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Pos = 0x1 + // Bit mask of CNT_THR_EVENT_U1 field. + PCNT_INT_CLR_CNT_THR_EVENT_U1_Msk = 0x2 + // Bit CNT_THR_EVENT_U1. + PCNT_INT_CLR_CNT_THR_EVENT_U1 = 0x2 + // Position of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Pos = 0x2 + // Bit mask of CNT_THR_EVENT_U2 field. + PCNT_INT_CLR_CNT_THR_EVENT_U2_Msk = 0x4 + // Bit CNT_THR_EVENT_U2. + PCNT_INT_CLR_CNT_THR_EVENT_U2 = 0x4 + // Position of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Pos = 0x3 + // Bit mask of CNT_THR_EVENT_U3 field. + PCNT_INT_CLR_CNT_THR_EVENT_U3_Msk = 0x8 + // Bit CNT_THR_EVENT_U3. + PCNT_INT_CLR_CNT_THR_EVENT_U3 = 0x8 + + // U0_STATUS: PNCT UNIT%s status register + // Position of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Pos = 0x0 + // Bit mask of ZERO_MODE field. + PCNT_U_STATUS_ZERO_MODE_Msk = 0x3 + // Position of THRES1 field. + PCNT_U_STATUS_THRES1_Pos = 0x2 + // Bit mask of THRES1 field. + PCNT_U_STATUS_THRES1_Msk = 0x4 + // Bit THRES1. + PCNT_U_STATUS_THRES1 = 0x4 + // Position of THRES0 field. + PCNT_U_STATUS_THRES0_Pos = 0x3 + // Bit mask of THRES0 field. + PCNT_U_STATUS_THRES0_Msk = 0x8 + // Bit THRES0. + PCNT_U_STATUS_THRES0 = 0x8 + // Position of L_LIM field. + PCNT_U_STATUS_L_LIM_Pos = 0x4 + // Bit mask of L_LIM field. + PCNT_U_STATUS_L_LIM_Msk = 0x10 + // Bit L_LIM. + PCNT_U_STATUS_L_LIM = 0x10 + // Position of H_LIM field. + PCNT_U_STATUS_H_LIM_Pos = 0x5 + // Bit mask of H_LIM field. + PCNT_U_STATUS_H_LIM_Msk = 0x20 + // Bit H_LIM. + PCNT_U_STATUS_H_LIM = 0x20 + // Position of ZERO field. + PCNT_U_STATUS_ZERO_Pos = 0x6 + // Bit mask of ZERO field. + PCNT_U_STATUS_ZERO_Msk = 0x40 + // Bit ZERO. + PCNT_U_STATUS_ZERO = 0x40 + + // CTRL: Control register for all counters + // Position of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Pos = 0x0 + // Bit mask of CNT_RST_U0 field. + PCNT_CTRL_CNT_RST_U0_Msk = 0x1 + // Bit CNT_RST_U0. + PCNT_CTRL_CNT_RST_U0 = 0x1 + // Position of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Pos = 0x1 + // Bit mask of CNT_PAUSE_U0 field. + PCNT_CTRL_CNT_PAUSE_U0_Msk = 0x2 + // Bit CNT_PAUSE_U0. + PCNT_CTRL_CNT_PAUSE_U0 = 0x2 + // Position of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Pos = 0x2 + // Bit mask of CNT_RST_U1 field. + PCNT_CTRL_CNT_RST_U1_Msk = 0x4 + // Bit CNT_RST_U1. + PCNT_CTRL_CNT_RST_U1 = 0x4 + // Position of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Pos = 0x3 + // Bit mask of CNT_PAUSE_U1 field. + PCNT_CTRL_CNT_PAUSE_U1_Msk = 0x8 + // Bit CNT_PAUSE_U1. + PCNT_CTRL_CNT_PAUSE_U1 = 0x8 + // Position of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Pos = 0x4 + // Bit mask of CNT_RST_U2 field. + PCNT_CTRL_CNT_RST_U2_Msk = 0x10 + // Bit CNT_RST_U2. + PCNT_CTRL_CNT_RST_U2 = 0x10 + // Position of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Pos = 0x5 + // Bit mask of CNT_PAUSE_U2 field. + PCNT_CTRL_CNT_PAUSE_U2_Msk = 0x20 + // Bit CNT_PAUSE_U2. + PCNT_CTRL_CNT_PAUSE_U2 = 0x20 + // Position of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Pos = 0x6 + // Bit mask of CNT_RST_U3 field. + PCNT_CTRL_CNT_RST_U3_Msk = 0x40 + // Bit CNT_RST_U3. + PCNT_CTRL_CNT_RST_U3 = 0x40 + // Position of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Pos = 0x7 + // Bit mask of CNT_PAUSE_U3 field. + PCNT_CTRL_CNT_PAUSE_U3_Msk = 0x80 + // Bit CNT_PAUSE_U3. + PCNT_CTRL_CNT_PAUSE_U3 = 0x80 + // Position of CLK_EN field. + PCNT_CTRL_CLK_EN_Pos = 0x10 + // Bit mask of CLK_EN field. + PCNT_CTRL_CLK_EN_Msk = 0x10000 + // Bit CLK_EN. + PCNT_CTRL_CLK_EN = 0x10000 + + // DATE: PCNT version control register + // Position of DATE field. + PCNT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PCNT_DATE_DATE_Msk = 0xffffffff +) + +// Constants for PERI_BACKUP: PERI_BACKUP Peripheral +const ( + // CONFIG: x + // Position of FLOW_ERR field. + PERI_BACKUP_CONFIG_FLOW_ERR_Pos = 0x0 + // Bit mask of FLOW_ERR field. + PERI_BACKUP_CONFIG_FLOW_ERR_Msk = 0x7 + // Position of ADDR_MAP_MODE field. + PERI_BACKUP_CONFIG_ADDR_MAP_MODE_Pos = 0x3 + // Bit mask of ADDR_MAP_MODE field. + PERI_BACKUP_CONFIG_ADDR_MAP_MODE_Msk = 0x8 + // Bit ADDR_MAP_MODE. + PERI_BACKUP_CONFIG_ADDR_MAP_MODE = 0x8 + // Position of BURST_LIMIT field. + PERI_BACKUP_CONFIG_BURST_LIMIT_Pos = 0x4 + // Bit mask of BURST_LIMIT field. + PERI_BACKUP_CONFIG_BURST_LIMIT_Msk = 0x1f0 + // Position of TOUT_THRES field. + PERI_BACKUP_CONFIG_TOUT_THRES_Pos = 0x9 + // Bit mask of TOUT_THRES field. + PERI_BACKUP_CONFIG_TOUT_THRES_Msk = 0x7fe00 + // Position of SIZE field. + PERI_BACKUP_CONFIG_SIZE_Pos = 0x13 + // Bit mask of SIZE field. + PERI_BACKUP_CONFIG_SIZE_Msk = 0x1ff80000 + // Position of START field. + PERI_BACKUP_CONFIG_START_Pos = 0x1d + // Bit mask of START field. + PERI_BACKUP_CONFIG_START_Msk = 0x20000000 + // Bit START. + PERI_BACKUP_CONFIG_START = 0x20000000 + // Position of TO_MEM field. + PERI_BACKUP_CONFIG_TO_MEM_Pos = 0x1e + // Bit mask of TO_MEM field. + PERI_BACKUP_CONFIG_TO_MEM_Msk = 0x40000000 + // Bit TO_MEM. + PERI_BACKUP_CONFIG_TO_MEM = 0x40000000 + // Position of ENA field. + PERI_BACKUP_CONFIG_ENA_Pos = 0x1f + // Bit mask of ENA field. + PERI_BACKUP_CONFIG_ENA_Msk = 0x80000000 + // Bit ENA. + PERI_BACKUP_CONFIG_ENA = 0x80000000 + + // APB_ADDR: x + // Position of APB_START_ADDR field. + PERI_BACKUP_APB_ADDR_APB_START_ADDR_Pos = 0x0 + // Bit mask of APB_START_ADDR field. + PERI_BACKUP_APB_ADDR_APB_START_ADDR_Msk = 0xffffffff + + // MEM_ADDR: x + // Position of MEM_START_ADDR field. + PERI_BACKUP_MEM_ADDR_MEM_START_ADDR_Pos = 0x0 + // Bit mask of MEM_START_ADDR field. + PERI_BACKUP_MEM_ADDR_MEM_START_ADDR_Msk = 0xffffffff + + // REG_MAP0: x + // Position of MAP0 field. + PERI_BACKUP_REG_MAP0_MAP0_Pos = 0x0 + // Bit mask of MAP0 field. + PERI_BACKUP_REG_MAP0_MAP0_Msk = 0xffffffff + + // REG_MAP1: x + // Position of MAP1 field. + PERI_BACKUP_REG_MAP1_MAP1_Pos = 0x0 + // Bit mask of MAP1 field. + PERI_BACKUP_REG_MAP1_MAP1_Msk = 0xffffffff + + // REG_MAP2: x + // Position of MAP2 field. + PERI_BACKUP_REG_MAP2_MAP2_Pos = 0x0 + // Bit mask of MAP2 field. + PERI_BACKUP_REG_MAP2_MAP2_Msk = 0xffffffff + + // REG_MAP3: x + // Position of MAP3 field. + PERI_BACKUP_REG_MAP3_MAP3_Pos = 0x0 + // Bit mask of MAP3 field. + PERI_BACKUP_REG_MAP3_MAP3_Msk = 0xffffffff + + // INT_RAW: x + // Position of DONE_INT_RAW field. + PERI_BACKUP_INT_RAW_DONE_INT_RAW_Pos = 0x0 + // Bit mask of DONE_INT_RAW field. + PERI_BACKUP_INT_RAW_DONE_INT_RAW_Msk = 0x1 + // Bit DONE_INT_RAW. + PERI_BACKUP_INT_RAW_DONE_INT_RAW = 0x1 + // Position of ERR_INT_RAW field. + PERI_BACKUP_INT_RAW_ERR_INT_RAW_Pos = 0x1 + // Bit mask of ERR_INT_RAW field. + PERI_BACKUP_INT_RAW_ERR_INT_RAW_Msk = 0x2 + // Bit ERR_INT_RAW. + PERI_BACKUP_INT_RAW_ERR_INT_RAW = 0x2 + + // INT_ST: x + // Position of DONE_INT_ST field. + PERI_BACKUP_INT_ST_DONE_INT_ST_Pos = 0x0 + // Bit mask of DONE_INT_ST field. + PERI_BACKUP_INT_ST_DONE_INT_ST_Msk = 0x1 + // Bit DONE_INT_ST. + PERI_BACKUP_INT_ST_DONE_INT_ST = 0x1 + // Position of ERR_INT_ST field. + PERI_BACKUP_INT_ST_ERR_INT_ST_Pos = 0x1 + // Bit mask of ERR_INT_ST field. + PERI_BACKUP_INT_ST_ERR_INT_ST_Msk = 0x2 + // Bit ERR_INT_ST. + PERI_BACKUP_INT_ST_ERR_INT_ST = 0x2 + + // INT_ENA: x + // Position of DONE_INT_ENA field. + PERI_BACKUP_INT_ENA_DONE_INT_ENA_Pos = 0x0 + // Bit mask of DONE_INT_ENA field. + PERI_BACKUP_INT_ENA_DONE_INT_ENA_Msk = 0x1 + // Bit DONE_INT_ENA. + PERI_BACKUP_INT_ENA_DONE_INT_ENA = 0x1 + // Position of ERR_INT_ENA field. + PERI_BACKUP_INT_ENA_ERR_INT_ENA_Pos = 0x1 + // Bit mask of ERR_INT_ENA field. + PERI_BACKUP_INT_ENA_ERR_INT_ENA_Msk = 0x2 + // Bit ERR_INT_ENA. + PERI_BACKUP_INT_ENA_ERR_INT_ENA = 0x2 + + // INT_CLR: x + // Position of DONE_INT_CLR field. + PERI_BACKUP_INT_CLR_DONE_INT_CLR_Pos = 0x0 + // Bit mask of DONE_INT_CLR field. + PERI_BACKUP_INT_CLR_DONE_INT_CLR_Msk = 0x1 + // Bit DONE_INT_CLR. + PERI_BACKUP_INT_CLR_DONE_INT_CLR = 0x1 + // Position of ERR_INT_CLR field. + PERI_BACKUP_INT_CLR_ERR_INT_CLR_Pos = 0x1 + // Bit mask of ERR_INT_CLR field. + PERI_BACKUP_INT_CLR_ERR_INT_CLR_Msk = 0x2 + // Bit ERR_INT_CLR. + PERI_BACKUP_INT_CLR_ERR_INT_CLR = 0x2 + + // DATE: x + // Position of DATE field. + PERI_BACKUP_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + PERI_BACKUP_DATE_DATE_Msk = 0xfffffff + // Position of CLK_EN field. + PERI_BACKUP_DATE_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + PERI_BACKUP_DATE_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + PERI_BACKUP_DATE_CLK_EN = 0x80000000 +) + +// Constants for MCPWM0: Motor Control Pulse-Width Modulation 0 +const ( + // CLK_CFG: PWM clock prescaler register. + // Position of CLK_PRESCALE field. + PWM_CLK_CFG_CLK_PRESCALE_Pos = 0x0 + // Bit mask of CLK_PRESCALE field. + PWM_CLK_CFG_CLK_PRESCALE_Msk = 0xff + + // TIMER0_CFG0: PWM timer0 period and update method configuration register. + // Position of TIMER0_PRESCALE field. + PWM_TIMER0_CFG0_TIMER0_PRESCALE_Pos = 0x0 + // Bit mask of TIMER0_PRESCALE field. + PWM_TIMER0_CFG0_TIMER0_PRESCALE_Msk = 0xff + // Position of TIMER0_PERIOD field. + PWM_TIMER0_CFG0_TIMER0_PERIOD_Pos = 0x8 + // Bit mask of TIMER0_PERIOD field. + PWM_TIMER0_CFG0_TIMER0_PERIOD_Msk = 0xffff00 + // Position of TIMER0_PERIOD_UPMETHOD field. + PWM_TIMER0_CFG0_TIMER0_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER0_PERIOD_UPMETHOD field. + PWM_TIMER0_CFG0_TIMER0_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER0_CFG1: PWM timer0 working mode and start/stop control configuration register. + // Position of TIMER0_START field. + PWM_TIMER0_CFG1_TIMER0_START_Pos = 0x0 + // Bit mask of TIMER0_START field. + PWM_TIMER0_CFG1_TIMER0_START_Msk = 0x7 + // Position of TIMER0_MOD field. + PWM_TIMER0_CFG1_TIMER0_MOD_Pos = 0x3 + // Bit mask of TIMER0_MOD field. + PWM_TIMER0_CFG1_TIMER0_MOD_Msk = 0x18 + + // TIMER0_SYNC: PWM timer0 sync function configuration register. + // Position of TIMER0_SYNCI_EN field. + PWM_TIMER0_SYNC_TIMER0_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER0_SYNCI_EN field. + PWM_TIMER0_SYNC_TIMER0_SYNCI_EN_Msk = 0x1 + // Bit TIMER0_SYNCI_EN. + PWM_TIMER0_SYNC_TIMER0_SYNCI_EN = 0x1 + // Position of SW field. + PWM_TIMER0_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + PWM_TIMER0_SYNC_SW_Msk = 0x2 + // Bit SW. + PWM_TIMER0_SYNC_SW = 0x2 + // Position of TIMER0_SYNCO_SEL field. + PWM_TIMER0_SYNC_TIMER0_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER0_SYNCO_SEL field. + PWM_TIMER0_SYNC_TIMER0_SYNCO_SEL_Msk = 0xc + // Position of TIMER0_PHASE field. + PWM_TIMER0_SYNC_TIMER0_PHASE_Pos = 0x4 + // Bit mask of TIMER0_PHASE field. + PWM_TIMER0_SYNC_TIMER0_PHASE_Msk = 0xffff0 + // Position of TIMER0_PHASE_DIRECTION field. + PWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER0_PHASE_DIRECTION field. + PWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER0_PHASE_DIRECTION. + PWM_TIMER0_SYNC_TIMER0_PHASE_DIRECTION = 0x100000 + + // TIMER0_STATUS: PWM timer0 status register. + // Position of TIMER0_VALUE field. + PWM_TIMER0_STATUS_TIMER0_VALUE_Pos = 0x0 + // Bit mask of TIMER0_VALUE field. + PWM_TIMER0_STATUS_TIMER0_VALUE_Msk = 0xffff + // Position of TIMER0_DIRECTION field. + PWM_TIMER0_STATUS_TIMER0_DIRECTION_Pos = 0x10 + // Bit mask of TIMER0_DIRECTION field. + PWM_TIMER0_STATUS_TIMER0_DIRECTION_Msk = 0x10000 + // Bit TIMER0_DIRECTION. + PWM_TIMER0_STATUS_TIMER0_DIRECTION = 0x10000 + + // TIMER1_CFG0: PWM timer1 period and update method configuration register. + // Position of TIMER1_PRESCALE field. + PWM_TIMER1_CFG0_TIMER1_PRESCALE_Pos = 0x0 + // Bit mask of TIMER1_PRESCALE field. + PWM_TIMER1_CFG0_TIMER1_PRESCALE_Msk = 0xff + // Position of TIMER1_PERIOD field. + PWM_TIMER1_CFG0_TIMER1_PERIOD_Pos = 0x8 + // Bit mask of TIMER1_PERIOD field. + PWM_TIMER1_CFG0_TIMER1_PERIOD_Msk = 0xffff00 + // Position of TIMER1_PERIOD_UPMETHOD field. + PWM_TIMER1_CFG0_TIMER1_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER1_PERIOD_UPMETHOD field. + PWM_TIMER1_CFG0_TIMER1_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER1_CFG1: PWM timer1 working mode and start/stop control configuration register. + // Position of TIMER1_START field. + PWM_TIMER1_CFG1_TIMER1_START_Pos = 0x0 + // Bit mask of TIMER1_START field. + PWM_TIMER1_CFG1_TIMER1_START_Msk = 0x7 + // Position of TIMER1_MOD field. + PWM_TIMER1_CFG1_TIMER1_MOD_Pos = 0x3 + // Bit mask of TIMER1_MOD field. + PWM_TIMER1_CFG1_TIMER1_MOD_Msk = 0x18 + + // TIMER1_SYNC: PWM timer1 sync function configuration register. + // Position of TIMER1_SYNCI_EN field. + PWM_TIMER1_SYNC_TIMER1_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER1_SYNCI_EN field. + PWM_TIMER1_SYNC_TIMER1_SYNCI_EN_Msk = 0x1 + // Bit TIMER1_SYNCI_EN. + PWM_TIMER1_SYNC_TIMER1_SYNCI_EN = 0x1 + // Position of SW field. + PWM_TIMER1_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + PWM_TIMER1_SYNC_SW_Msk = 0x2 + // Bit SW. + PWM_TIMER1_SYNC_SW = 0x2 + // Position of TIMER1_SYNCO_SEL field. + PWM_TIMER1_SYNC_TIMER1_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER1_SYNCO_SEL field. + PWM_TIMER1_SYNC_TIMER1_SYNCO_SEL_Msk = 0xc + // Position of TIMER1_PHASE field. + PWM_TIMER1_SYNC_TIMER1_PHASE_Pos = 0x4 + // Bit mask of TIMER1_PHASE field. + PWM_TIMER1_SYNC_TIMER1_PHASE_Msk = 0xffff0 + // Position of TIMER1_PHASE_DIRECTION field. + PWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER1_PHASE_DIRECTION field. + PWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER1_PHASE_DIRECTION. + PWM_TIMER1_SYNC_TIMER1_PHASE_DIRECTION = 0x100000 + + // TIMER1_STATUS: PWM timer1 status register. + // Position of TIMER1_VALUE field. + PWM_TIMER1_STATUS_TIMER1_VALUE_Pos = 0x0 + // Bit mask of TIMER1_VALUE field. + PWM_TIMER1_STATUS_TIMER1_VALUE_Msk = 0xffff + // Position of TIMER1_DIRECTION field. + PWM_TIMER1_STATUS_TIMER1_DIRECTION_Pos = 0x10 + // Bit mask of TIMER1_DIRECTION field. + PWM_TIMER1_STATUS_TIMER1_DIRECTION_Msk = 0x10000 + // Bit TIMER1_DIRECTION. + PWM_TIMER1_STATUS_TIMER1_DIRECTION = 0x10000 + + // TIMER2_CFG0: PWM timer2 period and update method configuration register. + // Position of TIMER2_PRESCALE field. + PWM_TIMER2_CFG0_TIMER2_PRESCALE_Pos = 0x0 + // Bit mask of TIMER2_PRESCALE field. + PWM_TIMER2_CFG0_TIMER2_PRESCALE_Msk = 0xff + // Position of TIMER2_PERIOD field. + PWM_TIMER2_CFG0_TIMER2_PERIOD_Pos = 0x8 + // Bit mask of TIMER2_PERIOD field. + PWM_TIMER2_CFG0_TIMER2_PERIOD_Msk = 0xffff00 + // Position of TIMER2_PERIOD_UPMETHOD field. + PWM_TIMER2_CFG0_TIMER2_PERIOD_UPMETHOD_Pos = 0x18 + // Bit mask of TIMER2_PERIOD_UPMETHOD field. + PWM_TIMER2_CFG0_TIMER2_PERIOD_UPMETHOD_Msk = 0x3000000 + + // TIMER2_CFG1: PWM timer2 working mode and start/stop control configuration register. + // Position of TIMER2_START field. + PWM_TIMER2_CFG1_TIMER2_START_Pos = 0x0 + // Bit mask of TIMER2_START field. + PWM_TIMER2_CFG1_TIMER2_START_Msk = 0x7 + // Position of TIMER2_MOD field. + PWM_TIMER2_CFG1_TIMER2_MOD_Pos = 0x3 + // Bit mask of TIMER2_MOD field. + PWM_TIMER2_CFG1_TIMER2_MOD_Msk = 0x18 + + // TIMER2_SYNC: PWM timer2 sync function configuration register. + // Position of TIMER2_SYNCI_EN field. + PWM_TIMER2_SYNC_TIMER2_SYNCI_EN_Pos = 0x0 + // Bit mask of TIMER2_SYNCI_EN field. + PWM_TIMER2_SYNC_TIMER2_SYNCI_EN_Msk = 0x1 + // Bit TIMER2_SYNCI_EN. + PWM_TIMER2_SYNC_TIMER2_SYNCI_EN = 0x1 + // Position of SW field. + PWM_TIMER2_SYNC_SW_Pos = 0x1 + // Bit mask of SW field. + PWM_TIMER2_SYNC_SW_Msk = 0x2 + // Bit SW. + PWM_TIMER2_SYNC_SW = 0x2 + // Position of TIMER2_SYNCO_SEL field. + PWM_TIMER2_SYNC_TIMER2_SYNCO_SEL_Pos = 0x2 + // Bit mask of TIMER2_SYNCO_SEL field. + PWM_TIMER2_SYNC_TIMER2_SYNCO_SEL_Msk = 0xc + // Position of TIMER2_PHASE field. + PWM_TIMER2_SYNC_TIMER2_PHASE_Pos = 0x4 + // Bit mask of TIMER2_PHASE field. + PWM_TIMER2_SYNC_TIMER2_PHASE_Msk = 0xffff0 + // Position of TIMER2_PHASE_DIRECTION field. + PWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION_Pos = 0x14 + // Bit mask of TIMER2_PHASE_DIRECTION field. + PWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION_Msk = 0x100000 + // Bit TIMER2_PHASE_DIRECTION. + PWM_TIMER2_SYNC_TIMER2_PHASE_DIRECTION = 0x100000 + + // TIMER2_STATUS: PWM timer2 status register. + // Position of TIMER2_VALUE field. + PWM_TIMER2_STATUS_TIMER2_VALUE_Pos = 0x0 + // Bit mask of TIMER2_VALUE field. + PWM_TIMER2_STATUS_TIMER2_VALUE_Msk = 0xffff + // Position of TIMER2_DIRECTION field. + PWM_TIMER2_STATUS_TIMER2_DIRECTION_Pos = 0x10 + // Bit mask of TIMER2_DIRECTION field. + PWM_TIMER2_STATUS_TIMER2_DIRECTION_Msk = 0x10000 + // Bit TIMER2_DIRECTION. + PWM_TIMER2_STATUS_TIMER2_DIRECTION = 0x10000 + + // TIMER_SYNCI_CFG: Synchronization input selection for three PWM timers. + // Position of TIMER0_SYNCISEL field. + PWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Pos = 0x0 + // Bit mask of TIMER0_SYNCISEL field. + PWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Msk = 0x7 + // Position of TIMER1_SYNCISEL field. + PWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Pos = 0x3 + // Bit mask of TIMER1_SYNCISEL field. + PWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Msk = 0x38 + // Position of TIMER2_SYNCISEL field. + PWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Pos = 0x6 + // Bit mask of TIMER2_SYNCISEL field. + PWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Msk = 0x1c0 + // Position of EXTERNAL_SYNCI0_INVERT field. + PWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Pos = 0x9 + // Bit mask of EXTERNAL_SYNCI0_INVERT field. + PWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Msk = 0x200 + // Bit EXTERNAL_SYNCI0_INVERT. + PWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT = 0x200 + // Position of EXTERNAL_SYNCI1_INVERT field. + PWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Pos = 0xa + // Bit mask of EXTERNAL_SYNCI1_INVERT field. + PWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Msk = 0x400 + // Bit EXTERNAL_SYNCI1_INVERT. + PWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT = 0x400 + // Position of EXTERNAL_SYNCI2_INVERT field. + PWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Pos = 0xb + // Bit mask of EXTERNAL_SYNCI2_INVERT field. + PWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Msk = 0x800 + // Bit EXTERNAL_SYNCI2_INVERT. + PWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT = 0x800 + + // OPERATOR_TIMERSEL: Select specific timer for PWM operators. + // Position of OPERATOR0_TIMERSEL field. + PWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Pos = 0x0 + // Bit mask of OPERATOR0_TIMERSEL field. + PWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Msk = 0x3 + // Position of OPERATOR1_TIMERSEL field. + PWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Pos = 0x2 + // Bit mask of OPERATOR1_TIMERSEL field. + PWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Msk = 0xc + // Position of OPERATOR2_TIMERSEL field. + PWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Pos = 0x4 + // Bit mask of OPERATOR2_TIMERSEL field. + PWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Msk = 0x30 + + // CMPR0_CFG: Transfer status and update method for time stamp registers A and B + // Position of CMPR0_A_UPMETHOD field. + PWM_CMPR0_CFG_CMPR0_A_UPMETHOD_Pos = 0x0 + // Bit mask of CMPR0_A_UPMETHOD field. + PWM_CMPR0_CFG_CMPR0_A_UPMETHOD_Msk = 0xf + // Position of CMPR0_B_UPMETHOD field. + PWM_CMPR0_CFG_CMPR0_B_UPMETHOD_Pos = 0x4 + // Bit mask of CMPR0_B_UPMETHOD field. + PWM_CMPR0_CFG_CMPR0_B_UPMETHOD_Msk = 0xf0 + // Position of CMPR0_A_SHDW_FULL field. + PWM_CMPR0_CFG_CMPR0_A_SHDW_FULL_Pos = 0x8 + // Bit mask of CMPR0_A_SHDW_FULL field. + PWM_CMPR0_CFG_CMPR0_A_SHDW_FULL_Msk = 0x100 + // Bit CMPR0_A_SHDW_FULL. + PWM_CMPR0_CFG_CMPR0_A_SHDW_FULL = 0x100 + // Position of CMPR0_B_SHDW_FULL field. + PWM_CMPR0_CFG_CMPR0_B_SHDW_FULL_Pos = 0x9 + // Bit mask of CMPR0_B_SHDW_FULL field. + PWM_CMPR0_CFG_CMPR0_B_SHDW_FULL_Msk = 0x200 + // Bit CMPR0_B_SHDW_FULL. + PWM_CMPR0_CFG_CMPR0_B_SHDW_FULL = 0x200 + + // CMPR0_VALUE0: Shadow register for register A. + // Position of CMPR0_A field. + PWM_CMPR0_VALUE0_CMPR0_A_Pos = 0x0 + // Bit mask of CMPR0_A field. + PWM_CMPR0_VALUE0_CMPR0_A_Msk = 0xffff + + // CMPR0_VALUE1: Shadow register for register B. + // Position of CMPR0_B field. + PWM_CMPR0_VALUE1_CMPR0_B_Pos = 0x0 + // Bit mask of CMPR0_B field. + PWM_CMPR0_VALUE1_CMPR0_B_Msk = 0xffff + + // GEN0_CFG0: Fault event T0 and T1 handling + // Position of GEN0_CFG_UPMETHOD field. + PWM_GEN0_CFG0_GEN0_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN0_CFG_UPMETHOD field. + PWM_GEN0_CFG0_GEN0_CFG_UPMETHOD_Msk = 0xf + // Position of GEN0_T0_SEL field. + PWM_GEN0_CFG0_GEN0_T0_SEL_Pos = 0x4 + // Bit mask of GEN0_T0_SEL field. + PWM_GEN0_CFG0_GEN0_T0_SEL_Msk = 0x70 + // Position of GEN0_T1_SEL field. + PWM_GEN0_CFG0_GEN0_T1_SEL_Pos = 0x7 + // Bit mask of GEN0_T1_SEL field. + PWM_GEN0_CFG0_GEN0_T1_SEL_Msk = 0x380 + + // GEN0_FORCE: Permissives to force PWM0A and PWM0B outputs by software + // Position of GEN0_CNTUFORCE_UPMETHOD field. + PWM_GEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN0_CNTUFORCE_UPMETHOD field. + PWM_GEN0_FORCE_GEN0_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN0_A_CNTUFORCE_MODE field. + PWM_GEN0_FORCE_GEN0_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN0_A_CNTUFORCE_MODE field. + PWM_GEN0_FORCE_GEN0_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN0_B_CNTUFORCE_MODE field. + PWM_GEN0_FORCE_GEN0_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN0_B_CNTUFORCE_MODE field. + PWM_GEN0_FORCE_GEN0_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN0_A_NCIFORCE field. + PWM_GEN0_FORCE_GEN0_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN0_A_NCIFORCE field. + PWM_GEN0_FORCE_GEN0_A_NCIFORCE_Msk = 0x400 + // Bit GEN0_A_NCIFORCE. + PWM_GEN0_FORCE_GEN0_A_NCIFORCE = 0x400 + // Position of GEN0_A_NCIFORCE_MODE field. + PWM_GEN0_FORCE_GEN0_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN0_A_NCIFORCE_MODE field. + PWM_GEN0_FORCE_GEN0_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN0_B_NCIFORCE field. + PWM_GEN0_FORCE_GEN0_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN0_B_NCIFORCE field. + PWM_GEN0_FORCE_GEN0_B_NCIFORCE_Msk = 0x2000 + // Bit GEN0_B_NCIFORCE. + PWM_GEN0_FORCE_GEN0_B_NCIFORCE = 0x2000 + // Position of GEN0_B_NCIFORCE_MODE field. + PWM_GEN0_FORCE_GEN0_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN0_B_NCIFORCE_MODE field. + PWM_GEN0_FORCE_GEN0_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN0_A: Actions triggered by events on PWM0A + // Position of UTEZ field. + PWM_GEN0_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + PWM_GEN0_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + PWM_GEN0_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + PWM_GEN0_A_UTEP_Msk = 0xc + // Position of UTEA field. + PWM_GEN0_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + PWM_GEN0_A_UTEA_Msk = 0x30 + // Position of UTEB field. + PWM_GEN0_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + PWM_GEN0_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + PWM_GEN0_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + PWM_GEN0_A_UT0_Msk = 0x300 + // Position of UT1 field. + PWM_GEN0_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + PWM_GEN0_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + PWM_GEN0_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + PWM_GEN0_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + PWM_GEN0_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + PWM_GEN0_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + PWM_GEN0_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + PWM_GEN0_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + PWM_GEN0_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + PWM_GEN0_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + PWM_GEN0_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + PWM_GEN0_A_DT0_Msk = 0x300000 + // Position of DT1 field. + PWM_GEN0_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + PWM_GEN0_A_DT1_Msk = 0xc00000 + + // GEN0_B: Actions triggered by events on PWM0B + // Position of UTEZ field. + PWM_GEN0_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + PWM_GEN0_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + PWM_GEN0_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + PWM_GEN0_B_UTEP_Msk = 0xc + // Position of UTEA field. + PWM_GEN0_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + PWM_GEN0_B_UTEA_Msk = 0x30 + // Position of UTEB field. + PWM_GEN0_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + PWM_GEN0_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + PWM_GEN0_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + PWM_GEN0_B_UT0_Msk = 0x300 + // Position of UT1 field. + PWM_GEN0_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + PWM_GEN0_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + PWM_GEN0_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + PWM_GEN0_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + PWM_GEN0_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + PWM_GEN0_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + PWM_GEN0_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + PWM_GEN0_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + PWM_GEN0_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + PWM_GEN0_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + PWM_GEN0_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + PWM_GEN0_B_DT0_Msk = 0x300000 + // Position of DT1 field. + PWM_GEN0_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + PWM_GEN0_B_DT1_Msk = 0xc00000 + + // DB0_CFG: dead time type selection and configuration + // Position of DB0_FED_UPMETHOD field. + PWM_DB0_CFG_DB0_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DB0_FED_UPMETHOD field. + PWM_DB0_CFG_DB0_FED_UPMETHOD_Msk = 0xf + // Position of DB0_RED_UPMETHOD field. + PWM_DB0_CFG_DB0_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DB0_RED_UPMETHOD field. + PWM_DB0_CFG_DB0_RED_UPMETHOD_Msk = 0xf0 + // Position of DB0_DEB_MODE field. + PWM_DB0_CFG_DB0_DEB_MODE_Pos = 0x8 + // Bit mask of DB0_DEB_MODE field. + PWM_DB0_CFG_DB0_DEB_MODE_Msk = 0x100 + // Bit DB0_DEB_MODE. + PWM_DB0_CFG_DB0_DEB_MODE = 0x100 + // Position of DB0_A_OUTSWAP field. + PWM_DB0_CFG_DB0_A_OUTSWAP_Pos = 0x9 + // Bit mask of DB0_A_OUTSWAP field. + PWM_DB0_CFG_DB0_A_OUTSWAP_Msk = 0x200 + // Bit DB0_A_OUTSWAP. + PWM_DB0_CFG_DB0_A_OUTSWAP = 0x200 + // Position of DB0_B_OUTSWAP field. + PWM_DB0_CFG_DB0_B_OUTSWAP_Pos = 0xa + // Bit mask of DB0_B_OUTSWAP field. + PWM_DB0_CFG_DB0_B_OUTSWAP_Msk = 0x400 + // Bit DB0_B_OUTSWAP. + PWM_DB0_CFG_DB0_B_OUTSWAP = 0x400 + // Position of DB0_RED_INSEL field. + PWM_DB0_CFG_DB0_RED_INSEL_Pos = 0xb + // Bit mask of DB0_RED_INSEL field. + PWM_DB0_CFG_DB0_RED_INSEL_Msk = 0x800 + // Bit DB0_RED_INSEL. + PWM_DB0_CFG_DB0_RED_INSEL = 0x800 + // Position of DB0_FED_INSEL field. + PWM_DB0_CFG_DB0_FED_INSEL_Pos = 0xc + // Bit mask of DB0_FED_INSEL field. + PWM_DB0_CFG_DB0_FED_INSEL_Msk = 0x1000 + // Bit DB0_FED_INSEL. + PWM_DB0_CFG_DB0_FED_INSEL = 0x1000 + // Position of DB0_RED_OUTINVERT field. + PWM_DB0_CFG_DB0_RED_OUTINVERT_Pos = 0xd + // Bit mask of DB0_RED_OUTINVERT field. + PWM_DB0_CFG_DB0_RED_OUTINVERT_Msk = 0x2000 + // Bit DB0_RED_OUTINVERT. + PWM_DB0_CFG_DB0_RED_OUTINVERT = 0x2000 + // Position of DB0_FED_OUTINVERT field. + PWM_DB0_CFG_DB0_FED_OUTINVERT_Pos = 0xe + // Bit mask of DB0_FED_OUTINVERT field. + PWM_DB0_CFG_DB0_FED_OUTINVERT_Msk = 0x4000 + // Bit DB0_FED_OUTINVERT. + PWM_DB0_CFG_DB0_FED_OUTINVERT = 0x4000 + // Position of DB0_A_OUTBYPASS field. + PWM_DB0_CFG_DB0_A_OUTBYPASS_Pos = 0xf + // Bit mask of DB0_A_OUTBYPASS field. + PWM_DB0_CFG_DB0_A_OUTBYPASS_Msk = 0x8000 + // Bit DB0_A_OUTBYPASS. + PWM_DB0_CFG_DB0_A_OUTBYPASS = 0x8000 + // Position of DB0_B_OUTBYPASS field. + PWM_DB0_CFG_DB0_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DB0_B_OUTBYPASS field. + PWM_DB0_CFG_DB0_B_OUTBYPASS_Msk = 0x10000 + // Bit DB0_B_OUTBYPASS. + PWM_DB0_CFG_DB0_B_OUTBYPASS = 0x10000 + // Position of DB0_CLK_SEL field. + PWM_DB0_CFG_DB0_CLK_SEL_Pos = 0x11 + // Bit mask of DB0_CLK_SEL field. + PWM_DB0_CFG_DB0_CLK_SEL_Msk = 0x20000 + // Bit DB0_CLK_SEL. + PWM_DB0_CFG_DB0_CLK_SEL = 0x20000 + + // DB0_FED_CFG: Shadow register for falling edge delay (FED). + // Position of DB0_FED field. + PWM_DB0_FED_CFG_DB0_FED_Pos = 0x0 + // Bit mask of DB0_FED field. + PWM_DB0_FED_CFG_DB0_FED_Msk = 0xffff + + // DB0_RED_CFG: Shadow register for rising edge delay (RED). + // Position of DB0_RED field. + PWM_DB0_RED_CFG_DB0_RED_Pos = 0x0 + // Bit mask of DB0_RED field. + PWM_DB0_RED_CFG_DB0_RED_Msk = 0xffff + + // CHOPPER0_CFG: Carrier enable and configuratoin + // Position of CHOPPER0_EN field. + PWM_CHOPPER0_CFG_CHOPPER0_EN_Pos = 0x0 + // Bit mask of CHOPPER0_EN field. + PWM_CHOPPER0_CFG_CHOPPER0_EN_Msk = 0x1 + // Bit CHOPPER0_EN. + PWM_CHOPPER0_CFG_CHOPPER0_EN = 0x1 + // Position of CHOPPER0_PRESCALE field. + PWM_CHOPPER0_CFG_CHOPPER0_PRESCALE_Pos = 0x1 + // Bit mask of CHOPPER0_PRESCALE field. + PWM_CHOPPER0_CFG_CHOPPER0_PRESCALE_Msk = 0x1e + // Position of CHOPPER0_DUTY field. + PWM_CHOPPER0_CFG_CHOPPER0_DUTY_Pos = 0x5 + // Bit mask of CHOPPER0_DUTY field. + PWM_CHOPPER0_CFG_CHOPPER0_DUTY_Msk = 0xe0 + // Position of CHOPPER0_OSHTWTH field. + PWM_CHOPPER0_CFG_CHOPPER0_OSHTWTH_Pos = 0x8 + // Bit mask of CHOPPER0_OSHTWTH field. + PWM_CHOPPER0_CFG_CHOPPER0_OSHTWTH_Msk = 0xf00 + // Position of CHOPPER0_OUT_INVERT field. + PWM_CHOPPER0_CFG_CHOPPER0_OUT_INVERT_Pos = 0xc + // Bit mask of CHOPPER0_OUT_INVERT field. + PWM_CHOPPER0_CFG_CHOPPER0_OUT_INVERT_Msk = 0x1000 + // Bit CHOPPER0_OUT_INVERT. + PWM_CHOPPER0_CFG_CHOPPER0_OUT_INVERT = 0x1000 + // Position of CHOPPER0_IN_INVERT field. + PWM_CHOPPER0_CFG_CHOPPER0_IN_INVERT_Pos = 0xd + // Bit mask of CHOPPER0_IN_INVERT field. + PWM_CHOPPER0_CFG_CHOPPER0_IN_INVERT_Msk = 0x2000 + // Bit CHOPPER0_IN_INVERT. + PWM_CHOPPER0_CFG_CHOPPER0_IN_INVERT = 0x2000 + + // TZ0_CFG0: Actions on PWM0A and PWM0B trip events + // Position of TZ0_SW_CBC field. + PWM_TZ0_CFG0_TZ0_SW_CBC_Pos = 0x0 + // Bit mask of TZ0_SW_CBC field. + PWM_TZ0_CFG0_TZ0_SW_CBC_Msk = 0x1 + // Bit TZ0_SW_CBC. + PWM_TZ0_CFG0_TZ0_SW_CBC = 0x1 + // Position of TZ0_F2_CBC field. + PWM_TZ0_CFG0_TZ0_F2_CBC_Pos = 0x1 + // Bit mask of TZ0_F2_CBC field. + PWM_TZ0_CFG0_TZ0_F2_CBC_Msk = 0x2 + // Bit TZ0_F2_CBC. + PWM_TZ0_CFG0_TZ0_F2_CBC = 0x2 + // Position of TZ0_F1_CBC field. + PWM_TZ0_CFG0_TZ0_F1_CBC_Pos = 0x2 + // Bit mask of TZ0_F1_CBC field. + PWM_TZ0_CFG0_TZ0_F1_CBC_Msk = 0x4 + // Bit TZ0_F1_CBC. + PWM_TZ0_CFG0_TZ0_F1_CBC = 0x4 + // Position of TZ0_F0_CBC field. + PWM_TZ0_CFG0_TZ0_F0_CBC_Pos = 0x3 + // Bit mask of TZ0_F0_CBC field. + PWM_TZ0_CFG0_TZ0_F0_CBC_Msk = 0x8 + // Bit TZ0_F0_CBC. + PWM_TZ0_CFG0_TZ0_F0_CBC = 0x8 + // Position of TZ0_SW_OST field. + PWM_TZ0_CFG0_TZ0_SW_OST_Pos = 0x4 + // Bit mask of TZ0_SW_OST field. + PWM_TZ0_CFG0_TZ0_SW_OST_Msk = 0x10 + // Bit TZ0_SW_OST. + PWM_TZ0_CFG0_TZ0_SW_OST = 0x10 + // Position of TZ0_F2_OST field. + PWM_TZ0_CFG0_TZ0_F2_OST_Pos = 0x5 + // Bit mask of TZ0_F2_OST field. + PWM_TZ0_CFG0_TZ0_F2_OST_Msk = 0x20 + // Bit TZ0_F2_OST. + PWM_TZ0_CFG0_TZ0_F2_OST = 0x20 + // Position of TZ0_F1_OST field. + PWM_TZ0_CFG0_TZ0_F1_OST_Pos = 0x6 + // Bit mask of TZ0_F1_OST field. + PWM_TZ0_CFG0_TZ0_F1_OST_Msk = 0x40 + // Bit TZ0_F1_OST. + PWM_TZ0_CFG0_TZ0_F1_OST = 0x40 + // Position of TZ0_F0_OST field. + PWM_TZ0_CFG0_TZ0_F0_OST_Pos = 0x7 + // Bit mask of TZ0_F0_OST field. + PWM_TZ0_CFG0_TZ0_F0_OST_Msk = 0x80 + // Bit TZ0_F0_OST. + PWM_TZ0_CFG0_TZ0_F0_OST = 0x80 + // Position of TZ0_A_CBC_D field. + PWM_TZ0_CFG0_TZ0_A_CBC_D_Pos = 0x8 + // Bit mask of TZ0_A_CBC_D field. + PWM_TZ0_CFG0_TZ0_A_CBC_D_Msk = 0x300 + // Position of TZ0_A_CBC_U field. + PWM_TZ0_CFG0_TZ0_A_CBC_U_Pos = 0xa + // Bit mask of TZ0_A_CBC_U field. + PWM_TZ0_CFG0_TZ0_A_CBC_U_Msk = 0xc00 + // Position of TZ0_A_OST_D field. + PWM_TZ0_CFG0_TZ0_A_OST_D_Pos = 0xc + // Bit mask of TZ0_A_OST_D field. + PWM_TZ0_CFG0_TZ0_A_OST_D_Msk = 0x3000 + // Position of TZ0_A_OST_U field. + PWM_TZ0_CFG0_TZ0_A_OST_U_Pos = 0xe + // Bit mask of TZ0_A_OST_U field. + PWM_TZ0_CFG0_TZ0_A_OST_U_Msk = 0xc000 + // Position of TZ0_B_CBC_D field. + PWM_TZ0_CFG0_TZ0_B_CBC_D_Pos = 0x10 + // Bit mask of TZ0_B_CBC_D field. + PWM_TZ0_CFG0_TZ0_B_CBC_D_Msk = 0x30000 + // Position of TZ0_B_CBC_U field. + PWM_TZ0_CFG0_TZ0_B_CBC_U_Pos = 0x12 + // Bit mask of TZ0_B_CBC_U field. + PWM_TZ0_CFG0_TZ0_B_CBC_U_Msk = 0xc0000 + // Position of TZ0_B_OST_D field. + PWM_TZ0_CFG0_TZ0_B_OST_D_Pos = 0x14 + // Bit mask of TZ0_B_OST_D field. + PWM_TZ0_CFG0_TZ0_B_OST_D_Msk = 0x300000 + // Position of TZ0_B_OST_U field. + PWM_TZ0_CFG0_TZ0_B_OST_U_Pos = 0x16 + // Bit mask of TZ0_B_OST_U field. + PWM_TZ0_CFG0_TZ0_B_OST_U_Msk = 0xc00000 + + // TZ0_CFG1: Software triggers for fault handler actions + // Position of TZ0_CLR_OST field. + PWM_TZ0_CFG1_TZ0_CLR_OST_Pos = 0x0 + // Bit mask of TZ0_CLR_OST field. + PWM_TZ0_CFG1_TZ0_CLR_OST_Msk = 0x1 + // Bit TZ0_CLR_OST. + PWM_TZ0_CFG1_TZ0_CLR_OST = 0x1 + // Position of TZ0_CBCPULSE field. + PWM_TZ0_CFG1_TZ0_CBCPULSE_Pos = 0x1 + // Bit mask of TZ0_CBCPULSE field. + PWM_TZ0_CFG1_TZ0_CBCPULSE_Msk = 0x6 + // Position of TZ0_FORCE_CBC field. + PWM_TZ0_CFG1_TZ0_FORCE_CBC_Pos = 0x3 + // Bit mask of TZ0_FORCE_CBC field. + PWM_TZ0_CFG1_TZ0_FORCE_CBC_Msk = 0x8 + // Bit TZ0_FORCE_CBC. + PWM_TZ0_CFG1_TZ0_FORCE_CBC = 0x8 + // Position of TZ0_FORCE_OST field. + PWM_TZ0_CFG1_TZ0_FORCE_OST_Pos = 0x4 + // Bit mask of TZ0_FORCE_OST field. + PWM_TZ0_CFG1_TZ0_FORCE_OST_Msk = 0x10 + // Bit TZ0_FORCE_OST. + PWM_TZ0_CFG1_TZ0_FORCE_OST = 0x10 + + // TZ0_STATUS: Status of fault events. + // Position of TZ0_CBC_ON field. + PWM_TZ0_STATUS_TZ0_CBC_ON_Pos = 0x0 + // Bit mask of TZ0_CBC_ON field. + PWM_TZ0_STATUS_TZ0_CBC_ON_Msk = 0x1 + // Bit TZ0_CBC_ON. + PWM_TZ0_STATUS_TZ0_CBC_ON = 0x1 + // Position of TZ0_OST_ON field. + PWM_TZ0_STATUS_TZ0_OST_ON_Pos = 0x1 + // Bit mask of TZ0_OST_ON field. + PWM_TZ0_STATUS_TZ0_OST_ON_Msk = 0x2 + // Bit TZ0_OST_ON. + PWM_TZ0_STATUS_TZ0_OST_ON = 0x2 + + // CMPR1_CFG: Transfer status and update method for time stamp registers A and B + // Position of CMPR1_A_UPMETHOD field. + PWM_CMPR1_CFG_CMPR1_A_UPMETHOD_Pos = 0x0 + // Bit mask of CMPR1_A_UPMETHOD field. + PWM_CMPR1_CFG_CMPR1_A_UPMETHOD_Msk = 0xf + // Position of CMPR1_B_UPMETHOD field. + PWM_CMPR1_CFG_CMPR1_B_UPMETHOD_Pos = 0x4 + // Bit mask of CMPR1_B_UPMETHOD field. + PWM_CMPR1_CFG_CMPR1_B_UPMETHOD_Msk = 0xf0 + // Position of CMPR1_A_SHDW_FULL field. + PWM_CMPR1_CFG_CMPR1_A_SHDW_FULL_Pos = 0x8 + // Bit mask of CMPR1_A_SHDW_FULL field. + PWM_CMPR1_CFG_CMPR1_A_SHDW_FULL_Msk = 0x100 + // Bit CMPR1_A_SHDW_FULL. + PWM_CMPR1_CFG_CMPR1_A_SHDW_FULL = 0x100 + // Position of CMPR1_B_SHDW_FULL field. + PWM_CMPR1_CFG_CMPR1_B_SHDW_FULL_Pos = 0x9 + // Bit mask of CMPR1_B_SHDW_FULL field. + PWM_CMPR1_CFG_CMPR1_B_SHDW_FULL_Msk = 0x200 + // Bit CMPR1_B_SHDW_FULL. + PWM_CMPR1_CFG_CMPR1_B_SHDW_FULL = 0x200 + + // CMPR1_VALUE0: Shadow register for register A. + // Position of CMPR1_A field. + PWM_CMPR1_VALUE0_CMPR1_A_Pos = 0x0 + // Bit mask of CMPR1_A field. + PWM_CMPR1_VALUE0_CMPR1_A_Msk = 0xffff + + // CMPR1_VALUE1: Shadow register for register B. + // Position of CMPR1_B field. + PWM_CMPR1_VALUE1_CMPR1_B_Pos = 0x0 + // Bit mask of CMPR1_B field. + PWM_CMPR1_VALUE1_CMPR1_B_Msk = 0xffff + + // GEN1_CFG0: Fault event T0 and T1 handling + // Position of GEN1_CFG_UPMETHOD field. + PWM_GEN1_CFG0_GEN1_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN1_CFG_UPMETHOD field. + PWM_GEN1_CFG0_GEN1_CFG_UPMETHOD_Msk = 0xf + // Position of GEN1_T0_SEL field. + PWM_GEN1_CFG0_GEN1_T0_SEL_Pos = 0x4 + // Bit mask of GEN1_T0_SEL field. + PWM_GEN1_CFG0_GEN1_T0_SEL_Msk = 0x70 + // Position of GEN1_T1_SEL field. + PWM_GEN1_CFG0_GEN1_T1_SEL_Pos = 0x7 + // Bit mask of GEN1_T1_SEL field. + PWM_GEN1_CFG0_GEN1_T1_SEL_Msk = 0x380 + + // GEN1_FORCE: Permissives to force PWM1A and PWM1B outputs by software + // Position of GEN1_CNTUFORCE_UPMETHOD field. + PWM_GEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN1_CNTUFORCE_UPMETHOD field. + PWM_GEN1_FORCE_GEN1_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN1_A_CNTUFORCE_MODE field. + PWM_GEN1_FORCE_GEN1_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN1_A_CNTUFORCE_MODE field. + PWM_GEN1_FORCE_GEN1_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN1_B_CNTUFORCE_MODE field. + PWM_GEN1_FORCE_GEN1_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN1_B_CNTUFORCE_MODE field. + PWM_GEN1_FORCE_GEN1_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN1_A_NCIFORCE field. + PWM_GEN1_FORCE_GEN1_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN1_A_NCIFORCE field. + PWM_GEN1_FORCE_GEN1_A_NCIFORCE_Msk = 0x400 + // Bit GEN1_A_NCIFORCE. + PWM_GEN1_FORCE_GEN1_A_NCIFORCE = 0x400 + // Position of GEN1_A_NCIFORCE_MODE field. + PWM_GEN1_FORCE_GEN1_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN1_A_NCIFORCE_MODE field. + PWM_GEN1_FORCE_GEN1_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN1_B_NCIFORCE field. + PWM_GEN1_FORCE_GEN1_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN1_B_NCIFORCE field. + PWM_GEN1_FORCE_GEN1_B_NCIFORCE_Msk = 0x2000 + // Bit GEN1_B_NCIFORCE. + PWM_GEN1_FORCE_GEN1_B_NCIFORCE = 0x2000 + // Position of GEN1_B_NCIFORCE_MODE field. + PWM_GEN1_FORCE_GEN1_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN1_B_NCIFORCE_MODE field. + PWM_GEN1_FORCE_GEN1_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN1_A: Actions triggered by events on PWM1A + // Position of UTEZ field. + PWM_GEN1_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + PWM_GEN1_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + PWM_GEN1_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + PWM_GEN1_A_UTEP_Msk = 0xc + // Position of UTEA field. + PWM_GEN1_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + PWM_GEN1_A_UTEA_Msk = 0x30 + // Position of UTEB field. + PWM_GEN1_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + PWM_GEN1_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + PWM_GEN1_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + PWM_GEN1_A_UT0_Msk = 0x300 + // Position of UT1 field. + PWM_GEN1_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + PWM_GEN1_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + PWM_GEN1_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + PWM_GEN1_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + PWM_GEN1_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + PWM_GEN1_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + PWM_GEN1_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + PWM_GEN1_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + PWM_GEN1_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + PWM_GEN1_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + PWM_GEN1_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + PWM_GEN1_A_DT0_Msk = 0x300000 + // Position of DT1 field. + PWM_GEN1_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + PWM_GEN1_A_DT1_Msk = 0xc00000 + + // GEN1_B: Actions triggered by events on PWM1B + // Position of UTEZ field. + PWM_GEN1_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + PWM_GEN1_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + PWM_GEN1_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + PWM_GEN1_B_UTEP_Msk = 0xc + // Position of UTEA field. + PWM_GEN1_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + PWM_GEN1_B_UTEA_Msk = 0x30 + // Position of UTEB field. + PWM_GEN1_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + PWM_GEN1_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + PWM_GEN1_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + PWM_GEN1_B_UT0_Msk = 0x300 + // Position of UT1 field. + PWM_GEN1_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + PWM_GEN1_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + PWM_GEN1_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + PWM_GEN1_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + PWM_GEN1_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + PWM_GEN1_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + PWM_GEN1_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + PWM_GEN1_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + PWM_GEN1_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + PWM_GEN1_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + PWM_GEN1_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + PWM_GEN1_B_DT0_Msk = 0x300000 + // Position of DT1 field. + PWM_GEN1_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + PWM_GEN1_B_DT1_Msk = 0xc00000 + + // DB1_CFG: dead time type selection and configuration + // Position of DB1_FED_UPMETHOD field. + PWM_DB1_CFG_DB1_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DB1_FED_UPMETHOD field. + PWM_DB1_CFG_DB1_FED_UPMETHOD_Msk = 0xf + // Position of DB1_RED_UPMETHOD field. + PWM_DB1_CFG_DB1_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DB1_RED_UPMETHOD field. + PWM_DB1_CFG_DB1_RED_UPMETHOD_Msk = 0xf0 + // Position of DB1_DEB_MODE field. + PWM_DB1_CFG_DB1_DEB_MODE_Pos = 0x8 + // Bit mask of DB1_DEB_MODE field. + PWM_DB1_CFG_DB1_DEB_MODE_Msk = 0x100 + // Bit DB1_DEB_MODE. + PWM_DB1_CFG_DB1_DEB_MODE = 0x100 + // Position of DB1_A_OUTSWAP field. + PWM_DB1_CFG_DB1_A_OUTSWAP_Pos = 0x9 + // Bit mask of DB1_A_OUTSWAP field. + PWM_DB1_CFG_DB1_A_OUTSWAP_Msk = 0x200 + // Bit DB1_A_OUTSWAP. + PWM_DB1_CFG_DB1_A_OUTSWAP = 0x200 + // Position of DB1_B_OUTSWAP field. + PWM_DB1_CFG_DB1_B_OUTSWAP_Pos = 0xa + // Bit mask of DB1_B_OUTSWAP field. + PWM_DB1_CFG_DB1_B_OUTSWAP_Msk = 0x400 + // Bit DB1_B_OUTSWAP. + PWM_DB1_CFG_DB1_B_OUTSWAP = 0x400 + // Position of DB1_RED_INSEL field. + PWM_DB1_CFG_DB1_RED_INSEL_Pos = 0xb + // Bit mask of DB1_RED_INSEL field. + PWM_DB1_CFG_DB1_RED_INSEL_Msk = 0x800 + // Bit DB1_RED_INSEL. + PWM_DB1_CFG_DB1_RED_INSEL = 0x800 + // Position of DB1_FED_INSEL field. + PWM_DB1_CFG_DB1_FED_INSEL_Pos = 0xc + // Bit mask of DB1_FED_INSEL field. + PWM_DB1_CFG_DB1_FED_INSEL_Msk = 0x1000 + // Bit DB1_FED_INSEL. + PWM_DB1_CFG_DB1_FED_INSEL = 0x1000 + // Position of DB1_RED_OUTINVERT field. + PWM_DB1_CFG_DB1_RED_OUTINVERT_Pos = 0xd + // Bit mask of DB1_RED_OUTINVERT field. + PWM_DB1_CFG_DB1_RED_OUTINVERT_Msk = 0x2000 + // Bit DB1_RED_OUTINVERT. + PWM_DB1_CFG_DB1_RED_OUTINVERT = 0x2000 + // Position of DB1_FED_OUTINVERT field. + PWM_DB1_CFG_DB1_FED_OUTINVERT_Pos = 0xe + // Bit mask of DB1_FED_OUTINVERT field. + PWM_DB1_CFG_DB1_FED_OUTINVERT_Msk = 0x4000 + // Bit DB1_FED_OUTINVERT. + PWM_DB1_CFG_DB1_FED_OUTINVERT = 0x4000 + // Position of DB1_A_OUTBYPASS field. + PWM_DB1_CFG_DB1_A_OUTBYPASS_Pos = 0xf + // Bit mask of DB1_A_OUTBYPASS field. + PWM_DB1_CFG_DB1_A_OUTBYPASS_Msk = 0x8000 + // Bit DB1_A_OUTBYPASS. + PWM_DB1_CFG_DB1_A_OUTBYPASS = 0x8000 + // Position of DB1_B_OUTBYPASS field. + PWM_DB1_CFG_DB1_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DB1_B_OUTBYPASS field. + PWM_DB1_CFG_DB1_B_OUTBYPASS_Msk = 0x10000 + // Bit DB1_B_OUTBYPASS. + PWM_DB1_CFG_DB1_B_OUTBYPASS = 0x10000 + // Position of DB1_CLK_SEL field. + PWM_DB1_CFG_DB1_CLK_SEL_Pos = 0x11 + // Bit mask of DB1_CLK_SEL field. + PWM_DB1_CFG_DB1_CLK_SEL_Msk = 0x20000 + // Bit DB1_CLK_SEL. + PWM_DB1_CFG_DB1_CLK_SEL = 0x20000 + + // DB1_FED_CFG: Shadow register for falling edge delay (FED). + // Position of DB1_FED field. + PWM_DB1_FED_CFG_DB1_FED_Pos = 0x0 + // Bit mask of DB1_FED field. + PWM_DB1_FED_CFG_DB1_FED_Msk = 0xffff + + // DB1_RED_CFG: Shadow register for rising edge delay (RED). + // Position of DB1_RED field. + PWM_DB1_RED_CFG_DB1_RED_Pos = 0x0 + // Bit mask of DB1_RED field. + PWM_DB1_RED_CFG_DB1_RED_Msk = 0xffff + + // CHOPPER1_CFG: Carrier enable and configuratoin + // Position of CHOPPER1_EN field. + PWM_CHOPPER1_CFG_CHOPPER1_EN_Pos = 0x0 + // Bit mask of CHOPPER1_EN field. + PWM_CHOPPER1_CFG_CHOPPER1_EN_Msk = 0x1 + // Bit CHOPPER1_EN. + PWM_CHOPPER1_CFG_CHOPPER1_EN = 0x1 + // Position of CHOPPER1_PRESCALE field. + PWM_CHOPPER1_CFG_CHOPPER1_PRESCALE_Pos = 0x1 + // Bit mask of CHOPPER1_PRESCALE field. + PWM_CHOPPER1_CFG_CHOPPER1_PRESCALE_Msk = 0x1e + // Position of CHOPPER1_DUTY field. + PWM_CHOPPER1_CFG_CHOPPER1_DUTY_Pos = 0x5 + // Bit mask of CHOPPER1_DUTY field. + PWM_CHOPPER1_CFG_CHOPPER1_DUTY_Msk = 0xe0 + // Position of CHOPPER1_OSHTWTH field. + PWM_CHOPPER1_CFG_CHOPPER1_OSHTWTH_Pos = 0x8 + // Bit mask of CHOPPER1_OSHTWTH field. + PWM_CHOPPER1_CFG_CHOPPER1_OSHTWTH_Msk = 0xf00 + // Position of CHOPPER1_OUT_INVERT field. + PWM_CHOPPER1_CFG_CHOPPER1_OUT_INVERT_Pos = 0xc + // Bit mask of CHOPPER1_OUT_INVERT field. + PWM_CHOPPER1_CFG_CHOPPER1_OUT_INVERT_Msk = 0x1000 + // Bit CHOPPER1_OUT_INVERT. + PWM_CHOPPER1_CFG_CHOPPER1_OUT_INVERT = 0x1000 + // Position of CHOPPER1_IN_INVERT field. + PWM_CHOPPER1_CFG_CHOPPER1_IN_INVERT_Pos = 0xd + // Bit mask of CHOPPER1_IN_INVERT field. + PWM_CHOPPER1_CFG_CHOPPER1_IN_INVERT_Msk = 0x2000 + // Bit CHOPPER1_IN_INVERT. + PWM_CHOPPER1_CFG_CHOPPER1_IN_INVERT = 0x2000 + + // TZ1_CFG0: Actions on PWM1A and PWM1B trip events + // Position of TZ1_SW_CBC field. + PWM_TZ1_CFG0_TZ1_SW_CBC_Pos = 0x0 + // Bit mask of TZ1_SW_CBC field. + PWM_TZ1_CFG0_TZ1_SW_CBC_Msk = 0x1 + // Bit TZ1_SW_CBC. + PWM_TZ1_CFG0_TZ1_SW_CBC = 0x1 + // Position of TZ1_F2_CBC field. + PWM_TZ1_CFG0_TZ1_F2_CBC_Pos = 0x1 + // Bit mask of TZ1_F2_CBC field. + PWM_TZ1_CFG0_TZ1_F2_CBC_Msk = 0x2 + // Bit TZ1_F2_CBC. + PWM_TZ1_CFG0_TZ1_F2_CBC = 0x2 + // Position of TZ1_F1_CBC field. + PWM_TZ1_CFG0_TZ1_F1_CBC_Pos = 0x2 + // Bit mask of TZ1_F1_CBC field. + PWM_TZ1_CFG0_TZ1_F1_CBC_Msk = 0x4 + // Bit TZ1_F1_CBC. + PWM_TZ1_CFG0_TZ1_F1_CBC = 0x4 + // Position of TZ1_F0_CBC field. + PWM_TZ1_CFG0_TZ1_F0_CBC_Pos = 0x3 + // Bit mask of TZ1_F0_CBC field. + PWM_TZ1_CFG0_TZ1_F0_CBC_Msk = 0x8 + // Bit TZ1_F0_CBC. + PWM_TZ1_CFG0_TZ1_F0_CBC = 0x8 + // Position of TZ1_SW_OST field. + PWM_TZ1_CFG0_TZ1_SW_OST_Pos = 0x4 + // Bit mask of TZ1_SW_OST field. + PWM_TZ1_CFG0_TZ1_SW_OST_Msk = 0x10 + // Bit TZ1_SW_OST. + PWM_TZ1_CFG0_TZ1_SW_OST = 0x10 + // Position of TZ1_F2_OST field. + PWM_TZ1_CFG0_TZ1_F2_OST_Pos = 0x5 + // Bit mask of TZ1_F2_OST field. + PWM_TZ1_CFG0_TZ1_F2_OST_Msk = 0x20 + // Bit TZ1_F2_OST. + PWM_TZ1_CFG0_TZ1_F2_OST = 0x20 + // Position of TZ1_F1_OST field. + PWM_TZ1_CFG0_TZ1_F1_OST_Pos = 0x6 + // Bit mask of TZ1_F1_OST field. + PWM_TZ1_CFG0_TZ1_F1_OST_Msk = 0x40 + // Bit TZ1_F1_OST. + PWM_TZ1_CFG0_TZ1_F1_OST = 0x40 + // Position of TZ1_F0_OST field. + PWM_TZ1_CFG0_TZ1_F0_OST_Pos = 0x7 + // Bit mask of TZ1_F0_OST field. + PWM_TZ1_CFG0_TZ1_F0_OST_Msk = 0x80 + // Bit TZ1_F0_OST. + PWM_TZ1_CFG0_TZ1_F0_OST = 0x80 + // Position of TZ1_A_CBC_D field. + PWM_TZ1_CFG0_TZ1_A_CBC_D_Pos = 0x8 + // Bit mask of TZ1_A_CBC_D field. + PWM_TZ1_CFG0_TZ1_A_CBC_D_Msk = 0x300 + // Position of TZ1_A_CBC_U field. + PWM_TZ1_CFG0_TZ1_A_CBC_U_Pos = 0xa + // Bit mask of TZ1_A_CBC_U field. + PWM_TZ1_CFG0_TZ1_A_CBC_U_Msk = 0xc00 + // Position of TZ1_A_OST_D field. + PWM_TZ1_CFG0_TZ1_A_OST_D_Pos = 0xc + // Bit mask of TZ1_A_OST_D field. + PWM_TZ1_CFG0_TZ1_A_OST_D_Msk = 0x3000 + // Position of TZ1_A_OST_U field. + PWM_TZ1_CFG0_TZ1_A_OST_U_Pos = 0xe + // Bit mask of TZ1_A_OST_U field. + PWM_TZ1_CFG0_TZ1_A_OST_U_Msk = 0xc000 + // Position of TZ1_B_CBC_D field. + PWM_TZ1_CFG0_TZ1_B_CBC_D_Pos = 0x10 + // Bit mask of TZ1_B_CBC_D field. + PWM_TZ1_CFG0_TZ1_B_CBC_D_Msk = 0x30000 + // Position of TZ1_B_CBC_U field. + PWM_TZ1_CFG0_TZ1_B_CBC_U_Pos = 0x12 + // Bit mask of TZ1_B_CBC_U field. + PWM_TZ1_CFG0_TZ1_B_CBC_U_Msk = 0xc0000 + // Position of TZ1_B_OST_D field. + PWM_TZ1_CFG0_TZ1_B_OST_D_Pos = 0x14 + // Bit mask of TZ1_B_OST_D field. + PWM_TZ1_CFG0_TZ1_B_OST_D_Msk = 0x300000 + // Position of TZ1_B_OST_U field. + PWM_TZ1_CFG0_TZ1_B_OST_U_Pos = 0x16 + // Bit mask of TZ1_B_OST_U field. + PWM_TZ1_CFG0_TZ1_B_OST_U_Msk = 0xc00000 + + // TZ1_CFG1: Software triggers for fault handler actions + // Position of TZ1_CLR_OST field. + PWM_TZ1_CFG1_TZ1_CLR_OST_Pos = 0x0 + // Bit mask of TZ1_CLR_OST field. + PWM_TZ1_CFG1_TZ1_CLR_OST_Msk = 0x1 + // Bit TZ1_CLR_OST. + PWM_TZ1_CFG1_TZ1_CLR_OST = 0x1 + // Position of TZ1_CBCPULSE field. + PWM_TZ1_CFG1_TZ1_CBCPULSE_Pos = 0x1 + // Bit mask of TZ1_CBCPULSE field. + PWM_TZ1_CFG1_TZ1_CBCPULSE_Msk = 0x6 + // Position of TZ1_FORCE_CBC field. + PWM_TZ1_CFG1_TZ1_FORCE_CBC_Pos = 0x3 + // Bit mask of TZ1_FORCE_CBC field. + PWM_TZ1_CFG1_TZ1_FORCE_CBC_Msk = 0x8 + // Bit TZ1_FORCE_CBC. + PWM_TZ1_CFG1_TZ1_FORCE_CBC = 0x8 + // Position of TZ1_FORCE_OST field. + PWM_TZ1_CFG1_TZ1_FORCE_OST_Pos = 0x4 + // Bit mask of TZ1_FORCE_OST field. + PWM_TZ1_CFG1_TZ1_FORCE_OST_Msk = 0x10 + // Bit TZ1_FORCE_OST. + PWM_TZ1_CFG1_TZ1_FORCE_OST = 0x10 + + // TZ1_STATUS: Status of fault events. + // Position of TZ1_CBC_ON field. + PWM_TZ1_STATUS_TZ1_CBC_ON_Pos = 0x0 + // Bit mask of TZ1_CBC_ON field. + PWM_TZ1_STATUS_TZ1_CBC_ON_Msk = 0x1 + // Bit TZ1_CBC_ON. + PWM_TZ1_STATUS_TZ1_CBC_ON = 0x1 + // Position of TZ1_OST_ON field. + PWM_TZ1_STATUS_TZ1_OST_ON_Pos = 0x1 + // Bit mask of TZ1_OST_ON field. + PWM_TZ1_STATUS_TZ1_OST_ON_Msk = 0x2 + // Bit TZ1_OST_ON. + PWM_TZ1_STATUS_TZ1_OST_ON = 0x2 + + // CMPR2_CFG: Transfer status and update method for time stamp registers A and B + // Position of CMPR2_A_UPMETHOD field. + PWM_CMPR2_CFG_CMPR2_A_UPMETHOD_Pos = 0x0 + // Bit mask of CMPR2_A_UPMETHOD field. + PWM_CMPR2_CFG_CMPR2_A_UPMETHOD_Msk = 0xf + // Position of CMPR2_B_UPMETHOD field. + PWM_CMPR2_CFG_CMPR2_B_UPMETHOD_Pos = 0x4 + // Bit mask of CMPR2_B_UPMETHOD field. + PWM_CMPR2_CFG_CMPR2_B_UPMETHOD_Msk = 0xf0 + // Position of CMPR2_A_SHDW_FULL field. + PWM_CMPR2_CFG_CMPR2_A_SHDW_FULL_Pos = 0x8 + // Bit mask of CMPR2_A_SHDW_FULL field. + PWM_CMPR2_CFG_CMPR2_A_SHDW_FULL_Msk = 0x100 + // Bit CMPR2_A_SHDW_FULL. + PWM_CMPR2_CFG_CMPR2_A_SHDW_FULL = 0x100 + // Position of CMPR2_B_SHDW_FULL field. + PWM_CMPR2_CFG_CMPR2_B_SHDW_FULL_Pos = 0x9 + // Bit mask of CMPR2_B_SHDW_FULL field. + PWM_CMPR2_CFG_CMPR2_B_SHDW_FULL_Msk = 0x200 + // Bit CMPR2_B_SHDW_FULL. + PWM_CMPR2_CFG_CMPR2_B_SHDW_FULL = 0x200 + + // CMPR2_VALUE0: Shadow register for register A. + // Position of CMPR2_A field. + PWM_CMPR2_VALUE0_CMPR2_A_Pos = 0x0 + // Bit mask of CMPR2_A field. + PWM_CMPR2_VALUE0_CMPR2_A_Msk = 0xffff + + // CMPR2_VALUE1: Shadow register for register B. + // Position of CMPR2_B field. + PWM_CMPR2_VALUE1_CMPR2_B_Pos = 0x0 + // Bit mask of CMPR2_B field. + PWM_CMPR2_VALUE1_CMPR2_B_Msk = 0xffff + + // GEN2_CFG0: Fault event T0 and T1 handling + // Position of GEN2_CFG_UPMETHOD field. + PWM_GEN2_CFG0_GEN2_CFG_UPMETHOD_Pos = 0x0 + // Bit mask of GEN2_CFG_UPMETHOD field. + PWM_GEN2_CFG0_GEN2_CFG_UPMETHOD_Msk = 0xf + // Position of GEN2_T0_SEL field. + PWM_GEN2_CFG0_GEN2_T0_SEL_Pos = 0x4 + // Bit mask of GEN2_T0_SEL field. + PWM_GEN2_CFG0_GEN2_T0_SEL_Msk = 0x70 + // Position of GEN2_T1_SEL field. + PWM_GEN2_CFG0_GEN2_T1_SEL_Pos = 0x7 + // Bit mask of GEN2_T1_SEL field. + PWM_GEN2_CFG0_GEN2_T1_SEL_Msk = 0x380 + + // GEN2_FORCE: Permissives to force PWM2A and PWM2B outputs by software + // Position of GEN2_CNTUFORCE_UPMETHOD field. + PWM_GEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD_Pos = 0x0 + // Bit mask of GEN2_CNTUFORCE_UPMETHOD field. + PWM_GEN2_FORCE_GEN2_CNTUFORCE_UPMETHOD_Msk = 0x3f + // Position of GEN2_A_CNTUFORCE_MODE field. + PWM_GEN2_FORCE_GEN2_A_CNTUFORCE_MODE_Pos = 0x6 + // Bit mask of GEN2_A_CNTUFORCE_MODE field. + PWM_GEN2_FORCE_GEN2_A_CNTUFORCE_MODE_Msk = 0xc0 + // Position of GEN2_B_CNTUFORCE_MODE field. + PWM_GEN2_FORCE_GEN2_B_CNTUFORCE_MODE_Pos = 0x8 + // Bit mask of GEN2_B_CNTUFORCE_MODE field. + PWM_GEN2_FORCE_GEN2_B_CNTUFORCE_MODE_Msk = 0x300 + // Position of GEN2_A_NCIFORCE field. + PWM_GEN2_FORCE_GEN2_A_NCIFORCE_Pos = 0xa + // Bit mask of GEN2_A_NCIFORCE field. + PWM_GEN2_FORCE_GEN2_A_NCIFORCE_Msk = 0x400 + // Bit GEN2_A_NCIFORCE. + PWM_GEN2_FORCE_GEN2_A_NCIFORCE = 0x400 + // Position of GEN2_A_NCIFORCE_MODE field. + PWM_GEN2_FORCE_GEN2_A_NCIFORCE_MODE_Pos = 0xb + // Bit mask of GEN2_A_NCIFORCE_MODE field. + PWM_GEN2_FORCE_GEN2_A_NCIFORCE_MODE_Msk = 0x1800 + // Position of GEN2_B_NCIFORCE field. + PWM_GEN2_FORCE_GEN2_B_NCIFORCE_Pos = 0xd + // Bit mask of GEN2_B_NCIFORCE field. + PWM_GEN2_FORCE_GEN2_B_NCIFORCE_Msk = 0x2000 + // Bit GEN2_B_NCIFORCE. + PWM_GEN2_FORCE_GEN2_B_NCIFORCE = 0x2000 + // Position of GEN2_B_NCIFORCE_MODE field. + PWM_GEN2_FORCE_GEN2_B_NCIFORCE_MODE_Pos = 0xe + // Bit mask of GEN2_B_NCIFORCE_MODE field. + PWM_GEN2_FORCE_GEN2_B_NCIFORCE_MODE_Msk = 0xc000 + + // GEN2_A: Actions triggered by events on PWM2A + // Position of UTEZ field. + PWM_GEN2_A_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + PWM_GEN2_A_UTEZ_Msk = 0x3 + // Position of UTEP field. + PWM_GEN2_A_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + PWM_GEN2_A_UTEP_Msk = 0xc + // Position of UTEA field. + PWM_GEN2_A_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + PWM_GEN2_A_UTEA_Msk = 0x30 + // Position of UTEB field. + PWM_GEN2_A_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + PWM_GEN2_A_UTEB_Msk = 0xc0 + // Position of UT0 field. + PWM_GEN2_A_UT0_Pos = 0x8 + // Bit mask of UT0 field. + PWM_GEN2_A_UT0_Msk = 0x300 + // Position of UT1 field. + PWM_GEN2_A_UT1_Pos = 0xa + // Bit mask of UT1 field. + PWM_GEN2_A_UT1_Msk = 0xc00 + // Position of DTEZ field. + PWM_GEN2_A_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + PWM_GEN2_A_DTEZ_Msk = 0x3000 + // Position of DTEP field. + PWM_GEN2_A_DTEP_Pos = 0xe + // Bit mask of DTEP field. + PWM_GEN2_A_DTEP_Msk = 0xc000 + // Position of DTEA field. + PWM_GEN2_A_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + PWM_GEN2_A_DTEA_Msk = 0x30000 + // Position of DTEB field. + PWM_GEN2_A_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + PWM_GEN2_A_DTEB_Msk = 0xc0000 + // Position of DT0 field. + PWM_GEN2_A_DT0_Pos = 0x14 + // Bit mask of DT0 field. + PWM_GEN2_A_DT0_Msk = 0x300000 + // Position of DT1 field. + PWM_GEN2_A_DT1_Pos = 0x16 + // Bit mask of DT1 field. + PWM_GEN2_A_DT1_Msk = 0xc00000 + + // GEN2_B: Actions triggered by events on PWM2B + // Position of UTEZ field. + PWM_GEN2_B_UTEZ_Pos = 0x0 + // Bit mask of UTEZ field. + PWM_GEN2_B_UTEZ_Msk = 0x3 + // Position of UTEP field. + PWM_GEN2_B_UTEP_Pos = 0x2 + // Bit mask of UTEP field. + PWM_GEN2_B_UTEP_Msk = 0xc + // Position of UTEA field. + PWM_GEN2_B_UTEA_Pos = 0x4 + // Bit mask of UTEA field. + PWM_GEN2_B_UTEA_Msk = 0x30 + // Position of UTEB field. + PWM_GEN2_B_UTEB_Pos = 0x6 + // Bit mask of UTEB field. + PWM_GEN2_B_UTEB_Msk = 0xc0 + // Position of UT0 field. + PWM_GEN2_B_UT0_Pos = 0x8 + // Bit mask of UT0 field. + PWM_GEN2_B_UT0_Msk = 0x300 + // Position of UT1 field. + PWM_GEN2_B_UT1_Pos = 0xa + // Bit mask of UT1 field. + PWM_GEN2_B_UT1_Msk = 0xc00 + // Position of DTEZ field. + PWM_GEN2_B_DTEZ_Pos = 0xc + // Bit mask of DTEZ field. + PWM_GEN2_B_DTEZ_Msk = 0x3000 + // Position of DTEP field. + PWM_GEN2_B_DTEP_Pos = 0xe + // Bit mask of DTEP field. + PWM_GEN2_B_DTEP_Msk = 0xc000 + // Position of DTEA field. + PWM_GEN2_B_DTEA_Pos = 0x10 + // Bit mask of DTEA field. + PWM_GEN2_B_DTEA_Msk = 0x30000 + // Position of DTEB field. + PWM_GEN2_B_DTEB_Pos = 0x12 + // Bit mask of DTEB field. + PWM_GEN2_B_DTEB_Msk = 0xc0000 + // Position of DT0 field. + PWM_GEN2_B_DT0_Pos = 0x14 + // Bit mask of DT0 field. + PWM_GEN2_B_DT0_Msk = 0x300000 + // Position of DT1 field. + PWM_GEN2_B_DT1_Pos = 0x16 + // Bit mask of DT1 field. + PWM_GEN2_B_DT1_Msk = 0xc00000 + + // DB2_CFG: dead time type selection and configuration + // Position of DB2_FED_UPMETHOD field. + PWM_DB2_CFG_DB2_FED_UPMETHOD_Pos = 0x0 + // Bit mask of DB2_FED_UPMETHOD field. + PWM_DB2_CFG_DB2_FED_UPMETHOD_Msk = 0xf + // Position of DB2_RED_UPMETHOD field. + PWM_DB2_CFG_DB2_RED_UPMETHOD_Pos = 0x4 + // Bit mask of DB2_RED_UPMETHOD field. + PWM_DB2_CFG_DB2_RED_UPMETHOD_Msk = 0xf0 + // Position of DB2_DEB_MODE field. + PWM_DB2_CFG_DB2_DEB_MODE_Pos = 0x8 + // Bit mask of DB2_DEB_MODE field. + PWM_DB2_CFG_DB2_DEB_MODE_Msk = 0x100 + // Bit DB2_DEB_MODE. + PWM_DB2_CFG_DB2_DEB_MODE = 0x100 + // Position of DB2_A_OUTSWAP field. + PWM_DB2_CFG_DB2_A_OUTSWAP_Pos = 0x9 + // Bit mask of DB2_A_OUTSWAP field. + PWM_DB2_CFG_DB2_A_OUTSWAP_Msk = 0x200 + // Bit DB2_A_OUTSWAP. + PWM_DB2_CFG_DB2_A_OUTSWAP = 0x200 + // Position of DB2_B_OUTSWAP field. + PWM_DB2_CFG_DB2_B_OUTSWAP_Pos = 0xa + // Bit mask of DB2_B_OUTSWAP field. + PWM_DB2_CFG_DB2_B_OUTSWAP_Msk = 0x400 + // Bit DB2_B_OUTSWAP. + PWM_DB2_CFG_DB2_B_OUTSWAP = 0x400 + // Position of DB2_RED_INSEL field. + PWM_DB2_CFG_DB2_RED_INSEL_Pos = 0xb + // Bit mask of DB2_RED_INSEL field. + PWM_DB2_CFG_DB2_RED_INSEL_Msk = 0x800 + // Bit DB2_RED_INSEL. + PWM_DB2_CFG_DB2_RED_INSEL = 0x800 + // Position of DB2_FED_INSEL field. + PWM_DB2_CFG_DB2_FED_INSEL_Pos = 0xc + // Bit mask of DB2_FED_INSEL field. + PWM_DB2_CFG_DB2_FED_INSEL_Msk = 0x1000 + // Bit DB2_FED_INSEL. + PWM_DB2_CFG_DB2_FED_INSEL = 0x1000 + // Position of DB2_RED_OUTINVERT field. + PWM_DB2_CFG_DB2_RED_OUTINVERT_Pos = 0xd + // Bit mask of DB2_RED_OUTINVERT field. + PWM_DB2_CFG_DB2_RED_OUTINVERT_Msk = 0x2000 + // Bit DB2_RED_OUTINVERT. + PWM_DB2_CFG_DB2_RED_OUTINVERT = 0x2000 + // Position of DB2_FED_OUTINVERT field. + PWM_DB2_CFG_DB2_FED_OUTINVERT_Pos = 0xe + // Bit mask of DB2_FED_OUTINVERT field. + PWM_DB2_CFG_DB2_FED_OUTINVERT_Msk = 0x4000 + // Bit DB2_FED_OUTINVERT. + PWM_DB2_CFG_DB2_FED_OUTINVERT = 0x4000 + // Position of DB2_A_OUTBYPASS field. + PWM_DB2_CFG_DB2_A_OUTBYPASS_Pos = 0xf + // Bit mask of DB2_A_OUTBYPASS field. + PWM_DB2_CFG_DB2_A_OUTBYPASS_Msk = 0x8000 + // Bit DB2_A_OUTBYPASS. + PWM_DB2_CFG_DB2_A_OUTBYPASS = 0x8000 + // Position of DB2_B_OUTBYPASS field. + PWM_DB2_CFG_DB2_B_OUTBYPASS_Pos = 0x10 + // Bit mask of DB2_B_OUTBYPASS field. + PWM_DB2_CFG_DB2_B_OUTBYPASS_Msk = 0x10000 + // Bit DB2_B_OUTBYPASS. + PWM_DB2_CFG_DB2_B_OUTBYPASS = 0x10000 + // Position of DB2_CLK_SEL field. + PWM_DB2_CFG_DB2_CLK_SEL_Pos = 0x11 + // Bit mask of DB2_CLK_SEL field. + PWM_DB2_CFG_DB2_CLK_SEL_Msk = 0x20000 + // Bit DB2_CLK_SEL. + PWM_DB2_CFG_DB2_CLK_SEL = 0x20000 + + // DB2_FED_CFG: Shadow register for falling edge delay (FED). + // Position of DB2_FED field. + PWM_DB2_FED_CFG_DB2_FED_Pos = 0x0 + // Bit mask of DB2_FED field. + PWM_DB2_FED_CFG_DB2_FED_Msk = 0xffff + + // DB2_RED_CFG: Shadow register for rising edge delay (RED). + // Position of DB2_RED field. + PWM_DB2_RED_CFG_DB2_RED_Pos = 0x0 + // Bit mask of DB2_RED field. + PWM_DB2_RED_CFG_DB2_RED_Msk = 0xffff + + // CHOPPER2_CFG: Carrier enable and configuratoin + // Position of CHOPPER2_EN field. + PWM_CHOPPER2_CFG_CHOPPER2_EN_Pos = 0x0 + // Bit mask of CHOPPER2_EN field. + PWM_CHOPPER2_CFG_CHOPPER2_EN_Msk = 0x1 + // Bit CHOPPER2_EN. + PWM_CHOPPER2_CFG_CHOPPER2_EN = 0x1 + // Position of CHOPPER2_PRESCALE field. + PWM_CHOPPER2_CFG_CHOPPER2_PRESCALE_Pos = 0x1 + // Bit mask of CHOPPER2_PRESCALE field. + PWM_CHOPPER2_CFG_CHOPPER2_PRESCALE_Msk = 0x1e + // Position of CHOPPER2_DUTY field. + PWM_CHOPPER2_CFG_CHOPPER2_DUTY_Pos = 0x5 + // Bit mask of CHOPPER2_DUTY field. + PWM_CHOPPER2_CFG_CHOPPER2_DUTY_Msk = 0xe0 + // Position of CHOPPER2_OSHTWTH field. + PWM_CHOPPER2_CFG_CHOPPER2_OSHTWTH_Pos = 0x8 + // Bit mask of CHOPPER2_OSHTWTH field. + PWM_CHOPPER2_CFG_CHOPPER2_OSHTWTH_Msk = 0xf00 + // Position of CHOPPER2_OUT_INVERT field. + PWM_CHOPPER2_CFG_CHOPPER2_OUT_INVERT_Pos = 0xc + // Bit mask of CHOPPER2_OUT_INVERT field. + PWM_CHOPPER2_CFG_CHOPPER2_OUT_INVERT_Msk = 0x1000 + // Bit CHOPPER2_OUT_INVERT. + PWM_CHOPPER2_CFG_CHOPPER2_OUT_INVERT = 0x1000 + // Position of CHOPPER2_IN_INVERT field. + PWM_CHOPPER2_CFG_CHOPPER2_IN_INVERT_Pos = 0xd + // Bit mask of CHOPPER2_IN_INVERT field. + PWM_CHOPPER2_CFG_CHOPPER2_IN_INVERT_Msk = 0x2000 + // Bit CHOPPER2_IN_INVERT. + PWM_CHOPPER2_CFG_CHOPPER2_IN_INVERT = 0x2000 + + // TZ2_CFG0: Actions on PWM2A and PWM2B trip events + // Position of TZ2_SW_CBC field. + PWM_TZ2_CFG0_TZ2_SW_CBC_Pos = 0x0 + // Bit mask of TZ2_SW_CBC field. + PWM_TZ2_CFG0_TZ2_SW_CBC_Msk = 0x1 + // Bit TZ2_SW_CBC. + PWM_TZ2_CFG0_TZ2_SW_CBC = 0x1 + // Position of TZ2_F2_CBC field. + PWM_TZ2_CFG0_TZ2_F2_CBC_Pos = 0x1 + // Bit mask of TZ2_F2_CBC field. + PWM_TZ2_CFG0_TZ2_F2_CBC_Msk = 0x2 + // Bit TZ2_F2_CBC. + PWM_TZ2_CFG0_TZ2_F2_CBC = 0x2 + // Position of TZ2_F1_CBC field. + PWM_TZ2_CFG0_TZ2_F1_CBC_Pos = 0x2 + // Bit mask of TZ2_F1_CBC field. + PWM_TZ2_CFG0_TZ2_F1_CBC_Msk = 0x4 + // Bit TZ2_F1_CBC. + PWM_TZ2_CFG0_TZ2_F1_CBC = 0x4 + // Position of TZ2_F0_CBC field. + PWM_TZ2_CFG0_TZ2_F0_CBC_Pos = 0x3 + // Bit mask of TZ2_F0_CBC field. + PWM_TZ2_CFG0_TZ2_F0_CBC_Msk = 0x8 + // Bit TZ2_F0_CBC. + PWM_TZ2_CFG0_TZ2_F0_CBC = 0x8 + // Position of TZ2_SW_OST field. + PWM_TZ2_CFG0_TZ2_SW_OST_Pos = 0x4 + // Bit mask of TZ2_SW_OST field. + PWM_TZ2_CFG0_TZ2_SW_OST_Msk = 0x10 + // Bit TZ2_SW_OST. + PWM_TZ2_CFG0_TZ2_SW_OST = 0x10 + // Position of TZ2_F2_OST field. + PWM_TZ2_CFG0_TZ2_F2_OST_Pos = 0x5 + // Bit mask of TZ2_F2_OST field. + PWM_TZ2_CFG0_TZ2_F2_OST_Msk = 0x20 + // Bit TZ2_F2_OST. + PWM_TZ2_CFG0_TZ2_F2_OST = 0x20 + // Position of TZ2_F1_OST field. + PWM_TZ2_CFG0_TZ2_F1_OST_Pos = 0x6 + // Bit mask of TZ2_F1_OST field. + PWM_TZ2_CFG0_TZ2_F1_OST_Msk = 0x40 + // Bit TZ2_F1_OST. + PWM_TZ2_CFG0_TZ2_F1_OST = 0x40 + // Position of TZ2_F0_OST field. + PWM_TZ2_CFG0_TZ2_F0_OST_Pos = 0x7 + // Bit mask of TZ2_F0_OST field. + PWM_TZ2_CFG0_TZ2_F0_OST_Msk = 0x80 + // Bit TZ2_F0_OST. + PWM_TZ2_CFG0_TZ2_F0_OST = 0x80 + // Position of TZ2_A_CBC_D field. + PWM_TZ2_CFG0_TZ2_A_CBC_D_Pos = 0x8 + // Bit mask of TZ2_A_CBC_D field. + PWM_TZ2_CFG0_TZ2_A_CBC_D_Msk = 0x300 + // Position of TZ2_A_CBC_U field. + PWM_TZ2_CFG0_TZ2_A_CBC_U_Pos = 0xa + // Bit mask of TZ2_A_CBC_U field. + PWM_TZ2_CFG0_TZ2_A_CBC_U_Msk = 0xc00 + // Position of TZ2_A_OST_D field. + PWM_TZ2_CFG0_TZ2_A_OST_D_Pos = 0xc + // Bit mask of TZ2_A_OST_D field. + PWM_TZ2_CFG0_TZ2_A_OST_D_Msk = 0x3000 + // Position of TZ2_A_OST_U field. + PWM_TZ2_CFG0_TZ2_A_OST_U_Pos = 0xe + // Bit mask of TZ2_A_OST_U field. + PWM_TZ2_CFG0_TZ2_A_OST_U_Msk = 0xc000 + // Position of TZ2_B_CBC_D field. + PWM_TZ2_CFG0_TZ2_B_CBC_D_Pos = 0x10 + // Bit mask of TZ2_B_CBC_D field. + PWM_TZ2_CFG0_TZ2_B_CBC_D_Msk = 0x30000 + // Position of TZ2_B_CBC_U field. + PWM_TZ2_CFG0_TZ2_B_CBC_U_Pos = 0x12 + // Bit mask of TZ2_B_CBC_U field. + PWM_TZ2_CFG0_TZ2_B_CBC_U_Msk = 0xc0000 + // Position of TZ2_B_OST_D field. + PWM_TZ2_CFG0_TZ2_B_OST_D_Pos = 0x14 + // Bit mask of TZ2_B_OST_D field. + PWM_TZ2_CFG0_TZ2_B_OST_D_Msk = 0x300000 + // Position of TZ2_B_OST_U field. + PWM_TZ2_CFG0_TZ2_B_OST_U_Pos = 0x16 + // Bit mask of TZ2_B_OST_U field. + PWM_TZ2_CFG0_TZ2_B_OST_U_Msk = 0xc00000 + + // TZ2_CFG1: Software triggers for fault handler actions + // Position of TZ2_CLR_OST field. + PWM_TZ2_CFG1_TZ2_CLR_OST_Pos = 0x0 + // Bit mask of TZ2_CLR_OST field. + PWM_TZ2_CFG1_TZ2_CLR_OST_Msk = 0x1 + // Bit TZ2_CLR_OST. + PWM_TZ2_CFG1_TZ2_CLR_OST = 0x1 + // Position of TZ2_CBCPULSE field. + PWM_TZ2_CFG1_TZ2_CBCPULSE_Pos = 0x1 + // Bit mask of TZ2_CBCPULSE field. + PWM_TZ2_CFG1_TZ2_CBCPULSE_Msk = 0x6 + // Position of TZ2_FORCE_CBC field. + PWM_TZ2_CFG1_TZ2_FORCE_CBC_Pos = 0x3 + // Bit mask of TZ2_FORCE_CBC field. + PWM_TZ2_CFG1_TZ2_FORCE_CBC_Msk = 0x8 + // Bit TZ2_FORCE_CBC. + PWM_TZ2_CFG1_TZ2_FORCE_CBC = 0x8 + // Position of TZ2_FORCE_OST field. + PWM_TZ2_CFG1_TZ2_FORCE_OST_Pos = 0x4 + // Bit mask of TZ2_FORCE_OST field. + PWM_TZ2_CFG1_TZ2_FORCE_OST_Msk = 0x10 + // Bit TZ2_FORCE_OST. + PWM_TZ2_CFG1_TZ2_FORCE_OST = 0x10 + + // TZ2_STATUS: Status of fault events. + // Position of TZ2_CBC_ON field. + PWM_TZ2_STATUS_TZ2_CBC_ON_Pos = 0x0 + // Bit mask of TZ2_CBC_ON field. + PWM_TZ2_STATUS_TZ2_CBC_ON_Msk = 0x1 + // Bit TZ2_CBC_ON. + PWM_TZ2_STATUS_TZ2_CBC_ON = 0x1 + // Position of TZ2_OST_ON field. + PWM_TZ2_STATUS_TZ2_OST_ON_Pos = 0x1 + // Bit mask of TZ2_OST_ON field. + PWM_TZ2_STATUS_TZ2_OST_ON_Msk = 0x2 + // Bit TZ2_OST_ON. + PWM_TZ2_STATUS_TZ2_OST_ON = 0x2 + + // FAULT_DETECT: Fault detection configuration and status + // Position of F0_EN field. + PWM_FAULT_DETECT_F0_EN_Pos = 0x0 + // Bit mask of F0_EN field. + PWM_FAULT_DETECT_F0_EN_Msk = 0x1 + // Bit F0_EN. + PWM_FAULT_DETECT_F0_EN = 0x1 + // Position of F1_EN field. + PWM_FAULT_DETECT_F1_EN_Pos = 0x1 + // Bit mask of F1_EN field. + PWM_FAULT_DETECT_F1_EN_Msk = 0x2 + // Bit F1_EN. + PWM_FAULT_DETECT_F1_EN = 0x2 + // Position of F2_EN field. + PWM_FAULT_DETECT_F2_EN_Pos = 0x2 + // Bit mask of F2_EN field. + PWM_FAULT_DETECT_F2_EN_Msk = 0x4 + // Bit F2_EN. + PWM_FAULT_DETECT_F2_EN = 0x4 + // Position of F0_POLE field. + PWM_FAULT_DETECT_F0_POLE_Pos = 0x3 + // Bit mask of F0_POLE field. + PWM_FAULT_DETECT_F0_POLE_Msk = 0x8 + // Bit F0_POLE. + PWM_FAULT_DETECT_F0_POLE = 0x8 + // Position of F1_POLE field. + PWM_FAULT_DETECT_F1_POLE_Pos = 0x4 + // Bit mask of F1_POLE field. + PWM_FAULT_DETECT_F1_POLE_Msk = 0x10 + // Bit F1_POLE. + PWM_FAULT_DETECT_F1_POLE = 0x10 + // Position of F2_POLE field. + PWM_FAULT_DETECT_F2_POLE_Pos = 0x5 + // Bit mask of F2_POLE field. + PWM_FAULT_DETECT_F2_POLE_Msk = 0x20 + // Bit F2_POLE. + PWM_FAULT_DETECT_F2_POLE = 0x20 + // Position of EVENT_F0 field. + PWM_FAULT_DETECT_EVENT_F0_Pos = 0x6 + // Bit mask of EVENT_F0 field. + PWM_FAULT_DETECT_EVENT_F0_Msk = 0x40 + // Bit EVENT_F0. + PWM_FAULT_DETECT_EVENT_F0 = 0x40 + // Position of EVENT_F1 field. + PWM_FAULT_DETECT_EVENT_F1_Pos = 0x7 + // Bit mask of EVENT_F1 field. + PWM_FAULT_DETECT_EVENT_F1_Msk = 0x80 + // Bit EVENT_F1. + PWM_FAULT_DETECT_EVENT_F1 = 0x80 + // Position of EVENT_F2 field. + PWM_FAULT_DETECT_EVENT_F2_Pos = 0x8 + // Bit mask of EVENT_F2 field. + PWM_FAULT_DETECT_EVENT_F2_Msk = 0x100 + // Bit EVENT_F2. + PWM_FAULT_DETECT_EVENT_F2 = 0x100 + + // CAP_TIMER_CFG: Configure capture timer + // Position of CAP_TIMER_EN field. + PWM_CAP_TIMER_CFG_CAP_TIMER_EN_Pos = 0x0 + // Bit mask of CAP_TIMER_EN field. + PWM_CAP_TIMER_CFG_CAP_TIMER_EN_Msk = 0x1 + // Bit CAP_TIMER_EN. + PWM_CAP_TIMER_CFG_CAP_TIMER_EN = 0x1 + // Position of CAP_SYNCI_EN field. + PWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Pos = 0x1 + // Bit mask of CAP_SYNCI_EN field. + PWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Msk = 0x2 + // Bit CAP_SYNCI_EN. + PWM_CAP_TIMER_CFG_CAP_SYNCI_EN = 0x2 + // Position of CAP_SYNCI_SEL field. + PWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Pos = 0x2 + // Bit mask of CAP_SYNCI_SEL field. + PWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Msk = 0x1c + // Position of CAP_SYNC_SW field. + PWM_CAP_TIMER_CFG_CAP_SYNC_SW_Pos = 0x5 + // Bit mask of CAP_SYNC_SW field. + PWM_CAP_TIMER_CFG_CAP_SYNC_SW_Msk = 0x20 + // Bit CAP_SYNC_SW. + PWM_CAP_TIMER_CFG_CAP_SYNC_SW = 0x20 + + // CAP_TIMER_PHASE: Phase for capture timer sync + // Position of CAP_PHASE field. + PWM_CAP_TIMER_PHASE_CAP_PHASE_Pos = 0x0 + // Bit mask of CAP_PHASE field. + PWM_CAP_TIMER_PHASE_CAP_PHASE_Msk = 0xffffffff + + // CAP_CH0_CFG: Capture channel 0 configuration and enable + // Position of CAP0_EN field. + PWM_CAP_CH0_CFG_CAP0_EN_Pos = 0x0 + // Bit mask of CAP0_EN field. + PWM_CAP_CH0_CFG_CAP0_EN_Msk = 0x1 + // Bit CAP0_EN. + PWM_CAP_CH0_CFG_CAP0_EN = 0x1 + // Position of CAP0_MODE field. + PWM_CAP_CH0_CFG_CAP0_MODE_Pos = 0x1 + // Bit mask of CAP0_MODE field. + PWM_CAP_CH0_CFG_CAP0_MODE_Msk = 0x6 + // Position of CAP0_PRESCALE field. + PWM_CAP_CH0_CFG_CAP0_PRESCALE_Pos = 0x3 + // Bit mask of CAP0_PRESCALE field. + PWM_CAP_CH0_CFG_CAP0_PRESCALE_Msk = 0x7f8 + // Position of CAP0_IN_INVERT field. + PWM_CAP_CH0_CFG_CAP0_IN_INVERT_Pos = 0xb + // Bit mask of CAP0_IN_INVERT field. + PWM_CAP_CH0_CFG_CAP0_IN_INVERT_Msk = 0x800 + // Bit CAP0_IN_INVERT. + PWM_CAP_CH0_CFG_CAP0_IN_INVERT = 0x800 + // Position of CAP0_SW field. + PWM_CAP_CH0_CFG_CAP0_SW_Pos = 0xc + // Bit mask of CAP0_SW field. + PWM_CAP_CH0_CFG_CAP0_SW_Msk = 0x1000 + // Bit CAP0_SW. + PWM_CAP_CH0_CFG_CAP0_SW = 0x1000 + + // CAP_CH1_CFG: Capture channel 1 configuration and enable + // Position of CAP1_EN field. + PWM_CAP_CH1_CFG_CAP1_EN_Pos = 0x0 + // Bit mask of CAP1_EN field. + PWM_CAP_CH1_CFG_CAP1_EN_Msk = 0x1 + // Bit CAP1_EN. + PWM_CAP_CH1_CFG_CAP1_EN = 0x1 + // Position of CAP1_MODE field. + PWM_CAP_CH1_CFG_CAP1_MODE_Pos = 0x1 + // Bit mask of CAP1_MODE field. + PWM_CAP_CH1_CFG_CAP1_MODE_Msk = 0x6 + // Position of CAP1_PRESCALE field. + PWM_CAP_CH1_CFG_CAP1_PRESCALE_Pos = 0x3 + // Bit mask of CAP1_PRESCALE field. + PWM_CAP_CH1_CFG_CAP1_PRESCALE_Msk = 0x7f8 + // Position of CAP1_IN_INVERT field. + PWM_CAP_CH1_CFG_CAP1_IN_INVERT_Pos = 0xb + // Bit mask of CAP1_IN_INVERT field. + PWM_CAP_CH1_CFG_CAP1_IN_INVERT_Msk = 0x800 + // Bit CAP1_IN_INVERT. + PWM_CAP_CH1_CFG_CAP1_IN_INVERT = 0x800 + // Position of CAP1_SW field. + PWM_CAP_CH1_CFG_CAP1_SW_Pos = 0xc + // Bit mask of CAP1_SW field. + PWM_CAP_CH1_CFG_CAP1_SW_Msk = 0x1000 + // Bit CAP1_SW. + PWM_CAP_CH1_CFG_CAP1_SW = 0x1000 + + // CAP_CH2_CFG: Capture channel 2 configuration and enable + // Position of CAP2_EN field. + PWM_CAP_CH2_CFG_CAP2_EN_Pos = 0x0 + // Bit mask of CAP2_EN field. + PWM_CAP_CH2_CFG_CAP2_EN_Msk = 0x1 + // Bit CAP2_EN. + PWM_CAP_CH2_CFG_CAP2_EN = 0x1 + // Position of CAP2_MODE field. + PWM_CAP_CH2_CFG_CAP2_MODE_Pos = 0x1 + // Bit mask of CAP2_MODE field. + PWM_CAP_CH2_CFG_CAP2_MODE_Msk = 0x6 + // Position of CAP2_PRESCALE field. + PWM_CAP_CH2_CFG_CAP2_PRESCALE_Pos = 0x3 + // Bit mask of CAP2_PRESCALE field. + PWM_CAP_CH2_CFG_CAP2_PRESCALE_Msk = 0x7f8 + // Position of CAP2_IN_INVERT field. + PWM_CAP_CH2_CFG_CAP2_IN_INVERT_Pos = 0xb + // Bit mask of CAP2_IN_INVERT field. + PWM_CAP_CH2_CFG_CAP2_IN_INVERT_Msk = 0x800 + // Bit CAP2_IN_INVERT. + PWM_CAP_CH2_CFG_CAP2_IN_INVERT = 0x800 + // Position of CAP2_SW field. + PWM_CAP_CH2_CFG_CAP2_SW_Pos = 0xc + // Bit mask of CAP2_SW field. + PWM_CAP_CH2_CFG_CAP2_SW_Msk = 0x1000 + // Bit CAP2_SW. + PWM_CAP_CH2_CFG_CAP2_SW = 0x1000 + + // CAP_CH0: Value of last capture on channel 0 + // Position of CAP0_VALUE field. + PWM_CAP_CH0_CAP0_VALUE_Pos = 0x0 + // Bit mask of CAP0_VALUE field. + PWM_CAP_CH0_CAP0_VALUE_Msk = 0xffffffff + + // CAP_CH1: Value of last capture on channel 1 + // Position of CAP1_VALUE field. + PWM_CAP_CH1_CAP1_VALUE_Pos = 0x0 + // Bit mask of CAP1_VALUE field. + PWM_CAP_CH1_CAP1_VALUE_Msk = 0xffffffff + + // CAP_CH2: Value of last capture on channel 2 + // Position of CAP2_VALUE field. + PWM_CAP_CH2_CAP2_VALUE_Pos = 0x0 + // Bit mask of CAP2_VALUE field. + PWM_CAP_CH2_CAP2_VALUE_Msk = 0xffffffff + + // CAP_STATUS: Edge of last capture trigger + // Position of CAP0_EDGE field. + PWM_CAP_STATUS_CAP0_EDGE_Pos = 0x0 + // Bit mask of CAP0_EDGE field. + PWM_CAP_STATUS_CAP0_EDGE_Msk = 0x1 + // Bit CAP0_EDGE. + PWM_CAP_STATUS_CAP0_EDGE = 0x1 + // Position of CAP1_EDGE field. + PWM_CAP_STATUS_CAP1_EDGE_Pos = 0x1 + // Bit mask of CAP1_EDGE field. + PWM_CAP_STATUS_CAP1_EDGE_Msk = 0x2 + // Bit CAP1_EDGE. + PWM_CAP_STATUS_CAP1_EDGE = 0x2 + // Position of CAP2_EDGE field. + PWM_CAP_STATUS_CAP2_EDGE_Pos = 0x2 + // Bit mask of CAP2_EDGE field. + PWM_CAP_STATUS_CAP2_EDGE_Msk = 0x4 + // Bit CAP2_EDGE. + PWM_CAP_STATUS_CAP2_EDGE = 0x4 + + // UPDATE_CFG: Enable update. + // Position of GLOBAL_UP_EN field. + PWM_UPDATE_CFG_GLOBAL_UP_EN_Pos = 0x0 + // Bit mask of GLOBAL_UP_EN field. + PWM_UPDATE_CFG_GLOBAL_UP_EN_Msk = 0x1 + // Bit GLOBAL_UP_EN. + PWM_UPDATE_CFG_GLOBAL_UP_EN = 0x1 + // Position of GLOBAL_FORCE_UP field. + PWM_UPDATE_CFG_GLOBAL_FORCE_UP_Pos = 0x1 + // Bit mask of GLOBAL_FORCE_UP field. + PWM_UPDATE_CFG_GLOBAL_FORCE_UP_Msk = 0x2 + // Bit GLOBAL_FORCE_UP. + PWM_UPDATE_CFG_GLOBAL_FORCE_UP = 0x2 + // Position of OP0_UP_EN field. + PWM_UPDATE_CFG_OP0_UP_EN_Pos = 0x2 + // Bit mask of OP0_UP_EN field. + PWM_UPDATE_CFG_OP0_UP_EN_Msk = 0x4 + // Bit OP0_UP_EN. + PWM_UPDATE_CFG_OP0_UP_EN = 0x4 + // Position of OP0_FORCE_UP field. + PWM_UPDATE_CFG_OP0_FORCE_UP_Pos = 0x3 + // Bit mask of OP0_FORCE_UP field. + PWM_UPDATE_CFG_OP0_FORCE_UP_Msk = 0x8 + // Bit OP0_FORCE_UP. + PWM_UPDATE_CFG_OP0_FORCE_UP = 0x8 + // Position of OP1_UP_EN field. + PWM_UPDATE_CFG_OP1_UP_EN_Pos = 0x4 + // Bit mask of OP1_UP_EN field. + PWM_UPDATE_CFG_OP1_UP_EN_Msk = 0x10 + // Bit OP1_UP_EN. + PWM_UPDATE_CFG_OP1_UP_EN = 0x10 + // Position of OP1_FORCE_UP field. + PWM_UPDATE_CFG_OP1_FORCE_UP_Pos = 0x5 + // Bit mask of OP1_FORCE_UP field. + PWM_UPDATE_CFG_OP1_FORCE_UP_Msk = 0x20 + // Bit OP1_FORCE_UP. + PWM_UPDATE_CFG_OP1_FORCE_UP = 0x20 + // Position of OP2_UP_EN field. + PWM_UPDATE_CFG_OP2_UP_EN_Pos = 0x6 + // Bit mask of OP2_UP_EN field. + PWM_UPDATE_CFG_OP2_UP_EN_Msk = 0x40 + // Bit OP2_UP_EN. + PWM_UPDATE_CFG_OP2_UP_EN = 0x40 + // Position of OP2_FORCE_UP field. + PWM_UPDATE_CFG_OP2_FORCE_UP_Pos = 0x7 + // Bit mask of OP2_FORCE_UP field. + PWM_UPDATE_CFG_OP2_FORCE_UP_Msk = 0x80 + // Bit OP2_FORCE_UP. + PWM_UPDATE_CFG_OP2_FORCE_UP = 0x80 + + // INT_ENA: Interrupt enable bits + // Position of TIMER0_STOP_INT_ENA field. + PWM_INT_ENA_TIMER0_STOP_INT_ENA_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_ENA field. + PWM_INT_ENA_TIMER0_STOP_INT_ENA_Msk = 0x1 + // Bit TIMER0_STOP_INT_ENA. + PWM_INT_ENA_TIMER0_STOP_INT_ENA = 0x1 + // Position of TIMER1_STOP_INT_ENA field. + PWM_INT_ENA_TIMER1_STOP_INT_ENA_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_ENA field. + PWM_INT_ENA_TIMER1_STOP_INT_ENA_Msk = 0x2 + // Bit TIMER1_STOP_INT_ENA. + PWM_INT_ENA_TIMER1_STOP_INT_ENA = 0x2 + // Position of TIMER2_STOP_INT_ENA field. + PWM_INT_ENA_TIMER2_STOP_INT_ENA_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_ENA field. + PWM_INT_ENA_TIMER2_STOP_INT_ENA_Msk = 0x4 + // Bit TIMER2_STOP_INT_ENA. + PWM_INT_ENA_TIMER2_STOP_INT_ENA = 0x4 + // Position of TIMER0_TEZ_INT_ENA field. + PWM_INT_ENA_TIMER0_TEZ_INT_ENA_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_ENA field. + PWM_INT_ENA_TIMER0_TEZ_INT_ENA_Msk = 0x8 + // Bit TIMER0_TEZ_INT_ENA. + PWM_INT_ENA_TIMER0_TEZ_INT_ENA = 0x8 + // Position of TIMER1_TEZ_INT_ENA field. + PWM_INT_ENA_TIMER1_TEZ_INT_ENA_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_ENA field. + PWM_INT_ENA_TIMER1_TEZ_INT_ENA_Msk = 0x10 + // Bit TIMER1_TEZ_INT_ENA. + PWM_INT_ENA_TIMER1_TEZ_INT_ENA = 0x10 + // Position of TIMER2_TEZ_INT_ENA field. + PWM_INT_ENA_TIMER2_TEZ_INT_ENA_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_ENA field. + PWM_INT_ENA_TIMER2_TEZ_INT_ENA_Msk = 0x20 + // Bit TIMER2_TEZ_INT_ENA. + PWM_INT_ENA_TIMER2_TEZ_INT_ENA = 0x20 + // Position of TIMER0_TEP_INT_ENA field. + PWM_INT_ENA_TIMER0_TEP_INT_ENA_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_ENA field. + PWM_INT_ENA_TIMER0_TEP_INT_ENA_Msk = 0x40 + // Bit TIMER0_TEP_INT_ENA. + PWM_INT_ENA_TIMER0_TEP_INT_ENA = 0x40 + // Position of TIMER1_TEP_INT_ENA field. + PWM_INT_ENA_TIMER1_TEP_INT_ENA_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_ENA field. + PWM_INT_ENA_TIMER1_TEP_INT_ENA_Msk = 0x80 + // Bit TIMER1_TEP_INT_ENA. + PWM_INT_ENA_TIMER1_TEP_INT_ENA = 0x80 + // Position of TIMER2_TEP_INT_ENA field. + PWM_INT_ENA_TIMER2_TEP_INT_ENA_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_ENA field. + PWM_INT_ENA_TIMER2_TEP_INT_ENA_Msk = 0x100 + // Bit TIMER2_TEP_INT_ENA. + PWM_INT_ENA_TIMER2_TEP_INT_ENA = 0x100 + // Position of FAULT0_INT_ENA field. + PWM_INT_ENA_FAULT0_INT_ENA_Pos = 0x9 + // Bit mask of FAULT0_INT_ENA field. + PWM_INT_ENA_FAULT0_INT_ENA_Msk = 0x200 + // Bit FAULT0_INT_ENA. + PWM_INT_ENA_FAULT0_INT_ENA = 0x200 + // Position of FAULT1_INT_ENA field. + PWM_INT_ENA_FAULT1_INT_ENA_Pos = 0xa + // Bit mask of FAULT1_INT_ENA field. + PWM_INT_ENA_FAULT1_INT_ENA_Msk = 0x400 + // Bit FAULT1_INT_ENA. + PWM_INT_ENA_FAULT1_INT_ENA = 0x400 + // Position of FAULT2_INT_ENA field. + PWM_INT_ENA_FAULT2_INT_ENA_Pos = 0xb + // Bit mask of FAULT2_INT_ENA field. + PWM_INT_ENA_FAULT2_INT_ENA_Msk = 0x800 + // Bit FAULT2_INT_ENA. + PWM_INT_ENA_FAULT2_INT_ENA = 0x800 + // Position of FAULT0_CLR_INT_ENA field. + PWM_INT_ENA_FAULT0_CLR_INT_ENA_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_ENA field. + PWM_INT_ENA_FAULT0_CLR_INT_ENA_Msk = 0x1000 + // Bit FAULT0_CLR_INT_ENA. + PWM_INT_ENA_FAULT0_CLR_INT_ENA = 0x1000 + // Position of FAULT1_CLR_INT_ENA field. + PWM_INT_ENA_FAULT1_CLR_INT_ENA_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_ENA field. + PWM_INT_ENA_FAULT1_CLR_INT_ENA_Msk = 0x2000 + // Bit FAULT1_CLR_INT_ENA. + PWM_INT_ENA_FAULT1_CLR_INT_ENA = 0x2000 + // Position of FAULT2_CLR_INT_ENA field. + PWM_INT_ENA_FAULT2_CLR_INT_ENA_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_ENA field. + PWM_INT_ENA_FAULT2_CLR_INT_ENA_Msk = 0x4000 + // Bit FAULT2_CLR_INT_ENA. + PWM_INT_ENA_FAULT2_CLR_INT_ENA = 0x4000 + // Position of CMPR0_TEA_INT_ENA field. + PWM_INT_ENA_CMPR0_TEA_INT_ENA_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_ENA field. + PWM_INT_ENA_CMPR0_TEA_INT_ENA_Msk = 0x8000 + // Bit CMPR0_TEA_INT_ENA. + PWM_INT_ENA_CMPR0_TEA_INT_ENA = 0x8000 + // Position of CMPR1_TEA_INT_ENA field. + PWM_INT_ENA_CMPR1_TEA_INT_ENA_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_ENA field. + PWM_INT_ENA_CMPR1_TEA_INT_ENA_Msk = 0x10000 + // Bit CMPR1_TEA_INT_ENA. + PWM_INT_ENA_CMPR1_TEA_INT_ENA = 0x10000 + // Position of CMPR2_TEA_INT_ENA field. + PWM_INT_ENA_CMPR2_TEA_INT_ENA_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_ENA field. + PWM_INT_ENA_CMPR2_TEA_INT_ENA_Msk = 0x20000 + // Bit CMPR2_TEA_INT_ENA. + PWM_INT_ENA_CMPR2_TEA_INT_ENA = 0x20000 + // Position of CMPR0_TEB_INT_ENA field. + PWM_INT_ENA_CMPR0_TEB_INT_ENA_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_ENA field. + PWM_INT_ENA_CMPR0_TEB_INT_ENA_Msk = 0x40000 + // Bit CMPR0_TEB_INT_ENA. + PWM_INT_ENA_CMPR0_TEB_INT_ENA = 0x40000 + // Position of CMPR1_TEB_INT_ENA field. + PWM_INT_ENA_CMPR1_TEB_INT_ENA_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_ENA field. + PWM_INT_ENA_CMPR1_TEB_INT_ENA_Msk = 0x80000 + // Bit CMPR1_TEB_INT_ENA. + PWM_INT_ENA_CMPR1_TEB_INT_ENA = 0x80000 + // Position of CMPR2_TEB_INT_ENA field. + PWM_INT_ENA_CMPR2_TEB_INT_ENA_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_ENA field. + PWM_INT_ENA_CMPR2_TEB_INT_ENA_Msk = 0x100000 + // Bit CMPR2_TEB_INT_ENA. + PWM_INT_ENA_CMPR2_TEB_INT_ENA = 0x100000 + // Position of TZ0_CBC_INT_ENA field. + PWM_INT_ENA_TZ0_CBC_INT_ENA_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_ENA field. + PWM_INT_ENA_TZ0_CBC_INT_ENA_Msk = 0x200000 + // Bit TZ0_CBC_INT_ENA. + PWM_INT_ENA_TZ0_CBC_INT_ENA = 0x200000 + // Position of TZ1_CBC_INT_ENA field. + PWM_INT_ENA_TZ1_CBC_INT_ENA_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_ENA field. + PWM_INT_ENA_TZ1_CBC_INT_ENA_Msk = 0x400000 + // Bit TZ1_CBC_INT_ENA. + PWM_INT_ENA_TZ1_CBC_INT_ENA = 0x400000 + // Position of TZ2_CBC_INT_ENA field. + PWM_INT_ENA_TZ2_CBC_INT_ENA_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_ENA field. + PWM_INT_ENA_TZ2_CBC_INT_ENA_Msk = 0x800000 + // Bit TZ2_CBC_INT_ENA. + PWM_INT_ENA_TZ2_CBC_INT_ENA = 0x800000 + // Position of TZ0_OST_INT_ENA field. + PWM_INT_ENA_TZ0_OST_INT_ENA_Pos = 0x18 + // Bit mask of TZ0_OST_INT_ENA field. + PWM_INT_ENA_TZ0_OST_INT_ENA_Msk = 0x1000000 + // Bit TZ0_OST_INT_ENA. + PWM_INT_ENA_TZ0_OST_INT_ENA = 0x1000000 + // Position of TZ1_OST_INT_ENA field. + PWM_INT_ENA_TZ1_OST_INT_ENA_Pos = 0x19 + // Bit mask of TZ1_OST_INT_ENA field. + PWM_INT_ENA_TZ1_OST_INT_ENA_Msk = 0x2000000 + // Bit TZ1_OST_INT_ENA. + PWM_INT_ENA_TZ1_OST_INT_ENA = 0x2000000 + // Position of TZ2_OST_INT_ENA field. + PWM_INT_ENA_TZ2_OST_INT_ENA_Pos = 0x1a + // Bit mask of TZ2_OST_INT_ENA field. + PWM_INT_ENA_TZ2_OST_INT_ENA_Msk = 0x4000000 + // Bit TZ2_OST_INT_ENA. + PWM_INT_ENA_TZ2_OST_INT_ENA = 0x4000000 + // Position of CAP0_INT_ENA field. + PWM_INT_ENA_CAP0_INT_ENA_Pos = 0x1b + // Bit mask of CAP0_INT_ENA field. + PWM_INT_ENA_CAP0_INT_ENA_Msk = 0x8000000 + // Bit CAP0_INT_ENA. + PWM_INT_ENA_CAP0_INT_ENA = 0x8000000 + // Position of CAP1_INT_ENA field. + PWM_INT_ENA_CAP1_INT_ENA_Pos = 0x1c + // Bit mask of CAP1_INT_ENA field. + PWM_INT_ENA_CAP1_INT_ENA_Msk = 0x10000000 + // Bit CAP1_INT_ENA. + PWM_INT_ENA_CAP1_INT_ENA = 0x10000000 + // Position of CAP2_INT_ENA field. + PWM_INT_ENA_CAP2_INT_ENA_Pos = 0x1d + // Bit mask of CAP2_INT_ENA field. + PWM_INT_ENA_CAP2_INT_ENA_Msk = 0x20000000 + // Bit CAP2_INT_ENA. + PWM_INT_ENA_CAP2_INT_ENA = 0x20000000 + + // INT_RAW: Raw interrupt status + // Position of TIMER0_STOP_INT_RAW field. + PWM_INT_RAW_TIMER0_STOP_INT_RAW_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_RAW field. + PWM_INT_RAW_TIMER0_STOP_INT_RAW_Msk = 0x1 + // Bit TIMER0_STOP_INT_RAW. + PWM_INT_RAW_TIMER0_STOP_INT_RAW = 0x1 + // Position of TIMER1_STOP_INT_RAW field. + PWM_INT_RAW_TIMER1_STOP_INT_RAW_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_RAW field. + PWM_INT_RAW_TIMER1_STOP_INT_RAW_Msk = 0x2 + // Bit TIMER1_STOP_INT_RAW. + PWM_INT_RAW_TIMER1_STOP_INT_RAW = 0x2 + // Position of TIMER2_STOP_INT_RAW field. + PWM_INT_RAW_TIMER2_STOP_INT_RAW_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_RAW field. + PWM_INT_RAW_TIMER2_STOP_INT_RAW_Msk = 0x4 + // Bit TIMER2_STOP_INT_RAW. + PWM_INT_RAW_TIMER2_STOP_INT_RAW = 0x4 + // Position of TIMER0_TEZ_INT_RAW field. + PWM_INT_RAW_TIMER0_TEZ_INT_RAW_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_RAW field. + PWM_INT_RAW_TIMER0_TEZ_INT_RAW_Msk = 0x8 + // Bit TIMER0_TEZ_INT_RAW. + PWM_INT_RAW_TIMER0_TEZ_INT_RAW = 0x8 + // Position of TIMER1_TEZ_INT_RAW field. + PWM_INT_RAW_TIMER1_TEZ_INT_RAW_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_RAW field. + PWM_INT_RAW_TIMER1_TEZ_INT_RAW_Msk = 0x10 + // Bit TIMER1_TEZ_INT_RAW. + PWM_INT_RAW_TIMER1_TEZ_INT_RAW = 0x10 + // Position of TIMER2_TEZ_INT_RAW field. + PWM_INT_RAW_TIMER2_TEZ_INT_RAW_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_RAW field. + PWM_INT_RAW_TIMER2_TEZ_INT_RAW_Msk = 0x20 + // Bit TIMER2_TEZ_INT_RAW. + PWM_INT_RAW_TIMER2_TEZ_INT_RAW = 0x20 + // Position of TIMER0_TEP_INT_RAW field. + PWM_INT_RAW_TIMER0_TEP_INT_RAW_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_RAW field. + PWM_INT_RAW_TIMER0_TEP_INT_RAW_Msk = 0x40 + // Bit TIMER0_TEP_INT_RAW. + PWM_INT_RAW_TIMER0_TEP_INT_RAW = 0x40 + // Position of TIMER1_TEP_INT_RAW field. + PWM_INT_RAW_TIMER1_TEP_INT_RAW_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_RAW field. + PWM_INT_RAW_TIMER1_TEP_INT_RAW_Msk = 0x80 + // Bit TIMER1_TEP_INT_RAW. + PWM_INT_RAW_TIMER1_TEP_INT_RAW = 0x80 + // Position of TIMER2_TEP_INT_RAW field. + PWM_INT_RAW_TIMER2_TEP_INT_RAW_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_RAW field. + PWM_INT_RAW_TIMER2_TEP_INT_RAW_Msk = 0x100 + // Bit TIMER2_TEP_INT_RAW. + PWM_INT_RAW_TIMER2_TEP_INT_RAW = 0x100 + // Position of FAULT0_INT_RAW field. + PWM_INT_RAW_FAULT0_INT_RAW_Pos = 0x9 + // Bit mask of FAULT0_INT_RAW field. + PWM_INT_RAW_FAULT0_INT_RAW_Msk = 0x200 + // Bit FAULT0_INT_RAW. + PWM_INT_RAW_FAULT0_INT_RAW = 0x200 + // Position of FAULT1_INT_RAW field. + PWM_INT_RAW_FAULT1_INT_RAW_Pos = 0xa + // Bit mask of FAULT1_INT_RAW field. + PWM_INT_RAW_FAULT1_INT_RAW_Msk = 0x400 + // Bit FAULT1_INT_RAW. + PWM_INT_RAW_FAULT1_INT_RAW = 0x400 + // Position of FAULT2_INT_RAW field. + PWM_INT_RAW_FAULT2_INT_RAW_Pos = 0xb + // Bit mask of FAULT2_INT_RAW field. + PWM_INT_RAW_FAULT2_INT_RAW_Msk = 0x800 + // Bit FAULT2_INT_RAW. + PWM_INT_RAW_FAULT2_INT_RAW = 0x800 + // Position of FAULT0_CLR_INT_RAW field. + PWM_INT_RAW_FAULT0_CLR_INT_RAW_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_RAW field. + PWM_INT_RAW_FAULT0_CLR_INT_RAW_Msk = 0x1000 + // Bit FAULT0_CLR_INT_RAW. + PWM_INT_RAW_FAULT0_CLR_INT_RAW = 0x1000 + // Position of FAULT1_CLR_INT_RAW field. + PWM_INT_RAW_FAULT1_CLR_INT_RAW_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_RAW field. + PWM_INT_RAW_FAULT1_CLR_INT_RAW_Msk = 0x2000 + // Bit FAULT1_CLR_INT_RAW. + PWM_INT_RAW_FAULT1_CLR_INT_RAW = 0x2000 + // Position of FAULT2_CLR_INT_RAW field. + PWM_INT_RAW_FAULT2_CLR_INT_RAW_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_RAW field. + PWM_INT_RAW_FAULT2_CLR_INT_RAW_Msk = 0x4000 + // Bit FAULT2_CLR_INT_RAW. + PWM_INT_RAW_FAULT2_CLR_INT_RAW = 0x4000 + // Position of CMPR0_TEA_INT_RAW field. + PWM_INT_RAW_CMPR0_TEA_INT_RAW_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_RAW field. + PWM_INT_RAW_CMPR0_TEA_INT_RAW_Msk = 0x8000 + // Bit CMPR0_TEA_INT_RAW. + PWM_INT_RAW_CMPR0_TEA_INT_RAW = 0x8000 + // Position of CMPR1_TEA_INT_RAW field. + PWM_INT_RAW_CMPR1_TEA_INT_RAW_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_RAW field. + PWM_INT_RAW_CMPR1_TEA_INT_RAW_Msk = 0x10000 + // Bit CMPR1_TEA_INT_RAW. + PWM_INT_RAW_CMPR1_TEA_INT_RAW = 0x10000 + // Position of CMPR2_TEA_INT_RAW field. + PWM_INT_RAW_CMPR2_TEA_INT_RAW_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_RAW field. + PWM_INT_RAW_CMPR2_TEA_INT_RAW_Msk = 0x20000 + // Bit CMPR2_TEA_INT_RAW. + PWM_INT_RAW_CMPR2_TEA_INT_RAW = 0x20000 + // Position of CMPR0_TEB_INT_RAW field. + PWM_INT_RAW_CMPR0_TEB_INT_RAW_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_RAW field. + PWM_INT_RAW_CMPR0_TEB_INT_RAW_Msk = 0x40000 + // Bit CMPR0_TEB_INT_RAW. + PWM_INT_RAW_CMPR0_TEB_INT_RAW = 0x40000 + // Position of CMPR1_TEB_INT_RAW field. + PWM_INT_RAW_CMPR1_TEB_INT_RAW_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_RAW field. + PWM_INT_RAW_CMPR1_TEB_INT_RAW_Msk = 0x80000 + // Bit CMPR1_TEB_INT_RAW. + PWM_INT_RAW_CMPR1_TEB_INT_RAW = 0x80000 + // Position of CMPR2_TEB_INT_RAW field. + PWM_INT_RAW_CMPR2_TEB_INT_RAW_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_RAW field. + PWM_INT_RAW_CMPR2_TEB_INT_RAW_Msk = 0x100000 + // Bit CMPR2_TEB_INT_RAW. + PWM_INT_RAW_CMPR2_TEB_INT_RAW = 0x100000 + // Position of TZ0_CBC_INT_RAW field. + PWM_INT_RAW_TZ0_CBC_INT_RAW_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_RAW field. + PWM_INT_RAW_TZ0_CBC_INT_RAW_Msk = 0x200000 + // Bit TZ0_CBC_INT_RAW. + PWM_INT_RAW_TZ0_CBC_INT_RAW = 0x200000 + // Position of TZ1_CBC_INT_RAW field. + PWM_INT_RAW_TZ1_CBC_INT_RAW_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_RAW field. + PWM_INT_RAW_TZ1_CBC_INT_RAW_Msk = 0x400000 + // Bit TZ1_CBC_INT_RAW. + PWM_INT_RAW_TZ1_CBC_INT_RAW = 0x400000 + // Position of TZ2_CBC_INT_RAW field. + PWM_INT_RAW_TZ2_CBC_INT_RAW_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_RAW field. + PWM_INT_RAW_TZ2_CBC_INT_RAW_Msk = 0x800000 + // Bit TZ2_CBC_INT_RAW. + PWM_INT_RAW_TZ2_CBC_INT_RAW = 0x800000 + // Position of TZ0_OST_INT_RAW field. + PWM_INT_RAW_TZ0_OST_INT_RAW_Pos = 0x18 + // Bit mask of TZ0_OST_INT_RAW field. + PWM_INT_RAW_TZ0_OST_INT_RAW_Msk = 0x1000000 + // Bit TZ0_OST_INT_RAW. + PWM_INT_RAW_TZ0_OST_INT_RAW = 0x1000000 + // Position of TZ1_OST_INT_RAW field. + PWM_INT_RAW_TZ1_OST_INT_RAW_Pos = 0x19 + // Bit mask of TZ1_OST_INT_RAW field. + PWM_INT_RAW_TZ1_OST_INT_RAW_Msk = 0x2000000 + // Bit TZ1_OST_INT_RAW. + PWM_INT_RAW_TZ1_OST_INT_RAW = 0x2000000 + // Position of TZ2_OST_INT_RAW field. + PWM_INT_RAW_TZ2_OST_INT_RAW_Pos = 0x1a + // Bit mask of TZ2_OST_INT_RAW field. + PWM_INT_RAW_TZ2_OST_INT_RAW_Msk = 0x4000000 + // Bit TZ2_OST_INT_RAW. + PWM_INT_RAW_TZ2_OST_INT_RAW = 0x4000000 + // Position of CAP0_INT_RAW field. + PWM_INT_RAW_CAP0_INT_RAW_Pos = 0x1b + // Bit mask of CAP0_INT_RAW field. + PWM_INT_RAW_CAP0_INT_RAW_Msk = 0x8000000 + // Bit CAP0_INT_RAW. + PWM_INT_RAW_CAP0_INT_RAW = 0x8000000 + // Position of CAP1_INT_RAW field. + PWM_INT_RAW_CAP1_INT_RAW_Pos = 0x1c + // Bit mask of CAP1_INT_RAW field. + PWM_INT_RAW_CAP1_INT_RAW_Msk = 0x10000000 + // Bit CAP1_INT_RAW. + PWM_INT_RAW_CAP1_INT_RAW = 0x10000000 + // Position of CAP2_INT_RAW field. + PWM_INT_RAW_CAP2_INT_RAW_Pos = 0x1d + // Bit mask of CAP2_INT_RAW field. + PWM_INT_RAW_CAP2_INT_RAW_Msk = 0x20000000 + // Bit CAP2_INT_RAW. + PWM_INT_RAW_CAP2_INT_RAW = 0x20000000 + + // INT_ST: Masked interrupt status + // Position of TIMER0_STOP_INT_ST field. + PWM_INT_ST_TIMER0_STOP_INT_ST_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_ST field. + PWM_INT_ST_TIMER0_STOP_INT_ST_Msk = 0x1 + // Bit TIMER0_STOP_INT_ST. + PWM_INT_ST_TIMER0_STOP_INT_ST = 0x1 + // Position of TIMER1_STOP_INT_ST field. + PWM_INT_ST_TIMER1_STOP_INT_ST_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_ST field. + PWM_INT_ST_TIMER1_STOP_INT_ST_Msk = 0x2 + // Bit TIMER1_STOP_INT_ST. + PWM_INT_ST_TIMER1_STOP_INT_ST = 0x2 + // Position of TIMER2_STOP_INT_ST field. + PWM_INT_ST_TIMER2_STOP_INT_ST_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_ST field. + PWM_INT_ST_TIMER2_STOP_INT_ST_Msk = 0x4 + // Bit TIMER2_STOP_INT_ST. + PWM_INT_ST_TIMER2_STOP_INT_ST = 0x4 + // Position of TIMER0_TEZ_INT_ST field. + PWM_INT_ST_TIMER0_TEZ_INT_ST_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_ST field. + PWM_INT_ST_TIMER0_TEZ_INT_ST_Msk = 0x8 + // Bit TIMER0_TEZ_INT_ST. + PWM_INT_ST_TIMER0_TEZ_INT_ST = 0x8 + // Position of TIMER1_TEZ_INT_ST field. + PWM_INT_ST_TIMER1_TEZ_INT_ST_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_ST field. + PWM_INT_ST_TIMER1_TEZ_INT_ST_Msk = 0x10 + // Bit TIMER1_TEZ_INT_ST. + PWM_INT_ST_TIMER1_TEZ_INT_ST = 0x10 + // Position of TIMER2_TEZ_INT_ST field. + PWM_INT_ST_TIMER2_TEZ_INT_ST_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_ST field. + PWM_INT_ST_TIMER2_TEZ_INT_ST_Msk = 0x20 + // Bit TIMER2_TEZ_INT_ST. + PWM_INT_ST_TIMER2_TEZ_INT_ST = 0x20 + // Position of TIMER0_TEP_INT_ST field. + PWM_INT_ST_TIMER0_TEP_INT_ST_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_ST field. + PWM_INT_ST_TIMER0_TEP_INT_ST_Msk = 0x40 + // Bit TIMER0_TEP_INT_ST. + PWM_INT_ST_TIMER0_TEP_INT_ST = 0x40 + // Position of TIMER1_TEP_INT_ST field. + PWM_INT_ST_TIMER1_TEP_INT_ST_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_ST field. + PWM_INT_ST_TIMER1_TEP_INT_ST_Msk = 0x80 + // Bit TIMER1_TEP_INT_ST. + PWM_INT_ST_TIMER1_TEP_INT_ST = 0x80 + // Position of TIMER2_TEP_INT_ST field. + PWM_INT_ST_TIMER2_TEP_INT_ST_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_ST field. + PWM_INT_ST_TIMER2_TEP_INT_ST_Msk = 0x100 + // Bit TIMER2_TEP_INT_ST. + PWM_INT_ST_TIMER2_TEP_INT_ST = 0x100 + // Position of FAULT0_INT_ST field. + PWM_INT_ST_FAULT0_INT_ST_Pos = 0x9 + // Bit mask of FAULT0_INT_ST field. + PWM_INT_ST_FAULT0_INT_ST_Msk = 0x200 + // Bit FAULT0_INT_ST. + PWM_INT_ST_FAULT0_INT_ST = 0x200 + // Position of FAULT1_INT_ST field. + PWM_INT_ST_FAULT1_INT_ST_Pos = 0xa + // Bit mask of FAULT1_INT_ST field. + PWM_INT_ST_FAULT1_INT_ST_Msk = 0x400 + // Bit FAULT1_INT_ST. + PWM_INT_ST_FAULT1_INT_ST = 0x400 + // Position of FAULT2_INT_ST field. + PWM_INT_ST_FAULT2_INT_ST_Pos = 0xb + // Bit mask of FAULT2_INT_ST field. + PWM_INT_ST_FAULT2_INT_ST_Msk = 0x800 + // Bit FAULT2_INT_ST. + PWM_INT_ST_FAULT2_INT_ST = 0x800 + // Position of FAULT0_CLR_INT_ST field. + PWM_INT_ST_FAULT0_CLR_INT_ST_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_ST field. + PWM_INT_ST_FAULT0_CLR_INT_ST_Msk = 0x1000 + // Bit FAULT0_CLR_INT_ST. + PWM_INT_ST_FAULT0_CLR_INT_ST = 0x1000 + // Position of FAULT1_CLR_INT_ST field. + PWM_INT_ST_FAULT1_CLR_INT_ST_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_ST field. + PWM_INT_ST_FAULT1_CLR_INT_ST_Msk = 0x2000 + // Bit FAULT1_CLR_INT_ST. + PWM_INT_ST_FAULT1_CLR_INT_ST = 0x2000 + // Position of FAULT2_CLR_INT_ST field. + PWM_INT_ST_FAULT2_CLR_INT_ST_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_ST field. + PWM_INT_ST_FAULT2_CLR_INT_ST_Msk = 0x4000 + // Bit FAULT2_CLR_INT_ST. + PWM_INT_ST_FAULT2_CLR_INT_ST = 0x4000 + // Position of CMPR0_TEA_INT_ST field. + PWM_INT_ST_CMPR0_TEA_INT_ST_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_ST field. + PWM_INT_ST_CMPR0_TEA_INT_ST_Msk = 0x8000 + // Bit CMPR0_TEA_INT_ST. + PWM_INT_ST_CMPR0_TEA_INT_ST = 0x8000 + // Position of CMPR1_TEA_INT_ST field. + PWM_INT_ST_CMPR1_TEA_INT_ST_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_ST field. + PWM_INT_ST_CMPR1_TEA_INT_ST_Msk = 0x10000 + // Bit CMPR1_TEA_INT_ST. + PWM_INT_ST_CMPR1_TEA_INT_ST = 0x10000 + // Position of CMPR2_TEA_INT_ST field. + PWM_INT_ST_CMPR2_TEA_INT_ST_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_ST field. + PWM_INT_ST_CMPR2_TEA_INT_ST_Msk = 0x20000 + // Bit CMPR2_TEA_INT_ST. + PWM_INT_ST_CMPR2_TEA_INT_ST = 0x20000 + // Position of CMPR0_TEB_INT_ST field. + PWM_INT_ST_CMPR0_TEB_INT_ST_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_ST field. + PWM_INT_ST_CMPR0_TEB_INT_ST_Msk = 0x40000 + // Bit CMPR0_TEB_INT_ST. + PWM_INT_ST_CMPR0_TEB_INT_ST = 0x40000 + // Position of CMPR1_TEB_INT_ST field. + PWM_INT_ST_CMPR1_TEB_INT_ST_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_ST field. + PWM_INT_ST_CMPR1_TEB_INT_ST_Msk = 0x80000 + // Bit CMPR1_TEB_INT_ST. + PWM_INT_ST_CMPR1_TEB_INT_ST = 0x80000 + // Position of CMPR2_TEB_INT_ST field. + PWM_INT_ST_CMPR2_TEB_INT_ST_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_ST field. + PWM_INT_ST_CMPR2_TEB_INT_ST_Msk = 0x100000 + // Bit CMPR2_TEB_INT_ST. + PWM_INT_ST_CMPR2_TEB_INT_ST = 0x100000 + // Position of TZ0_CBC_INT_ST field. + PWM_INT_ST_TZ0_CBC_INT_ST_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_ST field. + PWM_INT_ST_TZ0_CBC_INT_ST_Msk = 0x200000 + // Bit TZ0_CBC_INT_ST. + PWM_INT_ST_TZ0_CBC_INT_ST = 0x200000 + // Position of TZ1_CBC_INT_ST field. + PWM_INT_ST_TZ1_CBC_INT_ST_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_ST field. + PWM_INT_ST_TZ1_CBC_INT_ST_Msk = 0x400000 + // Bit TZ1_CBC_INT_ST. + PWM_INT_ST_TZ1_CBC_INT_ST = 0x400000 + // Position of TZ2_CBC_INT_ST field. + PWM_INT_ST_TZ2_CBC_INT_ST_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_ST field. + PWM_INT_ST_TZ2_CBC_INT_ST_Msk = 0x800000 + // Bit TZ2_CBC_INT_ST. + PWM_INT_ST_TZ2_CBC_INT_ST = 0x800000 + // Position of TZ0_OST_INT_ST field. + PWM_INT_ST_TZ0_OST_INT_ST_Pos = 0x18 + // Bit mask of TZ0_OST_INT_ST field. + PWM_INT_ST_TZ0_OST_INT_ST_Msk = 0x1000000 + // Bit TZ0_OST_INT_ST. + PWM_INT_ST_TZ0_OST_INT_ST = 0x1000000 + // Position of TZ1_OST_INT_ST field. + PWM_INT_ST_TZ1_OST_INT_ST_Pos = 0x19 + // Bit mask of TZ1_OST_INT_ST field. + PWM_INT_ST_TZ1_OST_INT_ST_Msk = 0x2000000 + // Bit TZ1_OST_INT_ST. + PWM_INT_ST_TZ1_OST_INT_ST = 0x2000000 + // Position of TZ2_OST_INT_ST field. + PWM_INT_ST_TZ2_OST_INT_ST_Pos = 0x1a + // Bit mask of TZ2_OST_INT_ST field. + PWM_INT_ST_TZ2_OST_INT_ST_Msk = 0x4000000 + // Bit TZ2_OST_INT_ST. + PWM_INT_ST_TZ2_OST_INT_ST = 0x4000000 + // Position of CAP0_INT_ST field. + PWM_INT_ST_CAP0_INT_ST_Pos = 0x1b + // Bit mask of CAP0_INT_ST field. + PWM_INT_ST_CAP0_INT_ST_Msk = 0x8000000 + // Bit CAP0_INT_ST. + PWM_INT_ST_CAP0_INT_ST = 0x8000000 + // Position of CAP1_INT_ST field. + PWM_INT_ST_CAP1_INT_ST_Pos = 0x1c + // Bit mask of CAP1_INT_ST field. + PWM_INT_ST_CAP1_INT_ST_Msk = 0x10000000 + // Bit CAP1_INT_ST. + PWM_INT_ST_CAP1_INT_ST = 0x10000000 + // Position of CAP2_INT_ST field. + PWM_INT_ST_CAP2_INT_ST_Pos = 0x1d + // Bit mask of CAP2_INT_ST field. + PWM_INT_ST_CAP2_INT_ST_Msk = 0x20000000 + // Bit CAP2_INT_ST. + PWM_INT_ST_CAP2_INT_ST = 0x20000000 + + // INT_CLR: Interrupt clear bits + // Position of TIMER0_STOP_INT_CLR field. + PWM_INT_CLR_TIMER0_STOP_INT_CLR_Pos = 0x0 + // Bit mask of TIMER0_STOP_INT_CLR field. + PWM_INT_CLR_TIMER0_STOP_INT_CLR_Msk = 0x1 + // Bit TIMER0_STOP_INT_CLR. + PWM_INT_CLR_TIMER0_STOP_INT_CLR = 0x1 + // Position of TIMER1_STOP_INT_CLR field. + PWM_INT_CLR_TIMER1_STOP_INT_CLR_Pos = 0x1 + // Bit mask of TIMER1_STOP_INT_CLR field. + PWM_INT_CLR_TIMER1_STOP_INT_CLR_Msk = 0x2 + // Bit TIMER1_STOP_INT_CLR. + PWM_INT_CLR_TIMER1_STOP_INT_CLR = 0x2 + // Position of TIMER2_STOP_INT_CLR field. + PWM_INT_CLR_TIMER2_STOP_INT_CLR_Pos = 0x2 + // Bit mask of TIMER2_STOP_INT_CLR field. + PWM_INT_CLR_TIMER2_STOP_INT_CLR_Msk = 0x4 + // Bit TIMER2_STOP_INT_CLR. + PWM_INT_CLR_TIMER2_STOP_INT_CLR = 0x4 + // Position of TIMER0_TEZ_INT_CLR field. + PWM_INT_CLR_TIMER0_TEZ_INT_CLR_Pos = 0x3 + // Bit mask of TIMER0_TEZ_INT_CLR field. + PWM_INT_CLR_TIMER0_TEZ_INT_CLR_Msk = 0x8 + // Bit TIMER0_TEZ_INT_CLR. + PWM_INT_CLR_TIMER0_TEZ_INT_CLR = 0x8 + // Position of TIMER1_TEZ_INT_CLR field. + PWM_INT_CLR_TIMER1_TEZ_INT_CLR_Pos = 0x4 + // Bit mask of TIMER1_TEZ_INT_CLR field. + PWM_INT_CLR_TIMER1_TEZ_INT_CLR_Msk = 0x10 + // Bit TIMER1_TEZ_INT_CLR. + PWM_INT_CLR_TIMER1_TEZ_INT_CLR = 0x10 + // Position of TIMER2_TEZ_INT_CLR field. + PWM_INT_CLR_TIMER2_TEZ_INT_CLR_Pos = 0x5 + // Bit mask of TIMER2_TEZ_INT_CLR field. + PWM_INT_CLR_TIMER2_TEZ_INT_CLR_Msk = 0x20 + // Bit TIMER2_TEZ_INT_CLR. + PWM_INT_CLR_TIMER2_TEZ_INT_CLR = 0x20 + // Position of TIMER0_TEP_INT_CLR field. + PWM_INT_CLR_TIMER0_TEP_INT_CLR_Pos = 0x6 + // Bit mask of TIMER0_TEP_INT_CLR field. + PWM_INT_CLR_TIMER0_TEP_INT_CLR_Msk = 0x40 + // Bit TIMER0_TEP_INT_CLR. + PWM_INT_CLR_TIMER0_TEP_INT_CLR = 0x40 + // Position of TIMER1_TEP_INT_CLR field. + PWM_INT_CLR_TIMER1_TEP_INT_CLR_Pos = 0x7 + // Bit mask of TIMER1_TEP_INT_CLR field. + PWM_INT_CLR_TIMER1_TEP_INT_CLR_Msk = 0x80 + // Bit TIMER1_TEP_INT_CLR. + PWM_INT_CLR_TIMER1_TEP_INT_CLR = 0x80 + // Position of TIMER2_TEP_INT_CLR field. + PWM_INT_CLR_TIMER2_TEP_INT_CLR_Pos = 0x8 + // Bit mask of TIMER2_TEP_INT_CLR field. + PWM_INT_CLR_TIMER2_TEP_INT_CLR_Msk = 0x100 + // Bit TIMER2_TEP_INT_CLR. + PWM_INT_CLR_TIMER2_TEP_INT_CLR = 0x100 + // Position of FAULT0_INT_CLR field. + PWM_INT_CLR_FAULT0_INT_CLR_Pos = 0x9 + // Bit mask of FAULT0_INT_CLR field. + PWM_INT_CLR_FAULT0_INT_CLR_Msk = 0x200 + // Bit FAULT0_INT_CLR. + PWM_INT_CLR_FAULT0_INT_CLR = 0x200 + // Position of FAULT1_INT_CLR field. + PWM_INT_CLR_FAULT1_INT_CLR_Pos = 0xa + // Bit mask of FAULT1_INT_CLR field. + PWM_INT_CLR_FAULT1_INT_CLR_Msk = 0x400 + // Bit FAULT1_INT_CLR. + PWM_INT_CLR_FAULT1_INT_CLR = 0x400 + // Position of FAULT2_INT_CLR field. + PWM_INT_CLR_FAULT2_INT_CLR_Pos = 0xb + // Bit mask of FAULT2_INT_CLR field. + PWM_INT_CLR_FAULT2_INT_CLR_Msk = 0x800 + // Bit FAULT2_INT_CLR. + PWM_INT_CLR_FAULT2_INT_CLR = 0x800 + // Position of FAULT0_CLR_INT_CLR field. + PWM_INT_CLR_FAULT0_CLR_INT_CLR_Pos = 0xc + // Bit mask of FAULT0_CLR_INT_CLR field. + PWM_INT_CLR_FAULT0_CLR_INT_CLR_Msk = 0x1000 + // Bit FAULT0_CLR_INT_CLR. + PWM_INT_CLR_FAULT0_CLR_INT_CLR = 0x1000 + // Position of FAULT1_CLR_INT_CLR field. + PWM_INT_CLR_FAULT1_CLR_INT_CLR_Pos = 0xd + // Bit mask of FAULT1_CLR_INT_CLR field. + PWM_INT_CLR_FAULT1_CLR_INT_CLR_Msk = 0x2000 + // Bit FAULT1_CLR_INT_CLR. + PWM_INT_CLR_FAULT1_CLR_INT_CLR = 0x2000 + // Position of FAULT2_CLR_INT_CLR field. + PWM_INT_CLR_FAULT2_CLR_INT_CLR_Pos = 0xe + // Bit mask of FAULT2_CLR_INT_CLR field. + PWM_INT_CLR_FAULT2_CLR_INT_CLR_Msk = 0x4000 + // Bit FAULT2_CLR_INT_CLR. + PWM_INT_CLR_FAULT2_CLR_INT_CLR = 0x4000 + // Position of CMPR0_TEA_INT_CLR field. + PWM_INT_CLR_CMPR0_TEA_INT_CLR_Pos = 0xf + // Bit mask of CMPR0_TEA_INT_CLR field. + PWM_INT_CLR_CMPR0_TEA_INT_CLR_Msk = 0x8000 + // Bit CMPR0_TEA_INT_CLR. + PWM_INT_CLR_CMPR0_TEA_INT_CLR = 0x8000 + // Position of CMPR1_TEA_INT_CLR field. + PWM_INT_CLR_CMPR1_TEA_INT_CLR_Pos = 0x10 + // Bit mask of CMPR1_TEA_INT_CLR field. + PWM_INT_CLR_CMPR1_TEA_INT_CLR_Msk = 0x10000 + // Bit CMPR1_TEA_INT_CLR. + PWM_INT_CLR_CMPR1_TEA_INT_CLR = 0x10000 + // Position of CMPR2_TEA_INT_CLR field. + PWM_INT_CLR_CMPR2_TEA_INT_CLR_Pos = 0x11 + // Bit mask of CMPR2_TEA_INT_CLR field. + PWM_INT_CLR_CMPR2_TEA_INT_CLR_Msk = 0x20000 + // Bit CMPR2_TEA_INT_CLR. + PWM_INT_CLR_CMPR2_TEA_INT_CLR = 0x20000 + // Position of CMPR0_TEB_INT_CLR field. + PWM_INT_CLR_CMPR0_TEB_INT_CLR_Pos = 0x12 + // Bit mask of CMPR0_TEB_INT_CLR field. + PWM_INT_CLR_CMPR0_TEB_INT_CLR_Msk = 0x40000 + // Bit CMPR0_TEB_INT_CLR. + PWM_INT_CLR_CMPR0_TEB_INT_CLR = 0x40000 + // Position of CMPR1_TEB_INT_CLR field. + PWM_INT_CLR_CMPR1_TEB_INT_CLR_Pos = 0x13 + // Bit mask of CMPR1_TEB_INT_CLR field. + PWM_INT_CLR_CMPR1_TEB_INT_CLR_Msk = 0x80000 + // Bit CMPR1_TEB_INT_CLR. + PWM_INT_CLR_CMPR1_TEB_INT_CLR = 0x80000 + // Position of CMPR2_TEB_INT_CLR field. + PWM_INT_CLR_CMPR2_TEB_INT_CLR_Pos = 0x14 + // Bit mask of CMPR2_TEB_INT_CLR field. + PWM_INT_CLR_CMPR2_TEB_INT_CLR_Msk = 0x100000 + // Bit CMPR2_TEB_INT_CLR. + PWM_INT_CLR_CMPR2_TEB_INT_CLR = 0x100000 + // Position of TZ0_CBC_INT_CLR field. + PWM_INT_CLR_TZ0_CBC_INT_CLR_Pos = 0x15 + // Bit mask of TZ0_CBC_INT_CLR field. + PWM_INT_CLR_TZ0_CBC_INT_CLR_Msk = 0x200000 + // Bit TZ0_CBC_INT_CLR. + PWM_INT_CLR_TZ0_CBC_INT_CLR = 0x200000 + // Position of TZ1_CBC_INT_CLR field. + PWM_INT_CLR_TZ1_CBC_INT_CLR_Pos = 0x16 + // Bit mask of TZ1_CBC_INT_CLR field. + PWM_INT_CLR_TZ1_CBC_INT_CLR_Msk = 0x400000 + // Bit TZ1_CBC_INT_CLR. + PWM_INT_CLR_TZ1_CBC_INT_CLR = 0x400000 + // Position of TZ2_CBC_INT_CLR field. + PWM_INT_CLR_TZ2_CBC_INT_CLR_Pos = 0x17 + // Bit mask of TZ2_CBC_INT_CLR field. + PWM_INT_CLR_TZ2_CBC_INT_CLR_Msk = 0x800000 + // Bit TZ2_CBC_INT_CLR. + PWM_INT_CLR_TZ2_CBC_INT_CLR = 0x800000 + // Position of TZ0_OST_INT_CLR field. + PWM_INT_CLR_TZ0_OST_INT_CLR_Pos = 0x18 + // Bit mask of TZ0_OST_INT_CLR field. + PWM_INT_CLR_TZ0_OST_INT_CLR_Msk = 0x1000000 + // Bit TZ0_OST_INT_CLR. + PWM_INT_CLR_TZ0_OST_INT_CLR = 0x1000000 + // Position of TZ1_OST_INT_CLR field. + PWM_INT_CLR_TZ1_OST_INT_CLR_Pos = 0x19 + // Bit mask of TZ1_OST_INT_CLR field. + PWM_INT_CLR_TZ1_OST_INT_CLR_Msk = 0x2000000 + // Bit TZ1_OST_INT_CLR. + PWM_INT_CLR_TZ1_OST_INT_CLR = 0x2000000 + // Position of TZ2_OST_INT_CLR field. + PWM_INT_CLR_TZ2_OST_INT_CLR_Pos = 0x1a + // Bit mask of TZ2_OST_INT_CLR field. + PWM_INT_CLR_TZ2_OST_INT_CLR_Msk = 0x4000000 + // Bit TZ2_OST_INT_CLR. + PWM_INT_CLR_TZ2_OST_INT_CLR = 0x4000000 + // Position of CAP0_INT_CLR field. + PWM_INT_CLR_CAP0_INT_CLR_Pos = 0x1b + // Bit mask of CAP0_INT_CLR field. + PWM_INT_CLR_CAP0_INT_CLR_Msk = 0x8000000 + // Bit CAP0_INT_CLR. + PWM_INT_CLR_CAP0_INT_CLR = 0x8000000 + // Position of CAP1_INT_CLR field. + PWM_INT_CLR_CAP1_INT_CLR_Pos = 0x1c + // Bit mask of CAP1_INT_CLR field. + PWM_INT_CLR_CAP1_INT_CLR_Msk = 0x10000000 + // Bit CAP1_INT_CLR. + PWM_INT_CLR_CAP1_INT_CLR = 0x10000000 + // Position of CAP2_INT_CLR field. + PWM_INT_CLR_CAP2_INT_CLR_Pos = 0x1d + // Bit mask of CAP2_INT_CLR field. + PWM_INT_CLR_CAP2_INT_CLR_Msk = 0x20000000 + // Bit CAP2_INT_CLR. + PWM_INT_CLR_CAP2_INT_CLR = 0x20000000 + + // CLK: MCPWM APB configuration register + // Position of EN field. + PWM_CLK_EN_Pos = 0x0 + // Bit mask of EN field. + PWM_CLK_EN_Msk = 0x1 + // Bit EN. + PWM_CLK_EN = 0x1 + + // VERSION: Version register. + // Position of DATE field. + PWM_VERSION_DATE_Pos = 0x0 + // Bit mask of DATE field. + PWM_VERSION_DATE_Msk = 0xfffffff +) + +// Constants for RMT: Remote Control +const ( + // CH0DATA: The read and write data register for CHANNEL%s by apb fifo access. + // Position of DATA field. + RMT_CHDATA_DATA_Pos = 0x0 + // Bit mask of DATA field. + RMT_CHDATA_DATA_Msk = 0xffffffff + + // CH0_TX_CONF0: Channel %s configure register 0 + // Position of TX_START field. + RMT_CH_TX_CONF0_TX_START_Pos = 0x0 + // Bit mask of TX_START field. + RMT_CH_TX_CONF0_TX_START_Msk = 0x1 + // Bit TX_START. + RMT_CH_TX_CONF0_TX_START = 0x1 + // Position of MEM_RD_RST field. + RMT_CH_TX_CONF0_MEM_RD_RST_Pos = 0x1 + // Bit mask of MEM_RD_RST field. + RMT_CH_TX_CONF0_MEM_RD_RST_Msk = 0x2 + // Bit MEM_RD_RST. + RMT_CH_TX_CONF0_MEM_RD_RST = 0x2 + // Position of APB_MEM_RST field. + RMT_CH_TX_CONF0_APB_MEM_RST_Pos = 0x2 + // Bit mask of APB_MEM_RST field. + RMT_CH_TX_CONF0_APB_MEM_RST_Msk = 0x4 + // Bit APB_MEM_RST. + RMT_CH_TX_CONF0_APB_MEM_RST = 0x4 + // Position of TX_CONTI_MODE field. + RMT_CH_TX_CONF0_TX_CONTI_MODE_Pos = 0x3 + // Bit mask of TX_CONTI_MODE field. + RMT_CH_TX_CONF0_TX_CONTI_MODE_Msk = 0x8 + // Bit TX_CONTI_MODE. + RMT_CH_TX_CONF0_TX_CONTI_MODE = 0x8 + // Position of MEM_TX_WRAP_EN field. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN_Pos = 0x4 + // Bit mask of MEM_TX_WRAP_EN field. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN_Msk = 0x10 + // Bit MEM_TX_WRAP_EN. + RMT_CH_TX_CONF0_MEM_TX_WRAP_EN = 0x10 + // Position of IDLE_OUT_LV field. + RMT_CH_TX_CONF0_IDLE_OUT_LV_Pos = 0x5 + // Bit mask of IDLE_OUT_LV field. + RMT_CH_TX_CONF0_IDLE_OUT_LV_Msk = 0x20 + // Bit IDLE_OUT_LV. + RMT_CH_TX_CONF0_IDLE_OUT_LV = 0x20 + // Position of IDLE_OUT_EN field. + RMT_CH_TX_CONF0_IDLE_OUT_EN_Pos = 0x6 + // Bit mask of IDLE_OUT_EN field. + RMT_CH_TX_CONF0_IDLE_OUT_EN_Msk = 0x40 + // Bit IDLE_OUT_EN. + RMT_CH_TX_CONF0_IDLE_OUT_EN = 0x40 + // Position of TX_STOP field. + RMT_CH_TX_CONF0_TX_STOP_Pos = 0x7 + // Bit mask of TX_STOP field. + RMT_CH_TX_CONF0_TX_STOP_Msk = 0x80 + // Bit TX_STOP. + RMT_CH_TX_CONF0_TX_STOP = 0x80 + // Position of DIV_CNT field. + RMT_CH_TX_CONF0_DIV_CNT_Pos = 0x8 + // Bit mask of DIV_CNT field. + RMT_CH_TX_CONF0_DIV_CNT_Msk = 0xff00 + // Position of MEM_SIZE field. + RMT_CH_TX_CONF0_MEM_SIZE_Pos = 0x10 + // Bit mask of MEM_SIZE field. + RMT_CH_TX_CONF0_MEM_SIZE_Msk = 0xf0000 + // Position of CARRIER_EFF_EN field. + RMT_CH_TX_CONF0_CARRIER_EFF_EN_Pos = 0x14 + // Bit mask of CARRIER_EFF_EN field. + RMT_CH_TX_CONF0_CARRIER_EFF_EN_Msk = 0x100000 + // Bit CARRIER_EFF_EN. + RMT_CH_TX_CONF0_CARRIER_EFF_EN = 0x100000 + // Position of CARRIER_EN field. + RMT_CH_TX_CONF0_CARRIER_EN_Pos = 0x15 + // Bit mask of CARRIER_EN field. + RMT_CH_TX_CONF0_CARRIER_EN_Msk = 0x200000 + // Bit CARRIER_EN. + RMT_CH_TX_CONF0_CARRIER_EN = 0x200000 + // Position of CARRIER_OUT_LV field. + RMT_CH_TX_CONF0_CARRIER_OUT_LV_Pos = 0x16 + // Bit mask of CARRIER_OUT_LV field. + RMT_CH_TX_CONF0_CARRIER_OUT_LV_Msk = 0x400000 + // Bit CARRIER_OUT_LV. + RMT_CH_TX_CONF0_CARRIER_OUT_LV = 0x400000 + // Position of AFIFO_RST field. + RMT_CH_TX_CONF0_AFIFO_RST_Pos = 0x17 + // Bit mask of AFIFO_RST field. + RMT_CH_TX_CONF0_AFIFO_RST_Msk = 0x800000 + // Bit AFIFO_RST. + RMT_CH_TX_CONF0_AFIFO_RST = 0x800000 + // Position of CONF_UPDATE field. + RMT_CH_TX_CONF0_CONF_UPDATE_Pos = 0x18 + // Bit mask of CONF_UPDATE field. + RMT_CH_TX_CONF0_CONF_UPDATE_Msk = 0x1000000 + // Bit CONF_UPDATE. + RMT_CH_TX_CONF0_CONF_UPDATE = 0x1000000 + + // CH4_RX_CONF0: Channel %s configure register 0 + // Position of DIV_CNT field. + RMT_CH_RX_CONF0_DIV_CNT_Pos = 0x0 + // Bit mask of DIV_CNT field. + RMT_CH_RX_CONF0_DIV_CNT_Msk = 0xff + // Position of IDLE_THRES field. + RMT_CH_RX_CONF0_IDLE_THRES_Pos = 0x8 + // Bit mask of IDLE_THRES field. + RMT_CH_RX_CONF0_IDLE_THRES_Msk = 0x7fff00 + // Position of MEM_SIZE field. + RMT_CH_RX_CONF0_MEM_SIZE_Pos = 0x18 + // Bit mask of MEM_SIZE field. + RMT_CH_RX_CONF0_MEM_SIZE_Msk = 0xf000000 + // Position of CARRIER_EN field. + RMT_CH_RX_CONF0_CARRIER_EN_Pos = 0x1c + // Bit mask of CARRIER_EN field. + RMT_CH_RX_CONF0_CARRIER_EN_Msk = 0x10000000 + // Bit CARRIER_EN. + RMT_CH_RX_CONF0_CARRIER_EN = 0x10000000 + // Position of CARRIER_OUT_LV field. + RMT_CH_RX_CONF0_CARRIER_OUT_LV_Pos = 0x1d + // Bit mask of CARRIER_OUT_LV field. + RMT_CH_RX_CONF0_CARRIER_OUT_LV_Msk = 0x20000000 + // Bit CARRIER_OUT_LV. + RMT_CH_RX_CONF0_CARRIER_OUT_LV = 0x20000000 + + // CH4_RX_CONF1: Channel %s configure register 1 + // Position of RX_EN field. + RMT_CH_RX_CONF1_RX_EN_Pos = 0x0 + // Bit mask of RX_EN field. + RMT_CH_RX_CONF1_RX_EN_Msk = 0x1 + // Bit RX_EN. + RMT_CH_RX_CONF1_RX_EN = 0x1 + // Position of MEM_WR_RST field. + RMT_CH_RX_CONF1_MEM_WR_RST_Pos = 0x1 + // Bit mask of MEM_WR_RST field. + RMT_CH_RX_CONF1_MEM_WR_RST_Msk = 0x2 + // Bit MEM_WR_RST. + RMT_CH_RX_CONF1_MEM_WR_RST = 0x2 + // Position of APB_MEM_RST field. + RMT_CH_RX_CONF1_APB_MEM_RST_Pos = 0x2 + // Bit mask of APB_MEM_RST field. + RMT_CH_RX_CONF1_APB_MEM_RST_Msk = 0x4 + // Bit APB_MEM_RST. + RMT_CH_RX_CONF1_APB_MEM_RST = 0x4 + // Position of MEM_OWNER field. + RMT_CH_RX_CONF1_MEM_OWNER_Pos = 0x3 + // Bit mask of MEM_OWNER field. + RMT_CH_RX_CONF1_MEM_OWNER_Msk = 0x8 + // Bit MEM_OWNER. + RMT_CH_RX_CONF1_MEM_OWNER = 0x8 + // Position of RX_FILTER_EN field. + RMT_CH_RX_CONF1_RX_FILTER_EN_Pos = 0x4 + // Bit mask of RX_FILTER_EN field. + RMT_CH_RX_CONF1_RX_FILTER_EN_Msk = 0x10 + // Bit RX_FILTER_EN. + RMT_CH_RX_CONF1_RX_FILTER_EN = 0x10 + // Position of RX_FILTER_THRES field. + RMT_CH_RX_CONF1_RX_FILTER_THRES_Pos = 0x5 + // Bit mask of RX_FILTER_THRES field. + RMT_CH_RX_CONF1_RX_FILTER_THRES_Msk = 0x1fe0 + // Position of MEM_RX_WRAP_EN field. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN_Pos = 0xd + // Bit mask of MEM_RX_WRAP_EN field. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN_Msk = 0x2000 + // Bit MEM_RX_WRAP_EN. + RMT_CH_RX_CONF1_MEM_RX_WRAP_EN = 0x2000 + // Position of AFIFO_RST field. + RMT_CH_RX_CONF1_AFIFO_RST_Pos = 0xe + // Bit mask of AFIFO_RST field. + RMT_CH_RX_CONF1_AFIFO_RST_Msk = 0x4000 + // Bit AFIFO_RST. + RMT_CH_RX_CONF1_AFIFO_RST = 0x4000 + // Position of CONF_UPDATE field. + RMT_CH_RX_CONF1_CONF_UPDATE_Pos = 0xf + // Bit mask of CONF_UPDATE field. + RMT_CH_RX_CONF1_CONF_UPDATE_Msk = 0x8000 + // Bit CONF_UPDATE. + RMT_CH_RX_CONF1_CONF_UPDATE = 0x8000 + + // CH0_TX_STATUS: Channel %s status register + // Position of MEM_RADDR_EX field. + RMT_CH_TX_STATUS_MEM_RADDR_EX_Pos = 0x0 + // Bit mask of MEM_RADDR_EX field. + RMT_CH_TX_STATUS_MEM_RADDR_EX_Msk = 0x3ff + // Position of APB_MEM_WADDR field. + RMT_CH_TX_STATUS_APB_MEM_WADDR_Pos = 0xb + // Bit mask of APB_MEM_WADDR field. + RMT_CH_TX_STATUS_APB_MEM_WADDR_Msk = 0x1ff800 + // Position of STATE field. + RMT_CH_TX_STATUS_STATE_Pos = 0x16 + // Bit mask of STATE field. + RMT_CH_TX_STATUS_STATE_Msk = 0x1c00000 + // Position of MEM_EMPTY field. + RMT_CH_TX_STATUS_MEM_EMPTY_Pos = 0x19 + // Bit mask of MEM_EMPTY field. + RMT_CH_TX_STATUS_MEM_EMPTY_Msk = 0x2000000 + // Bit MEM_EMPTY. + RMT_CH_TX_STATUS_MEM_EMPTY = 0x2000000 + // Position of APB_MEM_WR_ERR field. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR_Pos = 0x1a + // Bit mask of APB_MEM_WR_ERR field. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR_Msk = 0x4000000 + // Bit APB_MEM_WR_ERR. + RMT_CH_TX_STATUS_APB_MEM_WR_ERR = 0x4000000 + + // CH0_RX_STATUS: Channel %s status register + // Position of MEM_WADDR_EX field. + RMT_CH_RX_STATUS_MEM_WADDR_EX_Pos = 0x0 + // Bit mask of MEM_WADDR_EX field. + RMT_CH_RX_STATUS_MEM_WADDR_EX_Msk = 0x3ff + // Position of APB_MEM_RADDR field. + RMT_CH_RX_STATUS_APB_MEM_RADDR_Pos = 0xb + // Bit mask of APB_MEM_RADDR field. + RMT_CH_RX_STATUS_APB_MEM_RADDR_Msk = 0x1ff800 + // Position of STATE field. + RMT_CH_RX_STATUS_STATE_Pos = 0x16 + // Bit mask of STATE field. + RMT_CH_RX_STATUS_STATE_Msk = 0x1c00000 + // Position of MEM_OWNER_ERR field. + RMT_CH_RX_STATUS_MEM_OWNER_ERR_Pos = 0x19 + // Bit mask of MEM_OWNER_ERR field. + RMT_CH_RX_STATUS_MEM_OWNER_ERR_Msk = 0x2000000 + // Bit MEM_OWNER_ERR. + RMT_CH_RX_STATUS_MEM_OWNER_ERR = 0x2000000 + // Position of MEM_FULL field. + RMT_CH_RX_STATUS_MEM_FULL_Pos = 0x1a + // Bit mask of MEM_FULL field. + RMT_CH_RX_STATUS_MEM_FULL_Msk = 0x4000000 + // Bit MEM_FULL. + RMT_CH_RX_STATUS_MEM_FULL = 0x4000000 + // Position of APB_MEM_RD_ERR field. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR_Pos = 0x1b + // Bit mask of APB_MEM_RD_ERR field. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR_Msk = 0x8000000 + // Bit APB_MEM_RD_ERR. + RMT_CH_RX_STATUS_APB_MEM_RD_ERR = 0x8000000 + + // INT_RAW: Raw interrupt status + // Position of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_RAW_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_RAW_CH_s_TX_END = 0x1 + // Position of CH_s_TX_ERR field. + RMT_INT_RAW_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_RAW_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_RAW_CH_s_TX_ERR = 0x10 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_RAW_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_RAW_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_RAW_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_RAW_CH_s_TX_LOOP = 0x1000 + // Position of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Pos = 0x10 + // Bit mask of CH_s_RX_END field. + RMT_INT_RAW_CH_s_RX_END_Msk = 0x10000 + // Bit CH_s_RX_END. + RMT_INT_RAW_CH_s_RX_END = 0x10000 + // Position of CH_s_RX_ERR field. + RMT_INT_RAW_CH_s_RX_ERR_Pos = 0x14 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_RAW_CH_s_RX_ERR_Msk = 0x100000 + // Bit CH_s_RX_ERR. + RMT_INT_RAW_CH_s_RX_ERR = 0x100000 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_RAW_CH_s_RX_THR_EVENT_Pos = 0x18 + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_RAW_CH_s_RX_THR_EVENT_Msk = 0x1000000 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_RAW_CH_s_RX_THR_EVENT = 0x1000000 + // Position of TX_CH3_DMA_ACCESS_FAIL field. + RMT_INT_RAW_TX_CH3_DMA_ACCESS_FAIL_Pos = 0x1c + // Bit mask of TX_CH3_DMA_ACCESS_FAIL field. + RMT_INT_RAW_TX_CH3_DMA_ACCESS_FAIL_Msk = 0x10000000 + // Bit TX_CH3_DMA_ACCESS_FAIL. + RMT_INT_RAW_TX_CH3_DMA_ACCESS_FAIL = 0x10000000 + // Position of RX_CH7_DMA_ACCESS_FAIL field. + RMT_INT_RAW_RX_CH7_DMA_ACCESS_FAIL_Pos = 0x1d + // Bit mask of RX_CH7_DMA_ACCESS_FAIL field. + RMT_INT_RAW_RX_CH7_DMA_ACCESS_FAIL_Msk = 0x20000000 + // Bit RX_CH7_DMA_ACCESS_FAIL. + RMT_INT_RAW_RX_CH7_DMA_ACCESS_FAIL = 0x20000000 + + // INT_ST: Masked interrupt status + // Position of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ST_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ST_CH_s_TX_END = 0x1 + // Position of CH_s_TX_ERR field. + RMT_INT_ST_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_ST_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_ST_CH_s_TX_ERR = 0x10 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ST_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ST_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_TX_LOOP field. + RMT_INT_ST_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_ST_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_ST_CH_s_TX_LOOP = 0x1000 + // Position of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Pos = 0x10 + // Bit mask of CH_s_RX_END field. + RMT_INT_ST_CH_s_RX_END_Msk = 0x10000 + // Bit CH_s_RX_END. + RMT_INT_ST_CH_s_RX_END = 0x10000 + // Position of CH_s_RX_ERR field. + RMT_INT_ST_CH_s_RX_ERR_Pos = 0x14 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_ST_CH_s_RX_ERR_Msk = 0x100000 + // Bit CH_s_RX_ERR. + RMT_INT_ST_CH_s_RX_ERR = 0x100000 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_ST_CH_s_RX_THR_EVENT_Pos = 0x18 + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_ST_CH_s_RX_THR_EVENT_Msk = 0x1000000 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_ST_CH_s_RX_THR_EVENT = 0x1000000 + // Position of TX_CH3_DMA_ACCESS_FAIL field. + RMT_INT_ST_TX_CH3_DMA_ACCESS_FAIL_Pos = 0x1c + // Bit mask of TX_CH3_DMA_ACCESS_FAIL field. + RMT_INT_ST_TX_CH3_DMA_ACCESS_FAIL_Msk = 0x10000000 + // Bit TX_CH3_DMA_ACCESS_FAIL. + RMT_INT_ST_TX_CH3_DMA_ACCESS_FAIL = 0x10000000 + // Position of RX_CH7_DMA_ACCESS_FAIL field. + RMT_INT_ST_RX_CH7_DMA_ACCESS_FAIL_Pos = 0x1d + // Bit mask of RX_CH7_DMA_ACCESS_FAIL field. + RMT_INT_ST_RX_CH7_DMA_ACCESS_FAIL_Msk = 0x20000000 + // Bit RX_CH7_DMA_ACCESS_FAIL. + RMT_INT_ST_RX_CH7_DMA_ACCESS_FAIL = 0x20000000 + + // INT_ENA: Interrupt enable bits + // Position of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_ENA_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_ENA_CH_s_TX_END = 0x1 + // Position of CH_s_TX_ERR field. + RMT_INT_ENA_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_ENA_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_ENA_CH_s_TX_ERR = 0x10 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_ENA_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_ENA_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_TX_LOOP field. + RMT_INT_ENA_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_ENA_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_ENA_CH_s_TX_LOOP = 0x1000 + // Position of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Pos = 0x10 + // Bit mask of CH_s_RX_END field. + RMT_INT_ENA_CH_s_RX_END_Msk = 0x10000 + // Bit CH_s_RX_END. + RMT_INT_ENA_CH_s_RX_END = 0x10000 + // Position of CH_s_RX_ERR field. + RMT_INT_ENA_CH_s_RX_ERR_Pos = 0x14 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_ENA_CH_s_RX_ERR_Msk = 0x100000 + // Bit CH_s_RX_ERR. + RMT_INT_ENA_CH_s_RX_ERR = 0x100000 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_ENA_CH_s_RX_THR_EVENT_Pos = 0x18 + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_ENA_CH_s_RX_THR_EVENT_Msk = 0x1000000 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_ENA_CH_s_RX_THR_EVENT = 0x1000000 + // Position of TX_CH3_DMA_ACCESS_FAIL field. + RMT_INT_ENA_TX_CH3_DMA_ACCESS_FAIL_Pos = 0x1c + // Bit mask of TX_CH3_DMA_ACCESS_FAIL field. + RMT_INT_ENA_TX_CH3_DMA_ACCESS_FAIL_Msk = 0x10000000 + // Bit TX_CH3_DMA_ACCESS_FAIL. + RMT_INT_ENA_TX_CH3_DMA_ACCESS_FAIL = 0x10000000 + // Position of RX_CH7_DMA_ACCESS_FAIL field. + RMT_INT_ENA_RX_CH7_DMA_ACCESS_FAIL_Pos = 0x1d + // Bit mask of RX_CH7_DMA_ACCESS_FAIL field. + RMT_INT_ENA_RX_CH7_DMA_ACCESS_FAIL_Msk = 0x20000000 + // Bit RX_CH7_DMA_ACCESS_FAIL. + RMT_INT_ENA_RX_CH7_DMA_ACCESS_FAIL = 0x20000000 + + // INT_CLR: Interrupt clear bits + // Position of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Pos = 0x0 + // Bit mask of CH_s_TX_END field. + RMT_INT_CLR_CH_s_TX_END_Msk = 0x1 + // Bit CH_s_TX_END. + RMT_INT_CLR_CH_s_TX_END = 0x1 + // Position of CH_s_TX_ERR field. + RMT_INT_CLR_CH_s_TX_ERR_Pos = 0x4 + // Bit mask of CH_s_TX_ERR field. + RMT_INT_CLR_CH_s_TX_ERR_Msk = 0x10 + // Bit CH_s_TX_ERR. + RMT_INT_CLR_CH_s_TX_ERR = 0x10 + // Position of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Pos = 0x8 + // Bit mask of CH_s_TX_THR_EVENT field. + RMT_INT_CLR_CH_s_TX_THR_EVENT_Msk = 0x100 + // Bit CH_s_TX_THR_EVENT. + RMT_INT_CLR_CH_s_TX_THR_EVENT = 0x100 + // Position of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Pos = 0xc + // Bit mask of CH_s_TX_LOOP field. + RMT_INT_CLR_CH_s_TX_LOOP_Msk = 0x1000 + // Bit CH_s_TX_LOOP. + RMT_INT_CLR_CH_s_TX_LOOP = 0x1000 + // Position of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Pos = 0x10 + // Bit mask of CH_s_RX_END field. + RMT_INT_CLR_CH_s_RX_END_Msk = 0x10000 + // Bit CH_s_RX_END. + RMT_INT_CLR_CH_s_RX_END = 0x10000 + // Position of CH_s_RX_ERR field. + RMT_INT_CLR_CH_s_RX_ERR_Pos = 0x14 + // Bit mask of CH_s_RX_ERR field. + RMT_INT_CLR_CH_s_RX_ERR_Msk = 0x100000 + // Bit CH_s_RX_ERR. + RMT_INT_CLR_CH_s_RX_ERR = 0x100000 + // Position of CH_s_RX_THR_EVENT field. + RMT_INT_CLR_CH_s_RX_THR_EVENT_Pos = 0x18 + // Bit mask of CH_s_RX_THR_EVENT field. + RMT_INT_CLR_CH_s_RX_THR_EVENT_Msk = 0x1000000 + // Bit CH_s_RX_THR_EVENT. + RMT_INT_CLR_CH_s_RX_THR_EVENT = 0x1000000 + // Position of TX_CH3_DMA_ACCESS_FAIL field. + RMT_INT_CLR_TX_CH3_DMA_ACCESS_FAIL_Pos = 0x1c + // Bit mask of TX_CH3_DMA_ACCESS_FAIL field. + RMT_INT_CLR_TX_CH3_DMA_ACCESS_FAIL_Msk = 0x10000000 + // Bit TX_CH3_DMA_ACCESS_FAIL. + RMT_INT_CLR_TX_CH3_DMA_ACCESS_FAIL = 0x10000000 + // Position of RX_CH7_DMA_ACCESS_FAIL field. + RMT_INT_CLR_RX_CH7_DMA_ACCESS_FAIL_Pos = 0x1d + // Bit mask of RX_CH7_DMA_ACCESS_FAIL field. + RMT_INT_CLR_RX_CH7_DMA_ACCESS_FAIL_Msk = 0x20000000 + // Bit RX_CH7_DMA_ACCESS_FAIL. + RMT_INT_CLR_RX_CH7_DMA_ACCESS_FAIL = 0x20000000 + + // CH0CARRIER_DUTY: Channel %s duty cycle configuration register + // Position of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Pos = 0x0 + // Bit mask of CARRIER_LOW field. + RMT_CHCARRIER_DUTY_CARRIER_LOW_Msk = 0xffff + // Position of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Pos = 0x10 + // Bit mask of CARRIER_HIGH field. + RMT_CHCARRIER_DUTY_CARRIER_HIGH_Msk = 0xffff0000 + + // CH0_RX_CARRIER_RM: Channel %s carrier remove register + // Position of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Pos = 0x0 + // Bit mask of CARRIER_LOW_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_Msk = 0xffff + // Position of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Pos = 0x10 + // Bit mask of CARRIER_HIGH_THRES field. + RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_Msk = 0xffff0000 + + // CH0_TX_LIM: Channel %s Tx event configuration register + // Position of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Pos = 0x0 + // Bit mask of TX_LIM field. + RMT_CH_TX_LIM_TX_LIM_Msk = 0x1ff + // Position of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Pos = 0x9 + // Bit mask of TX_LOOP_NUM field. + RMT_CH_TX_LIM_TX_LOOP_NUM_Msk = 0x7fe00 + // Position of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Pos = 0x13 + // Bit mask of TX_LOOP_CNT_EN field. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN_Msk = 0x80000 + // Bit TX_LOOP_CNT_EN. + RMT_CH_TX_LIM_TX_LOOP_CNT_EN = 0x80000 + // Position of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Pos = 0x14 + // Bit mask of LOOP_COUNT_RESET field. + RMT_CH_TX_LIM_LOOP_COUNT_RESET_Msk = 0x100000 + // Bit LOOP_COUNT_RESET. + RMT_CH_TX_LIM_LOOP_COUNT_RESET = 0x100000 + // Position of LOOP_STOP_EN field. + RMT_CH_TX_LIM_LOOP_STOP_EN_Pos = 0x15 + // Bit mask of LOOP_STOP_EN field. + RMT_CH_TX_LIM_LOOP_STOP_EN_Msk = 0x200000 + // Bit LOOP_STOP_EN. + RMT_CH_TX_LIM_LOOP_STOP_EN = 0x200000 + + // CH0_RX_LIM: Channel %s Rx event configuration register + // Position of RX_LIM_CH4 field. + RMT_CH_RX_LIM_RX_LIM_CH4_Pos = 0x0 + // Bit mask of RX_LIM_CH4 field. + RMT_CH_RX_LIM_RX_LIM_CH4_Msk = 0x1ff + + // SYS_CONF: RMT apb configuration register + // Position of APB_FIFO_MASK field. + RMT_SYS_CONF_APB_FIFO_MASK_Pos = 0x0 + // Bit mask of APB_FIFO_MASK field. + RMT_SYS_CONF_APB_FIFO_MASK_Msk = 0x1 + // Bit APB_FIFO_MASK. + RMT_SYS_CONF_APB_FIFO_MASK = 0x1 + // Position of MEM_CLK_FORCE_ON field. + RMT_SYS_CONF_MEM_CLK_FORCE_ON_Pos = 0x1 + // Bit mask of MEM_CLK_FORCE_ON field. + RMT_SYS_CONF_MEM_CLK_FORCE_ON_Msk = 0x2 + // Bit MEM_CLK_FORCE_ON. + RMT_SYS_CONF_MEM_CLK_FORCE_ON = 0x2 + // Position of MEM_FORCE_PD field. + RMT_SYS_CONF_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of MEM_FORCE_PD field. + RMT_SYS_CONF_MEM_FORCE_PD_Msk = 0x4 + // Bit MEM_FORCE_PD. + RMT_SYS_CONF_MEM_FORCE_PD = 0x4 + // Position of MEM_FORCE_PU field. + RMT_SYS_CONF_MEM_FORCE_PU_Pos = 0x3 + // Bit mask of MEM_FORCE_PU field. + RMT_SYS_CONF_MEM_FORCE_PU_Msk = 0x8 + // Bit MEM_FORCE_PU. + RMT_SYS_CONF_MEM_FORCE_PU = 0x8 + // Position of SCLK_DIV_NUM field. + RMT_SYS_CONF_SCLK_DIV_NUM_Pos = 0x4 + // Bit mask of SCLK_DIV_NUM field. + RMT_SYS_CONF_SCLK_DIV_NUM_Msk = 0xff0 + // Position of SCLK_DIV_A field. + RMT_SYS_CONF_SCLK_DIV_A_Pos = 0xc + // Bit mask of SCLK_DIV_A field. + RMT_SYS_CONF_SCLK_DIV_A_Msk = 0x3f000 + // Position of SCLK_DIV_B field. + RMT_SYS_CONF_SCLK_DIV_B_Pos = 0x12 + // Bit mask of SCLK_DIV_B field. + RMT_SYS_CONF_SCLK_DIV_B_Msk = 0xfc0000 + // Position of SCLK_SEL field. + RMT_SYS_CONF_SCLK_SEL_Pos = 0x18 + // Bit mask of SCLK_SEL field. + RMT_SYS_CONF_SCLK_SEL_Msk = 0x3000000 + // Position of SCLK_ACTIVE field. + RMT_SYS_CONF_SCLK_ACTIVE_Pos = 0x1a + // Bit mask of SCLK_ACTIVE field. + RMT_SYS_CONF_SCLK_ACTIVE_Msk = 0x4000000 + // Bit SCLK_ACTIVE. + RMT_SYS_CONF_SCLK_ACTIVE = 0x4000000 + // Position of CLK_EN field. + RMT_SYS_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + RMT_SYS_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + RMT_SYS_CONF_CLK_EN = 0x80000000 + + // TX_SIM: RMT TX synchronous register + // Position of CH0 field. + RMT_TX_SIM_CH0_Pos = 0x0 + // Bit mask of CH0 field. + RMT_TX_SIM_CH0_Msk = 0x1 + // Bit CH0. + RMT_TX_SIM_CH0 = 0x1 + // Position of CH1 field. + RMT_TX_SIM_CH1_Pos = 0x1 + // Bit mask of CH1 field. + RMT_TX_SIM_CH1_Msk = 0x2 + // Bit CH1. + RMT_TX_SIM_CH1 = 0x2 + // Position of CH2 field. + RMT_TX_SIM_CH2_Pos = 0x2 + // Bit mask of CH2 field. + RMT_TX_SIM_CH2_Msk = 0x4 + // Bit CH2. + RMT_TX_SIM_CH2 = 0x4 + // Position of CH3 field. + RMT_TX_SIM_CH3_Pos = 0x3 + // Bit mask of CH3 field. + RMT_TX_SIM_CH3_Msk = 0x8 + // Bit CH3. + RMT_TX_SIM_CH3 = 0x8 + // Position of EN field. + RMT_TX_SIM_EN_Pos = 0x4 + // Bit mask of EN field. + RMT_TX_SIM_EN_Msk = 0x10 + // Bit EN. + RMT_TX_SIM_EN = 0x10 + + // REF_CNT_RST: RMT clock divider reset register + // Position of CH_s field. + RMT_REF_CNT_RST_CH_s_Pos = 0x0 + // Bit mask of CH_s field. + RMT_REF_CNT_RST_CH_s_Msk = 0x1 + // Bit CH_s. + RMT_REF_CNT_RST_CH_s = 0x1 + + // DATE: RMT version register + // Position of DATE field. + RMT_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RMT_DATE_DATE_Msk = 0xfffffff +) + +// Constants for RNG: Hardware Random Number Generator +const () + +// Constants for RSA: RSA (Rivest Shamir Adleman) Accelerator +const ( + // M_PRIME: RSA M' register + // Position of M_PRIME field. + RSA_M_PRIME_M_PRIME_Pos = 0x0 + // Bit mask of M_PRIME field. + RSA_M_PRIME_M_PRIME_Msk = 0xffffffff + + // MODE: RSA length mode register + // Position of MODE field. + RSA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + RSA_MODE_MODE_Msk = 0x7f + + // CLEAN: RSA clean register + // Position of CLEAN field. + RSA_CLEAN_CLEAN_Pos = 0x0 + // Bit mask of CLEAN field. + RSA_CLEAN_CLEAN_Msk = 0x1 + // Bit CLEAN. + RSA_CLEAN_CLEAN = 0x1 + + // MODEXP_START: Modular exponentiation trigger register. + // Position of MODEXP_START field. + RSA_MODEXP_START_MODEXP_START_Pos = 0x0 + // Bit mask of MODEXP_START field. + RSA_MODEXP_START_MODEXP_START_Msk = 0x1 + // Bit MODEXP_START. + RSA_MODEXP_START_MODEXP_START = 0x1 + + // MODMULT_START: Modular multiplication trigger register. + // Position of MODMULT_START field. + RSA_MODMULT_START_MODMULT_START_Pos = 0x0 + // Bit mask of MODMULT_START field. + RSA_MODMULT_START_MODMULT_START_Msk = 0x1 + // Bit MODMULT_START. + RSA_MODMULT_START_MODMULT_START = 0x1 + + // MULT_START: Normal multiplication trigger register. + // Position of MULT_START field. + RSA_MULT_START_MULT_START_Pos = 0x0 + // Bit mask of MULT_START field. + RSA_MULT_START_MULT_START_Msk = 0x1 + // Bit MULT_START. + RSA_MULT_START_MULT_START = 0x1 + + // IDLE: RSA idle register + // Position of IDLE field. + RSA_IDLE_IDLE_Pos = 0x0 + // Bit mask of IDLE field. + RSA_IDLE_IDLE_Msk = 0x1 + // Bit IDLE. + RSA_IDLE_IDLE = 0x1 + + // CLEAR_INTERRUPT: RSA interrupt clear register + // Position of CLEAR_INTERRUPT field. + RSA_CLEAR_INTERRUPT_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + RSA_CLEAR_INTERRUPT_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + RSA_CLEAR_INTERRUPT_CLEAR_INTERRUPT = 0x1 + + // CONSTANT_TIME: CONSTANT_TIME option control register + // Position of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Pos = 0x0 + // Bit mask of CONSTANT_TIME field. + RSA_CONSTANT_TIME_CONSTANT_TIME_Msk = 0x1 + // Bit CONSTANT_TIME. + RSA_CONSTANT_TIME_CONSTANT_TIME = 0x1 + + // SEARCH_ENABLE: SEARCH option enable register + // Position of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Pos = 0x0 + // Bit mask of SEARCH_ENABLE field. + RSA_SEARCH_ENABLE_SEARCH_ENABLE_Msk = 0x1 + // Bit SEARCH_ENABLE. + RSA_SEARCH_ENABLE_SEARCH_ENABLE = 0x1 + + // SEARCH_POS: RSA search position configure register + // Position of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Pos = 0x0 + // Bit mask of SEARCH_POS field. + RSA_SEARCH_POS_SEARCH_POS_Msk = 0xfff + + // INTERRUPT_ENA: RSA interrupt enable register + // Position of INTERRUPT_ENA field. + RSA_INTERRUPT_ENA_INTERRUPT_ENA_Pos = 0x0 + // Bit mask of INTERRUPT_ENA field. + RSA_INTERRUPT_ENA_INTERRUPT_ENA_Msk = 0x1 + // Bit INTERRUPT_ENA. + RSA_INTERRUPT_ENA_INTERRUPT_ENA = 0x1 + + // DATE: RSA version control register + // Position of DATE field. + RSA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RSA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for RTC_CNTL: Real-Time Clock Control +const ( + // OPTIONS0: RTC common configure register + // Position of SW_STALL_APPCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_APPCPU_C0_Pos = 0x0 + // Bit mask of SW_STALL_APPCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_APPCPU_C0_Msk = 0x3 + // Position of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Pos = 0x2 + // Bit mask of SW_STALL_PROCPU_C0 field. + RTC_CNTL_OPTIONS0_SW_STALL_PROCPU_C0_Msk = 0xc + // Position of SW_APPCPU_RST field. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST_Pos = 0x4 + // Bit mask of SW_APPCPU_RST field. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST_Msk = 0x10 + // Bit SW_APPCPU_RST. + RTC_CNTL_OPTIONS0_SW_APPCPU_RST = 0x10 + // Position of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Pos = 0x5 + // Bit mask of SW_PROCPU_RST field. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST_Msk = 0x20 + // Bit SW_PROCPU_RST. + RTC_CNTL_OPTIONS0_SW_PROCPU_RST = 0x20 + // Position of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Pos = 0x6 + // Bit mask of BB_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD_Msk = 0x40 + // Bit BB_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PD = 0x40 + // Position of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Pos = 0x7 + // Bit mask of BB_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU_Msk = 0x80 + // Bit BB_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BB_I2C_FORCE_PU = 0x80 + // Position of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Pos = 0x8 + // Bit mask of BBPLL_I2C_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD_Msk = 0x100 + // Bit BBPLL_I2C_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PD = 0x100 + // Position of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Pos = 0x9 + // Bit mask of BBPLL_I2C_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU_Msk = 0x200 + // Bit BBPLL_I2C_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_I2C_FORCE_PU = 0x200 + // Position of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Pos = 0xa + // Bit mask of BBPLL_FORCE_PD field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD_Msk = 0x400 + // Bit BBPLL_FORCE_PD. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PD = 0x400 + // Position of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Pos = 0xb + // Bit mask of BBPLL_FORCE_PU field. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU_Msk = 0x800 + // Bit BBPLL_FORCE_PU. + RTC_CNTL_OPTIONS0_BBPLL_FORCE_PU = 0x800 + // Position of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Pos = 0xc + // Bit mask of XTL_FORCE_PD field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD_Msk = 0x1000 + // Bit XTL_FORCE_PD. + RTC_CNTL_OPTIONS0_XTL_FORCE_PD = 0x1000 + // Position of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Pos = 0xd + // Bit mask of XTL_FORCE_PU field. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU_Msk = 0x2000 + // Bit XTL_FORCE_PU. + RTC_CNTL_OPTIONS0_XTL_FORCE_PU = 0x2000 + // Position of XTL_EN_WAIT field. + RTC_CNTL_OPTIONS0_XTL_EN_WAIT_Pos = 0xe + // Bit mask of XTL_EN_WAIT field. + RTC_CNTL_OPTIONS0_XTL_EN_WAIT_Msk = 0x3c000 + // Position of XTL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO_Pos = 0x17 + // Bit mask of XTL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO_Msk = 0x800000 + // Bit XTL_FORCE_ISO. + RTC_CNTL_OPTIONS0_XTL_FORCE_ISO = 0x800000 + // Position of PLL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO_Pos = 0x18 + // Bit mask of PLL_FORCE_ISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO_Msk = 0x1000000 + // Bit PLL_FORCE_ISO. + RTC_CNTL_OPTIONS0_PLL_FORCE_ISO = 0x1000000 + // Position of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Pos = 0x19 + // Bit mask of ANALOG_FORCE_ISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO_Msk = 0x2000000 + // Bit ANALOG_FORCE_ISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_ISO = 0x2000000 + // Position of XTL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO_Pos = 0x1a + // Bit mask of XTL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO_Msk = 0x4000000 + // Bit XTL_FORCE_NOISO. + RTC_CNTL_OPTIONS0_XTL_FORCE_NOISO = 0x4000000 + // Position of PLL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO_Pos = 0x1b + // Bit mask of PLL_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO_Msk = 0x8000000 + // Bit PLL_FORCE_NOISO. + RTC_CNTL_OPTIONS0_PLL_FORCE_NOISO = 0x8000000 + // Position of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Pos = 0x1c + // Bit mask of ANALOG_FORCE_NOISO field. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO_Msk = 0x10000000 + // Bit ANALOG_FORCE_NOISO. + RTC_CNTL_OPTIONS0_ANALOG_FORCE_NOISO = 0x10000000 + // Position of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Pos = 0x1d + // Bit mask of DG_WRAP_FORCE_RST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST_Msk = 0x20000000 + // Bit DG_WRAP_FORCE_RST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_RST = 0x20000000 + // Position of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_NORST field. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_NORST. + RTC_CNTL_OPTIONS0_DG_WRAP_FORCE_NORST = 0x40000000 + // Position of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Pos = 0x1f + // Bit mask of SW_SYS_RST field. + RTC_CNTL_OPTIONS0_SW_SYS_RST_Msk = 0x80000000 + // Bit SW_SYS_RST. + RTC_CNTL_OPTIONS0_SW_SYS_RST = 0x80000000 + + // SLP_TIMER0: configure min sleep time + // Position of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Pos = 0x0 + // Bit mask of SLP_VAL_LO field. + RTC_CNTL_SLP_TIMER0_SLP_VAL_LO_Msk = 0xffffffff + + // SLP_TIMER1: configure sleep time hi + // Position of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Pos = 0x0 + // Bit mask of SLP_VAL_HI field. + RTC_CNTL_SLP_TIMER1_SLP_VAL_HI_Msk = 0xffff + // Position of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Pos = 0x10 + // Bit mask of MAIN_TIMER_ALARM_EN field. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN_Msk = 0x10000 + // Bit MAIN_TIMER_ALARM_EN. + RTC_CNTL_SLP_TIMER1_MAIN_TIMER_ALARM_EN = 0x10000 + + // TIME_UPDATE: update rtc main timer + // Position of TIMER_SYS_STALL field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL_Pos = 0x1b + // Bit mask of TIMER_SYS_STALL field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL_Msk = 0x8000000 + // Bit TIMER_SYS_STALL. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_STALL = 0x8000000 + // Position of TIMER_XTL_OFF field. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF_Pos = 0x1c + // Bit mask of TIMER_XTL_OFF field. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF_Msk = 0x10000000 + // Bit TIMER_XTL_OFF. + RTC_CNTL_TIME_UPDATE_TIMER_XTL_OFF = 0x10000000 + // Position of TIMER_SYS_RST field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST_Pos = 0x1d + // Bit mask of TIMER_SYS_RST field. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST_Msk = 0x20000000 + // Bit TIMER_SYS_RST. + RTC_CNTL_TIME_UPDATE_TIMER_SYS_RST = 0x20000000 + // Position of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Pos = 0x1f + // Bit mask of TIME_UPDATE field. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE_Msk = 0x80000000 + // Bit TIME_UPDATE. + RTC_CNTL_TIME_UPDATE_TIME_UPDATE = 0x80000000 + + // TIME_LOW0: read rtc_main timer low bits + // Position of TIMER_VALUE0_LOW field. + RTC_CNTL_TIME_LOW0_TIMER_VALUE0_LOW_Pos = 0x0 + // Bit mask of TIMER_VALUE0_LOW field. + RTC_CNTL_TIME_LOW0_TIMER_VALUE0_LOW_Msk = 0xffffffff + + // TIME_HIGH0: read rtc_main timer high bits + // Position of TIMER_VALUE0_HIGH field. + RTC_CNTL_TIME_HIGH0_TIMER_VALUE0_HIGH_Pos = 0x0 + // Bit mask of TIMER_VALUE0_HIGH field. + RTC_CNTL_TIME_HIGH0_TIMER_VALUE0_HIGH_Msk = 0xffff + + // STATE0: configure chip sleep + // Position of SW_CPU_INT field. + RTC_CNTL_STATE0_SW_CPU_INT_Pos = 0x0 + // Bit mask of SW_CPU_INT field. + RTC_CNTL_STATE0_SW_CPU_INT_Msk = 0x1 + // Bit SW_CPU_INT. + RTC_CNTL_STATE0_SW_CPU_INT = 0x1 + // Position of SLP_REJECT_CAUSE_CLR field. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR_Pos = 0x1 + // Bit mask of SLP_REJECT_CAUSE_CLR field. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR_Msk = 0x2 + // Bit SLP_REJECT_CAUSE_CLR. + RTC_CNTL_STATE0_SLP_REJECT_CAUSE_CLR = 0x2 + // Position of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Pos = 0x16 + // Bit mask of APB2RTC_BRIDGE_SEL field. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL_Msk = 0x400000 + // Bit APB2RTC_BRIDGE_SEL. + RTC_CNTL_STATE0_APB2RTC_BRIDGE_SEL = 0x400000 + // Position of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Pos = 0x1c + // Bit mask of SDIO_ACTIVE_IND field. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND_Msk = 0x10000000 + // Bit SDIO_ACTIVE_IND. + RTC_CNTL_STATE0_SDIO_ACTIVE_IND = 0x10000000 + // Position of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Pos = 0x1d + // Bit mask of SLP_WAKEUP field. + RTC_CNTL_STATE0_SLP_WAKEUP_Msk = 0x20000000 + // Bit SLP_WAKEUP. + RTC_CNTL_STATE0_SLP_WAKEUP = 0x20000000 + // Position of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Pos = 0x1e + // Bit mask of SLP_REJECT field. + RTC_CNTL_STATE0_SLP_REJECT_Msk = 0x40000000 + // Bit SLP_REJECT. + RTC_CNTL_STATE0_SLP_REJECT = 0x40000000 + // Position of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Pos = 0x1f + // Bit mask of SLEEP_EN field. + RTC_CNTL_STATE0_SLEEP_EN_Msk = 0x80000000 + // Bit SLEEP_EN. + RTC_CNTL_STATE0_SLEEP_EN = 0x80000000 + + // TIMER1: rtc state wait time + // Position of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Pos = 0x0 + // Bit mask of CPU_STALL_EN field. + RTC_CNTL_TIMER1_CPU_STALL_EN_Msk = 0x1 + // Bit CPU_STALL_EN. + RTC_CNTL_TIMER1_CPU_STALL_EN = 0x1 + // Position of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Pos = 0x1 + // Bit mask of CPU_STALL_WAIT field. + RTC_CNTL_TIMER1_CPU_STALL_WAIT_Msk = 0x3e + // Position of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Pos = 0x6 + // Bit mask of CK8M_WAIT field. + RTC_CNTL_TIMER1_CK8M_WAIT_Msk = 0x3fc0 + // Position of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Pos = 0xe + // Bit mask of XTL_BUF_WAIT field. + RTC_CNTL_TIMER1_XTL_BUF_WAIT_Msk = 0xffc000 + // Position of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Pos = 0x18 + // Bit mask of PLL_BUF_WAIT field. + RTC_CNTL_TIMER1_PLL_BUF_WAIT_Msk = 0xff000000 + + // TIMER2: rtc monitor state delay time + // Position of ULPCP_TOUCH_START_WAIT field. + RTC_CNTL_TIMER2_ULPCP_TOUCH_START_WAIT_Pos = 0xf + // Bit mask of ULPCP_TOUCH_START_WAIT field. + RTC_CNTL_TIMER2_ULPCP_TOUCH_START_WAIT_Msk = 0xff8000 + // Position of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Pos = 0x18 + // Bit mask of MIN_TIME_CK8M_OFF field. + RTC_CNTL_TIMER2_MIN_TIME_CK8M_OFF_Msk = 0xff000000 + + // TIMER3: No public + // Position of WIFI_WAIT_TIMER field. + RTC_CNTL_TIMER3_WIFI_WAIT_TIMER_Pos = 0x0 + // Bit mask of WIFI_WAIT_TIMER field. + RTC_CNTL_TIMER3_WIFI_WAIT_TIMER_Msk = 0x1ff + // Position of WIFI_POWERUP_TIMER field. + RTC_CNTL_TIMER3_WIFI_POWERUP_TIMER_Pos = 0x9 + // Bit mask of WIFI_POWERUP_TIMER field. + RTC_CNTL_TIMER3_WIFI_POWERUP_TIMER_Msk = 0xfe00 + // Position of BT_WAIT_TIMER field. + RTC_CNTL_TIMER3_BT_WAIT_TIMER_Pos = 0x10 + // Bit mask of BT_WAIT_TIMER field. + RTC_CNTL_TIMER3_BT_WAIT_TIMER_Msk = 0x1ff0000 + // Position of BT_POWERUP_TIMER field. + RTC_CNTL_TIMER3_BT_POWERUP_TIMER_Pos = 0x19 + // Bit mask of BT_POWERUP_TIMER field. + RTC_CNTL_TIMER3_BT_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER4: No public + // Position of WAIT_TIMER field. + RTC_CNTL_TIMER4_WAIT_TIMER_Pos = 0x0 + // Bit mask of WAIT_TIMER field. + RTC_CNTL_TIMER4_WAIT_TIMER_Msk = 0x1ff + // Position of POWERUP_TIMER field. + RTC_CNTL_TIMER4_POWERUP_TIMER_Pos = 0x9 + // Bit mask of POWERUP_TIMER field. + RTC_CNTL_TIMER4_POWERUP_TIMER_Msk = 0xfe00 + // Position of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Pos = 0x10 + // Bit mask of DG_WRAP_WAIT_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_WAIT_TIMER_Msk = 0x1ff0000 + // Position of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Pos = 0x19 + // Bit mask of DG_WRAP_POWERUP_TIMER field. + RTC_CNTL_TIMER4_DG_WRAP_POWERUP_TIMER_Msk = 0xfe000000 + + // TIMER5: configure min sleep time + // Position of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Pos = 0x8 + // Bit mask of MIN_SLP_VAL field. + RTC_CNTL_TIMER5_MIN_SLP_VAL_Msk = 0xff00 + + // TIMER6: No public + // Position of CPU_TOP_WAIT_TIMER field. + RTC_CNTL_TIMER6_CPU_TOP_WAIT_TIMER_Pos = 0x0 + // Bit mask of CPU_TOP_WAIT_TIMER field. + RTC_CNTL_TIMER6_CPU_TOP_WAIT_TIMER_Msk = 0x1ff + // Position of CPU_TOP_POWERUP_TIMER field. + RTC_CNTL_TIMER6_CPU_TOP_POWERUP_TIMER_Pos = 0x9 + // Bit mask of CPU_TOP_POWERUP_TIMER field. + RTC_CNTL_TIMER6_CPU_TOP_POWERUP_TIMER_Msk = 0xfe00 + // Position of DG_PERI_WAIT_TIMER field. + RTC_CNTL_TIMER6_DG_PERI_WAIT_TIMER_Pos = 0x10 + // Bit mask of DG_PERI_WAIT_TIMER field. + RTC_CNTL_TIMER6_DG_PERI_WAIT_TIMER_Msk = 0x1ff0000 + // Position of DG_PERI_POWERUP_TIMER field. + RTC_CNTL_TIMER6_DG_PERI_POWERUP_TIMER_Pos = 0x19 + // Bit mask of DG_PERI_POWERUP_TIMER field. + RTC_CNTL_TIMER6_DG_PERI_POWERUP_TIMER_Msk = 0xfe000000 + + // ANA_CONF: analog configure register + // Position of I2C_RESET_POR_FORCE_PD field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PD_Pos = 0x12 + // Bit mask of I2C_RESET_POR_FORCE_PD field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PD_Msk = 0x40000 + // Bit I2C_RESET_POR_FORCE_PD. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PD = 0x40000 + // Position of I2C_RESET_POR_FORCE_PU field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PU_Pos = 0x13 + // Bit mask of I2C_RESET_POR_FORCE_PU field. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PU_Msk = 0x80000 + // Bit I2C_RESET_POR_FORCE_PU. + RTC_CNTL_ANA_CONF_I2C_RESET_POR_FORCE_PU = 0x80000 + // Position of GLITCH_RST_EN field. + RTC_CNTL_ANA_CONF_GLITCH_RST_EN_Pos = 0x14 + // Bit mask of GLITCH_RST_EN field. + RTC_CNTL_ANA_CONF_GLITCH_RST_EN_Msk = 0x100000 + // Bit GLITCH_RST_EN. + RTC_CNTL_ANA_CONF_GLITCH_RST_EN = 0x100000 + // Position of SAR_I2C_PU field. + RTC_CNTL_ANA_CONF_SAR_I2C_PU_Pos = 0x16 + // Bit mask of SAR_I2C_PU field. + RTC_CNTL_ANA_CONF_SAR_I2C_PU_Msk = 0x400000 + // Bit SAR_I2C_PU. + RTC_CNTL_ANA_CONF_SAR_I2C_PU = 0x400000 + // Position of ANALOG_TOP_ISO_SLEEP field. + RTC_CNTL_ANA_CONF_ANALOG_TOP_ISO_SLEEP_Pos = 0x17 + // Bit mask of ANALOG_TOP_ISO_SLEEP field. + RTC_CNTL_ANA_CONF_ANALOG_TOP_ISO_SLEEP_Msk = 0x800000 + // Bit ANALOG_TOP_ISO_SLEEP. + RTC_CNTL_ANA_CONF_ANALOG_TOP_ISO_SLEEP = 0x800000 + // Position of ANALOG_TOP_ISO_MONITOR field. + RTC_CNTL_ANA_CONF_ANALOG_TOP_ISO_MONITOR_Pos = 0x18 + // Bit mask of ANALOG_TOP_ISO_MONITOR field. + RTC_CNTL_ANA_CONF_ANALOG_TOP_ISO_MONITOR_Msk = 0x1000000 + // Bit ANALOG_TOP_ISO_MONITOR. + RTC_CNTL_ANA_CONF_ANALOG_TOP_ISO_MONITOR = 0x1000000 + // Position of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Pos = 0x19 + // Bit mask of BBPLL_CAL_SLP_START field. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START_Msk = 0x2000000 + // Bit BBPLL_CAL_SLP_START. + RTC_CNTL_ANA_CONF_BBPLL_CAL_SLP_START = 0x2000000 + // Position of PVTMON_PU field. + RTC_CNTL_ANA_CONF_PVTMON_PU_Pos = 0x1a + // Bit mask of PVTMON_PU field. + RTC_CNTL_ANA_CONF_PVTMON_PU_Msk = 0x4000000 + // Bit PVTMON_PU. + RTC_CNTL_ANA_CONF_PVTMON_PU = 0x4000000 + // Position of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Pos = 0x1b + // Bit mask of TXRF_I2C_PU field. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU_Msk = 0x8000000 + // Bit TXRF_I2C_PU. + RTC_CNTL_ANA_CONF_TXRF_I2C_PU = 0x8000000 + // Position of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Pos = 0x1c + // Bit mask of RFRX_PBUS_PU field. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU_Msk = 0x10000000 + // Bit RFRX_PBUS_PU. + RTC_CNTL_ANA_CONF_RFRX_PBUS_PU = 0x10000000 + // Position of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Pos = 0x1e + // Bit mask of CKGEN_I2C_PU field. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU_Msk = 0x40000000 + // Bit CKGEN_I2C_PU. + RTC_CNTL_ANA_CONF_CKGEN_I2C_PU = 0x40000000 + // Position of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Pos = 0x1f + // Bit mask of PLL_I2C_PU field. + RTC_CNTL_ANA_CONF_PLL_I2C_PU_Msk = 0x80000000 + // Bit PLL_I2C_PU. + RTC_CNTL_ANA_CONF_PLL_I2C_PU = 0x80000000 + + // RESET_STATE: get reset state + // Position of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Pos = 0x0 + // Bit mask of RESET_CAUSE_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_PROCPU_Msk = 0x3f + // Position of RESET_CAUSE_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_APPCPU_Pos = 0x6 + // Bit mask of RESET_CAUSE_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_CAUSE_APPCPU_Msk = 0xfc0 + // Position of APPCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_APPCPU_STAT_VECTOR_SEL_Pos = 0xc + // Bit mask of APPCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_APPCPU_STAT_VECTOR_SEL_Msk = 0x1000 + // Bit APPCPU_STAT_VECTOR_SEL. + RTC_CNTL_RESET_STATE_APPCPU_STAT_VECTOR_SEL = 0x1000 + // Position of PROCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_PROCPU_STAT_VECTOR_SEL_Pos = 0xd + // Bit mask of PROCPU_STAT_VECTOR_SEL field. + RTC_CNTL_RESET_STATE_PROCPU_STAT_VECTOR_SEL_Msk = 0x2000 + // Bit PROCPU_STAT_VECTOR_SEL. + RTC_CNTL_RESET_STATE_PROCPU_STAT_VECTOR_SEL = 0x2000 + // Position of RESET_FLAG_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_FLAG_PROCPU_Pos = 0xe + // Bit mask of RESET_FLAG_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_FLAG_PROCPU_Msk = 0x4000 + // Bit RESET_FLAG_PROCPU. + RTC_CNTL_RESET_STATE_RESET_FLAG_PROCPU = 0x4000 + // Position of RESET_FLAG_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_FLAG_APPCPU_Pos = 0xf + // Bit mask of RESET_FLAG_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_FLAG_APPCPU_Msk = 0x8000 + // Bit RESET_FLAG_APPCPU. + RTC_CNTL_RESET_STATE_RESET_FLAG_APPCPU = 0x8000 + // Position of RESET_FLAG_PROCPU_CLR field. + RTC_CNTL_RESET_STATE_RESET_FLAG_PROCPU_CLR_Pos = 0x10 + // Bit mask of RESET_FLAG_PROCPU_CLR field. + RTC_CNTL_RESET_STATE_RESET_FLAG_PROCPU_CLR_Msk = 0x10000 + // Bit RESET_FLAG_PROCPU_CLR. + RTC_CNTL_RESET_STATE_RESET_FLAG_PROCPU_CLR = 0x10000 + // Position of RESET_FLAG_APPCPU_CLR field. + RTC_CNTL_RESET_STATE_RESET_FLAG_APPCPU_CLR_Pos = 0x11 + // Bit mask of RESET_FLAG_APPCPU_CLR field. + RTC_CNTL_RESET_STATE_RESET_FLAG_APPCPU_CLR_Msk = 0x20000 + // Bit RESET_FLAG_APPCPU_CLR. + RTC_CNTL_RESET_STATE_RESET_FLAG_APPCPU_CLR = 0x20000 + // Position of APPCPU_OCD_HALT_ON_RESET field. + RTC_CNTL_RESET_STATE_APPCPU_OCD_HALT_ON_RESET_Pos = 0x12 + // Bit mask of APPCPU_OCD_HALT_ON_RESET field. + RTC_CNTL_RESET_STATE_APPCPU_OCD_HALT_ON_RESET_Msk = 0x40000 + // Bit APPCPU_OCD_HALT_ON_RESET. + RTC_CNTL_RESET_STATE_APPCPU_OCD_HALT_ON_RESET = 0x40000 + // Position of PROCPU_OCD_HALT_ON_RESET field. + RTC_CNTL_RESET_STATE_PROCPU_OCD_HALT_ON_RESET_Pos = 0x13 + // Bit mask of PROCPU_OCD_HALT_ON_RESET field. + RTC_CNTL_RESET_STATE_PROCPU_OCD_HALT_ON_RESET_Msk = 0x80000 + // Bit PROCPU_OCD_HALT_ON_RESET. + RTC_CNTL_RESET_STATE_PROCPU_OCD_HALT_ON_RESET = 0x80000 + // Position of RESET_FLAG_JTAG_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_PROCPU_Pos = 0x14 + // Bit mask of RESET_FLAG_JTAG_PROCPU field. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_PROCPU_Msk = 0x100000 + // Bit RESET_FLAG_JTAG_PROCPU. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_PROCPU = 0x100000 + // Position of RESET_FLAG_JTAG_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_APPCPU_Pos = 0x15 + // Bit mask of RESET_FLAG_JTAG_APPCPU field. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_APPCPU_Msk = 0x200000 + // Bit RESET_FLAG_JTAG_APPCPU. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_APPCPU = 0x200000 + // Position of RESET_FLAG_JTAG_PROCPU_CLR field. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_PROCPU_CLR_Pos = 0x16 + // Bit mask of RESET_FLAG_JTAG_PROCPU_CLR field. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_PROCPU_CLR_Msk = 0x400000 + // Bit RESET_FLAG_JTAG_PROCPU_CLR. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_PROCPU_CLR = 0x400000 + // Position of RESET_FLAG_JTAG_APPCPU_CLR field. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_APPCPU_CLR_Pos = 0x17 + // Bit mask of RESET_FLAG_JTAG_APPCPU_CLR field. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_APPCPU_CLR_Msk = 0x800000 + // Bit RESET_FLAG_JTAG_APPCPU_CLR. + RTC_CNTL_RESET_STATE_RESET_FLAG_JTAG_APPCPU_CLR = 0x800000 + // Position of APP_DRESET_MASK field. + RTC_CNTL_RESET_STATE_APP_DRESET_MASK_Pos = 0x18 + // Bit mask of APP_DRESET_MASK field. + RTC_CNTL_RESET_STATE_APP_DRESET_MASK_Msk = 0x1000000 + // Bit APP_DRESET_MASK. + RTC_CNTL_RESET_STATE_APP_DRESET_MASK = 0x1000000 + // Position of PRO_DRESET_MASK field. + RTC_CNTL_RESET_STATE_PRO_DRESET_MASK_Pos = 0x19 + // Bit mask of PRO_DRESET_MASK field. + RTC_CNTL_RESET_STATE_PRO_DRESET_MASK_Msk = 0x2000000 + // Bit PRO_DRESET_MASK. + RTC_CNTL_RESET_STATE_PRO_DRESET_MASK = 0x2000000 + + // WAKEUP_STATE: configure wakeup state + // Position of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Pos = 0xf + // Bit mask of WAKEUP_ENA field. + RTC_CNTL_WAKEUP_STATE_WAKEUP_ENA_Msk = 0xffff8000 + + // INT_ENA_RTC: configure rtc interrupt register + // Position of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SLP_WAKEUP_INT_ENA = 0x1 + // Position of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SLP_REJECT_INT_ENA = 0x2 + // Position of SDIO_IDLE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SDIO_IDLE_INT_ENA_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SDIO_IDLE_INT_ENA_Msk = 0x4 + // Bit SDIO_IDLE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SDIO_IDLE_INT_ENA = 0x4 + // Position of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA_Pos = 0x3 + // Bit mask of WDT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA_Msk = 0x8 + // Bit WDT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_WDT_INT_ENA = 0x8 + // Position of TOUCH_SCAN_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_SCAN_DONE_INT_ENA = 0x10 + // Position of ULP_CP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_ULP_CP_INT_ENA_Pos = 0x5 + // Bit mask of ULP_CP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_ULP_CP_INT_ENA_Msk = 0x20 + // Bit ULP_CP_INT_ENA. + RTC_CNTL_INT_ENA_RTC_ULP_CP_INT_ENA = 0x20 + // Position of TOUCH_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_DONE_INT_ENA_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_DONE_INT_ENA_Msk = 0x40 + // Bit TOUCH_DONE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_DONE_INT_ENA = 0x40 + // Position of TOUCH_ACTIVE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_ACTIVE_INT_ENA_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_ACTIVE_INT_ENA_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_ACTIVE_INT_ENA = 0x80 + // Position of TOUCH_INACTIVE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_INACTIVE_INT_ENA_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_INACTIVE_INT_ENA_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_INACTIVE_INT_ENA = 0x100 + // Position of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_BROWN_OUT_INT_ENA = 0x200 + // Position of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA. + RTC_CNTL_INT_ENA_RTC_MAIN_TIMER_INT_ENA = 0x400 + // Position of SARADC1_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SARADC1_INT_ENA_Pos = 0xb + // Bit mask of SARADC1_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SARADC1_INT_ENA_Msk = 0x800 + // Bit SARADC1_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SARADC1_INT_ENA = 0x800 + // Position of TSENS_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TSENS_INT_ENA_Pos = 0xc + // Bit mask of TSENS_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TSENS_INT_ENA_Msk = 0x1000 + // Bit TSENS_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TSENS_INT_ENA = 0x1000 + // Position of COCPU_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_COCPU_INT_ENA_Pos = 0xd + // Bit mask of COCPU_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_COCPU_INT_ENA_Msk = 0x2000 + // Bit COCPU_INT_ENA. + RTC_CNTL_INT_ENA_RTC_COCPU_INT_ENA = 0x2000 + // Position of SARADC2_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SARADC2_INT_ENA_Pos = 0xe + // Bit mask of SARADC2_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SARADC2_INT_ENA_Msk = 0x4000 + // Bit SARADC2_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SARADC2_INT_ENA = 0x4000 + // Position of SWD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA_Pos = 0xf + // Bit mask of SWD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA_Msk = 0x8000 + // Bit SWD_INT_ENA. + RTC_CNTL_INT_ENA_RTC_SWD_INT_ENA = 0x8000 + // Position of XTAL32K_DEAD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_XTAL32K_DEAD_INT_ENA_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_XTAL32K_DEAD_INT_ENA_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ENA. + RTC_CNTL_INT_ENA_RTC_XTAL32K_DEAD_INT_ENA = 0x10000 + // Position of COCPU_TRAP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_COCPU_TRAP_INT_ENA_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_COCPU_TRAP_INT_ENA_Msk = 0x20000 + // Bit COCPU_TRAP_INT_ENA. + RTC_CNTL_INT_ENA_RTC_COCPU_TRAP_INT_ENA = 0x20000 + // Position of TOUCH_TIMEOUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_TIMEOUT_INT_ENA = 0x40000 + // Position of GLITCH_DET_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_GLITCH_DET_INT_ENA_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_GLITCH_DET_INT_ENA_Msk = 0x80000 + // Bit GLITCH_DET_INT_ENA. + RTC_CNTL_INT_ENA_RTC_GLITCH_DET_INT_ENA = 0x80000 + // Position of TOUCH_APPROACH_LOOP_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_Pos = 0x14 + // Bit mask of TOUCH_APPROACH_LOOP_DONE_INT_ENA field. + RTC_CNTL_INT_ENA_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_Msk = 0x100000 + // Bit TOUCH_APPROACH_LOOP_DONE_INT_ENA. + RTC_CNTL_INT_ENA_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA = 0x100000 + + // INT_RAW_RTC: rtc interrupt register + // Position of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW_Msk = 0x1 + // Bit SLP_WAKEUP_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SLP_WAKEUP_INT_RAW = 0x1 + // Position of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW_Msk = 0x2 + // Bit SLP_REJECT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SLP_REJECT_INT_RAW = 0x2 + // Position of SDIO_IDLE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SDIO_IDLE_INT_RAW_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SDIO_IDLE_INT_RAW_Msk = 0x4 + // Bit SDIO_IDLE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SDIO_IDLE_INT_RAW = 0x4 + // Position of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW_Pos = 0x3 + // Bit mask of WDT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW_Msk = 0x8 + // Bit WDT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_WDT_INT_RAW = 0x8 + // Position of TOUCH_SCAN_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_SCAN_DONE_INT_RAW = 0x10 + // Position of ULP_CP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_ULP_CP_INT_RAW_Pos = 0x5 + // Bit mask of ULP_CP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_ULP_CP_INT_RAW_Msk = 0x20 + // Bit ULP_CP_INT_RAW. + RTC_CNTL_INT_RAW_RTC_ULP_CP_INT_RAW = 0x20 + // Position of TOUCH_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_DONE_INT_RAW_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_DONE_INT_RAW_Msk = 0x40 + // Bit TOUCH_DONE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_DONE_INT_RAW = 0x40 + // Position of TOUCH_ACTIVE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_ACTIVE_INT_RAW_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_ACTIVE_INT_RAW_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_ACTIVE_INT_RAW = 0x80 + // Position of TOUCH_INACTIVE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_INACTIVE_INT_RAW_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_INACTIVE_INT_RAW_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_INACTIVE_INT_RAW = 0x100 + // Position of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW_Msk = 0x200 + // Bit BROWN_OUT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_BROWN_OUT_INT_RAW = 0x200 + // Position of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW_Msk = 0x400 + // Bit MAIN_TIMER_INT_RAW. + RTC_CNTL_INT_RAW_RTC_MAIN_TIMER_INT_RAW = 0x400 + // Position of SARADC1_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SARADC1_INT_RAW_Pos = 0xb + // Bit mask of SARADC1_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SARADC1_INT_RAW_Msk = 0x800 + // Bit SARADC1_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SARADC1_INT_RAW = 0x800 + // Position of TSENS_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TSENS_INT_RAW_Pos = 0xc + // Bit mask of TSENS_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TSENS_INT_RAW_Msk = 0x1000 + // Bit TSENS_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TSENS_INT_RAW = 0x1000 + // Position of COCPU_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_COCPU_INT_RAW_Pos = 0xd + // Bit mask of COCPU_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_COCPU_INT_RAW_Msk = 0x2000 + // Bit COCPU_INT_RAW. + RTC_CNTL_INT_RAW_RTC_COCPU_INT_RAW = 0x2000 + // Position of SARADC2_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SARADC2_INT_RAW_Pos = 0xe + // Bit mask of SARADC2_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SARADC2_INT_RAW_Msk = 0x4000 + // Bit SARADC2_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SARADC2_INT_RAW = 0x4000 + // Position of SWD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW_Pos = 0xf + // Bit mask of SWD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW_Msk = 0x8000 + // Bit SWD_INT_RAW. + RTC_CNTL_INT_RAW_RTC_SWD_INT_RAW = 0x8000 + // Position of XTAL32K_DEAD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_XTAL32K_DEAD_INT_RAW_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_XTAL32K_DEAD_INT_RAW_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_RAW. + RTC_CNTL_INT_RAW_RTC_XTAL32K_DEAD_INT_RAW = 0x10000 + // Position of COCPU_TRAP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_COCPU_TRAP_INT_RAW_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_COCPU_TRAP_INT_RAW_Msk = 0x20000 + // Bit COCPU_TRAP_INT_RAW. + RTC_CNTL_INT_RAW_RTC_COCPU_TRAP_INT_RAW = 0x20000 + // Position of TOUCH_TIMEOUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_TIMEOUT_INT_RAW = 0x40000 + // Position of GLITCH_DET_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_GLITCH_DET_INT_RAW_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_GLITCH_DET_INT_RAW_Msk = 0x80000 + // Bit GLITCH_DET_INT_RAW. + RTC_CNTL_INT_RAW_RTC_GLITCH_DET_INT_RAW = 0x80000 + // Position of TOUCH_APPROACH_LOOP_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_Pos = 0x14 + // Bit mask of TOUCH_APPROACH_LOOP_DONE_INT_RAW field. + RTC_CNTL_INT_RAW_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_Msk = 0x100000 + // Bit TOUCH_APPROACH_LOOP_DONE_INT_RAW. + RTC_CNTL_INT_RAW_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW = 0x100000 + + // INT_ST_RTC: rtc interrupt register + // Position of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ST. + RTC_CNTL_INT_ST_RTC_SLP_WAKEUP_INT_ST = 0x1 + // Position of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ST field. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST_Msk = 0x2 + // Bit SLP_REJECT_INT_ST. + RTC_CNTL_INT_ST_RTC_SLP_REJECT_INT_ST = 0x2 + // Position of SDIO_IDLE_INT_ST field. + RTC_CNTL_INT_ST_RTC_SDIO_IDLE_INT_ST_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_ST field. + RTC_CNTL_INT_ST_RTC_SDIO_IDLE_INT_ST_Msk = 0x4 + // Bit SDIO_IDLE_INT_ST. + RTC_CNTL_INT_ST_RTC_SDIO_IDLE_INT_ST = 0x4 + // Position of WDT_INT_ST field. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST_Pos = 0x3 + // Bit mask of WDT_INT_ST field. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST_Msk = 0x8 + // Bit WDT_INT_ST. + RTC_CNTL_INT_ST_RTC_WDT_INT_ST = 0x8 + // Position of TOUCH_SCAN_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_SCAN_DONE_INT_ST_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_SCAN_DONE_INT_ST_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_SCAN_DONE_INT_ST = 0x10 + // Position of ULP_CP_INT_ST field. + RTC_CNTL_INT_ST_RTC_ULP_CP_INT_ST_Pos = 0x5 + // Bit mask of ULP_CP_INT_ST field. + RTC_CNTL_INT_ST_RTC_ULP_CP_INT_ST_Msk = 0x20 + // Bit ULP_CP_INT_ST. + RTC_CNTL_INT_ST_RTC_ULP_CP_INT_ST = 0x20 + // Position of TOUCH_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_DONE_INT_ST_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_DONE_INT_ST_Msk = 0x40 + // Bit TOUCH_DONE_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_DONE_INT_ST = 0x40 + // Position of TOUCH_ACTIVE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_ACTIVE_INT_ST_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_ACTIVE_INT_ST_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_ACTIVE_INT_ST = 0x80 + // Position of TOUCH_INACTIVE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_INACTIVE_INT_ST_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_INACTIVE_INT_ST_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_INACTIVE_INT_ST = 0x100 + // Position of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST_Msk = 0x200 + // Bit BROWN_OUT_INT_ST. + RTC_CNTL_INT_ST_RTC_BROWN_OUT_INT_ST = 0x200 + // Position of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ST field. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST_Msk = 0x400 + // Bit MAIN_TIMER_INT_ST. + RTC_CNTL_INT_ST_RTC_MAIN_TIMER_INT_ST = 0x400 + // Position of SARADC1_INT_ST field. + RTC_CNTL_INT_ST_RTC_SARADC1_INT_ST_Pos = 0xb + // Bit mask of SARADC1_INT_ST field. + RTC_CNTL_INT_ST_RTC_SARADC1_INT_ST_Msk = 0x800 + // Bit SARADC1_INT_ST. + RTC_CNTL_INT_ST_RTC_SARADC1_INT_ST = 0x800 + // Position of TSENS_INT_ST field. + RTC_CNTL_INT_ST_RTC_TSENS_INT_ST_Pos = 0xc + // Bit mask of TSENS_INT_ST field. + RTC_CNTL_INT_ST_RTC_TSENS_INT_ST_Msk = 0x1000 + // Bit TSENS_INT_ST. + RTC_CNTL_INT_ST_RTC_TSENS_INT_ST = 0x1000 + // Position of COCPU_INT_ST field. + RTC_CNTL_INT_ST_RTC_COCPU_INT_ST_Pos = 0xd + // Bit mask of COCPU_INT_ST field. + RTC_CNTL_INT_ST_RTC_COCPU_INT_ST_Msk = 0x2000 + // Bit COCPU_INT_ST. + RTC_CNTL_INT_ST_RTC_COCPU_INT_ST = 0x2000 + // Position of SARADC2_INT_ST field. + RTC_CNTL_INT_ST_RTC_SARADC2_INT_ST_Pos = 0xe + // Bit mask of SARADC2_INT_ST field. + RTC_CNTL_INT_ST_RTC_SARADC2_INT_ST_Msk = 0x4000 + // Bit SARADC2_INT_ST. + RTC_CNTL_INT_ST_RTC_SARADC2_INT_ST = 0x4000 + // Position of SWD_INT_ST field. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST_Pos = 0xf + // Bit mask of SWD_INT_ST field. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST_Msk = 0x8000 + // Bit SWD_INT_ST. + RTC_CNTL_INT_ST_RTC_SWD_INT_ST = 0x8000 + // Position of XTAL32K_DEAD_INT_ST field. + RTC_CNTL_INT_ST_RTC_XTAL32K_DEAD_INT_ST_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ST field. + RTC_CNTL_INT_ST_RTC_XTAL32K_DEAD_INT_ST_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ST. + RTC_CNTL_INT_ST_RTC_XTAL32K_DEAD_INT_ST = 0x10000 + // Position of COCPU_TRAP_INT_ST field. + RTC_CNTL_INT_ST_RTC_COCPU_TRAP_INT_ST_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_ST field. + RTC_CNTL_INT_ST_RTC_COCPU_TRAP_INT_ST_Msk = 0x20000 + // Bit COCPU_TRAP_INT_ST. + RTC_CNTL_INT_ST_RTC_COCPU_TRAP_INT_ST = 0x20000 + // Position of TOUCH_TIMEOUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_TIMEOUT_INT_ST_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_TIMEOUT_INT_ST_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_TIMEOUT_INT_ST = 0x40000 + // Position of GLITCH_DET_INT_ST field. + RTC_CNTL_INT_ST_RTC_GLITCH_DET_INT_ST_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ST field. + RTC_CNTL_INT_ST_RTC_GLITCH_DET_INT_ST_Msk = 0x80000 + // Bit GLITCH_DET_INT_ST. + RTC_CNTL_INT_ST_RTC_GLITCH_DET_INT_ST = 0x80000 + // Position of TOUCH_APPROACH_LOOP_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_Pos = 0x14 + // Bit mask of TOUCH_APPROACH_LOOP_DONE_INT_ST field. + RTC_CNTL_INT_ST_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_Msk = 0x100000 + // Bit TOUCH_APPROACH_LOOP_DONE_INT_ST. + RTC_CNTL_INT_ST_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST = 0x100000 + + // INT_CLR_RTC: rtc interrupt register + // Position of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR_Msk = 0x1 + // Bit SLP_WAKEUP_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SLP_WAKEUP_INT_CLR = 0x1 + // Position of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR_Msk = 0x2 + // Bit SLP_REJECT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SLP_REJECT_INT_CLR = 0x2 + // Position of SDIO_IDLE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SDIO_IDLE_INT_CLR_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SDIO_IDLE_INT_CLR_Msk = 0x4 + // Bit SDIO_IDLE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SDIO_IDLE_INT_CLR = 0x4 + // Position of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR_Pos = 0x3 + // Bit mask of WDT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR_Msk = 0x8 + // Bit WDT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_WDT_INT_CLR = 0x8 + // Position of TOUCH_SCAN_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_SCAN_DONE_INT_CLR = 0x10 + // Position of ULP_CP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_ULP_CP_INT_CLR_Pos = 0x5 + // Bit mask of ULP_CP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_ULP_CP_INT_CLR_Msk = 0x20 + // Bit ULP_CP_INT_CLR. + RTC_CNTL_INT_CLR_RTC_ULP_CP_INT_CLR = 0x20 + // Position of TOUCH_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_DONE_INT_CLR_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_DONE_INT_CLR_Msk = 0x40 + // Bit TOUCH_DONE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_DONE_INT_CLR = 0x40 + // Position of TOUCH_ACTIVE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_ACTIVE_INT_CLR_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_ACTIVE_INT_CLR_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_ACTIVE_INT_CLR = 0x80 + // Position of TOUCH_INACTIVE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_INACTIVE_INT_CLR_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_INACTIVE_INT_CLR_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_INACTIVE_INT_CLR = 0x100 + // Position of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR_Msk = 0x200 + // Bit BROWN_OUT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_BROWN_OUT_INT_CLR = 0x200 + // Position of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR_Msk = 0x400 + // Bit MAIN_TIMER_INT_CLR. + RTC_CNTL_INT_CLR_RTC_MAIN_TIMER_INT_CLR = 0x400 + // Position of SARADC1_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SARADC1_INT_CLR_Pos = 0xb + // Bit mask of SARADC1_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SARADC1_INT_CLR_Msk = 0x800 + // Bit SARADC1_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SARADC1_INT_CLR = 0x800 + // Position of TSENS_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TSENS_INT_CLR_Pos = 0xc + // Bit mask of TSENS_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TSENS_INT_CLR_Msk = 0x1000 + // Bit TSENS_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TSENS_INT_CLR = 0x1000 + // Position of COCPU_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_COCPU_INT_CLR_Pos = 0xd + // Bit mask of COCPU_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_COCPU_INT_CLR_Msk = 0x2000 + // Bit COCPU_INT_CLR. + RTC_CNTL_INT_CLR_RTC_COCPU_INT_CLR = 0x2000 + // Position of SARADC2_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SARADC2_INT_CLR_Pos = 0xe + // Bit mask of SARADC2_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SARADC2_INT_CLR_Msk = 0x4000 + // Bit SARADC2_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SARADC2_INT_CLR = 0x4000 + // Position of SWD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR_Pos = 0xf + // Bit mask of SWD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR_Msk = 0x8000 + // Bit SWD_INT_CLR. + RTC_CNTL_INT_CLR_RTC_SWD_INT_CLR = 0x8000 + // Position of XTAL32K_DEAD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_XTAL32K_DEAD_INT_CLR_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_XTAL32K_DEAD_INT_CLR_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_CLR. + RTC_CNTL_INT_CLR_RTC_XTAL32K_DEAD_INT_CLR = 0x10000 + // Position of COCPU_TRAP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_COCPU_TRAP_INT_CLR_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_COCPU_TRAP_INT_CLR_Msk = 0x20000 + // Bit COCPU_TRAP_INT_CLR. + RTC_CNTL_INT_CLR_RTC_COCPU_TRAP_INT_CLR = 0x20000 + // Position of TOUCH_TIMEOUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_TIMEOUT_INT_CLR = 0x40000 + // Position of GLITCH_DET_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_GLITCH_DET_INT_CLR_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_GLITCH_DET_INT_CLR_Msk = 0x80000 + // Bit GLITCH_DET_INT_CLR. + RTC_CNTL_INT_CLR_RTC_GLITCH_DET_INT_CLR = 0x80000 + // Position of TOUCH_APPROACH_LOOP_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_Pos = 0x14 + // Bit mask of TOUCH_APPROACH_LOOP_DONE_INT_CLR field. + RTC_CNTL_INT_CLR_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_Msk = 0x100000 + // Bit TOUCH_APPROACH_LOOP_DONE_INT_CLR. + RTC_CNTL_INT_CLR_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR = 0x100000 + + // STORE0: Reserved register + // Position of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Pos = 0x0 + // Bit mask of SCRATCH0 field. + RTC_CNTL_STORE0_SCRATCH0_Msk = 0xffffffff + + // STORE1: Reserved register + // Position of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Pos = 0x0 + // Bit mask of SCRATCH1 field. + RTC_CNTL_STORE1_SCRATCH1_Msk = 0xffffffff + + // STORE2: Reserved register + // Position of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Pos = 0x0 + // Bit mask of SCRATCH2 field. + RTC_CNTL_STORE2_SCRATCH2_Msk = 0xffffffff + + // STORE3: Reserved register + // Position of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Pos = 0x0 + // Bit mask of SCRATCH3 field. + RTC_CNTL_STORE3_SCRATCH3_Msk = 0xffffffff + + // EXT_XTL_CONF: Reserved register + // Position of XTAL32K_WDT_EN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_EN_Pos = 0x0 + // Bit mask of XTAL32K_WDT_EN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_EN_Msk = 0x1 + // Bit XTAL32K_WDT_EN. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_EN = 0x1 + // Position of XTAL32K_WDT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_CLK_FO_Pos = 0x1 + // Bit mask of XTAL32K_WDT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_CLK_FO_Msk = 0x2 + // Bit XTAL32K_WDT_CLK_FO. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_CLK_FO = 0x2 + // Position of XTAL32K_WDT_RESET field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_RESET_Pos = 0x2 + // Bit mask of XTAL32K_WDT_RESET field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_RESET_Msk = 0x4 + // Bit XTAL32K_WDT_RESET. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_WDT_RESET = 0x4 + // Position of XTAL32K_EXT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_EXT_CLK_FO_Pos = 0x3 + // Bit mask of XTAL32K_EXT_CLK_FO field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_EXT_CLK_FO_Msk = 0x8 + // Bit XTAL32K_EXT_CLK_FO. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_EXT_CLK_FO = 0x8 + // Position of XTAL32K_AUTO_BACKUP field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_BACKUP_Pos = 0x4 + // Bit mask of XTAL32K_AUTO_BACKUP field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_BACKUP_Msk = 0x10 + // Bit XTAL32K_AUTO_BACKUP. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_BACKUP = 0x10 + // Position of XTAL32K_AUTO_RESTART field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RESTART_Pos = 0x5 + // Bit mask of XTAL32K_AUTO_RESTART field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RESTART_Msk = 0x20 + // Bit XTAL32K_AUTO_RESTART. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RESTART = 0x20 + // Position of XTAL32K_AUTO_RETURN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RETURN_Pos = 0x6 + // Bit mask of XTAL32K_AUTO_RETURN field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RETURN_Msk = 0x40 + // Bit XTAL32K_AUTO_RETURN. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_AUTO_RETURN = 0x40 + // Position of XTAL32K_XPD_FORCE field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_XPD_FORCE_Pos = 0x7 + // Bit mask of XTAL32K_XPD_FORCE field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_XPD_FORCE_Msk = 0x80 + // Bit XTAL32K_XPD_FORCE. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_XPD_FORCE = 0x80 + // Position of ENCKINIT_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_ENCKINIT_XTAL_32K_Pos = 0x8 + // Bit mask of ENCKINIT_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_ENCKINIT_XTAL_32K_Msk = 0x100 + // Bit ENCKINIT_XTAL_32K. + RTC_CNTL_EXT_XTL_CONF_ENCKINIT_XTAL_32K = 0x100 + // Position of DBUF_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DBUF_XTAL_32K_Pos = 0x9 + // Bit mask of DBUF_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DBUF_XTAL_32K_Msk = 0x200 + // Bit DBUF_XTAL_32K. + RTC_CNTL_EXT_XTL_CONF_DBUF_XTAL_32K = 0x200 + // Position of DGM_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DGM_XTAL_32K_Pos = 0xa + // Bit mask of DGM_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DGM_XTAL_32K_Msk = 0x1c00 + // Position of DRES_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DRES_XTAL_32K_Pos = 0xd + // Bit mask of DRES_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DRES_XTAL_32K_Msk = 0xe000 + // Position of XPD_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_XPD_XTAL_32K_Pos = 0x10 + // Bit mask of XPD_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_XPD_XTAL_32K_Msk = 0x10000 + // Bit XPD_XTAL_32K. + RTC_CNTL_EXT_XTL_CONF_XPD_XTAL_32K = 0x10000 + // Position of DAC_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DAC_XTAL_32K_Pos = 0x11 + // Bit mask of DAC_XTAL_32K field. + RTC_CNTL_EXT_XTL_CONF_DAC_XTAL_32K_Msk = 0xe0000 + // Position of WDT_STATE field. + RTC_CNTL_EXT_XTL_CONF_WDT_STATE_Pos = 0x14 + // Bit mask of WDT_STATE field. + RTC_CNTL_EXT_XTL_CONF_WDT_STATE_Msk = 0x700000 + // Position of XTAL32K_GPIO_SEL field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_GPIO_SEL_Pos = 0x17 + // Bit mask of XTAL32K_GPIO_SEL field. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_GPIO_SEL_Msk = 0x800000 + // Bit XTAL32K_GPIO_SEL. + RTC_CNTL_EXT_XTL_CONF_XTAL32K_GPIO_SEL = 0x800000 + // Position of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Pos = 0x1e + // Bit mask of XTL_EXT_CTR_LV field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV_Msk = 0x40000000 + // Bit XTL_EXT_CTR_LV. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_LV = 0x40000000 + // Position of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Pos = 0x1f + // Bit mask of XTL_EXT_CTR_EN field. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN_Msk = 0x80000000 + // Bit XTL_EXT_CTR_EN. + RTC_CNTL_EXT_XTL_CONF_XTL_EXT_CTR_EN = 0x80000000 + + // EXT_WAKEUP_CONF: ext wakeup configure + // Position of GPIO_WAKEUP_FILTER field. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER_Pos = 0x1d + // Bit mask of GPIO_WAKEUP_FILTER field. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER_Msk = 0x20000000 + // Bit GPIO_WAKEUP_FILTER. + RTC_CNTL_EXT_WAKEUP_CONF_GPIO_WAKEUP_FILTER = 0x20000000 + // Position of EXT_WAKEUP0_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP0_LV_Pos = 0x1e + // Bit mask of EXT_WAKEUP0_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP0_LV_Msk = 0x40000000 + // Bit EXT_WAKEUP0_LV. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP0_LV = 0x40000000 + // Position of EXT_WAKEUP1_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP1_LV_Pos = 0x1f + // Bit mask of EXT_WAKEUP1_LV field. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP1_LV_Msk = 0x80000000 + // Bit EXT_WAKEUP1_LV. + RTC_CNTL_EXT_WAKEUP_CONF_EXT_WAKEUP1_LV = 0x80000000 + + // SLP_REJECT_CONF: reject sleep register + // Position of SLEEP_REJECT_ENA field. + RTC_CNTL_SLP_REJECT_CONF_SLEEP_REJECT_ENA_Pos = 0xc + // Bit mask of SLEEP_REJECT_ENA field. + RTC_CNTL_SLP_REJECT_CONF_SLEEP_REJECT_ENA_Msk = 0x3ffff000 + // Position of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Pos = 0x1e + // Bit mask of LIGHT_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN_Msk = 0x40000000 + // Bit LIGHT_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_LIGHT_SLP_REJECT_EN = 0x40000000 + // Position of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Pos = 0x1f + // Bit mask of DEEP_SLP_REJECT_EN field. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN_Msk = 0x80000000 + // Bit DEEP_SLP_REJECT_EN. + RTC_CNTL_SLP_REJECT_CONF_DEEP_SLP_REJECT_EN = 0x80000000 + + // CPU_PERIOD_CONF: conigure cpu freq + // Position of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Pos = 0x1d + // Bit mask of CPUSEL_CONF field. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF_Msk = 0x20000000 + // Bit CPUSEL_CONF. + RTC_CNTL_CPU_PERIOD_CONF_CPUSEL_CONF = 0x20000000 + // Position of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Pos = 0x1e + // Bit mask of CPUPERIOD_SEL field. + RTC_CNTL_CPU_PERIOD_CONF_CPUPERIOD_SEL_Msk = 0xc0000000 + + // SDIO_ACT_CONF: No public + // Position of SDIO_ACT_DNUM field. + RTC_CNTL_SDIO_ACT_CONF_SDIO_ACT_DNUM_Pos = 0x16 + // Bit mask of SDIO_ACT_DNUM field. + RTC_CNTL_SDIO_ACT_CONF_SDIO_ACT_DNUM_Msk = 0xffc00000 + + // CLK_CONF: configure clock register + // Position of EFUSE_CLK_FORCE_GATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_GATING_Pos = 0x1 + // Bit mask of EFUSE_CLK_FORCE_GATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_GATING_Msk = 0x2 + // Bit EFUSE_CLK_FORCE_GATING. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_GATING = 0x2 + // Position of EFUSE_CLK_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_NOGATING_Pos = 0x2 + // Bit mask of EFUSE_CLK_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_NOGATING_Msk = 0x4 + // Bit EFUSE_CLK_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_EFUSE_CLK_FORCE_NOGATING = 0x4 + // Position of CK8M_DIV_SEL_VLD field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD_Pos = 0x3 + // Bit mask of CK8M_DIV_SEL_VLD field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD_Msk = 0x8 + // Bit CK8M_DIV_SEL_VLD. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_VLD = 0x8 + // Position of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Pos = 0x4 + // Bit mask of CK8M_DIV field. + RTC_CNTL_CLK_CONF_CK8M_DIV_Msk = 0x30 + // Position of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Pos = 0x6 + // Bit mask of ENB_CK8M field. + RTC_CNTL_CLK_CONF_ENB_CK8M_Msk = 0x40 + // Bit ENB_CK8M. + RTC_CNTL_CLK_CONF_ENB_CK8M = 0x40 + // Position of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Pos = 0x7 + // Bit mask of ENB_CK8M_DIV field. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV_Msk = 0x80 + // Bit ENB_CK8M_DIV. + RTC_CNTL_CLK_CONF_ENB_CK8M_DIV = 0x80 + // Position of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Pos = 0x8 + // Bit mask of DIG_XTAL32K_EN field. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN_Msk = 0x100 + // Bit DIG_XTAL32K_EN. + RTC_CNTL_CLK_CONF_DIG_XTAL32K_EN = 0x100 + // Position of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Pos = 0x9 + // Bit mask of DIG_CLK8M_D256_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN_Msk = 0x200 + // Bit DIG_CLK8M_D256_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_D256_EN = 0x200 + // Position of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Pos = 0xa + // Bit mask of DIG_CLK8M_EN field. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN_Msk = 0x400 + // Bit DIG_CLK8M_EN. + RTC_CNTL_CLK_CONF_DIG_CLK8M_EN = 0x400 + // Position of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Pos = 0xc + // Bit mask of CK8M_DIV_SEL field. + RTC_CNTL_CLK_CONF_CK8M_DIV_SEL_Msk = 0x7000 + // Position of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Pos = 0xf + // Bit mask of XTAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING_Msk = 0x8000 + // Bit XTAL_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_XTAL_FORCE_NOGATING = 0x8000 + // Position of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Pos = 0x10 + // Bit mask of CK8M_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING_Msk = 0x10000 + // Bit CK8M_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_CK8M_FORCE_NOGATING = 0x10000 + // Position of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Pos = 0x11 + // Bit mask of CK8M_DFREQ field. + RTC_CNTL_CLK_CONF_CK8M_DFREQ_Msk = 0x1fe0000 + // Position of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Pos = 0x19 + // Bit mask of CK8M_FORCE_PD field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD_Msk = 0x2000000 + // Bit CK8M_FORCE_PD. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PD = 0x2000000 + // Position of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Pos = 0x1a + // Bit mask of CK8M_FORCE_PU field. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU_Msk = 0x4000000 + // Bit CK8M_FORCE_PU. + RTC_CNTL_CLK_CONF_CK8M_FORCE_PU = 0x4000000 + // Position of XTAL_GLOBAL_FORCE_GATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_GATING_Pos = 0x1b + // Bit mask of XTAL_GLOBAL_FORCE_GATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_GATING_Msk = 0x8000000 + // Bit XTAL_GLOBAL_FORCE_GATING. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_GATING = 0x8000000 + // Position of XTAL_GLOBAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_NOGATING_Pos = 0x1c + // Bit mask of XTAL_GLOBAL_FORCE_NOGATING field. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_NOGATING_Msk = 0x10000000 + // Bit XTAL_GLOBAL_FORCE_NOGATING. + RTC_CNTL_CLK_CONF_XTAL_GLOBAL_FORCE_NOGATING = 0x10000000 + // Position of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Pos = 0x1d + // Bit mask of FAST_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL_Msk = 0x20000000 + // Bit FAST_CLK_RTC_SEL. + RTC_CNTL_CLK_CONF_FAST_CLK_RTC_SEL = 0x20000000 + // Position of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Pos = 0x1e + // Bit mask of ANA_CLK_RTC_SEL field. + RTC_CNTL_CLK_CONF_ANA_CLK_RTC_SEL_Msk = 0xc0000000 + + // SLOW_CLK_CONF: configure slow clk + // Position of ANA_CLK_DIV_VLD field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD_Pos = 0x16 + // Bit mask of ANA_CLK_DIV_VLD field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD_Msk = 0x400000 + // Bit ANA_CLK_DIV_VLD. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_VLD = 0x400000 + // Position of ANA_CLK_DIV field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_Pos = 0x17 + // Bit mask of ANA_CLK_DIV field. + RTC_CNTL_SLOW_CLK_CONF_ANA_CLK_DIV_Msk = 0x7f800000 + // Position of SLOW_CLK_NEXT_EDGE field. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE_Pos = 0x1f + // Bit mask of SLOW_CLK_NEXT_EDGE field. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE_Msk = 0x80000000 + // Bit SLOW_CLK_NEXT_EDGE. + RTC_CNTL_SLOW_CLK_CONF_SLOW_CLK_NEXT_EDGE = 0x80000000 + + // SDIO_CONF: configure flash power + // Position of SDIO_TIMER_TARGET field. + RTC_CNTL_SDIO_CONF_SDIO_TIMER_TARGET_Pos = 0x0 + // Bit mask of SDIO_TIMER_TARGET field. + RTC_CNTL_SDIO_CONF_SDIO_TIMER_TARGET_Msk = 0xff + // Position of SDIO_DTHDRV field. + RTC_CNTL_SDIO_CONF_SDIO_DTHDRV_Pos = 0x9 + // Bit mask of SDIO_DTHDRV field. + RTC_CNTL_SDIO_CONF_SDIO_DTHDRV_Msk = 0x600 + // Position of SDIO_DCAP field. + RTC_CNTL_SDIO_CONF_SDIO_DCAP_Pos = 0xb + // Bit mask of SDIO_DCAP field. + RTC_CNTL_SDIO_CONF_SDIO_DCAP_Msk = 0x1800 + // Position of SDIO_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_INITI_Pos = 0xd + // Bit mask of SDIO_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_INITI_Msk = 0x6000 + // Position of SDIO_EN_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_EN_INITI_Pos = 0xf + // Bit mask of SDIO_EN_INITI field. + RTC_CNTL_SDIO_CONF_SDIO_EN_INITI_Msk = 0x8000 + // Bit SDIO_EN_INITI. + RTC_CNTL_SDIO_CONF_SDIO_EN_INITI = 0x8000 + // Position of SDIO_DCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_DCURLIM_Pos = 0x10 + // Bit mask of SDIO_DCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_DCURLIM_Msk = 0x70000 + // Position of SDIO_MODECURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_MODECURLIM_Pos = 0x13 + // Bit mask of SDIO_MODECURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_MODECURLIM_Msk = 0x80000 + // Bit SDIO_MODECURLIM. + RTC_CNTL_SDIO_CONF_SDIO_MODECURLIM = 0x80000 + // Position of SDIO_ENCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_ENCURLIM_Pos = 0x14 + // Bit mask of SDIO_ENCURLIM field. + RTC_CNTL_SDIO_CONF_SDIO_ENCURLIM_Msk = 0x100000 + // Bit SDIO_ENCURLIM. + RTC_CNTL_SDIO_CONF_SDIO_ENCURLIM = 0x100000 + // Position of SDIO_REG_PD_EN field. + RTC_CNTL_SDIO_CONF_SDIO_REG_PD_EN_Pos = 0x15 + // Bit mask of SDIO_REG_PD_EN field. + RTC_CNTL_SDIO_CONF_SDIO_REG_PD_EN_Msk = 0x200000 + // Bit SDIO_REG_PD_EN. + RTC_CNTL_SDIO_CONF_SDIO_REG_PD_EN = 0x200000 + // Position of SDIO_FORCE field. + RTC_CNTL_SDIO_CONF_SDIO_FORCE_Pos = 0x16 + // Bit mask of SDIO_FORCE field. + RTC_CNTL_SDIO_CONF_SDIO_FORCE_Msk = 0x400000 + // Bit SDIO_FORCE. + RTC_CNTL_SDIO_CONF_SDIO_FORCE = 0x400000 + // Position of SDIO_TIEH field. + RTC_CNTL_SDIO_CONF_SDIO_TIEH_Pos = 0x17 + // Bit mask of SDIO_TIEH field. + RTC_CNTL_SDIO_CONF_SDIO_TIEH_Msk = 0x800000 + // Bit SDIO_TIEH. + RTC_CNTL_SDIO_CONF_SDIO_TIEH = 0x800000 + // Position of REG1P8_READY field. + RTC_CNTL_SDIO_CONF_REG1P8_READY_Pos = 0x18 + // Bit mask of REG1P8_READY field. + RTC_CNTL_SDIO_CONF_REG1P8_READY_Msk = 0x1000000 + // Bit REG1P8_READY. + RTC_CNTL_SDIO_CONF_REG1P8_READY = 0x1000000 + // Position of DREFL_SDIO field. + RTC_CNTL_SDIO_CONF_DREFL_SDIO_Pos = 0x19 + // Bit mask of DREFL_SDIO field. + RTC_CNTL_SDIO_CONF_DREFL_SDIO_Msk = 0x6000000 + // Position of DREFM_SDIO field. + RTC_CNTL_SDIO_CONF_DREFM_SDIO_Pos = 0x1b + // Bit mask of DREFM_SDIO field. + RTC_CNTL_SDIO_CONF_DREFM_SDIO_Msk = 0x18000000 + // Position of DREFH_SDIO field. + RTC_CNTL_SDIO_CONF_DREFH_SDIO_Pos = 0x1d + // Bit mask of DREFH_SDIO field. + RTC_CNTL_SDIO_CONF_DREFH_SDIO_Msk = 0x60000000 + // Position of XPD_SDIO field. + RTC_CNTL_SDIO_CONF_XPD_SDIO_Pos = 0x1f + // Bit mask of XPD_SDIO field. + RTC_CNTL_SDIO_CONF_XPD_SDIO_Msk = 0x80000000 + // Bit XPD_SDIO. + RTC_CNTL_SDIO_CONF_XPD_SDIO = 0x80000000 + + // BIAS_CONF: No public + // Position of BIAS_BUF_IDLE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE_Pos = 0xa + // Bit mask of BIAS_BUF_IDLE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE_Msk = 0x400 + // Bit BIAS_BUF_IDLE. + RTC_CNTL_BIAS_CONF_BIAS_BUF_IDLE = 0x400 + // Position of BIAS_BUF_WAKE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE_Pos = 0xb + // Bit mask of BIAS_BUF_WAKE field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE_Msk = 0x800 + // Bit BIAS_BUF_WAKE. + RTC_CNTL_BIAS_CONF_BIAS_BUF_WAKE = 0x800 + // Position of BIAS_BUF_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP_Pos = 0xc + // Bit mask of BIAS_BUF_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP_Msk = 0x1000 + // Bit BIAS_BUF_DEEP_SLP. + RTC_CNTL_BIAS_CONF_BIAS_BUF_DEEP_SLP = 0x1000 + // Position of BIAS_BUF_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR_Pos = 0xd + // Bit mask of BIAS_BUF_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR_Msk = 0x2000 + // Bit BIAS_BUF_MONITOR. + RTC_CNTL_BIAS_CONF_BIAS_BUF_MONITOR = 0x2000 + // Position of PD_CUR_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP_Pos = 0xe + // Bit mask of PD_CUR_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP_Msk = 0x4000 + // Bit PD_CUR_DEEP_SLP. + RTC_CNTL_BIAS_CONF_PD_CUR_DEEP_SLP = 0x4000 + // Position of PD_CUR_MONITOR field. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR_Pos = 0xf + // Bit mask of PD_CUR_MONITOR field. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR_Msk = 0x8000 + // Bit PD_CUR_MONITOR. + RTC_CNTL_BIAS_CONF_PD_CUR_MONITOR = 0x8000 + // Position of BIAS_SLEEP_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP_Pos = 0x10 + // Bit mask of BIAS_SLEEP_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP_Msk = 0x10000 + // Bit BIAS_SLEEP_DEEP_SLP. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_DEEP_SLP = 0x10000 + // Position of BIAS_SLEEP_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR_Pos = 0x11 + // Bit mask of BIAS_SLEEP_MONITOR field. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR_Msk = 0x20000 + // Bit BIAS_SLEEP_MONITOR. + RTC_CNTL_BIAS_CONF_BIAS_SLEEP_MONITOR = 0x20000 + // Position of DBG_ATTEN_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_DEEP_SLP_Pos = 0x12 + // Bit mask of DBG_ATTEN_DEEP_SLP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_DEEP_SLP_Msk = 0x3c0000 + // Position of DBG_ATTEN_MONITOR field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_MONITOR_Pos = 0x16 + // Bit mask of DBG_ATTEN_MONITOR field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_MONITOR_Msk = 0x3c00000 + // Position of DBG_ATTEN_WAKEUP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_WAKEUP_Pos = 0x1a + // Bit mask of DBG_ATTEN_WAKEUP field. + RTC_CNTL_BIAS_CONF_DBG_ATTEN_WAKEUP_Msk = 0x3c000000 + + // RTC: configure rtc regulator + // Position of DIG_REG_CAL_EN field. + RTC_CNTL_RTC_DIG_REG_CAL_EN_Pos = 0x7 + // Bit mask of DIG_REG_CAL_EN field. + RTC_CNTL_RTC_DIG_REG_CAL_EN_Msk = 0x80 + // Bit DIG_REG_CAL_EN. + RTC_CNTL_RTC_DIG_REG_CAL_EN = 0x80 + // Position of SCK_DCAP field. + RTC_CNTL_RTC_SCK_DCAP_Pos = 0xe + // Bit mask of SCK_DCAP field. + RTC_CNTL_RTC_SCK_DCAP_Msk = 0x3fc000 + // Position of DBOOST_FORCE_PD field. + RTC_CNTL_RTC_DBOOST_FORCE_PD_Pos = 0x1c + // Bit mask of DBOOST_FORCE_PD field. + RTC_CNTL_RTC_DBOOST_FORCE_PD_Msk = 0x10000000 + // Bit DBOOST_FORCE_PD. + RTC_CNTL_RTC_DBOOST_FORCE_PD = 0x10000000 + // Position of DBOOST_FORCE_PU field. + RTC_CNTL_RTC_DBOOST_FORCE_PU_Pos = 0x1d + // Bit mask of DBOOST_FORCE_PU field. + RTC_CNTL_RTC_DBOOST_FORCE_PU_Msk = 0x20000000 + // Bit DBOOST_FORCE_PU. + RTC_CNTL_RTC_DBOOST_FORCE_PU = 0x20000000 + // Position of REGULATOR_FORCE_PD field. + RTC_CNTL_RTC_REGULATOR_FORCE_PD_Pos = 0x1e + // Bit mask of REGULATOR_FORCE_PD field. + RTC_CNTL_RTC_REGULATOR_FORCE_PD_Msk = 0x40000000 + // Bit REGULATOR_FORCE_PD. + RTC_CNTL_RTC_REGULATOR_FORCE_PD = 0x40000000 + // Position of REGULATOR_FORCE_PU field. + RTC_CNTL_RTC_REGULATOR_FORCE_PU_Pos = 0x1f + // Bit mask of REGULATOR_FORCE_PU field. + RTC_CNTL_RTC_REGULATOR_FORCE_PU_Msk = 0x80000000 + // Bit REGULATOR_FORCE_PU. + RTC_CNTL_RTC_REGULATOR_FORCE_PU = 0x80000000 + + // PWC: configure rtc power + // Position of FASTMEM_FORCE_NOISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_NOISO_Pos = 0x0 + // Bit mask of FASTMEM_FORCE_NOISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_NOISO_Msk = 0x1 + // Bit FASTMEM_FORCE_NOISO. + RTC_CNTL_PWC_FASTMEM_FORCE_NOISO = 0x1 + // Position of FASTMEM_FORCE_ISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_ISO_Pos = 0x1 + // Bit mask of FASTMEM_FORCE_ISO field. + RTC_CNTL_PWC_FASTMEM_FORCE_ISO_Msk = 0x2 + // Bit FASTMEM_FORCE_ISO. + RTC_CNTL_PWC_FASTMEM_FORCE_ISO = 0x2 + // Position of SLOWMEM_FORCE_NOISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_NOISO_Pos = 0x2 + // Bit mask of SLOWMEM_FORCE_NOISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_NOISO_Msk = 0x4 + // Bit SLOWMEM_FORCE_NOISO. + RTC_CNTL_PWC_SLOWMEM_FORCE_NOISO = 0x4 + // Position of SLOWMEM_FORCE_ISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_ISO_Pos = 0x3 + // Bit mask of SLOWMEM_FORCE_ISO field. + RTC_CNTL_PWC_SLOWMEM_FORCE_ISO_Msk = 0x8 + // Bit SLOWMEM_FORCE_ISO. + RTC_CNTL_PWC_SLOWMEM_FORCE_ISO = 0x8 + // Position of FORCE_ISO field. + RTC_CNTL_PWC_FORCE_ISO_Pos = 0x4 + // Bit mask of FORCE_ISO field. + RTC_CNTL_PWC_FORCE_ISO_Msk = 0x10 + // Bit FORCE_ISO. + RTC_CNTL_PWC_FORCE_ISO = 0x10 + // Position of FORCE_NOISO field. + RTC_CNTL_PWC_FORCE_NOISO_Pos = 0x5 + // Bit mask of FORCE_NOISO field. + RTC_CNTL_PWC_FORCE_NOISO_Msk = 0x20 + // Bit FORCE_NOISO. + RTC_CNTL_PWC_FORCE_NOISO = 0x20 + // Position of FASTMEM_FOLW_CPU field. + RTC_CNTL_PWC_FASTMEM_FOLW_CPU_Pos = 0x6 + // Bit mask of FASTMEM_FOLW_CPU field. + RTC_CNTL_PWC_FASTMEM_FOLW_CPU_Msk = 0x40 + // Bit FASTMEM_FOLW_CPU. + RTC_CNTL_PWC_FASTMEM_FOLW_CPU = 0x40 + // Position of FASTMEM_FORCE_LPD field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPD_Pos = 0x7 + // Bit mask of FASTMEM_FORCE_LPD field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPD_Msk = 0x80 + // Bit FASTMEM_FORCE_LPD. + RTC_CNTL_PWC_FASTMEM_FORCE_LPD = 0x80 + // Position of FASTMEM_FORCE_LPU field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPU_Pos = 0x8 + // Bit mask of FASTMEM_FORCE_LPU field. + RTC_CNTL_PWC_FASTMEM_FORCE_LPU_Msk = 0x100 + // Bit FASTMEM_FORCE_LPU. + RTC_CNTL_PWC_FASTMEM_FORCE_LPU = 0x100 + // Position of SLOWMEM_FOLW_CPU field. + RTC_CNTL_PWC_SLOWMEM_FOLW_CPU_Pos = 0x9 + // Bit mask of SLOWMEM_FOLW_CPU field. + RTC_CNTL_PWC_SLOWMEM_FOLW_CPU_Msk = 0x200 + // Bit SLOWMEM_FOLW_CPU. + RTC_CNTL_PWC_SLOWMEM_FOLW_CPU = 0x200 + // Position of SLOWMEM_FORCE_LPD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPD_Pos = 0xa + // Bit mask of SLOWMEM_FORCE_LPD field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPD_Msk = 0x400 + // Bit SLOWMEM_FORCE_LPD. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPD = 0x400 + // Position of SLOWMEM_FORCE_LPU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPU_Pos = 0xb + // Bit mask of SLOWMEM_FORCE_LPU field. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPU_Msk = 0x800 + // Bit SLOWMEM_FORCE_LPU. + RTC_CNTL_PWC_SLOWMEM_FORCE_LPU = 0x800 + // Position of FORCE_PD field. + RTC_CNTL_PWC_FORCE_PD_Pos = 0x12 + // Bit mask of FORCE_PD field. + RTC_CNTL_PWC_FORCE_PD_Msk = 0x40000 + // Bit FORCE_PD. + RTC_CNTL_PWC_FORCE_PD = 0x40000 + // Position of FORCE_PU field. + RTC_CNTL_PWC_FORCE_PU_Pos = 0x13 + // Bit mask of FORCE_PU field. + RTC_CNTL_PWC_FORCE_PU_Msk = 0x80000 + // Bit FORCE_PU. + RTC_CNTL_PWC_FORCE_PU = 0x80000 + // Position of PD_EN field. + RTC_CNTL_PWC_PD_EN_Pos = 0x14 + // Bit mask of PD_EN field. + RTC_CNTL_PWC_PD_EN_Msk = 0x100000 + // Bit PD_EN. + RTC_CNTL_PWC_PD_EN = 0x100000 + // Position of PAD_FORCE_HOLD field. + RTC_CNTL_PWC_PAD_FORCE_HOLD_Pos = 0x15 + // Bit mask of PAD_FORCE_HOLD field. + RTC_CNTL_PWC_PAD_FORCE_HOLD_Msk = 0x200000 + // Bit PAD_FORCE_HOLD. + RTC_CNTL_PWC_PAD_FORCE_HOLD = 0x200000 + + // REGULATOR_DRV_CTRL: No public + // Position of REGULATOR_DRV_B_MONITOR field. + RTC_CNTL_REGULATOR_DRV_CTRL_REGULATOR_DRV_B_MONITOR_Pos = 0x0 + // Bit mask of REGULATOR_DRV_B_MONITOR field. + RTC_CNTL_REGULATOR_DRV_CTRL_REGULATOR_DRV_B_MONITOR_Msk = 0x3f + // Position of REGULATOR_DRV_B_SLP field. + RTC_CNTL_REGULATOR_DRV_CTRL_REGULATOR_DRV_B_SLP_Pos = 0x6 + // Bit mask of REGULATOR_DRV_B_SLP field. + RTC_CNTL_REGULATOR_DRV_CTRL_REGULATOR_DRV_B_SLP_Msk = 0xfc0 + // Position of DG_VDD_DRV_B_SLP field. + RTC_CNTL_REGULATOR_DRV_CTRL_DG_VDD_DRV_B_SLP_Pos = 0xc + // Bit mask of DG_VDD_DRV_B_SLP field. + RTC_CNTL_REGULATOR_DRV_CTRL_DG_VDD_DRV_B_SLP_Msk = 0xff000 + // Position of DG_VDD_DRV_B_MONITOR field. + RTC_CNTL_REGULATOR_DRV_CTRL_DG_VDD_DRV_B_MONITOR_Pos = 0x14 + // Bit mask of DG_VDD_DRV_B_MONITOR field. + RTC_CNTL_REGULATOR_DRV_CTRL_DG_VDD_DRV_B_MONITOR_Msk = 0xff00000 + + // DIG_PWC: configure digital power + // Position of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Pos = 0x3 + // Bit mask of LSLP_MEM_FORCE_PD field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD_Msk = 0x8 + // Bit LSLP_MEM_FORCE_PD. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PD = 0x8 + // Position of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Pos = 0x4 + // Bit mask of LSLP_MEM_FORCE_PU field. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU_Msk = 0x10 + // Bit LSLP_MEM_FORCE_PU. + RTC_CNTL_DIG_PWC_LSLP_MEM_FORCE_PU = 0x10 + // Position of BT_FORCE_PD field. + RTC_CNTL_DIG_PWC_BT_FORCE_PD_Pos = 0xb + // Bit mask of BT_FORCE_PD field. + RTC_CNTL_DIG_PWC_BT_FORCE_PD_Msk = 0x800 + // Bit BT_FORCE_PD. + RTC_CNTL_DIG_PWC_BT_FORCE_PD = 0x800 + // Position of BT_FORCE_PU field. + RTC_CNTL_DIG_PWC_BT_FORCE_PU_Pos = 0xc + // Bit mask of BT_FORCE_PU field. + RTC_CNTL_DIG_PWC_BT_FORCE_PU_Msk = 0x1000 + // Bit BT_FORCE_PU. + RTC_CNTL_DIG_PWC_BT_FORCE_PU = 0x1000 + // Position of DG_PERI_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PD_Pos = 0xd + // Bit mask of DG_PERI_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PD_Msk = 0x2000 + // Bit DG_PERI_FORCE_PD. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PD = 0x2000 + // Position of DG_PERI_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PU_Pos = 0xe + // Bit mask of DG_PERI_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PU_Msk = 0x4000 + // Bit DG_PERI_FORCE_PU. + RTC_CNTL_DIG_PWC_DG_PERI_FORCE_PU = 0x4000 + // Position of WIFI_FORCE_PD field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD_Pos = 0x11 + // Bit mask of WIFI_FORCE_PD field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD_Msk = 0x20000 + // Bit WIFI_FORCE_PD. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PD = 0x20000 + // Position of WIFI_FORCE_PU field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU_Pos = 0x12 + // Bit mask of WIFI_FORCE_PU field. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU_Msk = 0x40000 + // Bit WIFI_FORCE_PU. + RTC_CNTL_DIG_PWC_WIFI_FORCE_PU = 0x40000 + // Position of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Pos = 0x13 + // Bit mask of DG_WRAP_FORCE_PD field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD_Msk = 0x80000 + // Bit DG_WRAP_FORCE_PD. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PD = 0x80000 + // Position of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Pos = 0x14 + // Bit mask of DG_WRAP_FORCE_PU field. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU_Msk = 0x100000 + // Bit DG_WRAP_FORCE_PU. + RTC_CNTL_DIG_PWC_DG_WRAP_FORCE_PU = 0x100000 + // Position of CPU_TOP_FORCE_PD field. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PD_Pos = 0x15 + // Bit mask of CPU_TOP_FORCE_PD field. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PD_Msk = 0x200000 + // Bit CPU_TOP_FORCE_PD. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PD = 0x200000 + // Position of CPU_TOP_FORCE_PU field. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PU_Pos = 0x16 + // Bit mask of CPU_TOP_FORCE_PU field. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PU_Msk = 0x400000 + // Bit CPU_TOP_FORCE_PU. + RTC_CNTL_DIG_PWC_CPU_TOP_FORCE_PU = 0x400000 + // Position of BT_PD_EN field. + RTC_CNTL_DIG_PWC_BT_PD_EN_Pos = 0x1b + // Bit mask of BT_PD_EN field. + RTC_CNTL_DIG_PWC_BT_PD_EN_Msk = 0x8000000 + // Bit BT_PD_EN. + RTC_CNTL_DIG_PWC_BT_PD_EN = 0x8000000 + // Position of DG_PERI_PD_EN field. + RTC_CNTL_DIG_PWC_DG_PERI_PD_EN_Pos = 0x1c + // Bit mask of DG_PERI_PD_EN field. + RTC_CNTL_DIG_PWC_DG_PERI_PD_EN_Msk = 0x10000000 + // Bit DG_PERI_PD_EN. + RTC_CNTL_DIG_PWC_DG_PERI_PD_EN = 0x10000000 + // Position of CPU_TOP_PD_EN field. + RTC_CNTL_DIG_PWC_CPU_TOP_PD_EN_Pos = 0x1d + // Bit mask of CPU_TOP_PD_EN field. + RTC_CNTL_DIG_PWC_CPU_TOP_PD_EN_Msk = 0x20000000 + // Bit CPU_TOP_PD_EN. + RTC_CNTL_DIG_PWC_CPU_TOP_PD_EN = 0x20000000 + // Position of WIFI_PD_EN field. + RTC_CNTL_DIG_PWC_WIFI_PD_EN_Pos = 0x1e + // Bit mask of WIFI_PD_EN field. + RTC_CNTL_DIG_PWC_WIFI_PD_EN_Msk = 0x40000000 + // Bit WIFI_PD_EN. + RTC_CNTL_DIG_PWC_WIFI_PD_EN = 0x40000000 + // Position of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Pos = 0x1f + // Bit mask of DG_WRAP_PD_EN field. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN_Msk = 0x80000000 + // Bit DG_WRAP_PD_EN. + RTC_CNTL_DIG_PWC_DG_WRAP_PD_EN = 0x80000000 + + // DIG_ISO: congigure digital power isolation + // Position of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Pos = 0x7 + // Bit mask of FORCE_OFF field. + RTC_CNTL_DIG_ISO_FORCE_OFF_Msk = 0x80 + // Bit FORCE_OFF. + RTC_CNTL_DIG_ISO_FORCE_OFF = 0x80 + // Position of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Pos = 0x8 + // Bit mask of FORCE_ON field. + RTC_CNTL_DIG_ISO_FORCE_ON_Msk = 0x100 + // Bit FORCE_ON. + RTC_CNTL_DIG_ISO_FORCE_ON = 0x100 + // Position of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Pos = 0x9 + // Bit mask of DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_Msk = 0x200 + // Bit DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD = 0x200 + // Position of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Pos = 0xa + // Bit mask of CLR_DG_PAD_AUTOHOLD field. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD_Msk = 0x400 + // Bit CLR_DG_PAD_AUTOHOLD. + RTC_CNTL_DIG_ISO_CLR_DG_PAD_AUTOHOLD = 0x400 + // Position of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Pos = 0xb + // Bit mask of DG_PAD_AUTOHOLD_EN field. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN_Msk = 0x800 + // Bit DG_PAD_AUTOHOLD_EN. + RTC_CNTL_DIG_ISO_DG_PAD_AUTOHOLD_EN = 0x800 + // Position of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Pos = 0xc + // Bit mask of DG_PAD_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO_Msk = 0x1000 + // Bit DG_PAD_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_NOISO = 0x1000 + // Position of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Pos = 0xd + // Bit mask of DG_PAD_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO_Msk = 0x2000 + // Bit DG_PAD_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_ISO = 0x2000 + // Position of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Pos = 0xe + // Bit mask of DG_PAD_FORCE_UNHOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD_Msk = 0x4000 + // Bit DG_PAD_FORCE_UNHOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_UNHOLD = 0x4000 + // Position of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Pos = 0xf + // Bit mask of DG_PAD_FORCE_HOLD field. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD_Msk = 0x8000 + // Bit DG_PAD_FORCE_HOLD. + RTC_CNTL_DIG_ISO_DG_PAD_FORCE_HOLD = 0x8000 + // Position of BT_FORCE_ISO field. + RTC_CNTL_DIG_ISO_BT_FORCE_ISO_Pos = 0x16 + // Bit mask of BT_FORCE_ISO field. + RTC_CNTL_DIG_ISO_BT_FORCE_ISO_Msk = 0x400000 + // Bit BT_FORCE_ISO. + RTC_CNTL_DIG_ISO_BT_FORCE_ISO = 0x400000 + // Position of BT_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_BT_FORCE_NOISO_Pos = 0x17 + // Bit mask of BT_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_BT_FORCE_NOISO_Msk = 0x800000 + // Bit BT_FORCE_NOISO. + RTC_CNTL_DIG_ISO_BT_FORCE_NOISO = 0x800000 + // Position of DG_PERI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_ISO_Pos = 0x18 + // Bit mask of DG_PERI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_ISO_Msk = 0x1000000 + // Bit DG_PERI_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_ISO = 0x1000000 + // Position of DG_PERI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_NOISO_Pos = 0x19 + // Bit mask of DG_PERI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_NOISO_Msk = 0x2000000 + // Bit DG_PERI_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_PERI_FORCE_NOISO = 0x2000000 + // Position of CPU_TOP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_ISO_Pos = 0x1a + // Bit mask of CPU_TOP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_ISO_Msk = 0x4000000 + // Bit CPU_TOP_FORCE_ISO. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_ISO = 0x4000000 + // Position of CPU_TOP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_NOISO_Pos = 0x1b + // Bit mask of CPU_TOP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_NOISO_Msk = 0x8000000 + // Bit CPU_TOP_FORCE_NOISO. + RTC_CNTL_DIG_ISO_CPU_TOP_FORCE_NOISO = 0x8000000 + // Position of WIFI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO_Pos = 0x1c + // Bit mask of WIFI_FORCE_ISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO_Msk = 0x10000000 + // Bit WIFI_FORCE_ISO. + RTC_CNTL_DIG_ISO_WIFI_FORCE_ISO = 0x10000000 + // Position of WIFI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO_Pos = 0x1d + // Bit mask of WIFI_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO_Msk = 0x20000000 + // Bit WIFI_FORCE_NOISO. + RTC_CNTL_DIG_ISO_WIFI_FORCE_NOISO = 0x20000000 + // Position of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Pos = 0x1e + // Bit mask of DG_WRAP_FORCE_ISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO_Msk = 0x40000000 + // Bit DG_WRAP_FORCE_ISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_ISO = 0x40000000 + // Position of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Pos = 0x1f + // Bit mask of DG_WRAP_FORCE_NOISO field. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO_Msk = 0x80000000 + // Bit DG_WRAP_FORCE_NOISO. + RTC_CNTL_DIG_ISO_DG_WRAP_FORCE_NOISO = 0x80000000 + + // WDTCONFIG0: configure rtc watch dog + // Position of WDT_CHIP_RESET_WIDTH field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Pos = 0x0 + // Bit mask of WDT_CHIP_RESET_WIDTH field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_WIDTH_Msk = 0xff + // Position of WDT_CHIP_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN_Pos = 0x8 + // Bit mask of WDT_CHIP_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN_Msk = 0x100 + // Bit WDT_CHIP_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_CHIP_RESET_EN = 0x100 + // Position of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Pos = 0x9 + // Bit mask of WDT_PAUSE_IN_SLP field. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP_Msk = 0x200 + // Bit WDT_PAUSE_IN_SLP. + RTC_CNTL_WDTCONFIG0_WDT_PAUSE_IN_SLP = 0x200 + // Position of WDT_APPCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xa + // Bit mask of WDT_APPCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x400 + // Bit WDT_APPCPU_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x400 + // Position of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xb + // Bit mask of WDT_PROCPU_RESET_EN field. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x800 + // Bit WDT_PROCPU_RESET_EN. + RTC_CNTL_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x800 + // Position of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xc + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x1000 + // Bit WDT_FLASHBOOT_MOD_EN. + RTC_CNTL_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x1000 + // Position of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xd + // Bit mask of WDT_SYS_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0xe000 + // Position of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x10 + // Bit mask of WDT_CPU_RESET_LENGTH field. + RTC_CNTL_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x70000 + // Position of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Pos = 0x13 + // Bit mask of WDT_STG3 field. + RTC_CNTL_WDTCONFIG0_WDT_STG3_Msk = 0x380000 + // Position of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Pos = 0x16 + // Bit mask of WDT_STG2 field. + RTC_CNTL_WDTCONFIG0_WDT_STG2_Msk = 0x1c00000 + // Position of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Pos = 0x19 + // Bit mask of WDT_STG1 field. + RTC_CNTL_WDTCONFIG0_WDT_STG1_Msk = 0xe000000 + // Position of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Pos = 0x1c + // Bit mask of WDT_STG0 field. + RTC_CNTL_WDTCONFIG0_WDT_STG0_Msk = 0x70000000 + // Position of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + RTC_CNTL_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + RTC_CNTL_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: stage0 hold time + // Position of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + RTC_CNTL_WDTCONFIG1_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG2: stage1 hold time + // Position of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + RTC_CNTL_WDTCONFIG2_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: stage2 hold time + // Position of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + RTC_CNTL_WDTCONFIG3_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: stage3 hold time + // Position of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + RTC_CNTL_WDTCONFIG4_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: rtc wdt feed + // Position of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Pos = 0x1f + // Bit mask of WDT_FEED field. + RTC_CNTL_WDTFEED_WDT_FEED_Msk = 0x80000000 + // Bit WDT_FEED. + RTC_CNTL_WDTFEED_WDT_FEED = 0x80000000 + + // WDTWPROTECT: configure rtc watch dog + // Position of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + RTC_CNTL_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // SWD_CONF: congfigure super watch dog + // Position of SWD_RESET_FLAG field. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG_Pos = 0x0 + // Bit mask of SWD_RESET_FLAG field. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG_Msk = 0x1 + // Bit SWD_RESET_FLAG. + RTC_CNTL_SWD_CONF_SWD_RESET_FLAG = 0x1 + // Position of SWD_FEED_INT field. + RTC_CNTL_SWD_CONF_SWD_FEED_INT_Pos = 0x1 + // Bit mask of SWD_FEED_INT field. + RTC_CNTL_SWD_CONF_SWD_FEED_INT_Msk = 0x2 + // Bit SWD_FEED_INT. + RTC_CNTL_SWD_CONF_SWD_FEED_INT = 0x2 + // Position of SWD_BYPASS_RST field. + RTC_CNTL_SWD_CONF_SWD_BYPASS_RST_Pos = 0x11 + // Bit mask of SWD_BYPASS_RST field. + RTC_CNTL_SWD_CONF_SWD_BYPASS_RST_Msk = 0x20000 + // Bit SWD_BYPASS_RST. + RTC_CNTL_SWD_CONF_SWD_BYPASS_RST = 0x20000 + // Position of SWD_SIGNAL_WIDTH field. + RTC_CNTL_SWD_CONF_SWD_SIGNAL_WIDTH_Pos = 0x12 + // Bit mask of SWD_SIGNAL_WIDTH field. + RTC_CNTL_SWD_CONF_SWD_SIGNAL_WIDTH_Msk = 0xffc0000 + // Position of SWD_RST_FLAG_CLR field. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR_Pos = 0x1c + // Bit mask of SWD_RST_FLAG_CLR field. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR_Msk = 0x10000000 + // Bit SWD_RST_FLAG_CLR. + RTC_CNTL_SWD_CONF_SWD_RST_FLAG_CLR = 0x10000000 + // Position of SWD_FEED field. + RTC_CNTL_SWD_CONF_SWD_FEED_Pos = 0x1d + // Bit mask of SWD_FEED field. + RTC_CNTL_SWD_CONF_SWD_FEED_Msk = 0x20000000 + // Bit SWD_FEED. + RTC_CNTL_SWD_CONF_SWD_FEED = 0x20000000 + // Position of SWD_DISABLE field. + RTC_CNTL_SWD_CONF_SWD_DISABLE_Pos = 0x1e + // Bit mask of SWD_DISABLE field. + RTC_CNTL_SWD_CONF_SWD_DISABLE_Msk = 0x40000000 + // Bit SWD_DISABLE. + RTC_CNTL_SWD_CONF_SWD_DISABLE = 0x40000000 + // Position of SWD_AUTO_FEED_EN field. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN_Pos = 0x1f + // Bit mask of SWD_AUTO_FEED_EN field. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN_Msk = 0x80000000 + // Bit SWD_AUTO_FEED_EN. + RTC_CNTL_SWD_CONF_SWD_AUTO_FEED_EN = 0x80000000 + + // SWD_WPROTECT: super watch dog key + // Position of SWD_WKEY field. + RTC_CNTL_SWD_WPROTECT_SWD_WKEY_Pos = 0x0 + // Bit mask of SWD_WKEY field. + RTC_CNTL_SWD_WPROTECT_SWD_WKEY_Msk = 0xffffffff + + // SW_CPU_STALL: configure cpu stall by sw + // Position of SW_STALL_APPCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_APPCPU_C1_Pos = 0x14 + // Bit mask of SW_STALL_APPCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_APPCPU_C1_Msk = 0x3f00000 + // Position of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Pos = 0x1a + // Bit mask of SW_STALL_PROCPU_C1 field. + RTC_CNTL_SW_CPU_STALL_SW_STALL_PROCPU_C1_Msk = 0xfc000000 + + // STORE4: reserved register + // Position of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Pos = 0x0 + // Bit mask of SCRATCH4 field. + RTC_CNTL_STORE4_SCRATCH4_Msk = 0xffffffff + + // STORE5: reserved register + // Position of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Pos = 0x0 + // Bit mask of SCRATCH5 field. + RTC_CNTL_STORE5_SCRATCH5_Msk = 0xffffffff + + // STORE6: reserved register + // Position of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Pos = 0x0 + // Bit mask of SCRATCH6 field. + RTC_CNTL_STORE6_SCRATCH6_Msk = 0xffffffff + + // STORE7: reserved register + // Position of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Pos = 0x0 + // Bit mask of SCRATCH7 field. + RTC_CNTL_STORE7_SCRATCH7_Msk = 0xffffffff + + // LOW_POWER_ST: reserved register + // Position of XPD_ROM0 field. + RTC_CNTL_LOW_POWER_ST_XPD_ROM0_Pos = 0x0 + // Bit mask of XPD_ROM0 field. + RTC_CNTL_LOW_POWER_ST_XPD_ROM0_Msk = 0x1 + // Bit XPD_ROM0. + RTC_CNTL_LOW_POWER_ST_XPD_ROM0 = 0x1 + // Position of XPD_DIG_DCDC field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_DCDC_Pos = 0x2 + // Bit mask of XPD_DIG_DCDC field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_DCDC_Msk = 0x4 + // Bit XPD_DIG_DCDC. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_DCDC = 0x4 + // Position of PERI_ISO field. + RTC_CNTL_LOW_POWER_ST_PERI_ISO_Pos = 0x3 + // Bit mask of PERI_ISO field. + RTC_CNTL_LOW_POWER_ST_PERI_ISO_Msk = 0x8 + // Bit PERI_ISO. + RTC_CNTL_LOW_POWER_ST_PERI_ISO = 0x8 + // Position of XPD_RTC_PERI field. + RTC_CNTL_LOW_POWER_ST_XPD_RTC_PERI_Pos = 0x4 + // Bit mask of XPD_RTC_PERI field. + RTC_CNTL_LOW_POWER_ST_XPD_RTC_PERI_Msk = 0x10 + // Bit XPD_RTC_PERI. + RTC_CNTL_LOW_POWER_ST_XPD_RTC_PERI = 0x10 + // Position of WIFI_ISO field. + RTC_CNTL_LOW_POWER_ST_WIFI_ISO_Pos = 0x5 + // Bit mask of WIFI_ISO field. + RTC_CNTL_LOW_POWER_ST_WIFI_ISO_Msk = 0x20 + // Bit WIFI_ISO. + RTC_CNTL_LOW_POWER_ST_WIFI_ISO = 0x20 + // Position of XPD_WIFI field. + RTC_CNTL_LOW_POWER_ST_XPD_WIFI_Pos = 0x6 + // Bit mask of XPD_WIFI field. + RTC_CNTL_LOW_POWER_ST_XPD_WIFI_Msk = 0x40 + // Bit XPD_WIFI. + RTC_CNTL_LOW_POWER_ST_XPD_WIFI = 0x40 + // Position of DIG_ISO field. + RTC_CNTL_LOW_POWER_ST_DIG_ISO_Pos = 0x7 + // Bit mask of DIG_ISO field. + RTC_CNTL_LOW_POWER_ST_DIG_ISO_Msk = 0x80 + // Bit DIG_ISO. + RTC_CNTL_LOW_POWER_ST_DIG_ISO = 0x80 + // Position of XPD_DIG field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_Pos = 0x8 + // Bit mask of XPD_DIG field. + RTC_CNTL_LOW_POWER_ST_XPD_DIG_Msk = 0x100 + // Bit XPD_DIG. + RTC_CNTL_LOW_POWER_ST_XPD_DIG = 0x100 + // Position of TOUCH_STATE_START field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START_Pos = 0x9 + // Bit mask of TOUCH_STATE_START field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START_Msk = 0x200 + // Bit TOUCH_STATE_START. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_START = 0x200 + // Position of TOUCH_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH_Pos = 0xa + // Bit mask of TOUCH_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH_Msk = 0x400 + // Bit TOUCH_STATE_SWITCH. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SWITCH = 0x400 + // Position of TOUCH_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP_Pos = 0xb + // Bit mask of TOUCH_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP_Msk = 0x800 + // Bit TOUCH_STATE_SLP. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_SLP = 0x800 + // Position of TOUCH_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE_Pos = 0xc + // Bit mask of TOUCH_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE_Msk = 0x1000 + // Bit TOUCH_STATE_DONE. + RTC_CNTL_LOW_POWER_ST_TOUCH_STATE_DONE = 0x1000 + // Position of COCPU_STATE_START field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START_Pos = 0xd + // Bit mask of COCPU_STATE_START field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START_Msk = 0x2000 + // Bit COCPU_STATE_START. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_START = 0x2000 + // Position of COCPU_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH_Pos = 0xe + // Bit mask of COCPU_STATE_SWITCH field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH_Msk = 0x4000 + // Bit COCPU_STATE_SWITCH. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SWITCH = 0x4000 + // Position of COCPU_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP_Pos = 0xf + // Bit mask of COCPU_STATE_SLP field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP_Msk = 0x8000 + // Bit COCPU_STATE_SLP. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_SLP = 0x8000 + // Position of COCPU_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE_Pos = 0x10 + // Bit mask of COCPU_STATE_DONE field. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE_Msk = 0x10000 + // Bit COCPU_STATE_DONE. + RTC_CNTL_LOW_POWER_ST_COCPU_STATE_DONE = 0x10000 + // Position of MAIN_STATE_XTAL_ISO field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO_Pos = 0x11 + // Bit mask of MAIN_STATE_XTAL_ISO field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO_Msk = 0x20000 + // Bit MAIN_STATE_XTAL_ISO. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_XTAL_ISO = 0x20000 + // Position of MAIN_STATE_PLL_ON field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON_Pos = 0x12 + // Bit mask of MAIN_STATE_PLL_ON field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON_Msk = 0x40000 + // Bit MAIN_STATE_PLL_ON. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_PLL_ON = 0x40000 + // Position of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Pos = 0x13 + // Bit mask of RDY_FOR_WAKEUP field. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP_Msk = 0x80000 + // Bit RDY_FOR_WAKEUP. + RTC_CNTL_LOW_POWER_ST_RDY_FOR_WAKEUP = 0x80000 + // Position of MAIN_STATE_WAIT_END field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END_Pos = 0x14 + // Bit mask of MAIN_STATE_WAIT_END field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END_Msk = 0x100000 + // Bit MAIN_STATE_WAIT_END. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_WAIT_END = 0x100000 + // Position of IN_WAKEUP_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE_Pos = 0x15 + // Bit mask of IN_WAKEUP_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE_Msk = 0x200000 + // Bit IN_WAKEUP_STATE. + RTC_CNTL_LOW_POWER_ST_IN_WAKEUP_STATE = 0x200000 + // Position of IN_LOW_POWER_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE_Pos = 0x16 + // Bit mask of IN_LOW_POWER_STATE field. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE_Msk = 0x400000 + // Bit IN_LOW_POWER_STATE. + RTC_CNTL_LOW_POWER_ST_IN_LOW_POWER_STATE = 0x400000 + // Position of MAIN_STATE_IN_WAIT_8M field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M_Pos = 0x17 + // Bit mask of MAIN_STATE_IN_WAIT_8M field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M_Msk = 0x800000 + // Bit MAIN_STATE_IN_WAIT_8M. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_8M = 0x800000 + // Position of MAIN_STATE_IN_WAIT_PLL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL_Pos = 0x18 + // Bit mask of MAIN_STATE_IN_WAIT_PLL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL_Msk = 0x1000000 + // Bit MAIN_STATE_IN_WAIT_PLL. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_PLL = 0x1000000 + // Position of MAIN_STATE_IN_WAIT_XTL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL_Pos = 0x19 + // Bit mask of MAIN_STATE_IN_WAIT_XTL field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL_Msk = 0x2000000 + // Bit MAIN_STATE_IN_WAIT_XTL. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_WAIT_XTL = 0x2000000 + // Position of MAIN_STATE_IN_SLP field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP_Pos = 0x1a + // Bit mask of MAIN_STATE_IN_SLP field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP_Msk = 0x4000000 + // Bit MAIN_STATE_IN_SLP. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_SLP = 0x4000000 + // Position of MAIN_STATE_IN_IDLE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE_Pos = 0x1b + // Bit mask of MAIN_STATE_IN_IDLE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE_Msk = 0x8000000 + // Bit MAIN_STATE_IN_IDLE. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_IN_IDLE = 0x8000000 + // Position of MAIN_STATE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_Pos = 0x1c + // Bit mask of MAIN_STATE field. + RTC_CNTL_LOW_POWER_ST_MAIN_STATE_Msk = 0xf0000000 + + // DIAG0: No public + // Position of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG0_LOW_POWER_DIAG1_Pos = 0x0 + // Bit mask of LOW_POWER_DIAG1 field. + RTC_CNTL_DIAG0_LOW_POWER_DIAG1_Msk = 0xffffffff + + // PAD_HOLD: rtc pad hold configure + // Position of TOUCH_PAD0_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD0_HOLD_Pos = 0x0 + // Bit mask of TOUCH_PAD0_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD0_HOLD_Msk = 0x1 + // Bit TOUCH_PAD0_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD0_HOLD = 0x1 + // Position of TOUCH_PAD1_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD1_HOLD_Pos = 0x1 + // Bit mask of TOUCH_PAD1_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD1_HOLD_Msk = 0x2 + // Bit TOUCH_PAD1_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD1_HOLD = 0x2 + // Position of TOUCH_PAD2_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD2_HOLD_Pos = 0x2 + // Bit mask of TOUCH_PAD2_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD2_HOLD_Msk = 0x4 + // Bit TOUCH_PAD2_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD2_HOLD = 0x4 + // Position of TOUCH_PAD3_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD3_HOLD_Pos = 0x3 + // Bit mask of TOUCH_PAD3_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD3_HOLD_Msk = 0x8 + // Bit TOUCH_PAD3_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD3_HOLD = 0x8 + // Position of TOUCH_PAD4_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD4_HOLD_Pos = 0x4 + // Bit mask of TOUCH_PAD4_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD4_HOLD_Msk = 0x10 + // Bit TOUCH_PAD4_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD4_HOLD = 0x10 + // Position of TOUCH_PAD5_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD5_HOLD_Pos = 0x5 + // Bit mask of TOUCH_PAD5_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD5_HOLD_Msk = 0x20 + // Bit TOUCH_PAD5_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD5_HOLD = 0x20 + // Position of TOUCH_PAD6_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD6_HOLD_Pos = 0x6 + // Bit mask of TOUCH_PAD6_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD6_HOLD_Msk = 0x40 + // Bit TOUCH_PAD6_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD6_HOLD = 0x40 + // Position of TOUCH_PAD7_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD7_HOLD_Pos = 0x7 + // Bit mask of TOUCH_PAD7_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD7_HOLD_Msk = 0x80 + // Bit TOUCH_PAD7_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD7_HOLD = 0x80 + // Position of TOUCH_PAD8_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD8_HOLD_Pos = 0x8 + // Bit mask of TOUCH_PAD8_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD8_HOLD_Msk = 0x100 + // Bit TOUCH_PAD8_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD8_HOLD = 0x100 + // Position of TOUCH_PAD9_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD9_HOLD_Pos = 0x9 + // Bit mask of TOUCH_PAD9_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD9_HOLD_Msk = 0x200 + // Bit TOUCH_PAD9_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD9_HOLD = 0x200 + // Position of TOUCH_PAD10_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD10_HOLD_Pos = 0xa + // Bit mask of TOUCH_PAD10_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD10_HOLD_Msk = 0x400 + // Bit TOUCH_PAD10_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD10_HOLD = 0x400 + // Position of TOUCH_PAD11_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD11_HOLD_Pos = 0xb + // Bit mask of TOUCH_PAD11_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD11_HOLD_Msk = 0x800 + // Bit TOUCH_PAD11_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD11_HOLD = 0x800 + // Position of TOUCH_PAD12_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD12_HOLD_Pos = 0xc + // Bit mask of TOUCH_PAD12_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD12_HOLD_Msk = 0x1000 + // Bit TOUCH_PAD12_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD12_HOLD = 0x1000 + // Position of TOUCH_PAD13_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD13_HOLD_Pos = 0xd + // Bit mask of TOUCH_PAD13_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD13_HOLD_Msk = 0x2000 + // Bit TOUCH_PAD13_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD13_HOLD = 0x2000 + // Position of TOUCH_PAD14_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD14_HOLD_Pos = 0xe + // Bit mask of TOUCH_PAD14_HOLD field. + RTC_CNTL_PAD_HOLD_TOUCH_PAD14_HOLD_Msk = 0x4000 + // Bit TOUCH_PAD14_HOLD. + RTC_CNTL_PAD_HOLD_TOUCH_PAD14_HOLD = 0x4000 + // Position of X32P_HOLD field. + RTC_CNTL_PAD_HOLD_X32P_HOLD_Pos = 0xf + // Bit mask of X32P_HOLD field. + RTC_CNTL_PAD_HOLD_X32P_HOLD_Msk = 0x8000 + // Bit X32P_HOLD. + RTC_CNTL_PAD_HOLD_X32P_HOLD = 0x8000 + // Position of X32N_HOLD field. + RTC_CNTL_PAD_HOLD_X32N_HOLD_Pos = 0x10 + // Bit mask of X32N_HOLD field. + RTC_CNTL_PAD_HOLD_X32N_HOLD_Msk = 0x10000 + // Bit X32N_HOLD. + RTC_CNTL_PAD_HOLD_X32N_HOLD = 0x10000 + // Position of PDAC1_HOLD field. + RTC_CNTL_PAD_HOLD_PDAC1_HOLD_Pos = 0x11 + // Bit mask of PDAC1_HOLD field. + RTC_CNTL_PAD_HOLD_PDAC1_HOLD_Msk = 0x20000 + // Bit PDAC1_HOLD. + RTC_CNTL_PAD_HOLD_PDAC1_HOLD = 0x20000 + // Position of PDAC2_HOLD field. + RTC_CNTL_PAD_HOLD_PDAC2_HOLD_Pos = 0x12 + // Bit mask of PDAC2_HOLD field. + RTC_CNTL_PAD_HOLD_PDAC2_HOLD_Msk = 0x40000 + // Bit PDAC2_HOLD. + RTC_CNTL_PAD_HOLD_PDAC2_HOLD = 0x40000 + // Position of PAD19_HOLD field. + RTC_CNTL_PAD_HOLD_PAD19_HOLD_Pos = 0x13 + // Bit mask of PAD19_HOLD field. + RTC_CNTL_PAD_HOLD_PAD19_HOLD_Msk = 0x80000 + // Bit PAD19_HOLD. + RTC_CNTL_PAD_HOLD_PAD19_HOLD = 0x80000 + // Position of PAD20_HOLD field. + RTC_CNTL_PAD_HOLD_PAD20_HOLD_Pos = 0x14 + // Bit mask of PAD20_HOLD field. + RTC_CNTL_PAD_HOLD_PAD20_HOLD_Msk = 0x100000 + // Bit PAD20_HOLD. + RTC_CNTL_PAD_HOLD_PAD20_HOLD = 0x100000 + // Position of PAD21_HOLD field. + RTC_CNTL_PAD_HOLD_PAD21_HOLD_Pos = 0x15 + // Bit mask of PAD21_HOLD field. + RTC_CNTL_PAD_HOLD_PAD21_HOLD_Msk = 0x200000 + // Bit PAD21_HOLD. + RTC_CNTL_PAD_HOLD_PAD21_HOLD = 0x200000 + + // DIG_PAD_HOLD: configure digtal pad hold + // Position of DIG_PAD_HOLD field. + RTC_CNTL_DIG_PAD_HOLD_DIG_PAD_HOLD_Pos = 0x0 + // Bit mask of DIG_PAD_HOLD field. + RTC_CNTL_DIG_PAD_HOLD_DIG_PAD_HOLD_Msk = 0xffffffff + + // EXT_WAKEUP1: configure ext1 wakeup + // Position of EXT_WAKEUP1_SEL field. + RTC_CNTL_EXT_WAKEUP1_EXT_WAKEUP1_SEL_Pos = 0x0 + // Bit mask of EXT_WAKEUP1_SEL field. + RTC_CNTL_EXT_WAKEUP1_EXT_WAKEUP1_SEL_Msk = 0x3fffff + // Position of EXT_WAKEUP1_STATUS_CLR field. + RTC_CNTL_EXT_WAKEUP1_EXT_WAKEUP1_STATUS_CLR_Pos = 0x16 + // Bit mask of EXT_WAKEUP1_STATUS_CLR field. + RTC_CNTL_EXT_WAKEUP1_EXT_WAKEUP1_STATUS_CLR_Msk = 0x400000 + // Bit EXT_WAKEUP1_STATUS_CLR. + RTC_CNTL_EXT_WAKEUP1_EXT_WAKEUP1_STATUS_CLR = 0x400000 + + // EXT_WAKEUP1_STATUS: check ext wakeup1 status + // Position of EXT_WAKEUP1_STATUS field. + RTC_CNTL_EXT_WAKEUP1_STATUS_EXT_WAKEUP1_STATUS_Pos = 0x0 + // Bit mask of EXT_WAKEUP1_STATUS field. + RTC_CNTL_EXT_WAKEUP1_STATUS_EXT_WAKEUP1_STATUS_Msk = 0x3fffff + + // BROWN_OUT: congfigure brownout + // Position of BROWN_OUT_INT_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_INT_WAIT_Pos = 0x4 + // Bit mask of BROWN_OUT_INT_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_INT_WAIT_Msk = 0x3ff0 + // Position of BROWN_OUT_CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA_Pos = 0xe + // Bit mask of BROWN_OUT_CLOSE_FLASH_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA_Msk = 0x4000 + // Bit BROWN_OUT_CLOSE_FLASH_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CLOSE_FLASH_ENA = 0x4000 + // Position of BROWN_OUT_PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_PD_RF_ENA_Pos = 0xf + // Bit mask of BROWN_OUT_PD_RF_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_PD_RF_ENA_Msk = 0x8000 + // Bit BROWN_OUT_PD_RF_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_PD_RF_ENA = 0x8000 + // Position of BROWN_OUT_RST_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_WAIT_Pos = 0x10 + // Bit mask of BROWN_OUT_RST_WAIT field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_WAIT_Msk = 0x3ff0000 + // Position of BROWN_OUT_RST_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_ENA_Pos = 0x1a + // Bit mask of BROWN_OUT_RST_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_ENA_Msk = 0x4000000 + // Bit BROWN_OUT_RST_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_ENA = 0x4000000 + // Position of BROWN_OUT_RST_SEL field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_SEL_Pos = 0x1b + // Bit mask of BROWN_OUT_RST_SEL field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_SEL_Msk = 0x8000000 + // Bit BROWN_OUT_RST_SEL. + RTC_CNTL_BROWN_OUT_BROWN_OUT_RST_SEL = 0x8000000 + // Position of BROWN_OUT_ANA_RST_EN field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ANA_RST_EN_Pos = 0x1c + // Bit mask of BROWN_OUT_ANA_RST_EN field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ANA_RST_EN_Msk = 0x10000000 + // Bit BROWN_OUT_ANA_RST_EN. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ANA_RST_EN = 0x10000000 + // Position of BROWN_OUT_CNT_CLR field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CNT_CLR_Pos = 0x1d + // Bit mask of BROWN_OUT_CNT_CLR field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CNT_CLR_Msk = 0x20000000 + // Bit BROWN_OUT_CNT_CLR. + RTC_CNTL_BROWN_OUT_BROWN_OUT_CNT_CLR = 0x20000000 + // Position of BROWN_OUT_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ENA_Pos = 0x1e + // Bit mask of BROWN_OUT_ENA field. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ENA_Msk = 0x40000000 + // Bit BROWN_OUT_ENA. + RTC_CNTL_BROWN_OUT_BROWN_OUT_ENA = 0x40000000 + // Position of DET field. + RTC_CNTL_BROWN_OUT_DET_Pos = 0x1f + // Bit mask of DET field. + RTC_CNTL_BROWN_OUT_DET_Msk = 0x80000000 + // Bit DET. + RTC_CNTL_BROWN_OUT_DET = 0x80000000 + + // TIME_LOW1: RTC timer low 32 bits + // Position of TIMER_VALUE1_LOW field. + RTC_CNTL_TIME_LOW1_TIMER_VALUE1_LOW_Pos = 0x0 + // Bit mask of TIMER_VALUE1_LOW field. + RTC_CNTL_TIME_LOW1_TIMER_VALUE1_LOW_Msk = 0xffffffff + + // TIME_HIGH1: RTC timer high 16 bits + // Position of TIMER_VALUE1_HIGH field. + RTC_CNTL_TIME_HIGH1_TIMER_VALUE1_HIGH_Pos = 0x0 + // Bit mask of TIMER_VALUE1_HIGH field. + RTC_CNTL_TIME_HIGH1_TIMER_VALUE1_HIGH_Msk = 0xffff + + // XTAL32K_CLK_FACTOR: xtal 32k watch dog backup clock factor + // Position of XTAL32K_CLK_FACTOR field. + RTC_CNTL_XTAL32K_CLK_FACTOR_XTAL32K_CLK_FACTOR_Pos = 0x0 + // Bit mask of XTAL32K_CLK_FACTOR field. + RTC_CNTL_XTAL32K_CLK_FACTOR_XTAL32K_CLK_FACTOR_Msk = 0xffffffff + + // XTAL32K_CONF: configure xtal32k + // Position of XTAL32K_RETURN_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RETURN_WAIT_Pos = 0x0 + // Bit mask of XTAL32K_RETURN_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RETURN_WAIT_Msk = 0xf + // Position of XTAL32K_RESTART_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RESTART_WAIT_Pos = 0x4 + // Bit mask of XTAL32K_RESTART_WAIT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_RESTART_WAIT_Msk = 0xffff0 + // Position of XTAL32K_WDT_TIMEOUT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_WDT_TIMEOUT_Pos = 0x14 + // Bit mask of XTAL32K_WDT_TIMEOUT field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_WDT_TIMEOUT_Msk = 0xff00000 + // Position of XTAL32K_STABLE_THRES field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_STABLE_THRES_Pos = 0x1c + // Bit mask of XTAL32K_STABLE_THRES field. + RTC_CNTL_XTAL32K_CONF_XTAL32K_STABLE_THRES_Msk = 0xf0000000 + + // ULP_CP_TIMER: configure ulp + // Position of ULP_CP_PC_INIT field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_PC_INIT_Pos = 0x0 + // Bit mask of ULP_CP_PC_INIT field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_PC_INIT_Msk = 0x7ff + // Position of ULP_CP_GPIO_WAKEUP_ENA field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA_Pos = 0x1d + // Bit mask of ULP_CP_GPIO_WAKEUP_ENA field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA_Msk = 0x20000000 + // Bit ULP_CP_GPIO_WAKEUP_ENA. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA = 0x20000000 + // Position of ULP_CP_GPIO_WAKEUP_CLR field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR_Pos = 0x1e + // Bit mask of ULP_CP_GPIO_WAKEUP_CLR field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR_Msk = 0x40000000 + // Bit ULP_CP_GPIO_WAKEUP_CLR. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR = 0x40000000 + // Position of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN_Pos = 0x1f + // Bit mask of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN_Msk = 0x80000000 + // Bit ULP_CP_SLP_TIMER_EN. + RTC_CNTL_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN = 0x80000000 + + // ULP_CP_CTRL: configure ulp + // Position of ULP_CP_MEM_ADDR_INIT field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT_Pos = 0x0 + // Bit mask of ULP_CP_MEM_ADDR_INIT field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT_Msk = 0x7ff + // Position of ULP_CP_MEM_ADDR_SIZE field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE_Pos = 0xb + // Bit mask of ULP_CP_MEM_ADDR_SIZE field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE_Msk = 0x3ff800 + // Position of ULP_CP_MEM_OFFST_CLR field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR_Pos = 0x16 + // Bit mask of ULP_CP_MEM_OFFST_CLR field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR_Msk = 0x400000 + // Bit ULP_CP_MEM_OFFST_CLR. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR = 0x400000 + // Position of ULP_CP_CLK_FO field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_CLK_FO_Pos = 0x1c + // Bit mask of ULP_CP_CLK_FO field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_CLK_FO_Msk = 0x10000000 + // Bit ULP_CP_CLK_FO. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_CLK_FO = 0x10000000 + // Position of ULP_CP_RESET field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_RESET_Pos = 0x1d + // Bit mask of ULP_CP_RESET field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_RESET_Msk = 0x20000000 + // Bit ULP_CP_RESET. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_RESET = 0x20000000 + // Position of ULP_CP_FORCE_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP_Pos = 0x1e + // Bit mask of ULP_CP_FORCE_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP_Msk = 0x40000000 + // Bit ULP_CP_FORCE_START_TOP. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP = 0x40000000 + // Position of ULP_CP_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_START_TOP_Pos = 0x1f + // Bit mask of ULP_CP_START_TOP field. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_START_TOP_Msk = 0x80000000 + // Bit ULP_CP_START_TOP. + RTC_CNTL_ULP_CP_CTRL_ULP_CP_START_TOP = 0x80000000 + + // COCPU_CTRL: configure ulp-riscv + // Position of COCPU_CLK_FO field. + RTC_CNTL_COCPU_CTRL_COCPU_CLK_FO_Pos = 0x0 + // Bit mask of COCPU_CLK_FO field. + RTC_CNTL_COCPU_CTRL_COCPU_CLK_FO_Msk = 0x1 + // Bit COCPU_CLK_FO. + RTC_CNTL_COCPU_CTRL_COCPU_CLK_FO = 0x1 + // Position of COCPU_START_2_RESET_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_RESET_DIS_Pos = 0x1 + // Bit mask of COCPU_START_2_RESET_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_RESET_DIS_Msk = 0x7e + // Position of COCPU_START_2_INTR_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_INTR_EN_Pos = 0x7 + // Bit mask of COCPU_START_2_INTR_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_START_2_INTR_EN_Msk = 0x1f80 + // Position of COCPU_SHUT field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_Pos = 0xd + // Bit mask of COCPU_SHUT field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_Msk = 0x2000 + // Bit COCPU_SHUT. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT = 0x2000 + // Position of COCPU_SHUT_2_CLK_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS_Pos = 0xe + // Bit mask of COCPU_SHUT_2_CLK_DIS field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS_Msk = 0x3fc000 + // Position of COCPU_SHUT_RESET_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_RESET_EN_Pos = 0x16 + // Bit mask of COCPU_SHUT_RESET_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_RESET_EN_Msk = 0x400000 + // Bit COCPU_SHUT_RESET_EN. + RTC_CNTL_COCPU_CTRL_COCPU_SHUT_RESET_EN = 0x400000 + // Position of COCPU_SEL field. + RTC_CNTL_COCPU_CTRL_COCPU_SEL_Pos = 0x17 + // Bit mask of COCPU_SEL field. + RTC_CNTL_COCPU_CTRL_COCPU_SEL_Msk = 0x800000 + // Bit COCPU_SEL. + RTC_CNTL_COCPU_CTRL_COCPU_SEL = 0x800000 + // Position of COCPU_DONE_FORCE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_FORCE_Pos = 0x18 + // Bit mask of COCPU_DONE_FORCE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_FORCE_Msk = 0x1000000 + // Bit COCPU_DONE_FORCE. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_FORCE = 0x1000000 + // Position of COCPU_DONE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_Pos = 0x19 + // Bit mask of COCPU_DONE field. + RTC_CNTL_COCPU_CTRL_COCPU_DONE_Msk = 0x2000000 + // Bit COCPU_DONE. + RTC_CNTL_COCPU_CTRL_COCPU_DONE = 0x2000000 + // Position of COCPU_SW_INT_TRIGGER field. + RTC_CNTL_COCPU_CTRL_COCPU_SW_INT_TRIGGER_Pos = 0x1a + // Bit mask of COCPU_SW_INT_TRIGGER field. + RTC_CNTL_COCPU_CTRL_COCPU_SW_INT_TRIGGER_Msk = 0x4000000 + // Bit COCPU_SW_INT_TRIGGER. + RTC_CNTL_COCPU_CTRL_COCPU_SW_INT_TRIGGER = 0x4000000 + // Position of COCPU_CLKGATE_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_CLKGATE_EN_Pos = 0x1b + // Bit mask of COCPU_CLKGATE_EN field. + RTC_CNTL_COCPU_CTRL_COCPU_CLKGATE_EN_Msk = 0x8000000 + // Bit COCPU_CLKGATE_EN. + RTC_CNTL_COCPU_CTRL_COCPU_CLKGATE_EN = 0x8000000 + + // TOUCH_CTRL1: configure touch controller + // Position of TOUCH_SLEEP_CYCLES field. + RTC_CNTL_TOUCH_CTRL1_TOUCH_SLEEP_CYCLES_Pos = 0x0 + // Bit mask of TOUCH_SLEEP_CYCLES field. + RTC_CNTL_TOUCH_CTRL1_TOUCH_SLEEP_CYCLES_Msk = 0xffff + // Position of TOUCH_MEAS_NUM field. + RTC_CNTL_TOUCH_CTRL1_TOUCH_MEAS_NUM_Pos = 0x10 + // Bit mask of TOUCH_MEAS_NUM field. + RTC_CNTL_TOUCH_CTRL1_TOUCH_MEAS_NUM_Msk = 0xffff0000 + + // TOUCH_CTRL2: configure touch controller + // Position of TOUCH_DRANGE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DRANGE_Pos = 0x2 + // Bit mask of TOUCH_DRANGE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DRANGE_Msk = 0xc + // Position of TOUCH_DREFL field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DREFL_Pos = 0x4 + // Bit mask of TOUCH_DREFL field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DREFL_Msk = 0x30 + // Position of TOUCH_DREFH field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DREFH_Pos = 0x6 + // Bit mask of TOUCH_DREFH field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DREFH_Msk = 0xc0 + // Position of TOUCH_XPD_BIAS field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_BIAS_Pos = 0x8 + // Bit mask of TOUCH_XPD_BIAS field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_BIAS_Msk = 0x100 + // Bit TOUCH_XPD_BIAS. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_BIAS = 0x100 + // Position of TOUCH_REFC field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_REFC_Pos = 0x9 + // Bit mask of TOUCH_REFC field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_REFC_Msk = 0xe00 + // Position of TOUCH_DBIAS field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DBIAS_Pos = 0xc + // Bit mask of TOUCH_DBIAS field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DBIAS_Msk = 0x1000 + // Bit TOUCH_DBIAS. + RTC_CNTL_TOUCH_CTRL2_TOUCH_DBIAS = 0x1000 + // Position of TOUCH_SLP_TIMER_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_TIMER_EN_Pos = 0xd + // Bit mask of TOUCH_SLP_TIMER_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_TIMER_EN_Msk = 0x2000 + // Bit TOUCH_SLP_TIMER_EN. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_TIMER_EN = 0x2000 + // Position of TOUCH_START_FSM_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FSM_EN_Pos = 0xe + // Bit mask of TOUCH_START_FSM_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FSM_EN_Msk = 0x4000 + // Bit TOUCH_START_FSM_EN. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FSM_EN = 0x4000 + // Position of TOUCH_START_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_EN_Pos = 0xf + // Bit mask of TOUCH_START_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_EN_Msk = 0x8000 + // Bit TOUCH_START_EN. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_EN = 0x8000 + // Position of TOUCH_START_FORCE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FORCE_Pos = 0x10 + // Bit mask of TOUCH_START_FORCE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FORCE_Msk = 0x10000 + // Bit TOUCH_START_FORCE. + RTC_CNTL_TOUCH_CTRL2_TOUCH_START_FORCE = 0x10000 + // Position of TOUCH_XPD_WAIT field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_WAIT_Pos = 0x11 + // Bit mask of TOUCH_XPD_WAIT field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_XPD_WAIT_Msk = 0x1fe0000 + // Position of TOUCH_SLP_CYC_DIV field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_CYC_DIV_Pos = 0x19 + // Bit mask of TOUCH_SLP_CYC_DIV field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_SLP_CYC_DIV_Msk = 0x6000000 + // Position of TOUCH_TIMER_FORCE_DONE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_TIMER_FORCE_DONE_Pos = 0x1b + // Bit mask of TOUCH_TIMER_FORCE_DONE field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_TIMER_FORCE_DONE_Msk = 0x18000000 + // Position of TOUCH_RESET field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_RESET_Pos = 0x1d + // Bit mask of TOUCH_RESET field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_RESET_Msk = 0x20000000 + // Bit TOUCH_RESET. + RTC_CNTL_TOUCH_CTRL2_TOUCH_RESET = 0x20000000 + // Position of TOUCH_CLK_FO field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLK_FO_Pos = 0x1e + // Bit mask of TOUCH_CLK_FO field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLK_FO_Msk = 0x40000000 + // Bit TOUCH_CLK_FO. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLK_FO = 0x40000000 + // Position of TOUCH_CLKGATE_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLKGATE_EN_Pos = 0x1f + // Bit mask of TOUCH_CLKGATE_EN field. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLKGATE_EN_Msk = 0x80000000 + // Bit TOUCH_CLKGATE_EN. + RTC_CNTL_TOUCH_CTRL2_TOUCH_CLKGATE_EN = 0x80000000 + + // TOUCH_SCAN_CTRL: configure touch controller + // Position of TOUCH_DENOISE_RES field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_RES_Pos = 0x0 + // Bit mask of TOUCH_DENOISE_RES field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_RES_Msk = 0x3 + // Position of TOUCH_DENOISE_EN field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_EN_Pos = 0x2 + // Bit mask of TOUCH_DENOISE_EN field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_EN_Msk = 0x4 + // Bit TOUCH_DENOISE_EN. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_DENOISE_EN = 0x4 + // Position of TOUCH_INACTIVE_CONNECTION field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_CONNECTION field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION_Msk = 0x100 + // Bit TOUCH_INACTIVE_CONNECTION. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_INACTIVE_CONNECTION = 0x100 + // Position of TOUCH_SHIELD_PAD_EN field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN_Pos = 0x9 + // Bit mask of TOUCH_SHIELD_PAD_EN field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN_Msk = 0x200 + // Bit TOUCH_SHIELD_PAD_EN. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SHIELD_PAD_EN = 0x200 + // Position of TOUCH_SCAN_PAD_MAP field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SCAN_PAD_MAP_Pos = 0xa + // Bit mask of TOUCH_SCAN_PAD_MAP field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_SCAN_PAD_MAP_Msk = 0x1fffc00 + // Position of TOUCH_BUFDRV field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_BUFDRV_Pos = 0x19 + // Bit mask of TOUCH_BUFDRV field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_BUFDRV_Msk = 0xe000000 + // Position of TOUCH_OUT_RING field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_OUT_RING_Pos = 0x1c + // Bit mask of TOUCH_OUT_RING field. + RTC_CNTL_TOUCH_SCAN_CTRL_TOUCH_OUT_RING_Msk = 0xf0000000 + + // TOUCH_SLP_THRES: configure touch controller + // Position of TOUCH_SLP_TH field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_TH_Pos = 0x0 + // Bit mask of TOUCH_SLP_TH field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_TH_Msk = 0x3fffff + // Position of TOUCH_SLP_APPROACH_EN field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN_Pos = 0x1a + // Bit mask of TOUCH_SLP_APPROACH_EN field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN_Msk = 0x4000000 + // Bit TOUCH_SLP_APPROACH_EN. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_APPROACH_EN = 0x4000000 + // Position of TOUCH_SLP_PAD field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_PAD_Pos = 0x1b + // Bit mask of TOUCH_SLP_PAD field. + RTC_CNTL_TOUCH_SLP_THRES_TOUCH_SLP_PAD_Msk = 0xf8000000 + + // TOUCH_APPROACH: configure touch controller + // Position of TOUCH_SLP_CHANNEL_CLR field. + RTC_CNTL_TOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR_Pos = 0x17 + // Bit mask of TOUCH_SLP_CHANNEL_CLR field. + RTC_CNTL_TOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR_Msk = 0x800000 + // Bit TOUCH_SLP_CHANNEL_CLR. + RTC_CNTL_TOUCH_APPROACH_TOUCH_SLP_CHANNEL_CLR = 0x800000 + // Position of TOUCH_APPROACH_MEAS_TIME field. + RTC_CNTL_TOUCH_APPROACH_TOUCH_APPROACH_MEAS_TIME_Pos = 0x18 + // Bit mask of TOUCH_APPROACH_MEAS_TIME field. + RTC_CNTL_TOUCH_APPROACH_TOUCH_APPROACH_MEAS_TIME_Msk = 0xff000000 + + // TOUCH_FILTER_CTRL: configure touch controller + // Position of TOUCH_BYPASS_NEG_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_BYPASS_NEG_NOISE_THRES_Pos = 0x7 + // Bit mask of TOUCH_BYPASS_NEG_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_BYPASS_NEG_NOISE_THRES_Msk = 0x80 + // Bit TOUCH_BYPASS_NEG_NOISE_THRES. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_BYPASS_NEG_NOISE_THRES = 0x80 + // Position of TOUCH_BYPASS_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_BYPASS_NOISE_THRES_Pos = 0x8 + // Bit mask of TOUCH_BYPASS_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_BYPASS_NOISE_THRES_Msk = 0x100 + // Bit TOUCH_BYPASS_NOISE_THRES. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_BYPASS_NOISE_THRES = 0x100 + // Position of TOUCH_SMOOTH_LVL field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_SMOOTH_LVL_Pos = 0x9 + // Bit mask of TOUCH_SMOOTH_LVL field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_SMOOTH_LVL_Msk = 0x600 + // Position of TOUCH_JITTER_STEP field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_JITTER_STEP_Pos = 0xb + // Bit mask of TOUCH_JITTER_STEP field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_JITTER_STEP_Msk = 0x7800 + // Position of TOUCH_NEG_NOISE_LIMIT field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_LIMIT_Pos = 0xf + // Bit mask of TOUCH_NEG_NOISE_LIMIT field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_LIMIT_Msk = 0x78000 + // Position of TOUCH_NEG_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_THRES_Pos = 0x13 + // Bit mask of TOUCH_NEG_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NEG_NOISE_THRES_Msk = 0x180000 + // Position of TOUCH_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NOISE_THRES_Pos = 0x15 + // Bit mask of TOUCH_NOISE_THRES field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_NOISE_THRES_Msk = 0x600000 + // Position of TOUCH_HYSTERESIS field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_HYSTERESIS_Pos = 0x17 + // Bit mask of TOUCH_HYSTERESIS field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_HYSTERESIS_Msk = 0x1800000 + // Position of TOUCH_DEBOUNCE field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_DEBOUNCE_Pos = 0x19 + // Bit mask of TOUCH_DEBOUNCE field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_DEBOUNCE_Msk = 0xe000000 + // Position of TOUCH_FILTER_MODE field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_MODE_Pos = 0x1c + // Bit mask of TOUCH_FILTER_MODE field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_MODE_Msk = 0x70000000 + // Position of TOUCH_FILTER_EN field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_EN_Pos = 0x1f + // Bit mask of TOUCH_FILTER_EN field. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_EN_Msk = 0x80000000 + // Bit TOUCH_FILTER_EN. + RTC_CNTL_TOUCH_FILTER_CTRL_TOUCH_FILTER_EN = 0x80000000 + + // USB_CONF: usb configure + // Position of USB_VREFH field. + RTC_CNTL_USB_CONF_USB_VREFH_Pos = 0x0 + // Bit mask of USB_VREFH field. + RTC_CNTL_USB_CONF_USB_VREFH_Msk = 0x3 + // Position of USB_VREFL field. + RTC_CNTL_USB_CONF_USB_VREFL_Pos = 0x2 + // Bit mask of USB_VREFL field. + RTC_CNTL_USB_CONF_USB_VREFL_Msk = 0xc + // Position of USB_VREF_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_VREF_OVERRIDE_Pos = 0x4 + // Bit mask of USB_VREF_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_VREF_OVERRIDE_Msk = 0x10 + // Bit USB_VREF_OVERRIDE. + RTC_CNTL_USB_CONF_USB_VREF_OVERRIDE = 0x10 + // Position of USB_PAD_PULL_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_PAD_PULL_OVERRIDE_Pos = 0x5 + // Bit mask of USB_PAD_PULL_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_PAD_PULL_OVERRIDE_Msk = 0x20 + // Bit USB_PAD_PULL_OVERRIDE. + RTC_CNTL_USB_CONF_USB_PAD_PULL_OVERRIDE = 0x20 + // Position of USB_DP_PULLUP field. + RTC_CNTL_USB_CONF_USB_DP_PULLUP_Pos = 0x6 + // Bit mask of USB_DP_PULLUP field. + RTC_CNTL_USB_CONF_USB_DP_PULLUP_Msk = 0x40 + // Bit USB_DP_PULLUP. + RTC_CNTL_USB_CONF_USB_DP_PULLUP = 0x40 + // Position of USB_DP_PULLDOWN field. + RTC_CNTL_USB_CONF_USB_DP_PULLDOWN_Pos = 0x7 + // Bit mask of USB_DP_PULLDOWN field. + RTC_CNTL_USB_CONF_USB_DP_PULLDOWN_Msk = 0x80 + // Bit USB_DP_PULLDOWN. + RTC_CNTL_USB_CONF_USB_DP_PULLDOWN = 0x80 + // Position of USB_DM_PULLUP field. + RTC_CNTL_USB_CONF_USB_DM_PULLUP_Pos = 0x8 + // Bit mask of USB_DM_PULLUP field. + RTC_CNTL_USB_CONF_USB_DM_PULLUP_Msk = 0x100 + // Bit USB_DM_PULLUP. + RTC_CNTL_USB_CONF_USB_DM_PULLUP = 0x100 + // Position of USB_DM_PULLDOWN field. + RTC_CNTL_USB_CONF_USB_DM_PULLDOWN_Pos = 0x9 + // Bit mask of USB_DM_PULLDOWN field. + RTC_CNTL_USB_CONF_USB_DM_PULLDOWN_Msk = 0x200 + // Bit USB_DM_PULLDOWN. + RTC_CNTL_USB_CONF_USB_DM_PULLDOWN = 0x200 + // Position of USB_PULLUP_VALUE field. + RTC_CNTL_USB_CONF_USB_PULLUP_VALUE_Pos = 0xa + // Bit mask of USB_PULLUP_VALUE field. + RTC_CNTL_USB_CONF_USB_PULLUP_VALUE_Msk = 0x400 + // Bit USB_PULLUP_VALUE. + RTC_CNTL_USB_CONF_USB_PULLUP_VALUE = 0x400 + // Position of USB_PAD_ENABLE_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_OVERRIDE_Pos = 0xb + // Bit mask of USB_PAD_ENABLE_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_OVERRIDE_Msk = 0x800 + // Bit USB_PAD_ENABLE_OVERRIDE. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_OVERRIDE = 0x800 + // Position of USB_PAD_ENABLE field. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_Pos = 0xc + // Bit mask of USB_PAD_ENABLE field. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE_Msk = 0x1000 + // Bit USB_PAD_ENABLE. + RTC_CNTL_USB_CONF_USB_PAD_ENABLE = 0x1000 + // Position of USB_TXM field. + RTC_CNTL_USB_CONF_USB_TXM_Pos = 0xd + // Bit mask of USB_TXM field. + RTC_CNTL_USB_CONF_USB_TXM_Msk = 0x2000 + // Bit USB_TXM. + RTC_CNTL_USB_CONF_USB_TXM = 0x2000 + // Position of USB_TXP field. + RTC_CNTL_USB_CONF_USB_TXP_Pos = 0xe + // Bit mask of USB_TXP field. + RTC_CNTL_USB_CONF_USB_TXP_Msk = 0x4000 + // Bit USB_TXP. + RTC_CNTL_USB_CONF_USB_TXP = 0x4000 + // Position of USB_TX_EN field. + RTC_CNTL_USB_CONF_USB_TX_EN_Pos = 0xf + // Bit mask of USB_TX_EN field. + RTC_CNTL_USB_CONF_USB_TX_EN_Msk = 0x8000 + // Bit USB_TX_EN. + RTC_CNTL_USB_CONF_USB_TX_EN = 0x8000 + // Position of USB_TX_EN_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_TX_EN_OVERRIDE_Pos = 0x10 + // Bit mask of USB_TX_EN_OVERRIDE field. + RTC_CNTL_USB_CONF_USB_TX_EN_OVERRIDE_Msk = 0x10000 + // Bit USB_TX_EN_OVERRIDE. + RTC_CNTL_USB_CONF_USB_TX_EN_OVERRIDE = 0x10000 + // Position of USB_RESET_DISABLE field. + RTC_CNTL_USB_CONF_USB_RESET_DISABLE_Pos = 0x11 + // Bit mask of USB_RESET_DISABLE field. + RTC_CNTL_USB_CONF_USB_RESET_DISABLE_Msk = 0x20000 + // Bit USB_RESET_DISABLE. + RTC_CNTL_USB_CONF_USB_RESET_DISABLE = 0x20000 + // Position of IO_MUX_RESET_DISABLE field. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE_Pos = 0x12 + // Bit mask of IO_MUX_RESET_DISABLE field. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE_Msk = 0x40000 + // Bit IO_MUX_RESET_DISABLE. + RTC_CNTL_USB_CONF_IO_MUX_RESET_DISABLE = 0x40000 + // Position of SW_USB_PHY_SEL field. + RTC_CNTL_USB_CONF_SW_USB_PHY_SEL_Pos = 0x13 + // Bit mask of SW_USB_PHY_SEL field. + RTC_CNTL_USB_CONF_SW_USB_PHY_SEL_Msk = 0x80000 + // Bit SW_USB_PHY_SEL. + RTC_CNTL_USB_CONF_SW_USB_PHY_SEL = 0x80000 + // Position of SW_HW_USB_PHY_SEL field. + RTC_CNTL_USB_CONF_SW_HW_USB_PHY_SEL_Pos = 0x14 + // Bit mask of SW_HW_USB_PHY_SEL field. + RTC_CNTL_USB_CONF_SW_HW_USB_PHY_SEL_Msk = 0x100000 + // Bit SW_HW_USB_PHY_SEL. + RTC_CNTL_USB_CONF_SW_HW_USB_PHY_SEL = 0x100000 + + // TOUCH_TIMEOUT_CTRL: configure touch controller + // Position of TOUCH_TIMEOUT_NUM field. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_NUM_Pos = 0x0 + // Bit mask of TOUCH_TIMEOUT_NUM field. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_NUM_Msk = 0x3fffff + // Position of TOUCH_TIMEOUT_EN field. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN_Pos = 0x16 + // Bit mask of TOUCH_TIMEOUT_EN field. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN_Msk = 0x400000 + // Bit TOUCH_TIMEOUT_EN. + RTC_CNTL_TOUCH_TIMEOUT_CTRL_TOUCH_TIMEOUT_EN = 0x400000 + + // SLP_REJECT_CAUSE: get reject casue + // Position of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CAUSE_REJECT_CAUSE_Pos = 0x0 + // Bit mask of REJECT_CAUSE field. + RTC_CNTL_SLP_REJECT_CAUSE_REJECT_CAUSE_Msk = 0x3ffff + + // OPTION1: rtc common configure + // Position of FORCE_DOWNLOAD_BOOT field. + RTC_CNTL_OPTION1_FORCE_DOWNLOAD_BOOT_Pos = 0x0 + // Bit mask of FORCE_DOWNLOAD_BOOT field. + RTC_CNTL_OPTION1_FORCE_DOWNLOAD_BOOT_Msk = 0x1 + // Bit FORCE_DOWNLOAD_BOOT. + RTC_CNTL_OPTION1_FORCE_DOWNLOAD_BOOT = 0x1 + + // SLP_WAKEUP_CAUSE: get wakeup cause + // Position of WAKEUP_CAUSE field. + RTC_CNTL_SLP_WAKEUP_CAUSE_WAKEUP_CAUSE_Pos = 0x0 + // Bit mask of WAKEUP_CAUSE field. + RTC_CNTL_SLP_WAKEUP_CAUSE_WAKEUP_CAUSE_Msk = 0x1ffff + + // ULP_CP_TIMER_1: configure ulp sleep time + // Position of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Pos = 0x8 + // Bit mask of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Msk = 0xffffff00 + + // INT_ENA_RTC_W1TS: oneset rtc interrupt + // Position of SLP_WAKEUP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_WAKEUP_INT_ENA_W1TS = 0x1 + // Position of SLP_REJECT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SLP_REJECT_INT_ENA_W1TS = 0x2 + // Position of SDIO_IDLE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SDIO_IDLE_INT_ENA_W1TS_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SDIO_IDLE_INT_ENA_W1TS_Msk = 0x4 + // Bit SDIO_IDLE_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SDIO_IDLE_INT_ENA_W1TS = 0x4 + // Position of WDT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS_Pos = 0x3 + // Bit mask of WDT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS_Msk = 0x8 + // Bit WDT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_WDT_INT_ENA_W1TS = 0x8 + // Position of TOUCH_SCAN_DONE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_SCAN_DONE_INT_ENA_W1TS_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_SCAN_DONE_INT_ENA_W1TS_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_SCAN_DONE_INT_ENA_W1TS = 0x10 + // Position of ULP_CP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_ULP_CP_INT_ENA_W1TS_Pos = 0x5 + // Bit mask of ULP_CP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_ULP_CP_INT_ENA_W1TS_Msk = 0x20 + // Bit ULP_CP_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_ULP_CP_INT_ENA_W1TS = 0x20 + // Position of TOUCH_DONE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_DONE_INT_ENA_W1TS_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_DONE_INT_ENA_W1TS_Msk = 0x40 + // Bit TOUCH_DONE_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_DONE_INT_ENA_W1TS = 0x40 + // Position of TOUCH_ACTIVE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_ACTIVE_INT_ENA_W1TS_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_ACTIVE_INT_ENA_W1TS_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_ACTIVE_INT_ENA_W1TS = 0x80 + // Position of TOUCH_INACTIVE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_INACTIVE_INT_ENA_W1TS_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_INACTIVE_INT_ENA_W1TS_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_INACTIVE_INT_ENA_W1TS = 0x100 + // Position of BROWN_OUT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_BROWN_OUT_INT_ENA_W1TS = 0x200 + // Position of MAIN_TIMER_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_MAIN_TIMER_INT_ENA_W1TS = 0x400 + // Position of SARADC1_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SARADC1_INT_ENA_W1TS_Pos = 0xb + // Bit mask of SARADC1_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SARADC1_INT_ENA_W1TS_Msk = 0x800 + // Bit SARADC1_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SARADC1_INT_ENA_W1TS = 0x800 + // Position of TSENS_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TSENS_INT_ENA_W1TS_Pos = 0xc + // Bit mask of TSENS_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TSENS_INT_ENA_W1TS_Msk = 0x1000 + // Bit TSENS_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_TSENS_INT_ENA_W1TS = 0x1000 + // Position of COCPU_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_COCPU_INT_ENA_W1TS_Pos = 0xd + // Bit mask of COCPU_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_COCPU_INT_ENA_W1TS_Msk = 0x2000 + // Bit COCPU_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_COCPU_INT_ENA_W1TS = 0x2000 + // Position of SARADC2_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SARADC2_INT_ENA_W1TS_Pos = 0xe + // Bit mask of SARADC2_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SARADC2_INT_ENA_W1TS_Msk = 0x4000 + // Bit SARADC2_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SARADC2_INT_ENA_W1TS = 0x4000 + // Position of SWD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS_Pos = 0xf + // Bit mask of SWD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS_Msk = 0x8000 + // Bit SWD_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_SWD_INT_ENA_W1TS = 0x8000 + // Position of XTAL32K_DEAD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_XTAL32K_DEAD_INT_ENA_W1TS = 0x10000 + // Position of COCPU_TRAP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_COCPU_TRAP_INT_ENA_W1TS_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_COCPU_TRAP_INT_ENA_W1TS_Msk = 0x20000 + // Bit COCPU_TRAP_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_COCPU_TRAP_INT_ENA_W1TS = 0x20000 + // Position of TOUCH_TIMEOUT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_TIMEOUT_INT_ENA_W1TS_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_TIMEOUT_INT_ENA_W1TS_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_TIMEOUT_INT_ENA_W1TS = 0x40000 + // Position of GLITCH_DET_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS_Msk = 0x80000 + // Bit GLITCH_DET_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_GLITCH_DET_INT_ENA_W1TS = 0x80000 + // Position of TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_Pos = 0x14 + // Bit mask of TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS field. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_Msk = 0x100000 + // Bit TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS. + RTC_CNTL_INT_ENA_RTC_W1TS_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS = 0x100000 + + // INT_ENA_RTC_W1TC: oneset clr rtc interrupt enable + // Position of SLP_WAKEUP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC_Pos = 0x0 + // Bit mask of SLP_WAKEUP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC_Msk = 0x1 + // Bit SLP_WAKEUP_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_WAKEUP_INT_ENA_W1TC = 0x1 + // Position of SLP_REJECT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC_Pos = 0x1 + // Bit mask of SLP_REJECT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC_Msk = 0x2 + // Bit SLP_REJECT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SLP_REJECT_INT_ENA_W1TC = 0x2 + // Position of SDIO_IDLE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SDIO_IDLE_INT_ENA_W1TC_Pos = 0x2 + // Bit mask of SDIO_IDLE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SDIO_IDLE_INT_ENA_W1TC_Msk = 0x4 + // Bit SDIO_IDLE_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SDIO_IDLE_INT_ENA_W1TC = 0x4 + // Position of WDT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC_Pos = 0x3 + // Bit mask of WDT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC_Msk = 0x8 + // Bit WDT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_WDT_INT_ENA_W1TC = 0x8 + // Position of TOUCH_SCAN_DONE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_SCAN_DONE_INT_ENA_W1TC_Pos = 0x4 + // Bit mask of TOUCH_SCAN_DONE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_SCAN_DONE_INT_ENA_W1TC_Msk = 0x10 + // Bit TOUCH_SCAN_DONE_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_SCAN_DONE_INT_ENA_W1TC = 0x10 + // Position of ULP_CP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_ULP_CP_INT_ENA_W1TC_Pos = 0x5 + // Bit mask of ULP_CP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_ULP_CP_INT_ENA_W1TC_Msk = 0x20 + // Bit ULP_CP_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_ULP_CP_INT_ENA_W1TC = 0x20 + // Position of TOUCH_DONE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_DONE_INT_ENA_W1TC_Pos = 0x6 + // Bit mask of TOUCH_DONE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_DONE_INT_ENA_W1TC_Msk = 0x40 + // Bit TOUCH_DONE_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_DONE_INT_ENA_W1TC = 0x40 + // Position of TOUCH_ACTIVE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_ACTIVE_INT_ENA_W1TC_Pos = 0x7 + // Bit mask of TOUCH_ACTIVE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_ACTIVE_INT_ENA_W1TC_Msk = 0x80 + // Bit TOUCH_ACTIVE_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_ACTIVE_INT_ENA_W1TC = 0x80 + // Position of TOUCH_INACTIVE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_INACTIVE_INT_ENA_W1TC_Pos = 0x8 + // Bit mask of TOUCH_INACTIVE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_INACTIVE_INT_ENA_W1TC_Msk = 0x100 + // Bit TOUCH_INACTIVE_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_INACTIVE_INT_ENA_W1TC = 0x100 + // Position of BROWN_OUT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC_Pos = 0x9 + // Bit mask of BROWN_OUT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC_Msk = 0x200 + // Bit BROWN_OUT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_BROWN_OUT_INT_ENA_W1TC = 0x200 + // Position of MAIN_TIMER_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC_Pos = 0xa + // Bit mask of MAIN_TIMER_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC_Msk = 0x400 + // Bit MAIN_TIMER_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_MAIN_TIMER_INT_ENA_W1TC = 0x400 + // Position of SARADC1_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SARADC1_INT_ENA_W1TC_Pos = 0xb + // Bit mask of SARADC1_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SARADC1_INT_ENA_W1TC_Msk = 0x800 + // Bit SARADC1_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SARADC1_INT_ENA_W1TC = 0x800 + // Position of TSENS_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TSENS_INT_ENA_W1TC_Pos = 0xc + // Bit mask of TSENS_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TSENS_INT_ENA_W1TC_Msk = 0x1000 + // Bit TSENS_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_TSENS_INT_ENA_W1TC = 0x1000 + // Position of COCPU_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_COCPU_INT_ENA_W1TC_Pos = 0xd + // Bit mask of COCPU_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_COCPU_INT_ENA_W1TC_Msk = 0x2000 + // Bit COCPU_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_COCPU_INT_ENA_W1TC = 0x2000 + // Position of SARADC2_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SARADC2_INT_ENA_W1TC_Pos = 0xe + // Bit mask of SARADC2_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SARADC2_INT_ENA_W1TC_Msk = 0x4000 + // Bit SARADC2_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SARADC2_INT_ENA_W1TC = 0x4000 + // Position of SWD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC_Pos = 0xf + // Bit mask of SWD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC_Msk = 0x8000 + // Bit SWD_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_SWD_INT_ENA_W1TC = 0x8000 + // Position of XTAL32K_DEAD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC_Pos = 0x10 + // Bit mask of XTAL32K_DEAD_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC_Msk = 0x10000 + // Bit XTAL32K_DEAD_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_XTAL32K_DEAD_INT_ENA_W1TC = 0x10000 + // Position of COCPU_TRAP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_COCPU_TRAP_INT_ENA_W1TC_Pos = 0x11 + // Bit mask of COCPU_TRAP_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_COCPU_TRAP_INT_ENA_W1TC_Msk = 0x20000 + // Bit COCPU_TRAP_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_COCPU_TRAP_INT_ENA_W1TC = 0x20000 + // Position of TOUCH_TIMEOUT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_TIMEOUT_INT_ENA_W1TC_Pos = 0x12 + // Bit mask of TOUCH_TIMEOUT_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_TIMEOUT_INT_ENA_W1TC_Msk = 0x40000 + // Bit TOUCH_TIMEOUT_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_TIMEOUT_INT_ENA_W1TC = 0x40000 + // Position of GLITCH_DET_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC_Pos = 0x13 + // Bit mask of GLITCH_DET_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC_Msk = 0x80000 + // Bit GLITCH_DET_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_GLITCH_DET_INT_ENA_W1TC = 0x80000 + // Position of TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_Pos = 0x14 + // Bit mask of TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC field. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_Msk = 0x100000 + // Bit TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC. + RTC_CNTL_INT_ENA_RTC_W1TC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC = 0x100000 + + // RETENTION_CTRL: configure retention + // Position of RETENTION_TAG_MODE field. + RTC_CNTL_RETENTION_CTRL_RETENTION_TAG_MODE_Pos = 0xa + // Bit mask of RETENTION_TAG_MODE field. + RTC_CNTL_RETENTION_CTRL_RETENTION_TAG_MODE_Msk = 0x3c00 + // Position of RETENTION_TARGET field. + RTC_CNTL_RETENTION_CTRL_RETENTION_TARGET_Pos = 0xe + // Bit mask of RETENTION_TARGET field. + RTC_CNTL_RETENTION_CTRL_RETENTION_TARGET_Msk = 0xc000 + // Position of RETENTION_CLK_SEL field. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLK_SEL_Pos = 0x10 + // Bit mask of RETENTION_CLK_SEL field. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLK_SEL_Msk = 0x10000 + // Bit RETENTION_CLK_SEL. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLK_SEL = 0x10000 + // Position of RETENTION_DONE_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_DONE_WAIT_Pos = 0x11 + // Bit mask of RETENTION_DONE_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_DONE_WAIT_Msk = 0xe0000 + // Position of RETENTION_CLKOFF_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLKOFF_WAIT_Pos = 0x14 + // Bit mask of RETENTION_CLKOFF_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_CLKOFF_WAIT_Msk = 0xf00000 + // Position of RETENTION_EN field. + RTC_CNTL_RETENTION_CTRL_RETENTION_EN_Pos = 0x18 + // Bit mask of RETENTION_EN field. + RTC_CNTL_RETENTION_CTRL_RETENTION_EN_Msk = 0x1000000 + // Bit RETENTION_EN. + RTC_CNTL_RETENTION_CTRL_RETENTION_EN = 0x1000000 + // Position of RETENTION_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_WAIT_Pos = 0x19 + // Bit mask of RETENTION_WAIT field. + RTC_CNTL_RETENTION_CTRL_RETENTION_WAIT_Msk = 0xfe000000 + + // PG_CTRL: configure power glitch + // Position of POWER_GLITCH_DSENSE field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_DSENSE_Pos = 0x1a + // Bit mask of POWER_GLITCH_DSENSE field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_DSENSE_Msk = 0xc000000 + // Position of POWER_GLITCH_FORCE_PD field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PD_Pos = 0x1c + // Bit mask of POWER_GLITCH_FORCE_PD field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PD_Msk = 0x10000000 + // Bit POWER_GLITCH_FORCE_PD. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PD = 0x10000000 + // Position of POWER_GLITCH_FORCE_PU field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PU_Pos = 0x1d + // Bit mask of POWER_GLITCH_FORCE_PU field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PU_Msk = 0x20000000 + // Bit POWER_GLITCH_FORCE_PU. + RTC_CNTL_PG_CTRL_POWER_GLITCH_FORCE_PU = 0x20000000 + // Position of POWER_GLITCH_EFUSE_SEL field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EFUSE_SEL_Pos = 0x1e + // Bit mask of POWER_GLITCH_EFUSE_SEL field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EFUSE_SEL_Msk = 0x40000000 + // Bit POWER_GLITCH_EFUSE_SEL. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EFUSE_SEL = 0x40000000 + // Position of POWER_GLITCH_EN field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EN_Pos = 0x1f + // Bit mask of POWER_GLITCH_EN field. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EN_Msk = 0x80000000 + // Bit POWER_GLITCH_EN. + RTC_CNTL_PG_CTRL_POWER_GLITCH_EN = 0x80000000 + + // FIB_SEL: No public + // Position of FIB_SEL field. + RTC_CNTL_FIB_SEL_FIB_SEL_Pos = 0x0 + // Bit mask of FIB_SEL field. + RTC_CNTL_FIB_SEL_FIB_SEL_Msk = 0x7 + + // TOUCH_DAC: configure touch dac + // Position of TOUCH_PAD9_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD9_DAC_Pos = 0x2 + // Bit mask of TOUCH_PAD9_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD9_DAC_Msk = 0x1c + // Position of TOUCH_PAD8_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD8_DAC_Pos = 0x5 + // Bit mask of TOUCH_PAD8_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD8_DAC_Msk = 0xe0 + // Position of TOUCH_PAD7_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD7_DAC_Pos = 0x8 + // Bit mask of TOUCH_PAD7_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD7_DAC_Msk = 0x700 + // Position of TOUCH_PAD6_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD6_DAC_Pos = 0xb + // Bit mask of TOUCH_PAD6_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD6_DAC_Msk = 0x3800 + // Position of TOUCH_PAD5_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD5_DAC_Pos = 0xe + // Bit mask of TOUCH_PAD5_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD5_DAC_Msk = 0x1c000 + // Position of TOUCH_PAD4_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD4_DAC_Pos = 0x11 + // Bit mask of TOUCH_PAD4_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD4_DAC_Msk = 0xe0000 + // Position of TOUCH_PAD3_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD3_DAC_Pos = 0x14 + // Bit mask of TOUCH_PAD3_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD3_DAC_Msk = 0x700000 + // Position of TOUCH_PAD2_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD2_DAC_Pos = 0x17 + // Bit mask of TOUCH_PAD2_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD2_DAC_Msk = 0x3800000 + // Position of TOUCH_PAD1_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD1_DAC_Pos = 0x1a + // Bit mask of TOUCH_PAD1_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD1_DAC_Msk = 0x1c000000 + // Position of TOUCH_PAD0_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD0_DAC_Pos = 0x1d + // Bit mask of TOUCH_PAD0_DAC field. + RTC_CNTL_TOUCH_DAC_TOUCH_PAD0_DAC_Msk = 0xe0000000 + + // TOUCH_DAC1: configure touch dac + // Position of TOUCH_PAD14_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD14_DAC_Pos = 0x11 + // Bit mask of TOUCH_PAD14_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD14_DAC_Msk = 0xe0000 + // Position of TOUCH_PAD13_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD13_DAC_Pos = 0x14 + // Bit mask of TOUCH_PAD13_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD13_DAC_Msk = 0x700000 + // Position of TOUCH_PAD12_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD12_DAC_Pos = 0x17 + // Bit mask of TOUCH_PAD12_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD12_DAC_Msk = 0x3800000 + // Position of TOUCH_PAD11_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD11_DAC_Pos = 0x1a + // Bit mask of TOUCH_PAD11_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD11_DAC_Msk = 0x1c000000 + // Position of TOUCH_PAD10_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD10_DAC_Pos = 0x1d + // Bit mask of TOUCH_PAD10_DAC field. + RTC_CNTL_TOUCH_DAC1_TOUCH_PAD10_DAC_Msk = 0xe0000000 + + // COCPU_DISABLE: configure ulp diable + // Position of DISABLE_RTC_CPU field. + RTC_CNTL_COCPU_DISABLE_DISABLE_RTC_CPU_Pos = 0x1f + // Bit mask of DISABLE_RTC_CPU field. + RTC_CNTL_COCPU_DISABLE_DISABLE_RTC_CPU_Msk = 0x80000000 + // Bit DISABLE_RTC_CPU. + RTC_CNTL_COCPU_DISABLE_DISABLE_RTC_CPU = 0x80000000 + + // DATE: version register + // Position of DATE field. + RTC_CNTL_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RTC_CNTL_DATE_DATE_Msk = 0xfffffff +) + +// Constants for RTC_I2C: Low-power I2C (Inter-Integrated Circuit) Controller +const ( + // SCL_LOW: configure low scl period + // Position of PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_Msk = 0xfffff + + // CTRL: configure i2c ctrl + // Position of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + RTC_I2C_CTRL_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + RTC_I2C_CTRL_SCL_FORCE_OUT = 0x2 + // Position of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Pos = 0x2 + // Bit mask of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Msk = 0x4 + // Bit MS_MODE. + RTC_I2C_CTRL_MS_MODE = 0x4 + // Position of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Pos = 0x3 + // Bit mask of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Msk = 0x8 + // Bit TRANS_START. + RTC_I2C_CTRL_TRANS_START = 0x8 + // Position of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Pos = 0x4 + // Bit mask of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Msk = 0x10 + // Bit TX_LSB_FIRST. + RTC_I2C_CTRL_TX_LSB_FIRST = 0x10 + // Position of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Pos = 0x5 + // Bit mask of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Msk = 0x20 + // Bit RX_LSB_FIRST. + RTC_I2C_CTRL_RX_LSB_FIRST = 0x20 + // Position of I2C_CTRL_CLK_GATE_EN field. + RTC_I2C_CTRL_I2C_CTRL_CLK_GATE_EN_Pos = 0x1d + // Bit mask of I2C_CTRL_CLK_GATE_EN field. + RTC_I2C_CTRL_I2C_CTRL_CLK_GATE_EN_Msk = 0x20000000 + // Bit I2C_CTRL_CLK_GATE_EN. + RTC_I2C_CTRL_I2C_CTRL_CLK_GATE_EN = 0x20000000 + // Position of I2C_RESET field. + RTC_I2C_CTRL_I2C_RESET_Pos = 0x1e + // Bit mask of I2C_RESET field. + RTC_I2C_CTRL_I2C_RESET_Msk = 0x40000000 + // Bit I2C_RESET. + RTC_I2C_CTRL_I2C_RESET = 0x40000000 + // Position of I2CCLK_EN field. + RTC_I2C_CTRL_I2CCLK_EN_Pos = 0x1f + // Bit mask of I2CCLK_EN field. + RTC_I2C_CTRL_I2CCLK_EN_Msk = 0x80000000 + // Bit I2CCLK_EN. + RTC_I2C_CTRL_I2CCLK_EN = 0x80000000 + + // STATUS: get i2c status + // Position of ACK_REC field. + RTC_I2C_STATUS_ACK_REC_Pos = 0x0 + // Bit mask of ACK_REC field. + RTC_I2C_STATUS_ACK_REC_Msk = 0x1 + // Bit ACK_REC. + RTC_I2C_STATUS_ACK_REC = 0x1 + // Position of SLAVE_RW field. + RTC_I2C_STATUS_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + RTC_I2C_STATUS_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + RTC_I2C_STATUS_SLAVE_RW = 0x2 + // Position of ARB_LOST field. + RTC_I2C_STATUS_ARB_LOST_Pos = 0x2 + // Bit mask of ARB_LOST field. + RTC_I2C_STATUS_ARB_LOST_Msk = 0x4 + // Bit ARB_LOST. + RTC_I2C_STATUS_ARB_LOST = 0x4 + // Position of BUS_BUSY field. + RTC_I2C_STATUS_BUS_BUSY_Pos = 0x3 + // Bit mask of BUS_BUSY field. + RTC_I2C_STATUS_BUS_BUSY_Msk = 0x8 + // Bit BUS_BUSY. + RTC_I2C_STATUS_BUS_BUSY = 0x8 + // Position of SLAVE_ADDRESSED field. + RTC_I2C_STATUS_SLAVE_ADDRESSED_Pos = 0x4 + // Bit mask of SLAVE_ADDRESSED field. + RTC_I2C_STATUS_SLAVE_ADDRESSED_Msk = 0x10 + // Bit SLAVE_ADDRESSED. + RTC_I2C_STATUS_SLAVE_ADDRESSED = 0x10 + // Position of BYTE_TRANS field. + RTC_I2C_STATUS_BYTE_TRANS_Pos = 0x5 + // Bit mask of BYTE_TRANS field. + RTC_I2C_STATUS_BYTE_TRANS_Msk = 0x20 + // Bit BYTE_TRANS. + RTC_I2C_STATUS_BYTE_TRANS = 0x20 + // Position of OP_CNT field. + RTC_I2C_STATUS_OP_CNT_Pos = 0x6 + // Bit mask of OP_CNT field. + RTC_I2C_STATUS_OP_CNT_Msk = 0xc0 + // Position of SHIFT field. + RTC_I2C_STATUS_SHIFT_Pos = 0x10 + // Bit mask of SHIFT field. + RTC_I2C_STATUS_SHIFT_Msk = 0xff0000 + // Position of SCL_MAIN_STATE_LAST field. + RTC_I2C_STATUS_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + RTC_I2C_STATUS_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + RTC_I2C_STATUS_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + RTC_I2C_STATUS_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: configure time out + // Position of TIME_OUT field. + RTC_I2C_TO_TIME_OUT_Pos = 0x0 + // Bit mask of TIME_OUT field. + RTC_I2C_TO_TIME_OUT_Msk = 0xfffff + + // SLAVE_ADDR: configure slave id + // Position of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // SCL_HIGH: configure high scl period + // Position of PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_Msk = 0xfffff + + // SDA_DUTY: configure sda duty + // Position of NUM field. + RTC_I2C_SDA_DUTY_NUM_Pos = 0x0 + // Bit mask of NUM field. + RTC_I2C_SDA_DUTY_NUM_Msk = 0xfffff + + // SCL_START_PERIOD: configure scl start period + // Position of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Pos = 0x0 + // Bit mask of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Msk = 0xfffff + + // SCL_STOP_PERIOD: configure scl stop period + // Position of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Pos = 0x0 + // Bit mask of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Msk = 0xfffff + + // INT_CLR: interrupt clear register + // Position of SLAVE_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_CLR. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR = 0x1 + // Position of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_CLR. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x2 + // Position of MASTER_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_CLR. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR = 0x4 + // Position of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_CLR. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x8 + // Position of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x4 + // Bit mask of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x10 + // Bit TIME_OUT_INT_CLR. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR = 0x10 + // Position of ACK_ERR_INT_CLR field. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR_Pos = 0x5 + // Bit mask of ACK_ERR_INT_CLR field. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR_Msk = 0x20 + // Bit ACK_ERR_INT_CLR. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR = 0x20 + // Position of RX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR_Pos = 0x6 + // Bit mask of RX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR_Msk = 0x40 + // Bit RX_DATA_INT_CLR. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR = 0x40 + // Position of TX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR_Pos = 0x7 + // Bit mask of TX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR_Msk = 0x80 + // Bit TX_DATA_INT_CLR. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR = 0x80 + // Position of DETECT_START_INT_CLR field. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR_Pos = 0x8 + // Bit mask of DETECT_START_INT_CLR field. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR_Msk = 0x100 + // Bit DETECT_START_INT_CLR. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR = 0x100 + + // INT_RAW: interrupt raw register + // Position of SLAVE_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_RAW. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW = 0x1 + // Position of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_RAW. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x2 + // Position of MASTER_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_RAW. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW = 0x4 + // Position of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_RAW. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x8 + // Position of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x4 + // Bit mask of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x10 + // Bit TIME_OUT_INT_RAW. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW = 0x10 + // Position of ACK_ERR_INT_RAW field. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW_Pos = 0x5 + // Bit mask of ACK_ERR_INT_RAW field. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW_Msk = 0x20 + // Bit ACK_ERR_INT_RAW. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW = 0x20 + // Position of RX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW_Pos = 0x6 + // Bit mask of RX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW_Msk = 0x40 + // Bit RX_DATA_INT_RAW. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW = 0x40 + // Position of TX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW_Pos = 0x7 + // Bit mask of TX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW_Msk = 0x80 + // Bit TX_DATA_INT_RAW. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW = 0x80 + // Position of DETECT_START_INT_RAW field. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW_Pos = 0x8 + // Bit mask of DETECT_START_INT_RAW field. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW_Msk = 0x100 + // Bit DETECT_START_INT_RAW. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW = 0x100 + + // INT_ST: interrupt state register + // Position of SLAVE_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_ST. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST = 0x1 + // Position of ARBITRATION_LOST_INT_ST field. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_ST field. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_ST. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST = 0x2 + // Position of MASTER_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_ST. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST = 0x4 + // Position of TRANS_COMPLETE_INT_ST field. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_ST field. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_ST. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST = 0x8 + // Position of TIME_OUT_INT_ST field. + RTC_I2C_INT_ST_TIME_OUT_INT_ST_Pos = 0x4 + // Bit mask of TIME_OUT_INT_ST field. + RTC_I2C_INT_ST_TIME_OUT_INT_ST_Msk = 0x10 + // Bit TIME_OUT_INT_ST. + RTC_I2C_INT_ST_TIME_OUT_INT_ST = 0x10 + // Position of ACK_ERR_INT_ST field. + RTC_I2C_INT_ST_ACK_ERR_INT_ST_Pos = 0x5 + // Bit mask of ACK_ERR_INT_ST field. + RTC_I2C_INT_ST_ACK_ERR_INT_ST_Msk = 0x20 + // Bit ACK_ERR_INT_ST. + RTC_I2C_INT_ST_ACK_ERR_INT_ST = 0x20 + // Position of RX_DATA_INT_ST field. + RTC_I2C_INT_ST_RX_DATA_INT_ST_Pos = 0x6 + // Bit mask of RX_DATA_INT_ST field. + RTC_I2C_INT_ST_RX_DATA_INT_ST_Msk = 0x40 + // Bit RX_DATA_INT_ST. + RTC_I2C_INT_ST_RX_DATA_INT_ST = 0x40 + // Position of TX_DATA_INT_ST field. + RTC_I2C_INT_ST_TX_DATA_INT_ST_Pos = 0x7 + // Bit mask of TX_DATA_INT_ST field. + RTC_I2C_INT_ST_TX_DATA_INT_ST_Msk = 0x80 + // Bit TX_DATA_INT_ST. + RTC_I2C_INT_ST_TX_DATA_INT_ST = 0x80 + // Position of DETECT_START_INT_ST field. + RTC_I2C_INT_ST_DETECT_START_INT_ST_Pos = 0x8 + // Bit mask of DETECT_START_INT_ST field. + RTC_I2C_INT_ST_DETECT_START_INT_ST_Msk = 0x100 + // Bit DETECT_START_INT_ST. + RTC_I2C_INT_ST_DETECT_START_INT_ST = 0x100 + + // INT_ENA: interrupt enable register + // Position of SLAVE_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_ENA. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA = 0x1 + // Position of ARBITRATION_LOST_INT_ENA field. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_ENA. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x2 + // Position of MASTER_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_ENA. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA = 0x4 + // Position of TRANS_COMPLETE_INT_ENA field. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_ENA. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x8 + // Position of TIME_OUT_INT_ENA field. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x4 + // Bit mask of TIME_OUT_INT_ENA field. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x10 + // Bit TIME_OUT_INT_ENA. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA = 0x10 + // Position of ACK_ERR_INT_ENA field. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA_Pos = 0x5 + // Bit mask of ACK_ERR_INT_ENA field. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA_Msk = 0x20 + // Bit ACK_ERR_INT_ENA. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA = 0x20 + // Position of RX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA_Pos = 0x6 + // Bit mask of RX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA_Msk = 0x40 + // Bit RX_DATA_INT_ENA. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA = 0x40 + // Position of TX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA_Pos = 0x7 + // Bit mask of TX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA_Msk = 0x80 + // Bit TX_DATA_INT_ENA. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA = 0x80 + // Position of DETECT_START_INT_ENA field. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA_Pos = 0x8 + // Bit mask of DETECT_START_INT_ENA field. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA_Msk = 0x100 + // Bit DETECT_START_INT_ENA. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA = 0x100 + + // DATA: get i2c data status + // Position of I2C_RDATA field. + RTC_I2C_DATA_I2C_RDATA_Pos = 0x0 + // Bit mask of I2C_RDATA field. + RTC_I2C_DATA_I2C_RDATA_Msk = 0xff + // Position of SLAVE_TX_DATA field. + RTC_I2C_DATA_SLAVE_TX_DATA_Pos = 0x8 + // Bit mask of SLAVE_TX_DATA field. + RTC_I2C_DATA_SLAVE_TX_DATA_Msk = 0xff00 + // Position of I2C_DONE field. + RTC_I2C_DATA_I2C_DONE_Pos = 0x1f + // Bit mask of I2C_DONE field. + RTC_I2C_DATA_I2C_DONE_Msk = 0x80000000 + // Bit I2C_DONE. + RTC_I2C_DATA_I2C_DONE = 0x80000000 + + // CMD0: i2c commond0 register + // Position of COMMAND0 field. + RTC_I2C_CMD0_COMMAND0_Pos = 0x0 + // Bit mask of COMMAND0 field. + RTC_I2C_CMD0_COMMAND0_Msk = 0x3fff + // Position of COMMAND0_DONE field. + RTC_I2C_CMD0_COMMAND0_DONE_Pos = 0x1f + // Bit mask of COMMAND0_DONE field. + RTC_I2C_CMD0_COMMAND0_DONE_Msk = 0x80000000 + // Bit COMMAND0_DONE. + RTC_I2C_CMD0_COMMAND0_DONE = 0x80000000 + + // CMD1: i2c commond1 register + // Position of COMMAND1 field. + RTC_I2C_CMD1_COMMAND1_Pos = 0x0 + // Bit mask of COMMAND1 field. + RTC_I2C_CMD1_COMMAND1_Msk = 0x3fff + // Position of COMMAND1_DONE field. + RTC_I2C_CMD1_COMMAND1_DONE_Pos = 0x1f + // Bit mask of COMMAND1_DONE field. + RTC_I2C_CMD1_COMMAND1_DONE_Msk = 0x80000000 + // Bit COMMAND1_DONE. + RTC_I2C_CMD1_COMMAND1_DONE = 0x80000000 + + // CMD2: i2c commond2 register + // Position of COMMAND2 field. + RTC_I2C_CMD2_COMMAND2_Pos = 0x0 + // Bit mask of COMMAND2 field. + RTC_I2C_CMD2_COMMAND2_Msk = 0x3fff + // Position of COMMAND2_DONE field. + RTC_I2C_CMD2_COMMAND2_DONE_Pos = 0x1f + // Bit mask of COMMAND2_DONE field. + RTC_I2C_CMD2_COMMAND2_DONE_Msk = 0x80000000 + // Bit COMMAND2_DONE. + RTC_I2C_CMD2_COMMAND2_DONE = 0x80000000 + + // CMD3: i2c commond3 register + // Position of COMMAND3 field. + RTC_I2C_CMD3_COMMAND3_Pos = 0x0 + // Bit mask of COMMAND3 field. + RTC_I2C_CMD3_COMMAND3_Msk = 0x3fff + // Position of COMMAND3_DONE field. + RTC_I2C_CMD3_COMMAND3_DONE_Pos = 0x1f + // Bit mask of COMMAND3_DONE field. + RTC_I2C_CMD3_COMMAND3_DONE_Msk = 0x80000000 + // Bit COMMAND3_DONE. + RTC_I2C_CMD3_COMMAND3_DONE = 0x80000000 + + // CMD4: i2c commond4 register + // Position of COMMAND4 field. + RTC_I2C_CMD4_COMMAND4_Pos = 0x0 + // Bit mask of COMMAND4 field. + RTC_I2C_CMD4_COMMAND4_Msk = 0x3fff + // Position of COMMAND4_DONE field. + RTC_I2C_CMD4_COMMAND4_DONE_Pos = 0x1f + // Bit mask of COMMAND4_DONE field. + RTC_I2C_CMD4_COMMAND4_DONE_Msk = 0x80000000 + // Bit COMMAND4_DONE. + RTC_I2C_CMD4_COMMAND4_DONE = 0x80000000 + + // CMD5: i2c commond5_register + // Position of COMMAND5 field. + RTC_I2C_CMD5_COMMAND5_Pos = 0x0 + // Bit mask of COMMAND5 field. + RTC_I2C_CMD5_COMMAND5_Msk = 0x3fff + // Position of COMMAND5_DONE field. + RTC_I2C_CMD5_COMMAND5_DONE_Pos = 0x1f + // Bit mask of COMMAND5_DONE field. + RTC_I2C_CMD5_COMMAND5_DONE_Msk = 0x80000000 + // Bit COMMAND5_DONE. + RTC_I2C_CMD5_COMMAND5_DONE = 0x80000000 + + // CMD6: i2c commond6 register + // Position of COMMAND6 field. + RTC_I2C_CMD6_COMMAND6_Pos = 0x0 + // Bit mask of COMMAND6 field. + RTC_I2C_CMD6_COMMAND6_Msk = 0x3fff + // Position of COMMAND6_DONE field. + RTC_I2C_CMD6_COMMAND6_DONE_Pos = 0x1f + // Bit mask of COMMAND6_DONE field. + RTC_I2C_CMD6_COMMAND6_DONE_Msk = 0x80000000 + // Bit COMMAND6_DONE. + RTC_I2C_CMD6_COMMAND6_DONE = 0x80000000 + + // CMD7: i2c commond7 register + // Position of COMMAND7 field. + RTC_I2C_CMD7_COMMAND7_Pos = 0x0 + // Bit mask of COMMAND7 field. + RTC_I2C_CMD7_COMMAND7_Msk = 0x3fff + // Position of COMMAND7_DONE field. + RTC_I2C_CMD7_COMMAND7_DONE_Pos = 0x1f + // Bit mask of COMMAND7_DONE field. + RTC_I2C_CMD7_COMMAND7_DONE_Msk = 0x80000000 + // Bit COMMAND7_DONE. + RTC_I2C_CMD7_COMMAND7_DONE = 0x80000000 + + // CMD8: i2c commond8 register + // Position of COMMAND8 field. + RTC_I2C_CMD8_COMMAND8_Pos = 0x0 + // Bit mask of COMMAND8 field. + RTC_I2C_CMD8_COMMAND8_Msk = 0x3fff + // Position of COMMAND8_DONE field. + RTC_I2C_CMD8_COMMAND8_DONE_Pos = 0x1f + // Bit mask of COMMAND8_DONE field. + RTC_I2C_CMD8_COMMAND8_DONE_Msk = 0x80000000 + // Bit COMMAND8_DONE. + RTC_I2C_CMD8_COMMAND8_DONE = 0x80000000 + + // CMD9: i2c commond9 register + // Position of COMMAND9 field. + RTC_I2C_CMD9_COMMAND9_Pos = 0x0 + // Bit mask of COMMAND9 field. + RTC_I2C_CMD9_COMMAND9_Msk = 0x3fff + // Position of COMMAND9_DONE field. + RTC_I2C_CMD9_COMMAND9_DONE_Pos = 0x1f + // Bit mask of COMMAND9_DONE field. + RTC_I2C_CMD9_COMMAND9_DONE_Msk = 0x80000000 + // Bit COMMAND9_DONE. + RTC_I2C_CMD9_COMMAND9_DONE = 0x80000000 + + // CMD10: i2c commond10 register + // Position of COMMAND10 field. + RTC_I2C_CMD10_COMMAND10_Pos = 0x0 + // Bit mask of COMMAND10 field. + RTC_I2C_CMD10_COMMAND10_Msk = 0x3fff + // Position of COMMAND10_DONE field. + RTC_I2C_CMD10_COMMAND10_DONE_Pos = 0x1f + // Bit mask of COMMAND10_DONE field. + RTC_I2C_CMD10_COMMAND10_DONE_Msk = 0x80000000 + // Bit COMMAND10_DONE. + RTC_I2C_CMD10_COMMAND10_DONE = 0x80000000 + + // CMD11: i2c commond11 register + // Position of COMMAND11 field. + RTC_I2C_CMD11_COMMAND11_Pos = 0x0 + // Bit mask of COMMAND11 field. + RTC_I2C_CMD11_COMMAND11_Msk = 0x3fff + // Position of COMMAND11_DONE field. + RTC_I2C_CMD11_COMMAND11_DONE_Pos = 0x1f + // Bit mask of COMMAND11_DONE field. + RTC_I2C_CMD11_COMMAND11_DONE_Msk = 0x80000000 + // Bit COMMAND11_DONE. + RTC_I2C_CMD11_COMMAND11_DONE = 0x80000000 + + // CMD12: i2c commond12 register + // Position of COMMAND12 field. + RTC_I2C_CMD12_COMMAND12_Pos = 0x0 + // Bit mask of COMMAND12 field. + RTC_I2C_CMD12_COMMAND12_Msk = 0x3fff + // Position of COMMAND12_DONE field. + RTC_I2C_CMD12_COMMAND12_DONE_Pos = 0x1f + // Bit mask of COMMAND12_DONE field. + RTC_I2C_CMD12_COMMAND12_DONE_Msk = 0x80000000 + // Bit COMMAND12_DONE. + RTC_I2C_CMD12_COMMAND12_DONE = 0x80000000 + + // CMD13: i2c commond13 register + // Position of COMMAND13 field. + RTC_I2C_CMD13_COMMAND13_Pos = 0x0 + // Bit mask of COMMAND13 field. + RTC_I2C_CMD13_COMMAND13_Msk = 0x3fff + // Position of COMMAND13_DONE field. + RTC_I2C_CMD13_COMMAND13_DONE_Pos = 0x1f + // Bit mask of COMMAND13_DONE field. + RTC_I2C_CMD13_COMMAND13_DONE_Msk = 0x80000000 + // Bit COMMAND13_DONE. + RTC_I2C_CMD13_COMMAND13_DONE = 0x80000000 + + // CMD14: i2c commond14 register + // Position of COMMAND14 field. + RTC_I2C_CMD14_COMMAND14_Pos = 0x0 + // Bit mask of COMMAND14 field. + RTC_I2C_CMD14_COMMAND14_Msk = 0x3fff + // Position of COMMAND14_DONE field. + RTC_I2C_CMD14_COMMAND14_DONE_Pos = 0x1f + // Bit mask of COMMAND14_DONE field. + RTC_I2C_CMD14_COMMAND14_DONE_Msk = 0x80000000 + // Bit COMMAND14_DONE. + RTC_I2C_CMD14_COMMAND14_DONE = 0x80000000 + + // CMD15: i2c commond15 register + // Position of COMMAND15 field. + RTC_I2C_CMD15_COMMAND15_Pos = 0x0 + // Bit mask of COMMAND15 field. + RTC_I2C_CMD15_COMMAND15_Msk = 0x3fff + // Position of COMMAND15_DONE field. + RTC_I2C_CMD15_COMMAND15_DONE_Pos = 0x1f + // Bit mask of COMMAND15_DONE field. + RTC_I2C_CMD15_COMMAND15_DONE_Msk = 0x80000000 + // Bit COMMAND15_DONE. + RTC_I2C_CMD15_COMMAND15_DONE = 0x80000000 + + // DATE: version register + // Position of I2C_DATE field. + RTC_I2C_DATE_I2C_DATE_Pos = 0x0 + // Bit mask of I2C_DATE field. + RTC_I2C_DATE_I2C_DATE_Msk = 0xfffffff +) + +// Constants for RTC_IO: Low-power Input/Output +const ( + // RTC_GPIO_OUT: RTC GPIO 0 ~ 21 output data register + // Position of DATA field. + RTC_IO_RTC_GPIO_OUT_DATA_Pos = 0xa + // Bit mask of DATA field. + RTC_IO_RTC_GPIO_OUT_DATA_Msk = 0xfffffc00 + + // RTC_GPIO_OUT_W1TS: one set RTC GPIO output data + // Position of RTC_GPIO_OUT_DATA_W1TS field. + RTC_IO_RTC_GPIO_OUT_W1TS_RTC_GPIO_OUT_DATA_W1TS_Pos = 0xa + // Bit mask of RTC_GPIO_OUT_DATA_W1TS field. + RTC_IO_RTC_GPIO_OUT_W1TS_RTC_GPIO_OUT_DATA_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_OUT_W1TC: one clear RTC GPIO output data + // Position of RTC_GPIO_OUT_DATA_W1TC field. + RTC_IO_RTC_GPIO_OUT_W1TC_RTC_GPIO_OUT_DATA_W1TC_Pos = 0xa + // Bit mask of RTC_GPIO_OUT_DATA_W1TC field. + RTC_IO_RTC_GPIO_OUT_W1TC_RTC_GPIO_OUT_DATA_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE: Configure RTC GPIO output enable + // Position of RTC_GPIO_ENABLE field. + RTC_IO_RTC_GPIO_ENABLE_RTC_GPIO_ENABLE_Pos = 0xa + // Bit mask of RTC_GPIO_ENABLE field. + RTC_IO_RTC_GPIO_ENABLE_RTC_GPIO_ENABLE_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE_W1TS: one set RTC GPIO output enable + // Position of RTC_GPIO_ENABLE_W1TS field. + RTC_IO_RTC_GPIO_ENABLE_W1TS_RTC_GPIO_ENABLE_W1TS_Pos = 0xa + // Bit mask of RTC_GPIO_ENABLE_W1TS field. + RTC_IO_RTC_GPIO_ENABLE_W1TS_RTC_GPIO_ENABLE_W1TS_Msk = 0xfffffc00 + + // ENABLE_W1TC: one clear RTC GPIO output enable + // Position of ENABLE_W1TC field. + RTC_IO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0xa + // Bit mask of ENABLE_W1TC field. + RTC_IO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS: RTC GPIO 0 ~ 21 interrupt status + // Position of INT field. + RTC_IO_RTC_GPIO_STATUS_INT_Pos = 0xa + // Bit mask of INT field. + RTC_IO_RTC_GPIO_STATUS_INT_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS_W1TS: One set RTC GPIO 0 ~ 21 interrupt status + // Position of RTC_GPIO_STATUS_INT_W1TS field. + RTC_IO_RTC_GPIO_STATUS_W1TS_RTC_GPIO_STATUS_INT_W1TS_Pos = 0xa + // Bit mask of RTC_GPIO_STATUS_INT_W1TS field. + RTC_IO_RTC_GPIO_STATUS_W1TS_RTC_GPIO_STATUS_INT_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS_W1TC: One clear RTC GPIO 0 ~ 21 interrupt status + // Position of RTC_GPIO_STATUS_INT_W1TC field. + RTC_IO_RTC_GPIO_STATUS_W1TC_RTC_GPIO_STATUS_INT_W1TC_Pos = 0xa + // Bit mask of RTC_GPIO_STATUS_INT_W1TC field. + RTC_IO_RTC_GPIO_STATUS_W1TC_RTC_GPIO_STATUS_INT_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_IN: RTC GPIO input data + // Position of NEXT field. + RTC_IO_RTC_GPIO_IN_NEXT_Pos = 0xa + // Bit mask of NEXT field. + RTC_IO_RTC_GPIO_IN_NEXT_Msk = 0xfffffc00 + + // PIN0: configure RTC GPIO%s + // Position of PAD_DRIVER field. + RTC_IO_PIN_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_PIN_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_PIN_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_PIN_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_PIN_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_PIN_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_PIN_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_PIN_WAKEUP_ENABLE = 0x400 + + // RTC_DEBUG_SEL: configure rtc debug + // Position of RTC_DEBUG_SEL0 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL0_Pos = 0x0 + // Bit mask of RTC_DEBUG_SEL0 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL0_Msk = 0x1f + // Position of RTC_DEBUG_SEL1 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL1_Pos = 0x5 + // Bit mask of RTC_DEBUG_SEL1 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL1_Msk = 0x3e0 + // Position of RTC_DEBUG_SEL2 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL2_Pos = 0xa + // Bit mask of RTC_DEBUG_SEL2 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL2_Msk = 0x7c00 + // Position of RTC_DEBUG_SEL3 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL3_Pos = 0xf + // Bit mask of RTC_DEBUG_SEL3 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL3_Msk = 0xf8000 + // Position of RTC_DEBUG_SEL4 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL4_Pos = 0x14 + // Bit mask of RTC_DEBUG_SEL4 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL4_Msk = 0x1f00000 + // Position of RTC_DEBUG_12M_NO_GATING field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING_Pos = 0x19 + // Bit mask of RTC_DEBUG_12M_NO_GATING field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING_Msk = 0x2000000 + // Bit RTC_DEBUG_12M_NO_GATING. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING = 0x2000000 + + // TOUCH_PAD0: configure RTC PAD0 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD0_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD0_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD0_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD0_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD0_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD0_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD0_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD0_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD0_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD0_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD0_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD0_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD0_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD0_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD0_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD0_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD0_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD0_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD0_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD0_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD0_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD0_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD0_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD0_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD0_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD0_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD0_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD0_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD0_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD0_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD0_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD0_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD0_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD0_DRV_Msk = 0x60000000 + + // TOUCH_PAD1: configure RTC PAD1 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD1_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD1_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD1_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD1_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD1_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD1_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD1_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD1_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD1_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD1_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD1_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD1_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD1_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD1_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD1_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD1_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD1_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD1_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD1_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD1_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD1_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD1_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD1_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD1_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD1_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD1_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD1_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD1_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD1_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD1_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD1_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD1_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD1_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD1_DRV_Msk = 0x60000000 + + // TOUCH_PAD2: configure RTC PAD2 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD2_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD2_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD2_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD2_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD2_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD2_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD2_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD2_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD2_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD2_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD2_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD2_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD2_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD2_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD2_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD2_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD2_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD2_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD2_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD2_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD2_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD2_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD2_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD2_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD2_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD2_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD2_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD2_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD2_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD2_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD2_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD2_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD2_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD2_DRV_Msk = 0x60000000 + + // TOUCH_PAD3: configure RTC PAD3 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD3_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD3_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD3_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD3_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD3_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD3_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD3_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD3_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD3_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD3_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD3_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD3_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD3_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD3_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD3_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD3_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD3_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD3_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD3_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD3_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD3_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD3_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD3_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD3_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD3_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD3_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD3_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD3_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD3_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD3_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD3_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD3_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD3_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD3_DRV_Msk = 0x60000000 + + // TOUCH_PAD4: configure RTC PAD4 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD4_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD4_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD4_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD4_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD4_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD4_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD4_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD4_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD4_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD4_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD4_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD4_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD4_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD4_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD4_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD4_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD4_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD4_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD4_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD4_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD4_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD4_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD4_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD4_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD4_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD4_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD4_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD4_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD4_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD4_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD4_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD4_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD4_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD4_DRV_Msk = 0x60000000 + + // TOUCH_PAD5: configure RTC PAD5 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD5_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD5_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD5_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD5_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD5_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD5_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD5_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD5_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD5_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD5_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD5_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD5_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD5_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD5_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD5_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD5_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD5_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD5_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD5_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD5_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD5_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD5_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD5_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD5_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD5_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD5_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD5_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD5_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD5_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD5_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD5_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD5_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD5_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD5_DRV_Msk = 0x60000000 + + // TOUCH_PAD6: configure RTC PAD6 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD6_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD6_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD6_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD6_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD6_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD6_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD6_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD6_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD6_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD6_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD6_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD6_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD6_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD6_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD6_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD6_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD6_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD6_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD6_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD6_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD6_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD6_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD6_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD6_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD6_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD6_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD6_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD6_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD6_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD6_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD6_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD6_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD6_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD6_DRV_Msk = 0x60000000 + + // TOUCH_PAD7: configure RTC PAD7 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD7_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD7_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD7_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD7_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD7_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD7_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD7_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD7_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD7_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD7_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD7_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD7_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD7_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD7_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD7_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD7_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD7_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD7_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD7_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD7_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD7_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD7_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD7_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD7_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD7_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD7_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD7_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD7_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD7_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD7_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD7_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD7_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD7_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD7_DRV_Msk = 0x60000000 + + // TOUCH_PAD8: configure RTC PAD8 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD8_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD8_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD8_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD8_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD8_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD8_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD8_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD8_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD8_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD8_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD8_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD8_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD8_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD8_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD8_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD8_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD8_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD8_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD8_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD8_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD8_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD8_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD8_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD8_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD8_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD8_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD8_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD8_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD8_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD8_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD8_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD8_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD8_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD8_DRV_Msk = 0x60000000 + + // TOUCH_PAD9: configure RTC PAD9 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD9_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD9_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD9_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD9_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD9_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD9_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD9_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD9_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD9_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD9_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD9_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD9_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD9_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD9_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD9_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD9_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD9_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD9_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD9_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD9_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD9_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD9_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD9_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD9_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD9_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD9_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD9_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD9_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD9_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD9_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD9_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD9_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD9_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD9_DRV_Msk = 0x60000000 + + // TOUCH_PAD10: configure RTC PAD10 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD10_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD10_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD10_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD10_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD10_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD10_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD10_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD10_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD10_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD10_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD10_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD10_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD10_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD10_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD10_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD10_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD10_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD10_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD10_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD10_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD10_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD10_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD10_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD10_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD10_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD10_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD10_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD10_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD10_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD10_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD10_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD10_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD10_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD10_DRV_Msk = 0x60000000 + + // TOUCH_PAD11: configure RTC PAD11 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD11_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD11_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD11_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD11_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD11_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD11_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD11_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD11_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD11_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD11_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD11_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD11_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD11_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD11_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD11_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD11_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD11_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD11_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD11_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD11_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD11_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD11_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD11_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD11_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD11_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD11_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD11_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD11_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD11_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD11_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD11_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD11_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD11_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD11_DRV_Msk = 0x60000000 + + // TOUCH_PAD12: configure RTC PAD12 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD12_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD12_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD12_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD12_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD12_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD12_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD12_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD12_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD12_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD12_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD12_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD12_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD12_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD12_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD12_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD12_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD12_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD12_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD12_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD12_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD12_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD12_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD12_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD12_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD12_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD12_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD12_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD12_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD12_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD12_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD12_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD12_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD12_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD12_DRV_Msk = 0x60000000 + + // TOUCH_PAD13: configure RTC PAD13 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD13_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD13_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD13_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD13_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD13_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD13_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD13_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD13_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD13_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD13_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD13_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD13_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD13_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD13_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD13_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD13_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD13_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD13_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD13_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD13_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD13_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD13_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD13_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD13_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD13_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD13_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD13_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD13_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD13_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD13_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD13_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD13_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD13_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD13_DRV_Msk = 0x60000000 + + // TOUCH_PAD14: configure RTC PAD14 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD14_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD14_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD14_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD14_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD14_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD14_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD14_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD14_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD14_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD14_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD14_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD14_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD14_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD14_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD14_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD14_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD14_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD14_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD14_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD14_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD14_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD14_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD14_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD14_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD14_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD14_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD14_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD14_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD14_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD14_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD14_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD14_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD14_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD14_DRV_Msk = 0x60000000 + + // XTAL_32P_PAD: configure RTC PAD15 + // Position of X32P_FUN_IE field. + RTC_IO_XTAL_32P_PAD_X32P_FUN_IE_Pos = 0xd + // Bit mask of X32P_FUN_IE field. + RTC_IO_XTAL_32P_PAD_X32P_FUN_IE_Msk = 0x2000 + // Bit X32P_FUN_IE. + RTC_IO_XTAL_32P_PAD_X32P_FUN_IE = 0x2000 + // Position of X32P_SLP_OE field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_OE_Pos = 0xe + // Bit mask of X32P_SLP_OE field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_OE_Msk = 0x4000 + // Bit X32P_SLP_OE. + RTC_IO_XTAL_32P_PAD_X32P_SLP_OE = 0x4000 + // Position of X32P_SLP_IE field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_IE_Pos = 0xf + // Bit mask of X32P_SLP_IE field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_IE_Msk = 0x8000 + // Bit X32P_SLP_IE. + RTC_IO_XTAL_32P_PAD_X32P_SLP_IE = 0x8000 + // Position of X32P_SLP_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_SEL_Pos = 0x10 + // Bit mask of X32P_SLP_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_SEL_Msk = 0x10000 + // Bit X32P_SLP_SEL. + RTC_IO_XTAL_32P_PAD_X32P_SLP_SEL = 0x10000 + // Position of X32P_FUN_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_FUN_SEL_Pos = 0x11 + // Bit mask of X32P_FUN_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_FUN_SEL_Msk = 0x60000 + // Position of X32P_MUX_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_MUX_SEL_Pos = 0x13 + // Bit mask of X32P_MUX_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_MUX_SEL_Msk = 0x80000 + // Bit X32P_MUX_SEL. + RTC_IO_XTAL_32P_PAD_X32P_MUX_SEL = 0x80000 + // Position of X32P_RUE field. + RTC_IO_XTAL_32P_PAD_X32P_RUE_Pos = 0x1b + // Bit mask of X32P_RUE field. + RTC_IO_XTAL_32P_PAD_X32P_RUE_Msk = 0x8000000 + // Bit X32P_RUE. + RTC_IO_XTAL_32P_PAD_X32P_RUE = 0x8000000 + // Position of X32P_RDE field. + RTC_IO_XTAL_32P_PAD_X32P_RDE_Pos = 0x1c + // Bit mask of X32P_RDE field. + RTC_IO_XTAL_32P_PAD_X32P_RDE_Msk = 0x10000000 + // Bit X32P_RDE. + RTC_IO_XTAL_32P_PAD_X32P_RDE = 0x10000000 + // Position of X32P_DRV field. + RTC_IO_XTAL_32P_PAD_X32P_DRV_Pos = 0x1d + // Bit mask of X32P_DRV field. + RTC_IO_XTAL_32P_PAD_X32P_DRV_Msk = 0x60000000 + + // XTAL_32N_PAD: configure RTC PAD16 + // Position of X32N_FUN_IE field. + RTC_IO_XTAL_32N_PAD_X32N_FUN_IE_Pos = 0xd + // Bit mask of X32N_FUN_IE field. + RTC_IO_XTAL_32N_PAD_X32N_FUN_IE_Msk = 0x2000 + // Bit X32N_FUN_IE. + RTC_IO_XTAL_32N_PAD_X32N_FUN_IE = 0x2000 + // Position of X32N_SLP_OE field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_OE_Pos = 0xe + // Bit mask of X32N_SLP_OE field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_OE_Msk = 0x4000 + // Bit X32N_SLP_OE. + RTC_IO_XTAL_32N_PAD_X32N_SLP_OE = 0x4000 + // Position of X32N_SLP_IE field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_IE_Pos = 0xf + // Bit mask of X32N_SLP_IE field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_IE_Msk = 0x8000 + // Bit X32N_SLP_IE. + RTC_IO_XTAL_32N_PAD_X32N_SLP_IE = 0x8000 + // Position of X32N_SLP_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_SEL_Pos = 0x10 + // Bit mask of X32N_SLP_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_SEL_Msk = 0x10000 + // Bit X32N_SLP_SEL. + RTC_IO_XTAL_32N_PAD_X32N_SLP_SEL = 0x10000 + // Position of X32N_FUN_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_FUN_SEL_Pos = 0x11 + // Bit mask of X32N_FUN_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_FUN_SEL_Msk = 0x60000 + // Position of X32N_MUX_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_MUX_SEL_Pos = 0x13 + // Bit mask of X32N_MUX_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_MUX_SEL_Msk = 0x80000 + // Bit X32N_MUX_SEL. + RTC_IO_XTAL_32N_PAD_X32N_MUX_SEL = 0x80000 + // Position of X32N_RUE field. + RTC_IO_XTAL_32N_PAD_X32N_RUE_Pos = 0x1b + // Bit mask of X32N_RUE field. + RTC_IO_XTAL_32N_PAD_X32N_RUE_Msk = 0x8000000 + // Bit X32N_RUE. + RTC_IO_XTAL_32N_PAD_X32N_RUE = 0x8000000 + // Position of X32N_RDE field. + RTC_IO_XTAL_32N_PAD_X32N_RDE_Pos = 0x1c + // Bit mask of X32N_RDE field. + RTC_IO_XTAL_32N_PAD_X32N_RDE_Msk = 0x10000000 + // Bit X32N_RDE. + RTC_IO_XTAL_32N_PAD_X32N_RDE = 0x10000000 + // Position of X32N_DRV field. + RTC_IO_XTAL_32N_PAD_X32N_DRV_Pos = 0x1d + // Bit mask of X32N_DRV field. + RTC_IO_XTAL_32N_PAD_X32N_DRV_Msk = 0x60000000 + + // PAD_DAC1: configure RTC PAD17 + // Position of PDAC1_DAC field. + RTC_IO_PAD_DAC1_PDAC1_DAC_Pos = 0x3 + // Bit mask of PDAC1_DAC field. + RTC_IO_PAD_DAC1_PDAC1_DAC_Msk = 0x7f8 + // Position of PDAC1_XPD_DAC field. + RTC_IO_PAD_DAC1_PDAC1_XPD_DAC_Pos = 0xb + // Bit mask of PDAC1_XPD_DAC field. + RTC_IO_PAD_DAC1_PDAC1_XPD_DAC_Msk = 0x800 + // Bit PDAC1_XPD_DAC. + RTC_IO_PAD_DAC1_PDAC1_XPD_DAC = 0x800 + // Position of PDAC1_DAC_XPD_FORCE field. + RTC_IO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Pos = 0xc + // Bit mask of PDAC1_DAC_XPD_FORCE field. + RTC_IO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Msk = 0x1000 + // Bit PDAC1_DAC_XPD_FORCE. + RTC_IO_PAD_DAC1_PDAC1_DAC_XPD_FORCE = 0x1000 + // Position of PDAC1_FUN_IE field. + RTC_IO_PAD_DAC1_PDAC1_FUN_IE_Pos = 0xd + // Bit mask of PDAC1_FUN_IE field. + RTC_IO_PAD_DAC1_PDAC1_FUN_IE_Msk = 0x2000 + // Bit PDAC1_FUN_IE. + RTC_IO_PAD_DAC1_PDAC1_FUN_IE = 0x2000 + // Position of PDAC1_SLP_OE field. + RTC_IO_PAD_DAC1_PDAC1_SLP_OE_Pos = 0xe + // Bit mask of PDAC1_SLP_OE field. + RTC_IO_PAD_DAC1_PDAC1_SLP_OE_Msk = 0x4000 + // Bit PDAC1_SLP_OE. + RTC_IO_PAD_DAC1_PDAC1_SLP_OE = 0x4000 + // Position of PDAC1_SLP_IE field. + RTC_IO_PAD_DAC1_PDAC1_SLP_IE_Pos = 0xf + // Bit mask of PDAC1_SLP_IE field. + RTC_IO_PAD_DAC1_PDAC1_SLP_IE_Msk = 0x8000 + // Bit PDAC1_SLP_IE. + RTC_IO_PAD_DAC1_PDAC1_SLP_IE = 0x8000 + // Position of PDAC1_SLP_SEL field. + RTC_IO_PAD_DAC1_PDAC1_SLP_SEL_Pos = 0x10 + // Bit mask of PDAC1_SLP_SEL field. + RTC_IO_PAD_DAC1_PDAC1_SLP_SEL_Msk = 0x10000 + // Bit PDAC1_SLP_SEL. + RTC_IO_PAD_DAC1_PDAC1_SLP_SEL = 0x10000 + // Position of PDAC1_FUN_SEL field. + RTC_IO_PAD_DAC1_PDAC1_FUN_SEL_Pos = 0x11 + // Bit mask of PDAC1_FUN_SEL field. + RTC_IO_PAD_DAC1_PDAC1_FUN_SEL_Msk = 0x60000 + // Position of PDAC1_MUX_SEL field. + RTC_IO_PAD_DAC1_PDAC1_MUX_SEL_Pos = 0x13 + // Bit mask of PDAC1_MUX_SEL field. + RTC_IO_PAD_DAC1_PDAC1_MUX_SEL_Msk = 0x80000 + // Bit PDAC1_MUX_SEL. + RTC_IO_PAD_DAC1_PDAC1_MUX_SEL = 0x80000 + // Position of PDAC1_RUE field. + RTC_IO_PAD_DAC1_PDAC1_RUE_Pos = 0x1b + // Bit mask of PDAC1_RUE field. + RTC_IO_PAD_DAC1_PDAC1_RUE_Msk = 0x8000000 + // Bit PDAC1_RUE. + RTC_IO_PAD_DAC1_PDAC1_RUE = 0x8000000 + // Position of PDAC1_RDE field. + RTC_IO_PAD_DAC1_PDAC1_RDE_Pos = 0x1c + // Bit mask of PDAC1_RDE field. + RTC_IO_PAD_DAC1_PDAC1_RDE_Msk = 0x10000000 + // Bit PDAC1_RDE. + RTC_IO_PAD_DAC1_PDAC1_RDE = 0x10000000 + // Position of PDAC1_DRV field. + RTC_IO_PAD_DAC1_PDAC1_DRV_Pos = 0x1d + // Bit mask of PDAC1_DRV field. + RTC_IO_PAD_DAC1_PDAC1_DRV_Msk = 0x60000000 + + // PAD_DAC2: configure RTC PAD18 + // Position of PDAC2_DAC field. + RTC_IO_PAD_DAC2_PDAC2_DAC_Pos = 0x3 + // Bit mask of PDAC2_DAC field. + RTC_IO_PAD_DAC2_PDAC2_DAC_Msk = 0x7f8 + // Position of PDAC2_XPD_DAC field. + RTC_IO_PAD_DAC2_PDAC2_XPD_DAC_Pos = 0xb + // Bit mask of PDAC2_XPD_DAC field. + RTC_IO_PAD_DAC2_PDAC2_XPD_DAC_Msk = 0x800 + // Bit PDAC2_XPD_DAC. + RTC_IO_PAD_DAC2_PDAC2_XPD_DAC = 0x800 + // Position of PDAC2_DAC_XPD_FORCE field. + RTC_IO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Pos = 0xc + // Bit mask of PDAC2_DAC_XPD_FORCE field. + RTC_IO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Msk = 0x1000 + // Bit PDAC2_DAC_XPD_FORCE. + RTC_IO_PAD_DAC2_PDAC2_DAC_XPD_FORCE = 0x1000 + // Position of PDAC2_FUN_IE field. + RTC_IO_PAD_DAC2_PDAC2_FUN_IE_Pos = 0xd + // Bit mask of PDAC2_FUN_IE field. + RTC_IO_PAD_DAC2_PDAC2_FUN_IE_Msk = 0x2000 + // Bit PDAC2_FUN_IE. + RTC_IO_PAD_DAC2_PDAC2_FUN_IE = 0x2000 + // Position of PDAC2_SLP_OE field. + RTC_IO_PAD_DAC2_PDAC2_SLP_OE_Pos = 0xe + // Bit mask of PDAC2_SLP_OE field. + RTC_IO_PAD_DAC2_PDAC2_SLP_OE_Msk = 0x4000 + // Bit PDAC2_SLP_OE. + RTC_IO_PAD_DAC2_PDAC2_SLP_OE = 0x4000 + // Position of PDAC2_SLP_IE field. + RTC_IO_PAD_DAC2_PDAC2_SLP_IE_Pos = 0xf + // Bit mask of PDAC2_SLP_IE field. + RTC_IO_PAD_DAC2_PDAC2_SLP_IE_Msk = 0x8000 + // Bit PDAC2_SLP_IE. + RTC_IO_PAD_DAC2_PDAC2_SLP_IE = 0x8000 + // Position of PDAC2_SLP_SEL field. + RTC_IO_PAD_DAC2_PDAC2_SLP_SEL_Pos = 0x10 + // Bit mask of PDAC2_SLP_SEL field. + RTC_IO_PAD_DAC2_PDAC2_SLP_SEL_Msk = 0x10000 + // Bit PDAC2_SLP_SEL. + RTC_IO_PAD_DAC2_PDAC2_SLP_SEL = 0x10000 + // Position of PDAC2_FUN_SEL field. + RTC_IO_PAD_DAC2_PDAC2_FUN_SEL_Pos = 0x11 + // Bit mask of PDAC2_FUN_SEL field. + RTC_IO_PAD_DAC2_PDAC2_FUN_SEL_Msk = 0x60000 + // Position of PDAC2_MUX_SEL field. + RTC_IO_PAD_DAC2_PDAC2_MUX_SEL_Pos = 0x13 + // Bit mask of PDAC2_MUX_SEL field. + RTC_IO_PAD_DAC2_PDAC2_MUX_SEL_Msk = 0x80000 + // Bit PDAC2_MUX_SEL. + RTC_IO_PAD_DAC2_PDAC2_MUX_SEL = 0x80000 + // Position of PDAC2_RUE field. + RTC_IO_PAD_DAC2_PDAC2_RUE_Pos = 0x1b + // Bit mask of PDAC2_RUE field. + RTC_IO_PAD_DAC2_PDAC2_RUE_Msk = 0x8000000 + // Bit PDAC2_RUE. + RTC_IO_PAD_DAC2_PDAC2_RUE = 0x8000000 + // Position of PDAC2_RDE field. + RTC_IO_PAD_DAC2_PDAC2_RDE_Pos = 0x1c + // Bit mask of PDAC2_RDE field. + RTC_IO_PAD_DAC2_PDAC2_RDE_Msk = 0x10000000 + // Bit PDAC2_RDE. + RTC_IO_PAD_DAC2_PDAC2_RDE = 0x10000000 + // Position of PDAC2_DRV field. + RTC_IO_PAD_DAC2_PDAC2_DRV_Pos = 0x1d + // Bit mask of PDAC2_DRV field. + RTC_IO_PAD_DAC2_PDAC2_DRV_Msk = 0x60000000 + + // RTC_PAD19: configure RTC PAD19 + // Position of FUN_IE field. + RTC_IO_RTC_PAD19_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_RTC_PAD19_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_RTC_PAD19_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_RTC_PAD19_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_RTC_PAD19_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_RTC_PAD19_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_RTC_PAD19_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_RTC_PAD19_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_RTC_PAD19_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_RTC_PAD19_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_RTC_PAD19_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_RTC_PAD19_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_RTC_PAD19_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_RTC_PAD19_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_RTC_PAD19_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_RTC_PAD19_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_RTC_PAD19_MUX_SEL = 0x80000 + // Position of RUE field. + RTC_IO_RTC_PAD19_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_RTC_PAD19_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_RTC_PAD19_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_RTC_PAD19_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_RTC_PAD19_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_RTC_PAD19_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_RTC_PAD19_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_RTC_PAD19_DRV_Msk = 0x60000000 + + // RTC_PAD20: configure RTC PAD20 + // Position of FUN_IE field. + RTC_IO_RTC_PAD20_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_RTC_PAD20_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_RTC_PAD20_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_RTC_PAD20_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_RTC_PAD20_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_RTC_PAD20_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_RTC_PAD20_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_RTC_PAD20_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_RTC_PAD20_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_RTC_PAD20_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_RTC_PAD20_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_RTC_PAD20_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_RTC_PAD20_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_RTC_PAD20_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_RTC_PAD20_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_RTC_PAD20_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_RTC_PAD20_MUX_SEL = 0x80000 + // Position of RUE field. + RTC_IO_RTC_PAD20_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_RTC_PAD20_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_RTC_PAD20_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_RTC_PAD20_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_RTC_PAD20_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_RTC_PAD20_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_RTC_PAD20_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_RTC_PAD20_DRV_Msk = 0x60000000 + + // RTC_PAD21: configure RTC PAD21 + // Position of FUN_IE field. + RTC_IO_RTC_PAD21_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_RTC_PAD21_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_RTC_PAD21_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_RTC_PAD21_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_RTC_PAD21_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_RTC_PAD21_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_RTC_PAD21_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_RTC_PAD21_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_RTC_PAD21_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_RTC_PAD21_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_RTC_PAD21_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_RTC_PAD21_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_RTC_PAD21_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_RTC_PAD21_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_RTC_PAD21_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_RTC_PAD21_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_RTC_PAD21_MUX_SEL = 0x80000 + // Position of RUE field. + RTC_IO_RTC_PAD21_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_RTC_PAD21_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_RTC_PAD21_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_RTC_PAD21_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_RTC_PAD21_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_RTC_PAD21_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_RTC_PAD21_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_RTC_PAD21_DRV_Msk = 0x60000000 + + // EXT_WAKEUP0: configure EXT0 wakeup + // Position of SEL field. + RTC_IO_EXT_WAKEUP0_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTC_IO_EXT_WAKEUP0_SEL_Msk = 0xf8000000 + + // XTL_EXT_CTR: configure gpio pd XTAL + // Position of SEL field. + RTC_IO_XTL_EXT_CTR_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTC_IO_XTL_EXT_CTR_SEL_Msk = 0xf8000000 + + // SAR_I2C_IO: configure rtc i2c mux + // Position of SAR_DEBUG_BIT_SEL field. + RTC_IO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Pos = 0x17 + // Bit mask of SAR_DEBUG_BIT_SEL field. + RTC_IO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Msk = 0xf800000 + // Position of SAR_I2C_SCL_SEL field. + RTC_IO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Pos = 0x1c + // Bit mask of SAR_I2C_SCL_SEL field. + RTC_IO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Msk = 0x30000000 + // Position of SAR_I2C_SDA_SEL field. + RTC_IO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Pos = 0x1e + // Bit mask of SAR_I2C_SDA_SEL field. + RTC_IO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Msk = 0xc0000000 + + // TOUCH_CTRL: configure touch pad bufmode + // Position of IO_TOUCH_BUFSEL field. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL_Pos = 0x0 + // Bit mask of IO_TOUCH_BUFSEL field. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL_Msk = 0xf + // Position of IO_TOUCH_BUFMODE field. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE_Pos = 0x4 + // Bit mask of IO_TOUCH_BUFMODE field. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE_Msk = 0x10 + // Bit IO_TOUCH_BUFMODE. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE = 0x10 + + // DATE: version + // Position of DATE field. + RTC_IO_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RTC_IO_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SDHOST: SD/MMC Host Controller +const ( + // CTRL: Control register + // Position of CONTROLLER_RESET field. + SDHOST_CTRL_CONTROLLER_RESET_Pos = 0x0 + // Bit mask of CONTROLLER_RESET field. + SDHOST_CTRL_CONTROLLER_RESET_Msk = 0x1 + // Bit CONTROLLER_RESET. + SDHOST_CTRL_CONTROLLER_RESET = 0x1 + // Position of FIFO_RESET field. + SDHOST_CTRL_FIFO_RESET_Pos = 0x1 + // Bit mask of FIFO_RESET field. + SDHOST_CTRL_FIFO_RESET_Msk = 0x2 + // Bit FIFO_RESET. + SDHOST_CTRL_FIFO_RESET = 0x2 + // Position of DMA_RESET field. + SDHOST_CTRL_DMA_RESET_Pos = 0x2 + // Bit mask of DMA_RESET field. + SDHOST_CTRL_DMA_RESET_Msk = 0x4 + // Bit DMA_RESET. + SDHOST_CTRL_DMA_RESET = 0x4 + // Position of INT_ENABLE field. + SDHOST_CTRL_INT_ENABLE_Pos = 0x4 + // Bit mask of INT_ENABLE field. + SDHOST_CTRL_INT_ENABLE_Msk = 0x10 + // Bit INT_ENABLE. + SDHOST_CTRL_INT_ENABLE = 0x10 + // Position of READ_WAIT field. + SDHOST_CTRL_READ_WAIT_Pos = 0x6 + // Bit mask of READ_WAIT field. + SDHOST_CTRL_READ_WAIT_Msk = 0x40 + // Bit READ_WAIT. + SDHOST_CTRL_READ_WAIT = 0x40 + // Position of SEND_IRQ_RESPONSE field. + SDHOST_CTRL_SEND_IRQ_RESPONSE_Pos = 0x7 + // Bit mask of SEND_IRQ_RESPONSE field. + SDHOST_CTRL_SEND_IRQ_RESPONSE_Msk = 0x80 + // Bit SEND_IRQ_RESPONSE. + SDHOST_CTRL_SEND_IRQ_RESPONSE = 0x80 + // Position of ABORT_READ_DATA field. + SDHOST_CTRL_ABORT_READ_DATA_Pos = 0x8 + // Bit mask of ABORT_READ_DATA field. + SDHOST_CTRL_ABORT_READ_DATA_Msk = 0x100 + // Bit ABORT_READ_DATA. + SDHOST_CTRL_ABORT_READ_DATA = 0x100 + // Position of SEND_CCSD field. + SDHOST_CTRL_SEND_CCSD_Pos = 0x9 + // Bit mask of SEND_CCSD field. + SDHOST_CTRL_SEND_CCSD_Msk = 0x200 + // Bit SEND_CCSD. + SDHOST_CTRL_SEND_CCSD = 0x200 + // Position of SEND_AUTO_STOP_CCSD field. + SDHOST_CTRL_SEND_AUTO_STOP_CCSD_Pos = 0xa + // Bit mask of SEND_AUTO_STOP_CCSD field. + SDHOST_CTRL_SEND_AUTO_STOP_CCSD_Msk = 0x400 + // Bit SEND_AUTO_STOP_CCSD. + SDHOST_CTRL_SEND_AUTO_STOP_CCSD = 0x400 + // Position of CEATA_DEVICE_INTERRUPT_STATUS field. + SDHOST_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos = 0xb + // Bit mask of CEATA_DEVICE_INTERRUPT_STATUS field. + SDHOST_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk = 0x800 + // Bit CEATA_DEVICE_INTERRUPT_STATUS. + SDHOST_CTRL_CEATA_DEVICE_INTERRUPT_STATUS = 0x800 + + // CLKDIV: Clock divider configuration register + // Position of CLK_DIVIDER0 field. + SDHOST_CLKDIV_CLK_DIVIDER0_Pos = 0x0 + // Bit mask of CLK_DIVIDER0 field. + SDHOST_CLKDIV_CLK_DIVIDER0_Msk = 0xff + // Position of CLK_DIVIDER1 field. + SDHOST_CLKDIV_CLK_DIVIDER1_Pos = 0x8 + // Bit mask of CLK_DIVIDER1 field. + SDHOST_CLKDIV_CLK_DIVIDER1_Msk = 0xff00 + // Position of CLK_DIVIDER2 field. + SDHOST_CLKDIV_CLK_DIVIDER2_Pos = 0x10 + // Bit mask of CLK_DIVIDER2 field. + SDHOST_CLKDIV_CLK_DIVIDER2_Msk = 0xff0000 + // Position of CLK_DIVIDER3 field. + SDHOST_CLKDIV_CLK_DIVIDER3_Pos = 0x18 + // Bit mask of CLK_DIVIDER3 field. + SDHOST_CLKDIV_CLK_DIVIDER3_Msk = 0xff000000 + + // CLKSRC: Clock source selection register + // Position of CLKSRC field. + SDHOST_CLKSRC_CLKSRC_Pos = 0x0 + // Bit mask of CLKSRC field. + SDHOST_CLKSRC_CLKSRC_Msk = 0xf + + // CLKENA: Clock enable register + // Position of CCLK_ENABLE field. + SDHOST_CLKENA_CCLK_ENABLE_Pos = 0x0 + // Bit mask of CCLK_ENABLE field. + SDHOST_CLKENA_CCLK_ENABLE_Msk = 0x3 + // Position of LP_ENABLE field. + SDHOST_CLKENA_LP_ENABLE_Pos = 0x10 + // Bit mask of LP_ENABLE field. + SDHOST_CLKENA_LP_ENABLE_Msk = 0x30000 + + // TMOUT: Data and response timeout configuration register + // Position of RESPONSE_TIMEOUT field. + SDHOST_TMOUT_RESPONSE_TIMEOUT_Pos = 0x0 + // Bit mask of RESPONSE_TIMEOUT field. + SDHOST_TMOUT_RESPONSE_TIMEOUT_Msk = 0xff + // Position of DATA_TIMEOUT field. + SDHOST_TMOUT_DATA_TIMEOUT_Pos = 0x8 + // Bit mask of DATA_TIMEOUT field. + SDHOST_TMOUT_DATA_TIMEOUT_Msk = 0xffffff00 + + // CTYPE: Card bus width configuration register + // Position of CARD_WIDTH4 field. + SDHOST_CTYPE_CARD_WIDTH4_Pos = 0x0 + // Bit mask of CARD_WIDTH4 field. + SDHOST_CTYPE_CARD_WIDTH4_Msk = 0x3 + // Position of CARD_WIDTH8 field. + SDHOST_CTYPE_CARD_WIDTH8_Pos = 0x10 + // Bit mask of CARD_WIDTH8 field. + SDHOST_CTYPE_CARD_WIDTH8_Msk = 0x30000 + + // BLKSIZ: Card data block size configuration register + // Position of BLOCK_SIZE field. + SDHOST_BLKSIZ_BLOCK_SIZE_Pos = 0x0 + // Bit mask of BLOCK_SIZE field. + SDHOST_BLKSIZ_BLOCK_SIZE_Msk = 0xffff + + // BYTCNT: Data transfer length configuration register + // Position of BYTE_COUNT field. + SDHOST_BYTCNT_BYTE_COUNT_Pos = 0x0 + // Bit mask of BYTE_COUNT field. + SDHOST_BYTCNT_BYTE_COUNT_Msk = 0xffffffff + + // INTMASK: SDIO interrupt mask register + // Position of INT_MASK field. + SDHOST_INTMASK_INT_MASK_Pos = 0x0 + // Bit mask of INT_MASK field. + SDHOST_INTMASK_INT_MASK_Msk = 0xffff + // Position of SDIO_INT_MASK field. + SDHOST_INTMASK_SDIO_INT_MASK_Pos = 0x10 + // Bit mask of SDIO_INT_MASK field. + SDHOST_INTMASK_SDIO_INT_MASK_Msk = 0x30000 + + // CMDARG: Command argument data register + // Position of CMDARG field. + SDHOST_CMDARG_CMDARG_Pos = 0x0 + // Bit mask of CMDARG field. + SDHOST_CMDARG_CMDARG_Msk = 0xffffffff + + // CMD: Command and boot configuration register + // Position of INDEX field. + SDHOST_CMD_INDEX_Pos = 0x0 + // Bit mask of INDEX field. + SDHOST_CMD_INDEX_Msk = 0x3f + // Position of RESPONSE_EXPECT field. + SDHOST_CMD_RESPONSE_EXPECT_Pos = 0x6 + // Bit mask of RESPONSE_EXPECT field. + SDHOST_CMD_RESPONSE_EXPECT_Msk = 0x40 + // Bit RESPONSE_EXPECT. + SDHOST_CMD_RESPONSE_EXPECT = 0x40 + // Position of RESPONSE_LENGTH field. + SDHOST_CMD_RESPONSE_LENGTH_Pos = 0x7 + // Bit mask of RESPONSE_LENGTH field. + SDHOST_CMD_RESPONSE_LENGTH_Msk = 0x80 + // Bit RESPONSE_LENGTH. + SDHOST_CMD_RESPONSE_LENGTH = 0x80 + // Position of CHECK_RESPONSE_CRC field. + SDHOST_CMD_CHECK_RESPONSE_CRC_Pos = 0x8 + // Bit mask of CHECK_RESPONSE_CRC field. + SDHOST_CMD_CHECK_RESPONSE_CRC_Msk = 0x100 + // Bit CHECK_RESPONSE_CRC. + SDHOST_CMD_CHECK_RESPONSE_CRC = 0x100 + // Position of DATA_EXPECTED field. + SDHOST_CMD_DATA_EXPECTED_Pos = 0x9 + // Bit mask of DATA_EXPECTED field. + SDHOST_CMD_DATA_EXPECTED_Msk = 0x200 + // Bit DATA_EXPECTED. + SDHOST_CMD_DATA_EXPECTED = 0x200 + // Position of READ_WRITE field. + SDHOST_CMD_READ_WRITE_Pos = 0xa + // Bit mask of READ_WRITE field. + SDHOST_CMD_READ_WRITE_Msk = 0x400 + // Bit READ_WRITE. + SDHOST_CMD_READ_WRITE = 0x400 + // Position of TRANSFER_MODE field. + SDHOST_CMD_TRANSFER_MODE_Pos = 0xb + // Bit mask of TRANSFER_MODE field. + SDHOST_CMD_TRANSFER_MODE_Msk = 0x800 + // Bit TRANSFER_MODE. + SDHOST_CMD_TRANSFER_MODE = 0x800 + // Position of SEND_AUTO_STOP field. + SDHOST_CMD_SEND_AUTO_STOP_Pos = 0xc + // Bit mask of SEND_AUTO_STOP field. + SDHOST_CMD_SEND_AUTO_STOP_Msk = 0x1000 + // Bit SEND_AUTO_STOP. + SDHOST_CMD_SEND_AUTO_STOP = 0x1000 + // Position of WAIT_PRVDATA_COMPLETE field. + SDHOST_CMD_WAIT_PRVDATA_COMPLETE_Pos = 0xd + // Bit mask of WAIT_PRVDATA_COMPLETE field. + SDHOST_CMD_WAIT_PRVDATA_COMPLETE_Msk = 0x2000 + // Bit WAIT_PRVDATA_COMPLETE. + SDHOST_CMD_WAIT_PRVDATA_COMPLETE = 0x2000 + // Position of STOP_ABORT_CMD field. + SDHOST_CMD_STOP_ABORT_CMD_Pos = 0xe + // Bit mask of STOP_ABORT_CMD field. + SDHOST_CMD_STOP_ABORT_CMD_Msk = 0x4000 + // Bit STOP_ABORT_CMD. + SDHOST_CMD_STOP_ABORT_CMD = 0x4000 + // Position of SEND_INITIALIZATION field. + SDHOST_CMD_SEND_INITIALIZATION_Pos = 0xf + // Bit mask of SEND_INITIALIZATION field. + SDHOST_CMD_SEND_INITIALIZATION_Msk = 0x8000 + // Bit SEND_INITIALIZATION. + SDHOST_CMD_SEND_INITIALIZATION = 0x8000 + // Position of CARD_NUMBER field. + SDHOST_CMD_CARD_NUMBER_Pos = 0x10 + // Bit mask of CARD_NUMBER field. + SDHOST_CMD_CARD_NUMBER_Msk = 0x1f0000 + // Position of UPDATE_CLOCK_REGISTERS_ONLY field. + SDHOST_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos = 0x15 + // Bit mask of UPDATE_CLOCK_REGISTERS_ONLY field. + SDHOST_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk = 0x200000 + // Bit UPDATE_CLOCK_REGISTERS_ONLY. + SDHOST_CMD_UPDATE_CLOCK_REGISTERS_ONLY = 0x200000 + // Position of READ_CEATA_DEVICE field. + SDHOST_CMD_READ_CEATA_DEVICE_Pos = 0x16 + // Bit mask of READ_CEATA_DEVICE field. + SDHOST_CMD_READ_CEATA_DEVICE_Msk = 0x400000 + // Bit READ_CEATA_DEVICE. + SDHOST_CMD_READ_CEATA_DEVICE = 0x400000 + // Position of CCS_EXPECTED field. + SDHOST_CMD_CCS_EXPECTED_Pos = 0x17 + // Bit mask of CCS_EXPECTED field. + SDHOST_CMD_CCS_EXPECTED_Msk = 0x800000 + // Bit CCS_EXPECTED. + SDHOST_CMD_CCS_EXPECTED = 0x800000 + // Position of USE_HOLE field. + SDHOST_CMD_USE_HOLE_Pos = 0x1d + // Bit mask of USE_HOLE field. + SDHOST_CMD_USE_HOLE_Msk = 0x20000000 + // Bit USE_HOLE. + SDHOST_CMD_USE_HOLE = 0x20000000 + // Position of START_CMD field. + SDHOST_CMD_START_CMD_Pos = 0x1f + // Bit mask of START_CMD field. + SDHOST_CMD_START_CMD_Msk = 0x80000000 + // Bit START_CMD. + SDHOST_CMD_START_CMD = 0x80000000 + + // RESP0: Response data register + // Position of RESPONSE0 field. + SDHOST_RESP0_RESPONSE0_Pos = 0x0 + // Bit mask of RESPONSE0 field. + SDHOST_RESP0_RESPONSE0_Msk = 0xffffffff + + // RESP1: Long response data register + // Position of RESPONSE1 field. + SDHOST_RESP1_RESPONSE1_Pos = 0x0 + // Bit mask of RESPONSE1 field. + SDHOST_RESP1_RESPONSE1_Msk = 0xffffffff + + // RESP2: Long response data register + // Position of RESPONSE2 field. + SDHOST_RESP2_RESPONSE2_Pos = 0x0 + // Bit mask of RESPONSE2 field. + SDHOST_RESP2_RESPONSE2_Msk = 0xffffffff + + // RESP3: Long response data register + // Position of RESPONSE3 field. + SDHOST_RESP3_RESPONSE3_Pos = 0x0 + // Bit mask of RESPONSE3 field. + SDHOST_RESP3_RESPONSE3_Msk = 0xffffffff + + // MINTSTS: Masked interrupt status register + // Position of INT_STATUS_MSK field. + SDHOST_MINTSTS_INT_STATUS_MSK_Pos = 0x0 + // Bit mask of INT_STATUS_MSK field. + SDHOST_MINTSTS_INT_STATUS_MSK_Msk = 0xffff + // Position of SDIO_INTERRUPT_MSK field. + SDHOST_MINTSTS_SDIO_INTERRUPT_MSK_Pos = 0x10 + // Bit mask of SDIO_INTERRUPT_MSK field. + SDHOST_MINTSTS_SDIO_INTERRUPT_MSK_Msk = 0x30000 + + // RINTSTS: Raw interrupt status register + // Position of INT_STATUS_RAW field. + SDHOST_RINTSTS_INT_STATUS_RAW_Pos = 0x0 + // Bit mask of INT_STATUS_RAW field. + SDHOST_RINTSTS_INT_STATUS_RAW_Msk = 0xffff + // Position of SDIO_INTERRUPT_RAW field. + SDHOST_RINTSTS_SDIO_INTERRUPT_RAW_Pos = 0x10 + // Bit mask of SDIO_INTERRUPT_RAW field. + SDHOST_RINTSTS_SDIO_INTERRUPT_RAW_Msk = 0x30000 + + // STATUS: SD/MMC status register + // Position of FIFO_RX_WATERMARK field. + SDHOST_STATUS_FIFO_RX_WATERMARK_Pos = 0x0 + // Bit mask of FIFO_RX_WATERMARK field. + SDHOST_STATUS_FIFO_RX_WATERMARK_Msk = 0x1 + // Bit FIFO_RX_WATERMARK. + SDHOST_STATUS_FIFO_RX_WATERMARK = 0x1 + // Position of FIFO_TX_WATERMARK field. + SDHOST_STATUS_FIFO_TX_WATERMARK_Pos = 0x1 + // Bit mask of FIFO_TX_WATERMARK field. + SDHOST_STATUS_FIFO_TX_WATERMARK_Msk = 0x2 + // Bit FIFO_TX_WATERMARK. + SDHOST_STATUS_FIFO_TX_WATERMARK = 0x2 + // Position of FIFO_EMPTY field. + SDHOST_STATUS_FIFO_EMPTY_Pos = 0x2 + // Bit mask of FIFO_EMPTY field. + SDHOST_STATUS_FIFO_EMPTY_Msk = 0x4 + // Bit FIFO_EMPTY. + SDHOST_STATUS_FIFO_EMPTY = 0x4 + // Position of FIFO_FULL field. + SDHOST_STATUS_FIFO_FULL_Pos = 0x3 + // Bit mask of FIFO_FULL field. + SDHOST_STATUS_FIFO_FULL_Msk = 0x8 + // Bit FIFO_FULL. + SDHOST_STATUS_FIFO_FULL = 0x8 + // Position of COMMAND_FSM_STATES field. + SDHOST_STATUS_COMMAND_FSM_STATES_Pos = 0x4 + // Bit mask of COMMAND_FSM_STATES field. + SDHOST_STATUS_COMMAND_FSM_STATES_Msk = 0xf0 + // Position of DATA_3_STATUS field. + SDHOST_STATUS_DATA_3_STATUS_Pos = 0x8 + // Bit mask of DATA_3_STATUS field. + SDHOST_STATUS_DATA_3_STATUS_Msk = 0x100 + // Bit DATA_3_STATUS. + SDHOST_STATUS_DATA_3_STATUS = 0x100 + // Position of DATA_BUSY field. + SDHOST_STATUS_DATA_BUSY_Pos = 0x9 + // Bit mask of DATA_BUSY field. + SDHOST_STATUS_DATA_BUSY_Msk = 0x200 + // Bit DATA_BUSY. + SDHOST_STATUS_DATA_BUSY = 0x200 + // Position of DATA_STATE_MC_BUSY field. + SDHOST_STATUS_DATA_STATE_MC_BUSY_Pos = 0xa + // Bit mask of DATA_STATE_MC_BUSY field. + SDHOST_STATUS_DATA_STATE_MC_BUSY_Msk = 0x400 + // Bit DATA_STATE_MC_BUSY. + SDHOST_STATUS_DATA_STATE_MC_BUSY = 0x400 + // Position of RESPONSE_INDEX field. + SDHOST_STATUS_RESPONSE_INDEX_Pos = 0xb + // Bit mask of RESPONSE_INDEX field. + SDHOST_STATUS_RESPONSE_INDEX_Msk = 0x1f800 + // Position of FIFO_COUNT field. + SDHOST_STATUS_FIFO_COUNT_Pos = 0x11 + // Bit mask of FIFO_COUNT field. + SDHOST_STATUS_FIFO_COUNT_Msk = 0x3ffe0000 + + // FIFOTH: FIFO configuration register + // Position of TX_WMARK field. + SDHOST_FIFOTH_TX_WMARK_Pos = 0x0 + // Bit mask of TX_WMARK field. + SDHOST_FIFOTH_TX_WMARK_Msk = 0xfff + // Position of RX_WMARK field. + SDHOST_FIFOTH_RX_WMARK_Pos = 0x10 + // Bit mask of RX_WMARK field. + SDHOST_FIFOTH_RX_WMARK_Msk = 0x7ff0000 + // Position of DMA_MULTIPLE_TRANSACTION_SIZE field. + SDHOST_FIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE_Pos = 0x1c + // Bit mask of DMA_MULTIPLE_TRANSACTION_SIZE field. + SDHOST_FIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE_Msk = 0x70000000 + + // CDETECT: Card detect register + // Position of CARD_DETECT_N field. + SDHOST_CDETECT_CARD_DETECT_N_Pos = 0x0 + // Bit mask of CARD_DETECT_N field. + SDHOST_CDETECT_CARD_DETECT_N_Msk = 0x3 + + // WRTPRT: Card write protection (WP) status register + // Position of WRITE_PROTECT field. + SDHOST_WRTPRT_WRITE_PROTECT_Pos = 0x0 + // Bit mask of WRITE_PROTECT field. + SDHOST_WRTPRT_WRITE_PROTECT_Msk = 0x3 + + // TCBCNT: Transferred byte count register + // Position of TCBCNT field. + SDHOST_TCBCNT_TCBCNT_Pos = 0x0 + // Bit mask of TCBCNT field. + SDHOST_TCBCNT_TCBCNT_Msk = 0xffffffff + + // TBBCNT: Transferred byte count register + // Position of TBBCNT field. + SDHOST_TBBCNT_TBBCNT_Pos = 0x0 + // Bit mask of TBBCNT field. + SDHOST_TBBCNT_TBBCNT_Msk = 0xffffffff + + // DEBNCE: Debounce filter time configuration register + // Position of DEBOUNCE_COUNT field. + SDHOST_DEBNCE_DEBOUNCE_COUNT_Pos = 0x0 + // Bit mask of DEBOUNCE_COUNT field. + SDHOST_DEBNCE_DEBOUNCE_COUNT_Msk = 0xffffff + + // USRID: User ID (scratchpad) register + // Position of USRID field. + SDHOST_USRID_USRID_Pos = 0x0 + // Bit mask of USRID field. + SDHOST_USRID_USRID_Msk = 0xffffffff + + // VERID: Version ID (scratchpad) register + // Position of VERSIONID field. + SDHOST_VERID_VERSIONID_Pos = 0x0 + // Bit mask of VERSIONID field. + SDHOST_VERID_VERSIONID_Msk = 0xffffffff + + // HCON: Hardware feature register + // Position of CARD_TYPE field. + SDHOST_HCON_CARD_TYPE_Pos = 0x0 + // Bit mask of CARD_TYPE field. + SDHOST_HCON_CARD_TYPE_Msk = 0x1 + // Bit CARD_TYPE. + SDHOST_HCON_CARD_TYPE = 0x1 + // Position of CARD_NUM field. + SDHOST_HCON_CARD_NUM_Pos = 0x1 + // Bit mask of CARD_NUM field. + SDHOST_HCON_CARD_NUM_Msk = 0x3e + // Position of BUS_TYPE field. + SDHOST_HCON_BUS_TYPE_Pos = 0x6 + // Bit mask of BUS_TYPE field. + SDHOST_HCON_BUS_TYPE_Msk = 0x40 + // Bit BUS_TYPE. + SDHOST_HCON_BUS_TYPE = 0x40 + // Position of DATA_WIDTH field. + SDHOST_HCON_DATA_WIDTH_Pos = 0x7 + // Bit mask of DATA_WIDTH field. + SDHOST_HCON_DATA_WIDTH_Msk = 0x380 + // Position of ADDR_WIDTH field. + SDHOST_HCON_ADDR_WIDTH_Pos = 0xa + // Bit mask of ADDR_WIDTH field. + SDHOST_HCON_ADDR_WIDTH_Msk = 0xfc00 + // Position of DMA_WIDTH field. + SDHOST_HCON_DMA_WIDTH_Pos = 0x12 + // Bit mask of DMA_WIDTH field. + SDHOST_HCON_DMA_WIDTH_Msk = 0x1c0000 + // Position of RAM_INDISE field. + SDHOST_HCON_RAM_INDISE_Pos = 0x15 + // Bit mask of RAM_INDISE field. + SDHOST_HCON_RAM_INDISE_Msk = 0x200000 + // Bit RAM_INDISE. + SDHOST_HCON_RAM_INDISE = 0x200000 + // Position of HOLD field. + SDHOST_HCON_HOLD_Pos = 0x16 + // Bit mask of HOLD field. + SDHOST_HCON_HOLD_Msk = 0x400000 + // Bit HOLD. + SDHOST_HCON_HOLD = 0x400000 + // Position of NUM_CLK_DIV field. + SDHOST_HCON_NUM_CLK_DIV_Pos = 0x18 + // Bit mask of NUM_CLK_DIV field. + SDHOST_HCON_NUM_CLK_DIV_Msk = 0x3000000 + + // UHS: UHS-1 register + // Position of DDR field. + SDHOST_UHS_DDR_Pos = 0x10 + // Bit mask of DDR field. + SDHOST_UHS_DDR_Msk = 0x30000 + + // RST_N: Card reset register + // Position of CARD_RESET field. + SDHOST_RST_N_CARD_RESET_Pos = 0x0 + // Bit mask of CARD_RESET field. + SDHOST_RST_N_CARD_RESET_Msk = 0x3 + + // BMOD: Burst mode transfer configuration register + // Position of SWR field. + SDHOST_BMOD_SWR_Pos = 0x0 + // Bit mask of SWR field. + SDHOST_BMOD_SWR_Msk = 0x1 + // Bit SWR. + SDHOST_BMOD_SWR = 0x1 + // Position of FB field. + SDHOST_BMOD_FB_Pos = 0x1 + // Bit mask of FB field. + SDHOST_BMOD_FB_Msk = 0x2 + // Bit FB. + SDHOST_BMOD_FB = 0x2 + // Position of DE field. + SDHOST_BMOD_DE_Pos = 0x7 + // Bit mask of DE field. + SDHOST_BMOD_DE_Msk = 0x80 + // Bit DE. + SDHOST_BMOD_DE = 0x80 + // Position of PBL field. + SDHOST_BMOD_PBL_Pos = 0x8 + // Bit mask of PBL field. + SDHOST_BMOD_PBL_Msk = 0x700 + + // PLDMND: Poll demand configuration register + // Position of PD field. + SDHOST_PLDMND_PD_Pos = 0x0 + // Bit mask of PD field. + SDHOST_PLDMND_PD_Msk = 0xffffffff + + // DBADDR: Descriptor base address register + // Position of DBADDR field. + SDHOST_DBADDR_DBADDR_Pos = 0x0 + // Bit mask of DBADDR field. + SDHOST_DBADDR_DBADDR_Msk = 0xffffffff + + // IDSTS: IDMAC status register + // Position of TI field. + SDHOST_IDSTS_TI_Pos = 0x0 + // Bit mask of TI field. + SDHOST_IDSTS_TI_Msk = 0x1 + // Bit TI. + SDHOST_IDSTS_TI = 0x1 + // Position of RI field. + SDHOST_IDSTS_RI_Pos = 0x1 + // Bit mask of RI field. + SDHOST_IDSTS_RI_Msk = 0x2 + // Bit RI. + SDHOST_IDSTS_RI = 0x2 + // Position of FBE field. + SDHOST_IDSTS_FBE_Pos = 0x2 + // Bit mask of FBE field. + SDHOST_IDSTS_FBE_Msk = 0x4 + // Bit FBE. + SDHOST_IDSTS_FBE = 0x4 + // Position of DU field. + SDHOST_IDSTS_DU_Pos = 0x4 + // Bit mask of DU field. + SDHOST_IDSTS_DU_Msk = 0x10 + // Bit DU. + SDHOST_IDSTS_DU = 0x10 + // Position of CES field. + SDHOST_IDSTS_CES_Pos = 0x5 + // Bit mask of CES field. + SDHOST_IDSTS_CES_Msk = 0x20 + // Bit CES. + SDHOST_IDSTS_CES = 0x20 + // Position of NIS field. + SDHOST_IDSTS_NIS_Pos = 0x8 + // Bit mask of NIS field. + SDHOST_IDSTS_NIS_Msk = 0x100 + // Bit NIS. + SDHOST_IDSTS_NIS = 0x100 + // Position of AIS field. + SDHOST_IDSTS_AIS_Pos = 0x9 + // Bit mask of AIS field. + SDHOST_IDSTS_AIS_Msk = 0x200 + // Bit AIS. + SDHOST_IDSTS_AIS = 0x200 + // Position of FBE_CODE field. + SDHOST_IDSTS_FBE_CODE_Pos = 0xa + // Bit mask of FBE_CODE field. + SDHOST_IDSTS_FBE_CODE_Msk = 0x1c00 + // Position of FSM field. + SDHOST_IDSTS_FSM_Pos = 0xd + // Bit mask of FSM field. + SDHOST_IDSTS_FSM_Msk = 0x1e000 + + // IDINTEN: IDMAC interrupt enable register + // Position of TI field. + SDHOST_IDINTEN_TI_Pos = 0x0 + // Bit mask of TI field. + SDHOST_IDINTEN_TI_Msk = 0x1 + // Bit TI. + SDHOST_IDINTEN_TI = 0x1 + // Position of RI field. + SDHOST_IDINTEN_RI_Pos = 0x1 + // Bit mask of RI field. + SDHOST_IDINTEN_RI_Msk = 0x2 + // Bit RI. + SDHOST_IDINTEN_RI = 0x2 + // Position of FBE field. + SDHOST_IDINTEN_FBE_Pos = 0x2 + // Bit mask of FBE field. + SDHOST_IDINTEN_FBE_Msk = 0x4 + // Bit FBE. + SDHOST_IDINTEN_FBE = 0x4 + // Position of DU field. + SDHOST_IDINTEN_DU_Pos = 0x4 + // Bit mask of DU field. + SDHOST_IDINTEN_DU_Msk = 0x10 + // Bit DU. + SDHOST_IDINTEN_DU = 0x10 + // Position of CES field. + SDHOST_IDINTEN_CES_Pos = 0x5 + // Bit mask of CES field. + SDHOST_IDINTEN_CES_Msk = 0x20 + // Bit CES. + SDHOST_IDINTEN_CES = 0x20 + // Position of NI field. + SDHOST_IDINTEN_NI_Pos = 0x8 + // Bit mask of NI field. + SDHOST_IDINTEN_NI_Msk = 0x100 + // Bit NI. + SDHOST_IDINTEN_NI = 0x100 + // Position of AI field. + SDHOST_IDINTEN_AI_Pos = 0x9 + // Bit mask of AI field. + SDHOST_IDINTEN_AI_Msk = 0x200 + // Bit AI. + SDHOST_IDINTEN_AI = 0x200 + + // DSCADDR: Host descriptor address pointer + // Position of DSCADDR field. + SDHOST_DSCADDR_DSCADDR_Pos = 0x0 + // Bit mask of DSCADDR field. + SDHOST_DSCADDR_DSCADDR_Msk = 0xffffffff + + // BUFADDR: Host buffer address pointer register + // Position of BUFADDR field. + SDHOST_BUFADDR_BUFADDR_Pos = 0x0 + // Bit mask of BUFADDR field. + SDHOST_BUFADDR_BUFADDR_Msk = 0xffffffff + + // CARDTHRCTL: Card Threshold Control register + // Position of CARDRDTHREN field. + SDHOST_CARDTHRCTL_CARDRDTHREN_Pos = 0x0 + // Bit mask of CARDRDTHREN field. + SDHOST_CARDTHRCTL_CARDRDTHREN_Msk = 0x1 + // Bit CARDRDTHREN. + SDHOST_CARDTHRCTL_CARDRDTHREN = 0x1 + // Position of CARDCLRINTEN field. + SDHOST_CARDTHRCTL_CARDCLRINTEN_Pos = 0x1 + // Bit mask of CARDCLRINTEN field. + SDHOST_CARDTHRCTL_CARDCLRINTEN_Msk = 0x2 + // Bit CARDCLRINTEN. + SDHOST_CARDTHRCTL_CARDCLRINTEN = 0x2 + // Position of CARDWRTHREN field. + SDHOST_CARDTHRCTL_CARDWRTHREN_Pos = 0x2 + // Bit mask of CARDWRTHREN field. + SDHOST_CARDTHRCTL_CARDWRTHREN_Msk = 0x4 + // Bit CARDWRTHREN. + SDHOST_CARDTHRCTL_CARDWRTHREN = 0x4 + // Position of CARDTHRESHOLD field. + SDHOST_CARDTHRCTL_CARDTHRESHOLD_Pos = 0x10 + // Bit mask of CARDTHRESHOLD field. + SDHOST_CARDTHRCTL_CARDTHRESHOLD_Msk = 0xffff0000 + + // EMMCDDR: eMMC DDR register + // Position of HALFSTARTBIT field. + SDHOST_EMMCDDR_HALFSTARTBIT_Pos = 0x0 + // Bit mask of HALFSTARTBIT field. + SDHOST_EMMCDDR_HALFSTARTBIT_Msk = 0x3 + // Position of HS400_MODE field. + SDHOST_EMMCDDR_HS400_MODE_Pos = 0x1f + // Bit mask of HS400_MODE field. + SDHOST_EMMCDDR_HS400_MODE_Msk = 0x80000000 + // Bit HS400_MODE. + SDHOST_EMMCDDR_HS400_MODE = 0x80000000 + + // ENSHIFT: Enable Phase Shift register + // Position of ENABLE_SHIFT field. + SDHOST_ENSHIFT_ENABLE_SHIFT_Pos = 0x0 + // Bit mask of ENABLE_SHIFT field. + SDHOST_ENSHIFT_ENABLE_SHIFT_Msk = 0xf + + // BUFFIFO: CPU write and read transmit data by FIFO + // Position of BUFFIFO field. + SDHOST_BUFFIFO_BUFFIFO_Pos = 0x0 + // Bit mask of BUFFIFO field. + SDHOST_BUFFIFO_BUFFIFO_Msk = 0xffffffff + + // CLK_EDGE_SEL: SDIO control register. + // Position of CCLKIN_EDGE_DRV_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL_Pos = 0x0 + // Bit mask of CCLKIN_EDGE_DRV_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL_Msk = 0x7 + // Position of CCLKIN_EDGE_SAM_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL_Pos = 0x3 + // Bit mask of CCLKIN_EDGE_SAM_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL_Msk = 0x38 + // Position of CCLKIN_EDGE_SLF_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL_Pos = 0x6 + // Bit mask of CCLKIN_EDGE_SLF_SEL field. + SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL_Msk = 0x1c0 + // Position of CCLLKIN_EDGE_H field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_H_Pos = 0x9 + // Bit mask of CCLLKIN_EDGE_H field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_H_Msk = 0x1e00 + // Position of CCLLKIN_EDGE_L field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_L_Pos = 0xd + // Bit mask of CCLLKIN_EDGE_L field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_L_Msk = 0x1e000 + // Position of CCLLKIN_EDGE_N field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_N_Pos = 0x11 + // Bit mask of CCLLKIN_EDGE_N field. + SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_N_Msk = 0x1e0000 + // Position of ESDIO_MODE field. + SDHOST_CLK_EDGE_SEL_ESDIO_MODE_Pos = 0x15 + // Bit mask of ESDIO_MODE field. + SDHOST_CLK_EDGE_SEL_ESDIO_MODE_Msk = 0x200000 + // Bit ESDIO_MODE. + SDHOST_CLK_EDGE_SEL_ESDIO_MODE = 0x200000 + // Position of ESD_MODE field. + SDHOST_CLK_EDGE_SEL_ESD_MODE_Pos = 0x16 + // Bit mask of ESD_MODE field. + SDHOST_CLK_EDGE_SEL_ESD_MODE_Msk = 0x400000 + // Bit ESD_MODE. + SDHOST_CLK_EDGE_SEL_ESD_MODE = 0x400000 + // Position of CCLK_EN field. + SDHOST_CLK_EDGE_SEL_CCLK_EN_Pos = 0x17 + // Bit mask of CCLK_EN field. + SDHOST_CLK_EDGE_SEL_CCLK_EN_Msk = 0x800000 + // Bit CCLK_EN. + SDHOST_CLK_EDGE_SEL_CCLK_EN = 0x800000 +) + +// Constants for SENS: SENS Peripheral +const ( + // SAR_READER1_CTRL: configure saradc1 reader + // Position of SAR_SAR1_CLK_DIV field. + SENS_SAR_READER1_CTRL_SAR_SAR1_CLK_DIV_Pos = 0x0 + // Bit mask of SAR_SAR1_CLK_DIV field. + SENS_SAR_READER1_CTRL_SAR_SAR1_CLK_DIV_Msk = 0xff + // Position of SAR_SAR1_CLK_GATED field. + SENS_SAR_READER1_CTRL_SAR_SAR1_CLK_GATED_Pos = 0x12 + // Bit mask of SAR_SAR1_CLK_GATED field. + SENS_SAR_READER1_CTRL_SAR_SAR1_CLK_GATED_Msk = 0x40000 + // Bit SAR_SAR1_CLK_GATED. + SENS_SAR_READER1_CTRL_SAR_SAR1_CLK_GATED = 0x40000 + // Position of SAR_SAR1_SAMPLE_NUM field. + SENS_SAR_READER1_CTRL_SAR_SAR1_SAMPLE_NUM_Pos = 0x13 + // Bit mask of SAR_SAR1_SAMPLE_NUM field. + SENS_SAR_READER1_CTRL_SAR_SAR1_SAMPLE_NUM_Msk = 0x7f80000 + // Position of SAR_SAR1_DATA_INV field. + SENS_SAR_READER1_CTRL_SAR_SAR1_DATA_INV_Pos = 0x1c + // Bit mask of SAR_SAR1_DATA_INV field. + SENS_SAR_READER1_CTRL_SAR_SAR1_DATA_INV_Msk = 0x10000000 + // Bit SAR_SAR1_DATA_INV. + SENS_SAR_READER1_CTRL_SAR_SAR1_DATA_INV = 0x10000000 + // Position of SAR_SAR1_INT_EN field. + SENS_SAR_READER1_CTRL_SAR_SAR1_INT_EN_Pos = 0x1d + // Bit mask of SAR_SAR1_INT_EN field. + SENS_SAR_READER1_CTRL_SAR_SAR1_INT_EN_Msk = 0x20000000 + // Bit SAR_SAR1_INT_EN. + SENS_SAR_READER1_CTRL_SAR_SAR1_INT_EN = 0x20000000 + + // SAR_READER1_STATUS: get saradc1 reader controller status + // Position of SAR_SAR1_READER_STATUS field. + SENS_SAR_READER1_STATUS_SAR_SAR1_READER_STATUS_Pos = 0x0 + // Bit mask of SAR_SAR1_READER_STATUS field. + SENS_SAR_READER1_STATUS_SAR_SAR1_READER_STATUS_Msk = 0xffffffff + + // SAR_MEAS1_CTRL1: no public + // Position of FORCE_XPD_AMP field. + SENS_SAR_MEAS1_CTRL1_FORCE_XPD_AMP_Pos = 0x18 + // Bit mask of FORCE_XPD_AMP field. + SENS_SAR_MEAS1_CTRL1_FORCE_XPD_AMP_Msk = 0x3000000 + // Position of AMP_RST_FB_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_RST_FB_FORCE_Pos = 0x1a + // Bit mask of AMP_RST_FB_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_RST_FB_FORCE_Msk = 0xc000000 + // Position of AMP_SHORT_REF_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_SHORT_REF_FORCE_Pos = 0x1c + // Bit mask of AMP_SHORT_REF_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_SHORT_REF_FORCE_Msk = 0x30000000 + // Position of AMP_SHORT_REF_GND_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE_Pos = 0x1e + // Bit mask of AMP_SHORT_REF_GND_FORCE field. + SENS_SAR_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE_Msk = 0xc0000000 + + // SAR_MEAS1_CTRL2: configure saradc1 controller + // Position of MEAS1_DATA_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_DATA_SAR_Pos = 0x0 + // Bit mask of MEAS1_DATA_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_DATA_SAR_Msk = 0xffff + // Position of MEAS1_DONE_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_DONE_SAR_Pos = 0x10 + // Bit mask of MEAS1_DONE_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_DONE_SAR_Msk = 0x10000 + // Bit MEAS1_DONE_SAR. + SENS_SAR_MEAS1_CTRL2_MEAS1_DONE_SAR = 0x10000 + // Position of MEAS1_START_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_SAR_Pos = 0x11 + // Bit mask of MEAS1_START_SAR field. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_SAR_Msk = 0x20000 + // Bit MEAS1_START_SAR. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_SAR = 0x20000 + // Position of MEAS1_START_FORCE field. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_FORCE_Pos = 0x12 + // Bit mask of MEAS1_START_FORCE field. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_FORCE_Msk = 0x40000 + // Bit MEAS1_START_FORCE. + SENS_SAR_MEAS1_CTRL2_MEAS1_START_FORCE = 0x40000 + // Position of SAR1_EN_PAD field. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_Pos = 0x13 + // Bit mask of SAR1_EN_PAD field. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_Msk = 0x7ff80000 + // Position of SAR1_EN_PAD_FORCE field. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE_Pos = 0x1f + // Bit mask of SAR1_EN_PAD_FORCE field. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE_Msk = 0x80000000 + // Bit SAR1_EN_PAD_FORCE. + SENS_SAR_MEAS1_CTRL2_SAR1_EN_PAD_FORCE = 0x80000000 + + // SAR_MEAS1_MUX: configure saradc1 controller + // Position of SAR1_DIG_FORCE field. + SENS_SAR_MEAS1_MUX_SAR1_DIG_FORCE_Pos = 0x1f + // Bit mask of SAR1_DIG_FORCE field. + SENS_SAR_MEAS1_MUX_SAR1_DIG_FORCE_Msk = 0x80000000 + // Bit SAR1_DIG_FORCE. + SENS_SAR_MEAS1_MUX_SAR1_DIG_FORCE = 0x80000000 + + // SAR_ATTEN1: configure saradc1 controller + // Position of SAR1_ATTEN field. + SENS_SAR_ATTEN1_SAR1_ATTEN_Pos = 0x0 + // Bit mask of SAR1_ATTEN field. + SENS_SAR_ATTEN1_SAR1_ATTEN_Msk = 0xffffffff + + // SAR_AMP_CTRL1: no public + // Position of SAR_AMP_WAIT1 field. + SENS_SAR_AMP_CTRL1_SAR_AMP_WAIT1_Pos = 0x0 + // Bit mask of SAR_AMP_WAIT1 field. + SENS_SAR_AMP_CTRL1_SAR_AMP_WAIT1_Msk = 0xffff + // Position of SAR_AMP_WAIT2 field. + SENS_SAR_AMP_CTRL1_SAR_AMP_WAIT2_Pos = 0x10 + // Bit mask of SAR_AMP_WAIT2 field. + SENS_SAR_AMP_CTRL1_SAR_AMP_WAIT2_Msk = 0xffff0000 + + // SAR_AMP_CTRL2: no public + // Position of SAR_SAR1_DAC_XPD_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_SAR1_DAC_XPD_FSM_IDLE_Pos = 0x0 + // Bit mask of SAR_SAR1_DAC_XPD_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_SAR1_DAC_XPD_FSM_IDLE_Msk = 0x1 + // Bit SAR_SAR1_DAC_XPD_FSM_IDLE. + SENS_SAR_AMP_CTRL2_SAR_SAR1_DAC_XPD_FSM_IDLE = 0x1 + // Position of SAR_XPD_SAR_AMP_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_XPD_SAR_AMP_FSM_IDLE_Pos = 0x1 + // Bit mask of SAR_XPD_SAR_AMP_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_XPD_SAR_AMP_FSM_IDLE_Msk = 0x2 + // Bit SAR_XPD_SAR_AMP_FSM_IDLE. + SENS_SAR_AMP_CTRL2_SAR_XPD_SAR_AMP_FSM_IDLE = 0x2 + // Position of SAR_AMP_RST_FB_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_AMP_RST_FB_FSM_IDLE_Pos = 0x2 + // Bit mask of SAR_AMP_RST_FB_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_AMP_RST_FB_FSM_IDLE_Msk = 0x4 + // Bit SAR_AMP_RST_FB_FSM_IDLE. + SENS_SAR_AMP_CTRL2_SAR_AMP_RST_FB_FSM_IDLE = 0x4 + // Position of SAR_AMP_SHORT_REF_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_AMP_SHORT_REF_FSM_IDLE_Pos = 0x3 + // Bit mask of SAR_AMP_SHORT_REF_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_AMP_SHORT_REF_FSM_IDLE_Msk = 0x8 + // Bit SAR_AMP_SHORT_REF_FSM_IDLE. + SENS_SAR_AMP_CTRL2_SAR_AMP_SHORT_REF_FSM_IDLE = 0x8 + // Position of SAR_AMP_SHORT_REF_GND_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_AMP_SHORT_REF_GND_FSM_IDLE_Pos = 0x4 + // Bit mask of SAR_AMP_SHORT_REF_GND_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_AMP_SHORT_REF_GND_FSM_IDLE_Msk = 0x10 + // Bit SAR_AMP_SHORT_REF_GND_FSM_IDLE. + SENS_SAR_AMP_CTRL2_SAR_AMP_SHORT_REF_GND_FSM_IDLE = 0x10 + // Position of SAR_XPD_SAR_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_XPD_SAR_FSM_IDLE_Pos = 0x5 + // Bit mask of SAR_XPD_SAR_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_XPD_SAR_FSM_IDLE_Msk = 0x20 + // Bit SAR_XPD_SAR_FSM_IDLE. + SENS_SAR_AMP_CTRL2_SAR_XPD_SAR_FSM_IDLE = 0x20 + // Position of SAR_RSTB_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE_Pos = 0x6 + // Bit mask of SAR_RSTB_FSM_IDLE field. + SENS_SAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE_Msk = 0x40 + // Bit SAR_RSTB_FSM_IDLE. + SENS_SAR_AMP_CTRL2_SAR_RSTB_FSM_IDLE = 0x40 + // Position of SAR_AMP_WAIT3 field. + SENS_SAR_AMP_CTRL2_SAR_AMP_WAIT3_Pos = 0x10 + // Bit mask of SAR_AMP_WAIT3 field. + SENS_SAR_AMP_CTRL2_SAR_AMP_WAIT3_Msk = 0xffff0000 + + // SAR_AMP_CTRL3: no public + // Position of SAR1_DAC_XPD_FSM field. + SENS_SAR_AMP_CTRL3_SAR1_DAC_XPD_FSM_Pos = 0x0 + // Bit mask of SAR1_DAC_XPD_FSM field. + SENS_SAR_AMP_CTRL3_SAR1_DAC_XPD_FSM_Msk = 0xf + // Position of XPD_SAR_AMP_FSM field. + SENS_SAR_AMP_CTRL3_XPD_SAR_AMP_FSM_Pos = 0x4 + // Bit mask of XPD_SAR_AMP_FSM field. + SENS_SAR_AMP_CTRL3_XPD_SAR_AMP_FSM_Msk = 0xf0 + // Position of AMP_RST_FB_FSM field. + SENS_SAR_AMP_CTRL3_AMP_RST_FB_FSM_Pos = 0x8 + // Bit mask of AMP_RST_FB_FSM field. + SENS_SAR_AMP_CTRL3_AMP_RST_FB_FSM_Msk = 0xf00 + // Position of AMP_SHORT_REF_FSM field. + SENS_SAR_AMP_CTRL3_AMP_SHORT_REF_FSM_Pos = 0xc + // Bit mask of AMP_SHORT_REF_FSM field. + SENS_SAR_AMP_CTRL3_AMP_SHORT_REF_FSM_Msk = 0xf000 + // Position of AMP_SHORT_REF_GND_FSM field. + SENS_SAR_AMP_CTRL3_AMP_SHORT_REF_GND_FSM_Pos = 0x10 + // Bit mask of AMP_SHORT_REF_GND_FSM field. + SENS_SAR_AMP_CTRL3_AMP_SHORT_REF_GND_FSM_Msk = 0xf0000 + // Position of XPD_SAR_FSM field. + SENS_SAR_AMP_CTRL3_XPD_SAR_FSM_Pos = 0x14 + // Bit mask of XPD_SAR_FSM field. + SENS_SAR_AMP_CTRL3_XPD_SAR_FSM_Msk = 0xf00000 + // Position of RSTB_FSM field. + SENS_SAR_AMP_CTRL3_RSTB_FSM_Pos = 0x18 + // Bit mask of RSTB_FSM field. + SENS_SAR_AMP_CTRL3_RSTB_FSM_Msk = 0xf000000 + + // SAR_READER2_CTRL: configure saradc2 reader + // Position of SAR_SAR2_CLK_DIV field. + SENS_SAR_READER2_CTRL_SAR_SAR2_CLK_DIV_Pos = 0x0 + // Bit mask of SAR_SAR2_CLK_DIV field. + SENS_SAR_READER2_CTRL_SAR_SAR2_CLK_DIV_Msk = 0xff + // Position of SAR_SAR2_WAIT_ARB_CYCLE field. + SENS_SAR_READER2_CTRL_SAR_SAR2_WAIT_ARB_CYCLE_Pos = 0x10 + // Bit mask of SAR_SAR2_WAIT_ARB_CYCLE field. + SENS_SAR_READER2_CTRL_SAR_SAR2_WAIT_ARB_CYCLE_Msk = 0x30000 + // Position of SAR_SAR2_CLK_GATED field. + SENS_SAR_READER2_CTRL_SAR_SAR2_CLK_GATED_Pos = 0x12 + // Bit mask of SAR_SAR2_CLK_GATED field. + SENS_SAR_READER2_CTRL_SAR_SAR2_CLK_GATED_Msk = 0x40000 + // Bit SAR_SAR2_CLK_GATED. + SENS_SAR_READER2_CTRL_SAR_SAR2_CLK_GATED = 0x40000 + // Position of SAR_SAR2_SAMPLE_NUM field. + SENS_SAR_READER2_CTRL_SAR_SAR2_SAMPLE_NUM_Pos = 0x13 + // Bit mask of SAR_SAR2_SAMPLE_NUM field. + SENS_SAR_READER2_CTRL_SAR_SAR2_SAMPLE_NUM_Msk = 0x7f80000 + // Position of SAR_SAR2_DATA_INV field. + SENS_SAR_READER2_CTRL_SAR_SAR2_DATA_INV_Pos = 0x1d + // Bit mask of SAR_SAR2_DATA_INV field. + SENS_SAR_READER2_CTRL_SAR_SAR2_DATA_INV_Msk = 0x20000000 + // Bit SAR_SAR2_DATA_INV. + SENS_SAR_READER2_CTRL_SAR_SAR2_DATA_INV = 0x20000000 + // Position of SAR_SAR2_INT_EN field. + SENS_SAR_READER2_CTRL_SAR_SAR2_INT_EN_Pos = 0x1e + // Bit mask of SAR_SAR2_INT_EN field. + SENS_SAR_READER2_CTRL_SAR_SAR2_INT_EN_Msk = 0x40000000 + // Bit SAR_SAR2_INT_EN. + SENS_SAR_READER2_CTRL_SAR_SAR2_INT_EN = 0x40000000 + + // SAR_READER2_STATUS: get saradc1 reader controller status + // Position of SAR_SAR2_READER_STATUS field. + SENS_SAR_READER2_STATUS_SAR_SAR2_READER_STATUS_Pos = 0x0 + // Bit mask of SAR_SAR2_READER_STATUS field. + SENS_SAR_READER2_STATUS_SAR_SAR2_READER_STATUS_Msk = 0xffffffff + + // SAR_MEAS2_CTRL1: configure saradc2 controller + // Position of SAR_SAR2_CNTL_STATE field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_CNTL_STATE_Pos = 0x0 + // Bit mask of SAR_SAR2_CNTL_STATE field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_CNTL_STATE_Msk = 0x7 + // Position of SAR_SAR2_PWDET_CAL_EN field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_PWDET_CAL_EN_Pos = 0x3 + // Bit mask of SAR_SAR2_PWDET_CAL_EN field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_PWDET_CAL_EN_Msk = 0x8 + // Bit SAR_SAR2_PWDET_CAL_EN. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_PWDET_CAL_EN = 0x8 + // Position of SAR_SAR2_PKDET_CAL_EN field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_PKDET_CAL_EN_Pos = 0x4 + // Bit mask of SAR_SAR2_PKDET_CAL_EN field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_PKDET_CAL_EN_Msk = 0x10 + // Bit SAR_SAR2_PKDET_CAL_EN. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_PKDET_CAL_EN = 0x10 + // Position of SAR_SAR2_EN_TEST field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_EN_TEST_Pos = 0x5 + // Bit mask of SAR_SAR2_EN_TEST field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_EN_TEST_Msk = 0x20 + // Bit SAR_SAR2_EN_TEST. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_EN_TEST = 0x20 + // Position of SAR_SAR2_RSTB_FORCE field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_RSTB_FORCE_Pos = 0x6 + // Bit mask of SAR_SAR2_RSTB_FORCE field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_RSTB_FORCE_Msk = 0xc0 + // Position of SAR_SAR2_STANDBY_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_STANDBY_WAIT_Pos = 0x8 + // Bit mask of SAR_SAR2_STANDBY_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_STANDBY_WAIT_Msk = 0xff00 + // Position of SAR_SAR2_RSTB_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_RSTB_WAIT_Pos = 0x10 + // Bit mask of SAR_SAR2_RSTB_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_RSTB_WAIT_Msk = 0xff0000 + // Position of SAR_SAR2_XPD_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_XPD_WAIT_Pos = 0x18 + // Bit mask of SAR_SAR2_XPD_WAIT field. + SENS_SAR_MEAS2_CTRL1_SAR_SAR2_XPD_WAIT_Msk = 0xff000000 + + // SAR_MEAS2_CTRL2: configure saradc2 controller + // Position of MEAS2_DATA_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_DATA_SAR_Pos = 0x0 + // Bit mask of MEAS2_DATA_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_DATA_SAR_Msk = 0xffff + // Position of MEAS2_DONE_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_DONE_SAR_Pos = 0x10 + // Bit mask of MEAS2_DONE_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_DONE_SAR_Msk = 0x10000 + // Bit MEAS2_DONE_SAR. + SENS_SAR_MEAS2_CTRL2_MEAS2_DONE_SAR = 0x10000 + // Position of MEAS2_START_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_SAR_Pos = 0x11 + // Bit mask of MEAS2_START_SAR field. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_SAR_Msk = 0x20000 + // Bit MEAS2_START_SAR. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_SAR = 0x20000 + // Position of MEAS2_START_FORCE field. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_FORCE_Pos = 0x12 + // Bit mask of MEAS2_START_FORCE field. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_FORCE_Msk = 0x40000 + // Bit MEAS2_START_FORCE. + SENS_SAR_MEAS2_CTRL2_MEAS2_START_FORCE = 0x40000 + // Position of SAR2_EN_PAD field. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_Pos = 0x13 + // Bit mask of SAR2_EN_PAD field. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_Msk = 0x7ff80000 + // Position of SAR2_EN_PAD_FORCE field. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE_Pos = 0x1f + // Bit mask of SAR2_EN_PAD_FORCE field. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE_Msk = 0x80000000 + // Bit SAR2_EN_PAD_FORCE. + SENS_SAR_MEAS2_CTRL2_SAR2_EN_PAD_FORCE = 0x80000000 + + // SAR_MEAS2_MUX: configure saradc2 controller + // Position of SAR2_PWDET_CCT field. + SENS_SAR_MEAS2_MUX_SAR2_PWDET_CCT_Pos = 0x1c + // Bit mask of SAR2_PWDET_CCT field. + SENS_SAR_MEAS2_MUX_SAR2_PWDET_CCT_Msk = 0x70000000 + // Position of SAR2_RTC_FORCE field. + SENS_SAR_MEAS2_MUX_SAR2_RTC_FORCE_Pos = 0x1f + // Bit mask of SAR2_RTC_FORCE field. + SENS_SAR_MEAS2_MUX_SAR2_RTC_FORCE_Msk = 0x80000000 + // Bit SAR2_RTC_FORCE. + SENS_SAR_MEAS2_MUX_SAR2_RTC_FORCE = 0x80000000 + + // SAR_ATTEN2: configure saradc2 controller + // Position of SAR2_ATTEN field. + SENS_SAR_ATTEN2_SAR2_ATTEN_Pos = 0x0 + // Bit mask of SAR2_ATTEN field. + SENS_SAR_ATTEN2_SAR2_ATTEN_Msk = 0xffffffff + + // SAR_POWER_XPD_SAR: configure power of saradc + // Position of FORCE_XPD_SAR field. + SENS_SAR_POWER_XPD_SAR_FORCE_XPD_SAR_Pos = 0x1d + // Bit mask of FORCE_XPD_SAR field. + SENS_SAR_POWER_XPD_SAR_FORCE_XPD_SAR_Msk = 0x60000000 + // Position of SARCLK_EN field. + SENS_SAR_POWER_XPD_SAR_SARCLK_EN_Pos = 0x1f + // Bit mask of SARCLK_EN field. + SENS_SAR_POWER_XPD_SAR_SARCLK_EN_Msk = 0x80000000 + // Bit SARCLK_EN. + SENS_SAR_POWER_XPD_SAR_SARCLK_EN = 0x80000000 + + // SAR_SLAVE_ADDR1: configure i2c slave address + // Position of SAR_I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR1_Pos = 0x0 + // Bit mask of SAR_I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR1_Msk = 0x7ff + // Position of SAR_I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR0_Pos = 0xb + // Bit mask of SAR_I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR0_Msk = 0x3ff800 + // Position of SAR_SARADC_MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_SAR_SARADC_MEAS_STATUS_Pos = 0x16 + // Bit mask of SAR_SARADC_MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_SAR_SARADC_MEAS_STATUS_Msk = 0x3fc00000 + + // SAR_SLAVE_ADDR2: configure i2c slave address + // Position of SAR_I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR3_Pos = 0x0 + // Bit mask of SAR_I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR3_Msk = 0x7ff + // Position of SAR_I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR2_Pos = 0xb + // Bit mask of SAR_I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR2_Msk = 0x3ff800 + + // SAR_SLAVE_ADDR3: configure i2c slave address + // Position of SAR_I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR5_Pos = 0x0 + // Bit mask of SAR_I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR5_Msk = 0x7ff + // Position of SAR_I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR4_Pos = 0xb + // Bit mask of SAR_I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR4_Msk = 0x3ff800 + + // SAR_SLAVE_ADDR4: configure i2c slave address + // Position of SAR_I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR7_Pos = 0x0 + // Bit mask of SAR_I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR7_Msk = 0x7ff + // Position of SAR_I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR6_Pos = 0xb + // Bit mask of SAR_I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR6_Msk = 0x3ff800 + + // SAR_TSENS_CTRL: configure tsens controller + // Position of SAR_TSENS_OUT field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_OUT_Pos = 0x0 + // Bit mask of SAR_TSENS_OUT field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_OUT_Msk = 0xff + // Position of SAR_TSENS_READY field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_READY_Pos = 0x8 + // Bit mask of SAR_TSENS_READY field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_READY_Msk = 0x100 + // Bit SAR_TSENS_READY. + SENS_SAR_TSENS_CTRL_SAR_TSENS_READY = 0x100 + // Position of SAR_TSENS_INT_EN field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_INT_EN_Pos = 0xc + // Bit mask of SAR_TSENS_INT_EN field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_INT_EN_Msk = 0x1000 + // Bit SAR_TSENS_INT_EN. + SENS_SAR_TSENS_CTRL_SAR_TSENS_INT_EN = 0x1000 + // Position of SAR_TSENS_IN_INV field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_IN_INV_Pos = 0xd + // Bit mask of SAR_TSENS_IN_INV field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_IN_INV_Msk = 0x2000 + // Bit SAR_TSENS_IN_INV. + SENS_SAR_TSENS_CTRL_SAR_TSENS_IN_INV = 0x2000 + // Position of SAR_TSENS_CLK_DIV field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_CLK_DIV_Pos = 0xe + // Bit mask of SAR_TSENS_CLK_DIV field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_CLK_DIV_Msk = 0x3fc000 + // Position of SAR_TSENS_POWER_UP field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_POWER_UP_Pos = 0x16 + // Bit mask of SAR_TSENS_POWER_UP field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_POWER_UP_Msk = 0x400000 + // Bit SAR_TSENS_POWER_UP. + SENS_SAR_TSENS_CTRL_SAR_TSENS_POWER_UP = 0x400000 + // Position of SAR_TSENS_POWER_UP_FORCE field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_POWER_UP_FORCE_Pos = 0x17 + // Bit mask of SAR_TSENS_POWER_UP_FORCE field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_POWER_UP_FORCE_Msk = 0x800000 + // Bit SAR_TSENS_POWER_UP_FORCE. + SENS_SAR_TSENS_CTRL_SAR_TSENS_POWER_UP_FORCE = 0x800000 + // Position of SAR_TSENS_DUMP_OUT field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_DUMP_OUT_Pos = 0x18 + // Bit mask of SAR_TSENS_DUMP_OUT field. + SENS_SAR_TSENS_CTRL_SAR_TSENS_DUMP_OUT_Msk = 0x1000000 + // Bit SAR_TSENS_DUMP_OUT. + SENS_SAR_TSENS_CTRL_SAR_TSENS_DUMP_OUT = 0x1000000 + + // SAR_TSENS_CTRL2: configure tsens controller + // Position of SAR_TSENS_XPD_WAIT field. + SENS_SAR_TSENS_CTRL2_SAR_TSENS_XPD_WAIT_Pos = 0x0 + // Bit mask of SAR_TSENS_XPD_WAIT field. + SENS_SAR_TSENS_CTRL2_SAR_TSENS_XPD_WAIT_Msk = 0xfff + // Position of SAR_TSENS_XPD_FORCE field. + SENS_SAR_TSENS_CTRL2_SAR_TSENS_XPD_FORCE_Pos = 0xc + // Bit mask of SAR_TSENS_XPD_FORCE field. + SENS_SAR_TSENS_CTRL2_SAR_TSENS_XPD_FORCE_Msk = 0x3000 + // Position of SAR_TSENS_CLK_INV field. + SENS_SAR_TSENS_CTRL2_SAR_TSENS_CLK_INV_Pos = 0xe + // Bit mask of SAR_TSENS_CLK_INV field. + SENS_SAR_TSENS_CTRL2_SAR_TSENS_CLK_INV_Msk = 0x4000 + // Bit SAR_TSENS_CLK_INV. + SENS_SAR_TSENS_CTRL2_SAR_TSENS_CLK_INV = 0x4000 + + // SAR_I2C_CTRL: configure rtc i2c controller by sw + // Position of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Pos = 0x0 + // Bit mask of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Msk = 0xfffffff + // Position of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Pos = 0x1c + // Bit mask of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Msk = 0x10000000 + // Bit SAR_I2C_START. + SENS_SAR_I2C_CTRL_SAR_I2C_START = 0x10000000 + // Position of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Pos = 0x1d + // Bit mask of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Msk = 0x20000000 + // Bit SAR_I2C_START_FORCE. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE = 0x20000000 + + // SAR_TOUCH_CONF: configure touch controller + // Position of SAR_TOUCH_OUTEN field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_OUTEN_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUTEN field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_OUTEN_Msk = 0x7fff + // Position of SAR_TOUCH_STATUS_CLR field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_STATUS_CLR_Pos = 0xf + // Bit mask of SAR_TOUCH_STATUS_CLR field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_STATUS_CLR_Msk = 0x8000 + // Bit SAR_TOUCH_STATUS_CLR. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_STATUS_CLR = 0x8000 + // Position of SAR_TOUCH_DATA_SEL field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_DATA_SEL_Pos = 0x10 + // Bit mask of SAR_TOUCH_DATA_SEL field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_DATA_SEL_Msk = 0x30000 + // Position of SAR_TOUCH_DENOISE_END field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_DENOISE_END_Pos = 0x12 + // Bit mask of SAR_TOUCH_DENOISE_END field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_DENOISE_END_Msk = 0x40000 + // Bit SAR_TOUCH_DENOISE_END. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_DENOISE_END = 0x40000 + // Position of SAR_TOUCH_UNIT_END field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_UNIT_END_Pos = 0x13 + // Bit mask of SAR_TOUCH_UNIT_END field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_UNIT_END_Msk = 0x80000 + // Bit SAR_TOUCH_UNIT_END. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_UNIT_END = 0x80000 + // Position of SAR_TOUCH_APPROACH_PAD2 field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD2_Pos = 0x14 + // Bit mask of SAR_TOUCH_APPROACH_PAD2 field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD2_Msk = 0xf00000 + // Position of SAR_TOUCH_APPROACH_PAD1 field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD1_Pos = 0x18 + // Bit mask of SAR_TOUCH_APPROACH_PAD1 field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD1_Msk = 0xf000000 + // Position of SAR_TOUCH_APPROACH_PAD0 field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD0_Pos = 0x1c + // Bit mask of SAR_TOUCH_APPROACH_PAD0 field. + SENS_SAR_TOUCH_CONF_SAR_TOUCH_APPROACH_PAD0_Msk = 0xf0000000 + + // SAR_TOUCH_DENOISE: configure touch controller + // Position of DATA field. + SENS_SAR_TOUCH_DENOISE_DATA_Pos = 0x0 + // Bit mask of DATA field. + SENS_SAR_TOUCH_DENOISE_DATA_Msk = 0x3fffff + + // SAR_TOUCH_THRES1: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH1 field. + SENS_SAR_TOUCH_THRES1_SAR_TOUCH_OUT_TH1_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH1 field. + SENS_SAR_TOUCH_THRES1_SAR_TOUCH_OUT_TH1_Msk = 0x3fffff + + // SAR_TOUCH_THRES2: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH2 field. + SENS_SAR_TOUCH_THRES2_SAR_TOUCH_OUT_TH2_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH2 field. + SENS_SAR_TOUCH_THRES2_SAR_TOUCH_OUT_TH2_Msk = 0x3fffff + + // SAR_TOUCH_THRES3: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH3 field. + SENS_SAR_TOUCH_THRES3_SAR_TOUCH_OUT_TH3_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH3 field. + SENS_SAR_TOUCH_THRES3_SAR_TOUCH_OUT_TH3_Msk = 0x3fffff + + // SAR_TOUCH_THRES4: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH4 field. + SENS_SAR_TOUCH_THRES4_SAR_TOUCH_OUT_TH4_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH4 field. + SENS_SAR_TOUCH_THRES4_SAR_TOUCH_OUT_TH4_Msk = 0x3fffff + + // SAR_TOUCH_THRES5: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH5 field. + SENS_SAR_TOUCH_THRES5_SAR_TOUCH_OUT_TH5_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH5 field. + SENS_SAR_TOUCH_THRES5_SAR_TOUCH_OUT_TH5_Msk = 0x3fffff + + // SAR_TOUCH_THRES6: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH6 field. + SENS_SAR_TOUCH_THRES6_SAR_TOUCH_OUT_TH6_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH6 field. + SENS_SAR_TOUCH_THRES6_SAR_TOUCH_OUT_TH6_Msk = 0x3fffff + + // SAR_TOUCH_THRES7: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH7 field. + SENS_SAR_TOUCH_THRES7_SAR_TOUCH_OUT_TH7_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH7 field. + SENS_SAR_TOUCH_THRES7_SAR_TOUCH_OUT_TH7_Msk = 0x3fffff + + // SAR_TOUCH_THRES8: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH8 field. + SENS_SAR_TOUCH_THRES8_SAR_TOUCH_OUT_TH8_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH8 field. + SENS_SAR_TOUCH_THRES8_SAR_TOUCH_OUT_TH8_Msk = 0x3fffff + + // SAR_TOUCH_THRES9: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH9 field. + SENS_SAR_TOUCH_THRES9_SAR_TOUCH_OUT_TH9_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH9 field. + SENS_SAR_TOUCH_THRES9_SAR_TOUCH_OUT_TH9_Msk = 0x3fffff + + // SAR_TOUCH_THRES10: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH10 field. + SENS_SAR_TOUCH_THRES10_SAR_TOUCH_OUT_TH10_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH10 field. + SENS_SAR_TOUCH_THRES10_SAR_TOUCH_OUT_TH10_Msk = 0x3fffff + + // SAR_TOUCH_THRES11: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH11 field. + SENS_SAR_TOUCH_THRES11_SAR_TOUCH_OUT_TH11_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH11 field. + SENS_SAR_TOUCH_THRES11_SAR_TOUCH_OUT_TH11_Msk = 0x3fffff + + // SAR_TOUCH_THRES12: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH12 field. + SENS_SAR_TOUCH_THRES12_SAR_TOUCH_OUT_TH12_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH12 field. + SENS_SAR_TOUCH_THRES12_SAR_TOUCH_OUT_TH12_Msk = 0x3fffff + + // SAR_TOUCH_THRES13: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH13 field. + SENS_SAR_TOUCH_THRES13_SAR_TOUCH_OUT_TH13_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH13 field. + SENS_SAR_TOUCH_THRES13_SAR_TOUCH_OUT_TH13_Msk = 0x3fffff + + // SAR_TOUCH_THRES14: configure touch thres of touch pad + // Position of SAR_TOUCH_OUT_TH14 field. + SENS_SAR_TOUCH_THRES14_SAR_TOUCH_OUT_TH14_Pos = 0x0 + // Bit mask of SAR_TOUCH_OUT_TH14 field. + SENS_SAR_TOUCH_THRES14_SAR_TOUCH_OUT_TH14_Msk = 0x3fffff + + // SAR_TOUCH_CHN_ST: Get touch channel status + // Position of SAR_TOUCH_PAD_ACTIVE field. + SENS_SAR_TOUCH_CHN_ST_SAR_TOUCH_PAD_ACTIVE_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD_ACTIVE field. + SENS_SAR_TOUCH_CHN_ST_SAR_TOUCH_PAD_ACTIVE_Msk = 0x7fff + // Position of SAR_TOUCH_CHANNEL_CLR field. + SENS_SAR_TOUCH_CHN_ST_SAR_TOUCH_CHANNEL_CLR_Pos = 0xf + // Bit mask of SAR_TOUCH_CHANNEL_CLR field. + SENS_SAR_TOUCH_CHN_ST_SAR_TOUCH_CHANNEL_CLR_Msk = 0x3fff8000 + // Position of SAR_TOUCH_MEAS_DONE field. + SENS_SAR_TOUCH_CHN_ST_SAR_TOUCH_MEAS_DONE_Pos = 0x1f + // Bit mask of SAR_TOUCH_MEAS_DONE field. + SENS_SAR_TOUCH_CHN_ST_SAR_TOUCH_MEAS_DONE_Msk = 0x80000000 + // Bit SAR_TOUCH_MEAS_DONE. + SENS_SAR_TOUCH_CHN_ST_SAR_TOUCH_MEAS_DONE = 0x80000000 + + // SAR_TOUCH_STATUS0: get touch scan status + // Position of SAR_TOUCH_SCAN_CURR field. + SENS_SAR_TOUCH_STATUS0_SAR_TOUCH_SCAN_CURR_Pos = 0x16 + // Bit mask of SAR_TOUCH_SCAN_CURR field. + SENS_SAR_TOUCH_STATUS0_SAR_TOUCH_SCAN_CURR_Msk = 0x3c00000 + + // SAR_TOUCH_STATUS1: touch channel status of touch pad 1 + // Position of SAR_TOUCH_PAD1_DATA field. + SENS_SAR_TOUCH_STATUS1_SAR_TOUCH_PAD1_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD1_DATA field. + SENS_SAR_TOUCH_STATUS1_SAR_TOUCH_PAD1_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD1_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS1_SAR_TOUCH_PAD1_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD1_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS1_SAR_TOUCH_PAD1_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS2: touch channel status of touch pad 2 + // Position of SAR_TOUCH_PAD2_DATA field. + SENS_SAR_TOUCH_STATUS2_SAR_TOUCH_PAD2_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD2_DATA field. + SENS_SAR_TOUCH_STATUS2_SAR_TOUCH_PAD2_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD2_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS2_SAR_TOUCH_PAD2_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD2_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS2_SAR_TOUCH_PAD2_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS3: touch channel status of touch pad 3 + // Position of SAR_TOUCH_PAD3_DATA field. + SENS_SAR_TOUCH_STATUS3_SAR_TOUCH_PAD3_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD3_DATA field. + SENS_SAR_TOUCH_STATUS3_SAR_TOUCH_PAD3_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD3_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS3_SAR_TOUCH_PAD3_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD3_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS3_SAR_TOUCH_PAD3_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS4: touch channel status of touch pad 4 + // Position of SAR_TOUCH_PAD4_DATA field. + SENS_SAR_TOUCH_STATUS4_SAR_TOUCH_PAD4_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD4_DATA field. + SENS_SAR_TOUCH_STATUS4_SAR_TOUCH_PAD4_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD4_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS4_SAR_TOUCH_PAD4_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD4_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS4_SAR_TOUCH_PAD4_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS5: touch channel status of touch pad 5 + // Position of SAR_TOUCH_PAD5_DATA field. + SENS_SAR_TOUCH_STATUS5_SAR_TOUCH_PAD5_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD5_DATA field. + SENS_SAR_TOUCH_STATUS5_SAR_TOUCH_PAD5_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD5_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS5_SAR_TOUCH_PAD5_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD5_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS5_SAR_TOUCH_PAD5_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS6: touch channel status of touch pad 6 + // Position of SAR_TOUCH_PAD6_DATA field. + SENS_SAR_TOUCH_STATUS6_SAR_TOUCH_PAD6_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD6_DATA field. + SENS_SAR_TOUCH_STATUS6_SAR_TOUCH_PAD6_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD6_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS6_SAR_TOUCH_PAD6_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD6_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS6_SAR_TOUCH_PAD6_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS7: touch channel status of touch pad 7 + // Position of SAR_TOUCH_PAD7_DATA field. + SENS_SAR_TOUCH_STATUS7_SAR_TOUCH_PAD7_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD7_DATA field. + SENS_SAR_TOUCH_STATUS7_SAR_TOUCH_PAD7_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD7_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS7_SAR_TOUCH_PAD7_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD7_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS7_SAR_TOUCH_PAD7_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS8: touch channel status of touch pad 8 + // Position of SAR_TOUCH_PAD8_DATA field. + SENS_SAR_TOUCH_STATUS8_SAR_TOUCH_PAD8_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD8_DATA field. + SENS_SAR_TOUCH_STATUS8_SAR_TOUCH_PAD8_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD8_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS8_SAR_TOUCH_PAD8_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD8_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS8_SAR_TOUCH_PAD8_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS9: touch channel status of touch pad 9 + // Position of SAR_TOUCH_PAD9_DATA field. + SENS_SAR_TOUCH_STATUS9_SAR_TOUCH_PAD9_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD9_DATA field. + SENS_SAR_TOUCH_STATUS9_SAR_TOUCH_PAD9_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD9_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS9_SAR_TOUCH_PAD9_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD9_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS9_SAR_TOUCH_PAD9_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS10: touch channel status of touch pad 10 + // Position of SAR_TOUCH_PAD10_DATA field. + SENS_SAR_TOUCH_STATUS10_SAR_TOUCH_PAD10_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD10_DATA field. + SENS_SAR_TOUCH_STATUS10_SAR_TOUCH_PAD10_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD10_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS10_SAR_TOUCH_PAD10_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD10_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS10_SAR_TOUCH_PAD10_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS11: touch channel status of touch pad 11 + // Position of SAR_TOUCH_PAD11_DATA field. + SENS_SAR_TOUCH_STATUS11_SAR_TOUCH_PAD11_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD11_DATA field. + SENS_SAR_TOUCH_STATUS11_SAR_TOUCH_PAD11_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD11_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS11_SAR_TOUCH_PAD11_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD11_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS11_SAR_TOUCH_PAD11_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS12: touch channel status of touch pad 12 + // Position of SAR_TOUCH_PAD12_DATA field. + SENS_SAR_TOUCH_STATUS12_SAR_TOUCH_PAD12_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD12_DATA field. + SENS_SAR_TOUCH_STATUS12_SAR_TOUCH_PAD12_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD12_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS12_SAR_TOUCH_PAD12_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD12_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS12_SAR_TOUCH_PAD12_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS13: touch channel status of touch pad 13 + // Position of SAR_TOUCH_PAD13_DATA field. + SENS_SAR_TOUCH_STATUS13_SAR_TOUCH_PAD13_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD13_DATA field. + SENS_SAR_TOUCH_STATUS13_SAR_TOUCH_PAD13_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD13_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS13_SAR_TOUCH_PAD13_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD13_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS13_SAR_TOUCH_PAD13_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS14: touch channel status of touch pad 14 + // Position of SAR_TOUCH_PAD14_DATA field. + SENS_SAR_TOUCH_STATUS14_SAR_TOUCH_PAD14_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_PAD14_DATA field. + SENS_SAR_TOUCH_STATUS14_SAR_TOUCH_PAD14_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_PAD14_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS14_SAR_TOUCH_PAD14_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_PAD14_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS14_SAR_TOUCH_PAD14_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS15: touch channel status of sleep pad + // Position of SAR_TOUCH_SLP_DATA field. + SENS_SAR_TOUCH_STATUS15_SAR_TOUCH_SLP_DATA_Pos = 0x0 + // Bit mask of SAR_TOUCH_SLP_DATA field. + SENS_SAR_TOUCH_STATUS15_SAR_TOUCH_SLP_DATA_Msk = 0x3fffff + // Position of SAR_TOUCH_SLP_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS15_SAR_TOUCH_SLP_DEBOUNCE_Pos = 0x1d + // Bit mask of SAR_TOUCH_SLP_DEBOUNCE field. + SENS_SAR_TOUCH_STATUS15_SAR_TOUCH_SLP_DEBOUNCE_Msk = 0xe0000000 + + // SAR_TOUCH_STATUS16: touch channel status of approach mode + // Position of SAR_TOUCH_APPROACH_PAD2_CNT field. + SENS_SAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD2_CNT_Pos = 0x0 + // Bit mask of SAR_TOUCH_APPROACH_PAD2_CNT field. + SENS_SAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD2_CNT_Msk = 0xff + // Position of SAR_TOUCH_APPROACH_PAD1_CNT field. + SENS_SAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD1_CNT_Pos = 0x8 + // Bit mask of SAR_TOUCH_APPROACH_PAD1_CNT field. + SENS_SAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD1_CNT_Msk = 0xff00 + // Position of SAR_TOUCH_APPROACH_PAD0_CNT field. + SENS_SAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD0_CNT_Pos = 0x10 + // Bit mask of SAR_TOUCH_APPROACH_PAD0_CNT field. + SENS_SAR_TOUCH_STATUS16_SAR_TOUCH_APPROACH_PAD0_CNT_Msk = 0xff0000 + // Position of SAR_TOUCH_SLP_APPROACH_CNT field. + SENS_SAR_TOUCH_STATUS16_SAR_TOUCH_SLP_APPROACH_CNT_Pos = 0x18 + // Bit mask of SAR_TOUCH_SLP_APPROACH_CNT field. + SENS_SAR_TOUCH_STATUS16_SAR_TOUCH_SLP_APPROACH_CNT_Msk = 0xff000000 + + // SAR_COCPU_STATE: get cocpu status + // Position of SAR_COCPU_DBG_TRIGGER field. + SENS_SAR_COCPU_STATE_SAR_COCPU_DBG_TRIGGER_Pos = 0x19 + // Bit mask of SAR_COCPU_DBG_TRIGGER field. + SENS_SAR_COCPU_STATE_SAR_COCPU_DBG_TRIGGER_Msk = 0x2000000 + // Bit SAR_COCPU_DBG_TRIGGER. + SENS_SAR_COCPU_STATE_SAR_COCPU_DBG_TRIGGER = 0x2000000 + // Position of SAR_COCPU_CLK_EN_ST field. + SENS_SAR_COCPU_STATE_SAR_COCPU_CLK_EN_ST_Pos = 0x1a + // Bit mask of SAR_COCPU_CLK_EN_ST field. + SENS_SAR_COCPU_STATE_SAR_COCPU_CLK_EN_ST_Msk = 0x4000000 + // Bit SAR_COCPU_CLK_EN_ST. + SENS_SAR_COCPU_STATE_SAR_COCPU_CLK_EN_ST = 0x4000000 + // Position of SAR_COCPU_RESET_N field. + SENS_SAR_COCPU_STATE_SAR_COCPU_RESET_N_Pos = 0x1b + // Bit mask of SAR_COCPU_RESET_N field. + SENS_SAR_COCPU_STATE_SAR_COCPU_RESET_N_Msk = 0x8000000 + // Bit SAR_COCPU_RESET_N. + SENS_SAR_COCPU_STATE_SAR_COCPU_RESET_N = 0x8000000 + // Position of SAR_COCPU_EOI field. + SENS_SAR_COCPU_STATE_SAR_COCPU_EOI_Pos = 0x1c + // Bit mask of SAR_COCPU_EOI field. + SENS_SAR_COCPU_STATE_SAR_COCPU_EOI_Msk = 0x10000000 + // Bit SAR_COCPU_EOI. + SENS_SAR_COCPU_STATE_SAR_COCPU_EOI = 0x10000000 + // Position of SAR_COCPU_TRAP field. + SENS_SAR_COCPU_STATE_SAR_COCPU_TRAP_Pos = 0x1d + // Bit mask of SAR_COCPU_TRAP field. + SENS_SAR_COCPU_STATE_SAR_COCPU_TRAP_Msk = 0x20000000 + // Bit SAR_COCPU_TRAP. + SENS_SAR_COCPU_STATE_SAR_COCPU_TRAP = 0x20000000 + // Position of SAR_COCPU_EBREAK field. + SENS_SAR_COCPU_STATE_SAR_COCPU_EBREAK_Pos = 0x1e + // Bit mask of SAR_COCPU_EBREAK field. + SENS_SAR_COCPU_STATE_SAR_COCPU_EBREAK_Msk = 0x40000000 + // Bit SAR_COCPU_EBREAK. + SENS_SAR_COCPU_STATE_SAR_COCPU_EBREAK = 0x40000000 + + // SAR_COCPU_INT_RAW: the interrupt raw of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW = 0x4 + // Position of SAR_COCPU_SARADC1_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW = 0x8 + // Position of SAR_COCPU_SARADC2_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW = 0x10 + // Position of SAR_COCPU_TSENS_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW = 0x20 + // Position of SAR_COCPU_START_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW_Msk = 0x40 + // Bit SAR_COCPU_START_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW = 0x40 + // Position of SAR_COCPU_SW_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW = 0x80 + // Position of SAR_COCPU_SWD_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW = 0x800 + + // SAR_COCPU_INT_ENA: the interrupt enable of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA = 0x4 + // Position of SAR_COCPU_SARADC1_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA = 0x8 + // Position of SAR_COCPU_SARADC2_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA = 0x10 + // Position of SAR_COCPU_TSENS_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA = 0x20 + // Position of SAR_COCPU_START_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA_Msk = 0x40 + // Bit SAR_COCPU_START_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA = 0x40 + // Position of SAR_COCPU_SW_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA = 0x80 + // Position of SAR_COCPU_SWD_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA = 0x800 + + // SAR_COCPU_INT_ST: the interrupt state of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST = 0x4 + // Position of SAR_COCPU_SARADC1_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST = 0x8 + // Position of SAR_COCPU_SARADC2_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST = 0x10 + // Position of SAR_COCPU_TSENS_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST = 0x20 + // Position of SAR_COCPU_START_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST_Msk = 0x40 + // Bit SAR_COCPU_START_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST = 0x40 + // Position of SAR_COCPU_SW_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST = 0x80 + // Position of SAR_COCPU_SWD_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST = 0x800 + + // SAR_COCPU_INT_CLR: the interrupt clear of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR = 0x4 + // Position of SAR_COCPU_SARADC1_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR = 0x8 + // Position of SAR_COCPU_SARADC2_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR = 0x10 + // Position of SAR_COCPU_TSENS_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR = 0x20 + // Position of SAR_COCPU_START_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR_Msk = 0x40 + // Bit SAR_COCPU_START_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR = 0x40 + // Position of SAR_COCPU_SW_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR = 0x80 + // Position of SAR_COCPU_SWD_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR = 0x800 + + // SAR_COCPU_DEBUG: Ulp-riscv debug signal + // Position of SAR_COCPU_PC field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_PC_Pos = 0x0 + // Bit mask of SAR_COCPU_PC field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_PC_Msk = 0x1fff + // Position of SAR_COCPU_MEM_VLD field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_VLD_Pos = 0xd + // Bit mask of SAR_COCPU_MEM_VLD field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_VLD_Msk = 0x2000 + // Bit SAR_COCPU_MEM_VLD. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_VLD = 0x2000 + // Position of SAR_COCPU_MEM_RDY field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_RDY_Pos = 0xe + // Bit mask of SAR_COCPU_MEM_RDY field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_RDY_Msk = 0x4000 + // Bit SAR_COCPU_MEM_RDY. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_RDY = 0x4000 + // Position of SAR_COCPU_MEM_WEN field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_WEN_Pos = 0xf + // Bit mask of SAR_COCPU_MEM_WEN field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_WEN_Msk = 0x78000 + // Position of SAR_COCPU_MEM_ADDR field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_ADDR_Pos = 0x13 + // Bit mask of SAR_COCPU_MEM_ADDR field. + SENS_SAR_COCPU_DEBUG_SAR_COCPU_MEM_ADDR_Msk = 0xfff80000 + + // SAR_HALL_CTRL: no public + // Position of XPD_HALL field. + SENS_SAR_HALL_CTRL_XPD_HALL_Pos = 0x1c + // Bit mask of XPD_HALL field. + SENS_SAR_HALL_CTRL_XPD_HALL_Msk = 0x10000000 + // Bit XPD_HALL. + SENS_SAR_HALL_CTRL_XPD_HALL = 0x10000000 + // Position of XPD_HALL_FORCE field. + SENS_SAR_HALL_CTRL_XPD_HALL_FORCE_Pos = 0x1d + // Bit mask of XPD_HALL_FORCE field. + SENS_SAR_HALL_CTRL_XPD_HALL_FORCE_Msk = 0x20000000 + // Bit XPD_HALL_FORCE. + SENS_SAR_HALL_CTRL_XPD_HALL_FORCE = 0x20000000 + // Position of HALL_PHASE field. + SENS_SAR_HALL_CTRL_HALL_PHASE_Pos = 0x1e + // Bit mask of HALL_PHASE field. + SENS_SAR_HALL_CTRL_HALL_PHASE_Msk = 0x40000000 + // Bit HALL_PHASE. + SENS_SAR_HALL_CTRL_HALL_PHASE = 0x40000000 + // Position of HALL_PHASE_FORCE field. + SENS_SAR_HALL_CTRL_HALL_PHASE_FORCE_Pos = 0x1f + // Bit mask of HALL_PHASE_FORCE field. + SENS_SAR_HALL_CTRL_HALL_PHASE_FORCE_Msk = 0x80000000 + // Bit HALL_PHASE_FORCE. + SENS_SAR_HALL_CTRL_HALL_PHASE_FORCE = 0x80000000 + + // SAR_NOUSE: no public + // Position of SAR_NOUSE field. + SENS_SAR_NOUSE_SAR_NOUSE_Pos = 0x0 + // Bit mask of SAR_NOUSE field. + SENS_SAR_NOUSE_SAR_NOUSE_Msk = 0xffffffff + + // SAR_PERI_CLK_GATE_CONF: the peri clock gate of rtc peri + // Position of RTC_I2C_CLK_EN field. + SENS_SAR_PERI_CLK_GATE_CONF_RTC_I2C_CLK_EN_Pos = 0x1b + // Bit mask of RTC_I2C_CLK_EN field. + SENS_SAR_PERI_CLK_GATE_CONF_RTC_I2C_CLK_EN_Msk = 0x8000000 + // Bit RTC_I2C_CLK_EN. + SENS_SAR_PERI_CLK_GATE_CONF_RTC_I2C_CLK_EN = 0x8000000 + // Position of TSENS_CLK_EN field. + SENS_SAR_PERI_CLK_GATE_CONF_TSENS_CLK_EN_Pos = 0x1d + // Bit mask of TSENS_CLK_EN field. + SENS_SAR_PERI_CLK_GATE_CONF_TSENS_CLK_EN_Msk = 0x20000000 + // Bit TSENS_CLK_EN. + SENS_SAR_PERI_CLK_GATE_CONF_TSENS_CLK_EN = 0x20000000 + // Position of SARADC_CLK_EN field. + SENS_SAR_PERI_CLK_GATE_CONF_SARADC_CLK_EN_Pos = 0x1e + // Bit mask of SARADC_CLK_EN field. + SENS_SAR_PERI_CLK_GATE_CONF_SARADC_CLK_EN_Msk = 0x40000000 + // Bit SARADC_CLK_EN. + SENS_SAR_PERI_CLK_GATE_CONF_SARADC_CLK_EN = 0x40000000 + // Position of IOMUX_CLK_EN field. + SENS_SAR_PERI_CLK_GATE_CONF_IOMUX_CLK_EN_Pos = 0x1f + // Bit mask of IOMUX_CLK_EN field. + SENS_SAR_PERI_CLK_GATE_CONF_IOMUX_CLK_EN_Msk = 0x80000000 + // Bit IOMUX_CLK_EN. + SENS_SAR_PERI_CLK_GATE_CONF_IOMUX_CLK_EN = 0x80000000 + + // SAR_PERI_RESET_CONF: the peri reset of rtc peri + // Position of SAR_COCPU_RESET field. + SENS_SAR_PERI_RESET_CONF_SAR_COCPU_RESET_Pos = 0x19 + // Bit mask of SAR_COCPU_RESET field. + SENS_SAR_PERI_RESET_CONF_SAR_COCPU_RESET_Msk = 0x2000000 + // Bit SAR_COCPU_RESET. + SENS_SAR_PERI_RESET_CONF_SAR_COCPU_RESET = 0x2000000 + // Position of SAR_RTC_I2C_RESET field. + SENS_SAR_PERI_RESET_CONF_SAR_RTC_I2C_RESET_Pos = 0x1b + // Bit mask of SAR_RTC_I2C_RESET field. + SENS_SAR_PERI_RESET_CONF_SAR_RTC_I2C_RESET_Msk = 0x8000000 + // Bit SAR_RTC_I2C_RESET. + SENS_SAR_PERI_RESET_CONF_SAR_RTC_I2C_RESET = 0x8000000 + // Position of SAR_TSENS_RESET field. + SENS_SAR_PERI_RESET_CONF_SAR_TSENS_RESET_Pos = 0x1d + // Bit mask of SAR_TSENS_RESET field. + SENS_SAR_PERI_RESET_CONF_SAR_TSENS_RESET_Msk = 0x20000000 + // Bit SAR_TSENS_RESET. + SENS_SAR_PERI_RESET_CONF_SAR_TSENS_RESET = 0x20000000 + // Position of SAR_SARADC_RESET field. + SENS_SAR_PERI_RESET_CONF_SAR_SARADC_RESET_Pos = 0x1e + // Bit mask of SAR_SARADC_RESET field. + SENS_SAR_PERI_RESET_CONF_SAR_SARADC_RESET_Msk = 0x40000000 + // Bit SAR_SARADC_RESET. + SENS_SAR_PERI_RESET_CONF_SAR_SARADC_RESET = 0x40000000 + + // SAR_COCPU_INT_ENA_W1TS: the interrupt enable of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS = 0x4 + // Position of SAR_COCPU_SARADC1_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC1_INT_ENA_W1TS_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC1_INT_ENA_W1TS_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC1_INT_ENA_W1TS = 0x8 + // Position of SAR_COCPU_SARADC2_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC2_INT_ENA_W1TS_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC2_INT_ENA_W1TS_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SARADC2_INT_ENA_W1TS = 0x10 + // Position of SAR_COCPU_TSENS_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TSENS_INT_ENA_W1TS_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TSENS_INT_ENA_W1TS_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TSENS_INT_ENA_W1TS = 0x20 + // Position of SAR_COCPU_START_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_START_INT_ENA_W1TS_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_START_INT_ENA_W1TS_Msk = 0x40 + // Bit SAR_COCPU_START_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_START_INT_ENA_W1TS = 0x40 + // Position of SAR_COCPU_SW_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SW_INT_ENA_W1TS_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SW_INT_ENA_W1TS_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SW_INT_ENA_W1TS = 0x80 + // Position of SAR_COCPU_SWD_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SWD_INT_ENA_W1TS_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SWD_INT_ENA_W1TS_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_SWD_INT_ENA_W1TS = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS field. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS. + SENS_SAR_COCPU_INT_ENA_W1TS_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS = 0x800 + + // SAR_COCPU_INT_ENA_W1TC: the interrupt enable clear of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC = 0x4 + // Position of SAR_COCPU_SARADC1_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC1_INT_ENA_W1TC_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC1_INT_ENA_W1TC_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC1_INT_ENA_W1TC = 0x8 + // Position of SAR_COCPU_SARADC2_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC2_INT_ENA_W1TC_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC2_INT_ENA_W1TC_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SARADC2_INT_ENA_W1TC = 0x10 + // Position of SAR_COCPU_TSENS_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TSENS_INT_ENA_W1TC_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TSENS_INT_ENA_W1TC_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TSENS_INT_ENA_W1TC = 0x20 + // Position of SAR_COCPU_START_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_START_INT_ENA_W1TC_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_START_INT_ENA_W1TC_Msk = 0x40 + // Bit SAR_COCPU_START_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_START_INT_ENA_W1TC = 0x40 + // Position of SAR_COCPU_SW_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SW_INT_ENA_W1TC_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SW_INT_ENA_W1TC_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SW_INT_ENA_W1TC = 0x80 + // Position of SAR_COCPU_SWD_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SWD_INT_ENA_W1TC_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SWD_INT_ENA_W1TC_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_SWD_INT_ENA_W1TC = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC field. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC. + SENS_SAR_COCPU_INT_ENA_W1TC_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC = 0x800 + + // SAR_DEBUG_CONF: rtc peri debug configure + // Position of SAR_DEBUG_BIT_SEL field. + SENS_SAR_DEBUG_CONF_SAR_DEBUG_BIT_SEL_Pos = 0x0 + // Bit mask of SAR_DEBUG_BIT_SEL field. + SENS_SAR_DEBUG_CONF_SAR_DEBUG_BIT_SEL_Msk = 0x1f + + // SAR_SARDATE: version + // Position of SAR_DATE field. + SENS_SAR_SARDATE_SAR_DATE_Pos = 0x0 + // Bit mask of SAR_DATE field. + SENS_SAR_SARDATE_SAR_DATE_Msk = 0xfffffff +) + +// Constants for SENSITIVE: SENSITIVE Peripheral +const ( + // CACHE_DATAARRAY_CONNECT_0: Cache data array configuration register 0. + // Position of CACHE_DATAARRAY_CONNECT_LOCK field. + SENSITIVE_CACHE_DATAARRAY_CONNECT_0_CACHE_DATAARRAY_CONNECT_LOCK_Pos = 0x0 + // Bit mask of CACHE_DATAARRAY_CONNECT_LOCK field. + SENSITIVE_CACHE_DATAARRAY_CONNECT_0_CACHE_DATAARRAY_CONNECT_LOCK_Msk = 0x1 + // Bit CACHE_DATAARRAY_CONNECT_LOCK. + SENSITIVE_CACHE_DATAARRAY_CONNECT_0_CACHE_DATAARRAY_CONNECT_LOCK = 0x1 + + // CACHE_DATAARRAY_CONNECT_1: Cache data array configuration register 1. + // Position of CACHE_DATAARRAY_CONNECT_FLATTEN field. + SENSITIVE_CACHE_DATAARRAY_CONNECT_1_CACHE_DATAARRAY_CONNECT_FLATTEN_Pos = 0x0 + // Bit mask of CACHE_DATAARRAY_CONNECT_FLATTEN field. + SENSITIVE_CACHE_DATAARRAY_CONNECT_1_CACHE_DATAARRAY_CONNECT_FLATTEN_Msk = 0xff + + // APB_PERIPHERAL_ACCESS_0: APB peripheral configuration register 0. + // Position of APB_PERIPHERAL_ACCESS_LOCK field. + SENSITIVE_APB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK_Pos = 0x0 + // Bit mask of APB_PERIPHERAL_ACCESS_LOCK field. + SENSITIVE_APB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK_Msk = 0x1 + // Bit APB_PERIPHERAL_ACCESS_LOCK. + SENSITIVE_APB_PERIPHERAL_ACCESS_0_APB_PERIPHERAL_ACCESS_LOCK = 0x1 + + // APB_PERIPHERAL_ACCESS_1: APB peripheral configuration register 1. + // Position of APB_PERIPHERAL_ACCESS_SPLIT_BURST field. + SENSITIVE_APB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST_Pos = 0x0 + // Bit mask of APB_PERIPHERAL_ACCESS_SPLIT_BURST field. + SENSITIVE_APB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST_Msk = 0x1 + // Bit APB_PERIPHERAL_ACCESS_SPLIT_BURST. + SENSITIVE_APB_PERIPHERAL_ACCESS_1_APB_PERIPHERAL_ACCESS_SPLIT_BURST = 0x1 + + // INTERNAL_SRAM_USAGE_0: Internal SRAM configuration register 0. + // Position of INTERNAL_SRAM_USAGE_LOCK field. + SENSITIVE_INTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_USAGE_LOCK field. + SENSITIVE_INTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK_Msk = 0x1 + // Bit INTERNAL_SRAM_USAGE_LOCK. + SENSITIVE_INTERNAL_SRAM_USAGE_0_INTERNAL_SRAM_USAGE_LOCK = 0x1 + + // INTERNAL_SRAM_USAGE_1: Internal SRAM configuration register 1. + // Position of INTERNAL_SRAM_ICACHE_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_ICACHE_USAGE_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_ICACHE_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_ICACHE_USAGE_Msk = 0x3 + // Position of INTERNAL_SRAM_DCACHE_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_DCACHE_USAGE_Pos = 0x2 + // Bit mask of INTERNAL_SRAM_DCACHE_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_DCACHE_USAGE_Msk = 0xc + // Position of INTERNAL_SRAM_CPU_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_CPU_USAGE_Pos = 0x4 + // Bit mask of INTERNAL_SRAM_CPU_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_1_INTERNAL_SRAM_CPU_USAGE_Msk = 0x7f0 + + // INTERNAL_SRAM_USAGE_2: Internal SRAM configuration register 2. + // Position of INTERNAL_SRAM_CORE0_TRACE_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE0_TRACE_USAGE_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_CORE0_TRACE_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE0_TRACE_USAGE_Msk = 0x7f + // Position of INTERNAL_SRAM_CORE1_TRACE_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE1_TRACE_USAGE_Pos = 0x7 + // Bit mask of INTERNAL_SRAM_CORE1_TRACE_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE1_TRACE_USAGE_Msk = 0x3f80 + // Position of INTERNAL_SRAM_CORE0_TRACE_ALLOC field. + SENSITIVE_INTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE0_TRACE_ALLOC_Pos = 0xe + // Bit mask of INTERNAL_SRAM_CORE0_TRACE_ALLOC field. + SENSITIVE_INTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE0_TRACE_ALLOC_Msk = 0xc000 + // Position of INTERNAL_SRAM_CORE1_TRACE_ALLOC field. + SENSITIVE_INTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE1_TRACE_ALLOC_Pos = 0x10 + // Bit mask of INTERNAL_SRAM_CORE1_TRACE_ALLOC field. + SENSITIVE_INTERNAL_SRAM_USAGE_2_INTERNAL_SRAM_CORE1_TRACE_ALLOC_Msk = 0x30000 + + // INTERNAL_SRAM_USAGE_3: Internal SRAM configuration register 3. + // Position of INTERNAL_SRAM_MAC_DUMP_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_MAC_DUMP_USAGE_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_MAC_DUMP_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_3_INTERNAL_SRAM_MAC_DUMP_USAGE_Msk = 0xf + + // INTERNAL_SRAM_USAGE_4: Internal SRAM configuration register 4. + // Position of INTERNAL_SRAM_LOG_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_4_INTERNAL_SRAM_LOG_USAGE_Pos = 0x0 + // Bit mask of INTERNAL_SRAM_LOG_USAGE field. + SENSITIVE_INTERNAL_SRAM_USAGE_4_INTERNAL_SRAM_LOG_USAGE_Msk = 0x7f + + // RETENTION_DISABLE: Retention configuration register. + // Position of RETENTION_DISABLE field. + SENSITIVE_RETENTION_DISABLE_RETENTION_DISABLE_Pos = 0x0 + // Bit mask of RETENTION_DISABLE field. + SENSITIVE_RETENTION_DISABLE_RETENTION_DISABLE_Msk = 0x1 + // Bit RETENTION_DISABLE. + SENSITIVE_RETENTION_DISABLE_RETENTION_DISABLE = 0x1 + + // CACHE_TAG_ACCESS_0: Cache tag configuration register 0. + // Position of CACHE_TAG_ACCESS_LOCK field. + SENSITIVE_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK_Pos = 0x0 + // Bit mask of CACHE_TAG_ACCESS_LOCK field. + SENSITIVE_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK_Msk = 0x1 + // Bit CACHE_TAG_ACCESS_LOCK. + SENSITIVE_CACHE_TAG_ACCESS_0_CACHE_TAG_ACCESS_LOCK = 0x1 + + // CACHE_TAG_ACCESS_1: Cache tag configuration register 1. + // Position of PRO_I_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS_Pos = 0x0 + // Bit mask of PRO_I_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS_Msk = 0x1 + // Bit PRO_I_TAG_RD_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_RD_ACS = 0x1 + // Position of PRO_I_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS_Pos = 0x1 + // Bit mask of PRO_I_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS_Msk = 0x2 + // Bit PRO_I_TAG_WR_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_I_TAG_WR_ACS = 0x2 + // Position of PRO_D_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS_Pos = 0x2 + // Bit mask of PRO_D_TAG_RD_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS_Msk = 0x4 + // Bit PRO_D_TAG_RD_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_RD_ACS = 0x4 + // Position of PRO_D_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS_Pos = 0x3 + // Bit mask of PRO_D_TAG_WR_ACS field. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS_Msk = 0x8 + // Bit PRO_D_TAG_WR_ACS. + SENSITIVE_CACHE_TAG_ACCESS_1_PRO_D_TAG_WR_ACS = 0x8 + + // CACHE_MMU_ACCESS_0: Cache MMU configuration register 0. + // Position of CACHE_MMU_ACCESS_LOCK field. + SENSITIVE_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK_Pos = 0x0 + // Bit mask of CACHE_MMU_ACCESS_LOCK field. + SENSITIVE_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK_Msk = 0x1 + // Bit CACHE_MMU_ACCESS_LOCK. + SENSITIVE_CACHE_MMU_ACCESS_0_CACHE_MMU_ACCESS_LOCK = 0x1 + + // CACHE_MMU_ACCESS_1: Cache MMU configuration register 1. + // Position of PRO_MMU_RD_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS_Pos = 0x0 + // Bit mask of PRO_MMU_RD_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS_Msk = 0x1 + // Bit PRO_MMU_RD_ACS. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_RD_ACS = 0x1 + // Position of PRO_MMU_WR_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS_Pos = 0x1 + // Bit mask of PRO_MMU_WR_ACS field. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS_Msk = 0x2 + // Bit PRO_MMU_WR_ACS. + SENSITIVE_CACHE_MMU_ACCESS_1_PRO_MMU_WR_ACS = 0x2 + + // DMA_APBPERI_SPI2_PMS_CONSTRAIN_0: spi2 dma permission configuration register 0. + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_SPI2_PMS_CONSTRAIN_1: spi2 dma permission configuration register 1. + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_SPI3_PMS_CONSTRAIN_0: spi3 dma permission configuration register 0. + // Position of DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_SPI3_PMS_CONSTRAIN_1: spi3 dma permission configuration register 1. + // Position of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0: uhci0 dma permission configuration register 0. + // Position of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1: uhci0 dma permission configuration register 1. + // Position of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_I2S0_PMS_CONSTRAIN_0: i2s0 dma permission configuration register 0. + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_I2S0_PMS_CONSTRAIN_1: i2s0 dma permission configuration register 1. + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_I2S1_PMS_CONSTRAIN_0: i2s1 dma permission configuration register 0. + // Position of DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_I2S1_PMS_CONSTRAIN_1: i2s1 dma permission configuration register 1. + // Position of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_MAC_PMS_CONSTRAIN_0: mac dma permission configuration register 0. + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_MAC_PMS_CONSTRAIN_1: mac dma permission configuration register 1. + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0: backup dma permission configuration register 0. + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1: backup dma permission configuration register 1. + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_AES_PMS_CONSTRAIN_0: aes dma permission configuration register 0. + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_AES_PMS_CONSTRAIN_1: aes dma permission configuration register 1. + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_SHA_PMS_CONSTRAIN_0: sha dma permission configuration register 0. + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_SHA_PMS_CONSTRAIN_1: sha dma permission configuration register 1. + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0: adc_dac dma permission configuration register 0. + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1: adc_dac dma permission configuration register 1. + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_RMT_PMS_CONSTRAIN_0: rmt dma permission configuration register 0. + // Position of DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_0_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_0_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_0_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_RMT_PMS_CONSTRAIN_1: rmt dma permission configuration register 1. + // Position of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0: lcd_cam dma permission configuration register 0. + // Position of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1: lcd_cam dma permission configuration register 1. + // Position of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_USB_PMS_CONSTRAIN_0: usb dma permission configuration register 0. + // Position of DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_USB_PMS_CONSTRAIN_1: usb dma permission configuration register 1. + // Position of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_LC_PMS_CONSTRAIN_0: lc dma permission configuration register 0. + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_LC_PMS_CONSTRAIN_1: lc dma permission configuration register 1. + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_SDIO_PMS_CONSTRAIN_0: sdio dma permission configuration register 0. + // Position of DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK = 0x1 + + // DMA_APBPERI_SDIO_PMS_CONSTRAIN_1: sdio dma permission configuration register 1. + // Position of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_Pos = 0x0 + // Bit mask of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_Msk = 0x3 + // Position of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_Pos = 0x2 + // Bit mask of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_Msk = 0xc + // Position of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_Pos = 0x4 + // Bit mask of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_Msk = 0x30 + // Position of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_Pos = 0x6 + // Bit mask of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_Msk = 0xc0 + // Position of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + + // DMA_APBPERI_PMS_MONITOR_0: dma permission monitor configuration register 0. + // Position of DMA_APBPERI_PMS_MONITOR_LOCK field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_LOCK field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit DMA_APBPERI_PMS_MONITOR_LOCK. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_DMA_APBPERI_PMS_MONITOR_LOCK = 0x1 + + // DMA_APBPERI_PMS_MONITOR_1: dma permission monitor configuration register 1. + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit DMA_APBPERI_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN = 0x2 + + // DMA_APBPERI_PMS_MONITOR_2: dma permission monitor configuration register 2. + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_Pos = 0x1 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_Msk = 0x6 + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_Pos = 0x3 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_Msk = 0x1fffff8 + + // DMA_APBPERI_PMS_MONITOR_3: dma permission monitor configuration register 3. + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_Pos = 0x0 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_Msk = 0x1 + // Bit DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR = 0x1 + // Position of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Pos = 0x1 + // Bit mask of DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Msk = 0x1fffe + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0: sram split line configuration register 0 + // Position of CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK = 0x1 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1: sram split line configuration register 1 + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_Msk = 0xc + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_Pos = 0x6 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_Msk = 0xc0 + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_Pos = 0x8 + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_Msk = 0x300 + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_Pos = 0xa + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_Msk = 0xc00 + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_Pos = 0xc + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_Msk = 0x3000 + // Position of CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2: sram split line configuration register 1 + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_Msk = 0xc + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_Pos = 0x6 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_Msk = 0xc0 + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_Pos = 0x8 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_Msk = 0x300 + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_Pos = 0xa + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_Msk = 0xc00 + // Position of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_Pos = 0xc + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_Msk = 0x3000 + // Position of CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3: sram split line configuration register 1 + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_Msk = 0xc + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_Pos = 0x6 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_Msk = 0xc0 + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_Pos = 0x8 + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_Msk = 0x300 + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_Pos = 0xa + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_Msk = 0xc00 + // Position of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_Pos = 0xc + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_Msk = 0x3000 + // Position of CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4: sram split line configuration register 1 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_Msk = 0xc + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_Pos = 0x6 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_Msk = 0xc0 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_Pos = 0x8 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_Msk = 0x300 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_Pos = 0xa + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_Msk = 0xc00 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_Pos = 0xc + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_Msk = 0x3000 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5: sram split line configuration register 1 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_Pos = 0x0 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_Msk = 0x3 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_Pos = 0x2 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_Msk = 0xc + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_Pos = 0x4 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_Msk = 0x30 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_Pos = 0x6 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_Msk = 0xc0 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_Pos = 0x8 + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_Msk = 0x300 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_Pos = 0xa + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_Msk = 0xc00 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_Pos = 0xc + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_Msk = 0x3000 + // Position of CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_Pos = 0xe + // Bit mask of CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR field. + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_Msk = 0x3fc000 + + // CORE_X_IRAM0_PMS_CONSTRAIN_0: corex iram0 permission configuration register 0 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_X_IRAM0_PMS_CONSTRAIN_LOCK. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK = 0x1 + + // CORE_X_IRAM0_PMS_CONSTRAIN_1: corex iram0 permission configuration register 0 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x7 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0x3 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0x38 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x6 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x1c0 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x9 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xe00 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_Pos = 0xc + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_Msk = 0x7000 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_Pos = 0xf + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_Msk = 0x38000 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_Pos = 0x12 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_Msk = 0x1c0000 + + // CORE_X_IRAM0_PMS_CONSTRAIN_2: corex iram0 permission configuration register 1 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x7 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x3 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0x38 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x6 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x1c0 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x9 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xe00 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_Pos = 0xc + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_Msk = 0x7000 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_Pos = 0xf + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_Msk = 0x38000 + // Position of CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_Pos = 0x12 + // Bit mask of CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS field. + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_Msk = 0x1c0000 + + // CORE_0_IRAM0_PMS_MONITOR_0: core0 iram0 permission monitor configuration register 0 + // Position of CORE_0_IRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit CORE_0_IRAM0_PMS_MONITOR_LOCK. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_CORE_0_IRAM0_PMS_MONITOR_LOCK = 0x1 + + // CORE_0_IRAM0_PMS_MONITOR_1: core0 iram0 permission monitor configuration register 1 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN = 0x2 + + // CORE_0_IRAM0_PMS_MONITOR_2: core0 iram0 permission monitor configuration register 2 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Pos = 0x1 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Msk = 0x2 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR = 0x2 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_Pos = 0x2 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_Msk = 0x4 + // Bit CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE = 0x4 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Pos = 0x3 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Msk = 0x18 + // Position of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Pos = 0x5 + // Bit mask of CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Msk = 0x1fffffe0 + + // CORE_1_IRAM0_PMS_MONITOR_0: core1 iram0 permission monitor configuration register 0 + // Position of CORE_1_IRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_CORE_1_IRAM0_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_CORE_1_IRAM0_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit CORE_1_IRAM0_PMS_MONITOR_LOCK. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_CORE_1_IRAM0_PMS_MONITOR_LOCK = 0x1 + + // CORE_1_IRAM0_PMS_MONITOR_1: core1 iram0 permission monitor configuration register 1 + // Position of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN = 0x2 + + // CORE_1_IRAM0_PMS_MONITOR_2: core1 iram0 permission monitor configuration register 2 + // Position of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Pos = 0x1 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Msk = 0x2 + // Bit CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR = 0x2 + // Position of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_Pos = 0x2 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_Msk = 0x4 + // Bit CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE = 0x4 + // Position of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Pos = 0x3 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Msk = 0x18 + // Position of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Pos = 0x5 + // Bit mask of CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Msk = 0x1fffffe0 + + // CORE_X_DRAM0_PMS_CONSTRAIN_0: corex dram0 permission configuration register 0 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_X_DRAM0_PMS_CONSTRAIN_LOCK. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK = 0x1 + + // CORE_X_DRAM0_PMS_CONSTRAIN_1: corex dram0 permission configuration register 1 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Pos = 0x0 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_Msk = 0x3 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Pos = 0x2 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_Msk = 0xc + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Pos = 0x4 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_Msk = 0x30 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Pos = 0x6 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_Msk = 0xc0 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_Pos = 0x8 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_Msk = 0x300 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_Pos = 0xa + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_Msk = 0xc00 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Pos = 0xc + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_Msk = 0x3000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Pos = 0xe + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_Msk = 0xc000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Pos = 0x10 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_Msk = 0x30000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Pos = 0x12 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_Msk = 0xc0000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_Pos = 0x14 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_Msk = 0x300000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_Pos = 0x16 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_Msk = 0xc00000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_Pos = 0x18 + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_Msk = 0x3000000 + // Position of CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_Pos = 0x1a + // Bit mask of CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS field. + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_Msk = 0xc000000 + + // CORE_0_DRAM0_PMS_MONITOR_0: core0 dram0 permission monitor configuration register 0 + // Position of CORE_0_DRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit CORE_0_DRAM0_PMS_MONITOR_LOCK. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_CORE_0_DRAM0_PMS_MONITOR_LOCK = 0x1 + + // CORE_0_DRAM0_PMS_MONITOR_1: core0 dram0 permission monitor configuration register 1 + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN = 0x2 + + // CORE_0_DRAM0_PMS_MONITOR_2: core0 dram0 permission monitor configuration register 2. + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_Pos = 0x1 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_Msk = 0x2 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK = 0x2 + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Pos = 0x2 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Msk = 0xc + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Pos = 0x4 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Msk = 0x3fffff0 + + // CORE_0_DRAM0_PMS_MONITOR_3: core0 dram0 permission monitor configuration register 3. + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Pos = 0x0 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Msk = 0x1 + // Bit CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR = 0x1 + // Position of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Pos = 0x1 + // Bit mask of CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Msk = 0x1fffe + + // CORE_1_DRAM0_PMS_MONITOR_0: core1 dram0 permission monitor configuration register 0 + // Position of CORE_1_DRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_CORE_1_DRAM0_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_CORE_1_DRAM0_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit CORE_1_DRAM0_PMS_MONITOR_LOCK. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_CORE_1_DRAM0_PMS_MONITOR_LOCK = 0x1 + + // CORE_1_DRAM0_PMS_MONITOR_1: core1 dram0 permission monitor configuration register 1 + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN = 0x2 + + // CORE_1_DRAM0_PMS_MONITOR_2: core1 dram0 permission monitor configuration register 2. + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_Pos = 0x1 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_Msk = 0x2 + // Bit CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK = 0x2 + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Pos = 0x2 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_Msk = 0xc + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Pos = 0x4 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_Msk = 0x3fffff0 + + // CORE_1_DRAM0_PMS_MONITOR_3: core1 dram0 permission monitor configuration register 3. + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Pos = 0x0 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_Msk = 0x1 + // Bit CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR = 0x1 + // Position of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Pos = 0x1 + // Bit mask of CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN field. + SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_Msk = 0x1fffe + + // CORE_0_PIF_PMS_CONSTRAIN_0: Core0 access peripherals permission configuration register 0. + // Position of CORE_0_PIF_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_0_PIF_PMS_CONSTRAIN_LOCK. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_CORE_0_PIF_PMS_CONSTRAIN_LOCK = 0x1 + + // CORE_0_PIF_PMS_CONSTRAIN_1: Core0 access peripherals permission configuration register 1. + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_Pos = 0x14 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_Msk = 0x300000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_2: Core0 access peripherals permission configuration register 2. + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_Pos = 0x12 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_Msk = 0xc0000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_3: Core0 access peripherals permission configuration register 3. + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_Msk = 0x30000000 + + // CORE_0_PIF_PMS_CONSTRAIN_4: Core0 access peripherals permission configuration register 4. + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_Pos = 0x12 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_Msk = 0xc0000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_Pos = 0x14 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_Msk = 0x300000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_5: Core0 access peripherals permission configuration register 5. + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_Pos = 0x14 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_Msk = 0x300000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_6: Core0 access peripherals permission configuration register 6. + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_Pos = 0x12 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_Msk = 0xc0000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_7: Core0 access peripherals permission configuration register 7. + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_Msk = 0x30000000 + + // CORE_0_PIF_PMS_CONSTRAIN_8: Core0 access peripherals permission configuration register 8. + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_Msk = 0x3 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_Msk = 0xc + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_Pos = 0x4 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_Msk = 0x30 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_Msk = 0xc0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_Pos = 0x8 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_Msk = 0x300 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_Pos = 0xa + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_Msk = 0xc00 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_Pos = 0xc + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_Msk = 0x3000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_Pos = 0xe + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_Msk = 0xc000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_Pos = 0x10 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_Msk = 0x30000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_Pos = 0x12 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_Msk = 0xc0000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_Pos = 0x14 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_Msk = 0x300000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_Pos = 0x16 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_Msk = 0xc00000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_Pos = 0x18 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_Msk = 0x3000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_Pos = 0x1a + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_Msk = 0xc000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_Pos = 0x1c + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_Msk = 0x30000000 + // Position of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_Pos = 0x1e + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_Msk = 0xc0000000 + + // CORE_0_PIF_PMS_CONSTRAIN_9: Core0 access peripherals permission configuration register 9. + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_Msk = 0x7ff + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_Pos = 0xb + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_Msk = 0x3ff800 + + // CORE_0_PIF_PMS_CONSTRAIN_10: Core0 access peripherals permission configuration register 10. + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_Msk = 0x7 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_Pos = 0x3 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_Msk = 0x38 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_Msk = 0x1c0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_Pos = 0x9 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_Msk = 0xe00 + + // CORE_0_PIF_PMS_CONSTRAIN_11: Core0 access peripherals permission configuration register 11. + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_Msk = 0x7ff + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_Pos = 0xb + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_Msk = 0x3ff800 + + // CORE_0_PIF_PMS_CONSTRAIN_12: Core0 access peripherals permission configuration register 12. + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_Msk = 0x7 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_Pos = 0x3 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_Msk = 0x38 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_Msk = 0x1c0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_Pos = 0x9 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_Msk = 0xe00 + + // CORE_0_PIF_PMS_CONSTRAIN_13: Core0 access peripherals permission configuration register 13. + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_Msk = 0x7ff + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_Pos = 0xb + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_Msk = 0x3ff800 + + // CORE_0_PIF_PMS_CONSTRAIN_14: Core0 access peripherals permission configuration register 14. + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_Msk = 0x7 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_Pos = 0x3 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_Msk = 0x38 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_Msk = 0x1c0 + // Position of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_Pos = 0x9 + // Bit mask of CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H field. + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_Msk = 0xe00 + + // CORE_0_REGION_PMS_CONSTRAIN_0: Core0 region permission register 0. + // Position of CORE_0_REGION_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_0_CORE_0_REGION_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_0_CORE_0_REGION_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_0_REGION_PMS_CONSTRAIN_LOCK. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_0_CORE_0_REGION_PMS_CONSTRAIN_LOCK = 0x1 + + // CORE_0_REGION_PMS_CONSTRAIN_1: Core0 region permission register 1. + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_Msk = 0x3 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_Pos = 0x2 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_Msk = 0xc + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_Pos = 0x4 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_Msk = 0x30 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_Pos = 0x6 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_Msk = 0xc0 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_Pos = 0x8 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_Msk = 0x300 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_Pos = 0xa + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_Msk = 0xc00 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_Pos = 0xc + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_Msk = 0x3000 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_Pos = 0xe + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_Msk = 0xc000 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_Pos = 0x10 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_Msk = 0x30000 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_Pos = 0x12 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_Msk = 0xc0000 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_Pos = 0x14 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_Msk = 0x300000 + + // CORE_0_REGION_PMS_CONSTRAIN_2: Core0 region permission register 2. + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_Msk = 0x3 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_Pos = 0x2 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_Msk = 0xc + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_Pos = 0x4 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_Msk = 0x30 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_Pos = 0x6 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_Msk = 0xc0 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_Pos = 0x8 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_Msk = 0x300 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_Pos = 0xa + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_Msk = 0xc00 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_Pos = 0xc + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_Msk = 0x3000 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_Pos = 0xe + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_Msk = 0xc000 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_Pos = 0x10 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_Msk = 0x30000 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_Pos = 0x12 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_Msk = 0xc0000 + // Position of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_Pos = 0x14 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_Msk = 0x300000 + + // CORE_0_REGION_PMS_CONSTRAIN_3: Core0 region permission register 3. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_3_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_3_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_4: Core0 region permission register 4. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_4_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_4_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_5: Core0 region permission register 5. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_5_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_5_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_6: Core0 region permission register 6. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_6_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_6_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_7: Core0 region permission register 7. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_7_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_7_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_8: Core0 region permission register 8. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_8_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_8_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_9: Core0 region permission register 9. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_9_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_9_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_10: Core0 region permission register 10. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_10_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_10_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_11: Core0 region permission register 11. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_11_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_11_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_12: Core0 region permission register 12. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_12_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_12_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_13: Core0 region permission register 13. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_13_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_13_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_Msk = 0x3fffffff + + // CORE_0_REGION_PMS_CONSTRAIN_14: Core0 region permission register 14. + // Position of CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_14_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_Pos = 0x0 + // Bit mask of CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 field. + SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_14_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_Msk = 0x3fffffff + + // CORE_0_PIF_PMS_MONITOR_0: Core0 permission report register 0. + // Position of CORE_0_PIF_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_LOCK. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_CORE_0_PIF_PMS_MONITOR_LOCK = 0x1 + + // CORE_0_PIF_PMS_MONITOR_1: Core0 permission report register 1. + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN = 0x2 + + // CORE_0_PIF_PMS_MONITOR_2: Core0 permission report register 2. + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_Pos = 0x1 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_Msk = 0x2 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 = 0x2 + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Pos = 0x2 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Msk = 0x1c + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Pos = 0x5 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Msk = 0x20 + // Bit CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE = 0x20 + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_Pos = 0x6 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_Msk = 0xc0 + + // CORE_0_PIF_PMS_MONITOR_3: Core0 permission report register 3. + // Position of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_Msk = 0xffffffff + + // CORE_0_PIF_PMS_MONITOR_4: Core0 permission report register 4. + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR = 0x1 + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_Msk = 0x2 + // Bit CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN = 0x2 + + // CORE_0_PIF_PMS_MONITOR_5: Core0 permission report register 5. + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR = 0x1 + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_Pos = 0x1 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_Msk = 0x6 + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_Pos = 0x3 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_Msk = 0x18 + + // CORE_0_PIF_PMS_MONITOR_6: Core0 permission report register 6. + // Position of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_Pos = 0x0 + // Bit mask of CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_Msk = 0xffffffff + + // CORE_0_VECBASE_OVERRIDE_LOCK: core0 vecbase override configuration register 0 + // Position of CORE_0_VECBASE_OVERRIDE_LOCK field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_CORE_0_VECBASE_OVERRIDE_LOCK_Pos = 0x0 + // Bit mask of CORE_0_VECBASE_OVERRIDE_LOCK field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_CORE_0_VECBASE_OVERRIDE_LOCK_Msk = 0x1 + // Bit CORE_0_VECBASE_OVERRIDE_LOCK. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_CORE_0_VECBASE_OVERRIDE_LOCK = 0x1 + + // CORE_0_VECBASE_OVERRIDE_0: core0 vecbase override configuration register 0 + // Position of CORE_0_VECBASE_WORLD_MASK field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_CORE_0_VECBASE_WORLD_MASK_Pos = 0x0 + // Bit mask of CORE_0_VECBASE_WORLD_MASK field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_CORE_0_VECBASE_WORLD_MASK_Msk = 0x1 + // Bit CORE_0_VECBASE_WORLD_MASK. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_CORE_0_VECBASE_WORLD_MASK = 0x1 + + // CORE_0_VECBASE_OVERRIDE_1: core0 vecbase override configuration register 1 + // Position of CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_Pos = 0x0 + // Bit mask of CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_Msk = 0x3fffff + // Position of CORE_0_VECBASE_OVERRIDE_SEL field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_CORE_0_VECBASE_OVERRIDE_SEL_Pos = 0x16 + // Bit mask of CORE_0_VECBASE_OVERRIDE_SEL field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_CORE_0_VECBASE_OVERRIDE_SEL_Msk = 0xc00000 + + // CORE_0_VECBASE_OVERRIDE_2: core0 vecbase override configuration register 1 + // Position of CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_2_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_Pos = 0x0 + // Bit mask of CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE field. + SENSITIVE_CORE_0_VECBASE_OVERRIDE_2_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_Msk = 0x3fffff + + // CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0: core0 toomanyexception override configuration register 0. + // Position of CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK field. + SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_Pos = 0x0 + // Bit mask of CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK field. + SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_Msk = 0x1 + // Bit CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK. + SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK = 0x1 + + // CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1: core0 toomanyexception override configuration register 1. + // Position of CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE field. + SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_Pos = 0x0 + // Bit mask of CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE field. + SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_Msk = 0x1 + // Bit CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE. + SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE = 0x1 + + // CORE_1_PIF_PMS_CONSTRAIN_0: Core1 access peripherals permission configuration register 0. + // Position of CORE_1_PIF_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_CORE_1_PIF_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_CORE_1_PIF_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_1_PIF_PMS_CONSTRAIN_LOCK. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_CORE_1_PIF_PMS_CONSTRAIN_LOCK = 0x1 + + // CORE_1_PIF_PMS_CONSTRAIN_1: Core1 access peripherals permission configuration register 1. + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_Msk = 0x3 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_Pos = 0x2 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_Msk = 0xc + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_Pos = 0x4 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_Msk = 0x30 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_Msk = 0xc0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_Pos = 0x8 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_Msk = 0x300 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_Pos = 0xa + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_Msk = 0xc00 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_Pos = 0xe + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_Msk = 0xc000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_Pos = 0x10 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_Msk = 0x30000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_Pos = 0x14 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_Msk = 0x300000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_Pos = 0x18 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_Msk = 0x3000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_Pos = 0x1a + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_Msk = 0xc000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_Pos = 0x1c + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_Msk = 0x30000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_Pos = 0x1e + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_Msk = 0xc0000000 + + // CORE_1_PIF_PMS_CONSTRAIN_2: Core1 access peripherals permission configuration register 2. + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_Msk = 0x3 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_Pos = 0x4 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_Msk = 0x30 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_Msk = 0xc0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_Pos = 0x8 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_Msk = 0x300 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_Pos = 0xa + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_Msk = 0xc00 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_Pos = 0xc + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_Msk = 0x3000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_Pos = 0xe + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_Msk = 0xc000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_Pos = 0x10 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_Msk = 0x30000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_Pos = 0x12 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_Msk = 0xc0000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_Pos = 0x16 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_Msk = 0xc00000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_Pos = 0x18 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_Msk = 0x3000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_Pos = 0x1a + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_Msk = 0xc000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_Pos = 0x1c + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_Msk = 0x30000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_Pos = 0x1e + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_Msk = 0xc0000000 + + // CORE_1_PIF_PMS_CONSTRAIN_3: Core1 access peripherals permission configuration register 3. + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_Msk = 0x3 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_Pos = 0x2 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_Msk = 0xc + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_Pos = 0x4 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_Msk = 0x30 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_Msk = 0xc0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_Pos = 0x8 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_Msk = 0x300 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_Pos = 0xa + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_Msk = 0xc00 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_Pos = 0xc + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_Msk = 0x3000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_Pos = 0xe + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_Msk = 0xc000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_Pos = 0x10 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_Msk = 0x30000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_Pos = 0x16 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_Msk = 0xc00000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_Pos = 0x1a + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_Msk = 0xc000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_Pos = 0x1c + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_Msk = 0x30000000 + + // CORE_1_PIF_PMS_CONSTRAIN_4: Core1 access peripherals permission configuration register 4. + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_Msk = 0x3 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_Pos = 0x2 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_Msk = 0xc + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_Pos = 0x4 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_Msk = 0x30 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_Msk = 0xc0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_Pos = 0x8 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_Msk = 0x300 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_Pos = 0xa + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_Msk = 0xc00 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_Pos = 0xc + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_Msk = 0x3000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_Pos = 0xe + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_Msk = 0xc000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_Pos = 0x10 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_Msk = 0x30000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_Pos = 0x12 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_Msk = 0xc0000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_Pos = 0x14 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_Msk = 0x300000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_Pos = 0x16 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_Msk = 0xc00000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_Pos = 0x18 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_Msk = 0x3000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_Pos = 0x1a + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_Msk = 0xc000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_Pos = 0x1c + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_Msk = 0x30000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_Pos = 0x1e + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_Msk = 0xc0000000 + + // CORE_1_PIF_PMS_CONSTRAIN_5: Core1 access peripherals permission configuration register 5. + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_Msk = 0x3 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_Pos = 0x2 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_Msk = 0xc + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_Pos = 0x4 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_Msk = 0x30 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_Msk = 0xc0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_Pos = 0x8 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_Msk = 0x300 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_Pos = 0xa + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_Msk = 0xc00 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_Pos = 0xe + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_Msk = 0xc000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_Pos = 0x10 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_Msk = 0x30000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_Pos = 0x14 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_Msk = 0x300000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_Pos = 0x18 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_Msk = 0x3000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_Pos = 0x1a + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_Msk = 0xc000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_Pos = 0x1c + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_Msk = 0x30000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_Pos = 0x1e + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_Msk = 0xc0000000 + + // CORE_1_PIF_PMS_CONSTRAIN_6: Core1 access peripherals permission configuration register 6. + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_Msk = 0x3 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_Pos = 0x4 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_Msk = 0x30 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_Msk = 0xc0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_Pos = 0x8 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_Msk = 0x300 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_Pos = 0xa + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_Msk = 0xc00 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_Pos = 0xc + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_Msk = 0x3000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_Pos = 0xe + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_Msk = 0xc000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_Pos = 0x10 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_Msk = 0x30000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_Pos = 0x12 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_Msk = 0xc0000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_Pos = 0x16 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_Msk = 0xc00000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_Pos = 0x18 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_Msk = 0x3000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_Pos = 0x1a + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_Msk = 0xc000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_Pos = 0x1c + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_Msk = 0x30000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_Pos = 0x1e + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_Msk = 0xc0000000 + + // CORE_1_PIF_PMS_CONSTRAIN_7: Core1 access peripherals permission configuration register 7. + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_Msk = 0x3 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_Pos = 0x2 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_Msk = 0xc + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_Pos = 0x4 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_Msk = 0x30 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_Msk = 0xc0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_Pos = 0x8 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_Msk = 0x300 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_Pos = 0xa + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_Msk = 0xc00 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_Pos = 0xc + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_Msk = 0x3000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_Pos = 0xe + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_Msk = 0xc000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_Pos = 0x10 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_Msk = 0x30000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_Pos = 0x16 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_Msk = 0xc00000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_Pos = 0x1a + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_Msk = 0xc000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_Pos = 0x1c + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_Msk = 0x30000000 + + // CORE_1_PIF_PMS_CONSTRAIN_8: Core1 access peripherals permission configuration register 8. + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_Msk = 0x3 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_Pos = 0x2 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_Msk = 0xc + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_Pos = 0x4 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_Msk = 0x30 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_Msk = 0xc0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_Pos = 0x8 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_Msk = 0x300 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_Pos = 0xa + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_Msk = 0xc00 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_Pos = 0xc + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_Msk = 0x3000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_Pos = 0xe + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_Msk = 0xc000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_Pos = 0x10 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_Msk = 0x30000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_Pos = 0x12 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_Msk = 0xc0000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_Pos = 0x14 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_Msk = 0x300000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_Pos = 0x16 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_Msk = 0xc00000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_Pos = 0x18 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_Msk = 0x3000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_Pos = 0x1a + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_Msk = 0xc000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_Pos = 0x1c + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_Msk = 0x30000000 + // Position of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_Pos = 0x1e + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_Msk = 0xc0000000 + + // CORE_1_PIF_PMS_CONSTRAIN_9: Core1 access peripherals permission configuration register 9. + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_Msk = 0x7ff + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_Pos = 0xb + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_Msk = 0x3ff800 + + // CORE_1_PIF_PMS_CONSTRAIN_10: core1 access peripherals permission configuration register 10. + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_Msk = 0x7 + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_Pos = 0x3 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_Msk = 0x38 + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_Msk = 0x1c0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_Pos = 0x9 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_Msk = 0xe00 + + // CORE_1_PIF_PMS_CONSTRAIN_11: core1 access peripherals permission configuration register 11. + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_Msk = 0x7ff + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_Pos = 0xb + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_Msk = 0x3ff800 + + // CORE_1_PIF_PMS_CONSTRAIN_12: core1 access peripherals permission configuration register 12. + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_Msk = 0x7 + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_Pos = 0x3 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_Msk = 0x38 + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_Msk = 0x1c0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_Pos = 0x9 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_Msk = 0xe00 + + // CORE_1_PIF_PMS_CONSTRAIN_13: core1 access peripherals permission configuration register 13. + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_Msk = 0x7ff + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_Pos = 0xb + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_Msk = 0x3ff800 + + // CORE_1_PIF_PMS_CONSTRAIN_14: core1 access peripherals permission configuration register 14. + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_Msk = 0x7 + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_Pos = 0x3 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_Msk = 0x38 + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_Msk = 0x1c0 + // Position of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_Pos = 0x9 + // Bit mask of CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H field. + SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_Msk = 0xe00 + + // CORE_1_REGION_PMS_CONSTRAIN_0: core1 region permission register 0. + // Position of CORE_1_REGION_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_0_CORE_1_REGION_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_LOCK field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_0_CORE_1_REGION_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit CORE_1_REGION_PMS_CONSTRAIN_LOCK. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_0_CORE_1_REGION_PMS_CONSTRAIN_LOCK = 0x1 + + // CORE_1_REGION_PMS_CONSTRAIN_1: core1 region permission register 1. + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_Msk = 0x3 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_Pos = 0x2 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_Msk = 0xc + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_Pos = 0x4 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_Msk = 0x30 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_Pos = 0x6 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_Msk = 0xc0 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_Pos = 0x8 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_Msk = 0x300 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_Pos = 0xa + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_Msk = 0xc00 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_Pos = 0xc + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_Msk = 0x3000 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_Pos = 0xe + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_Msk = 0xc000 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_Pos = 0x10 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_Msk = 0x30000 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_Pos = 0x12 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_Msk = 0xc0000 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_Pos = 0x14 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_Msk = 0x300000 + + // CORE_1_REGION_PMS_CONSTRAIN_2: core1 region permission register 2. + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_Msk = 0x3 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_Pos = 0x2 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_Msk = 0xc + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_Pos = 0x4 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_Msk = 0x30 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_Pos = 0x6 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_Msk = 0xc0 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_Pos = 0x8 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_Msk = 0x300 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_Pos = 0xa + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_Msk = 0xc00 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_Pos = 0xc + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_Msk = 0x3000 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_Pos = 0xe + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_Msk = 0xc000 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_Pos = 0x10 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_Msk = 0x30000 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_Pos = 0x12 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_Msk = 0xc0000 + // Position of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_Pos = 0x14 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_Msk = 0x300000 + + // CORE_1_REGION_PMS_CONSTRAIN_3: core1 region permission register 3. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_3_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_3_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_4: core1 region permission register 4. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_4_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_4_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_5: core1 region permission register 5. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_5_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_5_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_6: core1 region permission register 6. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_6_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_6_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_7: core1 region permission register 7. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_7_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_7_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_8: core1 region permission register 8. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_8_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_8_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_9: core1 region permission register 9. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_9_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_9_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_10: core1 region permission register 10. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_10_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_10_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_11: core1 region permission register 11. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_11_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_11_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_12: core1 region permission register 12. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_12_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_12_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_13: core1 region permission register 13. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_13_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_13_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_Msk = 0x3fffffff + + // CORE_1_REGION_PMS_CONSTRAIN_14: core1 region permission register 14. + // Position of CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_14_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_Pos = 0x0 + // Bit mask of CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 field. + SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_14_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_Msk = 0x3fffffff + + // CORE_1_PIF_PMS_MONITOR_0: core1 permission report register 0. + // Position of CORE_1_PIF_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_CORE_1_PIF_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_LOCK field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_CORE_1_PIF_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit CORE_1_PIF_PMS_MONITOR_LOCK. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_CORE_1_PIF_PMS_MONITOR_LOCK = 0x1 + + // CORE_1_PIF_PMS_MONITOR_1: core1 permission report register 1. + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit CORE_1_PIF_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN = 0x2 + + // CORE_1_PIF_PMS_MONITOR_2: core1 permission report register 2. + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_Pos = 0x1 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_Msk = 0x2 + // Bit CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 = 0x2 + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Pos = 0x2 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Msk = 0x1c + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Pos = 0x5 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Msk = 0x20 + // Bit CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE = 0x20 + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_Pos = 0x6 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_Msk = 0xc0 + + // CORE_1_PIF_PMS_MONITOR_3: core1 permission report register 3. + // Position of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_Msk = 0xffffffff + + // CORE_1_PIF_PMS_MONITOR_4: core1 permission report register 4. + // Position of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_Msk = 0x1 + // Bit CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR = 0x1 + // Position of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_Pos = 0x1 + // Bit mask of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_Msk = 0x2 + // Bit CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN = 0x2 + + // CORE_1_PIF_PMS_MONITOR_5: core1 permission report register 5. + // Position of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_Msk = 0x1 + // Bit CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR = 0x1 + // Position of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_Pos = 0x1 + // Bit mask of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_Msk = 0x6 + // Position of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_Pos = 0x3 + // Bit mask of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_Msk = 0x18 + + // CORE_1_PIF_PMS_MONITOR_6: core1 permission report register 6. + // Position of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_Pos = 0x0 + // Bit mask of CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR field. + SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_Msk = 0xffffffff + + // CORE_1_VECBASE_OVERRIDE_LOCK: core1 vecbase override configuration register 0 + // Position of CORE_1_VECBASE_OVERRIDE_LOCK field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_CORE_1_VECBASE_OVERRIDE_LOCK_Pos = 0x0 + // Bit mask of CORE_1_VECBASE_OVERRIDE_LOCK field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_CORE_1_VECBASE_OVERRIDE_LOCK_Msk = 0x1 + // Bit CORE_1_VECBASE_OVERRIDE_LOCK. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_CORE_1_VECBASE_OVERRIDE_LOCK = 0x1 + + // CORE_1_VECBASE_OVERRIDE_0: core1 vecbase override configuration register 0 + // Position of CORE_1_VECBASE_WORLD_MASK field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_CORE_1_VECBASE_WORLD_MASK_Pos = 0x0 + // Bit mask of CORE_1_VECBASE_WORLD_MASK field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_CORE_1_VECBASE_WORLD_MASK_Msk = 0x1 + // Bit CORE_1_VECBASE_WORLD_MASK. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_CORE_1_VECBASE_WORLD_MASK = 0x1 + + // CORE_1_VECBASE_OVERRIDE_1: core1 vecbase override configuration register 1 + // Position of CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_Pos = 0x0 + // Bit mask of CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_Msk = 0x3fffff + // Position of CORE_1_VECBASE_OVERRIDE_SEL field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_CORE_1_VECBASE_OVERRIDE_SEL_Pos = 0x16 + // Bit mask of CORE_1_VECBASE_OVERRIDE_SEL field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_CORE_1_VECBASE_OVERRIDE_SEL_Msk = 0xc00000 + + // CORE_1_VECBASE_OVERRIDE_2: core1 vecbase override configuration register 1 + // Position of CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_2_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_Pos = 0x0 + // Bit mask of CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE field. + SENSITIVE_CORE_1_VECBASE_OVERRIDE_2_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_Msk = 0x3fffff + + // CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0: core1 toomanyexception override configuration register 0. + // Position of CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK field. + SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_Pos = 0x0 + // Bit mask of CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK field. + SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_Msk = 0x1 + // Bit CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK. + SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK = 0x1 + + // CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1: core1 toomanyexception override configuration register 1. + // Position of CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE field. + SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_Pos = 0x0 + // Bit mask of CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE field. + SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_Msk = 0x1 + // Bit CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE. + SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE = 0x1 + + // BACKUP_BUS_PMS_CONSTRAIN_0: BackUp access peripherals permission configuration register 0. + // Position of BACKUP_BUS_PMS_CONSTRAIN_LOCK field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_LOCK field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK_Msk = 0x1 + // Bit BACKUP_BUS_PMS_CONSTRAIN_LOCK. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_BACKUP_BUS_PMS_CONSTRAIN_LOCK = 0x1 + + // BACKUP_BUS_PMS_CONSTRAIN_1: BackUp access peripherals permission configuration register 1. + // Position of BACKUP_BUS_PMS_CONSTRAIN_UART field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_UART field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART_Msk = 0x3 + // Position of BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_Pos = 0x2 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_Msk = 0xc + // Position of BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_Pos = 0x4 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_Msk = 0x30 + // Position of BACKUP_BUS_PMS_CONSTRAIN_GPIO field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_GPIO_Pos = 0x6 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_GPIO field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_GPIO_Msk = 0xc0 + // Position of BACKUP_BUS_PMS_CONSTRAIN_FE2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE2_Pos = 0x8 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_FE2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE2_Msk = 0x300 + // Position of BACKUP_BUS_PMS_CONSTRAIN_FE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE_Pos = 0xa + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_FE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_FE_Msk = 0xc00 + // Position of BACKUP_BUS_PMS_CONSTRAIN_RTC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_RTC_Pos = 0xe + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_RTC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_RTC_Msk = 0xc000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_IO_MUX field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_Pos = 0x10 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_IO_MUX field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_Msk = 0x30000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_HINF field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_HINF_Pos = 0x14 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_HINF field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_HINF_Msk = 0x300000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_MISC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_MISC_Pos = 0x18 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_MISC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_MISC_Msk = 0x3000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_I2C field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2C_Pos = 0x1a + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_I2C field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2C_Msk = 0xc000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_I2S0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2S0_Pos = 0x1c + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_I2S0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_I2S0_Msk = 0x30000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_UART1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART1_Pos = 0x1e + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_UART1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_BACKUP_BUS_PMS_CONSTRAIN_UART1_Msk = 0xc0000000 + + // BACKUP_BUS_PMS_CONSTRAIN_2: BackUp access peripherals permission configuration register 2. + // Position of BACKUP_BUS_PMS_CONSTRAIN_BT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BT_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_BT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BT_Msk = 0x3 + // Position of BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_Pos = 0x4 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_Msk = 0x30 + // Position of BACKUP_BUS_PMS_CONSTRAIN_UHCI0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_Pos = 0x6 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_UHCI0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_Msk = 0xc0 + // Position of BACKUP_BUS_PMS_CONSTRAIN_SLCHOST field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_Pos = 0x8 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SLCHOST field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_Msk = 0x300 + // Position of BACKUP_BUS_PMS_CONSTRAIN_RMT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_RMT_Pos = 0xa + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_RMT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_RMT_Msk = 0xc00 + // Position of BACKUP_BUS_PMS_CONSTRAIN_PCNT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_PCNT_Pos = 0xc + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_PCNT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_PCNT_Msk = 0x3000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_SLC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SLC_Pos = 0xe + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SLC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SLC_Msk = 0xc000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_LEDC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_LEDC_Pos = 0x10 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_LEDC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_LEDC_Msk = 0x30000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_BACKUP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_Pos = 0x12 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_BACKUP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_Msk = 0xc0000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_BB field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BB_Pos = 0x16 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_BB field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_BB_Msk = 0xc00000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_PWM0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_PWM0_Pos = 0x18 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_PWM0 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_PWM0_Msk = 0x3000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_Pos = 0x1a + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_Msk = 0xc000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_Pos = 0x1c + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_Msk = 0x30000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_Pos = 0x1e + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_Msk = 0xc0000000 + + // BACKUP_BUS_PMS_CONSTRAIN_3: BackUp access peripherals permission configuration register 3. + // Position of BACKUP_BUS_PMS_CONSTRAIN_SPI_2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SPI_2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_Msk = 0x3 + // Position of BACKUP_BUS_PMS_CONSTRAIN_SPI_3 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_Pos = 0x2 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SPI_3 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_Msk = 0xc + // Position of BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_Pos = 0x4 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_Msk = 0x30 + // Position of BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_Pos = 0x6 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_Msk = 0xc0 + // Position of BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_Pos = 0x8 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_Msk = 0x300 + // Position of BACKUP_BUS_PMS_CONSTRAIN_CAN field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_CAN_Pos = 0xa + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_CAN field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_CAN_Msk = 0xc00 + // Position of BACKUP_BUS_PMS_CONSTRAIN_PWM1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWM1_Pos = 0xc + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_PWM1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWM1_Msk = 0x3000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_I2S1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2S1_Pos = 0xe + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_I2S1 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_I2S1_Msk = 0xc000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_UART2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_UART2_Pos = 0x10 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_UART2 field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_UART2_Msk = 0x30000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_RWBT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_RWBT_Pos = 0x16 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_RWBT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_RWBT_Msk = 0xc00000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_Pos = 0x1a + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_Msk = 0xc000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_PWR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWR_Pos = 0x1c + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_PWR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_BACKUP_BUS_PMS_CONSTRAIN_PWR_Msk = 0x30000000 + + // BACKUP_BUS_PMS_CONSTRAIN_4: BackUp access peripherals permission configuration register 4. + // Position of BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_Msk = 0x3 + // Position of BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_Pos = 0x2 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_Msk = 0xc + // Position of BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_Pos = 0x4 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_Msk = 0x30 + // Position of BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_Pos = 0x6 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_Msk = 0xc0 + // Position of BACKUP_BUS_PMS_CONSTRAIN_APB_ADC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_Pos = 0x8 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_APB_ADC field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_Msk = 0x300 + // Position of BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_Pos = 0xa + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_Msk = 0xc00 + // Position of BACKUP_BUS_PMS_CONSTRAIN_BT_PWR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_Pos = 0xc + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_BT_PWR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_Msk = 0x3000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_USB field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_Pos = 0xe + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_USB field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_USB_Msk = 0xc000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_SYSTEM field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_Pos = 0x10 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SYSTEM field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_Msk = 0x30000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_Pos = 0x12 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_Msk = 0xc0000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_Pos = 0x14 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_Msk = 0x300000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_Pos = 0x16 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_Msk = 0xc00000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_Pos = 0x18 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_Msk = 0x3000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_AD field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_AD_Pos = 0x1a + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_AD field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_AD_Msk = 0xc000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_DIO field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_DIO_Pos = 0x1c + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_DIO field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_DIO_Msk = 0x30000000 + // Position of BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_Pos = 0x1e + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_Msk = 0xc0000000 + + // BACKUP_BUS_PMS_CONSTRAIN_5: BackUp access peripherals permission configuration register 5. + // Position of BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_Msk = 0x7ff + + // BACKUP_BUS_PMS_CONSTRAIN_6: BackUp access peripherals permission configuration register 6. + // Position of BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_Msk = 0x7 + // Position of BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_Pos = 0x3 + // Bit mask of BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H field. + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_Msk = 0x38 + + // BACKUP_BUS_PMS_MONITOR_0: BackUp permission report register 0. + // Position of BACKUP_BUS_PMS_MONITOR_LOCK field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_MONITOR_LOCK field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK_Msk = 0x1 + // Bit BACKUP_BUS_PMS_MONITOR_LOCK. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_BACKUP_BUS_PMS_MONITOR_LOCK = 0x1 + + // BACKUP_BUS_PMS_MONITOR_1: BackUp permission report register 1. + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_Msk = 0x1 + // Bit BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR = 0x1 + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_Pos = 0x1 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_EN field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_Msk = 0x2 + // Bit BACKUP_BUS_PMS_MONITOR_VIOLATE_EN. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN = 0x2 + + // BACKUP_BUS_PMS_MONITOR_2: BackUp permission report register 2. + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_Msk = 0x1 + // Bit BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR = 0x1 + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_Pos = 0x1 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_Msk = 0x6 + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Pos = 0x3 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_Msk = 0x38 + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Pos = 0x6 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_Msk = 0x40 + // Bit BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE = 0x40 + + // BACKUP_BUS_PMS_MONITOR_3: BackUp permission report register 3. + // Position of BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_Pos = 0x0 + // Bit mask of BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR field. + SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_Msk = 0xffffffff + + // EDMA_BOUNDARY_LOCK: EDMA boundary lock register. + // Position of EDMA_BOUNDARY_LOCK field. + SENSITIVE_EDMA_BOUNDARY_LOCK_EDMA_BOUNDARY_LOCK_Pos = 0x0 + // Bit mask of EDMA_BOUNDARY_LOCK field. + SENSITIVE_EDMA_BOUNDARY_LOCK_EDMA_BOUNDARY_LOCK_Msk = 0x1 + // Bit EDMA_BOUNDARY_LOCK. + SENSITIVE_EDMA_BOUNDARY_LOCK_EDMA_BOUNDARY_LOCK = 0x1 + + // EDMA_BOUNDARY_0: EDMA boundary 0 configuration + // Position of EDMA_BOUNDARY_0 field. + SENSITIVE_EDMA_BOUNDARY_0_EDMA_BOUNDARY_0_Pos = 0x0 + // Bit mask of EDMA_BOUNDARY_0 field. + SENSITIVE_EDMA_BOUNDARY_0_EDMA_BOUNDARY_0_Msk = 0x3fff + + // EDMA_BOUNDARY_1: EDMA boundary 1 configuration + // Position of EDMA_BOUNDARY_1 field. + SENSITIVE_EDMA_BOUNDARY_1_EDMA_BOUNDARY_1_Pos = 0x0 + // Bit mask of EDMA_BOUNDARY_1 field. + SENSITIVE_EDMA_BOUNDARY_1_EDMA_BOUNDARY_1_Msk = 0x3fff + + // EDMA_BOUNDARY_2: EDMA boundary 2 configuration + // Position of EDMA_BOUNDARY_2 field. + SENSITIVE_EDMA_BOUNDARY_2_EDMA_BOUNDARY_2_Pos = 0x0 + // Bit mask of EDMA_BOUNDARY_2 field. + SENSITIVE_EDMA_BOUNDARY_2_EDMA_BOUNDARY_2_Msk = 0x3fff + + // EDMA_PMS_SPI2_LOCK: EDMA-SPI2 permission lock register. + // Position of EDMA_PMS_SPI2_LOCK field. + SENSITIVE_EDMA_PMS_SPI2_LOCK_EDMA_PMS_SPI2_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_SPI2_LOCK field. + SENSITIVE_EDMA_PMS_SPI2_LOCK_EDMA_PMS_SPI2_LOCK_Msk = 0x1 + // Bit EDMA_PMS_SPI2_LOCK. + SENSITIVE_EDMA_PMS_SPI2_LOCK_EDMA_PMS_SPI2_LOCK = 0x1 + + // EDMA_PMS_SPI2: EDMA-SPI2 permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_SPI2_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_SPI2_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_SPI2_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_SPI2_ATTR2_Msk = 0xc + + // EDMA_PMS_SPI3_LOCK: EDMA-SPI3 permission lock register. + // Position of EDMA_PMS_SPI3_LOCK field. + SENSITIVE_EDMA_PMS_SPI3_LOCK_EDMA_PMS_SPI3_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_SPI3_LOCK field. + SENSITIVE_EDMA_PMS_SPI3_LOCK_EDMA_PMS_SPI3_LOCK_Msk = 0x1 + // Bit EDMA_PMS_SPI3_LOCK. + SENSITIVE_EDMA_PMS_SPI3_LOCK_EDMA_PMS_SPI3_LOCK = 0x1 + + // EDMA_PMS_SPI3: EDMA-SPI3 permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_SPI3_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_SPI3_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_SPI3_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_SPI3_ATTR2_Msk = 0xc + + // EDMA_PMS_UHCI0_LOCK: EDMA-UHCI0 permission lock register. + // Position of EDMA_PMS_UHCI0_LOCK field. + SENSITIVE_EDMA_PMS_UHCI0_LOCK_EDMA_PMS_UHCI0_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_UHCI0_LOCK field. + SENSITIVE_EDMA_PMS_UHCI0_LOCK_EDMA_PMS_UHCI0_LOCK_Msk = 0x1 + // Bit EDMA_PMS_UHCI0_LOCK. + SENSITIVE_EDMA_PMS_UHCI0_LOCK_EDMA_PMS_UHCI0_LOCK = 0x1 + + // EDMA_PMS_UHCI0: EDMA-UHCI0 permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_UHCI0_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_UHCI0_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_UHCI0_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_UHCI0_ATTR2_Msk = 0xc + + // EDMA_PMS_I2S0_LOCK: EDMA-I2S0 permission lock register. + // Position of EDMA_PMS_I2S0_LOCK field. + SENSITIVE_EDMA_PMS_I2S0_LOCK_EDMA_PMS_I2S0_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_I2S0_LOCK field. + SENSITIVE_EDMA_PMS_I2S0_LOCK_EDMA_PMS_I2S0_LOCK_Msk = 0x1 + // Bit EDMA_PMS_I2S0_LOCK. + SENSITIVE_EDMA_PMS_I2S0_LOCK_EDMA_PMS_I2S0_LOCK = 0x1 + + // EDMA_PMS_I2S0: EDMA-I2S0 permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_I2S0_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_I2S0_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_I2S0_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_I2S0_ATTR2_Msk = 0xc + + // EDMA_PMS_I2S1_LOCK: EDMA-I2S1 permission lock register. + // Position of EDMA_PMS_I2S1_LOCK field. + SENSITIVE_EDMA_PMS_I2S1_LOCK_EDMA_PMS_I2S1_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_I2S1_LOCK field. + SENSITIVE_EDMA_PMS_I2S1_LOCK_EDMA_PMS_I2S1_LOCK_Msk = 0x1 + // Bit EDMA_PMS_I2S1_LOCK. + SENSITIVE_EDMA_PMS_I2S1_LOCK_EDMA_PMS_I2S1_LOCK = 0x1 + + // EDMA_PMS_I2S1: EDMA-I2S1 permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_I2S1_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_I2S1_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_I2S1_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_I2S1_ATTR2_Msk = 0xc + + // EDMA_PMS_LCD_CAM_LOCK: EDMA-LCD/CAM permission lock register. + // Position of EDMA_PMS_LCD_CAM_LOCK field. + SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_EDMA_PMS_LCD_CAM_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_LCD_CAM_LOCK field. + SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_EDMA_PMS_LCD_CAM_LOCK_Msk = 0x1 + // Bit EDMA_PMS_LCD_CAM_LOCK. + SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_EDMA_PMS_LCD_CAM_LOCK = 0x1 + + // EDMA_PMS_LCD_CAM: EDMA-LCD/CAM permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_Msk = 0xc + + // EDMA_PMS_AES_LOCK: EDMA-AES permission lock register. + // Position of EDMA_PMS_AES_LOCK field. + SENSITIVE_EDMA_PMS_AES_LOCK_EDMA_PMS_AES_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_AES_LOCK field. + SENSITIVE_EDMA_PMS_AES_LOCK_EDMA_PMS_AES_LOCK_Msk = 0x1 + // Bit EDMA_PMS_AES_LOCK. + SENSITIVE_EDMA_PMS_AES_LOCK_EDMA_PMS_AES_LOCK = 0x1 + + // EDMA_PMS_AES: EDMA-AES permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_AES_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_AES_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_AES_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_AES_ATTR2_Msk = 0xc + + // EDMA_PMS_SHA_LOCK: EDMA-SHA permission lock register. + // Position of EDMA_PMS_SHA_LOCK field. + SENSITIVE_EDMA_PMS_SHA_LOCK_EDMA_PMS_SHA_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_SHA_LOCK field. + SENSITIVE_EDMA_PMS_SHA_LOCK_EDMA_PMS_SHA_LOCK_Msk = 0x1 + // Bit EDMA_PMS_SHA_LOCK. + SENSITIVE_EDMA_PMS_SHA_LOCK_EDMA_PMS_SHA_LOCK = 0x1 + + // EDMA_PMS_SHA: EDMA-SHA permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_SHA_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_SHA_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_SHA_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_SHA_ATTR2_Msk = 0xc + + // EDMA_PMS_ADC_DAC_LOCK: EDMA-ADC/DAC permission lock register. + // Position of EDMA_PMS_ADC_DAC_LOCK field. + SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_EDMA_PMS_ADC_DAC_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_ADC_DAC_LOCK field. + SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_EDMA_PMS_ADC_DAC_LOCK_Msk = 0x1 + // Bit EDMA_PMS_ADC_DAC_LOCK. + SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_EDMA_PMS_ADC_DAC_LOCK = 0x1 + + // EDMA_PMS_ADC_DAC: EDMA-ADC/DAC permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_Msk = 0xc + + // EDMA_PMS_RMT_LOCK: EDMA-RMT permission lock register. + // Position of EDMA_PMS_RMT_LOCK field. + SENSITIVE_EDMA_PMS_RMT_LOCK_EDMA_PMS_RMT_LOCK_Pos = 0x0 + // Bit mask of EDMA_PMS_RMT_LOCK field. + SENSITIVE_EDMA_PMS_RMT_LOCK_EDMA_PMS_RMT_LOCK_Msk = 0x1 + // Bit EDMA_PMS_RMT_LOCK. + SENSITIVE_EDMA_PMS_RMT_LOCK_EDMA_PMS_RMT_LOCK = 0x1 + + // EDMA_PMS_RMT: EDMA-RMT permission control register. + // Position of ATTR1 field. + SENSITIVE_EDMA_PMS_RMT_ATTR1_Pos = 0x0 + // Bit mask of ATTR1 field. + SENSITIVE_EDMA_PMS_RMT_ATTR1_Msk = 0x3 + // Position of ATTR2 field. + SENSITIVE_EDMA_PMS_RMT_ATTR2_Pos = 0x2 + // Bit mask of ATTR2 field. + SENSITIVE_EDMA_PMS_RMT_ATTR2_Msk = 0xc + + // CLOCK_GATE: Sensitive module clock gate configuration register. + // Position of REG_CLK_EN field. + SENSITIVE_CLOCK_GATE_REG_CLK_EN_Pos = 0x0 + // Bit mask of REG_CLK_EN field. + SENSITIVE_CLOCK_GATE_REG_CLK_EN_Msk = 0x1 + // Bit REG_CLK_EN. + SENSITIVE_CLOCK_GATE_REG_CLK_EN = 0x1 + + // RTC_PMS: RTC coprocessor permission register. + // Position of DIS_RTC_CPU field. + SENSITIVE_RTC_PMS_DIS_RTC_CPU_Pos = 0x0 + // Bit mask of DIS_RTC_CPU field. + SENSITIVE_RTC_PMS_DIS_RTC_CPU_Msk = 0x1 + // Bit DIS_RTC_CPU. + SENSITIVE_RTC_PMS_DIS_RTC_CPU = 0x1 + + // DATE: Sensitive version register. + // Position of DATE field. + SENSITIVE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SENSITIVE_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SHA: SHA (Secure Hash Algorithm) Accelerator +const ( + // MODE: Initial configuration register. + // Position of MODE field. + SHA_MODE_MODE_Pos = 0x0 + // Bit mask of MODE field. + SHA_MODE_MODE_Msk = 0x7 + + // T_STRING: SHA 512/t configuration register 0. + // Position of T_STRING field. + SHA_T_STRING_T_STRING_Pos = 0x0 + // Bit mask of T_STRING field. + SHA_T_STRING_T_STRING_Msk = 0xffffffff + + // T_LENGTH: SHA 512/t configuration register 1. + // Position of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Pos = 0x0 + // Bit mask of T_LENGTH field. + SHA_T_LENGTH_T_LENGTH_Msk = 0x3f + + // DMA_BLOCK_NUM: DMA configuration register 0. + // Position of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Pos = 0x0 + // Bit mask of DMA_BLOCK_NUM field. + SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Msk = 0x3f + + // START: Typical SHA configuration register 0. + // Position of START field. + SHA_START_START_Pos = 0x1 + // Bit mask of START field. + SHA_START_START_Msk = 0xfffffffe + + // CONTINUE: Typical SHA configuration register 1. + // Position of CONTINUE field. + SHA_CONTINUE_CONTINUE_Pos = 0x1 + // Bit mask of CONTINUE field. + SHA_CONTINUE_CONTINUE_Msk = 0xfffffffe + + // BUSY: Busy register. + // Position of STATE field. + SHA_BUSY_STATE_Pos = 0x0 + // Bit mask of STATE field. + SHA_BUSY_STATE_Msk = 0x1 + // Bit STATE. + SHA_BUSY_STATE = 0x1 + + // DMA_START: DMA configuration register 1. + // Position of DMA_START field. + SHA_DMA_START_DMA_START_Pos = 0x0 + // Bit mask of DMA_START field. + SHA_DMA_START_DMA_START_Msk = 0x1 + // Bit DMA_START. + SHA_DMA_START_DMA_START = 0x1 + + // DMA_CONTINUE: DMA configuration register 2. + // Position of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Pos = 0x0 + // Bit mask of DMA_CONTINUE field. + SHA_DMA_CONTINUE_DMA_CONTINUE_Msk = 0x1 + // Bit DMA_CONTINUE. + SHA_DMA_CONTINUE_DMA_CONTINUE = 0x1 + + // CLEAR_IRQ: Interrupt clear register. + // Position of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Pos = 0x0 + // Bit mask of CLEAR_INTERRUPT field. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Msk = 0x1 + // Bit CLEAR_INTERRUPT. + SHA_CLEAR_IRQ_CLEAR_INTERRUPT = 0x1 + + // IRQ_ENA: Interrupt enable register. + // Position of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Pos = 0x0 + // Bit mask of INTERRUPT_ENA field. + SHA_IRQ_ENA_INTERRUPT_ENA_Msk = 0x1 + // Bit INTERRUPT_ENA. + SHA_IRQ_ENA_INTERRUPT_ENA = 0x1 + + // DATE: Date register. + // Position of DATE field. + SHA_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SHA_DATE_DATE_Msk = 0x3fffffff +) + +// Constants for SPI0: SPI (Serial Peripheral Interface) Controller 0 +const ( + // CTRL: SPI0 control register. + // Position of FDUMMY_OUT field. + SPI0_CTRL_FDUMMY_OUT_Pos = 0x3 + // Bit mask of FDUMMY_OUT field. + SPI0_CTRL_FDUMMY_OUT_Msk = 0x8 + // Bit FDUMMY_OUT. + SPI0_CTRL_FDUMMY_OUT = 0x8 + // Position of FDOUT_OCT field. + SPI0_CTRL_FDOUT_OCT_Pos = 0x4 + // Bit mask of FDOUT_OCT field. + SPI0_CTRL_FDOUT_OCT_Msk = 0x10 + // Bit FDOUT_OCT. + SPI0_CTRL_FDOUT_OCT = 0x10 + // Position of FDIN_OCT field. + SPI0_CTRL_FDIN_OCT_Pos = 0x5 + // Bit mask of FDIN_OCT field. + SPI0_CTRL_FDIN_OCT_Msk = 0x20 + // Bit FDIN_OCT. + SPI0_CTRL_FDIN_OCT = 0x20 + // Position of FADDR_OCT field. + SPI0_CTRL_FADDR_OCT_Pos = 0x6 + // Bit mask of FADDR_OCT field. + SPI0_CTRL_FADDR_OCT_Msk = 0x40 + // Bit FADDR_OCT. + SPI0_CTRL_FADDR_OCT = 0x40 + // Position of FCMD_DUAL field. + SPI0_CTRL_FCMD_DUAL_Pos = 0x7 + // Bit mask of FCMD_DUAL field. + SPI0_CTRL_FCMD_DUAL_Msk = 0x80 + // Bit FCMD_DUAL. + SPI0_CTRL_FCMD_DUAL = 0x80 + // Position of FCMD_QUAD field. + SPI0_CTRL_FCMD_QUAD_Pos = 0x8 + // Bit mask of FCMD_QUAD field. + SPI0_CTRL_FCMD_QUAD_Msk = 0x100 + // Bit FCMD_QUAD. + SPI0_CTRL_FCMD_QUAD = 0x100 + // Position of FCMD_OCT field. + SPI0_CTRL_FCMD_OCT_Pos = 0x9 + // Bit mask of FCMD_OCT field. + SPI0_CTRL_FCMD_OCT_Msk = 0x200 + // Bit FCMD_OCT. + SPI0_CTRL_FCMD_OCT = 0x200 + // Position of FASTRD_MODE field. + SPI0_CTRL_FASTRD_MODE_Pos = 0xd + // Bit mask of FASTRD_MODE field. + SPI0_CTRL_FASTRD_MODE_Msk = 0x2000 + // Bit FASTRD_MODE. + SPI0_CTRL_FASTRD_MODE = 0x2000 + // Position of FREAD_DUAL field. + SPI0_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI0_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI0_CTRL_FREAD_DUAL = 0x4000 + // Position of Q_POL field. + SPI0_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI0_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI0_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI0_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI0_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI0_CTRL_D_POL = 0x80000 + // Position of FREAD_QUAD field. + SPI0_CTRL_FREAD_QUAD_Pos = 0x14 + // Bit mask of FREAD_QUAD field. + SPI0_CTRL_FREAD_QUAD_Msk = 0x100000 + // Bit FREAD_QUAD. + SPI0_CTRL_FREAD_QUAD = 0x100000 + // Position of WP field. + SPI0_CTRL_WP_Pos = 0x15 + // Bit mask of WP field. + SPI0_CTRL_WP_Msk = 0x200000 + // Bit WP. + SPI0_CTRL_WP = 0x200000 + // Position of FREAD_DIO field. + SPI0_CTRL_FREAD_DIO_Pos = 0x17 + // Bit mask of FREAD_DIO field. + SPI0_CTRL_FREAD_DIO_Msk = 0x800000 + // Bit FREAD_DIO. + SPI0_CTRL_FREAD_DIO = 0x800000 + // Position of FREAD_QIO field. + SPI0_CTRL_FREAD_QIO_Pos = 0x18 + // Bit mask of FREAD_QIO field. + SPI0_CTRL_FREAD_QIO_Msk = 0x1000000 + // Bit FREAD_QIO. + SPI0_CTRL_FREAD_QIO = 0x1000000 + + // CTRL1: SPI0 control 1 register. + // Position of CLK_MODE field. + SPI0_CTRL1_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI0_CTRL1_CLK_MODE_Msk = 0x3 + // Position of RXFIFO_RST field. + SPI0_CTRL1_RXFIFO_RST_Pos = 0x1e + // Bit mask of RXFIFO_RST field. + SPI0_CTRL1_RXFIFO_RST_Msk = 0x40000000 + // Bit RXFIFO_RST. + SPI0_CTRL1_RXFIFO_RST = 0x40000000 + + // CTRL2: SPI0 control 2 register. + // Position of CS_SETUP_TIME field. + SPI0_CTRL2_CS_SETUP_TIME_Pos = 0x0 + // Bit mask of CS_SETUP_TIME field. + SPI0_CTRL2_CS_SETUP_TIME_Msk = 0x1f + // Position of CS_HOLD_TIME field. + SPI0_CTRL2_CS_HOLD_TIME_Pos = 0x5 + // Bit mask of CS_HOLD_TIME field. + SPI0_CTRL2_CS_HOLD_TIME_Msk = 0x3e0 + // Position of ECC_CS_HOLD_TIME field. + SPI0_CTRL2_ECC_CS_HOLD_TIME_Pos = 0xa + // Bit mask of ECC_CS_HOLD_TIME field. + SPI0_CTRL2_ECC_CS_HOLD_TIME_Msk = 0x1c00 + // Position of ECC_SKIP_PAGE_CORNER field. + SPI0_CTRL2_ECC_SKIP_PAGE_CORNER_Pos = 0xd + // Bit mask of ECC_SKIP_PAGE_CORNER field. + SPI0_CTRL2_ECC_SKIP_PAGE_CORNER_Msk = 0x2000 + // Bit ECC_SKIP_PAGE_CORNER. + SPI0_CTRL2_ECC_SKIP_PAGE_CORNER = 0x2000 + // Position of ECC_16TO18_BYTE_EN field. + SPI0_CTRL2_ECC_16TO18_BYTE_EN_Pos = 0xe + // Bit mask of ECC_16TO18_BYTE_EN field. + SPI0_CTRL2_ECC_16TO18_BYTE_EN_Msk = 0x4000 + // Bit ECC_16TO18_BYTE_EN. + SPI0_CTRL2_ECC_16TO18_BYTE_EN = 0x4000 + // Position of CS_HOLD_DELAY field. + SPI0_CTRL2_CS_HOLD_DELAY_Pos = 0x19 + // Bit mask of CS_HOLD_DELAY field. + SPI0_CTRL2_CS_HOLD_DELAY_Msk = 0x7e000000 + // Position of SYNC_RESET field. + SPI0_CTRL2_SYNC_RESET_Pos = 0x1f + // Bit mask of SYNC_RESET field. + SPI0_CTRL2_SYNC_RESET_Msk = 0x80000000 + // Bit SYNC_RESET. + SPI0_CTRL2_SYNC_RESET = 0x80000000 + + // CLOCK: SPI_CLK clock division register when SPI0 accesses to flash. + // Position of CLKCNT_L field. + SPI0_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI0_CLOCK_CLKCNT_L_Msk = 0xff + // Position of CLKCNT_H field. + SPI0_CLOCK_CLKCNT_H_Pos = 0x8 + // Bit mask of CLKCNT_H field. + SPI0_CLOCK_CLKCNT_H_Msk = 0xff00 + // Position of CLKCNT_N field. + SPI0_CLOCK_CLKCNT_N_Pos = 0x10 + // Bit mask of CLKCNT_N field. + SPI0_CLOCK_CLKCNT_N_Msk = 0xff0000 + // Position of CLK_EQU_SYSCLK field. + SPI0_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI0_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI0_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI0 user register. + // Position of CS_HOLD field. + SPI0_USER_CS_HOLD_Pos = 0x6 + // Bit mask of CS_HOLD field. + SPI0_USER_CS_HOLD_Msk = 0x40 + // Bit CS_HOLD. + SPI0_USER_CS_HOLD = 0x40 + // Position of CS_SETUP field. + SPI0_USER_CS_SETUP_Pos = 0x7 + // Bit mask of CS_SETUP field. + SPI0_USER_CS_SETUP_Msk = 0x80 + // Bit CS_SETUP. + SPI0_USER_CS_SETUP = 0x80 + // Position of CK_OUT_EDGE field. + SPI0_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI0_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI0_USER_CK_OUT_EDGE = 0x200 + // Position of USR_DUMMY_IDLE field. + SPI0_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI0_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI0_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_DUMMY field. + SPI0_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI0_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI0_USER_USR_DUMMY = 0x20000000 + + // USER1: SPI0 user1 register. + // Position of USR_DUMMY_CYCLELEN field. + SPI0_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI0_USER1_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of USR_ADDR_BITLEN field. + SPI0_USER1_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of USR_ADDR_BITLEN field. + SPI0_USER1_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // USER2: SPI0 user2 register. + // Position of USR_COMMAND_VALUE field. + SPI0_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI0_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of USR_COMMAND_BITLEN field. + SPI0_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI0_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // RD_STATUS: SPI0 read control register. + // Position of WB_MODE field. + SPI0_RD_STATUS_WB_MODE_Pos = 0x10 + // Bit mask of WB_MODE field. + SPI0_RD_STATUS_WB_MODE_Msk = 0xff0000 + + // EXT_ADDR: SPI0 extended address register. + // Position of EXT_ADDR field. + SPI0_EXT_ADDR_EXT_ADDR_Pos = 0x0 + // Bit mask of EXT_ADDR field. + SPI0_EXT_ADDR_EXT_ADDR_Msk = 0xffffffff + + // MISC: SPI0 misc register + // Position of FSUB_PIN field. + SPI0_MISC_FSUB_PIN_Pos = 0x7 + // Bit mask of FSUB_PIN field. + SPI0_MISC_FSUB_PIN_Msk = 0x80 + // Bit FSUB_PIN. + SPI0_MISC_FSUB_PIN = 0x80 + // Position of SSUB_PIN field. + SPI0_MISC_SSUB_PIN_Pos = 0x8 + // Bit mask of SSUB_PIN field. + SPI0_MISC_SSUB_PIN_Msk = 0x100 + // Bit SSUB_PIN. + SPI0_MISC_SSUB_PIN = 0x100 + // Position of CK_IDLE_EDGE field. + SPI0_MISC_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of CK_IDLE_EDGE field. + SPI0_MISC_CK_IDLE_EDGE_Msk = 0x200 + // Bit CK_IDLE_EDGE. + SPI0_MISC_CK_IDLE_EDGE = 0x200 + // Position of CS_KEEP_ACTIVE field. + SPI0_MISC_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of CS_KEEP_ACTIVE field. + SPI0_MISC_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit CS_KEEP_ACTIVE. + SPI0_MISC_CS_KEEP_ACTIVE = 0x400 + + // CACHE_FCTRL: SPI0 external RAM bit mode control register. + // Position of CACHE_REQ_EN field. + SPI0_CACHE_FCTRL_CACHE_REQ_EN_Pos = 0x0 + // Bit mask of CACHE_REQ_EN field. + SPI0_CACHE_FCTRL_CACHE_REQ_EN_Msk = 0x1 + // Bit CACHE_REQ_EN. + SPI0_CACHE_FCTRL_CACHE_REQ_EN = 0x1 + // Position of CACHE_USR_CMD_4BYTE field. + SPI0_CACHE_FCTRL_CACHE_USR_CMD_4BYTE_Pos = 0x1 + // Bit mask of CACHE_USR_CMD_4BYTE field. + SPI0_CACHE_FCTRL_CACHE_USR_CMD_4BYTE_Msk = 0x2 + // Bit CACHE_USR_CMD_4BYTE. + SPI0_CACHE_FCTRL_CACHE_USR_CMD_4BYTE = 0x2 + // Position of CACHE_FLASH_USR_CMD field. + SPI0_CACHE_FCTRL_CACHE_FLASH_USR_CMD_Pos = 0x2 + // Bit mask of CACHE_FLASH_USR_CMD field. + SPI0_CACHE_FCTRL_CACHE_FLASH_USR_CMD_Msk = 0x4 + // Bit CACHE_FLASH_USR_CMD. + SPI0_CACHE_FCTRL_CACHE_FLASH_USR_CMD = 0x4 + // Position of FDIN_DUAL field. + SPI0_CACHE_FCTRL_FDIN_DUAL_Pos = 0x3 + // Bit mask of FDIN_DUAL field. + SPI0_CACHE_FCTRL_FDIN_DUAL_Msk = 0x8 + // Bit FDIN_DUAL. + SPI0_CACHE_FCTRL_FDIN_DUAL = 0x8 + // Position of FDOUT_DUAL field. + SPI0_CACHE_FCTRL_FDOUT_DUAL_Pos = 0x4 + // Bit mask of FDOUT_DUAL field. + SPI0_CACHE_FCTRL_FDOUT_DUAL_Msk = 0x10 + // Bit FDOUT_DUAL. + SPI0_CACHE_FCTRL_FDOUT_DUAL = 0x10 + // Position of FADDR_DUAL field. + SPI0_CACHE_FCTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI0_CACHE_FCTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI0_CACHE_FCTRL_FADDR_DUAL = 0x20 + // Position of FDIN_QUAD field. + SPI0_CACHE_FCTRL_FDIN_QUAD_Pos = 0x6 + // Bit mask of FDIN_QUAD field. + SPI0_CACHE_FCTRL_FDIN_QUAD_Msk = 0x40 + // Bit FDIN_QUAD. + SPI0_CACHE_FCTRL_FDIN_QUAD = 0x40 + // Position of FDOUT_QUAD field. + SPI0_CACHE_FCTRL_FDOUT_QUAD_Pos = 0x7 + // Bit mask of FDOUT_QUAD field. + SPI0_CACHE_FCTRL_FDOUT_QUAD_Msk = 0x80 + // Bit FDOUT_QUAD. + SPI0_CACHE_FCTRL_FDOUT_QUAD = 0x80 + // Position of FADDR_QUAD field. + SPI0_CACHE_FCTRL_FADDR_QUAD_Pos = 0x8 + // Bit mask of FADDR_QUAD field. + SPI0_CACHE_FCTRL_FADDR_QUAD_Msk = 0x100 + // Bit FADDR_QUAD. + SPI0_CACHE_FCTRL_FADDR_QUAD = 0x100 + + // CACHE_SCTRL: SPI0 external RAM control register + // Position of CACHE_USR_SCMD_4BYTE field. + SPI0_CACHE_SCTRL_CACHE_USR_SCMD_4BYTE_Pos = 0x0 + // Bit mask of CACHE_USR_SCMD_4BYTE field. + SPI0_CACHE_SCTRL_CACHE_USR_SCMD_4BYTE_Msk = 0x1 + // Bit CACHE_USR_SCMD_4BYTE. + SPI0_CACHE_SCTRL_CACHE_USR_SCMD_4BYTE = 0x1 + // Position of USR_SRAM_DIO field. + SPI0_CACHE_SCTRL_USR_SRAM_DIO_Pos = 0x1 + // Bit mask of USR_SRAM_DIO field. + SPI0_CACHE_SCTRL_USR_SRAM_DIO_Msk = 0x2 + // Bit USR_SRAM_DIO. + SPI0_CACHE_SCTRL_USR_SRAM_DIO = 0x2 + // Position of USR_SRAM_QIO field. + SPI0_CACHE_SCTRL_USR_SRAM_QIO_Pos = 0x2 + // Bit mask of USR_SRAM_QIO field. + SPI0_CACHE_SCTRL_USR_SRAM_QIO_Msk = 0x4 + // Bit USR_SRAM_QIO. + SPI0_CACHE_SCTRL_USR_SRAM_QIO = 0x4 + // Position of USR_WR_SRAM_DUMMY field. + SPI0_CACHE_SCTRL_USR_WR_SRAM_DUMMY_Pos = 0x3 + // Bit mask of USR_WR_SRAM_DUMMY field. + SPI0_CACHE_SCTRL_USR_WR_SRAM_DUMMY_Msk = 0x8 + // Bit USR_WR_SRAM_DUMMY. + SPI0_CACHE_SCTRL_USR_WR_SRAM_DUMMY = 0x8 + // Position of USR_RD_SRAM_DUMMY field. + SPI0_CACHE_SCTRL_USR_RD_SRAM_DUMMY_Pos = 0x4 + // Bit mask of USR_RD_SRAM_DUMMY field. + SPI0_CACHE_SCTRL_USR_RD_SRAM_DUMMY_Msk = 0x10 + // Bit USR_RD_SRAM_DUMMY. + SPI0_CACHE_SCTRL_USR_RD_SRAM_DUMMY = 0x10 + // Position of CACHE_SRAM_USR_RCMD field. + SPI0_CACHE_SCTRL_CACHE_SRAM_USR_RCMD_Pos = 0x5 + // Bit mask of CACHE_SRAM_USR_RCMD field. + SPI0_CACHE_SCTRL_CACHE_SRAM_USR_RCMD_Msk = 0x20 + // Bit CACHE_SRAM_USR_RCMD. + SPI0_CACHE_SCTRL_CACHE_SRAM_USR_RCMD = 0x20 + // Position of SRAM_RDUMMY_CYCLELEN field. + SPI0_CACHE_SCTRL_SRAM_RDUMMY_CYCLELEN_Pos = 0x6 + // Bit mask of SRAM_RDUMMY_CYCLELEN field. + SPI0_CACHE_SCTRL_SRAM_RDUMMY_CYCLELEN_Msk = 0xfc0 + // Position of SRAM_ADDR_BITLEN field. + SPI0_CACHE_SCTRL_SRAM_ADDR_BITLEN_Pos = 0xe + // Bit mask of SRAM_ADDR_BITLEN field. + SPI0_CACHE_SCTRL_SRAM_ADDR_BITLEN_Msk = 0xfc000 + // Position of CACHE_SRAM_USR_WCMD field. + SPI0_CACHE_SCTRL_CACHE_SRAM_USR_WCMD_Pos = 0x14 + // Bit mask of CACHE_SRAM_USR_WCMD field. + SPI0_CACHE_SCTRL_CACHE_SRAM_USR_WCMD_Msk = 0x100000 + // Bit CACHE_SRAM_USR_WCMD. + SPI0_CACHE_SCTRL_CACHE_SRAM_USR_WCMD = 0x100000 + // Position of SRAM_OCT field. + SPI0_CACHE_SCTRL_SRAM_OCT_Pos = 0x15 + // Bit mask of SRAM_OCT field. + SPI0_CACHE_SCTRL_SRAM_OCT_Msk = 0x200000 + // Bit SRAM_OCT. + SPI0_CACHE_SCTRL_SRAM_OCT = 0x200000 + // Position of SRAM_WDUMMY_CYCLELEN field. + SPI0_CACHE_SCTRL_SRAM_WDUMMY_CYCLELEN_Pos = 0x16 + // Bit mask of SRAM_WDUMMY_CYCLELEN field. + SPI0_CACHE_SCTRL_SRAM_WDUMMY_CYCLELEN_Msk = 0xfc00000 + + // SRAM_CMD: SPI0 external RAM mode control register + // Position of SCLK_MODE field. + SPI0_SRAM_CMD_SCLK_MODE_Pos = 0x0 + // Bit mask of SCLK_MODE field. + SPI0_SRAM_CMD_SCLK_MODE_Msk = 0x3 + // Position of SWB_MODE field. + SPI0_SRAM_CMD_SWB_MODE_Pos = 0x2 + // Bit mask of SWB_MODE field. + SPI0_SRAM_CMD_SWB_MODE_Msk = 0x3fc + // Position of SDIN_DUAL field. + SPI0_SRAM_CMD_SDIN_DUAL_Pos = 0xa + // Bit mask of SDIN_DUAL field. + SPI0_SRAM_CMD_SDIN_DUAL_Msk = 0x400 + // Bit SDIN_DUAL. + SPI0_SRAM_CMD_SDIN_DUAL = 0x400 + // Position of SDOUT_DUAL field. + SPI0_SRAM_CMD_SDOUT_DUAL_Pos = 0xb + // Bit mask of SDOUT_DUAL field. + SPI0_SRAM_CMD_SDOUT_DUAL_Msk = 0x800 + // Bit SDOUT_DUAL. + SPI0_SRAM_CMD_SDOUT_DUAL = 0x800 + // Position of SADDR_DUAL field. + SPI0_SRAM_CMD_SADDR_DUAL_Pos = 0xc + // Bit mask of SADDR_DUAL field. + SPI0_SRAM_CMD_SADDR_DUAL_Msk = 0x1000 + // Bit SADDR_DUAL. + SPI0_SRAM_CMD_SADDR_DUAL = 0x1000 + // Position of SCMD_DUAL field. + SPI0_SRAM_CMD_SCMD_DUAL_Pos = 0xd + // Bit mask of SCMD_DUAL field. + SPI0_SRAM_CMD_SCMD_DUAL_Msk = 0x2000 + // Bit SCMD_DUAL. + SPI0_SRAM_CMD_SCMD_DUAL = 0x2000 + // Position of SDIN_QUAD field. + SPI0_SRAM_CMD_SDIN_QUAD_Pos = 0xe + // Bit mask of SDIN_QUAD field. + SPI0_SRAM_CMD_SDIN_QUAD_Msk = 0x4000 + // Bit SDIN_QUAD. + SPI0_SRAM_CMD_SDIN_QUAD = 0x4000 + // Position of SDOUT_QUAD field. + SPI0_SRAM_CMD_SDOUT_QUAD_Pos = 0xf + // Bit mask of SDOUT_QUAD field. + SPI0_SRAM_CMD_SDOUT_QUAD_Msk = 0x8000 + // Bit SDOUT_QUAD. + SPI0_SRAM_CMD_SDOUT_QUAD = 0x8000 + // Position of SADDR_QUAD field. + SPI0_SRAM_CMD_SADDR_QUAD_Pos = 0x10 + // Bit mask of SADDR_QUAD field. + SPI0_SRAM_CMD_SADDR_QUAD_Msk = 0x10000 + // Bit SADDR_QUAD. + SPI0_SRAM_CMD_SADDR_QUAD = 0x10000 + // Position of SCMD_QUAD field. + SPI0_SRAM_CMD_SCMD_QUAD_Pos = 0x11 + // Bit mask of SCMD_QUAD field. + SPI0_SRAM_CMD_SCMD_QUAD_Msk = 0x20000 + // Bit SCMD_QUAD. + SPI0_SRAM_CMD_SCMD_QUAD = 0x20000 + // Position of SDIN_OCT field. + SPI0_SRAM_CMD_SDIN_OCT_Pos = 0x12 + // Bit mask of SDIN_OCT field. + SPI0_SRAM_CMD_SDIN_OCT_Msk = 0x40000 + // Bit SDIN_OCT. + SPI0_SRAM_CMD_SDIN_OCT = 0x40000 + // Position of SDOUT_OCT field. + SPI0_SRAM_CMD_SDOUT_OCT_Pos = 0x13 + // Bit mask of SDOUT_OCT field. + SPI0_SRAM_CMD_SDOUT_OCT_Msk = 0x80000 + // Bit SDOUT_OCT. + SPI0_SRAM_CMD_SDOUT_OCT = 0x80000 + // Position of SADDR_OCT field. + SPI0_SRAM_CMD_SADDR_OCT_Pos = 0x14 + // Bit mask of SADDR_OCT field. + SPI0_SRAM_CMD_SADDR_OCT_Msk = 0x100000 + // Bit SADDR_OCT. + SPI0_SRAM_CMD_SADDR_OCT = 0x100000 + // Position of SCMD_OCT field. + SPI0_SRAM_CMD_SCMD_OCT_Pos = 0x15 + // Bit mask of SCMD_OCT field. + SPI0_SRAM_CMD_SCMD_OCT_Msk = 0x200000 + // Bit SCMD_OCT. + SPI0_SRAM_CMD_SCMD_OCT = 0x200000 + // Position of SDUMMY_OUT field. + SPI0_SRAM_CMD_SDUMMY_OUT_Pos = 0x16 + // Bit mask of SDUMMY_OUT field. + SPI0_SRAM_CMD_SDUMMY_OUT_Msk = 0x400000 + // Bit SDUMMY_OUT. + SPI0_SRAM_CMD_SDUMMY_OUT = 0x400000 + + // SRAM_DRD_CMD: SPI0 external RAM DDR read command control register + // Position of CACHE_SRAM_USR_RD_CMD_VALUE field. + SPI0_SRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_VALUE_Pos = 0x0 + // Bit mask of CACHE_SRAM_USR_RD_CMD_VALUE field. + SPI0_SRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_VALUE_Msk = 0xffff + // Position of CACHE_SRAM_USR_RD_CMD_BITLEN field. + SPI0_SRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_BITLEN_Pos = 0x1c + // Bit mask of CACHE_SRAM_USR_RD_CMD_BITLEN field. + SPI0_SRAM_DRD_CMD_CACHE_SRAM_USR_RD_CMD_BITLEN_Msk = 0xf0000000 + + // SRAM_DWR_CMD: SPI0 external RAM DDR write command control register + // Position of CACHE_SRAM_USR_WR_CMD_VALUE field. + SPI0_SRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_VALUE_Pos = 0x0 + // Bit mask of CACHE_SRAM_USR_WR_CMD_VALUE field. + SPI0_SRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_VALUE_Msk = 0xffff + // Position of CACHE_SRAM_USR_WR_CMD_BITLEN field. + SPI0_SRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_BITLEN_Pos = 0x1c + // Bit mask of CACHE_SRAM_USR_WR_CMD_BITLEN field. + SPI0_SRAM_DWR_CMD_CACHE_SRAM_USR_WR_CMD_BITLEN_Msk = 0xf0000000 + + // SRAM_CLK: SPI_CLK clock division register when SPI0 accesses to Ext_RAM. + // Position of SCLKCNT_L field. + SPI0_SRAM_CLK_SCLKCNT_L_Pos = 0x0 + // Bit mask of SCLKCNT_L field. + SPI0_SRAM_CLK_SCLKCNT_L_Msk = 0xff + // Position of SCLKCNT_H field. + SPI0_SRAM_CLK_SCLKCNT_H_Pos = 0x8 + // Bit mask of SCLKCNT_H field. + SPI0_SRAM_CLK_SCLKCNT_H_Msk = 0xff00 + // Position of SCLKCNT_N field. + SPI0_SRAM_CLK_SCLKCNT_N_Pos = 0x10 + // Bit mask of SCLKCNT_N field. + SPI0_SRAM_CLK_SCLKCNT_N_Msk = 0xff0000 + // Position of SCLK_EQU_SYSCLK field. + SPI0_SRAM_CLK_SCLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of SCLK_EQU_SYSCLK field. + SPI0_SRAM_CLK_SCLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit SCLK_EQU_SYSCLK. + SPI0_SRAM_CLK_SCLK_EQU_SYSCLK = 0x80000000 + + // FSM: SPI0 state machine(FSM) status register. + // Position of ST field. + SPI0_FSM_ST_Pos = 0x0 + // Bit mask of ST field. + SPI0_FSM_ST_Msk = 0x7 + + // TIMING_CALI: SPI0 timing compensation register when accesses to flash. + // Position of TIMING_CLK_ENA field. + SPI0_TIMING_CALI_TIMING_CLK_ENA_Pos = 0x0 + // Bit mask of TIMING_CLK_ENA field. + SPI0_TIMING_CALI_TIMING_CLK_ENA_Msk = 0x1 + // Bit TIMING_CLK_ENA. + SPI0_TIMING_CALI_TIMING_CLK_ENA = 0x1 + // Position of TIMING_CALI field. + SPI0_TIMING_CALI_TIMING_CALI_Pos = 0x1 + // Bit mask of TIMING_CALI field. + SPI0_TIMING_CALI_TIMING_CALI_Msk = 0x2 + // Bit TIMING_CALI. + SPI0_TIMING_CALI_TIMING_CALI = 0x2 + // Position of EXTRA_DUMMY_CYCLELEN field. + SPI0_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of EXTRA_DUMMY_CYCLELEN field. + SPI0_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + + // DIN_MODE: MSPI input timing delay mode control register when accesses to flash. + // Position of DIN0_MODE field. + SPI0_DIN_MODE_DIN0_MODE_Pos = 0x0 + // Bit mask of DIN0_MODE field. + SPI0_DIN_MODE_DIN0_MODE_Msk = 0x7 + // Position of DIN1_MODE field. + SPI0_DIN_MODE_DIN1_MODE_Pos = 0x3 + // Bit mask of DIN1_MODE field. + SPI0_DIN_MODE_DIN1_MODE_Msk = 0x38 + // Position of DIN2_MODE field. + SPI0_DIN_MODE_DIN2_MODE_Pos = 0x6 + // Bit mask of DIN2_MODE field. + SPI0_DIN_MODE_DIN2_MODE_Msk = 0x1c0 + // Position of DIN3_MODE field. + SPI0_DIN_MODE_DIN3_MODE_Pos = 0x9 + // Bit mask of DIN3_MODE field. + SPI0_DIN_MODE_DIN3_MODE_Msk = 0xe00 + // Position of DIN4_MODE field. + SPI0_DIN_MODE_DIN4_MODE_Pos = 0xc + // Bit mask of DIN4_MODE field. + SPI0_DIN_MODE_DIN4_MODE_Msk = 0x7000 + // Position of DIN5_MODE field. + SPI0_DIN_MODE_DIN5_MODE_Pos = 0xf + // Bit mask of DIN5_MODE field. + SPI0_DIN_MODE_DIN5_MODE_Msk = 0x38000 + // Position of DIN6_MODE field. + SPI0_DIN_MODE_DIN6_MODE_Pos = 0x12 + // Bit mask of DIN6_MODE field. + SPI0_DIN_MODE_DIN6_MODE_Msk = 0x1c0000 + // Position of DIN7_MODE field. + SPI0_DIN_MODE_DIN7_MODE_Pos = 0x15 + // Bit mask of DIN7_MODE field. + SPI0_DIN_MODE_DIN7_MODE_Msk = 0xe00000 + // Position of DINS_MODE field. + SPI0_DIN_MODE_DINS_MODE_Pos = 0x18 + // Bit mask of DINS_MODE field. + SPI0_DIN_MODE_DINS_MODE_Msk = 0x7000000 + + // DIN_NUM: MSPI input timing delay number control register when accesses to flash. + // Position of DIN0_NUM field. + SPI0_DIN_NUM_DIN0_NUM_Pos = 0x0 + // Bit mask of DIN0_NUM field. + SPI0_DIN_NUM_DIN0_NUM_Msk = 0x3 + // Position of DIN1_NUM field. + SPI0_DIN_NUM_DIN1_NUM_Pos = 0x2 + // Bit mask of DIN1_NUM field. + SPI0_DIN_NUM_DIN1_NUM_Msk = 0xc + // Position of DIN2_NUM field. + SPI0_DIN_NUM_DIN2_NUM_Pos = 0x4 + // Bit mask of DIN2_NUM field. + SPI0_DIN_NUM_DIN2_NUM_Msk = 0x30 + // Position of DIN3_NUM field. + SPI0_DIN_NUM_DIN3_NUM_Pos = 0x6 + // Bit mask of DIN3_NUM field. + SPI0_DIN_NUM_DIN3_NUM_Msk = 0xc0 + // Position of DIN4_NUM field. + SPI0_DIN_NUM_DIN4_NUM_Pos = 0x8 + // Bit mask of DIN4_NUM field. + SPI0_DIN_NUM_DIN4_NUM_Msk = 0x300 + // Position of DIN5_NUM field. + SPI0_DIN_NUM_DIN5_NUM_Pos = 0xa + // Bit mask of DIN5_NUM field. + SPI0_DIN_NUM_DIN5_NUM_Msk = 0xc00 + // Position of DIN6_NUM field. + SPI0_DIN_NUM_DIN6_NUM_Pos = 0xc + // Bit mask of DIN6_NUM field. + SPI0_DIN_NUM_DIN6_NUM_Msk = 0x3000 + // Position of DIN7_NUM field. + SPI0_DIN_NUM_DIN7_NUM_Pos = 0xe + // Bit mask of DIN7_NUM field. + SPI0_DIN_NUM_DIN7_NUM_Msk = 0xc000 + // Position of DINS_NUM field. + SPI0_DIN_NUM_DINS_NUM_Pos = 0x10 + // Bit mask of DINS_NUM field. + SPI0_DIN_NUM_DINS_NUM_Msk = 0x30000 + + // DOUT_MODE: MSPI output timing delay mode control register when accesses to flash. + // Position of DOUT0_MODE field. + SPI0_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + SPI0_DOUT_MODE_DOUT0_MODE_Msk = 0x1 + // Bit DOUT0_MODE. + SPI0_DOUT_MODE_DOUT0_MODE = 0x1 + // Position of DOUT1_MODE field. + SPI0_DOUT_MODE_DOUT1_MODE_Pos = 0x1 + // Bit mask of DOUT1_MODE field. + SPI0_DOUT_MODE_DOUT1_MODE_Msk = 0x2 + // Bit DOUT1_MODE. + SPI0_DOUT_MODE_DOUT1_MODE = 0x2 + // Position of DOUT2_MODE field. + SPI0_DOUT_MODE_DOUT2_MODE_Pos = 0x2 + // Bit mask of DOUT2_MODE field. + SPI0_DOUT_MODE_DOUT2_MODE_Msk = 0x4 + // Bit DOUT2_MODE. + SPI0_DOUT_MODE_DOUT2_MODE = 0x4 + // Position of DOUT3_MODE field. + SPI0_DOUT_MODE_DOUT3_MODE_Pos = 0x3 + // Bit mask of DOUT3_MODE field. + SPI0_DOUT_MODE_DOUT3_MODE_Msk = 0x8 + // Bit DOUT3_MODE. + SPI0_DOUT_MODE_DOUT3_MODE = 0x8 + // Position of DOUT4_MODE field. + SPI0_DOUT_MODE_DOUT4_MODE_Pos = 0x4 + // Bit mask of DOUT4_MODE field. + SPI0_DOUT_MODE_DOUT4_MODE_Msk = 0x10 + // Bit DOUT4_MODE. + SPI0_DOUT_MODE_DOUT4_MODE = 0x10 + // Position of DOUT5_MODE field. + SPI0_DOUT_MODE_DOUT5_MODE_Pos = 0x5 + // Bit mask of DOUT5_MODE field. + SPI0_DOUT_MODE_DOUT5_MODE_Msk = 0x20 + // Bit DOUT5_MODE. + SPI0_DOUT_MODE_DOUT5_MODE = 0x20 + // Position of DOUT6_MODE field. + SPI0_DOUT_MODE_DOUT6_MODE_Pos = 0x6 + // Bit mask of DOUT6_MODE field. + SPI0_DOUT_MODE_DOUT6_MODE_Msk = 0x40 + // Bit DOUT6_MODE. + SPI0_DOUT_MODE_DOUT6_MODE = 0x40 + // Position of DOUT7_MODE field. + SPI0_DOUT_MODE_DOUT7_MODE_Pos = 0x7 + // Bit mask of DOUT7_MODE field. + SPI0_DOUT_MODE_DOUT7_MODE_Msk = 0x80 + // Bit DOUT7_MODE. + SPI0_DOUT_MODE_DOUT7_MODE = 0x80 + // Position of DOUTS_MODE field. + SPI0_DOUT_MODE_DOUTS_MODE_Pos = 0x8 + // Bit mask of DOUTS_MODE field. + SPI0_DOUT_MODE_DOUTS_MODE_Msk = 0x100 + // Bit DOUTS_MODE. + SPI0_DOUT_MODE_DOUTS_MODE = 0x100 + + // SPI_SMEM_TIMING_CALI: SPI0 Ext_RAM timing compensation register. + // Position of SPI_SMEM_TIMING_CLK_ENA field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA_Pos = 0x0 + // Bit mask of SPI_SMEM_TIMING_CLK_ENA field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA_Msk = 0x1 + // Bit SPI_SMEM_TIMING_CLK_ENA. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA = 0x1 + // Position of SPI_SMEM_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI_Pos = 0x1 + // Bit mask of SPI_SMEM_TIMING_CALI field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI_Msk = 0x2 + // Bit SPI_SMEM_TIMING_CALI. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI = 0x2 + // Position of SPI_SMEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of SPI_SMEM_EXTRA_DUMMY_CYCLELEN field. + SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + + // SPI_SMEM_DIN_MODE: MSPI input timing delay mode control register when accesses to Ext_RAM. + // Position of SPI_SMEM_DIN0_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE_Pos = 0x0 + // Bit mask of SPI_SMEM_DIN0_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE_Msk = 0x7 + // Position of SPI_SMEM_DIN1_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE_Pos = 0x3 + // Bit mask of SPI_SMEM_DIN1_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE_Msk = 0x38 + // Position of SPI_SMEM_DIN2_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE_Pos = 0x6 + // Bit mask of SPI_SMEM_DIN2_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE_Msk = 0x1c0 + // Position of SPI_SMEM_DIN3_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE_Pos = 0x9 + // Bit mask of SPI_SMEM_DIN3_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE_Msk = 0xe00 + // Position of SPI_SMEM_DIN4_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE_Pos = 0xc + // Bit mask of SPI_SMEM_DIN4_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE_Msk = 0x7000 + // Position of SPI_SMEM_DIN5_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE_Pos = 0xf + // Bit mask of SPI_SMEM_DIN5_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE_Msk = 0x38000 + // Position of SPI_SMEM_DIN6_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE_Pos = 0x12 + // Bit mask of SPI_SMEM_DIN6_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE_Msk = 0x1c0000 + // Position of SPI_SMEM_DIN7_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE_Pos = 0x15 + // Bit mask of SPI_SMEM_DIN7_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE_Msk = 0xe00000 + // Position of SPI_SMEM_DINS_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE_Pos = 0x18 + // Bit mask of SPI_SMEM_DINS_MODE field. + SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE_Msk = 0x7000000 + + // SPI_SMEM_DIN_NUM: MSPI input timing delay number control register when accesses to Ext_RAM. + // Position of SPI_SMEM_DIN0_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM_Pos = 0x0 + // Bit mask of SPI_SMEM_DIN0_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM_Msk = 0x3 + // Position of SPI_SMEM_DIN1_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM_Pos = 0x2 + // Bit mask of SPI_SMEM_DIN1_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM_Msk = 0xc + // Position of SPI_SMEM_DIN2_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM_Pos = 0x4 + // Bit mask of SPI_SMEM_DIN2_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM_Msk = 0x30 + // Position of SPI_SMEM_DIN3_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM_Pos = 0x6 + // Bit mask of SPI_SMEM_DIN3_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM_Msk = 0xc0 + // Position of SPI_SMEM_DIN4_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM_Pos = 0x8 + // Bit mask of SPI_SMEM_DIN4_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM_Msk = 0x300 + // Position of SPI_SMEM_DIN5_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM_Pos = 0xa + // Bit mask of SPI_SMEM_DIN5_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM_Msk = 0xc00 + // Position of SPI_SMEM_DIN6_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM_Pos = 0xc + // Bit mask of SPI_SMEM_DIN6_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM_Msk = 0x3000 + // Position of SPI_SMEM_DIN7_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM_Pos = 0xe + // Bit mask of SPI_SMEM_DIN7_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM_Msk = 0xc000 + // Position of SPI_SMEM_DINS_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM_Pos = 0x10 + // Bit mask of SPI_SMEM_DINS_NUM field. + SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM_Msk = 0x30000 + + // SPI_SMEM_DOUT_MODE: MSPI output timing delay mode control register when accesses to Ext_RAM. + // Position of SPI_SMEM_DOUT0_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE_Pos = 0x0 + // Bit mask of SPI_SMEM_DOUT0_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE_Msk = 0x1 + // Bit SPI_SMEM_DOUT0_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE = 0x1 + // Position of SPI_SMEM_DOUT1_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE_Pos = 0x1 + // Bit mask of SPI_SMEM_DOUT1_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE_Msk = 0x2 + // Bit SPI_SMEM_DOUT1_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE = 0x2 + // Position of SPI_SMEM_DOUT2_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE_Pos = 0x2 + // Bit mask of SPI_SMEM_DOUT2_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE_Msk = 0x4 + // Bit SPI_SMEM_DOUT2_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE = 0x4 + // Position of SPI_SMEM_DOUT3_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE_Pos = 0x3 + // Bit mask of SPI_SMEM_DOUT3_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE_Msk = 0x8 + // Bit SPI_SMEM_DOUT3_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE = 0x8 + // Position of SPI_SMEM_DOUT4_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE_Pos = 0x4 + // Bit mask of SPI_SMEM_DOUT4_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE_Msk = 0x10 + // Bit SPI_SMEM_DOUT4_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE = 0x10 + // Position of SPI_SMEM_DOUT5_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE_Pos = 0x5 + // Bit mask of SPI_SMEM_DOUT5_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE_Msk = 0x20 + // Bit SPI_SMEM_DOUT5_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE = 0x20 + // Position of SPI_SMEM_DOUT6_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE_Pos = 0x6 + // Bit mask of SPI_SMEM_DOUT6_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE_Msk = 0x40 + // Bit SPI_SMEM_DOUT6_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE = 0x40 + // Position of SPI_SMEM_DOUT7_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE_Pos = 0x7 + // Bit mask of SPI_SMEM_DOUT7_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE_Msk = 0x80 + // Bit SPI_SMEM_DOUT7_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE = 0x80 + // Position of SPI_SMEM_DOUTS_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE_Pos = 0x8 + // Bit mask of SPI_SMEM_DOUTS_MODE field. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE_Msk = 0x100 + // Bit SPI_SMEM_DOUTS_MODE. + SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE = 0x100 + + // ECC_CTRL: MSPI ECC control register + // Position of ECC_ERR_INT_NUM field. + SPI0_ECC_CTRL_ECC_ERR_INT_NUM_Pos = 0x0 + // Bit mask of ECC_ERR_INT_NUM field. + SPI0_ECC_CTRL_ECC_ERR_INT_NUM_Msk = 0xff + // Position of SPI_FMEM_ECC_ERR_INT_EN field. + SPI0_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN_Pos = 0x8 + // Bit mask of SPI_FMEM_ECC_ERR_INT_EN field. + SPI0_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN_Msk = 0x100 + // Bit SPI_FMEM_ECC_ERR_INT_EN. + SPI0_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN = 0x100 + + // ECC_ERR_ADDR: MSPI ECC error address register + // Position of ECC_ERR_ADDR field. + SPI0_ECC_ERR_ADDR_ECC_ERR_ADDR_Pos = 0x0 + // Bit mask of ECC_ERR_ADDR field. + SPI0_ECC_ERR_ADDR_ECC_ERR_ADDR_Msk = 0xffffffff + + // ECC_ERR_BIT: MSPI ECC error bits register + // Position of ECC_DATA_ERR_BIT field. + SPI0_ECC_ERR_BIT_ECC_DATA_ERR_BIT_Pos = 0x6 + // Bit mask of ECC_DATA_ERR_BIT field. + SPI0_ECC_ERR_BIT_ECC_DATA_ERR_BIT_Msk = 0x1fc0 + // Position of ECC_CHK_ERR_BIT field. + SPI0_ECC_ERR_BIT_ECC_CHK_ERR_BIT_Pos = 0xd + // Bit mask of ECC_CHK_ERR_BIT field. + SPI0_ECC_ERR_BIT_ECC_CHK_ERR_BIT_Msk = 0xe000 + // Position of ECC_BYTE_ERR field. + SPI0_ECC_ERR_BIT_ECC_BYTE_ERR_Pos = 0x10 + // Bit mask of ECC_BYTE_ERR field. + SPI0_ECC_ERR_BIT_ECC_BYTE_ERR_Msk = 0x10000 + // Bit ECC_BYTE_ERR. + SPI0_ECC_ERR_BIT_ECC_BYTE_ERR = 0x10000 + // Position of ECC_ERR_CNT field. + SPI0_ECC_ERR_BIT_ECC_ERR_CNT_Pos = 0x11 + // Bit mask of ECC_ERR_CNT field. + SPI0_ECC_ERR_BIT_ECC_ERR_CNT_Msk = 0x1fe0000 + + // SPI_SMEM_AC: MSPI external RAM ECC and SPI CS timing control register + // Position of SPI_SMEM_CS_SETUP field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_Pos = 0x0 + // Bit mask of SPI_SMEM_CS_SETUP field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_Msk = 0x1 + // Bit SPI_SMEM_CS_SETUP. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP = 0x1 + // Position of SPI_SMEM_CS_HOLD field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_Pos = 0x1 + // Bit mask of SPI_SMEM_CS_HOLD field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_Msk = 0x2 + // Bit SPI_SMEM_CS_HOLD. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD = 0x2 + // Position of SPI_SMEM_CS_SETUP_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME_Pos = 0x2 + // Bit mask of SPI_SMEM_CS_SETUP_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME_Msk = 0x7c + // Position of SPI_SMEM_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME_Pos = 0x7 + // Bit mask of SPI_SMEM_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME_Msk = 0xf80 + // Position of SPI_SMEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME_Pos = 0xc + // Bit mask of SPI_SMEM_ECC_CS_HOLD_TIME field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME_Msk = 0x7000 + // Position of SPI_SMEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER_Pos = 0xf + // Bit mask of SPI_SMEM_ECC_SKIP_PAGE_CORNER field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER_Msk = 0x8000 + // Bit SPI_SMEM_ECC_SKIP_PAGE_CORNER. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER = 0x8000 + // Position of SPI_SMEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN_Pos = 0x10 + // Bit mask of SPI_SMEM_ECC_16TO18_BYTE_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN_Msk = 0x10000 + // Bit SPI_SMEM_ECC_16TO18_BYTE_EN. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN = 0x10000 + // Position of SPI_SMEM_ECC_ERR_INT_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_ERR_INT_EN_Pos = 0x18 + // Bit mask of SPI_SMEM_ECC_ERR_INT_EN field. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_ERR_INT_EN_Msk = 0x1000000 + // Bit SPI_SMEM_ECC_ERR_INT_EN. + SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_ERR_INT_EN = 0x1000000 + // Position of SPI_SMEM_CS_HOLD_DELAY field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY_Pos = 0x19 + // Bit mask of SPI_SMEM_CS_HOLD_DELAY field. + SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY_Msk = 0x7e000000 + + // DDR: SPI0 flash DDR mode control register + // Position of SPI_FMEM_DDR_EN field. + SPI0_DDR_SPI_FMEM_DDR_EN_Pos = 0x0 + // Bit mask of SPI_FMEM_DDR_EN field. + SPI0_DDR_SPI_FMEM_DDR_EN_Msk = 0x1 + // Bit SPI_FMEM_DDR_EN. + SPI0_DDR_SPI_FMEM_DDR_EN = 0x1 + // Position of SPI_FMEM_VAR_DUMMY field. + SPI0_DDR_SPI_FMEM_VAR_DUMMY_Pos = 0x1 + // Bit mask of SPI_FMEM_VAR_DUMMY field. + SPI0_DDR_SPI_FMEM_VAR_DUMMY_Msk = 0x2 + // Bit SPI_FMEM_VAR_DUMMY. + SPI0_DDR_SPI_FMEM_VAR_DUMMY = 0x2 + // Position of SPI_FMEM_DDR_RDAT_SWP field. + SPI0_DDR_SPI_FMEM_DDR_RDAT_SWP_Pos = 0x2 + // Bit mask of SPI_FMEM_DDR_RDAT_SWP field. + SPI0_DDR_SPI_FMEM_DDR_RDAT_SWP_Msk = 0x4 + // Bit SPI_FMEM_DDR_RDAT_SWP. + SPI0_DDR_SPI_FMEM_DDR_RDAT_SWP = 0x4 + // Position of SPI_FMEM_DDR_WDAT_SWP field. + SPI0_DDR_SPI_FMEM_DDR_WDAT_SWP_Pos = 0x3 + // Bit mask of SPI_FMEM_DDR_WDAT_SWP field. + SPI0_DDR_SPI_FMEM_DDR_WDAT_SWP_Msk = 0x8 + // Bit SPI_FMEM_DDR_WDAT_SWP. + SPI0_DDR_SPI_FMEM_DDR_WDAT_SWP = 0x8 + // Position of SPI_FMEM_DDR_CMD_DIS field. + SPI0_DDR_SPI_FMEM_DDR_CMD_DIS_Pos = 0x4 + // Bit mask of SPI_FMEM_DDR_CMD_DIS field. + SPI0_DDR_SPI_FMEM_DDR_CMD_DIS_Msk = 0x10 + // Bit SPI_FMEM_DDR_CMD_DIS. + SPI0_DDR_SPI_FMEM_DDR_CMD_DIS = 0x10 + // Position of SPI_FMEM_OUTMINBYTELEN field. + SPI0_DDR_SPI_FMEM_OUTMINBYTELEN_Pos = 0x5 + // Bit mask of SPI_FMEM_OUTMINBYTELEN field. + SPI0_DDR_SPI_FMEM_OUTMINBYTELEN_Msk = 0xfe0 + // Position of SPI_FMEM_TX_DDR_MSK_EN field. + SPI0_DDR_SPI_FMEM_TX_DDR_MSK_EN_Pos = 0xc + // Bit mask of SPI_FMEM_TX_DDR_MSK_EN field. + SPI0_DDR_SPI_FMEM_TX_DDR_MSK_EN_Msk = 0x1000 + // Bit SPI_FMEM_TX_DDR_MSK_EN. + SPI0_DDR_SPI_FMEM_TX_DDR_MSK_EN = 0x1000 + // Position of SPI_FMEM_RX_DDR_MSK_EN field. + SPI0_DDR_SPI_FMEM_RX_DDR_MSK_EN_Pos = 0xd + // Bit mask of SPI_FMEM_RX_DDR_MSK_EN field. + SPI0_DDR_SPI_FMEM_RX_DDR_MSK_EN_Msk = 0x2000 + // Bit SPI_FMEM_RX_DDR_MSK_EN. + SPI0_DDR_SPI_FMEM_RX_DDR_MSK_EN = 0x2000 + // Position of SPI_FMEM_USR_DDR_DQS_THD field. + SPI0_DDR_SPI_FMEM_USR_DDR_DQS_THD_Pos = 0xe + // Bit mask of SPI_FMEM_USR_DDR_DQS_THD field. + SPI0_DDR_SPI_FMEM_USR_DDR_DQS_THD_Msk = 0x1fc000 + // Position of SPI_FMEM_DDR_DQS_LOOP field. + SPI0_DDR_SPI_FMEM_DDR_DQS_LOOP_Pos = 0x15 + // Bit mask of SPI_FMEM_DDR_DQS_LOOP field. + SPI0_DDR_SPI_FMEM_DDR_DQS_LOOP_Msk = 0x200000 + // Bit SPI_FMEM_DDR_DQS_LOOP. + SPI0_DDR_SPI_FMEM_DDR_DQS_LOOP = 0x200000 + // Position of SPI_FMEM_DDR_DQS_LOOP_MODE field. + SPI0_DDR_SPI_FMEM_DDR_DQS_LOOP_MODE_Pos = 0x16 + // Bit mask of SPI_FMEM_DDR_DQS_LOOP_MODE field. + SPI0_DDR_SPI_FMEM_DDR_DQS_LOOP_MODE_Msk = 0x400000 + // Bit SPI_FMEM_DDR_DQS_LOOP_MODE. + SPI0_DDR_SPI_FMEM_DDR_DQS_LOOP_MODE = 0x400000 + // Position of SPI_FMEM_CLK_DIFF_EN field. + SPI0_DDR_SPI_FMEM_CLK_DIFF_EN_Pos = 0x18 + // Bit mask of SPI_FMEM_CLK_DIFF_EN field. + SPI0_DDR_SPI_FMEM_CLK_DIFF_EN_Msk = 0x1000000 + // Bit SPI_FMEM_CLK_DIFF_EN. + SPI0_DDR_SPI_FMEM_CLK_DIFF_EN = 0x1000000 + // Position of SPI_FMEM_HYPERBUS_MODE field. + SPI0_DDR_SPI_FMEM_HYPERBUS_MODE_Pos = 0x19 + // Bit mask of SPI_FMEM_HYPERBUS_MODE field. + SPI0_DDR_SPI_FMEM_HYPERBUS_MODE_Msk = 0x2000000 + // Bit SPI_FMEM_HYPERBUS_MODE. + SPI0_DDR_SPI_FMEM_HYPERBUS_MODE = 0x2000000 + // Position of SPI_FMEM_DQS_CA_IN field. + SPI0_DDR_SPI_FMEM_DQS_CA_IN_Pos = 0x1a + // Bit mask of SPI_FMEM_DQS_CA_IN field. + SPI0_DDR_SPI_FMEM_DQS_CA_IN_Msk = 0x4000000 + // Bit SPI_FMEM_DQS_CA_IN. + SPI0_DDR_SPI_FMEM_DQS_CA_IN = 0x4000000 + // Position of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI0_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b + // Bit mask of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI0_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000 + // Bit SPI_FMEM_HYPERBUS_DUMMY_2X. + SPI0_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X = 0x8000000 + // Position of SPI_FMEM_CLK_DIFF_INV field. + SPI0_DDR_SPI_FMEM_CLK_DIFF_INV_Pos = 0x1c + // Bit mask of SPI_FMEM_CLK_DIFF_INV field. + SPI0_DDR_SPI_FMEM_CLK_DIFF_INV_Msk = 0x10000000 + // Bit SPI_FMEM_CLK_DIFF_INV. + SPI0_DDR_SPI_FMEM_CLK_DIFF_INV = 0x10000000 + // Position of SPI_FMEM_OCTA_RAM_ADDR field. + SPI0_DDR_SPI_FMEM_OCTA_RAM_ADDR_Pos = 0x1d + // Bit mask of SPI_FMEM_OCTA_RAM_ADDR field. + SPI0_DDR_SPI_FMEM_OCTA_RAM_ADDR_Msk = 0x20000000 + // Bit SPI_FMEM_OCTA_RAM_ADDR. + SPI0_DDR_SPI_FMEM_OCTA_RAM_ADDR = 0x20000000 + // Position of SPI_FMEM_HYPERBUS_CA field. + SPI0_DDR_SPI_FMEM_HYPERBUS_CA_Pos = 0x1e + // Bit mask of SPI_FMEM_HYPERBUS_CA field. + SPI0_DDR_SPI_FMEM_HYPERBUS_CA_Msk = 0x40000000 + // Bit SPI_FMEM_HYPERBUS_CA. + SPI0_DDR_SPI_FMEM_HYPERBUS_CA = 0x40000000 + + // SPI_SMEM_DDR: SPI0 external RAM DDR mode control register + // Position of EN field. + SPI0_SPI_SMEM_DDR_EN_Pos = 0x0 + // Bit mask of EN field. + SPI0_SPI_SMEM_DDR_EN_Msk = 0x1 + // Bit EN. + SPI0_SPI_SMEM_DDR_EN = 0x1 + // Position of SPI_SMEM_VAR_DUMMY field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY_Pos = 0x1 + // Bit mask of SPI_SMEM_VAR_DUMMY field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY_Msk = 0x2 + // Bit SPI_SMEM_VAR_DUMMY. + SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY = 0x2 + // Position of RDAT_SWP field. + SPI0_SPI_SMEM_DDR_RDAT_SWP_Pos = 0x2 + // Bit mask of RDAT_SWP field. + SPI0_SPI_SMEM_DDR_RDAT_SWP_Msk = 0x4 + // Bit RDAT_SWP. + SPI0_SPI_SMEM_DDR_RDAT_SWP = 0x4 + // Position of WDAT_SWP field. + SPI0_SPI_SMEM_DDR_WDAT_SWP_Pos = 0x3 + // Bit mask of WDAT_SWP field. + SPI0_SPI_SMEM_DDR_WDAT_SWP_Msk = 0x8 + // Bit WDAT_SWP. + SPI0_SPI_SMEM_DDR_WDAT_SWP = 0x8 + // Position of CMD_DIS field. + SPI0_SPI_SMEM_DDR_CMD_DIS_Pos = 0x4 + // Bit mask of CMD_DIS field. + SPI0_SPI_SMEM_DDR_CMD_DIS_Msk = 0x10 + // Bit CMD_DIS. + SPI0_SPI_SMEM_DDR_CMD_DIS = 0x10 + // Position of SPI_SMEM_OUTMINBYTELEN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN_Pos = 0x5 + // Bit mask of SPI_SMEM_OUTMINBYTELEN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN_Msk = 0xfe0 + // Position of SPI_SMEM_TX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN_Pos = 0xc + // Bit mask of SPI_SMEM_TX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN_Msk = 0x1000 + // Bit SPI_SMEM_TX_DDR_MSK_EN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN = 0x1000 + // Position of SPI_SMEM_RX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN_Pos = 0xd + // Bit mask of SPI_SMEM_RX_DDR_MSK_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN_Msk = 0x2000 + // Bit SPI_SMEM_RX_DDR_MSK_EN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN = 0x2000 + // Position of SPI_SMEM_USR_DDR_DQS_THD field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD_Pos = 0xe + // Bit mask of SPI_SMEM_USR_DDR_DQS_THD field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD_Msk = 0x1fc000 + // Position of DQS_LOOP field. + SPI0_SPI_SMEM_DDR_DQS_LOOP_Pos = 0x15 + // Bit mask of DQS_LOOP field. + SPI0_SPI_SMEM_DDR_DQS_LOOP_Msk = 0x200000 + // Bit DQS_LOOP. + SPI0_SPI_SMEM_DDR_DQS_LOOP = 0x200000 + // Position of DQS_LOOP_MODE field. + SPI0_SPI_SMEM_DDR_DQS_LOOP_MODE_Pos = 0x16 + // Bit mask of DQS_LOOP_MODE field. + SPI0_SPI_SMEM_DDR_DQS_LOOP_MODE_Msk = 0x400000 + // Bit DQS_LOOP_MODE. + SPI0_SPI_SMEM_DDR_DQS_LOOP_MODE = 0x400000 + // Position of SPI_SMEM_CLK_DIFF_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN_Pos = 0x18 + // Bit mask of SPI_SMEM_CLK_DIFF_EN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN_Msk = 0x1000000 + // Bit SPI_SMEM_CLK_DIFF_EN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN = 0x1000000 + // Position of SPI_SMEM_HYPERBUS_MODE field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_MODE_Pos = 0x19 + // Bit mask of SPI_SMEM_HYPERBUS_MODE field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_MODE_Msk = 0x2000000 + // Bit SPI_SMEM_HYPERBUS_MODE. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_MODE = 0x2000000 + // Position of SPI_SMEM_DQS_CA_IN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN_Pos = 0x1a + // Bit mask of SPI_SMEM_DQS_CA_IN field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN_Msk = 0x4000000 + // Bit SPI_SMEM_DQS_CA_IN. + SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN = 0x4000000 + // Position of SPI_SMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b + // Bit mask of SPI_SMEM_HYPERBUS_DUMMY_2X field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000 + // Bit SPI_SMEM_HYPERBUS_DUMMY_2X. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X = 0x8000000 + // Position of SPI_SMEM_CLK_DIFF_INV field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV_Pos = 0x1c + // Bit mask of SPI_SMEM_CLK_DIFF_INV field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV_Msk = 0x10000000 + // Bit SPI_SMEM_CLK_DIFF_INV. + SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV = 0x10000000 + // Position of SPI_SMEM_OCTA_RAM_ADDR field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR_Pos = 0x1d + // Bit mask of SPI_SMEM_OCTA_RAM_ADDR field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR_Msk = 0x20000000 + // Bit SPI_SMEM_OCTA_RAM_ADDR. + SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR = 0x20000000 + // Position of SPI_SMEM_HYPERBUS_CA field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA_Pos = 0x1e + // Bit mask of SPI_SMEM_HYPERBUS_CA field. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA_Msk = 0x40000000 + // Bit SPI_SMEM_HYPERBUS_CA. + SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA = 0x40000000 + + // CLOCK_GATE: SPI0 clk_gate register + // Position of CLK_EN field. + SPI0_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI0_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI0_CLOCK_GATE_CLK_EN = 0x1 + + // CORE_CLK_SEL: SPI0 module clock select register + // Position of CORE_CLK_SEL field. + SPI0_CORE_CLK_SEL_CORE_CLK_SEL_Pos = 0x0 + // Bit mask of CORE_CLK_SEL field. + SPI0_CORE_CLK_SEL_CORE_CLK_SEL_Msk = 0x3 + + // INT_ENA: SPI1 interrupt enable register + // Position of TOTAL_TRANS_END_INT_ENA field. + SPI0_INT_ENA_TOTAL_TRANS_END_INT_ENA_Pos = 0x2 + // Bit mask of TOTAL_TRANS_END_INT_ENA field. + SPI0_INT_ENA_TOTAL_TRANS_END_INT_ENA_Msk = 0x4 + // Bit TOTAL_TRANS_END_INT_ENA. + SPI0_INT_ENA_TOTAL_TRANS_END_INT_ENA = 0x4 + // Position of ECC_ERR_INT_ENA field. + SPI0_INT_ENA_ECC_ERR_INT_ENA_Pos = 0x4 + // Bit mask of ECC_ERR_INT_ENA field. + SPI0_INT_ENA_ECC_ERR_INT_ENA_Msk = 0x10 + // Bit ECC_ERR_INT_ENA. + SPI0_INT_ENA_ECC_ERR_INT_ENA = 0x10 + + // INT_CLR: SPI1 interrupt clear register + // Position of TOTAL_TRANS_END_INT_CLR field. + SPI0_INT_CLR_TOTAL_TRANS_END_INT_CLR_Pos = 0x2 + // Bit mask of TOTAL_TRANS_END_INT_CLR field. + SPI0_INT_CLR_TOTAL_TRANS_END_INT_CLR_Msk = 0x4 + // Bit TOTAL_TRANS_END_INT_CLR. + SPI0_INT_CLR_TOTAL_TRANS_END_INT_CLR = 0x4 + // Position of ECC_ERR_INT_CLR field. + SPI0_INT_CLR_ECC_ERR_INT_CLR_Pos = 0x4 + // Bit mask of ECC_ERR_INT_CLR field. + SPI0_INT_CLR_ECC_ERR_INT_CLR_Msk = 0x10 + // Bit ECC_ERR_INT_CLR. + SPI0_INT_CLR_ECC_ERR_INT_CLR = 0x10 + + // INT_RAW: SPI1 interrupt raw register + // Position of TOTAL_TRANS_END_INT_RAW field. + SPI0_INT_RAW_TOTAL_TRANS_END_INT_RAW_Pos = 0x2 + // Bit mask of TOTAL_TRANS_END_INT_RAW field. + SPI0_INT_RAW_TOTAL_TRANS_END_INT_RAW_Msk = 0x4 + // Bit TOTAL_TRANS_END_INT_RAW. + SPI0_INT_RAW_TOTAL_TRANS_END_INT_RAW = 0x4 + // Position of ECC_ERR_INT_RAW field. + SPI0_INT_RAW_ECC_ERR_INT_RAW_Pos = 0x4 + // Bit mask of ECC_ERR_INT_RAW field. + SPI0_INT_RAW_ECC_ERR_INT_RAW_Msk = 0x10 + // Bit ECC_ERR_INT_RAW. + SPI0_INT_RAW_ECC_ERR_INT_RAW = 0x10 + + // INT_ST: SPI1 interrupt status register + // Position of TOTAL_TRANS_END_INT_ST field. + SPI0_INT_ST_TOTAL_TRANS_END_INT_ST_Pos = 0x2 + // Bit mask of TOTAL_TRANS_END_INT_ST field. + SPI0_INT_ST_TOTAL_TRANS_END_INT_ST_Msk = 0x4 + // Bit TOTAL_TRANS_END_INT_ST. + SPI0_INT_ST_TOTAL_TRANS_END_INT_ST = 0x4 + // Position of ECC_ERR_INT_ST field. + SPI0_INT_ST_ECC_ERR_INT_ST_Pos = 0x4 + // Bit mask of ECC_ERR_INT_ST field. + SPI0_INT_ST_ECC_ERR_INT_ST_Msk = 0x10 + // Bit ECC_ERR_INT_ST. + SPI0_INT_ST_ECC_ERR_INT_ST = 0x10 + + // DATE: SPI0 version control register + // Position of SPI_SMEM_SPICLK_FUN_DRV field. + SPI0_DATE_SPI_SMEM_SPICLK_FUN_DRV_Pos = 0x0 + // Bit mask of SPI_SMEM_SPICLK_FUN_DRV field. + SPI0_DATE_SPI_SMEM_SPICLK_FUN_DRV_Msk = 0x3 + // Position of SPI_FMEM_SPICLK_FUN_DRV field. + SPI0_DATE_SPI_FMEM_SPICLK_FUN_DRV_Pos = 0x2 + // Bit mask of SPI_FMEM_SPICLK_FUN_DRV field. + SPI0_DATE_SPI_FMEM_SPICLK_FUN_DRV_Msk = 0xc + // Position of SPI_SPICLK_PAD_DRV_CTL_EN field. + SPI0_DATE_SPI_SPICLK_PAD_DRV_CTL_EN_Pos = 0x4 + // Bit mask of SPI_SPICLK_PAD_DRV_CTL_EN field. + SPI0_DATE_SPI_SPICLK_PAD_DRV_CTL_EN_Msk = 0x10 + // Bit SPI_SPICLK_PAD_DRV_CTL_EN. + SPI0_DATE_SPI_SPICLK_PAD_DRV_CTL_EN = 0x10 + // Position of DATE field. + SPI0_DATE_DATE_Pos = 0x5 + // Bit mask of DATE field. + SPI0_DATE_DATE_Msk = 0xfffffe0 +) + +// Constants for SPI1: SPI (Serial Peripheral Interface) Controller 1 +const ( + // CMD: SPI1 memory command register + // Position of FLASH_PE field. + SPI1_CMD_FLASH_PE_Pos = 0x11 + // Bit mask of FLASH_PE field. + SPI1_CMD_FLASH_PE_Msk = 0x20000 + // Bit FLASH_PE. + SPI1_CMD_FLASH_PE = 0x20000 + // Position of USR field. + SPI1_CMD_USR_Pos = 0x12 + // Bit mask of USR field. + SPI1_CMD_USR_Msk = 0x40000 + // Bit USR. + SPI1_CMD_USR = 0x40000 + // Position of FLASH_HPM field. + SPI1_CMD_FLASH_HPM_Pos = 0x13 + // Bit mask of FLASH_HPM field. + SPI1_CMD_FLASH_HPM_Msk = 0x80000 + // Bit FLASH_HPM. + SPI1_CMD_FLASH_HPM = 0x80000 + // Position of FLASH_RES field. + SPI1_CMD_FLASH_RES_Pos = 0x14 + // Bit mask of FLASH_RES field. + SPI1_CMD_FLASH_RES_Msk = 0x100000 + // Bit FLASH_RES. + SPI1_CMD_FLASH_RES = 0x100000 + // Position of FLASH_DP field. + SPI1_CMD_FLASH_DP_Pos = 0x15 + // Bit mask of FLASH_DP field. + SPI1_CMD_FLASH_DP_Msk = 0x200000 + // Bit FLASH_DP. + SPI1_CMD_FLASH_DP = 0x200000 + // Position of FLASH_CE field. + SPI1_CMD_FLASH_CE_Pos = 0x16 + // Bit mask of FLASH_CE field. + SPI1_CMD_FLASH_CE_Msk = 0x400000 + // Bit FLASH_CE. + SPI1_CMD_FLASH_CE = 0x400000 + // Position of FLASH_BE field. + SPI1_CMD_FLASH_BE_Pos = 0x17 + // Bit mask of FLASH_BE field. + SPI1_CMD_FLASH_BE_Msk = 0x800000 + // Bit FLASH_BE. + SPI1_CMD_FLASH_BE = 0x800000 + // Position of FLASH_SE field. + SPI1_CMD_FLASH_SE_Pos = 0x18 + // Bit mask of FLASH_SE field. + SPI1_CMD_FLASH_SE_Msk = 0x1000000 + // Bit FLASH_SE. + SPI1_CMD_FLASH_SE = 0x1000000 + // Position of FLASH_PP field. + SPI1_CMD_FLASH_PP_Pos = 0x19 + // Bit mask of FLASH_PP field. + SPI1_CMD_FLASH_PP_Msk = 0x2000000 + // Bit FLASH_PP. + SPI1_CMD_FLASH_PP = 0x2000000 + // Position of FLASH_WRSR field. + SPI1_CMD_FLASH_WRSR_Pos = 0x1a + // Bit mask of FLASH_WRSR field. + SPI1_CMD_FLASH_WRSR_Msk = 0x4000000 + // Bit FLASH_WRSR. + SPI1_CMD_FLASH_WRSR = 0x4000000 + // Position of FLASH_RDSR field. + SPI1_CMD_FLASH_RDSR_Pos = 0x1b + // Bit mask of FLASH_RDSR field. + SPI1_CMD_FLASH_RDSR_Msk = 0x8000000 + // Bit FLASH_RDSR. + SPI1_CMD_FLASH_RDSR = 0x8000000 + // Position of FLASH_RDID field. + SPI1_CMD_FLASH_RDID_Pos = 0x1c + // Bit mask of FLASH_RDID field. + SPI1_CMD_FLASH_RDID_Msk = 0x10000000 + // Bit FLASH_RDID. + SPI1_CMD_FLASH_RDID = 0x10000000 + // Position of FLASH_WRDI field. + SPI1_CMD_FLASH_WRDI_Pos = 0x1d + // Bit mask of FLASH_WRDI field. + SPI1_CMD_FLASH_WRDI_Msk = 0x20000000 + // Bit FLASH_WRDI. + SPI1_CMD_FLASH_WRDI = 0x20000000 + // Position of FLASH_WREN field. + SPI1_CMD_FLASH_WREN_Pos = 0x1e + // Bit mask of FLASH_WREN field. + SPI1_CMD_FLASH_WREN_Msk = 0x40000000 + // Bit FLASH_WREN. + SPI1_CMD_FLASH_WREN = 0x40000000 + // Position of FLASH_READ field. + SPI1_CMD_FLASH_READ_Pos = 0x1f + // Bit mask of FLASH_READ field. + SPI1_CMD_FLASH_READ_Msk = 0x80000000 + // Bit FLASH_READ. + SPI1_CMD_FLASH_READ = 0x80000000 + + // ADDR: SPI1 address register + // Position of USR_ADDR_VALUE field. + SPI1_ADDR_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of USR_ADDR_VALUE field. + SPI1_ADDR_USR_ADDR_VALUE_Msk = 0xffffffff + + // CTRL: SPI1 control register + // Position of FDUMMY_OUT field. + SPI1_CTRL_FDUMMY_OUT_Pos = 0x3 + // Bit mask of FDUMMY_OUT field. + SPI1_CTRL_FDUMMY_OUT_Msk = 0x8 + // Bit FDUMMY_OUT. + SPI1_CTRL_FDUMMY_OUT = 0x8 + // Position of FDOUT_OCT field. + SPI1_CTRL_FDOUT_OCT_Pos = 0x4 + // Bit mask of FDOUT_OCT field. + SPI1_CTRL_FDOUT_OCT_Msk = 0x10 + // Bit FDOUT_OCT. + SPI1_CTRL_FDOUT_OCT = 0x10 + // Position of FDIN_OCT field. + SPI1_CTRL_FDIN_OCT_Pos = 0x5 + // Bit mask of FDIN_OCT field. + SPI1_CTRL_FDIN_OCT_Msk = 0x20 + // Bit FDIN_OCT. + SPI1_CTRL_FDIN_OCT = 0x20 + // Position of FADDR_OCT field. + SPI1_CTRL_FADDR_OCT_Pos = 0x6 + // Bit mask of FADDR_OCT field. + SPI1_CTRL_FADDR_OCT_Msk = 0x40 + // Bit FADDR_OCT. + SPI1_CTRL_FADDR_OCT = 0x40 + // Position of FCMD_DUAL field. + SPI1_CTRL_FCMD_DUAL_Pos = 0x7 + // Bit mask of FCMD_DUAL field. + SPI1_CTRL_FCMD_DUAL_Msk = 0x80 + // Bit FCMD_DUAL. + SPI1_CTRL_FCMD_DUAL = 0x80 + // Position of FCMD_QUAD field. + SPI1_CTRL_FCMD_QUAD_Pos = 0x8 + // Bit mask of FCMD_QUAD field. + SPI1_CTRL_FCMD_QUAD_Msk = 0x100 + // Bit FCMD_QUAD. + SPI1_CTRL_FCMD_QUAD = 0x100 + // Position of FCMD_OCT field. + SPI1_CTRL_FCMD_OCT_Pos = 0x9 + // Bit mask of FCMD_OCT field. + SPI1_CTRL_FCMD_OCT_Msk = 0x200 + // Bit FCMD_OCT. + SPI1_CTRL_FCMD_OCT = 0x200 + // Position of FCS_CRC_EN field. + SPI1_CTRL_FCS_CRC_EN_Pos = 0xa + // Bit mask of FCS_CRC_EN field. + SPI1_CTRL_FCS_CRC_EN_Msk = 0x400 + // Bit FCS_CRC_EN. + SPI1_CTRL_FCS_CRC_EN = 0x400 + // Position of TX_CRC_EN field. + SPI1_CTRL_TX_CRC_EN_Pos = 0xb + // Bit mask of TX_CRC_EN field. + SPI1_CTRL_TX_CRC_EN_Msk = 0x800 + // Bit TX_CRC_EN. + SPI1_CTRL_TX_CRC_EN = 0x800 + // Position of FASTRD_MODE field. + SPI1_CTRL_FASTRD_MODE_Pos = 0xd + // Bit mask of FASTRD_MODE field. + SPI1_CTRL_FASTRD_MODE_Msk = 0x2000 + // Bit FASTRD_MODE. + SPI1_CTRL_FASTRD_MODE = 0x2000 + // Position of FREAD_DUAL field. + SPI1_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI1_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI1_CTRL_FREAD_DUAL = 0x4000 + // Position of RESANDRES field. + SPI1_CTRL_RESANDRES_Pos = 0xf + // Bit mask of RESANDRES field. + SPI1_CTRL_RESANDRES_Msk = 0x8000 + // Bit RESANDRES. + SPI1_CTRL_RESANDRES = 0x8000 + // Position of Q_POL field. + SPI1_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI1_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI1_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI1_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI1_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI1_CTRL_D_POL = 0x80000 + // Position of FREAD_QUAD field. + SPI1_CTRL_FREAD_QUAD_Pos = 0x14 + // Bit mask of FREAD_QUAD field. + SPI1_CTRL_FREAD_QUAD_Msk = 0x100000 + // Bit FREAD_QUAD. + SPI1_CTRL_FREAD_QUAD = 0x100000 + // Position of WP field. + SPI1_CTRL_WP_Pos = 0x15 + // Bit mask of WP field. + SPI1_CTRL_WP_Msk = 0x200000 + // Bit WP. + SPI1_CTRL_WP = 0x200000 + // Position of WRSR_2B field. + SPI1_CTRL_WRSR_2B_Pos = 0x16 + // Bit mask of WRSR_2B field. + SPI1_CTRL_WRSR_2B_Msk = 0x400000 + // Bit WRSR_2B. + SPI1_CTRL_WRSR_2B = 0x400000 + // Position of FREAD_DIO field. + SPI1_CTRL_FREAD_DIO_Pos = 0x17 + // Bit mask of FREAD_DIO field. + SPI1_CTRL_FREAD_DIO_Msk = 0x800000 + // Bit FREAD_DIO. + SPI1_CTRL_FREAD_DIO = 0x800000 + // Position of FREAD_QIO field. + SPI1_CTRL_FREAD_QIO_Pos = 0x18 + // Bit mask of FREAD_QIO field. + SPI1_CTRL_FREAD_QIO_Msk = 0x1000000 + // Bit FREAD_QIO. + SPI1_CTRL_FREAD_QIO = 0x1000000 + + // CTRL1: SPI1 control1 register + // Position of CLK_MODE field. + SPI1_CTRL1_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI1_CTRL1_CLK_MODE_Msk = 0x3 + // Position of CS_HOLD_DLY_RES field. + SPI1_CTRL1_CS_HOLD_DLY_RES_Pos = 0x2 + // Bit mask of CS_HOLD_DLY_RES field. + SPI1_CTRL1_CS_HOLD_DLY_RES_Msk = 0xffc + + // CTRL2: SPI1 control2 register + // Position of SYNC_RESET field. + SPI1_CTRL2_SYNC_RESET_Pos = 0x1f + // Bit mask of SYNC_RESET field. + SPI1_CTRL2_SYNC_RESET_Msk = 0x80000000 + // Bit SYNC_RESET. + SPI1_CTRL2_SYNC_RESET = 0x80000000 + + // CLOCK: SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM. + // Position of CLKCNT_L field. + SPI1_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI1_CLOCK_CLKCNT_L_Msk = 0xff + // Position of CLKCNT_H field. + SPI1_CLOCK_CLKCNT_H_Pos = 0x8 + // Bit mask of CLKCNT_H field. + SPI1_CLOCK_CLKCNT_H_Msk = 0xff00 + // Position of CLKCNT_N field. + SPI1_CLOCK_CLKCNT_N_Pos = 0x10 + // Bit mask of CLKCNT_N field. + SPI1_CLOCK_CLKCNT_N_Msk = 0xff0000 + // Position of CLK_EQU_SYSCLK field. + SPI1_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI1_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI1_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI1 user register. + // Position of CK_OUT_EDGE field. + SPI1_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI1_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI1_USER_CK_OUT_EDGE = 0x200 + // Position of FWRITE_DUAL field. + SPI1_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI1_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI1_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI1_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI1_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI1_USER_FWRITE_QUAD = 0x2000 + // Position of FWRITE_DIO field. + SPI1_USER_FWRITE_DIO_Pos = 0xe + // Bit mask of FWRITE_DIO field. + SPI1_USER_FWRITE_DIO_Msk = 0x4000 + // Bit FWRITE_DIO. + SPI1_USER_FWRITE_DIO = 0x4000 + // Position of FWRITE_QIO field. + SPI1_USER_FWRITE_QIO_Pos = 0xf + // Bit mask of FWRITE_QIO field. + SPI1_USER_FWRITE_QIO_Msk = 0x8000 + // Bit FWRITE_QIO. + SPI1_USER_FWRITE_QIO = 0x8000 + // Position of USR_MISO_HIGHPART field. + SPI1_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI1_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI1_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI1_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI1_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI1_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI1_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI1_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI1_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI1_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI1_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI1_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI1_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI1_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI1_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI1_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI1_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI1_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI1_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI1_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI1_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI1_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI1_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI1_USER_USR_COMMAND = 0x80000000 + + // USER1: SPI1 user1 register. + // Position of USR_DUMMY_CYCLELEN field. + SPI1_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI1_USER1_USR_DUMMY_CYCLELEN_Msk = 0x3f + // Position of USR_ADDR_BITLEN field. + SPI1_USER1_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of USR_ADDR_BITLEN field. + SPI1_USER1_USR_ADDR_BITLEN_Msk = 0xfc000000 + + // USER2: SPI1 user2 register. + // Position of USR_COMMAND_VALUE field. + SPI1_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI1_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of USR_COMMAND_BITLEN field. + SPI1_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI1_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MOSI_DLEN: SPI1 write-data bit length register. + // Position of USR_MOSI_DBITLEN field. + SPI1_MOSI_DLEN_USR_MOSI_DBITLEN_Pos = 0x0 + // Bit mask of USR_MOSI_DBITLEN field. + SPI1_MOSI_DLEN_USR_MOSI_DBITLEN_Msk = 0x3ff + + // MISO_DLEN: SPI1 read-data bit length register. + // Position of USR_MISO_DBITLEN field. + SPI1_MISO_DLEN_USR_MISO_DBITLEN_Pos = 0x0 + // Bit mask of USR_MISO_DBITLEN field. + SPI1_MISO_DLEN_USR_MISO_DBITLEN_Msk = 0x3ff + + // RD_STATUS: SPI1 read control register. + // Position of STATUS field. + SPI1_RD_STATUS_STATUS_Pos = 0x0 + // Bit mask of STATUS field. + SPI1_RD_STATUS_STATUS_Msk = 0xffff + // Position of WB_MODE field. + SPI1_RD_STATUS_WB_MODE_Pos = 0x10 + // Bit mask of WB_MODE field. + SPI1_RD_STATUS_WB_MODE_Msk = 0xff0000 + + // EXT_ADDR: SPI1 extended address register. + // Position of EXT_ADDR field. + SPI1_EXT_ADDR_EXT_ADDR_Pos = 0x0 + // Bit mask of EXT_ADDR field. + SPI1_EXT_ADDR_EXT_ADDR_Msk = 0xffffffff + + // MISC: SPI1 misc register. + // Position of CS0_DIS field. + SPI1_MISC_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI1_MISC_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI1_MISC_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI1_MISC_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI1_MISC_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI1_MISC_CS1_DIS = 0x2 + // Position of CK_IDLE_EDGE field. + SPI1_MISC_CK_IDLE_EDGE_Pos = 0x9 + // Bit mask of CK_IDLE_EDGE field. + SPI1_MISC_CK_IDLE_EDGE_Msk = 0x200 + // Bit CK_IDLE_EDGE. + SPI1_MISC_CK_IDLE_EDGE = 0x200 + // Position of CS_KEEP_ACTIVE field. + SPI1_MISC_CS_KEEP_ACTIVE_Pos = 0xa + // Bit mask of CS_KEEP_ACTIVE field. + SPI1_MISC_CS_KEEP_ACTIVE_Msk = 0x400 + // Bit CS_KEEP_ACTIVE. + SPI1_MISC_CS_KEEP_ACTIVE = 0x400 + // Position of AUTO_PER field. + SPI1_MISC_AUTO_PER_Pos = 0xb + // Bit mask of AUTO_PER field. + SPI1_MISC_AUTO_PER_Msk = 0x800 + // Bit AUTO_PER. + SPI1_MISC_AUTO_PER = 0x800 + + // TX_CRC: SPI1 CRC data register. + // Position of DATA field. + SPI1_TX_CRC_DATA_Pos = 0x0 + // Bit mask of DATA field. + SPI1_TX_CRC_DATA_Msk = 0xffffffff + + // CACHE_FCTRL: SPI1 bit mode control register. + // Position of CACHE_USR_CMD_4BYTE field. + SPI1_CACHE_FCTRL_CACHE_USR_CMD_4BYTE_Pos = 0x1 + // Bit mask of CACHE_USR_CMD_4BYTE field. + SPI1_CACHE_FCTRL_CACHE_USR_CMD_4BYTE_Msk = 0x2 + // Bit CACHE_USR_CMD_4BYTE. + SPI1_CACHE_FCTRL_CACHE_USR_CMD_4BYTE = 0x2 + // Position of FDIN_DUAL field. + SPI1_CACHE_FCTRL_FDIN_DUAL_Pos = 0x3 + // Bit mask of FDIN_DUAL field. + SPI1_CACHE_FCTRL_FDIN_DUAL_Msk = 0x8 + // Bit FDIN_DUAL. + SPI1_CACHE_FCTRL_FDIN_DUAL = 0x8 + // Position of FDOUT_DUAL field. + SPI1_CACHE_FCTRL_FDOUT_DUAL_Pos = 0x4 + // Bit mask of FDOUT_DUAL field. + SPI1_CACHE_FCTRL_FDOUT_DUAL_Msk = 0x10 + // Bit FDOUT_DUAL. + SPI1_CACHE_FCTRL_FDOUT_DUAL = 0x10 + // Position of FADDR_DUAL field. + SPI1_CACHE_FCTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI1_CACHE_FCTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI1_CACHE_FCTRL_FADDR_DUAL = 0x20 + // Position of FDIN_QUAD field. + SPI1_CACHE_FCTRL_FDIN_QUAD_Pos = 0x6 + // Bit mask of FDIN_QUAD field. + SPI1_CACHE_FCTRL_FDIN_QUAD_Msk = 0x40 + // Bit FDIN_QUAD. + SPI1_CACHE_FCTRL_FDIN_QUAD = 0x40 + // Position of FDOUT_QUAD field. + SPI1_CACHE_FCTRL_FDOUT_QUAD_Pos = 0x7 + // Bit mask of FDOUT_QUAD field. + SPI1_CACHE_FCTRL_FDOUT_QUAD_Msk = 0x80 + // Bit FDOUT_QUAD. + SPI1_CACHE_FCTRL_FDOUT_QUAD = 0x80 + // Position of FADDR_QUAD field. + SPI1_CACHE_FCTRL_FADDR_QUAD_Pos = 0x8 + // Bit mask of FADDR_QUAD field. + SPI1_CACHE_FCTRL_FADDR_QUAD_Msk = 0x100 + // Bit FADDR_QUAD. + SPI1_CACHE_FCTRL_FADDR_QUAD = 0x100 + + // FSM: SPI1 state machine(FSM) status register. + // Position of ST field. + SPI1_FSM_ST_Pos = 0x0 + // Bit mask of ST field. + SPI1_FSM_ST_Msk = 0x7 + + // W0: SPI1 memory data buffer0 + // Position of BUF0 field. + SPI1_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI1_W0_BUF0_Msk = 0xffffffff + + // W1: SPI1 memory data buffer1 + // Position of BUF1 field. + SPI1_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI1_W1_BUF1_Msk = 0xffffffff + + // W2: SPI1 memory data buffer2 + // Position of BUF2 field. + SPI1_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI1_W2_BUF2_Msk = 0xffffffff + + // W3: SPI1 memory data buffer3 + // Position of BUF3 field. + SPI1_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI1_W3_BUF3_Msk = 0xffffffff + + // W4: SPI1 memory data buffer4 + // Position of BUF4 field. + SPI1_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI1_W4_BUF4_Msk = 0xffffffff + + // W5: SPI1 memory data buffer5 + // Position of BUF5 field. + SPI1_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI1_W5_BUF5_Msk = 0xffffffff + + // W6: SPI1 memory data buffer6 + // Position of BUF6 field. + SPI1_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI1_W6_BUF6_Msk = 0xffffffff + + // W7: SPI1 memory data buffer7 + // Position of BUF7 field. + SPI1_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI1_W7_BUF7_Msk = 0xffffffff + + // W8: SPI1 memory data buffer8 + // Position of BUF8 field. + SPI1_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI1_W8_BUF8_Msk = 0xffffffff + + // W9: SPI1 memory data buffer9 + // Position of BUF9 field. + SPI1_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI1_W9_BUF9_Msk = 0xffffffff + + // W10: SPI1 memory data buffer10 + // Position of BUF10 field. + SPI1_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI1_W10_BUF10_Msk = 0xffffffff + + // W11: SPI1 memory data buffer11 + // Position of BUF11 field. + SPI1_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI1_W11_BUF11_Msk = 0xffffffff + + // W12: SPI1 memory data buffer12 + // Position of BUF12 field. + SPI1_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI1_W12_BUF12_Msk = 0xffffffff + + // W13: SPI1 memory data buffer13 + // Position of BUF13 field. + SPI1_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI1_W13_BUF13_Msk = 0xffffffff + + // W14: SPI1 memory data buffer14 + // Position of BUF14 field. + SPI1_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI1_W14_BUF14_Msk = 0xffffffff + + // W15: SPI1 memory data buffer15 + // Position of BUF15 field. + SPI1_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI1_W15_BUF15_Msk = 0xffffffff + + // FLASH_WAITI_CTRL: SPI1 wait idle control register + // Position of WAITI_EN field. + SPI1_FLASH_WAITI_CTRL_WAITI_EN_Pos = 0x0 + // Bit mask of WAITI_EN field. + SPI1_FLASH_WAITI_CTRL_WAITI_EN_Msk = 0x1 + // Bit WAITI_EN. + SPI1_FLASH_WAITI_CTRL_WAITI_EN = 0x1 + // Position of WAITI_DUMMY field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_Pos = 0x1 + // Bit mask of WAITI_DUMMY field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_Msk = 0x2 + // Bit WAITI_DUMMY. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY = 0x2 + // Position of WAITI_CMD field. + SPI1_FLASH_WAITI_CTRL_WAITI_CMD_Pos = 0x2 + // Bit mask of WAITI_CMD field. + SPI1_FLASH_WAITI_CTRL_WAITI_CMD_Msk = 0x3fc + // Position of WAITI_DUMMY_CYCLELEN field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN_Pos = 0xa + // Bit mask of WAITI_DUMMY_CYCLELEN field. + SPI1_FLASH_WAITI_CTRL_WAITI_DUMMY_CYCLELEN_Msk = 0xfc00 + + // FLASH_SUS_CMD: SPI1 flash suspend control register + // Position of FLASH_PER field. + SPI1_FLASH_SUS_CMD_FLASH_PER_Pos = 0x0 + // Bit mask of FLASH_PER field. + SPI1_FLASH_SUS_CMD_FLASH_PER_Msk = 0x1 + // Bit FLASH_PER. + SPI1_FLASH_SUS_CMD_FLASH_PER = 0x1 + // Position of FLASH_PES field. + SPI1_FLASH_SUS_CMD_FLASH_PES_Pos = 0x1 + // Bit mask of FLASH_PES field. + SPI1_FLASH_SUS_CMD_FLASH_PES_Msk = 0x2 + // Bit FLASH_PES. + SPI1_FLASH_SUS_CMD_FLASH_PES = 0x2 + // Position of FLASH_PER_WAIT_EN field. + SPI1_FLASH_SUS_CMD_FLASH_PER_WAIT_EN_Pos = 0x2 + // Bit mask of FLASH_PER_WAIT_EN field. + SPI1_FLASH_SUS_CMD_FLASH_PER_WAIT_EN_Msk = 0x4 + // Bit FLASH_PER_WAIT_EN. + SPI1_FLASH_SUS_CMD_FLASH_PER_WAIT_EN = 0x4 + // Position of FLASH_PES_WAIT_EN field. + SPI1_FLASH_SUS_CMD_FLASH_PES_WAIT_EN_Pos = 0x3 + // Bit mask of FLASH_PES_WAIT_EN field. + SPI1_FLASH_SUS_CMD_FLASH_PES_WAIT_EN_Msk = 0x8 + // Bit FLASH_PES_WAIT_EN. + SPI1_FLASH_SUS_CMD_FLASH_PES_WAIT_EN = 0x8 + // Position of PES_PER_EN field. + SPI1_FLASH_SUS_CMD_PES_PER_EN_Pos = 0x4 + // Bit mask of PES_PER_EN field. + SPI1_FLASH_SUS_CMD_PES_PER_EN_Msk = 0x10 + // Bit PES_PER_EN. + SPI1_FLASH_SUS_CMD_PES_PER_EN = 0x10 + // Position of PESR_IDLE_EN field. + SPI1_FLASH_SUS_CMD_PESR_IDLE_EN_Pos = 0x5 + // Bit mask of PESR_IDLE_EN field. + SPI1_FLASH_SUS_CMD_PESR_IDLE_EN_Msk = 0x20 + // Bit PESR_IDLE_EN. + SPI1_FLASH_SUS_CMD_PESR_IDLE_EN = 0x20 + + // FLASH_SUS_CTRL: SPI1 flash suspend command register + // Position of FLASH_PES_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_EN_Pos = 0x0 + // Bit mask of FLASH_PES_EN field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_EN_Msk = 0x1 + // Bit FLASH_PES_EN. + SPI1_FLASH_SUS_CTRL_FLASH_PES_EN = 0x1 + // Position of FLASH_PER_COMMAND field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_COMMAND_Pos = 0x1 + // Bit mask of FLASH_PER_COMMAND field. + SPI1_FLASH_SUS_CTRL_FLASH_PER_COMMAND_Msk = 0x1fe + // Position of FLASH_PES_COMMAND field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_COMMAND_Pos = 0x9 + // Bit mask of FLASH_PES_COMMAND field. + SPI1_FLASH_SUS_CTRL_FLASH_PES_COMMAND_Msk = 0x1fe00 + + // SUS_STATUS: SPI1 flash suspend status register + // Position of FLASH_SUS field. + SPI1_SUS_STATUS_FLASH_SUS_Pos = 0x0 + // Bit mask of FLASH_SUS field. + SPI1_SUS_STATUS_FLASH_SUS_Msk = 0x1 + // Bit FLASH_SUS. + SPI1_SUS_STATUS_FLASH_SUS = 0x1 + // Position of FLASH_HPM_DLY_256 field. + SPI1_SUS_STATUS_FLASH_HPM_DLY_256_Pos = 0x2 + // Bit mask of FLASH_HPM_DLY_256 field. + SPI1_SUS_STATUS_FLASH_HPM_DLY_256_Msk = 0x4 + // Bit FLASH_HPM_DLY_256. + SPI1_SUS_STATUS_FLASH_HPM_DLY_256 = 0x4 + // Position of FLASH_RES_DLY_256 field. + SPI1_SUS_STATUS_FLASH_RES_DLY_256_Pos = 0x3 + // Bit mask of FLASH_RES_DLY_256 field. + SPI1_SUS_STATUS_FLASH_RES_DLY_256_Msk = 0x8 + // Bit FLASH_RES_DLY_256. + SPI1_SUS_STATUS_FLASH_RES_DLY_256 = 0x8 + // Position of FLASH_DP_DLY_256 field. + SPI1_SUS_STATUS_FLASH_DP_DLY_256_Pos = 0x4 + // Bit mask of FLASH_DP_DLY_256 field. + SPI1_SUS_STATUS_FLASH_DP_DLY_256_Msk = 0x10 + // Bit FLASH_DP_DLY_256. + SPI1_SUS_STATUS_FLASH_DP_DLY_256 = 0x10 + // Position of FLASH_PER_DLY_256 field. + SPI1_SUS_STATUS_FLASH_PER_DLY_256_Pos = 0x5 + // Bit mask of FLASH_PER_DLY_256 field. + SPI1_SUS_STATUS_FLASH_PER_DLY_256_Msk = 0x20 + // Bit FLASH_PER_DLY_256. + SPI1_SUS_STATUS_FLASH_PER_DLY_256 = 0x20 + // Position of FLASH_PES_DLY_256 field. + SPI1_SUS_STATUS_FLASH_PES_DLY_256_Pos = 0x6 + // Bit mask of FLASH_PES_DLY_256 field. + SPI1_SUS_STATUS_FLASH_PES_DLY_256_Msk = 0x40 + // Bit FLASH_PES_DLY_256. + SPI1_SUS_STATUS_FLASH_PES_DLY_256 = 0x40 + + // TIMING_CALI: SPI1 timing compensation register when accesses to flash or Ext_RAM. + // Position of TIMING_CALI field. + SPI1_TIMING_CALI_TIMING_CALI_Pos = 0x1 + // Bit mask of TIMING_CALI field. + SPI1_TIMING_CALI_TIMING_CALI_Msk = 0x2 + // Bit TIMING_CALI. + SPI1_TIMING_CALI_TIMING_CALI = 0x2 + // Position of EXTRA_DUMMY_CYCLELEN field. + SPI1_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Pos = 0x2 + // Bit mask of EXTRA_DUMMY_CYCLELEN field. + SPI1_TIMING_CALI_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c + + // DDR: SPI1 DDR control register + // Position of SPI_FMEM_DDR_EN field. + SPI1_DDR_SPI_FMEM_DDR_EN_Pos = 0x0 + // Bit mask of SPI_FMEM_DDR_EN field. + SPI1_DDR_SPI_FMEM_DDR_EN_Msk = 0x1 + // Bit SPI_FMEM_DDR_EN. + SPI1_DDR_SPI_FMEM_DDR_EN = 0x1 + // Position of SPI_FMEM_VAR_DUMMY field. + SPI1_DDR_SPI_FMEM_VAR_DUMMY_Pos = 0x1 + // Bit mask of SPI_FMEM_VAR_DUMMY field. + SPI1_DDR_SPI_FMEM_VAR_DUMMY_Msk = 0x2 + // Bit SPI_FMEM_VAR_DUMMY. + SPI1_DDR_SPI_FMEM_VAR_DUMMY = 0x2 + // Position of SPI_FMEM_DDR_RDAT_SWP field. + SPI1_DDR_SPI_FMEM_DDR_RDAT_SWP_Pos = 0x2 + // Bit mask of SPI_FMEM_DDR_RDAT_SWP field. + SPI1_DDR_SPI_FMEM_DDR_RDAT_SWP_Msk = 0x4 + // Bit SPI_FMEM_DDR_RDAT_SWP. + SPI1_DDR_SPI_FMEM_DDR_RDAT_SWP = 0x4 + // Position of SPI_FMEM_DDR_WDAT_SWP field. + SPI1_DDR_SPI_FMEM_DDR_WDAT_SWP_Pos = 0x3 + // Bit mask of SPI_FMEM_DDR_WDAT_SWP field. + SPI1_DDR_SPI_FMEM_DDR_WDAT_SWP_Msk = 0x8 + // Bit SPI_FMEM_DDR_WDAT_SWP. + SPI1_DDR_SPI_FMEM_DDR_WDAT_SWP = 0x8 + // Position of SPI_FMEM_DDR_CMD_DIS field. + SPI1_DDR_SPI_FMEM_DDR_CMD_DIS_Pos = 0x4 + // Bit mask of SPI_FMEM_DDR_CMD_DIS field. + SPI1_DDR_SPI_FMEM_DDR_CMD_DIS_Msk = 0x10 + // Bit SPI_FMEM_DDR_CMD_DIS. + SPI1_DDR_SPI_FMEM_DDR_CMD_DIS = 0x10 + // Position of SPI_FMEM_OUTMINBYTELEN field. + SPI1_DDR_SPI_FMEM_OUTMINBYTELEN_Pos = 0x5 + // Bit mask of SPI_FMEM_OUTMINBYTELEN field. + SPI1_DDR_SPI_FMEM_OUTMINBYTELEN_Msk = 0xfe0 + // Position of SPI_FMEM_USR_DDR_DQS_THD field. + SPI1_DDR_SPI_FMEM_USR_DDR_DQS_THD_Pos = 0xe + // Bit mask of SPI_FMEM_USR_DDR_DQS_THD field. + SPI1_DDR_SPI_FMEM_USR_DDR_DQS_THD_Msk = 0x1fc000 + // Position of SPI_FMEM_DDR_DQS_LOOP field. + SPI1_DDR_SPI_FMEM_DDR_DQS_LOOP_Pos = 0x15 + // Bit mask of SPI_FMEM_DDR_DQS_LOOP field. + SPI1_DDR_SPI_FMEM_DDR_DQS_LOOP_Msk = 0x200000 + // Bit SPI_FMEM_DDR_DQS_LOOP. + SPI1_DDR_SPI_FMEM_DDR_DQS_LOOP = 0x200000 + // Position of SPI_FMEM_DDR_DQS_LOOP_MODE field. + SPI1_DDR_SPI_FMEM_DDR_DQS_LOOP_MODE_Pos = 0x16 + // Bit mask of SPI_FMEM_DDR_DQS_LOOP_MODE field. + SPI1_DDR_SPI_FMEM_DDR_DQS_LOOP_MODE_Msk = 0x400000 + // Bit SPI_FMEM_DDR_DQS_LOOP_MODE. + SPI1_DDR_SPI_FMEM_DDR_DQS_LOOP_MODE = 0x400000 + // Position of SPI_FMEM_CLK_DIFF_EN field. + SPI1_DDR_SPI_FMEM_CLK_DIFF_EN_Pos = 0x18 + // Bit mask of SPI_FMEM_CLK_DIFF_EN field. + SPI1_DDR_SPI_FMEM_CLK_DIFF_EN_Msk = 0x1000000 + // Bit SPI_FMEM_CLK_DIFF_EN. + SPI1_DDR_SPI_FMEM_CLK_DIFF_EN = 0x1000000 + // Position of SPI_FMEM_HYPERBUS_MODE field. + SPI1_DDR_SPI_FMEM_HYPERBUS_MODE_Pos = 0x19 + // Bit mask of SPI_FMEM_HYPERBUS_MODE field. + SPI1_DDR_SPI_FMEM_HYPERBUS_MODE_Msk = 0x2000000 + // Bit SPI_FMEM_HYPERBUS_MODE. + SPI1_DDR_SPI_FMEM_HYPERBUS_MODE = 0x2000000 + // Position of SPI_FMEM_DQS_CA_IN field. + SPI1_DDR_SPI_FMEM_DQS_CA_IN_Pos = 0x1a + // Bit mask of SPI_FMEM_DQS_CA_IN field. + SPI1_DDR_SPI_FMEM_DQS_CA_IN_Msk = 0x4000000 + // Bit SPI_FMEM_DQS_CA_IN. + SPI1_DDR_SPI_FMEM_DQS_CA_IN = 0x4000000 + // Position of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI1_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b + // Bit mask of SPI_FMEM_HYPERBUS_DUMMY_2X field. + SPI1_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000 + // Bit SPI_FMEM_HYPERBUS_DUMMY_2X. + SPI1_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X = 0x8000000 + // Position of SPI_FMEM_CLK_DIFF_INV field. + SPI1_DDR_SPI_FMEM_CLK_DIFF_INV_Pos = 0x1c + // Bit mask of SPI_FMEM_CLK_DIFF_INV field. + SPI1_DDR_SPI_FMEM_CLK_DIFF_INV_Msk = 0x10000000 + // Bit SPI_FMEM_CLK_DIFF_INV. + SPI1_DDR_SPI_FMEM_CLK_DIFF_INV = 0x10000000 + // Position of SPI_FMEM_OCTA_RAM_ADDR field. + SPI1_DDR_SPI_FMEM_OCTA_RAM_ADDR_Pos = 0x1d + // Bit mask of SPI_FMEM_OCTA_RAM_ADDR field. + SPI1_DDR_SPI_FMEM_OCTA_RAM_ADDR_Msk = 0x20000000 + // Bit SPI_FMEM_OCTA_RAM_ADDR. + SPI1_DDR_SPI_FMEM_OCTA_RAM_ADDR = 0x20000000 + // Position of SPI_FMEM_HYPERBUS_CA field. + SPI1_DDR_SPI_FMEM_HYPERBUS_CA_Pos = 0x1e + // Bit mask of SPI_FMEM_HYPERBUS_CA field. + SPI1_DDR_SPI_FMEM_HYPERBUS_CA_Msk = 0x40000000 + // Bit SPI_FMEM_HYPERBUS_CA. + SPI1_DDR_SPI_FMEM_HYPERBUS_CA = 0x40000000 + + // CLOCK_GATE: SPI1 clk_gate register + // Position of CLK_EN field. + SPI1_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI1_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI1_CLOCK_GATE_CLK_EN = 0x1 + + // INT_ENA: SPI1 interrupt enable register + // Position of PER_END_INT_ENA field. + SPI1_INT_ENA_PER_END_INT_ENA_Pos = 0x0 + // Bit mask of PER_END_INT_ENA field. + SPI1_INT_ENA_PER_END_INT_ENA_Msk = 0x1 + // Bit PER_END_INT_ENA. + SPI1_INT_ENA_PER_END_INT_ENA = 0x1 + // Position of PES_END_INT_ENA field. + SPI1_INT_ENA_PES_END_INT_ENA_Pos = 0x1 + // Bit mask of PES_END_INT_ENA field. + SPI1_INT_ENA_PES_END_INT_ENA_Msk = 0x2 + // Bit PES_END_INT_ENA. + SPI1_INT_ENA_PES_END_INT_ENA = 0x2 + // Position of TOTAL_TRANS_END_INT_ENA field. + SPI1_INT_ENA_TOTAL_TRANS_END_INT_ENA_Pos = 0x2 + // Bit mask of TOTAL_TRANS_END_INT_ENA field. + SPI1_INT_ENA_TOTAL_TRANS_END_INT_ENA_Msk = 0x4 + // Bit TOTAL_TRANS_END_INT_ENA. + SPI1_INT_ENA_TOTAL_TRANS_END_INT_ENA = 0x4 + // Position of BROWN_OUT_INT_ENA field. + SPI1_INT_ENA_BROWN_OUT_INT_ENA_Pos = 0x3 + // Bit mask of BROWN_OUT_INT_ENA field. + SPI1_INT_ENA_BROWN_OUT_INT_ENA_Msk = 0x8 + // Bit BROWN_OUT_INT_ENA. + SPI1_INT_ENA_BROWN_OUT_INT_ENA = 0x8 + + // INT_CLR: SPI1 interrupt clear register + // Position of PER_END_INT_CLR field. + SPI1_INT_CLR_PER_END_INT_CLR_Pos = 0x0 + // Bit mask of PER_END_INT_CLR field. + SPI1_INT_CLR_PER_END_INT_CLR_Msk = 0x1 + // Bit PER_END_INT_CLR. + SPI1_INT_CLR_PER_END_INT_CLR = 0x1 + // Position of PES_END_INT_CLR field. + SPI1_INT_CLR_PES_END_INT_CLR_Pos = 0x1 + // Bit mask of PES_END_INT_CLR field. + SPI1_INT_CLR_PES_END_INT_CLR_Msk = 0x2 + // Bit PES_END_INT_CLR. + SPI1_INT_CLR_PES_END_INT_CLR = 0x2 + // Position of TOTAL_TRANS_END_INT_CLR field. + SPI1_INT_CLR_TOTAL_TRANS_END_INT_CLR_Pos = 0x2 + // Bit mask of TOTAL_TRANS_END_INT_CLR field. + SPI1_INT_CLR_TOTAL_TRANS_END_INT_CLR_Msk = 0x4 + // Bit TOTAL_TRANS_END_INT_CLR. + SPI1_INT_CLR_TOTAL_TRANS_END_INT_CLR = 0x4 + // Position of BROWN_OUT_INT_CLR field. + SPI1_INT_CLR_BROWN_OUT_INT_CLR_Pos = 0x3 + // Bit mask of BROWN_OUT_INT_CLR field. + SPI1_INT_CLR_BROWN_OUT_INT_CLR_Msk = 0x8 + // Bit BROWN_OUT_INT_CLR. + SPI1_INT_CLR_BROWN_OUT_INT_CLR = 0x8 + + // INT_RAW: SPI1 interrupt raw register + // Position of PER_END_INT_RAW field. + SPI1_INT_RAW_PER_END_INT_RAW_Pos = 0x0 + // Bit mask of PER_END_INT_RAW field. + SPI1_INT_RAW_PER_END_INT_RAW_Msk = 0x1 + // Bit PER_END_INT_RAW. + SPI1_INT_RAW_PER_END_INT_RAW = 0x1 + // Position of PES_END_INT_RAW field. + SPI1_INT_RAW_PES_END_INT_RAW_Pos = 0x1 + // Bit mask of PES_END_INT_RAW field. + SPI1_INT_RAW_PES_END_INT_RAW_Msk = 0x2 + // Bit PES_END_INT_RAW. + SPI1_INT_RAW_PES_END_INT_RAW = 0x2 + // Position of TOTAL_TRANS_END_INT_RAW field. + SPI1_INT_RAW_TOTAL_TRANS_END_INT_RAW_Pos = 0x2 + // Bit mask of TOTAL_TRANS_END_INT_RAW field. + SPI1_INT_RAW_TOTAL_TRANS_END_INT_RAW_Msk = 0x4 + // Bit TOTAL_TRANS_END_INT_RAW. + SPI1_INT_RAW_TOTAL_TRANS_END_INT_RAW = 0x4 + // Position of BROWN_OUT_INT_RAW field. + SPI1_INT_RAW_BROWN_OUT_INT_RAW_Pos = 0x3 + // Bit mask of BROWN_OUT_INT_RAW field. + SPI1_INT_RAW_BROWN_OUT_INT_RAW_Msk = 0x8 + // Bit BROWN_OUT_INT_RAW. + SPI1_INT_RAW_BROWN_OUT_INT_RAW = 0x8 + + // INT_ST: SPI1 interrupt status register + // Position of PER_END_INT_ST field. + SPI1_INT_ST_PER_END_INT_ST_Pos = 0x0 + // Bit mask of PER_END_INT_ST field. + SPI1_INT_ST_PER_END_INT_ST_Msk = 0x1 + // Bit PER_END_INT_ST. + SPI1_INT_ST_PER_END_INT_ST = 0x1 + // Position of PES_END_INT_ST field. + SPI1_INT_ST_PES_END_INT_ST_Pos = 0x1 + // Bit mask of PES_END_INT_ST field. + SPI1_INT_ST_PES_END_INT_ST_Msk = 0x2 + // Bit PES_END_INT_ST. + SPI1_INT_ST_PES_END_INT_ST = 0x2 + // Position of TOTAL_TRANS_END_INT_ST field. + SPI1_INT_ST_TOTAL_TRANS_END_INT_ST_Pos = 0x2 + // Bit mask of TOTAL_TRANS_END_INT_ST field. + SPI1_INT_ST_TOTAL_TRANS_END_INT_ST_Msk = 0x4 + // Bit TOTAL_TRANS_END_INT_ST. + SPI1_INT_ST_TOTAL_TRANS_END_INT_ST = 0x4 + // Position of BROWN_OUT_INT_ST field. + SPI1_INT_ST_BROWN_OUT_INT_ST_Pos = 0x3 + // Bit mask of BROWN_OUT_INT_ST field. + SPI1_INT_ST_BROWN_OUT_INT_ST_Msk = 0x8 + // Bit BROWN_OUT_INT_ST. + SPI1_INT_ST_BROWN_OUT_INT_ST = 0x8 + + // DATE: SPI0 version control register + // Position of DATE field. + SPI1_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI1_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SPI2: SPI (Serial Peripheral Interface) Controller 2 +const ( + // CMD: Command control register + // Position of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Pos = 0x0 + // Bit mask of CONF_BITLEN field. + SPI2_CMD_CONF_BITLEN_Msk = 0x3ffff + // Position of UPDATE field. + SPI2_CMD_UPDATE_Pos = 0x17 + // Bit mask of UPDATE field. + SPI2_CMD_UPDATE_Msk = 0x800000 + // Bit UPDATE. + SPI2_CMD_UPDATE = 0x800000 + // Position of USR field. + SPI2_CMD_USR_Pos = 0x18 + // Bit mask of USR field. + SPI2_CMD_USR_Msk = 0x1000000 + // Bit USR. + SPI2_CMD_USR = 0x1000000 + + // ADDR: Address value register + // Position of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Pos = 0x0 + // Bit mask of USR_ADDR_VALUE field. + SPI2_ADDR_USR_ADDR_VALUE_Msk = 0xffffffff + + // CTRL: SPI control register + // Position of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Pos = 0x3 + // Bit mask of DUMMY_OUT field. + SPI2_CTRL_DUMMY_OUT_Msk = 0x8 + // Bit DUMMY_OUT. + SPI2_CTRL_DUMMY_OUT = 0x8 + // Position of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Pos = 0x5 + // Bit mask of FADDR_DUAL field. + SPI2_CTRL_FADDR_DUAL_Msk = 0x20 + // Bit FADDR_DUAL. + SPI2_CTRL_FADDR_DUAL = 0x20 + // Position of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Pos = 0x6 + // Bit mask of FADDR_QUAD field. + SPI2_CTRL_FADDR_QUAD_Msk = 0x40 + // Bit FADDR_QUAD. + SPI2_CTRL_FADDR_QUAD = 0x40 + // Position of FADDR_OCT field. + SPI2_CTRL_FADDR_OCT_Pos = 0x7 + // Bit mask of FADDR_OCT field. + SPI2_CTRL_FADDR_OCT_Msk = 0x80 + // Bit FADDR_OCT. + SPI2_CTRL_FADDR_OCT = 0x80 + // Position of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Pos = 0x8 + // Bit mask of FCMD_DUAL field. + SPI2_CTRL_FCMD_DUAL_Msk = 0x100 + // Bit FCMD_DUAL. + SPI2_CTRL_FCMD_DUAL = 0x100 + // Position of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Pos = 0x9 + // Bit mask of FCMD_QUAD field. + SPI2_CTRL_FCMD_QUAD_Msk = 0x200 + // Bit FCMD_QUAD. + SPI2_CTRL_FCMD_QUAD = 0x200 + // Position of FCMD_OCT field. + SPI2_CTRL_FCMD_OCT_Pos = 0xa + // Bit mask of FCMD_OCT field. + SPI2_CTRL_FCMD_OCT_Msk = 0x400 + // Bit FCMD_OCT. + SPI2_CTRL_FCMD_OCT = 0x400 + // Position of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Pos = 0xe + // Bit mask of FREAD_DUAL field. + SPI2_CTRL_FREAD_DUAL_Msk = 0x4000 + // Bit FREAD_DUAL. + SPI2_CTRL_FREAD_DUAL = 0x4000 + // Position of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Pos = 0xf + // Bit mask of FREAD_QUAD field. + SPI2_CTRL_FREAD_QUAD_Msk = 0x8000 + // Bit FREAD_QUAD. + SPI2_CTRL_FREAD_QUAD = 0x8000 + // Position of FREAD_OCT field. + SPI2_CTRL_FREAD_OCT_Pos = 0x10 + // Bit mask of FREAD_OCT field. + SPI2_CTRL_FREAD_OCT_Msk = 0x10000 + // Bit FREAD_OCT. + SPI2_CTRL_FREAD_OCT = 0x10000 + // Position of Q_POL field. + SPI2_CTRL_Q_POL_Pos = 0x12 + // Bit mask of Q_POL field. + SPI2_CTRL_Q_POL_Msk = 0x40000 + // Bit Q_POL. + SPI2_CTRL_Q_POL = 0x40000 + // Position of D_POL field. + SPI2_CTRL_D_POL_Pos = 0x13 + // Bit mask of D_POL field. + SPI2_CTRL_D_POL_Msk = 0x80000 + // Bit D_POL. + SPI2_CTRL_D_POL = 0x80000 + // Position of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Pos = 0x14 + // Bit mask of HOLD_POL field. + SPI2_CTRL_HOLD_POL_Msk = 0x100000 + // Bit HOLD_POL. + SPI2_CTRL_HOLD_POL = 0x100000 + // Position of WP_POL field. + SPI2_CTRL_WP_POL_Pos = 0x15 + // Bit mask of WP_POL field. + SPI2_CTRL_WP_POL_Msk = 0x200000 + // Bit WP_POL. + SPI2_CTRL_WP_POL = 0x200000 + // Position of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Pos = 0x17 + // Bit mask of RD_BIT_ORDER field. + SPI2_CTRL_RD_BIT_ORDER_Msk = 0x1800000 + // Position of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Pos = 0x19 + // Bit mask of WR_BIT_ORDER field. + SPI2_CTRL_WR_BIT_ORDER_Msk = 0x6000000 + + // CLOCK: SPI clock control register + // Position of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Pos = 0x0 + // Bit mask of CLKCNT_L field. + SPI2_CLOCK_CLKCNT_L_Msk = 0x3f + // Position of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Pos = 0x6 + // Bit mask of CLKCNT_H field. + SPI2_CLOCK_CLKCNT_H_Msk = 0xfc0 + // Position of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Pos = 0xc + // Bit mask of CLKCNT_N field. + SPI2_CLOCK_CLKCNT_N_Msk = 0x3f000 + // Position of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Pos = 0x12 + // Bit mask of CLKDIV_PRE field. + SPI2_CLOCK_CLKDIV_PRE_Msk = 0x3c0000 + // Position of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of CLK_EQU_SYSCLK field. + SPI2_CLOCK_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit CLK_EQU_SYSCLK. + SPI2_CLOCK_CLK_EQU_SYSCLK = 0x80000000 + + // USER: SPI USER control register + // Position of DOUTDIN field. + SPI2_USER_DOUTDIN_Pos = 0x0 + // Bit mask of DOUTDIN field. + SPI2_USER_DOUTDIN_Msk = 0x1 + // Bit DOUTDIN. + SPI2_USER_DOUTDIN = 0x1 + // Position of QPI_MODE field. + SPI2_USER_QPI_MODE_Pos = 0x3 + // Bit mask of QPI_MODE field. + SPI2_USER_QPI_MODE_Msk = 0x8 + // Bit QPI_MODE. + SPI2_USER_QPI_MODE = 0x8 + // Position of OPI_MODE field. + SPI2_USER_OPI_MODE_Pos = 0x4 + // Bit mask of OPI_MODE field. + SPI2_USER_OPI_MODE_Msk = 0x10 + // Bit OPI_MODE. + SPI2_USER_OPI_MODE = 0x10 + // Position of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Pos = 0x5 + // Bit mask of TSCK_I_EDGE field. + SPI2_USER_TSCK_I_EDGE_Msk = 0x20 + // Bit TSCK_I_EDGE. + SPI2_USER_TSCK_I_EDGE = 0x20 + // Position of CS_HOLD field. + SPI2_USER_CS_HOLD_Pos = 0x6 + // Bit mask of CS_HOLD field. + SPI2_USER_CS_HOLD_Msk = 0x40 + // Bit CS_HOLD. + SPI2_USER_CS_HOLD = 0x40 + // Position of CS_SETUP field. + SPI2_USER_CS_SETUP_Pos = 0x7 + // Bit mask of CS_SETUP field. + SPI2_USER_CS_SETUP_Msk = 0x80 + // Bit CS_SETUP. + SPI2_USER_CS_SETUP = 0x80 + // Position of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Pos = 0x8 + // Bit mask of RSCK_I_EDGE field. + SPI2_USER_RSCK_I_EDGE_Msk = 0x100 + // Bit RSCK_I_EDGE. + SPI2_USER_RSCK_I_EDGE = 0x100 + // Position of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Pos = 0x9 + // Bit mask of CK_OUT_EDGE field. + SPI2_USER_CK_OUT_EDGE_Msk = 0x200 + // Bit CK_OUT_EDGE. + SPI2_USER_CK_OUT_EDGE = 0x200 + // Position of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Pos = 0xc + // Bit mask of FWRITE_DUAL field. + SPI2_USER_FWRITE_DUAL_Msk = 0x1000 + // Bit FWRITE_DUAL. + SPI2_USER_FWRITE_DUAL = 0x1000 + // Position of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Pos = 0xd + // Bit mask of FWRITE_QUAD field. + SPI2_USER_FWRITE_QUAD_Msk = 0x2000 + // Bit FWRITE_QUAD. + SPI2_USER_FWRITE_QUAD = 0x2000 + // Position of FWRITE_OCT field. + SPI2_USER_FWRITE_OCT_Pos = 0xe + // Bit mask of FWRITE_OCT field. + SPI2_USER_FWRITE_OCT_Msk = 0x4000 + // Bit FWRITE_OCT. + SPI2_USER_FWRITE_OCT = 0x4000 + // Position of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Pos = 0xf + // Bit mask of USR_CONF_NXT field. + SPI2_USER_USR_CONF_NXT_Msk = 0x8000 + // Bit USR_CONF_NXT. + SPI2_USER_USR_CONF_NXT = 0x8000 + // Position of SIO field. + SPI2_USER_SIO_Pos = 0x11 + // Bit mask of SIO field. + SPI2_USER_SIO_Msk = 0x20000 + // Bit SIO. + SPI2_USER_SIO = 0x20000 + // Position of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of USR_MISO_HIGHPART field. + SPI2_USER_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit USR_MISO_HIGHPART. + SPI2_USER_USR_MISO_HIGHPART = 0x1000000 + // Position of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of USR_MOSI_HIGHPART field. + SPI2_USER_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit USR_MOSI_HIGHPART. + SPI2_USER_USR_MOSI_HIGHPART = 0x2000000 + // Position of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Pos = 0x1a + // Bit mask of USR_DUMMY_IDLE field. + SPI2_USER_USR_DUMMY_IDLE_Msk = 0x4000000 + // Bit USR_DUMMY_IDLE. + SPI2_USER_USR_DUMMY_IDLE = 0x4000000 + // Position of USR_MOSI field. + SPI2_USER_USR_MOSI_Pos = 0x1b + // Bit mask of USR_MOSI field. + SPI2_USER_USR_MOSI_Msk = 0x8000000 + // Bit USR_MOSI. + SPI2_USER_USR_MOSI = 0x8000000 + // Position of USR_MISO field. + SPI2_USER_USR_MISO_Pos = 0x1c + // Bit mask of USR_MISO field. + SPI2_USER_USR_MISO_Msk = 0x10000000 + // Bit USR_MISO. + SPI2_USER_USR_MISO = 0x10000000 + // Position of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Pos = 0x1d + // Bit mask of USR_DUMMY field. + SPI2_USER_USR_DUMMY_Msk = 0x20000000 + // Bit USR_DUMMY. + SPI2_USER_USR_DUMMY = 0x20000000 + // Position of USR_ADDR field. + SPI2_USER_USR_ADDR_Pos = 0x1e + // Bit mask of USR_ADDR field. + SPI2_USER_USR_ADDR_Msk = 0x40000000 + // Bit USR_ADDR. + SPI2_USER_USR_ADDR = 0x40000000 + // Position of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Pos = 0x1f + // Bit mask of USR_COMMAND field. + SPI2_USER_USR_COMMAND_Msk = 0x80000000 + // Bit USR_COMMAND. + SPI2_USER_USR_COMMAND = 0x80000000 + + // USER1: SPI USER control register 1 + // Position of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of USR_DUMMY_CYCLELEN field. + SPI2_USER1_USR_DUMMY_CYCLELEN_Msk = 0xff + // Position of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Pos = 0x10 + // Bit mask of MST_WFULL_ERR_END_EN field. + SPI2_USER1_MST_WFULL_ERR_END_EN_Msk = 0x10000 + // Bit MST_WFULL_ERR_END_EN. + SPI2_USER1_MST_WFULL_ERR_END_EN = 0x10000 + // Position of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Pos = 0x11 + // Bit mask of CS_SETUP_TIME field. + SPI2_USER1_CS_SETUP_TIME_Msk = 0x3e0000 + // Position of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Pos = 0x16 + // Bit mask of CS_HOLD_TIME field. + SPI2_USER1_CS_HOLD_TIME_Msk = 0x7c00000 + // Position of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Pos = 0x1b + // Bit mask of USR_ADDR_BITLEN field. + SPI2_USER1_USR_ADDR_BITLEN_Msk = 0xf8000000 + + // USER2: SPI USER control register 2 + // Position of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of USR_COMMAND_VALUE field. + SPI2_USER2_USR_COMMAND_VALUE_Msk = 0xffff + // Position of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Pos = 0x1b + // Bit mask of MST_REMPTY_ERR_END_EN field. + SPI2_USER2_MST_REMPTY_ERR_END_EN_Msk = 0x8000000 + // Bit MST_REMPTY_ERR_END_EN. + SPI2_USER2_MST_REMPTY_ERR_END_EN = 0x8000000 + // Position of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of USR_COMMAND_BITLEN field. + SPI2_USER2_USR_COMMAND_BITLEN_Msk = 0xf0000000 + + // MS_DLEN: SPI data bit length control register + // Position of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Pos = 0x0 + // Bit mask of MS_DATA_BITLEN field. + SPI2_MS_DLEN_MS_DATA_BITLEN_Msk = 0x3ffff + + // MISC: SPI misc register + // Position of CS0_DIS field. + SPI2_MISC_CS0_DIS_Pos = 0x0 + // Bit mask of CS0_DIS field. + SPI2_MISC_CS0_DIS_Msk = 0x1 + // Bit CS0_DIS. + SPI2_MISC_CS0_DIS = 0x1 + // Position of CS1_DIS field. + SPI2_MISC_CS1_DIS_Pos = 0x1 + // Bit mask of CS1_DIS field. + SPI2_MISC_CS1_DIS_Msk = 0x2 + // Bit CS1_DIS. + SPI2_MISC_CS1_DIS = 0x2 + // Position of CS2_DIS field. + SPI2_MISC_CS2_DIS_Pos = 0x2 + // Bit mask of CS2_DIS field. + SPI2_MISC_CS2_DIS_Msk = 0x4 + // Bit CS2_DIS. + SPI2_MISC_CS2_DIS = 0x4 + // Position of CS3_DIS field. + SPI2_MISC_CS3_DIS_Pos = 0x3 + // Bit mask of CS3_DIS field. + SPI2_MISC_CS3_DIS_Msk = 0x8 + // Bit CS3_DIS. + SPI2_MISC_CS3_DIS = 0x8 + // Position of CS4_DIS field. + SPI2_MISC_CS4_DIS_Pos = 0x4 + // Bit mask of CS4_DIS field. + SPI2_MISC_CS4_DIS_Msk = 0x10 + // Bit CS4_DIS. + SPI2_MISC_CS4_DIS = 0x10 + // Position of CS5_DIS field. + SPI2_MISC_CS5_DIS_Pos = 0x5 + // Bit mask of CS5_DIS field. + SPI2_MISC_CS5_DIS_Msk = 0x20 + // Bit CS5_DIS. + SPI2_MISC_CS5_DIS = 0x20 + // Position of CK_DIS field. + SPI2_MISC_CK_DIS_Pos = 0x6 + // Bit mask of CK_DIS field. + SPI2_MISC_CK_DIS_Msk = 0x40 + // Bit CK_DIS. + SPI2_MISC_CK_DIS = 0x40 + // Position of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Pos = 0x7 + // Bit mask of MASTER_CS_POL field. + SPI2_MISC_MASTER_CS_POL_Msk = 0x1f80 + // Position of CLK_DATA_DTR_EN field. + SPI2_MISC_CLK_DATA_DTR_EN_Pos = 0x10 + // Bit mask of CLK_DATA_DTR_EN field. + SPI2_MISC_CLK_DATA_DTR_EN_Msk = 0x10000 + // Bit CLK_DATA_DTR_EN. + SPI2_MISC_CLK_DATA_DTR_EN = 0x10000 + // Position of DATA_DTR_EN field. + SPI2_MISC_DATA_DTR_EN_Pos = 0x11 + // Bit mask of DATA_DTR_EN field. + SPI2_MISC_DATA_DTR_EN_Msk = 0x20000 + // Bit DATA_DTR_EN. + SPI2_MISC_DATA_DTR_EN = 0x20000 + // Position of ADDR_DTR_EN field. + SPI2_MISC_ADDR_DTR_EN_Pos = 0x12 + // Bit mask of ADDR_DTR_EN field. + SPI2_MISC_ADDR_DTR_EN_Msk = 0x40000 + // Bit ADDR_DTR_EN. + SPI2_MISC_ADDR_DTR_EN = 0x40000 + // Position of CMD_DTR_EN field. + SPI2_MISC_CMD_DTR_EN_Pos = 0x13 + // Bit mask of CMD_DTR_EN field. + SPI2_MISC_CMD_DTR_EN_Msk = 0x80000 + // Bit CMD_DTR_EN. + SPI2_MISC_CMD_DTR_EN = 0x80000 + // Position of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Pos = 0x17 + // Bit mask of SLAVE_CS_POL field. + SPI2_MISC_SLAVE_CS_POL_Msk = 0x800000 + // Bit SLAVE_CS_POL. + SPI2_MISC_SLAVE_CS_POL = 0x800000 + // Position of DQS_IDLE_EDGE field. + SPI2_MISC_DQS_IDLE_EDGE_Pos = 0x18 + // Bit mask of DQS_IDLE_EDGE field. + SPI2_MISC_DQS_IDLE_EDGE_Msk = 0x1000000 + // Bit DQS_IDLE_EDGE. + SPI2_MISC_DQS_IDLE_EDGE = 0x1000000 + // Position of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Pos = 0x1d + // Bit mask of CK_IDLE_EDGE field. + SPI2_MISC_CK_IDLE_EDGE_Msk = 0x20000000 + // Bit CK_IDLE_EDGE. + SPI2_MISC_CK_IDLE_EDGE = 0x20000000 + // Position of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Pos = 0x1e + // Bit mask of CS_KEEP_ACTIVE field. + SPI2_MISC_CS_KEEP_ACTIVE_Msk = 0x40000000 + // Bit CS_KEEP_ACTIVE. + SPI2_MISC_CS_KEEP_ACTIVE = 0x40000000 + // Position of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Pos = 0x1f + // Bit mask of QUAD_DIN_PIN_SWAP field. + SPI2_MISC_QUAD_DIN_PIN_SWAP_Msk = 0x80000000 + // Bit QUAD_DIN_PIN_SWAP. + SPI2_MISC_QUAD_DIN_PIN_SWAP = 0x80000000 + + // DIN_MODE: SPI input delay mode configuration + // Position of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Pos = 0x0 + // Bit mask of DIN0_MODE field. + SPI2_DIN_MODE_DIN0_MODE_Msk = 0x3 + // Position of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Pos = 0x2 + // Bit mask of DIN1_MODE field. + SPI2_DIN_MODE_DIN1_MODE_Msk = 0xc + // Position of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Pos = 0x4 + // Bit mask of DIN2_MODE field. + SPI2_DIN_MODE_DIN2_MODE_Msk = 0x30 + // Position of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Pos = 0x6 + // Bit mask of DIN3_MODE field. + SPI2_DIN_MODE_DIN3_MODE_Msk = 0xc0 + // Position of DIN4_MODE field. + SPI2_DIN_MODE_DIN4_MODE_Pos = 0x8 + // Bit mask of DIN4_MODE field. + SPI2_DIN_MODE_DIN4_MODE_Msk = 0x300 + // Position of DIN5_MODE field. + SPI2_DIN_MODE_DIN5_MODE_Pos = 0xa + // Bit mask of DIN5_MODE field. + SPI2_DIN_MODE_DIN5_MODE_Msk = 0xc00 + // Position of DIN6_MODE field. + SPI2_DIN_MODE_DIN6_MODE_Pos = 0xc + // Bit mask of DIN6_MODE field. + SPI2_DIN_MODE_DIN6_MODE_Msk = 0x3000 + // Position of DIN7_MODE field. + SPI2_DIN_MODE_DIN7_MODE_Pos = 0xe + // Bit mask of DIN7_MODE field. + SPI2_DIN_MODE_DIN7_MODE_Msk = 0xc000 + // Position of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Pos = 0x10 + // Bit mask of TIMING_HCLK_ACTIVE field. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE_Msk = 0x10000 + // Bit TIMING_HCLK_ACTIVE. + SPI2_DIN_MODE_TIMING_HCLK_ACTIVE = 0x10000 + + // DIN_NUM: SPI input delay number configuration + // Position of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Pos = 0x0 + // Bit mask of DIN0_NUM field. + SPI2_DIN_NUM_DIN0_NUM_Msk = 0x3 + // Position of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Pos = 0x2 + // Bit mask of DIN1_NUM field. + SPI2_DIN_NUM_DIN1_NUM_Msk = 0xc + // Position of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Pos = 0x4 + // Bit mask of DIN2_NUM field. + SPI2_DIN_NUM_DIN2_NUM_Msk = 0x30 + // Position of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Pos = 0x6 + // Bit mask of DIN3_NUM field. + SPI2_DIN_NUM_DIN3_NUM_Msk = 0xc0 + // Position of DIN4_NUM field. + SPI2_DIN_NUM_DIN4_NUM_Pos = 0x8 + // Bit mask of DIN4_NUM field. + SPI2_DIN_NUM_DIN4_NUM_Msk = 0x300 + // Position of DIN5_NUM field. + SPI2_DIN_NUM_DIN5_NUM_Pos = 0xa + // Bit mask of DIN5_NUM field. + SPI2_DIN_NUM_DIN5_NUM_Msk = 0xc00 + // Position of DIN6_NUM field. + SPI2_DIN_NUM_DIN6_NUM_Pos = 0xc + // Bit mask of DIN6_NUM field. + SPI2_DIN_NUM_DIN6_NUM_Msk = 0x3000 + // Position of DIN7_NUM field. + SPI2_DIN_NUM_DIN7_NUM_Pos = 0xe + // Bit mask of DIN7_NUM field. + SPI2_DIN_NUM_DIN7_NUM_Msk = 0xc000 + + // DOUT_MODE: SPI output delay mode configuration + // Position of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Pos = 0x0 + // Bit mask of DOUT0_MODE field. + SPI2_DOUT_MODE_DOUT0_MODE_Msk = 0x1 + // Bit DOUT0_MODE. + SPI2_DOUT_MODE_DOUT0_MODE = 0x1 + // Position of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Pos = 0x1 + // Bit mask of DOUT1_MODE field. + SPI2_DOUT_MODE_DOUT1_MODE_Msk = 0x2 + // Bit DOUT1_MODE. + SPI2_DOUT_MODE_DOUT1_MODE = 0x2 + // Position of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Pos = 0x2 + // Bit mask of DOUT2_MODE field. + SPI2_DOUT_MODE_DOUT2_MODE_Msk = 0x4 + // Bit DOUT2_MODE. + SPI2_DOUT_MODE_DOUT2_MODE = 0x4 + // Position of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Pos = 0x3 + // Bit mask of DOUT3_MODE field. + SPI2_DOUT_MODE_DOUT3_MODE_Msk = 0x8 + // Bit DOUT3_MODE. + SPI2_DOUT_MODE_DOUT3_MODE = 0x8 + // Position of DOUT4_MODE field. + SPI2_DOUT_MODE_DOUT4_MODE_Pos = 0x4 + // Bit mask of DOUT4_MODE field. + SPI2_DOUT_MODE_DOUT4_MODE_Msk = 0x10 + // Bit DOUT4_MODE. + SPI2_DOUT_MODE_DOUT4_MODE = 0x10 + // Position of DOUT5_MODE field. + SPI2_DOUT_MODE_DOUT5_MODE_Pos = 0x5 + // Bit mask of DOUT5_MODE field. + SPI2_DOUT_MODE_DOUT5_MODE_Msk = 0x20 + // Bit DOUT5_MODE. + SPI2_DOUT_MODE_DOUT5_MODE = 0x20 + // Position of DOUT6_MODE field. + SPI2_DOUT_MODE_DOUT6_MODE_Pos = 0x6 + // Bit mask of DOUT6_MODE field. + SPI2_DOUT_MODE_DOUT6_MODE_Msk = 0x40 + // Bit DOUT6_MODE. + SPI2_DOUT_MODE_DOUT6_MODE = 0x40 + // Position of DOUT7_MODE field. + SPI2_DOUT_MODE_DOUT7_MODE_Pos = 0x7 + // Bit mask of DOUT7_MODE field. + SPI2_DOUT_MODE_DOUT7_MODE_Msk = 0x80 + // Bit DOUT7_MODE. + SPI2_DOUT_MODE_DOUT7_MODE = 0x80 + // Position of D_DQS_MODE field. + SPI2_DOUT_MODE_D_DQS_MODE_Pos = 0x8 + // Bit mask of D_DQS_MODE field. + SPI2_DOUT_MODE_D_DQS_MODE_Msk = 0x100 + // Bit D_DQS_MODE. + SPI2_DOUT_MODE_D_DQS_MODE = 0x100 + + // DMA_CONF: SPI DMA control register + // Position of DMA_OUTFIFO_EMPTY field. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY_Pos = 0x0 + // Bit mask of DMA_OUTFIFO_EMPTY field. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY_Msk = 0x1 + // Bit DMA_OUTFIFO_EMPTY. + SPI2_DMA_CONF_DMA_OUTFIFO_EMPTY = 0x1 + // Position of DMA_INFIFO_FULL field. + SPI2_DMA_CONF_DMA_INFIFO_FULL_Pos = 0x1 + // Bit mask of DMA_INFIFO_FULL field. + SPI2_DMA_CONF_DMA_INFIFO_FULL_Msk = 0x2 + // Bit DMA_INFIFO_FULL. + SPI2_DMA_CONF_DMA_INFIFO_FULL = 0x2 + // Position of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Pos = 0x12 + // Bit mask of DMA_SLV_SEG_TRANS_EN field. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN_Msk = 0x40000 + // Bit DMA_SLV_SEG_TRANS_EN. + SPI2_DMA_CONF_DMA_SLV_SEG_TRANS_EN = 0x40000 + // Position of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Pos = 0x13 + // Bit mask of SLV_RX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN_Msk = 0x80000 + // Bit SLV_RX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_RX_SEG_TRANS_CLR_EN = 0x80000 + // Position of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Pos = 0x14 + // Bit mask of SLV_TX_SEG_TRANS_CLR_EN field. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN_Msk = 0x100000 + // Bit SLV_TX_SEG_TRANS_CLR_EN. + SPI2_DMA_CONF_SLV_TX_SEG_TRANS_CLR_EN = 0x100000 + // Position of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Pos = 0x15 + // Bit mask of RX_EOF_EN field. + SPI2_DMA_CONF_RX_EOF_EN_Msk = 0x200000 + // Bit RX_EOF_EN. + SPI2_DMA_CONF_RX_EOF_EN = 0x200000 + // Position of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Pos = 0x1b + // Bit mask of DMA_RX_ENA field. + SPI2_DMA_CONF_DMA_RX_ENA_Msk = 0x8000000 + // Bit DMA_RX_ENA. + SPI2_DMA_CONF_DMA_RX_ENA = 0x8000000 + // Position of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Pos = 0x1c + // Bit mask of DMA_TX_ENA field. + SPI2_DMA_CONF_DMA_TX_ENA_Msk = 0x10000000 + // Bit DMA_TX_ENA. + SPI2_DMA_CONF_DMA_TX_ENA = 0x10000000 + // Position of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Pos = 0x1d + // Bit mask of RX_AFIFO_RST field. + SPI2_DMA_CONF_RX_AFIFO_RST_Msk = 0x20000000 + // Bit RX_AFIFO_RST. + SPI2_DMA_CONF_RX_AFIFO_RST = 0x20000000 + // Position of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Pos = 0x1e + // Bit mask of BUF_AFIFO_RST field. + SPI2_DMA_CONF_BUF_AFIFO_RST_Msk = 0x40000000 + // Bit BUF_AFIFO_RST. + SPI2_DMA_CONF_BUF_AFIFO_RST = 0x40000000 + // Position of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Pos = 0x1f + // Bit mask of DMA_AFIFO_RST field. + SPI2_DMA_CONF_DMA_AFIFO_RST_Msk = 0x80000000 + // Bit DMA_AFIFO_RST. + SPI2_DMA_CONF_DMA_AFIFO_RST = 0x80000000 + + // DMA_INT_ENA: SPI interrupt enable register + // Position of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_INFIFO_FULL_ERR_INT_ENA = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_DMA_OUTFIFO_EMPTY_ERR_INT_ENA = 0x2 + // Position of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EX_QPI_INT_ENA = 0x4 + // Position of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ENA. + SPI2_DMA_INT_ENA_SLV_EN_QPI_INT_ENA = 0x8 + // Position of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA_Msk = 0x10 + // Bit SLV_CMD7_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD7_INT_ENA = 0x10 + // Position of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA_Msk = 0x20 + // Bit SLV_CMD8_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD8_INT_ENA = 0x20 + // Position of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA_Msk = 0x40 + // Bit SLV_CMD9_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD9_INT_ENA = 0x40 + // Position of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA_Msk = 0x80 + // Bit SLV_CMDA_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMDA_INT_ENA = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_DMA_DONE_INT_ENA = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_DMA_DONE_INT_ENA = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_RD_BUF_DONE_INT_ENA = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ENA. + SPI2_DMA_INT_ENA_SLV_WR_BUF_DONE_INT_ENA = 0x800 + // Position of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA_Msk = 0x1000 + // Bit TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_TRANS_DONE_INT_ENA = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ENA field. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ENA. + SPI2_DMA_INT_ENA_DMA_SEG_TRANS_DONE_INT_ENA = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SEG_MAGIC_ERR_INT_ENA = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_BUF_ADDR_ERR_INT_ENA = 0x8000 + // Position of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ENA. + SPI2_DMA_INT_ENA_SLV_CMD_ERR_INT_ENA = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_RX_AFIFO_WFULL_ERR_INT_ENA = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ENA field. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ENA. + SPI2_DMA_INT_ENA_MST_TX_AFIFO_REMPTY_ERR_INT_ENA = 0x40000 + // Position of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Pos = 0x13 + // Bit mask of APP2_INT_ENA field. + SPI2_DMA_INT_ENA_APP2_INT_ENA_Msk = 0x80000 + // Bit APP2_INT_ENA. + SPI2_DMA_INT_ENA_APP2_INT_ENA = 0x80000 + // Position of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Pos = 0x14 + // Bit mask of APP1_INT_ENA field. + SPI2_DMA_INT_ENA_APP1_INT_ENA_Msk = 0x100000 + // Bit APP1_INT_ENA. + SPI2_DMA_INT_ENA_APP1_INT_ENA = 0x100000 + + // DMA_INT_CLR: SPI interrupt clear register + // Position of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_INFIFO_FULL_ERR_INT_CLR = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_DMA_OUTFIFO_EMPTY_ERR_INT_CLR = 0x2 + // Position of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR_Msk = 0x4 + // Bit SLV_EX_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EX_QPI_INT_CLR = 0x4 + // Position of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR_Msk = 0x8 + // Bit SLV_EN_QPI_INT_CLR. + SPI2_DMA_INT_CLR_SLV_EN_QPI_INT_CLR = 0x8 + // Position of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR_Msk = 0x10 + // Bit SLV_CMD7_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD7_INT_CLR = 0x10 + // Position of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR_Msk = 0x20 + // Bit SLV_CMD8_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD8_INT_CLR = 0x20 + // Position of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR_Msk = 0x40 + // Bit SLV_CMD9_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD9_INT_CLR = 0x40 + // Position of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR_Msk = 0x80 + // Bit SLV_CMDA_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMDA_INT_CLR = 0x80 + // Position of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_DMA_DONE_INT_CLR = 0x100 + // Position of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_DMA_DONE_INT_CLR = 0x200 + // Position of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_RD_BUF_DONE_INT_CLR = 0x400 + // Position of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_CLR. + SPI2_DMA_INT_CLR_SLV_WR_BUF_DONE_INT_CLR = 0x800 + // Position of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Pos = 0xc + // Bit mask of TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR_Msk = 0x1000 + // Bit TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_TRANS_DONE_INT_CLR = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_CLR field. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_CLR. + SPI2_DMA_INT_CLR_DMA_SEG_TRANS_DONE_INT_CLR = 0x2000 + // Position of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SEG_MAGIC_ERR_INT_CLR = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_BUF_ADDR_ERR_INT_CLR = 0x8000 + // Position of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_CLR. + SPI2_DMA_INT_CLR_SLV_CMD_ERR_INT_CLR = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_RX_AFIFO_WFULL_ERR_INT_CLR = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_CLR field. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_CLR. + SPI2_DMA_INT_CLR_MST_TX_AFIFO_REMPTY_ERR_INT_CLR = 0x40000 + // Position of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Pos = 0x13 + // Bit mask of APP2_INT_CLR field. + SPI2_DMA_INT_CLR_APP2_INT_CLR_Msk = 0x80000 + // Bit APP2_INT_CLR. + SPI2_DMA_INT_CLR_APP2_INT_CLR = 0x80000 + // Position of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Pos = 0x14 + // Bit mask of APP1_INT_CLR field. + SPI2_DMA_INT_CLR_APP1_INT_CLR_Msk = 0x100000 + // Bit APP1_INT_CLR. + SPI2_DMA_INT_CLR_APP1_INT_CLR = 0x100000 + + // DMA_INT_RAW: SPI interrupt raw register + // Position of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_INFIFO_FULL_ERR_INT_RAW = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_DMA_OUTFIFO_EMPTY_ERR_INT_RAW = 0x2 + // Position of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW_Msk = 0x4 + // Bit SLV_EX_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EX_QPI_INT_RAW = 0x4 + // Position of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW_Msk = 0x8 + // Bit SLV_EN_QPI_INT_RAW. + SPI2_DMA_INT_RAW_SLV_EN_QPI_INT_RAW = 0x8 + // Position of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW_Msk = 0x10 + // Bit SLV_CMD7_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD7_INT_RAW = 0x10 + // Position of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW_Msk = 0x20 + // Bit SLV_CMD8_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD8_INT_RAW = 0x20 + // Position of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW_Msk = 0x40 + // Bit SLV_CMD9_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD9_INT_RAW = 0x40 + // Position of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW_Msk = 0x80 + // Bit SLV_CMDA_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMDA_INT_RAW = 0x80 + // Position of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_DMA_DONE_INT_RAW = 0x100 + // Position of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_DMA_DONE_INT_RAW = 0x200 + // Position of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_RD_BUF_DONE_INT_RAW = 0x400 + // Position of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_RAW. + SPI2_DMA_INT_RAW_SLV_WR_BUF_DONE_INT_RAW = 0x800 + // Position of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Pos = 0xc + // Bit mask of TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW_Msk = 0x1000 + // Bit TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_TRANS_DONE_INT_RAW = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_RAW field. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_RAW. + SPI2_DMA_INT_RAW_DMA_SEG_TRANS_DONE_INT_RAW = 0x2000 + // Position of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SEG_MAGIC_ERR_INT_RAW = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_BUF_ADDR_ERR_INT_RAW = 0x8000 + // Position of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_RAW. + SPI2_DMA_INT_RAW_SLV_CMD_ERR_INT_RAW = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_RX_AFIFO_WFULL_ERR_INT_RAW = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_RAW field. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_RAW. + SPI2_DMA_INT_RAW_MST_TX_AFIFO_REMPTY_ERR_INT_RAW = 0x40000 + // Position of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Pos = 0x13 + // Bit mask of APP2_INT_RAW field. + SPI2_DMA_INT_RAW_APP2_INT_RAW_Msk = 0x80000 + // Bit APP2_INT_RAW. + SPI2_DMA_INT_RAW_APP2_INT_RAW = 0x80000 + // Position of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Pos = 0x14 + // Bit mask of APP1_INT_RAW field. + SPI2_DMA_INT_RAW_APP1_INT_RAW_Msk = 0x100000 + // Bit APP1_INT_RAW. + SPI2_DMA_INT_RAW_APP1_INT_RAW = 0x100000 + + // DMA_INT_ST: SPI interrupt status register + // Position of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_INFIFO_FULL_ERR_INT_ST = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_DMA_OUTFIFO_EMPTY_ERR_INT_ST = 0x2 + // Position of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST_Msk = 0x4 + // Bit SLV_EX_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EX_QPI_INT_ST = 0x4 + // Position of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_ST field. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST_Msk = 0x8 + // Bit SLV_EN_QPI_INT_ST. + SPI2_DMA_INT_ST_SLV_EN_QPI_INT_ST = 0x8 + // Position of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST_Msk = 0x10 + // Bit SLV_CMD7_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD7_INT_ST = 0x10 + // Position of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST_Msk = 0x20 + // Bit SLV_CMD8_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD8_INT_ST = 0x20 + // Position of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST_Msk = 0x40 + // Bit SLV_CMD9_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD9_INT_ST = 0x40 + // Position of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST_Msk = 0x80 + // Bit SLV_CMDA_INT_ST. + SPI2_DMA_INT_ST_SLV_CMDA_INT_ST = 0x80 + // Position of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_DMA_DONE_INT_ST = 0x100 + // Position of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_DMA_DONE_INT_ST = 0x200 + // Position of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_RD_BUF_DONE_INT_ST = 0x400 + // Position of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_ST field. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_ST. + SPI2_DMA_INT_ST_SLV_WR_BUF_DONE_INT_ST = 0x800 + // Position of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Pos = 0xc + // Bit mask of TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST_Msk = 0x1000 + // Bit TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_TRANS_DONE_INT_ST = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_ST field. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_ST. + SPI2_DMA_INT_ST_DMA_SEG_TRANS_DONE_INT_ST = 0x2000 + // Position of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_ST field. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_ST. + SPI2_DMA_INT_ST_SEG_MAGIC_ERR_INT_ST = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_BUF_ADDR_ERR_INT_ST = 0x8000 + // Position of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_ST field. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_ST. + SPI2_DMA_INT_ST_SLV_CMD_ERR_INT_ST = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_RX_AFIFO_WFULL_ERR_INT_ST = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_ST field. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_ST. + SPI2_DMA_INT_ST_MST_TX_AFIFO_REMPTY_ERR_INT_ST = 0x40000 + // Position of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Pos = 0x13 + // Bit mask of APP2_INT_ST field. + SPI2_DMA_INT_ST_APP2_INT_ST_Msk = 0x80000 + // Bit APP2_INT_ST. + SPI2_DMA_INT_ST_APP2_INT_ST = 0x80000 + // Position of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Pos = 0x14 + // Bit mask of APP1_INT_ST field. + SPI2_DMA_INT_ST_APP1_INT_ST_Msk = 0x100000 + // Bit APP1_INT_ST. + SPI2_DMA_INT_ST_APP1_INT_ST = 0x100000 + + // DMA_INT_SET: SPI interrupt software set register + // Position of DMA_INFIFO_FULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET_Pos = 0x0 + // Bit mask of DMA_INFIFO_FULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET_Msk = 0x1 + // Bit DMA_INFIFO_FULL_ERR_INT_SET. + SPI2_DMA_INT_SET_DMA_INFIFO_FULL_ERR_INT_SET = 0x1 + // Position of DMA_OUTFIFO_EMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Pos = 0x1 + // Bit mask of DMA_OUTFIFO_EMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Msk = 0x2 + // Bit DMA_OUTFIFO_EMPTY_ERR_INT_SET. + SPI2_DMA_INT_SET_DMA_OUTFIFO_EMPTY_ERR_INT_SET = 0x2 + // Position of SLV_EX_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET_Pos = 0x2 + // Bit mask of SLV_EX_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET_Msk = 0x4 + // Bit SLV_EX_QPI_INT_SET. + SPI2_DMA_INT_SET_SLV_EX_QPI_INT_SET = 0x4 + // Position of SLV_EN_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET_Pos = 0x3 + // Bit mask of SLV_EN_QPI_INT_SET field. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET_Msk = 0x8 + // Bit SLV_EN_QPI_INT_SET. + SPI2_DMA_INT_SET_SLV_EN_QPI_INT_SET = 0x8 + // Position of SLV_CMD7_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET_Pos = 0x4 + // Bit mask of SLV_CMD7_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET_Msk = 0x10 + // Bit SLV_CMD7_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD7_INT_SET = 0x10 + // Position of SLV_CMD8_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET_Pos = 0x5 + // Bit mask of SLV_CMD8_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET_Msk = 0x20 + // Bit SLV_CMD8_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD8_INT_SET = 0x20 + // Position of SLV_CMD9_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET_Pos = 0x6 + // Bit mask of SLV_CMD9_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET_Msk = 0x40 + // Bit SLV_CMD9_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD9_INT_SET = 0x40 + // Position of SLV_CMDA_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET_Pos = 0x7 + // Bit mask of SLV_CMDA_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET_Msk = 0x80 + // Bit SLV_CMDA_INT_SET. + SPI2_DMA_INT_SET_SLV_CMDA_INT_SET = 0x80 + // Position of SLV_RD_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET_Pos = 0x8 + // Bit mask of SLV_RD_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET_Msk = 0x100 + // Bit SLV_RD_DMA_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_RD_DMA_DONE_INT_SET = 0x100 + // Position of SLV_WR_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET_Pos = 0x9 + // Bit mask of SLV_WR_DMA_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET_Msk = 0x200 + // Bit SLV_WR_DMA_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_WR_DMA_DONE_INT_SET = 0x200 + // Position of SLV_RD_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET_Pos = 0xa + // Bit mask of SLV_RD_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET_Msk = 0x400 + // Bit SLV_RD_BUF_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_RD_BUF_DONE_INT_SET = 0x400 + // Position of SLV_WR_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET_Pos = 0xb + // Bit mask of SLV_WR_BUF_DONE_INT_SET field. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET_Msk = 0x800 + // Bit SLV_WR_BUF_DONE_INT_SET. + SPI2_DMA_INT_SET_SLV_WR_BUF_DONE_INT_SET = 0x800 + // Position of TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET_Pos = 0xc + // Bit mask of TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET_Msk = 0x1000 + // Bit TRANS_DONE_INT_SET. + SPI2_DMA_INT_SET_TRANS_DONE_INT_SET = 0x1000 + // Position of DMA_SEG_TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET_Pos = 0xd + // Bit mask of DMA_SEG_TRANS_DONE_INT_SET field. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET_Msk = 0x2000 + // Bit DMA_SEG_TRANS_DONE_INT_SET. + SPI2_DMA_INT_SET_DMA_SEG_TRANS_DONE_INT_SET = 0x2000 + // Position of SEG_MAGIC_ERR_INT_SET field. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET_Pos = 0xe + // Bit mask of SEG_MAGIC_ERR_INT_SET field. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET_Msk = 0x4000 + // Bit SEG_MAGIC_ERR_INT_SET. + SPI2_DMA_INT_SET_SEG_MAGIC_ERR_INT_SET = 0x4000 + // Position of SLV_BUF_ADDR_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET_Pos = 0xf + // Bit mask of SLV_BUF_ADDR_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET_Msk = 0x8000 + // Bit SLV_BUF_ADDR_ERR_INT_SET. + SPI2_DMA_INT_SET_SLV_BUF_ADDR_ERR_INT_SET = 0x8000 + // Position of SLV_CMD_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET_Pos = 0x10 + // Bit mask of SLV_CMD_ERR_INT_SET field. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET_Msk = 0x10000 + // Bit SLV_CMD_ERR_INT_SET. + SPI2_DMA_INT_SET_SLV_CMD_ERR_INT_SET = 0x10000 + // Position of MST_RX_AFIFO_WFULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET_Pos = 0x11 + // Bit mask of MST_RX_AFIFO_WFULL_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET_Msk = 0x20000 + // Bit MST_RX_AFIFO_WFULL_ERR_INT_SET. + SPI2_DMA_INT_SET_MST_RX_AFIFO_WFULL_ERR_INT_SET = 0x20000 + // Position of MST_TX_AFIFO_REMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Pos = 0x12 + // Bit mask of MST_TX_AFIFO_REMPTY_ERR_INT_SET field. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Msk = 0x40000 + // Bit MST_TX_AFIFO_REMPTY_ERR_INT_SET. + SPI2_DMA_INT_SET_MST_TX_AFIFO_REMPTY_ERR_INT_SET = 0x40000 + // Position of APP2_INT_SET field. + SPI2_DMA_INT_SET_APP2_INT_SET_Pos = 0x13 + // Bit mask of APP2_INT_SET field. + SPI2_DMA_INT_SET_APP2_INT_SET_Msk = 0x80000 + // Bit APP2_INT_SET. + SPI2_DMA_INT_SET_APP2_INT_SET = 0x80000 + // Position of APP1_INT_SET field. + SPI2_DMA_INT_SET_APP1_INT_SET_Pos = 0x14 + // Bit mask of APP1_INT_SET field. + SPI2_DMA_INT_SET_APP1_INT_SET_Msk = 0x100000 + // Bit APP1_INT_SET. + SPI2_DMA_INT_SET_APP1_INT_SET = 0x100000 + + // W0: SPI CPU-controlled buffer0 + // Position of BUF0 field. + SPI2_W0_BUF0_Pos = 0x0 + // Bit mask of BUF0 field. + SPI2_W0_BUF0_Msk = 0xffffffff + + // W1: SPI CPU-controlled buffer1 + // Position of BUF1 field. + SPI2_W1_BUF1_Pos = 0x0 + // Bit mask of BUF1 field. + SPI2_W1_BUF1_Msk = 0xffffffff + + // W2: SPI CPU-controlled buffer2 + // Position of BUF2 field. + SPI2_W2_BUF2_Pos = 0x0 + // Bit mask of BUF2 field. + SPI2_W2_BUF2_Msk = 0xffffffff + + // W3: SPI CPU-controlled buffer3 + // Position of BUF3 field. + SPI2_W3_BUF3_Pos = 0x0 + // Bit mask of BUF3 field. + SPI2_W3_BUF3_Msk = 0xffffffff + + // W4: SPI CPU-controlled buffer4 + // Position of BUF4 field. + SPI2_W4_BUF4_Pos = 0x0 + // Bit mask of BUF4 field. + SPI2_W4_BUF4_Msk = 0xffffffff + + // W5: SPI CPU-controlled buffer5 + // Position of BUF5 field. + SPI2_W5_BUF5_Pos = 0x0 + // Bit mask of BUF5 field. + SPI2_W5_BUF5_Msk = 0xffffffff + + // W6: SPI CPU-controlled buffer6 + // Position of BUF6 field. + SPI2_W6_BUF6_Pos = 0x0 + // Bit mask of BUF6 field. + SPI2_W6_BUF6_Msk = 0xffffffff + + // W7: SPI CPU-controlled buffer7 + // Position of BUF7 field. + SPI2_W7_BUF7_Pos = 0x0 + // Bit mask of BUF7 field. + SPI2_W7_BUF7_Msk = 0xffffffff + + // W8: SPI CPU-controlled buffer8 + // Position of BUF8 field. + SPI2_W8_BUF8_Pos = 0x0 + // Bit mask of BUF8 field. + SPI2_W8_BUF8_Msk = 0xffffffff + + // W9: SPI CPU-controlled buffer9 + // Position of BUF9 field. + SPI2_W9_BUF9_Pos = 0x0 + // Bit mask of BUF9 field. + SPI2_W9_BUF9_Msk = 0xffffffff + + // W10: SPI CPU-controlled buffer10 + // Position of BUF10 field. + SPI2_W10_BUF10_Pos = 0x0 + // Bit mask of BUF10 field. + SPI2_W10_BUF10_Msk = 0xffffffff + + // W11: SPI CPU-controlled buffer11 + // Position of BUF11 field. + SPI2_W11_BUF11_Pos = 0x0 + // Bit mask of BUF11 field. + SPI2_W11_BUF11_Msk = 0xffffffff + + // W12: SPI CPU-controlled buffer12 + // Position of BUF12 field. + SPI2_W12_BUF12_Pos = 0x0 + // Bit mask of BUF12 field. + SPI2_W12_BUF12_Msk = 0xffffffff + + // W13: SPI CPU-controlled buffer13 + // Position of BUF13 field. + SPI2_W13_BUF13_Pos = 0x0 + // Bit mask of BUF13 field. + SPI2_W13_BUF13_Msk = 0xffffffff + + // W14: SPI CPU-controlled buffer14 + // Position of BUF14 field. + SPI2_W14_BUF14_Pos = 0x0 + // Bit mask of BUF14 field. + SPI2_W14_BUF14_Msk = 0xffffffff + + // W15: SPI CPU-controlled buffer15 + // Position of BUF15 field. + SPI2_W15_BUF15_Pos = 0x0 + // Bit mask of BUF15 field. + SPI2_W15_BUF15_Msk = 0xffffffff + + // SLAVE: SPI slave control register + // Position of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Pos = 0x0 + // Bit mask of CLK_MODE field. + SPI2_SLAVE_CLK_MODE_Msk = 0x3 + // Position of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Pos = 0x2 + // Bit mask of CLK_MODE_13 field. + SPI2_SLAVE_CLK_MODE_13_Msk = 0x4 + // Bit CLK_MODE_13. + SPI2_SLAVE_CLK_MODE_13 = 0x4 + // Position of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Pos = 0x3 + // Bit mask of RSCK_DATA_OUT field. + SPI2_SLAVE_RSCK_DATA_OUT_Msk = 0x8 + // Bit RSCK_DATA_OUT. + SPI2_SLAVE_RSCK_DATA_OUT = 0x8 + // Position of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Pos = 0x8 + // Bit mask of SLV_RDDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN_Msk = 0x100 + // Bit SLV_RDDMA_BITLEN_EN. + SPI2_SLAVE_SLV_RDDMA_BITLEN_EN = 0x100 + // Position of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Pos = 0x9 + // Bit mask of SLV_WRDMA_BITLEN_EN field. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN_Msk = 0x200 + // Bit SLV_WRDMA_BITLEN_EN. + SPI2_SLAVE_SLV_WRDMA_BITLEN_EN = 0x200 + // Position of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Pos = 0xa + // Bit mask of SLV_RDBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN_Msk = 0x400 + // Bit SLV_RDBUF_BITLEN_EN. + SPI2_SLAVE_SLV_RDBUF_BITLEN_EN = 0x400 + // Position of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Pos = 0xb + // Bit mask of SLV_WRBUF_BITLEN_EN field. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN_Msk = 0x800 + // Bit SLV_WRBUF_BITLEN_EN. + SPI2_SLAVE_SLV_WRBUF_BITLEN_EN = 0x800 + // Position of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Pos = 0x16 + // Bit mask of DMA_SEG_MAGIC_VALUE field. + SPI2_SLAVE_DMA_SEG_MAGIC_VALUE_Msk = 0x3c00000 + // Position of MODE field. + SPI2_SLAVE_MODE_Pos = 0x1a + // Bit mask of MODE field. + SPI2_SLAVE_MODE_Msk = 0x4000000 + // Bit MODE. + SPI2_SLAVE_MODE = 0x4000000 + // Position of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Pos = 0x1b + // Bit mask of SOFT_RESET field. + SPI2_SLAVE_SOFT_RESET_Msk = 0x8000000 + // Bit SOFT_RESET. + SPI2_SLAVE_SOFT_RESET = 0x8000000 + // Position of USR_CONF field. + SPI2_SLAVE_USR_CONF_Pos = 0x1c + // Bit mask of USR_CONF field. + SPI2_SLAVE_USR_CONF_Msk = 0x10000000 + // Bit USR_CONF. + SPI2_SLAVE_USR_CONF = 0x10000000 + + // SLAVE1: SPI slave control register 1 + // Position of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Pos = 0x0 + // Bit mask of SLV_DATA_BITLEN field. + SPI2_SLAVE1_SLV_DATA_BITLEN_Msk = 0x3ffff + // Position of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Pos = 0x12 + // Bit mask of SLV_LAST_COMMAND field. + SPI2_SLAVE1_SLV_LAST_COMMAND_Msk = 0x3fc0000 + // Position of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Pos = 0x1a + // Bit mask of SLV_LAST_ADDR field. + SPI2_SLAVE1_SLV_LAST_ADDR_Msk = 0xfc000000 + + // CLK_GATE: SPI module clock and register clock control + // Position of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SPI2_CLK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SPI2_CLK_GATE_CLK_EN = 0x1 + // Position of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Pos = 0x1 + // Bit mask of MST_CLK_ACTIVE field. + SPI2_CLK_GATE_MST_CLK_ACTIVE_Msk = 0x2 + // Bit MST_CLK_ACTIVE. + SPI2_CLK_GATE_MST_CLK_ACTIVE = 0x2 + // Position of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Pos = 0x2 + // Bit mask of MST_CLK_SEL field. + SPI2_CLK_GATE_MST_CLK_SEL_Msk = 0x4 + // Bit MST_CLK_SEL. + SPI2_CLK_GATE_MST_CLK_SEL = 0x4 + + // DATE: Version control + // Position of DATE field. + SPI2_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SPI2_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SYSTEM: System Configuration Registers +const ( + // CORE_1_CONTROL_0: Core0 control regiter 0 + // Position of CONTROL_CORE_1_RUNSTALL field. + SYSTEM_CORE_1_CONTROL_0_CONTROL_CORE_1_RUNSTALL_Pos = 0x0 + // Bit mask of CONTROL_CORE_1_RUNSTALL field. + SYSTEM_CORE_1_CONTROL_0_CONTROL_CORE_1_RUNSTALL_Msk = 0x1 + // Bit CONTROL_CORE_1_RUNSTALL. + SYSTEM_CORE_1_CONTROL_0_CONTROL_CORE_1_RUNSTALL = 0x1 + // Position of CONTROL_CORE_1_CLKGATE_EN field. + SYSTEM_CORE_1_CONTROL_0_CONTROL_CORE_1_CLKGATE_EN_Pos = 0x1 + // Bit mask of CONTROL_CORE_1_CLKGATE_EN field. + SYSTEM_CORE_1_CONTROL_0_CONTROL_CORE_1_CLKGATE_EN_Msk = 0x2 + // Bit CONTROL_CORE_1_CLKGATE_EN. + SYSTEM_CORE_1_CONTROL_0_CONTROL_CORE_1_CLKGATE_EN = 0x2 + // Position of CONTROL_CORE_1_RESETING field. + SYSTEM_CORE_1_CONTROL_0_CONTROL_CORE_1_RESETING_Pos = 0x2 + // Bit mask of CONTROL_CORE_1_RESETING field. + SYSTEM_CORE_1_CONTROL_0_CONTROL_CORE_1_RESETING_Msk = 0x4 + // Bit CONTROL_CORE_1_RESETING. + SYSTEM_CORE_1_CONTROL_0_CONTROL_CORE_1_RESETING = 0x4 + + // CORE_1_CONTROL_1: Core0 control regiter 1 + // Position of CONTROL_CORE_1_MESSAGE field. + SYSTEM_CORE_1_CONTROL_1_CONTROL_CORE_1_MESSAGE_Pos = 0x0 + // Bit mask of CONTROL_CORE_1_MESSAGE field. + SYSTEM_CORE_1_CONTROL_1_CONTROL_CORE_1_MESSAGE_Msk = 0xffffffff + + // CPU_PERI_CLK_EN: cpu_peripheral clock configuration register + // Position of CLK_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG_Pos = 0x6 + // Bit mask of CLK_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG_Msk = 0x40 + // Bit CLK_EN_ASSIST_DEBUG. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_ASSIST_DEBUG = 0x40 + // Position of CLK_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO_Pos = 0x7 + // Bit mask of CLK_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO_Msk = 0x80 + // Bit CLK_EN_DEDICATED_GPIO. + SYSTEM_CPU_PERI_CLK_EN_CLK_EN_DEDICATED_GPIO = 0x80 + + // CPU_PERI_RST_EN: cpu_peripheral reset configuration regsiter + // Position of RST_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG_Pos = 0x6 + // Bit mask of RST_EN_ASSIST_DEBUG field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG_Msk = 0x40 + // Bit RST_EN_ASSIST_DEBUG. + SYSTEM_CPU_PERI_RST_EN_RST_EN_ASSIST_DEBUG = 0x40 + // Position of RST_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO_Pos = 0x7 + // Bit mask of RST_EN_DEDICATED_GPIO field. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO_Msk = 0x80 + // Bit RST_EN_DEDICATED_GPIO. + SYSTEM_CPU_PERI_RST_EN_RST_EN_DEDICATED_GPIO = 0x80 + + // CPU_PER_CONF: cpu peripheral clock configuration register + // Position of CPUPERIOD_SEL field. + SYSTEM_CPU_PER_CONF_CPUPERIOD_SEL_Pos = 0x0 + // Bit mask of CPUPERIOD_SEL field. + SYSTEM_CPU_PER_CONF_CPUPERIOD_SEL_Msk = 0x3 + // Position of PLL_FREQ_SEL field. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL_Pos = 0x2 + // Bit mask of PLL_FREQ_SEL field. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL_Msk = 0x4 + // Bit PLL_FREQ_SEL. + SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL = 0x4 + // Position of CPU_WAIT_MODE_FORCE_ON field. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON_Pos = 0x3 + // Bit mask of CPU_WAIT_MODE_FORCE_ON field. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON_Msk = 0x8 + // Bit CPU_WAIT_MODE_FORCE_ON. + SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON = 0x8 + // Position of CPU_WAITI_DELAY_NUM field. + SYSTEM_CPU_PER_CONF_CPU_WAITI_DELAY_NUM_Pos = 0x4 + // Bit mask of CPU_WAITI_DELAY_NUM field. + SYSTEM_CPU_PER_CONF_CPU_WAITI_DELAY_NUM_Msk = 0xf0 + + // MEM_PD_MASK: memory power down mask configuration register + // Position of LSLP_MEM_PD_MASK field. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK_Pos = 0x0 + // Bit mask of LSLP_MEM_PD_MASK field. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK_Msk = 0x1 + // Bit LSLP_MEM_PD_MASK. + SYSTEM_MEM_PD_MASK_LSLP_MEM_PD_MASK = 0x1 + + // PERIP_CLK_EN0: peripheral clock configuration regsiter 0 + // Position of TIMERS_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERS_CLK_EN_Pos = 0x0 + // Bit mask of TIMERS_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERS_CLK_EN_Msk = 0x1 + // Bit TIMERS_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERS_CLK_EN = 0x1 + // Position of SPI01_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN_Pos = 0x1 + // Bit mask of SPI01_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN_Msk = 0x2 + // Bit SPI01_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI01_CLK_EN = 0x2 + // Position of UART_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN_Pos = 0x2 + // Bit mask of UART_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN_Msk = 0x4 + // Bit UART_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART_CLK_EN = 0x4 + // Position of WDG_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_WDG_CLK_EN_Pos = 0x3 + // Bit mask of WDG_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_WDG_CLK_EN_Msk = 0x8 + // Bit WDG_CLK_EN. + SYSTEM_PERIP_CLK_EN0_WDG_CLK_EN = 0x8 + // Position of I2S0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S0_CLK_EN_Pos = 0x4 + // Bit mask of I2S0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S0_CLK_EN_Msk = 0x10 + // Bit I2S0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2S0_CLK_EN = 0x10 + // Position of UART1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN_Pos = 0x5 + // Bit mask of UART1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN_Msk = 0x20 + // Bit UART1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN = 0x20 + // Position of SPI2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN_Pos = 0x6 + // Bit mask of SPI2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN_Msk = 0x40 + // Bit SPI2_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI2_CLK_EN = 0x40 + // Position of I2C_EXT0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN_Pos = 0x7 + // Bit mask of I2C_EXT0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN_Msk = 0x80 + // Bit I2C_EXT0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2C_EXT0_CLK_EN = 0x80 + // Position of UHCI0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI0_CLK_EN_Pos = 0x8 + // Bit mask of UHCI0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI0_CLK_EN_Msk = 0x100 + // Bit UHCI0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UHCI0_CLK_EN = 0x100 + // Position of RMT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_RMT_CLK_EN_Pos = 0x9 + // Bit mask of RMT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_RMT_CLK_EN_Msk = 0x200 + // Bit RMT_CLK_EN. + SYSTEM_PERIP_CLK_EN0_RMT_CLK_EN = 0x200 + // Position of PCNT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PCNT_CLK_EN_Pos = 0xa + // Bit mask of PCNT_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PCNT_CLK_EN_Msk = 0x400 + // Bit PCNT_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PCNT_CLK_EN = 0x400 + // Position of LEDC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN_Pos = 0xb + // Bit mask of LEDC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN_Msk = 0x800 + // Bit LEDC_CLK_EN. + SYSTEM_PERIP_CLK_EN0_LEDC_CLK_EN = 0x800 + // Position of UHCI1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI1_CLK_EN_Pos = 0xc + // Bit mask of UHCI1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UHCI1_CLK_EN_Msk = 0x1000 + // Bit UHCI1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UHCI1_CLK_EN = 0x1000 + // Position of TIMERGROUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN_Pos = 0xd + // Bit mask of TIMERGROUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN_Msk = 0x2000 + // Bit TIMERGROUP_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP_CLK_EN = 0x2000 + // Position of EFUSE_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_EFUSE_CLK_EN_Pos = 0xe + // Bit mask of EFUSE_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_EFUSE_CLK_EN_Msk = 0x4000 + // Bit EFUSE_CLK_EN. + SYSTEM_PERIP_CLK_EN0_EFUSE_CLK_EN = 0x4000 + // Position of TIMERGROUP1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP1_CLK_EN_Pos = 0xf + // Bit mask of TIMERGROUP1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP1_CLK_EN_Msk = 0x8000 + // Bit TIMERGROUP1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TIMERGROUP1_CLK_EN = 0x8000 + // Position of SPI3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_CLK_EN_Pos = 0x10 + // Bit mask of SPI3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_CLK_EN_Msk = 0x10000 + // Bit SPI3_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI3_CLK_EN = 0x10000 + // Position of PWM0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM0_CLK_EN_Pos = 0x11 + // Bit mask of PWM0_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM0_CLK_EN_Msk = 0x20000 + // Bit PWM0_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM0_CLK_EN = 0x20000 + // Position of I2C_EXT1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT1_CLK_EN_Pos = 0x12 + // Bit mask of I2C_EXT1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2C_EXT1_CLK_EN_Msk = 0x40000 + // Bit I2C_EXT1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2C_EXT1_CLK_EN = 0x40000 + // Position of TWAI_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TWAI_CLK_EN_Pos = 0x13 + // Bit mask of TWAI_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_TWAI_CLK_EN_Msk = 0x80000 + // Bit TWAI_CLK_EN. + SYSTEM_PERIP_CLK_EN0_TWAI_CLK_EN = 0x80000 + // Position of PWM1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM1_CLK_EN_Pos = 0x14 + // Bit mask of PWM1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM1_CLK_EN_Msk = 0x100000 + // Bit PWM1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM1_CLK_EN = 0x100000 + // Position of I2S1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S1_CLK_EN_Pos = 0x15 + // Bit mask of I2S1_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_I2S1_CLK_EN_Msk = 0x200000 + // Bit I2S1_CLK_EN. + SYSTEM_PERIP_CLK_EN0_I2S1_CLK_EN = 0x200000 + // Position of SPI2_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_DMA_CLK_EN_Pos = 0x16 + // Bit mask of SPI2_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI2_DMA_CLK_EN_Msk = 0x400000 + // Bit SPI2_DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI2_DMA_CLK_EN = 0x400000 + // Position of USB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_USB_CLK_EN_Pos = 0x17 + // Bit mask of USB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_USB_CLK_EN_Msk = 0x800000 + // Bit USB_CLK_EN. + SYSTEM_PERIP_CLK_EN0_USB_CLK_EN = 0x800000 + // Position of UART_MEM_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN_Pos = 0x18 + // Bit mask of UART_MEM_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN_Msk = 0x1000000 + // Bit UART_MEM_CLK_EN. + SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN = 0x1000000 + // Position of PWM2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM2_CLK_EN_Pos = 0x19 + // Bit mask of PWM2_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM2_CLK_EN_Msk = 0x2000000 + // Bit PWM2_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM2_CLK_EN = 0x2000000 + // Position of PWM3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM3_CLK_EN_Pos = 0x1a + // Bit mask of PWM3_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_PWM3_CLK_EN_Msk = 0x4000000 + // Bit PWM3_CLK_EN. + SYSTEM_PERIP_CLK_EN0_PWM3_CLK_EN = 0x4000000 + // Position of SPI3_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_DMA_CLK_EN_Pos = 0x1b + // Bit mask of SPI3_DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI3_DMA_CLK_EN_Msk = 0x8000000 + // Bit SPI3_DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI3_DMA_CLK_EN = 0x8000000 + // Position of APB_SARADC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN_Pos = 0x1c + // Bit mask of APB_SARADC_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN_Msk = 0x10000000 + // Bit APB_SARADC_CLK_EN. + SYSTEM_PERIP_CLK_EN0_APB_SARADC_CLK_EN = 0x10000000 + // Position of SYSTIMER_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN_Pos = 0x1d + // Bit mask of SYSTIMER_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN_Msk = 0x20000000 + // Bit SYSTIMER_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SYSTIMER_CLK_EN = 0x20000000 + // Position of ADC2_ARB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN_Pos = 0x1e + // Bit mask of ADC2_ARB_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN_Msk = 0x40000000 + // Bit ADC2_ARB_CLK_EN. + SYSTEM_PERIP_CLK_EN0_ADC2_ARB_CLK_EN = 0x40000000 + // Position of SPI4_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI4_CLK_EN_Pos = 0x1f + // Bit mask of SPI4_CLK_EN field. + SYSTEM_PERIP_CLK_EN0_SPI4_CLK_EN_Msk = 0x80000000 + // Bit SPI4_CLK_EN. + SYSTEM_PERIP_CLK_EN0_SPI4_CLK_EN = 0x80000000 + + // PERIP_CLK_EN1: peripheral clock configuration regsiter 1 + // Position of PERI_BACKUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_PERI_BACKUP_CLK_EN_Pos = 0x0 + // Bit mask of PERI_BACKUP_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_PERI_BACKUP_CLK_EN_Msk = 0x1 + // Bit PERI_BACKUP_CLK_EN. + SYSTEM_PERIP_CLK_EN1_PERI_BACKUP_CLK_EN = 0x1 + // Position of CRYPTO_AES_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_AES_CLK_EN_Pos = 0x1 + // Bit mask of CRYPTO_AES_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_AES_CLK_EN_Msk = 0x2 + // Bit CRYPTO_AES_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_AES_CLK_EN = 0x2 + // Position of CRYPTO_SHA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN_Pos = 0x2 + // Bit mask of CRYPTO_SHA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN_Msk = 0x4 + // Bit CRYPTO_SHA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_SHA_CLK_EN = 0x4 + // Position of CRYPTO_RSA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_RSA_CLK_EN_Pos = 0x3 + // Bit mask of CRYPTO_RSA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_RSA_CLK_EN_Msk = 0x8 + // Bit CRYPTO_RSA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_RSA_CLK_EN = 0x8 + // Position of CRYPTO_DS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DS_CLK_EN_Pos = 0x4 + // Bit mask of CRYPTO_DS_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DS_CLK_EN_Msk = 0x10 + // Bit CRYPTO_DS_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_DS_CLK_EN = 0x10 + // Position of CRYPTO_HMAC_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN_Pos = 0x5 + // Bit mask of CRYPTO_HMAC_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN_Msk = 0x20 + // Bit CRYPTO_HMAC_CLK_EN. + SYSTEM_PERIP_CLK_EN1_CRYPTO_HMAC_CLK_EN = 0x20 + // Position of DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_DMA_CLK_EN_Pos = 0x6 + // Bit mask of DMA_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_DMA_CLK_EN_Msk = 0x40 + // Bit DMA_CLK_EN. + SYSTEM_PERIP_CLK_EN1_DMA_CLK_EN = 0x40 + // Position of SDIO_HOST_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_SDIO_HOST_CLK_EN_Pos = 0x7 + // Bit mask of SDIO_HOST_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_SDIO_HOST_CLK_EN_Msk = 0x80 + // Bit SDIO_HOST_CLK_EN. + SYSTEM_PERIP_CLK_EN1_SDIO_HOST_CLK_EN = 0x80 + // Position of LCD_CAM_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_LCD_CAM_CLK_EN_Pos = 0x8 + // Bit mask of LCD_CAM_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_LCD_CAM_CLK_EN_Msk = 0x100 + // Bit LCD_CAM_CLK_EN. + SYSTEM_PERIP_CLK_EN1_LCD_CAM_CLK_EN = 0x100 + // Position of UART2_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_UART2_CLK_EN_Pos = 0x9 + // Bit mask of UART2_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_UART2_CLK_EN_Msk = 0x200 + // Bit UART2_CLK_EN. + SYSTEM_PERIP_CLK_EN1_UART2_CLK_EN = 0x200 + // Position of USB_DEVICE_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_USB_DEVICE_CLK_EN_Pos = 0xa + // Bit mask of USB_DEVICE_CLK_EN field. + SYSTEM_PERIP_CLK_EN1_USB_DEVICE_CLK_EN_Msk = 0x400 + // Bit USB_DEVICE_CLK_EN. + SYSTEM_PERIP_CLK_EN1_USB_DEVICE_CLK_EN = 0x400 + + // PERIP_RST_EN0: peripheral reset configuration register0 + // Position of TIMERS_RST field. + SYSTEM_PERIP_RST_EN0_TIMERS_RST_Pos = 0x0 + // Bit mask of TIMERS_RST field. + SYSTEM_PERIP_RST_EN0_TIMERS_RST_Msk = 0x1 + // Bit TIMERS_RST. + SYSTEM_PERIP_RST_EN0_TIMERS_RST = 0x1 + // Position of SPI01_RST field. + SYSTEM_PERIP_RST_EN0_SPI01_RST_Pos = 0x1 + // Bit mask of SPI01_RST field. + SYSTEM_PERIP_RST_EN0_SPI01_RST_Msk = 0x2 + // Bit SPI01_RST. + SYSTEM_PERIP_RST_EN0_SPI01_RST = 0x2 + // Position of UART_RST field. + SYSTEM_PERIP_RST_EN0_UART_RST_Pos = 0x2 + // Bit mask of UART_RST field. + SYSTEM_PERIP_RST_EN0_UART_RST_Msk = 0x4 + // Bit UART_RST. + SYSTEM_PERIP_RST_EN0_UART_RST = 0x4 + // Position of WDG_RST field. + SYSTEM_PERIP_RST_EN0_WDG_RST_Pos = 0x3 + // Bit mask of WDG_RST field. + SYSTEM_PERIP_RST_EN0_WDG_RST_Msk = 0x8 + // Bit WDG_RST. + SYSTEM_PERIP_RST_EN0_WDG_RST = 0x8 + // Position of I2S0_RST field. + SYSTEM_PERIP_RST_EN0_I2S0_RST_Pos = 0x4 + // Bit mask of I2S0_RST field. + SYSTEM_PERIP_RST_EN0_I2S0_RST_Msk = 0x10 + // Bit I2S0_RST. + SYSTEM_PERIP_RST_EN0_I2S0_RST = 0x10 + // Position of UART1_RST field. + SYSTEM_PERIP_RST_EN0_UART1_RST_Pos = 0x5 + // Bit mask of UART1_RST field. + SYSTEM_PERIP_RST_EN0_UART1_RST_Msk = 0x20 + // Bit UART1_RST. + SYSTEM_PERIP_RST_EN0_UART1_RST = 0x20 + // Position of SPI2_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_RST_Pos = 0x6 + // Bit mask of SPI2_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_RST_Msk = 0x40 + // Bit SPI2_RST. + SYSTEM_PERIP_RST_EN0_SPI2_RST = 0x40 + // Position of I2C_EXT0_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST_Pos = 0x7 + // Bit mask of I2C_EXT0_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST_Msk = 0x80 + // Bit I2C_EXT0_RST. + SYSTEM_PERIP_RST_EN0_I2C_EXT0_RST = 0x80 + // Position of UHCI0_RST field. + SYSTEM_PERIP_RST_EN0_UHCI0_RST_Pos = 0x8 + // Bit mask of UHCI0_RST field. + SYSTEM_PERIP_RST_EN0_UHCI0_RST_Msk = 0x100 + // Bit UHCI0_RST. + SYSTEM_PERIP_RST_EN0_UHCI0_RST = 0x100 + // Position of RMT_RST field. + SYSTEM_PERIP_RST_EN0_RMT_RST_Pos = 0x9 + // Bit mask of RMT_RST field. + SYSTEM_PERIP_RST_EN0_RMT_RST_Msk = 0x200 + // Bit RMT_RST. + SYSTEM_PERIP_RST_EN0_RMT_RST = 0x200 + // Position of PCNT_RST field. + SYSTEM_PERIP_RST_EN0_PCNT_RST_Pos = 0xa + // Bit mask of PCNT_RST field. + SYSTEM_PERIP_RST_EN0_PCNT_RST_Msk = 0x400 + // Bit PCNT_RST. + SYSTEM_PERIP_RST_EN0_PCNT_RST = 0x400 + // Position of LEDC_RST field. + SYSTEM_PERIP_RST_EN0_LEDC_RST_Pos = 0xb + // Bit mask of LEDC_RST field. + SYSTEM_PERIP_RST_EN0_LEDC_RST_Msk = 0x800 + // Bit LEDC_RST. + SYSTEM_PERIP_RST_EN0_LEDC_RST = 0x800 + // Position of UHCI1_RST field. + SYSTEM_PERIP_RST_EN0_UHCI1_RST_Pos = 0xc + // Bit mask of UHCI1_RST field. + SYSTEM_PERIP_RST_EN0_UHCI1_RST_Msk = 0x1000 + // Bit UHCI1_RST. + SYSTEM_PERIP_RST_EN0_UHCI1_RST = 0x1000 + // Position of TIMERGROUP_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST_Pos = 0xd + // Bit mask of TIMERGROUP_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST_Msk = 0x2000 + // Bit TIMERGROUP_RST. + SYSTEM_PERIP_RST_EN0_TIMERGROUP_RST = 0x2000 + // Position of EFUSE_RST field. + SYSTEM_PERIP_RST_EN0_EFUSE_RST_Pos = 0xe + // Bit mask of EFUSE_RST field. + SYSTEM_PERIP_RST_EN0_EFUSE_RST_Msk = 0x4000 + // Bit EFUSE_RST. + SYSTEM_PERIP_RST_EN0_EFUSE_RST = 0x4000 + // Position of TIMERGROUP1_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP1_RST_Pos = 0xf + // Bit mask of TIMERGROUP1_RST field. + SYSTEM_PERIP_RST_EN0_TIMERGROUP1_RST_Msk = 0x8000 + // Bit TIMERGROUP1_RST. + SYSTEM_PERIP_RST_EN0_TIMERGROUP1_RST = 0x8000 + // Position of SPI3_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_RST_Pos = 0x10 + // Bit mask of SPI3_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_RST_Msk = 0x10000 + // Bit SPI3_RST. + SYSTEM_PERIP_RST_EN0_SPI3_RST = 0x10000 + // Position of PWM0_RST field. + SYSTEM_PERIP_RST_EN0_PWM0_RST_Pos = 0x11 + // Bit mask of PWM0_RST field. + SYSTEM_PERIP_RST_EN0_PWM0_RST_Msk = 0x20000 + // Bit PWM0_RST. + SYSTEM_PERIP_RST_EN0_PWM0_RST = 0x20000 + // Position of I2C_EXT1_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT1_RST_Pos = 0x12 + // Bit mask of I2C_EXT1_RST field. + SYSTEM_PERIP_RST_EN0_I2C_EXT1_RST_Msk = 0x40000 + // Bit I2C_EXT1_RST. + SYSTEM_PERIP_RST_EN0_I2C_EXT1_RST = 0x40000 + // Position of TWAI_RST field. + SYSTEM_PERIP_RST_EN0_TWAI_RST_Pos = 0x13 + // Bit mask of TWAI_RST field. + SYSTEM_PERIP_RST_EN0_TWAI_RST_Msk = 0x80000 + // Bit TWAI_RST. + SYSTEM_PERIP_RST_EN0_TWAI_RST = 0x80000 + // Position of PWM1_RST field. + SYSTEM_PERIP_RST_EN0_PWM1_RST_Pos = 0x14 + // Bit mask of PWM1_RST field. + SYSTEM_PERIP_RST_EN0_PWM1_RST_Msk = 0x100000 + // Bit PWM1_RST. + SYSTEM_PERIP_RST_EN0_PWM1_RST = 0x100000 + // Position of I2S1_RST field. + SYSTEM_PERIP_RST_EN0_I2S1_RST_Pos = 0x15 + // Bit mask of I2S1_RST field. + SYSTEM_PERIP_RST_EN0_I2S1_RST_Msk = 0x200000 + // Bit I2S1_RST. + SYSTEM_PERIP_RST_EN0_I2S1_RST = 0x200000 + // Position of SPI2_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_DMA_RST_Pos = 0x16 + // Bit mask of SPI2_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI2_DMA_RST_Msk = 0x400000 + // Bit SPI2_DMA_RST. + SYSTEM_PERIP_RST_EN0_SPI2_DMA_RST = 0x400000 + // Position of USB_RST field. + SYSTEM_PERIP_RST_EN0_USB_RST_Pos = 0x17 + // Bit mask of USB_RST field. + SYSTEM_PERIP_RST_EN0_USB_RST_Msk = 0x800000 + // Bit USB_RST. + SYSTEM_PERIP_RST_EN0_USB_RST = 0x800000 + // Position of UART_MEM_RST field. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST_Pos = 0x18 + // Bit mask of UART_MEM_RST field. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST_Msk = 0x1000000 + // Bit UART_MEM_RST. + SYSTEM_PERIP_RST_EN0_UART_MEM_RST = 0x1000000 + // Position of PWM2_RST field. + SYSTEM_PERIP_RST_EN0_PWM2_RST_Pos = 0x19 + // Bit mask of PWM2_RST field. + SYSTEM_PERIP_RST_EN0_PWM2_RST_Msk = 0x2000000 + // Bit PWM2_RST. + SYSTEM_PERIP_RST_EN0_PWM2_RST = 0x2000000 + // Position of PWM3_RST field. + SYSTEM_PERIP_RST_EN0_PWM3_RST_Pos = 0x1a + // Bit mask of PWM3_RST field. + SYSTEM_PERIP_RST_EN0_PWM3_RST_Msk = 0x4000000 + // Bit PWM3_RST. + SYSTEM_PERIP_RST_EN0_PWM3_RST = 0x4000000 + // Position of SPI3_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_DMA_RST_Pos = 0x1b + // Bit mask of SPI3_DMA_RST field. + SYSTEM_PERIP_RST_EN0_SPI3_DMA_RST_Msk = 0x8000000 + // Bit SPI3_DMA_RST. + SYSTEM_PERIP_RST_EN0_SPI3_DMA_RST = 0x8000000 + // Position of APB_SARADC_RST field. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST_Pos = 0x1c + // Bit mask of APB_SARADC_RST field. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST_Msk = 0x10000000 + // Bit APB_SARADC_RST. + SYSTEM_PERIP_RST_EN0_APB_SARADC_RST = 0x10000000 + // Position of SYSTIMER_RST field. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST_Pos = 0x1d + // Bit mask of SYSTIMER_RST field. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST_Msk = 0x20000000 + // Bit SYSTIMER_RST. + SYSTEM_PERIP_RST_EN0_SYSTIMER_RST = 0x20000000 + // Position of ADC2_ARB_RST field. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST_Pos = 0x1e + // Bit mask of ADC2_ARB_RST field. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST_Msk = 0x40000000 + // Bit ADC2_ARB_RST. + SYSTEM_PERIP_RST_EN0_ADC2_ARB_RST = 0x40000000 + // Position of SPI4_RST field. + SYSTEM_PERIP_RST_EN0_SPI4_RST_Pos = 0x1f + // Bit mask of SPI4_RST field. + SYSTEM_PERIP_RST_EN0_SPI4_RST_Msk = 0x80000000 + // Bit SPI4_RST. + SYSTEM_PERIP_RST_EN0_SPI4_RST = 0x80000000 + + // PERIP_RST_EN1: peripheral reset configuration regsiter 1 + // Position of PERI_BACKUP_RST field. + SYSTEM_PERIP_RST_EN1_PERI_BACKUP_RST_Pos = 0x0 + // Bit mask of PERI_BACKUP_RST field. + SYSTEM_PERIP_RST_EN1_PERI_BACKUP_RST_Msk = 0x1 + // Bit PERI_BACKUP_RST. + SYSTEM_PERIP_RST_EN1_PERI_BACKUP_RST = 0x1 + // Position of CRYPTO_AES_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_AES_RST_Pos = 0x1 + // Bit mask of CRYPTO_AES_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_AES_RST_Msk = 0x2 + // Bit CRYPTO_AES_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_AES_RST = 0x2 + // Position of CRYPTO_SHA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST_Pos = 0x2 + // Bit mask of CRYPTO_SHA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST_Msk = 0x4 + // Bit CRYPTO_SHA_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_SHA_RST = 0x4 + // Position of CRYPTO_RSA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_RSA_RST_Pos = 0x3 + // Bit mask of CRYPTO_RSA_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_RSA_RST_Msk = 0x8 + // Bit CRYPTO_RSA_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_RSA_RST = 0x8 + // Position of CRYPTO_DS_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_DS_RST_Pos = 0x4 + // Bit mask of CRYPTO_DS_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_DS_RST_Msk = 0x10 + // Bit CRYPTO_DS_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_DS_RST = 0x10 + // Position of CRYPTO_HMAC_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_HMAC_RST_Pos = 0x5 + // Bit mask of CRYPTO_HMAC_RST field. + SYSTEM_PERIP_RST_EN1_CRYPTO_HMAC_RST_Msk = 0x20 + // Bit CRYPTO_HMAC_RST. + SYSTEM_PERIP_RST_EN1_CRYPTO_HMAC_RST = 0x20 + // Position of DMA_RST field. + SYSTEM_PERIP_RST_EN1_DMA_RST_Pos = 0x6 + // Bit mask of DMA_RST field. + SYSTEM_PERIP_RST_EN1_DMA_RST_Msk = 0x40 + // Bit DMA_RST. + SYSTEM_PERIP_RST_EN1_DMA_RST = 0x40 + // Position of SDIO_HOST_RST field. + SYSTEM_PERIP_RST_EN1_SDIO_HOST_RST_Pos = 0x7 + // Bit mask of SDIO_HOST_RST field. + SYSTEM_PERIP_RST_EN1_SDIO_HOST_RST_Msk = 0x80 + // Bit SDIO_HOST_RST. + SYSTEM_PERIP_RST_EN1_SDIO_HOST_RST = 0x80 + // Position of LCD_CAM_RST field. + SYSTEM_PERIP_RST_EN1_LCD_CAM_RST_Pos = 0x8 + // Bit mask of LCD_CAM_RST field. + SYSTEM_PERIP_RST_EN1_LCD_CAM_RST_Msk = 0x100 + // Bit LCD_CAM_RST. + SYSTEM_PERIP_RST_EN1_LCD_CAM_RST = 0x100 + // Position of UART2_RST field. + SYSTEM_PERIP_RST_EN1_UART2_RST_Pos = 0x9 + // Bit mask of UART2_RST field. + SYSTEM_PERIP_RST_EN1_UART2_RST_Msk = 0x200 + // Bit UART2_RST. + SYSTEM_PERIP_RST_EN1_UART2_RST = 0x200 + // Position of USB_DEVICE_RST field. + SYSTEM_PERIP_RST_EN1_USB_DEVICE_RST_Pos = 0xa + // Bit mask of USB_DEVICE_RST field. + SYSTEM_PERIP_RST_EN1_USB_DEVICE_RST_Msk = 0x400 + // Bit USB_DEVICE_RST. + SYSTEM_PERIP_RST_EN1_USB_DEVICE_RST = 0x400 + + // BT_LPCK_DIV_INT: low power clock frequent division factor configuration regsiter + // Position of BT_LPCK_DIV_NUM field. + SYSTEM_BT_LPCK_DIV_INT_BT_LPCK_DIV_NUM_Pos = 0x0 + // Bit mask of BT_LPCK_DIV_NUM field. + SYSTEM_BT_LPCK_DIV_INT_BT_LPCK_DIV_NUM_Msk = 0xfff + + // BT_LPCK_DIV_FRAC: low power clock configuration register + // Position of BT_LPCK_DIV_B field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_B_Pos = 0x0 + // Bit mask of BT_LPCK_DIV_B field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_B_Msk = 0xfff + // Position of BT_LPCK_DIV_A field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_A_Pos = 0xc + // Bit mask of BT_LPCK_DIV_A field. + SYSTEM_BT_LPCK_DIV_FRAC_BT_LPCK_DIV_A_Msk = 0xfff000 + // Position of LPCLK_SEL_RTC_SLOW field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Pos = 0x18 + // Bit mask of LPCLK_SEL_RTC_SLOW field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW_Msk = 0x1000000 + // Bit LPCLK_SEL_RTC_SLOW. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_RTC_SLOW = 0x1000000 + // Position of LPCLK_SEL_8M field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Pos = 0x19 + // Bit mask of LPCLK_SEL_8M field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M_Msk = 0x2000000 + // Bit LPCLK_SEL_8M. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_8M = 0x2000000 + // Position of LPCLK_SEL_XTAL field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Pos = 0x1a + // Bit mask of LPCLK_SEL_XTAL field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL_Msk = 0x4000000 + // Bit LPCLK_SEL_XTAL. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL = 0x4000000 + // Position of LPCLK_SEL_XTAL32K field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Pos = 0x1b + // Bit mask of LPCLK_SEL_XTAL32K field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K_Msk = 0x8000000 + // Bit LPCLK_SEL_XTAL32K. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_SEL_XTAL32K = 0x8000000 + // Position of LPCLK_RTC_EN field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN_Pos = 0x1c + // Bit mask of LPCLK_RTC_EN field. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN_Msk = 0x10000000 + // Bit LPCLK_RTC_EN. + SYSTEM_BT_LPCK_DIV_FRAC_LPCLK_RTC_EN = 0x10000000 + + // CPU_INTR_FROM_CPU_0: interrupt source register 0 + // Position of CPU_INTR_FROM_CPU_0 field. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_0 field. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_0. + SYSTEM_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0 = 0x1 + + // CPU_INTR_FROM_CPU_1: interrupt source register 1 + // Position of CPU_INTR_FROM_CPU_1 field. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_1 field. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_1. + SYSTEM_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1 = 0x1 + + // CPU_INTR_FROM_CPU_2: interrupt source register 2 + // Position of CPU_INTR_FROM_CPU_2 field. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_2 field. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_2. + SYSTEM_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2 = 0x1 + + // CPU_INTR_FROM_CPU_3: interrupt source register 3 + // Position of CPU_INTR_FROM_CPU_3 field. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Pos = 0x0 + // Bit mask of CPU_INTR_FROM_CPU_3 field. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Msk = 0x1 + // Bit CPU_INTR_FROM_CPU_3. + SYSTEM_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3 = 0x1 + + // RSA_PD_CTRL: rsa memory power control register + // Position of RSA_MEM_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD_Pos = 0x0 + // Bit mask of RSA_MEM_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD_Msk = 0x1 + // Bit RSA_MEM_PD. + SYSTEM_RSA_PD_CTRL_RSA_MEM_PD = 0x1 + // Position of RSA_MEM_FORCE_PU field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Pos = 0x1 + // Bit mask of RSA_MEM_FORCE_PU field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Msk = 0x2 + // Bit RSA_MEM_FORCE_PU. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PU = 0x2 + // Position of RSA_MEM_FORCE_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Pos = 0x2 + // Bit mask of RSA_MEM_FORCE_PD field. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Msk = 0x4 + // Bit RSA_MEM_FORCE_PD. + SYSTEM_RSA_PD_CTRL_RSA_MEM_FORCE_PD = 0x4 + + // EDMA_CTRL: EDMA control register + // Position of EDMA_CLK_ON field. + SYSTEM_EDMA_CTRL_EDMA_CLK_ON_Pos = 0x0 + // Bit mask of EDMA_CLK_ON field. + SYSTEM_EDMA_CTRL_EDMA_CLK_ON_Msk = 0x1 + // Bit EDMA_CLK_ON. + SYSTEM_EDMA_CTRL_EDMA_CLK_ON = 0x1 + // Position of EDMA_RESET field. + SYSTEM_EDMA_CTRL_EDMA_RESET_Pos = 0x1 + // Bit mask of EDMA_RESET field. + SYSTEM_EDMA_CTRL_EDMA_RESET_Msk = 0x2 + // Bit EDMA_RESET. + SYSTEM_EDMA_CTRL_EDMA_RESET = 0x2 + + // CACHE_CONTROL: Cache control register + // Position of ICACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_ICACHE_CLK_ON_Pos = 0x0 + // Bit mask of ICACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_ICACHE_CLK_ON_Msk = 0x1 + // Bit ICACHE_CLK_ON. + SYSTEM_CACHE_CONTROL_ICACHE_CLK_ON = 0x1 + // Position of ICACHE_RESET field. + SYSTEM_CACHE_CONTROL_ICACHE_RESET_Pos = 0x1 + // Bit mask of ICACHE_RESET field. + SYSTEM_CACHE_CONTROL_ICACHE_RESET_Msk = 0x2 + // Bit ICACHE_RESET. + SYSTEM_CACHE_CONTROL_ICACHE_RESET = 0x2 + // Position of DCACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_DCACHE_CLK_ON_Pos = 0x2 + // Bit mask of DCACHE_CLK_ON field. + SYSTEM_CACHE_CONTROL_DCACHE_CLK_ON_Msk = 0x4 + // Bit DCACHE_CLK_ON. + SYSTEM_CACHE_CONTROL_DCACHE_CLK_ON = 0x4 + // Position of DCACHE_RESET field. + SYSTEM_CACHE_CONTROL_DCACHE_RESET_Pos = 0x3 + // Bit mask of DCACHE_RESET field. + SYSTEM_CACHE_CONTROL_DCACHE_RESET_Msk = 0x8 + // Bit DCACHE_RESET. + SYSTEM_CACHE_CONTROL_DCACHE_RESET = 0x8 + + // EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: External memory encrypt and decrypt control register + // Position of ENABLE_SPI_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Pos = 0x0 + // Bit mask of ENABLE_SPI_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT_Msk = 0x1 + // Bit ENABLE_SPI_MANUAL_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_SPI_MANUAL_ENCRYPT = 0x1 + // Position of ENABLE_DOWNLOAD_DB_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Pos = 0x1 + // Bit mask of ENABLE_DOWNLOAD_DB_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT_Msk = 0x2 + // Bit ENABLE_DOWNLOAD_DB_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_DB_ENCRYPT = 0x2 + // Position of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Pos = 0x2 + // Bit mask of ENABLE_DOWNLOAD_G0CB_DECRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT_Msk = 0x4 + // Bit ENABLE_DOWNLOAD_G0CB_DECRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_G0CB_DECRYPT = 0x4 + // Position of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x3 + // Bit mask of ENABLE_DOWNLOAD_MANUAL_ENCRYPT field. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x8 + // Bit ENABLE_DOWNLOAD_MANUAL_ENCRYPT. + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_ENABLE_DOWNLOAD_MANUAL_ENCRYPT = 0x8 + + // RTC_FASTMEM_CONFIG: RTC fast memory configuration register + // Position of RTC_MEM_CRC_START field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START_Pos = 0x8 + // Bit mask of RTC_MEM_CRC_START field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START_Msk = 0x100 + // Bit RTC_MEM_CRC_START. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_START = 0x100 + // Position of RTC_MEM_CRC_ADDR field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR_Pos = 0x9 + // Bit mask of RTC_MEM_CRC_ADDR field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_ADDR_Msk = 0xffe00 + // Position of RTC_MEM_CRC_LEN field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN_Pos = 0x14 + // Bit mask of RTC_MEM_CRC_LEN field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_LEN_Msk = 0x7ff00000 + // Position of RTC_MEM_CRC_FINISH field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH_Pos = 0x1f + // Bit mask of RTC_MEM_CRC_FINISH field. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH_Msk = 0x80000000 + // Bit RTC_MEM_CRC_FINISH. + SYSTEM_RTC_FASTMEM_CONFIG_RTC_MEM_CRC_FINISH = 0x80000000 + + // RTC_FASTMEM_CRC: RTC fast memory CRC control register + // Position of RTC_MEM_CRC_RES field. + SYSTEM_RTC_FASTMEM_CRC_RTC_MEM_CRC_RES_Pos = 0x0 + // Bit mask of RTC_MEM_CRC_RES field. + SYSTEM_RTC_FASTMEM_CRC_RTC_MEM_CRC_RES_Msk = 0xffffffff + + // REDUNDANT_ECO_CTRL: ******* Description *********** + // Position of REDUNDANT_ECO_DRIVE field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE_Pos = 0x0 + // Bit mask of REDUNDANT_ECO_DRIVE field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE_Msk = 0x1 + // Bit REDUNDANT_ECO_DRIVE. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_DRIVE = 0x1 + // Position of REDUNDANT_ECO_RESULT field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT_Pos = 0x1 + // Bit mask of REDUNDANT_ECO_RESULT field. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT_Msk = 0x2 + // Bit REDUNDANT_ECO_RESULT. + SYSTEM_REDUNDANT_ECO_CTRL_REDUNDANT_ECO_RESULT = 0x2 + + // CLOCK_GATE: ******* Description *********** + // Position of CLK_EN field. + SYSTEM_CLOCK_GATE_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + SYSTEM_CLOCK_GATE_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + SYSTEM_CLOCK_GATE_CLK_EN = 0x1 + + // SYSCLK_CONF: System clock configuration register. + // Position of PRE_DIV_CNT field. + SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_Pos = 0x0 + // Bit mask of PRE_DIV_CNT field. + SYSTEM_SYSCLK_CONF_PRE_DIV_CNT_Msk = 0x3ff + // Position of SOC_CLK_SEL field. + SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_Pos = 0xa + // Bit mask of SOC_CLK_SEL field. + SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_Msk = 0xc00 + // Position of CLK_XTAL_FREQ field. + SYSTEM_SYSCLK_CONF_CLK_XTAL_FREQ_Pos = 0xc + // Bit mask of CLK_XTAL_FREQ field. + SYSTEM_SYSCLK_CONF_CLK_XTAL_FREQ_Msk = 0x7f000 + // Position of CLK_DIV_EN field. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN_Pos = 0x13 + // Bit mask of CLK_DIV_EN field. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN_Msk = 0x80000 + // Bit CLK_DIV_EN. + SYSTEM_SYSCLK_CONF_CLK_DIV_EN = 0x80000 + + // MEM_PVT: ******* Description *********** + // Position of MEM_PATH_LEN field. + SYSTEM_MEM_PVT_MEM_PATH_LEN_Pos = 0x0 + // Bit mask of MEM_PATH_LEN field. + SYSTEM_MEM_PVT_MEM_PATH_LEN_Msk = 0xf + // Position of MEM_ERR_CNT_CLR field. + SYSTEM_MEM_PVT_MEM_ERR_CNT_CLR_Pos = 0x4 + // Bit mask of MEM_ERR_CNT_CLR field. + SYSTEM_MEM_PVT_MEM_ERR_CNT_CLR_Msk = 0x10 + // Bit MEM_ERR_CNT_CLR. + SYSTEM_MEM_PVT_MEM_ERR_CNT_CLR = 0x10 + // Position of MONITOR_EN field. + SYSTEM_MEM_PVT_MONITOR_EN_Pos = 0x5 + // Bit mask of MONITOR_EN field. + SYSTEM_MEM_PVT_MONITOR_EN_Msk = 0x20 + // Bit MONITOR_EN. + SYSTEM_MEM_PVT_MONITOR_EN = 0x20 + // Position of MEM_TIMING_ERR_CNT field. + SYSTEM_MEM_PVT_MEM_TIMING_ERR_CNT_Pos = 0x6 + // Bit mask of MEM_TIMING_ERR_CNT field. + SYSTEM_MEM_PVT_MEM_TIMING_ERR_CNT_Msk = 0x3fffc0 + // Position of MEM_VT_SEL field. + SYSTEM_MEM_PVT_MEM_VT_SEL_Pos = 0x16 + // Bit mask of MEM_VT_SEL field. + SYSTEM_MEM_PVT_MEM_VT_SEL_Msk = 0xc00000 + + // COMB_PVT_LVT_CONF: ******* Description *********** + // Position of COMB_PATH_LEN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT_Pos = 0x0 + // Bit mask of COMB_PATH_LEN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PATH_LEN_LVT_Msk = 0x1f + // Position of COMB_ERR_CNT_CLR_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT_Pos = 0x5 + // Bit mask of COMB_ERR_CNT_CLR_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT_Msk = 0x20 + // Bit COMB_ERR_CNT_CLR_LVT. + SYSTEM_COMB_PVT_LVT_CONF_COMB_ERR_CNT_CLR_LVT = 0x20 + // Position of COMB_PVT_MONITOR_EN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT_Pos = 0x6 + // Bit mask of COMB_PVT_MONITOR_EN_LVT field. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT_Msk = 0x40 + // Bit COMB_PVT_MONITOR_EN_LVT. + SYSTEM_COMB_PVT_LVT_CONF_COMB_PVT_MONITOR_EN_LVT = 0x40 + + // COMB_PVT_NVT_CONF: ******* Description *********** + // Position of COMB_PATH_LEN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT_Pos = 0x0 + // Bit mask of COMB_PATH_LEN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PATH_LEN_NVT_Msk = 0x1f + // Position of COMB_ERR_CNT_CLR_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT_Pos = 0x5 + // Bit mask of COMB_ERR_CNT_CLR_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT_Msk = 0x20 + // Bit COMB_ERR_CNT_CLR_NVT. + SYSTEM_COMB_PVT_NVT_CONF_COMB_ERR_CNT_CLR_NVT = 0x20 + // Position of COMB_PVT_MONITOR_EN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT_Pos = 0x6 + // Bit mask of COMB_PVT_MONITOR_EN_NVT field. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT_Msk = 0x40 + // Bit COMB_PVT_MONITOR_EN_NVT. + SYSTEM_COMB_PVT_NVT_CONF_COMB_PVT_MONITOR_EN_NVT = 0x40 + + // COMB_PVT_HVT_CONF: ******* Description *********** + // Position of COMB_PATH_LEN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT_Pos = 0x0 + // Bit mask of COMB_PATH_LEN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PATH_LEN_HVT_Msk = 0x1f + // Position of COMB_ERR_CNT_CLR_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT_Pos = 0x5 + // Bit mask of COMB_ERR_CNT_CLR_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT_Msk = 0x20 + // Bit COMB_ERR_CNT_CLR_HVT. + SYSTEM_COMB_PVT_HVT_CONF_COMB_ERR_CNT_CLR_HVT = 0x20 + // Position of COMB_PVT_MONITOR_EN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT_Pos = 0x6 + // Bit mask of COMB_PVT_MONITOR_EN_HVT field. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT_Msk = 0x40 + // Bit COMB_PVT_MONITOR_EN_HVT. + SYSTEM_COMB_PVT_HVT_CONF_COMB_PVT_MONITOR_EN_HVT = 0x40 + + // COMB_PVT_ERR_LVT_SITE0: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_LVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE0_COMB_TIMING_ERR_CNT_LVT_SITE0_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE0: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_NVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE0_COMB_TIMING_ERR_CNT_NVT_SITE0_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE0: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_HVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE0 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE0_COMB_TIMING_ERR_CNT_HVT_SITE0_Msk = 0xffff + + // COMB_PVT_ERR_LVT_SITE1: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_LVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE1_COMB_TIMING_ERR_CNT_LVT_SITE1_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE1: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_NVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE1_COMB_TIMING_ERR_CNT_NVT_SITE1_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE1: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_HVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE1 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE1_COMB_TIMING_ERR_CNT_HVT_SITE1_Msk = 0xffff + + // COMB_PVT_ERR_LVT_SITE2: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_LVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE2_COMB_TIMING_ERR_CNT_LVT_SITE2_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE2: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_NVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE2_COMB_TIMING_ERR_CNT_NVT_SITE2_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE2: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_HVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE2 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE2_COMB_TIMING_ERR_CNT_HVT_SITE2_Msk = 0xffff + + // COMB_PVT_ERR_LVT_SITE3: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_LVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_LVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_LVT_SITE3_COMB_TIMING_ERR_CNT_LVT_SITE3_Msk = 0xffff + + // COMB_PVT_ERR_NVT_SITE3: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_NVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_NVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_NVT_SITE3_COMB_TIMING_ERR_CNT_NVT_SITE3_Msk = 0xffff + + // COMB_PVT_ERR_HVT_SITE3: ******* Description *********** + // Position of COMB_TIMING_ERR_CNT_HVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3_Pos = 0x0 + // Bit mask of COMB_TIMING_ERR_CNT_HVT_SITE3 field. + SYSTEM_COMB_PVT_ERR_HVT_SITE3_COMB_TIMING_ERR_CNT_HVT_SITE3_Msk = 0xffff + + // DATE: version register + // Position of DATE field. + SYSTEM_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SYSTEM_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SYSTIMER: System Timer +const ( + // CONF: Configure system timer clock + // Position of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Pos = 0x0 + // Bit mask of SYSTIMER_CLK_FO field. + SYSTIMER_CONF_SYSTIMER_CLK_FO_Msk = 0x1 + // Bit SYSTIMER_CLK_FO. + SYSTIMER_CONF_SYSTIMER_CLK_FO = 0x1 + // Position of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Pos = 0x16 + // Bit mask of TARGET2_WORK_EN field. + SYSTIMER_CONF_TARGET2_WORK_EN_Msk = 0x400000 + // Bit TARGET2_WORK_EN. + SYSTIMER_CONF_TARGET2_WORK_EN = 0x400000 + // Position of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Pos = 0x17 + // Bit mask of TARGET1_WORK_EN field. + SYSTIMER_CONF_TARGET1_WORK_EN_Msk = 0x800000 + // Bit TARGET1_WORK_EN. + SYSTIMER_CONF_TARGET1_WORK_EN = 0x800000 + // Position of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Pos = 0x18 + // Bit mask of TARGET0_WORK_EN field. + SYSTIMER_CONF_TARGET0_WORK_EN_Msk = 0x1000000 + // Bit TARGET0_WORK_EN. + SYSTIMER_CONF_TARGET0_WORK_EN = 0x1000000 + // Position of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Pos = 0x19 + // Bit mask of TIMER_UNIT1_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Msk = 0x2000000 + // Bit TIMER_UNIT1_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN = 0x2000000 + // Position of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Pos = 0x1a + // Bit mask of TIMER_UNIT1_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Msk = 0x4000000 + // Bit TIMER_UNIT1_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN = 0x4000000 + // Position of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Pos = 0x1b + // Bit mask of TIMER_UNIT0_CORE1_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Msk = 0x8000000 + // Bit TIMER_UNIT0_CORE1_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN = 0x8000000 + // Position of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Pos = 0x1c + // Bit mask of TIMER_UNIT0_CORE0_STALL_EN field. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Msk = 0x10000000 + // Bit TIMER_UNIT0_CORE0_STALL_EN. + SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN = 0x10000000 + // Position of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Pos = 0x1d + // Bit mask of TIMER_UNIT1_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Msk = 0x20000000 + // Bit TIMER_UNIT1_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT1_WORK_EN = 0x20000000 + // Position of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Pos = 0x1e + // Bit mask of TIMER_UNIT0_WORK_EN field. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Msk = 0x40000000 + // Bit TIMER_UNIT0_WORK_EN. + SYSTIMER_CONF_TIMER_UNIT0_WORK_EN = 0x40000000 + // Position of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + SYSTIMER_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + SYSTIMER_CONF_CLK_EN = 0x80000000 + + // UNIT0_OP: system timer unit0 value update register + // Position of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT0_VALUE_VALID field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT0_VALUE_VALID. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT0_UPDATE field. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT0_UPDATE. + SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE = 0x40000000 + + // UNIT1_OP: system timer unit1 value update register + // Position of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Pos = 0x1d + // Bit mask of TIMER_UNIT1_VALUE_VALID field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Msk = 0x20000000 + // Bit TIMER_UNIT1_VALUE_VALID. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID = 0x20000000 + // Position of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Pos = 0x1e + // Bit mask of TIMER_UNIT1_UPDATE field. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Msk = 0x40000000 + // Bit TIMER_UNIT1_UPDATE. + SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE = 0x40000000 + + // UNIT0_LOAD_HI: system timer unit0 value high load register + // Position of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_HI field. + SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Msk = 0xfffff + + // UNIT0_LOAD_LO: system timer unit0 value low load register + // Position of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD_LO field. + SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Msk = 0xffffffff + + // UNIT1_LOAD_HI: system timer unit1 value high load register + // Position of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_HI field. + SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Msk = 0xfffff + + // UNIT1_LOAD_LO: system timer unit1 value low load register + // Position of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD_LO field. + SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Msk = 0xffffffff + + // TARGET0_HI: system timer comp0 value high register + // Position of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET0_HI field. + SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Msk = 0xfffff + + // TARGET0_LO: system timer comp0 value low register + // Position of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET0_LO field. + SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Msk = 0xffffffff + + // TARGET1_HI: system timer comp1 value high register + // Position of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET1_HI field. + SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Msk = 0xfffff + + // TARGET1_LO: system timer comp1 value low register + // Position of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET1_LO field. + SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Msk = 0xffffffff + + // TARGET2_HI: system timer comp2 value high register + // Position of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Pos = 0x0 + // Bit mask of TIMER_TARGET2_HI field. + SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Msk = 0xfffff + + // TARGET2_LO: system timer comp2 value low register + // Position of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Pos = 0x0 + // Bit mask of TIMER_TARGET2_LO field. + SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Msk = 0xffffffff + + // TARGET0_CONF: system timer comp0 target mode register + // Position of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Pos = 0x0 + // Bit mask of TARGET0_PERIOD field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Msk = 0x3ffffff + // Position of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET0_PERIOD_MODE field. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET0_PERIOD_MODE. + SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE = 0x40000000 + // Position of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET0_TIMER_UNIT_SEL field. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET0_TIMER_UNIT_SEL. + SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL = 0x80000000 + + // TARGET1_CONF: system timer comp1 target mode register + // Position of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Pos = 0x0 + // Bit mask of TARGET1_PERIOD field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Msk = 0x3ffffff + // Position of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET1_PERIOD_MODE field. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET1_PERIOD_MODE. + SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE = 0x40000000 + // Position of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET1_TIMER_UNIT_SEL field. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET1_TIMER_UNIT_SEL. + SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL = 0x80000000 + + // TARGET2_CONF: system timer comp2 target mode register + // Position of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Pos = 0x0 + // Bit mask of TARGET2_PERIOD field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Msk = 0x3ffffff + // Position of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Pos = 0x1e + // Bit mask of TARGET2_PERIOD_MODE field. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Msk = 0x40000000 + // Bit TARGET2_PERIOD_MODE. + SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE = 0x40000000 + // Position of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Pos = 0x1f + // Bit mask of TARGET2_TIMER_UNIT_SEL field. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Msk = 0x80000000 + // Bit TARGET2_TIMER_UNIT_SEL. + SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL = 0x80000000 + + // UNIT0_VALUE_HI: system timer unit0 value high register + // Position of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_HI field. + SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Msk = 0xfffff + + // UNIT0_VALUE_LO: system timer unit0 value low register + // Position of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT0_VALUE_LO field. + SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Msk = 0xffffffff + + // UNIT1_VALUE_HI: system timer unit1 value high register + // Position of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_HI field. + SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Msk = 0xfffff + + // UNIT1_VALUE_LO: system timer unit1 value low register + // Position of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Pos = 0x0 + // Bit mask of TIMER_UNIT1_VALUE_LO field. + SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Msk = 0xffffffff + + // COMP0_LOAD: system timer comp0 conf sync register + // Position of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP0_LOAD field. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Msk = 0x1 + // Bit TIMER_COMP0_LOAD. + SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD = 0x1 + + // COMP1_LOAD: system timer comp1 conf sync register + // Position of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP1_LOAD field. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Msk = 0x1 + // Bit TIMER_COMP1_LOAD. + SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD = 0x1 + + // COMP2_LOAD: system timer comp2 conf sync register + // Position of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Pos = 0x0 + // Bit mask of TIMER_COMP2_LOAD field. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Msk = 0x1 + // Bit TIMER_COMP2_LOAD. + SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD = 0x1 + + // UNIT0_LOAD: system timer unit0 conf sync register + // Position of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT0_LOAD field. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Msk = 0x1 + // Bit TIMER_UNIT0_LOAD. + SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD = 0x1 + + // UNIT1_LOAD: system timer unit1 conf sync register + // Position of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Pos = 0x0 + // Bit mask of TIMER_UNIT1_LOAD field. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Msk = 0x1 + // Bit TIMER_UNIT1_LOAD. + SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD = 0x1 + + // INT_ENA: systimer interrupt enable register + // Position of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Pos = 0x0 + // Bit mask of TARGET0_INT_ENA field. + SYSTIMER_INT_ENA_TARGET0_INT_ENA_Msk = 0x1 + // Bit TARGET0_INT_ENA. + SYSTIMER_INT_ENA_TARGET0_INT_ENA = 0x1 + // Position of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Pos = 0x1 + // Bit mask of TARGET1_INT_ENA field. + SYSTIMER_INT_ENA_TARGET1_INT_ENA_Msk = 0x2 + // Bit TARGET1_INT_ENA. + SYSTIMER_INT_ENA_TARGET1_INT_ENA = 0x2 + // Position of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Pos = 0x2 + // Bit mask of TARGET2_INT_ENA field. + SYSTIMER_INT_ENA_TARGET2_INT_ENA_Msk = 0x4 + // Bit TARGET2_INT_ENA. + SYSTIMER_INT_ENA_TARGET2_INT_ENA = 0x4 + + // INT_RAW: systimer interrupt raw register + // Position of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Pos = 0x0 + // Bit mask of TARGET0_INT_RAW field. + SYSTIMER_INT_RAW_TARGET0_INT_RAW_Msk = 0x1 + // Bit TARGET0_INT_RAW. + SYSTIMER_INT_RAW_TARGET0_INT_RAW = 0x1 + // Position of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Pos = 0x1 + // Bit mask of TARGET1_INT_RAW field. + SYSTIMER_INT_RAW_TARGET1_INT_RAW_Msk = 0x2 + // Bit TARGET1_INT_RAW. + SYSTIMER_INT_RAW_TARGET1_INT_RAW = 0x2 + // Position of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Pos = 0x2 + // Bit mask of TARGET2_INT_RAW field. + SYSTIMER_INT_RAW_TARGET2_INT_RAW_Msk = 0x4 + // Bit TARGET2_INT_RAW. + SYSTIMER_INT_RAW_TARGET2_INT_RAW = 0x4 + + // INT_CLR: systimer interrupt clear register + // Position of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Pos = 0x0 + // Bit mask of TARGET0_INT_CLR field. + SYSTIMER_INT_CLR_TARGET0_INT_CLR_Msk = 0x1 + // Bit TARGET0_INT_CLR. + SYSTIMER_INT_CLR_TARGET0_INT_CLR = 0x1 + // Position of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Pos = 0x1 + // Bit mask of TARGET1_INT_CLR field. + SYSTIMER_INT_CLR_TARGET1_INT_CLR_Msk = 0x2 + // Bit TARGET1_INT_CLR. + SYSTIMER_INT_CLR_TARGET1_INT_CLR = 0x2 + // Position of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Pos = 0x2 + // Bit mask of TARGET2_INT_CLR field. + SYSTIMER_INT_CLR_TARGET2_INT_CLR_Msk = 0x4 + // Bit TARGET2_INT_CLR. + SYSTIMER_INT_CLR_TARGET2_INT_CLR = 0x4 + + // INT_ST: systimer interrupt status register + // Position of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Pos = 0x0 + // Bit mask of TARGET0_INT_ST field. + SYSTIMER_INT_ST_TARGET0_INT_ST_Msk = 0x1 + // Bit TARGET0_INT_ST. + SYSTIMER_INT_ST_TARGET0_INT_ST = 0x1 + // Position of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Pos = 0x1 + // Bit mask of TARGET1_INT_ST field. + SYSTIMER_INT_ST_TARGET1_INT_ST_Msk = 0x2 + // Bit TARGET1_INT_ST. + SYSTIMER_INT_ST_TARGET1_INT_ST = 0x2 + // Position of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Pos = 0x2 + // Bit mask of TARGET2_INT_ST field. + SYSTIMER_INT_ST_TARGET2_INT_ST_Msk = 0x4 + // Bit TARGET2_INT_ST. + SYSTIMER_INT_ST_TARGET2_INT_ST = 0x4 + + // REAL_TARGET0_LO: system timer comp0 actual target value low register + // Position of TARGET0_LO_RO field. + SYSTIMER_REAL_TARGET0_LO_TARGET0_LO_RO_Pos = 0x0 + // Bit mask of TARGET0_LO_RO field. + SYSTIMER_REAL_TARGET0_LO_TARGET0_LO_RO_Msk = 0xffffffff + + // REAL_TARGET0_HI: system timer comp0 actual target value high register + // Position of TARGET0_HI_RO field. + SYSTIMER_REAL_TARGET0_HI_TARGET0_HI_RO_Pos = 0x0 + // Bit mask of TARGET0_HI_RO field. + SYSTIMER_REAL_TARGET0_HI_TARGET0_HI_RO_Msk = 0xfffff + + // REAL_TARGET1_LO: system timer comp1 actual target value low register + // Position of TARGET1_LO_RO field. + SYSTIMER_REAL_TARGET1_LO_TARGET1_LO_RO_Pos = 0x0 + // Bit mask of TARGET1_LO_RO field. + SYSTIMER_REAL_TARGET1_LO_TARGET1_LO_RO_Msk = 0xffffffff + + // REAL_TARGET1_HI: system timer comp1 actual target value high register + // Position of TARGET1_HI_RO field. + SYSTIMER_REAL_TARGET1_HI_TARGET1_HI_RO_Pos = 0x0 + // Bit mask of TARGET1_HI_RO field. + SYSTIMER_REAL_TARGET1_HI_TARGET1_HI_RO_Msk = 0xfffff + + // REAL_TARGET2_LO: system timer comp2 actual target value low register + // Position of TARGET2_LO_RO field. + SYSTIMER_REAL_TARGET2_LO_TARGET2_LO_RO_Pos = 0x0 + // Bit mask of TARGET2_LO_RO field. + SYSTIMER_REAL_TARGET2_LO_TARGET2_LO_RO_Msk = 0xffffffff + + // REAL_TARGET2_HI: system timer comp2 actual target value high register + // Position of TARGET2_HI_RO field. + SYSTIMER_REAL_TARGET2_HI_TARGET2_HI_RO_Pos = 0x0 + // Bit mask of TARGET2_HI_RO field. + SYSTIMER_REAL_TARGET2_HI_TARGET2_HI_RO_Msk = 0xfffff + + // DATE: system timer version control register + // Position of DATE field. + SYSTIMER_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + SYSTIMER_DATE_DATE_Msk = 0xffffffff +) + +// Constants for TIMG0: Timer Group 0 +const ( + // T0CONFIG: Timer %s configuration register + // Position of USE_XTAL field. + TIMG_TCONFIG_USE_XTAL_Pos = 0x9 + // Bit mask of USE_XTAL field. + TIMG_TCONFIG_USE_XTAL_Msk = 0x200 + // Bit USE_XTAL. + TIMG_TCONFIG_USE_XTAL = 0x200 + // Position of ALARM_EN field. + TIMG_TCONFIG_ALARM_EN_Pos = 0xa + // Bit mask of ALARM_EN field. + TIMG_TCONFIG_ALARM_EN_Msk = 0x400 + // Bit ALARM_EN. + TIMG_TCONFIG_ALARM_EN = 0x400 + // Position of DIVIDER field. + TIMG_TCONFIG_DIVIDER_Pos = 0xd + // Bit mask of DIVIDER field. + TIMG_TCONFIG_DIVIDER_Msk = 0x1fffe000 + // Position of AUTORELOAD field. + TIMG_TCONFIG_AUTORELOAD_Pos = 0x1d + // Bit mask of AUTORELOAD field. + TIMG_TCONFIG_AUTORELOAD_Msk = 0x20000000 + // Bit AUTORELOAD. + TIMG_TCONFIG_AUTORELOAD = 0x20000000 + // Position of INCREASE field. + TIMG_TCONFIG_INCREASE_Pos = 0x1e + // Bit mask of INCREASE field. + TIMG_TCONFIG_INCREASE_Msk = 0x40000000 + // Bit INCREASE. + TIMG_TCONFIG_INCREASE = 0x40000000 + // Position of EN field. + TIMG_TCONFIG_EN_Pos = 0x1f + // Bit mask of EN field. + TIMG_TCONFIG_EN_Msk = 0x80000000 + // Bit EN. + TIMG_TCONFIG_EN = 0x80000000 + + // T0LO: Timer %s current value, low 32 bits + // Position of LO field. + TIMG_TLO_LO_Pos = 0x0 + // Bit mask of LO field. + TIMG_TLO_LO_Msk = 0xffffffff + + // T0HI: Timer %s current value, high 22 bits + // Position of HI field. + TIMG_THI_HI_Pos = 0x0 + // Bit mask of HI field. + TIMG_THI_HI_Msk = 0x3fffff + + // T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + // Position of UPDATE field. + TIMG_TUPDATE_UPDATE_Pos = 0x1f + // Bit mask of UPDATE field. + TIMG_TUPDATE_UPDATE_Msk = 0x80000000 + // Bit UPDATE. + TIMG_TUPDATE_UPDATE = 0x80000000 + + // T0ALARMLO: Timer %s alarm value, low 32 bits + // Position of ALARM_LO field. + TIMG_TALARMLO_ALARM_LO_Pos = 0x0 + // Bit mask of ALARM_LO field. + TIMG_TALARMLO_ALARM_LO_Msk = 0xffffffff + + // T0ALARMHI: Timer %s alarm value, high bits + // Position of ALARM_HI field. + TIMG_TALARMHI_ALARM_HI_Pos = 0x0 + // Bit mask of ALARM_HI field. + TIMG_TALARMHI_ALARM_HI_Msk = 0x3fffff + + // T0LOADLO: Timer %s reload value, low 32 bits + // Position of LOAD_LO field. + TIMG_TLOADLO_LOAD_LO_Pos = 0x0 + // Bit mask of LOAD_LO field. + TIMG_TLOADLO_LOAD_LO_Msk = 0xffffffff + + // T0LOADHI: Timer %s reload value, high 22 bits + // Position of LOAD_HI field. + TIMG_TLOADHI_LOAD_HI_Pos = 0x0 + // Bit mask of LOAD_HI field. + TIMG_TLOADHI_LOAD_HI_Msk = 0x3fffff + + // T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + // Position of LOAD field. + TIMG_TLOAD_LOAD_Pos = 0x0 + // Bit mask of LOAD field. + TIMG_TLOAD_LOAD_Msk = 0xffffffff + + // WDTCONFIG0: Watchdog timer configuration register + // Position of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xc + // Bit mask of WDT_APPCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x1000 + // Bit WDT_APPCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x1000 + // Position of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xd + // Bit mask of WDT_PROCPU_RESET_EN field. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x2000 + // Bit WDT_PROCPU_RESET_EN. + TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x2000 + // Position of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xe + // Bit mask of WDT_FLASHBOOT_MOD_EN field. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x4000 + // Bit WDT_FLASHBOOT_MOD_EN. + TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x4000 + // Position of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xf + // Bit mask of WDT_SYS_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0x38000 + // Position of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x12 + // Bit mask of WDT_CPU_RESET_LENGTH field. + TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x1c0000 + // Position of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Pos = 0x17 + // Bit mask of WDT_STG3 field. + TIMG_WDTCONFIG0_WDT_STG3_Msk = 0x1800000 + // Position of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Pos = 0x19 + // Bit mask of WDT_STG2 field. + TIMG_WDTCONFIG0_WDT_STG2_Msk = 0x6000000 + // Position of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Pos = 0x1b + // Bit mask of WDT_STG1 field. + TIMG_WDTCONFIG0_WDT_STG1_Msk = 0x18000000 + // Position of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Pos = 0x1d + // Bit mask of WDT_STG0 field. + TIMG_WDTCONFIG0_WDT_STG0_Msk = 0x60000000 + // Position of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Pos = 0x1f + // Bit mask of WDT_EN field. + TIMG_WDTCONFIG0_WDT_EN_Msk = 0x80000000 + // Bit WDT_EN. + TIMG_WDTCONFIG0_WDT_EN = 0x80000000 + + // WDTCONFIG1: Watchdog timer prescaler register + // Position of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Pos = 0x10 + // Bit mask of WDT_CLK_PRESCALE field. + TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Msk = 0xffff0000 + + // WDTCONFIG2: Watchdog timer stage 0 timeout value + // Position of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Pos = 0x0 + // Bit mask of WDT_STG0_HOLD field. + TIMG_WDTCONFIG2_WDT_STG0_HOLD_Msk = 0xffffffff + + // WDTCONFIG3: Watchdog timer stage 1 timeout value + // Position of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Pos = 0x0 + // Bit mask of WDT_STG1_HOLD field. + TIMG_WDTCONFIG3_WDT_STG1_HOLD_Msk = 0xffffffff + + // WDTCONFIG4: Watchdog timer stage 2 timeout value + // Position of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Pos = 0x0 + // Bit mask of WDT_STG2_HOLD field. + TIMG_WDTCONFIG4_WDT_STG2_HOLD_Msk = 0xffffffff + + // WDTCONFIG5: Watchdog timer stage 3 timeout value + // Position of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Pos = 0x0 + // Bit mask of WDT_STG3_HOLD field. + TIMG_WDTCONFIG5_WDT_STG3_HOLD_Msk = 0xffffffff + + // WDTFEED: Write to feed the watchdog timer + // Position of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Pos = 0x0 + // Bit mask of WDT_FEED field. + TIMG_WDTFEED_WDT_FEED_Msk = 0xffffffff + + // WDTWPROTECT: Watchdog write protect register + // Position of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Pos = 0x0 + // Bit mask of WDT_WKEY field. + TIMG_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff + + // RTCCALICFG: RTC calibration configure register + // Position of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Pos = 0xc + // Bit mask of RTC_CALI_START_CYCLING field. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Msk = 0x1000 + // Bit RTC_CALI_START_CYCLING. + TIMG_RTCCALICFG_RTC_CALI_START_CYCLING = 0x1000 + // Position of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Pos = 0xd + // Bit mask of RTC_CALI_CLK_SEL field. + TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Msk = 0x6000 + // Position of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Pos = 0xf + // Bit mask of RTC_CALI_RDY field. + TIMG_RTCCALICFG_RTC_CALI_RDY_Msk = 0x8000 + // Bit RTC_CALI_RDY. + TIMG_RTCCALICFG_RTC_CALI_RDY = 0x8000 + // Position of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Pos = 0x10 + // Bit mask of RTC_CALI_MAX field. + TIMG_RTCCALICFG_RTC_CALI_MAX_Msk = 0x7fff0000 + // Position of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Pos = 0x1f + // Bit mask of RTC_CALI_START field. + TIMG_RTCCALICFG_RTC_CALI_START_Msk = 0x80000000 + // Bit RTC_CALI_START. + TIMG_RTCCALICFG_RTC_CALI_START = 0x80000000 + + // RTCCALICFG1: RTC calibration configure1 register + // Position of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Pos = 0x0 + // Bit mask of RTC_CALI_CYCLING_DATA_VLD field. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Msk = 0x1 + // Bit RTC_CALI_CYCLING_DATA_VLD. + TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD = 0x1 + // Position of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Pos = 0x7 + // Bit mask of RTC_CALI_VALUE field. + TIMG_RTCCALICFG1_RTC_CALI_VALUE_Msk = 0xffffff80 + + // INT_ENA_TIMERS: Interrupt enable bits + // Position of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Pos = 0x0 + // Bit mask of T0_INT_ENA field. + TIMG_INT_ENA_TIMERS_T0_INT_ENA_Msk = 0x1 + // Bit T0_INT_ENA. + TIMG_INT_ENA_TIMERS_T0_INT_ENA = 0x1 + // Position of T1_INT_ENA field. + TIMG_INT_ENA_TIMERS_T1_INT_ENA_Pos = 0x1 + // Bit mask of T1_INT_ENA field. + TIMG_INT_ENA_TIMERS_T1_INT_ENA_Msk = 0x2 + // Bit T1_INT_ENA. + TIMG_INT_ENA_TIMERS_T1_INT_ENA = 0x2 + // Position of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Pos = 0x2 + // Bit mask of WDT_INT_ENA field. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Msk = 0x4 + // Bit WDT_INT_ENA. + TIMG_INT_ENA_TIMERS_WDT_INT_ENA = 0x4 + + // INT_RAW_TIMERS: Raw interrupt status + // Position of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Pos = 0x0 + // Bit mask of T0_INT_RAW field. + TIMG_INT_RAW_TIMERS_T0_INT_RAW_Msk = 0x1 + // Bit T0_INT_RAW. + TIMG_INT_RAW_TIMERS_T0_INT_RAW = 0x1 + // Position of T1_INT_RAW field. + TIMG_INT_RAW_TIMERS_T1_INT_RAW_Pos = 0x1 + // Bit mask of T1_INT_RAW field. + TIMG_INT_RAW_TIMERS_T1_INT_RAW_Msk = 0x2 + // Bit T1_INT_RAW. + TIMG_INT_RAW_TIMERS_T1_INT_RAW = 0x2 + // Position of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Pos = 0x2 + // Bit mask of WDT_INT_RAW field. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Msk = 0x4 + // Bit WDT_INT_RAW. + TIMG_INT_RAW_TIMERS_WDT_INT_RAW = 0x4 + + // INT_ST_TIMERS: Masked interrupt status + // Position of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Pos = 0x0 + // Bit mask of T0_INT_ST field. + TIMG_INT_ST_TIMERS_T0_INT_ST_Msk = 0x1 + // Bit T0_INT_ST. + TIMG_INT_ST_TIMERS_T0_INT_ST = 0x1 + // Position of T1_INT_ST field. + TIMG_INT_ST_TIMERS_T1_INT_ST_Pos = 0x1 + // Bit mask of T1_INT_ST field. + TIMG_INT_ST_TIMERS_T1_INT_ST_Msk = 0x2 + // Bit T1_INT_ST. + TIMG_INT_ST_TIMERS_T1_INT_ST = 0x2 + // Position of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Pos = 0x2 + // Bit mask of WDT_INT_ST field. + TIMG_INT_ST_TIMERS_WDT_INT_ST_Msk = 0x4 + // Bit WDT_INT_ST. + TIMG_INT_ST_TIMERS_WDT_INT_ST = 0x4 + + // INT_CLR_TIMERS: Interrupt clear bits + // Position of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Pos = 0x0 + // Bit mask of T0_INT_CLR field. + TIMG_INT_CLR_TIMERS_T0_INT_CLR_Msk = 0x1 + // Bit T0_INT_CLR. + TIMG_INT_CLR_TIMERS_T0_INT_CLR = 0x1 + // Position of T1_INT_CLR field. + TIMG_INT_CLR_TIMERS_T1_INT_CLR_Pos = 0x1 + // Bit mask of T1_INT_CLR field. + TIMG_INT_CLR_TIMERS_T1_INT_CLR_Msk = 0x2 + // Bit T1_INT_CLR. + TIMG_INT_CLR_TIMERS_T1_INT_CLR = 0x2 + // Position of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Pos = 0x2 + // Bit mask of WDT_INT_CLR field. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Msk = 0x4 + // Bit WDT_INT_CLR. + TIMG_INT_CLR_TIMERS_WDT_INT_CLR = 0x4 + + // RTCCALICFG2: Timer group calibration register + // Position of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Pos = 0x0 + // Bit mask of RTC_CALI_TIMEOUT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Msk = 0x1 + // Bit RTC_CALI_TIMEOUT. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT = 0x1 + // Position of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Pos = 0x3 + // Bit mask of RTC_CALI_TIMEOUT_RST_CNT field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Msk = 0x78 + // Position of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Pos = 0x7 + // Bit mask of RTC_CALI_TIMEOUT_THRES field. + TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Msk = 0xffffff80 + + // NTIMERS_DATE: Timer version control register + // Position of NTIMERS_DATE field. + TIMG_NTIMERS_DATE_NTIMERS_DATE_Pos = 0x0 + // Bit mask of NTIMERS_DATE field. + TIMG_NTIMERS_DATE_NTIMERS_DATE_Msk = 0xfffffff + + // REGCLK: Timer group clock gate register + // Position of CLK_EN field. + TIMG_REGCLK_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + TIMG_REGCLK_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + TIMG_REGCLK_CLK_EN = 0x80000000 +) + +// Constants for TWAI0: Two-Wire Automotive Interface +const ( + // MODE: Mode Register + // Position of RESET_MODE field. + TWAI_MODE_RESET_MODE_Pos = 0x0 + // Bit mask of RESET_MODE field. + TWAI_MODE_RESET_MODE_Msk = 0x1 + // Bit RESET_MODE. + TWAI_MODE_RESET_MODE = 0x1 + // Position of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Pos = 0x1 + // Bit mask of LISTEN_ONLY_MODE field. + TWAI_MODE_LISTEN_ONLY_MODE_Msk = 0x2 + // Bit LISTEN_ONLY_MODE. + TWAI_MODE_LISTEN_ONLY_MODE = 0x2 + // Position of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Pos = 0x2 + // Bit mask of SELF_TEST_MODE field. + TWAI_MODE_SELF_TEST_MODE_Msk = 0x4 + // Bit SELF_TEST_MODE. + TWAI_MODE_SELF_TEST_MODE = 0x4 + // Position of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Pos = 0x3 + // Bit mask of RX_FILTER_MODE field. + TWAI_MODE_RX_FILTER_MODE_Msk = 0x8 + // Bit RX_FILTER_MODE. + TWAI_MODE_RX_FILTER_MODE = 0x8 + + // CMD: Command Register + // Position of TX_REQ field. + TWAI_CMD_TX_REQ_Pos = 0x0 + // Bit mask of TX_REQ field. + TWAI_CMD_TX_REQ_Msk = 0x1 + // Bit TX_REQ. + TWAI_CMD_TX_REQ = 0x1 + // Position of ABORT_TX field. + TWAI_CMD_ABORT_TX_Pos = 0x1 + // Bit mask of ABORT_TX field. + TWAI_CMD_ABORT_TX_Msk = 0x2 + // Bit ABORT_TX. + TWAI_CMD_ABORT_TX = 0x2 + // Position of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Pos = 0x2 + // Bit mask of RELEASE_BUF field. + TWAI_CMD_RELEASE_BUF_Msk = 0x4 + // Bit RELEASE_BUF. + TWAI_CMD_RELEASE_BUF = 0x4 + // Position of CLR_OVERRUN field. + TWAI_CMD_CLR_OVERRUN_Pos = 0x3 + // Bit mask of CLR_OVERRUN field. + TWAI_CMD_CLR_OVERRUN_Msk = 0x8 + // Bit CLR_OVERRUN. + TWAI_CMD_CLR_OVERRUN = 0x8 + // Position of SELF_RX_REQ field. + TWAI_CMD_SELF_RX_REQ_Pos = 0x4 + // Bit mask of SELF_RX_REQ field. + TWAI_CMD_SELF_RX_REQ_Msk = 0x10 + // Bit SELF_RX_REQ. + TWAI_CMD_SELF_RX_REQ = 0x10 + + // STATUS: Status register + // Position of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Pos = 0x0 + // Bit mask of RX_BUF_ST field. + TWAI_STATUS_RX_BUF_ST_Msk = 0x1 + // Bit RX_BUF_ST. + TWAI_STATUS_RX_BUF_ST = 0x1 + // Position of OVERRUN_ST field. + TWAI_STATUS_OVERRUN_ST_Pos = 0x1 + // Bit mask of OVERRUN_ST field. + TWAI_STATUS_OVERRUN_ST_Msk = 0x2 + // Bit OVERRUN_ST. + TWAI_STATUS_OVERRUN_ST = 0x2 + // Position of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Pos = 0x2 + // Bit mask of TX_BUF_ST field. + TWAI_STATUS_TX_BUF_ST_Msk = 0x4 + // Bit TX_BUF_ST. + TWAI_STATUS_TX_BUF_ST = 0x4 + // Position of TX_COMPLETE field. + TWAI_STATUS_TX_COMPLETE_Pos = 0x3 + // Bit mask of TX_COMPLETE field. + TWAI_STATUS_TX_COMPLETE_Msk = 0x8 + // Bit TX_COMPLETE. + TWAI_STATUS_TX_COMPLETE = 0x8 + // Position of RX_ST field. + TWAI_STATUS_RX_ST_Pos = 0x4 + // Bit mask of RX_ST field. + TWAI_STATUS_RX_ST_Msk = 0x10 + // Bit RX_ST. + TWAI_STATUS_RX_ST = 0x10 + // Position of TX_ST field. + TWAI_STATUS_TX_ST_Pos = 0x5 + // Bit mask of TX_ST field. + TWAI_STATUS_TX_ST_Msk = 0x20 + // Bit TX_ST. + TWAI_STATUS_TX_ST = 0x20 + // Position of ERR_ST field. + TWAI_STATUS_ERR_ST_Pos = 0x6 + // Bit mask of ERR_ST field. + TWAI_STATUS_ERR_ST_Msk = 0x40 + // Bit ERR_ST. + TWAI_STATUS_ERR_ST = 0x40 + // Position of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Pos = 0x7 + // Bit mask of BUS_OFF_ST field. + TWAI_STATUS_BUS_OFF_ST_Msk = 0x80 + // Bit BUS_OFF_ST. + TWAI_STATUS_BUS_OFF_ST = 0x80 + // Position of MISS_ST field. + TWAI_STATUS_MISS_ST_Pos = 0x8 + // Bit mask of MISS_ST field. + TWAI_STATUS_MISS_ST_Msk = 0x100 + // Bit MISS_ST. + TWAI_STATUS_MISS_ST = 0x100 + + // INT_RAW: Interrupt Register + // Position of RX_INT_ST field. + TWAI_INT_RAW_RX_INT_ST_Pos = 0x0 + // Bit mask of RX_INT_ST field. + TWAI_INT_RAW_RX_INT_ST_Msk = 0x1 + // Bit RX_INT_ST. + TWAI_INT_RAW_RX_INT_ST = 0x1 + // Position of TX_INT_ST field. + TWAI_INT_RAW_TX_INT_ST_Pos = 0x1 + // Bit mask of TX_INT_ST field. + TWAI_INT_RAW_TX_INT_ST_Msk = 0x2 + // Bit TX_INT_ST. + TWAI_INT_RAW_TX_INT_ST = 0x2 + // Position of ERR_WARN_INT_ST field. + TWAI_INT_RAW_ERR_WARN_INT_ST_Pos = 0x2 + // Bit mask of ERR_WARN_INT_ST field. + TWAI_INT_RAW_ERR_WARN_INT_ST_Msk = 0x4 + // Bit ERR_WARN_INT_ST. + TWAI_INT_RAW_ERR_WARN_INT_ST = 0x4 + // Position of OVERRUN_INT_ST field. + TWAI_INT_RAW_OVERRUN_INT_ST_Pos = 0x3 + // Bit mask of OVERRUN_INT_ST field. + TWAI_INT_RAW_OVERRUN_INT_ST_Msk = 0x8 + // Bit OVERRUN_INT_ST. + TWAI_INT_RAW_OVERRUN_INT_ST = 0x8 + // Position of ERR_PASSIVE_INT_ST field. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ST field. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ST. + TWAI_INT_RAW_ERR_PASSIVE_INT_ST = 0x20 + // Position of ARB_LOST_INT_ST field. + TWAI_INT_RAW_ARB_LOST_INT_ST_Pos = 0x6 + // Bit mask of ARB_LOST_INT_ST field. + TWAI_INT_RAW_ARB_LOST_INT_ST_Msk = 0x40 + // Bit ARB_LOST_INT_ST. + TWAI_INT_RAW_ARB_LOST_INT_ST = 0x40 + // Position of BUS_ERR_INT_ST field. + TWAI_INT_RAW_BUS_ERR_INT_ST_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ST field. + TWAI_INT_RAW_BUS_ERR_INT_ST_Msk = 0x80 + // Bit BUS_ERR_INT_ST. + TWAI_INT_RAW_BUS_ERR_INT_ST = 0x80 + + // INT_ENA: Interrupt Enable Register + // Position of RX_INT_ENA field. + TWAI_INT_ENA_RX_INT_ENA_Pos = 0x0 + // Bit mask of RX_INT_ENA field. + TWAI_INT_ENA_RX_INT_ENA_Msk = 0x1 + // Bit RX_INT_ENA. + TWAI_INT_ENA_RX_INT_ENA = 0x1 + // Position of TX_INT_ENA field. + TWAI_INT_ENA_TX_INT_ENA_Pos = 0x1 + // Bit mask of TX_INT_ENA field. + TWAI_INT_ENA_TX_INT_ENA_Msk = 0x2 + // Bit TX_INT_ENA. + TWAI_INT_ENA_TX_INT_ENA = 0x2 + // Position of ERR_WARN_INT_ENA field. + TWAI_INT_ENA_ERR_WARN_INT_ENA_Pos = 0x2 + // Bit mask of ERR_WARN_INT_ENA field. + TWAI_INT_ENA_ERR_WARN_INT_ENA_Msk = 0x4 + // Bit ERR_WARN_INT_ENA. + TWAI_INT_ENA_ERR_WARN_INT_ENA = 0x4 + // Position of OVERRUN_INT_ENA field. + TWAI_INT_ENA_OVERRUN_INT_ENA_Pos = 0x3 + // Bit mask of OVERRUN_INT_ENA field. + TWAI_INT_ENA_OVERRUN_INT_ENA_Msk = 0x8 + // Bit OVERRUN_INT_ENA. + TWAI_INT_ENA_OVERRUN_INT_ENA = 0x8 + // Position of ERR_PASSIVE_INT_ENA field. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA_Pos = 0x5 + // Bit mask of ERR_PASSIVE_INT_ENA field. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA_Msk = 0x20 + // Bit ERR_PASSIVE_INT_ENA. + TWAI_INT_ENA_ERR_PASSIVE_INT_ENA = 0x20 + // Position of ARB_LOST_INT_ENA field. + TWAI_INT_ENA_ARB_LOST_INT_ENA_Pos = 0x6 + // Bit mask of ARB_LOST_INT_ENA field. + TWAI_INT_ENA_ARB_LOST_INT_ENA_Msk = 0x40 + // Bit ARB_LOST_INT_ENA. + TWAI_INT_ENA_ARB_LOST_INT_ENA = 0x40 + // Position of BUS_ERR_INT_ENA field. + TWAI_INT_ENA_BUS_ERR_INT_ENA_Pos = 0x7 + // Bit mask of BUS_ERR_INT_ENA field. + TWAI_INT_ENA_BUS_ERR_INT_ENA_Msk = 0x80 + // Bit BUS_ERR_INT_ENA. + TWAI_INT_ENA_BUS_ERR_INT_ENA = 0x80 + + // BUS_TIMING_0: Bus Timing Register 0 + // Position of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Pos = 0x0 + // Bit mask of BAUD_PRESC field. + TWAI_BUS_TIMING_0_BAUD_PRESC_Msk = 0x3fff + // Position of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Pos = 0xe + // Bit mask of SYNC_JUMP_WIDTH field. + TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Msk = 0xc000 + + // BUS_TIMING_1: Bus Timing Register 1 + // Position of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Pos = 0x0 + // Bit mask of TIME_SEG1 field. + TWAI_BUS_TIMING_1_TIME_SEG1_Msk = 0xf + // Position of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Pos = 0x4 + // Bit mask of TIME_SEG2 field. + TWAI_BUS_TIMING_1_TIME_SEG2_Msk = 0x70 + // Position of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Pos = 0x7 + // Bit mask of TIME_SAMP field. + TWAI_BUS_TIMING_1_TIME_SAMP_Msk = 0x80 + // Bit TIME_SAMP. + TWAI_BUS_TIMING_1_TIME_SAMP = 0x80 + + // ARB_LOST_CAP: Arbitration Lost Capture Register + // Position of ARB_LOST_CAP field. + TWAI_ARB_LOST_CAP_ARB_LOST_CAP_Pos = 0x0 + // Bit mask of ARB_LOST_CAP field. + TWAI_ARB_LOST_CAP_ARB_LOST_CAP_Msk = 0x1f + + // ERR_CODE_CAP: Error Code Capture Register + // Position of ECC_SEGMENT field. + TWAI_ERR_CODE_CAP_ECC_SEGMENT_Pos = 0x0 + // Bit mask of ECC_SEGMENT field. + TWAI_ERR_CODE_CAP_ECC_SEGMENT_Msk = 0x1f + // Position of ECC_DIRECTION field. + TWAI_ERR_CODE_CAP_ECC_DIRECTION_Pos = 0x5 + // Bit mask of ECC_DIRECTION field. + TWAI_ERR_CODE_CAP_ECC_DIRECTION_Msk = 0x20 + // Bit ECC_DIRECTION. + TWAI_ERR_CODE_CAP_ECC_DIRECTION = 0x20 + // Position of ECC_TYPE field. + TWAI_ERR_CODE_CAP_ECC_TYPE_Pos = 0x6 + // Bit mask of ECC_TYPE field. + TWAI_ERR_CODE_CAP_ECC_TYPE_Msk = 0xc0 + + // ERR_WARNING_LIMIT: Error Warning Limit Register + // Position of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Pos = 0x0 + // Bit mask of ERR_WARNING_LIMIT field. + TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Msk = 0xff + + // RX_ERR_CNT: Receive Error Counter Register + // Position of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Pos = 0x0 + // Bit mask of RX_ERR_CNT field. + TWAI_RX_ERR_CNT_RX_ERR_CNT_Msk = 0xff + + // TX_ERR_CNT: Transmit Error Counter Register + // Position of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Pos = 0x0 + // Bit mask of TX_ERR_CNT field. + TWAI_TX_ERR_CNT_TX_ERR_CNT_Msk = 0xff + + // DATA_0: Data register 0 + // Position of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Pos = 0x0 + // Bit mask of TX_BYTE_0 field. + TWAI_DATA_0_TX_BYTE_0_Msk = 0xff + + // DATA_1: Data register 1 + // Position of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Pos = 0x0 + // Bit mask of TX_BYTE_1 field. + TWAI_DATA_1_TX_BYTE_1_Msk = 0xff + + // DATA_2: Data register 2 + // Position of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Pos = 0x0 + // Bit mask of TX_BYTE_2 field. + TWAI_DATA_2_TX_BYTE_2_Msk = 0xff + + // DATA_3: Data register 3 + // Position of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Pos = 0x0 + // Bit mask of TX_BYTE_3 field. + TWAI_DATA_3_TX_BYTE_3_Msk = 0xff + + // DATA_4: Data register 4 + // Position of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Pos = 0x0 + // Bit mask of TX_BYTE_4 field. + TWAI_DATA_4_TX_BYTE_4_Msk = 0xff + + // DATA_5: Data register 5 + // Position of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Pos = 0x0 + // Bit mask of TX_BYTE_5 field. + TWAI_DATA_5_TX_BYTE_5_Msk = 0xff + + // DATA_6: Data register 6 + // Position of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Pos = 0x0 + // Bit mask of TX_BYTE_6 field. + TWAI_DATA_6_TX_BYTE_6_Msk = 0xff + + // DATA_7: Data register 7 + // Position of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Pos = 0x0 + // Bit mask of TX_BYTE_7 field. + TWAI_DATA_7_TX_BYTE_7_Msk = 0xff + + // DATA_8: Data register 8 + // Position of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Pos = 0x0 + // Bit mask of TX_BYTE_8 field. + TWAI_DATA_8_TX_BYTE_8_Msk = 0xff + + // DATA_9: Data register 9 + // Position of TX_BYTE_9 field. + TWAI_DATA_9_TX_BYTE_9_Pos = 0x0 + // Bit mask of TX_BYTE_9 field. + TWAI_DATA_9_TX_BYTE_9_Msk = 0xff + + // DATA_10: Data register 10 + // Position of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Pos = 0x0 + // Bit mask of TX_BYTE_10 field. + TWAI_DATA_10_TX_BYTE_10_Msk = 0xff + + // DATA_11: Data register 11 + // Position of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Pos = 0x0 + // Bit mask of TX_BYTE_11 field. + TWAI_DATA_11_TX_BYTE_11_Msk = 0xff + + // DATA_12: Data register 12 + // Position of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Pos = 0x0 + // Bit mask of TX_BYTE_12 field. + TWAI_DATA_12_TX_BYTE_12_Msk = 0xff + + // RX_MESSAGE_CNT: Receive Message Counter Register + // Position of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Pos = 0x0 + // Bit mask of RX_MESSAGE_COUNTER field. + TWAI_RX_MESSAGE_CNT_RX_MESSAGE_COUNTER_Msk = 0x7f + + // CLOCK_DIVIDER: Clock Divider register + // Position of CD field. + TWAI_CLOCK_DIVIDER_CD_Pos = 0x0 + // Bit mask of CD field. + TWAI_CLOCK_DIVIDER_CD_Msk = 0xff + // Position of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Pos = 0x8 + // Bit mask of CLOCK_OFF field. + TWAI_CLOCK_DIVIDER_CLOCK_OFF_Msk = 0x100 + // Bit CLOCK_OFF. + TWAI_CLOCK_DIVIDER_CLOCK_OFF = 0x100 +) + +// Constants for UART0: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 +const ( + // FIFO: FIFO data register + // Position of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + + // INT_RAW: Raw interrupt status + // Position of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + // Position of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9 + // Bit mask of SW_XON_INT_RAW field. + UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200 + // Bit SW_XON_INT_RAW. + UART_INT_RAW_SW_XON_INT_RAW = 0x200 + // Position of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa + // Bit mask of SW_XOFF_INT_RAW field. + UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400 + // Bit SW_XOFF_INT_RAW. + UART_INT_RAW_SW_XOFF_INT_RAW = 0x400 + // Position of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb + // Bit mask of GLITCH_DET_INT_RAW field. + UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800 + // Bit GLITCH_DET_INT_RAW. + UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800 + // Position of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_RAW field. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_RAW. + UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000 + // Position of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of TX_DONE_INT_RAW field. + UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit TX_DONE_INT_RAW. + UART_INT_RAW_TX_DONE_INT_RAW = 0x4000 + // Position of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_RAW field. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_RAW. + UART_INT_RAW_RS485_PARITY_ERR_INT_RAW = 0x8000 + // Position of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_RAW field. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_RAW. + UART_INT_RAW_RS485_FRM_ERR_INT_RAW = 0x10000 + // Position of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_RAW field. + UART_INT_RAW_RS485_CLASH_INT_RAW_Msk = 0x20000 + // Bit RS485_CLASH_INT_RAW. + UART_INT_RAW_RS485_CLASH_INT_RAW = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_RAW field. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_RAW. + UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000 + // Position of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13 + // Bit mask of WAKEUP_INT_RAW field. + UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000 + // Bit WAKEUP_INT_RAW. + UART_INT_RAW_WAKEUP_INT_RAW = 0x80000 + + // INT_ST: Masked interrupt status + // Position of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + // Position of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Pos = 0x9 + // Bit mask of SW_XON_INT_ST field. + UART_INT_ST_SW_XON_INT_ST_Msk = 0x200 + // Bit SW_XON_INT_ST. + UART_INT_ST_SW_XON_INT_ST = 0x200 + // Position of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa + // Bit mask of SW_XOFF_INT_ST field. + UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400 + // Bit SW_XOFF_INT_ST. + UART_INT_ST_SW_XOFF_INT_ST = 0x400 + // Position of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ST field. + UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800 + // Bit GLITCH_DET_INT_ST. + UART_INT_ST_GLITCH_DET_INT_ST = 0x800 + // Position of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ST field. + UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ST. + UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ST field. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ST. + UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000 + // Position of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of TX_DONE_INT_ST field. + UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000 + // Bit TX_DONE_INT_ST. + UART_INT_ST_TX_DONE_INT_ST = 0x4000 + // Position of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ST field. + UART_INT_ST_RS485_PARITY_ERR_INT_ST_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ST. + UART_INT_ST_RS485_PARITY_ERR_INT_ST = 0x8000 + // Position of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ST field. + UART_INT_ST_RS485_FRM_ERR_INT_ST_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ST. + UART_INT_ST_RS485_FRM_ERR_INT_ST = 0x10000 + // Position of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ST field. + UART_INT_ST_RS485_CLASH_INT_ST_Msk = 0x20000 + // Bit RS485_CLASH_INT_ST. + UART_INT_ST_RS485_CLASH_INT_ST = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ST field. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ST. + UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000 + // Position of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13 + // Bit mask of WAKEUP_INT_ST field. + UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000 + // Bit WAKEUP_INT_ST. + UART_INT_ST_WAKEUP_INT_ST = 0x80000 + + // INT_ENA: Interrupt enable bits + // Position of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + // Position of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9 + // Bit mask of SW_XON_INT_ENA field. + UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200 + // Bit SW_XON_INT_ENA. + UART_INT_ENA_SW_XON_INT_ENA = 0x200 + // Position of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa + // Bit mask of SW_XOFF_INT_ENA field. + UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400 + // Bit SW_XOFF_INT_ENA. + UART_INT_ENA_SW_XOFF_INT_ENA = 0x400 + // Position of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb + // Bit mask of GLITCH_DET_INT_ENA field. + UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800 + // Bit GLITCH_DET_INT_ENA. + UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800 + // Position of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_ENA field. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_ENA. + UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000 + // Position of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of TX_DONE_INT_ENA field. + UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit TX_DONE_INT_ENA. + UART_INT_ENA_TX_DONE_INT_ENA = 0x4000 + // Position of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_ENA field. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_ENA. + UART_INT_ENA_RS485_PARITY_ERR_INT_ENA = 0x8000 + // Position of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_ENA field. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_ENA. + UART_INT_ENA_RS485_FRM_ERR_INT_ENA = 0x10000 + // Position of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_ENA field. + UART_INT_ENA_RS485_CLASH_INT_ENA_Msk = 0x20000 + // Bit RS485_CLASH_INT_ENA. + UART_INT_ENA_RS485_CLASH_INT_ENA = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_ENA field. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_ENA. + UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000 + // Position of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13 + // Bit mask of WAKEUP_INT_ENA field. + UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000 + // Bit WAKEUP_INT_ENA. + UART_INT_ENA_WAKEUP_INT_ENA = 0x80000 + + // INT_CLR: Interrupt clear bits + // Position of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + // Position of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9 + // Bit mask of SW_XON_INT_CLR field. + UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200 + // Bit SW_XON_INT_CLR. + UART_INT_CLR_SW_XON_INT_CLR = 0x200 + // Position of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa + // Bit mask of SW_XOFF_INT_CLR field. + UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400 + // Bit SW_XOFF_INT_CLR. + UART_INT_CLR_SW_XOFF_INT_CLR = 0x400 + // Position of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb + // Bit mask of GLITCH_DET_INT_CLR field. + UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800 + // Bit GLITCH_DET_INT_CLR. + UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800 + // Position of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc + // Bit mask of TX_BRK_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000 + // Bit TX_BRK_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000 + // Position of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd + // Bit mask of TX_BRK_IDLE_DONE_INT_CLR field. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000 + // Bit TX_BRK_IDLE_DONE_INT_CLR. + UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000 + // Position of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of TX_DONE_INT_CLR field. + UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit TX_DONE_INT_CLR. + UART_INT_CLR_TX_DONE_INT_CLR = 0x4000 + // Position of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Pos = 0xf + // Bit mask of RS485_PARITY_ERR_INT_CLR field. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Msk = 0x8000 + // Bit RS485_PARITY_ERR_INT_CLR. + UART_INT_CLR_RS485_PARITY_ERR_INT_CLR = 0x8000 + // Position of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Pos = 0x10 + // Bit mask of RS485_FRM_ERR_INT_CLR field. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Msk = 0x10000 + // Bit RS485_FRM_ERR_INT_CLR. + UART_INT_CLR_RS485_FRM_ERR_INT_CLR = 0x10000 + // Position of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Pos = 0x11 + // Bit mask of RS485_CLASH_INT_CLR field. + UART_INT_CLR_RS485_CLASH_INT_CLR_Msk = 0x20000 + // Bit RS485_CLASH_INT_CLR. + UART_INT_CLR_RS485_CLASH_INT_CLR = 0x20000 + // Position of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12 + // Bit mask of AT_CMD_CHAR_DET_INT_CLR field. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000 + // Bit AT_CMD_CHAR_DET_INT_CLR. + UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000 + // Position of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13 + // Bit mask of WAKEUP_INT_CLR field. + UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000 + // Bit WAKEUP_INT_CLR. + UART_INT_CLR_WAKEUP_INT_CLR = 0x80000 + + // CLKDIV: Clock divider configuration + // Position of CLKDIV field. + UART_CLKDIV_CLKDIV_Pos = 0x0 + // Bit mask of CLKDIV field. + UART_CLKDIV_CLKDIV_Msk = 0xfff + // Position of FRAG field. + UART_CLKDIV_FRAG_Pos = 0x14 + // Bit mask of FRAG field. + UART_CLKDIV_FRAG_Msk = 0xf00000 + + // RX_FILT: Rx Filter configuration + // Position of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Pos = 0x0 + // Bit mask of GLITCH_FILT field. + UART_RX_FILT_GLITCH_FILT_Msk = 0xff + // Position of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Pos = 0x8 + // Bit mask of GLITCH_FILT_EN field. + UART_RX_FILT_GLITCH_FILT_EN_Msk = 0x100 + // Bit GLITCH_FILT_EN. + UART_RX_FILT_GLITCH_FILT_EN = 0x100 + + // STATUS: UART status register + // Position of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Pos = 0x0 + // Bit mask of RXFIFO_CNT field. + UART_STATUS_RXFIFO_CNT_Msk = 0x3ff + // Position of DSRN field. + UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + UART_STATUS_DSRN = 0x2000 + // Position of CTSN field. + UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + UART_STATUS_CTSN = 0x4000 + // Position of RXD field. + UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + UART_STATUS_RXD = 0x8000 + // Position of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Pos = 0x10 + // Bit mask of TXFIFO_CNT field. + UART_STATUS_TXFIFO_CNT_Msk = 0x3ff0000 + // Position of DTRN field. + UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + UART_STATUS_DTRN = 0x20000000 + // Position of RTSN field. + UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + UART_STATUS_RTSN = 0x40000000 + // Position of TXD field. + UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + UART_STATUS_TXD = 0x80000000 + + // CONF0: a + // Position of PARITY field. + UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + UART_CONF0_PARITY = 0x1 + // Position of PARITY_EN field. + UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + UART_CONF0_PARITY_EN = 0x2 + // Position of BIT_NUM field. + UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + UART_CONF0_BIT_NUM_Msk = 0xc + // Position of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of SW_RTS field. + UART_CONF0_SW_RTS_Pos = 0x6 + // Bit mask of SW_RTS field. + UART_CONF0_SW_RTS_Msk = 0x40 + // Bit SW_RTS. + UART_CONF0_SW_RTS = 0x40 + // Position of SW_DTR field. + UART_CONF0_SW_DTR_Pos = 0x7 + // Bit mask of SW_DTR field. + UART_CONF0_SW_DTR_Msk = 0x80 + // Bit SW_DTR. + UART_CONF0_SW_DTR = 0x80 + // Position of TXD_BRK field. + UART_CONF0_TXD_BRK_Pos = 0x8 + // Bit mask of TXD_BRK field. + UART_CONF0_TXD_BRK_Msk = 0x100 + // Bit TXD_BRK. + UART_CONF0_TXD_BRK = 0x100 + // Position of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Pos = 0x9 + // Bit mask of IRDA_DPLX field. + UART_CONF0_IRDA_DPLX_Msk = 0x200 + // Bit IRDA_DPLX. + UART_CONF0_IRDA_DPLX = 0x200 + // Position of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Pos = 0xa + // Bit mask of IRDA_TX_EN field. + UART_CONF0_IRDA_TX_EN_Msk = 0x400 + // Bit IRDA_TX_EN. + UART_CONF0_IRDA_TX_EN = 0x400 + // Position of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Pos = 0xb + // Bit mask of IRDA_WCTL field. + UART_CONF0_IRDA_WCTL_Msk = 0x800 + // Bit IRDA_WCTL. + UART_CONF0_IRDA_WCTL = 0x800 + // Position of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Pos = 0xc + // Bit mask of IRDA_TX_INV field. + UART_CONF0_IRDA_TX_INV_Msk = 0x1000 + // Bit IRDA_TX_INV. + UART_CONF0_IRDA_TX_INV = 0x1000 + // Position of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Pos = 0xd + // Bit mask of IRDA_RX_INV field. + UART_CONF0_IRDA_RX_INV_Msk = 0x2000 + // Bit IRDA_RX_INV. + UART_CONF0_IRDA_RX_INV = 0x2000 + // Position of LOOPBACK field. + UART_CONF0_LOOPBACK_Pos = 0xe + // Bit mask of LOOPBACK field. + UART_CONF0_LOOPBACK_Msk = 0x4000 + // Bit LOOPBACK. + UART_CONF0_LOOPBACK = 0x4000 + // Position of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Pos = 0xf + // Bit mask of TX_FLOW_EN field. + UART_CONF0_TX_FLOW_EN_Msk = 0x8000 + // Bit TX_FLOW_EN. + UART_CONF0_TX_FLOW_EN = 0x8000 + // Position of IRDA_EN field. + UART_CONF0_IRDA_EN_Pos = 0x10 + // Bit mask of IRDA_EN field. + UART_CONF0_IRDA_EN_Msk = 0x10000 + // Bit IRDA_EN. + UART_CONF0_IRDA_EN = 0x10000 + // Position of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Pos = 0x11 + // Bit mask of RXFIFO_RST field. + UART_CONF0_RXFIFO_RST_Msk = 0x20000 + // Bit RXFIFO_RST. + UART_CONF0_RXFIFO_RST = 0x20000 + // Position of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Pos = 0x12 + // Bit mask of TXFIFO_RST field. + UART_CONF0_TXFIFO_RST_Msk = 0x40000 + // Bit TXFIFO_RST. + UART_CONF0_TXFIFO_RST = 0x40000 + // Position of RXD_INV field. + UART_CONF0_RXD_INV_Pos = 0x13 + // Bit mask of RXD_INV field. + UART_CONF0_RXD_INV_Msk = 0x80000 + // Bit RXD_INV. + UART_CONF0_RXD_INV = 0x80000 + // Position of CTS_INV field. + UART_CONF0_CTS_INV_Pos = 0x14 + // Bit mask of CTS_INV field. + UART_CONF0_CTS_INV_Msk = 0x100000 + // Bit CTS_INV. + UART_CONF0_CTS_INV = 0x100000 + // Position of DSR_INV field. + UART_CONF0_DSR_INV_Pos = 0x15 + // Bit mask of DSR_INV field. + UART_CONF0_DSR_INV_Msk = 0x200000 + // Bit DSR_INV. + UART_CONF0_DSR_INV = 0x200000 + // Position of TXD_INV field. + UART_CONF0_TXD_INV_Pos = 0x16 + // Bit mask of TXD_INV field. + UART_CONF0_TXD_INV_Msk = 0x400000 + // Bit TXD_INV. + UART_CONF0_TXD_INV = 0x400000 + // Position of RTS_INV field. + UART_CONF0_RTS_INV_Pos = 0x17 + // Bit mask of RTS_INV field. + UART_CONF0_RTS_INV_Msk = 0x800000 + // Bit RTS_INV. + UART_CONF0_RTS_INV = 0x800000 + // Position of DTR_INV field. + UART_CONF0_DTR_INV_Pos = 0x18 + // Bit mask of DTR_INV field. + UART_CONF0_DTR_INV_Msk = 0x1000000 + // Bit DTR_INV. + UART_CONF0_DTR_INV = 0x1000000 + // Position of CLK_EN field. + UART_CONF0_CLK_EN_Pos = 0x19 + // Bit mask of CLK_EN field. + UART_CONF0_CLK_EN_Msk = 0x2000000 + // Bit CLK_EN. + UART_CONF0_CLK_EN = 0x2000000 + // Position of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Pos = 0x1a + // Bit mask of ERR_WR_MASK field. + UART_CONF0_ERR_WR_MASK_Msk = 0x4000000 + // Bit ERR_WR_MASK. + UART_CONF0_ERR_WR_MASK = 0x4000000 + // Position of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Pos = 0x1b + // Bit mask of AUTOBAUD_EN field. + UART_CONF0_AUTOBAUD_EN_Msk = 0x8000000 + // Bit AUTOBAUD_EN. + UART_CONF0_AUTOBAUD_EN = 0x8000000 + // Position of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Pos = 0x1c + // Bit mask of MEM_CLK_EN field. + UART_CONF0_MEM_CLK_EN_Msk = 0x10000000 + // Bit MEM_CLK_EN. + UART_CONF0_MEM_CLK_EN = 0x10000000 + + // CONF1: Configuration register 1 + // Position of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0x3ff + // Position of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0xa + // Bit mask of TXFIFO_EMPTY_THRHD field. + UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0xffc00 + // Position of DIS_RX_DAT_OVF field. + UART_CONF1_DIS_RX_DAT_OVF_Pos = 0x14 + // Bit mask of DIS_RX_DAT_OVF field. + UART_CONF1_DIS_RX_DAT_OVF_Msk = 0x100000 + // Bit DIS_RX_DAT_OVF. + UART_CONF1_DIS_RX_DAT_OVF = 0x100000 + // Position of RX_TOUT_FLOW_DIS field. + UART_CONF1_RX_TOUT_FLOW_DIS_Pos = 0x15 + // Bit mask of RX_TOUT_FLOW_DIS field. + UART_CONF1_RX_TOUT_FLOW_DIS_Msk = 0x200000 + // Bit RX_TOUT_FLOW_DIS. + UART_CONF1_RX_TOUT_FLOW_DIS = 0x200000 + // Position of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Pos = 0x16 + // Bit mask of RX_FLOW_EN field. + UART_CONF1_RX_FLOW_EN_Msk = 0x400000 + // Bit RX_FLOW_EN. + UART_CONF1_RX_FLOW_EN = 0x400000 + // Position of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Pos = 0x17 + // Bit mask of RX_TOUT_EN field. + UART_CONF1_RX_TOUT_EN_Msk = 0x800000 + // Bit RX_TOUT_EN. + UART_CONF1_RX_TOUT_EN = 0x800000 + + // LOWPULSE: Autobaud minimum low pulse duration register + // Position of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_LOWPULSE_MIN_CNT_Msk = 0xfff + + // HIGHPULSE: Autobaud minimum high pulse duration register + // Position of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of MIN_CNT field. + UART_HIGHPULSE_MIN_CNT_Msk = 0xfff + + // RXD_CNT: Autobaud edge change count register + // Position of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0 + // Bit mask of RXD_EDGE_CNT field. + UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff + + // FLOW_CONF: Software flow-control configuration + // Position of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Pos = 0x0 + // Bit mask of SW_FLOW_CON_EN field. + UART_FLOW_CONF_SW_FLOW_CON_EN_Msk = 0x1 + // Bit SW_FLOW_CON_EN. + UART_FLOW_CONF_SW_FLOW_CON_EN = 0x1 + // Position of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Pos = 0x1 + // Bit mask of XONOFF_DEL field. + UART_FLOW_CONF_XONOFF_DEL_Msk = 0x2 + // Bit XONOFF_DEL. + UART_FLOW_CONF_XONOFF_DEL = 0x2 + // Position of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Pos = 0x2 + // Bit mask of FORCE_XON field. + UART_FLOW_CONF_FORCE_XON_Msk = 0x4 + // Bit FORCE_XON. + UART_FLOW_CONF_FORCE_XON = 0x4 + // Position of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Pos = 0x3 + // Bit mask of FORCE_XOFF field. + UART_FLOW_CONF_FORCE_XOFF_Msk = 0x8 + // Bit FORCE_XOFF. + UART_FLOW_CONF_FORCE_XOFF = 0x8 + // Position of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Pos = 0x4 + // Bit mask of SEND_XON field. + UART_FLOW_CONF_SEND_XON_Msk = 0x10 + // Bit SEND_XON. + UART_FLOW_CONF_SEND_XON = 0x10 + // Position of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Pos = 0x5 + // Bit mask of SEND_XOFF field. + UART_FLOW_CONF_SEND_XOFF_Msk = 0x20 + // Bit SEND_XOFF. + UART_FLOW_CONF_SEND_XOFF = 0x20 + + // SLEEP_CONF: Sleep-mode configuration + // Position of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Pos = 0x0 + // Bit mask of ACTIVE_THRESHOLD field. + UART_SLEEP_CONF_ACTIVE_THRESHOLD_Msk = 0x3ff + + // SWFC_CONF0: Software flow-control character configuration + // Position of XOFF_THRESHOLD field. + UART_SWFC_CONF0_XOFF_THRESHOLD_Pos = 0x0 + // Bit mask of XOFF_THRESHOLD field. + UART_SWFC_CONF0_XOFF_THRESHOLD_Msk = 0x3ff + // Position of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Pos = 0xa + // Bit mask of XOFF_CHAR field. + UART_SWFC_CONF0_XOFF_CHAR_Msk = 0x3fc00 + + // SWFC_CONF1: Software flow-control character configuration + // Position of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x0 + // Bit mask of XON_THRESHOLD field. + UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0x3ff + // Position of XON_CHAR field. + UART_SWFC_CONF1_XON_CHAR_Pos = 0xa + // Bit mask of XON_CHAR field. + UART_SWFC_CONF1_XON_CHAR_Msk = 0x3fc00 + + // TXBRK_CONF: Tx Break character configuration + // Position of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Pos = 0x0 + // Bit mask of TX_BRK_NUM field. + UART_TXBRK_CONF_TX_BRK_NUM_Msk = 0xff + + // IDLE_CONF: Frame-end idle configuration + // Position of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Pos = 0x0 + // Bit mask of RX_IDLE_THRHD field. + UART_IDLE_CONF_RX_IDLE_THRHD_Msk = 0x3ff + // Position of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Pos = 0xa + // Bit mask of TX_IDLE_NUM field. + UART_IDLE_CONF_TX_IDLE_NUM_Msk = 0xffc00 + + // RS485_CONF: RS485 mode configuration + // Position of RS485_EN field. + UART_RS485_CONF_RS485_EN_Pos = 0x0 + // Bit mask of RS485_EN field. + UART_RS485_CONF_RS485_EN_Msk = 0x1 + // Bit RS485_EN. + UART_RS485_CONF_RS485_EN = 0x1 + // Position of DL0_EN field. + UART_RS485_CONF_DL0_EN_Pos = 0x1 + // Bit mask of DL0_EN field. + UART_RS485_CONF_DL0_EN_Msk = 0x2 + // Bit DL0_EN. + UART_RS485_CONF_DL0_EN = 0x2 + // Position of DL1_EN field. + UART_RS485_CONF_DL1_EN_Pos = 0x2 + // Bit mask of DL1_EN field. + UART_RS485_CONF_DL1_EN_Msk = 0x4 + // Bit DL1_EN. + UART_RS485_CONF_DL1_EN = 0x4 + // Position of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Pos = 0x3 + // Bit mask of RS485TX_RX_EN field. + UART_RS485_CONF_RS485TX_RX_EN_Msk = 0x8 + // Bit RS485TX_RX_EN. + UART_RS485_CONF_RS485TX_RX_EN = 0x8 + // Position of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Pos = 0x4 + // Bit mask of RS485RXBY_TX_EN field. + UART_RS485_CONF_RS485RXBY_TX_EN_Msk = 0x10 + // Bit RS485RXBY_TX_EN. + UART_RS485_CONF_RS485RXBY_TX_EN = 0x10 + // Position of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Pos = 0x5 + // Bit mask of RS485_RX_DLY_NUM field. + UART_RS485_CONF_RS485_RX_DLY_NUM_Msk = 0x20 + // Bit RS485_RX_DLY_NUM. + UART_RS485_CONF_RS485_RX_DLY_NUM = 0x20 + // Position of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Pos = 0x6 + // Bit mask of RS485_TX_DLY_NUM field. + UART_RS485_CONF_RS485_TX_DLY_NUM_Msk = 0x3c0 + + // AT_CMD_PRECNT: Pre-sequence timing configuration + // Position of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Pos = 0x0 + // Bit mask of PRE_IDLE_NUM field. + UART_AT_CMD_PRECNT_PRE_IDLE_NUM_Msk = 0xffff + + // AT_CMD_POSTCNT: Post-sequence timing configuration + // Position of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Pos = 0x0 + // Bit mask of POST_IDLE_NUM field. + UART_AT_CMD_POSTCNT_POST_IDLE_NUM_Msk = 0xffff + + // AT_CMD_GAPTOUT: Timeout configuration + // Position of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Pos = 0x0 + // Bit mask of RX_GAP_TOUT field. + UART_AT_CMD_GAPTOUT_RX_GAP_TOUT_Msk = 0xffff + + // AT_CMD_CHAR: AT escape sequence detection configuration + // Position of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Pos = 0x0 + // Bit mask of AT_CMD_CHAR field. + UART_AT_CMD_CHAR_AT_CMD_CHAR_Msk = 0xff + // Position of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Pos = 0x8 + // Bit mask of CHAR_NUM field. + UART_AT_CMD_CHAR_CHAR_NUM_Msk = 0xff00 + + // MEM_CONF: UART threshold and allocation configuration + // Position of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Pos = 0x1 + // Bit mask of RX_SIZE field. + UART_MEM_CONF_RX_SIZE_Msk = 0xe + // Position of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Pos = 0x4 + // Bit mask of TX_SIZE field. + UART_MEM_CONF_TX_SIZE_Msk = 0x70 + // Position of RX_FLOW_THRHD field. + UART_MEM_CONF_RX_FLOW_THRHD_Pos = 0x7 + // Bit mask of RX_FLOW_THRHD field. + UART_MEM_CONF_RX_FLOW_THRHD_Msk = 0x1ff80 + // Position of RX_TOUT_THRHD field. + UART_MEM_CONF_RX_TOUT_THRHD_Pos = 0x11 + // Bit mask of RX_TOUT_THRHD field. + UART_MEM_CONF_RX_TOUT_THRHD_Msk = 0x7fe0000 + // Position of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x1b + // Bit mask of MEM_FORCE_PD field. + UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x8000000 + // Bit MEM_FORCE_PD. + UART_MEM_CONF_MEM_FORCE_PD = 0x8000000 + // Position of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1c + // Bit mask of MEM_FORCE_PU field. + UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x10000000 + // Bit MEM_FORCE_PU. + UART_MEM_CONF_MEM_FORCE_PU = 0x10000000 + + // MEM_TX_STATUS: Tx-FIFO write and read offset address. + // Position of APB_TX_WADDR field. + UART_MEM_TX_STATUS_APB_TX_WADDR_Pos = 0x0 + // Bit mask of APB_TX_WADDR field. + UART_MEM_TX_STATUS_APB_TX_WADDR_Msk = 0x3ff + // Position of TX_RADDR field. + UART_MEM_TX_STATUS_TX_RADDR_Pos = 0xb + // Bit mask of TX_RADDR field. + UART_MEM_TX_STATUS_TX_RADDR_Msk = 0x1ff800 + + // MEM_RX_STATUS: Rx-FIFO write and read offset address. + // Position of APB_RX_RADDR field. + UART_MEM_RX_STATUS_APB_RX_RADDR_Pos = 0x0 + // Bit mask of APB_RX_RADDR field. + UART_MEM_RX_STATUS_APB_RX_RADDR_Msk = 0x3ff + // Position of RX_WADDR field. + UART_MEM_RX_STATUS_RX_WADDR_Pos = 0xb + // Bit mask of RX_WADDR field. + UART_MEM_RX_STATUS_RX_WADDR_Msk = 0x1ff800 + + // FSM_STATUS: UART transmit and receive status. + // Position of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0 + // Bit mask of ST_URX_OUT field. + UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf + // Position of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4 + // Bit mask of ST_UTX_OUT field. + UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0 + + // POSPULSE: Autobaud high pulse register + // Position of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of POSEDGE_MIN_CNT field. + UART_POSPULSE_POSEDGE_MIN_CNT_Msk = 0xfff + + // NEGPULSE: Autobaud low pulse register + // Position of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Pos = 0x0 + // Bit mask of NEGEDGE_MIN_CNT field. + UART_NEGPULSE_NEGEDGE_MIN_CNT_Msk = 0xfff + + // CLK_CONF: UART core clock configuration + // Position of SCLK_DIV_B field. + UART_CLK_CONF_SCLK_DIV_B_Pos = 0x0 + // Bit mask of SCLK_DIV_B field. + UART_CLK_CONF_SCLK_DIV_B_Msk = 0x3f + // Position of SCLK_DIV_A field. + UART_CLK_CONF_SCLK_DIV_A_Pos = 0x6 + // Bit mask of SCLK_DIV_A field. + UART_CLK_CONF_SCLK_DIV_A_Msk = 0xfc0 + // Position of SCLK_DIV_NUM field. + UART_CLK_CONF_SCLK_DIV_NUM_Pos = 0xc + // Bit mask of SCLK_DIV_NUM field. + UART_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff000 + // Position of SCLK_SEL field. + UART_CLK_CONF_SCLK_SEL_Pos = 0x14 + // Bit mask of SCLK_SEL field. + UART_CLK_CONF_SCLK_SEL_Msk = 0x300000 + // Position of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Pos = 0x16 + // Bit mask of SCLK_EN field. + UART_CLK_CONF_SCLK_EN_Msk = 0x400000 + // Bit SCLK_EN. + UART_CLK_CONF_SCLK_EN = 0x400000 + // Position of RST_CORE field. + UART_CLK_CONF_RST_CORE_Pos = 0x17 + // Bit mask of RST_CORE field. + UART_CLK_CONF_RST_CORE_Msk = 0x800000 + // Bit RST_CORE. + UART_CLK_CONF_RST_CORE = 0x800000 + // Position of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Pos = 0x18 + // Bit mask of TX_SCLK_EN field. + UART_CLK_CONF_TX_SCLK_EN_Msk = 0x1000000 + // Bit TX_SCLK_EN. + UART_CLK_CONF_TX_SCLK_EN = 0x1000000 + // Position of RX_SCLK_EN field. + UART_CLK_CONF_RX_SCLK_EN_Pos = 0x19 + // Bit mask of RX_SCLK_EN field. + UART_CLK_CONF_RX_SCLK_EN_Msk = 0x2000000 + // Bit RX_SCLK_EN. + UART_CLK_CONF_RX_SCLK_EN = 0x2000000 + // Position of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Pos = 0x1a + // Bit mask of TX_RST_CORE field. + UART_CLK_CONF_TX_RST_CORE_Msk = 0x4000000 + // Bit TX_RST_CORE. + UART_CLK_CONF_TX_RST_CORE = 0x4000000 + // Position of RX_RST_CORE field. + UART_CLK_CONF_RX_RST_CORE_Pos = 0x1b + // Bit mask of RX_RST_CORE field. + UART_CLK_CONF_RX_RST_CORE_Msk = 0x8000000 + // Bit RX_RST_CORE. + UART_CLK_CONF_RX_RST_CORE = 0x8000000 + + // DATE: UART Version register + // Position of DATE field. + UART_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UART_DATE_DATE_Msk = 0xffffffff + + // ID: UART ID register + // Position of ID field. + UART_ID_ID_Pos = 0x0 + // Bit mask of ID field. + UART_ID_ID_Msk = 0x3fffffff + // Position of HIGH_SPEED field. + UART_ID_HIGH_SPEED_Pos = 0x1e + // Bit mask of HIGH_SPEED field. + UART_ID_HIGH_SPEED_Msk = 0x40000000 + // Bit HIGH_SPEED. + UART_ID_HIGH_SPEED = 0x40000000 + // Position of REG_UPDATE field. + UART_ID_REG_UPDATE_Pos = 0x1f + // Bit mask of REG_UPDATE field. + UART_ID_REG_UPDATE_Msk = 0x80000000 + // Bit REG_UPDATE. + UART_ID_REG_UPDATE = 0x80000000 +) + +// Constants for UHCI0: Universal Host Controller Interface 0 +const ( + // CONF0: UHCI configuration register + // Position of TX_RST field. + UHCI_CONF0_TX_RST_Pos = 0x0 + // Bit mask of TX_RST field. + UHCI_CONF0_TX_RST_Msk = 0x1 + // Bit TX_RST. + UHCI_CONF0_TX_RST = 0x1 + // Position of RX_RST field. + UHCI_CONF0_RX_RST_Pos = 0x1 + // Bit mask of RX_RST field. + UHCI_CONF0_RX_RST_Msk = 0x2 + // Bit RX_RST. + UHCI_CONF0_RX_RST = 0x2 + // Position of UART0_CE field. + UHCI_CONF0_UART0_CE_Pos = 0x2 + // Bit mask of UART0_CE field. + UHCI_CONF0_UART0_CE_Msk = 0x4 + // Bit UART0_CE. + UHCI_CONF0_UART0_CE = 0x4 + // Position of UART1_CE field. + UHCI_CONF0_UART1_CE_Pos = 0x3 + // Bit mask of UART1_CE field. + UHCI_CONF0_UART1_CE_Msk = 0x8 + // Bit UART1_CE. + UHCI_CONF0_UART1_CE = 0x8 + // Position of UART2_CE field. + UHCI_CONF0_UART2_CE_Pos = 0x4 + // Bit mask of UART2_CE field. + UHCI_CONF0_UART2_CE_Msk = 0x10 + // Bit UART2_CE. + UHCI_CONF0_UART2_CE = 0x10 + // Position of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Pos = 0x5 + // Bit mask of SEPER_EN field. + UHCI_CONF0_SEPER_EN_Msk = 0x20 + // Bit SEPER_EN. + UHCI_CONF0_SEPER_EN = 0x20 + // Position of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Pos = 0x6 + // Bit mask of HEAD_EN field. + UHCI_CONF0_HEAD_EN_Msk = 0x40 + // Bit HEAD_EN. + UHCI_CONF0_HEAD_EN = 0x40 + // Position of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Pos = 0x7 + // Bit mask of CRC_REC_EN field. + UHCI_CONF0_CRC_REC_EN_Msk = 0x80 + // Bit CRC_REC_EN. + UHCI_CONF0_CRC_REC_EN = 0x80 + // Position of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Pos = 0x8 + // Bit mask of UART_IDLE_EOF_EN field. + UHCI_CONF0_UART_IDLE_EOF_EN_Msk = 0x100 + // Bit UART_IDLE_EOF_EN. + UHCI_CONF0_UART_IDLE_EOF_EN = 0x100 + // Position of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Pos = 0x9 + // Bit mask of LEN_EOF_EN field. + UHCI_CONF0_LEN_EOF_EN_Msk = 0x200 + // Bit LEN_EOF_EN. + UHCI_CONF0_LEN_EOF_EN = 0x200 + // Position of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Pos = 0xa + // Bit mask of ENCODE_CRC_EN field. + UHCI_CONF0_ENCODE_CRC_EN_Msk = 0x400 + // Bit ENCODE_CRC_EN. + UHCI_CONF0_ENCODE_CRC_EN = 0x400 + // Position of CLK_EN field. + UHCI_CONF0_CLK_EN_Pos = 0xb + // Bit mask of CLK_EN field. + UHCI_CONF0_CLK_EN_Msk = 0x800 + // Bit CLK_EN. + UHCI_CONF0_CLK_EN = 0x800 + // Position of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Pos = 0xc + // Bit mask of UART_RX_BRK_EOF_EN field. + UHCI_CONF0_UART_RX_BRK_EOF_EN_Msk = 0x1000 + // Bit UART_RX_BRK_EOF_EN. + UHCI_CONF0_UART_RX_BRK_EOF_EN = 0x1000 + + // INT_RAW: Raw interrupt status + // Position of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Pos = 0x0 + // Bit mask of RX_START_INT_RAW field. + UHCI_INT_RAW_RX_START_INT_RAW_Msk = 0x1 + // Bit RX_START_INT_RAW. + UHCI_INT_RAW_RX_START_INT_RAW = 0x1 + // Position of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Pos = 0x1 + // Bit mask of TX_START_INT_RAW field. + UHCI_INT_RAW_TX_START_INT_RAW_Msk = 0x2 + // Bit TX_START_INT_RAW. + UHCI_INT_RAW_TX_START_INT_RAW = 0x2 + // Position of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2 + // Bit mask of RX_HUNG_INT_RAW field. + UHCI_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4 + // Bit RX_HUNG_INT_RAW. + UHCI_INT_RAW_RX_HUNG_INT_RAW = 0x4 + // Position of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3 + // Bit mask of TX_HUNG_INT_RAW field. + UHCI_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8 + // Bit TX_HUNG_INT_RAW. + UHCI_INT_RAW_TX_HUNG_INT_RAW = 0x8 + // Position of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW = 0x10 + // Position of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_RAW field. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_RAW. + UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW = 0x20 + // Position of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x6 + // Bit mask of OUT_EOF_INT_RAW field. + UHCI_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x40 + // Bit OUT_EOF_INT_RAW. + UHCI_INT_RAW_OUT_EOF_INT_RAW = 0x40 + // Position of APP_CTRL0_INT_RAW field. + UHCI_INT_RAW_APP_CTRL0_INT_RAW_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_RAW field. + UHCI_INT_RAW_APP_CTRL0_INT_RAW_Msk = 0x80 + // Bit APP_CTRL0_INT_RAW. + UHCI_INT_RAW_APP_CTRL0_INT_RAW = 0x80 + // Position of APP_CTRL1_INT_RAW field. + UHCI_INT_RAW_APP_CTRL1_INT_RAW_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_RAW field. + UHCI_INT_RAW_APP_CTRL1_INT_RAW_Msk = 0x100 + // Bit APP_CTRL1_INT_RAW. + UHCI_INT_RAW_APP_CTRL1_INT_RAW = 0x100 + + // INT_ST: Masked interrupt status + // Position of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Pos = 0x0 + // Bit mask of RX_START_INT_ST field. + UHCI_INT_ST_RX_START_INT_ST_Msk = 0x1 + // Bit RX_START_INT_ST. + UHCI_INT_ST_RX_START_INT_ST = 0x1 + // Position of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Pos = 0x1 + // Bit mask of TX_START_INT_ST field. + UHCI_INT_ST_TX_START_INT_ST_Msk = 0x2 + // Bit TX_START_INT_ST. + UHCI_INT_ST_TX_START_INT_ST = 0x2 + // Position of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ST field. + UHCI_INT_ST_RX_HUNG_INT_ST_Msk = 0x4 + // Bit RX_HUNG_INT_ST. + UHCI_INT_ST_RX_HUNG_INT_ST = 0x4 + // Position of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ST field. + UHCI_INT_ST_TX_HUNG_INT_ST_Msk = 0x8 + // Bit TX_HUNG_INT_ST. + UHCI_INT_ST_TX_HUNG_INT_ST = 0x8 + // Position of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_ST. + UHCI_INT_ST_SEND_S_REG_Q_INT_ST = 0x10 + // Position of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_ST field. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_ST. + UHCI_INT_ST_SEND_A_REG_Q_INT_ST = 0x20 + // Position of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_ST field. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_ST. + UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST = 0x40 + // Position of APP_CTRL0_INT_ST field. + UHCI_INT_ST_APP_CTRL0_INT_ST_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_ST field. + UHCI_INT_ST_APP_CTRL0_INT_ST_Msk = 0x80 + // Bit APP_CTRL0_INT_ST. + UHCI_INT_ST_APP_CTRL0_INT_ST = 0x80 + // Position of APP_CTRL1_INT_ST field. + UHCI_INT_ST_APP_CTRL1_INT_ST_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_ST field. + UHCI_INT_ST_APP_CTRL1_INT_ST_Msk = 0x100 + // Bit APP_CTRL1_INT_ST. + UHCI_INT_ST_APP_CTRL1_INT_ST = 0x100 + + // INT_ENA: Interrupt enable bits + // Position of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Pos = 0x0 + // Bit mask of RX_START_INT_ENA field. + UHCI_INT_ENA_RX_START_INT_ENA_Msk = 0x1 + // Bit RX_START_INT_ENA. + UHCI_INT_ENA_RX_START_INT_ENA = 0x1 + // Position of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Pos = 0x1 + // Bit mask of TX_START_INT_ENA field. + UHCI_INT_ENA_TX_START_INT_ENA_Msk = 0x2 + // Bit TX_START_INT_ENA. + UHCI_INT_ENA_TX_START_INT_ENA = 0x2 + // Position of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2 + // Bit mask of RX_HUNG_INT_ENA field. + UHCI_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4 + // Bit RX_HUNG_INT_ENA. + UHCI_INT_ENA_RX_HUNG_INT_ENA = 0x4 + // Position of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3 + // Bit mask of TX_HUNG_INT_ENA field. + UHCI_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8 + // Bit TX_HUNG_INT_ENA. + UHCI_INT_ENA_TX_HUNG_INT_ENA = 0x8 + // Position of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA = 0x10 + // Position of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_ENA field. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_ENA. + UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA = 0x20 + // Position of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_ENA field. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_ENA. + UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA = 0x40 + // Position of APP_CTRL0_INT_ENA field. + UHCI_INT_ENA_APP_CTRL0_INT_ENA_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_ENA field. + UHCI_INT_ENA_APP_CTRL0_INT_ENA_Msk = 0x80 + // Bit APP_CTRL0_INT_ENA. + UHCI_INT_ENA_APP_CTRL0_INT_ENA = 0x80 + // Position of APP_CTRL1_INT_ENA field. + UHCI_INT_ENA_APP_CTRL1_INT_ENA_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_ENA field. + UHCI_INT_ENA_APP_CTRL1_INT_ENA_Msk = 0x100 + // Bit APP_CTRL1_INT_ENA. + UHCI_INT_ENA_APP_CTRL1_INT_ENA = 0x100 + + // INT_CLR: Interrupt clear bits + // Position of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Pos = 0x0 + // Bit mask of RX_START_INT_CLR field. + UHCI_INT_CLR_RX_START_INT_CLR_Msk = 0x1 + // Bit RX_START_INT_CLR. + UHCI_INT_CLR_RX_START_INT_CLR = 0x1 + // Position of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Pos = 0x1 + // Bit mask of TX_START_INT_CLR field. + UHCI_INT_CLR_TX_START_INT_CLR_Msk = 0x2 + // Bit TX_START_INT_CLR. + UHCI_INT_CLR_TX_START_INT_CLR = 0x2 + // Position of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2 + // Bit mask of RX_HUNG_INT_CLR field. + UHCI_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4 + // Bit RX_HUNG_INT_CLR. + UHCI_INT_CLR_RX_HUNG_INT_CLR = 0x4 + // Position of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3 + // Bit mask of TX_HUNG_INT_CLR field. + UHCI_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8 + // Bit TX_HUNG_INT_CLR. + UHCI_INT_CLR_TX_HUNG_INT_CLR = 0x8 + // Position of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Pos = 0x4 + // Bit mask of SEND_S_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Msk = 0x10 + // Bit SEND_S_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR = 0x10 + // Position of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Pos = 0x5 + // Bit mask of SEND_A_REG_Q_INT_CLR field. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Msk = 0x20 + // Bit SEND_A_REG_Q_INT_CLR. + UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR = 0x20 + // Position of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Pos = 0x6 + // Bit mask of OUTLINK_EOF_ERR_INT_CLR field. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Msk = 0x40 + // Bit OUTLINK_EOF_ERR_INT_CLR. + UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR = 0x40 + // Position of APP_CTRL0_INT_CLR field. + UHCI_INT_CLR_APP_CTRL0_INT_CLR_Pos = 0x7 + // Bit mask of APP_CTRL0_INT_CLR field. + UHCI_INT_CLR_APP_CTRL0_INT_CLR_Msk = 0x80 + // Bit APP_CTRL0_INT_CLR. + UHCI_INT_CLR_APP_CTRL0_INT_CLR = 0x80 + // Position of APP_CTRL1_INT_CLR field. + UHCI_INT_CLR_APP_CTRL1_INT_CLR_Pos = 0x8 + // Bit mask of APP_CTRL1_INT_CLR field. + UHCI_INT_CLR_APP_CTRL1_INT_CLR_Msk = 0x100 + // Bit APP_CTRL1_INT_CLR. + UHCI_INT_CLR_APP_CTRL1_INT_CLR = 0x100 + + // APP_INT_SET: Software interrupt trigger source + // Position of APP_CTRL0_INT_SET field. + UHCI_APP_INT_SET_APP_CTRL0_INT_SET_Pos = 0x0 + // Bit mask of APP_CTRL0_INT_SET field. + UHCI_APP_INT_SET_APP_CTRL0_INT_SET_Msk = 0x1 + // Bit APP_CTRL0_INT_SET. + UHCI_APP_INT_SET_APP_CTRL0_INT_SET = 0x1 + // Position of APP_CTRL1_INT_SET field. + UHCI_APP_INT_SET_APP_CTRL1_INT_SET_Pos = 0x1 + // Bit mask of APP_CTRL1_INT_SET field. + UHCI_APP_INT_SET_APP_CTRL1_INT_SET_Msk = 0x2 + // Bit APP_CTRL1_INT_SET. + UHCI_APP_INT_SET_APP_CTRL1_INT_SET = 0x2 + + // CONF1: UHCI configuration register + // Position of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Pos = 0x0 + // Bit mask of CHECK_SUM_EN field. + UHCI_CONF1_CHECK_SUM_EN_Msk = 0x1 + // Bit CHECK_SUM_EN. + UHCI_CONF1_CHECK_SUM_EN = 0x1 + // Position of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Pos = 0x1 + // Bit mask of CHECK_SEQ_EN field. + UHCI_CONF1_CHECK_SEQ_EN_Msk = 0x2 + // Bit CHECK_SEQ_EN. + UHCI_CONF1_CHECK_SEQ_EN = 0x2 + // Position of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Pos = 0x2 + // Bit mask of CRC_DISABLE field. + UHCI_CONF1_CRC_DISABLE_Msk = 0x4 + // Bit CRC_DISABLE. + UHCI_CONF1_CRC_DISABLE = 0x4 + // Position of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Pos = 0x3 + // Bit mask of SAVE_HEAD field. + UHCI_CONF1_SAVE_HEAD_Msk = 0x8 + // Bit SAVE_HEAD. + UHCI_CONF1_SAVE_HEAD = 0x8 + // Position of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Pos = 0x4 + // Bit mask of TX_CHECK_SUM_RE field. + UHCI_CONF1_TX_CHECK_SUM_RE_Msk = 0x10 + // Bit TX_CHECK_SUM_RE. + UHCI_CONF1_TX_CHECK_SUM_RE = 0x10 + // Position of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Pos = 0x5 + // Bit mask of TX_ACK_NUM_RE field. + UHCI_CONF1_TX_ACK_NUM_RE_Msk = 0x20 + // Bit TX_ACK_NUM_RE. + UHCI_CONF1_TX_ACK_NUM_RE = 0x20 + // Position of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Pos = 0x7 + // Bit mask of WAIT_SW_START field. + UHCI_CONF1_WAIT_SW_START_Msk = 0x80 + // Bit WAIT_SW_START. + UHCI_CONF1_WAIT_SW_START = 0x80 + // Position of SW_START field. + UHCI_CONF1_SW_START_Pos = 0x8 + // Bit mask of SW_START field. + UHCI_CONF1_SW_START_Msk = 0x100 + // Bit SW_START. + UHCI_CONF1_SW_START = 0x100 + + // STATE0: UHCI receive status + // Position of RX_ERR_CAUSE field. + UHCI_STATE0_RX_ERR_CAUSE_Pos = 0x0 + // Bit mask of RX_ERR_CAUSE field. + UHCI_STATE0_RX_ERR_CAUSE_Msk = 0x7 + // Position of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Pos = 0x3 + // Bit mask of DECODE_STATE field. + UHCI_STATE0_DECODE_STATE_Msk = 0x38 + + // STATE1: UHCI transmit status + // Position of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Pos = 0x0 + // Bit mask of ENCODE_STATE field. + UHCI_STATE1_ENCODE_STATE_Msk = 0x7 + + // ESCAPE_CONF: Escape character configuration + // Position of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Pos = 0x0 + // Bit mask of TX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Msk = 0x1 + // Bit TX_C0_ESC_EN. + UHCI_ESCAPE_CONF_TX_C0_ESC_EN = 0x1 + // Position of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Pos = 0x1 + // Bit mask of TX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Msk = 0x2 + // Bit TX_DB_ESC_EN. + UHCI_ESCAPE_CONF_TX_DB_ESC_EN = 0x2 + // Position of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Pos = 0x2 + // Bit mask of TX_11_ESC_EN field. + UHCI_ESCAPE_CONF_TX_11_ESC_EN_Msk = 0x4 + // Bit TX_11_ESC_EN. + UHCI_ESCAPE_CONF_TX_11_ESC_EN = 0x4 + // Position of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Pos = 0x3 + // Bit mask of TX_13_ESC_EN field. + UHCI_ESCAPE_CONF_TX_13_ESC_EN_Msk = 0x8 + // Bit TX_13_ESC_EN. + UHCI_ESCAPE_CONF_TX_13_ESC_EN = 0x8 + // Position of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Pos = 0x4 + // Bit mask of RX_C0_ESC_EN field. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Msk = 0x10 + // Bit RX_C0_ESC_EN. + UHCI_ESCAPE_CONF_RX_C0_ESC_EN = 0x10 + // Position of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Pos = 0x5 + // Bit mask of RX_DB_ESC_EN field. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Msk = 0x20 + // Bit RX_DB_ESC_EN. + UHCI_ESCAPE_CONF_RX_DB_ESC_EN = 0x20 + // Position of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Pos = 0x6 + // Bit mask of RX_11_ESC_EN field. + UHCI_ESCAPE_CONF_RX_11_ESC_EN_Msk = 0x40 + // Bit RX_11_ESC_EN. + UHCI_ESCAPE_CONF_RX_11_ESC_EN = 0x40 + // Position of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Pos = 0x7 + // Bit mask of RX_13_ESC_EN field. + UHCI_ESCAPE_CONF_RX_13_ESC_EN_Msk = 0x80 + // Bit RX_13_ESC_EN. + UHCI_ESCAPE_CONF_RX_13_ESC_EN = 0x80 + + // HUNG_CONF: Timeout configuration + // Position of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Pos = 0x0 + // Bit mask of TXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Msk = 0xff + // Position of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Pos = 0x8 + // Bit mask of TXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Msk = 0x700 + // Position of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Pos = 0xb + // Bit mask of TXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Msk = 0x800 + // Bit TXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA = 0x800 + // Position of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Pos = 0xc + // Bit mask of RXFIFO_TIMEOUT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Msk = 0xff000 + // Position of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Pos = 0x14 + // Bit mask of RXFIFO_TIMEOUT_SHIFT field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Msk = 0x700000 + // Position of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Pos = 0x17 + // Bit mask of RXFIFO_TIMEOUT_ENA field. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Msk = 0x800000 + // Bit RXFIFO_TIMEOUT_ENA. + UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA = 0x800000 + + // ACK_NUM: UHCI ACK number configuration + // Position of ACK_NUM field. + UHCI_ACK_NUM_ACK_NUM_Pos = 0x0 + // Bit mask of ACK_NUM field. + UHCI_ACK_NUM_ACK_NUM_Msk = 0x7 + // Position of LOAD field. + UHCI_ACK_NUM_LOAD_Pos = 0x3 + // Bit mask of LOAD field. + UHCI_ACK_NUM_LOAD_Msk = 0x8 + // Bit LOAD. + UHCI_ACK_NUM_LOAD = 0x8 + + // RX_HEAD: UHCI packet header register + // Position of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Pos = 0x0 + // Bit mask of RX_HEAD field. + UHCI_RX_HEAD_RX_HEAD_Msk = 0xffffffff + + // QUICK_SENT: UHCI quick send configuration register + // Position of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Pos = 0x0 + // Bit mask of SINGLE_SEND_NUM field. + UHCI_QUICK_SENT_SINGLE_SEND_NUM_Msk = 0x7 + // Position of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Pos = 0x3 + // Bit mask of SINGLE_SEND_EN field. + UHCI_QUICK_SENT_SINGLE_SEND_EN_Msk = 0x8 + // Bit SINGLE_SEND_EN. + UHCI_QUICK_SENT_SINGLE_SEND_EN = 0x8 + // Position of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Pos = 0x4 + // Bit mask of ALWAYS_SEND_NUM field. + UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Msk = 0x70 + // Position of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Pos = 0x7 + // Bit mask of ALWAYS_SEND_EN field. + UHCI_QUICK_SENT_ALWAYS_SEND_EN_Msk = 0x80 + // Bit ALWAYS_SEND_EN. + UHCI_QUICK_SENT_ALWAYS_SEND_EN = 0x80 + + // REG_Q0_WORD0: Q0_WORD0 quick_sent register + // Position of SEND_Q0_WORD0 field. + UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Pos = 0x0 + // Bit mask of SEND_Q0_WORD0 field. + UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Msk = 0xffffffff + + // REG_Q0_WORD1: Q0_WORD1 quick_sent register + // Position of SEND_Q0_WORD1 field. + UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Pos = 0x0 + // Bit mask of SEND_Q0_WORD1 field. + UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Msk = 0xffffffff + + // REG_Q1_WORD0: Q1_WORD0 quick_sent register + // Position of SEND_Q1_WORD0 field. + UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Pos = 0x0 + // Bit mask of SEND_Q1_WORD0 field. + UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Msk = 0xffffffff + + // REG_Q1_WORD1: Q1_WORD1 quick_sent register + // Position of SEND_Q1_WORD1 field. + UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Pos = 0x0 + // Bit mask of SEND_Q1_WORD1 field. + UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Msk = 0xffffffff + + // REG_Q2_WORD0: Q2_WORD0 quick_sent register + // Position of SEND_Q2_WORD0 field. + UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Pos = 0x0 + // Bit mask of SEND_Q2_WORD0 field. + UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Msk = 0xffffffff + + // REG_Q2_WORD1: Q2_WORD1 quick_sent register + // Position of SEND_Q2_WORD1 field. + UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Pos = 0x0 + // Bit mask of SEND_Q2_WORD1 field. + UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Msk = 0xffffffff + + // REG_Q3_WORD0: Q3_WORD0 quick_sent register + // Position of SEND_Q3_WORD0 field. + UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Pos = 0x0 + // Bit mask of SEND_Q3_WORD0 field. + UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Msk = 0xffffffff + + // REG_Q3_WORD1: Q3_WORD1 quick_sent register + // Position of SEND_Q3_WORD1 field. + UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Pos = 0x0 + // Bit mask of SEND_Q3_WORD1 field. + UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Msk = 0xffffffff + + // REG_Q4_WORD0: Q4_WORD0 quick_sent register + // Position of SEND_Q4_WORD0 field. + UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Pos = 0x0 + // Bit mask of SEND_Q4_WORD0 field. + UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Msk = 0xffffffff + + // REG_Q4_WORD1: Q4_WORD1 quick_sent register + // Position of SEND_Q4_WORD1 field. + UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Pos = 0x0 + // Bit mask of SEND_Q4_WORD1 field. + UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Msk = 0xffffffff + + // REG_Q5_WORD0: Q5_WORD0 quick_sent register + // Position of SEND_Q5_WORD0 field. + UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Pos = 0x0 + // Bit mask of SEND_Q5_WORD0 field. + UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Msk = 0xffffffff + + // REG_Q5_WORD1: Q5_WORD1 quick_sent register + // Position of SEND_Q5_WORD1 field. + UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Pos = 0x0 + // Bit mask of SEND_Q5_WORD1 field. + UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Msk = 0xffffffff + + // REG_Q6_WORD0: Q6_WORD0 quick_sent register + // Position of SEND_Q6_WORD0 field. + UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Pos = 0x0 + // Bit mask of SEND_Q6_WORD0 field. + UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Msk = 0xffffffff + + // REG_Q6_WORD1: Q6_WORD1 quick_sent register + // Position of SEND_Q6_WORD1 field. + UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Pos = 0x0 + // Bit mask of SEND_Q6_WORD1 field. + UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Msk = 0xffffffff + + // ESC_CONF0: Escape sequence configuration register 0 + // Position of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Pos = 0x0 + // Bit mask of SEPER_CHAR field. + UHCI_ESC_CONF0_SEPER_CHAR_Msk = 0xff + // Position of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Pos = 0x8 + // Bit mask of SEPER_ESC_CHAR0 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Msk = 0xff00 + // Position of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Pos = 0x10 + // Bit mask of SEPER_ESC_CHAR1 field. + UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Msk = 0xff0000 + + // ESC_CONF1: Escape sequence configuration register 1 + // Position of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Pos = 0x0 + // Bit mask of ESC_SEQ0 field. + UHCI_ESC_CONF1_ESC_SEQ0_Msk = 0xff + // Position of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ0_CHAR0 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ0_CHAR1 field. + UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Msk = 0xff0000 + + // ESC_CONF2: Escape sequence configuration register 2 + // Position of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Pos = 0x0 + // Bit mask of ESC_SEQ1 field. + UHCI_ESC_CONF2_ESC_SEQ1_Msk = 0xff + // Position of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ1_CHAR0 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ1_CHAR1 field. + UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Msk = 0xff0000 + + // ESC_CONF3: Escape sequence configuration register 3 + // Position of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Pos = 0x0 + // Bit mask of ESC_SEQ2 field. + UHCI_ESC_CONF3_ESC_SEQ2_Msk = 0xff + // Position of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Pos = 0x8 + // Bit mask of ESC_SEQ2_CHAR0 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Msk = 0xff00 + // Position of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Pos = 0x10 + // Bit mask of ESC_SEQ2_CHAR1 field. + UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Msk = 0xff0000 + + // PKT_THRES: Configure register for packet length + // Position of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Pos = 0x0 + // Bit mask of PKT_THRS field. + UHCI_PKT_THRES_PKT_THRS_Msk = 0x1fff + + // DATE: UHCI version control register + // Position of DATE field. + UHCI_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + UHCI_DATE_DATE_Msk = 0xffffffff +) + +// Constants for USB0: USB OTG (On-The-Go) +const ( + // GOTGCTL + // Position of SESREQSCS field. + USB_GOTGCTL_SESREQSCS_Pos = 0x0 + // Bit mask of SESREQSCS field. + USB_GOTGCTL_SESREQSCS_Msk = 0x1 + // Bit SESREQSCS. + USB_GOTGCTL_SESREQSCS = 0x1 + // Position of SESREQ field. + USB_GOTGCTL_SESREQ_Pos = 0x1 + // Bit mask of SESREQ field. + USB_GOTGCTL_SESREQ_Msk = 0x2 + // Bit SESREQ. + USB_GOTGCTL_SESREQ = 0x2 + // Position of VBVALIDOVEN field. + USB_GOTGCTL_VBVALIDOVEN_Pos = 0x2 + // Bit mask of VBVALIDOVEN field. + USB_GOTGCTL_VBVALIDOVEN_Msk = 0x4 + // Bit VBVALIDOVEN. + USB_GOTGCTL_VBVALIDOVEN = 0x4 + // Position of VBVALIDOVVAL field. + USB_GOTGCTL_VBVALIDOVVAL_Pos = 0x3 + // Bit mask of VBVALIDOVVAL field. + USB_GOTGCTL_VBVALIDOVVAL_Msk = 0x8 + // Bit VBVALIDOVVAL. + USB_GOTGCTL_VBVALIDOVVAL = 0x8 + // Position of AVALIDOVEN field. + USB_GOTGCTL_AVALIDOVEN_Pos = 0x4 + // Bit mask of AVALIDOVEN field. + USB_GOTGCTL_AVALIDOVEN_Msk = 0x10 + // Bit AVALIDOVEN. + USB_GOTGCTL_AVALIDOVEN = 0x10 + // Position of AVALIDOVVAL field. + USB_GOTGCTL_AVALIDOVVAL_Pos = 0x5 + // Bit mask of AVALIDOVVAL field. + USB_GOTGCTL_AVALIDOVVAL_Msk = 0x20 + // Bit AVALIDOVVAL. + USB_GOTGCTL_AVALIDOVVAL = 0x20 + // Position of BVALIDOVEN field. + USB_GOTGCTL_BVALIDOVEN_Pos = 0x6 + // Bit mask of BVALIDOVEN field. + USB_GOTGCTL_BVALIDOVEN_Msk = 0x40 + // Bit BVALIDOVEN. + USB_GOTGCTL_BVALIDOVEN = 0x40 + // Position of BVALIDOVVAL field. + USB_GOTGCTL_BVALIDOVVAL_Pos = 0x7 + // Bit mask of BVALIDOVVAL field. + USB_GOTGCTL_BVALIDOVVAL_Msk = 0x80 + // Bit BVALIDOVVAL. + USB_GOTGCTL_BVALIDOVVAL = 0x80 + // Position of HSTNEGSCS field. + USB_GOTGCTL_HSTNEGSCS_Pos = 0x8 + // Bit mask of HSTNEGSCS field. + USB_GOTGCTL_HSTNEGSCS_Msk = 0x100 + // Bit HSTNEGSCS. + USB_GOTGCTL_HSTNEGSCS = 0x100 + // Position of HNPREQ field. + USB_GOTGCTL_HNPREQ_Pos = 0x9 + // Bit mask of HNPREQ field. + USB_GOTGCTL_HNPREQ_Msk = 0x200 + // Bit HNPREQ. + USB_GOTGCTL_HNPREQ = 0x200 + // Position of HSTSETHNPEN field. + USB_GOTGCTL_HSTSETHNPEN_Pos = 0xa + // Bit mask of HSTSETHNPEN field. + USB_GOTGCTL_HSTSETHNPEN_Msk = 0x400 + // Bit HSTSETHNPEN. + USB_GOTGCTL_HSTSETHNPEN = 0x400 + // Position of DEVHNPEN field. + USB_GOTGCTL_DEVHNPEN_Pos = 0xb + // Bit mask of DEVHNPEN field. + USB_GOTGCTL_DEVHNPEN_Msk = 0x800 + // Bit DEVHNPEN. + USB_GOTGCTL_DEVHNPEN = 0x800 + // Position of EHEN field. + USB_GOTGCTL_EHEN_Pos = 0xc + // Bit mask of EHEN field. + USB_GOTGCTL_EHEN_Msk = 0x1000 + // Bit EHEN. + USB_GOTGCTL_EHEN = 0x1000 + // Position of DBNCEFLTRBYPASS field. + USB_GOTGCTL_DBNCEFLTRBYPASS_Pos = 0xf + // Bit mask of DBNCEFLTRBYPASS field. + USB_GOTGCTL_DBNCEFLTRBYPASS_Msk = 0x8000 + // Bit DBNCEFLTRBYPASS. + USB_GOTGCTL_DBNCEFLTRBYPASS = 0x8000 + // Position of CONIDSTS field. + USB_GOTGCTL_CONIDSTS_Pos = 0x10 + // Bit mask of CONIDSTS field. + USB_GOTGCTL_CONIDSTS_Msk = 0x10000 + // Bit CONIDSTS. + USB_GOTGCTL_CONIDSTS = 0x10000 + // Position of DBNCTIME field. + USB_GOTGCTL_DBNCTIME_Pos = 0x11 + // Bit mask of DBNCTIME field. + USB_GOTGCTL_DBNCTIME_Msk = 0x20000 + // Bit DBNCTIME. + USB_GOTGCTL_DBNCTIME = 0x20000 + // Position of ASESVLD field. + USB_GOTGCTL_ASESVLD_Pos = 0x12 + // Bit mask of ASESVLD field. + USB_GOTGCTL_ASESVLD_Msk = 0x40000 + // Bit ASESVLD. + USB_GOTGCTL_ASESVLD = 0x40000 + // Position of BSESVLD field. + USB_GOTGCTL_BSESVLD_Pos = 0x13 + // Bit mask of BSESVLD field. + USB_GOTGCTL_BSESVLD_Msk = 0x80000 + // Bit BSESVLD. + USB_GOTGCTL_BSESVLD = 0x80000 + // Position of OTGVER field. + USB_GOTGCTL_OTGVER_Pos = 0x14 + // Bit mask of OTGVER field. + USB_GOTGCTL_OTGVER_Msk = 0x100000 + // Bit OTGVER. + USB_GOTGCTL_OTGVER = 0x100000 + // Position of CURMOD field. + USB_GOTGCTL_CURMOD_Pos = 0x15 + // Bit mask of CURMOD field. + USB_GOTGCTL_CURMOD_Msk = 0x200000 + // Bit CURMOD. + USB_GOTGCTL_CURMOD = 0x200000 + + // GOTGINT + // Position of SESENDDET field. + USB_GOTGINT_SESENDDET_Pos = 0x2 + // Bit mask of SESENDDET field. + USB_GOTGINT_SESENDDET_Msk = 0x4 + // Bit SESENDDET. + USB_GOTGINT_SESENDDET = 0x4 + // Position of SESREQSUCSTSCHNG field. + USB_GOTGINT_SESREQSUCSTSCHNG_Pos = 0x8 + // Bit mask of SESREQSUCSTSCHNG field. + USB_GOTGINT_SESREQSUCSTSCHNG_Msk = 0x100 + // Bit SESREQSUCSTSCHNG. + USB_GOTGINT_SESREQSUCSTSCHNG = 0x100 + // Position of HSTNEGSUCSTSCHNG field. + USB_GOTGINT_HSTNEGSUCSTSCHNG_Pos = 0x9 + // Bit mask of HSTNEGSUCSTSCHNG field. + USB_GOTGINT_HSTNEGSUCSTSCHNG_Msk = 0x200 + // Bit HSTNEGSUCSTSCHNG. + USB_GOTGINT_HSTNEGSUCSTSCHNG = 0x200 + // Position of HSTNEGDET field. + USB_GOTGINT_HSTNEGDET_Pos = 0x11 + // Bit mask of HSTNEGDET field. + USB_GOTGINT_HSTNEGDET_Msk = 0x20000 + // Bit HSTNEGDET. + USB_GOTGINT_HSTNEGDET = 0x20000 + // Position of ADEVTOUTCHG field. + USB_GOTGINT_ADEVTOUTCHG_Pos = 0x12 + // Bit mask of ADEVTOUTCHG field. + USB_GOTGINT_ADEVTOUTCHG_Msk = 0x40000 + // Bit ADEVTOUTCHG. + USB_GOTGINT_ADEVTOUTCHG = 0x40000 + // Position of DBNCEDONE field. + USB_GOTGINT_DBNCEDONE_Pos = 0x13 + // Bit mask of DBNCEDONE field. + USB_GOTGINT_DBNCEDONE_Msk = 0x80000 + // Bit DBNCEDONE. + USB_GOTGINT_DBNCEDONE = 0x80000 + + // GAHBCFG + // Position of GLBLLNTRMSK field. + USB_GAHBCFG_GLBLLNTRMSK_Pos = 0x0 + // Bit mask of GLBLLNTRMSK field. + USB_GAHBCFG_GLBLLNTRMSK_Msk = 0x1 + // Bit GLBLLNTRMSK. + USB_GAHBCFG_GLBLLNTRMSK = 0x1 + // Position of HBSTLEN field. + USB_GAHBCFG_HBSTLEN_Pos = 0x1 + // Bit mask of HBSTLEN field. + USB_GAHBCFG_HBSTLEN_Msk = 0x1e + // Position of DMAEN field. + USB_GAHBCFG_DMAEN_Pos = 0x5 + // Bit mask of DMAEN field. + USB_GAHBCFG_DMAEN_Msk = 0x20 + // Bit DMAEN. + USB_GAHBCFG_DMAEN = 0x20 + // Position of NPTXFEMPLVL field. + USB_GAHBCFG_NPTXFEMPLVL_Pos = 0x7 + // Bit mask of NPTXFEMPLVL field. + USB_GAHBCFG_NPTXFEMPLVL_Msk = 0x80 + // Bit NPTXFEMPLVL. + USB_GAHBCFG_NPTXFEMPLVL = 0x80 + // Position of PTXFEMPLVL field. + USB_GAHBCFG_PTXFEMPLVL_Pos = 0x8 + // Bit mask of PTXFEMPLVL field. + USB_GAHBCFG_PTXFEMPLVL_Msk = 0x100 + // Bit PTXFEMPLVL. + USB_GAHBCFG_PTXFEMPLVL = 0x100 + // Position of REMMEMSUPP field. + USB_GAHBCFG_REMMEMSUPP_Pos = 0x15 + // Bit mask of REMMEMSUPP field. + USB_GAHBCFG_REMMEMSUPP_Msk = 0x200000 + // Bit REMMEMSUPP. + USB_GAHBCFG_REMMEMSUPP = 0x200000 + // Position of NOTIALLDMAWRIT field. + USB_GAHBCFG_NOTIALLDMAWRIT_Pos = 0x16 + // Bit mask of NOTIALLDMAWRIT field. + USB_GAHBCFG_NOTIALLDMAWRIT_Msk = 0x400000 + // Bit NOTIALLDMAWRIT. + USB_GAHBCFG_NOTIALLDMAWRIT = 0x400000 + // Position of AHBSINGLE field. + USB_GAHBCFG_AHBSINGLE_Pos = 0x17 + // Bit mask of AHBSINGLE field. + USB_GAHBCFG_AHBSINGLE_Msk = 0x800000 + // Bit AHBSINGLE. + USB_GAHBCFG_AHBSINGLE = 0x800000 + // Position of INVDESCENDIANESS field. + USB_GAHBCFG_INVDESCENDIANESS_Pos = 0x18 + // Bit mask of INVDESCENDIANESS field. + USB_GAHBCFG_INVDESCENDIANESS_Msk = 0x1000000 + // Bit INVDESCENDIANESS. + USB_GAHBCFG_INVDESCENDIANESS = 0x1000000 + + // GUSBCFG + // Position of TOUTCAL field. + USB_GUSBCFG_TOUTCAL_Pos = 0x0 + // Bit mask of TOUTCAL field. + USB_GUSBCFG_TOUTCAL_Msk = 0x7 + // Position of PHYIF field. + USB_GUSBCFG_PHYIF_Pos = 0x3 + // Bit mask of PHYIF field. + USB_GUSBCFG_PHYIF_Msk = 0x8 + // Bit PHYIF. + USB_GUSBCFG_PHYIF = 0x8 + // Position of ULPI_UTMI_SEL field. + USB_GUSBCFG_ULPI_UTMI_SEL_Pos = 0x4 + // Bit mask of ULPI_UTMI_SEL field. + USB_GUSBCFG_ULPI_UTMI_SEL_Msk = 0x10 + // Bit ULPI_UTMI_SEL. + USB_GUSBCFG_ULPI_UTMI_SEL = 0x10 + // Position of FSINTF field. + USB_GUSBCFG_FSINTF_Pos = 0x5 + // Bit mask of FSINTF field. + USB_GUSBCFG_FSINTF_Msk = 0x20 + // Bit FSINTF. + USB_GUSBCFG_FSINTF = 0x20 + // Position of PHYSEL field. + USB_GUSBCFG_PHYSEL_Pos = 0x6 + // Bit mask of PHYSEL field. + USB_GUSBCFG_PHYSEL_Msk = 0x40 + // Bit PHYSEL. + USB_GUSBCFG_PHYSEL = 0x40 + // Position of SRPCAP field. + USB_GUSBCFG_SRPCAP_Pos = 0x8 + // Bit mask of SRPCAP field. + USB_GUSBCFG_SRPCAP_Msk = 0x100 + // Bit SRPCAP. + USB_GUSBCFG_SRPCAP = 0x100 + // Position of HNPCAP field. + USB_GUSBCFG_HNPCAP_Pos = 0x9 + // Bit mask of HNPCAP field. + USB_GUSBCFG_HNPCAP_Msk = 0x200 + // Bit HNPCAP. + USB_GUSBCFG_HNPCAP = 0x200 + // Position of USBTRDTIM field. + USB_GUSBCFG_USBTRDTIM_Pos = 0xa + // Bit mask of USBTRDTIM field. + USB_GUSBCFG_USBTRDTIM_Msk = 0x3c00 + // Position of TERMSELDLPULSE field. + USB_GUSBCFG_TERMSELDLPULSE_Pos = 0x16 + // Bit mask of TERMSELDLPULSE field. + USB_GUSBCFG_TERMSELDLPULSE_Msk = 0x400000 + // Bit TERMSELDLPULSE. + USB_GUSBCFG_TERMSELDLPULSE = 0x400000 + // Position of TXENDDELAY field. + USB_GUSBCFG_TXENDDELAY_Pos = 0x1c + // Bit mask of TXENDDELAY field. + USB_GUSBCFG_TXENDDELAY_Msk = 0x10000000 + // Bit TXENDDELAY. + USB_GUSBCFG_TXENDDELAY = 0x10000000 + // Position of FORCEHSTMODE field. + USB_GUSBCFG_FORCEHSTMODE_Pos = 0x1d + // Bit mask of FORCEHSTMODE field. + USB_GUSBCFG_FORCEHSTMODE_Msk = 0x20000000 + // Bit FORCEHSTMODE. + USB_GUSBCFG_FORCEHSTMODE = 0x20000000 + // Position of FORCEDEVMODE field. + USB_GUSBCFG_FORCEDEVMODE_Pos = 0x1e + // Bit mask of FORCEDEVMODE field. + USB_GUSBCFG_FORCEDEVMODE_Msk = 0x40000000 + // Bit FORCEDEVMODE. + USB_GUSBCFG_FORCEDEVMODE = 0x40000000 + // Position of CORRUPTTXPKT field. + USB_GUSBCFG_CORRUPTTXPKT_Pos = 0x1f + // Bit mask of CORRUPTTXPKT field. + USB_GUSBCFG_CORRUPTTXPKT_Msk = 0x80000000 + // Bit CORRUPTTXPKT. + USB_GUSBCFG_CORRUPTTXPKT = 0x80000000 + + // GRSTCTL + // Position of CSFTRST field. + USB_GRSTCTL_CSFTRST_Pos = 0x0 + // Bit mask of CSFTRST field. + USB_GRSTCTL_CSFTRST_Msk = 0x1 + // Bit CSFTRST. + USB_GRSTCTL_CSFTRST = 0x1 + // Position of PIUFSSFTRST field. + USB_GRSTCTL_PIUFSSFTRST_Pos = 0x1 + // Bit mask of PIUFSSFTRST field. + USB_GRSTCTL_PIUFSSFTRST_Msk = 0x2 + // Bit PIUFSSFTRST. + USB_GRSTCTL_PIUFSSFTRST = 0x2 + // Position of FRMCNTRRST field. + USB_GRSTCTL_FRMCNTRRST_Pos = 0x2 + // Bit mask of FRMCNTRRST field. + USB_GRSTCTL_FRMCNTRRST_Msk = 0x4 + // Bit FRMCNTRRST. + USB_GRSTCTL_FRMCNTRRST = 0x4 + // Position of RXFFLSH field. + USB_GRSTCTL_RXFFLSH_Pos = 0x4 + // Bit mask of RXFFLSH field. + USB_GRSTCTL_RXFFLSH_Msk = 0x10 + // Bit RXFFLSH. + USB_GRSTCTL_RXFFLSH = 0x10 + // Position of TXFFLSH field. + USB_GRSTCTL_TXFFLSH_Pos = 0x5 + // Bit mask of TXFFLSH field. + USB_GRSTCTL_TXFFLSH_Msk = 0x20 + // Bit TXFFLSH. + USB_GRSTCTL_TXFFLSH = 0x20 + // Position of TXFNUM field. + USB_GRSTCTL_TXFNUM_Pos = 0x6 + // Bit mask of TXFNUM field. + USB_GRSTCTL_TXFNUM_Msk = 0x7c0 + // Position of DMAREQ field. + USB_GRSTCTL_DMAREQ_Pos = 0x1e + // Bit mask of DMAREQ field. + USB_GRSTCTL_DMAREQ_Msk = 0x40000000 + // Bit DMAREQ. + USB_GRSTCTL_DMAREQ = 0x40000000 + // Position of AHBIDLE field. + USB_GRSTCTL_AHBIDLE_Pos = 0x1f + // Bit mask of AHBIDLE field. + USB_GRSTCTL_AHBIDLE_Msk = 0x80000000 + // Bit AHBIDLE. + USB_GRSTCTL_AHBIDLE = 0x80000000 + + // GINTSTS + // Position of CURMOD_INT field. + USB_GINTSTS_CURMOD_INT_Pos = 0x0 + // Bit mask of CURMOD_INT field. + USB_GINTSTS_CURMOD_INT_Msk = 0x1 + // Bit CURMOD_INT. + USB_GINTSTS_CURMOD_INT = 0x1 + // Position of MODEMIS field. + USB_GINTSTS_MODEMIS_Pos = 0x1 + // Bit mask of MODEMIS field. + USB_GINTSTS_MODEMIS_Msk = 0x2 + // Bit MODEMIS. + USB_GINTSTS_MODEMIS = 0x2 + // Position of OTGINT field. + USB_GINTSTS_OTGINT_Pos = 0x2 + // Bit mask of OTGINT field. + USB_GINTSTS_OTGINT_Msk = 0x4 + // Bit OTGINT. + USB_GINTSTS_OTGINT = 0x4 + // Position of SOF field. + USB_GINTSTS_SOF_Pos = 0x3 + // Bit mask of SOF field. + USB_GINTSTS_SOF_Msk = 0x8 + // Bit SOF. + USB_GINTSTS_SOF = 0x8 + // Position of RXFLVI field. + USB_GINTSTS_RXFLVI_Pos = 0x4 + // Bit mask of RXFLVI field. + USB_GINTSTS_RXFLVI_Msk = 0x10 + // Bit RXFLVI. + USB_GINTSTS_RXFLVI = 0x10 + // Position of NPTXFEMP field. + USB_GINTSTS_NPTXFEMP_Pos = 0x5 + // Bit mask of NPTXFEMP field. + USB_GINTSTS_NPTXFEMP_Msk = 0x20 + // Bit NPTXFEMP. + USB_GINTSTS_NPTXFEMP = 0x20 + // Position of GINNAKEFF field. + USB_GINTSTS_GINNAKEFF_Pos = 0x6 + // Bit mask of GINNAKEFF field. + USB_GINTSTS_GINNAKEFF_Msk = 0x40 + // Bit GINNAKEFF. + USB_GINTSTS_GINNAKEFF = 0x40 + // Position of GOUTNAKEFF field. + USB_GINTSTS_GOUTNAKEFF_Pos = 0x7 + // Bit mask of GOUTNAKEFF field. + USB_GINTSTS_GOUTNAKEFF_Msk = 0x80 + // Bit GOUTNAKEFF. + USB_GINTSTS_GOUTNAKEFF = 0x80 + // Position of ERLYSUSP field. + USB_GINTSTS_ERLYSUSP_Pos = 0xa + // Bit mask of ERLYSUSP field. + USB_GINTSTS_ERLYSUSP_Msk = 0x400 + // Bit ERLYSUSP. + USB_GINTSTS_ERLYSUSP = 0x400 + // Position of USBSUSP field. + USB_GINTSTS_USBSUSP_Pos = 0xb + // Bit mask of USBSUSP field. + USB_GINTSTS_USBSUSP_Msk = 0x800 + // Bit USBSUSP. + USB_GINTSTS_USBSUSP = 0x800 + // Position of USBRST field. + USB_GINTSTS_USBRST_Pos = 0xc + // Bit mask of USBRST field. + USB_GINTSTS_USBRST_Msk = 0x1000 + // Bit USBRST. + USB_GINTSTS_USBRST = 0x1000 + // Position of ENUMDONE field. + USB_GINTSTS_ENUMDONE_Pos = 0xd + // Bit mask of ENUMDONE field. + USB_GINTSTS_ENUMDONE_Msk = 0x2000 + // Bit ENUMDONE. + USB_GINTSTS_ENUMDONE = 0x2000 + // Position of ISOOUTDROP field. + USB_GINTSTS_ISOOUTDROP_Pos = 0xe + // Bit mask of ISOOUTDROP field. + USB_GINTSTS_ISOOUTDROP_Msk = 0x4000 + // Bit ISOOUTDROP. + USB_GINTSTS_ISOOUTDROP = 0x4000 + // Position of EOPF field. + USB_GINTSTS_EOPF_Pos = 0xf + // Bit mask of EOPF field. + USB_GINTSTS_EOPF_Msk = 0x8000 + // Bit EOPF. + USB_GINTSTS_EOPF = 0x8000 + // Position of EPMIS field. + USB_GINTSTS_EPMIS_Pos = 0x11 + // Bit mask of EPMIS field. + USB_GINTSTS_EPMIS_Msk = 0x20000 + // Bit EPMIS. + USB_GINTSTS_EPMIS = 0x20000 + // Position of IEPINT field. + USB_GINTSTS_IEPINT_Pos = 0x12 + // Bit mask of IEPINT field. + USB_GINTSTS_IEPINT_Msk = 0x40000 + // Bit IEPINT. + USB_GINTSTS_IEPINT = 0x40000 + // Position of OEPINT field. + USB_GINTSTS_OEPINT_Pos = 0x13 + // Bit mask of OEPINT field. + USB_GINTSTS_OEPINT_Msk = 0x80000 + // Bit OEPINT. + USB_GINTSTS_OEPINT = 0x80000 + // Position of INCOMPISOIN field. + USB_GINTSTS_INCOMPISOIN_Pos = 0x14 + // Bit mask of INCOMPISOIN field. + USB_GINTSTS_INCOMPISOIN_Msk = 0x100000 + // Bit INCOMPISOIN. + USB_GINTSTS_INCOMPISOIN = 0x100000 + // Position of INCOMPIP field. + USB_GINTSTS_INCOMPIP_Pos = 0x15 + // Bit mask of INCOMPIP field. + USB_GINTSTS_INCOMPIP_Msk = 0x200000 + // Bit INCOMPIP. + USB_GINTSTS_INCOMPIP = 0x200000 + // Position of FETSUSP field. + USB_GINTSTS_FETSUSP_Pos = 0x16 + // Bit mask of FETSUSP field. + USB_GINTSTS_FETSUSP_Msk = 0x400000 + // Bit FETSUSP. + USB_GINTSTS_FETSUSP = 0x400000 + // Position of RESETDET field. + USB_GINTSTS_RESETDET_Pos = 0x17 + // Bit mask of RESETDET field. + USB_GINTSTS_RESETDET_Msk = 0x800000 + // Bit RESETDET. + USB_GINTSTS_RESETDET = 0x800000 + // Position of PRTLNT field. + USB_GINTSTS_PRTLNT_Pos = 0x18 + // Bit mask of PRTLNT field. + USB_GINTSTS_PRTLNT_Msk = 0x1000000 + // Bit PRTLNT. + USB_GINTSTS_PRTLNT = 0x1000000 + // Position of HCHLNT field. + USB_GINTSTS_HCHLNT_Pos = 0x19 + // Bit mask of HCHLNT field. + USB_GINTSTS_HCHLNT_Msk = 0x2000000 + // Bit HCHLNT. + USB_GINTSTS_HCHLNT = 0x2000000 + // Position of PTXFEMP field. + USB_GINTSTS_PTXFEMP_Pos = 0x1a + // Bit mask of PTXFEMP field. + USB_GINTSTS_PTXFEMP_Msk = 0x4000000 + // Bit PTXFEMP. + USB_GINTSTS_PTXFEMP = 0x4000000 + // Position of CONIDSTSCHNG field. + USB_GINTSTS_CONIDSTSCHNG_Pos = 0x1c + // Bit mask of CONIDSTSCHNG field. + USB_GINTSTS_CONIDSTSCHNG_Msk = 0x10000000 + // Bit CONIDSTSCHNG. + USB_GINTSTS_CONIDSTSCHNG = 0x10000000 + // Position of DISCONNINT field. + USB_GINTSTS_DISCONNINT_Pos = 0x1d + // Bit mask of DISCONNINT field. + USB_GINTSTS_DISCONNINT_Msk = 0x20000000 + // Bit DISCONNINT. + USB_GINTSTS_DISCONNINT = 0x20000000 + // Position of SESSREQINT field. + USB_GINTSTS_SESSREQINT_Pos = 0x1e + // Bit mask of SESSREQINT field. + USB_GINTSTS_SESSREQINT_Msk = 0x40000000 + // Bit SESSREQINT. + USB_GINTSTS_SESSREQINT = 0x40000000 + // Position of WKUPINT field. + USB_GINTSTS_WKUPINT_Pos = 0x1f + // Bit mask of WKUPINT field. + USB_GINTSTS_WKUPINT_Msk = 0x80000000 + // Bit WKUPINT. + USB_GINTSTS_WKUPINT = 0x80000000 + + // GINTMSK + // Position of MODEMISMSK field. + USB_GINTMSK_MODEMISMSK_Pos = 0x1 + // Bit mask of MODEMISMSK field. + USB_GINTMSK_MODEMISMSK_Msk = 0x2 + // Bit MODEMISMSK. + USB_GINTMSK_MODEMISMSK = 0x2 + // Position of OTGINTMSK field. + USB_GINTMSK_OTGINTMSK_Pos = 0x2 + // Bit mask of OTGINTMSK field. + USB_GINTMSK_OTGINTMSK_Msk = 0x4 + // Bit OTGINTMSK. + USB_GINTMSK_OTGINTMSK = 0x4 + // Position of SOFMSK field. + USB_GINTMSK_SOFMSK_Pos = 0x3 + // Bit mask of SOFMSK field. + USB_GINTMSK_SOFMSK_Msk = 0x8 + // Bit SOFMSK. + USB_GINTMSK_SOFMSK = 0x8 + // Position of RXFLVIMSK field. + USB_GINTMSK_RXFLVIMSK_Pos = 0x4 + // Bit mask of RXFLVIMSK field. + USB_GINTMSK_RXFLVIMSK_Msk = 0x10 + // Bit RXFLVIMSK. + USB_GINTMSK_RXFLVIMSK = 0x10 + // Position of NPTXFEMPMSK field. + USB_GINTMSK_NPTXFEMPMSK_Pos = 0x5 + // Bit mask of NPTXFEMPMSK field. + USB_GINTMSK_NPTXFEMPMSK_Msk = 0x20 + // Bit NPTXFEMPMSK. + USB_GINTMSK_NPTXFEMPMSK = 0x20 + // Position of GINNAKEFFMSK field. + USB_GINTMSK_GINNAKEFFMSK_Pos = 0x6 + // Bit mask of GINNAKEFFMSK field. + USB_GINTMSK_GINNAKEFFMSK_Msk = 0x40 + // Bit GINNAKEFFMSK. + USB_GINTMSK_GINNAKEFFMSK = 0x40 + // Position of GOUTNACKEFFMSK field. + USB_GINTMSK_GOUTNACKEFFMSK_Pos = 0x7 + // Bit mask of GOUTNACKEFFMSK field. + USB_GINTMSK_GOUTNACKEFFMSK_Msk = 0x80 + // Bit GOUTNACKEFFMSK. + USB_GINTMSK_GOUTNACKEFFMSK = 0x80 + // Position of ERLYSUSPMSK field. + USB_GINTMSK_ERLYSUSPMSK_Pos = 0xa + // Bit mask of ERLYSUSPMSK field. + USB_GINTMSK_ERLYSUSPMSK_Msk = 0x400 + // Bit ERLYSUSPMSK. + USB_GINTMSK_ERLYSUSPMSK = 0x400 + // Position of USBSUSPMSK field. + USB_GINTMSK_USBSUSPMSK_Pos = 0xb + // Bit mask of USBSUSPMSK field. + USB_GINTMSK_USBSUSPMSK_Msk = 0x800 + // Bit USBSUSPMSK. + USB_GINTMSK_USBSUSPMSK = 0x800 + // Position of USBRSTMSK field. + USB_GINTMSK_USBRSTMSK_Pos = 0xc + // Bit mask of USBRSTMSK field. + USB_GINTMSK_USBRSTMSK_Msk = 0x1000 + // Bit USBRSTMSK. + USB_GINTMSK_USBRSTMSK = 0x1000 + // Position of ENUMDONEMSK field. + USB_GINTMSK_ENUMDONEMSK_Pos = 0xd + // Bit mask of ENUMDONEMSK field. + USB_GINTMSK_ENUMDONEMSK_Msk = 0x2000 + // Bit ENUMDONEMSK. + USB_GINTMSK_ENUMDONEMSK = 0x2000 + // Position of ISOOUTDROPMSK field. + USB_GINTMSK_ISOOUTDROPMSK_Pos = 0xe + // Bit mask of ISOOUTDROPMSK field. + USB_GINTMSK_ISOOUTDROPMSK_Msk = 0x4000 + // Bit ISOOUTDROPMSK. + USB_GINTMSK_ISOOUTDROPMSK = 0x4000 + // Position of EOPFMSK field. + USB_GINTMSK_EOPFMSK_Pos = 0xf + // Bit mask of EOPFMSK field. + USB_GINTMSK_EOPFMSK_Msk = 0x8000 + // Bit EOPFMSK. + USB_GINTMSK_EOPFMSK = 0x8000 + // Position of EPMISMSK field. + USB_GINTMSK_EPMISMSK_Pos = 0x11 + // Bit mask of EPMISMSK field. + USB_GINTMSK_EPMISMSK_Msk = 0x20000 + // Bit EPMISMSK. + USB_GINTMSK_EPMISMSK = 0x20000 + // Position of IEPINTMSK field. + USB_GINTMSK_IEPINTMSK_Pos = 0x12 + // Bit mask of IEPINTMSK field. + USB_GINTMSK_IEPINTMSK_Msk = 0x40000 + // Bit IEPINTMSK. + USB_GINTMSK_IEPINTMSK = 0x40000 + // Position of OEPINTMSK field. + USB_GINTMSK_OEPINTMSK_Pos = 0x13 + // Bit mask of OEPINTMSK field. + USB_GINTMSK_OEPINTMSK_Msk = 0x80000 + // Bit OEPINTMSK. + USB_GINTMSK_OEPINTMSK = 0x80000 + // Position of INCOMPISOINMSK field. + USB_GINTMSK_INCOMPISOINMSK_Pos = 0x14 + // Bit mask of INCOMPISOINMSK field. + USB_GINTMSK_INCOMPISOINMSK_Msk = 0x100000 + // Bit INCOMPISOINMSK. + USB_GINTMSK_INCOMPISOINMSK = 0x100000 + // Position of INCOMPIPMSK field. + USB_GINTMSK_INCOMPIPMSK_Pos = 0x15 + // Bit mask of INCOMPIPMSK field. + USB_GINTMSK_INCOMPIPMSK_Msk = 0x200000 + // Bit INCOMPIPMSK. + USB_GINTMSK_INCOMPIPMSK = 0x200000 + // Position of FETSUSPMSK field. + USB_GINTMSK_FETSUSPMSK_Pos = 0x16 + // Bit mask of FETSUSPMSK field. + USB_GINTMSK_FETSUSPMSK_Msk = 0x400000 + // Bit FETSUSPMSK. + USB_GINTMSK_FETSUSPMSK = 0x400000 + // Position of RESETDETMSK field. + USB_GINTMSK_RESETDETMSK_Pos = 0x17 + // Bit mask of RESETDETMSK field. + USB_GINTMSK_RESETDETMSK_Msk = 0x800000 + // Bit RESETDETMSK. + USB_GINTMSK_RESETDETMSK = 0x800000 + // Position of PRTLNTMSK field. + USB_GINTMSK_PRTLNTMSK_Pos = 0x18 + // Bit mask of PRTLNTMSK field. + USB_GINTMSK_PRTLNTMSK_Msk = 0x1000000 + // Bit PRTLNTMSK. + USB_GINTMSK_PRTLNTMSK = 0x1000000 + // Position of HCHINTMSK field. + USB_GINTMSK_HCHINTMSK_Pos = 0x19 + // Bit mask of HCHINTMSK field. + USB_GINTMSK_HCHINTMSK_Msk = 0x2000000 + // Bit HCHINTMSK. + USB_GINTMSK_HCHINTMSK = 0x2000000 + // Position of PTXFEMPMSK field. + USB_GINTMSK_PTXFEMPMSK_Pos = 0x1a + // Bit mask of PTXFEMPMSK field. + USB_GINTMSK_PTXFEMPMSK_Msk = 0x4000000 + // Bit PTXFEMPMSK. + USB_GINTMSK_PTXFEMPMSK = 0x4000000 + // Position of CONIDSTSCHNGMSK field. + USB_GINTMSK_CONIDSTSCHNGMSK_Pos = 0x1c + // Bit mask of CONIDSTSCHNGMSK field. + USB_GINTMSK_CONIDSTSCHNGMSK_Msk = 0x10000000 + // Bit CONIDSTSCHNGMSK. + USB_GINTMSK_CONIDSTSCHNGMSK = 0x10000000 + // Position of DISCONNINTMSK field. + USB_GINTMSK_DISCONNINTMSK_Pos = 0x1d + // Bit mask of DISCONNINTMSK field. + USB_GINTMSK_DISCONNINTMSK_Msk = 0x20000000 + // Bit DISCONNINTMSK. + USB_GINTMSK_DISCONNINTMSK = 0x20000000 + // Position of SESSREQINTMSK field. + USB_GINTMSK_SESSREQINTMSK_Pos = 0x1e + // Bit mask of SESSREQINTMSK field. + USB_GINTMSK_SESSREQINTMSK_Msk = 0x40000000 + // Bit SESSREQINTMSK. + USB_GINTMSK_SESSREQINTMSK = 0x40000000 + // Position of WKUPINTMSK field. + USB_GINTMSK_WKUPINTMSK_Pos = 0x1f + // Bit mask of WKUPINTMSK field. + USB_GINTMSK_WKUPINTMSK_Msk = 0x80000000 + // Bit WKUPINTMSK. + USB_GINTMSK_WKUPINTMSK = 0x80000000 + + // GRXSTSR + // Position of G_CHNUM field. + USB_GRXSTSR_G_CHNUM_Pos = 0x0 + // Bit mask of G_CHNUM field. + USB_GRXSTSR_G_CHNUM_Msk = 0xf + // Position of G_BCNT field. + USB_GRXSTSR_G_BCNT_Pos = 0x4 + // Bit mask of G_BCNT field. + USB_GRXSTSR_G_BCNT_Msk = 0x7ff0 + // Position of G_DPID field. + USB_GRXSTSR_G_DPID_Pos = 0xf + // Bit mask of G_DPID field. + USB_GRXSTSR_G_DPID_Msk = 0x18000 + // Position of G_PKTSTS field. + USB_GRXSTSR_G_PKTSTS_Pos = 0x11 + // Bit mask of G_PKTSTS field. + USB_GRXSTSR_G_PKTSTS_Msk = 0x1e0000 + // Position of G_FN field. + USB_GRXSTSR_G_FN_Pos = 0x15 + // Bit mask of G_FN field. + USB_GRXSTSR_G_FN_Msk = 0x1e00000 + + // GRXSTSP + // Position of CHNUM field. + USB_GRXSTSP_CHNUM_Pos = 0x0 + // Bit mask of CHNUM field. + USB_GRXSTSP_CHNUM_Msk = 0xf + // Position of BCNT field. + USB_GRXSTSP_BCNT_Pos = 0x4 + // Bit mask of BCNT field. + USB_GRXSTSP_BCNT_Msk = 0x7ff0 + // Position of DPID field. + USB_GRXSTSP_DPID_Pos = 0xf + // Bit mask of DPID field. + USB_GRXSTSP_DPID_Msk = 0x18000 + // Position of PKTSTS field. + USB_GRXSTSP_PKTSTS_Pos = 0x11 + // Bit mask of PKTSTS field. + USB_GRXSTSP_PKTSTS_Msk = 0x1e0000 + // Position of FN field. + USB_GRXSTSP_FN_Pos = 0x15 + // Bit mask of FN field. + USB_GRXSTSP_FN_Msk = 0x1e00000 + + // GRXFSIZ + // Position of RXFDEP field. + USB_GRXFSIZ_RXFDEP_Pos = 0x0 + // Bit mask of RXFDEP field. + USB_GRXFSIZ_RXFDEP_Msk = 0xffff + + // GNPTXFSIZ + // Position of NPTXFSTADDR field. + USB_GNPTXFSIZ_NPTXFSTADDR_Pos = 0x0 + // Bit mask of NPTXFSTADDR field. + USB_GNPTXFSIZ_NPTXFSTADDR_Msk = 0xffff + // Position of NPTXFDEP field. + USB_GNPTXFSIZ_NPTXFDEP_Pos = 0x10 + // Bit mask of NPTXFDEP field. + USB_GNPTXFSIZ_NPTXFDEP_Msk = 0xffff0000 + + // GNPTXSTS + // Position of NPTXFSPCAVAIL field. + USB_GNPTXSTS_NPTXFSPCAVAIL_Pos = 0x0 + // Bit mask of NPTXFSPCAVAIL field. + USB_GNPTXSTS_NPTXFSPCAVAIL_Msk = 0xffff + // Position of NPTXQSPCAVAIL field. + USB_GNPTXSTS_NPTXQSPCAVAIL_Pos = 0x10 + // Bit mask of NPTXQSPCAVAIL field. + USB_GNPTXSTS_NPTXQSPCAVAIL_Msk = 0xf0000 + // Position of NPTXQTOP field. + USB_GNPTXSTS_NPTXQTOP_Pos = 0x18 + // Bit mask of NPTXQTOP field. + USB_GNPTXSTS_NPTXQTOP_Msk = 0x7f000000 + + // GSNPSID + // Position of SYNOPSYSID field. + USB_GSNPSID_SYNOPSYSID_Pos = 0x0 + // Bit mask of SYNOPSYSID field. + USB_GSNPSID_SYNOPSYSID_Msk = 0xffffffff + + // GHWCFG1 + // Position of EPDIR field. + USB_GHWCFG1_EPDIR_Pos = 0x0 + // Bit mask of EPDIR field. + USB_GHWCFG1_EPDIR_Msk = 0xffffffff + + // GHWCFG2 + // Position of OTGMODE field. + USB_GHWCFG2_OTGMODE_Pos = 0x0 + // Bit mask of OTGMODE field. + USB_GHWCFG2_OTGMODE_Msk = 0x7 + // Position of OTGARCH field. + USB_GHWCFG2_OTGARCH_Pos = 0x3 + // Bit mask of OTGARCH field. + USB_GHWCFG2_OTGARCH_Msk = 0x18 + // Position of SINGPNT field. + USB_GHWCFG2_SINGPNT_Pos = 0x5 + // Bit mask of SINGPNT field. + USB_GHWCFG2_SINGPNT_Msk = 0x20 + // Bit SINGPNT. + USB_GHWCFG2_SINGPNT = 0x20 + // Position of HSPHYTYPE field. + USB_GHWCFG2_HSPHYTYPE_Pos = 0x6 + // Bit mask of HSPHYTYPE field. + USB_GHWCFG2_HSPHYTYPE_Msk = 0xc0 + // Position of FSPHYTYPE field. + USB_GHWCFG2_FSPHYTYPE_Pos = 0x8 + // Bit mask of FSPHYTYPE field. + USB_GHWCFG2_FSPHYTYPE_Msk = 0x300 + // Position of NUMDEVEPS field. + USB_GHWCFG2_NUMDEVEPS_Pos = 0xa + // Bit mask of NUMDEVEPS field. + USB_GHWCFG2_NUMDEVEPS_Msk = 0x3c00 + // Position of NUMHSTCHNL field. + USB_GHWCFG2_NUMHSTCHNL_Pos = 0xe + // Bit mask of NUMHSTCHNL field. + USB_GHWCFG2_NUMHSTCHNL_Msk = 0x3c000 + // Position of PERIOSUPPORT field. + USB_GHWCFG2_PERIOSUPPORT_Pos = 0x12 + // Bit mask of PERIOSUPPORT field. + USB_GHWCFG2_PERIOSUPPORT_Msk = 0x40000 + // Bit PERIOSUPPORT. + USB_GHWCFG2_PERIOSUPPORT = 0x40000 + // Position of DYNFIFOSIZING field. + USB_GHWCFG2_DYNFIFOSIZING_Pos = 0x13 + // Bit mask of DYNFIFOSIZING field. + USB_GHWCFG2_DYNFIFOSIZING_Msk = 0x80000 + // Bit DYNFIFOSIZING. + USB_GHWCFG2_DYNFIFOSIZING = 0x80000 + // Position of MULTIPROCINTRPT field. + USB_GHWCFG2_MULTIPROCINTRPT_Pos = 0x14 + // Bit mask of MULTIPROCINTRPT field. + USB_GHWCFG2_MULTIPROCINTRPT_Msk = 0x100000 + // Bit MULTIPROCINTRPT. + USB_GHWCFG2_MULTIPROCINTRPT = 0x100000 + // Position of NPTXQDEPTH field. + USB_GHWCFG2_NPTXQDEPTH_Pos = 0x16 + // Bit mask of NPTXQDEPTH field. + USB_GHWCFG2_NPTXQDEPTH_Msk = 0xc00000 + // Position of PTXQDEPTH field. + USB_GHWCFG2_PTXQDEPTH_Pos = 0x18 + // Bit mask of PTXQDEPTH field. + USB_GHWCFG2_PTXQDEPTH_Msk = 0x3000000 + // Position of TKNQDEPTH field. + USB_GHWCFG2_TKNQDEPTH_Pos = 0x1a + // Bit mask of TKNQDEPTH field. + USB_GHWCFG2_TKNQDEPTH_Msk = 0x7c000000 + // Position of OTG_ENABLE_IC_USB field. + USB_GHWCFG2_OTG_ENABLE_IC_USB_Pos = 0x1f + // Bit mask of OTG_ENABLE_IC_USB field. + USB_GHWCFG2_OTG_ENABLE_IC_USB_Msk = 0x80000000 + // Bit OTG_ENABLE_IC_USB. + USB_GHWCFG2_OTG_ENABLE_IC_USB = 0x80000000 + + // GHWCFG3 + // Position of XFERSIZEWIDTH field. + USB_GHWCFG3_XFERSIZEWIDTH_Pos = 0x0 + // Bit mask of XFERSIZEWIDTH field. + USB_GHWCFG3_XFERSIZEWIDTH_Msk = 0xf + // Position of PKTSIZEWIDTH field. + USB_GHWCFG3_PKTSIZEWIDTH_Pos = 0x4 + // Bit mask of PKTSIZEWIDTH field. + USB_GHWCFG3_PKTSIZEWIDTH_Msk = 0x70 + // Position of OTGEN field. + USB_GHWCFG3_OTGEN_Pos = 0x7 + // Bit mask of OTGEN field. + USB_GHWCFG3_OTGEN_Msk = 0x80 + // Bit OTGEN. + USB_GHWCFG3_OTGEN = 0x80 + // Position of I2CINTSEL field. + USB_GHWCFG3_I2CINTSEL_Pos = 0x8 + // Bit mask of I2CINTSEL field. + USB_GHWCFG3_I2CINTSEL_Msk = 0x100 + // Bit I2CINTSEL. + USB_GHWCFG3_I2CINTSEL = 0x100 + // Position of VNDCTLSUPT field. + USB_GHWCFG3_VNDCTLSUPT_Pos = 0x9 + // Bit mask of VNDCTLSUPT field. + USB_GHWCFG3_VNDCTLSUPT_Msk = 0x200 + // Bit VNDCTLSUPT. + USB_GHWCFG3_VNDCTLSUPT = 0x200 + // Position of OPTFEATURE field. + USB_GHWCFG3_OPTFEATURE_Pos = 0xa + // Bit mask of OPTFEATURE field. + USB_GHWCFG3_OPTFEATURE_Msk = 0x400 + // Bit OPTFEATURE. + USB_GHWCFG3_OPTFEATURE = 0x400 + // Position of RSTTYPE field. + USB_GHWCFG3_RSTTYPE_Pos = 0xb + // Bit mask of RSTTYPE field. + USB_GHWCFG3_RSTTYPE_Msk = 0x800 + // Bit RSTTYPE. + USB_GHWCFG3_RSTTYPE = 0x800 + // Position of ADPSUPPORT field. + USB_GHWCFG3_ADPSUPPORT_Pos = 0xc + // Bit mask of ADPSUPPORT field. + USB_GHWCFG3_ADPSUPPORT_Msk = 0x1000 + // Bit ADPSUPPORT. + USB_GHWCFG3_ADPSUPPORT = 0x1000 + // Position of HSICMODE field. + USB_GHWCFG3_HSICMODE_Pos = 0xd + // Bit mask of HSICMODE field. + USB_GHWCFG3_HSICMODE_Msk = 0x2000 + // Bit HSICMODE. + USB_GHWCFG3_HSICMODE = 0x2000 + // Position of BCSUPPORT field. + USB_GHWCFG3_BCSUPPORT_Pos = 0xe + // Bit mask of BCSUPPORT field. + USB_GHWCFG3_BCSUPPORT_Msk = 0x4000 + // Bit BCSUPPORT. + USB_GHWCFG3_BCSUPPORT = 0x4000 + // Position of LPMMODE field. + USB_GHWCFG3_LPMMODE_Pos = 0xf + // Bit mask of LPMMODE field. + USB_GHWCFG3_LPMMODE_Msk = 0x8000 + // Bit LPMMODE. + USB_GHWCFG3_LPMMODE = 0x8000 + // Position of DFIFODEPTH field. + USB_GHWCFG3_DFIFODEPTH_Pos = 0x10 + // Bit mask of DFIFODEPTH field. + USB_GHWCFG3_DFIFODEPTH_Msk = 0xffff0000 + + // GHWCFG4 + // Position of G_NUMDEVPERIOEPS field. + USB_GHWCFG4_G_NUMDEVPERIOEPS_Pos = 0x0 + // Bit mask of G_NUMDEVPERIOEPS field. + USB_GHWCFG4_G_NUMDEVPERIOEPS_Msk = 0xf + // Position of G_PARTIALPWRDN field. + USB_GHWCFG4_G_PARTIALPWRDN_Pos = 0x4 + // Bit mask of G_PARTIALPWRDN field. + USB_GHWCFG4_G_PARTIALPWRDN_Msk = 0x10 + // Bit G_PARTIALPWRDN. + USB_GHWCFG4_G_PARTIALPWRDN = 0x10 + // Position of G_AHBFREQ field. + USB_GHWCFG4_G_AHBFREQ_Pos = 0x5 + // Bit mask of G_AHBFREQ field. + USB_GHWCFG4_G_AHBFREQ_Msk = 0x20 + // Bit G_AHBFREQ. + USB_GHWCFG4_G_AHBFREQ = 0x20 + // Position of G_HIBERNATION field. + USB_GHWCFG4_G_HIBERNATION_Pos = 0x6 + // Bit mask of G_HIBERNATION field. + USB_GHWCFG4_G_HIBERNATION_Msk = 0x40 + // Bit G_HIBERNATION. + USB_GHWCFG4_G_HIBERNATION = 0x40 + // Position of G_EXTENDEDHIBERNATION field. + USB_GHWCFG4_G_EXTENDEDHIBERNATION_Pos = 0x7 + // Bit mask of G_EXTENDEDHIBERNATION field. + USB_GHWCFG4_G_EXTENDEDHIBERNATION_Msk = 0x80 + // Bit G_EXTENDEDHIBERNATION. + USB_GHWCFG4_G_EXTENDEDHIBERNATION = 0x80 + // Position of G_ACGSUPT field. + USB_GHWCFG4_G_ACGSUPT_Pos = 0xc + // Bit mask of G_ACGSUPT field. + USB_GHWCFG4_G_ACGSUPT_Msk = 0x1000 + // Bit G_ACGSUPT. + USB_GHWCFG4_G_ACGSUPT = 0x1000 + // Position of G_ENHANCEDLPMSUPT field. + USB_GHWCFG4_G_ENHANCEDLPMSUPT_Pos = 0xd + // Bit mask of G_ENHANCEDLPMSUPT field. + USB_GHWCFG4_G_ENHANCEDLPMSUPT_Msk = 0x2000 + // Bit G_ENHANCEDLPMSUPT. + USB_GHWCFG4_G_ENHANCEDLPMSUPT = 0x2000 + // Position of G_PHYDATAWIDTH field. + USB_GHWCFG4_G_PHYDATAWIDTH_Pos = 0xe + // Bit mask of G_PHYDATAWIDTH field. + USB_GHWCFG4_G_PHYDATAWIDTH_Msk = 0xc000 + // Position of G_NUMCTLEPS field. + USB_GHWCFG4_G_NUMCTLEPS_Pos = 0x10 + // Bit mask of G_NUMCTLEPS field. + USB_GHWCFG4_G_NUMCTLEPS_Msk = 0xf0000 + // Position of G_IDDQFLTR field. + USB_GHWCFG4_G_IDDQFLTR_Pos = 0x14 + // Bit mask of G_IDDQFLTR field. + USB_GHWCFG4_G_IDDQFLTR_Msk = 0x100000 + // Bit G_IDDQFLTR. + USB_GHWCFG4_G_IDDQFLTR = 0x100000 + // Position of G_VBUSVALIDFLTR field. + USB_GHWCFG4_G_VBUSVALIDFLTR_Pos = 0x15 + // Bit mask of G_VBUSVALIDFLTR field. + USB_GHWCFG4_G_VBUSVALIDFLTR_Msk = 0x200000 + // Bit G_VBUSVALIDFLTR. + USB_GHWCFG4_G_VBUSVALIDFLTR = 0x200000 + // Position of G_AVALIDFLTR field. + USB_GHWCFG4_G_AVALIDFLTR_Pos = 0x16 + // Bit mask of G_AVALIDFLTR field. + USB_GHWCFG4_G_AVALIDFLTR_Msk = 0x400000 + // Bit G_AVALIDFLTR. + USB_GHWCFG4_G_AVALIDFLTR = 0x400000 + // Position of G_BVALIDFLTR field. + USB_GHWCFG4_G_BVALIDFLTR_Pos = 0x17 + // Bit mask of G_BVALIDFLTR field. + USB_GHWCFG4_G_BVALIDFLTR_Msk = 0x800000 + // Bit G_BVALIDFLTR. + USB_GHWCFG4_G_BVALIDFLTR = 0x800000 + // Position of G_SESSENDFLTR field. + USB_GHWCFG4_G_SESSENDFLTR_Pos = 0x18 + // Bit mask of G_SESSENDFLTR field. + USB_GHWCFG4_G_SESSENDFLTR_Msk = 0x1000000 + // Bit G_SESSENDFLTR. + USB_GHWCFG4_G_SESSENDFLTR = 0x1000000 + // Position of G_DEDFIFOMODE field. + USB_GHWCFG4_G_DEDFIFOMODE_Pos = 0x19 + // Bit mask of G_DEDFIFOMODE field. + USB_GHWCFG4_G_DEDFIFOMODE_Msk = 0x2000000 + // Bit G_DEDFIFOMODE. + USB_GHWCFG4_G_DEDFIFOMODE = 0x2000000 + // Position of G_INEPS field. + USB_GHWCFG4_G_INEPS_Pos = 0x1a + // Bit mask of G_INEPS field. + USB_GHWCFG4_G_INEPS_Msk = 0x3c000000 + // Position of G_DESCDMAENABLED field. + USB_GHWCFG4_G_DESCDMAENABLED_Pos = 0x1e + // Bit mask of G_DESCDMAENABLED field. + USB_GHWCFG4_G_DESCDMAENABLED_Msk = 0x40000000 + // Bit G_DESCDMAENABLED. + USB_GHWCFG4_G_DESCDMAENABLED = 0x40000000 + // Position of G_DESCDMA field. + USB_GHWCFG4_G_DESCDMA_Pos = 0x1f + // Bit mask of G_DESCDMA field. + USB_GHWCFG4_G_DESCDMA_Msk = 0x80000000 + // Bit G_DESCDMA. + USB_GHWCFG4_G_DESCDMA = 0x80000000 + + // GDFIFOCFG + // Position of GDFIFOCFG field. + USB_GDFIFOCFG_GDFIFOCFG_Pos = 0x0 + // Bit mask of GDFIFOCFG field. + USB_GDFIFOCFG_GDFIFOCFG_Msk = 0xffff + // Position of EPINFOBASEADDR field. + USB_GDFIFOCFG_EPINFOBASEADDR_Pos = 0x10 + // Bit mask of EPINFOBASEADDR field. + USB_GDFIFOCFG_EPINFOBASEADDR_Msk = 0xffff0000 + + // HPTXFSIZ + // Position of PTXFSTADDR field. + USB_HPTXFSIZ_PTXFSTADDR_Pos = 0x0 + // Bit mask of PTXFSTADDR field. + USB_HPTXFSIZ_PTXFSTADDR_Msk = 0xffff + // Position of PTXFSIZE field. + USB_HPTXFSIZ_PTXFSIZE_Pos = 0x10 + // Bit mask of PTXFSIZE field. + USB_HPTXFSIZ_PTXFSIZE_Msk = 0xffff0000 + + // DIEPTXF1 + // Position of INEP1TXFSTADDR field. + USB_DIEPTXF1_INEP1TXFSTADDR_Pos = 0x0 + // Bit mask of INEP1TXFSTADDR field. + USB_DIEPTXF1_INEP1TXFSTADDR_Msk = 0xffff + // Position of INEP1TXFDEP field. + USB_DIEPTXF1_INEP1TXFDEP_Pos = 0x10 + // Bit mask of INEP1TXFDEP field. + USB_DIEPTXF1_INEP1TXFDEP_Msk = 0xffff0000 + + // DIEPTXF2 + // Position of INEP2TXFSTADDR field. + USB_DIEPTXF2_INEP2TXFSTADDR_Pos = 0x0 + // Bit mask of INEP2TXFSTADDR field. + USB_DIEPTXF2_INEP2TXFSTADDR_Msk = 0xffff + // Position of INEP2TXFDEP field. + USB_DIEPTXF2_INEP2TXFDEP_Pos = 0x10 + // Bit mask of INEP2TXFDEP field. + USB_DIEPTXF2_INEP2TXFDEP_Msk = 0xffff0000 + + // DIEPTXF3 + // Position of INEP3TXFSTADDR field. + USB_DIEPTXF3_INEP3TXFSTADDR_Pos = 0x0 + // Bit mask of INEP3TXFSTADDR field. + USB_DIEPTXF3_INEP3TXFSTADDR_Msk = 0xffff + // Position of INEP3TXFDEP field. + USB_DIEPTXF3_INEP3TXFDEP_Pos = 0x10 + // Bit mask of INEP3TXFDEP field. + USB_DIEPTXF3_INEP3TXFDEP_Msk = 0xffff0000 + + // DIEPTXF4 + // Position of INEP4TXFSTADDR field. + USB_DIEPTXF4_INEP4TXFSTADDR_Pos = 0x0 + // Bit mask of INEP4TXFSTADDR field. + USB_DIEPTXF4_INEP4TXFSTADDR_Msk = 0xffff + // Position of INEP4TXFDEP field. + USB_DIEPTXF4_INEP4TXFDEP_Pos = 0x10 + // Bit mask of INEP4TXFDEP field. + USB_DIEPTXF4_INEP4TXFDEP_Msk = 0xffff0000 + + // HCFG + // Position of H_FSLSPCLKSEL field. + USB_HCFG_H_FSLSPCLKSEL_Pos = 0x0 + // Bit mask of H_FSLSPCLKSEL field. + USB_HCFG_H_FSLSPCLKSEL_Msk = 0x3 + // Position of H_FSLSSUPP field. + USB_HCFG_H_FSLSSUPP_Pos = 0x2 + // Bit mask of H_FSLSSUPP field. + USB_HCFG_H_FSLSSUPP_Msk = 0x4 + // Bit H_FSLSSUPP. + USB_HCFG_H_FSLSSUPP = 0x4 + // Position of H_ENA32KHZS field. + USB_HCFG_H_ENA32KHZS_Pos = 0x7 + // Bit mask of H_ENA32KHZS field. + USB_HCFG_H_ENA32KHZS_Msk = 0x80 + // Bit H_ENA32KHZS. + USB_HCFG_H_ENA32KHZS = 0x80 + // Position of H_DESCDMA field. + USB_HCFG_H_DESCDMA_Pos = 0x17 + // Bit mask of H_DESCDMA field. + USB_HCFG_H_DESCDMA_Msk = 0x800000 + // Bit H_DESCDMA. + USB_HCFG_H_DESCDMA = 0x800000 + // Position of H_FRLISTEN field. + USB_HCFG_H_FRLISTEN_Pos = 0x18 + // Bit mask of H_FRLISTEN field. + USB_HCFG_H_FRLISTEN_Msk = 0x3000000 + // Position of H_PERSCHEDENA field. + USB_HCFG_H_PERSCHEDENA_Pos = 0x1a + // Bit mask of H_PERSCHEDENA field. + USB_HCFG_H_PERSCHEDENA_Msk = 0x4000000 + // Bit H_PERSCHEDENA. + USB_HCFG_H_PERSCHEDENA = 0x4000000 + // Position of H_MODECHTIMEN field. + USB_HCFG_H_MODECHTIMEN_Pos = 0x1f + // Bit mask of H_MODECHTIMEN field. + USB_HCFG_H_MODECHTIMEN_Msk = 0x80000000 + // Bit H_MODECHTIMEN. + USB_HCFG_H_MODECHTIMEN = 0x80000000 + + // HFIR + // Position of FRINT field. + USB_HFIR_FRINT_Pos = 0x0 + // Bit mask of FRINT field. + USB_HFIR_FRINT_Msk = 0xffff + // Position of HFIRRLDCTRL field. + USB_HFIR_HFIRRLDCTRL_Pos = 0x10 + // Bit mask of HFIRRLDCTRL field. + USB_HFIR_HFIRRLDCTRL_Msk = 0x10000 + // Bit HFIRRLDCTRL. + USB_HFIR_HFIRRLDCTRL = 0x10000 + + // HFNUM + // Position of FRNUM field. + USB_HFNUM_FRNUM_Pos = 0x0 + // Bit mask of FRNUM field. + USB_HFNUM_FRNUM_Msk = 0x3fff + // Position of FRREM field. + USB_HFNUM_FRREM_Pos = 0x10 + // Bit mask of FRREM field. + USB_HFNUM_FRREM_Msk = 0xffff0000 + + // HPTXSTS + // Position of PTXFSPCAVAIL field. + USB_HPTXSTS_PTXFSPCAVAIL_Pos = 0x0 + // Bit mask of PTXFSPCAVAIL field. + USB_HPTXSTS_PTXFSPCAVAIL_Msk = 0xffff + // Position of PTXQSPCAVAIL field. + USB_HPTXSTS_PTXQSPCAVAIL_Pos = 0x10 + // Bit mask of PTXQSPCAVAIL field. + USB_HPTXSTS_PTXQSPCAVAIL_Msk = 0x1f0000 + // Position of PTXQTOP field. + USB_HPTXSTS_PTXQTOP_Pos = 0x18 + // Bit mask of PTXQTOP field. + USB_HPTXSTS_PTXQTOP_Msk = 0xff000000 + + // HAINT + // Position of HAINT field. + USB_HAINT_HAINT_Pos = 0x0 + // Bit mask of HAINT field. + USB_HAINT_HAINT_Msk = 0xff + + // HAINTMSK + // Position of HAINTMSK field. + USB_HAINTMSK_HAINTMSK_Pos = 0x0 + // Bit mask of HAINTMSK field. + USB_HAINTMSK_HAINTMSK_Msk = 0xff + + // HFLBADDR + // Position of HFLBADDR field. + USB_HFLBADDR_HFLBADDR_Pos = 0x0 + // Bit mask of HFLBADDR field. + USB_HFLBADDR_HFLBADDR_Msk = 0xffffffff + + // HPRT + // Position of PRTCONNSTS field. + USB_HPRT_PRTCONNSTS_Pos = 0x0 + // Bit mask of PRTCONNSTS field. + USB_HPRT_PRTCONNSTS_Msk = 0x1 + // Bit PRTCONNSTS. + USB_HPRT_PRTCONNSTS = 0x1 + // Position of PRTCONNDET field. + USB_HPRT_PRTCONNDET_Pos = 0x1 + // Bit mask of PRTCONNDET field. + USB_HPRT_PRTCONNDET_Msk = 0x2 + // Bit PRTCONNDET. + USB_HPRT_PRTCONNDET = 0x2 + // Position of PRTENA field. + USB_HPRT_PRTENA_Pos = 0x2 + // Bit mask of PRTENA field. + USB_HPRT_PRTENA_Msk = 0x4 + // Bit PRTENA. + USB_HPRT_PRTENA = 0x4 + // Position of PRTENCHNG field. + USB_HPRT_PRTENCHNG_Pos = 0x3 + // Bit mask of PRTENCHNG field. + USB_HPRT_PRTENCHNG_Msk = 0x8 + // Bit PRTENCHNG. + USB_HPRT_PRTENCHNG = 0x8 + // Position of PRTOVRCURRACT field. + USB_HPRT_PRTOVRCURRACT_Pos = 0x4 + // Bit mask of PRTOVRCURRACT field. + USB_HPRT_PRTOVRCURRACT_Msk = 0x10 + // Bit PRTOVRCURRACT. + USB_HPRT_PRTOVRCURRACT = 0x10 + // Position of PRTOVRCURRCHNG field. + USB_HPRT_PRTOVRCURRCHNG_Pos = 0x5 + // Bit mask of PRTOVRCURRCHNG field. + USB_HPRT_PRTOVRCURRCHNG_Msk = 0x20 + // Bit PRTOVRCURRCHNG. + USB_HPRT_PRTOVRCURRCHNG = 0x20 + // Position of PRTRES field. + USB_HPRT_PRTRES_Pos = 0x6 + // Bit mask of PRTRES field. + USB_HPRT_PRTRES_Msk = 0x40 + // Bit PRTRES. + USB_HPRT_PRTRES = 0x40 + // Position of PRTSUSP field. + USB_HPRT_PRTSUSP_Pos = 0x7 + // Bit mask of PRTSUSP field. + USB_HPRT_PRTSUSP_Msk = 0x80 + // Bit PRTSUSP. + USB_HPRT_PRTSUSP = 0x80 + // Position of PRTRST field. + USB_HPRT_PRTRST_Pos = 0x8 + // Bit mask of PRTRST field. + USB_HPRT_PRTRST_Msk = 0x100 + // Bit PRTRST. + USB_HPRT_PRTRST = 0x100 + // Position of PRTLNSTS field. + USB_HPRT_PRTLNSTS_Pos = 0xa + // Bit mask of PRTLNSTS field. + USB_HPRT_PRTLNSTS_Msk = 0xc00 + // Position of PRTPWR field. + USB_HPRT_PRTPWR_Pos = 0xc + // Bit mask of PRTPWR field. + USB_HPRT_PRTPWR_Msk = 0x1000 + // Bit PRTPWR. + USB_HPRT_PRTPWR = 0x1000 + // Position of PRTTSTCTL field. + USB_HPRT_PRTTSTCTL_Pos = 0xd + // Bit mask of PRTTSTCTL field. + USB_HPRT_PRTTSTCTL_Msk = 0x1e000 + // Position of PRTSPD field. + USB_HPRT_PRTSPD_Pos = 0x11 + // Bit mask of PRTSPD field. + USB_HPRT_PRTSPD_Msk = 0x60000 + + // HCCHAR0 + // Position of H_MPS0 field. + USB_HCCHAR0_H_MPS0_Pos = 0x0 + // Bit mask of H_MPS0 field. + USB_HCCHAR0_H_MPS0_Msk = 0x7ff + // Position of H_EPNUM0 field. + USB_HCCHAR0_H_EPNUM0_Pos = 0xb + // Bit mask of H_EPNUM0 field. + USB_HCCHAR0_H_EPNUM0_Msk = 0x7800 + // Position of H_EPDIR0 field. + USB_HCCHAR0_H_EPDIR0_Pos = 0xf + // Bit mask of H_EPDIR0 field. + USB_HCCHAR0_H_EPDIR0_Msk = 0x8000 + // Bit H_EPDIR0. + USB_HCCHAR0_H_EPDIR0 = 0x8000 + // Position of H_LSPDDEV0 field. + USB_HCCHAR0_H_LSPDDEV0_Pos = 0x11 + // Bit mask of H_LSPDDEV0 field. + USB_HCCHAR0_H_LSPDDEV0_Msk = 0x20000 + // Bit H_LSPDDEV0. + USB_HCCHAR0_H_LSPDDEV0 = 0x20000 + // Position of H_EPTYPE0 field. + USB_HCCHAR0_H_EPTYPE0_Pos = 0x12 + // Bit mask of H_EPTYPE0 field. + USB_HCCHAR0_H_EPTYPE0_Msk = 0xc0000 + // Position of H_EC0 field. + USB_HCCHAR0_H_EC0_Pos = 0x15 + // Bit mask of H_EC0 field. + USB_HCCHAR0_H_EC0_Msk = 0x200000 + // Bit H_EC0. + USB_HCCHAR0_H_EC0 = 0x200000 + // Position of H_DEVADDR0 field. + USB_HCCHAR0_H_DEVADDR0_Pos = 0x16 + // Bit mask of H_DEVADDR0 field. + USB_HCCHAR0_H_DEVADDR0_Msk = 0x1fc00000 + // Position of H_ODDFRM0 field. + USB_HCCHAR0_H_ODDFRM0_Pos = 0x1d + // Bit mask of H_ODDFRM0 field. + USB_HCCHAR0_H_ODDFRM0_Msk = 0x20000000 + // Bit H_ODDFRM0. + USB_HCCHAR0_H_ODDFRM0 = 0x20000000 + // Position of H_CHDIS0 field. + USB_HCCHAR0_H_CHDIS0_Pos = 0x1e + // Bit mask of H_CHDIS0 field. + USB_HCCHAR0_H_CHDIS0_Msk = 0x40000000 + // Bit H_CHDIS0. + USB_HCCHAR0_H_CHDIS0 = 0x40000000 + // Position of H_CHENA0 field. + USB_HCCHAR0_H_CHENA0_Pos = 0x1f + // Bit mask of H_CHENA0 field. + USB_HCCHAR0_H_CHENA0_Msk = 0x80000000 + // Bit H_CHENA0. + USB_HCCHAR0_H_CHENA0 = 0x80000000 + + // HCINT0 + // Position of H_XFERCOMPL0 field. + USB_HCINT0_H_XFERCOMPL0_Pos = 0x0 + // Bit mask of H_XFERCOMPL0 field. + USB_HCINT0_H_XFERCOMPL0_Msk = 0x1 + // Bit H_XFERCOMPL0. + USB_HCINT0_H_XFERCOMPL0 = 0x1 + // Position of H_CHHLTD0 field. + USB_HCINT0_H_CHHLTD0_Pos = 0x1 + // Bit mask of H_CHHLTD0 field. + USB_HCINT0_H_CHHLTD0_Msk = 0x2 + // Bit H_CHHLTD0. + USB_HCINT0_H_CHHLTD0 = 0x2 + // Position of H_AHBERR0 field. + USB_HCINT0_H_AHBERR0_Pos = 0x2 + // Bit mask of H_AHBERR0 field. + USB_HCINT0_H_AHBERR0_Msk = 0x4 + // Bit H_AHBERR0. + USB_HCINT0_H_AHBERR0 = 0x4 + // Position of H_STALL0 field. + USB_HCINT0_H_STALL0_Pos = 0x3 + // Bit mask of H_STALL0 field. + USB_HCINT0_H_STALL0_Msk = 0x8 + // Bit H_STALL0. + USB_HCINT0_H_STALL0 = 0x8 + // Position of H_NACK0 field. + USB_HCINT0_H_NACK0_Pos = 0x4 + // Bit mask of H_NACK0 field. + USB_HCINT0_H_NACK0_Msk = 0x10 + // Bit H_NACK0. + USB_HCINT0_H_NACK0 = 0x10 + // Position of H_ACK0 field. + USB_HCINT0_H_ACK0_Pos = 0x5 + // Bit mask of H_ACK0 field. + USB_HCINT0_H_ACK0_Msk = 0x20 + // Bit H_ACK0. + USB_HCINT0_H_ACK0 = 0x20 + // Position of H_NYET0 field. + USB_HCINT0_H_NYET0_Pos = 0x6 + // Bit mask of H_NYET0 field. + USB_HCINT0_H_NYET0_Msk = 0x40 + // Bit H_NYET0. + USB_HCINT0_H_NYET0 = 0x40 + // Position of H_XACTERR0 field. + USB_HCINT0_H_XACTERR0_Pos = 0x7 + // Bit mask of H_XACTERR0 field. + USB_HCINT0_H_XACTERR0_Msk = 0x80 + // Bit H_XACTERR0. + USB_HCINT0_H_XACTERR0 = 0x80 + // Position of H_BBLERR0 field. + USB_HCINT0_H_BBLERR0_Pos = 0x8 + // Bit mask of H_BBLERR0 field. + USB_HCINT0_H_BBLERR0_Msk = 0x100 + // Bit H_BBLERR0. + USB_HCINT0_H_BBLERR0 = 0x100 + // Position of H_FRMOVRUN0 field. + USB_HCINT0_H_FRMOVRUN0_Pos = 0x9 + // Bit mask of H_FRMOVRUN0 field. + USB_HCINT0_H_FRMOVRUN0_Msk = 0x200 + // Bit H_FRMOVRUN0. + USB_HCINT0_H_FRMOVRUN0 = 0x200 + // Position of H_DATATGLERR0 field. + USB_HCINT0_H_DATATGLERR0_Pos = 0xa + // Bit mask of H_DATATGLERR0 field. + USB_HCINT0_H_DATATGLERR0_Msk = 0x400 + // Bit H_DATATGLERR0. + USB_HCINT0_H_DATATGLERR0 = 0x400 + // Position of H_BNAINTR0 field. + USB_HCINT0_H_BNAINTR0_Pos = 0xb + // Bit mask of H_BNAINTR0 field. + USB_HCINT0_H_BNAINTR0_Msk = 0x800 + // Bit H_BNAINTR0. + USB_HCINT0_H_BNAINTR0 = 0x800 + // Position of H_XCS_XACT_ERR0 field. + USB_HCINT0_H_XCS_XACT_ERR0_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR0 field. + USB_HCINT0_H_XCS_XACT_ERR0_Msk = 0x1000 + // Bit H_XCS_XACT_ERR0. + USB_HCINT0_H_XCS_XACT_ERR0 = 0x1000 + // Position of H_DESC_LST_ROLLINTR0 field. + USB_HCINT0_H_DESC_LST_ROLLINTR0_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR0 field. + USB_HCINT0_H_DESC_LST_ROLLINTR0_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR0. + USB_HCINT0_H_DESC_LST_ROLLINTR0 = 0x2000 + + // HCINTMSK0 + // Position of H_XFERCOMPLMSK0 field. + USB_HCINTMSK0_H_XFERCOMPLMSK0_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK0 field. + USB_HCINTMSK0_H_XFERCOMPLMSK0_Msk = 0x1 + // Bit H_XFERCOMPLMSK0. + USB_HCINTMSK0_H_XFERCOMPLMSK0 = 0x1 + // Position of H_CHHLTDMSK0 field. + USB_HCINTMSK0_H_CHHLTDMSK0_Pos = 0x1 + // Bit mask of H_CHHLTDMSK0 field. + USB_HCINTMSK0_H_CHHLTDMSK0_Msk = 0x2 + // Bit H_CHHLTDMSK0. + USB_HCINTMSK0_H_CHHLTDMSK0 = 0x2 + // Position of H_AHBERRMSK0 field. + USB_HCINTMSK0_H_AHBERRMSK0_Pos = 0x2 + // Bit mask of H_AHBERRMSK0 field. + USB_HCINTMSK0_H_AHBERRMSK0_Msk = 0x4 + // Bit H_AHBERRMSK0. + USB_HCINTMSK0_H_AHBERRMSK0 = 0x4 + // Position of H_STALLMSK0 field. + USB_HCINTMSK0_H_STALLMSK0_Pos = 0x3 + // Bit mask of H_STALLMSK0 field. + USB_HCINTMSK0_H_STALLMSK0_Msk = 0x8 + // Bit H_STALLMSK0. + USB_HCINTMSK0_H_STALLMSK0 = 0x8 + // Position of H_NAKMSK0 field. + USB_HCINTMSK0_H_NAKMSK0_Pos = 0x4 + // Bit mask of H_NAKMSK0 field. + USB_HCINTMSK0_H_NAKMSK0_Msk = 0x10 + // Bit H_NAKMSK0. + USB_HCINTMSK0_H_NAKMSK0 = 0x10 + // Position of H_ACKMSK0 field. + USB_HCINTMSK0_H_ACKMSK0_Pos = 0x5 + // Bit mask of H_ACKMSK0 field. + USB_HCINTMSK0_H_ACKMSK0_Msk = 0x20 + // Bit H_ACKMSK0. + USB_HCINTMSK0_H_ACKMSK0 = 0x20 + // Position of H_NYETMSK0 field. + USB_HCINTMSK0_H_NYETMSK0_Pos = 0x6 + // Bit mask of H_NYETMSK0 field. + USB_HCINTMSK0_H_NYETMSK0_Msk = 0x40 + // Bit H_NYETMSK0. + USB_HCINTMSK0_H_NYETMSK0 = 0x40 + // Position of H_XACTERRMSK0 field. + USB_HCINTMSK0_H_XACTERRMSK0_Pos = 0x7 + // Bit mask of H_XACTERRMSK0 field. + USB_HCINTMSK0_H_XACTERRMSK0_Msk = 0x80 + // Bit H_XACTERRMSK0. + USB_HCINTMSK0_H_XACTERRMSK0 = 0x80 + // Position of H_BBLERRMSK0 field. + USB_HCINTMSK0_H_BBLERRMSK0_Pos = 0x8 + // Bit mask of H_BBLERRMSK0 field. + USB_HCINTMSK0_H_BBLERRMSK0_Msk = 0x100 + // Bit H_BBLERRMSK0. + USB_HCINTMSK0_H_BBLERRMSK0 = 0x100 + // Position of H_FRMOVRUNMSK0 field. + USB_HCINTMSK0_H_FRMOVRUNMSK0_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK0 field. + USB_HCINTMSK0_H_FRMOVRUNMSK0_Msk = 0x200 + // Bit H_FRMOVRUNMSK0. + USB_HCINTMSK0_H_FRMOVRUNMSK0 = 0x200 + // Position of H_DATATGLERRMSK0 field. + USB_HCINTMSK0_H_DATATGLERRMSK0_Pos = 0xa + // Bit mask of H_DATATGLERRMSK0 field. + USB_HCINTMSK0_H_DATATGLERRMSK0_Msk = 0x400 + // Bit H_DATATGLERRMSK0. + USB_HCINTMSK0_H_DATATGLERRMSK0 = 0x400 + // Position of H_BNAINTRMSK0 field. + USB_HCINTMSK0_H_BNAINTRMSK0_Pos = 0xb + // Bit mask of H_BNAINTRMSK0 field. + USB_HCINTMSK0_H_BNAINTRMSK0_Msk = 0x800 + // Bit H_BNAINTRMSK0. + USB_HCINTMSK0_H_BNAINTRMSK0 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK0 field. + USB_HCINTMSK0_H_DESC_LST_ROLLINTRMSK0_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK0 field. + USB_HCINTMSK0_H_DESC_LST_ROLLINTRMSK0_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK0. + USB_HCINTMSK0_H_DESC_LST_ROLLINTRMSK0 = 0x2000 + + // HCTSIZ0 + // Position of H_XFERSIZE0 field. + USB_HCTSIZ0_H_XFERSIZE0_Pos = 0x0 + // Bit mask of H_XFERSIZE0 field. + USB_HCTSIZ0_H_XFERSIZE0_Msk = 0x7ffff + // Position of H_PKTCNT0 field. + USB_HCTSIZ0_H_PKTCNT0_Pos = 0x13 + // Bit mask of H_PKTCNT0 field. + USB_HCTSIZ0_H_PKTCNT0_Msk = 0x1ff80000 + // Position of H_PID0 field. + USB_HCTSIZ0_H_PID0_Pos = 0x1d + // Bit mask of H_PID0 field. + USB_HCTSIZ0_H_PID0_Msk = 0x60000000 + // Position of H_DOPNG0 field. + USB_HCTSIZ0_H_DOPNG0_Pos = 0x1f + // Bit mask of H_DOPNG0 field. + USB_HCTSIZ0_H_DOPNG0_Msk = 0x80000000 + // Bit H_DOPNG0. + USB_HCTSIZ0_H_DOPNG0 = 0x80000000 + + // HCDMA0 + // Position of H_DMAADDR0 field. + USB_HCDMA0_H_DMAADDR0_Pos = 0x0 + // Bit mask of H_DMAADDR0 field. + USB_HCDMA0_H_DMAADDR0_Msk = 0xffffffff + + // HCDMAB0 + // Position of H_HCDMAB0 field. + USB_HCDMAB0_H_HCDMAB0_Pos = 0x0 + // Bit mask of H_HCDMAB0 field. + USB_HCDMAB0_H_HCDMAB0_Msk = 0xffffffff + + // HCCHAR1 + // Position of H_MPS1 field. + USB_HCCHAR1_H_MPS1_Pos = 0x0 + // Bit mask of H_MPS1 field. + USB_HCCHAR1_H_MPS1_Msk = 0x7ff + // Position of H_EPNUM1 field. + USB_HCCHAR1_H_EPNUM1_Pos = 0xb + // Bit mask of H_EPNUM1 field. + USB_HCCHAR1_H_EPNUM1_Msk = 0x7800 + // Position of H_EPDIR1 field. + USB_HCCHAR1_H_EPDIR1_Pos = 0xf + // Bit mask of H_EPDIR1 field. + USB_HCCHAR1_H_EPDIR1_Msk = 0x8000 + // Bit H_EPDIR1. + USB_HCCHAR1_H_EPDIR1 = 0x8000 + // Position of H_LSPDDEV1 field. + USB_HCCHAR1_H_LSPDDEV1_Pos = 0x11 + // Bit mask of H_LSPDDEV1 field. + USB_HCCHAR1_H_LSPDDEV1_Msk = 0x20000 + // Bit H_LSPDDEV1. + USB_HCCHAR1_H_LSPDDEV1 = 0x20000 + // Position of H_EPTYPE1 field. + USB_HCCHAR1_H_EPTYPE1_Pos = 0x12 + // Bit mask of H_EPTYPE1 field. + USB_HCCHAR1_H_EPTYPE1_Msk = 0xc0000 + // Position of H_EC1 field. + USB_HCCHAR1_H_EC1_Pos = 0x15 + // Bit mask of H_EC1 field. + USB_HCCHAR1_H_EC1_Msk = 0x200000 + // Bit H_EC1. + USB_HCCHAR1_H_EC1 = 0x200000 + // Position of H_DEVADDR1 field. + USB_HCCHAR1_H_DEVADDR1_Pos = 0x16 + // Bit mask of H_DEVADDR1 field. + USB_HCCHAR1_H_DEVADDR1_Msk = 0x1fc00000 + // Position of H_ODDFRM1 field. + USB_HCCHAR1_H_ODDFRM1_Pos = 0x1d + // Bit mask of H_ODDFRM1 field. + USB_HCCHAR1_H_ODDFRM1_Msk = 0x20000000 + // Bit H_ODDFRM1. + USB_HCCHAR1_H_ODDFRM1 = 0x20000000 + // Position of H_CHDIS1 field. + USB_HCCHAR1_H_CHDIS1_Pos = 0x1e + // Bit mask of H_CHDIS1 field. + USB_HCCHAR1_H_CHDIS1_Msk = 0x40000000 + // Bit H_CHDIS1. + USB_HCCHAR1_H_CHDIS1 = 0x40000000 + // Position of H_CHENA1 field. + USB_HCCHAR1_H_CHENA1_Pos = 0x1f + // Bit mask of H_CHENA1 field. + USB_HCCHAR1_H_CHENA1_Msk = 0x80000000 + // Bit H_CHENA1. + USB_HCCHAR1_H_CHENA1 = 0x80000000 + + // HCINT1 + // Position of H_XFERCOMPL1 field. + USB_HCINT1_H_XFERCOMPL1_Pos = 0x0 + // Bit mask of H_XFERCOMPL1 field. + USB_HCINT1_H_XFERCOMPL1_Msk = 0x1 + // Bit H_XFERCOMPL1. + USB_HCINT1_H_XFERCOMPL1 = 0x1 + // Position of H_CHHLTD1 field. + USB_HCINT1_H_CHHLTD1_Pos = 0x1 + // Bit mask of H_CHHLTD1 field. + USB_HCINT1_H_CHHLTD1_Msk = 0x2 + // Bit H_CHHLTD1. + USB_HCINT1_H_CHHLTD1 = 0x2 + // Position of H_AHBERR1 field. + USB_HCINT1_H_AHBERR1_Pos = 0x2 + // Bit mask of H_AHBERR1 field. + USB_HCINT1_H_AHBERR1_Msk = 0x4 + // Bit H_AHBERR1. + USB_HCINT1_H_AHBERR1 = 0x4 + // Position of H_STALL1 field. + USB_HCINT1_H_STALL1_Pos = 0x3 + // Bit mask of H_STALL1 field. + USB_HCINT1_H_STALL1_Msk = 0x8 + // Bit H_STALL1. + USB_HCINT1_H_STALL1 = 0x8 + // Position of H_NACK1 field. + USB_HCINT1_H_NACK1_Pos = 0x4 + // Bit mask of H_NACK1 field. + USB_HCINT1_H_NACK1_Msk = 0x10 + // Bit H_NACK1. + USB_HCINT1_H_NACK1 = 0x10 + // Position of H_ACK1 field. + USB_HCINT1_H_ACK1_Pos = 0x5 + // Bit mask of H_ACK1 field. + USB_HCINT1_H_ACK1_Msk = 0x20 + // Bit H_ACK1. + USB_HCINT1_H_ACK1 = 0x20 + // Position of H_NYET1 field. + USB_HCINT1_H_NYET1_Pos = 0x6 + // Bit mask of H_NYET1 field. + USB_HCINT1_H_NYET1_Msk = 0x40 + // Bit H_NYET1. + USB_HCINT1_H_NYET1 = 0x40 + // Position of H_XACTERR1 field. + USB_HCINT1_H_XACTERR1_Pos = 0x7 + // Bit mask of H_XACTERR1 field. + USB_HCINT1_H_XACTERR1_Msk = 0x80 + // Bit H_XACTERR1. + USB_HCINT1_H_XACTERR1 = 0x80 + // Position of H_BBLERR1 field. + USB_HCINT1_H_BBLERR1_Pos = 0x8 + // Bit mask of H_BBLERR1 field. + USB_HCINT1_H_BBLERR1_Msk = 0x100 + // Bit H_BBLERR1. + USB_HCINT1_H_BBLERR1 = 0x100 + // Position of H_FRMOVRUN1 field. + USB_HCINT1_H_FRMOVRUN1_Pos = 0x9 + // Bit mask of H_FRMOVRUN1 field. + USB_HCINT1_H_FRMOVRUN1_Msk = 0x200 + // Bit H_FRMOVRUN1. + USB_HCINT1_H_FRMOVRUN1 = 0x200 + // Position of H_DATATGLERR1 field. + USB_HCINT1_H_DATATGLERR1_Pos = 0xa + // Bit mask of H_DATATGLERR1 field. + USB_HCINT1_H_DATATGLERR1_Msk = 0x400 + // Bit H_DATATGLERR1. + USB_HCINT1_H_DATATGLERR1 = 0x400 + // Position of H_BNAINTR1 field. + USB_HCINT1_H_BNAINTR1_Pos = 0xb + // Bit mask of H_BNAINTR1 field. + USB_HCINT1_H_BNAINTR1_Msk = 0x800 + // Bit H_BNAINTR1. + USB_HCINT1_H_BNAINTR1 = 0x800 + // Position of H_XCS_XACT_ERR1 field. + USB_HCINT1_H_XCS_XACT_ERR1_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR1 field. + USB_HCINT1_H_XCS_XACT_ERR1_Msk = 0x1000 + // Bit H_XCS_XACT_ERR1. + USB_HCINT1_H_XCS_XACT_ERR1 = 0x1000 + // Position of H_DESC_LST_ROLLINTR1 field. + USB_HCINT1_H_DESC_LST_ROLLINTR1_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR1 field. + USB_HCINT1_H_DESC_LST_ROLLINTR1_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR1. + USB_HCINT1_H_DESC_LST_ROLLINTR1 = 0x2000 + + // HCINTMSK1 + // Position of H_XFERCOMPLMSK1 field. + USB_HCINTMSK1_H_XFERCOMPLMSK1_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK1 field. + USB_HCINTMSK1_H_XFERCOMPLMSK1_Msk = 0x1 + // Bit H_XFERCOMPLMSK1. + USB_HCINTMSK1_H_XFERCOMPLMSK1 = 0x1 + // Position of H_CHHLTDMSK1 field. + USB_HCINTMSK1_H_CHHLTDMSK1_Pos = 0x1 + // Bit mask of H_CHHLTDMSK1 field. + USB_HCINTMSK1_H_CHHLTDMSK1_Msk = 0x2 + // Bit H_CHHLTDMSK1. + USB_HCINTMSK1_H_CHHLTDMSK1 = 0x2 + // Position of H_AHBERRMSK1 field. + USB_HCINTMSK1_H_AHBERRMSK1_Pos = 0x2 + // Bit mask of H_AHBERRMSK1 field. + USB_HCINTMSK1_H_AHBERRMSK1_Msk = 0x4 + // Bit H_AHBERRMSK1. + USB_HCINTMSK1_H_AHBERRMSK1 = 0x4 + // Position of H_STALLMSK1 field. + USB_HCINTMSK1_H_STALLMSK1_Pos = 0x3 + // Bit mask of H_STALLMSK1 field. + USB_HCINTMSK1_H_STALLMSK1_Msk = 0x8 + // Bit H_STALLMSK1. + USB_HCINTMSK1_H_STALLMSK1 = 0x8 + // Position of H_NAKMSK1 field. + USB_HCINTMSK1_H_NAKMSK1_Pos = 0x4 + // Bit mask of H_NAKMSK1 field. + USB_HCINTMSK1_H_NAKMSK1_Msk = 0x10 + // Bit H_NAKMSK1. + USB_HCINTMSK1_H_NAKMSK1 = 0x10 + // Position of H_ACKMSK1 field. + USB_HCINTMSK1_H_ACKMSK1_Pos = 0x5 + // Bit mask of H_ACKMSK1 field. + USB_HCINTMSK1_H_ACKMSK1_Msk = 0x20 + // Bit H_ACKMSK1. + USB_HCINTMSK1_H_ACKMSK1 = 0x20 + // Position of H_NYETMSK1 field. + USB_HCINTMSK1_H_NYETMSK1_Pos = 0x6 + // Bit mask of H_NYETMSK1 field. + USB_HCINTMSK1_H_NYETMSK1_Msk = 0x40 + // Bit H_NYETMSK1. + USB_HCINTMSK1_H_NYETMSK1 = 0x40 + // Position of H_XACTERRMSK1 field. + USB_HCINTMSK1_H_XACTERRMSK1_Pos = 0x7 + // Bit mask of H_XACTERRMSK1 field. + USB_HCINTMSK1_H_XACTERRMSK1_Msk = 0x80 + // Bit H_XACTERRMSK1. + USB_HCINTMSK1_H_XACTERRMSK1 = 0x80 + // Position of H_BBLERRMSK1 field. + USB_HCINTMSK1_H_BBLERRMSK1_Pos = 0x8 + // Bit mask of H_BBLERRMSK1 field. + USB_HCINTMSK1_H_BBLERRMSK1_Msk = 0x100 + // Bit H_BBLERRMSK1. + USB_HCINTMSK1_H_BBLERRMSK1 = 0x100 + // Position of H_FRMOVRUNMSK1 field. + USB_HCINTMSK1_H_FRMOVRUNMSK1_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK1 field. + USB_HCINTMSK1_H_FRMOVRUNMSK1_Msk = 0x200 + // Bit H_FRMOVRUNMSK1. + USB_HCINTMSK1_H_FRMOVRUNMSK1 = 0x200 + // Position of H_DATATGLERRMSK1 field. + USB_HCINTMSK1_H_DATATGLERRMSK1_Pos = 0xa + // Bit mask of H_DATATGLERRMSK1 field. + USB_HCINTMSK1_H_DATATGLERRMSK1_Msk = 0x400 + // Bit H_DATATGLERRMSK1. + USB_HCINTMSK1_H_DATATGLERRMSK1 = 0x400 + // Position of H_BNAINTRMSK1 field. + USB_HCINTMSK1_H_BNAINTRMSK1_Pos = 0xb + // Bit mask of H_BNAINTRMSK1 field. + USB_HCINTMSK1_H_BNAINTRMSK1_Msk = 0x800 + // Bit H_BNAINTRMSK1. + USB_HCINTMSK1_H_BNAINTRMSK1 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK1 field. + USB_HCINTMSK1_H_DESC_LST_ROLLINTRMSK1_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK1 field. + USB_HCINTMSK1_H_DESC_LST_ROLLINTRMSK1_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK1. + USB_HCINTMSK1_H_DESC_LST_ROLLINTRMSK1 = 0x2000 + + // HCTSIZ1 + // Position of H_XFERSIZE1 field. + USB_HCTSIZ1_H_XFERSIZE1_Pos = 0x0 + // Bit mask of H_XFERSIZE1 field. + USB_HCTSIZ1_H_XFERSIZE1_Msk = 0x7ffff + // Position of H_PKTCNT1 field. + USB_HCTSIZ1_H_PKTCNT1_Pos = 0x13 + // Bit mask of H_PKTCNT1 field. + USB_HCTSIZ1_H_PKTCNT1_Msk = 0x1ff80000 + // Position of H_PID1 field. + USB_HCTSIZ1_H_PID1_Pos = 0x1d + // Bit mask of H_PID1 field. + USB_HCTSIZ1_H_PID1_Msk = 0x60000000 + // Position of H_DOPNG1 field. + USB_HCTSIZ1_H_DOPNG1_Pos = 0x1f + // Bit mask of H_DOPNG1 field. + USB_HCTSIZ1_H_DOPNG1_Msk = 0x80000000 + // Bit H_DOPNG1. + USB_HCTSIZ1_H_DOPNG1 = 0x80000000 + + // HCDMA1 + // Position of H_DMAADDR1 field. + USB_HCDMA1_H_DMAADDR1_Pos = 0x0 + // Bit mask of H_DMAADDR1 field. + USB_HCDMA1_H_DMAADDR1_Msk = 0xffffffff + + // HCDMAB1 + // Position of H_HCDMAB1 field. + USB_HCDMAB1_H_HCDMAB1_Pos = 0x0 + // Bit mask of H_HCDMAB1 field. + USB_HCDMAB1_H_HCDMAB1_Msk = 0xffffffff + + // HCCHAR2 + // Position of H_MPS2 field. + USB_HCCHAR2_H_MPS2_Pos = 0x0 + // Bit mask of H_MPS2 field. + USB_HCCHAR2_H_MPS2_Msk = 0x7ff + // Position of H_EPNUM2 field. + USB_HCCHAR2_H_EPNUM2_Pos = 0xb + // Bit mask of H_EPNUM2 field. + USB_HCCHAR2_H_EPNUM2_Msk = 0x7800 + // Position of H_EPDIR2 field. + USB_HCCHAR2_H_EPDIR2_Pos = 0xf + // Bit mask of H_EPDIR2 field. + USB_HCCHAR2_H_EPDIR2_Msk = 0x8000 + // Bit H_EPDIR2. + USB_HCCHAR2_H_EPDIR2 = 0x8000 + // Position of H_LSPDDEV2 field. + USB_HCCHAR2_H_LSPDDEV2_Pos = 0x11 + // Bit mask of H_LSPDDEV2 field. + USB_HCCHAR2_H_LSPDDEV2_Msk = 0x20000 + // Bit H_LSPDDEV2. + USB_HCCHAR2_H_LSPDDEV2 = 0x20000 + // Position of H_EPTYPE2 field. + USB_HCCHAR2_H_EPTYPE2_Pos = 0x12 + // Bit mask of H_EPTYPE2 field. + USB_HCCHAR2_H_EPTYPE2_Msk = 0xc0000 + // Position of H_EC2 field. + USB_HCCHAR2_H_EC2_Pos = 0x15 + // Bit mask of H_EC2 field. + USB_HCCHAR2_H_EC2_Msk = 0x200000 + // Bit H_EC2. + USB_HCCHAR2_H_EC2 = 0x200000 + // Position of H_DEVADDR2 field. + USB_HCCHAR2_H_DEVADDR2_Pos = 0x16 + // Bit mask of H_DEVADDR2 field. + USB_HCCHAR2_H_DEVADDR2_Msk = 0x1fc00000 + // Position of H_ODDFRM2 field. + USB_HCCHAR2_H_ODDFRM2_Pos = 0x1d + // Bit mask of H_ODDFRM2 field. + USB_HCCHAR2_H_ODDFRM2_Msk = 0x20000000 + // Bit H_ODDFRM2. + USB_HCCHAR2_H_ODDFRM2 = 0x20000000 + // Position of H_CHDIS2 field. + USB_HCCHAR2_H_CHDIS2_Pos = 0x1e + // Bit mask of H_CHDIS2 field. + USB_HCCHAR2_H_CHDIS2_Msk = 0x40000000 + // Bit H_CHDIS2. + USB_HCCHAR2_H_CHDIS2 = 0x40000000 + // Position of H_CHENA2 field. + USB_HCCHAR2_H_CHENA2_Pos = 0x1f + // Bit mask of H_CHENA2 field. + USB_HCCHAR2_H_CHENA2_Msk = 0x80000000 + // Bit H_CHENA2. + USB_HCCHAR2_H_CHENA2 = 0x80000000 + + // HCINT2 + // Position of H_XFERCOMPL2 field. + USB_HCINT2_H_XFERCOMPL2_Pos = 0x0 + // Bit mask of H_XFERCOMPL2 field. + USB_HCINT2_H_XFERCOMPL2_Msk = 0x1 + // Bit H_XFERCOMPL2. + USB_HCINT2_H_XFERCOMPL2 = 0x1 + // Position of H_CHHLTD2 field. + USB_HCINT2_H_CHHLTD2_Pos = 0x1 + // Bit mask of H_CHHLTD2 field. + USB_HCINT2_H_CHHLTD2_Msk = 0x2 + // Bit H_CHHLTD2. + USB_HCINT2_H_CHHLTD2 = 0x2 + // Position of H_AHBERR2 field. + USB_HCINT2_H_AHBERR2_Pos = 0x2 + // Bit mask of H_AHBERR2 field. + USB_HCINT2_H_AHBERR2_Msk = 0x4 + // Bit H_AHBERR2. + USB_HCINT2_H_AHBERR2 = 0x4 + // Position of H_STALL2 field. + USB_HCINT2_H_STALL2_Pos = 0x3 + // Bit mask of H_STALL2 field. + USB_HCINT2_H_STALL2_Msk = 0x8 + // Bit H_STALL2. + USB_HCINT2_H_STALL2 = 0x8 + // Position of H_NACK2 field. + USB_HCINT2_H_NACK2_Pos = 0x4 + // Bit mask of H_NACK2 field. + USB_HCINT2_H_NACK2_Msk = 0x10 + // Bit H_NACK2. + USB_HCINT2_H_NACK2 = 0x10 + // Position of H_ACK2 field. + USB_HCINT2_H_ACK2_Pos = 0x5 + // Bit mask of H_ACK2 field. + USB_HCINT2_H_ACK2_Msk = 0x20 + // Bit H_ACK2. + USB_HCINT2_H_ACK2 = 0x20 + // Position of H_NYET2 field. + USB_HCINT2_H_NYET2_Pos = 0x6 + // Bit mask of H_NYET2 field. + USB_HCINT2_H_NYET2_Msk = 0x40 + // Bit H_NYET2. + USB_HCINT2_H_NYET2 = 0x40 + // Position of H_XACTERR2 field. + USB_HCINT2_H_XACTERR2_Pos = 0x7 + // Bit mask of H_XACTERR2 field. + USB_HCINT2_H_XACTERR2_Msk = 0x80 + // Bit H_XACTERR2. + USB_HCINT2_H_XACTERR2 = 0x80 + // Position of H_BBLERR2 field. + USB_HCINT2_H_BBLERR2_Pos = 0x8 + // Bit mask of H_BBLERR2 field. + USB_HCINT2_H_BBLERR2_Msk = 0x100 + // Bit H_BBLERR2. + USB_HCINT2_H_BBLERR2 = 0x100 + // Position of H_FRMOVRUN2 field. + USB_HCINT2_H_FRMOVRUN2_Pos = 0x9 + // Bit mask of H_FRMOVRUN2 field. + USB_HCINT2_H_FRMOVRUN2_Msk = 0x200 + // Bit H_FRMOVRUN2. + USB_HCINT2_H_FRMOVRUN2 = 0x200 + // Position of H_DATATGLERR2 field. + USB_HCINT2_H_DATATGLERR2_Pos = 0xa + // Bit mask of H_DATATGLERR2 field. + USB_HCINT2_H_DATATGLERR2_Msk = 0x400 + // Bit H_DATATGLERR2. + USB_HCINT2_H_DATATGLERR2 = 0x400 + // Position of H_BNAINTR2 field. + USB_HCINT2_H_BNAINTR2_Pos = 0xb + // Bit mask of H_BNAINTR2 field. + USB_HCINT2_H_BNAINTR2_Msk = 0x800 + // Bit H_BNAINTR2. + USB_HCINT2_H_BNAINTR2 = 0x800 + // Position of H_XCS_XACT_ERR2 field. + USB_HCINT2_H_XCS_XACT_ERR2_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR2 field. + USB_HCINT2_H_XCS_XACT_ERR2_Msk = 0x1000 + // Bit H_XCS_XACT_ERR2. + USB_HCINT2_H_XCS_XACT_ERR2 = 0x1000 + // Position of H_DESC_LST_ROLLINTR2 field. + USB_HCINT2_H_DESC_LST_ROLLINTR2_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR2 field. + USB_HCINT2_H_DESC_LST_ROLLINTR2_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR2. + USB_HCINT2_H_DESC_LST_ROLLINTR2 = 0x2000 + + // HCINTMSK2 + // Position of H_XFERCOMPLMSK2 field. + USB_HCINTMSK2_H_XFERCOMPLMSK2_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK2 field. + USB_HCINTMSK2_H_XFERCOMPLMSK2_Msk = 0x1 + // Bit H_XFERCOMPLMSK2. + USB_HCINTMSK2_H_XFERCOMPLMSK2 = 0x1 + // Position of H_CHHLTDMSK2 field. + USB_HCINTMSK2_H_CHHLTDMSK2_Pos = 0x1 + // Bit mask of H_CHHLTDMSK2 field. + USB_HCINTMSK2_H_CHHLTDMSK2_Msk = 0x2 + // Bit H_CHHLTDMSK2. + USB_HCINTMSK2_H_CHHLTDMSK2 = 0x2 + // Position of H_AHBERRMSK2 field. + USB_HCINTMSK2_H_AHBERRMSK2_Pos = 0x2 + // Bit mask of H_AHBERRMSK2 field. + USB_HCINTMSK2_H_AHBERRMSK2_Msk = 0x4 + // Bit H_AHBERRMSK2. + USB_HCINTMSK2_H_AHBERRMSK2 = 0x4 + // Position of H_STALLMSK2 field. + USB_HCINTMSK2_H_STALLMSK2_Pos = 0x3 + // Bit mask of H_STALLMSK2 field. + USB_HCINTMSK2_H_STALLMSK2_Msk = 0x8 + // Bit H_STALLMSK2. + USB_HCINTMSK2_H_STALLMSK2 = 0x8 + // Position of H_NAKMSK2 field. + USB_HCINTMSK2_H_NAKMSK2_Pos = 0x4 + // Bit mask of H_NAKMSK2 field. + USB_HCINTMSK2_H_NAKMSK2_Msk = 0x10 + // Bit H_NAKMSK2. + USB_HCINTMSK2_H_NAKMSK2 = 0x10 + // Position of H_ACKMSK2 field. + USB_HCINTMSK2_H_ACKMSK2_Pos = 0x5 + // Bit mask of H_ACKMSK2 field. + USB_HCINTMSK2_H_ACKMSK2_Msk = 0x20 + // Bit H_ACKMSK2. + USB_HCINTMSK2_H_ACKMSK2 = 0x20 + // Position of H_NYETMSK2 field. + USB_HCINTMSK2_H_NYETMSK2_Pos = 0x6 + // Bit mask of H_NYETMSK2 field. + USB_HCINTMSK2_H_NYETMSK2_Msk = 0x40 + // Bit H_NYETMSK2. + USB_HCINTMSK2_H_NYETMSK2 = 0x40 + // Position of H_XACTERRMSK2 field. + USB_HCINTMSK2_H_XACTERRMSK2_Pos = 0x7 + // Bit mask of H_XACTERRMSK2 field. + USB_HCINTMSK2_H_XACTERRMSK2_Msk = 0x80 + // Bit H_XACTERRMSK2. + USB_HCINTMSK2_H_XACTERRMSK2 = 0x80 + // Position of H_BBLERRMSK2 field. + USB_HCINTMSK2_H_BBLERRMSK2_Pos = 0x8 + // Bit mask of H_BBLERRMSK2 field. + USB_HCINTMSK2_H_BBLERRMSK2_Msk = 0x100 + // Bit H_BBLERRMSK2. + USB_HCINTMSK2_H_BBLERRMSK2 = 0x100 + // Position of H_FRMOVRUNMSK2 field. + USB_HCINTMSK2_H_FRMOVRUNMSK2_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK2 field. + USB_HCINTMSK2_H_FRMOVRUNMSK2_Msk = 0x200 + // Bit H_FRMOVRUNMSK2. + USB_HCINTMSK2_H_FRMOVRUNMSK2 = 0x200 + // Position of H_DATATGLERRMSK2 field. + USB_HCINTMSK2_H_DATATGLERRMSK2_Pos = 0xa + // Bit mask of H_DATATGLERRMSK2 field. + USB_HCINTMSK2_H_DATATGLERRMSK2_Msk = 0x400 + // Bit H_DATATGLERRMSK2. + USB_HCINTMSK2_H_DATATGLERRMSK2 = 0x400 + // Position of H_BNAINTRMSK2 field. + USB_HCINTMSK2_H_BNAINTRMSK2_Pos = 0xb + // Bit mask of H_BNAINTRMSK2 field. + USB_HCINTMSK2_H_BNAINTRMSK2_Msk = 0x800 + // Bit H_BNAINTRMSK2. + USB_HCINTMSK2_H_BNAINTRMSK2 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK2 field. + USB_HCINTMSK2_H_DESC_LST_ROLLINTRMSK2_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK2 field. + USB_HCINTMSK2_H_DESC_LST_ROLLINTRMSK2_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK2. + USB_HCINTMSK2_H_DESC_LST_ROLLINTRMSK2 = 0x2000 + + // HCTSIZ2 + // Position of H_XFERSIZE2 field. + USB_HCTSIZ2_H_XFERSIZE2_Pos = 0x0 + // Bit mask of H_XFERSIZE2 field. + USB_HCTSIZ2_H_XFERSIZE2_Msk = 0x7ffff + // Position of H_PKTCNT2 field. + USB_HCTSIZ2_H_PKTCNT2_Pos = 0x13 + // Bit mask of H_PKTCNT2 field. + USB_HCTSIZ2_H_PKTCNT2_Msk = 0x1ff80000 + // Position of H_PID2 field. + USB_HCTSIZ2_H_PID2_Pos = 0x1d + // Bit mask of H_PID2 field. + USB_HCTSIZ2_H_PID2_Msk = 0x60000000 + // Position of H_DOPNG2 field. + USB_HCTSIZ2_H_DOPNG2_Pos = 0x1f + // Bit mask of H_DOPNG2 field. + USB_HCTSIZ2_H_DOPNG2_Msk = 0x80000000 + // Bit H_DOPNG2. + USB_HCTSIZ2_H_DOPNG2 = 0x80000000 + + // HCDMA2 + // Position of H_DMAADDR2 field. + USB_HCDMA2_H_DMAADDR2_Pos = 0x0 + // Bit mask of H_DMAADDR2 field. + USB_HCDMA2_H_DMAADDR2_Msk = 0xffffffff + + // HCDMAB2 + // Position of H_HCDMAB2 field. + USB_HCDMAB2_H_HCDMAB2_Pos = 0x0 + // Bit mask of H_HCDMAB2 field. + USB_HCDMAB2_H_HCDMAB2_Msk = 0xffffffff + + // HCCHAR3 + // Position of H_MPS3 field. + USB_HCCHAR3_H_MPS3_Pos = 0x0 + // Bit mask of H_MPS3 field. + USB_HCCHAR3_H_MPS3_Msk = 0x7ff + // Position of H_EPNUM3 field. + USB_HCCHAR3_H_EPNUM3_Pos = 0xb + // Bit mask of H_EPNUM3 field. + USB_HCCHAR3_H_EPNUM3_Msk = 0x7800 + // Position of H_EPDIR3 field. + USB_HCCHAR3_H_EPDIR3_Pos = 0xf + // Bit mask of H_EPDIR3 field. + USB_HCCHAR3_H_EPDIR3_Msk = 0x8000 + // Bit H_EPDIR3. + USB_HCCHAR3_H_EPDIR3 = 0x8000 + // Position of H_LSPDDEV3 field. + USB_HCCHAR3_H_LSPDDEV3_Pos = 0x11 + // Bit mask of H_LSPDDEV3 field. + USB_HCCHAR3_H_LSPDDEV3_Msk = 0x20000 + // Bit H_LSPDDEV3. + USB_HCCHAR3_H_LSPDDEV3 = 0x20000 + // Position of H_EPTYPE3 field. + USB_HCCHAR3_H_EPTYPE3_Pos = 0x12 + // Bit mask of H_EPTYPE3 field. + USB_HCCHAR3_H_EPTYPE3_Msk = 0xc0000 + // Position of H_EC3 field. + USB_HCCHAR3_H_EC3_Pos = 0x15 + // Bit mask of H_EC3 field. + USB_HCCHAR3_H_EC3_Msk = 0x200000 + // Bit H_EC3. + USB_HCCHAR3_H_EC3 = 0x200000 + // Position of H_DEVADDR3 field. + USB_HCCHAR3_H_DEVADDR3_Pos = 0x16 + // Bit mask of H_DEVADDR3 field. + USB_HCCHAR3_H_DEVADDR3_Msk = 0x1fc00000 + // Position of H_ODDFRM3 field. + USB_HCCHAR3_H_ODDFRM3_Pos = 0x1d + // Bit mask of H_ODDFRM3 field. + USB_HCCHAR3_H_ODDFRM3_Msk = 0x20000000 + // Bit H_ODDFRM3. + USB_HCCHAR3_H_ODDFRM3 = 0x20000000 + // Position of H_CHDIS3 field. + USB_HCCHAR3_H_CHDIS3_Pos = 0x1e + // Bit mask of H_CHDIS3 field. + USB_HCCHAR3_H_CHDIS3_Msk = 0x40000000 + // Bit H_CHDIS3. + USB_HCCHAR3_H_CHDIS3 = 0x40000000 + // Position of H_CHENA3 field. + USB_HCCHAR3_H_CHENA3_Pos = 0x1f + // Bit mask of H_CHENA3 field. + USB_HCCHAR3_H_CHENA3_Msk = 0x80000000 + // Bit H_CHENA3. + USB_HCCHAR3_H_CHENA3 = 0x80000000 + + // HCINT3 + // Position of H_XFERCOMPL3 field. + USB_HCINT3_H_XFERCOMPL3_Pos = 0x0 + // Bit mask of H_XFERCOMPL3 field. + USB_HCINT3_H_XFERCOMPL3_Msk = 0x1 + // Bit H_XFERCOMPL3. + USB_HCINT3_H_XFERCOMPL3 = 0x1 + // Position of H_CHHLTD3 field. + USB_HCINT3_H_CHHLTD3_Pos = 0x1 + // Bit mask of H_CHHLTD3 field. + USB_HCINT3_H_CHHLTD3_Msk = 0x2 + // Bit H_CHHLTD3. + USB_HCINT3_H_CHHLTD3 = 0x2 + // Position of H_AHBERR3 field. + USB_HCINT3_H_AHBERR3_Pos = 0x2 + // Bit mask of H_AHBERR3 field. + USB_HCINT3_H_AHBERR3_Msk = 0x4 + // Bit H_AHBERR3. + USB_HCINT3_H_AHBERR3 = 0x4 + // Position of H_STALL3 field. + USB_HCINT3_H_STALL3_Pos = 0x3 + // Bit mask of H_STALL3 field. + USB_HCINT3_H_STALL3_Msk = 0x8 + // Bit H_STALL3. + USB_HCINT3_H_STALL3 = 0x8 + // Position of H_NACK3 field. + USB_HCINT3_H_NACK3_Pos = 0x4 + // Bit mask of H_NACK3 field. + USB_HCINT3_H_NACK3_Msk = 0x10 + // Bit H_NACK3. + USB_HCINT3_H_NACK3 = 0x10 + // Position of H_ACK3 field. + USB_HCINT3_H_ACK3_Pos = 0x5 + // Bit mask of H_ACK3 field. + USB_HCINT3_H_ACK3_Msk = 0x20 + // Bit H_ACK3. + USB_HCINT3_H_ACK3 = 0x20 + // Position of H_NYET3 field. + USB_HCINT3_H_NYET3_Pos = 0x6 + // Bit mask of H_NYET3 field. + USB_HCINT3_H_NYET3_Msk = 0x40 + // Bit H_NYET3. + USB_HCINT3_H_NYET3 = 0x40 + // Position of H_XACTERR3 field. + USB_HCINT3_H_XACTERR3_Pos = 0x7 + // Bit mask of H_XACTERR3 field. + USB_HCINT3_H_XACTERR3_Msk = 0x80 + // Bit H_XACTERR3. + USB_HCINT3_H_XACTERR3 = 0x80 + // Position of H_BBLERR3 field. + USB_HCINT3_H_BBLERR3_Pos = 0x8 + // Bit mask of H_BBLERR3 field. + USB_HCINT3_H_BBLERR3_Msk = 0x100 + // Bit H_BBLERR3. + USB_HCINT3_H_BBLERR3 = 0x100 + // Position of H_FRMOVRUN3 field. + USB_HCINT3_H_FRMOVRUN3_Pos = 0x9 + // Bit mask of H_FRMOVRUN3 field. + USB_HCINT3_H_FRMOVRUN3_Msk = 0x200 + // Bit H_FRMOVRUN3. + USB_HCINT3_H_FRMOVRUN3 = 0x200 + // Position of H_DATATGLERR3 field. + USB_HCINT3_H_DATATGLERR3_Pos = 0xa + // Bit mask of H_DATATGLERR3 field. + USB_HCINT3_H_DATATGLERR3_Msk = 0x400 + // Bit H_DATATGLERR3. + USB_HCINT3_H_DATATGLERR3 = 0x400 + // Position of H_BNAINTR3 field. + USB_HCINT3_H_BNAINTR3_Pos = 0xb + // Bit mask of H_BNAINTR3 field. + USB_HCINT3_H_BNAINTR3_Msk = 0x800 + // Bit H_BNAINTR3. + USB_HCINT3_H_BNAINTR3 = 0x800 + // Position of H_XCS_XACT_ERR3 field. + USB_HCINT3_H_XCS_XACT_ERR3_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR3 field. + USB_HCINT3_H_XCS_XACT_ERR3_Msk = 0x1000 + // Bit H_XCS_XACT_ERR3. + USB_HCINT3_H_XCS_XACT_ERR3 = 0x1000 + // Position of H_DESC_LST_ROLLINTR3 field. + USB_HCINT3_H_DESC_LST_ROLLINTR3_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR3 field. + USB_HCINT3_H_DESC_LST_ROLLINTR3_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR3. + USB_HCINT3_H_DESC_LST_ROLLINTR3 = 0x2000 + + // HCINTMSK3 + // Position of H_XFERCOMPLMSK3 field. + USB_HCINTMSK3_H_XFERCOMPLMSK3_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK3 field. + USB_HCINTMSK3_H_XFERCOMPLMSK3_Msk = 0x1 + // Bit H_XFERCOMPLMSK3. + USB_HCINTMSK3_H_XFERCOMPLMSK3 = 0x1 + // Position of H_CHHLTDMSK3 field. + USB_HCINTMSK3_H_CHHLTDMSK3_Pos = 0x1 + // Bit mask of H_CHHLTDMSK3 field. + USB_HCINTMSK3_H_CHHLTDMSK3_Msk = 0x2 + // Bit H_CHHLTDMSK3. + USB_HCINTMSK3_H_CHHLTDMSK3 = 0x2 + // Position of H_AHBERRMSK3 field. + USB_HCINTMSK3_H_AHBERRMSK3_Pos = 0x2 + // Bit mask of H_AHBERRMSK3 field. + USB_HCINTMSK3_H_AHBERRMSK3_Msk = 0x4 + // Bit H_AHBERRMSK3. + USB_HCINTMSK3_H_AHBERRMSK3 = 0x4 + // Position of H_STALLMSK3 field. + USB_HCINTMSK3_H_STALLMSK3_Pos = 0x3 + // Bit mask of H_STALLMSK3 field. + USB_HCINTMSK3_H_STALLMSK3_Msk = 0x8 + // Bit H_STALLMSK3. + USB_HCINTMSK3_H_STALLMSK3 = 0x8 + // Position of H_NAKMSK3 field. + USB_HCINTMSK3_H_NAKMSK3_Pos = 0x4 + // Bit mask of H_NAKMSK3 field. + USB_HCINTMSK3_H_NAKMSK3_Msk = 0x10 + // Bit H_NAKMSK3. + USB_HCINTMSK3_H_NAKMSK3 = 0x10 + // Position of H_ACKMSK3 field. + USB_HCINTMSK3_H_ACKMSK3_Pos = 0x5 + // Bit mask of H_ACKMSK3 field. + USB_HCINTMSK3_H_ACKMSK3_Msk = 0x20 + // Bit H_ACKMSK3. + USB_HCINTMSK3_H_ACKMSK3 = 0x20 + // Position of H_NYETMSK3 field. + USB_HCINTMSK3_H_NYETMSK3_Pos = 0x6 + // Bit mask of H_NYETMSK3 field. + USB_HCINTMSK3_H_NYETMSK3_Msk = 0x40 + // Bit H_NYETMSK3. + USB_HCINTMSK3_H_NYETMSK3 = 0x40 + // Position of H_XACTERRMSK3 field. + USB_HCINTMSK3_H_XACTERRMSK3_Pos = 0x7 + // Bit mask of H_XACTERRMSK3 field. + USB_HCINTMSK3_H_XACTERRMSK3_Msk = 0x80 + // Bit H_XACTERRMSK3. + USB_HCINTMSK3_H_XACTERRMSK3 = 0x80 + // Position of H_BBLERRMSK3 field. + USB_HCINTMSK3_H_BBLERRMSK3_Pos = 0x8 + // Bit mask of H_BBLERRMSK3 field. + USB_HCINTMSK3_H_BBLERRMSK3_Msk = 0x100 + // Bit H_BBLERRMSK3. + USB_HCINTMSK3_H_BBLERRMSK3 = 0x100 + // Position of H_FRMOVRUNMSK3 field. + USB_HCINTMSK3_H_FRMOVRUNMSK3_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK3 field. + USB_HCINTMSK3_H_FRMOVRUNMSK3_Msk = 0x200 + // Bit H_FRMOVRUNMSK3. + USB_HCINTMSK3_H_FRMOVRUNMSK3 = 0x200 + // Position of H_DATATGLERRMSK3 field. + USB_HCINTMSK3_H_DATATGLERRMSK3_Pos = 0xa + // Bit mask of H_DATATGLERRMSK3 field. + USB_HCINTMSK3_H_DATATGLERRMSK3_Msk = 0x400 + // Bit H_DATATGLERRMSK3. + USB_HCINTMSK3_H_DATATGLERRMSK3 = 0x400 + // Position of H_BNAINTRMSK3 field. + USB_HCINTMSK3_H_BNAINTRMSK3_Pos = 0xb + // Bit mask of H_BNAINTRMSK3 field. + USB_HCINTMSK3_H_BNAINTRMSK3_Msk = 0x800 + // Bit H_BNAINTRMSK3. + USB_HCINTMSK3_H_BNAINTRMSK3 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK3 field. + USB_HCINTMSK3_H_DESC_LST_ROLLINTRMSK3_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK3 field. + USB_HCINTMSK3_H_DESC_LST_ROLLINTRMSK3_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK3. + USB_HCINTMSK3_H_DESC_LST_ROLLINTRMSK3 = 0x2000 + + // HCTSIZ3 + // Position of H_XFERSIZE3 field. + USB_HCTSIZ3_H_XFERSIZE3_Pos = 0x0 + // Bit mask of H_XFERSIZE3 field. + USB_HCTSIZ3_H_XFERSIZE3_Msk = 0x7ffff + // Position of H_PKTCNT3 field. + USB_HCTSIZ3_H_PKTCNT3_Pos = 0x13 + // Bit mask of H_PKTCNT3 field. + USB_HCTSIZ3_H_PKTCNT3_Msk = 0x1ff80000 + // Position of H_PID3 field. + USB_HCTSIZ3_H_PID3_Pos = 0x1d + // Bit mask of H_PID3 field. + USB_HCTSIZ3_H_PID3_Msk = 0x60000000 + // Position of H_DOPNG3 field. + USB_HCTSIZ3_H_DOPNG3_Pos = 0x1f + // Bit mask of H_DOPNG3 field. + USB_HCTSIZ3_H_DOPNG3_Msk = 0x80000000 + // Bit H_DOPNG3. + USB_HCTSIZ3_H_DOPNG3 = 0x80000000 + + // HCDMA3 + // Position of H_DMAADDR3 field. + USB_HCDMA3_H_DMAADDR3_Pos = 0x0 + // Bit mask of H_DMAADDR3 field. + USB_HCDMA3_H_DMAADDR3_Msk = 0xffffffff + + // HCDMAB3 + // Position of H_HCDMAB3 field. + USB_HCDMAB3_H_HCDMAB3_Pos = 0x0 + // Bit mask of H_HCDMAB3 field. + USB_HCDMAB3_H_HCDMAB3_Msk = 0xffffffff + + // HCCHAR4 + // Position of H_MPS4 field. + USB_HCCHAR4_H_MPS4_Pos = 0x0 + // Bit mask of H_MPS4 field. + USB_HCCHAR4_H_MPS4_Msk = 0x7ff + // Position of H_EPNUM4 field. + USB_HCCHAR4_H_EPNUM4_Pos = 0xb + // Bit mask of H_EPNUM4 field. + USB_HCCHAR4_H_EPNUM4_Msk = 0x7800 + // Position of H_EPDIR4 field. + USB_HCCHAR4_H_EPDIR4_Pos = 0xf + // Bit mask of H_EPDIR4 field. + USB_HCCHAR4_H_EPDIR4_Msk = 0x8000 + // Bit H_EPDIR4. + USB_HCCHAR4_H_EPDIR4 = 0x8000 + // Position of H_LSPDDEV4 field. + USB_HCCHAR4_H_LSPDDEV4_Pos = 0x11 + // Bit mask of H_LSPDDEV4 field. + USB_HCCHAR4_H_LSPDDEV4_Msk = 0x20000 + // Bit H_LSPDDEV4. + USB_HCCHAR4_H_LSPDDEV4 = 0x20000 + // Position of H_EPTYPE4 field. + USB_HCCHAR4_H_EPTYPE4_Pos = 0x12 + // Bit mask of H_EPTYPE4 field. + USB_HCCHAR4_H_EPTYPE4_Msk = 0xc0000 + // Position of H_EC4 field. + USB_HCCHAR4_H_EC4_Pos = 0x15 + // Bit mask of H_EC4 field. + USB_HCCHAR4_H_EC4_Msk = 0x200000 + // Bit H_EC4. + USB_HCCHAR4_H_EC4 = 0x200000 + // Position of H_DEVADDR4 field. + USB_HCCHAR4_H_DEVADDR4_Pos = 0x16 + // Bit mask of H_DEVADDR4 field. + USB_HCCHAR4_H_DEVADDR4_Msk = 0x1fc00000 + // Position of H_ODDFRM4 field. + USB_HCCHAR4_H_ODDFRM4_Pos = 0x1d + // Bit mask of H_ODDFRM4 field. + USB_HCCHAR4_H_ODDFRM4_Msk = 0x20000000 + // Bit H_ODDFRM4. + USB_HCCHAR4_H_ODDFRM4 = 0x20000000 + // Position of H_CHDIS4 field. + USB_HCCHAR4_H_CHDIS4_Pos = 0x1e + // Bit mask of H_CHDIS4 field. + USB_HCCHAR4_H_CHDIS4_Msk = 0x40000000 + // Bit H_CHDIS4. + USB_HCCHAR4_H_CHDIS4 = 0x40000000 + // Position of H_CHENA4 field. + USB_HCCHAR4_H_CHENA4_Pos = 0x1f + // Bit mask of H_CHENA4 field. + USB_HCCHAR4_H_CHENA4_Msk = 0x80000000 + // Bit H_CHENA4. + USB_HCCHAR4_H_CHENA4 = 0x80000000 + + // HCINT4 + // Position of H_XFERCOMPL4 field. + USB_HCINT4_H_XFERCOMPL4_Pos = 0x0 + // Bit mask of H_XFERCOMPL4 field. + USB_HCINT4_H_XFERCOMPL4_Msk = 0x1 + // Bit H_XFERCOMPL4. + USB_HCINT4_H_XFERCOMPL4 = 0x1 + // Position of H_CHHLTD4 field. + USB_HCINT4_H_CHHLTD4_Pos = 0x1 + // Bit mask of H_CHHLTD4 field. + USB_HCINT4_H_CHHLTD4_Msk = 0x2 + // Bit H_CHHLTD4. + USB_HCINT4_H_CHHLTD4 = 0x2 + // Position of H_AHBERR4 field. + USB_HCINT4_H_AHBERR4_Pos = 0x2 + // Bit mask of H_AHBERR4 field. + USB_HCINT4_H_AHBERR4_Msk = 0x4 + // Bit H_AHBERR4. + USB_HCINT4_H_AHBERR4 = 0x4 + // Position of H_STALL4 field. + USB_HCINT4_H_STALL4_Pos = 0x3 + // Bit mask of H_STALL4 field. + USB_HCINT4_H_STALL4_Msk = 0x8 + // Bit H_STALL4. + USB_HCINT4_H_STALL4 = 0x8 + // Position of H_NACK4 field. + USB_HCINT4_H_NACK4_Pos = 0x4 + // Bit mask of H_NACK4 field. + USB_HCINT4_H_NACK4_Msk = 0x10 + // Bit H_NACK4. + USB_HCINT4_H_NACK4 = 0x10 + // Position of H_ACK4 field. + USB_HCINT4_H_ACK4_Pos = 0x5 + // Bit mask of H_ACK4 field. + USB_HCINT4_H_ACK4_Msk = 0x20 + // Bit H_ACK4. + USB_HCINT4_H_ACK4 = 0x20 + // Position of H_NYET4 field. + USB_HCINT4_H_NYET4_Pos = 0x6 + // Bit mask of H_NYET4 field. + USB_HCINT4_H_NYET4_Msk = 0x40 + // Bit H_NYET4. + USB_HCINT4_H_NYET4 = 0x40 + // Position of H_XACTERR4 field. + USB_HCINT4_H_XACTERR4_Pos = 0x7 + // Bit mask of H_XACTERR4 field. + USB_HCINT4_H_XACTERR4_Msk = 0x80 + // Bit H_XACTERR4. + USB_HCINT4_H_XACTERR4 = 0x80 + // Position of H_BBLERR4 field. + USB_HCINT4_H_BBLERR4_Pos = 0x8 + // Bit mask of H_BBLERR4 field. + USB_HCINT4_H_BBLERR4_Msk = 0x100 + // Bit H_BBLERR4. + USB_HCINT4_H_BBLERR4 = 0x100 + // Position of H_FRMOVRUN4 field. + USB_HCINT4_H_FRMOVRUN4_Pos = 0x9 + // Bit mask of H_FRMOVRUN4 field. + USB_HCINT4_H_FRMOVRUN4_Msk = 0x200 + // Bit H_FRMOVRUN4. + USB_HCINT4_H_FRMOVRUN4 = 0x200 + // Position of H_DATATGLERR4 field. + USB_HCINT4_H_DATATGLERR4_Pos = 0xa + // Bit mask of H_DATATGLERR4 field. + USB_HCINT4_H_DATATGLERR4_Msk = 0x400 + // Bit H_DATATGLERR4. + USB_HCINT4_H_DATATGLERR4 = 0x400 + // Position of H_BNAINTR4 field. + USB_HCINT4_H_BNAINTR4_Pos = 0xb + // Bit mask of H_BNAINTR4 field. + USB_HCINT4_H_BNAINTR4_Msk = 0x800 + // Bit H_BNAINTR4. + USB_HCINT4_H_BNAINTR4 = 0x800 + // Position of H_XCS_XACT_ERR4 field. + USB_HCINT4_H_XCS_XACT_ERR4_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR4 field. + USB_HCINT4_H_XCS_XACT_ERR4_Msk = 0x1000 + // Bit H_XCS_XACT_ERR4. + USB_HCINT4_H_XCS_XACT_ERR4 = 0x1000 + // Position of H_DESC_LST_ROLLINTR4 field. + USB_HCINT4_H_DESC_LST_ROLLINTR4_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR4 field. + USB_HCINT4_H_DESC_LST_ROLLINTR4_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR4. + USB_HCINT4_H_DESC_LST_ROLLINTR4 = 0x2000 + + // HCINTMSK4 + // Position of H_XFERCOMPLMSK4 field. + USB_HCINTMSK4_H_XFERCOMPLMSK4_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK4 field. + USB_HCINTMSK4_H_XFERCOMPLMSK4_Msk = 0x1 + // Bit H_XFERCOMPLMSK4. + USB_HCINTMSK4_H_XFERCOMPLMSK4 = 0x1 + // Position of H_CHHLTDMSK4 field. + USB_HCINTMSK4_H_CHHLTDMSK4_Pos = 0x1 + // Bit mask of H_CHHLTDMSK4 field. + USB_HCINTMSK4_H_CHHLTDMSK4_Msk = 0x2 + // Bit H_CHHLTDMSK4. + USB_HCINTMSK4_H_CHHLTDMSK4 = 0x2 + // Position of H_AHBERRMSK4 field. + USB_HCINTMSK4_H_AHBERRMSK4_Pos = 0x2 + // Bit mask of H_AHBERRMSK4 field. + USB_HCINTMSK4_H_AHBERRMSK4_Msk = 0x4 + // Bit H_AHBERRMSK4. + USB_HCINTMSK4_H_AHBERRMSK4 = 0x4 + // Position of H_STALLMSK4 field. + USB_HCINTMSK4_H_STALLMSK4_Pos = 0x3 + // Bit mask of H_STALLMSK4 field. + USB_HCINTMSK4_H_STALLMSK4_Msk = 0x8 + // Bit H_STALLMSK4. + USB_HCINTMSK4_H_STALLMSK4 = 0x8 + // Position of H_NAKMSK4 field. + USB_HCINTMSK4_H_NAKMSK4_Pos = 0x4 + // Bit mask of H_NAKMSK4 field. + USB_HCINTMSK4_H_NAKMSK4_Msk = 0x10 + // Bit H_NAKMSK4. + USB_HCINTMSK4_H_NAKMSK4 = 0x10 + // Position of H_ACKMSK4 field. + USB_HCINTMSK4_H_ACKMSK4_Pos = 0x5 + // Bit mask of H_ACKMSK4 field. + USB_HCINTMSK4_H_ACKMSK4_Msk = 0x20 + // Bit H_ACKMSK4. + USB_HCINTMSK4_H_ACKMSK4 = 0x20 + // Position of H_NYETMSK4 field. + USB_HCINTMSK4_H_NYETMSK4_Pos = 0x6 + // Bit mask of H_NYETMSK4 field. + USB_HCINTMSK4_H_NYETMSK4_Msk = 0x40 + // Bit H_NYETMSK4. + USB_HCINTMSK4_H_NYETMSK4 = 0x40 + // Position of H_XACTERRMSK4 field. + USB_HCINTMSK4_H_XACTERRMSK4_Pos = 0x7 + // Bit mask of H_XACTERRMSK4 field. + USB_HCINTMSK4_H_XACTERRMSK4_Msk = 0x80 + // Bit H_XACTERRMSK4. + USB_HCINTMSK4_H_XACTERRMSK4 = 0x80 + // Position of H_BBLERRMSK4 field. + USB_HCINTMSK4_H_BBLERRMSK4_Pos = 0x8 + // Bit mask of H_BBLERRMSK4 field. + USB_HCINTMSK4_H_BBLERRMSK4_Msk = 0x100 + // Bit H_BBLERRMSK4. + USB_HCINTMSK4_H_BBLERRMSK4 = 0x100 + // Position of H_FRMOVRUNMSK4 field. + USB_HCINTMSK4_H_FRMOVRUNMSK4_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK4 field. + USB_HCINTMSK4_H_FRMOVRUNMSK4_Msk = 0x200 + // Bit H_FRMOVRUNMSK4. + USB_HCINTMSK4_H_FRMOVRUNMSK4 = 0x200 + // Position of H_DATATGLERRMSK4 field. + USB_HCINTMSK4_H_DATATGLERRMSK4_Pos = 0xa + // Bit mask of H_DATATGLERRMSK4 field. + USB_HCINTMSK4_H_DATATGLERRMSK4_Msk = 0x400 + // Bit H_DATATGLERRMSK4. + USB_HCINTMSK4_H_DATATGLERRMSK4 = 0x400 + // Position of H_BNAINTRMSK4 field. + USB_HCINTMSK4_H_BNAINTRMSK4_Pos = 0xb + // Bit mask of H_BNAINTRMSK4 field. + USB_HCINTMSK4_H_BNAINTRMSK4_Msk = 0x800 + // Bit H_BNAINTRMSK4. + USB_HCINTMSK4_H_BNAINTRMSK4 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK4 field. + USB_HCINTMSK4_H_DESC_LST_ROLLINTRMSK4_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK4 field. + USB_HCINTMSK4_H_DESC_LST_ROLLINTRMSK4_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK4. + USB_HCINTMSK4_H_DESC_LST_ROLLINTRMSK4 = 0x2000 + + // HCTSIZ4 + // Position of H_XFERSIZE4 field. + USB_HCTSIZ4_H_XFERSIZE4_Pos = 0x0 + // Bit mask of H_XFERSIZE4 field. + USB_HCTSIZ4_H_XFERSIZE4_Msk = 0x7ffff + // Position of H_PKTCNT4 field. + USB_HCTSIZ4_H_PKTCNT4_Pos = 0x13 + // Bit mask of H_PKTCNT4 field. + USB_HCTSIZ4_H_PKTCNT4_Msk = 0x1ff80000 + // Position of H_PID4 field. + USB_HCTSIZ4_H_PID4_Pos = 0x1d + // Bit mask of H_PID4 field. + USB_HCTSIZ4_H_PID4_Msk = 0x60000000 + // Position of H_DOPNG4 field. + USB_HCTSIZ4_H_DOPNG4_Pos = 0x1f + // Bit mask of H_DOPNG4 field. + USB_HCTSIZ4_H_DOPNG4_Msk = 0x80000000 + // Bit H_DOPNG4. + USB_HCTSIZ4_H_DOPNG4 = 0x80000000 + + // HCDMA4 + // Position of H_DMAADDR4 field. + USB_HCDMA4_H_DMAADDR4_Pos = 0x0 + // Bit mask of H_DMAADDR4 field. + USB_HCDMA4_H_DMAADDR4_Msk = 0xffffffff + + // HCDMAB4 + // Position of H_HCDMAB4 field. + USB_HCDMAB4_H_HCDMAB4_Pos = 0x0 + // Bit mask of H_HCDMAB4 field. + USB_HCDMAB4_H_HCDMAB4_Msk = 0xffffffff + + // HCCHAR5 + // Position of H_MPS5 field. + USB_HCCHAR5_H_MPS5_Pos = 0x0 + // Bit mask of H_MPS5 field. + USB_HCCHAR5_H_MPS5_Msk = 0x7ff + // Position of H_EPNUM5 field. + USB_HCCHAR5_H_EPNUM5_Pos = 0xb + // Bit mask of H_EPNUM5 field. + USB_HCCHAR5_H_EPNUM5_Msk = 0x7800 + // Position of H_EPDIR5 field. + USB_HCCHAR5_H_EPDIR5_Pos = 0xf + // Bit mask of H_EPDIR5 field. + USB_HCCHAR5_H_EPDIR5_Msk = 0x8000 + // Bit H_EPDIR5. + USB_HCCHAR5_H_EPDIR5 = 0x8000 + // Position of H_LSPDDEV5 field. + USB_HCCHAR5_H_LSPDDEV5_Pos = 0x11 + // Bit mask of H_LSPDDEV5 field. + USB_HCCHAR5_H_LSPDDEV5_Msk = 0x20000 + // Bit H_LSPDDEV5. + USB_HCCHAR5_H_LSPDDEV5 = 0x20000 + // Position of H_EPTYPE5 field. + USB_HCCHAR5_H_EPTYPE5_Pos = 0x12 + // Bit mask of H_EPTYPE5 field. + USB_HCCHAR5_H_EPTYPE5_Msk = 0xc0000 + // Position of H_EC5 field. + USB_HCCHAR5_H_EC5_Pos = 0x15 + // Bit mask of H_EC5 field. + USB_HCCHAR5_H_EC5_Msk = 0x200000 + // Bit H_EC5. + USB_HCCHAR5_H_EC5 = 0x200000 + // Position of H_DEVADDR5 field. + USB_HCCHAR5_H_DEVADDR5_Pos = 0x16 + // Bit mask of H_DEVADDR5 field. + USB_HCCHAR5_H_DEVADDR5_Msk = 0x1fc00000 + // Position of H_ODDFRM5 field. + USB_HCCHAR5_H_ODDFRM5_Pos = 0x1d + // Bit mask of H_ODDFRM5 field. + USB_HCCHAR5_H_ODDFRM5_Msk = 0x20000000 + // Bit H_ODDFRM5. + USB_HCCHAR5_H_ODDFRM5 = 0x20000000 + // Position of H_CHDIS5 field. + USB_HCCHAR5_H_CHDIS5_Pos = 0x1e + // Bit mask of H_CHDIS5 field. + USB_HCCHAR5_H_CHDIS5_Msk = 0x40000000 + // Bit H_CHDIS5. + USB_HCCHAR5_H_CHDIS5 = 0x40000000 + // Position of H_CHENA5 field. + USB_HCCHAR5_H_CHENA5_Pos = 0x1f + // Bit mask of H_CHENA5 field. + USB_HCCHAR5_H_CHENA5_Msk = 0x80000000 + // Bit H_CHENA5. + USB_HCCHAR5_H_CHENA5 = 0x80000000 + + // HCINT5 + // Position of H_XFERCOMPL5 field. + USB_HCINT5_H_XFERCOMPL5_Pos = 0x0 + // Bit mask of H_XFERCOMPL5 field. + USB_HCINT5_H_XFERCOMPL5_Msk = 0x1 + // Bit H_XFERCOMPL5. + USB_HCINT5_H_XFERCOMPL5 = 0x1 + // Position of H_CHHLTD5 field. + USB_HCINT5_H_CHHLTD5_Pos = 0x1 + // Bit mask of H_CHHLTD5 field. + USB_HCINT5_H_CHHLTD5_Msk = 0x2 + // Bit H_CHHLTD5. + USB_HCINT5_H_CHHLTD5 = 0x2 + // Position of H_AHBERR5 field. + USB_HCINT5_H_AHBERR5_Pos = 0x2 + // Bit mask of H_AHBERR5 field. + USB_HCINT5_H_AHBERR5_Msk = 0x4 + // Bit H_AHBERR5. + USB_HCINT5_H_AHBERR5 = 0x4 + // Position of H_STALL5 field. + USB_HCINT5_H_STALL5_Pos = 0x3 + // Bit mask of H_STALL5 field. + USB_HCINT5_H_STALL5_Msk = 0x8 + // Bit H_STALL5. + USB_HCINT5_H_STALL5 = 0x8 + // Position of H_NACK5 field. + USB_HCINT5_H_NACK5_Pos = 0x4 + // Bit mask of H_NACK5 field. + USB_HCINT5_H_NACK5_Msk = 0x10 + // Bit H_NACK5. + USB_HCINT5_H_NACK5 = 0x10 + // Position of H_ACK5 field. + USB_HCINT5_H_ACK5_Pos = 0x5 + // Bit mask of H_ACK5 field. + USB_HCINT5_H_ACK5_Msk = 0x20 + // Bit H_ACK5. + USB_HCINT5_H_ACK5 = 0x20 + // Position of H_NYET5 field. + USB_HCINT5_H_NYET5_Pos = 0x6 + // Bit mask of H_NYET5 field. + USB_HCINT5_H_NYET5_Msk = 0x40 + // Bit H_NYET5. + USB_HCINT5_H_NYET5 = 0x40 + // Position of H_XACTERR5 field. + USB_HCINT5_H_XACTERR5_Pos = 0x7 + // Bit mask of H_XACTERR5 field. + USB_HCINT5_H_XACTERR5_Msk = 0x80 + // Bit H_XACTERR5. + USB_HCINT5_H_XACTERR5 = 0x80 + // Position of H_BBLERR5 field. + USB_HCINT5_H_BBLERR5_Pos = 0x8 + // Bit mask of H_BBLERR5 field. + USB_HCINT5_H_BBLERR5_Msk = 0x100 + // Bit H_BBLERR5. + USB_HCINT5_H_BBLERR5 = 0x100 + // Position of H_FRMOVRUN5 field. + USB_HCINT5_H_FRMOVRUN5_Pos = 0x9 + // Bit mask of H_FRMOVRUN5 field. + USB_HCINT5_H_FRMOVRUN5_Msk = 0x200 + // Bit H_FRMOVRUN5. + USB_HCINT5_H_FRMOVRUN5 = 0x200 + // Position of H_DATATGLERR5 field. + USB_HCINT5_H_DATATGLERR5_Pos = 0xa + // Bit mask of H_DATATGLERR5 field. + USB_HCINT5_H_DATATGLERR5_Msk = 0x400 + // Bit H_DATATGLERR5. + USB_HCINT5_H_DATATGLERR5 = 0x400 + // Position of H_BNAINTR5 field. + USB_HCINT5_H_BNAINTR5_Pos = 0xb + // Bit mask of H_BNAINTR5 field. + USB_HCINT5_H_BNAINTR5_Msk = 0x800 + // Bit H_BNAINTR5. + USB_HCINT5_H_BNAINTR5 = 0x800 + // Position of H_XCS_XACT_ERR5 field. + USB_HCINT5_H_XCS_XACT_ERR5_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR5 field. + USB_HCINT5_H_XCS_XACT_ERR5_Msk = 0x1000 + // Bit H_XCS_XACT_ERR5. + USB_HCINT5_H_XCS_XACT_ERR5 = 0x1000 + // Position of H_DESC_LST_ROLLINTR5 field. + USB_HCINT5_H_DESC_LST_ROLLINTR5_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR5 field. + USB_HCINT5_H_DESC_LST_ROLLINTR5_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR5. + USB_HCINT5_H_DESC_LST_ROLLINTR5 = 0x2000 + + // HCINTMSK5 + // Position of H_XFERCOMPLMSK5 field. + USB_HCINTMSK5_H_XFERCOMPLMSK5_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK5 field. + USB_HCINTMSK5_H_XFERCOMPLMSK5_Msk = 0x1 + // Bit H_XFERCOMPLMSK5. + USB_HCINTMSK5_H_XFERCOMPLMSK5 = 0x1 + // Position of H_CHHLTDMSK5 field. + USB_HCINTMSK5_H_CHHLTDMSK5_Pos = 0x1 + // Bit mask of H_CHHLTDMSK5 field. + USB_HCINTMSK5_H_CHHLTDMSK5_Msk = 0x2 + // Bit H_CHHLTDMSK5. + USB_HCINTMSK5_H_CHHLTDMSK5 = 0x2 + // Position of H_AHBERRMSK5 field. + USB_HCINTMSK5_H_AHBERRMSK5_Pos = 0x2 + // Bit mask of H_AHBERRMSK5 field. + USB_HCINTMSK5_H_AHBERRMSK5_Msk = 0x4 + // Bit H_AHBERRMSK5. + USB_HCINTMSK5_H_AHBERRMSK5 = 0x4 + // Position of H_STALLMSK5 field. + USB_HCINTMSK5_H_STALLMSK5_Pos = 0x3 + // Bit mask of H_STALLMSK5 field. + USB_HCINTMSK5_H_STALLMSK5_Msk = 0x8 + // Bit H_STALLMSK5. + USB_HCINTMSK5_H_STALLMSK5 = 0x8 + // Position of H_NAKMSK5 field. + USB_HCINTMSK5_H_NAKMSK5_Pos = 0x4 + // Bit mask of H_NAKMSK5 field. + USB_HCINTMSK5_H_NAKMSK5_Msk = 0x10 + // Bit H_NAKMSK5. + USB_HCINTMSK5_H_NAKMSK5 = 0x10 + // Position of H_ACKMSK5 field. + USB_HCINTMSK5_H_ACKMSK5_Pos = 0x5 + // Bit mask of H_ACKMSK5 field. + USB_HCINTMSK5_H_ACKMSK5_Msk = 0x20 + // Bit H_ACKMSK5. + USB_HCINTMSK5_H_ACKMSK5 = 0x20 + // Position of H_NYETMSK5 field. + USB_HCINTMSK5_H_NYETMSK5_Pos = 0x6 + // Bit mask of H_NYETMSK5 field. + USB_HCINTMSK5_H_NYETMSK5_Msk = 0x40 + // Bit H_NYETMSK5. + USB_HCINTMSK5_H_NYETMSK5 = 0x40 + // Position of H_XACTERRMSK5 field. + USB_HCINTMSK5_H_XACTERRMSK5_Pos = 0x7 + // Bit mask of H_XACTERRMSK5 field. + USB_HCINTMSK5_H_XACTERRMSK5_Msk = 0x80 + // Bit H_XACTERRMSK5. + USB_HCINTMSK5_H_XACTERRMSK5 = 0x80 + // Position of H_BBLERRMSK5 field. + USB_HCINTMSK5_H_BBLERRMSK5_Pos = 0x8 + // Bit mask of H_BBLERRMSK5 field. + USB_HCINTMSK5_H_BBLERRMSK5_Msk = 0x100 + // Bit H_BBLERRMSK5. + USB_HCINTMSK5_H_BBLERRMSK5 = 0x100 + // Position of H_FRMOVRUNMSK5 field. + USB_HCINTMSK5_H_FRMOVRUNMSK5_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK5 field. + USB_HCINTMSK5_H_FRMOVRUNMSK5_Msk = 0x200 + // Bit H_FRMOVRUNMSK5. + USB_HCINTMSK5_H_FRMOVRUNMSK5 = 0x200 + // Position of H_DATATGLERRMSK5 field. + USB_HCINTMSK5_H_DATATGLERRMSK5_Pos = 0xa + // Bit mask of H_DATATGLERRMSK5 field. + USB_HCINTMSK5_H_DATATGLERRMSK5_Msk = 0x400 + // Bit H_DATATGLERRMSK5. + USB_HCINTMSK5_H_DATATGLERRMSK5 = 0x400 + // Position of H_BNAINTRMSK5 field. + USB_HCINTMSK5_H_BNAINTRMSK5_Pos = 0xb + // Bit mask of H_BNAINTRMSK5 field. + USB_HCINTMSK5_H_BNAINTRMSK5_Msk = 0x800 + // Bit H_BNAINTRMSK5. + USB_HCINTMSK5_H_BNAINTRMSK5 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK5 field. + USB_HCINTMSK5_H_DESC_LST_ROLLINTRMSK5_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK5 field. + USB_HCINTMSK5_H_DESC_LST_ROLLINTRMSK5_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK5. + USB_HCINTMSK5_H_DESC_LST_ROLLINTRMSK5 = 0x2000 + + // HCTSIZ5 + // Position of H_XFERSIZE5 field. + USB_HCTSIZ5_H_XFERSIZE5_Pos = 0x0 + // Bit mask of H_XFERSIZE5 field. + USB_HCTSIZ5_H_XFERSIZE5_Msk = 0x7ffff + // Position of H_PKTCNT5 field. + USB_HCTSIZ5_H_PKTCNT5_Pos = 0x13 + // Bit mask of H_PKTCNT5 field. + USB_HCTSIZ5_H_PKTCNT5_Msk = 0x1ff80000 + // Position of H_PID5 field. + USB_HCTSIZ5_H_PID5_Pos = 0x1d + // Bit mask of H_PID5 field. + USB_HCTSIZ5_H_PID5_Msk = 0x60000000 + // Position of H_DOPNG5 field. + USB_HCTSIZ5_H_DOPNG5_Pos = 0x1f + // Bit mask of H_DOPNG5 field. + USB_HCTSIZ5_H_DOPNG5_Msk = 0x80000000 + // Bit H_DOPNG5. + USB_HCTSIZ5_H_DOPNG5 = 0x80000000 + + // HCDMA5 + // Position of H_DMAADDR5 field. + USB_HCDMA5_H_DMAADDR5_Pos = 0x0 + // Bit mask of H_DMAADDR5 field. + USB_HCDMA5_H_DMAADDR5_Msk = 0xffffffff + + // HCDMAB5 + // Position of H_HCDMAB5 field. + USB_HCDMAB5_H_HCDMAB5_Pos = 0x0 + // Bit mask of H_HCDMAB5 field. + USB_HCDMAB5_H_HCDMAB5_Msk = 0xffffffff + + // HCCHAR6 + // Position of H_MPS6 field. + USB_HCCHAR6_H_MPS6_Pos = 0x0 + // Bit mask of H_MPS6 field. + USB_HCCHAR6_H_MPS6_Msk = 0x7ff + // Position of H_EPNUM6 field. + USB_HCCHAR6_H_EPNUM6_Pos = 0xb + // Bit mask of H_EPNUM6 field. + USB_HCCHAR6_H_EPNUM6_Msk = 0x7800 + // Position of H_EPDIR6 field. + USB_HCCHAR6_H_EPDIR6_Pos = 0xf + // Bit mask of H_EPDIR6 field. + USB_HCCHAR6_H_EPDIR6_Msk = 0x8000 + // Bit H_EPDIR6. + USB_HCCHAR6_H_EPDIR6 = 0x8000 + // Position of H_LSPDDEV6 field. + USB_HCCHAR6_H_LSPDDEV6_Pos = 0x11 + // Bit mask of H_LSPDDEV6 field. + USB_HCCHAR6_H_LSPDDEV6_Msk = 0x20000 + // Bit H_LSPDDEV6. + USB_HCCHAR6_H_LSPDDEV6 = 0x20000 + // Position of H_EPTYPE6 field. + USB_HCCHAR6_H_EPTYPE6_Pos = 0x12 + // Bit mask of H_EPTYPE6 field. + USB_HCCHAR6_H_EPTYPE6_Msk = 0xc0000 + // Position of H_EC6 field. + USB_HCCHAR6_H_EC6_Pos = 0x15 + // Bit mask of H_EC6 field. + USB_HCCHAR6_H_EC6_Msk = 0x200000 + // Bit H_EC6. + USB_HCCHAR6_H_EC6 = 0x200000 + // Position of H_DEVADDR6 field. + USB_HCCHAR6_H_DEVADDR6_Pos = 0x16 + // Bit mask of H_DEVADDR6 field. + USB_HCCHAR6_H_DEVADDR6_Msk = 0x1fc00000 + // Position of H_ODDFRM6 field. + USB_HCCHAR6_H_ODDFRM6_Pos = 0x1d + // Bit mask of H_ODDFRM6 field. + USB_HCCHAR6_H_ODDFRM6_Msk = 0x20000000 + // Bit H_ODDFRM6. + USB_HCCHAR6_H_ODDFRM6 = 0x20000000 + // Position of H_CHDIS6 field. + USB_HCCHAR6_H_CHDIS6_Pos = 0x1e + // Bit mask of H_CHDIS6 field. + USB_HCCHAR6_H_CHDIS6_Msk = 0x40000000 + // Bit H_CHDIS6. + USB_HCCHAR6_H_CHDIS6 = 0x40000000 + // Position of H_CHENA6 field. + USB_HCCHAR6_H_CHENA6_Pos = 0x1f + // Bit mask of H_CHENA6 field. + USB_HCCHAR6_H_CHENA6_Msk = 0x80000000 + // Bit H_CHENA6. + USB_HCCHAR6_H_CHENA6 = 0x80000000 + + // HCINT6 + // Position of H_XFERCOMPL6 field. + USB_HCINT6_H_XFERCOMPL6_Pos = 0x0 + // Bit mask of H_XFERCOMPL6 field. + USB_HCINT6_H_XFERCOMPL6_Msk = 0x1 + // Bit H_XFERCOMPL6. + USB_HCINT6_H_XFERCOMPL6 = 0x1 + // Position of H_CHHLTD6 field. + USB_HCINT6_H_CHHLTD6_Pos = 0x1 + // Bit mask of H_CHHLTD6 field. + USB_HCINT6_H_CHHLTD6_Msk = 0x2 + // Bit H_CHHLTD6. + USB_HCINT6_H_CHHLTD6 = 0x2 + // Position of H_AHBERR6 field. + USB_HCINT6_H_AHBERR6_Pos = 0x2 + // Bit mask of H_AHBERR6 field. + USB_HCINT6_H_AHBERR6_Msk = 0x4 + // Bit H_AHBERR6. + USB_HCINT6_H_AHBERR6 = 0x4 + // Position of H_STALL6 field. + USB_HCINT6_H_STALL6_Pos = 0x3 + // Bit mask of H_STALL6 field. + USB_HCINT6_H_STALL6_Msk = 0x8 + // Bit H_STALL6. + USB_HCINT6_H_STALL6 = 0x8 + // Position of H_NACK6 field. + USB_HCINT6_H_NACK6_Pos = 0x4 + // Bit mask of H_NACK6 field. + USB_HCINT6_H_NACK6_Msk = 0x10 + // Bit H_NACK6. + USB_HCINT6_H_NACK6 = 0x10 + // Position of H_ACK6 field. + USB_HCINT6_H_ACK6_Pos = 0x5 + // Bit mask of H_ACK6 field. + USB_HCINT6_H_ACK6_Msk = 0x20 + // Bit H_ACK6. + USB_HCINT6_H_ACK6 = 0x20 + // Position of H_NYET6 field. + USB_HCINT6_H_NYET6_Pos = 0x6 + // Bit mask of H_NYET6 field. + USB_HCINT6_H_NYET6_Msk = 0x40 + // Bit H_NYET6. + USB_HCINT6_H_NYET6 = 0x40 + // Position of H_XACTERR6 field. + USB_HCINT6_H_XACTERR6_Pos = 0x7 + // Bit mask of H_XACTERR6 field. + USB_HCINT6_H_XACTERR6_Msk = 0x80 + // Bit H_XACTERR6. + USB_HCINT6_H_XACTERR6 = 0x80 + // Position of H_BBLERR6 field. + USB_HCINT6_H_BBLERR6_Pos = 0x8 + // Bit mask of H_BBLERR6 field. + USB_HCINT6_H_BBLERR6_Msk = 0x100 + // Bit H_BBLERR6. + USB_HCINT6_H_BBLERR6 = 0x100 + // Position of H_FRMOVRUN6 field. + USB_HCINT6_H_FRMOVRUN6_Pos = 0x9 + // Bit mask of H_FRMOVRUN6 field. + USB_HCINT6_H_FRMOVRUN6_Msk = 0x200 + // Bit H_FRMOVRUN6. + USB_HCINT6_H_FRMOVRUN6 = 0x200 + // Position of H_DATATGLERR6 field. + USB_HCINT6_H_DATATGLERR6_Pos = 0xa + // Bit mask of H_DATATGLERR6 field. + USB_HCINT6_H_DATATGLERR6_Msk = 0x400 + // Bit H_DATATGLERR6. + USB_HCINT6_H_DATATGLERR6 = 0x400 + // Position of H_BNAINTR6 field. + USB_HCINT6_H_BNAINTR6_Pos = 0xb + // Bit mask of H_BNAINTR6 field. + USB_HCINT6_H_BNAINTR6_Msk = 0x800 + // Bit H_BNAINTR6. + USB_HCINT6_H_BNAINTR6 = 0x800 + // Position of H_XCS_XACT_ERR6 field. + USB_HCINT6_H_XCS_XACT_ERR6_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR6 field. + USB_HCINT6_H_XCS_XACT_ERR6_Msk = 0x1000 + // Bit H_XCS_XACT_ERR6. + USB_HCINT6_H_XCS_XACT_ERR6 = 0x1000 + // Position of H_DESC_LST_ROLLINTR6 field. + USB_HCINT6_H_DESC_LST_ROLLINTR6_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR6 field. + USB_HCINT6_H_DESC_LST_ROLLINTR6_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR6. + USB_HCINT6_H_DESC_LST_ROLLINTR6 = 0x2000 + + // HCINTMSK6 + // Position of H_XFERCOMPLMSK6 field. + USB_HCINTMSK6_H_XFERCOMPLMSK6_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK6 field. + USB_HCINTMSK6_H_XFERCOMPLMSK6_Msk = 0x1 + // Bit H_XFERCOMPLMSK6. + USB_HCINTMSK6_H_XFERCOMPLMSK6 = 0x1 + // Position of H_CHHLTDMSK6 field. + USB_HCINTMSK6_H_CHHLTDMSK6_Pos = 0x1 + // Bit mask of H_CHHLTDMSK6 field. + USB_HCINTMSK6_H_CHHLTDMSK6_Msk = 0x2 + // Bit H_CHHLTDMSK6. + USB_HCINTMSK6_H_CHHLTDMSK6 = 0x2 + // Position of H_AHBERRMSK6 field. + USB_HCINTMSK6_H_AHBERRMSK6_Pos = 0x2 + // Bit mask of H_AHBERRMSK6 field. + USB_HCINTMSK6_H_AHBERRMSK6_Msk = 0x4 + // Bit H_AHBERRMSK6. + USB_HCINTMSK6_H_AHBERRMSK6 = 0x4 + // Position of H_STALLMSK6 field. + USB_HCINTMSK6_H_STALLMSK6_Pos = 0x3 + // Bit mask of H_STALLMSK6 field. + USB_HCINTMSK6_H_STALLMSK6_Msk = 0x8 + // Bit H_STALLMSK6. + USB_HCINTMSK6_H_STALLMSK6 = 0x8 + // Position of H_NAKMSK6 field. + USB_HCINTMSK6_H_NAKMSK6_Pos = 0x4 + // Bit mask of H_NAKMSK6 field. + USB_HCINTMSK6_H_NAKMSK6_Msk = 0x10 + // Bit H_NAKMSK6. + USB_HCINTMSK6_H_NAKMSK6 = 0x10 + // Position of H_ACKMSK6 field. + USB_HCINTMSK6_H_ACKMSK6_Pos = 0x5 + // Bit mask of H_ACKMSK6 field. + USB_HCINTMSK6_H_ACKMSK6_Msk = 0x20 + // Bit H_ACKMSK6. + USB_HCINTMSK6_H_ACKMSK6 = 0x20 + // Position of H_NYETMSK6 field. + USB_HCINTMSK6_H_NYETMSK6_Pos = 0x6 + // Bit mask of H_NYETMSK6 field. + USB_HCINTMSK6_H_NYETMSK6_Msk = 0x40 + // Bit H_NYETMSK6. + USB_HCINTMSK6_H_NYETMSK6 = 0x40 + // Position of H_XACTERRMSK6 field. + USB_HCINTMSK6_H_XACTERRMSK6_Pos = 0x7 + // Bit mask of H_XACTERRMSK6 field. + USB_HCINTMSK6_H_XACTERRMSK6_Msk = 0x80 + // Bit H_XACTERRMSK6. + USB_HCINTMSK6_H_XACTERRMSK6 = 0x80 + // Position of H_BBLERRMSK6 field. + USB_HCINTMSK6_H_BBLERRMSK6_Pos = 0x8 + // Bit mask of H_BBLERRMSK6 field. + USB_HCINTMSK6_H_BBLERRMSK6_Msk = 0x100 + // Bit H_BBLERRMSK6. + USB_HCINTMSK6_H_BBLERRMSK6 = 0x100 + // Position of H_FRMOVRUNMSK6 field. + USB_HCINTMSK6_H_FRMOVRUNMSK6_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK6 field. + USB_HCINTMSK6_H_FRMOVRUNMSK6_Msk = 0x200 + // Bit H_FRMOVRUNMSK6. + USB_HCINTMSK6_H_FRMOVRUNMSK6 = 0x200 + // Position of H_DATATGLERRMSK6 field. + USB_HCINTMSK6_H_DATATGLERRMSK6_Pos = 0xa + // Bit mask of H_DATATGLERRMSK6 field. + USB_HCINTMSK6_H_DATATGLERRMSK6_Msk = 0x400 + // Bit H_DATATGLERRMSK6. + USB_HCINTMSK6_H_DATATGLERRMSK6 = 0x400 + // Position of H_BNAINTRMSK6 field. + USB_HCINTMSK6_H_BNAINTRMSK6_Pos = 0xb + // Bit mask of H_BNAINTRMSK6 field. + USB_HCINTMSK6_H_BNAINTRMSK6_Msk = 0x800 + // Bit H_BNAINTRMSK6. + USB_HCINTMSK6_H_BNAINTRMSK6 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK6 field. + USB_HCINTMSK6_H_DESC_LST_ROLLINTRMSK6_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK6 field. + USB_HCINTMSK6_H_DESC_LST_ROLLINTRMSK6_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK6. + USB_HCINTMSK6_H_DESC_LST_ROLLINTRMSK6 = 0x2000 + + // HCTSIZ6 + // Position of H_XFERSIZE6 field. + USB_HCTSIZ6_H_XFERSIZE6_Pos = 0x0 + // Bit mask of H_XFERSIZE6 field. + USB_HCTSIZ6_H_XFERSIZE6_Msk = 0x7ffff + // Position of H_PKTCNT6 field. + USB_HCTSIZ6_H_PKTCNT6_Pos = 0x13 + // Bit mask of H_PKTCNT6 field. + USB_HCTSIZ6_H_PKTCNT6_Msk = 0x1ff80000 + // Position of H_PID6 field. + USB_HCTSIZ6_H_PID6_Pos = 0x1d + // Bit mask of H_PID6 field. + USB_HCTSIZ6_H_PID6_Msk = 0x60000000 + // Position of H_DOPNG6 field. + USB_HCTSIZ6_H_DOPNG6_Pos = 0x1f + // Bit mask of H_DOPNG6 field. + USB_HCTSIZ6_H_DOPNG6_Msk = 0x80000000 + // Bit H_DOPNG6. + USB_HCTSIZ6_H_DOPNG6 = 0x80000000 + + // HCDMA6 + // Position of H_DMAADDR6 field. + USB_HCDMA6_H_DMAADDR6_Pos = 0x0 + // Bit mask of H_DMAADDR6 field. + USB_HCDMA6_H_DMAADDR6_Msk = 0xffffffff + + // HCDMAB6 + // Position of H_HCDMAB6 field. + USB_HCDMAB6_H_HCDMAB6_Pos = 0x0 + // Bit mask of H_HCDMAB6 field. + USB_HCDMAB6_H_HCDMAB6_Msk = 0xffffffff + + // HCCHAR7 + // Position of H_MPS7 field. + USB_HCCHAR7_H_MPS7_Pos = 0x0 + // Bit mask of H_MPS7 field. + USB_HCCHAR7_H_MPS7_Msk = 0x7ff + // Position of H_EPNUM7 field. + USB_HCCHAR7_H_EPNUM7_Pos = 0xb + // Bit mask of H_EPNUM7 field. + USB_HCCHAR7_H_EPNUM7_Msk = 0x7800 + // Position of H_EPDIR7 field. + USB_HCCHAR7_H_EPDIR7_Pos = 0xf + // Bit mask of H_EPDIR7 field. + USB_HCCHAR7_H_EPDIR7_Msk = 0x8000 + // Bit H_EPDIR7. + USB_HCCHAR7_H_EPDIR7 = 0x8000 + // Position of H_LSPDDEV7 field. + USB_HCCHAR7_H_LSPDDEV7_Pos = 0x11 + // Bit mask of H_LSPDDEV7 field. + USB_HCCHAR7_H_LSPDDEV7_Msk = 0x20000 + // Bit H_LSPDDEV7. + USB_HCCHAR7_H_LSPDDEV7 = 0x20000 + // Position of H_EPTYPE7 field. + USB_HCCHAR7_H_EPTYPE7_Pos = 0x12 + // Bit mask of H_EPTYPE7 field. + USB_HCCHAR7_H_EPTYPE7_Msk = 0xc0000 + // Position of H_EC7 field. + USB_HCCHAR7_H_EC7_Pos = 0x15 + // Bit mask of H_EC7 field. + USB_HCCHAR7_H_EC7_Msk = 0x200000 + // Bit H_EC7. + USB_HCCHAR7_H_EC7 = 0x200000 + // Position of H_DEVADDR7 field. + USB_HCCHAR7_H_DEVADDR7_Pos = 0x16 + // Bit mask of H_DEVADDR7 field. + USB_HCCHAR7_H_DEVADDR7_Msk = 0x1fc00000 + // Position of H_ODDFRM7 field. + USB_HCCHAR7_H_ODDFRM7_Pos = 0x1d + // Bit mask of H_ODDFRM7 field. + USB_HCCHAR7_H_ODDFRM7_Msk = 0x20000000 + // Bit H_ODDFRM7. + USB_HCCHAR7_H_ODDFRM7 = 0x20000000 + // Position of H_CHDIS7 field. + USB_HCCHAR7_H_CHDIS7_Pos = 0x1e + // Bit mask of H_CHDIS7 field. + USB_HCCHAR7_H_CHDIS7_Msk = 0x40000000 + // Bit H_CHDIS7. + USB_HCCHAR7_H_CHDIS7 = 0x40000000 + // Position of H_CHENA7 field. + USB_HCCHAR7_H_CHENA7_Pos = 0x1f + // Bit mask of H_CHENA7 field. + USB_HCCHAR7_H_CHENA7_Msk = 0x80000000 + // Bit H_CHENA7. + USB_HCCHAR7_H_CHENA7 = 0x80000000 + + // HCINT7 + // Position of H_XFERCOMPL7 field. + USB_HCINT7_H_XFERCOMPL7_Pos = 0x0 + // Bit mask of H_XFERCOMPL7 field. + USB_HCINT7_H_XFERCOMPL7_Msk = 0x1 + // Bit H_XFERCOMPL7. + USB_HCINT7_H_XFERCOMPL7 = 0x1 + // Position of H_CHHLTD7 field. + USB_HCINT7_H_CHHLTD7_Pos = 0x1 + // Bit mask of H_CHHLTD7 field. + USB_HCINT7_H_CHHLTD7_Msk = 0x2 + // Bit H_CHHLTD7. + USB_HCINT7_H_CHHLTD7 = 0x2 + // Position of H_AHBERR7 field. + USB_HCINT7_H_AHBERR7_Pos = 0x2 + // Bit mask of H_AHBERR7 field. + USB_HCINT7_H_AHBERR7_Msk = 0x4 + // Bit H_AHBERR7. + USB_HCINT7_H_AHBERR7 = 0x4 + // Position of H_STALL7 field. + USB_HCINT7_H_STALL7_Pos = 0x3 + // Bit mask of H_STALL7 field. + USB_HCINT7_H_STALL7_Msk = 0x8 + // Bit H_STALL7. + USB_HCINT7_H_STALL7 = 0x8 + // Position of H_NACK7 field. + USB_HCINT7_H_NACK7_Pos = 0x4 + // Bit mask of H_NACK7 field. + USB_HCINT7_H_NACK7_Msk = 0x10 + // Bit H_NACK7. + USB_HCINT7_H_NACK7 = 0x10 + // Position of H_ACK7 field. + USB_HCINT7_H_ACK7_Pos = 0x5 + // Bit mask of H_ACK7 field. + USB_HCINT7_H_ACK7_Msk = 0x20 + // Bit H_ACK7. + USB_HCINT7_H_ACK7 = 0x20 + // Position of H_NYET7 field. + USB_HCINT7_H_NYET7_Pos = 0x6 + // Bit mask of H_NYET7 field. + USB_HCINT7_H_NYET7_Msk = 0x40 + // Bit H_NYET7. + USB_HCINT7_H_NYET7 = 0x40 + // Position of H_XACTERR7 field. + USB_HCINT7_H_XACTERR7_Pos = 0x7 + // Bit mask of H_XACTERR7 field. + USB_HCINT7_H_XACTERR7_Msk = 0x80 + // Bit H_XACTERR7. + USB_HCINT7_H_XACTERR7 = 0x80 + // Position of H_BBLERR7 field. + USB_HCINT7_H_BBLERR7_Pos = 0x8 + // Bit mask of H_BBLERR7 field. + USB_HCINT7_H_BBLERR7_Msk = 0x100 + // Bit H_BBLERR7. + USB_HCINT7_H_BBLERR7 = 0x100 + // Position of H_FRMOVRUN7 field. + USB_HCINT7_H_FRMOVRUN7_Pos = 0x9 + // Bit mask of H_FRMOVRUN7 field. + USB_HCINT7_H_FRMOVRUN7_Msk = 0x200 + // Bit H_FRMOVRUN7. + USB_HCINT7_H_FRMOVRUN7 = 0x200 + // Position of H_DATATGLERR7 field. + USB_HCINT7_H_DATATGLERR7_Pos = 0xa + // Bit mask of H_DATATGLERR7 field. + USB_HCINT7_H_DATATGLERR7_Msk = 0x400 + // Bit H_DATATGLERR7. + USB_HCINT7_H_DATATGLERR7 = 0x400 + // Position of H_BNAINTR7 field. + USB_HCINT7_H_BNAINTR7_Pos = 0xb + // Bit mask of H_BNAINTR7 field. + USB_HCINT7_H_BNAINTR7_Msk = 0x800 + // Bit H_BNAINTR7. + USB_HCINT7_H_BNAINTR7 = 0x800 + // Position of H_XCS_XACT_ERR7 field. + USB_HCINT7_H_XCS_XACT_ERR7_Pos = 0xc + // Bit mask of H_XCS_XACT_ERR7 field. + USB_HCINT7_H_XCS_XACT_ERR7_Msk = 0x1000 + // Bit H_XCS_XACT_ERR7. + USB_HCINT7_H_XCS_XACT_ERR7 = 0x1000 + // Position of H_DESC_LST_ROLLINTR7 field. + USB_HCINT7_H_DESC_LST_ROLLINTR7_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTR7 field. + USB_HCINT7_H_DESC_LST_ROLLINTR7_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTR7. + USB_HCINT7_H_DESC_LST_ROLLINTR7 = 0x2000 + + // HCINTMSK7 + // Position of H_XFERCOMPLMSK7 field. + USB_HCINTMSK7_H_XFERCOMPLMSK7_Pos = 0x0 + // Bit mask of H_XFERCOMPLMSK7 field. + USB_HCINTMSK7_H_XFERCOMPLMSK7_Msk = 0x1 + // Bit H_XFERCOMPLMSK7. + USB_HCINTMSK7_H_XFERCOMPLMSK7 = 0x1 + // Position of H_CHHLTDMSK7 field. + USB_HCINTMSK7_H_CHHLTDMSK7_Pos = 0x1 + // Bit mask of H_CHHLTDMSK7 field. + USB_HCINTMSK7_H_CHHLTDMSK7_Msk = 0x2 + // Bit H_CHHLTDMSK7. + USB_HCINTMSK7_H_CHHLTDMSK7 = 0x2 + // Position of H_AHBERRMSK7 field. + USB_HCINTMSK7_H_AHBERRMSK7_Pos = 0x2 + // Bit mask of H_AHBERRMSK7 field. + USB_HCINTMSK7_H_AHBERRMSK7_Msk = 0x4 + // Bit H_AHBERRMSK7. + USB_HCINTMSK7_H_AHBERRMSK7 = 0x4 + // Position of H_STALLMSK7 field. + USB_HCINTMSK7_H_STALLMSK7_Pos = 0x3 + // Bit mask of H_STALLMSK7 field. + USB_HCINTMSK7_H_STALLMSK7_Msk = 0x8 + // Bit H_STALLMSK7. + USB_HCINTMSK7_H_STALLMSK7 = 0x8 + // Position of H_NAKMSK7 field. + USB_HCINTMSK7_H_NAKMSK7_Pos = 0x4 + // Bit mask of H_NAKMSK7 field. + USB_HCINTMSK7_H_NAKMSK7_Msk = 0x10 + // Bit H_NAKMSK7. + USB_HCINTMSK7_H_NAKMSK7 = 0x10 + // Position of H_ACKMSK7 field. + USB_HCINTMSK7_H_ACKMSK7_Pos = 0x5 + // Bit mask of H_ACKMSK7 field. + USB_HCINTMSK7_H_ACKMSK7_Msk = 0x20 + // Bit H_ACKMSK7. + USB_HCINTMSK7_H_ACKMSK7 = 0x20 + // Position of H_NYETMSK7 field. + USB_HCINTMSK7_H_NYETMSK7_Pos = 0x6 + // Bit mask of H_NYETMSK7 field. + USB_HCINTMSK7_H_NYETMSK7_Msk = 0x40 + // Bit H_NYETMSK7. + USB_HCINTMSK7_H_NYETMSK7 = 0x40 + // Position of H_XACTERRMSK7 field. + USB_HCINTMSK7_H_XACTERRMSK7_Pos = 0x7 + // Bit mask of H_XACTERRMSK7 field. + USB_HCINTMSK7_H_XACTERRMSK7_Msk = 0x80 + // Bit H_XACTERRMSK7. + USB_HCINTMSK7_H_XACTERRMSK7 = 0x80 + // Position of H_BBLERRMSK7 field. + USB_HCINTMSK7_H_BBLERRMSK7_Pos = 0x8 + // Bit mask of H_BBLERRMSK7 field. + USB_HCINTMSK7_H_BBLERRMSK7_Msk = 0x100 + // Bit H_BBLERRMSK7. + USB_HCINTMSK7_H_BBLERRMSK7 = 0x100 + // Position of H_FRMOVRUNMSK7 field. + USB_HCINTMSK7_H_FRMOVRUNMSK7_Pos = 0x9 + // Bit mask of H_FRMOVRUNMSK7 field. + USB_HCINTMSK7_H_FRMOVRUNMSK7_Msk = 0x200 + // Bit H_FRMOVRUNMSK7. + USB_HCINTMSK7_H_FRMOVRUNMSK7 = 0x200 + // Position of H_DATATGLERRMSK7 field. + USB_HCINTMSK7_H_DATATGLERRMSK7_Pos = 0xa + // Bit mask of H_DATATGLERRMSK7 field. + USB_HCINTMSK7_H_DATATGLERRMSK7_Msk = 0x400 + // Bit H_DATATGLERRMSK7. + USB_HCINTMSK7_H_DATATGLERRMSK7 = 0x400 + // Position of H_BNAINTRMSK7 field. + USB_HCINTMSK7_H_BNAINTRMSK7_Pos = 0xb + // Bit mask of H_BNAINTRMSK7 field. + USB_HCINTMSK7_H_BNAINTRMSK7_Msk = 0x800 + // Bit H_BNAINTRMSK7. + USB_HCINTMSK7_H_BNAINTRMSK7 = 0x800 + // Position of H_DESC_LST_ROLLINTRMSK7 field. + USB_HCINTMSK7_H_DESC_LST_ROLLINTRMSK7_Pos = 0xd + // Bit mask of H_DESC_LST_ROLLINTRMSK7 field. + USB_HCINTMSK7_H_DESC_LST_ROLLINTRMSK7_Msk = 0x2000 + // Bit H_DESC_LST_ROLLINTRMSK7. + USB_HCINTMSK7_H_DESC_LST_ROLLINTRMSK7 = 0x2000 + + // HCTSIZ7 + // Position of H_XFERSIZE7 field. + USB_HCTSIZ7_H_XFERSIZE7_Pos = 0x0 + // Bit mask of H_XFERSIZE7 field. + USB_HCTSIZ7_H_XFERSIZE7_Msk = 0x7ffff + // Position of H_PKTCNT7 field. + USB_HCTSIZ7_H_PKTCNT7_Pos = 0x13 + // Bit mask of H_PKTCNT7 field. + USB_HCTSIZ7_H_PKTCNT7_Msk = 0x1ff80000 + // Position of H_PID7 field. + USB_HCTSIZ7_H_PID7_Pos = 0x1d + // Bit mask of H_PID7 field. + USB_HCTSIZ7_H_PID7_Msk = 0x60000000 + // Position of H_DOPNG7 field. + USB_HCTSIZ7_H_DOPNG7_Pos = 0x1f + // Bit mask of H_DOPNG7 field. + USB_HCTSIZ7_H_DOPNG7_Msk = 0x80000000 + // Bit H_DOPNG7. + USB_HCTSIZ7_H_DOPNG7 = 0x80000000 + + // HCDMA7 + // Position of H_DMAADDR7 field. + USB_HCDMA7_H_DMAADDR7_Pos = 0x0 + // Bit mask of H_DMAADDR7 field. + USB_HCDMA7_H_DMAADDR7_Msk = 0xffffffff + + // HCDMAB7 + // Position of H_HCDMAB7 field. + USB_HCDMAB7_H_HCDMAB7_Pos = 0x0 + // Bit mask of H_HCDMAB7 field. + USB_HCDMAB7_H_HCDMAB7_Msk = 0xffffffff + + // DCFG + // Position of NZSTSOUTHSHK field. + USB_DCFG_NZSTSOUTHSHK_Pos = 0x2 + // Bit mask of NZSTSOUTHSHK field. + USB_DCFG_NZSTSOUTHSHK_Msk = 0x4 + // Bit NZSTSOUTHSHK. + USB_DCFG_NZSTSOUTHSHK = 0x4 + // Position of ENA32KHZSUSP field. + USB_DCFG_ENA32KHZSUSP_Pos = 0x3 + // Bit mask of ENA32KHZSUSP field. + USB_DCFG_ENA32KHZSUSP_Msk = 0x8 + // Bit ENA32KHZSUSP. + USB_DCFG_ENA32KHZSUSP = 0x8 + // Position of DEVADDR field. + USB_DCFG_DEVADDR_Pos = 0x4 + // Bit mask of DEVADDR field. + USB_DCFG_DEVADDR_Msk = 0x7f0 + // Position of PERFRLINT field. + USB_DCFG_PERFRLINT_Pos = 0xb + // Bit mask of PERFRLINT field. + USB_DCFG_PERFRLINT_Msk = 0x1800 + // Position of ENDEVOUTNAK field. + USB_DCFG_ENDEVOUTNAK_Pos = 0xd + // Bit mask of ENDEVOUTNAK field. + USB_DCFG_ENDEVOUTNAK_Msk = 0x2000 + // Bit ENDEVOUTNAK. + USB_DCFG_ENDEVOUTNAK = 0x2000 + // Position of XCVRDLY field. + USB_DCFG_XCVRDLY_Pos = 0xe + // Bit mask of XCVRDLY field. + USB_DCFG_XCVRDLY_Msk = 0x4000 + // Bit XCVRDLY. + USB_DCFG_XCVRDLY = 0x4000 + // Position of ERRATICINTMSK field. + USB_DCFG_ERRATICINTMSK_Pos = 0xf + // Bit mask of ERRATICINTMSK field. + USB_DCFG_ERRATICINTMSK_Msk = 0x8000 + // Bit ERRATICINTMSK. + USB_DCFG_ERRATICINTMSK = 0x8000 + // Position of EPMISCNT field. + USB_DCFG_EPMISCNT_Pos = 0x12 + // Bit mask of EPMISCNT field. + USB_DCFG_EPMISCNT_Msk = 0x7c0000 + // Position of DESCDMA field. + USB_DCFG_DESCDMA_Pos = 0x17 + // Bit mask of DESCDMA field. + USB_DCFG_DESCDMA_Msk = 0x800000 + // Bit DESCDMA. + USB_DCFG_DESCDMA = 0x800000 + // Position of PERSCHINTVL field. + USB_DCFG_PERSCHINTVL_Pos = 0x18 + // Bit mask of PERSCHINTVL field. + USB_DCFG_PERSCHINTVL_Msk = 0x3000000 + // Position of RESVALID field. + USB_DCFG_RESVALID_Pos = 0x1a + // Bit mask of RESVALID field. + USB_DCFG_RESVALID_Msk = 0xfc000000 + + // DCTL + // Position of RMTWKUPSIG field. + USB_DCTL_RMTWKUPSIG_Pos = 0x0 + // Bit mask of RMTWKUPSIG field. + USB_DCTL_RMTWKUPSIG_Msk = 0x1 + // Bit RMTWKUPSIG. + USB_DCTL_RMTWKUPSIG = 0x1 + // Position of SFTDISCON field. + USB_DCTL_SFTDISCON_Pos = 0x1 + // Bit mask of SFTDISCON field. + USB_DCTL_SFTDISCON_Msk = 0x2 + // Bit SFTDISCON. + USB_DCTL_SFTDISCON = 0x2 + // Position of GNPINNAKSTS field. + USB_DCTL_GNPINNAKSTS_Pos = 0x2 + // Bit mask of GNPINNAKSTS field. + USB_DCTL_GNPINNAKSTS_Msk = 0x4 + // Bit GNPINNAKSTS. + USB_DCTL_GNPINNAKSTS = 0x4 + // Position of GOUTNAKSTS field. + USB_DCTL_GOUTNAKSTS_Pos = 0x3 + // Bit mask of GOUTNAKSTS field. + USB_DCTL_GOUTNAKSTS_Msk = 0x8 + // Bit GOUTNAKSTS. + USB_DCTL_GOUTNAKSTS = 0x8 + // Position of TSTCTL field. + USB_DCTL_TSTCTL_Pos = 0x4 + // Bit mask of TSTCTL field. + USB_DCTL_TSTCTL_Msk = 0x70 + // Position of SGNPINNAK field. + USB_DCTL_SGNPINNAK_Pos = 0x7 + // Bit mask of SGNPINNAK field. + USB_DCTL_SGNPINNAK_Msk = 0x80 + // Bit SGNPINNAK. + USB_DCTL_SGNPINNAK = 0x80 + // Position of CGNPINNAK field. + USB_DCTL_CGNPINNAK_Pos = 0x8 + // Bit mask of CGNPINNAK field. + USB_DCTL_CGNPINNAK_Msk = 0x100 + // Bit CGNPINNAK. + USB_DCTL_CGNPINNAK = 0x100 + // Position of SGOUTNAK field. + USB_DCTL_SGOUTNAK_Pos = 0x9 + // Bit mask of SGOUTNAK field. + USB_DCTL_SGOUTNAK_Msk = 0x200 + // Bit SGOUTNAK. + USB_DCTL_SGOUTNAK = 0x200 + // Position of CGOUTNAK field. + USB_DCTL_CGOUTNAK_Pos = 0xa + // Bit mask of CGOUTNAK field. + USB_DCTL_CGOUTNAK_Msk = 0x400 + // Bit CGOUTNAK. + USB_DCTL_CGOUTNAK = 0x400 + // Position of PWRONPRGDONE field. + USB_DCTL_PWRONPRGDONE_Pos = 0xb + // Bit mask of PWRONPRGDONE field. + USB_DCTL_PWRONPRGDONE_Msk = 0x800 + // Bit PWRONPRGDONE. + USB_DCTL_PWRONPRGDONE = 0x800 + // Position of GMC field. + USB_DCTL_GMC_Pos = 0xd + // Bit mask of GMC field. + USB_DCTL_GMC_Msk = 0x6000 + // Position of IGNRFRMNUM field. + USB_DCTL_IGNRFRMNUM_Pos = 0xf + // Bit mask of IGNRFRMNUM field. + USB_DCTL_IGNRFRMNUM_Msk = 0x8000 + // Bit IGNRFRMNUM. + USB_DCTL_IGNRFRMNUM = 0x8000 + // Position of NAKONBBLE field. + USB_DCTL_NAKONBBLE_Pos = 0x10 + // Bit mask of NAKONBBLE field. + USB_DCTL_NAKONBBLE_Msk = 0x10000 + // Bit NAKONBBLE. + USB_DCTL_NAKONBBLE = 0x10000 + // Position of ENCOUNTONBNA field. + USB_DCTL_ENCOUNTONBNA_Pos = 0x11 + // Bit mask of ENCOUNTONBNA field. + USB_DCTL_ENCOUNTONBNA_Msk = 0x20000 + // Bit ENCOUNTONBNA. + USB_DCTL_ENCOUNTONBNA = 0x20000 + // Position of DEEPSLEEPBESLREJECT field. + USB_DCTL_DEEPSLEEPBESLREJECT_Pos = 0x12 + // Bit mask of DEEPSLEEPBESLREJECT field. + USB_DCTL_DEEPSLEEPBESLREJECT_Msk = 0x40000 + // Bit DEEPSLEEPBESLREJECT. + USB_DCTL_DEEPSLEEPBESLREJECT = 0x40000 + + // DSTS + // Position of SUSPSTS field. + USB_DSTS_SUSPSTS_Pos = 0x0 + // Bit mask of SUSPSTS field. + USB_DSTS_SUSPSTS_Msk = 0x1 + // Bit SUSPSTS. + USB_DSTS_SUSPSTS = 0x1 + // Position of ENUMSPD field. + USB_DSTS_ENUMSPD_Pos = 0x1 + // Bit mask of ENUMSPD field. + USB_DSTS_ENUMSPD_Msk = 0x6 + // Position of ERRTICERR field. + USB_DSTS_ERRTICERR_Pos = 0x3 + // Bit mask of ERRTICERR field. + USB_DSTS_ERRTICERR_Msk = 0x8 + // Bit ERRTICERR. + USB_DSTS_ERRTICERR = 0x8 + // Position of SOFFN field. + USB_DSTS_SOFFN_Pos = 0x8 + // Bit mask of SOFFN field. + USB_DSTS_SOFFN_Msk = 0x3fff00 + // Position of DEVLNSTS field. + USB_DSTS_DEVLNSTS_Pos = 0x16 + // Bit mask of DEVLNSTS field. + USB_DSTS_DEVLNSTS_Msk = 0xc00000 + + // DIEPMSK + // Position of DI_XFERCOMPLMSK field. + USB_DIEPMSK_DI_XFERCOMPLMSK_Pos = 0x0 + // Bit mask of DI_XFERCOMPLMSK field. + USB_DIEPMSK_DI_XFERCOMPLMSK_Msk = 0x1 + // Bit DI_XFERCOMPLMSK. + USB_DIEPMSK_DI_XFERCOMPLMSK = 0x1 + // Position of DI_EPDISBLDMSK field. + USB_DIEPMSK_DI_EPDISBLDMSK_Pos = 0x1 + // Bit mask of DI_EPDISBLDMSK field. + USB_DIEPMSK_DI_EPDISBLDMSK_Msk = 0x2 + // Bit DI_EPDISBLDMSK. + USB_DIEPMSK_DI_EPDISBLDMSK = 0x2 + // Position of DI_AHBERMSK field. + USB_DIEPMSK_DI_AHBERMSK_Pos = 0x2 + // Bit mask of DI_AHBERMSK field. + USB_DIEPMSK_DI_AHBERMSK_Msk = 0x4 + // Bit DI_AHBERMSK. + USB_DIEPMSK_DI_AHBERMSK = 0x4 + // Position of TIMEOUTMSK field. + USB_DIEPMSK_TIMEOUTMSK_Pos = 0x3 + // Bit mask of TIMEOUTMSK field. + USB_DIEPMSK_TIMEOUTMSK_Msk = 0x8 + // Bit TIMEOUTMSK. + USB_DIEPMSK_TIMEOUTMSK = 0x8 + // Position of INTKNTXFEMPMSK field. + USB_DIEPMSK_INTKNTXFEMPMSK_Pos = 0x4 + // Bit mask of INTKNTXFEMPMSK field. + USB_DIEPMSK_INTKNTXFEMPMSK_Msk = 0x10 + // Bit INTKNTXFEMPMSK. + USB_DIEPMSK_INTKNTXFEMPMSK = 0x10 + // Position of INTKNEPMISMSK field. + USB_DIEPMSK_INTKNEPMISMSK_Pos = 0x5 + // Bit mask of INTKNEPMISMSK field. + USB_DIEPMSK_INTKNEPMISMSK_Msk = 0x20 + // Bit INTKNEPMISMSK. + USB_DIEPMSK_INTKNEPMISMSK = 0x20 + // Position of INEPNAKEFFMSK field. + USB_DIEPMSK_INEPNAKEFFMSK_Pos = 0x6 + // Bit mask of INEPNAKEFFMSK field. + USB_DIEPMSK_INEPNAKEFFMSK_Msk = 0x40 + // Bit INEPNAKEFFMSK. + USB_DIEPMSK_INEPNAKEFFMSK = 0x40 + // Position of TXFIFOUNDRNMSK field. + USB_DIEPMSK_TXFIFOUNDRNMSK_Pos = 0x8 + // Bit mask of TXFIFOUNDRNMSK field. + USB_DIEPMSK_TXFIFOUNDRNMSK_Msk = 0x100 + // Bit TXFIFOUNDRNMSK. + USB_DIEPMSK_TXFIFOUNDRNMSK = 0x100 + // Position of BNAININTRMSK field. + USB_DIEPMSK_BNAININTRMSK_Pos = 0x9 + // Bit mask of BNAININTRMSK field. + USB_DIEPMSK_BNAININTRMSK_Msk = 0x200 + // Bit BNAININTRMSK. + USB_DIEPMSK_BNAININTRMSK = 0x200 + // Position of DI_NAKMSK field. + USB_DIEPMSK_DI_NAKMSK_Pos = 0xd + // Bit mask of DI_NAKMSK field. + USB_DIEPMSK_DI_NAKMSK_Msk = 0x2000 + // Bit DI_NAKMSK. + USB_DIEPMSK_DI_NAKMSK = 0x2000 + + // DOEPMSK + // Position of XFERCOMPLMSK field. + USB_DOEPMSK_XFERCOMPLMSK_Pos = 0x0 + // Bit mask of XFERCOMPLMSK field. + USB_DOEPMSK_XFERCOMPLMSK_Msk = 0x1 + // Bit XFERCOMPLMSK. + USB_DOEPMSK_XFERCOMPLMSK = 0x1 + // Position of EPDISBLDMSK field. + USB_DOEPMSK_EPDISBLDMSK_Pos = 0x1 + // Bit mask of EPDISBLDMSK field. + USB_DOEPMSK_EPDISBLDMSK_Msk = 0x2 + // Bit EPDISBLDMSK. + USB_DOEPMSK_EPDISBLDMSK = 0x2 + // Position of AHBERMSK field. + USB_DOEPMSK_AHBERMSK_Pos = 0x2 + // Bit mask of AHBERMSK field. + USB_DOEPMSK_AHBERMSK_Msk = 0x4 + // Bit AHBERMSK. + USB_DOEPMSK_AHBERMSK = 0x4 + // Position of SETUPMSK field. + USB_DOEPMSK_SETUPMSK_Pos = 0x3 + // Bit mask of SETUPMSK field. + USB_DOEPMSK_SETUPMSK_Msk = 0x8 + // Bit SETUPMSK. + USB_DOEPMSK_SETUPMSK = 0x8 + // Position of OUTTKNEPDISMSK field. + USB_DOEPMSK_OUTTKNEPDISMSK_Pos = 0x4 + // Bit mask of OUTTKNEPDISMSK field. + USB_DOEPMSK_OUTTKNEPDISMSK_Msk = 0x10 + // Bit OUTTKNEPDISMSK. + USB_DOEPMSK_OUTTKNEPDISMSK = 0x10 + // Position of STSPHSERCVDMSK field. + USB_DOEPMSK_STSPHSERCVDMSK_Pos = 0x5 + // Bit mask of STSPHSERCVDMSK field. + USB_DOEPMSK_STSPHSERCVDMSK_Msk = 0x20 + // Bit STSPHSERCVDMSK. + USB_DOEPMSK_STSPHSERCVDMSK = 0x20 + // Position of BACK2BACKSETUP field. + USB_DOEPMSK_BACK2BACKSETUP_Pos = 0x6 + // Bit mask of BACK2BACKSETUP field. + USB_DOEPMSK_BACK2BACKSETUP_Msk = 0x40 + // Bit BACK2BACKSETUP. + USB_DOEPMSK_BACK2BACKSETUP = 0x40 + // Position of OUTPKTERRMSK field. + USB_DOEPMSK_OUTPKTERRMSK_Pos = 0x8 + // Bit mask of OUTPKTERRMSK field. + USB_DOEPMSK_OUTPKTERRMSK_Msk = 0x100 + // Bit OUTPKTERRMSK. + USB_DOEPMSK_OUTPKTERRMSK = 0x100 + // Position of BNAOUTINTRMSK field. + USB_DOEPMSK_BNAOUTINTRMSK_Pos = 0x9 + // Bit mask of BNAOUTINTRMSK field. + USB_DOEPMSK_BNAOUTINTRMSK_Msk = 0x200 + // Bit BNAOUTINTRMSK. + USB_DOEPMSK_BNAOUTINTRMSK = 0x200 + // Position of BBLEERRMSK field. + USB_DOEPMSK_BBLEERRMSK_Pos = 0xc + // Bit mask of BBLEERRMSK field. + USB_DOEPMSK_BBLEERRMSK_Msk = 0x1000 + // Bit BBLEERRMSK. + USB_DOEPMSK_BBLEERRMSK = 0x1000 + // Position of NAKMSK field. + USB_DOEPMSK_NAKMSK_Pos = 0xd + // Bit mask of NAKMSK field. + USB_DOEPMSK_NAKMSK_Msk = 0x2000 + // Bit NAKMSK. + USB_DOEPMSK_NAKMSK = 0x2000 + // Position of NYETMSK field. + USB_DOEPMSK_NYETMSK_Pos = 0xe + // Bit mask of NYETMSK field. + USB_DOEPMSK_NYETMSK_Msk = 0x4000 + // Bit NYETMSK. + USB_DOEPMSK_NYETMSK = 0x4000 + + // DAINT + // Position of INEPINT0 field. + USB_DAINT_INEPINT0_Pos = 0x0 + // Bit mask of INEPINT0 field. + USB_DAINT_INEPINT0_Msk = 0x1 + // Bit INEPINT0. + USB_DAINT_INEPINT0 = 0x1 + // Position of INEPINT1 field. + USB_DAINT_INEPINT1_Pos = 0x1 + // Bit mask of INEPINT1 field. + USB_DAINT_INEPINT1_Msk = 0x2 + // Bit INEPINT1. + USB_DAINT_INEPINT1 = 0x2 + // Position of INEPINT2 field. + USB_DAINT_INEPINT2_Pos = 0x2 + // Bit mask of INEPINT2 field. + USB_DAINT_INEPINT2_Msk = 0x4 + // Bit INEPINT2. + USB_DAINT_INEPINT2 = 0x4 + // Position of INEPINT3 field. + USB_DAINT_INEPINT3_Pos = 0x3 + // Bit mask of INEPINT3 field. + USB_DAINT_INEPINT3_Msk = 0x8 + // Bit INEPINT3. + USB_DAINT_INEPINT3 = 0x8 + // Position of INEPINT4 field. + USB_DAINT_INEPINT4_Pos = 0x4 + // Bit mask of INEPINT4 field. + USB_DAINT_INEPINT4_Msk = 0x10 + // Bit INEPINT4. + USB_DAINT_INEPINT4 = 0x10 + // Position of INEPINT5 field. + USB_DAINT_INEPINT5_Pos = 0x5 + // Bit mask of INEPINT5 field. + USB_DAINT_INEPINT5_Msk = 0x20 + // Bit INEPINT5. + USB_DAINT_INEPINT5 = 0x20 + // Position of INEPINT6 field. + USB_DAINT_INEPINT6_Pos = 0x6 + // Bit mask of INEPINT6 field. + USB_DAINT_INEPINT6_Msk = 0x40 + // Bit INEPINT6. + USB_DAINT_INEPINT6 = 0x40 + // Position of OUTEPINT0 field. + USB_DAINT_OUTEPINT0_Pos = 0x10 + // Bit mask of OUTEPINT0 field. + USB_DAINT_OUTEPINT0_Msk = 0x10000 + // Bit OUTEPINT0. + USB_DAINT_OUTEPINT0 = 0x10000 + // Position of OUTEPINT1 field. + USB_DAINT_OUTEPINT1_Pos = 0x11 + // Bit mask of OUTEPINT1 field. + USB_DAINT_OUTEPINT1_Msk = 0x20000 + // Bit OUTEPINT1. + USB_DAINT_OUTEPINT1 = 0x20000 + // Position of OUTEPINT2 field. + USB_DAINT_OUTEPINT2_Pos = 0x12 + // Bit mask of OUTEPINT2 field. + USB_DAINT_OUTEPINT2_Msk = 0x40000 + // Bit OUTEPINT2. + USB_DAINT_OUTEPINT2 = 0x40000 + // Position of OUTEPINT3 field. + USB_DAINT_OUTEPINT3_Pos = 0x13 + // Bit mask of OUTEPINT3 field. + USB_DAINT_OUTEPINT3_Msk = 0x80000 + // Bit OUTEPINT3. + USB_DAINT_OUTEPINT3 = 0x80000 + // Position of OUTEPINT4 field. + USB_DAINT_OUTEPINT4_Pos = 0x14 + // Bit mask of OUTEPINT4 field. + USB_DAINT_OUTEPINT4_Msk = 0x100000 + // Bit OUTEPINT4. + USB_DAINT_OUTEPINT4 = 0x100000 + // Position of OUTEPINT5 field. + USB_DAINT_OUTEPINT5_Pos = 0x15 + // Bit mask of OUTEPINT5 field. + USB_DAINT_OUTEPINT5_Msk = 0x200000 + // Bit OUTEPINT5. + USB_DAINT_OUTEPINT5 = 0x200000 + // Position of OUTEPINT6 field. + USB_DAINT_OUTEPINT6_Pos = 0x16 + // Bit mask of OUTEPINT6 field. + USB_DAINT_OUTEPINT6_Msk = 0x400000 + // Bit OUTEPINT6. + USB_DAINT_OUTEPINT6 = 0x400000 + + // DAINTMSK + // Position of INEPMSK0 field. + USB_DAINTMSK_INEPMSK0_Pos = 0x0 + // Bit mask of INEPMSK0 field. + USB_DAINTMSK_INEPMSK0_Msk = 0x1 + // Bit INEPMSK0. + USB_DAINTMSK_INEPMSK0 = 0x1 + // Position of INEPMSK1 field. + USB_DAINTMSK_INEPMSK1_Pos = 0x1 + // Bit mask of INEPMSK1 field. + USB_DAINTMSK_INEPMSK1_Msk = 0x2 + // Bit INEPMSK1. + USB_DAINTMSK_INEPMSK1 = 0x2 + // Position of INEPMSK2 field. + USB_DAINTMSK_INEPMSK2_Pos = 0x2 + // Bit mask of INEPMSK2 field. + USB_DAINTMSK_INEPMSK2_Msk = 0x4 + // Bit INEPMSK2. + USB_DAINTMSK_INEPMSK2 = 0x4 + // Position of INEPMSK3 field. + USB_DAINTMSK_INEPMSK3_Pos = 0x3 + // Bit mask of INEPMSK3 field. + USB_DAINTMSK_INEPMSK3_Msk = 0x8 + // Bit INEPMSK3. + USB_DAINTMSK_INEPMSK3 = 0x8 + // Position of INEPMSK4 field. + USB_DAINTMSK_INEPMSK4_Pos = 0x4 + // Bit mask of INEPMSK4 field. + USB_DAINTMSK_INEPMSK4_Msk = 0x10 + // Bit INEPMSK4. + USB_DAINTMSK_INEPMSK4 = 0x10 + // Position of INEPMSK5 field. + USB_DAINTMSK_INEPMSK5_Pos = 0x5 + // Bit mask of INEPMSK5 field. + USB_DAINTMSK_INEPMSK5_Msk = 0x20 + // Bit INEPMSK5. + USB_DAINTMSK_INEPMSK5 = 0x20 + // Position of INEPMSK6 field. + USB_DAINTMSK_INEPMSK6_Pos = 0x6 + // Bit mask of INEPMSK6 field. + USB_DAINTMSK_INEPMSK6_Msk = 0x40 + // Bit INEPMSK6. + USB_DAINTMSK_INEPMSK6 = 0x40 + // Position of OUTEPMSK0 field. + USB_DAINTMSK_OUTEPMSK0_Pos = 0x10 + // Bit mask of OUTEPMSK0 field. + USB_DAINTMSK_OUTEPMSK0_Msk = 0x10000 + // Bit OUTEPMSK0. + USB_DAINTMSK_OUTEPMSK0 = 0x10000 + // Position of OUTEPMSK1 field. + USB_DAINTMSK_OUTEPMSK1_Pos = 0x11 + // Bit mask of OUTEPMSK1 field. + USB_DAINTMSK_OUTEPMSK1_Msk = 0x20000 + // Bit OUTEPMSK1. + USB_DAINTMSK_OUTEPMSK1 = 0x20000 + // Position of OUTEPMSK2 field. + USB_DAINTMSK_OUTEPMSK2_Pos = 0x12 + // Bit mask of OUTEPMSK2 field. + USB_DAINTMSK_OUTEPMSK2_Msk = 0x40000 + // Bit OUTEPMSK2. + USB_DAINTMSK_OUTEPMSK2 = 0x40000 + // Position of OUTEPMSK3 field. + USB_DAINTMSK_OUTEPMSK3_Pos = 0x13 + // Bit mask of OUTEPMSK3 field. + USB_DAINTMSK_OUTEPMSK3_Msk = 0x80000 + // Bit OUTEPMSK3. + USB_DAINTMSK_OUTEPMSK3 = 0x80000 + // Position of OUTEPMSK4 field. + USB_DAINTMSK_OUTEPMSK4_Pos = 0x14 + // Bit mask of OUTEPMSK4 field. + USB_DAINTMSK_OUTEPMSK4_Msk = 0x100000 + // Bit OUTEPMSK4. + USB_DAINTMSK_OUTEPMSK4 = 0x100000 + // Position of OUTEPMSK5 field. + USB_DAINTMSK_OUTEPMSK5_Pos = 0x15 + // Bit mask of OUTEPMSK5 field. + USB_DAINTMSK_OUTEPMSK5_Msk = 0x200000 + // Bit OUTEPMSK5. + USB_DAINTMSK_OUTEPMSK5 = 0x200000 + // Position of OUTEPMSK6 field. + USB_DAINTMSK_OUTEPMSK6_Pos = 0x16 + // Bit mask of OUTEPMSK6 field. + USB_DAINTMSK_OUTEPMSK6_Msk = 0x400000 + // Bit OUTEPMSK6. + USB_DAINTMSK_OUTEPMSK6 = 0x400000 + + // DVBUSDIS + // Position of DVBUSDIS field. + USB_DVBUSDIS_DVBUSDIS_Pos = 0x0 + // Bit mask of DVBUSDIS field. + USB_DVBUSDIS_DVBUSDIS_Msk = 0xffff + + // DVBUSPULSE + // Position of DVBUSPULSE field. + USB_DVBUSPULSE_DVBUSPULSE_Pos = 0x0 + // Bit mask of DVBUSPULSE field. + USB_DVBUSPULSE_DVBUSPULSE_Msk = 0xfff + + // DTHRCTL + // Position of NONISOTHREN field. + USB_DTHRCTL_NONISOTHREN_Pos = 0x0 + // Bit mask of NONISOTHREN field. + USB_DTHRCTL_NONISOTHREN_Msk = 0x1 + // Bit NONISOTHREN. + USB_DTHRCTL_NONISOTHREN = 0x1 + // Position of ISOTHREN field. + USB_DTHRCTL_ISOTHREN_Pos = 0x1 + // Bit mask of ISOTHREN field. + USB_DTHRCTL_ISOTHREN_Msk = 0x2 + // Bit ISOTHREN. + USB_DTHRCTL_ISOTHREN = 0x2 + // Position of TXTHRLEN field. + USB_DTHRCTL_TXTHRLEN_Pos = 0x2 + // Bit mask of TXTHRLEN field. + USB_DTHRCTL_TXTHRLEN_Msk = 0x7fc + // Position of AHBTHRRATIO field. + USB_DTHRCTL_AHBTHRRATIO_Pos = 0xb + // Bit mask of AHBTHRRATIO field. + USB_DTHRCTL_AHBTHRRATIO_Msk = 0x1800 + // Position of RXTHREN field. + USB_DTHRCTL_RXTHREN_Pos = 0x10 + // Bit mask of RXTHREN field. + USB_DTHRCTL_RXTHREN_Msk = 0x10000 + // Bit RXTHREN. + USB_DTHRCTL_RXTHREN = 0x10000 + // Position of RXTHRLEN field. + USB_DTHRCTL_RXTHRLEN_Pos = 0x11 + // Bit mask of RXTHRLEN field. + USB_DTHRCTL_RXTHRLEN_Msk = 0x3fe0000 + // Position of ARBPRKEN field. + USB_DTHRCTL_ARBPRKEN_Pos = 0x1b + // Bit mask of ARBPRKEN field. + USB_DTHRCTL_ARBPRKEN_Msk = 0x8000000 + // Bit ARBPRKEN. + USB_DTHRCTL_ARBPRKEN = 0x8000000 + + // DIEPEMPMSK + // Position of D_INEPTXFEMPMSK field. + USB_DIEPEMPMSK_D_INEPTXFEMPMSK_Pos = 0x0 + // Bit mask of D_INEPTXFEMPMSK field. + USB_DIEPEMPMSK_D_INEPTXFEMPMSK_Msk = 0xffff + + // DIEPCTL0 + // Position of D_MPS0 field. + USB_DIEPCTL0_D_MPS0_Pos = 0x0 + // Bit mask of D_MPS0 field. + USB_DIEPCTL0_D_MPS0_Msk = 0x3 + // Position of D_USBACTEP0 field. + USB_DIEPCTL0_D_USBACTEP0_Pos = 0xf + // Bit mask of D_USBACTEP0 field. + USB_DIEPCTL0_D_USBACTEP0_Msk = 0x8000 + // Bit D_USBACTEP0. + USB_DIEPCTL0_D_USBACTEP0 = 0x8000 + // Position of D_NAKSTS0 field. + USB_DIEPCTL0_D_NAKSTS0_Pos = 0x11 + // Bit mask of D_NAKSTS0 field. + USB_DIEPCTL0_D_NAKSTS0_Msk = 0x20000 + // Bit D_NAKSTS0. + USB_DIEPCTL0_D_NAKSTS0 = 0x20000 + // Position of D_EPTYPE0 field. + USB_DIEPCTL0_D_EPTYPE0_Pos = 0x12 + // Bit mask of D_EPTYPE0 field. + USB_DIEPCTL0_D_EPTYPE0_Msk = 0xc0000 + // Position of D_STALL0 field. + USB_DIEPCTL0_D_STALL0_Pos = 0x15 + // Bit mask of D_STALL0 field. + USB_DIEPCTL0_D_STALL0_Msk = 0x200000 + // Bit D_STALL0. + USB_DIEPCTL0_D_STALL0 = 0x200000 + // Position of D_TXFNUM0 field. + USB_DIEPCTL0_D_TXFNUM0_Pos = 0x16 + // Bit mask of D_TXFNUM0 field. + USB_DIEPCTL0_D_TXFNUM0_Msk = 0x3c00000 + // Position of D_CNAK0 field. + USB_DIEPCTL0_D_CNAK0_Pos = 0x1a + // Bit mask of D_CNAK0 field. + USB_DIEPCTL0_D_CNAK0_Msk = 0x4000000 + // Bit D_CNAK0. + USB_DIEPCTL0_D_CNAK0 = 0x4000000 + // Position of DI_SNAK0 field. + USB_DIEPCTL0_DI_SNAK0_Pos = 0x1b + // Bit mask of DI_SNAK0 field. + USB_DIEPCTL0_DI_SNAK0_Msk = 0x8000000 + // Bit DI_SNAK0. + USB_DIEPCTL0_DI_SNAK0 = 0x8000000 + // Position of D_EPDIS0 field. + USB_DIEPCTL0_D_EPDIS0_Pos = 0x1e + // Bit mask of D_EPDIS0 field. + USB_DIEPCTL0_D_EPDIS0_Msk = 0x40000000 + // Bit D_EPDIS0. + USB_DIEPCTL0_D_EPDIS0 = 0x40000000 + // Position of D_EPENA0 field. + USB_DIEPCTL0_D_EPENA0_Pos = 0x1f + // Bit mask of D_EPENA0 field. + USB_DIEPCTL0_D_EPENA0_Msk = 0x80000000 + // Bit D_EPENA0. + USB_DIEPCTL0_D_EPENA0 = 0x80000000 + + // DIEPINT0 + // Position of D_XFERCOMPL0 field. + USB_DIEPINT0_D_XFERCOMPL0_Pos = 0x0 + // Bit mask of D_XFERCOMPL0 field. + USB_DIEPINT0_D_XFERCOMPL0_Msk = 0x1 + // Bit D_XFERCOMPL0. + USB_DIEPINT0_D_XFERCOMPL0 = 0x1 + // Position of D_EPDISBLD0 field. + USB_DIEPINT0_D_EPDISBLD0_Pos = 0x1 + // Bit mask of D_EPDISBLD0 field. + USB_DIEPINT0_D_EPDISBLD0_Msk = 0x2 + // Bit D_EPDISBLD0. + USB_DIEPINT0_D_EPDISBLD0 = 0x2 + // Position of D_AHBERR0 field. + USB_DIEPINT0_D_AHBERR0_Pos = 0x2 + // Bit mask of D_AHBERR0 field. + USB_DIEPINT0_D_AHBERR0_Msk = 0x4 + // Bit D_AHBERR0. + USB_DIEPINT0_D_AHBERR0 = 0x4 + // Position of D_TIMEOUT0 field. + USB_DIEPINT0_D_TIMEOUT0_Pos = 0x3 + // Bit mask of D_TIMEOUT0 field. + USB_DIEPINT0_D_TIMEOUT0_Msk = 0x8 + // Bit D_TIMEOUT0. + USB_DIEPINT0_D_TIMEOUT0 = 0x8 + // Position of D_INTKNTXFEMP0 field. + USB_DIEPINT0_D_INTKNTXFEMP0_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP0 field. + USB_DIEPINT0_D_INTKNTXFEMP0_Msk = 0x10 + // Bit D_INTKNTXFEMP0. + USB_DIEPINT0_D_INTKNTXFEMP0 = 0x10 + // Position of D_INTKNEPMIS0 field. + USB_DIEPINT0_D_INTKNEPMIS0_Pos = 0x5 + // Bit mask of D_INTKNEPMIS0 field. + USB_DIEPINT0_D_INTKNEPMIS0_Msk = 0x20 + // Bit D_INTKNEPMIS0. + USB_DIEPINT0_D_INTKNEPMIS0 = 0x20 + // Position of D_INEPNAKEFF0 field. + USB_DIEPINT0_D_INEPNAKEFF0_Pos = 0x6 + // Bit mask of D_INEPNAKEFF0 field. + USB_DIEPINT0_D_INEPNAKEFF0_Msk = 0x40 + // Bit D_INEPNAKEFF0. + USB_DIEPINT0_D_INEPNAKEFF0 = 0x40 + // Position of D_TXFEMP0 field. + USB_DIEPINT0_D_TXFEMP0_Pos = 0x7 + // Bit mask of D_TXFEMP0 field. + USB_DIEPINT0_D_TXFEMP0_Msk = 0x80 + // Bit D_TXFEMP0. + USB_DIEPINT0_D_TXFEMP0 = 0x80 + // Position of D_TXFIFOUNDRN0 field. + USB_DIEPINT0_D_TXFIFOUNDRN0_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN0 field. + USB_DIEPINT0_D_TXFIFOUNDRN0_Msk = 0x100 + // Bit D_TXFIFOUNDRN0. + USB_DIEPINT0_D_TXFIFOUNDRN0 = 0x100 + // Position of D_BNAINTR0 field. + USB_DIEPINT0_D_BNAINTR0_Pos = 0x9 + // Bit mask of D_BNAINTR0 field. + USB_DIEPINT0_D_BNAINTR0_Msk = 0x200 + // Bit D_BNAINTR0. + USB_DIEPINT0_D_BNAINTR0 = 0x200 + // Position of D_PKTDRPSTS0 field. + USB_DIEPINT0_D_PKTDRPSTS0_Pos = 0xb + // Bit mask of D_PKTDRPSTS0 field. + USB_DIEPINT0_D_PKTDRPSTS0_Msk = 0x800 + // Bit D_PKTDRPSTS0. + USB_DIEPINT0_D_PKTDRPSTS0 = 0x800 + // Position of D_BBLEERR0 field. + USB_DIEPINT0_D_BBLEERR0_Pos = 0xc + // Bit mask of D_BBLEERR0 field. + USB_DIEPINT0_D_BBLEERR0_Msk = 0x1000 + // Bit D_BBLEERR0. + USB_DIEPINT0_D_BBLEERR0 = 0x1000 + // Position of D_NAKINTRPT0 field. + USB_DIEPINT0_D_NAKINTRPT0_Pos = 0xd + // Bit mask of D_NAKINTRPT0 field. + USB_DIEPINT0_D_NAKINTRPT0_Msk = 0x2000 + // Bit D_NAKINTRPT0. + USB_DIEPINT0_D_NAKINTRPT0 = 0x2000 + // Position of D_NYETINTRPT0 field. + USB_DIEPINT0_D_NYETINTRPT0_Pos = 0xe + // Bit mask of D_NYETINTRPT0 field. + USB_DIEPINT0_D_NYETINTRPT0_Msk = 0x4000 + // Bit D_NYETINTRPT0. + USB_DIEPINT0_D_NYETINTRPT0 = 0x4000 + + // DIEPTSIZ0 + // Position of D_XFERSIZE0 field. + USB_DIEPTSIZ0_D_XFERSIZE0_Pos = 0x0 + // Bit mask of D_XFERSIZE0 field. + USB_DIEPTSIZ0_D_XFERSIZE0_Msk = 0x7f + // Position of D_PKTCNT0 field. + USB_DIEPTSIZ0_D_PKTCNT0_Pos = 0x13 + // Bit mask of D_PKTCNT0 field. + USB_DIEPTSIZ0_D_PKTCNT0_Msk = 0x180000 + + // DIEPDMA0 + // Position of D_DMAADDR0 field. + USB_DIEPDMA0_D_DMAADDR0_Pos = 0x0 + // Bit mask of D_DMAADDR0 field. + USB_DIEPDMA0_D_DMAADDR0_Msk = 0xffffffff + + // DTXFSTS0 + // Position of D_INEPTXFSPCAVAIL0 field. + USB_DTXFSTS0_D_INEPTXFSPCAVAIL0_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL0 field. + USB_DTXFSTS0_D_INEPTXFSPCAVAIL0_Msk = 0xffff + + // DIEPDMAB0 + // Position of D_DMABUFFERADDR0 field. + USB_DIEPDMAB0_D_DMABUFFERADDR0_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR0 field. + USB_DIEPDMAB0_D_DMABUFFERADDR0_Msk = 0xffffffff + + // DIEPCTL1 + // Position of D_MPS1 field. + USB_DIEPCTL1_D_MPS1_Pos = 0x0 + // Bit mask of D_MPS1 field. + USB_DIEPCTL1_D_MPS1_Msk = 0x3 + // Position of D_USBACTEP1 field. + USB_DIEPCTL1_D_USBACTEP1_Pos = 0xf + // Bit mask of D_USBACTEP1 field. + USB_DIEPCTL1_D_USBACTEP1_Msk = 0x8000 + // Bit D_USBACTEP1. + USB_DIEPCTL1_D_USBACTEP1 = 0x8000 + // Position of D_NAKSTS1 field. + USB_DIEPCTL1_D_NAKSTS1_Pos = 0x11 + // Bit mask of D_NAKSTS1 field. + USB_DIEPCTL1_D_NAKSTS1_Msk = 0x20000 + // Bit D_NAKSTS1. + USB_DIEPCTL1_D_NAKSTS1 = 0x20000 + // Position of D_EPTYPE1 field. + USB_DIEPCTL1_D_EPTYPE1_Pos = 0x12 + // Bit mask of D_EPTYPE1 field. + USB_DIEPCTL1_D_EPTYPE1_Msk = 0xc0000 + // Position of D_STALL1 field. + USB_DIEPCTL1_D_STALL1_Pos = 0x15 + // Bit mask of D_STALL1 field. + USB_DIEPCTL1_D_STALL1_Msk = 0x200000 + // Bit D_STALL1. + USB_DIEPCTL1_D_STALL1 = 0x200000 + // Position of D_TXFNUM1 field. + USB_DIEPCTL1_D_TXFNUM1_Pos = 0x16 + // Bit mask of D_TXFNUM1 field. + USB_DIEPCTL1_D_TXFNUM1_Msk = 0x3c00000 + // Position of D_CNAK1 field. + USB_DIEPCTL1_D_CNAK1_Pos = 0x1a + // Bit mask of D_CNAK1 field. + USB_DIEPCTL1_D_CNAK1_Msk = 0x4000000 + // Bit D_CNAK1. + USB_DIEPCTL1_D_CNAK1 = 0x4000000 + // Position of DI_SNAK1 field. + USB_DIEPCTL1_DI_SNAK1_Pos = 0x1b + // Bit mask of DI_SNAK1 field. + USB_DIEPCTL1_DI_SNAK1_Msk = 0x8000000 + // Bit DI_SNAK1. + USB_DIEPCTL1_DI_SNAK1 = 0x8000000 + // Position of DI_SETD0PID1 field. + USB_DIEPCTL1_DI_SETD0PID1_Pos = 0x1c + // Bit mask of DI_SETD0PID1 field. + USB_DIEPCTL1_DI_SETD0PID1_Msk = 0x10000000 + // Bit DI_SETD0PID1. + USB_DIEPCTL1_DI_SETD0PID1 = 0x10000000 + // Position of DI_SETD1PID1 field. + USB_DIEPCTL1_DI_SETD1PID1_Pos = 0x1d + // Bit mask of DI_SETD1PID1 field. + USB_DIEPCTL1_DI_SETD1PID1_Msk = 0x20000000 + // Bit DI_SETD1PID1. + USB_DIEPCTL1_DI_SETD1PID1 = 0x20000000 + // Position of D_EPDIS1 field. + USB_DIEPCTL1_D_EPDIS1_Pos = 0x1e + // Bit mask of D_EPDIS1 field. + USB_DIEPCTL1_D_EPDIS1_Msk = 0x40000000 + // Bit D_EPDIS1. + USB_DIEPCTL1_D_EPDIS1 = 0x40000000 + // Position of D_EPENA1 field. + USB_DIEPCTL1_D_EPENA1_Pos = 0x1f + // Bit mask of D_EPENA1 field. + USB_DIEPCTL1_D_EPENA1_Msk = 0x80000000 + // Bit D_EPENA1. + USB_DIEPCTL1_D_EPENA1 = 0x80000000 + + // DIEPINT1 + // Position of D_XFERCOMPL1 field. + USB_DIEPINT1_D_XFERCOMPL1_Pos = 0x0 + // Bit mask of D_XFERCOMPL1 field. + USB_DIEPINT1_D_XFERCOMPL1_Msk = 0x1 + // Bit D_XFERCOMPL1. + USB_DIEPINT1_D_XFERCOMPL1 = 0x1 + // Position of D_EPDISBLD1 field. + USB_DIEPINT1_D_EPDISBLD1_Pos = 0x1 + // Bit mask of D_EPDISBLD1 field. + USB_DIEPINT1_D_EPDISBLD1_Msk = 0x2 + // Bit D_EPDISBLD1. + USB_DIEPINT1_D_EPDISBLD1 = 0x2 + // Position of D_AHBERR1 field. + USB_DIEPINT1_D_AHBERR1_Pos = 0x2 + // Bit mask of D_AHBERR1 field. + USB_DIEPINT1_D_AHBERR1_Msk = 0x4 + // Bit D_AHBERR1. + USB_DIEPINT1_D_AHBERR1 = 0x4 + // Position of D_TIMEOUT1 field. + USB_DIEPINT1_D_TIMEOUT1_Pos = 0x3 + // Bit mask of D_TIMEOUT1 field. + USB_DIEPINT1_D_TIMEOUT1_Msk = 0x8 + // Bit D_TIMEOUT1. + USB_DIEPINT1_D_TIMEOUT1 = 0x8 + // Position of D_INTKNTXFEMP1 field. + USB_DIEPINT1_D_INTKNTXFEMP1_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP1 field. + USB_DIEPINT1_D_INTKNTXFEMP1_Msk = 0x10 + // Bit D_INTKNTXFEMP1. + USB_DIEPINT1_D_INTKNTXFEMP1 = 0x10 + // Position of D_INTKNEPMIS1 field. + USB_DIEPINT1_D_INTKNEPMIS1_Pos = 0x5 + // Bit mask of D_INTKNEPMIS1 field. + USB_DIEPINT1_D_INTKNEPMIS1_Msk = 0x20 + // Bit D_INTKNEPMIS1. + USB_DIEPINT1_D_INTKNEPMIS1 = 0x20 + // Position of D_INEPNAKEFF1 field. + USB_DIEPINT1_D_INEPNAKEFF1_Pos = 0x6 + // Bit mask of D_INEPNAKEFF1 field. + USB_DIEPINT1_D_INEPNAKEFF1_Msk = 0x40 + // Bit D_INEPNAKEFF1. + USB_DIEPINT1_D_INEPNAKEFF1 = 0x40 + // Position of D_TXFEMP1 field. + USB_DIEPINT1_D_TXFEMP1_Pos = 0x7 + // Bit mask of D_TXFEMP1 field. + USB_DIEPINT1_D_TXFEMP1_Msk = 0x80 + // Bit D_TXFEMP1. + USB_DIEPINT1_D_TXFEMP1 = 0x80 + // Position of D_TXFIFOUNDRN1 field. + USB_DIEPINT1_D_TXFIFOUNDRN1_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN1 field. + USB_DIEPINT1_D_TXFIFOUNDRN1_Msk = 0x100 + // Bit D_TXFIFOUNDRN1. + USB_DIEPINT1_D_TXFIFOUNDRN1 = 0x100 + // Position of D_BNAINTR1 field. + USB_DIEPINT1_D_BNAINTR1_Pos = 0x9 + // Bit mask of D_BNAINTR1 field. + USB_DIEPINT1_D_BNAINTR1_Msk = 0x200 + // Bit D_BNAINTR1. + USB_DIEPINT1_D_BNAINTR1 = 0x200 + // Position of D_PKTDRPSTS1 field. + USB_DIEPINT1_D_PKTDRPSTS1_Pos = 0xb + // Bit mask of D_PKTDRPSTS1 field. + USB_DIEPINT1_D_PKTDRPSTS1_Msk = 0x800 + // Bit D_PKTDRPSTS1. + USB_DIEPINT1_D_PKTDRPSTS1 = 0x800 + // Position of D_BBLEERR1 field. + USB_DIEPINT1_D_BBLEERR1_Pos = 0xc + // Bit mask of D_BBLEERR1 field. + USB_DIEPINT1_D_BBLEERR1_Msk = 0x1000 + // Bit D_BBLEERR1. + USB_DIEPINT1_D_BBLEERR1 = 0x1000 + // Position of D_NAKINTRPT1 field. + USB_DIEPINT1_D_NAKINTRPT1_Pos = 0xd + // Bit mask of D_NAKINTRPT1 field. + USB_DIEPINT1_D_NAKINTRPT1_Msk = 0x2000 + // Bit D_NAKINTRPT1. + USB_DIEPINT1_D_NAKINTRPT1 = 0x2000 + // Position of D_NYETINTRPT1 field. + USB_DIEPINT1_D_NYETINTRPT1_Pos = 0xe + // Bit mask of D_NYETINTRPT1 field. + USB_DIEPINT1_D_NYETINTRPT1_Msk = 0x4000 + // Bit D_NYETINTRPT1. + USB_DIEPINT1_D_NYETINTRPT1 = 0x4000 + + // DIEPTSIZ1 + // Position of D_XFERSIZE1 field. + USB_DIEPTSIZ1_D_XFERSIZE1_Pos = 0x0 + // Bit mask of D_XFERSIZE1 field. + USB_DIEPTSIZ1_D_XFERSIZE1_Msk = 0x7f + // Position of D_PKTCNT1 field. + USB_DIEPTSIZ1_D_PKTCNT1_Pos = 0x13 + // Bit mask of D_PKTCNT1 field. + USB_DIEPTSIZ1_D_PKTCNT1_Msk = 0x180000 + + // DIEPDMA1 + // Position of D_DMAADDR1 field. + USB_DIEPDMA1_D_DMAADDR1_Pos = 0x0 + // Bit mask of D_DMAADDR1 field. + USB_DIEPDMA1_D_DMAADDR1_Msk = 0xffffffff + + // DTXFSTS1 + // Position of D_INEPTXFSPCAVAIL1 field. + USB_DTXFSTS1_D_INEPTXFSPCAVAIL1_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL1 field. + USB_DTXFSTS1_D_INEPTXFSPCAVAIL1_Msk = 0xffff + + // DIEPDMAB1 + // Position of D_DMABUFFERADDR1 field. + USB_DIEPDMAB1_D_DMABUFFERADDR1_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR1 field. + USB_DIEPDMAB1_D_DMABUFFERADDR1_Msk = 0xffffffff + + // DIEPCTL2 + // Position of D_MPS2 field. + USB_DIEPCTL2_D_MPS2_Pos = 0x0 + // Bit mask of D_MPS2 field. + USB_DIEPCTL2_D_MPS2_Msk = 0x3 + // Position of D_USBACTEP2 field. + USB_DIEPCTL2_D_USBACTEP2_Pos = 0xf + // Bit mask of D_USBACTEP2 field. + USB_DIEPCTL2_D_USBACTEP2_Msk = 0x8000 + // Bit D_USBACTEP2. + USB_DIEPCTL2_D_USBACTEP2 = 0x8000 + // Position of D_NAKSTS2 field. + USB_DIEPCTL2_D_NAKSTS2_Pos = 0x11 + // Bit mask of D_NAKSTS2 field. + USB_DIEPCTL2_D_NAKSTS2_Msk = 0x20000 + // Bit D_NAKSTS2. + USB_DIEPCTL2_D_NAKSTS2 = 0x20000 + // Position of D_EPTYPE2 field. + USB_DIEPCTL2_D_EPTYPE2_Pos = 0x12 + // Bit mask of D_EPTYPE2 field. + USB_DIEPCTL2_D_EPTYPE2_Msk = 0xc0000 + // Position of D_STALL2 field. + USB_DIEPCTL2_D_STALL2_Pos = 0x15 + // Bit mask of D_STALL2 field. + USB_DIEPCTL2_D_STALL2_Msk = 0x200000 + // Bit D_STALL2. + USB_DIEPCTL2_D_STALL2 = 0x200000 + // Position of D_TXFNUM2 field. + USB_DIEPCTL2_D_TXFNUM2_Pos = 0x16 + // Bit mask of D_TXFNUM2 field. + USB_DIEPCTL2_D_TXFNUM2_Msk = 0x3c00000 + // Position of D_CNAK2 field. + USB_DIEPCTL2_D_CNAK2_Pos = 0x1a + // Bit mask of D_CNAK2 field. + USB_DIEPCTL2_D_CNAK2_Msk = 0x4000000 + // Bit D_CNAK2. + USB_DIEPCTL2_D_CNAK2 = 0x4000000 + // Position of DI_SNAK2 field. + USB_DIEPCTL2_DI_SNAK2_Pos = 0x1b + // Bit mask of DI_SNAK2 field. + USB_DIEPCTL2_DI_SNAK2_Msk = 0x8000000 + // Bit DI_SNAK2. + USB_DIEPCTL2_DI_SNAK2 = 0x8000000 + // Position of DI_SETD0PID2 field. + USB_DIEPCTL2_DI_SETD0PID2_Pos = 0x1c + // Bit mask of DI_SETD0PID2 field. + USB_DIEPCTL2_DI_SETD0PID2_Msk = 0x10000000 + // Bit DI_SETD0PID2. + USB_DIEPCTL2_DI_SETD0PID2 = 0x10000000 + // Position of DI_SETD1PID2 field. + USB_DIEPCTL2_DI_SETD1PID2_Pos = 0x1d + // Bit mask of DI_SETD1PID2 field. + USB_DIEPCTL2_DI_SETD1PID2_Msk = 0x20000000 + // Bit DI_SETD1PID2. + USB_DIEPCTL2_DI_SETD1PID2 = 0x20000000 + // Position of D_EPDIS2 field. + USB_DIEPCTL2_D_EPDIS2_Pos = 0x1e + // Bit mask of D_EPDIS2 field. + USB_DIEPCTL2_D_EPDIS2_Msk = 0x40000000 + // Bit D_EPDIS2. + USB_DIEPCTL2_D_EPDIS2 = 0x40000000 + // Position of D_EPENA2 field. + USB_DIEPCTL2_D_EPENA2_Pos = 0x1f + // Bit mask of D_EPENA2 field. + USB_DIEPCTL2_D_EPENA2_Msk = 0x80000000 + // Bit D_EPENA2. + USB_DIEPCTL2_D_EPENA2 = 0x80000000 + + // DIEPINT2 + // Position of D_XFERCOMPL2 field. + USB_DIEPINT2_D_XFERCOMPL2_Pos = 0x0 + // Bit mask of D_XFERCOMPL2 field. + USB_DIEPINT2_D_XFERCOMPL2_Msk = 0x1 + // Bit D_XFERCOMPL2. + USB_DIEPINT2_D_XFERCOMPL2 = 0x1 + // Position of D_EPDISBLD2 field. + USB_DIEPINT2_D_EPDISBLD2_Pos = 0x1 + // Bit mask of D_EPDISBLD2 field. + USB_DIEPINT2_D_EPDISBLD2_Msk = 0x2 + // Bit D_EPDISBLD2. + USB_DIEPINT2_D_EPDISBLD2 = 0x2 + // Position of D_AHBERR2 field. + USB_DIEPINT2_D_AHBERR2_Pos = 0x2 + // Bit mask of D_AHBERR2 field. + USB_DIEPINT2_D_AHBERR2_Msk = 0x4 + // Bit D_AHBERR2. + USB_DIEPINT2_D_AHBERR2 = 0x4 + // Position of D_TIMEOUT2 field. + USB_DIEPINT2_D_TIMEOUT2_Pos = 0x3 + // Bit mask of D_TIMEOUT2 field. + USB_DIEPINT2_D_TIMEOUT2_Msk = 0x8 + // Bit D_TIMEOUT2. + USB_DIEPINT2_D_TIMEOUT2 = 0x8 + // Position of D_INTKNTXFEMP2 field. + USB_DIEPINT2_D_INTKNTXFEMP2_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP2 field. + USB_DIEPINT2_D_INTKNTXFEMP2_Msk = 0x10 + // Bit D_INTKNTXFEMP2. + USB_DIEPINT2_D_INTKNTXFEMP2 = 0x10 + // Position of D_INTKNEPMIS2 field. + USB_DIEPINT2_D_INTKNEPMIS2_Pos = 0x5 + // Bit mask of D_INTKNEPMIS2 field. + USB_DIEPINT2_D_INTKNEPMIS2_Msk = 0x20 + // Bit D_INTKNEPMIS2. + USB_DIEPINT2_D_INTKNEPMIS2 = 0x20 + // Position of D_INEPNAKEFF2 field. + USB_DIEPINT2_D_INEPNAKEFF2_Pos = 0x6 + // Bit mask of D_INEPNAKEFF2 field. + USB_DIEPINT2_D_INEPNAKEFF2_Msk = 0x40 + // Bit D_INEPNAKEFF2. + USB_DIEPINT2_D_INEPNAKEFF2 = 0x40 + // Position of D_TXFEMP2 field. + USB_DIEPINT2_D_TXFEMP2_Pos = 0x7 + // Bit mask of D_TXFEMP2 field. + USB_DIEPINT2_D_TXFEMP2_Msk = 0x80 + // Bit D_TXFEMP2. + USB_DIEPINT2_D_TXFEMP2 = 0x80 + // Position of D_TXFIFOUNDRN2 field. + USB_DIEPINT2_D_TXFIFOUNDRN2_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN2 field. + USB_DIEPINT2_D_TXFIFOUNDRN2_Msk = 0x100 + // Bit D_TXFIFOUNDRN2. + USB_DIEPINT2_D_TXFIFOUNDRN2 = 0x100 + // Position of D_BNAINTR2 field. + USB_DIEPINT2_D_BNAINTR2_Pos = 0x9 + // Bit mask of D_BNAINTR2 field. + USB_DIEPINT2_D_BNAINTR2_Msk = 0x200 + // Bit D_BNAINTR2. + USB_DIEPINT2_D_BNAINTR2 = 0x200 + // Position of D_PKTDRPSTS2 field. + USB_DIEPINT2_D_PKTDRPSTS2_Pos = 0xb + // Bit mask of D_PKTDRPSTS2 field. + USB_DIEPINT2_D_PKTDRPSTS2_Msk = 0x800 + // Bit D_PKTDRPSTS2. + USB_DIEPINT2_D_PKTDRPSTS2 = 0x800 + // Position of D_BBLEERR2 field. + USB_DIEPINT2_D_BBLEERR2_Pos = 0xc + // Bit mask of D_BBLEERR2 field. + USB_DIEPINT2_D_BBLEERR2_Msk = 0x1000 + // Bit D_BBLEERR2. + USB_DIEPINT2_D_BBLEERR2 = 0x1000 + // Position of D_NAKINTRPT2 field. + USB_DIEPINT2_D_NAKINTRPT2_Pos = 0xd + // Bit mask of D_NAKINTRPT2 field. + USB_DIEPINT2_D_NAKINTRPT2_Msk = 0x2000 + // Bit D_NAKINTRPT2. + USB_DIEPINT2_D_NAKINTRPT2 = 0x2000 + // Position of D_NYETINTRPT2 field. + USB_DIEPINT2_D_NYETINTRPT2_Pos = 0xe + // Bit mask of D_NYETINTRPT2 field. + USB_DIEPINT2_D_NYETINTRPT2_Msk = 0x4000 + // Bit D_NYETINTRPT2. + USB_DIEPINT2_D_NYETINTRPT2 = 0x4000 + + // DIEPTSIZ2 + // Position of D_XFERSIZE2 field. + USB_DIEPTSIZ2_D_XFERSIZE2_Pos = 0x0 + // Bit mask of D_XFERSIZE2 field. + USB_DIEPTSIZ2_D_XFERSIZE2_Msk = 0x7f + // Position of D_PKTCNT2 field. + USB_DIEPTSIZ2_D_PKTCNT2_Pos = 0x13 + // Bit mask of D_PKTCNT2 field. + USB_DIEPTSIZ2_D_PKTCNT2_Msk = 0x180000 + + // DIEPDMA2 + // Position of D_DMAADDR2 field. + USB_DIEPDMA2_D_DMAADDR2_Pos = 0x0 + // Bit mask of D_DMAADDR2 field. + USB_DIEPDMA2_D_DMAADDR2_Msk = 0xffffffff + + // DTXFSTS2 + // Position of D_INEPTXFSPCAVAIL2 field. + USB_DTXFSTS2_D_INEPTXFSPCAVAIL2_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL2 field. + USB_DTXFSTS2_D_INEPTXFSPCAVAIL2_Msk = 0xffff + + // DIEPDMAB2 + // Position of D_DMABUFFERADDR2 field. + USB_DIEPDMAB2_D_DMABUFFERADDR2_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR2 field. + USB_DIEPDMAB2_D_DMABUFFERADDR2_Msk = 0xffffffff + + // DIEPCTL3 + // Position of DI_MPS3 field. + USB_DIEPCTL3_DI_MPS3_Pos = 0x0 + // Bit mask of DI_MPS3 field. + USB_DIEPCTL3_DI_MPS3_Msk = 0x3 + // Position of DI_USBACTEP3 field. + USB_DIEPCTL3_DI_USBACTEP3_Pos = 0xf + // Bit mask of DI_USBACTEP3 field. + USB_DIEPCTL3_DI_USBACTEP3_Msk = 0x8000 + // Bit DI_USBACTEP3. + USB_DIEPCTL3_DI_USBACTEP3 = 0x8000 + // Position of DI_NAKSTS3 field. + USB_DIEPCTL3_DI_NAKSTS3_Pos = 0x11 + // Bit mask of DI_NAKSTS3 field. + USB_DIEPCTL3_DI_NAKSTS3_Msk = 0x20000 + // Bit DI_NAKSTS3. + USB_DIEPCTL3_DI_NAKSTS3 = 0x20000 + // Position of DI_EPTYPE3 field. + USB_DIEPCTL3_DI_EPTYPE3_Pos = 0x12 + // Bit mask of DI_EPTYPE3 field. + USB_DIEPCTL3_DI_EPTYPE3_Msk = 0xc0000 + // Position of DI_STALL3 field. + USB_DIEPCTL3_DI_STALL3_Pos = 0x15 + // Bit mask of DI_STALL3 field. + USB_DIEPCTL3_DI_STALL3_Msk = 0x200000 + // Bit DI_STALL3. + USB_DIEPCTL3_DI_STALL3 = 0x200000 + // Position of DI_TXFNUM3 field. + USB_DIEPCTL3_DI_TXFNUM3_Pos = 0x16 + // Bit mask of DI_TXFNUM3 field. + USB_DIEPCTL3_DI_TXFNUM3_Msk = 0x3c00000 + // Position of DI_CNAK3 field. + USB_DIEPCTL3_DI_CNAK3_Pos = 0x1a + // Bit mask of DI_CNAK3 field. + USB_DIEPCTL3_DI_CNAK3_Msk = 0x4000000 + // Bit DI_CNAK3. + USB_DIEPCTL3_DI_CNAK3 = 0x4000000 + // Position of DI_SNAK3 field. + USB_DIEPCTL3_DI_SNAK3_Pos = 0x1b + // Bit mask of DI_SNAK3 field. + USB_DIEPCTL3_DI_SNAK3_Msk = 0x8000000 + // Bit DI_SNAK3. + USB_DIEPCTL3_DI_SNAK3 = 0x8000000 + // Position of DI_SETD0PID3 field. + USB_DIEPCTL3_DI_SETD0PID3_Pos = 0x1c + // Bit mask of DI_SETD0PID3 field. + USB_DIEPCTL3_DI_SETD0PID3_Msk = 0x10000000 + // Bit DI_SETD0PID3. + USB_DIEPCTL3_DI_SETD0PID3 = 0x10000000 + // Position of DI_SETD1PID3 field. + USB_DIEPCTL3_DI_SETD1PID3_Pos = 0x1d + // Bit mask of DI_SETD1PID3 field. + USB_DIEPCTL3_DI_SETD1PID3_Msk = 0x20000000 + // Bit DI_SETD1PID3. + USB_DIEPCTL3_DI_SETD1PID3 = 0x20000000 + // Position of DI_EPDIS3 field. + USB_DIEPCTL3_DI_EPDIS3_Pos = 0x1e + // Bit mask of DI_EPDIS3 field. + USB_DIEPCTL3_DI_EPDIS3_Msk = 0x40000000 + // Bit DI_EPDIS3. + USB_DIEPCTL3_DI_EPDIS3 = 0x40000000 + // Position of DI_EPENA3 field. + USB_DIEPCTL3_DI_EPENA3_Pos = 0x1f + // Bit mask of DI_EPENA3 field. + USB_DIEPCTL3_DI_EPENA3_Msk = 0x80000000 + // Bit DI_EPENA3. + USB_DIEPCTL3_DI_EPENA3 = 0x80000000 + + // DIEPINT3 + // Position of D_XFERCOMPL3 field. + USB_DIEPINT3_D_XFERCOMPL3_Pos = 0x0 + // Bit mask of D_XFERCOMPL3 field. + USB_DIEPINT3_D_XFERCOMPL3_Msk = 0x1 + // Bit D_XFERCOMPL3. + USB_DIEPINT3_D_XFERCOMPL3 = 0x1 + // Position of D_EPDISBLD3 field. + USB_DIEPINT3_D_EPDISBLD3_Pos = 0x1 + // Bit mask of D_EPDISBLD3 field. + USB_DIEPINT3_D_EPDISBLD3_Msk = 0x2 + // Bit D_EPDISBLD3. + USB_DIEPINT3_D_EPDISBLD3 = 0x2 + // Position of D_AHBERR3 field. + USB_DIEPINT3_D_AHBERR3_Pos = 0x2 + // Bit mask of D_AHBERR3 field. + USB_DIEPINT3_D_AHBERR3_Msk = 0x4 + // Bit D_AHBERR3. + USB_DIEPINT3_D_AHBERR3 = 0x4 + // Position of D_TIMEOUT3 field. + USB_DIEPINT3_D_TIMEOUT3_Pos = 0x3 + // Bit mask of D_TIMEOUT3 field. + USB_DIEPINT3_D_TIMEOUT3_Msk = 0x8 + // Bit D_TIMEOUT3. + USB_DIEPINT3_D_TIMEOUT3 = 0x8 + // Position of D_INTKNTXFEMP3 field. + USB_DIEPINT3_D_INTKNTXFEMP3_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP3 field. + USB_DIEPINT3_D_INTKNTXFEMP3_Msk = 0x10 + // Bit D_INTKNTXFEMP3. + USB_DIEPINT3_D_INTKNTXFEMP3 = 0x10 + // Position of D_INTKNEPMIS3 field. + USB_DIEPINT3_D_INTKNEPMIS3_Pos = 0x5 + // Bit mask of D_INTKNEPMIS3 field. + USB_DIEPINT3_D_INTKNEPMIS3_Msk = 0x20 + // Bit D_INTKNEPMIS3. + USB_DIEPINT3_D_INTKNEPMIS3 = 0x20 + // Position of D_INEPNAKEFF3 field. + USB_DIEPINT3_D_INEPNAKEFF3_Pos = 0x6 + // Bit mask of D_INEPNAKEFF3 field. + USB_DIEPINT3_D_INEPNAKEFF3_Msk = 0x40 + // Bit D_INEPNAKEFF3. + USB_DIEPINT3_D_INEPNAKEFF3 = 0x40 + // Position of D_TXFEMP3 field. + USB_DIEPINT3_D_TXFEMP3_Pos = 0x7 + // Bit mask of D_TXFEMP3 field. + USB_DIEPINT3_D_TXFEMP3_Msk = 0x80 + // Bit D_TXFEMP3. + USB_DIEPINT3_D_TXFEMP3 = 0x80 + // Position of D_TXFIFOUNDRN3 field. + USB_DIEPINT3_D_TXFIFOUNDRN3_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN3 field. + USB_DIEPINT3_D_TXFIFOUNDRN3_Msk = 0x100 + // Bit D_TXFIFOUNDRN3. + USB_DIEPINT3_D_TXFIFOUNDRN3 = 0x100 + // Position of D_BNAINTR3 field. + USB_DIEPINT3_D_BNAINTR3_Pos = 0x9 + // Bit mask of D_BNAINTR3 field. + USB_DIEPINT3_D_BNAINTR3_Msk = 0x200 + // Bit D_BNAINTR3. + USB_DIEPINT3_D_BNAINTR3 = 0x200 + // Position of D_PKTDRPSTS3 field. + USB_DIEPINT3_D_PKTDRPSTS3_Pos = 0xb + // Bit mask of D_PKTDRPSTS3 field. + USB_DIEPINT3_D_PKTDRPSTS3_Msk = 0x800 + // Bit D_PKTDRPSTS3. + USB_DIEPINT3_D_PKTDRPSTS3 = 0x800 + // Position of D_BBLEERR3 field. + USB_DIEPINT3_D_BBLEERR3_Pos = 0xc + // Bit mask of D_BBLEERR3 field. + USB_DIEPINT3_D_BBLEERR3_Msk = 0x1000 + // Bit D_BBLEERR3. + USB_DIEPINT3_D_BBLEERR3 = 0x1000 + // Position of D_NAKINTRPT3 field. + USB_DIEPINT3_D_NAKINTRPT3_Pos = 0xd + // Bit mask of D_NAKINTRPT3 field. + USB_DIEPINT3_D_NAKINTRPT3_Msk = 0x2000 + // Bit D_NAKINTRPT3. + USB_DIEPINT3_D_NAKINTRPT3 = 0x2000 + // Position of D_NYETINTRPT3 field. + USB_DIEPINT3_D_NYETINTRPT3_Pos = 0xe + // Bit mask of D_NYETINTRPT3 field. + USB_DIEPINT3_D_NYETINTRPT3_Msk = 0x4000 + // Bit D_NYETINTRPT3. + USB_DIEPINT3_D_NYETINTRPT3 = 0x4000 + + // DIEPTSIZ3 + // Position of D_XFERSIZE3 field. + USB_DIEPTSIZ3_D_XFERSIZE3_Pos = 0x0 + // Bit mask of D_XFERSIZE3 field. + USB_DIEPTSIZ3_D_XFERSIZE3_Msk = 0x7f + // Position of D_PKTCNT3 field. + USB_DIEPTSIZ3_D_PKTCNT3_Pos = 0x13 + // Bit mask of D_PKTCNT3 field. + USB_DIEPTSIZ3_D_PKTCNT3_Msk = 0x180000 + + // DIEPDMA3 + // Position of D_DMAADDR3 field. + USB_DIEPDMA3_D_DMAADDR3_Pos = 0x0 + // Bit mask of D_DMAADDR3 field. + USB_DIEPDMA3_D_DMAADDR3_Msk = 0xffffffff + + // DTXFSTS3 + // Position of D_INEPTXFSPCAVAIL3 field. + USB_DTXFSTS3_D_INEPTXFSPCAVAIL3_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL3 field. + USB_DTXFSTS3_D_INEPTXFSPCAVAIL3_Msk = 0xffff + + // DIEPDMAB3 + // Position of D_DMABUFFERADDR3 field. + USB_DIEPDMAB3_D_DMABUFFERADDR3_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR3 field. + USB_DIEPDMAB3_D_DMABUFFERADDR3_Msk = 0xffffffff + + // DIEPCTL4 + // Position of D_MPS4 field. + USB_DIEPCTL4_D_MPS4_Pos = 0x0 + // Bit mask of D_MPS4 field. + USB_DIEPCTL4_D_MPS4_Msk = 0x3 + // Position of D_USBACTEP4 field. + USB_DIEPCTL4_D_USBACTEP4_Pos = 0xf + // Bit mask of D_USBACTEP4 field. + USB_DIEPCTL4_D_USBACTEP4_Msk = 0x8000 + // Bit D_USBACTEP4. + USB_DIEPCTL4_D_USBACTEP4 = 0x8000 + // Position of D_NAKSTS4 field. + USB_DIEPCTL4_D_NAKSTS4_Pos = 0x11 + // Bit mask of D_NAKSTS4 field. + USB_DIEPCTL4_D_NAKSTS4_Msk = 0x20000 + // Bit D_NAKSTS4. + USB_DIEPCTL4_D_NAKSTS4 = 0x20000 + // Position of D_EPTYPE4 field. + USB_DIEPCTL4_D_EPTYPE4_Pos = 0x12 + // Bit mask of D_EPTYPE4 field. + USB_DIEPCTL4_D_EPTYPE4_Msk = 0xc0000 + // Position of D_STALL4 field. + USB_DIEPCTL4_D_STALL4_Pos = 0x15 + // Bit mask of D_STALL4 field. + USB_DIEPCTL4_D_STALL4_Msk = 0x200000 + // Bit D_STALL4. + USB_DIEPCTL4_D_STALL4 = 0x200000 + // Position of D_TXFNUM4 field. + USB_DIEPCTL4_D_TXFNUM4_Pos = 0x16 + // Bit mask of D_TXFNUM4 field. + USB_DIEPCTL4_D_TXFNUM4_Msk = 0x3c00000 + // Position of D_CNAK4 field. + USB_DIEPCTL4_D_CNAK4_Pos = 0x1a + // Bit mask of D_CNAK4 field. + USB_DIEPCTL4_D_CNAK4_Msk = 0x4000000 + // Bit D_CNAK4. + USB_DIEPCTL4_D_CNAK4 = 0x4000000 + // Position of DI_SNAK4 field. + USB_DIEPCTL4_DI_SNAK4_Pos = 0x1b + // Bit mask of DI_SNAK4 field. + USB_DIEPCTL4_DI_SNAK4_Msk = 0x8000000 + // Bit DI_SNAK4. + USB_DIEPCTL4_DI_SNAK4 = 0x8000000 + // Position of DI_SETD0PID4 field. + USB_DIEPCTL4_DI_SETD0PID4_Pos = 0x1c + // Bit mask of DI_SETD0PID4 field. + USB_DIEPCTL4_DI_SETD0PID4_Msk = 0x10000000 + // Bit DI_SETD0PID4. + USB_DIEPCTL4_DI_SETD0PID4 = 0x10000000 + // Position of DI_SETD1PID4 field. + USB_DIEPCTL4_DI_SETD1PID4_Pos = 0x1d + // Bit mask of DI_SETD1PID4 field. + USB_DIEPCTL4_DI_SETD1PID4_Msk = 0x20000000 + // Bit DI_SETD1PID4. + USB_DIEPCTL4_DI_SETD1PID4 = 0x20000000 + // Position of D_EPDIS4 field. + USB_DIEPCTL4_D_EPDIS4_Pos = 0x1e + // Bit mask of D_EPDIS4 field. + USB_DIEPCTL4_D_EPDIS4_Msk = 0x40000000 + // Bit D_EPDIS4. + USB_DIEPCTL4_D_EPDIS4 = 0x40000000 + // Position of D_EPENA4 field. + USB_DIEPCTL4_D_EPENA4_Pos = 0x1f + // Bit mask of D_EPENA4 field. + USB_DIEPCTL4_D_EPENA4_Msk = 0x80000000 + // Bit D_EPENA4. + USB_DIEPCTL4_D_EPENA4 = 0x80000000 + + // DIEPINT4 + // Position of D_XFERCOMPL4 field. + USB_DIEPINT4_D_XFERCOMPL4_Pos = 0x0 + // Bit mask of D_XFERCOMPL4 field. + USB_DIEPINT4_D_XFERCOMPL4_Msk = 0x1 + // Bit D_XFERCOMPL4. + USB_DIEPINT4_D_XFERCOMPL4 = 0x1 + // Position of D_EPDISBLD4 field. + USB_DIEPINT4_D_EPDISBLD4_Pos = 0x1 + // Bit mask of D_EPDISBLD4 field. + USB_DIEPINT4_D_EPDISBLD4_Msk = 0x2 + // Bit D_EPDISBLD4. + USB_DIEPINT4_D_EPDISBLD4 = 0x2 + // Position of D_AHBERR4 field. + USB_DIEPINT4_D_AHBERR4_Pos = 0x2 + // Bit mask of D_AHBERR4 field. + USB_DIEPINT4_D_AHBERR4_Msk = 0x4 + // Bit D_AHBERR4. + USB_DIEPINT4_D_AHBERR4 = 0x4 + // Position of D_TIMEOUT4 field. + USB_DIEPINT4_D_TIMEOUT4_Pos = 0x3 + // Bit mask of D_TIMEOUT4 field. + USB_DIEPINT4_D_TIMEOUT4_Msk = 0x8 + // Bit D_TIMEOUT4. + USB_DIEPINT4_D_TIMEOUT4 = 0x8 + // Position of D_INTKNTXFEMP4 field. + USB_DIEPINT4_D_INTKNTXFEMP4_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP4 field. + USB_DIEPINT4_D_INTKNTXFEMP4_Msk = 0x10 + // Bit D_INTKNTXFEMP4. + USB_DIEPINT4_D_INTKNTXFEMP4 = 0x10 + // Position of D_INTKNEPMIS4 field. + USB_DIEPINT4_D_INTKNEPMIS4_Pos = 0x5 + // Bit mask of D_INTKNEPMIS4 field. + USB_DIEPINT4_D_INTKNEPMIS4_Msk = 0x20 + // Bit D_INTKNEPMIS4. + USB_DIEPINT4_D_INTKNEPMIS4 = 0x20 + // Position of D_INEPNAKEFF4 field. + USB_DIEPINT4_D_INEPNAKEFF4_Pos = 0x6 + // Bit mask of D_INEPNAKEFF4 field. + USB_DIEPINT4_D_INEPNAKEFF4_Msk = 0x40 + // Bit D_INEPNAKEFF4. + USB_DIEPINT4_D_INEPNAKEFF4 = 0x40 + // Position of D_TXFEMP4 field. + USB_DIEPINT4_D_TXFEMP4_Pos = 0x7 + // Bit mask of D_TXFEMP4 field. + USB_DIEPINT4_D_TXFEMP4_Msk = 0x80 + // Bit D_TXFEMP4. + USB_DIEPINT4_D_TXFEMP4 = 0x80 + // Position of D_TXFIFOUNDRN4 field. + USB_DIEPINT4_D_TXFIFOUNDRN4_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN4 field. + USB_DIEPINT4_D_TXFIFOUNDRN4_Msk = 0x100 + // Bit D_TXFIFOUNDRN4. + USB_DIEPINT4_D_TXFIFOUNDRN4 = 0x100 + // Position of D_BNAINTR4 field. + USB_DIEPINT4_D_BNAINTR4_Pos = 0x9 + // Bit mask of D_BNAINTR4 field. + USB_DIEPINT4_D_BNAINTR4_Msk = 0x200 + // Bit D_BNAINTR4. + USB_DIEPINT4_D_BNAINTR4 = 0x200 + // Position of D_PKTDRPSTS4 field. + USB_DIEPINT4_D_PKTDRPSTS4_Pos = 0xb + // Bit mask of D_PKTDRPSTS4 field. + USB_DIEPINT4_D_PKTDRPSTS4_Msk = 0x800 + // Bit D_PKTDRPSTS4. + USB_DIEPINT4_D_PKTDRPSTS4 = 0x800 + // Position of D_BBLEERR4 field. + USB_DIEPINT4_D_BBLEERR4_Pos = 0xc + // Bit mask of D_BBLEERR4 field. + USB_DIEPINT4_D_BBLEERR4_Msk = 0x1000 + // Bit D_BBLEERR4. + USB_DIEPINT4_D_BBLEERR4 = 0x1000 + // Position of D_NAKINTRPT4 field. + USB_DIEPINT4_D_NAKINTRPT4_Pos = 0xd + // Bit mask of D_NAKINTRPT4 field. + USB_DIEPINT4_D_NAKINTRPT4_Msk = 0x2000 + // Bit D_NAKINTRPT4. + USB_DIEPINT4_D_NAKINTRPT4 = 0x2000 + // Position of D_NYETINTRPT4 field. + USB_DIEPINT4_D_NYETINTRPT4_Pos = 0xe + // Bit mask of D_NYETINTRPT4 field. + USB_DIEPINT4_D_NYETINTRPT4_Msk = 0x4000 + // Bit D_NYETINTRPT4. + USB_DIEPINT4_D_NYETINTRPT4 = 0x4000 + + // DIEPTSIZ4 + // Position of D_XFERSIZE4 field. + USB_DIEPTSIZ4_D_XFERSIZE4_Pos = 0x0 + // Bit mask of D_XFERSIZE4 field. + USB_DIEPTSIZ4_D_XFERSIZE4_Msk = 0x7f + // Position of D_PKTCNT4 field. + USB_DIEPTSIZ4_D_PKTCNT4_Pos = 0x13 + // Bit mask of D_PKTCNT4 field. + USB_DIEPTSIZ4_D_PKTCNT4_Msk = 0x180000 + + // DIEPDMA4 + // Position of D_DMAADDR4 field. + USB_DIEPDMA4_D_DMAADDR4_Pos = 0x0 + // Bit mask of D_DMAADDR4 field. + USB_DIEPDMA4_D_DMAADDR4_Msk = 0xffffffff + + // DTXFSTS4 + // Position of D_INEPTXFSPCAVAIL4 field. + USB_DTXFSTS4_D_INEPTXFSPCAVAIL4_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL4 field. + USB_DTXFSTS4_D_INEPTXFSPCAVAIL4_Msk = 0xffff + + // DIEPDMAB4 + // Position of D_DMABUFFERADDR4 field. + USB_DIEPDMAB4_D_DMABUFFERADDR4_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR4 field. + USB_DIEPDMAB4_D_DMABUFFERADDR4_Msk = 0xffffffff + + // DIEPCTL5 + // Position of DI_MPS5 field. + USB_DIEPCTL5_DI_MPS5_Pos = 0x0 + // Bit mask of DI_MPS5 field. + USB_DIEPCTL5_DI_MPS5_Msk = 0x3 + // Position of DI_USBACTEP5 field. + USB_DIEPCTL5_DI_USBACTEP5_Pos = 0xf + // Bit mask of DI_USBACTEP5 field. + USB_DIEPCTL5_DI_USBACTEP5_Msk = 0x8000 + // Bit DI_USBACTEP5. + USB_DIEPCTL5_DI_USBACTEP5 = 0x8000 + // Position of DI_NAKSTS5 field. + USB_DIEPCTL5_DI_NAKSTS5_Pos = 0x11 + // Bit mask of DI_NAKSTS5 field. + USB_DIEPCTL5_DI_NAKSTS5_Msk = 0x20000 + // Bit DI_NAKSTS5. + USB_DIEPCTL5_DI_NAKSTS5 = 0x20000 + // Position of DI_EPTYPE5 field. + USB_DIEPCTL5_DI_EPTYPE5_Pos = 0x12 + // Bit mask of DI_EPTYPE5 field. + USB_DIEPCTL5_DI_EPTYPE5_Msk = 0xc0000 + // Position of DI_STALL5 field. + USB_DIEPCTL5_DI_STALL5_Pos = 0x15 + // Bit mask of DI_STALL5 field. + USB_DIEPCTL5_DI_STALL5_Msk = 0x200000 + // Bit DI_STALL5. + USB_DIEPCTL5_DI_STALL5 = 0x200000 + // Position of DI_TXFNUM5 field. + USB_DIEPCTL5_DI_TXFNUM5_Pos = 0x16 + // Bit mask of DI_TXFNUM5 field. + USB_DIEPCTL5_DI_TXFNUM5_Msk = 0x3c00000 + // Position of DI_CNAK5 field. + USB_DIEPCTL5_DI_CNAK5_Pos = 0x1a + // Bit mask of DI_CNAK5 field. + USB_DIEPCTL5_DI_CNAK5_Msk = 0x4000000 + // Bit DI_CNAK5. + USB_DIEPCTL5_DI_CNAK5 = 0x4000000 + // Position of DI_SNAK5 field. + USB_DIEPCTL5_DI_SNAK5_Pos = 0x1b + // Bit mask of DI_SNAK5 field. + USB_DIEPCTL5_DI_SNAK5_Msk = 0x8000000 + // Bit DI_SNAK5. + USB_DIEPCTL5_DI_SNAK5 = 0x8000000 + // Position of DI_SETD0PID5 field. + USB_DIEPCTL5_DI_SETD0PID5_Pos = 0x1c + // Bit mask of DI_SETD0PID5 field. + USB_DIEPCTL5_DI_SETD0PID5_Msk = 0x10000000 + // Bit DI_SETD0PID5. + USB_DIEPCTL5_DI_SETD0PID5 = 0x10000000 + // Position of DI_SETD1PID5 field. + USB_DIEPCTL5_DI_SETD1PID5_Pos = 0x1d + // Bit mask of DI_SETD1PID5 field. + USB_DIEPCTL5_DI_SETD1PID5_Msk = 0x20000000 + // Bit DI_SETD1PID5. + USB_DIEPCTL5_DI_SETD1PID5 = 0x20000000 + // Position of DI_EPDIS5 field. + USB_DIEPCTL5_DI_EPDIS5_Pos = 0x1e + // Bit mask of DI_EPDIS5 field. + USB_DIEPCTL5_DI_EPDIS5_Msk = 0x40000000 + // Bit DI_EPDIS5. + USB_DIEPCTL5_DI_EPDIS5 = 0x40000000 + // Position of DI_EPENA5 field. + USB_DIEPCTL5_DI_EPENA5_Pos = 0x1f + // Bit mask of DI_EPENA5 field. + USB_DIEPCTL5_DI_EPENA5_Msk = 0x80000000 + // Bit DI_EPENA5. + USB_DIEPCTL5_DI_EPENA5 = 0x80000000 + + // DIEPINT5 + // Position of D_XFERCOMPL5 field. + USB_DIEPINT5_D_XFERCOMPL5_Pos = 0x0 + // Bit mask of D_XFERCOMPL5 field. + USB_DIEPINT5_D_XFERCOMPL5_Msk = 0x1 + // Bit D_XFERCOMPL5. + USB_DIEPINT5_D_XFERCOMPL5 = 0x1 + // Position of D_EPDISBLD5 field. + USB_DIEPINT5_D_EPDISBLD5_Pos = 0x1 + // Bit mask of D_EPDISBLD5 field. + USB_DIEPINT5_D_EPDISBLD5_Msk = 0x2 + // Bit D_EPDISBLD5. + USB_DIEPINT5_D_EPDISBLD5 = 0x2 + // Position of D_AHBERR5 field. + USB_DIEPINT5_D_AHBERR5_Pos = 0x2 + // Bit mask of D_AHBERR5 field. + USB_DIEPINT5_D_AHBERR5_Msk = 0x4 + // Bit D_AHBERR5. + USB_DIEPINT5_D_AHBERR5 = 0x4 + // Position of D_TIMEOUT5 field. + USB_DIEPINT5_D_TIMEOUT5_Pos = 0x3 + // Bit mask of D_TIMEOUT5 field. + USB_DIEPINT5_D_TIMEOUT5_Msk = 0x8 + // Bit D_TIMEOUT5. + USB_DIEPINT5_D_TIMEOUT5 = 0x8 + // Position of D_INTKNTXFEMP5 field. + USB_DIEPINT5_D_INTKNTXFEMP5_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP5 field. + USB_DIEPINT5_D_INTKNTXFEMP5_Msk = 0x10 + // Bit D_INTKNTXFEMP5. + USB_DIEPINT5_D_INTKNTXFEMP5 = 0x10 + // Position of D_INTKNEPMIS5 field. + USB_DIEPINT5_D_INTKNEPMIS5_Pos = 0x5 + // Bit mask of D_INTKNEPMIS5 field. + USB_DIEPINT5_D_INTKNEPMIS5_Msk = 0x20 + // Bit D_INTKNEPMIS5. + USB_DIEPINT5_D_INTKNEPMIS5 = 0x20 + // Position of D_INEPNAKEFF5 field. + USB_DIEPINT5_D_INEPNAKEFF5_Pos = 0x6 + // Bit mask of D_INEPNAKEFF5 field. + USB_DIEPINT5_D_INEPNAKEFF5_Msk = 0x40 + // Bit D_INEPNAKEFF5. + USB_DIEPINT5_D_INEPNAKEFF5 = 0x40 + // Position of D_TXFEMP5 field. + USB_DIEPINT5_D_TXFEMP5_Pos = 0x7 + // Bit mask of D_TXFEMP5 field. + USB_DIEPINT5_D_TXFEMP5_Msk = 0x80 + // Bit D_TXFEMP5. + USB_DIEPINT5_D_TXFEMP5 = 0x80 + // Position of D_TXFIFOUNDRN5 field. + USB_DIEPINT5_D_TXFIFOUNDRN5_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN5 field. + USB_DIEPINT5_D_TXFIFOUNDRN5_Msk = 0x100 + // Bit D_TXFIFOUNDRN5. + USB_DIEPINT5_D_TXFIFOUNDRN5 = 0x100 + // Position of D_BNAINTR5 field. + USB_DIEPINT5_D_BNAINTR5_Pos = 0x9 + // Bit mask of D_BNAINTR5 field. + USB_DIEPINT5_D_BNAINTR5_Msk = 0x200 + // Bit D_BNAINTR5. + USB_DIEPINT5_D_BNAINTR5 = 0x200 + // Position of D_PKTDRPSTS5 field. + USB_DIEPINT5_D_PKTDRPSTS5_Pos = 0xb + // Bit mask of D_PKTDRPSTS5 field. + USB_DIEPINT5_D_PKTDRPSTS5_Msk = 0x800 + // Bit D_PKTDRPSTS5. + USB_DIEPINT5_D_PKTDRPSTS5 = 0x800 + // Position of D_BBLEERR5 field. + USB_DIEPINT5_D_BBLEERR5_Pos = 0xc + // Bit mask of D_BBLEERR5 field. + USB_DIEPINT5_D_BBLEERR5_Msk = 0x1000 + // Bit D_BBLEERR5. + USB_DIEPINT5_D_BBLEERR5 = 0x1000 + // Position of D_NAKINTRPT5 field. + USB_DIEPINT5_D_NAKINTRPT5_Pos = 0xd + // Bit mask of D_NAKINTRPT5 field. + USB_DIEPINT5_D_NAKINTRPT5_Msk = 0x2000 + // Bit D_NAKINTRPT5. + USB_DIEPINT5_D_NAKINTRPT5 = 0x2000 + // Position of D_NYETINTRPT5 field. + USB_DIEPINT5_D_NYETINTRPT5_Pos = 0xe + // Bit mask of D_NYETINTRPT5 field. + USB_DIEPINT5_D_NYETINTRPT5_Msk = 0x4000 + // Bit D_NYETINTRPT5. + USB_DIEPINT5_D_NYETINTRPT5 = 0x4000 + + // DIEPTSIZ5 + // Position of D_XFERSIZE5 field. + USB_DIEPTSIZ5_D_XFERSIZE5_Pos = 0x0 + // Bit mask of D_XFERSIZE5 field. + USB_DIEPTSIZ5_D_XFERSIZE5_Msk = 0x7f + // Position of D_PKTCNT5 field. + USB_DIEPTSIZ5_D_PKTCNT5_Pos = 0x13 + // Bit mask of D_PKTCNT5 field. + USB_DIEPTSIZ5_D_PKTCNT5_Msk = 0x180000 + + // DIEPDMA5 + // Position of D_DMAADDR5 field. + USB_DIEPDMA5_D_DMAADDR5_Pos = 0x0 + // Bit mask of D_DMAADDR5 field. + USB_DIEPDMA5_D_DMAADDR5_Msk = 0xffffffff + + // DTXFSTS5 + // Position of D_INEPTXFSPCAVAIL5 field. + USB_DTXFSTS5_D_INEPTXFSPCAVAIL5_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL5 field. + USB_DTXFSTS5_D_INEPTXFSPCAVAIL5_Msk = 0xffff + + // DIEPDMAB5 + // Position of D_DMABUFFERADDR5 field. + USB_DIEPDMAB5_D_DMABUFFERADDR5_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR5 field. + USB_DIEPDMAB5_D_DMABUFFERADDR5_Msk = 0xffffffff + + // DIEPCTL6 + // Position of D_MPS6 field. + USB_DIEPCTL6_D_MPS6_Pos = 0x0 + // Bit mask of D_MPS6 field. + USB_DIEPCTL6_D_MPS6_Msk = 0x3 + // Position of D_USBACTEP6 field. + USB_DIEPCTL6_D_USBACTEP6_Pos = 0xf + // Bit mask of D_USBACTEP6 field. + USB_DIEPCTL6_D_USBACTEP6_Msk = 0x8000 + // Bit D_USBACTEP6. + USB_DIEPCTL6_D_USBACTEP6 = 0x8000 + // Position of D_NAKSTS6 field. + USB_DIEPCTL6_D_NAKSTS6_Pos = 0x11 + // Bit mask of D_NAKSTS6 field. + USB_DIEPCTL6_D_NAKSTS6_Msk = 0x20000 + // Bit D_NAKSTS6. + USB_DIEPCTL6_D_NAKSTS6 = 0x20000 + // Position of D_EPTYPE6 field. + USB_DIEPCTL6_D_EPTYPE6_Pos = 0x12 + // Bit mask of D_EPTYPE6 field. + USB_DIEPCTL6_D_EPTYPE6_Msk = 0xc0000 + // Position of D_STALL6 field. + USB_DIEPCTL6_D_STALL6_Pos = 0x15 + // Bit mask of D_STALL6 field. + USB_DIEPCTL6_D_STALL6_Msk = 0x200000 + // Bit D_STALL6. + USB_DIEPCTL6_D_STALL6 = 0x200000 + // Position of D_TXFNUM6 field. + USB_DIEPCTL6_D_TXFNUM6_Pos = 0x16 + // Bit mask of D_TXFNUM6 field. + USB_DIEPCTL6_D_TXFNUM6_Msk = 0x3c00000 + // Position of D_CNAK6 field. + USB_DIEPCTL6_D_CNAK6_Pos = 0x1a + // Bit mask of D_CNAK6 field. + USB_DIEPCTL6_D_CNAK6_Msk = 0x4000000 + // Bit D_CNAK6. + USB_DIEPCTL6_D_CNAK6 = 0x4000000 + // Position of DI_SNAK6 field. + USB_DIEPCTL6_DI_SNAK6_Pos = 0x1b + // Bit mask of DI_SNAK6 field. + USB_DIEPCTL6_DI_SNAK6_Msk = 0x8000000 + // Bit DI_SNAK6. + USB_DIEPCTL6_DI_SNAK6 = 0x8000000 + // Position of DI_SETD0PID6 field. + USB_DIEPCTL6_DI_SETD0PID6_Pos = 0x1c + // Bit mask of DI_SETD0PID6 field. + USB_DIEPCTL6_DI_SETD0PID6_Msk = 0x10000000 + // Bit DI_SETD0PID6. + USB_DIEPCTL6_DI_SETD0PID6 = 0x10000000 + // Position of DI_SETD1PID6 field. + USB_DIEPCTL6_DI_SETD1PID6_Pos = 0x1d + // Bit mask of DI_SETD1PID6 field. + USB_DIEPCTL6_DI_SETD1PID6_Msk = 0x20000000 + // Bit DI_SETD1PID6. + USB_DIEPCTL6_DI_SETD1PID6 = 0x20000000 + // Position of D_EPDIS6 field. + USB_DIEPCTL6_D_EPDIS6_Pos = 0x1e + // Bit mask of D_EPDIS6 field. + USB_DIEPCTL6_D_EPDIS6_Msk = 0x40000000 + // Bit D_EPDIS6. + USB_DIEPCTL6_D_EPDIS6 = 0x40000000 + // Position of D_EPENA6 field. + USB_DIEPCTL6_D_EPENA6_Pos = 0x1f + // Bit mask of D_EPENA6 field. + USB_DIEPCTL6_D_EPENA6_Msk = 0x80000000 + // Bit D_EPENA6. + USB_DIEPCTL6_D_EPENA6 = 0x80000000 + + // DIEPINT6 + // Position of D_XFERCOMPL6 field. + USB_DIEPINT6_D_XFERCOMPL6_Pos = 0x0 + // Bit mask of D_XFERCOMPL6 field. + USB_DIEPINT6_D_XFERCOMPL6_Msk = 0x1 + // Bit D_XFERCOMPL6. + USB_DIEPINT6_D_XFERCOMPL6 = 0x1 + // Position of D_EPDISBLD6 field. + USB_DIEPINT6_D_EPDISBLD6_Pos = 0x1 + // Bit mask of D_EPDISBLD6 field. + USB_DIEPINT6_D_EPDISBLD6_Msk = 0x2 + // Bit D_EPDISBLD6. + USB_DIEPINT6_D_EPDISBLD6 = 0x2 + // Position of D_AHBERR6 field. + USB_DIEPINT6_D_AHBERR6_Pos = 0x2 + // Bit mask of D_AHBERR6 field. + USB_DIEPINT6_D_AHBERR6_Msk = 0x4 + // Bit D_AHBERR6. + USB_DIEPINT6_D_AHBERR6 = 0x4 + // Position of D_TIMEOUT6 field. + USB_DIEPINT6_D_TIMEOUT6_Pos = 0x3 + // Bit mask of D_TIMEOUT6 field. + USB_DIEPINT6_D_TIMEOUT6_Msk = 0x8 + // Bit D_TIMEOUT6. + USB_DIEPINT6_D_TIMEOUT6 = 0x8 + // Position of D_INTKNTXFEMP6 field. + USB_DIEPINT6_D_INTKNTXFEMP6_Pos = 0x4 + // Bit mask of D_INTKNTXFEMP6 field. + USB_DIEPINT6_D_INTKNTXFEMP6_Msk = 0x10 + // Bit D_INTKNTXFEMP6. + USB_DIEPINT6_D_INTKNTXFEMP6 = 0x10 + // Position of D_INTKNEPMIS6 field. + USB_DIEPINT6_D_INTKNEPMIS6_Pos = 0x5 + // Bit mask of D_INTKNEPMIS6 field. + USB_DIEPINT6_D_INTKNEPMIS6_Msk = 0x20 + // Bit D_INTKNEPMIS6. + USB_DIEPINT6_D_INTKNEPMIS6 = 0x20 + // Position of D_INEPNAKEFF6 field. + USB_DIEPINT6_D_INEPNAKEFF6_Pos = 0x6 + // Bit mask of D_INEPNAKEFF6 field. + USB_DIEPINT6_D_INEPNAKEFF6_Msk = 0x40 + // Bit D_INEPNAKEFF6. + USB_DIEPINT6_D_INEPNAKEFF6 = 0x40 + // Position of D_TXFEMP6 field. + USB_DIEPINT6_D_TXFEMP6_Pos = 0x7 + // Bit mask of D_TXFEMP6 field. + USB_DIEPINT6_D_TXFEMP6_Msk = 0x80 + // Bit D_TXFEMP6. + USB_DIEPINT6_D_TXFEMP6 = 0x80 + // Position of D_TXFIFOUNDRN6 field. + USB_DIEPINT6_D_TXFIFOUNDRN6_Pos = 0x8 + // Bit mask of D_TXFIFOUNDRN6 field. + USB_DIEPINT6_D_TXFIFOUNDRN6_Msk = 0x100 + // Bit D_TXFIFOUNDRN6. + USB_DIEPINT6_D_TXFIFOUNDRN6 = 0x100 + // Position of D_BNAINTR6 field. + USB_DIEPINT6_D_BNAINTR6_Pos = 0x9 + // Bit mask of D_BNAINTR6 field. + USB_DIEPINT6_D_BNAINTR6_Msk = 0x200 + // Bit D_BNAINTR6. + USB_DIEPINT6_D_BNAINTR6 = 0x200 + // Position of D_PKTDRPSTS6 field. + USB_DIEPINT6_D_PKTDRPSTS6_Pos = 0xb + // Bit mask of D_PKTDRPSTS6 field. + USB_DIEPINT6_D_PKTDRPSTS6_Msk = 0x800 + // Bit D_PKTDRPSTS6. + USB_DIEPINT6_D_PKTDRPSTS6 = 0x800 + // Position of D_BBLEERR6 field. + USB_DIEPINT6_D_BBLEERR6_Pos = 0xc + // Bit mask of D_BBLEERR6 field. + USB_DIEPINT6_D_BBLEERR6_Msk = 0x1000 + // Bit D_BBLEERR6. + USB_DIEPINT6_D_BBLEERR6 = 0x1000 + // Position of D_NAKINTRPT6 field. + USB_DIEPINT6_D_NAKINTRPT6_Pos = 0xd + // Bit mask of D_NAKINTRPT6 field. + USB_DIEPINT6_D_NAKINTRPT6_Msk = 0x2000 + // Bit D_NAKINTRPT6. + USB_DIEPINT6_D_NAKINTRPT6 = 0x2000 + // Position of D_NYETINTRPT6 field. + USB_DIEPINT6_D_NYETINTRPT6_Pos = 0xe + // Bit mask of D_NYETINTRPT6 field. + USB_DIEPINT6_D_NYETINTRPT6_Msk = 0x4000 + // Bit D_NYETINTRPT6. + USB_DIEPINT6_D_NYETINTRPT6 = 0x4000 + + // DIEPTSIZ6 + // Position of D_XFERSIZE6 field. + USB_DIEPTSIZ6_D_XFERSIZE6_Pos = 0x0 + // Bit mask of D_XFERSIZE6 field. + USB_DIEPTSIZ6_D_XFERSIZE6_Msk = 0x7f + // Position of D_PKTCNT6 field. + USB_DIEPTSIZ6_D_PKTCNT6_Pos = 0x13 + // Bit mask of D_PKTCNT6 field. + USB_DIEPTSIZ6_D_PKTCNT6_Msk = 0x180000 + + // DIEPDMA6 + // Position of D_DMAADDR6 field. + USB_DIEPDMA6_D_DMAADDR6_Pos = 0x0 + // Bit mask of D_DMAADDR6 field. + USB_DIEPDMA6_D_DMAADDR6_Msk = 0xffffffff + + // DTXFSTS6 + // Position of D_INEPTXFSPCAVAIL6 field. + USB_DTXFSTS6_D_INEPTXFSPCAVAIL6_Pos = 0x0 + // Bit mask of D_INEPTXFSPCAVAIL6 field. + USB_DTXFSTS6_D_INEPTXFSPCAVAIL6_Msk = 0xffff + + // DIEPDMAB6 + // Position of D_DMABUFFERADDR6 field. + USB_DIEPDMAB6_D_DMABUFFERADDR6_Pos = 0x0 + // Bit mask of D_DMABUFFERADDR6 field. + USB_DIEPDMAB6_D_DMABUFFERADDR6_Msk = 0xffffffff + + // DOEPCTL0 + // Position of MPS0 field. + USB_DOEPCTL0_MPS0_Pos = 0x0 + // Bit mask of MPS0 field. + USB_DOEPCTL0_MPS0_Msk = 0x3 + // Position of USBACTEP0 field. + USB_DOEPCTL0_USBACTEP0_Pos = 0xf + // Bit mask of USBACTEP0 field. + USB_DOEPCTL0_USBACTEP0_Msk = 0x8000 + // Bit USBACTEP0. + USB_DOEPCTL0_USBACTEP0 = 0x8000 + // Position of NAKSTS0 field. + USB_DOEPCTL0_NAKSTS0_Pos = 0x11 + // Bit mask of NAKSTS0 field. + USB_DOEPCTL0_NAKSTS0_Msk = 0x20000 + // Bit NAKSTS0. + USB_DOEPCTL0_NAKSTS0 = 0x20000 + // Position of EPTYPE0 field. + USB_DOEPCTL0_EPTYPE0_Pos = 0x12 + // Bit mask of EPTYPE0 field. + USB_DOEPCTL0_EPTYPE0_Msk = 0xc0000 + // Position of SNP0 field. + USB_DOEPCTL0_SNP0_Pos = 0x14 + // Bit mask of SNP0 field. + USB_DOEPCTL0_SNP0_Msk = 0x100000 + // Bit SNP0. + USB_DOEPCTL0_SNP0 = 0x100000 + // Position of STALL0 field. + USB_DOEPCTL0_STALL0_Pos = 0x15 + // Bit mask of STALL0 field. + USB_DOEPCTL0_STALL0_Msk = 0x200000 + // Bit STALL0. + USB_DOEPCTL0_STALL0 = 0x200000 + // Position of CNAK0 field. + USB_DOEPCTL0_CNAK0_Pos = 0x1a + // Bit mask of CNAK0 field. + USB_DOEPCTL0_CNAK0_Msk = 0x4000000 + // Bit CNAK0. + USB_DOEPCTL0_CNAK0 = 0x4000000 + // Position of DO_SNAK0 field. + USB_DOEPCTL0_DO_SNAK0_Pos = 0x1b + // Bit mask of DO_SNAK0 field. + USB_DOEPCTL0_DO_SNAK0_Msk = 0x8000000 + // Bit DO_SNAK0. + USB_DOEPCTL0_DO_SNAK0 = 0x8000000 + // Position of EPDIS0 field. + USB_DOEPCTL0_EPDIS0_Pos = 0x1e + // Bit mask of EPDIS0 field. + USB_DOEPCTL0_EPDIS0_Msk = 0x40000000 + // Bit EPDIS0. + USB_DOEPCTL0_EPDIS0 = 0x40000000 + // Position of EPENA0 field. + USB_DOEPCTL0_EPENA0_Pos = 0x1f + // Bit mask of EPENA0 field. + USB_DOEPCTL0_EPENA0_Msk = 0x80000000 + // Bit EPENA0. + USB_DOEPCTL0_EPENA0 = 0x80000000 + + // DOEPINT0 + // Position of XFERCOMPL0 field. + USB_DOEPINT0_XFERCOMPL0_Pos = 0x0 + // Bit mask of XFERCOMPL0 field. + USB_DOEPINT0_XFERCOMPL0_Msk = 0x1 + // Bit XFERCOMPL0. + USB_DOEPINT0_XFERCOMPL0 = 0x1 + // Position of EPDISBLD0 field. + USB_DOEPINT0_EPDISBLD0_Pos = 0x1 + // Bit mask of EPDISBLD0 field. + USB_DOEPINT0_EPDISBLD0_Msk = 0x2 + // Bit EPDISBLD0. + USB_DOEPINT0_EPDISBLD0 = 0x2 + // Position of AHBERR0 field. + USB_DOEPINT0_AHBERR0_Pos = 0x2 + // Bit mask of AHBERR0 field. + USB_DOEPINT0_AHBERR0_Msk = 0x4 + // Bit AHBERR0. + USB_DOEPINT0_AHBERR0 = 0x4 + // Position of SETUP0 field. + USB_DOEPINT0_SETUP0_Pos = 0x3 + // Bit mask of SETUP0 field. + USB_DOEPINT0_SETUP0_Msk = 0x8 + // Bit SETUP0. + USB_DOEPINT0_SETUP0 = 0x8 + // Position of OUTTKNEPDIS0 field. + USB_DOEPINT0_OUTTKNEPDIS0_Pos = 0x4 + // Bit mask of OUTTKNEPDIS0 field. + USB_DOEPINT0_OUTTKNEPDIS0_Msk = 0x10 + // Bit OUTTKNEPDIS0. + USB_DOEPINT0_OUTTKNEPDIS0 = 0x10 + // Position of STSPHSERCVD0 field. + USB_DOEPINT0_STSPHSERCVD0_Pos = 0x5 + // Bit mask of STSPHSERCVD0 field. + USB_DOEPINT0_STSPHSERCVD0_Msk = 0x20 + // Bit STSPHSERCVD0. + USB_DOEPINT0_STSPHSERCVD0 = 0x20 + // Position of BACK2BACKSETUP0 field. + USB_DOEPINT0_BACK2BACKSETUP0_Pos = 0x6 + // Bit mask of BACK2BACKSETUP0 field. + USB_DOEPINT0_BACK2BACKSETUP0_Msk = 0x40 + // Bit BACK2BACKSETUP0. + USB_DOEPINT0_BACK2BACKSETUP0 = 0x40 + // Position of OUTPKTERR0 field. + USB_DOEPINT0_OUTPKTERR0_Pos = 0x8 + // Bit mask of OUTPKTERR0 field. + USB_DOEPINT0_OUTPKTERR0_Msk = 0x100 + // Bit OUTPKTERR0. + USB_DOEPINT0_OUTPKTERR0 = 0x100 + // Position of BNAINTR0 field. + USB_DOEPINT0_BNAINTR0_Pos = 0x9 + // Bit mask of BNAINTR0 field. + USB_DOEPINT0_BNAINTR0_Msk = 0x200 + // Bit BNAINTR0. + USB_DOEPINT0_BNAINTR0 = 0x200 + // Position of PKTDRPSTS0 field. + USB_DOEPINT0_PKTDRPSTS0_Pos = 0xb + // Bit mask of PKTDRPSTS0 field. + USB_DOEPINT0_PKTDRPSTS0_Msk = 0x800 + // Bit PKTDRPSTS0. + USB_DOEPINT0_PKTDRPSTS0 = 0x800 + // Position of BBLEERR0 field. + USB_DOEPINT0_BBLEERR0_Pos = 0xc + // Bit mask of BBLEERR0 field. + USB_DOEPINT0_BBLEERR0_Msk = 0x1000 + // Bit BBLEERR0. + USB_DOEPINT0_BBLEERR0 = 0x1000 + // Position of NAKINTRPT0 field. + USB_DOEPINT0_NAKINTRPT0_Pos = 0xd + // Bit mask of NAKINTRPT0 field. + USB_DOEPINT0_NAKINTRPT0_Msk = 0x2000 + // Bit NAKINTRPT0. + USB_DOEPINT0_NAKINTRPT0 = 0x2000 + // Position of NYEPINTRPT0 field. + USB_DOEPINT0_NYEPINTRPT0_Pos = 0xe + // Bit mask of NYEPINTRPT0 field. + USB_DOEPINT0_NYEPINTRPT0_Msk = 0x4000 + // Bit NYEPINTRPT0. + USB_DOEPINT0_NYEPINTRPT0 = 0x4000 + // Position of STUPPKTRCVD0 field. + USB_DOEPINT0_STUPPKTRCVD0_Pos = 0xf + // Bit mask of STUPPKTRCVD0 field. + USB_DOEPINT0_STUPPKTRCVD0_Msk = 0x8000 + // Bit STUPPKTRCVD0. + USB_DOEPINT0_STUPPKTRCVD0 = 0x8000 + + // DOEPTSIZ0 + // Position of XFERSIZE0 field. + USB_DOEPTSIZ0_XFERSIZE0_Pos = 0x0 + // Bit mask of XFERSIZE0 field. + USB_DOEPTSIZ0_XFERSIZE0_Msk = 0x7f + // Position of PKTCNT0 field. + USB_DOEPTSIZ0_PKTCNT0_Pos = 0x13 + // Bit mask of PKTCNT0 field. + USB_DOEPTSIZ0_PKTCNT0_Msk = 0x80000 + // Bit PKTCNT0. + USB_DOEPTSIZ0_PKTCNT0 = 0x80000 + // Position of SUPCNT0 field. + USB_DOEPTSIZ0_SUPCNT0_Pos = 0x1d + // Bit mask of SUPCNT0 field. + USB_DOEPTSIZ0_SUPCNT0_Msk = 0x60000000 + + // DOEPDMA0 + // Position of DMAADDR0 field. + USB_DOEPDMA0_DMAADDR0_Pos = 0x0 + // Bit mask of DMAADDR0 field. + USB_DOEPDMA0_DMAADDR0_Msk = 0xffffffff + + // DOEPDMAB0 + // Position of DMABUFFERADDR0 field. + USB_DOEPDMAB0_DMABUFFERADDR0_Pos = 0x0 + // Bit mask of DMABUFFERADDR0 field. + USB_DOEPDMAB0_DMABUFFERADDR0_Msk = 0xffffffff + + // DOEPCTL1 + // Position of MPS1 field. + USB_DOEPCTL1_MPS1_Pos = 0x0 + // Bit mask of MPS1 field. + USB_DOEPCTL1_MPS1_Msk = 0x7ff + // Position of USBACTEP1 field. + USB_DOEPCTL1_USBACTEP1_Pos = 0xf + // Bit mask of USBACTEP1 field. + USB_DOEPCTL1_USBACTEP1_Msk = 0x8000 + // Bit USBACTEP1. + USB_DOEPCTL1_USBACTEP1 = 0x8000 + // Position of NAKSTS1 field. + USB_DOEPCTL1_NAKSTS1_Pos = 0x11 + // Bit mask of NAKSTS1 field. + USB_DOEPCTL1_NAKSTS1_Msk = 0x20000 + // Bit NAKSTS1. + USB_DOEPCTL1_NAKSTS1 = 0x20000 + // Position of EPTYPE1 field. + USB_DOEPCTL1_EPTYPE1_Pos = 0x12 + // Bit mask of EPTYPE1 field. + USB_DOEPCTL1_EPTYPE1_Msk = 0xc0000 + // Position of SNP1 field. + USB_DOEPCTL1_SNP1_Pos = 0x14 + // Bit mask of SNP1 field. + USB_DOEPCTL1_SNP1_Msk = 0x100000 + // Bit SNP1. + USB_DOEPCTL1_SNP1 = 0x100000 + // Position of STALL1 field. + USB_DOEPCTL1_STALL1_Pos = 0x15 + // Bit mask of STALL1 field. + USB_DOEPCTL1_STALL1_Msk = 0x200000 + // Bit STALL1. + USB_DOEPCTL1_STALL1 = 0x200000 + // Position of CNAK1 field. + USB_DOEPCTL1_CNAK1_Pos = 0x1a + // Bit mask of CNAK1 field. + USB_DOEPCTL1_CNAK1_Msk = 0x4000000 + // Bit CNAK1. + USB_DOEPCTL1_CNAK1 = 0x4000000 + // Position of DO_SNAK1 field. + USB_DOEPCTL1_DO_SNAK1_Pos = 0x1b + // Bit mask of DO_SNAK1 field. + USB_DOEPCTL1_DO_SNAK1_Msk = 0x8000000 + // Bit DO_SNAK1. + USB_DOEPCTL1_DO_SNAK1 = 0x8000000 + // Position of DO_SETD0PID1 field. + USB_DOEPCTL1_DO_SETD0PID1_Pos = 0x1c + // Bit mask of DO_SETD0PID1 field. + USB_DOEPCTL1_DO_SETD0PID1_Msk = 0x10000000 + // Bit DO_SETD0PID1. + USB_DOEPCTL1_DO_SETD0PID1 = 0x10000000 + // Position of DO_SETD1PID1 field. + USB_DOEPCTL1_DO_SETD1PID1_Pos = 0x1d + // Bit mask of DO_SETD1PID1 field. + USB_DOEPCTL1_DO_SETD1PID1_Msk = 0x20000000 + // Bit DO_SETD1PID1. + USB_DOEPCTL1_DO_SETD1PID1 = 0x20000000 + // Position of EPDIS1 field. + USB_DOEPCTL1_EPDIS1_Pos = 0x1e + // Bit mask of EPDIS1 field. + USB_DOEPCTL1_EPDIS1_Msk = 0x40000000 + // Bit EPDIS1. + USB_DOEPCTL1_EPDIS1 = 0x40000000 + // Position of EPENA1 field. + USB_DOEPCTL1_EPENA1_Pos = 0x1f + // Bit mask of EPENA1 field. + USB_DOEPCTL1_EPENA1_Msk = 0x80000000 + // Bit EPENA1. + USB_DOEPCTL1_EPENA1 = 0x80000000 + + // DOEPINT1 + // Position of XFERCOMPL1 field. + USB_DOEPINT1_XFERCOMPL1_Pos = 0x0 + // Bit mask of XFERCOMPL1 field. + USB_DOEPINT1_XFERCOMPL1_Msk = 0x1 + // Bit XFERCOMPL1. + USB_DOEPINT1_XFERCOMPL1 = 0x1 + // Position of EPDISBLD1 field. + USB_DOEPINT1_EPDISBLD1_Pos = 0x1 + // Bit mask of EPDISBLD1 field. + USB_DOEPINT1_EPDISBLD1_Msk = 0x2 + // Bit EPDISBLD1. + USB_DOEPINT1_EPDISBLD1 = 0x2 + // Position of AHBERR1 field. + USB_DOEPINT1_AHBERR1_Pos = 0x2 + // Bit mask of AHBERR1 field. + USB_DOEPINT1_AHBERR1_Msk = 0x4 + // Bit AHBERR1. + USB_DOEPINT1_AHBERR1 = 0x4 + // Position of SETUP1 field. + USB_DOEPINT1_SETUP1_Pos = 0x3 + // Bit mask of SETUP1 field. + USB_DOEPINT1_SETUP1_Msk = 0x8 + // Bit SETUP1. + USB_DOEPINT1_SETUP1 = 0x8 + // Position of OUTTKNEPDIS1 field. + USB_DOEPINT1_OUTTKNEPDIS1_Pos = 0x4 + // Bit mask of OUTTKNEPDIS1 field. + USB_DOEPINT1_OUTTKNEPDIS1_Msk = 0x10 + // Bit OUTTKNEPDIS1. + USB_DOEPINT1_OUTTKNEPDIS1 = 0x10 + // Position of STSPHSERCVD1 field. + USB_DOEPINT1_STSPHSERCVD1_Pos = 0x5 + // Bit mask of STSPHSERCVD1 field. + USB_DOEPINT1_STSPHSERCVD1_Msk = 0x20 + // Bit STSPHSERCVD1. + USB_DOEPINT1_STSPHSERCVD1 = 0x20 + // Position of BACK2BACKSETUP1 field. + USB_DOEPINT1_BACK2BACKSETUP1_Pos = 0x6 + // Bit mask of BACK2BACKSETUP1 field. + USB_DOEPINT1_BACK2BACKSETUP1_Msk = 0x40 + // Bit BACK2BACKSETUP1. + USB_DOEPINT1_BACK2BACKSETUP1 = 0x40 + // Position of OUTPKTERR1 field. + USB_DOEPINT1_OUTPKTERR1_Pos = 0x8 + // Bit mask of OUTPKTERR1 field. + USB_DOEPINT1_OUTPKTERR1_Msk = 0x100 + // Bit OUTPKTERR1. + USB_DOEPINT1_OUTPKTERR1 = 0x100 + // Position of BNAINTR1 field. + USB_DOEPINT1_BNAINTR1_Pos = 0x9 + // Bit mask of BNAINTR1 field. + USB_DOEPINT1_BNAINTR1_Msk = 0x200 + // Bit BNAINTR1. + USB_DOEPINT1_BNAINTR1 = 0x200 + // Position of PKTDRPSTS1 field. + USB_DOEPINT1_PKTDRPSTS1_Pos = 0xb + // Bit mask of PKTDRPSTS1 field. + USB_DOEPINT1_PKTDRPSTS1_Msk = 0x800 + // Bit PKTDRPSTS1. + USB_DOEPINT1_PKTDRPSTS1 = 0x800 + // Position of BBLEERR1 field. + USB_DOEPINT1_BBLEERR1_Pos = 0xc + // Bit mask of BBLEERR1 field. + USB_DOEPINT1_BBLEERR1_Msk = 0x1000 + // Bit BBLEERR1. + USB_DOEPINT1_BBLEERR1 = 0x1000 + // Position of NAKINTRPT1 field. + USB_DOEPINT1_NAKINTRPT1_Pos = 0xd + // Bit mask of NAKINTRPT1 field. + USB_DOEPINT1_NAKINTRPT1_Msk = 0x2000 + // Bit NAKINTRPT1. + USB_DOEPINT1_NAKINTRPT1 = 0x2000 + // Position of NYEPINTRPT1 field. + USB_DOEPINT1_NYEPINTRPT1_Pos = 0xe + // Bit mask of NYEPINTRPT1 field. + USB_DOEPINT1_NYEPINTRPT1_Msk = 0x4000 + // Bit NYEPINTRPT1. + USB_DOEPINT1_NYEPINTRPT1 = 0x4000 + // Position of STUPPKTRCVD1 field. + USB_DOEPINT1_STUPPKTRCVD1_Pos = 0xf + // Bit mask of STUPPKTRCVD1 field. + USB_DOEPINT1_STUPPKTRCVD1_Msk = 0x8000 + // Bit STUPPKTRCVD1. + USB_DOEPINT1_STUPPKTRCVD1 = 0x8000 + + // DOEPTSIZ1 + // Position of XFERSIZE1 field. + USB_DOEPTSIZ1_XFERSIZE1_Pos = 0x0 + // Bit mask of XFERSIZE1 field. + USB_DOEPTSIZ1_XFERSIZE1_Msk = 0x7f + // Position of PKTCNT1 field. + USB_DOEPTSIZ1_PKTCNT1_Pos = 0x13 + // Bit mask of PKTCNT1 field. + USB_DOEPTSIZ1_PKTCNT1_Msk = 0x80000 + // Bit PKTCNT1. + USB_DOEPTSIZ1_PKTCNT1 = 0x80000 + // Position of SUPCNT1 field. + USB_DOEPTSIZ1_SUPCNT1_Pos = 0x1d + // Bit mask of SUPCNT1 field. + USB_DOEPTSIZ1_SUPCNT1_Msk = 0x60000000 + + // DOEPDMA1 + // Position of DMAADDR1 field. + USB_DOEPDMA1_DMAADDR1_Pos = 0x0 + // Bit mask of DMAADDR1 field. + USB_DOEPDMA1_DMAADDR1_Msk = 0xffffffff + + // DOEPDMAB1 + // Position of DMABUFFERADDR1 field. + USB_DOEPDMAB1_DMABUFFERADDR1_Pos = 0x0 + // Bit mask of DMABUFFERADDR1 field. + USB_DOEPDMAB1_DMABUFFERADDR1_Msk = 0xffffffff + + // DOEPCTL2 + // Position of MPS2 field. + USB_DOEPCTL2_MPS2_Pos = 0x0 + // Bit mask of MPS2 field. + USB_DOEPCTL2_MPS2_Msk = 0x7ff + // Position of USBACTEP2 field. + USB_DOEPCTL2_USBACTEP2_Pos = 0xf + // Bit mask of USBACTEP2 field. + USB_DOEPCTL2_USBACTEP2_Msk = 0x8000 + // Bit USBACTEP2. + USB_DOEPCTL2_USBACTEP2 = 0x8000 + // Position of NAKSTS2 field. + USB_DOEPCTL2_NAKSTS2_Pos = 0x11 + // Bit mask of NAKSTS2 field. + USB_DOEPCTL2_NAKSTS2_Msk = 0x20000 + // Bit NAKSTS2. + USB_DOEPCTL2_NAKSTS2 = 0x20000 + // Position of EPTYPE2 field. + USB_DOEPCTL2_EPTYPE2_Pos = 0x12 + // Bit mask of EPTYPE2 field. + USB_DOEPCTL2_EPTYPE2_Msk = 0xc0000 + // Position of SNP2 field. + USB_DOEPCTL2_SNP2_Pos = 0x14 + // Bit mask of SNP2 field. + USB_DOEPCTL2_SNP2_Msk = 0x100000 + // Bit SNP2. + USB_DOEPCTL2_SNP2 = 0x100000 + // Position of STALL2 field. + USB_DOEPCTL2_STALL2_Pos = 0x15 + // Bit mask of STALL2 field. + USB_DOEPCTL2_STALL2_Msk = 0x200000 + // Bit STALL2. + USB_DOEPCTL2_STALL2 = 0x200000 + // Position of CNAK2 field. + USB_DOEPCTL2_CNAK2_Pos = 0x1a + // Bit mask of CNAK2 field. + USB_DOEPCTL2_CNAK2_Msk = 0x4000000 + // Bit CNAK2. + USB_DOEPCTL2_CNAK2 = 0x4000000 + // Position of DO_SNAK2 field. + USB_DOEPCTL2_DO_SNAK2_Pos = 0x1b + // Bit mask of DO_SNAK2 field. + USB_DOEPCTL2_DO_SNAK2_Msk = 0x8000000 + // Bit DO_SNAK2. + USB_DOEPCTL2_DO_SNAK2 = 0x8000000 + // Position of DO_SETD0PID2 field. + USB_DOEPCTL2_DO_SETD0PID2_Pos = 0x1c + // Bit mask of DO_SETD0PID2 field. + USB_DOEPCTL2_DO_SETD0PID2_Msk = 0x10000000 + // Bit DO_SETD0PID2. + USB_DOEPCTL2_DO_SETD0PID2 = 0x10000000 + // Position of DO_SETD1PID2 field. + USB_DOEPCTL2_DO_SETD1PID2_Pos = 0x1d + // Bit mask of DO_SETD1PID2 field. + USB_DOEPCTL2_DO_SETD1PID2_Msk = 0x20000000 + // Bit DO_SETD1PID2. + USB_DOEPCTL2_DO_SETD1PID2 = 0x20000000 + // Position of EPDIS2 field. + USB_DOEPCTL2_EPDIS2_Pos = 0x1e + // Bit mask of EPDIS2 field. + USB_DOEPCTL2_EPDIS2_Msk = 0x40000000 + // Bit EPDIS2. + USB_DOEPCTL2_EPDIS2 = 0x40000000 + // Position of EPENA2 field. + USB_DOEPCTL2_EPENA2_Pos = 0x1f + // Bit mask of EPENA2 field. + USB_DOEPCTL2_EPENA2_Msk = 0x80000000 + // Bit EPENA2. + USB_DOEPCTL2_EPENA2 = 0x80000000 + + // DOEPINT2 + // Position of XFERCOMPL2 field. + USB_DOEPINT2_XFERCOMPL2_Pos = 0x0 + // Bit mask of XFERCOMPL2 field. + USB_DOEPINT2_XFERCOMPL2_Msk = 0x1 + // Bit XFERCOMPL2. + USB_DOEPINT2_XFERCOMPL2 = 0x1 + // Position of EPDISBLD2 field. + USB_DOEPINT2_EPDISBLD2_Pos = 0x1 + // Bit mask of EPDISBLD2 field. + USB_DOEPINT2_EPDISBLD2_Msk = 0x2 + // Bit EPDISBLD2. + USB_DOEPINT2_EPDISBLD2 = 0x2 + // Position of AHBERR2 field. + USB_DOEPINT2_AHBERR2_Pos = 0x2 + // Bit mask of AHBERR2 field. + USB_DOEPINT2_AHBERR2_Msk = 0x4 + // Bit AHBERR2. + USB_DOEPINT2_AHBERR2 = 0x4 + // Position of SETUP2 field. + USB_DOEPINT2_SETUP2_Pos = 0x3 + // Bit mask of SETUP2 field. + USB_DOEPINT2_SETUP2_Msk = 0x8 + // Bit SETUP2. + USB_DOEPINT2_SETUP2 = 0x8 + // Position of OUTTKNEPDIS2 field. + USB_DOEPINT2_OUTTKNEPDIS2_Pos = 0x4 + // Bit mask of OUTTKNEPDIS2 field. + USB_DOEPINT2_OUTTKNEPDIS2_Msk = 0x10 + // Bit OUTTKNEPDIS2. + USB_DOEPINT2_OUTTKNEPDIS2 = 0x10 + // Position of STSPHSERCVD2 field. + USB_DOEPINT2_STSPHSERCVD2_Pos = 0x5 + // Bit mask of STSPHSERCVD2 field. + USB_DOEPINT2_STSPHSERCVD2_Msk = 0x20 + // Bit STSPHSERCVD2. + USB_DOEPINT2_STSPHSERCVD2 = 0x20 + // Position of BACK2BACKSETUP2 field. + USB_DOEPINT2_BACK2BACKSETUP2_Pos = 0x6 + // Bit mask of BACK2BACKSETUP2 field. + USB_DOEPINT2_BACK2BACKSETUP2_Msk = 0x40 + // Bit BACK2BACKSETUP2. + USB_DOEPINT2_BACK2BACKSETUP2 = 0x40 + // Position of OUTPKTERR2 field. + USB_DOEPINT2_OUTPKTERR2_Pos = 0x8 + // Bit mask of OUTPKTERR2 field. + USB_DOEPINT2_OUTPKTERR2_Msk = 0x100 + // Bit OUTPKTERR2. + USB_DOEPINT2_OUTPKTERR2 = 0x100 + // Position of BNAINTR2 field. + USB_DOEPINT2_BNAINTR2_Pos = 0x9 + // Bit mask of BNAINTR2 field. + USB_DOEPINT2_BNAINTR2_Msk = 0x200 + // Bit BNAINTR2. + USB_DOEPINT2_BNAINTR2 = 0x200 + // Position of PKTDRPSTS2 field. + USB_DOEPINT2_PKTDRPSTS2_Pos = 0xb + // Bit mask of PKTDRPSTS2 field. + USB_DOEPINT2_PKTDRPSTS2_Msk = 0x800 + // Bit PKTDRPSTS2. + USB_DOEPINT2_PKTDRPSTS2 = 0x800 + // Position of BBLEERR2 field. + USB_DOEPINT2_BBLEERR2_Pos = 0xc + // Bit mask of BBLEERR2 field. + USB_DOEPINT2_BBLEERR2_Msk = 0x1000 + // Bit BBLEERR2. + USB_DOEPINT2_BBLEERR2 = 0x1000 + // Position of NAKINTRPT2 field. + USB_DOEPINT2_NAKINTRPT2_Pos = 0xd + // Bit mask of NAKINTRPT2 field. + USB_DOEPINT2_NAKINTRPT2_Msk = 0x2000 + // Bit NAKINTRPT2. + USB_DOEPINT2_NAKINTRPT2 = 0x2000 + // Position of NYEPINTRPT2 field. + USB_DOEPINT2_NYEPINTRPT2_Pos = 0xe + // Bit mask of NYEPINTRPT2 field. + USB_DOEPINT2_NYEPINTRPT2_Msk = 0x4000 + // Bit NYEPINTRPT2. + USB_DOEPINT2_NYEPINTRPT2 = 0x4000 + // Position of STUPPKTRCVD2 field. + USB_DOEPINT2_STUPPKTRCVD2_Pos = 0xf + // Bit mask of STUPPKTRCVD2 field. + USB_DOEPINT2_STUPPKTRCVD2_Msk = 0x8000 + // Bit STUPPKTRCVD2. + USB_DOEPINT2_STUPPKTRCVD2 = 0x8000 + + // DOEPTSIZ2 + // Position of XFERSIZE2 field. + USB_DOEPTSIZ2_XFERSIZE2_Pos = 0x0 + // Bit mask of XFERSIZE2 field. + USB_DOEPTSIZ2_XFERSIZE2_Msk = 0x7f + // Position of PKTCNT2 field. + USB_DOEPTSIZ2_PKTCNT2_Pos = 0x13 + // Bit mask of PKTCNT2 field. + USB_DOEPTSIZ2_PKTCNT2_Msk = 0x80000 + // Bit PKTCNT2. + USB_DOEPTSIZ2_PKTCNT2 = 0x80000 + // Position of SUPCNT2 field. + USB_DOEPTSIZ2_SUPCNT2_Pos = 0x1d + // Bit mask of SUPCNT2 field. + USB_DOEPTSIZ2_SUPCNT2_Msk = 0x60000000 + + // DOEPDMA2 + // Position of DMAADDR2 field. + USB_DOEPDMA2_DMAADDR2_Pos = 0x0 + // Bit mask of DMAADDR2 field. + USB_DOEPDMA2_DMAADDR2_Msk = 0xffffffff + + // DOEPDMAB2 + // Position of DMABUFFERADDR2 field. + USB_DOEPDMAB2_DMABUFFERADDR2_Pos = 0x0 + // Bit mask of DMABUFFERADDR2 field. + USB_DOEPDMAB2_DMABUFFERADDR2_Msk = 0xffffffff + + // DOEPCTL3 + // Position of MPS3 field. + USB_DOEPCTL3_MPS3_Pos = 0x0 + // Bit mask of MPS3 field. + USB_DOEPCTL3_MPS3_Msk = 0x7ff + // Position of USBACTEP3 field. + USB_DOEPCTL3_USBACTEP3_Pos = 0xf + // Bit mask of USBACTEP3 field. + USB_DOEPCTL3_USBACTEP3_Msk = 0x8000 + // Bit USBACTEP3. + USB_DOEPCTL3_USBACTEP3 = 0x8000 + // Position of NAKSTS3 field. + USB_DOEPCTL3_NAKSTS3_Pos = 0x11 + // Bit mask of NAKSTS3 field. + USB_DOEPCTL3_NAKSTS3_Msk = 0x20000 + // Bit NAKSTS3. + USB_DOEPCTL3_NAKSTS3 = 0x20000 + // Position of EPTYPE3 field. + USB_DOEPCTL3_EPTYPE3_Pos = 0x12 + // Bit mask of EPTYPE3 field. + USB_DOEPCTL3_EPTYPE3_Msk = 0xc0000 + // Position of SNP3 field. + USB_DOEPCTL3_SNP3_Pos = 0x14 + // Bit mask of SNP3 field. + USB_DOEPCTL3_SNP3_Msk = 0x100000 + // Bit SNP3. + USB_DOEPCTL3_SNP3 = 0x100000 + // Position of STALL3 field. + USB_DOEPCTL3_STALL3_Pos = 0x15 + // Bit mask of STALL3 field. + USB_DOEPCTL3_STALL3_Msk = 0x200000 + // Bit STALL3. + USB_DOEPCTL3_STALL3 = 0x200000 + // Position of CNAK3 field. + USB_DOEPCTL3_CNAK3_Pos = 0x1a + // Bit mask of CNAK3 field. + USB_DOEPCTL3_CNAK3_Msk = 0x4000000 + // Bit CNAK3. + USB_DOEPCTL3_CNAK3 = 0x4000000 + // Position of DO_SNAK3 field. + USB_DOEPCTL3_DO_SNAK3_Pos = 0x1b + // Bit mask of DO_SNAK3 field. + USB_DOEPCTL3_DO_SNAK3_Msk = 0x8000000 + // Bit DO_SNAK3. + USB_DOEPCTL3_DO_SNAK3 = 0x8000000 + // Position of DO_SETD0PID3 field. + USB_DOEPCTL3_DO_SETD0PID3_Pos = 0x1c + // Bit mask of DO_SETD0PID3 field. + USB_DOEPCTL3_DO_SETD0PID3_Msk = 0x10000000 + // Bit DO_SETD0PID3. + USB_DOEPCTL3_DO_SETD0PID3 = 0x10000000 + // Position of DO_SETD1PID3 field. + USB_DOEPCTL3_DO_SETD1PID3_Pos = 0x1d + // Bit mask of DO_SETD1PID3 field. + USB_DOEPCTL3_DO_SETD1PID3_Msk = 0x20000000 + // Bit DO_SETD1PID3. + USB_DOEPCTL3_DO_SETD1PID3 = 0x20000000 + // Position of EPDIS3 field. + USB_DOEPCTL3_EPDIS3_Pos = 0x1e + // Bit mask of EPDIS3 field. + USB_DOEPCTL3_EPDIS3_Msk = 0x40000000 + // Bit EPDIS3. + USB_DOEPCTL3_EPDIS3 = 0x40000000 + // Position of EPENA3 field. + USB_DOEPCTL3_EPENA3_Pos = 0x1f + // Bit mask of EPENA3 field. + USB_DOEPCTL3_EPENA3_Msk = 0x80000000 + // Bit EPENA3. + USB_DOEPCTL3_EPENA3 = 0x80000000 + + // DOEPINT3 + // Position of XFERCOMPL3 field. + USB_DOEPINT3_XFERCOMPL3_Pos = 0x0 + // Bit mask of XFERCOMPL3 field. + USB_DOEPINT3_XFERCOMPL3_Msk = 0x1 + // Bit XFERCOMPL3. + USB_DOEPINT3_XFERCOMPL3 = 0x1 + // Position of EPDISBLD3 field. + USB_DOEPINT3_EPDISBLD3_Pos = 0x1 + // Bit mask of EPDISBLD3 field. + USB_DOEPINT3_EPDISBLD3_Msk = 0x2 + // Bit EPDISBLD3. + USB_DOEPINT3_EPDISBLD3 = 0x2 + // Position of AHBERR3 field. + USB_DOEPINT3_AHBERR3_Pos = 0x2 + // Bit mask of AHBERR3 field. + USB_DOEPINT3_AHBERR3_Msk = 0x4 + // Bit AHBERR3. + USB_DOEPINT3_AHBERR3 = 0x4 + // Position of SETUP3 field. + USB_DOEPINT3_SETUP3_Pos = 0x3 + // Bit mask of SETUP3 field. + USB_DOEPINT3_SETUP3_Msk = 0x8 + // Bit SETUP3. + USB_DOEPINT3_SETUP3 = 0x8 + // Position of OUTTKNEPDIS3 field. + USB_DOEPINT3_OUTTKNEPDIS3_Pos = 0x4 + // Bit mask of OUTTKNEPDIS3 field. + USB_DOEPINT3_OUTTKNEPDIS3_Msk = 0x10 + // Bit OUTTKNEPDIS3. + USB_DOEPINT3_OUTTKNEPDIS3 = 0x10 + // Position of STSPHSERCVD3 field. + USB_DOEPINT3_STSPHSERCVD3_Pos = 0x5 + // Bit mask of STSPHSERCVD3 field. + USB_DOEPINT3_STSPHSERCVD3_Msk = 0x20 + // Bit STSPHSERCVD3. + USB_DOEPINT3_STSPHSERCVD3 = 0x20 + // Position of BACK2BACKSETUP3 field. + USB_DOEPINT3_BACK2BACKSETUP3_Pos = 0x6 + // Bit mask of BACK2BACKSETUP3 field. + USB_DOEPINT3_BACK2BACKSETUP3_Msk = 0x40 + // Bit BACK2BACKSETUP3. + USB_DOEPINT3_BACK2BACKSETUP3 = 0x40 + // Position of OUTPKTERR3 field. + USB_DOEPINT3_OUTPKTERR3_Pos = 0x8 + // Bit mask of OUTPKTERR3 field. + USB_DOEPINT3_OUTPKTERR3_Msk = 0x100 + // Bit OUTPKTERR3. + USB_DOEPINT3_OUTPKTERR3 = 0x100 + // Position of BNAINTR3 field. + USB_DOEPINT3_BNAINTR3_Pos = 0x9 + // Bit mask of BNAINTR3 field. + USB_DOEPINT3_BNAINTR3_Msk = 0x200 + // Bit BNAINTR3. + USB_DOEPINT3_BNAINTR3 = 0x200 + // Position of PKTDRPSTS3 field. + USB_DOEPINT3_PKTDRPSTS3_Pos = 0xb + // Bit mask of PKTDRPSTS3 field. + USB_DOEPINT3_PKTDRPSTS3_Msk = 0x800 + // Bit PKTDRPSTS3. + USB_DOEPINT3_PKTDRPSTS3 = 0x800 + // Position of BBLEERR3 field. + USB_DOEPINT3_BBLEERR3_Pos = 0xc + // Bit mask of BBLEERR3 field. + USB_DOEPINT3_BBLEERR3_Msk = 0x1000 + // Bit BBLEERR3. + USB_DOEPINT3_BBLEERR3 = 0x1000 + // Position of NAKINTRPT3 field. + USB_DOEPINT3_NAKINTRPT3_Pos = 0xd + // Bit mask of NAKINTRPT3 field. + USB_DOEPINT3_NAKINTRPT3_Msk = 0x2000 + // Bit NAKINTRPT3. + USB_DOEPINT3_NAKINTRPT3 = 0x2000 + // Position of NYEPINTRPT3 field. + USB_DOEPINT3_NYEPINTRPT3_Pos = 0xe + // Bit mask of NYEPINTRPT3 field. + USB_DOEPINT3_NYEPINTRPT3_Msk = 0x4000 + // Bit NYEPINTRPT3. + USB_DOEPINT3_NYEPINTRPT3 = 0x4000 + // Position of STUPPKTRCVD3 field. + USB_DOEPINT3_STUPPKTRCVD3_Pos = 0xf + // Bit mask of STUPPKTRCVD3 field. + USB_DOEPINT3_STUPPKTRCVD3_Msk = 0x8000 + // Bit STUPPKTRCVD3. + USB_DOEPINT3_STUPPKTRCVD3 = 0x8000 + + // DOEPTSIZ3 + // Position of XFERSIZE3 field. + USB_DOEPTSIZ3_XFERSIZE3_Pos = 0x0 + // Bit mask of XFERSIZE3 field. + USB_DOEPTSIZ3_XFERSIZE3_Msk = 0x7f + // Position of PKTCNT3 field. + USB_DOEPTSIZ3_PKTCNT3_Pos = 0x13 + // Bit mask of PKTCNT3 field. + USB_DOEPTSIZ3_PKTCNT3_Msk = 0x80000 + // Bit PKTCNT3. + USB_DOEPTSIZ3_PKTCNT3 = 0x80000 + // Position of SUPCNT3 field. + USB_DOEPTSIZ3_SUPCNT3_Pos = 0x1d + // Bit mask of SUPCNT3 field. + USB_DOEPTSIZ3_SUPCNT3_Msk = 0x60000000 + + // DOEPDMA3 + // Position of DMAADDR3 field. + USB_DOEPDMA3_DMAADDR3_Pos = 0x0 + // Bit mask of DMAADDR3 field. + USB_DOEPDMA3_DMAADDR3_Msk = 0xffffffff + + // DOEPDMAB3 + // Position of DMABUFFERADDR3 field. + USB_DOEPDMAB3_DMABUFFERADDR3_Pos = 0x0 + // Bit mask of DMABUFFERADDR3 field. + USB_DOEPDMAB3_DMABUFFERADDR3_Msk = 0xffffffff + + // DOEPCTL4 + // Position of MPS4 field. + USB_DOEPCTL4_MPS4_Pos = 0x0 + // Bit mask of MPS4 field. + USB_DOEPCTL4_MPS4_Msk = 0x7ff + // Position of USBACTEP4 field. + USB_DOEPCTL4_USBACTEP4_Pos = 0xf + // Bit mask of USBACTEP4 field. + USB_DOEPCTL4_USBACTEP4_Msk = 0x8000 + // Bit USBACTEP4. + USB_DOEPCTL4_USBACTEP4 = 0x8000 + // Position of NAKSTS4 field. + USB_DOEPCTL4_NAKSTS4_Pos = 0x11 + // Bit mask of NAKSTS4 field. + USB_DOEPCTL4_NAKSTS4_Msk = 0x20000 + // Bit NAKSTS4. + USB_DOEPCTL4_NAKSTS4 = 0x20000 + // Position of EPTYPE4 field. + USB_DOEPCTL4_EPTYPE4_Pos = 0x12 + // Bit mask of EPTYPE4 field. + USB_DOEPCTL4_EPTYPE4_Msk = 0xc0000 + // Position of SNP4 field. + USB_DOEPCTL4_SNP4_Pos = 0x14 + // Bit mask of SNP4 field. + USB_DOEPCTL4_SNP4_Msk = 0x100000 + // Bit SNP4. + USB_DOEPCTL4_SNP4 = 0x100000 + // Position of STALL4 field. + USB_DOEPCTL4_STALL4_Pos = 0x15 + // Bit mask of STALL4 field. + USB_DOEPCTL4_STALL4_Msk = 0x200000 + // Bit STALL4. + USB_DOEPCTL4_STALL4 = 0x200000 + // Position of CNAK4 field. + USB_DOEPCTL4_CNAK4_Pos = 0x1a + // Bit mask of CNAK4 field. + USB_DOEPCTL4_CNAK4_Msk = 0x4000000 + // Bit CNAK4. + USB_DOEPCTL4_CNAK4 = 0x4000000 + // Position of DO_SNAK4 field. + USB_DOEPCTL4_DO_SNAK4_Pos = 0x1b + // Bit mask of DO_SNAK4 field. + USB_DOEPCTL4_DO_SNAK4_Msk = 0x8000000 + // Bit DO_SNAK4. + USB_DOEPCTL4_DO_SNAK4 = 0x8000000 + // Position of DO_SETD0PID4 field. + USB_DOEPCTL4_DO_SETD0PID4_Pos = 0x1c + // Bit mask of DO_SETD0PID4 field. + USB_DOEPCTL4_DO_SETD0PID4_Msk = 0x10000000 + // Bit DO_SETD0PID4. + USB_DOEPCTL4_DO_SETD0PID4 = 0x10000000 + // Position of DO_SETD1PID4 field. + USB_DOEPCTL4_DO_SETD1PID4_Pos = 0x1d + // Bit mask of DO_SETD1PID4 field. + USB_DOEPCTL4_DO_SETD1PID4_Msk = 0x20000000 + // Bit DO_SETD1PID4. + USB_DOEPCTL4_DO_SETD1PID4 = 0x20000000 + // Position of EPDIS4 field. + USB_DOEPCTL4_EPDIS4_Pos = 0x1e + // Bit mask of EPDIS4 field. + USB_DOEPCTL4_EPDIS4_Msk = 0x40000000 + // Bit EPDIS4. + USB_DOEPCTL4_EPDIS4 = 0x40000000 + // Position of EPENA4 field. + USB_DOEPCTL4_EPENA4_Pos = 0x1f + // Bit mask of EPENA4 field. + USB_DOEPCTL4_EPENA4_Msk = 0x80000000 + // Bit EPENA4. + USB_DOEPCTL4_EPENA4 = 0x80000000 + + // DOEPINT4 + // Position of XFERCOMPL4 field. + USB_DOEPINT4_XFERCOMPL4_Pos = 0x0 + // Bit mask of XFERCOMPL4 field. + USB_DOEPINT4_XFERCOMPL4_Msk = 0x1 + // Bit XFERCOMPL4. + USB_DOEPINT4_XFERCOMPL4 = 0x1 + // Position of EPDISBLD4 field. + USB_DOEPINT4_EPDISBLD4_Pos = 0x1 + // Bit mask of EPDISBLD4 field. + USB_DOEPINT4_EPDISBLD4_Msk = 0x2 + // Bit EPDISBLD4. + USB_DOEPINT4_EPDISBLD4 = 0x2 + // Position of AHBERR4 field. + USB_DOEPINT4_AHBERR4_Pos = 0x2 + // Bit mask of AHBERR4 field. + USB_DOEPINT4_AHBERR4_Msk = 0x4 + // Bit AHBERR4. + USB_DOEPINT4_AHBERR4 = 0x4 + // Position of SETUP4 field. + USB_DOEPINT4_SETUP4_Pos = 0x3 + // Bit mask of SETUP4 field. + USB_DOEPINT4_SETUP4_Msk = 0x8 + // Bit SETUP4. + USB_DOEPINT4_SETUP4 = 0x8 + // Position of OUTTKNEPDIS4 field. + USB_DOEPINT4_OUTTKNEPDIS4_Pos = 0x4 + // Bit mask of OUTTKNEPDIS4 field. + USB_DOEPINT4_OUTTKNEPDIS4_Msk = 0x10 + // Bit OUTTKNEPDIS4. + USB_DOEPINT4_OUTTKNEPDIS4 = 0x10 + // Position of STSPHSERCVD4 field. + USB_DOEPINT4_STSPHSERCVD4_Pos = 0x5 + // Bit mask of STSPHSERCVD4 field. + USB_DOEPINT4_STSPHSERCVD4_Msk = 0x20 + // Bit STSPHSERCVD4. + USB_DOEPINT4_STSPHSERCVD4 = 0x20 + // Position of BACK2BACKSETUP4 field. + USB_DOEPINT4_BACK2BACKSETUP4_Pos = 0x6 + // Bit mask of BACK2BACKSETUP4 field. + USB_DOEPINT4_BACK2BACKSETUP4_Msk = 0x40 + // Bit BACK2BACKSETUP4. + USB_DOEPINT4_BACK2BACKSETUP4 = 0x40 + // Position of OUTPKTERR4 field. + USB_DOEPINT4_OUTPKTERR4_Pos = 0x8 + // Bit mask of OUTPKTERR4 field. + USB_DOEPINT4_OUTPKTERR4_Msk = 0x100 + // Bit OUTPKTERR4. + USB_DOEPINT4_OUTPKTERR4 = 0x100 + // Position of BNAINTR4 field. + USB_DOEPINT4_BNAINTR4_Pos = 0x9 + // Bit mask of BNAINTR4 field. + USB_DOEPINT4_BNAINTR4_Msk = 0x200 + // Bit BNAINTR4. + USB_DOEPINT4_BNAINTR4 = 0x200 + // Position of PKTDRPSTS4 field. + USB_DOEPINT4_PKTDRPSTS4_Pos = 0xb + // Bit mask of PKTDRPSTS4 field. + USB_DOEPINT4_PKTDRPSTS4_Msk = 0x800 + // Bit PKTDRPSTS4. + USB_DOEPINT4_PKTDRPSTS4 = 0x800 + // Position of BBLEERR4 field. + USB_DOEPINT4_BBLEERR4_Pos = 0xc + // Bit mask of BBLEERR4 field. + USB_DOEPINT4_BBLEERR4_Msk = 0x1000 + // Bit BBLEERR4. + USB_DOEPINT4_BBLEERR4 = 0x1000 + // Position of NAKINTRPT4 field. + USB_DOEPINT4_NAKINTRPT4_Pos = 0xd + // Bit mask of NAKINTRPT4 field. + USB_DOEPINT4_NAKINTRPT4_Msk = 0x2000 + // Bit NAKINTRPT4. + USB_DOEPINT4_NAKINTRPT4 = 0x2000 + // Position of NYEPINTRPT4 field. + USB_DOEPINT4_NYEPINTRPT4_Pos = 0xe + // Bit mask of NYEPINTRPT4 field. + USB_DOEPINT4_NYEPINTRPT4_Msk = 0x4000 + // Bit NYEPINTRPT4. + USB_DOEPINT4_NYEPINTRPT4 = 0x4000 + // Position of STUPPKTRCVD4 field. + USB_DOEPINT4_STUPPKTRCVD4_Pos = 0xf + // Bit mask of STUPPKTRCVD4 field. + USB_DOEPINT4_STUPPKTRCVD4_Msk = 0x8000 + // Bit STUPPKTRCVD4. + USB_DOEPINT4_STUPPKTRCVD4 = 0x8000 + + // DOEPTSIZ4 + // Position of XFERSIZE4 field. + USB_DOEPTSIZ4_XFERSIZE4_Pos = 0x0 + // Bit mask of XFERSIZE4 field. + USB_DOEPTSIZ4_XFERSIZE4_Msk = 0x7f + // Position of PKTCNT4 field. + USB_DOEPTSIZ4_PKTCNT4_Pos = 0x13 + // Bit mask of PKTCNT4 field. + USB_DOEPTSIZ4_PKTCNT4_Msk = 0x80000 + // Bit PKTCNT4. + USB_DOEPTSIZ4_PKTCNT4 = 0x80000 + // Position of SUPCNT4 field. + USB_DOEPTSIZ4_SUPCNT4_Pos = 0x1d + // Bit mask of SUPCNT4 field. + USB_DOEPTSIZ4_SUPCNT4_Msk = 0x60000000 + + // DOEPDMA4 + // Position of DMAADDR4 field. + USB_DOEPDMA4_DMAADDR4_Pos = 0x0 + // Bit mask of DMAADDR4 field. + USB_DOEPDMA4_DMAADDR4_Msk = 0xffffffff + + // DOEPDMAB4 + // Position of DMABUFFERADDR4 field. + USB_DOEPDMAB4_DMABUFFERADDR4_Pos = 0x0 + // Bit mask of DMABUFFERADDR4 field. + USB_DOEPDMAB4_DMABUFFERADDR4_Msk = 0xffffffff + + // DOEPCTL5 + // Position of MPS5 field. + USB_DOEPCTL5_MPS5_Pos = 0x0 + // Bit mask of MPS5 field. + USB_DOEPCTL5_MPS5_Msk = 0x7ff + // Position of USBACTEP5 field. + USB_DOEPCTL5_USBACTEP5_Pos = 0xf + // Bit mask of USBACTEP5 field. + USB_DOEPCTL5_USBACTEP5_Msk = 0x8000 + // Bit USBACTEP5. + USB_DOEPCTL5_USBACTEP5 = 0x8000 + // Position of NAKSTS5 field. + USB_DOEPCTL5_NAKSTS5_Pos = 0x11 + // Bit mask of NAKSTS5 field. + USB_DOEPCTL5_NAKSTS5_Msk = 0x20000 + // Bit NAKSTS5. + USB_DOEPCTL5_NAKSTS5 = 0x20000 + // Position of EPTYPE5 field. + USB_DOEPCTL5_EPTYPE5_Pos = 0x12 + // Bit mask of EPTYPE5 field. + USB_DOEPCTL5_EPTYPE5_Msk = 0xc0000 + // Position of SNP5 field. + USB_DOEPCTL5_SNP5_Pos = 0x14 + // Bit mask of SNP5 field. + USB_DOEPCTL5_SNP5_Msk = 0x100000 + // Bit SNP5. + USB_DOEPCTL5_SNP5 = 0x100000 + // Position of STALL5 field. + USB_DOEPCTL5_STALL5_Pos = 0x15 + // Bit mask of STALL5 field. + USB_DOEPCTL5_STALL5_Msk = 0x200000 + // Bit STALL5. + USB_DOEPCTL5_STALL5 = 0x200000 + // Position of CNAK5 field. + USB_DOEPCTL5_CNAK5_Pos = 0x1a + // Bit mask of CNAK5 field. + USB_DOEPCTL5_CNAK5_Msk = 0x4000000 + // Bit CNAK5. + USB_DOEPCTL5_CNAK5 = 0x4000000 + // Position of DO_SNAK5 field. + USB_DOEPCTL5_DO_SNAK5_Pos = 0x1b + // Bit mask of DO_SNAK5 field. + USB_DOEPCTL5_DO_SNAK5_Msk = 0x8000000 + // Bit DO_SNAK5. + USB_DOEPCTL5_DO_SNAK5 = 0x8000000 + // Position of DO_SETD0PID5 field. + USB_DOEPCTL5_DO_SETD0PID5_Pos = 0x1c + // Bit mask of DO_SETD0PID5 field. + USB_DOEPCTL5_DO_SETD0PID5_Msk = 0x10000000 + // Bit DO_SETD0PID5. + USB_DOEPCTL5_DO_SETD0PID5 = 0x10000000 + // Position of DO_SETD1PID5 field. + USB_DOEPCTL5_DO_SETD1PID5_Pos = 0x1d + // Bit mask of DO_SETD1PID5 field. + USB_DOEPCTL5_DO_SETD1PID5_Msk = 0x20000000 + // Bit DO_SETD1PID5. + USB_DOEPCTL5_DO_SETD1PID5 = 0x20000000 + // Position of EPDIS5 field. + USB_DOEPCTL5_EPDIS5_Pos = 0x1e + // Bit mask of EPDIS5 field. + USB_DOEPCTL5_EPDIS5_Msk = 0x40000000 + // Bit EPDIS5. + USB_DOEPCTL5_EPDIS5 = 0x40000000 + // Position of EPENA5 field. + USB_DOEPCTL5_EPENA5_Pos = 0x1f + // Bit mask of EPENA5 field. + USB_DOEPCTL5_EPENA5_Msk = 0x80000000 + // Bit EPENA5. + USB_DOEPCTL5_EPENA5 = 0x80000000 + + // DOEPINT5 + // Position of XFERCOMPL5 field. + USB_DOEPINT5_XFERCOMPL5_Pos = 0x0 + // Bit mask of XFERCOMPL5 field. + USB_DOEPINT5_XFERCOMPL5_Msk = 0x1 + // Bit XFERCOMPL5. + USB_DOEPINT5_XFERCOMPL5 = 0x1 + // Position of EPDISBLD5 field. + USB_DOEPINT5_EPDISBLD5_Pos = 0x1 + // Bit mask of EPDISBLD5 field. + USB_DOEPINT5_EPDISBLD5_Msk = 0x2 + // Bit EPDISBLD5. + USB_DOEPINT5_EPDISBLD5 = 0x2 + // Position of AHBERR5 field. + USB_DOEPINT5_AHBERR5_Pos = 0x2 + // Bit mask of AHBERR5 field. + USB_DOEPINT5_AHBERR5_Msk = 0x4 + // Bit AHBERR5. + USB_DOEPINT5_AHBERR5 = 0x4 + // Position of SETUP5 field. + USB_DOEPINT5_SETUP5_Pos = 0x3 + // Bit mask of SETUP5 field. + USB_DOEPINT5_SETUP5_Msk = 0x8 + // Bit SETUP5. + USB_DOEPINT5_SETUP5 = 0x8 + // Position of OUTTKNEPDIS5 field. + USB_DOEPINT5_OUTTKNEPDIS5_Pos = 0x4 + // Bit mask of OUTTKNEPDIS5 field. + USB_DOEPINT5_OUTTKNEPDIS5_Msk = 0x10 + // Bit OUTTKNEPDIS5. + USB_DOEPINT5_OUTTKNEPDIS5 = 0x10 + // Position of STSPHSERCVD5 field. + USB_DOEPINT5_STSPHSERCVD5_Pos = 0x5 + // Bit mask of STSPHSERCVD5 field. + USB_DOEPINT5_STSPHSERCVD5_Msk = 0x20 + // Bit STSPHSERCVD5. + USB_DOEPINT5_STSPHSERCVD5 = 0x20 + // Position of BACK2BACKSETUP5 field. + USB_DOEPINT5_BACK2BACKSETUP5_Pos = 0x6 + // Bit mask of BACK2BACKSETUP5 field. + USB_DOEPINT5_BACK2BACKSETUP5_Msk = 0x40 + // Bit BACK2BACKSETUP5. + USB_DOEPINT5_BACK2BACKSETUP5 = 0x40 + // Position of OUTPKTERR5 field. + USB_DOEPINT5_OUTPKTERR5_Pos = 0x8 + // Bit mask of OUTPKTERR5 field. + USB_DOEPINT5_OUTPKTERR5_Msk = 0x100 + // Bit OUTPKTERR5. + USB_DOEPINT5_OUTPKTERR5 = 0x100 + // Position of BNAINTR5 field. + USB_DOEPINT5_BNAINTR5_Pos = 0x9 + // Bit mask of BNAINTR5 field. + USB_DOEPINT5_BNAINTR5_Msk = 0x200 + // Bit BNAINTR5. + USB_DOEPINT5_BNAINTR5 = 0x200 + // Position of PKTDRPSTS5 field. + USB_DOEPINT5_PKTDRPSTS5_Pos = 0xb + // Bit mask of PKTDRPSTS5 field. + USB_DOEPINT5_PKTDRPSTS5_Msk = 0x800 + // Bit PKTDRPSTS5. + USB_DOEPINT5_PKTDRPSTS5 = 0x800 + // Position of BBLEERR5 field. + USB_DOEPINT5_BBLEERR5_Pos = 0xc + // Bit mask of BBLEERR5 field. + USB_DOEPINT5_BBLEERR5_Msk = 0x1000 + // Bit BBLEERR5. + USB_DOEPINT5_BBLEERR5 = 0x1000 + // Position of NAKINTRPT5 field. + USB_DOEPINT5_NAKINTRPT5_Pos = 0xd + // Bit mask of NAKINTRPT5 field. + USB_DOEPINT5_NAKINTRPT5_Msk = 0x2000 + // Bit NAKINTRPT5. + USB_DOEPINT5_NAKINTRPT5 = 0x2000 + // Position of NYEPINTRPT5 field. + USB_DOEPINT5_NYEPINTRPT5_Pos = 0xe + // Bit mask of NYEPINTRPT5 field. + USB_DOEPINT5_NYEPINTRPT5_Msk = 0x4000 + // Bit NYEPINTRPT5. + USB_DOEPINT5_NYEPINTRPT5 = 0x4000 + // Position of STUPPKTRCVD5 field. + USB_DOEPINT5_STUPPKTRCVD5_Pos = 0xf + // Bit mask of STUPPKTRCVD5 field. + USB_DOEPINT5_STUPPKTRCVD5_Msk = 0x8000 + // Bit STUPPKTRCVD5. + USB_DOEPINT5_STUPPKTRCVD5 = 0x8000 + + // DOEPTSIZ5 + // Position of XFERSIZE5 field. + USB_DOEPTSIZ5_XFERSIZE5_Pos = 0x0 + // Bit mask of XFERSIZE5 field. + USB_DOEPTSIZ5_XFERSIZE5_Msk = 0x7f + // Position of PKTCNT5 field. + USB_DOEPTSIZ5_PKTCNT5_Pos = 0x13 + // Bit mask of PKTCNT5 field. + USB_DOEPTSIZ5_PKTCNT5_Msk = 0x80000 + // Bit PKTCNT5. + USB_DOEPTSIZ5_PKTCNT5 = 0x80000 + // Position of SUPCNT5 field. + USB_DOEPTSIZ5_SUPCNT5_Pos = 0x1d + // Bit mask of SUPCNT5 field. + USB_DOEPTSIZ5_SUPCNT5_Msk = 0x60000000 + + // DOEPDMA5 + // Position of DMAADDR5 field. + USB_DOEPDMA5_DMAADDR5_Pos = 0x0 + // Bit mask of DMAADDR5 field. + USB_DOEPDMA5_DMAADDR5_Msk = 0xffffffff + + // DOEPDMAB5 + // Position of DMABUFFERADDR5 field. + USB_DOEPDMAB5_DMABUFFERADDR5_Pos = 0x0 + // Bit mask of DMABUFFERADDR5 field. + USB_DOEPDMAB5_DMABUFFERADDR5_Msk = 0xffffffff + + // DOEPCTL6 + // Position of MPS6 field. + USB_DOEPCTL6_MPS6_Pos = 0x0 + // Bit mask of MPS6 field. + USB_DOEPCTL6_MPS6_Msk = 0x7ff + // Position of USBACTEP6 field. + USB_DOEPCTL6_USBACTEP6_Pos = 0xf + // Bit mask of USBACTEP6 field. + USB_DOEPCTL6_USBACTEP6_Msk = 0x8000 + // Bit USBACTEP6. + USB_DOEPCTL6_USBACTEP6 = 0x8000 + // Position of NAKSTS6 field. + USB_DOEPCTL6_NAKSTS6_Pos = 0x11 + // Bit mask of NAKSTS6 field. + USB_DOEPCTL6_NAKSTS6_Msk = 0x20000 + // Bit NAKSTS6. + USB_DOEPCTL6_NAKSTS6 = 0x20000 + // Position of EPTYPE6 field. + USB_DOEPCTL6_EPTYPE6_Pos = 0x12 + // Bit mask of EPTYPE6 field. + USB_DOEPCTL6_EPTYPE6_Msk = 0xc0000 + // Position of SNP6 field. + USB_DOEPCTL6_SNP6_Pos = 0x14 + // Bit mask of SNP6 field. + USB_DOEPCTL6_SNP6_Msk = 0x100000 + // Bit SNP6. + USB_DOEPCTL6_SNP6 = 0x100000 + // Position of STALL6 field. + USB_DOEPCTL6_STALL6_Pos = 0x15 + // Bit mask of STALL6 field. + USB_DOEPCTL6_STALL6_Msk = 0x200000 + // Bit STALL6. + USB_DOEPCTL6_STALL6 = 0x200000 + // Position of CNAK6 field. + USB_DOEPCTL6_CNAK6_Pos = 0x1a + // Bit mask of CNAK6 field. + USB_DOEPCTL6_CNAK6_Msk = 0x4000000 + // Bit CNAK6. + USB_DOEPCTL6_CNAK6 = 0x4000000 + // Position of DO_SNAK6 field. + USB_DOEPCTL6_DO_SNAK6_Pos = 0x1b + // Bit mask of DO_SNAK6 field. + USB_DOEPCTL6_DO_SNAK6_Msk = 0x8000000 + // Bit DO_SNAK6. + USB_DOEPCTL6_DO_SNAK6 = 0x8000000 + // Position of DO_SETD0PID6 field. + USB_DOEPCTL6_DO_SETD0PID6_Pos = 0x1c + // Bit mask of DO_SETD0PID6 field. + USB_DOEPCTL6_DO_SETD0PID6_Msk = 0x10000000 + // Bit DO_SETD0PID6. + USB_DOEPCTL6_DO_SETD0PID6 = 0x10000000 + // Position of DO_SETD1PID6 field. + USB_DOEPCTL6_DO_SETD1PID6_Pos = 0x1d + // Bit mask of DO_SETD1PID6 field. + USB_DOEPCTL6_DO_SETD1PID6_Msk = 0x20000000 + // Bit DO_SETD1PID6. + USB_DOEPCTL6_DO_SETD1PID6 = 0x20000000 + // Position of EPDIS6 field. + USB_DOEPCTL6_EPDIS6_Pos = 0x1e + // Bit mask of EPDIS6 field. + USB_DOEPCTL6_EPDIS6_Msk = 0x40000000 + // Bit EPDIS6. + USB_DOEPCTL6_EPDIS6 = 0x40000000 + // Position of EPENA6 field. + USB_DOEPCTL6_EPENA6_Pos = 0x1f + // Bit mask of EPENA6 field. + USB_DOEPCTL6_EPENA6_Msk = 0x80000000 + // Bit EPENA6. + USB_DOEPCTL6_EPENA6 = 0x80000000 + + // DOEPINT6 + // Position of XFERCOMPL6 field. + USB_DOEPINT6_XFERCOMPL6_Pos = 0x0 + // Bit mask of XFERCOMPL6 field. + USB_DOEPINT6_XFERCOMPL6_Msk = 0x1 + // Bit XFERCOMPL6. + USB_DOEPINT6_XFERCOMPL6 = 0x1 + // Position of EPDISBLD6 field. + USB_DOEPINT6_EPDISBLD6_Pos = 0x1 + // Bit mask of EPDISBLD6 field. + USB_DOEPINT6_EPDISBLD6_Msk = 0x2 + // Bit EPDISBLD6. + USB_DOEPINT6_EPDISBLD6 = 0x2 + // Position of AHBERR6 field. + USB_DOEPINT6_AHBERR6_Pos = 0x2 + // Bit mask of AHBERR6 field. + USB_DOEPINT6_AHBERR6_Msk = 0x4 + // Bit AHBERR6. + USB_DOEPINT6_AHBERR6 = 0x4 + // Position of SETUP6 field. + USB_DOEPINT6_SETUP6_Pos = 0x3 + // Bit mask of SETUP6 field. + USB_DOEPINT6_SETUP6_Msk = 0x8 + // Bit SETUP6. + USB_DOEPINT6_SETUP6 = 0x8 + // Position of OUTTKNEPDIS6 field. + USB_DOEPINT6_OUTTKNEPDIS6_Pos = 0x4 + // Bit mask of OUTTKNEPDIS6 field. + USB_DOEPINT6_OUTTKNEPDIS6_Msk = 0x10 + // Bit OUTTKNEPDIS6. + USB_DOEPINT6_OUTTKNEPDIS6 = 0x10 + // Position of STSPHSERCVD6 field. + USB_DOEPINT6_STSPHSERCVD6_Pos = 0x5 + // Bit mask of STSPHSERCVD6 field. + USB_DOEPINT6_STSPHSERCVD6_Msk = 0x20 + // Bit STSPHSERCVD6. + USB_DOEPINT6_STSPHSERCVD6 = 0x20 + // Position of BACK2BACKSETUP6 field. + USB_DOEPINT6_BACK2BACKSETUP6_Pos = 0x6 + // Bit mask of BACK2BACKSETUP6 field. + USB_DOEPINT6_BACK2BACKSETUP6_Msk = 0x40 + // Bit BACK2BACKSETUP6. + USB_DOEPINT6_BACK2BACKSETUP6 = 0x40 + // Position of OUTPKTERR6 field. + USB_DOEPINT6_OUTPKTERR6_Pos = 0x8 + // Bit mask of OUTPKTERR6 field. + USB_DOEPINT6_OUTPKTERR6_Msk = 0x100 + // Bit OUTPKTERR6. + USB_DOEPINT6_OUTPKTERR6 = 0x100 + // Position of BNAINTR6 field. + USB_DOEPINT6_BNAINTR6_Pos = 0x9 + // Bit mask of BNAINTR6 field. + USB_DOEPINT6_BNAINTR6_Msk = 0x200 + // Bit BNAINTR6. + USB_DOEPINT6_BNAINTR6 = 0x200 + // Position of PKTDRPSTS6 field. + USB_DOEPINT6_PKTDRPSTS6_Pos = 0xb + // Bit mask of PKTDRPSTS6 field. + USB_DOEPINT6_PKTDRPSTS6_Msk = 0x800 + // Bit PKTDRPSTS6. + USB_DOEPINT6_PKTDRPSTS6 = 0x800 + // Position of BBLEERR6 field. + USB_DOEPINT6_BBLEERR6_Pos = 0xc + // Bit mask of BBLEERR6 field. + USB_DOEPINT6_BBLEERR6_Msk = 0x1000 + // Bit BBLEERR6. + USB_DOEPINT6_BBLEERR6 = 0x1000 + // Position of NAKINTRPT6 field. + USB_DOEPINT6_NAKINTRPT6_Pos = 0xd + // Bit mask of NAKINTRPT6 field. + USB_DOEPINT6_NAKINTRPT6_Msk = 0x2000 + // Bit NAKINTRPT6. + USB_DOEPINT6_NAKINTRPT6 = 0x2000 + // Position of NYEPINTRPT6 field. + USB_DOEPINT6_NYEPINTRPT6_Pos = 0xe + // Bit mask of NYEPINTRPT6 field. + USB_DOEPINT6_NYEPINTRPT6_Msk = 0x4000 + // Bit NYEPINTRPT6. + USB_DOEPINT6_NYEPINTRPT6 = 0x4000 + // Position of STUPPKTRCVD6 field. + USB_DOEPINT6_STUPPKTRCVD6_Pos = 0xf + // Bit mask of STUPPKTRCVD6 field. + USB_DOEPINT6_STUPPKTRCVD6_Msk = 0x8000 + // Bit STUPPKTRCVD6. + USB_DOEPINT6_STUPPKTRCVD6 = 0x8000 + + // DOEPTSIZ6 + // Position of XFERSIZE6 field. + USB_DOEPTSIZ6_XFERSIZE6_Pos = 0x0 + // Bit mask of XFERSIZE6 field. + USB_DOEPTSIZ6_XFERSIZE6_Msk = 0x7f + // Position of PKTCNT6 field. + USB_DOEPTSIZ6_PKTCNT6_Pos = 0x13 + // Bit mask of PKTCNT6 field. + USB_DOEPTSIZ6_PKTCNT6_Msk = 0x80000 + // Bit PKTCNT6. + USB_DOEPTSIZ6_PKTCNT6 = 0x80000 + // Position of SUPCNT6 field. + USB_DOEPTSIZ6_SUPCNT6_Pos = 0x1d + // Bit mask of SUPCNT6 field. + USB_DOEPTSIZ6_SUPCNT6_Msk = 0x60000000 + + // DOEPDMA6 + // Position of DMAADDR6 field. + USB_DOEPDMA6_DMAADDR6_Pos = 0x0 + // Bit mask of DMAADDR6 field. + USB_DOEPDMA6_DMAADDR6_Msk = 0xffffffff + + // DOEPDMAB6 + // Position of DMABUFFERADDR6 field. + USB_DOEPDMAB6_DMABUFFERADDR6_Pos = 0x0 + // Bit mask of DMABUFFERADDR6 field. + USB_DOEPDMAB6_DMABUFFERADDR6_Msk = 0xffffffff + + // PCGCCTL + // Position of STOPPCLK field. + USB_PCGCCTL_STOPPCLK_Pos = 0x0 + // Bit mask of STOPPCLK field. + USB_PCGCCTL_STOPPCLK_Msk = 0x1 + // Bit STOPPCLK. + USB_PCGCCTL_STOPPCLK = 0x1 + // Position of GATEHCLK field. + USB_PCGCCTL_GATEHCLK_Pos = 0x1 + // Bit mask of GATEHCLK field. + USB_PCGCCTL_GATEHCLK_Msk = 0x2 + // Bit GATEHCLK. + USB_PCGCCTL_GATEHCLK = 0x2 + // Position of PWRCLMP field. + USB_PCGCCTL_PWRCLMP_Pos = 0x2 + // Bit mask of PWRCLMP field. + USB_PCGCCTL_PWRCLMP_Msk = 0x4 + // Bit PWRCLMP. + USB_PCGCCTL_PWRCLMP = 0x4 + // Position of RSTPDWNMODULE field. + USB_PCGCCTL_RSTPDWNMODULE_Pos = 0x3 + // Bit mask of RSTPDWNMODULE field. + USB_PCGCCTL_RSTPDWNMODULE_Msk = 0x8 + // Bit RSTPDWNMODULE. + USB_PCGCCTL_RSTPDWNMODULE = 0x8 + // Position of PHYSLEEP field. + USB_PCGCCTL_PHYSLEEP_Pos = 0x6 + // Bit mask of PHYSLEEP field. + USB_PCGCCTL_PHYSLEEP_Msk = 0x40 + // Bit PHYSLEEP. + USB_PCGCCTL_PHYSLEEP = 0x40 + // Position of L1SUSPENDED field. + USB_PCGCCTL_L1SUSPENDED_Pos = 0x7 + // Bit mask of L1SUSPENDED field. + USB_PCGCCTL_L1SUSPENDED_Msk = 0x80 + // Bit L1SUSPENDED. + USB_PCGCCTL_L1SUSPENDED = 0x80 + // Position of RESETAFTERSUSP field. + USB_PCGCCTL_RESETAFTERSUSP_Pos = 0x8 + // Bit mask of RESETAFTERSUSP field. + USB_PCGCCTL_RESETAFTERSUSP_Msk = 0x100 + // Bit RESETAFTERSUSP. + USB_PCGCCTL_RESETAFTERSUSP = 0x100 +) + +// Constants for USB_DEVICE: Full-speed USB Serial/JTAG Controller +const ( + // EP1: Endpoint 1 FIFO register + // Position of RDWR_BYTE field. + USB_DEVICE_EP1_RDWR_BYTE_Pos = 0x0 + // Bit mask of RDWR_BYTE field. + USB_DEVICE_EP1_RDWR_BYTE_Msk = 0xff + + // EP1_CONF: Endpoint 1 configure and status register + // Position of WR_DONE field. + USB_DEVICE_EP1_CONF_WR_DONE_Pos = 0x0 + // Bit mask of WR_DONE field. + USB_DEVICE_EP1_CONF_WR_DONE_Msk = 0x1 + // Bit WR_DONE. + USB_DEVICE_EP1_CONF_WR_DONE = 0x1 + // Position of SERIAL_IN_EP_DATA_FREE field. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE_Pos = 0x1 + // Bit mask of SERIAL_IN_EP_DATA_FREE field. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE_Msk = 0x2 + // Bit SERIAL_IN_EP_DATA_FREE. + USB_DEVICE_EP1_CONF_SERIAL_IN_EP_DATA_FREE = 0x2 + // Position of SERIAL_OUT_EP_DATA_AVAIL field. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL_Pos = 0x2 + // Bit mask of SERIAL_OUT_EP_DATA_AVAIL field. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL_Msk = 0x4 + // Bit SERIAL_OUT_EP_DATA_AVAIL. + USB_DEVICE_EP1_CONF_SERIAL_OUT_EP_DATA_AVAIL = 0x4 + + // INT_RAW: Raw status interrupt + // Position of JTAG_IN_FLUSH_INT_RAW field. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_RAW field. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_RAW. + USB_DEVICE_INT_RAW_JTAG_IN_FLUSH_INT_RAW = 0x1 + // Position of SOF_INT_RAW field. + USB_DEVICE_INT_RAW_SOF_INT_RAW_Pos = 0x1 + // Bit mask of SOF_INT_RAW field. + USB_DEVICE_INT_RAW_SOF_INT_RAW_Msk = 0x2 + // Bit SOF_INT_RAW. + USB_DEVICE_INT_RAW_SOF_INT_RAW = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_RAW. + USB_DEVICE_INT_RAW_SERIAL_OUT_RECV_PKT_INT_RAW = 0x4 + // Position of SERIAL_IN_EMPTY_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_RAW field. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_RAW. + USB_DEVICE_INT_RAW_SERIAL_IN_EMPTY_INT_RAW = 0x8 + // Position of PID_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW_Pos = 0x4 + // Bit mask of PID_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW_Msk = 0x10 + // Bit PID_ERR_INT_RAW. + USB_DEVICE_INT_RAW_PID_ERR_INT_RAW = 0x10 + // Position of CRC5_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW_Msk = 0x20 + // Bit CRC5_ERR_INT_RAW. + USB_DEVICE_INT_RAW_CRC5_ERR_INT_RAW = 0x20 + // Position of CRC16_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW_Msk = 0x40 + // Bit CRC16_ERR_INT_RAW. + USB_DEVICE_INT_RAW_CRC16_ERR_INT_RAW = 0x40 + // Position of STUFF_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_RAW field. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW_Msk = 0x80 + // Bit STUFF_ERR_INT_RAW. + USB_DEVICE_INT_RAW_STUFF_ERR_INT_RAW = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_RAW field. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_RAW field. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_RAW. + USB_DEVICE_INT_RAW_IN_TOKEN_REC_IN_EP1_INT_RAW = 0x100 + // Position of USB_BUS_RESET_INT_RAW field. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_RAW field. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW_Msk = 0x200 + // Bit USB_BUS_RESET_INT_RAW. + USB_DEVICE_INT_RAW_USB_BUS_RESET_INT_RAW = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_RAW. + USB_DEVICE_INT_RAW_OUT_EP1_ZERO_PAYLOAD_INT_RAW = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_RAW field. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_RAW. + USB_DEVICE_INT_RAW_OUT_EP2_ZERO_PAYLOAD_INT_RAW = 0x800 + + // INT_ST: Masked interrupt + // Position of JTAG_IN_FLUSH_INT_ST field. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_ST field. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_ST. + USB_DEVICE_INT_ST_JTAG_IN_FLUSH_INT_ST = 0x1 + // Position of SOF_INT_ST field. + USB_DEVICE_INT_ST_SOF_INT_ST_Pos = 0x1 + // Bit mask of SOF_INT_ST field. + USB_DEVICE_INT_ST_SOF_INT_ST_Msk = 0x2 + // Bit SOF_INT_ST. + USB_DEVICE_INT_ST_SOF_INT_ST = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_ST. + USB_DEVICE_INT_ST_SERIAL_OUT_RECV_PKT_INT_ST = 0x4 + // Position of SERIAL_IN_EMPTY_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_ST field. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_ST. + USB_DEVICE_INT_ST_SERIAL_IN_EMPTY_INT_ST = 0x8 + // Position of PID_ERR_INT_ST field. + USB_DEVICE_INT_ST_PID_ERR_INT_ST_Pos = 0x4 + // Bit mask of PID_ERR_INT_ST field. + USB_DEVICE_INT_ST_PID_ERR_INT_ST_Msk = 0x10 + // Bit PID_ERR_INT_ST. + USB_DEVICE_INT_ST_PID_ERR_INT_ST = 0x10 + // Position of CRC5_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST_Msk = 0x20 + // Bit CRC5_ERR_INT_ST. + USB_DEVICE_INT_ST_CRC5_ERR_INT_ST = 0x20 + // Position of CRC16_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_ST field. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST_Msk = 0x40 + // Bit CRC16_ERR_INT_ST. + USB_DEVICE_INT_ST_CRC16_ERR_INT_ST = 0x40 + // Position of STUFF_ERR_INT_ST field. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_ST field. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST_Msk = 0x80 + // Bit STUFF_ERR_INT_ST. + USB_DEVICE_INT_ST_STUFF_ERR_INT_ST = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_ST field. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_ST field. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_ST. + USB_DEVICE_INT_ST_IN_TOKEN_REC_IN_EP1_INT_ST = 0x100 + // Position of USB_BUS_RESET_INT_ST field. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_ST field. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST_Msk = 0x200 + // Bit USB_BUS_RESET_INT_ST. + USB_DEVICE_INT_ST_USB_BUS_RESET_INT_ST = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_ST. + USB_DEVICE_INT_ST_OUT_EP1_ZERO_PAYLOAD_INT_ST = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_ST field. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_ST. + USB_DEVICE_INT_ST_OUT_EP2_ZERO_PAYLOAD_INT_ST = 0x800 + + // INT_ENA: Interrupt enable bits + // Position of JTAG_IN_FLUSH_INT_ENA field. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_ENA field. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_ENA. + USB_DEVICE_INT_ENA_JTAG_IN_FLUSH_INT_ENA = 0x1 + // Position of SOF_INT_ENA field. + USB_DEVICE_INT_ENA_SOF_INT_ENA_Pos = 0x1 + // Bit mask of SOF_INT_ENA field. + USB_DEVICE_INT_ENA_SOF_INT_ENA_Msk = 0x2 + // Bit SOF_INT_ENA. + USB_DEVICE_INT_ENA_SOF_INT_ENA = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_ENA. + USB_DEVICE_INT_ENA_SERIAL_OUT_RECV_PKT_INT_ENA = 0x4 + // Position of SERIAL_IN_EMPTY_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_ENA field. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_ENA. + USB_DEVICE_INT_ENA_SERIAL_IN_EMPTY_INT_ENA = 0x8 + // Position of PID_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA_Pos = 0x4 + // Bit mask of PID_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA_Msk = 0x10 + // Bit PID_ERR_INT_ENA. + USB_DEVICE_INT_ENA_PID_ERR_INT_ENA = 0x10 + // Position of CRC5_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA_Msk = 0x20 + // Bit CRC5_ERR_INT_ENA. + USB_DEVICE_INT_ENA_CRC5_ERR_INT_ENA = 0x20 + // Position of CRC16_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA_Msk = 0x40 + // Bit CRC16_ERR_INT_ENA. + USB_DEVICE_INT_ENA_CRC16_ERR_INT_ENA = 0x40 + // Position of STUFF_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_ENA field. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA_Msk = 0x80 + // Bit STUFF_ERR_INT_ENA. + USB_DEVICE_INT_ENA_STUFF_ERR_INT_ENA = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_ENA field. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_ENA field. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_ENA. + USB_DEVICE_INT_ENA_IN_TOKEN_REC_IN_EP1_INT_ENA = 0x100 + // Position of USB_BUS_RESET_INT_ENA field. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_ENA field. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA_Msk = 0x200 + // Bit USB_BUS_RESET_INT_ENA. + USB_DEVICE_INT_ENA_USB_BUS_RESET_INT_ENA = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_ENA. + USB_DEVICE_INT_ENA_OUT_EP1_ZERO_PAYLOAD_INT_ENA = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_ENA field. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_ENA. + USB_DEVICE_INT_ENA_OUT_EP2_ZERO_PAYLOAD_INT_ENA = 0x800 + + // INT_CLR: Interrupt clear bits + // Position of JTAG_IN_FLUSH_INT_CLR field. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR_Pos = 0x0 + // Bit mask of JTAG_IN_FLUSH_INT_CLR field. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR_Msk = 0x1 + // Bit JTAG_IN_FLUSH_INT_CLR. + USB_DEVICE_INT_CLR_JTAG_IN_FLUSH_INT_CLR = 0x1 + // Position of SOF_INT_CLR field. + USB_DEVICE_INT_CLR_SOF_INT_CLR_Pos = 0x1 + // Bit mask of SOF_INT_CLR field. + USB_DEVICE_INT_CLR_SOF_INT_CLR_Msk = 0x2 + // Bit SOF_INT_CLR. + USB_DEVICE_INT_CLR_SOF_INT_CLR = 0x2 + // Position of SERIAL_OUT_RECV_PKT_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR_Pos = 0x2 + // Bit mask of SERIAL_OUT_RECV_PKT_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR_Msk = 0x4 + // Bit SERIAL_OUT_RECV_PKT_INT_CLR. + USB_DEVICE_INT_CLR_SERIAL_OUT_RECV_PKT_INT_CLR = 0x4 + // Position of SERIAL_IN_EMPTY_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR_Pos = 0x3 + // Bit mask of SERIAL_IN_EMPTY_INT_CLR field. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR_Msk = 0x8 + // Bit SERIAL_IN_EMPTY_INT_CLR. + USB_DEVICE_INT_CLR_SERIAL_IN_EMPTY_INT_CLR = 0x8 + // Position of PID_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR_Pos = 0x4 + // Bit mask of PID_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR_Msk = 0x10 + // Bit PID_ERR_INT_CLR. + USB_DEVICE_INT_CLR_PID_ERR_INT_CLR = 0x10 + // Position of CRC5_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR_Pos = 0x5 + // Bit mask of CRC5_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR_Msk = 0x20 + // Bit CRC5_ERR_INT_CLR. + USB_DEVICE_INT_CLR_CRC5_ERR_INT_CLR = 0x20 + // Position of CRC16_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR_Pos = 0x6 + // Bit mask of CRC16_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR_Msk = 0x40 + // Bit CRC16_ERR_INT_CLR. + USB_DEVICE_INT_CLR_CRC16_ERR_INT_CLR = 0x40 + // Position of STUFF_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR_Pos = 0x7 + // Bit mask of STUFF_ERR_INT_CLR field. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR_Msk = 0x80 + // Bit STUFF_ERR_INT_CLR. + USB_DEVICE_INT_CLR_STUFF_ERR_INT_CLR = 0x80 + // Position of IN_TOKEN_REC_IN_EP1_INT_CLR field. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR_Pos = 0x8 + // Bit mask of IN_TOKEN_REC_IN_EP1_INT_CLR field. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR_Msk = 0x100 + // Bit IN_TOKEN_REC_IN_EP1_INT_CLR. + USB_DEVICE_INT_CLR_IN_TOKEN_REC_IN_EP1_INT_CLR = 0x100 + // Position of USB_BUS_RESET_INT_CLR field. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR_Pos = 0x9 + // Bit mask of USB_BUS_RESET_INT_CLR field. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR_Msk = 0x200 + // Bit USB_BUS_RESET_INT_CLR. + USB_DEVICE_INT_CLR_USB_BUS_RESET_INT_CLR = 0x200 + // Position of OUT_EP1_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Pos = 0xa + // Bit mask of OUT_EP1_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Msk = 0x400 + // Bit OUT_EP1_ZERO_PAYLOAD_INT_CLR. + USB_DEVICE_INT_CLR_OUT_EP1_ZERO_PAYLOAD_INT_CLR = 0x400 + // Position of OUT_EP2_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Pos = 0xb + // Bit mask of OUT_EP2_ZERO_PAYLOAD_INT_CLR field. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Msk = 0x800 + // Bit OUT_EP2_ZERO_PAYLOAD_INT_CLR. + USB_DEVICE_INT_CLR_OUT_EP2_ZERO_PAYLOAD_INT_CLR = 0x800 + + // CONF0: Configure 0 register + // Position of PHY_SEL field. + USB_DEVICE_CONF0_PHY_SEL_Pos = 0x0 + // Bit mask of PHY_SEL field. + USB_DEVICE_CONF0_PHY_SEL_Msk = 0x1 + // Bit PHY_SEL. + USB_DEVICE_CONF0_PHY_SEL = 0x1 + // Position of EXCHG_PINS_OVERRIDE field. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE_Pos = 0x1 + // Bit mask of EXCHG_PINS_OVERRIDE field. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE_Msk = 0x2 + // Bit EXCHG_PINS_OVERRIDE. + USB_DEVICE_CONF0_EXCHG_PINS_OVERRIDE = 0x2 + // Position of EXCHG_PINS field. + USB_DEVICE_CONF0_EXCHG_PINS_Pos = 0x2 + // Bit mask of EXCHG_PINS field. + USB_DEVICE_CONF0_EXCHG_PINS_Msk = 0x4 + // Bit EXCHG_PINS. + USB_DEVICE_CONF0_EXCHG_PINS = 0x4 + // Position of VREFH field. + USB_DEVICE_CONF0_VREFH_Pos = 0x3 + // Bit mask of VREFH field. + USB_DEVICE_CONF0_VREFH_Msk = 0x18 + // Position of VREFL field. + USB_DEVICE_CONF0_VREFL_Pos = 0x5 + // Bit mask of VREFL field. + USB_DEVICE_CONF0_VREFL_Msk = 0x60 + // Position of VREF_OVERRIDE field. + USB_DEVICE_CONF0_VREF_OVERRIDE_Pos = 0x7 + // Bit mask of VREF_OVERRIDE field. + USB_DEVICE_CONF0_VREF_OVERRIDE_Msk = 0x80 + // Bit VREF_OVERRIDE. + USB_DEVICE_CONF0_VREF_OVERRIDE = 0x80 + // Position of PAD_PULL_OVERRIDE field. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE_Pos = 0x8 + // Bit mask of PAD_PULL_OVERRIDE field. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE_Msk = 0x100 + // Bit PAD_PULL_OVERRIDE. + USB_DEVICE_CONF0_PAD_PULL_OVERRIDE = 0x100 + // Position of DP_PULLUP field. + USB_DEVICE_CONF0_DP_PULLUP_Pos = 0x9 + // Bit mask of DP_PULLUP field. + USB_DEVICE_CONF0_DP_PULLUP_Msk = 0x200 + // Bit DP_PULLUP. + USB_DEVICE_CONF0_DP_PULLUP = 0x200 + // Position of DP_PULLDOWN field. + USB_DEVICE_CONF0_DP_PULLDOWN_Pos = 0xa + // Bit mask of DP_PULLDOWN field. + USB_DEVICE_CONF0_DP_PULLDOWN_Msk = 0x400 + // Bit DP_PULLDOWN. + USB_DEVICE_CONF0_DP_PULLDOWN = 0x400 + // Position of DM_PULLUP field. + USB_DEVICE_CONF0_DM_PULLUP_Pos = 0xb + // Bit mask of DM_PULLUP field. + USB_DEVICE_CONF0_DM_PULLUP_Msk = 0x800 + // Bit DM_PULLUP. + USB_DEVICE_CONF0_DM_PULLUP = 0x800 + // Position of DM_PULLDOWN field. + USB_DEVICE_CONF0_DM_PULLDOWN_Pos = 0xc + // Bit mask of DM_PULLDOWN field. + USB_DEVICE_CONF0_DM_PULLDOWN_Msk = 0x1000 + // Bit DM_PULLDOWN. + USB_DEVICE_CONF0_DM_PULLDOWN = 0x1000 + // Position of PULLUP_VALUE field. + USB_DEVICE_CONF0_PULLUP_VALUE_Pos = 0xd + // Bit mask of PULLUP_VALUE field. + USB_DEVICE_CONF0_PULLUP_VALUE_Msk = 0x2000 + // Bit PULLUP_VALUE. + USB_DEVICE_CONF0_PULLUP_VALUE = 0x2000 + // Position of USB_PAD_ENABLE field. + USB_DEVICE_CONF0_USB_PAD_ENABLE_Pos = 0xe + // Bit mask of USB_PAD_ENABLE field. + USB_DEVICE_CONF0_USB_PAD_ENABLE_Msk = 0x4000 + // Bit USB_PAD_ENABLE. + USB_DEVICE_CONF0_USB_PAD_ENABLE = 0x4000 + // Position of PHY_TX_EDGE_SEL field. + USB_DEVICE_CONF0_PHY_TX_EDGE_SEL_Pos = 0xf + // Bit mask of PHY_TX_EDGE_SEL field. + USB_DEVICE_CONF0_PHY_TX_EDGE_SEL_Msk = 0x8000 + // Bit PHY_TX_EDGE_SEL. + USB_DEVICE_CONF0_PHY_TX_EDGE_SEL = 0x8000 + // Position of USB_JTAG_BRIDGE_EN field. + USB_DEVICE_CONF0_USB_JTAG_BRIDGE_EN_Pos = 0x10 + // Bit mask of USB_JTAG_BRIDGE_EN field. + USB_DEVICE_CONF0_USB_JTAG_BRIDGE_EN_Msk = 0x10000 + // Bit USB_JTAG_BRIDGE_EN. + USB_DEVICE_CONF0_USB_JTAG_BRIDGE_EN = 0x10000 + + // TEST: USB Internal PHY test register + // Position of ENABLE field. + USB_DEVICE_TEST_ENABLE_Pos = 0x0 + // Bit mask of ENABLE field. + USB_DEVICE_TEST_ENABLE_Msk = 0x1 + // Bit ENABLE. + USB_DEVICE_TEST_ENABLE = 0x1 + // Position of USB_OE field. + USB_DEVICE_TEST_USB_OE_Pos = 0x1 + // Bit mask of USB_OE field. + USB_DEVICE_TEST_USB_OE_Msk = 0x2 + // Bit USB_OE. + USB_DEVICE_TEST_USB_OE = 0x2 + // Position of TX_DP field. + USB_DEVICE_TEST_TX_DP_Pos = 0x2 + // Bit mask of TX_DP field. + USB_DEVICE_TEST_TX_DP_Msk = 0x4 + // Bit TX_DP. + USB_DEVICE_TEST_TX_DP = 0x4 + // Position of TX_DM field. + USB_DEVICE_TEST_TX_DM_Pos = 0x3 + // Bit mask of TX_DM field. + USB_DEVICE_TEST_TX_DM_Msk = 0x8 + // Bit TX_DM. + USB_DEVICE_TEST_TX_DM = 0x8 + // Position of RX_RCV field. + USB_DEVICE_TEST_RX_RCV_Pos = 0x4 + // Bit mask of RX_RCV field. + USB_DEVICE_TEST_RX_RCV_Msk = 0x10 + // Bit RX_RCV. + USB_DEVICE_TEST_RX_RCV = 0x10 + // Position of RX_DP field. + USB_DEVICE_TEST_RX_DP_Pos = 0x5 + // Bit mask of RX_DP field. + USB_DEVICE_TEST_RX_DP_Msk = 0x20 + // Bit RX_DP. + USB_DEVICE_TEST_RX_DP = 0x20 + // Position of RX_DM field. + USB_DEVICE_TEST_RX_DM_Pos = 0x6 + // Bit mask of RX_DM field. + USB_DEVICE_TEST_RX_DM_Msk = 0x40 + // Bit RX_DM. + USB_DEVICE_TEST_RX_DM = 0x40 + + // JFIFO_ST: USB-JTAG FIFO status + // Position of IN_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_IN_FIFO_CNT_Pos = 0x0 + // Bit mask of IN_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_IN_FIFO_CNT_Msk = 0x3 + // Position of IN_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY_Pos = 0x2 + // Bit mask of IN_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY_Msk = 0x4 + // Bit IN_FIFO_EMPTY. + USB_DEVICE_JFIFO_ST_IN_FIFO_EMPTY = 0x4 + // Position of IN_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL_Pos = 0x3 + // Bit mask of IN_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL_Msk = 0x8 + // Bit IN_FIFO_FULL. + USB_DEVICE_JFIFO_ST_IN_FIFO_FULL = 0x8 + // Position of OUT_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_CNT_Pos = 0x4 + // Bit mask of OUT_FIFO_CNT field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_CNT_Msk = 0x30 + // Position of OUT_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY_Pos = 0x6 + // Bit mask of OUT_FIFO_EMPTY field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY_Msk = 0x40 + // Bit OUT_FIFO_EMPTY. + USB_DEVICE_JFIFO_ST_OUT_FIFO_EMPTY = 0x40 + // Position of OUT_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL_Pos = 0x7 + // Bit mask of OUT_FIFO_FULL field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL_Msk = 0x80 + // Bit OUT_FIFO_FULL. + USB_DEVICE_JFIFO_ST_OUT_FIFO_FULL = 0x80 + // Position of IN_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET_Pos = 0x8 + // Bit mask of IN_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET_Msk = 0x100 + // Bit IN_FIFO_RESET. + USB_DEVICE_JFIFO_ST_IN_FIFO_RESET = 0x100 + // Position of OUT_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET_Pos = 0x9 + // Bit mask of OUT_FIFO_RESET field. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET_Msk = 0x200 + // Bit OUT_FIFO_RESET. + USB_DEVICE_JFIFO_ST_OUT_FIFO_RESET = 0x200 + + // FRAM_NUM: SOF frame number + // Position of SOF_FRAME_INDEX field. + USB_DEVICE_FRAM_NUM_SOF_FRAME_INDEX_Pos = 0x0 + // Bit mask of SOF_FRAME_INDEX field. + USB_DEVICE_FRAM_NUM_SOF_FRAME_INDEX_Msk = 0x7ff + + // IN_EP0_ST: IN Endpoint 0 status + // Position of IN_EP0_STATE field. + USB_DEVICE_IN_EP0_ST_IN_EP0_STATE_Pos = 0x0 + // Bit mask of IN_EP0_STATE field. + USB_DEVICE_IN_EP0_ST_IN_EP0_STATE_Msk = 0x3 + // Position of IN_EP0_WR_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP0_WR_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_WR_ADDR_Msk = 0x1fc + // Position of IN_EP0_RD_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP0_RD_ADDR field. + USB_DEVICE_IN_EP0_ST_IN_EP0_RD_ADDR_Msk = 0xfe00 + + // IN_EP1_ST: IN Endpoint 1 status + // Position of IN_EP1_STATE field. + USB_DEVICE_IN_EP1_ST_IN_EP1_STATE_Pos = 0x0 + // Bit mask of IN_EP1_STATE field. + USB_DEVICE_IN_EP1_ST_IN_EP1_STATE_Msk = 0x3 + // Position of IN_EP1_WR_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP1_WR_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_WR_ADDR_Msk = 0x1fc + // Position of IN_EP1_RD_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP1_RD_ADDR field. + USB_DEVICE_IN_EP1_ST_IN_EP1_RD_ADDR_Msk = 0xfe00 + + // IN_EP2_ST: IN Endpoint 2 status + // Position of IN_EP2_STATE field. + USB_DEVICE_IN_EP2_ST_IN_EP2_STATE_Pos = 0x0 + // Bit mask of IN_EP2_STATE field. + USB_DEVICE_IN_EP2_ST_IN_EP2_STATE_Msk = 0x3 + // Position of IN_EP2_WR_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP2_WR_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_WR_ADDR_Msk = 0x1fc + // Position of IN_EP2_RD_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP2_RD_ADDR field. + USB_DEVICE_IN_EP2_ST_IN_EP2_RD_ADDR_Msk = 0xfe00 + + // IN_EP3_ST: IN Endpoint 3 status + // Position of IN_EP3_STATE field. + USB_DEVICE_IN_EP3_ST_IN_EP3_STATE_Pos = 0x0 + // Bit mask of IN_EP3_STATE field. + USB_DEVICE_IN_EP3_ST_IN_EP3_STATE_Msk = 0x3 + // Position of IN_EP3_WR_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_WR_ADDR_Pos = 0x2 + // Bit mask of IN_EP3_WR_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_WR_ADDR_Msk = 0x1fc + // Position of IN_EP3_RD_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_RD_ADDR_Pos = 0x9 + // Bit mask of IN_EP3_RD_ADDR field. + USB_DEVICE_IN_EP3_ST_IN_EP3_RD_ADDR_Msk = 0xfe00 + + // OUT_EP0_ST: OUT Endpoint 0 status + // Position of OUT_EP0_STATE field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_STATE_Pos = 0x0 + // Bit mask of OUT_EP0_STATE field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_STATE_Msk = 0x3 + // Position of OUT_EP0_WR_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP0_WR_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP0_RD_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP0_RD_ADDR field. + USB_DEVICE_OUT_EP0_ST_OUT_EP0_RD_ADDR_Msk = 0xfe00 + + // OUT_EP1_ST: OUT Endpoint 1 status + // Position of OUT_EP1_STATE field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_STATE_Pos = 0x0 + // Bit mask of OUT_EP1_STATE field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_STATE_Msk = 0x3 + // Position of OUT_EP1_WR_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP1_WR_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP1_RD_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP1_RD_ADDR field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_RD_ADDR_Msk = 0xfe00 + // Position of OUT_EP1_REC_DATA_CNT field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_REC_DATA_CNT_Pos = 0x10 + // Bit mask of OUT_EP1_REC_DATA_CNT field. + USB_DEVICE_OUT_EP1_ST_OUT_EP1_REC_DATA_CNT_Msk = 0x7f0000 + + // OUT_EP2_ST: OUT Endpoint 2 status + // Position of OUT_EP2_STATE field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_STATE_Pos = 0x0 + // Bit mask of OUT_EP2_STATE field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_STATE_Msk = 0x3 + // Position of OUT_EP2_WR_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_WR_ADDR_Pos = 0x2 + // Bit mask of OUT_EP2_WR_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_WR_ADDR_Msk = 0x1fc + // Position of OUT_EP2_RD_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_RD_ADDR_Pos = 0x9 + // Bit mask of OUT_EP2_RD_ADDR field. + USB_DEVICE_OUT_EP2_ST_OUT_EP2_RD_ADDR_Msk = 0xfe00 + + // MISC_CONF: MISC register + // Position of CLK_EN field. + USB_DEVICE_MISC_CONF_CLK_EN_Pos = 0x0 + // Bit mask of CLK_EN field. + USB_DEVICE_MISC_CONF_CLK_EN_Msk = 0x1 + // Bit CLK_EN. + USB_DEVICE_MISC_CONF_CLK_EN = 0x1 + + // MEM_CONF: Power control + // Position of USB_MEM_PD field. + USB_DEVICE_MEM_CONF_USB_MEM_PD_Pos = 0x0 + // Bit mask of USB_MEM_PD field. + USB_DEVICE_MEM_CONF_USB_MEM_PD_Msk = 0x1 + // Bit USB_MEM_PD. + USB_DEVICE_MEM_CONF_USB_MEM_PD = 0x1 + // Position of USB_MEM_CLK_EN field. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN_Pos = 0x1 + // Bit mask of USB_MEM_CLK_EN field. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN_Msk = 0x2 + // Bit USB_MEM_CLK_EN. + USB_DEVICE_MEM_CONF_USB_MEM_CLK_EN = 0x2 + + // DATE: Version control register + // Position of DATE field. + USB_DEVICE_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + USB_DEVICE_DATE_DATE_Msk = 0xffffffff +) + +// Constants for USB_WRAP: USB_WRAP Peripheral +const ( + // OTG_CONF: USB OTG Wrapper Configure Register + // Position of SRP_SESSEND_OVERRIDE field. + USB_WRAP_OTG_CONF_SRP_SESSEND_OVERRIDE_Pos = 0x0 + // Bit mask of SRP_SESSEND_OVERRIDE field. + USB_WRAP_OTG_CONF_SRP_SESSEND_OVERRIDE_Msk = 0x1 + // Bit SRP_SESSEND_OVERRIDE. + USB_WRAP_OTG_CONF_SRP_SESSEND_OVERRIDE = 0x1 + // Position of SRP_SESSEND_VALUE field. + USB_WRAP_OTG_CONF_SRP_SESSEND_VALUE_Pos = 0x1 + // Bit mask of SRP_SESSEND_VALUE field. + USB_WRAP_OTG_CONF_SRP_SESSEND_VALUE_Msk = 0x2 + // Bit SRP_SESSEND_VALUE. + USB_WRAP_OTG_CONF_SRP_SESSEND_VALUE = 0x2 + // Position of PHY_SEL field. + USB_WRAP_OTG_CONF_PHY_SEL_Pos = 0x2 + // Bit mask of PHY_SEL field. + USB_WRAP_OTG_CONF_PHY_SEL_Msk = 0x4 + // Bit PHY_SEL. + USB_WRAP_OTG_CONF_PHY_SEL = 0x4 + // Position of DFIFO_FORCE_PD field. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PD_Pos = 0x3 + // Bit mask of DFIFO_FORCE_PD field. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PD_Msk = 0x8 + // Bit DFIFO_FORCE_PD. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PD = 0x8 + // Position of DBNCE_FLTR_BYPASS field. + USB_WRAP_OTG_CONF_DBNCE_FLTR_BYPASS_Pos = 0x4 + // Bit mask of DBNCE_FLTR_BYPASS field. + USB_WRAP_OTG_CONF_DBNCE_FLTR_BYPASS_Msk = 0x10 + // Bit DBNCE_FLTR_BYPASS. + USB_WRAP_OTG_CONF_DBNCE_FLTR_BYPASS = 0x10 + // Position of EXCHG_PINS_OVERRIDE field. + USB_WRAP_OTG_CONF_EXCHG_PINS_OVERRIDE_Pos = 0x5 + // Bit mask of EXCHG_PINS_OVERRIDE field. + USB_WRAP_OTG_CONF_EXCHG_PINS_OVERRIDE_Msk = 0x20 + // Bit EXCHG_PINS_OVERRIDE. + USB_WRAP_OTG_CONF_EXCHG_PINS_OVERRIDE = 0x20 + // Position of EXCHG_PINS field. + USB_WRAP_OTG_CONF_EXCHG_PINS_Pos = 0x6 + // Bit mask of EXCHG_PINS field. + USB_WRAP_OTG_CONF_EXCHG_PINS_Msk = 0x40 + // Bit EXCHG_PINS. + USB_WRAP_OTG_CONF_EXCHG_PINS = 0x40 + // Position of VREFH field. + USB_WRAP_OTG_CONF_VREFH_Pos = 0x7 + // Bit mask of VREFH field. + USB_WRAP_OTG_CONF_VREFH_Msk = 0x180 + // Position of VREFL field. + USB_WRAP_OTG_CONF_VREFL_Pos = 0x9 + // Bit mask of VREFL field. + USB_WRAP_OTG_CONF_VREFL_Msk = 0x600 + // Position of VREF_OVERRIDE field. + USB_WRAP_OTG_CONF_VREF_OVERRIDE_Pos = 0xb + // Bit mask of VREF_OVERRIDE field. + USB_WRAP_OTG_CONF_VREF_OVERRIDE_Msk = 0x800 + // Bit VREF_OVERRIDE. + USB_WRAP_OTG_CONF_VREF_OVERRIDE = 0x800 + // Position of PAD_PULL_OVERRIDE field. + USB_WRAP_OTG_CONF_PAD_PULL_OVERRIDE_Pos = 0xc + // Bit mask of PAD_PULL_OVERRIDE field. + USB_WRAP_OTG_CONF_PAD_PULL_OVERRIDE_Msk = 0x1000 + // Bit PAD_PULL_OVERRIDE. + USB_WRAP_OTG_CONF_PAD_PULL_OVERRIDE = 0x1000 + // Position of DP_PULLUP field. + USB_WRAP_OTG_CONF_DP_PULLUP_Pos = 0xd + // Bit mask of DP_PULLUP field. + USB_WRAP_OTG_CONF_DP_PULLUP_Msk = 0x2000 + // Bit DP_PULLUP. + USB_WRAP_OTG_CONF_DP_PULLUP = 0x2000 + // Position of DP_PULLDOWN field. + USB_WRAP_OTG_CONF_DP_PULLDOWN_Pos = 0xe + // Bit mask of DP_PULLDOWN field. + USB_WRAP_OTG_CONF_DP_PULLDOWN_Msk = 0x4000 + // Bit DP_PULLDOWN. + USB_WRAP_OTG_CONF_DP_PULLDOWN = 0x4000 + // Position of DM_PULLUP field. + USB_WRAP_OTG_CONF_DM_PULLUP_Pos = 0xf + // Bit mask of DM_PULLUP field. + USB_WRAP_OTG_CONF_DM_PULLUP_Msk = 0x8000 + // Bit DM_PULLUP. + USB_WRAP_OTG_CONF_DM_PULLUP = 0x8000 + // Position of DM_PULLDOWN field. + USB_WRAP_OTG_CONF_DM_PULLDOWN_Pos = 0x10 + // Bit mask of DM_PULLDOWN field. + USB_WRAP_OTG_CONF_DM_PULLDOWN_Msk = 0x10000 + // Bit DM_PULLDOWN. + USB_WRAP_OTG_CONF_DM_PULLDOWN = 0x10000 + // Position of PULLUP_VALUE field. + USB_WRAP_OTG_CONF_PULLUP_VALUE_Pos = 0x11 + // Bit mask of PULLUP_VALUE field. + USB_WRAP_OTG_CONF_PULLUP_VALUE_Msk = 0x20000 + // Bit PULLUP_VALUE. + USB_WRAP_OTG_CONF_PULLUP_VALUE = 0x20000 + // Position of USB_PAD_ENABLE field. + USB_WRAP_OTG_CONF_USB_PAD_ENABLE_Pos = 0x12 + // Bit mask of USB_PAD_ENABLE field. + USB_WRAP_OTG_CONF_USB_PAD_ENABLE_Msk = 0x40000 + // Bit USB_PAD_ENABLE. + USB_WRAP_OTG_CONF_USB_PAD_ENABLE = 0x40000 + // Position of AHB_CLK_FORCE_ON field. + USB_WRAP_OTG_CONF_AHB_CLK_FORCE_ON_Pos = 0x13 + // Bit mask of AHB_CLK_FORCE_ON field. + USB_WRAP_OTG_CONF_AHB_CLK_FORCE_ON_Msk = 0x80000 + // Bit AHB_CLK_FORCE_ON. + USB_WRAP_OTG_CONF_AHB_CLK_FORCE_ON = 0x80000 + // Position of PHY_CLK_FORCE_ON field. + USB_WRAP_OTG_CONF_PHY_CLK_FORCE_ON_Pos = 0x14 + // Bit mask of PHY_CLK_FORCE_ON field. + USB_WRAP_OTG_CONF_PHY_CLK_FORCE_ON_Msk = 0x100000 + // Bit PHY_CLK_FORCE_ON. + USB_WRAP_OTG_CONF_PHY_CLK_FORCE_ON = 0x100000 + // Position of PHY_TX_EDGE_SEL field. + USB_WRAP_OTG_CONF_PHY_TX_EDGE_SEL_Pos = 0x15 + // Bit mask of PHY_TX_EDGE_SEL field. + USB_WRAP_OTG_CONF_PHY_TX_EDGE_SEL_Msk = 0x200000 + // Bit PHY_TX_EDGE_SEL. + USB_WRAP_OTG_CONF_PHY_TX_EDGE_SEL = 0x200000 + // Position of DFIFO_FORCE_PU field. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PU_Pos = 0x16 + // Bit mask of DFIFO_FORCE_PU field. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PU_Msk = 0x400000 + // Bit DFIFO_FORCE_PU. + USB_WRAP_OTG_CONF_DFIFO_FORCE_PU = 0x400000 + // Position of CLK_EN field. + USB_WRAP_OTG_CONF_CLK_EN_Pos = 0x1f + // Bit mask of CLK_EN field. + USB_WRAP_OTG_CONF_CLK_EN_Msk = 0x80000000 + // Bit CLK_EN. + USB_WRAP_OTG_CONF_CLK_EN = 0x80000000 + + // TEST_CONF: USB Internal PHY Testing Register + // Position of TEST_ENABLE field. + USB_WRAP_TEST_CONF_TEST_ENABLE_Pos = 0x0 + // Bit mask of TEST_ENABLE field. + USB_WRAP_TEST_CONF_TEST_ENABLE_Msk = 0x1 + // Bit TEST_ENABLE. + USB_WRAP_TEST_CONF_TEST_ENABLE = 0x1 + // Position of TEST_USB_OE field. + USB_WRAP_TEST_CONF_TEST_USB_OE_Pos = 0x1 + // Bit mask of TEST_USB_OE field. + USB_WRAP_TEST_CONF_TEST_USB_OE_Msk = 0x2 + // Bit TEST_USB_OE. + USB_WRAP_TEST_CONF_TEST_USB_OE = 0x2 + // Position of TEST_TX_DP field. + USB_WRAP_TEST_CONF_TEST_TX_DP_Pos = 0x2 + // Bit mask of TEST_TX_DP field. + USB_WRAP_TEST_CONF_TEST_TX_DP_Msk = 0x4 + // Bit TEST_TX_DP. + USB_WRAP_TEST_CONF_TEST_TX_DP = 0x4 + // Position of TEST_TX_DM field. + USB_WRAP_TEST_CONF_TEST_TX_DM_Pos = 0x3 + // Bit mask of TEST_TX_DM field. + USB_WRAP_TEST_CONF_TEST_TX_DM_Msk = 0x8 + // Bit TEST_TX_DM. + USB_WRAP_TEST_CONF_TEST_TX_DM = 0x8 + // Position of TEST_RX_RCV field. + USB_WRAP_TEST_CONF_TEST_RX_RCV_Pos = 0x4 + // Bit mask of TEST_RX_RCV field. + USB_WRAP_TEST_CONF_TEST_RX_RCV_Msk = 0x10 + // Bit TEST_RX_RCV. + USB_WRAP_TEST_CONF_TEST_RX_RCV = 0x10 + // Position of TEST_RX_DP field. + USB_WRAP_TEST_CONF_TEST_RX_DP_Pos = 0x5 + // Bit mask of TEST_RX_DP field. + USB_WRAP_TEST_CONF_TEST_RX_DP_Msk = 0x20 + // Bit TEST_RX_DP. + USB_WRAP_TEST_CONF_TEST_RX_DP = 0x20 + // Position of TEST_RX_DM field. + USB_WRAP_TEST_CONF_TEST_RX_DM_Pos = 0x6 + // Bit mask of TEST_RX_DM field. + USB_WRAP_TEST_CONF_TEST_RX_DM_Msk = 0x40 + // Bit TEST_RX_DM. + USB_WRAP_TEST_CONF_TEST_RX_DM = 0x40 + + // DATE: Version Control Register + // Position of USB_WRAP_DATE field. + USB_WRAP_DATE_USB_WRAP_DATE_Pos = 0x0 + // Bit mask of USB_WRAP_DATE field. + USB_WRAP_DATE_USB_WRAP_DATE_Msk = 0xffffffff +) + +// Constants for WCL: WCL Peripheral +const ( + // Core_0_ENTRY_1_ADDR: Core_0 Entry 1 address configuration Register + // Position of CORE_0_ENTRY_1_ADDR field. + WCL_Core_0_ENTRY_1_ADDR_CORE_0_ENTRY_1_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_1_ADDR field. + WCL_Core_0_ENTRY_1_ADDR_CORE_0_ENTRY_1_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_2_ADDR: Core_0 Entry 2 address configuration Register + // Position of CORE_0_ENTRY_2_ADDR field. + WCL_Core_0_ENTRY_2_ADDR_CORE_0_ENTRY_2_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_2_ADDR field. + WCL_Core_0_ENTRY_2_ADDR_CORE_0_ENTRY_2_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_3_ADDR: Core_0 Entry 3 address configuration Register + // Position of CORE_0_ENTRY_3_ADDR field. + WCL_Core_0_ENTRY_3_ADDR_CORE_0_ENTRY_3_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_3_ADDR field. + WCL_Core_0_ENTRY_3_ADDR_CORE_0_ENTRY_3_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_4_ADDR: Core_0 Entry 4 address configuration Register + // Position of CORE_0_ENTRY_4_ADDR field. + WCL_Core_0_ENTRY_4_ADDR_CORE_0_ENTRY_4_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_4_ADDR field. + WCL_Core_0_ENTRY_4_ADDR_CORE_0_ENTRY_4_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_5_ADDR: Core_0 Entry 5 address configuration Register + // Position of CORE_0_ENTRY_5_ADDR field. + WCL_Core_0_ENTRY_5_ADDR_CORE_0_ENTRY_5_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_5_ADDR field. + WCL_Core_0_ENTRY_5_ADDR_CORE_0_ENTRY_5_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_6_ADDR: Core_0 Entry 6 address configuration Register + // Position of CORE_0_ENTRY_6_ADDR field. + WCL_Core_0_ENTRY_6_ADDR_CORE_0_ENTRY_6_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_6_ADDR field. + WCL_Core_0_ENTRY_6_ADDR_CORE_0_ENTRY_6_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_7_ADDR: Core_0 Entry 7 address configuration Register + // Position of CORE_0_ENTRY_7_ADDR field. + WCL_Core_0_ENTRY_7_ADDR_CORE_0_ENTRY_7_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_7_ADDR field. + WCL_Core_0_ENTRY_7_ADDR_CORE_0_ENTRY_7_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_8_ADDR: Core_0 Entry 8 address configuration Register + // Position of CORE_0_ENTRY_8_ADDR field. + WCL_Core_0_ENTRY_8_ADDR_CORE_0_ENTRY_8_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_8_ADDR field. + WCL_Core_0_ENTRY_8_ADDR_CORE_0_ENTRY_8_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_9_ADDR: Core_0 Entry 9 address configuration Register + // Position of CORE_0_ENTRY_9_ADDR field. + WCL_Core_0_ENTRY_9_ADDR_CORE_0_ENTRY_9_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_9_ADDR field. + WCL_Core_0_ENTRY_9_ADDR_CORE_0_ENTRY_9_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_10_ADDR: Core_0 Entry 10 address configuration Register + // Position of CORE_0_ENTRY_10_ADDR field. + WCL_Core_0_ENTRY_10_ADDR_CORE_0_ENTRY_10_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_10_ADDR field. + WCL_Core_0_ENTRY_10_ADDR_CORE_0_ENTRY_10_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_11_ADDR: Core_0 Entry 11 address configuration Register + // Position of CORE_0_ENTRY_11_ADDR field. + WCL_Core_0_ENTRY_11_ADDR_CORE_0_ENTRY_11_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_11_ADDR field. + WCL_Core_0_ENTRY_11_ADDR_CORE_0_ENTRY_11_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_12_ADDR: Core_0 Entry 12 address configuration Register + // Position of CORE_0_ENTRY_12_ADDR field. + WCL_Core_0_ENTRY_12_ADDR_CORE_0_ENTRY_12_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_12_ADDR field. + WCL_Core_0_ENTRY_12_ADDR_CORE_0_ENTRY_12_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_13_ADDR: Core_0 Entry 13 address configuration Register + // Position of CORE_0_ENTRY_13_ADDR field. + WCL_Core_0_ENTRY_13_ADDR_CORE_0_ENTRY_13_ADDR_Pos = 0x0 + // Bit mask of CORE_0_ENTRY_13_ADDR field. + WCL_Core_0_ENTRY_13_ADDR_CORE_0_ENTRY_13_ADDR_Msk = 0xffffffff + + // Core_0_ENTRY_CHECK: Core_0 Entry check configuration Register + // Position of CORE_0_ENTRY_CHECK field. + WCL_Core_0_ENTRY_CHECK_CORE_0_ENTRY_CHECK_Pos = 0x1 + // Bit mask of CORE_0_ENTRY_CHECK field. + WCL_Core_0_ENTRY_CHECK_CORE_0_ENTRY_CHECK_Msk = 0x3ffe + + // Core_0_STATUSTABLE1: Status register of world switch of entry 1 + // Position of CORE_0_FROM_WORLD_1 field. + WCL_Core_0_STATUSTABLE1_CORE_0_FROM_WORLD_1_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_1 field. + WCL_Core_0_STATUSTABLE1_CORE_0_FROM_WORLD_1_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_1. + WCL_Core_0_STATUSTABLE1_CORE_0_FROM_WORLD_1 = 0x1 + // Position of CORE_0_FROM_ENTRY_1 field. + WCL_Core_0_STATUSTABLE1_CORE_0_FROM_ENTRY_1_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_1 field. + WCL_Core_0_STATUSTABLE1_CORE_0_FROM_ENTRY_1_Msk = 0x1e + // Position of CORE_0_CURRENT_1 field. + WCL_Core_0_STATUSTABLE1_CORE_0_CURRENT_1_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_1 field. + WCL_Core_0_STATUSTABLE1_CORE_0_CURRENT_1_Msk = 0x20 + // Bit CORE_0_CURRENT_1. + WCL_Core_0_STATUSTABLE1_CORE_0_CURRENT_1 = 0x20 + + // Core_0_STATUSTABLE2: Status register of world switch of entry 2 + // Position of CORE_0_FROM_WORLD_2 field. + WCL_Core_0_STATUSTABLE2_CORE_0_FROM_WORLD_2_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_2 field. + WCL_Core_0_STATUSTABLE2_CORE_0_FROM_WORLD_2_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_2. + WCL_Core_0_STATUSTABLE2_CORE_0_FROM_WORLD_2 = 0x1 + // Position of CORE_0_FROM_ENTRY_2 field. + WCL_Core_0_STATUSTABLE2_CORE_0_FROM_ENTRY_2_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_2 field. + WCL_Core_0_STATUSTABLE2_CORE_0_FROM_ENTRY_2_Msk = 0x1e + // Position of CORE_0_CURRENT_2 field. + WCL_Core_0_STATUSTABLE2_CORE_0_CURRENT_2_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_2 field. + WCL_Core_0_STATUSTABLE2_CORE_0_CURRENT_2_Msk = 0x20 + // Bit CORE_0_CURRENT_2. + WCL_Core_0_STATUSTABLE2_CORE_0_CURRENT_2 = 0x20 + + // Core_0_STATUSTABLE3: Status register of world switch of entry 3 + // Position of CORE_0_FROM_WORLD_3 field. + WCL_Core_0_STATUSTABLE3_CORE_0_FROM_WORLD_3_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_3 field. + WCL_Core_0_STATUSTABLE3_CORE_0_FROM_WORLD_3_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_3. + WCL_Core_0_STATUSTABLE3_CORE_0_FROM_WORLD_3 = 0x1 + // Position of CORE_0_FROM_ENTRY_3 field. + WCL_Core_0_STATUSTABLE3_CORE_0_FROM_ENTRY_3_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_3 field. + WCL_Core_0_STATUSTABLE3_CORE_0_FROM_ENTRY_3_Msk = 0x1e + // Position of CORE_0_CURRENT_3 field. + WCL_Core_0_STATUSTABLE3_CORE_0_CURRENT_3_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_3 field. + WCL_Core_0_STATUSTABLE3_CORE_0_CURRENT_3_Msk = 0x20 + // Bit CORE_0_CURRENT_3. + WCL_Core_0_STATUSTABLE3_CORE_0_CURRENT_3 = 0x20 + + // Core_0_STATUSTABLE4: Status register of world switch of entry 4 + // Position of CORE_0_FROM_WORLD_4 field. + WCL_Core_0_STATUSTABLE4_CORE_0_FROM_WORLD_4_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_4 field. + WCL_Core_0_STATUSTABLE4_CORE_0_FROM_WORLD_4_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_4. + WCL_Core_0_STATUSTABLE4_CORE_0_FROM_WORLD_4 = 0x1 + // Position of CORE_0_FROM_ENTRY_4 field. + WCL_Core_0_STATUSTABLE4_CORE_0_FROM_ENTRY_4_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_4 field. + WCL_Core_0_STATUSTABLE4_CORE_0_FROM_ENTRY_4_Msk = 0x1e + // Position of CORE_0_CURRENT_4 field. + WCL_Core_0_STATUSTABLE4_CORE_0_CURRENT_4_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_4 field. + WCL_Core_0_STATUSTABLE4_CORE_0_CURRENT_4_Msk = 0x20 + // Bit CORE_0_CURRENT_4. + WCL_Core_0_STATUSTABLE4_CORE_0_CURRENT_4 = 0x20 + + // Core_0_STATUSTABLE5: Status register of world switch of entry 5 + // Position of CORE_0_FROM_WORLD_5 field. + WCL_Core_0_STATUSTABLE5_CORE_0_FROM_WORLD_5_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_5 field. + WCL_Core_0_STATUSTABLE5_CORE_0_FROM_WORLD_5_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_5. + WCL_Core_0_STATUSTABLE5_CORE_0_FROM_WORLD_5 = 0x1 + // Position of CORE_0_FROM_ENTRY_5 field. + WCL_Core_0_STATUSTABLE5_CORE_0_FROM_ENTRY_5_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_5 field. + WCL_Core_0_STATUSTABLE5_CORE_0_FROM_ENTRY_5_Msk = 0x1e + // Position of CORE_0_CURRENT_5 field. + WCL_Core_0_STATUSTABLE5_CORE_0_CURRENT_5_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_5 field. + WCL_Core_0_STATUSTABLE5_CORE_0_CURRENT_5_Msk = 0x20 + // Bit CORE_0_CURRENT_5. + WCL_Core_0_STATUSTABLE5_CORE_0_CURRENT_5 = 0x20 + + // Core_0_STATUSTABLE6: Status register of world switch of entry 6 + // Position of CORE_0_FROM_WORLD_6 field. + WCL_Core_0_STATUSTABLE6_CORE_0_FROM_WORLD_6_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_6 field. + WCL_Core_0_STATUSTABLE6_CORE_0_FROM_WORLD_6_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_6. + WCL_Core_0_STATUSTABLE6_CORE_0_FROM_WORLD_6 = 0x1 + // Position of CORE_0_FROM_ENTRY_6 field. + WCL_Core_0_STATUSTABLE6_CORE_0_FROM_ENTRY_6_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_6 field. + WCL_Core_0_STATUSTABLE6_CORE_0_FROM_ENTRY_6_Msk = 0x1e + // Position of CORE_0_CURRENT_6 field. + WCL_Core_0_STATUSTABLE6_CORE_0_CURRENT_6_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_6 field. + WCL_Core_0_STATUSTABLE6_CORE_0_CURRENT_6_Msk = 0x20 + // Bit CORE_0_CURRENT_6. + WCL_Core_0_STATUSTABLE6_CORE_0_CURRENT_6 = 0x20 + + // Core_0_STATUSTABLE7: Status register of world switch of entry 7 + // Position of CORE_0_FROM_WORLD_7 field. + WCL_Core_0_STATUSTABLE7_CORE_0_FROM_WORLD_7_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_7 field. + WCL_Core_0_STATUSTABLE7_CORE_0_FROM_WORLD_7_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_7. + WCL_Core_0_STATUSTABLE7_CORE_0_FROM_WORLD_7 = 0x1 + // Position of CORE_0_FROM_ENTRY_7 field. + WCL_Core_0_STATUSTABLE7_CORE_0_FROM_ENTRY_7_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_7 field. + WCL_Core_0_STATUSTABLE7_CORE_0_FROM_ENTRY_7_Msk = 0x1e + // Position of CORE_0_CURRENT_7 field. + WCL_Core_0_STATUSTABLE7_CORE_0_CURRENT_7_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_7 field. + WCL_Core_0_STATUSTABLE7_CORE_0_CURRENT_7_Msk = 0x20 + // Bit CORE_0_CURRENT_7. + WCL_Core_0_STATUSTABLE7_CORE_0_CURRENT_7 = 0x20 + + // Core_0_STATUSTABLE8: Status register of world switch of entry 8 + // Position of CORE_0_FROM_WORLD_8 field. + WCL_Core_0_STATUSTABLE8_CORE_0_FROM_WORLD_8_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_8 field. + WCL_Core_0_STATUSTABLE8_CORE_0_FROM_WORLD_8_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_8. + WCL_Core_0_STATUSTABLE8_CORE_0_FROM_WORLD_8 = 0x1 + // Position of CORE_0_FROM_ENTRY_8 field. + WCL_Core_0_STATUSTABLE8_CORE_0_FROM_ENTRY_8_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_8 field. + WCL_Core_0_STATUSTABLE8_CORE_0_FROM_ENTRY_8_Msk = 0x1e + // Position of CORE_0_CURRENT_8 field. + WCL_Core_0_STATUSTABLE8_CORE_0_CURRENT_8_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_8 field. + WCL_Core_0_STATUSTABLE8_CORE_0_CURRENT_8_Msk = 0x20 + // Bit CORE_0_CURRENT_8. + WCL_Core_0_STATUSTABLE8_CORE_0_CURRENT_8 = 0x20 + + // Core_0_STATUSTABLE9: Status register of world switch of entry 9 + // Position of CORE_0_FROM_WORLD_9 field. + WCL_Core_0_STATUSTABLE9_CORE_0_FROM_WORLD_9_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_9 field. + WCL_Core_0_STATUSTABLE9_CORE_0_FROM_WORLD_9_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_9. + WCL_Core_0_STATUSTABLE9_CORE_0_FROM_WORLD_9 = 0x1 + // Position of CORE_0_FROM_ENTRY_9 field. + WCL_Core_0_STATUSTABLE9_CORE_0_FROM_ENTRY_9_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_9 field. + WCL_Core_0_STATUSTABLE9_CORE_0_FROM_ENTRY_9_Msk = 0x1e + // Position of CORE_0_CURRENT_9 field. + WCL_Core_0_STATUSTABLE9_CORE_0_CURRENT_9_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_9 field. + WCL_Core_0_STATUSTABLE9_CORE_0_CURRENT_9_Msk = 0x20 + // Bit CORE_0_CURRENT_9. + WCL_Core_0_STATUSTABLE9_CORE_0_CURRENT_9 = 0x20 + + // Core_0_STATUSTABLE10: Status register of world switch of entry 10 + // Position of CORE_0_FROM_WORLD_10 field. + WCL_Core_0_STATUSTABLE10_CORE_0_FROM_WORLD_10_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_10 field. + WCL_Core_0_STATUSTABLE10_CORE_0_FROM_WORLD_10_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_10. + WCL_Core_0_STATUSTABLE10_CORE_0_FROM_WORLD_10 = 0x1 + // Position of CORE_0_FROM_ENTRY_10 field. + WCL_Core_0_STATUSTABLE10_CORE_0_FROM_ENTRY_10_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_10 field. + WCL_Core_0_STATUSTABLE10_CORE_0_FROM_ENTRY_10_Msk = 0x1e + // Position of CORE_0_CURRENT_10 field. + WCL_Core_0_STATUSTABLE10_CORE_0_CURRENT_10_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_10 field. + WCL_Core_0_STATUSTABLE10_CORE_0_CURRENT_10_Msk = 0x20 + // Bit CORE_0_CURRENT_10. + WCL_Core_0_STATUSTABLE10_CORE_0_CURRENT_10 = 0x20 + + // Core_0_STATUSTABLE11: Status register of world switch of entry 11 + // Position of CORE_0_FROM_WORLD_11 field. + WCL_Core_0_STATUSTABLE11_CORE_0_FROM_WORLD_11_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_11 field. + WCL_Core_0_STATUSTABLE11_CORE_0_FROM_WORLD_11_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_11. + WCL_Core_0_STATUSTABLE11_CORE_0_FROM_WORLD_11 = 0x1 + // Position of CORE_0_FROM_ENTRY_11 field. + WCL_Core_0_STATUSTABLE11_CORE_0_FROM_ENTRY_11_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_11 field. + WCL_Core_0_STATUSTABLE11_CORE_0_FROM_ENTRY_11_Msk = 0x1e + // Position of CORE_0_CURRENT_11 field. + WCL_Core_0_STATUSTABLE11_CORE_0_CURRENT_11_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_11 field. + WCL_Core_0_STATUSTABLE11_CORE_0_CURRENT_11_Msk = 0x20 + // Bit CORE_0_CURRENT_11. + WCL_Core_0_STATUSTABLE11_CORE_0_CURRENT_11 = 0x20 + + // Core_0_STATUSTABLE12: Status register of world switch of entry 12 + // Position of CORE_0_FROM_WORLD_12 field. + WCL_Core_0_STATUSTABLE12_CORE_0_FROM_WORLD_12_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_12 field. + WCL_Core_0_STATUSTABLE12_CORE_0_FROM_WORLD_12_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_12. + WCL_Core_0_STATUSTABLE12_CORE_0_FROM_WORLD_12 = 0x1 + // Position of CORE_0_FROM_ENTRY_12 field. + WCL_Core_0_STATUSTABLE12_CORE_0_FROM_ENTRY_12_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_12 field. + WCL_Core_0_STATUSTABLE12_CORE_0_FROM_ENTRY_12_Msk = 0x1e + // Position of CORE_0_CURRENT_12 field. + WCL_Core_0_STATUSTABLE12_CORE_0_CURRENT_12_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_12 field. + WCL_Core_0_STATUSTABLE12_CORE_0_CURRENT_12_Msk = 0x20 + // Bit CORE_0_CURRENT_12. + WCL_Core_0_STATUSTABLE12_CORE_0_CURRENT_12 = 0x20 + + // Core_0_STATUSTABLE13: Status register of world switch of entry 13 + // Position of CORE_0_FROM_WORLD_13 field. + WCL_Core_0_STATUSTABLE13_CORE_0_FROM_WORLD_13_Pos = 0x0 + // Bit mask of CORE_0_FROM_WORLD_13 field. + WCL_Core_0_STATUSTABLE13_CORE_0_FROM_WORLD_13_Msk = 0x1 + // Bit CORE_0_FROM_WORLD_13. + WCL_Core_0_STATUSTABLE13_CORE_0_FROM_WORLD_13 = 0x1 + // Position of CORE_0_FROM_ENTRY_13 field. + WCL_Core_0_STATUSTABLE13_CORE_0_FROM_ENTRY_13_Pos = 0x1 + // Bit mask of CORE_0_FROM_ENTRY_13 field. + WCL_Core_0_STATUSTABLE13_CORE_0_FROM_ENTRY_13_Msk = 0x1e + // Position of CORE_0_CURRENT_13 field. + WCL_Core_0_STATUSTABLE13_CORE_0_CURRENT_13_Pos = 0x5 + // Bit mask of CORE_0_CURRENT_13 field. + WCL_Core_0_STATUSTABLE13_CORE_0_CURRENT_13_Msk = 0x20 + // Bit CORE_0_CURRENT_13. + WCL_Core_0_STATUSTABLE13_CORE_0_CURRENT_13 = 0x20 + + // Core_0_STATUSTABLE_CURRENT: Status register of statustable current + // Position of CORE_0_STATUSTABLE_CURRENT field. + WCL_Core_0_STATUSTABLE_CURRENT_CORE_0_STATUSTABLE_CURRENT_Pos = 0x1 + // Bit mask of CORE_0_STATUSTABLE_CURRENT field. + WCL_Core_0_STATUSTABLE_CURRENT_CORE_0_STATUSTABLE_CURRENT_Msk = 0x3ffe + + // Core_0_MESSAGE_ADDR: Clear writer_buffer write address configuration register + // Position of CORE_0_MESSAGE_ADDR field. + WCL_Core_0_MESSAGE_ADDR_CORE_0_MESSAGE_ADDR_Pos = 0x0 + // Bit mask of CORE_0_MESSAGE_ADDR field. + WCL_Core_0_MESSAGE_ADDR_CORE_0_MESSAGE_ADDR_Msk = 0xffffffff + + // Core_0_MESSAGE_MAX: Clear writer_buffer write number configuration register + // Position of CORE_0_MESSAGE_MAX field. + WCL_Core_0_MESSAGE_MAX_CORE_0_MESSAGE_MAX_Pos = 0x0 + // Bit mask of CORE_0_MESSAGE_MAX field. + WCL_Core_0_MESSAGE_MAX_CORE_0_MESSAGE_MAX_Msk = 0xf + + // Core_0_MESSAGE_PHASE: Clear writer_buffer status register + // Position of CORE_0_MESSAGE_MATCH field. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_MATCH_Pos = 0x0 + // Bit mask of CORE_0_MESSAGE_MATCH field. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_MATCH_Msk = 0x1 + // Bit CORE_0_MESSAGE_MATCH. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_MATCH = 0x1 + // Position of CORE_0_MESSAGE_EXPECT field. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_EXPECT_Pos = 0x1 + // Bit mask of CORE_0_MESSAGE_EXPECT field. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_EXPECT_Msk = 0x1e + // Position of CORE_0_MESSAGE_DATAPHASE field. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_DATAPHASE_Pos = 0x5 + // Bit mask of CORE_0_MESSAGE_DATAPHASE field. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_DATAPHASE_Msk = 0x20 + // Bit CORE_0_MESSAGE_DATAPHASE. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_DATAPHASE = 0x20 + // Position of CORE_0_MESSAGE_ADDRESSPHASE field. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_ADDRESSPHASE_Pos = 0x6 + // Bit mask of CORE_0_MESSAGE_ADDRESSPHASE field. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_ADDRESSPHASE_Msk = 0x40 + // Bit CORE_0_MESSAGE_ADDRESSPHASE. + WCL_Core_0_MESSAGE_PHASE_CORE_0_MESSAGE_ADDRESSPHASE = 0x40 + + // Core_0_World_TRIGGER_ADDR: Core_0 trigger address configuration Register + // Position of CORE_0_WORLD_TRIGGER_ADDR field. + WCL_Core_0_World_TRIGGER_ADDR_CORE_0_WORLD_TRIGGER_ADDR_Pos = 0x0 + // Bit mask of CORE_0_WORLD_TRIGGER_ADDR field. + WCL_Core_0_World_TRIGGER_ADDR_CORE_0_WORLD_TRIGGER_ADDR_Msk = 0xffffffff + + // Core_0_World_PREPARE: Core_0 prepare world configuration Register + // Position of CORE_0_WORLD_PREPARE field. + WCL_Core_0_World_PREPARE_CORE_0_WORLD_PREPARE_Pos = 0x0 + // Bit mask of CORE_0_WORLD_PREPARE field. + WCL_Core_0_World_PREPARE_CORE_0_WORLD_PREPARE_Msk = 0x3 + + // Core_0_World_UPDATE: Core_0 configuration update register + // Position of CORE_0_UPDATE field. + WCL_Core_0_World_UPDATE_CORE_0_UPDATE_Pos = 0x0 + // Bit mask of CORE_0_UPDATE field. + WCL_Core_0_World_UPDATE_CORE_0_UPDATE_Msk = 0xffffffff + + // Core_0_World_Cancel: Core_0 configuration cancel register + // Position of CORE_0_WORLD_CANCEL field. + WCL_Core_0_World_Cancel_CORE_0_WORLD_CANCEL_Pos = 0x0 + // Bit mask of CORE_0_WORLD_CANCEL field. + WCL_Core_0_World_Cancel_CORE_0_WORLD_CANCEL_Msk = 0xffffffff + + // Core_0_World_IRam0: Core_0 Iram0 world register + // Position of CORE_0_WORLD_IRAM0 field. + WCL_Core_0_World_IRam0_CORE_0_WORLD_IRAM0_Pos = 0x0 + // Bit mask of CORE_0_WORLD_IRAM0 field. + WCL_Core_0_World_IRam0_CORE_0_WORLD_IRAM0_Msk = 0x3 + + // Core_0_World_DRam0_PIF: Core_0 dram0 and PIF world register + // Position of CORE_0_WORLD_DRAM0_PIF field. + WCL_Core_0_World_DRam0_PIF_CORE_0_WORLD_DRAM0_PIF_Pos = 0x0 + // Bit mask of CORE_0_WORLD_DRAM0_PIF field. + WCL_Core_0_World_DRam0_PIF_CORE_0_WORLD_DRAM0_PIF_Msk = 0x3 + + // Core_0_World_Phase: Core_0 world status register + // Position of CORE_0_WORLD_PHASE field. + WCL_Core_0_World_Phase_CORE_0_WORLD_PHASE_Pos = 0x0 + // Bit mask of CORE_0_WORLD_PHASE field. + WCL_Core_0_World_Phase_CORE_0_WORLD_PHASE_Msk = 0x1 + // Bit CORE_0_WORLD_PHASE. + WCL_Core_0_World_Phase_CORE_0_WORLD_PHASE = 0x1 + + // Core_0_NMI_MASK_ENABLE: Core_0 NMI mask enable register + // Position of CORE_0_NMI_MASK_ENABLE field. + WCL_Core_0_NMI_MASK_ENABLE_CORE_0_NMI_MASK_ENABLE_Pos = 0x0 + // Bit mask of CORE_0_NMI_MASK_ENABLE field. + WCL_Core_0_NMI_MASK_ENABLE_CORE_0_NMI_MASK_ENABLE_Msk = 0xffffffff + + // Core_0_NMI_MASK_TRIGGER_ADDR: Core_0 NMI mask trigger address register + // Position of CORE_0_NMI_MASK_TRIGGER_ADDR field. + WCL_Core_0_NMI_MASK_TRIGGER_ADDR_CORE_0_NMI_MASK_TRIGGER_ADDR_Pos = 0x0 + // Bit mask of CORE_0_NMI_MASK_TRIGGER_ADDR field. + WCL_Core_0_NMI_MASK_TRIGGER_ADDR_CORE_0_NMI_MASK_TRIGGER_ADDR_Msk = 0xffffffff + + // Core_0_NMI_MASK_DISABLE: Core_0 NMI mask disable register + // Position of CORE_0_NMI_MASK_DISABLE field. + WCL_Core_0_NMI_MASK_DISABLE_CORE_0_NMI_MASK_DISABLE_Pos = 0x0 + // Bit mask of CORE_0_NMI_MASK_DISABLE field. + WCL_Core_0_NMI_MASK_DISABLE_CORE_0_NMI_MASK_DISABLE_Msk = 0xffffffff + + // Core_0_NMI_MASK_CANCLE: Core_0 NMI mask disable register + // Position of CORE_0_NMI_MASK_CANCEL field. + WCL_Core_0_NMI_MASK_CANCLE_CORE_0_NMI_MASK_CANCEL_Pos = 0x0 + // Bit mask of CORE_0_NMI_MASK_CANCEL field. + WCL_Core_0_NMI_MASK_CANCLE_CORE_0_NMI_MASK_CANCEL_Msk = 0xffffffff + + // Core_0_NMI_MASK: Core_0 NMI mask register + // Position of CORE_0_NMI_MASK field. + WCL_Core_0_NMI_MASK_CORE_0_NMI_MASK_Pos = 0x0 + // Bit mask of CORE_0_NMI_MASK field. + WCL_Core_0_NMI_MASK_CORE_0_NMI_MASK_Msk = 0x1 + // Bit CORE_0_NMI_MASK. + WCL_Core_0_NMI_MASK_CORE_0_NMI_MASK = 0x1 + + // Core_0_NMI_MASK_PHASE: Core_0 NMI mask phase register + // Position of CORE_0_NMI_MASK_PHASE field. + WCL_Core_0_NMI_MASK_PHASE_CORE_0_NMI_MASK_PHASE_Pos = 0x0 + // Bit mask of CORE_0_NMI_MASK_PHASE field. + WCL_Core_0_NMI_MASK_PHASE_CORE_0_NMI_MASK_PHASE_Msk = 0x1 + // Bit CORE_0_NMI_MASK_PHASE. + WCL_Core_0_NMI_MASK_PHASE_CORE_0_NMI_MASK_PHASE = 0x1 + + // Core_1_ENTRY_1_ADDR: Core_1 Entry 1 address configuration Register + // Position of CORE_1_ENTRY_1_ADDR field. + WCL_Core_1_ENTRY_1_ADDR_CORE_1_ENTRY_1_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_1_ADDR field. + WCL_Core_1_ENTRY_1_ADDR_CORE_1_ENTRY_1_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_2_ADDR: Core_1 Entry 2 address configuration Register + // Position of CORE_1_ENTRY_2_ADDR field. + WCL_Core_1_ENTRY_2_ADDR_CORE_1_ENTRY_2_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_2_ADDR field. + WCL_Core_1_ENTRY_2_ADDR_CORE_1_ENTRY_2_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_3_ADDR: Core_1 Entry 3 address configuration Register + // Position of CORE_1_ENTRY_3_ADDR field. + WCL_Core_1_ENTRY_3_ADDR_CORE_1_ENTRY_3_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_3_ADDR field. + WCL_Core_1_ENTRY_3_ADDR_CORE_1_ENTRY_3_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_4_ADDR: Core_1 Entry 4 address configuration Register + // Position of CORE_1_ENTRY_4_ADDR field. + WCL_Core_1_ENTRY_4_ADDR_CORE_1_ENTRY_4_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_4_ADDR field. + WCL_Core_1_ENTRY_4_ADDR_CORE_1_ENTRY_4_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_5_ADDR: Core_1 Entry 5 address configuration Register + // Position of CORE_1_ENTRY_5_ADDR field. + WCL_Core_1_ENTRY_5_ADDR_CORE_1_ENTRY_5_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_5_ADDR field. + WCL_Core_1_ENTRY_5_ADDR_CORE_1_ENTRY_5_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_6_ADDR: Core_1 Entry 6 address configuration Register + // Position of CORE_1_ENTRY_6_ADDR field. + WCL_Core_1_ENTRY_6_ADDR_CORE_1_ENTRY_6_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_6_ADDR field. + WCL_Core_1_ENTRY_6_ADDR_CORE_1_ENTRY_6_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_7_ADDR: Core_1 Entry 7 address configuration Register + // Position of CORE_1_ENTRY_7_ADDR field. + WCL_Core_1_ENTRY_7_ADDR_CORE_1_ENTRY_7_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_7_ADDR field. + WCL_Core_1_ENTRY_7_ADDR_CORE_1_ENTRY_7_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_8_ADDR: Core_1 Entry 8 address configuration Register + // Position of CORE_1_ENTRY_8_ADDR field. + WCL_Core_1_ENTRY_8_ADDR_CORE_1_ENTRY_8_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_8_ADDR field. + WCL_Core_1_ENTRY_8_ADDR_CORE_1_ENTRY_8_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_9_ADDR: Core_1 Entry 9 address configuration Register + // Position of CORE_1_ENTRY_9_ADDR field. + WCL_Core_1_ENTRY_9_ADDR_CORE_1_ENTRY_9_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_9_ADDR field. + WCL_Core_1_ENTRY_9_ADDR_CORE_1_ENTRY_9_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_10_ADDR: Core_1 Entry 10 address configuration Register + // Position of CORE_1_ENTRY_10_ADDR field. + WCL_Core_1_ENTRY_10_ADDR_CORE_1_ENTRY_10_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_10_ADDR field. + WCL_Core_1_ENTRY_10_ADDR_CORE_1_ENTRY_10_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_11_ADDR: Core_1 Entry 11 address configuration Register + // Position of CORE_1_ENTRY_11_ADDR field. + WCL_Core_1_ENTRY_11_ADDR_CORE_1_ENTRY_11_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_11_ADDR field. + WCL_Core_1_ENTRY_11_ADDR_CORE_1_ENTRY_11_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_12_ADDR: Core_1 Entry 12 address configuration Register + // Position of CORE_1_ENTRY_12_ADDR field. + WCL_Core_1_ENTRY_12_ADDR_CORE_1_ENTRY_12_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_12_ADDR field. + WCL_Core_1_ENTRY_12_ADDR_CORE_1_ENTRY_12_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_13_ADDR: Core_1 Entry 13 address configuration Register + // Position of CORE_1_ENTRY_13_ADDR field. + WCL_Core_1_ENTRY_13_ADDR_CORE_1_ENTRY_13_ADDR_Pos = 0x0 + // Bit mask of CORE_1_ENTRY_13_ADDR field. + WCL_Core_1_ENTRY_13_ADDR_CORE_1_ENTRY_13_ADDR_Msk = 0xffffffff + + // Core_1_ENTRY_CHECK: Core_1 Entry check configuration Register + // Position of CORE_1_ENTRY_CHECK field. + WCL_Core_1_ENTRY_CHECK_CORE_1_ENTRY_CHECK_Pos = 0x1 + // Bit mask of CORE_1_ENTRY_CHECK field. + WCL_Core_1_ENTRY_CHECK_CORE_1_ENTRY_CHECK_Msk = 0x3ffe + + // Core_1_STATUSTABLE1: Status register of world switch of entry 1 + // Position of CORE_1_FROM_WORLD_1 field. + WCL_Core_1_STATUSTABLE1_CORE_1_FROM_WORLD_1_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_1 field. + WCL_Core_1_STATUSTABLE1_CORE_1_FROM_WORLD_1_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_1. + WCL_Core_1_STATUSTABLE1_CORE_1_FROM_WORLD_1 = 0x1 + // Position of CORE_1_FROM_ENTRY_1 field. + WCL_Core_1_STATUSTABLE1_CORE_1_FROM_ENTRY_1_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_1 field. + WCL_Core_1_STATUSTABLE1_CORE_1_FROM_ENTRY_1_Msk = 0x1e + // Position of CORE_1_CURRENT_1 field. + WCL_Core_1_STATUSTABLE1_CORE_1_CURRENT_1_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_1 field. + WCL_Core_1_STATUSTABLE1_CORE_1_CURRENT_1_Msk = 0x20 + // Bit CORE_1_CURRENT_1. + WCL_Core_1_STATUSTABLE1_CORE_1_CURRENT_1 = 0x20 + + // Core_1_STATUSTABLE2: Status register of world switch of entry 2 + // Position of CORE_1_FROM_WORLD_2 field. + WCL_Core_1_STATUSTABLE2_CORE_1_FROM_WORLD_2_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_2 field. + WCL_Core_1_STATUSTABLE2_CORE_1_FROM_WORLD_2_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_2. + WCL_Core_1_STATUSTABLE2_CORE_1_FROM_WORLD_2 = 0x1 + // Position of CORE_1_FROM_ENTRY_2 field. + WCL_Core_1_STATUSTABLE2_CORE_1_FROM_ENTRY_2_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_2 field. + WCL_Core_1_STATUSTABLE2_CORE_1_FROM_ENTRY_2_Msk = 0x1e + // Position of CORE_1_CURRENT_2 field. + WCL_Core_1_STATUSTABLE2_CORE_1_CURRENT_2_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_2 field. + WCL_Core_1_STATUSTABLE2_CORE_1_CURRENT_2_Msk = 0x20 + // Bit CORE_1_CURRENT_2. + WCL_Core_1_STATUSTABLE2_CORE_1_CURRENT_2 = 0x20 + + // Core_1_STATUSTABLE3: Status register of world switch of entry 3 + // Position of CORE_1_FROM_WORLD_3 field. + WCL_Core_1_STATUSTABLE3_CORE_1_FROM_WORLD_3_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_3 field. + WCL_Core_1_STATUSTABLE3_CORE_1_FROM_WORLD_3_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_3. + WCL_Core_1_STATUSTABLE3_CORE_1_FROM_WORLD_3 = 0x1 + // Position of CORE_1_FROM_ENTRY_3 field. + WCL_Core_1_STATUSTABLE3_CORE_1_FROM_ENTRY_3_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_3 field. + WCL_Core_1_STATUSTABLE3_CORE_1_FROM_ENTRY_3_Msk = 0x1e + // Position of CORE_1_CURRENT_3 field. + WCL_Core_1_STATUSTABLE3_CORE_1_CURRENT_3_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_3 field. + WCL_Core_1_STATUSTABLE3_CORE_1_CURRENT_3_Msk = 0x20 + // Bit CORE_1_CURRENT_3. + WCL_Core_1_STATUSTABLE3_CORE_1_CURRENT_3 = 0x20 + + // Core_1_STATUSTABLE4: Status register of world switch of entry 4 + // Position of CORE_1_FROM_WORLD_4 field. + WCL_Core_1_STATUSTABLE4_CORE_1_FROM_WORLD_4_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_4 field. + WCL_Core_1_STATUSTABLE4_CORE_1_FROM_WORLD_4_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_4. + WCL_Core_1_STATUSTABLE4_CORE_1_FROM_WORLD_4 = 0x1 + // Position of CORE_1_FROM_ENTRY_4 field. + WCL_Core_1_STATUSTABLE4_CORE_1_FROM_ENTRY_4_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_4 field. + WCL_Core_1_STATUSTABLE4_CORE_1_FROM_ENTRY_4_Msk = 0x1e + // Position of CORE_1_CURRENT_4 field. + WCL_Core_1_STATUSTABLE4_CORE_1_CURRENT_4_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_4 field. + WCL_Core_1_STATUSTABLE4_CORE_1_CURRENT_4_Msk = 0x20 + // Bit CORE_1_CURRENT_4. + WCL_Core_1_STATUSTABLE4_CORE_1_CURRENT_4 = 0x20 + + // Core_1_STATUSTABLE5: Status register of world switch of entry 5 + // Position of CORE_1_FROM_WORLD_5 field. + WCL_Core_1_STATUSTABLE5_CORE_1_FROM_WORLD_5_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_5 field. + WCL_Core_1_STATUSTABLE5_CORE_1_FROM_WORLD_5_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_5. + WCL_Core_1_STATUSTABLE5_CORE_1_FROM_WORLD_5 = 0x1 + // Position of CORE_1_FROM_ENTRY_5 field. + WCL_Core_1_STATUSTABLE5_CORE_1_FROM_ENTRY_5_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_5 field. + WCL_Core_1_STATUSTABLE5_CORE_1_FROM_ENTRY_5_Msk = 0x1e + // Position of CORE_1_CURRENT_5 field. + WCL_Core_1_STATUSTABLE5_CORE_1_CURRENT_5_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_5 field. + WCL_Core_1_STATUSTABLE5_CORE_1_CURRENT_5_Msk = 0x20 + // Bit CORE_1_CURRENT_5. + WCL_Core_1_STATUSTABLE5_CORE_1_CURRENT_5 = 0x20 + + // Core_1_STATUSTABLE6: Status register of world switch of entry 6 + // Position of CORE_1_FROM_WORLD_6 field. + WCL_Core_1_STATUSTABLE6_CORE_1_FROM_WORLD_6_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_6 field. + WCL_Core_1_STATUSTABLE6_CORE_1_FROM_WORLD_6_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_6. + WCL_Core_1_STATUSTABLE6_CORE_1_FROM_WORLD_6 = 0x1 + // Position of CORE_1_FROM_ENTRY_6 field. + WCL_Core_1_STATUSTABLE6_CORE_1_FROM_ENTRY_6_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_6 field. + WCL_Core_1_STATUSTABLE6_CORE_1_FROM_ENTRY_6_Msk = 0x1e + // Position of CORE_1_CURRENT_6 field. + WCL_Core_1_STATUSTABLE6_CORE_1_CURRENT_6_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_6 field. + WCL_Core_1_STATUSTABLE6_CORE_1_CURRENT_6_Msk = 0x20 + // Bit CORE_1_CURRENT_6. + WCL_Core_1_STATUSTABLE6_CORE_1_CURRENT_6 = 0x20 + + // Core_1_STATUSTABLE7: Status register of world switch of entry 7 + // Position of CORE_1_FROM_WORLD_7 field. + WCL_Core_1_STATUSTABLE7_CORE_1_FROM_WORLD_7_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_7 field. + WCL_Core_1_STATUSTABLE7_CORE_1_FROM_WORLD_7_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_7. + WCL_Core_1_STATUSTABLE7_CORE_1_FROM_WORLD_7 = 0x1 + // Position of CORE_1_FROM_ENTRY_7 field. + WCL_Core_1_STATUSTABLE7_CORE_1_FROM_ENTRY_7_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_7 field. + WCL_Core_1_STATUSTABLE7_CORE_1_FROM_ENTRY_7_Msk = 0x1e + // Position of CORE_1_CURRENT_7 field. + WCL_Core_1_STATUSTABLE7_CORE_1_CURRENT_7_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_7 field. + WCL_Core_1_STATUSTABLE7_CORE_1_CURRENT_7_Msk = 0x20 + // Bit CORE_1_CURRENT_7. + WCL_Core_1_STATUSTABLE7_CORE_1_CURRENT_7 = 0x20 + + // Core_1_STATUSTABLE8: Status register of world switch of entry 8 + // Position of CORE_1_FROM_WORLD_8 field. + WCL_Core_1_STATUSTABLE8_CORE_1_FROM_WORLD_8_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_8 field. + WCL_Core_1_STATUSTABLE8_CORE_1_FROM_WORLD_8_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_8. + WCL_Core_1_STATUSTABLE8_CORE_1_FROM_WORLD_8 = 0x1 + // Position of CORE_1_FROM_ENTRY_8 field. + WCL_Core_1_STATUSTABLE8_CORE_1_FROM_ENTRY_8_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_8 field. + WCL_Core_1_STATUSTABLE8_CORE_1_FROM_ENTRY_8_Msk = 0x1e + // Position of CORE_1_CURRENT_8 field. + WCL_Core_1_STATUSTABLE8_CORE_1_CURRENT_8_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_8 field. + WCL_Core_1_STATUSTABLE8_CORE_1_CURRENT_8_Msk = 0x20 + // Bit CORE_1_CURRENT_8. + WCL_Core_1_STATUSTABLE8_CORE_1_CURRENT_8 = 0x20 + + // Core_1_STATUSTABLE9: Status register of world switch of entry 9 + // Position of CORE_1_FROM_WORLD_9 field. + WCL_Core_1_STATUSTABLE9_CORE_1_FROM_WORLD_9_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_9 field. + WCL_Core_1_STATUSTABLE9_CORE_1_FROM_WORLD_9_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_9. + WCL_Core_1_STATUSTABLE9_CORE_1_FROM_WORLD_9 = 0x1 + // Position of CORE_1_FROM_ENTRY_9 field. + WCL_Core_1_STATUSTABLE9_CORE_1_FROM_ENTRY_9_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_9 field. + WCL_Core_1_STATUSTABLE9_CORE_1_FROM_ENTRY_9_Msk = 0x1e + // Position of CORE_1_CURRENT_9 field. + WCL_Core_1_STATUSTABLE9_CORE_1_CURRENT_9_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_9 field. + WCL_Core_1_STATUSTABLE9_CORE_1_CURRENT_9_Msk = 0x20 + // Bit CORE_1_CURRENT_9. + WCL_Core_1_STATUSTABLE9_CORE_1_CURRENT_9 = 0x20 + + // Core_1_STATUSTABLE10: Status register of world switch of entry 10 + // Position of CORE_1_FROM_WORLD_10 field. + WCL_Core_1_STATUSTABLE10_CORE_1_FROM_WORLD_10_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_10 field. + WCL_Core_1_STATUSTABLE10_CORE_1_FROM_WORLD_10_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_10. + WCL_Core_1_STATUSTABLE10_CORE_1_FROM_WORLD_10 = 0x1 + // Position of CORE_1_FROM_ENTRY_10 field. + WCL_Core_1_STATUSTABLE10_CORE_1_FROM_ENTRY_10_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_10 field. + WCL_Core_1_STATUSTABLE10_CORE_1_FROM_ENTRY_10_Msk = 0x1e + // Position of CORE_1_CURRENT_10 field. + WCL_Core_1_STATUSTABLE10_CORE_1_CURRENT_10_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_10 field. + WCL_Core_1_STATUSTABLE10_CORE_1_CURRENT_10_Msk = 0x20 + // Bit CORE_1_CURRENT_10. + WCL_Core_1_STATUSTABLE10_CORE_1_CURRENT_10 = 0x20 + + // Core_1_STATUSTABLE11: Status register of world switch of entry 11 + // Position of CORE_1_FROM_WORLD_11 field. + WCL_Core_1_STATUSTABLE11_CORE_1_FROM_WORLD_11_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_11 field. + WCL_Core_1_STATUSTABLE11_CORE_1_FROM_WORLD_11_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_11. + WCL_Core_1_STATUSTABLE11_CORE_1_FROM_WORLD_11 = 0x1 + // Position of CORE_1_FROM_ENTRY_11 field. + WCL_Core_1_STATUSTABLE11_CORE_1_FROM_ENTRY_11_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_11 field. + WCL_Core_1_STATUSTABLE11_CORE_1_FROM_ENTRY_11_Msk = 0x1e + // Position of CORE_1_CURRENT_11 field. + WCL_Core_1_STATUSTABLE11_CORE_1_CURRENT_11_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_11 field. + WCL_Core_1_STATUSTABLE11_CORE_1_CURRENT_11_Msk = 0x20 + // Bit CORE_1_CURRENT_11. + WCL_Core_1_STATUSTABLE11_CORE_1_CURRENT_11 = 0x20 + + // Core_1_STATUSTABLE12: Status register of world switch of entry 12 + // Position of CORE_1_FROM_WORLD_12 field. + WCL_Core_1_STATUSTABLE12_CORE_1_FROM_WORLD_12_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_12 field. + WCL_Core_1_STATUSTABLE12_CORE_1_FROM_WORLD_12_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_12. + WCL_Core_1_STATUSTABLE12_CORE_1_FROM_WORLD_12 = 0x1 + // Position of CORE_1_FROM_ENTRY_12 field. + WCL_Core_1_STATUSTABLE12_CORE_1_FROM_ENTRY_12_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_12 field. + WCL_Core_1_STATUSTABLE12_CORE_1_FROM_ENTRY_12_Msk = 0x1e + // Position of CORE_1_CURRENT_12 field. + WCL_Core_1_STATUSTABLE12_CORE_1_CURRENT_12_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_12 field. + WCL_Core_1_STATUSTABLE12_CORE_1_CURRENT_12_Msk = 0x20 + // Bit CORE_1_CURRENT_12. + WCL_Core_1_STATUSTABLE12_CORE_1_CURRENT_12 = 0x20 + + // Core_1_STATUSTABLE13: Status register of world switch of entry 13 + // Position of CORE_1_FROM_WORLD_13 field. + WCL_Core_1_STATUSTABLE13_CORE_1_FROM_WORLD_13_Pos = 0x0 + // Bit mask of CORE_1_FROM_WORLD_13 field. + WCL_Core_1_STATUSTABLE13_CORE_1_FROM_WORLD_13_Msk = 0x1 + // Bit CORE_1_FROM_WORLD_13. + WCL_Core_1_STATUSTABLE13_CORE_1_FROM_WORLD_13 = 0x1 + // Position of CORE_1_FROM_ENTRY_13 field. + WCL_Core_1_STATUSTABLE13_CORE_1_FROM_ENTRY_13_Pos = 0x1 + // Bit mask of CORE_1_FROM_ENTRY_13 field. + WCL_Core_1_STATUSTABLE13_CORE_1_FROM_ENTRY_13_Msk = 0x1e + // Position of CORE_1_CURRENT_13 field. + WCL_Core_1_STATUSTABLE13_CORE_1_CURRENT_13_Pos = 0x5 + // Bit mask of CORE_1_CURRENT_13 field. + WCL_Core_1_STATUSTABLE13_CORE_1_CURRENT_13_Msk = 0x20 + // Bit CORE_1_CURRENT_13. + WCL_Core_1_STATUSTABLE13_CORE_1_CURRENT_13 = 0x20 + + // Core_1_STATUSTABLE_CURRENT: Status register of statustable current + // Position of CORE_1_STATUSTABLE_CURRENT field. + WCL_Core_1_STATUSTABLE_CURRENT_CORE_1_STATUSTABLE_CURRENT_Pos = 0x1 + // Bit mask of CORE_1_STATUSTABLE_CURRENT field. + WCL_Core_1_STATUSTABLE_CURRENT_CORE_1_STATUSTABLE_CURRENT_Msk = 0x3ffe + + // Core_1_MESSAGE_ADDR: Clear writer_buffer write address configuration register + // Position of CORE_1_MESSAGE_ADDR field. + WCL_Core_1_MESSAGE_ADDR_CORE_1_MESSAGE_ADDR_Pos = 0x0 + // Bit mask of CORE_1_MESSAGE_ADDR field. + WCL_Core_1_MESSAGE_ADDR_CORE_1_MESSAGE_ADDR_Msk = 0xffffffff + + // Core_1_MESSAGE_MAX: Clear writer_buffer write number configuration register + // Position of CORE_1_MESSAGE_MAX field. + WCL_Core_1_MESSAGE_MAX_CORE_1_MESSAGE_MAX_Pos = 0x0 + // Bit mask of CORE_1_MESSAGE_MAX field. + WCL_Core_1_MESSAGE_MAX_CORE_1_MESSAGE_MAX_Msk = 0xf + + // Core_1_MESSAGE_PHASE: Clear writer_buffer status register + // Position of CORE_1_MESSAGE_MATCH field. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_MATCH_Pos = 0x0 + // Bit mask of CORE_1_MESSAGE_MATCH field. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_MATCH_Msk = 0x1 + // Bit CORE_1_MESSAGE_MATCH. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_MATCH = 0x1 + // Position of CORE_1_MESSAGE_EXPECT field. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_EXPECT_Pos = 0x1 + // Bit mask of CORE_1_MESSAGE_EXPECT field. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_EXPECT_Msk = 0x1e + // Position of CORE_1_MESSAGE_DATAPHASE field. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_DATAPHASE_Pos = 0x5 + // Bit mask of CORE_1_MESSAGE_DATAPHASE field. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_DATAPHASE_Msk = 0x20 + // Bit CORE_1_MESSAGE_DATAPHASE. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_DATAPHASE = 0x20 + // Position of CORE_1_MESSAGE_ADDRESSPHASE field. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_ADDRESSPHASE_Pos = 0x6 + // Bit mask of CORE_1_MESSAGE_ADDRESSPHASE field. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_ADDRESSPHASE_Msk = 0x40 + // Bit CORE_1_MESSAGE_ADDRESSPHASE. + WCL_Core_1_MESSAGE_PHASE_CORE_1_MESSAGE_ADDRESSPHASE = 0x40 + + // Core_1_World_TRIGGER_ADDR: Core_1 trigger address configuration Register + // Position of CORE_1_WORLD_TRIGGER_ADDR field. + WCL_Core_1_World_TRIGGER_ADDR_CORE_1_WORLD_TRIGGER_ADDR_Pos = 0x0 + // Bit mask of CORE_1_WORLD_TRIGGER_ADDR field. + WCL_Core_1_World_TRIGGER_ADDR_CORE_1_WORLD_TRIGGER_ADDR_Msk = 0xffffffff + + // Core_1_World_PREPARE: Core_1 prepare world configuration Register + // Position of CORE_1_WORLD_PREPARE field. + WCL_Core_1_World_PREPARE_CORE_1_WORLD_PREPARE_Pos = 0x0 + // Bit mask of CORE_1_WORLD_PREPARE field. + WCL_Core_1_World_PREPARE_CORE_1_WORLD_PREPARE_Msk = 0x3 + + // Core_1_World_UPDATE: Core_1 configuration update register + // Position of CORE_1_UPDATE field. + WCL_Core_1_World_UPDATE_CORE_1_UPDATE_Pos = 0x0 + // Bit mask of CORE_1_UPDATE field. + WCL_Core_1_World_UPDATE_CORE_1_UPDATE_Msk = 0xffffffff + + // Core_1_World_Cancel: Core_1 configuration cancel register + // Position of CORE_1_WORLD_CANCEL field. + WCL_Core_1_World_Cancel_CORE_1_WORLD_CANCEL_Pos = 0x0 + // Bit mask of CORE_1_WORLD_CANCEL field. + WCL_Core_1_World_Cancel_CORE_1_WORLD_CANCEL_Msk = 0xffffffff + + // Core_1_World_IRam0: Core_1 Iram0 world register + // Position of CORE_1_WORLD_IRAM0 field. + WCL_Core_1_World_IRam0_CORE_1_WORLD_IRAM0_Pos = 0x0 + // Bit mask of CORE_1_WORLD_IRAM0 field. + WCL_Core_1_World_IRam0_CORE_1_WORLD_IRAM0_Msk = 0x3 + + // Core_1_World_DRam0_PIF: Core_1 dram0 and PIF world register + // Position of CORE_1_WORLD_DRAM0_PIF field. + WCL_Core_1_World_DRam0_PIF_CORE_1_WORLD_DRAM0_PIF_Pos = 0x0 + // Bit mask of CORE_1_WORLD_DRAM0_PIF field. + WCL_Core_1_World_DRam0_PIF_CORE_1_WORLD_DRAM0_PIF_Msk = 0x3 + + // Core_1_World_Phase: Core_0 world status register + // Position of CORE_1_WORLD_PHASE field. + WCL_Core_1_World_Phase_CORE_1_WORLD_PHASE_Pos = 0x0 + // Bit mask of CORE_1_WORLD_PHASE field. + WCL_Core_1_World_Phase_CORE_1_WORLD_PHASE_Msk = 0x1 + // Bit CORE_1_WORLD_PHASE. + WCL_Core_1_World_Phase_CORE_1_WORLD_PHASE = 0x1 + + // Core_1_NMI_MASK_ENABLE: Core_1 NMI mask enable register + // Position of CORE_1_NMI_MASK_ENABLE field. + WCL_Core_1_NMI_MASK_ENABLE_CORE_1_NMI_MASK_ENABLE_Pos = 0x0 + // Bit mask of CORE_1_NMI_MASK_ENABLE field. + WCL_Core_1_NMI_MASK_ENABLE_CORE_1_NMI_MASK_ENABLE_Msk = 0xffffffff + + // Core_1_NMI_MASK_TRIGGER_ADDR: Core_1 NMI mask trigger addr register + // Position of CORE_1_NMI_MASK_TRIGGER_ADDR field. + WCL_Core_1_NMI_MASK_TRIGGER_ADDR_CORE_1_NMI_MASK_TRIGGER_ADDR_Pos = 0x0 + // Bit mask of CORE_1_NMI_MASK_TRIGGER_ADDR field. + WCL_Core_1_NMI_MASK_TRIGGER_ADDR_CORE_1_NMI_MASK_TRIGGER_ADDR_Msk = 0xffffffff + + // Core_1_NMI_MASK_DISABLE: Core_1 NMI mask disable register + // Position of CORE_1_NMI_MASK_DISABLE field. + WCL_Core_1_NMI_MASK_DISABLE_CORE_1_NMI_MASK_DISABLE_Pos = 0x0 + // Bit mask of CORE_1_NMI_MASK_DISABLE field. + WCL_Core_1_NMI_MASK_DISABLE_CORE_1_NMI_MASK_DISABLE_Msk = 0xffffffff + + // Core_1_NMI_MASK_CANCLE: Core_1 NMI mask disable register + // Position of CORE_1_NMI_MASK_CANCEL field. + WCL_Core_1_NMI_MASK_CANCLE_CORE_1_NMI_MASK_CANCEL_Pos = 0x0 + // Bit mask of CORE_1_NMI_MASK_CANCEL field. + WCL_Core_1_NMI_MASK_CANCLE_CORE_1_NMI_MASK_CANCEL_Msk = 0xffffffff + + // Core_1_NMI_MASK: Core_1 NMI mask register + // Position of CORE_1_NMI_MASK field. + WCL_Core_1_NMI_MASK_CORE_1_NMI_MASK_Pos = 0x0 + // Bit mask of CORE_1_NMI_MASK field. + WCL_Core_1_NMI_MASK_CORE_1_NMI_MASK_Msk = 0x1 + // Bit CORE_1_NMI_MASK. + WCL_Core_1_NMI_MASK_CORE_1_NMI_MASK = 0x1 + + // Core_1_NMI_MASK_PHASE: Core_1 NMI mask phase register + // Position of CORE_1_NMI_MASK_PHASE field. + WCL_Core_1_NMI_MASK_PHASE_CORE_1_NMI_MASK_PHASE_Pos = 0x0 + // Bit mask of CORE_1_NMI_MASK_PHASE field. + WCL_Core_1_NMI_MASK_PHASE_CORE_1_NMI_MASK_PHASE_Msk = 0x1 + // Bit CORE_1_NMI_MASK_PHASE. + WCL_Core_1_NMI_MASK_PHASE_CORE_1_NMI_MASK_PHASE = 0x1 +) + +// Constants for XTS_AES: XTS-AES-128 Flash Encryption +const ( + // PLAIN_0: Plaintext register %s + // Position of PLAIN field. + XTS_AES_PLAIN_PLAIN_Pos = 0x0 + // Bit mask of PLAIN field. + XTS_AES_PLAIN_PLAIN_Msk = 0xffffffff + + // LINESIZE: XTS-AES line-size register + // Position of LINESIZE field. + XTS_AES_LINESIZE_LINESIZE_Pos = 0x0 + // Bit mask of LINESIZE field. + XTS_AES_LINESIZE_LINESIZE_Msk = 0x1 + // Bit LINESIZE. + XTS_AES_LINESIZE_LINESIZE = 0x1 + + // DESTINATION: XTS-AES destination register + // Position of DESTINATION field. + XTS_AES_DESTINATION_DESTINATION_Pos = 0x0 + // Bit mask of DESTINATION field. + XTS_AES_DESTINATION_DESTINATION_Msk = 0x1 + // Bit DESTINATION. + XTS_AES_DESTINATION_DESTINATION = 0x1 + + // PHYSICAL_ADDRESS: physical address + // Position of PHYSICAL_ADDRESS field. + XTS_AES_PHYSICAL_ADDRESS_PHYSICAL_ADDRESS_Pos = 0x0 + // Bit mask of PHYSICAL_ADDRESS field. + XTS_AES_PHYSICAL_ADDRESS_PHYSICAL_ADDRESS_Msk = 0x3fffffff + + // TRIGGER: XTS-AES trigger register + // Position of TRIGGER field. + XTS_AES_TRIGGER_TRIGGER_Pos = 0x0 + // Bit mask of TRIGGER field. + XTS_AES_TRIGGER_TRIGGER_Msk = 0x1 + // Bit TRIGGER. + XTS_AES_TRIGGER_TRIGGER = 0x1 + + // RELEASE: XTS-AES release control register + // Position of RELEASE field. + XTS_AES_RELEASE_RELEASE_Pos = 0x0 + // Bit mask of RELEASE field. + XTS_AES_RELEASE_RELEASE_Msk = 0x1 + // Bit RELEASE. + XTS_AES_RELEASE_RELEASE = 0x1 + + // DESTROY: XTS-AES destroy control register + // Position of DESTROY field. + XTS_AES_DESTROY_DESTROY_Pos = 0x0 + // Bit mask of DESTROY field. + XTS_AES_DESTROY_DESTROY_Msk = 0x1 + // Bit DESTROY. + XTS_AES_DESTROY_DESTROY = 0x1 + + // STATE: XTS-AES status register + // Position of STATE field. + XTS_AES_STATE_STATE_Pos = 0x0 + // Bit mask of STATE field. + XTS_AES_STATE_STATE_Msk = 0x3 + + // DATE: XTS-AES version control register + // Position of DATE field. + XTS_AES_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + XTS_AES_DATE_DATE_Msk = 0x3fffffff +) diff --git a/emb/device/esp/esp32s3ulp.go b/emb/device/esp/esp32s3ulp.go new file mode 100644 index 0000000..b2421fb --- /dev/null +++ b/emb/device/esp/esp32s3ulp.go @@ -0,0 +1,6647 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp32s3-ulp.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif + +//go:build esp && esp32s3ulp + +/* +// 32-bit RISC-V MCU +*/ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "ESP32-S3-ULP" + CPU = "RV32IMC" + FPUPresent = false + NVICPrioBits = 4 +) + +// Interrupt numbers. +const ( + // SENS Peripheral + IRQ_TOUCH_DONE_INT = 0 + + // SENS Peripheral + IRQ_TOUCH_INACTIVE_INT = 1 + + // SENS Peripheral + IRQ_TOUCH_ACTIVE_INT = 2 + + // SENS Peripheral + IRQ_SARADC1_DONE_INT = 3 + + // SENS Peripheral + IRQ_SARADC2_DONE_INT = 4 + + // SENS Peripheral + IRQ_TSENS_DONE_INT = 5 + + // Real-Time Clock Control + IRQ_RISCV_START_INT = 6 + + // Real-Time Clock Control + IRQ_SW_INT = 7 + + // Real-Time Clock Control + IRQ_SWD_INT = 8 + + // SENS Peripheral + IRQ_TOUCH_TIME_OUT_INT = 9 + + // SENS Peripheral + IRQ_TOUCH_APPROACH_LOOP_DONE_INT = 10 + + // SENS Peripheral + IRQ_TOUCH_SCAN_DONE_INT = 11 + + // Highest interrupt number on this device. + IRQ_max = 11 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + case IRQ_TOUCH_DONE_INT: + callHandlers(IRQ_TOUCH_DONE_INT) + case IRQ_TOUCH_INACTIVE_INT: + callHandlers(IRQ_TOUCH_INACTIVE_INT) + case IRQ_TOUCH_ACTIVE_INT: + callHandlers(IRQ_TOUCH_ACTIVE_INT) + case IRQ_SARADC1_DONE_INT: + callHandlers(IRQ_SARADC1_DONE_INT) + case IRQ_SARADC2_DONE_INT: + callHandlers(IRQ_SARADC2_DONE_INT) + case IRQ_TSENS_DONE_INT: + callHandlers(IRQ_TSENS_DONE_INT) + case IRQ_RISCV_START_INT: + callHandlers(IRQ_RISCV_START_INT) + case IRQ_SW_INT: + callHandlers(IRQ_SW_INT) + case IRQ_SWD_INT: + callHandlers(IRQ_SWD_INT) + case IRQ_TOUCH_TIME_OUT_INT: + callHandlers(IRQ_TOUCH_TIME_OUT_INT) + case IRQ_TOUCH_APPROACH_LOOP_DONE_INT: + callHandlers(IRQ_TOUCH_APPROACH_LOOP_DONE_INT) + case IRQ_TOUCH_SCAN_DONE_INT: + callHandlers(IRQ_TOUCH_SCAN_DONE_INT) + } +} + +// Peripherals. +var ( + // Real-Time Clock Control + RTC_CNTL = (*RTC_CNTL_Type)(unsafe.Pointer(uintptr(0x8000))) + + // Low-power I2C (Inter-Integrated Circuit) Controller + RTC_I2C = (*RTC_I2C_Type)(unsafe.Pointer(uintptr(0xec00))) + + // Low-power Input/Output + RTC_IO = (*RTC_IO_Type)(unsafe.Pointer(uintptr(0xa400))) + + // SENS Peripheral + SENS = (*SENS_Type)(unsafe.Pointer(uintptr(0xc800))) +) + +// Real-Time Clock Control +type RTC_CNTL_Type struct { + _ [252]byte + RTC_ULP_CP_TIMER volatile.Register32 // 0xFC + RTC_ULP_CP_CTRL volatile.Register32 // 0x100 + RTC_COCPU_CTRL volatile.Register32 // 0x104 + _ [44]byte + RTC_ULP_CP_TIMER_1 volatile.Register32 // 0x134 +} + +// RTC_CNTL.RTC_ULP_CP_TIMER: configure ulp +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_TIMER_ULP_CP_PC_INIT(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_TIMER.Reg)&^(0x7ff)|value) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_TIMER_ULP_CP_PC_INIT() uint32 { + return volatile.LoadUint32(&o.RTC_ULP_CP_TIMER.Reg) & 0x7ff +} +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_TIMER.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_TIMER.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_TIMER.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_TIMER.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_TIMER.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_TIMER.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_TIMER.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.RTC_ULP_CP_CTRL: configure ulp +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg)&^(0x7ff)|value) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT() uint32 { + return volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg) & 0x7ff +} +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg)&^(0x3ff800)|value<<11) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg) & 0x3ff800) >> 11 +} +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_CTRL_ULP_CP_CLK_FO(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_CTRL_ULP_CP_CLK_FO() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_CTRL_ULP_CP_RESET(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_CTRL_ULP_CP_RESET() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_CTRL_ULP_CP_START_TOP(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_CTRL.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_CTRL_ULP_CP_START_TOP() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_CNTL.RTC_COCPU_CTRL: configure ulp-riscv +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_CLK_FO(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x1)|value) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_CLK_FO() uint32 { + return volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x1 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_START_2_RESET_DIS(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x7e)|value<<1) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_START_2_RESET_DIS() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x7e) >> 1 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_START_2_INTR_EN(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x1f80)|value<<7) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_START_2_INTR_EN() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x1f80) >> 7 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_SHUT(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_SHUT() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x2000) >> 13 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x3fc000)|value<<14) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x3fc000) >> 14 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_SHUT_RESET_EN(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_SHUT_RESET_EN() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x400000) >> 22 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x800000) >> 23 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_DONE_FORCE(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_DONE_FORCE() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_DONE(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_DONE() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_SW_INT_TRIGGER(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_SW_INT_TRIGGER() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *RTC_CNTL_Type) SetRTC_COCPU_CTRL_COCPU_CLKGATE_EN(value uint32) { + volatile.StoreUint32(&o.RTC_COCPU_CTRL.Reg, volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_CNTL_Type) GetRTC_COCPU_CTRL_COCPU_CLKGATE_EN() uint32 { + return (volatile.LoadUint32(&o.RTC_COCPU_CTRL.Reg) & 0x8000000) >> 27 +} + +// RTC_CNTL.RTC_ULP_CP_TIMER_1: configure ulp sleep time +func (o *RTC_CNTL_Type) SetRTC_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE(value uint32) { + volatile.StoreUint32(&o.RTC_ULP_CP_TIMER_1.Reg, volatile.LoadUint32(&o.RTC_ULP_CP_TIMER_1.Reg)&^(0xffffff00)|value<<8) +} +func (o *RTC_CNTL_Type) GetRTC_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE() uint32 { + return (volatile.LoadUint32(&o.RTC_ULP_CP_TIMER_1.Reg) & 0xffffff00) >> 8 +} + +// Low-power I2C (Inter-Integrated Circuit) Controller +type RTC_I2C_Type struct { + SCL_LOW volatile.Register32 // 0x0 + CTRL volatile.Register32 // 0x4 + STATUS volatile.Register32 // 0x8 + TO volatile.Register32 // 0xC + SLAVE_ADDR volatile.Register32 // 0x10 + SCL_HIGH volatile.Register32 // 0x14 + SDA_DUTY volatile.Register32 // 0x18 + SCL_START_PERIOD volatile.Register32 // 0x1C + SCL_STOP_PERIOD volatile.Register32 // 0x20 + INT_CLR volatile.Register32 // 0x24 + INT_RAW volatile.Register32 // 0x28 + INT_ST volatile.Register32 // 0x2C + INT_ENA volatile.Register32 // 0x30 + DATA volatile.Register32 // 0x34 + CMD0 volatile.Register32 // 0x38 + CMD1 volatile.Register32 // 0x3C + CMD2 volatile.Register32 // 0x40 + CMD3 volatile.Register32 // 0x44 + CMD4 volatile.Register32 // 0x48 + CMD5 volatile.Register32 // 0x4C + CMD6 volatile.Register32 // 0x50 + CMD7 volatile.Register32 // 0x54 + CMD8 volatile.Register32 // 0x58 + CMD9 volatile.Register32 // 0x5C + CMD10 volatile.Register32 // 0x60 + CMD11 volatile.Register32 // 0x64 + CMD12 volatile.Register32 // 0x68 + CMD13 volatile.Register32 // 0x6C + CMD14 volatile.Register32 // 0x70 + CMD15 volatile.Register32 // 0x74 + _ [132]byte + DATE volatile.Register32 // 0xFC +} + +// RTC_I2C.SCL_LOW: configure low scl period +func (o *RTC_I2C_Type) SetSCL_LOW_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_LOW.Reg, volatile.LoadUint32(&o.SCL_LOW.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_LOW_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_LOW.Reg) & 0xfffff +} + +// RTC_I2C.CTRL: configure i2c ctrl +func (o *RTC_I2C_Type) SetCTRL_SDA_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetCTRL_SDA_FORCE_OUT() uint32 { + return volatile.LoadUint32(&o.CTRL.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetCTRL_SCL_FORCE_OUT(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetCTRL_SCL_FORCE_OUT() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetCTRL_MS_MODE(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetCTRL_MS_MODE() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetCTRL_TRANS_START(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetCTRL_TRANS_START() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetCTRL_TX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetCTRL_TX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetCTRL_RX_LSB_FIRST(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetCTRL_RX_LSB_FIRST() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetCTRL_I2C_CTRL_CLK_GATE_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *RTC_I2C_Type) GetCTRL_I2C_CTRL_CLK_GATE_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20000000) >> 29 +} +func (o *RTC_I2C_Type) SetCTRL_I2C_RESET(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40000000)|value<<30) +} +func (o *RTC_I2C_Type) GetCTRL_I2C_RESET() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40000000) >> 30 +} +func (o *RTC_I2C_Type) SetCTRL_I2CCLK_EN(value uint32) { + volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCTRL_I2CCLK_EN() uint32 { + return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.STATUS: get i2c status +func (o *RTC_I2C_Type) SetSTATUS_ACK_REC(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetSTATUS_ACK_REC() uint32 { + return volatile.LoadUint32(&o.STATUS.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetSTATUS_SLAVE_RW(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetSTATUS_SLAVE_RW() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetSTATUS_ARB_LOST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetSTATUS_ARB_LOST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetSTATUS_BUS_BUSY(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetSTATUS_BUS_BUSY() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetSTATUS_SLAVE_ADDRESSED(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetSTATUS_SLAVE_ADDRESSED() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetSTATUS_BYTE_TRANS(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetSTATUS_BYTE_TRANS() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetSTATUS_OP_CNT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xc0)|value<<6) +} +func (o *RTC_I2C_Type) GetSTATUS_OP_CNT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xc0) >> 6 +} +func (o *RTC_I2C_Type) SetSTATUS_SHIFT(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *RTC_I2C_Type) GetSTATUS_SHIFT() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0xff0000) >> 16 +} +func (o *RTC_I2C_Type) SetSTATUS_SCL_MAIN_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x7000000)|value<<24) +} +func (o *RTC_I2C_Type) GetSTATUS_SCL_MAIN_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x7000000) >> 24 +} +func (o *RTC_I2C_Type) SetSTATUS_SCL_STATE_LAST(value uint32) { + volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x70000000)|value<<28) +} +func (o *RTC_I2C_Type) GetSTATUS_SCL_STATE_LAST() uint32 { + return (volatile.LoadUint32(&o.STATUS.Reg) & 0x70000000) >> 28 +} + +// RTC_I2C.TO: configure time out +func (o *RTC_I2C_Type) SetTO_TIME_OUT(value uint32) { + volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetTO_TIME_OUT() uint32 { + return volatile.LoadUint32(&o.TO.Reg) & 0xfffff +} + +// RTC_I2C.SLAVE_ADDR: configure slave id +func (o *RTC_I2C_Type) SetSLAVE_ADDR(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR() uint32 { + return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff +} +func (o *RTC_I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) { + volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 { + return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.SCL_HIGH: configure high scl period +func (o *RTC_I2C_Type) SetSCL_HIGH_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_HIGH.Reg, volatile.LoadUint32(&o.SCL_HIGH.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_HIGH_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_HIGH.Reg) & 0xfffff +} + +// RTC_I2C.SDA_DUTY: configure sda duty +func (o *RTC_I2C_Type) SetSDA_DUTY_NUM(value uint32) { + volatile.StoreUint32(&o.SDA_DUTY.Reg, volatile.LoadUint32(&o.SDA_DUTY.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSDA_DUTY_NUM() uint32 { + return volatile.LoadUint32(&o.SDA_DUTY.Reg) & 0xfffff +} + +// RTC_I2C.SCL_START_PERIOD: configure scl start period +func (o *RTC_I2C_Type) SetSCL_START_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_START_PERIOD.Reg, volatile.LoadUint32(&o.SCL_START_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_START_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_START_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.SCL_STOP_PERIOD: configure scl stop period +func (o *RTC_I2C_Type) SetSCL_STOP_PERIOD(value uint32) { + volatile.StoreUint32(&o.SCL_STOP_PERIOD.Reg, volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg)&^(0xfffff)|value) +} +func (o *RTC_I2C_Type) GetSCL_STOP_PERIOD() uint32 { + return volatile.LoadUint32(&o.SCL_STOP_PERIOD.Reg) & 0xfffff +} + +// RTC_I2C.INT_CLR: interrupt clear register +func (o *RTC_I2C_Type) SetINT_CLR_SLAVE_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_CLR_SLAVE_TRAN_COMP_INT_CLR() uint32 { + return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_CLR_MASTER_TRAN_COMP_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_CLR_MASTER_TRAN_COMP_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_CLR_ACK_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_CLR_ACK_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_CLR_RX_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_CLR_RX_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_CLR_TX_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_CLR_TX_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_CLR_DETECT_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_CLR_DETECT_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_RAW: interrupt raw register +func (o *RTC_I2C_Type) SetINT_RAW_SLAVE_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_RAW_SLAVE_TRAN_COMP_INT_RAW() uint32 { + return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_RAW_MASTER_TRAN_COMP_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_RAW_MASTER_TRAN_COMP_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_RAW_ACK_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_RAW_ACK_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_RAW_RX_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_RAW_RX_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_RAW_TX_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_RAW_TX_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_RAW_DETECT_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_RAW_DETECT_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_ST: interrupt state register +func (o *RTC_I2C_Type) SetINT_ST_SLAVE_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_ST_SLAVE_TRAN_COMP_INT_ST() uint32 { + return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_ST_ARBITRATION_LOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_ST_ARBITRATION_LOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_ST_MASTER_TRAN_COMP_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_ST_MASTER_TRAN_COMP_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_ST_TRANS_COMPLETE_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_ST_TRANS_COMPLETE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_ST_TIME_OUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_ST_TIME_OUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_ST_ACK_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_ST_ACK_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_ST_RX_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_ST_RX_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_ST_TX_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_ST_TX_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_ST_DETECT_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_ST_DETECT_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8 +} + +// RTC_I2C.INT_ENA: interrupt enable register +func (o *RTC_I2C_Type) SetINT_ENA_SLAVE_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value) +} +func (o *RTC_I2C_Type) GetINT_ENA_SLAVE_TRAN_COMP_INT_ENA() uint32 { + return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1 +} +func (o *RTC_I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *RTC_I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1 +} +func (o *RTC_I2C_Type) SetINT_ENA_MASTER_TRAN_COMP_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *RTC_I2C_Type) GetINT_ENA_MASTER_TRAN_COMP_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2 +} +func (o *RTC_I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *RTC_I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3 +} +func (o *RTC_I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *RTC_I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4 +} +func (o *RTC_I2C_Type) SetINT_ENA_ACK_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *RTC_I2C_Type) GetINT_ENA_ACK_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5 +} +func (o *RTC_I2C_Type) SetINT_ENA_RX_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *RTC_I2C_Type) GetINT_ENA_RX_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6 +} +func (o *RTC_I2C_Type) SetINT_ENA_TX_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *RTC_I2C_Type) GetINT_ENA_TX_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7 +} +func (o *RTC_I2C_Type) SetINT_ENA_DETECT_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *RTC_I2C_Type) GetINT_ENA_DETECT_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8 +} + +// RTC_I2C.DATA: get i2c data status +func (o *RTC_I2C_Type) SetDATA_I2C_RDATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value) +} +func (o *RTC_I2C_Type) GetDATA_I2C_RDATA() uint32 { + return volatile.LoadUint32(&o.DATA.Reg) & 0xff +} +func (o *RTC_I2C_Type) SetDATA_SLAVE_TX_DATA(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff00)|value<<8) +} +func (o *RTC_I2C_Type) GetDATA_SLAVE_TX_DATA() uint32 { + return (volatile.LoadUint32(&o.DATA.Reg) & 0xff00) >> 8 +} +func (o *RTC_I2C_Type) SetDATA_I2C_DONE(value uint32) { + volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetDATA_I2C_DONE() uint32 { + return (volatile.LoadUint32(&o.DATA.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD0: i2c commond0 register +func (o *RTC_I2C_Type) SetCMD0_COMMAND0(value uint32) { + volatile.StoreUint32(&o.CMD0.Reg, volatile.LoadUint32(&o.CMD0.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD0_COMMAND0() uint32 { + return volatile.LoadUint32(&o.CMD0.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD0_COMMAND0_DONE(value uint32) { + volatile.StoreUint32(&o.CMD0.Reg, volatile.LoadUint32(&o.CMD0.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD0_COMMAND0_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD0.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD1: i2c commond1 register +func (o *RTC_I2C_Type) SetCMD1_COMMAND1(value uint32) { + volatile.StoreUint32(&o.CMD1.Reg, volatile.LoadUint32(&o.CMD1.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD1_COMMAND1() uint32 { + return volatile.LoadUint32(&o.CMD1.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD1_COMMAND1_DONE(value uint32) { + volatile.StoreUint32(&o.CMD1.Reg, volatile.LoadUint32(&o.CMD1.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD1_COMMAND1_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD1.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD2: i2c commond2 register +func (o *RTC_I2C_Type) SetCMD2_COMMAND2(value uint32) { + volatile.StoreUint32(&o.CMD2.Reg, volatile.LoadUint32(&o.CMD2.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD2_COMMAND2() uint32 { + return volatile.LoadUint32(&o.CMD2.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD2_COMMAND2_DONE(value uint32) { + volatile.StoreUint32(&o.CMD2.Reg, volatile.LoadUint32(&o.CMD2.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD2_COMMAND2_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD2.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD3: i2c commond3 register +func (o *RTC_I2C_Type) SetCMD3_COMMAND3(value uint32) { + volatile.StoreUint32(&o.CMD3.Reg, volatile.LoadUint32(&o.CMD3.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD3_COMMAND3() uint32 { + return volatile.LoadUint32(&o.CMD3.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD3_COMMAND3_DONE(value uint32) { + volatile.StoreUint32(&o.CMD3.Reg, volatile.LoadUint32(&o.CMD3.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD3_COMMAND3_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD3.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD4: i2c commond4 register +func (o *RTC_I2C_Type) SetCMD4_COMMAND4(value uint32) { + volatile.StoreUint32(&o.CMD4.Reg, volatile.LoadUint32(&o.CMD4.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD4_COMMAND4() uint32 { + return volatile.LoadUint32(&o.CMD4.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD4_COMMAND4_DONE(value uint32) { + volatile.StoreUint32(&o.CMD4.Reg, volatile.LoadUint32(&o.CMD4.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD4_COMMAND4_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD4.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD5: i2c commond5_register +func (o *RTC_I2C_Type) SetCMD5_COMMAND5(value uint32) { + volatile.StoreUint32(&o.CMD5.Reg, volatile.LoadUint32(&o.CMD5.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD5_COMMAND5() uint32 { + return volatile.LoadUint32(&o.CMD5.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD5_COMMAND5_DONE(value uint32) { + volatile.StoreUint32(&o.CMD5.Reg, volatile.LoadUint32(&o.CMD5.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD5_COMMAND5_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD5.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD6: i2c commond6 register +func (o *RTC_I2C_Type) SetCMD6_COMMAND6(value uint32) { + volatile.StoreUint32(&o.CMD6.Reg, volatile.LoadUint32(&o.CMD6.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD6_COMMAND6() uint32 { + return volatile.LoadUint32(&o.CMD6.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD6_COMMAND6_DONE(value uint32) { + volatile.StoreUint32(&o.CMD6.Reg, volatile.LoadUint32(&o.CMD6.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD6_COMMAND6_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD6.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD7: i2c commond7 register +func (o *RTC_I2C_Type) SetCMD7_COMMAND7(value uint32) { + volatile.StoreUint32(&o.CMD7.Reg, volatile.LoadUint32(&o.CMD7.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD7_COMMAND7() uint32 { + return volatile.LoadUint32(&o.CMD7.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD7_COMMAND7_DONE(value uint32) { + volatile.StoreUint32(&o.CMD7.Reg, volatile.LoadUint32(&o.CMD7.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD7_COMMAND7_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD7.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD8: i2c commond8 register +func (o *RTC_I2C_Type) SetCMD8_COMMAND8(value uint32) { + volatile.StoreUint32(&o.CMD8.Reg, volatile.LoadUint32(&o.CMD8.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD8_COMMAND8() uint32 { + return volatile.LoadUint32(&o.CMD8.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD8_COMMAND8_DONE(value uint32) { + volatile.StoreUint32(&o.CMD8.Reg, volatile.LoadUint32(&o.CMD8.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD8_COMMAND8_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD8.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD9: i2c commond9 register +func (o *RTC_I2C_Type) SetCMD9_COMMAND9(value uint32) { + volatile.StoreUint32(&o.CMD9.Reg, volatile.LoadUint32(&o.CMD9.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD9_COMMAND9() uint32 { + return volatile.LoadUint32(&o.CMD9.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD9_COMMAND9_DONE(value uint32) { + volatile.StoreUint32(&o.CMD9.Reg, volatile.LoadUint32(&o.CMD9.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD9_COMMAND9_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD9.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD10: i2c commond10 register +func (o *RTC_I2C_Type) SetCMD10_COMMAND10(value uint32) { + volatile.StoreUint32(&o.CMD10.Reg, volatile.LoadUint32(&o.CMD10.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD10_COMMAND10() uint32 { + return volatile.LoadUint32(&o.CMD10.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD10_COMMAND10_DONE(value uint32) { + volatile.StoreUint32(&o.CMD10.Reg, volatile.LoadUint32(&o.CMD10.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD10_COMMAND10_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD10.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD11: i2c commond11 register +func (o *RTC_I2C_Type) SetCMD11_COMMAND11(value uint32) { + volatile.StoreUint32(&o.CMD11.Reg, volatile.LoadUint32(&o.CMD11.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD11_COMMAND11() uint32 { + return volatile.LoadUint32(&o.CMD11.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD11_COMMAND11_DONE(value uint32) { + volatile.StoreUint32(&o.CMD11.Reg, volatile.LoadUint32(&o.CMD11.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD11_COMMAND11_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD11.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD12: i2c commond12 register +func (o *RTC_I2C_Type) SetCMD12_COMMAND12(value uint32) { + volatile.StoreUint32(&o.CMD12.Reg, volatile.LoadUint32(&o.CMD12.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD12_COMMAND12() uint32 { + return volatile.LoadUint32(&o.CMD12.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD12_COMMAND12_DONE(value uint32) { + volatile.StoreUint32(&o.CMD12.Reg, volatile.LoadUint32(&o.CMD12.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD12_COMMAND12_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD12.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD13: i2c commond13 register +func (o *RTC_I2C_Type) SetCMD13_COMMAND13(value uint32) { + volatile.StoreUint32(&o.CMD13.Reg, volatile.LoadUint32(&o.CMD13.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD13_COMMAND13() uint32 { + return volatile.LoadUint32(&o.CMD13.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD13_COMMAND13_DONE(value uint32) { + volatile.StoreUint32(&o.CMD13.Reg, volatile.LoadUint32(&o.CMD13.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD13_COMMAND13_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD13.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD14: i2c commond14 register +func (o *RTC_I2C_Type) SetCMD14_COMMAND14(value uint32) { + volatile.StoreUint32(&o.CMD14.Reg, volatile.LoadUint32(&o.CMD14.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD14_COMMAND14() uint32 { + return volatile.LoadUint32(&o.CMD14.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD14_COMMAND14_DONE(value uint32) { + volatile.StoreUint32(&o.CMD14.Reg, volatile.LoadUint32(&o.CMD14.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD14_COMMAND14_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD14.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.CMD15: i2c commond15 register +func (o *RTC_I2C_Type) SetCMD15_COMMAND15(value uint32) { + volatile.StoreUint32(&o.CMD15.Reg, volatile.LoadUint32(&o.CMD15.Reg)&^(0x3fff)|value) +} +func (o *RTC_I2C_Type) GetCMD15_COMMAND15() uint32 { + return volatile.LoadUint32(&o.CMD15.Reg) & 0x3fff +} +func (o *RTC_I2C_Type) SetCMD15_COMMAND15_DONE(value uint32) { + volatile.StoreUint32(&o.CMD15.Reg, volatile.LoadUint32(&o.CMD15.Reg)&^(0x80000000)|value<<31) +} +func (o *RTC_I2C_Type) GetCMD15_COMMAND15_DONE() uint32 { + return (volatile.LoadUint32(&o.CMD15.Reg) & 0x80000000) >> 31 +} + +// RTC_I2C.DATE: version register +func (o *RTC_I2C_Type) SetDATE_I2C_DATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_I2C_Type) GetDATE_I2C_DATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// Low-power Input/Output +type RTC_IO_Type struct { + RTC_GPIO_OUT volatile.Register32 // 0x0 + RTC_GPIO_OUT_W1TS volatile.Register32 // 0x4 + RTC_GPIO_OUT_W1TC volatile.Register32 // 0x8 + RTC_GPIO_ENABLE volatile.Register32 // 0xC + RTC_GPIO_ENABLE_W1TS volatile.Register32 // 0x10 + RTC_GPIO_ENABLE_W1TC volatile.Register32 // 0x14 + RTC_GPIO_STATUS volatile.Register32 // 0x18 + RTC_GPIO_STATUS_W1TS volatile.Register32 // 0x1C + RTC_GPIO_STATUS_W1TC volatile.Register32 // 0x20 + RTC_GPIO_IN volatile.Register32 // 0x24 + RTC_GPIO_PIN0 volatile.Register32 // 0x28 + RTC_GPIO_PIN1 volatile.Register32 // 0x2C + RTC_GPIO_PIN2 volatile.Register32 // 0x30 + RTC_GPIO_PIN3 volatile.Register32 // 0x34 + RTC_GPIO_PIN4 volatile.Register32 // 0x38 + RTC_GPIO_PIN5 volatile.Register32 // 0x3C + RTC_GPIO_PIN6 volatile.Register32 // 0x40 + RTC_GPIO_PIN7 volatile.Register32 // 0x44 + RTC_GPIO_PIN8 volatile.Register32 // 0x48 + RTC_GPIO_PIN9 volatile.Register32 // 0x4C + RTC_GPIO_PIN10 volatile.Register32 // 0x50 + RTC_GPIO_PIN11 volatile.Register32 // 0x54 + RTC_GPIO_PIN12 volatile.Register32 // 0x58 + RTC_GPIO_PIN13 volatile.Register32 // 0x5C + RTC_GPIO_PIN14 volatile.Register32 // 0x60 + RTC_GPIO_PIN15 volatile.Register32 // 0x64 + RTC_GPIO_PIN16 volatile.Register32 // 0x68 + RTC_GPIO_PIN17 volatile.Register32 // 0x6C + RTC_GPIO_PIN18 volatile.Register32 // 0x70 + RTC_GPIO_PIN19 volatile.Register32 // 0x74 + RTC_GPIO_PIN20 volatile.Register32 // 0x78 + RTC_GPIO_PIN21 volatile.Register32 // 0x7C + RTC_DEBUG_SEL volatile.Register32 // 0x80 + TOUCH_PAD0 volatile.Register32 // 0x84 + TOUCH_PAD1 volatile.Register32 // 0x88 + TOUCH_PAD2 volatile.Register32 // 0x8C + TOUCH_PAD3 volatile.Register32 // 0x90 + TOUCH_PAD4 volatile.Register32 // 0x94 + TOUCH_PAD5 volatile.Register32 // 0x98 + TOUCH_PAD6 volatile.Register32 // 0x9C + TOUCH_PAD7 volatile.Register32 // 0xA0 + TOUCH_PAD8 volatile.Register32 // 0xA4 + TOUCH_PAD9 volatile.Register32 // 0xA8 + TOUCH_PAD10 volatile.Register32 // 0xAC + TOUCH_PAD11 volatile.Register32 // 0xB0 + TOUCH_PAD12 volatile.Register32 // 0xB4 + TOUCH_PAD13 volatile.Register32 // 0xB8 + TOUCH_PAD14 volatile.Register32 // 0xBC + XTAL_32P_PAD volatile.Register32 // 0xC0 + XTAL_32N_PAD volatile.Register32 // 0xC4 + PAD_DAC1 volatile.Register32 // 0xC8 + PAD_DAC2 volatile.Register32 // 0xCC + RTC_PAD19 volatile.Register32 // 0xD0 + RTC_PAD20 volatile.Register32 // 0xD4 + RTC_PAD21 volatile.Register32 // 0xD8 + EXT_WAKEUP0 volatile.Register32 // 0xDC + XTL_EXT_CTR volatile.Register32 // 0xE0 + SAR_I2C_IO volatile.Register32 // 0xE4 + TOUCH_CTRL volatile.Register32 // 0xE8 + _ [272]byte + DATE volatile.Register32 // 0x1FC +} + +// RTC_IO.RTC_GPIO_OUT: RTC GPIO 0 ~ 21 output data register +func (o *RTC_IO_Type) SetRTC_GPIO_OUT_DATA(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_OUT_DATA() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_OUT_W1TS: one set RTC GPIO output data +func (o *RTC_IO_Type) SetRTC_GPIO_OUT_W1TS_RTC_GPIO_OUT_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_OUT_W1TS_RTC_GPIO_OUT_DATA_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_OUT_W1TC: one clear RTC GPIO output data +func (o *RTC_IO_Type) SetRTC_GPIO_OUT_W1TC_RTC_GPIO_OUT_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_OUT_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_OUT_W1TC_RTC_GPIO_OUT_DATA_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_OUT_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_ENABLE: Configure RTC GPIO output enable +func (o *RTC_IO_Type) SetRTC_GPIO_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_ENABLE_W1TS: one set RTC GPIO output enable +func (o *RTC_IO_Type) SetRTC_GPIO_ENABLE_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_ENABLE_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_ENABLE_W1TC: one clear RTC GPIO output enable +func (o *RTC_IO_Type) SetRTC_GPIO_ENABLE_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_ENABLE_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_ENABLE_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_ENABLE_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_STATUS: RTC GPIO 0 ~ 21 interrupt status +func (o *RTC_IO_Type) SetRTC_GPIO_STATUS_INT(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_STATUS_INT() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_STATUS_W1TS: One set RTC GPIO 0 ~ 21 interrupt status +func (o *RTC_IO_Type) SetRTC_GPIO_STATUS_W1TS_RTC_GPIO_STATUS_INT_W1TS(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS_W1TS.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TS.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_STATUS_W1TS_RTC_GPIO_STATUS_INT_W1TS() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TS.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_STATUS_W1TC: One clear RTC GPIO 0 ~ 21 interrupt status +func (o *RTC_IO_Type) SetRTC_GPIO_STATUS_W1TC_RTC_GPIO_STATUS_INT_W1TC(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_STATUS_W1TC.Reg, volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TC.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_STATUS_W1TC_RTC_GPIO_STATUS_INT_W1TC() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_STATUS_W1TC.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_IN: RTC GPIO input data +func (o *RTC_IO_Type) SetRTC_GPIO_IN_NEXT(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_IN.Reg, volatile.LoadUint32(&o.RTC_GPIO_IN.Reg)&^(0xfffffc00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_IN_NEXT() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_IN.Reg) & 0xfffffc00) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN0: configure RTC GPIO0 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN0_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN0.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN0_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN0.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN0.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN0.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN1: configure RTC GPIO1 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN1_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN1.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN1_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN1.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN1.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN1.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN2: configure RTC GPIO2 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN2_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN2.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN2_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN2.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN2.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN2.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN3: configure RTC GPIO3 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN3_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN3.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN3_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN3.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN3.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN3.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN4: configure RTC GPIO4 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN4_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN4.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN4_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN4.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN4.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN4.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN5: configure RTC GPIO5 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN5_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN5.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN5_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN5.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN5.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN5.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN6: configure RTC GPIO6 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN6_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN6.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN6_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN6.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN6.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN6.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN7: configure RTC GPIO7 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN7_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN7.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN7_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN7.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN7.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN7.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN8: configure RTC GPIO8 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN8_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN8.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN8_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN8.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN8.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN8.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN9: configure RTC GPIO9 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN9_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN9.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN9_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN9.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN9.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN9.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN10: configure RTC GPIO10 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN10_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN10.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN10_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN10.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN10.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN10.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN11: configure RTC GPIO11 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN11_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN11.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN11_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN11.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN11.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN11.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN12: configure RTC GPIO12 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN12_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN12.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN12_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN12.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN12.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN12.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN13: configure RTC GPIO13 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN13_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN13.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN13_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN13.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN13.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN13.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN14: configure RTC GPIO14 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN14_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN14.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN14_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN14.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN14.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN14.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN15: configure RTC GPIO15 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN15_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN15.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN15_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN15.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN15.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN15.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN16: configure RTC GPIO16 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN16_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN16.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN16_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN16_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN16.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN16_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN16_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN16.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN16_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN16.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN17: configure RTC GPIO17 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN17_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN17.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN17_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN17_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN17.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN17_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN17_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN17.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN17_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN17.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN18: configure RTC GPIO18 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN18_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN18.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN18_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN18_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN18.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN18_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN18_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN18.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN18_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN18.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN19: configure RTC GPIO19 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN19_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN19.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN19_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN19_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN19.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN19_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN19_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN19.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN19_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN19.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN20: configure RTC GPIO20 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN20_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN20.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN20_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN20_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN20.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN20_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN20_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN20.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN20_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN20.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_GPIO_PIN21: configure RTC GPIO21 +func (o *RTC_IO_Type) SetRTC_GPIO_PIN21_PAD_DRIVER(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN21.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg)&^(0x4)|value<<2) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN21_PAD_DRIVER() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg) & 0x4) >> 2 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN21_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN21.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg)&^(0x380)|value<<7) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN21_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg) & 0x380) >> 7 +} +func (o *RTC_IO_Type) SetRTC_GPIO_PIN21_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.RTC_GPIO_PIN21.Reg, volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg)&^(0x400)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_GPIO_PIN21_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.RTC_GPIO_PIN21.Reg) & 0x400) >> 10 +} + +// RTC_IO.RTC_DEBUG_SEL: configure rtc debug +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL0(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f)|value) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL0() uint32 { + return volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL1(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x3e0)|value<<5) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL1() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x3e0) >> 5 +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL2(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x7c00)|value<<10) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL2() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x7c00) >> 10 +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL3(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0xf8000)|value<<15) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL3() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0xf8000) >> 15 +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_SEL4(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x1f00000)|value<<20) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_SEL4() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x1f00000) >> 20 +} +func (o *RTC_IO_Type) SetRTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING(value uint32) { + volatile.StoreUint32(&o.RTC_DEBUG_SEL.Reg, volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg)&^(0x2000000)|value<<25) +} +func (o *RTC_IO_Type) GetRTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING() uint32 { + return (volatile.LoadUint32(&o.RTC_DEBUG_SEL.Reg) & 0x2000000) >> 25 +} + +// RTC_IO.TOUCH_PAD0: configure RTC PAD0 +func (o *RTC_IO_Type) SetTOUCH_PAD0_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD0_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD0.Reg, volatile.LoadUint32(&o.TOUCH_PAD0.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD0_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD0.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD1: configure RTC PAD1 +func (o *RTC_IO_Type) SetTOUCH_PAD1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD1_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD1.Reg, volatile.LoadUint32(&o.TOUCH_PAD1.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD1_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD1.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD2: configure RTC PAD2 +func (o *RTC_IO_Type) SetTOUCH_PAD2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD2_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD2.Reg, volatile.LoadUint32(&o.TOUCH_PAD2.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD2_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD2.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD3: configure RTC PAD3 +func (o *RTC_IO_Type) SetTOUCH_PAD3_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD3_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD3.Reg, volatile.LoadUint32(&o.TOUCH_PAD3.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD3_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD3.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD4: configure RTC PAD4 +func (o *RTC_IO_Type) SetTOUCH_PAD4_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD4_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD4.Reg, volatile.LoadUint32(&o.TOUCH_PAD4.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD4_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD4.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD5: configure RTC PAD5 +func (o *RTC_IO_Type) SetTOUCH_PAD5_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD5_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD5.Reg, volatile.LoadUint32(&o.TOUCH_PAD5.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD5_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD5.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD6: configure RTC PAD6 +func (o *RTC_IO_Type) SetTOUCH_PAD6_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD6_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD6.Reg, volatile.LoadUint32(&o.TOUCH_PAD6.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD6_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD6.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD7: configure RTC PAD7 +func (o *RTC_IO_Type) SetTOUCH_PAD7_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD7_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD7.Reg, volatile.LoadUint32(&o.TOUCH_PAD7.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD7_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD7.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD8: configure RTC PAD8 +func (o *RTC_IO_Type) SetTOUCH_PAD8_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD8_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD8.Reg, volatile.LoadUint32(&o.TOUCH_PAD8.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD8_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD8.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD9: configure RTC PAD9 +func (o *RTC_IO_Type) SetTOUCH_PAD9_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD9_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD9.Reg, volatile.LoadUint32(&o.TOUCH_PAD9.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD9_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD9.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD10: configure RTC PAD10 +func (o *RTC_IO_Type) SetTOUCH_PAD10_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD10_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD10.Reg, volatile.LoadUint32(&o.TOUCH_PAD10.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD10_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD10.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD11: configure RTC PAD11 +func (o *RTC_IO_Type) SetTOUCH_PAD11_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD11_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD11.Reg, volatile.LoadUint32(&o.TOUCH_PAD11.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD11_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD11.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD12: configure RTC PAD12 +func (o *RTC_IO_Type) SetTOUCH_PAD12_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD12_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD12.Reg, volatile.LoadUint32(&o.TOUCH_PAD12.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD12_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD12.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD13: configure RTC PAD13 +func (o *RTC_IO_Type) SetTOUCH_PAD13_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD13_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD13.Reg, volatile.LoadUint32(&o.TOUCH_PAD13.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD13_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD13.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.TOUCH_PAD14: configure RTC PAD14 +func (o *RTC_IO_Type) SetTOUCH_PAD14_FUN_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_SLP_OE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_SLP_IE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_XPD(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x100000)|value<<20) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_XPD() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x100000) >> 20 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_TIE_OPT(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x200000)|value<<21) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_TIE_OPT() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x200000) >> 21 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_START(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x400000)|value<<22) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_START() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x400000) >> 22 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_RUE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_RUE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_RDE(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_RDE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetTOUCH_PAD14_DRV(value uint32) { + volatile.StoreUint32(&o.TOUCH_PAD14.Reg, volatile.LoadUint32(&o.TOUCH_PAD14.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetTOUCH_PAD14_DRV() uint32 { + return (volatile.LoadUint32(&o.TOUCH_PAD14.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.XTAL_32P_PAD: configure RTC PAD15 +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetXTAL_32P_PAD_X32P_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32P_PAD.Reg, volatile.LoadUint32(&o.XTAL_32P_PAD.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetXTAL_32P_PAD_X32P_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32P_PAD.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.XTAL_32N_PAD: configure RTC PAD16 +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_FUN_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_SLP_OE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_SLP_IE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_RUE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_RUE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_RDE(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_RDE() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetXTAL_32N_PAD_X32N_DRV(value uint32) { + volatile.StoreUint32(&o.XTAL_32N_PAD.Reg, volatile.LoadUint32(&o.XTAL_32N_PAD.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetXTAL_32N_PAD_X32N_DRV() uint32 { + return (volatile.LoadUint32(&o.XTAL_32N_PAD.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.PAD_DAC1: configure RTC PAD17 +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x7f8)|value<<3) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x7f8) >> 3 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x800)|value<<11) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x800) >> 11 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x1000) >> 12 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetPAD_DAC1_PDAC1_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC1.Reg, volatile.LoadUint32(&o.PAD_DAC1.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetPAD_DAC1_PDAC1_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC1.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.PAD_DAC2: configure RTC PAD18 +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x7f8)|value<<3) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x7f8) >> 3 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_XPD_DAC(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x800)|value<<11) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_XPD_DAC() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x800) >> 11 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_DAC_XPD_FORCE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x1000)|value<<12) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_DAC_XPD_FORCE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x1000) >> 12 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_FUN_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_SLP_OE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_SLP_IE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_RUE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_RUE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_RDE(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_RDE() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetPAD_DAC2_PDAC2_DRV(value uint32) { + volatile.StoreUint32(&o.PAD_DAC2.Reg, volatile.LoadUint32(&o.PAD_DAC2.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetPAD_DAC2_PDAC2_DRV() uint32 { + return (volatile.LoadUint32(&o.PAD_DAC2.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.RTC_PAD19: configure RTC PAD19 +func (o *RTC_IO_Type) SetRTC_PAD19_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetRTC_PAD19_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetRTC_PAD19_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetRTC_PAD19_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetRTC_PAD19_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetRTC_PAD19_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetRTC_PAD19_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetRTC_PAD19_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetRTC_PAD19_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetRTC_PAD19_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetRTC_PAD19_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetRTC_PAD19_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetRTC_PAD19_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetRTC_PAD19_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetRTC_PAD19_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetRTC_PAD19_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetRTC_PAD19_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD19.Reg, volatile.LoadUint32(&o.RTC_PAD19.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetRTC_PAD19_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD19.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.RTC_PAD20: configure RTC PAD20 +func (o *RTC_IO_Type) SetRTC_PAD20_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetRTC_PAD20_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetRTC_PAD20_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetRTC_PAD20_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetRTC_PAD20_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetRTC_PAD20_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetRTC_PAD20_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetRTC_PAD20_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetRTC_PAD20_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetRTC_PAD20_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetRTC_PAD20_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetRTC_PAD20_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetRTC_PAD20_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetRTC_PAD20_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetRTC_PAD20_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetRTC_PAD20_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetRTC_PAD20_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD20.Reg, volatile.LoadUint32(&o.RTC_PAD20.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetRTC_PAD20_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD20.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.RTC_PAD21: configure RTC PAD21 +func (o *RTC_IO_Type) SetRTC_PAD21_FUN_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x2000)|value<<13) +} +func (o *RTC_IO_Type) GetRTC_PAD21_FUN_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x2000) >> 13 +} +func (o *RTC_IO_Type) SetRTC_PAD21_SLP_OE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x4000)|value<<14) +} +func (o *RTC_IO_Type) GetRTC_PAD21_SLP_OE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x4000) >> 14 +} +func (o *RTC_IO_Type) SetRTC_PAD21_SLP_IE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x8000)|value<<15) +} +func (o *RTC_IO_Type) GetRTC_PAD21_SLP_IE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x8000) >> 15 +} +func (o *RTC_IO_Type) SetRTC_PAD21_SLP_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x10000)|value<<16) +} +func (o *RTC_IO_Type) GetRTC_PAD21_SLP_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x10000) >> 16 +} +func (o *RTC_IO_Type) SetRTC_PAD21_FUN_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x60000)|value<<17) +} +func (o *RTC_IO_Type) GetRTC_PAD21_FUN_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x60000) >> 17 +} +func (o *RTC_IO_Type) SetRTC_PAD21_MUX_SEL(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x80000)|value<<19) +} +func (o *RTC_IO_Type) GetRTC_PAD21_MUX_SEL() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x80000) >> 19 +} +func (o *RTC_IO_Type) SetRTC_PAD21_RUE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x8000000)|value<<27) +} +func (o *RTC_IO_Type) GetRTC_PAD21_RUE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x8000000) >> 27 +} +func (o *RTC_IO_Type) SetRTC_PAD21_RDE(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x10000000)|value<<28) +} +func (o *RTC_IO_Type) GetRTC_PAD21_RDE() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x10000000) >> 28 +} +func (o *RTC_IO_Type) SetRTC_PAD21_DRV(value uint32) { + volatile.StoreUint32(&o.RTC_PAD21.Reg, volatile.LoadUint32(&o.RTC_PAD21.Reg)&^(0x60000000)|value<<29) +} +func (o *RTC_IO_Type) GetRTC_PAD21_DRV() uint32 { + return (volatile.LoadUint32(&o.RTC_PAD21.Reg) & 0x60000000) >> 29 +} + +// RTC_IO.EXT_WAKEUP0: configure EXT0 wakeup +func (o *RTC_IO_Type) SetEXT_WAKEUP0_SEL(value uint32) { + volatile.StoreUint32(&o.EXT_WAKEUP0.Reg, volatile.LoadUint32(&o.EXT_WAKEUP0.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_IO_Type) GetEXT_WAKEUP0_SEL() uint32 { + return (volatile.LoadUint32(&o.EXT_WAKEUP0.Reg) & 0xf8000000) >> 27 +} + +// RTC_IO.XTL_EXT_CTR: configure gpio pd XTAL +func (o *RTC_IO_Type) SetXTL_EXT_CTR_SEL(value uint32) { + volatile.StoreUint32(&o.XTL_EXT_CTR.Reg, volatile.LoadUint32(&o.XTL_EXT_CTR.Reg)&^(0xf8000000)|value<<27) +} +func (o *RTC_IO_Type) GetXTL_EXT_CTR_SEL() uint32 { + return (volatile.LoadUint32(&o.XTL_EXT_CTR.Reg) & 0xf8000000) >> 27 +} + +// RTC_IO.SAR_I2C_IO: configure rtc i2c mux +func (o *RTC_IO_Type) SetSAR_I2C_IO_SAR_DEBUG_BIT_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xf800000)|value<<23) +} +func (o *RTC_IO_Type) GetSAR_I2C_IO_SAR_DEBUG_BIT_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xf800000) >> 23 +} +func (o *RTC_IO_Type) SetSAR_I2C_IO_SAR_I2C_SCL_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0x30000000)|value<<28) +} +func (o *RTC_IO_Type) GetSAR_I2C_IO_SAR_I2C_SCL_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0x30000000) >> 28 +} +func (o *RTC_IO_Type) SetSAR_I2C_IO_SAR_I2C_SDA_SEL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_IO.Reg, volatile.LoadUint32(&o.SAR_I2C_IO.Reg)&^(0xc0000000)|value<<30) +} +func (o *RTC_IO_Type) GetSAR_I2C_IO_SAR_I2C_SDA_SEL() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_IO.Reg) & 0xc0000000) >> 30 +} + +// RTC_IO.TOUCH_CTRL: configure touch pad bufmode +func (o *RTC_IO_Type) SetTOUCH_CTRL_IO_TOUCH_BUFSEL(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_CTRL.Reg)&^(0xf)|value) +} +func (o *RTC_IO_Type) GetTOUCH_CTRL_IO_TOUCH_BUFSEL() uint32 { + return volatile.LoadUint32(&o.TOUCH_CTRL.Reg) & 0xf +} +func (o *RTC_IO_Type) SetTOUCH_CTRL_IO_TOUCH_BUFMODE(value uint32) { + volatile.StoreUint32(&o.TOUCH_CTRL.Reg, volatile.LoadUint32(&o.TOUCH_CTRL.Reg)&^(0x10)|value<<4) +} +func (o *RTC_IO_Type) GetTOUCH_CTRL_IO_TOUCH_BUFMODE() uint32 { + return (volatile.LoadUint32(&o.TOUCH_CTRL.Reg) & 0x10) >> 4 +} + +// RTC_IO.DATE: version +func (o *RTC_IO_Type) SetDATE(value uint32) { + volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value) +} +func (o *RTC_IO_Type) GetDATE() uint32 { + return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff +} + +// SENS Peripheral +type SENS_Type struct { + _ [64]byte + SAR_SLAVE_ADDR1 volatile.Register32 // 0x40 + SAR_SLAVE_ADDR2 volatile.Register32 // 0x44 + SAR_SLAVE_ADDR3 volatile.Register32 // 0x48 + SAR_SLAVE_ADDR4 volatile.Register32 // 0x4C + _ [8]byte + SAR_I2C_CTRL volatile.Register32 // 0x58 + _ [140]byte + SAR_COCPU_INT_RAW volatile.Register32 // 0xE8 + SAR_COCPU_INT_ENA volatile.Register32 // 0xEC + SAR_COCPU_INT_ST volatile.Register32 // 0xF0 + SAR_COCPU_INT_CLR volatile.Register32 // 0xF4 +} + +// SENS.SAR_SLAVE_ADDR1: configure i2c slave address +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR1(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR1() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR0(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR0() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3ff800) >> 11 +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR1_SAR_SARADC_MEAS_STATUS(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR1.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg)&^(0x3fc00000)|value<<22) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR1_SAR_SARADC_MEAS_STATUS() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR1.Reg) & 0x3fc00000) >> 22 +} + +// SENS.SAR_SLAVE_ADDR2: configure i2c slave address +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR3(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR3() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR2(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR2.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR2() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR2.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_SLAVE_ADDR3: configure i2c slave address +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR5(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR5() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR4(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR3.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR4() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR3.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_SLAVE_ADDR4: configure i2c slave address +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR7(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x7ff)|value) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR7() uint32 { + return volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x7ff +} +func (o *SENS_Type) SetSAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR6(value uint32) { + volatile.StoreUint32(&o.SAR_SLAVE_ADDR4.Reg, volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg)&^(0x3ff800)|value<<11) +} +func (o *SENS_Type) GetSAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR6() uint32 { + return (volatile.LoadUint32(&o.SAR_SLAVE_ADDR4.Reg) & 0x3ff800) >> 11 +} + +// SENS.SAR_I2C_CTRL: configure rtc i2c controller by sw +func (o *SENS_Type) SetSAR_I2C_CTRL(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0xfffffff)|value) +} +func (o *SENS_Type) GetSAR_I2C_CTRL() uint32 { + return volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0xfffffff +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x10000000)|value<<28) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x10000000) >> 28 +} +func (o *SENS_Type) SetSAR_I2C_CTRL_SAR_I2C_START_FORCE(value uint32) { + volatile.StoreUint32(&o.SAR_I2C_CTRL.Reg, volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg)&^(0x20000000)|value<<29) +} +func (o *SENS_Type) GetSAR_I2C_CTRL_SAR_I2C_START_FORCE() uint32 { + return (volatile.LoadUint32(&o.SAR_I2C_CTRL.Reg) & 0x20000000) >> 29 +} + +// SENS.SAR_COCPU_INT_RAW: the interrupt raw of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_RAW.Reg) & 0x800) >> 11 +} + +// SENS.SAR_COCPU_INT_ENA: the interrupt enable of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ENA.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ENA.Reg) & 0x800) >> 11 +} + +// SENS.SAR_COCPU_INT_ST: the interrupt state of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_ST.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_ST.Reg) & 0x800) >> 11 +} + +// SENS.SAR_COCPU_INT_CLR: the interrupt clear of ulp +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SENS_Type) SetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SAR_COCPU_INT_CLR.Reg, volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SENS_Type) GetSAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SAR_COCPU_INT_CLR.Reg) & 0x800) >> 11 +} + +// Constants for RTC_CNTL: Real-Time Clock Control +const ( + // RTC_ULP_CP_TIMER: configure ulp + // Position of ULP_CP_PC_INIT field. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_PC_INIT_Pos = 0x0 + // Bit mask of ULP_CP_PC_INIT field. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_PC_INIT_Msk = 0x7ff + // Position of ULP_CP_GPIO_WAKEUP_ENA field. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA_Pos = 0x1d + // Bit mask of ULP_CP_GPIO_WAKEUP_ENA field. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA_Msk = 0x20000000 + // Bit ULP_CP_GPIO_WAKEUP_ENA. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_ENA = 0x20000000 + // Position of ULP_CP_GPIO_WAKEUP_CLR field. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR_Pos = 0x1e + // Bit mask of ULP_CP_GPIO_WAKEUP_CLR field. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR_Msk = 0x40000000 + // Bit ULP_CP_GPIO_WAKEUP_CLR. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_GPIO_WAKEUP_CLR = 0x40000000 + // Position of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN_Pos = 0x1f + // Bit mask of ULP_CP_SLP_TIMER_EN field. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN_Msk = 0x80000000 + // Bit ULP_CP_SLP_TIMER_EN. + RTC_CNTL_RTC_ULP_CP_TIMER_ULP_CP_SLP_TIMER_EN = 0x80000000 + + // RTC_ULP_CP_CTRL: configure ulp + // Position of ULP_CP_MEM_ADDR_INIT field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT_Pos = 0x0 + // Bit mask of ULP_CP_MEM_ADDR_INIT field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_MEM_ADDR_INIT_Msk = 0x7ff + // Position of ULP_CP_MEM_ADDR_SIZE field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE_Pos = 0xb + // Bit mask of ULP_CP_MEM_ADDR_SIZE field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_MEM_ADDR_SIZE_Msk = 0x3ff800 + // Position of ULP_CP_MEM_OFFST_CLR field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR_Pos = 0x16 + // Bit mask of ULP_CP_MEM_OFFST_CLR field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR_Msk = 0x400000 + // Bit ULP_CP_MEM_OFFST_CLR. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_MEM_OFFST_CLR = 0x400000 + // Position of ULP_CP_CLK_FO field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_CLK_FO_Pos = 0x1c + // Bit mask of ULP_CP_CLK_FO field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_CLK_FO_Msk = 0x10000000 + // Bit ULP_CP_CLK_FO. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_CLK_FO = 0x10000000 + // Position of ULP_CP_RESET field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_RESET_Pos = 0x1d + // Bit mask of ULP_CP_RESET field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_RESET_Msk = 0x20000000 + // Bit ULP_CP_RESET. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_RESET = 0x20000000 + // Position of ULP_CP_FORCE_START_TOP field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP_Pos = 0x1e + // Bit mask of ULP_CP_FORCE_START_TOP field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP_Msk = 0x40000000 + // Bit ULP_CP_FORCE_START_TOP. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_FORCE_START_TOP = 0x40000000 + // Position of ULP_CP_START_TOP field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_START_TOP_Pos = 0x1f + // Bit mask of ULP_CP_START_TOP field. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_START_TOP_Msk = 0x80000000 + // Bit ULP_CP_START_TOP. + RTC_CNTL_RTC_ULP_CP_CTRL_ULP_CP_START_TOP = 0x80000000 + + // RTC_COCPU_CTRL: configure ulp-riscv + // Position of COCPU_CLK_FO field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_CLK_FO_Pos = 0x0 + // Bit mask of COCPU_CLK_FO field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_CLK_FO_Msk = 0x1 + // Bit COCPU_CLK_FO. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_CLK_FO = 0x1 + // Position of COCPU_START_2_RESET_DIS field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_START_2_RESET_DIS_Pos = 0x1 + // Bit mask of COCPU_START_2_RESET_DIS field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_START_2_RESET_DIS_Msk = 0x7e + // Position of COCPU_START_2_INTR_EN field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_START_2_INTR_EN_Pos = 0x7 + // Bit mask of COCPU_START_2_INTR_EN field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_START_2_INTR_EN_Msk = 0x1f80 + // Position of COCPU_SHUT field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SHUT_Pos = 0xd + // Bit mask of COCPU_SHUT field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SHUT_Msk = 0x2000 + // Bit COCPU_SHUT. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SHUT = 0x2000 + // Position of COCPU_SHUT_2_CLK_DIS field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS_Pos = 0xe + // Bit mask of COCPU_SHUT_2_CLK_DIS field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SHUT_2_CLK_DIS_Msk = 0x3fc000 + // Position of COCPU_SHUT_RESET_EN field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SHUT_RESET_EN_Pos = 0x16 + // Bit mask of COCPU_SHUT_RESET_EN field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SHUT_RESET_EN_Msk = 0x400000 + // Bit COCPU_SHUT_RESET_EN. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SHUT_RESET_EN = 0x400000 + // Position of COCPU_SEL field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SEL_Pos = 0x17 + // Bit mask of COCPU_SEL field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SEL_Msk = 0x800000 + // Bit COCPU_SEL. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SEL = 0x800000 + // Position of COCPU_DONE_FORCE field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_DONE_FORCE_Pos = 0x18 + // Bit mask of COCPU_DONE_FORCE field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_DONE_FORCE_Msk = 0x1000000 + // Bit COCPU_DONE_FORCE. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_DONE_FORCE = 0x1000000 + // Position of COCPU_DONE field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_DONE_Pos = 0x19 + // Bit mask of COCPU_DONE field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_DONE_Msk = 0x2000000 + // Bit COCPU_DONE. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_DONE = 0x2000000 + // Position of COCPU_SW_INT_TRIGGER field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SW_INT_TRIGGER_Pos = 0x1a + // Bit mask of COCPU_SW_INT_TRIGGER field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SW_INT_TRIGGER_Msk = 0x4000000 + // Bit COCPU_SW_INT_TRIGGER. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_SW_INT_TRIGGER = 0x4000000 + // Position of COCPU_CLKGATE_EN field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_CLKGATE_EN_Pos = 0x1b + // Bit mask of COCPU_CLKGATE_EN field. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_CLKGATE_EN_Msk = 0x8000000 + // Bit COCPU_CLKGATE_EN. + RTC_CNTL_RTC_COCPU_CTRL_COCPU_CLKGATE_EN = 0x8000000 + + // RTC_ULP_CP_TIMER_1: configure ulp sleep time + // Position of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_RTC_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Pos = 0x8 + // Bit mask of ULP_CP_TIMER_SLP_CYCLE field. + RTC_CNTL_RTC_ULP_CP_TIMER_1_ULP_CP_TIMER_SLP_CYCLE_Msk = 0xffffff00 +) + +// Constants for RTC_I2C: Low-power I2C (Inter-Integrated Circuit) Controller +const ( + // SCL_LOW: configure low scl period + // Position of PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_Pos = 0x0 + // Bit mask of PERIOD field. + RTC_I2C_SCL_LOW_PERIOD_Msk = 0xfffff + + // CTRL: configure i2c ctrl + // Position of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Pos = 0x0 + // Bit mask of SDA_FORCE_OUT field. + RTC_I2C_CTRL_SDA_FORCE_OUT_Msk = 0x1 + // Bit SDA_FORCE_OUT. + RTC_I2C_CTRL_SDA_FORCE_OUT = 0x1 + // Position of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Pos = 0x1 + // Bit mask of SCL_FORCE_OUT field. + RTC_I2C_CTRL_SCL_FORCE_OUT_Msk = 0x2 + // Bit SCL_FORCE_OUT. + RTC_I2C_CTRL_SCL_FORCE_OUT = 0x2 + // Position of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Pos = 0x2 + // Bit mask of MS_MODE field. + RTC_I2C_CTRL_MS_MODE_Msk = 0x4 + // Bit MS_MODE. + RTC_I2C_CTRL_MS_MODE = 0x4 + // Position of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Pos = 0x3 + // Bit mask of TRANS_START field. + RTC_I2C_CTRL_TRANS_START_Msk = 0x8 + // Bit TRANS_START. + RTC_I2C_CTRL_TRANS_START = 0x8 + // Position of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Pos = 0x4 + // Bit mask of TX_LSB_FIRST field. + RTC_I2C_CTRL_TX_LSB_FIRST_Msk = 0x10 + // Bit TX_LSB_FIRST. + RTC_I2C_CTRL_TX_LSB_FIRST = 0x10 + // Position of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Pos = 0x5 + // Bit mask of RX_LSB_FIRST field. + RTC_I2C_CTRL_RX_LSB_FIRST_Msk = 0x20 + // Bit RX_LSB_FIRST. + RTC_I2C_CTRL_RX_LSB_FIRST = 0x20 + // Position of I2C_CTRL_CLK_GATE_EN field. + RTC_I2C_CTRL_I2C_CTRL_CLK_GATE_EN_Pos = 0x1d + // Bit mask of I2C_CTRL_CLK_GATE_EN field. + RTC_I2C_CTRL_I2C_CTRL_CLK_GATE_EN_Msk = 0x20000000 + // Bit I2C_CTRL_CLK_GATE_EN. + RTC_I2C_CTRL_I2C_CTRL_CLK_GATE_EN = 0x20000000 + // Position of I2C_RESET field. + RTC_I2C_CTRL_I2C_RESET_Pos = 0x1e + // Bit mask of I2C_RESET field. + RTC_I2C_CTRL_I2C_RESET_Msk = 0x40000000 + // Bit I2C_RESET. + RTC_I2C_CTRL_I2C_RESET = 0x40000000 + // Position of I2CCLK_EN field. + RTC_I2C_CTRL_I2CCLK_EN_Pos = 0x1f + // Bit mask of I2CCLK_EN field. + RTC_I2C_CTRL_I2CCLK_EN_Msk = 0x80000000 + // Bit I2CCLK_EN. + RTC_I2C_CTRL_I2CCLK_EN = 0x80000000 + + // STATUS: get i2c status + // Position of ACK_REC field. + RTC_I2C_STATUS_ACK_REC_Pos = 0x0 + // Bit mask of ACK_REC field. + RTC_I2C_STATUS_ACK_REC_Msk = 0x1 + // Bit ACK_REC. + RTC_I2C_STATUS_ACK_REC = 0x1 + // Position of SLAVE_RW field. + RTC_I2C_STATUS_SLAVE_RW_Pos = 0x1 + // Bit mask of SLAVE_RW field. + RTC_I2C_STATUS_SLAVE_RW_Msk = 0x2 + // Bit SLAVE_RW. + RTC_I2C_STATUS_SLAVE_RW = 0x2 + // Position of ARB_LOST field. + RTC_I2C_STATUS_ARB_LOST_Pos = 0x2 + // Bit mask of ARB_LOST field. + RTC_I2C_STATUS_ARB_LOST_Msk = 0x4 + // Bit ARB_LOST. + RTC_I2C_STATUS_ARB_LOST = 0x4 + // Position of BUS_BUSY field. + RTC_I2C_STATUS_BUS_BUSY_Pos = 0x3 + // Bit mask of BUS_BUSY field. + RTC_I2C_STATUS_BUS_BUSY_Msk = 0x8 + // Bit BUS_BUSY. + RTC_I2C_STATUS_BUS_BUSY = 0x8 + // Position of SLAVE_ADDRESSED field. + RTC_I2C_STATUS_SLAVE_ADDRESSED_Pos = 0x4 + // Bit mask of SLAVE_ADDRESSED field. + RTC_I2C_STATUS_SLAVE_ADDRESSED_Msk = 0x10 + // Bit SLAVE_ADDRESSED. + RTC_I2C_STATUS_SLAVE_ADDRESSED = 0x10 + // Position of BYTE_TRANS field. + RTC_I2C_STATUS_BYTE_TRANS_Pos = 0x5 + // Bit mask of BYTE_TRANS field. + RTC_I2C_STATUS_BYTE_TRANS_Msk = 0x20 + // Bit BYTE_TRANS. + RTC_I2C_STATUS_BYTE_TRANS = 0x20 + // Position of OP_CNT field. + RTC_I2C_STATUS_OP_CNT_Pos = 0x6 + // Bit mask of OP_CNT field. + RTC_I2C_STATUS_OP_CNT_Msk = 0xc0 + // Position of SHIFT field. + RTC_I2C_STATUS_SHIFT_Pos = 0x10 + // Bit mask of SHIFT field. + RTC_I2C_STATUS_SHIFT_Msk = 0xff0000 + // Position of SCL_MAIN_STATE_LAST field. + RTC_I2C_STATUS_SCL_MAIN_STATE_LAST_Pos = 0x18 + // Bit mask of SCL_MAIN_STATE_LAST field. + RTC_I2C_STATUS_SCL_MAIN_STATE_LAST_Msk = 0x7000000 + // Position of SCL_STATE_LAST field. + RTC_I2C_STATUS_SCL_STATE_LAST_Pos = 0x1c + // Bit mask of SCL_STATE_LAST field. + RTC_I2C_STATUS_SCL_STATE_LAST_Msk = 0x70000000 + + // TO: configure time out + // Position of TIME_OUT field. + RTC_I2C_TO_TIME_OUT_Pos = 0x0 + // Bit mask of TIME_OUT field. + RTC_I2C_TO_TIME_OUT_Msk = 0xfffff + + // SLAVE_ADDR: configure slave id + // Position of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0 + // Bit mask of SLAVE_ADDR field. + RTC_I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff + // Position of ADDR_10BIT_EN field. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f + // Bit mask of ADDR_10BIT_EN field. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000 + // Bit ADDR_10BIT_EN. + RTC_I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000 + + // SCL_HIGH: configure high scl period + // Position of PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_Pos = 0x0 + // Bit mask of PERIOD field. + RTC_I2C_SCL_HIGH_PERIOD_Msk = 0xfffff + + // SDA_DUTY: configure sda duty + // Position of NUM field. + RTC_I2C_SDA_DUTY_NUM_Pos = 0x0 + // Bit mask of NUM field. + RTC_I2C_SDA_DUTY_NUM_Msk = 0xfffff + + // SCL_START_PERIOD: configure scl start period + // Position of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Pos = 0x0 + // Bit mask of SCL_START_PERIOD field. + RTC_I2C_SCL_START_PERIOD_SCL_START_PERIOD_Msk = 0xfffff + + // SCL_STOP_PERIOD: configure scl stop period + // Position of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Pos = 0x0 + // Bit mask of SCL_STOP_PERIOD field. + RTC_I2C_SCL_STOP_PERIOD_SCL_STOP_PERIOD_Msk = 0xfffff + + // INT_CLR: interrupt clear register + // Position of SLAVE_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_CLR. + RTC_I2C_INT_CLR_SLAVE_TRAN_COMP_INT_CLR = 0x1 + // Position of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_CLR field. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_CLR. + RTC_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x2 + // Position of MASTER_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_CLR field. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_CLR. + RTC_I2C_INT_CLR_MASTER_TRAN_COMP_INT_CLR = 0x4 + // Position of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_CLR field. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_CLR. + RTC_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x8 + // Position of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x4 + // Bit mask of TIME_OUT_INT_CLR field. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x10 + // Bit TIME_OUT_INT_CLR. + RTC_I2C_INT_CLR_TIME_OUT_INT_CLR = 0x10 + // Position of ACK_ERR_INT_CLR field. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR_Pos = 0x5 + // Bit mask of ACK_ERR_INT_CLR field. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR_Msk = 0x20 + // Bit ACK_ERR_INT_CLR. + RTC_I2C_INT_CLR_ACK_ERR_INT_CLR = 0x20 + // Position of RX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR_Pos = 0x6 + // Bit mask of RX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR_Msk = 0x40 + // Bit RX_DATA_INT_CLR. + RTC_I2C_INT_CLR_RX_DATA_INT_CLR = 0x40 + // Position of TX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR_Pos = 0x7 + // Bit mask of TX_DATA_INT_CLR field. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR_Msk = 0x80 + // Bit TX_DATA_INT_CLR. + RTC_I2C_INT_CLR_TX_DATA_INT_CLR = 0x80 + // Position of DETECT_START_INT_CLR field. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR_Pos = 0x8 + // Bit mask of DETECT_START_INT_CLR field. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR_Msk = 0x100 + // Bit DETECT_START_INT_CLR. + RTC_I2C_INT_CLR_DETECT_START_INT_CLR = 0x100 + + // INT_RAW: interrupt raw register + // Position of SLAVE_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_RAW. + RTC_I2C_INT_RAW_SLAVE_TRAN_COMP_INT_RAW = 0x1 + // Position of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_RAW field. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_RAW. + RTC_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x2 + // Position of MASTER_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_RAW field. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_RAW. + RTC_I2C_INT_RAW_MASTER_TRAN_COMP_INT_RAW = 0x4 + // Position of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_RAW field. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_RAW. + RTC_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x8 + // Position of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x4 + // Bit mask of TIME_OUT_INT_RAW field. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x10 + // Bit TIME_OUT_INT_RAW. + RTC_I2C_INT_RAW_TIME_OUT_INT_RAW = 0x10 + // Position of ACK_ERR_INT_RAW field. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW_Pos = 0x5 + // Bit mask of ACK_ERR_INT_RAW field. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW_Msk = 0x20 + // Bit ACK_ERR_INT_RAW. + RTC_I2C_INT_RAW_ACK_ERR_INT_RAW = 0x20 + // Position of RX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW_Pos = 0x6 + // Bit mask of RX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW_Msk = 0x40 + // Bit RX_DATA_INT_RAW. + RTC_I2C_INT_RAW_RX_DATA_INT_RAW = 0x40 + // Position of TX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW_Pos = 0x7 + // Bit mask of TX_DATA_INT_RAW field. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW_Msk = 0x80 + // Bit TX_DATA_INT_RAW. + RTC_I2C_INT_RAW_TX_DATA_INT_RAW = 0x80 + // Position of DETECT_START_INT_RAW field. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW_Pos = 0x8 + // Bit mask of DETECT_START_INT_RAW field. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW_Msk = 0x100 + // Bit DETECT_START_INT_RAW. + RTC_I2C_INT_RAW_DETECT_START_INT_RAW = 0x100 + + // INT_ST: interrupt state register + // Position of SLAVE_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_ST. + RTC_I2C_INT_ST_SLAVE_TRAN_COMP_INT_ST = 0x1 + // Position of ARBITRATION_LOST_INT_ST field. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_ST field. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_ST. + RTC_I2C_INT_ST_ARBITRATION_LOST_INT_ST = 0x2 + // Position of MASTER_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_ST field. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_ST. + RTC_I2C_INT_ST_MASTER_TRAN_COMP_INT_ST = 0x4 + // Position of TRANS_COMPLETE_INT_ST field. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_ST field. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_ST. + RTC_I2C_INT_ST_TRANS_COMPLETE_INT_ST = 0x8 + // Position of TIME_OUT_INT_ST field. + RTC_I2C_INT_ST_TIME_OUT_INT_ST_Pos = 0x4 + // Bit mask of TIME_OUT_INT_ST field. + RTC_I2C_INT_ST_TIME_OUT_INT_ST_Msk = 0x10 + // Bit TIME_OUT_INT_ST. + RTC_I2C_INT_ST_TIME_OUT_INT_ST = 0x10 + // Position of ACK_ERR_INT_ST field. + RTC_I2C_INT_ST_ACK_ERR_INT_ST_Pos = 0x5 + // Bit mask of ACK_ERR_INT_ST field. + RTC_I2C_INT_ST_ACK_ERR_INT_ST_Msk = 0x20 + // Bit ACK_ERR_INT_ST. + RTC_I2C_INT_ST_ACK_ERR_INT_ST = 0x20 + // Position of RX_DATA_INT_ST field. + RTC_I2C_INT_ST_RX_DATA_INT_ST_Pos = 0x6 + // Bit mask of RX_DATA_INT_ST field. + RTC_I2C_INT_ST_RX_DATA_INT_ST_Msk = 0x40 + // Bit RX_DATA_INT_ST. + RTC_I2C_INT_ST_RX_DATA_INT_ST = 0x40 + // Position of TX_DATA_INT_ST field. + RTC_I2C_INT_ST_TX_DATA_INT_ST_Pos = 0x7 + // Bit mask of TX_DATA_INT_ST field. + RTC_I2C_INT_ST_TX_DATA_INT_ST_Msk = 0x80 + // Bit TX_DATA_INT_ST. + RTC_I2C_INT_ST_TX_DATA_INT_ST = 0x80 + // Position of DETECT_START_INT_ST field. + RTC_I2C_INT_ST_DETECT_START_INT_ST_Pos = 0x8 + // Bit mask of DETECT_START_INT_ST field. + RTC_I2C_INT_ST_DETECT_START_INT_ST_Msk = 0x100 + // Bit DETECT_START_INT_ST. + RTC_I2C_INT_ST_DETECT_START_INT_ST = 0x100 + + // INT_ENA: interrupt enable register + // Position of SLAVE_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Pos = 0x0 + // Bit mask of SLAVE_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA_Msk = 0x1 + // Bit SLAVE_TRAN_COMP_INT_ENA. + RTC_I2C_INT_ENA_SLAVE_TRAN_COMP_INT_ENA = 0x1 + // Position of ARBITRATION_LOST_INT_ENA field. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x1 + // Bit mask of ARBITRATION_LOST_INT_ENA field. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x2 + // Bit ARBITRATION_LOST_INT_ENA. + RTC_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x2 + // Position of MASTER_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Pos = 0x2 + // Bit mask of MASTER_TRAN_COMP_INT_ENA field. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA_Msk = 0x4 + // Bit MASTER_TRAN_COMP_INT_ENA. + RTC_I2C_INT_ENA_MASTER_TRAN_COMP_INT_ENA = 0x4 + // Position of TRANS_COMPLETE_INT_ENA field. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x3 + // Bit mask of TRANS_COMPLETE_INT_ENA field. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x8 + // Bit TRANS_COMPLETE_INT_ENA. + RTC_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x8 + // Position of TIME_OUT_INT_ENA field. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x4 + // Bit mask of TIME_OUT_INT_ENA field. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x10 + // Bit TIME_OUT_INT_ENA. + RTC_I2C_INT_ENA_TIME_OUT_INT_ENA = 0x10 + // Position of ACK_ERR_INT_ENA field. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA_Pos = 0x5 + // Bit mask of ACK_ERR_INT_ENA field. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA_Msk = 0x20 + // Bit ACK_ERR_INT_ENA. + RTC_I2C_INT_ENA_ACK_ERR_INT_ENA = 0x20 + // Position of RX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA_Pos = 0x6 + // Bit mask of RX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA_Msk = 0x40 + // Bit RX_DATA_INT_ENA. + RTC_I2C_INT_ENA_RX_DATA_INT_ENA = 0x40 + // Position of TX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA_Pos = 0x7 + // Bit mask of TX_DATA_INT_ENA field. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA_Msk = 0x80 + // Bit TX_DATA_INT_ENA. + RTC_I2C_INT_ENA_TX_DATA_INT_ENA = 0x80 + // Position of DETECT_START_INT_ENA field. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA_Pos = 0x8 + // Bit mask of DETECT_START_INT_ENA field. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA_Msk = 0x100 + // Bit DETECT_START_INT_ENA. + RTC_I2C_INT_ENA_DETECT_START_INT_ENA = 0x100 + + // DATA: get i2c data status + // Position of I2C_RDATA field. + RTC_I2C_DATA_I2C_RDATA_Pos = 0x0 + // Bit mask of I2C_RDATA field. + RTC_I2C_DATA_I2C_RDATA_Msk = 0xff + // Position of SLAVE_TX_DATA field. + RTC_I2C_DATA_SLAVE_TX_DATA_Pos = 0x8 + // Bit mask of SLAVE_TX_DATA field. + RTC_I2C_DATA_SLAVE_TX_DATA_Msk = 0xff00 + // Position of I2C_DONE field. + RTC_I2C_DATA_I2C_DONE_Pos = 0x1f + // Bit mask of I2C_DONE field. + RTC_I2C_DATA_I2C_DONE_Msk = 0x80000000 + // Bit I2C_DONE. + RTC_I2C_DATA_I2C_DONE = 0x80000000 + + // CMD0: i2c commond0 register + // Position of COMMAND0 field. + RTC_I2C_CMD0_COMMAND0_Pos = 0x0 + // Bit mask of COMMAND0 field. + RTC_I2C_CMD0_COMMAND0_Msk = 0x3fff + // Position of COMMAND0_DONE field. + RTC_I2C_CMD0_COMMAND0_DONE_Pos = 0x1f + // Bit mask of COMMAND0_DONE field. + RTC_I2C_CMD0_COMMAND0_DONE_Msk = 0x80000000 + // Bit COMMAND0_DONE. + RTC_I2C_CMD0_COMMAND0_DONE = 0x80000000 + + // CMD1: i2c commond1 register + // Position of COMMAND1 field. + RTC_I2C_CMD1_COMMAND1_Pos = 0x0 + // Bit mask of COMMAND1 field. + RTC_I2C_CMD1_COMMAND1_Msk = 0x3fff + // Position of COMMAND1_DONE field. + RTC_I2C_CMD1_COMMAND1_DONE_Pos = 0x1f + // Bit mask of COMMAND1_DONE field. + RTC_I2C_CMD1_COMMAND1_DONE_Msk = 0x80000000 + // Bit COMMAND1_DONE. + RTC_I2C_CMD1_COMMAND1_DONE = 0x80000000 + + // CMD2: i2c commond2 register + // Position of COMMAND2 field. + RTC_I2C_CMD2_COMMAND2_Pos = 0x0 + // Bit mask of COMMAND2 field. + RTC_I2C_CMD2_COMMAND2_Msk = 0x3fff + // Position of COMMAND2_DONE field. + RTC_I2C_CMD2_COMMAND2_DONE_Pos = 0x1f + // Bit mask of COMMAND2_DONE field. + RTC_I2C_CMD2_COMMAND2_DONE_Msk = 0x80000000 + // Bit COMMAND2_DONE. + RTC_I2C_CMD2_COMMAND2_DONE = 0x80000000 + + // CMD3: i2c commond3 register + // Position of COMMAND3 field. + RTC_I2C_CMD3_COMMAND3_Pos = 0x0 + // Bit mask of COMMAND3 field. + RTC_I2C_CMD3_COMMAND3_Msk = 0x3fff + // Position of COMMAND3_DONE field. + RTC_I2C_CMD3_COMMAND3_DONE_Pos = 0x1f + // Bit mask of COMMAND3_DONE field. + RTC_I2C_CMD3_COMMAND3_DONE_Msk = 0x80000000 + // Bit COMMAND3_DONE. + RTC_I2C_CMD3_COMMAND3_DONE = 0x80000000 + + // CMD4: i2c commond4 register + // Position of COMMAND4 field. + RTC_I2C_CMD4_COMMAND4_Pos = 0x0 + // Bit mask of COMMAND4 field. + RTC_I2C_CMD4_COMMAND4_Msk = 0x3fff + // Position of COMMAND4_DONE field. + RTC_I2C_CMD4_COMMAND4_DONE_Pos = 0x1f + // Bit mask of COMMAND4_DONE field. + RTC_I2C_CMD4_COMMAND4_DONE_Msk = 0x80000000 + // Bit COMMAND4_DONE. + RTC_I2C_CMD4_COMMAND4_DONE = 0x80000000 + + // CMD5: i2c commond5_register + // Position of COMMAND5 field. + RTC_I2C_CMD5_COMMAND5_Pos = 0x0 + // Bit mask of COMMAND5 field. + RTC_I2C_CMD5_COMMAND5_Msk = 0x3fff + // Position of COMMAND5_DONE field. + RTC_I2C_CMD5_COMMAND5_DONE_Pos = 0x1f + // Bit mask of COMMAND5_DONE field. + RTC_I2C_CMD5_COMMAND5_DONE_Msk = 0x80000000 + // Bit COMMAND5_DONE. + RTC_I2C_CMD5_COMMAND5_DONE = 0x80000000 + + // CMD6: i2c commond6 register + // Position of COMMAND6 field. + RTC_I2C_CMD6_COMMAND6_Pos = 0x0 + // Bit mask of COMMAND6 field. + RTC_I2C_CMD6_COMMAND6_Msk = 0x3fff + // Position of COMMAND6_DONE field. + RTC_I2C_CMD6_COMMAND6_DONE_Pos = 0x1f + // Bit mask of COMMAND6_DONE field. + RTC_I2C_CMD6_COMMAND6_DONE_Msk = 0x80000000 + // Bit COMMAND6_DONE. + RTC_I2C_CMD6_COMMAND6_DONE = 0x80000000 + + // CMD7: i2c commond7 register + // Position of COMMAND7 field. + RTC_I2C_CMD7_COMMAND7_Pos = 0x0 + // Bit mask of COMMAND7 field. + RTC_I2C_CMD7_COMMAND7_Msk = 0x3fff + // Position of COMMAND7_DONE field. + RTC_I2C_CMD7_COMMAND7_DONE_Pos = 0x1f + // Bit mask of COMMAND7_DONE field. + RTC_I2C_CMD7_COMMAND7_DONE_Msk = 0x80000000 + // Bit COMMAND7_DONE. + RTC_I2C_CMD7_COMMAND7_DONE = 0x80000000 + + // CMD8: i2c commond8 register + // Position of COMMAND8 field. + RTC_I2C_CMD8_COMMAND8_Pos = 0x0 + // Bit mask of COMMAND8 field. + RTC_I2C_CMD8_COMMAND8_Msk = 0x3fff + // Position of COMMAND8_DONE field. + RTC_I2C_CMD8_COMMAND8_DONE_Pos = 0x1f + // Bit mask of COMMAND8_DONE field. + RTC_I2C_CMD8_COMMAND8_DONE_Msk = 0x80000000 + // Bit COMMAND8_DONE. + RTC_I2C_CMD8_COMMAND8_DONE = 0x80000000 + + // CMD9: i2c commond9 register + // Position of COMMAND9 field. + RTC_I2C_CMD9_COMMAND9_Pos = 0x0 + // Bit mask of COMMAND9 field. + RTC_I2C_CMD9_COMMAND9_Msk = 0x3fff + // Position of COMMAND9_DONE field. + RTC_I2C_CMD9_COMMAND9_DONE_Pos = 0x1f + // Bit mask of COMMAND9_DONE field. + RTC_I2C_CMD9_COMMAND9_DONE_Msk = 0x80000000 + // Bit COMMAND9_DONE. + RTC_I2C_CMD9_COMMAND9_DONE = 0x80000000 + + // CMD10: i2c commond10 register + // Position of COMMAND10 field. + RTC_I2C_CMD10_COMMAND10_Pos = 0x0 + // Bit mask of COMMAND10 field. + RTC_I2C_CMD10_COMMAND10_Msk = 0x3fff + // Position of COMMAND10_DONE field. + RTC_I2C_CMD10_COMMAND10_DONE_Pos = 0x1f + // Bit mask of COMMAND10_DONE field. + RTC_I2C_CMD10_COMMAND10_DONE_Msk = 0x80000000 + // Bit COMMAND10_DONE. + RTC_I2C_CMD10_COMMAND10_DONE = 0x80000000 + + // CMD11: i2c commond11 register + // Position of COMMAND11 field. + RTC_I2C_CMD11_COMMAND11_Pos = 0x0 + // Bit mask of COMMAND11 field. + RTC_I2C_CMD11_COMMAND11_Msk = 0x3fff + // Position of COMMAND11_DONE field. + RTC_I2C_CMD11_COMMAND11_DONE_Pos = 0x1f + // Bit mask of COMMAND11_DONE field. + RTC_I2C_CMD11_COMMAND11_DONE_Msk = 0x80000000 + // Bit COMMAND11_DONE. + RTC_I2C_CMD11_COMMAND11_DONE = 0x80000000 + + // CMD12: i2c commond12 register + // Position of COMMAND12 field. + RTC_I2C_CMD12_COMMAND12_Pos = 0x0 + // Bit mask of COMMAND12 field. + RTC_I2C_CMD12_COMMAND12_Msk = 0x3fff + // Position of COMMAND12_DONE field. + RTC_I2C_CMD12_COMMAND12_DONE_Pos = 0x1f + // Bit mask of COMMAND12_DONE field. + RTC_I2C_CMD12_COMMAND12_DONE_Msk = 0x80000000 + // Bit COMMAND12_DONE. + RTC_I2C_CMD12_COMMAND12_DONE = 0x80000000 + + // CMD13: i2c commond13 register + // Position of COMMAND13 field. + RTC_I2C_CMD13_COMMAND13_Pos = 0x0 + // Bit mask of COMMAND13 field. + RTC_I2C_CMD13_COMMAND13_Msk = 0x3fff + // Position of COMMAND13_DONE field. + RTC_I2C_CMD13_COMMAND13_DONE_Pos = 0x1f + // Bit mask of COMMAND13_DONE field. + RTC_I2C_CMD13_COMMAND13_DONE_Msk = 0x80000000 + // Bit COMMAND13_DONE. + RTC_I2C_CMD13_COMMAND13_DONE = 0x80000000 + + // CMD14: i2c commond14 register + // Position of COMMAND14 field. + RTC_I2C_CMD14_COMMAND14_Pos = 0x0 + // Bit mask of COMMAND14 field. + RTC_I2C_CMD14_COMMAND14_Msk = 0x3fff + // Position of COMMAND14_DONE field. + RTC_I2C_CMD14_COMMAND14_DONE_Pos = 0x1f + // Bit mask of COMMAND14_DONE field. + RTC_I2C_CMD14_COMMAND14_DONE_Msk = 0x80000000 + // Bit COMMAND14_DONE. + RTC_I2C_CMD14_COMMAND14_DONE = 0x80000000 + + // CMD15: i2c commond15 register + // Position of COMMAND15 field. + RTC_I2C_CMD15_COMMAND15_Pos = 0x0 + // Bit mask of COMMAND15 field. + RTC_I2C_CMD15_COMMAND15_Msk = 0x3fff + // Position of COMMAND15_DONE field. + RTC_I2C_CMD15_COMMAND15_DONE_Pos = 0x1f + // Bit mask of COMMAND15_DONE field. + RTC_I2C_CMD15_COMMAND15_DONE_Msk = 0x80000000 + // Bit COMMAND15_DONE. + RTC_I2C_CMD15_COMMAND15_DONE = 0x80000000 + + // DATE: version register + // Position of I2C_DATE field. + RTC_I2C_DATE_I2C_DATE_Pos = 0x0 + // Bit mask of I2C_DATE field. + RTC_I2C_DATE_I2C_DATE_Msk = 0xfffffff +) + +// Constants for RTC_IO: Low-power Input/Output +const ( + // RTC_GPIO_OUT: RTC GPIO 0 ~ 21 output data register + // Position of DATA field. + RTC_IO_RTC_GPIO_OUT_DATA_Pos = 0xa + // Bit mask of DATA field. + RTC_IO_RTC_GPIO_OUT_DATA_Msk = 0xfffffc00 + + // RTC_GPIO_OUT_W1TS: one set RTC GPIO output data + // Position of RTC_GPIO_OUT_DATA_W1TS field. + RTC_IO_RTC_GPIO_OUT_W1TS_RTC_GPIO_OUT_DATA_W1TS_Pos = 0xa + // Bit mask of RTC_GPIO_OUT_DATA_W1TS field. + RTC_IO_RTC_GPIO_OUT_W1TS_RTC_GPIO_OUT_DATA_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_OUT_W1TC: one clear RTC GPIO output data + // Position of RTC_GPIO_OUT_DATA_W1TC field. + RTC_IO_RTC_GPIO_OUT_W1TC_RTC_GPIO_OUT_DATA_W1TC_Pos = 0xa + // Bit mask of RTC_GPIO_OUT_DATA_W1TC field. + RTC_IO_RTC_GPIO_OUT_W1TC_RTC_GPIO_OUT_DATA_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE: Configure RTC GPIO output enable + // Position of RTC_GPIO_ENABLE field. + RTC_IO_RTC_GPIO_ENABLE_RTC_GPIO_ENABLE_Pos = 0xa + // Bit mask of RTC_GPIO_ENABLE field. + RTC_IO_RTC_GPIO_ENABLE_RTC_GPIO_ENABLE_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE_W1TS: one set RTC GPIO output enable + // Position of RTC_GPIO_ENABLE_W1TS field. + RTC_IO_RTC_GPIO_ENABLE_W1TS_RTC_GPIO_ENABLE_W1TS_Pos = 0xa + // Bit mask of RTC_GPIO_ENABLE_W1TS field. + RTC_IO_RTC_GPIO_ENABLE_W1TS_RTC_GPIO_ENABLE_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_ENABLE_W1TC: one clear RTC GPIO output enable + // Position of RTC_GPIO_ENABLE_W1TC field. + RTC_IO_RTC_GPIO_ENABLE_W1TC_RTC_GPIO_ENABLE_W1TC_Pos = 0xa + // Bit mask of RTC_GPIO_ENABLE_W1TC field. + RTC_IO_RTC_GPIO_ENABLE_W1TC_RTC_GPIO_ENABLE_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS: RTC GPIO 0 ~ 21 interrupt status + // Position of INT field. + RTC_IO_RTC_GPIO_STATUS_INT_Pos = 0xa + // Bit mask of INT field. + RTC_IO_RTC_GPIO_STATUS_INT_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS_W1TS: One set RTC GPIO 0 ~ 21 interrupt status + // Position of RTC_GPIO_STATUS_INT_W1TS field. + RTC_IO_RTC_GPIO_STATUS_W1TS_RTC_GPIO_STATUS_INT_W1TS_Pos = 0xa + // Bit mask of RTC_GPIO_STATUS_INT_W1TS field. + RTC_IO_RTC_GPIO_STATUS_W1TS_RTC_GPIO_STATUS_INT_W1TS_Msk = 0xfffffc00 + + // RTC_GPIO_STATUS_W1TC: One clear RTC GPIO 0 ~ 21 interrupt status + // Position of RTC_GPIO_STATUS_INT_W1TC field. + RTC_IO_RTC_GPIO_STATUS_W1TC_RTC_GPIO_STATUS_INT_W1TC_Pos = 0xa + // Bit mask of RTC_GPIO_STATUS_INT_W1TC field. + RTC_IO_RTC_GPIO_STATUS_W1TC_RTC_GPIO_STATUS_INT_W1TC_Msk = 0xfffffc00 + + // RTC_GPIO_IN: RTC GPIO input data + // Position of NEXT field. + RTC_IO_RTC_GPIO_IN_NEXT_Pos = 0xa + // Bit mask of NEXT field. + RTC_IO_RTC_GPIO_IN_NEXT_Msk = 0xfffffc00 + + // RTC_GPIO_PIN0: configure RTC GPIO0 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN0_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN0_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN0_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN0_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN0_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN0_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN0_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN0_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN1: configure RTC GPIO1 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN1_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN1_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN1_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN1_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN1_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN1_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN1_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN1_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN2: configure RTC GPIO2 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN2_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN2_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN2_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN2_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN2_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN2_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN2_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN2_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN3: configure RTC GPIO3 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN3_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN3_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN3_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN3_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN3_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN3_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN3_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN3_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN4: configure RTC GPIO4 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN4_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN4_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN4_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN4_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN4_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN4_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN4_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN4_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN5: configure RTC GPIO5 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN5_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN5_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN5_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN5_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN5_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN5_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN5_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN5_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN6: configure RTC GPIO6 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN6_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN6_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN6_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN6_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN6_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN6_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN6_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN6_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN7: configure RTC GPIO7 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN7_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN7_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN7_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN7_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN7_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN7_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN7_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN7_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN8: configure RTC GPIO8 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN8_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN8_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN8_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN8_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN8_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN8_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN8_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN8_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN9: configure RTC GPIO9 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN9_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN9_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN9_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN9_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN9_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN9_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN9_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN9_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN10: configure RTC GPIO10 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN10_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN10_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN10_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN10_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN10_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN10_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN10_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN10_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN11: configure RTC GPIO11 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN11_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN11_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN11_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN11_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN11_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN11_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN11_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN11_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN12: configure RTC GPIO12 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN12_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN12_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN12_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN12_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN12_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN12_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN12_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN12_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN13: configure RTC GPIO13 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN13_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN13_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN13_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN13_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN13_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN13_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN13_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN13_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN14: configure RTC GPIO14 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN14_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN14_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN14_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN14_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN14_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN14_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN14_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN14_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN15: configure RTC GPIO15 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN15_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN15_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN15_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN15_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN15_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN15_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN15_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN15_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN16: configure RTC GPIO16 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN16_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN16_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN16_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN16_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN16_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN16_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN16_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN16_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN17: configure RTC GPIO17 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN17_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN17_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN17_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN17_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN17_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN17_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN17_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN17_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN18: configure RTC GPIO18 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN18_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN18_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN18_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN18_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN18_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN18_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN18_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN18_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN19: configure RTC GPIO19 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN19_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN19_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN19_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN19_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN19_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN19_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN19_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN19_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN20: configure RTC GPIO20 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN20_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN20_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN20_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN20_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN20_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN20_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN20_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN20_WAKEUP_ENABLE = 0x400 + + // RTC_GPIO_PIN21: configure RTC GPIO21 + // Position of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN21_PAD_DRIVER_Pos = 0x2 + // Bit mask of PAD_DRIVER field. + RTC_IO_RTC_GPIO_PIN21_PAD_DRIVER_Msk = 0x4 + // Bit PAD_DRIVER. + RTC_IO_RTC_GPIO_PIN21_PAD_DRIVER = 0x4 + // Position of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN21_INT_TYPE_Pos = 0x7 + // Bit mask of INT_TYPE field. + RTC_IO_RTC_GPIO_PIN21_INT_TYPE_Msk = 0x380 + // Position of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN21_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of WAKEUP_ENABLE field. + RTC_IO_RTC_GPIO_PIN21_WAKEUP_ENABLE_Msk = 0x400 + // Bit WAKEUP_ENABLE. + RTC_IO_RTC_GPIO_PIN21_WAKEUP_ENABLE = 0x400 + + // RTC_DEBUG_SEL: configure rtc debug + // Position of RTC_DEBUG_SEL0 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL0_Pos = 0x0 + // Bit mask of RTC_DEBUG_SEL0 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL0_Msk = 0x1f + // Position of RTC_DEBUG_SEL1 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL1_Pos = 0x5 + // Bit mask of RTC_DEBUG_SEL1 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL1_Msk = 0x3e0 + // Position of RTC_DEBUG_SEL2 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL2_Pos = 0xa + // Bit mask of RTC_DEBUG_SEL2 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL2_Msk = 0x7c00 + // Position of RTC_DEBUG_SEL3 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL3_Pos = 0xf + // Bit mask of RTC_DEBUG_SEL3 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL3_Msk = 0xf8000 + // Position of RTC_DEBUG_SEL4 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL4_Pos = 0x14 + // Bit mask of RTC_DEBUG_SEL4 field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_SEL4_Msk = 0x1f00000 + // Position of RTC_DEBUG_12M_NO_GATING field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING_Pos = 0x19 + // Bit mask of RTC_DEBUG_12M_NO_GATING field. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING_Msk = 0x2000000 + // Bit RTC_DEBUG_12M_NO_GATING. + RTC_IO_RTC_DEBUG_SEL_RTC_DEBUG_12M_NO_GATING = 0x2000000 + + // TOUCH_PAD0: configure RTC PAD0 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD0_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD0_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD0_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD0_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD0_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD0_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD0_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD0_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD0_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD0_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD0_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD0_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD0_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD0_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD0_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD0_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD0_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD0_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD0_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD0_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD0_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD0_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD0_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD0_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD0_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD0_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD0_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD0_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD0_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD0_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD0_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD0_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD0_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD0_DRV_Msk = 0x60000000 + + // TOUCH_PAD1: configure RTC PAD1 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD1_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD1_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD1_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD1_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD1_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD1_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD1_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD1_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD1_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD1_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD1_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD1_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD1_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD1_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD1_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD1_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD1_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD1_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD1_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD1_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD1_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD1_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD1_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD1_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD1_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD1_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD1_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD1_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD1_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD1_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD1_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD1_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD1_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD1_DRV_Msk = 0x60000000 + + // TOUCH_PAD2: configure RTC PAD2 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD2_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD2_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD2_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD2_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD2_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD2_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD2_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD2_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD2_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD2_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD2_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD2_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD2_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD2_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD2_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD2_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD2_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD2_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD2_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD2_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD2_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD2_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD2_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD2_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD2_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD2_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD2_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD2_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD2_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD2_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD2_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD2_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD2_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD2_DRV_Msk = 0x60000000 + + // TOUCH_PAD3: configure RTC PAD3 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD3_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD3_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD3_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD3_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD3_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD3_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD3_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD3_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD3_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD3_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD3_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD3_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD3_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD3_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD3_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD3_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD3_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD3_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD3_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD3_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD3_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD3_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD3_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD3_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD3_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD3_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD3_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD3_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD3_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD3_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD3_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD3_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD3_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD3_DRV_Msk = 0x60000000 + + // TOUCH_PAD4: configure RTC PAD4 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD4_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD4_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD4_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD4_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD4_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD4_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD4_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD4_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD4_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD4_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD4_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD4_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD4_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD4_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD4_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD4_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD4_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD4_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD4_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD4_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD4_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD4_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD4_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD4_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD4_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD4_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD4_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD4_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD4_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD4_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD4_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD4_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD4_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD4_DRV_Msk = 0x60000000 + + // TOUCH_PAD5: configure RTC PAD5 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD5_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD5_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD5_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD5_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD5_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD5_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD5_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD5_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD5_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD5_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD5_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD5_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD5_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD5_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD5_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD5_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD5_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD5_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD5_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD5_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD5_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD5_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD5_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD5_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD5_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD5_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD5_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD5_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD5_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD5_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD5_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD5_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD5_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD5_DRV_Msk = 0x60000000 + + // TOUCH_PAD6: configure RTC PAD6 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD6_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD6_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD6_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD6_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD6_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD6_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD6_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD6_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD6_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD6_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD6_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD6_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD6_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD6_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD6_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD6_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD6_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD6_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD6_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD6_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD6_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD6_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD6_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD6_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD6_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD6_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD6_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD6_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD6_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD6_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD6_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD6_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD6_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD6_DRV_Msk = 0x60000000 + + // TOUCH_PAD7: configure RTC PAD7 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD7_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD7_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD7_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD7_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD7_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD7_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD7_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD7_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD7_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD7_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD7_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD7_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD7_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD7_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD7_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD7_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD7_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD7_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD7_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD7_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD7_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD7_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD7_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD7_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD7_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD7_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD7_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD7_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD7_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD7_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD7_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD7_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD7_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD7_DRV_Msk = 0x60000000 + + // TOUCH_PAD8: configure RTC PAD8 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD8_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD8_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD8_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD8_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD8_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD8_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD8_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD8_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD8_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD8_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD8_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD8_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD8_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD8_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD8_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD8_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD8_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD8_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD8_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD8_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD8_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD8_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD8_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD8_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD8_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD8_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD8_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD8_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD8_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD8_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD8_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD8_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD8_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD8_DRV_Msk = 0x60000000 + + // TOUCH_PAD9: configure RTC PAD9 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD9_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD9_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD9_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD9_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD9_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD9_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD9_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD9_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD9_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD9_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD9_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD9_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD9_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD9_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD9_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD9_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD9_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD9_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD9_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD9_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD9_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD9_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD9_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD9_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD9_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD9_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD9_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD9_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD9_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD9_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD9_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD9_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD9_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD9_DRV_Msk = 0x60000000 + + // TOUCH_PAD10: configure RTC PAD10 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD10_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD10_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD10_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD10_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD10_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD10_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD10_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD10_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD10_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD10_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD10_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD10_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD10_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD10_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD10_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD10_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD10_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD10_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD10_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD10_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD10_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD10_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD10_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD10_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD10_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD10_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD10_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD10_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD10_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD10_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD10_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD10_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD10_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD10_DRV_Msk = 0x60000000 + + // TOUCH_PAD11: configure RTC PAD11 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD11_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD11_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD11_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD11_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD11_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD11_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD11_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD11_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD11_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD11_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD11_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD11_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD11_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD11_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD11_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD11_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD11_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD11_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD11_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD11_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD11_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD11_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD11_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD11_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD11_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD11_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD11_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD11_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD11_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD11_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD11_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD11_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD11_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD11_DRV_Msk = 0x60000000 + + // TOUCH_PAD12: configure RTC PAD12 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD12_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD12_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD12_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD12_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD12_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD12_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD12_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD12_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD12_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD12_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD12_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD12_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD12_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD12_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD12_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD12_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD12_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD12_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD12_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD12_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD12_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD12_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD12_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD12_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD12_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD12_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD12_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD12_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD12_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD12_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD12_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD12_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD12_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD12_DRV_Msk = 0x60000000 + + // TOUCH_PAD13: configure RTC PAD13 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD13_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD13_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD13_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD13_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD13_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD13_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD13_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD13_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD13_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD13_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD13_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD13_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD13_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD13_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD13_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD13_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD13_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD13_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD13_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD13_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD13_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD13_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD13_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD13_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD13_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD13_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD13_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD13_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD13_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD13_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD13_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD13_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD13_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD13_DRV_Msk = 0x60000000 + + // TOUCH_PAD14: configure RTC PAD14 + // Position of FUN_IE field. + RTC_IO_TOUCH_PAD14_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_TOUCH_PAD14_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_TOUCH_PAD14_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_TOUCH_PAD14_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_TOUCH_PAD14_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_TOUCH_PAD14_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_TOUCH_PAD14_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_TOUCH_PAD14_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_TOUCH_PAD14_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_TOUCH_PAD14_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_TOUCH_PAD14_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_TOUCH_PAD14_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_TOUCH_PAD14_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_TOUCH_PAD14_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_TOUCH_PAD14_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_TOUCH_PAD14_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_TOUCH_PAD14_MUX_SEL = 0x80000 + // Position of XPD field. + RTC_IO_TOUCH_PAD14_XPD_Pos = 0x14 + // Bit mask of XPD field. + RTC_IO_TOUCH_PAD14_XPD_Msk = 0x100000 + // Bit XPD. + RTC_IO_TOUCH_PAD14_XPD = 0x100000 + // Position of TIE_OPT field. + RTC_IO_TOUCH_PAD14_TIE_OPT_Pos = 0x15 + // Bit mask of TIE_OPT field. + RTC_IO_TOUCH_PAD14_TIE_OPT_Msk = 0x200000 + // Bit TIE_OPT. + RTC_IO_TOUCH_PAD14_TIE_OPT = 0x200000 + // Position of START field. + RTC_IO_TOUCH_PAD14_START_Pos = 0x16 + // Bit mask of START field. + RTC_IO_TOUCH_PAD14_START_Msk = 0x400000 + // Bit START. + RTC_IO_TOUCH_PAD14_START = 0x400000 + // Position of RUE field. + RTC_IO_TOUCH_PAD14_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_TOUCH_PAD14_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_TOUCH_PAD14_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_TOUCH_PAD14_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_TOUCH_PAD14_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_TOUCH_PAD14_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_TOUCH_PAD14_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_TOUCH_PAD14_DRV_Msk = 0x60000000 + + // XTAL_32P_PAD: configure RTC PAD15 + // Position of X32P_FUN_IE field. + RTC_IO_XTAL_32P_PAD_X32P_FUN_IE_Pos = 0xd + // Bit mask of X32P_FUN_IE field. + RTC_IO_XTAL_32P_PAD_X32P_FUN_IE_Msk = 0x2000 + // Bit X32P_FUN_IE. + RTC_IO_XTAL_32P_PAD_X32P_FUN_IE = 0x2000 + // Position of X32P_SLP_OE field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_OE_Pos = 0xe + // Bit mask of X32P_SLP_OE field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_OE_Msk = 0x4000 + // Bit X32P_SLP_OE. + RTC_IO_XTAL_32P_PAD_X32P_SLP_OE = 0x4000 + // Position of X32P_SLP_IE field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_IE_Pos = 0xf + // Bit mask of X32P_SLP_IE field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_IE_Msk = 0x8000 + // Bit X32P_SLP_IE. + RTC_IO_XTAL_32P_PAD_X32P_SLP_IE = 0x8000 + // Position of X32P_SLP_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_SEL_Pos = 0x10 + // Bit mask of X32P_SLP_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_SLP_SEL_Msk = 0x10000 + // Bit X32P_SLP_SEL. + RTC_IO_XTAL_32P_PAD_X32P_SLP_SEL = 0x10000 + // Position of X32P_FUN_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_FUN_SEL_Pos = 0x11 + // Bit mask of X32P_FUN_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_FUN_SEL_Msk = 0x60000 + // Position of X32P_MUX_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_MUX_SEL_Pos = 0x13 + // Bit mask of X32P_MUX_SEL field. + RTC_IO_XTAL_32P_PAD_X32P_MUX_SEL_Msk = 0x80000 + // Bit X32P_MUX_SEL. + RTC_IO_XTAL_32P_PAD_X32P_MUX_SEL = 0x80000 + // Position of X32P_RUE field. + RTC_IO_XTAL_32P_PAD_X32P_RUE_Pos = 0x1b + // Bit mask of X32P_RUE field. + RTC_IO_XTAL_32P_PAD_X32P_RUE_Msk = 0x8000000 + // Bit X32P_RUE. + RTC_IO_XTAL_32P_PAD_X32P_RUE = 0x8000000 + // Position of X32P_RDE field. + RTC_IO_XTAL_32P_PAD_X32P_RDE_Pos = 0x1c + // Bit mask of X32P_RDE field. + RTC_IO_XTAL_32P_PAD_X32P_RDE_Msk = 0x10000000 + // Bit X32P_RDE. + RTC_IO_XTAL_32P_PAD_X32P_RDE = 0x10000000 + // Position of X32P_DRV field. + RTC_IO_XTAL_32P_PAD_X32P_DRV_Pos = 0x1d + // Bit mask of X32P_DRV field. + RTC_IO_XTAL_32P_PAD_X32P_DRV_Msk = 0x60000000 + + // XTAL_32N_PAD: configure RTC PAD16 + // Position of X32N_FUN_IE field. + RTC_IO_XTAL_32N_PAD_X32N_FUN_IE_Pos = 0xd + // Bit mask of X32N_FUN_IE field. + RTC_IO_XTAL_32N_PAD_X32N_FUN_IE_Msk = 0x2000 + // Bit X32N_FUN_IE. + RTC_IO_XTAL_32N_PAD_X32N_FUN_IE = 0x2000 + // Position of X32N_SLP_OE field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_OE_Pos = 0xe + // Bit mask of X32N_SLP_OE field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_OE_Msk = 0x4000 + // Bit X32N_SLP_OE. + RTC_IO_XTAL_32N_PAD_X32N_SLP_OE = 0x4000 + // Position of X32N_SLP_IE field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_IE_Pos = 0xf + // Bit mask of X32N_SLP_IE field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_IE_Msk = 0x8000 + // Bit X32N_SLP_IE. + RTC_IO_XTAL_32N_PAD_X32N_SLP_IE = 0x8000 + // Position of X32N_SLP_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_SEL_Pos = 0x10 + // Bit mask of X32N_SLP_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_SLP_SEL_Msk = 0x10000 + // Bit X32N_SLP_SEL. + RTC_IO_XTAL_32N_PAD_X32N_SLP_SEL = 0x10000 + // Position of X32N_FUN_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_FUN_SEL_Pos = 0x11 + // Bit mask of X32N_FUN_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_FUN_SEL_Msk = 0x60000 + // Position of X32N_MUX_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_MUX_SEL_Pos = 0x13 + // Bit mask of X32N_MUX_SEL field. + RTC_IO_XTAL_32N_PAD_X32N_MUX_SEL_Msk = 0x80000 + // Bit X32N_MUX_SEL. + RTC_IO_XTAL_32N_PAD_X32N_MUX_SEL = 0x80000 + // Position of X32N_RUE field. + RTC_IO_XTAL_32N_PAD_X32N_RUE_Pos = 0x1b + // Bit mask of X32N_RUE field. + RTC_IO_XTAL_32N_PAD_X32N_RUE_Msk = 0x8000000 + // Bit X32N_RUE. + RTC_IO_XTAL_32N_PAD_X32N_RUE = 0x8000000 + // Position of X32N_RDE field. + RTC_IO_XTAL_32N_PAD_X32N_RDE_Pos = 0x1c + // Bit mask of X32N_RDE field. + RTC_IO_XTAL_32N_PAD_X32N_RDE_Msk = 0x10000000 + // Bit X32N_RDE. + RTC_IO_XTAL_32N_PAD_X32N_RDE = 0x10000000 + // Position of X32N_DRV field. + RTC_IO_XTAL_32N_PAD_X32N_DRV_Pos = 0x1d + // Bit mask of X32N_DRV field. + RTC_IO_XTAL_32N_PAD_X32N_DRV_Msk = 0x60000000 + + // PAD_DAC1: configure RTC PAD17 + // Position of PDAC1_DAC field. + RTC_IO_PAD_DAC1_PDAC1_DAC_Pos = 0x3 + // Bit mask of PDAC1_DAC field. + RTC_IO_PAD_DAC1_PDAC1_DAC_Msk = 0x7f8 + // Position of PDAC1_XPD_DAC field. + RTC_IO_PAD_DAC1_PDAC1_XPD_DAC_Pos = 0xb + // Bit mask of PDAC1_XPD_DAC field. + RTC_IO_PAD_DAC1_PDAC1_XPD_DAC_Msk = 0x800 + // Bit PDAC1_XPD_DAC. + RTC_IO_PAD_DAC1_PDAC1_XPD_DAC = 0x800 + // Position of PDAC1_DAC_XPD_FORCE field. + RTC_IO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Pos = 0xc + // Bit mask of PDAC1_DAC_XPD_FORCE field. + RTC_IO_PAD_DAC1_PDAC1_DAC_XPD_FORCE_Msk = 0x1000 + // Bit PDAC1_DAC_XPD_FORCE. + RTC_IO_PAD_DAC1_PDAC1_DAC_XPD_FORCE = 0x1000 + // Position of PDAC1_FUN_IE field. + RTC_IO_PAD_DAC1_PDAC1_FUN_IE_Pos = 0xd + // Bit mask of PDAC1_FUN_IE field. + RTC_IO_PAD_DAC1_PDAC1_FUN_IE_Msk = 0x2000 + // Bit PDAC1_FUN_IE. + RTC_IO_PAD_DAC1_PDAC1_FUN_IE = 0x2000 + // Position of PDAC1_SLP_OE field. + RTC_IO_PAD_DAC1_PDAC1_SLP_OE_Pos = 0xe + // Bit mask of PDAC1_SLP_OE field. + RTC_IO_PAD_DAC1_PDAC1_SLP_OE_Msk = 0x4000 + // Bit PDAC1_SLP_OE. + RTC_IO_PAD_DAC1_PDAC1_SLP_OE = 0x4000 + // Position of PDAC1_SLP_IE field. + RTC_IO_PAD_DAC1_PDAC1_SLP_IE_Pos = 0xf + // Bit mask of PDAC1_SLP_IE field. + RTC_IO_PAD_DAC1_PDAC1_SLP_IE_Msk = 0x8000 + // Bit PDAC1_SLP_IE. + RTC_IO_PAD_DAC1_PDAC1_SLP_IE = 0x8000 + // Position of PDAC1_SLP_SEL field. + RTC_IO_PAD_DAC1_PDAC1_SLP_SEL_Pos = 0x10 + // Bit mask of PDAC1_SLP_SEL field. + RTC_IO_PAD_DAC1_PDAC1_SLP_SEL_Msk = 0x10000 + // Bit PDAC1_SLP_SEL. + RTC_IO_PAD_DAC1_PDAC1_SLP_SEL = 0x10000 + // Position of PDAC1_FUN_SEL field. + RTC_IO_PAD_DAC1_PDAC1_FUN_SEL_Pos = 0x11 + // Bit mask of PDAC1_FUN_SEL field. + RTC_IO_PAD_DAC1_PDAC1_FUN_SEL_Msk = 0x60000 + // Position of PDAC1_MUX_SEL field. + RTC_IO_PAD_DAC1_PDAC1_MUX_SEL_Pos = 0x13 + // Bit mask of PDAC1_MUX_SEL field. + RTC_IO_PAD_DAC1_PDAC1_MUX_SEL_Msk = 0x80000 + // Bit PDAC1_MUX_SEL. + RTC_IO_PAD_DAC1_PDAC1_MUX_SEL = 0x80000 + // Position of PDAC1_RUE field. + RTC_IO_PAD_DAC1_PDAC1_RUE_Pos = 0x1b + // Bit mask of PDAC1_RUE field. + RTC_IO_PAD_DAC1_PDAC1_RUE_Msk = 0x8000000 + // Bit PDAC1_RUE. + RTC_IO_PAD_DAC1_PDAC1_RUE = 0x8000000 + // Position of PDAC1_RDE field. + RTC_IO_PAD_DAC1_PDAC1_RDE_Pos = 0x1c + // Bit mask of PDAC1_RDE field. + RTC_IO_PAD_DAC1_PDAC1_RDE_Msk = 0x10000000 + // Bit PDAC1_RDE. + RTC_IO_PAD_DAC1_PDAC1_RDE = 0x10000000 + // Position of PDAC1_DRV field. + RTC_IO_PAD_DAC1_PDAC1_DRV_Pos = 0x1d + // Bit mask of PDAC1_DRV field. + RTC_IO_PAD_DAC1_PDAC1_DRV_Msk = 0x60000000 + + // PAD_DAC2: configure RTC PAD18 + // Position of PDAC2_DAC field. + RTC_IO_PAD_DAC2_PDAC2_DAC_Pos = 0x3 + // Bit mask of PDAC2_DAC field. + RTC_IO_PAD_DAC2_PDAC2_DAC_Msk = 0x7f8 + // Position of PDAC2_XPD_DAC field. + RTC_IO_PAD_DAC2_PDAC2_XPD_DAC_Pos = 0xb + // Bit mask of PDAC2_XPD_DAC field. + RTC_IO_PAD_DAC2_PDAC2_XPD_DAC_Msk = 0x800 + // Bit PDAC2_XPD_DAC. + RTC_IO_PAD_DAC2_PDAC2_XPD_DAC = 0x800 + // Position of PDAC2_DAC_XPD_FORCE field. + RTC_IO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Pos = 0xc + // Bit mask of PDAC2_DAC_XPD_FORCE field. + RTC_IO_PAD_DAC2_PDAC2_DAC_XPD_FORCE_Msk = 0x1000 + // Bit PDAC2_DAC_XPD_FORCE. + RTC_IO_PAD_DAC2_PDAC2_DAC_XPD_FORCE = 0x1000 + // Position of PDAC2_FUN_IE field. + RTC_IO_PAD_DAC2_PDAC2_FUN_IE_Pos = 0xd + // Bit mask of PDAC2_FUN_IE field. + RTC_IO_PAD_DAC2_PDAC2_FUN_IE_Msk = 0x2000 + // Bit PDAC2_FUN_IE. + RTC_IO_PAD_DAC2_PDAC2_FUN_IE = 0x2000 + // Position of PDAC2_SLP_OE field. + RTC_IO_PAD_DAC2_PDAC2_SLP_OE_Pos = 0xe + // Bit mask of PDAC2_SLP_OE field. + RTC_IO_PAD_DAC2_PDAC2_SLP_OE_Msk = 0x4000 + // Bit PDAC2_SLP_OE. + RTC_IO_PAD_DAC2_PDAC2_SLP_OE = 0x4000 + // Position of PDAC2_SLP_IE field. + RTC_IO_PAD_DAC2_PDAC2_SLP_IE_Pos = 0xf + // Bit mask of PDAC2_SLP_IE field. + RTC_IO_PAD_DAC2_PDAC2_SLP_IE_Msk = 0x8000 + // Bit PDAC2_SLP_IE. + RTC_IO_PAD_DAC2_PDAC2_SLP_IE = 0x8000 + // Position of PDAC2_SLP_SEL field. + RTC_IO_PAD_DAC2_PDAC2_SLP_SEL_Pos = 0x10 + // Bit mask of PDAC2_SLP_SEL field. + RTC_IO_PAD_DAC2_PDAC2_SLP_SEL_Msk = 0x10000 + // Bit PDAC2_SLP_SEL. + RTC_IO_PAD_DAC2_PDAC2_SLP_SEL = 0x10000 + // Position of PDAC2_FUN_SEL field. + RTC_IO_PAD_DAC2_PDAC2_FUN_SEL_Pos = 0x11 + // Bit mask of PDAC2_FUN_SEL field. + RTC_IO_PAD_DAC2_PDAC2_FUN_SEL_Msk = 0x60000 + // Position of PDAC2_MUX_SEL field. + RTC_IO_PAD_DAC2_PDAC2_MUX_SEL_Pos = 0x13 + // Bit mask of PDAC2_MUX_SEL field. + RTC_IO_PAD_DAC2_PDAC2_MUX_SEL_Msk = 0x80000 + // Bit PDAC2_MUX_SEL. + RTC_IO_PAD_DAC2_PDAC2_MUX_SEL = 0x80000 + // Position of PDAC2_RUE field. + RTC_IO_PAD_DAC2_PDAC2_RUE_Pos = 0x1b + // Bit mask of PDAC2_RUE field. + RTC_IO_PAD_DAC2_PDAC2_RUE_Msk = 0x8000000 + // Bit PDAC2_RUE. + RTC_IO_PAD_DAC2_PDAC2_RUE = 0x8000000 + // Position of PDAC2_RDE field. + RTC_IO_PAD_DAC2_PDAC2_RDE_Pos = 0x1c + // Bit mask of PDAC2_RDE field. + RTC_IO_PAD_DAC2_PDAC2_RDE_Msk = 0x10000000 + // Bit PDAC2_RDE. + RTC_IO_PAD_DAC2_PDAC2_RDE = 0x10000000 + // Position of PDAC2_DRV field. + RTC_IO_PAD_DAC2_PDAC2_DRV_Pos = 0x1d + // Bit mask of PDAC2_DRV field. + RTC_IO_PAD_DAC2_PDAC2_DRV_Msk = 0x60000000 + + // RTC_PAD19: configure RTC PAD19 + // Position of FUN_IE field. + RTC_IO_RTC_PAD19_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_RTC_PAD19_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_RTC_PAD19_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_RTC_PAD19_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_RTC_PAD19_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_RTC_PAD19_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_RTC_PAD19_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_RTC_PAD19_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_RTC_PAD19_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_RTC_PAD19_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_RTC_PAD19_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_RTC_PAD19_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_RTC_PAD19_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_RTC_PAD19_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_RTC_PAD19_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_RTC_PAD19_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_RTC_PAD19_MUX_SEL = 0x80000 + // Position of RUE field. + RTC_IO_RTC_PAD19_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_RTC_PAD19_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_RTC_PAD19_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_RTC_PAD19_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_RTC_PAD19_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_RTC_PAD19_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_RTC_PAD19_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_RTC_PAD19_DRV_Msk = 0x60000000 + + // RTC_PAD20: configure RTC PAD20 + // Position of FUN_IE field. + RTC_IO_RTC_PAD20_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_RTC_PAD20_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_RTC_PAD20_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_RTC_PAD20_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_RTC_PAD20_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_RTC_PAD20_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_RTC_PAD20_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_RTC_PAD20_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_RTC_PAD20_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_RTC_PAD20_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_RTC_PAD20_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_RTC_PAD20_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_RTC_PAD20_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_RTC_PAD20_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_RTC_PAD20_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_RTC_PAD20_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_RTC_PAD20_MUX_SEL = 0x80000 + // Position of RUE field. + RTC_IO_RTC_PAD20_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_RTC_PAD20_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_RTC_PAD20_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_RTC_PAD20_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_RTC_PAD20_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_RTC_PAD20_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_RTC_PAD20_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_RTC_PAD20_DRV_Msk = 0x60000000 + + // RTC_PAD21: configure RTC PAD21 + // Position of FUN_IE field. + RTC_IO_RTC_PAD21_FUN_IE_Pos = 0xd + // Bit mask of FUN_IE field. + RTC_IO_RTC_PAD21_FUN_IE_Msk = 0x2000 + // Bit FUN_IE. + RTC_IO_RTC_PAD21_FUN_IE = 0x2000 + // Position of SLP_OE field. + RTC_IO_RTC_PAD21_SLP_OE_Pos = 0xe + // Bit mask of SLP_OE field. + RTC_IO_RTC_PAD21_SLP_OE_Msk = 0x4000 + // Bit SLP_OE. + RTC_IO_RTC_PAD21_SLP_OE = 0x4000 + // Position of SLP_IE field. + RTC_IO_RTC_PAD21_SLP_IE_Pos = 0xf + // Bit mask of SLP_IE field. + RTC_IO_RTC_PAD21_SLP_IE_Msk = 0x8000 + // Bit SLP_IE. + RTC_IO_RTC_PAD21_SLP_IE = 0x8000 + // Position of SLP_SEL field. + RTC_IO_RTC_PAD21_SLP_SEL_Pos = 0x10 + // Bit mask of SLP_SEL field. + RTC_IO_RTC_PAD21_SLP_SEL_Msk = 0x10000 + // Bit SLP_SEL. + RTC_IO_RTC_PAD21_SLP_SEL = 0x10000 + // Position of FUN_SEL field. + RTC_IO_RTC_PAD21_FUN_SEL_Pos = 0x11 + // Bit mask of FUN_SEL field. + RTC_IO_RTC_PAD21_FUN_SEL_Msk = 0x60000 + // Position of MUX_SEL field. + RTC_IO_RTC_PAD21_MUX_SEL_Pos = 0x13 + // Bit mask of MUX_SEL field. + RTC_IO_RTC_PAD21_MUX_SEL_Msk = 0x80000 + // Bit MUX_SEL. + RTC_IO_RTC_PAD21_MUX_SEL = 0x80000 + // Position of RUE field. + RTC_IO_RTC_PAD21_RUE_Pos = 0x1b + // Bit mask of RUE field. + RTC_IO_RTC_PAD21_RUE_Msk = 0x8000000 + // Bit RUE. + RTC_IO_RTC_PAD21_RUE = 0x8000000 + // Position of RDE field. + RTC_IO_RTC_PAD21_RDE_Pos = 0x1c + // Bit mask of RDE field. + RTC_IO_RTC_PAD21_RDE_Msk = 0x10000000 + // Bit RDE. + RTC_IO_RTC_PAD21_RDE = 0x10000000 + // Position of DRV field. + RTC_IO_RTC_PAD21_DRV_Pos = 0x1d + // Bit mask of DRV field. + RTC_IO_RTC_PAD21_DRV_Msk = 0x60000000 + + // EXT_WAKEUP0: configure EXT0 wakeup + // Position of SEL field. + RTC_IO_EXT_WAKEUP0_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTC_IO_EXT_WAKEUP0_SEL_Msk = 0xf8000000 + + // XTL_EXT_CTR: configure gpio pd XTAL + // Position of SEL field. + RTC_IO_XTL_EXT_CTR_SEL_Pos = 0x1b + // Bit mask of SEL field. + RTC_IO_XTL_EXT_CTR_SEL_Msk = 0xf8000000 + + // SAR_I2C_IO: configure rtc i2c mux + // Position of SAR_DEBUG_BIT_SEL field. + RTC_IO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Pos = 0x17 + // Bit mask of SAR_DEBUG_BIT_SEL field. + RTC_IO_SAR_I2C_IO_SAR_DEBUG_BIT_SEL_Msk = 0xf800000 + // Position of SAR_I2C_SCL_SEL field. + RTC_IO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Pos = 0x1c + // Bit mask of SAR_I2C_SCL_SEL field. + RTC_IO_SAR_I2C_IO_SAR_I2C_SCL_SEL_Msk = 0x30000000 + // Position of SAR_I2C_SDA_SEL field. + RTC_IO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Pos = 0x1e + // Bit mask of SAR_I2C_SDA_SEL field. + RTC_IO_SAR_I2C_IO_SAR_I2C_SDA_SEL_Msk = 0xc0000000 + + // TOUCH_CTRL: configure touch pad bufmode + // Position of IO_TOUCH_BUFSEL field. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL_Pos = 0x0 + // Bit mask of IO_TOUCH_BUFSEL field. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFSEL_Msk = 0xf + // Position of IO_TOUCH_BUFMODE field. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE_Pos = 0x4 + // Bit mask of IO_TOUCH_BUFMODE field. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE_Msk = 0x10 + // Bit IO_TOUCH_BUFMODE. + RTC_IO_TOUCH_CTRL_IO_TOUCH_BUFMODE = 0x10 + + // DATE: version + // Position of DATE field. + RTC_IO_DATE_DATE_Pos = 0x0 + // Bit mask of DATE field. + RTC_IO_DATE_DATE_Msk = 0xfffffff +) + +// Constants for SENS: SENS Peripheral +const ( + // SAR_SLAVE_ADDR1: configure i2c slave address + // Position of SAR_I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR1_Pos = 0x0 + // Bit mask of SAR_I2C_SLAVE_ADDR1 field. + SENS_SAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR1_Msk = 0x7ff + // Position of SAR_I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR0_Pos = 0xb + // Bit mask of SAR_I2C_SLAVE_ADDR0 field. + SENS_SAR_SLAVE_ADDR1_SAR_I2C_SLAVE_ADDR0_Msk = 0x3ff800 + // Position of SAR_SARADC_MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_SAR_SARADC_MEAS_STATUS_Pos = 0x16 + // Bit mask of SAR_SARADC_MEAS_STATUS field. + SENS_SAR_SLAVE_ADDR1_SAR_SARADC_MEAS_STATUS_Msk = 0x3fc00000 + + // SAR_SLAVE_ADDR2: configure i2c slave address + // Position of SAR_I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR3_Pos = 0x0 + // Bit mask of SAR_I2C_SLAVE_ADDR3 field. + SENS_SAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR3_Msk = 0x7ff + // Position of SAR_I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR2_Pos = 0xb + // Bit mask of SAR_I2C_SLAVE_ADDR2 field. + SENS_SAR_SLAVE_ADDR2_SAR_I2C_SLAVE_ADDR2_Msk = 0x3ff800 + + // SAR_SLAVE_ADDR3: configure i2c slave address + // Position of SAR_I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR5_Pos = 0x0 + // Bit mask of SAR_I2C_SLAVE_ADDR5 field. + SENS_SAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR5_Msk = 0x7ff + // Position of SAR_I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR4_Pos = 0xb + // Bit mask of SAR_I2C_SLAVE_ADDR4 field. + SENS_SAR_SLAVE_ADDR3_SAR_I2C_SLAVE_ADDR4_Msk = 0x3ff800 + + // SAR_SLAVE_ADDR4: configure i2c slave address + // Position of SAR_I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR7_Pos = 0x0 + // Bit mask of SAR_I2C_SLAVE_ADDR7 field. + SENS_SAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR7_Msk = 0x7ff + // Position of SAR_I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR6_Pos = 0xb + // Bit mask of SAR_I2C_SLAVE_ADDR6 field. + SENS_SAR_SLAVE_ADDR4_SAR_I2C_SLAVE_ADDR6_Msk = 0x3ff800 + + // SAR_I2C_CTRL: configure rtc i2c controller by sw + // Position of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Pos = 0x0 + // Bit mask of SAR_I2C_CTRL field. + SENS_SAR_I2C_CTRL_SAR_I2C_CTRL_Msk = 0xfffffff + // Position of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Pos = 0x1c + // Bit mask of SAR_I2C_START field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_Msk = 0x10000000 + // Bit SAR_I2C_START. + SENS_SAR_I2C_CTRL_SAR_I2C_START = 0x10000000 + // Position of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Pos = 0x1d + // Bit mask of SAR_I2C_START_FORCE field. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE_Msk = 0x20000000 + // Bit SAR_I2C_START_FORCE. + SENS_SAR_I2C_CTRL_SAR_I2C_START_FORCE = 0x20000000 + + // SAR_COCPU_INT_RAW: the interrupt raw of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_DONE_INT_RAW = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_INACTIVE_INT_RAW = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_ACTIVE_INT_RAW = 0x4 + // Position of SAR_COCPU_SARADC1_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC1_INT_RAW = 0x8 + // Position of SAR_COCPU_SARADC2_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SARADC2_INT_RAW = 0x10 + // Position of SAR_COCPU_TSENS_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TSENS_INT_RAW = 0x20 + // Position of SAR_COCPU_START_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW_Msk = 0x40 + // Bit SAR_COCPU_START_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_START_INT_RAW = 0x40 + // Position of SAR_COCPU_SW_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SW_INT_RAW = 0x80 + // Position of SAR_COCPU_SWD_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_SWD_INT_RAW = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_TIMEOUT_INT_RAW = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW field. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW. + SENS_SAR_COCPU_INT_RAW_SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW = 0x800 + + // SAR_COCPU_INT_ENA: the interrupt enable of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_DONE_INT_ENA = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_INACTIVE_INT_ENA = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_ACTIVE_INT_ENA = 0x4 + // Position of SAR_COCPU_SARADC1_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC1_INT_ENA = 0x8 + // Position of SAR_COCPU_SARADC2_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SARADC2_INT_ENA = 0x10 + // Position of SAR_COCPU_TSENS_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TSENS_INT_ENA = 0x20 + // Position of SAR_COCPU_START_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA_Msk = 0x40 + // Bit SAR_COCPU_START_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_START_INT_ENA = 0x40 + // Position of SAR_COCPU_SW_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SW_INT_ENA = 0x80 + // Position of SAR_COCPU_SWD_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_SWD_INT_ENA = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_TIMEOUT_INT_ENA = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA field. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA. + SENS_SAR_COCPU_INT_ENA_SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA = 0x800 + + // SAR_COCPU_INT_ST: the interrupt state of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_DONE_INT_ST = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_INACTIVE_INT_ST = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_ACTIVE_INT_ST = 0x4 + // Position of SAR_COCPU_SARADC1_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC1_INT_ST = 0x8 + // Position of SAR_COCPU_SARADC2_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SARADC2_INT_ST = 0x10 + // Position of SAR_COCPU_TSENS_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TSENS_INT_ST = 0x20 + // Position of SAR_COCPU_START_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST_Msk = 0x40 + // Bit SAR_COCPU_START_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_START_INT_ST = 0x40 + // Position of SAR_COCPU_SW_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SW_INT_ST = 0x80 + // Position of SAR_COCPU_SWD_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_SWD_INT_ST = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_TIMEOUT_INT_ST = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_ST field. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_ST. + SENS_SAR_COCPU_INT_ST_SAR_COCPU_TOUCH_SCAN_DONE_INT_ST = 0x800 + + // SAR_COCPU_INT_CLR: the interrupt clear of ulp + // Position of SAR_COCPU_TOUCH_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR_Pos = 0x0 + // Bit mask of SAR_COCPU_TOUCH_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR_Msk = 0x1 + // Bit SAR_COCPU_TOUCH_DONE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_DONE_INT_CLR = 0x1 + // Position of SAR_COCPU_TOUCH_INACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR_Pos = 0x1 + // Bit mask of SAR_COCPU_TOUCH_INACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR_Msk = 0x2 + // Bit SAR_COCPU_TOUCH_INACTIVE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_INACTIVE_INT_CLR = 0x2 + // Position of SAR_COCPU_TOUCH_ACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR_Pos = 0x2 + // Bit mask of SAR_COCPU_TOUCH_ACTIVE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR_Msk = 0x4 + // Bit SAR_COCPU_TOUCH_ACTIVE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_ACTIVE_INT_CLR = 0x4 + // Position of SAR_COCPU_SARADC1_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR_Pos = 0x3 + // Bit mask of SAR_COCPU_SARADC1_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR_Msk = 0x8 + // Bit SAR_COCPU_SARADC1_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC1_INT_CLR = 0x8 + // Position of SAR_COCPU_SARADC2_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR_Pos = 0x4 + // Bit mask of SAR_COCPU_SARADC2_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR_Msk = 0x10 + // Bit SAR_COCPU_SARADC2_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SARADC2_INT_CLR = 0x10 + // Position of SAR_COCPU_TSENS_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR_Pos = 0x5 + // Bit mask of SAR_COCPU_TSENS_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR_Msk = 0x20 + // Bit SAR_COCPU_TSENS_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TSENS_INT_CLR = 0x20 + // Position of SAR_COCPU_START_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR_Pos = 0x6 + // Bit mask of SAR_COCPU_START_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR_Msk = 0x40 + // Bit SAR_COCPU_START_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_START_INT_CLR = 0x40 + // Position of SAR_COCPU_SW_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR_Pos = 0x7 + // Bit mask of SAR_COCPU_SW_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR_Msk = 0x80 + // Bit SAR_COCPU_SW_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SW_INT_CLR = 0x80 + // Position of SAR_COCPU_SWD_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR_Pos = 0x8 + // Bit mask of SAR_COCPU_SWD_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR_Msk = 0x100 + // Bit SAR_COCPU_SWD_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_SWD_INT_CLR = 0x100 + // Position of SAR_COCPU_TOUCH_TIMEOUT_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR_Pos = 0x9 + // Bit mask of SAR_COCPU_TOUCH_TIMEOUT_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR_Msk = 0x200 + // Bit SAR_COCPU_TOUCH_TIMEOUT_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_TIMEOUT_INT_CLR = 0x200 + // Position of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_Pos = 0xa + // Bit mask of SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_Msk = 0x400 + // Bit SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR = 0x400 + // Position of SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR_Pos = 0xb + // Bit mask of SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR field. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR_Msk = 0x800 + // Bit SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR. + SENS_SAR_COCPU_INT_CLR_SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR = 0x800 +) diff --git a/emb/device/esp/esp8266.S b/emb/device/esp/esp8266.S new file mode 100644 index 0000000..cffa503 --- /dev/null +++ b/emb/device/esp/esp8266.S @@ -0,0 +1,6 @@ + +.section .text.tinygo_scanCurrentStack +.global tinygo_scanCurrentStack +tinygo_scanCurrentStack: + // TODO: save callee saved registers on the stack + j tinygo_scanstack diff --git a/emb/device/esp/esp8266.go b/emb/device/esp/esp8266.go new file mode 100644 index 0000000..d07a842 --- /dev/null +++ b/emb/device/esp/esp8266.go @@ -0,0 +1,10874 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device-svd.go from esp8266.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif-Community + +//go:build esp && esp8266 + +/* + + */ + +package esp + +import ( + "runtime/volatile" + "unsafe" +) + +// Some information about this device. +const ( + Device = "esp8266" + CPU = "Xtensa LX106" + FPUPresent = true + NVICPrioBits = 3 +) + +// Interrupt numbers. +const ( + // Highest interrupt number on this device. + IRQ_max = 0 +) + +// Pseudo function call that is replaced by the compiler with the actual +// functions registered through interrupt.New. +// +//go:linkname callHandlers runtime/interrupt.callHandlers +func callHandlers(num int) +func HandleInterrupt(num int) { + switch num { + } +} + +// Peripherals. +var ( + DPORT = (*DPORT_Type)(unsafe.Pointer(uintptr(0x3ff00000))) + + EFUSE = (*EFUSE_Type)(unsafe.Pointer(uintptr(0x3ff00050))) + + GPIO = (*GPIO_Type)(unsafe.Pointer(uintptr(0x60000300))) + + I2S = (*I2S_Type)(unsafe.Pointer(uintptr(0x60000e00))) + + IO_MUX = (*IO_MUX_Type)(unsafe.Pointer(uintptr(0x60000800))) + + RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x60000700))) + + SLC = (*SLC_Type)(unsafe.Pointer(uintptr(0x60000b00))) + + SPI0 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x60000200))) + + SPI1 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x60000100))) + + TIMER = (*TIMER_Type)(unsafe.Pointer(uintptr(0x60000600))) + + UART0 = (*UART0_Type)(unsafe.Pointer(uintptr(0x60000000))) + + UART1 = (*UART1_Type)(unsafe.Pointer(uintptr(0x60000f00))) + + WDT = (*WDT_Type)(unsafe.Pointer(uintptr(0x60000900))) + + // RNG register + RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x3ff20e44))) + + // Watchdog registers + WATCHDOG = (*WATCHDOG_Type)(unsafe.Pointer(uintptr(0x60000900))) +) + +type DPORT_Type struct { + _ [4]byte + EDGE_INT_ENABLE volatile.Register32 // 0x4 + _ [12]byte + DPORT_CTL volatile.Register32 // 0x14 +} + +// DPORT.EDGE_INT_ENABLE: EDGE_INT_ENABLE +func (o *DPORT_Type) SetEDGE_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.EDGE_INT_ENABLE.Reg, value) +} +func (o *DPORT_Type) GetEDGE_INT_ENABLE() uint32 { + return volatile.LoadUint32(&o.EDGE_INT_ENABLE.Reg) +} +func (o *DPORT_Type) SetEDGE_INT_ENABLE_WDT_EDGE_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.EDGE_INT_ENABLE.Reg, volatile.LoadUint32(&o.EDGE_INT_ENABLE.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetEDGE_INT_ENABLE_WDT_EDGE_INT_ENABLE() uint32 { + return volatile.LoadUint32(&o.EDGE_INT_ENABLE.Reg) & 0x1 +} +func (o *DPORT_Type) SetEDGE_INT_ENABLE_TIMER1_EDGE_INT_ENABLE(value uint32) { + volatile.StoreUint32(&o.EDGE_INT_ENABLE.Reg, volatile.LoadUint32(&o.EDGE_INT_ENABLE.Reg)&^(0x2)|value<<1) +} +func (o *DPORT_Type) GetEDGE_INT_ENABLE_TIMER1_EDGE_INT_ENABLE() uint32 { + return (volatile.LoadUint32(&o.EDGE_INT_ENABLE.Reg) & 0x2) >> 1 +} + +// DPORT.DPORT_CTL: DPORT_CTL +func (o *DPORT_Type) SetDPORT_CTL_DPORT_CTL_DOUBLE_CLK(value uint32) { + volatile.StoreUint32(&o.DPORT_CTL.Reg, volatile.LoadUint32(&o.DPORT_CTL.Reg)&^(0x1)|value) +} +func (o *DPORT_Type) GetDPORT_CTL_DPORT_CTL_DOUBLE_CLK() uint32 { + return volatile.LoadUint32(&o.DPORT_CTL.Reg) & 0x1 +} + +type EFUSE_Type struct { + EFUSE_DATA0 volatile.Register32 // 0x0 + EFUSE_DATA1 volatile.Register32 // 0x4 + EFUSE_DATA2 volatile.Register32 // 0x8 + EFUSE_DATA3 volatile.Register32 // 0xC +} + +// EFUSE.EFUSE_DATA0: EFUSE_DATA0 +func (o *EFUSE_Type) SetEFUSE_DATA0(value uint32) { + volatile.StoreUint32(&o.EFUSE_DATA0.Reg, value) +} +func (o *EFUSE_Type) GetEFUSE_DATA0() uint32 { + return volatile.LoadUint32(&o.EFUSE_DATA0.Reg) +} + +// EFUSE.EFUSE_DATA1: EFUSE_DATA1 +func (o *EFUSE_Type) SetEFUSE_DATA1(value uint32) { + volatile.StoreUint32(&o.EFUSE_DATA1.Reg, value) +} +func (o *EFUSE_Type) GetEFUSE_DATA1() uint32 { + return volatile.LoadUint32(&o.EFUSE_DATA1.Reg) +} + +// EFUSE.EFUSE_DATA2: EFUSE_DATA2 +func (o *EFUSE_Type) SetEFUSE_DATA2(value uint32) { + volatile.StoreUint32(&o.EFUSE_DATA2.Reg, value) +} +func (o *EFUSE_Type) GetEFUSE_DATA2() uint32 { + return volatile.LoadUint32(&o.EFUSE_DATA2.Reg) +} + +// EFUSE.EFUSE_DATA3: EFUSE_DATA3 +func (o *EFUSE_Type) SetEFUSE_DATA3(value uint32) { + volatile.StoreUint32(&o.EFUSE_DATA3.Reg, value) +} +func (o *EFUSE_Type) GetEFUSE_DATA3() uint32 { + return volatile.LoadUint32(&o.EFUSE_DATA3.Reg) +} + +type GPIO_Type struct { + GPIO_OUT volatile.Register32 // 0x0 + GPIO_OUT_W1TS volatile.Register32 // 0x4 + GPIO_OUT_W1TC volatile.Register32 // 0x8 + GPIO_ENABLE volatile.Register32 // 0xC + GPIO_ENABLE_W1TS volatile.Register32 // 0x10 + GPIO_ENABLE_W1TC volatile.Register32 // 0x14 + GPIO_IN volatile.Register32 // 0x18 + GPIO_STATUS volatile.Register32 // 0x1C + GPIO_STATUS_W1TS volatile.Register32 // 0x20 + GPIO_STATUS_W1TC volatile.Register32 // 0x24 + GPIO_PIN0 volatile.Register32 // 0x28 + GPIO_PIN1 volatile.Register32 // 0x2C + GPIO_PIN2 volatile.Register32 // 0x30 + GPIO_PIN3 volatile.Register32 // 0x34 + GPIO_PIN4 volatile.Register32 // 0x38 + GPIO_PIN5 volatile.Register32 // 0x3C + GPIO_PIN6 volatile.Register32 // 0x40 + GPIO_PIN7 volatile.Register32 // 0x44 + GPIO_PIN8 volatile.Register32 // 0x48 + GPIO_PIN9 volatile.Register32 // 0x4C + GPIO_PIN10 volatile.Register32 // 0x50 + GPIO_PIN11 volatile.Register32 // 0x54 + GPIO_PIN12 volatile.Register32 // 0x58 + GPIO_PIN13 volatile.Register32 // 0x5C + GPIO_PIN14 volatile.Register32 // 0x60 + GPIO_PIN15 volatile.Register32 // 0x64 + GPIO_SIGMA_DELTA volatile.Register32 // 0x68 + GPIO_RTC_CALIB_SYNC volatile.Register32 // 0x6C + GPIO_RTC_CALIB_VALUE volatile.Register32 // 0x70 +} + +// GPIO.GPIO_OUT: BT-Coexist Selection register +func (o *GPIO_Type) SetGPIO_OUT_GPIO_BT_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO_OUT.Reg, volatile.LoadUint32(&o.GPIO_OUT.Reg)&^(0xffff0000)|value<<16) +} +func (o *GPIO_Type) GetGPIO_OUT_GPIO_BT_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO_OUT.Reg) & 0xffff0000) >> 16 +} +func (o *GPIO_Type) SetGPIO_OUT_GPIO_OUT_DATA(value uint32) { + volatile.StoreUint32(&o.GPIO_OUT.Reg, volatile.LoadUint32(&o.GPIO_OUT.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_OUT_GPIO_OUT_DATA() uint32 { + return volatile.LoadUint32(&o.GPIO_OUT.Reg) & 0xffff +} + +// GPIO.GPIO_OUT_W1TS: GPIO_OUT_W1TS +func (o *GPIO_Type) SetGPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.GPIO_OUT_W1TS.Reg, volatile.LoadUint32(&o.GPIO_OUT_W1TS.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS() uint32 { + return volatile.LoadUint32(&o.GPIO_OUT_W1TS.Reg) & 0xffff +} + +// GPIO.GPIO_OUT_W1TC: GPIO_OUT_W1TC +func (o *GPIO_Type) SetGPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.GPIO_OUT_W1TC.Reg, volatile.LoadUint32(&o.GPIO_OUT_W1TC.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC() uint32 { + return volatile.LoadUint32(&o.GPIO_OUT_W1TC.Reg) & 0xffff +} + +// GPIO.GPIO_ENABLE: GPIO_ENABLE +func (o *GPIO_Type) SetGPIO_ENABLE_GPIO_SDIO_SEL(value uint32) { + volatile.StoreUint32(&o.GPIO_ENABLE.Reg, volatile.LoadUint32(&o.GPIO_ENABLE.Reg)&^(0x3f0000)|value<<16) +} +func (o *GPIO_Type) GetGPIO_ENABLE_GPIO_SDIO_SEL() uint32 { + return (volatile.LoadUint32(&o.GPIO_ENABLE.Reg) & 0x3f0000) >> 16 +} +func (o *GPIO_Type) SetGPIO_ENABLE_GPIO_ENABLE_DATA(value uint32) { + volatile.StoreUint32(&o.GPIO_ENABLE.Reg, volatile.LoadUint32(&o.GPIO_ENABLE.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_ENABLE_GPIO_ENABLE_DATA() uint32 { + return volatile.LoadUint32(&o.GPIO_ENABLE.Reg) & 0xffff +} + +// GPIO.GPIO_ENABLE_W1TS: GPIO_ENABLE_W1TS +func (o *GPIO_Type) SetGPIO_ENABLE_W1TS_GPIO_ENABLE_DATA_W1TS(value uint32) { + volatile.StoreUint32(&o.GPIO_ENABLE_W1TS.Reg, volatile.LoadUint32(&o.GPIO_ENABLE_W1TS.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_ENABLE_W1TS_GPIO_ENABLE_DATA_W1TS() uint32 { + return volatile.LoadUint32(&o.GPIO_ENABLE_W1TS.Reg) & 0xffff +} + +// GPIO.GPIO_ENABLE_W1TC: GPIO_ENABLE_W1TC +func (o *GPIO_Type) SetGPIO_ENABLE_W1TC_GPIO_ENABLE_DATA_W1TC(value uint32) { + volatile.StoreUint32(&o.GPIO_ENABLE_W1TC.Reg, volatile.LoadUint32(&o.GPIO_ENABLE_W1TC.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_ENABLE_W1TC_GPIO_ENABLE_DATA_W1TC() uint32 { + return volatile.LoadUint32(&o.GPIO_ENABLE_W1TC.Reg) & 0xffff +} + +// GPIO.GPIO_IN: The values of the strapping pins. +func (o *GPIO_Type) SetGPIO_IN_GPIO_STRAPPING(value uint32) { + volatile.StoreUint32(&o.GPIO_IN.Reg, volatile.LoadUint32(&o.GPIO_IN.Reg)&^(0xffff0000)|value<<16) +} +func (o *GPIO_Type) GetGPIO_IN_GPIO_STRAPPING() uint32 { + return (volatile.LoadUint32(&o.GPIO_IN.Reg) & 0xffff0000) >> 16 +} +func (o *GPIO_Type) SetGPIO_IN_GPIO_IN_DATA(value uint32) { + volatile.StoreUint32(&o.GPIO_IN.Reg, volatile.LoadUint32(&o.GPIO_IN.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_IN_GPIO_IN_DATA() uint32 { + return volatile.LoadUint32(&o.GPIO_IN.Reg) & 0xffff +} + +// GPIO.GPIO_STATUS: GPIO_STATUS +func (o *GPIO_Type) SetGPIO_STATUS_GPIO_STATUS_INTERRUPT(value uint32) { + volatile.StoreUint32(&o.GPIO_STATUS.Reg, volatile.LoadUint32(&o.GPIO_STATUS.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_STATUS_GPIO_STATUS_INTERRUPT() uint32 { + return volatile.LoadUint32(&o.GPIO_STATUS.Reg) & 0xffff +} + +// GPIO.GPIO_STATUS_W1TS: GPIO_STATUS_W1TS +func (o *GPIO_Type) SetGPIO_STATUS_W1TS_GPIO_STATUS_INTERRUPT_W1TS(value uint32) { + volatile.StoreUint32(&o.GPIO_STATUS_W1TS.Reg, volatile.LoadUint32(&o.GPIO_STATUS_W1TS.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_STATUS_W1TS_GPIO_STATUS_INTERRUPT_W1TS() uint32 { + return volatile.LoadUint32(&o.GPIO_STATUS_W1TS.Reg) & 0xffff +} + +// GPIO.GPIO_STATUS_W1TC: GPIO_STATUS_W1TC +func (o *GPIO_Type) SetGPIO_STATUS_W1TC_GPIO_STATUS_INTERRUPT_W1TC(value uint32) { + volatile.StoreUint32(&o.GPIO_STATUS_W1TC.Reg, volatile.LoadUint32(&o.GPIO_STATUS_W1TC.Reg)&^(0xffff)|value) +} +func (o *GPIO_Type) GetGPIO_STATUS_W1TC_GPIO_STATUS_INTERRUPT_W1TC() uint32 { + return volatile.LoadUint32(&o.GPIO_STATUS_W1TC.Reg) & 0xffff +} + +// GPIO.GPIO_PIN0: GPIO_PIN0 +func (o *GPIO_Type) SetGPIO_PIN0_GPIO_PIN0_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN0.Reg, volatile.LoadUint32(&o.GPIO_PIN0.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN0_GPIO_PIN0_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN0.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN0_GPIO_PIN0_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN0.Reg, volatile.LoadUint32(&o.GPIO_PIN0.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN0_GPIO_PIN0_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN0.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN0_GPIO_PIN0_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN0.Reg, volatile.LoadUint32(&o.GPIO_PIN0.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN0_GPIO_PIN0_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN0.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN0_GPIO_PIN0_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN0.Reg, volatile.LoadUint32(&o.GPIO_PIN0.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN0_GPIO_PIN0_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN0.Reg) & 0x1 +} + +// GPIO.GPIO_PIN1: GPIO_PIN1 +func (o *GPIO_Type) SetGPIO_PIN1_GPIO_PIN1_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN1.Reg, volatile.LoadUint32(&o.GPIO_PIN1.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN1_GPIO_PIN1_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN1.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN1_GPIO_PIN1_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN1.Reg, volatile.LoadUint32(&o.GPIO_PIN1.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN1_GPIO_PIN1_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN1.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN1_GPIO_PIN1_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN1.Reg, volatile.LoadUint32(&o.GPIO_PIN1.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN1_GPIO_PIN1_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN1.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN1_GPIO_PIN1_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN1.Reg, volatile.LoadUint32(&o.GPIO_PIN1.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN1_GPIO_PIN1_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN1.Reg) & 0x1 +} + +// GPIO.GPIO_PIN2: GPIO_PIN2 +func (o *GPIO_Type) SetGPIO_PIN2_GPIO_PIN2_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN2.Reg, volatile.LoadUint32(&o.GPIO_PIN2.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN2_GPIO_PIN2_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN2.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN2_GPIO_PIN2_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN2.Reg, volatile.LoadUint32(&o.GPIO_PIN2.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN2_GPIO_PIN2_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN2.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN2_GPIO_PIN2_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN2.Reg, volatile.LoadUint32(&o.GPIO_PIN2.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN2_GPIO_PIN2_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN2.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN2_GPIO_PIN2_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN2.Reg, volatile.LoadUint32(&o.GPIO_PIN2.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN2_GPIO_PIN2_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN2.Reg) & 0x1 +} + +// GPIO.GPIO_PIN3: GPIO_PIN3 +func (o *GPIO_Type) SetGPIO_PIN3_GPIO_PIN3_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN3.Reg, volatile.LoadUint32(&o.GPIO_PIN3.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN3_GPIO_PIN3_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN3.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN3_GPIO_PIN3_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN3.Reg, volatile.LoadUint32(&o.GPIO_PIN3.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN3_GPIO_PIN3_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN3.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN3_GPIO_PIN3_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN3.Reg, volatile.LoadUint32(&o.GPIO_PIN3.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN3_GPIO_PIN3_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN3.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN3_GPIO_PIN3_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN3.Reg, volatile.LoadUint32(&o.GPIO_PIN3.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN3_GPIO_PIN3_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN3.Reg) & 0x1 +} + +// GPIO.GPIO_PIN4: GPIO_PIN4 +func (o *GPIO_Type) SetGPIO_PIN4_GPIO_PIN4_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN4.Reg, volatile.LoadUint32(&o.GPIO_PIN4.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN4_GPIO_PIN4_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN4.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN4_GPIO_PIN4_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN4.Reg, volatile.LoadUint32(&o.GPIO_PIN4.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN4_GPIO_PIN4_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN4.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN4_GPIO_PIN4_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN4.Reg, volatile.LoadUint32(&o.GPIO_PIN4.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN4_GPIO_PIN4_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN4.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN4_GPIO_PIN4_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN4.Reg, volatile.LoadUint32(&o.GPIO_PIN4.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN4_GPIO_PIN4_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN4.Reg) & 0x1 +} + +// GPIO.GPIO_PIN5: GPIO_PIN5 +func (o *GPIO_Type) SetGPIO_PIN5_GPIO_PIN5_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN5.Reg, volatile.LoadUint32(&o.GPIO_PIN5.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN5_GPIO_PIN5_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN5.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN5_GPIO_PIN5_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN5.Reg, volatile.LoadUint32(&o.GPIO_PIN5.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN5_GPIO_PIN5_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN5.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN5_GPIO_PIN5_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN5.Reg, volatile.LoadUint32(&o.GPIO_PIN5.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN5_GPIO_PIN5_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN5.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN5_GPIO_PIN5_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN5.Reg, volatile.LoadUint32(&o.GPIO_PIN5.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN5_GPIO_PIN5_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN5.Reg) & 0x1 +} + +// GPIO.GPIO_PIN6: GPIO_PIN6 +func (o *GPIO_Type) SetGPIO_PIN6_GPIO_PIN6_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN6.Reg, volatile.LoadUint32(&o.GPIO_PIN6.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN6_GPIO_PIN6_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN6.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN6_GPIO_PIN6_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN6.Reg, volatile.LoadUint32(&o.GPIO_PIN6.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN6_GPIO_PIN6_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN6.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN6_GPIO_PIN6_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN6.Reg, volatile.LoadUint32(&o.GPIO_PIN6.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN6_GPIO_PIN6_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN6.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN6_GPIO_PIN6_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN6.Reg, volatile.LoadUint32(&o.GPIO_PIN6.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN6_GPIO_PIN6_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN6.Reg) & 0x1 +} + +// GPIO.GPIO_PIN7: GPIO_PIN7 +func (o *GPIO_Type) SetGPIO_PIN7_GPIO_PIN7_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN7.Reg, volatile.LoadUint32(&o.GPIO_PIN7.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN7_GPIO_PIN7_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN7.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN7_GPIO_PIN7_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN7.Reg, volatile.LoadUint32(&o.GPIO_PIN7.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN7_GPIO_PIN7_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN7.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN7_GPIO_PIN7_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN7.Reg, volatile.LoadUint32(&o.GPIO_PIN7.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN7_GPIO_PIN7_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN7.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN7_GPIO_PIN7_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN7.Reg, volatile.LoadUint32(&o.GPIO_PIN7.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN7_GPIO_PIN7_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN7.Reg) & 0x1 +} + +// GPIO.GPIO_PIN8: GPIO_PIN8 +func (o *GPIO_Type) SetGPIO_PIN8_GPIO_PIN8_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN8.Reg, volatile.LoadUint32(&o.GPIO_PIN8.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN8_GPIO_PIN8_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN8.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN8_GPIO_PIN8_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN8.Reg, volatile.LoadUint32(&o.GPIO_PIN8.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN8_GPIO_PIN8_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN8.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN8_GPIO_PIN8_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN8.Reg, volatile.LoadUint32(&o.GPIO_PIN8.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN8_GPIO_PIN8_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN8.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN8_GPIO_PIN8_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN8.Reg, volatile.LoadUint32(&o.GPIO_PIN8.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN8_GPIO_PIN8_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN8.Reg) & 0x1 +} + +// GPIO.GPIO_PIN9: GPIO_PIN9 +func (o *GPIO_Type) SetGPIO_PIN9_GPIO_PIN9_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN9.Reg, volatile.LoadUint32(&o.GPIO_PIN9.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN9_GPIO_PIN9_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN9.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN9_GPIO_PIN9_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN9.Reg, volatile.LoadUint32(&o.GPIO_PIN9.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN9_GPIO_PIN9_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN9.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN9_GPIO_PIN9_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN9.Reg, volatile.LoadUint32(&o.GPIO_PIN9.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN9_GPIO_PIN9_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN9.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN9_GPIO_PIN9_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN9.Reg, volatile.LoadUint32(&o.GPIO_PIN9.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN9_GPIO_PIN9_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN9.Reg) & 0x1 +} + +// GPIO.GPIO_PIN10: GPIO_PIN10 +func (o *GPIO_Type) SetGPIO_PIN10_GPIO_PIN10_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN10.Reg, volatile.LoadUint32(&o.GPIO_PIN10.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN10_GPIO_PIN10_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN10.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN10_GPIO_PIN10_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN10.Reg, volatile.LoadUint32(&o.GPIO_PIN10.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN10_GPIO_PIN10_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN10.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN10_GPIO_PIN10_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN10.Reg, volatile.LoadUint32(&o.GPIO_PIN10.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN10_GPIO_PIN10_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN10.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN10_GPIO_PIN10_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN10.Reg, volatile.LoadUint32(&o.GPIO_PIN10.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN10_GPIO_PIN10_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN10.Reg) & 0x1 +} + +// GPIO.GPIO_PIN11: GPIO_PIN11 +func (o *GPIO_Type) SetGPIO_PIN11_GPIO_PIN11_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN11.Reg, volatile.LoadUint32(&o.GPIO_PIN11.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN11_GPIO_PIN11_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN11.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN11_GPIO_PIN11_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN11.Reg, volatile.LoadUint32(&o.GPIO_PIN11.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN11_GPIO_PIN11_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN11.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN11_GPIO_PIN11_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN11.Reg, volatile.LoadUint32(&o.GPIO_PIN11.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN11_GPIO_PIN11_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN11.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN11_GPIO_PIN11_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN11.Reg, volatile.LoadUint32(&o.GPIO_PIN11.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN11_GPIO_PIN11_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN11.Reg) & 0x1 +} + +// GPIO.GPIO_PIN12: GPIO_PIN12 +func (o *GPIO_Type) SetGPIO_PIN12_GPIO_PIN12_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN12.Reg, volatile.LoadUint32(&o.GPIO_PIN12.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN12_GPIO_PIN12_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN12.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN12_GPIO_PIN12_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN12.Reg, volatile.LoadUint32(&o.GPIO_PIN12.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN12_GPIO_PIN12_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN12.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN12_GPIO_PIN12_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN12.Reg, volatile.LoadUint32(&o.GPIO_PIN12.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN12_GPIO_PIN12_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN12.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN12_GPIO_PIN12_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN12.Reg, volatile.LoadUint32(&o.GPIO_PIN12.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN12_GPIO_PIN12_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN12.Reg) & 0x1 +} + +// GPIO.GPIO_PIN13: GPIO_PIN13 +func (o *GPIO_Type) SetGPIO_PIN13_GPIO_PIN13_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN13.Reg, volatile.LoadUint32(&o.GPIO_PIN13.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN13_GPIO_PIN13_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN13.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN13_GPIO_PIN13_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN13.Reg, volatile.LoadUint32(&o.GPIO_PIN13.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN13_GPIO_PIN13_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN13.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN13_GPIO_PIN13_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN13.Reg, volatile.LoadUint32(&o.GPIO_PIN13.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN13_GPIO_PIN13_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN13.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN13_GPIO_PIN13_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN13.Reg, volatile.LoadUint32(&o.GPIO_PIN13.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN13_GPIO_PIN13_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN13.Reg) & 0x1 +} + +// GPIO.GPIO_PIN14: GPIO_PIN14 +func (o *GPIO_Type) SetGPIO_PIN14_GPIO_PIN14_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN14.Reg, volatile.LoadUint32(&o.GPIO_PIN14.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN14_GPIO_PIN14_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN14.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN14_GPIO_PIN14_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN14.Reg, volatile.LoadUint32(&o.GPIO_PIN14.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN14_GPIO_PIN14_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN14.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN14_GPIO_PIN14_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN14.Reg, volatile.LoadUint32(&o.GPIO_PIN14.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN14_GPIO_PIN14_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN14.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN14_GPIO_PIN14_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN14.Reg, volatile.LoadUint32(&o.GPIO_PIN14.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN14_GPIO_PIN14_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN14.Reg) & 0x1 +} + +// GPIO.GPIO_PIN15: GPIO_PIN15 +func (o *GPIO_Type) SetGPIO_PIN15_GPIO_PIN15_WAKEUP_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN15.Reg, volatile.LoadUint32(&o.GPIO_PIN15.Reg)&^(0x400)|value<<10) +} +func (o *GPIO_Type) GetGPIO_PIN15_GPIO_PIN15_WAKEUP_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN15.Reg) & 0x400) >> 10 +} +func (o *GPIO_Type) SetGPIO_PIN15_GPIO_PIN15_INT_TYPE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN15.Reg, volatile.LoadUint32(&o.GPIO_PIN15.Reg)&^(0x380)|value<<7) +} +func (o *GPIO_Type) GetGPIO_PIN15_GPIO_PIN15_INT_TYPE() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN15.Reg) & 0x380) >> 7 +} +func (o *GPIO_Type) SetGPIO_PIN15_GPIO_PIN15_DRIVER(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN15.Reg, volatile.LoadUint32(&o.GPIO_PIN15.Reg)&^(0x4)|value<<2) +} +func (o *GPIO_Type) GetGPIO_PIN15_GPIO_PIN15_DRIVER() uint32 { + return (volatile.LoadUint32(&o.GPIO_PIN15.Reg) & 0x4) >> 2 +} +func (o *GPIO_Type) SetGPIO_PIN15_GPIO_PIN15_SOURCE(value uint32) { + volatile.StoreUint32(&o.GPIO_PIN15.Reg, volatile.LoadUint32(&o.GPIO_PIN15.Reg)&^(0x1)|value) +} +func (o *GPIO_Type) GetGPIO_PIN15_GPIO_PIN15_SOURCE() uint32 { + return volatile.LoadUint32(&o.GPIO_PIN15.Reg) & 0x1 +} + +// GPIO.GPIO_SIGMA_DELTA: GPIO_SIGMA_DELTA +func (o *GPIO_Type) SetGPIO_SIGMA_DELTA_SIGMA_DELTA_ENABLE(value uint32) { + volatile.StoreUint32(&o.GPIO_SIGMA_DELTA.Reg, volatile.LoadUint32(&o.GPIO_SIGMA_DELTA.Reg)&^(0x10000)|value<<16) +} +func (o *GPIO_Type) GetGPIO_SIGMA_DELTA_SIGMA_DELTA_ENABLE() uint32 { + return (volatile.LoadUint32(&o.GPIO_SIGMA_DELTA.Reg) & 0x10000) >> 16 +} +func (o *GPIO_Type) SetGPIO_SIGMA_DELTA_SIGMA_DELTA_PRESCALAR(value uint32) { + volatile.StoreUint32(&o.GPIO_SIGMA_DELTA.Reg, volatile.LoadUint32(&o.GPIO_SIGMA_DELTA.Reg)&^(0xff00)|value<<8) +} +func (o *GPIO_Type) GetGPIO_SIGMA_DELTA_SIGMA_DELTA_PRESCALAR() uint32 { + return (volatile.LoadUint32(&o.GPIO_SIGMA_DELTA.Reg) & 0xff00) >> 8 +} +func (o *GPIO_Type) SetGPIO_SIGMA_DELTA_SIGMA_DELTA_TARGET(value uint32) { + volatile.StoreUint32(&o.GPIO_SIGMA_DELTA.Reg, volatile.LoadUint32(&o.GPIO_SIGMA_DELTA.Reg)&^(0xff)|value) +} +func (o *GPIO_Type) GetGPIO_SIGMA_DELTA_SIGMA_DELTA_TARGET() uint32 { + return volatile.LoadUint32(&o.GPIO_SIGMA_DELTA.Reg) & 0xff +} + +// GPIO.GPIO_RTC_CALIB_SYNC: Positvie edge of this bit will trigger the RTC-clock-calibration process. +func (o *GPIO_Type) SetGPIO_RTC_CALIB_SYNC_RTC_CALIB_START(value uint32) { + volatile.StoreUint32(&o.GPIO_RTC_CALIB_SYNC.Reg, volatile.LoadUint32(&o.GPIO_RTC_CALIB_SYNC.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIO_Type) GetGPIO_RTC_CALIB_SYNC_RTC_CALIB_START() uint32 { + return (volatile.LoadUint32(&o.GPIO_RTC_CALIB_SYNC.Reg) & 0x80000000) >> 31 +} +func (o *GPIO_Type) SetGPIO_RTC_CALIB_SYNC_RTC_PERIOD_NUM(value uint32) { + volatile.StoreUint32(&o.GPIO_RTC_CALIB_SYNC.Reg, volatile.LoadUint32(&o.GPIO_RTC_CALIB_SYNC.Reg)&^(0x3ff)|value) +} +func (o *GPIO_Type) GetGPIO_RTC_CALIB_SYNC_RTC_PERIOD_NUM() uint32 { + return volatile.LoadUint32(&o.GPIO_RTC_CALIB_SYNC.Reg) & 0x3ff +} + +// GPIO.GPIO_RTC_CALIB_VALUE: 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done +func (o *GPIO_Type) SetGPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY(value uint32) { + volatile.StoreUint32(&o.GPIO_RTC_CALIB_VALUE.Reg, volatile.LoadUint32(&o.GPIO_RTC_CALIB_VALUE.Reg)&^(0x80000000)|value<<31) +} +func (o *GPIO_Type) GetGPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY() uint32 { + return (volatile.LoadUint32(&o.GPIO_RTC_CALIB_VALUE.Reg) & 0x80000000) >> 31 +} +func (o *GPIO_Type) SetGPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY_REAL(value uint32) { + volatile.StoreUint32(&o.GPIO_RTC_CALIB_VALUE.Reg, volatile.LoadUint32(&o.GPIO_RTC_CALIB_VALUE.Reg)&^(0x40000000)|value<<30) +} +func (o *GPIO_Type) GetGPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY_REAL() uint32 { + return (volatile.LoadUint32(&o.GPIO_RTC_CALIB_VALUE.Reg) & 0x40000000) >> 30 +} +func (o *GPIO_Type) SetGPIO_RTC_CALIB_VALUE_RTC_CALIB_VALUE(value uint32) { + volatile.StoreUint32(&o.GPIO_RTC_CALIB_VALUE.Reg, volatile.LoadUint32(&o.GPIO_RTC_CALIB_VALUE.Reg)&^(0xfffff)|value) +} +func (o *GPIO_Type) GetGPIO_RTC_CALIB_VALUE_RTC_CALIB_VALUE() uint32 { + return volatile.LoadUint32(&o.GPIO_RTC_CALIB_VALUE.Reg) & 0xfffff +} + +type I2S_Type struct { + I2STXFIFO volatile.Register32 // 0x0 + I2SRXFIFO volatile.Register32 // 0x4 + I2SCONF volatile.Register32 // 0x8 + I2SINT_RAW volatile.Register32 // 0xC + I2SINT_ST volatile.Register32 // 0x10 + I2SINT_ENA volatile.Register32 // 0x14 + I2SINT_CLR volatile.Register32 // 0x18 + I2STIMING volatile.Register32 // 0x1C + I2S_FIFO_CONF volatile.Register32 // 0x20 + I2SRXEOF_NUM volatile.Register32 // 0x24 + I2SCONF_SIGLE_DATA volatile.Register32 // 0x28 +} + +// I2S.I2STXFIFO: I2STXFIFO +func (o *I2S_Type) SetI2STXFIFO(value uint32) { + volatile.StoreUint32(&o.I2STXFIFO.Reg, value) +} +func (o *I2S_Type) GetI2STXFIFO() uint32 { + return volatile.LoadUint32(&o.I2STXFIFO.Reg) +} + +// I2S.I2SRXFIFO: I2SRXFIFO +func (o *I2S_Type) SetI2SRXFIFO(value uint32) { + volatile.StoreUint32(&o.I2SRXFIFO.Reg, value) +} +func (o *I2S_Type) GetI2SRXFIFO() uint32 { + return volatile.LoadUint32(&o.I2SRXFIFO.Reg) +} + +// I2S.I2SCONF: I2SCONF +func (o *I2S_Type) SetI2SCONF_I2S_BCK_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0xfc00000)|value<<22) +} +func (o *I2S_Type) GetI2SCONF_I2S_BCK_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0xfc00000) >> 22 +} +func (o *I2S_Type) SetI2SCONF_I2S_CLKM_DIV_NUM(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x3f0000)|value<<16) +} +func (o *I2S_Type) GetI2SCONF_I2S_CLKM_DIV_NUM() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x3f0000) >> 16 +} +func (o *I2S_Type) SetI2SCONF_I2S_BITS_MOD(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0xf000)|value<<12) +} +func (o *I2S_Type) GetI2SCONF_I2S_BITS_MOD() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0xf000) >> 12 +} +func (o *I2S_Type) SetI2SCONF_I2S_RECE_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x800)|value<<11) +} +func (o *I2S_Type) GetI2SCONF_I2S_RECE_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x800) >> 11 +} +func (o *I2S_Type) SetI2SCONF_I2S_TRANS_MSB_SHIFT(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x400)|value<<10) +} +func (o *I2S_Type) GetI2SCONF_I2S_TRANS_MSB_SHIFT() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x400) >> 10 +} +func (o *I2S_Type) SetI2SCONF_I2S_I2S_RX_START(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x200)|value<<9) +} +func (o *I2S_Type) GetI2SCONF_I2S_I2S_RX_START() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x200) >> 9 +} +func (o *I2S_Type) SetI2SCONF_I2S_I2S_TX_START(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x100)|value<<8) +} +func (o *I2S_Type) GetI2SCONF_I2S_I2S_TX_START() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x100) >> 8 +} +func (o *I2S_Type) SetI2SCONF_I2S_MSB_RIGHT(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x80)|value<<7) +} +func (o *I2S_Type) GetI2SCONF_I2S_MSB_RIGHT() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x80) >> 7 +} +func (o *I2S_Type) SetI2SCONF_I2S_RIGHT_FIRST(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x40)|value<<6) +} +func (o *I2S_Type) GetI2SCONF_I2S_RIGHT_FIRST() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x40) >> 6 +} +func (o *I2S_Type) SetI2SCONF_I2S_RECE_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetI2SCONF_I2S_RECE_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetI2SCONF_I2S_TRANS_SLAVE_MOD(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetI2SCONF_I2S_TRANS_SLAVE_MOD() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetI2SCONF_I2S_I2S_RX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetI2SCONF_I2S_I2S_RX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetI2SCONF_I2S_I2S_TX_FIFO_RESET(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetI2SCONF_I2S_I2S_TX_FIFO_RESET() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetI2SCONF_I2S_I2S_RX_RESET(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetI2SCONF_I2S_I2S_RX_RESET() uint32 { + return (volatile.LoadUint32(&o.I2SCONF.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetI2SCONF_I2S_I2S_TX_RESET(value uint32) { + volatile.StoreUint32(&o.I2SCONF.Reg, volatile.LoadUint32(&o.I2SCONF.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetI2SCONF_I2S_I2S_TX_RESET() uint32 { + return volatile.LoadUint32(&o.I2SCONF.Reg) & 0x1 +} + +// I2S.I2SINT_RAW: I2SINT_RAW +func (o *I2S_Type) SetI2SINT_RAW_I2S_I2S_TX_REMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2SINT_RAW.Reg, volatile.LoadUint32(&o.I2SINT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetI2SINT_RAW_I2S_I2S_TX_REMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2SINT_RAW.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetI2SINT_RAW_I2S_I2S_TX_WFULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2SINT_RAW.Reg, volatile.LoadUint32(&o.I2SINT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetI2SINT_RAW_I2S_I2S_TX_WFULL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2SINT_RAW.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetI2SINT_RAW_I2S_I2S_RX_REMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2SINT_RAW.Reg, volatile.LoadUint32(&o.I2SINT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetI2SINT_RAW_I2S_I2S_RX_REMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2SINT_RAW.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetI2SINT_RAW_I2S_I2S_RX_WFULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2SINT_RAW.Reg, volatile.LoadUint32(&o.I2SINT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetI2SINT_RAW_I2S_I2S_RX_WFULL_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2SINT_RAW.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetI2SINT_RAW_I2S_I2S_TX_PUT_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2SINT_RAW.Reg, volatile.LoadUint32(&o.I2SINT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetI2SINT_RAW_I2S_I2S_TX_PUT_DATA_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.I2SINT_RAW.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetI2SINT_RAW_I2S_I2S_RX_TAKE_DATA_INT_RAW(value uint32) { + volatile.StoreUint32(&o.I2SINT_RAW.Reg, volatile.LoadUint32(&o.I2SINT_RAW.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetI2SINT_RAW_I2S_I2S_RX_TAKE_DATA_INT_RAW() uint32 { + return volatile.LoadUint32(&o.I2SINT_RAW.Reg) & 0x1 +} + +// I2S.I2SINT_ST: I2SINT_ST +func (o *I2S_Type) SetI2SINT_ST_I2S_I2S_TX_REMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2SINT_ST.Reg, volatile.LoadUint32(&o.I2SINT_ST.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetI2SINT_ST_I2S_I2S_TX_REMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ST.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetI2SINT_ST_I2S_I2S_TX_WFULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2SINT_ST.Reg, volatile.LoadUint32(&o.I2SINT_ST.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetI2SINT_ST_I2S_I2S_TX_WFULL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ST.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetI2SINT_ST_I2S_I2S_RX_REMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2SINT_ST.Reg, volatile.LoadUint32(&o.I2SINT_ST.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetI2SINT_ST_I2S_I2S_RX_REMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ST.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetI2SINT_ST_I2S_I2S_RX_WFULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2SINT_ST.Reg, volatile.LoadUint32(&o.I2SINT_ST.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetI2SINT_ST_I2S_I2S_RX_WFULL_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ST.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetI2SINT_ST_I2S_I2S_TX_PUT_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2SINT_ST.Reg, volatile.LoadUint32(&o.I2SINT_ST.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetI2SINT_ST_I2S_I2S_TX_PUT_DATA_INT_ST() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ST.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetI2SINT_ST_I2S_I2S_RX_TAKE_DATA_INT_ST(value uint32) { + volatile.StoreUint32(&o.I2SINT_ST.Reg, volatile.LoadUint32(&o.I2SINT_ST.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetI2SINT_ST_I2S_I2S_RX_TAKE_DATA_INT_ST() uint32 { + return volatile.LoadUint32(&o.I2SINT_ST.Reg) & 0x1 +} + +// I2S.I2SINT_ENA: I2SINT_ENA +func (o *I2S_Type) SetI2SINT_ENA_I2S_I2S_TX_REMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2SINT_ENA.Reg, volatile.LoadUint32(&o.I2SINT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetI2SINT_ENA_I2S_I2S_TX_REMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ENA.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetI2SINT_ENA_I2S_I2S_TX_WFULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2SINT_ENA.Reg, volatile.LoadUint32(&o.I2SINT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetI2SINT_ENA_I2S_I2S_TX_WFULL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ENA.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetI2SINT_ENA_I2S_I2S_RX_REMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2SINT_ENA.Reg, volatile.LoadUint32(&o.I2SINT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetI2SINT_ENA_I2S_I2S_RX_REMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ENA.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetI2SINT_ENA_I2S_I2S_RX_WFULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2SINT_ENA.Reg, volatile.LoadUint32(&o.I2SINT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetI2SINT_ENA_I2S_I2S_RX_WFULL_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ENA.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetI2SINT_ENA_I2S_I2S_TX_PUT_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2SINT_ENA.Reg, volatile.LoadUint32(&o.I2SINT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetI2SINT_ENA_I2S_I2S_TX_PUT_DATA_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.I2SINT_ENA.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetI2SINT_ENA_I2S_I2S_RX_TAKE_DATA_INT_ENA(value uint32) { + volatile.StoreUint32(&o.I2SINT_ENA.Reg, volatile.LoadUint32(&o.I2SINT_ENA.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetI2SINT_ENA_I2S_I2S_RX_TAKE_DATA_INT_ENA() uint32 { + return volatile.LoadUint32(&o.I2SINT_ENA.Reg) & 0x1 +} + +// I2S.I2SINT_CLR: I2SINT_CLR +func (o *I2S_Type) SetI2SINT_CLR_I2S_I2S_TX_REMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2SINT_CLR.Reg, volatile.LoadUint32(&o.I2SINT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *I2S_Type) GetI2SINT_CLR_I2S_I2S_TX_REMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2SINT_CLR.Reg) & 0x20) >> 5 +} +func (o *I2S_Type) SetI2SINT_CLR_I2S_I2S_TX_WFULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2SINT_CLR.Reg, volatile.LoadUint32(&o.I2SINT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *I2S_Type) GetI2SINT_CLR_I2S_I2S_TX_WFULL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2SINT_CLR.Reg) & 0x10) >> 4 +} +func (o *I2S_Type) SetI2SINT_CLR_I2S_I2S_RX_REMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2SINT_CLR.Reg, volatile.LoadUint32(&o.I2SINT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *I2S_Type) GetI2SINT_CLR_I2S_I2S_RX_REMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2SINT_CLR.Reg) & 0x8) >> 3 +} +func (o *I2S_Type) SetI2SINT_CLR_I2S_I2S_RX_WFULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2SINT_CLR.Reg, volatile.LoadUint32(&o.I2SINT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *I2S_Type) GetI2SINT_CLR_I2S_I2S_RX_WFULL_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2SINT_CLR.Reg) & 0x4) >> 2 +} +func (o *I2S_Type) SetI2SINT_CLR_I2S_I2S_PUT_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2SINT_CLR.Reg, volatile.LoadUint32(&o.I2SINT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *I2S_Type) GetI2SINT_CLR_I2S_I2S_PUT_DATA_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.I2SINT_CLR.Reg) & 0x2) >> 1 +} +func (o *I2S_Type) SetI2SINT_CLR_I2S_I2S_TAKE_DATA_INT_CLR(value uint32) { + volatile.StoreUint32(&o.I2SINT_CLR.Reg, volatile.LoadUint32(&o.I2SINT_CLR.Reg)&^(0x1)|value) +} +func (o *I2S_Type) GetI2SINT_CLR_I2S_I2S_TAKE_DATA_INT_CLR() uint32 { + return volatile.LoadUint32(&o.I2SINT_CLR.Reg) & 0x1 +} + +// I2S.I2STIMING: I2STIMING +func (o *I2S_Type) SetI2STIMING_I2S_TRANS_BCK_IN_INV(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0x400000)|value<<22) +} +func (o *I2S_Type) GetI2STIMING_I2S_TRANS_BCK_IN_INV() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0x400000) >> 22 +} +func (o *I2S_Type) SetI2STIMING_I2S_RECE_DSYNC_SW(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0x200000)|value<<21) +} +func (o *I2S_Type) GetI2STIMING_I2S_RECE_DSYNC_SW() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0x200000) >> 21 +} +func (o *I2S_Type) SetI2STIMING_I2S_TRANS_DSYNC_SW(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0x100000)|value<<20) +} +func (o *I2S_Type) GetI2STIMING_I2S_TRANS_DSYNC_SW() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0x100000) >> 20 +} +func (o *I2S_Type) SetI2STIMING_I2S_RECE_BCK_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0xc0000)|value<<18) +} +func (o *I2S_Type) GetI2STIMING_I2S_RECE_BCK_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0xc0000) >> 18 +} +func (o *I2S_Type) SetI2STIMING_I2S_RECE_WS_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0x30000)|value<<16) +} +func (o *I2S_Type) GetI2STIMING_I2S_RECE_WS_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0x30000) >> 16 +} +func (o *I2S_Type) SetI2STIMING_I2S_TRANS_SD_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0xc000)|value<<14) +} +func (o *I2S_Type) GetI2STIMING_I2S_TRANS_SD_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0xc000) >> 14 +} +func (o *I2S_Type) SetI2STIMING_I2S_TRANS_WS_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0x3000)|value<<12) +} +func (o *I2S_Type) GetI2STIMING_I2S_TRANS_WS_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0x3000) >> 12 +} +func (o *I2S_Type) SetI2STIMING_I2S_TRANS_BCK_OUT_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0xc00)|value<<10) +} +func (o *I2S_Type) GetI2STIMING_I2S_TRANS_BCK_OUT_DELAY() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0xc00) >> 10 +} +func (o *I2S_Type) SetI2STIMING_I2S_RECE_SD_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0x300)|value<<8) +} +func (o *I2S_Type) GetI2STIMING_I2S_RECE_SD_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0x300) >> 8 +} +func (o *I2S_Type) SetI2STIMING_I2S_RECE_WS_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0xc0)|value<<6) +} +func (o *I2S_Type) GetI2STIMING_I2S_RECE_WS_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0xc0) >> 6 +} +func (o *I2S_Type) SetI2STIMING_I2S_RECE_BCK_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0x30)|value<<4) +} +func (o *I2S_Type) GetI2STIMING_I2S_RECE_BCK_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0x30) >> 4 +} +func (o *I2S_Type) SetI2STIMING_I2S_TRANS_WS_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0xc)|value<<2) +} +func (o *I2S_Type) GetI2STIMING_I2S_TRANS_WS_IN_DELAY() uint32 { + return (volatile.LoadUint32(&o.I2STIMING.Reg) & 0xc) >> 2 +} +func (o *I2S_Type) SetI2STIMING_I2S_TRANS_BCK_IN_DELAY(value uint32) { + volatile.StoreUint32(&o.I2STIMING.Reg, volatile.LoadUint32(&o.I2STIMING.Reg)&^(0x3)|value) +} +func (o *I2S_Type) GetI2STIMING_I2S_TRANS_BCK_IN_DELAY() uint32 { + return volatile.LoadUint32(&o.I2STIMING.Reg) & 0x3 +} + +// I2S.I2S_FIFO_CONF: I2S_FIFO_CONF +func (o *I2S_Type) SetI2S_FIFO_CONF_I2S_I2S_RX_FIFO_MOD(value uint32) { + volatile.StoreUint32(&o.I2S_FIFO_CONF.Reg, volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg)&^(0x70000)|value<<16) +} +func (o *I2S_Type) GetI2S_FIFO_CONF_I2S_I2S_RX_FIFO_MOD() uint32 { + return (volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg) & 0x70000) >> 16 +} +func (o *I2S_Type) SetI2S_FIFO_CONF_I2S_I2S_TX_FIFO_MOD(value uint32) { + volatile.StoreUint32(&o.I2S_FIFO_CONF.Reg, volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg)&^(0xe000)|value<<13) +} +func (o *I2S_Type) GetI2S_FIFO_CONF_I2S_I2S_TX_FIFO_MOD() uint32 { + return (volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg) & 0xe000) >> 13 +} +func (o *I2S_Type) SetI2S_FIFO_CONF_I2S_I2S_DSCR_EN(value uint32) { + volatile.StoreUint32(&o.I2S_FIFO_CONF.Reg, volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *I2S_Type) GetI2S_FIFO_CONF_I2S_I2S_DSCR_EN() uint32 { + return (volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg) & 0x1000) >> 12 +} +func (o *I2S_Type) SetI2S_FIFO_CONF_I2S_I2S_TX_DATA_NUM(value uint32) { + volatile.StoreUint32(&o.I2S_FIFO_CONF.Reg, volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg)&^(0xfc0)|value<<6) +} +func (o *I2S_Type) GetI2S_FIFO_CONF_I2S_I2S_TX_DATA_NUM() uint32 { + return (volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg) & 0xfc0) >> 6 +} +func (o *I2S_Type) SetI2S_FIFO_CONF_I2S_I2S_RX_DATA_NUM(value uint32) { + volatile.StoreUint32(&o.I2S_FIFO_CONF.Reg, volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg)&^(0x3f)|value) +} +func (o *I2S_Type) GetI2S_FIFO_CONF_I2S_I2S_RX_DATA_NUM() uint32 { + return volatile.LoadUint32(&o.I2S_FIFO_CONF.Reg) & 0x3f +} + +// I2S.I2SRXEOF_NUM: I2SRXEOF_NUM +func (o *I2S_Type) SetI2SRXEOF_NUM(value uint32) { + volatile.StoreUint32(&o.I2SRXEOF_NUM.Reg, value) +} +func (o *I2S_Type) GetI2SRXEOF_NUM() uint32 { + return volatile.LoadUint32(&o.I2SRXEOF_NUM.Reg) +} + +// I2S.I2SCONF_SIGLE_DATA: I2SCONF_SIGLE_DATA +func (o *I2S_Type) SetI2SCONF_SIGLE_DATA(value uint32) { + volatile.StoreUint32(&o.I2SCONF_SIGLE_DATA.Reg, value) +} +func (o *I2S_Type) GetI2SCONF_SIGLE_DATA() uint32 { + return volatile.LoadUint32(&o.I2SCONF_SIGLE_DATA.Reg) +} + +type IO_MUX_Type struct { + IO_MUX_CONF volatile.Register32 // 0x0 + IO_MUX_MTDI volatile.Register32 // 0x4 + IO_MUX_MTCK volatile.Register32 // 0x8 + IO_MUX_MTMS volatile.Register32 // 0xC + IO_MUX_MTDO volatile.Register32 // 0x10 + IO_MUX_U0RXD volatile.Register32 // 0x14 + IO_MUX_U0TXD volatile.Register32 // 0x18 + IO_MUX_SD_CLK volatile.Register32 // 0x1C + IO_MUX_SD_DATA0 volatile.Register32 // 0x20 + IO_MUX_SD_DATA1 volatile.Register32 // 0x24 + IO_MUX_SD_DATA2 volatile.Register32 // 0x28 + IO_MUX_SD_DATA3 volatile.Register32 // 0x2C + IO_MUX_SD_CMD volatile.Register32 // 0x30 + IO_MUX_GPIO0 volatile.Register32 // 0x34 + IO_MUX_GPIO2 volatile.Register32 // 0x38 + IO_MUX_GPIO4 volatile.Register32 // 0x3C + IO_MUX_GPIO5 volatile.Register32 // 0x40 +} + +// IO_MUX.IO_MUX_CONF: IO_MUX_CONF +func (o *IO_MUX_Type) SetIO_MUX_CONF_SPI0_CLK_EQU_SYS_CLK(value uint32) { + volatile.StoreUint32(&o.IO_MUX_CONF.Reg, volatile.LoadUint32(&o.IO_MUX_CONF.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_CONF_SPI0_CLK_EQU_SYS_CLK() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_CONF.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_CONF_SPI1_CLK_EQU_SYS_CLK(value uint32) { + volatile.StoreUint32(&o.IO_MUX_CONF.Reg, volatile.LoadUint32(&o.IO_MUX_CONF.Reg)&^(0x200)|value<<9) +} +func (o *IO_MUX_Type) GetIO_MUX_CONF_SPI1_CLK_EQU_SYS_CLK() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_CONF.Reg) & 0x200) >> 9 +} + +// IO_MUX.IO_MUX_MTDI: IO_MUX_MTDI +func (o *IO_MUX_Type) SetIO_MUX_MTDI(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDI.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDI() uint32 { + return volatile.LoadUint32(&o.IO_MUX_MTDI.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_MTDI_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDI.Reg, volatile.LoadUint32(&o.IO_MUX_MTDI.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDI_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTDI.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_MTDI_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDI.Reg, volatile.LoadUint32(&o.IO_MUX_MTDI.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDI_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTDI.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_MTDI_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDI.Reg, volatile.LoadUint32(&o.IO_MUX_MTDI.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDI_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTDI.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_MTDI_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDI.Reg, volatile.LoadUint32(&o.IO_MUX_MTDI.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDI_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTDI.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_MTDI_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDI.Reg, volatile.LoadUint32(&o.IO_MUX_MTDI.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDI_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_MTDI.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_MTCK: IO_MUX_MTCK +func (o *IO_MUX_Type) SetIO_MUX_MTCK(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTCK.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_MTCK() uint32 { + return volatile.LoadUint32(&o.IO_MUX_MTCK.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_MTCK_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTCK.Reg, volatile.LoadUint32(&o.IO_MUX_MTCK.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_MTCK_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTCK.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_MTCK_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTCK.Reg, volatile.LoadUint32(&o.IO_MUX_MTCK.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_MTCK_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTCK.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_MTCK_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTCK.Reg, volatile.LoadUint32(&o.IO_MUX_MTCK.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_MTCK_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTCK.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_MTCK_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTCK.Reg, volatile.LoadUint32(&o.IO_MUX_MTCK.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_MTCK_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTCK.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_MTCK_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTCK.Reg, volatile.LoadUint32(&o.IO_MUX_MTCK.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_MTCK_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_MTCK.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_MTMS: IO_MUX_MTMS +func (o *IO_MUX_Type) SetIO_MUX_MTMS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTMS.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_MTMS() uint32 { + return volatile.LoadUint32(&o.IO_MUX_MTMS.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_MTMS_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTMS.Reg, volatile.LoadUint32(&o.IO_MUX_MTMS.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_MTMS_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTMS.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_MTMS_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTMS.Reg, volatile.LoadUint32(&o.IO_MUX_MTMS.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_MTMS_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTMS.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_MTMS_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTMS.Reg, volatile.LoadUint32(&o.IO_MUX_MTMS.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_MTMS_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTMS.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_MTMS_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTMS.Reg, volatile.LoadUint32(&o.IO_MUX_MTMS.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_MTMS_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTMS.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_MTMS_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTMS.Reg, volatile.LoadUint32(&o.IO_MUX_MTMS.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_MTMS_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_MTMS.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_MTDO: IO_MUX_MTDO +func (o *IO_MUX_Type) SetIO_MUX_MTDO(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDO.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDO() uint32 { + return volatile.LoadUint32(&o.IO_MUX_MTDO.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_MTDO_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDO.Reg, volatile.LoadUint32(&o.IO_MUX_MTDO.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDO_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTDO.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_MTDO_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDO.Reg, volatile.LoadUint32(&o.IO_MUX_MTDO.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDO_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTDO.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_MTDO_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDO.Reg, volatile.LoadUint32(&o.IO_MUX_MTDO.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDO_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTDO.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_MTDO_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDO.Reg, volatile.LoadUint32(&o.IO_MUX_MTDO.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDO_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_MTDO.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_MTDO_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_MTDO.Reg, volatile.LoadUint32(&o.IO_MUX_MTDO.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_MTDO_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_MTDO.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_U0RXD: IO_MUX_U0RXD +func (o *IO_MUX_Type) SetIO_MUX_U0RXD(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0RXD.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_U0RXD() uint32 { + return volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_U0RXD_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0RXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_U0RXD_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_U0RXD_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0RXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_U0RXD_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_U0RXD_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0RXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_U0RXD_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_U0RXD_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0RXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_U0RXD_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_U0RXD_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0RXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_U0RXD_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_U0RXD.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_U0TXD: IO_MUX_U0TXD +func (o *IO_MUX_Type) SetIO_MUX_U0TXD(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0TXD.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_U0TXD() uint32 { + return volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_U0TXD_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0TXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_U0TXD_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_U0TXD_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0TXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_U0TXD_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_U0TXD_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0TXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_U0TXD_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_U0TXD_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0TXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_U0TXD_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_U0TXD_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_U0TXD.Reg, volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_U0TXD_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_U0TXD.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_SD_CLK: IO_MUX_SD_CLK +func (o *IO_MUX_Type) SetIO_MUX_SD_CLK(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CLK.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CLK() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CLK_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CLK.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CLK_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CLK_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CLK.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CLK_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CLK_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CLK.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CLK_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CLK_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CLK.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CLK_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CLK_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CLK.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CLK_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_CLK.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_SD_DATA0: IO_MUX_SD_DATA0 +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA0(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA0.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA0() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA0_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA0.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA0_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA0_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA0.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA0_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA0_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA0.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA0_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA0_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA0.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA0_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA0_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA0.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA0_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_DATA0.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_SD_DATA1: IO_MUX_SD_DATA1 +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA1(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA1.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA1() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA1_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA1.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA1_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA1_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA1.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA1_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA1_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA1.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA1_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA1_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA1.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA1_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA1_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA1.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA1_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_DATA1.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_SD_DATA2: IO_MUX_SD_DATA2 +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA2(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA2.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA2() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA2_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA2.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA2_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA2_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA2.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA2_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA2_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA2.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA2_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA2_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA2.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA2_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA2_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA2.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA2_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_DATA2.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_SD_DATA3: IO_MUX_SD_DATA3 +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA3(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA3.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA3() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA3_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA3.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA3_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA3_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA3.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA3_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA3_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA3.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA3_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA3_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA3.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA3_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_DATA3_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_DATA3.Reg, volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_DATA3_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_DATA3.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_SD_CMD: IO_MUX_SD_CMD +func (o *IO_MUX_Type) SetIO_MUX_SD_CMD(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CMD.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CMD() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CMD_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CMD.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CMD_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CMD_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CMD.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CMD_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CMD_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CMD.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CMD_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CMD_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CMD.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CMD_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_SD_CMD_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_SD_CMD.Reg, volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_SD_CMD_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_SD_CMD.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_GPIO0: IO_MUX_GPIO0 +func (o *IO_MUX_Type) SetIO_MUX_GPIO0(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO0.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO0() uint32 { + return volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO0_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO0.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO0_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO0_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO0.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO0_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO0_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO0.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO0_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO0_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO0.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO0_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO0_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO0.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO0_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_GPIO0.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_GPIO2: IO_MUX_GPIO2 +func (o *IO_MUX_Type) SetIO_MUX_GPIO2(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO2.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO2() uint32 { + return volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO2_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO2.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO2_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO2_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO2.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO2_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO2_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO2.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO2_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO2_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO2.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO2_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO2_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO2.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO2_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_GPIO2.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_GPIO4: IO_MUX_GPIO4 +func (o *IO_MUX_Type) SetIO_MUX_GPIO4(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO4.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO4() uint32 { + return volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO4_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO4.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO4_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO4_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO4.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO4_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO4_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO4.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO4_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO4_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO4.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO4_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO4_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO4.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO4_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_GPIO4.Reg) & 0x1 +} + +// IO_MUX.IO_MUX_GPIO5: IO_MUX_GPIO5 +func (o *IO_MUX_Type) SetIO_MUX_GPIO5(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO5.Reg, value) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO5() uint32 { + return volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg) +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO5_FUNCTION_SELECT_LOW_BITS(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO5.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg)&^(0x30)|value<<4) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO5_FUNCTION_SELECT_LOW_BITS() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg) & 0x30) >> 4 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO5_FUNCTION_SELECT_HIGH_BIT(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO5.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg)&^(0x100)|value<<8) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO5_FUNCTION_SELECT_HIGH_BIT() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg) & 0x100) >> 8 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO5_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO5.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg)&^(0x80)|value<<7) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO5_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg) & 0x80) >> 7 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO5_SLEEP_PULLUP(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO5.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg)&^(0x8)|value<<3) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO5_SLEEP_PULLUP() uint32 { + return (volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg) & 0x8) >> 3 +} +func (o *IO_MUX_Type) SetIO_MUX_GPIO5_SLEEP_ENABLE(value uint32) { + volatile.StoreUint32(&o.IO_MUX_GPIO5.Reg, volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg)&^(0x1)|value) +} +func (o *IO_MUX_Type) GetIO_MUX_GPIO5_SLEEP_ENABLE() uint32 { + return volatile.LoadUint32(&o.IO_MUX_GPIO5.Reg) & 0x1 +} + +type RTC_Type struct { + _ [20]byte + RTC_STATE1 volatile.Register32 // 0x14 + _ [24]byte + RTC_STORE0 volatile.Register32 // 0x30 +} + +// RTC.RTC_STATE1: RTC_STATE1 +func (o *RTC_Type) SetRTC_STATE1(value uint32) { + volatile.StoreUint32(&o.RTC_STATE1.Reg, value) +} +func (o *RTC_Type) GetRTC_STATE1() uint32 { + return volatile.LoadUint32(&o.RTC_STATE1.Reg) +} + +// RTC.RTC_STORE0: RTC_STORE0 +func (o *RTC_Type) SetRTC_STORE0(value uint32) { + volatile.StoreUint32(&o.RTC_STORE0.Reg, value) +} +func (o *RTC_Type) GetRTC_STORE0() uint32 { + return volatile.LoadUint32(&o.RTC_STORE0.Reg) +} + +type SLC_Type struct { + SLC_CONF0 volatile.Register32 // 0x0 + SLC_INT_RAW volatile.Register32 // 0x4 + SLC_INT_STATUS volatile.Register32 // 0x8 + SLC_INT_ENA volatile.Register32 // 0xC + SLC_INT_CLR volatile.Register32 // 0x10 + SLC_RX_STATUS volatile.Register32 // 0x14 + SLC_RX_FIFO_PUSH volatile.Register32 // 0x18 + SLC_TX_STATUS volatile.Register32 // 0x1C + SLC_TX_FIFO_POP volatile.Register32 // 0x20 + SLC_RX_LINK volatile.Register32 // 0x24 + SLC_TX_LINK volatile.Register32 // 0x28 + SLC_INTVEC_TOHOST volatile.Register32 // 0x2C + SLC_TOKEN0 volatile.Register32 // 0x30 + SLC_TOKEN1 volatile.Register32 // 0x34 + SLC_CONF1 volatile.Register32 // 0x38 + SLC_STATE0 volatile.Register32 // 0x3C + SLC_STATE1 volatile.Register32 // 0x40 + SLC_BRIDGE_CONF volatile.Register32 // 0x44 + SLC_RX_EOF_DES_ADDR volatile.Register32 // 0x48 + SLC_TX_EOF_DES_ADDR volatile.Register32 // 0x4C + SLC_RX_EOF_BFR_DES_ADDR volatile.Register32 // 0x50 + SLC_AHB_TEST volatile.Register32 // 0x54 + SLC_SDIO_ST volatile.Register32 // 0x58 + SLC_RX_DSCR_CONF volatile.Register32 // 0x5C + SLC_TXLINK_DSCR volatile.Register32 // 0x60 + SLC_TXLINK_DSCR_BF0 volatile.Register32 // 0x64 + SLC_TXLINK_DSCR_BF1 volatile.Register32 // 0x68 + SLC_RXLINK_DSCR volatile.Register32 // 0x6C + SLC_RXLINK_DSCR_BF0 volatile.Register32 // 0x70 + SLC_RXLINK_DSCR_BF1 volatile.Register32 // 0x74 + SLC_DATE volatile.Register32 // 0x78 + SLC_ID volatile.Register32 // 0x7C +} + +// SLC.SLC_CONF0: SLC_CONF0 +func (o *SLC_Type) SetSLC_CONF0_SLC_MODE(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x3000)|value<<12) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_MODE() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x3000) >> 12 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_DATA_BURST_EN(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_DATA_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_DSCR_BURST_EN(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_DSCR_BURST_EN() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_RX_NO_RESTART_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_RX_NO_RESTART_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_RX_AUTO_WRBACK(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_RX_AUTO_WRBACK() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_RX_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_RX_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_TX_LOOP_TEST(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_TX_LOOP_TEST() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_AHBM_RST(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_AHBM_RST() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_AHBM_FIFO_RST(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_AHBM_FIFO_RST() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_RXLINK_RST(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_RXLINK_RST() uint32 { + return (volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetSLC_CONF0_SLC_TXLINK_RST(value uint32) { + volatile.StoreUint32(&o.SLC_CONF0.Reg, volatile.LoadUint32(&o.SLC_CONF0.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetSLC_CONF0_SLC_TXLINK_RST() uint32 { + return volatile.LoadUint32(&o.SLC_CONF0.Reg) & 0x1 +} + +// SLC.SLC_INT_RAW: SLC_INT_RAW +func (o *SLC_Type) SetSLC_INT_RAW_SLC_TX_DSCR_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_TX_DSCR_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_RX_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_RX_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_TX_DSCR_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_TX_DSCR_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_TOHOST_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_TOHOST_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_RX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_RX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_RX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_RX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_TX_EOF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_TX_EOF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_TX_DONE_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_TX_DONE_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_TOKEN1_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_TOKEN1_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_TOKEN0_1TO0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_TOKEN0_1TO0_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_TX_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_TX_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_RX_UDF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_RX_UDF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_TX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_TX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_RX_START_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_RX_START_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_FRHOST_BIT7_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_FRHOST_BIT7_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_FRHOST_BIT6_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_FRHOST_BIT6_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_FRHOST_BIT5_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_FRHOST_BIT5_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_FRHOST_BIT4_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_FRHOST_BIT4_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_FRHOST_BIT3_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_FRHOST_BIT3_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_FRHOST_BIT2_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_FRHOST_BIT2_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_FRHOST_BIT1_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_FRHOST_BIT1_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetSLC_INT_RAW_SLC_FRHOST_BIT0_INT_RAW(value uint32) { + volatile.StoreUint32(&o.SLC_INT_RAW.Reg, volatile.LoadUint32(&o.SLC_INT_RAW.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetSLC_INT_RAW_SLC_FRHOST_BIT0_INT_RAW() uint32 { + return volatile.LoadUint32(&o.SLC_INT_RAW.Reg) & 0x1 +} + +// SLC.SLC_INT_STATUS: SLC_INT_STATUS +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_TX_DSCR_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_TX_DSCR_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_RX_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_RX_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_TX_DSCR_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_TX_DSCR_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_TOHOST_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_TOHOST_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_RX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_RX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_RX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_RX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_TX_EOF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_TX_EOF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_TX_DONE_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_TX_DONE_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_TOKEN1_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_TOKEN1_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_TOKEN0_1TO0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_TOKEN0_1TO0_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_TX_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_TX_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_RX_UDF_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_RX_UDF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_TX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_TX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_RX_START_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_RX_START_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_FRHOST_BIT7_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_FRHOST_BIT7_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_FRHOST_BIT6_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_FRHOST_BIT6_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_FRHOST_BIT5_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_FRHOST_BIT5_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_FRHOST_BIT4_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_FRHOST_BIT4_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_FRHOST_BIT3_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_FRHOST_BIT3_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_FRHOST_BIT2_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_FRHOST_BIT2_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_FRHOST_BIT1_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_FRHOST_BIT1_INT_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetSLC_INT_STATUS_SLC_FRHOST_BIT0_INT_ST(value uint32) { + volatile.StoreUint32(&o.SLC_INT_STATUS.Reg, volatile.LoadUint32(&o.SLC_INT_STATUS.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetSLC_INT_STATUS_SLC_FRHOST_BIT0_INT_ST() uint32 { + return volatile.LoadUint32(&o.SLC_INT_STATUS.Reg) & 0x1 +} + +// SLC.SLC_INT_ENA: SLC_INT_ENA +func (o *SLC_Type) SetSLC_INT_ENA_SLC_TX_DSCR_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_TX_DSCR_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_RX_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_RX_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_TX_DSCR_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_TX_DSCR_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_TOHOST_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_TOHOST_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_RX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_RX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_RX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_RX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_TX_EOF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_TX_EOF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_TX_DONE_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_TX_DONE_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_TOKEN1_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_TOKEN1_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_TOKEN0_1TO0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_TOKEN0_1TO0_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_TX_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_TX_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_RX_UDF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_RX_UDF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_TX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_TX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_RX_START_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_RX_START_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_FRHOST_BIT7_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_FRHOST_BIT7_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_FRHOST_BIT6_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_FRHOST_BIT6_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_FRHOST_BIT5_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_FRHOST_BIT5_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_FRHOST_BIT4_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_FRHOST_BIT4_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_FRHOST_BIT3_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_FRHOST_BIT3_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_FRHOST_BIT2_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_FRHOST_BIT2_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_FRHOST_BIT1_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_FRHOST_BIT1_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetSLC_INT_ENA_SLC_FRHOST_BIT0_INT_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_INT_ENA.Reg, volatile.LoadUint32(&o.SLC_INT_ENA.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetSLC_INT_ENA_SLC_FRHOST_BIT0_INT_ENA() uint32 { + return volatile.LoadUint32(&o.SLC_INT_ENA.Reg) & 0x1 +} + +// SLC.SLC_INT_CLR: SLC_INT_CLR +func (o *SLC_Type) SetSLC_INT_CLR_SLC_TX_DSCR_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x200000)|value<<21) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_TX_DSCR_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x200000) >> 21 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_RX_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x100000)|value<<20) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_RX_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x100000) >> 20 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_TX_DSCR_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x80000)|value<<19) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_TX_DSCR_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x80000) >> 19 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_TOHOST_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x40000)|value<<18) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_TOHOST_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x40000) >> 18 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_RX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x20000)|value<<17) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_RX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x20000) >> 17 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_RX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_RX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_TX_EOF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x8000)|value<<15) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_TX_EOF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x8000) >> 15 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_TX_DONE_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_TX_DONE_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_TOKEN1_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_TOKEN1_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_TOKEN0_1TO0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_TOKEN0_1TO0_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_TX_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x800)|value<<11) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_TX_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x800) >> 11 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_RX_UDF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x400)|value<<10) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_RX_UDF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x400) >> 10 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_TX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_TX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_RX_START_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_RX_START_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_FRHOST_BIT7_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_FRHOST_BIT7_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_FRHOST_BIT6_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_FRHOST_BIT6_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_FRHOST_BIT5_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_FRHOST_BIT5_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_FRHOST_BIT4_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_FRHOST_BIT4_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_FRHOST_BIT3_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_FRHOST_BIT3_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_FRHOST_BIT2_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_FRHOST_BIT2_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_FRHOST_BIT1_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_FRHOST_BIT1_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetSLC_INT_CLR_SLC_FRHOST_BIT0_INT_CLR(value uint32) { + volatile.StoreUint32(&o.SLC_INT_CLR.Reg, volatile.LoadUint32(&o.SLC_INT_CLR.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetSLC_INT_CLR_SLC_FRHOST_BIT0_INT_CLR() uint32 { + return volatile.LoadUint32(&o.SLC_INT_CLR.Reg) & 0x1 +} + +// SLC.SLC_RX_STATUS: SLC_RX_STATUS +func (o *SLC_Type) SetSLC_RX_STATUS_SLC_RX_EMPTY(value uint32) { + volatile.StoreUint32(&o.SLC_RX_STATUS.Reg, volatile.LoadUint32(&o.SLC_RX_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetSLC_RX_STATUS_SLC_RX_EMPTY() uint32 { + return (volatile.LoadUint32(&o.SLC_RX_STATUS.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetSLC_RX_STATUS_SLC_RX_FULL(value uint32) { + volatile.StoreUint32(&o.SLC_RX_STATUS.Reg, volatile.LoadUint32(&o.SLC_RX_STATUS.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetSLC_RX_STATUS_SLC_RX_FULL() uint32 { + return volatile.LoadUint32(&o.SLC_RX_STATUS.Reg) & 0x1 +} + +// SLC.SLC_RX_FIFO_PUSH: SLC_RX_FIFO_PUSH +func (o *SLC_Type) SetSLC_RX_FIFO_PUSH_SLC_RXFIFO_PUSH(value uint32) { + volatile.StoreUint32(&o.SLC_RX_FIFO_PUSH.Reg, volatile.LoadUint32(&o.SLC_RX_FIFO_PUSH.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetSLC_RX_FIFO_PUSH_SLC_RXFIFO_PUSH() uint32 { + return (volatile.LoadUint32(&o.SLC_RX_FIFO_PUSH.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetSLC_RX_FIFO_PUSH_SLC_RXFIFO_WDATA(value uint32) { + volatile.StoreUint32(&o.SLC_RX_FIFO_PUSH.Reg, volatile.LoadUint32(&o.SLC_RX_FIFO_PUSH.Reg)&^(0x1ff)|value) +} +func (o *SLC_Type) GetSLC_RX_FIFO_PUSH_SLC_RXFIFO_WDATA() uint32 { + return volatile.LoadUint32(&o.SLC_RX_FIFO_PUSH.Reg) & 0x1ff +} + +// SLC.SLC_TX_STATUS: SLC_TX_STATUS +func (o *SLC_Type) SetSLC_TX_STATUS_SLC_TX_EMPTY(value uint32) { + volatile.StoreUint32(&o.SLC_TX_STATUS.Reg, volatile.LoadUint32(&o.SLC_TX_STATUS.Reg)&^(0x2)|value<<1) +} +func (o *SLC_Type) GetSLC_TX_STATUS_SLC_TX_EMPTY() uint32 { + return (volatile.LoadUint32(&o.SLC_TX_STATUS.Reg) & 0x2) >> 1 +} +func (o *SLC_Type) SetSLC_TX_STATUS_SLC_TX_FULL(value uint32) { + volatile.StoreUint32(&o.SLC_TX_STATUS.Reg, volatile.LoadUint32(&o.SLC_TX_STATUS.Reg)&^(0x1)|value) +} +func (o *SLC_Type) GetSLC_TX_STATUS_SLC_TX_FULL() uint32 { + return volatile.LoadUint32(&o.SLC_TX_STATUS.Reg) & 0x1 +} + +// SLC.SLC_TX_FIFO_POP: SLC_TX_FIFO_POP +func (o *SLC_Type) SetSLC_TX_FIFO_POP_SLC_TXFIFO_POP(value uint32) { + volatile.StoreUint32(&o.SLC_TX_FIFO_POP.Reg, volatile.LoadUint32(&o.SLC_TX_FIFO_POP.Reg)&^(0x10000)|value<<16) +} +func (o *SLC_Type) GetSLC_TX_FIFO_POP_SLC_TXFIFO_POP() uint32 { + return (volatile.LoadUint32(&o.SLC_TX_FIFO_POP.Reg) & 0x10000) >> 16 +} +func (o *SLC_Type) SetSLC_TX_FIFO_POP_SLC_TXFIFO_RDATA(value uint32) { + volatile.StoreUint32(&o.SLC_TX_FIFO_POP.Reg, volatile.LoadUint32(&o.SLC_TX_FIFO_POP.Reg)&^(0x7ff)|value) +} +func (o *SLC_Type) GetSLC_TX_FIFO_POP_SLC_TXFIFO_RDATA() uint32 { + return volatile.LoadUint32(&o.SLC_TX_FIFO_POP.Reg) & 0x7ff +} + +// SLC.SLC_RX_LINK: SLC_RX_LINK +func (o *SLC_Type) SetSLC_RX_LINK_SLC_RXLINK_PARK(value uint32) { + volatile.StoreUint32(&o.SLC_RX_LINK.Reg, volatile.LoadUint32(&o.SLC_RX_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *SLC_Type) GetSLC_RX_LINK_SLC_RXLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.SLC_RX_LINK.Reg) & 0x80000000) >> 31 +} +func (o *SLC_Type) SetSLC_RX_LINK_SLC_RXLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.SLC_RX_LINK.Reg, volatile.LoadUint32(&o.SLC_RX_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SLC_Type) GetSLC_RX_LINK_SLC_RXLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.SLC_RX_LINK.Reg) & 0x40000000) >> 30 +} +func (o *SLC_Type) SetSLC_RX_LINK_SLC_RXLINK_START(value uint32) { + volatile.StoreUint32(&o.SLC_RX_LINK.Reg, volatile.LoadUint32(&o.SLC_RX_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SLC_Type) GetSLC_RX_LINK_SLC_RXLINK_START() uint32 { + return (volatile.LoadUint32(&o.SLC_RX_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SLC_Type) SetSLC_RX_LINK_SLC_RXLINK_STOP(value uint32) { + volatile.StoreUint32(&o.SLC_RX_LINK.Reg, volatile.LoadUint32(&o.SLC_RX_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SLC_Type) GetSLC_RX_LINK_SLC_RXLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.SLC_RX_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SLC_Type) SetSLC_RX_LINK_SLC_RXLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.SLC_RX_LINK.Reg, volatile.LoadUint32(&o.SLC_RX_LINK.Reg)&^(0xfffff)|value) +} +func (o *SLC_Type) GetSLC_RX_LINK_SLC_RXLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.SLC_RX_LINK.Reg) & 0xfffff +} + +// SLC.SLC_TX_LINK: SLC_TX_LINK +func (o *SLC_Type) SetSLC_TX_LINK_SLC_TXLINK_PARK(value uint32) { + volatile.StoreUint32(&o.SLC_TX_LINK.Reg, volatile.LoadUint32(&o.SLC_TX_LINK.Reg)&^(0x80000000)|value<<31) +} +func (o *SLC_Type) GetSLC_TX_LINK_SLC_TXLINK_PARK() uint32 { + return (volatile.LoadUint32(&o.SLC_TX_LINK.Reg) & 0x80000000) >> 31 +} +func (o *SLC_Type) SetSLC_TX_LINK_SLC_TXLINK_RESTART(value uint32) { + volatile.StoreUint32(&o.SLC_TX_LINK.Reg, volatile.LoadUint32(&o.SLC_TX_LINK.Reg)&^(0x40000000)|value<<30) +} +func (o *SLC_Type) GetSLC_TX_LINK_SLC_TXLINK_RESTART() uint32 { + return (volatile.LoadUint32(&o.SLC_TX_LINK.Reg) & 0x40000000) >> 30 +} +func (o *SLC_Type) SetSLC_TX_LINK_SLC_TXLINK_START(value uint32) { + volatile.StoreUint32(&o.SLC_TX_LINK.Reg, volatile.LoadUint32(&o.SLC_TX_LINK.Reg)&^(0x20000000)|value<<29) +} +func (o *SLC_Type) GetSLC_TX_LINK_SLC_TXLINK_START() uint32 { + return (volatile.LoadUint32(&o.SLC_TX_LINK.Reg) & 0x20000000) >> 29 +} +func (o *SLC_Type) SetSLC_TX_LINK_SLC_TXLINK_STOP(value uint32) { + volatile.StoreUint32(&o.SLC_TX_LINK.Reg, volatile.LoadUint32(&o.SLC_TX_LINK.Reg)&^(0x10000000)|value<<28) +} +func (o *SLC_Type) GetSLC_TX_LINK_SLC_TXLINK_STOP() uint32 { + return (volatile.LoadUint32(&o.SLC_TX_LINK.Reg) & 0x10000000) >> 28 +} +func (o *SLC_Type) SetSLC_TX_LINK_SLC_TXLINK_ADDR(value uint32) { + volatile.StoreUint32(&o.SLC_TX_LINK.Reg, volatile.LoadUint32(&o.SLC_TX_LINK.Reg)&^(0xfffff)|value) +} +func (o *SLC_Type) GetSLC_TX_LINK_SLC_TXLINK_ADDR() uint32 { + return volatile.LoadUint32(&o.SLC_TX_LINK.Reg) & 0xfffff +} + +// SLC.SLC_INTVEC_TOHOST: SLC_INTVEC_TOHOST +func (o *SLC_Type) SetSLC_INTVEC_TOHOST_SLC_TOHOST_INTVEC(value uint32) { + volatile.StoreUint32(&o.SLC_INTVEC_TOHOST.Reg, volatile.LoadUint32(&o.SLC_INTVEC_TOHOST.Reg)&^(0xff)|value) +} +func (o *SLC_Type) GetSLC_INTVEC_TOHOST_SLC_TOHOST_INTVEC() uint32 { + return volatile.LoadUint32(&o.SLC_INTVEC_TOHOST.Reg) & 0xff +} + +// SLC.SLC_TOKEN0: SLC_TOKEN0 +func (o *SLC_Type) SetSLC_TOKEN0(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN0.Reg, volatile.LoadUint32(&o.SLC_TOKEN0.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLC_Type) GetSLC_TOKEN0() uint32 { + return (volatile.LoadUint32(&o.SLC_TOKEN0.Reg) & 0xfff0000) >> 16 +} +func (o *SLC_Type) SetSLC_TOKEN0_SLC_TOKEN0_LOCAL_INC_MORE(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN0.Reg, volatile.LoadUint32(&o.SLC_TOKEN0.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) GetSLC_TOKEN0_SLC_TOKEN0_LOCAL_INC_MORE() uint32 { + return (volatile.LoadUint32(&o.SLC_TOKEN0.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) SetSLC_TOKEN0_SLC_TOKEN0_LOCAL_INC(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN0.Reg, volatile.LoadUint32(&o.SLC_TOKEN0.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) GetSLC_TOKEN0_SLC_TOKEN0_LOCAL_INC() uint32 { + return (volatile.LoadUint32(&o.SLC_TOKEN0.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) SetSLC_TOKEN0_SLC_TOKEN0_LOCAL_WR(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN0.Reg, volatile.LoadUint32(&o.SLC_TOKEN0.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) GetSLC_TOKEN0_SLC_TOKEN0_LOCAL_WR() uint32 { + return (volatile.LoadUint32(&o.SLC_TOKEN0.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) SetSLC_TOKEN0_SLC_TOKEN0_LOCAL_WDATA(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN0.Reg, volatile.LoadUint32(&o.SLC_TOKEN0.Reg)&^(0xfff)|value) +} +func (o *SLC_Type) GetSLC_TOKEN0_SLC_TOKEN0_LOCAL_WDATA() uint32 { + return volatile.LoadUint32(&o.SLC_TOKEN0.Reg) & 0xfff +} + +// SLC.SLC_TOKEN1: SLC_TOKEN1 +func (o *SLC_Type) SetSLC_TOKEN1(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN1.Reg, volatile.LoadUint32(&o.SLC_TOKEN1.Reg)&^(0xfff0000)|value<<16) +} +func (o *SLC_Type) GetSLC_TOKEN1() uint32 { + return (volatile.LoadUint32(&o.SLC_TOKEN1.Reg) & 0xfff0000) >> 16 +} +func (o *SLC_Type) SetSLC_TOKEN1_SLC_TOKEN1_LOCAL_INC_MORE(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN1.Reg, volatile.LoadUint32(&o.SLC_TOKEN1.Reg)&^(0x4000)|value<<14) +} +func (o *SLC_Type) GetSLC_TOKEN1_SLC_TOKEN1_LOCAL_INC_MORE() uint32 { + return (volatile.LoadUint32(&o.SLC_TOKEN1.Reg) & 0x4000) >> 14 +} +func (o *SLC_Type) SetSLC_TOKEN1_SLC_TOKEN1_LOCAL_INC(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN1.Reg, volatile.LoadUint32(&o.SLC_TOKEN1.Reg)&^(0x2000)|value<<13) +} +func (o *SLC_Type) GetSLC_TOKEN1_SLC_TOKEN1_LOCAL_INC() uint32 { + return (volatile.LoadUint32(&o.SLC_TOKEN1.Reg) & 0x2000) >> 13 +} +func (o *SLC_Type) SetSLC_TOKEN1_SLC_TOKEN1_LOCAL_WR(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN1.Reg, volatile.LoadUint32(&o.SLC_TOKEN1.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) GetSLC_TOKEN1_SLC_TOKEN1_LOCAL_WR() uint32 { + return (volatile.LoadUint32(&o.SLC_TOKEN1.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) SetSLC_TOKEN1_SLC_TOKEN1_LOCAL_WDATA(value uint32) { + volatile.StoreUint32(&o.SLC_TOKEN1.Reg, volatile.LoadUint32(&o.SLC_TOKEN1.Reg)&^(0xfff)|value) +} +func (o *SLC_Type) GetSLC_TOKEN1_SLC_TOKEN1_LOCAL_WDATA() uint32 { + return volatile.LoadUint32(&o.SLC_TOKEN1.Reg) & 0xfff +} + +// SLC.SLC_CONF1: SLC_CONF1 +func (o *SLC_Type) SetSLC_CONF1(value uint32) { + volatile.StoreUint32(&o.SLC_CONF1.Reg, value) +} +func (o *SLC_Type) GetSLC_CONF1() uint32 { + return volatile.LoadUint32(&o.SLC_CONF1.Reg) +} + +// SLC.SLC_STATE0: SLC_STATE0 +func (o *SLC_Type) SetSLC_STATE0(value uint32) { + volatile.StoreUint32(&o.SLC_STATE0.Reg, value) +} +func (o *SLC_Type) GetSLC_STATE0() uint32 { + return volatile.LoadUint32(&o.SLC_STATE0.Reg) +} + +// SLC.SLC_STATE1: SLC_STATE1 +func (o *SLC_Type) SetSLC_STATE1(value uint32) { + volatile.StoreUint32(&o.SLC_STATE1.Reg, value) +} +func (o *SLC_Type) GetSLC_STATE1() uint32 { + return volatile.LoadUint32(&o.SLC_STATE1.Reg) +} + +// SLC.SLC_BRIDGE_CONF: SLC_BRIDGE_CONF +func (o *SLC_Type) SetSLC_BRIDGE_CONF_SLC_TX_PUSH_IDLE_NUM(value uint32) { + volatile.StoreUint32(&o.SLC_BRIDGE_CONF.Reg, volatile.LoadUint32(&o.SLC_BRIDGE_CONF.Reg)&^(0xffff0000)|value<<16) +} +func (o *SLC_Type) GetSLC_BRIDGE_CONF_SLC_TX_PUSH_IDLE_NUM() uint32 { + return (volatile.LoadUint32(&o.SLC_BRIDGE_CONF.Reg) & 0xffff0000) >> 16 +} +func (o *SLC_Type) SetSLC_BRIDGE_CONF_SLC_TX_DUMMY_MODE(value uint32) { + volatile.StoreUint32(&o.SLC_BRIDGE_CONF.Reg, volatile.LoadUint32(&o.SLC_BRIDGE_CONF.Reg)&^(0x1000)|value<<12) +} +func (o *SLC_Type) GetSLC_BRIDGE_CONF_SLC_TX_DUMMY_MODE() uint32 { + return (volatile.LoadUint32(&o.SLC_BRIDGE_CONF.Reg) & 0x1000) >> 12 +} +func (o *SLC_Type) SetSLC_BRIDGE_CONF_SLC_FIFO_MAP_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_BRIDGE_CONF.Reg, volatile.LoadUint32(&o.SLC_BRIDGE_CONF.Reg)&^(0xf00)|value<<8) +} +func (o *SLC_Type) GetSLC_BRIDGE_CONF_SLC_FIFO_MAP_ENA() uint32 { + return (volatile.LoadUint32(&o.SLC_BRIDGE_CONF.Reg) & 0xf00) >> 8 +} +func (o *SLC_Type) SetSLC_BRIDGE_CONF_SLC_TXEOF_ENA(value uint32) { + volatile.StoreUint32(&o.SLC_BRIDGE_CONF.Reg, volatile.LoadUint32(&o.SLC_BRIDGE_CONF.Reg)&^(0x3f)|value) +} +func (o *SLC_Type) GetSLC_BRIDGE_CONF_SLC_TXEOF_ENA() uint32 { + return volatile.LoadUint32(&o.SLC_BRIDGE_CONF.Reg) & 0x3f +} + +// SLC.SLC_RX_EOF_DES_ADDR: SLC_RX_EOF_DES_ADDR +func (o *SLC_Type) SetSLC_RX_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.SLC_RX_EOF_DES_ADDR.Reg, value) +} +func (o *SLC_Type) GetSLC_RX_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.SLC_RX_EOF_DES_ADDR.Reg) +} + +// SLC.SLC_TX_EOF_DES_ADDR: SLC_TX_EOF_DES_ADDR +func (o *SLC_Type) SetSLC_TX_EOF_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.SLC_TX_EOF_DES_ADDR.Reg, value) +} +func (o *SLC_Type) GetSLC_TX_EOF_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.SLC_TX_EOF_DES_ADDR.Reg) +} + +// SLC.SLC_RX_EOF_BFR_DES_ADDR: SLC_RX_EOF_BFR_DES_ADDR +func (o *SLC_Type) SetSLC_RX_EOF_BFR_DES_ADDR(value uint32) { + volatile.StoreUint32(&o.SLC_RX_EOF_BFR_DES_ADDR.Reg, value) +} +func (o *SLC_Type) GetSLC_RX_EOF_BFR_DES_ADDR() uint32 { + return volatile.LoadUint32(&o.SLC_RX_EOF_BFR_DES_ADDR.Reg) +} + +// SLC.SLC_AHB_TEST: SLC_AHB_TEST +func (o *SLC_Type) SetSLC_AHB_TEST_SLC_AHB_TESTADDR(value uint32) { + volatile.StoreUint32(&o.SLC_AHB_TEST.Reg, volatile.LoadUint32(&o.SLC_AHB_TEST.Reg)&^(0x30)|value<<4) +} +func (o *SLC_Type) GetSLC_AHB_TEST_SLC_AHB_TESTADDR() uint32 { + return (volatile.LoadUint32(&o.SLC_AHB_TEST.Reg) & 0x30) >> 4 +} +func (o *SLC_Type) SetSLC_AHB_TEST_SLC_AHB_TESTMODE(value uint32) { + volatile.StoreUint32(&o.SLC_AHB_TEST.Reg, volatile.LoadUint32(&o.SLC_AHB_TEST.Reg)&^(0x7)|value) +} +func (o *SLC_Type) GetSLC_AHB_TEST_SLC_AHB_TESTMODE() uint32 { + return volatile.LoadUint32(&o.SLC_AHB_TEST.Reg) & 0x7 +} + +// SLC.SLC_SDIO_ST: SLC_SDIO_ST +func (o *SLC_Type) SetSLC_SDIO_ST_SLC_BUS_ST(value uint32) { + volatile.StoreUint32(&o.SLC_SDIO_ST.Reg, volatile.LoadUint32(&o.SLC_SDIO_ST.Reg)&^(0x7000)|value<<12) +} +func (o *SLC_Type) GetSLC_SDIO_ST_SLC_BUS_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_SDIO_ST.Reg) & 0x7000) >> 12 +} +func (o *SLC_Type) SetSLC_SDIO_ST_SLC_SDIO_WAKEUP(value uint32) { + volatile.StoreUint32(&o.SLC_SDIO_ST.Reg, volatile.LoadUint32(&o.SLC_SDIO_ST.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) GetSLC_SDIO_ST_SLC_SDIO_WAKEUP() uint32 { + return (volatile.LoadUint32(&o.SLC_SDIO_ST.Reg) & 0x100) >> 8 +} +func (o *SLC_Type) SetSLC_SDIO_ST_SLC_FUNC_ST(value uint32) { + volatile.StoreUint32(&o.SLC_SDIO_ST.Reg, volatile.LoadUint32(&o.SLC_SDIO_ST.Reg)&^(0xf0)|value<<4) +} +func (o *SLC_Type) GetSLC_SDIO_ST_SLC_FUNC_ST() uint32 { + return (volatile.LoadUint32(&o.SLC_SDIO_ST.Reg) & 0xf0) >> 4 +} +func (o *SLC_Type) SetSLC_SDIO_ST_SLC_CMD_ST(value uint32) { + volatile.StoreUint32(&o.SLC_SDIO_ST.Reg, volatile.LoadUint32(&o.SLC_SDIO_ST.Reg)&^(0x7)|value) +} +func (o *SLC_Type) GetSLC_SDIO_ST_SLC_CMD_ST() uint32 { + return volatile.LoadUint32(&o.SLC_SDIO_ST.Reg) & 0x7 +} + +// SLC.SLC_RX_DSCR_CONF: SLC_RX_DSCR_CONF +func (o *SLC_Type) SetSLC_RX_DSCR_CONF_SLC_INFOR_NO_REPLACE(value uint32) { + volatile.StoreUint32(&o.SLC_RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.SLC_RX_DSCR_CONF.Reg)&^(0x200)|value<<9) +} +func (o *SLC_Type) GetSLC_RX_DSCR_CONF_SLC_INFOR_NO_REPLACE() uint32 { + return (volatile.LoadUint32(&o.SLC_RX_DSCR_CONF.Reg) & 0x200) >> 9 +} +func (o *SLC_Type) SetSLC_RX_DSCR_CONF_SLC_TOKEN_NO_REPLACE(value uint32) { + volatile.StoreUint32(&o.SLC_RX_DSCR_CONF.Reg, volatile.LoadUint32(&o.SLC_RX_DSCR_CONF.Reg)&^(0x100)|value<<8) +} +func (o *SLC_Type) GetSLC_RX_DSCR_CONF_SLC_TOKEN_NO_REPLACE() uint32 { + return (volatile.LoadUint32(&o.SLC_RX_DSCR_CONF.Reg) & 0x100) >> 8 +} + +// SLC.SLC_TXLINK_DSCR: SLC_TXLINK_DSCR +func (o *SLC_Type) SetSLC_TXLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.SLC_TXLINK_DSCR.Reg, value) +} +func (o *SLC_Type) GetSLC_TXLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.SLC_TXLINK_DSCR.Reg) +} + +// SLC.SLC_TXLINK_DSCR_BF0: SLC_TXLINK_DSCR_BF0 +func (o *SLC_Type) SetSLC_TXLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.SLC_TXLINK_DSCR_BF0.Reg, value) +} +func (o *SLC_Type) GetSLC_TXLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.SLC_TXLINK_DSCR_BF0.Reg) +} + +// SLC.SLC_TXLINK_DSCR_BF1: SLC_TXLINK_DSCR_BF1 +func (o *SLC_Type) SetSLC_TXLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.SLC_TXLINK_DSCR_BF1.Reg, value) +} +func (o *SLC_Type) GetSLC_TXLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.SLC_TXLINK_DSCR_BF1.Reg) +} + +// SLC.SLC_RXLINK_DSCR: SLC_RXLINK_DSCR +func (o *SLC_Type) SetSLC_RXLINK_DSCR(value uint32) { + volatile.StoreUint32(&o.SLC_RXLINK_DSCR.Reg, value) +} +func (o *SLC_Type) GetSLC_RXLINK_DSCR() uint32 { + return volatile.LoadUint32(&o.SLC_RXLINK_DSCR.Reg) +} + +// SLC.SLC_RXLINK_DSCR_BF0: SLC_RXLINK_DSCR_BF0 +func (o *SLC_Type) SetSLC_RXLINK_DSCR_BF0(value uint32) { + volatile.StoreUint32(&o.SLC_RXLINK_DSCR_BF0.Reg, value) +} +func (o *SLC_Type) GetSLC_RXLINK_DSCR_BF0() uint32 { + return volatile.LoadUint32(&o.SLC_RXLINK_DSCR_BF0.Reg) +} + +// SLC.SLC_RXLINK_DSCR_BF1: SLC_RXLINK_DSCR_BF1 +func (o *SLC_Type) SetSLC_RXLINK_DSCR_BF1(value uint32) { + volatile.StoreUint32(&o.SLC_RXLINK_DSCR_BF1.Reg, value) +} +func (o *SLC_Type) GetSLC_RXLINK_DSCR_BF1() uint32 { + return volatile.LoadUint32(&o.SLC_RXLINK_DSCR_BF1.Reg) +} + +// SLC.SLC_DATE: SLC_DATE +func (o *SLC_Type) SetSLC_DATE(value uint32) { + volatile.StoreUint32(&o.SLC_DATE.Reg, value) +} +func (o *SLC_Type) GetSLC_DATE() uint32 { + return volatile.LoadUint32(&o.SLC_DATE.Reg) +} + +// SLC.SLC_ID: SLC_ID +func (o *SLC_Type) SetSLC_ID(value uint32) { + volatile.StoreUint32(&o.SLC_ID.Reg, value) +} +func (o *SLC_Type) GetSLC_ID() uint32 { + return volatile.LoadUint32(&o.SLC_ID.Reg) +} + +type SPI0_Type struct { + SPI_CMD volatile.Register32 // 0x0 + SPI_ADDR volatile.Register32 // 0x4 + SPI_CTRL volatile.Register32 // 0x8 + SPI_CTRL1 volatile.Register32 // 0xC + SPI_RD_STATUS volatile.Register32 // 0x10 + SPI_CTRL2 volatile.Register32 // 0x14 + SPI_CLOCK volatile.Register32 // 0x18 + SPI_USER volatile.Register32 // 0x1C + SPI_USER1 volatile.Register32 // 0x20 + SPI_USER2 volatile.Register32 // 0x24 + SPI_WR_STATUS volatile.Register32 // 0x28 + SPI_PIN volatile.Register32 // 0x2C + SPI_SLAVE volatile.Register32 // 0x30 + SPI_SLAVE1 volatile.Register32 // 0x34 + SPI_SLAVE2 volatile.Register32 // 0x38 + SPI_SLAVE3 volatile.Register32 // 0x3C + SPI_W0 volatile.Register32 // 0x40 + _ [28]byte + SPI_W1 volatile.Register32 // 0x60 + _ [28]byte + SPI_W2 volatile.Register32 // 0x80 + _ [28]byte + SPI_W3 volatile.Register32 // 0xA0 + _ [28]byte + SPI_W4 volatile.Register32 // 0xC0 + _ [28]byte + SPI_W5 volatile.Register32 // 0xE0 + _ [24]byte + SPI_EXT3 volatile.Register32 // 0xFC + SPI_W6 volatile.Register32 // 0x100 + _ [28]byte + SPI_W7 volatile.Register32 // 0x120 + _ [28]byte + SPI_W8 volatile.Register32 // 0x140 + _ [28]byte + SPI_W9 volatile.Register32 // 0x160 + _ [28]byte + SPI_W10 volatile.Register32 // 0x180 + _ [28]byte + SPI_W11 volatile.Register32 // 0x1A0 + _ [28]byte + SPI_W12 volatile.Register32 // 0x1C0 + _ [28]byte + SPI_W13 volatile.Register32 // 0x1E0 + _ [28]byte + SPI_W14 volatile.Register32 // 0x200 + _ [28]byte + SPI_W15 volatile.Register32 // 0x220 +} + +// SPI0.SPI_CMD: In the master mode, it is the start bit of a single operation. Self-clear by hardware +func (o *SPI0_Type) SetSPI_CMD_SPI_USR(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_READ(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_READ() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x80000000) >> 31 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_WRITE_ENABLE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_WRITE_ENABLE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_WRITE_DISABLE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_WRITE_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_READ_ID(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_READ_ID() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_READ_SR(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_READ_SR() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_WRITE_SR(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_WRITE_SR() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_PP(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_PP() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_SE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_SE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_BE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_BE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_CE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_CE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_DP(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_DP() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_RES(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_RES() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_CMD_SPI_HPM(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI0_Type) GetSPI_CMD_SPI_HPM() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x80000) >> 19 +} + +// SPI0.SPI_ADDR: In the master mode, it is the value of address in "address" phase. +func (o *SPI0_Type) SetSPI_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_ADDR.Reg, value) +} +func (o *SPI0_Type) GetSPI_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_ADDR.Reg) +} +func (o *SPI0_Type) SetSPI_ADDR_ADDRESS(value uint32) { + volatile.StoreUint32(&o.SPI_ADDR.Reg, volatile.LoadUint32(&o.SPI_ADDR.Reg)&^(0xffffff)|value) +} +func (o *SPI0_Type) GetSPI_ADDR_ADDRESS() uint32 { + return volatile.LoadUint32(&o.SPI_ADDR.Reg) & 0xffffff +} +func (o *SPI0_Type) SetSPI_ADDR_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_ADDR.Reg, volatile.LoadUint32(&o.SPI_ADDR.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_ADDR_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_ADDR.Reg) & 0xff000000) >> 24 +} + +// SPI0.SPI_CTRL: SPI_CTRL +func (o *SPI0_Type) SetSPI_CTRL_SPI_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_CTRL_SPI_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *SPI0_Type) SetSPI_CTRL_SPI_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_CTRL_SPI_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_CTRL_SPI_QIO_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_CTRL_SPI_QIO_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_CTRL_SPI_DIO_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_CTRL_SPI_DIO_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI0_Type) SetSPI_CTRL_SPI_QOUT_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI0_Type) GetSPI_CTRL_SPI_QOUT_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI0_Type) SetSPI_CTRL_SPI_DOUT_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_CTRL_SPI_DOUT_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_CTRL_SPI_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_CTRL_SPI_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x2000) >> 13 +} + +// SPI0.SPI_CTRL1 +func (o *SPI0_Type) SetSPI_CTRL1_STATUS(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL1.Reg, volatile.LoadUint32(&o.SPI_CTRL1.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_CTRL1_STATUS() uint32 { + return volatile.LoadUint32(&o.SPI_CTRL1.Reg) & 0xffff +} +func (o *SPI0_Type) SetSPI_CTRL1_WB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL1.Reg, volatile.LoadUint32(&o.SPI_CTRL1.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_CTRL1_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL1.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_CTRL1_STATUS_EXT(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL1.Reg, volatile.LoadUint32(&o.SPI_CTRL1.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_CTRL1_STATUS_EXT() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL1.Reg) & 0xff000000) >> 24 +} + +// SPI0.SPI_RD_STATUS: In the slave mode, this register are the status register for the master to read out. +func (o *SPI0_Type) SetSPI_RD_STATUS(value uint32) { + volatile.StoreUint32(&o.SPI_RD_STATUS.Reg, value) +} +func (o *SPI0_Type) GetSPI_RD_STATUS() uint32 { + return volatile.LoadUint32(&o.SPI_RD_STATUS.Reg) +} + +// SPI0.SPI_CTRL2: spi_cs signal is delayed by 80MHz clock cycles +func (o *SPI0_Type) SetSPI_CTRL2_SPI_CS_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_CTRL2_SPI_CS_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0xf0000000) >> 28 +} +func (o *SPI0_Type) SetSPI_CTRL2_SPI_CS_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0xc000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_CTRL2_SPI_CS_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0xc000000) >> 26 +} +func (o *SPI0_Type) SetSPI_CTRL2_SPI_MOSI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0x3800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_CTRL2_SPI_MOSI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0x3800000) >> 23 +} +func (o *SPI0_Type) SetSPI_CTRL2_SPI_MOSI_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0x600000)|value<<21) +} +func (o *SPI0_Type) GetSPI_CTRL2_SPI_MOSI_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0x600000) >> 21 +} +func (o *SPI0_Type) SetSPI_CTRL2_SPI_MISO_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_CTRL2_SPI_MISO_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0x1c0000) >> 18 +} +func (o *SPI0_Type) SetSPI_CTRL2_SPI_MISO_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0x30000)|value<<16) +} +func (o *SPI0_Type) GetSPI_CTRL2_SPI_MISO_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0x30000) >> 16 +} + +// SPI0.SPI_CLOCK: In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. +func (o *SPI0_Type) SetSPI_CLOCK_SPI_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_CLOCK_SPI_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x80000000) >> 31 +} +func (o *SPI0_Type) SetSPI_CLOCK_SPI_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *SPI0_Type) GetSPI_CLOCK_SPI_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x7ffc0000) >> 18 +} +func (o *SPI0_Type) SetSPI_CLOCK_SPI_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI0_Type) GetSPI_CLOCK_SPI_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI0_Type) SetSPI_CLOCK_SPI_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI0_Type) GetSPI_CLOCK_SPI_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI0_Type) SetSPI_CLOCK_SPI_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI0_Type) GetSPI_CLOCK_SPI_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f +} + +// SPI0.SPI_USER: This bit enable the "command" phase of an operation. +func (o *SPI0_Type) SetSPI_USER_SPI_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_USER_SPI_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80000000) >> 31 +} +func (o *SPI0_Type) SetSPI_USER_SPI_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_USER_SPI_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_USER_SPI_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_USER_SPI_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI0_Type) SetSPI_USER_SPI_USR_MISO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_USER_SPI_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI0_Type) SetSPI_USER_SPI_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_USER_SPI_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_USER_REG_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI0_Type) GetSPI_USER_REG_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI0_Type) SetSPI_USER_REG_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_USER_REG_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI0_Type) SetSPI_USER_SPI_SIO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10000)|value<<16) +} +func (o *SPI0_Type) GetSPI_USER_SPI_SIO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10000) >> 16 +} +func (o *SPI0_Type) SetSPI_USER_SPI_FWRITE_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI0_Type) GetSPI_USER_SPI_FWRITE_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000) >> 15 +} +func (o *SPI0_Type) SetSPI_USER_SPI_FWRITE_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI0_Type) GetSPI_USER_SPI_FWRITE_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4000) >> 14 +} +func (o *SPI0_Type) SetSPI_USER_SPI_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI0_Type) GetSPI_USER_SPI_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000) >> 13 +} +func (o *SPI0_Type) SetSPI_USER_SPI_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI0_Type) GetSPI_USER_SPI_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000) >> 12 +} +func (o *SPI0_Type) SetSPI_USER_SPI_WR_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x800)|value<<11) +} +func (o *SPI0_Type) GetSPI_USER_SPI_WR_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x800) >> 11 +} +func (o *SPI0_Type) SetSPI_USER_SPI_RD_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x400)|value<<10) +} +func (o *SPI0_Type) GetSPI_USER_SPI_RD_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x400) >> 10 +} +func (o *SPI0_Type) SetSPI_USER_SPI_CK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI0_Type) GetSPI_USER_SPI_CK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40) >> 6 +} +func (o *SPI0_Type) SetSPI_USER_SPI_CK_O_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI0_Type) GetSPI_USER_SPI_CK_O_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80) >> 7 +} +func (o *SPI0_Type) SetSPI_USER_SPI_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI0_Type) GetSPI_USER_SPI_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20) >> 5 +} +func (o *SPI0_Type) SetSPI_USER_SPI_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_USER_SPI_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_USER_SPI_AHB_USER_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_USER_SPI_AHB_USER_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_USER_SPI_FLASH_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_USER_SPI_FLASH_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_USER_SPI_AHB_USER_COMMAND_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_USER_SPI_AHB_USER_COMMAND_4BYTE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_USER_SPI_DUPLEX(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_USER_SPI_DUPLEX() uint32 { + return volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1 +} + +// SPI0.SPI_USER1: The length in bits of "address" phase. The register value shall be (bit_num-1) +func (o *SPI0_Type) SetSPI_USER1_REG_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI0_Type) GetSPI_USER1_REG_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xfc000000) >> 26 +} +func (o *SPI0_Type) SetSPI_USER1_REG_USR_MOSI_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x3fe0000)|value<<17) +} +func (o *SPI0_Type) GetSPI_USER1_REG_USR_MOSI_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x3fe0000) >> 17 +} +func (o *SPI0_Type) SetSPI_USER1_REG_USR_MISO_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x1ff00)|value<<8) +} +func (o *SPI0_Type) GetSPI_USER1_REG_USR_MISO_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x1ff00) >> 8 +} +func (o *SPI0_Type) SetSPI_USER1_REG_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSPI_USER1_REG_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xff +} + +// SPI0.SPI_USER2: The length in bits of "command" phase. The register value shall be (bit_num-1) +func (o *SPI0_Type) SetSPI_USER2_REG_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI0_Type) GetSPI_USER2_REG_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xf0000000) >> 28 +} +func (o *SPI0_Type) SetSPI_USER2_REG_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI0_Type) GetSPI_USER2_REG_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xffff +} + +// SPI0.SPI_WR_STATUS: In the slave mode, this register are the status register for the master to write into. +func (o *SPI0_Type) SetSPI_WR_STATUS(value uint32) { + volatile.StoreUint32(&o.SPI_WR_STATUS.Reg, value) +} +func (o *SPI0_Type) GetSPI_WR_STATUS() uint32 { + return volatile.LoadUint32(&o.SPI_WR_STATUS.Reg) +} + +// SPI0.SPI_PIN: 1: disable CS2; 0: spi_cs signal is from/to CS2 pin +func (o *SPI0_Type) SetSPI_PIN_SPI_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_PIN.Reg, volatile.LoadUint32(&o.SPI_PIN.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_PIN_SPI_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_PIN.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_PIN_SPI_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_PIN.Reg, volatile.LoadUint32(&o.SPI_PIN.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_PIN_SPI_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_PIN.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_PIN_SPI_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_PIN.Reg, volatile.LoadUint32(&o.SPI_PIN.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_PIN_SPI_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.SPI_PIN.Reg) & 0x1 +} +func (o *SPI0_Type) SetSPI_PIN_SPI_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_PIN.Reg, volatile.LoadUint32(&o.SPI_PIN.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI0_Type) GetSPI_PIN_SPI_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_PIN.Reg) & 0x20000000) >> 29 +} + +// SPI0.SPI_SLAVE: It is the synchronous reset signal of the module. This bit is self-cleared by hardware. +func (o *SPI0_Type) SetSPI_SLAVE_SPI_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI0_Type) GetSPI_SLAVE_SPI_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x80000000) >> 31 +} +func (o *SPI0_Type) SetSPI_SLAVE_SPI_SLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI0_Type) GetSPI_SLAVE_SPI_SLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x40000000) >> 30 +} +func (o *SPI0_Type) SetSPI_SLAVE_SLV_CMD_DEFINE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_SLAVE_SLV_CMD_DEFINE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_SLAVE_SPI_TRANS_CNT(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x7800000)|value<<23) +} +func (o *SPI0_Type) GetSPI_SLAVE_SPI_TRANS_CNT() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x7800000) >> 23 +} +func (o *SPI0_Type) SetSPI_SLAVE_SPI_INT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x3e0)|value<<5) +} +func (o *SPI0_Type) GetSPI_SLAVE_SPI_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x3e0) >> 5 +} +func (o *SPI0_Type) SetSPI_SLAVE_SPI_TRANS_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x10)|value<<4) +} +func (o *SPI0_Type) GetSPI_SLAVE_SPI_TRANS_DONE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x10) >> 4 +} +func (o *SPI0_Type) SetSPI_SLAVE_SLV_WR_STA_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SLAVE_SLV_WR_STA_DONE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SLAVE_SLV_RD_STA_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SLAVE_SLV_RD_STA_DONE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SLAVE_SLV_WR_BUF_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SLAVE_SLV_WR_BUF_DONE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SLAVE_SLV_RD_BUF_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SLAVE_SLV_RD_BUF_DONE() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x1 +} + +// SPI0.SPI_SLAVE1: In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) +func (o *SPI0_Type) SetSPI_SLAVE1_SLV_STATUS_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI0_Type) GetSPI_SLAVE1_SLV_STATUS_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0xf8000000) >> 27 +} +func (o *SPI0_Type) SetSPI_SLAVE1_SLV_BUF_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x1ff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SLAVE1_SLV_BUF_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x1ff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_SLAVE1_SLV_RD_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0xfc00)|value<<10) +} +func (o *SPI0_Type) GetSPI_SLAVE1_SLV_RD_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0xfc00) >> 10 +} +func (o *SPI0_Type) SetSPI_SLAVE1_SLV_WR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3f0)|value<<4) +} +func (o *SPI0_Type) GetSPI_SLAVE1_SLV_WR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3f0) >> 4 +} +func (o *SPI0_Type) SetSPI_SLAVE1_SLV_WRSTA_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x8)|value<<3) +} +func (o *SPI0_Type) GetSPI_SLAVE1_SLV_WRSTA_DUMMY_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x8) >> 3 +} +func (o *SPI0_Type) SetSPI_SLAVE1_SLV_RDSTA_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x4)|value<<2) +} +func (o *SPI0_Type) GetSPI_SLAVE1_SLV_RDSTA_DUMMY_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x4) >> 2 +} +func (o *SPI0_Type) SetSPI_SLAVE1_SLV_WRBUF_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x2)|value<<1) +} +func (o *SPI0_Type) GetSPI_SLAVE1_SLV_WRBUF_DUMMY_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x2) >> 1 +} +func (o *SPI0_Type) SetSPI_SLAVE1_SLV_RDBUF_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x1)|value) +} +func (o *SPI0_Type) GetSPI_SLAVE1_SLV_RDBUF_DUMMY_EN() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x1 +} + +// SPI0.SPI_SLAVE2: In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) +func (o *SPI0_Type) SetSPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE2.Reg, volatile.LoadUint32(&o.SPI_SLAVE2.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE2.Reg) & 0xff000000) >> 24 +} +func (o *SPI0_Type) SetSPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE2.Reg, volatile.LoadUint32(&o.SPI_SLAVE2.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE2.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE2.Reg, volatile.LoadUint32(&o.SPI_SLAVE2.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetSPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE2.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetSPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE2.Reg, volatile.LoadUint32(&o.SPI_SLAVE2.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE2.Reg) & 0xff +} + +// SPI0.SPI_SLAVE3: In slave mode, it is the value of "write-status" command +func (o *SPI0_Type) SetSPI_SLAVE3_SLV_WRSTA_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE3.Reg, volatile.LoadUint32(&o.SPI_SLAVE3.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI0_Type) GetSPI_SLAVE3_SLV_WRSTA_CMD_VALUE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE3.Reg) & 0xff000000) >> 24 +} +func (o *SPI0_Type) SetSPI_SLAVE3_SLV_RDSTA_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE3.Reg, volatile.LoadUint32(&o.SPI_SLAVE3.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI0_Type) GetSPI_SLAVE3_SLV_RDSTA_CMD_VALUE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE3.Reg) & 0xff0000) >> 16 +} +func (o *SPI0_Type) SetSPI_SLAVE3_SLV_WRBUF_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE3.Reg, volatile.LoadUint32(&o.SPI_SLAVE3.Reg)&^(0xff00)|value<<8) +} +func (o *SPI0_Type) GetSPI_SLAVE3_SLV_WRBUF_CMD_VALUE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE3.Reg) & 0xff00) >> 8 +} +func (o *SPI0_Type) SetSPI_SLAVE3_SLV_RDBUF_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE3.Reg, volatile.LoadUint32(&o.SPI_SLAVE3.Reg)&^(0xff)|value) +} +func (o *SPI0_Type) GetSPI_SLAVE3_SLV_RDBUF_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE3.Reg) & 0xff +} + +// SPI0.SPI_W0: the data inside the buffer of the SPI module, byte 0 +func (o *SPI0_Type) SetSPI_W0(value uint32) { + volatile.StoreUint32(&o.SPI_W0.Reg, value) +} +func (o *SPI0_Type) GetSPI_W0() uint32 { + return volatile.LoadUint32(&o.SPI_W0.Reg) +} + +// SPI0.SPI_W1: the data inside the buffer of the SPI module, byte 1 +func (o *SPI0_Type) SetSPI_W1(value uint32) { + volatile.StoreUint32(&o.SPI_W1.Reg, value) +} +func (o *SPI0_Type) GetSPI_W1() uint32 { + return volatile.LoadUint32(&o.SPI_W1.Reg) +} + +// SPI0.SPI_W2: the data inside the buffer of the SPI module, byte 2 +func (o *SPI0_Type) SetSPI_W2(value uint32) { + volatile.StoreUint32(&o.SPI_W2.Reg, value) +} +func (o *SPI0_Type) GetSPI_W2() uint32 { + return volatile.LoadUint32(&o.SPI_W2.Reg) +} + +// SPI0.SPI_W3: the data inside the buffer of the SPI module, byte 3 +func (o *SPI0_Type) SetSPI_W3(value uint32) { + volatile.StoreUint32(&o.SPI_W3.Reg, value) +} +func (o *SPI0_Type) GetSPI_W3() uint32 { + return volatile.LoadUint32(&o.SPI_W3.Reg) +} + +// SPI0.SPI_W4: the data inside the buffer of the SPI module, byte 4 +func (o *SPI0_Type) SetSPI_W4(value uint32) { + volatile.StoreUint32(&o.SPI_W4.Reg, value) +} +func (o *SPI0_Type) GetSPI_W4() uint32 { + return volatile.LoadUint32(&o.SPI_W4.Reg) +} + +// SPI0.SPI_W5: the data inside the buffer of the SPI module, byte 5 +func (o *SPI0_Type) SetSPI_W5(value uint32) { + volatile.StoreUint32(&o.SPI_W5.Reg, value) +} +func (o *SPI0_Type) GetSPI_W5() uint32 { + return volatile.LoadUint32(&o.SPI_W5.Reg) +} + +// SPI0.SPI_EXT3: This register is for two SPI masters to share the same cs, clock and data signals. +func (o *SPI0_Type) SetSPI_EXT3_REG_INT_HOLD_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_EXT3.Reg, volatile.LoadUint32(&o.SPI_EXT3.Reg)&^(0x3)|value) +} +func (o *SPI0_Type) GetSPI_EXT3_REG_INT_HOLD_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_EXT3.Reg) & 0x3 +} + +// SPI0.SPI_W6: the data inside the buffer of the SPI module, byte 6 +func (o *SPI0_Type) SetSPI_W6(value uint32) { + volatile.StoreUint32(&o.SPI_W6.Reg, value) +} +func (o *SPI0_Type) GetSPI_W6() uint32 { + return volatile.LoadUint32(&o.SPI_W6.Reg) +} + +// SPI0.SPI_W7: the data inside the buffer of the SPI module, byte 7 +func (o *SPI0_Type) SetSPI_W7(value uint32) { + volatile.StoreUint32(&o.SPI_W7.Reg, value) +} +func (o *SPI0_Type) GetSPI_W7() uint32 { + return volatile.LoadUint32(&o.SPI_W7.Reg) +} + +// SPI0.SPI_W8: the data inside the buffer of the SPI module, byte 8 +func (o *SPI0_Type) SetSPI_W8(value uint32) { + volatile.StoreUint32(&o.SPI_W8.Reg, value) +} +func (o *SPI0_Type) GetSPI_W8() uint32 { + return volatile.LoadUint32(&o.SPI_W8.Reg) +} + +// SPI0.SPI_W9: the data inside the buffer of the SPI module, byte 9 +func (o *SPI0_Type) SetSPI_W9(value uint32) { + volatile.StoreUint32(&o.SPI_W9.Reg, value) +} +func (o *SPI0_Type) GetSPI_W9() uint32 { + return volatile.LoadUint32(&o.SPI_W9.Reg) +} + +// SPI0.SPI_W10: the data inside the buffer of the SPI module, byte 10 +func (o *SPI0_Type) SetSPI_W10(value uint32) { + volatile.StoreUint32(&o.SPI_W10.Reg, value) +} +func (o *SPI0_Type) GetSPI_W10() uint32 { + return volatile.LoadUint32(&o.SPI_W10.Reg) +} + +// SPI0.SPI_W11: the data inside the buffer of the SPI module, byte 11 +func (o *SPI0_Type) SetSPI_W11(value uint32) { + volatile.StoreUint32(&o.SPI_W11.Reg, value) +} +func (o *SPI0_Type) GetSPI_W11() uint32 { + return volatile.LoadUint32(&o.SPI_W11.Reg) +} + +// SPI0.SPI_W12: the data inside the buffer of the SPI module, byte 12 +func (o *SPI0_Type) SetSPI_W12(value uint32) { + volatile.StoreUint32(&o.SPI_W12.Reg, value) +} +func (o *SPI0_Type) GetSPI_W12() uint32 { + return volatile.LoadUint32(&o.SPI_W12.Reg) +} + +// SPI0.SPI_W13: the data inside the buffer of the SPI module, byte 13 +func (o *SPI0_Type) SetSPI_W13(value uint32) { + volatile.StoreUint32(&o.SPI_W13.Reg, value) +} +func (o *SPI0_Type) GetSPI_W13() uint32 { + return volatile.LoadUint32(&o.SPI_W13.Reg) +} + +// SPI0.SPI_W14: the data inside the buffer of the SPI module, byte 14 +func (o *SPI0_Type) SetSPI_W14(value uint32) { + volatile.StoreUint32(&o.SPI_W14.Reg, value) +} +func (o *SPI0_Type) GetSPI_W14() uint32 { + return volatile.LoadUint32(&o.SPI_W14.Reg) +} + +// SPI0.SPI_W15: the data inside the buffer of the SPI module, byte 15 +func (o *SPI0_Type) SetSPI_W15(value uint32) { + volatile.StoreUint32(&o.SPI_W15.Reg, value) +} +func (o *SPI0_Type) GetSPI_W15() uint32 { + return volatile.LoadUint32(&o.SPI_W15.Reg) +} + +type SPI1_Type struct { + SPI_CMD volatile.Register32 // 0x0 + SPI_ADDR volatile.Register32 // 0x4 + SPI_CTRL volatile.Register32 // 0x8 + SPI_CTRL1 volatile.Register32 // 0xC + SPI_RD_STATUS volatile.Register32 // 0x10 + SPI_CTRL2 volatile.Register32 // 0x14 + SPI_CLOCK volatile.Register32 // 0x18 + SPI_USER volatile.Register32 // 0x1C + SPI_USER1 volatile.Register32 // 0x20 + SPI_USER2 volatile.Register32 // 0x24 + SPI_WR_STATUS volatile.Register32 // 0x28 + SPI_PIN volatile.Register32 // 0x2C + SPI_SLAVE volatile.Register32 // 0x30 + SPI_SLAVE1 volatile.Register32 // 0x34 + SPI_SLAVE2 volatile.Register32 // 0x38 + SPI_SLAVE3 volatile.Register32 // 0x3C + SPI_W0 volatile.Register32 // 0x40 + _ [28]byte + SPI_W1 volatile.Register32 // 0x60 + _ [28]byte + SPI_W2 volatile.Register32 // 0x80 + _ [28]byte + SPI_W3 volatile.Register32 // 0xA0 + _ [28]byte + SPI_W4 volatile.Register32 // 0xC0 + _ [28]byte + SPI_W5 volatile.Register32 // 0xE0 + _ [24]byte + SPI_EXT3 volatile.Register32 // 0xFC + SPI_W6 volatile.Register32 // 0x100 + _ [28]byte + SPI_W7 volatile.Register32 // 0x120 + _ [28]byte + SPI_W8 volatile.Register32 // 0x140 + _ [28]byte + SPI_W9 volatile.Register32 // 0x160 + _ [28]byte + SPI_W10 volatile.Register32 // 0x180 + _ [28]byte + SPI_W11 volatile.Register32 // 0x1A0 + _ [28]byte + SPI_W12 volatile.Register32 // 0x1C0 + _ [28]byte + SPI_W13 volatile.Register32 // 0x1E0 + _ [28]byte + SPI_W14 volatile.Register32 // 0x200 + _ [28]byte + SPI_W15 volatile.Register32 // 0x220 +} + +// SPI1.SPI_CMD: In the master mode, it is the start bit of a single operation. Self-clear by hardware +func (o *SPI1_Type) SetSPI_CMD_SPI_USR(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x40000)|value<<18) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_USR() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x40000) >> 18 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_READ(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_READ() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x80000000) >> 31 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_WRITE_ENABLE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_WRITE_ENABLE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_WRITE_DISABLE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_WRITE_DISABLE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_READ_ID(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_READ_ID() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_READ_SR(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_READ_SR() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_WRITE_SR(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_WRITE_SR() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_PP(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_PP() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_SE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_SE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_BE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_BE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_CE(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x400000)|value<<22) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_CE() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x400000) >> 22 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_DP(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x200000)|value<<21) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_DP() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x200000) >> 21 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_RES(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_RES() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetSPI_CMD_SPI_HPM(value uint32) { + volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x80000)|value<<19) +} +func (o *SPI1_Type) GetSPI_CMD_SPI_HPM() uint32 { + return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x80000) >> 19 +} + +// SPI1.SPI_ADDR: In the master mode, it is the value of address in "address" phase. +func (o *SPI1_Type) SetSPI_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_ADDR.Reg, value) +} +func (o *SPI1_Type) GetSPI_ADDR() uint32 { + return volatile.LoadUint32(&o.SPI_ADDR.Reg) +} +func (o *SPI1_Type) SetSPI_ADDR_ADDRESS(value uint32) { + volatile.StoreUint32(&o.SPI_ADDR.Reg, volatile.LoadUint32(&o.SPI_ADDR.Reg)&^(0xffffff)|value) +} +func (o *SPI1_Type) GetSPI_ADDR_ADDRESS() uint32 { + return volatile.LoadUint32(&o.SPI_ADDR.Reg) & 0xffffff +} +func (o *SPI1_Type) SetSPI_ADDR_SIZE(value uint32) { + volatile.StoreUint32(&o.SPI_ADDR.Reg, volatile.LoadUint32(&o.SPI_ADDR.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_ADDR_SIZE() uint32 { + return (volatile.LoadUint32(&o.SPI_ADDR.Reg) & 0xff000000) >> 24 +} + +// SPI1.SPI_CTRL: SPI_CTRL +func (o *SPI1_Type) SetSPI_CTRL_SPI_WR_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x4000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_CTRL_SPI_WR_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x4000000) >> 26 +} +func (o *SPI1_Type) SetSPI_CTRL_SPI_RD_BIT_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_CTRL_SPI_RD_BIT_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetSPI_CTRL_SPI_QIO_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_CTRL_SPI_QIO_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_CTRL_SPI_DIO_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_CTRL_SPI_DIO_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x800000) >> 23 +} +func (o *SPI1_Type) SetSPI_CTRL_SPI_QOUT_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100000)|value<<20) +} +func (o *SPI1_Type) GetSPI_CTRL_SPI_QOUT_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100000) >> 20 +} +func (o *SPI1_Type) SetSPI_CTRL_SPI_DOUT_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetSPI_CTRL_SPI_DOUT_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetSPI_CTRL_SPI_FASTRD_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetSPI_CTRL_SPI_FASTRD_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x2000) >> 13 +} + +// SPI1.SPI_CTRL1 +func (o *SPI1_Type) SetSPI_CTRL1_STATUS(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL1.Reg, volatile.LoadUint32(&o.SPI_CTRL1.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_CTRL1_STATUS() uint32 { + return volatile.LoadUint32(&o.SPI_CTRL1.Reg) & 0xffff +} +func (o *SPI1_Type) SetSPI_CTRL1_WB_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL1.Reg, volatile.LoadUint32(&o.SPI_CTRL1.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_CTRL1_WB_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL1.Reg) & 0xff0000) >> 16 +} +func (o *SPI1_Type) SetSPI_CTRL1_STATUS_EXT(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL1.Reg, volatile.LoadUint32(&o.SPI_CTRL1.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_CTRL1_STATUS_EXT() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL1.Reg) & 0xff000000) >> 24 +} + +// SPI1.SPI_RD_STATUS: In the slave mode, this register are the status register for the master to read out. +func (o *SPI1_Type) SetSPI_RD_STATUS(value uint32) { + volatile.StoreUint32(&o.SPI_RD_STATUS.Reg, value) +} +func (o *SPI1_Type) GetSPI_RD_STATUS() uint32 { + return volatile.LoadUint32(&o.SPI_RD_STATUS.Reg) +} + +// SPI1.SPI_CTRL2: spi_cs signal is delayed by 80MHz clock cycles +func (o *SPI1_Type) SetSPI_CTRL2_SPI_CS_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_CTRL2_SPI_CS_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0xf0000000) >> 28 +} +func (o *SPI1_Type) SetSPI_CTRL2_SPI_CS_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0xc000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_CTRL2_SPI_CS_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0xc000000) >> 26 +} +func (o *SPI1_Type) SetSPI_CTRL2_SPI_MOSI_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0x3800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_CTRL2_SPI_MOSI_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0x3800000) >> 23 +} +func (o *SPI1_Type) SetSPI_CTRL2_SPI_MOSI_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0x600000)|value<<21) +} +func (o *SPI1_Type) GetSPI_CTRL2_SPI_MOSI_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0x600000) >> 21 +} +func (o *SPI1_Type) SetSPI_CTRL2_SPI_MISO_DELAY_NUM(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0x1c0000)|value<<18) +} +func (o *SPI1_Type) GetSPI_CTRL2_SPI_MISO_DELAY_NUM() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0x1c0000) >> 18 +} +func (o *SPI1_Type) SetSPI_CTRL2_SPI_MISO_DELAY_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_CTRL2.Reg, volatile.LoadUint32(&o.SPI_CTRL2.Reg)&^(0x30000)|value<<16) +} +func (o *SPI1_Type) GetSPI_CTRL2_SPI_MISO_DELAY_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_CTRL2.Reg) & 0x30000) >> 16 +} + +// SPI1.SPI_CLOCK: In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. +func (o *SPI1_Type) SetSPI_CLOCK_SPI_CLK_EQU_SYSCLK(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_CLOCK_SPI_CLK_EQU_SYSCLK() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x80000000) >> 31 +} +func (o *SPI1_Type) SetSPI_CLOCK_SPI_CLKDIV_PRE(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x7ffc0000)|value<<18) +} +func (o *SPI1_Type) GetSPI_CLOCK_SPI_CLKDIV_PRE() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x7ffc0000) >> 18 +} +func (o *SPI1_Type) SetSPI_CLOCK_SPI_CLKCNT_N(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f000)|value<<12) +} +func (o *SPI1_Type) GetSPI_CLOCK_SPI_CLKCNT_N() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f000) >> 12 +} +func (o *SPI1_Type) SetSPI_CLOCK_SPI_CLKCNT_H(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0xfc0)|value<<6) +} +func (o *SPI1_Type) GetSPI_CLOCK_SPI_CLKCNT_H() uint32 { + return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0xfc0) >> 6 +} +func (o *SPI1_Type) SetSPI_CLOCK_SPI_CLKCNT_L(value uint32) { + volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f)|value) +} +func (o *SPI1_Type) GetSPI_CLOCK_SPI_CLKCNT_L() uint32 { + return volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f +} + +// SPI1.SPI_USER: This bit enable the "command" phase of an operation. +func (o *SPI1_Type) SetSPI_USER_SPI_USR_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_USER_SPI_USR_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80000000) >> 31 +} +func (o *SPI1_Type) SetSPI_USER_SPI_USR_ADDR(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_USER_SPI_USR_ADDR() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetSPI_USER_SPI_USR_DUMMY(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_USER_SPI_USR_DUMMY() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000000) >> 29 +} +func (o *SPI1_Type) SetSPI_USER_SPI_USR_MISO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_USER_SPI_USR_MISO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10000000) >> 28 +} +func (o *SPI1_Type) SetSPI_USER_SPI_USR_MOSI(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_USER_SPI_USR_MOSI() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_USER_REG_USR_MOSI_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000000)|value<<25) +} +func (o *SPI1_Type) GetSPI_USER_REG_USR_MOSI_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000000) >> 25 +} +func (o *SPI1_Type) SetSPI_USER_REG_USR_MISO_HIGHPART(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_USER_REG_USR_MISO_HIGHPART() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000000) >> 24 +} +func (o *SPI1_Type) SetSPI_USER_SPI_SIO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10000)|value<<16) +} +func (o *SPI1_Type) GetSPI_USER_SPI_SIO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10000) >> 16 +} +func (o *SPI1_Type) SetSPI_USER_SPI_FWRITE_QIO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000)|value<<15) +} +func (o *SPI1_Type) GetSPI_USER_SPI_FWRITE_QIO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000) >> 15 +} +func (o *SPI1_Type) SetSPI_USER_SPI_FWRITE_DIO(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4000)|value<<14) +} +func (o *SPI1_Type) GetSPI_USER_SPI_FWRITE_DIO() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4000) >> 14 +} +func (o *SPI1_Type) SetSPI_USER_SPI_FWRITE_QUAD(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000)|value<<13) +} +func (o *SPI1_Type) GetSPI_USER_SPI_FWRITE_QUAD() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000) >> 13 +} +func (o *SPI1_Type) SetSPI_USER_SPI_FWRITE_DUAL(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000)|value<<12) +} +func (o *SPI1_Type) GetSPI_USER_SPI_FWRITE_DUAL() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000) >> 12 +} +func (o *SPI1_Type) SetSPI_USER_SPI_WR_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x800)|value<<11) +} +func (o *SPI1_Type) GetSPI_USER_SPI_WR_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x800) >> 11 +} +func (o *SPI1_Type) SetSPI_USER_SPI_RD_BYTE_ORDER(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x400)|value<<10) +} +func (o *SPI1_Type) GetSPI_USER_SPI_RD_BYTE_ORDER() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x400) >> 10 +} +func (o *SPI1_Type) SetSPI_USER_SPI_CK_I_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40)|value<<6) +} +func (o *SPI1_Type) GetSPI_USER_SPI_CK_I_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40) >> 6 +} +func (o *SPI1_Type) SetSPI_USER_SPI_CK_O_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80)|value<<7) +} +func (o *SPI1_Type) GetSPI_USER_SPI_CK_O_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80) >> 7 +} +func (o *SPI1_Type) SetSPI_USER_SPI_CS_SETUP(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20)|value<<5) +} +func (o *SPI1_Type) GetSPI_USER_SPI_CS_SETUP() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20) >> 5 +} +func (o *SPI1_Type) SetSPI_USER_SPI_CS_HOLD(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_USER_SPI_CS_HOLD() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_USER_SPI_AHB_USER_COMMAND(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_USER_SPI_AHB_USER_COMMAND() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_USER_SPI_FLASH_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_USER_SPI_FLASH_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_USER_SPI_AHB_USER_COMMAND_4BYTE(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_USER_SPI_AHB_USER_COMMAND_4BYTE() uint32 { + return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_USER_SPI_DUPLEX(value uint32) { + volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_USER_SPI_DUPLEX() uint32 { + return volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1 +} + +// SPI1.SPI_USER1: The length in bits of "address" phase. The register value shall be (bit_num-1) +func (o *SPI1_Type) SetSPI_USER1_REG_USR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xfc000000)|value<<26) +} +func (o *SPI1_Type) GetSPI_USER1_REG_USR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xfc000000) >> 26 +} +func (o *SPI1_Type) SetSPI_USER1_REG_USR_MOSI_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x3fe0000)|value<<17) +} +func (o *SPI1_Type) GetSPI_USER1_REG_USR_MOSI_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x3fe0000) >> 17 +} +func (o *SPI1_Type) SetSPI_USER1_REG_USR_MISO_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x1ff00)|value<<8) +} +func (o *SPI1_Type) GetSPI_USER1_REG_USR_MISO_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x1ff00) >> 8 +} +func (o *SPI1_Type) SetSPI_USER1_REG_USR_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetSPI_USER1_REG_USR_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xff +} + +// SPI1.SPI_USER2: The length in bits of "command" phase. The register value shall be (bit_num-1) +func (o *SPI1_Type) SetSPI_USER2_REG_USR_COMMAND_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xf0000000)|value<<28) +} +func (o *SPI1_Type) GetSPI_USER2_REG_USR_COMMAND_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xf0000000) >> 28 +} +func (o *SPI1_Type) SetSPI_USER2_REG_USR_COMMAND_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xffff)|value) +} +func (o *SPI1_Type) GetSPI_USER2_REG_USR_COMMAND_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xffff +} + +// SPI1.SPI_WR_STATUS: In the slave mode, this register are the status register for the master to write into. +func (o *SPI1_Type) SetSPI_WR_STATUS(value uint32) { + volatile.StoreUint32(&o.SPI_WR_STATUS.Reg, value) +} +func (o *SPI1_Type) GetSPI_WR_STATUS() uint32 { + return volatile.LoadUint32(&o.SPI_WR_STATUS.Reg) +} + +// SPI1.SPI_PIN: 1: disable CS2; 0: spi_cs signal is from/to CS2 pin +func (o *SPI1_Type) SetSPI_PIN_SPI_CS2_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_PIN.Reg, volatile.LoadUint32(&o.SPI_PIN.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_PIN_SPI_CS2_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_PIN.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_PIN_SPI_CS1_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_PIN.Reg, volatile.LoadUint32(&o.SPI_PIN.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_PIN_SPI_CS1_DIS() uint32 { + return (volatile.LoadUint32(&o.SPI_PIN.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_PIN_SPI_CS0_DIS(value uint32) { + volatile.StoreUint32(&o.SPI_PIN.Reg, volatile.LoadUint32(&o.SPI_PIN.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_PIN_SPI_CS0_DIS() uint32 { + return volatile.LoadUint32(&o.SPI_PIN.Reg) & 0x1 +} +func (o *SPI1_Type) SetSPI_PIN_SPI_IDLE_EDGE(value uint32) { + volatile.StoreUint32(&o.SPI_PIN.Reg, volatile.LoadUint32(&o.SPI_PIN.Reg)&^(0x20000000)|value<<29) +} +func (o *SPI1_Type) GetSPI_PIN_SPI_IDLE_EDGE() uint32 { + return (volatile.LoadUint32(&o.SPI_PIN.Reg) & 0x20000000) >> 29 +} + +// SPI1.SPI_SLAVE: It is the synchronous reset signal of the module. This bit is self-cleared by hardware. +func (o *SPI1_Type) SetSPI_SLAVE_SPI_SYNC_RESET(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x80000000)|value<<31) +} +func (o *SPI1_Type) GetSPI_SLAVE_SPI_SYNC_RESET() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x80000000) >> 31 +} +func (o *SPI1_Type) SetSPI_SLAVE_SPI_SLAVE_MODE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x40000000)|value<<30) +} +func (o *SPI1_Type) GetSPI_SLAVE_SPI_SLAVE_MODE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x40000000) >> 30 +} +func (o *SPI1_Type) SetSPI_SLAVE_SLV_CMD_DEFINE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_SLAVE_SLV_CMD_DEFINE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_SLAVE_SPI_TRANS_CNT(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x7800000)|value<<23) +} +func (o *SPI1_Type) GetSPI_SLAVE_SPI_TRANS_CNT() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x7800000) >> 23 +} +func (o *SPI1_Type) SetSPI_SLAVE_SPI_INT_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x3e0)|value<<5) +} +func (o *SPI1_Type) GetSPI_SLAVE_SPI_INT_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x3e0) >> 5 +} +func (o *SPI1_Type) SetSPI_SLAVE_SPI_TRANS_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x10)|value<<4) +} +func (o *SPI1_Type) GetSPI_SLAVE_SPI_TRANS_DONE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x10) >> 4 +} +func (o *SPI1_Type) SetSPI_SLAVE_SLV_WR_STA_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_SLAVE_SLV_WR_STA_DONE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_SLAVE_SLV_RD_STA_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_SLAVE_SLV_RD_STA_DONE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_SLAVE_SLV_WR_BUF_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_SLAVE_SLV_WR_BUF_DONE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_SLAVE_SLV_RD_BUF_DONE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_SLAVE_SLV_RD_BUF_DONE() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x1 +} + +// SPI1.SPI_SLAVE1: In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) +func (o *SPI1_Type) SetSPI_SLAVE1_SLV_STATUS_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0xf8000000)|value<<27) +} +func (o *SPI1_Type) GetSPI_SLAVE1_SLV_STATUS_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0xf8000000) >> 27 +} +func (o *SPI1_Type) SetSPI_SLAVE1_SLV_BUF_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x1ff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_SLAVE1_SLV_BUF_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x1ff0000) >> 16 +} +func (o *SPI1_Type) SetSPI_SLAVE1_SLV_RD_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0xfc00)|value<<10) +} +func (o *SPI1_Type) GetSPI_SLAVE1_SLV_RD_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0xfc00) >> 10 +} +func (o *SPI1_Type) SetSPI_SLAVE1_SLV_WR_ADDR_BITLEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3f0)|value<<4) +} +func (o *SPI1_Type) GetSPI_SLAVE1_SLV_WR_ADDR_BITLEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3f0) >> 4 +} +func (o *SPI1_Type) SetSPI_SLAVE1_SLV_WRSTA_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x8)|value<<3) +} +func (o *SPI1_Type) GetSPI_SLAVE1_SLV_WRSTA_DUMMY_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x8) >> 3 +} +func (o *SPI1_Type) SetSPI_SLAVE1_SLV_RDSTA_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x4)|value<<2) +} +func (o *SPI1_Type) GetSPI_SLAVE1_SLV_RDSTA_DUMMY_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x4) >> 2 +} +func (o *SPI1_Type) SetSPI_SLAVE1_SLV_WRBUF_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x2)|value<<1) +} +func (o *SPI1_Type) GetSPI_SLAVE1_SLV_WRBUF_DUMMY_EN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x2) >> 1 +} +func (o *SPI1_Type) SetSPI_SLAVE1_SLV_RDBUF_DUMMY_EN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x1)|value) +} +func (o *SPI1_Type) GetSPI_SLAVE1_SLV_RDBUF_DUMMY_EN() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x1 +} + +// SPI1.SPI_SLAVE2: In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) +func (o *SPI1_Type) SetSPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE2.Reg, volatile.LoadUint32(&o.SPI_SLAVE2.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE2.Reg) & 0xff000000) >> 24 +} +func (o *SPI1_Type) SetSPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE2.Reg, volatile.LoadUint32(&o.SPI_SLAVE2.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE2.Reg) & 0xff0000) >> 16 +} +func (o *SPI1_Type) SetSPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE2.Reg, volatile.LoadUint32(&o.SPI_SLAVE2.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetSPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE2.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetSPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE2.Reg, volatile.LoadUint32(&o.SPI_SLAVE2.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetSPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE2.Reg) & 0xff +} + +// SPI1.SPI_SLAVE3: In slave mode, it is the value of "write-status" command +func (o *SPI1_Type) SetSPI_SLAVE3_SLV_WRSTA_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE3.Reg, volatile.LoadUint32(&o.SPI_SLAVE3.Reg)&^(0xff000000)|value<<24) +} +func (o *SPI1_Type) GetSPI_SLAVE3_SLV_WRSTA_CMD_VALUE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE3.Reg) & 0xff000000) >> 24 +} +func (o *SPI1_Type) SetSPI_SLAVE3_SLV_RDSTA_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE3.Reg, volatile.LoadUint32(&o.SPI_SLAVE3.Reg)&^(0xff0000)|value<<16) +} +func (o *SPI1_Type) GetSPI_SLAVE3_SLV_RDSTA_CMD_VALUE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE3.Reg) & 0xff0000) >> 16 +} +func (o *SPI1_Type) SetSPI_SLAVE3_SLV_WRBUF_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE3.Reg, volatile.LoadUint32(&o.SPI_SLAVE3.Reg)&^(0xff00)|value<<8) +} +func (o *SPI1_Type) GetSPI_SLAVE3_SLV_WRBUF_CMD_VALUE() uint32 { + return (volatile.LoadUint32(&o.SPI_SLAVE3.Reg) & 0xff00) >> 8 +} +func (o *SPI1_Type) SetSPI_SLAVE3_SLV_RDBUF_CMD_VALUE(value uint32) { + volatile.StoreUint32(&o.SPI_SLAVE3.Reg, volatile.LoadUint32(&o.SPI_SLAVE3.Reg)&^(0xff)|value) +} +func (o *SPI1_Type) GetSPI_SLAVE3_SLV_RDBUF_CMD_VALUE() uint32 { + return volatile.LoadUint32(&o.SPI_SLAVE3.Reg) & 0xff +} + +// SPI1.SPI_W0: the data inside the buffer of the SPI module, byte 0 +func (o *SPI1_Type) SetSPI_W0(value uint32) { + volatile.StoreUint32(&o.SPI_W0.Reg, value) +} +func (o *SPI1_Type) GetSPI_W0() uint32 { + return volatile.LoadUint32(&o.SPI_W0.Reg) +} + +// SPI1.SPI_W1: the data inside the buffer of the SPI module, byte 1 +func (o *SPI1_Type) SetSPI_W1(value uint32) { + volatile.StoreUint32(&o.SPI_W1.Reg, value) +} +func (o *SPI1_Type) GetSPI_W1() uint32 { + return volatile.LoadUint32(&o.SPI_W1.Reg) +} + +// SPI1.SPI_W2: the data inside the buffer of the SPI module, byte 2 +func (o *SPI1_Type) SetSPI_W2(value uint32) { + volatile.StoreUint32(&o.SPI_W2.Reg, value) +} +func (o *SPI1_Type) GetSPI_W2() uint32 { + return volatile.LoadUint32(&o.SPI_W2.Reg) +} + +// SPI1.SPI_W3: the data inside the buffer of the SPI module, byte 3 +func (o *SPI1_Type) SetSPI_W3(value uint32) { + volatile.StoreUint32(&o.SPI_W3.Reg, value) +} +func (o *SPI1_Type) GetSPI_W3() uint32 { + return volatile.LoadUint32(&o.SPI_W3.Reg) +} + +// SPI1.SPI_W4: the data inside the buffer of the SPI module, byte 4 +func (o *SPI1_Type) SetSPI_W4(value uint32) { + volatile.StoreUint32(&o.SPI_W4.Reg, value) +} +func (o *SPI1_Type) GetSPI_W4() uint32 { + return volatile.LoadUint32(&o.SPI_W4.Reg) +} + +// SPI1.SPI_W5: the data inside the buffer of the SPI module, byte 5 +func (o *SPI1_Type) SetSPI_W5(value uint32) { + volatile.StoreUint32(&o.SPI_W5.Reg, value) +} +func (o *SPI1_Type) GetSPI_W5() uint32 { + return volatile.LoadUint32(&o.SPI_W5.Reg) +} + +// SPI1.SPI_EXT3: This register is for two SPI masters to share the same cs, clock and data signals. +func (o *SPI1_Type) SetSPI_EXT3_REG_INT_HOLD_ENA(value uint32) { + volatile.StoreUint32(&o.SPI_EXT3.Reg, volatile.LoadUint32(&o.SPI_EXT3.Reg)&^(0x3)|value) +} +func (o *SPI1_Type) GetSPI_EXT3_REG_INT_HOLD_ENA() uint32 { + return volatile.LoadUint32(&o.SPI_EXT3.Reg) & 0x3 +} + +// SPI1.SPI_W6: the data inside the buffer of the SPI module, byte 6 +func (o *SPI1_Type) SetSPI_W6(value uint32) { + volatile.StoreUint32(&o.SPI_W6.Reg, value) +} +func (o *SPI1_Type) GetSPI_W6() uint32 { + return volatile.LoadUint32(&o.SPI_W6.Reg) +} + +// SPI1.SPI_W7: the data inside the buffer of the SPI module, byte 7 +func (o *SPI1_Type) SetSPI_W7(value uint32) { + volatile.StoreUint32(&o.SPI_W7.Reg, value) +} +func (o *SPI1_Type) GetSPI_W7() uint32 { + return volatile.LoadUint32(&o.SPI_W7.Reg) +} + +// SPI1.SPI_W8: the data inside the buffer of the SPI module, byte 8 +func (o *SPI1_Type) SetSPI_W8(value uint32) { + volatile.StoreUint32(&o.SPI_W8.Reg, value) +} +func (o *SPI1_Type) GetSPI_W8() uint32 { + return volatile.LoadUint32(&o.SPI_W8.Reg) +} + +// SPI1.SPI_W9: the data inside the buffer of the SPI module, byte 9 +func (o *SPI1_Type) SetSPI_W9(value uint32) { + volatile.StoreUint32(&o.SPI_W9.Reg, value) +} +func (o *SPI1_Type) GetSPI_W9() uint32 { + return volatile.LoadUint32(&o.SPI_W9.Reg) +} + +// SPI1.SPI_W10: the data inside the buffer of the SPI module, byte 10 +func (o *SPI1_Type) SetSPI_W10(value uint32) { + volatile.StoreUint32(&o.SPI_W10.Reg, value) +} +func (o *SPI1_Type) GetSPI_W10() uint32 { + return volatile.LoadUint32(&o.SPI_W10.Reg) +} + +// SPI1.SPI_W11: the data inside the buffer of the SPI module, byte 11 +func (o *SPI1_Type) SetSPI_W11(value uint32) { + volatile.StoreUint32(&o.SPI_W11.Reg, value) +} +func (o *SPI1_Type) GetSPI_W11() uint32 { + return volatile.LoadUint32(&o.SPI_W11.Reg) +} + +// SPI1.SPI_W12: the data inside the buffer of the SPI module, byte 12 +func (o *SPI1_Type) SetSPI_W12(value uint32) { + volatile.StoreUint32(&o.SPI_W12.Reg, value) +} +func (o *SPI1_Type) GetSPI_W12() uint32 { + return volatile.LoadUint32(&o.SPI_W12.Reg) +} + +// SPI1.SPI_W13: the data inside the buffer of the SPI module, byte 13 +func (o *SPI1_Type) SetSPI_W13(value uint32) { + volatile.StoreUint32(&o.SPI_W13.Reg, value) +} +func (o *SPI1_Type) GetSPI_W13() uint32 { + return volatile.LoadUint32(&o.SPI_W13.Reg) +} + +// SPI1.SPI_W14: the data inside the buffer of the SPI module, byte 14 +func (o *SPI1_Type) SetSPI_W14(value uint32) { + volatile.StoreUint32(&o.SPI_W14.Reg, value) +} +func (o *SPI1_Type) GetSPI_W14() uint32 { + return volatile.LoadUint32(&o.SPI_W14.Reg) +} + +// SPI1.SPI_W15: the data inside the buffer of the SPI module, byte 15 +func (o *SPI1_Type) SetSPI_W15(value uint32) { + volatile.StoreUint32(&o.SPI_W15.Reg, value) +} +func (o *SPI1_Type) GetSPI_W15() uint32 { + return volatile.LoadUint32(&o.SPI_W15.Reg) +} + +type TIMER_Type struct { + FRC1_LOAD volatile.Register32 // 0x0 + FRC1_COUNT volatile.Register32 // 0x4 + FRC1_CTRL volatile.Register32 // 0x8 + FRC1_INT volatile.Register32 // 0xC + _ [16]byte + FRC2_LOAD volatile.Register32 // 0x20 + FRC2_COUNT volatile.Register32 // 0x24 + FRC2_CTRL volatile.Register32 // 0x28 + FRC2_INT volatile.Register32 // 0x2C + FRC2_ALARM volatile.Register32 // 0x30 +} + +// TIMER.FRC1_LOAD: the load value into the counter +func (o *TIMER_Type) SetFRC1_LOAD_FRC1_LOAD_VALUE(value uint32) { + volatile.StoreUint32(&o.FRC1_LOAD.Reg, volatile.LoadUint32(&o.FRC1_LOAD.Reg)&^(0x7fffff)|value) +} +func (o *TIMER_Type) GetFRC1_LOAD_FRC1_LOAD_VALUE() uint32 { + return volatile.LoadUint32(&o.FRC1_LOAD.Reg) & 0x7fffff +} + +// TIMER.FRC1_COUNT: the current value of the counter. It is a decreasingcounter. +func (o *TIMER_Type) SetFRC1_COUNT(value uint32) { + volatile.StoreUint32(&o.FRC1_COUNT.Reg, volatile.LoadUint32(&o.FRC1_COUNT.Reg)&^(0x7fffff)|value) +} +func (o *TIMER_Type) GetFRC1_COUNT() uint32 { + return volatile.LoadUint32(&o.FRC1_COUNT.Reg) & 0x7fffff +} + +// TIMER.FRC1_CTRL: FRC1_CTRL +func (o *TIMER_Type) SetFRC1_CTRL_FRC1_INT(value uint32) { + volatile.StoreUint32(&o.FRC1_CTRL.Reg, volatile.LoadUint32(&o.FRC1_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *TIMER_Type) GetFRC1_CTRL_FRC1_INT() uint32 { + return (volatile.LoadUint32(&o.FRC1_CTRL.Reg) & 0x100) >> 8 +} +func (o *TIMER_Type) SetFRC1_CTRL(value uint32) { + volatile.StoreUint32(&o.FRC1_CTRL.Reg, volatile.LoadUint32(&o.FRC1_CTRL.Reg)&^(0xff)|value) +} +func (o *TIMER_Type) GetFRC1_CTRL() uint32 { + return volatile.LoadUint32(&o.FRC1_CTRL.Reg) & 0xff +} +func (o *TIMER_Type) SetFRC1_CTRL_TIMER_ENABLE(value uint32) { + volatile.StoreUint32(&o.FRC1_CTRL.Reg, volatile.LoadUint32(&o.FRC1_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *TIMER_Type) GetFRC1_CTRL_TIMER_ENABLE() uint32 { + return (volatile.LoadUint32(&o.FRC1_CTRL.Reg) & 0x80) >> 7 +} +func (o *TIMER_Type) SetFRC1_CTRL_ROLLOVER(value uint32) { + volatile.StoreUint32(&o.FRC1_CTRL.Reg, volatile.LoadUint32(&o.FRC1_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *TIMER_Type) GetFRC1_CTRL_ROLLOVER() uint32 { + return (volatile.LoadUint32(&o.FRC1_CTRL.Reg) & 0x40) >> 6 +} +func (o *TIMER_Type) SetFRC1_CTRL_PRESCALE_DIVIDER(value uint32) { + volatile.StoreUint32(&o.FRC1_CTRL.Reg, volatile.LoadUint32(&o.FRC1_CTRL.Reg)&^(0xc)|value<<2) +} +func (o *TIMER_Type) GetFRC1_CTRL_PRESCALE_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.FRC1_CTRL.Reg) & 0xc) >> 2 +} +func (o *TIMER_Type) SetFRC1_CTRL_INTERRUPT_TYPE(value uint32) { + volatile.StoreUint32(&o.FRC1_CTRL.Reg, volatile.LoadUint32(&o.FRC1_CTRL.Reg)&^(0x1)|value) +} +func (o *TIMER_Type) GetFRC1_CTRL_INTERRUPT_TYPE() uint32 { + return volatile.LoadUint32(&o.FRC1_CTRL.Reg) & 0x1 +} + +// TIMER.FRC1_INT: FRC1_INT +func (o *TIMER_Type) SetFRC1_INT_FRC1_INT_CLR_MASK(value uint32) { + volatile.StoreUint32(&o.FRC1_INT.Reg, volatile.LoadUint32(&o.FRC1_INT.Reg)&^(0x1)|value) +} +func (o *TIMER_Type) GetFRC1_INT_FRC1_INT_CLR_MASK() uint32 { + return volatile.LoadUint32(&o.FRC1_INT.Reg) & 0x1 +} + +// TIMER.FRC2_LOAD: the load value into the counter +func (o *TIMER_Type) SetFRC2_LOAD(value uint32) { + volatile.StoreUint32(&o.FRC2_LOAD.Reg, value) +} +func (o *TIMER_Type) GetFRC2_LOAD() uint32 { + return volatile.LoadUint32(&o.FRC2_LOAD.Reg) +} + +// TIMER.FRC2_COUNT: the current value of the counter. It is a increasingcounter. +func (o *TIMER_Type) SetFRC2_COUNT(value uint32) { + volatile.StoreUint32(&o.FRC2_COUNT.Reg, value) +} +func (o *TIMER_Type) GetFRC2_COUNT() uint32 { + return volatile.LoadUint32(&o.FRC2_COUNT.Reg) +} + +// TIMER.FRC2_CTRL: FRC2_CTRL +func (o *TIMER_Type) SetFRC2_CTRL_FRC2_INT(value uint32) { + volatile.StoreUint32(&o.FRC2_CTRL.Reg, volatile.LoadUint32(&o.FRC2_CTRL.Reg)&^(0x100)|value<<8) +} +func (o *TIMER_Type) GetFRC2_CTRL_FRC2_INT() uint32 { + return (volatile.LoadUint32(&o.FRC2_CTRL.Reg) & 0x100) >> 8 +} +func (o *TIMER_Type) SetFRC2_CTRL(value uint32) { + volatile.StoreUint32(&o.FRC2_CTRL.Reg, volatile.LoadUint32(&o.FRC2_CTRL.Reg)&^(0xff)|value) +} +func (o *TIMER_Type) GetFRC2_CTRL() uint32 { + return volatile.LoadUint32(&o.FRC2_CTRL.Reg) & 0xff +} +func (o *TIMER_Type) SetFRC2_CTRL_TIMER_ENABLE(value uint32) { + volatile.StoreUint32(&o.FRC2_CTRL.Reg, volatile.LoadUint32(&o.FRC2_CTRL.Reg)&^(0x80)|value<<7) +} +func (o *TIMER_Type) GetFRC2_CTRL_TIMER_ENABLE() uint32 { + return (volatile.LoadUint32(&o.FRC2_CTRL.Reg) & 0x80) >> 7 +} +func (o *TIMER_Type) SetFRC2_CTRL_ROLLOVER(value uint32) { + volatile.StoreUint32(&o.FRC2_CTRL.Reg, volatile.LoadUint32(&o.FRC2_CTRL.Reg)&^(0x40)|value<<6) +} +func (o *TIMER_Type) GetFRC2_CTRL_ROLLOVER() uint32 { + return (volatile.LoadUint32(&o.FRC2_CTRL.Reg) & 0x40) >> 6 +} +func (o *TIMER_Type) SetFRC2_CTRL_PRESCALE_DIVIDER(value uint32) { + volatile.StoreUint32(&o.FRC2_CTRL.Reg, volatile.LoadUint32(&o.FRC2_CTRL.Reg)&^(0xc)|value<<2) +} +func (o *TIMER_Type) GetFRC2_CTRL_PRESCALE_DIVIDER() uint32 { + return (volatile.LoadUint32(&o.FRC2_CTRL.Reg) & 0xc) >> 2 +} +func (o *TIMER_Type) SetFRC2_CTRL_INTERRUPT_TYPE(value uint32) { + volatile.StoreUint32(&o.FRC2_CTRL.Reg, volatile.LoadUint32(&o.FRC2_CTRL.Reg)&^(0x1)|value) +} +func (o *TIMER_Type) GetFRC2_CTRL_INTERRUPT_TYPE() uint32 { + return volatile.LoadUint32(&o.FRC2_CTRL.Reg) & 0x1 +} + +// TIMER.FRC2_INT: FRC2_INT +func (o *TIMER_Type) SetFRC2_INT_FRC2_INT_CLR_MASK(value uint32) { + volatile.StoreUint32(&o.FRC2_INT.Reg, volatile.LoadUint32(&o.FRC2_INT.Reg)&^(0x1)|value) +} +func (o *TIMER_Type) GetFRC2_INT_FRC2_INT_CLR_MASK() uint32 { + return volatile.LoadUint32(&o.FRC2_INT.Reg) & 0x1 +} + +// TIMER.FRC2_ALARM: the alarm value for the counter +func (o *TIMER_Type) SetFRC2_ALARM(value uint32) { + volatile.StoreUint32(&o.FRC2_ALARM.Reg, value) +} +func (o *TIMER_Type) GetFRC2_ALARM() uint32 { + return volatile.LoadUint32(&o.FRC2_ALARM.Reg) +} + +type UART0_Type struct { + UART_FIFO volatile.Register32 // 0x0 + UART_INT_RAW volatile.Register32 // 0x4 + UART_INT_ST volatile.Register32 // 0x8 + UART_INT_ENA volatile.Register32 // 0xC + UART_INT_CLR volatile.Register32 // 0x10 + UART_CLKDIV volatile.Register32 // 0x14 + UART_AUTOBAUD volatile.Register32 // 0x18 + UART_STATUS volatile.Register32 // 0x1C + UART_CONF0 volatile.Register32 // 0x20 + UART_CONF1 volatile.Register32 // 0x24 + UART_LOWPULSE volatile.Register32 // 0x28 + UART_HIGHPULSE volatile.Register32 // 0x2C + UART_RXD_CNT volatile.Register32 // 0x30 + _ [68]byte + UART_DATE volatile.Register32 // 0x78 + UART_ID volatile.Register32 // 0x7C +} + +// UART0.UART_FIFO: UART FIFO,length 128 +func (o *UART0_Type) SetUART_FIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.UART_FIFO.Reg, volatile.LoadUint32(&o.UART_FIFO.Reg)&^(0xff)|value) +} +func (o *UART0_Type) GetUART_FIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.UART_FIFO.Reg) & 0xff +} +func (o *UART0_Type) SetUART_FIFO_RXFIFO_WRITE_BYTE(value uint32) { + volatile.StoreUint32(&o.UART_FIFO.Reg, volatile.LoadUint32(&o.UART_FIFO.Reg)&^(0xff)|value) +} +func (o *UART0_Type) GetUART_FIFO_RXFIFO_WRITE_BYTE() uint32 { + return volatile.LoadUint32(&o.UART_FIFO.Reg) & 0xff +} + +// UART0.UART_INT_RAW: UART INTERRUPT RAW STATE +func (o *UART0_Type) SetUART_INT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART0_Type) GetUART_INT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART0_Type) SetUART_INT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART0_Type) GetUART_INT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART0_Type) SetUART_INT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART0_Type) GetUART_INT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART0_Type) SetUART_INT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART0_Type) GetUART_INT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART0_Type) SetUART_INT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART0_Type) GetUART_INT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART0_Type) SetUART_INT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART0_Type) GetUART_INT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART0_Type) SetUART_INT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART0_Type) GetUART_INT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART0_Type) SetUART_INT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART0_Type) GetUART_INT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART0_Type) SetUART_INT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART0_Type) GetUART_INT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x1 +} + +// UART0.UART_INT_ST: UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA +func (o *UART0_Type) SetUART_INT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART0_Type) GetUART_INT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART0_Type) SetUART_INT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART0_Type) GetUART_INT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART0_Type) SetUART_INT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART0_Type) GetUART_INT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART0_Type) SetUART_INT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART0_Type) GetUART_INT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART0_Type) SetUART_INT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART0_Type) GetUART_INT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART0_Type) SetUART_INT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART0_Type) GetUART_INT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART0_Type) SetUART_INT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART0_Type) GetUART_INT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART0_Type) SetUART_INT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART0_Type) GetUART_INT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART0_Type) SetUART_INT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x1)|value) +} +func (o *UART0_Type) GetUART_INT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x1 +} + +// UART0.UART_INT_ENA: UART INTERRUPT ENABLE REGISTER +func (o *UART0_Type) SetUART_INT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART0_Type) GetUART_INT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART0_Type) SetUART_INT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART0_Type) GetUART_INT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART0_Type) SetUART_INT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART0_Type) GetUART_INT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART0_Type) SetUART_INT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART0_Type) GetUART_INT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART0_Type) SetUART_INT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART0_Type) GetUART_INT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART0_Type) SetUART_INT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART0_Type) GetUART_INT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART0_Type) SetUART_INT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART0_Type) GetUART_INT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART0_Type) SetUART_INT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART0_Type) GetUART_INT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART0_Type) SetUART_INT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART0_Type) GetUART_INT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x1 +} + +// UART0.UART_INT_CLR: UART INTERRUPT CLEAR REGISTER +func (o *UART0_Type) SetUART_INT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART0_Type) GetUART_INT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART0_Type) SetUART_INT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART0_Type) GetUART_INT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART0_Type) SetUART_INT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART0_Type) GetUART_INT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART0_Type) SetUART_INT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART0_Type) GetUART_INT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART0_Type) SetUART_INT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART0_Type) GetUART_INT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART0_Type) SetUART_INT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART0_Type) GetUART_INT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART0_Type) SetUART_INT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART0_Type) GetUART_INT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART0_Type) SetUART_INT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART0_Type) GetUART_INT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART0_Type) SetUART_INT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART0_Type) GetUART_INT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x1 +} + +// UART0.UART_CLKDIV: UART CLK DIV REGISTER +func (o *UART0_Type) SetUART_CLKDIV(value uint32) { + volatile.StoreUint32(&o.UART_CLKDIV.Reg, volatile.LoadUint32(&o.UART_CLKDIV.Reg)&^(0xfffff)|value) +} +func (o *UART0_Type) GetUART_CLKDIV() uint32 { + return volatile.LoadUint32(&o.UART_CLKDIV.Reg) & 0xfffff +} + +// UART0.UART_AUTOBAUD: UART BAUDRATE DETECT REGISTER +func (o *UART0_Type) SetUART_AUTOBAUD_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.UART_AUTOBAUD.Reg, volatile.LoadUint32(&o.UART_AUTOBAUD.Reg)&^(0xff00)|value<<8) +} +func (o *UART0_Type) GetUART_AUTOBAUD_GLITCH_FILT() uint32 { + return (volatile.LoadUint32(&o.UART_AUTOBAUD.Reg) & 0xff00) >> 8 +} +func (o *UART0_Type) SetUART_AUTOBAUD_AUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.UART_AUTOBAUD.Reg, volatile.LoadUint32(&o.UART_AUTOBAUD.Reg)&^(0x1)|value) +} +func (o *UART0_Type) GetUART_AUTOBAUD_AUTOBAUD_EN() uint32 { + return volatile.LoadUint32(&o.UART_AUTOBAUD.Reg) & 0x1 +} + +// UART0.UART_STATUS: UART STATUS REGISTER +func (o *UART0_Type) SetUART_STATUS_TXD(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART0_Type) GetUART_STATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x80000000) >> 31 +} +func (o *UART0_Type) SetUART_STATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART0_Type) GetUART_STATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART0_Type) SetUART_STATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART0_Type) GetUART_STATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART0_Type) SetUART_STATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *UART0_Type) GetUART_STATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0xff0000) >> 16 +} +func (o *UART0_Type) SetUART_STATUS_RXD(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART0_Type) GetUART_STATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART0_Type) SetUART_STATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART0_Type) GetUART_STATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART0_Type) SetUART_STATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART0_Type) GetUART_STATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART0_Type) SetUART_STATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0xff)|value) +} +func (o *UART0_Type) GetUART_STATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.UART_STATUS.Reg) & 0xff +} + +// UART0.UART_CONF0: UART CONFIG0(UART0 and UART1) +func (o *UART0_Type) SetUART_CONF0_UART_DTR_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *UART0_Type) GetUART_CONF0_UART_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x1000000) >> 24 +} +func (o *UART0_Type) SetUART_CONF0_UART_RTS_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UART0_Type) GetUART_CONF0_UART_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x800000) >> 23 +} +func (o *UART0_Type) SetUART_CONF0_UART_TXD_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART0_Type) GetUART_CONF0_UART_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x400000) >> 22 +} +func (o *UART0_Type) SetUART_CONF0_UART_DSR_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART0_Type) GetUART_CONF0_UART_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART0_Type) SetUART_CONF0_UART_CTS_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART0_Type) GetUART_CONF0_UART_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART0_Type) SetUART_CONF0_UART_RXD_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART0_Type) GetUART_CONF0_UART_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART0_Type) SetUART_CONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART0_Type) GetUART_CONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART0_Type) SetUART_CONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART0_Type) GetUART_CONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART0_Type) SetUART_CONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UART0_Type) GetUART_CONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x8000) >> 15 +} +func (o *UART0_Type) SetUART_CONF0_UART_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UART0_Type) GetUART_CONF0_UART_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x4000) >> 14 +} +func (o *UART0_Type) SetUART_CONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UART0_Type) GetUART_CONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x100) >> 8 +} +func (o *UART0_Type) SetUART_CONF0_SW_DTR(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UART0_Type) GetUART_CONF0_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x80) >> 7 +} +func (o *UART0_Type) SetUART_CONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UART0_Type) GetUART_CONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x40) >> 6 +} +func (o *UART0_Type) SetUART_CONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x30)|value<<4) +} +func (o *UART0_Type) GetUART_CONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x30) >> 4 +} +func (o *UART0_Type) SetUART_CONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0xc)|value<<2) +} +func (o *UART0_Type) GetUART_CONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0xc) >> 2 +} +func (o *UART0_Type) SetUART_CONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UART0_Type) GetUART_CONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x2) >> 1 +} +func (o *UART0_Type) SetUART_CONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x1)|value) +} +func (o *UART0_Type) GetUART_CONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x1 +} + +// UART0.UART_CONF1: Set this bit to enable rx time-out function +func (o *UART0_Type) SetUART_CONF1_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *UART0_Type) GetUART_CONF1_RX_TOUT_EN() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x80000000) >> 31 +} +func (o *UART0_Type) SetUART_CONF1_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x7f000000)|value<<24) +} +func (o *UART0_Type) GetUART_CONF1_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x7f000000) >> 24 +} +func (o *UART0_Type) SetUART_CONF1_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x800000)|value<<23) +} +func (o *UART0_Type) GetUART_CONF1_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x800000) >> 23 +} +func (o *UART0_Type) SetUART_CONF1_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x7f0000)|value<<16) +} +func (o *UART0_Type) GetUART_CONF1_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x7f0000) >> 16 +} +func (o *UART0_Type) SetUART_CONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x7f00)|value<<8) +} +func (o *UART0_Type) GetUART_CONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x7f00) >> 8 +} +func (o *UART0_Type) SetUART_CONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x7f)|value) +} +func (o *UART0_Type) GetUART_CONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x7f +} + +// UART0.UART_LOWPULSE: UART_LOWPULSE +func (o *UART0_Type) SetUART_LOWPULSE_LOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.UART_LOWPULSE.Reg, volatile.LoadUint32(&o.UART_LOWPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART0_Type) GetUART_LOWPULSE_LOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.UART_LOWPULSE.Reg) & 0xfffff +} + +// UART0.UART_HIGHPULSE: UART_HIGHPULSE +func (o *UART0_Type) SetUART_HIGHPULSE_HIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.UART_HIGHPULSE.Reg, volatile.LoadUint32(&o.UART_HIGHPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART0_Type) GetUART_HIGHPULSE_HIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.UART_HIGHPULSE.Reg) & 0xfffff +} + +// UART0.UART_RXD_CNT: UART_RXD_CNT +func (o *UART0_Type) SetUART_RXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.UART_RXD_CNT.Reg, volatile.LoadUint32(&o.UART_RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART0_Type) GetUART_RXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.UART_RXD_CNT.Reg) & 0x3ff +} + +// UART0.UART_DATE: UART HW INFO +func (o *UART0_Type) SetUART_DATE(value uint32) { + volatile.StoreUint32(&o.UART_DATE.Reg, value) +} +func (o *UART0_Type) GetUART_DATE() uint32 { + return volatile.LoadUint32(&o.UART_DATE.Reg) +} + +// UART0.UART_ID: UART_ID +func (o *UART0_Type) SetUART_ID(value uint32) { + volatile.StoreUint32(&o.UART_ID.Reg, value) +} +func (o *UART0_Type) GetUART_ID() uint32 { + return volatile.LoadUint32(&o.UART_ID.Reg) +} + +type UART1_Type struct { + UART_FIFO volatile.Register32 // 0x0 + UART_INT_RAW volatile.Register32 // 0x4 + UART_INT_ST volatile.Register32 // 0x8 + UART_INT_ENA volatile.Register32 // 0xC + UART_INT_CLR volatile.Register32 // 0x10 + UART_CLKDIV volatile.Register32 // 0x14 + UART_AUTOBAUD volatile.Register32 // 0x18 + UART_STATUS volatile.Register32 // 0x1C + UART_CONF0 volatile.Register32 // 0x20 + UART_CONF1 volatile.Register32 // 0x24 + UART_LOWPULSE volatile.Register32 // 0x28 + UART_HIGHPULSE volatile.Register32 // 0x2C + UART_RXD_CNT volatile.Register32 // 0x30 + _ [68]byte + UART_DATE volatile.Register32 // 0x78 + UART_ID volatile.Register32 // 0x7C +} + +// UART1.UART_FIFO: UART FIFO,length 128 +func (o *UART1_Type) SetUART_FIFO_RXFIFO_RD_BYTE(value uint32) { + volatile.StoreUint32(&o.UART_FIFO.Reg, volatile.LoadUint32(&o.UART_FIFO.Reg)&^(0xff)|value) +} +func (o *UART1_Type) GetUART_FIFO_RXFIFO_RD_BYTE() uint32 { + return volatile.LoadUint32(&o.UART_FIFO.Reg) & 0xff +} +func (o *UART1_Type) SetUART_FIFO_RXFIFO_WRITE_BYTE(value uint32) { + volatile.StoreUint32(&o.UART_FIFO.Reg, volatile.LoadUint32(&o.UART_FIFO.Reg)&^(0xff)|value) +} +func (o *UART1_Type) GetUART_FIFO_RXFIFO_WRITE_BYTE() uint32 { + return volatile.LoadUint32(&o.UART_FIFO.Reg) & 0xff +} + +// UART1.UART_INT_RAW: UART INTERRUPT RAW STATE +func (o *UART1_Type) SetUART_INT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x100)|value<<8) +} +func (o *UART1_Type) GetUART_INT_RAW_RXFIFO_TOUT_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x100) >> 8 +} +func (o *UART1_Type) SetUART_INT_RAW_BRK_DET_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x80)|value<<7) +} +func (o *UART1_Type) GetUART_INT_RAW_BRK_DET_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x80) >> 7 +} +func (o *UART1_Type) SetUART_INT_RAW_CTS_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x40)|value<<6) +} +func (o *UART1_Type) GetUART_INT_RAW_CTS_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x40) >> 6 +} +func (o *UART1_Type) SetUART_INT_RAW_DSR_CHG_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x20)|value<<5) +} +func (o *UART1_Type) GetUART_INT_RAW_DSR_CHG_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x20) >> 5 +} +func (o *UART1_Type) SetUART_INT_RAW_RXFIFO_OVF_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x10)|value<<4) +} +func (o *UART1_Type) GetUART_INT_RAW_RXFIFO_OVF_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x10) >> 4 +} +func (o *UART1_Type) SetUART_INT_RAW_FRM_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x8)|value<<3) +} +func (o *UART1_Type) GetUART_INT_RAW_FRM_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x8) >> 3 +} +func (o *UART1_Type) SetUART_INT_RAW_PARITY_ERR_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x4)|value<<2) +} +func (o *UART1_Type) GetUART_INT_RAW_PARITY_ERR_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x4) >> 2 +} +func (o *UART1_Type) SetUART_INT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x2)|value<<1) +} +func (o *UART1_Type) GetUART_INT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 { + return (volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x2) >> 1 +} +func (o *UART1_Type) SetUART_INT_RAW_RXFIFO_FULL_INT_RAW(value uint32) { + volatile.StoreUint32(&o.UART_INT_RAW.Reg, volatile.LoadUint32(&o.UART_INT_RAW.Reg)&^(0x1)|value) +} +func (o *UART1_Type) GetUART_INT_RAW_RXFIFO_FULL_INT_RAW() uint32 { + return volatile.LoadUint32(&o.UART_INT_RAW.Reg) & 0x1 +} + +// UART1.UART_INT_ST: UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA +func (o *UART1_Type) SetUART_INT_ST_RXFIFO_TOUT_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x100)|value<<8) +} +func (o *UART1_Type) GetUART_INT_ST_RXFIFO_TOUT_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x100) >> 8 +} +func (o *UART1_Type) SetUART_INT_ST_BRK_DET_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x80)|value<<7) +} +func (o *UART1_Type) GetUART_INT_ST_BRK_DET_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x80) >> 7 +} +func (o *UART1_Type) SetUART_INT_ST_CTS_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x40)|value<<6) +} +func (o *UART1_Type) GetUART_INT_ST_CTS_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x40) >> 6 +} +func (o *UART1_Type) SetUART_INT_ST_DSR_CHG_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x20)|value<<5) +} +func (o *UART1_Type) GetUART_INT_ST_DSR_CHG_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x20) >> 5 +} +func (o *UART1_Type) SetUART_INT_ST_RXFIFO_OVF_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x10)|value<<4) +} +func (o *UART1_Type) GetUART_INT_ST_RXFIFO_OVF_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x10) >> 4 +} +func (o *UART1_Type) SetUART_INT_ST_FRM_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x8)|value<<3) +} +func (o *UART1_Type) GetUART_INT_ST_FRM_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x8) >> 3 +} +func (o *UART1_Type) SetUART_INT_ST_PARITY_ERR_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x4)|value<<2) +} +func (o *UART1_Type) GetUART_INT_ST_PARITY_ERR_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x4) >> 2 +} +func (o *UART1_Type) SetUART_INT_ST_TXFIFO_EMPTY_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x2)|value<<1) +} +func (o *UART1_Type) GetUART_INT_ST_TXFIFO_EMPTY_INT_ST() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x2) >> 1 +} +func (o *UART1_Type) SetUART_INT_ST_RXFIFO_FULL_INT_ST(value uint32) { + volatile.StoreUint32(&o.UART_INT_ST.Reg, volatile.LoadUint32(&o.UART_INT_ST.Reg)&^(0x1)|value) +} +func (o *UART1_Type) GetUART_INT_ST_RXFIFO_FULL_INT_ST() uint32 { + return volatile.LoadUint32(&o.UART_INT_ST.Reg) & 0x1 +} + +// UART1.UART_INT_ENA: UART INTERRUPT ENABLE REGISTER +func (o *UART1_Type) SetUART_INT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x100)|value<<8) +} +func (o *UART1_Type) GetUART_INT_ENA_RXFIFO_TOUT_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x100) >> 8 +} +func (o *UART1_Type) SetUART_INT_ENA_BRK_DET_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x80)|value<<7) +} +func (o *UART1_Type) GetUART_INT_ENA_BRK_DET_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x80) >> 7 +} +func (o *UART1_Type) SetUART_INT_ENA_CTS_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x40)|value<<6) +} +func (o *UART1_Type) GetUART_INT_ENA_CTS_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x40) >> 6 +} +func (o *UART1_Type) SetUART_INT_ENA_DSR_CHG_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x20)|value<<5) +} +func (o *UART1_Type) GetUART_INT_ENA_DSR_CHG_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x20) >> 5 +} +func (o *UART1_Type) SetUART_INT_ENA_RXFIFO_OVF_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x10)|value<<4) +} +func (o *UART1_Type) GetUART_INT_ENA_RXFIFO_OVF_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x10) >> 4 +} +func (o *UART1_Type) SetUART_INT_ENA_FRM_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x8)|value<<3) +} +func (o *UART1_Type) GetUART_INT_ENA_FRM_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x8) >> 3 +} +func (o *UART1_Type) SetUART_INT_ENA_PARITY_ERR_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x4)|value<<2) +} +func (o *UART1_Type) GetUART_INT_ENA_PARITY_ERR_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x4) >> 2 +} +func (o *UART1_Type) SetUART_INT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x2)|value<<1) +} +func (o *UART1_Type) GetUART_INT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 { + return (volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x2) >> 1 +} +func (o *UART1_Type) SetUART_INT_ENA_RXFIFO_FULL_INT_ENA(value uint32) { + volatile.StoreUint32(&o.UART_INT_ENA.Reg, volatile.LoadUint32(&o.UART_INT_ENA.Reg)&^(0x1)|value) +} +func (o *UART1_Type) GetUART_INT_ENA_RXFIFO_FULL_INT_ENA() uint32 { + return volatile.LoadUint32(&o.UART_INT_ENA.Reg) & 0x1 +} + +// UART1.UART_INT_CLR: UART INTERRUPT CLEAR REGISTER +func (o *UART1_Type) SetUART_INT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x100)|value<<8) +} +func (o *UART1_Type) GetUART_INT_CLR_RXFIFO_TOUT_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x100) >> 8 +} +func (o *UART1_Type) SetUART_INT_CLR_BRK_DET_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x80)|value<<7) +} +func (o *UART1_Type) GetUART_INT_CLR_BRK_DET_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x80) >> 7 +} +func (o *UART1_Type) SetUART_INT_CLR_CTS_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x40)|value<<6) +} +func (o *UART1_Type) GetUART_INT_CLR_CTS_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x40) >> 6 +} +func (o *UART1_Type) SetUART_INT_CLR_DSR_CHG_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x20)|value<<5) +} +func (o *UART1_Type) GetUART_INT_CLR_DSR_CHG_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x20) >> 5 +} +func (o *UART1_Type) SetUART_INT_CLR_RXFIFO_OVF_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x10)|value<<4) +} +func (o *UART1_Type) GetUART_INT_CLR_RXFIFO_OVF_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x10) >> 4 +} +func (o *UART1_Type) SetUART_INT_CLR_FRM_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x8)|value<<3) +} +func (o *UART1_Type) GetUART_INT_CLR_FRM_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x8) >> 3 +} +func (o *UART1_Type) SetUART_INT_CLR_PARITY_ERR_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x4)|value<<2) +} +func (o *UART1_Type) GetUART_INT_CLR_PARITY_ERR_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x4) >> 2 +} +func (o *UART1_Type) SetUART_INT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x2)|value<<1) +} +func (o *UART1_Type) GetUART_INT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 { + return (volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x2) >> 1 +} +func (o *UART1_Type) SetUART_INT_CLR_RXFIFO_FULL_INT_CLR(value uint32) { + volatile.StoreUint32(&o.UART_INT_CLR.Reg, volatile.LoadUint32(&o.UART_INT_CLR.Reg)&^(0x1)|value) +} +func (o *UART1_Type) GetUART_INT_CLR_RXFIFO_FULL_INT_CLR() uint32 { + return volatile.LoadUint32(&o.UART_INT_CLR.Reg) & 0x1 +} + +// UART1.UART_CLKDIV: UART CLK DIV REGISTER +func (o *UART1_Type) SetUART_CLKDIV(value uint32) { + volatile.StoreUint32(&o.UART_CLKDIV.Reg, volatile.LoadUint32(&o.UART_CLKDIV.Reg)&^(0xfffff)|value) +} +func (o *UART1_Type) GetUART_CLKDIV() uint32 { + return volatile.LoadUint32(&o.UART_CLKDIV.Reg) & 0xfffff +} + +// UART1.UART_AUTOBAUD: UART BAUDRATE DETECT REGISTER +func (o *UART1_Type) SetUART_AUTOBAUD_GLITCH_FILT(value uint32) { + volatile.StoreUint32(&o.UART_AUTOBAUD.Reg, volatile.LoadUint32(&o.UART_AUTOBAUD.Reg)&^(0xff00)|value<<8) +} +func (o *UART1_Type) GetUART_AUTOBAUD_GLITCH_FILT() uint32 { + return (volatile.LoadUint32(&o.UART_AUTOBAUD.Reg) & 0xff00) >> 8 +} +func (o *UART1_Type) SetUART_AUTOBAUD_AUTOBAUD_EN(value uint32) { + volatile.StoreUint32(&o.UART_AUTOBAUD.Reg, volatile.LoadUint32(&o.UART_AUTOBAUD.Reg)&^(0x1)|value) +} +func (o *UART1_Type) GetUART_AUTOBAUD_AUTOBAUD_EN() uint32 { + return volatile.LoadUint32(&o.UART_AUTOBAUD.Reg) & 0x1 +} + +// UART1.UART_STATUS: UART STATUS REGISTER +func (o *UART1_Type) SetUART_STATUS_TXD(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x80000000)|value<<31) +} +func (o *UART1_Type) GetUART_STATUS_TXD() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x80000000) >> 31 +} +func (o *UART1_Type) SetUART_STATUS_RTSN(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x40000000)|value<<30) +} +func (o *UART1_Type) GetUART_STATUS_RTSN() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x40000000) >> 30 +} +func (o *UART1_Type) SetUART_STATUS_DTRN(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x20000000)|value<<29) +} +func (o *UART1_Type) GetUART_STATUS_DTRN() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x20000000) >> 29 +} +func (o *UART1_Type) SetUART_STATUS_TXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0xff0000)|value<<16) +} +func (o *UART1_Type) GetUART_STATUS_TXFIFO_CNT() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0xff0000) >> 16 +} +func (o *UART1_Type) SetUART_STATUS_RXD(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x8000)|value<<15) +} +func (o *UART1_Type) GetUART_STATUS_RXD() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x8000) >> 15 +} +func (o *UART1_Type) SetUART_STATUS_CTSN(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x4000)|value<<14) +} +func (o *UART1_Type) GetUART_STATUS_CTSN() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x4000) >> 14 +} +func (o *UART1_Type) SetUART_STATUS_DSRN(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0x2000)|value<<13) +} +func (o *UART1_Type) GetUART_STATUS_DSRN() uint32 { + return (volatile.LoadUint32(&o.UART_STATUS.Reg) & 0x2000) >> 13 +} +func (o *UART1_Type) SetUART_STATUS_RXFIFO_CNT(value uint32) { + volatile.StoreUint32(&o.UART_STATUS.Reg, volatile.LoadUint32(&o.UART_STATUS.Reg)&^(0xff)|value) +} +func (o *UART1_Type) GetUART_STATUS_RXFIFO_CNT() uint32 { + return volatile.LoadUint32(&o.UART_STATUS.Reg) & 0xff +} + +// UART1.UART_CONF0: UART CONFIG0(UART0 and UART1) +func (o *UART1_Type) SetUART_CONF0_UART_DTR_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x1000000)|value<<24) +} +func (o *UART1_Type) GetUART_CONF0_UART_DTR_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x1000000) >> 24 +} +func (o *UART1_Type) SetUART_CONF0_UART_RTS_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x800000)|value<<23) +} +func (o *UART1_Type) GetUART_CONF0_UART_RTS_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x800000) >> 23 +} +func (o *UART1_Type) SetUART_CONF0_UART_TXD_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x400000)|value<<22) +} +func (o *UART1_Type) GetUART_CONF0_UART_TXD_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x400000) >> 22 +} +func (o *UART1_Type) SetUART_CONF0_UART_DSR_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x200000)|value<<21) +} +func (o *UART1_Type) GetUART_CONF0_UART_DSR_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x200000) >> 21 +} +func (o *UART1_Type) SetUART_CONF0_UART_CTS_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x100000)|value<<20) +} +func (o *UART1_Type) GetUART_CONF0_UART_CTS_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x100000) >> 20 +} +func (o *UART1_Type) SetUART_CONF0_UART_RXD_INV(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x80000)|value<<19) +} +func (o *UART1_Type) GetUART_CONF0_UART_RXD_INV() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x80000) >> 19 +} +func (o *UART1_Type) SetUART_CONF0_TXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x40000)|value<<18) +} +func (o *UART1_Type) GetUART_CONF0_TXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x40000) >> 18 +} +func (o *UART1_Type) SetUART_CONF0_RXFIFO_RST(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x20000)|value<<17) +} +func (o *UART1_Type) GetUART_CONF0_RXFIFO_RST() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x20000) >> 17 +} +func (o *UART1_Type) SetUART_CONF0_TX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x8000)|value<<15) +} +func (o *UART1_Type) GetUART_CONF0_TX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x8000) >> 15 +} +func (o *UART1_Type) SetUART_CONF0_UART_LOOPBACK(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x4000)|value<<14) +} +func (o *UART1_Type) GetUART_CONF0_UART_LOOPBACK() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x4000) >> 14 +} +func (o *UART1_Type) SetUART_CONF0_TXD_BRK(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x100)|value<<8) +} +func (o *UART1_Type) GetUART_CONF0_TXD_BRK() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x100) >> 8 +} +func (o *UART1_Type) SetUART_CONF0_SW_DTR(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x80)|value<<7) +} +func (o *UART1_Type) GetUART_CONF0_SW_DTR() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x80) >> 7 +} +func (o *UART1_Type) SetUART_CONF0_SW_RTS(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x40)|value<<6) +} +func (o *UART1_Type) GetUART_CONF0_SW_RTS() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x40) >> 6 +} +func (o *UART1_Type) SetUART_CONF0_STOP_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x30)|value<<4) +} +func (o *UART1_Type) GetUART_CONF0_STOP_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x30) >> 4 +} +func (o *UART1_Type) SetUART_CONF0_BIT_NUM(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0xc)|value<<2) +} +func (o *UART1_Type) GetUART_CONF0_BIT_NUM() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0xc) >> 2 +} +func (o *UART1_Type) SetUART_CONF0_PARITY_EN(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x2)|value<<1) +} +func (o *UART1_Type) GetUART_CONF0_PARITY_EN() uint32 { + return (volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x2) >> 1 +} +func (o *UART1_Type) SetUART_CONF0_PARITY(value uint32) { + volatile.StoreUint32(&o.UART_CONF0.Reg, volatile.LoadUint32(&o.UART_CONF0.Reg)&^(0x1)|value) +} +func (o *UART1_Type) GetUART_CONF0_PARITY() uint32 { + return volatile.LoadUint32(&o.UART_CONF0.Reg) & 0x1 +} + +// UART1.UART_CONF1: Set this bit to enable rx time-out function +func (o *UART1_Type) SetUART_CONF1_RX_TOUT_EN(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x80000000)|value<<31) +} +func (o *UART1_Type) GetUART_CONF1_RX_TOUT_EN() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x80000000) >> 31 +} +func (o *UART1_Type) SetUART_CONF1_RX_TOUT_THRHD(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x7f000000)|value<<24) +} +func (o *UART1_Type) GetUART_CONF1_RX_TOUT_THRHD() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x7f000000) >> 24 +} +func (o *UART1_Type) SetUART_CONF1_RX_FLOW_EN(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x800000)|value<<23) +} +func (o *UART1_Type) GetUART_CONF1_RX_FLOW_EN() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x800000) >> 23 +} +func (o *UART1_Type) SetUART_CONF1_RX_FLOW_THRHD(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x7f0000)|value<<16) +} +func (o *UART1_Type) GetUART_CONF1_RX_FLOW_THRHD() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x7f0000) >> 16 +} +func (o *UART1_Type) SetUART_CONF1_TXFIFO_EMPTY_THRHD(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x7f00)|value<<8) +} +func (o *UART1_Type) GetUART_CONF1_TXFIFO_EMPTY_THRHD() uint32 { + return (volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x7f00) >> 8 +} +func (o *UART1_Type) SetUART_CONF1_RXFIFO_FULL_THRHD(value uint32) { + volatile.StoreUint32(&o.UART_CONF1.Reg, volatile.LoadUint32(&o.UART_CONF1.Reg)&^(0x7f)|value) +} +func (o *UART1_Type) GetUART_CONF1_RXFIFO_FULL_THRHD() uint32 { + return volatile.LoadUint32(&o.UART_CONF1.Reg) & 0x7f +} + +// UART1.UART_LOWPULSE: UART_LOWPULSE +func (o *UART1_Type) SetUART_LOWPULSE_LOWPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.UART_LOWPULSE.Reg, volatile.LoadUint32(&o.UART_LOWPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART1_Type) GetUART_LOWPULSE_LOWPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.UART_LOWPULSE.Reg) & 0xfffff +} + +// UART1.UART_HIGHPULSE: UART_HIGHPULSE +func (o *UART1_Type) SetUART_HIGHPULSE_HIGHPULSE_MIN_CNT(value uint32) { + volatile.StoreUint32(&o.UART_HIGHPULSE.Reg, volatile.LoadUint32(&o.UART_HIGHPULSE.Reg)&^(0xfffff)|value) +} +func (o *UART1_Type) GetUART_HIGHPULSE_HIGHPULSE_MIN_CNT() uint32 { + return volatile.LoadUint32(&o.UART_HIGHPULSE.Reg) & 0xfffff +} + +// UART1.UART_RXD_CNT: UART_RXD_CNT +func (o *UART1_Type) SetUART_RXD_CNT_RXD_EDGE_CNT(value uint32) { + volatile.StoreUint32(&o.UART_RXD_CNT.Reg, volatile.LoadUint32(&o.UART_RXD_CNT.Reg)&^(0x3ff)|value) +} +func (o *UART1_Type) GetUART_RXD_CNT_RXD_EDGE_CNT() uint32 { + return volatile.LoadUint32(&o.UART_RXD_CNT.Reg) & 0x3ff +} + +// UART1.UART_DATE: UART HW INFO +func (o *UART1_Type) SetUART_DATE(value uint32) { + volatile.StoreUint32(&o.UART_DATE.Reg, value) +} +func (o *UART1_Type) GetUART_DATE() uint32 { + return volatile.LoadUint32(&o.UART_DATE.Reg) +} + +// UART1.UART_ID: UART_ID +func (o *UART1_Type) SetUART_ID(value uint32) { + volatile.StoreUint32(&o.UART_ID.Reg, value) +} +func (o *UART1_Type) GetUART_ID() uint32 { + return volatile.LoadUint32(&o.UART_ID.Reg) +} + +type WDT_Type struct { + WDT_CTL volatile.Register32 // 0x0 + WDT_OP volatile.Register32 // 0x4 + WDT_OP_ND volatile.Register32 // 0x8 + _ [8]byte + WDT_RST volatile.Register32 // 0x14 +} + +// WDT.WDT_CTL: WDT_CTL +func (o *WDT_Type) SetWDT_CTL(value uint32) { + volatile.StoreUint32(&o.WDT_CTL.Reg, value) +} +func (o *WDT_Type) GetWDT_CTL() uint32 { + return volatile.LoadUint32(&o.WDT_CTL.Reg) +} + +// WDT.WDT_OP: WDT_OP +func (o *WDT_Type) SetWDT_OP(value uint32) { + volatile.StoreUint32(&o.WDT_OP.Reg, value) +} +func (o *WDT_Type) GetWDT_OP() uint32 { + return volatile.LoadUint32(&o.WDT_OP.Reg) +} + +// WDT.WDT_OP_ND: WDT_OP_ND +func (o *WDT_Type) SetWDT_OP_ND(value uint32) { + volatile.StoreUint32(&o.WDT_OP_ND.Reg, value) +} +func (o *WDT_Type) GetWDT_OP_ND() uint32 { + return volatile.LoadUint32(&o.WDT_OP_ND.Reg) +} + +// WDT.WDT_RST: WDT_RST +func (o *WDT_Type) SetWDT_RST(value uint32) { + volatile.StoreUint32(&o.WDT_RST.Reg, value) +} +func (o *WDT_Type) GetWDT_RST() uint32 { + return volatile.LoadUint32(&o.WDT_RST.Reg) +} + +// RNG register +type RNG_Type struct { + RNG volatile.Register32 // 0x0 +} + +// Watchdog registers +type WATCHDOG_Type struct { + CTL volatile.Register32 // 0x0 + RELOAD_STAGE0 volatile.Register32 // 0x4 + RELOAD_STAGE1 volatile.Register32 // 0x8 + COUNT volatile.Register32 // 0xC + STAGE volatile.Register32 // 0x10 + RESET volatile.Register32 // 0x14 + RESET_STAGE volatile.Register32 // 0x18 +} + +// WATCHDOG.CTL: Watchdog control +func (o *WATCHDOG_Type) SetCTL_ENABLE(value uint32) { + volatile.StoreUint32(&o.CTL.Reg, volatile.LoadUint32(&o.CTL.Reg)&^(0x1)|value) +} +func (o *WATCHDOG_Type) GetCTL_ENABLE() uint32 { + return volatile.LoadUint32(&o.CTL.Reg) & 0x1 +} +func (o *WATCHDOG_Type) SetCTL_STAGE_1_NO_RESET(value uint32) { + volatile.StoreUint32(&o.CTL.Reg, volatile.LoadUint32(&o.CTL.Reg)&^(0x2)|value<<1) +} +func (o *WATCHDOG_Type) GetCTL_STAGE_1_NO_RESET() uint32 { + return (volatile.LoadUint32(&o.CTL.Reg) & 0x2) >> 1 +} +func (o *WATCHDOG_Type) SetCTL_STAGE_1_DISABLE(value uint32) { + volatile.StoreUint32(&o.CTL.Reg, volatile.LoadUint32(&o.CTL.Reg)&^(0x4)|value<<2) +} +func (o *WATCHDOG_Type) GetCTL_STAGE_1_DISABLE() uint32 { + return (volatile.LoadUint32(&o.CTL.Reg) & 0x4) >> 2 +} +func (o *WATCHDOG_Type) SetCTL_UNKNOWN_3(value uint32) { + volatile.StoreUint32(&o.CTL.Reg, volatile.LoadUint32(&o.CTL.Reg)&^(0x8)|value<<3) +} +func (o *WATCHDOG_Type) GetCTL_UNKNOWN_3() uint32 { + return (volatile.LoadUint32(&o.CTL.Reg) & 0x8) >> 3 +} +func (o *WATCHDOG_Type) SetCTL_UNKNOWN_4(value uint32) { + volatile.StoreUint32(&o.CTL.Reg, volatile.LoadUint32(&o.CTL.Reg)&^(0x10)|value<<4) +} +func (o *WATCHDOG_Type) GetCTL_UNKNOWN_4() uint32 { + return (volatile.LoadUint32(&o.CTL.Reg) & 0x10) >> 4 +} +func (o *WATCHDOG_Type) SetCTL_UNKNOWN_5(value uint32) { + volatile.StoreUint32(&o.CTL.Reg, volatile.LoadUint32(&o.CTL.Reg)&^(0x20)|value<<5) +} +func (o *WATCHDOG_Type) GetCTL_UNKNOWN_5() uint32 { + return (volatile.LoadUint32(&o.CTL.Reg) & 0x20) >> 5 +} + +// Constants for DPORT +const ( + // EDGE_INT_ENABLE: EDGE_INT_ENABLE + // Position of Register field. + DPORT_EDGE_INT_ENABLE_Register_Pos = 0x0 + // Bit mask of Register field. + DPORT_EDGE_INT_ENABLE_Register_Msk = 0xffffffff + // Position of WDT_EDGE_INT_ENABLE field. + DPORT_EDGE_INT_ENABLE_WDT_EDGE_INT_ENABLE_Pos = 0x0 + // Bit mask of WDT_EDGE_INT_ENABLE field. + DPORT_EDGE_INT_ENABLE_WDT_EDGE_INT_ENABLE_Msk = 0x1 + // Bit WDT_EDGE_INT_ENABLE. + DPORT_EDGE_INT_ENABLE_WDT_EDGE_INT_ENABLE = 0x1 + // Position of TIMER1_EDGE_INT_ENABLE field. + DPORT_EDGE_INT_ENABLE_TIMER1_EDGE_INT_ENABLE_Pos = 0x1 + // Bit mask of TIMER1_EDGE_INT_ENABLE field. + DPORT_EDGE_INT_ENABLE_TIMER1_EDGE_INT_ENABLE_Msk = 0x2 + // Bit TIMER1_EDGE_INT_ENABLE. + DPORT_EDGE_INT_ENABLE_TIMER1_EDGE_INT_ENABLE = 0x2 + + // DPORT_CTL: DPORT_CTL + // Position of DPORT_CTL_DOUBLE_CLK field. + DPORT_DPORT_CTL_DPORT_CTL_DOUBLE_CLK_Pos = 0x0 + // Bit mask of DPORT_CTL_DOUBLE_CLK field. + DPORT_DPORT_CTL_DPORT_CTL_DOUBLE_CLK_Msk = 0x1 + // Bit DPORT_CTL_DOUBLE_CLK. + DPORT_DPORT_CTL_DPORT_CTL_DOUBLE_CLK = 0x1 +) + +// Constants for EFUSE +const ( + // EFUSE_DATA0: EFUSE_DATA0 + // Position of Register field. + EFUSE_EFUSE_DATA0_Register_Pos = 0x0 + // Bit mask of Register field. + EFUSE_EFUSE_DATA0_Register_Msk = 0xffffffff + + // EFUSE_DATA1: EFUSE_DATA1 + // Position of Register field. + EFUSE_EFUSE_DATA1_Register_Pos = 0x0 + // Bit mask of Register field. + EFUSE_EFUSE_DATA1_Register_Msk = 0xffffffff + + // EFUSE_DATA2: EFUSE_DATA2 + // Position of Register field. + EFUSE_EFUSE_DATA2_Register_Pos = 0x0 + // Bit mask of Register field. + EFUSE_EFUSE_DATA2_Register_Msk = 0xffffffff + + // EFUSE_DATA3: EFUSE_DATA3 + // Position of Register field. + EFUSE_EFUSE_DATA3_Register_Pos = 0x0 + // Bit mask of Register field. + EFUSE_EFUSE_DATA3_Register_Msk = 0xffffffff +) + +// Constants for GPIO +const ( + // GPIO_OUT: BT-Coexist Selection register + // Position of GPIO_BT_SEL field. + GPIO_GPIO_OUT_GPIO_BT_SEL_Pos = 0x10 + // Bit mask of GPIO_BT_SEL field. + GPIO_GPIO_OUT_GPIO_BT_SEL_Msk = 0xffff0000 + // Position of GPIO_OUT_DATA field. + GPIO_GPIO_OUT_GPIO_OUT_DATA_Pos = 0x0 + // Bit mask of GPIO_OUT_DATA field. + GPIO_GPIO_OUT_GPIO_OUT_DATA_Msk = 0xffff + + // GPIO_OUT_W1TS: GPIO_OUT_W1TS + // Position of GPIO_OUT_DATA_W1TS field. + GPIO_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS_Pos = 0x0 + // Bit mask of GPIO_OUT_DATA_W1TS field. + GPIO_GPIO_OUT_W1TS_GPIO_OUT_DATA_W1TS_Msk = 0xffff + + // GPIO_OUT_W1TC: GPIO_OUT_W1TC + // Position of GPIO_OUT_DATA_W1TC field. + GPIO_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC_Pos = 0x0 + // Bit mask of GPIO_OUT_DATA_W1TC field. + GPIO_GPIO_OUT_W1TC_GPIO_OUT_DATA_W1TC_Msk = 0xffff + + // GPIO_ENABLE: GPIO_ENABLE + // Position of GPIO_SDIO_SEL field. + GPIO_GPIO_ENABLE_GPIO_SDIO_SEL_Pos = 0x10 + // Bit mask of GPIO_SDIO_SEL field. + GPIO_GPIO_ENABLE_GPIO_SDIO_SEL_Msk = 0x3f0000 + // Position of GPIO_ENABLE_DATA field. + GPIO_GPIO_ENABLE_GPIO_ENABLE_DATA_Pos = 0x0 + // Bit mask of GPIO_ENABLE_DATA field. + GPIO_GPIO_ENABLE_GPIO_ENABLE_DATA_Msk = 0xffff + + // GPIO_ENABLE_W1TS: GPIO_ENABLE_W1TS + // Position of GPIO_ENABLE_DATA_W1TS field. + GPIO_GPIO_ENABLE_W1TS_GPIO_ENABLE_DATA_W1TS_Pos = 0x0 + // Bit mask of GPIO_ENABLE_DATA_W1TS field. + GPIO_GPIO_ENABLE_W1TS_GPIO_ENABLE_DATA_W1TS_Msk = 0xffff + + // GPIO_ENABLE_W1TC: GPIO_ENABLE_W1TC + // Position of GPIO_ENABLE_DATA_W1TC field. + GPIO_GPIO_ENABLE_W1TC_GPIO_ENABLE_DATA_W1TC_Pos = 0x0 + // Bit mask of GPIO_ENABLE_DATA_W1TC field. + GPIO_GPIO_ENABLE_W1TC_GPIO_ENABLE_DATA_W1TC_Msk = 0xffff + + // GPIO_IN: The values of the strapping pins. + // Position of GPIO_STRAPPING field. + GPIO_GPIO_IN_GPIO_STRAPPING_Pos = 0x10 + // Bit mask of GPIO_STRAPPING field. + GPIO_GPIO_IN_GPIO_STRAPPING_Msk = 0xffff0000 + // Position of GPIO_IN_DATA field. + GPIO_GPIO_IN_GPIO_IN_DATA_Pos = 0x0 + // Bit mask of GPIO_IN_DATA field. + GPIO_GPIO_IN_GPIO_IN_DATA_Msk = 0xffff + + // GPIO_STATUS: GPIO_STATUS + // Position of GPIO_STATUS_INTERRUPT field. + GPIO_GPIO_STATUS_GPIO_STATUS_INTERRUPT_Pos = 0x0 + // Bit mask of GPIO_STATUS_INTERRUPT field. + GPIO_GPIO_STATUS_GPIO_STATUS_INTERRUPT_Msk = 0xffff + + // GPIO_STATUS_W1TS: GPIO_STATUS_W1TS + // Position of GPIO_STATUS_INTERRUPT_W1TS field. + GPIO_GPIO_STATUS_W1TS_GPIO_STATUS_INTERRUPT_W1TS_Pos = 0x0 + // Bit mask of GPIO_STATUS_INTERRUPT_W1TS field. + GPIO_GPIO_STATUS_W1TS_GPIO_STATUS_INTERRUPT_W1TS_Msk = 0xffff + + // GPIO_STATUS_W1TC: GPIO_STATUS_W1TC + // Position of GPIO_STATUS_INTERRUPT_W1TC field. + GPIO_GPIO_STATUS_W1TC_GPIO_STATUS_INTERRUPT_W1TC_Pos = 0x0 + // Bit mask of GPIO_STATUS_INTERRUPT_W1TC field. + GPIO_GPIO_STATUS_W1TC_GPIO_STATUS_INTERRUPT_W1TC_Msk = 0xffff + + // GPIO_PIN0: GPIO_PIN0 + // Position of GPIO_PIN0_WAKEUP_ENABLE field. + GPIO_GPIO_PIN0_GPIO_PIN0_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN0_WAKEUP_ENABLE field. + GPIO_GPIO_PIN0_GPIO_PIN0_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN0_WAKEUP_ENABLE. + GPIO_GPIO_PIN0_GPIO_PIN0_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN0_INT_TYPE field. + GPIO_GPIO_PIN0_GPIO_PIN0_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN0_INT_TYPE field. + GPIO_GPIO_PIN0_GPIO_PIN0_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN0_GPIO_PIN0_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN0_GPIO_PIN0_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN0_GPIO_PIN0_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN0_GPIO_PIN0_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN0_GPIO_PIN0_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN0_GPIO_PIN0_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN0_DRIVER field. + GPIO_GPIO_PIN0_GPIO_PIN0_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN0_DRIVER field. + GPIO_GPIO_PIN0_GPIO_PIN0_DRIVER_Msk = 0x4 + // Bit GPIO_PIN0_DRIVER. + GPIO_GPIO_PIN0_GPIO_PIN0_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN0_GPIO_PIN0_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN0_GPIO_PIN0_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN0_SOURCE field. + GPIO_GPIO_PIN0_GPIO_PIN0_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN0_SOURCE field. + GPIO_GPIO_PIN0_GPIO_PIN0_SOURCE_Msk = 0x1 + // Bit GPIO_PIN0_SOURCE. + GPIO_GPIO_PIN0_GPIO_PIN0_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN0_GPIO_PIN0_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN0_GPIO_PIN0_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN1: GPIO_PIN1 + // Position of GPIO_PIN1_WAKEUP_ENABLE field. + GPIO_GPIO_PIN1_GPIO_PIN1_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN1_WAKEUP_ENABLE field. + GPIO_GPIO_PIN1_GPIO_PIN1_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN1_WAKEUP_ENABLE. + GPIO_GPIO_PIN1_GPIO_PIN1_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN1_INT_TYPE field. + GPIO_GPIO_PIN1_GPIO_PIN1_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN1_INT_TYPE field. + GPIO_GPIO_PIN1_GPIO_PIN1_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN1_GPIO_PIN1_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN1_GPIO_PIN1_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN1_GPIO_PIN1_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN1_GPIO_PIN1_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN1_GPIO_PIN1_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN1_GPIO_PIN1_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN1_DRIVER field. + GPIO_GPIO_PIN1_GPIO_PIN1_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN1_DRIVER field. + GPIO_GPIO_PIN1_GPIO_PIN1_DRIVER_Msk = 0x4 + // Bit GPIO_PIN1_DRIVER. + GPIO_GPIO_PIN1_GPIO_PIN1_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN1_GPIO_PIN1_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN1_GPIO_PIN1_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN1_SOURCE field. + GPIO_GPIO_PIN1_GPIO_PIN1_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN1_SOURCE field. + GPIO_GPIO_PIN1_GPIO_PIN1_SOURCE_Msk = 0x1 + // Bit GPIO_PIN1_SOURCE. + GPIO_GPIO_PIN1_GPIO_PIN1_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN1_GPIO_PIN1_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN1_GPIO_PIN1_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN2: GPIO_PIN2 + // Position of GPIO_PIN2_WAKEUP_ENABLE field. + GPIO_GPIO_PIN2_GPIO_PIN2_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN2_WAKEUP_ENABLE field. + GPIO_GPIO_PIN2_GPIO_PIN2_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN2_WAKEUP_ENABLE. + GPIO_GPIO_PIN2_GPIO_PIN2_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN2_INT_TYPE field. + GPIO_GPIO_PIN2_GPIO_PIN2_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN2_INT_TYPE field. + GPIO_GPIO_PIN2_GPIO_PIN2_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN2_GPIO_PIN2_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN2_GPIO_PIN2_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN2_GPIO_PIN2_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN2_GPIO_PIN2_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN2_GPIO_PIN2_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN2_GPIO_PIN2_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN2_DRIVER field. + GPIO_GPIO_PIN2_GPIO_PIN2_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN2_DRIVER field. + GPIO_GPIO_PIN2_GPIO_PIN2_DRIVER_Msk = 0x4 + // Bit GPIO_PIN2_DRIVER. + GPIO_GPIO_PIN2_GPIO_PIN2_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN2_GPIO_PIN2_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN2_GPIO_PIN2_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN2_SOURCE field. + GPIO_GPIO_PIN2_GPIO_PIN2_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN2_SOURCE field. + GPIO_GPIO_PIN2_GPIO_PIN2_SOURCE_Msk = 0x1 + // Bit GPIO_PIN2_SOURCE. + GPIO_GPIO_PIN2_GPIO_PIN2_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN2_GPIO_PIN2_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN2_GPIO_PIN2_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN3: GPIO_PIN3 + // Position of GPIO_PIN3_WAKEUP_ENABLE field. + GPIO_GPIO_PIN3_GPIO_PIN3_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN3_WAKEUP_ENABLE field. + GPIO_GPIO_PIN3_GPIO_PIN3_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN3_WAKEUP_ENABLE. + GPIO_GPIO_PIN3_GPIO_PIN3_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN3_INT_TYPE field. + GPIO_GPIO_PIN3_GPIO_PIN3_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN3_INT_TYPE field. + GPIO_GPIO_PIN3_GPIO_PIN3_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN3_GPIO_PIN3_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN3_GPIO_PIN3_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN3_GPIO_PIN3_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN3_GPIO_PIN3_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN3_GPIO_PIN3_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN3_GPIO_PIN3_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN3_DRIVER field. + GPIO_GPIO_PIN3_GPIO_PIN3_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN3_DRIVER field. + GPIO_GPIO_PIN3_GPIO_PIN3_DRIVER_Msk = 0x4 + // Bit GPIO_PIN3_DRIVER. + GPIO_GPIO_PIN3_GPIO_PIN3_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN3_GPIO_PIN3_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN3_GPIO_PIN3_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN3_SOURCE field. + GPIO_GPIO_PIN3_GPIO_PIN3_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN3_SOURCE field. + GPIO_GPIO_PIN3_GPIO_PIN3_SOURCE_Msk = 0x1 + // Bit GPIO_PIN3_SOURCE. + GPIO_GPIO_PIN3_GPIO_PIN3_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN3_GPIO_PIN3_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN3_GPIO_PIN3_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN4: GPIO_PIN4 + // Position of GPIO_PIN4_WAKEUP_ENABLE field. + GPIO_GPIO_PIN4_GPIO_PIN4_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN4_WAKEUP_ENABLE field. + GPIO_GPIO_PIN4_GPIO_PIN4_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN4_WAKEUP_ENABLE. + GPIO_GPIO_PIN4_GPIO_PIN4_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN4_INT_TYPE field. + GPIO_GPIO_PIN4_GPIO_PIN4_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN4_INT_TYPE field. + GPIO_GPIO_PIN4_GPIO_PIN4_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN4_GPIO_PIN4_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN4_GPIO_PIN4_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN4_GPIO_PIN4_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN4_GPIO_PIN4_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN4_GPIO_PIN4_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN4_GPIO_PIN4_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN4_DRIVER field. + GPIO_GPIO_PIN4_GPIO_PIN4_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN4_DRIVER field. + GPIO_GPIO_PIN4_GPIO_PIN4_DRIVER_Msk = 0x4 + // Bit GPIO_PIN4_DRIVER. + GPIO_GPIO_PIN4_GPIO_PIN4_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN4_GPIO_PIN4_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN4_GPIO_PIN4_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN4_SOURCE field. + GPIO_GPIO_PIN4_GPIO_PIN4_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN4_SOURCE field. + GPIO_GPIO_PIN4_GPIO_PIN4_SOURCE_Msk = 0x1 + // Bit GPIO_PIN4_SOURCE. + GPIO_GPIO_PIN4_GPIO_PIN4_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN4_GPIO_PIN4_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN4_GPIO_PIN4_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN5: GPIO_PIN5 + // Position of GPIO_PIN5_WAKEUP_ENABLE field. + GPIO_GPIO_PIN5_GPIO_PIN5_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN5_WAKEUP_ENABLE field. + GPIO_GPIO_PIN5_GPIO_PIN5_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN5_WAKEUP_ENABLE. + GPIO_GPIO_PIN5_GPIO_PIN5_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN5_INT_TYPE field. + GPIO_GPIO_PIN5_GPIO_PIN5_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN5_INT_TYPE field. + GPIO_GPIO_PIN5_GPIO_PIN5_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN5_GPIO_PIN5_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN5_GPIO_PIN5_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN5_GPIO_PIN5_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN5_GPIO_PIN5_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN5_GPIO_PIN5_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN5_GPIO_PIN5_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN5_DRIVER field. + GPIO_GPIO_PIN5_GPIO_PIN5_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN5_DRIVER field. + GPIO_GPIO_PIN5_GPIO_PIN5_DRIVER_Msk = 0x4 + // Bit GPIO_PIN5_DRIVER. + GPIO_GPIO_PIN5_GPIO_PIN5_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN5_GPIO_PIN5_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN5_GPIO_PIN5_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN5_SOURCE field. + GPIO_GPIO_PIN5_GPIO_PIN5_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN5_SOURCE field. + GPIO_GPIO_PIN5_GPIO_PIN5_SOURCE_Msk = 0x1 + // Bit GPIO_PIN5_SOURCE. + GPIO_GPIO_PIN5_GPIO_PIN5_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN5_GPIO_PIN5_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN5_GPIO_PIN5_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN6: GPIO_PIN6 + // Position of GPIO_PIN6_WAKEUP_ENABLE field. + GPIO_GPIO_PIN6_GPIO_PIN6_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN6_WAKEUP_ENABLE field. + GPIO_GPIO_PIN6_GPIO_PIN6_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN6_WAKEUP_ENABLE. + GPIO_GPIO_PIN6_GPIO_PIN6_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN6_INT_TYPE field. + GPIO_GPIO_PIN6_GPIO_PIN6_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN6_INT_TYPE field. + GPIO_GPIO_PIN6_GPIO_PIN6_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN6_GPIO_PIN6_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN6_GPIO_PIN6_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN6_GPIO_PIN6_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN6_GPIO_PIN6_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN6_GPIO_PIN6_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN6_GPIO_PIN6_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN6_DRIVER field. + GPIO_GPIO_PIN6_GPIO_PIN6_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN6_DRIVER field. + GPIO_GPIO_PIN6_GPIO_PIN6_DRIVER_Msk = 0x4 + // Bit GPIO_PIN6_DRIVER. + GPIO_GPIO_PIN6_GPIO_PIN6_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN6_GPIO_PIN6_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN6_GPIO_PIN6_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN6_SOURCE field. + GPIO_GPIO_PIN6_GPIO_PIN6_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN6_SOURCE field. + GPIO_GPIO_PIN6_GPIO_PIN6_SOURCE_Msk = 0x1 + // Bit GPIO_PIN6_SOURCE. + GPIO_GPIO_PIN6_GPIO_PIN6_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN6_GPIO_PIN6_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN6_GPIO_PIN6_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN7: GPIO_PIN7 + // Position of GPIO_PIN7_WAKEUP_ENABLE field. + GPIO_GPIO_PIN7_GPIO_PIN7_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN7_WAKEUP_ENABLE field. + GPIO_GPIO_PIN7_GPIO_PIN7_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN7_WAKEUP_ENABLE. + GPIO_GPIO_PIN7_GPIO_PIN7_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN7_INT_TYPE field. + GPIO_GPIO_PIN7_GPIO_PIN7_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN7_INT_TYPE field. + GPIO_GPIO_PIN7_GPIO_PIN7_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN7_GPIO_PIN7_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN7_GPIO_PIN7_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN7_GPIO_PIN7_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN7_GPIO_PIN7_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN7_GPIO_PIN7_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN7_GPIO_PIN7_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN7_DRIVER field. + GPIO_GPIO_PIN7_GPIO_PIN7_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN7_DRIVER field. + GPIO_GPIO_PIN7_GPIO_PIN7_DRIVER_Msk = 0x4 + // Bit GPIO_PIN7_DRIVER. + GPIO_GPIO_PIN7_GPIO_PIN7_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN7_GPIO_PIN7_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN7_GPIO_PIN7_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN7_SOURCE field. + GPIO_GPIO_PIN7_GPIO_PIN7_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN7_SOURCE field. + GPIO_GPIO_PIN7_GPIO_PIN7_SOURCE_Msk = 0x1 + // Bit GPIO_PIN7_SOURCE. + GPIO_GPIO_PIN7_GPIO_PIN7_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN7_GPIO_PIN7_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN7_GPIO_PIN7_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN8: GPIO_PIN8 + // Position of GPIO_PIN8_WAKEUP_ENABLE field. + GPIO_GPIO_PIN8_GPIO_PIN8_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN8_WAKEUP_ENABLE field. + GPIO_GPIO_PIN8_GPIO_PIN8_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN8_WAKEUP_ENABLE. + GPIO_GPIO_PIN8_GPIO_PIN8_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN8_INT_TYPE field. + GPIO_GPIO_PIN8_GPIO_PIN8_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN8_INT_TYPE field. + GPIO_GPIO_PIN8_GPIO_PIN8_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN8_GPIO_PIN8_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN8_GPIO_PIN8_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN8_GPIO_PIN8_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN8_GPIO_PIN8_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN8_GPIO_PIN8_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN8_GPIO_PIN8_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN8_DRIVER field. + GPIO_GPIO_PIN8_GPIO_PIN8_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN8_DRIVER field. + GPIO_GPIO_PIN8_GPIO_PIN8_DRIVER_Msk = 0x4 + // Bit GPIO_PIN8_DRIVER. + GPIO_GPIO_PIN8_GPIO_PIN8_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN8_GPIO_PIN8_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN8_GPIO_PIN8_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN8_SOURCE field. + GPIO_GPIO_PIN8_GPIO_PIN8_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN8_SOURCE field. + GPIO_GPIO_PIN8_GPIO_PIN8_SOURCE_Msk = 0x1 + // Bit GPIO_PIN8_SOURCE. + GPIO_GPIO_PIN8_GPIO_PIN8_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN8_GPIO_PIN8_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN8_GPIO_PIN8_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN9: GPIO_PIN9 + // Position of GPIO_PIN9_WAKEUP_ENABLE field. + GPIO_GPIO_PIN9_GPIO_PIN9_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN9_WAKEUP_ENABLE field. + GPIO_GPIO_PIN9_GPIO_PIN9_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN9_WAKEUP_ENABLE. + GPIO_GPIO_PIN9_GPIO_PIN9_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN9_INT_TYPE field. + GPIO_GPIO_PIN9_GPIO_PIN9_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN9_INT_TYPE field. + GPIO_GPIO_PIN9_GPIO_PIN9_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN9_GPIO_PIN9_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN9_GPIO_PIN9_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN9_GPIO_PIN9_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN9_GPIO_PIN9_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN9_GPIO_PIN9_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN9_GPIO_PIN9_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN9_DRIVER field. + GPIO_GPIO_PIN9_GPIO_PIN9_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN9_DRIVER field. + GPIO_GPIO_PIN9_GPIO_PIN9_DRIVER_Msk = 0x4 + // Bit GPIO_PIN9_DRIVER. + GPIO_GPIO_PIN9_GPIO_PIN9_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN9_GPIO_PIN9_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN9_GPIO_PIN9_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN9_SOURCE field. + GPIO_GPIO_PIN9_GPIO_PIN9_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN9_SOURCE field. + GPIO_GPIO_PIN9_GPIO_PIN9_SOURCE_Msk = 0x1 + // Bit GPIO_PIN9_SOURCE. + GPIO_GPIO_PIN9_GPIO_PIN9_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN9_GPIO_PIN9_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN9_GPIO_PIN9_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN10: GPIO_PIN10 + // Position of GPIO_PIN10_WAKEUP_ENABLE field. + GPIO_GPIO_PIN10_GPIO_PIN10_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN10_WAKEUP_ENABLE field. + GPIO_GPIO_PIN10_GPIO_PIN10_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN10_WAKEUP_ENABLE. + GPIO_GPIO_PIN10_GPIO_PIN10_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN10_INT_TYPE field. + GPIO_GPIO_PIN10_GPIO_PIN10_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN10_INT_TYPE field. + GPIO_GPIO_PIN10_GPIO_PIN10_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN10_GPIO_PIN10_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN10_GPIO_PIN10_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN10_GPIO_PIN10_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN10_GPIO_PIN10_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN10_GPIO_PIN10_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN10_GPIO_PIN10_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN10_DRIVER field. + GPIO_GPIO_PIN10_GPIO_PIN10_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN10_DRIVER field. + GPIO_GPIO_PIN10_GPIO_PIN10_DRIVER_Msk = 0x4 + // Bit GPIO_PIN10_DRIVER. + GPIO_GPIO_PIN10_GPIO_PIN10_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN10_GPIO_PIN10_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN10_GPIO_PIN10_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN10_SOURCE field. + GPIO_GPIO_PIN10_GPIO_PIN10_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN10_SOURCE field. + GPIO_GPIO_PIN10_GPIO_PIN10_SOURCE_Msk = 0x1 + // Bit GPIO_PIN10_SOURCE. + GPIO_GPIO_PIN10_GPIO_PIN10_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN10_GPIO_PIN10_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN10_GPIO_PIN10_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN11: GPIO_PIN11 + // Position of GPIO_PIN11_WAKEUP_ENABLE field. + GPIO_GPIO_PIN11_GPIO_PIN11_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN11_WAKEUP_ENABLE field. + GPIO_GPIO_PIN11_GPIO_PIN11_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN11_WAKEUP_ENABLE. + GPIO_GPIO_PIN11_GPIO_PIN11_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN11_INT_TYPE field. + GPIO_GPIO_PIN11_GPIO_PIN11_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN11_INT_TYPE field. + GPIO_GPIO_PIN11_GPIO_PIN11_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN11_GPIO_PIN11_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN11_GPIO_PIN11_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN11_GPIO_PIN11_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN11_GPIO_PIN11_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN11_GPIO_PIN11_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN11_GPIO_PIN11_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN11_DRIVER field. + GPIO_GPIO_PIN11_GPIO_PIN11_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN11_DRIVER field. + GPIO_GPIO_PIN11_GPIO_PIN11_DRIVER_Msk = 0x4 + // Bit GPIO_PIN11_DRIVER. + GPIO_GPIO_PIN11_GPIO_PIN11_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN11_GPIO_PIN11_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN11_GPIO_PIN11_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN11_SOURCE field. + GPIO_GPIO_PIN11_GPIO_PIN11_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN11_SOURCE field. + GPIO_GPIO_PIN11_GPIO_PIN11_SOURCE_Msk = 0x1 + // Bit GPIO_PIN11_SOURCE. + GPIO_GPIO_PIN11_GPIO_PIN11_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN11_GPIO_PIN11_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN11_GPIO_PIN11_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN12: GPIO_PIN12 + // Position of GPIO_PIN12_WAKEUP_ENABLE field. + GPIO_GPIO_PIN12_GPIO_PIN12_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN12_WAKEUP_ENABLE field. + GPIO_GPIO_PIN12_GPIO_PIN12_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN12_WAKEUP_ENABLE. + GPIO_GPIO_PIN12_GPIO_PIN12_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN12_INT_TYPE field. + GPIO_GPIO_PIN12_GPIO_PIN12_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN12_INT_TYPE field. + GPIO_GPIO_PIN12_GPIO_PIN12_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN12_GPIO_PIN12_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN12_GPIO_PIN12_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN12_GPIO_PIN12_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN12_GPIO_PIN12_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN12_GPIO_PIN12_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN12_GPIO_PIN12_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN12_DRIVER field. + GPIO_GPIO_PIN12_GPIO_PIN12_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN12_DRIVER field. + GPIO_GPIO_PIN12_GPIO_PIN12_DRIVER_Msk = 0x4 + // Bit GPIO_PIN12_DRIVER. + GPIO_GPIO_PIN12_GPIO_PIN12_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN12_GPIO_PIN12_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN12_GPIO_PIN12_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN12_SOURCE field. + GPIO_GPIO_PIN12_GPIO_PIN12_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN12_SOURCE field. + GPIO_GPIO_PIN12_GPIO_PIN12_SOURCE_Msk = 0x1 + // Bit GPIO_PIN12_SOURCE. + GPIO_GPIO_PIN12_GPIO_PIN12_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN12_GPIO_PIN12_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN12_GPIO_PIN12_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN13: GPIO_PIN13 + // Position of GPIO_PIN13_WAKEUP_ENABLE field. + GPIO_GPIO_PIN13_GPIO_PIN13_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN13_WAKEUP_ENABLE field. + GPIO_GPIO_PIN13_GPIO_PIN13_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN13_WAKEUP_ENABLE. + GPIO_GPIO_PIN13_GPIO_PIN13_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN13_INT_TYPE field. + GPIO_GPIO_PIN13_GPIO_PIN13_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN13_INT_TYPE field. + GPIO_GPIO_PIN13_GPIO_PIN13_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN13_GPIO_PIN13_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN13_GPIO_PIN13_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN13_GPIO_PIN13_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN13_GPIO_PIN13_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN13_GPIO_PIN13_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN13_GPIO_PIN13_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN13_DRIVER field. + GPIO_GPIO_PIN13_GPIO_PIN13_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN13_DRIVER field. + GPIO_GPIO_PIN13_GPIO_PIN13_DRIVER_Msk = 0x4 + // Bit GPIO_PIN13_DRIVER. + GPIO_GPIO_PIN13_GPIO_PIN13_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN13_GPIO_PIN13_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN13_GPIO_PIN13_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN13_SOURCE field. + GPIO_GPIO_PIN13_GPIO_PIN13_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN13_SOURCE field. + GPIO_GPIO_PIN13_GPIO_PIN13_SOURCE_Msk = 0x1 + // Bit GPIO_PIN13_SOURCE. + GPIO_GPIO_PIN13_GPIO_PIN13_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN13_GPIO_PIN13_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN13_GPIO_PIN13_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN14: GPIO_PIN14 + // Position of GPIO_PIN14_WAKEUP_ENABLE field. + GPIO_GPIO_PIN14_GPIO_PIN14_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN14_WAKEUP_ENABLE field. + GPIO_GPIO_PIN14_GPIO_PIN14_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN14_WAKEUP_ENABLE. + GPIO_GPIO_PIN14_GPIO_PIN14_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN14_INT_TYPE field. + GPIO_GPIO_PIN14_GPIO_PIN14_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN14_INT_TYPE field. + GPIO_GPIO_PIN14_GPIO_PIN14_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN14_GPIO_PIN14_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN14_GPIO_PIN14_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN14_GPIO_PIN14_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN14_GPIO_PIN14_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN14_GPIO_PIN14_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN14_GPIO_PIN14_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN14_DRIVER field. + GPIO_GPIO_PIN14_GPIO_PIN14_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN14_DRIVER field. + GPIO_GPIO_PIN14_GPIO_PIN14_DRIVER_Msk = 0x4 + // Bit GPIO_PIN14_DRIVER. + GPIO_GPIO_PIN14_GPIO_PIN14_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN14_GPIO_PIN14_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN14_GPIO_PIN14_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN14_SOURCE field. + GPIO_GPIO_PIN14_GPIO_PIN14_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN14_SOURCE field. + GPIO_GPIO_PIN14_GPIO_PIN14_SOURCE_Msk = 0x1 + // Bit GPIO_PIN14_SOURCE. + GPIO_GPIO_PIN14_GPIO_PIN14_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN14_GPIO_PIN14_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN14_GPIO_PIN14_SOURCE_GPIO_DATA = 0x1 + + // GPIO_PIN15: GPIO_PIN15 + // Position of GPIO_PIN15_WAKEUP_ENABLE field. + GPIO_GPIO_PIN15_GPIO_PIN15_WAKEUP_ENABLE_Pos = 0xa + // Bit mask of GPIO_PIN15_WAKEUP_ENABLE field. + GPIO_GPIO_PIN15_GPIO_PIN15_WAKEUP_ENABLE_Msk = 0x400 + // Bit GPIO_PIN15_WAKEUP_ENABLE. + GPIO_GPIO_PIN15_GPIO_PIN15_WAKEUP_ENABLE = 0x400 + // Position of GPIO_PIN15_INT_TYPE field. + GPIO_GPIO_PIN15_GPIO_PIN15_INT_TYPE_Pos = 0x7 + // Bit mask of GPIO_PIN15_INT_TYPE field. + GPIO_GPIO_PIN15_GPIO_PIN15_INT_TYPE_Msk = 0x380 + // interrupt is disabled + GPIO_GPIO_PIN15_GPIO_PIN15_INT_TYPE_DISABLED = 0x0 + // interrupt is triggered on the positive edge + GPIO_GPIO_PIN15_GPIO_PIN15_INT_TYPE_POSITIVE_EDGE = 0x1 + // interrupt is triggered on the negative edge + GPIO_GPIO_PIN15_GPIO_PIN15_INT_TYPE_NEGATIVE_EDGE = 0x2 + // interrupt is triggered on both edges + GPIO_GPIO_PIN15_GPIO_PIN15_INT_TYPE_BOTH_EDGES = 0x3 + // interrupt is triggered on the low level + GPIO_GPIO_PIN15_GPIO_PIN15_INT_TYPE_LOW_LEVEL = 0x4 + // interrupt is triggered on the high level + GPIO_GPIO_PIN15_GPIO_PIN15_INT_TYPE_HIGH_LEVEL = 0x5 + // Position of GPIO_PIN15_DRIVER field. + GPIO_GPIO_PIN15_GPIO_PIN15_DRIVER_Pos = 0x2 + // Bit mask of GPIO_PIN15_DRIVER field. + GPIO_GPIO_PIN15_GPIO_PIN15_DRIVER_Msk = 0x4 + // Bit GPIO_PIN15_DRIVER. + GPIO_GPIO_PIN15_GPIO_PIN15_DRIVER = 0x4 + // open drain + GPIO_GPIO_PIN15_GPIO_PIN15_DRIVER_OPEN_DRAIN = 0x0 + // normal + GPIO_GPIO_PIN15_GPIO_PIN15_DRIVER_NORMAL = 0x1 + // Position of GPIO_PIN15_SOURCE field. + GPIO_GPIO_PIN15_GPIO_PIN15_SOURCE_Pos = 0x0 + // Bit mask of GPIO_PIN15_SOURCE field. + GPIO_GPIO_PIN15_GPIO_PIN15_SOURCE_Msk = 0x1 + // Bit GPIO_PIN15_SOURCE. + GPIO_GPIO_PIN15_GPIO_PIN15_SOURCE = 0x1 + // sigma-delta + GPIO_GPIO_PIN15_GPIO_PIN15_SOURCE_SIGMA_DELTA = 0x0 + // gpio data + GPIO_GPIO_PIN15_GPIO_PIN15_SOURCE_GPIO_DATA = 0x1 + + // GPIO_SIGMA_DELTA: GPIO_SIGMA_DELTA + // Position of SIGMA_DELTA_ENABLE field. + GPIO_GPIO_SIGMA_DELTA_SIGMA_DELTA_ENABLE_Pos = 0x10 + // Bit mask of SIGMA_DELTA_ENABLE field. + GPIO_GPIO_SIGMA_DELTA_SIGMA_DELTA_ENABLE_Msk = 0x10000 + // Bit SIGMA_DELTA_ENABLE. + GPIO_GPIO_SIGMA_DELTA_SIGMA_DELTA_ENABLE = 0x10000 + // Position of SIGMA_DELTA_PRESCALAR field. + GPIO_GPIO_SIGMA_DELTA_SIGMA_DELTA_PRESCALAR_Pos = 0x8 + // Bit mask of SIGMA_DELTA_PRESCALAR field. + GPIO_GPIO_SIGMA_DELTA_SIGMA_DELTA_PRESCALAR_Msk = 0xff00 + // Position of SIGMA_DELTA_TARGET field. + GPIO_GPIO_SIGMA_DELTA_SIGMA_DELTA_TARGET_Pos = 0x0 + // Bit mask of SIGMA_DELTA_TARGET field. + GPIO_GPIO_SIGMA_DELTA_SIGMA_DELTA_TARGET_Msk = 0xff + + // GPIO_RTC_CALIB_SYNC: Positvie edge of this bit will trigger the RTC-clock-calibration process. + // Position of RTC_CALIB_START field. + GPIO_GPIO_RTC_CALIB_SYNC_RTC_CALIB_START_Pos = 0x1f + // Bit mask of RTC_CALIB_START field. + GPIO_GPIO_RTC_CALIB_SYNC_RTC_CALIB_START_Msk = 0x80000000 + // Bit RTC_CALIB_START. + GPIO_GPIO_RTC_CALIB_SYNC_RTC_CALIB_START = 0x80000000 + // Position of RTC_PERIOD_NUM field. + GPIO_GPIO_RTC_CALIB_SYNC_RTC_PERIOD_NUM_Pos = 0x0 + // Bit mask of RTC_PERIOD_NUM field. + GPIO_GPIO_RTC_CALIB_SYNC_RTC_PERIOD_NUM_Msk = 0x3ff + + // GPIO_RTC_CALIB_VALUE: 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done + // Position of RTC_CALIB_RDY field. + GPIO_GPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY_Pos = 0x1f + // Bit mask of RTC_CALIB_RDY field. + GPIO_GPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY_Msk = 0x80000000 + // Bit RTC_CALIB_RDY. + GPIO_GPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY = 0x80000000 + // Position of RTC_CALIB_RDY_REAL field. + GPIO_GPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY_REAL_Pos = 0x1e + // Bit mask of RTC_CALIB_RDY_REAL field. + GPIO_GPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY_REAL_Msk = 0x40000000 + // Bit RTC_CALIB_RDY_REAL. + GPIO_GPIO_RTC_CALIB_VALUE_RTC_CALIB_RDY_REAL = 0x40000000 + // Position of RTC_CALIB_VALUE field. + GPIO_GPIO_RTC_CALIB_VALUE_RTC_CALIB_VALUE_Pos = 0x0 + // Bit mask of RTC_CALIB_VALUE field. + GPIO_GPIO_RTC_CALIB_VALUE_RTC_CALIB_VALUE_Msk = 0xfffff +) + +// Constants for I2S +const ( + // I2STXFIFO: I2STXFIFO + // Position of Register field. + I2S_I2STXFIFO_Register_Pos = 0x0 + // Bit mask of Register field. + I2S_I2STXFIFO_Register_Msk = 0xffffffff + + // I2SRXFIFO: I2SRXFIFO + // Position of Register field. + I2S_I2SRXFIFO_Register_Pos = 0x0 + // Bit mask of Register field. + I2S_I2SRXFIFO_Register_Msk = 0xffffffff + + // I2SCONF: I2SCONF + // Position of I2S_BCK_DIV_NUM field. + I2S_I2SCONF_I2S_BCK_DIV_NUM_Pos = 0x16 + // Bit mask of I2S_BCK_DIV_NUM field. + I2S_I2SCONF_I2S_BCK_DIV_NUM_Msk = 0xfc00000 + // Position of I2S_CLKM_DIV_NUM field. + I2S_I2SCONF_I2S_CLKM_DIV_NUM_Pos = 0x10 + // Bit mask of I2S_CLKM_DIV_NUM field. + I2S_I2SCONF_I2S_CLKM_DIV_NUM_Msk = 0x3f0000 + // Position of I2S_BITS_MOD field. + I2S_I2SCONF_I2S_BITS_MOD_Pos = 0xc + // Bit mask of I2S_BITS_MOD field. + I2S_I2SCONF_I2S_BITS_MOD_Msk = 0xf000 + // Position of I2S_RECE_MSB_SHIFT field. + I2S_I2SCONF_I2S_RECE_MSB_SHIFT_Pos = 0xb + // Bit mask of I2S_RECE_MSB_SHIFT field. + I2S_I2SCONF_I2S_RECE_MSB_SHIFT_Msk = 0x800 + // Bit I2S_RECE_MSB_SHIFT. + I2S_I2SCONF_I2S_RECE_MSB_SHIFT = 0x800 + // Position of I2S_TRANS_MSB_SHIFT field. + I2S_I2SCONF_I2S_TRANS_MSB_SHIFT_Pos = 0xa + // Bit mask of I2S_TRANS_MSB_SHIFT field. + I2S_I2SCONF_I2S_TRANS_MSB_SHIFT_Msk = 0x400 + // Bit I2S_TRANS_MSB_SHIFT. + I2S_I2SCONF_I2S_TRANS_MSB_SHIFT = 0x400 + // Position of I2S_I2S_RX_START field. + I2S_I2SCONF_I2S_I2S_RX_START_Pos = 0x9 + // Bit mask of I2S_I2S_RX_START field. + I2S_I2SCONF_I2S_I2S_RX_START_Msk = 0x200 + // Bit I2S_I2S_RX_START. + I2S_I2SCONF_I2S_I2S_RX_START = 0x200 + // Position of I2S_I2S_TX_START field. + I2S_I2SCONF_I2S_I2S_TX_START_Pos = 0x8 + // Bit mask of I2S_I2S_TX_START field. + I2S_I2SCONF_I2S_I2S_TX_START_Msk = 0x100 + // Bit I2S_I2S_TX_START. + I2S_I2SCONF_I2S_I2S_TX_START = 0x100 + // Position of I2S_MSB_RIGHT field. + I2S_I2SCONF_I2S_MSB_RIGHT_Pos = 0x7 + // Bit mask of I2S_MSB_RIGHT field. + I2S_I2SCONF_I2S_MSB_RIGHT_Msk = 0x80 + // Bit I2S_MSB_RIGHT. + I2S_I2SCONF_I2S_MSB_RIGHT = 0x80 + // Position of I2S_RIGHT_FIRST field. + I2S_I2SCONF_I2S_RIGHT_FIRST_Pos = 0x6 + // Bit mask of I2S_RIGHT_FIRST field. + I2S_I2SCONF_I2S_RIGHT_FIRST_Msk = 0x40 + // Bit I2S_RIGHT_FIRST. + I2S_I2SCONF_I2S_RIGHT_FIRST = 0x40 + // Position of I2S_RECE_SLAVE_MOD field. + I2S_I2SCONF_I2S_RECE_SLAVE_MOD_Pos = 0x5 + // Bit mask of I2S_RECE_SLAVE_MOD field. + I2S_I2SCONF_I2S_RECE_SLAVE_MOD_Msk = 0x20 + // Bit I2S_RECE_SLAVE_MOD. + I2S_I2SCONF_I2S_RECE_SLAVE_MOD = 0x20 + // Position of I2S_TRANS_SLAVE_MOD field. + I2S_I2SCONF_I2S_TRANS_SLAVE_MOD_Pos = 0x4 + // Bit mask of I2S_TRANS_SLAVE_MOD field. + I2S_I2SCONF_I2S_TRANS_SLAVE_MOD_Msk = 0x10 + // Bit I2S_TRANS_SLAVE_MOD. + I2S_I2SCONF_I2S_TRANS_SLAVE_MOD = 0x10 + // Position of I2S_I2S_RX_FIFO_RESET field. + I2S_I2SCONF_I2S_I2S_RX_FIFO_RESET_Pos = 0x3 + // Bit mask of I2S_I2S_RX_FIFO_RESET field. + I2S_I2SCONF_I2S_I2S_RX_FIFO_RESET_Msk = 0x8 + // Bit I2S_I2S_RX_FIFO_RESET. + I2S_I2SCONF_I2S_I2S_RX_FIFO_RESET = 0x8 + // Position of I2S_I2S_TX_FIFO_RESET field. + I2S_I2SCONF_I2S_I2S_TX_FIFO_RESET_Pos = 0x2 + // Bit mask of I2S_I2S_TX_FIFO_RESET field. + I2S_I2SCONF_I2S_I2S_TX_FIFO_RESET_Msk = 0x4 + // Bit I2S_I2S_TX_FIFO_RESET. + I2S_I2SCONF_I2S_I2S_TX_FIFO_RESET = 0x4 + // Position of I2S_I2S_RX_RESET field. + I2S_I2SCONF_I2S_I2S_RX_RESET_Pos = 0x1 + // Bit mask of I2S_I2S_RX_RESET field. + I2S_I2SCONF_I2S_I2S_RX_RESET_Msk = 0x2 + // Bit I2S_I2S_RX_RESET. + I2S_I2SCONF_I2S_I2S_RX_RESET = 0x2 + // Position of I2S_I2S_TX_RESET field. + I2S_I2SCONF_I2S_I2S_TX_RESET_Pos = 0x0 + // Bit mask of I2S_I2S_TX_RESET field. + I2S_I2SCONF_I2S_I2S_TX_RESET_Msk = 0x1 + // Bit I2S_I2S_TX_RESET. + I2S_I2SCONF_I2S_I2S_TX_RESET = 0x1 + + // I2SINT_RAW: I2SINT_RAW + // Position of I2S_I2S_TX_REMPTY_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_TX_REMPTY_INT_RAW_Pos = 0x5 + // Bit mask of I2S_I2S_TX_REMPTY_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_TX_REMPTY_INT_RAW_Msk = 0x20 + // Bit I2S_I2S_TX_REMPTY_INT_RAW. + I2S_I2SINT_RAW_I2S_I2S_TX_REMPTY_INT_RAW = 0x20 + // Position of I2S_I2S_TX_WFULL_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_TX_WFULL_INT_RAW_Pos = 0x4 + // Bit mask of I2S_I2S_TX_WFULL_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_TX_WFULL_INT_RAW_Msk = 0x10 + // Bit I2S_I2S_TX_WFULL_INT_RAW. + I2S_I2SINT_RAW_I2S_I2S_TX_WFULL_INT_RAW = 0x10 + // Position of I2S_I2S_RX_REMPTY_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_RX_REMPTY_INT_RAW_Pos = 0x3 + // Bit mask of I2S_I2S_RX_REMPTY_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_RX_REMPTY_INT_RAW_Msk = 0x8 + // Bit I2S_I2S_RX_REMPTY_INT_RAW. + I2S_I2SINT_RAW_I2S_I2S_RX_REMPTY_INT_RAW = 0x8 + // Position of I2S_I2S_RX_WFULL_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_RX_WFULL_INT_RAW_Pos = 0x2 + // Bit mask of I2S_I2S_RX_WFULL_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_RX_WFULL_INT_RAW_Msk = 0x4 + // Bit I2S_I2S_RX_WFULL_INT_RAW. + I2S_I2SINT_RAW_I2S_I2S_RX_WFULL_INT_RAW = 0x4 + // Position of I2S_I2S_TX_PUT_DATA_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_TX_PUT_DATA_INT_RAW_Pos = 0x1 + // Bit mask of I2S_I2S_TX_PUT_DATA_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_TX_PUT_DATA_INT_RAW_Msk = 0x2 + // Bit I2S_I2S_TX_PUT_DATA_INT_RAW. + I2S_I2SINT_RAW_I2S_I2S_TX_PUT_DATA_INT_RAW = 0x2 + // Position of I2S_I2S_RX_TAKE_DATA_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_RX_TAKE_DATA_INT_RAW_Pos = 0x0 + // Bit mask of I2S_I2S_RX_TAKE_DATA_INT_RAW field. + I2S_I2SINT_RAW_I2S_I2S_RX_TAKE_DATA_INT_RAW_Msk = 0x1 + // Bit I2S_I2S_RX_TAKE_DATA_INT_RAW. + I2S_I2SINT_RAW_I2S_I2S_RX_TAKE_DATA_INT_RAW = 0x1 + + // I2SINT_ST: I2SINT_ST + // Position of I2S_I2S_TX_REMPTY_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_TX_REMPTY_INT_ST_Pos = 0x5 + // Bit mask of I2S_I2S_TX_REMPTY_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_TX_REMPTY_INT_ST_Msk = 0x20 + // Bit I2S_I2S_TX_REMPTY_INT_ST. + I2S_I2SINT_ST_I2S_I2S_TX_REMPTY_INT_ST = 0x20 + // Position of I2S_I2S_TX_WFULL_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_TX_WFULL_INT_ST_Pos = 0x4 + // Bit mask of I2S_I2S_TX_WFULL_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_TX_WFULL_INT_ST_Msk = 0x10 + // Bit I2S_I2S_TX_WFULL_INT_ST. + I2S_I2SINT_ST_I2S_I2S_TX_WFULL_INT_ST = 0x10 + // Position of I2S_I2S_RX_REMPTY_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_RX_REMPTY_INT_ST_Pos = 0x3 + // Bit mask of I2S_I2S_RX_REMPTY_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_RX_REMPTY_INT_ST_Msk = 0x8 + // Bit I2S_I2S_RX_REMPTY_INT_ST. + I2S_I2SINT_ST_I2S_I2S_RX_REMPTY_INT_ST = 0x8 + // Position of I2S_I2S_RX_WFULL_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_RX_WFULL_INT_ST_Pos = 0x2 + // Bit mask of I2S_I2S_RX_WFULL_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_RX_WFULL_INT_ST_Msk = 0x4 + // Bit I2S_I2S_RX_WFULL_INT_ST. + I2S_I2SINT_ST_I2S_I2S_RX_WFULL_INT_ST = 0x4 + // Position of I2S_I2S_TX_PUT_DATA_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_TX_PUT_DATA_INT_ST_Pos = 0x1 + // Bit mask of I2S_I2S_TX_PUT_DATA_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_TX_PUT_DATA_INT_ST_Msk = 0x2 + // Bit I2S_I2S_TX_PUT_DATA_INT_ST. + I2S_I2SINT_ST_I2S_I2S_TX_PUT_DATA_INT_ST = 0x2 + // Position of I2S_I2S_RX_TAKE_DATA_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_RX_TAKE_DATA_INT_ST_Pos = 0x0 + // Bit mask of I2S_I2S_RX_TAKE_DATA_INT_ST field. + I2S_I2SINT_ST_I2S_I2S_RX_TAKE_DATA_INT_ST_Msk = 0x1 + // Bit I2S_I2S_RX_TAKE_DATA_INT_ST. + I2S_I2SINT_ST_I2S_I2S_RX_TAKE_DATA_INT_ST = 0x1 + + // I2SINT_ENA: I2SINT_ENA + // Position of I2S_I2S_TX_REMPTY_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_TX_REMPTY_INT_ENA_Pos = 0x5 + // Bit mask of I2S_I2S_TX_REMPTY_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_TX_REMPTY_INT_ENA_Msk = 0x20 + // Bit I2S_I2S_TX_REMPTY_INT_ENA. + I2S_I2SINT_ENA_I2S_I2S_TX_REMPTY_INT_ENA = 0x20 + // Position of I2S_I2S_TX_WFULL_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_TX_WFULL_INT_ENA_Pos = 0x4 + // Bit mask of I2S_I2S_TX_WFULL_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_TX_WFULL_INT_ENA_Msk = 0x10 + // Bit I2S_I2S_TX_WFULL_INT_ENA. + I2S_I2SINT_ENA_I2S_I2S_TX_WFULL_INT_ENA = 0x10 + // Position of I2S_I2S_RX_REMPTY_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_RX_REMPTY_INT_ENA_Pos = 0x3 + // Bit mask of I2S_I2S_RX_REMPTY_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_RX_REMPTY_INT_ENA_Msk = 0x8 + // Bit I2S_I2S_RX_REMPTY_INT_ENA. + I2S_I2SINT_ENA_I2S_I2S_RX_REMPTY_INT_ENA = 0x8 + // Position of I2S_I2S_RX_WFULL_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_RX_WFULL_INT_ENA_Pos = 0x2 + // Bit mask of I2S_I2S_RX_WFULL_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_RX_WFULL_INT_ENA_Msk = 0x4 + // Bit I2S_I2S_RX_WFULL_INT_ENA. + I2S_I2SINT_ENA_I2S_I2S_RX_WFULL_INT_ENA = 0x4 + // Position of I2S_I2S_TX_PUT_DATA_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_TX_PUT_DATA_INT_ENA_Pos = 0x1 + // Bit mask of I2S_I2S_TX_PUT_DATA_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_TX_PUT_DATA_INT_ENA_Msk = 0x2 + // Bit I2S_I2S_TX_PUT_DATA_INT_ENA. + I2S_I2SINT_ENA_I2S_I2S_TX_PUT_DATA_INT_ENA = 0x2 + // Position of I2S_I2S_RX_TAKE_DATA_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_RX_TAKE_DATA_INT_ENA_Pos = 0x0 + // Bit mask of I2S_I2S_RX_TAKE_DATA_INT_ENA field. + I2S_I2SINT_ENA_I2S_I2S_RX_TAKE_DATA_INT_ENA_Msk = 0x1 + // Bit I2S_I2S_RX_TAKE_DATA_INT_ENA. + I2S_I2SINT_ENA_I2S_I2S_RX_TAKE_DATA_INT_ENA = 0x1 + + // I2SINT_CLR: I2SINT_CLR + // Position of I2S_I2S_TX_REMPTY_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_TX_REMPTY_INT_CLR_Pos = 0x5 + // Bit mask of I2S_I2S_TX_REMPTY_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_TX_REMPTY_INT_CLR_Msk = 0x20 + // Bit I2S_I2S_TX_REMPTY_INT_CLR. + I2S_I2SINT_CLR_I2S_I2S_TX_REMPTY_INT_CLR = 0x20 + // Position of I2S_I2S_TX_WFULL_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_TX_WFULL_INT_CLR_Pos = 0x4 + // Bit mask of I2S_I2S_TX_WFULL_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_TX_WFULL_INT_CLR_Msk = 0x10 + // Bit I2S_I2S_TX_WFULL_INT_CLR. + I2S_I2SINT_CLR_I2S_I2S_TX_WFULL_INT_CLR = 0x10 + // Position of I2S_I2S_RX_REMPTY_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_RX_REMPTY_INT_CLR_Pos = 0x3 + // Bit mask of I2S_I2S_RX_REMPTY_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_RX_REMPTY_INT_CLR_Msk = 0x8 + // Bit I2S_I2S_RX_REMPTY_INT_CLR. + I2S_I2SINT_CLR_I2S_I2S_RX_REMPTY_INT_CLR = 0x8 + // Position of I2S_I2S_RX_WFULL_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_RX_WFULL_INT_CLR_Pos = 0x2 + // Bit mask of I2S_I2S_RX_WFULL_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_RX_WFULL_INT_CLR_Msk = 0x4 + // Bit I2S_I2S_RX_WFULL_INT_CLR. + I2S_I2SINT_CLR_I2S_I2S_RX_WFULL_INT_CLR = 0x4 + // Position of I2S_I2S_PUT_DATA_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_PUT_DATA_INT_CLR_Pos = 0x1 + // Bit mask of I2S_I2S_PUT_DATA_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_PUT_DATA_INT_CLR_Msk = 0x2 + // Bit I2S_I2S_PUT_DATA_INT_CLR. + I2S_I2SINT_CLR_I2S_I2S_PUT_DATA_INT_CLR = 0x2 + // Position of I2S_I2S_TAKE_DATA_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_TAKE_DATA_INT_CLR_Pos = 0x0 + // Bit mask of I2S_I2S_TAKE_DATA_INT_CLR field. + I2S_I2SINT_CLR_I2S_I2S_TAKE_DATA_INT_CLR_Msk = 0x1 + // Bit I2S_I2S_TAKE_DATA_INT_CLR. + I2S_I2SINT_CLR_I2S_I2S_TAKE_DATA_INT_CLR = 0x1 + + // I2STIMING: I2STIMING + // Position of I2S_TRANS_BCK_IN_INV field. + I2S_I2STIMING_I2S_TRANS_BCK_IN_INV_Pos = 0x16 + // Bit mask of I2S_TRANS_BCK_IN_INV field. + I2S_I2STIMING_I2S_TRANS_BCK_IN_INV_Msk = 0x400000 + // Bit I2S_TRANS_BCK_IN_INV. + I2S_I2STIMING_I2S_TRANS_BCK_IN_INV = 0x400000 + // Position of I2S_RECE_DSYNC_SW field. + I2S_I2STIMING_I2S_RECE_DSYNC_SW_Pos = 0x15 + // Bit mask of I2S_RECE_DSYNC_SW field. + I2S_I2STIMING_I2S_RECE_DSYNC_SW_Msk = 0x200000 + // Bit I2S_RECE_DSYNC_SW. + I2S_I2STIMING_I2S_RECE_DSYNC_SW = 0x200000 + // Position of I2S_TRANS_DSYNC_SW field. + I2S_I2STIMING_I2S_TRANS_DSYNC_SW_Pos = 0x14 + // Bit mask of I2S_TRANS_DSYNC_SW field. + I2S_I2STIMING_I2S_TRANS_DSYNC_SW_Msk = 0x100000 + // Bit I2S_TRANS_DSYNC_SW. + I2S_I2STIMING_I2S_TRANS_DSYNC_SW = 0x100000 + // Position of I2S_RECE_BCK_OUT_DELAY field. + I2S_I2STIMING_I2S_RECE_BCK_OUT_DELAY_Pos = 0x12 + // Bit mask of I2S_RECE_BCK_OUT_DELAY field. + I2S_I2STIMING_I2S_RECE_BCK_OUT_DELAY_Msk = 0xc0000 + // Position of I2S_RECE_WS_OUT_DELAY field. + I2S_I2STIMING_I2S_RECE_WS_OUT_DELAY_Pos = 0x10 + // Bit mask of I2S_RECE_WS_OUT_DELAY field. + I2S_I2STIMING_I2S_RECE_WS_OUT_DELAY_Msk = 0x30000 + // Position of I2S_TRANS_SD_OUT_DELAY field. + I2S_I2STIMING_I2S_TRANS_SD_OUT_DELAY_Pos = 0xe + // Bit mask of I2S_TRANS_SD_OUT_DELAY field. + I2S_I2STIMING_I2S_TRANS_SD_OUT_DELAY_Msk = 0xc000 + // Position of I2S_TRANS_WS_OUT_DELAY field. + I2S_I2STIMING_I2S_TRANS_WS_OUT_DELAY_Pos = 0xc + // Bit mask of I2S_TRANS_WS_OUT_DELAY field. + I2S_I2STIMING_I2S_TRANS_WS_OUT_DELAY_Msk = 0x3000 + // Position of I2S_TRANS_BCK_OUT_DELAY field. + I2S_I2STIMING_I2S_TRANS_BCK_OUT_DELAY_Pos = 0xa + // Bit mask of I2S_TRANS_BCK_OUT_DELAY field. + I2S_I2STIMING_I2S_TRANS_BCK_OUT_DELAY_Msk = 0xc00 + // Position of I2S_RECE_SD_IN_DELAY field. + I2S_I2STIMING_I2S_RECE_SD_IN_DELAY_Pos = 0x8 + // Bit mask of I2S_RECE_SD_IN_DELAY field. + I2S_I2STIMING_I2S_RECE_SD_IN_DELAY_Msk = 0x300 + // Position of I2S_RECE_WS_IN_DELAY field. + I2S_I2STIMING_I2S_RECE_WS_IN_DELAY_Pos = 0x6 + // Bit mask of I2S_RECE_WS_IN_DELAY field. + I2S_I2STIMING_I2S_RECE_WS_IN_DELAY_Msk = 0xc0 + // Position of I2S_RECE_BCK_IN_DELAY field. + I2S_I2STIMING_I2S_RECE_BCK_IN_DELAY_Pos = 0x4 + // Bit mask of I2S_RECE_BCK_IN_DELAY field. + I2S_I2STIMING_I2S_RECE_BCK_IN_DELAY_Msk = 0x30 + // Position of I2S_TRANS_WS_IN_DELAY field. + I2S_I2STIMING_I2S_TRANS_WS_IN_DELAY_Pos = 0x2 + // Bit mask of I2S_TRANS_WS_IN_DELAY field. + I2S_I2STIMING_I2S_TRANS_WS_IN_DELAY_Msk = 0xc + // Position of I2S_TRANS_BCK_IN_DELAY field. + I2S_I2STIMING_I2S_TRANS_BCK_IN_DELAY_Pos = 0x0 + // Bit mask of I2S_TRANS_BCK_IN_DELAY field. + I2S_I2STIMING_I2S_TRANS_BCK_IN_DELAY_Msk = 0x3 + + // I2S_FIFO_CONF: I2S_FIFO_CONF + // Position of I2S_I2S_RX_FIFO_MOD field. + I2S_I2S_FIFO_CONF_I2S_I2S_RX_FIFO_MOD_Pos = 0x10 + // Bit mask of I2S_I2S_RX_FIFO_MOD field. + I2S_I2S_FIFO_CONF_I2S_I2S_RX_FIFO_MOD_Msk = 0x70000 + // Position of I2S_I2S_TX_FIFO_MOD field. + I2S_I2S_FIFO_CONF_I2S_I2S_TX_FIFO_MOD_Pos = 0xd + // Bit mask of I2S_I2S_TX_FIFO_MOD field. + I2S_I2S_FIFO_CONF_I2S_I2S_TX_FIFO_MOD_Msk = 0xe000 + // Position of I2S_I2S_DSCR_EN field. + I2S_I2S_FIFO_CONF_I2S_I2S_DSCR_EN_Pos = 0xc + // Bit mask of I2S_I2S_DSCR_EN field. + I2S_I2S_FIFO_CONF_I2S_I2S_DSCR_EN_Msk = 0x1000 + // Bit I2S_I2S_DSCR_EN. + I2S_I2S_FIFO_CONF_I2S_I2S_DSCR_EN = 0x1000 + // Position of I2S_I2S_TX_DATA_NUM field. + I2S_I2S_FIFO_CONF_I2S_I2S_TX_DATA_NUM_Pos = 0x6 + // Bit mask of I2S_I2S_TX_DATA_NUM field. + I2S_I2S_FIFO_CONF_I2S_I2S_TX_DATA_NUM_Msk = 0xfc0 + // Position of I2S_I2S_RX_DATA_NUM field. + I2S_I2S_FIFO_CONF_I2S_I2S_RX_DATA_NUM_Pos = 0x0 + // Bit mask of I2S_I2S_RX_DATA_NUM field. + I2S_I2S_FIFO_CONF_I2S_I2S_RX_DATA_NUM_Msk = 0x3f + + // I2SRXEOF_NUM: I2SRXEOF_NUM + // Position of I2S_I2S_RX_EOF_NUM field. + I2S_I2SRXEOF_NUM_I2S_I2S_RX_EOF_NUM_Pos = 0x0 + // Bit mask of I2S_I2S_RX_EOF_NUM field. + I2S_I2SRXEOF_NUM_I2S_I2S_RX_EOF_NUM_Msk = 0xffffffff + + // I2SCONF_SIGLE_DATA: I2SCONF_SIGLE_DATA + // Position of I2S_I2S_SIGLE_DATA field. + I2S_I2SCONF_SIGLE_DATA_I2S_I2S_SIGLE_DATA_Pos = 0x0 + // Bit mask of I2S_I2S_SIGLE_DATA field. + I2S_I2SCONF_SIGLE_DATA_I2S_I2S_SIGLE_DATA_Msk = 0xffffffff +) + +// Constants for IO_MUX +const ( + // IO_MUX_CONF: IO_MUX_CONF + // Position of SPI0_CLK_EQU_SYS_CLK field. + IO_MUX_IO_MUX_CONF_SPI0_CLK_EQU_SYS_CLK_Pos = 0x8 + // Bit mask of SPI0_CLK_EQU_SYS_CLK field. + IO_MUX_IO_MUX_CONF_SPI0_CLK_EQU_SYS_CLK_Msk = 0x100 + // Bit SPI0_CLK_EQU_SYS_CLK. + IO_MUX_IO_MUX_CONF_SPI0_CLK_EQU_SYS_CLK = 0x100 + // Position of SPI1_CLK_EQU_SYS_CLK field. + IO_MUX_IO_MUX_CONF_SPI1_CLK_EQU_SYS_CLK_Pos = 0x9 + // Bit mask of SPI1_CLK_EQU_SYS_CLK field. + IO_MUX_IO_MUX_CONF_SPI1_CLK_EQU_SYS_CLK_Msk = 0x200 + // Bit SPI1_CLK_EQU_SYS_CLK. + IO_MUX_IO_MUX_CONF_SPI1_CLK_EQU_SYS_CLK = 0x200 + + // IO_MUX_MTDI: IO_MUX_MTDI + // Position of Register field. + IO_MUX_IO_MUX_MTDI_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_MTDI_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_MTDI_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_MTDI_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_MTDI_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_MTDI_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_MTDI_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_MTDI_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_MTDI_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_MTDI_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_MTDI_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_MTDI_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_MTDI_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_MTDI_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_MTDI_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_MTDI_SLEEP_ENABLE = 0x1 + + // IO_MUX_MTCK: IO_MUX_MTCK + // Position of Register field. + IO_MUX_IO_MUX_MTCK_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_MTCK_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_MTCK_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_MTCK_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_MTCK_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_MTCK_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_MTCK_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_MTCK_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_MTCK_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_MTCK_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_MTCK_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_MTCK_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_MTCK_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_MTCK_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_MTCK_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_MTCK_SLEEP_ENABLE = 0x1 + + // IO_MUX_MTMS: IO_MUX_MTMS + // Position of Register field. + IO_MUX_IO_MUX_MTMS_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_MTMS_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_MTMS_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_MTMS_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_MTMS_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_MTMS_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_MTMS_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_MTMS_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_MTMS_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_MTMS_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_MTMS_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_MTMS_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_MTMS_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_MTMS_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_MTMS_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_MTMS_SLEEP_ENABLE = 0x1 + + // IO_MUX_MTDO: IO_MUX_MTDO + // Position of Register field. + IO_MUX_IO_MUX_MTDO_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_MTDO_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_MTDO_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_MTDO_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_MTDO_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_MTDO_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_MTDO_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_MTDO_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_MTDO_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_MTDO_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_MTDO_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_MTDO_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_MTDO_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_MTDO_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_MTDO_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_MTDO_SLEEP_ENABLE = 0x1 + + // IO_MUX_U0RXD: IO_MUX_U0RXD + // Position of Register field. + IO_MUX_IO_MUX_U0RXD_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_U0RXD_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_U0RXD_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_U0RXD_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_U0RXD_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_U0RXD_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_U0RXD_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_U0RXD_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_U0RXD_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_U0RXD_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_U0RXD_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_U0RXD_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_U0RXD_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_U0RXD_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_U0RXD_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_U0RXD_SLEEP_ENABLE = 0x1 + + // IO_MUX_U0TXD: IO_MUX_U0TXD + // Position of Register field. + IO_MUX_IO_MUX_U0TXD_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_U0TXD_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_U0TXD_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_U0TXD_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_U0TXD_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_U0TXD_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_U0TXD_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_U0TXD_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_U0TXD_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_U0TXD_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_U0TXD_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_U0TXD_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_U0TXD_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_U0TXD_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_U0TXD_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_U0TXD_SLEEP_ENABLE = 0x1 + + // IO_MUX_SD_CLK: IO_MUX_SD_CLK + // Position of Register field. + IO_MUX_IO_MUX_SD_CLK_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_SD_CLK_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_CLK_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_CLK_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_CLK_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_CLK_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_SD_CLK_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_SD_CLK_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_SD_CLK_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_SD_CLK_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_CLK_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_CLK_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_SD_CLK_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_CLK_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_CLK_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_SD_CLK_SLEEP_ENABLE = 0x1 + + // IO_MUX_SD_DATA0: IO_MUX_SD_DATA0 + // Position of Register field. + IO_MUX_IO_MUX_SD_DATA0_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_SD_DATA0_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_DATA0_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_DATA0_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_DATA0_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_DATA0_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_SD_DATA0_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_SD_DATA0_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_SD_DATA0_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_SD_DATA0_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_DATA0_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_DATA0_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_SD_DATA0_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_DATA0_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_DATA0_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_SD_DATA0_SLEEP_ENABLE = 0x1 + + // IO_MUX_SD_DATA1: IO_MUX_SD_DATA1 + // Position of Register field. + IO_MUX_IO_MUX_SD_DATA1_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_SD_DATA1_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_DATA1_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_DATA1_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_DATA1_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_DATA1_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_SD_DATA1_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_SD_DATA1_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_SD_DATA1_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_SD_DATA1_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_DATA1_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_DATA1_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_SD_DATA1_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_DATA1_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_DATA1_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_SD_DATA1_SLEEP_ENABLE = 0x1 + + // IO_MUX_SD_DATA2: IO_MUX_SD_DATA2 + // Position of Register field. + IO_MUX_IO_MUX_SD_DATA2_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_SD_DATA2_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_DATA2_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_DATA2_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_DATA2_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_DATA2_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_SD_DATA2_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_SD_DATA2_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_SD_DATA2_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_SD_DATA2_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_DATA2_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_DATA2_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_SD_DATA2_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_DATA2_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_DATA2_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_SD_DATA2_SLEEP_ENABLE = 0x1 + + // IO_MUX_SD_DATA3: IO_MUX_SD_DATA3 + // Position of Register field. + IO_MUX_IO_MUX_SD_DATA3_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_SD_DATA3_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_DATA3_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_DATA3_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_DATA3_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_DATA3_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_SD_DATA3_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_SD_DATA3_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_SD_DATA3_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_SD_DATA3_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_DATA3_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_DATA3_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_SD_DATA3_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_DATA3_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_DATA3_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_SD_DATA3_SLEEP_ENABLE = 0x1 + + // IO_MUX_SD_CMD: IO_MUX_SD_CMD + // Position of Register field. + IO_MUX_IO_MUX_SD_CMD_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_SD_CMD_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_CMD_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_SD_CMD_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_CMD_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_SD_CMD_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_SD_CMD_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_SD_CMD_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_SD_CMD_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_SD_CMD_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_CMD_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_SD_CMD_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_SD_CMD_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_CMD_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_SD_CMD_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_SD_CMD_SLEEP_ENABLE = 0x1 + + // IO_MUX_GPIO0: IO_MUX_GPIO0 + // Position of Register field. + IO_MUX_IO_MUX_GPIO0_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_GPIO0_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_GPIO0_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_GPIO0_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_GPIO0_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_GPIO0_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_GPIO0_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_GPIO0_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_GPIO0_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_GPIO0_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_GPIO0_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_GPIO0_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_GPIO0_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_GPIO0_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_GPIO0_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_GPIO0_SLEEP_ENABLE = 0x1 + + // IO_MUX_GPIO2: IO_MUX_GPIO2 + // Position of Register field. + IO_MUX_IO_MUX_GPIO2_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_GPIO2_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_GPIO2_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_GPIO2_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_GPIO2_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_GPIO2_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_GPIO2_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_GPIO2_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_GPIO2_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_GPIO2_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_GPIO2_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_GPIO2_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_GPIO2_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_GPIO2_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_GPIO2_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_GPIO2_SLEEP_ENABLE = 0x1 + + // IO_MUX_GPIO4: IO_MUX_GPIO4 + // Position of Register field. + IO_MUX_IO_MUX_GPIO4_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_GPIO4_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_GPIO4_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_GPIO4_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_GPIO4_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_GPIO4_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_GPIO4_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_GPIO4_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_GPIO4_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_GPIO4_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_GPIO4_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_GPIO4_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_GPIO4_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_GPIO4_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_GPIO4_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_GPIO4_SLEEP_ENABLE = 0x1 + + // IO_MUX_GPIO5: IO_MUX_GPIO5 + // Position of Register field. + IO_MUX_IO_MUX_GPIO5_Register_Pos = 0x0 + // Bit mask of Register field. + IO_MUX_IO_MUX_GPIO5_Register_Msk = 0xffffffff + // Position of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_GPIO5_FUNCTION_SELECT_LOW_BITS_Pos = 0x4 + // Bit mask of FUNCTION_SELECT_LOW_BITS field. + IO_MUX_IO_MUX_GPIO5_FUNCTION_SELECT_LOW_BITS_Msk = 0x30 + // Position of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_GPIO5_FUNCTION_SELECT_HIGH_BIT_Pos = 0x8 + // Bit mask of FUNCTION_SELECT_HIGH_BIT field. + IO_MUX_IO_MUX_GPIO5_FUNCTION_SELECT_HIGH_BIT_Msk = 0x100 + // Bit FUNCTION_SELECT_HIGH_BIT. + IO_MUX_IO_MUX_GPIO5_FUNCTION_SELECT_HIGH_BIT = 0x100 + // Position of PULLUP field. + IO_MUX_IO_MUX_GPIO5_PULLUP_Pos = 0x7 + // Bit mask of PULLUP field. + IO_MUX_IO_MUX_GPIO5_PULLUP_Msk = 0x80 + // Bit PULLUP. + IO_MUX_IO_MUX_GPIO5_PULLUP = 0x80 + // Position of SLEEP_PULLUP field. + IO_MUX_IO_MUX_GPIO5_SLEEP_PULLUP_Pos = 0x3 + // Bit mask of SLEEP_PULLUP field. + IO_MUX_IO_MUX_GPIO5_SLEEP_PULLUP_Msk = 0x8 + // Bit SLEEP_PULLUP. + IO_MUX_IO_MUX_GPIO5_SLEEP_PULLUP = 0x8 + // Position of SLEEP_ENABLE field. + IO_MUX_IO_MUX_GPIO5_SLEEP_ENABLE_Pos = 0x0 + // Bit mask of SLEEP_ENABLE field. + IO_MUX_IO_MUX_GPIO5_SLEEP_ENABLE_Msk = 0x1 + // Bit SLEEP_ENABLE. + IO_MUX_IO_MUX_GPIO5_SLEEP_ENABLE = 0x1 +) + +// Constants for RTC +const ( + // RTC_STATE1: RTC_STATE1 + // Position of Register field. + RTC_RTC_STATE1_Register_Pos = 0x0 + // Bit mask of Register field. + RTC_RTC_STATE1_Register_Msk = 0xffffffff + + // RTC_STORE0: RTC_STORE0 + // Position of Register field. + RTC_RTC_STORE0_Register_Pos = 0x0 + // Bit mask of Register field. + RTC_RTC_STORE0_Register_Msk = 0xffffffff +) + +// Constants for SLC +const ( + // SLC_CONF0: SLC_CONF0 + // Position of SLC_MODE field. + SLC_SLC_CONF0_SLC_MODE_Pos = 0xc + // Bit mask of SLC_MODE field. + SLC_SLC_CONF0_SLC_MODE_Msk = 0x3000 + // Position of SLC_DATA_BURST_EN field. + SLC_SLC_CONF0_SLC_DATA_BURST_EN_Pos = 0x9 + // Bit mask of SLC_DATA_BURST_EN field. + SLC_SLC_CONF0_SLC_DATA_BURST_EN_Msk = 0x200 + // Bit SLC_DATA_BURST_EN. + SLC_SLC_CONF0_SLC_DATA_BURST_EN = 0x200 + // Position of SLC_DSCR_BURST_EN field. + SLC_SLC_CONF0_SLC_DSCR_BURST_EN_Pos = 0x8 + // Bit mask of SLC_DSCR_BURST_EN field. + SLC_SLC_CONF0_SLC_DSCR_BURST_EN_Msk = 0x100 + // Bit SLC_DSCR_BURST_EN. + SLC_SLC_CONF0_SLC_DSCR_BURST_EN = 0x100 + // Position of SLC_RX_NO_RESTART_CLR field. + SLC_SLC_CONF0_SLC_RX_NO_RESTART_CLR_Pos = 0x7 + // Bit mask of SLC_RX_NO_RESTART_CLR field. + SLC_SLC_CONF0_SLC_RX_NO_RESTART_CLR_Msk = 0x80 + // Bit SLC_RX_NO_RESTART_CLR. + SLC_SLC_CONF0_SLC_RX_NO_RESTART_CLR = 0x80 + // Position of SLC_RX_AUTO_WRBACK field. + SLC_SLC_CONF0_SLC_RX_AUTO_WRBACK_Pos = 0x6 + // Bit mask of SLC_RX_AUTO_WRBACK field. + SLC_SLC_CONF0_SLC_RX_AUTO_WRBACK_Msk = 0x40 + // Bit SLC_RX_AUTO_WRBACK. + SLC_SLC_CONF0_SLC_RX_AUTO_WRBACK = 0x40 + // Position of SLC_RX_LOOP_TEST field. + SLC_SLC_CONF0_SLC_RX_LOOP_TEST_Pos = 0x5 + // Bit mask of SLC_RX_LOOP_TEST field. + SLC_SLC_CONF0_SLC_RX_LOOP_TEST_Msk = 0x20 + // Bit SLC_RX_LOOP_TEST. + SLC_SLC_CONF0_SLC_RX_LOOP_TEST = 0x20 + // Position of SLC_TX_LOOP_TEST field. + SLC_SLC_CONF0_SLC_TX_LOOP_TEST_Pos = 0x4 + // Bit mask of SLC_TX_LOOP_TEST field. + SLC_SLC_CONF0_SLC_TX_LOOP_TEST_Msk = 0x10 + // Bit SLC_TX_LOOP_TEST. + SLC_SLC_CONF0_SLC_TX_LOOP_TEST = 0x10 + // Position of SLC_AHBM_RST field. + SLC_SLC_CONF0_SLC_AHBM_RST_Pos = 0x3 + // Bit mask of SLC_AHBM_RST field. + SLC_SLC_CONF0_SLC_AHBM_RST_Msk = 0x8 + // Bit SLC_AHBM_RST. + SLC_SLC_CONF0_SLC_AHBM_RST = 0x8 + // Position of SLC_AHBM_FIFO_RST field. + SLC_SLC_CONF0_SLC_AHBM_FIFO_RST_Pos = 0x2 + // Bit mask of SLC_AHBM_FIFO_RST field. + SLC_SLC_CONF0_SLC_AHBM_FIFO_RST_Msk = 0x4 + // Bit SLC_AHBM_FIFO_RST. + SLC_SLC_CONF0_SLC_AHBM_FIFO_RST = 0x4 + // Position of SLC_RXLINK_RST field. + SLC_SLC_CONF0_SLC_RXLINK_RST_Pos = 0x1 + // Bit mask of SLC_RXLINK_RST field. + SLC_SLC_CONF0_SLC_RXLINK_RST_Msk = 0x2 + // Bit SLC_RXLINK_RST. + SLC_SLC_CONF0_SLC_RXLINK_RST = 0x2 + // Position of SLC_TXLINK_RST field. + SLC_SLC_CONF0_SLC_TXLINK_RST_Pos = 0x0 + // Bit mask of SLC_TXLINK_RST field. + SLC_SLC_CONF0_SLC_TXLINK_RST_Msk = 0x1 + // Bit SLC_TXLINK_RST. + SLC_SLC_CONF0_SLC_TXLINK_RST = 0x1 + + // SLC_INT_RAW: SLC_INT_RAW + // Position of SLC_TX_DSCR_EMPTY_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_DSCR_EMPTY_INT_RAW_Pos = 0x15 + // Bit mask of SLC_TX_DSCR_EMPTY_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_DSCR_EMPTY_INT_RAW_Msk = 0x200000 + // Bit SLC_TX_DSCR_EMPTY_INT_RAW. + SLC_SLC_INT_RAW_SLC_TX_DSCR_EMPTY_INT_RAW = 0x200000 + // Position of SLC_RX_DSCR_ERR_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_DSCR_ERR_INT_RAW_Pos = 0x14 + // Bit mask of SLC_RX_DSCR_ERR_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_DSCR_ERR_INT_RAW_Msk = 0x100000 + // Bit SLC_RX_DSCR_ERR_INT_RAW. + SLC_SLC_INT_RAW_SLC_RX_DSCR_ERR_INT_RAW = 0x100000 + // Position of SLC_TX_DSCR_ERR_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_DSCR_ERR_INT_RAW_Pos = 0x13 + // Bit mask of SLC_TX_DSCR_ERR_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_DSCR_ERR_INT_RAW_Msk = 0x80000 + // Bit SLC_TX_DSCR_ERR_INT_RAW. + SLC_SLC_INT_RAW_SLC_TX_DSCR_ERR_INT_RAW = 0x80000 + // Position of SLC_TOHOST_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TOHOST_INT_RAW_Pos = 0x12 + // Bit mask of SLC_TOHOST_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TOHOST_INT_RAW_Msk = 0x40000 + // Bit SLC_TOHOST_INT_RAW. + SLC_SLC_INT_RAW_SLC_TOHOST_INT_RAW = 0x40000 + // Position of SLC_RX_EOF_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_EOF_INT_RAW_Pos = 0x11 + // Bit mask of SLC_RX_EOF_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_EOF_INT_RAW_Msk = 0x20000 + // Bit SLC_RX_EOF_INT_RAW. + SLC_SLC_INT_RAW_SLC_RX_EOF_INT_RAW = 0x20000 + // Position of SLC_RX_DONE_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_DONE_INT_RAW_Pos = 0x10 + // Bit mask of SLC_RX_DONE_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_DONE_INT_RAW_Msk = 0x10000 + // Bit SLC_RX_DONE_INT_RAW. + SLC_SLC_INT_RAW_SLC_RX_DONE_INT_RAW = 0x10000 + // Position of SLC_TX_EOF_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_EOF_INT_RAW_Pos = 0xf + // Bit mask of SLC_TX_EOF_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_EOF_INT_RAW_Msk = 0x8000 + // Bit SLC_TX_EOF_INT_RAW. + SLC_SLC_INT_RAW_SLC_TX_EOF_INT_RAW = 0x8000 + // Position of SLC_TX_DONE_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_DONE_INT_RAW_Pos = 0xe + // Bit mask of SLC_TX_DONE_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_DONE_INT_RAW_Msk = 0x4000 + // Bit SLC_TX_DONE_INT_RAW. + SLC_SLC_INT_RAW_SLC_TX_DONE_INT_RAW = 0x4000 + // Position of SLC_TOKEN1_1TO0_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TOKEN1_1TO0_INT_RAW_Pos = 0xd + // Bit mask of SLC_TOKEN1_1TO0_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TOKEN1_1TO0_INT_RAW_Msk = 0x2000 + // Bit SLC_TOKEN1_1TO0_INT_RAW. + SLC_SLC_INT_RAW_SLC_TOKEN1_1TO0_INT_RAW = 0x2000 + // Position of SLC_TOKEN0_1TO0_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TOKEN0_1TO0_INT_RAW_Pos = 0xc + // Bit mask of SLC_TOKEN0_1TO0_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TOKEN0_1TO0_INT_RAW_Msk = 0x1000 + // Bit SLC_TOKEN0_1TO0_INT_RAW. + SLC_SLC_INT_RAW_SLC_TOKEN0_1TO0_INT_RAW = 0x1000 + // Position of SLC_TX_OVF_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_OVF_INT_RAW_Pos = 0xb + // Bit mask of SLC_TX_OVF_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_OVF_INT_RAW_Msk = 0x800 + // Bit SLC_TX_OVF_INT_RAW. + SLC_SLC_INT_RAW_SLC_TX_OVF_INT_RAW = 0x800 + // Position of SLC_RX_UDF_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_UDF_INT_RAW_Pos = 0xa + // Bit mask of SLC_RX_UDF_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_UDF_INT_RAW_Msk = 0x400 + // Bit SLC_RX_UDF_INT_RAW. + SLC_SLC_INT_RAW_SLC_RX_UDF_INT_RAW = 0x400 + // Position of SLC_TX_START_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_START_INT_RAW_Pos = 0x9 + // Bit mask of SLC_TX_START_INT_RAW field. + SLC_SLC_INT_RAW_SLC_TX_START_INT_RAW_Msk = 0x200 + // Bit SLC_TX_START_INT_RAW. + SLC_SLC_INT_RAW_SLC_TX_START_INT_RAW = 0x200 + // Position of SLC_RX_START_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_START_INT_RAW_Pos = 0x8 + // Bit mask of SLC_RX_START_INT_RAW field. + SLC_SLC_INT_RAW_SLC_RX_START_INT_RAW_Msk = 0x100 + // Bit SLC_RX_START_INT_RAW. + SLC_SLC_INT_RAW_SLC_RX_START_INT_RAW = 0x100 + // Position of SLC_FRHOST_BIT7_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT7_INT_RAW_Pos = 0x7 + // Bit mask of SLC_FRHOST_BIT7_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT7_INT_RAW_Msk = 0x80 + // Bit SLC_FRHOST_BIT7_INT_RAW. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT7_INT_RAW = 0x80 + // Position of SLC_FRHOST_BIT6_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT6_INT_RAW_Pos = 0x6 + // Bit mask of SLC_FRHOST_BIT6_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT6_INT_RAW_Msk = 0x40 + // Bit SLC_FRHOST_BIT6_INT_RAW. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT6_INT_RAW = 0x40 + // Position of SLC_FRHOST_BIT5_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT5_INT_RAW_Pos = 0x5 + // Bit mask of SLC_FRHOST_BIT5_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT5_INT_RAW_Msk = 0x20 + // Bit SLC_FRHOST_BIT5_INT_RAW. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT5_INT_RAW = 0x20 + // Position of SLC_FRHOST_BIT4_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT4_INT_RAW_Pos = 0x4 + // Bit mask of SLC_FRHOST_BIT4_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT4_INT_RAW_Msk = 0x10 + // Bit SLC_FRHOST_BIT4_INT_RAW. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT4_INT_RAW = 0x10 + // Position of SLC_FRHOST_BIT3_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT3_INT_RAW_Pos = 0x3 + // Bit mask of SLC_FRHOST_BIT3_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT3_INT_RAW_Msk = 0x8 + // Bit SLC_FRHOST_BIT3_INT_RAW. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT3_INT_RAW = 0x8 + // Position of SLC_FRHOST_BIT2_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT2_INT_RAW_Pos = 0x2 + // Bit mask of SLC_FRHOST_BIT2_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT2_INT_RAW_Msk = 0x4 + // Bit SLC_FRHOST_BIT2_INT_RAW. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT2_INT_RAW = 0x4 + // Position of SLC_FRHOST_BIT1_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT1_INT_RAW_Pos = 0x1 + // Bit mask of SLC_FRHOST_BIT1_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT1_INT_RAW_Msk = 0x2 + // Bit SLC_FRHOST_BIT1_INT_RAW. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT1_INT_RAW = 0x2 + // Position of SLC_FRHOST_BIT0_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT0_INT_RAW_Pos = 0x0 + // Bit mask of SLC_FRHOST_BIT0_INT_RAW field. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT0_INT_RAW_Msk = 0x1 + // Bit SLC_FRHOST_BIT0_INT_RAW. + SLC_SLC_INT_RAW_SLC_FRHOST_BIT0_INT_RAW = 0x1 + + // SLC_INT_STATUS: SLC_INT_STATUS + // Position of SLC_TX_DSCR_EMPTY_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_DSCR_EMPTY_INT_ST_Pos = 0x15 + // Bit mask of SLC_TX_DSCR_EMPTY_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_DSCR_EMPTY_INT_ST_Msk = 0x200000 + // Bit SLC_TX_DSCR_EMPTY_INT_ST. + SLC_SLC_INT_STATUS_SLC_TX_DSCR_EMPTY_INT_ST = 0x200000 + // Position of SLC_RX_DSCR_ERR_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_DSCR_ERR_INT_ST_Pos = 0x14 + // Bit mask of SLC_RX_DSCR_ERR_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_DSCR_ERR_INT_ST_Msk = 0x100000 + // Bit SLC_RX_DSCR_ERR_INT_ST. + SLC_SLC_INT_STATUS_SLC_RX_DSCR_ERR_INT_ST = 0x100000 + // Position of SLC_TX_DSCR_ERR_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_DSCR_ERR_INT_ST_Pos = 0x13 + // Bit mask of SLC_TX_DSCR_ERR_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_DSCR_ERR_INT_ST_Msk = 0x80000 + // Bit SLC_TX_DSCR_ERR_INT_ST. + SLC_SLC_INT_STATUS_SLC_TX_DSCR_ERR_INT_ST = 0x80000 + // Position of SLC_TOHOST_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TOHOST_INT_ST_Pos = 0x12 + // Bit mask of SLC_TOHOST_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TOHOST_INT_ST_Msk = 0x40000 + // Bit SLC_TOHOST_INT_ST. + SLC_SLC_INT_STATUS_SLC_TOHOST_INT_ST = 0x40000 + // Position of SLC_RX_EOF_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_EOF_INT_ST_Pos = 0x11 + // Bit mask of SLC_RX_EOF_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_EOF_INT_ST_Msk = 0x20000 + // Bit SLC_RX_EOF_INT_ST. + SLC_SLC_INT_STATUS_SLC_RX_EOF_INT_ST = 0x20000 + // Position of SLC_RX_DONE_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_DONE_INT_ST_Pos = 0x10 + // Bit mask of SLC_RX_DONE_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_DONE_INT_ST_Msk = 0x10000 + // Bit SLC_RX_DONE_INT_ST. + SLC_SLC_INT_STATUS_SLC_RX_DONE_INT_ST = 0x10000 + // Position of SLC_TX_EOF_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_EOF_INT_ST_Pos = 0xf + // Bit mask of SLC_TX_EOF_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_EOF_INT_ST_Msk = 0x8000 + // Bit SLC_TX_EOF_INT_ST. + SLC_SLC_INT_STATUS_SLC_TX_EOF_INT_ST = 0x8000 + // Position of SLC_TX_DONE_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_DONE_INT_ST_Pos = 0xe + // Bit mask of SLC_TX_DONE_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_DONE_INT_ST_Msk = 0x4000 + // Bit SLC_TX_DONE_INT_ST. + SLC_SLC_INT_STATUS_SLC_TX_DONE_INT_ST = 0x4000 + // Position of SLC_TOKEN1_1TO0_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TOKEN1_1TO0_INT_ST_Pos = 0xd + // Bit mask of SLC_TOKEN1_1TO0_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TOKEN1_1TO0_INT_ST_Msk = 0x2000 + // Bit SLC_TOKEN1_1TO0_INT_ST. + SLC_SLC_INT_STATUS_SLC_TOKEN1_1TO0_INT_ST = 0x2000 + // Position of SLC_TOKEN0_1TO0_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TOKEN0_1TO0_INT_ST_Pos = 0xc + // Bit mask of SLC_TOKEN0_1TO0_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TOKEN0_1TO0_INT_ST_Msk = 0x1000 + // Bit SLC_TOKEN0_1TO0_INT_ST. + SLC_SLC_INT_STATUS_SLC_TOKEN0_1TO0_INT_ST = 0x1000 + // Position of SLC_TX_OVF_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_OVF_INT_ST_Pos = 0xb + // Bit mask of SLC_TX_OVF_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_OVF_INT_ST_Msk = 0x800 + // Bit SLC_TX_OVF_INT_ST. + SLC_SLC_INT_STATUS_SLC_TX_OVF_INT_ST = 0x800 + // Position of SLC_RX_UDF_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_UDF_INT_ST_Pos = 0xa + // Bit mask of SLC_RX_UDF_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_UDF_INT_ST_Msk = 0x400 + // Bit SLC_RX_UDF_INT_ST. + SLC_SLC_INT_STATUS_SLC_RX_UDF_INT_ST = 0x400 + // Position of SLC_TX_START_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_START_INT_ST_Pos = 0x9 + // Bit mask of SLC_TX_START_INT_ST field. + SLC_SLC_INT_STATUS_SLC_TX_START_INT_ST_Msk = 0x200 + // Bit SLC_TX_START_INT_ST. + SLC_SLC_INT_STATUS_SLC_TX_START_INT_ST = 0x200 + // Position of SLC_RX_START_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_START_INT_ST_Pos = 0x8 + // Bit mask of SLC_RX_START_INT_ST field. + SLC_SLC_INT_STATUS_SLC_RX_START_INT_ST_Msk = 0x100 + // Bit SLC_RX_START_INT_ST. + SLC_SLC_INT_STATUS_SLC_RX_START_INT_ST = 0x100 + // Position of SLC_FRHOST_BIT7_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT7_INT_ST_Pos = 0x7 + // Bit mask of SLC_FRHOST_BIT7_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT7_INT_ST_Msk = 0x80 + // Bit SLC_FRHOST_BIT7_INT_ST. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT7_INT_ST = 0x80 + // Position of SLC_FRHOST_BIT6_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT6_INT_ST_Pos = 0x6 + // Bit mask of SLC_FRHOST_BIT6_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT6_INT_ST_Msk = 0x40 + // Bit SLC_FRHOST_BIT6_INT_ST. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT6_INT_ST = 0x40 + // Position of SLC_FRHOST_BIT5_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT5_INT_ST_Pos = 0x5 + // Bit mask of SLC_FRHOST_BIT5_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT5_INT_ST_Msk = 0x20 + // Bit SLC_FRHOST_BIT5_INT_ST. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT5_INT_ST = 0x20 + // Position of SLC_FRHOST_BIT4_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT4_INT_ST_Pos = 0x4 + // Bit mask of SLC_FRHOST_BIT4_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT4_INT_ST_Msk = 0x10 + // Bit SLC_FRHOST_BIT4_INT_ST. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT4_INT_ST = 0x10 + // Position of SLC_FRHOST_BIT3_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT3_INT_ST_Pos = 0x3 + // Bit mask of SLC_FRHOST_BIT3_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT3_INT_ST_Msk = 0x8 + // Bit SLC_FRHOST_BIT3_INT_ST. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT3_INT_ST = 0x8 + // Position of SLC_FRHOST_BIT2_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT2_INT_ST_Pos = 0x2 + // Bit mask of SLC_FRHOST_BIT2_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT2_INT_ST_Msk = 0x4 + // Bit SLC_FRHOST_BIT2_INT_ST. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT2_INT_ST = 0x4 + // Position of SLC_FRHOST_BIT1_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT1_INT_ST_Pos = 0x1 + // Bit mask of SLC_FRHOST_BIT1_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT1_INT_ST_Msk = 0x2 + // Bit SLC_FRHOST_BIT1_INT_ST. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT1_INT_ST = 0x2 + // Position of SLC_FRHOST_BIT0_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT0_INT_ST_Pos = 0x0 + // Bit mask of SLC_FRHOST_BIT0_INT_ST field. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT0_INT_ST_Msk = 0x1 + // Bit SLC_FRHOST_BIT0_INT_ST. + SLC_SLC_INT_STATUS_SLC_FRHOST_BIT0_INT_ST = 0x1 + + // SLC_INT_ENA: SLC_INT_ENA + // Position of SLC_TX_DSCR_EMPTY_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_DSCR_EMPTY_INT_ENA_Pos = 0x15 + // Bit mask of SLC_TX_DSCR_EMPTY_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_DSCR_EMPTY_INT_ENA_Msk = 0x200000 + // Bit SLC_TX_DSCR_EMPTY_INT_ENA. + SLC_SLC_INT_ENA_SLC_TX_DSCR_EMPTY_INT_ENA = 0x200000 + // Position of SLC_RX_DSCR_ERR_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_DSCR_ERR_INT_ENA_Pos = 0x14 + // Bit mask of SLC_RX_DSCR_ERR_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_DSCR_ERR_INT_ENA_Msk = 0x100000 + // Bit SLC_RX_DSCR_ERR_INT_ENA. + SLC_SLC_INT_ENA_SLC_RX_DSCR_ERR_INT_ENA = 0x100000 + // Position of SLC_TX_DSCR_ERR_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_DSCR_ERR_INT_ENA_Pos = 0x13 + // Bit mask of SLC_TX_DSCR_ERR_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_DSCR_ERR_INT_ENA_Msk = 0x80000 + // Bit SLC_TX_DSCR_ERR_INT_ENA. + SLC_SLC_INT_ENA_SLC_TX_DSCR_ERR_INT_ENA = 0x80000 + // Position of SLC_TOHOST_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TOHOST_INT_ENA_Pos = 0x12 + // Bit mask of SLC_TOHOST_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TOHOST_INT_ENA_Msk = 0x40000 + // Bit SLC_TOHOST_INT_ENA. + SLC_SLC_INT_ENA_SLC_TOHOST_INT_ENA = 0x40000 + // Position of SLC_RX_EOF_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_EOF_INT_ENA_Pos = 0x11 + // Bit mask of SLC_RX_EOF_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_EOF_INT_ENA_Msk = 0x20000 + // Bit SLC_RX_EOF_INT_ENA. + SLC_SLC_INT_ENA_SLC_RX_EOF_INT_ENA = 0x20000 + // Position of SLC_RX_DONE_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_DONE_INT_ENA_Pos = 0x10 + // Bit mask of SLC_RX_DONE_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_DONE_INT_ENA_Msk = 0x10000 + // Bit SLC_RX_DONE_INT_ENA. + SLC_SLC_INT_ENA_SLC_RX_DONE_INT_ENA = 0x10000 + // Position of SLC_TX_EOF_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_EOF_INT_ENA_Pos = 0xf + // Bit mask of SLC_TX_EOF_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_EOF_INT_ENA_Msk = 0x8000 + // Bit SLC_TX_EOF_INT_ENA. + SLC_SLC_INT_ENA_SLC_TX_EOF_INT_ENA = 0x8000 + // Position of SLC_TX_DONE_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_DONE_INT_ENA_Pos = 0xe + // Bit mask of SLC_TX_DONE_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_DONE_INT_ENA_Msk = 0x4000 + // Bit SLC_TX_DONE_INT_ENA. + SLC_SLC_INT_ENA_SLC_TX_DONE_INT_ENA = 0x4000 + // Position of SLC_TOKEN1_1TO0_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TOKEN1_1TO0_INT_ENA_Pos = 0xd + // Bit mask of SLC_TOKEN1_1TO0_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TOKEN1_1TO0_INT_ENA_Msk = 0x2000 + // Bit SLC_TOKEN1_1TO0_INT_ENA. + SLC_SLC_INT_ENA_SLC_TOKEN1_1TO0_INT_ENA = 0x2000 + // Position of SLC_TOKEN0_1TO0_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TOKEN0_1TO0_INT_ENA_Pos = 0xc + // Bit mask of SLC_TOKEN0_1TO0_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TOKEN0_1TO0_INT_ENA_Msk = 0x1000 + // Bit SLC_TOKEN0_1TO0_INT_ENA. + SLC_SLC_INT_ENA_SLC_TOKEN0_1TO0_INT_ENA = 0x1000 + // Position of SLC_TX_OVF_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_OVF_INT_ENA_Pos = 0xb + // Bit mask of SLC_TX_OVF_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_OVF_INT_ENA_Msk = 0x800 + // Bit SLC_TX_OVF_INT_ENA. + SLC_SLC_INT_ENA_SLC_TX_OVF_INT_ENA = 0x800 + // Position of SLC_RX_UDF_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_UDF_INT_ENA_Pos = 0xa + // Bit mask of SLC_RX_UDF_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_UDF_INT_ENA_Msk = 0x400 + // Bit SLC_RX_UDF_INT_ENA. + SLC_SLC_INT_ENA_SLC_RX_UDF_INT_ENA = 0x400 + // Position of SLC_TX_START_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_START_INT_ENA_Pos = 0x9 + // Bit mask of SLC_TX_START_INT_ENA field. + SLC_SLC_INT_ENA_SLC_TX_START_INT_ENA_Msk = 0x200 + // Bit SLC_TX_START_INT_ENA. + SLC_SLC_INT_ENA_SLC_TX_START_INT_ENA = 0x200 + // Position of SLC_RX_START_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_START_INT_ENA_Pos = 0x8 + // Bit mask of SLC_RX_START_INT_ENA field. + SLC_SLC_INT_ENA_SLC_RX_START_INT_ENA_Msk = 0x100 + // Bit SLC_RX_START_INT_ENA. + SLC_SLC_INT_ENA_SLC_RX_START_INT_ENA = 0x100 + // Position of SLC_FRHOST_BIT7_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT7_INT_ENA_Pos = 0x7 + // Bit mask of SLC_FRHOST_BIT7_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT7_INT_ENA_Msk = 0x80 + // Bit SLC_FRHOST_BIT7_INT_ENA. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT7_INT_ENA = 0x80 + // Position of SLC_FRHOST_BIT6_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT6_INT_ENA_Pos = 0x6 + // Bit mask of SLC_FRHOST_BIT6_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT6_INT_ENA_Msk = 0x40 + // Bit SLC_FRHOST_BIT6_INT_ENA. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT6_INT_ENA = 0x40 + // Position of SLC_FRHOST_BIT5_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT5_INT_ENA_Pos = 0x5 + // Bit mask of SLC_FRHOST_BIT5_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT5_INT_ENA_Msk = 0x20 + // Bit SLC_FRHOST_BIT5_INT_ENA. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT5_INT_ENA = 0x20 + // Position of SLC_FRHOST_BIT4_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT4_INT_ENA_Pos = 0x4 + // Bit mask of SLC_FRHOST_BIT4_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT4_INT_ENA_Msk = 0x10 + // Bit SLC_FRHOST_BIT4_INT_ENA. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT4_INT_ENA = 0x10 + // Position of SLC_FRHOST_BIT3_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT3_INT_ENA_Pos = 0x3 + // Bit mask of SLC_FRHOST_BIT3_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT3_INT_ENA_Msk = 0x8 + // Bit SLC_FRHOST_BIT3_INT_ENA. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT3_INT_ENA = 0x8 + // Position of SLC_FRHOST_BIT2_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT2_INT_ENA_Pos = 0x2 + // Bit mask of SLC_FRHOST_BIT2_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT2_INT_ENA_Msk = 0x4 + // Bit SLC_FRHOST_BIT2_INT_ENA. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT2_INT_ENA = 0x4 + // Position of SLC_FRHOST_BIT1_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT1_INT_ENA_Pos = 0x1 + // Bit mask of SLC_FRHOST_BIT1_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT1_INT_ENA_Msk = 0x2 + // Bit SLC_FRHOST_BIT1_INT_ENA. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT1_INT_ENA = 0x2 + // Position of SLC_FRHOST_BIT0_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT0_INT_ENA_Pos = 0x0 + // Bit mask of SLC_FRHOST_BIT0_INT_ENA field. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT0_INT_ENA_Msk = 0x1 + // Bit SLC_FRHOST_BIT0_INT_ENA. + SLC_SLC_INT_ENA_SLC_FRHOST_BIT0_INT_ENA = 0x1 + + // SLC_INT_CLR: SLC_INT_CLR + // Position of SLC_TX_DSCR_EMPTY_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_DSCR_EMPTY_INT_CLR_Pos = 0x15 + // Bit mask of SLC_TX_DSCR_EMPTY_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_DSCR_EMPTY_INT_CLR_Msk = 0x200000 + // Bit SLC_TX_DSCR_EMPTY_INT_CLR. + SLC_SLC_INT_CLR_SLC_TX_DSCR_EMPTY_INT_CLR = 0x200000 + // Position of SLC_RX_DSCR_ERR_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_DSCR_ERR_INT_CLR_Pos = 0x14 + // Bit mask of SLC_RX_DSCR_ERR_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_DSCR_ERR_INT_CLR_Msk = 0x100000 + // Bit SLC_RX_DSCR_ERR_INT_CLR. + SLC_SLC_INT_CLR_SLC_RX_DSCR_ERR_INT_CLR = 0x100000 + // Position of SLC_TX_DSCR_ERR_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_DSCR_ERR_INT_CLR_Pos = 0x13 + // Bit mask of SLC_TX_DSCR_ERR_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_DSCR_ERR_INT_CLR_Msk = 0x80000 + // Bit SLC_TX_DSCR_ERR_INT_CLR. + SLC_SLC_INT_CLR_SLC_TX_DSCR_ERR_INT_CLR = 0x80000 + // Position of SLC_TOHOST_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TOHOST_INT_CLR_Pos = 0x12 + // Bit mask of SLC_TOHOST_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TOHOST_INT_CLR_Msk = 0x40000 + // Bit SLC_TOHOST_INT_CLR. + SLC_SLC_INT_CLR_SLC_TOHOST_INT_CLR = 0x40000 + // Position of SLC_RX_EOF_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_EOF_INT_CLR_Pos = 0x11 + // Bit mask of SLC_RX_EOF_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_EOF_INT_CLR_Msk = 0x20000 + // Bit SLC_RX_EOF_INT_CLR. + SLC_SLC_INT_CLR_SLC_RX_EOF_INT_CLR = 0x20000 + // Position of SLC_RX_DONE_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_DONE_INT_CLR_Pos = 0x10 + // Bit mask of SLC_RX_DONE_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_DONE_INT_CLR_Msk = 0x10000 + // Bit SLC_RX_DONE_INT_CLR. + SLC_SLC_INT_CLR_SLC_RX_DONE_INT_CLR = 0x10000 + // Position of SLC_TX_EOF_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_EOF_INT_CLR_Pos = 0xf + // Bit mask of SLC_TX_EOF_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_EOF_INT_CLR_Msk = 0x8000 + // Bit SLC_TX_EOF_INT_CLR. + SLC_SLC_INT_CLR_SLC_TX_EOF_INT_CLR = 0x8000 + // Position of SLC_TX_DONE_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_DONE_INT_CLR_Pos = 0xe + // Bit mask of SLC_TX_DONE_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_DONE_INT_CLR_Msk = 0x4000 + // Bit SLC_TX_DONE_INT_CLR. + SLC_SLC_INT_CLR_SLC_TX_DONE_INT_CLR = 0x4000 + // Position of SLC_TOKEN1_1TO0_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TOKEN1_1TO0_INT_CLR_Pos = 0xd + // Bit mask of SLC_TOKEN1_1TO0_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TOKEN1_1TO0_INT_CLR_Msk = 0x2000 + // Bit SLC_TOKEN1_1TO0_INT_CLR. + SLC_SLC_INT_CLR_SLC_TOKEN1_1TO0_INT_CLR = 0x2000 + // Position of SLC_TOKEN0_1TO0_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TOKEN0_1TO0_INT_CLR_Pos = 0xc + // Bit mask of SLC_TOKEN0_1TO0_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TOKEN0_1TO0_INT_CLR_Msk = 0x1000 + // Bit SLC_TOKEN0_1TO0_INT_CLR. + SLC_SLC_INT_CLR_SLC_TOKEN0_1TO0_INT_CLR = 0x1000 + // Position of SLC_TX_OVF_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_OVF_INT_CLR_Pos = 0xb + // Bit mask of SLC_TX_OVF_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_OVF_INT_CLR_Msk = 0x800 + // Bit SLC_TX_OVF_INT_CLR. + SLC_SLC_INT_CLR_SLC_TX_OVF_INT_CLR = 0x800 + // Position of SLC_RX_UDF_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_UDF_INT_CLR_Pos = 0xa + // Bit mask of SLC_RX_UDF_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_UDF_INT_CLR_Msk = 0x400 + // Bit SLC_RX_UDF_INT_CLR. + SLC_SLC_INT_CLR_SLC_RX_UDF_INT_CLR = 0x400 + // Position of SLC_TX_START_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_START_INT_CLR_Pos = 0x9 + // Bit mask of SLC_TX_START_INT_CLR field. + SLC_SLC_INT_CLR_SLC_TX_START_INT_CLR_Msk = 0x200 + // Bit SLC_TX_START_INT_CLR. + SLC_SLC_INT_CLR_SLC_TX_START_INT_CLR = 0x200 + // Position of SLC_RX_START_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_START_INT_CLR_Pos = 0x8 + // Bit mask of SLC_RX_START_INT_CLR field. + SLC_SLC_INT_CLR_SLC_RX_START_INT_CLR_Msk = 0x100 + // Bit SLC_RX_START_INT_CLR. + SLC_SLC_INT_CLR_SLC_RX_START_INT_CLR = 0x100 + // Position of SLC_FRHOST_BIT7_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT7_INT_CLR_Pos = 0x7 + // Bit mask of SLC_FRHOST_BIT7_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT7_INT_CLR_Msk = 0x80 + // Bit SLC_FRHOST_BIT7_INT_CLR. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT7_INT_CLR = 0x80 + // Position of SLC_FRHOST_BIT6_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT6_INT_CLR_Pos = 0x6 + // Bit mask of SLC_FRHOST_BIT6_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT6_INT_CLR_Msk = 0x40 + // Bit SLC_FRHOST_BIT6_INT_CLR. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT6_INT_CLR = 0x40 + // Position of SLC_FRHOST_BIT5_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT5_INT_CLR_Pos = 0x5 + // Bit mask of SLC_FRHOST_BIT5_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT5_INT_CLR_Msk = 0x20 + // Bit SLC_FRHOST_BIT5_INT_CLR. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT5_INT_CLR = 0x20 + // Position of SLC_FRHOST_BIT4_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT4_INT_CLR_Pos = 0x4 + // Bit mask of SLC_FRHOST_BIT4_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT4_INT_CLR_Msk = 0x10 + // Bit SLC_FRHOST_BIT4_INT_CLR. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT4_INT_CLR = 0x10 + // Position of SLC_FRHOST_BIT3_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT3_INT_CLR_Pos = 0x3 + // Bit mask of SLC_FRHOST_BIT3_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT3_INT_CLR_Msk = 0x8 + // Bit SLC_FRHOST_BIT3_INT_CLR. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT3_INT_CLR = 0x8 + // Position of SLC_FRHOST_BIT2_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT2_INT_CLR_Pos = 0x2 + // Bit mask of SLC_FRHOST_BIT2_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT2_INT_CLR_Msk = 0x4 + // Bit SLC_FRHOST_BIT2_INT_CLR. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT2_INT_CLR = 0x4 + // Position of SLC_FRHOST_BIT1_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT1_INT_CLR_Pos = 0x1 + // Bit mask of SLC_FRHOST_BIT1_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT1_INT_CLR_Msk = 0x2 + // Bit SLC_FRHOST_BIT1_INT_CLR. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT1_INT_CLR = 0x2 + // Position of SLC_FRHOST_BIT0_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT0_INT_CLR_Pos = 0x0 + // Bit mask of SLC_FRHOST_BIT0_INT_CLR field. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT0_INT_CLR_Msk = 0x1 + // Bit SLC_FRHOST_BIT0_INT_CLR. + SLC_SLC_INT_CLR_SLC_FRHOST_BIT0_INT_CLR = 0x1 + + // SLC_RX_STATUS: SLC_RX_STATUS + // Position of SLC_RX_EMPTY field. + SLC_SLC_RX_STATUS_SLC_RX_EMPTY_Pos = 0x1 + // Bit mask of SLC_RX_EMPTY field. + SLC_SLC_RX_STATUS_SLC_RX_EMPTY_Msk = 0x2 + // Bit SLC_RX_EMPTY. + SLC_SLC_RX_STATUS_SLC_RX_EMPTY = 0x2 + // Position of SLC_RX_FULL field. + SLC_SLC_RX_STATUS_SLC_RX_FULL_Pos = 0x0 + // Bit mask of SLC_RX_FULL field. + SLC_SLC_RX_STATUS_SLC_RX_FULL_Msk = 0x1 + // Bit SLC_RX_FULL. + SLC_SLC_RX_STATUS_SLC_RX_FULL = 0x1 + + // SLC_RX_FIFO_PUSH: SLC_RX_FIFO_PUSH + // Position of SLC_RXFIFO_PUSH field. + SLC_SLC_RX_FIFO_PUSH_SLC_RXFIFO_PUSH_Pos = 0x10 + // Bit mask of SLC_RXFIFO_PUSH field. + SLC_SLC_RX_FIFO_PUSH_SLC_RXFIFO_PUSH_Msk = 0x10000 + // Bit SLC_RXFIFO_PUSH. + SLC_SLC_RX_FIFO_PUSH_SLC_RXFIFO_PUSH = 0x10000 + // Position of SLC_RXFIFO_WDATA field. + SLC_SLC_RX_FIFO_PUSH_SLC_RXFIFO_WDATA_Pos = 0x0 + // Bit mask of SLC_RXFIFO_WDATA field. + SLC_SLC_RX_FIFO_PUSH_SLC_RXFIFO_WDATA_Msk = 0x1ff + + // SLC_TX_STATUS: SLC_TX_STATUS + // Position of SLC_TX_EMPTY field. + SLC_SLC_TX_STATUS_SLC_TX_EMPTY_Pos = 0x1 + // Bit mask of SLC_TX_EMPTY field. + SLC_SLC_TX_STATUS_SLC_TX_EMPTY_Msk = 0x2 + // Bit SLC_TX_EMPTY. + SLC_SLC_TX_STATUS_SLC_TX_EMPTY = 0x2 + // Position of SLC_TX_FULL field. + SLC_SLC_TX_STATUS_SLC_TX_FULL_Pos = 0x0 + // Bit mask of SLC_TX_FULL field. + SLC_SLC_TX_STATUS_SLC_TX_FULL_Msk = 0x1 + // Bit SLC_TX_FULL. + SLC_SLC_TX_STATUS_SLC_TX_FULL = 0x1 + + // SLC_TX_FIFO_POP: SLC_TX_FIFO_POP + // Position of SLC_TXFIFO_POP field. + SLC_SLC_TX_FIFO_POP_SLC_TXFIFO_POP_Pos = 0x10 + // Bit mask of SLC_TXFIFO_POP field. + SLC_SLC_TX_FIFO_POP_SLC_TXFIFO_POP_Msk = 0x10000 + // Bit SLC_TXFIFO_POP. + SLC_SLC_TX_FIFO_POP_SLC_TXFIFO_POP = 0x10000 + // Position of SLC_TXFIFO_RDATA field. + SLC_SLC_TX_FIFO_POP_SLC_TXFIFO_RDATA_Pos = 0x0 + // Bit mask of SLC_TXFIFO_RDATA field. + SLC_SLC_TX_FIFO_POP_SLC_TXFIFO_RDATA_Msk = 0x7ff + + // SLC_RX_LINK: SLC_RX_LINK + // Position of SLC_RXLINK_PARK field. + SLC_SLC_RX_LINK_SLC_RXLINK_PARK_Pos = 0x1f + // Bit mask of SLC_RXLINK_PARK field. + SLC_SLC_RX_LINK_SLC_RXLINK_PARK_Msk = 0x80000000 + // Bit SLC_RXLINK_PARK. + SLC_SLC_RX_LINK_SLC_RXLINK_PARK = 0x80000000 + // Position of SLC_RXLINK_RESTART field. + SLC_SLC_RX_LINK_SLC_RXLINK_RESTART_Pos = 0x1e + // Bit mask of SLC_RXLINK_RESTART field. + SLC_SLC_RX_LINK_SLC_RXLINK_RESTART_Msk = 0x40000000 + // Bit SLC_RXLINK_RESTART. + SLC_SLC_RX_LINK_SLC_RXLINK_RESTART = 0x40000000 + // Position of SLC_RXLINK_START field. + SLC_SLC_RX_LINK_SLC_RXLINK_START_Pos = 0x1d + // Bit mask of SLC_RXLINK_START field. + SLC_SLC_RX_LINK_SLC_RXLINK_START_Msk = 0x20000000 + // Bit SLC_RXLINK_START. + SLC_SLC_RX_LINK_SLC_RXLINK_START = 0x20000000 + // Position of SLC_RXLINK_STOP field. + SLC_SLC_RX_LINK_SLC_RXLINK_STOP_Pos = 0x1c + // Bit mask of SLC_RXLINK_STOP field. + SLC_SLC_RX_LINK_SLC_RXLINK_STOP_Msk = 0x10000000 + // Bit SLC_RXLINK_STOP. + SLC_SLC_RX_LINK_SLC_RXLINK_STOP = 0x10000000 + // Position of SLC_RXLINK_ADDR field. + SLC_SLC_RX_LINK_SLC_RXLINK_ADDR_Pos = 0x0 + // Bit mask of SLC_RXLINK_ADDR field. + SLC_SLC_RX_LINK_SLC_RXLINK_ADDR_Msk = 0xfffff + + // SLC_TX_LINK: SLC_TX_LINK + // Position of SLC_TXLINK_PARK field. + SLC_SLC_TX_LINK_SLC_TXLINK_PARK_Pos = 0x1f + // Bit mask of SLC_TXLINK_PARK field. + SLC_SLC_TX_LINK_SLC_TXLINK_PARK_Msk = 0x80000000 + // Bit SLC_TXLINK_PARK. + SLC_SLC_TX_LINK_SLC_TXLINK_PARK = 0x80000000 + // Position of SLC_TXLINK_RESTART field. + SLC_SLC_TX_LINK_SLC_TXLINK_RESTART_Pos = 0x1e + // Bit mask of SLC_TXLINK_RESTART field. + SLC_SLC_TX_LINK_SLC_TXLINK_RESTART_Msk = 0x40000000 + // Bit SLC_TXLINK_RESTART. + SLC_SLC_TX_LINK_SLC_TXLINK_RESTART = 0x40000000 + // Position of SLC_TXLINK_START field. + SLC_SLC_TX_LINK_SLC_TXLINK_START_Pos = 0x1d + // Bit mask of SLC_TXLINK_START field. + SLC_SLC_TX_LINK_SLC_TXLINK_START_Msk = 0x20000000 + // Bit SLC_TXLINK_START. + SLC_SLC_TX_LINK_SLC_TXLINK_START = 0x20000000 + // Position of SLC_TXLINK_STOP field. + SLC_SLC_TX_LINK_SLC_TXLINK_STOP_Pos = 0x1c + // Bit mask of SLC_TXLINK_STOP field. + SLC_SLC_TX_LINK_SLC_TXLINK_STOP_Msk = 0x10000000 + // Bit SLC_TXLINK_STOP. + SLC_SLC_TX_LINK_SLC_TXLINK_STOP = 0x10000000 + // Position of SLC_TXLINK_ADDR field. + SLC_SLC_TX_LINK_SLC_TXLINK_ADDR_Pos = 0x0 + // Bit mask of SLC_TXLINK_ADDR field. + SLC_SLC_TX_LINK_SLC_TXLINK_ADDR_Msk = 0xfffff + + // SLC_INTVEC_TOHOST: SLC_INTVEC_TOHOST + // Position of SLC_TOHOST_INTVEC field. + SLC_SLC_INTVEC_TOHOST_SLC_TOHOST_INTVEC_Pos = 0x0 + // Bit mask of SLC_TOHOST_INTVEC field. + SLC_SLC_INTVEC_TOHOST_SLC_TOHOST_INTVEC_Msk = 0xff + + // SLC_TOKEN0: SLC_TOKEN0 + // Position of SLC_TOKEN0 field. + SLC_SLC_TOKEN0_SLC_TOKEN0_Pos = 0x10 + // Bit mask of SLC_TOKEN0 field. + SLC_SLC_TOKEN0_SLC_TOKEN0_Msk = 0xfff0000 + // Position of SLC_TOKEN0_LOCAL_INC_MORE field. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_INC_MORE_Pos = 0xe + // Bit mask of SLC_TOKEN0_LOCAL_INC_MORE field. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_INC_MORE_Msk = 0x4000 + // Bit SLC_TOKEN0_LOCAL_INC_MORE. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_INC_MORE = 0x4000 + // Position of SLC_TOKEN0_LOCAL_INC field. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_INC_Pos = 0xd + // Bit mask of SLC_TOKEN0_LOCAL_INC field. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_INC_Msk = 0x2000 + // Bit SLC_TOKEN0_LOCAL_INC. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_INC = 0x2000 + // Position of SLC_TOKEN0_LOCAL_WR field. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_WR_Pos = 0xc + // Bit mask of SLC_TOKEN0_LOCAL_WR field. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_WR_Msk = 0x1000 + // Bit SLC_TOKEN0_LOCAL_WR. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_WR = 0x1000 + // Position of SLC_TOKEN0_LOCAL_WDATA field. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_WDATA_Pos = 0x0 + // Bit mask of SLC_TOKEN0_LOCAL_WDATA field. + SLC_SLC_TOKEN0_SLC_TOKEN0_LOCAL_WDATA_Msk = 0xfff + + // SLC_TOKEN1: SLC_TOKEN1 + // Position of SLC_TOKEN1 field. + SLC_SLC_TOKEN1_SLC_TOKEN1_Pos = 0x10 + // Bit mask of SLC_TOKEN1 field. + SLC_SLC_TOKEN1_SLC_TOKEN1_Msk = 0xfff0000 + // Position of SLC_TOKEN1_LOCAL_INC_MORE field. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_INC_MORE_Pos = 0xe + // Bit mask of SLC_TOKEN1_LOCAL_INC_MORE field. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_INC_MORE_Msk = 0x4000 + // Bit SLC_TOKEN1_LOCAL_INC_MORE. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_INC_MORE = 0x4000 + // Position of SLC_TOKEN1_LOCAL_INC field. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_INC_Pos = 0xd + // Bit mask of SLC_TOKEN1_LOCAL_INC field. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_INC_Msk = 0x2000 + // Bit SLC_TOKEN1_LOCAL_INC. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_INC = 0x2000 + // Position of SLC_TOKEN1_LOCAL_WR field. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_WR_Pos = 0xc + // Bit mask of SLC_TOKEN1_LOCAL_WR field. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_WR_Msk = 0x1000 + // Bit SLC_TOKEN1_LOCAL_WR. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_WR = 0x1000 + // Position of SLC_TOKEN1_LOCAL_WDATA field. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_WDATA_Pos = 0x0 + // Bit mask of SLC_TOKEN1_LOCAL_WDATA field. + SLC_SLC_TOKEN1_SLC_TOKEN1_LOCAL_WDATA_Msk = 0xfff + + // SLC_CONF1: SLC_CONF1 + // Position of Register field. + SLC_SLC_CONF1_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_CONF1_Register_Msk = 0xffffffff + + // SLC_STATE0: SLC_STATE0 + // Position of Register field. + SLC_SLC_STATE0_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_STATE0_Register_Msk = 0xffffffff + + // SLC_STATE1: SLC_STATE1 + // Position of Register field. + SLC_SLC_STATE1_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_STATE1_Register_Msk = 0xffffffff + + // SLC_BRIDGE_CONF: SLC_BRIDGE_CONF + // Position of SLC_TX_PUSH_IDLE_NUM field. + SLC_SLC_BRIDGE_CONF_SLC_TX_PUSH_IDLE_NUM_Pos = 0x10 + // Bit mask of SLC_TX_PUSH_IDLE_NUM field. + SLC_SLC_BRIDGE_CONF_SLC_TX_PUSH_IDLE_NUM_Msk = 0xffff0000 + // Position of SLC_TX_DUMMY_MODE field. + SLC_SLC_BRIDGE_CONF_SLC_TX_DUMMY_MODE_Pos = 0xc + // Bit mask of SLC_TX_DUMMY_MODE field. + SLC_SLC_BRIDGE_CONF_SLC_TX_DUMMY_MODE_Msk = 0x1000 + // Bit SLC_TX_DUMMY_MODE. + SLC_SLC_BRIDGE_CONF_SLC_TX_DUMMY_MODE = 0x1000 + // Position of SLC_FIFO_MAP_ENA field. + SLC_SLC_BRIDGE_CONF_SLC_FIFO_MAP_ENA_Pos = 0x8 + // Bit mask of SLC_FIFO_MAP_ENA field. + SLC_SLC_BRIDGE_CONF_SLC_FIFO_MAP_ENA_Msk = 0xf00 + // Position of SLC_TXEOF_ENA field. + SLC_SLC_BRIDGE_CONF_SLC_TXEOF_ENA_Pos = 0x0 + // Bit mask of SLC_TXEOF_ENA field. + SLC_SLC_BRIDGE_CONF_SLC_TXEOF_ENA_Msk = 0x3f + + // SLC_RX_EOF_DES_ADDR: SLC_RX_EOF_DES_ADDR + // Position of Register field. + SLC_SLC_RX_EOF_DES_ADDR_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_RX_EOF_DES_ADDR_Register_Msk = 0xffffffff + + // SLC_TX_EOF_DES_ADDR: SLC_TX_EOF_DES_ADDR + // Position of Register field. + SLC_SLC_TX_EOF_DES_ADDR_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_TX_EOF_DES_ADDR_Register_Msk = 0xffffffff + + // SLC_RX_EOF_BFR_DES_ADDR: SLC_RX_EOF_BFR_DES_ADDR + // Position of Register field. + SLC_SLC_RX_EOF_BFR_DES_ADDR_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_RX_EOF_BFR_DES_ADDR_Register_Msk = 0xffffffff + + // SLC_AHB_TEST: SLC_AHB_TEST + // Position of SLC_AHB_TESTADDR field. + SLC_SLC_AHB_TEST_SLC_AHB_TESTADDR_Pos = 0x4 + // Bit mask of SLC_AHB_TESTADDR field. + SLC_SLC_AHB_TEST_SLC_AHB_TESTADDR_Msk = 0x30 + // Position of SLC_AHB_TESTMODE field. + SLC_SLC_AHB_TEST_SLC_AHB_TESTMODE_Pos = 0x0 + // Bit mask of SLC_AHB_TESTMODE field. + SLC_SLC_AHB_TEST_SLC_AHB_TESTMODE_Msk = 0x7 + + // SLC_SDIO_ST: SLC_SDIO_ST + // Position of SLC_BUS_ST field. + SLC_SLC_SDIO_ST_SLC_BUS_ST_Pos = 0xc + // Bit mask of SLC_BUS_ST field. + SLC_SLC_SDIO_ST_SLC_BUS_ST_Msk = 0x7000 + // Position of SLC_SDIO_WAKEUP field. + SLC_SLC_SDIO_ST_SLC_SDIO_WAKEUP_Pos = 0x8 + // Bit mask of SLC_SDIO_WAKEUP field. + SLC_SLC_SDIO_ST_SLC_SDIO_WAKEUP_Msk = 0x100 + // Bit SLC_SDIO_WAKEUP. + SLC_SLC_SDIO_ST_SLC_SDIO_WAKEUP = 0x100 + // Position of SLC_FUNC_ST field. + SLC_SLC_SDIO_ST_SLC_FUNC_ST_Pos = 0x4 + // Bit mask of SLC_FUNC_ST field. + SLC_SLC_SDIO_ST_SLC_FUNC_ST_Msk = 0xf0 + // Position of SLC_CMD_ST field. + SLC_SLC_SDIO_ST_SLC_CMD_ST_Pos = 0x0 + // Bit mask of SLC_CMD_ST field. + SLC_SLC_SDIO_ST_SLC_CMD_ST_Msk = 0x7 + + // SLC_RX_DSCR_CONF: SLC_RX_DSCR_CONF + // Position of SLC_INFOR_NO_REPLACE field. + SLC_SLC_RX_DSCR_CONF_SLC_INFOR_NO_REPLACE_Pos = 0x9 + // Bit mask of SLC_INFOR_NO_REPLACE field. + SLC_SLC_RX_DSCR_CONF_SLC_INFOR_NO_REPLACE_Msk = 0x200 + // Bit SLC_INFOR_NO_REPLACE. + SLC_SLC_RX_DSCR_CONF_SLC_INFOR_NO_REPLACE = 0x200 + // Position of SLC_TOKEN_NO_REPLACE field. + SLC_SLC_RX_DSCR_CONF_SLC_TOKEN_NO_REPLACE_Pos = 0x8 + // Bit mask of SLC_TOKEN_NO_REPLACE field. + SLC_SLC_RX_DSCR_CONF_SLC_TOKEN_NO_REPLACE_Msk = 0x100 + // Bit SLC_TOKEN_NO_REPLACE. + SLC_SLC_RX_DSCR_CONF_SLC_TOKEN_NO_REPLACE = 0x100 + + // SLC_TXLINK_DSCR: SLC_TXLINK_DSCR + // Position of Register field. + SLC_SLC_TXLINK_DSCR_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_TXLINK_DSCR_Register_Msk = 0xffffffff + + // SLC_TXLINK_DSCR_BF0: SLC_TXLINK_DSCR_BF0 + // Position of Register field. + SLC_SLC_TXLINK_DSCR_BF0_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_TXLINK_DSCR_BF0_Register_Msk = 0xffffffff + + // SLC_TXLINK_DSCR_BF1: SLC_TXLINK_DSCR_BF1 + // Position of Register field. + SLC_SLC_TXLINK_DSCR_BF1_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_TXLINK_DSCR_BF1_Register_Msk = 0xffffffff + + // SLC_RXLINK_DSCR: SLC_RXLINK_DSCR + // Position of Register field. + SLC_SLC_RXLINK_DSCR_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_RXLINK_DSCR_Register_Msk = 0xffffffff + + // SLC_RXLINK_DSCR_BF0: SLC_RXLINK_DSCR_BF0 + // Position of Register field. + SLC_SLC_RXLINK_DSCR_BF0_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_RXLINK_DSCR_BF0_Register_Msk = 0xffffffff + + // SLC_RXLINK_DSCR_BF1: SLC_RXLINK_DSCR_BF1 + // Position of Register field. + SLC_SLC_RXLINK_DSCR_BF1_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_RXLINK_DSCR_BF1_Register_Msk = 0xffffffff + + // SLC_DATE: SLC_DATE + // Position of Register field. + SLC_SLC_DATE_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_DATE_Register_Msk = 0xffffffff + + // SLC_ID: SLC_ID + // Position of Register field. + SLC_SLC_ID_Register_Pos = 0x0 + // Bit mask of Register field. + SLC_SLC_ID_Register_Msk = 0xffffffff +) + +// Constants for SPI0 +const ( + // SPI_CMD: In the master mode, it is the start bit of a single operation. Self-clear by hardware + // Position of SPI_USR field. + SPI0_SPI_CMD_SPI_USR_Pos = 0x12 + // Bit mask of SPI_USR field. + SPI0_SPI_CMD_SPI_USR_Msk = 0x40000 + // Bit SPI_USR. + SPI0_SPI_CMD_SPI_USR = 0x40000 + // Position of SPI_READ field. + SPI0_SPI_CMD_SPI_READ_Pos = 0x1f + // Bit mask of SPI_READ field. + SPI0_SPI_CMD_SPI_READ_Msk = 0x80000000 + // Bit SPI_READ. + SPI0_SPI_CMD_SPI_READ = 0x80000000 + // Position of SPI_WRITE_ENABLE field. + SPI0_SPI_CMD_SPI_WRITE_ENABLE_Pos = 0x1e + // Bit mask of SPI_WRITE_ENABLE field. + SPI0_SPI_CMD_SPI_WRITE_ENABLE_Msk = 0x40000000 + // Bit SPI_WRITE_ENABLE. + SPI0_SPI_CMD_SPI_WRITE_ENABLE = 0x40000000 + // Position of SPI_WRITE_DISABLE field. + SPI0_SPI_CMD_SPI_WRITE_DISABLE_Pos = 0x1d + // Bit mask of SPI_WRITE_DISABLE field. + SPI0_SPI_CMD_SPI_WRITE_DISABLE_Msk = 0x20000000 + // Bit SPI_WRITE_DISABLE. + SPI0_SPI_CMD_SPI_WRITE_DISABLE = 0x20000000 + // Position of SPI_READ_ID field. + SPI0_SPI_CMD_SPI_READ_ID_Pos = 0x1c + // Bit mask of SPI_READ_ID field. + SPI0_SPI_CMD_SPI_READ_ID_Msk = 0x10000000 + // Bit SPI_READ_ID. + SPI0_SPI_CMD_SPI_READ_ID = 0x10000000 + // Position of SPI_READ_SR field. + SPI0_SPI_CMD_SPI_READ_SR_Pos = 0x1b + // Bit mask of SPI_READ_SR field. + SPI0_SPI_CMD_SPI_READ_SR_Msk = 0x8000000 + // Bit SPI_READ_SR. + SPI0_SPI_CMD_SPI_READ_SR = 0x8000000 + // Position of SPI_WRITE_SR field. + SPI0_SPI_CMD_SPI_WRITE_SR_Pos = 0x1a + // Bit mask of SPI_WRITE_SR field. + SPI0_SPI_CMD_SPI_WRITE_SR_Msk = 0x4000000 + // Bit SPI_WRITE_SR. + SPI0_SPI_CMD_SPI_WRITE_SR = 0x4000000 + // Position of SPI_PP field. + SPI0_SPI_CMD_SPI_PP_Pos = 0x19 + // Bit mask of SPI_PP field. + SPI0_SPI_CMD_SPI_PP_Msk = 0x2000000 + // Bit SPI_PP. + SPI0_SPI_CMD_SPI_PP = 0x2000000 + // Position of SPI_SE field. + SPI0_SPI_CMD_SPI_SE_Pos = 0x18 + // Bit mask of SPI_SE field. + SPI0_SPI_CMD_SPI_SE_Msk = 0x1000000 + // Bit SPI_SE. + SPI0_SPI_CMD_SPI_SE = 0x1000000 + // Position of SPI_BE field. + SPI0_SPI_CMD_SPI_BE_Pos = 0x17 + // Bit mask of SPI_BE field. + SPI0_SPI_CMD_SPI_BE_Msk = 0x800000 + // Bit SPI_BE. + SPI0_SPI_CMD_SPI_BE = 0x800000 + // Position of SPI_CE field. + SPI0_SPI_CMD_SPI_CE_Pos = 0x16 + // Bit mask of SPI_CE field. + SPI0_SPI_CMD_SPI_CE_Msk = 0x400000 + // Bit SPI_CE. + SPI0_SPI_CMD_SPI_CE = 0x400000 + // Position of SPI_DP field. + SPI0_SPI_CMD_SPI_DP_Pos = 0x15 + // Bit mask of SPI_DP field. + SPI0_SPI_CMD_SPI_DP_Msk = 0x200000 + // Bit SPI_DP. + SPI0_SPI_CMD_SPI_DP = 0x200000 + // Position of SPI_RES field. + SPI0_SPI_CMD_SPI_RES_Pos = 0x14 + // Bit mask of SPI_RES field. + SPI0_SPI_CMD_SPI_RES_Msk = 0x100000 + // Bit SPI_RES. + SPI0_SPI_CMD_SPI_RES = 0x100000 + // Position of SPI_HPM field. + SPI0_SPI_CMD_SPI_HPM_Pos = 0x13 + // Bit mask of SPI_HPM field. + SPI0_SPI_CMD_SPI_HPM_Msk = 0x80000 + // Bit SPI_HPM. + SPI0_SPI_CMD_SPI_HPM = 0x80000 + + // SPI_ADDR: In the master mode, it is the value of address in "address" phase. + // Position of IODATA_START_ADDR field. + SPI0_SPI_ADDR_IODATA_START_ADDR_Pos = 0x0 + // Bit mask of IODATA_START_ADDR field. + SPI0_SPI_ADDR_IODATA_START_ADDR_Msk = 0xffffffff + // Position of ADDRESS field. + SPI0_SPI_ADDR_ADDRESS_Pos = 0x0 + // Bit mask of ADDRESS field. + SPI0_SPI_ADDR_ADDRESS_Msk = 0xffffff + // Position of SIZE field. + SPI0_SPI_ADDR_SIZE_Pos = 0x18 + // Bit mask of SIZE field. + SPI0_SPI_ADDR_SIZE_Msk = 0xff000000 + + // SPI_CTRL: SPI_CTRL + // Position of SPI_WR_BIT_ORDER field. + SPI0_SPI_CTRL_SPI_WR_BIT_ORDER_Pos = 0x1a + // Bit mask of SPI_WR_BIT_ORDER field. + SPI0_SPI_CTRL_SPI_WR_BIT_ORDER_Msk = 0x4000000 + // Bit SPI_WR_BIT_ORDER. + SPI0_SPI_CTRL_SPI_WR_BIT_ORDER = 0x4000000 + // Position of SPI_RD_BIT_ORDER field. + SPI0_SPI_CTRL_SPI_RD_BIT_ORDER_Pos = 0x19 + // Bit mask of SPI_RD_BIT_ORDER field. + SPI0_SPI_CTRL_SPI_RD_BIT_ORDER_Msk = 0x2000000 + // Bit SPI_RD_BIT_ORDER. + SPI0_SPI_CTRL_SPI_RD_BIT_ORDER = 0x2000000 + // Position of SPI_QIO_MODE field. + SPI0_SPI_CTRL_SPI_QIO_MODE_Pos = 0x18 + // Bit mask of SPI_QIO_MODE field. + SPI0_SPI_CTRL_SPI_QIO_MODE_Msk = 0x1000000 + // Bit SPI_QIO_MODE. + SPI0_SPI_CTRL_SPI_QIO_MODE = 0x1000000 + // Position of SPI_DIO_MODE field. + SPI0_SPI_CTRL_SPI_DIO_MODE_Pos = 0x17 + // Bit mask of SPI_DIO_MODE field. + SPI0_SPI_CTRL_SPI_DIO_MODE_Msk = 0x800000 + // Bit SPI_DIO_MODE. + SPI0_SPI_CTRL_SPI_DIO_MODE = 0x800000 + // Position of SPI_QOUT_MODE field. + SPI0_SPI_CTRL_SPI_QOUT_MODE_Pos = 0x14 + // Bit mask of SPI_QOUT_MODE field. + SPI0_SPI_CTRL_SPI_QOUT_MODE_Msk = 0x100000 + // Bit SPI_QOUT_MODE. + SPI0_SPI_CTRL_SPI_QOUT_MODE = 0x100000 + // Position of SPI_DOUT_MODE field. + SPI0_SPI_CTRL_SPI_DOUT_MODE_Pos = 0xe + // Bit mask of SPI_DOUT_MODE field. + SPI0_SPI_CTRL_SPI_DOUT_MODE_Msk = 0x4000 + // Bit SPI_DOUT_MODE. + SPI0_SPI_CTRL_SPI_DOUT_MODE = 0x4000 + // Position of SPI_FASTRD_MODE field. + SPI0_SPI_CTRL_SPI_FASTRD_MODE_Pos = 0xd + // Bit mask of SPI_FASTRD_MODE field. + SPI0_SPI_CTRL_SPI_FASTRD_MODE_Msk = 0x2000 + // Bit SPI_FASTRD_MODE. + SPI0_SPI_CTRL_SPI_FASTRD_MODE = 0x2000 + + // SPI_CTRL1 + // Position of STATUS field. + SPI0_SPI_CTRL1_STATUS_Pos = 0x0 + // Bit mask of STATUS field. + SPI0_SPI_CTRL1_STATUS_Msk = 0xffff + // Position of WB_MODE field. + SPI0_SPI_CTRL1_WB_MODE_Pos = 0x10 + // Bit mask of WB_MODE field. + SPI0_SPI_CTRL1_WB_MODE_Msk = 0xff0000 + // Position of STATUS_EXT field. + SPI0_SPI_CTRL1_STATUS_EXT_Pos = 0x18 + // Bit mask of STATUS_EXT field. + SPI0_SPI_CTRL1_STATUS_EXT_Msk = 0xff000000 + + // SPI_RD_STATUS: In the slave mode, this register are the status register for the master to read out. + // Position of SLV_RD_STATUS field. + SPI0_SPI_RD_STATUS_SLV_RD_STATUS_Pos = 0x0 + // Bit mask of SLV_RD_STATUS field. + SPI0_SPI_RD_STATUS_SLV_RD_STATUS_Msk = 0xffffffff + + // SPI_CTRL2: spi_cs signal is delayed by 80MHz clock cycles + // Position of SPI_CS_DELAY_NUM field. + SPI0_SPI_CTRL2_SPI_CS_DELAY_NUM_Pos = 0x1c + // Bit mask of SPI_CS_DELAY_NUM field. + SPI0_SPI_CTRL2_SPI_CS_DELAY_NUM_Msk = 0xf0000000 + // Position of SPI_CS_DELAY_MODE field. + SPI0_SPI_CTRL2_SPI_CS_DELAY_MODE_Pos = 0x1a + // Bit mask of SPI_CS_DELAY_MODE field. + SPI0_SPI_CTRL2_SPI_CS_DELAY_MODE_Msk = 0xc000000 + // Position of SPI_MOSI_DELAY_NUM field. + SPI0_SPI_CTRL2_SPI_MOSI_DELAY_NUM_Pos = 0x17 + // Bit mask of SPI_MOSI_DELAY_NUM field. + SPI0_SPI_CTRL2_SPI_MOSI_DELAY_NUM_Msk = 0x3800000 + // Position of SPI_MOSI_DELAY_MODE field. + SPI0_SPI_CTRL2_SPI_MOSI_DELAY_MODE_Pos = 0x15 + // Bit mask of SPI_MOSI_DELAY_MODE field. + SPI0_SPI_CTRL2_SPI_MOSI_DELAY_MODE_Msk = 0x600000 + // Position of SPI_MISO_DELAY_NUM field. + SPI0_SPI_CTRL2_SPI_MISO_DELAY_NUM_Pos = 0x12 + // Bit mask of SPI_MISO_DELAY_NUM field. + SPI0_SPI_CTRL2_SPI_MISO_DELAY_NUM_Msk = 0x1c0000 + // Position of SPI_MISO_DELAY_MODE field. + SPI0_SPI_CTRL2_SPI_MISO_DELAY_MODE_Pos = 0x10 + // Bit mask of SPI_MISO_DELAY_MODE field. + SPI0_SPI_CTRL2_SPI_MISO_DELAY_MODE_Msk = 0x30000 + + // SPI_CLOCK: In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. + // Position of SPI_CLK_EQU_SYSCLK field. + SPI0_SPI_CLOCK_SPI_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of SPI_CLK_EQU_SYSCLK field. + SPI0_SPI_CLOCK_SPI_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit SPI_CLK_EQU_SYSCLK. + SPI0_SPI_CLOCK_SPI_CLK_EQU_SYSCLK = 0x80000000 + // Position of SPI_CLKDIV_PRE field. + SPI0_SPI_CLOCK_SPI_CLKDIV_PRE_Pos = 0x12 + // Bit mask of SPI_CLKDIV_PRE field. + SPI0_SPI_CLOCK_SPI_CLKDIV_PRE_Msk = 0x7ffc0000 + // Position of SPI_CLKCNT_N field. + SPI0_SPI_CLOCK_SPI_CLKCNT_N_Pos = 0xc + // Bit mask of SPI_CLKCNT_N field. + SPI0_SPI_CLOCK_SPI_CLKCNT_N_Msk = 0x3f000 + // Position of SPI_CLKCNT_H field. + SPI0_SPI_CLOCK_SPI_CLKCNT_H_Pos = 0x6 + // Bit mask of SPI_CLKCNT_H field. + SPI0_SPI_CLOCK_SPI_CLKCNT_H_Msk = 0xfc0 + // Position of SPI_CLKCNT_L field. + SPI0_SPI_CLOCK_SPI_CLKCNT_L_Pos = 0x0 + // Bit mask of SPI_CLKCNT_L field. + SPI0_SPI_CLOCK_SPI_CLKCNT_L_Msk = 0x3f + + // SPI_USER: This bit enable the "command" phase of an operation. + // Position of SPI_USR_COMMAND field. + SPI0_SPI_USER_SPI_USR_COMMAND_Pos = 0x1f + // Bit mask of SPI_USR_COMMAND field. + SPI0_SPI_USER_SPI_USR_COMMAND_Msk = 0x80000000 + // Bit SPI_USR_COMMAND. + SPI0_SPI_USER_SPI_USR_COMMAND = 0x80000000 + // Position of SPI_USR_ADDR field. + SPI0_SPI_USER_SPI_USR_ADDR_Pos = 0x1e + // Bit mask of SPI_USR_ADDR field. + SPI0_SPI_USER_SPI_USR_ADDR_Msk = 0x40000000 + // Bit SPI_USR_ADDR. + SPI0_SPI_USER_SPI_USR_ADDR = 0x40000000 + // Position of SPI_USR_DUMMY field. + SPI0_SPI_USER_SPI_USR_DUMMY_Pos = 0x1d + // Bit mask of SPI_USR_DUMMY field. + SPI0_SPI_USER_SPI_USR_DUMMY_Msk = 0x20000000 + // Bit SPI_USR_DUMMY. + SPI0_SPI_USER_SPI_USR_DUMMY = 0x20000000 + // Position of SPI_USR_MISO field. + SPI0_SPI_USER_SPI_USR_MISO_Pos = 0x1c + // Bit mask of SPI_USR_MISO field. + SPI0_SPI_USER_SPI_USR_MISO_Msk = 0x10000000 + // Bit SPI_USR_MISO. + SPI0_SPI_USER_SPI_USR_MISO = 0x10000000 + // Position of SPI_USR_MOSI field. + SPI0_SPI_USER_SPI_USR_MOSI_Pos = 0x1b + // Bit mask of SPI_USR_MOSI field. + SPI0_SPI_USER_SPI_USR_MOSI_Msk = 0x8000000 + // Bit SPI_USR_MOSI. + SPI0_SPI_USER_SPI_USR_MOSI = 0x8000000 + // Position of REG_USR_MOSI_HIGHPART field. + SPI0_SPI_USER_REG_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of REG_USR_MOSI_HIGHPART field. + SPI0_SPI_USER_REG_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit REG_USR_MOSI_HIGHPART. + SPI0_SPI_USER_REG_USR_MOSI_HIGHPART = 0x2000000 + // Position of REG_USR_MISO_HIGHPART field. + SPI0_SPI_USER_REG_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of REG_USR_MISO_HIGHPART field. + SPI0_SPI_USER_REG_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit REG_USR_MISO_HIGHPART. + SPI0_SPI_USER_REG_USR_MISO_HIGHPART = 0x1000000 + // Position of SPI_SIO field. + SPI0_SPI_USER_SPI_SIO_Pos = 0x10 + // Bit mask of SPI_SIO field. + SPI0_SPI_USER_SPI_SIO_Msk = 0x10000 + // Bit SPI_SIO. + SPI0_SPI_USER_SPI_SIO = 0x10000 + // Position of SPI_FWRITE_QIO field. + SPI0_SPI_USER_SPI_FWRITE_QIO_Pos = 0xf + // Bit mask of SPI_FWRITE_QIO field. + SPI0_SPI_USER_SPI_FWRITE_QIO_Msk = 0x8000 + // Bit SPI_FWRITE_QIO. + SPI0_SPI_USER_SPI_FWRITE_QIO = 0x8000 + // Position of SPI_FWRITE_DIO field. + SPI0_SPI_USER_SPI_FWRITE_DIO_Pos = 0xe + // Bit mask of SPI_FWRITE_DIO field. + SPI0_SPI_USER_SPI_FWRITE_DIO_Msk = 0x4000 + // Bit SPI_FWRITE_DIO. + SPI0_SPI_USER_SPI_FWRITE_DIO = 0x4000 + // Position of SPI_FWRITE_QUAD field. + SPI0_SPI_USER_SPI_FWRITE_QUAD_Pos = 0xd + // Bit mask of SPI_FWRITE_QUAD field. + SPI0_SPI_USER_SPI_FWRITE_QUAD_Msk = 0x2000 + // Bit SPI_FWRITE_QUAD. + SPI0_SPI_USER_SPI_FWRITE_QUAD = 0x2000 + // Position of SPI_FWRITE_DUAL field. + SPI0_SPI_USER_SPI_FWRITE_DUAL_Pos = 0xc + // Bit mask of SPI_FWRITE_DUAL field. + SPI0_SPI_USER_SPI_FWRITE_DUAL_Msk = 0x1000 + // Bit SPI_FWRITE_DUAL. + SPI0_SPI_USER_SPI_FWRITE_DUAL = 0x1000 + // Position of SPI_WR_BYTE_ORDER field. + SPI0_SPI_USER_SPI_WR_BYTE_ORDER_Pos = 0xb + // Bit mask of SPI_WR_BYTE_ORDER field. + SPI0_SPI_USER_SPI_WR_BYTE_ORDER_Msk = 0x800 + // Bit SPI_WR_BYTE_ORDER. + SPI0_SPI_USER_SPI_WR_BYTE_ORDER = 0x800 + // Position of SPI_RD_BYTE_ORDER field. + SPI0_SPI_USER_SPI_RD_BYTE_ORDER_Pos = 0xa + // Bit mask of SPI_RD_BYTE_ORDER field. + SPI0_SPI_USER_SPI_RD_BYTE_ORDER_Msk = 0x400 + // Bit SPI_RD_BYTE_ORDER. + SPI0_SPI_USER_SPI_RD_BYTE_ORDER = 0x400 + // Position of SPI_CK_I_EDGE field. + SPI0_SPI_USER_SPI_CK_I_EDGE_Pos = 0x6 + // Bit mask of SPI_CK_I_EDGE field. + SPI0_SPI_USER_SPI_CK_I_EDGE_Msk = 0x40 + // Bit SPI_CK_I_EDGE. + SPI0_SPI_USER_SPI_CK_I_EDGE = 0x40 + // Position of SPI_CK_O_EDGE field. + SPI0_SPI_USER_SPI_CK_O_EDGE_Pos = 0x7 + // Bit mask of SPI_CK_O_EDGE field. + SPI0_SPI_USER_SPI_CK_O_EDGE_Msk = 0x80 + // Bit SPI_CK_O_EDGE. + SPI0_SPI_USER_SPI_CK_O_EDGE = 0x80 + // Position of SPI_CS_SETUP field. + SPI0_SPI_USER_SPI_CS_SETUP_Pos = 0x5 + // Bit mask of SPI_CS_SETUP field. + SPI0_SPI_USER_SPI_CS_SETUP_Msk = 0x20 + // Bit SPI_CS_SETUP. + SPI0_SPI_USER_SPI_CS_SETUP = 0x20 + // Position of SPI_CS_HOLD field. + SPI0_SPI_USER_SPI_CS_HOLD_Pos = 0x4 + // Bit mask of SPI_CS_HOLD field. + SPI0_SPI_USER_SPI_CS_HOLD_Msk = 0x10 + // Bit SPI_CS_HOLD. + SPI0_SPI_USER_SPI_CS_HOLD = 0x10 + // Position of SPI_AHB_USER_COMMAND field. + SPI0_SPI_USER_SPI_AHB_USER_COMMAND_Pos = 0x3 + // Bit mask of SPI_AHB_USER_COMMAND field. + SPI0_SPI_USER_SPI_AHB_USER_COMMAND_Msk = 0x8 + // Bit SPI_AHB_USER_COMMAND. + SPI0_SPI_USER_SPI_AHB_USER_COMMAND = 0x8 + // Position of SPI_FLASH_MODE field. + SPI0_SPI_USER_SPI_FLASH_MODE_Pos = 0x2 + // Bit mask of SPI_FLASH_MODE field. + SPI0_SPI_USER_SPI_FLASH_MODE_Msk = 0x4 + // Bit SPI_FLASH_MODE. + SPI0_SPI_USER_SPI_FLASH_MODE = 0x4 + // Position of SPI_AHB_USER_COMMAND_4BYTE field. + SPI0_SPI_USER_SPI_AHB_USER_COMMAND_4BYTE_Pos = 0x1 + // Bit mask of SPI_AHB_USER_COMMAND_4BYTE field. + SPI0_SPI_USER_SPI_AHB_USER_COMMAND_4BYTE_Msk = 0x2 + // Bit SPI_AHB_USER_COMMAND_4BYTE. + SPI0_SPI_USER_SPI_AHB_USER_COMMAND_4BYTE = 0x2 + // Position of SPI_DUPLEX field. + SPI0_SPI_USER_SPI_DUPLEX_Pos = 0x0 + // Bit mask of SPI_DUPLEX field. + SPI0_SPI_USER_SPI_DUPLEX_Msk = 0x1 + // Bit SPI_DUPLEX. + SPI0_SPI_USER_SPI_DUPLEX = 0x1 + + // SPI_USER1: The length in bits of "address" phase. The register value shall be (bit_num-1) + // Position of REG_USR_ADDR_BITLEN field. + SPI0_SPI_USER1_REG_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of REG_USR_ADDR_BITLEN field. + SPI0_SPI_USER1_REG_USR_ADDR_BITLEN_Msk = 0xfc000000 + // Position of REG_USR_MOSI_BITLEN field. + SPI0_SPI_USER1_REG_USR_MOSI_BITLEN_Pos = 0x11 + // Bit mask of REG_USR_MOSI_BITLEN field. + SPI0_SPI_USER1_REG_USR_MOSI_BITLEN_Msk = 0x3fe0000 + // Position of REG_USR_MISO_BITLEN field. + SPI0_SPI_USER1_REG_USR_MISO_BITLEN_Pos = 0x8 + // Bit mask of REG_USR_MISO_BITLEN field. + SPI0_SPI_USER1_REG_USR_MISO_BITLEN_Msk = 0x1ff00 + // Position of REG_USR_DUMMY_CYCLELEN field. + SPI0_SPI_USER1_REG_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of REG_USR_DUMMY_CYCLELEN field. + SPI0_SPI_USER1_REG_USR_DUMMY_CYCLELEN_Msk = 0xff + + // SPI_USER2: The length in bits of "command" phase. The register value shall be (bit_num-1) + // Position of REG_USR_COMMAND_BITLEN field. + SPI0_SPI_USER2_REG_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of REG_USR_COMMAND_BITLEN field. + SPI0_SPI_USER2_REG_USR_COMMAND_BITLEN_Msk = 0xf0000000 + // Position of REG_USR_COMMAND_VALUE field. + SPI0_SPI_USER2_REG_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of REG_USR_COMMAND_VALUE field. + SPI0_SPI_USER2_REG_USR_COMMAND_VALUE_Msk = 0xffff + + // SPI_WR_STATUS: In the slave mode, this register are the status register for the master to write into. + // Position of SLV_WR_STATUS field. + SPI0_SPI_WR_STATUS_SLV_WR_STATUS_Pos = 0x0 + // Bit mask of SLV_WR_STATUS field. + SPI0_SPI_WR_STATUS_SLV_WR_STATUS_Msk = 0xffffffff + + // SPI_PIN: 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + // Position of SPI_CS2_DIS field. + SPI0_SPI_PIN_SPI_CS2_DIS_Pos = 0x2 + // Bit mask of SPI_CS2_DIS field. + SPI0_SPI_PIN_SPI_CS2_DIS_Msk = 0x4 + // Bit SPI_CS2_DIS. + SPI0_SPI_PIN_SPI_CS2_DIS = 0x4 + // Position of SPI_CS1_DIS field. + SPI0_SPI_PIN_SPI_CS1_DIS_Pos = 0x1 + // Bit mask of SPI_CS1_DIS field. + SPI0_SPI_PIN_SPI_CS1_DIS_Msk = 0x2 + // Bit SPI_CS1_DIS. + SPI0_SPI_PIN_SPI_CS1_DIS = 0x2 + // Position of SPI_CS0_DIS field. + SPI0_SPI_PIN_SPI_CS0_DIS_Pos = 0x0 + // Bit mask of SPI_CS0_DIS field. + SPI0_SPI_PIN_SPI_CS0_DIS_Msk = 0x1 + // Bit SPI_CS0_DIS. + SPI0_SPI_PIN_SPI_CS0_DIS = 0x1 + // Position of SPI_IDLE_EDGE field. + SPI0_SPI_PIN_SPI_IDLE_EDGE_Pos = 0x1d + // Bit mask of SPI_IDLE_EDGE field. + SPI0_SPI_PIN_SPI_IDLE_EDGE_Msk = 0x20000000 + // Bit SPI_IDLE_EDGE. + SPI0_SPI_PIN_SPI_IDLE_EDGE = 0x20000000 + + // SPI_SLAVE: It is the synchronous reset signal of the module. This bit is self-cleared by hardware. + // Position of SPI_SYNC_RESET field. + SPI0_SPI_SLAVE_SPI_SYNC_RESET_Pos = 0x1f + // Bit mask of SPI_SYNC_RESET field. + SPI0_SPI_SLAVE_SPI_SYNC_RESET_Msk = 0x80000000 + // Bit SPI_SYNC_RESET. + SPI0_SPI_SLAVE_SPI_SYNC_RESET = 0x80000000 + // Position of SPI_SLAVE_MODE field. + SPI0_SPI_SLAVE_SPI_SLAVE_MODE_Pos = 0x1e + // Bit mask of SPI_SLAVE_MODE field. + SPI0_SPI_SLAVE_SPI_SLAVE_MODE_Msk = 0x40000000 + // Bit SPI_SLAVE_MODE. + SPI0_SPI_SLAVE_SPI_SLAVE_MODE = 0x40000000 + // Position of SLV_CMD_DEFINE field. + SPI0_SPI_SLAVE_SLV_CMD_DEFINE_Pos = 0x1b + // Bit mask of SLV_CMD_DEFINE field. + SPI0_SPI_SLAVE_SLV_CMD_DEFINE_Msk = 0x8000000 + // Bit SLV_CMD_DEFINE. + SPI0_SPI_SLAVE_SLV_CMD_DEFINE = 0x8000000 + // Position of SPI_TRANS_CNT field. + SPI0_SPI_SLAVE_SPI_TRANS_CNT_Pos = 0x17 + // Bit mask of SPI_TRANS_CNT field. + SPI0_SPI_SLAVE_SPI_TRANS_CNT_Msk = 0x7800000 + // Position of SPI_INT_EN field. + SPI0_SPI_SLAVE_SPI_INT_EN_Pos = 0x5 + // Bit mask of SPI_INT_EN field. + SPI0_SPI_SLAVE_SPI_INT_EN_Msk = 0x3e0 + // Position of SPI_TRANS_DONE field. + SPI0_SPI_SLAVE_SPI_TRANS_DONE_Pos = 0x4 + // Bit mask of SPI_TRANS_DONE field. + SPI0_SPI_SLAVE_SPI_TRANS_DONE_Msk = 0x10 + // Bit SPI_TRANS_DONE. + SPI0_SPI_SLAVE_SPI_TRANS_DONE = 0x10 + // Position of SLV_WR_STA_DONE field. + SPI0_SPI_SLAVE_SLV_WR_STA_DONE_Pos = 0x3 + // Bit mask of SLV_WR_STA_DONE field. + SPI0_SPI_SLAVE_SLV_WR_STA_DONE_Msk = 0x8 + // Bit SLV_WR_STA_DONE. + SPI0_SPI_SLAVE_SLV_WR_STA_DONE = 0x8 + // Position of SLV_RD_STA_DONE field. + SPI0_SPI_SLAVE_SLV_RD_STA_DONE_Pos = 0x2 + // Bit mask of SLV_RD_STA_DONE field. + SPI0_SPI_SLAVE_SLV_RD_STA_DONE_Msk = 0x4 + // Bit SLV_RD_STA_DONE. + SPI0_SPI_SLAVE_SLV_RD_STA_DONE = 0x4 + // Position of SLV_WR_BUF_DONE field. + SPI0_SPI_SLAVE_SLV_WR_BUF_DONE_Pos = 0x1 + // Bit mask of SLV_WR_BUF_DONE field. + SPI0_SPI_SLAVE_SLV_WR_BUF_DONE_Msk = 0x2 + // Bit SLV_WR_BUF_DONE. + SPI0_SPI_SLAVE_SLV_WR_BUF_DONE = 0x2 + // Position of SLV_RD_BUF_DONE field. + SPI0_SPI_SLAVE_SLV_RD_BUF_DONE_Pos = 0x0 + // Bit mask of SLV_RD_BUF_DONE field. + SPI0_SPI_SLAVE_SLV_RD_BUF_DONE_Msk = 0x1 + // Bit SLV_RD_BUF_DONE. + SPI0_SPI_SLAVE_SLV_RD_BUF_DONE = 0x1 + + // SPI_SLAVE1: In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) + // Position of SLV_STATUS_BITLEN field. + SPI0_SPI_SLAVE1_SLV_STATUS_BITLEN_Pos = 0x1b + // Bit mask of SLV_STATUS_BITLEN field. + SPI0_SPI_SLAVE1_SLV_STATUS_BITLEN_Msk = 0xf8000000 + // Position of SLV_BUF_BITLEN field. + SPI0_SPI_SLAVE1_SLV_BUF_BITLEN_Pos = 0x10 + // Bit mask of SLV_BUF_BITLEN field. + SPI0_SPI_SLAVE1_SLV_BUF_BITLEN_Msk = 0x1ff0000 + // Position of SLV_RD_ADDR_BITLEN field. + SPI0_SPI_SLAVE1_SLV_RD_ADDR_BITLEN_Pos = 0xa + // Bit mask of SLV_RD_ADDR_BITLEN field. + SPI0_SPI_SLAVE1_SLV_RD_ADDR_BITLEN_Msk = 0xfc00 + // Position of SLV_WR_ADDR_BITLEN field. + SPI0_SPI_SLAVE1_SLV_WR_ADDR_BITLEN_Pos = 0x4 + // Bit mask of SLV_WR_ADDR_BITLEN field. + SPI0_SPI_SLAVE1_SLV_WR_ADDR_BITLEN_Msk = 0x3f0 + // Position of SLV_WRSTA_DUMMY_EN field. + SPI0_SPI_SLAVE1_SLV_WRSTA_DUMMY_EN_Pos = 0x3 + // Bit mask of SLV_WRSTA_DUMMY_EN field. + SPI0_SPI_SLAVE1_SLV_WRSTA_DUMMY_EN_Msk = 0x8 + // Bit SLV_WRSTA_DUMMY_EN. + SPI0_SPI_SLAVE1_SLV_WRSTA_DUMMY_EN = 0x8 + // Position of SLV_RDSTA_DUMMY_EN field. + SPI0_SPI_SLAVE1_SLV_RDSTA_DUMMY_EN_Pos = 0x2 + // Bit mask of SLV_RDSTA_DUMMY_EN field. + SPI0_SPI_SLAVE1_SLV_RDSTA_DUMMY_EN_Msk = 0x4 + // Bit SLV_RDSTA_DUMMY_EN. + SPI0_SPI_SLAVE1_SLV_RDSTA_DUMMY_EN = 0x4 + // Position of SLV_WRBUF_DUMMY_EN field. + SPI0_SPI_SLAVE1_SLV_WRBUF_DUMMY_EN_Pos = 0x1 + // Bit mask of SLV_WRBUF_DUMMY_EN field. + SPI0_SPI_SLAVE1_SLV_WRBUF_DUMMY_EN_Msk = 0x2 + // Bit SLV_WRBUF_DUMMY_EN. + SPI0_SPI_SLAVE1_SLV_WRBUF_DUMMY_EN = 0x2 + // Position of SLV_RDBUF_DUMMY_EN field. + SPI0_SPI_SLAVE1_SLV_RDBUF_DUMMY_EN_Pos = 0x0 + // Bit mask of SLV_RDBUF_DUMMY_EN field. + SPI0_SPI_SLAVE1_SLV_RDBUF_DUMMY_EN_Msk = 0x1 + // Bit SLV_RDBUF_DUMMY_EN. + SPI0_SPI_SLAVE1_SLV_RDBUF_DUMMY_EN = 0x1 + + // SPI_SLAVE2: In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) + // Position of SLV_WRBUF_DUMMY_CYCLELEN field. + SPI0_SPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN_Pos = 0x18 + // Bit mask of SLV_WRBUF_DUMMY_CYCLELEN field. + SPI0_SPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN_Msk = 0xff000000 + // Position of SLV_RDBUF_DUMMY_CYCLELEN field. + SPI0_SPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN_Pos = 0x10 + // Bit mask of SLV_RDBUF_DUMMY_CYCLELEN field. + SPI0_SPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN_Msk = 0xff0000 + // Position of SLV_WRSTA_DUMMY_CYCLELEN field. + SPI0_SPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN_Pos = 0x8 + // Bit mask of SLV_WRSTA_DUMMY_CYCLELEN field. + SPI0_SPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN_Msk = 0xff00 + // Position of SLV_RDSTA_DUMMY_CYCLELEN field. + SPI0_SPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of SLV_RDSTA_DUMMY_CYCLELEN field. + SPI0_SPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN_Msk = 0xff + + // SPI_SLAVE3: In slave mode, it is the value of "write-status" command + // Position of SLV_WRSTA_CMD_VALUE field. + SPI0_SPI_SLAVE3_SLV_WRSTA_CMD_VALUE_Pos = 0x18 + // Bit mask of SLV_WRSTA_CMD_VALUE field. + SPI0_SPI_SLAVE3_SLV_WRSTA_CMD_VALUE_Msk = 0xff000000 + // Position of SLV_RDSTA_CMD_VALUE field. + SPI0_SPI_SLAVE3_SLV_RDSTA_CMD_VALUE_Pos = 0x10 + // Bit mask of SLV_RDSTA_CMD_VALUE field. + SPI0_SPI_SLAVE3_SLV_RDSTA_CMD_VALUE_Msk = 0xff0000 + // Position of SLV_WRBUF_CMD_VALUE field. + SPI0_SPI_SLAVE3_SLV_WRBUF_CMD_VALUE_Pos = 0x8 + // Bit mask of SLV_WRBUF_CMD_VALUE field. + SPI0_SPI_SLAVE3_SLV_WRBUF_CMD_VALUE_Msk = 0xff00 + // Position of SLV_RDBUF_CMD_VALUE field. + SPI0_SPI_SLAVE3_SLV_RDBUF_CMD_VALUE_Pos = 0x0 + // Bit mask of SLV_RDBUF_CMD_VALUE field. + SPI0_SPI_SLAVE3_SLV_RDBUF_CMD_VALUE_Msk = 0xff + + // SPI_W0: the data inside the buffer of the SPI module, byte 0 + // Position of SPI_W0 field. + SPI0_SPI_W0_SPI_W0_Pos = 0x0 + // Bit mask of SPI_W0 field. + SPI0_SPI_W0_SPI_W0_Msk = 0xffffffff + + // SPI_W1: the data inside the buffer of the SPI module, byte 1 + // Position of SPI_W1 field. + SPI0_SPI_W1_SPI_W1_Pos = 0x0 + // Bit mask of SPI_W1 field. + SPI0_SPI_W1_SPI_W1_Msk = 0xffffffff + + // SPI_W2: the data inside the buffer of the SPI module, byte 2 + // Position of SPI_W2 field. + SPI0_SPI_W2_SPI_W2_Pos = 0x0 + // Bit mask of SPI_W2 field. + SPI0_SPI_W2_SPI_W2_Msk = 0xffffffff + + // SPI_W3: the data inside the buffer of the SPI module, byte 3 + // Position of SPI_W3 field. + SPI0_SPI_W3_SPI_W3_Pos = 0x0 + // Bit mask of SPI_W3 field. + SPI0_SPI_W3_SPI_W3_Msk = 0xffffffff + + // SPI_W4: the data inside the buffer of the SPI module, byte 4 + // Position of SPI_W4 field. + SPI0_SPI_W4_SPI_W4_Pos = 0x0 + // Bit mask of SPI_W4 field. + SPI0_SPI_W4_SPI_W4_Msk = 0xffffffff + + // SPI_W5: the data inside the buffer of the SPI module, byte 5 + // Position of SPI_W5 field. + SPI0_SPI_W5_SPI_W5_Pos = 0x0 + // Bit mask of SPI_W5 field. + SPI0_SPI_W5_SPI_W5_Msk = 0xffffffff + + // SPI_EXT3: This register is for two SPI masters to share the same cs, clock and data signals. + // Position of REG_INT_HOLD_ENA field. + SPI0_SPI_EXT3_REG_INT_HOLD_ENA_Pos = 0x0 + // Bit mask of REG_INT_HOLD_ENA field. + SPI0_SPI_EXT3_REG_INT_HOLD_ENA_Msk = 0x3 + + // SPI_W6: the data inside the buffer of the SPI module, byte 6 + // Position of SPI_W6 field. + SPI0_SPI_W6_SPI_W6_Pos = 0x0 + // Bit mask of SPI_W6 field. + SPI0_SPI_W6_SPI_W6_Msk = 0xffffffff + + // SPI_W7: the data inside the buffer of the SPI module, byte 7 + // Position of SPI_W7 field. + SPI0_SPI_W7_SPI_W7_Pos = 0x0 + // Bit mask of SPI_W7 field. + SPI0_SPI_W7_SPI_W7_Msk = 0xffffffff + + // SPI_W8: the data inside the buffer of the SPI module, byte 8 + // Position of SPI_W8 field. + SPI0_SPI_W8_SPI_W8_Pos = 0x0 + // Bit mask of SPI_W8 field. + SPI0_SPI_W8_SPI_W8_Msk = 0xffffffff + + // SPI_W9: the data inside the buffer of the SPI module, byte 9 + // Position of SPI_W9 field. + SPI0_SPI_W9_SPI_W9_Pos = 0x0 + // Bit mask of SPI_W9 field. + SPI0_SPI_W9_SPI_W9_Msk = 0xffffffff + + // SPI_W10: the data inside the buffer of the SPI module, byte 10 + // Position of SPI_W10 field. + SPI0_SPI_W10_SPI_W10_Pos = 0x0 + // Bit mask of SPI_W10 field. + SPI0_SPI_W10_SPI_W10_Msk = 0xffffffff + + // SPI_W11: the data inside the buffer of the SPI module, byte 11 + // Position of SPI_W11 field. + SPI0_SPI_W11_SPI_W11_Pos = 0x0 + // Bit mask of SPI_W11 field. + SPI0_SPI_W11_SPI_W11_Msk = 0xffffffff + + // SPI_W12: the data inside the buffer of the SPI module, byte 12 + // Position of SPI_W12 field. + SPI0_SPI_W12_SPI_W12_Pos = 0x0 + // Bit mask of SPI_W12 field. + SPI0_SPI_W12_SPI_W12_Msk = 0xffffffff + + // SPI_W13: the data inside the buffer of the SPI module, byte 13 + // Position of SPI_W13 field. + SPI0_SPI_W13_SPI_W13_Pos = 0x0 + // Bit mask of SPI_W13 field. + SPI0_SPI_W13_SPI_W13_Msk = 0xffffffff + + // SPI_W14: the data inside the buffer of the SPI module, byte 14 + // Position of SPI_W14 field. + SPI0_SPI_W14_SPI_W14_Pos = 0x0 + // Bit mask of SPI_W14 field. + SPI0_SPI_W14_SPI_W14_Msk = 0xffffffff + + // SPI_W15: the data inside the buffer of the SPI module, byte 15 + // Position of SPI_W15 field. + SPI0_SPI_W15_SPI_W15_Pos = 0x0 + // Bit mask of SPI_W15 field. + SPI0_SPI_W15_SPI_W15_Msk = 0xffffffff +) + +// Constants for SPI1 +const ( + // SPI_CMD: In the master mode, it is the start bit of a single operation. Self-clear by hardware + // Position of SPI_USR field. + SPI1_SPI_CMD_SPI_USR_Pos = 0x12 + // Bit mask of SPI_USR field. + SPI1_SPI_CMD_SPI_USR_Msk = 0x40000 + // Bit SPI_USR. + SPI1_SPI_CMD_SPI_USR = 0x40000 + // Position of SPI_READ field. + SPI1_SPI_CMD_SPI_READ_Pos = 0x1f + // Bit mask of SPI_READ field. + SPI1_SPI_CMD_SPI_READ_Msk = 0x80000000 + // Bit SPI_READ. + SPI1_SPI_CMD_SPI_READ = 0x80000000 + // Position of SPI_WRITE_ENABLE field. + SPI1_SPI_CMD_SPI_WRITE_ENABLE_Pos = 0x1e + // Bit mask of SPI_WRITE_ENABLE field. + SPI1_SPI_CMD_SPI_WRITE_ENABLE_Msk = 0x40000000 + // Bit SPI_WRITE_ENABLE. + SPI1_SPI_CMD_SPI_WRITE_ENABLE = 0x40000000 + // Position of SPI_WRITE_DISABLE field. + SPI1_SPI_CMD_SPI_WRITE_DISABLE_Pos = 0x1d + // Bit mask of SPI_WRITE_DISABLE field. + SPI1_SPI_CMD_SPI_WRITE_DISABLE_Msk = 0x20000000 + // Bit SPI_WRITE_DISABLE. + SPI1_SPI_CMD_SPI_WRITE_DISABLE = 0x20000000 + // Position of SPI_READ_ID field. + SPI1_SPI_CMD_SPI_READ_ID_Pos = 0x1c + // Bit mask of SPI_READ_ID field. + SPI1_SPI_CMD_SPI_READ_ID_Msk = 0x10000000 + // Bit SPI_READ_ID. + SPI1_SPI_CMD_SPI_READ_ID = 0x10000000 + // Position of SPI_READ_SR field. + SPI1_SPI_CMD_SPI_READ_SR_Pos = 0x1b + // Bit mask of SPI_READ_SR field. + SPI1_SPI_CMD_SPI_READ_SR_Msk = 0x8000000 + // Bit SPI_READ_SR. + SPI1_SPI_CMD_SPI_READ_SR = 0x8000000 + // Position of SPI_WRITE_SR field. + SPI1_SPI_CMD_SPI_WRITE_SR_Pos = 0x1a + // Bit mask of SPI_WRITE_SR field. + SPI1_SPI_CMD_SPI_WRITE_SR_Msk = 0x4000000 + // Bit SPI_WRITE_SR. + SPI1_SPI_CMD_SPI_WRITE_SR = 0x4000000 + // Position of SPI_PP field. + SPI1_SPI_CMD_SPI_PP_Pos = 0x19 + // Bit mask of SPI_PP field. + SPI1_SPI_CMD_SPI_PP_Msk = 0x2000000 + // Bit SPI_PP. + SPI1_SPI_CMD_SPI_PP = 0x2000000 + // Position of SPI_SE field. + SPI1_SPI_CMD_SPI_SE_Pos = 0x18 + // Bit mask of SPI_SE field. + SPI1_SPI_CMD_SPI_SE_Msk = 0x1000000 + // Bit SPI_SE. + SPI1_SPI_CMD_SPI_SE = 0x1000000 + // Position of SPI_BE field. + SPI1_SPI_CMD_SPI_BE_Pos = 0x17 + // Bit mask of SPI_BE field. + SPI1_SPI_CMD_SPI_BE_Msk = 0x800000 + // Bit SPI_BE. + SPI1_SPI_CMD_SPI_BE = 0x800000 + // Position of SPI_CE field. + SPI1_SPI_CMD_SPI_CE_Pos = 0x16 + // Bit mask of SPI_CE field. + SPI1_SPI_CMD_SPI_CE_Msk = 0x400000 + // Bit SPI_CE. + SPI1_SPI_CMD_SPI_CE = 0x400000 + // Position of SPI_DP field. + SPI1_SPI_CMD_SPI_DP_Pos = 0x15 + // Bit mask of SPI_DP field. + SPI1_SPI_CMD_SPI_DP_Msk = 0x200000 + // Bit SPI_DP. + SPI1_SPI_CMD_SPI_DP = 0x200000 + // Position of SPI_RES field. + SPI1_SPI_CMD_SPI_RES_Pos = 0x14 + // Bit mask of SPI_RES field. + SPI1_SPI_CMD_SPI_RES_Msk = 0x100000 + // Bit SPI_RES. + SPI1_SPI_CMD_SPI_RES = 0x100000 + // Position of SPI_HPM field. + SPI1_SPI_CMD_SPI_HPM_Pos = 0x13 + // Bit mask of SPI_HPM field. + SPI1_SPI_CMD_SPI_HPM_Msk = 0x80000 + // Bit SPI_HPM. + SPI1_SPI_CMD_SPI_HPM = 0x80000 + + // SPI_ADDR: In the master mode, it is the value of address in "address" phase. + // Position of IODATA_START_ADDR field. + SPI1_SPI_ADDR_IODATA_START_ADDR_Pos = 0x0 + // Bit mask of IODATA_START_ADDR field. + SPI1_SPI_ADDR_IODATA_START_ADDR_Msk = 0xffffffff + // Position of ADDRESS field. + SPI1_SPI_ADDR_ADDRESS_Pos = 0x0 + // Bit mask of ADDRESS field. + SPI1_SPI_ADDR_ADDRESS_Msk = 0xffffff + // Position of SIZE field. + SPI1_SPI_ADDR_SIZE_Pos = 0x18 + // Bit mask of SIZE field. + SPI1_SPI_ADDR_SIZE_Msk = 0xff000000 + + // SPI_CTRL: SPI_CTRL + // Position of SPI_WR_BIT_ORDER field. + SPI1_SPI_CTRL_SPI_WR_BIT_ORDER_Pos = 0x1a + // Bit mask of SPI_WR_BIT_ORDER field. + SPI1_SPI_CTRL_SPI_WR_BIT_ORDER_Msk = 0x4000000 + // Bit SPI_WR_BIT_ORDER. + SPI1_SPI_CTRL_SPI_WR_BIT_ORDER = 0x4000000 + // Position of SPI_RD_BIT_ORDER field. + SPI1_SPI_CTRL_SPI_RD_BIT_ORDER_Pos = 0x19 + // Bit mask of SPI_RD_BIT_ORDER field. + SPI1_SPI_CTRL_SPI_RD_BIT_ORDER_Msk = 0x2000000 + // Bit SPI_RD_BIT_ORDER. + SPI1_SPI_CTRL_SPI_RD_BIT_ORDER = 0x2000000 + // Position of SPI_QIO_MODE field. + SPI1_SPI_CTRL_SPI_QIO_MODE_Pos = 0x18 + // Bit mask of SPI_QIO_MODE field. + SPI1_SPI_CTRL_SPI_QIO_MODE_Msk = 0x1000000 + // Bit SPI_QIO_MODE. + SPI1_SPI_CTRL_SPI_QIO_MODE = 0x1000000 + // Position of SPI_DIO_MODE field. + SPI1_SPI_CTRL_SPI_DIO_MODE_Pos = 0x17 + // Bit mask of SPI_DIO_MODE field. + SPI1_SPI_CTRL_SPI_DIO_MODE_Msk = 0x800000 + // Bit SPI_DIO_MODE. + SPI1_SPI_CTRL_SPI_DIO_MODE = 0x800000 + // Position of SPI_QOUT_MODE field. + SPI1_SPI_CTRL_SPI_QOUT_MODE_Pos = 0x14 + // Bit mask of SPI_QOUT_MODE field. + SPI1_SPI_CTRL_SPI_QOUT_MODE_Msk = 0x100000 + // Bit SPI_QOUT_MODE. + SPI1_SPI_CTRL_SPI_QOUT_MODE = 0x100000 + // Position of SPI_DOUT_MODE field. + SPI1_SPI_CTRL_SPI_DOUT_MODE_Pos = 0xe + // Bit mask of SPI_DOUT_MODE field. + SPI1_SPI_CTRL_SPI_DOUT_MODE_Msk = 0x4000 + // Bit SPI_DOUT_MODE. + SPI1_SPI_CTRL_SPI_DOUT_MODE = 0x4000 + // Position of SPI_FASTRD_MODE field. + SPI1_SPI_CTRL_SPI_FASTRD_MODE_Pos = 0xd + // Bit mask of SPI_FASTRD_MODE field. + SPI1_SPI_CTRL_SPI_FASTRD_MODE_Msk = 0x2000 + // Bit SPI_FASTRD_MODE. + SPI1_SPI_CTRL_SPI_FASTRD_MODE = 0x2000 + + // SPI_CTRL1 + // Position of STATUS field. + SPI1_SPI_CTRL1_STATUS_Pos = 0x0 + // Bit mask of STATUS field. + SPI1_SPI_CTRL1_STATUS_Msk = 0xffff + // Position of WB_MODE field. + SPI1_SPI_CTRL1_WB_MODE_Pos = 0x10 + // Bit mask of WB_MODE field. + SPI1_SPI_CTRL1_WB_MODE_Msk = 0xff0000 + // Position of STATUS_EXT field. + SPI1_SPI_CTRL1_STATUS_EXT_Pos = 0x18 + // Bit mask of STATUS_EXT field. + SPI1_SPI_CTRL1_STATUS_EXT_Msk = 0xff000000 + + // SPI_RD_STATUS: In the slave mode, this register are the status register for the master to read out. + // Position of SLV_RD_STATUS field. + SPI1_SPI_RD_STATUS_SLV_RD_STATUS_Pos = 0x0 + // Bit mask of SLV_RD_STATUS field. + SPI1_SPI_RD_STATUS_SLV_RD_STATUS_Msk = 0xffffffff + + // SPI_CTRL2: spi_cs signal is delayed by 80MHz clock cycles + // Position of SPI_CS_DELAY_NUM field. + SPI1_SPI_CTRL2_SPI_CS_DELAY_NUM_Pos = 0x1c + // Bit mask of SPI_CS_DELAY_NUM field. + SPI1_SPI_CTRL2_SPI_CS_DELAY_NUM_Msk = 0xf0000000 + // Position of SPI_CS_DELAY_MODE field. + SPI1_SPI_CTRL2_SPI_CS_DELAY_MODE_Pos = 0x1a + // Bit mask of SPI_CS_DELAY_MODE field. + SPI1_SPI_CTRL2_SPI_CS_DELAY_MODE_Msk = 0xc000000 + // Position of SPI_MOSI_DELAY_NUM field. + SPI1_SPI_CTRL2_SPI_MOSI_DELAY_NUM_Pos = 0x17 + // Bit mask of SPI_MOSI_DELAY_NUM field. + SPI1_SPI_CTRL2_SPI_MOSI_DELAY_NUM_Msk = 0x3800000 + // Position of SPI_MOSI_DELAY_MODE field. + SPI1_SPI_CTRL2_SPI_MOSI_DELAY_MODE_Pos = 0x15 + // Bit mask of SPI_MOSI_DELAY_MODE field. + SPI1_SPI_CTRL2_SPI_MOSI_DELAY_MODE_Msk = 0x600000 + // Position of SPI_MISO_DELAY_NUM field. + SPI1_SPI_CTRL2_SPI_MISO_DELAY_NUM_Pos = 0x12 + // Bit mask of SPI_MISO_DELAY_NUM field. + SPI1_SPI_CTRL2_SPI_MISO_DELAY_NUM_Msk = 0x1c0000 + // Position of SPI_MISO_DELAY_MODE field. + SPI1_SPI_CTRL2_SPI_MISO_DELAY_MODE_Pos = 0x10 + // Bit mask of SPI_MISO_DELAY_MODE field. + SPI1_SPI_CTRL2_SPI_MISO_DELAY_MODE_Msk = 0x30000 + + // SPI_CLOCK: In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. + // Position of SPI_CLK_EQU_SYSCLK field. + SPI1_SPI_CLOCK_SPI_CLK_EQU_SYSCLK_Pos = 0x1f + // Bit mask of SPI_CLK_EQU_SYSCLK field. + SPI1_SPI_CLOCK_SPI_CLK_EQU_SYSCLK_Msk = 0x80000000 + // Bit SPI_CLK_EQU_SYSCLK. + SPI1_SPI_CLOCK_SPI_CLK_EQU_SYSCLK = 0x80000000 + // Position of SPI_CLKDIV_PRE field. + SPI1_SPI_CLOCK_SPI_CLKDIV_PRE_Pos = 0x12 + // Bit mask of SPI_CLKDIV_PRE field. + SPI1_SPI_CLOCK_SPI_CLKDIV_PRE_Msk = 0x7ffc0000 + // Position of SPI_CLKCNT_N field. + SPI1_SPI_CLOCK_SPI_CLKCNT_N_Pos = 0xc + // Bit mask of SPI_CLKCNT_N field. + SPI1_SPI_CLOCK_SPI_CLKCNT_N_Msk = 0x3f000 + // Position of SPI_CLKCNT_H field. + SPI1_SPI_CLOCK_SPI_CLKCNT_H_Pos = 0x6 + // Bit mask of SPI_CLKCNT_H field. + SPI1_SPI_CLOCK_SPI_CLKCNT_H_Msk = 0xfc0 + // Position of SPI_CLKCNT_L field. + SPI1_SPI_CLOCK_SPI_CLKCNT_L_Pos = 0x0 + // Bit mask of SPI_CLKCNT_L field. + SPI1_SPI_CLOCK_SPI_CLKCNT_L_Msk = 0x3f + + // SPI_USER: This bit enable the "command" phase of an operation. + // Position of SPI_USR_COMMAND field. + SPI1_SPI_USER_SPI_USR_COMMAND_Pos = 0x1f + // Bit mask of SPI_USR_COMMAND field. + SPI1_SPI_USER_SPI_USR_COMMAND_Msk = 0x80000000 + // Bit SPI_USR_COMMAND. + SPI1_SPI_USER_SPI_USR_COMMAND = 0x80000000 + // Position of SPI_USR_ADDR field. + SPI1_SPI_USER_SPI_USR_ADDR_Pos = 0x1e + // Bit mask of SPI_USR_ADDR field. + SPI1_SPI_USER_SPI_USR_ADDR_Msk = 0x40000000 + // Bit SPI_USR_ADDR. + SPI1_SPI_USER_SPI_USR_ADDR = 0x40000000 + // Position of SPI_USR_DUMMY field. + SPI1_SPI_USER_SPI_USR_DUMMY_Pos = 0x1d + // Bit mask of SPI_USR_DUMMY field. + SPI1_SPI_USER_SPI_USR_DUMMY_Msk = 0x20000000 + // Bit SPI_USR_DUMMY. + SPI1_SPI_USER_SPI_USR_DUMMY = 0x20000000 + // Position of SPI_USR_MISO field. + SPI1_SPI_USER_SPI_USR_MISO_Pos = 0x1c + // Bit mask of SPI_USR_MISO field. + SPI1_SPI_USER_SPI_USR_MISO_Msk = 0x10000000 + // Bit SPI_USR_MISO. + SPI1_SPI_USER_SPI_USR_MISO = 0x10000000 + // Position of SPI_USR_MOSI field. + SPI1_SPI_USER_SPI_USR_MOSI_Pos = 0x1b + // Bit mask of SPI_USR_MOSI field. + SPI1_SPI_USER_SPI_USR_MOSI_Msk = 0x8000000 + // Bit SPI_USR_MOSI. + SPI1_SPI_USER_SPI_USR_MOSI = 0x8000000 + // Position of REG_USR_MOSI_HIGHPART field. + SPI1_SPI_USER_REG_USR_MOSI_HIGHPART_Pos = 0x19 + // Bit mask of REG_USR_MOSI_HIGHPART field. + SPI1_SPI_USER_REG_USR_MOSI_HIGHPART_Msk = 0x2000000 + // Bit REG_USR_MOSI_HIGHPART. + SPI1_SPI_USER_REG_USR_MOSI_HIGHPART = 0x2000000 + // Position of REG_USR_MISO_HIGHPART field. + SPI1_SPI_USER_REG_USR_MISO_HIGHPART_Pos = 0x18 + // Bit mask of REG_USR_MISO_HIGHPART field. + SPI1_SPI_USER_REG_USR_MISO_HIGHPART_Msk = 0x1000000 + // Bit REG_USR_MISO_HIGHPART. + SPI1_SPI_USER_REG_USR_MISO_HIGHPART = 0x1000000 + // Position of SPI_SIO field. + SPI1_SPI_USER_SPI_SIO_Pos = 0x10 + // Bit mask of SPI_SIO field. + SPI1_SPI_USER_SPI_SIO_Msk = 0x10000 + // Bit SPI_SIO. + SPI1_SPI_USER_SPI_SIO = 0x10000 + // Position of SPI_FWRITE_QIO field. + SPI1_SPI_USER_SPI_FWRITE_QIO_Pos = 0xf + // Bit mask of SPI_FWRITE_QIO field. + SPI1_SPI_USER_SPI_FWRITE_QIO_Msk = 0x8000 + // Bit SPI_FWRITE_QIO. + SPI1_SPI_USER_SPI_FWRITE_QIO = 0x8000 + // Position of SPI_FWRITE_DIO field. + SPI1_SPI_USER_SPI_FWRITE_DIO_Pos = 0xe + // Bit mask of SPI_FWRITE_DIO field. + SPI1_SPI_USER_SPI_FWRITE_DIO_Msk = 0x4000 + // Bit SPI_FWRITE_DIO. + SPI1_SPI_USER_SPI_FWRITE_DIO = 0x4000 + // Position of SPI_FWRITE_QUAD field. + SPI1_SPI_USER_SPI_FWRITE_QUAD_Pos = 0xd + // Bit mask of SPI_FWRITE_QUAD field. + SPI1_SPI_USER_SPI_FWRITE_QUAD_Msk = 0x2000 + // Bit SPI_FWRITE_QUAD. + SPI1_SPI_USER_SPI_FWRITE_QUAD = 0x2000 + // Position of SPI_FWRITE_DUAL field. + SPI1_SPI_USER_SPI_FWRITE_DUAL_Pos = 0xc + // Bit mask of SPI_FWRITE_DUAL field. + SPI1_SPI_USER_SPI_FWRITE_DUAL_Msk = 0x1000 + // Bit SPI_FWRITE_DUAL. + SPI1_SPI_USER_SPI_FWRITE_DUAL = 0x1000 + // Position of SPI_WR_BYTE_ORDER field. + SPI1_SPI_USER_SPI_WR_BYTE_ORDER_Pos = 0xb + // Bit mask of SPI_WR_BYTE_ORDER field. + SPI1_SPI_USER_SPI_WR_BYTE_ORDER_Msk = 0x800 + // Bit SPI_WR_BYTE_ORDER. + SPI1_SPI_USER_SPI_WR_BYTE_ORDER = 0x800 + // Position of SPI_RD_BYTE_ORDER field. + SPI1_SPI_USER_SPI_RD_BYTE_ORDER_Pos = 0xa + // Bit mask of SPI_RD_BYTE_ORDER field. + SPI1_SPI_USER_SPI_RD_BYTE_ORDER_Msk = 0x400 + // Bit SPI_RD_BYTE_ORDER. + SPI1_SPI_USER_SPI_RD_BYTE_ORDER = 0x400 + // Position of SPI_CK_I_EDGE field. + SPI1_SPI_USER_SPI_CK_I_EDGE_Pos = 0x6 + // Bit mask of SPI_CK_I_EDGE field. + SPI1_SPI_USER_SPI_CK_I_EDGE_Msk = 0x40 + // Bit SPI_CK_I_EDGE. + SPI1_SPI_USER_SPI_CK_I_EDGE = 0x40 + // Position of SPI_CK_O_EDGE field. + SPI1_SPI_USER_SPI_CK_O_EDGE_Pos = 0x7 + // Bit mask of SPI_CK_O_EDGE field. + SPI1_SPI_USER_SPI_CK_O_EDGE_Msk = 0x80 + // Bit SPI_CK_O_EDGE. + SPI1_SPI_USER_SPI_CK_O_EDGE = 0x80 + // Position of SPI_CS_SETUP field. + SPI1_SPI_USER_SPI_CS_SETUP_Pos = 0x5 + // Bit mask of SPI_CS_SETUP field. + SPI1_SPI_USER_SPI_CS_SETUP_Msk = 0x20 + // Bit SPI_CS_SETUP. + SPI1_SPI_USER_SPI_CS_SETUP = 0x20 + // Position of SPI_CS_HOLD field. + SPI1_SPI_USER_SPI_CS_HOLD_Pos = 0x4 + // Bit mask of SPI_CS_HOLD field. + SPI1_SPI_USER_SPI_CS_HOLD_Msk = 0x10 + // Bit SPI_CS_HOLD. + SPI1_SPI_USER_SPI_CS_HOLD = 0x10 + // Position of SPI_AHB_USER_COMMAND field. + SPI1_SPI_USER_SPI_AHB_USER_COMMAND_Pos = 0x3 + // Bit mask of SPI_AHB_USER_COMMAND field. + SPI1_SPI_USER_SPI_AHB_USER_COMMAND_Msk = 0x8 + // Bit SPI_AHB_USER_COMMAND. + SPI1_SPI_USER_SPI_AHB_USER_COMMAND = 0x8 + // Position of SPI_FLASH_MODE field. + SPI1_SPI_USER_SPI_FLASH_MODE_Pos = 0x2 + // Bit mask of SPI_FLASH_MODE field. + SPI1_SPI_USER_SPI_FLASH_MODE_Msk = 0x4 + // Bit SPI_FLASH_MODE. + SPI1_SPI_USER_SPI_FLASH_MODE = 0x4 + // Position of SPI_AHB_USER_COMMAND_4BYTE field. + SPI1_SPI_USER_SPI_AHB_USER_COMMAND_4BYTE_Pos = 0x1 + // Bit mask of SPI_AHB_USER_COMMAND_4BYTE field. + SPI1_SPI_USER_SPI_AHB_USER_COMMAND_4BYTE_Msk = 0x2 + // Bit SPI_AHB_USER_COMMAND_4BYTE. + SPI1_SPI_USER_SPI_AHB_USER_COMMAND_4BYTE = 0x2 + // Position of SPI_DUPLEX field. + SPI1_SPI_USER_SPI_DUPLEX_Pos = 0x0 + // Bit mask of SPI_DUPLEX field. + SPI1_SPI_USER_SPI_DUPLEX_Msk = 0x1 + // Bit SPI_DUPLEX. + SPI1_SPI_USER_SPI_DUPLEX = 0x1 + + // SPI_USER1: The length in bits of "address" phase. The register value shall be (bit_num-1) + // Position of REG_USR_ADDR_BITLEN field. + SPI1_SPI_USER1_REG_USR_ADDR_BITLEN_Pos = 0x1a + // Bit mask of REG_USR_ADDR_BITLEN field. + SPI1_SPI_USER1_REG_USR_ADDR_BITLEN_Msk = 0xfc000000 + // Position of REG_USR_MOSI_BITLEN field. + SPI1_SPI_USER1_REG_USR_MOSI_BITLEN_Pos = 0x11 + // Bit mask of REG_USR_MOSI_BITLEN field. + SPI1_SPI_USER1_REG_USR_MOSI_BITLEN_Msk = 0x3fe0000 + // Position of REG_USR_MISO_BITLEN field. + SPI1_SPI_USER1_REG_USR_MISO_BITLEN_Pos = 0x8 + // Bit mask of REG_USR_MISO_BITLEN field. + SPI1_SPI_USER1_REG_USR_MISO_BITLEN_Msk = 0x1ff00 + // Position of REG_USR_DUMMY_CYCLELEN field. + SPI1_SPI_USER1_REG_USR_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of REG_USR_DUMMY_CYCLELEN field. + SPI1_SPI_USER1_REG_USR_DUMMY_CYCLELEN_Msk = 0xff + + // SPI_USER2: The length in bits of "command" phase. The register value shall be (bit_num-1) + // Position of REG_USR_COMMAND_BITLEN field. + SPI1_SPI_USER2_REG_USR_COMMAND_BITLEN_Pos = 0x1c + // Bit mask of REG_USR_COMMAND_BITLEN field. + SPI1_SPI_USER2_REG_USR_COMMAND_BITLEN_Msk = 0xf0000000 + // Position of REG_USR_COMMAND_VALUE field. + SPI1_SPI_USER2_REG_USR_COMMAND_VALUE_Pos = 0x0 + // Bit mask of REG_USR_COMMAND_VALUE field. + SPI1_SPI_USER2_REG_USR_COMMAND_VALUE_Msk = 0xffff + + // SPI_WR_STATUS: In the slave mode, this register are the status register for the master to write into. + // Position of SLV_WR_STATUS field. + SPI1_SPI_WR_STATUS_SLV_WR_STATUS_Pos = 0x0 + // Bit mask of SLV_WR_STATUS field. + SPI1_SPI_WR_STATUS_SLV_WR_STATUS_Msk = 0xffffffff + + // SPI_PIN: 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + // Position of SPI_CS2_DIS field. + SPI1_SPI_PIN_SPI_CS2_DIS_Pos = 0x2 + // Bit mask of SPI_CS2_DIS field. + SPI1_SPI_PIN_SPI_CS2_DIS_Msk = 0x4 + // Bit SPI_CS2_DIS. + SPI1_SPI_PIN_SPI_CS2_DIS = 0x4 + // Position of SPI_CS1_DIS field. + SPI1_SPI_PIN_SPI_CS1_DIS_Pos = 0x1 + // Bit mask of SPI_CS1_DIS field. + SPI1_SPI_PIN_SPI_CS1_DIS_Msk = 0x2 + // Bit SPI_CS1_DIS. + SPI1_SPI_PIN_SPI_CS1_DIS = 0x2 + // Position of SPI_CS0_DIS field. + SPI1_SPI_PIN_SPI_CS0_DIS_Pos = 0x0 + // Bit mask of SPI_CS0_DIS field. + SPI1_SPI_PIN_SPI_CS0_DIS_Msk = 0x1 + // Bit SPI_CS0_DIS. + SPI1_SPI_PIN_SPI_CS0_DIS = 0x1 + // Position of SPI_IDLE_EDGE field. + SPI1_SPI_PIN_SPI_IDLE_EDGE_Pos = 0x1d + // Bit mask of SPI_IDLE_EDGE field. + SPI1_SPI_PIN_SPI_IDLE_EDGE_Msk = 0x20000000 + // Bit SPI_IDLE_EDGE. + SPI1_SPI_PIN_SPI_IDLE_EDGE = 0x20000000 + + // SPI_SLAVE: It is the synchronous reset signal of the module. This bit is self-cleared by hardware. + // Position of SPI_SYNC_RESET field. + SPI1_SPI_SLAVE_SPI_SYNC_RESET_Pos = 0x1f + // Bit mask of SPI_SYNC_RESET field. + SPI1_SPI_SLAVE_SPI_SYNC_RESET_Msk = 0x80000000 + // Bit SPI_SYNC_RESET. + SPI1_SPI_SLAVE_SPI_SYNC_RESET = 0x80000000 + // Position of SPI_SLAVE_MODE field. + SPI1_SPI_SLAVE_SPI_SLAVE_MODE_Pos = 0x1e + // Bit mask of SPI_SLAVE_MODE field. + SPI1_SPI_SLAVE_SPI_SLAVE_MODE_Msk = 0x40000000 + // Bit SPI_SLAVE_MODE. + SPI1_SPI_SLAVE_SPI_SLAVE_MODE = 0x40000000 + // Position of SLV_CMD_DEFINE field. + SPI1_SPI_SLAVE_SLV_CMD_DEFINE_Pos = 0x1b + // Bit mask of SLV_CMD_DEFINE field. + SPI1_SPI_SLAVE_SLV_CMD_DEFINE_Msk = 0x8000000 + // Bit SLV_CMD_DEFINE. + SPI1_SPI_SLAVE_SLV_CMD_DEFINE = 0x8000000 + // Position of SPI_TRANS_CNT field. + SPI1_SPI_SLAVE_SPI_TRANS_CNT_Pos = 0x17 + // Bit mask of SPI_TRANS_CNT field. + SPI1_SPI_SLAVE_SPI_TRANS_CNT_Msk = 0x7800000 + // Position of SPI_INT_EN field. + SPI1_SPI_SLAVE_SPI_INT_EN_Pos = 0x5 + // Bit mask of SPI_INT_EN field. + SPI1_SPI_SLAVE_SPI_INT_EN_Msk = 0x3e0 + // Position of SPI_TRANS_DONE field. + SPI1_SPI_SLAVE_SPI_TRANS_DONE_Pos = 0x4 + // Bit mask of SPI_TRANS_DONE field. + SPI1_SPI_SLAVE_SPI_TRANS_DONE_Msk = 0x10 + // Bit SPI_TRANS_DONE. + SPI1_SPI_SLAVE_SPI_TRANS_DONE = 0x10 + // Position of SLV_WR_STA_DONE field. + SPI1_SPI_SLAVE_SLV_WR_STA_DONE_Pos = 0x3 + // Bit mask of SLV_WR_STA_DONE field. + SPI1_SPI_SLAVE_SLV_WR_STA_DONE_Msk = 0x8 + // Bit SLV_WR_STA_DONE. + SPI1_SPI_SLAVE_SLV_WR_STA_DONE = 0x8 + // Position of SLV_RD_STA_DONE field. + SPI1_SPI_SLAVE_SLV_RD_STA_DONE_Pos = 0x2 + // Bit mask of SLV_RD_STA_DONE field. + SPI1_SPI_SLAVE_SLV_RD_STA_DONE_Msk = 0x4 + // Bit SLV_RD_STA_DONE. + SPI1_SPI_SLAVE_SLV_RD_STA_DONE = 0x4 + // Position of SLV_WR_BUF_DONE field. + SPI1_SPI_SLAVE_SLV_WR_BUF_DONE_Pos = 0x1 + // Bit mask of SLV_WR_BUF_DONE field. + SPI1_SPI_SLAVE_SLV_WR_BUF_DONE_Msk = 0x2 + // Bit SLV_WR_BUF_DONE. + SPI1_SPI_SLAVE_SLV_WR_BUF_DONE = 0x2 + // Position of SLV_RD_BUF_DONE field. + SPI1_SPI_SLAVE_SLV_RD_BUF_DONE_Pos = 0x0 + // Bit mask of SLV_RD_BUF_DONE field. + SPI1_SPI_SLAVE_SLV_RD_BUF_DONE_Msk = 0x1 + // Bit SLV_RD_BUF_DONE. + SPI1_SPI_SLAVE_SLV_RD_BUF_DONE = 0x1 + + // SPI_SLAVE1: In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) + // Position of SLV_STATUS_BITLEN field. + SPI1_SPI_SLAVE1_SLV_STATUS_BITLEN_Pos = 0x1b + // Bit mask of SLV_STATUS_BITLEN field. + SPI1_SPI_SLAVE1_SLV_STATUS_BITLEN_Msk = 0xf8000000 + // Position of SLV_BUF_BITLEN field. + SPI1_SPI_SLAVE1_SLV_BUF_BITLEN_Pos = 0x10 + // Bit mask of SLV_BUF_BITLEN field. + SPI1_SPI_SLAVE1_SLV_BUF_BITLEN_Msk = 0x1ff0000 + // Position of SLV_RD_ADDR_BITLEN field. + SPI1_SPI_SLAVE1_SLV_RD_ADDR_BITLEN_Pos = 0xa + // Bit mask of SLV_RD_ADDR_BITLEN field. + SPI1_SPI_SLAVE1_SLV_RD_ADDR_BITLEN_Msk = 0xfc00 + // Position of SLV_WR_ADDR_BITLEN field. + SPI1_SPI_SLAVE1_SLV_WR_ADDR_BITLEN_Pos = 0x4 + // Bit mask of SLV_WR_ADDR_BITLEN field. + SPI1_SPI_SLAVE1_SLV_WR_ADDR_BITLEN_Msk = 0x3f0 + // Position of SLV_WRSTA_DUMMY_EN field. + SPI1_SPI_SLAVE1_SLV_WRSTA_DUMMY_EN_Pos = 0x3 + // Bit mask of SLV_WRSTA_DUMMY_EN field. + SPI1_SPI_SLAVE1_SLV_WRSTA_DUMMY_EN_Msk = 0x8 + // Bit SLV_WRSTA_DUMMY_EN. + SPI1_SPI_SLAVE1_SLV_WRSTA_DUMMY_EN = 0x8 + // Position of SLV_RDSTA_DUMMY_EN field. + SPI1_SPI_SLAVE1_SLV_RDSTA_DUMMY_EN_Pos = 0x2 + // Bit mask of SLV_RDSTA_DUMMY_EN field. + SPI1_SPI_SLAVE1_SLV_RDSTA_DUMMY_EN_Msk = 0x4 + // Bit SLV_RDSTA_DUMMY_EN. + SPI1_SPI_SLAVE1_SLV_RDSTA_DUMMY_EN = 0x4 + // Position of SLV_WRBUF_DUMMY_EN field. + SPI1_SPI_SLAVE1_SLV_WRBUF_DUMMY_EN_Pos = 0x1 + // Bit mask of SLV_WRBUF_DUMMY_EN field. + SPI1_SPI_SLAVE1_SLV_WRBUF_DUMMY_EN_Msk = 0x2 + // Bit SLV_WRBUF_DUMMY_EN. + SPI1_SPI_SLAVE1_SLV_WRBUF_DUMMY_EN = 0x2 + // Position of SLV_RDBUF_DUMMY_EN field. + SPI1_SPI_SLAVE1_SLV_RDBUF_DUMMY_EN_Pos = 0x0 + // Bit mask of SLV_RDBUF_DUMMY_EN field. + SPI1_SPI_SLAVE1_SLV_RDBUF_DUMMY_EN_Msk = 0x1 + // Bit SLV_RDBUF_DUMMY_EN. + SPI1_SPI_SLAVE1_SLV_RDBUF_DUMMY_EN = 0x1 + + // SPI_SLAVE2: In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) + // Position of SLV_WRBUF_DUMMY_CYCLELEN field. + SPI1_SPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN_Pos = 0x18 + // Bit mask of SLV_WRBUF_DUMMY_CYCLELEN field. + SPI1_SPI_SLAVE2_SLV_WRBUF_DUMMY_CYCLELEN_Msk = 0xff000000 + // Position of SLV_RDBUF_DUMMY_CYCLELEN field. + SPI1_SPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN_Pos = 0x10 + // Bit mask of SLV_RDBUF_DUMMY_CYCLELEN field. + SPI1_SPI_SLAVE2_SLV_RDBUF_DUMMY_CYCLELEN_Msk = 0xff0000 + // Position of SLV_WRSTA_DUMMY_CYCLELEN field. + SPI1_SPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN_Pos = 0x8 + // Bit mask of SLV_WRSTA_DUMMY_CYCLELEN field. + SPI1_SPI_SLAVE2_SLV_WRSTA_DUMMY_CYCLELEN_Msk = 0xff00 + // Position of SLV_RDSTA_DUMMY_CYCLELEN field. + SPI1_SPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN_Pos = 0x0 + // Bit mask of SLV_RDSTA_DUMMY_CYCLELEN field. + SPI1_SPI_SLAVE2_SLV_RDSTA_DUMMY_CYCLELEN_Msk = 0xff + + // SPI_SLAVE3: In slave mode, it is the value of "write-status" command + // Position of SLV_WRSTA_CMD_VALUE field. + SPI1_SPI_SLAVE3_SLV_WRSTA_CMD_VALUE_Pos = 0x18 + // Bit mask of SLV_WRSTA_CMD_VALUE field. + SPI1_SPI_SLAVE3_SLV_WRSTA_CMD_VALUE_Msk = 0xff000000 + // Position of SLV_RDSTA_CMD_VALUE field. + SPI1_SPI_SLAVE3_SLV_RDSTA_CMD_VALUE_Pos = 0x10 + // Bit mask of SLV_RDSTA_CMD_VALUE field. + SPI1_SPI_SLAVE3_SLV_RDSTA_CMD_VALUE_Msk = 0xff0000 + // Position of SLV_WRBUF_CMD_VALUE field. + SPI1_SPI_SLAVE3_SLV_WRBUF_CMD_VALUE_Pos = 0x8 + // Bit mask of SLV_WRBUF_CMD_VALUE field. + SPI1_SPI_SLAVE3_SLV_WRBUF_CMD_VALUE_Msk = 0xff00 + // Position of SLV_RDBUF_CMD_VALUE field. + SPI1_SPI_SLAVE3_SLV_RDBUF_CMD_VALUE_Pos = 0x0 + // Bit mask of SLV_RDBUF_CMD_VALUE field. + SPI1_SPI_SLAVE3_SLV_RDBUF_CMD_VALUE_Msk = 0xff + + // SPI_W0: the data inside the buffer of the SPI module, byte 0 + // Position of SPI_W0 field. + SPI1_SPI_W0_SPI_W0_Pos = 0x0 + // Bit mask of SPI_W0 field. + SPI1_SPI_W0_SPI_W0_Msk = 0xffffffff + + // SPI_W1: the data inside the buffer of the SPI module, byte 1 + // Position of SPI_W1 field. + SPI1_SPI_W1_SPI_W1_Pos = 0x0 + // Bit mask of SPI_W1 field. + SPI1_SPI_W1_SPI_W1_Msk = 0xffffffff + + // SPI_W2: the data inside the buffer of the SPI module, byte 2 + // Position of SPI_W2 field. + SPI1_SPI_W2_SPI_W2_Pos = 0x0 + // Bit mask of SPI_W2 field. + SPI1_SPI_W2_SPI_W2_Msk = 0xffffffff + + // SPI_W3: the data inside the buffer of the SPI module, byte 3 + // Position of SPI_W3 field. + SPI1_SPI_W3_SPI_W3_Pos = 0x0 + // Bit mask of SPI_W3 field. + SPI1_SPI_W3_SPI_W3_Msk = 0xffffffff + + // SPI_W4: the data inside the buffer of the SPI module, byte 4 + // Position of SPI_W4 field. + SPI1_SPI_W4_SPI_W4_Pos = 0x0 + // Bit mask of SPI_W4 field. + SPI1_SPI_W4_SPI_W4_Msk = 0xffffffff + + // SPI_W5: the data inside the buffer of the SPI module, byte 5 + // Position of SPI_W5 field. + SPI1_SPI_W5_SPI_W5_Pos = 0x0 + // Bit mask of SPI_W5 field. + SPI1_SPI_W5_SPI_W5_Msk = 0xffffffff + + // SPI_EXT3: This register is for two SPI masters to share the same cs, clock and data signals. + // Position of REG_INT_HOLD_ENA field. + SPI1_SPI_EXT3_REG_INT_HOLD_ENA_Pos = 0x0 + // Bit mask of REG_INT_HOLD_ENA field. + SPI1_SPI_EXT3_REG_INT_HOLD_ENA_Msk = 0x3 + + // SPI_W6: the data inside the buffer of the SPI module, byte 6 + // Position of SPI_W6 field. + SPI1_SPI_W6_SPI_W6_Pos = 0x0 + // Bit mask of SPI_W6 field. + SPI1_SPI_W6_SPI_W6_Msk = 0xffffffff + + // SPI_W7: the data inside the buffer of the SPI module, byte 7 + // Position of SPI_W7 field. + SPI1_SPI_W7_SPI_W7_Pos = 0x0 + // Bit mask of SPI_W7 field. + SPI1_SPI_W7_SPI_W7_Msk = 0xffffffff + + // SPI_W8: the data inside the buffer of the SPI module, byte 8 + // Position of SPI_W8 field. + SPI1_SPI_W8_SPI_W8_Pos = 0x0 + // Bit mask of SPI_W8 field. + SPI1_SPI_W8_SPI_W8_Msk = 0xffffffff + + // SPI_W9: the data inside the buffer of the SPI module, byte 9 + // Position of SPI_W9 field. + SPI1_SPI_W9_SPI_W9_Pos = 0x0 + // Bit mask of SPI_W9 field. + SPI1_SPI_W9_SPI_W9_Msk = 0xffffffff + + // SPI_W10: the data inside the buffer of the SPI module, byte 10 + // Position of SPI_W10 field. + SPI1_SPI_W10_SPI_W10_Pos = 0x0 + // Bit mask of SPI_W10 field. + SPI1_SPI_W10_SPI_W10_Msk = 0xffffffff + + // SPI_W11: the data inside the buffer of the SPI module, byte 11 + // Position of SPI_W11 field. + SPI1_SPI_W11_SPI_W11_Pos = 0x0 + // Bit mask of SPI_W11 field. + SPI1_SPI_W11_SPI_W11_Msk = 0xffffffff + + // SPI_W12: the data inside the buffer of the SPI module, byte 12 + // Position of SPI_W12 field. + SPI1_SPI_W12_SPI_W12_Pos = 0x0 + // Bit mask of SPI_W12 field. + SPI1_SPI_W12_SPI_W12_Msk = 0xffffffff + + // SPI_W13: the data inside the buffer of the SPI module, byte 13 + // Position of SPI_W13 field. + SPI1_SPI_W13_SPI_W13_Pos = 0x0 + // Bit mask of SPI_W13 field. + SPI1_SPI_W13_SPI_W13_Msk = 0xffffffff + + // SPI_W14: the data inside the buffer of the SPI module, byte 14 + // Position of SPI_W14 field. + SPI1_SPI_W14_SPI_W14_Pos = 0x0 + // Bit mask of SPI_W14 field. + SPI1_SPI_W14_SPI_W14_Msk = 0xffffffff + + // SPI_W15: the data inside the buffer of the SPI module, byte 15 + // Position of SPI_W15 field. + SPI1_SPI_W15_SPI_W15_Pos = 0x0 + // Bit mask of SPI_W15 field. + SPI1_SPI_W15_SPI_W15_Msk = 0xffffffff +) + +// Constants for TIMER +const ( + // FRC1_LOAD: the load value into the counter + // Position of FRC1_LOAD_VALUE field. + TIMER_FRC1_LOAD_FRC1_LOAD_VALUE_Pos = 0x0 + // Bit mask of FRC1_LOAD_VALUE field. + TIMER_FRC1_LOAD_FRC1_LOAD_VALUE_Msk = 0x7fffff + + // FRC1_COUNT: the current value of the counter. It is a decreasingcounter. + // Position of FRC1_COUNT field. + TIMER_FRC1_COUNT_FRC1_COUNT_Pos = 0x0 + // Bit mask of FRC1_COUNT field. + TIMER_FRC1_COUNT_FRC1_COUNT_Msk = 0x7fffff + + // FRC1_CTRL: FRC1_CTRL + // Position of FRC1_INT field. + TIMER_FRC1_CTRL_FRC1_INT_Pos = 0x8 + // Bit mask of FRC1_INT field. + TIMER_FRC1_CTRL_FRC1_INT_Msk = 0x100 + // Bit FRC1_INT. + TIMER_FRC1_CTRL_FRC1_INT = 0x100 + // Position of FRC1_CTRL field. + TIMER_FRC1_CTRL_FRC1_CTRL_Pos = 0x0 + // Bit mask of FRC1_CTRL field. + TIMER_FRC1_CTRL_FRC1_CTRL_Msk = 0xff + // Position of TIMER_ENABLE field. + TIMER_FRC1_CTRL_TIMER_ENABLE_Pos = 0x7 + // Bit mask of TIMER_ENABLE field. + TIMER_FRC1_CTRL_TIMER_ENABLE_Msk = 0x80 + // Bit TIMER_ENABLE. + TIMER_FRC1_CTRL_TIMER_ENABLE = 0x80 + // Position of ROLLOVER field. + TIMER_FRC1_CTRL_ROLLOVER_Pos = 0x6 + // Bit mask of ROLLOVER field. + TIMER_FRC1_CTRL_ROLLOVER_Msk = 0x40 + // Bit ROLLOVER. + TIMER_FRC1_CTRL_ROLLOVER = 0x40 + // Position of PRESCALE_DIVIDER field. + TIMER_FRC1_CTRL_PRESCALE_DIVIDER_Pos = 0x2 + // Bit mask of PRESCALE_DIVIDER field. + TIMER_FRC1_CTRL_PRESCALE_DIVIDER_Msk = 0xc + // divided by 1 + TIMER_FRC1_CTRL_PRESCALE_DIVIDER_DEVIDED_BY_1 = 0x0 + // divided by 16 + TIMER_FRC1_CTRL_PRESCALE_DIVIDER_DEVIDED_BY_16 = 0x1 + // divided by 256 + TIMER_FRC1_CTRL_PRESCALE_DIVIDER_DEVIDED_BY_256 = 0x2 + // Position of INTERRUPT_TYPE field. + TIMER_FRC1_CTRL_INTERRUPT_TYPE_Pos = 0x0 + // Bit mask of INTERRUPT_TYPE field. + TIMER_FRC1_CTRL_INTERRUPT_TYPE_Msk = 0x1 + // Bit INTERRUPT_TYPE. + TIMER_FRC1_CTRL_INTERRUPT_TYPE = 0x1 + // edge + TIMER_FRC1_CTRL_INTERRUPT_TYPE_EDGE = 0x0 + // level + TIMER_FRC1_CTRL_INTERRUPT_TYPE_LEVEL = 0x1 + + // FRC1_INT: FRC1_INT + // Position of FRC1_INT_CLR_MASK field. + TIMER_FRC1_INT_FRC1_INT_CLR_MASK_Pos = 0x0 + // Bit mask of FRC1_INT_CLR_MASK field. + TIMER_FRC1_INT_FRC1_INT_CLR_MASK_Msk = 0x1 + // Bit FRC1_INT_CLR_MASK. + TIMER_FRC1_INT_FRC1_INT_CLR_MASK = 0x1 + + // FRC2_LOAD: the load value into the counter + // Position of FRC2_LOAD_VALUE field. + TIMER_FRC2_LOAD_FRC2_LOAD_VALUE_Pos = 0x0 + // Bit mask of FRC2_LOAD_VALUE field. + TIMER_FRC2_LOAD_FRC2_LOAD_VALUE_Msk = 0xffffffff + + // FRC2_COUNT: the current value of the counter. It is a increasingcounter. + // Position of FRC2_COUNT field. + TIMER_FRC2_COUNT_FRC2_COUNT_Pos = 0x0 + // Bit mask of FRC2_COUNT field. + TIMER_FRC2_COUNT_FRC2_COUNT_Msk = 0xffffffff + + // FRC2_CTRL: FRC2_CTRL + // Position of FRC2_INT field. + TIMER_FRC2_CTRL_FRC2_INT_Pos = 0x8 + // Bit mask of FRC2_INT field. + TIMER_FRC2_CTRL_FRC2_INT_Msk = 0x100 + // Bit FRC2_INT. + TIMER_FRC2_CTRL_FRC2_INT = 0x100 + // Position of FRC2_CTRL field. + TIMER_FRC2_CTRL_FRC2_CTRL_Pos = 0x0 + // Bit mask of FRC2_CTRL field. + TIMER_FRC2_CTRL_FRC2_CTRL_Msk = 0xff + // Position of TIMER_ENABLE field. + TIMER_FRC2_CTRL_TIMER_ENABLE_Pos = 0x7 + // Bit mask of TIMER_ENABLE field. + TIMER_FRC2_CTRL_TIMER_ENABLE_Msk = 0x80 + // Bit TIMER_ENABLE. + TIMER_FRC2_CTRL_TIMER_ENABLE = 0x80 + // Position of ROLLOVER field. + TIMER_FRC2_CTRL_ROLLOVER_Pos = 0x6 + // Bit mask of ROLLOVER field. + TIMER_FRC2_CTRL_ROLLOVER_Msk = 0x40 + // Bit ROLLOVER. + TIMER_FRC2_CTRL_ROLLOVER = 0x40 + // Position of PRESCALE_DIVIDER field. + TIMER_FRC2_CTRL_PRESCALE_DIVIDER_Pos = 0x2 + // Bit mask of PRESCALE_DIVIDER field. + TIMER_FRC2_CTRL_PRESCALE_DIVIDER_Msk = 0xc + // divided by 1 + TIMER_FRC2_CTRL_PRESCALE_DIVIDER_DEVIDED_BY_1 = 0x0 + // divided by 16 + TIMER_FRC2_CTRL_PRESCALE_DIVIDER_DEVIDED_BY_16 = 0x1 + // divided by 256 + TIMER_FRC2_CTRL_PRESCALE_DIVIDER_DEVIDED_BY_256 = 0x2 + // Position of INTERRUPT_TYPE field. + TIMER_FRC2_CTRL_INTERRUPT_TYPE_Pos = 0x0 + // Bit mask of INTERRUPT_TYPE field. + TIMER_FRC2_CTRL_INTERRUPT_TYPE_Msk = 0x1 + // Bit INTERRUPT_TYPE. + TIMER_FRC2_CTRL_INTERRUPT_TYPE = 0x1 + // edge + TIMER_FRC2_CTRL_INTERRUPT_TYPE_EDGE = 0x0 + // level + TIMER_FRC2_CTRL_INTERRUPT_TYPE_LEVEL = 0x1 + + // FRC2_INT: FRC2_INT + // Position of FRC2_INT_CLR_MASK field. + TIMER_FRC2_INT_FRC2_INT_CLR_MASK_Pos = 0x0 + // Bit mask of FRC2_INT_CLR_MASK field. + TIMER_FRC2_INT_FRC2_INT_CLR_MASK_Msk = 0x1 + // Bit FRC2_INT_CLR_MASK. + TIMER_FRC2_INT_FRC2_INT_CLR_MASK = 0x1 + + // FRC2_ALARM: the alarm value for the counter + // Position of FRC2_ALARM field. + TIMER_FRC2_ALARM_FRC2_ALARM_Pos = 0x0 + // Bit mask of FRC2_ALARM field. + TIMER_FRC2_ALARM_FRC2_ALARM_Msk = 0xffffffff +) + +// Constants for UART0 +const ( + // UART_FIFO: UART FIFO,length 128 + // Position of RXFIFO_RD_BYTE field. + UART0_UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + UART0_UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + // Position of RXFIFO_WRITE_BYTE field. + UART0_UART_FIFO_RXFIFO_WRITE_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_WRITE_BYTE field. + UART0_UART_FIFO_RXFIFO_WRITE_BYTE_Msk = 0xff + + // UART_INT_RAW: UART INTERRUPT RAW STATE + // Position of RXFIFO_TOUT_INT_RAW field. + UART0_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + UART0_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + UART0_UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of BRK_DET_INT_RAW field. + UART0_UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + UART0_UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + UART0_UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of CTS_CHG_INT_RAW field. + UART0_UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + UART0_UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + UART0_UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of DSR_CHG_INT_RAW field. + UART0_UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + UART0_UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + UART0_UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of RXFIFO_OVF_INT_RAW field. + UART0_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + UART0_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + UART0_UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of FRM_ERR_INT_RAW field. + UART0_UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + UART0_UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + UART0_UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of PARITY_ERR_INT_RAW field. + UART0_UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + UART0_UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + UART0_UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of TXFIFO_EMPTY_INT_RAW field. + UART0_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + UART0_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + UART0_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of RXFIFO_FULL_INT_RAW field. + UART0_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + UART0_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + UART0_UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + + // UART_INT_ST: UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA + // Position of RXFIFO_TOUT_INT_ST field. + UART0_UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + UART0_UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + UART0_UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of BRK_DET_INT_ST field. + UART0_UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + UART0_UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + UART0_UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of CTS_CHG_INT_ST field. + UART0_UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + UART0_UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + UART0_UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of DSR_CHG_INT_ST field. + UART0_UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + UART0_UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + UART0_UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of RXFIFO_OVF_INT_ST field. + UART0_UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + UART0_UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + UART0_UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of FRM_ERR_INT_ST field. + UART0_UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + UART0_UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + UART0_UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of PARITY_ERR_INT_ST field. + UART0_UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + UART0_UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + UART0_UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of TXFIFO_EMPTY_INT_ST field. + UART0_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + UART0_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + UART0_UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of RXFIFO_FULL_INT_ST field. + UART0_UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + UART0_UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + UART0_UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + + // UART_INT_ENA: UART INTERRUPT ENABLE REGISTER + // Position of RXFIFO_TOUT_INT_ENA field. + UART0_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + UART0_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + UART0_UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of BRK_DET_INT_ENA field. + UART0_UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + UART0_UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + UART0_UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of CTS_CHG_INT_ENA field. + UART0_UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + UART0_UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + UART0_UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of DSR_CHG_INT_ENA field. + UART0_UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + UART0_UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + UART0_UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of RXFIFO_OVF_INT_ENA field. + UART0_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + UART0_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + UART0_UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of FRM_ERR_INT_ENA field. + UART0_UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + UART0_UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + UART0_UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of PARITY_ERR_INT_ENA field. + UART0_UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + UART0_UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + UART0_UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of TXFIFO_EMPTY_INT_ENA field. + UART0_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + UART0_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + UART0_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of RXFIFO_FULL_INT_ENA field. + UART0_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + UART0_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + UART0_UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + + // UART_INT_CLR: UART INTERRUPT CLEAR REGISTER + // Position of RXFIFO_TOUT_INT_CLR field. + UART0_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + UART0_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + UART0_UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of BRK_DET_INT_CLR field. + UART0_UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + UART0_UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + UART0_UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of CTS_CHG_INT_CLR field. + UART0_UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + UART0_UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + UART0_UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of DSR_CHG_INT_CLR field. + UART0_UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + UART0_UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + UART0_UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of RXFIFO_OVF_INT_CLR field. + UART0_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + UART0_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + UART0_UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of FRM_ERR_INT_CLR field. + UART0_UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + UART0_UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + UART0_UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of PARITY_ERR_INT_CLR field. + UART0_UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + UART0_UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + UART0_UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of TXFIFO_EMPTY_INT_CLR field. + UART0_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + UART0_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + UART0_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of RXFIFO_FULL_INT_CLR field. + UART0_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + UART0_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + UART0_UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + + // UART_CLKDIV: UART CLK DIV REGISTER + // Position of UART_CLKDIV field. + UART0_UART_CLKDIV_UART_CLKDIV_Pos = 0x0 + // Bit mask of UART_CLKDIV field. + UART0_UART_CLKDIV_UART_CLKDIV_Msk = 0xfffff + + // UART_AUTOBAUD: UART BAUDRATE DETECT REGISTER + // Position of GLITCH_FILT field. + UART0_UART_AUTOBAUD_GLITCH_FILT_Pos = 0x8 + // Bit mask of GLITCH_FILT field. + UART0_UART_AUTOBAUD_GLITCH_FILT_Msk = 0xff00 + // Position of AUTOBAUD_EN field. + UART0_UART_AUTOBAUD_AUTOBAUD_EN_Pos = 0x0 + // Bit mask of AUTOBAUD_EN field. + UART0_UART_AUTOBAUD_AUTOBAUD_EN_Msk = 0x1 + // Bit AUTOBAUD_EN. + UART0_UART_AUTOBAUD_AUTOBAUD_EN = 0x1 + + // UART_STATUS: UART STATUS REGISTER + // Position of TXD field. + UART0_UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + UART0_UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + UART0_UART_STATUS_TXD = 0x80000000 + // Position of RTSN field. + UART0_UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + UART0_UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + UART0_UART_STATUS_RTSN = 0x40000000 + // Position of DTRN field. + UART0_UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + UART0_UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + UART0_UART_STATUS_DTRN = 0x20000000 + // Position of TXFIFO_CNT field. + UART0_UART_STATUS_TXFIFO_CNT_Pos = 0x10 + // Bit mask of TXFIFO_CNT field. + UART0_UART_STATUS_TXFIFO_CNT_Msk = 0xff0000 + // Position of RXD field. + UART0_UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + UART0_UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + UART0_UART_STATUS_RXD = 0x8000 + // Position of CTSN field. + UART0_UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + UART0_UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + UART0_UART_STATUS_CTSN = 0x4000 + // Position of DSRN field. + UART0_UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + UART0_UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + UART0_UART_STATUS_DSRN = 0x2000 + // Position of RXFIFO_CNT field. + UART0_UART_STATUS_RXFIFO_CNT_Pos = 0x0 + // Bit mask of RXFIFO_CNT field. + UART0_UART_STATUS_RXFIFO_CNT_Msk = 0xff + + // UART_CONF0: UART CONFIG0(UART0 and UART1) + // Position of UART_DTR_INV field. + UART0_UART_CONF0_UART_DTR_INV_Pos = 0x18 + // Bit mask of UART_DTR_INV field. + UART0_UART_CONF0_UART_DTR_INV_Msk = 0x1000000 + // Bit UART_DTR_INV. + UART0_UART_CONF0_UART_DTR_INV = 0x1000000 + // Position of UART_RTS_INV field. + UART0_UART_CONF0_UART_RTS_INV_Pos = 0x17 + // Bit mask of UART_RTS_INV field. + UART0_UART_CONF0_UART_RTS_INV_Msk = 0x800000 + // Bit UART_RTS_INV. + UART0_UART_CONF0_UART_RTS_INV = 0x800000 + // Position of UART_TXD_INV field. + UART0_UART_CONF0_UART_TXD_INV_Pos = 0x16 + // Bit mask of UART_TXD_INV field. + UART0_UART_CONF0_UART_TXD_INV_Msk = 0x400000 + // Bit UART_TXD_INV. + UART0_UART_CONF0_UART_TXD_INV = 0x400000 + // Position of UART_DSR_INV field. + UART0_UART_CONF0_UART_DSR_INV_Pos = 0x15 + // Bit mask of UART_DSR_INV field. + UART0_UART_CONF0_UART_DSR_INV_Msk = 0x200000 + // Bit UART_DSR_INV. + UART0_UART_CONF0_UART_DSR_INV = 0x200000 + // Position of UART_CTS_INV field. + UART0_UART_CONF0_UART_CTS_INV_Pos = 0x14 + // Bit mask of UART_CTS_INV field. + UART0_UART_CONF0_UART_CTS_INV_Msk = 0x100000 + // Bit UART_CTS_INV. + UART0_UART_CONF0_UART_CTS_INV = 0x100000 + // Position of UART_RXD_INV field. + UART0_UART_CONF0_UART_RXD_INV_Pos = 0x13 + // Bit mask of UART_RXD_INV field. + UART0_UART_CONF0_UART_RXD_INV_Msk = 0x80000 + // Bit UART_RXD_INV. + UART0_UART_CONF0_UART_RXD_INV = 0x80000 + // Position of TXFIFO_RST field. + UART0_UART_CONF0_TXFIFO_RST_Pos = 0x12 + // Bit mask of TXFIFO_RST field. + UART0_UART_CONF0_TXFIFO_RST_Msk = 0x40000 + // Bit TXFIFO_RST. + UART0_UART_CONF0_TXFIFO_RST = 0x40000 + // Position of RXFIFO_RST field. + UART0_UART_CONF0_RXFIFO_RST_Pos = 0x11 + // Bit mask of RXFIFO_RST field. + UART0_UART_CONF0_RXFIFO_RST_Msk = 0x20000 + // Bit RXFIFO_RST. + UART0_UART_CONF0_RXFIFO_RST = 0x20000 + // Position of TX_FLOW_EN field. + UART0_UART_CONF0_TX_FLOW_EN_Pos = 0xf + // Bit mask of TX_FLOW_EN field. + UART0_UART_CONF0_TX_FLOW_EN_Msk = 0x8000 + // Bit TX_FLOW_EN. + UART0_UART_CONF0_TX_FLOW_EN = 0x8000 + // Position of UART_LOOPBACK field. + UART0_UART_CONF0_UART_LOOPBACK_Pos = 0xe + // Bit mask of UART_LOOPBACK field. + UART0_UART_CONF0_UART_LOOPBACK_Msk = 0x4000 + // Bit UART_LOOPBACK. + UART0_UART_CONF0_UART_LOOPBACK = 0x4000 + // Position of TXD_BRK field. + UART0_UART_CONF0_TXD_BRK_Pos = 0x8 + // Bit mask of TXD_BRK field. + UART0_UART_CONF0_TXD_BRK_Msk = 0x100 + // Bit TXD_BRK. + UART0_UART_CONF0_TXD_BRK = 0x100 + // Position of SW_DTR field. + UART0_UART_CONF0_SW_DTR_Pos = 0x7 + // Bit mask of SW_DTR field. + UART0_UART_CONF0_SW_DTR_Msk = 0x80 + // Bit SW_DTR. + UART0_UART_CONF0_SW_DTR = 0x80 + // Position of SW_RTS field. + UART0_UART_CONF0_SW_RTS_Pos = 0x6 + // Bit mask of SW_RTS field. + UART0_UART_CONF0_SW_RTS_Msk = 0x40 + // Bit SW_RTS. + UART0_UART_CONF0_SW_RTS = 0x40 + // Position of STOP_BIT_NUM field. + UART0_UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + UART0_UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of BIT_NUM field. + UART0_UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + UART0_UART_CONF0_BIT_NUM_Msk = 0xc + // Position of PARITY_EN field. + UART0_UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + UART0_UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + UART0_UART_CONF0_PARITY_EN = 0x2 + // Position of PARITY field. + UART0_UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + UART0_UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + UART0_UART_CONF0_PARITY = 0x1 + + // UART_CONF1: Set this bit to enable rx time-out function + // Position of RX_TOUT_EN field. + UART0_UART_CONF1_RX_TOUT_EN_Pos = 0x1f + // Bit mask of RX_TOUT_EN field. + UART0_UART_CONF1_RX_TOUT_EN_Msk = 0x80000000 + // Bit RX_TOUT_EN. + UART0_UART_CONF1_RX_TOUT_EN = 0x80000000 + // Position of RX_TOUT_THRHD field. + UART0_UART_CONF1_RX_TOUT_THRHD_Pos = 0x18 + // Bit mask of RX_TOUT_THRHD field. + UART0_UART_CONF1_RX_TOUT_THRHD_Msk = 0x7f000000 + // Position of RX_FLOW_EN field. + UART0_UART_CONF1_RX_FLOW_EN_Pos = 0x17 + // Bit mask of RX_FLOW_EN field. + UART0_UART_CONF1_RX_FLOW_EN_Msk = 0x800000 + // Bit RX_FLOW_EN. + UART0_UART_CONF1_RX_FLOW_EN = 0x800000 + // Position of RX_FLOW_THRHD field. + UART0_UART_CONF1_RX_FLOW_THRHD_Pos = 0x10 + // Bit mask of RX_FLOW_THRHD field. + UART0_UART_CONF1_RX_FLOW_THRHD_Msk = 0x7f0000 + // Position of TXFIFO_EMPTY_THRHD field. + UART0_UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0x8 + // Bit mask of TXFIFO_EMPTY_THRHD field. + UART0_UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0x7f00 + // Position of RXFIFO_FULL_THRHD field. + UART0_UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + UART0_UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0x7f + + // UART_LOWPULSE: UART_LOWPULSE + // Position of LOWPULSE_MIN_CNT field. + UART0_UART_LOWPULSE_LOWPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of LOWPULSE_MIN_CNT field. + UART0_UART_LOWPULSE_LOWPULSE_MIN_CNT_Msk = 0xfffff + + // UART_HIGHPULSE: UART_HIGHPULSE + // Position of HIGHPULSE_MIN_CNT field. + UART0_UART_HIGHPULSE_HIGHPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of HIGHPULSE_MIN_CNT field. + UART0_UART_HIGHPULSE_HIGHPULSE_MIN_CNT_Msk = 0xfffff + + // UART_RXD_CNT: UART_RXD_CNT + // Position of RXD_EDGE_CNT field. + UART0_UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0 + // Bit mask of RXD_EDGE_CNT field. + UART0_UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff + + // UART_DATE: UART HW INFO + // Position of UART_DATE field. + UART0_UART_DATE_UART_DATE_Pos = 0x0 + // Bit mask of UART_DATE field. + UART0_UART_DATE_UART_DATE_Msk = 0xffffffff + + // UART_ID: UART_ID + // Position of UART_ID field. + UART0_UART_ID_UART_ID_Pos = 0x0 + // Bit mask of UART_ID field. + UART0_UART_ID_UART_ID_Msk = 0xffffffff +) + +// Constants for UART1 +const ( + // UART_FIFO: UART FIFO,length 128 + // Position of RXFIFO_RD_BYTE field. + UART1_UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_RD_BYTE field. + UART1_UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff + // Position of RXFIFO_WRITE_BYTE field. + UART1_UART_FIFO_RXFIFO_WRITE_BYTE_Pos = 0x0 + // Bit mask of RXFIFO_WRITE_BYTE field. + UART1_UART_FIFO_RXFIFO_WRITE_BYTE_Msk = 0xff + + // UART_INT_RAW: UART INTERRUPT RAW STATE + // Position of RXFIFO_TOUT_INT_RAW field. + UART1_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_RAW field. + UART1_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_RAW. + UART1_UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100 + // Position of BRK_DET_INT_RAW field. + UART1_UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7 + // Bit mask of BRK_DET_INT_RAW field. + UART1_UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80 + // Bit BRK_DET_INT_RAW. + UART1_UART_INT_RAW_BRK_DET_INT_RAW = 0x80 + // Position of CTS_CHG_INT_RAW field. + UART1_UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6 + // Bit mask of CTS_CHG_INT_RAW field. + UART1_UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40 + // Bit CTS_CHG_INT_RAW. + UART1_UART_INT_RAW_CTS_CHG_INT_RAW = 0x40 + // Position of DSR_CHG_INT_RAW field. + UART1_UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5 + // Bit mask of DSR_CHG_INT_RAW field. + UART1_UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20 + // Bit DSR_CHG_INT_RAW. + UART1_UART_INT_RAW_DSR_CHG_INT_RAW = 0x20 + // Position of RXFIFO_OVF_INT_RAW field. + UART1_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_RAW field. + UART1_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10 + // Bit RXFIFO_OVF_INT_RAW. + UART1_UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10 + // Position of FRM_ERR_INT_RAW field. + UART1_UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3 + // Bit mask of FRM_ERR_INT_RAW field. + UART1_UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8 + // Bit FRM_ERR_INT_RAW. + UART1_UART_INT_RAW_FRM_ERR_INT_RAW = 0x8 + // Position of PARITY_ERR_INT_RAW field. + UART1_UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_RAW field. + UART1_UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4 + // Bit PARITY_ERR_INT_RAW. + UART1_UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4 + // Position of TXFIFO_EMPTY_INT_RAW field. + UART1_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_RAW field. + UART1_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_RAW. + UART1_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2 + // Position of RXFIFO_FULL_INT_RAW field. + UART1_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_RAW field. + UART1_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1 + // Bit RXFIFO_FULL_INT_RAW. + UART1_UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1 + + // UART_INT_ST: UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA + // Position of RXFIFO_TOUT_INT_ST field. + UART1_UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ST field. + UART1_UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ST. + UART1_UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100 + // Position of BRK_DET_INT_ST field. + UART1_UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7 + // Bit mask of BRK_DET_INT_ST field. + UART1_UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80 + // Bit BRK_DET_INT_ST. + UART1_UART_INT_ST_BRK_DET_INT_ST = 0x80 + // Position of CTS_CHG_INT_ST field. + UART1_UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ST field. + UART1_UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40 + // Bit CTS_CHG_INT_ST. + UART1_UART_INT_ST_CTS_CHG_INT_ST = 0x40 + // Position of DSR_CHG_INT_ST field. + UART1_UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ST field. + UART1_UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20 + // Bit DSR_CHG_INT_ST. + UART1_UART_INT_ST_DSR_CHG_INT_ST = 0x20 + // Position of RXFIFO_OVF_INT_ST field. + UART1_UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ST field. + UART1_UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ST. + UART1_UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10 + // Position of FRM_ERR_INT_ST field. + UART1_UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ST field. + UART1_UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8 + // Bit FRM_ERR_INT_ST. + UART1_UART_INT_ST_FRM_ERR_INT_ST = 0x8 + // Position of PARITY_ERR_INT_ST field. + UART1_UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ST field. + UART1_UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4 + // Bit PARITY_ERR_INT_ST. + UART1_UART_INT_ST_PARITY_ERR_INT_ST = 0x4 + // Position of TXFIFO_EMPTY_INT_ST field. + UART1_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ST field. + UART1_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ST. + UART1_UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2 + // Position of RXFIFO_FULL_INT_ST field. + UART1_UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ST field. + UART1_UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ST. + UART1_UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1 + + // UART_INT_ENA: UART INTERRUPT ENABLE REGISTER + // Position of RXFIFO_TOUT_INT_ENA field. + UART1_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_ENA field. + UART1_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_ENA. + UART1_UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100 + // Position of BRK_DET_INT_ENA field. + UART1_UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7 + // Bit mask of BRK_DET_INT_ENA field. + UART1_UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80 + // Bit BRK_DET_INT_ENA. + UART1_UART_INT_ENA_BRK_DET_INT_ENA = 0x80 + // Position of CTS_CHG_INT_ENA field. + UART1_UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6 + // Bit mask of CTS_CHG_INT_ENA field. + UART1_UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40 + // Bit CTS_CHG_INT_ENA. + UART1_UART_INT_ENA_CTS_CHG_INT_ENA = 0x40 + // Position of DSR_CHG_INT_ENA field. + UART1_UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5 + // Bit mask of DSR_CHG_INT_ENA field. + UART1_UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20 + // Bit DSR_CHG_INT_ENA. + UART1_UART_INT_ENA_DSR_CHG_INT_ENA = 0x20 + // Position of RXFIFO_OVF_INT_ENA field. + UART1_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_ENA field. + UART1_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10 + // Bit RXFIFO_OVF_INT_ENA. + UART1_UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10 + // Position of FRM_ERR_INT_ENA field. + UART1_UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3 + // Bit mask of FRM_ERR_INT_ENA field. + UART1_UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8 + // Bit FRM_ERR_INT_ENA. + UART1_UART_INT_ENA_FRM_ERR_INT_ENA = 0x8 + // Position of PARITY_ERR_INT_ENA field. + UART1_UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_ENA field. + UART1_UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4 + // Bit PARITY_ERR_INT_ENA. + UART1_UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4 + // Position of TXFIFO_EMPTY_INT_ENA field. + UART1_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_ENA field. + UART1_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_ENA. + UART1_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2 + // Position of RXFIFO_FULL_INT_ENA field. + UART1_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_ENA field. + UART1_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1 + // Bit RXFIFO_FULL_INT_ENA. + UART1_UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1 + + // UART_INT_CLR: UART INTERRUPT CLEAR REGISTER + // Position of RXFIFO_TOUT_INT_CLR field. + UART1_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8 + // Bit mask of RXFIFO_TOUT_INT_CLR field. + UART1_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100 + // Bit RXFIFO_TOUT_INT_CLR. + UART1_UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100 + // Position of BRK_DET_INT_CLR field. + UART1_UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7 + // Bit mask of BRK_DET_INT_CLR field. + UART1_UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80 + // Bit BRK_DET_INT_CLR. + UART1_UART_INT_CLR_BRK_DET_INT_CLR = 0x80 + // Position of CTS_CHG_INT_CLR field. + UART1_UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6 + // Bit mask of CTS_CHG_INT_CLR field. + UART1_UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40 + // Bit CTS_CHG_INT_CLR. + UART1_UART_INT_CLR_CTS_CHG_INT_CLR = 0x40 + // Position of DSR_CHG_INT_CLR field. + UART1_UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5 + // Bit mask of DSR_CHG_INT_CLR field. + UART1_UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20 + // Bit DSR_CHG_INT_CLR. + UART1_UART_INT_CLR_DSR_CHG_INT_CLR = 0x20 + // Position of RXFIFO_OVF_INT_CLR field. + UART1_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4 + // Bit mask of RXFIFO_OVF_INT_CLR field. + UART1_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10 + // Bit RXFIFO_OVF_INT_CLR. + UART1_UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10 + // Position of FRM_ERR_INT_CLR field. + UART1_UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3 + // Bit mask of FRM_ERR_INT_CLR field. + UART1_UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8 + // Bit FRM_ERR_INT_CLR. + UART1_UART_INT_CLR_FRM_ERR_INT_CLR = 0x8 + // Position of PARITY_ERR_INT_CLR field. + UART1_UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2 + // Bit mask of PARITY_ERR_INT_CLR field. + UART1_UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4 + // Bit PARITY_ERR_INT_CLR. + UART1_UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4 + // Position of TXFIFO_EMPTY_INT_CLR field. + UART1_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1 + // Bit mask of TXFIFO_EMPTY_INT_CLR field. + UART1_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2 + // Bit TXFIFO_EMPTY_INT_CLR. + UART1_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2 + // Position of RXFIFO_FULL_INT_CLR field. + UART1_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0 + // Bit mask of RXFIFO_FULL_INT_CLR field. + UART1_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1 + // Bit RXFIFO_FULL_INT_CLR. + UART1_UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1 + + // UART_CLKDIV: UART CLK DIV REGISTER + // Position of UART_CLKDIV field. + UART1_UART_CLKDIV_UART_CLKDIV_Pos = 0x0 + // Bit mask of UART_CLKDIV field. + UART1_UART_CLKDIV_UART_CLKDIV_Msk = 0xfffff + + // UART_AUTOBAUD: UART BAUDRATE DETECT REGISTER + // Position of GLITCH_FILT field. + UART1_UART_AUTOBAUD_GLITCH_FILT_Pos = 0x8 + // Bit mask of GLITCH_FILT field. + UART1_UART_AUTOBAUD_GLITCH_FILT_Msk = 0xff00 + // Position of AUTOBAUD_EN field. + UART1_UART_AUTOBAUD_AUTOBAUD_EN_Pos = 0x0 + // Bit mask of AUTOBAUD_EN field. + UART1_UART_AUTOBAUD_AUTOBAUD_EN_Msk = 0x1 + // Bit AUTOBAUD_EN. + UART1_UART_AUTOBAUD_AUTOBAUD_EN = 0x1 + + // UART_STATUS: UART STATUS REGISTER + // Position of TXD field. + UART1_UART_STATUS_TXD_Pos = 0x1f + // Bit mask of TXD field. + UART1_UART_STATUS_TXD_Msk = 0x80000000 + // Bit TXD. + UART1_UART_STATUS_TXD = 0x80000000 + // Position of RTSN field. + UART1_UART_STATUS_RTSN_Pos = 0x1e + // Bit mask of RTSN field. + UART1_UART_STATUS_RTSN_Msk = 0x40000000 + // Bit RTSN. + UART1_UART_STATUS_RTSN = 0x40000000 + // Position of DTRN field. + UART1_UART_STATUS_DTRN_Pos = 0x1d + // Bit mask of DTRN field. + UART1_UART_STATUS_DTRN_Msk = 0x20000000 + // Bit DTRN. + UART1_UART_STATUS_DTRN = 0x20000000 + // Position of TXFIFO_CNT field. + UART1_UART_STATUS_TXFIFO_CNT_Pos = 0x10 + // Bit mask of TXFIFO_CNT field. + UART1_UART_STATUS_TXFIFO_CNT_Msk = 0xff0000 + // Position of RXD field. + UART1_UART_STATUS_RXD_Pos = 0xf + // Bit mask of RXD field. + UART1_UART_STATUS_RXD_Msk = 0x8000 + // Bit RXD. + UART1_UART_STATUS_RXD = 0x8000 + // Position of CTSN field. + UART1_UART_STATUS_CTSN_Pos = 0xe + // Bit mask of CTSN field. + UART1_UART_STATUS_CTSN_Msk = 0x4000 + // Bit CTSN. + UART1_UART_STATUS_CTSN = 0x4000 + // Position of DSRN field. + UART1_UART_STATUS_DSRN_Pos = 0xd + // Bit mask of DSRN field. + UART1_UART_STATUS_DSRN_Msk = 0x2000 + // Bit DSRN. + UART1_UART_STATUS_DSRN = 0x2000 + // Position of RXFIFO_CNT field. + UART1_UART_STATUS_RXFIFO_CNT_Pos = 0x0 + // Bit mask of RXFIFO_CNT field. + UART1_UART_STATUS_RXFIFO_CNT_Msk = 0xff + + // UART_CONF0: UART CONFIG0(UART0 and UART1) + // Position of UART_DTR_INV field. + UART1_UART_CONF0_UART_DTR_INV_Pos = 0x18 + // Bit mask of UART_DTR_INV field. + UART1_UART_CONF0_UART_DTR_INV_Msk = 0x1000000 + // Bit UART_DTR_INV. + UART1_UART_CONF0_UART_DTR_INV = 0x1000000 + // Position of UART_RTS_INV field. + UART1_UART_CONF0_UART_RTS_INV_Pos = 0x17 + // Bit mask of UART_RTS_INV field. + UART1_UART_CONF0_UART_RTS_INV_Msk = 0x800000 + // Bit UART_RTS_INV. + UART1_UART_CONF0_UART_RTS_INV = 0x800000 + // Position of UART_TXD_INV field. + UART1_UART_CONF0_UART_TXD_INV_Pos = 0x16 + // Bit mask of UART_TXD_INV field. + UART1_UART_CONF0_UART_TXD_INV_Msk = 0x400000 + // Bit UART_TXD_INV. + UART1_UART_CONF0_UART_TXD_INV = 0x400000 + // Position of UART_DSR_INV field. + UART1_UART_CONF0_UART_DSR_INV_Pos = 0x15 + // Bit mask of UART_DSR_INV field. + UART1_UART_CONF0_UART_DSR_INV_Msk = 0x200000 + // Bit UART_DSR_INV. + UART1_UART_CONF0_UART_DSR_INV = 0x200000 + // Position of UART_CTS_INV field. + UART1_UART_CONF0_UART_CTS_INV_Pos = 0x14 + // Bit mask of UART_CTS_INV field. + UART1_UART_CONF0_UART_CTS_INV_Msk = 0x100000 + // Bit UART_CTS_INV. + UART1_UART_CONF0_UART_CTS_INV = 0x100000 + // Position of UART_RXD_INV field. + UART1_UART_CONF0_UART_RXD_INV_Pos = 0x13 + // Bit mask of UART_RXD_INV field. + UART1_UART_CONF0_UART_RXD_INV_Msk = 0x80000 + // Bit UART_RXD_INV. + UART1_UART_CONF0_UART_RXD_INV = 0x80000 + // Position of TXFIFO_RST field. + UART1_UART_CONF0_TXFIFO_RST_Pos = 0x12 + // Bit mask of TXFIFO_RST field. + UART1_UART_CONF0_TXFIFO_RST_Msk = 0x40000 + // Bit TXFIFO_RST. + UART1_UART_CONF0_TXFIFO_RST = 0x40000 + // Position of RXFIFO_RST field. + UART1_UART_CONF0_RXFIFO_RST_Pos = 0x11 + // Bit mask of RXFIFO_RST field. + UART1_UART_CONF0_RXFIFO_RST_Msk = 0x20000 + // Bit RXFIFO_RST. + UART1_UART_CONF0_RXFIFO_RST = 0x20000 + // Position of TX_FLOW_EN field. + UART1_UART_CONF0_TX_FLOW_EN_Pos = 0xf + // Bit mask of TX_FLOW_EN field. + UART1_UART_CONF0_TX_FLOW_EN_Msk = 0x8000 + // Bit TX_FLOW_EN. + UART1_UART_CONF0_TX_FLOW_EN = 0x8000 + // Position of UART_LOOPBACK field. + UART1_UART_CONF0_UART_LOOPBACK_Pos = 0xe + // Bit mask of UART_LOOPBACK field. + UART1_UART_CONF0_UART_LOOPBACK_Msk = 0x4000 + // Bit UART_LOOPBACK. + UART1_UART_CONF0_UART_LOOPBACK = 0x4000 + // Position of TXD_BRK field. + UART1_UART_CONF0_TXD_BRK_Pos = 0x8 + // Bit mask of TXD_BRK field. + UART1_UART_CONF0_TXD_BRK_Msk = 0x100 + // Bit TXD_BRK. + UART1_UART_CONF0_TXD_BRK = 0x100 + // Position of SW_DTR field. + UART1_UART_CONF0_SW_DTR_Pos = 0x7 + // Bit mask of SW_DTR field. + UART1_UART_CONF0_SW_DTR_Msk = 0x80 + // Bit SW_DTR. + UART1_UART_CONF0_SW_DTR = 0x80 + // Position of SW_RTS field. + UART1_UART_CONF0_SW_RTS_Pos = 0x6 + // Bit mask of SW_RTS field. + UART1_UART_CONF0_SW_RTS_Msk = 0x40 + // Bit SW_RTS. + UART1_UART_CONF0_SW_RTS = 0x40 + // Position of STOP_BIT_NUM field. + UART1_UART_CONF0_STOP_BIT_NUM_Pos = 0x4 + // Bit mask of STOP_BIT_NUM field. + UART1_UART_CONF0_STOP_BIT_NUM_Msk = 0x30 + // Position of BIT_NUM field. + UART1_UART_CONF0_BIT_NUM_Pos = 0x2 + // Bit mask of BIT_NUM field. + UART1_UART_CONF0_BIT_NUM_Msk = 0xc + // Position of PARITY_EN field. + UART1_UART_CONF0_PARITY_EN_Pos = 0x1 + // Bit mask of PARITY_EN field. + UART1_UART_CONF0_PARITY_EN_Msk = 0x2 + // Bit PARITY_EN. + UART1_UART_CONF0_PARITY_EN = 0x2 + // Position of PARITY field. + UART1_UART_CONF0_PARITY_Pos = 0x0 + // Bit mask of PARITY field. + UART1_UART_CONF0_PARITY_Msk = 0x1 + // Bit PARITY. + UART1_UART_CONF0_PARITY = 0x1 + + // UART_CONF1: Set this bit to enable rx time-out function + // Position of RX_TOUT_EN field. + UART1_UART_CONF1_RX_TOUT_EN_Pos = 0x1f + // Bit mask of RX_TOUT_EN field. + UART1_UART_CONF1_RX_TOUT_EN_Msk = 0x80000000 + // Bit RX_TOUT_EN. + UART1_UART_CONF1_RX_TOUT_EN = 0x80000000 + // Position of RX_TOUT_THRHD field. + UART1_UART_CONF1_RX_TOUT_THRHD_Pos = 0x18 + // Bit mask of RX_TOUT_THRHD field. + UART1_UART_CONF1_RX_TOUT_THRHD_Msk = 0x7f000000 + // Position of RX_FLOW_EN field. + UART1_UART_CONF1_RX_FLOW_EN_Pos = 0x17 + // Bit mask of RX_FLOW_EN field. + UART1_UART_CONF1_RX_FLOW_EN_Msk = 0x800000 + // Bit RX_FLOW_EN. + UART1_UART_CONF1_RX_FLOW_EN = 0x800000 + // Position of RX_FLOW_THRHD field. + UART1_UART_CONF1_RX_FLOW_THRHD_Pos = 0x10 + // Bit mask of RX_FLOW_THRHD field. + UART1_UART_CONF1_RX_FLOW_THRHD_Msk = 0x7f0000 + // Position of TXFIFO_EMPTY_THRHD field. + UART1_UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0x8 + // Bit mask of TXFIFO_EMPTY_THRHD field. + UART1_UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0x7f00 + // Position of RXFIFO_FULL_THRHD field. + UART1_UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0 + // Bit mask of RXFIFO_FULL_THRHD field. + UART1_UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0x7f + + // UART_LOWPULSE: UART_LOWPULSE + // Position of LOWPULSE_MIN_CNT field. + UART1_UART_LOWPULSE_LOWPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of LOWPULSE_MIN_CNT field. + UART1_UART_LOWPULSE_LOWPULSE_MIN_CNT_Msk = 0xfffff + + // UART_HIGHPULSE: UART_HIGHPULSE + // Position of HIGHPULSE_MIN_CNT field. + UART1_UART_HIGHPULSE_HIGHPULSE_MIN_CNT_Pos = 0x0 + // Bit mask of HIGHPULSE_MIN_CNT field. + UART1_UART_HIGHPULSE_HIGHPULSE_MIN_CNT_Msk = 0xfffff + + // UART_RXD_CNT: UART_RXD_CNT + // Position of RXD_EDGE_CNT field. + UART1_UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0 + // Bit mask of RXD_EDGE_CNT field. + UART1_UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff + + // UART_DATE: UART HW INFO + // Position of UART_DATE field. + UART1_UART_DATE_UART_DATE_Pos = 0x0 + // Bit mask of UART_DATE field. + UART1_UART_DATE_UART_DATE_Msk = 0xffffffff + + // UART_ID: UART_ID + // Position of UART_ID field. + UART1_UART_ID_UART_ID_Pos = 0x0 + // Bit mask of UART_ID field. + UART1_UART_ID_UART_ID_Msk = 0xffffffff +) + +// Constants for WDT +const ( + // WDT_CTL: WDT_CTL + // Position of Register field. + WDT_WDT_CTL_Register_Pos = 0x0 + // Bit mask of Register field. + WDT_WDT_CTL_Register_Msk = 0xffffffff + + // WDT_OP: WDT_OP + // Position of Register field. + WDT_WDT_OP_Register_Pos = 0x0 + // Bit mask of Register field. + WDT_WDT_OP_Register_Msk = 0xffffffff + + // WDT_OP_ND: WDT_OP_ND + // Position of Register field. + WDT_WDT_OP_ND_Register_Pos = 0x0 + // Bit mask of Register field. + WDT_WDT_OP_ND_Register_Msk = 0xffffffff + + // WDT_RST: WDT_RST + // Position of Register field. + WDT_WDT_RST_Register_Pos = 0x0 + // Bit mask of Register field. + WDT_WDT_RST_Register_Msk = 0xffffffff +) + +// Constants for RNG: RNG register +const () + +// Constants for WATCHDOG: Watchdog registers +const ( + // CTL: Watchdog control + // Position of ENABLE field. + WATCHDOG_CTL_ENABLE_Pos = 0x0 + // Bit mask of ENABLE field. + WATCHDOG_CTL_ENABLE_Msk = 0x1 + // Bit ENABLE. + WATCHDOG_CTL_ENABLE = 0x1 + // Position of STAGE_1_NO_RESET field. + WATCHDOG_CTL_STAGE_1_NO_RESET_Pos = 0x1 + // Bit mask of STAGE_1_NO_RESET field. + WATCHDOG_CTL_STAGE_1_NO_RESET_Msk = 0x2 + // Bit STAGE_1_NO_RESET. + WATCHDOG_CTL_STAGE_1_NO_RESET = 0x2 + // Position of STAGE_1_DISABLE field. + WATCHDOG_CTL_STAGE_1_DISABLE_Pos = 0x2 + // Bit mask of STAGE_1_DISABLE field. + WATCHDOG_CTL_STAGE_1_DISABLE_Msk = 0x4 + // Bit STAGE_1_DISABLE. + WATCHDOG_CTL_STAGE_1_DISABLE = 0x4 + // Position of UNKNOWN_3 field. + WATCHDOG_CTL_UNKNOWN_3_Pos = 0x3 + // Bit mask of UNKNOWN_3 field. + WATCHDOG_CTL_UNKNOWN_3_Msk = 0x8 + // Bit UNKNOWN_3. + WATCHDOG_CTL_UNKNOWN_3 = 0x8 + // Position of UNKNOWN_4 field. + WATCHDOG_CTL_UNKNOWN_4_Pos = 0x4 + // Bit mask of UNKNOWN_4 field. + WATCHDOG_CTL_UNKNOWN_4_Msk = 0x10 + // Bit UNKNOWN_4. + WATCHDOG_CTL_UNKNOWN_4 = 0x10 + // Position of UNKNOWN_5 field. + WATCHDOG_CTL_UNKNOWN_5_Pos = 0x5 + // Bit mask of UNKNOWN_5 field. + WATCHDOG_CTL_UNKNOWN_5_Msk = 0x20 + // Bit UNKNOWN_5. + WATCHDOG_CTL_UNKNOWN_5 = 0x20 +) diff --git a/emb/device/riscv/csr.go b/emb/device/riscv/csr.go new file mode 100644 index 0000000..52e97a2 --- /dev/null +++ b/emb/device/riscv/csr.go @@ -0,0 +1,335 @@ +package riscv + +// This file lists constants for CSR operations and defines methods on CSRs that +// are implemented as compiler intrinsics. + +// CSR constants are used for use in CSR (Control and Status Register) compiler +// intrinsics. +type CSR int16 + +// Get returns the value of the given CSR. +func (csr CSR) Get() uintptr + +// Set stores a new value in the given CSR. +func (csr CSR) Set(uintptr) + +// SetBits atomically sets the given bits in this ISR and returns the old value. +func (csr CSR) SetBits(uintptr) uintptr + +// ClearBits atomically clears the given bits in this ISR and returns the old +// value. +func (csr CSR) ClearBits(uintptr) uintptr + +// CSR values defined in the RISC-V privileged specification. Not all values may +// be available on any given chip. +// +// Source: https://github.com/riscv/riscv-isa-manual/blob/riscv-priv-1.10/src/priv-csrs.tex +const ( + // User Trap Setup + USTATUS CSR = 0x000 // User status register. + UIE CSR = 0x004 // User interrupt-enable register. + UTVEC CSR = 0x005 // User trap handler base address. + + // User Trap Handling + USCRATCH CSR = 0x040 // Scratch register for user trap handlers. + UEPC CSR = 0x041 // User exception program counter. + UCAUSE CSR = 0x042 // User trap cause. + UTVAL CSR = 0x043 // User bad address or instruction. + UIP CSR = 0x044 // User interrupt pending. + + // User Floating-Point CSRs + FFLAGS CSR = 0x001 // Floating-Point Accrued Exceptions. + FRM CSR = 0x002 // Floating-Point Dynamic Rounding Mode. + FCSR CSR = 0x003 // Floating-Point Control and Status + + // User Counter/Timers + CYCLE CSR = 0xC00 // Cycle counter for RDCYCLE instruction. + TIME CSR = 0xC01 // Timer for RDTIME instruction. + INSTRET CSR = 0xC02 // Instructions-retired counter for RDINSTRET instruction. + HPMCOUNTER3 CSR = 0xC03 // Performance-monitoring counter 3. + HPMCOUNTER4 CSR = 0xC04 // Performance-monitoring counter 4. + HPMCOUNTER5 CSR = 0xC05 // Performance-monitoring counter 5. + HPMCOUNTER6 CSR = 0xC06 // Performance-monitoring counter 6. + HPMCOUNTER7 CSR = 0xC07 // Performance-monitoring counter 7. + HPMCOUNTER8 CSR = 0xC08 // Performance-monitoring counter 8. + HPMCOUNTER9 CSR = 0xC09 // Performance-monitoring counter 9. + HPMCOUNTER10 CSR = 0xC0A // Performance-monitoring counter 10. + HPMCOUNTER11 CSR = 0xC0B // Performance-monitoring counter 11. + HPMCOUNTER12 CSR = 0xC0C // Performance-monitoring counter 12. + HPMCOUNTER13 CSR = 0xC0D // Performance-monitoring counter 13. + HPMCOUNTER14 CSR = 0xC0E // Performance-monitoring counter 14. + HPMCOUNTER15 CSR = 0xC0F // Performance-monitoring counter 15. + HPMCOUNTER16 CSR = 0xC10 // Performance-monitoring counter 16. + HPMCOUNTER17 CSR = 0xC11 // Performance-monitoring counter 17. + HPMCOUNTER18 CSR = 0xC12 // Performance-monitoring counter 18. + HPMCOUNTER19 CSR = 0xC13 // Performance-monitoring counter 19. + HPMCOUNTER20 CSR = 0xC14 // Performance-monitoring counter 20. + HPMCOUNTER21 CSR = 0xC15 // Performance-monitoring counter 21. + HPMCOUNTER22 CSR = 0xC16 // Performance-monitoring counter 22. + HPMCOUNTER23 CSR = 0xC17 // Performance-monitoring counter 23. + HPMCOUNTER24 CSR = 0xC18 // Performance-monitoring counter 24. + HPMCOUNTER25 CSR = 0xC19 // Performance-monitoring counter 25. + HPMCOUNTER26 CSR = 0xC1A // Performance-monitoring counter 26. + HPMCOUNTER27 CSR = 0xC1B // Performance-monitoring counter 27. + HPMCOUNTER28 CSR = 0xC1C // Performance-monitoring counter 28. + HPMCOUNTER29 CSR = 0xC1D // Performance-monitoring counter 29. + HPMCOUNTER30 CSR = 0xC1E // Performance-monitoring counter 30. + HPMCOUNTER31 CSR = 0xC1F // Performance-monitoring counter 31. + CYCLEH CSR = 0xC80 // Upper 32 bits of CYCLE, RV32I only. + TIMEH CSR = 0xC81 // Upper 32 bits of TIME, RV32I only. + INSTRETH CSR = 0xC82 // Upper 32 bits of INSTRET, RV32I only. + HPMCOUNTER3H CSR = 0xC83 // Upper 32 bits of HPMCOUNTER3, RV32I only. + HPMCOUNTER4H CSR = 0xC84 // Upper 32 bits of HPMCOUNTER4, RV32I only. + HPMCOUNTER5H CSR = 0xC85 // Upper 32 bits of HPMCOUNTER5, RV32I only. + HPMCOUNTER6H CSR = 0xC86 // Upper 32 bits of HPMCOUNTER6, RV32I only. + HPMCOUNTER7H CSR = 0xC87 // Upper 32 bits of HPMCOUNTER7, RV32I only. + HPMCOUNTER8H CSR = 0xC88 // Upper 32 bits of HPMCOUNTER8, RV32I only. + HPMCOUNTER9H CSR = 0xC89 // Upper 32 bits of HPMCOUNTER9, RV32I only. + HPMCOUNTER10H CSR = 0xC8A // Upper 32 bits of HPMCOUNTER10, RV32I only. + HPMCOUNTER11H CSR = 0xC8B // Upper 32 bits of HPMCOUNTER11, RV32I only. + HPMCOUNTER12H CSR = 0xC8C // Upper 32 bits of HPMCOUNTER12, RV32I only. + HPMCOUNTER13H CSR = 0xC8D // Upper 32 bits of HPMCOUNTER13, RV32I only. + HPMCOUNTER14H CSR = 0xC8E // Upper 32 bits of HPMCOUNTER14, RV32I only. + HPMCOUNTER15H CSR = 0xC8F // Upper 32 bits of HPMCOUNTER15, RV32I only. + HPMCOUNTER16H CSR = 0xC90 // Upper 32 bits of HPMCOUNTER16, RV32I only. + HPMCOUNTER17H CSR = 0xC91 // Upper 32 bits of HPMCOUNTER17, RV32I only. + HPMCOUNTER18H CSR = 0xC92 // Upper 32 bits of HPMCOUNTER18, RV32I only. + HPMCOUNTER19H CSR = 0xC93 // Upper 32 bits of HPMCOUNTER19, RV32I only. + HPMCOUNTER20H CSR = 0xC94 // Upper 32 bits of HPMCOUNTER20, RV32I only. + HPMCOUNTER21H CSR = 0xC95 // Upper 32 bits of HPMCOUNTER21, RV32I only. + HPMCOUNTER22H CSR = 0xC96 // Upper 32 bits of HPMCOUNTER22, RV32I only. + HPMCOUNTER23H CSR = 0xC97 // Upper 32 bits of HPMCOUNTER23, RV32I only. + HPMCOUNTER24H CSR = 0xC98 // Upper 32 bits of HPMCOUNTER24, RV32I only. + HPMCOUNTER25H CSR = 0xC99 // Upper 32 bits of HPMCOUNTER25, RV32I only. + HPMCOUNTER26H CSR = 0xC9A // Upper 32 bits of HPMCOUNTER26, RV32I only. + HPMCOUNTER27H CSR = 0xC9B // Upper 32 bits of HPMCOUNTER27, RV32I only. + HPMCOUNTER28H CSR = 0xC9C // Upper 32 bits of HPMCOUNTER28, RV32I only. + HPMCOUNTER29H CSR = 0xC9D // Upper 32 bits of HPMCOUNTER29, RV32I only. + HPMCOUNTER30H CSR = 0xC9E // Upper 32 bits of HPMCOUNTER30, RV32I only. + HPMCOUNTER31H CSR = 0xC9F // Upper 32 bits of HPMCOUNTER31, RV32I only. + + // Supervisor Trap Setup + SSTATUS CSR = 0x100 // Supervisor status register. + SEDELEG CSR = 0x102 // Supervisor exception delegation register. + SIDELEG CSR = 0x103 // Supervisor interrupt delegation register. + SIE CSR = 0x104 // Supervisor interrupt-enable register. + STVEC CSR = 0x105 // Supervisor trap handler base address. + SCOUNTEREN CSR = 0x106 // Supervisor counter enable. + + // Supervisor Trap Handling + SSCRATCH CSR = 0x140 // Scratch register for supervisor trap handlers. + SEPC CSR = 0x141 // Supervisor exception program counter. + SCAUSE CSR = 0x142 // Supervisor trap cause. + STVAL CSR = 0x143 // Supervisor bad address or instruction. + SIP CSR = 0x144 // Supervisor interrupt pending. + + // Supervisor Protection and Translation + SATP CSR = 0x180 // Supervisor address translation and protection. + + // Machine Information Registers + MVENDORID CSR = 0xF11 // Vendor ID. + MARCHID CSR = 0xF12 // Architecture ID. + MIMPID CSR = 0xF13 // Implementation ID. + MHARTID CSR = 0xF14 // Hardware thread ID. + + // Machine Trap Setup + MSTATUS CSR = 0x300 // Machine status register. + MISA CSR = 0x301 // ISA and extensions + MEDELEG CSR = 0x302 // Machine exception delegation register. + MIDELEG CSR = 0x303 // Machine interrupt delegation register. + MIE CSR = 0x304 // Machine interrupt-enable register. + MTVEC CSR = 0x305 // Machine trap-handler base address. + MCOUNTEREN CSR = 0x306 // Machine counter enable. + + // Machine Trap Handling + MSCRATCH CSR = 0x340 // Scratch register for machine trap handlers. + MEPC CSR = 0x341 // Machine exception program counter. + MCAUSE CSR = 0x342 // Machine trap cause. + MTVAL CSR = 0x343 // Machine bad address or instruction. + MIP CSR = 0x344 // Machine interrupt pending. + + // Machine Protection and Translation + PMPCFG0 CSR = 0x3A0 // Physical memory protection configuration. + PMPCFG1 CSR = 0x3A1 // Physical memory protection configuration, RV32 only. + PMPCFG2 CSR = 0x3A2 // Physical memory protection configuration. + PMPCFG3 CSR = 0x3A3 // Physical memory protection configuration, RV32 only. + PMPADDR0 CSR = 0x3B0 // Physical memory protection address register 0. + PMPADDR1 CSR = 0x3B1 // Physical memory protection address register 1. + PMPADDR2 CSR = 0x3B2 // Physical memory protection address register 2. + PMPADDR3 CSR = 0x3B3 // Physical memory protection address register 3. + PMPADDR4 CSR = 0x3B4 // Physical memory protection address register 4. + PMPADDR5 CSR = 0x3B5 // Physical memory protection address register 5. + PMPADDR6 CSR = 0x3B6 // Physical memory protection address register 6. + PMPADDR7 CSR = 0x3B7 // Physical memory protection address register 7. + PMPADDR8 CSR = 0x3B8 // Physical memory protection address register 8. + PMPADDR9 CSR = 0x3B9 // Physical memory protection address register 9. + PMPADDR10 CSR = 0x3BA // Physical memory protection address register 10. + PMPADDR11 CSR = 0x3BB // Physical memory protection address register 11. + PMPADDR12 CSR = 0x3BC // Physical memory protection address register 12. + PMPADDR13 CSR = 0x3BD // Physical memory protection address register 13. + PMPADDR14 CSR = 0x3BE // Physical memory protection address register 14. + PMPADDR15 CSR = 0x3BF // Physical memory protection address register 15. + + // Machine Counter/Timers + mcycle CSR = 0xB00 // Machine cycle counter. + minstret CSR = 0xB02 // Machine instructions-retired counter. + MHPMCOUNTER3 CSR = 0xB03 // Machine performance-monitoring counter 3. + MHPMCOUNTER4 CSR = 0xB04 // Machine performance-monitoring counter 4. + MHPMCOUNTER5 CSR = 0xB05 // Machine performance-monitoring counter 5. + MHPMCOUNTER6 CSR = 0xB06 // Machine performance-monitoring counter 6. + MHPMCOUNTER7 CSR = 0xB07 // Machine performance-monitoring counter 7. + MHPMCOUNTER8 CSR = 0xB08 // Machine performance-monitoring counter 8. + MHPMCOUNTER9 CSR = 0xB09 // Machine performance-monitoring counter 9. + MHPMCOUNTER10 CSR = 0xB0A // Machine performance-monitoring counter 10. + MHPMCOUNTER11 CSR = 0xB0B // Machine performance-monitoring counter 11. + MHPMCOUNTER12 CSR = 0xB0C // Machine performance-monitoring counter 12. + MHPMCOUNTER13 CSR = 0xB0D // Machine performance-monitoring counter 13. + MHPMCOUNTER14 CSR = 0xB0E // Machine performance-monitoring counter 14. + MHPMCOUNTER15 CSR = 0xB0F // Machine performance-monitoring counter 15. + MHPMCOUNTER16 CSR = 0xB10 // Machine performance-monitoring counter 16. + MHPMCOUNTER17 CSR = 0xB11 // Machine performance-monitoring counter 17. + MHPMCOUNTER18 CSR = 0xB12 // Machine performance-monitoring counter 18. + MHPMCOUNTER19 CSR = 0xB13 // Machine performance-monitoring counter 19. + MHPMCOUNTER20 CSR = 0xB14 // Machine performance-monitoring counter 20. + MHPMCOUNTER21 CSR = 0xB15 // Machine performance-monitoring counter 21. + MHPMCOUNTER22 CSR = 0xB16 // Machine performance-monitoring counter 22. + MHPMCOUNTER23 CSR = 0xB17 // Machine performance-monitoring counter 23. + MHPMCOUNTER24 CSR = 0xB18 // Machine performance-monitoring counter 24. + MHPMCOUNTER25 CSR = 0xB19 // Machine performance-monitoring counter 25. + MHPMCOUNTER26 CSR = 0xB1A // Machine performance-monitoring counter 26. + MHPMCOUNTER27 CSR = 0xB1B // Machine performance-monitoring counter 27. + MHPMCOUNTER28 CSR = 0xB1C // Machine performance-monitoring counter 28. + MHPMCOUNTER29 CSR = 0xB1D // Machine performance-monitoring counter 29. + MHPMCOUNTER30 CSR = 0xB1E // Machine performance-monitoring counter 30. + MHPMCOUNTER31 CSR = 0xB1F // Machine performance-monitoring counter 31. + MCYCLEH CSR = 0xB80 // Upper 32 bits of MCYCLE, RV32I only. + MINSTRETH CSR = 0xB82 // Upper 32 bits of MINSTRET, RV32I only. + MHPMCOUNTER3H CSR = 0xB83 // Upper 32 bits of MHPMCOUNTER3, RV32I only. + MHPMCOUNTER4H CSR = 0xB84 // Upper 32 bits of MHPMCOUNTER4, RV32I only. + MHPMCOUNTER5H CSR = 0xB85 // Upper 32 bits of MHPMCOUNTER5, RV32I only. + MHPMCOUNTER6H CSR = 0xB86 // Upper 32 bits of MHPMCOUNTER6, RV32I only. + MHPMCOUNTER7H CSR = 0xB87 // Upper 32 bits of MHPMCOUNTER7, RV32I only. + MHPMCOUNTER8H CSR = 0xB88 // Upper 32 bits of MHPMCOUNTER8, RV32I only. + MHPMCOUNTER9H CSR = 0xB89 // Upper 32 bits of MHPMCOUNTER9, RV32I only. + MHPMCOUNTER10H CSR = 0xB8A // Upper 32 bits of MHPMCOUNTER10, RV32I only. + MHPMCOUNTER11H CSR = 0xB8B // Upper 32 bits of MHPMCOUNTER11, RV32I only. + MHPMCOUNTER12H CSR = 0xB8C // Upper 32 bits of MHPMCOUNTER12, RV32I only. + MHPMCOUNTER13H CSR = 0xB8D // Upper 32 bits of MHPMCOUNTER13, RV32I only. + MHPMCOUNTER14H CSR = 0xB8E // Upper 32 bits of MHPMCOUNTER14, RV32I only. + MHPMCOUNTER15H CSR = 0xB8F // Upper 32 bits of MHPMCOUNTER15, RV32I only. + MHPMCOUNTER16H CSR = 0xB90 // Upper 32 bits of MHPMCOUNTER16, RV32I only. + MHPMCOUNTER17H CSR = 0xB91 // Upper 32 bits of MHPMCOUNTER17, RV32I only. + MHPMCOUNTER18H CSR = 0xB92 // Upper 32 bits of MHPMCOUNTER18, RV32I only. + MHPMCOUNTER19H CSR = 0xB93 // Upper 32 bits of MHPMCOUNTER19, RV32I only. + MHPMCOUNTER20H CSR = 0xB94 // Upper 32 bits of MHPMCOUNTER20, RV32I only. + MHPMCOUNTER21H CSR = 0xB95 // Upper 32 bits of MHPMCOUNTER21, RV32I only. + MHPMCOUNTER22H CSR = 0xB96 // Upper 32 bits of MHPMCOUNTER22, RV32I only. + MHPMCOUNTER23H CSR = 0xB97 // Upper 32 bits of MHPMCOUNTER23, RV32I only. + MHPMCOUNTER24H CSR = 0xB98 // Upper 32 bits of MHPMCOUNTER24, RV32I only. + MHPMCOUNTER25H CSR = 0xB99 // Upper 32 bits of MHPMCOUNTER25, RV32I only. + MHPMCOUNTER26H CSR = 0xB9A // Upper 32 bits of MHPMCOUNTER26, RV32I only. + MHPMCOUNTER27H CSR = 0xB9B // Upper 32 bits of MHPMCOUNTER27, RV32I only. + MHPMCOUNTER28H CSR = 0xB9C // Upper 32 bits of MHPMCOUNTER28, RV32I only. + MHPMCOUNTER29H CSR = 0xB9D // Upper 32 bits of MHPMCOUNTER29, RV32I only. + MHPMCOUNTER30H CSR = 0xB9E // Upper 32 bits of MHPMCOUNTER30, RV32I only. + MHPMCOUNTER31H CSR = 0xB9F // Upper 32 bits of MHPMCOUNTER31, RV32I only. + + // Machine Counter Setup + MHPMEVENT4 CSR = 0x324 // Machine performance-monitoring event selector 4. + MHPMEVENT5 CSR = 0x325 // Machine performance-monitoring event selector 5. + MHPMEVENT6 CSR = 0x326 // Machine performance-monitoring event selector 6. + MHPMEVENT7 CSR = 0x327 // Machine performance-monitoring event selector 7. + MHPMEVENT8 CSR = 0x328 // Machine performance-monitoring event selector 8. + MHPMEVENT9 CSR = 0x329 // Machine performance-monitoring event selector 9. + MHPMEVENT10 CSR = 0x32A // Machine performance-monitoring event selector 10. + MHPMEVENT11 CSR = 0x32B // Machine performance-monitoring event selector 11. + MHPMEVENT12 CSR = 0x32C // Machine performance-monitoring event selector 12. + MHPMEVENT13 CSR = 0x32D // Machine performance-monitoring event selector 13. + MHPMEVENT14 CSR = 0x32E // Machine performance-monitoring event selector 14. + MHPMEVENT15 CSR = 0x32F // Machine performance-monitoring event selector 15. + MHPMEVENT16 CSR = 0x330 // Machine performance-monitoring event selector 16. + MHPMEVENT17 CSR = 0x331 // Machine performance-monitoring event selector 17. + MHPMEVENT18 CSR = 0x332 // Machine performance-monitoring event selector 18. + MHPMEVENT19 CSR = 0x333 // Machine performance-monitoring event selector 19. + MHPMEVENT20 CSR = 0x334 // Machine performance-monitoring event selector 20. + MHPMEVENT21 CSR = 0x335 // Machine performance-monitoring event selector 21. + MHPMEVENT22 CSR = 0x336 // Machine performance-monitoring event selector 22. + MHPMEVENT23 CSR = 0x337 // Machine performance-monitoring event selector 23. + MHPMEVENT24 CSR = 0x338 // Machine performance-monitoring event selector 24. + MHPMEVENT25 CSR = 0x339 // Machine performance-monitoring event selector 25. + MHPMEVENT26 CSR = 0x33A // Machine performance-monitoring event selector 26. + MHPMEVENT27 CSR = 0x33B // Machine performance-monitoring event selector 27. + MHPMEVENT28 CSR = 0x33C // Machine performance-monitoring event selector 28. + MHPMEVENT29 CSR = 0x33D // Machine performance-monitoring event selector 29. + MHPMEVENT30 CSR = 0x33E // Machine performance-monitoring event selector 30. + MHPMEVENT31 CSR = 0x33F // Machine performance-monitoring event selector 31. + + // Debug/Trace Registers (shared with Debug Mode) + TSELECT CSR = 0x7A0 // Debug/Trace trigger register select. + TDATA1 CSR = 0x7A1 // First Debug/Trace trigger data register. + TDATA2 CSR = 0x7A2 // Second Debug/Trace trigger data register. + TDATA3 CSR = 0x7A3 // Third Debug/Trace trigger data register. + + // Debug Mode Registers + DCSR CSR = 0x7B0 // Debug control and status register. + DPC CSR = 0x7B1 // Debug PC. + DSCRATCH CSR = 0x7B2 // Debug scratch register. +) + +// Bitfields for the CSR registers above. +const ( + // MSTATUS (common bits between RV32 and RV64) + MSTATUS_SIE = 1 << 1 + MSTATUS_MIE = 1 << 3 + MSTATUS_SPIE = 1 << 5 + MSTATUS_UBE = 1 << 6 + MSTATUS_MPIE = 1 << 7 + MSTATUS_SPP = 1 << 8 + MSTATUS_MPRV = 1 << 17 + MSTATUS_SUM = 1 << 18 + MSTATUS_MXR = 1 << 19 + MSTATUS_TVM = 1 << 20 + MSTATUS_TW = 1 << 21 + MSTATUS_TSR = 1 << 22 + + MIE_SSIE = 1 << 1 + MIE_MSIE = 1 << 3 + MIE_STIE = 1 << 5 + MIE_MTIE = 1 << 7 + MIE_SEIE = 1 << 9 + MIE_MEIE = 1 << 11 + + MIP_SSIP = 1 << 1 + MIP_MSIP = 1 << 3 + MIP_STIP = 1 << 5 + MIP_MTIP = 1 << 7 + MIP_SEIP = 1 << 9 + MIP_MEIP = 1 << 11 +) + +// Interrupt constants +const ( + // MCAUSE values with the topmost bit (interrupt bit) set. + SupervisorSoftwareInterrupt = 1 + MachineSoftwareInterrupt = 3 + SupervisorTimerInterrupt = 5 + MachineTimerInterrupt = 7 + SupervisorExternalInterrupt = 9 + MachineExternalInterrupt = 11 + + // MCAUSE values with the topmost bit (interrupt bit) clear. + InstructionAddressMisaligned = 0 + InstructionAccessFault = 1 + IllegalInstruction = 2 + Breakpoint = 3 + LoadAddressMisaligned = 4 + LoadAccessFault = 5 + StoreOrAMOAddressMisaligned = 6 + StoreOrAMOAccessFault = 7 + EnvironmentCallFromUMode = 8 + EnvironmentCallFromSMode = 9 + EnvironmentCallFromMMode = 11 + InstructionPageFault = 12 + LoadPageFault = 13 + StoreOrAMOPageFault = 15 +) diff --git a/emb/device/riscv/handleinterrupt.S b/emb/device/riscv/handleinterrupt.S new file mode 100644 index 0000000..c206c01 --- /dev/null +++ b/emb/device/riscv/handleinterrupt.S @@ -0,0 +1,130 @@ +#ifdef __riscv_flen +#define NREG 48 +#define LFREG flw +#define SFREG fsw +#else +#define NREG 16 +#endif + +#if __riscv_xlen==64 +#define REGSIZE 8 +#define SREG sd +#define LREG ld +#else +#define REGSIZE 4 +#define SREG sw +#define LREG lw +#endif + +.section .text.handleInterruptASM +.global handleInterruptASM +.type handleInterruptASM,@function +handleInterruptASM: + // Save and restore all registers, because the hardware only saves/restores + // the pc. + // Note: we have to do this in assembly because the "interrupt"="machine" + // attribute is broken in LLVM: https://bugs.llvm.org/show_bug.cgi?id=42984 + addi sp, sp, -NREG*REGSIZE + SREG ra, 0*REGSIZE(sp) + SREG t0, 1*REGSIZE(sp) + SREG t1, 2*REGSIZE(sp) + SREG t2, 3*REGSIZE(sp) + SREG a0, 4*REGSIZE(sp) + SREG a1, 5*REGSIZE(sp) + SREG a2, 6*REGSIZE(sp) + SREG a3, 7*REGSIZE(sp) + SREG a4, 8*REGSIZE(sp) + SREG a5, 9*REGSIZE(sp) + SREG a6, 10*REGSIZE(sp) + SREG a7, 11*REGSIZE(sp) + SREG t3, 12*REGSIZE(sp) + SREG t4, 13*REGSIZE(sp) + SREG t5, 14*REGSIZE(sp) + SREG t6, 15*REGSIZE(sp) +#ifdef __riscv_flen + SFREG f0, (0 + 16)*REGSIZE(sp) + SFREG f1, (1 + 16)*REGSIZE(sp) + SFREG f2, (2 + 16)*REGSIZE(sp) + SFREG f3, (3 + 16)*REGSIZE(sp) + SFREG f4, (4 + 16)*REGSIZE(sp) + SFREG f5, (5 + 16)*REGSIZE(sp) + SFREG f6, (6 + 16)*REGSIZE(sp) + SFREG f7, (7 + 16)*REGSIZE(sp) + SFREG f8, (8 + 16)*REGSIZE(sp) + SFREG f9, (9 + 16)*REGSIZE(sp) + SFREG f10,(10 + 16)*REGSIZE(sp) + SFREG f11,(11 + 16)*REGSIZE(sp) + SFREG f12,(12 + 16)*REGSIZE(sp) + SFREG f13,(13 + 16)*REGSIZE(sp) + SFREG f14,(14 + 16)*REGSIZE(sp) + SFREG f15,(15 + 16)*REGSIZE(sp) + SFREG f16,(16 + 16)*REGSIZE(sp) + SFREG f17,(17 + 16)*REGSIZE(sp) + SFREG f18,(18 + 16)*REGSIZE(sp) + SFREG f19,(19 + 16)*REGSIZE(sp) + SFREG f20,(20 + 16)*REGSIZE(sp) + SFREG f21,(21 + 16)*REGSIZE(sp) + SFREG f22,(22 + 16)*REGSIZE(sp) + SFREG f23,(23 + 16)*REGSIZE(sp) + SFREG f24,(24 + 16)*REGSIZE(sp) + SFREG f25,(25 + 16)*REGSIZE(sp) + SFREG f26,(26 + 16)*REGSIZE(sp) + SFREG f27,(27 + 16)*REGSIZE(sp) + SFREG f28,(28 + 16)*REGSIZE(sp) + SFREG f29,(29 + 16)*REGSIZE(sp) + SFREG f30,(30 + 16)*REGSIZE(sp) + SFREG f31,(31 + 16)*REGSIZE(sp) +#endif + call handleInterrupt +#ifdef __riscv_flen + LFREG f0, (31 + 16)*REGSIZE(sp) + LFREG f1, (30 + 16)*REGSIZE(sp) + LFREG f2, (29 + 16)*REGSIZE(sp) + LFREG f3, (28 + 16)*REGSIZE(sp) + LFREG f4, (27 + 16)*REGSIZE(sp) + LFREG f5, (26 + 16)*REGSIZE(sp) + LFREG f6, (25 + 16)*REGSIZE(sp) + LFREG f7, (24 + 16)*REGSIZE(sp) + LFREG f8, (23 + 16)*REGSIZE(sp) + LFREG f9, (22 + 16)*REGSIZE(sp) + LFREG f10,(21 + 16)*REGSIZE(sp) + LFREG f11,(20 + 16)*REGSIZE(sp) + LFREG f12,(19 + 16)*REGSIZE(sp) + LFREG f13,(18 + 16)*REGSIZE(sp) + LFREG f14,(17 + 16)*REGSIZE(sp) + LFREG f15,(16 + 16)*REGSIZE(sp) + LFREG f16,(15 + 16)*REGSIZE(sp) + LFREG f17,(14 + 16)*REGSIZE(sp) + LFREG f18,(13 + 16)*REGSIZE(sp) + LFREG f19,(12 + 16)*REGSIZE(sp) + LFREG f20,(11 + 16)*REGSIZE(sp) + LFREG f21,(10 + 16)*REGSIZE(sp) + LFREG f22,(9 + 16)*REGSIZE(sp) + LFREG f23,(8 + 16)*REGSIZE(sp) + LFREG f24,(7 + 16)*REGSIZE(sp) + LFREG f25,(6 + 16)*REGSIZE(sp) + LFREG f26,(5 + 16)*REGSIZE(sp) + LFREG f27,(4 + 16)*REGSIZE(sp) + LFREG f28,(3 + 16)*REGSIZE(sp) + LFREG f29,(2 + 16)*REGSIZE(sp) + LFREG f30,(1 + 16)*REGSIZE(sp) + LFREG f31,(0 + 16)*REGSIZE(sp) +#endif + LREG t6, 15*REGSIZE(sp) + LREG t5, 14*REGSIZE(sp) + LREG t4, 13*REGSIZE(sp) + LREG t3, 12*REGSIZE(sp) + LREG a7, 11*REGSIZE(sp) + LREG a6, 10*REGSIZE(sp) + LREG a5, 9*REGSIZE(sp) + LREG a4, 8*REGSIZE(sp) + LREG a3, 7*REGSIZE(sp) + LREG a2, 6*REGSIZE(sp) + LREG a1, 5*REGSIZE(sp) + LREG a0, 4*REGSIZE(sp) + LREG t2, 3*REGSIZE(sp) + LREG t1, 2*REGSIZE(sp) + LREG t0, 1*REGSIZE(sp) + LREG ra, 0*REGSIZE(sp) + addi sp, sp, NREG*REGSIZE + mret diff --git a/emb/device/riscv/riscv.go b/emb/device/riscv/riscv.go new file mode 100644 index 0000000..1c3c3e6 --- /dev/null +++ b/emb/device/riscv/riscv.go @@ -0,0 +1,38 @@ +package riscv + +// Run the given assembly code. The code will be marked as having side effects, +// as it doesn't produce output and thus would normally be eliminated by the +// optimizer. +func Asm(asm string) + +// Run the given inline assembly. The code will be marked as having side +// effects, as it would otherwise be optimized away. The inline assembly string +// recognizes template values in the form {name}, like so: +// +// arm.AsmFull( +// "st {value}, {result}", +// map[string]interface{}{ +// "value": 1 +// "result": &dest, +// }) +// +// You can use {} in the asm string (which expands to a register) to set the +// return value. +func AsmFull(asm string, regs map[string]interface{}) uintptr + +// DisableInterrupts disables all interrupts, and returns the old interrupt +// state. +func DisableInterrupts() uintptr { + // Note: this can be optimized with a CSRRW instruction, which atomically + // swaps the value and returns the old value. + mask := MSTATUS.Get() + MSTATUS.ClearBits(1 << 3) // clear the MIE bit + return mask +} + +// EnableInterrupts enables all interrupts again. The value passed in must be +// the mask returned by DisableInterrupts. +func EnableInterrupts(mask uintptr) { + mask &= 1 << 3 // clear all bits except for the MIE bit + MSTATUS.SetBits(mask) // set the MIE bit, if it was previously cleared +} diff --git a/emb/device/riscv/start.S b/emb/device/riscv/start.S new file mode 100644 index 0000000..d67d82d --- /dev/null +++ b/emb/device/riscv/start.S @@ -0,0 +1,59 @@ +.section .init +.global _start +.type _start,@function + +_start: + // If we're on a multicore system, we need to wait for hart 0 to wake us up. +#if TINYGO_CORES > 1 + csrr a0, mhartid + + // Hart 0 stack + bnez a0, 1f + la sp, _stack_top + +1: + // Hart 1 stack + li a1, 1 + bne a0, a1, 2f + la sp, _stack1_top + +2: + // Hart 2 stack + #if TINYGO_CORES >= 3 + li a1, 2 + bne a0, a1, 3f + la sp, _stack2_top + #endif + +3: + // Hart 3 stack + #if TINYGO_CORES >= 4 + li a1, 3 + bne a0, a1, 4f + la sp, _stack3_top + #endif + +4: + // done + +#if TINYGO_CORES > 4 +#error only up to 4 cores are supported at the moment! +#endif + +#else + // Load the stack pointer. + la sp, _stack_top +#endif + + // Load the globals pointer. The program will load pointers relative to this + // register, so it must be set to the right value on startup. + // See: https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register + // Linker relaxations must be disabled to avoid the initialization beign + // relaxed with an uninitialized global pointer: mv gp, gp + .option push + .option norelax + la gp, __global_pointer$ + .option pop + + // Jump to runtime.main + call main From bfd519e6f5f16e84e3516be9f36c94a50741c7eb Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Wed, 10 Sep 2025 23:09:53 +0800 Subject: [PATCH 04/10] lib/runtime volatile --- emb/device/arm/arm.go | 2 +- emb/device/arm/scb.go | 2 +- emb/device/esp/esp32.go | 2 +- emb/device/esp/esp32c2.go | 2 +- emb/device/esp/esp32c3.go | 2 +- emb/device/esp/esp32c6.go | 2 +- emb/device/esp/esp32c6lp.go | 2 +- emb/device/esp/esp32h2.go | 2 +- emb/device/esp/esp32p4.go | 2 +- emb/device/esp/esp32s2.go | 2 +- emb/device/esp/esp32s2ulp.go | 2 +- emb/device/esp/esp32s3.go | 2 +- emb/device/esp/esp32s3ulp.go | 2 +- emb/device/esp/esp8266.go | 2 +- emb/machine/_usb/adc/midi/buffer.go | 2 +- emb/machine/_usb/cdc/buffer.go | 2 +- emb/machine/_usb/descriptor/descriptor.go | 2 +- emb/machine/_usb/hid/buffer.go | 2 +- emb/machine/machine_esp32.go | 2 +- emb/machine/machine_esp32_i2c.go | 2 +- emb/machine/machine_esp32c3.go | 2 +- emb/machine/machine_esp32c3_i2c.go | 2 +- emb/machine/machine_esp32c3_spi.go | 2 +- emb/machine/machine_esp8266.go | 2 +- emb/machine/serial-rtt.go | 2 +- 25 files changed, 25 insertions(+), 25 deletions(-) diff --git a/emb/device/arm/arm.go b/emb/device/arm/arm.go index 1f26b7f..144e162 100644 --- a/emb/device/arm/arm.go +++ b/emb/device/arm/arm.go @@ -32,7 +32,7 @@ package arm import "C" import ( "errors" - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/arm/scb.go b/emb/device/arm/scb.go index 528b7cb..094620c 100644 --- a/emb/device/arm/scb.go +++ b/emb/device/arm/scb.go @@ -6,7 +6,7 @@ package arm import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32.go b/emb/device/esp/esp32.go index 381c6cd..1d87e54 100644 --- a/emb/device/esp/esp32.go +++ b/emb/device/esp/esp32.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32c2.go b/emb/device/esp/esp32c2.go index 74a4181..4fb18fa 100644 --- a/emb/device/esp/esp32c2.go +++ b/emb/device/esp/esp32c2.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32c3.go b/emb/device/esp/esp32c3.go index fd94177..667040b 100644 --- a/emb/device/esp/esp32c3.go +++ b/emb/device/esp/esp32c3.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32c6.go b/emb/device/esp/esp32c6.go index 0542017..6105c7c 100644 --- a/emb/device/esp/esp32c6.go +++ b/emb/device/esp/esp32c6.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32c6lp.go b/emb/device/esp/esp32c6lp.go index a19db04..5825db4 100644 --- a/emb/device/esp/esp32c6lp.go +++ b/emb/device/esp/esp32c6lp.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32h2.go b/emb/device/esp/esp32h2.go index e565c86..406cf88 100644 --- a/emb/device/esp/esp32h2.go +++ b/emb/device/esp/esp32h2.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32p4.go b/emb/device/esp/esp32p4.go index 62d3385..ed13981 100644 --- a/emb/device/esp/esp32p4.go +++ b/emb/device/esp/esp32p4.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32s2.go b/emb/device/esp/esp32s2.go index 3d72984..7db3b61 100644 --- a/emb/device/esp/esp32s2.go +++ b/emb/device/esp/esp32s2.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32s2ulp.go b/emb/device/esp/esp32s2ulp.go index 9d53590..6639eb5 100644 --- a/emb/device/esp/esp32s2ulp.go +++ b/emb/device/esp/esp32s2ulp.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32s3.go b/emb/device/esp/esp32s3.go index 054c0fe..5240ada 100644 --- a/emb/device/esp/esp32s3.go +++ b/emb/device/esp/esp32s3.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp32s3ulp.go b/emb/device/esp/esp32s3ulp.go index b2421fb..c801513 100644 --- a/emb/device/esp/esp32s3ulp.go +++ b/emb/device/esp/esp32s3ulp.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/device/esp/esp8266.go b/emb/device/esp/esp8266.go index d07a842..196baec 100644 --- a/emb/device/esp/esp8266.go +++ b/emb/device/esp/esp8266.go @@ -10,7 +10,7 @@ package esp import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/machine/_usb/adc/midi/buffer.go b/emb/machine/_usb/adc/midi/buffer.go index 39cab2c..0ffefe5 100644 --- a/emb/machine/_usb/adc/midi/buffer.go +++ b/emb/machine/_usb/adc/midi/buffer.go @@ -1,7 +1,7 @@ package midi import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" ) const bufferSize = 128 diff --git a/emb/machine/_usb/cdc/buffer.go b/emb/machine/_usb/cdc/buffer.go index ad5eb36..b34df9d 100644 --- a/emb/machine/_usb/cdc/buffer.go +++ b/emb/machine/_usb/cdc/buffer.go @@ -1,7 +1,7 @@ package cdc import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" ) const rxRingBufferSize = 128 diff --git a/emb/machine/_usb/descriptor/descriptor.go b/emb/machine/_usb/descriptor/descriptor.go index 852ddab..ec60719 100644 --- a/emb/machine/_usb/descriptor/descriptor.go +++ b/emb/machine/_usb/descriptor/descriptor.go @@ -1,7 +1,7 @@ package descriptor import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" ) const ( diff --git a/emb/machine/_usb/hid/buffer.go b/emb/machine/_usb/hid/buffer.go index 2674bbd..3bcf60a 100644 --- a/emb/machine/_usb/hid/buffer.go +++ b/emb/machine/_usb/hid/buffer.go @@ -1,7 +1,7 @@ package hid import ( - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" ) const bufferSize = 128 diff --git a/emb/machine/machine_esp32.go b/emb/machine/machine_esp32.go index 237a129..abc09f0 100644 --- a/emb/machine/machine_esp32.go +++ b/emb/machine/machine_esp32.go @@ -5,7 +5,7 @@ package machine import ( "device/esp" "errors" - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/machine/machine_esp32_i2c.go b/emb/machine/machine_esp32_i2c.go index 746e722..b71bbad 100644 --- a/emb/machine/machine_esp32_i2c.go +++ b/emb/machine/machine_esp32_i2c.go @@ -4,7 +4,7 @@ package machine import ( "device/esp" - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/machine/machine_esp32c3.go b/emb/machine/machine_esp32c3.go index 727fcc1..a3d5d25 100644 --- a/emb/machine/machine_esp32c3.go +++ b/emb/machine/machine_esp32c3.go @@ -7,7 +7,7 @@ import ( "device/riscv" "errors" "runtime/interrupt" - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "sync" "unsafe" ) diff --git a/emb/machine/machine_esp32c3_i2c.go b/emb/machine/machine_esp32c3_i2c.go index dd334b0..10bba57 100644 --- a/emb/machine/machine_esp32c3_i2c.go +++ b/emb/machine/machine_esp32c3_i2c.go @@ -4,7 +4,7 @@ package machine import ( "device/esp" - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/machine/machine_esp32c3_spi.go b/emb/machine/machine_esp32c3_spi.go index aec3ca7..f6fc7fd 100644 --- a/emb/machine/machine_esp32c3_spi.go +++ b/emb/machine/machine_esp32c3_spi.go @@ -11,7 +11,7 @@ package machine import ( "device/esp" "errors" - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/machine/machine_esp8266.go b/emb/machine/machine_esp8266.go index 4edd4a5..24beae9 100644 --- a/emb/machine/machine_esp8266.go +++ b/emb/machine/machine_esp8266.go @@ -4,7 +4,7 @@ package machine import ( "device/esp" - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" ) const deviceName = esp.Device diff --git a/emb/machine/serial-rtt.go b/emb/machine/serial-rtt.go index 15f6463..48c0432 100644 --- a/emb/machine/serial-rtt.go +++ b/emb/machine/serial-rtt.go @@ -11,7 +11,7 @@ package machine import ( "runtime/interrupt" - "runtime/volatile" + "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) From 0a17a10e18c2ac931bc53fccae23f74a657989e5 Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Wed, 10 Sep 2025 23:19:38 +0800 Subject: [PATCH 05/10] github.com/goplus/lib/emb/device/esp --- emb/device/arm/arm.go | 3 ++- emb/machine/machine_esp32.go | 2 +- emb/machine/machine_esp32_i2c.go | 2 +- emb/machine/machine_esp32c3.go | 4 ++-- emb/machine/machine_esp32c3_i2c.go | 2 +- emb/machine/machine_esp32c3_spi.go | 2 +- emb/machine/machine_esp8266.go | 2 +- 7 files changed, 9 insertions(+), 8 deletions(-) diff --git a/emb/device/arm/arm.go b/emb/device/arm/arm.go index 144e162..bee97f6 100644 --- a/emb/device/arm/arm.go +++ b/emb/device/arm/arm.go @@ -32,8 +32,9 @@ package arm import "C" import ( "errors" - "github.com/goplus/lib/emb/runtime/volatile" "unsafe" + + "github.com/goplus/lib/emb/runtime/volatile" ) var errCycleCountTooLarge = errors.New("requested cycle count is too large, overflows 24 bit counter") diff --git a/emb/machine/machine_esp32.go b/emb/machine/machine_esp32.go index abc09f0..06348af 100644 --- a/emb/machine/machine_esp32.go +++ b/emb/machine/machine_esp32.go @@ -3,7 +3,7 @@ package machine import ( - "device/esp" + "github.com/goplus/lib/emb/device/esp" "errors" "github.com/goplus/lib/emb/runtime/volatile" "unsafe" diff --git a/emb/machine/machine_esp32_i2c.go b/emb/machine/machine_esp32_i2c.go index b71bbad..462832c 100644 --- a/emb/machine/machine_esp32_i2c.go +++ b/emb/machine/machine_esp32_i2c.go @@ -3,7 +3,7 @@ package machine import ( - "device/esp" + "github.com/goplus/lib/emb/device/esp" "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/machine/machine_esp32c3.go b/emb/machine/machine_esp32c3.go index a3d5d25..8f999db 100644 --- a/emb/machine/machine_esp32c3.go +++ b/emb/machine/machine_esp32c3.go @@ -3,8 +3,8 @@ package machine import ( - "device/esp" - "device/riscv" + "github.com/goplus/lib/emb/device/esp" + "github.com/goplus/lib/emb/device/riscv" "errors" "runtime/interrupt" "github.com/goplus/lib/emb/runtime/volatile" diff --git a/emb/machine/machine_esp32c3_i2c.go b/emb/machine/machine_esp32c3_i2c.go index 10bba57..3c148e5 100644 --- a/emb/machine/machine_esp32c3_i2c.go +++ b/emb/machine/machine_esp32c3_i2c.go @@ -3,7 +3,7 @@ package machine import ( - "device/esp" + "github.com/goplus/lib/emb/device/esp" "github.com/goplus/lib/emb/runtime/volatile" "unsafe" ) diff --git a/emb/machine/machine_esp32c3_spi.go b/emb/machine/machine_esp32c3_spi.go index f6fc7fd..1785f9d 100644 --- a/emb/machine/machine_esp32c3_spi.go +++ b/emb/machine/machine_esp32c3_spi.go @@ -9,7 +9,7 @@ package machine // https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/api-reference/peripherals/spi_master.html import ( - "device/esp" + "github.com/goplus/lib/emb/device/esp" "errors" "github.com/goplus/lib/emb/runtime/volatile" "unsafe" diff --git a/emb/machine/machine_esp8266.go b/emb/machine/machine_esp8266.go index 24beae9..d634cf2 100644 --- a/emb/machine/machine_esp8266.go +++ b/emb/machine/machine_esp8266.go @@ -3,7 +3,7 @@ package machine import ( - "device/esp" + "github.com/goplus/lib/emb/device/esp" "github.com/goplus/lib/emb/runtime/volatile" ) From 12795ea919dc2465fb48017952b822ab9528ce72 Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Wed, 10 Sep 2025 23:35:32 +0800 Subject: [PATCH 06/10] buffer size --- emb/machine/buffer_generic.go | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 emb/machine/buffer_generic.go diff --git a/emb/machine/buffer_generic.go b/emb/machine/buffer_generic.go new file mode 100644 index 0000000..49e723b --- /dev/null +++ b/emb/machine/buffer_generic.go @@ -0,0 +1,5 @@ +//go:build !atmega + +package machine + +const bufferSize = 128 \ No newline at end of file From 54ee452f2ee1790062fde65264c2fa875c109ad8 Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Fri, 12 Sep 2025 11:55:49 +0800 Subject: [PATCH 07/10] demo --- demo/esp/main.go | 31 +++++++++++++++++++++++++++++++ emb/device/esp/esp32c2.go | 3 ++- emb/machine/machine_esp32_i2c.go | 3 ++- emb/runtime/volatile/volatile.go | 2 +- 4 files changed, 36 insertions(+), 3 deletions(-) create mode 100644 demo/esp/main.go diff --git a/demo/esp/main.go b/demo/esp/main.go new file mode 100644 index 0000000..75ddfd4 --- /dev/null +++ b/demo/esp/main.go @@ -0,0 +1,31 @@ +package main + +import ( + "unsafe" + + "github.com/goplus/lib/emb/machine" +) + +//go:linkname StoreUint32 llgo.atomicStore +func StoreUint32(addr *uint32, val uint32) + +//go:linkname sleep sleep +func sleep(tm int) + +func main() { + StoreUint32((*uint32)(unsafe.Pointer(uintptr(0x3ff480A4))), 0x50D83AA1) + + StoreUint32((*uint32)(unsafe.Pointer(uintptr(0x3ff4808C))), 0) + StoreUint32((*uint32)(unsafe.Pointer(uintptr(0x3ff5f048))), 0) + buttonPin := machine.GPIO34 + buttonPin.Configure(machine.PinConfig{Mode: machine.PinInput}) + for { + sleep(10) + buttonState := buttonPin.Get() + if buttonState { + println(buttonState) + } + // println(buttonState) + // time.Sleep(200 * time.Millisecond) + } +} diff --git a/emb/device/esp/esp32c2.go b/emb/device/esp/esp32c2.go index 4fb18fa..62448ea 100644 --- a/emb/device/esp/esp32c2.go +++ b/emb/device/esp/esp32c2.go @@ -10,8 +10,9 @@ package esp import ( - "github.com/goplus/lib/emb/runtime/volatile" "unsafe" + + "github.com/goplus/lib/emb/runtime/volatile" ) // Some information about this device. diff --git a/emb/machine/machine_esp32_i2c.go b/emb/machine/machine_esp32_i2c.go index 462832c..68990a8 100644 --- a/emb/machine/machine_esp32_i2c.go +++ b/emb/machine/machine_esp32_i2c.go @@ -3,9 +3,10 @@ package machine import ( + "unsafe" + "github.com/goplus/lib/emb/device/esp" "github.com/goplus/lib/emb/runtime/volatile" - "unsafe" ) var ( diff --git a/emb/runtime/volatile/volatile.go b/emb/runtime/volatile/volatile.go index ead2e7d..b96248e 100644 --- a/emb/runtime/volatile/volatile.go +++ b/emb/runtime/volatile/volatile.go @@ -18,7 +18,7 @@ package volatile import _ "unsafe" const ( - LLGoPackage = "decl" + LLGoPackage = "link" ) // LoadUint8 loads the volatile value *addr. From 2f28bc305536af5678793fcfbe48460cbe80103e Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Fri, 12 Sep 2025 13:42:11 +0800 Subject: [PATCH 08/10] llgo.asm --- emb/device/arm64/arm64.go | 8 ++++++-- emb/device/asm.go | 8 ++++++-- emb/device/riscv/riscv.go | 8 ++++++-- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/emb/device/arm64/arm64.go b/emb/device/arm64/arm64.go index 7e8cea6..cd6442e 100644 --- a/emb/device/arm64/arm64.go +++ b/emb/device/arm64/arm64.go @@ -3,7 +3,9 @@ package arm64 // Run the given assembly code. The code will be marked as having side effects, // as it doesn't produce output and thus would normally be eliminated by the // optimizer. -func Asm(asm string) +// +//llgo:link asmFull llgo.asm +func Asm(asm string) {} // Run the given inline assembly. The code will be marked as having side // effects, as it would otherwise be optimized away. The inline assembly string @@ -18,7 +20,9 @@ func Asm(asm string) // // You can use {} in the asm string (which expands to a register) to set the // return value. -func AsmFull(asm string, regs map[string]interface{}) uintptr +// +//llgo:link asmFull llgo.asm +func AsmFull(asm string, regs map[string]interface{}) uintptr { return 0 } // Run the following system call (SVCall) with 0 arguments. func SVCall0(num uintptr) uintptr diff --git a/emb/device/asm.go b/emb/device/asm.go index 49ddbc3..7edf121 100644 --- a/emb/device/asm.go +++ b/emb/device/asm.go @@ -3,7 +3,9 @@ package device // Run the given assembly code. The code will be marked as having side effects, // as it doesn't produce output and thus would normally be eliminated by the // optimizer. -func Asm(asm string) +// +//llgo:link asmFull llgo.asm +func Asm(asm string) {} // Run the given inline assembly. The code will be marked as having side // effects, as it would otherwise be optimized away. The inline assembly string @@ -18,4 +20,6 @@ func Asm(asm string) // // You can use {} in the asm string (which expands to a register) to set the // return value. -func AsmFull(asm string, regs map[string]interface{}) uintptr +// +//llgo:link asmFull llgo.asm +func AsmFull(asm string, regs map[string]interface{}) uintptr { return 0 } diff --git a/emb/device/riscv/riscv.go b/emb/device/riscv/riscv.go index 1c3c3e6..787d782 100644 --- a/emb/device/riscv/riscv.go +++ b/emb/device/riscv/riscv.go @@ -3,7 +3,9 @@ package riscv // Run the given assembly code. The code will be marked as having side effects, // as it doesn't produce output and thus would normally be eliminated by the // optimizer. -func Asm(asm string) +// +//llgo:link asmFull llgo.asm +func Asm(asm string) {} // Run the given inline assembly. The code will be marked as having side // effects, as it would otherwise be optimized away. The inline assembly string @@ -18,7 +20,9 @@ func Asm(asm string) // // You can use {} in the asm string (which expands to a register) to set the // return value. -func AsmFull(asm string, regs map[string]interface{}) uintptr +// +//llgo:link asmFull llgo.asm +func AsmFull(asm string, regs map[string]interface{}) uintptr { return 0 } // DisableInterrupts disables all interrupts, and returns the old interrupt // state. From 40f3d7ebded752222792613569a41709c97c8ec8 Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Fri, 12 Sep 2025 13:48:04 +0800 Subject: [PATCH 09/10] remove device's asm code --- {demo => _demo}/esp/main.go | 17 ++-- emb/device/arm/cortexm.S | 37 -------- emb/device/arm/interrupts.c | 22 ----- emb/device/esp/esp32.S | 57 ------------- emb/device/esp/esp32c3.S | 67 --------------- emb/device/esp/esp8266.S | 6 -- emb/device/riscv/handleinterrupt.S | 130 ----------------------------- emb/device/riscv/start.S | 59 ------------- 8 files changed, 5 insertions(+), 390 deletions(-) rename {demo => _demo}/esp/main.go (69%) delete mode 100644 emb/device/arm/cortexm.S delete mode 100644 emb/device/arm/interrupts.c delete mode 100644 emb/device/esp/esp32.S delete mode 100644 emb/device/esp/esp32c3.S delete mode 100644 emb/device/esp/esp8266.S delete mode 100644 emb/device/riscv/handleinterrupt.S delete mode 100644 emb/device/riscv/start.S diff --git a/demo/esp/main.go b/_demo/esp/main.go similarity index 69% rename from demo/esp/main.go rename to _demo/esp/main.go index 75ddfd4..b8b4a3c 100644 --- a/demo/esp/main.go +++ b/_demo/esp/main.go @@ -2,8 +2,6 @@ package main import ( "unsafe" - - "github.com/goplus/lib/emb/machine" ) //go:linkname StoreUint32 llgo.atomicStore @@ -14,18 +12,13 @@ func sleep(tm int) func main() { StoreUint32((*uint32)(unsafe.Pointer(uintptr(0x3ff480A4))), 0x50D83AA1) - StoreUint32((*uint32)(unsafe.Pointer(uintptr(0x3ff4808C))), 0) StoreUint32((*uint32)(unsafe.Pointer(uintptr(0x3ff5f048))), 0) buttonPin := machine.GPIO34 buttonPin.Configure(machine.PinConfig{Mode: machine.PinInput}) - for { - sleep(10) - buttonState := buttonPin.Get() - if buttonState { - println(buttonState) - } - // println(buttonState) - // time.Sleep(200 * time.Millisecond) - } + println(buttonPin.Get()) + sleep(2) + println(buttonPin.Get()) + println(buttonState) + // time.Sleep(200 * time.Millisecond) } diff --git a/emb/device/arm/cortexm.S b/emb/device/arm/cortexm.S deleted file mode 100644 index e9b15aa..0000000 --- a/emb/device/arm/cortexm.S +++ /dev/null @@ -1,37 +0,0 @@ -.syntax unified -.cfi_sections .debug_frame - -.section .text.HardFault_Handler -.global HardFault_Handler -.type HardFault_Handler, %function -HardFault_Handler: - .cfi_startproc - // Put the old stack pointer in the first argument, for easy debugging. This - // is especially useful on Cortex-M0, which supports far fewer debug - // facilities. - mov r0, sp - - // Load the default stack pointer from address 0 so that we can call normal - // functions again that expect a working stack. However, it will corrupt the - // old stack so the function below must not attempt to recover from this - // fault. - movs r3, #0 - ldr r3, [r3] - mov sp, r3 - - // Continue handling this error in Go. - bl handleHardFault - .cfi_endproc -.size HardFault_Handler, .-HardFault_Handler - -// This is a convenience function for semihosting support. -// At some point, this should be replaced by inline assembly. -.section .text.SemihostingCall -.global SemihostingCall -.type SemihostingCall, %function -SemihostingCall: - .cfi_startproc - bkpt 0xab - bx lr - .cfi_endproc -.size SemihostingCall, .-SemihostingCall diff --git a/emb/device/arm/interrupts.c b/emb/device/arm/interrupts.c deleted file mode 100644 index d94a313..0000000 --- a/emb/device/arm/interrupts.c +++ /dev/null @@ -1,22 +0,0 @@ -#include - -void EnableInterrupts(uintptr_t mask) { - asm volatile( - "msr PRIMASK, %0" - : - : "r"(mask) - : "memory" - ); -} - -uintptr_t DisableInterrupts() { - uintptr_t mask; - asm volatile( - "mrs %0, PRIMASK\n\t" - "cpsid i" - : "=r"(mask) - : - : "memory" - ); - return mask; -} \ No newline at end of file diff --git a/emb/device/esp/esp32.S b/emb/device/esp/esp32.S deleted file mode 100644 index 1179a2d..0000000 --- a/emb/device/esp/esp32.S +++ /dev/null @@ -1,57 +0,0 @@ - -// The following definitions were copied from: -// esp-idf/components/xtensa/include/xtensa/corebits.h -#define PS_WOE_MASK 0x00040000 -#define PS_OWB_MASK 0x00000F00 -#define PS_CALLINC_MASK 0x00030000 -#define PS_WOE PS_WOE_MASK - -// Only calling it call_start_cpu0 for consistency with ESP-IDF. -.section .text.call_start_cpu0 -1: - .long _stack_top -.global call_start_cpu0 -call_start_cpu0: - // We need to set the stack pointer to a different value. This is somewhat - // complicated in the Xtensa architecture. The code below is a modified - // version of the following code: - // https://github.com/espressif/esp-idf/blob/c77c4ccf/components/xtensa/include/xt_instr_macros.h#L47 - - // Disable WOE. - rsr.ps a2 - movi a3, ~(PS_WOE_MASK) - and a2, a2, a3 - wsr.ps a2 - rsync - - // Set WINDOWSTART to 1 << WINDOWBASE. - rsr.windowbase a2 - ssl a2 - movi a2, 1 - sll a2, a2 - wsr.windowstart a2 - rsync - - // Load new stack pointer. - l32r sp, 1b - - // Re-enable WOE. - rsr.ps a2 - movi a3, PS_WOE - or a2, a2, a3 - wsr.ps a2 - rsync - - // Enable the FPU (coprocessor 0 so the lowest bit). - movi a2, 1 - wsr.cpenable a2 - rsync - - // Jump to the runtime start function written in Go. - call4 main - -.section .text.tinygo_scanCurrentStack -.global tinygo_scanCurrentStack -tinygo_scanCurrentStack: - // TODO: save callee saved registers on the stack - j tinygo_scanstack diff --git a/emb/device/esp/esp32c3.S b/emb/device/esp/esp32c3.S deleted file mode 100644 index 0395d73..0000000 --- a/emb/device/esp/esp32c3.S +++ /dev/null @@ -1,67 +0,0 @@ -// This is a very minimal bootloader for the ESP32-C3. It only initializes the -// flash and then continues with the generic RISC-V initialization code, which -// in turn will call runtime.main. -// It is written in assembly (and not in a higher level language) to make sure -// it is entirely loaded into IRAM and doesn't accidentally call functions -// stored in IROM. -// -// For reference, here is a nice introduction into RISC-V assembly: -// https://www.imperialviolet.org/2016/12/31/riscv.html - -.section .init -.global call_start_cpu0 -.type call_start_cpu0,@function -call_start_cpu0: - // At this point: - // - The ROM bootloader is finished and has jumped to here. - // - We're running from IRAM: both IRAM and DRAM segments have been loaded - // by the ROM bootloader. - // - We have a usable stack (but not the one we would like to use). - // - No flash mappings (MMU) are set up yet. - - // Reset MMU, see bootloader_reset_mmu in the ESP-IDF. - call Cache_Suspend_ICache - mv s0, a0 // autoload value - call Cache_Invalidate_ICache_All - call Cache_MMU_Init - - // Set up DROM from flash. - // Somehow, this also sets up IROM from flash. Not sure why, but it avoids - // the need for another such call. - // C equivalent: - // Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, 0x3C00_0000, 0, 64, 128, 0) - li a0, 0 // ext_ram: MMU_ACCESS_FLASH - li a1, 0x3C000000 // vaddr: address in the data bus - li a2, 0 // paddr: physical address in the flash chip - li a3, 64 // psize: always 64 (kilobytes) - li a4, 128 // num: pages to be set (8192K / 64K = 128) - li a5, 0 // fixed - call Cache_Dbus_MMU_Set - - // Enable the flash cache. - mv a0, s0 // restore autoload value from Cache_Suspend_ICache call - call Cache_Resume_ICache - - // Jump to generic RISC-V initialization, which initializes the stack - // pointer and globals register. It should not return. - // (It appears that the linker relaxes this jump and instead inserts the - // _start function right after here). - j _start - -.section .text.exception_vectors -.global _vector_table -.type _vector_table,@function - -_vector_table: - - .option push - .option norvc - - .rept 32 - j handleInterruptASM /* interrupt handler */ - .endr - - .option pop - -.size _vector_table, .-_vector_table - diff --git a/emb/device/esp/esp8266.S b/emb/device/esp/esp8266.S deleted file mode 100644 index cffa503..0000000 --- a/emb/device/esp/esp8266.S +++ /dev/null @@ -1,6 +0,0 @@ - -.section .text.tinygo_scanCurrentStack -.global tinygo_scanCurrentStack -tinygo_scanCurrentStack: - // TODO: save callee saved registers on the stack - j tinygo_scanstack diff --git a/emb/device/riscv/handleinterrupt.S b/emb/device/riscv/handleinterrupt.S deleted file mode 100644 index c206c01..0000000 --- a/emb/device/riscv/handleinterrupt.S +++ /dev/null @@ -1,130 +0,0 @@ -#ifdef __riscv_flen -#define NREG 48 -#define LFREG flw -#define SFREG fsw -#else -#define NREG 16 -#endif - -#if __riscv_xlen==64 -#define REGSIZE 8 -#define SREG sd -#define LREG ld -#else -#define REGSIZE 4 -#define SREG sw -#define LREG lw -#endif - -.section .text.handleInterruptASM -.global handleInterruptASM -.type handleInterruptASM,@function -handleInterruptASM: - // Save and restore all registers, because the hardware only saves/restores - // the pc. - // Note: we have to do this in assembly because the "interrupt"="machine" - // attribute is broken in LLVM: https://bugs.llvm.org/show_bug.cgi?id=42984 - addi sp, sp, -NREG*REGSIZE - SREG ra, 0*REGSIZE(sp) - SREG t0, 1*REGSIZE(sp) - SREG t1, 2*REGSIZE(sp) - SREG t2, 3*REGSIZE(sp) - SREG a0, 4*REGSIZE(sp) - SREG a1, 5*REGSIZE(sp) - SREG a2, 6*REGSIZE(sp) - SREG a3, 7*REGSIZE(sp) - SREG a4, 8*REGSIZE(sp) - SREG a5, 9*REGSIZE(sp) - SREG a6, 10*REGSIZE(sp) - SREG a7, 11*REGSIZE(sp) - SREG t3, 12*REGSIZE(sp) - SREG t4, 13*REGSIZE(sp) - SREG t5, 14*REGSIZE(sp) - SREG t6, 15*REGSIZE(sp) -#ifdef __riscv_flen - SFREG f0, (0 + 16)*REGSIZE(sp) - SFREG f1, (1 + 16)*REGSIZE(sp) - SFREG f2, (2 + 16)*REGSIZE(sp) - SFREG f3, (3 + 16)*REGSIZE(sp) - SFREG f4, (4 + 16)*REGSIZE(sp) - SFREG f5, (5 + 16)*REGSIZE(sp) - SFREG f6, (6 + 16)*REGSIZE(sp) - SFREG f7, (7 + 16)*REGSIZE(sp) - SFREG f8, (8 + 16)*REGSIZE(sp) - SFREG f9, (9 + 16)*REGSIZE(sp) - SFREG f10,(10 + 16)*REGSIZE(sp) - SFREG f11,(11 + 16)*REGSIZE(sp) - SFREG f12,(12 + 16)*REGSIZE(sp) - SFREG f13,(13 + 16)*REGSIZE(sp) - SFREG f14,(14 + 16)*REGSIZE(sp) - SFREG f15,(15 + 16)*REGSIZE(sp) - SFREG f16,(16 + 16)*REGSIZE(sp) - SFREG f17,(17 + 16)*REGSIZE(sp) - SFREG f18,(18 + 16)*REGSIZE(sp) - SFREG f19,(19 + 16)*REGSIZE(sp) - SFREG f20,(20 + 16)*REGSIZE(sp) - SFREG f21,(21 + 16)*REGSIZE(sp) - SFREG f22,(22 + 16)*REGSIZE(sp) - SFREG f23,(23 + 16)*REGSIZE(sp) - SFREG f24,(24 + 16)*REGSIZE(sp) - SFREG f25,(25 + 16)*REGSIZE(sp) - SFREG f26,(26 + 16)*REGSIZE(sp) - SFREG f27,(27 + 16)*REGSIZE(sp) - SFREG f28,(28 + 16)*REGSIZE(sp) - SFREG f29,(29 + 16)*REGSIZE(sp) - SFREG f30,(30 + 16)*REGSIZE(sp) - SFREG f31,(31 + 16)*REGSIZE(sp) -#endif - call handleInterrupt -#ifdef __riscv_flen - LFREG f0, (31 + 16)*REGSIZE(sp) - LFREG f1, (30 + 16)*REGSIZE(sp) - LFREG f2, (29 + 16)*REGSIZE(sp) - LFREG f3, (28 + 16)*REGSIZE(sp) - LFREG f4, (27 + 16)*REGSIZE(sp) - LFREG f5, (26 + 16)*REGSIZE(sp) - LFREG f6, (25 + 16)*REGSIZE(sp) - LFREG f7, (24 + 16)*REGSIZE(sp) - LFREG f8, (23 + 16)*REGSIZE(sp) - LFREG f9, (22 + 16)*REGSIZE(sp) - LFREG f10,(21 + 16)*REGSIZE(sp) - LFREG f11,(20 + 16)*REGSIZE(sp) - LFREG f12,(19 + 16)*REGSIZE(sp) - LFREG f13,(18 + 16)*REGSIZE(sp) - LFREG f14,(17 + 16)*REGSIZE(sp) - LFREG f15,(16 + 16)*REGSIZE(sp) - LFREG f16,(15 + 16)*REGSIZE(sp) - LFREG f17,(14 + 16)*REGSIZE(sp) - LFREG f18,(13 + 16)*REGSIZE(sp) - LFREG f19,(12 + 16)*REGSIZE(sp) - LFREG f20,(11 + 16)*REGSIZE(sp) - LFREG f21,(10 + 16)*REGSIZE(sp) - LFREG f22,(9 + 16)*REGSIZE(sp) - LFREG f23,(8 + 16)*REGSIZE(sp) - LFREG f24,(7 + 16)*REGSIZE(sp) - LFREG f25,(6 + 16)*REGSIZE(sp) - LFREG f26,(5 + 16)*REGSIZE(sp) - LFREG f27,(4 + 16)*REGSIZE(sp) - LFREG f28,(3 + 16)*REGSIZE(sp) - LFREG f29,(2 + 16)*REGSIZE(sp) - LFREG f30,(1 + 16)*REGSIZE(sp) - LFREG f31,(0 + 16)*REGSIZE(sp) -#endif - LREG t6, 15*REGSIZE(sp) - LREG t5, 14*REGSIZE(sp) - LREG t4, 13*REGSIZE(sp) - LREG t3, 12*REGSIZE(sp) - LREG a7, 11*REGSIZE(sp) - LREG a6, 10*REGSIZE(sp) - LREG a5, 9*REGSIZE(sp) - LREG a4, 8*REGSIZE(sp) - LREG a3, 7*REGSIZE(sp) - LREG a2, 6*REGSIZE(sp) - LREG a1, 5*REGSIZE(sp) - LREG a0, 4*REGSIZE(sp) - LREG t2, 3*REGSIZE(sp) - LREG t1, 2*REGSIZE(sp) - LREG t0, 1*REGSIZE(sp) - LREG ra, 0*REGSIZE(sp) - addi sp, sp, NREG*REGSIZE - mret diff --git a/emb/device/riscv/start.S b/emb/device/riscv/start.S deleted file mode 100644 index d67d82d..0000000 --- a/emb/device/riscv/start.S +++ /dev/null @@ -1,59 +0,0 @@ -.section .init -.global _start -.type _start,@function - -_start: - // If we're on a multicore system, we need to wait for hart 0 to wake us up. -#if TINYGO_CORES > 1 - csrr a0, mhartid - - // Hart 0 stack - bnez a0, 1f - la sp, _stack_top - -1: - // Hart 1 stack - li a1, 1 - bne a0, a1, 2f - la sp, _stack1_top - -2: - // Hart 2 stack - #if TINYGO_CORES >= 3 - li a1, 2 - bne a0, a1, 3f - la sp, _stack2_top - #endif - -3: - // Hart 3 stack - #if TINYGO_CORES >= 4 - li a1, 3 - bne a0, a1, 4f - la sp, _stack3_top - #endif - -4: - // done - -#if TINYGO_CORES > 4 -#error only up to 4 cores are supported at the moment! -#endif - -#else - // Load the stack pointer. - la sp, _stack_top -#endif - - // Load the globals pointer. The program will load pointers relative to this - // register, so it must be set to the right value on startup. - // See: https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register - // Linker relaxations must be disabled to avoid the initialization beign - // relaxed with an uninitialized global pointer: mv gp, gp - .option push - .option norelax - la gp, __global_pointer$ - .option pop - - // Jump to runtime.main - call main From aa5ba1ecf02d68b07cf3fe4578a023ee416c71d1 Mon Sep 17 00:00:00 2001 From: luoliwoshang <2643523683@qq.com> Date: Fri, 12 Sep 2025 15:54:50 +0800 Subject: [PATCH 10/10] update demo --- _demo/esp/main.go | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/_demo/esp/main.go b/_demo/esp/main.go index b8b4a3c..c91e429 100644 --- a/_demo/esp/main.go +++ b/_demo/esp/main.go @@ -2,13 +2,16 @@ package main import ( "unsafe" + _ "unsafe" + + "github.com/goplus/lib/emb/machine" ) //go:linkname StoreUint32 llgo.atomicStore func StoreUint32(addr *uint32, val uint32) //go:linkname sleep sleep -func sleep(tm int) +func sleep(n int) func main() { StoreUint32((*uint32)(unsafe.Pointer(uintptr(0x3ff480A4))), 0x50D83AA1) @@ -16,9 +19,13 @@ func main() { StoreUint32((*uint32)(unsafe.Pointer(uintptr(0x3ff5f048))), 0) buttonPin := machine.GPIO34 buttonPin.Configure(machine.PinConfig{Mode: machine.PinInput}) - println(buttonPin.Get()) - sleep(2) - println(buttonPin.Get()) - println(buttonState) - // time.Sleep(200 * time.Millisecond) + + for i := 0; i < 10; i++ { + if buttonPin.Get() { + println("yes") + } else { + println("no") + } + sleep(1) + } }